From 196a34e94b4b1f5d512135b5f966c47cd6421840 Mon Sep 17 00:00:00 2001 From: Federico Fissore Date: Tue, 13 Jan 2015 18:38:37 +0100 Subject: [PATCH] Introducing Atmel toolchain 3.4.5 --- .gitignore | 4 +- arch.arm.build.bash | 2 +- arch.linux32.build.bash | 2 +- arch.linux64.build.bash | 2 +- arch.mac32.build.bash | 2 +- arch.win32.build.bash | 2 +- .../00-avr-libc-1.8.0-atmel.patch | 946854 +++++++++++---- avr-libc.build.bash | 14 +- avrdude.build.bash | 2 +- binutils-patches/00-binutils-2.24-atmel.patch | 7841 +- binutils.build.bash | 4 +- clean.bash | 2 +- gcc-patches/00-gcc-4.8.1-atmel.patch | 1262 +- gcc.build.bash | 8 +- ...7.7-atmel.patch => 00-gdb-7.8-atmel.patch} | 94453 +- gdb.build.bash | 12 +- libusb.build.bash | 4 +- 17 files changed, 747587 insertions(+), 302883 deletions(-) rename gdb-patches/{00-gdb-7.7-atmel.patch => 00-gdb-7.8-atmel.patch} (98%) diff --git a/.gitignore b/.gitignore index 7562499..2d5b84a 100644 --- a/.gitignore +++ b/.gitignore @@ -1,6 +1,6 @@ .DS_Store *.bz2 -*.tar.gz +*.tar.* *.zip objdir toolsdir @@ -15,5 +15,5 @@ avrdude-5.11.1 avrdude-6.0.1 libusb-1.0.18 libusb-compat-0.1.5 -gdb-7.7 +gdb-7.8 tmp diff --git a/arch.arm.build.bash b/arch.arm.build.bash index 0cf8cf5..2c34729 100755 --- a/arch.arm.build.bash +++ b/arch.arm.build.bash @@ -4,5 +4,5 @@ rm -f avr-toolchain-*.zip cd objdir -zip -r -9 ../avr-toolchain-armv7l-3.4.4.zip . +zip -r -9 ../avr-toolchain-armv7l-3.4.5.zip . diff --git a/arch.linux32.build.bash b/arch.linux32.build.bash index 0e4cfed..29b1992 100755 --- a/arch.linux32.build.bash +++ b/arch.linux32.build.bash @@ -4,5 +4,5 @@ CC="gcc -m32" CXX="g++ -m32" ./build.all.bash rm -f avr-toolchain-*.zip cd objdir -zip -r -9 ../avr-toolchain-linux32-3.4.4.zip . +zip -r -9 ../avr-toolchain-linux32-3.4.5.zip . diff --git a/arch.linux64.build.bash b/arch.linux64.build.bash index c84f251..e027bc4 100755 --- a/arch.linux64.build.bash +++ b/arch.linux64.build.bash @@ -4,5 +4,5 @@ rm -f avr-toolchain-*.zip cd objdir -zip -r -9 ../avr-toolchain-linux64-3.4.4.zip . +zip -r -9 ../avr-toolchain-linux64-3.4.5.zip . diff --git a/arch.mac32.build.bash b/arch.mac32.build.bash index 667fafa..5e172a7 100755 --- a/arch.mac32.build.bash +++ b/arch.mac32.build.bash @@ -6,5 +6,5 @@ CC="gcc -arch i386 -mmacosx-version-min=10.5" CXX="g++ -arch i386 -mmacosx-versi rm -f avr-toolchain-*.zip cd objdir -zip -r -9 ../avr-toolchain-mac32-3.4.4.zip . +zip -r -9 ../avr-toolchain-mac32-3.4.5.zip . diff --git a/arch.win32.build.bash b/arch.win32.build.bash index 3c5e0f3..5f49ec3 100755 --- a/arch.win32.build.bash +++ b/arch.win32.build.bash @@ -9,5 +9,5 @@ for folder in avr/bin bin libexec/gcc/avr/4.8.1/ do cp /c/MinGW/bin/libiconv-2.dll $folder done -zip -r -9 ../avr-toolchain-win32-3.4.4.zip . +zip -r -9 ../avr-toolchain-win32-3.4.5.zip . diff --git a/avr-libc-patches/00-avr-libc-1.8.0-atmel.patch b/avr-libc-patches/00-avr-libc-1.8.0-atmel.patch index 83add51..c6f10d1 100644 --- a/avr-libc-patches/00-avr-libc-1.8.0-atmel.patch +++ b/avr-libc-patches/00-avr-libc-1.8.0-atmel.patch @@ -1,11 +1,10 @@ diff --git a/ChangeLog b/ChangeLog -index 9a55a33..38b3294 100644 +index 9a55a33..36865a9 100644 --- a/ChangeLog +++ b/ChangeLog -@@ -1,431 +1,13 @@ +@@ -1,431 +1,79 @@ -2011-12-29 Joerg Wunsch -+2013-01-27 Dmitry Xmelkov - +- - Released avr-libc-1.7.1. - * configure.ac: Bump version. - @@ -88,12 +87,8 @@ index 9a55a33..38b3294 100644 - - Fix for bug #33920. - * include/avr/iotn167.h (ICR): Define ICR to be a word register. -+ Fix for bug #37778: _MemoryBarrier() in cpufunc.h error on compile -+ * include/avr/cpufunc.h: Place empty string for asm body. This is -+ needed for older GCC versions. -+ * tests/simulate/regression/bug-37778.c: New file. - * NEWS: Add to fixed bug list. - +- * NEWS: Add to fixed bug list. +- -2011-09-22 Joerg Wunsch - - * configure.ac (avr_libc_revision, avr_libc_reldate): Bump in @@ -169,8 +164,80 @@ index 9a55a33..38b3294 100644 - - Fix for bug #32988. - * include/avr/pgmspace.h: Add const keyword to PSTR definition. -- * NEWS: Add to fixed bug list. -- ++2014-08-05 Senthil Kumar Selvaraj ++ ++ * include/avr/io1200.h: Add RAMSTART. ++ * include/avr/io2313.h: Likewise. ++ * include/avr/io2323.h: Likewise. ++ * include/avr/io2333.h: Likewise. ++ * include/avr/io2343.h: Likewise. ++ * include/avr/io43u32x.h: Likewise. ++ * include/avr/io43u35x.h: Likewise. ++ * include/avr/io4414.h: Likewise. ++ * include/avr/io4433.h: Likewise. ++ * include/avr/io4434.h: Likewise. ++ * include/avr/io76c711.h: Likewise. ++ * include/avr/io8515.h: Likewise. ++ * include/avr/io8534.h: Likewise. ++ * include/avr/io8535.h: Likewise. ++ * include/avr/io86r401.h: Likewise. ++ * include/avr/io90pwm216.h: Likewise. ++ * include/avr/io90pwm2b.h: Likewise. ++ * include/avr/io90pwm316.h: Likewise. ++ * include/avr/io90pwm3b.h: Likewise. ++ * include/avr/ioat94k.h: Likewise. ++ * include/avr/iocan128.h: Likewise. ++ * include/avr/iocan32.h: Likewise. ++ * include/avr/iocan64.h: Likewise. ++ * include/avr/iom103.h: Likewise. ++ * include/avr/iom128.h: Likewise. ++ * include/avr/iom1280.h: Likewise. ++ * include/avr/iom161.h: Likewise. ++ * include/avr/iom162.h: Likewise. ++ * include/avr/iom163.h: Likewise. ++ * include/avr/iom165.h: Likewise. ++ * include/avr/iom165p.h: Likewise. ++ * include/avr/iom169.h: Likewise. ++ * include/avr/iom169p.h: Likewise. ++ * include/avr/iom16hva.h: Likewise. ++ * include/avr/iom2560.h: Likewise. ++ * include/avr/iom2561.h: Likewise. ++ * include/avr/iom323.h: Likewise. ++ * include/avr/iom329.h: Likewise. ++ * include/avr/iom3290.h: Likewise. ++ * include/avr/iom32hvbrevb.h: Likewise. ++ * include/avr/iom406.h: Likewise. ++ * include/avr/iom64.h: Likewise. ++ * include/avr/iom640.h: Likewise. ++ * include/avr/iom649.h: Likewise. ++ * include/avr/iom6490.h: Likewise. ++ * include/avr/iom8hva.h: Likewise. ++ * include/avr/iotn11.h: Likewise. ++ * include/avr/iotn12.h: Likewise. ++ * include/avr/iotn15.h: Likewise. ++ * include/avr/iotn22.h: Likewise. ++ * include/avr/iotn26.h: Likewise. ++ * include/avr/iotn28.h: Likewise. ++ * include/avr/iotn43u.h: Likewise. ++ * include/avr/iousb1286.h: Likewise. ++ * include/avr/iousb1287.h: Likewise. ++ * include/avr/iousb162.h: Likewise. ++ * include/avr/iousb646.h: Likewise. ++ * include/avr/iousb647.h: Likewise. ++ * include/avr/iousb82.h: Likewise. ++ * include/avr/io90pwm1.h: Add RAMSTART and fix FLASHEND. ++ * include/avr/io90pwmx.h: Likewise. ++ * include/avr/iom3000.h: Add RAMSTART and fix RAMEND. ++ * include/avr/iotn167.h: Fix RAMSIZE. ++ ++2013-01-27 Dmitry Xmelkov ++ ++ Fix for bug #37778: _MemoryBarrier() in cpufunc.h error on compile ++ * include/avr/cpufunc.h: Place empty string for asm body. This is ++ needed for older GCC versions. ++ * tests/simulate/regression/bug-37778.c: New file. + * NEWS: Add to fixed bug list. + -2011-05-09 Eric B. Weddington - - Fix for bug #33230. @@ -1799,10 +1866,10 @@ index a0ec05c..7474e00 100644 EXTRA_DIST = \ diff --git a/NEWS b/NEWS -index 0e5dad4..19fed26 100644 +index 0e5dad4..5873ba4 100644 --- a/NEWS +++ b/NEWS -@@ -1,3 +1,31 @@ +@@ -1,3 +1,32 @@ +*** Changes since avr-libc-1.8.0: + +* Bugs fixed: @@ -1824,6 +1891,7 @@ index 0e5dad4..19fed26 100644 + [#7909] Adding __volatile__ to __asm__ within pgmspace header + [#7910] Add missing PCINT2_vect to iotn40.h and update all the + following vector numbers ++ [no-id] Add RAMSTART, fix RAMSIZE, RAMEND and FLASHEND in device headers + +* Other changes: + @@ -1977,7 +2045,7 @@ index 08e2586..090bf9a 100644 #ifndef _NTZ_H #define _NTZ_H diff --git a/configure.ac b/configure.ac -index a372df2..60b0917 100644 +index a372df2..9077327 100644 --- a/configure.ac +++ b/configure.ac @@ -30,7 +30,7 @@ @@ -2148,7 +2216,7 @@ index a372df2..60b0917 100644 # avr4 AM_CONDITIONAL(HAS_avr4, true) -@@ -579,12 +643,30 @@ AM_CONDITIONAL(HAS_atmega8, true) +@@ -579,12 +643,33 @@ AM_CONDITIONAL(HAS_atmega8, true) AM_CONDITIONAL(HAS_atmega8515, true) AM_CONDITIONAL(HAS_atmega8535, true) @@ -2175,11 +2243,24 @@ index a372df2..60b0917 100644 +CHECK_AVR_DEVICE(atmega48pa) +AM_CONDITIONAL(HAS_atmega48pa, test "x$HAS_atmega48pa" = "xyes") ++ ++CHECK_AVR_DEVICE(atmega48pb) ++AM_CONDITIONAL(HAS_atmega48pb, test "x$HAS_atmega48pb" = "xyes") + CHECK_AVR_DEVICE(atmega48p) AM_CONDITIONAL(HAS_atmega48p, test "x$HAS_atmega48p" = "xyes") -@@ -646,9 +728,30 @@ AM_CONDITIONAL(HAS_at90pwm316, test "x$HAS_at90pwm316" = "xyes") +@@ -600,6 +685,9 @@ AM_CONDITIONAL(HAS_atmega88p, test "x$HAS_atmega88p" = "xyes") + CHECK_AVR_DEVICE(atmega88pa) + AM_CONDITIONAL(HAS_atmega88pa, test "x$HAS_atmega88pa" = "xyes") + ++CHECK_AVR_DEVICE(atmega88pb) ++AM_CONDITIONAL(HAS_atmega88pb, test "x$HAS_atmega88pb" = "xyes") ++ + CHECK_AVR_DEVICE(atmega8hva) + AM_CONDITIONAL(HAS_atmega8hva, test "x$HAS_atmega8hva" = "xyes") + +@@ -646,9 +734,36 @@ AM_CONDITIONAL(HAS_at90pwm316, test "x$HAS_at90pwm316" = "xyes") CHECK_AVR_DEVICE(at90pwm216) AM_CONDITIONAL(HAS_at90pwm216, test "x$HAS_at90pwm216" = "xyes") @@ -2192,6 +2273,9 @@ index a372df2..60b0917 100644 +CHECK_AVR_DEVICE(ata5702m322) +AM_CONDITIONAL(HAS_ata5702m322, test "x$HAS_ata5702m322" = "xyes") + ++CHECK_AVR_DEVICE(ata5782) ++AM_CONDITIONAL(HAS_ata5782, test "x$HAS_ata5782" = "xyes") ++ +CHECK_AVR_DEVICE(ata5790) +AM_CONDITIONAL(HAS_ata5790, test "x$HAS_ata5790" = "xyes") + @@ -2201,6 +2285,9 @@ index a372df2..60b0917 100644 +CHECK_AVR_DEVICE(ata5795) +AM_CONDITIONAL(HAS_ata5795, test "x$HAS_ata5795" = "xyes") + ++CHECK_AVR_DEVICE(ata5831) ++AM_CONDITIONAL(HAS_ata5831, test "x$HAS_ata5831" = "xyes") ++ +CHECK_AVR_DEVICE(ata6613c) +AM_CONDITIONAL(HAS_ata6613c, test "x$HAS_ata6613c" = "xyes") + @@ -2210,7 +2297,7 @@ index a372df2..60b0917 100644 CHECK_AVR_DEVICE(atmega16) AM_CONDITIONAL(HAS_atmega16, test "x$HAS_atmega16" = "xyes") -@@ -670,6 +773,9 @@ AM_CONDITIONAL(HAS_atmega164a, test "x$HAS_atmega164a" = "xyes") +@@ -670,6 +785,9 @@ AM_CONDITIONAL(HAS_atmega164a, test "x$HAS_atmega164a" = "xyes") CHECK_AVR_DEVICE(atmega164p) AM_CONDITIONAL(HAS_atmega164p, test "x$HAS_atmega164p" = "xyes") @@ -2220,7 +2307,7 @@ index a372df2..60b0917 100644 CHECK_AVR_DEVICE(atmega165) AM_CONDITIONAL(HAS_atmega165, test "x$HAS_atmega165" = "xyes") -@@ -679,6 +785,9 @@ AM_CONDITIONAL(HAS_atmega165a, test "x$HAS_atmega165a" = "xyes") +@@ -679,6 +797,9 @@ AM_CONDITIONAL(HAS_atmega165a, test "x$HAS_atmega165a" = "xyes") CHECK_AVR_DEVICE(atmega165p) AM_CONDITIONAL(HAS_atmega165p, test "x$HAS_atmega165p" = "xyes") @@ -2230,17 +2317,20 @@ index a372df2..60b0917 100644 CHECK_AVR_DEVICE(atmega168) AM_CONDITIONAL(HAS_atmega168, test "x$HAS_atmega168" = "xyes") -@@ -688,6 +797,9 @@ AM_CONDITIONAL(HAS_atmega168a, test "x$HAS_atmega168a" = "xyes") +@@ -688,6 +809,12 @@ AM_CONDITIONAL(HAS_atmega168a, test "x$HAS_atmega168a" = "xyes") CHECK_AVR_DEVICE(atmega168p) AM_CONDITIONAL(HAS_atmega168p, test "x$HAS_atmega168p" = "xyes") +CHECK_AVR_DEVICE(atmega168pa) +AM_CONDITIONAL(HAS_atmega168pa, test "x$HAS_atmega168pa" = "xyes") ++ ++CHECK_AVR_DEVICE(atmega168pb) ++AM_CONDITIONAL(HAS_atmega168pb, test "x$HAS_atmega168pb" = "xyes") + CHECK_AVR_DEVICE(atmega169) AM_CONDITIONAL(HAS_atmega169, test "x$HAS_atmega169" = "xyes") -@@ -721,6 +833,9 @@ AM_CONDITIONAL(HAS_atmega16u4, test "x$HAS_atmega16u4" = "xyes") +@@ -721,6 +848,9 @@ AM_CONDITIONAL(HAS_atmega16u4, test "x$HAS_atmega16u4" = "xyes") CHECK_AVR_DEVICE(atmega32) AM_CONDITIONAL(HAS_atmega32, test "x$HAS_atmega32" = "xyes") @@ -2250,7 +2340,7 @@ index a372df2..60b0917 100644 CHECK_AVR_DEVICE(atmega323) AM_CONDITIONAL(HAS_atmega323, test "x$HAS_atmega323" = "xyes") -@@ -742,6 +857,9 @@ AM_CONDITIONAL(HAS_atmega325a, test "x$HAS_atmega325a" = "xyes") +@@ -742,6 +872,9 @@ AM_CONDITIONAL(HAS_atmega325a, test "x$HAS_atmega325a" = "xyes") CHECK_AVR_DEVICE(atmega325p) AM_CONDITIONAL(HAS_atmega325p, test "x$HAS_atmega325p" = "xyes") @@ -2260,7 +2350,7 @@ index a372df2..60b0917 100644 CHECK_AVR_DEVICE(atmega3250) AM_CONDITIONAL(HAS_atmega3250, test "x$HAS_atmega3250" = "xyes") -@@ -751,6 +869,9 @@ AM_CONDITIONAL(HAS_atmega3250a, test "x$HAS_atmega3250a" = "xyes") +@@ -751,6 +884,9 @@ AM_CONDITIONAL(HAS_atmega3250a, test "x$HAS_atmega3250a" = "xyes") CHECK_AVR_DEVICE(atmega3250p) AM_CONDITIONAL(HAS_atmega3250p, test "x$HAS_atmega3250p" = "xyes") @@ -2270,7 +2360,7 @@ index a372df2..60b0917 100644 CHECK_AVR_DEVICE(atmega328) AM_CONDITIONAL(HAS_atmega328, test "x$HAS_atmega328" = "xyes") -@@ -778,6 +899,9 @@ AM_CONDITIONAL(HAS_atmega3290a, test "x$HAS_atmega3290a" = "xyes") +@@ -778,6 +914,9 @@ AM_CONDITIONAL(HAS_atmega3290a, test "x$HAS_atmega3290a" = "xyes") CHECK_AVR_DEVICE(atmega3290p) AM_CONDITIONAL(HAS_atmega3290p, test "x$HAS_atmega3290p" = "xyes") @@ -2280,7 +2370,7 @@ index a372df2..60b0917 100644 CHECK_AVR_DEVICE(atmega32c1) AM_CONDITIONAL(HAS_atmega32c1, test "x$HAS_atmega32c1" = "xyes") -@@ -799,9 +923,18 @@ AM_CONDITIONAL(HAS_atmega32u6, test "x$HAS_atmega32u6" = "xyes") +@@ -799,9 +938,18 @@ AM_CONDITIONAL(HAS_atmega32u6, test "x$HAS_atmega32u6" = "xyes") CHECK_AVR_DEVICE(atmega406) AM_CONDITIONAL(HAS_atmega406, test "x$HAS_atmega406" = "xyes") @@ -2299,7 +2389,7 @@ index a372df2..60b0917 100644 CHECK_AVR_DEVICE(atmega640) AM_CONDITIONAL(HAS_atmega640, test "x$HAS_atmega640" = "xyes") -@@ -859,6 +992,9 @@ AM_CONDITIONAL(HAS_atmega64c1, test "x$HAS_atmega64c1" = "xyes") +@@ -859,6 +1007,9 @@ AM_CONDITIONAL(HAS_atmega64c1, test "x$HAS_atmega64c1" = "xyes") CHECK_AVR_DEVICE(atmega64hve) AM_CONDITIONAL(HAS_atmega64hve, test "x$HAS_atmega64hve" = "xyes") @@ -2309,7 +2399,7 @@ index a372df2..60b0917 100644 CHECK_AVR_DEVICE(atmega64m1) AM_CONDITIONAL(HAS_atmega64m1, test "x$HAS_atmega64m1" = "xyes") -@@ -876,12 +1012,18 @@ AM_CONDITIONAL(HAS_avr51, test "x$HAS_avr51" = "xyes") +@@ -876,12 +1027,18 @@ AM_CONDITIONAL(HAS_avr51, test "x$HAS_avr51" = "xyes") AM_CONDITIONAL(HAS_atmega128, true) @@ -2328,7 +2418,7 @@ index a372df2..60b0917 100644 CHECK_AVR_DEVICE(atmega1284p) AM_CONDITIONAL(HAS_atmega1284p, test "x$HAS_atmega1284p" = "xyes") -@@ -894,6 +1036,12 @@ AM_CONDITIONAL(HAS_at90usb1286, test "x$HAS_at90usb1286" = "xyes") +@@ -894,6 +1051,12 @@ AM_CONDITIONAL(HAS_at90usb1286, test "x$HAS_at90usb1286" = "xyes") CHECK_AVR_DEVICE(at90usb1287) AM_CONDITIONAL(HAS_at90usb1287, test "x$HAS_at90usb1287" = "xyes") @@ -2341,7 +2431,7 @@ index a372df2..60b0917 100644 # avr6 CHECK_AVR_DEVICE(avr6) -@@ -905,6 +1053,23 @@ AM_CONDITIONAL(HAS_atmega2560, test "x$HAS_atmega2560" = "xyes") +@@ -905,6 +1068,14 @@ AM_CONDITIONAL(HAS_atmega2560, test "x$HAS_atmega2560" = "xyes") CHECK_AVR_DEVICE(atmega2561) AM_CONDITIONAL(HAS_atmega2561, test "x$HAS_atmega2561" = "xyes") @@ -2352,20 +2442,11 @@ index a372df2..60b0917 100644 +AM_CONDITIONAL(HAS_atmega2564rfr2, test "x$HAS_atmega2564rfr2" = "xyes") + + -+# avr7 -+CHECK_AVR_DEVICE(avr7) -+AM_CONDITIONAL(HAS_avr7, test "x$HAS_avr7" = "xyes") -+ -+CHECK_AVR_DEVICE(ata5782) -+AM_CONDITIONAL(HAS_ata5782, test "x$HAS_ata5782" = "xyes") -+ -+CHECK_AVR_DEVICE(ata5831) -+AM_CONDITIONAL(HAS_ata5831, test "x$HAS_ata5831" = "xyes") + # avrxmega2 CHECK_AVR_DEVICE(avrxmega2) -@@ -913,15 +1078,42 @@ AM_CONDITIONAL(HAS_avrxmega2, test "x$HAS_avrxmega2" = "xyes") +@@ -913,15 +1084,42 @@ AM_CONDITIONAL(HAS_avrxmega2, test "x$HAS_avrxmega2" = "xyes") CHECK_AVR_DEVICE(atxmega16a4) AM_CONDITIONAL(HAS_atxmega16a4, test "x$HAS_atxmega16a4" = "xyes") @@ -2408,7 +2489,7 @@ index a372df2..60b0917 100644 # avrxmega4 CHECK_AVR_DEVICE(avrxmega4) -@@ -930,9 +1122,27 @@ AM_CONDITIONAL(HAS_avrxmega4, test "x$HAS_avrxmega4" = "xyes") +@@ -930,9 +1128,27 @@ AM_CONDITIONAL(HAS_avrxmega4, test "x$HAS_avrxmega4" = "xyes") CHECK_AVR_DEVICE(atxmega64a3) AM_CONDITIONAL(HAS_atxmega64a3, test "x$HAS_atxmega64a3" = "xyes") @@ -2436,7 +2517,7 @@ index a372df2..60b0917 100644 # avrxmega5 CHECK_AVR_DEVICE(avrxmega5) -@@ -952,24 +1162,59 @@ AM_CONDITIONAL(HAS_avrxmega6, test "x$HAS_avrxmega6" = "xyes") +@@ -952,24 +1168,59 @@ AM_CONDITIONAL(HAS_avrxmega6, test "x$HAS_avrxmega6" = "xyes") CHECK_AVR_DEVICE(atxmega128a3) AM_CONDITIONAL(HAS_atxmega128a3, test "x$HAS_atxmega128a3" = "xyes") @@ -2496,7 +2577,7 @@ index a372df2..60b0917 100644 # avrxmega7 CHECK_AVR_DEVICE(avrxmega7) -@@ -981,10 +1226,13 @@ AM_CONDITIONAL(HAS_atxmega128a1, test "x$HAS_atxmega128a1" = "xyes") +@@ -981,10 +1232,13 @@ AM_CONDITIONAL(HAS_atxmega128a1, test "x$HAS_atxmega128a1" = "xyes") CHECK_AVR_DEVICE(atxmega128a1u) AM_CONDITIONAL(HAS_atxmega128a1u, test "x$HAS_atxmega128a1u" = "xyes") @@ -2513,7 +2594,7 @@ index a372df2..60b0917 100644 CHECK_AVR_DEVICE(attiny4) AM_CONDITIONAL(HAS_attiny4, test "x$HAS_attiny4" = "xyes") -@@ -1071,11 +1319,24 @@ AC_CONFIG_FILES([ +@@ -1071,11 +1325,24 @@ AC_CONFIG_FILES([ avr/lib/avr2/at86rf401/Makefile ]) @@ -2539,7 +2620,7 @@ index a372df2..60b0917 100644 avr/lib/avr25/attiny13/Makefile avr/lib/avr25/attiny13a/Makefile avr/lib/avr25/attiny2313/Makefile -@@ -1089,12 +1350,15 @@ AC_CONFIG_FILES([ +@@ -1089,12 +1356,15 @@ AC_CONFIG_FILES([ avr/lib/avr25/attiny43u/Makefile avr/lib/avr25/attiny44/Makefile avr/lib/avr25/attiny44a/Makefile @@ -2555,7 +2636,7 @@ index a372df2..60b0917 100644 avr/lib/avr25/attiny85/Makefile avr/lib/avr25/attiny861/Makefile avr/lib/avr25/attiny861a/Makefile -@@ -1102,6 +1366,20 @@ AC_CONFIG_FILES([ +@@ -1102,6 +1372,20 @@ AC_CONFIG_FILES([ avr/lib/avr25/attiny88/Makefile ]) @@ -2576,7 +2657,7 @@ index a372df2..60b0917 100644 #avr3 AC_CONFIG_FILES([ avr/lib/avr3/Makefile -@@ -1125,19 +1403,29 @@ AC_CONFIG_FILES([ +@@ -1125,23 +1409,35 @@ AC_CONFIG_FILES([ avr/lib/avr35/Makefile avr/lib/avr35/at90usb82/Makefile avr/lib/avr35/at90usb162/Makefile @@ -2600,13 +2681,19 @@ index a372df2..60b0917 100644 avr/lib/avr4/atmega48/Makefile avr/lib/avr4/atmega48a/Makefile + avr/lib/avr4/atmega48pa/Makefile ++ avr/lib/avr4/atmega48pb/Makefile avr/lib/avr4/atmega48p/Makefile avr/lib/avr4/atmega8/Makefile + avr/lib/avr4/atmega8a/Makefile avr/lib/avr4/atmega88/Makefile avr/lib/avr4/atmega88a/Makefile avr/lib/avr4/atmega88p/Makefile -@@ -1161,12 +1449,19 @@ AC_CONFIG_FILES([ + avr/lib/avr4/atmega88pa/Makefile ++ avr/lib/avr4/atmega88pb/Makefile + avr/lib/avr4/atmega8515/Makefile + avr/lib/avr4/atmega8535/Makefile + avr/lib/avr4/atmega8hva/Makefile +@@ -1161,12 +1457,21 @@ AC_CONFIG_FILES([ avr/lib/avr5/at90can128/Makefile avr/lib/avr5/at90pwm216/Makefile avr/lib/avr5/at90pwm316/Makefile @@ -2618,15 +2705,17 @@ index a372df2..60b0917 100644 avr/lib/avr5/at90usb1287/Makefile avr/lib/avr5/at94k/Makefile + avr/lib/avr5/ata5702m322/Makefile ++ avr/lib/avr5/ata5782/Makefile + avr/lib/avr5/ata5790/Makefile + avr/lib/avr5/ata5790n/Makefile + avr/lib/avr5/ata5795/Makefile ++ avr/lib/avr5/ata5831/Makefile + avr/lib/avr5/ata6613c/Makefile + avr/lib/avr5/ata6614q/Makefile avr/lib/avr5/atmega16/Makefile avr/lib/avr5/atmega16a/Makefile avr/lib/avr5/atmega161/Makefile -@@ -1174,12 +1469,15 @@ AC_CONFIG_FILES([ +@@ -1174,12 +1479,16 @@ AC_CONFIG_FILES([ avr/lib/avr5/atmega163/Makefile avr/lib/avr5/atmega164a/Makefile avr/lib/avr5/atmega164p/Makefile @@ -2639,10 +2728,11 @@ index a372df2..60b0917 100644 avr/lib/avr5/atmega168a/Makefile avr/lib/avr5/atmega168p/Makefile + avr/lib/avr5/atmega168pa/Makefile ++ avr/lib/avr5/atmega168pb/Makefile avr/lib/avr5/atmega169/Makefile avr/lib/avr5/atmega169a/Makefile avr/lib/avr5/atmega169p/Makefile -@@ -1191,6 +1489,7 @@ AC_CONFIG_FILES([ +@@ -1191,6 +1500,7 @@ AC_CONFIG_FILES([ avr/lib/avr5/atmega16m1/Makefile avr/lib/avr5/atmega16u4/Makefile avr/lib/avr5/atmega32/Makefile @@ -2650,7 +2740,7 @@ index a372df2..60b0917 100644 avr/lib/avr5/atmega323/Makefile avr/lib/avr5/atmega324a/Makefile avr/lib/avr5/atmega324p/Makefile -@@ -1198,9 +1497,11 @@ AC_CONFIG_FILES([ +@@ -1198,9 +1508,11 @@ AC_CONFIG_FILES([ avr/lib/avr5/atmega325/Makefile avr/lib/avr5/atmega325a/Makefile avr/lib/avr5/atmega325p/Makefile @@ -2662,7 +2752,7 @@ index a372df2..60b0917 100644 avr/lib/avr5/atmega328/Makefile avr/lib/avr5/atmega328p/Makefile avr/lib/avr5/atmega329/Makefile -@@ -1210,6 +1511,7 @@ AC_CONFIG_FILES([ +@@ -1210,6 +1522,7 @@ AC_CONFIG_FILES([ avr/lib/avr5/atmega3290/Makefile avr/lib/avr5/atmega3290a/Makefile avr/lib/avr5/atmega3290p/Makefile @@ -2670,7 +2760,7 @@ index a372df2..60b0917 100644 avr/lib/avr5/atmega32c1/Makefile avr/lib/avr5/atmega32hvb/Makefile avr/lib/avr5/atmega32hvbrevb/Makefile -@@ -1217,7 +1519,10 @@ AC_CONFIG_FILES([ +@@ -1217,7 +1530,10 @@ AC_CONFIG_FILES([ avr/lib/avr5/atmega32u4/Makefile avr/lib/avr5/atmega32u6/Makefile avr/lib/avr5/atmega406/Makefile @@ -2681,7 +2771,7 @@ index a372df2..60b0917 100644 avr/lib/avr5/atmega640/Makefile avr/lib/avr5/atmega644/Makefile avr/lib/avr5/atmega644a/Makefile -@@ -1237,6 +1542,7 @@ AC_CONFIG_FILES([ +@@ -1237,6 +1553,7 @@ AC_CONFIG_FILES([ avr/lib/avr5/atmega6490p/Makefile avr/lib/avr5/atmega64c1/Makefile avr/lib/avr5/atmega64hve/Makefile @@ -2689,7 +2779,7 @@ index a372df2..60b0917 100644 avr/lib/avr5/atmega64m1/Makefile avr/lib/avr5/atmega128/Makefile avr/lib/avr5/atmega1280/Makefile -@@ -1250,10 +1556,14 @@ AC_CONFIG_FILES([ +@@ -1250,10 +1567,14 @@ AC_CONFIG_FILES([ AC_CONFIG_FILES([ avr/lib/avr51/Makefile avr/lib/avr51/atmega128/Makefile @@ -2704,19 +2794,12 @@ index a372df2..60b0917 100644 avr/lib/avr51/at90can128/Makefile avr/lib/avr51/at90usb1286/Makefile avr/lib/avr51/at90usb1287/Makefile -@@ -1264,22 +1574,46 @@ AC_CONFIG_FILES([ +@@ -1264,22 +1585,39 @@ AC_CONFIG_FILES([ avr/lib/avr6/Makefile avr/lib/avr6/atmega2560/Makefile avr/lib/avr6/atmega2561/Makefile + avr/lib/avr6/atmega256rfr2/Makefile + avr/lib/avr6/atmega2564rfr2/Makefile -+]) -+ -+#avr7 -+AC_CONFIG_FILES([ -+ avr/lib/avr7/Makefile -+ avr/lib/avr7/ata5782/Makefile -+ avr/lib/avr7/ata5831/Makefile ]) # avrxmega2 @@ -2751,7 +2834,7 @@ index a372df2..60b0917 100644 ]) # avrxmega5 -@@ -1293,12 +1627,24 @@ AC_CONFIG_FILES([ +@@ -1293,12 +1631,24 @@ AC_CONFIG_FILES([ AC_CONFIG_FILES([ avr/lib/avrxmega6/Makefile avr/lib/avrxmega6/atxmega128a3/Makefile @@ -2776,7 +2859,7 @@ index a372df2..60b0917 100644 ]) # avrxmega7 -@@ -1306,18 +1652,19 @@ AC_CONFIG_FILES([ +@@ -1306,18 +1656,19 @@ AC_CONFIG_FILES([ avr/lib/avrxmega7/Makefile avr/lib/avrxmega7/atxmega128a1/Makefile avr/lib/avrxmega7/atxmega128a1u/Makefile @@ -2909,7 +2992,7 @@ index cb5a45e..f72ee21 100755 # diff --git a/devtools/gen-avr-lib-tree.sh b/devtools/gen-avr-lib-tree.sh -index 276304a..9b7fa7a 100755 +index 276304a..5d8f3fb 100755 --- a/devtools/gen-avr-lib-tree.sh +++ b/devtools/gen-avr-lib-tree.sh @@ -29,7 +29,7 @@ @@ -2986,7 +3069,7 @@ index 276304a..9b7fa7a 100755 AVR3_DEV_INFO="\ atmega103:crtm103.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ -@@ -127,17 +155,27 @@ at43usb320:crt43320.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS}\ +@@ -127,21 +155,33 @@ at43usb320:crt43320.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS}\ AVR35_DEV_INFO="\ at90usb82:crtusb82.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90usb162:crtusb162.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ @@ -3009,13 +3092,19 @@ index 276304a..9b7fa7a 100755 atmega48:crtm48.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega48a:crtm48a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ +atmega48pa:crtm48pa.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ ++atmega48pb:crtm48pb.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega48p:crtm48p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega8:crtm8.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ +atmega8a:crtm8a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega88:crtm88.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega88a:crtm88a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega88p:crtm88p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ -@@ -159,12 +197,19 @@ at90can64:crtcan64.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ + atmega88pa:crtm88pa.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ ++atmega88pb:crtm88pb.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ + atmega8515:crtm8515.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ + atmega8535:crtm8535.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ + atmega8hva:crtm8hva.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ +@@ -159,12 +199,21 @@ at90can64:crtcan64.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90can128:crtcan128.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90pwm216:crt90pwm216.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at90pwm316:crt90pwm316.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ @@ -3027,15 +3116,17 @@ index 276304a..9b7fa7a 100755 at90usb1287:crtusb1287.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ at94k:crtat94k.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ +ata5702m322:crta5702m322.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ ++ata5782:crta5782.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ +ata5790:crta5790.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ +ata5790n:crta5790n.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ +ata5795:crta5795.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ ++ata5831:crta5831.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ +ata6613c:crta6613c.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ +ata6614q:crta6614q.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega16:crtm16.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega16a:crtm16a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega161:crtm161.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ -@@ -172,12 +217,15 @@ atmega162:crtm162.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ +@@ -172,12 +221,16 @@ atmega162:crtm162.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega163:crtm163.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega164a:crtm164a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega164p:crtm164p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ @@ -3048,10 +3139,11 @@ index 276304a..9b7fa7a 100755 atmega168a:crtm168a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega168p:crtm168p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ +atmega168pa:crtm168pa.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ ++atmega168pb:crtm168pb.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega169:crtm169.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega169a:crtm169a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega169p:crtm169p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ -@@ -189,6 +237,7 @@ atmega16hvbrevb:crtm16hvbrevb.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ +@@ -189,6 +242,7 @@ atmega16hvbrevb:crtm16hvbrevb.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega16m1:crtm16m1.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega16u4:crtm16u4.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega32:crtm32.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ @@ -3059,7 +3151,7 @@ index 276304a..9b7fa7a 100755 atmega323:crtm323.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega324a:crtm324a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega324p:crtm324p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ -@@ -196,9 +245,11 @@ atmega324pa:crtm324pa.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ +@@ -196,9 +250,11 @@ atmega324pa:crtm324pa.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega325:crtm325.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega325a:crtm325a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega325p:crtm325p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ @@ -3071,7 +3163,7 @@ index 276304a..9b7fa7a 100755 atmega328:crtm328.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega328p:crtm328p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega329:crtm329.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ -@@ -208,6 +259,7 @@ atmega329pa:crtm329pa.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ +@@ -208,6 +264,7 @@ atmega329pa:crtm329pa.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega3290:crtm3290.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega3290a:crtm3290a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega3290p:crtm3290p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ @@ -3079,7 +3171,7 @@ index 276304a..9b7fa7a 100755 atmega32c1:crtm32c1.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega32hvb:crtm32hvb.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega32hvbrevb:crtm32hvbrevb.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ -@@ -215,7 +267,10 @@ atmega32m1:crtm32m1.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ +@@ -215,7 +272,10 @@ atmega32m1:crtm32m1.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega32u4:crtm32u4.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega32u6:crtm32u6.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega406:crtm406.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ @@ -3090,7 +3182,7 @@ index 276304a..9b7fa7a 100755 atmega640:crtm640.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega644:crtm644.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega644a:crtm644a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ -@@ -235,6 +290,7 @@ atmega6490a:crtm6490a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ +@@ -235,6 +295,7 @@ atmega6490a:crtm6490a.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega6490p:crtm6490p.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega64c1:crtm64c1.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega64hve:crtm64hve.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ @@ -3098,7 +3190,7 @@ index 276304a..9b7fa7a 100755 atmega64m1:crtm64m1.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega128:crtm128.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ atmega1280:crtm1280.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ -@@ -246,10 +302,14 @@ m3000:crtm3000.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS}\ +@@ -246,10 +307,14 @@ m3000:crtm3000.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS}\ AVR51_DEV_INFO="\ atmega128:crtm128.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ @@ -3113,7 +3205,7 @@ index 276304a..9b7fa7a 100755 at90can128:crtcan128.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ at90usb1286:crtusb1286.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ at90usb1287:crtusb1287.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS}\ -@@ -257,19 +317,41 @@ at90usb1287:crtusb1287.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS}\ +@@ -257,19 +322,36 @@ at90usb1287:crtusb1287.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS}\ AVR6_DEV_INFO="\ atmega2560:crtm2560.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ @@ -3121,11 +3213,6 @@ index 276304a..9b7fa7a 100755 +atmega2561:crtm2561.o:${DEV_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ +atmega256rfr2:crtm256rfr2.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ +atmega2564rfr2:crtm2564rfr2.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS}\ -+" -+ -+AVR7_DEV_INFO="\ -+ata5782:crta5782.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ -+ata5831:crta5831.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS}\ " AVRXMEGA2_DEV_INFO="\ @@ -3195,7 +3282,7 @@ index 276304a..9b7fa7a 100755 attiny4:crttn4.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny5:crttn5.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ attiny9:crttn9.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ -@@ -305,21 +400,24 @@ attiny40:crttn40.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS}\ +@@ -305,21 +400,23 @@ attiny40:crttn40.o:${DEV_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS}\ LIB_DEFS="-D__COMPILING_AVR_LIBC__" AVR_ARH_INFO="\ @@ -3225,7 +3312,6 @@ index 276304a..9b7fa7a 100755 +avr5::AVR5_DEV_INFO:${LIB_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ +avr51::AVR51_DEV_INFO:${LIB_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ +avr6::AVR6_DEV_INFO:${LIB_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ -+avr7::AVR7_DEV_INFO:${LIB_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ +avrxmega2::AVRXMEGA2_DEV_INFO:${LIB_DEFS}:${CFLAGS_SPACE}:${DEV_ASFLAGS};\ +avrxmega4::AVRXMEGA4_DEV_INFO:${LIB_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ +avrxmega5::AVRXMEGA5_DEV_INFO:${LIB_DEFS}:${CFLAGS_BIG_MEMORY}:${DEV_ASFLAGS};\ @@ -3235,7 +3321,7 @@ index 276304a..9b7fa7a 100755 " echo "Generating source directories:" -@@ -354,21 +452,38 @@ ARH_SUBDIRS="" +@@ -354,21 +451,38 @@ ARH_SUBDIRS="" for ath_lib in $AVR_ARH_INFO do arh=$(echo $ath_lib | cut -d ':' -f 1) @@ -3282,7 +3368,7 @@ index 276304a..9b7fa7a 100755 DEV_SUBDIRS="" -@@ -382,7 +497,7 @@ do +@@ -382,7 +496,7 @@ do crt_cflags=$(echo $dev_crt | cut -d ':' -f 4) crt_asflags=$(echo $dev_crt | cut -d ':' -f 5) @@ -3291,7 +3377,7 @@ index 276304a..9b7fa7a 100755 test -d $dev || mkdir $dev -@@ -393,7 +508,7 @@ do +@@ -393,7 +507,7 @@ do -e "s/<>/$crt_defs/g" \ -e "s/<>/$crt_cflags/g" \ -e "s/<>/$crt_asflags/g" \ @@ -3300,7 +3386,7 @@ index 276304a..9b7fa7a 100755 > $dev/tempfile && mv -f $dev/tempfile $dev/Makefile.am DEV_SUBDIRS="$DEV_SUBDIRS $dev" -@@ -406,7 +521,7 @@ do +@@ -406,7 +520,7 @@ do -e "s/<>/$lib_defs/g" \ -e "s/<>/$lib_cflags/g" \ -e "s/<>/$lib_asflags/g" \ @@ -3309,7 +3395,7 @@ index 276304a..9b7fa7a 100755 > tempfile && mv -f tempfile Makefile.am # Find the first and the last lines of <> block. -@@ -428,19 +543,22 @@ do +@@ -428,19 +542,22 @@ do # After the <> block. tail -n +$(($n2 + 1)) Makefile.am >> tempfile @@ -4473,7 +4559,7 @@ index a519ab1..9e64b04 100644 /** diff --git a/doc/api/main_page.dox b/doc/api/main_page.dox -index 689e366..d79ec2c 100644 +index 689e366..cd8531d 100644 --- a/doc/api/main_page.dox +++ b/doc/api/main_page.dox @@ -27,7 +27,7 @@ @@ -4496,7 +4582,7 @@ index 689e366..d79ec2c 100644 - atmega1284p - atmega16 - atmega161 -@@ -103,16 +105,20 @@ compile-time. +@@ -103,16 +105,21 @@ compile-time. - atmega163 - atmega164a - atmega164p @@ -4509,6 +4595,7 @@ index 689e366..d79ec2c 100644 - atmega168a - atmega168p +- atmega168pa ++- atmega168pb - atmega16a - atmega2560 - atmega2561 @@ -4517,7 +4604,7 @@ index 689e366..d79ec2c 100644 - atmega323 - atmega324a - atmega324p -@@ -120,15 +126,19 @@ compile-time. +@@ -120,15 +127,20 @@ compile-time. - atmega325 - atmega325a - atmega325p @@ -4531,13 +4618,14 @@ index 689e366..d79ec2c 100644 - atmega48 - atmega48a +- atmega48pa ++- atmega48pb - atmega48p - atmega64 +- atmega64a - atmega640 - atmega644 - atmega644a -@@ -141,6 +151,7 @@ compile-time. +@@ -141,10 +153,12 @@ compile-time. - atmega6450a - atmega6450p - atmega8 @@ -4545,7 +4633,12 @@ index 689e366..d79ec2c 100644 - atmega88 - atmega88a - atmega88p -@@ -174,17 +185,21 @@ compile-time. + - atmega88pa ++- atmega88pb + - atmega8515 + - atmega8535 + +@@ -174,17 +188,21 @@ compile-time. - attiny43u - attiny44 - attiny44a @@ -4567,7 +4660,7 @@ index 689e366..d79ec2c 100644 \par Automotive AVR Devices: -@@ -194,6 +209,20 @@ compile-time. +@@ -194,6 +212,20 @@ compile-time. - atmega64c1 - atmega64m1 - attiny167 @@ -4588,7 +4681,7 @@ index 689e366..d79ec2c 100644 \par CAN AVR Devices: -@@ -214,6 +243,7 @@ compile-time. +@@ -214,6 +246,7 @@ compile-time. - atmega3290 - atmega3290a - atmega3290p @@ -4596,7 +4689,7 @@ index 689e366..d79ec2c 100644 - atmega649 - atmega649a - atmega6490 -@@ -230,6 +260,7 @@ compile-time. +@@ -230,6 +263,7 @@ compile-time. - at90pwm3 - at90pwm3b - at90pwm316 @@ -4604,7 +4697,7 @@ index 689e366..d79ec2c 100644 - at90pwm81 \par Smart Battery AVR Devices: -@@ -242,6 +273,7 @@ compile-time. +@@ -242,6 +276,7 @@ compile-time. - atmega32hvb - atmega32hvbrevb - atmega64hve @@ -4612,7 +4705,7 @@ index 689e366..d79ec2c 100644 - atmega406 \par USB AVR Devices: -@@ -262,22 +294,61 @@ compile-time. +@@ -262,22 +297,61 @@ compile-time. \par XMEGA Devices: - atxmega16a4 @@ -4674,7 +4767,7 @@ index 689e366..d79ec2c 100644 \par Miscellaneous Devices: -@@ -287,6 +358,8 @@ compile-time. +@@ -287,6 +361,8 @@ compile-time. - at43usb355 - at86rf401 - at90scr100 @@ -5169,7 +5262,7 @@ index f34420b..f4596b8 100644 /** \page using_avrprog Using the avrdude program diff --git a/doc/api/using-tools.dox b/doc/api/using-tools.dox -index f2b753a..2c10a40 100644 +index f2b753a..2bf0d69 100644 --- a/doc/api/using-tools.dox +++ b/doc/api/using-tools.dox @@ -26,7 +26,7 @@ @@ -5181,28 +5274,7 @@ index f2b753a..2c10a40 100644 /** \page using_tools Using the GNU tools -@@ -180,6 +180,20 @@ AVR will be defined as well when using the standard levels gnu89 - - "Enhanced" CPU core, 256 KB of ROM - -+ -+ avr7 [2] -+ -+ __AVR_ARCH__=7
-+ __AVR_MEGA__ [5]
-+ __AVR_ENHANCED__ [5]
-+ __AVR_HAVE_JMP_CALL__ [4]
-+ __AVR_HAVE_MOVW__ [1]
-+ __AVR_HAVE_LPMX__ [1]
-+ __AVR_HAVE_MUL__ [1]
-+ __AVR_2_BYTE_PC__ [2] -+ -+ "Enhanced" CPU core, 20K of Flash that starts at 0x8000 -+ - -

- [1] New in GCC 4.2
-@@ -231,6 +245,8 @@ AVR will be defined as well when using the standard levels gnu89 +@@ -231,6 +231,8 @@ AVR will be defined as well when using the standard levels gnu89 avr2/avr25 [1]at86rf401__AVR_AT86RF401__ avr2/avr25 [1]ata6289__AVR_ATA6289__ @@ -5211,7 +5283,7 @@ index f2b753a..2c10a40 100644 avr2/avr25 [1]attiny13__AVR_ATtiny13__ avr2/avr25 [1]attiny13a__AVR_ATtiny13A__ avr2/avr25 [1]attiny2313__AVR_ATtiny2313__ -@@ -244,12 +260,15 @@ AVR will be defined as well when using the standard levels gnu89 +@@ -244,12 +246,15 @@ AVR will be defined as well when using the standard levels gnu89 avr2/avr25 [1]attiny43u__AVR_ATtiny43U__ avr2/avr25 [1]attiny44__AVR_ATtiny44__ avr2/avr25 [1]attiny44a__AVR_ATtiny44A__ @@ -5227,7 +5299,7 @@ index f2b753a..2c10a40 100644 avr2/avr25 [1]attiny85__AVR_ATtiny85__ avr2/avr25 [1]attiny861__AVR_ATtiny861__ avr2/avr25 [1]attiny861a__AVR_ATtiny861A__ -@@ -264,16 +283,25 @@ AVR will be defined as well when using the standard levels gnu89 +@@ -264,22 +269,33 @@ AVR will be defined as well when using the standard levels gnu89 avr3/avr35 [2]at90usb82__AVR_AT90USB82__ avr3/avr35 [2]at90usb162__AVR_AT90USB162__ @@ -5247,13 +5319,21 @@ index f2b753a..2c10a40 100644 avr4atmega48__AVR_ATmega48__ avr4atmega48a__AVR_ATmega48A__ + avr4atmega48pa__AVR_ATmega48PA__ ++ avr4atmega48pb__AVR_ATmega48PB__ avr4atmega48p__AVR_ATmega48P__ avr4atmega8__AVR_ATmega8__ + avr4atmega8a__AVR_ATmega8A__ avr4atmega8515__AVR_ATmega8515__ avr4atmega8535__AVR_ATmega8535__ avr4atmega88__AVR_ATmega88__ -@@ -290,6 +318,7 @@ AVR will be defined as well when using the standard levels gnu89 + avr4atmega88a__AVR_ATmega88A__ + avr4atmega88p__AVR_ATmega88P__ + avr4atmega88pa__AVR_ATmega88PA__ ++ avr4atmega88pb__AVR_ATmega88PB__ + avr4atmega8hva__AVR_ATmega8HVA__ + avr4at90pwm1__AVR_AT90PWM1__ + avr4at90pwm2__AVR_AT90PWM2__ +@@ -290,6 +306,7 @@ AVR will be defined as well when using the standard levels gnu89 avr5at90can32__AVR_AT90CAN32__ avr5at90can64__AVR_AT90CAN64__ @@ -5261,16 +5341,18 @@ index f2b753a..2c10a40 100644 avr5at90pwm216__AVR_AT90PWM216__ avr5at90pwm316__AVR_AT90PWM316__ avr5at90scr100__AVR_AT90SCR100__ -@@ -297,17 +326,26 @@ AVR will be defined as well when using the standard levels gnu89 +@@ -297,17 +314,29 @@ AVR will be defined as well when using the standard levels gnu89 avr5at90usb647__AVR_AT90USB647__ avr5at94k__AVR_AT94K__ avr5atmega16__AVR_ATmega16__ + avr5ata5790__AVR_ATA5790__ + avr5ata5702m322__AVR_ATA5702M322__ ++ avr5ata5782__AVR_ATA5782__ + avr5ata6613c__AVR_ATA6613C__ + avr5ata6614q__AVR_ATA6614Q__ + avr5ata5790n__AVR_ATA5790N__ + avr5ata5795__AVR_ATA5795__ ++ avr5ata5831__AVR_ATA5831__ avr5atmega161__AVR_ATmega161__ avr5atmega162__AVR_ATmega162__ avr5atmega163__AVR_ATmega163__ @@ -5285,15 +5367,11 @@ index f2b753a..2c10a40 100644 avr5atmega168a__AVR_ATmega168A__ avr5atmega168p__AVR_ATmega168P__ + avr5atmega168pa__AVR_ATmega168PA__ ++ avr5atmega168pb__AVR_ATmega168PB__ avr5atmega169__AVR_ATmega169__ avr5atmega169a__AVR_ATmega169A__ avr5atmega169p__AVR_ATmega169P__ -@@ -316,10 +354,11 @@ AVR will be defined as well when using the standard levels gnu89 - avr5atmega16hva__AVR_ATmega16HVA__ - avr5atmega16hva2__AVR_ATmega16HVA2__ - avr5atmega16hvb__AVR_ATmega16HVB__ -- avr5atmega16hvbrevb__AVR_ATmega16HVBREVB__ -+ avr5atmega16hvbrevb__AVR_ATmega16HVBrevB__ +@@ -320,6 +349,7 @@ AVR will be defined as well when using the standard levels gnu89 avr5atmega16m1__AVR_ATmega16M1__ avr5atmega16u4__AVR_ATmega16U4__ avr5atmega32__AVR_ATmega32__ @@ -5301,7 +5379,7 @@ index f2b753a..2c10a40 100644 avr5atmega323__AVR_ATmega323__ avr5atmega324a__AVR_ATmega324A__ avr5atmega324p__AVR_ATmega324P__ -@@ -327,9 +366,11 @@ AVR will be defined as well when using the standard levels gnu89 +@@ -327,9 +357,11 @@ AVR will be defined as well when using the standard levels gnu89 avr5atmega325__AVR_ATmega325__ avr5atmega325a__AVR_ATmega325A__ avr5atmega325p__AVR_ATmega325P__ @@ -5313,16 +5391,15 @@ index f2b753a..2c10a40 100644 avr5atmega328__AVR_ATmega328__ avr5atmega328p__AVR_ATmega328P__ avr5atmega329__AVR_ATmega329__ -@@ -339,14 +380,18 @@ AVR will be defined as well when using the standard levels gnu89 +@@ -339,6 +371,7 @@ AVR will be defined as well when using the standard levels gnu89 avr5atmega3290__AVR_ATmega3290__ avr5atmega3290a__AVR_ATmega3290A__ avr5atmega3290p__AVR_ATmega3290P__ + avr5atmega3290pa__AVR_ATmega3290PA__ avr5atmega32c1__AVR_ATmega32C1__ avr5atmega32hvb__AVR_ATmega32HVB__ -- avr5atmega32hvbrevb__AVR_ATmega32HVBREVB__ -+ avr5atmega32hvbrevb__AVR_ATmega32HVBrevB__ - avr5atmega32m1__AVR_ATmega32M1__ + avr5atmega32hvbrevb__AVR_ATmega32HVBREVB__ +@@ -346,7 +379,10 @@ AVR will be defined as well when using the standard levels gnu89 avr5atmega32u4__AVR_ATmega32U4__ avr5atmega32u6__AVR_ATmega32U6__ avr5atmega406__AVR_ATmega406__ @@ -5333,7 +5410,7 @@ index f2b753a..2c10a40 100644 avr5atmega640__AVR_ATmega640__ avr5atmega644__AVR_ATmega644__ avr5atmega644a__AVR_ATmega644A__ -@@ -366,6 +411,7 @@ AVR will be defined as well when using the standard levels gnu89 +@@ -366,6 +402,7 @@ AVR will be defined as well when using the standard levels gnu89 avr5atmega649p__AVR_ATmega649P__ avr5atmega64c1__AVR_ATmega64C1__ avr5atmega64hve__AVR_ATmega64HVE__ @@ -5341,7 +5418,7 @@ index f2b753a..2c10a40 100644 avr5atmega64m1__AVR_ATmega64M1__ avr5m3000__AVR_M3000__ -@@ -373,34 +419,70 @@ AVR will be defined as well when using the standard levels gnu89 +@@ -373,34 +410,68 @@ AVR will be defined as well when using the standard levels gnu89 avr5/avr51 [3]at90usb1286__AVR_AT90USB1286__ avr5/avr51 [3]at90usb1287__AVR_AT90USB1287__ avr5/avr51 [3]atmega128__AVR_ATmega128__ @@ -5357,8 +5434,6 @@ index f2b753a..2c10a40 100644 avr6atmega2561__AVR_ATmega2561__ + avr6atmega256rfr2__AVR_ATmega256RFR2__ + avr6atmega2564rfr2__AVR_ATmega2564RFR2__ -+ avr7ata5782__AVR_ATA5782__ -+ avr7ata5831__AVR_ATA5831__ avrxmega2atxmega16a4__AVR_ATxmega16A4__ + avrxmega2atxmega16a4u__AVR_ATxmega16A4U__ @@ -5788,7 +5863,7 @@ index c349463..fc53235 100644 /** * \def assert diff --git a/include/avr/Makefile.am b/include/avr/Makefile.am -index efbef3d..2ae591f 100644 +index efbef3d..6d33b84 100644 --- a/include/avr/Makefile.am +++ b/include/avr/Makefile.am @@ -26,7 +26,7 @@ @@ -5827,7 +5902,7 @@ index efbef3d..2ae591f 100644 ioat94k.h \ iocan32.h \ iocan64.h \ -@@ -71,21 +88,33 @@ avr_HEADERS = \ +@@ -71,21 +88,34 @@ avr_HEADERS = \ iocanxx.h \ iom103.h \ iom128.h \ @@ -5856,12 +5931,13 @@ index efbef3d..2ae591f 100644 + iom168a.h \ iom168p.h \ + iom168pa.h \ ++ iom168pb.h \ iom169.h \ + iom169a.h \ iom169p.h \ iom169pa.h \ iom16hva.h \ -@@ -97,16 +126,32 @@ avr_HEADERS = \ +@@ -97,16 +127,32 @@ avr_HEADERS = \ iom16u4.h \ iom2560.h \ iom2561.h \ @@ -5895,13 +5971,14 @@ index efbef3d..2ae591f 100644 iom32hvb.h \ iom32hvbrevb.h \ iom32c1.h \ -@@ -114,26 +159,42 @@ avr_HEADERS = \ +@@ -114,28 +160,46 @@ avr_HEADERS = \ iom32u2.h \ iom32u4.h \ iom32u6.h \ + iom48a.h \ iom48.h \ + iom48pa.h \ ++ iom48pb.h \ iom48p.h \ iom406.h \ iom64.h \ @@ -5937,8 +6014,11 @@ index efbef3d..2ae591f 100644 + iom88a.h \ iom88p.h \ iom88pa.h \ ++ iom88pb.h \ iom8hva.h \ -@@ -152,8 +213,10 @@ avr_HEADERS = \ + iom8u2.h \ + iomx8.h \ +@@ -152,8 +216,10 @@ avr_HEADERS = \ iotn13a.h \ iotn15.h \ iotn167.h \ @@ -5949,7 +6029,7 @@ index efbef3d..2ae591f 100644 iotn2313.h \ iotn2313a.h \ iotn24.h \ -@@ -168,6 +231,7 @@ avr_HEADERS = \ +@@ -168,6 +234,7 @@ avr_HEADERS = \ iotn43u.h \ iotn44.h \ iotn44a.h \ @@ -5957,7 +6037,7 @@ index efbef3d..2ae591f 100644 iotn45.h \ iotn461.h \ iotn461a.h \ -@@ -175,6 +239,7 @@ avr_HEADERS = \ +@@ -175,6 +242,7 @@ avr_HEADERS = \ iotn88.h \ iotn84.h \ iotn84a.h \ @@ -5965,7 +6045,7 @@ index efbef3d..2ae591f 100644 iotn85.h \ iotn861.h \ iotn861a.h \ -@@ -191,22 +256,50 @@ avr_HEADERS = \ +@@ -191,22 +259,50 @@ avr_HEADERS = \ iousb647.h \ iousbxx6_7.h \ iox64d3.h \ @@ -6016,7 +6096,7 @@ index efbef3d..2ae591f 100644 lock.h \ parity.h \ pgmspace.h \ -@@ -217,7 +310,8 @@ avr_HEADERS = \ +@@ -217,7 +313,8 @@ avr_HEADERS = \ signal.h \ sleep.h \ version.h \ @@ -6149,7 +6229,7 @@ index 7a295a5..2847ceb 100644 #ifndef _AVR_DELAY_H_ #define _AVR_DELAY_H_ diff --git a/include/avr/eeprom.h b/include/avr/eeprom.h -index 8ff9bcf..9ebdf97 100644 +index 8ff9bcf..648498d 100644 --- a/include/avr/eeprom.h +++ b/include/avr/eeprom.h @@ -30,7 +30,7 @@ @@ -6246,8 +6326,7 @@ index 8ff9bcf..9ebdf97 100644 +# define _EEPROM_SUFFIX _m3290pa #elif defined (__AVR_ATmega32HVB__) # define _EEPROM_SUFFIX _m32hvb --#elif defined (__AVR_ATmega32HVBREVB__) -+#elif defined (__AVR_ATmega32HVBrevB__) + #elif defined (__AVR_ATmega32HVBREVB__) # define _EEPROM_SUFFIX _m32hvbrevb #elif defined (__AVR_ATmega64HVE__) # define _EEPROM_SUFFIX _m64hve @@ -6256,7 +6335,7 @@ index 8ff9bcf..9ebdf97 100644 #elif defined (__AVR_ATmega406__) # define _EEPROM_SUFFIX _m406 #elif defined (__AVR_ATmega16__) -@@ -223,18 +253,24 @@ +@@ -223,18 +253,26 @@ # define _EEPROM_SUFFIX _m164 #elif defined (__AVR_ATmega164P__) # define _EEPROM_SUFFIX _m164p @@ -6278,15 +6357,12 @@ index 8ff9bcf..9ebdf97 100644 # define _EEPROM_SUFFIX _m168p +#elif defined (__AVR_ATmega168PA__) +# define _EEPROM_SUFFIX _m168pa ++#elif defined (__AVR_ATmega168PB__) ++# define _EEPROM_SUFFIX _m168pb #elif defined (__AVR_ATmega169__) # define _EEPROM_SUFFIX _m169 #elif defined (__AVR_ATmega169A__) -@@ -251,14 +287,18 @@ - # define _EEPROM_SUFFIX _m16hva2 - #elif defined (__AVR_ATmega16HVB__) - # define _EEPROM_SUFFIX _m16hvb --#elif defined (__AVR_ATmega16HVBREVB__) -+#elif defined (__AVR_ATmega16HVBrevB__) +@@ -255,10 +293,16 @@ # define _EEPROM_SUFFIX _m16hvbrevb #elif defined (__AVR_ATmega8__) # define _EEPROM_SUFFIX _m8 @@ -6298,10 +6374,21 @@ index 8ff9bcf..9ebdf97 100644 # define _EEPROM_SUFFIX _m48a +#elif defined (__AVR_ATmega48PA__) +# define _EEPROM_SUFFIX _m48pa ++#elif defined (__AVR_ATmega48PB__) ++# define _EEPROM_SUFFIX _m48pb #elif defined (__AVR_ATmega48P__) # define _EEPROM_SUFFIX _m48p #elif defined (__AVR_ATmega88__) -@@ -321,10 +361,14 @@ +@@ -269,6 +313,8 @@ + # define _EEPROM_SUFFIX _m88p + #elif defined (__AVR_ATmega88PA__) + # define _EEPROM_SUFFIX _m88pa ++#elif defined (__AVR_ATmega88PB__) ++# define _EEPROM_SUFFIX _m88pb + #elif defined (__AVR_ATmega8515__) + # define _EEPROM_SUFFIX _m8515 + #elif defined (__AVR_ATmega8535__) +@@ -321,10 +367,14 @@ # define _EEPROM_SUFFIX _tn44 #elif defined (__AVR_ATtiny44A__) # define _EEPROM_SUFFIX _tn44a @@ -6316,7 +6403,7 @@ index 8ff9bcf..9ebdf97 100644 #elif defined (__AVR_ATtiny261__) # define _EEPROM_SUFFIX _tn261 #elif defined (__AVR_ATtiny261A__) -@@ -341,50 +385,142 @@ +@@ -341,50 +391,142 @@ # define _EEPROM_SUFFIX _tn43u #elif defined (__AVR_ATtiny48__) # define _EEPROM_SUFFIX _tn48 @@ -6495,7 +6582,7 @@ index 5487f66..ce9a4bd 100644 #ifndef _AVR_INTERRUPT_H_ #define _AVR_INTERRUPT_H_ diff --git a/include/avr/io.h b/include/avr/io.h -index c2dee8a..bd7d761 100644 +index c2dee8a..16a4e94 100644 --- a/include/avr/io.h +++ b/include/avr/io.h @@ -29,7 +29,7 @@ @@ -6543,7 +6630,7 @@ index c2dee8a..bd7d761 100644 #elif defined (__AVR_ATmega2560__) # include #elif defined (__AVR_ATmega2561__) -@@ -178,59 +192,105 @@ +@@ -178,54 +192,100 @@ # include #elif defined (__AVR_AT90USB1287__) # include @@ -6660,13 +6747,7 @@ index c2dee8a..bd7d761 100644 #elif defined (__AVR_ATmega3290P__) # include #elif defined (__AVR_ATmega32HVB__) - # include --#elif defined (__AVR_ATmega32HVBREVB__) -+#elif defined (__AVR_ATmega32HVBrevB__) - # include - #elif defined (__AVR_ATmega406__) - # include -@@ -244,18 +304,32 @@ +@@ -244,18 +304,34 @@ # include #elif defined (__AVR_ATmega163__) # include @@ -6697,6 +6778,8 @@ index c2dee8a..bd7d761 100644 -#elif defined (__AVR_ATmega169__) || defined (__AVR_ATmega169A__) +#elif defined (__AVR_ATmega168PA__) +# include ++#elif defined (__AVR_ATmega168PB__) ++# include +#elif defined (__AVR_ATmega169__) # include +#elif (defined __AVR_ATmega169A__) @@ -6704,12 +6787,7 @@ index c2dee8a..bd7d761 100644 #elif defined (__AVR_ATmega169P__) # include #elif defined (__AVR_ATmega169PA__) -@@ -268,16 +342,24 @@ - # include - #elif defined (__AVR_ATmega16HVB__) - # include --#elif defined (__AVR_ATmega16HVBREVB__) -+#elif defined (__AVR_ATmega16HVBrevB__) +@@ -272,16 +348,28 @@ # include #elif defined (__AVR_ATmega8__) # include @@ -6722,6 +6800,8 @@ index c2dee8a..bd7d761 100644 # include +#elif defined (__AVR_ATmega48PA__) +# include ++#elif defined (__AVR_ATmega48PB__) ++# include #elif defined (__AVR_ATmega48P__) # include -#elif defined (__AVR_ATmega88__) || defined (__AVR_ATmega88A__) @@ -6732,7 +6812,13 @@ index c2dee8a..bd7d761 100644 #elif defined (__AVR_ATmega88P__) # include #elif defined (__AVR_ATmega88PA__) -@@ -346,10 +428,14 @@ + # include ++#elif defined (__AVR_ATmega88PB__) ++# include + #elif defined (__AVR_ATmega8515__) + # include + #elif defined (__AVR_ATmega8535__) +@@ -346,10 +434,14 @@ # include #elif defined (__AVR_ATtiny44A__) # include @@ -6747,7 +6833,7 @@ index c2dee8a..bd7d761 100644 #elif defined (__AVR_ATtiny261__) # include #elif defined (__AVR_ATtiny261A__) -@@ -368,48 +454,140 @@ +@@ -368,48 +460,140 @@ # include #elif defined (__AVR_ATtiny88__) # include @@ -6888,7 +6974,7 @@ index c2dee8a..bd7d761 100644 /* avr1: the following only supported for assembler programs */ #elif defined (__AVR_ATtiny28__) # include -@@ -435,6 +613,10 @@ +@@ -435,6 +619,10 @@ #include @@ -6899,45665 +6985,71036 @@ index c2dee8a..bd7d761 100644 /* Include fuse.h after individual IO header files. */ #include +diff --git a/include/avr/io1200.h b/include/avr/io1200.h +index b215eb6..aeaf7d6 100644 +--- a/include/avr/io1200.h ++++ b/include/avr/io1200.h +@@ -1,273 +1,274 @@ +-/* Copyright (c) 2002, Marek Michalkiewicz +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: io1200.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* avr/io1200.h - definitions for AT90S1200 */ +- +-#ifndef _AVR_IO1200_H_ +-#define _AVR_IO1200_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "io1200.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-#ifndef __ASSEMBLER__ +-# warning "MCU not supported by the C compiler" +-#endif +- +-/* I/O registers */ +- +-/* 0x00..0x07 reserved */ +- +-/* Analog Comparator Control and Status Register */ +-#define ACSR _SFR_IO8(0x08) +- +-/* 0x09..0x0F reserved */ +- +-#define PIND _SFR_IO8(0x10) +-#define DDRD _SFR_IO8(0x11) +-#define PORTD _SFR_IO8(0x12) +- +-/* 0x13..0x15 reserved */ +- +-#define PINB _SFR_IO8(0x16) +-#define DDRB _SFR_IO8(0x17) +-#define PORTB _SFR_IO8(0x18) +- +-/* 0x19..0x1B reserved */ +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO8(0x1E) +-#define EEARL _SFR_IO8(0x1E) +- +-/* 0x1F..0x20 reserved */ +- +-/* Watchdog Timer Control Register */ +-#define WDTCR _SFR_IO8(0x21) +- +-/* 0x22..0x31 reserved */ +- +-#define TCNT0 _SFR_IO8(0x32) +-#define TCCR0 _SFR_IO8(0x33) +- +-/* 0x34 reserved */ +- +-#define MCUCR _SFR_IO8(0x35) +- +-/* 0x36..0x37 reserved */ +- +-/* Timer/Counter Interrupt Flag Register */ +-#define TIFR _SFR_IO8(0x38) +- +-/* Timer/Counter Interrupt MaSK Register */ +-#define TIMSK _SFR_IO8(0x39) +- +-/* 0x3A reserved */ +- +-#define GIMSK _SFR_IO8(0x3B) +- +-/* 0x3C..0x3E reserved */ +- +-/* 0x3F SREG */ +- +-/* Interrupt vectors */ +- +-/* External Interrupt 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 2 +-#define TIMER0_OVF_vect _VECTOR(2) +-#define SIG_OVERFLOW0 _VECTOR(2) +- +-/* Analog Comparator */ +-#define ANA_COMP_vect_num 3 +-#define ANA_COMP_vect _VECTOR(3) +-#define SIG_COMPARATOR _VECTOR(3) +- +-#define _VECTORS_SIZE 8 +- +-/* Bit numbers */ +- +-/* GIMSK */ +-#define INT0 6 +- +-/* TIMSK */ +-#define TOIE0 1 +- +-/* TIFR */ +-#define TOV0 1 +- +-/* MCUCR */ +-#define SE 5 +-#define SM 4 +-#define ISC01 1 +-#define ISC00 0 +- +-/* TCCR0 */ +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* WDTCR */ +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* EECR */ +-#undef EEMWE +- +-/* +- PB7 = SCK +- PB6 = MISO +- PB5 = MOSI +- PB1 = AIN1 +- PB0 = AIN0 +- */ +- +-/* PORTB */ +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* DDRB */ +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* PINB */ +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* PORTD */ +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* DDRD */ +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-/* PIND */ +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-/* ACSR */ +-#define ACD 7 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIS1 1 +-#define ACIS0 0 +- +-/* EEPROM Control Register */ +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-#undef ZH +- +-/* Last memory addresses */ +-#define RAMEND 0x1F +-#define XRAMEND 0x0 +-#define E2END 0x3F +-#define E2PAGESIZE 0 +-#define FLASHEND 0x3FF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 1 +- +-/* Low Fuse Byte */ +-#define FUSE_RCEN (unsigned char)~_BV(0) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define LFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x90 +-#define SIGNATURE_2 0x01 +- +- +-#endif /* _AVR_IO1200_H_ */ ++/* Copyright (c) 2002, Marek Michalkiewicz ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: io1200.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* avr/io1200.h - definitions for AT90S1200 */ ++ ++#ifndef _AVR_IO1200_H_ ++#define _AVR_IO1200_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "io1200.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef __ASSEMBLER__ ++# warning "MCU not supported by the C compiler" ++#endif ++ ++/* I/O registers */ ++ ++/* 0x00..0x07 reserved */ ++ ++/* Analog Comparator Control and Status Register */ ++#define ACSR _SFR_IO8(0x08) ++ ++/* 0x09..0x0F reserved */ ++ ++#define PIND _SFR_IO8(0x10) ++#define DDRD _SFR_IO8(0x11) ++#define PORTD _SFR_IO8(0x12) ++ ++/* 0x13..0x15 reserved */ ++ ++#define PINB _SFR_IO8(0x16) ++#define DDRB _SFR_IO8(0x17) ++#define PORTB _SFR_IO8(0x18) ++ ++/* 0x19..0x1B reserved */ ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO8(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++ ++/* 0x1F..0x20 reserved */ ++ ++/* Watchdog Timer Control Register */ ++#define WDTCR _SFR_IO8(0x21) ++ ++/* 0x22..0x31 reserved */ ++ ++#define TCNT0 _SFR_IO8(0x32) ++#define TCCR0 _SFR_IO8(0x33) ++ ++/* 0x34 reserved */ ++ ++#define MCUCR _SFR_IO8(0x35) ++ ++/* 0x36..0x37 reserved */ ++ ++/* Timer/Counter Interrupt Flag Register */ ++#define TIFR _SFR_IO8(0x38) ++ ++/* Timer/Counter Interrupt MaSK Register */ ++#define TIMSK _SFR_IO8(0x39) ++ ++/* 0x3A reserved */ ++ ++#define GIMSK _SFR_IO8(0x3B) ++ ++/* 0x3C..0x3E reserved */ ++ ++/* 0x3F SREG */ ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 2 ++#define TIMER0_OVF_vect _VECTOR(2) ++#define SIG_OVERFLOW0 _VECTOR(2) ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect_num 3 ++#define ANA_COMP_vect _VECTOR(3) ++#define SIG_COMPARATOR _VECTOR(3) ++ ++#define _VECTORS_SIZE 8 ++ ++/* Bit numbers */ ++ ++/* GIMSK */ ++#define INT0 6 ++ ++/* TIMSK */ ++#define TOIE0 1 ++ ++/* TIFR */ ++#define TOV0 1 ++ ++/* MCUCR */ ++#define SE 5 ++#define SM 4 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* TCCR0 */ ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* WDTCR */ ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* EECR */ ++#undef EEMWE ++ ++/* ++ PB7 = SCK ++ PB6 = MISO ++ PB5 = MOSI ++ PB1 = AIN1 ++ PB0 = AIN0 ++ */ ++ ++/* PORTB */ ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* DDRB */ ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* PINB */ ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* PORTD */ ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* DDRD */ ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++/* PIND */ ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++/* ACSR */ ++#define ACD 7 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++/* EEPROM Control Register */ ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++#undef ZH ++ ++#define RAMSTART 0x60 ++/* Last memory addresses */ ++#define RAMEND 0x1F ++#define XRAMEND 0x0 ++#define E2END 0x3F ++#define E2PAGESIZE 0 ++#define FLASHEND 0x3FF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Low Fuse Byte */ ++#define FUSE_RCEN (unsigned char)~_BV(0) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define LFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x90 ++#define SIGNATURE_2 0x01 ++ ++ ++#endif /* _AVR_IO1200_H_ */ +diff --git a/include/avr/io2313.h b/include/avr/io2313.h +index c105dd8..ad88345 100644 +--- a/include/avr/io2313.h ++++ b/include/avr/io2313.h +@@ -1,381 +1,382 @@ +-/* Copyright (c) 2002, Marek Michalkiewicz +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: io2313.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* avr/io2313.h - definitions for AT90S2313 */ +- +-#ifndef _AVR_IO2313_H_ +-#define _AVR_IO2313_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "io2313.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* Analog Comparator Control and Status Register */ +-#define ACSR _SFR_IO8(0x08) +- +-/* UART Baud Rate Register */ +-#define UBRR _SFR_IO8(0x09) +- +-/* UART Control Register */ +-#define UCR _SFR_IO8(0x0A) +- +-/* UART Status Register */ +-#define USR _SFR_IO8(0x0B) +- +-/* UART I/O Data Register */ +-#define UDR _SFR_IO8(0x0C) +- +-/* Input Pins, Port D */ +-#define PIND _SFR_IO8(0x10) +- +-/* Data Direction Register, Port D */ +-#define DDRD _SFR_IO8(0x11) +- +-/* Data Register, Port D */ +-#define PORTD _SFR_IO8(0x12) +- +-/* Input Pins, Port B */ +-#define PINB _SFR_IO8(0x16) +- +-/* Data Direction Register, Port B */ +-#define DDRB _SFR_IO8(0x17) +- +-/* Data Register, Port B */ +-#define PORTB _SFR_IO8(0x18) +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO8(0x1E) +-#define EEARL _SFR_IO8(0x1E) +- +-/* Watchdog Timer Control Register */ +-#define WDTCR _SFR_IO8(0x21) +- +-/* T/C 1 Input Capture Register */ +-#define ICR1 _SFR_IO16(0x24) +-#define ICR1L _SFR_IO8(0x24) +-#define ICR1H _SFR_IO8(0x25) +- +-/* Output Compare Register 1 */ +-#define OCR1 _SFR_IO16(0x2A) +-#define OCR1L _SFR_IO8(0x2A) +-#define OCR1H _SFR_IO8(0x2B) +-#define OCR1A _SFR_IO16(0x2A) +-#define OCR1AL _SFR_IO8(0x2A) +-#define OCR1AH _SFR_IO8(0x2B) +- +-/* Timer/Counter 1 */ +-#define TCNT1 _SFR_IO16(0x2C) +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1H _SFR_IO8(0x2D) +- +-/* Timer/Counter 1 Control and Status Register */ +-#define TCCR1B _SFR_IO8(0x2E) +- +-/* Timer/Counter 1 Control Register */ +-#define TCCR1A _SFR_IO8(0x2F) +- +-/* Timer/Counter 0 */ +-#define TCNT0 _SFR_IO8(0x32) +- +-/* Timer/Counter 0 Control Register */ +-#define TCCR0 _SFR_IO8(0x33) +- +-/* MCU general Control Register */ +-#define MCUCR _SFR_IO8(0x35) +- +-/* Timer/Counter Interrupt Flag register */ +-#define TIFR _SFR_IO8(0x38) +- +-/* Timer/Counter Interrupt MaSK register */ +-#define TIMSK _SFR_IO8(0x39) +- +-/* General Interrupt Flag Register */ +-#define GIFR _SFR_IO8(0x3A) +- +-/* General Interrupt MaSK register */ +-#define GIMSK _SFR_IO8(0x3B) +- +-/* 0x3C..0x3D SP */ +- +-/* 0x3F SREG */ +- +-/* Interrupt vectors */ +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt Request 1 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +-#define SIG_INTERRUPT1 _VECTOR(2) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT1_vect_num 3 +-#define TIMER1_CAPT1_vect _VECTOR(3) +-#define SIG_INPUT_CAPTURE1 _VECTOR(3) +- +-/* Timer/Counter1 Compare Match */ +-#define TIMER1_COMP1_vect_num 4 +-#define TIMER1_COMP1_vect _VECTOR(4) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(4) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF1_vect_num 5 +-#define TIMER1_OVF1_vect _VECTOR(5) +-#define SIG_OVERFLOW1 _VECTOR(5) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF0_vect_num 6 +-#define TIMER0_OVF0_vect _VECTOR(6) +-#define SIG_OVERFLOW0 _VECTOR(6) +- +-/* UART, Rx Complete */ +-#define UART_RX_vect_num 7 +-#define UART_RX_vect _VECTOR(7) +-#define SIG_UART_RECV _VECTOR(7) +- +-/* UART Data Register Empty */ +-#define UART_UDRE_vect_num 8 +-#define UART_UDRE_vect _VECTOR(8) +-#define SIG_UART_DATA _VECTOR(8) +- +-/* UART, Tx Complete */ +-#define UART_TX_vect_num 9 +-#define UART_TX_vect _VECTOR(9) +-#define SIG_UART_TRANS _VECTOR(9) +- +-/* Analog Comparator */ +-#define ANA_COMP_vect_num 10 +-#define ANA_COMP_vect _VECTOR(10) +-#define SIG_COMPARATOR _VECTOR(10) +- +-#define _VECTORS_SIZE 22 +- +-/* +- * The Register Bit names are represented by their bit number (0-7). +- */ +- +-/* General Interrupt MaSK register */ +-#define INT1 7 +-#define INT0 6 +- +-/* General Interrupt Flag Register */ +-#define INTF1 7 +-#define INTF0 6 +- +-/* Timer/Counter Interrupt MaSK register */ +-#define TOIE1 7 +-#define OCIE1A 6 +-#define TICIE 3 /* old name */ +-#define TICIE1 3 +-#define TOIE0 1 +- +-/* Timer/Counter Interrupt Flag register */ +-#define TOV1 7 +-#define OCF1A 6 +-#define ICF1 3 +-#define TOV0 1 +- +-/* MCU general Control Register */ +-#define SE 5 +-#define SM 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-/* Timer/Counter 0 Control Register */ +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* Timer/Counter 1 Control Register */ +-#define COM1A1 7 +-#define COM1A0 6 +-#define PWM11 1 +-#define PWM10 0 +- +-/* Timer/Counter 1 Control and Status Register */ +-#define ICNC1 7 +-#define ICES1 6 +-#define CTC1 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* Watchdog Timer Control Register */ +-#define WDTOE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* EEPROM Control Register */ +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-/* Data Register, Port B */ +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* Data Direction Register, Port B */ +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* Input Pins, Port B */ +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* Data Register, Port D */ +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* Data Direction Register, Port D */ +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-/* Input Pins, Port D */ +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-/* UART Status Register */ +-#define RXC 7 +-#define TXC 6 +-#define UDRE 5 +-#define FE 4 +-#define DOR 3 +- +-/* UART Control Register */ +-#define RXCIE 7 +-#define TXCIE 6 +-#define UDRIE 5 +-#define RXEN 4 +-#define TXEN 3 +-#define CHR9 2 +-#define RXB8 1 +-#define TXB8 0 +- +-/* Analog Comparator Control and Status Register */ +-#define ACD 7 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +- +-/* EEPROM Control Register */ +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-/* Constants */ +-#define RAMEND 0xDF +-#define XRAMEND RAMEND +-#define E2END 0x7F +-#define E2PAGESIZE 0 +-#define FLASHEND 0x07FF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 1 +- +-/* Low Fuse Byte */ +-#define FUSE_FSTRT (unsigned char)~_BV(0) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define LFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x91 +-#define SIGNATURE_2 0x01 +- +- +-#endif /* _AVR_IO2313_H_ */ ++/* Copyright (c) 2002, Marek Michalkiewicz ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: io2313.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* avr/io2313.h - definitions for AT90S2313 */ ++ ++#ifndef _AVR_IO2313_H_ ++#define _AVR_IO2313_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "io2313.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* Analog Comparator Control and Status Register */ ++#define ACSR _SFR_IO8(0x08) ++ ++/* UART Baud Rate Register */ ++#define UBRR _SFR_IO8(0x09) ++ ++/* UART Control Register */ ++#define UCR _SFR_IO8(0x0A) ++ ++/* UART Status Register */ ++#define USR _SFR_IO8(0x0B) ++ ++/* UART I/O Data Register */ ++#define UDR _SFR_IO8(0x0C) ++ ++/* Input Pins, Port D */ ++#define PIND _SFR_IO8(0x10) ++ ++/* Data Direction Register, Port D */ ++#define DDRD _SFR_IO8(0x11) ++ ++/* Data Register, Port D */ ++#define PORTD _SFR_IO8(0x12) ++ ++/* Input Pins, Port B */ ++#define PINB _SFR_IO8(0x16) ++ ++/* Data Direction Register, Port B */ ++#define DDRB _SFR_IO8(0x17) ++ ++/* Data Register, Port B */ ++#define PORTB _SFR_IO8(0x18) ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO8(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++ ++/* Watchdog Timer Control Register */ ++#define WDTCR _SFR_IO8(0x21) ++ ++/* T/C 1 Input Capture Register */ ++#define ICR1 _SFR_IO16(0x24) ++#define ICR1L _SFR_IO8(0x24) ++#define ICR1H _SFR_IO8(0x25) ++ ++/* Output Compare Register 1 */ ++#define OCR1 _SFR_IO16(0x2A) ++#define OCR1L _SFR_IO8(0x2A) ++#define OCR1H _SFR_IO8(0x2B) ++#define OCR1A _SFR_IO16(0x2A) ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++ ++/* Timer/Counter 1 */ ++#define TCNT1 _SFR_IO16(0x2C) ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++ ++/* Timer/Counter 1 Control and Status Register */ ++#define TCCR1B _SFR_IO8(0x2E) ++ ++/* Timer/Counter 1 Control Register */ ++#define TCCR1A _SFR_IO8(0x2F) ++ ++/* Timer/Counter 0 */ ++#define TCNT0 _SFR_IO8(0x32) ++ ++/* Timer/Counter 0 Control Register */ ++#define TCCR0 _SFR_IO8(0x33) ++ ++/* MCU general Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++ ++/* Timer/Counter Interrupt Flag register */ ++#define TIFR _SFR_IO8(0x38) ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define TIMSK _SFR_IO8(0x39) ++ ++/* General Interrupt Flag Register */ ++#define GIFR _SFR_IO8(0x3A) ++ ++/* General Interrupt MaSK register */ ++#define GIMSK _SFR_IO8(0x3B) ++ ++/* 0x3C..0x3D SP */ ++ ++/* 0x3F SREG */ ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++#define SIG_INTERRUPT1 _VECTOR(2) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT1_vect_num 3 ++#define TIMER1_CAPT1_vect _VECTOR(3) ++#define SIG_INPUT_CAPTURE1 _VECTOR(3) ++ ++/* Timer/Counter1 Compare Match */ ++#define TIMER1_COMP1_vect_num 4 ++#define TIMER1_COMP1_vect _VECTOR(4) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(4) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF1_vect_num 5 ++#define TIMER1_OVF1_vect _VECTOR(5) ++#define SIG_OVERFLOW1 _VECTOR(5) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF0_vect_num 6 ++#define TIMER0_OVF0_vect _VECTOR(6) ++#define SIG_OVERFLOW0 _VECTOR(6) ++ ++/* UART, Rx Complete */ ++#define UART_RX_vect_num 7 ++#define UART_RX_vect _VECTOR(7) ++#define SIG_UART_RECV _VECTOR(7) ++ ++/* UART Data Register Empty */ ++#define UART_UDRE_vect_num 8 ++#define UART_UDRE_vect _VECTOR(8) ++#define SIG_UART_DATA _VECTOR(8) ++ ++/* UART, Tx Complete */ ++#define UART_TX_vect_num 9 ++#define UART_TX_vect _VECTOR(9) ++#define SIG_UART_TRANS _VECTOR(9) ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect_num 10 ++#define ANA_COMP_vect _VECTOR(10) ++#define SIG_COMPARATOR _VECTOR(10) ++ ++#define _VECTORS_SIZE 22 ++ ++/* ++ * The Register Bit names are represented by their bit number (0-7). ++ */ ++ ++/* General Interrupt MaSK register */ ++#define INT1 7 ++#define INT0 6 ++ ++/* General Interrupt Flag Register */ ++#define INTF1 7 ++#define INTF0 6 ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define TOIE1 7 ++#define OCIE1A 6 ++#define TICIE 3 /* old name */ ++#define TICIE1 3 ++#define TOIE0 1 ++ ++/* Timer/Counter Interrupt Flag register */ ++#define TOV1 7 ++#define OCF1A 6 ++#define ICF1 3 ++#define TOV0 1 ++ ++/* MCU general Control Register */ ++#define SE 5 ++#define SM 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* Timer/Counter 0 Control Register */ ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* Timer/Counter 1 Control Register */ ++#define COM1A1 7 ++#define COM1A0 6 ++#define PWM11 1 ++#define PWM10 0 ++ ++/* Timer/Counter 1 Control and Status Register */ ++#define ICNC1 7 ++#define ICES1 6 ++#define CTC1 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* Watchdog Timer Control Register */ ++#define WDTOE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* EEPROM Control Register */ ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++/* Data Register, Port B */ ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* Data Direction Register, Port B */ ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* Input Pins, Port B */ ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* Data Register, Port D */ ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* Data Direction Register, Port D */ ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++/* Input Pins, Port D */ ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++/* UART Status Register */ ++#define RXC 7 ++#define TXC 6 ++#define UDRE 5 ++#define FE 4 ++#define DOR 3 ++ ++/* UART Control Register */ ++#define RXCIE 7 ++#define TXCIE 6 ++#define UDRIE 5 ++#define RXEN 4 ++#define TXEN 3 ++#define CHR9 2 ++#define RXB8 1 ++#define TXB8 0 ++ ++/* Analog Comparator Control and Status Register */ ++#define ACD 7 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++/* EEPROM Control Register */ ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++/* Constants */ ++#define RAMSTART 0x60 ++#define RAMEND 0xDF ++#define XRAMEND RAMEND ++#define E2END 0x7F ++#define E2PAGESIZE 0 ++#define FLASHEND 0x07FF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Low Fuse Byte */ ++#define FUSE_FSTRT (unsigned char)~_BV(0) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define LFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x91 ++#define SIGNATURE_2 0x01 ++ ++ ++#endif /* _AVR_IO2313_H_ */ +diff --git a/include/avr/io2323.h b/include/avr/io2323.h +index e7886ca..d0fac3f 100644 +--- a/include/avr/io2323.h ++++ b/include/avr/io2323.h +@@ -1,206 +1,207 @@ +-/* Copyright (c) 2002, Marek Michalkiewicz +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: io2323.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* avr/io2323.h - definitions for AT90S2323 */ +- +-#ifndef _AVR_IO2323_H_ +-#define _AVR_IO2323_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "io2323.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* Input Pins, Port B */ +-#define PINB _SFR_IO8(0x16) +- +-/* Data Direction Register, Port B */ +-#define DDRB _SFR_IO8(0x17) +- +-/* Data Register, Port B */ +-#define PORTB _SFR_IO8(0x18) +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO8(0x1E) +-#define EEARL _SFR_IO8(0x1E) +- +-/* Watchdog Timer Control Register */ +-#define WDTCR _SFR_IO8(0x21) +- +-/* Timer/Counter 0 */ +-#define TCNT0 _SFR_IO8(0x32) +- +-/* Timer/Counter 0 Control Register */ +-#define TCCR0 _SFR_IO8(0x33) +- +-/* MCU Status Register */ +-#define MCUSR _SFR_IO8(0x34) +- +-/* MCU general Control Register */ +-#define MCUCR _SFR_IO8(0x35) +- +-/* Timer/Counter Interrupt Flag register */ +-#define TIFR _SFR_IO8(0x38) +- +-/* Timer/Counter Interrupt MaSK register */ +-#define TIMSK _SFR_IO8(0x39) +- +-/* General Interrupt Flag register */ +-#define GIFR _SFR_IO8(0x3A) +- +-/* General Interrupt MaSK register */ +-#define GIMSK _SFR_IO8(0x3B) +- +-/* 0x3D..0x3E SP */ +- +-/* 0x3F SREG */ +- +-/* Interrupt vectors */ +- +-/* External Interrupt 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF0_vect_num 2 +-#define TIMER0_OVF0_vect _VECTOR(2) +-#define SIG_OVERFLOW0 _VECTOR(2) +- +-#define _VECTORS_SIZE 6 +- +-/* +- The Register Bit names are represented by their bit number (0-7). +- */ +- +-/* General Interrupt MaSK register */ +-#define INT0 6 +-#define INTF0 6 +- +-/* General Interrupt Flag Register */ +-#define TOIE0 1 +-#define TOV0 1 +- +-/* MCU general Control Register */ +-#define SE 5 +-#define SM 4 +-#define ISC01 1 +-#define ISC00 0 +- +-/* Timer/Counter 0 Control Register */ +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* Watchdog Timer Control Register */ +-#define WDTOE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* +- PB2 = SCK/T0 +- PB1 = MISO/INT0 +- PB0 = MOSI +- */ +- +-/* Data Register, Port B */ +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* Data Direction Register, Port B */ +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* Input Pins, Port B */ +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* EEPROM Control Register */ +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-/* Constants */ +-#define RAMEND 0xDF +-#define XRAMEND RAMEND +-#define E2END 0x7F +-#define E2PAGESIZE 0 +-#define FLASHEND 0x07FF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 1 +- +-/* Low Fuse Byte */ +-#define FUSE_FSTRT (unsigned char)~_BV(0) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define LFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x91 +-#define SIGNATURE_2 0x02 +- +- +-#endif /* _AVR_IO2323_H_ */ +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x91 +-#define SIGNATURE_2 0x02 +- ++/* Copyright (c) 2002, Marek Michalkiewicz ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: io2323.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* avr/io2323.h - definitions for AT90S2323 */ ++ ++#ifndef _AVR_IO2323_H_ ++#define _AVR_IO2323_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "io2323.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* Input Pins, Port B */ ++#define PINB _SFR_IO8(0x16) ++ ++/* Data Direction Register, Port B */ ++#define DDRB _SFR_IO8(0x17) ++ ++/* Data Register, Port B */ ++#define PORTB _SFR_IO8(0x18) ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO8(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++ ++/* Watchdog Timer Control Register */ ++#define WDTCR _SFR_IO8(0x21) ++ ++/* Timer/Counter 0 */ ++#define TCNT0 _SFR_IO8(0x32) ++ ++/* Timer/Counter 0 Control Register */ ++#define TCCR0 _SFR_IO8(0x33) ++ ++/* MCU Status Register */ ++#define MCUSR _SFR_IO8(0x34) ++ ++/* MCU general Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++ ++/* Timer/Counter Interrupt Flag register */ ++#define TIFR _SFR_IO8(0x38) ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define TIMSK _SFR_IO8(0x39) ++ ++/* General Interrupt Flag register */ ++#define GIFR _SFR_IO8(0x3A) ++ ++/* General Interrupt MaSK register */ ++#define GIMSK _SFR_IO8(0x3B) ++ ++/* 0x3D..0x3E SP */ ++ ++/* 0x3F SREG */ ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF0_vect_num 2 ++#define TIMER0_OVF0_vect _VECTOR(2) ++#define SIG_OVERFLOW0 _VECTOR(2) ++ ++#define _VECTORS_SIZE 6 ++ ++/* ++ The Register Bit names are represented by their bit number (0-7). ++ */ ++ ++/* General Interrupt MaSK register */ ++#define INT0 6 ++#define INTF0 6 ++ ++/* General Interrupt Flag Register */ ++#define TOIE0 1 ++#define TOV0 1 ++ ++/* MCU general Control Register */ ++#define SE 5 ++#define SM 4 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* Timer/Counter 0 Control Register */ ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* Watchdog Timer Control Register */ ++#define WDTOE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* ++ PB2 = SCK/T0 ++ PB1 = MISO/INT0 ++ PB0 = MOSI ++ */ ++ ++/* Data Register, Port B */ ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* Data Direction Register, Port B */ ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* Input Pins, Port B */ ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* EEPROM Control Register */ ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++/* Constants */ ++#define RAMSTART 0x60 ++#define RAMEND 0xDF ++#define XRAMEND RAMEND ++#define E2END 0x7F ++#define E2PAGESIZE 0 ++#define FLASHEND 0x07FF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Low Fuse Byte */ ++#define FUSE_FSTRT (unsigned char)~_BV(0) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define LFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x91 ++#define SIGNATURE_2 0x02 ++ ++ ++#endif /* _AVR_IO2323_H_ */ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x91 ++#define SIGNATURE_2 0x02 ++ +diff --git a/include/avr/io2333.h b/include/avr/io2333.h +index 157018c..6d49d8c 100644 +--- a/include/avr/io2333.h ++++ b/include/avr/io2333.h +@@ -1,457 +1,458 @@ +-/* Copyright (c) 2002, Marek Michalkiewicz +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: io2333.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* avr/io2333.h - definitions for AT90S2333 */ +- +-#ifndef _AVR_IO2333_H_ +-#define _AVR_IO2333_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "io2333.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* UART Baud Rate Register high */ +-#define UBRRH _SFR_IO8(0x03) +- +-/* ADC Data register */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x04) +-#endif +-#define ADCW _SFR_IO16(0x04) +-#define ADCL _SFR_IO8(0x04) +-#define ADCH _SFR_IO8(0x05) +- +-/* ADC Control and Status Register */ +-#define ADCSR _SFR_IO8(0x06) +- +-/* ADC MUX */ +-#define ADMUX _SFR_IO8(0x07) +- +-/* Analog Comparator Control and Status Register */ +-#define ACSR _SFR_IO8(0x08) +- +-/* UART Baud Rate Register */ +-#define UBRR _SFR_IO8(0x09) +- +-/* UART Control/Status Registers */ +-#define UCSRB _SFR_IO8(0x0A) +-#define UCSRA _SFR_IO8(0x0B) +- +-/* UART I/O Data Register */ +-#define UDR _SFR_IO8(0x0C) +- +-/* SPI Control Register */ +-#define SPCR _SFR_IO8(0x0D) +- +-/* SPI Status Register */ +-#define SPSR _SFR_IO8(0x0E) +- +-/* SPI I/O Data Register */ +-#define SPDR _SFR_IO8(0x0F) +- +-/* Input Pins, Port D */ +-#define PIND _SFR_IO8(0x10) +- +-/* Data Direction Register, Port D */ +-#define DDRD _SFR_IO8(0x11) +- +-/* Data Register, Port D */ +-#define PORTD _SFR_IO8(0x12) +- +-/* Input Pins, Port C */ +-#define PINC _SFR_IO8(0x13) +- +-/* Data Direction Register, Port C */ +-#define DDRC _SFR_IO8(0x14) +- +-/* Data Register, Port C */ +-#define PORTC _SFR_IO8(0x15) +- +-/* Input Pins, Port B */ +-#define PINB _SFR_IO8(0x16) +- +-/* Data Direction Register, Port B */ +-#define DDRB _SFR_IO8(0x17) +- +-/* Data Register, Port B */ +-#define PORTB _SFR_IO8(0x18) +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO8(0x1E) +-#define EEARL _SFR_IO8(0x1E) +- +-/* Watchdog Timer Control Register */ +-#define WDTCR _SFR_IO8(0x21) +- +-/* T/C 1 Input Capture Register */ +-#define ICR1 _SFR_IO16(0x26) +-#define ICR1L _SFR_IO8(0x26) +-#define ICR1H _SFR_IO8(0x27) +- +-/* Timer/Counter1 Output Compare Register A */ +-#define OCR1 _SFR_IO16(0x2A) +-#define OCR1L _SFR_IO8(0x2A) +-#define OCR1H _SFR_IO8(0x2B) +- +-/* Timer/Counter 1 */ +-#define TCNT1 _SFR_IO16(0x2C) +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1H _SFR_IO8(0x2D) +- +-/* Timer/Counter 1 Control and Status Register */ +-#define TCCR1B _SFR_IO8(0x2E) +- +-/* Timer/Counter 1 Control Register */ +-#define TCCR1A _SFR_IO8(0x2F) +- +-/* Timer/Counter 0 */ +-#define TCNT0 _SFR_IO8(0x32) +- +-/* Timer/Counter 0 Control Register */ +-#define TCCR0 _SFR_IO8(0x33) +- +-/* MCU general Status Register */ +-#define MCUSR _SFR_IO8(0x34) +- +-/* MCU general Control Register */ +-#define MCUCR _SFR_IO8(0x35) +- +-/* Timer/Counter Interrupt Flag register */ +-#define TIFR _SFR_IO8(0x38) +- +-/* Timer/Counter Interrupt MaSK register */ +-#define TIMSK _SFR_IO8(0x39) +- +-/* General Interrupt Flag Register */ +-#define GIFR _SFR_IO8(0x3A) +- +-/* General Interrupt MaSK register */ +-#define GIMSK _SFR_IO8(0x3B) +- +-/* Interrupt vectors */ +- +-/* External Interrupt 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt 1 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +-#define SIG_INTERRUPT1 _VECTOR(2) +- +-/* Timer/Counter Capture Event */ +-#define TIMER1_CAPT_vect_num 3 +-#define TIMER1_CAPT_vect _VECTOR(3) +-#define SIG_INPUT_CAPTURE1 _VECTOR(3) +- +-/* Timer/Counter1 Compare Match */ +-#define TIMER1_COMP_vect_num 4 +-#define TIMER1_COMP_vect _VECTOR(4) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(4) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 5 +-#define TIMER1_OVF_vect _VECTOR(5) +-#define SIG_OVERFLOW1 _VECTOR(5) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 6 +-#define TIMER0_OVF_vect _VECTOR(6) +-#define SIG_OVERFLOW0 _VECTOR(6) +- +-/* Serial Transfer Complete */ +-#define SPI_STC_vect_num 7 +-#define SPI_STC_vect _VECTOR(7) +-#define SIG_SPI _VECTOR(7) +- +-/* UART, Rx Complete */ +-#define UART_RX_vect_num 8 +-#define UART_RX_vect _VECTOR(8) +-#define SIG_UART_RECV _VECTOR(8) +- +-/* UART Data Register Empty */ +-#define UART_UDRE_vect_num 9 +-#define UART_UDRE_vect _VECTOR(9) +-#define SIG_UART_DATA _VECTOR(9) +- +-/* UART, Tx Complete */ +-#define UART_TX_vect_num 10 +-#define UART_TX_vect _VECTOR(10) +-#define SIG_UART_TRANS _VECTOR(10) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 11 +-#define ADC_vect _VECTOR(11) +-#define SIG_ADC _VECTOR(11) +- +-/* EEPROM Ready */ +-#define EE_RDY_vect_num 12 +-#define EE_RDY_vect _VECTOR(12) +-#define SIG_EEPROM_READY _VECTOR(12) +- +-/* Analog Comparator */ +-#define ANA_COMP_vect_num 13 +-#define ANA_COMP_vect _VECTOR(13) +-#define SIG_COMPARATOR _VECTOR(13) +- +-#define _VECTORS_SIZE 28 +- +-/* +- The Register Bit names are represented by their bit number (0-7). +-*/ +- +-/* MCU general Status Register */ +-#define WDRF 3 +-#define BORF 2 +-#define EXTRF 1 +-#define PORF 0 +- +-/* General Interrupt MaSK register */ +-#define INT1 7 +-#define INT0 6 +- +-/* General Interrupt Flag Register */ +-#define INTF1 7 +-#define INTF0 6 +- +-/* Timer/Counter Interrupt MaSK register */ +-#define TOIE1 7 +-#define OCIE1 6 +-#define TICIE1 3 +-#define TOIE0 1 +- +-/* Timer/Counter Interrupt Flag register */ +-#define TOV1 7 +-#define OCF1 6 +-#define ICF1 3 +-#define TOV0 1 +- +-/* MCU general Control Register */ +-#define SE 5 +-#define SM 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-/* Timer/Counter 0 Control Register */ +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* Timer/Counter 1 Control Register */ +-#define COM11 7 +-#define COM10 6 +-#define PWM11 1 +-#define PWM10 0 +- +-/* Timer/Counter 1 Control and Status Register */ +-#define ICNC1 7 +-#define ICES1 6 +-#define CTC1 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* Watchdog Timer Control Register */ +-#define WDTOE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* SPI Control Register */ +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +-/* SPI Status Register */ +-#define SPIF 7 +-#define WCOL 6 +- +-/* UART Status Register */ +-#define RXC 7 +-#define TXC 6 +-#define UDRE 5 +-#define FE 4 +-#define DOR 3 +-#define MPCM 0 +- +-/* UART Control Register */ +-#define RXCIE 7 +-#define TXCIE 6 +-#define UDRIE 5 +-#define RXEN 4 +-#define TXEN 3 +-#define CHR9 2 +-#define RXB8 1 +-#define TXB8 0 +- +-/* Analog Comparator Control and Status Register */ +-#define ACD 7 +-#define AINBG 6 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +- +-/* ADC MUX */ +-#define ACDBG 6 +-#define MUX2 2 +-#define MUX1 1 +-#define MUX0 0 +- +-/* ADC Control and Status Register */ +-#define ADEN 7 +-#define ADSC 6 +-#define ADFR 5 +-#define ADIF 4 +-#define ADIE 3 +-#define ADPS2 2 +-#define ADPS1 1 +-#define ADPS0 0 +- +-/* Data Register, Port B */ +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* Data Direction Register, Port B */ +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* Input Pins, Port B */ +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* Data Register, Port C */ +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-/* Data Direction Register, Port C */ +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-/* Input Pins, Port C */ +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-/* Data Register, Port D */ +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* Data Direction Register, Port D */ +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-/* Input Pins, Port D */ +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-/* EEPROM Control Register */ +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-/* Constants */ +-#define RAMEND 0xDF /*Last On-Chip SRAM location*/ +-#define XRAMEND RAMEND +-#define E2END 0x7F +-#define FLASHEND 0x7FF +- +-#endif /* _AVR_IO2333_H_ */ ++/* Copyright (c) 2002, Marek Michalkiewicz ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: io2333.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* avr/io2333.h - definitions for AT90S2333 */ ++ ++#ifndef _AVR_IO2333_H_ ++#define _AVR_IO2333_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "io2333.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* UART Baud Rate Register high */ ++#define UBRRH _SFR_IO8(0x03) ++ ++/* ADC Data register */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCW _SFR_IO16(0x04) ++#define ADCL _SFR_IO8(0x04) ++#define ADCH _SFR_IO8(0x05) ++ ++/* ADC Control and Status Register */ ++#define ADCSR _SFR_IO8(0x06) ++ ++/* ADC MUX */ ++#define ADMUX _SFR_IO8(0x07) ++ ++/* Analog Comparator Control and Status Register */ ++#define ACSR _SFR_IO8(0x08) ++ ++/* UART Baud Rate Register */ ++#define UBRR _SFR_IO8(0x09) ++ ++/* UART Control/Status Registers */ ++#define UCSRB _SFR_IO8(0x0A) ++#define UCSRA _SFR_IO8(0x0B) ++ ++/* UART I/O Data Register */ ++#define UDR _SFR_IO8(0x0C) ++ ++/* SPI Control Register */ ++#define SPCR _SFR_IO8(0x0D) ++ ++/* SPI Status Register */ ++#define SPSR _SFR_IO8(0x0E) ++ ++/* SPI I/O Data Register */ ++#define SPDR _SFR_IO8(0x0F) ++ ++/* Input Pins, Port D */ ++#define PIND _SFR_IO8(0x10) ++ ++/* Data Direction Register, Port D */ ++#define DDRD _SFR_IO8(0x11) ++ ++/* Data Register, Port D */ ++#define PORTD _SFR_IO8(0x12) ++ ++/* Input Pins, Port C */ ++#define PINC _SFR_IO8(0x13) ++ ++/* Data Direction Register, Port C */ ++#define DDRC _SFR_IO8(0x14) ++ ++/* Data Register, Port C */ ++#define PORTC _SFR_IO8(0x15) ++ ++/* Input Pins, Port B */ ++#define PINB _SFR_IO8(0x16) ++ ++/* Data Direction Register, Port B */ ++#define DDRB _SFR_IO8(0x17) ++ ++/* Data Register, Port B */ ++#define PORTB _SFR_IO8(0x18) ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO8(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++ ++/* Watchdog Timer Control Register */ ++#define WDTCR _SFR_IO8(0x21) ++ ++/* T/C 1 Input Capture Register */ ++#define ICR1 _SFR_IO16(0x26) ++#define ICR1L _SFR_IO8(0x26) ++#define ICR1H _SFR_IO8(0x27) ++ ++/* Timer/Counter1 Output Compare Register A */ ++#define OCR1 _SFR_IO16(0x2A) ++#define OCR1L _SFR_IO8(0x2A) ++#define OCR1H _SFR_IO8(0x2B) ++ ++/* Timer/Counter 1 */ ++#define TCNT1 _SFR_IO16(0x2C) ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++ ++/* Timer/Counter 1 Control and Status Register */ ++#define TCCR1B _SFR_IO8(0x2E) ++ ++/* Timer/Counter 1 Control Register */ ++#define TCCR1A _SFR_IO8(0x2F) ++ ++/* Timer/Counter 0 */ ++#define TCNT0 _SFR_IO8(0x32) ++ ++/* Timer/Counter 0 Control Register */ ++#define TCCR0 _SFR_IO8(0x33) ++ ++/* MCU general Status Register */ ++#define MCUSR _SFR_IO8(0x34) ++ ++/* MCU general Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++ ++/* Timer/Counter Interrupt Flag register */ ++#define TIFR _SFR_IO8(0x38) ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define TIMSK _SFR_IO8(0x39) ++ ++/* General Interrupt Flag Register */ ++#define GIFR _SFR_IO8(0x3A) ++ ++/* General Interrupt MaSK register */ ++#define GIMSK _SFR_IO8(0x3B) ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt 1 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++#define SIG_INTERRUPT1 _VECTOR(2) ++ ++/* Timer/Counter Capture Event */ ++#define TIMER1_CAPT_vect_num 3 ++#define TIMER1_CAPT_vect _VECTOR(3) ++#define SIG_INPUT_CAPTURE1 _VECTOR(3) ++ ++/* Timer/Counter1 Compare Match */ ++#define TIMER1_COMP_vect_num 4 ++#define TIMER1_COMP_vect _VECTOR(4) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(4) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 5 ++#define TIMER1_OVF_vect _VECTOR(5) ++#define SIG_OVERFLOW1 _VECTOR(5) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 6 ++#define TIMER0_OVF_vect _VECTOR(6) ++#define SIG_OVERFLOW0 _VECTOR(6) ++ ++/* Serial Transfer Complete */ ++#define SPI_STC_vect_num 7 ++#define SPI_STC_vect _VECTOR(7) ++#define SIG_SPI _VECTOR(7) ++ ++/* UART, Rx Complete */ ++#define UART_RX_vect_num 8 ++#define UART_RX_vect _VECTOR(8) ++#define SIG_UART_RECV _VECTOR(8) ++ ++/* UART Data Register Empty */ ++#define UART_UDRE_vect_num 9 ++#define UART_UDRE_vect _VECTOR(9) ++#define SIG_UART_DATA _VECTOR(9) ++ ++/* UART, Tx Complete */ ++#define UART_TX_vect_num 10 ++#define UART_TX_vect _VECTOR(10) ++#define SIG_UART_TRANS _VECTOR(10) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 11 ++#define ADC_vect _VECTOR(11) ++#define SIG_ADC _VECTOR(11) ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect_num 12 ++#define EE_RDY_vect _VECTOR(12) ++#define SIG_EEPROM_READY _VECTOR(12) ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect_num 13 ++#define ANA_COMP_vect _VECTOR(13) ++#define SIG_COMPARATOR _VECTOR(13) ++ ++#define _VECTORS_SIZE 28 ++ ++/* ++ The Register Bit names are represented by their bit number (0-7). ++*/ ++ ++/* MCU general Status Register */ ++#define WDRF 3 ++#define BORF 2 ++#define EXTRF 1 ++#define PORF 0 ++ ++/* General Interrupt MaSK register */ ++#define INT1 7 ++#define INT0 6 ++ ++/* General Interrupt Flag Register */ ++#define INTF1 7 ++#define INTF0 6 ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define TOIE1 7 ++#define OCIE1 6 ++#define TICIE1 3 ++#define TOIE0 1 ++ ++/* Timer/Counter Interrupt Flag register */ ++#define TOV1 7 ++#define OCF1 6 ++#define ICF1 3 ++#define TOV0 1 ++ ++/* MCU general Control Register */ ++#define SE 5 ++#define SM 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* Timer/Counter 0 Control Register */ ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* Timer/Counter 1 Control Register */ ++#define COM11 7 ++#define COM10 6 ++#define PWM11 1 ++#define PWM10 0 ++ ++/* Timer/Counter 1 Control and Status Register */ ++#define ICNC1 7 ++#define ICES1 6 ++#define CTC1 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* Watchdog Timer Control Register */ ++#define WDTOE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* SPI Control Register */ ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++/* SPI Status Register */ ++#define SPIF 7 ++#define WCOL 6 ++ ++/* UART Status Register */ ++#define RXC 7 ++#define TXC 6 ++#define UDRE 5 ++#define FE 4 ++#define DOR 3 ++#define MPCM 0 ++ ++/* UART Control Register */ ++#define RXCIE 7 ++#define TXCIE 6 ++#define UDRIE 5 ++#define RXEN 4 ++#define TXEN 3 ++#define CHR9 2 ++#define RXB8 1 ++#define TXB8 0 ++ ++/* Analog Comparator Control and Status Register */ ++#define ACD 7 ++#define AINBG 6 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++/* ADC MUX */ ++#define ACDBG 6 ++#define MUX2 2 ++#define MUX1 1 ++#define MUX0 0 ++ ++/* ADC Control and Status Register */ ++#define ADEN 7 ++#define ADSC 6 ++#define ADFR 5 ++#define ADIF 4 ++#define ADIE 3 ++#define ADPS2 2 ++#define ADPS1 1 ++#define ADPS0 0 ++ ++/* Data Register, Port B */ ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* Data Direction Register, Port B */ ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* Input Pins, Port B */ ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* Data Register, Port C */ ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++/* Data Direction Register, Port C */ ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++/* Input Pins, Port C */ ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++/* Data Register, Port D */ ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* Data Direction Register, Port D */ ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++/* Input Pins, Port D */ ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++/* EEPROM Control Register */ ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++/* Constants */ ++#define RAMSTART 0x60 ++#define RAMEND 0xDF /*Last On-Chip SRAM location*/ ++#define XRAMEND RAMEND ++#define E2END 0x7F ++#define FLASHEND 0x7FF ++ ++#endif /* _AVR_IO2333_H_ */ +diff --git a/include/avr/io2343.h b/include/avr/io2343.h +index 40b76bf..46fdd98 100644 +--- a/include/avr/io2343.h ++++ b/include/avr/io2343.h +@@ -1,211 +1,212 @@ +-/* Copyright (c) 2002, Marek Michalkiewicz +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: io2343.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* avr/io2343.h - definitions for AT90S2343 */ +- +-#ifndef _AVR_IO2343_H_ +-#define _AVR_IO2343_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "io2343.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* Input Pins, Port B */ +-#define PINB _SFR_IO8(0x16) +- +-/* Data Direction Register, Port B */ +-#define DDRB _SFR_IO8(0x17) +- +-/* Data Register, Port B */ +-#define PORTB _SFR_IO8(0x18) +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO8(0x1E) +-#define EEARL _SFR_IO8(0x1E) +- +-/* Watchdog Timer Control Register */ +-#define WDTCR _SFR_IO8(0x21) +- +-/* Timer/Counter 0 */ +-#define TCNT0 _SFR_IO8(0x32) +- +-/* Timer/Counter 0 Control Register */ +-#define TCCR0 _SFR_IO8(0x33) +- +-/* MCU Status Register */ +-#define MCUSR _SFR_IO8(0x34) +- +-/* MCU general Control Register */ +-#define MCUCR _SFR_IO8(0x35) +- +-/* Timer/Counter Interrupt Flag register */ +-#define TIFR _SFR_IO8(0x38) +- +-/* Timer/Counter Interrupt MaSK register */ +-#define TIMSK _SFR_IO8(0x39) +- +-/* General Interrupt Flag register */ +-#define GIFR _SFR_IO8(0x3A) +- +-/* General Interrupt MaSK register */ +-#define GIMSK _SFR_IO8(0x3B) +- +-/* 0x3D..0x3E SP */ +- +-/* 0x3F SREG */ +- +-/* Interrupt vectors */ +- +-/* External Interrupt 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF0_vect_num 2 +-#define TIMER0_OVF0_vect _VECTOR(2) +-#define SIG_OVERFLOW0 _VECTOR(2) +- +-#define _VECTORS_SIZE 6 +- +-/* +- The Register Bit names are represented by their bit number (0-7). +- */ +- +-/* General Interrupt MaSK register */ +-#define INT0 6 +-#define INTF0 6 +- +-/* General Interrupt Flag Register */ +-#define TOIE0 1 +-#define TOV0 1 +- +-/* MCU general Control Register */ +-#define SE 5 +-#define SM 4 +-#define ISC01 1 +-#define ISC00 0 +- +-/* MCU Status Register */ +-#define PORF 0 +-#define EXTRF 1 +- +-/* Timer/Counter 0 Control Register */ +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* Watchdog Timer Control Register */ +-#define WDTOE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* +- PB3 = CLOCK +- PB2 = SCK/T0 +- PB1 = MISO/INT0 +- PB0 = MOSI +- */ +- +-/* Data Register, Port B */ +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* Data Direction Register, Port B */ +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* Input Pins, Port B */ +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* EEPROM Control Register */ +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-/* Constants */ +-#define RAMEND 0xDF +-#define XRAMEND RAMEND +-#define E2END 0x7F +-#define E2PAGESIZE 0 +-#define FLASHEND 0x07FF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 1 +- +-/* Low Fuse Byte */ +-#define FUSE_RCEN (unsigned char)~_BV(0) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define LFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x91 +-#define SIGNATURE_2 0x03 +- +- +-#endif /* _AVR_IO2343_H_ */ ++/* Copyright (c) 2002, Marek Michalkiewicz ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: io2343.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* avr/io2343.h - definitions for AT90S2343 */ ++ ++#ifndef _AVR_IO2343_H_ ++#define _AVR_IO2343_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "io2343.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* Input Pins, Port B */ ++#define PINB _SFR_IO8(0x16) ++ ++/* Data Direction Register, Port B */ ++#define DDRB _SFR_IO8(0x17) ++ ++/* Data Register, Port B */ ++#define PORTB _SFR_IO8(0x18) ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO8(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++ ++/* Watchdog Timer Control Register */ ++#define WDTCR _SFR_IO8(0x21) ++ ++/* Timer/Counter 0 */ ++#define TCNT0 _SFR_IO8(0x32) ++ ++/* Timer/Counter 0 Control Register */ ++#define TCCR0 _SFR_IO8(0x33) ++ ++/* MCU Status Register */ ++#define MCUSR _SFR_IO8(0x34) ++ ++/* MCU general Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++ ++/* Timer/Counter Interrupt Flag register */ ++#define TIFR _SFR_IO8(0x38) ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define TIMSK _SFR_IO8(0x39) ++ ++/* General Interrupt Flag register */ ++#define GIFR _SFR_IO8(0x3A) ++ ++/* General Interrupt MaSK register */ ++#define GIMSK _SFR_IO8(0x3B) ++ ++/* 0x3D..0x3E SP */ ++ ++/* 0x3F SREG */ ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF0_vect_num 2 ++#define TIMER0_OVF0_vect _VECTOR(2) ++#define SIG_OVERFLOW0 _VECTOR(2) ++ ++#define _VECTORS_SIZE 6 ++ ++/* ++ The Register Bit names are represented by their bit number (0-7). ++ */ ++ ++/* General Interrupt MaSK register */ ++#define INT0 6 ++#define INTF0 6 ++ ++/* General Interrupt Flag Register */ ++#define TOIE0 1 ++#define TOV0 1 ++ ++/* MCU general Control Register */ ++#define SE 5 ++#define SM 4 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* MCU Status Register */ ++#define PORF 0 ++#define EXTRF 1 ++ ++/* Timer/Counter 0 Control Register */ ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* Watchdog Timer Control Register */ ++#define WDTOE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* ++ PB3 = CLOCK ++ PB2 = SCK/T0 ++ PB1 = MISO/INT0 ++ PB0 = MOSI ++ */ ++ ++/* Data Register, Port B */ ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* Data Direction Register, Port B */ ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* Input Pins, Port B */ ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* EEPROM Control Register */ ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++/* Constants */ ++#define RAMSTART 0x60 ++#define RAMEND 0xDF ++#define XRAMEND RAMEND ++#define E2END 0x7F ++#define E2PAGESIZE 0 ++#define FLASHEND 0x07FF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Low Fuse Byte */ ++#define FUSE_RCEN (unsigned char)~_BV(0) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define LFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x91 ++#define SIGNATURE_2 0x03 ++ ++ ++#endif /* _AVR_IO2343_H_ */ +diff --git a/include/avr/io43u32x.h b/include/avr/io43u32x.h +index b7df824..824a009 100644 +--- a/include/avr/io43u32x.h ++++ b/include/avr/io43u32x.h +@@ -1,436 +1,437 @@ +-/* Copyright (c) 2003,2005 Keith Gudger +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: io43u32x.h 1873 2009-02-11 17:53:39Z arcanum $ */ +- +-/* avr/io43u32x.h - definitions for AT43USB32x */ +- +-#ifndef _AVR_IO43U32X_H_ +-#define _AVR_IO43U32X_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "io43u32x.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* Analog Comparator Control and Status Register */ +-#define ACSR _SFR_IO8(0x08) +- +-/* UART Baud Rate Register */ +-#define UBRR _SFR_IO8(0x09) +- +-/* UART Control Register */ +-#define UCR _SFR_IO8(0x0A) +- +-/* UART Status Register */ +-#define USR _SFR_IO8(0x0B) +- +-/* UART I/O Data Register */ +-#define UDR _SFR_IO8(0x0C) +- +-/* Input Pins, Port E */ // new port for 43324/6 +-#define PINE _SFR_IO8(0x01) +- +-/* Data Direction Register, Port E */ +-#define DDRE _SFR_IO8(0x02) +- +-/* Data Register, Port E */ +-#define PORTE _SFR_IO8(0x03) +- +-/* SPI Control Register */ +-#define SPCR _SFR_IO8(0x0D) +- +-/* SPI Status Register */ +-#define SPSR _SFR_IO8(0x0E) +- +-/* SPI I/O Data Register */ +-#define SPDR _SFR_IO8(0x0F) +- +-/* Input Pins, Port D */ +-#define PIND _SFR_IO8(0x10) +- +-/* Data Direction Register, Port D */ +-#define DDRD _SFR_IO8(0x11) +- +-/* Data Register, Port D */ +-#define PORTD _SFR_IO8(0x12) +- +-/* Input Pins, Port C */ +-#define PINC _SFR_IO8(0x13) +- +-/* Data Direction Register, Port C */ +-#define DDRC _SFR_IO8(0x14) +- +-/* Data Register, Port C */ +-#define PORTC _SFR_IO8(0x15) +- +-/* Input Pins, Port B */ +-#define PINB _SFR_IO8(0x16) +- +-/* Data Direction Register, Port B */ +-#define DDRB _SFR_IO8(0x17) +- +-/* Data Register, Port B */ +-#define PORTB _SFR_IO8(0x18) +- +-/* Input Pins, Port A */ +-#define PINA _SFR_IO8(0x19) +- +-/* Data Direction Register, Port A */ +-#define DDRA _SFR_IO8(0x1A) +- +-/* Data Register, Port A */ +-#define PORTA _SFR_IO8(0x1B) +- +-/* 0x1C..0x1F reserved */ +- +-/* Watchdog Timer Control Register */ +-#define WDTCR _SFR_IO8(0x21) +- +-/* T/C 1 Input Capture Register */ +-#define ICR1 _SFR_IO16(0x24) +-#define ICR1L _SFR_IO8(0x24) +-#define ICR1H _SFR_IO8(0x25) +- +-/* Timer/Counter1 Output Compare Register B */ +-#define OCR1B _SFR_IO16(0x28) +-#define OCR1BL _SFR_IO8(0x28) +-#define OCR1BH _SFR_IO8(0x29) +- +-/* Timer/Counter1 Output Compare Register A */ +-#define OCR1A _SFR_IO16(0x2A) +-#define OCR1AL _SFR_IO8(0x2A) +-#define OCR1AH _SFR_IO8(0x2B) +- +-/* Timer/Counter 1 */ +-#define TCNT1 _SFR_IO16(0x2C) +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1H _SFR_IO8(0x2D) +- +-/* Timer/Counter 1 Control and Status Register */ +-#define TCCR1B _SFR_IO8(0x2E) +- +-/* Timer/Counter 1 Control Register */ +-#define TCCR1A _SFR_IO8(0x2F) +- +-/* Timer/Counter 0 */ +-#define TCNT0 _SFR_IO8(0x32) +- +-/* Timer/Counter 0 Control Register */ +-#define TCCR0 _SFR_IO8(0x33) +- +-/* MCU general Control Register */ +-#define MCUCR _SFR_IO8(0x35) +- +-/* Timer/Counter Interrupt Flag Register */ +-#define TIFR _SFR_IO8(0x38) +- +-/* Timer/Counter Interrupt MaSK register */ +-#define TIMSK _SFR_IO8(0x39) +- +-/* General Interrupt Control Register */ +-#define GIFR _SFR_IO8(0x3A) +- +-/* General Interrupt Mask register */ +-#define GIMSK _SFR_IO8(0x3B) +- +-/* Interrupt vectors */ +- +-#define SIG_INTERRUPT0 _VECTOR(1) +-#define SIG_INTERRUPT1 _VECTOR(2) +-#define SIG_TIMER1_CAPT1 _VECTOR(3) +-#define SIG_INPUT_CAPTURE1 _VECTOR(3) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(4) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(5) +-#define SIG_OVERFLOW1 _VECTOR(6) +-#define SIG_OVERFLOW0 _VECTOR(7) +-#define SIG_SPI _VECTOR(8) +-#define SIG_UART_RECV _VECTOR(9) +-#define SIG_UART_DATA _VECTOR(10) +-#define SIG_UART_TRANS _VECTOR(11) +-#define SIG_USB_INT _VECTOR(12) +- +-#define _VECTORS_SIZE 52 +- +-/* +- The Register Bit names are represented by their bit number (0-7). +-*/ +- +-/* Timer/Counter Interrupt MaSK register */ +-#define TICIE1 3 +-#define OCIE1A 6 +-#define OCIE1B 5 +-#define TOIE1 7 +-#define TOIE0 1 +- +-/* Timer/Counter Interrupt Flag Register */ +-#define ICF1 3 +-#define OCF1A 6 +-#define OCF1B 5 +-#define TOV1 7 +-#define TOV0 1 +- +-/* MCU general Control Register */ +-#define SE 5 +-#define SM 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-/* Timer/Counter 0 Control Register */ +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +- +-/* Timer/Counter 1 Control Register */ +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define PWM11 1 +-#define PWM10 0 +- +-/* Timer/Counter 1 Control and Status Register */ +-#define ICNC1 7 +-#define ICES1 6 +-#define CTC1 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* Watchdog Timer Control Register */ +-#define WDTOE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* Data Register, Port A */ +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-/* Data Direction Register, Port A */ +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-/* Input Pins, Port A */ +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-/* Data Register, Port B */ +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* Data Direction Register, Port B */ +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* Input Pins, Port B */ +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* Data Direction Register, Port C */ +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-/* Input Pins, Port C */ +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-/* Data Register, Port C */ +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-/* Data Register, Port D */ +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* Data Direction Register, Port D */ +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-/* Input Pins, Port D */ +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-/* Data Register, Port E */ +-#define PE7 7 +-#define PE6 6 +-#define PE5 5 +-#define PE4 4 +-#define PE3 3 +-#define PE2 2 +-#define PE1 1 +-#define PE0 0 +- +-/* Data Direction Register, Port E */ +-#define DDE7 7 +-#define DDE6 6 +-#define DDE5 5 +-#define DDE4 4 +-#define DDE3 3 +-#define DDE2 2 +-#define DDE1 1 +-#define DDE0 0 +- +-/* Input Pins, Port E */ +-#define PINE7 7 +-#define PINE6 6 +-#define PINE5 5 +-#define PINE4 4 +-#define PINE3 3 +-#define PINE2 2 +-#define PINE1 1 +-#define PINE0 0 +- +-/* SPI Status Register */ +-#define SPIF 7 +-#define WCOL 6 +- +-/* SPI Control Register */ +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +-/* UART Status Register */ +-#define RXC 7 +-#define TXC 6 +-#define UDRE 5 +-#define FE 4 +-#define DOR 3 +- +-/* UART Control Register */ +-#define RXCIE 7 +-#define TXCIE 6 +-#define UDRIE 5 +-#define RXEN 4 +-#define TXEN 3 +-#define CHR9 2 +-#define RXB8 1 +-#define TXB8 0 +- +-/* Constants */ +-#define RAMEND 0x025F /*Last On-Chip SRAM Location*/ +-#define XRAMEND RAMEND +-#define E2END 0x0000 +- +-/* FIXME: should be 0x1FFFF for max 128K (64K*16) external program memory, +- but no RAMPZ causes gcrt1.S build to fail, so assume 64K for now... */ +-#define FLASHEND 0x0FFFF +- +-#endif /* _AVR_43USB32X_H_ */ ++/* Copyright (c) 2003,2005 Keith Gudger ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: io43u32x.h 1873 2009-02-11 17:53:39Z arcanum $ */ ++ ++/* avr/io43u32x.h - definitions for AT43USB32x */ ++ ++#ifndef _AVR_IO43U32X_H_ ++#define _AVR_IO43U32X_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "io43u32x.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* Analog Comparator Control and Status Register */ ++#define ACSR _SFR_IO8(0x08) ++ ++/* UART Baud Rate Register */ ++#define UBRR _SFR_IO8(0x09) ++ ++/* UART Control Register */ ++#define UCR _SFR_IO8(0x0A) ++ ++/* UART Status Register */ ++#define USR _SFR_IO8(0x0B) ++ ++/* UART I/O Data Register */ ++#define UDR _SFR_IO8(0x0C) ++ ++/* Input Pins, Port E */ // new port for 43324/6 ++#define PINE _SFR_IO8(0x01) ++ ++/* Data Direction Register, Port E */ ++#define DDRE _SFR_IO8(0x02) ++ ++/* Data Register, Port E */ ++#define PORTE _SFR_IO8(0x03) ++ ++/* SPI Control Register */ ++#define SPCR _SFR_IO8(0x0D) ++ ++/* SPI Status Register */ ++#define SPSR _SFR_IO8(0x0E) ++ ++/* SPI I/O Data Register */ ++#define SPDR _SFR_IO8(0x0F) ++ ++/* Input Pins, Port D */ ++#define PIND _SFR_IO8(0x10) ++ ++/* Data Direction Register, Port D */ ++#define DDRD _SFR_IO8(0x11) ++ ++/* Data Register, Port D */ ++#define PORTD _SFR_IO8(0x12) ++ ++/* Input Pins, Port C */ ++#define PINC _SFR_IO8(0x13) ++ ++/* Data Direction Register, Port C */ ++#define DDRC _SFR_IO8(0x14) ++ ++/* Data Register, Port C */ ++#define PORTC _SFR_IO8(0x15) ++ ++/* Input Pins, Port B */ ++#define PINB _SFR_IO8(0x16) ++ ++/* Data Direction Register, Port B */ ++#define DDRB _SFR_IO8(0x17) ++ ++/* Data Register, Port B */ ++#define PORTB _SFR_IO8(0x18) ++ ++/* Input Pins, Port A */ ++#define PINA _SFR_IO8(0x19) ++ ++/* Data Direction Register, Port A */ ++#define DDRA _SFR_IO8(0x1A) ++ ++/* Data Register, Port A */ ++#define PORTA _SFR_IO8(0x1B) ++ ++/* 0x1C..0x1F reserved */ ++ ++/* Watchdog Timer Control Register */ ++#define WDTCR _SFR_IO8(0x21) ++ ++/* T/C 1 Input Capture Register */ ++#define ICR1 _SFR_IO16(0x24) ++#define ICR1L _SFR_IO8(0x24) ++#define ICR1H _SFR_IO8(0x25) ++ ++/* Timer/Counter1 Output Compare Register B */ ++#define OCR1B _SFR_IO16(0x28) ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BH _SFR_IO8(0x29) ++ ++/* Timer/Counter1 Output Compare Register A */ ++#define OCR1A _SFR_IO16(0x2A) ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++ ++/* Timer/Counter 1 */ ++#define TCNT1 _SFR_IO16(0x2C) ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++ ++/* Timer/Counter 1 Control and Status Register */ ++#define TCCR1B _SFR_IO8(0x2E) ++ ++/* Timer/Counter 1 Control Register */ ++#define TCCR1A _SFR_IO8(0x2F) ++ ++/* Timer/Counter 0 */ ++#define TCNT0 _SFR_IO8(0x32) ++ ++/* Timer/Counter 0 Control Register */ ++#define TCCR0 _SFR_IO8(0x33) ++ ++/* MCU general Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++ ++/* Timer/Counter Interrupt Flag Register */ ++#define TIFR _SFR_IO8(0x38) ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define TIMSK _SFR_IO8(0x39) ++ ++/* General Interrupt Control Register */ ++#define GIFR _SFR_IO8(0x3A) ++ ++/* General Interrupt Mask register */ ++#define GIMSK _SFR_IO8(0x3B) ++ ++/* Interrupt vectors */ ++ ++#define SIG_INTERRUPT0 _VECTOR(1) ++#define SIG_INTERRUPT1 _VECTOR(2) ++#define SIG_TIMER1_CAPT1 _VECTOR(3) ++#define SIG_INPUT_CAPTURE1 _VECTOR(3) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(4) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(5) ++#define SIG_OVERFLOW1 _VECTOR(6) ++#define SIG_OVERFLOW0 _VECTOR(7) ++#define SIG_SPI _VECTOR(8) ++#define SIG_UART_RECV _VECTOR(9) ++#define SIG_UART_DATA _VECTOR(10) ++#define SIG_UART_TRANS _VECTOR(11) ++#define SIG_USB_INT _VECTOR(12) ++ ++#define _VECTORS_SIZE 52 ++ ++/* ++ The Register Bit names are represented by their bit number (0-7). ++*/ ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define TICIE1 3 ++#define OCIE1A 6 ++#define OCIE1B 5 ++#define TOIE1 7 ++#define TOIE0 1 ++ ++/* Timer/Counter Interrupt Flag Register */ ++#define ICF1 3 ++#define OCF1A 6 ++#define OCF1B 5 ++#define TOV1 7 ++#define TOV0 1 ++ ++/* MCU general Control Register */ ++#define SE 5 ++#define SM 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* Timer/Counter 0 Control Register */ ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++ ++/* Timer/Counter 1 Control Register */ ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define PWM11 1 ++#define PWM10 0 ++ ++/* Timer/Counter 1 Control and Status Register */ ++#define ICNC1 7 ++#define ICES1 6 ++#define CTC1 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* Watchdog Timer Control Register */ ++#define WDTOE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* Data Register, Port A */ ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++/* Data Direction Register, Port A */ ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++/* Input Pins, Port A */ ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++/* Data Register, Port B */ ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* Data Direction Register, Port B */ ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* Input Pins, Port B */ ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* Data Direction Register, Port C */ ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++/* Input Pins, Port C */ ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++/* Data Register, Port C */ ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++/* Data Register, Port D */ ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* Data Direction Register, Port D */ ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++/* Input Pins, Port D */ ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++/* Data Register, Port E */ ++#define PE7 7 ++#define PE6 6 ++#define PE5 5 ++#define PE4 4 ++#define PE3 3 ++#define PE2 2 ++#define PE1 1 ++#define PE0 0 ++ ++/* Data Direction Register, Port E */ ++#define DDE7 7 ++#define DDE6 6 ++#define DDE5 5 ++#define DDE4 4 ++#define DDE3 3 ++#define DDE2 2 ++#define DDE1 1 ++#define DDE0 0 ++ ++/* Input Pins, Port E */ ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++/* SPI Status Register */ ++#define SPIF 7 ++#define WCOL 6 ++ ++/* SPI Control Register */ ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++/* UART Status Register */ ++#define RXC 7 ++#define TXC 6 ++#define UDRE 5 ++#define FE 4 ++#define DOR 3 ++ ++/* UART Control Register */ ++#define RXCIE 7 ++#define TXCIE 6 ++#define UDRIE 5 ++#define RXEN 4 ++#define TXEN 3 ++#define CHR9 2 ++#define RXB8 1 ++#define TXB8 0 ++ ++/* Constants */ ++#define RAMSTART 0x60 ++#define RAMEND 0x025F /*Last On-Chip SRAM Location*/ ++#define XRAMEND RAMEND ++#define E2END 0x0000 ++ ++/* FIXME: should be 0x1FFFF for max 128K (64K*16) external program memory, ++ but no RAMPZ causes gcrt1.S build to fail, so assume 64K for now... */ ++#define FLASHEND 0x0FFFF ++ ++#endif /* _AVR_43USB32X_H_ */ +diff --git a/include/avr/io43u35x.h b/include/avr/io43u35x.h +index e077f1f..bdeb7f6 100644 +--- a/include/avr/io43u35x.h ++++ b/include/avr/io43u35x.h +@@ -1,428 +1,429 @@ +-/* Copyright (c) 2003,2005 Keith Gudger +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: io43u35x.h 1873 2009-02-11 17:53:39Z arcanum $ */ +- +-/* avr/io43u35x.h - definitions for AT43USB35x */ +- +-#ifndef _AVR_IO43U35X_H_ +-#define _AVR_IO43U35X_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "io43u35x.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* ADC Data Register */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x02) +-#endif +-#define ADCW _SFR_IO16(0x02) +-#define ADCL _SFR_IO8(0x02) +-#define ADCH _SFR_IO8(0x03) +- +-/* ADC Control and status register */ +-#define ADCSR _SFR_IO8(0x07) +- +-/* ADC Multiplexer select */ +-#define ADMUX _SFR_IO8(0x08) +- +-/* Analog Comparator Control and Status Register */ +-#define ACSR _SFR_IO8(0x08) +- +-/* Input Pins, Port F */ +-#define PINF _SFR_IO8(0x04) +- +-/* Data Direction Register, Port F */ +-#define DDRF _SFR_IO8(0x05) +- +-/* Data Register, Port F */ +-#define PORTF _SFR_IO8(0x06) +- +-/* Input Pins, Port E */ +-#define PINE _SFR_IO8(0x01) +- +-/* Data Direction Register, Port E */ +-#define DDRE _SFR_IO8(0x02) +- +-/* Data Register, Port E */ +-#define PORTE _SFR_IO8(0x03) +- +-/* SPI Control Register */ +-#define SPCR _SFR_IO8(0x0D) +- +-/* SPI Status Register */ +-#define SPSR _SFR_IO8(0x0E) +- +-/* SPI I/O Data Register */ +-#define SPDR _SFR_IO8(0x0F) +- +-/* Input Pins, Port D */ +-#define PIND _SFR_IO8(0x10) +- +-/* Data Direction Register, Port D */ +-#define DDRD _SFR_IO8(0x11) +- +-/* Data Register, Port D */ +-#define PORTD _SFR_IO8(0x12) +- +-/* Input Pins, Port C */ +-#define PINC _SFR_IO8(0x13) +- +-/* Data Direction Register, Port C */ +-#define DDRC _SFR_IO8(0x14) +- +-/* Data Register, Port C */ +-#define PORTC _SFR_IO8(0x15) +- +-/* Input Pins, Port B */ +-#define PINB _SFR_IO8(0x16) +- +-/* Data Direction Register, Port B */ +-#define DDRB _SFR_IO8(0x17) +- +-/* Data Register, Port B */ +-#define PORTB _SFR_IO8(0x18) +- +-/* Input Pins, Port A */ +-#define PINA _SFR_IO8(0x19) +- +-/* Data Direction Register, Port A */ +-#define DDRA _SFR_IO8(0x1A) +- +-/* Data Register, Port A */ +-#define PORTA _SFR_IO8(0x1B) +- +-/* 0x1C..0x1F reserved */ +- +-/* Watchdog Timer Control Register */ +-#define WDTCR _SFR_IO8(0x21) +- +-/* T/C 1 Input Capture Register */ +-#define ICR1 _SFR_IO16(0x24) +-#define ICR1L _SFR_IO8(0x24) +-#define ICR1H _SFR_IO8(0x25) +- +-/* Timer/Counter1 Output Compare Register B */ +-#define OCR1B _SFR_IO16(0x28) +-#define OCR1BL _SFR_IO8(0x28) +-#define OCR1BH _SFR_IO8(0x29) +- +-/* Timer/Counter1 Output Compare Register A */ +-#define OCR1A _SFR_IO16(0x2A) +-#define OCR1AL _SFR_IO8(0x2A) +-#define OCR1AH _SFR_IO8(0x2B) +- +-/* Timer/Counter 1 */ +-#define TCNT1 _SFR_IO16(0x2C) +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1H _SFR_IO8(0x2D) +- +-/* Timer/Counter 1 Control and Status Register */ +-#define TCCR1B _SFR_IO8(0x2E) +- +-/* Timer/Counter 1 Control Register */ +-#define TCCR1A _SFR_IO8(0x2F) +- +-/* Timer/Counter 0 */ +-#define TCNT0 _SFR_IO8(0x32) +- +-/* Timer/Counter 0 Control Register */ +-#define TCCR0 _SFR_IO8(0x33) +- +-/* MCU general Control Register */ +-#define MCUCR _SFR_IO8(0x35) +- +-/* Timer/Counter Interrupt Flag Register */ +-#define TIFR _SFR_IO8(0x38) +- +-/* Timer/Counter Interrupt MaSK register */ +-#define TIMSK _SFR_IO8(0x39) +- +-/* General Interrupt Control Register */ +-#define GIFR _SFR_IO8(0x3A) +- +-/* General Interrupt Mask register */ +-#define GIMSK _SFR_IO8(0x3B) +- +-/* Interrupt vectors */ +- +-#define SIG_INTERRUPT0 _VECTOR(1) /* suspend/resume */ +-#define SIG_INTERRUPT1 _VECTOR(2) +-#define SIG_TIMER1_CAPT1 _VECTOR(3) +-#define SIG_INPUT_CAPTURE1 _VECTOR(3) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(4) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(5) +-#define SIG_OVERFLOW1 _VECTOR(6) +-#define SIG_OVERFLOW0 _VECTOR(7) +-#define SIG_SPI _VECTOR(8) +-/* 9, 10: reserved */ +-#define SIG_ADC _VECTOR(11) +-#define SIG_USB_INT _VECTOR(12) +- +-#define _VECTORS_SIZE 52 +- +-/* +- The Register Bit names are represented by their bit number (0-7). +-*/ +- +-/* Timer/Counter Interrupt MaSK register */ +-#define TICIE1 3 +-#define OCIE1A 6 +-#define OCIE1B 5 +-#define TOIE1 7 +-#define TOIE0 1 +- +-/* Timer/Counter Interrupt Flag Register */ +-#define ICF1 3 +-#define OCF1A 6 +-#define OCF1B 5 +-#define TOV1 7 +-#define TOV0 1 +- +-/* MCU general Control Register */ +-#define SE 5 +-#define SM 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-/* Timer/Counter 0 Control Register */ +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +- +-/* Timer/Counter 1 Control Register */ +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define PWM11 1 +-#define PWM10 0 +- +-/* Timer/Counter 1 Control and Status Register */ +-#define ICNC1 7 +-#define ICES1 6 +-#define CTC1 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* Watchdog Timer Control Register */ +-#define WDTOE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* Data Register, Port A */ +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-/* Data Direction Register, Port A */ +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-/* Input Pins, Port A */ +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-/* Data Register, Port B */ +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* Data Direction Register, Port B */ +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* Input Pins, Port B */ +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* Data Direction Register, Port C */ +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-/* Input Pins, Port C */ +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-/* Data Register, Port C */ +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-/* Data Register, Port D */ +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* Data Direction Register, Port D */ +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-/* Input Pins, Port D */ +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-/* Data Register, Port F */ +-#define PF3 3 +-#define PF2 2 +-#define PF1 1 +-#define PF0 0 +- +-/* Data Direction Register, Port F */ +-#define DDF3 3 +-#define DDF2 2 +-#define DDF1 1 +- +-/* Input Pins, Port F */ +-#define PINF3 3 +-#define PINF2 2 +-#define PINF1 1 +-#define PINF0 0 +- +-/* SPI Status Register */ +-#define SPIF 7 +-#define WCOL 6 +- +-/* SPI Control Register */ +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +-/* ADC Multiplexer select */ +-#define MUX2 2 +-#define MUX1 1 +-#define MUX0 0 +- +-/* ADC Control and Status Register */ +-#define ADEN 7 +-#define ADSC 6 +-#define ADFR 5 +-#define ADIF 4 +-#define ADIE 3 +-#define ADPS2 2 +-#define ADPS1 1 +-#define ADPS0 0 +- +-/* Constants */ +-#define RAMEND 0x045F /*Last On-Chip SRAM Location*/ +-#define XRAMEND RAMEND +-#define E2END 0x0000 +-#define FLASHEND 0x5FFF +- +-#endif /* _AVR_43USB355_H_ */ ++/* Copyright (c) 2003,2005 Keith Gudger ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: io43u35x.h 1873 2009-02-11 17:53:39Z arcanum $ */ ++ ++/* avr/io43u35x.h - definitions for AT43USB35x */ ++ ++#ifndef _AVR_IO43U35X_H_ ++#define _AVR_IO43U35X_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "io43u35x.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* ADC Data Register */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x02) ++#endif ++#define ADCW _SFR_IO16(0x02) ++#define ADCL _SFR_IO8(0x02) ++#define ADCH _SFR_IO8(0x03) ++ ++/* ADC Control and status register */ ++#define ADCSR _SFR_IO8(0x07) ++ ++/* ADC Multiplexer select */ ++#define ADMUX _SFR_IO8(0x08) ++ ++/* Analog Comparator Control and Status Register */ ++#define ACSR _SFR_IO8(0x08) ++ ++/* Input Pins, Port F */ ++#define PINF _SFR_IO8(0x04) ++ ++/* Data Direction Register, Port F */ ++#define DDRF _SFR_IO8(0x05) ++ ++/* Data Register, Port F */ ++#define PORTF _SFR_IO8(0x06) ++ ++/* Input Pins, Port E */ ++#define PINE _SFR_IO8(0x01) ++ ++/* Data Direction Register, Port E */ ++#define DDRE _SFR_IO8(0x02) ++ ++/* Data Register, Port E */ ++#define PORTE _SFR_IO8(0x03) ++ ++/* SPI Control Register */ ++#define SPCR _SFR_IO8(0x0D) ++ ++/* SPI Status Register */ ++#define SPSR _SFR_IO8(0x0E) ++ ++/* SPI I/O Data Register */ ++#define SPDR _SFR_IO8(0x0F) ++ ++/* Input Pins, Port D */ ++#define PIND _SFR_IO8(0x10) ++ ++/* Data Direction Register, Port D */ ++#define DDRD _SFR_IO8(0x11) ++ ++/* Data Register, Port D */ ++#define PORTD _SFR_IO8(0x12) ++ ++/* Input Pins, Port C */ ++#define PINC _SFR_IO8(0x13) ++ ++/* Data Direction Register, Port C */ ++#define DDRC _SFR_IO8(0x14) ++ ++/* Data Register, Port C */ ++#define PORTC _SFR_IO8(0x15) ++ ++/* Input Pins, Port B */ ++#define PINB _SFR_IO8(0x16) ++ ++/* Data Direction Register, Port B */ ++#define DDRB _SFR_IO8(0x17) ++ ++/* Data Register, Port B */ ++#define PORTB _SFR_IO8(0x18) ++ ++/* Input Pins, Port A */ ++#define PINA _SFR_IO8(0x19) ++ ++/* Data Direction Register, Port A */ ++#define DDRA _SFR_IO8(0x1A) ++ ++/* Data Register, Port A */ ++#define PORTA _SFR_IO8(0x1B) ++ ++/* 0x1C..0x1F reserved */ ++ ++/* Watchdog Timer Control Register */ ++#define WDTCR _SFR_IO8(0x21) ++ ++/* T/C 1 Input Capture Register */ ++#define ICR1 _SFR_IO16(0x24) ++#define ICR1L _SFR_IO8(0x24) ++#define ICR1H _SFR_IO8(0x25) ++ ++/* Timer/Counter1 Output Compare Register B */ ++#define OCR1B _SFR_IO16(0x28) ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BH _SFR_IO8(0x29) ++ ++/* Timer/Counter1 Output Compare Register A */ ++#define OCR1A _SFR_IO16(0x2A) ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++ ++/* Timer/Counter 1 */ ++#define TCNT1 _SFR_IO16(0x2C) ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++ ++/* Timer/Counter 1 Control and Status Register */ ++#define TCCR1B _SFR_IO8(0x2E) ++ ++/* Timer/Counter 1 Control Register */ ++#define TCCR1A _SFR_IO8(0x2F) ++ ++/* Timer/Counter 0 */ ++#define TCNT0 _SFR_IO8(0x32) ++ ++/* Timer/Counter 0 Control Register */ ++#define TCCR0 _SFR_IO8(0x33) ++ ++/* MCU general Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++ ++/* Timer/Counter Interrupt Flag Register */ ++#define TIFR _SFR_IO8(0x38) ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define TIMSK _SFR_IO8(0x39) ++ ++/* General Interrupt Control Register */ ++#define GIFR _SFR_IO8(0x3A) ++ ++/* General Interrupt Mask register */ ++#define GIMSK _SFR_IO8(0x3B) ++ ++/* Interrupt vectors */ ++ ++#define SIG_INTERRUPT0 _VECTOR(1) /* suspend/resume */ ++#define SIG_INTERRUPT1 _VECTOR(2) ++#define SIG_TIMER1_CAPT1 _VECTOR(3) ++#define SIG_INPUT_CAPTURE1 _VECTOR(3) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(4) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(5) ++#define SIG_OVERFLOW1 _VECTOR(6) ++#define SIG_OVERFLOW0 _VECTOR(7) ++#define SIG_SPI _VECTOR(8) ++/* 9, 10: reserved */ ++#define SIG_ADC _VECTOR(11) ++#define SIG_USB_INT _VECTOR(12) ++ ++#define _VECTORS_SIZE 52 ++ ++/* ++ The Register Bit names are represented by their bit number (0-7). ++*/ ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define TICIE1 3 ++#define OCIE1A 6 ++#define OCIE1B 5 ++#define TOIE1 7 ++#define TOIE0 1 ++ ++/* Timer/Counter Interrupt Flag Register */ ++#define ICF1 3 ++#define OCF1A 6 ++#define OCF1B 5 ++#define TOV1 7 ++#define TOV0 1 ++ ++/* MCU general Control Register */ ++#define SE 5 ++#define SM 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* Timer/Counter 0 Control Register */ ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++ ++/* Timer/Counter 1 Control Register */ ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define PWM11 1 ++#define PWM10 0 ++ ++/* Timer/Counter 1 Control and Status Register */ ++#define ICNC1 7 ++#define ICES1 6 ++#define CTC1 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* Watchdog Timer Control Register */ ++#define WDTOE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* Data Register, Port A */ ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++/* Data Direction Register, Port A */ ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++/* Input Pins, Port A */ ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++/* Data Register, Port B */ ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* Data Direction Register, Port B */ ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* Input Pins, Port B */ ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* Data Direction Register, Port C */ ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++/* Input Pins, Port C */ ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++/* Data Register, Port C */ ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++/* Data Register, Port D */ ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* Data Direction Register, Port D */ ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++/* Input Pins, Port D */ ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++/* Data Register, Port F */ ++#define PF3 3 ++#define PF2 2 ++#define PF1 1 ++#define PF0 0 ++ ++/* Data Direction Register, Port F */ ++#define DDF3 3 ++#define DDF2 2 ++#define DDF1 1 ++ ++/* Input Pins, Port F */ ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++/* SPI Status Register */ ++#define SPIF 7 ++#define WCOL 6 ++ ++/* SPI Control Register */ ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++/* ADC Multiplexer select */ ++#define MUX2 2 ++#define MUX1 1 ++#define MUX0 0 ++ ++/* ADC Control and Status Register */ ++#define ADEN 7 ++#define ADSC 6 ++#define ADFR 5 ++#define ADIF 4 ++#define ADIE 3 ++#define ADPS2 2 ++#define ADPS1 1 ++#define ADPS0 0 ++ ++/* Constants */ ++#define RAMSTART 0x60 ++#define RAMEND 0x045F /*Last On-Chip SRAM Location*/ ++#define XRAMEND RAMEND ++#define E2END 0x0000 ++#define FLASHEND 0x5FFF ++ ++#endif /* _AVR_43USB355_H_ */ +diff --git a/include/avr/io4414.h b/include/avr/io4414.h +index 51c1e35..41944ff 100644 +--- a/include/avr/io4414.h ++++ b/include/avr/io4414.h +@@ -1,497 +1,498 @@ +-/* Copyright (c) 2002, Marek Michalkiewicz +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: io4414.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* avr/io4414.h - definitions for AT90S4414 */ +- +-#ifndef _AVR_IO4414_H_ +-#define _AVR_IO4414_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "io4414.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* Analog Comparator Control and Status Register */ +-#define ACSR _SFR_IO8(0x08) +- +-/* UART Baud Rate Register */ +-#define UBRR _SFR_IO8(0x09) +- +-/* UART Control Register */ +-#define UCR _SFR_IO8(0x0A) +- +-/* UART Status Register */ +-#define USR _SFR_IO8(0x0B) +- +-/* UART I/O Data Register */ +-#define UDR _SFR_IO8(0x0C) +- +-/* SPI Control Register */ +-#define SPCR _SFR_IO8(0x0D) +- +-/* SPI Status Register */ +-#define SPSR _SFR_IO8(0x0E) +- +-/* SPI I/O Data Register */ +-#define SPDR _SFR_IO8(0x0F) +- +-/* Input Pins, Port D */ +-#define PIND _SFR_IO8(0x10) +- +-/* Data Direction Register, Port D */ +-#define DDRD _SFR_IO8(0x11) +- +-/* Data Register, Port D */ +-#define PORTD _SFR_IO8(0x12) +- +-/* Input Pins, Port C */ +-#define PINC _SFR_IO8(0x13) +- +-/* Data Direction Register, Port C */ +-#define DDRC _SFR_IO8(0x14) +- +-/* Data Register, Port C */ +-#define PORTC _SFR_IO8(0x15) +- +-/* Input Pins, Port B */ +-#define PINB _SFR_IO8(0x16) +- +-/* Data Direction Register, Port B */ +-#define DDRB _SFR_IO8(0x17) +- +-/* Data Register, Port B */ +-#define PORTB _SFR_IO8(0x18) +- +-/* Input Pins, Port A */ +-#define PINA _SFR_IO8(0x19) +- +-/* Data Direction Register, Port A */ +-#define DDRA _SFR_IO8(0x1A) +- +-/* Data Register, Port A */ +-#define PORTA _SFR_IO8(0x1B) +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO8(0x1E) +-#define EEARL _SFR_IO8(0x1E) +- +-/* Watchdog Timer Control Register */ +-#define WDTCR _SFR_IO8(0x21) +- +-/* T/C 1 Input Capture Register */ +-#define ICR1 _SFR_IO16(0x24) +-#define ICR1L _SFR_IO8(0x24) +-#define ICR1H _SFR_IO8(0x25) +- +-/* Timer/Counter1 Output Compare Register B */ +-#define OCR1B _SFR_IO16(0x28) +-#define OCR1BL _SFR_IO8(0x28) +-#define OCR1BH _SFR_IO8(0x29) +- +-/* Timer/Counter1 Output Compare Register A */ +-#define OCR1A _SFR_IO16(0x2A) +-#define OCR1AL _SFR_IO8(0x2A) +-#define OCR1AH _SFR_IO8(0x2B) +- +-/* Timer/Counter 1 */ +-#define TCNT1 _SFR_IO16(0x2C) +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1H _SFR_IO8(0x2D) +- +-/* Timer/Counter 1 Control and Status Register */ +-#define TCCR1B _SFR_IO8(0x2E) +- +-/* Timer/Counter 1 Control Register */ +-#define TCCR1A _SFR_IO8(0x2F) +- +-/* Timer/Counter 0 */ +-#define TCNT0 _SFR_IO8(0x32) +- +-/* Timer/Counter 0 Control Register */ +-#define TCCR0 _SFR_IO8(0x33) +- +-/* MCU general Control Register */ +-#define MCUCR _SFR_IO8(0x35) +- +-/* Timer/Counter Interrupt Flag register */ +-#define TIFR _SFR_IO8(0x38) +- +-/* Timer/Counter Interrupt MaSK register */ +-#define TIMSK _SFR_IO8(0x39) +- +-/* General Interrupt Flag Register */ +-#define GIFR _SFR_IO8(0x3A) +- +-/* General Interrupt MaSK register */ +-#define GIMSK _SFR_IO8(0x3B) +- +-/* 0x3C..0x3D SP */ +- +-/* 0x3F SREG */ +- +-/* Interrupt vectors */ +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt Request 1 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +-#define SIG_INTERRUPT1 _VECTOR(2) +- +-/* Timer/Counter Capture Event */ +-#define TIMER1_CAPT_vect_num 3 +-#define TIMER1_CAPT_vect _VECTOR(3) +-#define SIG_INPUT_CAPTURE1 _VECTOR(3) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 4 +-#define TIMER1_COMPA_vect _VECTOR(4) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(4) +- +-/* Timer/Counter1 Compare MatchB */ +-#define TIMER1_COMPB_vect_num 5 +-#define TIMER1_COMPB_vect _VECTOR(5) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(5) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 6 +-#define TIMER1_OVF_vect _VECTOR(6) +-#define SIG_OVERFLOW1 _VECTOR(6) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 7 +-#define TIMER0_OVF_vect _VECTOR(7) +-#define SIG_OVERFLOW0 _VECTOR(7) +- +-/* Serial Transfer Complete */ +-#define SPI_STC_vect_num 8 +-#define SPI_STC_vect _VECTOR(8) +-#define SIG_SPI _VECTOR(8) +- +-/* UART, Rx Complete */ +-#define UART_RX_vect_num 9 +-#define UART_RX_vect _VECTOR(9) +-#define SIG_UART_RECV _VECTOR(9) +- +-/* UART Data Register Empty */ +-#define UART_UDRE_vect_num 10 +-#define UART_UDRE_vect _VECTOR(10) +-#define SIG_UART_DATA _VECTOR(10) +- +-/* UART, Tx Complete */ +-#define UART_TX_vect_num 11 +-#define UART_TX_vect _VECTOR(11) +-#define SIG_UART_TRANS _VECTOR(11) +- +-/* Analog Comparator */ +-#define ANA_COMP_vect_num 12 +-#define ANA_COMP_vect _VECTOR(12) +-#define SIG_COMPARATOR _VECTOR(12) +- +-#define _VECTORS_SIZE 26 +- +-/* +- The Register Bit names are represented by their bit number (0-7). +-*/ +- +-/* General Interrupt MaSK register */ +-#define INT1 7 +-#define INT0 6 +- +-/* General Interrupt Flag Register */ +-#define INTF1 7 +-#define INTF0 6 +- +-/* Timer/Counter Interrupt MaSK register */ +-#define TOIE1 7 +-#define OCIE1A 6 +-#define OCIE1B 5 +-#define TICIE1 3 +-#define TOIE0 1 +- +-/* Timer/Counter Interrupt Flag register */ +-#define TOV1 7 +-#define OCF1A 6 +-#define OCF1B 5 +-#define ICF1 3 +-#define TOV0 1 +- +-/* MCU general Control Register */ +-#define SRE 7 +-#define SRW 6 +-#define SE 5 +-#define SM 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-/* Timer/Counter 0 Control Register */ +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* Timer/Counter 1 Control Register */ +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define PWM11 1 +-#define PWM10 0 +- +-/* Timer/Counter 1 Control and Status Register */ +-#define ICNC1 7 +-#define ICES1 6 +-#define CTC1 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* Watchdog Timer Control Register */ +-#define WDTOE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* Data Register, Port A */ +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-/* Data Direction Register, Port A */ +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-/* Input Pins, Port A */ +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-/* Data Register, Port B */ +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* Data Direction Register, Port B */ +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* Input Pins, Port B */ +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* Data Register, Port C */ +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-/* Data Direction Register, Port C */ +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-/* Input Pins, Port C */ +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-/* Data Register, Port D */ +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* Data Direction Register, Port D */ +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-/* Input Pins, Port D */ +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-/* SPI Status Register */ +-#define SPIF 7 +-#define WCOL 6 +- +-/* SPI Control Register */ +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +-/* UART Status Register */ +-#define RXC 7 +-#define TXC 6 +-#define UDRE 5 +-#define FE 4 +-#define DOR 3 +- +-/* UART Control Register */ +-#define RXCIE 7 +-#define TXCIE 6 +-#define UDRIE 5 +-#define RXEN 4 +-#define TXEN 3 +-#define CHR9 2 +-#define RXB8 1 +-#define TXB8 0 +- +-/* Analog Comparator Control and Status Register */ +-#define ACD 7 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +- +-/* EEPROM Control Register */ +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-/* Constants */ +-#define RAMEND 0x15F /* Last On-Chip SRAM Location */ +-#define XRAMEND 0xFFFF +-#define E2END 0xFF +-#define E2PAGESIZE 0 +-#define FLASHEND 0xFFF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 1 +- +-/* Low Fuse Byte */ +-#define FUSE_SPIEN (unsigned char)~_BV(1) /* Serial Program Downloading Enabled */ +-#define FUSE_FSTRT (unsigned char)~_BV(2) /* Short Start-up time selected */ +-#define LFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x92 +-#define SIGNATURE_2 0x01 +- +- +-#endif /* _AVR_IO4414_H_ */ ++/* Copyright (c) 2002, Marek Michalkiewicz ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: io4414.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* avr/io4414.h - definitions for AT90S4414 */ ++ ++#ifndef _AVR_IO4414_H_ ++#define _AVR_IO4414_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "io4414.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* Analog Comparator Control and Status Register */ ++#define ACSR _SFR_IO8(0x08) ++ ++/* UART Baud Rate Register */ ++#define UBRR _SFR_IO8(0x09) ++ ++/* UART Control Register */ ++#define UCR _SFR_IO8(0x0A) ++ ++/* UART Status Register */ ++#define USR _SFR_IO8(0x0B) ++ ++/* UART I/O Data Register */ ++#define UDR _SFR_IO8(0x0C) ++ ++/* SPI Control Register */ ++#define SPCR _SFR_IO8(0x0D) ++ ++/* SPI Status Register */ ++#define SPSR _SFR_IO8(0x0E) ++ ++/* SPI I/O Data Register */ ++#define SPDR _SFR_IO8(0x0F) ++ ++/* Input Pins, Port D */ ++#define PIND _SFR_IO8(0x10) ++ ++/* Data Direction Register, Port D */ ++#define DDRD _SFR_IO8(0x11) ++ ++/* Data Register, Port D */ ++#define PORTD _SFR_IO8(0x12) ++ ++/* Input Pins, Port C */ ++#define PINC _SFR_IO8(0x13) ++ ++/* Data Direction Register, Port C */ ++#define DDRC _SFR_IO8(0x14) ++ ++/* Data Register, Port C */ ++#define PORTC _SFR_IO8(0x15) ++ ++/* Input Pins, Port B */ ++#define PINB _SFR_IO8(0x16) ++ ++/* Data Direction Register, Port B */ ++#define DDRB _SFR_IO8(0x17) ++ ++/* Data Register, Port B */ ++#define PORTB _SFR_IO8(0x18) ++ ++/* Input Pins, Port A */ ++#define PINA _SFR_IO8(0x19) ++ ++/* Data Direction Register, Port A */ ++#define DDRA _SFR_IO8(0x1A) ++ ++/* Data Register, Port A */ ++#define PORTA _SFR_IO8(0x1B) ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO8(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++ ++/* Watchdog Timer Control Register */ ++#define WDTCR _SFR_IO8(0x21) ++ ++/* T/C 1 Input Capture Register */ ++#define ICR1 _SFR_IO16(0x24) ++#define ICR1L _SFR_IO8(0x24) ++#define ICR1H _SFR_IO8(0x25) ++ ++/* Timer/Counter1 Output Compare Register B */ ++#define OCR1B _SFR_IO16(0x28) ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BH _SFR_IO8(0x29) ++ ++/* Timer/Counter1 Output Compare Register A */ ++#define OCR1A _SFR_IO16(0x2A) ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++ ++/* Timer/Counter 1 */ ++#define TCNT1 _SFR_IO16(0x2C) ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++ ++/* Timer/Counter 1 Control and Status Register */ ++#define TCCR1B _SFR_IO8(0x2E) ++ ++/* Timer/Counter 1 Control Register */ ++#define TCCR1A _SFR_IO8(0x2F) ++ ++/* Timer/Counter 0 */ ++#define TCNT0 _SFR_IO8(0x32) ++ ++/* Timer/Counter 0 Control Register */ ++#define TCCR0 _SFR_IO8(0x33) ++ ++/* MCU general Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++ ++/* Timer/Counter Interrupt Flag register */ ++#define TIFR _SFR_IO8(0x38) ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define TIMSK _SFR_IO8(0x39) ++ ++/* General Interrupt Flag Register */ ++#define GIFR _SFR_IO8(0x3A) ++ ++/* General Interrupt MaSK register */ ++#define GIMSK _SFR_IO8(0x3B) ++ ++/* 0x3C..0x3D SP */ ++ ++/* 0x3F SREG */ ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++#define SIG_INTERRUPT1 _VECTOR(2) ++ ++/* Timer/Counter Capture Event */ ++#define TIMER1_CAPT_vect_num 3 ++#define TIMER1_CAPT_vect _VECTOR(3) ++#define SIG_INPUT_CAPTURE1 _VECTOR(3) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 4 ++#define TIMER1_COMPA_vect _VECTOR(4) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(4) ++ ++/* Timer/Counter1 Compare MatchB */ ++#define TIMER1_COMPB_vect_num 5 ++#define TIMER1_COMPB_vect _VECTOR(5) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(5) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 6 ++#define TIMER1_OVF_vect _VECTOR(6) ++#define SIG_OVERFLOW1 _VECTOR(6) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 7 ++#define TIMER0_OVF_vect _VECTOR(7) ++#define SIG_OVERFLOW0 _VECTOR(7) ++ ++/* Serial Transfer Complete */ ++#define SPI_STC_vect_num 8 ++#define SPI_STC_vect _VECTOR(8) ++#define SIG_SPI _VECTOR(8) ++ ++/* UART, Rx Complete */ ++#define UART_RX_vect_num 9 ++#define UART_RX_vect _VECTOR(9) ++#define SIG_UART_RECV _VECTOR(9) ++ ++/* UART Data Register Empty */ ++#define UART_UDRE_vect_num 10 ++#define UART_UDRE_vect _VECTOR(10) ++#define SIG_UART_DATA _VECTOR(10) ++ ++/* UART, Tx Complete */ ++#define UART_TX_vect_num 11 ++#define UART_TX_vect _VECTOR(11) ++#define SIG_UART_TRANS _VECTOR(11) ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect_num 12 ++#define ANA_COMP_vect _VECTOR(12) ++#define SIG_COMPARATOR _VECTOR(12) ++ ++#define _VECTORS_SIZE 26 ++ ++/* ++ The Register Bit names are represented by their bit number (0-7). ++*/ ++ ++/* General Interrupt MaSK register */ ++#define INT1 7 ++#define INT0 6 ++ ++/* General Interrupt Flag Register */ ++#define INTF1 7 ++#define INTF0 6 ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define TOIE1 7 ++#define OCIE1A 6 ++#define OCIE1B 5 ++#define TICIE1 3 ++#define TOIE0 1 ++ ++/* Timer/Counter Interrupt Flag register */ ++#define TOV1 7 ++#define OCF1A 6 ++#define OCF1B 5 ++#define ICF1 3 ++#define TOV0 1 ++ ++/* MCU general Control Register */ ++#define SRE 7 ++#define SRW 6 ++#define SE 5 ++#define SM 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* Timer/Counter 0 Control Register */ ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* Timer/Counter 1 Control Register */ ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define PWM11 1 ++#define PWM10 0 ++ ++/* Timer/Counter 1 Control and Status Register */ ++#define ICNC1 7 ++#define ICES1 6 ++#define CTC1 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* Watchdog Timer Control Register */ ++#define WDTOE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* Data Register, Port A */ ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++/* Data Direction Register, Port A */ ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++/* Input Pins, Port A */ ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++/* Data Register, Port B */ ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* Data Direction Register, Port B */ ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* Input Pins, Port B */ ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* Data Register, Port C */ ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++/* Data Direction Register, Port C */ ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++/* Input Pins, Port C */ ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++/* Data Register, Port D */ ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* Data Direction Register, Port D */ ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++/* Input Pins, Port D */ ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++/* SPI Status Register */ ++#define SPIF 7 ++#define WCOL 6 ++ ++/* SPI Control Register */ ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++/* UART Status Register */ ++#define RXC 7 ++#define TXC 6 ++#define UDRE 5 ++#define FE 4 ++#define DOR 3 ++ ++/* UART Control Register */ ++#define RXCIE 7 ++#define TXCIE 6 ++#define UDRIE 5 ++#define RXEN 4 ++#define TXEN 3 ++#define CHR9 2 ++#define RXB8 1 ++#define TXB8 0 ++ ++/* Analog Comparator Control and Status Register */ ++#define ACD 7 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++/* EEPROM Control Register */ ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++/* Constants */ ++#define RAMSTART 0x60 ++#define RAMEND 0x15F /* Last On-Chip SRAM Location */ ++#define XRAMEND 0xFFFF ++#define E2END 0xFF ++#define E2PAGESIZE 0 ++#define FLASHEND 0xFFF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Low Fuse Byte */ ++#define FUSE_SPIEN (unsigned char)~_BV(1) /* Serial Program Downloading Enabled */ ++#define FUSE_FSTRT (unsigned char)~_BV(2) /* Short Start-up time selected */ ++#define LFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x92 ++#define SIGNATURE_2 0x01 ++ ++ ++#endif /* _AVR_IO4414_H_ */ +diff --git a/include/avr/io4433.h b/include/avr/io4433.h +index 1a4cfd8..9acb97d 100644 +--- a/include/avr/io4433.h ++++ b/include/avr/io4433.h +@@ -1,486 +1,487 @@ +-/* Copyright (c) 2002, Marek Michalkiewicz +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: io4433.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* avr/io4433.h - definitions for AT90S4433 */ +- +-#ifndef _AVR_IO4433_H_ +-#define _AVR_IO4433_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "io4433.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* UART Baud Rate Register high */ +-#define UBRRH _SFR_IO8(0x03) +- +-/* ADC Data register */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x04) +-#endif +-#define ADCW _SFR_IO16(0x04) +-#define ADCL _SFR_IO8(0x04) +-#define ADCH _SFR_IO8(0x05) +- +-/* ADC Control and Status Register */ +-#define ADCSR _SFR_IO8(0x06) +- +-/* ADC MUX */ +-#define ADMUX _SFR_IO8(0x07) +- +-/* Analog Comparator Control and Status Register */ +-#define ACSR _SFR_IO8(0x08) +- +-/* UART Baud Rate Register */ +-#define UBRR _SFR_IO8(0x09) +- +-/* UART Control/Status Registers */ +-#define UCSRB _SFR_IO8(0x0A) +-#define UCSRA _SFR_IO8(0x0B) +- +-/* UART I/O Data Register */ +-#define UDR _SFR_IO8(0x0C) +- +-/* SPI Control Register */ +-#define SPCR _SFR_IO8(0x0D) +- +-/* SPI Status Register */ +-#define SPSR _SFR_IO8(0x0E) +- +-/* SPI I/O Data Register */ +-#define SPDR _SFR_IO8(0x0F) +- +-/* Input Pins, Port D */ +-#define PIND _SFR_IO8(0x10) +- +-/* Data Direction Register, Port D */ +-#define DDRD _SFR_IO8(0x11) +- +-/* Data Register, Port D */ +-#define PORTD _SFR_IO8(0x12) +- +-/* Input Pins, Port C */ +-#define PINC _SFR_IO8(0x13) +- +-/* Data Direction Register, Port C */ +-#define DDRC _SFR_IO8(0x14) +- +-/* Data Register, Port C */ +-#define PORTC _SFR_IO8(0x15) +- +-/* Input Pins, Port B */ +-#define PINB _SFR_IO8(0x16) +- +-/* Data Direction Register, Port B */ +-#define DDRB _SFR_IO8(0x17) +- +-/* Data Register, Port B */ +-#define PORTB _SFR_IO8(0x18) +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO8(0x1E) +-#define EEARL _SFR_IO8(0x1E) +- +-/* Watchdog Timer Control Register */ +-#define WDTCR _SFR_IO8(0x21) +- +-/* T/C 1 Input Capture Register */ +-#define ICR1 _SFR_IO16(0x26) +-#define ICR1L _SFR_IO8(0x26) +-#define ICR1H _SFR_IO8(0x27) +- +-/* Timer/Counter1 Output Compare Register A */ +-#define OCR1 _SFR_IO16(0x2A) +-#define OCR1L _SFR_IO8(0x2A) +-#define OCR1H _SFR_IO8(0x2B) +- +-/* Timer/Counter 1 */ +-#define TCNT1 _SFR_IO16(0x2C) +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1H _SFR_IO8(0x2D) +- +-/* Timer/Counter 1 Control and Status Register */ +-#define TCCR1B _SFR_IO8(0x2E) +- +-/* Timer/Counter 1 Control Register */ +-#define TCCR1A _SFR_IO8(0x2F) +- +-/* Timer/Counter 0 */ +-#define TCNT0 _SFR_IO8(0x32) +- +-/* Timer/Counter 0 Control Register */ +-#define TCCR0 _SFR_IO8(0x33) +- +-/* MCU general Status Register */ +-#define MCUSR _SFR_IO8(0x34) +- +-/* MCU general Control Register */ +-#define MCUCR _SFR_IO8(0x35) +- +-/* Timer/Counter Interrupt Flag register */ +-#define TIFR _SFR_IO8(0x38) +- +-/* Timer/Counter Interrupt MaSK register */ +-#define TIMSK _SFR_IO8(0x39) +- +-/* General Interrupt Flag Register */ +-#define GIFR _SFR_IO8(0x3A) +- +-/* General Interrupt MaSK register */ +-#define GIMSK _SFR_IO8(0x3B) +- +-/* 0x3D..0x3E SP */ +- +-/* 0x3F SREG */ +- +-/* Interrupt vectors */ +- +-/* External Interrupt 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt 1 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +-#define SIG_INTERRUPT1 _VECTOR(2) +- +-/* Timer/Counter Capture Event */ +-#define TIMER1_CAPT_vect_num 3 +-#define TIMER1_CAPT_vect _VECTOR(3) +-#define SIG_INPUT_CAPTURE1 _VECTOR(3) +- +-/* Timer/Counter1 Compare Match */ +-#define TIMER1_COMP_vect_num 4 +-#define TIMER1_COMP_vect _VECTOR(4) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(4) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 5 +-#define TIMER1_OVF_vect _VECTOR(5) +-#define SIG_OVERFLOW1 _VECTOR(5) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 6 +-#define TIMER0_OVF_vect _VECTOR(6) +-#define SIG_OVERFLOW0 _VECTOR(6) +- +-/* Serial Transfer Complete */ +-#define SPI_STC_vect_num 7 +-#define SPI_STC_vect _VECTOR(7) +-#define SIG_SPI _VECTOR(7) +- +-/* UART, Rx Complete */ +-#define UART_RX_vect_num 8 +-#define UART_RX_vect _VECTOR(8) +-#define SIG_UART_RECV _VECTOR(8) +- +-/* UART Data Register Empty */ +-#define UART_UDRE_vect_num 9 +-#define UART_UDRE_vect _VECTOR(9) +-#define SIG_UART_DATA _VECTOR(9) +- +-/* UART, Tx Complete */ +-#define UART_TX_vect_num 10 +-#define UART_TX_vect _VECTOR(10) +-#define SIG_UART_TRANS _VECTOR(10) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 11 +-#define ADC_vect _VECTOR(11) +-#define SIG_ADC _VECTOR(11) +- +-/* EEPROM Ready */ +-#define EE_RDY_vect_num 12 +-#define EE_RDY_vect _VECTOR(12) +-#define SIG_EEPROM_READY _VECTOR(12) +- +-/* Analog Comparator */ +-#define ANA_COMP_vect_num 13 +-#define ANA_COMP_vect _VECTOR(13) +-#define SIG_COMPARATOR _VECTOR(13) +- +-#define _VECTORS_SIZE 28 +- +-/* +- The Register Bit names are represented by their bit number (0-7). +-*/ +- +-/* MCU general Status Register */ +-#define WDRF 3 +-#define BORF 2 +-#define EXTRF 1 +-#define PORF 0 +- +-/* General Interrupt MaSK register */ +-#define INT1 7 +-#define INT0 6 +- +-/* General Interrupt Flag Register */ +-#define INTF1 7 +-#define INTF0 6 +- +-/* Timer/Counter Interrupt MaSK register */ +-#define TOIE1 7 +-#define OCIE1 6 +-#define TICIE1 3 +-#define TOIE0 1 +- +-/* Timer/Counter Interrupt Flag register */ +-#define TOV1 7 +-#define OCF1 6 +-#define ICF1 3 +-#define TOV0 1 +- +-/* MCU general Control Register */ +-#define SE 5 +-#define SM 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-/* Timer/Counter 0 Control Register */ +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* Timer/Counter 1 Control Register */ +-#define COM11 7 +-#define COM10 6 +-#define PWM11 1 +-#define PWM10 0 +- +-/* Timer/Counter 1 Control and Status Register */ +-#define ICNC1 7 +-#define ICES1 6 +-#define CTC1 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* Watchdog Timer Control Register */ +-#define WDTOE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* SPI Control Register */ +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +-/* SPI Status Register */ +-#define SPIF 7 +-#define WCOL 6 +- +-/* UART Status Register */ +-#define RXC 7 +-#define TXC 6 +-#define UDRE 5 +-#define FE 4 +-#define DOR 3 +-#define MPCM 0 +- +-/* UART Control Register */ +-#define RXCIE 7 +-#define TXCIE 6 +-#define UDRIE 5 +-#define RXEN 4 +-#define TXEN 3 +-#define CHR9 2 +-#define RXB8 1 +-#define TXB8 0 +- +-/* Analog Comparator Control and Status Register */ +-#define ACD 7 +-#define AINBG 6 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +- +-/* ADC MUX */ +-#define ACDBG 6 +-#define MUX2 2 +-#define MUX1 1 +-#define MUX0 0 +- +-/* ADC Control and Status Register */ +-#define ADEN 7 +-#define ADSC 6 +-#define ADFR 5 +-#define ADIF 4 +-#define ADIE 3 +-#define ADPS2 2 +-#define ADPS1 1 +-#define ADPS0 0 +- +-/* Data Register, Port B */ +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* Data Direction Register, Port B */ +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* Input Pins, Port B */ +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* Data Register, Port C */ +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-/* Data Direction Register, Port C */ +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-/* Input Pins, Port C */ +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-/* Data Register, Port D */ +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* Data Direction Register, Port D */ +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-/* Input Pins, Port D */ +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-/* EEPROM Control Register */ +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-/* Constants */ +-#define RAMEND 0xDF /*Last On-Chip SRAM location*/ +-#define XRAMEND RAMEND +-#define E2END 0xFF +-#define E2PAGESIZE 0 +-#define FLASHEND 0xFFF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 1 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_BODEN (unsigned char)~_BV(3) +-#define FUSE_BODLEVEL (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define LFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x92 +-#define SIGNATURE_2 0x03 +- +- +-#endif /* _AVR_IO4433_H_ */ ++/* Copyright (c) 2002, Marek Michalkiewicz ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: io4433.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* avr/io4433.h - definitions for AT90S4433 */ ++ ++#ifndef _AVR_IO4433_H_ ++#define _AVR_IO4433_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "io4433.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* UART Baud Rate Register high */ ++#define UBRRH _SFR_IO8(0x03) ++ ++/* ADC Data register */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCW _SFR_IO16(0x04) ++#define ADCL _SFR_IO8(0x04) ++#define ADCH _SFR_IO8(0x05) ++ ++/* ADC Control and Status Register */ ++#define ADCSR _SFR_IO8(0x06) ++ ++/* ADC MUX */ ++#define ADMUX _SFR_IO8(0x07) ++ ++/* Analog Comparator Control and Status Register */ ++#define ACSR _SFR_IO8(0x08) ++ ++/* UART Baud Rate Register */ ++#define UBRR _SFR_IO8(0x09) ++ ++/* UART Control/Status Registers */ ++#define UCSRB _SFR_IO8(0x0A) ++#define UCSRA _SFR_IO8(0x0B) ++ ++/* UART I/O Data Register */ ++#define UDR _SFR_IO8(0x0C) ++ ++/* SPI Control Register */ ++#define SPCR _SFR_IO8(0x0D) ++ ++/* SPI Status Register */ ++#define SPSR _SFR_IO8(0x0E) ++ ++/* SPI I/O Data Register */ ++#define SPDR _SFR_IO8(0x0F) ++ ++/* Input Pins, Port D */ ++#define PIND _SFR_IO8(0x10) ++ ++/* Data Direction Register, Port D */ ++#define DDRD _SFR_IO8(0x11) ++ ++/* Data Register, Port D */ ++#define PORTD _SFR_IO8(0x12) ++ ++/* Input Pins, Port C */ ++#define PINC _SFR_IO8(0x13) ++ ++/* Data Direction Register, Port C */ ++#define DDRC _SFR_IO8(0x14) ++ ++/* Data Register, Port C */ ++#define PORTC _SFR_IO8(0x15) ++ ++/* Input Pins, Port B */ ++#define PINB _SFR_IO8(0x16) ++ ++/* Data Direction Register, Port B */ ++#define DDRB _SFR_IO8(0x17) ++ ++/* Data Register, Port B */ ++#define PORTB _SFR_IO8(0x18) ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO8(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++ ++/* Watchdog Timer Control Register */ ++#define WDTCR _SFR_IO8(0x21) ++ ++/* T/C 1 Input Capture Register */ ++#define ICR1 _SFR_IO16(0x26) ++#define ICR1L _SFR_IO8(0x26) ++#define ICR1H _SFR_IO8(0x27) ++ ++/* Timer/Counter1 Output Compare Register A */ ++#define OCR1 _SFR_IO16(0x2A) ++#define OCR1L _SFR_IO8(0x2A) ++#define OCR1H _SFR_IO8(0x2B) ++ ++/* Timer/Counter 1 */ ++#define TCNT1 _SFR_IO16(0x2C) ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++ ++/* Timer/Counter 1 Control and Status Register */ ++#define TCCR1B _SFR_IO8(0x2E) ++ ++/* Timer/Counter 1 Control Register */ ++#define TCCR1A _SFR_IO8(0x2F) ++ ++/* Timer/Counter 0 */ ++#define TCNT0 _SFR_IO8(0x32) ++ ++/* Timer/Counter 0 Control Register */ ++#define TCCR0 _SFR_IO8(0x33) ++ ++/* MCU general Status Register */ ++#define MCUSR _SFR_IO8(0x34) ++ ++/* MCU general Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++ ++/* Timer/Counter Interrupt Flag register */ ++#define TIFR _SFR_IO8(0x38) ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define TIMSK _SFR_IO8(0x39) ++ ++/* General Interrupt Flag Register */ ++#define GIFR _SFR_IO8(0x3A) ++ ++/* General Interrupt MaSK register */ ++#define GIMSK _SFR_IO8(0x3B) ++ ++/* 0x3D..0x3E SP */ ++ ++/* 0x3F SREG */ ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt 1 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++#define SIG_INTERRUPT1 _VECTOR(2) ++ ++/* Timer/Counter Capture Event */ ++#define TIMER1_CAPT_vect_num 3 ++#define TIMER1_CAPT_vect _VECTOR(3) ++#define SIG_INPUT_CAPTURE1 _VECTOR(3) ++ ++/* Timer/Counter1 Compare Match */ ++#define TIMER1_COMP_vect_num 4 ++#define TIMER1_COMP_vect _VECTOR(4) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(4) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 5 ++#define TIMER1_OVF_vect _VECTOR(5) ++#define SIG_OVERFLOW1 _VECTOR(5) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 6 ++#define TIMER0_OVF_vect _VECTOR(6) ++#define SIG_OVERFLOW0 _VECTOR(6) ++ ++/* Serial Transfer Complete */ ++#define SPI_STC_vect_num 7 ++#define SPI_STC_vect _VECTOR(7) ++#define SIG_SPI _VECTOR(7) ++ ++/* UART, Rx Complete */ ++#define UART_RX_vect_num 8 ++#define UART_RX_vect _VECTOR(8) ++#define SIG_UART_RECV _VECTOR(8) ++ ++/* UART Data Register Empty */ ++#define UART_UDRE_vect_num 9 ++#define UART_UDRE_vect _VECTOR(9) ++#define SIG_UART_DATA _VECTOR(9) ++ ++/* UART, Tx Complete */ ++#define UART_TX_vect_num 10 ++#define UART_TX_vect _VECTOR(10) ++#define SIG_UART_TRANS _VECTOR(10) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 11 ++#define ADC_vect _VECTOR(11) ++#define SIG_ADC _VECTOR(11) ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect_num 12 ++#define EE_RDY_vect _VECTOR(12) ++#define SIG_EEPROM_READY _VECTOR(12) ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect_num 13 ++#define ANA_COMP_vect _VECTOR(13) ++#define SIG_COMPARATOR _VECTOR(13) ++ ++#define _VECTORS_SIZE 28 ++ ++/* ++ The Register Bit names are represented by their bit number (0-7). ++*/ ++ ++/* MCU general Status Register */ ++#define WDRF 3 ++#define BORF 2 ++#define EXTRF 1 ++#define PORF 0 ++ ++/* General Interrupt MaSK register */ ++#define INT1 7 ++#define INT0 6 ++ ++/* General Interrupt Flag Register */ ++#define INTF1 7 ++#define INTF0 6 ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define TOIE1 7 ++#define OCIE1 6 ++#define TICIE1 3 ++#define TOIE0 1 ++ ++/* Timer/Counter Interrupt Flag register */ ++#define TOV1 7 ++#define OCF1 6 ++#define ICF1 3 ++#define TOV0 1 ++ ++/* MCU general Control Register */ ++#define SE 5 ++#define SM 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* Timer/Counter 0 Control Register */ ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* Timer/Counter 1 Control Register */ ++#define COM11 7 ++#define COM10 6 ++#define PWM11 1 ++#define PWM10 0 ++ ++/* Timer/Counter 1 Control and Status Register */ ++#define ICNC1 7 ++#define ICES1 6 ++#define CTC1 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* Watchdog Timer Control Register */ ++#define WDTOE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* SPI Control Register */ ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++/* SPI Status Register */ ++#define SPIF 7 ++#define WCOL 6 ++ ++/* UART Status Register */ ++#define RXC 7 ++#define TXC 6 ++#define UDRE 5 ++#define FE 4 ++#define DOR 3 ++#define MPCM 0 ++ ++/* UART Control Register */ ++#define RXCIE 7 ++#define TXCIE 6 ++#define UDRIE 5 ++#define RXEN 4 ++#define TXEN 3 ++#define CHR9 2 ++#define RXB8 1 ++#define TXB8 0 ++ ++/* Analog Comparator Control and Status Register */ ++#define ACD 7 ++#define AINBG 6 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++/* ADC MUX */ ++#define ACDBG 6 ++#define MUX2 2 ++#define MUX1 1 ++#define MUX0 0 ++ ++/* ADC Control and Status Register */ ++#define ADEN 7 ++#define ADSC 6 ++#define ADFR 5 ++#define ADIF 4 ++#define ADIE 3 ++#define ADPS2 2 ++#define ADPS1 1 ++#define ADPS0 0 ++ ++/* Data Register, Port B */ ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* Data Direction Register, Port B */ ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* Input Pins, Port B */ ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* Data Register, Port C */ ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++/* Data Direction Register, Port C */ ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++/* Input Pins, Port C */ ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++/* Data Register, Port D */ ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* Data Direction Register, Port D */ ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++/* Input Pins, Port D */ ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++/* EEPROM Control Register */ ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++/* Constants */ ++#define RAMSTART 0x60 ++#define RAMEND 0xDF /*Last On-Chip SRAM location*/ ++#define XRAMEND RAMEND ++#define E2END 0xFF ++#define E2PAGESIZE 0 ++#define FLASHEND 0xFFF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_BODEN (unsigned char)~_BV(3) ++#define FUSE_BODLEVEL (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define LFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x92 ++#define SIGNATURE_2 0x03 ++ ++ ++#endif /* _AVR_IO4433_H_ */ +diff --git a/include/avr/io4434.h b/include/avr/io4434.h +index f113696..f37793b 100644 +--- a/include/avr/io4434.h ++++ b/include/avr/io4434.h +@@ -1,583 +1,584 @@ +-/* Copyright (c) 2002, Marek Michalkiewicz +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: io4434.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* avr/io4434.h - definitions for AT90S4434 */ +- +-#ifndef _AVR_IO4434_H_ +-#define _AVR_IO4434_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "io4434.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* ADC Data register */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x04) +-#endif +-#define ADCW _SFR_IO16(0x04) +-#define ADCL _SFR_IO8(0x04) +-#define ADCH _SFR_IO8(0x05) +- +-/* ADC Control and Status Register */ +-#define ADCSR _SFR_IO8(0x06) +- +-/* ADC MUX */ +-#define ADMUX _SFR_IO8(0x07) +- +-/* Analog Comparator Control and Status Register */ +-#define ACSR _SFR_IO8(0x08) +- +-/* UART Baud Rate Register */ +-#define UBRR _SFR_IO8(0x09) +- +-/* UART Control Register */ +-#define UCR _SFR_IO8(0x0A) +- +-/* UART Status Register */ +-#define USR _SFR_IO8(0x0B) +- +-/* UART I/O Data Register */ +-#define UDR _SFR_IO8(0x0C) +- +-/* SPI Control Register */ +-#define SPCR _SFR_IO8(0x0D) +- +-/* SPI Status Register */ +-#define SPSR _SFR_IO8(0x0E) +- +-/* SPI I/O Data Register */ +-#define SPDR _SFR_IO8(0x0F) +- +-/* Input Pins, Port D */ +-#define PIND _SFR_IO8(0x10) +- +-/* Data Direction Register, Port D */ +-#define DDRD _SFR_IO8(0x11) +- +-/* Data Register, Port D */ +-#define PORTD _SFR_IO8(0x12) +- +-/* Input Pins, Port C */ +-#define PINC _SFR_IO8(0x13) +- +-/* Data Direction Register, Port C */ +-#define DDRC _SFR_IO8(0x14) +- +-/* Data Register, Port C */ +-#define PORTC _SFR_IO8(0x15) +- +-/* Input Pins, Port B */ +-#define PINB _SFR_IO8(0x16) +- +-/* Data Direction Register, Port B */ +-#define DDRB _SFR_IO8(0x17) +- +-/* Data Register, Port B */ +-#define PORTB _SFR_IO8(0x18) +- +-/* Input Pins, Port A */ +-#define PINA _SFR_IO8(0x19) +- +-/* Data Direction Register, Port A */ +-#define DDRA _SFR_IO8(0x1A) +- +-/* Data Register, Port A */ +-#define PORTA _SFR_IO8(0x1B) +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO8(0x1E) +-#define EEARL _SFR_IO8(0x1E) +- +-/* Watchdog Timer Control Register */ +-#define WDTCR _SFR_IO8(0x21) +- +-/* Asynchronous mode Status Register */ +-#define ASSR _SFR_IO8(0x22) +- +-/* Timer/Counter2 Output Compare Register */ +-#define OCR2 _SFR_IO8(0x23) +- +-/* Timer/Counter 2 */ +-#define TCNT2 _SFR_IO8(0x24) +- +-/* Timer/Counter 2 Control Register */ +-#define TCCR2 _SFR_IO8(0x25) +- +-/* T/C 1 Input Capture Register */ +-#define ICR1 _SFR_IO16(0x26) +-#define ICR1L _SFR_IO8(0x26) +-#define ICR1H _SFR_IO8(0x27) +- +-/* Timer/Counter1 Output Compare Register B */ +-#define OCR1B _SFR_IO16(0x28) +-#define OCR1BL _SFR_IO8(0x28) +-#define OCR1BH _SFR_IO8(0x29) +- +-/* Timer/Counter1 Output Compare Register A */ +-#define OCR1A _SFR_IO16(0x2A) +-#define OCR1AL _SFR_IO8(0x2A) +-#define OCR1AH _SFR_IO8(0x2B) +- +-/* Timer/Counter 1 */ +-#define TCNT1 _SFR_IO16(0x2C) +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1H _SFR_IO8(0x2D) +- +-/* Timer/Counter 1 Control and Status Register */ +-#define TCCR1B _SFR_IO8(0x2E) +- +-/* Timer/Counter 1 Control Register */ +-#define TCCR1A _SFR_IO8(0x2F) +- +-/* Timer/Counter 0 */ +-#define TCNT0 _SFR_IO8(0x32) +- +-/* Timer/Counter 0 Control Register */ +-#define TCCR0 _SFR_IO8(0x33) +- +-/* MCU general Status Register */ +-#define MCUSR _SFR_IO8(0x34) +- +-/* MCU general Control Register */ +-#define MCUCR _SFR_IO8(0x35) +- +-/* Timer/Counter Interrupt Flag register */ +-#define TIFR _SFR_IO8(0x38) +- +-/* Timer/Counter Interrupt MaSK register */ +-#define TIMSK _SFR_IO8(0x39) +- +-/* General Interrupt Flag Register */ +-#define GIFR _SFR_IO8(0x3A) +- +-/* General Interrupt MaSK register */ +-#define GIMSK _SFR_IO8(0x3B) +- +-/* 0x3D..0x3E SP */ +- +-/* 0x3F SREG */ +- +-/* Interrupt vectors */ +- +-/* External Interrupt 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt 1 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +-#define SIG_INTERRUPT1 _VECTOR(2) +- +-/* Timer/Counter2 Compare Match */ +-#define TIMER2_COMP_vect_num 3 +-#define TIMER2_COMP_vect _VECTOR(3) +-#define SIG_OUTPUT_COMPARE2 _VECTOR(3) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 4 +-#define TIMER2_OVF_vect _VECTOR(4) +-#define SIG_OVERFLOW2 _VECTOR(4) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 5 +-#define TIMER1_CAPT_vect _VECTOR(5) +-#define SIG_INPUT_CAPTURE1 _VECTOR(5) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 6 +-#define TIMER1_COMPA_vect _VECTOR(6) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(6) +- +-/* Timer/Counter1 Compare Match B */ +-#define TIMER1_COMPB_vect_num 7 +-#define TIMER1_COMPB_vect _VECTOR(7) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(7) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 8 +-#define TIMER1_OVF_vect _VECTOR(8) +-#define SIG_OVERFLOW1 _VECTOR(8) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 9 +-#define TIMER0_OVF_vect _VECTOR(9) +-#define SIG_OVERFLOW0 _VECTOR(9) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 10 +-#define SPI_STC_vect _VECTOR(10) +-#define SIG_SPI _VECTOR(10) +- +-/* UART, RX Complete */ +-#define UART_RX_vect_num 11 +-#define UART_RX_vect _VECTOR(11) +-#define SIG_UART_RECV _VECTOR(11) +- +-/* UART Data Register Empty */ +-#define UART_UDRE_vect_num 12 +-#define UART_UDRE_vect _VECTOR(12) +-#define SIG_UART_DATA _VECTOR(12) +- +-/* UART, TX Complete */ +-#define UART_TX_vect_num 13 +-#define UART_TX_vect _VECTOR(13) +-#define SIG_UART_TRANS _VECTOR(13) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 14 +-#define ADC_vect _VECTOR(14) +-#define SIG_ADC _VECTOR(14) +- +-/* EEPROM Ready */ +-#define EE_RDY_vect_num 15 +-#define EE_RDY_vect _VECTOR(15) +-#define SIG_EEPROM_READY _VECTOR(15) +- +-/* Analog Comparator */ +-#define ANA_COMP_vect_num 16 +-#define ANA_COMP_vect _VECTOR(16) +-#define SIG_COMPARATOR _VECTOR(16) +- +-#define _VECTORS_SIZE 34 +- +-/* +- The Register Bit names are represented by their bit number (0-7). +-*/ +- +-/* MCU general Status Register */ +-#define EXTRF 1 +-#define PORF 0 +- +-/* General Interrupt MaSK register */ +-#define INT1 7 +-#define INT0 6 +- +-/* General Interrupt Flag Register */ +-#define INTF1 7 +-#define INTF0 6 +- +-/* Timer/Counter Interrupt MaSK register */ +-#define OCIE2 7 +-#define TOIE2 6 +-#define TICIE1 5 +-#define OCIE1A 4 +-#define OCIE1B 3 +-#define TOIE1 2 +-#define TOIE0 0 +- +-/* Timer/Counter Interrupt Flag register */ +-#define OCF2 7 +-#define TOV2 6 +-#define ICF1 5 +-#define OCF1A 4 +-#define OCF1B 3 +-#define TOV1 2 +-#define TOV0 0 +- +-/* MCU general Control Register */ +-#define SE 6 +-#define SM1 5 +-#define SM0 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-/* Timer/Counter 0 Control Register */ +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* Timer/Counter 1 Control Register */ +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define PWM11 1 +-#define PWM10 0 +- +-/* Timer/Counter 1 Control and Status Register */ +-#define ICNC1 7 +-#define ICES1 6 +-#define CTC1 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* Timer/Counter 2 Control Register */ +-#define PWM2 6 +-#define COM21 5 +-#define COM20 4 +-#define CTC2 3 +-#define CS22 2 +-#define CS21 1 +-#define CS20 0 +- +-/* Asynchronous mode Status Register */ +-#define AS2 3 +-#define TCN2UB 2 +-#define OCR2UB 1 +-#define TCR2UB 0 +- +-/* Watchdog Timer Control Register */ +-#define WDTOE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* Data Register, Port A */ +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-/* Data Direction Register, Port A */ +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-/* Input Pins, Port A */ +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-/* Data Register, Port B */ +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* Data Direction Register, Port B */ +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* Input Pins, Port B */ +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* Data Register, Port C */ +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-/* Data Direction Register, Port C */ +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-/* Input Pins, Port C */ +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-/* Data Register, Port D */ +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* Data Direction Register, Port D */ +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-/* Input Pins, Port D */ +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-/* SPI Control Register */ +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +-/* SPI Status Register */ +-#define SPIF 7 +-#define WCOL 6 +- +-/* UART Status Register */ +-#define RXC 7 +-#define TXC 6 +-#define UDRE 5 +-#define FE 4 +-#define DOR 3 +- +-/* UART Control Register */ +-#define RXCIE 7 +-#define TXCIE 6 +-#define UDRIE 5 +-#define RXEN 4 +-#define TXEN 3 +-#define CHR9 2 +-#define RXB8 1 +-#define TXB8 0 +- +-/* Analog Comparator Control and Status Register */ +-#define ACD 7 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +- +-/* ADC MUX */ +-#define MUX2 2 +-#define MUX1 1 +-#define MUX0 0 +- +-/* ADC Control and Status Register */ +-#define ADEN 7 +-#define ADSC 6 +-#define ADFR 5 +-#define ADIF 4 +-#define ADIE 3 +-#define ADPS2 2 +-#define ADPS1 1 +-#define ADPS0 0 +- +-/* EEPROM Control Register */ +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-/* Constants */ +-#define RAMEND 0x15F /*Last On-Chip SRAM location*/ +-#define XRAMEND RAMEND +-#define E2END 0xFF +-#define E2PAGESIZE 0 +-#define FLASHEND 0xFFF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 1 +- +-/* Low Fuse Byte */ +-#define FUSE_SPIEN ~_BV(1) /* Serial Program Downloading Enabled */ +-#define FUSE_FSTRT ~_BV(2) /* Short Start-up time selected */ +-#define LFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x93 +-#define SIGNATURE_2 0x03 +- +- +-#endif /* _AVR_IO4434_H_ */ ++/* Copyright (c) 2002, Marek Michalkiewicz ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: io4434.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* avr/io4434.h - definitions for AT90S4434 */ ++ ++#ifndef _AVR_IO4434_H_ ++#define _AVR_IO4434_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "io4434.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* ADC Data register */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCW _SFR_IO16(0x04) ++#define ADCL _SFR_IO8(0x04) ++#define ADCH _SFR_IO8(0x05) ++ ++/* ADC Control and Status Register */ ++#define ADCSR _SFR_IO8(0x06) ++ ++/* ADC MUX */ ++#define ADMUX _SFR_IO8(0x07) ++ ++/* Analog Comparator Control and Status Register */ ++#define ACSR _SFR_IO8(0x08) ++ ++/* UART Baud Rate Register */ ++#define UBRR _SFR_IO8(0x09) ++ ++/* UART Control Register */ ++#define UCR _SFR_IO8(0x0A) ++ ++/* UART Status Register */ ++#define USR _SFR_IO8(0x0B) ++ ++/* UART I/O Data Register */ ++#define UDR _SFR_IO8(0x0C) ++ ++/* SPI Control Register */ ++#define SPCR _SFR_IO8(0x0D) ++ ++/* SPI Status Register */ ++#define SPSR _SFR_IO8(0x0E) ++ ++/* SPI I/O Data Register */ ++#define SPDR _SFR_IO8(0x0F) ++ ++/* Input Pins, Port D */ ++#define PIND _SFR_IO8(0x10) ++ ++/* Data Direction Register, Port D */ ++#define DDRD _SFR_IO8(0x11) ++ ++/* Data Register, Port D */ ++#define PORTD _SFR_IO8(0x12) ++ ++/* Input Pins, Port C */ ++#define PINC _SFR_IO8(0x13) ++ ++/* Data Direction Register, Port C */ ++#define DDRC _SFR_IO8(0x14) ++ ++/* Data Register, Port C */ ++#define PORTC _SFR_IO8(0x15) ++ ++/* Input Pins, Port B */ ++#define PINB _SFR_IO8(0x16) ++ ++/* Data Direction Register, Port B */ ++#define DDRB _SFR_IO8(0x17) ++ ++/* Data Register, Port B */ ++#define PORTB _SFR_IO8(0x18) ++ ++/* Input Pins, Port A */ ++#define PINA _SFR_IO8(0x19) ++ ++/* Data Direction Register, Port A */ ++#define DDRA _SFR_IO8(0x1A) ++ ++/* Data Register, Port A */ ++#define PORTA _SFR_IO8(0x1B) ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO8(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++ ++/* Watchdog Timer Control Register */ ++#define WDTCR _SFR_IO8(0x21) ++ ++/* Asynchronous mode Status Register */ ++#define ASSR _SFR_IO8(0x22) ++ ++/* Timer/Counter2 Output Compare Register */ ++#define OCR2 _SFR_IO8(0x23) ++ ++/* Timer/Counter 2 */ ++#define TCNT2 _SFR_IO8(0x24) ++ ++/* Timer/Counter 2 Control Register */ ++#define TCCR2 _SFR_IO8(0x25) ++ ++/* T/C 1 Input Capture Register */ ++#define ICR1 _SFR_IO16(0x26) ++#define ICR1L _SFR_IO8(0x26) ++#define ICR1H _SFR_IO8(0x27) ++ ++/* Timer/Counter1 Output Compare Register B */ ++#define OCR1B _SFR_IO16(0x28) ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BH _SFR_IO8(0x29) ++ ++/* Timer/Counter1 Output Compare Register A */ ++#define OCR1A _SFR_IO16(0x2A) ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++ ++/* Timer/Counter 1 */ ++#define TCNT1 _SFR_IO16(0x2C) ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++ ++/* Timer/Counter 1 Control and Status Register */ ++#define TCCR1B _SFR_IO8(0x2E) ++ ++/* Timer/Counter 1 Control Register */ ++#define TCCR1A _SFR_IO8(0x2F) ++ ++/* Timer/Counter 0 */ ++#define TCNT0 _SFR_IO8(0x32) ++ ++/* Timer/Counter 0 Control Register */ ++#define TCCR0 _SFR_IO8(0x33) ++ ++/* MCU general Status Register */ ++#define MCUSR _SFR_IO8(0x34) ++ ++/* MCU general Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++ ++/* Timer/Counter Interrupt Flag register */ ++#define TIFR _SFR_IO8(0x38) ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define TIMSK _SFR_IO8(0x39) ++ ++/* General Interrupt Flag Register */ ++#define GIFR _SFR_IO8(0x3A) ++ ++/* General Interrupt MaSK register */ ++#define GIMSK _SFR_IO8(0x3B) ++ ++/* 0x3D..0x3E SP */ ++ ++/* 0x3F SREG */ ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt 1 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++#define SIG_INTERRUPT1 _VECTOR(2) ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect_num 3 ++#define TIMER2_COMP_vect _VECTOR(3) ++#define SIG_OUTPUT_COMPARE2 _VECTOR(3) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 4 ++#define TIMER2_OVF_vect _VECTOR(4) ++#define SIG_OVERFLOW2 _VECTOR(4) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 5 ++#define TIMER1_CAPT_vect _VECTOR(5) ++#define SIG_INPUT_CAPTURE1 _VECTOR(5) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 6 ++#define TIMER1_COMPA_vect _VECTOR(6) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(6) ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect_num 7 ++#define TIMER1_COMPB_vect _VECTOR(7) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(7) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 8 ++#define TIMER1_OVF_vect _VECTOR(8) ++#define SIG_OVERFLOW1 _VECTOR(8) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 9 ++#define TIMER0_OVF_vect _VECTOR(9) ++#define SIG_OVERFLOW0 _VECTOR(9) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 10 ++#define SPI_STC_vect _VECTOR(10) ++#define SIG_SPI _VECTOR(10) ++ ++/* UART, RX Complete */ ++#define UART_RX_vect_num 11 ++#define UART_RX_vect _VECTOR(11) ++#define SIG_UART_RECV _VECTOR(11) ++ ++/* UART Data Register Empty */ ++#define UART_UDRE_vect_num 12 ++#define UART_UDRE_vect _VECTOR(12) ++#define SIG_UART_DATA _VECTOR(12) ++ ++/* UART, TX Complete */ ++#define UART_TX_vect_num 13 ++#define UART_TX_vect _VECTOR(13) ++#define SIG_UART_TRANS _VECTOR(13) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 14 ++#define ADC_vect _VECTOR(14) ++#define SIG_ADC _VECTOR(14) ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect_num 15 ++#define EE_RDY_vect _VECTOR(15) ++#define SIG_EEPROM_READY _VECTOR(15) ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect_num 16 ++#define ANA_COMP_vect _VECTOR(16) ++#define SIG_COMPARATOR _VECTOR(16) ++ ++#define _VECTORS_SIZE 34 ++ ++/* ++ The Register Bit names are represented by their bit number (0-7). ++*/ ++ ++/* MCU general Status Register */ ++#define EXTRF 1 ++#define PORF 0 ++ ++/* General Interrupt MaSK register */ ++#define INT1 7 ++#define INT0 6 ++ ++/* General Interrupt Flag Register */ ++#define INTF1 7 ++#define INTF0 6 ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define OCIE2 7 ++#define TOIE2 6 ++#define TICIE1 5 ++#define OCIE1A 4 ++#define OCIE1B 3 ++#define TOIE1 2 ++#define TOIE0 0 ++ ++/* Timer/Counter Interrupt Flag register */ ++#define OCF2 7 ++#define TOV2 6 ++#define ICF1 5 ++#define OCF1A 4 ++#define OCF1B 3 ++#define TOV1 2 ++#define TOV0 0 ++ ++/* MCU general Control Register */ ++#define SE 6 ++#define SM1 5 ++#define SM0 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* Timer/Counter 0 Control Register */ ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* Timer/Counter 1 Control Register */ ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define PWM11 1 ++#define PWM10 0 ++ ++/* Timer/Counter 1 Control and Status Register */ ++#define ICNC1 7 ++#define ICES1 6 ++#define CTC1 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* Timer/Counter 2 Control Register */ ++#define PWM2 6 ++#define COM21 5 ++#define COM20 4 ++#define CTC2 3 ++#define CS22 2 ++#define CS21 1 ++#define CS20 0 ++ ++/* Asynchronous mode Status Register */ ++#define AS2 3 ++#define TCN2UB 2 ++#define OCR2UB 1 ++#define TCR2UB 0 ++ ++/* Watchdog Timer Control Register */ ++#define WDTOE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* Data Register, Port A */ ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++/* Data Direction Register, Port A */ ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++/* Input Pins, Port A */ ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++/* Data Register, Port B */ ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* Data Direction Register, Port B */ ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* Input Pins, Port B */ ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* Data Register, Port C */ ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++/* Data Direction Register, Port C */ ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++/* Input Pins, Port C */ ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++/* Data Register, Port D */ ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* Data Direction Register, Port D */ ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++/* Input Pins, Port D */ ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++/* SPI Control Register */ ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++/* SPI Status Register */ ++#define SPIF 7 ++#define WCOL 6 ++ ++/* UART Status Register */ ++#define RXC 7 ++#define TXC 6 ++#define UDRE 5 ++#define FE 4 ++#define DOR 3 ++ ++/* UART Control Register */ ++#define RXCIE 7 ++#define TXCIE 6 ++#define UDRIE 5 ++#define RXEN 4 ++#define TXEN 3 ++#define CHR9 2 ++#define RXB8 1 ++#define TXB8 0 ++ ++/* Analog Comparator Control and Status Register */ ++#define ACD 7 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++/* ADC MUX */ ++#define MUX2 2 ++#define MUX1 1 ++#define MUX0 0 ++ ++/* ADC Control and Status Register */ ++#define ADEN 7 ++#define ADSC 6 ++#define ADFR 5 ++#define ADIF 4 ++#define ADIE 3 ++#define ADPS2 2 ++#define ADPS1 1 ++#define ADPS0 0 ++ ++/* EEPROM Control Register */ ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++/* Constants */ ++#define RAMSTART 0x60 ++#define RAMEND 0x15F /*Last On-Chip SRAM location*/ ++#define XRAMEND RAMEND ++#define E2END 0xFF ++#define E2PAGESIZE 0 ++#define FLASHEND 0xFFF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Low Fuse Byte */ ++#define FUSE_SPIEN ~_BV(1) /* Serial Program Downloading Enabled */ ++#define FUSE_FSTRT ~_BV(2) /* Short Start-up time selected */ ++#define LFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x03 ++ ++ ++#endif /* _AVR_IO4434_H_ */ +diff --git a/include/avr/io76c711.h b/include/avr/io76c711.h +index 7ce3844..7009580 100644 +--- a/include/avr/io76c711.h ++++ b/include/avr/io76c711.h +@@ -1,493 +1,494 @@ +-/* Copyright (c) 2002, Marek Michalkiewicz +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: io76c711.h 1873 2009-02-11 17:53:39Z arcanum $ */ +- +-/* avr/io76c711.h - definitions for AT76C711 */ +- +-#ifndef _AVR_IO76C711_H_ +-#define _AVR_IO76C711_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "io76c711.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* 0x00-0x0C reserved */ +- +-/* SPI */ +-#define SPCR _SFR_IO8(0x0D) +-#define SPSR _SFR_IO8(0x0E) +-#define SPDR _SFR_IO8(0x0F) +- +-/* Port D */ +-#define PIND _SFR_IO8(0x10) +-#define DDRD _SFR_IO8(0x11) +-#define PORTD _SFR_IO8(0x12) +- +-/* Peripheral Enable Register */ +-#define PERIPHEN _SFR_IO8(0x13) +- +-/* Clock Control Register */ +-#define CLK_CNTR _SFR_IO8(0x14) +- +-/* Data Register, Port C */ +-#define PORTC _SFR_IO8(0x15) +- +-/* Port B */ +-#define PINB _SFR_IO8(0x16) +-#define DDRB _SFR_IO8(0x17) +-#define PORTB _SFR_IO8(0x18) +- +-/* Port A */ +-#define PINA _SFR_IO8(0x19) +-#define DDRA _SFR_IO8(0x1A) +-#define PORTA _SFR_IO8(0x1B) +- +-/* 0x1C-0x1F reserved */ +- +-#define IRDAMOD _SFR_IO8(0x20) +- +-#define WDTCR _SFR_IO8(0x21) +- +-/* 0x22-0x25 reserved */ +-/* Timer 1 */ +-#define ICR1 _SFR_IO16(0x26) +-#define ICR1L _SFR_IO8(0x26) +-#define ICR1H _SFR_IO8(0x27) +-#define OCR1B _SFR_IO16(0x28) +-#define OCR1BL _SFR_IO8(0x28) +-#define OCR1BH _SFR_IO8(0x29) +-#define OCR1A _SFR_IO16(0x2A) +-#define OCR1AL _SFR_IO8(0x2A) +-#define OCR1AH _SFR_IO8(0x2B) +-#define TCNT1 _SFR_IO16(0x2C) +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1H _SFR_IO8(0x2D) +-#define TCCR1B _SFR_IO8(0x2E) +-#define TCCR1A _SFR_IO8(0x2F) +- +-/* 0x30 reserved */ +- +-/* Timer 0 */ +-#define PRELD _SFR_IO8(0x31) +-#define TCNT0 _SFR_IO8(0x32) +-#define TCCR0 _SFR_IO8(0x33) +- +-#define MCUSR _SFR_IO8(0x34) +-#define MCUCR _SFR_IO8(0x35) +- +-#define TIFR _SFR_IO8(0x36) +-#define TIMSK _SFR_IO8(0x37) +- +-/* 0x38 reserved */ +- +-#define EIMSK _SFR_IO8(0x39) +- +-/* 0x3A-0x3C reserved */ +- +-/* 0x3D..0x3E SP */ +- +-/* 0x3F SREG */ +- +-/* Interrupt vectors */ +- +-#define SIG_SUSPEND_RESUME _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(2) +-#define SIG_INPUT_CAPTURE1 _VECTOR(3) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(4) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(5) +-#define SIG_OVERFLOW1 _VECTOR(6) +-#define SIG_OVERFLOW0 _VECTOR(7) +-#define SIG_SPI _VECTOR(8) +-#define SIG_TDMAC _VECTOR(9) +-#define SIG_UART0 _VECTOR(10) +-#define SIG_RDMAC _VECTOR(11) +-#define SIG_USB_HW _VECTOR(12) +-#define SIG_UART1 _VECTOR(13) +-#define SIG_INTERRUPT1 _VECTOR(14) +- +-#define _VECTORS_SIZE 60 +- +-/* Bit numbers */ +- +-/* EIMSK */ +-/* bits 7-4 reserved */ +-#define POL1 3 +-#define POL0 2 +-#define INT1 1 +-#define INT0 0 +- +-/* TIMSK */ +-#define TOIE1 7 +-#define OCIE1A 6 +-#define OCIE1B 5 +-/* bit 4 reserved */ +-#define TICIE1 3 +-/* bit 2 reserved */ +-#define TOIE0 1 +-/* bit 0 reserved */ +- +-/* TIFR */ +-#define TOV1 7 +-#define OCF1A 6 +-#define OCF1B 5 +-/* bit 4 reserved */ +-#define ICF1 3 +-/* bit 2 reserved */ +-#define TOV0 1 +-/* bit 0 reserved */ +- +-/* MCUCR */ +-/* bits 7-6 reserved */ +-#define SE 5 +-#define SM1 4 +-#define SM0 3 +-/* bits 2-0 reserved */ +- +-/* MCUSR */ +-/* bits 7-2 reserved */ +-#define EXTRF 1 +-#define PORF 0 +- +-/* TCCR0 */ +-/* bits 7-6 reserved */ +-#define COM01 5 +-#define COM00 4 +-#define CTC0 3 +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* TCCR1A */ +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-/* bits 3-0 reserved */ +- +-/* TCCR1B */ +-#define ICNC1 7 +-#define ICES1 6 +-/* bits 5-4 reserved */ +-#define CTC1 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* WDTCR */ +-/* bits 7-5 reserved */ +-#define WDTOE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* IRDAMOD */ +-/* bits 7-3 reserved */ +-#define POL 2 +-#define MODE 1 +-#define EN 0 +- +-/* PORTA */ +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-/* DDRA */ +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-/* PINA */ +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-/* +- PB7 = SCK +- PB6 = MISO +- PB5 = MOSI +- PB4 = SS# +- PB2 = ICP +- PB1 = T1 +- PB0 = T0 +- */ +- +-/* PORTB */ +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* DDRB */ +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* PINB */ +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* PORTC */ +-/* bits 7-4 reserved */ +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-/* +- PD7 = INT1 / OC1B +- PD6 = INT0 / OC1A +- PD1 = TXD +- PD0 = RXD +- */ +- +-/* PORTD */ +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* DDRD */ +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-/* PIND */ +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-/* CLK_CNTR */ +-/* bits 7-5 reserved */ +-#define UOSC 4 +-#define UCK 3 +-#define IRCK 2 +-/* bits 1-0 reserved */ +- +-/* PERIPHEN */ +-/* bits 7-3 reserved */ +-#define IRDA 2 +-#define UART 1 +-#define USB 0 +- +-/* SPSR */ +-#define SPIF 7 +-#define WCOL 6 +-/* bits 5-0 reserved */ +- +-/* SPCR */ +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +-/* Memory mapped registers (XXX - not yet changed to use _SFR_MEM8() macros) */ +- +-/* UART */ +-#define UART0_BASE 0x2020 +-#define UART1_BASE 0x2030 +-/* offsets from the base address */ +-#define US_RHR 0x00 +-#define US_THR 0x00 +-#define US_IER 0x01 +-#define US_FCR 0x02 +-#define US_PMR 0x03 +-#define US_MR 0x04 +-#define US_CSR 0x05 +-#define US_CR 0x06 +-#define US_BL 0x07 +-#define US_BM 0x08 +-#define US_RTO 0x09 +-#define US_TTG 0x0A +- +-/* DMA */ +-#define DMA_BASE 0x2000 +-/* offsets from the base address */ +-#define TXTADL 0x01 +-#define TXPLL 0x03 +-#define TXPLM 0x04 +-#define TXTPLL 0x05 +-#define TXTPLM 0x06 +-#define RXTADL 0x07 +-#define RXTADMEN 0x08 +-#define RSPLL 0x09 +-#define RXPLM 0x0A +-#define RXTPLL 0x0B +-#define RXTPLM 0x0C +-#define INTCST 0x0D +-/* XXX DPORG register mentioned on page 20, but undocumented */ +- +-/* XXX Program Memory Control Bit mentioned on page 20, but undocumented */ +-#define PROGRAM_MEMORY_CONTROL_BIT 0x2040 +- +-/* USB */ +-#define USB_BASE 0x1000 +-/* offsets from the base address */ +-#define FRM_NUM_H 0x0FD +-#define FRM_NUM_L 0x0FC +-#define GLB_STATE 0x0FB +-#define SPRSR 0x0FA +-#define SPRSIE 0x0F9 +-#define UISR 0x0F7 +-#define UIAR 0x0F5 +-#define FADDR 0x0F2 +-#define ENDPPGPG 0x0F1 +-#define ECR0 0x0EF +-#define ECR1 0x0EE +-#define ECR2 0x0ED +-#define ECR3 0x0EC +-#define ECR4 0x0EB +-#define ECR5 0x0EA +-#define ECR6 0x0E9 +-#define ECR7 0x0E8 +-#define CSR0 0x0DF +-#define CSR1 0x0DE +-#define CSR2 0x0DD +-#define CSR3 0x0DC +-#define CSR4 0x0DB +-#define CSR5 0x0DA +-#define CSR6 0x0D9 +-#define CSR7 0x0D8 +-#define FDR0 0x0CF +-#define FDR1 0x0CE +-#define FDR2 0x0CD +-#define FDR3 0x0CC +-#define FDR4 0x0CB +-#define FDR5 0x0CA +-#define FDR6 0x0C9 +-#define FDR7 0x0C8 +-#define FBYTE_CNT0_L 0x0BF +-#define FBYTE_CNT1_L 0x0BE +-#define FBYTE_CNT2_L 0x0BD +-#define FBYTE_CNT3_L 0x0BC +-#define FBYTE_CNT4_L 0x0BB +-#define FBYTE_CNT5_L 0x0BA +-#define FBYTE_CNT6_L 0x0B9 +-#define FBYTE_CNT7_L 0x0B8 +-#define FBYTE_CNT0_H 0x0AF +-#define FBYTE_CNT1_H 0x0AE +-#define FBYTE_CNT2_H 0x0AD +-#define FBYTE_CNT3_H 0x0AC +-#define FBYTE_CNT4_H 0x0AB +-#define FBYTE_CNT5_H 0x0AA +-#define FBYTE_CNT6_H 0x0A9 +-#define FBYTE_CNT7_H 0x0A8 +-#define SLP_MD_EN 0x100 +-#define IRQ_EN 0x101 +-#define IRQ_STAT 0x102 +-#define SUSP_WUP 0x103 +-#define PA_EN 0x104 +-#define USB_DMA_ADL 0x105 +-#define USB_DMA_ADH 0x106 +-#define USB_DMA_PLR 0x107 +-#define USB_DMA_EAD 0x108 +-#define USB_DMA_PLT 0x109 +-#define USB_DMA_EN 0x10A +- +-/* Last memory addresses */ +-#define RAMEND 0x07FF +-#define XRAMEND RAMEND +-#define E2END 0 +-#define FLASHEND 0x3FFF +- +-/* +- AT76C711 data space memory map (ranges not listed are reserved): +- 0x0000 - 0x001F - AVR registers +- 0x0020 - 0x005F - AVR I/O space +- 0x0060 - 0x07FF - AVR data SRAM +- 0x1000 - 0x1FFF - USB (not all locations used) +- 0x2000 - 0x201F - DMA controller +- 0x2020 - 0x202F - UART0 +- 0x2030 - 0x203F - UART1 (IRDA) +- 0x2040 - the mysterious Program Memory Control bit (???) +- 0x3000 - 0x37FF - DPRAM +- 0x8000 - 0xBFFF - program SRAM (read/write), would be nice if other +- AVR devices did that as well (no need to use LPM!) +- */ +-#endif /* _AVR_IO76C711_H_ */ ++/* Copyright (c) 2002, Marek Michalkiewicz ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: io76c711.h 1873 2009-02-11 17:53:39Z arcanum $ */ ++ ++/* avr/io76c711.h - definitions for AT76C711 */ ++ ++#ifndef _AVR_IO76C711_H_ ++#define _AVR_IO76C711_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "io76c711.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* 0x00-0x0C reserved */ ++ ++/* SPI */ ++#define SPCR _SFR_IO8(0x0D) ++#define SPSR _SFR_IO8(0x0E) ++#define SPDR _SFR_IO8(0x0F) ++ ++/* Port D */ ++#define PIND _SFR_IO8(0x10) ++#define DDRD _SFR_IO8(0x11) ++#define PORTD _SFR_IO8(0x12) ++ ++/* Peripheral Enable Register */ ++#define PERIPHEN _SFR_IO8(0x13) ++ ++/* Clock Control Register */ ++#define CLK_CNTR _SFR_IO8(0x14) ++ ++/* Data Register, Port C */ ++#define PORTC _SFR_IO8(0x15) ++ ++/* Port B */ ++#define PINB _SFR_IO8(0x16) ++#define DDRB _SFR_IO8(0x17) ++#define PORTB _SFR_IO8(0x18) ++ ++/* Port A */ ++#define PINA _SFR_IO8(0x19) ++#define DDRA _SFR_IO8(0x1A) ++#define PORTA _SFR_IO8(0x1B) ++ ++/* 0x1C-0x1F reserved */ ++ ++#define IRDAMOD _SFR_IO8(0x20) ++ ++#define WDTCR _SFR_IO8(0x21) ++ ++/* 0x22-0x25 reserved */ ++/* Timer 1 */ ++#define ICR1 _SFR_IO16(0x26) ++#define ICR1L _SFR_IO8(0x26) ++#define ICR1H _SFR_IO8(0x27) ++#define OCR1B _SFR_IO16(0x28) ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BH _SFR_IO8(0x29) ++#define OCR1A _SFR_IO16(0x2A) ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++#define TCNT1 _SFR_IO16(0x2C) ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++#define TCCR1B _SFR_IO8(0x2E) ++#define TCCR1A _SFR_IO8(0x2F) ++ ++/* 0x30 reserved */ ++ ++/* Timer 0 */ ++#define PRELD _SFR_IO8(0x31) ++#define TCNT0 _SFR_IO8(0x32) ++#define TCCR0 _SFR_IO8(0x33) ++ ++#define MCUSR _SFR_IO8(0x34) ++#define MCUCR _SFR_IO8(0x35) ++ ++#define TIFR _SFR_IO8(0x36) ++#define TIMSK _SFR_IO8(0x37) ++ ++/* 0x38 reserved */ ++ ++#define EIMSK _SFR_IO8(0x39) ++ ++/* 0x3A-0x3C reserved */ ++ ++/* 0x3D..0x3E SP */ ++ ++/* 0x3F SREG */ ++ ++/* Interrupt vectors */ ++ ++#define SIG_SUSPEND_RESUME _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(2) ++#define SIG_INPUT_CAPTURE1 _VECTOR(3) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(4) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(5) ++#define SIG_OVERFLOW1 _VECTOR(6) ++#define SIG_OVERFLOW0 _VECTOR(7) ++#define SIG_SPI _VECTOR(8) ++#define SIG_TDMAC _VECTOR(9) ++#define SIG_UART0 _VECTOR(10) ++#define SIG_RDMAC _VECTOR(11) ++#define SIG_USB_HW _VECTOR(12) ++#define SIG_UART1 _VECTOR(13) ++#define SIG_INTERRUPT1 _VECTOR(14) ++ ++#define _VECTORS_SIZE 60 ++ ++/* Bit numbers */ ++ ++/* EIMSK */ ++/* bits 7-4 reserved */ ++#define POL1 3 ++#define POL0 2 ++#define INT1 1 ++#define INT0 0 ++ ++/* TIMSK */ ++#define TOIE1 7 ++#define OCIE1A 6 ++#define OCIE1B 5 ++/* bit 4 reserved */ ++#define TICIE1 3 ++/* bit 2 reserved */ ++#define TOIE0 1 ++/* bit 0 reserved */ ++ ++/* TIFR */ ++#define TOV1 7 ++#define OCF1A 6 ++#define OCF1B 5 ++/* bit 4 reserved */ ++#define ICF1 3 ++/* bit 2 reserved */ ++#define TOV0 1 ++/* bit 0 reserved */ ++ ++/* MCUCR */ ++/* bits 7-6 reserved */ ++#define SE 5 ++#define SM1 4 ++#define SM0 3 ++/* bits 2-0 reserved */ ++ ++/* MCUSR */ ++/* bits 7-2 reserved */ ++#define EXTRF 1 ++#define PORF 0 ++ ++/* TCCR0 */ ++/* bits 7-6 reserved */ ++#define COM01 5 ++#define COM00 4 ++#define CTC0 3 ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* TCCR1A */ ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++/* bits 3-0 reserved */ ++ ++/* TCCR1B */ ++#define ICNC1 7 ++#define ICES1 6 ++/* bits 5-4 reserved */ ++#define CTC1 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* WDTCR */ ++/* bits 7-5 reserved */ ++#define WDTOE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* IRDAMOD */ ++/* bits 7-3 reserved */ ++#define POL 2 ++#define MODE 1 ++#define EN 0 ++ ++/* PORTA */ ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++/* DDRA */ ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++/* PINA */ ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++/* ++ PB7 = SCK ++ PB6 = MISO ++ PB5 = MOSI ++ PB4 = SS# ++ PB2 = ICP ++ PB1 = T1 ++ PB0 = T0 ++ */ ++ ++/* PORTB */ ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* DDRB */ ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* PINB */ ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* PORTC */ ++/* bits 7-4 reserved */ ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++/* ++ PD7 = INT1 / OC1B ++ PD6 = INT0 / OC1A ++ PD1 = TXD ++ PD0 = RXD ++ */ ++ ++/* PORTD */ ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* DDRD */ ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++/* PIND */ ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++/* CLK_CNTR */ ++/* bits 7-5 reserved */ ++#define UOSC 4 ++#define UCK 3 ++#define IRCK 2 ++/* bits 1-0 reserved */ ++ ++/* PERIPHEN */ ++/* bits 7-3 reserved */ ++#define IRDA 2 ++#define UART 1 ++#define USB 0 ++ ++/* SPSR */ ++#define SPIF 7 ++#define WCOL 6 ++/* bits 5-0 reserved */ ++ ++/* SPCR */ ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++/* Memory mapped registers (XXX - not yet changed to use _SFR_MEM8() macros) */ ++ ++/* UART */ ++#define UART0_BASE 0x2020 ++#define UART1_BASE 0x2030 ++/* offsets from the base address */ ++#define US_RHR 0x00 ++#define US_THR 0x00 ++#define US_IER 0x01 ++#define US_FCR 0x02 ++#define US_PMR 0x03 ++#define US_MR 0x04 ++#define US_CSR 0x05 ++#define US_CR 0x06 ++#define US_BL 0x07 ++#define US_BM 0x08 ++#define US_RTO 0x09 ++#define US_TTG 0x0A ++ ++/* DMA */ ++#define DMA_BASE 0x2000 ++/* offsets from the base address */ ++#define TXTADL 0x01 ++#define TXPLL 0x03 ++#define TXPLM 0x04 ++#define TXTPLL 0x05 ++#define TXTPLM 0x06 ++#define RXTADL 0x07 ++#define RXTADMEN 0x08 ++#define RSPLL 0x09 ++#define RXPLM 0x0A ++#define RXTPLL 0x0B ++#define RXTPLM 0x0C ++#define INTCST 0x0D ++/* XXX DPORG register mentioned on page 20, but undocumented */ ++ ++/* XXX Program Memory Control Bit mentioned on page 20, but undocumented */ ++#define PROGRAM_MEMORY_CONTROL_BIT 0x2040 ++ ++/* USB */ ++#define USB_BASE 0x1000 ++/* offsets from the base address */ ++#define FRM_NUM_H 0x0FD ++#define FRM_NUM_L 0x0FC ++#define GLB_STATE 0x0FB ++#define SPRSR 0x0FA ++#define SPRSIE 0x0F9 ++#define UISR 0x0F7 ++#define UIAR 0x0F5 ++#define FADDR 0x0F2 ++#define ENDPPGPG 0x0F1 ++#define ECR0 0x0EF ++#define ECR1 0x0EE ++#define ECR2 0x0ED ++#define ECR3 0x0EC ++#define ECR4 0x0EB ++#define ECR5 0x0EA ++#define ECR6 0x0E9 ++#define ECR7 0x0E8 ++#define CSR0 0x0DF ++#define CSR1 0x0DE ++#define CSR2 0x0DD ++#define CSR3 0x0DC ++#define CSR4 0x0DB ++#define CSR5 0x0DA ++#define CSR6 0x0D9 ++#define CSR7 0x0D8 ++#define FDR0 0x0CF ++#define FDR1 0x0CE ++#define FDR2 0x0CD ++#define FDR3 0x0CC ++#define FDR4 0x0CB ++#define FDR5 0x0CA ++#define FDR6 0x0C9 ++#define FDR7 0x0C8 ++#define FBYTE_CNT0_L 0x0BF ++#define FBYTE_CNT1_L 0x0BE ++#define FBYTE_CNT2_L 0x0BD ++#define FBYTE_CNT3_L 0x0BC ++#define FBYTE_CNT4_L 0x0BB ++#define FBYTE_CNT5_L 0x0BA ++#define FBYTE_CNT6_L 0x0B9 ++#define FBYTE_CNT7_L 0x0B8 ++#define FBYTE_CNT0_H 0x0AF ++#define FBYTE_CNT1_H 0x0AE ++#define FBYTE_CNT2_H 0x0AD ++#define FBYTE_CNT3_H 0x0AC ++#define FBYTE_CNT4_H 0x0AB ++#define FBYTE_CNT5_H 0x0AA ++#define FBYTE_CNT6_H 0x0A9 ++#define FBYTE_CNT7_H 0x0A8 ++#define SLP_MD_EN 0x100 ++#define IRQ_EN 0x101 ++#define IRQ_STAT 0x102 ++#define SUSP_WUP 0x103 ++#define PA_EN 0x104 ++#define USB_DMA_ADL 0x105 ++#define USB_DMA_ADH 0x106 ++#define USB_DMA_PLR 0x107 ++#define USB_DMA_EAD 0x108 ++#define USB_DMA_PLT 0x109 ++#define USB_DMA_EN 0x10A ++ ++/* Last memory addresses */ ++#define RAMSTART 0x60 ++#define RAMEND 0x07FF ++#define XRAMEND RAMEND ++#define E2END 0 ++#define FLASHEND 0x3FFF ++ ++/* ++ AT76C711 data space memory map (ranges not listed are reserved): ++ 0x0000 - 0x001F - AVR registers ++ 0x0020 - 0x005F - AVR I/O space ++ 0x0060 - 0x07FF - AVR data SRAM ++ 0x1000 - 0x1FFF - USB (not all locations used) ++ 0x2000 - 0x201F - DMA controller ++ 0x2020 - 0x202F - UART0 ++ 0x2030 - 0x203F - UART1 (IRDA) ++ 0x2040 - the mysterious Program Memory Control bit (???) ++ 0x3000 - 0x37FF - DPRAM ++ 0x8000 - 0xBFFF - program SRAM (read/write), would be nice if other ++ AVR devices did that as well (no need to use LPM!) ++ */ ++#endif /* _AVR_IO76C711_H_ */ +diff --git a/include/avr/io8515.h b/include/avr/io8515.h +index 2a931b8..76b9e6a 100644 +--- a/include/avr/io8515.h ++++ b/include/avr/io8515.h +@@ -1,498 +1,499 @@ +-/* Copyright (c) 2002, Marek Michalkiewicz +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: io8515.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* avr/io8515.h - definitions for AT90S8515 */ +- +-#ifndef _AVR_IO8515_H_ +-#define _AVR_IO8515_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "io8515.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* Analog Comparator Control and Status Register */ +-#define ACSR _SFR_IO8(0x08) +- +-/* UART Baud Rate Register */ +-#define UBRR _SFR_IO8(0x09) +- +-/* UART Control Register */ +-#define UCR _SFR_IO8(0x0A) +- +-/* UART Status Register */ +-#define USR _SFR_IO8(0x0B) +- +-/* UART I/O Data Register */ +-#define UDR _SFR_IO8(0x0C) +- +-/* SPI Control Register */ +-#define SPCR _SFR_IO8(0x0D) +- +-/* SPI Status Register */ +-#define SPSR _SFR_IO8(0x0E) +- +-/* SPI I/O Data Register */ +-#define SPDR _SFR_IO8(0x0F) +- +-/* Input Pins, Port D */ +-#define PIND _SFR_IO8(0x10) +- +-/* Data Direction Register, Port D */ +-#define DDRD _SFR_IO8(0x11) +- +-/* Data Register, Port D */ +-#define PORTD _SFR_IO8(0x12) +- +-/* Input Pins, Port C */ +-#define PINC _SFR_IO8(0x13) +- +-/* Data Direction Register, Port C */ +-#define DDRC _SFR_IO8(0x14) +- +-/* Data Register, Port C */ +-#define PORTC _SFR_IO8(0x15) +- +-/* Input Pins, Port B */ +-#define PINB _SFR_IO8(0x16) +- +-/* Data Direction Register, Port B */ +-#define DDRB _SFR_IO8(0x17) +- +-/* Data Register, Port B */ +-#define PORTB _SFR_IO8(0x18) +- +-/* Input Pins, Port A */ +-#define PINA _SFR_IO8(0x19) +- +-/* Data Direction Register, Port A */ +-#define DDRA _SFR_IO8(0x1A) +- +-/* Data Register, Port A */ +-#define PORTA _SFR_IO8(0x1B) +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO16(0x1E) +-#define EEARL _SFR_IO8(0x1E) +-#define EEARH _SFR_IO8(0x1F) +- +-/* Watchdog Timer Control Register */ +-#define WDTCR _SFR_IO8(0x21) +- +-/* T/C 1 Input Capture Register */ +-#define ICR1 _SFR_IO16(0x24) +-#define ICR1L _SFR_IO8(0x24) +-#define ICR1H _SFR_IO8(0x25) +- +-/* Timer/Counter1 Output Compare Register B */ +-#define OCR1B _SFR_IO16(0x28) +-#define OCR1BL _SFR_IO8(0x28) +-#define OCR1BH _SFR_IO8(0x29) +- +-/* Timer/Counter1 Output Compare Register A */ +-#define OCR1A _SFR_IO16(0x2A) +-#define OCR1AL _SFR_IO8(0x2A) +-#define OCR1AH _SFR_IO8(0x2B) +- +-/* Timer/Counter 1 */ +-#define TCNT1 _SFR_IO16(0x2C) +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1H _SFR_IO8(0x2D) +- +-/* Timer/Counter 1 Control and Status Register */ +-#define TCCR1B _SFR_IO8(0x2E) +- +-/* Timer/Counter 1 Control Register */ +-#define TCCR1A _SFR_IO8(0x2F) +- +-/* Timer/Counter 0 */ +-#define TCNT0 _SFR_IO8(0x32) +- +-/* Timer/Counter 0 Control Register */ +-#define TCCR0 _SFR_IO8(0x33) +- +-/* MCU general Control Register */ +-#define MCUCR _SFR_IO8(0x35) +- +-/* Timer/Counter Interrupt Flag register */ +-#define TIFR _SFR_IO8(0x38) +- +-/* Timer/Counter Interrupt MaSK register */ +-#define TIMSK _SFR_IO8(0x39) +- +-/* General Interrupt Flag Register */ +-#define GIFR _SFR_IO8(0x3A) +- +-/* General Interrupt MaSK register */ +-#define GIMSK _SFR_IO8(0x3B) +- +-/* 0x3D..0x3E SP */ +- +-/* 0x3F SREG */ +- +-/* Interrupt vectors */ +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt Request 1 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +-#define SIG_INTERRUPT1 _VECTOR(2) +- +-/* Timer/Counter Capture Event */ +-#define TIMER1_CAPT_vect_num 3 +-#define TIMER1_CAPT_vect _VECTOR(3) +-#define SIG_INPUT_CAPTURE1 _VECTOR(3) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 4 +-#define TIMER1_COMPA_vect _VECTOR(4) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(4) +- +-/* Timer/Counter1 Compare MatchB */ +-#define TIMER1_COMPB_vect_num 5 +-#define TIMER1_COMPB_vect _VECTOR(5) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(5) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 6 +-#define TIMER1_OVF_vect _VECTOR(6) +-#define SIG_OVERFLOW1 _VECTOR(6) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 7 +-#define TIMER0_OVF_vect _VECTOR(7) +-#define SIG_OVERFLOW0 _VECTOR(7) +- +-/* Serial Transfer Complete */ +-#define SPI_STC_vect_num 8 +-#define SPI_STC_vect _VECTOR(8) +-#define SIG_SPI _VECTOR(8) +- +-/* UART, Rx Complete */ +-#define UART_RX_vect_num 9 +-#define UART_RX_vect _VECTOR(9) +-#define SIG_UART_RECV _VECTOR(9) +- +-/* UART Data Register Empty */ +-#define UART_UDRE_vect_num 10 +-#define UART_UDRE_vect _VECTOR(10) +-#define SIG_UART_DATA _VECTOR(10) +- +-/* UART, Tx Complete */ +-#define UART_TX_vect_num 11 +-#define UART_TX_vect _VECTOR(11) +-#define SIG_UART_TRANS _VECTOR(11) +- +-/* Analog Comparator */ +-#define ANA_COMP_vect_num 12 +-#define ANA_COMP_vect _VECTOR(12) +-#define SIG_COMPARATOR _VECTOR(12) +- +-#define _VECTORS_SIZE 26 +- +-/* +- The Register Bit names are represented by their bit number (0-7). +-*/ +- +-/* General Interrupt MaSK register */ +-#define INT1 7 +-#define INT0 6 +- +-/* General Interrupt Flag Register */ +-#define INTF1 7 +-#define INTF0 6 +- +-/* Timer/Counter Interrupt MaSK register */ +-#define TOIE1 7 +-#define OCIE1A 6 +-#define OCIE1B 5 +-#define TICIE1 3 +-#define TOIE0 1 +- +-/* Timer/Counter Interrupt Flag register */ +-#define TOV1 7 +-#define OCF1A 6 +-#define OCF1B 5 +-#define ICF1 3 +-#define TOV0 1 +- +-/* MCU general Control Register */ +-#define SRE 7 +-#define SRW 6 +-#define SE 5 +-#define SM 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-/* Timer/Counter 0 Control Register */ +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* Timer/Counter 1 Control Register */ +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define PWM11 1 +-#define PWM10 0 +- +-/* Timer/Counter 1 Control and Status Register */ +-#define ICNC1 7 +-#define ICES1 6 +-#define CTC1 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* Watchdog Timer Control Register */ +-#define WDTOE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* Data Register, Port A */ +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-/* Data Direction Register, Port A */ +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-/* Input Pins, Port A */ +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-/* Data Register, Port B */ +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* Data Direction Register, Port B */ +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* Input Pins, Port B */ +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* Data Register, Port C */ +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-/* Data Direction Register, Port C */ +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-/* Input Pins, Port C */ +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-/* Data Register, Port D */ +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* Data Direction Register, Port D */ +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-/* Input Pins, Port D */ +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-/* SPI Status Register */ +-#define SPIF 7 +-#define WCOL 6 +- +-/* SPI Control Register */ +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +-/* UART Status Register */ +-#define RXC 7 +-#define TXC 6 +-#define UDRE 5 +-#define FE 4 +-#define DOR 3 +- +-/* UART Control Register */ +-#define RXCIE 7 +-#define TXCIE 6 +-#define UDRIE 5 +-#define RXEN 4 +-#define TXEN 3 +-#define CHR9 2 +-#define RXB8 1 +-#define TXB8 0 +- +-/* Analog Comparator Control and Status Register */ +-#define ACD 7 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +- +-/* EEPROM Control Register */ +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-/* Constants */ +-#define RAMEND 0x25F /* Last On-Chip SRAM Location */ +-#define XRAMEND 0xFFFF +-#define E2END 0x1FF +-#define E2PAGESIZE 0 +-#define FLASHEND 0x1FFF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 1 +- +-/* Low Fuse Byte */ +-#define FUSE_SPIEN ~_BV(1) /* Serial Program Downloading Enabled */ +-#define FUSE_FSTRT ~_BV(2) /* Short Start-up time selected */ +-#define LFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x93 +-#define SIGNATURE_2 0x01 +- +- +-#endif /* _AVR_IO8515_H_ */ ++/* Copyright (c) 2002, Marek Michalkiewicz ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: io8515.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* avr/io8515.h - definitions for AT90S8515 */ ++ ++#ifndef _AVR_IO8515_H_ ++#define _AVR_IO8515_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "io8515.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* Analog Comparator Control and Status Register */ ++#define ACSR _SFR_IO8(0x08) ++ ++/* UART Baud Rate Register */ ++#define UBRR _SFR_IO8(0x09) ++ ++/* UART Control Register */ ++#define UCR _SFR_IO8(0x0A) ++ ++/* UART Status Register */ ++#define USR _SFR_IO8(0x0B) ++ ++/* UART I/O Data Register */ ++#define UDR _SFR_IO8(0x0C) ++ ++/* SPI Control Register */ ++#define SPCR _SFR_IO8(0x0D) ++ ++/* SPI Status Register */ ++#define SPSR _SFR_IO8(0x0E) ++ ++/* SPI I/O Data Register */ ++#define SPDR _SFR_IO8(0x0F) ++ ++/* Input Pins, Port D */ ++#define PIND _SFR_IO8(0x10) ++ ++/* Data Direction Register, Port D */ ++#define DDRD _SFR_IO8(0x11) ++ ++/* Data Register, Port D */ ++#define PORTD _SFR_IO8(0x12) ++ ++/* Input Pins, Port C */ ++#define PINC _SFR_IO8(0x13) ++ ++/* Data Direction Register, Port C */ ++#define DDRC _SFR_IO8(0x14) ++ ++/* Data Register, Port C */ ++#define PORTC _SFR_IO8(0x15) ++ ++/* Input Pins, Port B */ ++#define PINB _SFR_IO8(0x16) ++ ++/* Data Direction Register, Port B */ ++#define DDRB _SFR_IO8(0x17) ++ ++/* Data Register, Port B */ ++#define PORTB _SFR_IO8(0x18) ++ ++/* Input Pins, Port A */ ++#define PINA _SFR_IO8(0x19) ++ ++/* Data Direction Register, Port A */ ++#define DDRA _SFR_IO8(0x1A) ++ ++/* Data Register, Port A */ ++#define PORTA _SFR_IO8(0x1B) ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO16(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++#define EEARH _SFR_IO8(0x1F) ++ ++/* Watchdog Timer Control Register */ ++#define WDTCR _SFR_IO8(0x21) ++ ++/* T/C 1 Input Capture Register */ ++#define ICR1 _SFR_IO16(0x24) ++#define ICR1L _SFR_IO8(0x24) ++#define ICR1H _SFR_IO8(0x25) ++ ++/* Timer/Counter1 Output Compare Register B */ ++#define OCR1B _SFR_IO16(0x28) ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BH _SFR_IO8(0x29) ++ ++/* Timer/Counter1 Output Compare Register A */ ++#define OCR1A _SFR_IO16(0x2A) ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++ ++/* Timer/Counter 1 */ ++#define TCNT1 _SFR_IO16(0x2C) ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++ ++/* Timer/Counter 1 Control and Status Register */ ++#define TCCR1B _SFR_IO8(0x2E) ++ ++/* Timer/Counter 1 Control Register */ ++#define TCCR1A _SFR_IO8(0x2F) ++ ++/* Timer/Counter 0 */ ++#define TCNT0 _SFR_IO8(0x32) ++ ++/* Timer/Counter 0 Control Register */ ++#define TCCR0 _SFR_IO8(0x33) ++ ++/* MCU general Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++ ++/* Timer/Counter Interrupt Flag register */ ++#define TIFR _SFR_IO8(0x38) ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define TIMSK _SFR_IO8(0x39) ++ ++/* General Interrupt Flag Register */ ++#define GIFR _SFR_IO8(0x3A) ++ ++/* General Interrupt MaSK register */ ++#define GIMSK _SFR_IO8(0x3B) ++ ++/* 0x3D..0x3E SP */ ++ ++/* 0x3F SREG */ ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++#define SIG_INTERRUPT1 _VECTOR(2) ++ ++/* Timer/Counter Capture Event */ ++#define TIMER1_CAPT_vect_num 3 ++#define TIMER1_CAPT_vect _VECTOR(3) ++#define SIG_INPUT_CAPTURE1 _VECTOR(3) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 4 ++#define TIMER1_COMPA_vect _VECTOR(4) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(4) ++ ++/* Timer/Counter1 Compare MatchB */ ++#define TIMER1_COMPB_vect_num 5 ++#define TIMER1_COMPB_vect _VECTOR(5) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(5) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 6 ++#define TIMER1_OVF_vect _VECTOR(6) ++#define SIG_OVERFLOW1 _VECTOR(6) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 7 ++#define TIMER0_OVF_vect _VECTOR(7) ++#define SIG_OVERFLOW0 _VECTOR(7) ++ ++/* Serial Transfer Complete */ ++#define SPI_STC_vect_num 8 ++#define SPI_STC_vect _VECTOR(8) ++#define SIG_SPI _VECTOR(8) ++ ++/* UART, Rx Complete */ ++#define UART_RX_vect_num 9 ++#define UART_RX_vect _VECTOR(9) ++#define SIG_UART_RECV _VECTOR(9) ++ ++/* UART Data Register Empty */ ++#define UART_UDRE_vect_num 10 ++#define UART_UDRE_vect _VECTOR(10) ++#define SIG_UART_DATA _VECTOR(10) ++ ++/* UART, Tx Complete */ ++#define UART_TX_vect_num 11 ++#define UART_TX_vect _VECTOR(11) ++#define SIG_UART_TRANS _VECTOR(11) ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect_num 12 ++#define ANA_COMP_vect _VECTOR(12) ++#define SIG_COMPARATOR _VECTOR(12) ++ ++#define _VECTORS_SIZE 26 ++ ++/* ++ The Register Bit names are represented by their bit number (0-7). ++*/ ++ ++/* General Interrupt MaSK register */ ++#define INT1 7 ++#define INT0 6 ++ ++/* General Interrupt Flag Register */ ++#define INTF1 7 ++#define INTF0 6 ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define TOIE1 7 ++#define OCIE1A 6 ++#define OCIE1B 5 ++#define TICIE1 3 ++#define TOIE0 1 ++ ++/* Timer/Counter Interrupt Flag register */ ++#define TOV1 7 ++#define OCF1A 6 ++#define OCF1B 5 ++#define ICF1 3 ++#define TOV0 1 ++ ++/* MCU general Control Register */ ++#define SRE 7 ++#define SRW 6 ++#define SE 5 ++#define SM 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* Timer/Counter 0 Control Register */ ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* Timer/Counter 1 Control Register */ ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define PWM11 1 ++#define PWM10 0 ++ ++/* Timer/Counter 1 Control and Status Register */ ++#define ICNC1 7 ++#define ICES1 6 ++#define CTC1 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* Watchdog Timer Control Register */ ++#define WDTOE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* Data Register, Port A */ ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++/* Data Direction Register, Port A */ ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++/* Input Pins, Port A */ ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++/* Data Register, Port B */ ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* Data Direction Register, Port B */ ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* Input Pins, Port B */ ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* Data Register, Port C */ ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++/* Data Direction Register, Port C */ ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++/* Input Pins, Port C */ ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++/* Data Register, Port D */ ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* Data Direction Register, Port D */ ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++/* Input Pins, Port D */ ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++/* SPI Status Register */ ++#define SPIF 7 ++#define WCOL 6 ++ ++/* SPI Control Register */ ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++/* UART Status Register */ ++#define RXC 7 ++#define TXC 6 ++#define UDRE 5 ++#define FE 4 ++#define DOR 3 ++ ++/* UART Control Register */ ++#define RXCIE 7 ++#define TXCIE 6 ++#define UDRIE 5 ++#define RXEN 4 ++#define TXEN 3 ++#define CHR9 2 ++#define RXB8 1 ++#define TXB8 0 ++ ++/* Analog Comparator Control and Status Register */ ++#define ACD 7 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++/* EEPROM Control Register */ ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++/* Constants */ ++#define RAMSTART 0x60 ++#define RAMEND 0x25F /* Last On-Chip SRAM Location */ ++#define XRAMEND 0xFFFF ++#define E2END 0x1FF ++#define E2PAGESIZE 0 ++#define FLASHEND 0x1FFF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Low Fuse Byte */ ++#define FUSE_SPIEN ~_BV(1) /* Serial Program Downloading Enabled */ ++#define FUSE_FSTRT ~_BV(2) /* Short Start-up time selected */ ++#define LFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x01 ++ ++ ++#endif /* _AVR_IO8515_H_ */ +diff --git a/include/avr/io8534.h b/include/avr/io8534.h +index 08e79da..63d4ad0 100644 +--- a/include/avr/io8534.h ++++ b/include/avr/io8534.h +@@ -1,216 +1,217 @@ +-/* Copyright (c) 2002, Marek Michalkiewicz +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: io8534.h 1873 2009-02-11 17:53:39Z arcanum $ */ +- +-/* avr/io8534.h - definitions for AT90C8534 */ +- +-#ifndef _AVR_IO8534_ +-#define _AVR_IO8534_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "io8534.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* 0x00..0x03 reserved */ +- +-/* ADC Data Register */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x04) +-#endif +-#define ADCW _SFR_IO16(0x04) +-#define ADCL _SFR_IO8(0x04) +-#define ADCH _SFR_IO8(0x05) +- +-/* ADC Control and Status Register */ +-#define ADCSR _SFR_IO8(0x06) +- +-/* ADC Multiplexer Select Register */ +-#define ADMUX _SFR_IO8(0x07) +- +-/* 0x08..0x0F reserved */ +- +-/* General Interrupt Pin Register */ +-#define GIPR _SFR_IO8(0x10) +- +-/* 0x11..0x19 reserved */ +- +-/* Data Direction Register, Port A */ +-#define DDRA _SFR_IO8(0x1A) +- +-/* Data Register, Port A */ +-#define PORTA _SFR_IO8(0x1B) +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO16(0x1E) +-#define EEARL _SFR_IO8(0x1E) +-#define EEARH _SFR_IO8(0x1F) +- +-/* 0x20..0x2B reserved */ +- +-/* Timer/Counter1 */ +-#define TCNT1 _SFR_IO16(0x2C) +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1H _SFR_IO8(0x2D) +- +-/* Timer/Counter1 Control Register */ +-#define TCCR1 _SFR_IO8(0x2E) +- +-/* 0x2F..0x31 reserved */ +- +-/* Timer/Counter0 (8-bit) */ +-#define TCNT0 _SFR_IO8(0x32) +- +-/* Timer/Counter0 Control Register */ +-#define TCCR0 _SFR_IO8(0x33) +- +-/* 0x34 reserved */ +- +-/* MCU general Control Register */ +-#define MCUCR _SFR_IO8(0x35) +- +-/* 0x36..0x37 reserved */ +- +-/* Timer/Counter Interrupt Flag Register */ +-#define TIFR _SFR_IO8(0x38) +- +-/* Timer/Counter Interrupt MaSK Register */ +-#define TIMSK _SFR_IO8(0x39) +- +-/* General Interrupt Flag Register */ +-#define GIFR _SFR_IO8(0x3A) +- +-/* General Interrupt MaSK register */ +-#define GIMSK _SFR_IO8(0x3B) +- +-/* 0x3C reserved */ +- +-/* 0x3D..0x3E SP */ +- +-/* 0x3F SREG */ +- +-/* Interrupt vectors */ +- +-#define SIG_INTERRUPT0 _VECTOR(1) +-#define SIG_INTERRUPT1 _VECTOR(2) +-#define SIG_OVERFLOW1 _VECTOR(3) +-#define SIG_OVERFLOW0 _VECTOR(4) +-#define SIG_ADC _VECTOR(5) +-#define SIG_EEPROM_READY _VECTOR(6) +- +-#define _VECTORS_SIZE 14 +- +-/* Bit numbers */ +- +-/* GIMSK */ +-#define INT1 7 +-#define INT0 6 +- +-/* GIFR */ +-#define INTF1 7 +-#define INTF0 6 +- +-/* GIPR */ +-#define IPIN1 3 +-#define IPIN0 2 +- +-/* TIMSK */ +-#define TOIE1 2 +-#define TOIE0 0 +- +-/* TIFR */ +-#define TOV1 2 +-#define TOV0 0 +- +-/* MCUCR */ +-#define SE 6 +-#define SM 5 +-#define ISC1 2 +-#define ISC0 0 +- +-/* TCCR0 */ +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* TCCR1 */ +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* PORTA */ +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-/* DDRA */ +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-/* EEPROM Control Register */ +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-/* Last memory addresses */ +-#define RAMEND 0x15F +-#define XRAMEND RAMEND +-#define E2END 0x1FF +-#define FLASHEND 0x1FFF +- +-#endif /* _AVR_IO8534_H_ */ ++/* Copyright (c) 2002, Marek Michalkiewicz ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: io8534.h 1873 2009-02-11 17:53:39Z arcanum $ */ ++ ++/* avr/io8534.h - definitions for AT90C8534 */ ++ ++#ifndef _AVR_IO8534_ ++#define _AVR_IO8534_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "io8534.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* 0x00..0x03 reserved */ ++ ++/* ADC Data Register */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCW _SFR_IO16(0x04) ++#define ADCL _SFR_IO8(0x04) ++#define ADCH _SFR_IO8(0x05) ++ ++/* ADC Control and Status Register */ ++#define ADCSR _SFR_IO8(0x06) ++ ++/* ADC Multiplexer Select Register */ ++#define ADMUX _SFR_IO8(0x07) ++ ++/* 0x08..0x0F reserved */ ++ ++/* General Interrupt Pin Register */ ++#define GIPR _SFR_IO8(0x10) ++ ++/* 0x11..0x19 reserved */ ++ ++/* Data Direction Register, Port A */ ++#define DDRA _SFR_IO8(0x1A) ++ ++/* Data Register, Port A */ ++#define PORTA _SFR_IO8(0x1B) ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO16(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++#define EEARH _SFR_IO8(0x1F) ++ ++/* 0x20..0x2B reserved */ ++ ++/* Timer/Counter1 */ ++#define TCNT1 _SFR_IO16(0x2C) ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++ ++/* Timer/Counter1 Control Register */ ++#define TCCR1 _SFR_IO8(0x2E) ++ ++/* 0x2F..0x31 reserved */ ++ ++/* Timer/Counter0 (8-bit) */ ++#define TCNT0 _SFR_IO8(0x32) ++ ++/* Timer/Counter0 Control Register */ ++#define TCCR0 _SFR_IO8(0x33) ++ ++/* 0x34 reserved */ ++ ++/* MCU general Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++ ++/* 0x36..0x37 reserved */ ++ ++/* Timer/Counter Interrupt Flag Register */ ++#define TIFR _SFR_IO8(0x38) ++ ++/* Timer/Counter Interrupt MaSK Register */ ++#define TIMSK _SFR_IO8(0x39) ++ ++/* General Interrupt Flag Register */ ++#define GIFR _SFR_IO8(0x3A) ++ ++/* General Interrupt MaSK register */ ++#define GIMSK _SFR_IO8(0x3B) ++ ++/* 0x3C reserved */ ++ ++/* 0x3D..0x3E SP */ ++ ++/* 0x3F SREG */ ++ ++/* Interrupt vectors */ ++ ++#define SIG_INTERRUPT0 _VECTOR(1) ++#define SIG_INTERRUPT1 _VECTOR(2) ++#define SIG_OVERFLOW1 _VECTOR(3) ++#define SIG_OVERFLOW0 _VECTOR(4) ++#define SIG_ADC _VECTOR(5) ++#define SIG_EEPROM_READY _VECTOR(6) ++ ++#define _VECTORS_SIZE 14 ++ ++/* Bit numbers */ ++ ++/* GIMSK */ ++#define INT1 7 ++#define INT0 6 ++ ++/* GIFR */ ++#define INTF1 7 ++#define INTF0 6 ++ ++/* GIPR */ ++#define IPIN1 3 ++#define IPIN0 2 ++ ++/* TIMSK */ ++#define TOIE1 2 ++#define TOIE0 0 ++ ++/* TIFR */ ++#define TOV1 2 ++#define TOV0 0 ++ ++/* MCUCR */ ++#define SE 6 ++#define SM 5 ++#define ISC1 2 ++#define ISC0 0 ++ ++/* TCCR0 */ ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* TCCR1 */ ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* PORTA */ ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++/* DDRA */ ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++/* EEPROM Control Register */ ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++/* Last memory addresses */ ++#define RAMSTART 0x60 ++#define RAMEND 0x15F ++#define XRAMEND RAMEND ++#define E2END 0x1FF ++#define FLASHEND 0x1FFF ++ ++#endif /* _AVR_IO8534_H_ */ +diff --git a/include/avr/io8535.h b/include/avr/io8535.h +index 884d02e..d05b54f 100644 +--- a/include/avr/io8535.h ++++ b/include/avr/io8535.h +@@ -1,584 +1,585 @@ +-/* Copyright (c) 2002, Marek Michalkiewicz +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: io8535.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* avr/io8535.h - definitions for AT90S8535 */ +- +-#ifndef _AVR_IO8535_H_ +-#define _AVR_IO8535_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "io8535.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* ADC Data register */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x04) +-#endif +-#define ADCW _SFR_IO16(0x04) +-#define ADCL _SFR_IO8(0x04) +-#define ADCH _SFR_IO8(0x05) +- +-/* ADC Control and Status Register */ +-#define ADCSR _SFR_IO8(0x06) +- +-/* ADC MUX */ +-#define ADMUX _SFR_IO8(0x07) +- +-/* Analog Comparator Control and Status Register */ +-#define ACSR _SFR_IO8(0x08) +- +-/* UART Baud Rate Register */ +-#define UBRR _SFR_IO8(0x09) +- +-/* UART Control Register */ +-#define UCR _SFR_IO8(0x0A) +- +-/* UART Status Register */ +-#define USR _SFR_IO8(0x0B) +- +-/* UART I/O Data Register */ +-#define UDR _SFR_IO8(0x0C) +- +-/* SPI Control Register */ +-#define SPCR _SFR_IO8(0x0D) +- +-/* SPI Status Register */ +-#define SPSR _SFR_IO8(0x0E) +- +-/* SPI I/O Data Register */ +-#define SPDR _SFR_IO8(0x0F) +- +-/* Input Pins, Port D */ +-#define PIND _SFR_IO8(0x10) +- +-/* Data Direction Register, Port D */ +-#define DDRD _SFR_IO8(0x11) +- +-/* Data Register, Port D */ +-#define PORTD _SFR_IO8(0x12) +- +-/* Input Pins, Port C */ +-#define PINC _SFR_IO8(0x13) +- +-/* Data Direction Register, Port C */ +-#define DDRC _SFR_IO8(0x14) +- +-/* Data Register, Port C */ +-#define PORTC _SFR_IO8(0x15) +- +-/* Input Pins, Port B */ +-#define PINB _SFR_IO8(0x16) +- +-/* Data Direction Register, Port B */ +-#define DDRB _SFR_IO8(0x17) +- +-/* Data Register, Port B */ +-#define PORTB _SFR_IO8(0x18) +- +-/* Input Pins, Port A */ +-#define PINA _SFR_IO8(0x19) +- +-/* Data Direction Register, Port A */ +-#define DDRA _SFR_IO8(0x1A) +- +-/* Data Register, Port A */ +-#define PORTA _SFR_IO8(0x1B) +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO16(0x1E) +-#define EEARL _SFR_IO8(0x1E) +-#define EEARH _SFR_IO8(0x1F) +- +-/* Watchdog Timer Control Register */ +-#define WDTCR _SFR_IO8(0x21) +- +-/* Asynchronous mode Status Register */ +-#define ASSR _SFR_IO8(0x22) +- +-/* Timer/Counter2 Output Compare Register */ +-#define OCR2 _SFR_IO8(0x23) +- +-/* Timer/Counter 2 */ +-#define TCNT2 _SFR_IO8(0x24) +- +-/* Timer/Counter 2 Control Register */ +-#define TCCR2 _SFR_IO8(0x25) +- +-/* T/C 1 Input Capture Register */ +-#define ICR1 _SFR_IO16(0x26) +-#define ICR1L _SFR_IO8(0x26) +-#define ICR1H _SFR_IO8(0x27) +- +-/* Timer/Counter1 Output Compare Register B */ +-#define OCR1B _SFR_IO16(0x28) +-#define OCR1BL _SFR_IO8(0x28) +-#define OCR1BH _SFR_IO8(0x29) +- +-/* Timer/Counter1 Output Compare Register A */ +-#define OCR1A _SFR_IO16(0x2A) +-#define OCR1AL _SFR_IO8(0x2A) +-#define OCR1AH _SFR_IO8(0x2B) +- +-/* Timer/Counter 1 */ +-#define TCNT1 _SFR_IO16(0x2C) +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1H _SFR_IO8(0x2D) +- +-/* Timer/Counter 1 Control and Status Register */ +-#define TCCR1B _SFR_IO8(0x2E) +- +-/* Timer/Counter 1 Control Register */ +-#define TCCR1A _SFR_IO8(0x2F) +- +-/* Timer/Counter 0 */ +-#define TCNT0 _SFR_IO8(0x32) +- +-/* Timer/Counter 0 Control Register */ +-#define TCCR0 _SFR_IO8(0x33) +- +-/* MCU general Status Register */ +-#define MCUSR _SFR_IO8(0x34) +- +-/* MCU general Control Register */ +-#define MCUCR _SFR_IO8(0x35) +- +-/* Timer/Counter Interrupt Flag register */ +-#define TIFR _SFR_IO8(0x38) +- +-/* Timer/Counter Interrupt MaSK register */ +-#define TIMSK _SFR_IO8(0x39) +- +-/* General Interrupt Flag Register */ +-#define GIFR _SFR_IO8(0x3A) +- +-/* General Interrupt MaSK register */ +-#define GIMSK _SFR_IO8(0x3B) +- +-/* 0x3D..0x3E SP */ +- +-/* 0x3F SREG */ +- +-/* Interrupt vectors */ +- +-/* External Interrupt 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt 1 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +-#define SIG_INTERRUPT1 _VECTOR(2) +- +-/* Timer/Counter2 Compare Match */ +-#define TIMER2_COMP_vect_num 3 +-#define TIMER2_COMP_vect _VECTOR(3) +-#define SIG_OUTPUT_COMPARE2 _VECTOR(3) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 4 +-#define TIMER2_OVF_vect _VECTOR(4) +-#define SIG_OVERFLOW2 _VECTOR(4) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 5 +-#define TIMER1_CAPT_vect _VECTOR(5) +-#define SIG_INPUT_CAPTURE1 _VECTOR(5) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 6 +-#define TIMER1_COMPA_vect _VECTOR(6) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(6) +- +-/* Timer/Counter1 Compare Match B */ +-#define TIMER1_COMPB_vect_num 7 +-#define TIMER1_COMPB_vect _VECTOR(7) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(7) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 8 +-#define TIMER1_OVF_vect _VECTOR(8) +-#define SIG_OVERFLOW1 _VECTOR(8) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 9 +-#define TIMER0_OVF_vect _VECTOR(9) +-#define SIG_OVERFLOW0 _VECTOR(9) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 10 +-#define SPI_STC_vect _VECTOR(10) +-#define SIG_SPI _VECTOR(10) +- +-/* UART, RX Complete */ +-#define UART_RX_vect_num 11 +-#define UART_RX_vect _VECTOR(11) +-#define SIG_UART_RECV _VECTOR(11) +- +-/* UART Data Register Empty */ +-#define UART_UDRE_vect_num 12 +-#define UART_UDRE_vect _VECTOR(12) +-#define SIG_UART_DATA _VECTOR(12) +- +-/* UART, TX Complete */ +-#define UART_TX_vect_num 13 +-#define UART_TX_vect _VECTOR(13) +-#define SIG_UART_TRANS _VECTOR(13) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 14 +-#define ADC_vect _VECTOR(14) +-#define SIG_ADC _VECTOR(14) +- +-/* EEPROM Ready */ +-#define EE_RDY_vect_num 15 +-#define EE_RDY_vect _VECTOR(15) +-#define SIG_EEPROM_READY _VECTOR(15) +- +-/* Analog Comparator */ +-#define ANA_COMP_vect_num 16 +-#define ANA_COMP_vect _VECTOR(16) +-#define SIG_COMPARATOR _VECTOR(16) +- +-#define _VECTORS_SIZE 34 +- +-/* +- The Register Bit names are represented by their bit number (0-7). +-*/ +- +-/* MCU general Status Register */ +-#define EXTRF 1 +-#define PORF 0 +- +-/* General Interrupt MaSK register */ +-#define INT1 7 +-#define INT0 6 +- +-/* General Interrupt Flag Register */ +-#define INTF1 7 +-#define INTF0 6 +- +-/* Timer/Counter Interrupt MaSK register */ +-#define OCIE2 7 +-#define TOIE2 6 +-#define TICIE1 5 +-#define OCIE1A 4 +-#define OCIE1B 3 +-#define TOIE1 2 +-#define TOIE0 0 +- +-/* Timer/Counter Interrupt Flag register */ +-#define OCF2 7 +-#define TOV2 6 +-#define ICF1 5 +-#define OCF1A 4 +-#define OCF1B 3 +-#define TOV1 2 +-#define TOV0 0 +- +-/* MCU general Control Register */ +-#define SE 6 +-#define SM1 5 +-#define SM0 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-/* Timer/Counter 0 Control Register */ +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* Timer/Counter 1 Control Register */ +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define PWM11 1 +-#define PWM10 0 +- +-/* Timer/Counter 1 Control and Status Register */ +-#define ICNC1 7 +-#define ICES1 6 +-#define CTC1 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* Timer/Counter 2 Control Register */ +-#define PWM2 6 +-#define COM21 5 +-#define COM20 4 +-#define CTC2 3 +-#define CS22 2 +-#define CS21 1 +-#define CS20 0 +- +-/* Asynchronous mode Status Register */ +-#define AS2 3 +-#define TCN2UB 2 +-#define OCR2UB 1 +-#define TCR2UB 0 +- +-/* Watchdog Timer Control Register */ +-#define WDTOE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* Data Register, Port A */ +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-/* Data Direction Register, Port A */ +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-/* Input Pins, Port A */ +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-/* Data Register, Port B */ +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* Data Direction Register, Port B */ +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* Input Pins, Port B */ +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* Data Register, Port C */ +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-/* Data Direction Register, Port C */ +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-/* Input Pins, Port C */ +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-/* Data Register, Port D */ +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* Data Direction Register, Port D */ +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-/* Input Pins, Port D */ +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-/* SPI Control Register */ +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +-/* SPI Status Register */ +-#define SPIF 7 +-#define WCOL 6 +- +-/* UART Status Register */ +-#define RXC 7 +-#define TXC 6 +-#define UDRE 5 +-#define FE 4 +-#define DOR 3 +- +-/* UART Control Register */ +-#define RXCIE 7 +-#define TXCIE 6 +-#define UDRIE 5 +-#define RXEN 4 +-#define TXEN 3 +-#define CHR9 2 +-#define RXB8 1 +-#define TXB8 0 +- +-/* Analog Comparator Control and Status Register */ +-#define ACD 7 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +- +-/* ADC MUX */ +-#define MUX2 2 +-#define MUX1 1 +-#define MUX0 0 +- +-/* ADC Control and Status Register */ +-#define ADEN 7 +-#define ADSC 6 +-#define ADFR 5 +-#define ADIF 4 +-#define ADIE 3 +-#define ADPS2 2 +-#define ADPS1 1 +-#define ADPS0 0 +- +-/* EEPROM Control Register */ +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-/* Constants */ +-#define RAMEND 0x25F /*Last On-Chip SRAM location*/ +-#define XRAMEND RAMEND +-#define E2END 0x1FF +-#define E2PAGESIZE 0 +-#define FLASHEND 0x1FFF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 1 +- +-/* Low Fuse Byte */ +-#define FUSE_SPIEN (unsigned char)~_BV(1) /* Serial Program Downloading Enabled */ +-#define FUSE_FSTRT (unsigned char)~_BV(2) /* Short Start-up time selected */ +-#define LFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x93 +-#define SIGNATURE_2 0x03 +- +- +-#endif /* _AVR_IO8535_H_ */ ++/* Copyright (c) 2002, Marek Michalkiewicz ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: io8535.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* avr/io8535.h - definitions for AT90S8535 */ ++ ++#ifndef _AVR_IO8535_H_ ++#define _AVR_IO8535_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "io8535.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* ADC Data register */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCW _SFR_IO16(0x04) ++#define ADCL _SFR_IO8(0x04) ++#define ADCH _SFR_IO8(0x05) ++ ++/* ADC Control and Status Register */ ++#define ADCSR _SFR_IO8(0x06) ++ ++/* ADC MUX */ ++#define ADMUX _SFR_IO8(0x07) ++ ++/* Analog Comparator Control and Status Register */ ++#define ACSR _SFR_IO8(0x08) ++ ++/* UART Baud Rate Register */ ++#define UBRR _SFR_IO8(0x09) ++ ++/* UART Control Register */ ++#define UCR _SFR_IO8(0x0A) ++ ++/* UART Status Register */ ++#define USR _SFR_IO8(0x0B) ++ ++/* UART I/O Data Register */ ++#define UDR _SFR_IO8(0x0C) ++ ++/* SPI Control Register */ ++#define SPCR _SFR_IO8(0x0D) ++ ++/* SPI Status Register */ ++#define SPSR _SFR_IO8(0x0E) ++ ++/* SPI I/O Data Register */ ++#define SPDR _SFR_IO8(0x0F) ++ ++/* Input Pins, Port D */ ++#define PIND _SFR_IO8(0x10) ++ ++/* Data Direction Register, Port D */ ++#define DDRD _SFR_IO8(0x11) ++ ++/* Data Register, Port D */ ++#define PORTD _SFR_IO8(0x12) ++ ++/* Input Pins, Port C */ ++#define PINC _SFR_IO8(0x13) ++ ++/* Data Direction Register, Port C */ ++#define DDRC _SFR_IO8(0x14) ++ ++/* Data Register, Port C */ ++#define PORTC _SFR_IO8(0x15) ++ ++/* Input Pins, Port B */ ++#define PINB _SFR_IO8(0x16) ++ ++/* Data Direction Register, Port B */ ++#define DDRB _SFR_IO8(0x17) ++ ++/* Data Register, Port B */ ++#define PORTB _SFR_IO8(0x18) ++ ++/* Input Pins, Port A */ ++#define PINA _SFR_IO8(0x19) ++ ++/* Data Direction Register, Port A */ ++#define DDRA _SFR_IO8(0x1A) ++ ++/* Data Register, Port A */ ++#define PORTA _SFR_IO8(0x1B) ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO16(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++#define EEARH _SFR_IO8(0x1F) ++ ++/* Watchdog Timer Control Register */ ++#define WDTCR _SFR_IO8(0x21) ++ ++/* Asynchronous mode Status Register */ ++#define ASSR _SFR_IO8(0x22) ++ ++/* Timer/Counter2 Output Compare Register */ ++#define OCR2 _SFR_IO8(0x23) ++ ++/* Timer/Counter 2 */ ++#define TCNT2 _SFR_IO8(0x24) ++ ++/* Timer/Counter 2 Control Register */ ++#define TCCR2 _SFR_IO8(0x25) ++ ++/* T/C 1 Input Capture Register */ ++#define ICR1 _SFR_IO16(0x26) ++#define ICR1L _SFR_IO8(0x26) ++#define ICR1H _SFR_IO8(0x27) ++ ++/* Timer/Counter1 Output Compare Register B */ ++#define OCR1B _SFR_IO16(0x28) ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BH _SFR_IO8(0x29) ++ ++/* Timer/Counter1 Output Compare Register A */ ++#define OCR1A _SFR_IO16(0x2A) ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++ ++/* Timer/Counter 1 */ ++#define TCNT1 _SFR_IO16(0x2C) ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++ ++/* Timer/Counter 1 Control and Status Register */ ++#define TCCR1B _SFR_IO8(0x2E) ++ ++/* Timer/Counter 1 Control Register */ ++#define TCCR1A _SFR_IO8(0x2F) ++ ++/* Timer/Counter 0 */ ++#define TCNT0 _SFR_IO8(0x32) ++ ++/* Timer/Counter 0 Control Register */ ++#define TCCR0 _SFR_IO8(0x33) ++ ++/* MCU general Status Register */ ++#define MCUSR _SFR_IO8(0x34) ++ ++/* MCU general Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++ ++/* Timer/Counter Interrupt Flag register */ ++#define TIFR _SFR_IO8(0x38) ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define TIMSK _SFR_IO8(0x39) ++ ++/* General Interrupt Flag Register */ ++#define GIFR _SFR_IO8(0x3A) ++ ++/* General Interrupt MaSK register */ ++#define GIMSK _SFR_IO8(0x3B) ++ ++/* 0x3D..0x3E SP */ ++ ++/* 0x3F SREG */ ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt 1 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++#define SIG_INTERRUPT1 _VECTOR(2) ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect_num 3 ++#define TIMER2_COMP_vect _VECTOR(3) ++#define SIG_OUTPUT_COMPARE2 _VECTOR(3) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 4 ++#define TIMER2_OVF_vect _VECTOR(4) ++#define SIG_OVERFLOW2 _VECTOR(4) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 5 ++#define TIMER1_CAPT_vect _VECTOR(5) ++#define SIG_INPUT_CAPTURE1 _VECTOR(5) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 6 ++#define TIMER1_COMPA_vect _VECTOR(6) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(6) ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect_num 7 ++#define TIMER1_COMPB_vect _VECTOR(7) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(7) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 8 ++#define TIMER1_OVF_vect _VECTOR(8) ++#define SIG_OVERFLOW1 _VECTOR(8) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 9 ++#define TIMER0_OVF_vect _VECTOR(9) ++#define SIG_OVERFLOW0 _VECTOR(9) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 10 ++#define SPI_STC_vect _VECTOR(10) ++#define SIG_SPI _VECTOR(10) ++ ++/* UART, RX Complete */ ++#define UART_RX_vect_num 11 ++#define UART_RX_vect _VECTOR(11) ++#define SIG_UART_RECV _VECTOR(11) ++ ++/* UART Data Register Empty */ ++#define UART_UDRE_vect_num 12 ++#define UART_UDRE_vect _VECTOR(12) ++#define SIG_UART_DATA _VECTOR(12) ++ ++/* UART, TX Complete */ ++#define UART_TX_vect_num 13 ++#define UART_TX_vect _VECTOR(13) ++#define SIG_UART_TRANS _VECTOR(13) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 14 ++#define ADC_vect _VECTOR(14) ++#define SIG_ADC _VECTOR(14) ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect_num 15 ++#define EE_RDY_vect _VECTOR(15) ++#define SIG_EEPROM_READY _VECTOR(15) ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect_num 16 ++#define ANA_COMP_vect _VECTOR(16) ++#define SIG_COMPARATOR _VECTOR(16) ++ ++#define _VECTORS_SIZE 34 ++ ++/* ++ The Register Bit names are represented by their bit number (0-7). ++*/ ++ ++/* MCU general Status Register */ ++#define EXTRF 1 ++#define PORF 0 ++ ++/* General Interrupt MaSK register */ ++#define INT1 7 ++#define INT0 6 ++ ++/* General Interrupt Flag Register */ ++#define INTF1 7 ++#define INTF0 6 ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define OCIE2 7 ++#define TOIE2 6 ++#define TICIE1 5 ++#define OCIE1A 4 ++#define OCIE1B 3 ++#define TOIE1 2 ++#define TOIE0 0 ++ ++/* Timer/Counter Interrupt Flag register */ ++#define OCF2 7 ++#define TOV2 6 ++#define ICF1 5 ++#define OCF1A 4 ++#define OCF1B 3 ++#define TOV1 2 ++#define TOV0 0 ++ ++/* MCU general Control Register */ ++#define SE 6 ++#define SM1 5 ++#define SM0 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* Timer/Counter 0 Control Register */ ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* Timer/Counter 1 Control Register */ ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define PWM11 1 ++#define PWM10 0 ++ ++/* Timer/Counter 1 Control and Status Register */ ++#define ICNC1 7 ++#define ICES1 6 ++#define CTC1 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* Timer/Counter 2 Control Register */ ++#define PWM2 6 ++#define COM21 5 ++#define COM20 4 ++#define CTC2 3 ++#define CS22 2 ++#define CS21 1 ++#define CS20 0 ++ ++/* Asynchronous mode Status Register */ ++#define AS2 3 ++#define TCN2UB 2 ++#define OCR2UB 1 ++#define TCR2UB 0 ++ ++/* Watchdog Timer Control Register */ ++#define WDTOE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* Data Register, Port A */ ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++/* Data Direction Register, Port A */ ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++/* Input Pins, Port A */ ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++/* Data Register, Port B */ ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* Data Direction Register, Port B */ ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* Input Pins, Port B */ ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* Data Register, Port C */ ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++/* Data Direction Register, Port C */ ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++/* Input Pins, Port C */ ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++/* Data Register, Port D */ ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* Data Direction Register, Port D */ ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++/* Input Pins, Port D */ ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++/* SPI Control Register */ ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++/* SPI Status Register */ ++#define SPIF 7 ++#define WCOL 6 ++ ++/* UART Status Register */ ++#define RXC 7 ++#define TXC 6 ++#define UDRE 5 ++#define FE 4 ++#define DOR 3 ++ ++/* UART Control Register */ ++#define RXCIE 7 ++#define TXCIE 6 ++#define UDRIE 5 ++#define RXEN 4 ++#define TXEN 3 ++#define CHR9 2 ++#define RXB8 1 ++#define TXB8 0 ++ ++/* Analog Comparator Control and Status Register */ ++#define ACD 7 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++/* ADC MUX */ ++#define MUX2 2 ++#define MUX1 1 ++#define MUX0 0 ++ ++/* ADC Control and Status Register */ ++#define ADEN 7 ++#define ADSC 6 ++#define ADFR 5 ++#define ADIF 4 ++#define ADIE 3 ++#define ADPS2 2 ++#define ADPS1 1 ++#define ADPS0 0 ++ ++/* EEPROM Control Register */ ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++/* Constants */ ++#define RAMSTART 0x60 ++#define RAMEND 0x25F /*Last On-Chip SRAM location*/ ++#define XRAMEND RAMEND ++#define E2END 0x1FF ++#define E2PAGESIZE 0 ++#define FLASHEND 0x1FFF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Low Fuse Byte */ ++#define FUSE_SPIEN (unsigned char)~_BV(1) /* Serial Program Downloading Enabled */ ++#define FUSE_FSTRT (unsigned char)~_BV(2) /* Short Start-up time selected */ ++#define LFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x03 ++ ++ ++#endif /* _AVR_IO8535_H_ */ +diff --git a/include/avr/io86r401.h b/include/avr/io86r401.h +index 8758317..238aff5 100644 +--- a/include/avr/io86r401.h ++++ b/include/avr/io86r401.h +@@ -1,310 +1,311 @@ +-/* Copyright (c) 2002, Colin O'Flynn +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* avr/io86r401.h - definitions for AT86RF401 */ +- +-#ifndef _AVR_IO86RF401_H_ +-#define _AVR_IO86RF401_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "io86r401.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-#include +- +-/* Status REGister */ +-#define SREG _SFR_IO8(0x3F) +- +-/* Stack Pointer */ +-#define SP _SFR_IO16(0x3D) +-#define SPH _SFR_IO8(0x3E) +-#define SPL _SFR_IO8(0x3D) +- +-/*Battery low configeration register */ +-#define BL_CONFIG _SFR_IO8(0x35) +- +-/*Button detect register*/ +-#define B_DET _SFR_IO8(0x34) +- +-/*AVR Configeration register*/ +-#define AVR_CONFIG _SFR_IO8(0x33) +- +-/* I/O registers */ +- +-/*Data in register */ +-#define IO_DATIN _SFR_IO8(0x32) +- +-/*Data out register */ +-#define IO_DATOUT _SFR_IO8(0x31) +- +-/*IO Enable register */ +-#define IO_ENAB _SFR_IO8(0x30) +- +-/* Watchdog Timer Control Register */ +-#define WDTCR _SFR_IO8(0x22) +- +-/* Bit Timer Control Register */ +-#define BTCR _SFR_IO8(0x21) +- +-#define BTCNT _SFR_IO8(0x20) +- +-/* +-NOTE: EEPROM name's changed to have D in front on them, per datasheet, but +-you may want to remove the leading D. +-*/ +-/* EEPROM Control Register */ +- +-/* EEPROM Address Register */ +-#define DEEAR _SFR_IO8(0x1E) +-#define DEEARL _SFR_IO8(0x1E) +- +-/* EEPROM Data Register */ +-#define DEEDR _SFR_IO8(0x1D) +-/* EEPROM Control Register */ +-#define DEECR _SFR_IO8(0x1C) +- +-/* Lock Detector Configuration Register 2 */ +-#define LOCKDET2 _SFR_IO8(0x17) +- +-/* VCO Tuning Register*/ +-#define VCOTUNE _SFR_IO8(0x16) +- +-/* Power Attenuation Control Register */ +-#define PWR_ATTEN _SFR_IO8(0x14) +- +-/* Transmitter Control Register */ +-#define TX_CNTL _SFR_IO8(0x12) +- +-/* Lock Detector Configuration Register 1 */ +-#define LOCKDET1 _SFR_IO8(0x10) +- +- +-/* Interrupt vectors */ +- +-/* Transmission Done, Bit Timer Flag 2 Interrupt */ +-#define TXDONE_vect_num 1 +-#define TXDONE_vect _VECTOR(1) +-#define SIG_TXDONE _VECTOR(1) +- +-/* Transmit Buffer Empty, Bit Itmer Flag 0 Interrupt */ +-#define TXEMPTY_vect_num 2 +-#define TXEMPTY_vect _VECTOR(2) +-#define SIG_TXBE _VECTOR(2) +- +-#define _VECTORS_SIZE 12 +- +-/* +- * The Register Bit names are represented by their bit number (0-7). +- */ +- +-/* Lock Detector Configuration Register 1 - LOCKDET1 */ +-#define UPOK 4 +-#define ENKO 3 +-#define BOD 2 +-#define CS1 1 +-#define CS0 0 +- +-/* Transmit Control Register - TX_CNTL */ +-#define TXE 5 +-#define TXK 4 +-#define LOC 2 +- +-/* Power Attenuation Control Register - PWR_ATTEN */ +-#define PCC2 5 +-#define PCC1 4 +-#define PCC0 3 +-#define PCF2 2 +-#define PCF1 1 +-#define PCF0 0 +- +-/* VCO Tuning Register 6 - VCOTUNE --NOTE: [] removed from names*/ +-#define VCOVDET1 7 +-#define VCOVDET0 6 +-#define VCOTUNE4 4 +-#define VCOTUNE3 3 +-#define VCOTUNE2 2 +-#define VCOTUNE1 1 +-#define VCOTUNE0 0 +- +-/* Lock Detector Configuration Register 2 - LOCKDET2 --NOTE: [] removed from names*/ +-#define EUD 7 +-#define LAT 6 +-#define ULC2 5 +-#define ULC1 4 +-#define ULC0 3 +-#define LC2 2 +-#define LC1 1 +-#define LC0 0 +- +-/* Data EEPROM Control Register - DEECR */ +-#define BSY 3 +-#define EEU 2 +-#define EEL 1 +-#define EER 0 +- +-/* Data EEPROM Data Register - DEEDR */ +-#define ED7 7 +-#define ED6 6 +-#define ED5 5 +-#define ED4 4 +-#define ED3 3 +-#define ED2 2 +-#define ED1 1 +-#define ED0 0 +- +-/* Data EEPROM Address Register - DEEAR */ +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define BA2 2 /* B is not a typo! */ +-#define BA1 1 +-#define BA0 0 +- +-/* Bit Timer Count Register - BTCNT */ +-#define C7 7 +-#define C6 6 +-#define C5 5 +-#define C4 4 +-#define C3 3 +-#define C2 2 +-#define C1 1 +-#define C0 0 +- +-/* Bit Timer Control Register - BTCR */ +-#define C9 7 +-#define C8 6 +-#define M1 5 +-#define M0 4 +-#define IE 3 +-#define F2 2 +-#define DATA 1 +-#define F0 0 +- +-/* Watchdog Timer Control Register - WDTCR */ +-#define WDTOE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* I/O Enable Register - IO_ENAB */ +-#define BOHYST 6 +-#define IOE5 5 +-#define IOE4 4 +-#define IOE3 3 +-#define IOE2 2 +-#define IOE1 1 +-#define IOE0 0 +- +-/* Note: No PORTB or whatever, this is the equivalent. */ +-/* I/O Data Out Register - IO_DATOUT */ +-#define IOO5 5 +-#define IOO4 4 +-#define IOO3 3 +-#define IOO2 2 +-#define IOO1 1 +-#define IOO0 0 +- +-/* Note: No PINB or whatever, this is the equivalent. */ +-/* I/O Data In Register - IO_DATIN */ +-#define IOI5 5 +-#define IOI4 4 +-#define IOI3 3 +-#define IOI2 2 +-#define IOI1 1 +-#define IOI0 0 +- +-/* AVR Configuration Register - AVR_CONFIG */ +-#define ACS1 6 +-#define ACS0 5 +-#define TM 4 +-#define BD 3 +-#define BLI 2 +-#define SLEEP 1 +-#define BBM 0 +- +-/* Button Detect Register - B_DET */ +-#define BD5 5 +-#define BD4 4 +-#define BD3 3 +-#define BD2 2 +-#define BD1 1 +-#define BD0 0 +- +-/* Battery Low Configuration Register - BL_CONFIG */ +-#define BL 7 +-#define BLV 6 +-#define BL5 5 +-#define BL4 4 +-#define BL3 3 +-#define BL2 2 +-#define BL1 1 +-#define BL0 0 +- +-/* Pointer definition */ +-#define XL r26 +-#define XH r27 +-#define YL r28 +-#define YH r29 +-#define ZL r30 +-#define ZH r31 +- +-/* Constants */ +-#define RAMEND 0xDF +-#define XRAMEND RAMEND +-#define E2END 0x7F +-#define E2PAGESIZE 0 +-#define FLASHEND 0x07FF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 0 +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x91 +-#define SIGNATURE_2 0x81 +- +- +-#endif /* _AVR_IO86RF401_H_ */ ++/* Copyright (c) 2002, Colin O'Flynn ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* avr/io86r401.h - definitions for AT86RF401 */ ++ ++#ifndef _AVR_IO86RF401_H_ ++#define _AVR_IO86RF401_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "io86r401.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#include ++ ++/* Status REGister */ ++#define SREG _SFR_IO8(0x3F) ++ ++/* Stack Pointer */ ++#define SP _SFR_IO16(0x3D) ++#define SPH _SFR_IO8(0x3E) ++#define SPL _SFR_IO8(0x3D) ++ ++/*Battery low configeration register */ ++#define BL_CONFIG _SFR_IO8(0x35) ++ ++/*Button detect register*/ ++#define B_DET _SFR_IO8(0x34) ++ ++/*AVR Configeration register*/ ++#define AVR_CONFIG _SFR_IO8(0x33) ++ ++/* I/O registers */ ++ ++/*Data in register */ ++#define IO_DATIN _SFR_IO8(0x32) ++ ++/*Data out register */ ++#define IO_DATOUT _SFR_IO8(0x31) ++ ++/*IO Enable register */ ++#define IO_ENAB _SFR_IO8(0x30) ++ ++/* Watchdog Timer Control Register */ ++#define WDTCR _SFR_IO8(0x22) ++ ++/* Bit Timer Control Register */ ++#define BTCR _SFR_IO8(0x21) ++ ++#define BTCNT _SFR_IO8(0x20) ++ ++/* ++NOTE: EEPROM name's changed to have D in front on them, per datasheet, but ++you may want to remove the leading D. ++*/ ++/* EEPROM Control Register */ ++ ++/* EEPROM Address Register */ ++#define DEEAR _SFR_IO8(0x1E) ++#define DEEARL _SFR_IO8(0x1E) ++ ++/* EEPROM Data Register */ ++#define DEEDR _SFR_IO8(0x1D) ++/* EEPROM Control Register */ ++#define DEECR _SFR_IO8(0x1C) ++ ++/* Lock Detector Configuration Register 2 */ ++#define LOCKDET2 _SFR_IO8(0x17) ++ ++/* VCO Tuning Register*/ ++#define VCOTUNE _SFR_IO8(0x16) ++ ++/* Power Attenuation Control Register */ ++#define PWR_ATTEN _SFR_IO8(0x14) ++ ++/* Transmitter Control Register */ ++#define TX_CNTL _SFR_IO8(0x12) ++ ++/* Lock Detector Configuration Register 1 */ ++#define LOCKDET1 _SFR_IO8(0x10) ++ ++ ++/* Interrupt vectors */ ++ ++/* Transmission Done, Bit Timer Flag 2 Interrupt */ ++#define TXDONE_vect_num 1 ++#define TXDONE_vect _VECTOR(1) ++#define SIG_TXDONE _VECTOR(1) ++ ++/* Transmit Buffer Empty, Bit Itmer Flag 0 Interrupt */ ++#define TXEMPTY_vect_num 2 ++#define TXEMPTY_vect _VECTOR(2) ++#define SIG_TXBE _VECTOR(2) ++ ++#define _VECTORS_SIZE 12 ++ ++/* ++ * The Register Bit names are represented by their bit number (0-7). ++ */ ++ ++/* Lock Detector Configuration Register 1 - LOCKDET1 */ ++#define UPOK 4 ++#define ENKO 3 ++#define BOD 2 ++#define CS1 1 ++#define CS0 0 ++ ++/* Transmit Control Register - TX_CNTL */ ++#define TXE 5 ++#define TXK 4 ++#define LOC 2 ++ ++/* Power Attenuation Control Register - PWR_ATTEN */ ++#define PCC2 5 ++#define PCC1 4 ++#define PCC0 3 ++#define PCF2 2 ++#define PCF1 1 ++#define PCF0 0 ++ ++/* VCO Tuning Register 6 - VCOTUNE --NOTE: [] removed from names*/ ++#define VCOVDET1 7 ++#define VCOVDET0 6 ++#define VCOTUNE4 4 ++#define VCOTUNE3 3 ++#define VCOTUNE2 2 ++#define VCOTUNE1 1 ++#define VCOTUNE0 0 ++ ++/* Lock Detector Configuration Register 2 - LOCKDET2 --NOTE: [] removed from names*/ ++#define EUD 7 ++#define LAT 6 ++#define ULC2 5 ++#define ULC1 4 ++#define ULC0 3 ++#define LC2 2 ++#define LC1 1 ++#define LC0 0 ++ ++/* Data EEPROM Control Register - DEECR */ ++#define BSY 3 ++#define EEU 2 ++#define EEL 1 ++#define EER 0 ++ ++/* Data EEPROM Data Register - DEEDR */ ++#define ED7 7 ++#define ED6 6 ++#define ED5 5 ++#define ED4 4 ++#define ED3 3 ++#define ED2 2 ++#define ED1 1 ++#define ED0 0 ++ ++/* Data EEPROM Address Register - DEEAR */ ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define BA2 2 /* B is not a typo! */ ++#define BA1 1 ++#define BA0 0 ++ ++/* Bit Timer Count Register - BTCNT */ ++#define C7 7 ++#define C6 6 ++#define C5 5 ++#define C4 4 ++#define C3 3 ++#define C2 2 ++#define C1 1 ++#define C0 0 ++ ++/* Bit Timer Control Register - BTCR */ ++#define C9 7 ++#define C8 6 ++#define M1 5 ++#define M0 4 ++#define IE 3 ++#define F2 2 ++#define DATA 1 ++#define F0 0 ++ ++/* Watchdog Timer Control Register - WDTCR */ ++#define WDTOE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* I/O Enable Register - IO_ENAB */ ++#define BOHYST 6 ++#define IOE5 5 ++#define IOE4 4 ++#define IOE3 3 ++#define IOE2 2 ++#define IOE1 1 ++#define IOE0 0 ++ ++/* Note: No PORTB or whatever, this is the equivalent. */ ++/* I/O Data Out Register - IO_DATOUT */ ++#define IOO5 5 ++#define IOO4 4 ++#define IOO3 3 ++#define IOO2 2 ++#define IOO1 1 ++#define IOO0 0 ++ ++/* Note: No PINB or whatever, this is the equivalent. */ ++/* I/O Data In Register - IO_DATIN */ ++#define IOI5 5 ++#define IOI4 4 ++#define IOI3 3 ++#define IOI2 2 ++#define IOI1 1 ++#define IOI0 0 ++ ++/* AVR Configuration Register - AVR_CONFIG */ ++#define ACS1 6 ++#define ACS0 5 ++#define TM 4 ++#define BD 3 ++#define BLI 2 ++#define SLEEP 1 ++#define BBM 0 ++ ++/* Button Detect Register - B_DET */ ++#define BD5 5 ++#define BD4 4 ++#define BD3 3 ++#define BD2 2 ++#define BD1 1 ++#define BD0 0 ++ ++/* Battery Low Configuration Register - BL_CONFIG */ ++#define BL 7 ++#define BLV 6 ++#define BL5 5 ++#define BL4 4 ++#define BL3 3 ++#define BL2 2 ++#define BL1 1 ++#define BL0 0 ++ ++/* Pointer definition */ ++#define XL r26 ++#define XH r27 ++#define YL r28 ++#define YH r29 ++#define ZL r30 ++#define ZH r31 ++ ++/* Constants */ ++#define RAMSTART 0x60 ++#define RAMEND 0xDF ++#define XRAMEND RAMEND ++#define E2END 0x7F ++#define E2PAGESIZE 0 ++#define FLASHEND 0x07FF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 0 ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x91 ++#define SIGNATURE_2 0x81 ++ ++ ++#endif /* _AVR_IO86RF401_H_ */ +diff --git a/include/avr/io90pwm1.h b/include/avr/io90pwm1.h +index f1d2d08..844cd7d 100644 +--- a/include/avr/io90pwm1.h ++++ b/include/avr/io90pwm1.h +@@ -1,1143 +1,1144 @@ +-/* Copyright (c) 2005, Andrey Pashchenko +- Copyright (c) 2007, Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: io90pwm1.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* avr/iopwm1.h - definitions for AT90PWM1 device */ +- +-#ifndef _AVR_IOPWM1_H_ +-#define _AVR_IOPWM1_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iopwm1.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* Reserved [0x00..0x02] */ +- +-/* Port B Input Pins Address */ +-#define PINB _SFR_IO8(0x03) +-/* PINB */ +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* Port B Data Direction Register */ +-#define DDRB _SFR_IO8(0x04) +-/* DDRB */ +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* Port B Data Register */ +-#define PORTB _SFR_IO8(0x05) +-/* PORTB */ +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* Reserved [0x06..0x08] */ +- +-/* Port D Input Pins Address */ +-#define PIND _SFR_IO8(0x09) +-/* PIND */ +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-/* Port D Data Direction Register */ +-#define DDRD _SFR_IO8(0x0A) +-/* DDRD */ +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-/* Port D Data Register */ +-#define PORTD _SFR_IO8(0x0B) +-/* PORTD */ +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* Port E Input Pins Address */ +-#define PINE _SFR_IO8(0x0C) +-/* PINE */ +-#define PINE2 2 +-#define PINE1 1 +-#define PINE0 0 +- +-/* Port E Data Direction Register */ +-#define DDRE _SFR_IO8(0x0D) +-/* DDRE */ +-#define DDE2 2 +-#define DDE1 1 +-#define DDE0 0 +- +-/* Port E Data Register */ +-#define PORTE _SFR_IO8(0x0E) +-/* PORTE */ +-#define PE2 2 +-#define PE1 1 +-#define PE0 0 +- +-/* Reserved [0x0F..0x14] */ +- +-/* Timer/Counter 0 Interrupt Flag Register */ +-#define TIFR0 _SFR_IO8(0x15) +-/* TIFR0 */ +-#define OCF0B 2 /* Output Compare Flag 0B */ +-#define OCF0A 1 /* Output Compare Flag 0A */ +-#define TOV0 0 /* Overflow Flag */ +- +-/* Timer/Counter1 Interrupt Flag Register */ +-#define TIFR1 _SFR_IO8(0x16) +-/* TIFR1 */ +-#define ICF1 5 /* Input Capture Flag 1 */ +-#define OCF1B 2 /* Output Compare Flag 1B*/ +-#define OCF1A 1 /* Output Compare Flag 1A*/ +-#define TOV1 0 /* Overflow Flag */ +- +-/* Reserved [0x17..0x18] */ +- +-/* General Purpose I/O Register 1 */ +-#define GPIOR1 _SFR_IO8(0x19) +-/* GPIOR1 */ +-#define GPIOR17 7 +-#define GPIOR16 6 +-#define GPIOR15 5 +-#define GPIOR14 4 +-#define GPIOR13 3 +-#define GPIOR12 2 +-#define GPIOR11 1 +-#define GPIOR10 0 +- +-/* General Purpose I/O Register 2 */ +-#define GPIOR2 _SFR_IO8(0x1A) +-/* GPIOR2 */ +-#define GPIOR27 7 +-#define GPIOR26 6 +-#define GPIOR25 5 +-#define GPIOR24 4 +-#define GPIOR23 3 +-#define GPIOR22 2 +-#define GPIOR21 1 +-#define GPIOR20 0 +- +-/* General Purpose I/O Register 3 */ +-#define GPIOR3 _SFR_IO8(0x1B) +-/* GPIOR3 */ +-#define GPIOR37 7 +-#define GPIOR36 6 +-#define GPIOR35 5 +-#define GPIOR34 4 +-#define GPIOR33 3 +-#define GPIOR32 2 +-#define GPIOR31 1 +-#define GPIOR30 0 +- +-/* External Interrupt Flag Register */ +-#define EIFR _SFR_IO8(0x1C) +-/* EIFR */ +-#define INTF3 3 +-#define INTF2 2 +-#define INTF1 1 +-#define INTF0 0 +- +-/* External Interrupt Mask Register */ +-#define EIMSK _SFR_IO8(0x1D) +-/* EIMSK */ +-#define INT3 3 /* External Interrupt Request 3 Enable */ +-#define INT2 2 /* External Interrupt Request 2 Enable */ +-#define INT1 1 /* External Interrupt Request 1 Enable */ +-#define INT0 0 /* External Interrupt Request 0 Enable */ +- +-/* General Purpose I/O Register 0 */ +-#define GPIOR0 _SFR_IO8(0x1E) +-/* GPIOR0 */ +-#define GPIOR07 7 +-#define GPIOR06 6 +-#define GPIOR05 5 +-#define GPIOR04 4 +-#define GPIOR03 3 +-#define GPIOR02 2 +-#define GPIOR01 1 +-#define GPIOR00 0 +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1F) +-/* EECR */ +-#define EERIE 3 /* EEPROM Ready Interrupt Enable */ +-#define EEMWE 2 /* EEPROM Master Write Enable */ +-#define EEWE 1 /* EEPROM Write Enable */ +-#define EERE 0 /* EEPROM Read Enable */ +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x20) +-/* EEDR */ +-#define EEDR7 7 +-#define EEDR6 6 +-#define EEDR5 5 +-#define EEDR4 4 +-#define EEDR3 3 +-#define EEDR2 2 +-#define EEDR1 1 +-#define EEDR0 0 +- +-/* The EEPROM Address Registers */ +-#define EEAR _SFR_IO16(0x21) +-#define EEARL _SFR_IO8(0x21) +-#define EEARH _SFR_IO8(0x22) +-/* EEARH */ +-#define EEAR11 3 +-#define EEAR10 2 +-#define EEAR9 1 +-#define EEAR8 0 +-/* EEARL */ +-#define EEAR7 7 +-#define EEAR6 6 +-#define EEAR5 5 +-#define EEAR4 4 +-#define EEAR3 3 +-#define EEAR2 2 +-#define EEAR1 1 +-#define EEAR0 0 +- +-/* 6-char sequence denoting where to find the EEPROM registers in memory space. +- Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM +- subroutines. +- First two letters: EECR address. +- Second two letters: EEDR address. +- Last two letters: EEAR address. */ +-#define __EEPROM_REG_LOCATIONS__ 1F2021 +- +-/* General Timer/Counter Control Register */ +-#define GTCCR _SFR_IO8(0x23) +-/* GTCCR */ +-#define TSM 7 /* Timer/Counter Synchronization Mode */ +-#define ICPSEL1 6 /* Timer1 Input Capture Selection Bit */ +-#define PSRSYNC 0 +- +-/* Timer/Counter Control Register A */ +-#define TCCR0A _SFR_IO8(0x24) +-/* TCCR0A */ +-#define COM0A1 7 /* Compare Output Mode, Phase Correct PWM Mode */ +-#define COM0A0 6 /* Compare Output Mode, Phase Correct PWM Mode */ +-#define COM0B1 5 /* Compare Output Mode, Fast PWm */ +-#define COM0B0 4 /* Compare Output Mode, Fast PWm */ +-#define WGM01 1 /* Waveform Generation Mode */ +-#define WGM00 0 /* Waveform Generation Mode */ +- +-/* Timer/Counter Control Register B */ +-#define TCCR0B _SFR_IO8(0x25) +-/* TCCR0B */ +-#define FOC0A 7 /* Force Output Compare A */ +-#define FOC0B 6 /* Force Output Compare B */ +-#define WGM02 3 /* Waveform Generation Mode */ +-#define CS02 2 /* Clock Select */ +-#define CS01 1 /* Clock Select */ +-#define CS00 0 /* Clock Select */ +- +-/* Timer/Counter0 Register */ +-#define TCNT0 _SFR_IO8(0x26) +-/* TCNT0 */ +-#define TCNT07 7 +-#define TCNT06 6 +-#define TCNT05 5 +-#define TCNT04 4 +-#define TCNT03 3 +-#define TCNT02 2 +-#define TCNT01 1 +-#define TCNT00 0 +- +-/* Timer/Counter0 Output Compare Register A */ +-#define OCR0A _SFR_IO8(0x27) +-/* OCR0A */ +-#define OCR0A7 7 +-#define OCR0A6 6 +-#define OCR0A5 5 +-#define OCR0A4 4 +-#define OCR0A3 3 +-#define OCR0A2 2 +-#define OCR0A1 1 +-#define OCR0A0 0 +- +-/* Timer/Counter0 Output Compare Register B */ +-#define OCR0B _SFR_IO8(0x28) +-/* OCR0B */ +-#define OCR0B7 7 +-#define OCR0B6 6 +-#define OCR0B5 5 +-#define OCR0B4 4 +-#define OCR0B3 3 +-#define OCR0B2 2 +-#define OCR0B1 1 +-#define OCR0B0 0 +- +-/* PLL Control and Status Register */ +-#define PLLCSR _SFR_IO8(0x29) +-/* PLLCSR */ +-#define PLLF 2 +-#define PLLE 1 /* PLL Enable */ +-#define PLOCK 0 /* PLL Lock Detector */ +- +-/* Reserved [0x2A..0x2B] */ +- +-/* SPI Control Register */ +-#define SPCR _SFR_IO8(0x2C) +-/* SPCR */ +-#define SPIE 7 /* SPI Interrupt Enable */ +-#define SPE 6 /* SPI Enable */ +-#define DORD 5 /* Data Order */ +-#define MSTR 4 /* Master/Slave Select */ +-#define CPOL 3 /* Clock polarity */ +-#define CPHA 2 /* Clock Phase */ +-#define SPR1 1 /* SPI Clock Rate Select 1 */ +-#define SPR0 0 /* SPI Clock Rate Select 0 */ +- +-/* SPI Status Register */ +-#define SPSR _SFR_IO8(0x2D) +-/* SPSR */ +-#define SPIF 7 /* SPI Interrupt Flag */ +-#define WCOL 6 /* Write Collision Flag */ +-#define SPI2X 0 /* Double SPI Speed Bit */ +- +-/* SPI Data Register */ +-#define SPDR _SFR_IO8(0x2E) +-/* SPDR */ +-#define SPD7 7 +-#define SPD6 6 +-#define SPD5 5 +-#define SPD4 4 +-#define SPD3 3 +-#define SPD2 2 +-#define SPD1 1 +-#define SPD0 0 +- +-/* Reserved [0x2F] */ +- +-/* Analog Comparator Status Register */ +-#define ACSR _SFR_IO8(0x30) +-/* ACSR */ +-#define ACCKDIV 7 /* Analog Comparator Clock Divider */ +-#define AC2IF 6 /* Analog Comparator 2 Interrupt Flag Bit */ +-#define AC0IF 4 /* Analog Comparator 0 Interrupt Flag Bit */ +-#define AC2O 2 /* Analog Comparator 2 Output Bit */ +-#define AC0O 0 /* Analog Comparator 0 Output Bit */ +- +-/* Monitor Data Register */ +-#define MONDR _SFR_IO8(0x31) +- +-/* Monitor Stop Mode Control Register */ +-#define MSMCR _SFR_IO8(0x32) +- +-/* Sleep Mode Control Register */ +-#define SMCR _SFR_IO8(0x33) +-/* SMCR */ +-#define SM2 3 /* Sleep Mode Select bit2 */ +-#define SM1 2 /* Sleep Mode Select bit1 */ +-#define SM0 1 /* Sleep Mode Select bit0 */ +-#define SE 0 /* Sleep Enable */ +- +-/* MCU Status Register */ +-#define MCUSR _SFR_IO8(0x34) +-/* MCUSR */ +-#define WDRF 3 /* Watchdog Reset Flag */ +-#define BORF 2 /* Brown-out Reset Flag */ +-#define EXTRF 1 /* External Reset Flag */ +-#define PORF 0 /* Power-on reset flag */ +- +-/* MCU Control Register */ +-#define MCUCR _SFR_IO8(0x35) +-/* MCUCR */ +-#define SPIPS 7 /* SPI Pin Select */ +-#define PUD 4 /* Pull-up disable */ +-#define IVSEL 1 /* Interrupt Vector Select */ +-#define IVCE 0 /* Interrupt Vector Change Enable */ +- +-/* Reserved [0x36] */ +- +-/* Store Program Memory Control Register */ +-#define SPMCSR _SFR_IO8(0x37) +-/* SPMCSR */ +-#define SPMIE 7 /* SPM Interrupt Enable */ +-#define RWWSB 6 /* Read While Write Section Busy */ +-#define RWWSRE 4 /* Read While Write section read enable */ +-#define BLBSET 3 /* Boot Lock Bit Set */ +-#define PGWRT 2 /* Page Write */ +-#define PGERS 1 /* Page Erase */ +-#define SPMEN 0 /* Store Program Memory Enable */ +- +-/* Reserved [0x38..0x3C] */ +- +-/* 0x3D..0x3E SP [defined in ] */ +-/* 0x3F SREG [defined in ] */ +- +-/* Watchdog Timer Control Register */ +-#define WDTCSR _SFR_MEM8(0x60) +-/* WDTCSR */ +-#define WDIF 7 /* Watchdog Timeout Interrupt Flag */ +-#define WDIE 6 /* Watchdog Timeout Interrupt Enable */ +-#define WDP3 5 /* Watchdog Timer Prescaler bit3 */ +-#define WDCE 4 /* Watchdog Change Enable */ +-#define WDE 3 /* Watchdog Enable */ +-#define WDP2 2 /* Watchdog Timer Prescaler bit2 */ +-#define WDP1 1 /* Watchdog Timer Prescaler bit1 */ +-#define WDP0 0 /* Watchdog Timer Prescaler bit0 */ +- +-/* Clock Prescaler Register */ +-#define CLKPR _SFR_MEM8(0x61) +-/* CLKPR */ +-#define CLKPCE 7 /* Clock Prescaler Change Enable */ +-#define CLKPS3 3 /* Clock Prescaler Select bit3 */ +-#define CLKPS2 2 /* Clock Prescaler Select bit2 */ +-#define CLKPS1 1 /* Clock Prescaler Select bit1 */ +-#define CLKPS0 0 /* Clock Prescaler Select bit0 */ +- +-/* Reserved [0x62..0x63] */ +- +-/* Power Reduction Register */ +-#define PRR _SFR_MEM8(0x64) +-/* PRR */ +-#define PRPSC2 7 /* Power Reduction PSC2 */ +-#define PRPSC1 6 /* Power Reduction PSC1 */ +-#define PRPSC0 5 /* Power Reduction PSC0 */ +-#define PRTIM1 4 /* Power Reduction Timer/Counter1 */ +-#define PRTIM0 3 /* Power Reduction Timer/Counter0 */ +-#define PRSPI 2 /* Power Reduction Serial Peripheral Interface */ +-#define PRADC 0 /* Power Reduction ADC */ +- +-/* Reserved [0x65] */ +- +-/* Oscillator Calibration Value */ +-#define OSCCAL _SFR_MEM8(0x66) +-/* OSCCAL */ +-#define CAL6 6 +-#define CAL5 5 +-#define CAL4 4 +-#define CAL3 3 +-#define CAL2 2 +-#define CAL1 1 +-#define CAL0 0 +- +-/* Reserved [0x67..0x68] */ +- +-/* External Interrupt Control Register A */ +-#define EICRA _SFR_MEM8(0x69) +-/* EICRA */ +-#define ISC31 7 +-#define ISC30 6 +-#define ISC21 5 +-#define ISC20 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-/* Reserved [0x6A..0x6D] */ +- +-/* Timer/Counter0 Interrupt Mask Register */ +-#define TIMSK0 _SFR_MEM8(0x6E) +-/* TIMSK0 */ +-#define OCIE0B 2 /* Output Compare Match B Interrupt Enable */ +-#define OCIE0A 1 /* Output Compare Match A Interrupt Enable */ +-#define TOIE0 0 /* Overflow Interrupt Enable */ +- +-/* Timer/Counter1 Interrupt Mask Register */ +-#define TIMSK1 _SFR_MEM8(0x6F) +-/* TIMSK1 */ +-#define ICIE1 5 /* Input Capture Interrupt Enable */ +-#define OCIE1B 2 /* Output Compare Match B Interrupt Enable */ +-#define OCIE1A 1 /* Output Compare Match A Interrupt Enable */ +-#define TOIE1 0 /* Overflow Interrupt Enable */ +- +-/* Reserved [0x70..0x75] */ +- +-/* Amplifier 0 Control and Status register */ +-#define AMP0CSR _SFR_MEM8(0x76) +-#define AMP0EN 7 +-#define AMP0IS 6 +-#define AMP0G1 5 +-#define AMP0G0 4 +-#define AMP0TS1 1 +-#define AMP0TS0 0 +- +-/* Reserved [0x77] */ +- +-/* ADC Result Data Register */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +-#define ADCL _SFR_MEM8(0x78) +-#define ADCH _SFR_MEM8(0x79) +- +-/* ADC Control and Status Register A */ +-#define ADCSRA _SFR_MEM8(0x7A) +-/* ADCSRA */ +-#define ADEN 7 /* ADC Enable */ +-#define ADSC 6 /* ADC Start Conversion */ +-#define ADATE 5 /* ADC Auto Trigger Enable */ +-#define ADIF 4 /* ADC Interrupt Flag */ +-#define ADIE 3 /* ADC Interrupt Enable */ +-#define ADPS2 2 /* ADC Prescaler Select bit2 */ +-#define ADPS1 1 /* ADC Prescaler Select bit1 */ +-#define ADPS0 0 /* ADC Prescaler Select bit0 */ +- +-/* ADC Control and Status Register B */ +-#define ADCSRB _SFR_MEM8(0x7B) +-/* ADCSRB */ +-#define ADTS3 3 /* ADC Auto Trigger Source 2 */ +-#define ADTS2 2 /* ADC Auto Trigger Source 2 */ +-#define ADTS1 1 /* ADC Auto Trigger Source 1 */ +-#define ADTS0 0 /* ADC Auto Trigger Source 0 */ +- +-/* ADC multiplexer Selection Register */ +-#define ADMUX _SFR_MEM8(0x7C) +-/* ADMUX */ +-#define REFS1 7 /* Reference Selection bit1 */ +-#define REFS0 6 /* Reference Selection bit0 */ +-#define ADLAR 5 /* Left Adjust Result */ +-#define MUX3 3 /* Analog Channel and Gain Selection bit3 */ +-#define MUX2 2 /* Analog Channel and Gain Selection bit2 */ +-#define MUX1 1 /* Analog Channel and Gain Selection bit1 */ +-#define MUX0 0 /* Analog Channel and Gain Selection bit0 */ +- +-/* Reserved [0x7D] */ +- +-/* Digital Input Disable Register 0 */ +-#define DIDR0 _SFR_MEM8(0x7E) +-/* DIDR0 */ +-#define ADC7D 7 /* ADC7 Digital input Disable */ +-#define ADC6D 6 /* ADC6 Digital input Disable */ +-#define ADC5D 5 /* ADC5 Digital input Disable */ +-#define ADC4D 4 /* ADC4 Digital input Disable */ +-#define ADC3D 3 /* ADC3 Digital input Disable */ +-#define ADC2D 2 /* ADC2 Digital input Disable */ +-#define ADC1D 1 /* ADC1 Digital input Disable */ +-#define ADC0D 0 /* ADC0 Digital input Disable */ +- +-/* Digital Input Disable Register 1 */ +-#define DIDR1 _SFR_MEM8(0x7F) +-/* DIDR1 */ +-#define ACMP0D 5 +-#define AMP0PD 4 +-#define AMP0ND 3 +-#define ADC10D 2 /* ADC10 Digital input Disable */ +-#define ADC9D 1 /* ADC9 Digital input Disable */ +-#define ADC8D 0 /* ADC8 Digital input Disable */ +- +-/* Timer/Counter1 Control Register A */ +-#define TCCR1A _SFR_MEM8(0x80) +-/* TCCR1A */ +-#define COM1A1 7 /* Comparet Ouput Mode 1A, bit 1 */ +-#define COM1A0 6 /* Comparet Ouput Mode 1A, bit 0 */ +-#define COM1B1 5 /* Compare Output Mode 1B, bit 1 */ +-#define COM1B0 4 /* Compare Output Mode 1B, bit 0 */ +-#define WGM11 1 /* Waveform Generation Mode */ +-#define WGM10 0 /* Waveform Generation Mode */ +- +-/* Timer/Counter1 Control Register B */ +-#define TCCR1B _SFR_MEM8(0x81) +-/* TCCR1B */ +-#define ICNC1 7 /* Input Capture 1 Noise Canceler */ +-#define ICES1 6 /* Input Capture 1 Edge Select */ +-#define WGM13 4 /* Waveform Generation Mode */ +-#define WGM12 3 /* Waveform Generation Mode */ +-#define CS12 2 /* Prescaler source of Timer/Counter 1 */ +-#define CS11 1 /* Prescaler source of Timer/Counter 1 */ +-#define CS10 0 /* Prescaler source of Timer/Counter 1 */ +- +-/* Timer/Counter1 Control Register C */ +-#define TCCR1C _SFR_MEM8(0x82) +-/* TCCR1C */ +-#define FOC1A 7 /* Force Output Compare for Channel A */ +-#define FOC1B 6 /* Force Output Compare for Channel B */ +- +-/* Reserved [0x83] */ +- +-/* Timer/Counter1 */ +-#define TCNT1 _SFR_MEM16(0x84) +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1H _SFR_MEM8(0x85) +-/* TCNT1H */ +-#define TCNT115 7 +-#define TCNT114 6 +-#define TCNT113 5 +-#define TCNT112 4 +-#define TCNT111 3 +-#define TCNT110 2 +-#define TCNT19 1 +-#define TCNT18 0 +-/* TCNT1L */ +-#define TCNT17 7 +-#define TCNT16 6 +-#define TCNT15 5 +-#define TCNT14 4 +-#define TCNT13 3 +-#define TCNT12 2 +-#define TCNT11 1 +-#define TCNT10 0 +- +-/* Input Capture Register 1 */ +-#define ICR1 _SFR_MEM16(0x86) +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1H _SFR_MEM8(0x87) +-/* ICR1H */ +-#define ICR115 7 +-#define ICR114 6 +-#define ICR113 5 +-#define ICR112 4 +-#define ICR111 3 +-#define ICR110 2 +-#define ICR19 1 +-#define ICR18 0 +-/* ICR1L */ +-#define ICR17 7 +-#define ICR16 6 +-#define ICR15 5 +-#define ICR14 4 +-#define ICR13 3 +-#define ICR12 2 +-#define ICR11 1 +-#define ICR10 0 +- +-/* Output Compare Register 1 A */ +-#define OCR1A _SFR_MEM16(0x88) +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AH _SFR_MEM8(0x89) +-/* OCR1AH */ +-#define OCR1A15 7 +-#define OCR1A14 6 +-#define OCR1A13 5 +-#define OCR1A12 4 +-#define OCR1A11 3 +-#define OCR1A10 2 +-#define OCR1A9 1 +-#define OCR1A8 0 +-/* OCR1AL */ +-#define OCR1A7 7 +-#define OCR1A6 6 +-#define OCR1A5 5 +-#define OCR1A4 4 +-#define OCR1A3 3 +-#define OCR1A2 2 +-#define OCR1A1 1 +-#define OCR1A0 0 +- +-/* Output Compare Register 1 B */ +-#define OCR1B _SFR_MEM16(0x8A) +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BH _SFR_MEM8(0x8B) +-/* OCR1BH */ +-#define OCR1B15 7 +-#define OCR1B14 6 +-#define OCR1B13 5 +-#define OCR1B12 4 +-#define OCR1B11 3 +-#define OCR1B10 2 +-#define OCR1B9 1 +-#define OCR1B8 0 +-/* OCR1BL */ +-#define OCR1B7 7 +-#define OCR1B6 6 +-#define OCR1B5 5 +-#define OCR1B4 4 +-#define OCR1B3 3 +-#define OCR1B2 2 +-#define OCR1B1 1 +-#define OCR1B0 0 +- +-/* Reserved [0x8C..0x9F] */ +- +-/* PSC0 Interrupt Flag Register */ +-#define PIFR0 _SFR_MEM8(0xA0) +-/* PIFR0 */ +-#define PSEI0 5 /* PSC0 Synchro Error Interrupt */ +-#define PEV0B 4 /* PSC0 External Event B Interrupt */ +-#define PEV0A 3 /* PSC0 External Event A Interrupt */ +-#define PRN01 2 /* PSC0 Ramp Number bit1 */ +-#define PRN00 1 /* PSC0 Ramp Number bit0 */ +-#define PEOP0 0 /* End Of PSC0 Interrupt */ +- +-/* PSC0 Interrupt Mask Register */ +-#define PIM0 _SFR_MEM8(0xA1) +-/* PIM0 */ +-#define PSEIE0 5 /* PSC0 Synchro Error Interrupt Enable */ +-#define PEVE0B 4 /* PSC0 External Event B Interrupt Enable */ +-#define PEVE0A 3 /* PSC0 External Event A Interrupt Enable */ +-#define PEOPE0 0 /* PSC0 End Of Cycle Interrupt Enable */ +- +-/* Reserved [0xA2..0xA3] */ +- +-/* PSC2 Interrupt Flag Register */ +-#define PIFR2 _SFR_MEM8(0xA4) +-/* PIFR2 */ +-#define PSEI2 5 /* PSC2 Synchro Error Interrupt */ +-#define PEV2B 4 /* PSC2 External Event B Interrupt */ +-#define PEV2A 3 /* PSC2 External Event A Interrupt */ +-#define PRN21 2 /* PSC2 Ramp Number bit1 */ +-#define PRN20 1 /* PSC2 Ramp Number bit0 */ +-#define PEOP2 0 /* End Of PSC2 Interrupt */ +- +-/* PSC2 Interrupt Mask Register */ +-#define PIM2 _SFR_MEM8(0xA5) +-/* PIM2 */ +-#define PSEIE2 5 /* PSC2 Synchro Error Interrupt Enable */ +-#define PEVE2B 4 /* PSC2 External Event B Interrupt Enable */ +-#define PEVE2A 3 /* PSC2 External Event A Interrupt Enable */ +-#define PEOPE2 0 /* PSC2 End Of Cycle Interrupt Enable */ +- +-/* Reserved [0xA6..0xAC] */ +- +-/* Analog Comparator 0 Control Register */ +-#define AC0CON _SFR_MEM8(0xAD) +-/* AC0CON */ +-#define AC0EN 7 /* Analog Comparator 0 Enable Bit */ +-#define AC0IE 6 /* Analog Comparator 0 Interrupt Enable bit */ +-#define AC0IS1 5 /* Analog Comparator 0 Interrupt Select bit1 */ +-#define AC0IS0 4 /* Analog Comparator 0 Interrupt Select bit0 */ +-#define AC0M2 2 /* Analog Comparator 0 Multiplexer register bit2 */ +-#define AC0M1 1 /* Analog Comparator 0 Multiplexer register bit1 */ +-#define AC0M0 0 /* Analog Comparator 0 Multiplexer register bit0 */ +- +-/* Reserved [0xB0..0xAE] */ +- +-/* Analog Comparator 2 Control Register */ +-#define AC2CON _SFR_MEM8(0xAF) +-/* AC2CON */ +-#define AC2EN 7 /* Analog Comparator 2 Enable Bit */ +-#define AC2IE 6 /* Analog Comparator 2 Interrupt Enable bit */ +-#define AC2IS1 5 /* Analog Comparator 2 Interrupt Select bit1 */ +-#define AC2IS0 4 /* Analog Comparator 2 Interrupt Select bit0 */ +-#define AC2M2 2 /* Analog Comparator 2 Multiplexer register bit2 */ +-#define AC2M1 1 /* Analog Comparator 2 Multiplexer register bit1 */ +-#define AC2M0 0 /* Analog Comparator 2 Multiplexer register bit0 */ +- +-/* Reserved [0xB0..0xCF] */ +- +-/* PSC 0 Synchro and Output Configuration */ +-#define PSOC0 _SFR_MEM8(0xD0) +-/* PSOC0 */ +-#define PSYNC01 5 /* Synchronization Out for ADC Selection bit1 */ +-#define PSYNC00 4 /* Synchronization Out for ADC Selection bit0 */ +-#define POEN0B 2 /* PSC 0 OUT Part B Output Enable */ +-#define POEN0A 0 /* PSC 0 OUT Part A Output Enable */ +- +-/* Reserved [0xD1] */ +- +-/* Output Compare SA Registers */ +-#define OCR0SA _SFR_MEM16(0xD2) +-#define OCR0SAL _SFR_MEM8(0xD2) +-#define OCR0SAH _SFR_MEM8(0xD3) +- +-/* Output Compare RA Registers */ +-#define OCR0RA _SFR_MEM16(0xD4) +-#define OCR0RAL _SFR_MEM8(0xD4) +-#define OCR0RAH _SFR_MEM8(0xD5) +- +-/* Output Compare SB Registers */ +-#define OCR0SB _SFR_MEM16(0xD6) +-#define OCR0SBL _SFR_MEM8(0xD6) +-#define OCR0SBH _SFR_MEM8(0xD7) +- +-/* Output Compare RB Registers */ +-#define OCR0RB _SFR_MEM16(0xD8) +-#define OCR0RBL _SFR_MEM8(0xD8) +-#define OCR0RBH _SFR_MEM8(0xD9) +- +-/* PSC 0 Configuration Register */ +-#define PCNF0 _SFR_MEM8(0xDA) +-/* PCNF0 */ +-#define PFIFTY0 7 /* PSC 0 Fifty */ +-#define PALOCK0 6 /* PSC 0 Autolock */ +-#define PLOCK0 5 /* PSC 0 Lock */ +-#define PMODE01 4 /* PSC 0 Mode bit1 */ +-#define PMODE00 3 /* PSC 0 Mode bit0 */ +-#define POP0 2 /* PSC 0 Output Polarity */ +-#define PCLKSEL0 1 /* PSC 0 Input Clock Select */ +- +-/* PSC 0 Control Register */ +-#define PCTL0 _SFR_MEM8(0xDB) +-/* PCTL0 */ +-#define PPRE01 7 /* PSC 0 Prescaler Select bit1 */ +-#define PPRE00 6 /* PSC 0 Prescaler Select bit0 */ +-#define PBFM0 5 /* Balance Flank Width Modulation */ +-#define PAOC0B 4 /* PSC 0 Asynchronous Output Control B */ +-#define PAOC0A 3 /* PSC 0 Asynchronous Output Control A */ +-#define PARUN0 2 /* PSC 0 Autorun */ +-#define PCCYC0 1 /* PSC 0 Complete Cycle */ +-#define PRUN0 0 /* PSC 0 Run */ +- +-/* PSC 0 Input A Control Register */ +-#define PFRC0A _SFR_MEM8(0xDC) +-/* PFRC0A */ +-#define PCAE0A 7 /* PSC 0 Capture Enable Input Part A */ +-#define PISEL0A 6 /* PSC 0 Input Select for Part A */ +-#define PELEV0A 5 /* PSC 0 Edge Level Selector of Input Part A */ +-#define PFLTE0A 4 /* PSC 0 Filter Enable on Input Part A */ +-#define PRFM0A3 3 /* PSC 0 Fault Mode bit3 */ +-#define PRFM0A2 2 /* PSC 0 Fault Mode bit2 */ +-#define PRFM0A1 1 /* PSC 0 Fault Mode bit1 */ +-#define PRFM0A0 0 /* PSC 0 Fault Mode bit0 */ +- +-/* PSC 0 Input B Control Register */ +-#define PFRC0B _SFR_MEM8(0xDD) +-/* PFRC0B */ +-#define PCAE0B 7 /* PSC 0 Capture Enable Input Part B */ +-#define PISEL0B 6 /* PSC 0 Input Select for Part B */ +-#define PELEV0B 5 /* PSC 0 Edge Level Selector of Input Part B */ +-#define PFLTE0B 4 /* PSC 0 Filter Enable on Input Part B */ +-#define PRFM0B3 3 /* PSC 0 Fault Mode bit3 */ +-#define PRFM0B2 2 /* PSC 0 Fault Mode bit2 */ +-#define PRFM0B1 1 /* PSC 0 Fault Mode bit1 */ +-#define PRFM0B0 0 /* PSC 0 Fault Mode bit0 */ +- +-/* PSC 0 Input Capture Registers */ +-#define PICR0 _SFR_MEM16(0xDE) +- +-#define PICR0L _SFR_MEM8(0xDE) +- +-#define PICR0H _SFR_MEM8(0xDF) +-#define PCST0 7 /* PSC Capture Software Trig bit */ +- +-/* Reserved [0xE0..0xEF] */ +- +-/* PSC 2 Synchro and Output Configuration */ +-#define PSOC2 _SFR_MEM8(0xF0) +-/* PSOC2 */ +-#define POS23 7 /* PSCOUT23 Selection */ +-#define POS22 6 /* PSCOUT22 Selection */ +-#define PSYNC21 5 /* Synchronization Out for ADC Selection bit1 */ +-#define PSYNC20 4 /* Synchronization Out for ADC Selection bit0 */ +-#define POEN2D 3 /* PSCOUT23 Output Enable */ +-#define POEN2B 2 /* PSC 2 OUT Part B Output Enable */ +-#define POEN2C 1 /* PSCOUT22 Output Enable */ +-#define POEN2A 0 /* PSC 2 OUT Part A Output Enable */ +- +-/* PSC 2 Output Matrix */ +-#define POM2 _SFR_MEM8(0xF1) +-/* POM2 */ +-#define POMV2B3 7 /* Output Matrix Output B Ramp 3 */ +-#define POMV2B2 6 /* Output Matrix Output B Ramp 2 */ +-#define POMV2B1 5 /* Output Matrix Output B Ramp 1 */ +-#define POMV2B0 4 /* Output Matrix Output B Ramp 0 */ +-#define POMV2A3 3 /* Output Matrix Output A Ramp 3 */ +-#define POMV2A2 2 /* Output Matrix Output A Ramp 2 */ +-#define POMV2A1 1 /* Output Matrix Output A Ramp 1 */ +-#define POMV2A0 0 /* Output Matrix Output A Ramp 0 */ +- +-/* Output Compare SA Registers */ +-#define OCR2SA _SFR_MEM16(0xF2) +-#define OCR2SAL _SFR_MEM8(0xF2) +-#define OCR2SAH _SFR_MEM8(0xF3) +- +-/* Output Compare RA Registers */ +-#define OCR2RA _SFR_MEM16(0xF4) +-#define OCR2RAL _SFR_MEM8(0xF4) +-#define OCR2RAH _SFR_MEM8(0xF5) +- +-/* Output Compare SB Registers */ +-#define OCR2SB _SFR_MEM16(0xF6) +-#define OCR2SBL _SFR_MEM8(0xF6) +-#define OCR2SBH _SFR_MEM8(0xF7) +- +-/* Output Compare RB Registers */ +-#define OCR2RB _SFR_MEM16(0xF8) +-#define OCR2RBL _SFR_MEM8(0xF8) +-#define OCR2RBH _SFR_MEM8(0xF9) +- +-/* PSC 2 Configuration Register */ +-#define PCNF2 _SFR_MEM8(0xFA) +-/* PCNF2 */ +-#define PFIFTY2 7 /* PSC 2 Fifty */ +-#define PALOCK2 6 /* PSC 2 Autolock */ +-#define PLOCK2 5 /* PSC 2 Lock */ +-#define PMODE21 4 /* PSC 2 Mode bit1 */ +-#define PMODE20 3 /* PSC 2 Mode bit0 */ +-#define POP2 2 /* PSC 2 Output Polarity */ +-#define PCLKSEL2 1 /* PSC 2 Input Clock Select */ +-#define POME2 0 /* PSC 2 Output Matrix Enable */ +- +-/* PSC 2 Control Register */ +-#define PCTL2 _SFR_MEM8(0xFB) +-/* PCTL2 */ +-#define PPRE21 7 /* PSC 2 Prescaler Select bit1 */ +-#define PPRE20 6 /* PSC 2 Prescaler Select bit0 */ +-#define PBFM2 5 /* Balance Flank Width Modulation */ +-#define PAOC2B 4 /* PSC 2 Asynchronous Output Control B */ +-#define PAOC2A 3 /* PSC 2 Asynchronous Output Control A */ +-#define PARUN2 2 /* PSC 2 Autorun */ +-#define PCCYC2 1 /* PSC 2 Complete Cycle */ +-#define PRUN2 0 /* PSC 2 Run */ +- +-/* PSC 2 Input A Control Register */ +-#define PFRC2A _SFR_MEM8(0xFC) +-/* PFRC2A */ +-#define PCAE2A 7 /* PSC 2 Capture Enable Input Part A */ +-#define PISEL2A 6 /* PSC 2 Input Select for Part A */ +-#define PELEV2A 5 /* PSC 2 Edge Level Selector of Input Part A */ +-#define PFLTE2A 4 /* PSC 2 Filter Enable on Input Part A */ +-#define PRFM2A3 3 /* PSC 2 Fault Mode bit3 */ +-#define PRFM2A2 2 /* PSC 2 Fault Mode bit2 */ +-#define PRFM2A1 1 /* PSC 2 Fault Mode bit1 */ +-#define PRFM2A0 0 /* PSC 2 Fault Mode bit0 */ +- +-/* PSC 2 Input B Control Register */ +-#define PFRC2B _SFR_MEM8(0xFD) +-/* PFRC2B */ +-#define PCAE2B 7 /* PSC 2 Capture Enable Input Part B */ +-#define PISEL2B 6 /* PSC 2 Input Select for Part B */ +-#define PELEV2B 5 /* PSC 2 Edge Level Selector of Input Part B */ +-#define PFLTE2B 4 /* PSC 2 Filter Enable on Input Part B */ +-#define PRFM2B3 3 /* PSC 2 Fault Mode bit3 */ +-#define PRFM2B2 2 /* PSC 2 Fault Mode bit2 */ +-#define PRFM2B1 1 /* PSC 2 Fault Mode bit1 */ +-#define PRFM2B0 0 /* PSC 2 Fault Mode bit0 */ +- +-/* PSC 2 Input Capture Registers */ +-#define PICR2 _SFR_MEM16(0xFE) +- +-#define PICR2L _SFR_MEM8(0xFE) +- +-#define PICR2H _SFR_MEM8(0xFF) +-#define PCST2 7 /* PSC Capture Software Trig bit */ +- /* not implemented on AT90PWM2/AT90PWM3 */ +- +- +-/* Interrupt vectors */ +-/* PSC2 Capture Event */ +-#define PSC2_CAPT_vect_num 1 +-#define PSC2_CAPT_vect _VECTOR(1) +-#define SIG_PSC2_CAPTURE _VECTOR(1) +- +-/* PSC2 End Cycle */ +-#define PSC2_EC_vect_num 2 +-#define PSC2_EC_vect _VECTOR(2) +-#define SIG_PSC2_END_CYCLE _VECTOR(2) +- +-/* PSC0 Capture Event */ +-#define PSC0_CAPT_vect_num 5 +-#define PSC0_CAPT_vect _VECTOR(5) +-#define SIG_PSC0_CAPTURE _VECTOR(5) +- +-/* PSC0 End Cycle */ +-#define PSC0_EC_vect_num 6 +-#define PSC0_EC_vect _VECTOR(6) +-#define SIG_PSC0_END_CYCLE _VECTOR(6) +- +-/* Analog Comparator 0 */ +-#define ANALOG_COMP_0_vect_num 7 +-#define ANALOG_COMP_0_vect _VECTOR(7) +-#define SIG_COMPARATOR0 _VECTOR(7) +- +-/* Analog Comparator 2 */ +-#define ANALOG_COMP_2_vect_num 9 +-#define ANALOG_COMP_2_vect _VECTOR(9) +-#define SIG_COMPARATOR2 _VECTOR(9) +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 10 +-#define INT0_vect _VECTOR(10) +-#define SIG_INTERRUPT0 _VECTOR(10) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 11 +-#define TIMER1_CAPT_vect _VECTOR(11) +-#define SIG_INPUT_CAPTURE1 _VECTOR(11) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 12 +-#define TIMER1_COMPA_vect _VECTOR(12) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(12) +-#define SIG_OUTPUT_COMPARE1_A _VECTOR(12) +- +-/* Timer/Counter Compare Match B */ +-#define TIMER1_COMPB_vect_num 13 +-#define TIMER1_COMPB_vect _VECTOR(13) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(13) +-#define SIG_OUTPUT_COMPARE1_B _VECTOR(13) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 15 +-#define TIMER1_OVF_vect _VECTOR(15) +-#define SIG_OVERFLOW1 _VECTOR(15) +- +-/* Timer/Counter0 Compare Match A */ +-#define TIMER0_COMP_A_vect_num 16 +-#define TIMER0_COMP_A_vect _VECTOR(16) +-#define SIG_OUTPUT_COMPARE0A _VECTOR(16) +-#define SIG_OUTPUT_COMPARE0_A _VECTOR(16) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 17 +-#define TIMER0_OVF_vect _VECTOR(17) +-#define SIG_OVERFLOW0 _VECTOR(17) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 18 +-#define ADC_vect _VECTOR(18) +-#define SIG_ADC _VECTOR(18) +- +-/* External Interrupt Request 1 */ +-#define INT1_vect_num 19 +-#define INT1_vect _VECTOR(19) +-#define SIG_INTERRUPT1 _VECTOR(19) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 20 +-#define SPI_STC_vect _VECTOR(20) +-#define SIG_SPI _VECTOR(20) +- +-/* External Interrupt Request 2 */ +-#define INT2_vect_num 24 +-#define INT2_vect _VECTOR(24) +-#define SIG_INTERRUPT2 _VECTOR(24) +- +-/* Watchdog Timeout Interrupt */ +-#define WDT_vect_num 25 +-#define WDT_vect _VECTOR(25) +-#define SIG_WDT _VECTOR(25) +-#define SIG_WATCHDOG_TIMEOUT _VECTOR(25) +- +-/* EEPROM Ready */ +-#define EE_READY_vect_num 26 +-#define EE_READY_vect _VECTOR(26) +-#define SIG_EEPROM_READY _VECTOR(26) +- +-/* Timer Counter 0 Compare Match B */ +-#define TIMER0_COMPB_vect_num 27 +-#define TIMER0_COMPB_vect _VECTOR(27) +-#define SIG_OUTPUT_COMPARE0B _VECTOR(27) +-#define SIG_OUTPUT_COMPARE0_B _VECTOR(27) +- +-/* External Interrupt Request 3 */ +-#define INT3_vect_num 28 +-#define INT3_vect _VECTOR(28) +-#define SIG_INTERRUPT3 _VECTOR(28) +- +-/* Store Program Memory Read */ +-#define SPM_READY_vect_num 31 +-#define SPM_READY_vect _VECTOR(31) +-#define SIG_SPM_READY _VECTOR(31) +- +-#define _VECTORS_SIZE 64 +- +-/* Constants */ +-#define SPM_PAGESIZE 64 +- +-#define RAMEND 0x02FF +-#define XRAMEND RAMEND +-#define E2END 0x01FF +-#define FLASHEND 0x0FFF +- +- +-/* Fuse Information */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Diasble */ +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_PSCRV (unsigned char)~_BV(4) +-#define FUSE_PSC0RB (unsigned char)~_BV(5) +-#define FUSE_PSC2RB (unsigned char)~_BV(7) +-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-#endif /* _AVR_IOPWM1_H_ */ ++/* Copyright (c) 2005, Andrey Pashchenko ++ Copyright (c) 2007, Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: io90pwm1.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* avr/iopwm1.h - definitions for AT90PWM1 device */ ++ ++#ifndef _AVR_IOPWM1_H_ ++#define _AVR_IOPWM1_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iopwm1.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* Reserved [0x00..0x02] */ ++ ++/* Port B Input Pins Address */ ++#define PINB _SFR_IO8(0x03) ++/* PINB */ ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* Port B Data Direction Register */ ++#define DDRB _SFR_IO8(0x04) ++/* DDRB */ ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* Port B Data Register */ ++#define PORTB _SFR_IO8(0x05) ++/* PORTB */ ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* Reserved [0x06..0x08] */ ++ ++/* Port D Input Pins Address */ ++#define PIND _SFR_IO8(0x09) ++/* PIND */ ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++/* Port D Data Direction Register */ ++#define DDRD _SFR_IO8(0x0A) ++/* DDRD */ ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++/* Port D Data Register */ ++#define PORTD _SFR_IO8(0x0B) ++/* PORTD */ ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* Port E Input Pins Address */ ++#define PINE _SFR_IO8(0x0C) ++/* PINE */ ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++/* Port E Data Direction Register */ ++#define DDRE _SFR_IO8(0x0D) ++/* DDRE */ ++#define DDE2 2 ++#define DDE1 1 ++#define DDE0 0 ++ ++/* Port E Data Register */ ++#define PORTE _SFR_IO8(0x0E) ++/* PORTE */ ++#define PE2 2 ++#define PE1 1 ++#define PE0 0 ++ ++/* Reserved [0x0F..0x14] */ ++ ++/* Timer/Counter 0 Interrupt Flag Register */ ++#define TIFR0 _SFR_IO8(0x15) ++/* TIFR0 */ ++#define OCF0B 2 /* Output Compare Flag 0B */ ++#define OCF0A 1 /* Output Compare Flag 0A */ ++#define TOV0 0 /* Overflow Flag */ ++ ++/* Timer/Counter1 Interrupt Flag Register */ ++#define TIFR1 _SFR_IO8(0x16) ++/* TIFR1 */ ++#define ICF1 5 /* Input Capture Flag 1 */ ++#define OCF1B 2 /* Output Compare Flag 1B*/ ++#define OCF1A 1 /* Output Compare Flag 1A*/ ++#define TOV1 0 /* Overflow Flag */ ++ ++/* Reserved [0x17..0x18] */ ++ ++/* General Purpose I/O Register 1 */ ++#define GPIOR1 _SFR_IO8(0x19) ++/* GPIOR1 */ ++#define GPIOR17 7 ++#define GPIOR16 6 ++#define GPIOR15 5 ++#define GPIOR14 4 ++#define GPIOR13 3 ++#define GPIOR12 2 ++#define GPIOR11 1 ++#define GPIOR10 0 ++ ++/* General Purpose I/O Register 2 */ ++#define GPIOR2 _SFR_IO8(0x1A) ++/* GPIOR2 */ ++#define GPIOR27 7 ++#define GPIOR26 6 ++#define GPIOR25 5 ++#define GPIOR24 4 ++#define GPIOR23 3 ++#define GPIOR22 2 ++#define GPIOR21 1 ++#define GPIOR20 0 ++ ++/* General Purpose I/O Register 3 */ ++#define GPIOR3 _SFR_IO8(0x1B) ++/* GPIOR3 */ ++#define GPIOR37 7 ++#define GPIOR36 6 ++#define GPIOR35 5 ++#define GPIOR34 4 ++#define GPIOR33 3 ++#define GPIOR32 2 ++#define GPIOR31 1 ++#define GPIOR30 0 ++ ++/* External Interrupt Flag Register */ ++#define EIFR _SFR_IO8(0x1C) ++/* EIFR */ ++#define INTF3 3 ++#define INTF2 2 ++#define INTF1 1 ++#define INTF0 0 ++ ++/* External Interrupt Mask Register */ ++#define EIMSK _SFR_IO8(0x1D) ++/* EIMSK */ ++#define INT3 3 /* External Interrupt Request 3 Enable */ ++#define INT2 2 /* External Interrupt Request 2 Enable */ ++#define INT1 1 /* External Interrupt Request 1 Enable */ ++#define INT0 0 /* External Interrupt Request 0 Enable */ ++ ++/* General Purpose I/O Register 0 */ ++#define GPIOR0 _SFR_IO8(0x1E) ++/* GPIOR0 */ ++#define GPIOR07 7 ++#define GPIOR06 6 ++#define GPIOR05 5 ++#define GPIOR04 4 ++#define GPIOR03 3 ++#define GPIOR02 2 ++#define GPIOR01 1 ++#define GPIOR00 0 ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1F) ++/* EECR */ ++#define EERIE 3 /* EEPROM Ready Interrupt Enable */ ++#define EEMWE 2 /* EEPROM Master Write Enable */ ++#define EEWE 1 /* EEPROM Write Enable */ ++#define EERE 0 /* EEPROM Read Enable */ ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x20) ++/* EEDR */ ++#define EEDR7 7 ++#define EEDR6 6 ++#define EEDR5 5 ++#define EEDR4 4 ++#define EEDR3 3 ++#define EEDR2 2 ++#define EEDR1 1 ++#define EEDR0 0 ++ ++/* The EEPROM Address Registers */ ++#define EEAR _SFR_IO16(0x21) ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++/* EEARH */ ++#define EEAR11 3 ++#define EEAR10 2 ++#define EEAR9 1 ++#define EEAR8 0 ++/* EEARL */ ++#define EEAR7 7 ++#define EEAR6 6 ++#define EEAR5 5 ++#define EEAR4 4 ++#define EEAR3 3 ++#define EEAR2 2 ++#define EEAR1 1 ++#define EEAR0 0 ++ ++/* 6-char sequence denoting where to find the EEPROM registers in memory space. ++ Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM ++ subroutines. ++ First two letters: EECR address. ++ Second two letters: EEDR address. ++ Last two letters: EEAR address. */ ++#define __EEPROM_REG_LOCATIONS__ 1F2021 ++ ++/* General Timer/Counter Control Register */ ++#define GTCCR _SFR_IO8(0x23) ++/* GTCCR */ ++#define TSM 7 /* Timer/Counter Synchronization Mode */ ++#define ICPSEL1 6 /* Timer1 Input Capture Selection Bit */ ++#define PSRSYNC 0 ++ ++/* Timer/Counter Control Register A */ ++#define TCCR0A _SFR_IO8(0x24) ++/* TCCR0A */ ++#define COM0A1 7 /* Compare Output Mode, Phase Correct PWM Mode */ ++#define COM0A0 6 /* Compare Output Mode, Phase Correct PWM Mode */ ++#define COM0B1 5 /* Compare Output Mode, Fast PWm */ ++#define COM0B0 4 /* Compare Output Mode, Fast PWm */ ++#define WGM01 1 /* Waveform Generation Mode */ ++#define WGM00 0 /* Waveform Generation Mode */ ++ ++/* Timer/Counter Control Register B */ ++#define TCCR0B _SFR_IO8(0x25) ++/* TCCR0B */ ++#define FOC0A 7 /* Force Output Compare A */ ++#define FOC0B 6 /* Force Output Compare B */ ++#define WGM02 3 /* Waveform Generation Mode */ ++#define CS02 2 /* Clock Select */ ++#define CS01 1 /* Clock Select */ ++#define CS00 0 /* Clock Select */ ++ ++/* Timer/Counter0 Register */ ++#define TCNT0 _SFR_IO8(0x26) ++/* TCNT0 */ ++#define TCNT07 7 ++#define TCNT06 6 ++#define TCNT05 5 ++#define TCNT04 4 ++#define TCNT03 3 ++#define TCNT02 2 ++#define TCNT01 1 ++#define TCNT00 0 ++ ++/* Timer/Counter0 Output Compare Register A */ ++#define OCR0A _SFR_IO8(0x27) ++/* OCR0A */ ++#define OCR0A7 7 ++#define OCR0A6 6 ++#define OCR0A5 5 ++#define OCR0A4 4 ++#define OCR0A3 3 ++#define OCR0A2 2 ++#define OCR0A1 1 ++#define OCR0A0 0 ++ ++/* Timer/Counter0 Output Compare Register B */ ++#define OCR0B _SFR_IO8(0x28) ++/* OCR0B */ ++#define OCR0B7 7 ++#define OCR0B6 6 ++#define OCR0B5 5 ++#define OCR0B4 4 ++#define OCR0B3 3 ++#define OCR0B2 2 ++#define OCR0B1 1 ++#define OCR0B0 0 ++ ++/* PLL Control and Status Register */ ++#define PLLCSR _SFR_IO8(0x29) ++/* PLLCSR */ ++#define PLLF 2 ++#define PLLE 1 /* PLL Enable */ ++#define PLOCK 0 /* PLL Lock Detector */ ++ ++/* Reserved [0x2A..0x2B] */ ++ ++/* SPI Control Register */ ++#define SPCR _SFR_IO8(0x2C) ++/* SPCR */ ++#define SPIE 7 /* SPI Interrupt Enable */ ++#define SPE 6 /* SPI Enable */ ++#define DORD 5 /* Data Order */ ++#define MSTR 4 /* Master/Slave Select */ ++#define CPOL 3 /* Clock polarity */ ++#define CPHA 2 /* Clock Phase */ ++#define SPR1 1 /* SPI Clock Rate Select 1 */ ++#define SPR0 0 /* SPI Clock Rate Select 0 */ ++ ++/* SPI Status Register */ ++#define SPSR _SFR_IO8(0x2D) ++/* SPSR */ ++#define SPIF 7 /* SPI Interrupt Flag */ ++#define WCOL 6 /* Write Collision Flag */ ++#define SPI2X 0 /* Double SPI Speed Bit */ ++ ++/* SPI Data Register */ ++#define SPDR _SFR_IO8(0x2E) ++/* SPDR */ ++#define SPD7 7 ++#define SPD6 6 ++#define SPD5 5 ++#define SPD4 4 ++#define SPD3 3 ++#define SPD2 2 ++#define SPD1 1 ++#define SPD0 0 ++ ++/* Reserved [0x2F] */ ++ ++/* Analog Comparator Status Register */ ++#define ACSR _SFR_IO8(0x30) ++/* ACSR */ ++#define ACCKDIV 7 /* Analog Comparator Clock Divider */ ++#define AC2IF 6 /* Analog Comparator 2 Interrupt Flag Bit */ ++#define AC0IF 4 /* Analog Comparator 0 Interrupt Flag Bit */ ++#define AC2O 2 /* Analog Comparator 2 Output Bit */ ++#define AC0O 0 /* Analog Comparator 0 Output Bit */ ++ ++/* Monitor Data Register */ ++#define MONDR _SFR_IO8(0x31) ++ ++/* Monitor Stop Mode Control Register */ ++#define MSMCR _SFR_IO8(0x32) ++ ++/* Sleep Mode Control Register */ ++#define SMCR _SFR_IO8(0x33) ++/* SMCR */ ++#define SM2 3 /* Sleep Mode Select bit2 */ ++#define SM1 2 /* Sleep Mode Select bit1 */ ++#define SM0 1 /* Sleep Mode Select bit0 */ ++#define SE 0 /* Sleep Enable */ ++ ++/* MCU Status Register */ ++#define MCUSR _SFR_IO8(0x34) ++/* MCUSR */ ++#define WDRF 3 /* Watchdog Reset Flag */ ++#define BORF 2 /* Brown-out Reset Flag */ ++#define EXTRF 1 /* External Reset Flag */ ++#define PORF 0 /* Power-on reset flag */ ++ ++/* MCU Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++/* MCUCR */ ++#define SPIPS 7 /* SPI Pin Select */ ++#define PUD 4 /* Pull-up disable */ ++#define IVSEL 1 /* Interrupt Vector Select */ ++#define IVCE 0 /* Interrupt Vector Change Enable */ ++ ++/* Reserved [0x36] */ ++ ++/* Store Program Memory Control Register */ ++#define SPMCSR _SFR_IO8(0x37) ++/* SPMCSR */ ++#define SPMIE 7 /* SPM Interrupt Enable */ ++#define RWWSB 6 /* Read While Write Section Busy */ ++#define RWWSRE 4 /* Read While Write section read enable */ ++#define BLBSET 3 /* Boot Lock Bit Set */ ++#define PGWRT 2 /* Page Write */ ++#define PGERS 1 /* Page Erase */ ++#define SPMEN 0 /* Store Program Memory Enable */ ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* 0x3D..0x3E SP [defined in ] */ ++/* 0x3F SREG [defined in ] */ ++ ++/* Watchdog Timer Control Register */ ++#define WDTCSR _SFR_MEM8(0x60) ++/* WDTCSR */ ++#define WDIF 7 /* Watchdog Timeout Interrupt Flag */ ++#define WDIE 6 /* Watchdog Timeout Interrupt Enable */ ++#define WDP3 5 /* Watchdog Timer Prescaler bit3 */ ++#define WDCE 4 /* Watchdog Change Enable */ ++#define WDE 3 /* Watchdog Enable */ ++#define WDP2 2 /* Watchdog Timer Prescaler bit2 */ ++#define WDP1 1 /* Watchdog Timer Prescaler bit1 */ ++#define WDP0 0 /* Watchdog Timer Prescaler bit0 */ ++ ++/* Clock Prescaler Register */ ++#define CLKPR _SFR_MEM8(0x61) ++/* CLKPR */ ++#define CLKPCE 7 /* Clock Prescaler Change Enable */ ++#define CLKPS3 3 /* Clock Prescaler Select bit3 */ ++#define CLKPS2 2 /* Clock Prescaler Select bit2 */ ++#define CLKPS1 1 /* Clock Prescaler Select bit1 */ ++#define CLKPS0 0 /* Clock Prescaler Select bit0 */ ++ ++/* Reserved [0x62..0x63] */ ++ ++/* Power Reduction Register */ ++#define PRR _SFR_MEM8(0x64) ++/* PRR */ ++#define PRPSC2 7 /* Power Reduction PSC2 */ ++#define PRPSC1 6 /* Power Reduction PSC1 */ ++#define PRPSC0 5 /* Power Reduction PSC0 */ ++#define PRTIM1 4 /* Power Reduction Timer/Counter1 */ ++#define PRTIM0 3 /* Power Reduction Timer/Counter0 */ ++#define PRSPI 2 /* Power Reduction Serial Peripheral Interface */ ++#define PRADC 0 /* Power Reduction ADC */ ++ ++/* Reserved [0x65] */ ++ ++/* Oscillator Calibration Value */ ++#define OSCCAL _SFR_MEM8(0x66) ++/* OSCCAL */ ++#define CAL6 6 ++#define CAL5 5 ++#define CAL4 4 ++#define CAL3 3 ++#define CAL2 2 ++#define CAL1 1 ++#define CAL0 0 ++ ++/* Reserved [0x67..0x68] */ ++ ++/* External Interrupt Control Register A */ ++#define EICRA _SFR_MEM8(0x69) ++/* EICRA */ ++#define ISC31 7 ++#define ISC30 6 ++#define ISC21 5 ++#define ISC20 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* Reserved [0x6A..0x6D] */ ++ ++/* Timer/Counter0 Interrupt Mask Register */ ++#define TIMSK0 _SFR_MEM8(0x6E) ++/* TIMSK0 */ ++#define OCIE0B 2 /* Output Compare Match B Interrupt Enable */ ++#define OCIE0A 1 /* Output Compare Match A Interrupt Enable */ ++#define TOIE0 0 /* Overflow Interrupt Enable */ ++ ++/* Timer/Counter1 Interrupt Mask Register */ ++#define TIMSK1 _SFR_MEM8(0x6F) ++/* TIMSK1 */ ++#define ICIE1 5 /* Input Capture Interrupt Enable */ ++#define OCIE1B 2 /* Output Compare Match B Interrupt Enable */ ++#define OCIE1A 1 /* Output Compare Match A Interrupt Enable */ ++#define TOIE1 0 /* Overflow Interrupt Enable */ ++ ++/* Reserved [0x70..0x75] */ ++ ++/* Amplifier 0 Control and Status register */ ++#define AMP0CSR _SFR_MEM8(0x76) ++#define AMP0EN 7 ++#define AMP0IS 6 ++#define AMP0G1 5 ++#define AMP0G0 4 ++#define AMP0TS1 1 ++#define AMP0TS0 0 ++ ++/* Reserved [0x77] */ ++ ++/* ADC Result Data Register */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++/* ADC Control and Status Register A */ ++#define ADCSRA _SFR_MEM8(0x7A) ++/* ADCSRA */ ++#define ADEN 7 /* ADC Enable */ ++#define ADSC 6 /* ADC Start Conversion */ ++#define ADATE 5 /* ADC Auto Trigger Enable */ ++#define ADIF 4 /* ADC Interrupt Flag */ ++#define ADIE 3 /* ADC Interrupt Enable */ ++#define ADPS2 2 /* ADC Prescaler Select bit2 */ ++#define ADPS1 1 /* ADC Prescaler Select bit1 */ ++#define ADPS0 0 /* ADC Prescaler Select bit0 */ ++ ++/* ADC Control and Status Register B */ ++#define ADCSRB _SFR_MEM8(0x7B) ++/* ADCSRB */ ++#define ADTS3 3 /* ADC Auto Trigger Source 2 */ ++#define ADTS2 2 /* ADC Auto Trigger Source 2 */ ++#define ADTS1 1 /* ADC Auto Trigger Source 1 */ ++#define ADTS0 0 /* ADC Auto Trigger Source 0 */ ++ ++/* ADC multiplexer Selection Register */ ++#define ADMUX _SFR_MEM8(0x7C) ++/* ADMUX */ ++#define REFS1 7 /* Reference Selection bit1 */ ++#define REFS0 6 /* Reference Selection bit0 */ ++#define ADLAR 5 /* Left Adjust Result */ ++#define MUX3 3 /* Analog Channel and Gain Selection bit3 */ ++#define MUX2 2 /* Analog Channel and Gain Selection bit2 */ ++#define MUX1 1 /* Analog Channel and Gain Selection bit1 */ ++#define MUX0 0 /* Analog Channel and Gain Selection bit0 */ ++ ++/* Reserved [0x7D] */ ++ ++/* Digital Input Disable Register 0 */ ++#define DIDR0 _SFR_MEM8(0x7E) ++/* DIDR0 */ ++#define ADC7D 7 /* ADC7 Digital input Disable */ ++#define ADC6D 6 /* ADC6 Digital input Disable */ ++#define ADC5D 5 /* ADC5 Digital input Disable */ ++#define ADC4D 4 /* ADC4 Digital input Disable */ ++#define ADC3D 3 /* ADC3 Digital input Disable */ ++#define ADC2D 2 /* ADC2 Digital input Disable */ ++#define ADC1D 1 /* ADC1 Digital input Disable */ ++#define ADC0D 0 /* ADC0 Digital input Disable */ ++ ++/* Digital Input Disable Register 1 */ ++#define DIDR1 _SFR_MEM8(0x7F) ++/* DIDR1 */ ++#define ACMP0D 5 ++#define AMP0PD 4 ++#define AMP0ND 3 ++#define ADC10D 2 /* ADC10 Digital input Disable */ ++#define ADC9D 1 /* ADC9 Digital input Disable */ ++#define ADC8D 0 /* ADC8 Digital input Disable */ ++ ++/* Timer/Counter1 Control Register A */ ++#define TCCR1A _SFR_MEM8(0x80) ++/* TCCR1A */ ++#define COM1A1 7 /* Comparet Ouput Mode 1A, bit 1 */ ++#define COM1A0 6 /* Comparet Ouput Mode 1A, bit 0 */ ++#define COM1B1 5 /* Compare Output Mode 1B, bit 1 */ ++#define COM1B0 4 /* Compare Output Mode 1B, bit 0 */ ++#define WGM11 1 /* Waveform Generation Mode */ ++#define WGM10 0 /* Waveform Generation Mode */ ++ ++/* Timer/Counter1 Control Register B */ ++#define TCCR1B _SFR_MEM8(0x81) ++/* TCCR1B */ ++#define ICNC1 7 /* Input Capture 1 Noise Canceler */ ++#define ICES1 6 /* Input Capture 1 Edge Select */ ++#define WGM13 4 /* Waveform Generation Mode */ ++#define WGM12 3 /* Waveform Generation Mode */ ++#define CS12 2 /* Prescaler source of Timer/Counter 1 */ ++#define CS11 1 /* Prescaler source of Timer/Counter 1 */ ++#define CS10 0 /* Prescaler source of Timer/Counter 1 */ ++ ++/* Timer/Counter1 Control Register C */ ++#define TCCR1C _SFR_MEM8(0x82) ++/* TCCR1C */ ++#define FOC1A 7 /* Force Output Compare for Channel A */ ++#define FOC1B 6 /* Force Output Compare for Channel B */ ++ ++/* Reserved [0x83] */ ++ ++/* Timer/Counter1 */ ++#define TCNT1 _SFR_MEM16(0x84) ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++/* TCNT1H */ ++#define TCNT115 7 ++#define TCNT114 6 ++#define TCNT113 5 ++#define TCNT112 4 ++#define TCNT111 3 ++#define TCNT110 2 ++#define TCNT19 1 ++#define TCNT18 0 ++/* TCNT1L */ ++#define TCNT17 7 ++#define TCNT16 6 ++#define TCNT15 5 ++#define TCNT14 4 ++#define TCNT13 3 ++#define TCNT12 2 ++#define TCNT11 1 ++#define TCNT10 0 ++ ++/* Input Capture Register 1 */ ++#define ICR1 _SFR_MEM16(0x86) ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++/* ICR1H */ ++#define ICR115 7 ++#define ICR114 6 ++#define ICR113 5 ++#define ICR112 4 ++#define ICR111 3 ++#define ICR110 2 ++#define ICR19 1 ++#define ICR18 0 ++/* ICR1L */ ++#define ICR17 7 ++#define ICR16 6 ++#define ICR15 5 ++#define ICR14 4 ++#define ICR13 3 ++#define ICR12 2 ++#define ICR11 1 ++#define ICR10 0 ++ ++/* Output Compare Register 1 A */ ++#define OCR1A _SFR_MEM16(0x88) ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++/* OCR1AH */ ++#define OCR1A15 7 ++#define OCR1A14 6 ++#define OCR1A13 5 ++#define OCR1A12 4 ++#define OCR1A11 3 ++#define OCR1A10 2 ++#define OCR1A9 1 ++#define OCR1A8 0 ++/* OCR1AL */ ++#define OCR1A7 7 ++#define OCR1A6 6 ++#define OCR1A5 5 ++#define OCR1A4 4 ++#define OCR1A3 3 ++#define OCR1A2 2 ++#define OCR1A1 1 ++#define OCR1A0 0 ++ ++/* Output Compare Register 1 B */ ++#define OCR1B _SFR_MEM16(0x8A) ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++/* OCR1BH */ ++#define OCR1B15 7 ++#define OCR1B14 6 ++#define OCR1B13 5 ++#define OCR1B12 4 ++#define OCR1B11 3 ++#define OCR1B10 2 ++#define OCR1B9 1 ++#define OCR1B8 0 ++/* OCR1BL */ ++#define OCR1B7 7 ++#define OCR1B6 6 ++#define OCR1B5 5 ++#define OCR1B4 4 ++#define OCR1B3 3 ++#define OCR1B2 2 ++#define OCR1B1 1 ++#define OCR1B0 0 ++ ++/* Reserved [0x8C..0x9F] */ ++ ++/* PSC0 Interrupt Flag Register */ ++#define PIFR0 _SFR_MEM8(0xA0) ++/* PIFR0 */ ++#define PSEI0 5 /* PSC0 Synchro Error Interrupt */ ++#define PEV0B 4 /* PSC0 External Event B Interrupt */ ++#define PEV0A 3 /* PSC0 External Event A Interrupt */ ++#define PRN01 2 /* PSC0 Ramp Number bit1 */ ++#define PRN00 1 /* PSC0 Ramp Number bit0 */ ++#define PEOP0 0 /* End Of PSC0 Interrupt */ ++ ++/* PSC0 Interrupt Mask Register */ ++#define PIM0 _SFR_MEM8(0xA1) ++/* PIM0 */ ++#define PSEIE0 5 /* PSC0 Synchro Error Interrupt Enable */ ++#define PEVE0B 4 /* PSC0 External Event B Interrupt Enable */ ++#define PEVE0A 3 /* PSC0 External Event A Interrupt Enable */ ++#define PEOPE0 0 /* PSC0 End Of Cycle Interrupt Enable */ ++ ++/* Reserved [0xA2..0xA3] */ ++ ++/* PSC2 Interrupt Flag Register */ ++#define PIFR2 _SFR_MEM8(0xA4) ++/* PIFR2 */ ++#define PSEI2 5 /* PSC2 Synchro Error Interrupt */ ++#define PEV2B 4 /* PSC2 External Event B Interrupt */ ++#define PEV2A 3 /* PSC2 External Event A Interrupt */ ++#define PRN21 2 /* PSC2 Ramp Number bit1 */ ++#define PRN20 1 /* PSC2 Ramp Number bit0 */ ++#define PEOP2 0 /* End Of PSC2 Interrupt */ ++ ++/* PSC2 Interrupt Mask Register */ ++#define PIM2 _SFR_MEM8(0xA5) ++/* PIM2 */ ++#define PSEIE2 5 /* PSC2 Synchro Error Interrupt Enable */ ++#define PEVE2B 4 /* PSC2 External Event B Interrupt Enable */ ++#define PEVE2A 3 /* PSC2 External Event A Interrupt Enable */ ++#define PEOPE2 0 /* PSC2 End Of Cycle Interrupt Enable */ ++ ++/* Reserved [0xA6..0xAC] */ ++ ++/* Analog Comparator 0 Control Register */ ++#define AC0CON _SFR_MEM8(0xAD) ++/* AC0CON */ ++#define AC0EN 7 /* Analog Comparator 0 Enable Bit */ ++#define AC0IE 6 /* Analog Comparator 0 Interrupt Enable bit */ ++#define AC0IS1 5 /* Analog Comparator 0 Interrupt Select bit1 */ ++#define AC0IS0 4 /* Analog Comparator 0 Interrupt Select bit0 */ ++#define AC0M2 2 /* Analog Comparator 0 Multiplexer register bit2 */ ++#define AC0M1 1 /* Analog Comparator 0 Multiplexer register bit1 */ ++#define AC0M0 0 /* Analog Comparator 0 Multiplexer register bit0 */ ++ ++/* Reserved [0xB0..0xAE] */ ++ ++/* Analog Comparator 2 Control Register */ ++#define AC2CON _SFR_MEM8(0xAF) ++/* AC2CON */ ++#define AC2EN 7 /* Analog Comparator 2 Enable Bit */ ++#define AC2IE 6 /* Analog Comparator 2 Interrupt Enable bit */ ++#define AC2IS1 5 /* Analog Comparator 2 Interrupt Select bit1 */ ++#define AC2IS0 4 /* Analog Comparator 2 Interrupt Select bit0 */ ++#define AC2M2 2 /* Analog Comparator 2 Multiplexer register bit2 */ ++#define AC2M1 1 /* Analog Comparator 2 Multiplexer register bit1 */ ++#define AC2M0 0 /* Analog Comparator 2 Multiplexer register bit0 */ ++ ++/* Reserved [0xB0..0xCF] */ ++ ++/* PSC 0 Synchro and Output Configuration */ ++#define PSOC0 _SFR_MEM8(0xD0) ++/* PSOC0 */ ++#define PSYNC01 5 /* Synchronization Out for ADC Selection bit1 */ ++#define PSYNC00 4 /* Synchronization Out for ADC Selection bit0 */ ++#define POEN0B 2 /* PSC 0 OUT Part B Output Enable */ ++#define POEN0A 0 /* PSC 0 OUT Part A Output Enable */ ++ ++/* Reserved [0xD1] */ ++ ++/* Output Compare SA Registers */ ++#define OCR0SA _SFR_MEM16(0xD2) ++#define OCR0SAL _SFR_MEM8(0xD2) ++#define OCR0SAH _SFR_MEM8(0xD3) ++ ++/* Output Compare RA Registers */ ++#define OCR0RA _SFR_MEM16(0xD4) ++#define OCR0RAL _SFR_MEM8(0xD4) ++#define OCR0RAH _SFR_MEM8(0xD5) ++ ++/* Output Compare SB Registers */ ++#define OCR0SB _SFR_MEM16(0xD6) ++#define OCR0SBL _SFR_MEM8(0xD6) ++#define OCR0SBH _SFR_MEM8(0xD7) ++ ++/* Output Compare RB Registers */ ++#define OCR0RB _SFR_MEM16(0xD8) ++#define OCR0RBL _SFR_MEM8(0xD8) ++#define OCR0RBH _SFR_MEM8(0xD9) ++ ++/* PSC 0 Configuration Register */ ++#define PCNF0 _SFR_MEM8(0xDA) ++/* PCNF0 */ ++#define PFIFTY0 7 /* PSC 0 Fifty */ ++#define PALOCK0 6 /* PSC 0 Autolock */ ++#define PLOCK0 5 /* PSC 0 Lock */ ++#define PMODE01 4 /* PSC 0 Mode bit1 */ ++#define PMODE00 3 /* PSC 0 Mode bit0 */ ++#define POP0 2 /* PSC 0 Output Polarity */ ++#define PCLKSEL0 1 /* PSC 0 Input Clock Select */ ++ ++/* PSC 0 Control Register */ ++#define PCTL0 _SFR_MEM8(0xDB) ++/* PCTL0 */ ++#define PPRE01 7 /* PSC 0 Prescaler Select bit1 */ ++#define PPRE00 6 /* PSC 0 Prescaler Select bit0 */ ++#define PBFM0 5 /* Balance Flank Width Modulation */ ++#define PAOC0B 4 /* PSC 0 Asynchronous Output Control B */ ++#define PAOC0A 3 /* PSC 0 Asynchronous Output Control A */ ++#define PARUN0 2 /* PSC 0 Autorun */ ++#define PCCYC0 1 /* PSC 0 Complete Cycle */ ++#define PRUN0 0 /* PSC 0 Run */ ++ ++/* PSC 0 Input A Control Register */ ++#define PFRC0A _SFR_MEM8(0xDC) ++/* PFRC0A */ ++#define PCAE0A 7 /* PSC 0 Capture Enable Input Part A */ ++#define PISEL0A 6 /* PSC 0 Input Select for Part A */ ++#define PELEV0A 5 /* PSC 0 Edge Level Selector of Input Part A */ ++#define PFLTE0A 4 /* PSC 0 Filter Enable on Input Part A */ ++#define PRFM0A3 3 /* PSC 0 Fault Mode bit3 */ ++#define PRFM0A2 2 /* PSC 0 Fault Mode bit2 */ ++#define PRFM0A1 1 /* PSC 0 Fault Mode bit1 */ ++#define PRFM0A0 0 /* PSC 0 Fault Mode bit0 */ ++ ++/* PSC 0 Input B Control Register */ ++#define PFRC0B _SFR_MEM8(0xDD) ++/* PFRC0B */ ++#define PCAE0B 7 /* PSC 0 Capture Enable Input Part B */ ++#define PISEL0B 6 /* PSC 0 Input Select for Part B */ ++#define PELEV0B 5 /* PSC 0 Edge Level Selector of Input Part B */ ++#define PFLTE0B 4 /* PSC 0 Filter Enable on Input Part B */ ++#define PRFM0B3 3 /* PSC 0 Fault Mode bit3 */ ++#define PRFM0B2 2 /* PSC 0 Fault Mode bit2 */ ++#define PRFM0B1 1 /* PSC 0 Fault Mode bit1 */ ++#define PRFM0B0 0 /* PSC 0 Fault Mode bit0 */ ++ ++/* PSC 0 Input Capture Registers */ ++#define PICR0 _SFR_MEM16(0xDE) ++ ++#define PICR0L _SFR_MEM8(0xDE) ++ ++#define PICR0H _SFR_MEM8(0xDF) ++#define PCST0 7 /* PSC Capture Software Trig bit */ ++ ++/* Reserved [0xE0..0xEF] */ ++ ++/* PSC 2 Synchro and Output Configuration */ ++#define PSOC2 _SFR_MEM8(0xF0) ++/* PSOC2 */ ++#define POS23 7 /* PSCOUT23 Selection */ ++#define POS22 6 /* PSCOUT22 Selection */ ++#define PSYNC21 5 /* Synchronization Out for ADC Selection bit1 */ ++#define PSYNC20 4 /* Synchronization Out for ADC Selection bit0 */ ++#define POEN2D 3 /* PSCOUT23 Output Enable */ ++#define POEN2B 2 /* PSC 2 OUT Part B Output Enable */ ++#define POEN2C 1 /* PSCOUT22 Output Enable */ ++#define POEN2A 0 /* PSC 2 OUT Part A Output Enable */ ++ ++/* PSC 2 Output Matrix */ ++#define POM2 _SFR_MEM8(0xF1) ++/* POM2 */ ++#define POMV2B3 7 /* Output Matrix Output B Ramp 3 */ ++#define POMV2B2 6 /* Output Matrix Output B Ramp 2 */ ++#define POMV2B1 5 /* Output Matrix Output B Ramp 1 */ ++#define POMV2B0 4 /* Output Matrix Output B Ramp 0 */ ++#define POMV2A3 3 /* Output Matrix Output A Ramp 3 */ ++#define POMV2A2 2 /* Output Matrix Output A Ramp 2 */ ++#define POMV2A1 1 /* Output Matrix Output A Ramp 1 */ ++#define POMV2A0 0 /* Output Matrix Output A Ramp 0 */ ++ ++/* Output Compare SA Registers */ ++#define OCR2SA _SFR_MEM16(0xF2) ++#define OCR2SAL _SFR_MEM8(0xF2) ++#define OCR2SAH _SFR_MEM8(0xF3) ++ ++/* Output Compare RA Registers */ ++#define OCR2RA _SFR_MEM16(0xF4) ++#define OCR2RAL _SFR_MEM8(0xF4) ++#define OCR2RAH _SFR_MEM8(0xF5) ++ ++/* Output Compare SB Registers */ ++#define OCR2SB _SFR_MEM16(0xF6) ++#define OCR2SBL _SFR_MEM8(0xF6) ++#define OCR2SBH _SFR_MEM8(0xF7) ++ ++/* Output Compare RB Registers */ ++#define OCR2RB _SFR_MEM16(0xF8) ++#define OCR2RBL _SFR_MEM8(0xF8) ++#define OCR2RBH _SFR_MEM8(0xF9) ++ ++/* PSC 2 Configuration Register */ ++#define PCNF2 _SFR_MEM8(0xFA) ++/* PCNF2 */ ++#define PFIFTY2 7 /* PSC 2 Fifty */ ++#define PALOCK2 6 /* PSC 2 Autolock */ ++#define PLOCK2 5 /* PSC 2 Lock */ ++#define PMODE21 4 /* PSC 2 Mode bit1 */ ++#define PMODE20 3 /* PSC 2 Mode bit0 */ ++#define POP2 2 /* PSC 2 Output Polarity */ ++#define PCLKSEL2 1 /* PSC 2 Input Clock Select */ ++#define POME2 0 /* PSC 2 Output Matrix Enable */ ++ ++/* PSC 2 Control Register */ ++#define PCTL2 _SFR_MEM8(0xFB) ++/* PCTL2 */ ++#define PPRE21 7 /* PSC 2 Prescaler Select bit1 */ ++#define PPRE20 6 /* PSC 2 Prescaler Select bit0 */ ++#define PBFM2 5 /* Balance Flank Width Modulation */ ++#define PAOC2B 4 /* PSC 2 Asynchronous Output Control B */ ++#define PAOC2A 3 /* PSC 2 Asynchronous Output Control A */ ++#define PARUN2 2 /* PSC 2 Autorun */ ++#define PCCYC2 1 /* PSC 2 Complete Cycle */ ++#define PRUN2 0 /* PSC 2 Run */ ++ ++/* PSC 2 Input A Control Register */ ++#define PFRC2A _SFR_MEM8(0xFC) ++/* PFRC2A */ ++#define PCAE2A 7 /* PSC 2 Capture Enable Input Part A */ ++#define PISEL2A 6 /* PSC 2 Input Select for Part A */ ++#define PELEV2A 5 /* PSC 2 Edge Level Selector of Input Part A */ ++#define PFLTE2A 4 /* PSC 2 Filter Enable on Input Part A */ ++#define PRFM2A3 3 /* PSC 2 Fault Mode bit3 */ ++#define PRFM2A2 2 /* PSC 2 Fault Mode bit2 */ ++#define PRFM2A1 1 /* PSC 2 Fault Mode bit1 */ ++#define PRFM2A0 0 /* PSC 2 Fault Mode bit0 */ ++ ++/* PSC 2 Input B Control Register */ ++#define PFRC2B _SFR_MEM8(0xFD) ++/* PFRC2B */ ++#define PCAE2B 7 /* PSC 2 Capture Enable Input Part B */ ++#define PISEL2B 6 /* PSC 2 Input Select for Part B */ ++#define PELEV2B 5 /* PSC 2 Edge Level Selector of Input Part B */ ++#define PFLTE2B 4 /* PSC 2 Filter Enable on Input Part B */ ++#define PRFM2B3 3 /* PSC 2 Fault Mode bit3 */ ++#define PRFM2B2 2 /* PSC 2 Fault Mode bit2 */ ++#define PRFM2B1 1 /* PSC 2 Fault Mode bit1 */ ++#define PRFM2B0 0 /* PSC 2 Fault Mode bit0 */ ++ ++/* PSC 2 Input Capture Registers */ ++#define PICR2 _SFR_MEM16(0xFE) ++ ++#define PICR2L _SFR_MEM8(0xFE) ++ ++#define PICR2H _SFR_MEM8(0xFF) ++#define PCST2 7 /* PSC Capture Software Trig bit */ ++ /* not implemented on AT90PWM2/AT90PWM3 */ ++ ++ ++/* Interrupt vectors */ ++/* PSC2 Capture Event */ ++#define PSC2_CAPT_vect_num 1 ++#define PSC2_CAPT_vect _VECTOR(1) ++#define SIG_PSC2_CAPTURE _VECTOR(1) ++ ++/* PSC2 End Cycle */ ++#define PSC2_EC_vect_num 2 ++#define PSC2_EC_vect _VECTOR(2) ++#define SIG_PSC2_END_CYCLE _VECTOR(2) ++ ++/* PSC0 Capture Event */ ++#define PSC0_CAPT_vect_num 5 ++#define PSC0_CAPT_vect _VECTOR(5) ++#define SIG_PSC0_CAPTURE _VECTOR(5) ++ ++/* PSC0 End Cycle */ ++#define PSC0_EC_vect_num 6 ++#define PSC0_EC_vect _VECTOR(6) ++#define SIG_PSC0_END_CYCLE _VECTOR(6) ++ ++/* Analog Comparator 0 */ ++#define ANALOG_COMP_0_vect_num 7 ++#define ANALOG_COMP_0_vect _VECTOR(7) ++#define SIG_COMPARATOR0 _VECTOR(7) ++ ++/* Analog Comparator 2 */ ++#define ANALOG_COMP_2_vect_num 9 ++#define ANALOG_COMP_2_vect _VECTOR(9) ++#define SIG_COMPARATOR2 _VECTOR(9) ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 10 ++#define INT0_vect _VECTOR(10) ++#define SIG_INTERRUPT0 _VECTOR(10) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 11 ++#define TIMER1_CAPT_vect _VECTOR(11) ++#define SIG_INPUT_CAPTURE1 _VECTOR(11) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 12 ++#define TIMER1_COMPA_vect _VECTOR(12) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(12) ++#define SIG_OUTPUT_COMPARE1_A _VECTOR(12) ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect_num 13 ++#define TIMER1_COMPB_vect _VECTOR(13) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(13) ++#define SIG_OUTPUT_COMPARE1_B _VECTOR(13) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 15 ++#define TIMER1_OVF_vect _VECTOR(15) ++#define SIG_OVERFLOW1 _VECTOR(15) ++ ++/* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMP_A_vect_num 16 ++#define TIMER0_COMP_A_vect _VECTOR(16) ++#define SIG_OUTPUT_COMPARE0A _VECTOR(16) ++#define SIG_OUTPUT_COMPARE0_A _VECTOR(16) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 17 ++#define TIMER0_OVF_vect _VECTOR(17) ++#define SIG_OVERFLOW0 _VECTOR(17) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 18 ++#define ADC_vect _VECTOR(18) ++#define SIG_ADC _VECTOR(18) ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect_num 19 ++#define INT1_vect _VECTOR(19) ++#define SIG_INTERRUPT1 _VECTOR(19) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 20 ++#define SPI_STC_vect _VECTOR(20) ++#define SIG_SPI _VECTOR(20) ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect_num 24 ++#define INT2_vect _VECTOR(24) ++#define SIG_INTERRUPT2 _VECTOR(24) ++ ++/* Watchdog Timeout Interrupt */ ++#define WDT_vect_num 25 ++#define WDT_vect _VECTOR(25) ++#define SIG_WDT _VECTOR(25) ++#define SIG_WATCHDOG_TIMEOUT _VECTOR(25) ++ ++/* EEPROM Ready */ ++#define EE_READY_vect_num 26 ++#define EE_READY_vect _VECTOR(26) ++#define SIG_EEPROM_READY _VECTOR(26) ++ ++/* Timer Counter 0 Compare Match B */ ++#define TIMER0_COMPB_vect_num 27 ++#define TIMER0_COMPB_vect _VECTOR(27) ++#define SIG_OUTPUT_COMPARE0B _VECTOR(27) ++#define SIG_OUTPUT_COMPARE0_B _VECTOR(27) ++ ++/* External Interrupt Request 3 */ ++#define INT3_vect_num 28 ++#define INT3_vect _VECTOR(28) ++#define SIG_INTERRUPT3 _VECTOR(28) ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect_num 31 ++#define SPM_READY_vect _VECTOR(31) ++#define SIG_SPM_READY _VECTOR(31) ++ ++#define _VECTORS_SIZE 64 ++ ++/* Constants */ ++#define SPM_PAGESIZE 64 ++ ++#define RAMSTART 0x100 ++#define RAMEND 0x02FF ++#define XRAMEND RAMEND ++#define E2END 0x01FF ++#define FLASHEND 0x1FFF ++ ++ ++/* Fuse Information */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Diasble */ ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_PSCRV (unsigned char)~_BV(4) ++#define FUSE_PSC0RB (unsigned char)~_BV(5) ++#define FUSE_PSC2RB (unsigned char)~_BV(7) ++#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++#endif /* _AVR_IOPWM1_H_ */ diff --git a/include/avr/io90pwm161.h b/include/avr/io90pwm161.h new file mode 100644 -index 0000000..df75ed1 +index 0000000..7229726 --- /dev/null +++ b/include/avr/io90pwm161.h @@ -0,0 +1,859 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_AT90PWM161_H_INCLUDED -+#define _AVR_AT90PWM161_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "io90pwm161.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define ACSR _SFR_IO8(0x00) -+#define AC1O 1 -+#define AC2O 2 -+#define AC3O 3 -+#define AC1IF 5 -+#define AC2IF 6 -+#define AC3IF 7 -+ -+#define TIMSK1 _SFR_IO8(0x01) -+#define TOIE1 0 -+#define ICIE1 5 -+ -+#define TIFR1 _SFR_IO8(0x02) -+#define TOV1 0 -+#define ICF1 5 -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define ADCSRA _SFR_IO8(0x06) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADCSRB _SFR_IO8(0x07) -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+#define ADTS3 3 -+#define ADSSEN 4 -+#define ADNCDIS 6 -+#define ADHSM 7 -+ -+#define ADMUX _SFR_IO8(0x08) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+#define PIND _SFR_IO8(0x09) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0A) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x0B) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+#define PINE _SFR_IO8(0x0C) -+#define PINE2 2 -+#define PINE1 1 -+#define PINE0 0 -+ -+#define DDRE _SFR_IO8(0x0D) -+#define DDRE2 2 -+#define DDRE1 1 -+#define DDRE0 0 -+ -+#define PORTE _SFR_IO8(0x0E) -+#define PORTE2 2 -+#define PORTE1 1 -+#define PORTE0 0 -+ -+#define PIM0 _SFR_IO8(0x0F) -+#define PEOPE0 0 -+#define PEOEPE0 1 -+#define PEVE0A 3 -+#define PEVE0B 4 -+ -+#define PIFR0 _SFR_IO8(0x10) -+#define PEOP0 0 -+#define PRN00 1 -+#define PRN01 2 -+#define PEV0A 3 -+#define PEV0B 4 -+#define POAC0A 6 -+#define POAC0B 7 -+ -+#define PCNF0 _SFR_IO8(0x11) -+#define PCLKSEL0 1 -+#define POP0 2 -+#define PMODE00 3 -+#define PMODE01 4 -+#define PLOCK0 5 -+#define PALOCK0 6 -+#define PFIFTY0 7 -+ -+#define PCTL0 _SFR_IO8(0x12) -+#define PRUN0 0 -+#define PCCYC0 1 -+#define PAOC0A 3 -+#define PAOC0B 4 -+#define PBFM00 2 -+#define PBFM01 5 -+#define PPRE00 6 -+#define PPRE01 7 -+ -+#define PIM2 _SFR_IO8(0x13) -+#define PEOPE2 0 -+#define PEOEPE2 1 -+#define PEVE2A 3 -+#define PEVE2B 4 -+#define PSEIE2 5 -+ -+#define PIFR2 _SFR_IO8(0x14) -+#define PEOP2 0 -+#define PRN20 1 -+#define PRN21 2 -+#define PEV2A 3 -+#define PEV2B 4 -+#define PSEI2 5 -+#define POAC2A 6 -+#define POAC2B 7 -+ -+#define PCNF2 _SFR_IO8(0x15) -+#define POME2 0 -+#define PCLKSEL2 1 -+#define POP2 2 -+#define PMODE20 3 -+#define PMODE21 4 -+#define PLOCK2 5 -+#define PALOCK2 6 -+#define PFIFTY2 7 -+ -+#define PCTL2 _SFR_IO8(0x16) -+#define PRUN2 0 -+#define PCCYC2 1 -+#define PARUN2 2 -+#define PAOC2A 3 -+#define PAOC2B 4 -+#define PBFM2 5 -+#define PPRE20 6 -+#define PPRE21 7 -+ -+#define SPCR _SFR_IO8(0x17) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x18) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define GPIOR0 _SFR_IO8(0x19) -+#define GPIOR00 0 -+#define GPIOR01 1 -+#define GPIOR02 2 -+#define GPIOR03 3 -+#define GPIOR04 4 -+#define GPIOR05 5 -+#define GPIOR06 6 -+#define GPIOR07 7 -+ -+#define GPIOR1 _SFR_IO8(0x1A) -+#define GPIOR10 0 -+#define GPIOR11 1 -+#define GPIOR12 2 -+#define GPIOR13 3 -+#define GPIOR14 4 -+#define GPIOR15 5 -+#define GPIOR16 6 -+#define GPIOR17 7 -+ -+#define GPIOR2 _SFR_IO8(0x1B) -+#define GPIOR20 0 -+#define GPIOR21 1 -+#define GPIOR22 2 -+#define GPIOR23 3 -+#define GPIOR24 4 -+#define GPIOR25 5 -+#define GPIOR26 6 -+#define GPIOR27 7 -+ -+#define EECR _SFR_IO8(0x1C) -+#define EERE 0 -+#define EEWE 1 -+#define EEMWE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+#define EEPAGE 6 -+#define NVMBSY 7 -+ -+#define EEDR _SFR_IO8(0x1D) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x1E) -+ -+#define EEARL _SFR_IO8(0x1E) -+#define EEARH _SFR_IO8(0x1F) -+ -+#define EIFR _SFR_IO8(0x20) -+#define INTF0 0 -+#define INTF1 1 -+#define INTF2 2 -+ -+#define EIMSK _SFR_IO8(0x21) -+#define INT0 0 -+#define INT1 1 -+#define INT2 2 -+ -+/* Combine OCR0SBL and OCR0SBH */ -+#define OCR0SB _SFR_IO16(0x22) -+ -+#define OCR0SBL _SFR_IO8(0x22) -+#define OCR0SBH _SFR_IO8(0x23) -+ -+/* Combine OCR0RBL and OCR0RBH */ -+#define OCR0RB _SFR_IO16(0x24) -+ -+#define OCR0RBL _SFR_IO8(0x24) -+#define OCR0RBH _SFR_IO8(0x25) -+ -+/* Combine OCR2SBL and OCR2SBH */ -+#define OCR2SB _SFR_IO16(0x26) -+ -+#define OCR2SBL _SFR_IO8(0x26) -+#define OCR2SBH _SFR_IO8(0x27) -+ -+/* Combine OCR2RBL and OCR2RBH */ -+#define OCR2RB _SFR_IO16(0x28) -+ -+#define OCR2RBL _SFR_IO8(0x28) -+#define OCR2RBH _SFR_IO8(0x29) -+ -+/* Combine OCR0RAL and OCR0RAH */ -+#define OCR0RA _SFR_IO16(0x2A) -+ -+#define OCR0RAL _SFR_IO8(0x2A) -+#define OCR0RAH _SFR_IO8(0x2B) -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_IO16(0x2C) -+#endif -+#define ADCW _SFR_IO16(0x2C) -+ -+#define ADCL _SFR_IO8(0x2C) -+#define ADCH _SFR_IO8(0x2D) -+ -+/* Combine OCR2RAL and OCR2RAH */ -+#define OCR2RA _SFR_IO16(0x2E) -+ -+#define OCR2RAL _SFR_IO8(0x2E) -+#define OCR2RAH _SFR_IO8(0x2F) -+ -+/* Reserved [0x30..0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define IVCE 0 -+#define IVSEL 1 -+#define CKRC81 2 -+#define RSTDIS 3 -+#define PUD 4 -+ -+#define SPDR _SFR_IO8(0x36) -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define SIGRD 5 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+#define DACL _SFR_IO8(0x38) -+#define DACL0 0 -+#define DACL1 1 -+#define DACL2 2 -+#define DACL3 3 -+#define DACL4 4 -+#define DACL5 5 -+#define DACL6 6 -+#define DACL7 7 -+ -+#define DACH _SFR_IO8(0x39) -+#define DACH0 0 -+#define DACH1 1 -+#define DACH2 2 -+#define DACH3 3 -+#define DACH4 4 -+#define DACH5 5 -+#define DACH6 6 -+#define DACH7 7 -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_IO16(0x3A) -+ -+#define TCNT1L _SFR_IO8(0x3A) -+#define TCNT1H _SFR_IO8(0x3B) -+ -+/* Reserved [0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+/* Combine OCR0SAL and OCR0SAH */ -+#define OCR0SA _SFR_MEM16(0x60) -+ -+#define OCR0SAL _SFR_MEM8(0x60) -+#define OCR0SAH _SFR_MEM8(0x61) -+ -+#define PFRC0A _SFR_MEM8(0x62) -+#define PRFM0A0 0 -+#define PRFM0A1 1 -+#define PRFM0A2 2 -+#define PRFM0A3 3 -+#define PFLTE0A 4 -+#define PELEV0A 5 -+#define PISEL0A 6 -+#define PCAE0A 7 -+ -+#define PFRC0B _SFR_MEM8(0x63) -+#define PRFM0B0 0 -+#define PRFM0B1 1 -+#define PRFM0B2 2 -+#define PRFM0B3 3 -+#define PFLTE0B 4 -+#define PELEV0B 5 -+#define PISEL0B 6 -+#define PCAE0B 7 -+ -+/* Combine OCR2SAL and OCR2SAH */ -+#define OCR2SA _SFR_MEM16(0x64) -+ -+#define OCR2SAL _SFR_MEM8(0x64) -+#define OCR2SAH _SFR_MEM8(0x65) -+ -+#define PFRC2A _SFR_MEM8(0x66) -+#define PRFM2A0 0 -+#define PRFM2A1 1 -+#define PRFM2A2 2 -+#define PRFM2A3 3 -+#define PFLTE2A 4 -+#define PELEV2A 5 -+#define PISEL2A 6 -+#define PCAE2A 7 -+ -+#define PFRC2B _SFR_MEM8(0x67) -+#define PRFM2B0 0 -+#define PRFM2B1 1 -+#define PRFM2B2 2 -+#define PRFM2B3 3 -+#define PFLTE2B 4 -+#define PELEV2B 5 -+#define PISEL2B 6 -+#define PCAE2B 7 -+ -+/* Combine PICR0L and PICR0H */ -+#define PICR0 _SFR_MEM16(0x68) -+ -+#define PICR0L _SFR_MEM8(0x68) -+#define PICR0H _SFR_MEM8(0x69) -+ -+#define PSOC0 _SFR_MEM8(0x6A) -+#define POEN0A 0 -+#define POEN0B 2 -+#define PSYNC00 4 -+#define PSYNC01 5 -+#define PISEL0B1 6 -+#define PISEL0A1 7 -+ -+/* Reserved [0x6B] */ -+ -+#define PICR2L _SFR_MEM8(0x6C) -+ -+#define PICR2H _SFR_MEM8(0x6D) -+#define PICR28 0 -+#define PICR29 1 -+#define PICR210 2 -+#define PICR211 3 -+#define PCST2 7 -+ -+#define PSOC2 _SFR_MEM8(0x6E) -+#define POEN2A 0 -+#define POEN2C 1 -+#define POEN2B 2 -+#define POEN2D 3 -+#define PSYNC20 4 -+#define PSYNC21 5 -+#define POS22 6 -+#define POS23 7 -+ -+#define POM2 _SFR_MEM8(0x6F) -+#define POMV2A0 0 -+#define POMV2A1 1 -+#define POMV2A2 2 -+#define POMV2A3 3 -+#define POMV2B0 4 -+#define POMV2B1 5 -+#define POMV2B2 6 -+#define POMV2B3 7 -+ -+#define PCNFE2 _SFR_MEM8(0x70) -+#define PISEL2B1 0 -+#define PISEL2A1 1 -+#define PELEV2B1 2 -+#define PELEV2A1 3 -+#define PBFM21 4 -+#define PASDLK20 5 -+#define PASDLK21 6 -+#define PASDLK22 7 -+ -+#define PASDLY2 _SFR_MEM8(0x71) -+ -+/* Reserved [0x72..0x75] */ -+ -+#define DACON _SFR_MEM8(0x76) -+#define DAEN 0 -+#define DALA 2 -+#define DATS0 4 -+#define DATS1 5 -+#define DATS2 6 -+#define DAATE 7 -+ -+#define DIDR0 _SFR_MEM8(0x77) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+#define ADC6D 6 -+#define ADC7D 7 -+ -+#define DIDR1 _SFR_MEM8(0x78) -+#define ADC9D 0 -+#define ADC10D 1 -+#define AMP0POSD 2 -+#define ACMP1MD 3 -+ -+#define AMP0CSR _SFR_MEM8(0x79) -+#define AMP0TS0 0 -+#define AMP0TS1 1 -+#define AMP0GS 3 -+#define AMP0G0 4 -+#define AMP0G1 5 -+#define AMP0IS 6 -+#define AMP0EN 7 -+ -+#define AC1ECON _SFR_MEM8(0x7A) -+#define AC1H0 0 -+#define AC1H1 1 -+#define AC1H2 2 -+#define AC1ICE 3 -+#define AC1OE 4 -+#define AC1OI 5 -+ -+#define AC2ECON _SFR_MEM8(0x7B) -+#define AC2H0 0 -+#define AC2H1 1 -+#define AC2H2 2 -+#define AC2OE 4 -+#define AC2OI 5 -+ -+#define AC3ECON _SFR_MEM8(0x7C) -+#define AC3H0 0 -+#define AC3H1 1 -+#define AC3H2 2 -+#define AC3OE 4 -+#define AC3OI 5 -+ -+#define AC1CON _SFR_MEM8(0x7D) -+#define AC1M0 0 -+#define AC1M1 1 -+#define AC1M2 2 -+#define AC1IS0 4 -+#define AC1IS1 5 -+#define AC1IE 6 -+#define AC1EN 7 -+ -+#define AC2CON _SFR_MEM8(0x7E) -+#define AC2M0 0 -+#define AC2M1 1 -+#define AC2M2 2 -+#define AC2IS0 4 -+#define AC2IS1 5 -+#define AC2IE 6 -+#define AC2EN 7 -+ -+#define AC3CON _SFR_MEM8(0x7F) -+#define AC3M0 0 -+#define AC3M1 1 -+#define AC3M2 2 -+#define AC3OEA 3 -+#define AC3IS0 4 -+#define AC3IS1 5 -+#define AC3IE 6 -+#define AC3EN 7 -+ -+#define BGCRR _SFR_MEM8(0x80) -+#define BGCR0 0 -+#define BGCR1 1 -+#define BGCR2 2 -+#define BGCR3 3 -+ -+#define BGCCR _SFR_MEM8(0x81) -+#define BGCC0 0 -+#define BGCC1 1 -+#define BGCC2 2 -+#define BGCC3 3 -+ -+#define WDTCSR _SFR_MEM8(0x82) -+#define WDE 3 -+#define WDCE 4 -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDP3 5 -+#define WDIE 6 -+#define WDIF 7 -+ -+#define CLKPR _SFR_MEM8(0x83) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+#define CLKPCE 7 -+ -+#define CLKCSR _SFR_MEM8(0x84) -+#define CLKC0 0 -+#define CLKC1 1 -+#define CLKC2 2 -+#define CLKC3 3 -+#define CLKRDY 4 -+#define CLKCCE 7 -+ -+#define CLKSELR _SFR_MEM8(0x85) -+#define CKSEL0 0 -+#define CKSEL1 1 -+#define CKSEL2 2 -+#define CKSEL3 3 -+#define CSUT0 4 -+#define CSUT1 5 -+#define COUT 6 -+ -+#define PRR _SFR_MEM8(0x86) -+#define PRADC 0 -+#define PRSPI 2 -+#define PRTIM1 4 -+#define PRPSCR 5 -+#define PRPSC2 7 -+ -+#define PLLCSR _SFR_MEM8(0x87) -+#define PLOCK 0 -+#define PLLE 1 -+#define PLLF0 2 -+#define PLLF1 3 -+#define PLLF2 4 -+#define PLLF3 5 -+ -+#define OSCCAL _SFR_MEM8(0x88) -+#define OSCCAL0 0 -+#define OSCCAL1 1 -+#define OSCCAL2 2 -+#define OSCCAL3 3 -+#define OSCCAL4 4 -+#define OSCCAL5 5 -+#define OSCCAL6 6 -+#define OSCCAL7 7 -+ -+#define EICRA _SFR_MEM8(0x89) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+#define ISC20 4 -+#define ISC21 5 -+ -+#define TCCR1B _SFR_MEM8(0x8A) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+/* Reserved [0x8B] */ -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x8C) -+ -+#define ICR1L _SFR_MEM8(0x8C) -+#define ICR1H _SFR_MEM8(0x8D) -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* PSC2 Capture Event */ -+#define PSC2_CAPT_vect _VECTOR(1) -+#define PSC2_CAPT_vect_num 1 -+ -+/* PSC2 End Cycle */ -+#define PSC2_EC_vect _VECTOR(2) -+#define PSC2_EC_vect_num 2 -+ -+/* PSC2 End Of Enhanced Cycle */ -+#define PSC2_EEC_vect _VECTOR(3) -+#define PSC2_EEC_vect_num 3 -+ -+/* PSC0 Capture Event */ -+#define PSC0_CAPT_vect _VECTOR(4) -+#define PSC0_CAPT_vect_num 4 -+ -+/* PSC0 End Cycle */ -+#define PSC0_EC_vect _VECTOR(5) -+#define PSC0_EC_vect_num 5 -+ -+/* PSC0 End Of Enhanced Cycle */ -+#define PSC0_EEC_vect _VECTOR(6) -+#define PSC0_EEC_vect_num 6 -+ -+/* Analog Comparator 1 */ -+#define ANALOG_COMP_1_vect _VECTOR(7) -+#define ANALOG_COMP_1_vect_num 7 -+ -+/* Analog Comparator 2 */ -+#define ANALOG_COMP_2_vect _VECTOR(8) -+#define ANALOG_COMP_2_vect_num 8 -+ -+/* Analog Comparator 3 */ -+#define ANALOG_COMP_3_vect _VECTOR(9) -+#define ANALOG_COMP_3_vect_num 9 -+ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(10) -+#define INT0_vect_num 10 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(11) -+#define TIMER1_CAPT_vect_num 11 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(12) -+#define TIMER1_OVF_vect_num 12 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(13) -+#define ADC_vect_num 13 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(14) -+#define INT1_vect_num 14 -+ -+/* SPI Serial Transfer Complet */ -+#define SPI_STC_vect _VECTOR(15) -+#define SPI_STC_vect_num 15 -+ -+/* External Interrupt Request 2 */ -+#define INT2_vect _VECTOR(16) -+#define INT2_vect_num 16 -+ -+/* Watchdog Timeout Interrupt */ -+#define WDT_vect _VECTOR(17) -+#define WDT_vect_num 17 -+ -+/* EEPROM Ready */ -+#define EE_READY_vect _VECTOR(18) -+#define EE_READY_vect_num 18 -+ -+/* Store Program Memory Read */ -+#define SPM_READY_vect _VECTOR(19) -+#define SPM_READY_vect_num 19 -+ -+#define _VECTORS_SIZE 80 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 128 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x3FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 1024 -+#define RAMEND 0x04FF -+#define E2START 0 -+#define E2SIZE 512 -+#define E2PAGESIZE 4 -+#define E2END 0x01FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -+#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_DWEN (unsigned char)~_BV(6) -+#define FUSE_RSTDISBL (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -+#define FUSE_PSCINRB (unsigned char)~_BV(3) -+#define FUSE_PSCRV (unsigned char)~_BV(4) -+#define FUSE_PSC0RB (unsigned char)~_BV(5) -+#define FUSE_PSC2RBA (unsigned char)~_BV(6) -+#define FUSE_PSC2RB (unsigned char)~_BV(7) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x94 -+#define SIGNATURE_2 0x8B -+ -+ -+#endif /* #ifdef _AVR_AT90PWM161_H_INCLUDED */ -+ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_AT90PWM161_H_INCLUDED ++#define _AVR_AT90PWM161_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "io90pwm161.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define ACSR _SFR_IO8(0x00) ++#define AC1O 1 ++#define AC2O 2 ++#define AC3O 3 ++#define AC1IF 5 ++#define AC2IF 6 ++#define AC3IF 7 ++ ++#define TIMSK1 _SFR_IO8(0x01) ++#define TOIE1 0 ++#define ICIE1 5 ++ ++#define TIFR1 _SFR_IO8(0x02) ++#define TOV1 0 ++#define ICF1 5 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define ADCSRA _SFR_IO8(0x06) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_IO8(0x07) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ADTS3 3 ++#define ADSSEN 4 ++#define ADNCDIS 6 ++#define ADHSM 7 ++ ++#define ADMUX _SFR_IO8(0x08) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDRE2 2 ++#define DDRE1 1 ++#define DDRE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE2 2 ++#define PORTE1 1 ++#define PORTE0 0 ++ ++#define PIM0 _SFR_IO8(0x0F) ++#define PEOPE0 0 ++#define PEOEPE0 1 ++#define PEVE0A 3 ++#define PEVE0B 4 ++ ++#define PIFR0 _SFR_IO8(0x10) ++#define PEOP0 0 ++#define PRN00 1 ++#define PRN01 2 ++#define PEV0A 3 ++#define PEV0B 4 ++#define POAC0A 6 ++#define POAC0B 7 ++ ++#define PCNF0 _SFR_IO8(0x11) ++#define PCLKSEL0 1 ++#define POP0 2 ++#define PMODE00 3 ++#define PMODE01 4 ++#define PLOCK0 5 ++#define PALOCK0 6 ++#define PFIFTY0 7 ++ ++#define PCTL0 _SFR_IO8(0x12) ++#define PRUN0 0 ++#define PCCYC0 1 ++#define PAOC0A 3 ++#define PAOC0B 4 ++#define PBFM00 2 ++#define PBFM01 5 ++#define PPRE00 6 ++#define PPRE01 7 ++ ++#define PIM2 _SFR_IO8(0x13) ++#define PEOPE2 0 ++#define PEOEPE2 1 ++#define PEVE2A 3 ++#define PEVE2B 4 ++#define PSEIE2 5 ++ ++#define PIFR2 _SFR_IO8(0x14) ++#define PEOP2 0 ++#define PRN20 1 ++#define PRN21 2 ++#define PEV2A 3 ++#define PEV2B 4 ++#define PSEI2 5 ++#define POAC2A 6 ++#define POAC2B 7 ++ ++#define PCNF2 _SFR_IO8(0x15) ++#define POME2 0 ++#define PCLKSEL2 1 ++#define POP2 2 ++#define PMODE20 3 ++#define PMODE21 4 ++#define PLOCK2 5 ++#define PALOCK2 6 ++#define PFIFTY2 7 ++ ++#define PCTL2 _SFR_IO8(0x16) ++#define PRUN2 0 ++#define PCCYC2 1 ++#define PARUN2 2 ++#define PAOC2A 3 ++#define PAOC2B 4 ++#define PBFM2 5 ++#define PPRE20 6 ++#define PPRE21 7 ++ ++#define SPCR _SFR_IO8(0x17) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x18) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define GPIOR0 _SFR_IO8(0x19) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define GPIOR1 _SFR_IO8(0x1A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x1B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define EECR _SFR_IO8(0x1C) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++#define EEPAGE 6 ++#define NVMBSY 7 ++ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x1E) ++ ++#define EEARL _SFR_IO8(0x1E) ++#define EEARH _SFR_IO8(0x1F) ++ ++#define EIFR _SFR_IO8(0x20) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++ ++#define EIMSK _SFR_IO8(0x21) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++ ++/* Combine OCR0SBL and OCR0SBH */ ++#define OCR0SB _SFR_IO16(0x22) ++ ++#define OCR0SBL _SFR_IO8(0x22) ++#define OCR0SBH _SFR_IO8(0x23) ++ ++/* Combine OCR0RBL and OCR0RBH */ ++#define OCR0RB _SFR_IO16(0x24) ++ ++#define OCR0RBL _SFR_IO8(0x24) ++#define OCR0RBH _SFR_IO8(0x25) ++ ++/* Combine OCR2SBL and OCR2SBH */ ++#define OCR2SB _SFR_IO16(0x26) ++ ++#define OCR2SBL _SFR_IO8(0x26) ++#define OCR2SBH _SFR_IO8(0x27) ++ ++/* Combine OCR2RBL and OCR2RBH */ ++#define OCR2RB _SFR_IO16(0x28) ++ ++#define OCR2RBL _SFR_IO8(0x28) ++#define OCR2RBH _SFR_IO8(0x29) ++ ++/* Combine OCR0RAL and OCR0RAH */ ++#define OCR0RA _SFR_IO16(0x2A) ++ ++#define OCR0RAL _SFR_IO8(0x2A) ++#define OCR0RAH _SFR_IO8(0x2B) ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x2C) ++#endif ++#define ADCW _SFR_IO16(0x2C) ++ ++#define ADCL _SFR_IO8(0x2C) ++#define ADCH _SFR_IO8(0x2D) ++ ++/* Combine OCR2RAL and OCR2RAH */ ++#define OCR2RA _SFR_IO16(0x2E) ++ ++#define OCR2RAL _SFR_IO8(0x2E) ++#define OCR2RAH _SFR_IO8(0x2F) ++ ++/* Reserved [0x30..0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define CKRC81 2 ++#define RSTDIS 3 ++#define PUD 4 ++ ++#define SPDR _SFR_IO8(0x36) ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define DACL _SFR_IO8(0x38) ++#define DACL0 0 ++#define DACL1 1 ++#define DACL2 2 ++#define DACL3 3 ++#define DACL4 4 ++#define DACL5 5 ++#define DACL6 6 ++#define DACL7 7 ++ ++#define DACH _SFR_IO8(0x39) ++#define DACH0 0 ++#define DACH1 1 ++#define DACH2 2 ++#define DACH3 3 ++#define DACH4 4 ++#define DACH5 5 ++#define DACH6 6 ++#define DACH7 7 ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_IO16(0x3A) ++ ++#define TCNT1L _SFR_IO8(0x3A) ++#define TCNT1H _SFR_IO8(0x3B) ++ ++/* Reserved [0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++/* Combine OCR0SAL and OCR0SAH */ ++#define OCR0SA _SFR_MEM16(0x60) ++ ++#define OCR0SAL _SFR_MEM8(0x60) ++#define OCR0SAH _SFR_MEM8(0x61) ++ ++#define PFRC0A _SFR_MEM8(0x62) ++#define PRFM0A0 0 ++#define PRFM0A1 1 ++#define PRFM0A2 2 ++#define PRFM0A3 3 ++#define PFLTE0A 4 ++#define PELEV0A 5 ++#define PISEL0A 6 ++#define PCAE0A 7 ++ ++#define PFRC0B _SFR_MEM8(0x63) ++#define PRFM0B0 0 ++#define PRFM0B1 1 ++#define PRFM0B2 2 ++#define PRFM0B3 3 ++#define PFLTE0B 4 ++#define PELEV0B 5 ++#define PISEL0B 6 ++#define PCAE0B 7 ++ ++/* Combine OCR2SAL and OCR2SAH */ ++#define OCR2SA _SFR_MEM16(0x64) ++ ++#define OCR2SAL _SFR_MEM8(0x64) ++#define OCR2SAH _SFR_MEM8(0x65) ++ ++#define PFRC2A _SFR_MEM8(0x66) ++#define PRFM2A0 0 ++#define PRFM2A1 1 ++#define PRFM2A2 2 ++#define PRFM2A3 3 ++#define PFLTE2A 4 ++#define PELEV2A 5 ++#define PISEL2A 6 ++#define PCAE2A 7 ++ ++#define PFRC2B _SFR_MEM8(0x67) ++#define PRFM2B0 0 ++#define PRFM2B1 1 ++#define PRFM2B2 2 ++#define PRFM2B3 3 ++#define PFLTE2B 4 ++#define PELEV2B 5 ++#define PISEL2B 6 ++#define PCAE2B 7 ++ ++/* Combine PICR0L and PICR0H */ ++#define PICR0 _SFR_MEM16(0x68) ++ ++#define PICR0L _SFR_MEM8(0x68) ++#define PICR0H _SFR_MEM8(0x69) ++ ++#define PSOC0 _SFR_MEM8(0x6A) ++#define POEN0A 0 ++#define POEN0B 2 ++#define PSYNC00 4 ++#define PSYNC01 5 ++#define PISEL0B1 6 ++#define PISEL0A1 7 ++ ++/* Reserved [0x6B] */ ++ ++#define PICR2L _SFR_MEM8(0x6C) ++ ++#define PICR2H _SFR_MEM8(0x6D) ++#define PICR28 0 ++#define PICR29 1 ++#define PICR210 2 ++#define PICR211 3 ++#define PCST2 7 ++ ++#define PSOC2 _SFR_MEM8(0x6E) ++#define POEN2A 0 ++#define POEN2C 1 ++#define POEN2B 2 ++#define POEN2D 3 ++#define PSYNC20 4 ++#define PSYNC21 5 ++#define POS22 6 ++#define POS23 7 ++ ++#define POM2 _SFR_MEM8(0x6F) ++#define POMV2A0 0 ++#define POMV2A1 1 ++#define POMV2A2 2 ++#define POMV2A3 3 ++#define POMV2B0 4 ++#define POMV2B1 5 ++#define POMV2B2 6 ++#define POMV2B3 7 ++ ++#define PCNFE2 _SFR_MEM8(0x70) ++#define PISEL2B1 0 ++#define PISEL2A1 1 ++#define PELEV2B1 2 ++#define PELEV2A1 3 ++#define PBFM21 4 ++#define PASDLK20 5 ++#define PASDLK21 6 ++#define PASDLK22 7 ++ ++#define PASDLY2 _SFR_MEM8(0x71) ++ ++/* Reserved [0x72..0x75] */ ++ ++#define DACON _SFR_MEM8(0x76) ++#define DAEN 0 ++#define DALA 2 ++#define DATS0 4 ++#define DATS1 5 ++#define DATS2 6 ++#define DAATE 7 ++ ++#define DIDR0 _SFR_MEM8(0x77) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x78) ++#define ADC9D 0 ++#define ADC10D 1 ++#define AMP0POSD 2 ++#define ACMP1MD 3 ++ ++#define AMP0CSR _SFR_MEM8(0x79) ++#define AMP0TS0 0 ++#define AMP0TS1 1 ++#define AMP0GS 3 ++#define AMP0G0 4 ++#define AMP0G1 5 ++#define AMP0IS 6 ++#define AMP0EN 7 ++ ++#define AC1ECON _SFR_MEM8(0x7A) ++#define AC1H0 0 ++#define AC1H1 1 ++#define AC1H2 2 ++#define AC1ICE 3 ++#define AC1OE 4 ++#define AC1OI 5 ++ ++#define AC2ECON _SFR_MEM8(0x7B) ++#define AC2H0 0 ++#define AC2H1 1 ++#define AC2H2 2 ++#define AC2OE 4 ++#define AC2OI 5 ++ ++#define AC3ECON _SFR_MEM8(0x7C) ++#define AC3H0 0 ++#define AC3H1 1 ++#define AC3H2 2 ++#define AC3OE 4 ++#define AC3OI 5 ++ ++#define AC1CON _SFR_MEM8(0x7D) ++#define AC1M0 0 ++#define AC1M1 1 ++#define AC1M2 2 ++#define AC1IS0 4 ++#define AC1IS1 5 ++#define AC1IE 6 ++#define AC1EN 7 ++ ++#define AC2CON _SFR_MEM8(0x7E) ++#define AC2M0 0 ++#define AC2M1 1 ++#define AC2M2 2 ++#define AC2IS0 4 ++#define AC2IS1 5 ++#define AC2IE 6 ++#define AC2EN 7 ++ ++#define AC3CON _SFR_MEM8(0x7F) ++#define AC3M0 0 ++#define AC3M1 1 ++#define AC3M2 2 ++#define AC3OEA 3 ++#define AC3IS0 4 ++#define AC3IS1 5 ++#define AC3IE 6 ++#define AC3EN 7 ++ ++#define BGCRR _SFR_MEM8(0x80) ++#define BGCR0 0 ++#define BGCR1 1 ++#define BGCR2 2 ++#define BGCR3 3 ++ ++#define BGCCR _SFR_MEM8(0x81) ++#define BGCC0 0 ++#define BGCC1 1 ++#define BGCC2 2 ++#define BGCC3 3 ++ ++#define WDTCSR _SFR_MEM8(0x82) ++#define WDE 3 ++#define WDCE 4 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x83) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define CLKCSR _SFR_MEM8(0x84) ++#define CLKC0 0 ++#define CLKC1 1 ++#define CLKC2 2 ++#define CLKC3 3 ++#define CLKRDY 4 ++#define CLKCCE 7 ++ ++#define CLKSELR _SFR_MEM8(0x85) ++#define CKSEL0 0 ++#define CKSEL1 1 ++#define CKSEL2 2 ++#define CKSEL3 3 ++#define CSUT0 4 ++#define CSUT1 5 ++#define COUT 6 ++ ++#define PRR _SFR_MEM8(0x86) ++#define PRADC 0 ++#define PRSPI 2 ++#define PRTIM1 4 ++#define PRPSCR 5 ++#define PRPSC2 7 ++ ++#define PLLCSR _SFR_MEM8(0x87) ++#define PLOCK 0 ++#define PLLE 1 ++#define PLLF0 2 ++#define PLLF1 3 ++#define PLLF2 4 ++#define PLLF3 5 ++ ++#define OSCCAL _SFR_MEM8(0x88) ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++#define EICRA _SFR_MEM8(0x89) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++ ++#define TCCR1B _SFR_MEM8(0x8A) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++/* Reserved [0x8B] */ ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x8C) ++ ++#define ICR1L _SFR_MEM8(0x8C) ++#define ICR1H _SFR_MEM8(0x8D) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* PSC2 Capture Event */ ++#define PSC2_CAPT_vect _VECTOR(1) ++#define PSC2_CAPT_vect_num 1 ++ ++/* PSC2 End Cycle */ ++#define PSC2_EC_vect _VECTOR(2) ++#define PSC2_EC_vect_num 2 ++ ++/* PSC2 End Of Enhanced Cycle */ ++#define PSC2_EEC_vect _VECTOR(3) ++#define PSC2_EEC_vect_num 3 ++ ++/* PSC0 Capture Event */ ++#define PSC0_CAPT_vect _VECTOR(4) ++#define PSC0_CAPT_vect_num 4 ++ ++/* PSC0 End Cycle */ ++#define PSC0_EC_vect _VECTOR(5) ++#define PSC0_EC_vect_num 5 ++ ++/* PSC0 End Of Enhanced Cycle */ ++#define PSC0_EEC_vect _VECTOR(6) ++#define PSC0_EEC_vect_num 6 ++ ++/* Analog Comparator 1 */ ++#define ANALOG_COMP_1_vect _VECTOR(7) ++#define ANALOG_COMP_1_vect_num 7 ++ ++/* Analog Comparator 2 */ ++#define ANALOG_COMP_2_vect _VECTOR(8) ++#define ANALOG_COMP_2_vect_num 8 ++ ++/* Analog Comparator 3 */ ++#define ANALOG_COMP_3_vect _VECTOR(9) ++#define ANALOG_COMP_3_vect_num 9 ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(10) ++#define INT0_vect_num 10 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(11) ++#define TIMER1_CAPT_vect_num 11 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(12) ++#define TIMER1_OVF_vect_num 12 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(13) ++#define ADC_vect_num 13 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(14) ++#define INT1_vect_num 14 ++ ++/* SPI Serial Transfer Complet */ ++#define SPI_STC_vect _VECTOR(15) ++#define SPI_STC_vect_num 15 ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect _VECTOR(16) ++#define INT2_vect_num 16 ++ ++/* Watchdog Timeout Interrupt */ ++#define WDT_vect _VECTOR(17) ++#define WDT_vect_num 17 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(18) ++#define EE_READY_vect_num 18 ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect _VECTOR(19) ++#define SPM_READY_vect_num 19 ++ ++#define _VECTORS_SIZE 80 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 128 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x3FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 1024 ++#define RAMEND 0x04FF ++#define E2START 0 ++#define E2SIZE 512 ++#define E2PAGESIZE 4 ++#define E2END 0x01FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_PSCINRB (unsigned char)~_BV(3) ++#define FUSE_PSCRV (unsigned char)~_BV(4) ++#define FUSE_PSC0RB (unsigned char)~_BV(5) ++#define FUSE_PSC2RBA (unsigned char)~_BV(6) ++#define FUSE_PSC2RB (unsigned char)~_BV(7) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x8B ++ ++ ++#endif /* #ifdef _AVR_AT90PWM161_H_INCLUDED */ ++ diff --git a/include/avr/io90pwm216.h b/include/avr/io90pwm216.h -index 543ccec..166297a 100644 +index 543ccec..edcba00 100644 --- a/include/avr/io90pwm216.h +++ b/include/avr/io90pwm216.h -@@ -434,7 +434,7 @@ - /* Power Reduction Register */ - #define PRR _SFR_MEM8(0x64) - #define PRADC 0 /* Power Reduction ADC */ +@@ -1,1209 +1,1210 @@ +-/* Copyright (c) 2007, Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: io90pwm216.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* avr/io90pwm216.h - definitions for AT90PWM216 */ +- +-#ifndef _AVR_IO90PWM216_H_ +-#define _AVR_IO90PWM216_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "io90pwm216.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* Port B Input Pins Address */ +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-/* Port B Data Direction Register */ +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-/* Port B Data Register */ +-#define PORTB _SFR_IO8(0x05) +-#define PB0 0 +-#define PB1 1 +-#define PB2 2 +-#define PB3 3 +-#define PB4 4 +-#define PB5 5 +-#define PB6 6 +-#define PB7 7 +- +-/* Port C Input Pins Address */ +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +-#define PINC7 7 +- +-/* Port C Data Direction Register */ +-#define DDRC _SFR_IO8(0x07) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC3 3 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +-#define DDC7 7 +- +-/* Port C Data Register */ +-#define PORTC _SFR_IO8(0x08) +-#define PC0 0 +-#define PC1 1 +-#define PC2 2 +-#define PC3 3 +-#define PC4 4 +-#define PC5 5 +-#define PC6 6 +-#define PC7 7 +- +-/* Port D Input Pins Address */ +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-/* Port D Data Direction Register */ +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-/* Port D Data Register */ +-#define PORTD _SFR_IO8(0x0B) +-#define PD0 0 +-#define PD1 1 +-#define PD2 2 +-#define PD3 3 +-#define PD4 4 +-#define PD5 5 +-#define PD6 6 +-#define PD7 7 +- +-/* Port E Input Pins Address */ +-#define PINE _SFR_IO8(0x0C) +-#define PINE0 0 +-#define PINE1 1 +-#define PINE2 2 +- +-/* Port E Data Direction Register */ +-#define DDRE _SFR_IO8(0x0D) +-#define DDE0 0 +-#define DDE1 1 +-#define DDE2 2 +- +-/* Port E Data Register */ +-#define PORTE _SFR_IO8(0x0E) +-#define PE0 0 +-#define PE1 1 +-#define PE2 2 +- +-/* Timer/Counter 0 Interrupt Flag Register */ +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 /* Overflow Flag */ +-#define OCF0A 1 /* Output Compare Flag 0A */ +-#define OCF0B 2 /* Output Compare Flag 0B */ +- +-/* Timer/Counter1 Interrupt Flag Register */ +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 /* Overflow Flag */ +-#define OCF1A 1 /* Output Compare Flag 1A*/ +-#define OCF1B 2 /* Output Compare Flag 1B*/ +-#define ICF1 5 /* Input Capture Flag 1 */ +- +-/* General Purpose I/O Register 1 */ +-#define GPIOR1 _SFR_IO8(0x19) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-/* General Purpose I/O Register 2 */ +-#define GPIOR2 _SFR_IO8(0x1A) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-/* General Purpose I/O Register 3 */ +-#define GPIOR3 _SFR_IO8(0x1B) +-#define GPIOR30 0 +-#define GPIOR31 1 +-#define GPIOR32 2 +-#define GPIOR33 3 +-#define GPIOR34 4 +-#define GPIOR35 5 +-#define GPIOR36 6 +-#define GPIOR37 7 +- +-/* External Interrupt Flag Register */ +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +-#define INTF2 2 +-#define INTF3 3 +- +-/* External Interrupt Mask Register */ +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 /* External Interrupt Request 0 Enable */ +-#define INT1 1 /* External Interrupt Request 1 Enable */ +-#define INT2 2 /* External Interrupt Request 2 Enable */ +-#define INT3 3 /* External Interrupt Request 3 Enable */ +- +-/* General Purpose I/O Register 0 */ +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 /* EEPROM Read Enable */ +-#define EEWE 1 /* EEPROM Write Enable */ +-#define EEMWE 2 /* EEPROM Master Write Enable */ +-#define EERIE 3 /* EEPROM Ready Interrupt Enable */ +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-/* The EEPROM Address Registers */ +-#define EEAR _SFR_IO16(0x21) +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +-#define EEAR9 1 +-#define EEAR10 2 +-#define EEAR11 3 +- +-/* 6-char sequence denoting where to find the EEPROM registers in memory space. +- Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM +- subroutines. +- First two letters: EECR address. +- Second two letters: EEDR address. +- Last two letters: EEAR address. */ +-#define __EEPROM_REG_LOCATIONS__ 1F2021 +- +-/* General Timer/Counter Control Register */ +-#define GTCCR _SFR_IO8(0x23) +-#define PSR10 0 /* Prescaler Reset Timer/Counter1 and Timer/Counter0 */ +-#define ICPSEL1 6 /* Timer1 Input Capture Selection Bit */ +-#define TSM 7 /* Timer/Counter Synchronization Mode */ +- +-/* Timer/Counter Control Register A */ +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 /* Waveform Generation Mode */ +-#define WGM01 1 /* Waveform Generation Mode */ +-#define COM0B0 4 /* Compare Output Mode, Fast PWm */ +-#define COM0B1 5 /* Compare Output Mode, Fast PWm */ +-#define COM0A0 6 /* Compare Output Mode, Phase Correct PWM Mode */ +-#define COM0A1 7 /* Compare Output Mode, Phase Correct PWM Mode */ +- +-/* Timer/Counter Control Register B */ +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 /* Clock Select */ +-#define CS01 1 /* Clock Select */ +-#define CS02 2 /* Clock Select */ +-#define WGM02 3 /* Waveform Generation Mode */ +-#define FOC0B 6 /* Force Output Compare B */ +-#define FOC0A 7 /* Force Output Compare A */ +- +-/* Timer/Counter0 Register */ +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT00 0 +-#define TCNT01 1 +-#define TCNT02 2 +-#define TCNT03 3 +-#define TCNT04 4 +-#define TCNT05 5 +-#define TCNT06 6 +-#define TCNT07 7 +- +-/* Timer/Counter0 Output Compare Register A */ +-#define OCR0A _SFR_IO8(0x27) +-#define OCR0A0 0 +-#define OCR0A1 1 +-#define OCR0A2 2 +-#define OCR0A3 3 +-#define OCR0A4 4 +-#define OCR0A5 5 +-#define OCR0A6 6 +-#define OCR0A7 7 +- +-/* Timer/Counter0 Output Compare Register B */ +-#define OCR0B _SFR_IO8(0x28) +-#define OCR0B0 0 +-#define OCR0B1 1 +-#define OCR0B2 2 +-#define OCR0B3 3 +-#define OCR0B4 4 +-#define OCR0B5 5 +-#define OCR0B6 6 +-#define OCR0B7 7 +- +-/* PLL Control and Status Register */ +-#define PLLCSR _SFR_IO8(0x29) +-#define PLOCK 0 /* PLL Lock Detector */ +-#define PLLE 1 /* PLL Enable */ +-#define PLLF 2 /* PLL Factor */ +- +-/* SPI Control Register */ +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 /* SPI Clock Rate Select 0 */ +-#define SPR1 1 /* SPI Clock Rate Select 1 */ +-#define CPHA 2 /* Clock Phase */ +-#define CPOL 3 /* Clock polarity */ +-#define MSTR 4 /* Master/Slave Select */ +-#define DORD 5 /* Data Order */ +-#define SPE 6 /* SPI Enable */ +-#define SPIE 7 /* SPI Interrupt Enable */ +- +-/* SPI Status Register */ +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 /* Double SPI Speed Bit */ +-#define WCOL 6 /* Write Collision Flag */ +-#define SPIF 7 /* SPI Interrupt Flag */ +- +-/* SPI Data Register */ +-#define SPDR _SFR_IO8(0x2E) +-#define SPD0 0 +-#define SPD1 1 +-#define SPD2 2 +-#define SPD3 3 +-#define SPD4 4 +-#define SPD5 5 +-#define SPD6 6 +-#define SPD7 7 +- +-/* Analog Comparator Status Register */ +-#define ACSR _SFR_IO8(0x30) +-#define AC0O 0 /* Analog Comparator 0 Output Bit */ +-#define AC1O 1 /* Analog Comparator 1 Output Bit */ +-#define AC2O 2 /* Analog Comparator 2 Output Bit */ +-#define AC0IF 4 /* Analog Comparator 0 Interrupt Flag Bit */ +-#define AC1IF 5 /* Analog Comparator 1 Interrupt Flag Bit */ +-#define AC2IF 6 /* Analog Comparator 2 Interrupt Flag Bit */ +-#define ACCKDIV 7 /* Analog Comparator Clock Divider */ +- +-/* Sleep Mode Control Register */ +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 /* Sleep Enable */ +-#define SM0 1 /* Sleep Mode Select bit0 */ +-#define SM1 2 /* Sleep Mode Select bit1 */ +-#define SM2 3 /* Sleep Mode Select bit2 */ +- +-/* MCU Status Register */ +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 /* Power-on reset flag */ +-#define EXTRF 1 /* External Reset Flag */ +-#define BORF 2 /* Brown-out Reset Flag */ +-#define WDRF 3 /* Watchdog Reset Flag */ +- +-/* MCU Control Register */ +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 /* Interrupt Vector Change Enable */ +-#define IVSEL 1 /* Interrupt Vector Select */ +-#define PUD 4 /* Pull-up disable */ +-#define SPIPS 7 /* SPI Pin Select */ +- +-/* Store Program Memory Control Register */ +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 /* Store Program Memory Enable */ +-#define PGERS 1 /* Page Erase */ +-#define PGWRT 2 /* Page Write */ +-#define BLBSET 3 /* Boot Lock Bit Set */ +-#define RWWSRE 4 /* Read While Write section read enable */ +-#define RWWSB 6 /* Read While Write Section Busy */ +-#define SPMIE 7 /* SPM Interrupt Enable */ +- +-/* Watchdog Timer Control Register */ +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 /* Watchdog Timer Prescaler bit0 */ +-#define WDP1 1 /* Watchdog Timer Prescaler bit1 */ +-#define WDP2 2 /* Watchdog Timer Prescaler bit2 */ +-#define WDE 3 /* Watchdog Enable */ +-#define WDCE 4 /* Watchdog Change Enable */ +-#define WDP3 5 /* Watchdog Timer Prescaler bit3 */ +-#define WDIE 6 /* Watchdog Timeout Interrupt Enable */ +-#define WDIF 7 /* Watchdog Timeout Interrupt Flag */ +- +-/* Clock Prescaler Register */ +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 /* Clock Prescaler Select bit0 */ +-#define CLKPS1 1 /* Clock Prescaler Select bit1 */ +-#define CLKPS2 2 /* Clock Prescaler Select bit2 */ +-#define CLKPS3 3 /* Clock Prescaler Select bit3 */ +-#define CLKPCE 7 /* Clock Prescaler Change Enable */ +- +-/* Power Reduction Register */ +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 /* Power Reduction ADC */ -#define PRUSART 1 /* Power Reduction USART */ -+#define PRUSART0 1 /* Power Reduction USART0 */ - #define PRSPI 2 /* Power Reduction Serial Peripheral Interface */ - #define PRTIM0 3 /* Power Reduction Timer/Counter0 */ - #define PRTIM1 4 /* Power Reduction Timer/Counter1 */ -diff --git a/include/avr/io90pwm316.h b/include/avr/io90pwm316.h -index ae0dda0..92ea20e 100644 ---- a/include/avr/io90pwm316.h -+++ b/include/avr/io90pwm316.h -@@ -434,7 +434,7 @@ - /* Power Reduction Register */ - #define PRR _SFR_MEM8(0x64) - #define PRADC 0 /* Power Reduction ADC */ --#define PRUSART 1 /* Power Reduction USART */ -+#define PRUSART0 1 /* Power Reduction USART0 */ - #define PRSPI 2 /* Power Reduction Serial Peripheral Interface */ - #define PRTIM0 3 /* Power Reduction Timer/Counter0 */ - #define PRTIM1 4 /* Power Reduction Timer/Counter1 */ -diff --git a/include/avr/io90pwmx.h b/include/avr/io90pwmx.h -index c0ce8e5..d953a19 100644 ---- a/include/avr/io90pwmx.h -+++ b/include/avr/io90pwmx.h -@@ -492,7 +492,7 @@ - #define PRTIM1 4 /* Power Reduction Timer/Counter1 */ - #define PRTIM0 3 /* Power Reduction Timer/Counter0 */ - #define PRSPI 2 /* Power Reduction Serial Peripheral Interface */ --#define PRUSART 1 /* Power Reduction USART */ -+#define PRUSART0 1 /* Power Reduction USART */ - #define PRADC 0 /* Power Reduction ADC */ - - /* Oscillator Calibration Value */ -diff --git a/include/avr/ioa5272.h b/include/avr/ioa5272.h -new file mode 100644 -index 0000000..d3fbb94 ---- /dev/null -+++ b/include/avr/ioa5272.h -@@ -0,0 +1,745 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATA5272_H_INCLUDED -+#define _AVR_ATA5272_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "ioa5272.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINA _SFR_IO8(0x00) -+#define PINA7 7 -+#define PINA6 6 -+#define PINA5 5 -+#define PINA4 4 -+#define PINA3 3 -+#define PINA2 2 -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x01) -+#define DDRA7 7 -+#define DDRA6 6 -+#define DDRA5 5 -+#define DDRA4 4 -+#define DDRA3 3 -+#define DDRA2 2 -+#define DDRA1 1 -+#define DDRA0 0 -+ -+#define PORTA _SFR_IO8(0x02) -+#define PORTA7 7 -+#define PORTA6 6 -+#define PORTA5 5 -+#define PORTA4 4 -+#define PORTA3 3 -+#define PORTA2 2 -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+/* Reserved [0x06..0x11] */ -+ -+#define PORTCR _SFR_IO8(0x12) -+ -+/* Reserved [0x13..0x14] */ -+ -+#define TIFR0 _SFR_IO8(0x15) -+#define TOV0 0 -+#define OCF0A 1 -+ -+#define TIFR1 _SFR_IO8(0x16) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define ICF1 5 -+ -+/* Reserved [0x17..0x1A] */ -+ -+#define PCIFR _SFR_IO8(0x1B) -+#define PCIF0 0 -+#define PCIF1 1 -+ -+#define EIFR _SFR_IO8(0x1C) -+#define INTF0 0 -+#define INTF1 1 -+ -+#define EIMSK _SFR_IO8(0x1D) -+#define INT0 0 -+#define INT1 1 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEPE 1 -+#define EEMPE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSR1 0 -+#define PSR0 1 -+#define TSM 7 -+ -+/* Reserved [0x24] */ -+ -+#define TCCR0A _SFR_IO8(0x25) -+#define WGM00 0 -+#define WGM01 1 -+#define COM0A0 6 -+#define COM0A1 7 -+ -+#define TCCR0B _SFR_IO8(0x26) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define FOC0A 7 -+ -+#define TCNT2 _SFR_IO8(0x27) -+ -+#define OCR0A _SFR_IO8(0x28) -+ -+/* Reserved [0x29] */ -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+/* Reserved [0x2F] */ -+ -+#define ACSR _SFR_IO8(0x30) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACIRS 6 -+#define ACD 7 -+ -+#define DWDR _SFR_IO8(0x31) -+ -+/* Reserved [0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define PUD 4 -+#define BODS 5 -+#define BODSE 6 -+ -+/* Reserved [0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define RFLB 3 -+#define CTPB 4 -+#define SIGRD 5 -+#define RWWSB 6 -+ -+/* Reserved [0x38..0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCR _SFR_MEM8(0x60) -+#define WDE 3 -+#define WDCE 4 -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDP3 5 -+#define WDIE 6 -+#define WDIF 7 -+ -+#define CLKPR _SFR_MEM8(0x61) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+#define CLKPCE 7 -+ -+#define CLKCSR _SFR_MEM8(0x62) -+#define CLKC0 0 -+#define CLKC1 1 -+#define CLKC2 2 -+#define CLKC3 3 -+#define CLKRDY 4 -+#define CLKCCE 7 -+ -+#define CLKSELR _SFR_MEM8(0x63) -+#define CSEL0 0 -+#define CSEL1 1 -+#define CSEL2 2 -+#define CSEL3 3 -+#define CSUT0 4 -+#define CSUT1 5 -+#define COUT 6 -+ -+#define PRR _SFR_MEM8(0x64) -+#define PRADC 0 -+#define PRUSI 1 -+#define PRTIM0 2 -+#define PRTIM1 3 -+#define PRSPI 4 -+#define PRLIN 5 -+ -+/* Reserved [0x65] */ -+ -+#define OSCCAL _SFR_MEM8(0x66) -+#define OSCCAL0 0 -+#define OSCCAL1 1 -+#define OSCCAL2 2 -+#define OSCCAL3 3 -+#define OSCCAL4 4 -+#define OSCCAL5 5 -+#define OSCCAL6 6 -+#define OSCCAL7 7 -+ -+/* Reserved [0x67] */ -+ -+#define PCICR _SFR_MEM8(0x68) -+#define PCIE0 0 -+#define PCIE1 1 -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+ -+/* Reserved [0x6A] */ -+ -+#define PCMSK0 _SFR_MEM8(0x6B) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6C) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+#define PCINT14 6 -+#define PCINT15 7 -+ -+/* Reserved [0x6D] */ -+ -+#define TIMSK0 _SFR_MEM8(0x6E) -+#define TOIE0 0 -+#define OCIE0A 1 -+ -+#define TIMSK1 _SFR_MEM8(0x6F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define ICIE1 5 -+ -+/* Reserved [0x70..0x76] */ -+ -+#define AMISCR _SFR_MEM8(0x77) -+#define XREFEN 1 -+#define AREFEN 2 -+#define ISRCEN 0 -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_MEM16(0x78) -+#endif -+#define ADCW _SFR_MEM16(0x78) -+ -+#define ADCL _SFR_MEM8(0x78) -+#define ADCH _SFR_MEM8(0x79) -+ -+#define ADCSRA _SFR_MEM8(0x7A) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADCSRB _SFR_MEM8(0x7B) -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+#define BIN 7 -+#define ACIR0 4 -+#define ACIR1 5 -+#define ACME 6 -+ -+#define ADMUX _SFR_MEM8(0x7C) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define MUX4 4 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+/* Reserved [0x7D] */ -+ -+#define DIDR0 _SFR_MEM8(0x7E) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+#define ADC6D 6 -+#define ADC7D 7 -+ -+#define DIDR1 _SFR_MEM8(0x7F) -+#define ADC8D 0 -+#define ADC9D 1 -+#define ADC10D 2 -+ -+#define TCCR1A _SFR_MEM8(0x80) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR1B _SFR_MEM8(0x81) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1C _SFR_MEM8(0x82) -+#define FOC1B 6 -+#define FOC1A 7 -+ -+#define TCCR1D _SFR_MEM8(0x83) -+#define OC1AU 0 -+#define OC1AV 1 -+#define OC1AW 2 -+#define OC1AX 3 -+#define OC1BU 4 -+#define OC1BV 5 -+#define OC1BW 6 -+#define OC1BX 7 -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x84) -+ -+#define TCNT1L _SFR_MEM8(0x84) -+#define TCNT1H _SFR_MEM8(0x85) -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x86) -+ -+#define ICR1L _SFR_MEM8(0x86) -+#define ICR1H _SFR_MEM8(0x87) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_MEM16(0x88) -+ -+#define OCR1AL _SFR_MEM8(0x88) -+#define OCR1AH _SFR_MEM8(0x89) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_MEM16(0x8A) -+ -+#define OCR1BL _SFR_MEM8(0x8A) -+#define OCR1BH _SFR_MEM8(0x8B) -+ -+/* Reserved [0x8C..0xB5] */ -+ -+#define ASSR _SFR_MEM8(0xB6) -+#define TCR0BUB 0 -+#define TCR0AUB 1 -+#define OCR0AUB 3 -+#define TCN0UB 4 -+#define AS0 5 -+#define EXCLK 6 -+ -+/* Reserved [0xB7] */ -+ -+#define USICR _SFR_MEM8(0xB8) -+#define USITC 0 -+#define USICLK 1 -+#define USICS0 2 -+#define USICS1 3 -+#define USIWM0 4 -+#define USIWM1 5 -+#define USIOIE 6 -+#define USISIE 7 -+ -+#define USISR _SFR_MEM8(0xB9) -+#define USICNT0 0 -+#define USICNT1 1 -+#define USICNT2 2 -+#define USICNT3 3 -+#define USIDC 4 -+#define USIPF 5 -+#define USIOIF 6 -+#define USISIF 7 -+ -+#define USIDR _SFR_MEM8(0xBA) -+ -+#define USIBR _SFR_MEM8(0xBB) -+ -+#define USIPP _SFR_MEM8(0xBC) -+ -+/* Reserved [0xBD..0xC7] */ -+ -+#define LINCR _SFR_MEM8(0xC8) -+#define LCMD0 0 -+#define LCMD1 1 -+#define LCMD2 2 -+#define LENA 3 -+#define LCONF0 4 -+#define LCONF1 5 -+#define LIN13 6 -+#define LSWRES 7 -+ -+#define LINSIR _SFR_MEM8(0xC9) -+#define LRXOK 0 -+#define LTXOK 1 -+#define LIDOK 2 -+#define LERR 3 -+#define LBUSY 4 -+#define LIDST0 5 -+#define LIDST1 6 -+#define LIDST2 7 -+ -+#define LINENIR _SFR_MEM8(0xCA) -+#define LENRXOK 0 -+#define LENTXOK 1 -+#define LENIDOK 2 -+#define LENERR 3 -+ -+#define LINERR _SFR_MEM8(0xCB) -+#define LBERR 0 -+#define LCERR 1 -+#define LPERR 2 -+#define LSERR 3 -+#define LFERR 4 -+#define LOVERR 5 -+#define LTOERR 6 -+#define LABORT 7 -+ -+#define LINBTR _SFR_MEM8(0xCC) -+#define LBT0 0 -+#define LBT1 1 -+#define LBT2 2 -+#define LBT3 3 -+#define LBT4 4 -+#define LBT5 5 -+#define LDISR 7 -+ -+#define LINBRRL _SFR_MEM8(0xCD) -+#define LDIV0 0 -+#define LDIV1 1 -+#define LDIV2 2 -+#define LDIV3 3 -+#define LDIV4 4 -+#define LDIV5 5 -+#define LDIV6 6 -+#define LDIV7 7 -+ -+#define LINBRRH _SFR_MEM8(0xCE) -+#define LDIV8 0 -+#define LDIV9 1 -+#define LDIV10 2 -+#define LDIV11 3 -+ -+#define LINDLR _SFR_MEM8(0xCF) -+#define LRXDL0 0 -+#define LRXDL1 1 -+#define LRXDL2 2 -+#define LRXDL3 3 -+#define LTXDL0 4 -+#define LTXDL1 5 -+#define LTXDL2 6 -+#define LTXDL3 7 -+ -+#define LINIDR _SFR_MEM8(0xD0) -+#define LID0 0 -+#define LID1 1 -+#define LID2 2 -+#define LID3 3 -+#define LID4 4 -+#define LID5 5 -+#define LP0 6 -+#define LP1 7 -+ -+#define LINSEL _SFR_MEM8(0xD1) -+#define LINDX0 0 -+#define LINDX1 1 -+#define LINDX2 2 -+#define LAINC 3 -+ -+#define LINDAT _SFR_MEM8(0xD2) -+#define LDATA0 0 -+#define LDATA1 1 -+#define LDATA2 2 -+#define LDATA3 3 -+#define LDATA4 4 -+#define LDATA5 5 -+#define LDATA6 6 -+#define LDATA7 7 -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(3) -+#define PCINT0_vect_num 3 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(4) -+#define PCINT1_vect_num 4 -+ -+/* Watchdog Time-Out Interrupt */ -+#define WDT_vect _VECTOR(5) -+#define WDT_vect_num 5 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(6) -+#define TIMER1_CAPT_vect_num 6 -+ -+/* Timer/Counter1 Compare Match 1A */ -+#define TIMER1_COMPA_vect _VECTOR(7) -+#define TIMER1_COMPA_vect_num 7 -+ -+/* Timer/Counter1 Compare Match 1B */ -+#define TIMER1_COMPB_vect _VECTOR(8) -+#define TIMER1_COMPB_vect_num 8 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(9) -+#define TIMER1_OVF_vect_num 9 -+ -+/* Timer/Counter0 Compare Match 0A */ -+#define TIMER0_COMPA_vect _VECTOR(10) -+#define TIMER0_COMPA_vect_num 10 -+ -+/* Timer/Counter0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(11) -+#define TIMER0_OVF_vect_num 11 -+ -+/* LIN Transfer Complete */ -+#define LIN_TC_vect _VECTOR(12) -+#define LIN_TC_vect_num 12 -+ -+/* LIN Error */ -+#define LIN_ERR_vect _VECTOR(13) -+#define LIN_ERR_vect_num 13 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(14) -+#define SPI_STC_vect_num 14 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(15) -+#define ADC_vect_num 15 -+ -+/* EEPROM Ready */ -+#define EE_RDY_vect _VECTOR(16) -+#define EE_RDY_vect_num 16 -+ -+/* USI Overflow */ -+#define USI_OVF_vect _VECTOR(19) -+#define USI_OVF_vect_num 19 -+ -+/* Analog Comparator */ -+#define ANA_COMP_vect _VECTOR(34) -+#define ANA_COMP_vect_num 34 -+ -+/* USI Start */ -+#define USI_START_vect _VECTOR(36) -+#define USI_START_vect_num 36 -+ -+#define _VECTORS_SIZE 74 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 128 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x1FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 512 -+#define RAMEND 0x02FF -+#define E2START 0 -+#define E2SIZE 512 -+#define E2PAGESIZE 4 -+#define E2END 0x01FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -+#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_DWEN (unsigned char)~_BV(6) -+#define FUSE_RSTDISBL (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_SELFPRGEN (unsigned char)~_BV(0) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x93 -+#define SIGNATURE_2 0x87 -+ -+ -+#endif /* #ifdef _AVR_ATA5272_H_INCLUDED */ -+ -diff --git a/include/avr/ioa5505.h b/include/avr/ioa5505.h -new file mode 100644 -index 0000000..19ede6a ---- /dev/null -+++ b/include/avr/ioa5505.h -@@ -0,0 +1,745 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATA5505_H_INCLUDED -+#define _AVR_ATA5505_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "ioa5505.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINA _SFR_IO8(0x00) -+#define PINA7 7 -+#define PINA6 6 -+#define PINA5 5 -+#define PINA4 4 -+#define PINA3 3 -+#define PINA2 2 -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x01) -+#define DDRA7 7 -+#define DDRA6 6 -+#define DDRA5 5 -+#define DDRA4 4 -+#define DDRA3 3 -+#define DDRA2 2 -+#define DDRA1 1 -+#define DDRA0 0 -+ -+#define PORTA _SFR_IO8(0x02) -+#define PORTA7 7 -+#define PORTA6 6 -+#define PORTA5 5 -+#define PORTA4 4 -+#define PORTA3 3 -+#define PORTA2 2 -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+/* Reserved [0x06..0x11] */ -+ -+#define PORTCR _SFR_IO8(0x12) -+ -+/* Reserved [0x13..0x14] */ -+ -+#define TIFR0 _SFR_IO8(0x15) -+#define TOV0 0 -+#define OCF0A 1 -+ -+#define TIFR1 _SFR_IO8(0x16) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define ICF1 5 -+ -+/* Reserved [0x17..0x1A] */ -+ -+#define PCIFR _SFR_IO8(0x1B) -+#define PCIF0 0 -+#define PCIF1 1 -+ -+#define EIFR _SFR_IO8(0x1C) -+#define INTF0 0 -+#define INTF1 1 -+ -+#define EIMSK _SFR_IO8(0x1D) -+#define INT0 0 -+#define INT1 1 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEPE 1 -+#define EEMPE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSR1 0 -+#define PSR0 1 -+#define TSM 7 -+ -+/* Reserved [0x24] */ -+ -+#define TCCR0A _SFR_IO8(0x25) -+#define WGM00 0 -+#define WGM01 1 -+#define COM0A0 6 -+#define COM0A1 7 -+ -+#define TCCR0B _SFR_IO8(0x26) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define FOC0A 7 -+ -+#define TCNT2 _SFR_IO8(0x27) -+ -+#define OCR0A _SFR_IO8(0x28) -+ -+/* Reserved [0x29] */ -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+/* Reserved [0x2F] */ -+ -+#define ACSR _SFR_IO8(0x30) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACIRS 6 -+#define ACD 7 -+ -+#define DWDR _SFR_IO8(0x31) -+ -+/* Reserved [0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define PUD 4 -+#define BODS 5 -+#define BODSE 6 -+ -+/* Reserved [0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define RFLB 3 -+#define CTPB 4 -+#define SIGRD 5 -+#define RWWSB 6 -+ -+/* Reserved [0x38..0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCR _SFR_MEM8(0x60) -+#define WDE 3 -+#define WDCE 4 -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDP3 5 -+#define WDIE 6 -+#define WDIF 7 -+ -+#define CLKPR _SFR_MEM8(0x61) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+#define CLKPCE 7 -+ -+#define CLKCSR _SFR_MEM8(0x62) -+#define CLKC0 0 -+#define CLKC1 1 -+#define CLKC2 2 -+#define CLKC3 3 -+#define CLKRDY 4 -+#define CLKCCE 7 -+ -+#define CLKSELR _SFR_MEM8(0x63) -+#define CSEL0 0 -+#define CSEL1 1 -+#define CSEL2 2 -+#define CSEL3 3 -+#define CSUT0 4 -+#define CSUT1 5 -+#define COUT 6 -+ -+#define PRR _SFR_MEM8(0x64) -+#define PRADC 0 -+#define PRUSI 1 -+#define PRTIM0 2 -+#define PRTIM1 3 -+#define PRSPI 4 -+#define PRLIN 5 -+ -+/* Reserved [0x65] */ -+ -+#define OSCCAL _SFR_MEM8(0x66) -+#define OSCCAL0 0 -+#define OSCCAL1 1 -+#define OSCCAL2 2 -+#define OSCCAL3 3 -+#define OSCCAL4 4 -+#define OSCCAL5 5 -+#define OSCCAL6 6 -+#define OSCCAL7 7 -+ -+/* Reserved [0x67] */ -+ -+#define PCICR _SFR_MEM8(0x68) -+#define PCIE0 0 -+#define PCIE1 1 -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+ -+/* Reserved [0x6A] */ -+ -+#define PCMSK0 _SFR_MEM8(0x6B) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6C) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+#define PCINT14 6 -+#define PCINT15 7 -+ -+/* Reserved [0x6D] */ -+ -+#define TIMSK0 _SFR_MEM8(0x6E) -+#define TOIE0 0 -+#define OCIE0A 1 -+ -+#define TIMSK1 _SFR_MEM8(0x6F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define ICIE1 5 -+ -+/* Reserved [0x70..0x76] */ -+ -+#define AMISCR _SFR_MEM8(0x77) -+#define XREFEN 1 -+#define AREFEN 2 -+#define ISRCEN 0 -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_MEM16(0x78) -+#endif -+#define ADCW _SFR_MEM16(0x78) -+ -+#define ADCL _SFR_MEM8(0x78) -+#define ADCH _SFR_MEM8(0x79) -+ -+#define ADCSRA _SFR_MEM8(0x7A) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADCSRB _SFR_MEM8(0x7B) -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+#define BIN 7 -+#define ACIR0 4 -+#define ACIR1 5 -+#define ACME 6 -+ -+#define ADMUX _SFR_MEM8(0x7C) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define MUX4 4 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+/* Reserved [0x7D] */ -+ -+#define DIDR0 _SFR_MEM8(0x7E) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+#define ADC6D 6 -+#define ADC7D 7 -+ -+#define DIDR1 _SFR_MEM8(0x7F) -+#define ADC8D 0 -+#define ADC9D 1 -+#define ADC10D 2 -+ -+#define TCCR1A _SFR_MEM8(0x80) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR1B _SFR_MEM8(0x81) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1C _SFR_MEM8(0x82) -+#define FOC1B 6 -+#define FOC1A 7 -+ -+#define TCCR1D _SFR_MEM8(0x83) -+#define OC1AU 0 -+#define OC1AV 1 -+#define OC1AW 2 -+#define OC1AX 3 -+#define OC1BU 4 -+#define OC1BV 5 -+#define OC1BW 6 -+#define OC1BX 7 -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x84) -+ -+#define TCNT1L _SFR_MEM8(0x84) -+#define TCNT1H _SFR_MEM8(0x85) -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x86) -+ -+#define ICR1L _SFR_MEM8(0x86) -+#define ICR1H _SFR_MEM8(0x87) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_MEM16(0x88) -+ -+#define OCR1AL _SFR_MEM8(0x88) -+#define OCR1AH _SFR_MEM8(0x89) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_MEM16(0x8A) -+ -+#define OCR1BL _SFR_MEM8(0x8A) -+#define OCR1BH _SFR_MEM8(0x8B) -+ -+/* Reserved [0x8C..0xB5] */ -+ -+#define ASSR _SFR_MEM8(0xB6) -+#define TCR0BUB 0 -+#define TCR0AUB 1 -+#define OCR0AUB 3 -+#define TCN0UB 4 -+#define AS0 5 -+#define EXCLK 6 -+ -+/* Reserved [0xB7] */ -+ -+#define USICR _SFR_MEM8(0xB8) -+#define USITC 0 -+#define USICLK 1 -+#define USICS0 2 -+#define USICS1 3 -+#define USIWM0 4 -+#define USIWM1 5 -+#define USIOIE 6 -+#define USISIE 7 -+ -+#define USISR _SFR_MEM8(0xB9) -+#define USICNT0 0 -+#define USICNT1 1 -+#define USICNT2 2 -+#define USICNT3 3 -+#define USIDC 4 -+#define USIPF 5 -+#define USIOIF 6 -+#define USISIF 7 -+ -+#define USIDR _SFR_MEM8(0xBA) -+ -+#define USIBR _SFR_MEM8(0xBB) -+ -+#define USIPP _SFR_MEM8(0xBC) -+ -+/* Reserved [0xBD..0xC7] */ -+ -+#define LINCR _SFR_MEM8(0xC8) -+#define LCMD0 0 -+#define LCMD1 1 -+#define LCMD2 2 -+#define LENA 3 -+#define LCONF0 4 -+#define LCONF1 5 -+#define LIN13 6 -+#define LSWRES 7 -+ -+#define LINSIR _SFR_MEM8(0xC9) -+#define LRXOK 0 -+#define LTXOK 1 -+#define LIDOK 2 -+#define LERR 3 -+#define LBUSY 4 -+#define LIDST0 5 -+#define LIDST1 6 -+#define LIDST2 7 -+ -+#define LINENIR _SFR_MEM8(0xCA) -+#define LENRXOK 0 -+#define LENTXOK 1 -+#define LENIDOK 2 -+#define LENERR 3 -+ -+#define LINERR _SFR_MEM8(0xCB) -+#define LBERR 0 -+#define LCERR 1 -+#define LPERR 2 -+#define LSERR 3 -+#define LFERR 4 -+#define LOVERR 5 -+#define LTOERR 6 -+#define LABORT 7 -+ -+#define LINBTR _SFR_MEM8(0xCC) -+#define LBT0 0 -+#define LBT1 1 -+#define LBT2 2 -+#define LBT3 3 -+#define LBT4 4 -+#define LBT5 5 -+#define LDISR 7 -+ -+#define LINBRRL _SFR_MEM8(0xCD) -+#define LDIV0 0 -+#define LDIV1 1 -+#define LDIV2 2 -+#define LDIV3 3 -+#define LDIV4 4 -+#define LDIV5 5 -+#define LDIV6 6 -+#define LDIV7 7 -+ -+#define LINBRRH _SFR_MEM8(0xCE) -+#define LDIV8 0 -+#define LDIV9 1 -+#define LDIV10 2 -+#define LDIV11 3 -+ -+#define LINDLR _SFR_MEM8(0xCF) -+#define LRXDL0 0 -+#define LRXDL1 1 -+#define LRXDL2 2 -+#define LRXDL3 3 -+#define LTXDL0 4 -+#define LTXDL1 5 -+#define LTXDL2 6 -+#define LTXDL3 7 -+ -+#define LINIDR _SFR_MEM8(0xD0) -+#define LID0 0 -+#define LID1 1 -+#define LID2 2 -+#define LID3 3 -+#define LID4 4 -+#define LID5 5 -+#define LP0 6 -+#define LP1 7 -+ -+#define LINSEL _SFR_MEM8(0xD1) -+#define LINDX0 0 -+#define LINDX1 1 -+#define LINDX2 2 -+#define LAINC 3 -+ -+#define LINDAT _SFR_MEM8(0xD2) -+#define LDATA0 0 -+#define LDATA1 1 -+#define LDATA2 2 -+#define LDATA3 3 -+#define LDATA4 4 -+#define LDATA5 5 -+#define LDATA6 6 -+#define LDATA7 7 -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(3) -+#define PCINT0_vect_num 3 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(4) -+#define PCINT1_vect_num 4 -+ -+/* Watchdog Time-Out Interrupt */ -+#define WDT_vect _VECTOR(5) -+#define WDT_vect_num 5 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(6) -+#define TIMER1_CAPT_vect_num 6 -+ -+/* Timer/Counter1 Compare Match 1A */ -+#define TIMER1_COMPA_vect _VECTOR(7) -+#define TIMER1_COMPA_vect_num 7 -+ -+/* Timer/Counter1 Compare Match 1B */ -+#define TIMER1_COMPB_vect _VECTOR(8) -+#define TIMER1_COMPB_vect_num 8 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(9) -+#define TIMER1_OVF_vect_num 9 -+ -+/* Timer/Counter0 Compare Match 0A */ -+#define TIMER0_COMPA_vect _VECTOR(10) -+#define TIMER0_COMPA_vect_num 10 -+ -+/* Timer/Counter0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(11) -+#define TIMER0_OVF_vect_num 11 -+ -+/* LIN Transfer Complete */ -+#define LIN_TC_vect _VECTOR(12) -+#define LIN_TC_vect_num 12 -+ -+/* LIN Error */ -+#define LIN_ERR_vect _VECTOR(13) -+#define LIN_ERR_vect_num 13 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(14) -+#define SPI_STC_vect_num 14 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(15) -+#define ADC_vect_num 15 -+ -+/* EEPROM Ready */ -+#define EE_RDY_vect _VECTOR(16) -+#define EE_RDY_vect_num 16 -+ -+/* Analog Comparator */ -+#define ANA_COMP_vect _VECTOR(17) -+#define ANA_COMP_vect_num 17 -+ -+/* USI Start */ -+#define USI_START_vect _VECTOR(18) -+#define USI_START_vect_num 18 -+ -+/* USI Overflow */ -+#define USI_OVF_vect _VECTOR(19) -+#define USI_OVF_vect_num 19 -+ -+#define _VECTORS_SIZE 80 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 128 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x3FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 512 -+#define RAMEND 0x02FF -+#define E2START 0 -+#define E2SIZE 512 -+#define E2PAGESIZE 4 -+#define E2END 0x01FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -+#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_DWEN (unsigned char)~_BV(6) -+#define FUSE_RSTDISBL (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_SELFPRGEN (unsigned char)~_BV(0) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x94 -+#define SIGNATURE_2 0x87 -+ -+ -+#endif /* #ifdef _AVR_ATA5505_H_INCLUDED */ -+ -diff --git a/include/avr/ioa5702m322.h b/include/avr/ioa5702m322.h -new file mode 100644 -index 0000000..d78179d ---- /dev/null -+++ b/include/avr/ioa5702m322.h -@@ -0,0 +1,1903 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATA5702M322_H_INCLUDED -+#define _AVR_ATA5702M322_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "ioa5702m322.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define GPIOR0 _SFR_IO8(0x00) -+ -+#define PRR1 _SFR_IO8(0x01) -+#define PRT1 0 -+#define PRT2 1 -+#define PRT3 2 -+#define PRT4 3 -+#define PRT5 4 -+#define PRLFR 5 -+#define PRCI 6 -+ -+#define PRR2 _SFR_IO8(0x02) -+#define PRSF 2 -+#define PRDF 3 -+#define PRTM 6 -+#define PRSSM 7 -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x06) -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x07) -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x08) -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PIND _SFR_IO8(0x09) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0A) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x0B) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+#define TPCR2 _SFR_IO8(0x0C) -+#define TPMA 0 -+#define TPMOD 1 -+#define TPPSD 2 -+#define TPD 3 -+#define TPNFTO 4 -+#define TPWDLV0 5 -+#define TPWDLV1 6 -+ -+#define TPFR _SFR_IO8(0x0D) -+#define TPF 0 -+#define TPFTF 1 -+#define TPNFTF 2 -+#define TPBERF 3 -+ -+#define MCUCR _SFR_IO8(0x0E) -+#define IVCE 0 -+#define IVSEL 1 -+#define SPIIO 2 -+#define ENPS 3 -+#define PUD 4 -+#define TRCCE 5 -+#define TRCEN 6 -+ -+#define FSCR _SFR_IO8(0x0F) -+#define TXMOD 0 -+#define SFM 1 -+#define TXMS0 2 -+#define TXMS1 3 -+#define PAOER 4 -+#define PAON 7 -+ -+/* Reserved [0x10] */ -+ -+#define T1CR _SFR_IO8(0x11) -+#define T1OTM 0 -+#define T1CTM 1 -+#define T1CRM 2 -+#define T1TOP 4 -+#define T1RES 5 -+#define T1TOS 6 -+#define T1ENA 7 -+ -+#define T2CR _SFR_IO8(0x12) -+#define T2OTM 0 -+#define T2CTM 1 -+#define T2CRM 2 -+#define T2TOP 4 -+#define T2RES 5 -+#define T2TOS 6 -+#define T2ENA 7 -+ -+#define T3CR _SFR_IO8(0x13) -+#define T3OTM 0 -+#define T3CTM 1 -+#define T3CRM 2 -+#define T3CPRM 3 -+#define T3TOP 4 -+#define T3RES 5 -+#define T3TOS 6 -+#define T3ENA 7 -+ -+#define T4CR _SFR_IO8(0x14) -+#define T4OTM 0 -+#define T4CTM 1 -+#define T4CRM 2 -+#define T4CPRM 3 -+#define T4TOP 4 -+#define T4RES 5 -+#define T4TOS 6 -+#define T4ENA 7 -+ -+#define T1IFR _SFR_IO8(0x15) -+#define T1OFF 0 -+#define T1COF 1 -+ -+#define T2IFR _SFR_IO8(0x16) -+#define T2OFF 0 -+#define T2COF 1 -+ -+#define T3IFR _SFR_IO8(0x17) -+#define T3OFF 0 -+#define T3COF 1 -+#define T3ICF 2 -+ -+#define T4IFR _SFR_IO8(0x18) -+#define T4OFF 0 -+#define T4COF 1 -+#define T4ICF 2 -+ -+#define T5IFR _SFR_IO8(0x19) -+#define T5OFF 0 -+#define T5COF 1 -+ -+#define PRR0 _SFR_IO8(0x1A) -+#define PRSPI 0 -+#define PRTXDC 2 -+#define PRCRC 3 -+#define PRVM 4 -+#define PRCO 5 -+#define PRCU 6 -+#define PRTWI 7 -+ -+#define PHFR _SFR_IO8(0x1B) -+#define CRCEF 0 -+#define PHTBLF 1 -+#define PHDFF 2 -+#define PHIDFF 3 -+#define PHID0F 4 -+#define PHID1F 5 -+ -+#define LFFR _SFR_IO8(0x1C) -+#define LFSYDF 0 -+#define LFDEF 1 -+#define LFEOF 2 -+#define LFTOF 3 -+#define LFSD 6 -+#define LFES 7 -+ -+#define AESCR _SFR_IO8(0x1D) -+#define AESWK 0 -+#define AESWD 1 -+#define AESIM 2 -+#define AESD 3 -+#define AESXOR 4 -+#define AESRES 5 -+#define AESLKM 6 -+#define AESE 7 -+ -+#define AESSR _SFR_IO8(0x1E) -+#define AESRF 0 -+#define AESERF 7 -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEWE 1 -+#define EEMWE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+#define EEPAGE 6 -+#define NVMBSY 7 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define EEPR _SFR_IO8(0x23) -+#define EEAP0 0 -+#define EEAP1 1 -+#define EEAP2 2 -+#define EEAP3 3 -+ -+#define GPIOR1 _SFR_IO8(0x24) -+ -+#define GPIOR2 _SFR_IO8(0x25) -+ -+#define PCICR _SFR_IO8(0x26) -+#define PCIE0 0 -+#define PCIE1 1 -+ -+#define EIMSK _SFR_IO8(0x27) -+#define INT0 0 -+#define INT1 1 -+ -+#define EIFR _SFR_IO8(0x28) -+#define INTF0 0 -+#define INTF1 1 -+ -+#define CRCDIR _SFR_IO8(0x29) -+ -+#define VMSR _SFR_IO8(0x2A) -+#define VMF 0 -+ -+#define MCUSR _SFR_IO8(0x2B) -+#define PORF 0 -+#define EXTRF 1 -+#define BODRF 2 -+#define WDRF 3 -+#define TPRF 5 -+#define DVCCRF 6 -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define RXIF 4 -+#define TXIF 5 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+#define LFCR0 _SFR_IO8(0x2F) -+#define LFCE1 0 -+#define LFCE2 1 -+#define LFCE3 2 -+#define LFBR0 3 -+#define LFBR1 4 -+#define LFMG 5 -+#define LFRRT0 6 -+#define LFRRT1 7 -+ -+#define LFCR1 _SFR_IO8(0x30) -+#define LFFM0 0 -+#define LFFM1 1 -+#define ARMDE 2 -+#define FLLEN 4 -+#define ADTHEN 5 -+#define LFPEEN 6 -+#define LFRE 7 -+ -+#define DWDR _SFR_IO8(0x31) -+ -+#define T0IFR _SFR_IO8(0x32) -+#define T0F 0 -+ -+/* Reserved [0x33..0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SELFPRGEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define SPMIE 7 -+ -+#define SMCR _SFR_IO8(0x38) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define TPSR _SFR_IO8(0x39) -+#define TPA 0 -+#define TPGAP 1 -+#define TPPSW 2 -+#define TPBCOK 3 -+ -+#define LFCR2 _SFR_IO8(0x3A) -+#define LFSEN0 0 -+#define LFSEN1 1 -+#define LFDAMP 2 -+#define LFVC0 5 -+#define LFVC1 6 -+#define LFVC2 7 -+ -+#define LFCR3 _SFR_IO8(0x3B) -+#define LFRCTEN 0 -+#define LFRCPCEN 1 -+#define LFRCPM 2 -+ -+/* Reserved [0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define FSEN _SFR_MEM8(0x60) -+#define SDPU 0 -+#define SDEN 1 -+#define GAEN 2 -+#define PEEN 3 -+#define ASEN 4 -+#define ANTT 5 -+ -+#define FSFCR _SFR_MEM8(0x61) -+#define BTSEL0 0 -+#define BTSEL1 1 -+#define ASDIV0 4 -+#define ASDIV1 5 -+#define ASDIV2 6 -+#define ASDIV3 7 -+ -+/* Combine GACDIVL and GACDIVH */ -+#define GACDIV _SFR_MEM16(0x62) -+ -+#define GACDIVL _SFR_MEM8(0x62) -+#define GACDIVH _SFR_MEM8(0x63) -+ -+#define FFREQ1L _SFR_MEM8(0x64) -+ -+#define FFREQ1M _SFR_MEM8(0x65) -+ -+#define FFREQ1H _SFR_MEM8(0x66) -+ -+#define FFREQ2L _SFR_MEM8(0x67) -+ -+#define FFREQ2M _SFR_MEM8(0x68) -+ -+#define FFREQ2H _SFR_MEM8(0x69) -+ -+/* Reserved [0x6A] */ -+ -+#define EICRA _SFR_MEM8(0x6B) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+ -+#define PCMSK0 _SFR_MEM8(0x6C) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6D) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+#define PCINT14 6 -+#define PCINT15 7 -+ -+#define WDTCR _SFR_MEM8(0x6E) -+#define WDPS0 0 -+#define WDPS1 1 -+#define WDPS2 2 -+#define WDE 3 -+#define WDCE 4 -+ -+#define T1CNT _SFR_MEM8(0x6F) -+ -+#define T1COR _SFR_MEM8(0x70) -+ -+#define T1MR _SFR_MEM8(0x71) -+#define T1CS0 0 -+#define T1CS1 1 -+#define T1PS0 2 -+#define T1PS1 3 -+#define T1PS2 4 -+#define T1PS3 5 -+#define T1DC0 6 -+#define T1DC1 7 -+ -+#define T1IMR _SFR_MEM8(0x72) -+#define T1OIM 0 -+#define T1CIM 1 -+ -+#define T2CNT _SFR_MEM8(0x73) -+ -+#define T2COR _SFR_MEM8(0x74) -+ -+#define T2MR _SFR_MEM8(0x75) -+#define T2CS0 0 -+#define T2CS1 1 -+#define T2PS0 2 -+#define T2PS1 3 -+#define T2PS2 4 -+#define T2PS3 5 -+#define T2DC0 6 -+#define T2DC1 7 -+ -+#define T2IMR _SFR_MEM8(0x76) -+#define T2OIM 0 -+#define T2CIM 1 -+ -+/* Combine T3CNTL and T3CNTH */ -+#define T3CNT _SFR_MEM16(0x77) -+ -+#define T3CNTL _SFR_MEM8(0x77) -+#define T3CNTH _SFR_MEM8(0x78) -+ -+/* Combine T3CORL and T3CORH */ -+#define T3COR _SFR_MEM16(0x79) -+ -+#define T3CORL _SFR_MEM8(0x79) -+#define T3CORH _SFR_MEM8(0x7A) -+ -+/* Combine T3ICRL and T3ICRH */ -+#define T3ICR _SFR_MEM16(0x7B) -+ -+#define T3ICRL _SFR_MEM8(0x7B) -+#define T3ICRH _SFR_MEM8(0x7C) -+ -+#define T3MRA _SFR_MEM8(0x7D) -+#define T3CS0 0 -+#define T3CS1 1 -+#define T3PS0 2 -+#define T3PS1 3 -+#define T3PS2 4 -+ -+#define T3MRB _SFR_MEM8(0x7E) -+#define T3SCE 1 -+#define T3CNC 2 -+#define T3CE0 3 -+#define T3CE1 4 -+#define T3ICS0 5 -+#define T3ICS1 6 -+#define T3ICS2 7 -+ -+#define T3IMR _SFR_MEM8(0x7F) -+#define T3OIM 0 -+#define T3CIM 1 -+#define T3CPIM 2 -+ -+/* Combine T4CNTL and T4CNTH */ -+#define T4CNT _SFR_MEM16(0x80) -+ -+#define T4CNTL _SFR_MEM8(0x80) -+#define T4CNTH _SFR_MEM8(0x81) -+ -+/* Combine T4CORL and T4CORH */ -+#define T4COR _SFR_MEM16(0x82) -+ -+#define T4CORL _SFR_MEM8(0x82) -+#define T4CORH _SFR_MEM8(0x83) -+ -+/* Combine T4ICRL and T4ICRH */ -+#define T4ICR _SFR_MEM16(0x84) -+ -+#define T4ICRL _SFR_MEM8(0x84) -+#define T4ICRH _SFR_MEM8(0x85) -+ -+#define T4MRA _SFR_MEM8(0x86) -+#define T4CS0 0 -+#define T4CS1 1 -+#define T4PS0 2 -+#define T4PS1 3 -+#define T4PS2 4 -+ -+#define T4MRB _SFR_MEM8(0x87) -+#define T4SCE 1 -+#define T4CNC 2 -+#define T4CE0 3 -+#define T4CE1 4 -+#define T4ICS0 5 -+#define T4ICS1 6 -+#define T4ICS2 7 -+ -+#define T4IMR _SFR_MEM8(0x88) -+#define T4OIM 0 -+#define T4CIM 1 -+#define T4CPIM 2 -+ -+#define T5TEMP _SFR_MEM8(0x89) -+ -+/* Combine T5OCRL and T5OCRH */ -+#define T5OCR _SFR_MEM16(0x8A) -+ -+#define T5OCRL _SFR_MEM8(0x8A) -+#define T5OCRH _SFR_MEM8(0x8B) -+ -+#define T5CCR _SFR_MEM8(0x8C) -+#define T5CS0 0 -+#define T5CS1 1 -+#define T5CS2 2 -+#define T5CTC 3 -+ -+/* Combine T5CNTL and T5CNTH */ -+#define T5CNT _SFR_MEM16(0x8D) -+ -+#define T5CNTL _SFR_MEM8(0x8D) -+#define T5CNTH _SFR_MEM8(0x8E) -+ -+#define T5IMR _SFR_MEM8(0x8F) -+#define T5OIM 0 -+#define T5CIM 1 -+ -+#define GTCCR _SFR_MEM8(0x90) -+#define PSR10 0 -+#define TSM 7 -+ -+/* Reserved [0x91..0xC2] */ -+ -+#define CLKOD _SFR_MEM8(0xC3) -+ -+#define CLKOCR _SFR_MEM8(0xC4) -+#define CLKOS0 0 -+#define CLKOS1 1 -+#define CLKOEN 2 -+ -+/* Reserved [0xC5] */ -+ -+#define MRCCAL _SFR_MEM8(0xC6) -+ -+#define FRCCAL _SFR_MEM8(0xC7) -+ -+/* Reserved [0xC8] */ -+ -+#define CMSR _SFR_MEM8(0xC9) -+#define ECF 0 -+ -+#define CMOCR _SFR_MEM8(0xCA) -+#define FRCAO 0 -+#define MRCAO 1 -+#define FRCACT 2 -+ -+#define SUPFR _SFR_MEM8(0xCB) -+#define AVCCRF 0 -+#define AVCCLF 1 -+ -+#define SUPCR _SFR_MEM8(0xCC) -+#define AVCCRM 0 -+#define AVCCLM 1 -+#define PVEN 2 -+#define AVDIC 3 -+#define AVEN 4 -+#define DVHEN 5 -+ -+/* Reserved [0xCD..0xD1] */ -+ -+#define DFS _SFR_MEM8(0xD2) -+#define DFFLRF 0 -+#define DFUFL 1 -+#define DFOFL 2 -+ -+/* Combine DFTLL and DFTLH */ -+#define DFTL _SFR_MEM16(0xD3) -+ -+#define DFTLL _SFR_MEM8(0xD3) -+#define DFTLH _SFR_MEM8(0xD4) -+ -+#define DFL _SFR_MEM8(0xD5) -+#define DFFLS0 0 -+#define DFFLS1 1 -+#define DFFLS2 2 -+#define DFFLS3 3 -+#define DFFLS4 4 -+#define DFFLS5 5 -+#define DFCLR 7 -+ -+#define DFWP _SFR_MEM8(0xD6) -+ -+#define DFRP _SFR_MEM8(0xD7) -+ -+#define DFD _SFR_MEM8(0xD8) -+ -+#define DFI _SFR_MEM8(0xD9) -+#define DFFLIM 0 -+#define DFERIM 1 -+ -+#define DFC _SFR_MEM8(0xDA) -+#define DFFLC0 0 -+#define DFFLC1 1 -+#define DFFLC2 2 -+#define DFFLC3 3 -+#define DFFLC4 4 -+#define DFFLC5 5 -+#define DFDRA 7 -+ -+#define SFS _SFR_MEM8(0xDB) -+#define SFFLRF 0 -+#define SFUFL 1 -+#define SFOFL 2 -+ -+#define SFL _SFR_MEM8(0xDC) -+#define SFFLS0 0 -+#define SFFLS1 1 -+#define SFFLS2 2 -+#define SFFLS3 3 -+#define SFFLS4 4 -+#define SFCLR 7 -+ -+#define SFWP _SFR_MEM8(0xDD) -+ -+#define SFRP _SFR_MEM8(0xDE) -+ -+#define SFD _SFR_MEM8(0xDF) -+ -+#define SFI _SFR_MEM8(0xE0) -+#define SFFLIM 0 -+#define SFERIM 1 -+ -+#define SFC _SFR_MEM8(0xE1) -+#define SFFLC0 0 -+#define SFFLC1 1 -+#define SFFLC2 2 -+#define SFFLC3 3 -+#define SFFLC4 4 -+#define SFDRA 7 -+ -+#define SSMCR _SFR_MEM8(0xE2) -+#define SSMTGE 2 -+#define SSMTPE 3 -+#define SSMPVE 4 -+#define SSMTAE 5 -+ -+/* Reserved [0xE3] */ -+ -+#define SSMFBR _SFR_MEM8(0xE4) -+#define SSMPLDT 5 -+ -+#define SSMRR _SFR_MEM8(0xE5) -+#define SSMR 0 -+#define SSMST 1 -+ -+#define SSMSR _SFR_MEM8(0xE6) -+#define SSMESM0 0 -+#define SSMESM1 1 -+#define SSMESM2 2 -+#define SSMESM3 3 -+#define SSMERR 7 -+ -+#define SSMIFR _SFR_MEM8(0xE7) -+#define SSMIF 0 -+ -+#define SSMIMR _SFR_MEM8(0xE8) -+#define SSMIM 0 -+ -+#define MSMSTR _SFR_MEM8(0xE9) -+#define SSMMST0 0 -+#define SSMMST1 1 -+#define SSMMST2 2 -+#define SSMMST3 3 -+#define SSMMST4 4 -+ -+#define SSMSTR _SFR_MEM8(0xEA) -+#define SSMSTA0 0 -+#define SSMSTA1 1 -+#define SSMSTA2 2 -+#define SSMSTA3 3 -+#define SSMSTA4 4 -+#define SSMSTA5 5 -+ -+/* Reserved [0xEB] */ -+ -+#define MSMCR1 _SFR_MEM8(0xEC) -+#define MSMSM00 0 -+#define MSMSM01 1 -+#define MSMSM02 2 -+#define MSMSM03 3 -+#define MSMSM10 4 -+#define MSMSM11 5 -+#define MSMSM12 6 -+#define MSMSM13 7 -+ -+#define MSMCR2 _SFR_MEM8(0xED) -+#define MSMSM20 0 -+#define MSMSM21 1 -+#define MSMSM22 2 -+#define MSMSM23 3 -+#define MSMSM30 4 -+#define MSMSM31 5 -+#define MSMSM32 6 -+#define MSMSM33 7 -+ -+#define MSMCR3 _SFR_MEM8(0xEE) -+#define MSMSM40 0 -+#define MSMSM41 1 -+#define MSMSM42 2 -+#define MSMSM43 3 -+#define MSMSM50 4 -+#define MSMSM51 5 -+#define MSMSM52 6 -+#define MSMSM53 7 -+ -+#define MSMCR4 _SFR_MEM8(0xEF) -+#define MSMSM60 0 -+#define MSMSM61 1 -+#define MSMSM62 2 -+#define MSMSM63 3 -+#define MSMSM70 4 -+#define MSMSM71 5 -+#define MSMSM72 6 -+#define MSMSM73 7 -+ -+/* Reserved [0xF0..0xFB] */ -+ -+/* Combine TRCIDL and TRCIDH */ -+#define TRCID _SFR_MEM16(0xFC) -+ -+#define TRCIDL _SFR_MEM8(0xFC) -+#define TRCIDH _SFR_MEM8(0xFD) -+ -+/* Reserved [0xFE] */ -+ -+#define TRCDR _SFR_MEM8(0xFF) -+ -+#define FESR _SFR_MEM8(0x100) -+#define XRDY 2 -+#define PLCK 3 -+#define ANTS 4 -+ -+#define FEEN1 _SFR_MEM8(0x101) -+#define PLEN 0 -+#define PLCAL 1 -+#define XTOEN 2 -+#define PLSP1 6 -+#define ATEN 7 -+ -+#define FEEN2 _SFR_MEM8(0x102) -+#define PAEN 2 -+#define PLPEN 4 -+#define CPBIA 6 -+ -+/* Reserved [0x103] */ -+ -+#define FEAT _SFR_MEM8(0x104) -+#define ANTN0 0 -+#define ANTN1 1 -+#define ANTN2 2 -+#define ANTN3 3 -+ -+#define FEPAC _SFR_MEM8(0x105) -+#define PACR0 0 -+#define PACR1 1 -+#define PACR2 2 -+#define PACR3 3 -+#define PACR4 4 -+#define PACR5 5 -+#define PACR6 6 -+#define PACR7 7 -+ -+#define FEVCT _SFR_MEM8(0x106) -+ -+#define FEBT _SFR_MEM8(0x107) -+#define CTN20 0 -+#define CTN21 1 -+#define RTN20 2 -+#define RTN21 3 -+ -+#define FEMS _SFR_MEM8(0x108) -+#define PLLS0 0 -+#define PLLS1 1 -+#define PLLS2 2 -+#define PLLS3 3 -+#define PLLM0 4 -+#define PLLM1 5 -+#define PLLM2 6 -+#define PLLM3 7 -+ -+#define FETN4 _SFR_MEM8(0x109) -+#define CTN40 0 -+#define CTN41 1 -+#define CTN42 2 -+#define CTN43 3 -+#define RTN40 4 -+#define RTN41 5 -+#define RTN42 6 -+#define RTN43 7 -+ -+#define FECR _SFR_MEM8(0x10A) -+#define LBNHB 0 -+#define S4N3 1 -+#define PLCKG 4 -+#define ANPS 5 -+ -+#define FEVCO _SFR_MEM8(0x10B) -+#define CPCC0 0 -+#define CPCC1 1 -+#define CPCC2 2 -+#define CPCC3 3 -+#define VCOB0 4 -+#define VCOB1 5 -+#define VCOB2 6 -+#define VCOB3 7 -+ -+#define FEALR _SFR_MEM8(0x10C) -+#define RNGE0 0 -+#define RNGE1 1 -+ -+#define FEANT _SFR_MEM8(0x10D) -+#define LVLC0 0 -+#define LVLC1 1 -+#define LVLC2 2 -+#define LVLC3 3 -+ -+/* Reserved [0x10E..0x11F] */ -+ -+#define TMFSM _SFR_MEM8(0x120) -+#define TMSSM0 0 -+#define TMSSM1 1 -+#define TMSSM2 2 -+#define TMSSM3 3 -+#define TMMSM0 4 -+#define TMMSM1 5 -+#define TMMSM2 6 -+ -+/* Combine TMCRCL and TMCRCH */ -+#define TMCRC _SFR_MEM16(0x121) -+ -+#define TMCRCL _SFR_MEM8(0x121) -+#define TMCRCH _SFR_MEM8(0x122) -+ -+#define TMCSB _SFR_MEM8(0x123) -+ -+/* Combine TMCIL and TMCIH */ -+#define TMCI _SFR_MEM16(0x124) -+ -+#define TMCIL _SFR_MEM8(0x124) -+#define TMCIH _SFR_MEM8(0x125) -+ -+/* Combine TMCPL and TMCPH */ -+#define TMCP _SFR_MEM16(0x126) -+ -+#define TMCPL _SFR_MEM8(0x126) -+#define TMCPH _SFR_MEM8(0x127) -+ -+#define TMSHR _SFR_MEM8(0x128) -+ -+/* Combine TMTLLL and TMTLLH */ -+#define TMTLL _SFR_MEM16(0x129) -+ -+#define TMTLLL _SFR_MEM8(0x129) -+#define TMTLLH _SFR_MEM8(0x12A) -+ -+#define TMSSC _SFR_MEM8(0x12B) -+#define TMSSP0 0 -+#define TMSSP1 1 -+#define TMSSP2 2 -+#define TMSSP3 3 -+#define TMSSL0 4 -+#define TMSSL1 5 -+#define TMSSL2 6 -+#define TMSSH 7 -+ -+#define TMSR _SFR_MEM8(0x12C) -+#define TMTCF 0 -+ -+#define TMCR2 _SFR_MEM8(0x12D) -+#define TMCRCE 0 -+#define TMCRCSE0 1 -+#define TMCRCSE1 2 -+#define TMNRZE 3 -+#define TMPOL 4 -+#define TMSSE 5 -+#define TMLSB 6 -+ -+#define TMCR1 _SFR_MEM8(0x12E) -+#define TMPIS0 0 -+#define TMPIS1 1 -+#define TMPIS2 2 -+#define TMSCS 3 -+#define TMCIM 4 -+ -+/* Reserved [0x12F..0x144] */ -+ -+#define CRCCR _SFR_MEM8(0x145) -+#define CRCRS 0 -+#define REFLI 1 -+#define REFLO 2 -+ -+#define CRCDOR _SFR_MEM8(0x146) -+ -+/* Reserved [0x147..0x150] */ -+ -+#define LFDSRR _SFR_MEM8(0x151) -+#define SRCDT0 0 -+#define SRCDT1 1 -+#define SRCDT2 2 -+#define SRCDT3 3 -+#define SRCDT4 4 -+#define SRCDT5 5 -+#define SRCDT6 6 -+#define SRCDT7 7 -+ -+#define DBCR _SFR_MEM8(0x152) -+#define DBMD 0 -+#define DBCS 1 -+#define DBTMS 2 -+#define DBHA 3 -+ -+#define DBTC _SFR_MEM8(0x153) -+ -+#define DBENB _SFR_MEM8(0x154) -+ -+#define DBENC _SFR_MEM8(0x155) -+ -+#define DBGSW _SFR_MEM8(0x156) -+#define DBGGS0 0 -+#define DBGGS1 1 -+#define DBGGS2 2 -+#define DBGGS3 3 -+#define CPBFOS0 4 -+#define CPBFOS1 5 -+#define CPBF 6 -+#define ATEST 7 -+ -+#define SFFR _SFR_MEM8(0x157) -+#define RFL0 0 -+#define RFL1 1 -+#define RFL2 2 -+#define RFC 3 -+#define TFL0 4 -+#define TFL1 5 -+#define TFL2 6 -+#define TFC 7 -+ -+#define SFIR _SFR_MEM8(0x158) -+#define RIL0 0 -+#define RIL1 1 -+#define RIL2 2 -+#define SRIE 3 -+#define TIL0 4 -+#define TIL1 5 -+#define TIL2 6 -+#define STIE 7 -+ -+#define EECR2 _SFR_MEM8(0x159) -+#define EEBRE 0 -+#define E2CIM 1 -+#define E2FF 6 -+#define E2CF 7 -+ -+/* Reserved [0x15A] */ -+ -+#define EEST _SFR_MEM8(0x15B) -+#define EESYN0 0 -+#define EESYN1 1 -+#define EESYN2 2 -+#define EESYN3 3 -+ -+/* Reserved [0x15C..0x15F] */ -+ -+#define LFRSFR _SFR_MEM8(0x160) -+#define LFRSMF 0 -+#define LFRSTO1 1 -+#define LFRSTO2 2 -+#define LFRSTO3 3 -+ -+#define PCIFR _SFR_MEM8(0x161) -+#define PCIF0 0 -+#define PCIF1 1 -+ -+#define T0CR _SFR_MEM8(0x162) -+#define T0PS0 0 -+#define T0PS1 1 -+#define T0PS2 2 -+#define T0IE 3 -+#define T0PR 4 -+ -+/* Reserved [0x163] */ -+ -+#define DBEND _SFR_MEM8(0x164) -+ -+#define TPCR1 _SFR_MEM8(0x165) -+#define TPQPLM 2 -+#define TPBR 4 -+#define TPDFCP0 5 -+#define TPDFCP1 6 -+#define TPMODE 7 -+ -+#define TPIMR _SFR_MEM8(0x166) -+#define TPIM 0 -+#define TPFTIM 1 -+#define TPNFTIM 2 -+#define TPBERIM 3 -+ -+#define TPDCR1 _SFR_MEM8(0x167) -+#define TPDCL10 0 -+#define TPDCL11 1 -+#define TPDCL12 2 -+#define TPDCL13 3 -+#define TPDCL14 4 -+#define TPDCL15 5 -+ -+#define TPDCR2 _SFR_MEM8(0x168) -+#define TPDCL20 0 -+#define TPDCL21 1 -+#define TPDCL22 2 -+#define TPDCL23 3 -+#define TPDCL24 4 -+#define TPDCL25 5 -+ -+#define TPDCR3 _SFR_MEM8(0x169) -+#define TPDCL30 0 -+#define TPDCL31 1 -+#define TPDCL32 2 -+#define TPDCL33 3 -+#define TPDCL34 4 -+#define TPDCL35 5 -+ -+#define TPDCR4 _SFR_MEM8(0x16A) -+#define TPDCL40 0 -+#define TPDCL41 1 -+#define TPDCL42 2 -+#define TPDCL43 3 -+#define TPDCL44 4 -+#define TPDCL45 5 -+ -+#define TPDCR5 _SFR_MEM8(0x16B) -+#define TPDCL50 0 -+#define TPDCL51 1 -+#define TPDCL52 2 -+#define TPDCL53 3 -+#define TPDCL54 4 -+#define TPDCL55 5 -+ -+#define TPECR1 _SFR_MEM8(0x16C) -+#define TPECL10 0 -+#define TPECL11 1 -+#define TPECL12 2 -+#define TPECL13 3 -+#define TPECL14 4 -+#define TPECL15 5 -+#define TPECL16 6 -+#define TPECL17 7 -+ -+#define TPECR2 _SFR_MEM8(0x16D) -+#define TPECL20 0 -+#define TPECL21 1 -+#define TPECL22 2 -+#define TPECL23 3 -+#define TPECL24 4 -+#define TPECL25 5 -+#define TPECL26 6 -+#define TPECL27 7 -+ -+#define TPECR3 _SFR_MEM8(0x16E) -+#define TPECL30 0 -+#define TPECL31 1 -+#define TPECL32 2 -+#define TPECL33 3 -+#define TPECL34 4 -+#define TPECL35 5 -+#define TPECL36 6 -+#define TPECL37 7 -+ -+#define TPECR4 _SFR_MEM8(0x16F) -+#define TPECL40 0 -+#define TPECL41 1 -+#define TPECL42 2 -+#define TPECL43 3 -+#define TPECL44 4 -+#define TPECL45 5 -+#define TPECL46 6 -+#define TPECL47 7 -+ -+#define TPECMR _SFR_MEM8(0x170) -+#define TPECM10 0 -+#define TPECM11 1 -+#define TPECM20 2 -+#define TPECM21 3 -+#define TPECM30 4 -+#define TPECM31 5 -+#define TPECM40 6 -+#define TPECM41 7 -+ -+#define TPCR3 _SFR_MEM8(0x171) -+#define TPTD 0 -+#define TPRD 1 -+#define TPTLIW 2 -+#define TPRCD 5 -+ -+#define TPCR4 _SFR_MEM8(0x172) -+#define TPBCCS0 0 -+#define TPBCCS1 1 -+#define TPBCCS2 2 -+#define TPBCCS3 3 -+#define TPBCM 4 -+ -+#define TPCR5 _SFR_MEM8(0x173) -+#define TPMUD0 0 -+#define TPMUD1 1 -+#define TPMUD2 2 -+#define TPMD0 4 -+#define TPMD1 5 -+#define TPMD2 6 -+ -+#define LFRSMR _SFR_MEM8(0x174) -+#define LFRSM0 0 -+#define LFRSM1 1 -+#define LFRSM2 2 -+#define LFRSM3 3 -+#define LFRSCM 4 -+#define LFRSFD 5 -+#define LFRSD0 6 -+#define LFRSD1 7 -+ -+/* Reserved [0x175..0x17E] */ -+ -+#define AESDPR _SFR_MEM8(0x17F) -+ -+#define AESKR _SFR_MEM8(0x180) -+ -+#define AESDR _SFR_MEM8(0x181) -+ -+#define GPIOR3 _SFR_MEM8(0x182) -+ -+#define GPIOR4 _SFR_MEM8(0x183) -+ -+#define GPIOR5 _SFR_MEM8(0x184) -+ -+#define GPIOR6 _SFR_MEM8(0x185) -+ -+#define PHBCRR _SFR_MEM8(0x186) -+#define PHBCR0 0 -+#define PHBCR1 1 -+#define PHBCR2 2 -+#define PHBCR3 3 -+#define PHBCR4 4 -+#define PHBCR5 5 -+#define PHBCR6 6 -+#define PHBCR7 7 -+ -+#define LFRSCR _SFR_MEM8(0x187) -+#define LFRSA0 0 -+#define LFRSA1 1 -+#define LFRSA2 2 -+#define LFRSMS 3 -+#define LFRSIM 4 -+#define LFRSRS 5 -+ -+/* Combine LFRSC1L and LFRSC1H */ -+#define LFRSC1 _SFR_MEM16(0x188) -+ -+#define LFRSC1L _SFR_MEM8(0x188) -+#define LFRSC1H _SFR_MEM8(0x189) -+ -+/* Combine LFRSC2L and LFRSC2H */ -+#define LFRSC2 _SFR_MEM16(0x18A) -+ -+#define LFRSC2L _SFR_MEM8(0x18A) -+#define LFRSC2H _SFR_MEM8(0x18B) -+ -+/* Combine LFRSC3L and LFRSC3H */ -+#define LFRSC3 _SFR_MEM16(0x18C) -+ -+#define LFRSC3L _SFR_MEM8(0x18C) -+#define LFRSC3H _SFR_MEM8(0x18D) -+ -+#define LFCPR _SFR_MEM8(0x18E) -+#define LFCALP 0 -+#define LFCALRY 1 -+#define LFCPCE 7 -+ -+#define LFIMR _SFR_MEM8(0x18F) -+#define LFSYDIM 0 -+#define LFDEIM 1 -+#define LFEOIM 2 -+ -+#define PHID00 _SFR_MEM8(0x190) -+#define ID000 0 -+#define ID001 1 -+#define ID002 2 -+#define ID003 3 -+#define ID004 4 -+#define ID005 5 -+#define ID006 6 -+#define ID007 7 -+ -+#define PHID01 _SFR_MEM8(0x191) -+#define ID010 0 -+#define ID011 1 -+#define ID012 2 -+#define ID013 3 -+#define ID014 4 -+#define ID015 5 -+#define ID016 6 -+#define ID017 7 -+ -+#define PHID02 _SFR_MEM8(0x192) -+#define ID020 0 -+#define ID021 1 -+#define ID022 2 -+#define ID023 3 -+#define ID024 4 -+#define ID025 5 -+#define ID026 6 -+#define ID027 7 -+ -+#define PHID03 _SFR_MEM8(0x193) -+#define ID030 0 -+#define ID031 1 -+#define ID032 2 -+#define ID033 3 -+#define ID034 4 -+#define ID035 5 -+#define ID036 6 -+#define ID037 7 -+ -+#define PHID0L _SFR_MEM8(0x194) -+#define ID0FS0 0 -+#define ID0FS1 1 -+#define ID0FS2 2 -+#define ID0FS3 3 -+#define ID0FS4 4 -+#define ID0FS5 5 -+ -+#define PHID10 _SFR_MEM8(0x195) -+#define ID100 0 -+#define ID101 1 -+#define ID102 2 -+#define ID103 3 -+#define ID104 4 -+#define ID105 5 -+#define ID106 6 -+#define ID107 7 -+ -+#define PHID11 _SFR_MEM8(0x196) -+#define ID110 0 -+#define ID111 1 -+#define ID112 2 -+#define ID113 3 -+#define ID114 4 -+#define ID115 5 -+#define ID116 6 -+#define ID117 7 -+ -+#define PHID12 _SFR_MEM8(0x197) -+#define ID120 0 -+#define ID121 1 -+#define ID122 2 -+#define ID123 3 -+#define ID124 4 -+#define ID125 5 -+#define ID126 6 -+#define ID127 7 -+ -+#define PHID13 _SFR_MEM8(0x198) -+#define ID130 0 -+#define ID131 1 -+#define ID132 2 -+#define ID133 3 -+#define ID134 4 -+#define ID135 5 -+#define ID136 6 -+#define ID137 7 -+ -+#define PHID1L _SFR_MEM8(0x199) -+#define ID1FS0 0 -+#define ID1FS1 1 -+#define ID1FS2 2 -+#define ID1FS3 3 -+#define ID1FS4 4 -+#define ID1FS5 5 -+ -+#define PHIDFR _SFR_MEM8(0x19A) -+#define RDFS0 0 -+#define RDFS1 1 -+#define RDFS2 2 -+#define RDFS3 3 -+#define RDFS4 4 -+#define RDFS5 5 -+#define RDFS6 6 -+#define RDFS7 7 -+ -+#define LFSYSY0 _SFR_MEM8(0x19B) -+ -+#define LFSYSY1 _SFR_MEM8(0x19C) -+ -+#define LFSYSY2 _SFR_MEM8(0x19D) -+ -+#define LFSYSY3 _SFR_MEM8(0x19E) -+ -+#define LFSYLE _SFR_MEM8(0x19F) -+ -+#define LFSTOP _SFR_MEM8(0x1A0) -+#define LFSTSY0 0 -+#define LFSTSY1 1 -+#define LFSTSY2 2 -+#define LFSTSY3 3 -+#define LFSTL0 4 -+#define LFSTL1 5 -+#define LFSTL2 6 -+ -+#define PHTCOR _SFR_MEM8(0x1A1) -+ -+#define PHTCMR _SFR_MEM8(0x1A2) -+#define PHPS0 0 -+#define PHPS1 1 -+#define PHPS2 2 -+#define PHCRM 3 -+#define PHCIM 4 -+#define PHRES 5 -+#define PHSM 6 -+#define PHTE 7 -+ -+/* Reserved [0x1A3] */ -+ -+#define PHTBLR _SFR_MEM8(0x1A4) -+#define PHTBL0 0 -+#define PHTBL1 1 -+#define PHTBL2 2 -+#define PHTBL3 3 -+#define PHTBL4 4 -+#define PHTBL5 5 -+#define PHTBL6 6 -+#define PHTBL7 7 -+ -+#define PHDFR _SFR_MEM8(0x1A5) -+#define PHDF0 0 -+#define PHDF1 1 -+#define PHDF2 2 -+#define PHDF3 3 -+#define PHDF4 4 -+#define PHDF5 5 -+#define PHDF6 6 -+#define PHDF7 7 -+ -+#define PHTEMR _SFR_MEM8(0x1A6) -+#define ID0EM 0 -+#define ID1EM 1 -+#define IDFEM 2 -+#define DFEM 3 -+#define TBLEM 4 -+#define FLEM 5 -+#define EOFEM 6 -+#define PHCOF 7 -+ -+#define LFQC3 _SFR_MEM8(0x1A7) -+#define LFQS30 0 -+#define LFQS31 1 -+#define LFQS32 2 -+#define LFQS33 3 -+#define LFCS30 4 -+#define LFCS31 5 -+#define LFCS32 6 -+#define LFCS33 7 -+ -+#define LFQC2 _SFR_MEM8(0x1A8) -+#define LFQS20 0 -+#define LFQS21 1 -+#define LFQS22 2 -+#define LFQS23 3 -+#define LFCS20 4 -+#define LFCS21 5 -+#define LFCS22 6 -+#define LFCS23 7 -+ -+#define LFQC1 _SFR_MEM8(0x1A9) -+#define LFQS10 0 -+#define LFQS11 1 -+#define LFQS12 2 -+#define LFQS13 3 -+#define LFCS10 4 -+#define LFCS11 5 -+#define LFCS12 6 -+#define LFCS13 7 -+ -+/* Reserved [0x1AA..0x1D0] */ -+ -+#define PHFS _SFR_MEM8(0x1D1) -+#define FLRF 0 -+#define FUFL 1 -+#define FOFL 2 -+ -+#define PHFL _SFR_MEM8(0x1D2) -+#define FLS0 0 -+#define FLS1 1 -+#define FLS2 2 -+#define FLS3 3 -+#define FLS4 4 -+#define FLS5 5 -+#define PHCLR 7 -+ -+#define PHFWP _SFR_MEM8(0x1D3) -+#define FWP0 0 -+#define FWP1 1 -+#define FWP2 2 -+#define FWP3 3 -+#define FWP4 4 -+#define FWP5 5 -+ -+#define PHFRP _SFR_MEM8(0x1D4) -+#define FRP0 0 -+#define FRP1 1 -+#define FRP2 2 -+#define FRP3 3 -+#define FRP4 4 -+#define FRP5 5 -+ -+#define PHFD _SFR_MEM8(0x1D5) -+ -+#define PHFI _SFR_MEM8(0x1D6) -+#define FLIM 0 -+#define ERIM 1 -+ -+#define PHFC _SFR_MEM8(0x1D7) -+#define FLC0 0 -+#define FLC1 1 -+#define FLC2 2 -+#define FLC3 3 -+#define FLC4 4 -+#define FLC5 5 -+#define FFMSB 6 -+#define DRA 7 -+ -+#define PHIMR _SFR_MEM8(0x1D8) -+#define PHTBLIM 1 -+#define PHDFIM 2 -+#define PHIDFIM 3 -+#define PHID0IM 4 -+#define PHID1IM 5 -+ -+#define PHCRCR _SFR_MEM8(0x1D9) -+#define CRCFR 2 -+#define CRCMSB 3 -+#define CRCSE0 4 -+#define CRCSE1 5 -+#define STREN 6 -+#define CRCEN 7 -+ -+/* Combine PHCSTL and PHCSTH */ -+#define PHCST _SFR_MEM16(0x1DA) -+ -+#define PHCSTL _SFR_MEM8(0x1DA) -+#define PHCSTH _SFR_MEM8(0x1DB) -+ -+/* Combine PHCRPL and PHCRPH */ -+#define PHCRP _SFR_MEM16(0x1DC) -+ -+#define PHCRPL _SFR_MEM8(0x1DC) -+#define PHCRPH _SFR_MEM8(0x1DD) -+ -+/* Combine PHCSRL and PHCSRH */ -+#define PHCSR _SFR_MEM16(0x1DE) -+ -+#define PHCSRL _SFR_MEM8(0x1DE) -+#define PHCSRH _SFR_MEM8(0x1DF) -+ -+#define PHCKSR _SFR_MEM8(0x1E0) -+#define FIFO_SW 0 -+ -+#define PHCKCR _SFR_MEM8(0x1E1) -+#define FIFSCSW 0 -+#define FRFIFO 5 -+#define CPM 6 -+#define CSM 7 -+ -+/* Reserved [0x1E2] */ -+ -+#define CMCR _SFR_MEM8(0x1E3) -+#define CMM0 0 -+#define CMM1 1 -+#define CMM2 2 -+#define CCS 3 -+#define CMONEN 6 -+#define CMCCE 7 -+ -+#define CMIMR _SFR_MEM8(0x1E4) -+#define ECIE 0 -+ -+#define CLPR _SFR_MEM8(0x1E5) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLTPS0 3 -+#define CLTPS1 4 -+#define CLTPS2 5 -+#define CLPCE 7 -+ -+#define VMCR _SFR_MEM8(0x1E6) -+#define VMLS0 0 -+#define VMLS1 1 -+#define VMLS2 2 -+#define VMLS3 3 -+#define VMIM 4 -+#define VMPS0 5 -+#define VMPS1 6 -+#define VMRS 7 -+ -+/* Reserved [0x1E7..0x1E8] */ -+ -+#define TWBR _SFR_MEM8(0x1E9) -+ -+#define TWCR _SFR_MEM8(0x1EA) -+#define TWIE 0 -+#define TWEN 2 -+#define TWWC 3 -+#define TWSTO 4 -+#define TWSTA 5 -+#define TWEA 6 -+#define TWINT 7 -+ -+#define TWSR _SFR_MEM8(0x1EB) -+#define TWPS0 0 -+#define TWPS1 1 -+#define TWS0 3 -+#define TWS1 4 -+#define TWS2 5 -+#define TWS3 6 -+#define TWS4 7 -+ -+#define TWDR _SFR_MEM8(0x1EC) -+ -+#define TWAR _SFR_MEM8(0x1ED) -+#define TWGCE 0 -+#define TWA0 1 -+#define TWA1 2 -+#define TWA2 3 -+#define TWA3 4 -+#define TWA4 5 -+#define TWA5 6 -+#define TWA6 7 -+ -+#define TWAMR _SFR_MEM8(0x1EE) -+#define TWAM0 1 -+#define TWAM1 2 -+#define TWAM2 3 -+#define TWAM3 4 -+#define TWAM4 5 -+#define TWAM5 6 -+#define TWAM6 7 -+ -+#define PDSCR _SFR_MEM8(0x1EF) -+#define PDSC0 0 -+#define PDSC1 1 -+#define PDSC2 2 -+#define PDSC3 3 -+#define PDSC4 4 -+ -+#define TMOCR _SFR_MEM8(0x1F0) -+#define TO1PIS0 0 -+#define TO1PIS1 1 -+#define TO2PIS0 2 -+#define TO2PIS1 3 -+#define TO3PIS0 4 -+#define TO3PIS1 5 -+#define TO4PIS0 6 -+#define TO4PIS1 7 -+ -+#define SRCCAL _SFR_MEM8(0x1F1) -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCI0_vect _VECTOR(3) -+#define PCI0_vect_num 3 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCI1_vect _VECTOR(4) -+#define PCI1_vect_num 4 -+ -+/* Voltage Monitoring Interrupt */ -+#define VMON_vect _VECTOR(5) -+#define VMON_vect_num 5 -+ -+/* AVCC Reset Interrupt */ -+#define AVCCR_vect _VECTOR(6) -+#define AVCCR_vect_num 6 -+ -+/* AVCC Low Interrupt */ -+#define AVCCL_vect _VECTOR(7) -+#define AVCCL_vect_num 7 -+ -+/* Timer0 Interval Interrupt */ -+#define T0INT_vect _VECTOR(8) -+#define T0INT_vect_num 8 -+ -+/* Timer/Counter1 Compare Match Interrupt */ -+#define T1COMP_vect _VECTOR(9) -+#define T1COMP_vect_num 9 -+ -+/* Timer/Counter1 Overflow Interrupt */ -+#define T1OVF_vect _VECTOR(10) -+#define T1OVF_vect_num 10 -+ -+/* Timer/Counter2 Compare Match Interrupt */ -+#define T2COMP_vect _VECTOR(11) -+#define T2COMP_vect_num 11 -+ -+/* Timer/Counter2 Overflow Interrupt */ -+#define T2OVF_vect _VECTOR(12) -+#define T2OVF_vect_num 12 -+ -+/* Timer/Counter3 Capture Event Interrupt */ -+#define T3CAP_vect _VECTOR(13) -+#define T3CAP_vect_num 13 -+ -+/* Timer/Counter3 Compare Match Interrupt */ -+#define T3COMP_vect _VECTOR(14) -+#define T3COMP_vect_num 14 -+ -+/* Timer/Counter3 Overflow Interrupt */ -+#define T3OVF_vect _VECTOR(15) -+#define T3OVF_vect_num 15 -+ -+/* Timer/Counter4 Capture Event Interrupt */ -+#define T4CAP_vect _VECTOR(16) -+#define T4CAP_vect_num 16 -+ -+/* Timer/Counter4 Compare Match Interrupt */ -+#define T4COMP_vect _VECTOR(17) -+#define T4COMP_vect_num 17 -+ -+/* Timer/Counter4 Overflow Interrupt */ -+#define T4OVF_vect _VECTOR(18) -+#define T4OVF_vect_num 18 -+ -+/* Timer/Counter5 Compare Match Interrupt */ -+#define T5COMP_vect _VECTOR(19) -+#define T5COMP_vect_num 19 -+ -+/* Timer/Counter5 Overflow Interrupt */ -+#define T5OVF_vect _VECTOR(20) -+#define T5OVF_vect_num 20 -+ -+/* SPI Serial Transfer Complete Interrupt */ -+#define SPI_vect _VECTOR(21) -+#define SPI_vect_num 21 -+ -+/* SPI Rx Buffer Interrupt */ -+#define SRX_FIFO_vect _VECTOR(22) -+#define SRX_FIFO_vect_num 22 -+ -+/* SPI Tx Buffer Interrupt */ -+#define STX_FIFO_vect _VECTOR(23) -+#define STX_FIFO_vect_num 23 -+ -+/* Sequencer State Machine Interrupt */ -+#define SSM_vect _VECTOR(24) -+#define SSM_vect_num 24 -+ -+/* Data FIFO fill level reached Interrupt */ -+#define DFFLR_vect _VECTOR(25) -+#define DFFLR_vect_num 25 -+ -+/* Data FIFO overflow or underflow error Interrupt */ -+#define DFOUE_vect _VECTOR(26) -+#define DFOUE_vect_num 26 -+ -+/* RSSI/Preamble FIFO fill level reached Interrupt */ -+#define SFFLR_vect _VECTOR(27) -+#define SFFLR_vect_num 27 -+ -+/* RSSI/Preamble FIFO overflow or underflow error Interrupt */ -+#define SFOUE_vect _VECTOR(28) -+#define SFOUE_vect_num 28 -+ -+/* Tx Modulator Telegram Finish Interrupt */ -+#define TMTCF_vect _VECTOR(29) -+#define TMTCF_vect_num 29 -+ -+/* AES Krypto Unit Interrupt */ -+#define AES_vect _VECTOR(30) -+#define AES_vect_num 30 -+ -+/* Transponder Mode Interrupt */ -+#define TPINT_vect _VECTOR(31) -+#define TPINT_vect_num 31 -+ -+/* Transponder Timeout Error Interrupt */ -+#define TPTOERR_vect _VECTOR(32) -+#define TPTOERR_vect_num 32 -+ -+/* LF receiver Identifier 0 Interrupt */ -+#define LFID0INT_vect _VECTOR(33) -+#define LFID0INT_vect_num 33 -+ -+/* LF receiver Identifier 1 Interrupt */ -+#define LFID1INT_vect _VECTOR(34) -+#define LFID1INT_vect_num 34 -+ -+/* LF receiver Frame End Interrupt */ -+#define LFFEINT_vect _VECTOR(35) -+#define LFFEINT_vect_num 35 -+ -+/* LF receiver Bit Count Reached Interrupt */ -+#define LFBCR_vect _VECTOR(36) -+#define LFBCR_vect_num 36 -+ -+/* LF receiver PreBurst Detected Interrupt */ -+#define LFPBD_vect _VECTOR(37) -+#define LFPBD_vect_num 37 -+ -+/* LF receiver Decoder Error Interrupt */ -+#define LFDE_vect _VECTOR(38) -+#define LFDE_vect_num 38 -+ -+/* LF receiver End of Telegram Interrupt */ -+#define LFEOT_vect _VECTOR(39) -+#define LFEOT_vect_num 39 -+ -+/* LF receiver Timer Compare Match Interrupt */ -+#define LFTCOR_vect _VECTOR(40) -+#define LFTCOR_vect_num 40 -+ -+/* LF receiver RSSI measurement Interrupt */ -+#define LFRSCO_vect _VECTOR(41) -+#define LFRSCO_vect_num 41 -+ -+/* Protocol Handler FIFO Fill Level Reached Interrupt */ -+#define PHFFLR_vect _VECTOR(42) -+#define PHFFLR_vect_num 42 -+ -+/* Protocol Handler FIFO Overflow or Underflow Error Interrupt */ -+#define PHFOUE_vect _VECTOR(43) -+#define PHFOUE_vect_num 43 -+ -+/* External input Clock monitoring Interrupt */ -+#define EXCM_vect _VECTOR(44) -+#define EXCM_vect_num 44 -+ -+/* EEPROM Error Correction Interrupt */ -+#define E2CINT_vect _VECTOR(45) -+#define E2CINT_vect_num 45 -+ -+/* EEPROM Ready Interrupt */ -+#define ERDY_vect _VECTOR(46) -+#define ERDY_vect_num 46 -+ -+/* Store Program Memory Ready */ -+#define SPMR_vect _VECTOR(47) -+#define SPMR_vect_num 47 -+ -+/* TWI Interrupt */ -+#define TWI_vect _VECTOR(48) -+#define TWI_vect_num 48 -+ -+#define _VECTORS_SIZE 196 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 32 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0xFFFF -+#define RAMSTART 0x0200 -+#define RAMSIZE 1024 -+#define RAMEND 0x05FF -+#define E2START 0 -+#define E2SIZE 2304 -+#define E2PAGESIZE 16 -+#define E2END 0x08FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 1 -+ -+/* Fuse Byte */ -+#define FUSE_CKDIV8 (unsigned char)~_BV(128) -+#define FUSE_DWEN (unsigned char)~_BV(64) -+#define FUSE_SPIEN (unsigned char)~_BV(32) -+#define FUSE_WDTON (unsigned char)~_BV(16) -+#define FUSE_EESAVE (unsigned char)~_BV(8) -+#define FUSE_BOOTRST (unsigned char)~_BV(4) -+#define FUSE_EEACC (unsigned char)~_BV(2) -+#define FUSE_EXTCLKEN (unsigned char)~_BV(1) -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x95 -+#define SIGNATURE_2 0x69 -+ -+ -+#endif /* #ifdef _AVR_ATA5702M322_H_INCLUDED */ -+ -diff --git a/include/avr/ioa5781.h b/include/avr/ioa5781.h -new file mode 100644 -index 0000000..95bd770 ---- /dev/null -+++ b/include/avr/ioa5781.h -@@ -0,0 +1,1781 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATA5781_H_INCLUDED -+#define _AVR_ATA5781_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "ioa5781.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PRR0 _SFR_IO8(0x01) -+#define PRSPI 0 -+#define PRRXDC 1 -+#define PRTXDC 2 -+#define PRCRC 3 -+#define PRVM 4 -+#define PRCO 5 -+ -+#define PRR1 _SFR_IO8(0x02) -+#define PRT1 0 -+#define PRT2 1 -+#define PRT3 2 -+#define PRT4 3 -+#define PRT5 4 -+ -+#define PRR2 _SFR_IO8(0x03) -+#define PRXB 0 -+#define PRXA 1 -+#define PRSF 2 -+#define PRDF 3 -+#define PRIDS 4 -+#define PRRS 5 -+#define PRTM 6 -+#define PRSSM 7 -+ -+#define RDPR _SFR_IO8(0x04) -+#define PRPTB 0 -+#define PRPTA 1 -+#define PRFLT 2 -+#define PRTMP 3 -+#define APRPTB 4 -+#define APRPTA 5 -+#define ARDPRF 6 -+#define RDPRF 7 -+ -+#define PINB _SFR_IO8(0x05) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x06) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x07) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x08) -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x09) -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x0A) -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+/* Reserved [0x0B..0x0C] */ -+ -+#define RDSIFR _SFR_IO8(0x0D) -+#define NBITA 0 -+#define NBITB 1 -+#define EOTA 2 -+#define EOTB 3 -+#define SOTA 4 -+#define SOTB 5 -+#define WCOA 6 -+#define WCOB 7 -+ -+#define MCUCR _SFR_IO8(0x0E) -+#define IVCE 0 -+#define IVSEL 1 -+#define SPIIO 2 -+#define ENPS 3 -+#define PUD 4 -+#define PB4HS 5 -+#define PB7LS 6 -+#define PB7HS 7 -+ -+#define PCIFR _SFR_IO8(0x0F) -+#define PCIF0 0 -+#define PCIF1 1 -+ -+#define T0CR _SFR_IO8(0x10) -+#define T0PS0 0 -+#define T0PS1 1 -+#define T0PS2 2 -+#define T0IE 3 -+#define T0PR 4 -+ -+#define T1CR _SFR_IO8(0x11) -+#define T1OTM 0 -+#define T1CTM 1 -+#define T1CRM 2 -+#define T1TOP 4 -+#define T1RES 5 -+#define T1TOS 6 -+#define T1ENA 7 -+ -+#define T2CR _SFR_IO8(0x12) -+#define T2OTM 0 -+#define T2CTM 1 -+#define T2CRM 2 -+#define T2TOP 4 -+#define T2RES 5 -+#define T2TOS 6 -+#define T2ENA 7 -+ -+#define T3CR _SFR_IO8(0x13) -+#define T3OTM 0 -+#define T3CTM 1 -+#define T3CRM 2 -+#define T3CPRM 3 -+#define T3TOP 4 -+#define T3RES 5 -+#define T3TOS 6 -+#define T3ENA 7 -+ -+#define T4CR _SFR_IO8(0x14) -+#define T4OTM 0 -+#define T4CTM 1 -+#define T4CRM 2 -+#define T4CPRM 3 -+#define T4TOP 4 -+#define T4RES 5 -+#define T4TOS 6 -+#define T4ENA 7 -+ -+#define T1IFR _SFR_IO8(0x15) -+#define T1OFF 0 -+#define T1COF 1 -+ -+#define T2IFR _SFR_IO8(0x16) -+#define T2OFF 0 -+#define T2COF 1 -+ -+#define T3IFR _SFR_IO8(0x17) -+#define T3OFF 0 -+#define T3COF 1 -+#define T3ICF 2 -+ -+#define T4IFR _SFR_IO8(0x18) -+#define T4OFF 0 -+#define T4COF 1 -+#define T4ICF 2 -+ -+#define T5IFR _SFR_IO8(0x19) -+#define T5OFF 0 -+#define T5COF 1 -+ -+#define GPIOR0 _SFR_IO8(0x1A) -+ -+#define GPIOR3 _SFR_IO8(0x1B) -+ -+#define GPIOR4 _SFR_IO8(0x1C) -+ -+#define GPIOR5 _SFR_IO8(0x1D) -+ -+#define GPIOR6 _SFR_IO8(0x1E) -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEWE 1 -+#define EEMWE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+#define EEPAGE 6 -+#define NVMBSY 7 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define EEPR _SFR_IO8(0x23) -+#define EEAP0 0 -+#define EEAP1 1 -+#define EEAP2 2 -+#define EEAP3 3 -+ -+#define GPIOR1 _SFR_IO8(0x24) -+ -+#define GPIOR2 _SFR_IO8(0x25) -+ -+#define PCICR _SFR_IO8(0x26) -+#define PCIE0 0 -+#define PCIE1 1 -+ -+#define EIMSK _SFR_IO8(0x27) -+#define INT0 0 -+#define INT1 1 -+ -+#define EIFR _SFR_IO8(0x28) -+#define INTF0 0 -+#define INTF1 1 -+ -+#define CRCDIR _SFR_IO8(0x29) -+ -+#define VMCSR _SFR_IO8(0x2A) -+#define VMLS0 0 -+#define VMLS1 1 -+#define VMLS2 2 -+#define VMLS3 3 -+#define VMIM 4 -+#define VMF 5 -+ -+#define MCUSR _SFR_IO8(0x2B) -+#define PORF 0 -+#define EXTRF 1 -+#define WDRF 3 -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define RXIF 4 -+#define TXIF 5 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+#define T0IFR _SFR_IO8(0x2F) -+#define T0F 0 -+ -+/* Reserved [0x30] */ -+ -+#define DWDR _SFR_IO8(0x31) -+ -+/* Reserved [0x32] */ -+ -+#define RDCR _SFR_IO8(0x33) -+#define RDPU 0 -+#define ADIVEN 1 -+#define RDEN 2 -+ -+#define EOTSA _SFR_IO8(0x34) -+#define CARFA 0 -+#define AMPFA 1 -+#define SYTFA 2 -+#define MANFA 3 -+#define TMOFA 4 -+#define TELRA 5 -+#define RRFA 6 -+#define EOTBF 7 -+ -+#define EOTCA _SFR_IO8(0x35) -+#define CARFEA 0 -+#define AMPFEA 1 -+#define SYTFEA 2 -+#define MANFEA 3 -+#define TMOFEA 4 -+#define TELREA 5 -+#define RRFEA 6 -+#define EOTBFE 7 -+ -+#define EOTSB _SFR_IO8(0x36) -+#define CARFB 0 -+#define AMPFB 1 -+#define SYTFB 2 -+#define MANFB 3 -+#define TMOFB 4 -+#define TELRB 5 -+#define RRFB 6 -+#define EOTAF 7 -+ -+#define EOTCB _SFR_IO8(0x37) -+#define CARFEB 0 -+#define AMPFEB 1 -+#define SYTFEB 2 -+#define MANFEB 3 -+#define TMOFEB 4 -+#define TELREB 5 -+#define RRFEB 6 -+#define EOTAFE 7 -+ -+#define SMCR _SFR_IO8(0x38) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define CMCR _SFR_IO8(0x39) -+#define CMM0 0 -+#define CMM1 1 -+#define CMM2 2 -+#define CCS 3 -+#define SRCD 4 -+#define CMONEN 6 -+#define CMCCE 7 -+ -+#define CMIMR _SFR_IO8(0x3A) -+#define ECIE 0 -+ -+#define CLPR _SFR_IO8(0x3B) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLTPS0 3 -+#define CLTPS1 4 -+#define CLTPS2 5 -+#define CLPCE 7 -+ -+#define SPMCSR _SFR_IO8(0x3C) -+#define SELFPRGEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define SPMIE 7 -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define FSEN _SFR_MEM8(0x60) -+#define SDPU 0 -+#define SDEN 1 -+ -+/* Reserved [0x61..0x63] */ -+ -+#define FFREQ1L _SFR_MEM8(0x64) -+ -+#define FFREQ1M _SFR_MEM8(0x65) -+ -+#define FFREQ1H _SFR_MEM8(0x66) -+ -+#define FFREQ2L _SFR_MEM8(0x67) -+ -+#define FFREQ2M _SFR_MEM8(0x68) -+ -+#define FFREQ2H _SFR_MEM8(0x69) -+ -+/* Reserved [0x6A] */ -+ -+#define EICRA _SFR_MEM8(0x6B) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+ -+#define PCMSK0 _SFR_MEM8(0x6C) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6D) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+ -+#define WDTCR _SFR_MEM8(0x6E) -+#define WDPS0 0 -+#define WDPS1 1 -+#define WDPS2 2 -+#define WDE 3 -+#define WDCE 4 -+ -+#define T1CNT _SFR_MEM8(0x6F) -+ -+#define T1COR _SFR_MEM8(0x70) -+ -+#define T1MR _SFR_MEM8(0x71) -+#define T1CS0 0 -+#define T1CS1 1 -+#define T1PS0 2 -+#define T1PS1 3 -+#define T1PS2 4 -+#define T1PS3 5 -+#define T1DC0 6 -+#define T1DC1 7 -+ -+#define T1IMR _SFR_MEM8(0x72) -+#define T1OIM 0 -+#define T1CIM 1 -+ -+#define T2CNT _SFR_MEM8(0x73) -+ -+#define T2COR _SFR_MEM8(0x74) -+ -+#define T2MR _SFR_MEM8(0x75) -+#define T2CS0 0 -+#define T2CS1 1 -+#define T2PS0 2 -+#define T2PS1 3 -+#define T2PS2 4 -+#define T2PS3 5 -+#define T2DC0 6 -+#define T2DC1 7 -+ -+#define T2IMR _SFR_MEM8(0x76) -+#define T2OIM 0 -+#define T2CIM 1 -+ -+/* Combine T3CNTL and T3CNTH */ -+#define T3CNT _SFR_MEM16(0x77) -+ -+#define T3CNTL _SFR_MEM8(0x77) -+#define T3CNTH _SFR_MEM8(0x78) -+ -+/* Combine T3CORL and T3CORH */ -+#define T3COR _SFR_MEM16(0x79) -+ -+#define T3CORL _SFR_MEM8(0x79) -+#define T3CORH _SFR_MEM8(0x7A) -+ -+/* Combine T3ICRL and T3ICRH */ -+#define T3ICR _SFR_MEM16(0x7B) -+ -+#define T3ICRL _SFR_MEM8(0x7B) -+#define T3ICRH _SFR_MEM8(0x7C) -+ -+#define T3MRA _SFR_MEM8(0x7D) -+#define T3CS0 0 -+#define T3CS1 1 -+#define T3PS0 2 -+#define T3PS1 3 -+#define T3PS2 4 -+ -+#define T3MRB _SFR_MEM8(0x7E) -+#define T3SCE 1 -+#define T3CNC 2 -+#define T3CE0 3 -+#define T3CE1 4 -+#define T3ICS0 5 -+#define T3ICS1 6 -+#define T3ICS2 7 -+ -+#define T3IMR _SFR_MEM8(0x7F) -+#define T3OIM 0 -+#define T3CIM 1 -+#define T3CPIM 2 -+ -+/* Combine T4CNTL and T4CNTH */ -+#define T4CNT _SFR_MEM16(0x80) -+ -+#define T4CNTL _SFR_MEM8(0x80) -+#define T4CNTH _SFR_MEM8(0x81) -+ -+/* Combine T4CORL and T4CORH */ -+#define T4COR _SFR_MEM16(0x82) -+ -+#define T4CORL _SFR_MEM8(0x82) -+#define T4CORH _SFR_MEM8(0x83) -+ -+/* Combine T4ICRL and T4ICRH */ -+#define T4ICR _SFR_MEM16(0x84) -+ -+#define T4ICRL _SFR_MEM8(0x84) -+#define T4ICRH _SFR_MEM8(0x85) -+ -+#define T4MRA _SFR_MEM8(0x86) -+#define T4CS0 0 -+#define T4CS1 1 -+#define T4PS0 2 -+#define T4PS1 3 -+#define T4PS2 4 -+ -+#define T4MRB _SFR_MEM8(0x87) -+#define T4SCE 1 -+#define T4CNC 2 -+#define T4CE0 3 -+#define T4CE1 4 -+#define T4ICS0 5 -+#define T4ICS1 6 -+#define T4ICS2 7 -+ -+#define T4IMR _SFR_MEM8(0x88) -+#define T4OIM 0 -+#define T4CIM 1 -+#define T4CPIM 2 -+ -+/* Reserved [0x89] */ -+ -+/* Combine T5OCRL and T5OCRH */ -+#define T5OCR _SFR_MEM16(0x8A) -+ -+#define T5OCRL _SFR_MEM8(0x8A) -+#define T5OCRH _SFR_MEM8(0x8B) -+ -+#define T5CCR _SFR_MEM8(0x8C) -+#define T5CS0 0 -+#define T5CS1 1 -+#define T5CS2 2 -+#define T5CTC 3 -+ -+/* Combine T5CNTL and T5CNTH */ -+#define T5CNT _SFR_MEM16(0x8D) -+ -+#define T5CNTL _SFR_MEM8(0x8D) -+#define T5CNTH _SFR_MEM8(0x8E) -+ -+#define T5IMR _SFR_MEM8(0x8F) -+#define T5OIM 0 -+#define T5CIM 1 -+ -+#define GTCCR _SFR_MEM8(0x90) -+#define PSR10 0 -+#define TSM 7 -+ -+#define SOTSB _SFR_MEM8(0x91) -+#define CAROB 0 -+#define AMPOB 1 -+#define SYTOB 2 -+#define MANOB 3 -+#define WUPOB 4 -+#define SFIDOB 5 -+#define RROB 6 -+#define WCOAO 7 -+ -+#define SOTSA _SFR_MEM8(0x92) -+#define CAROA 0 -+#define AMPOA 1 -+#define SYTOA 2 -+#define MANOA 3 -+#define WUPOA 4 -+#define SFIDOA 5 -+#define RROA 6 -+#define WCOBO 7 -+ -+#define SOTCB _SFR_MEM8(0x93) -+#define CAROEB 0 -+#define AMPOEB 1 -+#define SYTOEB 2 -+#define MANOEB 3 -+#define WUPEB 4 -+#define SFIDEB 5 -+#define RROEB 6 -+#define WCOAOE 7 -+ -+#define SOTCA _SFR_MEM8(0x94) -+#define CAROEA 0 -+#define AMPOEA 1 -+#define SYTOEA 2 -+#define MANOEA 3 -+#define WUPEA 4 -+#define SFIDEA 5 -+#define RROEA 6 -+#define WCOBOE 7 -+ -+#define TESRB _SFR_MEM8(0x95) -+#define CRCOB 0 -+#define EOTLB0 1 -+#define EOTLB1 2 -+ -+#define TESRA _SFR_MEM8(0x96) -+#define CRCOA 0 -+#define EOTLA0 1 -+#define EOTLA1 2 -+ -+/* Reserved [0x97] */ -+ -+#define RDSIMR _SFR_MEM8(0x98) -+#define NBITAM 0 -+#define NBITBM 1 -+#define EOTAM 2 -+#define EOTBM 3 -+#define SOTAM 4 -+#define SOTBM 5 -+#define WCOAM 6 -+#define WCOBM 7 -+ -+#define RDOCR _SFR_MEM8(0x99) -+#define TMDS0 1 -+#define TMDS1 2 -+#define ETRPA 3 -+#define ETRPB 4 -+#define RDSIDA 5 -+#define RDSIDB 6 -+ -+/* Reserved [0x9A] */ -+ -+#define TEMPL _SFR_MEM8(0x9B) -+ -+#define TEMPH _SFR_MEM8(0x9C) -+ -+#define SYCB _SFR_MEM8(0x9D) -+#define SYCSB0 0 -+#define SYCSB1 1 -+#define SYCSB2 2 -+#define SYCSB3 3 -+#define SYTLB0 4 -+#define SYTLB1 5 -+#define SYTLB2 6 -+#define SYTLB3 7 -+ -+#define SYCA _SFR_MEM8(0x9E) -+#define SYCSA0 0 -+#define SYCSA1 1 -+#define SYCSA2 2 -+#define SYCSA3 3 -+#define SYTLA0 4 -+#define SYTLA1 5 -+#define SYTLA2 6 -+#define SYTLA3 7 -+ -+#define RXFOB _SFR_MEM8(0x9F) -+ -+#define RXFOA _SFR_MEM8(0xA0) -+ -+#define DMMB _SFR_MEM8(0xA1) -+#define DMATB0 0 -+#define DMATB1 1 -+#define DMATB2 2 -+#define DMATB3 3 -+#define DMATB4 4 -+#define DMPB 5 -+#define DMHB 6 -+#define DMNEB 7 -+ -+#define DMMA _SFR_MEM8(0xA2) -+#define DMATA0 0 -+#define DMATA1 1 -+#define DMATA2 2 -+#define DMATA3 3 -+#define DMATA4 4 -+#define DMPA 5 -+#define DMHA 6 -+#define DMNEA 7 -+ -+#define DMCDB _SFR_MEM8(0xA3) -+#define DMCLB0 0 -+#define DMCLB1 1 -+#define DMCLB2 2 -+#define DMCLB3 3 -+#define DMCLB4 4 -+#define DMCTB0 5 -+#define DMCTB1 6 -+#define DMCTB2 7 -+ -+#define DMCDA _SFR_MEM8(0xA4) -+#define DMCLA0 0 -+#define DMCLA1 1 -+#define DMCLA2 2 -+#define DMCLA3 3 -+#define DMCLA4 4 -+#define DMCTA0 5 -+#define DMCTA1 6 -+#define DMCTA2 7 -+ -+#define DMCRB _SFR_MEM8(0xA5) -+#define DMPGB0 0 -+#define DMPGB1 1 -+#define DMPGB2 2 -+#define DMPGB3 3 -+#define DMPGB4 4 -+#define SASKB 5 -+#define SY1TB 6 -+#define DMARB 7 -+ -+#define DMCRA _SFR_MEM8(0xA6) -+#define DMPGA0 0 -+#define DMPGA1 1 -+#define DMPGA2 2 -+#define DMPGA3 3 -+#define DMPGA4 4 -+#define SASKA 5 -+#define SY1TA 6 -+#define DMARA 7 -+ -+#define DMDRB _SFR_MEM8(0xA7) -+#define DMAB0 0 -+#define DMAB1 1 -+#define DMAB2 2 -+#define DMAB3 3 -+#define DMDNB0 4 -+#define DMDNB1 5 -+#define DMDNB2 6 -+#define DMDNB3 7 -+ -+#define DMDRA _SFR_MEM8(0xA8) -+#define DMAA0 0 -+#define DMAA1 1 -+#define DMAA2 2 -+#define DMAA3 3 -+#define DMDNA0 4 -+#define DMDNA1 5 -+#define DMDNA2 6 -+#define DMDNA3 7 -+ -+#define CHCR _SFR_MEM8(0xA9) -+#define BWM0 0 -+#define BWM1 1 -+#define BWM2 2 -+#define BWM3 3 -+ -+#define CHDN _SFR_MEM8(0xAA) -+#define BBDN0 0 -+#define BBDN1 1 -+#define BBDN2 2 -+#define BBDN3 3 -+#define BBDN4 4 -+#define ADCDN 5 -+ -+#define SFIDCB _SFR_MEM8(0xAB) -+#define SFIDTB0 0 -+#define SFIDTB1 1 -+#define SFIDTB2 2 -+#define SFIDTB3 3 -+#define SFIDTB4 4 -+#define SEMEB 7 -+ -+#define SFIDLB _SFR_MEM8(0xAC) -+#define SFIDLB0 0 -+#define SFIDLB1 1 -+#define SFIDLB2 2 -+#define SFIDLB3 3 -+#define SFIDLB4 4 -+#define SFIDLB5 5 -+ -+#define WUPTB _SFR_MEM8(0xAD) -+#define WUPTB0 0 -+#define WUPTB1 1 -+#define WUPTB2 2 -+#define WUPTB3 3 -+#define WUPTB4 4 -+ -+#define WUPLB _SFR_MEM8(0xAE) -+#define WUPLB0 0 -+#define WUPLB1 1 -+#define WUPLB2 2 -+#define WUPLB3 3 -+#define WUPLB4 4 -+#define WUPLB5 5 -+ -+#define SFID1B _SFR_MEM8(0xAF) -+ -+#define SFID2B _SFR_MEM8(0xB0) -+ -+#define SFID3B _SFR_MEM8(0xB1) -+ -+#define SFID4B _SFR_MEM8(0xB2) -+ -+#define WUP1B _SFR_MEM8(0xB3) -+ -+#define WUP2B _SFR_MEM8(0xB4) -+ -+#define WUP3B _SFR_MEM8(0xB5) -+ -+#define WUP4B _SFR_MEM8(0xB6) -+ -+#define SFIDCA _SFR_MEM8(0xB7) -+#define SFIDTA0 0 -+#define SFIDTA1 1 -+#define SFIDTA2 2 -+#define SFIDTA3 3 -+#define SFIDTA4 4 -+#define SEMEA 7 -+ -+#define SFIDLA _SFR_MEM8(0xB8) -+#define SFIDLA0 0 -+#define SFIDLA1 1 -+#define SFIDLA2 2 -+#define SFIDLA3 3 -+#define SFIDLA4 4 -+#define SFIDLA5 5 -+ -+#define WUPTA _SFR_MEM8(0xB9) -+#define WUPTA0 0 -+#define WUPTA1 1 -+#define WUPTA2 2 -+#define WUPTA3 3 -+#define WUPTA4 4 -+ -+#define WUPLA _SFR_MEM8(0xBA) -+#define WUPLA0 0 -+#define WUPLA1 1 -+#define WUPLA2 2 -+#define WUPLA3 3 -+#define WUPLA4 4 -+#define WUPLA5 5 -+ -+#define SFID1A _SFR_MEM8(0xBB) -+ -+#define SFID2A _SFR_MEM8(0xBC) -+ -+#define SFID3A _SFR_MEM8(0xBD) -+ -+#define SFID4A _SFR_MEM8(0xBE) -+ -+#define WUP1A _SFR_MEM8(0xBF) -+ -+#define WUP2A _SFR_MEM8(0xC0) -+ -+#define WUP3A _SFR_MEM8(0xC1) -+ -+#define WUP4A _SFR_MEM8(0xC2) -+ -+#define CLKOD _SFR_MEM8(0xC3) -+ -+#define CLKOCR _SFR_MEM8(0xC4) -+#define CLKOS0 0 -+#define CLKOS1 1 -+#define CLKOEN 2 -+ -+#define XFUSE _SFR_MEM8(0xC5) -+ -+#define SRCCAL _SFR_MEM8(0xC6) -+#define SRCCAL0 0 -+#define SRCCAL1 1 -+#define SRCCAL2 2 -+#define SRCCAL3 3 -+#define SRCCAL4 4 -+#define SRCCAL5 5 -+#define SRCTC0 6 -+#define SRCTC1 7 -+ -+#define FRCCAL _SFR_MEM8(0xC7) -+#define FRCCAL0 0 -+#define FRCCAL1 1 -+#define FRCCAL2 2 -+#define FRCCAL3 3 -+#define FRCCAL4 4 -+#define FRCTC 5 -+ -+#define CMSR _SFR_MEM8(0xC8) -+#define ECF 0 -+ -+#define CMOCR _SFR_MEM8(0xC9) -+#define FRCAO 0 -+#define SRCAO 1 -+#define FRCACT 2 -+#define SRCACT 3 -+ -+#define SUPFR _SFR_MEM8(0xCA) -+#define AVCCRF 0 -+#define AVCCLF 1 -+ -+#define SUPCR _SFR_MEM8(0xCB) -+#define AVCCRM 0 -+#define AVCCLM 1 -+#define PVEN 2 -+#define DVDIS 4 -+#define AVEN 5 -+#define AVDIC 6 -+ -+/* Reserved [0xCC] */ -+ -+#define SUPCA2 _SFR_MEM8(0xCD) -+#define BGCAL0 0 -+#define BGCAL1 1 -+#define BGCAL2 2 -+#define BGCAL3 3 -+ -+#define SUPCA3 _SFR_MEM8(0xCE) -+#define ACAL4 0 -+#define ACAL5 1 -+#define ACAL6 2 -+#define ACAL7 3 -+#define DCAL4 4 -+#define DCAL5 5 -+#define DCAL6 6 -+ -+#define SUPCA4 _SFR_MEM8(0xCF) -+#define ACAL0 0 -+#define ACAL1 1 -+#define ACAL2 2 -+#define ACAL3 3 -+#define DCAL0 4 -+#define DCAL1 5 -+#define DCAL2 6 -+#define DCAL3 7 -+ -+#define CALRDY _SFR_MEM8(0xD0) -+ -+#define VMCAL _SFR_MEM8(0xD1) -+#define VMCAL0 0 -+#define VMCAL1 1 -+#define VMCAL2 2 -+ -+#define DFS _SFR_MEM8(0xD2) -+#define DFFLRF 0 -+#define DFUFL 1 -+#define DFOFL 2 -+ -+/* Combine DFTLL and DFTLH */ -+#define DFTL _SFR_MEM16(0xD3) -+ -+#define DFTLL _SFR_MEM8(0xD3) -+#define DFTLH _SFR_MEM8(0xD4) -+ -+#define DFL _SFR_MEM8(0xD5) -+#define DFFLS0 0 -+#define DFFLS1 1 -+#define DFFLS2 2 -+#define DFFLS3 3 -+#define DFFLS4 4 -+#define DFFLS5 5 -+#define DFCLR 7 -+ -+#define DFWP _SFR_MEM8(0xD6) -+#define DFWP0 0 -+#define DFWP1 1 -+#define DFWP2 2 -+#define DFWP3 3 -+#define DFWP4 4 -+#define DFWP5 5 -+ -+#define DFRP _SFR_MEM8(0xD7) -+#define DFRP0 0 -+#define DFRP1 1 -+#define DFRP2 2 -+#define DFRP3 3 -+#define DFRP4 4 -+#define DFRP5 5 -+ -+#define DFD _SFR_MEM8(0xD8) -+ -+#define DFI _SFR_MEM8(0xD9) -+#define DFFLIM 0 -+#define DFERIM 1 -+ -+#define DFC _SFR_MEM8(0xDA) -+#define DFFLC0 0 -+#define DFFLC1 1 -+#define DFFLC2 2 -+#define DFFLC3 3 -+#define DFFLC4 4 -+#define DFFLC5 5 -+#define DFDRA 7 -+ -+#define SFS _SFR_MEM8(0xDB) -+#define SFFLRF 0 -+#define SFUFL 1 -+#define SFOFL 2 -+ -+#define SFL _SFR_MEM8(0xDC) -+#define SFFLS0 0 -+#define SFFLS1 1 -+#define SFFLS2 2 -+#define SFFLS3 3 -+#define SFFLS4 4 -+#define SFCLR 7 -+ -+#define SFWP _SFR_MEM8(0xDD) -+#define SFWP0 0 -+#define SFWP1 1 -+#define SFWP2 2 -+#define SFWP3 3 -+#define SFWP4 4 -+ -+#define SFRP _SFR_MEM8(0xDE) -+#define SFRP0 0 -+#define SFRP1 1 -+#define SFRP2 2 -+#define SFRP3 3 -+#define SFRP4 4 -+ -+#define SFD _SFR_MEM8(0xDF) -+ -+#define SFI _SFR_MEM8(0xE0) -+#define SFFLIM 0 -+#define SFERIM 1 -+ -+#define SFC _SFR_MEM8(0xE1) -+#define SFFLC0 0 -+#define SFFLC1 1 -+#define SFFLC2 2 -+#define SFFLC3 3 -+#define SFFLC4 4 -+#define SFDRA 7 -+ -+#define SSMCR _SFR_MEM8(0xE2) -+#define SSMTX 0 -+#define SSMTM 1 -+#define SSMTGE 2 -+#define SSMTPE 3 -+#define SSMPVE 4 -+#define SSMTAE 5 -+#define SETRPA 6 -+#define SETRPB 7 -+ -+#define SSMRCR _SFR_MEM8(0xE3) -+#define SSMPA 0 -+#define SSMPB 1 -+#define SSMADA 2 -+#define SSMADB 3 -+#define SSMPVS 4 -+#define SSMIFA 5 -+#define SSMIDSE 6 -+#define SSMTMOE 7 -+ -+#define SSMFBR _SFR_MEM8(0xE4) -+#define SSMFID0 0 -+#define SSMFID1 1 -+#define SSMFID2 2 -+#define SSMDFDT 3 -+#define SSMHADT 4 -+#define SSMPLDT 5 -+ -+#define SSMRR _SFR_MEM8(0xE5) -+#define SSMR 0 -+#define SSMST 1 -+ -+#define SSMSR _SFR_MEM8(0xE6) -+#define SSMESM0 0 -+#define SSMESM1 1 -+#define SSMESM2 2 -+#define SSMESM3 3 -+#define SSMERR 7 -+ -+#define SSMIFR _SFR_MEM8(0xE7) -+#define SSMIF 0 -+ -+#define SSMIMR _SFR_MEM8(0xE8) -+#define SSMIM 0 -+ -+#define MSMSTR _SFR_MEM8(0xE9) -+#define SSMMST0 0 -+#define SSMMST1 1 -+#define SSMMST2 2 -+#define SSMMST3 3 -+#define SSMMST4 4 -+ -+#define SSMSTR _SFR_MEM8(0xEA) -+#define SSMSTA0 0 -+#define SSMSTA1 1 -+#define SSMSTA2 2 -+#define SSMSTA3 3 -+#define SSMSTA4 4 -+#define SSMSTA5 5 -+ -+#define SSMXSR _SFR_MEM8(0xEB) -+#define SSMSTB0 0 -+#define SSMSTB1 1 -+#define SSMSTB2 2 -+#define SSMSTB3 3 -+#define SSMSTB4 4 -+#define SSMSTB5 5 -+ -+#define MSMCR1 _SFR_MEM8(0xEC) -+#define MSMSM00 0 -+#define MSMSM01 1 -+#define MSMSM02 2 -+#define MSMSM03 3 -+#define MSMSM10 4 -+#define MSMSM11 5 -+#define MSMSM12 6 -+#define MSMSM13 7 -+ -+#define MSMCR2 _SFR_MEM8(0xED) -+#define MSMSM20 0 -+#define MSMSM21 1 -+#define MSMSM22 2 -+#define MSMSM23 3 -+#define MSMSM30 4 -+#define MSMSM31 5 -+#define MSMSM32 6 -+#define MSMSM33 7 -+ -+#define MSMCR3 _SFR_MEM8(0xEE) -+#define MSMSM40 0 -+#define MSMSM41 1 -+#define MSMSM42 2 -+#define MSMSM43 3 -+#define MSMSM50 4 -+#define MSMSM51 5 -+#define MSMSM52 6 -+#define MSMSM53 7 -+ -+#define MSMCR4 _SFR_MEM8(0xEF) -+#define MSMSM60 0 -+#define MSMSM61 1 -+#define MSMSM62 2 -+#define MSMSM63 3 -+#define MSMSM70 4 -+#define MSMSM71 5 -+#define MSMSM72 6 -+#define MSMSM73 7 -+ -+#define GTCR _SFR_MEM8(0xF0) -+#define RXTEHA 0 -+#define GAPMA 1 -+#define DARA 2 -+#define IWUPA 3 -+#define RXTEHB 4 -+#define GAPMB 5 -+#define DARB 6 -+#define IWUPB 7 -+ -+#define SOTC1A _SFR_MEM8(0xF1) -+#define CAROEA1 0 -+#define AMPOEA1 1 -+#define SYTOEA1 2 -+#define MANOEA1 3 -+#define WUPEA1 4 -+#define SFIDEA1 5 -+#define RROEA1 6 -+#define WCOBOE1 7 -+ -+#define SOTC2A _SFR_MEM8(0xF2) -+#define CAROEA2 0 -+#define AMPOEA2 1 -+#define SYTOEA2 2 -+#define MANOEA2 3 -+#define WUPEA2 4 -+#define SFIDEA2 5 -+#define RROEA2 6 -+#define WCOBOE2 7 -+ -+#define SOTC1B _SFR_MEM8(0xF3) -+#define CAROEB1 0 -+#define AMPOEB1 1 -+#define SYTOEB1 2 -+#define MANOEB1 3 -+#define WUPEB1 4 -+#define SFIDEB1 5 -+#define RROEB1 6 -+#define WCOAOE1 7 -+ -+#define SOTC2B _SFR_MEM8(0xF4) -+#define CAROEB2 0 -+#define AMPOEB2 1 -+#define SYTOEB2 2 -+#define MANOEB2 3 -+#define WUPEB2 4 -+#define SFIDEB2 5 -+#define RROEB2 6 -+#define WCOAOE2 7 -+ -+#define EOTC1A _SFR_MEM8(0xF5) -+#define CARFEA1 0 -+#define AMPFEA1 1 -+#define SYTFEA1 2 -+#define MANFEA1 3 -+#define TMOFEA1 4 -+#define TELREA1 5 -+#define RRFEA1 6 -+#define EOTBFE1 7 -+ -+#define EOTC2A _SFR_MEM8(0xF6) -+#define CARFEA2 0 -+#define AMPFEA2 1 -+#define SYTFEA2 2 -+#define MANFEA2 3 -+#define TMOFEA2 4 -+#define TELREA2 5 -+#define RRFEA2 6 -+#define EOTBFE2 7 -+ -+#define EOTC3A _SFR_MEM8(0xF7) -+#define CARFEA3 0 -+#define AMPFEA3 1 -+#define SYTFEA3 2 -+#define MANFEA3 3 -+#define TMOFEA3 4 -+#define TELREA3 5 -+#define RRFEA3 6 -+#define EOTBFE3 7 -+ -+#define EOTC1B _SFR_MEM8(0xF8) -+#define CARFEB1 0 -+#define AMPFEB1 1 -+#define SYTFEB1 2 -+#define MANFEB1 3 -+#define TMOFEB1 4 -+#define TELREB1 5 -+#define RRFEB1 6 -+#define EOTAFE1 7 -+ -+#define EOTC2B _SFR_MEM8(0xF9) -+#define CARFEB2 0 -+#define AMPFEB2 1 -+#define SYTFEB2 2 -+#define MANFEB2 3 -+#define TMOFEB2 4 -+#define TELREB2 5 -+#define RRFEB2 6 -+#define EOTAFE2 7 -+ -+#define EOTC3B _SFR_MEM8(0xFA) -+#define CARFEB3 0 -+#define AMPFEB3 1 -+#define SYTFEB3 2 -+#define MANFEB3 3 -+#define TMOFEB3 4 -+#define TELREB3 5 -+#define RRFEB3 6 -+#define EOTAFE3 7 -+ -+#define WCOTOA _SFR_MEM8(0xFB) -+ -+#define WCOTOB _SFR_MEM8(0xFC) -+ -+#define SOTTOA _SFR_MEM8(0xFD) -+ -+#define SOTTOB _SFR_MEM8(0xFE) -+ -+#define SSMFCR _SFR_MEM8(0xFF) -+#define SSMIDSO 0 -+#define SSMIDSF 1 -+ -+#define FESR _SFR_MEM8(0x100) -+#define LBSAT 0 -+#define HBSAT 1 -+#define XRDY 2 -+#define PLCK 3 -+ -+#define FEEN1 _SFR_MEM8(0x101) -+#define PLEN 0 -+#define PLCAL 1 -+#define XTOEN 2 -+#define LNAEN 3 -+#define ADEN 4 -+#define ADCLK 5 -+#define PLSP1 6 -+#define ATEN 7 -+ -+#define FEEN2 _SFR_MEM8(0x102) -+#define SDRX 0 -+#define SDRX2 1 -+#define PAEN 2 -+#define TMPM 3 -+#define PLPEN 4 -+#define XTPEN 5 -+ -+#define FELNA _SFR_MEM8(0x103) -+#define LBH0 0 -+#define LBH1 1 -+#define LBH2 2 -+#define LBH3 3 -+#define LBL0 4 -+#define LBL1 5 -+#define LBL2 6 -+#define LBL3 7 -+ -+/* Reserved [0x104..0x105] */ -+ -+#define FEVCT _SFR_MEM8(0x106) -+#define FEVCT0 0 -+#define FEVCT1 1 -+#define FEVCT2 2 -+#define FEVCT3 3 -+ -+#define FEBT _SFR_MEM8(0x107) -+#define CTN20 0 -+#define CTN21 1 -+#define RTN20 2 -+#define RTN21 3 -+ -+#define FEMS _SFR_MEM8(0x108) -+#define PLLS0 0 -+#define PLLS1 1 -+#define PLLS2 2 -+#define PLLS3 3 -+#define PLLM0 4 -+#define PLLM1 5 -+#define PLLM2 6 -+#define PLLM3 7 -+ -+#define FETN4 _SFR_MEM8(0x109) -+#define CTN40 0 -+#define CTN41 1 -+#define CTN42 2 -+#define CTN43 3 -+#define RTN40 4 -+#define RTN41 5 -+#define RTN42 6 -+#define RTN43 7 -+ -+#define FECR _SFR_MEM8(0x10A) -+#define LBNHB 0 -+#define S4N3 1 -+#define ANDP 2 -+#define ADHS 3 -+#define PLCKG 4 -+#define ANPS 5 -+ -+#define FEVCO _SFR_MEM8(0x10B) -+#define CPCC0 0 -+#define CPCC1 1 -+#define CPCC2 2 -+#define CPCC3 3 -+#define VCOB0 4 -+#define VCOB1 5 -+#define VCOB2 6 -+#define VCOB3 7 -+ -+#define FEALR _SFR_MEM8(0x10C) -+#define RNGE0 0 -+#define RNGE1 1 -+ -+#define FEANT _SFR_MEM8(0x10D) -+#define LVLC0 0 -+#define LVLC1 1 -+#define LVLC2 2 -+#define LVLC3 3 -+ -+#define FEBIA _SFR_MEM8(0x10E) -+#define IFAEN 7 -+ -+/* Reserved [0x10F..0x12E] */ -+ -+#define RXBC1 _SFR_MEM8(0x12F) -+#define RXCEA 0 -+#define RXCBLA0 1 -+#define RXCBLA1 2 -+#define RXMSBA 3 -+#define RXCEB 4 -+#define RXCBLB0 5 -+#define RXCBLB1 6 -+#define RXMSBB 7 -+ -+#define RXBC2 _SFR_MEM8(0x130) -+#define RXBPB 0 -+#define RXBF 1 -+#define RXBCLR 2 -+ -+#define RXTLLB _SFR_MEM8(0x131) -+ -+#define RXTLHB _SFR_MEM8(0x132) -+#define RXTLHB0 0 -+#define RXTLHB1 1 -+#define RXTLHB2 2 -+#define RXTLHB3 3 -+ -+#define RXCRLB _SFR_MEM8(0x133) -+ -+#define RXCRHB _SFR_MEM8(0x134) -+ -+#define RXCSBB _SFR_MEM8(0x135) -+ -+#define RXCILB _SFR_MEM8(0x136) -+ -+#define RXCIHB _SFR_MEM8(0x137) -+ -+#define RXCPLB _SFR_MEM8(0x138) -+ -+#define RXCPHB _SFR_MEM8(0x139) -+ -+#define RXDSB _SFR_MEM8(0x13A) -+ -+#define RXTLLA _SFR_MEM8(0x13B) -+ -+#define RXTLHA _SFR_MEM8(0x13C) -+#define RXTLHA0 0 -+#define RXTLHA1 1 -+#define RXTLHA2 2 -+#define RXTLHA3 3 -+ -+#define RXCRLA _SFR_MEM8(0x13D) -+ -+#define RXCRHA _SFR_MEM8(0x13E) -+ -+#define RXCSBA _SFR_MEM8(0x13F) -+ -+#define RXCILA _SFR_MEM8(0x140) -+ -+#define RXCIHA _SFR_MEM8(0x141) -+ -+#define RXCPLA _SFR_MEM8(0x142) -+ -+#define RXCPHA _SFR_MEM8(0x143) -+ -+#define RXDSA _SFR_MEM8(0x144) -+ -+#define CRCCR _SFR_MEM8(0x145) -+#define CRCRS 0 -+#define REFLI 1 -+#define REFLO 2 -+ -+#define CRCDOR _SFR_MEM8(0x146) -+ -+#define IDB0 _SFR_MEM8(0x147) -+ -+#define IDB1 _SFR_MEM8(0x148) -+ -+#define IDB2 _SFR_MEM8(0x149) -+ -+#define IDB3 _SFR_MEM8(0x14A) -+ -+#define IDC _SFR_MEM8(0x14B) -+#define IDL0 0 -+#define IDL1 1 -+#define IDBO0 2 -+#define IDBO1 3 -+#define IDFIM 5 -+#define IDCLR 6 -+#define IDCE 7 -+ -+#define IDS _SFR_MEM8(0x14C) -+#define IDOK 0 -+#define IDFULL 1 -+ -+#define RSSAV _SFR_MEM8(0x14D) -+ -+#define RSSPK _SFR_MEM8(0x14E) -+ -+#define RSSL _SFR_MEM8(0x14F) -+ -+#define RSSH _SFR_MEM8(0x150) -+ -+#define RSSC _SFR_MEM8(0x151) -+#define RSUP0 0 -+#define RSUP1 1 -+#define RSUP2 2 -+#define RSUP3 3 -+#define RSWLH 4 -+#define RSHRX 5 -+#define RSPKF 6 -+ -+#define DBCR _SFR_MEM8(0x152) -+#define DBMD 0 -+#define DBCS 1 -+#define DBTMS 2 -+#define DBHA 3 -+ -+#define DBTC _SFR_MEM8(0x153) -+ -+#define DBENB _SFR_MEM8(0x154) -+ -+#define DBENC _SFR_MEM8(0x155) -+ -+#define DBGSW _SFR_MEM8(0x156) -+#define DBGGS0 0 -+#define DBGGS1 1 -+#define DBGGS2 2 -+#define DBGGS3 3 -+#define CPBFOS0 4 -+#define CPBFOS1 5 -+#define CPBF 6 -+#define DBGSE 7 -+ -+#define SFFR _SFR_MEM8(0x157) -+#define RFL0 0 -+#define RFL1 1 -+#define RFL2 2 -+#define RFC 3 -+#define TFL0 4 -+#define TFL1 5 -+#define TFL2 6 -+#define TFC 7 -+ -+#define SFIR _SFR_MEM8(0x158) -+#define RIL0 0 -+#define RIL1 1 -+#define RIL2 2 -+#define SRIE 3 -+#define TIL0 4 -+#define TIL1 5 -+#define TIL2 6 -+#define STIE 7 -+ -+#define EECR2 _SFR_MEM8(0x159) -+#define EEBRE 0 -+ -+#define PGMST _SFR_MEM8(0x15A) -+#define PGMSYN0 0 -+#define PGMSYN1 1 -+#define PGMSYN2 2 -+#define PGMSYN3 3 -+#define PGMSYN4 4 -+ -+#define EEST _SFR_MEM8(0x15B) -+#define EESYN0 0 -+#define EESYN1 1 -+#define EESYN2 2 -+#define EESYN3 3 -+ -+#define RSIFG _SFR_MEM8(0x15C) -+ -+#define RSLDV _SFR_MEM8(0x15D) -+ -+#define RSHDV _SFR_MEM8(0x15E) -+ -+#define RSCOM _SFR_MEM8(0x15F) -+#define RSDC 0 -+#define RSIFC 1 -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCI0_vect _VECTOR(3) -+#define PCI0_vect_num 3 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCI1_vect _VECTOR(4) -+#define PCI1_vect_num 4 -+ -+/* Voltage Monitoring Interrupt */ -+#define VMON_vect _VECTOR(5) -+#define VMON_vect_num 5 -+ -+/* AVCC Reset Interrupt */ -+#define AVCCR_vect _VECTOR(6) -+#define AVCCR_vect_num 6 -+ -+/* AVCC Low Interrupt */ -+#define AVCCL_vect _VECTOR(7) -+#define AVCCL_vect_num 7 -+ -+/* Timer 0 Interval Interrupt */ -+#define T0INT_vect _VECTOR(8) -+#define T0INT_vect_num 8 -+ -+/* Timer/Counter1 Compare Match Interrupt */ -+#define T1COMP_vect _VECTOR(9) -+#define T1COMP_vect_num 9 -+ -+/* Timer/Counter1 Overflow Interrupt */ -+#define T1OVF_vect _VECTOR(10) -+#define T1OVF_vect_num 10 -+ -+/* Timer/Counter2 Compare Match Interrupt */ -+#define T2COMP_vect _VECTOR(11) -+#define T2COMP_vect_num 11 -+ -+/* Timer/Counter2 Overflow Interrupt */ -+#define T2OVF_vect _VECTOR(12) -+#define T2OVF_vect_num 12 -+ -+/* Timer/Counter3 Capture Event Interrupt */ -+#define T3CAP_vect _VECTOR(13) -+#define T3CAP_vect_num 13 -+ -+/* Timer/Counter3 Compare Match Interrupt */ -+#define T3COMP_vect _VECTOR(14) -+#define T3COMP_vect_num 14 -+ -+/* Timer/Counter3 Overflow Interrupt */ -+#define T3OVF_vect _VECTOR(15) -+#define T3OVF_vect_num 15 -+ -+/* Timer/Counter4 Capture Event Interrupt */ -+#define T4CAP_vect _VECTOR(16) -+#define T4CAP_vect_num 16 -+ -+/* Timer/Counter4 Compare Match Interrupt */ -+#define T4COMP_vect _VECTOR(17) -+#define T4COMP_vect_num 17 -+ -+/* Timer/Counter4 Overflow Interrupt */ -+#define T4OVF_vect _VECTOR(18) -+#define T4OVF_vect_num 18 -+ -+/* Timer/Counter5 Compare Match Interrupt */ -+#define T5COMP_vect _VECTOR(19) -+#define T5COMP_vect_num 19 -+ -+/* Timer/Counter5 Overflow Interrupt */ -+#define T5OVF_vect _VECTOR(20) -+#define T5OVF_vect_num 20 -+ -+/* SPI Serial Transfer Complete Interrupt */ -+#define SPI_vect _VECTOR(21) -+#define SPI_vect_num 21 -+ -+/* SPI Rx Buffer Interrupt */ -+#define SRX_FIFO_vect _VECTOR(22) -+#define SRX_FIFO_vect_num 22 -+ -+/* SPI Tx Buffer Interrupt */ -+#define STX_FIFO_vect _VECTOR(23) -+#define STX_FIFO_vect_num 23 -+ -+/* Sequencer State Machine Interrupt */ -+#define SSM_vect _VECTOR(24) -+#define SSM_vect_num 24 -+ -+/* Data FIFO fill level reached Interrupt */ -+#define DFFLR_vect _VECTOR(25) -+#define DFFLR_vect_num 25 -+ -+/* Data FIFO overflow or underflow error Interrupt */ -+#define DFOUE_vect _VECTOR(26) -+#define DFOUE_vect_num 26 -+ -+/* RSSI/Preamble FIFO fill level reached Interrupt */ -+#define SFFLR_vect _VECTOR(27) -+#define SFFLR_vect_num 27 -+ -+/* RSSI/Preamble FIFO overflow or underflow error Interrupt */ -+#define SFOUE_vect _VECTOR(28) -+#define SFOUE_vect_num 28 -+ -+/* Tx Modulator Telegram Finish Interrupt */ -+#define TMTCF_vect _VECTOR(29) -+#define TMTCF_vect_num 29 -+ -+/* UHF receiver wake up ok on Rx path B */ -+#define UHF_WCOB_vect _VECTOR(30) -+#define UHF_WCOB_vect_num 30 -+ -+/* UHF receiver wake up ok on Rx path A */ -+#define UHF_WCOA_vect _VECTOR(31) -+#define UHF_WCOA_vect_num 31 -+ -+/* UHF receiver start of telegram ok on Rx path B */ -+#define UHF_SOTB_vect _VECTOR(32) -+#define UHF_SOTB_vect_num 32 -+ -+/* UHF receiver start of telegram ok on Rx path A */ -+#define UHF_SOTA_vect _VECTOR(33) -+#define UHF_SOTA_vect_num 33 -+ -+/* UHF receiver end of telegram on Rx path B */ -+#define UHF_EOTB_vect _VECTOR(34) -+#define UHF_EOTB_vect_num 34 -+ -+/* UHF receiver end of telegram on Rx path A */ -+#define UHF_EOTA_vect _VECTOR(35) -+#define UHF_EOTA_vect_num 35 -+ -+/* UHF receiver new bit on Rx path B */ -+#define UHF_NBITB_vect _VECTOR(36) -+#define UHF_NBITB_vect_num 36 -+ -+/* UHF receiver new bit on Rx path A */ -+#define UHF_NBITA_vect _VECTOR(37) -+#define UHF_NBITA_vect_num 37 -+ -+/* External input Clock monitoring Interrupt */ -+#define EXCM_vect _VECTOR(38) -+#define EXCM_vect_num 38 -+ -+/* EEPROM Ready Interrupt */ -+#define ERDY_vect _VECTOR(39) -+#define ERDY_vect_num 39 -+ -+/* Store Program Memory Ready */ -+#define SPMR_vect _VECTOR(40) -+#define SPMR_vect_num 40 -+ -+/* IDSCAN Full Interrupt */ -+#define IDFULL_vect _VECTOR(41) -+#define IDFULL_vect_num 41 -+ -+#define _VECTORS_SIZE 168 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 64 -+#define FLASHSTART 0x8000 -+#define FLASHEND 0xCFFF -+#define RAMSTART 0x0200 -+#define RAMSIZE 1024 -+#define RAMEND 0x05FF -+#define E2START 0 -+#define E2SIZE 1152 -+#define E2PAGESIZE 16 -+#define E2END 0x047F -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 1 -+ -+/* Fuse Byte */ -+#define FUSE_CKDIV8 (unsigned char)~_BV(128) -+#define FUSE_DWEN (unsigned char)~_BV(64) -+#define FUSE_SPIEN (unsigned char)~_BV(32) -+#define FUSE_WDTON (unsigned char)~_BV(16) -+#define FUSE_EESAVE (unsigned char)~_BV(8) -+#define FUSE_BOOTRST (unsigned char)~_BV(4) -+#define FUSE_RSTDISBL (unsigned char)~_BV(2) -+#define FUSE_EXTCLKEN (unsigned char)~_BV(1) -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x95 -+#define SIGNATURE_2 0x64 -+ -+ -+#endif /* #ifdef _AVR_ATA5781_H_INCLUDED */ -+ -diff --git a/include/avr/ioa5782.h b/include/avr/ioa5782.h -new file mode 100644 -index 0000000..fbd1f0e ---- /dev/null -+++ b/include/avr/ioa5782.h -@@ -0,0 +1,1781 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATA5782_H_INCLUDED -+#define _AVR_ATA5782_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "ioa5782.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PRR0 _SFR_IO8(0x01) -+#define PRSPI 0 -+#define PRRXDC 1 -+#define PRTXDC 2 -+#define PRCRC 3 -+#define PRVM 4 -+#define PRCO 5 -+ -+#define PRR1 _SFR_IO8(0x02) -+#define PRT1 0 -+#define PRT2 1 -+#define PRT3 2 -+#define PRT4 3 -+#define PRT5 4 -+ -+#define PRR2 _SFR_IO8(0x03) -+#define PRXB 0 -+#define PRXA 1 -+#define PRSF 2 -+#define PRDF 3 -+#define PRIDS 4 -+#define PRRS 5 -+#define PRTM 6 -+#define PRSSM 7 -+ -+#define RDPR _SFR_IO8(0x04) -+#define PRPTB 0 -+#define PRPTA 1 -+#define PRFLT 2 -+#define PRTMP 3 -+#define APRPTB 4 -+#define APRPTA 5 -+#define ARDPRF 6 -+#define RDPRF 7 -+ -+#define PINB _SFR_IO8(0x05) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x06) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x07) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x08) -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x09) -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x0A) -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+/* Reserved [0x0B..0x0C] */ -+ -+#define RDSIFR _SFR_IO8(0x0D) -+#define NBITA 0 -+#define NBITB 1 -+#define EOTA 2 -+#define EOTB 3 -+#define SOTA 4 -+#define SOTB 5 -+#define WCOA 6 -+#define WCOB 7 -+ -+#define MCUCR _SFR_IO8(0x0E) -+#define IVCE 0 -+#define IVSEL 1 -+#define SPIIO 2 -+#define ENPS 3 -+#define PUD 4 -+#define PB4HS 5 -+#define PB7LS 6 -+#define PB7HS 7 -+ -+#define PCIFR _SFR_IO8(0x0F) -+#define PCIF0 0 -+#define PCIF1 1 -+ -+#define T0CR _SFR_IO8(0x10) -+#define T0PS0 0 -+#define T0PS1 1 -+#define T0PS2 2 -+#define T0IE 3 -+#define T0PR 4 -+ -+#define T1CR _SFR_IO8(0x11) -+#define T1OTM 0 -+#define T1CTM 1 -+#define T1CRM 2 -+#define T1TOP 4 -+#define T1RES 5 -+#define T1TOS 6 -+#define T1ENA 7 -+ -+#define T2CR _SFR_IO8(0x12) -+#define T2OTM 0 -+#define T2CTM 1 -+#define T2CRM 2 -+#define T2TOP 4 -+#define T2RES 5 -+#define T2TOS 6 -+#define T2ENA 7 -+ -+#define T3CR _SFR_IO8(0x13) -+#define T3OTM 0 -+#define T3CTM 1 -+#define T3CRM 2 -+#define T3CPRM 3 -+#define T3TOP 4 -+#define T3RES 5 -+#define T3TOS 6 -+#define T3ENA 7 -+ -+#define T4CR _SFR_IO8(0x14) -+#define T4OTM 0 -+#define T4CTM 1 -+#define T4CRM 2 -+#define T4CPRM 3 -+#define T4TOP 4 -+#define T4RES 5 -+#define T4TOS 6 -+#define T4ENA 7 -+ -+#define T1IFR _SFR_IO8(0x15) -+#define T1OFF 0 -+#define T1COF 1 -+ -+#define T2IFR _SFR_IO8(0x16) -+#define T2OFF 0 -+#define T2COF 1 -+ -+#define T3IFR _SFR_IO8(0x17) -+#define T3OFF 0 -+#define T3COF 1 -+#define T3ICF 2 -+ -+#define T4IFR _SFR_IO8(0x18) -+#define T4OFF 0 -+#define T4COF 1 -+#define T4ICF 2 -+ -+#define T5IFR _SFR_IO8(0x19) -+#define T5OFF 0 -+#define T5COF 1 -+ -+#define GPIOR0 _SFR_IO8(0x1A) -+ -+#define GPIOR3 _SFR_IO8(0x1B) -+ -+#define GPIOR4 _SFR_IO8(0x1C) -+ -+#define GPIOR5 _SFR_IO8(0x1D) -+ -+#define GPIOR6 _SFR_IO8(0x1E) -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEWE 1 -+#define EEMWE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+#define EEPAGE 6 -+#define NVMBSY 7 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define EEPR _SFR_IO8(0x23) -+#define EEAP0 0 -+#define EEAP1 1 -+#define EEAP2 2 -+#define EEAP3 3 -+ -+#define GPIOR1 _SFR_IO8(0x24) -+ -+#define GPIOR2 _SFR_IO8(0x25) -+ -+#define PCICR _SFR_IO8(0x26) -+#define PCIE0 0 -+#define PCIE1 1 -+ -+#define EIMSK _SFR_IO8(0x27) -+#define INT0 0 -+#define INT1 1 -+ -+#define EIFR _SFR_IO8(0x28) -+#define INTF0 0 -+#define INTF1 1 -+ -+#define CRCDIR _SFR_IO8(0x29) -+ -+#define VMCSR _SFR_IO8(0x2A) -+#define VMLS0 0 -+#define VMLS1 1 -+#define VMLS2 2 -+#define VMLS3 3 -+#define VMIM 4 -+#define VMF 5 -+ -+#define MCUSR _SFR_IO8(0x2B) -+#define PORF 0 -+#define EXTRF 1 -+#define WDRF 3 -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define RXIF 4 -+#define TXIF 5 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+#define T0IFR _SFR_IO8(0x2F) -+#define T0F 0 -+ -+/* Reserved [0x30] */ -+ -+#define DWDR _SFR_IO8(0x31) -+ -+/* Reserved [0x32] */ -+ -+#define RDCR _SFR_IO8(0x33) -+#define RDPU 0 -+#define ADIVEN 1 -+#define RDEN 2 -+ -+#define EOTSA _SFR_IO8(0x34) -+#define CARFA 0 -+#define AMPFA 1 -+#define SYTFA 2 -+#define MANFA 3 -+#define TMOFA 4 -+#define TELRA 5 -+#define RRFA 6 -+#define EOTBF 7 -+ -+#define EOTCA _SFR_IO8(0x35) -+#define CARFEA 0 -+#define AMPFEA 1 -+#define SYTFEA 2 -+#define MANFEA 3 -+#define TMOFEA 4 -+#define TELREA 5 -+#define RRFEA 6 -+#define EOTBFE 7 -+ -+#define EOTSB _SFR_IO8(0x36) -+#define CARFB 0 -+#define AMPFB 1 -+#define SYTFB 2 -+#define MANFB 3 -+#define TMOFB 4 -+#define TELRB 5 -+#define RRFB 6 -+#define EOTAF 7 -+ -+#define EOTCB _SFR_IO8(0x37) -+#define CARFEB 0 -+#define AMPFEB 1 -+#define SYTFEB 2 -+#define MANFEB 3 -+#define TMOFEB 4 -+#define TELREB 5 -+#define RRFEB 6 -+#define EOTAFE 7 -+ -+#define SMCR _SFR_IO8(0x38) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define CMCR _SFR_IO8(0x39) -+#define CMM0 0 -+#define CMM1 1 -+#define CMM2 2 -+#define CCS 3 -+#define SRCD 4 -+#define CMONEN 6 -+#define CMCCE 7 -+ -+#define CMIMR _SFR_IO8(0x3A) -+#define ECIE 0 -+ -+#define CLPR _SFR_IO8(0x3B) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLTPS0 3 -+#define CLTPS1 4 -+#define CLTPS2 5 -+#define CLPCE 7 -+ -+#define SPMCSR _SFR_IO8(0x3C) -+#define SELFPRGEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define SPMIE 7 -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define FSEN _SFR_MEM8(0x60) -+#define SDPU 0 -+#define SDEN 1 -+ -+/* Reserved [0x61..0x63] */ -+ -+#define FFREQ1L _SFR_MEM8(0x64) -+ -+#define FFREQ1M _SFR_MEM8(0x65) -+ -+#define FFREQ1H _SFR_MEM8(0x66) -+ -+#define FFREQ2L _SFR_MEM8(0x67) -+ -+#define FFREQ2M _SFR_MEM8(0x68) -+ -+#define FFREQ2H _SFR_MEM8(0x69) -+ -+/* Reserved [0x6A] */ -+ -+#define EICRA _SFR_MEM8(0x6B) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+ -+#define PCMSK0 _SFR_MEM8(0x6C) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6D) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+ -+#define WDTCR _SFR_MEM8(0x6E) -+#define WDPS0 0 -+#define WDPS1 1 -+#define WDPS2 2 -+#define WDE 3 -+#define WDCE 4 -+ -+#define T1CNT _SFR_MEM8(0x6F) -+ -+#define T1COR _SFR_MEM8(0x70) -+ -+#define T1MR _SFR_MEM8(0x71) -+#define T1CS0 0 -+#define T1CS1 1 -+#define T1PS0 2 -+#define T1PS1 3 -+#define T1PS2 4 -+#define T1PS3 5 -+#define T1DC0 6 -+#define T1DC1 7 -+ -+#define T1IMR _SFR_MEM8(0x72) -+#define T1OIM 0 -+#define T1CIM 1 -+ -+#define T2CNT _SFR_MEM8(0x73) -+ -+#define T2COR _SFR_MEM8(0x74) -+ -+#define T2MR _SFR_MEM8(0x75) -+#define T2CS0 0 -+#define T2CS1 1 -+#define T2PS0 2 -+#define T2PS1 3 -+#define T2PS2 4 -+#define T2PS3 5 -+#define T2DC0 6 -+#define T2DC1 7 -+ -+#define T2IMR _SFR_MEM8(0x76) -+#define T2OIM 0 -+#define T2CIM 1 -+ -+/* Combine T3CNTL and T3CNTH */ -+#define T3CNT _SFR_MEM16(0x77) -+ -+#define T3CNTL _SFR_MEM8(0x77) -+#define T3CNTH _SFR_MEM8(0x78) -+ -+/* Combine T3CORL and T3CORH */ -+#define T3COR _SFR_MEM16(0x79) -+ -+#define T3CORL _SFR_MEM8(0x79) -+#define T3CORH _SFR_MEM8(0x7A) -+ -+/* Combine T3ICRL and T3ICRH */ -+#define T3ICR _SFR_MEM16(0x7B) -+ -+#define T3ICRL _SFR_MEM8(0x7B) -+#define T3ICRH _SFR_MEM8(0x7C) -+ -+#define T3MRA _SFR_MEM8(0x7D) -+#define T3CS0 0 -+#define T3CS1 1 -+#define T3PS0 2 -+#define T3PS1 3 -+#define T3PS2 4 -+ -+#define T3MRB _SFR_MEM8(0x7E) -+#define T3SCE 1 -+#define T3CNC 2 -+#define T3CE0 3 -+#define T3CE1 4 -+#define T3ICS0 5 -+#define T3ICS1 6 -+#define T3ICS2 7 -+ -+#define T3IMR _SFR_MEM8(0x7F) -+#define T3OIM 0 -+#define T3CIM 1 -+#define T3CPIM 2 -+ -+/* Combine T4CNTL and T4CNTH */ -+#define T4CNT _SFR_MEM16(0x80) -+ -+#define T4CNTL _SFR_MEM8(0x80) -+#define T4CNTH _SFR_MEM8(0x81) -+ -+/* Combine T4CORL and T4CORH */ -+#define T4COR _SFR_MEM16(0x82) -+ -+#define T4CORL _SFR_MEM8(0x82) -+#define T4CORH _SFR_MEM8(0x83) -+ -+/* Combine T4ICRL and T4ICRH */ -+#define T4ICR _SFR_MEM16(0x84) -+ -+#define T4ICRL _SFR_MEM8(0x84) -+#define T4ICRH _SFR_MEM8(0x85) -+ -+#define T4MRA _SFR_MEM8(0x86) -+#define T4CS0 0 -+#define T4CS1 1 -+#define T4PS0 2 -+#define T4PS1 3 -+#define T4PS2 4 -+ -+#define T4MRB _SFR_MEM8(0x87) -+#define T4SCE 1 -+#define T4CNC 2 -+#define T4CE0 3 -+#define T4CE1 4 -+#define T4ICS0 5 -+#define T4ICS1 6 -+#define T4ICS2 7 -+ -+#define T4IMR _SFR_MEM8(0x88) -+#define T4OIM 0 -+#define T4CIM 1 -+#define T4CPIM 2 -+ -+/* Reserved [0x89] */ -+ -+/* Combine T5OCRL and T5OCRH */ -+#define T5OCR _SFR_MEM16(0x8A) -+ -+#define T5OCRL _SFR_MEM8(0x8A) -+#define T5OCRH _SFR_MEM8(0x8B) -+ -+#define T5CCR _SFR_MEM8(0x8C) -+#define T5CS0 0 -+#define T5CS1 1 -+#define T5CS2 2 -+#define T5CTC 3 -+ -+/* Combine T5CNTL and T5CNTH */ -+#define T5CNT _SFR_MEM16(0x8D) -+ -+#define T5CNTL _SFR_MEM8(0x8D) -+#define T5CNTH _SFR_MEM8(0x8E) -+ -+#define T5IMR _SFR_MEM8(0x8F) -+#define T5OIM 0 -+#define T5CIM 1 -+ -+#define GTCCR _SFR_MEM8(0x90) -+#define PSR10 0 -+#define TSM 7 -+ -+#define SOTSB _SFR_MEM8(0x91) -+#define CAROB 0 -+#define AMPOB 1 -+#define SYTOB 2 -+#define MANOB 3 -+#define WUPOB 4 -+#define SFIDOB 5 -+#define RROB 6 -+#define WCOAO 7 -+ -+#define SOTSA _SFR_MEM8(0x92) -+#define CAROA 0 -+#define AMPOA 1 -+#define SYTOA 2 -+#define MANOA 3 -+#define WUPOA 4 -+#define SFIDOA 5 -+#define RROA 6 -+#define WCOBO 7 -+ -+#define SOTCB _SFR_MEM8(0x93) -+#define CAROEB 0 -+#define AMPOEB 1 -+#define SYTOEB 2 -+#define MANOEB 3 -+#define WUPEB 4 -+#define SFIDEB 5 -+#define RROEB 6 -+#define WCOAOE 7 -+ -+#define SOTCA _SFR_MEM8(0x94) -+#define CAROEA 0 -+#define AMPOEA 1 -+#define SYTOEA 2 -+#define MANOEA 3 -+#define WUPEA 4 -+#define SFIDEA 5 -+#define RROEA 6 -+#define WCOBOE 7 -+ -+#define TESRB _SFR_MEM8(0x95) -+#define CRCOB 0 -+#define EOTLB0 1 -+#define EOTLB1 2 -+ -+#define TESRA _SFR_MEM8(0x96) -+#define CRCOA 0 -+#define EOTLA0 1 -+#define EOTLA1 2 -+ -+/* Reserved [0x97] */ -+ -+#define RDSIMR _SFR_MEM8(0x98) -+#define NBITAM 0 -+#define NBITBM 1 -+#define EOTAM 2 -+#define EOTBM 3 -+#define SOTAM 4 -+#define SOTBM 5 -+#define WCOAM 6 -+#define WCOBM 7 -+ -+#define RDOCR _SFR_MEM8(0x99) -+#define TMDS0 1 -+#define TMDS1 2 -+#define ETRPA 3 -+#define ETRPB 4 -+#define RDSIDA 5 -+#define RDSIDB 6 -+ -+/* Reserved [0x9A] */ -+ -+#define TEMPL _SFR_MEM8(0x9B) -+ -+#define TEMPH _SFR_MEM8(0x9C) -+ -+#define SYCB _SFR_MEM8(0x9D) -+#define SYCSB0 0 -+#define SYCSB1 1 -+#define SYCSB2 2 -+#define SYCSB3 3 -+#define SYTLB0 4 -+#define SYTLB1 5 -+#define SYTLB2 6 -+#define SYTLB3 7 -+ -+#define SYCA _SFR_MEM8(0x9E) -+#define SYCSA0 0 -+#define SYCSA1 1 -+#define SYCSA2 2 -+#define SYCSA3 3 -+#define SYTLA0 4 -+#define SYTLA1 5 -+#define SYTLA2 6 -+#define SYTLA3 7 -+ -+#define RXFOB _SFR_MEM8(0x9F) -+ -+#define RXFOA _SFR_MEM8(0xA0) -+ -+#define DMMB _SFR_MEM8(0xA1) -+#define DMATB0 0 -+#define DMATB1 1 -+#define DMATB2 2 -+#define DMATB3 3 -+#define DMATB4 4 -+#define DMPB 5 -+#define DMHB 6 -+#define DMNEB 7 -+ -+#define DMMA _SFR_MEM8(0xA2) -+#define DMATA0 0 -+#define DMATA1 1 -+#define DMATA2 2 -+#define DMATA3 3 -+#define DMATA4 4 -+#define DMPA 5 -+#define DMHA 6 -+#define DMNEA 7 -+ -+#define DMCDB _SFR_MEM8(0xA3) -+#define DMCLB0 0 -+#define DMCLB1 1 -+#define DMCLB2 2 -+#define DMCLB3 3 -+#define DMCLB4 4 -+#define DMCTB0 5 -+#define DMCTB1 6 -+#define DMCTB2 7 -+ -+#define DMCDA _SFR_MEM8(0xA4) -+#define DMCLA0 0 -+#define DMCLA1 1 -+#define DMCLA2 2 -+#define DMCLA3 3 -+#define DMCLA4 4 -+#define DMCTA0 5 -+#define DMCTA1 6 -+#define DMCTA2 7 -+ -+#define DMCRB _SFR_MEM8(0xA5) -+#define DMPGB0 0 -+#define DMPGB1 1 -+#define DMPGB2 2 -+#define DMPGB3 3 -+#define DMPGB4 4 -+#define SASKB 5 -+#define SY1TB 6 -+#define DMARB 7 -+ -+#define DMCRA _SFR_MEM8(0xA6) -+#define DMPGA0 0 -+#define DMPGA1 1 -+#define DMPGA2 2 -+#define DMPGA3 3 -+#define DMPGA4 4 -+#define SASKA 5 -+#define SY1TA 6 -+#define DMARA 7 -+ -+#define DMDRB _SFR_MEM8(0xA7) -+#define DMAB0 0 -+#define DMAB1 1 -+#define DMAB2 2 -+#define DMAB3 3 -+#define DMDNB0 4 -+#define DMDNB1 5 -+#define DMDNB2 6 -+#define DMDNB3 7 -+ -+#define DMDRA _SFR_MEM8(0xA8) -+#define DMAA0 0 -+#define DMAA1 1 -+#define DMAA2 2 -+#define DMAA3 3 -+#define DMDNA0 4 -+#define DMDNA1 5 -+#define DMDNA2 6 -+#define DMDNA3 7 -+ -+#define CHCR _SFR_MEM8(0xA9) -+#define BWM0 0 -+#define BWM1 1 -+#define BWM2 2 -+#define BWM3 3 -+ -+#define CHDN _SFR_MEM8(0xAA) -+#define BBDN0 0 -+#define BBDN1 1 -+#define BBDN2 2 -+#define BBDN3 3 -+#define BBDN4 4 -+#define ADCDN 5 -+ -+#define SFIDCB _SFR_MEM8(0xAB) -+#define SFIDTB0 0 -+#define SFIDTB1 1 -+#define SFIDTB2 2 -+#define SFIDTB3 3 -+#define SFIDTB4 4 -+#define SEMEB 7 -+ -+#define SFIDLB _SFR_MEM8(0xAC) -+#define SFIDLB0 0 -+#define SFIDLB1 1 -+#define SFIDLB2 2 -+#define SFIDLB3 3 -+#define SFIDLB4 4 -+#define SFIDLB5 5 -+ -+#define WUPTB _SFR_MEM8(0xAD) -+#define WUPTB0 0 -+#define WUPTB1 1 -+#define WUPTB2 2 -+#define WUPTB3 3 -+#define WUPTB4 4 -+ -+#define WUPLB _SFR_MEM8(0xAE) -+#define WUPLB0 0 -+#define WUPLB1 1 -+#define WUPLB2 2 -+#define WUPLB3 3 -+#define WUPLB4 4 -+#define WUPLB5 5 -+ -+#define SFID1B _SFR_MEM8(0xAF) -+ -+#define SFID2B _SFR_MEM8(0xB0) -+ -+#define SFID3B _SFR_MEM8(0xB1) -+ -+#define SFID4B _SFR_MEM8(0xB2) -+ -+#define WUP1B _SFR_MEM8(0xB3) -+ -+#define WUP2B _SFR_MEM8(0xB4) -+ -+#define WUP3B _SFR_MEM8(0xB5) -+ -+#define WUP4B _SFR_MEM8(0xB6) -+ -+#define SFIDCA _SFR_MEM8(0xB7) -+#define SFIDTA0 0 -+#define SFIDTA1 1 -+#define SFIDTA2 2 -+#define SFIDTA3 3 -+#define SFIDTA4 4 -+#define SEMEA 7 -+ -+#define SFIDLA _SFR_MEM8(0xB8) -+#define SFIDLA0 0 -+#define SFIDLA1 1 -+#define SFIDLA2 2 -+#define SFIDLA3 3 -+#define SFIDLA4 4 -+#define SFIDLA5 5 -+ -+#define WUPTA _SFR_MEM8(0xB9) -+#define WUPTA0 0 -+#define WUPTA1 1 -+#define WUPTA2 2 -+#define WUPTA3 3 -+#define WUPTA4 4 -+ -+#define WUPLA _SFR_MEM8(0xBA) -+#define WUPLA0 0 -+#define WUPLA1 1 -+#define WUPLA2 2 -+#define WUPLA3 3 -+#define WUPLA4 4 -+#define WUPLA5 5 -+ -+#define SFID1A _SFR_MEM8(0xBB) -+ -+#define SFID2A _SFR_MEM8(0xBC) -+ -+#define SFID3A _SFR_MEM8(0xBD) -+ -+#define SFID4A _SFR_MEM8(0xBE) -+ -+#define WUP1A _SFR_MEM8(0xBF) -+ -+#define WUP2A _SFR_MEM8(0xC0) -+ -+#define WUP3A _SFR_MEM8(0xC1) -+ -+#define WUP4A _SFR_MEM8(0xC2) -+ -+#define CLKOD _SFR_MEM8(0xC3) -+ -+#define CLKOCR _SFR_MEM8(0xC4) -+#define CLKOS0 0 -+#define CLKOS1 1 -+#define CLKOEN 2 -+ -+#define XFUSE _SFR_MEM8(0xC5) -+ -+#define SRCCAL _SFR_MEM8(0xC6) -+#define SRCCAL0 0 -+#define SRCCAL1 1 -+#define SRCCAL2 2 -+#define SRCCAL3 3 -+#define SRCCAL4 4 -+#define SRCCAL5 5 -+#define SRCTC0 6 -+#define SRCTC1 7 -+ -+#define FRCCAL _SFR_MEM8(0xC7) -+#define FRCCAL0 0 -+#define FRCCAL1 1 -+#define FRCCAL2 2 -+#define FRCCAL3 3 -+#define FRCCAL4 4 -+#define FRCTC 5 -+ -+#define CMSR _SFR_MEM8(0xC8) -+#define ECF 0 -+ -+#define CMOCR _SFR_MEM8(0xC9) -+#define FRCAO 0 -+#define SRCAO 1 -+#define FRCACT 2 -+#define SRCACT 3 -+ -+#define SUPFR _SFR_MEM8(0xCA) -+#define AVCCRF 0 -+#define AVCCLF 1 -+ -+#define SUPCR _SFR_MEM8(0xCB) -+#define AVCCRM 0 -+#define AVCCLM 1 -+#define PVEN 2 -+#define DVDIS 4 -+#define AVEN 5 -+#define AVDIC 6 -+ -+/* Reserved [0xCC] */ -+ -+#define SUPCA2 _SFR_MEM8(0xCD) -+#define BGCAL0 0 -+#define BGCAL1 1 -+#define BGCAL2 2 -+#define BGCAL3 3 -+ -+#define SUPCA3 _SFR_MEM8(0xCE) -+#define ACAL4 0 -+#define ACAL5 1 -+#define ACAL6 2 -+#define ACAL7 3 -+#define DCAL4 4 -+#define DCAL5 5 -+#define DCAL6 6 -+ -+#define SUPCA4 _SFR_MEM8(0xCF) -+#define ACAL0 0 -+#define ACAL1 1 -+#define ACAL2 2 -+#define ACAL3 3 -+#define DCAL0 4 -+#define DCAL1 5 -+#define DCAL2 6 -+#define DCAL3 7 -+ -+#define CALRDY _SFR_MEM8(0xD0) -+ -+#define VMCAL _SFR_MEM8(0xD1) -+#define VMCAL0 0 -+#define VMCAL1 1 -+#define VMCAL2 2 -+ -+#define DFS _SFR_MEM8(0xD2) -+#define DFFLRF 0 -+#define DFUFL 1 -+#define DFOFL 2 -+ -+/* Combine DFTLL and DFTLH */ -+#define DFTL _SFR_MEM16(0xD3) -+ -+#define DFTLL _SFR_MEM8(0xD3) -+#define DFTLH _SFR_MEM8(0xD4) -+ -+#define DFL _SFR_MEM8(0xD5) -+#define DFFLS0 0 -+#define DFFLS1 1 -+#define DFFLS2 2 -+#define DFFLS3 3 -+#define DFFLS4 4 -+#define DFFLS5 5 -+#define DFCLR 7 -+ -+#define DFWP _SFR_MEM8(0xD6) -+#define DFWP0 0 -+#define DFWP1 1 -+#define DFWP2 2 -+#define DFWP3 3 -+#define DFWP4 4 -+#define DFWP5 5 -+ -+#define DFRP _SFR_MEM8(0xD7) -+#define DFRP0 0 -+#define DFRP1 1 -+#define DFRP2 2 -+#define DFRP3 3 -+#define DFRP4 4 -+#define DFRP5 5 -+ -+#define DFD _SFR_MEM8(0xD8) -+ -+#define DFI _SFR_MEM8(0xD9) -+#define DFFLIM 0 -+#define DFERIM 1 -+ -+#define DFC _SFR_MEM8(0xDA) -+#define DFFLC0 0 -+#define DFFLC1 1 -+#define DFFLC2 2 -+#define DFFLC3 3 -+#define DFFLC4 4 -+#define DFFLC5 5 -+#define DFDRA 7 -+ -+#define SFS _SFR_MEM8(0xDB) -+#define SFFLRF 0 -+#define SFUFL 1 -+#define SFOFL 2 -+ -+#define SFL _SFR_MEM8(0xDC) -+#define SFFLS0 0 -+#define SFFLS1 1 -+#define SFFLS2 2 -+#define SFFLS3 3 -+#define SFFLS4 4 -+#define SFCLR 7 -+ -+#define SFWP _SFR_MEM8(0xDD) -+#define SFWP0 0 -+#define SFWP1 1 -+#define SFWP2 2 -+#define SFWP3 3 -+#define SFWP4 4 -+ -+#define SFRP _SFR_MEM8(0xDE) -+#define SFRP0 0 -+#define SFRP1 1 -+#define SFRP2 2 -+#define SFRP3 3 -+#define SFRP4 4 -+ -+#define SFD _SFR_MEM8(0xDF) -+ -+#define SFI _SFR_MEM8(0xE0) -+#define SFFLIM 0 -+#define SFERIM 1 -+ -+#define SFC _SFR_MEM8(0xE1) -+#define SFFLC0 0 -+#define SFFLC1 1 -+#define SFFLC2 2 -+#define SFFLC3 3 -+#define SFFLC4 4 -+#define SFDRA 7 -+ -+#define SSMCR _SFR_MEM8(0xE2) -+#define SSMTX 0 -+#define SSMTM 1 -+#define SSMTGE 2 -+#define SSMTPE 3 -+#define SSMPVE 4 -+#define SSMTAE 5 -+#define SETRPA 6 -+#define SETRPB 7 -+ -+#define SSMRCR _SFR_MEM8(0xE3) -+#define SSMPA 0 -+#define SSMPB 1 -+#define SSMADA 2 -+#define SSMADB 3 -+#define SSMPVS 4 -+#define SSMIFA 5 -+#define SSMIDSE 6 -+#define SSMTMOE 7 -+ -+#define SSMFBR _SFR_MEM8(0xE4) -+#define SSMFID0 0 -+#define SSMFID1 1 -+#define SSMFID2 2 -+#define SSMDFDT 3 -+#define SSMHADT 4 -+#define SSMPLDT 5 -+ -+#define SSMRR _SFR_MEM8(0xE5) -+#define SSMR 0 -+#define SSMST 1 -+ -+#define SSMSR _SFR_MEM8(0xE6) -+#define SSMESM0 0 -+#define SSMESM1 1 -+#define SSMESM2 2 -+#define SSMESM3 3 -+#define SSMERR 7 -+ -+#define SSMIFR _SFR_MEM8(0xE7) -+#define SSMIF 0 -+ -+#define SSMIMR _SFR_MEM8(0xE8) -+#define SSMIM 0 -+ -+#define MSMSTR _SFR_MEM8(0xE9) -+#define SSMMST0 0 -+#define SSMMST1 1 -+#define SSMMST2 2 -+#define SSMMST3 3 -+#define SSMMST4 4 -+ -+#define SSMSTR _SFR_MEM8(0xEA) -+#define SSMSTA0 0 -+#define SSMSTA1 1 -+#define SSMSTA2 2 -+#define SSMSTA3 3 -+#define SSMSTA4 4 -+#define SSMSTA5 5 -+ -+#define SSMXSR _SFR_MEM8(0xEB) -+#define SSMSTB0 0 -+#define SSMSTB1 1 -+#define SSMSTB2 2 -+#define SSMSTB3 3 -+#define SSMSTB4 4 -+#define SSMSTB5 5 -+ -+#define MSMCR1 _SFR_MEM8(0xEC) -+#define MSMSM00 0 -+#define MSMSM01 1 -+#define MSMSM02 2 -+#define MSMSM03 3 -+#define MSMSM10 4 -+#define MSMSM11 5 -+#define MSMSM12 6 -+#define MSMSM13 7 -+ -+#define MSMCR2 _SFR_MEM8(0xED) -+#define MSMSM20 0 -+#define MSMSM21 1 -+#define MSMSM22 2 -+#define MSMSM23 3 -+#define MSMSM30 4 -+#define MSMSM31 5 -+#define MSMSM32 6 -+#define MSMSM33 7 -+ -+#define MSMCR3 _SFR_MEM8(0xEE) -+#define MSMSM40 0 -+#define MSMSM41 1 -+#define MSMSM42 2 -+#define MSMSM43 3 -+#define MSMSM50 4 -+#define MSMSM51 5 -+#define MSMSM52 6 -+#define MSMSM53 7 -+ -+#define MSMCR4 _SFR_MEM8(0xEF) -+#define MSMSM60 0 -+#define MSMSM61 1 -+#define MSMSM62 2 -+#define MSMSM63 3 -+#define MSMSM70 4 -+#define MSMSM71 5 -+#define MSMSM72 6 -+#define MSMSM73 7 -+ -+#define GTCR _SFR_MEM8(0xF0) -+#define RXTEHA 0 -+#define GAPMA 1 -+#define DARA 2 -+#define IWUPA 3 -+#define RXTEHB 4 -+#define GAPMB 5 -+#define DARB 6 -+#define IWUPB 7 -+ -+#define SOTC1A _SFR_MEM8(0xF1) -+#define CAROEA1 0 -+#define AMPOEA1 1 -+#define SYTOEA1 2 -+#define MANOEA1 3 -+#define WUPEA1 4 -+#define SFIDEA1 5 -+#define RROEA1 6 -+#define WCOBOE1 7 -+ -+#define SOTC2A _SFR_MEM8(0xF2) -+#define CAROEA2 0 -+#define AMPOEA2 1 -+#define SYTOEA2 2 -+#define MANOEA2 3 -+#define WUPEA2 4 -+#define SFIDEA2 5 -+#define RROEA2 6 -+#define WCOBOE2 7 -+ -+#define SOTC1B _SFR_MEM8(0xF3) -+#define CAROEB1 0 -+#define AMPOEB1 1 -+#define SYTOEB1 2 -+#define MANOEB1 3 -+#define WUPEB1 4 -+#define SFIDEB1 5 -+#define RROEB1 6 -+#define WCOAOE1 7 -+ -+#define SOTC2B _SFR_MEM8(0xF4) -+#define CAROEB2 0 -+#define AMPOEB2 1 -+#define SYTOEB2 2 -+#define MANOEB2 3 -+#define WUPEB2 4 -+#define SFIDEB2 5 -+#define RROEB2 6 -+#define WCOAOE2 7 -+ -+#define EOTC1A _SFR_MEM8(0xF5) -+#define CARFEA1 0 -+#define AMPFEA1 1 -+#define SYTFEA1 2 -+#define MANFEA1 3 -+#define TMOFEA1 4 -+#define TELREA1 5 -+#define RRFEA1 6 -+#define EOTBFE1 7 -+ -+#define EOTC2A _SFR_MEM8(0xF6) -+#define CARFEA2 0 -+#define AMPFEA2 1 -+#define SYTFEA2 2 -+#define MANFEA2 3 -+#define TMOFEA2 4 -+#define TELREA2 5 -+#define RRFEA2 6 -+#define EOTBFE2 7 -+ -+#define EOTC3A _SFR_MEM8(0xF7) -+#define CARFEA3 0 -+#define AMPFEA3 1 -+#define SYTFEA3 2 -+#define MANFEA3 3 -+#define TMOFEA3 4 -+#define TELREA3 5 -+#define RRFEA3 6 -+#define EOTBFE3 7 -+ -+#define EOTC1B _SFR_MEM8(0xF8) -+#define CARFEB1 0 -+#define AMPFEB1 1 -+#define SYTFEB1 2 -+#define MANFEB1 3 -+#define TMOFEB1 4 -+#define TELREB1 5 -+#define RRFEB1 6 -+#define EOTAFE1 7 -+ -+#define EOTC2B _SFR_MEM8(0xF9) -+#define CARFEB2 0 -+#define AMPFEB2 1 -+#define SYTFEB2 2 -+#define MANFEB2 3 -+#define TMOFEB2 4 -+#define TELREB2 5 -+#define RRFEB2 6 -+#define EOTAFE2 7 -+ -+#define EOTC3B _SFR_MEM8(0xFA) -+#define CARFEB3 0 -+#define AMPFEB3 1 -+#define SYTFEB3 2 -+#define MANFEB3 3 -+#define TMOFEB3 4 -+#define TELREB3 5 -+#define RRFEB3 6 -+#define EOTAFE3 7 -+ -+#define WCOTOA _SFR_MEM8(0xFB) -+ -+#define WCOTOB _SFR_MEM8(0xFC) -+ -+#define SOTTOA _SFR_MEM8(0xFD) -+ -+#define SOTTOB _SFR_MEM8(0xFE) -+ -+#define SSMFCR _SFR_MEM8(0xFF) -+#define SSMIDSO 0 -+#define SSMIDSF 1 -+ -+#define FESR _SFR_MEM8(0x100) -+#define LBSAT 0 -+#define HBSAT 1 -+#define XRDY 2 -+#define PLCK 3 -+ -+#define FEEN1 _SFR_MEM8(0x101) -+#define PLEN 0 -+#define PLCAL 1 -+#define XTOEN 2 -+#define LNAEN 3 -+#define ADEN 4 -+#define ADCLK 5 -+#define PLSP1 6 -+#define ATEN 7 -+ -+#define FEEN2 _SFR_MEM8(0x102) -+#define SDRX 0 -+#define SDRX2 1 -+#define PAEN 2 -+#define TMPM 3 -+#define PLPEN 4 -+#define XTPEN 5 -+ -+#define FELNA _SFR_MEM8(0x103) -+#define LBH0 0 -+#define LBH1 1 -+#define LBH2 2 -+#define LBH3 3 -+#define LBL0 4 -+#define LBL1 5 -+#define LBL2 6 -+#define LBL3 7 -+ -+/* Reserved [0x104..0x105] */ -+ -+#define FEVCT _SFR_MEM8(0x106) -+#define FEVCT0 0 -+#define FEVCT1 1 -+#define FEVCT2 2 -+#define FEVCT3 3 -+ -+#define FEBT _SFR_MEM8(0x107) -+#define CTN20 0 -+#define CTN21 1 -+#define RTN20 2 -+#define RTN21 3 -+ -+#define FEMS _SFR_MEM8(0x108) -+#define PLLS0 0 -+#define PLLS1 1 -+#define PLLS2 2 -+#define PLLS3 3 -+#define PLLM0 4 -+#define PLLM1 5 -+#define PLLM2 6 -+#define PLLM3 7 -+ -+#define FETN4 _SFR_MEM8(0x109) -+#define CTN40 0 -+#define CTN41 1 -+#define CTN42 2 -+#define CTN43 3 -+#define RTN40 4 -+#define RTN41 5 -+#define RTN42 6 -+#define RTN43 7 -+ -+#define FECR _SFR_MEM8(0x10A) -+#define LBNHB 0 -+#define S4N3 1 -+#define ANDP 2 -+#define ADHS 3 -+#define PLCKG 4 -+#define ANPS 5 -+ -+#define FEVCO _SFR_MEM8(0x10B) -+#define CPCC0 0 -+#define CPCC1 1 -+#define CPCC2 2 -+#define CPCC3 3 -+#define VCOB0 4 -+#define VCOB1 5 -+#define VCOB2 6 -+#define VCOB3 7 -+ -+#define FEALR _SFR_MEM8(0x10C) -+#define RNGE0 0 -+#define RNGE1 1 -+ -+#define FEANT _SFR_MEM8(0x10D) -+#define LVLC0 0 -+#define LVLC1 1 -+#define LVLC2 2 -+#define LVLC3 3 -+ -+#define FEBIA _SFR_MEM8(0x10E) -+#define IFAEN 7 -+ -+/* Reserved [0x10F..0x12E] */ -+ -+#define RXBC1 _SFR_MEM8(0x12F) -+#define RXCEA 0 -+#define RXCBLA0 1 -+#define RXCBLA1 2 -+#define RXMSBA 3 -+#define RXCEB 4 -+#define RXCBLB0 5 -+#define RXCBLB1 6 -+#define RXMSBB 7 -+ -+#define RXBC2 _SFR_MEM8(0x130) -+#define RXBPB 0 -+#define RXBF 1 -+#define RXBCLR 2 -+ -+#define RXTLLB _SFR_MEM8(0x131) -+ -+#define RXTLHB _SFR_MEM8(0x132) -+#define RXTLHB0 0 -+#define RXTLHB1 1 -+#define RXTLHB2 2 -+#define RXTLHB3 3 -+ -+#define RXCRLB _SFR_MEM8(0x133) -+ -+#define RXCRHB _SFR_MEM8(0x134) -+ -+#define RXCSBB _SFR_MEM8(0x135) -+ -+#define RXCILB _SFR_MEM8(0x136) -+ -+#define RXCIHB _SFR_MEM8(0x137) -+ -+#define RXCPLB _SFR_MEM8(0x138) -+ -+#define RXCPHB _SFR_MEM8(0x139) -+ -+#define RXDSB _SFR_MEM8(0x13A) -+ -+#define RXTLLA _SFR_MEM8(0x13B) -+ -+#define RXTLHA _SFR_MEM8(0x13C) -+#define RXTLHA0 0 -+#define RXTLHA1 1 -+#define RXTLHA2 2 -+#define RXTLHA3 3 -+ -+#define RXCRLA _SFR_MEM8(0x13D) -+ -+#define RXCRHA _SFR_MEM8(0x13E) -+ -+#define RXCSBA _SFR_MEM8(0x13F) -+ -+#define RXCILA _SFR_MEM8(0x140) -+ -+#define RXCIHA _SFR_MEM8(0x141) -+ -+#define RXCPLA _SFR_MEM8(0x142) -+ -+#define RXCPHA _SFR_MEM8(0x143) -+ -+#define RXDSA _SFR_MEM8(0x144) -+ -+#define CRCCR _SFR_MEM8(0x145) -+#define CRCRS 0 -+#define REFLI 1 -+#define REFLO 2 -+ -+#define CRCDOR _SFR_MEM8(0x146) -+ -+#define IDB0 _SFR_MEM8(0x147) -+ -+#define IDB1 _SFR_MEM8(0x148) -+ -+#define IDB2 _SFR_MEM8(0x149) -+ -+#define IDB3 _SFR_MEM8(0x14A) -+ -+#define IDC _SFR_MEM8(0x14B) -+#define IDL0 0 -+#define IDL1 1 -+#define IDBO0 2 -+#define IDBO1 3 -+#define IDFIM 5 -+#define IDCLR 6 -+#define IDCE 7 -+ -+#define IDS _SFR_MEM8(0x14C) -+#define IDOK 0 -+#define IDFULL 1 -+ -+#define RSSAV _SFR_MEM8(0x14D) -+ -+#define RSSPK _SFR_MEM8(0x14E) -+ -+#define RSSL _SFR_MEM8(0x14F) -+ -+#define RSSH _SFR_MEM8(0x150) -+ -+#define RSSC _SFR_MEM8(0x151) -+#define RSUP0 0 -+#define RSUP1 1 -+#define RSUP2 2 -+#define RSUP3 3 -+#define RSWLH 4 -+#define RSHRX 5 -+#define RSPKF 6 -+ -+#define DBCR _SFR_MEM8(0x152) -+#define DBMD 0 -+#define DBCS 1 -+#define DBTMS 2 -+#define DBHA 3 -+ -+#define DBTC _SFR_MEM8(0x153) -+ -+#define DBENB _SFR_MEM8(0x154) -+ -+#define DBENC _SFR_MEM8(0x155) -+ -+#define DBGSW _SFR_MEM8(0x156) -+#define DBGGS0 0 -+#define DBGGS1 1 -+#define DBGGS2 2 -+#define DBGGS3 3 -+#define CPBFOS0 4 -+#define CPBFOS1 5 -+#define CPBF 6 -+#define DBGSE 7 -+ -+#define SFFR _SFR_MEM8(0x157) -+#define RFL0 0 -+#define RFL1 1 -+#define RFL2 2 -+#define RFC 3 -+#define TFL0 4 -+#define TFL1 5 -+#define TFL2 6 -+#define TFC 7 -+ -+#define SFIR _SFR_MEM8(0x158) -+#define RIL0 0 -+#define RIL1 1 -+#define RIL2 2 -+#define SRIE 3 -+#define TIL0 4 -+#define TIL1 5 -+#define TIL2 6 -+#define STIE 7 -+ -+#define EECR2 _SFR_MEM8(0x159) -+#define EEBRE 0 -+ -+#define PGMST _SFR_MEM8(0x15A) -+#define PGMSYN0 0 -+#define PGMSYN1 1 -+#define PGMSYN2 2 -+#define PGMSYN3 3 -+#define PGMSYN4 4 -+ -+#define EEST _SFR_MEM8(0x15B) -+#define EESYN0 0 -+#define EESYN1 1 -+#define EESYN2 2 -+#define EESYN3 3 -+ -+#define RSIFG _SFR_MEM8(0x15C) -+ -+#define RSLDV _SFR_MEM8(0x15D) -+ -+#define RSHDV _SFR_MEM8(0x15E) -+ -+#define RSCOM _SFR_MEM8(0x15F) -+#define RSDC 0 -+#define RSIFC 1 -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCI0_vect _VECTOR(3) -+#define PCI0_vect_num 3 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCI1_vect _VECTOR(4) -+#define PCI1_vect_num 4 -+ -+/* Voltage Monitoring Interrupt */ -+#define VMON_vect _VECTOR(5) -+#define VMON_vect_num 5 -+ -+/* AVCC Reset Interrupt */ -+#define AVCCR_vect _VECTOR(6) -+#define AVCCR_vect_num 6 -+ -+/* AVCC Low Interrupt */ -+#define AVCCL_vect _VECTOR(7) -+#define AVCCL_vect_num 7 -+ -+/* Timer 0 Interval Interrupt */ -+#define T0INT_vect _VECTOR(8) -+#define T0INT_vect_num 8 -+ -+/* Timer/Counter1 Compare Match Interrupt */ -+#define T1COMP_vect _VECTOR(9) -+#define T1COMP_vect_num 9 -+ -+/* Timer/Counter1 Overflow Interrupt */ -+#define T1OVF_vect _VECTOR(10) -+#define T1OVF_vect_num 10 -+ -+/* Timer/Counter2 Compare Match Interrupt */ -+#define T2COMP_vect _VECTOR(11) -+#define T2COMP_vect_num 11 -+ -+/* Timer/Counter2 Overflow Interrupt */ -+#define T2OVF_vect _VECTOR(12) -+#define T2OVF_vect_num 12 -+ -+/* Timer/Counter3 Capture Event Interrupt */ -+#define T3CAP_vect _VECTOR(13) -+#define T3CAP_vect_num 13 -+ -+/* Timer/Counter3 Compare Match Interrupt */ -+#define T3COMP_vect _VECTOR(14) -+#define T3COMP_vect_num 14 -+ -+/* Timer/Counter3 Overflow Interrupt */ -+#define T3OVF_vect _VECTOR(15) -+#define T3OVF_vect_num 15 -+ -+/* Timer/Counter4 Capture Event Interrupt */ -+#define T4CAP_vect _VECTOR(16) -+#define T4CAP_vect_num 16 -+ -+/* Timer/Counter4 Compare Match Interrupt */ -+#define T4COMP_vect _VECTOR(17) -+#define T4COMP_vect_num 17 -+ -+/* Timer/Counter4 Overflow Interrupt */ -+#define T4OVF_vect _VECTOR(18) -+#define T4OVF_vect_num 18 -+ -+/* Timer/Counter5 Compare Match Interrupt */ -+#define T5COMP_vect _VECTOR(19) -+#define T5COMP_vect_num 19 -+ -+/* Timer/Counter5 Overflow Interrupt */ -+#define T5OVF_vect _VECTOR(20) -+#define T5OVF_vect_num 20 -+ -+/* SPI Serial Transfer Complete Interrupt */ -+#define SPI_vect _VECTOR(21) -+#define SPI_vect_num 21 -+ -+/* SPI Rx Buffer Interrupt */ -+#define SRX_FIFO_vect _VECTOR(22) -+#define SRX_FIFO_vect_num 22 -+ -+/* SPI Tx Buffer Interrupt */ -+#define STX_FIFO_vect _VECTOR(23) -+#define STX_FIFO_vect_num 23 -+ -+/* Sequencer State Machine Interrupt */ -+#define SSM_vect _VECTOR(24) -+#define SSM_vect_num 24 -+ -+/* Data FIFO fill level reached Interrupt */ -+#define DFFLR_vect _VECTOR(25) -+#define DFFLR_vect_num 25 -+ -+/* Data FIFO overflow or underflow error Interrupt */ -+#define DFOUE_vect _VECTOR(26) -+#define DFOUE_vect_num 26 -+ -+/* RSSI/Preamble FIFO fill level reached Interrupt */ -+#define SFFLR_vect _VECTOR(27) -+#define SFFLR_vect_num 27 -+ -+/* RSSI/Preamble FIFO overflow or underflow error Interrupt */ -+#define SFOUE_vect _VECTOR(28) -+#define SFOUE_vect_num 28 -+ -+/* Tx Modulator Telegram Finish Interrupt */ -+#define TMTCF_vect _VECTOR(29) -+#define TMTCF_vect_num 29 -+ -+/* UHF receiver wake up ok on Rx path B */ -+#define UHF_WCOB_vect _VECTOR(30) -+#define UHF_WCOB_vect_num 30 -+ -+/* UHF receiver wake up ok on Rx path A */ -+#define UHF_WCOA_vect _VECTOR(31) -+#define UHF_WCOA_vect_num 31 -+ -+/* UHF receiver start of telegram ok on Rx path B */ -+#define UHF_SOTB_vect _VECTOR(32) -+#define UHF_SOTB_vect_num 32 -+ -+/* UHF receiver start of telegram ok on Rx path A */ -+#define UHF_SOTA_vect _VECTOR(33) -+#define UHF_SOTA_vect_num 33 -+ -+/* UHF receiver end of telegram on Rx path B */ -+#define UHF_EOTB_vect _VECTOR(34) -+#define UHF_EOTB_vect_num 34 -+ -+/* UHF receiver end of telegram on Rx path A */ -+#define UHF_EOTA_vect _VECTOR(35) -+#define UHF_EOTA_vect_num 35 -+ -+/* UHF receiver new bit on Rx path B */ -+#define UHF_NBITB_vect _VECTOR(36) -+#define UHF_NBITB_vect_num 36 -+ -+/* UHF receiver new bit on Rx path A */ -+#define UHF_NBITA_vect _VECTOR(37) -+#define UHF_NBITA_vect_num 37 -+ -+/* External input Clock monitoring Interrupt */ -+#define EXCM_vect _VECTOR(38) -+#define EXCM_vect_num 38 -+ -+/* EEPROM Ready Interrupt */ -+#define ERDY_vect _VECTOR(39) -+#define ERDY_vect_num 39 -+ -+/* Store Program Memory Ready */ -+#define SPMR_vect _VECTOR(40) -+#define SPMR_vect_num 40 -+ -+/* IDSCAN Full Interrupt */ -+#define IDFULL_vect _VECTOR(41) -+#define IDFULL_vect_num 41 -+ -+#define _VECTORS_SIZE 168 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 64 -+#define FLASHSTART 0x8000 -+#define FLASHEND 0xCFFF -+#define RAMSTART 0x0200 -+#define RAMSIZE 1024 -+#define RAMEND 0x05FF -+#define E2START 0 -+#define E2SIZE 1152 -+#define E2PAGESIZE 16 -+#define E2END 0x047F -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 1 -+ -+/* Fuse Byte */ -+#define FUSE_CKDIV8 (unsigned char)~_BV(128) -+#define FUSE_DWEN (unsigned char)~_BV(64) -+#define FUSE_SPIEN (unsigned char)~_BV(32) -+#define FUSE_WDTON (unsigned char)~_BV(16) -+#define FUSE_EESAVE (unsigned char)~_BV(8) -+#define FUSE_BOOTRST (unsigned char)~_BV(4) -+#define FUSE_RSTDISBL (unsigned char)~_BV(2) -+#define FUSE_EXTCLKEN (unsigned char)~_BV(1) -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x95 -+#define SIGNATURE_2 0x65 -+ -+ -+#endif /* #ifdef _AVR_ATA5782_H_INCLUDED */ -+ -diff --git a/include/avr/ioa5783.h b/include/avr/ioa5783.h -new file mode 100644 -index 0000000..3411dc2 ---- /dev/null -+++ b/include/avr/ioa5783.h -@@ -0,0 +1,1781 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATA5783_H_INCLUDED -+#define _AVR_ATA5783_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "ioa5783.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PRR0 _SFR_IO8(0x01) -+#define PRSPI 0 -+#define PRRXDC 1 -+#define PRTXDC 2 -+#define PRCRC 3 -+#define PRVM 4 -+#define PRCO 5 -+ -+#define PRR1 _SFR_IO8(0x02) -+#define PRT1 0 -+#define PRT2 1 -+#define PRT3 2 -+#define PRT4 3 -+#define PRT5 4 -+ -+#define PRR2 _SFR_IO8(0x03) -+#define PRXB 0 -+#define PRXA 1 -+#define PRSF 2 -+#define PRDF 3 -+#define PRIDS 4 -+#define PRRS 5 -+#define PRTM 6 -+#define PRSSM 7 -+ -+#define RDPR _SFR_IO8(0x04) -+#define PRPTB 0 -+#define PRPTA 1 -+#define PRFLT 2 -+#define PRTMP 3 -+#define APRPTB 4 -+#define APRPTA 5 -+#define ARDPRF 6 -+#define RDPRF 7 -+ -+#define PINB _SFR_IO8(0x05) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x06) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x07) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x08) -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x09) -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x0A) -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+/* Reserved [0x0B..0x0C] */ -+ -+#define RDSIFR _SFR_IO8(0x0D) -+#define NBITA 0 -+#define NBITB 1 -+#define EOTA 2 -+#define EOTB 3 -+#define SOTA 4 -+#define SOTB 5 -+#define WCOA 6 -+#define WCOB 7 -+ -+#define MCUCR _SFR_IO8(0x0E) -+#define IVCE 0 -+#define IVSEL 1 -+#define SPIIO 2 -+#define ENPS 3 -+#define PUD 4 -+#define PB4HS 5 -+#define PB7LS 6 -+#define PB7HS 7 -+ -+#define PCIFR _SFR_IO8(0x0F) -+#define PCIF0 0 -+#define PCIF1 1 -+ -+#define T0CR _SFR_IO8(0x10) -+#define T0PS0 0 -+#define T0PS1 1 -+#define T0PS2 2 -+#define T0IE 3 -+#define T0PR 4 -+ -+#define T1CR _SFR_IO8(0x11) -+#define T1OTM 0 -+#define T1CTM 1 -+#define T1CRM 2 -+#define T1TOP 4 -+#define T1RES 5 -+#define T1TOS 6 -+#define T1ENA 7 -+ -+#define T2CR _SFR_IO8(0x12) -+#define T2OTM 0 -+#define T2CTM 1 -+#define T2CRM 2 -+#define T2TOP 4 -+#define T2RES 5 -+#define T2TOS 6 -+#define T2ENA 7 -+ -+#define T3CR _SFR_IO8(0x13) -+#define T3OTM 0 -+#define T3CTM 1 -+#define T3CRM 2 -+#define T3CPRM 3 -+#define T3TOP 4 -+#define T3RES 5 -+#define T3TOS 6 -+#define T3ENA 7 -+ -+#define T4CR _SFR_IO8(0x14) -+#define T4OTM 0 -+#define T4CTM 1 -+#define T4CRM 2 -+#define T4CPRM 3 -+#define T4TOP 4 -+#define T4RES 5 -+#define T4TOS 6 -+#define T4ENA 7 -+ -+#define T1IFR _SFR_IO8(0x15) -+#define T1OFF 0 -+#define T1COF 1 -+ -+#define T2IFR _SFR_IO8(0x16) -+#define T2OFF 0 -+#define T2COF 1 -+ -+#define T3IFR _SFR_IO8(0x17) -+#define T3OFF 0 -+#define T3COF 1 -+#define T3ICF 2 -+ -+#define T4IFR _SFR_IO8(0x18) -+#define T4OFF 0 -+#define T4COF 1 -+#define T4ICF 2 -+ -+#define T5IFR _SFR_IO8(0x19) -+#define T5OFF 0 -+#define T5COF 1 -+ -+#define GPIOR0 _SFR_IO8(0x1A) -+ -+#define GPIOR3 _SFR_IO8(0x1B) -+ -+#define GPIOR4 _SFR_IO8(0x1C) -+ -+#define GPIOR5 _SFR_IO8(0x1D) -+ -+#define GPIOR6 _SFR_IO8(0x1E) -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEWE 1 -+#define EEMWE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+#define EEPAGE 6 -+#define NVMBSY 7 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define EEPR _SFR_IO8(0x23) -+#define EEAP0 0 -+#define EEAP1 1 -+#define EEAP2 2 -+#define EEAP3 3 -+ -+#define GPIOR1 _SFR_IO8(0x24) -+ -+#define GPIOR2 _SFR_IO8(0x25) -+ -+#define PCICR _SFR_IO8(0x26) -+#define PCIE0 0 -+#define PCIE1 1 -+ -+#define EIMSK _SFR_IO8(0x27) -+#define INT0 0 -+#define INT1 1 -+ -+#define EIFR _SFR_IO8(0x28) -+#define INTF0 0 -+#define INTF1 1 -+ -+#define CRCDIR _SFR_IO8(0x29) -+ -+#define VMCSR _SFR_IO8(0x2A) -+#define VMLS0 0 -+#define VMLS1 1 -+#define VMLS2 2 -+#define VMLS3 3 -+#define VMIM 4 -+#define VMF 5 -+ -+#define MCUSR _SFR_IO8(0x2B) -+#define PORF 0 -+#define EXTRF 1 -+#define WDRF 3 -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define RXIF 4 -+#define TXIF 5 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+#define T0IFR _SFR_IO8(0x2F) -+#define T0F 0 -+ -+/* Reserved [0x30] */ -+ -+#define DWDR _SFR_IO8(0x31) -+ -+/* Reserved [0x32] */ -+ -+#define RDCR _SFR_IO8(0x33) -+#define RDPU 0 -+#define ADIVEN 1 -+#define RDEN 2 -+ -+#define EOTSA _SFR_IO8(0x34) -+#define CARFA 0 -+#define AMPFA 1 -+#define SYTFA 2 -+#define MANFA 3 -+#define TMOFA 4 -+#define TELRA 5 -+#define RRFA 6 -+#define EOTBF 7 -+ -+#define EOTCA _SFR_IO8(0x35) -+#define CARFEA 0 -+#define AMPFEA 1 -+#define SYTFEA 2 -+#define MANFEA 3 -+#define TMOFEA 4 -+#define TELREA 5 -+#define RRFEA 6 -+#define EOTBFE 7 -+ -+#define EOTSB _SFR_IO8(0x36) -+#define CARFB 0 -+#define AMPFB 1 -+#define SYTFB 2 -+#define MANFB 3 -+#define TMOFB 4 -+#define TELRB 5 -+#define RRFB 6 -+#define EOTAF 7 -+ -+#define EOTCB _SFR_IO8(0x37) -+#define CARFEB 0 -+#define AMPFEB 1 -+#define SYTFEB 2 -+#define MANFEB 3 -+#define TMOFEB 4 -+#define TELREB 5 -+#define RRFEB 6 -+#define EOTAFE 7 -+ -+#define SMCR _SFR_IO8(0x38) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define CMCR _SFR_IO8(0x39) -+#define CMM0 0 -+#define CMM1 1 -+#define CMM2 2 -+#define CCS 3 -+#define SRCD 4 -+#define CMONEN 6 -+#define CMCCE 7 -+ -+#define CMIMR _SFR_IO8(0x3A) -+#define ECIE 0 -+ -+#define CLPR _SFR_IO8(0x3B) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLTPS0 3 -+#define CLTPS1 4 -+#define CLTPS2 5 -+#define CLPCE 7 -+ -+#define SPMCSR _SFR_IO8(0x3C) -+#define SELFPRGEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define SPMIE 7 -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define FSEN _SFR_MEM8(0x60) -+#define SDPU 0 -+#define SDEN 1 -+ -+/* Reserved [0x61..0x63] */ -+ -+#define FFREQ1L _SFR_MEM8(0x64) -+ -+#define FFREQ1M _SFR_MEM8(0x65) -+ -+#define FFREQ1H _SFR_MEM8(0x66) -+ -+#define FFREQ2L _SFR_MEM8(0x67) -+ -+#define FFREQ2M _SFR_MEM8(0x68) -+ -+#define FFREQ2H _SFR_MEM8(0x69) -+ -+/* Reserved [0x6A] */ -+ -+#define EICRA _SFR_MEM8(0x6B) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+ -+#define PCMSK0 _SFR_MEM8(0x6C) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6D) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+ -+#define WDTCR _SFR_MEM8(0x6E) -+#define WDPS0 0 -+#define WDPS1 1 -+#define WDPS2 2 -+#define WDE 3 -+#define WDCE 4 -+ -+#define T1CNT _SFR_MEM8(0x6F) -+ -+#define T1COR _SFR_MEM8(0x70) -+ -+#define T1MR _SFR_MEM8(0x71) -+#define T1CS0 0 -+#define T1CS1 1 -+#define T1PS0 2 -+#define T1PS1 3 -+#define T1PS2 4 -+#define T1PS3 5 -+#define T1DC0 6 -+#define T1DC1 7 -+ -+#define T1IMR _SFR_MEM8(0x72) -+#define T1OIM 0 -+#define T1CIM 1 -+ -+#define T2CNT _SFR_MEM8(0x73) -+ -+#define T2COR _SFR_MEM8(0x74) -+ -+#define T2MR _SFR_MEM8(0x75) -+#define T2CS0 0 -+#define T2CS1 1 -+#define T2PS0 2 -+#define T2PS1 3 -+#define T2PS2 4 -+#define T2PS3 5 -+#define T2DC0 6 -+#define T2DC1 7 -+ -+#define T2IMR _SFR_MEM8(0x76) -+#define T2OIM 0 -+#define T2CIM 1 -+ -+/* Combine T3CNTL and T3CNTH */ -+#define T3CNT _SFR_MEM16(0x77) -+ -+#define T3CNTL _SFR_MEM8(0x77) -+#define T3CNTH _SFR_MEM8(0x78) -+ -+/* Combine T3CORL and T3CORH */ -+#define T3COR _SFR_MEM16(0x79) -+ -+#define T3CORL _SFR_MEM8(0x79) -+#define T3CORH _SFR_MEM8(0x7A) -+ -+/* Combine T3ICRL and T3ICRH */ -+#define T3ICR _SFR_MEM16(0x7B) -+ -+#define T3ICRL _SFR_MEM8(0x7B) -+#define T3ICRH _SFR_MEM8(0x7C) -+ -+#define T3MRA _SFR_MEM8(0x7D) -+#define T3CS0 0 -+#define T3CS1 1 -+#define T3PS0 2 -+#define T3PS1 3 -+#define T3PS2 4 -+ -+#define T3MRB _SFR_MEM8(0x7E) -+#define T3SCE 1 -+#define T3CNC 2 -+#define T3CE0 3 -+#define T3CE1 4 -+#define T3ICS0 5 -+#define T3ICS1 6 -+#define T3ICS2 7 -+ -+#define T3IMR _SFR_MEM8(0x7F) -+#define T3OIM 0 -+#define T3CIM 1 -+#define T3CPIM 2 -+ -+/* Combine T4CNTL and T4CNTH */ -+#define T4CNT _SFR_MEM16(0x80) -+ -+#define T4CNTL _SFR_MEM8(0x80) -+#define T4CNTH _SFR_MEM8(0x81) -+ -+/* Combine T4CORL and T4CORH */ -+#define T4COR _SFR_MEM16(0x82) -+ -+#define T4CORL _SFR_MEM8(0x82) -+#define T4CORH _SFR_MEM8(0x83) -+ -+/* Combine T4ICRL and T4ICRH */ -+#define T4ICR _SFR_MEM16(0x84) -+ -+#define T4ICRL _SFR_MEM8(0x84) -+#define T4ICRH _SFR_MEM8(0x85) -+ -+#define T4MRA _SFR_MEM8(0x86) -+#define T4CS0 0 -+#define T4CS1 1 -+#define T4PS0 2 -+#define T4PS1 3 -+#define T4PS2 4 -+ -+#define T4MRB _SFR_MEM8(0x87) -+#define T4SCE 1 -+#define T4CNC 2 -+#define T4CE0 3 -+#define T4CE1 4 -+#define T4ICS0 5 -+#define T4ICS1 6 -+#define T4ICS2 7 -+ -+#define T4IMR _SFR_MEM8(0x88) -+#define T4OIM 0 -+#define T4CIM 1 -+#define T4CPIM 2 -+ -+/* Reserved [0x89] */ -+ -+/* Combine T5OCRL and T5OCRH */ -+#define T5OCR _SFR_MEM16(0x8A) -+ -+#define T5OCRL _SFR_MEM8(0x8A) -+#define T5OCRH _SFR_MEM8(0x8B) -+ -+#define T5CCR _SFR_MEM8(0x8C) -+#define T5CS0 0 -+#define T5CS1 1 -+#define T5CS2 2 -+#define T5CTC 3 -+ -+/* Combine T5CNTL and T5CNTH */ -+#define T5CNT _SFR_MEM16(0x8D) -+ -+#define T5CNTL _SFR_MEM8(0x8D) -+#define T5CNTH _SFR_MEM8(0x8E) -+ -+#define T5IMR _SFR_MEM8(0x8F) -+#define T5OIM 0 -+#define T5CIM 1 -+ -+#define GTCCR _SFR_MEM8(0x90) -+#define PSR10 0 -+#define TSM 7 -+ -+#define SOTSB _SFR_MEM8(0x91) -+#define CAROB 0 -+#define AMPOB 1 -+#define SYTOB 2 -+#define MANOB 3 -+#define WUPOB 4 -+#define SFIDOB 5 -+#define RROB 6 -+#define WCOAO 7 -+ -+#define SOTSA _SFR_MEM8(0x92) -+#define CAROA 0 -+#define AMPOA 1 -+#define SYTOA 2 -+#define MANOA 3 -+#define WUPOA 4 -+#define SFIDOA 5 -+#define RROA 6 -+#define WCOBO 7 -+ -+#define SOTCB _SFR_MEM8(0x93) -+#define CAROEB 0 -+#define AMPOEB 1 -+#define SYTOEB 2 -+#define MANOEB 3 -+#define WUPEB 4 -+#define SFIDEB 5 -+#define RROEB 6 -+#define WCOAOE 7 -+ -+#define SOTCA _SFR_MEM8(0x94) -+#define CAROEA 0 -+#define AMPOEA 1 -+#define SYTOEA 2 -+#define MANOEA 3 -+#define WUPEA 4 -+#define SFIDEA 5 -+#define RROEA 6 -+#define WCOBOE 7 -+ -+#define TESRB _SFR_MEM8(0x95) -+#define CRCOB 0 -+#define EOTLB0 1 -+#define EOTLB1 2 -+ -+#define TESRA _SFR_MEM8(0x96) -+#define CRCOA 0 -+#define EOTLA0 1 -+#define EOTLA1 2 -+ -+/* Reserved [0x97] */ -+ -+#define RDSIMR _SFR_MEM8(0x98) -+#define NBITAM 0 -+#define NBITBM 1 -+#define EOTAM 2 -+#define EOTBM 3 -+#define SOTAM 4 -+#define SOTBM 5 -+#define WCOAM 6 -+#define WCOBM 7 -+ -+#define RDOCR _SFR_MEM8(0x99) -+#define TMDS0 1 -+#define TMDS1 2 -+#define ETRPA 3 -+#define ETRPB 4 -+#define RDSIDA 5 -+#define RDSIDB 6 -+ -+/* Reserved [0x9A] */ -+ -+#define TEMPL _SFR_MEM8(0x9B) -+ -+#define TEMPH _SFR_MEM8(0x9C) -+ -+#define SYCB _SFR_MEM8(0x9D) -+#define SYCSB0 0 -+#define SYCSB1 1 -+#define SYCSB2 2 -+#define SYCSB3 3 -+#define SYTLB0 4 -+#define SYTLB1 5 -+#define SYTLB2 6 -+#define SYTLB3 7 -+ -+#define SYCA _SFR_MEM8(0x9E) -+#define SYCSA0 0 -+#define SYCSA1 1 -+#define SYCSA2 2 -+#define SYCSA3 3 -+#define SYTLA0 4 -+#define SYTLA1 5 -+#define SYTLA2 6 -+#define SYTLA3 7 -+ -+#define RXFOB _SFR_MEM8(0x9F) -+ -+#define RXFOA _SFR_MEM8(0xA0) -+ -+#define DMMB _SFR_MEM8(0xA1) -+#define DMATB0 0 -+#define DMATB1 1 -+#define DMATB2 2 -+#define DMATB3 3 -+#define DMATB4 4 -+#define DMPB 5 -+#define DMHB 6 -+#define DMNEB 7 -+ -+#define DMMA _SFR_MEM8(0xA2) -+#define DMATA0 0 -+#define DMATA1 1 -+#define DMATA2 2 -+#define DMATA3 3 -+#define DMATA4 4 -+#define DMPA 5 -+#define DMHA 6 -+#define DMNEA 7 -+ -+#define DMCDB _SFR_MEM8(0xA3) -+#define DMCLB0 0 -+#define DMCLB1 1 -+#define DMCLB2 2 -+#define DMCLB3 3 -+#define DMCLB4 4 -+#define DMCTB0 5 -+#define DMCTB1 6 -+#define DMCTB2 7 -+ -+#define DMCDA _SFR_MEM8(0xA4) -+#define DMCLA0 0 -+#define DMCLA1 1 -+#define DMCLA2 2 -+#define DMCLA3 3 -+#define DMCLA4 4 -+#define DMCTA0 5 -+#define DMCTA1 6 -+#define DMCTA2 7 -+ -+#define DMCRB _SFR_MEM8(0xA5) -+#define DMPGB0 0 -+#define DMPGB1 1 -+#define DMPGB2 2 -+#define DMPGB3 3 -+#define DMPGB4 4 -+#define SASKB 5 -+#define SY1TB 6 -+#define DMARB 7 -+ -+#define DMCRA _SFR_MEM8(0xA6) -+#define DMPGA0 0 -+#define DMPGA1 1 -+#define DMPGA2 2 -+#define DMPGA3 3 -+#define DMPGA4 4 -+#define SASKA 5 -+#define SY1TA 6 -+#define DMARA 7 -+ -+#define DMDRB _SFR_MEM8(0xA7) -+#define DMAB0 0 -+#define DMAB1 1 -+#define DMAB2 2 -+#define DMAB3 3 -+#define DMDNB0 4 -+#define DMDNB1 5 -+#define DMDNB2 6 -+#define DMDNB3 7 -+ -+#define DMDRA _SFR_MEM8(0xA8) -+#define DMAA0 0 -+#define DMAA1 1 -+#define DMAA2 2 -+#define DMAA3 3 -+#define DMDNA0 4 -+#define DMDNA1 5 -+#define DMDNA2 6 -+#define DMDNA3 7 -+ -+#define CHCR _SFR_MEM8(0xA9) -+#define BWM0 0 -+#define BWM1 1 -+#define BWM2 2 -+#define BWM3 3 -+ -+#define CHDN _SFR_MEM8(0xAA) -+#define BBDN0 0 -+#define BBDN1 1 -+#define BBDN2 2 -+#define BBDN3 3 -+#define BBDN4 4 -+#define ADCDN 5 -+ -+#define SFIDCB _SFR_MEM8(0xAB) -+#define SFIDTB0 0 -+#define SFIDTB1 1 -+#define SFIDTB2 2 -+#define SFIDTB3 3 -+#define SFIDTB4 4 -+#define SEMEB 7 -+ -+#define SFIDLB _SFR_MEM8(0xAC) -+#define SFIDLB0 0 -+#define SFIDLB1 1 -+#define SFIDLB2 2 -+#define SFIDLB3 3 -+#define SFIDLB4 4 -+#define SFIDLB5 5 -+ -+#define WUPTB _SFR_MEM8(0xAD) -+#define WUPTB0 0 -+#define WUPTB1 1 -+#define WUPTB2 2 -+#define WUPTB3 3 -+#define WUPTB4 4 -+ -+#define WUPLB _SFR_MEM8(0xAE) -+#define WUPLB0 0 -+#define WUPLB1 1 -+#define WUPLB2 2 -+#define WUPLB3 3 -+#define WUPLB4 4 -+#define WUPLB5 5 -+ -+#define SFID1B _SFR_MEM8(0xAF) -+ -+#define SFID2B _SFR_MEM8(0xB0) -+ -+#define SFID3B _SFR_MEM8(0xB1) -+ -+#define SFID4B _SFR_MEM8(0xB2) -+ -+#define WUP1B _SFR_MEM8(0xB3) -+ -+#define WUP2B _SFR_MEM8(0xB4) -+ -+#define WUP3B _SFR_MEM8(0xB5) -+ -+#define WUP4B _SFR_MEM8(0xB6) -+ -+#define SFIDCA _SFR_MEM8(0xB7) -+#define SFIDTA0 0 -+#define SFIDTA1 1 -+#define SFIDTA2 2 -+#define SFIDTA3 3 -+#define SFIDTA4 4 -+#define SEMEA 7 -+ -+#define SFIDLA _SFR_MEM8(0xB8) -+#define SFIDLA0 0 -+#define SFIDLA1 1 -+#define SFIDLA2 2 -+#define SFIDLA3 3 -+#define SFIDLA4 4 -+#define SFIDLA5 5 -+ -+#define WUPTA _SFR_MEM8(0xB9) -+#define WUPTA0 0 -+#define WUPTA1 1 -+#define WUPTA2 2 -+#define WUPTA3 3 -+#define WUPTA4 4 -+ -+#define WUPLA _SFR_MEM8(0xBA) -+#define WUPLA0 0 -+#define WUPLA1 1 -+#define WUPLA2 2 -+#define WUPLA3 3 -+#define WUPLA4 4 -+#define WUPLA5 5 -+ -+#define SFID1A _SFR_MEM8(0xBB) -+ -+#define SFID2A _SFR_MEM8(0xBC) -+ -+#define SFID3A _SFR_MEM8(0xBD) -+ -+#define SFID4A _SFR_MEM8(0xBE) -+ -+#define WUP1A _SFR_MEM8(0xBF) -+ -+#define WUP2A _SFR_MEM8(0xC0) -+ -+#define WUP3A _SFR_MEM8(0xC1) -+ -+#define WUP4A _SFR_MEM8(0xC2) -+ -+#define CLKOD _SFR_MEM8(0xC3) -+ -+#define CLKOCR _SFR_MEM8(0xC4) -+#define CLKOS0 0 -+#define CLKOS1 1 -+#define CLKOEN 2 -+ -+#define XFUSE _SFR_MEM8(0xC5) -+ -+#define SRCCAL _SFR_MEM8(0xC6) -+#define SRCCAL0 0 -+#define SRCCAL1 1 -+#define SRCCAL2 2 -+#define SRCCAL3 3 -+#define SRCCAL4 4 -+#define SRCCAL5 5 -+#define SRCTC0 6 -+#define SRCTC1 7 -+ -+#define FRCCAL _SFR_MEM8(0xC7) -+#define FRCCAL0 0 -+#define FRCCAL1 1 -+#define FRCCAL2 2 -+#define FRCCAL3 3 -+#define FRCCAL4 4 -+#define FRCTC 5 -+ -+#define CMSR _SFR_MEM8(0xC8) -+#define ECF 0 -+ -+#define CMOCR _SFR_MEM8(0xC9) -+#define FRCAO 0 -+#define SRCAO 1 -+#define FRCACT 2 -+#define SRCACT 3 -+ -+#define SUPFR _SFR_MEM8(0xCA) -+#define AVCCRF 0 -+#define AVCCLF 1 -+ -+#define SUPCR _SFR_MEM8(0xCB) -+#define AVCCRM 0 -+#define AVCCLM 1 -+#define PVEN 2 -+#define DVDIS 4 -+#define AVEN 5 -+#define AVDIC 6 -+ -+/* Reserved [0xCC] */ -+ -+#define SUPCA2 _SFR_MEM8(0xCD) -+#define BGCAL0 0 -+#define BGCAL1 1 -+#define BGCAL2 2 -+#define BGCAL3 3 -+ -+#define SUPCA3 _SFR_MEM8(0xCE) -+#define ACAL4 0 -+#define ACAL5 1 -+#define ACAL6 2 -+#define ACAL7 3 -+#define DCAL4 4 -+#define DCAL5 5 -+#define DCAL6 6 -+ -+#define SUPCA4 _SFR_MEM8(0xCF) -+#define ACAL0 0 -+#define ACAL1 1 -+#define ACAL2 2 -+#define ACAL3 3 -+#define DCAL0 4 -+#define DCAL1 5 -+#define DCAL2 6 -+#define DCAL3 7 -+ -+#define CALRDY _SFR_MEM8(0xD0) -+ -+#define VMCAL _SFR_MEM8(0xD1) -+#define VMCAL0 0 -+#define VMCAL1 1 -+#define VMCAL2 2 -+ -+#define DFS _SFR_MEM8(0xD2) -+#define DFFLRF 0 -+#define DFUFL 1 -+#define DFOFL 2 -+ -+/* Combine DFTLL and DFTLH */ -+#define DFTL _SFR_MEM16(0xD3) -+ -+#define DFTLL _SFR_MEM8(0xD3) -+#define DFTLH _SFR_MEM8(0xD4) -+ -+#define DFL _SFR_MEM8(0xD5) -+#define DFFLS0 0 -+#define DFFLS1 1 -+#define DFFLS2 2 -+#define DFFLS3 3 -+#define DFFLS4 4 -+#define DFFLS5 5 -+#define DFCLR 7 -+ -+#define DFWP _SFR_MEM8(0xD6) -+#define DFWP0 0 -+#define DFWP1 1 -+#define DFWP2 2 -+#define DFWP3 3 -+#define DFWP4 4 -+#define DFWP5 5 -+ -+#define DFRP _SFR_MEM8(0xD7) -+#define DFRP0 0 -+#define DFRP1 1 -+#define DFRP2 2 -+#define DFRP3 3 -+#define DFRP4 4 -+#define DFRP5 5 -+ -+#define DFD _SFR_MEM8(0xD8) -+ -+#define DFI _SFR_MEM8(0xD9) -+#define DFFLIM 0 -+#define DFERIM 1 -+ -+#define DFC _SFR_MEM8(0xDA) -+#define DFFLC0 0 -+#define DFFLC1 1 -+#define DFFLC2 2 -+#define DFFLC3 3 -+#define DFFLC4 4 -+#define DFFLC5 5 -+#define DFDRA 7 -+ -+#define SFS _SFR_MEM8(0xDB) -+#define SFFLRF 0 -+#define SFUFL 1 -+#define SFOFL 2 -+ -+#define SFL _SFR_MEM8(0xDC) -+#define SFFLS0 0 -+#define SFFLS1 1 -+#define SFFLS2 2 -+#define SFFLS3 3 -+#define SFFLS4 4 -+#define SFCLR 7 -+ -+#define SFWP _SFR_MEM8(0xDD) -+#define SFWP0 0 -+#define SFWP1 1 -+#define SFWP2 2 -+#define SFWP3 3 -+#define SFWP4 4 -+ -+#define SFRP _SFR_MEM8(0xDE) -+#define SFRP0 0 -+#define SFRP1 1 -+#define SFRP2 2 -+#define SFRP3 3 -+#define SFRP4 4 -+ -+#define SFD _SFR_MEM8(0xDF) -+ -+#define SFI _SFR_MEM8(0xE0) -+#define SFFLIM 0 -+#define SFERIM 1 -+ -+#define SFC _SFR_MEM8(0xE1) -+#define SFFLC0 0 -+#define SFFLC1 1 -+#define SFFLC2 2 -+#define SFFLC3 3 -+#define SFFLC4 4 -+#define SFDRA 7 -+ -+#define SSMCR _SFR_MEM8(0xE2) -+#define SSMTX 0 -+#define SSMTM 1 -+#define SSMTGE 2 -+#define SSMTPE 3 -+#define SSMPVE 4 -+#define SSMTAE 5 -+#define SETRPA 6 -+#define SETRPB 7 -+ -+#define SSMRCR _SFR_MEM8(0xE3) -+#define SSMPA 0 -+#define SSMPB 1 -+#define SSMADA 2 -+#define SSMADB 3 -+#define SSMPVS 4 -+#define SSMIFA 5 -+#define SSMIDSE 6 -+#define SSMTMOE 7 -+ -+#define SSMFBR _SFR_MEM8(0xE4) -+#define SSMFID0 0 -+#define SSMFID1 1 -+#define SSMFID2 2 -+#define SSMDFDT 3 -+#define SSMHADT 4 -+#define SSMPLDT 5 -+ -+#define SSMRR _SFR_MEM8(0xE5) -+#define SSMR 0 -+#define SSMST 1 -+ -+#define SSMSR _SFR_MEM8(0xE6) -+#define SSMESM0 0 -+#define SSMESM1 1 -+#define SSMESM2 2 -+#define SSMESM3 3 -+#define SSMERR 7 -+ -+#define SSMIFR _SFR_MEM8(0xE7) -+#define SSMIF 0 -+ -+#define SSMIMR _SFR_MEM8(0xE8) -+#define SSMIM 0 -+ -+#define MSMSTR _SFR_MEM8(0xE9) -+#define SSMMST0 0 -+#define SSMMST1 1 -+#define SSMMST2 2 -+#define SSMMST3 3 -+#define SSMMST4 4 -+ -+#define SSMSTR _SFR_MEM8(0xEA) -+#define SSMSTA0 0 -+#define SSMSTA1 1 -+#define SSMSTA2 2 -+#define SSMSTA3 3 -+#define SSMSTA4 4 -+#define SSMSTA5 5 -+ -+#define SSMXSR _SFR_MEM8(0xEB) -+#define SSMSTB0 0 -+#define SSMSTB1 1 -+#define SSMSTB2 2 -+#define SSMSTB3 3 -+#define SSMSTB4 4 -+#define SSMSTB5 5 -+ -+#define MSMCR1 _SFR_MEM8(0xEC) -+#define MSMSM00 0 -+#define MSMSM01 1 -+#define MSMSM02 2 -+#define MSMSM03 3 -+#define MSMSM10 4 -+#define MSMSM11 5 -+#define MSMSM12 6 -+#define MSMSM13 7 -+ -+#define MSMCR2 _SFR_MEM8(0xED) -+#define MSMSM20 0 -+#define MSMSM21 1 -+#define MSMSM22 2 -+#define MSMSM23 3 -+#define MSMSM30 4 -+#define MSMSM31 5 -+#define MSMSM32 6 -+#define MSMSM33 7 -+ -+#define MSMCR3 _SFR_MEM8(0xEE) -+#define MSMSM40 0 -+#define MSMSM41 1 -+#define MSMSM42 2 -+#define MSMSM43 3 -+#define MSMSM50 4 -+#define MSMSM51 5 -+#define MSMSM52 6 -+#define MSMSM53 7 -+ -+#define MSMCR4 _SFR_MEM8(0xEF) -+#define MSMSM60 0 -+#define MSMSM61 1 -+#define MSMSM62 2 -+#define MSMSM63 3 -+#define MSMSM70 4 -+#define MSMSM71 5 -+#define MSMSM72 6 -+#define MSMSM73 7 -+ -+#define GTCR _SFR_MEM8(0xF0) -+#define RXTEHA 0 -+#define GAPMA 1 -+#define DARA 2 -+#define IWUPA 3 -+#define RXTEHB 4 -+#define GAPMB 5 -+#define DARB 6 -+#define IWUPB 7 -+ -+#define SOTC1A _SFR_MEM8(0xF1) -+#define CAROEA1 0 -+#define AMPOEA1 1 -+#define SYTOEA1 2 -+#define MANOEA1 3 -+#define WUPEA1 4 -+#define SFIDEA1 5 -+#define RROEA1 6 -+#define WCOBOE1 7 -+ -+#define SOTC2A _SFR_MEM8(0xF2) -+#define CAROEA2 0 -+#define AMPOEA2 1 -+#define SYTOEA2 2 -+#define MANOEA2 3 -+#define WUPEA2 4 -+#define SFIDEA2 5 -+#define RROEA2 6 -+#define WCOBOE2 7 -+ -+#define SOTC1B _SFR_MEM8(0xF3) -+#define CAROEB1 0 -+#define AMPOEB1 1 -+#define SYTOEB1 2 -+#define MANOEB1 3 -+#define WUPEB1 4 -+#define SFIDEB1 5 -+#define RROEB1 6 -+#define WCOAOE1 7 -+ -+#define SOTC2B _SFR_MEM8(0xF4) -+#define CAROEB2 0 -+#define AMPOEB2 1 -+#define SYTOEB2 2 -+#define MANOEB2 3 -+#define WUPEB2 4 -+#define SFIDEB2 5 -+#define RROEB2 6 -+#define WCOAOE2 7 -+ -+#define EOTC1A _SFR_MEM8(0xF5) -+#define CARFEA1 0 -+#define AMPFEA1 1 -+#define SYTFEA1 2 -+#define MANFEA1 3 -+#define TMOFEA1 4 -+#define TELREA1 5 -+#define RRFEA1 6 -+#define EOTBFE1 7 -+ -+#define EOTC2A _SFR_MEM8(0xF6) -+#define CARFEA2 0 -+#define AMPFEA2 1 -+#define SYTFEA2 2 -+#define MANFEA2 3 -+#define TMOFEA2 4 -+#define TELREA2 5 -+#define RRFEA2 6 -+#define EOTBFE2 7 -+ -+#define EOTC3A _SFR_MEM8(0xF7) -+#define CARFEA3 0 -+#define AMPFEA3 1 -+#define SYTFEA3 2 -+#define MANFEA3 3 -+#define TMOFEA3 4 -+#define TELREA3 5 -+#define RRFEA3 6 -+#define EOTBFE3 7 -+ -+#define EOTC1B _SFR_MEM8(0xF8) -+#define CARFEB1 0 -+#define AMPFEB1 1 -+#define SYTFEB1 2 -+#define MANFEB1 3 -+#define TMOFEB1 4 -+#define TELREB1 5 -+#define RRFEB1 6 -+#define EOTAFE1 7 -+ -+#define EOTC2B _SFR_MEM8(0xF9) -+#define CARFEB2 0 -+#define AMPFEB2 1 -+#define SYTFEB2 2 -+#define MANFEB2 3 -+#define TMOFEB2 4 -+#define TELREB2 5 -+#define RRFEB2 6 -+#define EOTAFE2 7 -+ -+#define EOTC3B _SFR_MEM8(0xFA) -+#define CARFEB3 0 -+#define AMPFEB3 1 -+#define SYTFEB3 2 -+#define MANFEB3 3 -+#define TMOFEB3 4 -+#define TELREB3 5 -+#define RRFEB3 6 -+#define EOTAFE3 7 -+ -+#define WCOTOA _SFR_MEM8(0xFB) -+ -+#define WCOTOB _SFR_MEM8(0xFC) -+ -+#define SOTTOA _SFR_MEM8(0xFD) -+ -+#define SOTTOB _SFR_MEM8(0xFE) -+ -+#define SSMFCR _SFR_MEM8(0xFF) -+#define SSMIDSO 0 -+#define SSMIDSF 1 -+ -+#define FESR _SFR_MEM8(0x100) -+#define LBSAT 0 -+#define HBSAT 1 -+#define XRDY 2 -+#define PLCK 3 -+ -+#define FEEN1 _SFR_MEM8(0x101) -+#define PLEN 0 -+#define PLCAL 1 -+#define XTOEN 2 -+#define LNAEN 3 -+#define ADEN 4 -+#define ADCLK 5 -+#define PLSP1 6 -+#define ATEN 7 -+ -+#define FEEN2 _SFR_MEM8(0x102) -+#define SDRX 0 -+#define SDRX2 1 -+#define PAEN 2 -+#define TMPM 3 -+#define PLPEN 4 -+#define XTPEN 5 -+ -+#define FELNA _SFR_MEM8(0x103) -+#define LBH0 0 -+#define LBH1 1 -+#define LBH2 2 -+#define LBH3 3 -+#define LBL0 4 -+#define LBL1 5 -+#define LBL2 6 -+#define LBL3 7 -+ -+/* Reserved [0x104..0x105] */ -+ -+#define FEVCT _SFR_MEM8(0x106) -+#define FEVCT0 0 -+#define FEVCT1 1 -+#define FEVCT2 2 -+#define FEVCT3 3 -+ -+#define FEBT _SFR_MEM8(0x107) -+#define CTN20 0 -+#define CTN21 1 -+#define RTN20 2 -+#define RTN21 3 -+ -+#define FEMS _SFR_MEM8(0x108) -+#define PLLS0 0 -+#define PLLS1 1 -+#define PLLS2 2 -+#define PLLS3 3 -+#define PLLM0 4 -+#define PLLM1 5 -+#define PLLM2 6 -+#define PLLM3 7 -+ -+#define FETN4 _SFR_MEM8(0x109) -+#define CTN40 0 -+#define CTN41 1 -+#define CTN42 2 -+#define CTN43 3 -+#define RTN40 4 -+#define RTN41 5 -+#define RTN42 6 -+#define RTN43 7 -+ -+#define FECR _SFR_MEM8(0x10A) -+#define LBNHB 0 -+#define S4N3 1 -+#define ANDP 2 -+#define ADHS 3 -+#define PLCKG 4 -+#define ANPS 5 -+ -+#define FEVCO _SFR_MEM8(0x10B) -+#define CPCC0 0 -+#define CPCC1 1 -+#define CPCC2 2 -+#define CPCC3 3 -+#define VCOB0 4 -+#define VCOB1 5 -+#define VCOB2 6 -+#define VCOB3 7 -+ -+#define FEALR _SFR_MEM8(0x10C) -+#define RNGE0 0 -+#define RNGE1 1 -+ -+#define FEANT _SFR_MEM8(0x10D) -+#define LVLC0 0 -+#define LVLC1 1 -+#define LVLC2 2 -+#define LVLC3 3 -+ -+#define FEBIA _SFR_MEM8(0x10E) -+#define IFAEN 7 -+ -+/* Reserved [0x10F..0x12E] */ -+ -+#define RXBC1 _SFR_MEM8(0x12F) -+#define RXCEA 0 -+#define RXCBLA0 1 -+#define RXCBLA1 2 -+#define RXMSBA 3 -+#define RXCEB 4 -+#define RXCBLB0 5 -+#define RXCBLB1 6 -+#define RXMSBB 7 -+ -+#define RXBC2 _SFR_MEM8(0x130) -+#define RXBPB 0 -+#define RXBF 1 -+#define RXBCLR 2 -+ -+#define RXTLLB _SFR_MEM8(0x131) -+ -+#define RXTLHB _SFR_MEM8(0x132) -+#define RXTLHB0 0 -+#define RXTLHB1 1 -+#define RXTLHB2 2 -+#define RXTLHB3 3 -+ -+#define RXCRLB _SFR_MEM8(0x133) -+ -+#define RXCRHB _SFR_MEM8(0x134) -+ -+#define RXCSBB _SFR_MEM8(0x135) -+ -+#define RXCILB _SFR_MEM8(0x136) -+ -+#define RXCIHB _SFR_MEM8(0x137) -+ -+#define RXCPLB _SFR_MEM8(0x138) -+ -+#define RXCPHB _SFR_MEM8(0x139) -+ -+#define RXDSB _SFR_MEM8(0x13A) -+ -+#define RXTLLA _SFR_MEM8(0x13B) -+ -+#define RXTLHA _SFR_MEM8(0x13C) -+#define RXTLHA0 0 -+#define RXTLHA1 1 -+#define RXTLHA2 2 -+#define RXTLHA3 3 -+ -+#define RXCRLA _SFR_MEM8(0x13D) -+ -+#define RXCRHA _SFR_MEM8(0x13E) -+ -+#define RXCSBA _SFR_MEM8(0x13F) -+ -+#define RXCILA _SFR_MEM8(0x140) -+ -+#define RXCIHA _SFR_MEM8(0x141) -+ -+#define RXCPLA _SFR_MEM8(0x142) -+ -+#define RXCPHA _SFR_MEM8(0x143) -+ -+#define RXDSA _SFR_MEM8(0x144) -+ -+#define CRCCR _SFR_MEM8(0x145) -+#define CRCRS 0 -+#define REFLI 1 -+#define REFLO 2 -+ -+#define CRCDOR _SFR_MEM8(0x146) -+ -+#define IDB0 _SFR_MEM8(0x147) -+ -+#define IDB1 _SFR_MEM8(0x148) -+ -+#define IDB2 _SFR_MEM8(0x149) -+ -+#define IDB3 _SFR_MEM8(0x14A) -+ -+#define IDC _SFR_MEM8(0x14B) -+#define IDL0 0 -+#define IDL1 1 -+#define IDBO0 2 -+#define IDBO1 3 -+#define IDFIM 5 -+#define IDCLR 6 -+#define IDCE 7 -+ -+#define IDS _SFR_MEM8(0x14C) -+#define IDOK 0 -+#define IDFULL 1 -+ -+#define RSSAV _SFR_MEM8(0x14D) -+ -+#define RSSPK _SFR_MEM8(0x14E) -+ -+#define RSSL _SFR_MEM8(0x14F) -+ -+#define RSSH _SFR_MEM8(0x150) -+ -+#define RSSC _SFR_MEM8(0x151) -+#define RSUP0 0 -+#define RSUP1 1 -+#define RSUP2 2 -+#define RSUP3 3 -+#define RSWLH 4 -+#define RSHRX 5 -+#define RSPKF 6 -+ -+#define DBCR _SFR_MEM8(0x152) -+#define DBMD 0 -+#define DBCS 1 -+#define DBTMS 2 -+#define DBHA 3 -+ -+#define DBTC _SFR_MEM8(0x153) -+ -+#define DBENB _SFR_MEM8(0x154) -+ -+#define DBENC _SFR_MEM8(0x155) -+ -+#define DBGSW _SFR_MEM8(0x156) -+#define DBGGS0 0 -+#define DBGGS1 1 -+#define DBGGS2 2 -+#define DBGGS3 3 -+#define CPBFOS0 4 -+#define CPBFOS1 5 -+#define CPBF 6 -+#define DBGSE 7 -+ -+#define SFFR _SFR_MEM8(0x157) -+#define RFL0 0 -+#define RFL1 1 -+#define RFL2 2 -+#define RFC 3 -+#define TFL0 4 -+#define TFL1 5 -+#define TFL2 6 -+#define TFC 7 -+ -+#define SFIR _SFR_MEM8(0x158) -+#define RIL0 0 -+#define RIL1 1 -+#define RIL2 2 -+#define SRIE 3 -+#define TIL0 4 -+#define TIL1 5 -+#define TIL2 6 -+#define STIE 7 -+ -+#define EECR2 _SFR_MEM8(0x159) -+#define EEBRE 0 -+ -+#define PGMST _SFR_MEM8(0x15A) -+#define PGMSYN0 0 -+#define PGMSYN1 1 -+#define PGMSYN2 2 -+#define PGMSYN3 3 -+#define PGMSYN4 4 -+ -+#define EEST _SFR_MEM8(0x15B) -+#define EESYN0 0 -+#define EESYN1 1 -+#define EESYN2 2 -+#define EESYN3 3 -+ -+#define RSIFG _SFR_MEM8(0x15C) -+ -+#define RSLDV _SFR_MEM8(0x15D) -+ -+#define RSHDV _SFR_MEM8(0x15E) -+ -+#define RSCOM _SFR_MEM8(0x15F) -+#define RSDC 0 -+#define RSIFC 1 -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCI0_vect _VECTOR(3) -+#define PCI0_vect_num 3 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCI1_vect _VECTOR(4) -+#define PCI1_vect_num 4 -+ -+/* Voltage Monitoring Interrupt */ -+#define VMON_vect _VECTOR(5) -+#define VMON_vect_num 5 -+ -+/* AVCC Reset Interrupt */ -+#define AVCCR_vect _VECTOR(6) -+#define AVCCR_vect_num 6 -+ -+/* AVCC Low Interrupt */ -+#define AVCCL_vect _VECTOR(7) -+#define AVCCL_vect_num 7 -+ -+/* Timer 0 Interval Interrupt */ -+#define T0INT_vect _VECTOR(8) -+#define T0INT_vect_num 8 -+ -+/* Timer/Counter1 Compare Match Interrupt */ -+#define T1COMP_vect _VECTOR(9) -+#define T1COMP_vect_num 9 -+ -+/* Timer/Counter1 Overflow Interrupt */ -+#define T1OVF_vect _VECTOR(10) -+#define T1OVF_vect_num 10 -+ -+/* Timer/Counter2 Compare Match Interrupt */ -+#define T2COMP_vect _VECTOR(11) -+#define T2COMP_vect_num 11 -+ -+/* Timer/Counter2 Overflow Interrupt */ -+#define T2OVF_vect _VECTOR(12) -+#define T2OVF_vect_num 12 -+ -+/* Timer/Counter3 Capture Event Interrupt */ -+#define T3CAP_vect _VECTOR(13) -+#define T3CAP_vect_num 13 -+ -+/* Timer/Counter3 Compare Match Interrupt */ -+#define T3COMP_vect _VECTOR(14) -+#define T3COMP_vect_num 14 -+ -+/* Timer/Counter3 Overflow Interrupt */ -+#define T3OVF_vect _VECTOR(15) -+#define T3OVF_vect_num 15 -+ -+/* Timer/Counter4 Capture Event Interrupt */ -+#define T4CAP_vect _VECTOR(16) -+#define T4CAP_vect_num 16 -+ -+/* Timer/Counter4 Compare Match Interrupt */ -+#define T4COMP_vect _VECTOR(17) -+#define T4COMP_vect_num 17 -+ -+/* Timer/Counter4 Overflow Interrupt */ -+#define T4OVF_vect _VECTOR(18) -+#define T4OVF_vect_num 18 -+ -+/* Timer/Counter5 Compare Match Interrupt */ -+#define T5COMP_vect _VECTOR(19) -+#define T5COMP_vect_num 19 -+ -+/* Timer/Counter5 Overflow Interrupt */ -+#define T5OVF_vect _VECTOR(20) -+#define T5OVF_vect_num 20 -+ -+/* SPI Serial Transfer Complete Interrupt */ -+#define SPI_vect _VECTOR(21) -+#define SPI_vect_num 21 -+ -+/* SPI Rx Buffer Interrupt */ -+#define SRX_FIFO_vect _VECTOR(22) -+#define SRX_FIFO_vect_num 22 -+ -+/* SPI Tx Buffer Interrupt */ -+#define STX_FIFO_vect _VECTOR(23) -+#define STX_FIFO_vect_num 23 -+ -+/* Sequencer State Machine Interrupt */ -+#define SSM_vect _VECTOR(24) -+#define SSM_vect_num 24 -+ -+/* Data FIFO fill level reached Interrupt */ -+#define DFFLR_vect _VECTOR(25) -+#define DFFLR_vect_num 25 -+ -+/* Data FIFO overflow or underflow error Interrupt */ -+#define DFOUE_vect _VECTOR(26) -+#define DFOUE_vect_num 26 -+ -+/* RSSI/Preamble FIFO fill level reached Interrupt */ -+#define SFFLR_vect _VECTOR(27) -+#define SFFLR_vect_num 27 -+ -+/* RSSI/Preamble FIFO overflow or underflow error Interrupt */ -+#define SFOUE_vect _VECTOR(28) -+#define SFOUE_vect_num 28 -+ -+/* Tx Modulator Telegram Finish Interrupt */ -+#define TMTCF_vect _VECTOR(29) -+#define TMTCF_vect_num 29 -+ -+/* UHF receiver wake up ok on Rx path B */ -+#define UHF_WCOB_vect _VECTOR(30) -+#define UHF_WCOB_vect_num 30 -+ -+/* UHF receiver wake up ok on Rx path A */ -+#define UHF_WCOA_vect _VECTOR(31) -+#define UHF_WCOA_vect_num 31 -+ -+/* UHF receiver start of telegram ok on Rx path B */ -+#define UHF_SOTB_vect _VECTOR(32) -+#define UHF_SOTB_vect_num 32 -+ -+/* UHF receiver start of telegram ok on Rx path A */ -+#define UHF_SOTA_vect _VECTOR(33) -+#define UHF_SOTA_vect_num 33 -+ -+/* UHF receiver end of telegram on Rx path B */ -+#define UHF_EOTB_vect _VECTOR(34) -+#define UHF_EOTB_vect_num 34 -+ -+/* UHF receiver end of telegram on Rx path A */ -+#define UHF_EOTA_vect _VECTOR(35) -+#define UHF_EOTA_vect_num 35 -+ -+/* UHF receiver new bit on Rx path B */ -+#define UHF_NBITB_vect _VECTOR(36) -+#define UHF_NBITB_vect_num 36 -+ -+/* UHF receiver new bit on Rx path A */ -+#define UHF_NBITA_vect _VECTOR(37) -+#define UHF_NBITA_vect_num 37 -+ -+/* External input Clock monitoring Interrupt */ -+#define EXCM_vect _VECTOR(38) -+#define EXCM_vect_num 38 -+ -+/* EEPROM Ready Interrupt */ -+#define ERDY_vect _VECTOR(39) -+#define ERDY_vect_num 39 -+ -+/* Store Program Memory Ready */ -+#define SPMR_vect _VECTOR(40) -+#define SPMR_vect_num 40 -+ -+/* IDSCAN Full Interrupt */ -+#define IDFULL_vect _VECTOR(41) -+#define IDFULL_vect_num 41 -+ -+#define _VECTORS_SIZE 168 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 64 -+#define FLASHSTART 0x8000 -+#define FLASHEND 0xCFFF -+#define RAMSTART 0x0200 -+#define RAMSIZE 1024 -+#define RAMEND 0x05FF -+#define E2START 0 -+#define E2SIZE 1152 -+#define E2PAGESIZE 16 -+#define E2END 0x047F -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 1 -+ -+/* Fuse Byte */ -+#define FUSE_CKDIV8 (unsigned char)~_BV(128) -+#define FUSE_DWEN (unsigned char)~_BV(64) -+#define FUSE_SPIEN (unsigned char)~_BV(32) -+#define FUSE_WDTON (unsigned char)~_BV(16) -+#define FUSE_EESAVE (unsigned char)~_BV(8) -+#define FUSE_BOOTRST (unsigned char)~_BV(4) -+#define FUSE_RSTDISBL (unsigned char)~_BV(2) -+#define FUSE_EXTCLKEN (unsigned char)~_BV(1) -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x95 -+#define SIGNATURE_2 0x66 -+ -+ -+#endif /* #ifdef _AVR_ATA5783_H_INCLUDED */ -+ -diff --git a/include/avr/ioa5790.h b/include/avr/ioa5790.h -new file mode 100644 -index 0000000..6353a60 ---- /dev/null -+++ b/include/avr/ioa5790.h -@@ -0,0 +1,834 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATA5790_H_INCLUDED -+#define _AVR_ATA5790_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "ioa5790.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x06) -+#define PINC7 7 -+#define PINC6 6 -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x07) -+#define DDRC7 7 -+#define DDRC6 6 -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x08) -+#define PORTC7 7 -+#define PORTC6 6 -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PIND _SFR_IO8(0x09) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0A) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x0B) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+/* Reserved [0x0C] */ -+ -+#define TPCR _SFR_IO8(0x0D) -+#define TPMA 0 -+#define TPMOD 1 -+#define TPMS0 2 -+#define TPMS1 3 -+#define TPMD0 4 -+#define TPMD1 5 -+#define TPPSD 6 -+#define TPD 7 -+ -+#define TPFR _SFR_IO8(0x0E) -+#define TPF 0 -+#define TPA 1 -+#define TPGAP 2 -+#define TPPSW 3 -+ -+#define CMCR _SFR_IO8(0x0F) -+#define CMM0 0 -+#define CMM1 1 -+#define SRCD 2 -+#define CO32D 3 -+#define CCS 4 -+#define ECINS 5 -+#define CMONEN 6 -+#define CMCCE 7 -+ -+#define CMSR _SFR_IO8(0x10) -+#define ECF 0 -+#define SXF 1 -+#define RTCF 2 -+ -+#define T2CR _SFR_IO8(0x11) -+#define T2OTM 0 -+#define T2CTM 1 -+#define T2CRM 2 -+#define T2GRM 3 -+#define T2TOP 4 -+#define T2RES 5 -+#define T2TS 6 -+#define T2E 7 -+ -+#define T3CR _SFR_IO8(0x12) -+#define T3OTM 0 -+#define T3CTM 1 -+#define T3CRM 2 -+#define T3CPRM 3 -+#define T3TOP 4 -+#define T3RES 5 -+#define T3CPTM 6 -+#define T3E 7 -+ -+#define AESCR _SFR_IO8(0x13) -+#define AESWK 0 -+#define AESWD 1 -+#define AESIM 2 -+#define AESD 3 -+#define AESXOR 4 -+#define AESRES 5 -+#define AESE 7 -+ -+#define AESSR _SFR_IO8(0x14) -+#define AESRF 0 -+#define AESERF 7 -+ -+#define TMIFR _SFR_IO8(0x15) -+#define TMRXF 0 -+#define TMTXF 1 -+#define TMTCF 2 -+#define TMRXS 3 -+#define TMTXS 4 -+ -+#define VMSR _SFR_IO8(0x16) -+#define VMF 0 -+ -+#define PCIFR _SFR_IO8(0x17) -+#define PCIF0 0 -+#define PCIF1 1 -+ -+#define LFFR _SFR_IO8(0x18) -+#define LFID0F 0 -+#define LFID1F 1 -+#define LFFEF 2 -+#define LFDBF 3 -+#define LFRSF 4 -+#define LFSDF 5 -+#define LFMDF 6 -+#define LFCAF 7 -+ -+#define T0IFR _SFR_IO8(0x19) -+#define T0F 0 -+ -+#define T1IFR _SFR_IO8(0x1A) -+#define T1F 0 -+ -+#define T2IFR _SFR_IO8(0x1B) -+#define T2OFF 0 -+#define T2COF 1 -+ -+#define T3IFR _SFR_IO8(0x1C) -+#define T3OFF 0 -+#define T3COF 1 -+#define T3ICF 2 -+ -+#define EIFR _SFR_IO8(0x1D) -+#define INTF0 0 -+ -+#define GPIOR _SFR_IO8(0x1E) -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEWE 1 -+#define EEMWE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+#define EELP 6 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define EEPR _SFR_IO8(0x23) -+#define EEAP0 0 -+#define EEAP1 1 -+#define EEAP2 2 -+#define EEAP3 3 -+ -+#define EECCR _SFR_IO8(0x24) -+#define EEL0 0 -+#define EEL1 1 -+#define EEL2 2 -+#define EEL3 3 -+ -+/* Reserved [0x25] */ -+ -+#define PCICR _SFR_IO8(0x26) -+#define PCIE0 0 -+#define PCIE1 1 -+ -+#define EIMSK _SFR_IO8(0x27) -+#define INT0 0 -+ -+#define TMDR _SFR_IO8(0x28) -+ -+#define AESDR _SFR_IO8(0x29) -+ -+#define AESKR _SFR_IO8(0x2A) -+#define AESKR0 0 -+#define AESKR1 1 -+#define AESKR2 2 -+#define AESKR3 3 -+#define AESKR4 4 -+#define AESKR5 5 -+#define AESKR6 6 -+#define AESKR7 7 -+ -+#define VMCR _SFR_IO8(0x2B) -+#define VMLS0 0 -+#define VMLS1 1 -+#define VMLS2 2 -+#define VMLS3 3 -+#define VMIM 4 -+#define VMPS 5 -+#define BODPD 6 -+#define BODLS 7 -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+#define LFCR0 _SFR_IO8(0x2F) -+#define LFCE1 0 -+#define LFCE2 1 -+#define LFCE3 2 -+#define LFBRS 3 -+#define LFRBS 4 -+#define LFMG 5 -+#define LFVC0 6 -+#define LFVC1 7 -+ -+#define LFCR1 _SFR_IO8(0x30) -+#define LFM0 0 -+#define LFM1 1 -+#define LFFM0 2 -+#define LFFM1 3 -+#define LFRMS 4 -+#define LFRMSA 5 -+#define LFQCE 6 -+#define LFRE 7 -+ -+/* Reserved [0x31] */ -+ -+#define LFRDB _SFR_IO8(0x32) -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+#define TPRF 5 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define IVCE 0 -+#define IVSEL 1 -+#define PUD 4 -+ -+#define LFSR _SFR_IO8(0x36) -+#define LFES 0 -+#define LFSD 1 -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define SIGRD 5 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+#define T1CR _SFR_IO8(0x38) -+#define T1PS0 0 -+#define T1PS1 1 -+#define T1IE 2 -+#define T1CS0 3 -+#define T1CS1 4 -+#define T1E 7 -+ -+#define T0CR _SFR_IO8(0x39) -+#define T0PS0 0 -+#define T0PS1 1 -+#define T0PS2 2 -+#define T0IE 3 -+#define T0PR 4 -+ -+/* Reserved [0x3A] */ -+ -+#define CMIMR _SFR_IO8(0x3B) -+#define ECIE 0 -+#define SXIE 1 -+#define RTCIE 2 -+ -+#define CLKPR _SFR_IO8(0x3C) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLTPS0 3 -+#define CLTPS1 4 -+#define CLTPS2 5 -+#define CLKPCE 7 -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCR _SFR_MEM8(0x60) -+#define WDPS0 0 -+#define WDPS1 1 -+#define WDPS2 2 -+#define WDE 3 -+#define WDCE 4 -+ -+/* Reserved [0x61..0x62] */ -+ -+#define PRR0 _SFR_MEM8(0x63) -+#define PRLFR 0 -+#define PRT1 1 -+#define PRT2 2 -+#define PRT3 3 -+#define PRTM 4 -+#define PRCU 5 -+#define PRDS 6 -+#define PRVM 7 -+ -+#define PRR1 _SFR_MEM8(0x64) -+#define PRCI 0 -+#define PRSPI 1 -+ -+#define SRCCAL _SFR_MEM8(0x65) -+ -+#define FRCCAL _SFR_MEM8(0x66) -+ -+/* Reserved [0x67..0x68] */ -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+ -+#define PCMSK0 _SFR_MEM8(0x6A) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6B) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+#define PCINT14 6 -+#define PCINT15 7 -+ -+/* Reserved [0x6C] */ -+ -+#define LDCR _SFR_MEM8(0x6D) -+#define LDE 0 -+#define LDCS0 1 -+#define LDCS1 2 -+ -+/* Reserved [0x6E..0x6F] */ -+ -+#define T2CNT _SFR_MEM8(0x70) -+ -+#define T2COR _SFR_MEM8(0x71) -+ -+/* Reserved [0x72] */ -+ -+#define T2MR _SFR_MEM8(0x73) -+#define T2CS0 0 -+#define T2CS1 1 -+#define T2CS2 2 -+#define T2PS0 3 -+#define T2PS1 4 -+#define T2PS2 5 -+#define T2D0 6 -+#define T2D1 7 -+ -+#define T2IMR _SFR_MEM8(0x74) -+#define T2OIM 0 -+#define T2CIM 1 -+ -+/* Reserved [0x75] */ -+ -+#define T3CNT _SFR_MEM8(0x76) -+ -+#define T3COR _SFR_MEM8(0x77) -+ -+#define T3ICR _SFR_MEM8(0x78) -+ -+#define T3MRA _SFR_MEM8(0x79) -+#define T3CS0 0 -+#define T3CS1 1 -+#define T3SCE 2 -+#define T3CE0 3 -+#define T3CE1 4 -+#define T3CNC 5 -+#define T3ICS0 6 -+#define T3ICS1 7 -+ -+#define T3MRB _SFR_MEM8(0x7A) -+#define T3PS0 0 -+#define T3PS1 1 -+#define T3PS2 2 -+ -+#define T3IMR _SFR_MEM8(0x7B) -+#define T3OIM 0 -+#define T3CIM 1 -+#define T3CPIM 2 -+ -+/* Reserved [0x7C] */ -+ -+#define TMCR _SFR_MEM8(0x7D) -+#define MI1S0 0 -+#define MI1S1 1 -+#define MI2S0 2 -+#define MI2S1 3 -+#define MI4S0 4 -+#define MI4S1 5 -+#define TMCPOL 6 -+#define TMSSIE 7 -+ -+#define TMMR _SFR_MEM8(0x7E) -+#define MOS0 0 -+#define MOS1 1 -+#define MSCS0 2 -+#define MSCS1 3 -+#define MOUTC 4 -+#define TMMS0 5 -+#define TMMS1 6 -+#define TM12S 7 -+ -+#define TMIMR _SFR_MEM8(0x7F) -+#define TMRXIM 0 -+#define TMTXIM 1 -+#define TMTCIM 2 -+ -+/* Reserved [0x80..0x81] */ -+ -+#define LFIMR _SFR_MEM8(0x82) -+#define LFID0IM 0 -+#define LFID1IM 1 -+#define LFFEIM 2 -+#define LFDBIM 3 -+#define LFRSIM 4 -+#define LFSDIM 5 -+#define LFMDIM 6 -+ -+#define LFCAD _SFR_MEM8(0x83) -+ -+#define LFID00 _SFR_MEM8(0x84) -+ -+#define LFID01 _SFR_MEM8(0x85) -+ -+#define LFID02 _SFR_MEM8(0x86) -+ -+#define LFID03 _SFR_MEM8(0x87) -+ -+#define LFID10 _SFR_MEM8(0x88) -+ -+#define LFID11 _SFR_MEM8(0x89) -+ -+#define LFID12 _SFR_MEM8(0x8A) -+ -+#define LFID13 _SFR_MEM8(0x8B) -+ -+#define LFRD0 _SFR_MEM8(0x8C) -+ -+#define LFRD1 _SFR_MEM8(0x8D) -+ -+#define LFRD2 _SFR_MEM8(0x8E) -+ -+#define LFRD3 _SFR_MEM8(0x8F) -+ -+#define LFID0M _SFR_MEM8(0x90) -+#define ID0FS0 0 -+#define ID0FS1 1 -+#define ID0FS2 2 -+#define ID0FS3 3 -+#define ID0FS4 4 -+#define ID0E 7 -+ -+#define LFID1M _SFR_MEM8(0x91) -+#define ID1FS0 0 -+#define ID1FS1 1 -+#define ID1FS2 2 -+#define ID1FS3 3 -+#define ID1FS4 4 -+#define ID1E 7 -+ -+#define LFRDF _SFR_MEM8(0x92) -+#define RDFS0 0 -+#define RDFS1 1 -+#define RDFS2 2 -+#define RDFS3 3 -+#define RDFS4 4 -+#define RDFE 7 -+ -+#define LFRSD1 _SFR_MEM8(0x93) -+ -+#define LFRSD2 _SFR_MEM8(0x94) -+ -+#define LFRSD3 _SFR_MEM8(0x95) -+ -+#define LFCC1 _SFR_MEM8(0x96) -+ -+#define LFCC2 _SFR_MEM8(0x97) -+ -+#define LFCC3 _SFR_MEM8(0x98) -+ -+/* Reserved [0x99..0x9B] */ -+ -+#define TPIMR _SFR_MEM8(0x9C) -+#define TPIM 0 -+ -+/* Reserved [0x9D] */ -+ -+#define RTCCR _SFR_MEM8(0x9E) -+#define RTCR 0 -+ -+#define RTCDR _SFR_MEM8(0x9F) -+ -+/* Reserved [0xA0..0xA7] */ -+ -+#define TMMDR _SFR_MEM8(0xA8) -+ -+#define TMBDR _SFR_MEM8(0xA9) -+ -+#define TMTDR _SFR_MEM8(0xAA) -+ -+#define TMSR _SFR_MEM8(0xAB) -+ -+/* Reserved [0xAC] */ -+ -+#define CRCDR _SFR_MEM8(0xAD) -+ -+#define CRCCR _SFR_MEM8(0xAE) -+#define CRCN0 0 -+#define CRCN1 1 -+#define CRCN2 2 -+#define CRCSEL 3 -+#define REFLI 4 -+#define REFLO 5 -+#define CRCRS 7 -+ -+#define CRCSR _SFR_MEM8(0xAF) -+#define CRCBF 0 -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* Transponder Mode Interrupt */ -+#define TPINT_vect _VECTOR(1) -+#define TPINT_vect_num 1 -+ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(2) -+#define INT0_vect_num 2 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(3) -+#define PCINT0_vect_num 3 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(4) -+#define PCINT1_vect_num 4 -+ -+/* Voltage Monitoring Interrupt */ -+#define VMINT_vect _VECTOR(5) -+#define VMINT_vect_num 5 -+ -+/* Timer0 Interval Interrupt */ -+#define T0INT_vect _VECTOR(6) -+#define T0INT_vect_num 6 -+ -+/* LF-Receiver Identifier 0 Interrupt */ -+#define LFID0INT_vect _VECTOR(7) -+#define LFID0INT_vect_num 7 -+ -+/* LF-Receiver Identifier 1 Interrupt */ -+#define LFID1INT_vect _VECTOR(8) -+#define LFID1INT_vect_num 8 -+ -+/* LF-Receiver Frame End Interrupt */ -+#define LFFEINT_vect _VECTOR(9) -+#define LFFEINT_vect_num 9 -+ -+/* LF-Receiver Data Buffer full Interrupt */ -+#define LFDBINT_vect _VECTOR(10) -+#define LFDBINT_vect_num 10 -+ -+/* Timer/Counter3 Capture Event Interrupt */ -+#define T3CAPINT_vect _VECTOR(11) -+#define T3CAPINT_vect_num 11 -+ -+/* Timer/Counter3 Compare Match Interrupt */ -+#define T3COMINT_vect _VECTOR(12) -+#define T3COMINT_vect_num 12 -+ -+/* Timer/Counter3 Overflow Interrupt */ -+#define T3OVFINT_vect _VECTOR(13) -+#define T3OVFINT_vect_num 13 -+ -+/* Timer/Counter2 Compare Match Interrupt */ -+#define T2COMINT_vect _VECTOR(14) -+#define T2COMINT_vect_num 14 -+ -+/* Timer/Counter2 Overflow Interrupt */ -+#define T2OVFINT_vect _VECTOR(15) -+#define T2OVFINT_vect_num 15 -+ -+/* Timer 1 Interval Interrupt */ -+#define T1INT_vect _VECTOR(16) -+#define T1INT_vect_num 16 -+ -+/* SPI Serial Transfer Complete Interrupt */ -+#define SPISTC_vect _VECTOR(17) -+#define SPISTC_vect_num 17 -+ -+/* Timer Modulator SSI Receive Buffer Interrupt */ -+#define TMRXBINT_vect _VECTOR(18) -+#define TMRXBINT_vect_num 18 -+ -+/* Timer Modulator SSI Transmit Buffer Interrupt */ -+#define TMTXBINT_vect _VECTOR(19) -+#define TMTXBINT_vect_num 19 -+ -+/* Timer Modulator Transmit Complete Interrupt */ -+#define TMTXCINT_vect _VECTOR(20) -+#define TMTXCINT_vect_num 20 -+ -+/* AES Interrupt */ -+#define AESINT_vect _VECTOR(21) -+#define AESINT_vect_num 21 -+ -+/* LF-Receiver RSSi measurement Interrupt */ -+#define LFRSSINT_vect _VECTOR(22) -+#define LFRSSINT_vect_num 22 -+ -+/* LF-Receiver Signal Detect Interrupt */ -+#define LFSDINT_vect _VECTOR(23) -+#define LFSDINT_vect_num 23 -+ -+/* LF-Receiver Manchester Decoder error Interrupt */ -+#define LFMDINT_vect _VECTOR(24) -+#define LFMDINT_vect_num 24 -+ -+/* External Input Clock Monitoring Interrupt */ -+#define EXCMINT_vect _VECTOR(25) -+#define EXCMINT_vect_num 25 -+ -+/* External XTAL Oscillator Break Down Interrupt */ -+#define EXXMINT_vect _VECTOR(26) -+#define EXXMINT_vect_num 26 -+ -+/* Real Time Clock Interrupt */ -+#define RTCINT_vect _VECTOR(27) -+#define RTCINT_vect_num 27 -+ -+/* EEPROM Ready Interrupt */ -+#define EEREADY_vect _VECTOR(28) -+#define EEREADY_vect_num 28 -+ -+/* Store Program Memory Ready */ -+#define SPMREADY_vect _VECTOR(29) -+#define SPMREADY_vect_num 29 -+ -+#define _VECTORS_SIZE 120 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 128 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x3FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 512 -+#define RAMEND 0x02FF -+#define E2START 0 -+#define E2SIZE 2048 -+#define E2PAGESIZE 16 -+#define E2END 0x07FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 1 -+ -+/* Fuse Byte */ -+#define FUSE_CKDIV8 (unsigned char)~_BV(128) -+#define FUSE_DWEN (unsigned char)~_BV(64) -+#define FUSE_SPIEN (unsigned char)~_BV(32) -+#define FUSE_WDTON (unsigned char)~_BV(16) -+#define FUSE_EESAVE (unsigned char)~_BV(8) -+#define FUSE_Reserved (unsigned char)~_BV(4) -+#define FUSE__32OEN (unsigned char)~_BV(2) -+#define FUSE_EXTCLKEN (unsigned char)~_BV(1) -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x94 -+#define SIGNATURE_2 0x61 -+ -+ -+#endif /* #ifdef _AVR_ATA5790_H_INCLUDED */ -+ -diff --git a/include/avr/ioa5790n.h b/include/avr/ioa5790n.h -new file mode 100644 -index 0000000..9958b42 ---- /dev/null -+++ b/include/avr/ioa5790n.h -@@ -0,0 +1,850 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATA5790N_H_INCLUDED -+#define _AVR_ATA5790N_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "ioa5790n.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x06) -+#define PINC7 7 -+#define PINC6 6 -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x07) -+#define DDRC7 7 -+#define DDRC6 6 -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x08) -+#define PORTC7 7 -+#define PORTC6 6 -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PIND _SFR_IO8(0x09) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0A) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x0B) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+#define T3CR2 _SFR_IO8(0x0C) -+#define T3GRES 0 -+#define T3C2TM 1 -+#define T3C2RM 2 -+ -+#define TPCR _SFR_IO8(0x0D) -+#define TPMA 0 -+#define TPMOD 1 -+#define TPMS0 2 -+#define TPMS1 3 -+#define TPMD0 4 -+#define TPMD1 5 -+#define TPPSD 6 -+#define TPD 7 -+ -+#define TPFR _SFR_IO8(0x0E) -+#define TPF 0 -+#define TPA 1 -+#define TPGAP 2 -+#define TPPSW 3 -+ -+#define CMCR _SFR_IO8(0x0F) -+#define CMM0 0 -+#define CMM1 1 -+#define SRCD 2 -+#define CO32D 3 -+#define CCS 4 -+#define ECINS 5 -+#define CMONEN 6 -+#define CMCCE 7 -+ -+#define CMSR _SFR_IO8(0x10) -+#define ECF 0 -+#define SXF 1 -+#define RTCF 2 -+ -+#define T2CR _SFR_IO8(0x11) -+#define T2OTM 0 -+#define T2CTM 1 -+#define T2CRM 2 -+#define T2GRM 3 -+#define T2TOP 4 -+#define T2RES 5 -+#define T2TS 6 -+#define T2E 7 -+ -+#define T3CR _SFR_IO8(0x12) -+#define T3OTM 0 -+#define T3CTM 1 -+#define T3CRM 2 -+#define T3CPRM 3 -+#define T3TOP 4 -+#define T3RES 5 -+#define T3CPTM 6 -+#define T3E 7 -+ -+#define AESCR _SFR_IO8(0x13) -+#define AESWK 0 -+#define AESWD 1 -+#define AESIM 2 -+#define AESD 3 -+#define AESXOR 4 -+#define AESRES 5 -+#define AESE 7 -+ -+#define AESSR _SFR_IO8(0x14) -+#define AESRF 0 -+#define AESERF 7 -+ -+#define TMIFR _SFR_IO8(0x15) -+#define TMRXF 0 -+#define TMTXF 1 -+#define TMTCF 2 -+#define TMRXS 3 -+#define TMTXS 4 -+ -+#define VMSR _SFR_IO8(0x16) -+#define VMF 0 -+ -+#define PCIFR _SFR_IO8(0x17) -+#define PCIF0 0 -+#define PCIF1 1 -+ -+#define LFFR _SFR_IO8(0x18) -+#define LFID0F 0 -+#define LFID1F 1 -+#define LFFEF 2 -+#define LFDBF 3 -+#define LFRSF 4 -+#define LFSDF 5 -+#define LFMDF 6 -+#define LFCAF 7 -+ -+#define T0IFR _SFR_IO8(0x19) -+#define T0F 0 -+ -+#define T1IFR _SFR_IO8(0x1A) -+#define T1F 0 -+ -+#define T2IFR _SFR_IO8(0x1B) -+#define T2OFF 0 -+#define T2COF 1 -+ -+#define T3IFR _SFR_IO8(0x1C) -+#define T3OFF 0 -+#define T3COF 1 -+#define T3ICF 2 -+#define T3CO2F 3 -+ -+#define EIFR _SFR_IO8(0x1D) -+#define INTF0 0 -+ -+#define GPIOR _SFR_IO8(0x1E) -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEWE 1 -+#define EEMWE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+#define EELP 6 -+#define NVMBSY 7 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define EEPR _SFR_IO8(0x23) -+#define EEAP0 0 -+#define EEAP1 1 -+#define EEAP2 2 -+#define EEAP3 3 -+ -+#define EECCR _SFR_IO8(0x24) -+#define EEL0 0 -+#define EEL1 1 -+#define EEL2 2 -+#define EEL3 3 -+ -+#define EECR2 _SFR_IO8(0x25) -+#define EEBRE 0 -+#define EEPAGE 1 -+ -+#define PCICR _SFR_IO8(0x26) -+#define PCIE0 0 -+#define PCIE1 1 -+ -+#define EIMSK _SFR_IO8(0x27) -+#define INT0 0 -+ -+#define TMDR _SFR_IO8(0x28) -+ -+#define AESDR _SFR_IO8(0x29) -+ -+#define AESKR _SFR_IO8(0x2A) -+#define AESKR0 0 -+#define AESKR1 1 -+#define AESKR2 2 -+#define AESKR3 3 -+#define AESKR4 4 -+#define AESKR5 5 -+#define AESKR6 6 -+#define AESKR7 7 -+ -+#define VMCR _SFR_IO8(0x2B) -+#define VMLS0 0 -+#define VMLS1 1 -+#define VMLS2 2 -+#define VMLS3 3 -+#define VMIM 4 -+#define VMPS 5 -+#define BODPD 6 -+#define BODLS 7 -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+#define LFCR0 _SFR_IO8(0x2F) -+#define LFCE1 0 -+#define LFCE2 1 -+#define LFCE3 2 -+#define LFBRS 3 -+#define LFRBS 4 -+#define LFMG 5 -+#define LFVC0 6 -+#define LFVC1 7 -+ -+#define LFCR1 _SFR_IO8(0x30) -+#define LFM0 0 -+#define LFM1 1 -+#define LFFM0 2 -+#define LFFM1 3 -+#define LFRMS 4 -+#define LFRMSA 5 -+#define LFQCE 6 -+#define LFRE 7 -+ -+/* Reserved [0x31] */ -+ -+#define LFRDB _SFR_IO8(0x32) -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+#define TPRF 5 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define IVCE 0 -+#define IVSEL 1 -+#define PUD 4 -+ -+#define LFSR _SFR_IO8(0x36) -+#define LFES 0 -+#define LFSD 1 -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define SIGRD 5 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+#define T1CR _SFR_IO8(0x38) -+#define T1PS0 0 -+#define T1PS1 1 -+#define T1IE 2 -+#define T1CS0 3 -+#define T1CS1 4 -+#define T1E 7 -+ -+#define T0CR _SFR_IO8(0x39) -+#define T0PS0 0 -+#define T0PS1 1 -+#define T0PS2 2 -+#define T0IE 3 -+#define T0PR 4 -+ -+/* Reserved [0x3A] */ -+ -+#define CMIMR _SFR_IO8(0x3B) -+#define ECIE 0 -+#define SXIE 1 -+#define RTCIE 2 -+ -+#define CLKPR _SFR_IO8(0x3C) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLTPS0 3 -+#define CLTPS1 4 -+#define CLTPS2 5 -+#define CLKPCE 7 -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCR _SFR_MEM8(0x60) -+#define WDPS0 0 -+#define WDPS1 1 -+#define WDPS2 2 -+#define WDE 3 -+#define WDCE 4 -+ -+/* Reserved [0x61..0x62] */ -+ -+#define PRR0 _SFR_MEM8(0x63) -+#define PRLFR 0 -+#define PRT1 1 -+#define PRT2 2 -+#define PRT3 3 -+#define PRTM 4 -+#define PRCU 5 -+#define PRDS 6 -+#define PRVM 7 -+ -+#define PRR1 _SFR_MEM8(0x64) -+#define PRCI 0 -+#define PRSPI 1 -+ -+#define SRCCAL _SFR_MEM8(0x65) -+ -+#define FRCCAL _SFR_MEM8(0x66) -+ -+/* Reserved [0x67..0x68] */ -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+ -+#define PCMSK0 _SFR_MEM8(0x6A) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6B) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+#define PCINT14 6 -+#define PCINT15 7 -+ -+/* Reserved [0x6C] */ -+ -+#define LDCR _SFR_MEM8(0x6D) -+#define LDE 0 -+#define LDCS0 1 -+#define LDCS1 2 -+ -+/* Reserved [0x6E..0x6F] */ -+ -+#define T2CNT _SFR_MEM8(0x70) -+ -+#define T2COR _SFR_MEM8(0x71) -+ -+/* Reserved [0x72] */ -+ -+#define T2MR _SFR_MEM8(0x73) -+#define T2CS0 0 -+#define T2CS1 1 -+#define T2CS2 2 -+#define T2PS0 3 -+#define T2PS1 4 -+#define T2PS2 5 -+#define T2D0 6 -+#define T2D1 7 -+ -+#define T2IMR _SFR_MEM8(0x74) -+#define T2OIM 0 -+#define T2CIM 1 -+ -+#define T3CO2R _SFR_MEM8(0x75) -+ -+#define T3CNT _SFR_MEM8(0x76) -+ -+#define T3COR _SFR_MEM8(0x77) -+ -+#define T3ICR _SFR_MEM8(0x78) -+ -+#define T3MRA _SFR_MEM8(0x79) -+#define T3CS0 0 -+#define T3CS1 1 -+#define T3SCE 2 -+#define T3CE0 3 -+#define T3CE1 4 -+#define T3CNC 5 -+#define T3ICS0 6 -+#define T3ICS1 7 -+ -+#define T3MRB _SFR_MEM8(0x7A) -+#define T3PS0 0 -+#define T3PS1 1 -+#define T3PS2 2 -+ -+#define T3IMR _SFR_MEM8(0x7B) -+#define T3OIM 0 -+#define T3CIM 1 -+#define T3CPIM 2 -+#define T3C2IM 3 -+ -+/* Reserved [0x7C] */ -+ -+#define TMCR _SFR_MEM8(0x7D) -+#define MI1S0 0 -+#define MI1S1 1 -+#define MI2S0 2 -+#define MI2S1 3 -+#define MI4S0 4 -+#define MI4S1 5 -+#define TMCPOL 6 -+#define TMSSIE 7 -+ -+#define TMMR _SFR_MEM8(0x7E) -+#define MOS0 0 -+#define MOS1 1 -+#define MSCS0 2 -+#define MSCS1 3 -+#define MOUTC 4 -+#define TMMS0 5 -+#define TMMS1 6 -+#define TM12S 7 -+ -+#define TMIMR _SFR_MEM8(0x7F) -+#define TMRXIM 0 -+#define TMTXIM 1 -+#define TMTCIM 2 -+ -+/* Reserved [0x80..0x81] */ -+ -+#define LFIMR _SFR_MEM8(0x82) -+#define LFID0IM 0 -+#define LFID1IM 1 -+#define LFFEIM 2 -+#define LFDBIM 3 -+#define LFRSIM 4 -+#define LFSDIM 5 -+#define LFMDIM 6 -+ -+#define LFCAD _SFR_MEM8(0x83) -+ -+#define LFID00 _SFR_MEM8(0x84) -+ -+#define LFID01 _SFR_MEM8(0x85) -+ -+#define LFID02 _SFR_MEM8(0x86) -+ -+#define LFID03 _SFR_MEM8(0x87) -+ -+#define LFID10 _SFR_MEM8(0x88) -+ -+#define LFID11 _SFR_MEM8(0x89) -+ -+#define LFID12 _SFR_MEM8(0x8A) -+ -+#define LFID13 _SFR_MEM8(0x8B) -+ -+#define LFRD0 _SFR_MEM8(0x8C) -+ -+#define LFRD1 _SFR_MEM8(0x8D) -+ -+#define LFRD2 _SFR_MEM8(0x8E) -+ -+#define LFRD3 _SFR_MEM8(0x8F) -+ -+#define LFID0M _SFR_MEM8(0x90) -+#define ID0FS0 0 -+#define ID0FS1 1 -+#define ID0FS2 2 -+#define ID0FS3 3 -+#define ID0FS4 4 -+#define ID0E 7 -+ -+#define LFID1M _SFR_MEM8(0x91) -+#define ID1FS0 0 -+#define ID1FS1 1 -+#define ID1FS2 2 -+#define ID1FS3 3 -+#define ID1FS4 4 -+#define ID1E 7 -+ -+#define LFRDF _SFR_MEM8(0x92) -+#define RDFS0 0 -+#define RDFS1 1 -+#define RDFS2 2 -+#define RDFS3 3 -+#define RDFS4 4 -+#define RDFE 7 -+ -+#define LFRSD1 _SFR_MEM8(0x93) -+ -+#define LFRSD2 _SFR_MEM8(0x94) -+ -+#define LFRSD3 _SFR_MEM8(0x95) -+ -+#define LFCC1 _SFR_MEM8(0x96) -+ -+#define LFCC2 _SFR_MEM8(0x97) -+ -+#define LFCC3 _SFR_MEM8(0x98) -+ -+#define LFQCR _SFR_MEM8(0x99) -+#define LFQCLL 0 -+ -+/* Reserved [0x9A..0x9B] */ -+ -+#define TPIMR _SFR_MEM8(0x9C) -+#define TPIM 0 -+ -+/* Reserved [0x9D] */ -+ -+#define RTCCR _SFR_MEM8(0x9E) -+#define RTCR 0 -+ -+#define RTCDR _SFR_MEM8(0x9F) -+ -+/* Reserved [0xA0..0xA7] */ -+ -+#define TMMDR _SFR_MEM8(0xA8) -+ -+#define TMBDR _SFR_MEM8(0xA9) -+ -+#define TMTDR _SFR_MEM8(0xAA) -+ -+#define TMSR _SFR_MEM8(0xAB) -+ -+#define CRCPOL _SFR_MEM8(0xAC) -+ -+#define CRCDR _SFR_MEM8(0xAD) -+ -+#define CRCCR _SFR_MEM8(0xAE) -+#define CRCN0 0 -+#define CRCN1 1 -+#define CRCN2 2 -+#define CRCSEL 3 -+#define REFLI 4 -+#define REFLO 5 -+#define STVAL 6 -+#define CRCRS 7 -+ -+#define CRCSR _SFR_MEM8(0xAF) -+#define CRCBF 0 -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* Transponder Mode Interrupt */ -+#define TPINT_vect _VECTOR(1) -+#define TPINT_vect_num 1 -+ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(2) -+#define INT0_vect_num 2 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(3) -+#define PCINT0_vect_num 3 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(4) -+#define PCINT1_vect_num 4 -+ -+/* Voltage Monitoring Interrupt */ -+#define VMINT_vect _VECTOR(5) -+#define VMINT_vect_num 5 -+ -+/* Timer0 Interval Interrupt */ -+#define T0INT_vect _VECTOR(6) -+#define T0INT_vect_num 6 -+ -+/* LF-Receiver Identifier 0 Interrupt */ -+#define LFID0INT_vect _VECTOR(7) -+#define LFID0INT_vect_num 7 -+ -+/* LF-Receiver Identifier 1 Interrupt */ -+#define LFID1INT_vect _VECTOR(8) -+#define LFID1INT_vect_num 8 -+ -+/* LF-Receiver Frame End Interrupt */ -+#define LFFEINT_vect _VECTOR(9) -+#define LFFEINT_vect_num 9 -+ -+/* LF-Receiver Data Buffer full Interrupt */ -+#define LFDBINT_vect _VECTOR(10) -+#define LFDBINT_vect_num 10 -+ -+/* Timer/Counter3 Capture Event Interrupt */ -+#define T3CAPINT_vect _VECTOR(11) -+#define T3CAPINT_vect_num 11 -+ -+/* Timer/Counter3 Compare Match Interrupt */ -+#define T3COMINT_vect _VECTOR(12) -+#define T3COMINT_vect_num 12 -+ -+/* Timer/Counter3 Overflow Interrupt */ -+#define T3OVFINT_vect _VECTOR(13) -+#define T3OVFINT_vect_num 13 -+ -+/* Timer/Counter3 Compare Match 2 Interrupt */ -+#define T3COM2INT_vect _VECTOR(14) -+#define T3COM2INT_vect_num 14 -+ -+/* Timer/Counter2 Compare Match Interrupt */ -+#define T2COMINT_vect _VECTOR(15) -+#define T2COMINT_vect_num 15 -+ -+/* Timer/Counter2 Overflow Interrupt */ -+#define T2OVFINT_vect _VECTOR(16) -+#define T2OVFINT_vect_num 16 -+ -+/* Timer 1 Interval Interrupt */ -+#define T1INT_vect _VECTOR(17) -+#define T1INT_vect_num 17 -+ -+/* SPI Serial Transfer Complete Interrupt */ -+#define SPISTC_vect _VECTOR(18) -+#define SPISTC_vect_num 18 -+ -+/* Timer Modulator SSI Receive Buffer Interrupt */ -+#define TMRXBINT_vect _VECTOR(19) -+#define TMRXBINT_vect_num 19 -+ -+/* Timer Modulator SSI Transmit Buffer Interrupt */ -+#define TMTXBINT_vect _VECTOR(20) -+#define TMTXBINT_vect_num 20 -+ -+/* Timer Modulator Transmit Complete Interrupt */ -+#define TMTXCINT_vect _VECTOR(21) -+#define TMTXCINT_vect_num 21 -+ -+/* AES Interrupt */ -+#define AESINT_vect _VECTOR(22) -+#define AESINT_vect_num 22 -+ -+/* LF-Receiver RSSi measurement Interrupt */ -+#define LFRSSINT_vect _VECTOR(23) -+#define LFRSSINT_vect_num 23 -+ -+/* LF-Receiver Signal Detect Interrupt */ -+#define LFSDINT_vect _VECTOR(24) -+#define LFSDINT_vect_num 24 -+ -+/* LF-Receiver Manchester Decoder error Interrupt */ -+#define LFMDINT_vect _VECTOR(25) -+#define LFMDINT_vect_num 25 -+ -+/* External Input Clock Monitoring Interrupt */ -+#define EXCMINT_vect _VECTOR(26) -+#define EXCMINT_vect_num 26 -+ -+/* External XTAL Oscillator Break Down Interrupt */ -+#define EXXMINT_vect _VECTOR(27) -+#define EXXMINT_vect_num 27 -+ -+/* Real Time Clock Interrupt */ -+#define RTCINT_vect _VECTOR(28) -+#define RTCINT_vect_num 28 -+ -+/* EEPROM Ready Interrupt */ -+#define EEREADY_vect _VECTOR(29) -+#define EEREADY_vect_num 29 -+ -+/* Store Program Memory Ready */ -+#define SPMREADY_vect _VECTOR(30) -+#define SPMREADY_vect_num 30 -+ -+#define _VECTORS_SIZE 124 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 128 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x3FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 512 -+#define RAMEND 0x02FF -+#define E2START 0 -+#define E2SIZE 2048 -+#define E2PAGESIZE 16 -+#define E2END 0x07FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 1 -+ -+/* Fuse Byte */ -+#define FUSE_CKDIV8 (unsigned char)~_BV(128) -+#define FUSE_DWEN (unsigned char)~_BV(64) -+#define FUSE_SPIEN (unsigned char)~_BV(32) -+#define FUSE_WDTON (unsigned char)~_BV(16) -+#define FUSE_EESAVE (unsigned char)~_BV(8) -+#define FUSE_Reserved (unsigned char)~_BV(4) -+#define FUSE__32OEN (unsigned char)~_BV(2) -+#define FUSE_EXTCLKEN (unsigned char)~_BV(1) -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x94 -+#define SIGNATURE_2 0x62 -+ -+ -+#endif /* #ifdef _AVR_ATA5790N_H_INCLUDED */ -+ -diff --git a/include/avr/ioa5795.h b/include/avr/ioa5795.h -new file mode 100644 -index 0000000..949ff7f ---- /dev/null -+++ b/include/avr/ioa5795.h -@@ -0,0 +1,691 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATA5795_H_INCLUDED -+#define _AVR_ATA5795_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "ioa5795.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x06) -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x07) -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x08) -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PIND _SFR_IO8(0x09) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0A) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x0B) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+/* Reserved [0x0C] */ -+ -+#define TPCR _SFR_IO8(0x0D) -+#define TPMA 0 -+#define TPMOD 1 -+#define TPMS0 2 -+#define TPMS1 3 -+#define TPMD0 4 -+#define TPMD1 5 -+#define TPPSD 6 -+#define TPD 7 -+ -+#define TPFR _SFR_IO8(0x0E) -+#define TPF 0 -+#define TPA 1 -+#define TPGAP 2 -+#define TPPSW 3 -+ -+#define CMCR _SFR_IO8(0x0F) -+#define CMM0 0 -+#define CMM1 1 -+#define SRCD 2 -+#define CO32D 3 -+#define CCS 4 -+#define ECINS 5 -+#define CMONEN 6 -+#define CMCCE 7 -+ -+#define CMSR _SFR_IO8(0x10) -+#define ECF 0 -+#define SXF 1 -+#define RTCF 2 -+ -+#define T2CR _SFR_IO8(0x11) -+#define T2OTM 0 -+#define T2CTM 1 -+#define T2CRM 2 -+#define T2GRM 3 -+#define T2TOP 4 -+#define T2RES 5 -+#define T2TS 6 -+#define T2E 7 -+ -+#define T3CR _SFR_IO8(0x12) -+#define T3OTM 0 -+#define T3CTM 1 -+#define T3CRM 2 -+#define T3CPRM 3 -+#define T3TOP 4 -+#define T3RES 5 -+#define T3CPTM 6 -+#define T3E 7 -+ -+#define AESCR _SFR_IO8(0x13) -+#define AESWK 0 -+#define AESWD 1 -+#define AESIM 2 -+#define AESD 3 -+#define AESXOR 4 -+#define AESRES 5 -+#define AESE 7 -+ -+#define AESSR _SFR_IO8(0x14) -+#define AESRF 0 -+#define AESERF 7 -+ -+#define TMIFR _SFR_IO8(0x15) -+#define TMRXF 0 -+#define TMTXF 1 -+#define TMTCF 2 -+#define TMRXS 3 -+#define TMTXS 4 -+ -+#define VMSR _SFR_IO8(0x16) -+#define VMF 0 -+ -+#define PCIFR _SFR_IO8(0x17) -+#define PCIF0 0 -+#define PCIF1 1 -+ -+/* Reserved [0x18] */ -+ -+#define T0IFR _SFR_IO8(0x19) -+#define T0F 0 -+ -+#define T1IFR _SFR_IO8(0x1A) -+#define T1F 0 -+ -+#define T2IFR _SFR_IO8(0x1B) -+#define T2OFF 0 -+#define T2COF 1 -+ -+#define T3IFR _SFR_IO8(0x1C) -+#define T3OFF 0 -+#define T3COF 1 -+#define T3ICF 2 -+ -+#define EIFR _SFR_IO8(0x1D) -+#define INTF0 0 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEWE 1 -+#define EEMWE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+#define EELP 6 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define EEPR _SFR_IO8(0x23) -+#define EEAP0 0 -+#define EEAP1 1 -+#define EEAP2 2 -+#define EEAP3 3 -+ -+#define EECCR _SFR_IO8(0x24) -+#define EEL0 0 -+#define EEL1 1 -+#define EEL2 2 -+#define EEL3 3 -+ -+/* Reserved [0x25] */ -+ -+#define PCICR _SFR_IO8(0x26) -+#define PCIE0 0 -+#define PCIE1 1 -+ -+#define EIMSK _SFR_IO8(0x27) -+#define INT0 0 -+ -+#define TMDR _SFR_IO8(0x28) -+ -+#define AESDR _SFR_IO8(0x29) -+ -+#define AESKR _SFR_IO8(0x2A) -+#define AESKR0 0 -+#define AESKR1 1 -+#define AESKR2 2 -+#define AESKR3 3 -+#define AESKR4 4 -+#define AESKR5 5 -+#define AESKR6 6 -+#define AESKR7 7 -+ -+#define VMCR _SFR_IO8(0x2B) -+#define VMLS0 0 -+#define VMLS1 1 -+#define VMLS2 2 -+#define VMLS3 3 -+#define VMIM 4 -+#define VMPS 5 -+#define BODPD 6 -+#define BODLS 7 -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+/* Reserved [0x2F..0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+#define TPRF 5 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define IVCE 0 -+#define IVSEL 1 -+#define PUD 4 -+ -+/* Reserved [0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define SIGRD 5 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+#define T1CR _SFR_IO8(0x38) -+#define T1PS0 0 -+#define T1PS1 1 -+#define T1IE 2 -+#define T1CS0 3 -+#define T1CS1 4 -+#define T1E 7 -+ -+#define T0CR _SFR_IO8(0x39) -+#define T0PS0 0 -+#define T0PS1 1 -+#define T0PS2 2 -+#define T0IE 3 -+#define T0PR 4 -+ -+/* Reserved [0x3A] */ -+ -+#define CMIMR _SFR_IO8(0x3B) -+#define ECIE 0 -+#define SXIE 1 -+#define RTCIE 2 -+ -+#define CLKPR _SFR_IO8(0x3C) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLTPS0 3 -+#define CLTPS1 4 -+#define CLTPS2 5 -+#define CLKPCE 7 -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCR _SFR_MEM8(0x60) -+#define WDPS0 0 -+#define WDPS1 1 -+#define WDPS2 2 -+#define WDE 3 -+#define WDCE 4 -+ -+/* Reserved [0x61..0x62] */ -+ -+#define PRR0 _SFR_MEM8(0x63) -+#define PRT1 1 -+#define PRT2 2 -+#define PRT3 3 -+#define PRTM 4 -+#define PRCU 5 -+#define PRDS 6 -+#define PRVM 7 -+ -+#define PRR1 _SFR_MEM8(0x64) -+#define PRCI 0 -+#define PRSPI 1 -+ -+#define SRCCAL _SFR_MEM8(0x65) -+ -+#define FRCCAL _SFR_MEM8(0x66) -+ -+/* Reserved [0x67..0x68] */ -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+ -+#define PCMSK0 _SFR_MEM8(0x6A) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6B) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+#define PCINT14 6 -+#define PCINT15 7 -+ -+/* Reserved [0x6C] */ -+ -+#define LDCR _SFR_MEM8(0x6D) -+#define LDE 0 -+#define LDCS0 1 -+#define LDCS1 2 -+ -+/* Reserved [0x6E..0x6F] */ -+ -+#define T2CNT _SFR_MEM8(0x70) -+ -+#define T2COR _SFR_MEM8(0x71) -+ -+/* Reserved [0x72] */ -+ -+#define T2MR _SFR_MEM8(0x73) -+#define T2CS0 0 -+#define T2CS1 1 -+#define T2CS2 2 -+#define T2PS0 3 -+#define T2PS1 4 -+#define T2PS2 5 -+#define T2D0 6 -+#define T2D1 7 -+ -+#define T2IMR _SFR_MEM8(0x74) -+#define T2OIM 0 -+#define T2CIM 1 -+ -+/* Reserved [0x75] */ -+ -+#define T3CNT _SFR_MEM8(0x76) -+ -+#define T3COR _SFR_MEM8(0x77) -+ -+#define T3ICR _SFR_MEM8(0x78) -+ -+#define T3MRA _SFR_MEM8(0x79) -+#define T3CS0 0 -+#define T3CS1 1 -+#define T3SCE 2 -+#define T3CE0 3 -+#define T3CE1 4 -+#define T3CNC 5 -+#define T3ICS0 6 -+#define T3ICS1 7 -+ -+#define T3MRB _SFR_MEM8(0x7A) -+#define T3PS0 0 -+#define T3PS1 1 -+#define T3PS2 2 -+ -+#define T3IMR _SFR_MEM8(0x7B) -+#define T3OIM 0 -+#define T3CIM 1 -+#define T3CPIM 2 -+ -+/* Reserved [0x7C] */ -+ -+#define TMCR _SFR_MEM8(0x7D) -+#define MI1S0 0 -+#define MI1S1 1 -+#define MI2S0 2 -+#define MI2S1 3 -+#define MI4S0 4 -+#define MI4S1 5 -+#define TMCPOL 6 -+#define TMSSIE 7 -+ -+#define TMMR _SFR_MEM8(0x7E) -+#define MOS0 0 -+#define MOS1 1 -+#define MSCS0 2 -+#define MSCS1 3 -+#define MOUTC 4 -+#define TMMS0 5 -+#define TMMS1 6 -+#define TM12S 7 -+ -+#define TMIMR _SFR_MEM8(0x7F) -+#define TMRXIM 0 -+#define TMTXIM 1 -+#define TMTCIM 2 -+ -+/* Reserved [0x80..0x9B] */ -+ -+#define TPIMR _SFR_MEM8(0x9C) -+#define TPIM 0 -+ -+/* Reserved [0x9D] */ -+ -+#define RTCCR _SFR_MEM8(0x9E) -+#define RTCR 0 -+ -+#define RTCDR _SFR_MEM8(0x9F) -+ -+/* Reserved [0xA0..0xA7] */ -+ -+#define TMMDR _SFR_MEM8(0xA8) -+ -+#define TMBDR _SFR_MEM8(0xA9) -+ -+#define TMTDR _SFR_MEM8(0xAA) -+ -+#define TMSR _SFR_MEM8(0xAB) -+ -+/* Reserved [0xAC] */ -+ -+#define CRCDR _SFR_MEM8(0xAD) -+ -+#define CRCCR _SFR_MEM8(0xAE) -+#define CRCN0 0 -+#define CRCN1 1 -+#define CRCN2 2 -+#define CRCSEL 3 -+#define REFLI 4 -+#define REFLO 5 -+#define CRCRS 7 -+ -+#define CRCSR _SFR_MEM8(0xAF) -+#define CRCBF 0 -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* Transponder Mode Interrupt */ -+#define TPINT_vect _VECTOR(2) -+#define TPINT_vect_num 2 -+ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(4) -+#define INT0_vect_num 4 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(6) -+#define PCINT0_vect_num 6 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(8) -+#define PCINT1_vect_num 8 -+ -+/* Voltage Monitor Interrupt */ -+#define VMINT_vect _VECTOR(10) -+#define VMINT_vect_num 10 -+ -+/* Timer0 Interval Interrupt */ -+#define T0INT_vect _VECTOR(12) -+#define T0INT_vect_num 12 -+ -+/* Timer3 Capture Interrupt */ -+#define T3CAPINT_vect _VECTOR(14) -+#define T3CAPINT_vect_num 14 -+ -+/* Timer3 Compare Match Interrupt */ -+#define T3COMINT_vect _VECTOR(16) -+#define T3COMINT_vect_num 16 -+ -+/* Timer3 Overflow Interrupt */ -+#define T3OVFINT_vect _VECTOR(18) -+#define T3OVFINT_vect_num 18 -+ -+/* Timer2 Compare Match Interrupt */ -+#define T2COMINT_vect _VECTOR(20) -+#define T2COMINT_vect_num 20 -+ -+/* Timer2 Overflow Interrupt */ -+#define T2OVFINT_vect _VECTOR(22) -+#define T2OVFINT_vect_num 22 -+ -+/* Timer1 Interval Interrupt */ -+#define T1INT_vect _VECTOR(24) -+#define T1INT_vect_num 24 -+ -+/* SPI Serial Transfer Complete */ -+#define SPISTC_vect _VECTOR(26) -+#define SPISTC_vect_num 26 -+ -+/* Timer Modulator SSI Receive Buffer Interrupt */ -+#define TMRXBINT_vect _VECTOR(28) -+#define TMRXBINT_vect_num 28 -+ -+/* Timer Modulator SSI Transmit Buffer Interrupt */ -+#define TMTXBINT_vect _VECTOR(30) -+#define TMTXBINT_vect_num 30 -+ -+/* Timer Modulator Transmit Complete Interrupt */ -+#define TMTXCINT_vect _VECTOR(32) -+#define TMTXCINT_vect_num 32 -+ -+/* AES Interrupt */ -+#define AESINT_vect _VECTOR(34) -+#define AESINT_vect_num 34 -+ -+/* External Input Clock Monitoring Interrupt */ -+#define EXCMINT_vect _VECTOR(36) -+#define EXCMINT_vect_num 36 -+ -+/* External XTAL Oscillator Break Down Interrupt */ -+#define EXXMINT_vect _VECTOR(38) -+#define EXXMINT_vect_num 38 -+ -+/* Real Time Clock Interrupt */ -+#define RTCINT_vect _VECTOR(40) -+#define RTCINT_vect_num 40 -+ -+/* EEPROM Ready Interrupt */ -+#define EEREADY_vect _VECTOR(42) -+#define EEREADY_vect_num 42 -+ -+/* Store Program Memory Ready */ -+#define SPMREADY_vect _VECTOR(44) -+#define SPMREADY_vect_num 44 -+ -+#define _VECTORS_SIZE 90 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 64 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x1FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 512 -+#define RAMEND 0x02FF -+#define E2START 0 -+#define E2SIZE 2048 -+#define E2PAGESIZE 16 -+#define E2END 0x07FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 1 -+ -+/* Fuse Byte */ -+#define FUSE_CKDIV8 (unsigned char)~_BV(128) -+#define FUSE_DWEN (unsigned char)~_BV(64) -+#define FUSE_SPIEN (unsigned char)~_BV(32) -+#define FUSE_WDTON (unsigned char)~_BV(16) -+#define FUSE_EESAVE (unsigned char)~_BV(8) -+#define FUSE_Reserved (unsigned char)~_BV(4) -+#define FUSE__32OEN (unsigned char)~_BV(2) -+#define FUSE_EXTCLKEN (unsigned char)~_BV(1) -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x93 -+#define SIGNATURE_2 0x61 -+ -+ -+#endif /* #ifdef _AVR_ATA5795_H_INCLUDED */ -+ -diff --git a/include/avr/ioa5831.h b/include/avr/ioa5831.h -new file mode 100644 -index 0000000..761e4b9 ---- /dev/null -+++ b/include/avr/ioa5831.h -@@ -0,0 +1,1885 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATA5831_H_INCLUDED -+#define _AVR_ATA5831_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "ioa5831.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PRR0 _SFR_IO8(0x01) -+#define PRSPI 0 -+#define PRRXDC 1 -+#define PRTXDC 2 -+#define PRCRC 3 -+#define PRVM 4 -+#define PRCO 5 -+ -+#define PRR1 _SFR_IO8(0x02) -+#define PRT1 0 -+#define PRT2 1 -+#define PRT3 2 -+#define PRT4 3 -+#define PRT5 4 -+ -+#define PRR2 _SFR_IO8(0x03) -+#define PRXB 0 -+#define PRXA 1 -+#define PRSF 2 -+#define PRDF 3 -+#define PRIDS 4 -+#define PRRS 5 -+#define PRTM 6 -+#define PRSSM 7 -+ -+#define RDPR _SFR_IO8(0x04) -+#define PRPTB 0 -+#define PRPTA 1 -+#define PRFLT 2 -+#define PRTMP 3 -+#define APRPTB 4 -+#define APRPTA 5 -+#define ARDPRF 6 -+#define RDPRF 7 -+ -+#define PINB _SFR_IO8(0x05) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x06) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x07) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x08) -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x09) -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x0A) -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define FSCR _SFR_IO8(0x0B) -+#define TXMOD 0 -+#define SFM 1 -+#define TXMS0 2 -+#define TXMS1 3 -+#define PAOER 4 -+#define PAON 7 -+ -+/* Reserved [0x0C] */ -+ -+#define RDSIFR _SFR_IO8(0x0D) -+#define NBITA 0 -+#define NBITB 1 -+#define EOTA 2 -+#define EOTB 3 -+#define SOTA 4 -+#define SOTB 5 -+#define WCOA 6 -+#define WCOB 7 -+ -+#define MCUCR _SFR_IO8(0x0E) -+#define IVCE 0 -+#define IVSEL 1 -+#define SPIIO 2 -+#define ENPS 3 -+#define PUD 4 -+#define PB4HS 5 -+#define PB7LS 6 -+#define PB7HS 7 -+ -+#define PCIFR _SFR_IO8(0x0F) -+#define PCIF0 0 -+#define PCIF1 1 -+ -+#define T0CR _SFR_IO8(0x10) -+#define T0PS0 0 -+#define T0PS1 1 -+#define T0PS2 2 -+#define T0IE 3 -+#define T0PR 4 -+ -+#define T1CR _SFR_IO8(0x11) -+#define T1OTM 0 -+#define T1CTM 1 -+#define T1CRM 2 -+#define T1TOP 4 -+#define T1RES 5 -+#define T1TOS 6 -+#define T1ENA 7 -+ -+#define T2CR _SFR_IO8(0x12) -+#define T2OTM 0 -+#define T2CTM 1 -+#define T2CRM 2 -+#define T2TOP 4 -+#define T2RES 5 -+#define T2TOS 6 -+#define T2ENA 7 -+ -+#define T3CR _SFR_IO8(0x13) -+#define T3OTM 0 -+#define T3CTM 1 -+#define T3CRM 2 -+#define T3CPRM 3 -+#define T3TOP 4 -+#define T3RES 5 -+#define T3TOS 6 -+#define T3ENA 7 -+ -+#define T4CR _SFR_IO8(0x14) -+#define T4OTM 0 -+#define T4CTM 1 -+#define T4CRM 2 -+#define T4CPRM 3 -+#define T4TOP 4 -+#define T4RES 5 -+#define T4TOS 6 -+#define T4ENA 7 -+ -+#define T1IFR _SFR_IO8(0x15) -+#define T1OFF 0 -+#define T1COF 1 -+ -+#define T2IFR _SFR_IO8(0x16) -+#define T2OFF 0 -+#define T2COF 1 -+ -+#define T3IFR _SFR_IO8(0x17) -+#define T3OFF 0 -+#define T3COF 1 -+#define T3ICF 2 -+ -+#define T4IFR _SFR_IO8(0x18) -+#define T4OFF 0 -+#define T4COF 1 -+#define T4ICF 2 -+ -+#define T5IFR _SFR_IO8(0x19) -+#define T5OFF 0 -+#define T5COF 1 -+ -+#define GPIOR0 _SFR_IO8(0x1A) -+ -+#define GPIOR3 _SFR_IO8(0x1B) -+ -+#define GPIOR4 _SFR_IO8(0x1C) -+ -+#define GPIOR5 _SFR_IO8(0x1D) -+ -+#define GPIOR6 _SFR_IO8(0x1E) -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEWE 1 -+#define EEMWE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+#define EEPAGE 6 -+#define NVMBSY 7 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define EEPR _SFR_IO8(0x23) -+#define EEAP0 0 -+#define EEAP1 1 -+#define EEAP2 2 -+#define EEAP3 3 -+ -+#define GPIOR1 _SFR_IO8(0x24) -+ -+#define GPIOR2 _SFR_IO8(0x25) -+ -+#define PCICR _SFR_IO8(0x26) -+#define PCIE0 0 -+#define PCIE1 1 -+ -+#define EIMSK _SFR_IO8(0x27) -+#define INT0 0 -+#define INT1 1 -+ -+#define EIFR _SFR_IO8(0x28) -+#define INTF0 0 -+#define INTF1 1 -+ -+#define CRCDIR _SFR_IO8(0x29) -+ -+#define VMCSR _SFR_IO8(0x2A) -+#define VMLS0 0 -+#define VMLS1 1 -+#define VMLS2 2 -+#define VMLS3 3 -+#define VMIM 4 -+#define VMF 5 -+ -+#define MCUSR _SFR_IO8(0x2B) -+#define PORF 0 -+#define EXTRF 1 -+#define WDRF 3 -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define RXIF 4 -+#define TXIF 5 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+#define T0IFR _SFR_IO8(0x2F) -+#define T0F 0 -+ -+/* Reserved [0x30] */ -+ -+#define DWDR _SFR_IO8(0x31) -+ -+/* Reserved [0x32] */ -+ -+#define RDCR _SFR_IO8(0x33) -+#define RDPU 0 -+#define ADIVEN 1 -+#define RDEN 2 -+ -+#define EOTSA _SFR_IO8(0x34) -+#define CARFA 0 -+#define AMPFA 1 -+#define SYTFA 2 -+#define MANFA 3 -+#define TMOFA 4 -+#define TELRA 5 -+#define RRFA 6 -+#define EOTBF 7 -+ -+#define EOTCA _SFR_IO8(0x35) -+#define CARFEA 0 -+#define AMPFEA 1 -+#define SYTFEA 2 -+#define MANFEA 3 -+#define TMOFEA 4 -+#define TELREA 5 -+#define RRFEA 6 -+#define EOTBFE 7 -+ -+#define EOTSB _SFR_IO8(0x36) -+#define CARFB 0 -+#define AMPFB 1 -+#define SYTFB 2 -+#define MANFB 3 -+#define TMOFB 4 -+#define TELRB 5 -+#define RRFB 6 -+#define EOTAF 7 -+ -+#define EOTCB _SFR_IO8(0x37) -+#define CARFEB 0 -+#define AMPFEB 1 -+#define SYTFEB 2 -+#define MANFEB 3 -+#define TMOFEB 4 -+#define TELREB 5 -+#define RRFEB 6 -+#define EOTAFE 7 -+ -+#define SMCR _SFR_IO8(0x38) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define CMCR _SFR_IO8(0x39) -+#define CMM0 0 -+#define CMM1 1 -+#define CMM2 2 -+#define CCS 3 -+#define SRCD 4 -+#define CMONEN 6 -+#define CMCCE 7 -+ -+#define CMIMR _SFR_IO8(0x3A) -+#define ECIE 0 -+ -+#define CLPR _SFR_IO8(0x3B) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLTPS0 3 -+#define CLTPS1 4 -+#define CLTPS2 5 -+#define CLPCE 7 -+ -+#define SPMCSR _SFR_IO8(0x3C) -+#define SELFPRGEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define SPMIE 7 -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define FSEN _SFR_MEM8(0x60) -+#define SDPU 0 -+#define SDEN 1 -+#define GAEN 2 -+#define PEEN 3 -+#define ASEN 4 -+#define ANTT 5 -+ -+#define FSFCR _SFR_MEM8(0x61) -+#define BTSEL0 0 -+#define BTSEL1 1 -+#define ASDIV0 4 -+#define ASDIV1 5 -+#define ASDIV2 6 -+#define ASDIV3 7 -+ -+/* Combine GACDIVL and GACDIVH */ -+#define GACDIV _SFR_MEM16(0x62) -+ -+#define GACDIVL _SFR_MEM8(0x62) -+#define GACDIVH _SFR_MEM8(0x63) -+ -+#define FFREQ1L _SFR_MEM8(0x64) -+ -+#define FFREQ1M _SFR_MEM8(0x65) -+ -+#define FFREQ1H _SFR_MEM8(0x66) -+ -+#define FFREQ2L _SFR_MEM8(0x67) -+ -+#define FFREQ2M _SFR_MEM8(0x68) -+ -+#define FFREQ2H _SFR_MEM8(0x69) -+ -+/* Reserved [0x6A] */ -+ -+#define EICRA _SFR_MEM8(0x6B) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+ -+#define PCMSK0 _SFR_MEM8(0x6C) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6D) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+ -+#define WDTCR _SFR_MEM8(0x6E) -+#define WDPS0 0 -+#define WDPS1 1 -+#define WDPS2 2 -+#define WDE 3 -+#define WDCE 4 -+ -+#define T1CNT _SFR_MEM8(0x6F) -+ -+#define T1COR _SFR_MEM8(0x70) -+ -+#define T1MR _SFR_MEM8(0x71) -+#define T1CS0 0 -+#define T1CS1 1 -+#define T1PS0 2 -+#define T1PS1 3 -+#define T1PS2 4 -+#define T1PS3 5 -+#define T1DC0 6 -+#define T1DC1 7 -+ -+#define T1IMR _SFR_MEM8(0x72) -+#define T1OIM 0 -+#define T1CIM 1 -+ -+#define T2CNT _SFR_MEM8(0x73) -+ -+#define T2COR _SFR_MEM8(0x74) -+ -+#define T2MR _SFR_MEM8(0x75) -+#define T2CS0 0 -+#define T2CS1 1 -+#define T2PS0 2 -+#define T2PS1 3 -+#define T2PS2 4 -+#define T2PS3 5 -+#define T2DC0 6 -+#define T2DC1 7 -+ -+#define T2IMR _SFR_MEM8(0x76) -+#define T2OIM 0 -+#define T2CIM 1 -+ -+/* Combine T3CNTL and T3CNTH */ -+#define T3CNT _SFR_MEM16(0x77) -+ -+#define T3CNTL _SFR_MEM8(0x77) -+#define T3CNTH _SFR_MEM8(0x78) -+ -+/* Combine T3CORL and T3CORH */ -+#define T3COR _SFR_MEM16(0x79) -+ -+#define T3CORL _SFR_MEM8(0x79) -+#define T3CORH _SFR_MEM8(0x7A) -+ -+/* Combine T3ICRL and T3ICRH */ -+#define T3ICR _SFR_MEM16(0x7B) -+ -+#define T3ICRL _SFR_MEM8(0x7B) -+#define T3ICRH _SFR_MEM8(0x7C) -+ -+#define T3MRA _SFR_MEM8(0x7D) -+#define T3CS0 0 -+#define T3CS1 1 -+#define T3PS0 2 -+#define T3PS1 3 -+#define T3PS2 4 -+ -+#define T3MRB _SFR_MEM8(0x7E) -+#define T3SCE 1 -+#define T3CNC 2 -+#define T3CE0 3 -+#define T3CE1 4 -+#define T3ICS0 5 -+#define T3ICS1 6 -+#define T3ICS2 7 -+ -+#define T3IMR _SFR_MEM8(0x7F) -+#define T3OIM 0 -+#define T3CIM 1 -+#define T3CPIM 2 -+ -+/* Combine T4CNTL and T4CNTH */ -+#define T4CNT _SFR_MEM16(0x80) -+ -+#define T4CNTL _SFR_MEM8(0x80) -+#define T4CNTH _SFR_MEM8(0x81) -+ -+/* Combine T4CORL and T4CORH */ -+#define T4COR _SFR_MEM16(0x82) -+ -+#define T4CORL _SFR_MEM8(0x82) -+#define T4CORH _SFR_MEM8(0x83) -+ -+/* Combine T4ICRL and T4ICRH */ -+#define T4ICR _SFR_MEM16(0x84) -+ -+#define T4ICRL _SFR_MEM8(0x84) -+#define T4ICRH _SFR_MEM8(0x85) -+ -+#define T4MRA _SFR_MEM8(0x86) -+#define T4CS0 0 -+#define T4CS1 1 -+#define T4PS0 2 -+#define T4PS1 3 -+#define T4PS2 4 -+ -+#define T4MRB _SFR_MEM8(0x87) -+#define T4SCE 1 -+#define T4CNC 2 -+#define T4CE0 3 -+#define T4CE1 4 -+#define T4ICS0 5 -+#define T4ICS1 6 -+#define T4ICS2 7 -+ -+#define T4IMR _SFR_MEM8(0x88) -+#define T4OIM 0 -+#define T4CIM 1 -+#define T4CPIM 2 -+ -+/* Reserved [0x89] */ -+ -+/* Combine T5OCRL and T5OCRH */ -+#define T5OCR _SFR_MEM16(0x8A) -+ -+#define T5OCRL _SFR_MEM8(0x8A) -+#define T5OCRH _SFR_MEM8(0x8B) -+ -+#define T5CCR _SFR_MEM8(0x8C) -+#define T5CS0 0 -+#define T5CS1 1 -+#define T5CS2 2 -+#define T5CTC 3 -+ -+/* Combine T5CNTL and T5CNTH */ -+#define T5CNT _SFR_MEM16(0x8D) -+ -+#define T5CNTL _SFR_MEM8(0x8D) -+#define T5CNTH _SFR_MEM8(0x8E) -+ -+#define T5IMR _SFR_MEM8(0x8F) -+#define T5OIM 0 -+#define T5CIM 1 -+ -+#define GTCCR _SFR_MEM8(0x90) -+#define PSR10 0 -+#define TSM 7 -+ -+#define SOTSB _SFR_MEM8(0x91) -+#define CAROB 0 -+#define AMPOB 1 -+#define SYTOB 2 -+#define MANOB 3 -+#define WUPOB 4 -+#define SFIDOB 5 -+#define RROB 6 -+#define WCOAO 7 -+ -+#define SOTSA _SFR_MEM8(0x92) -+#define CAROA 0 -+#define AMPOA 1 -+#define SYTOA 2 -+#define MANOA 3 -+#define WUPOA 4 -+#define SFIDOA 5 -+#define RROA 6 -+#define WCOBO 7 -+ -+#define SOTCB _SFR_MEM8(0x93) -+#define CAROEB 0 -+#define AMPOEB 1 -+#define SYTOEB 2 -+#define MANOEB 3 -+#define WUPEB 4 -+#define SFIDEB 5 -+#define RROEB 6 -+#define WCOAOE 7 -+ -+#define SOTCA _SFR_MEM8(0x94) -+#define CAROEA 0 -+#define AMPOEA 1 -+#define SYTOEA 2 -+#define MANOEA 3 -+#define WUPEA 4 -+#define SFIDEA 5 -+#define RROEA 6 -+#define WCOBOE 7 -+ -+#define TESRB _SFR_MEM8(0x95) -+#define CRCOB 0 -+#define EOTLB0 1 -+#define EOTLB1 2 -+ -+#define TESRA _SFR_MEM8(0x96) -+#define CRCOA 0 -+#define EOTLA0 1 -+#define EOTLA1 2 -+ -+/* Reserved [0x97] */ -+ -+#define RDSIMR _SFR_MEM8(0x98) -+#define NBITAM 0 -+#define NBITBM 1 -+#define EOTAM 2 -+#define EOTBM 3 -+#define SOTAM 4 -+#define SOTBM 5 -+#define WCOAM 6 -+#define WCOBM 7 -+ -+#define RDOCR _SFR_MEM8(0x99) -+#define TMDS0 1 -+#define TMDS1 2 -+#define ETRPA 3 -+#define ETRPB 4 -+#define RDSIDA 5 -+#define RDSIDB 6 -+ -+/* Reserved [0x9A] */ -+ -+#define TEMPL _SFR_MEM8(0x9B) -+ -+#define TEMPH _SFR_MEM8(0x9C) -+ -+#define SYCB _SFR_MEM8(0x9D) -+#define SYCSB0 0 -+#define SYCSB1 1 -+#define SYCSB2 2 -+#define SYCSB3 3 -+#define SYTLB0 4 -+#define SYTLB1 5 -+#define SYTLB2 6 -+#define SYTLB3 7 -+ -+#define SYCA _SFR_MEM8(0x9E) -+#define SYCSA0 0 -+#define SYCSA1 1 -+#define SYCSA2 2 -+#define SYCSA3 3 -+#define SYTLA0 4 -+#define SYTLA1 5 -+#define SYTLA2 6 -+#define SYTLA3 7 -+ -+#define RXFOB _SFR_MEM8(0x9F) -+ -+#define RXFOA _SFR_MEM8(0xA0) -+ -+#define DMMB _SFR_MEM8(0xA1) -+#define DMATB0 0 -+#define DMATB1 1 -+#define DMATB2 2 -+#define DMATB3 3 -+#define DMATB4 4 -+#define DMPB 5 -+#define DMHB 6 -+#define DMNEB 7 -+ -+#define DMMA _SFR_MEM8(0xA2) -+#define DMATA0 0 -+#define DMATA1 1 -+#define DMATA2 2 -+#define DMATA3 3 -+#define DMATA4 4 -+#define DMPA 5 -+#define DMHA 6 -+#define DMNEA 7 -+ -+#define DMCDB _SFR_MEM8(0xA3) -+#define DMCLB0 0 -+#define DMCLB1 1 -+#define DMCLB2 2 -+#define DMCLB3 3 -+#define DMCLB4 4 -+#define DMCTB0 5 -+#define DMCTB1 6 -+#define DMCTB2 7 -+ -+#define DMCDA _SFR_MEM8(0xA4) -+#define DMCLA0 0 -+#define DMCLA1 1 -+#define DMCLA2 2 -+#define DMCLA3 3 -+#define DMCLA4 4 -+#define DMCTA0 5 -+#define DMCTA1 6 -+#define DMCTA2 7 -+ -+#define DMCRB _SFR_MEM8(0xA5) -+#define DMPGB0 0 -+#define DMPGB1 1 -+#define DMPGB2 2 -+#define DMPGB3 3 -+#define DMPGB4 4 -+#define SASKB 5 -+#define SY1TB 6 -+#define DMARB 7 -+ -+#define DMCRA _SFR_MEM8(0xA6) -+#define DMPGA0 0 -+#define DMPGA1 1 -+#define DMPGA2 2 -+#define DMPGA3 3 -+#define DMPGA4 4 -+#define SASKA 5 -+#define SY1TA 6 -+#define DMARA 7 -+ -+#define DMDRB _SFR_MEM8(0xA7) -+#define DMAB0 0 -+#define DMAB1 1 -+#define DMAB2 2 -+#define DMAB3 3 -+#define DMDNB0 4 -+#define DMDNB1 5 -+#define DMDNB2 6 -+#define DMDNB3 7 -+ -+#define DMDRA _SFR_MEM8(0xA8) -+#define DMAA0 0 -+#define DMAA1 1 -+#define DMAA2 2 -+#define DMAA3 3 -+#define DMDNA0 4 -+#define DMDNA1 5 -+#define DMDNA2 6 -+#define DMDNA3 7 -+ -+#define CHCR _SFR_MEM8(0xA9) -+#define BWM0 0 -+#define BWM1 1 -+#define BWM2 2 -+#define BWM3 3 -+ -+#define CHDN _SFR_MEM8(0xAA) -+#define BBDN0 0 -+#define BBDN1 1 -+#define BBDN2 2 -+#define BBDN3 3 -+#define BBDN4 4 -+#define ADCDN 5 -+ -+#define SFIDCB _SFR_MEM8(0xAB) -+#define SFIDTB0 0 -+#define SFIDTB1 1 -+#define SFIDTB2 2 -+#define SFIDTB3 3 -+#define SFIDTB4 4 -+#define SEMEB 7 -+ -+#define SFIDLB _SFR_MEM8(0xAC) -+#define SFIDLB0 0 -+#define SFIDLB1 1 -+#define SFIDLB2 2 -+#define SFIDLB3 3 -+#define SFIDLB4 4 -+#define SFIDLB5 5 -+ -+#define WUPTB _SFR_MEM8(0xAD) -+#define WUPTB0 0 -+#define WUPTB1 1 -+#define WUPTB2 2 -+#define WUPTB3 3 -+#define WUPTB4 4 -+ -+#define WUPLB _SFR_MEM8(0xAE) -+#define WUPLB0 0 -+#define WUPLB1 1 -+#define WUPLB2 2 -+#define WUPLB3 3 -+#define WUPLB4 4 -+#define WUPLB5 5 -+ -+#define SFID1B _SFR_MEM8(0xAF) -+ -+#define SFID2B _SFR_MEM8(0xB0) -+ -+#define SFID3B _SFR_MEM8(0xB1) -+ -+#define SFID4B _SFR_MEM8(0xB2) -+ -+#define WUP1B _SFR_MEM8(0xB3) -+ -+#define WUP2B _SFR_MEM8(0xB4) -+ -+#define WUP3B _SFR_MEM8(0xB5) -+ -+#define WUP4B _SFR_MEM8(0xB6) -+ -+#define SFIDCA _SFR_MEM8(0xB7) -+#define SFIDTA0 0 -+#define SFIDTA1 1 -+#define SFIDTA2 2 -+#define SFIDTA3 3 -+#define SFIDTA4 4 -+#define SEMEA 7 -+ -+#define SFIDLA _SFR_MEM8(0xB8) -+#define SFIDLA0 0 -+#define SFIDLA1 1 -+#define SFIDLA2 2 -+#define SFIDLA3 3 -+#define SFIDLA4 4 -+#define SFIDLA5 5 -+ -+#define WUPTA _SFR_MEM8(0xB9) -+#define WUPTA0 0 -+#define WUPTA1 1 -+#define WUPTA2 2 -+#define WUPTA3 3 -+#define WUPTA4 4 -+ -+#define WUPLA _SFR_MEM8(0xBA) -+#define WUPLA0 0 -+#define WUPLA1 1 -+#define WUPLA2 2 -+#define WUPLA3 3 -+#define WUPLA4 4 -+#define WUPLA5 5 -+ -+#define SFID1A _SFR_MEM8(0xBB) -+ -+#define SFID2A _SFR_MEM8(0xBC) -+ -+#define SFID3A _SFR_MEM8(0xBD) -+ -+#define SFID4A _SFR_MEM8(0xBE) -+ -+#define WUP1A _SFR_MEM8(0xBF) -+ -+#define WUP2A _SFR_MEM8(0xC0) -+ -+#define WUP3A _SFR_MEM8(0xC1) -+ -+#define WUP4A _SFR_MEM8(0xC2) -+ -+#define CLKOD _SFR_MEM8(0xC3) -+ -+#define CLKOCR _SFR_MEM8(0xC4) -+#define CLKOS0 0 -+#define CLKOS1 1 -+#define CLKOEN 2 -+ -+#define XFUSE _SFR_MEM8(0xC5) -+ -+#define SRCCAL _SFR_MEM8(0xC6) -+#define SRCCAL0 0 -+#define SRCCAL1 1 -+#define SRCCAL2 2 -+#define SRCCAL3 3 -+#define SRCCAL4 4 -+#define SRCCAL5 5 -+#define SRCTC0 6 -+#define SRCTC1 7 -+ -+#define FRCCAL _SFR_MEM8(0xC7) -+#define FRCCAL0 0 -+#define FRCCAL1 1 -+#define FRCCAL2 2 -+#define FRCCAL3 3 -+#define FRCCAL4 4 -+#define FRCTC 5 -+ -+#define CMSR _SFR_MEM8(0xC8) -+#define ECF 0 -+ -+#define CMOCR _SFR_MEM8(0xC9) -+#define FRCAO 0 -+#define SRCAO 1 -+#define FRCACT 2 -+#define SRCACT 3 -+ -+#define SUPFR _SFR_MEM8(0xCA) -+#define AVCCRF 0 -+#define AVCCLF 1 -+ -+#define SUPCR _SFR_MEM8(0xCB) -+#define AVCCRM 0 -+#define AVCCLM 1 -+#define PVEN 2 -+#define DVDIS 4 -+#define AVEN 5 -+#define AVDIC 6 -+ -+#define SUPCA1 _SFR_MEM8(0xCC) -+#define PV22 2 -+#define PVDIC 3 -+#define PVCAL0 4 -+#define PVCAL1 5 -+#define PVCAL2 6 -+#define PVCAL3 7 -+ -+#define SUPCA2 _SFR_MEM8(0xCD) -+#define BGCAL0 0 -+#define BGCAL1 1 -+#define BGCAL2 2 -+#define BGCAL3 3 -+ -+#define SUPCA3 _SFR_MEM8(0xCE) -+#define ACAL4 0 -+#define ACAL5 1 -+#define ACAL6 2 -+#define ACAL7 3 -+#define DCAL4 4 -+#define DCAL5 5 -+#define DCAL6 6 -+ -+#define SUPCA4 _SFR_MEM8(0xCF) -+#define ACAL0 0 -+#define ACAL1 1 -+#define ACAL2 2 -+#define ACAL3 3 -+#define DCAL0 4 -+#define DCAL1 5 -+#define DCAL2 6 -+#define DCAL3 7 -+ -+#define CALRDY _SFR_MEM8(0xD0) -+ -+#define VMCAL _SFR_MEM8(0xD1) -+#define VMCAL0 0 -+#define VMCAL1 1 -+#define VMCAL2 2 -+ -+#define DFS _SFR_MEM8(0xD2) -+#define DFFLRF 0 -+#define DFUFL 1 -+#define DFOFL 2 -+ -+/* Combine DFTLL and DFTLH */ -+#define DFTL _SFR_MEM16(0xD3) -+ -+#define DFTLL _SFR_MEM8(0xD3) -+#define DFTLH _SFR_MEM8(0xD4) -+ -+#define DFL _SFR_MEM8(0xD5) -+#define DFFLS0 0 -+#define DFFLS1 1 -+#define DFFLS2 2 -+#define DFFLS3 3 -+#define DFFLS4 4 -+#define DFFLS5 5 -+#define DFCLR 7 -+ -+#define DFWP _SFR_MEM8(0xD6) -+#define DFWP0 0 -+#define DFWP1 1 -+#define DFWP2 2 -+#define DFWP3 3 -+#define DFWP4 4 -+#define DFWP5 5 -+ -+#define DFRP _SFR_MEM8(0xD7) -+#define DFRP0 0 -+#define DFRP1 1 -+#define DFRP2 2 -+#define DFRP3 3 -+#define DFRP4 4 -+#define DFRP5 5 -+ -+#define DFD _SFR_MEM8(0xD8) -+ -+#define DFI _SFR_MEM8(0xD9) -+#define DFFLIM 0 -+#define DFERIM 1 -+ -+#define DFC _SFR_MEM8(0xDA) -+#define DFFLC0 0 -+#define DFFLC1 1 -+#define DFFLC2 2 -+#define DFFLC3 3 -+#define DFFLC4 4 -+#define DFFLC5 5 -+#define DFDRA 7 -+ -+#define SFS _SFR_MEM8(0xDB) -+#define SFFLRF 0 -+#define SFUFL 1 -+#define SFOFL 2 -+ -+#define SFL _SFR_MEM8(0xDC) -+#define SFFLS0 0 -+#define SFFLS1 1 -+#define SFFLS2 2 -+#define SFFLS3 3 -+#define SFFLS4 4 -+#define SFCLR 7 -+ -+#define SFWP _SFR_MEM8(0xDD) -+#define SFWP0 0 -+#define SFWP1 1 -+#define SFWP2 2 -+#define SFWP3 3 -+#define SFWP4 4 -+ -+#define SFRP _SFR_MEM8(0xDE) -+#define SFRP0 0 -+#define SFRP1 1 -+#define SFRP2 2 -+#define SFRP3 3 -+#define SFRP4 4 -+ -+#define SFD _SFR_MEM8(0xDF) -+ -+#define SFI _SFR_MEM8(0xE0) -+#define SFFLIM 0 -+#define SFERIM 1 -+ -+#define SFC _SFR_MEM8(0xE1) -+#define SFFLC0 0 -+#define SFFLC1 1 -+#define SFFLC2 2 -+#define SFFLC3 3 -+#define SFFLC4 4 -+#define SFDRA 7 -+ -+#define SSMCR _SFR_MEM8(0xE2) -+#define SSMTX 0 -+#define SSMTM 1 -+#define SSMTGE 2 -+#define SSMTPE 3 -+#define SSMPVE 4 -+#define SSMTAE 5 -+#define SETRPA 6 -+#define SETRPB 7 -+ -+#define SSMRCR _SFR_MEM8(0xE3) -+#define SSMPA 0 -+#define SSMPB 1 -+#define SSMADA 2 -+#define SSMADB 3 -+#define SSMPVS 4 -+#define SSMIFA 5 -+#define SSMIDSE 6 -+#define SSMTMOE 7 -+ -+#define SSMFBR _SFR_MEM8(0xE4) -+#define SSMFID0 0 -+#define SSMFID1 1 -+#define SSMFID2 2 -+#define SSMDFDT 3 -+#define SSMHADT 4 -+#define SSMPLDT 5 -+ -+#define SSMRR _SFR_MEM8(0xE5) -+#define SSMR 0 -+#define SSMST 1 -+ -+#define SSMSR _SFR_MEM8(0xE6) -+#define SSMESM0 0 -+#define SSMESM1 1 -+#define SSMESM2 2 -+#define SSMESM3 3 -+#define SSMERR 7 -+ -+#define SSMIFR _SFR_MEM8(0xE7) -+#define SSMIF 0 -+ -+#define SSMIMR _SFR_MEM8(0xE8) -+#define SSMIM 0 -+ -+#define MSMSTR _SFR_MEM8(0xE9) -+#define SSMMST0 0 -+#define SSMMST1 1 -+#define SSMMST2 2 -+#define SSMMST3 3 -+#define SSMMST4 4 -+ -+#define SSMSTR _SFR_MEM8(0xEA) -+#define SSMSTA0 0 -+#define SSMSTA1 1 -+#define SSMSTA2 2 -+#define SSMSTA3 3 -+#define SSMSTA4 4 -+#define SSMSTA5 5 -+ -+#define SSMXSR _SFR_MEM8(0xEB) -+#define SSMSTB0 0 -+#define SSMSTB1 1 -+#define SSMSTB2 2 -+#define SSMSTB3 3 -+#define SSMSTB4 4 -+#define SSMSTB5 5 -+ -+#define MSMCR1 _SFR_MEM8(0xEC) -+#define MSMSM00 0 -+#define MSMSM01 1 -+#define MSMSM02 2 -+#define MSMSM03 3 -+#define MSMSM10 4 -+#define MSMSM11 5 -+#define MSMSM12 6 -+#define MSMSM13 7 -+ -+#define MSMCR2 _SFR_MEM8(0xED) -+#define MSMSM20 0 -+#define MSMSM21 1 -+#define MSMSM22 2 -+#define MSMSM23 3 -+#define MSMSM30 4 -+#define MSMSM31 5 -+#define MSMSM32 6 -+#define MSMSM33 7 -+ -+#define MSMCR3 _SFR_MEM8(0xEE) -+#define MSMSM40 0 -+#define MSMSM41 1 -+#define MSMSM42 2 -+#define MSMSM43 3 -+#define MSMSM50 4 -+#define MSMSM51 5 -+#define MSMSM52 6 -+#define MSMSM53 7 -+ -+#define MSMCR4 _SFR_MEM8(0xEF) -+#define MSMSM60 0 -+#define MSMSM61 1 -+#define MSMSM62 2 -+#define MSMSM63 3 -+#define MSMSM70 4 -+#define MSMSM71 5 -+#define MSMSM72 6 -+#define MSMSM73 7 -+ -+#define GTCR _SFR_MEM8(0xF0) -+#define RXTEHA 0 -+#define GAPMA 1 -+#define DARA 2 -+#define IWUPA 3 -+#define RXTEHB 4 -+#define GAPMB 5 -+#define DARB 6 -+#define IWUPB 7 -+ -+#define SOTC1A _SFR_MEM8(0xF1) -+#define CAROEA1 0 -+#define AMPOEA1 1 -+#define SYTOEA1 2 -+#define MANOEA1 3 -+#define WUPEA1 4 -+#define SFIDEA1 5 -+#define RROEA1 6 -+#define WCOBOE1 7 -+ -+#define SOTC2A _SFR_MEM8(0xF2) -+#define CAROEA2 0 -+#define AMPOEA2 1 -+#define SYTOEA2 2 -+#define MANOEA2 3 -+#define WUPEA2 4 -+#define SFIDEA2 5 -+#define RROEA2 6 -+#define WCOBOE2 7 -+ -+#define SOTC1B _SFR_MEM8(0xF3) -+#define CAROEB1 0 -+#define AMPOEB1 1 -+#define SYTOEB1 2 -+#define MANOEB1 3 -+#define WUPEB1 4 -+#define SFIDEB1 5 -+#define RROEB1 6 -+#define WCOAOE1 7 -+ -+#define SOTC2B _SFR_MEM8(0xF4) -+#define CAROEB2 0 -+#define AMPOEB2 1 -+#define SYTOEB2 2 -+#define MANOEB2 3 -+#define WUPEB2 4 -+#define SFIDEB2 5 -+#define RROEB2 6 -+#define WCOAOE2 7 -+ -+#define EOTC1A _SFR_MEM8(0xF5) -+#define CARFEA1 0 -+#define AMPFEA1 1 -+#define SYTFEA1 2 -+#define MANFEA1 3 -+#define TMOFEA1 4 -+#define TELREA1 5 -+#define RRFEA1 6 -+#define EOTBFE1 7 -+ -+#define EOTC2A _SFR_MEM8(0xF6) -+#define CARFEA2 0 -+#define AMPFEA2 1 -+#define SYTFEA2 2 -+#define MANFEA2 3 -+#define TMOFEA2 4 -+#define TELREA2 5 -+#define RRFEA2 6 -+#define EOTBFE2 7 -+ -+#define EOTC3A _SFR_MEM8(0xF7) -+#define CARFEA3 0 -+#define AMPFEA3 1 -+#define SYTFEA3 2 -+#define MANFEA3 3 -+#define TMOFEA3 4 -+#define TELREA3 5 -+#define RRFEA3 6 -+#define EOTBFE3 7 -+ -+#define EOTC1B _SFR_MEM8(0xF8) -+#define CARFEB1 0 -+#define AMPFEB1 1 -+#define SYTFEB1 2 -+#define MANFEB1 3 -+#define TMOFEB1 4 -+#define TELREB1 5 -+#define RRFEB1 6 -+#define EOTAFE1 7 -+ -+#define EOTC2B _SFR_MEM8(0xF9) -+#define CARFEB2 0 -+#define AMPFEB2 1 -+#define SYTFEB2 2 -+#define MANFEB2 3 -+#define TMOFEB2 4 -+#define TELREB2 5 -+#define RRFEB2 6 -+#define EOTAFE2 7 -+ -+#define EOTC3B _SFR_MEM8(0xFA) -+#define CARFEB3 0 -+#define AMPFEB3 1 -+#define SYTFEB3 2 -+#define MANFEB3 3 -+#define TMOFEB3 4 -+#define TELREB3 5 -+#define RRFEB3 6 -+#define EOTAFE3 7 -+ -+#define WCOTOA _SFR_MEM8(0xFB) -+ -+#define WCOTOB _SFR_MEM8(0xFC) -+ -+#define SOTTOA _SFR_MEM8(0xFD) -+ -+#define SOTTOB _SFR_MEM8(0xFE) -+ -+#define SSMFCR _SFR_MEM8(0xFF) -+#define SSMIDSO 0 -+#define SSMIDSF 1 -+ -+#define FESR _SFR_MEM8(0x100) -+#define LBSAT 0 -+#define HBSAT 1 -+#define XRDY 2 -+#define PLCK 3 -+#define ANTS 4 -+ -+#define FEEN1 _SFR_MEM8(0x101) -+#define PLEN 0 -+#define PLCAL 1 -+#define XTOEN 2 -+#define LNAEN 3 -+#define ADEN 4 -+#define ADCLK 5 -+#define PLSP1 6 -+#define ATEN 7 -+ -+#define FEEN2 _SFR_MEM8(0x102) -+#define SDRX 0 -+#define SDTX 1 -+#define PAEN 2 -+#define TMPM 3 -+#define PLPEN 4 -+#define XTPEN 5 -+#define CPBIA 6 -+ -+#define FELNA _SFR_MEM8(0x103) -+#define LBH0 0 -+#define LBH1 1 -+#define LBH2 2 -+#define LBH3 3 -+#define LBL0 4 -+#define LBL1 5 -+#define LBL2 6 -+#define LBL3 7 -+ -+#define FEAT _SFR_MEM8(0x104) -+#define ANTN0 0 -+#define ANTN1 1 -+#define ANTN2 2 -+#define ANTN3 3 -+ -+#define FEPAC _SFR_MEM8(0x105) -+ -+#define FEVCT _SFR_MEM8(0x106) -+#define FEVCT0 0 -+#define FEVCT1 1 -+#define FEVCT2 2 -+#define FEVCT3 3 -+ -+#define FEBT _SFR_MEM8(0x107) -+#define CTN20 0 -+#define CTN21 1 -+#define RTN20 2 -+#define RTN21 3 -+ -+#define FEMS _SFR_MEM8(0x108) -+#define PLLS0 0 -+#define PLLS1 1 -+#define PLLS2 2 -+#define PLLS3 3 -+#define PLLM0 4 -+#define PLLM1 5 -+#define PLLM2 6 -+#define PLLM3 7 -+ -+#define FETN4 _SFR_MEM8(0x109) -+#define CTN40 0 -+#define CTN41 1 -+#define CTN42 2 -+#define CTN43 3 -+#define RTN40 4 -+#define RTN41 5 -+#define RTN42 6 -+#define RTN43 7 -+ -+#define FECR _SFR_MEM8(0x10A) -+#define LBNHB 0 -+#define S4N3 1 -+#define ANDP 2 -+#define ADHS 3 -+#define PLCKG 4 -+#define ANPS 5 -+ -+#define FEVCO _SFR_MEM8(0x10B) -+#define CPCC0 0 -+#define CPCC1 1 -+#define CPCC2 2 -+#define CPCC3 3 -+#define VCOB0 4 -+#define VCOB1 5 -+#define VCOB2 6 -+#define VCOB3 7 -+ -+#define FEALR _SFR_MEM8(0x10C) -+#define RNGE0 0 -+#define RNGE1 1 -+ -+#define FEANT _SFR_MEM8(0x10D) -+#define LVLC0 0 -+#define LVLC1 1 -+#define LVLC2 2 -+#define LVLC3 3 -+ -+#define FEBIA _SFR_MEM8(0x10E) -+#define IFAEN 7 -+ -+/* Reserved [0x10F..0x11F] */ -+ -+#define TMFSM _SFR_MEM8(0x120) -+#define TMSSM0 0 -+#define TMSSM1 1 -+#define TMSSM2 2 -+#define TMSSM3 3 -+#define TMMSM0 4 -+#define TMMSM1 5 -+#define TMMSM2 6 -+ -+/* Combine TMCRL and TMCRH */ -+#define TMCR _SFR_MEM16(0x121) -+ -+#define TMCRL _SFR_MEM8(0x121) -+#define TMCRH _SFR_MEM8(0x122) -+ -+#define TMCSB _SFR_MEM8(0x123) -+ -+/* Combine TMCIL and TMCIH */ -+#define TMCI _SFR_MEM16(0x124) -+ -+#define TMCIL _SFR_MEM8(0x124) -+#define TMCIH _SFR_MEM8(0x125) -+ -+/* Combine TMCPL and TMCPH */ -+#define TMCP _SFR_MEM16(0x126) -+ -+#define TMCPL _SFR_MEM8(0x126) -+#define TMCPH _SFR_MEM8(0x127) -+ -+#define TMSHR _SFR_MEM8(0x128) -+ -+/* Combine TMTLL and TMTLH */ -+#define TMTL _SFR_MEM16(0x129) -+ -+#define TMTLL _SFR_MEM8(0x129) -+#define TMTLH _SFR_MEM8(0x12A) -+ -+#define TMSSC _SFR_MEM8(0x12B) -+#define TMSSP0 0 -+#define TMSSP1 1 -+#define TMSSP2 2 -+#define TMSSP3 3 -+#define TMSSL0 4 -+#define TMSSL1 5 -+#define TMSSL2 6 -+#define TMSSH 7 -+ -+#define TMSR _SFR_MEM8(0x12C) -+#define TMTCF 0 -+ -+#define TMCR2 _SFR_MEM8(0x12D) -+#define TMCRCE 0 -+#define TMCRCL0 1 -+#define TMCRCL1 2 -+#define TMNRZE 3 -+#define TMPOL 4 -+#define TMSSE 5 -+#define TMMSB 6 -+ -+#define TMCR1 _SFR_MEM8(0x12E) -+#define TMPIS0 0 -+#define TMPIS1 1 -+#define TMPIS2 2 -+#define TMSCS 3 -+#define TMCIM 4 -+ -+#define RXBC1 _SFR_MEM8(0x12F) -+#define RXCEA 0 -+#define RXCBLA0 1 -+#define RXCBLA1 2 -+#define RXMSBA 3 -+#define RXCEB 4 -+#define RXCBLB0 5 -+#define RXCBLB1 6 -+#define RXMSBB 7 -+ -+#define RXBC2 _SFR_MEM8(0x130) -+#define RXBPB 0 -+#define RXBF 1 -+#define RXBCLR 2 -+ -+#define RXTLLB _SFR_MEM8(0x131) -+ -+#define RXTLHB _SFR_MEM8(0x132) -+#define RXTLHB0 0 -+#define RXTLHB1 1 -+#define RXTLHB2 2 -+#define RXTLHB3 3 -+ -+#define RXCRLB _SFR_MEM8(0x133) -+ -+#define RXCRHB _SFR_MEM8(0x134) -+ -+#define RXCSBB _SFR_MEM8(0x135) -+ -+#define RXCILB _SFR_MEM8(0x136) -+ -+#define RXCIHB _SFR_MEM8(0x137) -+ -+#define RXCPLB _SFR_MEM8(0x138) -+ -+#define RXCPHB _SFR_MEM8(0x139) -+ -+#define RXDSB _SFR_MEM8(0x13A) -+ -+#define RXTLLA _SFR_MEM8(0x13B) -+ -+#define RXTLHA _SFR_MEM8(0x13C) -+#define RXTLHA0 0 -+#define RXTLHA1 1 -+#define RXTLHA2 2 -+#define RXTLHA3 3 -+ -+#define RXCRLA _SFR_MEM8(0x13D) -+ -+#define RXCRHA _SFR_MEM8(0x13E) -+ -+#define RXCSBA _SFR_MEM8(0x13F) -+ -+#define RXCILA _SFR_MEM8(0x140) -+ -+#define RXCIHA _SFR_MEM8(0x141) -+ -+#define RXCPLA _SFR_MEM8(0x142) -+ -+#define RXCPHA _SFR_MEM8(0x143) -+ -+#define RXDSA _SFR_MEM8(0x144) -+ -+#define CRCCR _SFR_MEM8(0x145) -+#define CRCRS 0 -+#define REFLI 1 -+#define REFLO 2 -+ -+#define CRCDOR _SFR_MEM8(0x146) -+ -+#define IDB0 _SFR_MEM8(0x147) -+ -+#define IDB1 _SFR_MEM8(0x148) -+ -+#define IDB2 _SFR_MEM8(0x149) -+ -+#define IDB3 _SFR_MEM8(0x14A) -+ -+#define IDC _SFR_MEM8(0x14B) -+#define IDL0 0 -+#define IDL1 1 -+#define IDBO0 2 -+#define IDBO1 3 -+#define IDFIM 5 -+#define IDCLR 6 -+#define IDCE 7 -+ -+#define IDS _SFR_MEM8(0x14C) -+#define IDOK 0 -+#define IDFULL 1 -+ -+#define RSSAV _SFR_MEM8(0x14D) -+ -+#define RSSPK _SFR_MEM8(0x14E) -+ -+#define RSSL _SFR_MEM8(0x14F) -+ -+#define RSSH _SFR_MEM8(0x150) -+ -+#define RSSC _SFR_MEM8(0x151) -+#define RSUP0 0 -+#define RSUP1 1 -+#define RSUP2 2 -+#define RSUP3 3 -+#define RSWLH 4 -+#define RSHRX 5 -+#define RSPKF 6 -+ -+#define DBCR _SFR_MEM8(0x152) -+#define DBMD 0 -+#define DBCS 1 -+#define DBTMS 2 -+#define DBHA 3 -+ -+#define DBTC _SFR_MEM8(0x153) -+ -+#define DBENB _SFR_MEM8(0x154) -+ -+#define DBENC _SFR_MEM8(0x155) -+ -+#define DBGSW _SFR_MEM8(0x156) -+#define DBGGS0 0 -+#define DBGGS1 1 -+#define DBGGS2 2 -+#define DBGGS3 3 -+#define CPBFOS0 4 -+#define CPBFOS1 5 -+#define CPBF 6 -+#define DBGSE 7 -+ -+#define SFFR _SFR_MEM8(0x157) -+#define RFL0 0 -+#define RFL1 1 -+#define RFL2 2 -+#define RFC 3 -+#define TFL0 4 -+#define TFL1 5 -+#define TFL2 6 -+#define TFC 7 -+ -+#define SFIR _SFR_MEM8(0x158) -+#define RIL0 0 -+#define RIL1 1 -+#define RIL2 2 -+#define SRIE 3 -+#define TIL0 4 -+#define TIL1 5 -+#define TIL2 6 -+#define STIE 7 -+ -+#define EECR2 _SFR_MEM8(0x159) -+#define EEBRE 0 -+ -+#define PGMST _SFR_MEM8(0x15A) -+#define PGMSYN0 0 -+#define PGMSYN1 1 -+#define PGMSYN2 2 -+#define PGMSYN3 3 -+#define PGMSYN4 4 -+ -+#define EEST _SFR_MEM8(0x15B) -+#define EESYN0 0 -+#define EESYN1 1 -+#define EESYN2 2 -+#define EESYN3 3 -+ -+#define RSIFG _SFR_MEM8(0x15C) -+ -+#define RSLDV _SFR_MEM8(0x15D) -+ -+#define RSHDV _SFR_MEM8(0x15E) -+ -+#define RSCOM _SFR_MEM8(0x15F) -+#define RSDC 0 -+#define RSIFC 1 -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCI0_vect _VECTOR(3) -+#define PCI0_vect_num 3 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCI1_vect _VECTOR(4) -+#define PCI1_vect_num 4 -+ -+/* Voltage Monitoring Interrupt */ -+#define VMON_vect _VECTOR(5) -+#define VMON_vect_num 5 -+ -+/* AVCC Reset Interrupt */ -+#define AVCCR_vect _VECTOR(6) -+#define AVCCR_vect_num 6 -+ -+/* AVCC Low Interrupt */ -+#define AVCCL_vect _VECTOR(7) -+#define AVCCL_vect_num 7 -+ -+/* Timer 0 Interval Interrupt */ -+#define T0INT_vect _VECTOR(8) -+#define T0INT_vect_num 8 -+ -+/* Timer/Counter1 Compare Match Interrupt */ -+#define T1COMP_vect _VECTOR(9) -+#define T1COMP_vect_num 9 -+ -+/* Timer/Counter1 Overflow Interrupt */ -+#define T1OVF_vect _VECTOR(10) -+#define T1OVF_vect_num 10 -+ -+/* Timer/Counter2 Compare Match Interrupt */ -+#define T2COMP_vect _VECTOR(11) -+#define T2COMP_vect_num 11 -+ -+/* Timer/Counter2 Overflow Interrupt */ -+#define T2OVF_vect _VECTOR(12) -+#define T2OVF_vect_num 12 -+ -+/* Timer/Counter3 Capture Event Interrupt */ -+#define T3CAP_vect _VECTOR(13) -+#define T3CAP_vect_num 13 -+ -+/* Timer/Counter3 Compare Match Interrupt */ -+#define T3COMP_vect _VECTOR(14) -+#define T3COMP_vect_num 14 -+ -+/* Timer/Counter3 Overflow Interrupt */ -+#define T3OVF_vect _VECTOR(15) -+#define T3OVF_vect_num 15 -+ -+/* Timer/Counter4 Capture Event Interrupt */ -+#define T4CAP_vect _VECTOR(16) -+#define T4CAP_vect_num 16 -+ -+/* Timer/Counter4 Compare Match Interrupt */ -+#define T4COMP_vect _VECTOR(17) -+#define T4COMP_vect_num 17 -+ -+/* Timer/Counter4 Overflow Interrupt */ -+#define T4OVF_vect _VECTOR(18) -+#define T4OVF_vect_num 18 -+ -+/* Timer/Counter5 Compare Match Interrupt */ -+#define T5COMP_vect _VECTOR(19) -+#define T5COMP_vect_num 19 -+ -+/* Timer/Counter5 Overflow Interrupt */ -+#define T5OVF_vect _VECTOR(20) -+#define T5OVF_vect_num 20 -+ -+/* SPI Serial Transfer Complete Interrupt */ -+#define SPI_vect _VECTOR(21) -+#define SPI_vect_num 21 -+ -+/* SPI Rx Buffer Interrupt */ -+#define SRX_FIFO_vect _VECTOR(22) -+#define SRX_FIFO_vect_num 22 -+ -+/* SPI Tx Buffer Interrupt */ -+#define STX_FIFO_vect _VECTOR(23) -+#define STX_FIFO_vect_num 23 -+ -+/* Sequencer State Machine Interrupt */ -+#define SSM_vect _VECTOR(24) -+#define SSM_vect_num 24 -+ -+/* Data FIFO fill level reached Interrupt */ -+#define DFFLR_vect _VECTOR(25) -+#define DFFLR_vect_num 25 -+ -+/* Data FIFO overflow or underflow error Interrupt */ -+#define DFOUE_vect _VECTOR(26) -+#define DFOUE_vect_num 26 -+ -+/* RSSI/Preamble FIFO fill level reached Interrupt */ -+#define SFFLR_vect _VECTOR(27) -+#define SFFLR_vect_num 27 -+ -+/* RSSI/Preamble FIFO overflow or underflow error Interrupt */ -+#define SFOUE_vect _VECTOR(28) -+#define SFOUE_vect_num 28 -+ -+/* Tx Modulator Telegram Finish Interrupt */ -+#define TMTCF_vect _VECTOR(29) -+#define TMTCF_vect_num 29 -+ -+/* UHF receiver wake up ok on Rx path B */ -+#define UHF_WCOB_vect _VECTOR(30) -+#define UHF_WCOB_vect_num 30 -+ -+/* UHF receiver wake up ok on Rx path A */ -+#define UHF_WCOA_vect _VECTOR(31) -+#define UHF_WCOA_vect_num 31 -+ -+/* UHF receiver start of telegram ok on Rx path B */ -+#define UHF_SOTB_vect _VECTOR(32) -+#define UHF_SOTB_vect_num 32 -+ -+/* UHF receiver start of telegram ok on Rx path A */ -+#define UHF_SOTA_vect _VECTOR(33) -+#define UHF_SOTA_vect_num 33 -+ -+/* UHF receiver end of telegram on Rx path B */ -+#define UHF_EOTB_vect _VECTOR(34) -+#define UHF_EOTB_vect_num 34 -+ -+/* UHF receiver end of telegram on Rx path A */ -+#define UHF_EOTA_vect _VECTOR(35) -+#define UHF_EOTA_vect_num 35 -+ -+/* UHF receiver new bit on Rx path B */ -+#define UHF_NBITB_vect _VECTOR(36) -+#define UHF_NBITB_vect_num 36 -+ -+/* UHF receiver new bit on Rx path A */ -+#define UHF_NBITA_vect _VECTOR(37) -+#define UHF_NBITA_vect_num 37 -+ -+/* External input Clock monitoring Interrupt */ -+#define EXCM_vect _VECTOR(38) -+#define EXCM_vect_num 38 -+ -+/* EEPROM Ready Interrupt */ -+#define ERDY_vect _VECTOR(39) -+#define ERDY_vect_num 39 -+ -+/* Store Program Memory Ready */ -+#define SPMR_vect _VECTOR(40) -+#define SPMR_vect_num 40 -+ -+/* IDSCAN Full Interrupt */ -+#define IDFULL_vect _VECTOR(41) -+#define IDFULL_vect_num 41 -+ -+#define _VECTORS_SIZE 168 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 64 -+#define FLASHSTART 0x8000 -+#define FLASHEND 0xCFFF -+#define RAMSTART 0x0200 -+#define RAMSIZE 1024 -+#define RAMEND 0x05FF -+#define E2START 0 -+#define E2SIZE 1152 -+#define E2PAGESIZE 16 -+#define E2END 0x047F -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 1 -+ -+/* Fuse Byte */ -+#define FUSE_CKDIV8 (unsigned char)~_BV(128) -+#define FUSE_DWEN (unsigned char)~_BV(64) -+#define FUSE_SPIEN (unsigned char)~_BV(32) -+#define FUSE_WDTON (unsigned char)~_BV(16) -+#define FUSE_EESAVE (unsigned char)~_BV(8) -+#define FUSE_BOOTRST (unsigned char)~_BV(4) -+#define FUSE_RSTDISBL (unsigned char)~_BV(2) -+#define FUSE_EXTCLKEN (unsigned char)~_BV(1) -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x95 -+#define SIGNATURE_2 0x61 -+ -+ -+#endif /* #ifdef _AVR_ATA5831_H_INCLUDED */ -+ -diff --git a/include/avr/ioa5832.h b/include/avr/ioa5832.h -new file mode 100644 -index 0000000..f24d046 ---- /dev/null -+++ b/include/avr/ioa5832.h -@@ -0,0 +1,1885 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATA5832_H_INCLUDED -+#define _AVR_ATA5832_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "ioa5832.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PRR0 _SFR_IO8(0x01) -+#define PRSPI 0 -+#define PRRXDC 1 -+#define PRTXDC 2 -+#define PRCRC 3 -+#define PRVM 4 -+#define PRCO 5 -+ -+#define PRR1 _SFR_IO8(0x02) -+#define PRT1 0 -+#define PRT2 1 -+#define PRT3 2 -+#define PRT4 3 -+#define PRT5 4 -+ -+#define PRR2 _SFR_IO8(0x03) -+#define PRXB 0 -+#define PRXA 1 -+#define PRSF 2 -+#define PRDF 3 -+#define PRIDS 4 -+#define PRRS 5 -+#define PRTM 6 -+#define PRSSM 7 -+ -+#define RDPR _SFR_IO8(0x04) -+#define PRPTB 0 -+#define PRPTA 1 -+#define PRFLT 2 -+#define PRTMP 3 -+#define APRPTB 4 -+#define APRPTA 5 -+#define ARDPRF 6 -+#define RDPRF 7 -+ -+#define PINB _SFR_IO8(0x05) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x06) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x07) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x08) -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x09) -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x0A) -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define FSCR _SFR_IO8(0x0B) -+#define TXMOD 0 -+#define SFM 1 -+#define TXMS0 2 -+#define TXMS1 3 -+#define PAOER 4 -+#define PAON 7 -+ -+/* Reserved [0x0C] */ -+ -+#define RDSIFR _SFR_IO8(0x0D) -+#define NBITA 0 -+#define NBITB 1 -+#define EOTA 2 -+#define EOTB 3 -+#define SOTA 4 -+#define SOTB 5 -+#define WCOA 6 -+#define WCOB 7 -+ -+#define MCUCR _SFR_IO8(0x0E) -+#define IVCE 0 -+#define IVSEL 1 -+#define SPIIO 2 -+#define ENPS 3 -+#define PUD 4 -+#define PB4HS 5 -+#define PB7LS 6 -+#define PB7HS 7 -+ -+#define PCIFR _SFR_IO8(0x0F) -+#define PCIF0 0 -+#define PCIF1 1 -+ -+#define T0CR _SFR_IO8(0x10) -+#define T0PS0 0 -+#define T0PS1 1 -+#define T0PS2 2 -+#define T0IE 3 -+#define T0PR 4 -+ -+#define T1CR _SFR_IO8(0x11) -+#define T1OTM 0 -+#define T1CTM 1 -+#define T1CRM 2 -+#define T1TOP 4 -+#define T1RES 5 -+#define T1TOS 6 -+#define T1ENA 7 -+ -+#define T2CR _SFR_IO8(0x12) -+#define T2OTM 0 -+#define T2CTM 1 -+#define T2CRM 2 -+#define T2TOP 4 -+#define T2RES 5 -+#define T2TOS 6 -+#define T2ENA 7 -+ -+#define T3CR _SFR_IO8(0x13) -+#define T3OTM 0 -+#define T3CTM 1 -+#define T3CRM 2 -+#define T3CPRM 3 -+#define T3TOP 4 -+#define T3RES 5 -+#define T3TOS 6 -+#define T3ENA 7 -+ -+#define T4CR _SFR_IO8(0x14) -+#define T4OTM 0 -+#define T4CTM 1 -+#define T4CRM 2 -+#define T4CPRM 3 -+#define T4TOP 4 -+#define T4RES 5 -+#define T4TOS 6 -+#define T4ENA 7 -+ -+#define T1IFR _SFR_IO8(0x15) -+#define T1OFF 0 -+#define T1COF 1 -+ -+#define T2IFR _SFR_IO8(0x16) -+#define T2OFF 0 -+#define T2COF 1 -+ -+#define T3IFR _SFR_IO8(0x17) -+#define T3OFF 0 -+#define T3COF 1 -+#define T3ICF 2 -+ -+#define T4IFR _SFR_IO8(0x18) -+#define T4OFF 0 -+#define T4COF 1 -+#define T4ICF 2 -+ -+#define T5IFR _SFR_IO8(0x19) -+#define T5OFF 0 -+#define T5COF 1 -+ -+#define GPIOR0 _SFR_IO8(0x1A) -+ -+#define GPIOR3 _SFR_IO8(0x1B) -+ -+#define GPIOR4 _SFR_IO8(0x1C) -+ -+#define GPIOR5 _SFR_IO8(0x1D) -+ -+#define GPIOR6 _SFR_IO8(0x1E) -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEWE 1 -+#define EEMWE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+#define EEPAGE 6 -+#define NVMBSY 7 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define EEPR _SFR_IO8(0x23) -+#define EEAP0 0 -+#define EEAP1 1 -+#define EEAP2 2 -+#define EEAP3 3 -+ -+#define GPIOR1 _SFR_IO8(0x24) -+ -+#define GPIOR2 _SFR_IO8(0x25) -+ -+#define PCICR _SFR_IO8(0x26) -+#define PCIE0 0 -+#define PCIE1 1 -+ -+#define EIMSK _SFR_IO8(0x27) -+#define INT0 0 -+#define INT1 1 -+ -+#define EIFR _SFR_IO8(0x28) -+#define INTF0 0 -+#define INTF1 1 -+ -+#define CRCDIR _SFR_IO8(0x29) -+ -+#define VMCSR _SFR_IO8(0x2A) -+#define VMLS0 0 -+#define VMLS1 1 -+#define VMLS2 2 -+#define VMLS3 3 -+#define VMIM 4 -+#define VMF 5 -+ -+#define MCUSR _SFR_IO8(0x2B) -+#define PORF 0 -+#define EXTRF 1 -+#define WDRF 3 -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define RXIF 4 -+#define TXIF 5 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+#define T0IFR _SFR_IO8(0x2F) -+#define T0F 0 -+ -+/* Reserved [0x30] */ -+ -+#define DWDR _SFR_IO8(0x31) -+ -+/* Reserved [0x32] */ -+ -+#define RDCR _SFR_IO8(0x33) -+#define RDPU 0 -+#define ADIVEN 1 -+#define RDEN 2 -+ -+#define EOTSA _SFR_IO8(0x34) -+#define CARFA 0 -+#define AMPFA 1 -+#define SYTFA 2 -+#define MANFA 3 -+#define TMOFA 4 -+#define TELRA 5 -+#define RRFA 6 -+#define EOTBF 7 -+ -+#define EOTCA _SFR_IO8(0x35) -+#define CARFEA 0 -+#define AMPFEA 1 -+#define SYTFEA 2 -+#define MANFEA 3 -+#define TMOFEA 4 -+#define TELREA 5 -+#define RRFEA 6 -+#define EOTBFE 7 -+ -+#define EOTSB _SFR_IO8(0x36) -+#define CARFB 0 -+#define AMPFB 1 -+#define SYTFB 2 -+#define MANFB 3 -+#define TMOFB 4 -+#define TELRB 5 -+#define RRFB 6 -+#define EOTAF 7 -+ -+#define EOTCB _SFR_IO8(0x37) -+#define CARFEB 0 -+#define AMPFEB 1 -+#define SYTFEB 2 -+#define MANFEB 3 -+#define TMOFEB 4 -+#define TELREB 5 -+#define RRFEB 6 -+#define EOTAFE 7 -+ -+#define SMCR _SFR_IO8(0x38) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define CMCR _SFR_IO8(0x39) -+#define CMM0 0 -+#define CMM1 1 -+#define CMM2 2 -+#define CCS 3 -+#define SRCD 4 -+#define CMONEN 6 -+#define CMCCE 7 -+ -+#define CMIMR _SFR_IO8(0x3A) -+#define ECIE 0 -+ -+#define CLPR _SFR_IO8(0x3B) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLTPS0 3 -+#define CLTPS1 4 -+#define CLTPS2 5 -+#define CLPCE 7 -+ -+#define SPMCSR _SFR_IO8(0x3C) -+#define SELFPRGEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define SPMIE 7 -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define FSEN _SFR_MEM8(0x60) -+#define SDPU 0 -+#define SDEN 1 -+#define GAEN 2 -+#define PEEN 3 -+#define ASEN 4 -+#define ANTT 5 -+ -+#define FSFCR _SFR_MEM8(0x61) -+#define BTSEL0 0 -+#define BTSEL1 1 -+#define ASDIV0 4 -+#define ASDIV1 5 -+#define ASDIV2 6 -+#define ASDIV3 7 -+ -+/* Combine GACDIVL and GACDIVH */ -+#define GACDIV _SFR_MEM16(0x62) -+ -+#define GACDIVL _SFR_MEM8(0x62) -+#define GACDIVH _SFR_MEM8(0x63) -+ -+#define FFREQ1L _SFR_MEM8(0x64) -+ -+#define FFREQ1M _SFR_MEM8(0x65) -+ -+#define FFREQ1H _SFR_MEM8(0x66) -+ -+#define FFREQ2L _SFR_MEM8(0x67) -+ -+#define FFREQ2M _SFR_MEM8(0x68) -+ -+#define FFREQ2H _SFR_MEM8(0x69) -+ -+/* Reserved [0x6A] */ -+ -+#define EICRA _SFR_MEM8(0x6B) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+ -+#define PCMSK0 _SFR_MEM8(0x6C) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6D) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+ -+#define WDTCR _SFR_MEM8(0x6E) -+#define WDPS0 0 -+#define WDPS1 1 -+#define WDPS2 2 -+#define WDE 3 -+#define WDCE 4 -+ -+#define T1CNT _SFR_MEM8(0x6F) -+ -+#define T1COR _SFR_MEM8(0x70) -+ -+#define T1MR _SFR_MEM8(0x71) -+#define T1CS0 0 -+#define T1CS1 1 -+#define T1PS0 2 -+#define T1PS1 3 -+#define T1PS2 4 -+#define T1PS3 5 -+#define T1DC0 6 -+#define T1DC1 7 -+ -+#define T1IMR _SFR_MEM8(0x72) -+#define T1OIM 0 -+#define T1CIM 1 -+ -+#define T2CNT _SFR_MEM8(0x73) -+ -+#define T2COR _SFR_MEM8(0x74) -+ -+#define T2MR _SFR_MEM8(0x75) -+#define T2CS0 0 -+#define T2CS1 1 -+#define T2PS0 2 -+#define T2PS1 3 -+#define T2PS2 4 -+#define T2PS3 5 -+#define T2DC0 6 -+#define T2DC1 7 -+ -+#define T2IMR _SFR_MEM8(0x76) -+#define T2OIM 0 -+#define T2CIM 1 -+ -+/* Combine T3CNTL and T3CNTH */ -+#define T3CNT _SFR_MEM16(0x77) -+ -+#define T3CNTL _SFR_MEM8(0x77) -+#define T3CNTH _SFR_MEM8(0x78) -+ -+/* Combine T3CORL and T3CORH */ -+#define T3COR _SFR_MEM16(0x79) -+ -+#define T3CORL _SFR_MEM8(0x79) -+#define T3CORH _SFR_MEM8(0x7A) -+ -+/* Combine T3ICRL and T3ICRH */ -+#define T3ICR _SFR_MEM16(0x7B) -+ -+#define T3ICRL _SFR_MEM8(0x7B) -+#define T3ICRH _SFR_MEM8(0x7C) -+ -+#define T3MRA _SFR_MEM8(0x7D) -+#define T3CS0 0 -+#define T3CS1 1 -+#define T3PS0 2 -+#define T3PS1 3 -+#define T3PS2 4 -+ -+#define T3MRB _SFR_MEM8(0x7E) -+#define T3SCE 1 -+#define T3CNC 2 -+#define T3CE0 3 -+#define T3CE1 4 -+#define T3ICS0 5 -+#define T3ICS1 6 -+#define T3ICS2 7 -+ -+#define T3IMR _SFR_MEM8(0x7F) -+#define T3OIM 0 -+#define T3CIM 1 -+#define T3CPIM 2 -+ -+/* Combine T4CNTL and T4CNTH */ -+#define T4CNT _SFR_MEM16(0x80) -+ -+#define T4CNTL _SFR_MEM8(0x80) -+#define T4CNTH _SFR_MEM8(0x81) -+ -+/* Combine T4CORL and T4CORH */ -+#define T4COR _SFR_MEM16(0x82) -+ -+#define T4CORL _SFR_MEM8(0x82) -+#define T4CORH _SFR_MEM8(0x83) -+ -+/* Combine T4ICRL and T4ICRH */ -+#define T4ICR _SFR_MEM16(0x84) -+ -+#define T4ICRL _SFR_MEM8(0x84) -+#define T4ICRH _SFR_MEM8(0x85) -+ -+#define T4MRA _SFR_MEM8(0x86) -+#define T4CS0 0 -+#define T4CS1 1 -+#define T4PS0 2 -+#define T4PS1 3 -+#define T4PS2 4 -+ -+#define T4MRB _SFR_MEM8(0x87) -+#define T4SCE 1 -+#define T4CNC 2 -+#define T4CE0 3 -+#define T4CE1 4 -+#define T4ICS0 5 -+#define T4ICS1 6 -+#define T4ICS2 7 -+ -+#define T4IMR _SFR_MEM8(0x88) -+#define T4OIM 0 -+#define T4CIM 1 -+#define T4CPIM 2 -+ -+/* Reserved [0x89] */ -+ -+/* Combine T5OCRL and T5OCRH */ -+#define T5OCR _SFR_MEM16(0x8A) -+ -+#define T5OCRL _SFR_MEM8(0x8A) -+#define T5OCRH _SFR_MEM8(0x8B) -+ -+#define T5CCR _SFR_MEM8(0x8C) -+#define T5CS0 0 -+#define T5CS1 1 -+#define T5CS2 2 -+#define T5CTC 3 -+ -+/* Combine T5CNTL and T5CNTH */ -+#define T5CNT _SFR_MEM16(0x8D) -+ -+#define T5CNTL _SFR_MEM8(0x8D) -+#define T5CNTH _SFR_MEM8(0x8E) -+ -+#define T5IMR _SFR_MEM8(0x8F) -+#define T5OIM 0 -+#define T5CIM 1 -+ -+#define GTCCR _SFR_MEM8(0x90) -+#define PSR10 0 -+#define TSM 7 -+ -+#define SOTSB _SFR_MEM8(0x91) -+#define CAROB 0 -+#define AMPOB 1 -+#define SYTOB 2 -+#define MANOB 3 -+#define WUPOB 4 -+#define SFIDOB 5 -+#define RROB 6 -+#define WCOAO 7 -+ -+#define SOTSA _SFR_MEM8(0x92) -+#define CAROA 0 -+#define AMPOA 1 -+#define SYTOA 2 -+#define MANOA 3 -+#define WUPOA 4 -+#define SFIDOA 5 -+#define RROA 6 -+#define WCOBO 7 -+ -+#define SOTCB _SFR_MEM8(0x93) -+#define CAROEB 0 -+#define AMPOEB 1 -+#define SYTOEB 2 -+#define MANOEB 3 -+#define WUPEB 4 -+#define SFIDEB 5 -+#define RROEB 6 -+#define WCOAOE 7 -+ -+#define SOTCA _SFR_MEM8(0x94) -+#define CAROEA 0 -+#define AMPOEA 1 -+#define SYTOEA 2 -+#define MANOEA 3 -+#define WUPEA 4 -+#define SFIDEA 5 -+#define RROEA 6 -+#define WCOBOE 7 -+ -+#define TESRB _SFR_MEM8(0x95) -+#define CRCOB 0 -+#define EOTLB0 1 -+#define EOTLB1 2 -+ -+#define TESRA _SFR_MEM8(0x96) -+#define CRCOA 0 -+#define EOTLA0 1 -+#define EOTLA1 2 -+ -+/* Reserved [0x97] */ -+ -+#define RDSIMR _SFR_MEM8(0x98) -+#define NBITAM 0 -+#define NBITBM 1 -+#define EOTAM 2 -+#define EOTBM 3 -+#define SOTAM 4 -+#define SOTBM 5 -+#define WCOAM 6 -+#define WCOBM 7 -+ -+#define RDOCR _SFR_MEM8(0x99) -+#define TMDS0 1 -+#define TMDS1 2 -+#define ETRPA 3 -+#define ETRPB 4 -+#define RDSIDA 5 -+#define RDSIDB 6 -+ -+/* Reserved [0x9A] */ -+ -+#define TEMPL _SFR_MEM8(0x9B) -+ -+#define TEMPH _SFR_MEM8(0x9C) -+ -+#define SYCB _SFR_MEM8(0x9D) -+#define SYCSB0 0 -+#define SYCSB1 1 -+#define SYCSB2 2 -+#define SYCSB3 3 -+#define SYTLB0 4 -+#define SYTLB1 5 -+#define SYTLB2 6 -+#define SYTLB3 7 -+ -+#define SYCA _SFR_MEM8(0x9E) -+#define SYCSA0 0 -+#define SYCSA1 1 -+#define SYCSA2 2 -+#define SYCSA3 3 -+#define SYTLA0 4 -+#define SYTLA1 5 -+#define SYTLA2 6 -+#define SYTLA3 7 -+ -+#define RXFOB _SFR_MEM8(0x9F) -+ -+#define RXFOA _SFR_MEM8(0xA0) -+ -+#define DMMB _SFR_MEM8(0xA1) -+#define DMATB0 0 -+#define DMATB1 1 -+#define DMATB2 2 -+#define DMATB3 3 -+#define DMATB4 4 -+#define DMPB 5 -+#define DMHB 6 -+#define DMNEB 7 -+ -+#define DMMA _SFR_MEM8(0xA2) -+#define DMATA0 0 -+#define DMATA1 1 -+#define DMATA2 2 -+#define DMATA3 3 -+#define DMATA4 4 -+#define DMPA 5 -+#define DMHA 6 -+#define DMNEA 7 -+ -+#define DMCDB _SFR_MEM8(0xA3) -+#define DMCLB0 0 -+#define DMCLB1 1 -+#define DMCLB2 2 -+#define DMCLB3 3 -+#define DMCLB4 4 -+#define DMCTB0 5 -+#define DMCTB1 6 -+#define DMCTB2 7 -+ -+#define DMCDA _SFR_MEM8(0xA4) -+#define DMCLA0 0 -+#define DMCLA1 1 -+#define DMCLA2 2 -+#define DMCLA3 3 -+#define DMCLA4 4 -+#define DMCTA0 5 -+#define DMCTA1 6 -+#define DMCTA2 7 -+ -+#define DMCRB _SFR_MEM8(0xA5) -+#define DMPGB0 0 -+#define DMPGB1 1 -+#define DMPGB2 2 -+#define DMPGB3 3 -+#define DMPGB4 4 -+#define SASKB 5 -+#define SY1TB 6 -+#define DMARB 7 -+ -+#define DMCRA _SFR_MEM8(0xA6) -+#define DMPGA0 0 -+#define DMPGA1 1 -+#define DMPGA2 2 -+#define DMPGA3 3 -+#define DMPGA4 4 -+#define SASKA 5 -+#define SY1TA 6 -+#define DMARA 7 -+ -+#define DMDRB _SFR_MEM8(0xA7) -+#define DMAB0 0 -+#define DMAB1 1 -+#define DMAB2 2 -+#define DMAB3 3 -+#define DMDNB0 4 -+#define DMDNB1 5 -+#define DMDNB2 6 -+#define DMDNB3 7 -+ -+#define DMDRA _SFR_MEM8(0xA8) -+#define DMAA0 0 -+#define DMAA1 1 -+#define DMAA2 2 -+#define DMAA3 3 -+#define DMDNA0 4 -+#define DMDNA1 5 -+#define DMDNA2 6 -+#define DMDNA3 7 -+ -+#define CHCR _SFR_MEM8(0xA9) -+#define BWM0 0 -+#define BWM1 1 -+#define BWM2 2 -+#define BWM3 3 -+ -+#define CHDN _SFR_MEM8(0xAA) -+#define BBDN0 0 -+#define BBDN1 1 -+#define BBDN2 2 -+#define BBDN3 3 -+#define BBDN4 4 -+#define ADCDN 5 -+ -+#define SFIDCB _SFR_MEM8(0xAB) -+#define SFIDTB0 0 -+#define SFIDTB1 1 -+#define SFIDTB2 2 -+#define SFIDTB3 3 -+#define SFIDTB4 4 -+#define SEMEB 7 -+ -+#define SFIDLB _SFR_MEM8(0xAC) -+#define SFIDLB0 0 -+#define SFIDLB1 1 -+#define SFIDLB2 2 -+#define SFIDLB3 3 -+#define SFIDLB4 4 -+#define SFIDLB5 5 -+ -+#define WUPTB _SFR_MEM8(0xAD) -+#define WUPTB0 0 -+#define WUPTB1 1 -+#define WUPTB2 2 -+#define WUPTB3 3 -+#define WUPTB4 4 -+ -+#define WUPLB _SFR_MEM8(0xAE) -+#define WUPLB0 0 -+#define WUPLB1 1 -+#define WUPLB2 2 -+#define WUPLB3 3 -+#define WUPLB4 4 -+#define WUPLB5 5 -+ -+#define SFID1B _SFR_MEM8(0xAF) -+ -+#define SFID2B _SFR_MEM8(0xB0) -+ -+#define SFID3B _SFR_MEM8(0xB1) -+ -+#define SFID4B _SFR_MEM8(0xB2) -+ -+#define WUP1B _SFR_MEM8(0xB3) -+ -+#define WUP2B _SFR_MEM8(0xB4) -+ -+#define WUP3B _SFR_MEM8(0xB5) -+ -+#define WUP4B _SFR_MEM8(0xB6) -+ -+#define SFIDCA _SFR_MEM8(0xB7) -+#define SFIDTA0 0 -+#define SFIDTA1 1 -+#define SFIDTA2 2 -+#define SFIDTA3 3 -+#define SFIDTA4 4 -+#define SEMEA 7 -+ -+#define SFIDLA _SFR_MEM8(0xB8) -+#define SFIDLA0 0 -+#define SFIDLA1 1 -+#define SFIDLA2 2 -+#define SFIDLA3 3 -+#define SFIDLA4 4 -+#define SFIDLA5 5 -+ -+#define WUPTA _SFR_MEM8(0xB9) -+#define WUPTA0 0 -+#define WUPTA1 1 -+#define WUPTA2 2 -+#define WUPTA3 3 -+#define WUPTA4 4 -+ -+#define WUPLA _SFR_MEM8(0xBA) -+#define WUPLA0 0 -+#define WUPLA1 1 -+#define WUPLA2 2 -+#define WUPLA3 3 -+#define WUPLA4 4 -+#define WUPLA5 5 -+ -+#define SFID1A _SFR_MEM8(0xBB) -+ -+#define SFID2A _SFR_MEM8(0xBC) -+ -+#define SFID3A _SFR_MEM8(0xBD) -+ -+#define SFID4A _SFR_MEM8(0xBE) -+ -+#define WUP1A _SFR_MEM8(0xBF) -+ -+#define WUP2A _SFR_MEM8(0xC0) -+ -+#define WUP3A _SFR_MEM8(0xC1) -+ -+#define WUP4A _SFR_MEM8(0xC2) -+ -+#define CLKOD _SFR_MEM8(0xC3) -+ -+#define CLKOCR _SFR_MEM8(0xC4) -+#define CLKOS0 0 -+#define CLKOS1 1 -+#define CLKOEN 2 -+ -+#define XFUSE _SFR_MEM8(0xC5) -+ -+#define SRCCAL _SFR_MEM8(0xC6) -+#define SRCCAL0 0 -+#define SRCCAL1 1 -+#define SRCCAL2 2 -+#define SRCCAL3 3 -+#define SRCCAL4 4 -+#define SRCCAL5 5 -+#define SRCTC0 6 -+#define SRCTC1 7 -+ -+#define FRCCAL _SFR_MEM8(0xC7) -+#define FRCCAL0 0 -+#define FRCCAL1 1 -+#define FRCCAL2 2 -+#define FRCCAL3 3 -+#define FRCCAL4 4 -+#define FRCTC 5 -+ -+#define CMSR _SFR_MEM8(0xC8) -+#define ECF 0 -+ -+#define CMOCR _SFR_MEM8(0xC9) -+#define FRCAO 0 -+#define SRCAO 1 -+#define FRCACT 2 -+#define SRCACT 3 -+ -+#define SUPFR _SFR_MEM8(0xCA) -+#define AVCCRF 0 -+#define AVCCLF 1 -+ -+#define SUPCR _SFR_MEM8(0xCB) -+#define AVCCRM 0 -+#define AVCCLM 1 -+#define PVEN 2 -+#define DVDIS 4 -+#define AVEN 5 -+#define AVDIC 6 -+ -+#define SUPCA1 _SFR_MEM8(0xCC) -+#define PV22 2 -+#define PVDIC 3 -+#define PVCAL0 4 -+#define PVCAL1 5 -+#define PVCAL2 6 -+#define PVCAL3 7 -+ -+#define SUPCA2 _SFR_MEM8(0xCD) -+#define BGCAL0 0 -+#define BGCAL1 1 -+#define BGCAL2 2 -+#define BGCAL3 3 -+ -+#define SUPCA3 _SFR_MEM8(0xCE) -+#define ACAL4 0 -+#define ACAL5 1 -+#define ACAL6 2 -+#define ACAL7 3 -+#define DCAL4 4 -+#define DCAL5 5 -+#define DCAL6 6 -+ -+#define SUPCA4 _SFR_MEM8(0xCF) -+#define ACAL0 0 -+#define ACAL1 1 -+#define ACAL2 2 -+#define ACAL3 3 -+#define DCAL0 4 -+#define DCAL1 5 -+#define DCAL2 6 -+#define DCAL3 7 -+ -+#define CALRDY _SFR_MEM8(0xD0) -+ -+#define VMCAL _SFR_MEM8(0xD1) -+#define VMCAL0 0 -+#define VMCAL1 1 -+#define VMCAL2 2 -+ -+#define DFS _SFR_MEM8(0xD2) -+#define DFFLRF 0 -+#define DFUFL 1 -+#define DFOFL 2 -+ -+/* Combine DFTLL and DFTLH */ -+#define DFTL _SFR_MEM16(0xD3) -+ -+#define DFTLL _SFR_MEM8(0xD3) -+#define DFTLH _SFR_MEM8(0xD4) -+ -+#define DFL _SFR_MEM8(0xD5) -+#define DFFLS0 0 -+#define DFFLS1 1 -+#define DFFLS2 2 -+#define DFFLS3 3 -+#define DFFLS4 4 -+#define DFFLS5 5 -+#define DFCLR 7 -+ -+#define DFWP _SFR_MEM8(0xD6) -+#define DFWP0 0 -+#define DFWP1 1 -+#define DFWP2 2 -+#define DFWP3 3 -+#define DFWP4 4 -+#define DFWP5 5 -+ -+#define DFRP _SFR_MEM8(0xD7) -+#define DFRP0 0 -+#define DFRP1 1 -+#define DFRP2 2 -+#define DFRP3 3 -+#define DFRP4 4 -+#define DFRP5 5 -+ -+#define DFD _SFR_MEM8(0xD8) -+ -+#define DFI _SFR_MEM8(0xD9) -+#define DFFLIM 0 -+#define DFERIM 1 -+ -+#define DFC _SFR_MEM8(0xDA) -+#define DFFLC0 0 -+#define DFFLC1 1 -+#define DFFLC2 2 -+#define DFFLC3 3 -+#define DFFLC4 4 -+#define DFFLC5 5 -+#define DFDRA 7 -+ -+#define SFS _SFR_MEM8(0xDB) -+#define SFFLRF 0 -+#define SFUFL 1 -+#define SFOFL 2 -+ -+#define SFL _SFR_MEM8(0xDC) -+#define SFFLS0 0 -+#define SFFLS1 1 -+#define SFFLS2 2 -+#define SFFLS3 3 -+#define SFFLS4 4 -+#define SFCLR 7 -+ -+#define SFWP _SFR_MEM8(0xDD) -+#define SFWP0 0 -+#define SFWP1 1 -+#define SFWP2 2 -+#define SFWP3 3 -+#define SFWP4 4 -+ -+#define SFRP _SFR_MEM8(0xDE) -+#define SFRP0 0 -+#define SFRP1 1 -+#define SFRP2 2 -+#define SFRP3 3 -+#define SFRP4 4 -+ -+#define SFD _SFR_MEM8(0xDF) -+ -+#define SFI _SFR_MEM8(0xE0) -+#define SFFLIM 0 -+#define SFERIM 1 -+ -+#define SFC _SFR_MEM8(0xE1) -+#define SFFLC0 0 -+#define SFFLC1 1 -+#define SFFLC2 2 -+#define SFFLC3 3 -+#define SFFLC4 4 -+#define SFDRA 7 -+ -+#define SSMCR _SFR_MEM8(0xE2) -+#define SSMTX 0 -+#define SSMTM 1 -+#define SSMTGE 2 -+#define SSMTPE 3 -+#define SSMPVE 4 -+#define SSMTAE 5 -+#define SETRPA 6 -+#define SETRPB 7 -+ -+#define SSMRCR _SFR_MEM8(0xE3) -+#define SSMPA 0 -+#define SSMPB 1 -+#define SSMADA 2 -+#define SSMADB 3 -+#define SSMPVS 4 -+#define SSMIFA 5 -+#define SSMIDSE 6 -+#define SSMTMOE 7 -+ -+#define SSMFBR _SFR_MEM8(0xE4) -+#define SSMFID0 0 -+#define SSMFID1 1 -+#define SSMFID2 2 -+#define SSMDFDT 3 -+#define SSMHADT 4 -+#define SSMPLDT 5 -+ -+#define SSMRR _SFR_MEM8(0xE5) -+#define SSMR 0 -+#define SSMST 1 -+ -+#define SSMSR _SFR_MEM8(0xE6) -+#define SSMESM0 0 -+#define SSMESM1 1 -+#define SSMESM2 2 -+#define SSMESM3 3 -+#define SSMERR 7 -+ -+#define SSMIFR _SFR_MEM8(0xE7) -+#define SSMIF 0 -+ -+#define SSMIMR _SFR_MEM8(0xE8) -+#define SSMIM 0 -+ -+#define MSMSTR _SFR_MEM8(0xE9) -+#define SSMMST0 0 -+#define SSMMST1 1 -+#define SSMMST2 2 -+#define SSMMST3 3 -+#define SSMMST4 4 -+ -+#define SSMSTR _SFR_MEM8(0xEA) -+#define SSMSTA0 0 -+#define SSMSTA1 1 -+#define SSMSTA2 2 -+#define SSMSTA3 3 -+#define SSMSTA4 4 -+#define SSMSTA5 5 -+ -+#define SSMXSR _SFR_MEM8(0xEB) -+#define SSMSTB0 0 -+#define SSMSTB1 1 -+#define SSMSTB2 2 -+#define SSMSTB3 3 -+#define SSMSTB4 4 -+#define SSMSTB5 5 -+ -+#define MSMCR1 _SFR_MEM8(0xEC) -+#define MSMSM00 0 -+#define MSMSM01 1 -+#define MSMSM02 2 -+#define MSMSM03 3 -+#define MSMSM10 4 -+#define MSMSM11 5 -+#define MSMSM12 6 -+#define MSMSM13 7 -+ -+#define MSMCR2 _SFR_MEM8(0xED) -+#define MSMSM20 0 -+#define MSMSM21 1 -+#define MSMSM22 2 -+#define MSMSM23 3 -+#define MSMSM30 4 -+#define MSMSM31 5 -+#define MSMSM32 6 -+#define MSMSM33 7 -+ -+#define MSMCR3 _SFR_MEM8(0xEE) -+#define MSMSM40 0 -+#define MSMSM41 1 -+#define MSMSM42 2 -+#define MSMSM43 3 -+#define MSMSM50 4 -+#define MSMSM51 5 -+#define MSMSM52 6 -+#define MSMSM53 7 -+ -+#define MSMCR4 _SFR_MEM8(0xEF) -+#define MSMSM60 0 -+#define MSMSM61 1 -+#define MSMSM62 2 -+#define MSMSM63 3 -+#define MSMSM70 4 -+#define MSMSM71 5 -+#define MSMSM72 6 -+#define MSMSM73 7 -+ -+#define GTCR _SFR_MEM8(0xF0) -+#define RXTEHA 0 -+#define GAPMA 1 -+#define DARA 2 -+#define IWUPA 3 -+#define RXTEHB 4 -+#define GAPMB 5 -+#define DARB 6 -+#define IWUPB 7 -+ -+#define SOTC1A _SFR_MEM8(0xF1) -+#define CAROEA1 0 -+#define AMPOEA1 1 -+#define SYTOEA1 2 -+#define MANOEA1 3 -+#define WUPEA1 4 -+#define SFIDEA1 5 -+#define RROEA1 6 -+#define WCOBOE1 7 -+ -+#define SOTC2A _SFR_MEM8(0xF2) -+#define CAROEA2 0 -+#define AMPOEA2 1 -+#define SYTOEA2 2 -+#define MANOEA2 3 -+#define WUPEA2 4 -+#define SFIDEA2 5 -+#define RROEA2 6 -+#define WCOBOE2 7 -+ -+#define SOTC1B _SFR_MEM8(0xF3) -+#define CAROEB1 0 -+#define AMPOEB1 1 -+#define SYTOEB1 2 -+#define MANOEB1 3 -+#define WUPEB1 4 -+#define SFIDEB1 5 -+#define RROEB1 6 -+#define WCOAOE1 7 -+ -+#define SOTC2B _SFR_MEM8(0xF4) -+#define CAROEB2 0 -+#define AMPOEB2 1 -+#define SYTOEB2 2 -+#define MANOEB2 3 -+#define WUPEB2 4 -+#define SFIDEB2 5 -+#define RROEB2 6 -+#define WCOAOE2 7 -+ -+#define EOTC1A _SFR_MEM8(0xF5) -+#define CARFEA1 0 -+#define AMPFEA1 1 -+#define SYTFEA1 2 -+#define MANFEA1 3 -+#define TMOFEA1 4 -+#define TELREA1 5 -+#define RRFEA1 6 -+#define EOTBFE1 7 -+ -+#define EOTC2A _SFR_MEM8(0xF6) -+#define CARFEA2 0 -+#define AMPFEA2 1 -+#define SYTFEA2 2 -+#define MANFEA2 3 -+#define TMOFEA2 4 -+#define TELREA2 5 -+#define RRFEA2 6 -+#define EOTBFE2 7 -+ -+#define EOTC3A _SFR_MEM8(0xF7) -+#define CARFEA3 0 -+#define AMPFEA3 1 -+#define SYTFEA3 2 -+#define MANFEA3 3 -+#define TMOFEA3 4 -+#define TELREA3 5 -+#define RRFEA3 6 -+#define EOTBFE3 7 -+ -+#define EOTC1B _SFR_MEM8(0xF8) -+#define CARFEB1 0 -+#define AMPFEB1 1 -+#define SYTFEB1 2 -+#define MANFEB1 3 -+#define TMOFEB1 4 -+#define TELREB1 5 -+#define RRFEB1 6 -+#define EOTAFE1 7 -+ -+#define EOTC2B _SFR_MEM8(0xF9) -+#define CARFEB2 0 -+#define AMPFEB2 1 -+#define SYTFEB2 2 -+#define MANFEB2 3 -+#define TMOFEB2 4 -+#define TELREB2 5 -+#define RRFEB2 6 -+#define EOTAFE2 7 -+ -+#define EOTC3B _SFR_MEM8(0xFA) -+#define CARFEB3 0 -+#define AMPFEB3 1 -+#define SYTFEB3 2 -+#define MANFEB3 3 -+#define TMOFEB3 4 -+#define TELREB3 5 -+#define RRFEB3 6 -+#define EOTAFE3 7 -+ -+#define WCOTOA _SFR_MEM8(0xFB) -+ -+#define WCOTOB _SFR_MEM8(0xFC) -+ -+#define SOTTOA _SFR_MEM8(0xFD) -+ -+#define SOTTOB _SFR_MEM8(0xFE) -+ -+#define SSMFCR _SFR_MEM8(0xFF) -+#define SSMIDSO 0 -+#define SSMIDSF 1 -+ -+#define FESR _SFR_MEM8(0x100) -+#define LBSAT 0 -+#define HBSAT 1 -+#define XRDY 2 -+#define PLCK 3 -+#define ANTS 4 -+ -+#define FEEN1 _SFR_MEM8(0x101) -+#define PLEN 0 -+#define PLCAL 1 -+#define XTOEN 2 -+#define LNAEN 3 -+#define ADEN 4 -+#define ADCLK 5 -+#define PLSP1 6 -+#define ATEN 7 -+ -+#define FEEN2 _SFR_MEM8(0x102) -+#define SDRX 0 -+#define SDTX 1 -+#define PAEN 2 -+#define TMPM 3 -+#define PLPEN 4 -+#define XTPEN 5 -+#define CPBIA 6 -+ -+#define FELNA _SFR_MEM8(0x103) -+#define LBH0 0 -+#define LBH1 1 -+#define LBH2 2 -+#define LBH3 3 -+#define LBL0 4 -+#define LBL1 5 -+#define LBL2 6 -+#define LBL3 7 -+ -+#define FEAT _SFR_MEM8(0x104) -+#define ANTN0 0 -+#define ANTN1 1 -+#define ANTN2 2 -+#define ANTN3 3 -+ -+#define FEPAC _SFR_MEM8(0x105) -+ -+#define FEVCT _SFR_MEM8(0x106) -+#define FEVCT0 0 -+#define FEVCT1 1 -+#define FEVCT2 2 -+#define FEVCT3 3 -+ -+#define FEBT _SFR_MEM8(0x107) -+#define CTN20 0 -+#define CTN21 1 -+#define RTN20 2 -+#define RTN21 3 -+ -+#define FEMS _SFR_MEM8(0x108) -+#define PLLS0 0 -+#define PLLS1 1 -+#define PLLS2 2 -+#define PLLS3 3 -+#define PLLM0 4 -+#define PLLM1 5 -+#define PLLM2 6 -+#define PLLM3 7 -+ -+#define FETN4 _SFR_MEM8(0x109) -+#define CTN40 0 -+#define CTN41 1 -+#define CTN42 2 -+#define CTN43 3 -+#define RTN40 4 -+#define RTN41 5 -+#define RTN42 6 -+#define RTN43 7 -+ -+#define FECR _SFR_MEM8(0x10A) -+#define LBNHB 0 -+#define S4N3 1 -+#define ANDP 2 -+#define ADHS 3 -+#define PLCKG 4 -+#define ANPS 5 -+ -+#define FEVCO _SFR_MEM8(0x10B) -+#define CPCC0 0 -+#define CPCC1 1 -+#define CPCC2 2 -+#define CPCC3 3 -+#define VCOB0 4 -+#define VCOB1 5 -+#define VCOB2 6 -+#define VCOB3 7 -+ -+#define FEALR _SFR_MEM8(0x10C) -+#define RNGE0 0 -+#define RNGE1 1 -+ -+#define FEANT _SFR_MEM8(0x10D) -+#define LVLC0 0 -+#define LVLC1 1 -+#define LVLC2 2 -+#define LVLC3 3 -+ -+#define FEBIA _SFR_MEM8(0x10E) -+#define IFAEN 7 -+ -+/* Reserved [0x10F..0x11F] */ -+ -+#define TMFSM _SFR_MEM8(0x120) -+#define TMSSM0 0 -+#define TMSSM1 1 -+#define TMSSM2 2 -+#define TMSSM3 3 -+#define TMMSM0 4 -+#define TMMSM1 5 -+#define TMMSM2 6 -+ -+/* Combine TMCRL and TMCRH */ -+#define TMCR _SFR_MEM16(0x121) -+ -+#define TMCRL _SFR_MEM8(0x121) -+#define TMCRH _SFR_MEM8(0x122) -+ -+#define TMCSB _SFR_MEM8(0x123) -+ -+/* Combine TMCIL and TMCIH */ -+#define TMCI _SFR_MEM16(0x124) -+ -+#define TMCIL _SFR_MEM8(0x124) -+#define TMCIH _SFR_MEM8(0x125) -+ -+/* Combine TMCPL and TMCPH */ -+#define TMCP _SFR_MEM16(0x126) -+ -+#define TMCPL _SFR_MEM8(0x126) -+#define TMCPH _SFR_MEM8(0x127) -+ -+#define TMSHR _SFR_MEM8(0x128) -+ -+/* Combine TMTLL and TMTLH */ -+#define TMTL _SFR_MEM16(0x129) -+ -+#define TMTLL _SFR_MEM8(0x129) -+#define TMTLH _SFR_MEM8(0x12A) -+ -+#define TMSSC _SFR_MEM8(0x12B) -+#define TMSSP0 0 -+#define TMSSP1 1 -+#define TMSSP2 2 -+#define TMSSP3 3 -+#define TMSSL0 4 -+#define TMSSL1 5 -+#define TMSSL2 6 -+#define TMSSH 7 -+ -+#define TMSR _SFR_MEM8(0x12C) -+#define TMTCF 0 -+ -+#define TMCR2 _SFR_MEM8(0x12D) -+#define TMCRCE 0 -+#define TMCRCL0 1 -+#define TMCRCL1 2 -+#define TMNRZE 3 -+#define TMPOL 4 -+#define TMSSE 5 -+#define TMMSB 6 -+ -+#define TMCR1 _SFR_MEM8(0x12E) -+#define TMPIS0 0 -+#define TMPIS1 1 -+#define TMPIS2 2 -+#define TMSCS 3 -+#define TMCIM 4 -+ -+#define RXBC1 _SFR_MEM8(0x12F) -+#define RXCEA 0 -+#define RXCBLA0 1 -+#define RXCBLA1 2 -+#define RXMSBA 3 -+#define RXCEB 4 -+#define RXCBLB0 5 -+#define RXCBLB1 6 -+#define RXMSBB 7 -+ -+#define RXBC2 _SFR_MEM8(0x130) -+#define RXBPB 0 -+#define RXBF 1 -+#define RXBCLR 2 -+ -+#define RXTLLB _SFR_MEM8(0x131) -+ -+#define RXTLHB _SFR_MEM8(0x132) -+#define RXTLHB0 0 -+#define RXTLHB1 1 -+#define RXTLHB2 2 -+#define RXTLHB3 3 -+ -+#define RXCRLB _SFR_MEM8(0x133) -+ -+#define RXCRHB _SFR_MEM8(0x134) -+ -+#define RXCSBB _SFR_MEM8(0x135) -+ -+#define RXCILB _SFR_MEM8(0x136) -+ -+#define RXCIHB _SFR_MEM8(0x137) -+ -+#define RXCPLB _SFR_MEM8(0x138) -+ -+#define RXCPHB _SFR_MEM8(0x139) -+ -+#define RXDSB _SFR_MEM8(0x13A) -+ -+#define RXTLLA _SFR_MEM8(0x13B) -+ -+#define RXTLHA _SFR_MEM8(0x13C) -+#define RXTLHA0 0 -+#define RXTLHA1 1 -+#define RXTLHA2 2 -+#define RXTLHA3 3 -+ -+#define RXCRLA _SFR_MEM8(0x13D) -+ -+#define RXCRHA _SFR_MEM8(0x13E) -+ -+#define RXCSBA _SFR_MEM8(0x13F) -+ -+#define RXCILA _SFR_MEM8(0x140) -+ -+#define RXCIHA _SFR_MEM8(0x141) -+ -+#define RXCPLA _SFR_MEM8(0x142) -+ -+#define RXCPHA _SFR_MEM8(0x143) -+ -+#define RXDSA _SFR_MEM8(0x144) -+ -+#define CRCCR _SFR_MEM8(0x145) -+#define CRCRS 0 -+#define REFLI 1 -+#define REFLO 2 -+ -+#define CRCDOR _SFR_MEM8(0x146) -+ -+#define IDB0 _SFR_MEM8(0x147) -+ -+#define IDB1 _SFR_MEM8(0x148) -+ -+#define IDB2 _SFR_MEM8(0x149) -+ -+#define IDB3 _SFR_MEM8(0x14A) -+ -+#define IDC _SFR_MEM8(0x14B) -+#define IDL0 0 -+#define IDL1 1 -+#define IDBO0 2 -+#define IDBO1 3 -+#define IDFIM 5 -+#define IDCLR 6 -+#define IDCE 7 -+ -+#define IDS _SFR_MEM8(0x14C) -+#define IDOK 0 -+#define IDFULL 1 -+ -+#define RSSAV _SFR_MEM8(0x14D) -+ -+#define RSSPK _SFR_MEM8(0x14E) -+ -+#define RSSL _SFR_MEM8(0x14F) -+ -+#define RSSH _SFR_MEM8(0x150) -+ -+#define RSSC _SFR_MEM8(0x151) -+#define RSUP0 0 -+#define RSUP1 1 -+#define RSUP2 2 -+#define RSUP3 3 -+#define RSWLH 4 -+#define RSHRX 5 -+#define RSPKF 6 -+ -+#define DBCR _SFR_MEM8(0x152) -+#define DBMD 0 -+#define DBCS 1 -+#define DBTMS 2 -+#define DBHA 3 -+ -+#define DBTC _SFR_MEM8(0x153) -+ -+#define DBENB _SFR_MEM8(0x154) -+ -+#define DBENC _SFR_MEM8(0x155) -+ -+#define DBGSW _SFR_MEM8(0x156) -+#define DBGGS0 0 -+#define DBGGS1 1 -+#define DBGGS2 2 -+#define DBGGS3 3 -+#define CPBFOS0 4 -+#define CPBFOS1 5 -+#define CPBF 6 -+#define DBGSE 7 -+ -+#define SFFR _SFR_MEM8(0x157) -+#define RFL0 0 -+#define RFL1 1 -+#define RFL2 2 -+#define RFC 3 -+#define TFL0 4 -+#define TFL1 5 -+#define TFL2 6 -+#define TFC 7 -+ -+#define SFIR _SFR_MEM8(0x158) -+#define RIL0 0 -+#define RIL1 1 -+#define RIL2 2 -+#define SRIE 3 -+#define TIL0 4 -+#define TIL1 5 -+#define TIL2 6 -+#define STIE 7 -+ -+#define EECR2 _SFR_MEM8(0x159) -+#define EEBRE 0 -+ -+#define PGMST _SFR_MEM8(0x15A) -+#define PGMSYN0 0 -+#define PGMSYN1 1 -+#define PGMSYN2 2 -+#define PGMSYN3 3 -+#define PGMSYN4 4 -+ -+#define EEST _SFR_MEM8(0x15B) -+#define EESYN0 0 -+#define EESYN1 1 -+#define EESYN2 2 -+#define EESYN3 3 -+ -+#define RSIFG _SFR_MEM8(0x15C) -+ -+#define RSLDV _SFR_MEM8(0x15D) -+ -+#define RSHDV _SFR_MEM8(0x15E) -+ -+#define RSCOM _SFR_MEM8(0x15F) -+#define RSDC 0 -+#define RSIFC 1 -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCI0_vect _VECTOR(3) -+#define PCI0_vect_num 3 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCI1_vect _VECTOR(4) -+#define PCI1_vect_num 4 -+ -+/* Voltage Monitoring Interrupt */ -+#define VMON_vect _VECTOR(5) -+#define VMON_vect_num 5 -+ -+/* AVCC Reset Interrupt */ -+#define AVCCR_vect _VECTOR(6) -+#define AVCCR_vect_num 6 -+ -+/* AVCC Low Interrupt */ -+#define AVCCL_vect _VECTOR(7) -+#define AVCCL_vect_num 7 -+ -+/* Timer 0 Interval Interrupt */ -+#define T0INT_vect _VECTOR(8) -+#define T0INT_vect_num 8 -+ -+/* Timer/Counter1 Compare Match Interrupt */ -+#define T1COMP_vect _VECTOR(9) -+#define T1COMP_vect_num 9 -+ -+/* Timer/Counter1 Overflow Interrupt */ -+#define T1OVF_vect _VECTOR(10) -+#define T1OVF_vect_num 10 -+ -+/* Timer/Counter2 Compare Match Interrupt */ -+#define T2COMP_vect _VECTOR(11) -+#define T2COMP_vect_num 11 -+ -+/* Timer/Counter2 Overflow Interrupt */ -+#define T2OVF_vect _VECTOR(12) -+#define T2OVF_vect_num 12 -+ -+/* Timer/Counter3 Capture Event Interrupt */ -+#define T3CAP_vect _VECTOR(13) -+#define T3CAP_vect_num 13 -+ -+/* Timer/Counter3 Compare Match Interrupt */ -+#define T3COMP_vect _VECTOR(14) -+#define T3COMP_vect_num 14 -+ -+/* Timer/Counter3 Overflow Interrupt */ -+#define T3OVF_vect _VECTOR(15) -+#define T3OVF_vect_num 15 -+ -+/* Timer/Counter4 Capture Event Interrupt */ -+#define T4CAP_vect _VECTOR(16) -+#define T4CAP_vect_num 16 -+ -+/* Timer/Counter4 Compare Match Interrupt */ -+#define T4COMP_vect _VECTOR(17) -+#define T4COMP_vect_num 17 -+ -+/* Timer/Counter4 Overflow Interrupt */ -+#define T4OVF_vect _VECTOR(18) -+#define T4OVF_vect_num 18 -+ -+/* Timer/Counter5 Compare Match Interrupt */ -+#define T5COMP_vect _VECTOR(19) -+#define T5COMP_vect_num 19 -+ -+/* Timer/Counter5 Overflow Interrupt */ -+#define T5OVF_vect _VECTOR(20) -+#define T5OVF_vect_num 20 -+ -+/* SPI Serial Transfer Complete Interrupt */ -+#define SPI_vect _VECTOR(21) -+#define SPI_vect_num 21 -+ -+/* SPI Rx Buffer Interrupt */ -+#define SRX_FIFO_vect _VECTOR(22) -+#define SRX_FIFO_vect_num 22 -+ -+/* SPI Tx Buffer Interrupt */ -+#define STX_FIFO_vect _VECTOR(23) -+#define STX_FIFO_vect_num 23 -+ -+/* Sequencer State Machine Interrupt */ -+#define SSM_vect _VECTOR(24) -+#define SSM_vect_num 24 -+ -+/* Data FIFO fill level reached Interrupt */ -+#define DFFLR_vect _VECTOR(25) -+#define DFFLR_vect_num 25 -+ -+/* Data FIFO overflow or underflow error Interrupt */ -+#define DFOUE_vect _VECTOR(26) -+#define DFOUE_vect_num 26 -+ -+/* RSSI/Preamble FIFO fill level reached Interrupt */ -+#define SFFLR_vect _VECTOR(27) -+#define SFFLR_vect_num 27 -+ -+/* RSSI/Preamble FIFO overflow or underflow error Interrupt */ -+#define SFOUE_vect _VECTOR(28) -+#define SFOUE_vect_num 28 -+ -+/* Tx Modulator Telegram Finish Interrupt */ -+#define TMTCF_vect _VECTOR(29) -+#define TMTCF_vect_num 29 -+ -+/* UHF receiver wake up ok on Rx path B */ -+#define UHF_WCOB_vect _VECTOR(30) -+#define UHF_WCOB_vect_num 30 -+ -+/* UHF receiver wake up ok on Rx path A */ -+#define UHF_WCOA_vect _VECTOR(31) -+#define UHF_WCOA_vect_num 31 -+ -+/* UHF receiver start of telegram ok on Rx path B */ -+#define UHF_SOTB_vect _VECTOR(32) -+#define UHF_SOTB_vect_num 32 -+ -+/* UHF receiver start of telegram ok on Rx path A */ -+#define UHF_SOTA_vect _VECTOR(33) -+#define UHF_SOTA_vect_num 33 -+ -+/* UHF receiver end of telegram on Rx path B */ -+#define UHF_EOTB_vect _VECTOR(34) -+#define UHF_EOTB_vect_num 34 -+ -+/* UHF receiver end of telegram on Rx path A */ -+#define UHF_EOTA_vect _VECTOR(35) -+#define UHF_EOTA_vect_num 35 -+ -+/* UHF receiver new bit on Rx path B */ -+#define UHF_NBITB_vect _VECTOR(36) -+#define UHF_NBITB_vect_num 36 -+ -+/* UHF receiver new bit on Rx path A */ -+#define UHF_NBITA_vect _VECTOR(37) -+#define UHF_NBITA_vect_num 37 -+ -+/* External input Clock monitoring Interrupt */ -+#define EXCM_vect _VECTOR(38) -+#define EXCM_vect_num 38 -+ -+/* EEPROM Ready Interrupt */ -+#define ERDY_vect _VECTOR(39) -+#define ERDY_vect_num 39 -+ -+/* Store Program Memory Ready */ -+#define SPMR_vect _VECTOR(40) -+#define SPMR_vect_num 40 -+ -+/* IDSCAN Full Interrupt */ -+#define IDFULL_vect _VECTOR(41) -+#define IDFULL_vect_num 41 -+ -+#define _VECTORS_SIZE 168 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 64 -+#define FLASHSTART 0x8000 -+#define FLASHEND 0xCFFF -+#define RAMSTART 0x0200 -+#define RAMSIZE 1024 -+#define RAMEND 0x05FF -+#define E2START 0 -+#define E2SIZE 1152 -+#define E2PAGESIZE 16 -+#define E2END 0x047F -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 1 -+ -+/* Fuse Byte */ -+#define FUSE_CKDIV8 (unsigned char)~_BV(128) -+#define FUSE_DWEN (unsigned char)~_BV(64) -+#define FUSE_SPIEN (unsigned char)~_BV(32) -+#define FUSE_WDTON (unsigned char)~_BV(16) -+#define FUSE_EESAVE (unsigned char)~_BV(8) -+#define FUSE_BOOTRST (unsigned char)~_BV(4) -+#define FUSE_RSTDISBL (unsigned char)~_BV(2) -+#define FUSE_EXTCLKEN (unsigned char)~_BV(1) -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x95 -+#define SIGNATURE_2 0x62 -+ -+ -+#endif /* #ifdef _AVR_ATA5832_H_INCLUDED */ -+ -diff --git a/include/avr/ioa5833.h b/include/avr/ioa5833.h -new file mode 100644 -index 0000000..d66615d ---- /dev/null -+++ b/include/avr/ioa5833.h -@@ -0,0 +1,1885 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATA5833_H_INCLUDED -+#define _AVR_ATA5833_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "ioa5833.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PRR0 _SFR_IO8(0x01) -+#define PRSPI 0 -+#define PRRXDC 1 -+#define PRTXDC 2 -+#define PRCRC 3 -+#define PRVM 4 -+#define PRCO 5 -+ -+#define PRR1 _SFR_IO8(0x02) -+#define PRT1 0 -+#define PRT2 1 -+#define PRT3 2 -+#define PRT4 3 -+#define PRT5 4 -+ -+#define PRR2 _SFR_IO8(0x03) -+#define PRXB 0 -+#define PRXA 1 -+#define PRSF 2 -+#define PRDF 3 -+#define PRIDS 4 -+#define PRRS 5 -+#define PRTM 6 -+#define PRSSM 7 -+ -+#define RDPR _SFR_IO8(0x04) -+#define PRPTB 0 -+#define PRPTA 1 -+#define PRFLT 2 -+#define PRTMP 3 -+#define APRPTB 4 -+#define APRPTA 5 -+#define ARDPRF 6 -+#define RDPRF 7 -+ -+#define PINB _SFR_IO8(0x05) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x06) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x07) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x08) -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x09) -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x0A) -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define FSCR _SFR_IO8(0x0B) -+#define TXMOD 0 -+#define SFM 1 -+#define TXMS0 2 -+#define TXMS1 3 -+#define PAOER 4 -+#define PAON 7 -+ -+/* Reserved [0x0C] */ -+ -+#define RDSIFR _SFR_IO8(0x0D) -+#define NBITA 0 -+#define NBITB 1 -+#define EOTA 2 -+#define EOTB 3 -+#define SOTA 4 -+#define SOTB 5 -+#define WCOA 6 -+#define WCOB 7 -+ -+#define MCUCR _SFR_IO8(0x0E) -+#define IVCE 0 -+#define IVSEL 1 -+#define SPIIO 2 -+#define ENPS 3 -+#define PUD 4 -+#define PB4HS 5 -+#define PB7LS 6 -+#define PB7HS 7 -+ -+#define PCIFR _SFR_IO8(0x0F) -+#define PCIF0 0 -+#define PCIF1 1 -+ -+#define T0CR _SFR_IO8(0x10) -+#define T0PS0 0 -+#define T0PS1 1 -+#define T0PS2 2 -+#define T0IE 3 -+#define T0PR 4 -+ -+#define T1CR _SFR_IO8(0x11) -+#define T1OTM 0 -+#define T1CTM 1 -+#define T1CRM 2 -+#define T1TOP 4 -+#define T1RES 5 -+#define T1TOS 6 -+#define T1ENA 7 -+ -+#define T2CR _SFR_IO8(0x12) -+#define T2OTM 0 -+#define T2CTM 1 -+#define T2CRM 2 -+#define T2TOP 4 -+#define T2RES 5 -+#define T2TOS 6 -+#define T2ENA 7 -+ -+#define T3CR _SFR_IO8(0x13) -+#define T3OTM 0 -+#define T3CTM 1 -+#define T3CRM 2 -+#define T3CPRM 3 -+#define T3TOP 4 -+#define T3RES 5 -+#define T3TOS 6 -+#define T3ENA 7 -+ -+#define T4CR _SFR_IO8(0x14) -+#define T4OTM 0 -+#define T4CTM 1 -+#define T4CRM 2 -+#define T4CPRM 3 -+#define T4TOP 4 -+#define T4RES 5 -+#define T4TOS 6 -+#define T4ENA 7 -+ -+#define T1IFR _SFR_IO8(0x15) -+#define T1OFF 0 -+#define T1COF 1 -+ -+#define T2IFR _SFR_IO8(0x16) -+#define T2OFF 0 -+#define T2COF 1 -+ -+#define T3IFR _SFR_IO8(0x17) -+#define T3OFF 0 -+#define T3COF 1 -+#define T3ICF 2 -+ -+#define T4IFR _SFR_IO8(0x18) -+#define T4OFF 0 -+#define T4COF 1 -+#define T4ICF 2 -+ -+#define T5IFR _SFR_IO8(0x19) -+#define T5OFF 0 -+#define T5COF 1 -+ -+#define GPIOR0 _SFR_IO8(0x1A) -+ -+#define GPIOR3 _SFR_IO8(0x1B) -+ -+#define GPIOR4 _SFR_IO8(0x1C) -+ -+#define GPIOR5 _SFR_IO8(0x1D) -+ -+#define GPIOR6 _SFR_IO8(0x1E) -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEWE 1 -+#define EEMWE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+#define EEPAGE 6 -+#define NVMBSY 7 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define EEPR _SFR_IO8(0x23) -+#define EEAP0 0 -+#define EEAP1 1 -+#define EEAP2 2 -+#define EEAP3 3 -+ -+#define GPIOR1 _SFR_IO8(0x24) -+ -+#define GPIOR2 _SFR_IO8(0x25) -+ -+#define PCICR _SFR_IO8(0x26) -+#define PCIE0 0 -+#define PCIE1 1 -+ -+#define EIMSK _SFR_IO8(0x27) -+#define INT0 0 -+#define INT1 1 -+ -+#define EIFR _SFR_IO8(0x28) -+#define INTF0 0 -+#define INTF1 1 -+ -+#define CRCDIR _SFR_IO8(0x29) -+ -+#define VMCSR _SFR_IO8(0x2A) -+#define VMLS0 0 -+#define VMLS1 1 -+#define VMLS2 2 -+#define VMLS3 3 -+#define VMIM 4 -+#define VMF 5 -+ -+#define MCUSR _SFR_IO8(0x2B) -+#define PORF 0 -+#define EXTRF 1 -+#define WDRF 3 -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define RXIF 4 -+#define TXIF 5 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+#define T0IFR _SFR_IO8(0x2F) -+#define T0F 0 -+ -+/* Reserved [0x30] */ -+ -+#define DWDR _SFR_IO8(0x31) -+ -+/* Reserved [0x32] */ -+ -+#define RDCR _SFR_IO8(0x33) -+#define RDPU 0 -+#define ADIVEN 1 -+#define RDEN 2 -+ -+#define EOTSA _SFR_IO8(0x34) -+#define CARFA 0 -+#define AMPFA 1 -+#define SYTFA 2 -+#define MANFA 3 -+#define TMOFA 4 -+#define TELRA 5 -+#define RRFA 6 -+#define EOTBF 7 -+ -+#define EOTCA _SFR_IO8(0x35) -+#define CARFEA 0 -+#define AMPFEA 1 -+#define SYTFEA 2 -+#define MANFEA 3 -+#define TMOFEA 4 -+#define TELREA 5 -+#define RRFEA 6 -+#define EOTBFE 7 -+ -+#define EOTSB _SFR_IO8(0x36) -+#define CARFB 0 -+#define AMPFB 1 -+#define SYTFB 2 -+#define MANFB 3 -+#define TMOFB 4 -+#define TELRB 5 -+#define RRFB 6 -+#define EOTAF 7 -+ -+#define EOTCB _SFR_IO8(0x37) -+#define CARFEB 0 -+#define AMPFEB 1 -+#define SYTFEB 2 -+#define MANFEB 3 -+#define TMOFEB 4 -+#define TELREB 5 -+#define RRFEB 6 -+#define EOTAFE 7 -+ -+#define SMCR _SFR_IO8(0x38) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define CMCR _SFR_IO8(0x39) -+#define CMM0 0 -+#define CMM1 1 -+#define CMM2 2 -+#define CCS 3 -+#define SRCD 4 -+#define CMONEN 6 -+#define CMCCE 7 -+ -+#define CMIMR _SFR_IO8(0x3A) -+#define ECIE 0 -+ -+#define CLPR _SFR_IO8(0x3B) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLTPS0 3 -+#define CLTPS1 4 -+#define CLTPS2 5 -+#define CLPCE 7 -+ -+#define SPMCSR _SFR_IO8(0x3C) -+#define SELFPRGEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define SPMIE 7 -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define FSEN _SFR_MEM8(0x60) -+#define SDPU 0 -+#define SDEN 1 -+#define GAEN 2 -+#define PEEN 3 -+#define ASEN 4 -+#define ANTT 5 -+ -+#define FSFCR _SFR_MEM8(0x61) -+#define BTSEL0 0 -+#define BTSEL1 1 -+#define ASDIV0 4 -+#define ASDIV1 5 -+#define ASDIV2 6 -+#define ASDIV3 7 -+ -+/* Combine GACDIVL and GACDIVH */ -+#define GACDIV _SFR_MEM16(0x62) -+ -+#define GACDIVL _SFR_MEM8(0x62) -+#define GACDIVH _SFR_MEM8(0x63) -+ -+#define FFREQ1L _SFR_MEM8(0x64) -+ -+#define FFREQ1M _SFR_MEM8(0x65) -+ -+#define FFREQ1H _SFR_MEM8(0x66) -+ -+#define FFREQ2L _SFR_MEM8(0x67) -+ -+#define FFREQ2M _SFR_MEM8(0x68) -+ -+#define FFREQ2H _SFR_MEM8(0x69) -+ -+/* Reserved [0x6A] */ -+ -+#define EICRA _SFR_MEM8(0x6B) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+ -+#define PCMSK0 _SFR_MEM8(0x6C) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6D) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+ -+#define WDTCR _SFR_MEM8(0x6E) -+#define WDPS0 0 -+#define WDPS1 1 -+#define WDPS2 2 -+#define WDE 3 -+#define WDCE 4 -+ -+#define T1CNT _SFR_MEM8(0x6F) -+ -+#define T1COR _SFR_MEM8(0x70) -+ -+#define T1MR _SFR_MEM8(0x71) -+#define T1CS0 0 -+#define T1CS1 1 -+#define T1PS0 2 -+#define T1PS1 3 -+#define T1PS2 4 -+#define T1PS3 5 -+#define T1DC0 6 -+#define T1DC1 7 -+ -+#define T1IMR _SFR_MEM8(0x72) -+#define T1OIM 0 -+#define T1CIM 1 -+ -+#define T2CNT _SFR_MEM8(0x73) -+ -+#define T2COR _SFR_MEM8(0x74) -+ -+#define T2MR _SFR_MEM8(0x75) -+#define T2CS0 0 -+#define T2CS1 1 -+#define T2PS0 2 -+#define T2PS1 3 -+#define T2PS2 4 -+#define T2PS3 5 -+#define T2DC0 6 -+#define T2DC1 7 -+ -+#define T2IMR _SFR_MEM8(0x76) -+#define T2OIM 0 -+#define T2CIM 1 -+ -+/* Combine T3CNTL and T3CNTH */ -+#define T3CNT _SFR_MEM16(0x77) -+ -+#define T3CNTL _SFR_MEM8(0x77) -+#define T3CNTH _SFR_MEM8(0x78) -+ -+/* Combine T3CORL and T3CORH */ -+#define T3COR _SFR_MEM16(0x79) -+ -+#define T3CORL _SFR_MEM8(0x79) -+#define T3CORH _SFR_MEM8(0x7A) -+ -+/* Combine T3ICRL and T3ICRH */ -+#define T3ICR _SFR_MEM16(0x7B) -+ -+#define T3ICRL _SFR_MEM8(0x7B) -+#define T3ICRH _SFR_MEM8(0x7C) -+ -+#define T3MRA _SFR_MEM8(0x7D) -+#define T3CS0 0 -+#define T3CS1 1 -+#define T3PS0 2 -+#define T3PS1 3 -+#define T3PS2 4 -+ -+#define T3MRB _SFR_MEM8(0x7E) -+#define T3SCE 1 -+#define T3CNC 2 -+#define T3CE0 3 -+#define T3CE1 4 -+#define T3ICS0 5 -+#define T3ICS1 6 -+#define T3ICS2 7 -+ -+#define T3IMR _SFR_MEM8(0x7F) -+#define T3OIM 0 -+#define T3CIM 1 -+#define T3CPIM 2 -+ -+/* Combine T4CNTL and T4CNTH */ -+#define T4CNT _SFR_MEM16(0x80) -+ -+#define T4CNTL _SFR_MEM8(0x80) -+#define T4CNTH _SFR_MEM8(0x81) -+ -+/* Combine T4CORL and T4CORH */ -+#define T4COR _SFR_MEM16(0x82) -+ -+#define T4CORL _SFR_MEM8(0x82) -+#define T4CORH _SFR_MEM8(0x83) -+ -+/* Combine T4ICRL and T4ICRH */ -+#define T4ICR _SFR_MEM16(0x84) -+ -+#define T4ICRL _SFR_MEM8(0x84) -+#define T4ICRH _SFR_MEM8(0x85) -+ -+#define T4MRA _SFR_MEM8(0x86) -+#define T4CS0 0 -+#define T4CS1 1 -+#define T4PS0 2 -+#define T4PS1 3 -+#define T4PS2 4 -+ -+#define T4MRB _SFR_MEM8(0x87) -+#define T4SCE 1 -+#define T4CNC 2 -+#define T4CE0 3 -+#define T4CE1 4 -+#define T4ICS0 5 -+#define T4ICS1 6 -+#define T4ICS2 7 -+ -+#define T4IMR _SFR_MEM8(0x88) -+#define T4OIM 0 -+#define T4CIM 1 -+#define T4CPIM 2 -+ -+/* Reserved [0x89] */ -+ -+/* Combine T5OCRL and T5OCRH */ -+#define T5OCR _SFR_MEM16(0x8A) -+ -+#define T5OCRL _SFR_MEM8(0x8A) -+#define T5OCRH _SFR_MEM8(0x8B) -+ -+#define T5CCR _SFR_MEM8(0x8C) -+#define T5CS0 0 -+#define T5CS1 1 -+#define T5CS2 2 -+#define T5CTC 3 -+ -+/* Combine T5CNTL and T5CNTH */ -+#define T5CNT _SFR_MEM16(0x8D) -+ -+#define T5CNTL _SFR_MEM8(0x8D) -+#define T5CNTH _SFR_MEM8(0x8E) -+ -+#define T5IMR _SFR_MEM8(0x8F) -+#define T5OIM 0 -+#define T5CIM 1 -+ -+#define GTCCR _SFR_MEM8(0x90) -+#define PSR10 0 -+#define TSM 7 -+ -+#define SOTSB _SFR_MEM8(0x91) -+#define CAROB 0 -+#define AMPOB 1 -+#define SYTOB 2 -+#define MANOB 3 -+#define WUPOB 4 -+#define SFIDOB 5 -+#define RROB 6 -+#define WCOAO 7 -+ -+#define SOTSA _SFR_MEM8(0x92) -+#define CAROA 0 -+#define AMPOA 1 -+#define SYTOA 2 -+#define MANOA 3 -+#define WUPOA 4 -+#define SFIDOA 5 -+#define RROA 6 -+#define WCOBO 7 -+ -+#define SOTCB _SFR_MEM8(0x93) -+#define CAROEB 0 -+#define AMPOEB 1 -+#define SYTOEB 2 -+#define MANOEB 3 -+#define WUPEB 4 -+#define SFIDEB 5 -+#define RROEB 6 -+#define WCOAOE 7 -+ -+#define SOTCA _SFR_MEM8(0x94) -+#define CAROEA 0 -+#define AMPOEA 1 -+#define SYTOEA 2 -+#define MANOEA 3 -+#define WUPEA 4 -+#define SFIDEA 5 -+#define RROEA 6 -+#define WCOBOE 7 -+ -+#define TESRB _SFR_MEM8(0x95) -+#define CRCOB 0 -+#define EOTLB0 1 -+#define EOTLB1 2 -+ -+#define TESRA _SFR_MEM8(0x96) -+#define CRCOA 0 -+#define EOTLA0 1 -+#define EOTLA1 2 -+ -+/* Reserved [0x97] */ -+ -+#define RDSIMR _SFR_MEM8(0x98) -+#define NBITAM 0 -+#define NBITBM 1 -+#define EOTAM 2 -+#define EOTBM 3 -+#define SOTAM 4 -+#define SOTBM 5 -+#define WCOAM 6 -+#define WCOBM 7 -+ -+#define RDOCR _SFR_MEM8(0x99) -+#define TMDS0 1 -+#define TMDS1 2 -+#define ETRPA 3 -+#define ETRPB 4 -+#define RDSIDA 5 -+#define RDSIDB 6 -+ -+/* Reserved [0x9A] */ -+ -+#define TEMPL _SFR_MEM8(0x9B) -+ -+#define TEMPH _SFR_MEM8(0x9C) -+ -+#define SYCB _SFR_MEM8(0x9D) -+#define SYCSB0 0 -+#define SYCSB1 1 -+#define SYCSB2 2 -+#define SYCSB3 3 -+#define SYTLB0 4 -+#define SYTLB1 5 -+#define SYTLB2 6 -+#define SYTLB3 7 -+ -+#define SYCA _SFR_MEM8(0x9E) -+#define SYCSA0 0 -+#define SYCSA1 1 -+#define SYCSA2 2 -+#define SYCSA3 3 -+#define SYTLA0 4 -+#define SYTLA1 5 -+#define SYTLA2 6 -+#define SYTLA3 7 -+ -+#define RXFOB _SFR_MEM8(0x9F) -+ -+#define RXFOA _SFR_MEM8(0xA0) -+ -+#define DMMB _SFR_MEM8(0xA1) -+#define DMATB0 0 -+#define DMATB1 1 -+#define DMATB2 2 -+#define DMATB3 3 -+#define DMATB4 4 -+#define DMPB 5 -+#define DMHB 6 -+#define DMNEB 7 -+ -+#define DMMA _SFR_MEM8(0xA2) -+#define DMATA0 0 -+#define DMATA1 1 -+#define DMATA2 2 -+#define DMATA3 3 -+#define DMATA4 4 -+#define DMPA 5 -+#define DMHA 6 -+#define DMNEA 7 -+ -+#define DMCDB _SFR_MEM8(0xA3) -+#define DMCLB0 0 -+#define DMCLB1 1 -+#define DMCLB2 2 -+#define DMCLB3 3 -+#define DMCLB4 4 -+#define DMCTB0 5 -+#define DMCTB1 6 -+#define DMCTB2 7 -+ -+#define DMCDA _SFR_MEM8(0xA4) -+#define DMCLA0 0 -+#define DMCLA1 1 -+#define DMCLA2 2 -+#define DMCLA3 3 -+#define DMCLA4 4 -+#define DMCTA0 5 -+#define DMCTA1 6 -+#define DMCTA2 7 -+ -+#define DMCRB _SFR_MEM8(0xA5) -+#define DMPGB0 0 -+#define DMPGB1 1 -+#define DMPGB2 2 -+#define DMPGB3 3 -+#define DMPGB4 4 -+#define SASKB 5 -+#define SY1TB 6 -+#define DMARB 7 -+ -+#define DMCRA _SFR_MEM8(0xA6) -+#define DMPGA0 0 -+#define DMPGA1 1 -+#define DMPGA2 2 -+#define DMPGA3 3 -+#define DMPGA4 4 -+#define SASKA 5 -+#define SY1TA 6 -+#define DMARA 7 -+ -+#define DMDRB _SFR_MEM8(0xA7) -+#define DMAB0 0 -+#define DMAB1 1 -+#define DMAB2 2 -+#define DMAB3 3 -+#define DMDNB0 4 -+#define DMDNB1 5 -+#define DMDNB2 6 -+#define DMDNB3 7 -+ -+#define DMDRA _SFR_MEM8(0xA8) -+#define DMAA0 0 -+#define DMAA1 1 -+#define DMAA2 2 -+#define DMAA3 3 -+#define DMDNA0 4 -+#define DMDNA1 5 -+#define DMDNA2 6 -+#define DMDNA3 7 -+ -+#define CHCR _SFR_MEM8(0xA9) -+#define BWM0 0 -+#define BWM1 1 -+#define BWM2 2 -+#define BWM3 3 -+ -+#define CHDN _SFR_MEM8(0xAA) -+#define BBDN0 0 -+#define BBDN1 1 -+#define BBDN2 2 -+#define BBDN3 3 -+#define BBDN4 4 -+#define ADCDN 5 -+ -+#define SFIDCB _SFR_MEM8(0xAB) -+#define SFIDTB0 0 -+#define SFIDTB1 1 -+#define SFIDTB2 2 -+#define SFIDTB3 3 -+#define SFIDTB4 4 -+#define SEMEB 7 -+ -+#define SFIDLB _SFR_MEM8(0xAC) -+#define SFIDLB0 0 -+#define SFIDLB1 1 -+#define SFIDLB2 2 -+#define SFIDLB3 3 -+#define SFIDLB4 4 -+#define SFIDLB5 5 -+ -+#define WUPTB _SFR_MEM8(0xAD) -+#define WUPTB0 0 -+#define WUPTB1 1 -+#define WUPTB2 2 -+#define WUPTB3 3 -+#define WUPTB4 4 -+ -+#define WUPLB _SFR_MEM8(0xAE) -+#define WUPLB0 0 -+#define WUPLB1 1 -+#define WUPLB2 2 -+#define WUPLB3 3 -+#define WUPLB4 4 -+#define WUPLB5 5 -+ -+#define SFID1B _SFR_MEM8(0xAF) -+ -+#define SFID2B _SFR_MEM8(0xB0) -+ -+#define SFID3B _SFR_MEM8(0xB1) -+ -+#define SFID4B _SFR_MEM8(0xB2) -+ -+#define WUP1B _SFR_MEM8(0xB3) -+ -+#define WUP2B _SFR_MEM8(0xB4) -+ -+#define WUP3B _SFR_MEM8(0xB5) -+ -+#define WUP4B _SFR_MEM8(0xB6) -+ -+#define SFIDCA _SFR_MEM8(0xB7) -+#define SFIDTA0 0 -+#define SFIDTA1 1 -+#define SFIDTA2 2 -+#define SFIDTA3 3 -+#define SFIDTA4 4 -+#define SEMEA 7 -+ -+#define SFIDLA _SFR_MEM8(0xB8) -+#define SFIDLA0 0 -+#define SFIDLA1 1 -+#define SFIDLA2 2 -+#define SFIDLA3 3 -+#define SFIDLA4 4 -+#define SFIDLA5 5 -+ -+#define WUPTA _SFR_MEM8(0xB9) -+#define WUPTA0 0 -+#define WUPTA1 1 -+#define WUPTA2 2 -+#define WUPTA3 3 -+#define WUPTA4 4 -+ -+#define WUPLA _SFR_MEM8(0xBA) -+#define WUPLA0 0 -+#define WUPLA1 1 -+#define WUPLA2 2 -+#define WUPLA3 3 -+#define WUPLA4 4 -+#define WUPLA5 5 -+ -+#define SFID1A _SFR_MEM8(0xBB) -+ -+#define SFID2A _SFR_MEM8(0xBC) -+ -+#define SFID3A _SFR_MEM8(0xBD) -+ -+#define SFID4A _SFR_MEM8(0xBE) -+ -+#define WUP1A _SFR_MEM8(0xBF) -+ -+#define WUP2A _SFR_MEM8(0xC0) -+ -+#define WUP3A _SFR_MEM8(0xC1) -+ -+#define WUP4A _SFR_MEM8(0xC2) -+ -+#define CLKOD _SFR_MEM8(0xC3) -+ -+#define CLKOCR _SFR_MEM8(0xC4) -+#define CLKOS0 0 -+#define CLKOS1 1 -+#define CLKOEN 2 -+ -+#define XFUSE _SFR_MEM8(0xC5) -+ -+#define SRCCAL _SFR_MEM8(0xC6) -+#define SRCCAL0 0 -+#define SRCCAL1 1 -+#define SRCCAL2 2 -+#define SRCCAL3 3 -+#define SRCCAL4 4 -+#define SRCCAL5 5 -+#define SRCTC0 6 -+#define SRCTC1 7 -+ -+#define FRCCAL _SFR_MEM8(0xC7) -+#define FRCCAL0 0 -+#define FRCCAL1 1 -+#define FRCCAL2 2 -+#define FRCCAL3 3 -+#define FRCCAL4 4 -+#define FRCTC 5 -+ -+#define CMSR _SFR_MEM8(0xC8) -+#define ECF 0 -+ -+#define CMOCR _SFR_MEM8(0xC9) -+#define FRCAO 0 -+#define SRCAO 1 -+#define FRCACT 2 -+#define SRCACT 3 -+ -+#define SUPFR _SFR_MEM8(0xCA) -+#define AVCCRF 0 -+#define AVCCLF 1 -+ -+#define SUPCR _SFR_MEM8(0xCB) -+#define AVCCRM 0 -+#define AVCCLM 1 -+#define PVEN 2 -+#define DVDIS 4 -+#define AVEN 5 -+#define AVDIC 6 -+ -+#define SUPCA1 _SFR_MEM8(0xCC) -+#define PV22 2 -+#define PVDIC 3 -+#define PVCAL0 4 -+#define PVCAL1 5 -+#define PVCAL2 6 -+#define PVCAL3 7 -+ -+#define SUPCA2 _SFR_MEM8(0xCD) -+#define BGCAL0 0 -+#define BGCAL1 1 -+#define BGCAL2 2 -+#define BGCAL3 3 -+ -+#define SUPCA3 _SFR_MEM8(0xCE) -+#define ACAL4 0 -+#define ACAL5 1 -+#define ACAL6 2 -+#define ACAL7 3 -+#define DCAL4 4 -+#define DCAL5 5 -+#define DCAL6 6 -+ -+#define SUPCA4 _SFR_MEM8(0xCF) -+#define ACAL0 0 -+#define ACAL1 1 -+#define ACAL2 2 -+#define ACAL3 3 -+#define DCAL0 4 -+#define DCAL1 5 -+#define DCAL2 6 -+#define DCAL3 7 -+ -+#define CALRDY _SFR_MEM8(0xD0) -+ -+#define VMCAL _SFR_MEM8(0xD1) -+#define VMCAL0 0 -+#define VMCAL1 1 -+#define VMCAL2 2 -+ -+#define DFS _SFR_MEM8(0xD2) -+#define DFFLRF 0 -+#define DFUFL 1 -+#define DFOFL 2 -+ -+/* Combine DFTLL and DFTLH */ -+#define DFTL _SFR_MEM16(0xD3) -+ -+#define DFTLL _SFR_MEM8(0xD3) -+#define DFTLH _SFR_MEM8(0xD4) -+ -+#define DFL _SFR_MEM8(0xD5) -+#define DFFLS0 0 -+#define DFFLS1 1 -+#define DFFLS2 2 -+#define DFFLS3 3 -+#define DFFLS4 4 -+#define DFFLS5 5 -+#define DFCLR 7 -+ -+#define DFWP _SFR_MEM8(0xD6) -+#define DFWP0 0 -+#define DFWP1 1 -+#define DFWP2 2 -+#define DFWP3 3 -+#define DFWP4 4 -+#define DFWP5 5 -+ -+#define DFRP _SFR_MEM8(0xD7) -+#define DFRP0 0 -+#define DFRP1 1 -+#define DFRP2 2 -+#define DFRP3 3 -+#define DFRP4 4 -+#define DFRP5 5 -+ -+#define DFD _SFR_MEM8(0xD8) -+ -+#define DFI _SFR_MEM8(0xD9) -+#define DFFLIM 0 -+#define DFERIM 1 -+ -+#define DFC _SFR_MEM8(0xDA) -+#define DFFLC0 0 -+#define DFFLC1 1 -+#define DFFLC2 2 -+#define DFFLC3 3 -+#define DFFLC4 4 -+#define DFFLC5 5 -+#define DFDRA 7 -+ -+#define SFS _SFR_MEM8(0xDB) -+#define SFFLRF 0 -+#define SFUFL 1 -+#define SFOFL 2 -+ -+#define SFL _SFR_MEM8(0xDC) -+#define SFFLS0 0 -+#define SFFLS1 1 -+#define SFFLS2 2 -+#define SFFLS3 3 -+#define SFFLS4 4 -+#define SFCLR 7 -+ -+#define SFWP _SFR_MEM8(0xDD) -+#define SFWP0 0 -+#define SFWP1 1 -+#define SFWP2 2 -+#define SFWP3 3 -+#define SFWP4 4 -+ -+#define SFRP _SFR_MEM8(0xDE) -+#define SFRP0 0 -+#define SFRP1 1 -+#define SFRP2 2 -+#define SFRP3 3 -+#define SFRP4 4 -+ -+#define SFD _SFR_MEM8(0xDF) -+ -+#define SFI _SFR_MEM8(0xE0) -+#define SFFLIM 0 -+#define SFERIM 1 -+ -+#define SFC _SFR_MEM8(0xE1) -+#define SFFLC0 0 -+#define SFFLC1 1 -+#define SFFLC2 2 -+#define SFFLC3 3 -+#define SFFLC4 4 -+#define SFDRA 7 -+ -+#define SSMCR _SFR_MEM8(0xE2) -+#define SSMTX 0 -+#define SSMTM 1 -+#define SSMTGE 2 -+#define SSMTPE 3 -+#define SSMPVE 4 -+#define SSMTAE 5 -+#define SETRPA 6 -+#define SETRPB 7 -+ -+#define SSMRCR _SFR_MEM8(0xE3) -+#define SSMPA 0 -+#define SSMPB 1 -+#define SSMADA 2 -+#define SSMADB 3 -+#define SSMPVS 4 -+#define SSMIFA 5 -+#define SSMIDSE 6 -+#define SSMTMOE 7 -+ -+#define SSMFBR _SFR_MEM8(0xE4) -+#define SSMFID0 0 -+#define SSMFID1 1 -+#define SSMFID2 2 -+#define SSMDFDT 3 -+#define SSMHADT 4 -+#define SSMPLDT 5 -+ -+#define SSMRR _SFR_MEM8(0xE5) -+#define SSMR 0 -+#define SSMST 1 -+ -+#define SSMSR _SFR_MEM8(0xE6) -+#define SSMESM0 0 -+#define SSMESM1 1 -+#define SSMESM2 2 -+#define SSMESM3 3 -+#define SSMERR 7 -+ -+#define SSMIFR _SFR_MEM8(0xE7) -+#define SSMIF 0 -+ -+#define SSMIMR _SFR_MEM8(0xE8) -+#define SSMIM 0 -+ -+#define MSMSTR _SFR_MEM8(0xE9) -+#define SSMMST0 0 -+#define SSMMST1 1 -+#define SSMMST2 2 -+#define SSMMST3 3 -+#define SSMMST4 4 -+ -+#define SSMSTR _SFR_MEM8(0xEA) -+#define SSMSTA0 0 -+#define SSMSTA1 1 -+#define SSMSTA2 2 -+#define SSMSTA3 3 -+#define SSMSTA4 4 -+#define SSMSTA5 5 -+ -+#define SSMXSR _SFR_MEM8(0xEB) -+#define SSMSTB0 0 -+#define SSMSTB1 1 -+#define SSMSTB2 2 -+#define SSMSTB3 3 -+#define SSMSTB4 4 -+#define SSMSTB5 5 -+ -+#define MSMCR1 _SFR_MEM8(0xEC) -+#define MSMSM00 0 -+#define MSMSM01 1 -+#define MSMSM02 2 -+#define MSMSM03 3 -+#define MSMSM10 4 -+#define MSMSM11 5 -+#define MSMSM12 6 -+#define MSMSM13 7 -+ -+#define MSMCR2 _SFR_MEM8(0xED) -+#define MSMSM20 0 -+#define MSMSM21 1 -+#define MSMSM22 2 -+#define MSMSM23 3 -+#define MSMSM30 4 -+#define MSMSM31 5 -+#define MSMSM32 6 -+#define MSMSM33 7 -+ -+#define MSMCR3 _SFR_MEM8(0xEE) -+#define MSMSM40 0 -+#define MSMSM41 1 -+#define MSMSM42 2 -+#define MSMSM43 3 -+#define MSMSM50 4 -+#define MSMSM51 5 -+#define MSMSM52 6 -+#define MSMSM53 7 -+ -+#define MSMCR4 _SFR_MEM8(0xEF) -+#define MSMSM60 0 -+#define MSMSM61 1 -+#define MSMSM62 2 -+#define MSMSM63 3 -+#define MSMSM70 4 -+#define MSMSM71 5 -+#define MSMSM72 6 -+#define MSMSM73 7 -+ -+#define GTCR _SFR_MEM8(0xF0) -+#define RXTEHA 0 -+#define GAPMA 1 -+#define DARA 2 -+#define IWUPA 3 -+#define RXTEHB 4 -+#define GAPMB 5 -+#define DARB 6 -+#define IWUPB 7 -+ -+#define SOTC1A _SFR_MEM8(0xF1) -+#define CAROEA1 0 -+#define AMPOEA1 1 -+#define SYTOEA1 2 -+#define MANOEA1 3 -+#define WUPEA1 4 -+#define SFIDEA1 5 -+#define RROEA1 6 -+#define WCOBOE1 7 -+ -+#define SOTC2A _SFR_MEM8(0xF2) -+#define CAROEA2 0 -+#define AMPOEA2 1 -+#define SYTOEA2 2 -+#define MANOEA2 3 -+#define WUPEA2 4 -+#define SFIDEA2 5 -+#define RROEA2 6 -+#define WCOBOE2 7 -+ -+#define SOTC1B _SFR_MEM8(0xF3) -+#define CAROEB1 0 -+#define AMPOEB1 1 -+#define SYTOEB1 2 -+#define MANOEB1 3 -+#define WUPEB1 4 -+#define SFIDEB1 5 -+#define RROEB1 6 -+#define WCOAOE1 7 -+ -+#define SOTC2B _SFR_MEM8(0xF4) -+#define CAROEB2 0 -+#define AMPOEB2 1 -+#define SYTOEB2 2 -+#define MANOEB2 3 -+#define WUPEB2 4 -+#define SFIDEB2 5 -+#define RROEB2 6 -+#define WCOAOE2 7 -+ -+#define EOTC1A _SFR_MEM8(0xF5) -+#define CARFEA1 0 -+#define AMPFEA1 1 -+#define SYTFEA1 2 -+#define MANFEA1 3 -+#define TMOFEA1 4 -+#define TELREA1 5 -+#define RRFEA1 6 -+#define EOTBFE1 7 -+ -+#define EOTC2A _SFR_MEM8(0xF6) -+#define CARFEA2 0 -+#define AMPFEA2 1 -+#define SYTFEA2 2 -+#define MANFEA2 3 -+#define TMOFEA2 4 -+#define TELREA2 5 -+#define RRFEA2 6 -+#define EOTBFE2 7 -+ -+#define EOTC3A _SFR_MEM8(0xF7) -+#define CARFEA3 0 -+#define AMPFEA3 1 -+#define SYTFEA3 2 -+#define MANFEA3 3 -+#define TMOFEA3 4 -+#define TELREA3 5 -+#define RRFEA3 6 -+#define EOTBFE3 7 -+ -+#define EOTC1B _SFR_MEM8(0xF8) -+#define CARFEB1 0 -+#define AMPFEB1 1 -+#define SYTFEB1 2 -+#define MANFEB1 3 -+#define TMOFEB1 4 -+#define TELREB1 5 -+#define RRFEB1 6 -+#define EOTAFE1 7 -+ -+#define EOTC2B _SFR_MEM8(0xF9) -+#define CARFEB2 0 -+#define AMPFEB2 1 -+#define SYTFEB2 2 -+#define MANFEB2 3 -+#define TMOFEB2 4 -+#define TELREB2 5 -+#define RRFEB2 6 -+#define EOTAFE2 7 -+ -+#define EOTC3B _SFR_MEM8(0xFA) -+#define CARFEB3 0 -+#define AMPFEB3 1 -+#define SYTFEB3 2 -+#define MANFEB3 3 -+#define TMOFEB3 4 -+#define TELREB3 5 -+#define RRFEB3 6 -+#define EOTAFE3 7 -+ -+#define WCOTOA _SFR_MEM8(0xFB) -+ -+#define WCOTOB _SFR_MEM8(0xFC) -+ -+#define SOTTOA _SFR_MEM8(0xFD) -+ -+#define SOTTOB _SFR_MEM8(0xFE) -+ -+#define SSMFCR _SFR_MEM8(0xFF) -+#define SSMIDSO 0 -+#define SSMIDSF 1 -+ -+#define FESR _SFR_MEM8(0x100) -+#define LBSAT 0 -+#define HBSAT 1 -+#define XRDY 2 -+#define PLCK 3 -+#define ANTS 4 -+ -+#define FEEN1 _SFR_MEM8(0x101) -+#define PLEN 0 -+#define PLCAL 1 -+#define XTOEN 2 -+#define LNAEN 3 -+#define ADEN 4 -+#define ADCLK 5 -+#define PLSP1 6 -+#define ATEN 7 -+ -+#define FEEN2 _SFR_MEM8(0x102) -+#define SDRX 0 -+#define SDTX 1 -+#define PAEN 2 -+#define TMPM 3 -+#define PLPEN 4 -+#define XTPEN 5 -+#define CPBIA 6 -+ -+#define FELNA _SFR_MEM8(0x103) -+#define LBH0 0 -+#define LBH1 1 -+#define LBH2 2 -+#define LBH3 3 -+#define LBL0 4 -+#define LBL1 5 -+#define LBL2 6 -+#define LBL3 7 -+ -+#define FEAT _SFR_MEM8(0x104) -+#define ANTN0 0 -+#define ANTN1 1 -+#define ANTN2 2 -+#define ANTN3 3 -+ -+#define FEPAC _SFR_MEM8(0x105) -+ -+#define FEVCT _SFR_MEM8(0x106) -+#define FEVCT0 0 -+#define FEVCT1 1 -+#define FEVCT2 2 -+#define FEVCT3 3 -+ -+#define FEBT _SFR_MEM8(0x107) -+#define CTN20 0 -+#define CTN21 1 -+#define RTN20 2 -+#define RTN21 3 -+ -+#define FEMS _SFR_MEM8(0x108) -+#define PLLS0 0 -+#define PLLS1 1 -+#define PLLS2 2 -+#define PLLS3 3 -+#define PLLM0 4 -+#define PLLM1 5 -+#define PLLM2 6 -+#define PLLM3 7 -+ -+#define FETN4 _SFR_MEM8(0x109) -+#define CTN40 0 -+#define CTN41 1 -+#define CTN42 2 -+#define CTN43 3 -+#define RTN40 4 -+#define RTN41 5 -+#define RTN42 6 -+#define RTN43 7 -+ -+#define FECR _SFR_MEM8(0x10A) -+#define LBNHB 0 -+#define S4N3 1 -+#define ANDP 2 -+#define ADHS 3 -+#define PLCKG 4 -+#define ANPS 5 -+ -+#define FEVCO _SFR_MEM8(0x10B) -+#define CPCC0 0 -+#define CPCC1 1 -+#define CPCC2 2 -+#define CPCC3 3 -+#define VCOB0 4 -+#define VCOB1 5 -+#define VCOB2 6 -+#define VCOB3 7 -+ -+#define FEALR _SFR_MEM8(0x10C) -+#define RNGE0 0 -+#define RNGE1 1 -+ -+#define FEANT _SFR_MEM8(0x10D) -+#define LVLC0 0 -+#define LVLC1 1 -+#define LVLC2 2 -+#define LVLC3 3 -+ -+#define FEBIA _SFR_MEM8(0x10E) -+#define IFAEN 7 -+ -+/* Reserved [0x10F..0x11F] */ -+ -+#define TMFSM _SFR_MEM8(0x120) -+#define TMSSM0 0 -+#define TMSSM1 1 -+#define TMSSM2 2 -+#define TMSSM3 3 -+#define TMMSM0 4 -+#define TMMSM1 5 -+#define TMMSM2 6 -+ -+/* Combine TMCRL and TMCRH */ -+#define TMCR _SFR_MEM16(0x121) -+ -+#define TMCRL _SFR_MEM8(0x121) -+#define TMCRH _SFR_MEM8(0x122) -+ -+#define TMCSB _SFR_MEM8(0x123) -+ -+/* Combine TMCIL and TMCIH */ -+#define TMCI _SFR_MEM16(0x124) -+ -+#define TMCIL _SFR_MEM8(0x124) -+#define TMCIH _SFR_MEM8(0x125) -+ -+/* Combine TMCPL and TMCPH */ -+#define TMCP _SFR_MEM16(0x126) -+ -+#define TMCPL _SFR_MEM8(0x126) -+#define TMCPH _SFR_MEM8(0x127) -+ -+#define TMSHR _SFR_MEM8(0x128) -+ -+/* Combine TMTLL and TMTLH */ -+#define TMTL _SFR_MEM16(0x129) -+ -+#define TMTLL _SFR_MEM8(0x129) -+#define TMTLH _SFR_MEM8(0x12A) -+ -+#define TMSSC _SFR_MEM8(0x12B) -+#define TMSSP0 0 -+#define TMSSP1 1 -+#define TMSSP2 2 -+#define TMSSP3 3 -+#define TMSSL0 4 -+#define TMSSL1 5 -+#define TMSSL2 6 -+#define TMSSH 7 -+ -+#define TMSR _SFR_MEM8(0x12C) -+#define TMTCF 0 -+ -+#define TMCR2 _SFR_MEM8(0x12D) -+#define TMCRCE 0 -+#define TMCRCL0 1 -+#define TMCRCL1 2 -+#define TMNRZE 3 -+#define TMPOL 4 -+#define TMSSE 5 -+#define TMMSB 6 -+ -+#define TMCR1 _SFR_MEM8(0x12E) -+#define TMPIS0 0 -+#define TMPIS1 1 -+#define TMPIS2 2 -+#define TMSCS 3 -+#define TMCIM 4 -+ -+#define RXBC1 _SFR_MEM8(0x12F) -+#define RXCEA 0 -+#define RXCBLA0 1 -+#define RXCBLA1 2 -+#define RXMSBA 3 -+#define RXCEB 4 -+#define RXCBLB0 5 -+#define RXCBLB1 6 -+#define RXMSBB 7 -+ -+#define RXBC2 _SFR_MEM8(0x130) -+#define RXBPB 0 -+#define RXBF 1 -+#define RXBCLR 2 -+ -+#define RXTLLB _SFR_MEM8(0x131) -+ -+#define RXTLHB _SFR_MEM8(0x132) -+#define RXTLHB0 0 -+#define RXTLHB1 1 -+#define RXTLHB2 2 -+#define RXTLHB3 3 -+ -+#define RXCRLB _SFR_MEM8(0x133) -+ -+#define RXCRHB _SFR_MEM8(0x134) -+ -+#define RXCSBB _SFR_MEM8(0x135) -+ -+#define RXCILB _SFR_MEM8(0x136) -+ -+#define RXCIHB _SFR_MEM8(0x137) -+ -+#define RXCPLB _SFR_MEM8(0x138) -+ -+#define RXCPHB _SFR_MEM8(0x139) -+ -+#define RXDSB _SFR_MEM8(0x13A) -+ -+#define RXTLLA _SFR_MEM8(0x13B) -+ -+#define RXTLHA _SFR_MEM8(0x13C) -+#define RXTLHA0 0 -+#define RXTLHA1 1 -+#define RXTLHA2 2 -+#define RXTLHA3 3 -+ -+#define RXCRLA _SFR_MEM8(0x13D) -+ -+#define RXCRHA _SFR_MEM8(0x13E) -+ -+#define RXCSBA _SFR_MEM8(0x13F) -+ -+#define RXCILA _SFR_MEM8(0x140) -+ -+#define RXCIHA _SFR_MEM8(0x141) -+ -+#define RXCPLA _SFR_MEM8(0x142) -+ -+#define RXCPHA _SFR_MEM8(0x143) -+ -+#define RXDSA _SFR_MEM8(0x144) -+ -+#define CRCCR _SFR_MEM8(0x145) -+#define CRCRS 0 -+#define REFLI 1 -+#define REFLO 2 -+ -+#define CRCDOR _SFR_MEM8(0x146) -+ -+#define IDB0 _SFR_MEM8(0x147) -+ -+#define IDB1 _SFR_MEM8(0x148) -+ -+#define IDB2 _SFR_MEM8(0x149) -+ -+#define IDB3 _SFR_MEM8(0x14A) -+ -+#define IDC _SFR_MEM8(0x14B) -+#define IDL0 0 -+#define IDL1 1 -+#define IDBO0 2 -+#define IDBO1 3 -+#define IDFIM 5 -+#define IDCLR 6 -+#define IDCE 7 -+ -+#define IDS _SFR_MEM8(0x14C) -+#define IDOK 0 -+#define IDFULL 1 -+ -+#define RSSAV _SFR_MEM8(0x14D) -+ -+#define RSSPK _SFR_MEM8(0x14E) -+ -+#define RSSL _SFR_MEM8(0x14F) -+ -+#define RSSH _SFR_MEM8(0x150) -+ -+#define RSSC _SFR_MEM8(0x151) -+#define RSUP0 0 -+#define RSUP1 1 -+#define RSUP2 2 -+#define RSUP3 3 -+#define RSWLH 4 -+#define RSHRX 5 -+#define RSPKF 6 -+ -+#define DBCR _SFR_MEM8(0x152) -+#define DBMD 0 -+#define DBCS 1 -+#define DBTMS 2 -+#define DBHA 3 -+ -+#define DBTC _SFR_MEM8(0x153) -+ -+#define DBENB _SFR_MEM8(0x154) -+ -+#define DBENC _SFR_MEM8(0x155) -+ -+#define DBGSW _SFR_MEM8(0x156) -+#define DBGGS0 0 -+#define DBGGS1 1 -+#define DBGGS2 2 -+#define DBGGS3 3 -+#define CPBFOS0 4 -+#define CPBFOS1 5 -+#define CPBF 6 -+#define DBGSE 7 -+ -+#define SFFR _SFR_MEM8(0x157) -+#define RFL0 0 -+#define RFL1 1 -+#define RFL2 2 -+#define RFC 3 -+#define TFL0 4 -+#define TFL1 5 -+#define TFL2 6 -+#define TFC 7 -+ -+#define SFIR _SFR_MEM8(0x158) -+#define RIL0 0 -+#define RIL1 1 -+#define RIL2 2 -+#define SRIE 3 -+#define TIL0 4 -+#define TIL1 5 -+#define TIL2 6 -+#define STIE 7 -+ -+#define EECR2 _SFR_MEM8(0x159) -+#define EEBRE 0 -+ -+#define PGMST _SFR_MEM8(0x15A) -+#define PGMSYN0 0 -+#define PGMSYN1 1 -+#define PGMSYN2 2 -+#define PGMSYN3 3 -+#define PGMSYN4 4 -+ -+#define EEST _SFR_MEM8(0x15B) -+#define EESYN0 0 -+#define EESYN1 1 -+#define EESYN2 2 -+#define EESYN3 3 -+ -+#define RSIFG _SFR_MEM8(0x15C) -+ -+#define RSLDV _SFR_MEM8(0x15D) -+ -+#define RSHDV _SFR_MEM8(0x15E) -+ -+#define RSCOM _SFR_MEM8(0x15F) -+#define RSDC 0 -+#define RSIFC 1 -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCI0_vect _VECTOR(3) -+#define PCI0_vect_num 3 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCI1_vect _VECTOR(4) -+#define PCI1_vect_num 4 -+ -+/* Voltage Monitoring Interrupt */ -+#define VMON_vect _VECTOR(5) -+#define VMON_vect_num 5 -+ -+/* AVCC Reset Interrupt */ -+#define AVCCR_vect _VECTOR(6) -+#define AVCCR_vect_num 6 -+ -+/* AVCC Low Interrupt */ -+#define AVCCL_vect _VECTOR(7) -+#define AVCCL_vect_num 7 -+ -+/* Timer 0 Interval Interrupt */ -+#define T0INT_vect _VECTOR(8) -+#define T0INT_vect_num 8 -+ -+/* Timer/Counter1 Compare Match Interrupt */ -+#define T1COMP_vect _VECTOR(9) -+#define T1COMP_vect_num 9 -+ -+/* Timer/Counter1 Overflow Interrupt */ -+#define T1OVF_vect _VECTOR(10) -+#define T1OVF_vect_num 10 -+ -+/* Timer/Counter2 Compare Match Interrupt */ -+#define T2COMP_vect _VECTOR(11) -+#define T2COMP_vect_num 11 -+ -+/* Timer/Counter2 Overflow Interrupt */ -+#define T2OVF_vect _VECTOR(12) -+#define T2OVF_vect_num 12 -+ -+/* Timer/Counter3 Capture Event Interrupt */ -+#define T3CAP_vect _VECTOR(13) -+#define T3CAP_vect_num 13 -+ -+/* Timer/Counter3 Compare Match Interrupt */ -+#define T3COMP_vect _VECTOR(14) -+#define T3COMP_vect_num 14 -+ -+/* Timer/Counter3 Overflow Interrupt */ -+#define T3OVF_vect _VECTOR(15) -+#define T3OVF_vect_num 15 -+ -+/* Timer/Counter4 Capture Event Interrupt */ -+#define T4CAP_vect _VECTOR(16) -+#define T4CAP_vect_num 16 -+ -+/* Timer/Counter4 Compare Match Interrupt */ -+#define T4COMP_vect _VECTOR(17) -+#define T4COMP_vect_num 17 -+ -+/* Timer/Counter4 Overflow Interrupt */ -+#define T4OVF_vect _VECTOR(18) -+#define T4OVF_vect_num 18 -+ -+/* Timer/Counter5 Compare Match Interrupt */ -+#define T5COMP_vect _VECTOR(19) -+#define T5COMP_vect_num 19 -+ -+/* Timer/Counter5 Overflow Interrupt */ -+#define T5OVF_vect _VECTOR(20) -+#define T5OVF_vect_num 20 -+ -+/* SPI Serial Transfer Complete Interrupt */ -+#define SPI_vect _VECTOR(21) -+#define SPI_vect_num 21 -+ -+/* SPI Rx Buffer Interrupt */ -+#define SRX_FIFO_vect _VECTOR(22) -+#define SRX_FIFO_vect_num 22 -+ -+/* SPI Tx Buffer Interrupt */ -+#define STX_FIFO_vect _VECTOR(23) -+#define STX_FIFO_vect_num 23 -+ -+/* Sequencer State Machine Interrupt */ -+#define SSM_vect _VECTOR(24) -+#define SSM_vect_num 24 -+ -+/* Data FIFO fill level reached Interrupt */ -+#define DFFLR_vect _VECTOR(25) -+#define DFFLR_vect_num 25 -+ -+/* Data FIFO overflow or underflow error Interrupt */ -+#define DFOUE_vect _VECTOR(26) -+#define DFOUE_vect_num 26 -+ -+/* RSSI/Preamble FIFO fill level reached Interrupt */ -+#define SFFLR_vect _VECTOR(27) -+#define SFFLR_vect_num 27 -+ -+/* RSSI/Preamble FIFO overflow or underflow error Interrupt */ -+#define SFOUE_vect _VECTOR(28) -+#define SFOUE_vect_num 28 -+ -+/* Tx Modulator Telegram Finish Interrupt */ -+#define TMTCF_vect _VECTOR(29) -+#define TMTCF_vect_num 29 -+ -+/* UHF receiver wake up ok on Rx path B */ -+#define UHF_WCOB_vect _VECTOR(30) -+#define UHF_WCOB_vect_num 30 -+ -+/* UHF receiver wake up ok on Rx path A */ -+#define UHF_WCOA_vect _VECTOR(31) -+#define UHF_WCOA_vect_num 31 -+ -+/* UHF receiver start of telegram ok on Rx path B */ -+#define UHF_SOTB_vect _VECTOR(32) -+#define UHF_SOTB_vect_num 32 -+ -+/* UHF receiver start of telegram ok on Rx path A */ -+#define UHF_SOTA_vect _VECTOR(33) -+#define UHF_SOTA_vect_num 33 -+ -+/* UHF receiver end of telegram on Rx path B */ -+#define UHF_EOTB_vect _VECTOR(34) -+#define UHF_EOTB_vect_num 34 -+ -+/* UHF receiver end of telegram on Rx path A */ -+#define UHF_EOTA_vect _VECTOR(35) -+#define UHF_EOTA_vect_num 35 -+ -+/* UHF receiver new bit on Rx path B */ -+#define UHF_NBITB_vect _VECTOR(36) -+#define UHF_NBITB_vect_num 36 -+ -+/* UHF receiver new bit on Rx path A */ -+#define UHF_NBITA_vect _VECTOR(37) -+#define UHF_NBITA_vect_num 37 -+ -+/* External input Clock monitoring Interrupt */ -+#define EXCM_vect _VECTOR(38) -+#define EXCM_vect_num 38 -+ -+/* EEPROM Ready Interrupt */ -+#define ERDY_vect _VECTOR(39) -+#define ERDY_vect_num 39 -+ -+/* Store Program Memory Ready */ -+#define SPMR_vect _VECTOR(40) -+#define SPMR_vect_num 40 -+ -+/* IDSCAN Full Interrupt */ -+#define IDFULL_vect _VECTOR(41) -+#define IDFULL_vect_num 41 -+ -+#define _VECTORS_SIZE 168 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 64 -+#define FLASHSTART 0x8000 -+#define FLASHEND 0xCFFF -+#define RAMSTART 0x0200 -+#define RAMSIZE 1024 -+#define RAMEND 0x05FF -+#define E2START 0 -+#define E2SIZE 1152 -+#define E2PAGESIZE 16 -+#define E2END 0x047F -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 1 -+ -+/* Fuse Byte */ -+#define FUSE_CKDIV8 (unsigned char)~_BV(128) -+#define FUSE_DWEN (unsigned char)~_BV(64) -+#define FUSE_SPIEN (unsigned char)~_BV(32) -+#define FUSE_WDTON (unsigned char)~_BV(16) -+#define FUSE_EESAVE (unsigned char)~_BV(8) -+#define FUSE_BOOTRST (unsigned char)~_BV(4) -+#define FUSE_RSTDISBL (unsigned char)~_BV(2) -+#define FUSE_EXTCLKEN (unsigned char)~_BV(1) -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x95 -+#define SIGNATURE_2 0x63 -+ -+ -+#endif /* #ifdef _AVR_ATA5833_H_INCLUDED */ -+ -diff --git a/include/avr/ioa6285.h b/include/avr/ioa6285.h -new file mode 100644 -index 0000000..df86d17 ---- /dev/null -+++ b/include/avr/ioa6285.h -@@ -0,0 +1,691 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATA6285_H_INCLUDED -+#define _AVR_ATA6285_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "ioa6285.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x06) -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x07) -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x08) -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PIND _SFR_IO8(0x09) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0A) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x0B) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+/* Reserved [0x0C..0x0E] */ -+ -+#define CMCR _SFR_IO8(0x0F) -+#define CMM0 0 -+#define CMM1 1 -+#define SRCD 2 -+#define CMONEN 3 -+#define CCS 4 -+#define ECINS 5 -+#define CMCCE 7 -+ -+#define CMSR _SFR_IO8(0x10) -+#define ECF 0 -+ -+#define T2CRA _SFR_IO8(0x11) -+#define T2OTM 0 -+#define T2CTM 1 -+#define T2CR 2 -+#define T2CRM 3 -+#define T2ICS 5 -+#define T2TS 6 -+#define T2E 7 -+ -+#define T2CRB _SFR_IO8(0x12) -+#define T2SCE 0 -+ -+/* Reserved [0x13] */ -+ -+#define T3CRA _SFR_IO8(0x14) -+#define T3AC 0 -+#define T3SCE 1 -+#define T3CR 2 -+#define T3TS 6 -+#define T3E 7 -+ -+/* Reserved [0x15] */ -+ -+#define VMCSR _SFR_IO8(0x16) -+#define VMEN 0 -+#define VMLS0 1 -+#define VMLS1 2 -+#define VMLS2 3 -+#define VMIM 4 -+#define VMF 5 -+#define BODPD 6 -+#define BODLS 7 -+ -+#define PCIFR _SFR_IO8(0x17) -+#define PCIF0 0 -+#define PCIF1 1 -+#define PCIF2 2 -+ -+#define LFFR _SFR_IO8(0x18) -+#define LFWPF 0 -+#define LFBF 1 -+#define LFEDF 2 -+#define LFRF 3 -+ -+#define SSFR _SFR_IO8(0x19) -+#define MSENF 0 -+#define MSENO 1 -+ -+#define T10IFR _SFR_IO8(0x1A) -+#define T0F 0 -+#define T1F 1 -+ -+#define T2IFR _SFR_IO8(0x1B) -+#define T2OFF 0 -+#define T2COF 1 -+#define T2ICF 2 -+#define T2RXF 3 -+#define T2TXF 4 -+#define T2TCF 5 -+ -+#define T3IFR _SFR_IO8(0x1C) -+#define T3OFF 0 -+#define T3COAF 1 -+#define T3COBF 2 -+#define T3ICF 3 -+ -+#define EIFR _SFR_IO8(0x1D) -+#define INTF0 0 -+#define INTF1 1 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEWE 1 -+#define EEMWE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define PCICR _SFR_IO8(0x23) -+#define PCIE0 0 -+#define PCIE1 1 -+#define PCIE2 2 -+ -+#define EIMSK _SFR_IO8(0x24) -+#define INT0 0 -+#define INT1 1 -+ -+/* Reserved [0x25..0x26] */ -+ -+#define SVCR _SFR_IO8(0x27) -+ -+#define SCR _SFR_IO8(0x28) -+#define SMS 0 -+#define SEN0 1 -+#define SEN1 2 -+#define SMEN 3 -+ -+#define SCCR _SFR_IO8(0x29) -+#define SRCC0 0 -+#define SRCC1 1 -+#define SCCS0 2 -+#define SCCS1 3 -+#define SCCS2 4 -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+#define T2MDR _SFR_IO8(0x2F) -+ -+#define LFRR _SFR_IO8(0x30) -+ -+/* Reserved [0x31] */ -+ -+#define LFCDR _SFR_IO8(0x32) -+#define LFDO 0 -+#define LFRST 6 -+#define LFSCE 7 -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+#define TSRF 5 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define IVCE 0 -+#define IVSEL 1 -+#define PUD 4 -+ -+#define LFRB _SFR_IO8(0x36) -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SELFPRGEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+#define T1CR _SFR_IO8(0x38) -+#define T1PS0 0 -+#define T1PS1 1 -+#define T1PS2 2 -+#define T1CS0 3 -+#define T1CS1 4 -+#define T1CS2 5 -+#define T1IE 7 -+ -+#define T0CR _SFR_IO8(0x39) -+#define T0PAS0 0 -+#define T0PAS1 1 -+#define T0PAS2 2 -+#define T0IE 3 -+#define T0PR 4 -+#define T0PBS0 5 -+#define T0PBS1 6 -+#define T0PBS2 7 -+ -+/* Reserved [0x3A] */ -+ -+#define CMIMR _SFR_IO8(0x3B) -+#define ECIE 0 -+ -+#define CLKPR _SFR_IO8(0x3C) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLTPS0 3 -+#define CLTPS1 4 -+#define CLTPS2 5 -+#define CLPCE 7 -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCR _SFR_MEM8(0x60) -+#define WDPS0 0 -+#define WDPS1 1 -+#define WDPS2 2 -+#define WDE 3 -+#define WDCE 4 -+ -+#define SIMSK _SFR_MEM8(0x61) -+#define MSIE 0 -+ -+/* Reserved [0x62..0x63] */ -+ -+#define TSCR _SFR_MEM8(0x64) -+#define TSSD 0 -+ -+#define SRCCAL _SFR_MEM8(0x65) -+ -+#define FRCCAL _SFR_MEM8(0x66) -+ -+#define MSVCAL _SFR_MEM8(0x67) -+ -+/* Reserved [0x68] */ -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+ -+#define PCMSK0 _SFR_MEM8(0x6A) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6B) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+ -+#define PCMSK2 _SFR_MEM8(0x6C) -+#define PCINT16 0 -+#define PCINT17 1 -+#define PCINT18 2 -+#define PCINT19 3 -+#define PCINT20 4 -+#define PCINT21 5 -+#define PCINT22 6 -+#define PCINT23 7 -+ -+/* Reserved [0x6D] */ -+ -+#define T2ICRL _SFR_MEM8(0x6E) -+ -+#define T2ICR _SFR_MEM8(0x6F) -+ -+/* Combine T2CORL and T2CORH */ -+#define T2COR _SFR_MEM16(0x70) -+ -+#define T2CORL _SFR_MEM8(0x70) -+#define T2CORH _SFR_MEM8(0x71) -+ -+#define T2MRA _SFR_MEM8(0x72) -+#define T2CS0 0 -+#define T2CS1 1 -+#define T2CS2 2 -+#define T2CE0 3 -+#define T2CE1 4 -+#define T2CNC 5 -+#define T2TP0 6 -+#define T2TP1 7 -+ -+#define T2MRB _SFR_MEM8(0x73) -+#define T2M0 0 -+#define T2M1 1 -+#define T2M2 2 -+#define T2M3 3 -+#define T2TOP 4 -+#define T2CPOL 6 -+#define T2SSIE 7 -+ -+#define T2IMR _SFR_MEM8(0x74) -+#define T2OIM 0 -+#define T2CIM 1 -+#define T2CPIM 2 -+#define T2RXIM 3 -+#define T2TXIM 4 -+#define T2TCIM 5 -+ -+/* Reserved [0x75] */ -+ -+/* Combine T3ICRL and T3ICRH */ -+#define T3ICR _SFR_MEM16(0x76) -+ -+#define T3ICRL _SFR_MEM8(0x76) -+#define T3ICRH _SFR_MEM8(0x77) -+ -+/* Combine T3CORAL and T3CORAH */ -+#define T3CORA _SFR_MEM16(0x78) -+ -+#define T3CORAL _SFR_MEM8(0x78) -+#define T3CORAH _SFR_MEM8(0x79) -+ -+/* Combine T3CORBL and T3CORBH */ -+#define T3CORB _SFR_MEM16(0x7A) -+ -+#define T3CORBL _SFR_MEM8(0x7A) -+#define T3CORBH _SFR_MEM8(0x7B) -+ -+#define T3MRA _SFR_MEM8(0x7C) -+#define T3CS0 0 -+#define T3CS1 1 -+#define T3CS2 2 -+#define T3CE0 3 -+#define T3CE1 4 -+#define T3CNC 5 -+#define T3ICS0 6 -+#define T3ICS1 7 -+ -+#define T3MRB _SFR_MEM8(0x7D) -+#define T3M0 0 -+#define T3M1 1 -+#define T3M2 2 -+#define T3TOP 4 -+ -+#define T3CRB _SFR_MEM8(0x7E) -+#define T3CTMA 0 -+#define T3SAMA 1 -+#define T3CRMA 2 -+#define T3CTMB 3 -+#define T3SAMB 4 -+#define T3CRMB 5 -+#define T3CPRM 6 -+ -+#define T3IMR _SFR_MEM8(0x7F) -+#define T3OIM 0 -+#define T3CAIM 1 -+#define T3CBIM 2 -+#define T3CPIM 3 -+ -+/* Reserved [0x80] */ -+ -+#define LFIMR _SFR_MEM8(0x81) -+#define LFWIM 0 -+#define LFBIM 1 -+#define LFEIM 2 -+ -+#define LFRCR _SFR_MEM8(0x82) -+#define LFEN 0 -+#define LFBM 1 -+#define LFWM0 2 -+#define LFWM1 3 -+#define LFRSS 4 -+#define LFCS0 5 -+#define LFCS1 6 -+#define LFCS2 7 -+ -+#define LFHCR _SFR_MEM8(0x83) -+ -+/* Combine LFIDCL and LFIDCH */ -+#define LFIDC _SFR_MEM16(0x84) -+ -+#define LFIDCL _SFR_MEM8(0x84) -+#define LFIDCH _SFR_MEM8(0x85) -+ -+/* Combine LFCALL and LFCALH */ -+#define LFCAL _SFR_MEM16(0x86) -+ -+#define LFCALL _SFR_MEM8(0x86) -+#define LFCALH _SFR_MEM8(0x87) -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(3) -+#define PCINT0_vect_num 3 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(4) -+#define PCINT1_vect_num 4 -+ -+/* Pin Change Interrupt Request 2 */ -+#define PCINT2_vect _VECTOR(5) -+#define PCINT2_vect_num 5 -+ -+/* Voltage Monitor Interrupt */ -+#define INTVM_vect _VECTOR(6) -+#define INTVM_vect_num 6 -+ -+/* Sensor Interface Interrupt */ -+#define SENINT_vect _VECTOR(7) -+#define SENINT_vect_num 7 -+ -+/* Timer0 Interval Interrupt */ -+#define INTT0_vect _VECTOR(8) -+#define INTT0_vect_num 8 -+ -+/* LF-Receiver Wake-up Interrupt */ -+#define LFWP_vect _VECTOR(9) -+#define LFWP_vect_num 9 -+ -+/* Timer/Counter3 Capture Event */ -+#define T3CAP_vect _VECTOR(10) -+#define T3CAP_vect_num 10 -+ -+/* Timer/Counter3 Compare Match A */ -+#define T3COMA_vect _VECTOR(11) -+#define T3COMA_vect_num 11 -+ -+/* Timer/Counter3 Compare Match B */ -+#define T3COMB_vect _VECTOR(12) -+#define T3COMB_vect_num 12 -+ -+/* Timer/Counter3 Overflow */ -+#define T3OVF_vect _VECTOR(13) -+#define T3OVF_vect_num 13 -+ -+/* Timer/Counter2 Capture Event */ -+#define T2CAP_vect _VECTOR(14) -+#define T2CAP_vect_num 14 -+ -+/* Timer/Counter2 Compare Match */ -+#define T2COM_vect _VECTOR(15) -+#define T2COM_vect_num 15 -+ -+/* Timer/Counter2 Overflow */ -+#define T2OVF_vect _VECTOR(16) -+#define T2OVF_vect_num 16 -+ -+/* SPI Serial Transfer Complete */ -+#define SPISTC_vect _VECTOR(17) -+#define SPISTC_vect_num 17 -+ -+/* LF Receive Buffer Interrupt */ -+#define LFRXB_vect _VECTOR(18) -+#define LFRXB_vect_num 18 -+ -+/* Timer1 Interval Interrupt */ -+#define INTT1_vect _VECTOR(19) -+#define INTT1_vect_num 19 -+ -+/* Timer2 SSI Receive Buffer Interrupt */ -+#define T2RXB_vect _VECTOR(20) -+#define T2RXB_vect_num 20 -+ -+/* Timer2 SSI Transmit Buffer Interrupt */ -+#define T2TXB_vect _VECTOR(21) -+#define T2TXB_vect_num 21 -+ -+/* Timer2 SSI Transmit Complete Interrupt */ -+#define T2TXC_vect _VECTOR(22) -+#define T2TXC_vect_num 22 -+ -+/* LF-Receiver End of Burst Interrupt */ -+#define LFREOB_vect _VECTOR(23) -+#define LFREOB_vect_num 23 -+ -+/* External Input Clock break down Interrupt */ -+#define EXCM_vect _VECTOR(24) -+#define EXCM_vect_num 24 -+ -+/* EEPROM Ready Interrupt */ -+#define EEREADY_vect _VECTOR(25) -+#define EEREADY_vect_num 25 -+ -+/* Store Program Memory Ready */ -+#define SPM_RDY_vect _VECTOR(26) -+#define SPM_RDY_vect_num 26 -+ -+#define _VECTORS_SIZE 54 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 64 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x1FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 512 -+#define RAMEND 0x02FF -+#define E2START 0 -+#define E2SIZE 320 -+#define E2PAGESIZE 4 -+#define E2END 0x013F -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 2 -+ -+/* Low Fuse Byte */ -+#define FUSE_TSRDI (unsigned char)~_BV(0) -+#define FUSE_BODEN (unsigned char)~_BV(1) -+#define FUSE_FRCFS (unsigned char)~_BV(2) -+#define FUSE_WDRCON (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(4) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_DWEN (unsigned char)~_BV(6) -+#define FUSE_EELOCK (unsigned char)~_BV(7) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x93 -+#define SIGNATURE_2 0x82 -+ -+ -+#endif /* #ifdef _AVR_ATA6285_H_INCLUDED */ -+ -diff --git a/include/avr/ioa6286.h b/include/avr/ioa6286.h -new file mode 100644 -index 0000000..52d72dc ---- /dev/null -+++ b/include/avr/ioa6286.h -@@ -0,0 +1,691 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATA6286_H_INCLUDED -+#define _AVR_ATA6286_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "ioa6286.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x06) -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x07) -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x08) -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PIND _SFR_IO8(0x09) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0A) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x0B) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+/* Reserved [0x0C..0x0E] */ -+ -+#define CMCR _SFR_IO8(0x0F) -+#define CMM0 0 -+#define CMM1 1 -+#define SRCD 2 -+#define CMONEN 3 -+#define CCS 4 -+#define ECINS 5 -+#define CMCCE 7 -+ -+#define CMSR _SFR_IO8(0x10) -+#define ECF 0 -+ -+#define T2CRA _SFR_IO8(0x11) -+#define T2OTM 0 -+#define T2CTM 1 -+#define T2CR 2 -+#define T2CRM 3 -+#define T2ICS 5 -+#define T2TS 6 -+#define T2E 7 -+ -+#define T2CRB _SFR_IO8(0x12) -+#define T2SCE 0 -+ -+/* Reserved [0x13] */ -+ -+#define T3CRA _SFR_IO8(0x14) -+#define T3AC 0 -+#define T3SCE 1 -+#define T3CR 2 -+#define T3TS 6 -+#define T3E 7 -+ -+/* Reserved [0x15] */ -+ -+#define VMCSR _SFR_IO8(0x16) -+#define VMEN 0 -+#define VMLS0 1 -+#define VMLS1 2 -+#define VMLS2 3 -+#define VMIM 4 -+#define VMF 5 -+#define BODPD 6 -+#define BODLS 7 -+ -+#define PCIFR _SFR_IO8(0x17) -+#define PCIF0 0 -+#define PCIF1 1 -+#define PCIF2 2 -+ -+#define LFFR _SFR_IO8(0x18) -+#define LFWPF 0 -+#define LFBF 1 -+#define LFEDF 2 -+#define LFRF 3 -+ -+#define SSFR _SFR_IO8(0x19) -+#define MSENF 0 -+#define MSENO 1 -+ -+#define T10IFR _SFR_IO8(0x1A) -+#define T0F 0 -+#define T1F 1 -+ -+#define T2IFR _SFR_IO8(0x1B) -+#define T2OFF 0 -+#define T2COF 1 -+#define T2ICF 2 -+#define T2RXF 3 -+#define T2TXF 4 -+#define T2TCF 5 -+ -+#define T3IFR _SFR_IO8(0x1C) -+#define T3OFF 0 -+#define T3COAF 1 -+#define T3COBF 2 -+#define T3ICF 3 -+ -+#define EIFR _SFR_IO8(0x1D) -+#define INTF0 0 -+#define INTF1 1 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEWE 1 -+#define EEMWE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define PCICR _SFR_IO8(0x23) -+#define PCIE0 0 -+#define PCIE1 1 -+#define PCIE2 2 -+ -+#define EIMSK _SFR_IO8(0x24) -+#define INT0 0 -+#define INT1 1 -+ -+/* Reserved [0x25..0x26] */ -+ -+#define SVCR _SFR_IO8(0x27) -+ -+#define SCR _SFR_IO8(0x28) -+#define SMS 0 -+#define SEN0 1 -+#define SEN1 2 -+#define SMEN 3 -+ -+#define SCCR _SFR_IO8(0x29) -+#define SRCC0 0 -+#define SRCC1 1 -+#define SCCS0 2 -+#define SCCS1 3 -+#define SCCS2 4 -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+#define T2MDR _SFR_IO8(0x2F) -+ -+#define LFRR _SFR_IO8(0x30) -+ -+/* Reserved [0x31] */ -+ -+#define LFCDR _SFR_IO8(0x32) -+#define LFDO 0 -+#define LFRST 6 -+#define LFSCE 7 -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+#define TSRF 5 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define IVCE 0 -+#define IVSEL 1 -+#define PUD 4 -+ -+#define LFRB _SFR_IO8(0x36) -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SELFPRGEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+#define T1CR _SFR_IO8(0x38) -+#define T1PS0 0 -+#define T1PS1 1 -+#define T1PS2 2 -+#define T1CS0 3 -+#define T1CS1 4 -+#define T1CS2 5 -+#define T1IE 7 -+ -+#define T0CR _SFR_IO8(0x39) -+#define T0PAS0 0 -+#define T0PAS1 1 -+#define T0PAS2 2 -+#define T0IE 3 -+#define T0PR 4 -+#define T0PBS0 5 -+#define T0PBS1 6 -+#define T0PBS2 7 -+ -+/* Reserved [0x3A] */ -+ -+#define CMIMR _SFR_IO8(0x3B) -+#define ECIE 0 -+ -+#define CLKPR _SFR_IO8(0x3C) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLTPS0 3 -+#define CLTPS1 4 -+#define CLTPS2 5 -+#define CLPCE 7 -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCR _SFR_MEM8(0x60) -+#define WDPS0 0 -+#define WDPS1 1 -+#define WDPS2 2 -+#define WDE 3 -+#define WDCE 4 -+ -+#define SIMSK _SFR_MEM8(0x61) -+#define MSIE 0 -+ -+/* Reserved [0x62..0x63] */ -+ -+#define TSCR _SFR_MEM8(0x64) -+#define TSSD 0 -+ -+#define SRCCAL _SFR_MEM8(0x65) -+ -+#define FRCCAL _SFR_MEM8(0x66) -+ -+#define MSVCAL _SFR_MEM8(0x67) -+ -+/* Reserved [0x68] */ -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+ -+#define PCMSK0 _SFR_MEM8(0x6A) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6B) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+ -+#define PCMSK2 _SFR_MEM8(0x6C) -+#define PCINT16 0 -+#define PCINT17 1 -+#define PCINT18 2 -+#define PCINT19 3 -+#define PCINT20 4 -+#define PCINT21 5 -+#define PCINT22 6 -+#define PCINT23 7 -+ -+/* Reserved [0x6D] */ -+ -+#define T2ICRL _SFR_MEM8(0x6E) -+ -+#define T2ICR _SFR_MEM8(0x6F) -+ -+/* Combine T2CORL and T2CORH */ -+#define T2COR _SFR_MEM16(0x70) -+ -+#define T2CORL _SFR_MEM8(0x70) -+#define T2CORH _SFR_MEM8(0x71) -+ -+#define T2MRA _SFR_MEM8(0x72) -+#define T2CS0 0 -+#define T2CS1 1 -+#define T2CS2 2 -+#define T2CE0 3 -+#define T2CE1 4 -+#define T2CNC 5 -+#define T2TP0 6 -+#define T2TP1 7 -+ -+#define T2MRB _SFR_MEM8(0x73) -+#define T2M0 0 -+#define T2M1 1 -+#define T2M2 2 -+#define T2M3 3 -+#define T2TOP 4 -+#define T2CPOL 6 -+#define T2SSIE 7 -+ -+#define T2IMR _SFR_MEM8(0x74) -+#define T2OIM 0 -+#define T2CIM 1 -+#define T2CPIM 2 -+#define T2RXIM 3 -+#define T2TXIM 4 -+#define T2TCIM 5 -+ -+/* Reserved [0x75] */ -+ -+/* Combine T3ICRL and T3ICRH */ -+#define T3ICR _SFR_MEM16(0x76) -+ -+#define T3ICRL _SFR_MEM8(0x76) -+#define T3ICRH _SFR_MEM8(0x77) -+ -+/* Combine T3CORAL and T3CORAH */ -+#define T3CORA _SFR_MEM16(0x78) -+ -+#define T3CORAL _SFR_MEM8(0x78) -+#define T3CORAH _SFR_MEM8(0x79) -+ -+/* Combine T3CORBL and T3CORBH */ -+#define T3CORB _SFR_MEM16(0x7A) -+ -+#define T3CORBL _SFR_MEM8(0x7A) -+#define T3CORBH _SFR_MEM8(0x7B) -+ -+#define T3MRA _SFR_MEM8(0x7C) -+#define T3CS0 0 -+#define T3CS1 1 -+#define T3CS2 2 -+#define T3CE0 3 -+#define T3CE1 4 -+#define T3CNC 5 -+#define T3ICS0 6 -+#define T3ICS1 7 -+ -+#define T3MRB _SFR_MEM8(0x7D) -+#define T3M0 0 -+#define T3M1 1 -+#define T3M2 2 -+#define T3TOP 4 -+ -+#define T3CRB _SFR_MEM8(0x7E) -+#define T3CTMA 0 -+#define T3SAMA 1 -+#define T3CRMA 2 -+#define T3CTMB 3 -+#define T3SAMB 4 -+#define T3CRMB 5 -+#define T3CPRM 6 -+ -+#define T3IMR _SFR_MEM8(0x7F) -+#define T3OIM 0 -+#define T3CAIM 1 -+#define T3CBIM 2 -+#define T3CPIM 3 -+ -+/* Reserved [0x80] */ -+ -+#define LFIMR _SFR_MEM8(0x81) -+#define LFWIM 0 -+#define LFBIM 1 -+#define LFEIM 2 -+ -+#define LFRCR _SFR_MEM8(0x82) -+#define LFEN 0 -+#define LFBM 1 -+#define LFWM0 2 -+#define LFWM1 3 -+#define LFRSS 4 -+#define LFCS0 5 -+#define LFCS1 6 -+#define LFCS2 7 -+ -+#define LFHCR _SFR_MEM8(0x83) -+ -+/* Combine LFIDCL and LFIDCH */ -+#define LFIDC _SFR_MEM16(0x84) -+ -+#define LFIDCL _SFR_MEM8(0x84) -+#define LFIDCH _SFR_MEM8(0x85) -+ -+/* Combine LFCALL and LFCALH */ -+#define LFCAL _SFR_MEM16(0x86) -+ -+#define LFCALL _SFR_MEM8(0x86) -+#define LFCALH _SFR_MEM8(0x87) -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(3) -+#define PCINT0_vect_num 3 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(4) -+#define PCINT1_vect_num 4 -+ -+/* Pin Change Interrupt Request 2 */ -+#define PCINT2_vect _VECTOR(5) -+#define PCINT2_vect_num 5 -+ -+/* Voltage Monitor Interrupt */ -+#define INTVM_vect _VECTOR(6) -+#define INTVM_vect_num 6 -+ -+/* Sensor Interface Interrupt */ -+#define SENINT_vect _VECTOR(7) -+#define SENINT_vect_num 7 -+ -+/* Timer0 Interval Interrupt */ -+#define INTT0_vect _VECTOR(8) -+#define INTT0_vect_num 8 -+ -+/* LF-Receiver Wake-up Interrupt */ -+#define LFWP_vect _VECTOR(9) -+#define LFWP_vect_num 9 -+ -+/* Timer/Counter3 Capture Event */ -+#define T3CAP_vect _VECTOR(10) -+#define T3CAP_vect_num 10 -+ -+/* Timer/Counter3 Compare Match A */ -+#define T3COMA_vect _VECTOR(11) -+#define T3COMA_vect_num 11 -+ -+/* Timer/Counter3 Compare Match B */ -+#define T3COMB_vect _VECTOR(12) -+#define T3COMB_vect_num 12 -+ -+/* Timer/Counter3 Overflow */ -+#define T3OVF_vect _VECTOR(13) -+#define T3OVF_vect_num 13 -+ -+/* Timer/Counter2 Capture Event */ -+#define T2CAP_vect _VECTOR(14) -+#define T2CAP_vect_num 14 -+ -+/* Timer/Counter2 Compare Match */ -+#define T2COM_vect _VECTOR(15) -+#define T2COM_vect_num 15 -+ -+/* Timer/Counter2 Overflow */ -+#define T2OVF_vect _VECTOR(16) -+#define T2OVF_vect_num 16 -+ -+/* SPI Serial Transfer Complete */ -+#define SPISTC_vect _VECTOR(17) -+#define SPISTC_vect_num 17 -+ -+/* LF Receive Buffer Interrupt */ -+#define LFRXB_vect _VECTOR(18) -+#define LFRXB_vect_num 18 -+ -+/* Timer1 Interval Interrupt */ -+#define INTT1_vect _VECTOR(19) -+#define INTT1_vect_num 19 -+ -+/* Timer2 SSI Receive Buffer Interrupt */ -+#define T2RXB_vect _VECTOR(20) -+#define T2RXB_vect_num 20 -+ -+/* Timer2 SSI Transmit Buffer Interrupt */ -+#define T2TXB_vect _VECTOR(21) -+#define T2TXB_vect_num 21 -+ -+/* Timer2 SSI Transmit Complete Interrupt */ -+#define T2TXC_vect _VECTOR(22) -+#define T2TXC_vect_num 22 -+ -+/* LF-Receiver End of Burst Interrupt */ -+#define LFREOB_vect _VECTOR(23) -+#define LFREOB_vect_num 23 -+ -+/* External Input Clock break down Interrupt */ -+#define EXCM_vect _VECTOR(24) -+#define EXCM_vect_num 24 -+ -+/* EEPROM Ready Interrupt */ -+#define EEREADY_vect _VECTOR(25) -+#define EEREADY_vect_num 25 -+ -+/* Store Program Memory Ready */ -+#define SPM_RDY_vect _VECTOR(26) -+#define SPM_RDY_vect_num 26 -+ -+#define _VECTORS_SIZE 54 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 64 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x1FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 512 -+#define RAMEND 0x02FF -+#define E2START 0 -+#define E2SIZE 320 -+#define E2PAGESIZE 4 -+#define E2END 0x013F -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 2 -+ -+/* Low Fuse Byte */ -+#define FUSE_TSRDI (unsigned char)~_BV(0) -+#define FUSE_BODEN (unsigned char)~_BV(1) -+#define FUSE_FRCFS (unsigned char)~_BV(2) -+#define FUSE_WDRCON (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(4) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_DWEN (unsigned char)~_BV(6) -+#define FUSE_EELOCK (unsigned char)~_BV(7) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x93 -+#define SIGNATURE_2 0x82 -+ -+ -+#endif /* #ifdef _AVR_ATA6286_H_INCLUDED */ -+ -diff --git a/include/avr/ioa6612c.h b/include/avr/ioa6612c.h -new file mode 100644 -index 0000000..66ed988 ---- /dev/null -+++ b/include/avr/ioa6612c.h -@@ -0,0 +1,771 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATA6612C_H_INCLUDED -+#define _AVR_ATA6612C_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "ioa6612c.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDB0 0 -+#define DDB1 1 -+#define DDB2 2 -+#define DDB3 3 -+#define DDB4 4 -+#define DDB5 5 -+#define DDB6 6 -+#define DDB7 7 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x06) -+#define PINC6 6 -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x07) -+#define DDC0 0 -+#define DDC1 1 -+#define DDC2 2 -+#define DDC3 3 -+#define DDC4 4 -+#define DDC5 5 -+#define DDC6 6 -+ -+#define PORTC _SFR_IO8(0x08) -+#define PORTC6 6 -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PIND _SFR_IO8(0x09) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0A) -+#define DDD0 0 -+#define DDD1 1 -+#define DDD2 2 -+#define DDD3 3 -+#define DDD4 4 -+#define DDD5 5 -+#define DDD6 6 -+#define DDD7 7 -+ -+#define PORTD _SFR_IO8(0x0B) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+/* Reserved [0x0C..0x14] */ -+ -+#define TIFR0 _SFR_IO8(0x15) -+#define TOV0 0 -+#define OCF0A 1 -+#define OCF0B 2 -+ -+#define TIFR1 _SFR_IO8(0x16) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define ICF1 5 -+ -+#define TIFR2 _SFR_IO8(0x17) -+#define TOV2 0 -+#define OCF2A 1 -+#define OCF2B 2 -+ -+/* Reserved [0x18..0x1A] */ -+ -+#define PCIFR _SFR_IO8(0x1B) -+#define PCIF0 0 -+#define PCIF1 1 -+#define PCIF2 2 -+ -+#define EIFR _SFR_IO8(0x1C) -+#define INTF0 0 -+#define INTF1 1 -+ -+#define EIMSK _SFR_IO8(0x1D) -+#define INT0 0 -+#define INT1 1 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEPE 1 -+#define EEMPE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSRSYNC 0 -+#define TSM 7 -+#define PSRASY 1 -+ -+#define TCCR0A _SFR_IO8(0x24) -+#define WGM00 0 -+#define WGM01 1 -+#define COM0B0 4 -+#define COM0B1 5 -+#define COM0A0 6 -+#define COM0A1 7 -+ -+#define TCCR0B _SFR_IO8(0x25) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define WGM02 3 -+#define FOC0B 6 -+#define FOC0A 7 -+ -+#define TCNT0 _SFR_IO8(0x26) -+ -+#define OCR0A _SFR_IO8(0x27) -+ -+#define OCR0B _SFR_IO8(0x28) -+ -+/* Reserved [0x29] */ -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+/* Reserved [0x2F] */ -+ -+#define ACSR _SFR_IO8(0x30) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACBG 6 -+#define ACD 7 -+ -+/* Reserved [0x31..0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define IVCE 0 -+#define IVSEL 1 -+#define PUD 4 -+ -+/* Reserved [0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SELFPRGEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+/* Reserved [0x38..0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCSR _SFR_MEM8(0x60) -+#define WDE 3 -+#define WDCE 4 -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDP3 5 -+#define WDIE 6 -+#define WDIF 7 -+ -+#define CLKPR _SFR_MEM8(0x61) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+#define CLKPCE 7 -+ -+/* Reserved [0x62..0x63] */ -+ -+#define PRR _SFR_MEM8(0x64) -+#define PRADC 0 -+#define PRUSART0 1 -+#define PRSPI 2 -+#define PRTIM1 3 -+#define PRTIM0 5 -+#define PRTIM2 6 -+#define PRTWI 7 -+ -+/* Reserved [0x65] */ -+ -+#define OSCCAL _SFR_MEM8(0x66) -+#define OSCCAL0 0 -+#define OSCCAL1 1 -+#define OSCCAL2 2 -+#define OSCCAL3 3 -+#define OSCCAL4 4 -+#define OSCCAL5 5 -+#define OSCCAL6 6 -+#define OSCCAL7 7 -+ -+/* Reserved [0x67] */ -+ -+#define PCICR _SFR_MEM8(0x68) -+#define PCIE0 0 -+#define PCIE1 1 -+#define PCIE2 2 -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+ -+/* Reserved [0x6A] */ -+ -+#define PCMSK0 _SFR_MEM8(0x6B) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6C) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+#define PCINT14 6 -+ -+#define PCMSK2 _SFR_MEM8(0x6D) -+#define PCINT16 0 -+#define PCINT17 1 -+#define PCINT18 2 -+#define PCINT19 3 -+#define PCINT20 4 -+#define PCINT21 5 -+#define PCINT22 6 -+#define PCINT23 7 -+ -+#define TIMSK0 _SFR_MEM8(0x6E) -+#define TOIE0 0 -+#define OCIE0A 1 -+#define OCIE0B 2 -+ -+#define TIMSK1 _SFR_MEM8(0x6F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define ICIE1 5 -+ -+#define TIMSK2 _SFR_MEM8(0x70) -+#define TOIE2 0 -+#define OCIE2A 1 -+#define OCIE2B 2 -+ -+/* Reserved [0x71..0x77] */ -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_MEM16(0x78) -+#endif -+#define ADCW _SFR_MEM16(0x78) -+ -+#define ADCL _SFR_MEM8(0x78) -+#define ADCH _SFR_MEM8(0x79) -+ -+#define ADCSRA _SFR_MEM8(0x7A) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADCSRB _SFR_MEM8(0x7B) -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+#define ACME 6 -+ -+#define ADMUX _SFR_MEM8(0x7C) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+/* Reserved [0x7D] */ -+ -+#define DIDR0 _SFR_MEM8(0x7E) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+ -+#define DIDR1 _SFR_MEM8(0x7F) -+#define AIN0D 0 -+#define AIN1D 1 -+ -+#define TCCR1A _SFR_MEM8(0x80) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR1B _SFR_MEM8(0x81) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1C _SFR_MEM8(0x82) -+#define FOC1B 6 -+#define FOC1A 7 -+ -+/* Reserved [0x83] */ -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x84) -+ -+#define TCNT1L _SFR_MEM8(0x84) -+#define TCNT1H _SFR_MEM8(0x85) -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x86) -+ -+#define ICR1L _SFR_MEM8(0x86) -+#define ICR1H _SFR_MEM8(0x87) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_MEM16(0x88) -+ -+#define OCR1AL _SFR_MEM8(0x88) -+#define OCR1AH _SFR_MEM8(0x89) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_MEM16(0x8A) -+ -+#define OCR1BL _SFR_MEM8(0x8A) -+#define OCR1BH _SFR_MEM8(0x8B) -+ -+/* Reserved [0x8C..0xAF] */ -+ -+#define TCCR2A _SFR_MEM8(0xB0) -+#define WGM20 0 -+#define WGM21 1 -+#define COM2B0 4 -+#define COM2B1 5 -+#define COM2A0 6 -+#define COM2A1 7 -+ -+#define TCCR2B _SFR_MEM8(0xB1) -+#define CS20 0 -+#define CS21 1 -+#define CS22 2 -+#define WGM22 3 -+#define FOC2B 6 -+#define FOC2A 7 -+ -+#define TCNT2 _SFR_MEM8(0xB2) -+ -+#define OCR2A _SFR_MEM8(0xB3) -+ -+#define OCR2B _SFR_MEM8(0xB4) -+ -+/* Reserved [0xB5] */ -+ -+#define ASSR _SFR_MEM8(0xB6) -+#define TCR2BUB 0 -+#define TCR2AUB 1 -+#define OCR2BUB 2 -+#define OCR2AUB 3 -+#define TCN2UB 4 -+#define AS2 5 -+#define EXCLK 6 -+ -+/* Reserved [0xB7] */ -+ -+#define TWBR _SFR_MEM8(0xB8) -+ -+#define TWSR _SFR_MEM8(0xB9) -+#define TWPS0 0 -+#define TWPS1 1 -+#define TWS3 3 -+#define TWS4 4 -+#define TWS5 5 -+#define TWS6 6 -+#define TWS7 7 -+ -+#define TWAR _SFR_MEM8(0xBA) -+#define TWGCE 0 -+#define TWA0 1 -+#define TWA1 2 -+#define TWA2 3 -+#define TWA3 4 -+#define TWA4 5 -+#define TWA5 6 -+#define TWA6 7 -+ -+#define TWDR _SFR_MEM8(0xBB) -+ -+#define TWCR _SFR_MEM8(0xBC) -+#define TWIE 0 -+#define TWEN 2 -+#define TWWC 3 -+#define TWSTO 4 -+#define TWSTA 5 -+#define TWEA 6 -+#define TWINT 7 -+ -+#define TWAMR _SFR_MEM8(0xBD) -+#define TWAM0 1 -+#define TWAM1 2 -+#define TWAM2 3 -+#define TWAM3 4 -+#define TWAM4 5 -+#define TWAM5 6 -+#define TWAM6 7 -+ -+/* Reserved [0xBE..0xBF] */ -+ -+#define UCSR0A _SFR_MEM8(0xC0) -+#define MPCM0 0 -+#define U2X0 1 -+#define UPE0 2 -+#define DOR0 3 -+#define FE0 4 -+#define UDRE0 5 -+#define TXC0 6 -+#define RXC0 7 -+ -+#define UCSR0B _SFR_MEM8(0xC1) -+#define TXB80 0 -+#define RXB80 1 -+#define UCSZ02 2 -+#define TXEN0 3 -+#define RXEN0 4 -+#define UDRIE0 5 -+#define TXCIE0 6 -+#define RXCIE0 7 -+ -+#define UCSR0C _SFR_MEM8(0xC2) -+#define UCPOL0 0 -+#define UCPHA0 1 -+#define UDORD0 2 -+#define UCSZ00 1 -+#define UCSZ01 2 -+#define USBS0 3 -+#define UPM00 4 -+#define UPM01 5 -+#define UMSEL00 6 -+#define UMSEL01 7 -+ -+/* Reserved [0xC3] */ -+ -+/* Combine UBRR0L and UBRR0H */ -+#define UBRR0 _SFR_MEM16(0xC4) -+ -+#define UBRR0L _SFR_MEM8(0xC4) -+#define UBRR0H _SFR_MEM8(0xC5) -+ -+#define UDR0 _SFR_MEM8(0xC6) -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(3) -+#define PCINT0_vect_num 3 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT1_vect _VECTOR(4) -+#define PCINT1_vect_num 4 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT2_vect _VECTOR(5) -+#define PCINT2_vect_num 5 -+ -+/* Watchdog Time-out Interrupt */ -+#define WDT_vect _VECTOR(6) -+#define WDT_vect_num 6 -+ -+/* Timer/Counter2 Compare Match A */ -+#define TIMER2_COMPA_vect _VECTOR(7) -+#define TIMER2_COMPA_vect_num 7 -+ -+/* Timer/Counter2 Compare Match A */ -+#define TIMER2_COMPB_vect _VECTOR(8) -+#define TIMER2_COMPB_vect_num 8 -+ -+/* Timer/Counter2 Overflow */ -+#define TIMER2_OVF_vect _VECTOR(9) -+#define TIMER2_OVF_vect_num 9 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(10) -+#define TIMER1_CAPT_vect_num 10 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(11) -+#define TIMER1_COMPA_vect_num 11 -+ -+/* Timer/Counter1 Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(12) -+#define TIMER1_COMPB_vect_num 12 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(13) -+#define TIMER1_OVF_vect_num 13 -+ -+/* TimerCounter0 Compare Match A */ -+#define TIMER0_COMPA_vect _VECTOR(14) -+#define TIMER0_COMPA_vect_num 14 -+ -+/* TimerCounter0 Compare Match B */ -+#define TIMER0_COMPB_vect _VECTOR(15) -+#define TIMER0_COMPB_vect_num 15 -+ -+/* Timer/Couner0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(16) -+#define TIMER0_OVF_vect_num 16 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(17) -+#define SPI_STC_vect_num 17 -+ -+/* USART Rx Complete */ -+#define USART_RX_vect _VECTOR(18) -+#define USART_RX_vect_num 18 -+ -+/* USART, Data Register Empty */ -+#define USART_UDRE_vect _VECTOR(19) -+#define USART_UDRE_vect_num 19 -+ -+/* USART Tx Complete */ -+#define USART_TX_vect _VECTOR(20) -+#define USART_TX_vect_num 20 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(21) -+#define ADC_vect_num 21 -+ -+/* EEPROM Ready */ -+#define EE_READY_vect _VECTOR(22) -+#define EE_READY_vect_num 22 -+ -+/* Analog Comparator */ -+#define ANALOG_COMP_vect _VECTOR(23) -+#define ANALOG_COMP_vect_num 23 -+ -+/* Two-wire Serial Interface */ -+#define TWI_vect _VECTOR(24) -+#define TWI_vect_num 24 -+ -+/* Store Program Memory Read */ -+#define SPM_Ready_vect _VECTOR(25) -+#define SPM_Ready_vect_num 25 -+ -+#define _VECTORS_SIZE 52 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 64 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x1FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 1024 -+#define RAMEND 0x04FF -+#define E2START 0 -+#define E2SIZE 512 -+#define E2PAGESIZE 4 -+#define E2END 0x01FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -+#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_DWEN (unsigned char)~_BV(6) -+#define FUSE_RSTDISBL (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x93 -+#define SIGNATURE_2 0x0A -+ -+ -+#endif /* #ifdef _AVR_ATA6612C_H_INCLUDED */ -+ -diff --git a/include/avr/ioa6613c.h b/include/avr/ioa6613c.h -new file mode 100644 -index 0000000..bc6345f ---- /dev/null -+++ b/include/avr/ioa6613c.h -@@ -0,0 +1,771 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATA6613C_H_INCLUDED -+#define _AVR_ATA6613C_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "ioa6613c.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDB0 0 -+#define DDB1 1 -+#define DDB2 2 -+#define DDB3 3 -+#define DDB4 4 -+#define DDB5 5 -+#define DDB6 6 -+#define DDB7 7 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x06) -+#define PINC6 6 -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x07) -+#define DDC0 0 -+#define DDC1 1 -+#define DDC2 2 -+#define DDC3 3 -+#define DDC4 4 -+#define DDC5 5 -+#define DDC6 6 -+ -+#define PORTC _SFR_IO8(0x08) -+#define PORTC6 6 -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PIND _SFR_IO8(0x09) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0A) -+#define DDD0 0 -+#define DDD1 1 -+#define DDD2 2 -+#define DDD3 3 -+#define DDD4 4 -+#define DDD5 5 -+#define DDD6 6 -+#define DDD7 7 -+ -+#define PORTD _SFR_IO8(0x0B) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+/* Reserved [0x0C..0x14] */ -+ -+#define TIFR0 _SFR_IO8(0x15) -+#define TOV0 0 -+#define OCF0A 1 -+#define OCF0B 2 -+ -+#define TIFR1 _SFR_IO8(0x16) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define ICF1 5 -+ -+#define TIFR2 _SFR_IO8(0x17) -+#define TOV2 0 -+#define OCF2A 1 -+#define OCF2B 2 -+ -+/* Reserved [0x18..0x1A] */ -+ -+#define PCIFR _SFR_IO8(0x1B) -+#define PCIF0 0 -+#define PCIF1 1 -+#define PCIF2 2 -+ -+#define EIFR _SFR_IO8(0x1C) -+#define INTF0 0 -+#define INTF1 1 -+ -+#define EIMSK _SFR_IO8(0x1D) -+#define INT0 0 -+#define INT1 1 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEPE 1 -+#define EEMPE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSRSYNC 0 -+#define TSM 7 -+#define PSRASY 1 -+ -+#define TCCR0A _SFR_IO8(0x24) -+#define WGM00 0 -+#define WGM01 1 -+#define COM0B0 4 -+#define COM0B1 5 -+#define COM0A0 6 -+#define COM0A1 7 -+ -+#define TCCR0B _SFR_IO8(0x25) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define WGM02 3 -+#define FOC0B 6 -+#define FOC0A 7 -+ -+#define TCNT0 _SFR_IO8(0x26) -+ -+#define OCR0A _SFR_IO8(0x27) -+ -+#define OCR0B _SFR_IO8(0x28) -+ -+/* Reserved [0x29] */ -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+/* Reserved [0x2F] */ -+ -+#define ACSR _SFR_IO8(0x30) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACBG 6 -+#define ACD 7 -+ -+/* Reserved [0x31..0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define IVCE 0 -+#define IVSEL 1 -+#define PUD 4 -+ -+/* Reserved [0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SELFPRGEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+/* Reserved [0x38..0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCSR _SFR_MEM8(0x60) -+#define WDE 3 -+#define WDCE 4 -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDP3 5 -+#define WDIE 6 -+#define WDIF 7 -+ -+#define CLKPR _SFR_MEM8(0x61) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+#define CLKPCE 7 -+ -+/* Reserved [0x62..0x63] */ -+ -+#define PRR _SFR_MEM8(0x64) -+#define PRADC 0 -+#define PRUSART0 1 -+#define PRSPI 2 -+#define PRTIM1 3 -+#define PRTIM0 5 -+#define PRTIM2 6 -+#define PRTWI 7 -+ -+/* Reserved [0x65] */ -+ -+#define OSCCAL _SFR_MEM8(0x66) -+#define OSCCAL0 0 -+#define OSCCAL1 1 -+#define OSCCAL2 2 -+#define OSCCAL3 3 -+#define OSCCAL4 4 -+#define OSCCAL5 5 -+#define OSCCAL6 6 -+#define OSCCAL7 7 -+ -+/* Reserved [0x67] */ -+ -+#define PCICR _SFR_MEM8(0x68) -+#define PCIE0 0 -+#define PCIE1 1 -+#define PCIE2 2 -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+ -+/* Reserved [0x6A] */ -+ -+#define PCMSK0 _SFR_MEM8(0x6B) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6C) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+#define PCINT14 6 -+ -+#define PCMSK2 _SFR_MEM8(0x6D) -+#define PCINT16 0 -+#define PCINT17 1 -+#define PCINT18 2 -+#define PCINT19 3 -+#define PCINT20 4 -+#define PCINT21 5 -+#define PCINT22 6 -+#define PCINT23 7 -+ -+#define TIMSK0 _SFR_MEM8(0x6E) -+#define TOIE0 0 -+#define OCIE0A 1 -+#define OCIE0B 2 -+ -+#define TIMSK1 _SFR_MEM8(0x6F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define ICIE1 5 -+ -+#define TIMSK2 _SFR_MEM8(0x70) -+#define TOIE2 0 -+#define OCIE2A 1 -+#define OCIE2B 2 -+ -+/* Reserved [0x71..0x77] */ -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_MEM16(0x78) -+#endif -+#define ADCW _SFR_MEM16(0x78) -+ -+#define ADCL _SFR_MEM8(0x78) -+#define ADCH _SFR_MEM8(0x79) -+ -+#define ADCSRA _SFR_MEM8(0x7A) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADCSRB _SFR_MEM8(0x7B) -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+#define ACME 6 -+ -+#define ADMUX _SFR_MEM8(0x7C) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+/* Reserved [0x7D] */ -+ -+#define DIDR0 _SFR_MEM8(0x7E) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+ -+#define DIDR1 _SFR_MEM8(0x7F) -+#define AIN0D 0 -+#define AIN1D 1 -+ -+#define TCCR1A _SFR_MEM8(0x80) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR1B _SFR_MEM8(0x81) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1C _SFR_MEM8(0x82) -+#define FOC1B 6 -+#define FOC1A 7 -+ -+/* Reserved [0x83] */ -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x84) -+ -+#define TCNT1L _SFR_MEM8(0x84) -+#define TCNT1H _SFR_MEM8(0x85) -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x86) -+ -+#define ICR1L _SFR_MEM8(0x86) -+#define ICR1H _SFR_MEM8(0x87) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_MEM16(0x88) -+ -+#define OCR1AL _SFR_MEM8(0x88) -+#define OCR1AH _SFR_MEM8(0x89) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_MEM16(0x8A) -+ -+#define OCR1BL _SFR_MEM8(0x8A) -+#define OCR1BH _SFR_MEM8(0x8B) -+ -+/* Reserved [0x8C..0xAF] */ -+ -+#define TCCR2A _SFR_MEM8(0xB0) -+#define WGM20 0 -+#define WGM21 1 -+#define COM2B0 4 -+#define COM2B1 5 -+#define COM2A0 6 -+#define COM2A1 7 -+ -+#define TCCR2B _SFR_MEM8(0xB1) -+#define CS20 0 -+#define CS21 1 -+#define CS22 2 -+#define WGM22 3 -+#define FOC2B 6 -+#define FOC2A 7 -+ -+#define TCNT2 _SFR_MEM8(0xB2) -+ -+#define OCR2A _SFR_MEM8(0xB3) -+ -+#define OCR2B _SFR_MEM8(0xB4) -+ -+/* Reserved [0xB5] */ -+ -+#define ASSR _SFR_MEM8(0xB6) -+#define TCR2BUB 0 -+#define TCR2AUB 1 -+#define OCR2BUB 2 -+#define OCR2AUB 3 -+#define TCN2UB 4 -+#define AS2 5 -+#define EXCLK 6 -+ -+/* Reserved [0xB7] */ -+ -+#define TWBR _SFR_MEM8(0xB8) -+ -+#define TWSR _SFR_MEM8(0xB9) -+#define TWPS0 0 -+#define TWPS1 1 -+#define TWS3 3 -+#define TWS4 4 -+#define TWS5 5 -+#define TWS6 6 -+#define TWS7 7 -+ -+#define TWAR _SFR_MEM8(0xBA) -+#define TWGCE 0 -+#define TWA0 1 -+#define TWA1 2 -+#define TWA2 3 -+#define TWA3 4 -+#define TWA4 5 -+#define TWA5 6 -+#define TWA6 7 -+ -+#define TWDR _SFR_MEM8(0xBB) -+ -+#define TWCR _SFR_MEM8(0xBC) -+#define TWIE 0 -+#define TWEN 2 -+#define TWWC 3 -+#define TWSTO 4 -+#define TWSTA 5 -+#define TWEA 6 -+#define TWINT 7 -+ -+#define TWAMR _SFR_MEM8(0xBD) -+#define TWAM0 1 -+#define TWAM1 2 -+#define TWAM2 3 -+#define TWAM3 4 -+#define TWAM4 5 -+#define TWAM5 6 -+#define TWAM6 7 -+ -+/* Reserved [0xBE..0xBF] */ -+ -+#define UCSR0A _SFR_MEM8(0xC0) -+#define MPCM0 0 -+#define U2X0 1 -+#define UPE0 2 -+#define DOR0 3 -+#define FE0 4 -+#define UDRE0 5 -+#define TXC0 6 -+#define RXC0 7 -+ -+#define UCSR0B _SFR_MEM8(0xC1) -+#define TXB80 0 -+#define RXB80 1 -+#define UCSZ02 2 -+#define TXEN0 3 -+#define RXEN0 4 -+#define UDRIE0 5 -+#define TXCIE0 6 -+#define RXCIE0 7 -+ -+#define UCSR0C _SFR_MEM8(0xC2) -+#define UCPOL0 0 -+#define UCPHA0 1 -+#define UDORD0 2 -+#define UCSZ00 1 -+#define UCSZ01 2 -+#define USBS0 3 -+#define UPM00 4 -+#define UPM01 5 -+#define UMSEL00 6 -+#define UMSEL01 7 -+ -+/* Reserved [0xC3] */ -+ -+/* Combine UBRR0L and UBRR0H */ -+#define UBRR0 _SFR_MEM16(0xC4) -+ -+#define UBRR0L _SFR_MEM8(0xC4) -+#define UBRR0H _SFR_MEM8(0xC5) -+ -+#define UDR0 _SFR_MEM8(0xC6) -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(3) -+#define PCINT0_vect_num 3 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT1_vect _VECTOR(4) -+#define PCINT1_vect_num 4 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT2_vect _VECTOR(5) -+#define PCINT2_vect_num 5 -+ -+/* Watchdog Time-out Interrupt */ -+#define WDT_vect _VECTOR(6) -+#define WDT_vect_num 6 -+ -+/* Timer/Counter2 Compare Match A */ -+#define TIMER2_COMPA_vect _VECTOR(7) -+#define TIMER2_COMPA_vect_num 7 -+ -+/* Timer/Counter2 Compare Match A */ -+#define TIMER2_COMPB_vect _VECTOR(8) -+#define TIMER2_COMPB_vect_num 8 -+ -+/* Timer/Counter2 Overflow */ -+#define TIMER2_OVF_vect _VECTOR(9) -+#define TIMER2_OVF_vect_num 9 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(10) -+#define TIMER1_CAPT_vect_num 10 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(11) -+#define TIMER1_COMPA_vect_num 11 -+ -+/* Timer/Counter1 Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(12) -+#define TIMER1_COMPB_vect_num 12 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(13) -+#define TIMER1_OVF_vect_num 13 -+ -+/* TimerCounter0 Compare Match A */ -+#define TIMER0_COMPA_vect _VECTOR(14) -+#define TIMER0_COMPA_vect_num 14 -+ -+/* TimerCounter0 Compare Match B */ -+#define TIMER0_COMPB_vect _VECTOR(15) -+#define TIMER0_COMPB_vect_num 15 -+ -+/* Timer/Couner0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(16) -+#define TIMER0_OVF_vect_num 16 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(17) -+#define SPI_STC_vect_num 17 -+ -+/* USART Rx Complete */ -+#define USART_RX_vect _VECTOR(18) -+#define USART_RX_vect_num 18 -+ -+/* USART, Data Register Empty */ -+#define USART_UDRE_vect _VECTOR(19) -+#define USART_UDRE_vect_num 19 -+ -+/* USART Tx Complete */ -+#define USART_TX_vect _VECTOR(20) -+#define USART_TX_vect_num 20 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(21) -+#define ADC_vect_num 21 -+ -+/* EEPROM Ready */ -+#define EE_READY_vect _VECTOR(22) -+#define EE_READY_vect_num 22 -+ -+/* Analog Comparator */ -+#define ANALOG_COMP_vect _VECTOR(23) -+#define ANALOG_COMP_vect_num 23 -+ -+/* Two-wire Serial Interface */ -+#define TWI_vect _VECTOR(24) -+#define TWI_vect_num 24 -+ -+/* Store Program Memory Read */ -+#define SPM_Ready_vect _VECTOR(25) -+#define SPM_Ready_vect_num 25 -+ -+#define _VECTORS_SIZE 104 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 128 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x3FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 1024 -+#define RAMEND 0x04FF -+#define E2START 0 -+#define E2SIZE 512 -+#define E2PAGESIZE 4 -+#define E2END 0x01FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -+#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_DWEN (unsigned char)~_BV(6) -+#define FUSE_RSTDISBL (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x94 -+#define SIGNATURE_2 0x06 -+ -+ -+#endif /* #ifdef _AVR_ATA6613C_H_INCLUDED */ -+ -diff --git a/include/avr/ioa6614q.h b/include/avr/ioa6614q.h -new file mode 100644 -index 0000000..01dc4af ---- /dev/null -+++ b/include/avr/ioa6614q.h -@@ -0,0 +1,773 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATA6614Q_H_INCLUDED -+#define _AVR_ATA6614Q_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "ioa6614q.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDB0 0 -+#define DDB1 1 -+#define DDB2 2 -+#define DDB3 3 -+#define DDB4 4 -+#define DDB5 5 -+#define DDB6 6 -+#define DDB7 7 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x06) -+#define PINC6 6 -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x07) -+#define DDC0 0 -+#define DDC1 1 -+#define DDC2 2 -+#define DDC3 3 -+#define DDC4 4 -+#define DDC5 5 -+#define DDC6 6 -+ -+#define PORTC _SFR_IO8(0x08) -+#define PORTC6 6 -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PIND _SFR_IO8(0x09) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0A) -+#define DDD0 0 -+#define DDD1 1 -+#define DDD2 2 -+#define DDD3 3 -+#define DDD4 4 -+#define DDD5 5 -+#define DDD6 6 -+#define DDD7 7 -+ -+#define PORTD _SFR_IO8(0x0B) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+/* Reserved [0x0C..0x14] */ -+ -+#define TIFR0 _SFR_IO8(0x15) -+#define TOV0 0 -+#define OCF0A 1 -+#define OCF0B 2 -+ -+#define TIFR1 _SFR_IO8(0x16) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define ICF1 5 -+ -+#define TIFR2 _SFR_IO8(0x17) -+#define TOV2 0 -+#define OCF2A 1 -+#define OCF2B 2 -+ -+/* Reserved [0x18..0x1A] */ -+ -+#define PCIFR _SFR_IO8(0x1B) -+#define PCIF0 0 -+#define PCIF1 1 -+#define PCIF2 2 -+ -+#define EIFR _SFR_IO8(0x1C) -+#define INTF0 0 -+#define INTF1 1 -+ -+#define EIMSK _SFR_IO8(0x1D) -+#define INT0 0 -+#define INT1 1 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEPE 1 -+#define EEMPE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSRSYNC 0 -+#define TSM 7 -+#define PSRASY 1 -+ -+#define TCCR0A _SFR_IO8(0x24) -+#define WGM00 0 -+#define WGM01 1 -+#define COM0B0 4 -+#define COM0B1 5 -+#define COM0A0 6 -+#define COM0A1 7 -+ -+#define TCCR0B _SFR_IO8(0x25) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define WGM02 3 -+#define FOC0B 6 -+#define FOC0A 7 -+ -+#define TCNT0 _SFR_IO8(0x26) -+ -+#define OCR0A _SFR_IO8(0x27) -+ -+#define OCR0B _SFR_IO8(0x28) -+ -+/* Reserved [0x29] */ -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+/* Reserved [0x2F] */ -+ -+#define ACSR _SFR_IO8(0x30) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACBG 6 -+#define ACD 7 -+ -+/* Reserved [0x31..0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define IVCE 0 -+#define IVSEL 1 -+#define PUD 4 -+#define BODSE 5 -+#define BODS 6 -+ -+/* Reserved [0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SELFPRGEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+/* Reserved [0x38..0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCSR _SFR_MEM8(0x60) -+#define WDE 3 -+#define WDCE 4 -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDP3 5 -+#define WDIE 6 -+#define WDIF 7 -+ -+#define CLKPR _SFR_MEM8(0x61) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+#define CLKPCE 7 -+ -+/* Reserved [0x62..0x63] */ -+ -+#define PRR _SFR_MEM8(0x64) -+#define PRADC 0 -+#define PRUSART0 1 -+#define PRSPI 2 -+#define PRTIM1 3 -+#define PRTIM0 5 -+#define PRTIM2 6 -+#define PRTWI 7 -+ -+/* Reserved [0x65] */ -+ -+#define OSCCAL _SFR_MEM8(0x66) -+#define OSCCAL0 0 -+#define OSCCAL1 1 -+#define OSCCAL2 2 -+#define OSCCAL3 3 -+#define OSCCAL4 4 -+#define OSCCAL5 5 -+#define OSCCAL6 6 -+#define OSCCAL7 7 -+ -+/* Reserved [0x67] */ -+ -+#define PCICR _SFR_MEM8(0x68) -+#define PCIE0 0 -+#define PCIE1 1 -+#define PCIE2 2 -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+ -+/* Reserved [0x6A] */ -+ -+#define PCMSK0 _SFR_MEM8(0x6B) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6C) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+#define PCINT14 6 -+ -+#define PCMSK2 _SFR_MEM8(0x6D) -+#define PCINT16 0 -+#define PCINT17 1 -+#define PCINT18 2 -+#define PCINT19 3 -+#define PCINT20 4 -+#define PCINT21 5 -+#define PCINT22 6 -+#define PCINT23 7 -+ -+#define TIMSK0 _SFR_MEM8(0x6E) -+#define TOIE0 0 -+#define OCIE0A 1 -+#define OCIE0B 2 -+ -+#define TIMSK1 _SFR_MEM8(0x6F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define ICIE1 5 -+ -+#define TIMSK2 _SFR_MEM8(0x70) -+#define TOIE2 0 -+#define OCIE2A 1 -+#define OCIE2B 2 -+ -+/* Reserved [0x71..0x77] */ -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_MEM16(0x78) -+#endif -+#define ADCW _SFR_MEM16(0x78) -+ -+#define ADCL _SFR_MEM8(0x78) -+#define ADCH _SFR_MEM8(0x79) -+ -+#define ADCSRA _SFR_MEM8(0x7A) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADCSRB _SFR_MEM8(0x7B) -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+#define ACME 6 -+ -+#define ADMUX _SFR_MEM8(0x7C) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+/* Reserved [0x7D] */ -+ -+#define DIDR0 _SFR_MEM8(0x7E) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+ -+#define DIDR1 _SFR_MEM8(0x7F) -+#define AIN0D 0 -+#define AIN1D 1 -+ -+#define TCCR1A _SFR_MEM8(0x80) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR1B _SFR_MEM8(0x81) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1C _SFR_MEM8(0x82) -+#define FOC1B 6 -+#define FOC1A 7 -+ -+/* Reserved [0x83] */ -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x84) -+ -+#define TCNT1L _SFR_MEM8(0x84) -+#define TCNT1H _SFR_MEM8(0x85) -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x86) -+ -+#define ICR1L _SFR_MEM8(0x86) -+#define ICR1H _SFR_MEM8(0x87) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_MEM16(0x88) -+ -+#define OCR1AL _SFR_MEM8(0x88) -+#define OCR1AH _SFR_MEM8(0x89) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_MEM16(0x8A) -+ -+#define OCR1BL _SFR_MEM8(0x8A) -+#define OCR1BH _SFR_MEM8(0x8B) -+ -+/* Reserved [0x8C..0xAF] */ -+ -+#define TCCR2A _SFR_MEM8(0xB0) -+#define WGM20 0 -+#define WGM21 1 -+#define COM2B0 4 -+#define COM2B1 5 -+#define COM2A0 6 -+#define COM2A1 7 -+ -+#define TCCR2B _SFR_MEM8(0xB1) -+#define CS20 0 -+#define CS21 1 -+#define CS22 2 -+#define WGM22 3 -+#define FOC2B 6 -+#define FOC2A 7 -+ -+#define TCNT2 _SFR_MEM8(0xB2) -+ -+#define OCR2A _SFR_MEM8(0xB3) -+ -+#define OCR2B _SFR_MEM8(0xB4) -+ -+/* Reserved [0xB5] */ -+ -+#define ASSR _SFR_MEM8(0xB6) -+#define TCR2BUB 0 -+#define TCR2AUB 1 -+#define OCR2BUB 2 -+#define OCR2AUB 3 -+#define TCN2UB 4 -+#define AS2 5 -+#define EXCLK 6 -+ -+/* Reserved [0xB7] */ -+ -+#define TWBR _SFR_MEM8(0xB8) -+ -+#define TWSR _SFR_MEM8(0xB9) -+#define TWPS0 0 -+#define TWPS1 1 -+#define TWS3 3 -+#define TWS4 4 -+#define TWS5 5 -+#define TWS6 6 -+#define TWS7 7 -+ -+#define TWAR _SFR_MEM8(0xBA) -+#define TWGCE 0 -+#define TWA0 1 -+#define TWA1 2 -+#define TWA2 3 -+#define TWA3 4 -+#define TWA4 5 -+#define TWA5 6 -+#define TWA6 7 -+ -+#define TWDR _SFR_MEM8(0xBB) -+ -+#define TWCR _SFR_MEM8(0xBC) -+#define TWIE 0 -+#define TWEN 2 -+#define TWWC 3 -+#define TWSTO 4 -+#define TWSTA 5 -+#define TWEA 6 -+#define TWINT 7 -+ -+#define TWAMR _SFR_MEM8(0xBD) -+#define TWAM0 1 -+#define TWAM1 2 -+#define TWAM2 3 -+#define TWAM3 4 -+#define TWAM4 5 -+#define TWAM5 6 -+#define TWAM6 7 -+ -+/* Reserved [0xBE..0xBF] */ -+ -+#define UCSR0A _SFR_MEM8(0xC0) -+#define MPCM0 0 -+#define U2X0 1 -+#define UPE0 2 -+#define DOR0 3 -+#define FE0 4 -+#define UDRE0 5 -+#define TXC0 6 -+#define RXC0 7 -+ -+#define UCSR0B _SFR_MEM8(0xC1) -+#define TXB80 0 -+#define RXB80 1 -+#define UCSZ02 2 -+#define TXEN0 3 -+#define RXEN0 4 -+#define UDRIE0 5 -+#define TXCIE0 6 -+#define RXCIE0 7 -+ -+#define UCSR0C _SFR_MEM8(0xC2) -+#define UCPOL0 0 -+#define UCPHA0 1 -+#define UDORD0 2 -+#define UCSZ00 1 -+#define UCSZ01 2 -+#define USBS0 3 -+#define UPM00 4 -+#define UPM01 5 -+#define UMSEL00 6 -+#define UMSEL01 7 -+ -+/* Reserved [0xC3] */ -+ -+/* Combine UBRR0L and UBRR0H */ -+#define UBRR0 _SFR_MEM16(0xC4) -+ -+#define UBRR0L _SFR_MEM8(0xC4) -+#define UBRR0H _SFR_MEM8(0xC5) -+ -+#define UDR0 _SFR_MEM8(0xC6) -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(3) -+#define PCINT0_vect_num 3 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT1_vect _VECTOR(4) -+#define PCINT1_vect_num 4 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT2_vect _VECTOR(5) -+#define PCINT2_vect_num 5 -+ -+/* Watchdog Time-out Interrupt */ -+#define WDT_vect _VECTOR(6) -+#define WDT_vect_num 6 -+ -+/* Timer/Counter2 Compare Match A */ -+#define TIMER2_COMPA_vect _VECTOR(7) -+#define TIMER2_COMPA_vect_num 7 -+ -+/* Timer/Counter2 Compare Match A */ -+#define TIMER2_COMPB_vect _VECTOR(8) -+#define TIMER2_COMPB_vect_num 8 -+ -+/* Timer/Counter2 Overflow */ -+#define TIMER2_OVF_vect _VECTOR(9) -+#define TIMER2_OVF_vect_num 9 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(10) -+#define TIMER1_CAPT_vect_num 10 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(11) -+#define TIMER1_COMPA_vect_num 11 -+ -+/* Timer/Counter1 Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(12) -+#define TIMER1_COMPB_vect_num 12 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(13) -+#define TIMER1_OVF_vect_num 13 -+ -+/* TimerCounter0 Compare Match A */ -+#define TIMER0_COMPA_vect _VECTOR(14) -+#define TIMER0_COMPA_vect_num 14 -+ -+/* TimerCounter0 Compare Match B */ -+#define TIMER0_COMPB_vect _VECTOR(15) -+#define TIMER0_COMPB_vect_num 15 -+ -+/* Timer/Couner0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(16) -+#define TIMER0_OVF_vect_num 16 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(17) -+#define SPI_STC_vect_num 17 -+ -+/* USART Rx Complete */ -+#define USART_RX_vect _VECTOR(18) -+#define USART_RX_vect_num 18 -+ -+/* USART, Data Register Empty */ -+#define USART_UDRE_vect _VECTOR(19) -+#define USART_UDRE_vect_num 19 -+ -+/* USART Tx Complete */ -+#define USART_TX_vect _VECTOR(20) -+#define USART_TX_vect_num 20 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(21) -+#define ADC_vect_num 21 -+ -+/* EEPROM Ready */ -+#define EE_READY_vect _VECTOR(22) -+#define EE_READY_vect_num 22 -+ -+/* Analog Comparator */ -+#define ANALOG_COMP_vect _VECTOR(23) -+#define ANALOG_COMP_vect_num 23 -+ -+/* Two-wire Serial Interface */ -+#define TWI_vect _VECTOR(24) -+#define TWI_vect_num 24 -+ -+/* Store Program Memory Read */ -+#define SPM_Ready_vect _VECTOR(25) -+#define SPM_Ready_vect_num 25 -+ -+#define _VECTORS_SIZE 104 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 128 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x7FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 2048 -+#define RAMEND 0x08FF -+#define E2START 0 -+#define E2SIZE 1024 -+#define E2PAGESIZE 4 -+#define E2END 0x03FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -+#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_DWEN (unsigned char)~_BV(6) -+#define FUSE_RSTDISBL (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x95 -+#define SIGNATURE_2 0x0F -+ -+ -+#endif /* #ifdef _AVR_ATA6614Q_H_INCLUDED */ -+ -diff --git a/include/avr/ioa6616c.h b/include/avr/ioa6616c.h -new file mode 100644 -index 0000000..175d793 ---- /dev/null -+++ b/include/avr/ioa6616c.h -@@ -0,0 +1,844 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATA6616C_H_INCLUDED -+#define _AVR_ATA6616C_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "ioa6616c.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINA _SFR_IO8(0x00) -+#define PINA7 7 -+#define PINA6 6 -+#define PINA5 5 -+#define PINA4 4 -+#define PINA3 3 -+#define PINA2 2 -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x01) -+#define DDA0 0 -+#define DDA1 1 -+#define DDA2 2 -+#define DDA3 3 -+#define DDA4 4 -+#define DDA5 5 -+#define DDA6 6 -+#define DDA7 7 -+ -+#define PORTA _SFR_IO8(0x02) -+#define PORTA7 7 -+#define PORTA6 6 -+#define PORTA5 5 -+#define PORTA4 4 -+#define PORTA3 3 -+#define PORTA2 2 -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDB0 0 -+#define DDB1 1 -+#define DDB2 2 -+#define DDB3 3 -+#define DDB4 4 -+#define DDB5 5 -+#define DDB6 6 -+#define DDB7 7 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+/* Reserved [0x06..0x11] */ -+ -+#define PORTCR _SFR_IO8(0x12) -+#define PUDA 0 -+#define PUDB 1 -+#define BBMA 4 -+#define BBMB 5 -+ -+/* Reserved [0x13..0x14] */ -+ -+#define TIFR0 _SFR_IO8(0x15) -+#define TOV0 0 -+#define OCF0A 1 -+ -+#define TIFR1 _SFR_IO8(0x16) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define ICF1 5 -+ -+/* Reserved [0x17..0x1A] */ -+ -+#define PCIFR _SFR_IO8(0x1B) -+#define PCIF0 0 -+#define PCIF1 1 -+ -+#define EIFR _SFR_IO8(0x1C) -+#define INTF0 0 -+#define INTF1 1 -+ -+#define EIMSK _SFR_IO8(0x1D) -+#define INT0 0 -+#define INT1 1 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+#define GPIOR00 0 -+#define GPIOR01 1 -+#define GPIOR02 2 -+#define GPIOR03 3 -+#define GPIOR04 4 -+#define GPIOR05 5 -+#define GPIOR06 6 -+#define GPIOR07 7 -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEPE 1 -+#define EEMPE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+ -+#define EEDR _SFR_IO8(0x20) -+#define EEDR0 0 -+#define EEDR1 1 -+#define EEDR2 2 -+#define EEDR3 3 -+#define EEDR4 4 -+#define EEDR5 5 -+#define EEDR6 6 -+#define EEDR7 7 -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSR1 0 -+#define PSR0 1 -+#define TSM 7 -+ -+/* Reserved [0x24] */ -+ -+#define TCCR0A _SFR_IO8(0x25) -+#define WGM00 0 -+#define WGM01 1 -+#define COM0A0 6 -+#define COM0A1 7 -+ -+#define TCCR0B _SFR_IO8(0x26) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define FOC0A 7 -+ -+#define TCNT0 _SFR_IO8(0x27) -+#define TCNT00 0 -+#define TCNT01 1 -+#define TCNT02 2 -+#define TCNT03 3 -+#define TCNT04 4 -+#define TCNT05 5 -+#define TCNT06 6 -+#define TCNT07 7 -+ -+#define OCR0A _SFR_IO8(0x28) -+#define OCR00 0 -+#define OCR01 1 -+#define OCR02 2 -+#define OCR03 3 -+#define OCR04 4 -+#define OCR05 5 -+#define OCR06 6 -+#define OCR07 7 -+ -+/* Reserved [0x29] */ -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+#define GPIOR10 0 -+#define GPIOR11 1 -+#define GPIOR12 2 -+#define GPIOR13 3 -+#define GPIOR14 4 -+#define GPIOR15 5 -+#define GPIOR16 6 -+#define GPIOR17 7 -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+#define GPIOR20 0 -+#define GPIOR21 1 -+#define GPIOR22 2 -+#define GPIOR23 3 -+#define GPIOR24 4 -+#define GPIOR25 5 -+#define GPIOR26 6 -+#define GPIOR27 7 -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+#define SPDR0 0 -+#define SPDR1 1 -+#define SPDR2 2 -+#define SPDR3 3 -+#define SPDR4 4 -+#define SPDR5 5 -+#define SPDR6 6 -+#define SPDR7 7 -+ -+/* Reserved [0x2F] */ -+ -+#define ACSR _SFR_IO8(0x30) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACIRS 6 -+#define ACD 7 -+ -+#define DWDR _SFR_IO8(0x31) -+#define DWDR0 0 -+#define DWDR1 1 -+#define DWDR2 2 -+#define DWDR3 3 -+#define DWDR4 4 -+#define DWDR5 5 -+#define DWDR6 6 -+#define DWDR7 7 -+ -+/* Reserved [0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define PUD 4 -+#define BODSE 5 -+#define BODS 6 -+ -+/* Reserved [0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define RFLB 3 -+#define CTPB 4 -+#define SIGRD 5 -+#define RWWSB 6 -+ -+/* Reserved [0x38..0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCR _SFR_MEM8(0x60) -+#define WDE 3 -+#define WDCE 4 -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDP3 5 -+#define WDIE 6 -+#define WDIF 7 -+ -+#define CLKPR _SFR_MEM8(0x61) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+#define CLKPCE 7 -+ -+#define CLKCSR _SFR_MEM8(0x62) -+#define CLKC0 0 -+#define CLKC1 1 -+#define CLKC2 2 -+#define CLKC3 3 -+#define CLKRDY 4 -+#define CLKCCE 7 -+ -+#define CLKSELR _SFR_MEM8(0x63) -+#define CSEL0 0 -+#define CSEL1 1 -+#define CSEL2 2 -+#define CSEL3 3 -+#define CSUT0 4 -+#define CSUT1 5 -+#define COUT 6 -+ -+#define PRR _SFR_MEM8(0x64) -+#define PRADC 0 -+#define PRUSI 1 -+#define PRTIM0 2 -+#define PRTIM1 3 -+#define PRSPI 4 -+#define PRLIN 5 -+ -+/* Reserved [0x65] */ -+ -+#define OSCCAL _SFR_MEM8(0x66) -+#define CAL0 0 -+#define CAL1 1 -+#define CAL2 2 -+#define CAL3 3 -+#define CAL4 4 -+#define CAL5 5 -+#define CAL6 6 -+#define CAL7 7 -+#define OSCCAL0 0 -+#define OSCCAL1 1 -+#define OSCCAL2 2 -+#define OSCCAL3 3 -+#define OSCCAL4 4 -+#define OSCCAL5 5 -+#define OSCCAL6 6 -+#define OSCCAL7 7 -+ -+/* Reserved [0x67] */ -+ -+#define PCICR _SFR_MEM8(0x68) -+#define PCIE0 0 -+#define PCIE1 1 -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+ -+/* Reserved [0x6A] */ -+ -+#define PCMSK0 _SFR_MEM8(0x6B) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6C) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+#define PCINT14 6 -+#define PCINT15 7 -+ -+/* Reserved [0x6D] */ -+ -+#define TIMSK0 _SFR_MEM8(0x6E) -+#define TOIE0 0 -+#define OCIE0A 1 -+ -+#define TIMSK1 _SFR_MEM8(0x6F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define ICIE1 5 -+ -+/* Reserved [0x70..0x76] */ -+ -+#define AMISCR _SFR_MEM8(0x77) -+#define XREFEN 1 -+#define AREFEN 2 -+#define ISRCEN 0 -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_MEM16(0x78) -+#endif -+#define ADCW _SFR_MEM16(0x78) -+ -+#define ADCL _SFR_MEM8(0x78) -+#define ADCH _SFR_MEM8(0x79) -+ -+#define ADCSRA _SFR_MEM8(0x7A) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADCSRB _SFR_MEM8(0x7B) -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+#define BIN 7 -+#define ACIR0 4 -+#define ACIR1 5 -+#define ACME 6 -+ -+#define ADMUX _SFR_MEM8(0x7C) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define MUX4 4 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+/* Reserved [0x7D] */ -+ -+#define DIDR0 _SFR_MEM8(0x7E) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+#define ADC6D 6 -+#define ADC7D 7 -+ -+#define DIDR1 _SFR_MEM8(0x7F) -+#define ADC8D 0 -+#define ADC9D 1 -+#define ADC10D 2 -+ -+#define TCCR1A _SFR_MEM8(0x80) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR1B _SFR_MEM8(0x81) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1C _SFR_MEM8(0x82) -+#define FOC1B 6 -+#define FOC1A 7 -+ -+#define TCCR1D _SFR_MEM8(0x83) -+#define OC1AU 0 -+#define OC1AV 1 -+#define OC1AW 2 -+#define OC1AX 3 -+#define OC1BU 4 -+#define OC1BV 5 -+#define OC1BW 6 -+#define OC1BX 7 -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x84) -+ -+#define TCNT1L _SFR_MEM8(0x84) -+#define TCNT1H _SFR_MEM8(0x85) -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x86) -+ -+#define ICR1L _SFR_MEM8(0x86) -+#define ICR1H _SFR_MEM8(0x87) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_MEM16(0x88) -+ -+#define OCR1AL _SFR_MEM8(0x88) -+#define OCR1AH _SFR_MEM8(0x89) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_MEM16(0x8A) -+ -+#define OCR1BL _SFR_MEM8(0x8A) -+#define OCR1BH _SFR_MEM8(0x8B) -+ -+/* Reserved [0x8C..0xB5] */ -+ -+#define ASSR _SFR_MEM8(0xB6) -+#define TCR0BUB 0 -+#define TCR0AUB 1 -+#define OCR0AUB 3 -+#define TCN0UB 4 -+#define AS0 5 -+#define EXCLK 6 -+ -+/* Reserved [0xB7] */ -+ -+#define USICR _SFR_MEM8(0xB8) -+#define USITC 0 -+#define USICLK 1 -+#define USICS0 2 -+#define USICS1 3 -+#define USIWM0 4 -+#define USIWM1 5 -+#define USIOIE 6 -+#define USISIE 7 -+ -+#define USISR _SFR_MEM8(0xB9) -+#define USICNT0 0 -+#define USICNT1 1 -+#define USICNT2 2 -+#define USICNT3 3 -+#define USIDC 4 -+#define USIPF 5 -+#define USIOIF 6 -+#define USISIF 7 -+ -+#define USIDR _SFR_MEM8(0xBA) -+#define USIDR0 0 -+#define USIDR1 1 -+#define USIDR2 2 -+#define USIDR3 3 -+#define USIDR4 4 -+#define USIDR5 5 -+#define USIDR6 6 -+#define USIDR7 7 -+ -+#define USIBR _SFR_MEM8(0xBB) -+#define USIBR0 0 -+#define USIBR1 1 -+#define USIBR2 2 -+#define USIBR3 3 -+#define USIBR4 4 -+#define USIBR5 5 -+#define USIBR6 6 -+#define USIBR7 7 -+ -+#define USIPP _SFR_MEM8(0xBC) -+#define USIPOS 0 -+ -+/* Reserved [0xBD..0xC7] */ -+ -+#define LINCR _SFR_MEM8(0xC8) -+#define LCMD0 0 -+#define LCMD1 1 -+#define LCMD2 2 -+#define LENA 3 -+#define LCONF0 4 -+#define LCONF1 5 -+#define LIN13 6 -+#define LSWRES 7 -+ -+#define LINSIR _SFR_MEM8(0xC9) -+#define LRXOK 0 -+#define LTXOK 1 -+#define LIDOK 2 -+#define LERR 3 -+#define LBUSY 4 -+#define LIDST0 5 -+#define LIDST1 6 -+#define LIDST2 7 -+ -+#define LINENIR _SFR_MEM8(0xCA) -+#define LENRXOK 0 -+#define LENTXOK 1 -+#define LENIDOK 2 -+#define LENERR 3 -+ -+#define LINERR _SFR_MEM8(0xCB) -+#define LBERR 0 -+#define LCERR 1 -+#define LPERR 2 -+#define LSERR 3 -+#define LFERR 4 -+#define LOVERR 5 -+#define LTOERR 6 -+#define LABORT 7 -+ -+#define LINBTR _SFR_MEM8(0xCC) -+#define LBT0 0 -+#define LBT1 1 -+#define LBT2 2 -+#define LBT3 3 -+#define LBT4 4 -+#define LBT5 5 -+#define LDISR 7 -+ -+/* Combine LINBRRL and LINBRRH */ -+#define LINBRR _SFR_MEM16(0xCD) -+ -+#define LINBRRL _SFR_MEM8(0xCD) -+#define LINBRRH _SFR_MEM8(0xCE) -+ -+#define LINBRRL _SFR_MEM8(0xCD) -+#define LDIV0 0 -+#define LDIV1 1 -+#define LDIV2 2 -+#define LDIV3 3 -+#define LDIV4 4 -+#define LDIV5 5 -+#define LDIV6 6 -+#define LDIV7 7 -+ -+#define LINBRRH _SFR_MEM8(0xCE) -+#define LDIV8 0 -+#define LDIV9 1 -+#define LDIV10 2 -+#define LDIV11 3 -+ -+#define LINDLR _SFR_MEM8(0xCF) -+#define LRXDL0 0 -+#define LRXDL1 1 -+#define LRXDL2 2 -+#define LRXDL3 3 -+#define LTXDL0 4 -+#define LTXDL1 5 -+#define LTXDL2 6 -+#define LTXDL3 7 -+ -+#define LINIDR _SFR_MEM8(0xD0) -+#define LID0 0 -+#define LID1 1 -+#define LID2 2 -+#define LID3 3 -+#define LID4 4 -+#define LID5 5 -+#define LP0 6 -+#define LP1 7 -+ -+#define LINSEL _SFR_MEM8(0xD1) -+#define LINDX0 0 -+#define LINDX1 1 -+#define LINDX2 2 -+#define LAINC 3 -+ -+#define LINDAT _SFR_MEM8(0xD2) -+#define LDATA0 0 -+#define LDATA1 1 -+#define LDATA2 2 -+#define LDATA3 3 -+#define LDATA4 4 -+#define LDATA5 5 -+#define LDATA6 6 -+#define LDATA7 7 -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(3) -+#define PCINT0_vect_num 3 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(4) -+#define PCINT1_vect_num 4 -+ -+/* Watchdog Time-Out Interrupt */ -+#define WDT_vect _VECTOR(5) -+#define WDT_vect_num 5 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(6) -+#define TIMER1_CAPT_vect_num 6 -+ -+/* Timer/Counter1 Compare Match 1A */ -+#define TIMER1_COMPA_vect _VECTOR(7) -+#define TIMER1_COMPA_vect_num 7 -+ -+/* Timer/Counter1 Compare Match 1B */ -+#define TIMER1_COMPB_vect _VECTOR(8) -+#define TIMER1_COMPB_vect_num 8 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(9) -+#define TIMER1_OVF_vect_num 9 -+ -+/* Timer/Counter0 Compare Match 0A */ -+#define TIMER0_COMPA_vect _VECTOR(10) -+#define TIMER0_COMPA_vect_num 10 -+ -+/* Timer/Counter0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(11) -+#define TIMER0_OVF_vect_num 11 -+ -+/* LIN Transfer Complete */ -+#define LIN_TC_vect _VECTOR(12) -+#define LIN_TC_vect_num 12 -+ -+/* LIN Error */ -+#define LIN_ERR_vect _VECTOR(13) -+#define LIN_ERR_vect_num 13 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(14) -+#define SPI_STC_vect_num 14 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(15) -+#define ADC_vect_num 15 -+ -+/* EEPROM Ready */ -+#define EE_RDY_vect _VECTOR(16) -+#define EE_RDY_vect_num 16 -+ -+/* Analog Comparator */ -+#define ANA_COMP_vect _VECTOR(17) -+#define ANA_COMP_vect_num 17 -+ -+/* USI Start */ -+#define USI_START_vect _VECTOR(18) -+#define USI_START_vect_num 18 -+ -+/* USI Overflow */ -+#define USI_OVF_vect _VECTOR(19) -+#define USI_OVF_vect_num 19 -+ -+#define _VECTORS_SIZE 40 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 128 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x1FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 512 -+#define RAMEND 0x02FF -+#define E2START 0 -+#define E2SIZE 512 -+#define E2PAGESIZE 4 -+#define E2END 0x01FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -+#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_DWEN (unsigned char)~_BV(6) -+#define FUSE_RSTDISBL (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_SELFPRGEN (unsigned char)~_BV(0) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x93 -+#define SIGNATURE_2 0x87 -+ -+ -+#endif /* #ifdef _AVR_ATA6616C_H_INCLUDED */ -+ -diff --git a/include/avr/ioa6617c.h b/include/avr/ioa6617c.h -new file mode 100644 -index 0000000..d821765 ---- /dev/null -+++ b/include/avr/ioa6617c.h -@@ -0,0 +1,756 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATA6617C_H_INCLUDED -+#define _AVR_ATA6617C_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "ioa6617c.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINA _SFR_IO8(0x00) -+#define PINA7 7 -+#define PINA6 6 -+#define PINA5 5 -+#define PINA4 4 -+#define PINA3 3 -+#define PINA2 2 -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x01) -+#define DDA0 0 -+#define DDA1 1 -+#define DDA2 2 -+#define DDA3 3 -+#define DDA4 4 -+#define DDA5 5 -+#define DDA6 6 -+#define DDA7 7 -+ -+#define PORTA _SFR_IO8(0x02) -+#define PORTA7 7 -+#define PORTA6 6 -+#define PORTA5 5 -+#define PORTA4 4 -+#define PORTA3 3 -+#define PORTA2 2 -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDB0 0 -+#define DDB1 1 -+#define DDB2 2 -+#define DDB3 3 -+#define DDB4 4 -+#define DDB5 5 -+#define DDB6 6 -+#define DDB7 7 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+/* Reserved [0x06..0x11] */ -+ -+#define PORTCR _SFR_IO8(0x12) -+#define PUDA 0 -+#define PUDB 1 -+#define BBMA 4 -+#define BBMB 5 -+ -+/* Reserved [0x13..0x14] */ -+ -+#define TIFR0 _SFR_IO8(0x15) -+#define TOV0 0 -+#define OCF0A 1 -+ -+#define TIFR1 _SFR_IO8(0x16) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define ICF1 5 -+ -+/* Reserved [0x17..0x1A] */ -+ -+#define PCIFR _SFR_IO8(0x1B) -+#define PCIF0 0 -+#define PCIF1 1 -+ -+#define EIFR _SFR_IO8(0x1C) -+#define INTF0 0 -+#define INTF1 1 -+ -+#define EIMSK _SFR_IO8(0x1D) -+#define INT0 0 -+#define INT1 1 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEPE 1 -+#define EEMPE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSR1 0 -+#define PSR0 1 -+#define TSM 7 -+ -+/* Reserved [0x24] */ -+ -+#define TCCR0A _SFR_IO8(0x25) -+#define WGM00 0 -+#define WGM01 1 -+#define COM0A0 6 -+#define COM0A1 7 -+ -+#define TCCR0B _SFR_IO8(0x26) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define FOC0A 7 -+ -+#define TCNT0 _SFR_IO8(0x27) -+ -+#define OCR0A _SFR_IO8(0x28) -+ -+/* Reserved [0x29] */ -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+/* Reserved [0x2F] */ -+ -+#define ACSR _SFR_IO8(0x30) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACIRS 6 -+#define ACD 7 -+ -+#define DWDR _SFR_IO8(0x31) -+ -+/* Reserved [0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define PUD 4 -+#define BODSE 5 -+#define BODS 6 -+ -+/* Reserved [0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define RFLB 3 -+#define CTPB 4 -+#define SIGRD 5 -+#define RWWSB 6 -+ -+/* Reserved [0x38..0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCR _SFR_MEM8(0x60) -+#define WDE 3 -+#define WDCE 4 -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDP3 5 -+#define WDIE 6 -+#define WDIF 7 -+ -+#define CLKPR _SFR_MEM8(0x61) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+#define CLKPCE 7 -+ -+#define CLKCSR _SFR_MEM8(0x62) -+#define CLKC0 0 -+#define CLKC1 1 -+#define CLKC2 2 -+#define CLKC3 3 -+#define CLKRDY 4 -+#define CLKCCE 7 -+ -+#define CLKSELR _SFR_MEM8(0x63) -+#define CSEL0 0 -+#define CSEL1 1 -+#define CSEL2 2 -+#define CSEL3 3 -+#define CSUT0 4 -+#define CSUT1 5 -+#define COUT 6 -+ -+#define PRR _SFR_MEM8(0x64) -+#define PRADC 0 -+#define PRUSI 1 -+#define PRTIM0 2 -+#define PRTIM1 3 -+#define PRSPI 4 -+#define PRLIN 5 -+ -+/* Reserved [0x65] */ -+ -+#define OSCCAL _SFR_MEM8(0x66) -+#define OSCCAL0 0 -+#define OSCCAL1 1 -+#define OSCCAL2 2 -+#define OSCCAL3 3 -+#define OSCCAL4 4 -+#define OSCCAL5 5 -+#define OSCCAL6 6 -+#define OSCCAL7 7 -+ -+/* Reserved [0x67] */ -+ -+#define PCICR _SFR_MEM8(0x68) -+#define PCIE0 0 -+#define PCIE1 1 -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+ -+/* Reserved [0x6A] */ -+ -+#define PCMSK0 _SFR_MEM8(0x6B) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6C) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+#define PCINT14 6 -+#define PCINT15 7 -+ -+/* Reserved [0x6D] */ -+ -+#define TIMSK0 _SFR_MEM8(0x6E) -+#define TOIE0 0 -+#define OCIE0A 1 -+ -+#define TIMSK1 _SFR_MEM8(0x6F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define ICIE1 5 -+ -+/* Reserved [0x70..0x76] */ -+ -+#define AMISCR _SFR_MEM8(0x77) -+#define XREFEN 1 -+#define AREFEN 2 -+#define ISRCEN 0 -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_MEM16(0x78) -+#endif -+#define ADCW _SFR_MEM16(0x78) -+ -+#define ADCL _SFR_MEM8(0x78) -+#define ADCH _SFR_MEM8(0x79) -+ -+#define ADCSRA _SFR_MEM8(0x7A) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADCSRB _SFR_MEM8(0x7B) -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+#define BIN 7 -+#define ACIR0 4 -+#define ACIR1 5 -+#define ACME 6 -+ -+#define ADMUX _SFR_MEM8(0x7C) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define MUX4 4 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+/* Reserved [0x7D] */ -+ -+#define DIDR0 _SFR_MEM8(0x7E) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+#define ADC6D 6 -+#define ADC7D 7 -+ -+#define DIDR1 _SFR_MEM8(0x7F) -+#define ADC8D 0 -+#define ADC9D 1 -+#define ADC10D 2 -+ -+#define TCCR1A _SFR_MEM8(0x80) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR1B _SFR_MEM8(0x81) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1C _SFR_MEM8(0x82) -+#define FOC1B 6 -+#define FOC1A 7 -+ -+#define TCCR1D _SFR_MEM8(0x83) -+#define OC1AU 0 -+#define OC1AV 1 -+#define OC1AW 2 -+#define OC1AX 3 -+#define OC1BU 4 -+#define OC1BV 5 -+#define OC1BW 6 -+#define OC1BX 7 -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x84) -+ -+#define TCNT1L _SFR_MEM8(0x84) -+#define TCNT1H _SFR_MEM8(0x85) -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x86) -+ -+#define ICR1L _SFR_MEM8(0x86) -+#define ICR1H _SFR_MEM8(0x87) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_MEM16(0x88) -+ -+#define OCR1AL _SFR_MEM8(0x88) -+#define OCR1AH _SFR_MEM8(0x89) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_MEM16(0x8A) -+ -+#define OCR1BL _SFR_MEM8(0x8A) -+#define OCR1BH _SFR_MEM8(0x8B) -+ -+/* Reserved [0x8C..0xB5] */ -+ -+#define ASSR _SFR_MEM8(0xB6) -+#define TCR0BUB 0 -+#define TCR0AUB 1 -+#define OCR0AUB 3 -+#define TCN0UB 4 -+#define AS0 5 -+#define EXCLK 6 -+ -+/* Reserved [0xB7] */ -+ -+#define USICR _SFR_MEM8(0xB8) -+#define USITC 0 -+#define USICLK 1 -+#define USICS0 2 -+#define USICS1 3 -+#define USIWM0 4 -+#define USIWM1 5 -+#define USIOIE 6 -+#define USISIE 7 -+ -+#define USISR _SFR_MEM8(0xB9) -+#define USICNT0 0 -+#define USICNT1 1 -+#define USICNT2 2 -+#define USICNT3 3 -+#define USIDC 4 -+#define USIPF 5 -+#define USIOIF 6 -+#define USISIF 7 -+ -+#define USIDR _SFR_MEM8(0xBA) -+ -+#define USIBR _SFR_MEM8(0xBB) -+ -+#define USIPP _SFR_MEM8(0xBC) -+#define USIPOS 0 -+ -+/* Reserved [0xBD..0xC7] */ -+ -+#define LINCR _SFR_MEM8(0xC8) -+#define LCMD0 0 -+#define LCMD1 1 -+#define LCMD2 2 -+#define LENA 3 -+#define LCONF0 4 -+#define LCONF1 5 -+#define LIN13 6 -+#define LSWRES 7 -+ -+#define LINSIR _SFR_MEM8(0xC9) -+#define LRXOK 0 -+#define LTXOK 1 -+#define LIDOK 2 -+#define LERR 3 -+#define LBUSY 4 -+#define LIDST0 5 -+#define LIDST1 6 -+#define LIDST2 7 -+ -+#define LINENIR _SFR_MEM8(0xCA) -+#define LENRXOK 0 -+#define LENTXOK 1 -+#define LENIDOK 2 -+#define LENERR 3 -+ -+#define LINERR _SFR_MEM8(0xCB) -+#define LBERR 0 -+#define LCERR 1 -+#define LPERR 2 -+#define LSERR 3 -+#define LFERR 4 -+#define LOVERR 5 -+#define LTOERR 6 -+#define LABORT 7 -+ -+#define LINBTR _SFR_MEM8(0xCC) -+#define LBT0 0 -+#define LBT1 1 -+#define LBT2 2 -+#define LBT3 3 -+#define LBT4 4 -+#define LBT5 5 -+#define LDISR 7 -+ -+/* Combine LINBRRL and LINBRRH */ -+#define LINBRR _SFR_MEM16(0xCD) -+ -+#define LINBRRL _SFR_MEM8(0xCD) -+#define LINBRRH _SFR_MEM8(0xCE) -+ -+#define LINBRRL _SFR_MEM8(0xCD) -+#define LDIV0 0 -+#define LDIV1 1 -+#define LDIV2 2 -+#define LDIV3 3 -+#define LDIV4 4 -+#define LDIV5 5 -+#define LDIV6 6 -+#define LDIV7 7 -+ -+#define LINBRRH _SFR_MEM8(0xCE) -+#define LDIV8 0 -+#define LDIV9 1 -+#define LDIV10 2 -+#define LDIV11 3 -+ -+#define LINDLR _SFR_MEM8(0xCF) -+#define LRXDL0 0 -+#define LRXDL1 1 -+#define LRXDL2 2 -+#define LRXDL3 3 -+#define LTXDL0 4 -+#define LTXDL1 5 -+#define LTXDL2 6 -+#define LTXDL3 7 -+ -+#define LINIDR _SFR_MEM8(0xD0) -+#define LID0 0 -+#define LID1 1 -+#define LID2 2 -+#define LID3 3 -+#define LID4 4 -+#define LID5 5 -+#define LP0 6 -+#define LP1 7 -+ -+#define LINSEL _SFR_MEM8(0xD1) -+#define LINDX0 0 -+#define LINDX1 1 -+#define LINDX2 2 -+#define LAINC 3 -+ -+#define LINDAT _SFR_MEM8(0xD2) -+#define LDATA0 0 -+#define LDATA1 1 -+#define LDATA2 2 -+#define LDATA3 3 -+#define LDATA4 4 -+#define LDATA5 5 -+#define LDATA6 6 -+#define LDATA7 7 -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(3) -+#define PCINT0_vect_num 3 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(4) -+#define PCINT1_vect_num 4 -+ -+/* Watchdog Time-Out Interrupt */ -+#define WDT_vect _VECTOR(5) -+#define WDT_vect_num 5 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(6) -+#define TIMER1_CAPT_vect_num 6 -+ -+/* Timer/Counter1 Compare Match 1A */ -+#define TIMER1_COMPA_vect _VECTOR(7) -+#define TIMER1_COMPA_vect_num 7 -+ -+/* Timer/Counter1 Compare Match 1B */ -+#define TIMER1_COMPB_vect _VECTOR(8) -+#define TIMER1_COMPB_vect_num 8 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(9) -+#define TIMER1_OVF_vect_num 9 -+ -+/* Timer/Counter0 Compare Match 0A */ -+#define TIMER0_COMPA_vect _VECTOR(10) -+#define TIMER0_COMPA_vect_num 10 -+ -+/* Timer/Counter0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(11) -+#define TIMER0_OVF_vect_num 11 -+ -+/* LIN Transfer Complete */ -+#define LIN_TC_vect _VECTOR(12) -+#define LIN_TC_vect_num 12 -+ -+/* LIN Error */ -+#define LIN_ERR_vect _VECTOR(13) -+#define LIN_ERR_vect_num 13 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(14) -+#define SPI_STC_vect_num 14 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(15) -+#define ADC_vect_num 15 -+ -+/* EEPROM Ready */ -+#define EE_RDY_vect _VECTOR(16) -+#define EE_RDY_vect_num 16 -+ -+/* Analog Comparator */ -+#define ANA_COMP_vect _VECTOR(17) -+#define ANA_COMP_vect_num 17 -+ -+/* USI Start */ -+#define USI_START_vect _VECTOR(18) -+#define USI_START_vect_num 18 -+ -+/* USI Overflow */ -+#define USI_OVF_vect _VECTOR(19) -+#define USI_OVF_vect_num 19 -+ -+#define _VECTORS_SIZE 80 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 128 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x3FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 512 -+#define RAMEND 0x02FF -+#define E2START 0 -+#define E2SIZE 512 -+#define E2PAGESIZE 4 -+#define E2END 0x01FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -+#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_DWEN (unsigned char)~_BV(6) -+#define FUSE_RSTDISBL (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_SELFPRGEN (unsigned char)~_BV(0) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x94 -+#define SIGNATURE_2 0x87 -+ -+ -+#endif /* #ifdef _AVR_ATA6617C_H_INCLUDED */ -+ -diff --git a/include/avr/ioa664251.h b/include/avr/ioa664251.h -new file mode 100644 -index 0000000..2ac2d72 ---- /dev/null -+++ b/include/avr/ioa664251.h -@@ -0,0 +1,754 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATA664251_H_INCLUDED -+#define _AVR_ATA664251_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "ioa664251.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINA _SFR_IO8(0x00) -+#define PINA7 7 -+#define PINA6 6 -+#define PINA5 5 -+#define PINA4 4 -+#define PINA3 3 -+#define PINA2 2 -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x01) -+#define DDA0 0 -+#define DDA1 1 -+#define DDA2 2 -+#define DDA3 3 -+#define DDA4 4 -+#define DDA5 5 -+#define DDA6 6 -+#define DDA7 7 -+ -+#define PORTA _SFR_IO8(0x02) -+#define PORTA7 7 -+#define PORTA6 6 -+#define PORTA5 5 -+#define PORTA4 4 -+#define PORTA3 3 -+#define PORTA2 2 -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDB0 0 -+#define DDB1 1 -+#define DDB2 2 -+#define DDB3 3 -+#define DDB4 4 -+#define DDB5 5 -+#define DDB6 6 -+#define DDB7 7 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+/* Reserved [0x06..0x11] */ -+ -+#define PORTCR _SFR_IO8(0x12) -+#define PUDA 0 -+#define PUDB 1 -+#define BBMA 4 -+#define BBMB 5 -+ -+/* Reserved [0x13..0x14] */ -+ -+#define TIFR0 _SFR_IO8(0x15) -+#define TOV0 0 -+#define OCF0A 1 -+ -+#define TIFR1 _SFR_IO8(0x16) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define ICF1 5 -+ -+/* Reserved [0x17..0x1A] */ -+ -+#define PCIFR _SFR_IO8(0x1B) -+#define PCIF0 0 -+#define PCIF1 1 -+ -+#define EIFR _SFR_IO8(0x1C) -+#define INTF0 0 -+#define INTF1 1 -+ -+#define EIMSK _SFR_IO8(0x1D) -+#define INT0 0 -+#define INT1 1 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEPE 1 -+#define EEMPE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSR1 0 -+#define PSR0 1 -+#define TSM 7 -+ -+/* Reserved [0x24] */ -+ -+#define TCCR0A _SFR_IO8(0x25) -+#define WGM00 0 -+#define WGM01 1 -+#define COM0A0 6 -+#define COM0A1 7 -+ -+#define TCCR0B _SFR_IO8(0x26) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define FOC0A 7 -+ -+#define TCNT0 _SFR_IO8(0x27) -+ -+#define OCR0A _SFR_IO8(0x28) -+ -+/* Reserved [0x29] */ -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+/* Reserved [0x2F] */ -+ -+#define ACSR _SFR_IO8(0x30) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACIRS 6 -+#define ACD 7 -+ -+#define OSCCAL _SFR_IO8(0x31) -+#define OSCCAL0 0 -+#define OSCCAL1 1 -+#define OSCCAL2 2 -+#define OSCCAL3 3 -+#define OSCCAL4 4 -+#define OSCCAL5 5 -+#define OSCCAL6 6 -+#define OSCCAL7 7 -+ -+#define DWDR _SFR_IO8(0x31) -+ -+/* Reserved [0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define PUD 4 -+#define BODSE 5 -+#define BODS 6 -+ -+/* Reserved [0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define RFLB 3 -+#define CTPB 4 -+#define SIGRD 5 -+#define RWWSB 6 -+ -+/* Reserved [0x38..0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCR _SFR_MEM8(0x60) -+#define WDE 3 -+#define WDCE 4 -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDP3 5 -+#define WDIE 6 -+#define WDIF 7 -+ -+#define CLKPR _SFR_MEM8(0x61) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+#define CLKPCE 7 -+ -+#define CLKCSR _SFR_MEM8(0x62) -+#define CLKC0 0 -+#define CLKC1 1 -+#define CLKC2 2 -+#define CLKC3 3 -+#define CLKRDY 4 -+#define CLKCCE 7 -+ -+#define CLKSELR _SFR_MEM8(0x63) -+#define CSEL0 0 -+#define CSEL1 1 -+#define CSEL2 2 -+#define CSEL3 3 -+#define CSUT0 4 -+#define CSUT1 5 -+#define COUT 6 -+ -+#define PRR _SFR_MEM8(0x64) -+#define PRADC 0 -+#define PRUSI 1 -+#define PRTIM0 2 -+#define PRTIM1 3 -+#define PRSPI 4 -+#define PRLIN 5 -+ -+/* Reserved [0x65..0x67] */ -+ -+#define PCICR _SFR_MEM8(0x68) -+#define PCIE0 0 -+#define PCIE1 1 -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+ -+/* Reserved [0x6A] */ -+ -+#define PCMSK0 _SFR_MEM8(0x6B) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6C) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+#define PCINT14 6 -+#define PCINT15 7 -+ -+/* Reserved [0x6D] */ -+ -+#define TIMSK0 _SFR_MEM8(0x6E) -+#define TOIE0 0 -+#define OCIE0A 1 -+ -+#define TIMSK1 _SFR_MEM8(0x6F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define ICIE1 5 -+ -+/* Reserved [0x70..0x76] */ -+ -+#define AMISCR _SFR_MEM8(0x77) -+#define XREFEN 1 -+#define AREFEN 2 -+#define ISRCEN 0 -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_MEM16(0x78) -+#endif -+#define ADCW _SFR_MEM16(0x78) -+ -+#define ADCL _SFR_MEM8(0x78) -+#define ADCH _SFR_MEM8(0x79) -+ -+#define ADCSRA _SFR_MEM8(0x7A) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADCSRB _SFR_MEM8(0x7B) -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+#define BIN 7 -+#define ACIR0 4 -+#define ACIR1 5 -+#define ACME 6 -+ -+#define ADMUX _SFR_MEM8(0x7C) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define MUX4 4 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+/* Reserved [0x7D] */ -+ -+#define DIDR0 _SFR_MEM8(0x7E) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+#define ADC6D 6 -+#define ADC7D 7 -+ -+#define DIDR1 _SFR_MEM8(0x7F) -+#define ADC8D 0 -+#define ADC9D 1 -+#define ADC10D 2 -+ -+#define TCCR1A _SFR_MEM8(0x80) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR1B _SFR_MEM8(0x81) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1C _SFR_MEM8(0x82) -+#define FOC1B 6 -+#define FOC1A 7 -+ -+#define TCCR1D _SFR_MEM8(0x83) -+#define OC1AU 0 -+#define OC1AV 1 -+#define OC1AW 2 -+#define OC1AX 3 -+#define OC1BU 4 -+#define OC1BV 5 -+#define OC1BW 6 -+#define OC1BX 7 -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x84) -+ -+#define TCNT1L _SFR_MEM8(0x84) -+#define TCNT1H _SFR_MEM8(0x85) -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x86) -+ -+#define ICR1L _SFR_MEM8(0x86) -+#define ICR1H _SFR_MEM8(0x87) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_MEM16(0x88) -+ -+#define OCR1AL _SFR_MEM8(0x88) -+#define OCR1AH _SFR_MEM8(0x89) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_MEM16(0x8A) -+ -+#define OCR1BL _SFR_MEM8(0x8A) -+#define OCR1BH _SFR_MEM8(0x8B) -+ -+/* Reserved [0x8C..0xB5] */ -+ -+#define ASSR _SFR_MEM8(0xB6) -+#define TCR0BUB 0 -+#define TCR0AUB 1 -+#define OCR0AUB 3 -+#define TCN0UB 4 -+#define AS0 5 -+#define EXCLK 6 -+ -+/* Reserved [0xB7] */ -+ -+#define USICR _SFR_MEM8(0xB8) -+#define USITC 0 -+#define USICLK 1 -+#define USICS0 2 -+#define USICS1 3 -+#define USIWM0 4 -+#define USIWM1 5 -+#define USIOIE 6 -+#define USISIE 7 -+ -+#define USISR _SFR_MEM8(0xB9) -+#define USICNT0 0 -+#define USICNT1 1 -+#define USICNT2 2 -+#define USICNT3 3 -+#define USIDC 4 -+#define USIPF 5 -+#define USIOIF 6 -+#define USISIF 7 -+ -+#define USIDR _SFR_MEM8(0xBA) -+ -+#define USIBR _SFR_MEM8(0xBB) -+ -+#define USIPP _SFR_MEM8(0xBC) -+#define USIPOS 0 -+ -+/* Reserved [0xBD..0xC7] */ -+ -+#define LINCR _SFR_MEM8(0xC8) -+#define LCMD0 0 -+#define LCMD1 1 -+#define LCMD2 2 -+#define LENA 3 -+#define LCONF0 4 -+#define LCONF1 5 -+#define LIN13 6 -+#define LSWRES 7 -+ -+#define LINSIR _SFR_MEM8(0xC9) -+#define LRXOK 0 -+#define LTXOK 1 -+#define LIDOK 2 -+#define LERR 3 -+#define LBUSY 4 -+#define LIDST0 5 -+#define LIDST1 6 -+#define LIDST2 7 -+ -+#define LINENIR _SFR_MEM8(0xCA) -+#define LENRXOK 0 -+#define LENTXOK 1 -+#define LENIDOK 2 -+#define LENERR 3 -+ -+#define LINERR _SFR_MEM8(0xCB) -+#define LBERR 0 -+#define LCERR 1 -+#define LPERR 2 -+#define LSERR 3 -+#define LFERR 4 -+#define LOVERR 5 -+#define LTOERR 6 -+#define LABORT 7 -+ -+#define LINBTR _SFR_MEM8(0xCC) -+#define LBT0 0 -+#define LBT1 1 -+#define LBT2 2 -+#define LBT3 3 -+#define LBT4 4 -+#define LBT5 5 -+#define LDISR 7 -+ -+/* Combine LINBRRL and LINBRRH */ -+#define LINBRR _SFR_MEM16(0xCD) -+ -+#define LINBRRL _SFR_MEM8(0xCD) -+#define LINBRRH _SFR_MEM8(0xCE) -+ -+#define LINBRRL _SFR_MEM8(0xCD) -+#define LDIV0 0 -+#define LDIV1 1 -+#define LDIV2 2 -+#define LDIV3 3 -+#define LDIV4 4 -+#define LDIV5 5 -+#define LDIV6 6 -+#define LDIV7 7 -+ -+#define LINBRRH _SFR_MEM8(0xCE) -+#define LDIV8 0 -+#define LDIV9 1 -+#define LDIV10 2 -+#define LDIV11 3 -+ -+#define LINDLR _SFR_MEM8(0xCF) -+#define LRXDL0 0 -+#define LRXDL1 1 -+#define LRXDL2 2 -+#define LRXDL3 3 -+#define LTXDL0 4 -+#define LTXDL1 5 -+#define LTXDL2 6 -+#define LTXDL3 7 -+ -+#define LINIDR _SFR_MEM8(0xD0) -+#define LID0 0 -+#define LID1 1 -+#define LID2 2 -+#define LID3 3 -+#define LID4 4 -+#define LID5 5 -+#define LP0 6 -+#define LP1 7 -+ -+#define LINSEL _SFR_MEM8(0xD1) -+#define LINDX0 0 -+#define LINDX1 1 -+#define LINDX2 2 -+#define LAINC 3 -+ -+#define LINDAT _SFR_MEM8(0xD2) -+#define LDATA0 0 -+#define LDATA1 1 -+#define LDATA2 2 -+#define LDATA3 3 -+#define LDATA4 4 -+#define LDATA5 5 -+#define LDATA6 6 -+#define LDATA7 7 -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(3) -+#define PCINT0_vect_num 3 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(4) -+#define PCINT1_vect_num 4 -+ -+/* Watchdog Time-Out Interrupt */ -+#define WDT_vect _VECTOR(5) -+#define WDT_vect_num 5 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(6) -+#define TIMER1_CAPT_vect_num 6 -+ -+/* Timer/Counter1 Compare Match 1A */ -+#define TIMER1_COMPA_vect _VECTOR(7) -+#define TIMER1_COMPA_vect_num 7 -+ -+/* Timer/Counter1 Compare Match 1B */ -+#define TIMER1_COMPB_vect _VECTOR(8) -+#define TIMER1_COMPB_vect_num 8 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(9) -+#define TIMER1_OVF_vect_num 9 -+ -+/* Timer/Counter0 Compare Match 0A */ -+#define TIMER0_COMPA_vect _VECTOR(10) -+#define TIMER0_COMPA_vect_num 10 -+ -+/* Timer/Counter0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(11) -+#define TIMER0_OVF_vect_num 11 -+ -+/* LIN Transfer Complete */ -+#define LIN_TC_vect _VECTOR(12) -+#define LIN_TC_vect_num 12 -+ -+/* LIN Error */ -+#define LIN_ERR_vect _VECTOR(13) -+#define LIN_ERR_vect_num 13 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(14) -+#define SPI_STC_vect_num 14 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(15) -+#define ADC_vect_num 15 -+ -+/* EEPROM Ready */ -+#define EE_RDY_vect _VECTOR(16) -+#define EE_RDY_vect_num 16 -+ -+/* Analog Comparator */ -+#define ANA_COMP_vect _VECTOR(17) -+#define ANA_COMP_vect_num 17 -+ -+/* USI Start */ -+#define USI_START_vect _VECTOR(18) -+#define USI_START_vect_num 18 -+ -+/* USI Overflow */ -+#define USI_OVF_vect _VECTOR(19) -+#define USI_OVF_vect_num 19 -+ -+#define _VECTORS_SIZE 80 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 128 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x3FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 512 -+#define RAMEND 0x02FF -+#define E2START 0 -+#define E2SIZE 512 -+#define E2PAGESIZE 4 -+#define E2END 0x01FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -+#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_DWEN (unsigned char)~_BV(6) -+#define FUSE_RSTDISBL (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_SELFPRGEN (unsigned char)~_BV(0) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x94 -+#define SIGNATURE_2 0x87 -+ -+ -+#endif /* #ifdef _AVR_ATA664251_H_INCLUDED */ -+ -diff --git a/include/avr/iom103.h b/include/avr/iom103.h -index b79a9b0..6c3ff68 100644 ---- a/include/avr/iom103.h -+++ b/include/avr/iom103.h -@@ -202,7 +202,7 @@ - /* Timer/Counter Interrupt MaSK register */ - #define TIMSK _SFR_IO8(0x37) - --/* Èxternal Interrupt Flag Register */ -+/* �xternal Interrupt Flag Register */ - #define EIFR _SFR_IO8(0x38) - - /* External Interrupt MaSK register */ -@@ -377,7 +377,7 @@ - #define INT1 1 - #define INT0 0 - --/* Èxternal Interrupt Flag Register */ -+/* �xternal Interrupt Flag Register */ - #define INTF7 7 - #define INTF6 6 - #define INTF5 5 -diff --git a/include/avr/iom1284.h b/include/avr/iom1284.h -new file mode 100644 -index 0000000..07d5961 ---- /dev/null -+++ b/include/avr/iom1284.h -@@ -0,0 +1,1006 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATMEGA1284_H_INCLUDED -+#define _AVR_ATMEGA1284_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iom1284.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINA _SFR_IO8(0x00) -+#define PINA7 7 -+#define PINA6 6 -+#define PINA5 5 -+#define PINA4 4 -+#define PINA3 3 -+#define PINA2 2 -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x01) -+#define DDRA7 7 -+#define DDRA6 6 -+#define DDRA5 5 -+#define DDRA4 4 -+#define DDRA3 3 -+#define DDRA2 2 -+#define DDRA1 1 -+#define DDRA0 0 -+ -+#define PORTA _SFR_IO8(0x02) -+#define PORTA7 7 -+#define PORTA6 6 -+#define PORTA5 5 -+#define PORTA4 4 -+#define PORTA3 3 -+#define PORTA2 2 -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x06) -+#define PINC7 7 -+#define PINC6 6 -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x07) -+#define DDRC7 7 -+#define DDRC6 6 -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x08) -+#define PORTC7 7 -+#define PORTC6 6 -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PIND _SFR_IO8(0x09) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0A) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x0B) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+/* Reserved [0x0C..0x14] */ -+ -+#define TIFR0 _SFR_IO8(0x15) -+#define TOV0 0 -+#define OCF0A 1 -+#define OCF0B 2 -+ -+#define TIFR1 _SFR_IO8(0x16) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define ICF1 5 -+ -+#define TIFR2 _SFR_IO8(0x17) -+#define TOV2 0 -+#define OCF2A 1 -+#define OCF2B 2 -+ -+#define TIFR3 _SFR_IO8(0x18) -+#define TOV3 0 -+#define OCF3A 1 -+#define OCF3B 2 -+#define ICF3 5 -+ -+/* Reserved [0x19..0x1A] */ -+ -+#define PCIFR _SFR_IO8(0x1B) -+#define PCIF0 0 -+#define PCIF1 1 -+#define PCIF2 2 -+#define PCIF3 3 -+ -+#define EIFR _SFR_IO8(0x1C) -+#define INTF0 0 -+#define INTF1 1 -+#define INTF2 2 -+ -+#define EIMSK _SFR_IO8(0x1D) -+#define INT0 0 -+#define INT1 1 -+#define INT2 2 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+#define GPIOR00 0 -+#define GPIOR01 1 -+#define GPIOR02 2 -+#define GPIOR03 3 -+#define GPIOR04 4 -+#define GPIOR05 5 -+#define GPIOR06 6 -+#define GPIOR07 7 -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEPE 1 -+#define EEMPE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSRSYNC 0 -+#define TSM 7 -+#define PSRASY 1 -+ -+#define TCCR0A _SFR_IO8(0x24) -+#define WGM00 0 -+#define WGM01 1 -+#define COM0B0 4 -+#define COM0B1 5 -+#define COM0A0 6 -+#define COM0A1 7 -+ -+#define TCCR0B _SFR_IO8(0x25) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define WGM02 3 -+#define FOC0B 6 -+#define FOC0A 7 -+ -+#define TCNT0 _SFR_IO8(0x26) -+ -+#define OCR0A _SFR_IO8(0x27) -+ -+#define OCR0B _SFR_IO8(0x28) -+ -+/* Reserved [0x29] */ -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+#define GPIOR10 0 -+#define GPIOR11 1 -+#define GPIOR12 2 -+#define GPIOR13 3 -+#define GPIOR14 4 -+#define GPIOR15 5 -+#define GPIOR16 6 -+#define GPIOR17 7 -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+#define GPIOR20 0 -+#define GPIOR21 1 -+#define GPIOR22 2 -+#define GPIOR23 3 -+#define GPIOR24 4 -+#define GPIOR25 5 -+#define GPIOR26 6 -+#define GPIOR27 7 -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+/* Reserved [0x2F] */ -+ -+#define ACSR _SFR_IO8(0x30) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACBG 6 -+#define ACD 7 -+ -+#define OCDR _SFR_IO8(0x31) -+#define OCDR7 7 -+#define OCDR6 6 -+#define OCDR5 5 -+#define OCDR4 4 -+#define OCDR3 3 -+#define OCDR2 2 -+#define OCDR1 1 -+#define OCDR0 0 -+ -+/* Reserved [0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define JTRF 4 -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define JTD 7 -+#define IVCE 0 -+#define IVSEL 1 -+#define PUD 4 -+ -+/* Reserved [0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define SIGRD 5 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+/* Reserved [0x38..0x3A] */ -+ -+#define RAMPZ _SFR_IO8(0x3B) -+ -+/* Reserved [0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCSR _SFR_MEM8(0x60) -+#define WDE 3 -+#define WDCE 4 -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDP3 5 -+#define WDIE 6 -+#define WDIF 7 -+ -+#define CLKPR _SFR_MEM8(0x61) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+#define CLKPCE 7 -+ -+/* Reserved [0x62..0x63] */ -+ -+#define PRR0 _SFR_MEM8(0x64) -+#define PRADC 0 -+#define PRSPI 2 -+#define PRTIM1 3 -+#define PRUSART0 1 -+#define PRUSART1 4 -+#define PRTIM0 5 -+#define PRTIM2 6 -+#define PRTWI 7 -+ -+#define PRR1 _SFR_MEM8(0x65) -+#define PRTIM3 0 -+ -+#define OSCCAL _SFR_MEM8(0x66) -+#define OSCCAL0 0 -+#define OSCCAL1 1 -+#define OSCCAL2 2 -+#define OSCCAL3 3 -+#define OSCCAL4 4 -+#define OSCCAL5 5 -+#define OSCCAL6 6 -+#define OSCCAL7 7 -+ -+/* Reserved [0x67] */ -+ -+#define PCICR _SFR_MEM8(0x68) -+#define PCIE0 0 -+#define PCIE1 1 -+#define PCIE2 2 -+#define PCIE3 3 -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+#define ISC20 4 -+#define ISC21 5 -+ -+/* Reserved [0x6A] */ -+ -+#define PCMSK0 _SFR_MEM8(0x6B) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6C) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+#define PCINT14 6 -+#define PCINT15 7 -+ -+#define PCMSK2 _SFR_MEM8(0x6D) -+#define PCINT16 0 -+#define PCINT17 1 -+#define PCINT18 2 -+#define PCINT19 3 -+#define PCINT20 4 -+#define PCINT21 5 -+#define PCINT22 6 -+#define PCINT23 7 -+ -+#define TIMSK0 _SFR_MEM8(0x6E) -+#define TOIE0 0 -+#define OCIE0A 1 -+#define OCIE0B 2 -+ -+#define TIMSK1 _SFR_MEM8(0x6F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define ICIE1 5 -+ -+#define TIMSK2 _SFR_MEM8(0x70) -+#define TOIE2 0 -+#define OCIE2A 1 -+#define OCIE2B 2 -+ -+#define TIMSK3 _SFR_MEM8(0x71) -+#define TOIE3 0 -+#define OCIE3A 1 -+#define OCIE3B 2 -+#define ICIE3 5 -+ -+/* Reserved [0x72] */ -+ -+#define PCMSK3 _SFR_MEM8(0x73) -+#define PCINT24 0 -+#define PCINT25 1 -+#define PCINT26 2 -+#define PCINT27 3 -+#define PCINT28 4 -+#define PCINT29 5 -+#define PCINT30 6 -+#define PCINT31 7 -+ -+/* Reserved [0x74..0x77] */ -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_MEM16(0x78) -+#endif -+#define ADCW _SFR_MEM16(0x78) -+ -+#define ADCL _SFR_MEM8(0x78) -+#define ADCH _SFR_MEM8(0x79) -+ -+#define ADCSRA _SFR_MEM8(0x7A) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADCSRB _SFR_MEM8(0x7B) -+#define ACME 6 -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+ -+#define ADMUX _SFR_MEM8(0x7C) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define MUX4 4 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+/* Reserved [0x7D] */ -+ -+#define DIDR0 _SFR_MEM8(0x7E) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+#define ADC6D 6 -+#define ADC7D 7 -+ -+#define DIDR1 _SFR_MEM8(0x7F) -+#define AIN0D 0 -+#define AIN1D 1 -+ -+#define TCCR1A _SFR_MEM8(0x80) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR1B _SFR_MEM8(0x81) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1C _SFR_MEM8(0x82) -+#define FOC1B 6 -+#define FOC1A 7 -+ -+/* Reserved [0x83] */ -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x84) -+ -+#define TCNT1L _SFR_MEM8(0x84) -+#define TCNT1H _SFR_MEM8(0x85) -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x86) -+ -+#define ICR1L _SFR_MEM8(0x86) -+#define ICR1H _SFR_MEM8(0x87) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_MEM16(0x88) -+ -+#define OCR1AL _SFR_MEM8(0x88) -+#define OCR1AH _SFR_MEM8(0x89) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_MEM16(0x8A) -+ -+#define OCR1BL _SFR_MEM8(0x8A) -+#define OCR1BH _SFR_MEM8(0x8B) -+ -+/* Reserved [0x8C..0x8F] */ -+ -+#define TCCR3A _SFR_MEM8(0x90) -+#define WGM30 0 -+#define WGM31 1 -+#define COM3B0 4 -+#define COM3B1 5 -+#define COM3A0 6 -+#define COM3A1 7 -+ -+#define TCCR3B _SFR_MEM8(0x91) -+#define CS30 0 -+#define CS31 1 -+#define CS32 2 -+#define WGM32 3 -+#define WGM33 4 -+#define ICES3 6 -+#define ICNC3 7 -+ -+#define TCCR3C _SFR_MEM8(0x92) -+#define FOC3B 6 -+#define FOC3A 7 -+ -+/* Reserved [0x93] */ -+ -+/* Combine TCNT3L and TCNT3H */ -+#define TCNT3 _SFR_MEM16(0x94) -+ -+#define TCNT3L _SFR_MEM8(0x94) -+#define TCNT3H _SFR_MEM8(0x95) -+ -+/* Combine ICR3L and ICR3H */ -+#define ICR3 _SFR_MEM16(0x96) -+ -+#define ICR3L _SFR_MEM8(0x96) -+#define ICR3H _SFR_MEM8(0x97) -+ -+/* Combine OCR3AL and OCR3AH */ -+#define OCR3A _SFR_MEM16(0x98) -+ -+#define OCR3AL _SFR_MEM8(0x98) -+#define OCR3AH _SFR_MEM8(0x99) -+ -+/* Combine OCR3BL and OCR3BH */ -+#define OCR3B _SFR_MEM16(0x9A) -+ -+#define OCR3BL _SFR_MEM8(0x9A) -+#define OCR3BH _SFR_MEM8(0x9B) -+ -+/* Reserved [0x9C..0xAF] */ -+ -+#define TCCR2A _SFR_MEM8(0xB0) -+#define WGM20 0 -+#define WGM21 1 -+#define COM2B0 4 -+#define COM2B1 5 -+#define COM2A0 6 -+#define COM2A1 7 -+ -+#define TCCR2B _SFR_MEM8(0xB1) -+#define CS20 0 -+#define CS21 1 -+#define CS22 2 -+#define WGM22 3 -+#define FOC2B 6 -+#define FOC2A 7 -+ -+#define TCNT2 _SFR_MEM8(0xB2) -+ -+#define OCR2A _SFR_MEM8(0xB3) -+ -+#define OCR2B _SFR_MEM8(0xB4) -+ -+/* Reserved [0xB5] */ -+ -+#define ASSR _SFR_MEM8(0xB6) -+#define TCR2BUB 0 -+#define TCR2AUB 1 -+#define OCR2BUB 2 -+#define OCR2AUB 3 -+#define TCN2UB 4 -+#define AS2 5 -+#define EXCLK 6 -+ -+/* Reserved [0xB7] */ -+ -+#define TWBR _SFR_MEM8(0xB8) -+ -+#define TWSR _SFR_MEM8(0xB9) -+#define TWPS0 0 -+#define TWPS1 1 -+#define TWS3 3 -+#define TWS4 4 -+#define TWS5 5 -+#define TWS6 6 -+#define TWS7 7 -+ -+#define TWAR _SFR_MEM8(0xBA) -+#define TWGCE 0 -+#define TWA0 1 -+#define TWA1 2 -+#define TWA2 3 -+#define TWA3 4 -+#define TWA4 5 -+#define TWA5 6 -+#define TWA6 7 -+ -+#define TWDR _SFR_MEM8(0xBB) -+ -+#define TWCR _SFR_MEM8(0xBC) -+#define TWIE 0 -+#define TWEN 2 -+#define TWWC 3 -+#define TWSTO 4 -+#define TWSTA 5 -+#define TWEA 6 -+#define TWINT 7 -+ -+#define TWAMR _SFR_MEM8(0xBD) -+#define TWAM0 1 -+#define TWAM1 2 -+#define TWAM2 3 -+#define TWAM3 4 -+#define TWAM4 5 -+#define TWAM5 6 -+#define TWAM6 7 -+ -+/* Reserved [0xBE..0xBF] */ -+ -+#define UCSR0A _SFR_MEM8(0xC0) -+#define MPCM0 0 -+#define U2X0 1 -+#define UPE0 2 -+#define DOR0 3 -+#define FE0 4 -+#define UDRE0 5 -+#define TXC0 6 -+#define RXC0 7 -+ -+#define UCSR0B _SFR_MEM8(0xC1) -+#define TXB80 0 -+#define RXB80 1 -+#define UCSZ02 2 -+#define TXEN0 3 -+#define RXEN0 4 -+#define UDRIE0 5 -+#define TXCIE0 6 -+#define RXCIE0 7 -+ -+#define UCSR0C _SFR_MEM8(0xC2) -+#define UCPOL0 0 -+#define UCSZ00 1 -+#define UCSZ01 2 -+#define USBS0 3 -+#define UPM00 4 -+#define UPM01 5 -+#define UMSEL00 6 -+#define UMSEL01 7 -+ -+/* Reserved [0xC3] */ -+ -+/* Combine UBRR0L and UBRR0H */ -+#define UBRR0 _SFR_MEM16(0xC4) -+ -+#define UBRR0L _SFR_MEM8(0xC4) -+#define UBRR0H _SFR_MEM8(0xC5) -+ -+#define UDR0 _SFR_MEM8(0xC6) -+ -+/* Reserved [0xC7] */ -+ -+#define UCSR1A _SFR_MEM8(0xC8) -+#define MPCM1 0 -+#define U2X1 1 -+#define UPE1 2 -+#define DOR1 3 -+#define FE1 4 -+#define UDRE1 5 -+#define TXC1 6 -+#define RXC1 7 -+ -+#define UCSR1B _SFR_MEM8(0xC9) -+#define TXB81 0 -+#define RXB81 1 -+#define UCSZ12 2 -+#define TXEN1 3 -+#define RXEN1 4 -+#define UDRIE1 5 -+#define TXCIE1 6 -+#define RXCIE1 7 -+ -+#define UCSR1C _SFR_MEM8(0xCA) -+#define UCPOL1 0 -+#define UCSZ10 1 -+#define UCSZ11 2 -+#define USBS1 3 -+#define UPM10 4 -+#define UPM11 5 -+#define UMSEL10 6 -+#define UMSEL11 7 -+ -+/* Reserved [0xCB] */ -+ -+/* Combine UBRR1L and UBRR1H */ -+#define UBRR1 _SFR_MEM16(0xCC) -+ -+#define UBRR1L _SFR_MEM8(0xCC) -+#define UBRR1H _SFR_MEM8(0xCD) -+ -+#define UDR1 _SFR_MEM8(0xCE) -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* External Interrupt Request 2 */ -+#define INT2_vect _VECTOR(3) -+#define INT2_vect_num 3 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(4) -+#define PCINT0_vect_num 4 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(5) -+#define PCINT1_vect_num 5 -+ -+/* Pin Change Interrupt Request 2 */ -+#define PCINT2_vect _VECTOR(6) -+#define PCINT2_vect_num 6 -+ -+/* Pin Change Interrupt Request 3 */ -+#define PCINT3_vect _VECTOR(7) -+#define PCINT3_vect_num 7 -+ -+/* Watchdog Time-out Interrupt */ -+#define WDT_vect _VECTOR(8) -+#define WDT_vect_num 8 -+ -+/* Timer/Counter2 Compare Match A */ -+#define TIMER2_COMPA_vect _VECTOR(9) -+#define TIMER2_COMPA_vect_num 9 -+ -+/* Timer/Counter2 Compare Match B */ -+#define TIMER2_COMPB_vect _VECTOR(10) -+#define TIMER2_COMPB_vect_num 10 -+ -+/* Timer/Counter2 Overflow */ -+#define TIMER2_OVF_vect _VECTOR(11) -+#define TIMER2_OVF_vect_num 11 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(12) -+#define TIMER1_CAPT_vect_num 12 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(13) -+#define TIMER1_COMPA_vect_num 13 -+ -+/* Timer/Counter1 Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(14) -+#define TIMER1_COMPB_vect_num 14 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(15) -+#define TIMER1_OVF_vect_num 15 -+ -+/* Timer/Counter0 Compare Match A */ -+#define TIMER0_COMPA_vect _VECTOR(16) -+#define TIMER0_COMPA_vect_num 16 -+ -+/* Timer/Counter0 Compare Match B */ -+#define TIMER0_COMPB_vect _VECTOR(17) -+#define TIMER0_COMPB_vect_num 17 -+ -+/* Timer/Counter0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(18) -+#define TIMER0_OVF_vect_num 18 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(19) -+#define SPI_STC_vect_num 19 -+ -+/* USART0, Rx Complete */ -+#define USART0_RX_vect _VECTOR(20) -+#define USART0_RX_vect_num 20 -+ -+/* USART0 Data register Empty */ -+#define USART0_UDRE_vect _VECTOR(21) -+#define USART0_UDRE_vect_num 21 -+ -+/* USART0, Tx Complete */ -+#define USART0_TX_vect _VECTOR(22) -+#define USART0_TX_vect_num 22 -+ -+/* Analog Comparator */ -+#define ANALOG_COMP_vect _VECTOR(23) -+#define ANALOG_COMP_vect_num 23 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(24) -+#define ADC_vect_num 24 -+ -+/* EEPROM Ready */ -+#define EE_READY_vect _VECTOR(25) -+#define EE_READY_vect_num 25 -+ -+/* 2-wire Serial Interface */ -+#define TWI_vect _VECTOR(26) -+#define TWI_vect_num 26 -+ -+/* Store Program Memory Read */ -+#define SPM_READY_vect _VECTOR(27) -+#define SPM_READY_vect_num 27 -+ -+/* USART1 RX complete */ -+#define USART1_RX_vect _VECTOR(28) -+#define USART1_RX_vect_num 28 -+ -+/* USART1 Data Register Empty */ -+#define USART1_UDRE_vect _VECTOR(29) -+#define USART1_UDRE_vect_num 29 -+ -+/* USART1 TX complete */ -+#define USART1_TX_vect _VECTOR(30) -+#define USART1_TX_vect_num 30 -+ -+/* Timer/Counter3 Capture Event */ -+#define TIMER3_CAPT_vect _VECTOR(31) -+#define TIMER3_CAPT_vect_num 31 -+ -+/* Timer/Counter3 Compare Match A */ -+#define TIMER3_COMPA_vect _VECTOR(32) -+#define TIMER3_COMPA_vect_num 32 -+ -+/* Timer/Counter3 Compare Match B */ -+#define TIMER3_COMPB_vect _VECTOR(33) -+#define TIMER3_COMPB_vect_num 33 -+ -+/* Timer/Counter3 Overflow */ -+#define TIMER3_OVF_vect _VECTOR(34) -+#define TIMER3_OVF_vect_num 34 -+ -+#define _VECTORS_SIZE 140 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 256 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x1FFFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 16384 -+#define RAMEND 0x40FF -+#define E2START 0 -+#define E2SIZE 4096 -+#define E2PAGESIZE 8 -+#define E2END 0x0FFF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -+#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_JTAGEN (unsigned char)~_BV(6) -+#define FUSE_OCDEN (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x97 -+#define SIGNATURE_2 0x06 -+ -+ -+#endif /* #ifdef _AVR_ATMEGA1284_H_INCLUDED */ -+ -diff --git a/include/avr/iom1284rfr2.h b/include/avr/iom1284rfr2.h -new file mode 100644 -index 0000000..8b8ae14 ---- /dev/null -+++ b/include/avr/iom1284rfr2.h -@@ -0,0 +1,2563 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATMEGA1284RFR2_H_INCLUDED -+#define _AVR_ATMEGA1284RFR2_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iom1284rfr2.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINA _SFR_IO8(0x00) -+#define PINA7 7 -+#define PINA6 6 -+#define PINA5 5 -+#define PINA4 4 -+#define PINA3 3 -+#define PINA2 2 -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x01) -+#define DDRA7 7 -+#define DDRA6 6 -+#define DDRA5 5 -+#define DDRA4 4 -+#define DDRA3 3 -+#define DDRA2 2 -+#define DDRA1 1 -+#define DDRA0 0 -+ -+#define PORTA _SFR_IO8(0x02) -+#define PORTA7 7 -+#define PORTA6 6 -+#define PORTA5 5 -+#define PORTA4 4 -+#define PORTA3 3 -+#define PORTA2 2 -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x06) -+#define PINC7 7 -+#define PINC6 6 -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x07) -+#define DDRC7 7 -+#define DDRC6 6 -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x08) -+#define PORTC7 7 -+#define PORTC6 6 -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PIND _SFR_IO8(0x09) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0A) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x0B) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+#define PINE _SFR_IO8(0x0C) -+#define PINE7 7 -+#define PINE6 6 -+#define PINE5 5 -+#define PINE4 4 -+#define PINE3 3 -+#define PINE2 2 -+#define PINE1 1 -+#define PINE0 0 -+ -+#define DDRE _SFR_IO8(0x0D) -+#define DDRE7 7 -+#define DDRE6 6 -+#define DDRE5 5 -+#define DDRE4 4 -+#define DDRE3 3 -+#define DDRE2 2 -+#define DDRE1 1 -+#define DDRE0 0 -+ -+#define PORTE _SFR_IO8(0x0E) -+#define PORTE7 7 -+#define PORTE6 6 -+#define PORTE5 5 -+#define PORTE4 4 -+#define PORTE3 3 -+#define PORTE2 2 -+#define PORTE1 1 -+#define PORTE0 0 -+ -+#define PINF _SFR_IO8(0x0F) -+#define PINF7 7 -+#define PINF6 6 -+#define PINF5 5 -+#define PINF4 4 -+#define PINF3 3 -+#define PINF2 2 -+#define PINF1 1 -+#define PINF0 0 -+ -+#define DDRF _SFR_IO8(0x10) -+#define DDRF7 7 -+#define DDRF6 6 -+#define DDRF5 5 -+#define DDRF4 4 -+#define DDRF3 3 -+#define DDRF2 2 -+#define DDRF1 1 -+#define DDRF0 0 -+ -+#define PORTF _SFR_IO8(0x11) -+#define PORTF7 7 -+#define PORTF6 6 -+#define PORTF5 5 -+#define PORTF4 4 -+#define PORTF3 3 -+#define PORTF2 2 -+#define PORTF1 1 -+#define PORTF0 0 -+ -+#define PING _SFR_IO8(0x12) -+#define PING7 7 -+#define PING6 6 -+#define PING5 5 -+#define PING4 4 -+#define PING3 3 -+#define PING2 2 -+#define PING1 1 -+#define PING0 0 -+ -+#define DDRG _SFR_IO8(0x13) -+#define DDRG7 7 -+#define DDRG6 6 -+#define DDRG5 5 -+#define DDRG4 4 -+#define DDRG3 3 -+#define DDRG2 2 -+#define DDRG1 1 -+#define DDRG0 0 -+ -+#define PORTG _SFR_IO8(0x14) -+#define PORTG7 7 -+#define PORTG6 6 -+#define PORTG5 5 -+#define PORTG4 4 -+#define PORTG3 3 -+#define PORTG2 2 -+#define PORTG1 1 -+#define PORTG0 0 -+ -+#define TIFR0 _SFR_IO8(0x15) -+#define TOV0 0 -+#define OCF0A 1 -+#define OCF0B 2 -+#define Res0 3 -+#define Res1 4 -+#define Res2 5 -+#define Res3 6 -+#define Res4 7 -+ -+#define TIFR1 _SFR_IO8(0x16) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define OCF1C 3 -+#define ICF1 5 -+ -+#define TIFR2 _SFR_IO8(0x17) -+#define TOV2 0 -+#define OCF2A 1 -+#define OCF2B 2 -+ -+#define TIFR3 _SFR_IO8(0x18) -+#define TOV3 0 -+#define OCF3A 1 -+#define OCF3B 2 -+#define OCF3C 3 -+#define ICF3 5 -+ -+#define TIFR4 _SFR_IO8(0x19) -+#define TOV4 0 -+#define OCF4A 1 -+#define OCF4B 2 -+#define OCF4C 3 -+#define ICF4 5 -+ -+#define TIFR5 _SFR_IO8(0x1A) -+#define TOV5 0 -+#define OCF5A 1 -+#define OCF5B 2 -+#define OCF5C 3 -+#define ICF5 5 -+ -+#define PCIFR _SFR_IO8(0x1B) -+#define PCIF0 0 -+#define PCIF1 1 -+#define PCIF2 2 -+ -+#define EIFR _SFR_IO8(0x1C) -+#define INTF0 0 -+#define INTF1 1 -+#define INTF2 2 -+#define INTF3 3 -+#define INTF4 4 -+#define INTF5 5 -+#define INTF6 6 -+#define INTF7 7 -+ -+#define EIMSK _SFR_IO8(0x1D) -+#define INT0 0 -+#define INT1 1 -+#define INT2 2 -+#define INT3 3 -+#define INT4 4 -+#define INT5 5 -+#define INT6 6 -+#define INT7 7 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+#define GPIOR00 0 -+#define GPIOR01 1 -+#define GPIOR02 2 -+#define GPIOR03 3 -+#define GPIOR04 4 -+#define GPIOR05 5 -+#define GPIOR06 6 -+#define GPIOR07 7 -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEPE 1 -+#define EEMPE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSRSYNC 0 -+#define PSRASY 1 -+#define TSM 7 -+ -+#define TCCR0A _SFR_IO8(0x24) -+#define WGM00 0 -+#define WGM01 1 -+#define COM0B0 4 -+#define COM0B1 5 -+#define COM0A0 6 -+#define COM0A1 7 -+ -+#define TCCR0B _SFR_IO8(0x25) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define WGM02 3 -+#define FOC0B 6 -+#define FOC0A 7 -+ -+#define TCNT0 _SFR_IO8(0x26) -+ -+#define OCR0A _SFR_IO8(0x27) -+ -+#define OCR0B _SFR_IO8(0x28) -+ -+/* Reserved [0x29] */ -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+#define GPIOR10 0 -+#define GPIOR11 1 -+#define GPIOR12 2 -+#define GPIOR13 3 -+#define GPIOR14 4 -+#define GPIOR15 5 -+#define GPIOR16 6 -+#define GPIOR17 7 -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+#define GPIOR20 0 -+#define GPIOR21 1 -+#define GPIOR22 2 -+#define GPIOR23 3 -+#define GPIOR24 4 -+#define GPIOR25 5 -+#define GPIOR26 6 -+#define GPIOR27 7 -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+/* Reserved [0x2F] */ -+ -+#define ACSR _SFR_IO8(0x30) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACBG 6 -+#define ACD 7 -+ -+#define OCDR _SFR_IO8(0x31) -+#define OCDR0 0 -+#define OCDR1 1 -+#define OCDR2 2 -+#define OCDR3 3 -+#define OCDR4 4 -+#define OCDR5 5 -+#define OCDR6 6 -+#define OCDR7 7 -+ -+/* Reserved [0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define JTRF 4 -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define JTD 7 -+#define IVCE 0 -+#define IVSEL 1 -+#define PUD 4 -+ -+/* Reserved [0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define SIGRD 5 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+/* Reserved [0x38..0x3A] */ -+ -+#define RAMPZ _SFR_IO8(0x3B) -+#define RAMPZ0 0 -+#define Res5 6 -+#define Res6 7 -+ -+/* Reserved [0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCSR _SFR_MEM8(0x60) -+#define WDE 3 -+#define WDCE 4 -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDP3 5 -+#define WDIE 6 -+#define WDIF 7 -+ -+#define CLKPR _SFR_MEM8(0x61) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+#define CLKPCE 7 -+ -+/* Reserved [0x62] */ -+ -+#define PRR2 _SFR_MEM8(0x63) -+#define PRRAM0 0 -+#define PRRAM1 1 -+#define PRRAM2 2 -+#define PRRAM3 3 -+ -+#define PRR0 _SFR_MEM8(0x64) -+#define PRADC 0 -+#define PRUSART0 1 -+#define PRSPI 2 -+#define PRTIM1 3 -+#define PRPGA 4 -+#define PRTIM0 5 -+#define PRTIM2 6 -+#define PRTWI 7 -+ -+#define PRR1 _SFR_MEM8(0x65) -+#define PRUSART1 0 -+#define PRTIM3 3 -+#define PRTIM4 4 -+#define PRTIM5 5 -+#define PRTRX24 6 -+#define Res 7 -+ -+#define OSCCAL _SFR_MEM8(0x66) -+#define CAL0 0 -+#define CAL1 1 -+#define CAL2 2 -+#define CAL3 3 -+#define CAL4 4 -+#define CAL5 5 -+#define CAL6 6 -+#define CAL7 7 -+ -+#define BGCR _SFR_MEM8(0x67) -+#define BGCAL0 0 -+#define BGCAL1 1 -+#define BGCAL2 2 -+#define BGCAL_FINE0 3 -+#define BGCAL_FINE1 4 -+#define BGCAL_FINE2 5 -+#define BGCAL_FINE3 6 -+ -+#define PCICR _SFR_MEM8(0x68) -+#define PCIE0 0 -+#define PCIE1 1 -+#define PCIE2 2 -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+#define ISC20 4 -+#define ISC21 5 -+#define ISC30 6 -+#define ISC31 7 -+ -+#define EICRB _SFR_MEM8(0x6A) -+#define ISC40 0 -+#define ISC41 1 -+#define ISC50 2 -+#define ISC51 3 -+#define ISC60 4 -+#define ISC61 5 -+#define ISC70 6 -+#define ISC71 7 -+ -+#define PCMSK0 _SFR_MEM8(0x6B) -+ -+#define PCMSK1 _SFR_MEM8(0x6C) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+#define PCINT14 6 -+#define PCINT15 7 -+ -+#define PCMSK2 _SFR_MEM8(0x6D) -+#define PCINT16 0 -+#define PCINT17 1 -+#define PCINT18 2 -+#define PCINT19 3 -+#define PCINT20 4 -+#define PCINT21 5 -+#define PCINT22 6 -+#define PCINT23 7 -+ -+#define TIMSK0 _SFR_MEM8(0x6E) -+#define TOIE0 0 -+#define OCIE0A 1 -+#define OCIE0B 2 -+ -+#define TIMSK1 _SFR_MEM8(0x6F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define OCIE1C 3 -+#define ICIE1 5 -+ -+#define TIMSK2 _SFR_MEM8(0x70) -+#define TOIE2 0 -+#define OCIE2A 1 -+#define OCIE2B 2 -+ -+#define TIMSK3 _SFR_MEM8(0x71) -+#define TOIE3 0 -+#define OCIE3A 1 -+#define OCIE3B 2 -+#define OCIE3C 3 -+#define ICIE3 5 -+ -+#define TIMSK4 _SFR_MEM8(0x72) -+#define TOIE4 0 -+#define OCIE4A 1 -+#define OCIE4B 2 -+#define OCIE4C 3 -+#define ICIE4 5 -+ -+#define TIMSK5 _SFR_MEM8(0x73) -+#define TOIE5 0 -+#define OCIE5A 1 -+#define OCIE5B 2 -+#define OCIE5C 3 -+#define ICIE5 5 -+ -+/* Reserved [0x74] */ -+ -+#define NEMCR _SFR_MEM8(0x75) -+#define AEAM0 4 -+#define AEAM1 5 -+#define ENEAM 6 -+ -+/* Reserved [0x76] */ -+ -+#define ADCSRC _SFR_MEM8(0x77) -+#define ADSUT0 0 -+#define ADSUT1 1 -+#define ADSUT2 2 -+#define ADSUT3 3 -+#define ADSUT4 4 -+#define ADTHT0 6 -+#define ADTHT1 7 -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_MEM16(0x78) -+#endif -+#define ADCW _SFR_MEM16(0x78) -+ -+#define ADCL _SFR_MEM8(0x78) -+#define ADCH _SFR_MEM8(0x79) -+ -+#define ADCSRA _SFR_MEM8(0x7A) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADCSRB _SFR_MEM8(0x7B) -+#define ACME 6 -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+#define MUX5 3 -+#define ACCH 4 -+#define REFOK 5 -+#define AVDDOK 7 -+ -+#define ADMUX _SFR_MEM8(0x7C) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define MUX4 4 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+#define DIDR2 _SFR_MEM8(0x7D) -+#define ADC8D 0 -+#define ADC9D 1 -+#define ADC10D 2 -+#define ADC11D 3 -+#define ADC12D 4 -+#define ADC13D 5 -+#define ADC14D 6 -+#define ADC15D 7 -+ -+#define DIDR0 _SFR_MEM8(0x7E) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+#define ADC6D 6 -+#define ADC7D 7 -+ -+#define DIDR1 _SFR_MEM8(0x7F) -+#define AIN0D 0 -+#define AIN1D 1 -+ -+#define TCCR1A _SFR_MEM8(0x80) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1C0 2 -+#define COM1C1 3 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR1B _SFR_MEM8(0x81) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1C _SFR_MEM8(0x82) -+#define FOC1C 5 -+#define FOC1B 6 -+#define FOC1A 7 -+ -+/* Reserved [0x83] */ -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x84) -+ -+#define TCNT1L _SFR_MEM8(0x84) -+#define TCNT1H _SFR_MEM8(0x85) -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x86) -+ -+#define ICR1L _SFR_MEM8(0x86) -+#define ICR1H _SFR_MEM8(0x87) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_MEM16(0x88) -+ -+#define OCR1AL _SFR_MEM8(0x88) -+#define OCR1AH _SFR_MEM8(0x89) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_MEM16(0x8A) -+ -+#define OCR1BL _SFR_MEM8(0x8A) -+#define OCR1BH _SFR_MEM8(0x8B) -+ -+/* Combine OCR1CL and OCR1CH */ -+#define OCR1C _SFR_MEM16(0x8C) -+ -+#define OCR1CL _SFR_MEM8(0x8C) -+#define OCR1CH _SFR_MEM8(0x8D) -+ -+/* Reserved [0x8E..0x8F] */ -+ -+#define TCCR3A _SFR_MEM8(0x90) -+#define WGM30 0 -+#define WGM31 1 -+#define COM3C0 2 -+#define COM3C1 3 -+#define COM3B0 4 -+#define COM3B1 5 -+#define COM3A0 6 -+#define COM3A1 7 -+ -+#define TCCR3B _SFR_MEM8(0x91) -+#define CS30 0 -+#define CS31 1 -+#define CS32 2 -+#define WGM32 3 -+#define WGM33 4 -+#define ICES3 6 -+#define ICNC3 7 -+ -+#define TCCR3C _SFR_MEM8(0x92) -+#define FOC3C 5 -+#define FOC3B 6 -+#define FOC3A 7 -+ -+/* Reserved [0x93] */ -+ -+/* Combine TCNT3L and TCNT3H */ -+#define TCNT3 _SFR_MEM16(0x94) -+ -+#define TCNT3L _SFR_MEM8(0x94) -+#define TCNT3H _SFR_MEM8(0x95) -+ -+/* Combine ICR3L and ICR3H */ -+#define ICR3 _SFR_MEM16(0x96) -+ -+#define ICR3L _SFR_MEM8(0x96) -+#define ICR3H _SFR_MEM8(0x97) -+ -+/* Combine OCR3AL and OCR3AH */ -+#define OCR3A _SFR_MEM16(0x98) -+ -+#define OCR3AL _SFR_MEM8(0x98) -+#define OCR3AH _SFR_MEM8(0x99) -+ -+/* Combine OCR3BL and OCR3BH */ -+#define OCR3B _SFR_MEM16(0x9A) -+ -+#define OCR3BL _SFR_MEM8(0x9A) -+#define OCR3BH _SFR_MEM8(0x9B) -+ -+/* Combine OCR3CL and OCR3CH */ -+#define OCR3C _SFR_MEM16(0x9C) -+ -+#define OCR3CL _SFR_MEM8(0x9C) -+#define OCR3CH _SFR_MEM8(0x9D) -+ -+/* Reserved [0x9E..0x9F] */ -+ -+#define TCCR4A _SFR_MEM8(0xA0) -+#define WGM40 0 -+#define WGM41 1 -+#define COM4C0 2 -+#define COM4C1 3 -+#define COM4B0 4 -+#define COM4B1 5 -+#define COM4A0 6 -+#define COM4A1 7 -+ -+#define TCCR4B _SFR_MEM8(0xA1) -+#define CS40 0 -+#define CS41 1 -+#define CS42 2 -+#define WGM42 3 -+#define WGM43 4 -+#define ICES4 6 -+#define ICNC4 7 -+ -+#define TCCR4C _SFR_MEM8(0xA2) -+#define FOC4C 5 -+#define FOC4B 6 -+#define FOC4A 7 -+ -+/* Reserved [0xA3] */ -+ -+/* Combine TCNT4L and TCNT4H */ -+#define TCNT4 _SFR_MEM16(0xA4) -+ -+#define TCNT4L _SFR_MEM8(0xA4) -+#define TCNT4H _SFR_MEM8(0xA5) -+ -+/* Combine ICR4L and ICR4H */ -+#define ICR4 _SFR_MEM16(0xA6) -+ -+#define ICR4L _SFR_MEM8(0xA6) -+#define ICR4H _SFR_MEM8(0xA7) -+ -+/* Combine OCR4AL and OCR4AH */ -+#define OCR4A _SFR_MEM16(0xA8) -+ -+#define OCR4AL _SFR_MEM8(0xA8) -+#define OCR4AH _SFR_MEM8(0xA9) -+ -+/* Combine OCR4BL and OCR4BH */ -+#define OCR4B _SFR_MEM16(0xAA) -+ -+#define OCR4BL _SFR_MEM8(0xAA) -+#define OCR4BH _SFR_MEM8(0xAB) -+ -+/* Combine OCR4CL and OCR4CH */ -+#define OCR4C _SFR_MEM16(0xAC) -+ -+#define OCR4CL _SFR_MEM8(0xAC) -+#define OCR4CH _SFR_MEM8(0xAD) -+ -+/* Reserved [0xAE..0xAF] */ -+ -+#define TCCR2A _SFR_MEM8(0xB0) -+#define WGM20 0 -+#define WGM21 1 -+#define COM2B0 4 -+#define COM2B1 5 -+#define COM2A0 6 -+#define COM2A1 7 -+ -+#define TCCR2B _SFR_MEM8(0xB1) -+#define CS20 0 -+#define CS21 1 -+#define CS22 2 -+#define WGM22 3 -+#define FOC2B 6 -+#define FOC2A 7 -+ -+#define TCNT2 _SFR_MEM8(0xB2) -+ -+#define OCR2A _SFR_MEM8(0xB3) -+ -+#define OCR2B _SFR_MEM8(0xB4) -+ -+/* Reserved [0xB5] */ -+ -+#define ASSR _SFR_MEM8(0xB6) -+#define TCR2BUB 0 -+#define TCR2AUB 1 -+#define OCR2BUB 2 -+#define OCR2AUB 3 -+#define TCN2UB 4 -+#define AS2 5 -+#define EXCLK 6 -+#define EXCLKAMR 7 -+ -+/* Reserved [0xB7] */ -+ -+#define TWBR _SFR_MEM8(0xB8) -+ -+#define TWSR _SFR_MEM8(0xB9) -+#define TWPS0 0 -+#define TWPS1 1 -+#define TWS3 3 -+#define TWS4 4 -+#define TWS5 5 -+#define TWS6 6 -+#define TWS7 7 -+ -+#define TWAR _SFR_MEM8(0xBA) -+#define TWGCE 0 -+#define TWA0 1 -+#define TWA1 2 -+#define TWA2 3 -+#define TWA3 4 -+#define TWA4 5 -+#define TWA5 6 -+#define TWA6 7 -+ -+#define TWDR _SFR_MEM8(0xBB) -+ -+#define TWCR _SFR_MEM8(0xBC) -+#define TWIE 0 -+#define TWEN 2 -+#define TWWC 3 -+#define TWSTO 4 -+#define TWSTA 5 -+#define TWEA 6 -+#define TWINT 7 -+ -+#define TWAMR _SFR_MEM8(0xBD) -+#define TWAM0 1 -+#define TWAM1 2 -+#define TWAM2 3 -+#define TWAM3 4 -+#define TWAM4 5 -+#define TWAM5 6 -+#define TWAM6 7 -+ -+#define IRQ_MASK1 _SFR_MEM8(0xBE) -+#define TX_START_EN 0 -+#define MAF_0_AMI_EN 1 -+#define MAF_1_AMI_EN 2 -+#define MAF_2_AMI_EN 3 -+#define MAF_3_AMI_EN 4 -+ -+#define IRQ_STATUS1 _SFR_MEM8(0xBF) -+#define TX_START 0 -+#define MAF_0_AMI 1 -+#define MAF_1_AMI 2 -+#define MAF_2_AMI 3 -+#define MAF_3_AMI 4 -+ -+#define UCSR0A _SFR_MEM8(0xC0) -+#define MPCM0 0 -+#define U2X0 1 -+#define UPE0 2 -+#define DOR0 3 -+#define FE0 4 -+#define UDRE0 5 -+#define TXC0 6 -+#define RXC0 7 -+ -+#define UCSR0B _SFR_MEM8(0xC1) -+#define TXB80 0 -+#define RXB80 1 -+#define UCSZ02 2 -+#define TXEN0 3 -+#define RXEN0 4 -+#define UDRIE0 5 -+#define TXCIE0 6 -+#define RXCIE0 7 -+ -+#define UCSR0C _SFR_MEM8(0xC2) -+#define UCPOL0 0 -+#define UCSZ00 1 -+#define UCSZ01 2 -+#define USBS0 3 -+#define UPM00 4 -+#define UPM01 5 -+#define UMSEL00 6 -+#define UMSEL01 7 -+#define UCPHA0 1 -+#define UDORD0 2 -+ -+/* Reserved [0xC3] */ -+ -+/* Combine UBRR0L and UBRR0H */ -+#define UBRR0 _SFR_MEM16(0xC4) -+ -+#define UBRR0L _SFR_MEM8(0xC4) -+#define UBRR0H _SFR_MEM8(0xC5) -+ -+#define UDR0 _SFR_MEM8(0xC6) -+ -+/* Reserved [0xC7] */ -+ -+#define UCSR1A _SFR_MEM8(0xC8) -+#define MPCM1 0 -+#define U2X1 1 -+#define UPE1 2 -+#define DOR1 3 -+#define FE1 4 -+#define UDRE1 5 -+#define TXC1 6 -+#define RXC1 7 -+ -+#define UCSR1B _SFR_MEM8(0xC9) -+#define TXB81 0 -+#define RXB81 1 -+#define UCSZ12 2 -+#define TXEN1 3 -+#define RXEN1 4 -+#define UDRIE1 5 -+#define TXCIE1 6 -+#define RXCIE1 7 -+ -+#define UCSR1C _SFR_MEM8(0xCA) -+#define UCPOL1 0 -+#define UCSZ10 1 -+#define UCSZ11 2 -+#define USBS1 3 -+#define UPM10 4 -+#define UPM11 5 -+#define UMSEL10 6 -+#define UMSEL11 7 -+#define UCPHA1 1 -+#define UDORD1 2 -+ -+/* Reserved [0xCB] */ -+ -+/* Combine UBRR1L and UBRR1H */ -+#define UBRR1 _SFR_MEM16(0xCC) -+ -+#define UBRR1L _SFR_MEM8(0xCC) -+#define UBRR1H _SFR_MEM8(0xCD) -+ -+#define UDR1 _SFR_MEM8(0xCE) -+ -+/* Reserved [0xCF..0xD6] */ -+ -+#define SCRSTRLL _SFR_MEM8(0xD7) -+#define SCRSTRLL0 0 -+#define SCRSTRLL1 1 -+#define SCRSTRLL2 2 -+#define SCRSTRLL3 3 -+#define SCRSTRLL4 4 -+#define SCRSTRLL5 5 -+#define SCRSTRLL6 6 -+#define SCRSTRLL7 7 -+ -+#define SCRSTRLH _SFR_MEM8(0xD8) -+#define SCRSTRLH0 0 -+#define SCRSTRLH1 1 -+#define SCRSTRLH2 2 -+#define SCRSTRLH3 3 -+#define SCRSTRLH4 4 -+#define SCRSTRLH5 5 -+#define SCRSTRLH6 6 -+#define SCRSTRLH7 7 -+ -+#define SCRSTRHL _SFR_MEM8(0xD9) -+#define SCRSTRHL0 0 -+#define SCRSTRHL1 1 -+#define SCRSTRHL2 2 -+#define SCRSTRHL3 3 -+#define SCRSTRHL4 4 -+#define SCRSTRHL5 5 -+#define SCRSTRHL6 6 -+#define SCRSTRHL7 7 -+ -+#define SCRSTRHH _SFR_MEM8(0xDA) -+#define SCRSTRHH0 0 -+#define SCRSTRHH1 1 -+#define SCRSTRHH2 2 -+#define SCRSTRHH3 3 -+#define SCRSTRHH4 4 -+#define SCRSTRHH5 5 -+#define SCRSTRHH6 6 -+#define SCRSTRHH7 7 -+ -+#define SCCSR _SFR_MEM8(0xDB) -+#define SCCS10 0 -+#define SCCS11 1 -+#define SCCS20 2 -+#define SCCS21 3 -+#define SCCS30 4 -+#define SCCS31 5 -+ -+#define SCCR0 _SFR_MEM8(0xDC) -+#define SCCMP1 0 -+#define SCCMP2 1 -+#define SCCMP3 2 -+#define SCTSE 3 -+#define SCCKSEL 4 -+#define SCEN 5 -+#define SCMBTS 6 -+#define SCRES 7 -+ -+#define SCCR1 _SFR_MEM8(0xDD) -+#define SCENBO 0 -+#define SCEECLK 1 -+#define SCCKDIV0 2 -+#define SCCKDIV1 3 -+#define SCCKDIV2 4 -+#define SCBTSM 5 -+ -+#define SCSR _SFR_MEM8(0xDE) -+#define SCBSY 0 -+ -+#define SCIRQM _SFR_MEM8(0xDF) -+#define IRQMCP1 0 -+#define IRQMCP2 1 -+#define IRQMCP3 2 -+#define IRQMOF 3 -+#define IRQMBO 4 -+ -+#define SCIRQS _SFR_MEM8(0xE0) -+#define IRQSCP1 0 -+#define IRQSCP2 1 -+#define IRQSCP3 2 -+#define IRQSOF 3 -+#define IRQSBO 4 -+ -+#define SCCNTLL _SFR_MEM8(0xE1) -+#define SCCNTLL0 0 -+#define SCCNTLL1 1 -+#define SCCNTLL2 2 -+#define SCCNTLL3 3 -+#define SCCNTLL4 4 -+#define SCCNTLL5 5 -+#define SCCNTLL6 6 -+#define SCCNTLL7 7 -+ -+#define SCCNTLH _SFR_MEM8(0xE2) -+#define SCCNTLH0 0 -+#define SCCNTLH1 1 -+#define SCCNTLH2 2 -+#define SCCNTLH3 3 -+#define SCCNTLH4 4 -+#define SCCNTLH5 5 -+#define SCCNTLH6 6 -+#define SCCNTLH7 7 -+ -+#define SCCNTHL _SFR_MEM8(0xE3) -+#define SCCNTHL0 0 -+#define SCCNTHL1 1 -+#define SCCNTHL2 2 -+#define SCCNTHL3 3 -+#define SCCNTHL4 4 -+#define SCCNTHL5 5 -+#define SCCNTHL6 6 -+#define SCCNTHL7 7 -+ -+#define SCCNTHH _SFR_MEM8(0xE4) -+#define SCCNTHH0 0 -+#define SCCNTHH1 1 -+#define SCCNTHH2 2 -+#define SCCNTHH3 3 -+#define SCCNTHH4 4 -+#define SCCNTHH5 5 -+#define SCCNTHH6 6 -+#define SCCNTHH7 7 -+ -+#define SCBTSRLL _SFR_MEM8(0xE5) -+#define SCBTSRLL0 0 -+#define SCBTSRLL1 1 -+#define SCBTSRLL2 2 -+#define SCBTSRLL3 3 -+#define SCBTSRLL4 4 -+#define SCBTSRLL5 5 -+#define SCBTSRLL6 6 -+#define SCBTSRLL7 7 -+ -+#define SCBTSRLH _SFR_MEM8(0xE6) -+#define SCBTSRLH0 0 -+#define SCBTSRLH1 1 -+#define SCBTSRLH2 2 -+#define SCBTSRLH3 3 -+#define SCBTSRLH4 4 -+#define SCBTSRLH5 5 -+#define SCBTSRLH6 6 -+#define SCBTSRLH7 7 -+ -+#define SCBTSRHL _SFR_MEM8(0xE7) -+#define SCBTSRHL0 0 -+#define SCBTSRHL1 1 -+#define SCBTSRHL2 2 -+#define SCBTSRHL3 3 -+#define SCBTSRHL4 4 -+#define SCBTSRHL5 5 -+#define SCBTSRHL6 6 -+#define SCBTSRHL7 7 -+ -+#define SCBTSRHH _SFR_MEM8(0xE8) -+#define SCBTSRHH0 0 -+#define SCBTSRHH1 1 -+#define SCBTSRHH2 2 -+#define SCBTSRHH3 3 -+#define SCBTSRHH4 4 -+#define SCBTSRHH5 5 -+#define SCBTSRHH6 6 -+#define SCBTSRHH7 7 -+ -+#define SCTSRLL _SFR_MEM8(0xE9) -+#define SCTSRLL0 0 -+#define SCTSRLL1 1 -+#define SCTSRLL2 2 -+#define SCTSRLL3 3 -+#define SCTSRLL4 4 -+#define SCTSRLL5 5 -+#define SCTSRLL6 6 -+#define SCTSRLL7 7 -+ -+#define SCTSRLH _SFR_MEM8(0xEA) -+#define SCTSRLH0 0 -+#define SCTSRLH1 1 -+#define SCTSRLH2 2 -+#define SCTSRLH3 3 -+#define SCTSRLH4 4 -+#define SCTSRLH5 5 -+#define SCTSRLH6 6 -+#define SCTSRLH7 7 -+ -+#define SCTSRHL _SFR_MEM8(0xEB) -+#define SCTSRHL0 0 -+#define SCTSRHL1 1 -+#define SCTSRHL2 2 -+#define SCTSRHL3 3 -+#define SCTSRHL4 4 -+#define SCTSRHL5 5 -+#define SCTSRHL6 6 -+#define SCTSRHL7 7 -+ -+#define SCTSRHH _SFR_MEM8(0xEC) -+#define SCTSRHH0 0 -+#define SCTSRHH1 1 -+#define SCTSRHH2 2 -+#define SCTSRHH3 3 -+#define SCTSRHH4 4 -+#define SCTSRHH5 5 -+#define SCTSRHH6 6 -+#define SCTSRHH7 7 -+ -+#define SCOCR3LL _SFR_MEM8(0xED) -+#define SCOCR3LL0 0 -+#define SCOCR3LL1 1 -+#define SCOCR3LL2 2 -+#define SCOCR3LL3 3 -+#define SCOCR3LL4 4 -+#define SCOCR3LL5 5 -+#define SCOCR3LL6 6 -+#define SCOCR3LL7 7 -+ -+#define SCOCR3LH _SFR_MEM8(0xEE) -+#define SCOCR3LH0 0 -+#define SCOCR3LH1 1 -+#define SCOCR3LH2 2 -+#define SCOCR3LH3 3 -+#define SCOCR3LH4 4 -+#define SCOCR3LH5 5 -+#define SCOCR3LH6 6 -+#define SCOCR3LH7 7 -+ -+#define SCOCR3HL _SFR_MEM8(0xEF) -+#define SCOCR3HL0 0 -+#define SCOCR3HL1 1 -+#define SCOCR3HL2 2 -+#define SCOCR3HL3 3 -+#define SCOCR3HL4 4 -+#define SCOCR3HL5 5 -+#define SCOCR3HL6 6 -+#define SCOCR3HL7 7 -+ -+#define SCOCR3HH _SFR_MEM8(0xF0) -+#define SCOCR3HH0 0 -+#define SCOCR3HH1 1 -+#define SCOCR3HH2 2 -+#define SCOCR3HH3 3 -+#define SCOCR3HH4 4 -+#define SCOCR3HH5 5 -+#define SCOCR3HH6 6 -+#define SCOCR3HH7 7 -+ -+#define SCOCR2LL _SFR_MEM8(0xF1) -+#define SCOCR2LL0 0 -+#define SCOCR2LL1 1 -+#define SCOCR2LL2 2 -+#define SCOCR2LL3 3 -+#define SCOCR2LL4 4 -+#define SCOCR2LL5 5 -+#define SCOCR2LL6 6 -+#define SCOCR2LL7 7 -+ -+#define SCOCR2LH _SFR_MEM8(0xF2) -+#define SCOCR2LH0 0 -+#define SCOCR2LH1 1 -+#define SCOCR2LH2 2 -+#define SCOCR2LH3 3 -+#define SCOCR2LH4 4 -+#define SCOCR2LH5 5 -+#define SCOCR2LH6 6 -+#define SCOCR2LH7 7 -+ -+#define SCOCR2HL _SFR_MEM8(0xF3) -+#define SCOCR2HL0 0 -+#define SCOCR2HL1 1 -+#define SCOCR2HL2 2 -+#define SCOCR2HL3 3 -+#define SCOCR2HL4 4 -+#define SCOCR2HL5 5 -+#define SCOCR2HL6 6 -+#define SCOCR2HL7 7 -+ -+#define SCOCR2HH _SFR_MEM8(0xF4) -+#define SCOCR2HH0 0 -+#define SCOCR2HH1 1 -+#define SCOCR2HH2 2 -+#define SCOCR2HH3 3 -+#define SCOCR2HH4 4 -+#define SCOCR2HH5 5 -+#define SCOCR2HH6 6 -+#define SCOCR2HH7 7 -+ -+#define SCOCR1LL _SFR_MEM8(0xF5) -+#define SCOCR1LL0 0 -+#define SCOCR1LL1 1 -+#define SCOCR1LL2 2 -+#define SCOCR1LL3 3 -+#define SCOCR1LL4 4 -+#define SCOCR1LL5 5 -+#define SCOCR1LL6 6 -+#define SCOCR1LL7 7 -+ -+#define SCOCR1LH _SFR_MEM8(0xF6) -+#define SCOCR1LH0 0 -+#define SCOCR1LH1 1 -+#define SCOCR1LH2 2 -+#define SCOCR1LH3 3 -+#define SCOCR1LH4 4 -+#define SCOCR1LH5 5 -+#define SCOCR1LH6 6 -+#define SCOCR1LH7 7 -+ -+#define SCOCR1HL _SFR_MEM8(0xF7) -+#define SCOCR1HL0 0 -+#define SCOCR1HL1 1 -+#define SCOCR1HL2 2 -+#define SCOCR1HL3 3 -+#define SCOCR1HL4 4 -+#define SCOCR1HL5 5 -+#define SCOCR1HL6 6 -+#define SCOCR1HL7 7 -+ -+#define SCOCR1HH _SFR_MEM8(0xF8) -+#define SCOCR1HH0 0 -+#define SCOCR1HH1 1 -+#define SCOCR1HH2 2 -+#define SCOCR1HH3 3 -+#define SCOCR1HH4 4 -+#define SCOCR1HH5 5 -+#define SCOCR1HH6 6 -+#define SCOCR1HH7 7 -+ -+#define SCTSTRLL _SFR_MEM8(0xF9) -+#define SCTSTRLL0 0 -+#define SCTSTRLL1 1 -+#define SCTSTRLL2 2 -+#define SCTSTRLL3 3 -+#define SCTSTRLL4 4 -+#define SCTSTRLL5 5 -+#define SCTSTRLL6 6 -+#define SCTSTRLL7 7 -+ -+#define SCTSTRLH _SFR_MEM8(0xFA) -+#define SCTSTRLH0 0 -+#define SCTSTRLH1 1 -+#define SCTSTRLH2 2 -+#define SCTSTRLH3 3 -+#define SCTSTRLH4 4 -+#define SCTSTRLH5 5 -+#define SCTSTRLH6 6 -+#define SCTSTRLH7 7 -+ -+#define SCTSTRHL _SFR_MEM8(0xFB) -+#define SCTSTRHL0 0 -+#define SCTSTRHL1 1 -+#define SCTSTRHL2 2 -+#define SCTSTRHL3 3 -+#define SCTSTRHL4 4 -+#define SCTSTRHL5 5 -+#define SCTSTRHL6 6 -+#define SCTSTRHL7 7 -+ -+#define SCTSTRHH _SFR_MEM8(0xFC) -+#define SCTSTRHH0 0 -+#define SCTSTRHH1 1 -+#define SCTSTRHH2 2 -+#define SCTSTRHH3 3 -+#define SCTSTRHH4 4 -+#define SCTSTRHH5 5 -+#define SCTSTRHH6 6 -+#define SCTSTRHH7 7 -+ -+/* Reserved [0xFD..0x10B] */ -+ -+#define MAFCR0 _SFR_MEM8(0x10C) -+#define MAF0EN 0 -+#define MAF1EN 1 -+#define MAF2EN 2 -+#define MAF3EN 3 -+ -+#define MAFCR1 _SFR_MEM8(0x10D) -+#define AACK_0_I_AM_COORD 0 -+#define AACK_0_SET_PD 1 -+#define AACK_1_I_AM_COORD 2 -+#define AACK_1_SET_PD 3 -+#define AACK_2_I_AM_COORD 4 -+#define AACK_2_SET_PD 5 -+#define AACK_3_I_AM_COORD 6 -+#define AACK_3_SET_PD 7 -+ -+#define MAFSA0L _SFR_MEM8(0x10E) -+#define MAFSA0L0 0 -+#define MAFSA0L1 1 -+#define MAFSA0L2 2 -+#define MAFSA0L3 3 -+#define MAFSA0L4 4 -+#define MAFSA0L5 5 -+#define MAFSA0L6 6 -+#define MAFSA0L7 7 -+ -+#define MAFSA0H _SFR_MEM8(0x10F) -+#define MAFSA0H0 0 -+#define MAFSA0H1 1 -+#define MAFSA0H2 2 -+#define MAFSA0H3 3 -+#define MAFSA0H4 4 -+#define MAFSA0H5 5 -+#define MAFSA0H6 6 -+#define MAFSA0H7 7 -+ -+#define MAFPA0L _SFR_MEM8(0x110) -+#define MAFPA0L0 0 -+#define MAFPA0L1 1 -+#define MAFPA0L2 2 -+#define MAFPA0L3 3 -+#define MAFPA0L4 4 -+#define MAFPA0L5 5 -+#define MAFPA0L6 6 -+#define MAFPA0L7 7 -+ -+#define MAFPA0H _SFR_MEM8(0x111) -+#define MAFPA0H0 0 -+#define MAFPA0H1 1 -+#define MAFPA0H2 2 -+#define MAFPA0H3 3 -+#define MAFPA0H4 4 -+#define MAFPA0H5 5 -+#define MAFPA0H6 6 -+#define MAFPA0H7 7 -+ -+#define MAFSA1L _SFR_MEM8(0x112) -+#define MAFSA1L0 0 -+#define MAFSA1L1 1 -+#define MAFSA1L2 2 -+#define MAFSA1L3 3 -+#define MAFSA1L4 4 -+#define MAFSA1L5 5 -+#define MAFSA1L6 6 -+#define MAFSA1L7 7 -+ -+#define MAFSA1H _SFR_MEM8(0x113) -+#define MAFSA1H0 0 -+#define MAFSA1H1 1 -+#define MAFSA1H2 2 -+#define MAFSA1H3 3 -+#define MAFSA1H4 4 -+#define MAFSA1H5 5 -+#define MAFSA1H6 6 -+#define MAFSA1H7 7 -+ -+#define MAFPA1L _SFR_MEM8(0x114) -+#define MAFPA1L0 0 -+#define MAFPA1L1 1 -+#define MAFPA1L2 2 -+#define MAFPA1L3 3 -+#define MAFPA1L4 4 -+#define MAFPA1L5 5 -+#define MAFPA1L6 6 -+#define MAFPA1L7 7 -+ -+#define MAFPA1H _SFR_MEM8(0x115) -+#define MAFPA1H0 0 -+#define MAFPA1H1 1 -+#define MAFPA1H2 2 -+#define MAFPA1H3 3 -+#define MAFPA1H4 4 -+#define MAFPA1H5 5 -+#define MAFPA1H6 6 -+#define MAFPA1H7 7 -+ -+#define MAFSA2L _SFR_MEM8(0x116) -+#define MAFSA2L0 0 -+#define MAFSA2L1 1 -+#define MAFSA2L2 2 -+#define MAFSA2L3 3 -+#define MAFSA2L4 4 -+#define MAFSA2L5 5 -+#define MAFSA2L6 6 -+#define MAFSA2L7 7 -+ -+#define MAFSA2H _SFR_MEM8(0x117) -+#define MAFSA2H0 0 -+#define MAFSA2H1 1 -+#define MAFSA2H2 2 -+#define MAFSA2H3 3 -+#define MAFSA2H4 4 -+#define MAFSA2H5 5 -+#define MAFSA2H6 6 -+#define MAFSA2H7 7 -+ -+#define MAFPA2L _SFR_MEM8(0x118) -+#define MAFPA2L0 0 -+#define MAFPA2L1 1 -+#define MAFPA2L2 2 -+#define MAFPA2L3 3 -+#define MAFPA2L4 4 -+#define MAFPA2L5 5 -+#define MAFPA2L6 6 -+#define MAFPA2L7 7 -+ -+#define MAFPA2H _SFR_MEM8(0x119) -+#define MAFPA2H0 0 -+#define MAFPA2H1 1 -+#define MAFPA2H2 2 -+#define MAFPA2H3 3 -+#define MAFPA2H4 4 -+#define MAFPA2H5 5 -+#define MAFPA2H6 6 -+#define MAFPA2H7 7 -+ -+#define MAFSA3L _SFR_MEM8(0x11A) -+#define MAFSA3L0 0 -+#define MAFSA3L1 1 -+#define MAFSA3L2 2 -+#define MAFSA3L3 3 -+#define MAFSA3L4 4 -+#define MAFSA3L5 5 -+#define MAFSA3L6 6 -+#define MAFSA3L7 7 -+ -+#define MAFSA3H _SFR_MEM8(0x11B) -+#define MAFSA3H0 0 -+#define MAFSA3H1 1 -+#define MAFSA3H2 2 -+#define MAFSA3H3 3 -+#define MAFSA3H4 4 -+#define MAFSA3H5 5 -+#define MAFSA3H6 6 -+#define MAFSA3H7 7 -+ -+#define MAFPA3L _SFR_MEM8(0x11C) -+#define MAFPA3L0 0 -+#define MAFPA3L1 1 -+#define MAFPA3L2 2 -+#define MAFPA3L3 3 -+#define MAFPA3L4 4 -+#define MAFPA3L5 5 -+#define MAFPA3L6 6 -+#define MAFPA3L7 7 -+ -+#define MAFPA3H _SFR_MEM8(0x11D) -+#define MAFPA3H0 0 -+#define MAFPA3H1 1 -+#define MAFPA3H2 2 -+#define MAFPA3H3 3 -+#define MAFPA3H4 4 -+#define MAFPA3H5 5 -+#define MAFPA3H6 6 -+#define MAFPA3H7 7 -+ -+/* Reserved [0x11E..0x11F] */ -+ -+#define TCCR5A _SFR_MEM8(0x120) -+#define WGM50 0 -+#define WGM51 1 -+#define COM5C0 2 -+#define COM5C1 3 -+#define COM5B0 4 -+#define COM5B1 5 -+#define COM5A0 6 -+#define COM5A1 7 -+ -+#define TCCR5B _SFR_MEM8(0x121) -+#define CS50 0 -+#define CS51 1 -+#define CS52 2 -+#define WGM52 3 -+#define WGM53 4 -+#define ICES5 6 -+#define ICNC5 7 -+ -+#define TCCR5C _SFR_MEM8(0x122) -+#define FOC5C 5 -+#define FOC5B 6 -+#define FOC5A 7 -+ -+/* Reserved [0x123] */ -+ -+/* Combine TCNT5L and TCNT5H */ -+#define TCNT5 _SFR_MEM16(0x124) -+ -+#define TCNT5L _SFR_MEM8(0x124) -+#define TCNT5H _SFR_MEM8(0x125) -+ -+/* Combine ICR5L and ICR5H */ -+#define ICR5 _SFR_MEM16(0x126) -+ -+#define ICR5L _SFR_MEM8(0x126) -+#define ICR5H _SFR_MEM8(0x127) -+ -+/* Combine OCR5AL and OCR5AH */ -+#define OCR5A _SFR_MEM16(0x128) -+ -+#define OCR5AL _SFR_MEM8(0x128) -+#define OCR5AH _SFR_MEM8(0x129) -+ -+/* Combine OCR5BL and OCR5BH */ -+#define OCR5B _SFR_MEM16(0x12A) -+ -+#define OCR5BL _SFR_MEM8(0x12A) -+#define OCR5BH _SFR_MEM8(0x12B) -+ -+/* Combine OCR5CL and OCR5CH */ -+#define OCR5C _SFR_MEM16(0x12C) -+ -+#define OCR5CL _SFR_MEM8(0x12C) -+#define OCR5CH _SFR_MEM8(0x12D) -+ -+/* Reserved [0x12E] */ -+ -+#define LLCR _SFR_MEM8(0x12F) -+#define LLENCAL 0 -+#define LLSHORT 1 -+#define LLTCO 2 -+#define LLCAL 3 -+#define LLCOMP 4 -+#define LLDONE 5 -+ -+#define LLDRL _SFR_MEM8(0x130) -+#define LLDRL0 0 -+#define LLDRL1 1 -+#define LLDRL2 2 -+#define LLDRL3 3 -+ -+#define LLDRH _SFR_MEM8(0x131) -+#define LLDRH0 0 -+#define LLDRH1 1 -+#define LLDRH2 2 -+#define LLDRH3 3 -+#define LLDRH4 4 -+ -+#define DRTRAM3 _SFR_MEM8(0x132) -+#define ENDRT 4 -+#define DRTSWOK 5 -+ -+#define DRTRAM2 _SFR_MEM8(0x133) -+ -+#define DRTRAM1 _SFR_MEM8(0x134) -+ -+#define DRTRAM0 _SFR_MEM8(0x135) -+ -+#define DPDS0 _SFR_MEM8(0x136) -+#define PBDRV0 0 -+#define PBDRV1 1 -+#define PDDRV0 2 -+#define PDDRV1 3 -+#define PEDRV0 4 -+#define PEDRV1 5 -+#define PFDRV0 6 -+#define PFDRV1 7 -+ -+#define DPDS1 _SFR_MEM8(0x137) -+#define PGDRV0 0 -+#define PGDRV1 1 -+ -+#define PARCR _SFR_MEM8(0x138) -+#define PARUFI 0 -+#define PARDFI 1 -+#define PALTU0 2 -+#define PALTU1 3 -+#define PALTU2 4 -+#define PALTD0 5 -+#define PALTD1 6 -+#define PALTD2 7 -+ -+#define TRXPR _SFR_MEM8(0x139) -+#define TRXRST 0 -+#define SLPTR 1 -+ -+/* Reserved [0x13A..0x13B] */ -+ -+#define AES_CTRL _SFR_MEM8(0x13C) -+#define AES_IM 2 -+#define AES_DIR 3 -+#define AES_MODE 5 -+#define AES_REQUEST 7 -+ -+#define AES_STATUS _SFR_MEM8(0x13D) -+#define AES_DONE 0 -+#define AES_ER 7 -+ -+#define AES_STATE _SFR_MEM8(0x13E) -+#define AES_STATE0 0 -+#define AES_STATE1 1 -+#define AES_STATE2 2 -+#define AES_STATE3 3 -+#define AES_STATE4 4 -+#define AES_STATE5 5 -+#define AES_STATE6 6 -+#define AES_STATE7 7 -+ -+#define AES_KEY _SFR_MEM8(0x13F) -+#define AES_KEY0 0 -+#define AES_KEY1 1 -+#define AES_KEY2 2 -+#define AES_KEY3 3 -+#define AES_KEY4 4 -+#define AES_KEY5 5 -+#define AES_KEY6 6 -+#define AES_KEY7 7 -+ -+/* Reserved [0x140] */ -+ -+#define TRX_STATUS _SFR_MEM8(0x141) -+#define TRX_STATUS0 0 -+#define TRX_STATUS1 1 -+#define TRX_STATUS2 2 -+#define TRX_STATUS3 3 -+#define TRX_STATUS4 4 -+#define TST_STATUS 5 -+#define CCA_STATUS 6 -+#define CCA_DONE 7 -+ -+#define TRX_STATE _SFR_MEM8(0x142) -+#define TRX_CMD0 0 -+#define TRX_CMD1 1 -+#define TRX_CMD2 2 -+#define TRX_CMD3 3 -+#define TRX_CMD4 4 -+#define TRAC_STATUS0 5 -+#define TRAC_STATUS1 6 -+#define TRAC_STATUS2 7 -+ -+#define TRX_CTRL_0 _SFR_MEM8(0x143) -+#define PMU_IF_INV 4 -+#define PMU_START 5 -+#define PMU_EN 6 -+#define Res7 7 -+ -+#define TRX_CTRL_1 _SFR_MEM8(0x144) -+#define PLL_TX_FLT 4 -+#define TX_AUTO_CRC_ON 5 -+#define IRQ_2_EXT_EN 6 -+#define PA_EXT_EN 7 -+ -+#define PHY_TX_PWR _SFR_MEM8(0x145) -+#define TX_PWR0 0 -+#define TX_PWR1 1 -+#define TX_PWR2 2 -+#define TX_PWR3 3 -+ -+#define PHY_RSSI _SFR_MEM8(0x146) -+#define RSSI0 0 -+#define RSSI1 1 -+#define RSSI2 2 -+#define RSSI3 3 -+#define RSSI4 4 -+#define RND_VALUE0 5 -+#define RND_VALUE1 6 -+#define RX_CRC_VALID 7 -+ -+#define PHY_ED_LEVEL _SFR_MEM8(0x147) -+#define ED_LEVEL0 0 -+#define ED_LEVEL1 1 -+#define ED_LEVEL2 2 -+#define ED_LEVEL3 3 -+#define ED_LEVEL4 4 -+#define ED_LEVEL5 5 -+#define ED_LEVEL6 6 -+#define ED_LEVEL7 7 -+ -+#define PHY_CC_CCA _SFR_MEM8(0x148) -+#define CHANNEL0 0 -+#define CHANNEL1 1 -+#define CHANNEL2 2 -+#define CHANNEL3 3 -+#define CHANNEL4 4 -+#define CCA_MODE0 5 -+#define CCA_MODE1 6 -+#define CCA_REQUEST 7 -+ -+#define CCA_THRES _SFR_MEM8(0x149) -+#define CCA_ED_THRES0 0 -+#define CCA_ED_THRES1 1 -+#define CCA_ED_THRES2 2 -+#define CCA_ED_THRES3 3 -+#define CCA_CS_THRES0 4 -+#define CCA_CS_THRES1 5 -+#define CCA_CS_THRES2 6 -+#define CCA_CS_THRES3 7 -+ -+#define RX_CTRL _SFR_MEM8(0x14A) -+#define PDT_THRES0 0 -+#define PDT_THRES1 1 -+#define PDT_THRES2 2 -+#define PDT_THRES3 3 -+ -+#define SFD_VALUE _SFR_MEM8(0x14B) -+#define SFD_VALUE0 0 -+#define SFD_VALUE1 1 -+#define SFD_VALUE2 2 -+#define SFD_VALUE3 3 -+#define SFD_VALUE4 4 -+#define SFD_VALUE5 5 -+#define SFD_VALUE6 6 -+#define SFD_VALUE7 7 -+ -+#define TRX_CTRL_2 _SFR_MEM8(0x14C) -+#define OQPSK_DATA_RATE0 0 -+#define OQPSK_DATA_RATE1 1 -+#define RX_SAFE_MODE 7 -+ -+#define ANT_DIV _SFR_MEM8(0x14D) -+#define ANT_CTRL0 0 -+#define ANT_CTRL1 1 -+#define ANT_EXT_SW_EN 2 -+#define ANT_DIV_EN 3 -+#define ANT_SEL 7 -+ -+#define IRQ_MASK _SFR_MEM8(0x14E) -+#define PLL_LOCK_EN 0 -+#define PLL_UNLOCK_EN 1 -+#define RX_START_EN 2 -+#define RX_END_EN 3 -+#define CCA_ED_DONE_EN 4 -+#define AMI_EN 5 -+#define TX_END_EN 6 -+#define AWAKE_EN 7 -+ -+#define IRQ_STATUS _SFR_MEM8(0x14F) -+#define PLL_LOCK 0 -+#define PLL_UNLOCK 1 -+#define RX_START 2 -+#define RX_END 3 -+#define CCA_ED_DONE 4 -+#define AMI 5 -+#define TX_END 6 -+#define AWAKE 7 -+ -+#define VREG_CTRL _SFR_MEM8(0x150) -+#define DVDD_OK 2 -+#define DVREG_EXT 3 -+#define AVDD_OK 6 -+#define AVREG_EXT 7 -+ -+#define BATMON _SFR_MEM8(0x151) -+#define BATMON_VTH0 0 -+#define BATMON_VTH1 1 -+#define BATMON_VTH2 2 -+#define BATMON_VTH3 3 -+#define BATMON_HR 4 -+#define BATMON_OK 5 -+#define BAT_LOW_EN 6 -+#define BAT_LOW 7 -+ -+#define XOSC_CTRL _SFR_MEM8(0x152) -+#define XTAL_TRIM0 0 -+#define XTAL_TRIM1 1 -+#define XTAL_TRIM2 2 -+#define XTAL_TRIM3 3 -+#define XTAL_MODE0 4 -+#define XTAL_MODE1 5 -+#define XTAL_MODE2 6 -+#define XTAL_MODE3 7 -+ -+#define CC_CTRL_0 _SFR_MEM8(0x153) -+#define CC_NUMBER0 0 -+#define CC_NUMBER1 1 -+#define CC_NUMBER2 2 -+#define CC_NUMBER3 3 -+#define CC_NUMBER4 4 -+#define CC_NUMBER5 5 -+#define CC_NUMBER6 6 -+#define CC_NUMBER7 7 -+ -+#define CC_CTRL_1 _SFR_MEM8(0x154) -+#define CC_BAND0 0 -+#define CC_BAND1 1 -+#define CC_BAND2 2 -+#define CC_BAND3 3 -+ -+#define RX_SYN _SFR_MEM8(0x155) -+#define RX_PDT_LEVEL0 0 -+#define RX_PDT_LEVEL1 1 -+#define RX_PDT_LEVEL2 2 -+#define RX_PDT_LEVEL3 3 -+#define RX_OVERRIDE 6 -+#define RX_PDT_DIS 7 -+ -+#define TRX_RPC _SFR_MEM8(0x156) -+#define XAH_RPC_EN 0 -+#define IPAN_RPC_EN 1 -+#define PLL_RPC_EN 3 -+#define PDT_RPC_EN 4 -+#define RX_RPC_EN 5 -+#define RX_RPC_CTRL0 6 -+#define RX_RPC_CTRL1 7 -+ -+#define XAH_CTRL_1 _SFR_MEM8(0x157) -+#define AACK_PROM_MODE 1 -+#define AACK_ACK_TIME 2 -+#define AACK_UPLD_RES_FT 4 -+#define AACK_FLTR_RES_FT 5 -+ -+#define FTN_CTRL _SFR_MEM8(0x158) -+#define FTN_START 7 -+ -+/* Reserved [0x159] */ -+ -+#define PLL_CF _SFR_MEM8(0x15A) -+#define PLL_CF_START 7 -+ -+#define PLL_DCU _SFR_MEM8(0x15B) -+#define PLL_DCU_START 7 -+ -+#define PART_NUM _SFR_MEM8(0x15C) -+#define PART_NUM0 0 -+#define PART_NUM1 1 -+#define PART_NUM2 2 -+#define PART_NUM3 3 -+#define PART_NUM4 4 -+#define PART_NUM5 5 -+#define PART_NUM6 6 -+#define PART_NUM7 7 -+ -+#define VERSION_NUM _SFR_MEM8(0x15D) -+#define VERSION_NUM0 0 -+#define VERSION_NUM1 1 -+#define VERSION_NUM2 2 -+#define VERSION_NUM3 3 -+#define VERSION_NUM4 4 -+#define VERSION_NUM5 5 -+#define VERSION_NUM6 6 -+#define VERSION_NUM7 7 -+ -+#define MAN_ID_0 _SFR_MEM8(0x15E) -+#define MAN_ID_00 0 -+#define MAN_ID_01 1 -+#define MAN_ID_02 2 -+#define MAN_ID_03 3 -+#define MAN_ID_04 4 -+#define MAN_ID_05 5 -+#define MAN_ID_06 6 -+#define MAN_ID_07 7 -+ -+#define MAN_ID_1 _SFR_MEM8(0x15F) -+#define MAN_ID_10 0 -+#define MAN_ID_11 1 -+#define MAN_ID_12 2 -+#define MAN_ID_13 3 -+#define MAN_ID_14 4 -+#define MAN_ID_15 5 -+#define MAN_ID_16 6 -+#define MAN_ID_17 7 -+ -+#define SHORT_ADDR_0 _SFR_MEM8(0x160) -+#define SHORT_ADDR_00 0 -+#define SHORT_ADDR_01 1 -+#define SHORT_ADDR_02 2 -+#define SHORT_ADDR_03 3 -+#define SHORT_ADDR_04 4 -+#define SHORT_ADDR_05 5 -+#define SHORT_ADDR_06 6 -+#define SHORT_ADDR_07 7 -+ -+#define SHORT_ADDR_1 _SFR_MEM8(0x161) -+#define SHORT_ADDR_10 0 -+#define SHORT_ADDR_11 1 -+#define SHORT_ADDR_12 2 -+#define SHORT_ADDR_13 3 -+#define SHORT_ADDR_14 4 -+#define SHORT_ADDR_15 5 -+#define SHORT_ADDR_16 6 -+#define SHORT_ADDR_17 7 -+ -+#define PAN_ID_0 _SFR_MEM8(0x162) -+#define PAN_ID_00 0 -+#define PAN_ID_01 1 -+#define PAN_ID_02 2 -+#define PAN_ID_03 3 -+#define PAN_ID_04 4 -+#define PAN_ID_05 5 -+#define PAN_ID_06 6 -+#define PAN_ID_07 7 -+ -+#define PAN_ID_1 _SFR_MEM8(0x163) -+#define PAN_ID_10 0 -+#define PAN_ID_11 1 -+#define PAN_ID_12 2 -+#define PAN_ID_13 3 -+#define PAN_ID_14 4 -+#define PAN_ID_15 5 -+#define PAN_ID_16 6 -+#define PAN_ID_17 7 -+ -+#define IEEE_ADDR_0 _SFR_MEM8(0x164) -+#define IEEE_ADDR_00 0 -+#define IEEE_ADDR_01 1 -+#define IEEE_ADDR_02 2 -+#define IEEE_ADDR_03 3 -+#define IEEE_ADDR_04 4 -+#define IEEE_ADDR_05 5 -+#define IEEE_ADDR_06 6 -+#define IEEE_ADDR_07 7 -+ -+#define IEEE_ADDR_1 _SFR_MEM8(0x165) -+#define IEEE_ADDR_10 0 -+#define IEEE_ADDR_11 1 -+#define IEEE_ADDR_12 2 -+#define IEEE_ADDR_13 3 -+#define IEEE_ADDR_14 4 -+#define IEEE_ADDR_15 5 -+#define IEEE_ADDR_16 6 -+#define IEEE_ADDR_17 7 -+ -+#define IEEE_ADDR_2 _SFR_MEM8(0x166) -+#define IEEE_ADDR_20 0 -+#define IEEE_ADDR_21 1 -+#define IEEE_ADDR_22 2 -+#define IEEE_ADDR_23 3 -+#define IEEE_ADDR_24 4 -+#define IEEE_ADDR_25 5 -+#define IEEE_ADDR_26 6 -+#define IEEE_ADDR_27 7 -+ -+#define IEEE_ADDR_3 _SFR_MEM8(0x167) -+#define IEEE_ADDR_30 0 -+#define IEEE_ADDR_31 1 -+#define IEEE_ADDR_32 2 -+#define IEEE_ADDR_33 3 -+#define IEEE_ADDR_34 4 -+#define IEEE_ADDR_35 5 -+#define IEEE_ADDR_36 6 -+#define IEEE_ADDR_37 7 -+ -+#define IEEE_ADDR_4 _SFR_MEM8(0x168) -+#define IEEE_ADDR_40 0 -+#define IEEE_ADDR_41 1 -+#define IEEE_ADDR_42 2 -+#define IEEE_ADDR_43 3 -+#define IEEE_ADDR_44 4 -+#define IEEE_ADDR_45 5 -+#define IEEE_ADDR_46 6 -+#define IEEE_ADDR_47 7 -+ -+#define IEEE_ADDR_5 _SFR_MEM8(0x169) -+#define IEEE_ADDR_50 0 -+#define IEEE_ADDR_51 1 -+#define IEEE_ADDR_52 2 -+#define IEEE_ADDR_53 3 -+#define IEEE_ADDR_54 4 -+#define IEEE_ADDR_55 5 -+#define IEEE_ADDR_56 6 -+#define IEEE_ADDR_57 7 -+ -+#define IEEE_ADDR_6 _SFR_MEM8(0x16A) -+#define IEEE_ADDR_60 0 -+#define IEEE_ADDR_61 1 -+#define IEEE_ADDR_62 2 -+#define IEEE_ADDR_63 3 -+#define IEEE_ADDR_64 4 -+#define IEEE_ADDR_65 5 -+#define IEEE_ADDR_66 6 -+#define IEEE_ADDR_67 7 -+ -+#define IEEE_ADDR_7 _SFR_MEM8(0x16B) -+#define IEEE_ADDR_70 0 -+#define IEEE_ADDR_71 1 -+#define IEEE_ADDR_72 2 -+#define IEEE_ADDR_73 3 -+#define IEEE_ADDR_74 4 -+#define IEEE_ADDR_75 5 -+#define IEEE_ADDR_76 6 -+#define IEEE_ADDR_77 7 -+ -+#define XAH_CTRL_0 _SFR_MEM8(0x16C) -+#define SLOTTED_OPERATION 0 -+#define MAX_CSMA_RETRIES0 1 -+#define MAX_CSMA_RETRIES1 2 -+#define MAX_CSMA_RETRIES2 3 -+#define MAX_FRAME_RETRIES0 4 -+#define MAX_FRAME_RETRIES1 5 -+#define MAX_FRAME_RETRIES2 6 -+#define MAX_FRAME_RETRIES3 7 -+ -+#define CSMA_SEED_0 _SFR_MEM8(0x16D) -+#define CSMA_SEED_00 0 -+#define CSMA_SEED_01 1 -+#define CSMA_SEED_02 2 -+#define CSMA_SEED_03 3 -+#define CSMA_SEED_04 4 -+#define CSMA_SEED_05 5 -+#define CSMA_SEED_06 6 -+#define CSMA_SEED_07 7 -+ -+#define CSMA_SEED_1 _SFR_MEM8(0x16E) -+#define CSMA_SEED_10 0 -+#define CSMA_SEED_11 1 -+#define CSMA_SEED_12 2 -+#define AACK_I_AM_COORD 3 -+#define AACK_DIS_ACK 4 -+#define AACK_SET_PD 5 -+#define AACK_FVN_MODE0 6 -+#define AACK_FVN_MODE1 7 -+ -+#define CSMA_BE _SFR_MEM8(0x16F) -+#define MIN_BE0 0 -+#define MIN_BE1 1 -+#define MIN_BE2 2 -+#define MIN_BE3 3 -+#define MAX_BE0 4 -+#define MAX_BE1 5 -+#define MAX_BE2 6 -+#define MAX_BE3 7 -+ -+/* Reserved [0x170..0x175] */ -+ -+#define TST_CTRL_DIGI _SFR_MEM8(0x176) -+#define TST_CTRL_DIG0 0 -+#define TST_CTRL_DIG1 1 -+#define TST_CTRL_DIG2 2 -+#define TST_CTRL_DIG3 3 -+ -+/* Reserved [0x177..0x17A] */ -+ -+#define TST_RX_LENGTH _SFR_MEM8(0x17B) -+#define RX_LENGTH0 0 -+#define RX_LENGTH1 1 -+#define RX_LENGTH2 2 -+#define RX_LENGTH3 3 -+#define RX_LENGTH4 4 -+#define RX_LENGTH5 5 -+#define RX_LENGTH6 6 -+#define RX_LENGTH7 7 -+ -+/* Reserved [0x17C..0x17F] */ -+ -+#define TRXFBST _SFR_MEM8(0x180) -+ -+/* Reserved [0x181..0x1FE] */ -+ -+#define TRXFBEND _SFR_MEM8(0x1FF) -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* External Interrupt Request 2 */ -+#define INT2_vect _VECTOR(3) -+#define INT2_vect_num 3 -+ -+/* External Interrupt Request 3 */ -+#define INT3_vect _VECTOR(4) -+#define INT3_vect_num 4 -+ -+/* External Interrupt Request 4 */ -+#define INT4_vect _VECTOR(5) -+#define INT4_vect_num 5 -+ -+/* External Interrupt Request 5 */ -+#define INT5_vect _VECTOR(6) -+#define INT5_vect_num 6 -+ -+/* External Interrupt Request 6 */ -+#define INT6_vect _VECTOR(7) -+#define INT6_vect_num 7 -+ -+/* External Interrupt Request 7 */ -+#define INT7_vect _VECTOR(8) -+#define INT7_vect_num 8 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(9) -+#define PCINT0_vect_num 9 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(10) -+#define PCINT1_vect_num 10 -+ -+/* Pin Change Interrupt Request 2 */ -+#define PCINT2_vect _VECTOR(11) -+#define PCINT2_vect_num 11 -+ -+/* Watchdog Time-out Interrupt */ -+#define WDT_vect _VECTOR(12) -+#define WDT_vect_num 12 -+ -+/* Timer/Counter2 Compare Match A */ -+#define TIMER2_COMPA_vect _VECTOR(13) -+#define TIMER2_COMPA_vect_num 13 -+ -+/* Timer/Counter2 Compare Match B */ -+#define TIMER2_COMPB_vect _VECTOR(14) -+#define TIMER2_COMPB_vect_num 14 -+ -+/* Timer/Counter2 Overflow */ -+#define TIMER2_OVF_vect _VECTOR(15) -+#define TIMER2_OVF_vect_num 15 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(16) -+#define TIMER1_CAPT_vect_num 16 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(17) -+#define TIMER1_COMPA_vect_num 17 -+ -+/* Timer/Counter1 Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(18) -+#define TIMER1_COMPB_vect_num 18 -+ -+/* Timer/Counter1 Compare Match C */ -+#define TIMER1_COMPC_vect _VECTOR(19) -+#define TIMER1_COMPC_vect_num 19 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(20) -+#define TIMER1_OVF_vect_num 20 -+ -+/* Timer/Counter0 Compare Match A */ -+#define TIMER0_COMPA_vect _VECTOR(21) -+#define TIMER0_COMPA_vect_num 21 -+ -+/* Timer/Counter0 Compare Match B */ -+#define TIMER0_COMPB_vect _VECTOR(22) -+#define TIMER0_COMPB_vect_num 22 -+ -+/* Timer/Counter0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(23) -+#define TIMER0_OVF_vect_num 23 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(24) -+#define SPI_STC_vect_num 24 -+ -+/* USART0, Rx Complete */ -+#define USART0_RX_vect _VECTOR(25) -+#define USART0_RX_vect_num 25 -+ -+/* USART0 Data register Empty */ -+#define USART0_UDRE_vect _VECTOR(26) -+#define USART0_UDRE_vect_num 26 -+ -+/* USART0, Tx Complete */ -+#define USART0_TX_vect _VECTOR(27) -+#define USART0_TX_vect_num 27 -+ -+/* Analog Comparator */ -+#define ANALOG_COMP_vect _VECTOR(28) -+#define ANALOG_COMP_vect_num 28 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(29) -+#define ADC_vect_num 29 -+ -+/* EEPROM Ready */ -+#define EE_READY_vect _VECTOR(30) -+#define EE_READY_vect_num 30 -+ -+/* Timer/Counter3 Capture Event */ -+#define TIMER3_CAPT_vect _VECTOR(31) -+#define TIMER3_CAPT_vect_num 31 -+ -+/* Timer/Counter3 Compare Match A */ -+#define TIMER3_COMPA_vect _VECTOR(32) -+#define TIMER3_COMPA_vect_num 32 -+ -+/* Timer/Counter3 Compare Match B */ -+#define TIMER3_COMPB_vect _VECTOR(33) -+#define TIMER3_COMPB_vect_num 33 -+ -+/* Timer/Counter3 Compare Match C */ -+#define TIMER3_COMPC_vect _VECTOR(34) -+#define TIMER3_COMPC_vect_num 34 -+ -+/* Timer/Counter3 Overflow */ -+#define TIMER3_OVF_vect _VECTOR(35) -+#define TIMER3_OVF_vect_num 35 -+ -+/* USART1, Rx Complete */ -+#define USART1_RX_vect _VECTOR(36) -+#define USART1_RX_vect_num 36 -+ -+/* USART1 Data register Empty */ -+#define USART1_UDRE_vect _VECTOR(37) -+#define USART1_UDRE_vect_num 37 -+ -+/* USART1, Tx Complete */ -+#define USART1_TX_vect _VECTOR(38) -+#define USART1_TX_vect_num 38 -+ -+/* 2-wire Serial Interface */ -+#define TWI_vect _VECTOR(39) -+#define TWI_vect_num 39 -+ -+/* Store Program Memory Read */ -+#define SPM_READY_vect _VECTOR(40) -+#define SPM_READY_vect_num 40 -+ -+/* Timer/Counter4 Capture Event */ -+#define TIMER4_CAPT_vect _VECTOR(41) -+#define TIMER4_CAPT_vect_num 41 -+ -+/* Timer/Counter4 Compare Match A */ -+#define TIMER4_COMPA_vect _VECTOR(42) -+#define TIMER4_COMPA_vect_num 42 -+ -+/* Timer/Counter4 Compare Match B */ -+#define TIMER4_COMPB_vect _VECTOR(43) -+#define TIMER4_COMPB_vect_num 43 -+ -+/* Timer/Counter4 Compare Match C */ -+#define TIMER4_COMPC_vect _VECTOR(44) -+#define TIMER4_COMPC_vect_num 44 -+ -+/* Timer/Counter4 Overflow */ -+#define TIMER4_OVF_vect _VECTOR(45) -+#define TIMER4_OVF_vect_num 45 -+ -+/* Timer/Counter5 Capture Event */ -+#define TIMER5_CAPT_vect _VECTOR(46) -+#define TIMER5_CAPT_vect_num 46 -+ -+/* Timer/Counter5 Compare Match A */ -+#define TIMER5_COMPA_vect _VECTOR(47) -+#define TIMER5_COMPA_vect_num 47 -+ -+/* Timer/Counter5 Compare Match B */ -+#define TIMER5_COMPB_vect _VECTOR(48) -+#define TIMER5_COMPB_vect_num 48 -+ -+/* Timer/Counter5 Compare Match C */ -+#define TIMER5_COMPC_vect _VECTOR(49) -+#define TIMER5_COMPC_vect_num 49 -+ -+/* Timer/Counter5 Overflow */ -+#define TIMER5_OVF_vect _VECTOR(50) -+#define TIMER5_OVF_vect_num 50 -+ -+/* USART2, Rx Complete */ -+#define USART2_RX_vect _VECTOR(51) -+#define USART2_RX_vect_num 51 -+ -+/* USART2 Data register Empty */ -+#define USART2_UDRE_vect _VECTOR(52) -+#define USART2_UDRE_vect_num 52 -+ -+/* USART2, Tx Complete */ -+#define USART2_TX_vect _VECTOR(53) -+#define USART2_TX_vect_num 53 -+ -+/* USART3, Rx Complete */ -+#define USART3_RX_vect _VECTOR(54) -+#define USART3_RX_vect_num 54 -+ -+/* USART3 Data register Empty */ -+#define USART3_UDRE_vect _VECTOR(55) -+#define USART3_UDRE_vect_num 55 -+ -+/* USART3, Tx Complete */ -+#define USART3_TX_vect _VECTOR(56) -+#define USART3_TX_vect_num 56 -+ -+/* TRX24 - PLL lock interrupt */ -+#define TRX24_PLL_LOCK_vect _VECTOR(57) -+#define TRX24_PLL_LOCK_vect_num 57 -+ -+/* TRX24 - PLL unlock interrupt */ -+#define TRX24_PLL_UNLOCK_vect _VECTOR(58) -+#define TRX24_PLL_UNLOCK_vect_num 58 -+ -+/* TRX24 - Receive start interrupt */ -+#define TRX24_RX_START_vect _VECTOR(59) -+#define TRX24_RX_START_vect_num 59 -+ -+/* TRX24 - RX_END interrupt */ -+#define TRX24_RX_END_vect _VECTOR(60) -+#define TRX24_RX_END_vect_num 60 -+ -+/* TRX24 - CCA/ED done interrupt */ -+#define TRX24_CCA_ED_DONE_vect _VECTOR(61) -+#define TRX24_CCA_ED_DONE_vect_num 61 -+ -+/* TRX24 - XAH - AMI */ -+#define TRX24_XAH_AMI_vect _VECTOR(62) -+#define TRX24_XAH_AMI_vect_num 62 -+ -+/* TRX24 - TX_END interrupt */ -+#define TRX24_TX_END_vect _VECTOR(63) -+#define TRX24_TX_END_vect_num 63 -+ -+/* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */ -+#define TRX24_AWAKE_vect _VECTOR(64) -+#define TRX24_AWAKE_vect_num 64 -+ -+/* Symbol counter - compare match 1 interrupt */ -+#define SCNT_CMP1_vect _VECTOR(65) -+#define SCNT_CMP1_vect_num 65 -+ -+/* Symbol counter - compare match 2 interrupt */ -+#define SCNT_CMP2_vect _VECTOR(66) -+#define SCNT_CMP2_vect_num 66 -+ -+/* Symbol counter - compare match 3 interrupt */ -+#define SCNT_CMP3_vect _VECTOR(67) -+#define SCNT_CMP3_vect_num 67 -+ -+/* Symbol counter - overflow interrupt */ -+#define SCNT_OVFL_vect _VECTOR(68) -+#define SCNT_OVFL_vect_num 68 -+ -+/* Symbol counter - backoff interrupt */ -+#define SCNT_BACKOFF_vect _VECTOR(69) -+#define SCNT_BACKOFF_vect_num 69 -+ -+/* AES engine ready interrupt */ -+#define AES_READY_vect _VECTOR(70) -+#define AES_READY_vect_num 70 -+ -+/* Battery monitor indicates supply voltage below threshold */ -+#define BAT_LOW_vect _VECTOR(71) -+#define BAT_LOW_vect_num 71 -+ -+/* TRX24 TX start interrupt */ -+#define TRX24_TX_START_vect _VECTOR(72) -+#define TRX24_TX_START_vect_num 72 -+ -+/* Address match interrupt of address filter 0 */ -+#define TRX24_AMI0_vect _VECTOR(73) -+#define TRX24_AMI0_vect_num 73 -+ -+/* Address match interrupt of address filter 1 */ -+#define TRX24_AMI1_vect _VECTOR(74) -+#define TRX24_AMI1_vect_num 74 -+ -+/* Address match interrupt of address filter 2 */ -+#define TRX24_AMI2_vect _VECTOR(75) -+#define TRX24_AMI2_vect_num 75 -+ -+/* Address match interrupt of address filter 3 */ -+#define TRX24_AMI3_vect _VECTOR(76) -+#define TRX24_AMI3_vect_num 76 -+ -+#define _VECTORS_SIZE 308 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 256 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x1FFFF -+#define RAMSTART 0x0200 -+#define RAMSIZE 16384 -+#define RAMEND 0x41FF -+#define E2START 0 -+#define E2SIZE 4096 -+#define E2PAGESIZE 8 -+#define E2END 0x0FFF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_CKSEL_SUT0 (unsigned char)~_BV(0) -+#define FUSE_CKSEL_SUT1 (unsigned char)~_BV(1) -+#define FUSE_CKSEL_SUT2 (unsigned char)~_BV(2) -+#define FUSE_CKSEL_SUT3 (unsigned char)~_BV(3) -+#define FUSE_CKSEL_SUT4 (unsigned char)~_BV(4) -+#define FUSE_CKSEL_SUT5 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_JTAGEN (unsigned char)~_BV(6) -+#define FUSE_OCDEN (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0xA7 -+#define SIGNATURE_2 0x03 -+ -+ -+#endif /* #ifdef _AVR_ATMEGA1284RFR2_H_INCLUDED */ -+ -diff --git a/include/avr/iom128a.h b/include/avr/iom128a.h -new file mode 100644 -index 0000000..908742c ---- /dev/null -+++ b/include/avr/iom128a.h -@@ -0,0 +1,948 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATMEGA128A_H_INCLUDED -+#define _AVR_ATMEGA128A_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iom128a.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINF _SFR_IO8(0x00) -+#define PINF7 7 -+#define PINF6 6 -+#define PINF5 5 -+#define PINF4 4 -+#define PINF3 3 -+#define PINF2 2 -+#define PINF1 1 -+#define PINF0 0 -+ -+#define PINE _SFR_IO8(0x01) -+#define PINE7 7 -+#define PINE6 6 -+#define PINE5 5 -+#define PINE4 4 -+#define PINE3 3 -+#define PINE2 2 -+#define PINE1 1 -+#define PINE0 0 -+ -+#define DDRE _SFR_IO8(0x02) -+#define DDRE7 7 -+#define DDRE6 6 -+#define DDRE5 5 -+#define DDRE4 4 -+#define DDRE3 3 -+#define DDRE2 2 -+#define DDRE1 1 -+#define DDRE0 0 -+ -+#define PORTE _SFR_IO8(0x03) -+#define PORTE7 7 -+#define PORTE6 6 -+#define PORTE5 5 -+#define PORTE4 4 -+#define PORTE3 3 -+#define PORTE2 2 -+#define PORTE1 1 -+#define PORTE0 0 -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_IO16(0x04) -+#endif -+#define ADCW _SFR_IO16(0x04) -+ -+#define ADCL _SFR_IO8(0x04) -+#define ADCH _SFR_IO8(0x05) -+ -+#define ADCSRA _SFR_IO8(0x06) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADFR 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADMUX _SFR_IO8(0x07) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define MUX4 4 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+#define ACSR _SFR_IO8(0x08) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACBG 6 -+#define ACD 7 -+ -+#define UBRR0L _SFR_IO8(0x09) -+ -+#define UCSR0B _SFR_IO8(0x0A) -+#define TXB80 0 -+#define RXB80 1 -+#define UCSZ02 2 -+#define TXEN0 3 -+#define RXEN0 4 -+#define UDRIE0 5 -+#define TXCIE0 6 -+#define RXCIE0 7 -+ -+#define UCSR0A _SFR_IO8(0x0B) -+#define MPCM0 0 -+#define U2X0 1 -+#define UPE0 2 -+#define DOR0 3 -+#define FE0 4 -+#define UDRE0 5 -+#define TXC0 6 -+#define RXC0 7 -+ -+#define UDR0 _SFR_IO8(0x0C) -+ -+#define SPCR _SFR_IO8(0x0D) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x0E) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x0F) -+ -+#define PIND _SFR_IO8(0x10) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x11) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x12) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+#define PINC _SFR_IO8(0x13) -+#define PINC7 7 -+#define PINC6 6 -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x14) -+#define DDRC7 7 -+#define DDRC6 6 -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x15) -+#define PORTC7 7 -+#define PORTC6 6 -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PINB _SFR_IO8(0x16) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x17) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x18) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINA _SFR_IO8(0x19) -+#define PINA7 7 -+#define PINA6 6 -+#define PINA5 5 -+#define PINA4 4 -+#define PINA3 3 -+#define PINA2 2 -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x1A) -+#define DDRA7 7 -+#define DDRA6 6 -+#define DDRA5 5 -+#define DDRA4 4 -+#define DDRA3 3 -+#define DDRA2 2 -+#define DDRA1 1 -+#define DDRA0 0 -+ -+#define PORTA _SFR_IO8(0x1B) -+#define PORTA7 7 -+#define PORTA6 6 -+#define PORTA5 5 -+#define PORTA4 4 -+#define PORTA3 3 -+#define PORTA2 2 -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define EECR _SFR_IO8(0x1C) -+#define EERE 0 -+#define EEWE 1 -+#define EEMWE 2 -+#define EERIE 3 -+ -+#define EEDR _SFR_IO8(0x1D) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x1E) -+ -+#define EEARL _SFR_IO8(0x1E) -+#define EEARH _SFR_IO8(0x1F) -+ -+#define SFIOR _SFR_IO8(0x20) -+#define ACME 3 -+#define PSR321 0 -+#define PSR0 1 -+#define PUD 2 -+#define TSM 7 -+ -+#define WDTCR _SFR_IO8(0x21) -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDE 3 -+#define WDCE 4 -+ -+#define OCDR _SFR_IO8(0x22) -+#define OCDR0 0 -+#define OCDR1 1 -+#define OCDR2 2 -+#define OCDR3 3 -+#define OCDR4 4 -+#define OCDR5 5 -+#define OCDR6 6 -+#define OCDR7 7 -+ -+#define OCR2 _SFR_IO8(0x23) -+ -+#define TCNT2 _SFR_IO8(0x24) -+ -+#define TCCR2 _SFR_IO8(0x25) -+#define CS20 0 -+#define CS21 1 -+#define CS22 2 -+#define WGM21 3 -+#define COM20 4 -+#define COM21 5 -+#define WGM20 6 -+#define FOC2 7 -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_IO16(0x26) -+ -+#define ICR1L _SFR_IO8(0x26) -+#define ICR1H _SFR_IO8(0x27) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_IO16(0x28) -+ -+#define OCR1BL _SFR_IO8(0x28) -+#define OCR1BH _SFR_IO8(0x29) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_IO16(0x2A) -+ -+#define OCR1AL _SFR_IO8(0x2A) -+#define OCR1AH _SFR_IO8(0x2B) -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_IO16(0x2C) -+ -+#define TCNT1L _SFR_IO8(0x2C) -+#define TCNT1H _SFR_IO8(0x2D) -+ -+#define TCCR1B _SFR_IO8(0x2E) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1A _SFR_IO8(0x2F) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1C0 2 -+#define COM1C1 3 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define ASSR _SFR_IO8(0x30) -+#define TCR0UB 0 -+#define OCR0UB 1 -+#define TCN0UB 2 -+#define AS0 3 -+ -+#define OCR0 _SFR_IO8(0x31) -+ -+#define TCNT0 _SFR_IO8(0x32) -+ -+#define TCCR0 _SFR_IO8(0x33) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define WGM01 3 -+#define COM00 4 -+#define COM01 5 -+#define WGM00 6 -+#define FOC0 7 -+ -+#define MCUCSR _SFR_IO8(0x34) -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+#define JTRF 4 -+#define JTD 7 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define IVCE 0 -+#define IVSEL 1 -+#define SM2 2 -+#define SM0 3 -+#define SM1 4 -+#define SE 5 -+#define SRW10 6 -+#define SRE 7 -+ -+#define TIFR _SFR_IO8(0x36) -+#define TOV0 0 -+#define OCF0 1 -+#define TOV1 2 -+#define OCF1B 3 -+#define OCF1A 4 -+#define ICF1 5 -+#define TOV2 6 -+#define OCF2 7 -+ -+#define TIMSK _SFR_IO8(0x37) -+#define TOIE0 0 -+#define OCIE0 1 -+#define TOIE1 2 -+#define OCIE1B 3 -+#define OCIE1A 4 -+#define TICIE1 5 -+#define TOIE2 6 -+#define OCIE2 7 -+ -+#define EIFR _SFR_IO8(0x38) -+#define INTF0 0 -+#define INTF1 1 -+#define INTF2 2 -+#define INTF3 3 -+#define INTF4 4 -+#define INTF5 5 -+#define INTF6 6 -+#define INTF7 7 -+ -+#define EIMSK _SFR_IO8(0x39) -+#define INT0 0 -+#define INT1 1 -+#define INT2 2 -+#define INT3 3 -+#define INT4 4 -+#define INT5 5 -+#define INT6 6 -+#define INT7 7 -+ -+#define EICRB _SFR_IO8(0x3A) -+#define ISC40 0 -+#define ISC41 1 -+#define ISC50 2 -+#define ISC51 3 -+#define ISC60 4 -+#define ISC61 5 -+#define ISC70 6 -+#define ISC71 7 -+ -+#define RAMPZ _SFR_IO8(0x3B) -+#define RAMPZ0 0 -+ -+#define XDIV _SFR_IO8(0x3C) -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+/* Reserved [0x40..0x60] */ -+ -+#define DDRF _SFR_MEM8(0x61) -+#define DDRF7 7 -+#define DDRF6 6 -+#define DDRF5 5 -+#define DDRF4 4 -+#define DDRF3 3 -+#define DDRF2 2 -+#define DDRF1 1 -+#define DDRF0 0 -+ -+#define PORTF _SFR_MEM8(0x62) -+#define PORTF7 7 -+#define PORTF6 6 -+#define PORTF5 5 -+#define PORTF4 4 -+#define PORTF3 3 -+#define PORTF2 2 -+#define PORTF1 1 -+#define PORTF0 0 -+ -+#define PING _SFR_MEM8(0x63) -+#define PING4 4 -+#define PING3 3 -+#define PING2 2 -+#define PING1 1 -+#define PING0 0 -+ -+#define DDRG _SFR_MEM8(0x64) -+#define DDRG4 4 -+#define DDRG3 3 -+#define DDRG2 2 -+#define DDRG1 1 -+#define DDRG0 0 -+ -+#define PORTG _SFR_MEM8(0x65) -+#define PORTG4 4 -+#define PORTG3 3 -+#define PORTG2 2 -+#define PORTG1 1 -+#define PORTG0 0 -+ -+/* Reserved [0x66..0x67] */ -+ -+#define SPMCSR _SFR_MEM8(0x68) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+/* Reserved [0x69] */ -+ -+#define EICRA _SFR_MEM8(0x6A) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+#define ISC20 4 -+#define ISC21 5 -+#define ISC30 6 -+#define ISC31 7 -+ -+/* Reserved [0x6B] */ -+ -+#define XMCRB _SFR_MEM8(0x6C) -+#define XMM0 0 -+#define XMM1 1 -+#define XMM2 2 -+#define XMBK 7 -+ -+#define XMCRA _SFR_MEM8(0x6D) -+#define SRW11 1 -+#define SRW00 2 -+#define SRW01 3 -+#define SRL0 4 -+#define SRL1 5 -+#define SRL2 6 -+ -+/* Reserved [0x6E] */ -+ -+#define OSCCAL _SFR_MEM8(0x6F) -+#define OSCCAL0 0 -+#define OSCCAL1 1 -+#define OSCCAL2 2 -+#define OSCCAL3 3 -+#define OSCCAL4 4 -+#define OSCCAL5 5 -+#define OSCCAL6 6 -+#define OSCCAL7 7 -+ -+#define TWBR _SFR_MEM8(0x70) -+ -+#define TWSR _SFR_MEM8(0x71) -+#define TWPS0 0 -+#define TWPS1 1 -+#define TWS3 3 -+#define TWS4 4 -+#define TWS5 5 -+#define TWS6 6 -+#define TWS7 7 -+ -+#define TWAR _SFR_MEM8(0x72) -+#define TWGCE 0 -+#define TWA0 1 -+#define TWA1 2 -+#define TWA2 3 -+#define TWA3 4 -+#define TWA4 5 -+#define TWA5 6 -+#define TWA6 7 -+ -+#define TWDR _SFR_MEM8(0x73) -+ -+#define TWCR _SFR_MEM8(0x74) -+#define TWIE 0 -+#define TWEN 2 -+#define TWWC 3 -+#define TWSTO 4 -+#define TWSTA 5 -+#define TWEA 6 -+#define TWINT 7 -+ -+/* Reserved [0x75..0x77] */ -+ -+/* Combine OCR1CL and OCR1CH */ -+#define OCR1C _SFR_MEM16(0x78) -+ -+#define OCR1CL _SFR_MEM8(0x78) -+#define OCR1CH _SFR_MEM8(0x79) -+ -+#define TCCR1C _SFR_MEM8(0x7A) -+#define FOC1C 5 -+#define FOC1B 6 -+#define FOC1A 7 -+ -+/* Reserved [0x7B] */ -+ -+#define ETIFR _SFR_MEM8(0x7C) -+#define OCF1C 0 -+#define OCF3C 1 -+#define TOV3 2 -+#define OCF3B 3 -+#define OCF3A 4 -+#define ICF3 5 -+ -+#define ETIMSK _SFR_MEM8(0x7D) -+#define OCIE1C 0 -+#define OCIE3C 1 -+#define TOIE3 2 -+#define OCIE3B 3 -+#define OCIE3A 4 -+#define TICIE3 5 -+ -+/* Reserved [0x7E..0x7F] */ -+ -+/* Combine ICR3L and ICR3H */ -+#define ICR3 _SFR_MEM16(0x80) -+ -+#define ICR3L _SFR_MEM8(0x80) -+#define ICR3H _SFR_MEM8(0x81) -+ -+/* Combine OCR3CL and OCR3CH */ -+#define OCR3C _SFR_MEM16(0x82) -+ -+#define OCR3CL _SFR_MEM8(0x82) -+#define OCR3CH _SFR_MEM8(0x83) -+ -+/* Combine OCR3BL and OCR3BH */ -+#define OCR3B _SFR_MEM16(0x84) -+ -+#define OCR3BL _SFR_MEM8(0x84) -+#define OCR3BH _SFR_MEM8(0x85) -+ -+/* Combine OCR3AL and OCR3AH */ -+#define OCR3A _SFR_MEM16(0x86) -+ -+#define OCR3AL _SFR_MEM8(0x86) -+#define OCR3AH _SFR_MEM8(0x87) -+ -+/* Combine TCNT3L and TCNT3H */ -+#define TCNT3 _SFR_MEM16(0x88) -+ -+#define TCNT3L _SFR_MEM8(0x88) -+#define TCNT3H _SFR_MEM8(0x89) -+ -+#define TCCR3B _SFR_MEM8(0x8A) -+#define CS30 0 -+#define CS31 1 -+#define CS32 2 -+#define WGM32 3 -+#define WGM33 4 -+#define ICES3 6 -+#define ICNC3 7 -+ -+#define TCCR3A _SFR_MEM8(0x8B) -+#define WGM30 0 -+#define WGM31 1 -+#define COM3C0 2 -+#define COM3C1 3 -+#define COM3B0 4 -+#define COM3B1 5 -+#define COM3A0 6 -+#define COM3A1 7 -+ -+#define TCCR3C _SFR_MEM8(0x8C) -+#define FOC3C 5 -+#define FOC3B 6 -+#define FOC3A 7 -+ -+/* Reserved [0x8D..0x8F] */ -+ -+#define UBRR0H _SFR_MEM8(0x90) -+ -+/* Reserved [0x91..0x94] */ -+ -+#define UCSR0C _SFR_MEM8(0x95) -+#define UCPOL0 0 -+#define UCSZ00 1 -+#define UCSZ01 2 -+#define USBS0 3 -+#define UPM00 4 -+#define UPM01 5 -+#define UMSEL0 6 -+ -+/* Reserved [0x96..0x97] */ -+ -+#define UBRR1H _SFR_MEM8(0x98) -+ -+#define UBRR1L _SFR_MEM8(0x99) -+ -+#define UCSR1B _SFR_MEM8(0x9A) -+#define TXB81 0 -+#define RXB81 1 -+#define UCSZ12 2 -+#define TXEN1 3 -+#define RXEN1 4 -+#define UDRIE1 5 -+#define TXCIE1 6 -+#define RXCIE1 7 -+ -+#define UCSR1A _SFR_MEM8(0x9B) -+#define MPCM1 0 -+#define U2X1 1 -+#define UPE1 2 -+#define DOR1 3 -+#define FE1 4 -+#define UDRE1 5 -+#define TXC1 6 -+#define RXC1 7 -+ -+#define UDR1 _SFR_MEM8(0x9C) -+ -+#define UCSR1C _SFR_MEM8(0x9D) -+#define UCPOL1 0 -+#define UCSZ10 1 -+#define UCSZ11 2 -+#define USBS1 3 -+#define UPM10 4 -+#define UPM11 5 -+#define UMSEL1 6 -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* External Interrupt Request 2 */ -+#define INT2_vect _VECTOR(3) -+#define INT2_vect_num 3 -+ -+/* External Interrupt Request 3 */ -+#define INT3_vect _VECTOR(4) -+#define INT3_vect_num 4 -+ -+/* External Interrupt Request 4 */ -+#define INT4_vect _VECTOR(5) -+#define INT4_vect_num 5 -+ -+/* External Interrupt Request 5 */ -+#define INT5_vect _VECTOR(6) -+#define INT5_vect_num 6 -+ -+/* External Interrupt Request 6 */ -+#define INT6_vect _VECTOR(7) -+#define INT6_vect_num 7 -+ -+/* External Interrupt Request 7 */ -+#define INT7_vect _VECTOR(8) -+#define INT7_vect_num 8 -+ -+/* Timer/Counter2 Compare Match */ -+#define TIMER2_COMP_vect _VECTOR(9) -+#define TIMER2_COMP_vect_num 9 -+ -+/* Timer/Counter2 Overflow */ -+#define TIMER2_OVF_vect _VECTOR(10) -+#define TIMER2_OVF_vect_num 10 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(11) -+#define TIMER1_CAPT_vect_num 11 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(12) -+#define TIMER1_COMPA_vect_num 12 -+ -+/* Timer/Counter Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(13) -+#define TIMER1_COMPB_vect_num 13 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(14) -+#define TIMER1_OVF_vect_num 14 -+ -+/* Timer/Counter0 Compare Match */ -+#define TIMER0_COMP_vect _VECTOR(15) -+#define TIMER0_COMP_vect_num 15 -+ -+/* Timer/Counter0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(16) -+#define TIMER0_OVF_vect_num 16 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(17) -+#define SPI_STC_vect_num 17 -+ -+/* USART0, Rx Complete */ -+#define USART0_RX_vect _VECTOR(18) -+#define USART0_RX_vect_num 18 -+ -+/* USART0 Data Register Empty */ -+#define USART0_UDRE_vect _VECTOR(19) -+#define USART0_UDRE_vect_num 19 -+ -+/* USART0, Tx Complete */ -+#define USART0_TX_vect _VECTOR(20) -+#define USART0_TX_vect_num 20 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(21) -+#define ADC_vect_num 21 -+ -+/* EEPROM Ready */ -+#define EE_READY_vect _VECTOR(22) -+#define EE_READY_vect_num 22 -+ -+/* Analog Comparator */ -+#define ANALOG_COMP_vect _VECTOR(23) -+#define ANALOG_COMP_vect_num 23 -+ -+/* Timer/Counter1 Compare Match C */ -+#define TIMER1_COMPC_vect _VECTOR(24) -+#define TIMER1_COMPC_vect_num 24 -+ -+/* Timer/Counter3 Capture Event */ -+#define TIMER3_CAPT_vect _VECTOR(25) -+#define TIMER3_CAPT_vect_num 25 -+ -+/* Timer/Counter3 Compare Match A */ -+#define TIMER3_COMPA_vect _VECTOR(26) -+#define TIMER3_COMPA_vect_num 26 -+ -+/* Timer/Counter3 Compare Match B */ -+#define TIMER3_COMPB_vect _VECTOR(27) -+#define TIMER3_COMPB_vect_num 27 -+ -+/* Timer/Counter3 Compare Match C */ -+#define TIMER3_COMPC_vect _VECTOR(28) -+#define TIMER3_COMPC_vect_num 28 -+ -+/* Timer/Counter3 Overflow */ -+#define TIMER3_OVF_vect _VECTOR(29) -+#define TIMER3_OVF_vect_num 29 -+ -+/* USART1, Rx Complete */ -+#define USART1_RX_vect _VECTOR(30) -+#define USART1_RX_vect_num 30 -+ -+/* USART1, Data Register Empty */ -+#define USART1_UDRE_vect _VECTOR(31) -+#define USART1_UDRE_vect_num 31 -+ -+/* USART1, Tx Complete */ -+#define USART1_TX_vect _VECTOR(32) -+#define USART1_TX_vect_num 32 -+ -+/* 2-wire Serial Interface */ -+#define TWI_vect _VECTOR(33) -+#define TWI_vect_num 33 -+ -+/* Store Program Memory Read */ -+#define SPM_READY_vect _VECTOR(34) -+#define SPM_READY_vect_num 34 -+ -+#define _VECTORS_SIZE 140 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 256 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x1FFFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 4096 -+#define RAMEND 0x10FF -+#define E2START 0 -+#define E2SIZE 4096 -+#define E2PAGESIZE 8 -+#define E2END 0x0FFF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -+#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -+#define FUSE_BODEN (unsigned char)~_BV(6) -+#define FUSE_BODLEVEL (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_CKOPT (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_JTAGEN (unsigned char)~_BV(6) -+#define FUSE_OCDEN (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_WDTON (unsigned char)~_BV(0) -+#define FUSE_M103C (unsigned char)~_BV(1) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x97 -+#define SIGNATURE_2 0x02 -+ -+ -+#endif /* #ifdef _AVR_ATMEGA128A_H_INCLUDED */ -+ -diff --git a/include/avr/iom128rfr2.h b/include/avr/iom128rfr2.h -new file mode 100644 -index 0000000..8a6bfbf ---- /dev/null -+++ b/include/avr/iom128rfr2.h -@@ -0,0 +1,2579 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATMEGA128RFR2_H_INCLUDED -+#define _AVR_ATMEGA128RFR2_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iom128rfr2.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINA _SFR_IO8(0x00) -+#define PINA7 7 -+#define PINA6 6 -+#define PINA5 5 -+#define PINA4 4 -+#define PINA3 3 -+#define PINA2 2 -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x01) -+#define DDRA7 7 -+#define DDRA6 6 -+#define DDRA5 5 -+#define DDRA4 4 -+#define DDRA3 3 -+#define DDRA2 2 -+#define DDRA1 1 -+#define DDRA0 0 -+ -+#define PORTA _SFR_IO8(0x02) -+#define PORTA7 7 -+#define PORTA6 6 -+#define PORTA5 5 -+#define PORTA4 4 -+#define PORTA3 3 -+#define PORTA2 2 -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x06) -+#define PINC7 7 -+#define PINC6 6 -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x07) -+#define DDRC7 7 -+#define DDRC6 6 -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x08) -+#define PORTC7 7 -+#define PORTC6 6 -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PIND _SFR_IO8(0x09) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0A) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x0B) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+#define PINE _SFR_IO8(0x0C) -+#define PINE7 7 -+#define PINE6 6 -+#define PINE5 5 -+#define PINE4 4 -+#define PINE3 3 -+#define PINE2 2 -+#define PINE1 1 -+#define PINE0 0 -+ -+#define DDRE _SFR_IO8(0x0D) -+#define DDRE7 7 -+#define DDRE6 6 -+#define DDRE5 5 -+#define DDRE4 4 -+#define DDRE3 3 -+#define DDRE2 2 -+#define DDRE1 1 -+#define DDRE0 0 -+ -+#define PORTE _SFR_IO8(0x0E) -+#define PORTE7 7 -+#define PORTE6 6 -+#define PORTE5 5 -+#define PORTE4 4 -+#define PORTE3 3 -+#define PORTE2 2 -+#define PORTE1 1 -+#define PORTE0 0 -+ -+#define PINF _SFR_IO8(0x0F) -+#define PINF7 7 -+#define PINF6 6 -+#define PINF5 5 -+#define PINF4 4 -+#define PINF3 3 -+#define PINF2 2 -+#define PINF1 1 -+#define PINF0 0 -+ -+#define DDRF _SFR_IO8(0x10) -+#define DDRF7 7 -+#define DDRF6 6 -+#define DDRF5 5 -+#define DDRF4 4 -+#define DDRF3 3 -+#define DDRF2 2 -+#define DDRF1 1 -+#define DDRF0 0 -+ -+#define PORTF _SFR_IO8(0x11) -+#define PORTF7 7 -+#define PORTF6 6 -+#define PORTF5 5 -+#define PORTF4 4 -+#define PORTF3 3 -+#define PORTF2 2 -+#define PORTF1 1 -+#define PORTF0 0 -+ -+#define PING _SFR_IO8(0x12) -+#define PING7 7 -+#define PING6 6 -+#define PING5 5 -+#define PING4 4 -+#define PING3 3 -+#define PING2 2 -+#define PING1 1 -+#define PING0 0 -+ -+#define DDRG _SFR_IO8(0x13) -+#define DDRG7 7 -+#define DDRG6 6 -+#define DDRG5 5 -+#define DDRG4 4 -+#define DDRG3 3 -+#define DDRG2 2 -+#define DDRG1 1 -+#define DDRG0 0 -+ -+#define PORTG _SFR_IO8(0x14) -+#define PORTG7 7 -+#define PORTG6 6 -+#define PORTG5 5 -+#define PORTG4 4 -+#define PORTG3 3 -+#define PORTG2 2 -+#define PORTG1 1 -+#define PORTG0 0 -+ -+#define TIFR0 _SFR_IO8(0x15) -+#define TOV0 0 -+#define OCF0A 1 -+#define OCF0B 2 -+#define Res0 3 -+#define Res1 4 -+#define Res2 5 -+#define Res3 6 -+#define Res4 7 -+ -+#define TIFR1 _SFR_IO8(0x16) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define OCF1C 3 -+#define ICF1 5 -+ -+#define TIFR2 _SFR_IO8(0x17) -+#define TOV2 0 -+#define OCF2A 1 -+#define OCF2B 2 -+ -+#define TIFR3 _SFR_IO8(0x18) -+#define TOV3 0 -+#define OCF3A 1 -+#define OCF3B 2 -+#define OCF3C 3 -+#define ICF3 5 -+ -+#define TIFR4 _SFR_IO8(0x19) -+#define TOV4 0 -+#define OCF4A 1 -+#define OCF4B 2 -+#define OCF4C 3 -+#define ICF4 5 -+ -+#define TIFR5 _SFR_IO8(0x1A) -+#define TOV5 0 -+#define OCF5A 1 -+#define OCF5B 2 -+#define OCF5C 3 -+#define ICF5 5 -+ -+#define PCIFR _SFR_IO8(0x1B) -+#define PCIF0 0 -+#define PCIF1 1 -+#define PCIF2 2 -+ -+#define EIFR _SFR_IO8(0x1C) -+#define INTF0 0 -+#define INTF1 1 -+#define INTF2 2 -+#define INTF3 3 -+#define INTF4 4 -+#define INTF5 5 -+#define INTF6 6 -+#define INTF7 7 -+ -+#define EIMSK _SFR_IO8(0x1D) -+#define INT0 0 -+#define INT1 1 -+#define INT2 2 -+#define INT3 3 -+#define INT4 4 -+#define INT5 5 -+#define INT6 6 -+#define INT7 7 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+#define GPIOR00 0 -+#define GPIOR01 1 -+#define GPIOR02 2 -+#define GPIOR03 3 -+#define GPIOR04 4 -+#define GPIOR05 5 -+#define GPIOR06 6 -+#define GPIOR07 7 -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEPE 1 -+#define EEMPE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSRSYNC 0 -+#define PSRASY 1 -+#define TSM 7 -+ -+#define TCCR0A _SFR_IO8(0x24) -+#define WGM00 0 -+#define WGM01 1 -+#define COM0B0 4 -+#define COM0B1 5 -+#define COM0A0 6 -+#define COM0A1 7 -+ -+#define TCCR0B _SFR_IO8(0x25) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define WGM02 3 -+#define FOC0B 6 -+#define FOC0A 7 -+ -+#define TCNT0 _SFR_IO8(0x26) -+ -+#define OCR0A _SFR_IO8(0x27) -+ -+#define OCR0B _SFR_IO8(0x28) -+ -+/* Reserved [0x29] */ -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+#define GPIOR10 0 -+#define GPIOR11 1 -+#define GPIOR12 2 -+#define GPIOR13 3 -+#define GPIOR14 4 -+#define GPIOR15 5 -+#define GPIOR16 6 -+#define GPIOR17 7 -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+#define GPIOR20 0 -+#define GPIOR21 1 -+#define GPIOR22 2 -+#define GPIOR23 3 -+#define GPIOR24 4 -+#define GPIOR25 5 -+#define GPIOR26 6 -+#define GPIOR27 7 -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+/* Reserved [0x2F] */ -+ -+#define ACSR _SFR_IO8(0x30) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACBG 6 -+#define ACD 7 -+ -+#define OCDR _SFR_IO8(0x31) -+#define OCDR0 0 -+#define OCDR1 1 -+#define OCDR2 2 -+#define OCDR3 3 -+#define OCDR4 4 -+#define OCDR5 5 -+#define OCDR6 6 -+#define OCDR7 7 -+ -+/* Reserved [0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define JTRF 4 -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define JTD 7 -+#define IVCE 0 -+#define IVSEL 1 -+#define PUD 4 -+ -+/* Reserved [0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define SIGRD 5 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+/* Reserved [0x38..0x3A] */ -+ -+#define RAMPZ _SFR_IO8(0x3B) -+#define RAMPZ0 0 -+#define Res5 6 -+#define Res6 7 -+ -+/* Reserved [0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCSR _SFR_MEM8(0x60) -+#define WDE 3 -+#define WDCE 4 -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDP3 5 -+#define WDIE 6 -+#define WDIF 7 -+ -+#define CLKPR _SFR_MEM8(0x61) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+#define CLKPCE 7 -+ -+/* Reserved [0x62] */ -+ -+#define PRR2 _SFR_MEM8(0x63) -+#define PRRAM0 0 -+#define PRRAM1 1 -+#define PRRAM2 2 -+#define PRRAM3 3 -+ -+#define PRR0 _SFR_MEM8(0x64) -+#define PRADC 0 -+#define PRUSART0 1 -+#define PRSPI 2 -+#define PRTIM1 3 -+#define PRPGA 4 -+#define PRTIM0 5 -+#define PRTIM2 6 -+#define PRTWI 7 -+ -+#define PRR1 _SFR_MEM8(0x65) -+#define PRUSART1 0 -+#define PRTIM3 3 -+#define PRTIM4 4 -+#define PRTIM5 5 -+#define PRTRX24 6 -+#define Res 7 -+ -+#define OSCCAL _SFR_MEM8(0x66) -+#define CAL0 0 -+#define CAL1 1 -+#define CAL2 2 -+#define CAL3 3 -+#define CAL4 4 -+#define CAL5 5 -+#define CAL6 6 -+#define CAL7 7 -+#define OSCCAL0 0 -+#define OSCCAL1 1 -+#define OSCCAL2 2 -+#define OSCCAL3 3 -+#define OSCCAL4 4 -+#define OSCCAL5 5 -+#define OSCCAL6 6 -+#define OSCCAL7 7 -+ -+#define BGCR _SFR_MEM8(0x67) -+#define BGCAL0 0 -+#define BGCAL1 1 -+#define BGCAL2 2 -+#define BGCAL_FINE0 3 -+#define BGCAL_FINE1 4 -+#define BGCAL_FINE2 5 -+#define BGCAL_FINE3 6 -+ -+#define PCICR _SFR_MEM8(0x68) -+#define PCIE0 0 -+#define PCIE1 1 -+#define PCIE2 2 -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+#define ISC20 4 -+#define ISC21 5 -+#define ISC30 6 -+#define ISC31 7 -+ -+#define EICRB _SFR_MEM8(0x6A) -+#define ISC40 0 -+#define ISC41 1 -+#define ISC50 2 -+#define ISC51 3 -+#define ISC60 4 -+#define ISC61 5 -+#define ISC70 6 -+#define ISC71 7 -+ -+#define PCMSK0 _SFR_MEM8(0x6B) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6C) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+#define PCINT14 6 -+#define PCINT15 7 -+ -+#define PCMSK2 _SFR_MEM8(0x6D) -+#define PCINT16 0 -+#define PCINT17 1 -+#define PCINT18 2 -+#define PCINT19 3 -+#define PCINT20 4 -+#define PCINT21 5 -+#define PCINT22 6 -+#define PCINT23 7 -+ -+#define TIMSK0 _SFR_MEM8(0x6E) -+#define TOIE0 0 -+#define OCIE0A 1 -+#define OCIE0B 2 -+ -+#define TIMSK1 _SFR_MEM8(0x6F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define OCIE1C 3 -+#define ICIE1 5 -+ -+#define TIMSK2 _SFR_MEM8(0x70) -+#define TOIE2 0 -+#define OCIE2A 1 -+#define OCIE2B 2 -+ -+#define TIMSK3 _SFR_MEM8(0x71) -+#define TOIE3 0 -+#define OCIE3A 1 -+#define OCIE3B 2 -+#define OCIE3C 3 -+#define ICIE3 5 -+ -+#define TIMSK4 _SFR_MEM8(0x72) -+#define TOIE4 0 -+#define OCIE4A 1 -+#define OCIE4B 2 -+#define OCIE4C 3 -+#define ICIE4 5 -+ -+#define TIMSK5 _SFR_MEM8(0x73) -+#define TOIE5 0 -+#define OCIE5A 1 -+#define OCIE5B 2 -+#define OCIE5C 3 -+#define ICIE5 5 -+ -+/* Reserved [0x74] */ -+ -+#define NEMCR _SFR_MEM8(0x75) -+#define AEAM0 4 -+#define AEAM1 5 -+#define ENEAM 6 -+ -+/* Reserved [0x76] */ -+ -+#define ADCSRC _SFR_MEM8(0x77) -+#define ADSUT0 0 -+#define ADSUT1 1 -+#define ADSUT2 2 -+#define ADSUT3 3 -+#define ADSUT4 4 -+#define ADTHT0 6 -+#define ADTHT1 7 -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_MEM16(0x78) -+#endif -+#define ADCW _SFR_MEM16(0x78) -+ -+#define ADCL _SFR_MEM8(0x78) -+#define ADCH _SFR_MEM8(0x79) -+ -+#define ADCSRA _SFR_MEM8(0x7A) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADCSRB _SFR_MEM8(0x7B) -+#define ACME 6 -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+#define MUX5 3 -+#define ACCH 4 -+#define REFOK 5 -+#define AVDDOK 7 -+ -+#define ADMUX _SFR_MEM8(0x7C) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define MUX4 4 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+#define DIDR2 _SFR_MEM8(0x7D) -+#define ADC8D 0 -+#define ADC9D 1 -+#define ADC10D 2 -+#define ADC11D 3 -+#define ADC12D 4 -+#define ADC13D 5 -+#define ADC14D 6 -+#define ADC15D 7 -+ -+#define DIDR0 _SFR_MEM8(0x7E) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+#define ADC6D 6 -+#define ADC7D 7 -+ -+#define DIDR1 _SFR_MEM8(0x7F) -+#define AIN0D 0 -+#define AIN1D 1 -+ -+#define TCCR1A _SFR_MEM8(0x80) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1C0 2 -+#define COM1C1 3 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR1B _SFR_MEM8(0x81) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1C _SFR_MEM8(0x82) -+#define FOC1C 5 -+#define FOC1B 6 -+#define FOC1A 7 -+ -+/* Reserved [0x83] */ -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x84) -+ -+#define TCNT1L _SFR_MEM8(0x84) -+#define TCNT1H _SFR_MEM8(0x85) -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x86) -+ -+#define ICR1L _SFR_MEM8(0x86) -+#define ICR1H _SFR_MEM8(0x87) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_MEM16(0x88) -+ -+#define OCR1AL _SFR_MEM8(0x88) -+#define OCR1AH _SFR_MEM8(0x89) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_MEM16(0x8A) -+ -+#define OCR1BL _SFR_MEM8(0x8A) -+#define OCR1BH _SFR_MEM8(0x8B) -+ -+/* Combine OCR1CL and OCR1CH */ -+#define OCR1C _SFR_MEM16(0x8C) -+ -+#define OCR1CL _SFR_MEM8(0x8C) -+#define OCR1CH _SFR_MEM8(0x8D) -+ -+/* Reserved [0x8E..0x8F] */ -+ -+#define TCCR3A _SFR_MEM8(0x90) -+#define WGM30 0 -+#define WGM31 1 -+#define COM3C0 2 -+#define COM3C1 3 -+#define COM3B0 4 -+#define COM3B1 5 -+#define COM3A0 6 -+#define COM3A1 7 -+ -+#define TCCR3B _SFR_MEM8(0x91) -+#define CS30 0 -+#define CS31 1 -+#define CS32 2 -+#define WGM32 3 -+#define WGM33 4 -+#define ICES3 6 -+#define ICNC3 7 -+ -+#define TCCR3C _SFR_MEM8(0x92) -+#define FOC3C 5 -+#define FOC3B 6 -+#define FOC3A 7 -+ -+/* Reserved [0x93] */ -+ -+/* Combine TCNT3L and TCNT3H */ -+#define TCNT3 _SFR_MEM16(0x94) -+ -+#define TCNT3L _SFR_MEM8(0x94) -+#define TCNT3H _SFR_MEM8(0x95) -+ -+/* Combine ICR3L and ICR3H */ -+#define ICR3 _SFR_MEM16(0x96) -+ -+#define ICR3L _SFR_MEM8(0x96) -+#define ICR3H _SFR_MEM8(0x97) -+ -+/* Combine OCR3AL and OCR3AH */ -+#define OCR3A _SFR_MEM16(0x98) -+ -+#define OCR3AL _SFR_MEM8(0x98) -+#define OCR3AH _SFR_MEM8(0x99) -+ -+/* Combine OCR3BL and OCR3BH */ -+#define OCR3B _SFR_MEM16(0x9A) -+ -+#define OCR3BL _SFR_MEM8(0x9A) -+#define OCR3BH _SFR_MEM8(0x9B) -+ -+/* Combine OCR3CL and OCR3CH */ -+#define OCR3C _SFR_MEM16(0x9C) -+ -+#define OCR3CL _SFR_MEM8(0x9C) -+#define OCR3CH _SFR_MEM8(0x9D) -+ -+/* Reserved [0x9E..0x9F] */ -+ -+#define TCCR4A _SFR_MEM8(0xA0) -+#define WGM40 0 -+#define WGM41 1 -+#define COM4C0 2 -+#define COM4C1 3 -+#define COM4B0 4 -+#define COM4B1 5 -+#define COM4A0 6 -+#define COM4A1 7 -+ -+#define TCCR4B _SFR_MEM8(0xA1) -+#define CS40 0 -+#define CS41 1 -+#define CS42 2 -+#define WGM42 3 -+#define WGM43 4 -+#define ICES4 6 -+#define ICNC4 7 -+ -+#define TCCR4C _SFR_MEM8(0xA2) -+#define FOC4C 5 -+#define FOC4B 6 -+#define FOC4A 7 -+ -+/* Reserved [0xA3] */ -+ -+/* Combine TCNT4L and TCNT4H */ -+#define TCNT4 _SFR_MEM16(0xA4) -+ -+#define TCNT4L _SFR_MEM8(0xA4) -+#define TCNT4H _SFR_MEM8(0xA5) -+ -+/* Combine ICR4L and ICR4H */ -+#define ICR4 _SFR_MEM16(0xA6) -+ -+#define ICR4L _SFR_MEM8(0xA6) -+#define ICR4H _SFR_MEM8(0xA7) -+ -+/* Combine OCR4AL and OCR4AH */ -+#define OCR4A _SFR_MEM16(0xA8) -+ -+#define OCR4AL _SFR_MEM8(0xA8) -+#define OCR4AH _SFR_MEM8(0xA9) -+ -+/* Combine OCR4BL and OCR4BH */ -+#define OCR4B _SFR_MEM16(0xAA) -+ -+#define OCR4BL _SFR_MEM8(0xAA) -+#define OCR4BH _SFR_MEM8(0xAB) -+ -+/* Combine OCR4CL and OCR4CH */ -+#define OCR4C _SFR_MEM16(0xAC) -+ -+#define OCR4CL _SFR_MEM8(0xAC) -+#define OCR4CH _SFR_MEM8(0xAD) -+ -+/* Reserved [0xAE..0xAF] */ -+ -+#define TCCR2A _SFR_MEM8(0xB0) -+#define WGM20 0 -+#define WGM21 1 -+#define COM2B0 4 -+#define COM2B1 5 -+#define COM2A0 6 -+#define COM2A1 7 -+ -+#define TCCR2B _SFR_MEM8(0xB1) -+#define CS20 0 -+#define CS21 1 -+#define CS22 2 -+#define WGM22 3 -+#define FOC2B 6 -+#define FOC2A 7 -+ -+#define TCNT2 _SFR_MEM8(0xB2) -+ -+#define OCR2A _SFR_MEM8(0xB3) -+ -+#define OCR2B _SFR_MEM8(0xB4) -+ -+/* Reserved [0xB5] */ -+ -+#define ASSR _SFR_MEM8(0xB6) -+#define TCR2BUB 0 -+#define TCR2AUB 1 -+#define OCR2BUB 2 -+#define OCR2AUB 3 -+#define TCN2UB 4 -+#define AS2 5 -+#define EXCLK 6 -+#define EXCLKAMR 7 -+ -+/* Reserved [0xB7] */ -+ -+#define TWBR _SFR_MEM8(0xB8) -+ -+#define TWSR _SFR_MEM8(0xB9) -+#define TWPS0 0 -+#define TWPS1 1 -+#define TWS3 3 -+#define TWS4 4 -+#define TWS5 5 -+#define TWS6 6 -+#define TWS7 7 -+ -+#define TWAR _SFR_MEM8(0xBA) -+#define TWGCE 0 -+#define TWA0 1 -+#define TWA1 2 -+#define TWA2 3 -+#define TWA3 4 -+#define TWA4 5 -+#define TWA5 6 -+#define TWA6 7 -+ -+#define TWDR _SFR_MEM8(0xBB) -+ -+#define TWCR _SFR_MEM8(0xBC) -+#define TWIE 0 -+#define TWEN 2 -+#define TWWC 3 -+#define TWSTO 4 -+#define TWSTA 5 -+#define TWEA 6 -+#define TWINT 7 -+ -+#define TWAMR _SFR_MEM8(0xBD) -+#define TWAM0 1 -+#define TWAM1 2 -+#define TWAM2 3 -+#define TWAM3 4 -+#define TWAM4 5 -+#define TWAM5 6 -+#define TWAM6 7 -+ -+#define IRQ_MASK1 _SFR_MEM8(0xBE) -+#define TX_START_EN 0 -+#define MAF_0_AMI_EN 1 -+#define MAF_1_AMI_EN 2 -+#define MAF_2_AMI_EN 3 -+#define MAF_3_AMI_EN 4 -+ -+#define IRQ_STATUS1 _SFR_MEM8(0xBF) -+#define TX_START 0 -+#define MAF_0_AMI 1 -+#define MAF_1_AMI 2 -+#define MAF_2_AMI 3 -+#define MAF_3_AMI 4 -+ -+#define UCSR0A _SFR_MEM8(0xC0) -+#define MPCM0 0 -+#define U2X0 1 -+#define UPE0 2 -+#define DOR0 3 -+#define FE0 4 -+#define UDRE0 5 -+#define TXC0 6 -+#define RXC0 7 -+ -+#define UCSR0B _SFR_MEM8(0xC1) -+#define TXB80 0 -+#define RXB80 1 -+#define UCSZ02 2 -+#define TXEN0 3 -+#define RXEN0 4 -+#define UDRIE0 5 -+#define TXCIE0 6 -+#define RXCIE0 7 -+ -+#define UCSR0C _SFR_MEM8(0xC2) -+#define UCPOL0 0 -+#define UCSZ00 1 -+#define UCSZ01 2 -+#define USBS0 3 -+#define UPM00 4 -+#define UPM01 5 -+#define UMSEL00 6 -+#define UMSEL01 7 -+#define UCPHA0 1 -+#define UDORD0 2 -+ -+/* Reserved [0xC3] */ -+ -+/* Combine UBRR0L and UBRR0H */ -+#define UBRR0 _SFR_MEM16(0xC4) -+ -+#define UBRR0L _SFR_MEM8(0xC4) -+#define UBRR0H _SFR_MEM8(0xC5) -+ -+#define UDR0 _SFR_MEM8(0xC6) -+ -+/* Reserved [0xC7] */ -+ -+#define UCSR1A _SFR_MEM8(0xC8) -+#define MPCM1 0 -+#define U2X1 1 -+#define UPE1 2 -+#define DOR1 3 -+#define FE1 4 -+#define UDRE1 5 -+#define TXC1 6 -+#define RXC1 7 -+ -+#define UCSR1B _SFR_MEM8(0xC9) -+#define TXB81 0 -+#define RXB81 1 -+#define UCSZ12 2 -+#define TXEN1 3 -+#define RXEN1 4 -+#define UDRIE1 5 -+#define TXCIE1 6 -+#define RXCIE1 7 -+ -+#define UCSR1C _SFR_MEM8(0xCA) -+#define UCPOL1 0 -+#define UCSZ10 1 -+#define UCSZ11 2 -+#define USBS1 3 -+#define UPM10 4 -+#define UPM11 5 -+#define UMSEL10 6 -+#define UMSEL11 7 -+#define UCPHA1 1 -+#define UDORD1 2 -+ -+/* Reserved [0xCB] */ -+ -+/* Combine UBRR1L and UBRR1H */ -+#define UBRR1 _SFR_MEM16(0xCC) -+ -+#define UBRR1L _SFR_MEM8(0xCC) -+#define UBRR1H _SFR_MEM8(0xCD) -+ -+#define UDR1 _SFR_MEM8(0xCE) -+ -+/* Reserved [0xCF..0xD6] */ -+ -+#define SCRSTRLL _SFR_MEM8(0xD7) -+#define SCRSTRLL0 0 -+#define SCRSTRLL1 1 -+#define SCRSTRLL2 2 -+#define SCRSTRLL3 3 -+#define SCRSTRLL4 4 -+#define SCRSTRLL5 5 -+#define SCRSTRLL6 6 -+#define SCRSTRLL7 7 -+ -+#define SCRSTRLH _SFR_MEM8(0xD8) -+#define SCRSTRLH0 0 -+#define SCRSTRLH1 1 -+#define SCRSTRLH2 2 -+#define SCRSTRLH3 3 -+#define SCRSTRLH4 4 -+#define SCRSTRLH5 5 -+#define SCRSTRLH6 6 -+#define SCRSTRLH7 7 -+ -+#define SCRSTRHL _SFR_MEM8(0xD9) -+#define SCRSTRHL0 0 -+#define SCRSTRHL1 1 -+#define SCRSTRHL2 2 -+#define SCRSTRHL3 3 -+#define SCRSTRHL4 4 -+#define SCRSTRHL5 5 -+#define SCRSTRHL6 6 -+#define SCRSTRHL7 7 -+ -+#define SCRSTRHH _SFR_MEM8(0xDA) -+#define SCRSTRHH0 0 -+#define SCRSTRHH1 1 -+#define SCRSTRHH2 2 -+#define SCRSTRHH3 3 -+#define SCRSTRHH4 4 -+#define SCRSTRHH5 5 -+#define SCRSTRHH6 6 -+#define SCRSTRHH7 7 -+ -+#define SCCSR _SFR_MEM8(0xDB) -+#define SCCS10 0 -+#define SCCS11 1 -+#define SCCS20 2 -+#define SCCS21 3 -+#define SCCS30 4 -+#define SCCS31 5 -+ -+#define SCCR0 _SFR_MEM8(0xDC) -+#define SCCMP1 0 -+#define SCCMP2 1 -+#define SCCMP3 2 -+#define SCTSE 3 -+#define SCCKSEL 4 -+#define SCEN 5 -+#define SCMBTS 6 -+#define SCRES 7 -+ -+#define SCCR1 _SFR_MEM8(0xDD) -+#define SCENBO 0 -+#define SCEECLK 1 -+#define SCCKDIV0 2 -+#define SCCKDIV1 3 -+#define SCCKDIV2 4 -+#define SCBTSM 5 -+ -+#define SCSR _SFR_MEM8(0xDE) -+#define SCBSY 0 -+ -+#define SCIRQM _SFR_MEM8(0xDF) -+#define IRQMCP1 0 -+#define IRQMCP2 1 -+#define IRQMCP3 2 -+#define IRQMOF 3 -+#define IRQMBO 4 -+ -+#define SCIRQS _SFR_MEM8(0xE0) -+#define IRQSCP1 0 -+#define IRQSCP2 1 -+#define IRQSCP3 2 -+#define IRQSOF 3 -+#define IRQSBO 4 -+ -+#define SCCNTLL _SFR_MEM8(0xE1) -+#define SCCNTLL0 0 -+#define SCCNTLL1 1 -+#define SCCNTLL2 2 -+#define SCCNTLL3 3 -+#define SCCNTLL4 4 -+#define SCCNTLL5 5 -+#define SCCNTLL6 6 -+#define SCCNTLL7 7 -+ -+#define SCCNTLH _SFR_MEM8(0xE2) -+#define SCCNTLH0 0 -+#define SCCNTLH1 1 -+#define SCCNTLH2 2 -+#define SCCNTLH3 3 -+#define SCCNTLH4 4 -+#define SCCNTLH5 5 -+#define SCCNTLH6 6 -+#define SCCNTLH7 7 -+ -+#define SCCNTHL _SFR_MEM8(0xE3) -+#define SCCNTHL0 0 -+#define SCCNTHL1 1 -+#define SCCNTHL2 2 -+#define SCCNTHL3 3 -+#define SCCNTHL4 4 -+#define SCCNTHL5 5 -+#define SCCNTHL6 6 -+#define SCCNTHL7 7 -+ -+#define SCCNTHH _SFR_MEM8(0xE4) -+#define SCCNTHH0 0 -+#define SCCNTHH1 1 -+#define SCCNTHH2 2 -+#define SCCNTHH3 3 -+#define SCCNTHH4 4 -+#define SCCNTHH5 5 -+#define SCCNTHH6 6 -+#define SCCNTHH7 7 -+ -+#define SCBTSRLL _SFR_MEM8(0xE5) -+#define SCBTSRLL0 0 -+#define SCBTSRLL1 1 -+#define SCBTSRLL2 2 -+#define SCBTSRLL3 3 -+#define SCBTSRLL4 4 -+#define SCBTSRLL5 5 -+#define SCBTSRLL6 6 -+#define SCBTSRLL7 7 -+ -+#define SCBTSRLH _SFR_MEM8(0xE6) -+#define SCBTSRLH0 0 -+#define SCBTSRLH1 1 -+#define SCBTSRLH2 2 -+#define SCBTSRLH3 3 -+#define SCBTSRLH4 4 -+#define SCBTSRLH5 5 -+#define SCBTSRLH6 6 -+#define SCBTSRLH7 7 -+ -+#define SCBTSRHL _SFR_MEM8(0xE7) -+#define SCBTSRHL0 0 -+#define SCBTSRHL1 1 -+#define SCBTSRHL2 2 -+#define SCBTSRHL3 3 -+#define SCBTSRHL4 4 -+#define SCBTSRHL5 5 -+#define SCBTSRHL6 6 -+#define SCBTSRHL7 7 -+ -+#define SCBTSRHH _SFR_MEM8(0xE8) -+#define SCBTSRHH0 0 -+#define SCBTSRHH1 1 -+#define SCBTSRHH2 2 -+#define SCBTSRHH3 3 -+#define SCBTSRHH4 4 -+#define SCBTSRHH5 5 -+#define SCBTSRHH6 6 -+#define SCBTSRHH7 7 -+ -+#define SCTSRLL _SFR_MEM8(0xE9) -+#define SCTSRLL0 0 -+#define SCTSRLL1 1 -+#define SCTSRLL2 2 -+#define SCTSRLL3 3 -+#define SCTSRLL4 4 -+#define SCTSRLL5 5 -+#define SCTSRLL6 6 -+#define SCTSRLL7 7 -+ -+#define SCTSRLH _SFR_MEM8(0xEA) -+#define SCTSRLH0 0 -+#define SCTSRLH1 1 -+#define SCTSRLH2 2 -+#define SCTSRLH3 3 -+#define SCTSRLH4 4 -+#define SCTSRLH5 5 -+#define SCTSRLH6 6 -+#define SCTSRLH7 7 -+ -+#define SCTSRHL _SFR_MEM8(0xEB) -+#define SCTSRHL0 0 -+#define SCTSRHL1 1 -+#define SCTSRHL2 2 -+#define SCTSRHL3 3 -+#define SCTSRHL4 4 -+#define SCTSRHL5 5 -+#define SCTSRHL6 6 -+#define SCTSRHL7 7 -+ -+#define SCTSRHH _SFR_MEM8(0xEC) -+#define SCTSRHH0 0 -+#define SCTSRHH1 1 -+#define SCTSRHH2 2 -+#define SCTSRHH3 3 -+#define SCTSRHH4 4 -+#define SCTSRHH5 5 -+#define SCTSRHH6 6 -+#define SCTSRHH7 7 -+ -+#define SCOCR3LL _SFR_MEM8(0xED) -+#define SCOCR3LL0 0 -+#define SCOCR3LL1 1 -+#define SCOCR3LL2 2 -+#define SCOCR3LL3 3 -+#define SCOCR3LL4 4 -+#define SCOCR3LL5 5 -+#define SCOCR3LL6 6 -+#define SCOCR3LL7 7 -+ -+#define SCOCR3LH _SFR_MEM8(0xEE) -+#define SCOCR3LH0 0 -+#define SCOCR3LH1 1 -+#define SCOCR3LH2 2 -+#define SCOCR3LH3 3 -+#define SCOCR3LH4 4 -+#define SCOCR3LH5 5 -+#define SCOCR3LH6 6 -+#define SCOCR3LH7 7 -+ -+#define SCOCR3HL _SFR_MEM8(0xEF) -+#define SCOCR3HL0 0 -+#define SCOCR3HL1 1 -+#define SCOCR3HL2 2 -+#define SCOCR3HL3 3 -+#define SCOCR3HL4 4 -+#define SCOCR3HL5 5 -+#define SCOCR3HL6 6 -+#define SCOCR3HL7 7 -+ -+#define SCOCR3HH _SFR_MEM8(0xF0) -+#define SCOCR3HH0 0 -+#define SCOCR3HH1 1 -+#define SCOCR3HH2 2 -+#define SCOCR3HH3 3 -+#define SCOCR3HH4 4 -+#define SCOCR3HH5 5 -+#define SCOCR3HH6 6 -+#define SCOCR3HH7 7 -+ -+#define SCOCR2LL _SFR_MEM8(0xF1) -+#define SCOCR2LL0 0 -+#define SCOCR2LL1 1 -+#define SCOCR2LL2 2 -+#define SCOCR2LL3 3 -+#define SCOCR2LL4 4 -+#define SCOCR2LL5 5 -+#define SCOCR2LL6 6 -+#define SCOCR2LL7 7 -+ -+#define SCOCR2LH _SFR_MEM8(0xF2) -+#define SCOCR2LH0 0 -+#define SCOCR2LH1 1 -+#define SCOCR2LH2 2 -+#define SCOCR2LH3 3 -+#define SCOCR2LH4 4 -+#define SCOCR2LH5 5 -+#define SCOCR2LH6 6 -+#define SCOCR2LH7 7 -+ -+#define SCOCR2HL _SFR_MEM8(0xF3) -+#define SCOCR2HL0 0 -+#define SCOCR2HL1 1 -+#define SCOCR2HL2 2 -+#define SCOCR2HL3 3 -+#define SCOCR2HL4 4 -+#define SCOCR2HL5 5 -+#define SCOCR2HL6 6 -+#define SCOCR2HL7 7 -+ -+#define SCOCR2HH _SFR_MEM8(0xF4) -+#define SCOCR2HH0 0 -+#define SCOCR2HH1 1 -+#define SCOCR2HH2 2 -+#define SCOCR2HH3 3 -+#define SCOCR2HH4 4 -+#define SCOCR2HH5 5 -+#define SCOCR2HH6 6 -+#define SCOCR2HH7 7 -+ -+#define SCOCR1LL _SFR_MEM8(0xF5) -+#define SCOCR1LL0 0 -+#define SCOCR1LL1 1 -+#define SCOCR1LL2 2 -+#define SCOCR1LL3 3 -+#define SCOCR1LL4 4 -+#define SCOCR1LL5 5 -+#define SCOCR1LL6 6 -+#define SCOCR1LL7 7 -+ -+#define SCOCR1LH _SFR_MEM8(0xF6) -+#define SCOCR1LH0 0 -+#define SCOCR1LH1 1 -+#define SCOCR1LH2 2 -+#define SCOCR1LH3 3 -+#define SCOCR1LH4 4 -+#define SCOCR1LH5 5 -+#define SCOCR1LH6 6 -+#define SCOCR1LH7 7 -+ -+#define SCOCR1HL _SFR_MEM8(0xF7) -+#define SCOCR1HL0 0 -+#define SCOCR1HL1 1 -+#define SCOCR1HL2 2 -+#define SCOCR1HL3 3 -+#define SCOCR1HL4 4 -+#define SCOCR1HL5 5 -+#define SCOCR1HL6 6 -+#define SCOCR1HL7 7 -+ -+#define SCOCR1HH _SFR_MEM8(0xF8) -+#define SCOCR1HH0 0 -+#define SCOCR1HH1 1 -+#define SCOCR1HH2 2 -+#define SCOCR1HH3 3 -+#define SCOCR1HH4 4 -+#define SCOCR1HH5 5 -+#define SCOCR1HH6 6 -+#define SCOCR1HH7 7 -+ -+#define SCTSTRLL _SFR_MEM8(0xF9) -+#define SCTSTRLL0 0 -+#define SCTSTRLL1 1 -+#define SCTSTRLL2 2 -+#define SCTSTRLL3 3 -+#define SCTSTRLL4 4 -+#define SCTSTRLL5 5 -+#define SCTSTRLL6 6 -+#define SCTSTRLL7 7 -+ -+#define SCTSTRLH _SFR_MEM8(0xFA) -+#define SCTSTRLH0 0 -+#define SCTSTRLH1 1 -+#define SCTSTRLH2 2 -+#define SCTSTRLH3 3 -+#define SCTSTRLH4 4 -+#define SCTSTRLH5 5 -+#define SCTSTRLH6 6 -+#define SCTSTRLH7 7 -+ -+#define SCTSTRHL _SFR_MEM8(0xFB) -+#define SCTSTRHL0 0 -+#define SCTSTRHL1 1 -+#define SCTSTRHL2 2 -+#define SCTSTRHL3 3 -+#define SCTSTRHL4 4 -+#define SCTSTRHL5 5 -+#define SCTSTRHL6 6 -+#define SCTSTRHL7 7 -+ -+#define SCTSTRHH _SFR_MEM8(0xFC) -+#define SCTSTRHH0 0 -+#define SCTSTRHH1 1 -+#define SCTSTRHH2 2 -+#define SCTSTRHH3 3 -+#define SCTSTRHH4 4 -+#define SCTSTRHH5 5 -+#define SCTSTRHH6 6 -+#define SCTSTRHH7 7 -+ -+/* Reserved [0xFD..0x10B] */ -+ -+#define MAFCR0 _SFR_MEM8(0x10C) -+#define MAF0EN 0 -+#define MAF1EN 1 -+#define MAF2EN 2 -+#define MAF3EN 3 -+ -+#define MAFCR1 _SFR_MEM8(0x10D) -+#define AACK_0_I_AM_COORD 0 -+#define AACK_0_SET_PD 1 -+#define AACK_1_I_AM_COORD 2 -+#define AACK_1_SET_PD 3 -+#define AACK_2_I_AM_COORD 4 -+#define AACK_2_SET_PD 5 -+#define AACK_3_I_AM_COORD 6 -+#define AACK_3_SET_PD 7 -+ -+#define MAFSA0L _SFR_MEM8(0x10E) -+#define MAFSA0L0 0 -+#define MAFSA0L1 1 -+#define MAFSA0L2 2 -+#define MAFSA0L3 3 -+#define MAFSA0L4 4 -+#define MAFSA0L5 5 -+#define MAFSA0L6 6 -+#define MAFSA0L7 7 -+ -+#define MAFSA0H _SFR_MEM8(0x10F) -+#define MAFSA0H0 0 -+#define MAFSA0H1 1 -+#define MAFSA0H2 2 -+#define MAFSA0H3 3 -+#define MAFSA0H4 4 -+#define MAFSA0H5 5 -+#define MAFSA0H6 6 -+#define MAFSA0H7 7 -+ -+#define MAFPA0L _SFR_MEM8(0x110) -+#define MAFPA0L0 0 -+#define MAFPA0L1 1 -+#define MAFPA0L2 2 -+#define MAFPA0L3 3 -+#define MAFPA0L4 4 -+#define MAFPA0L5 5 -+#define MAFPA0L6 6 -+#define MAFPA0L7 7 -+ -+#define MAFPA0H _SFR_MEM8(0x111) -+#define MAFPA0H0 0 -+#define MAFPA0H1 1 -+#define MAFPA0H2 2 -+#define MAFPA0H3 3 -+#define MAFPA0H4 4 -+#define MAFPA0H5 5 -+#define MAFPA0H6 6 -+#define MAFPA0H7 7 -+ -+#define MAFSA1L _SFR_MEM8(0x112) -+#define MAFSA1L0 0 -+#define MAFSA1L1 1 -+#define MAFSA1L2 2 -+#define MAFSA1L3 3 -+#define MAFSA1L4 4 -+#define MAFSA1L5 5 -+#define MAFSA1L6 6 -+#define MAFSA1L7 7 -+ -+#define MAFSA1H _SFR_MEM8(0x113) -+#define MAFSA1H0 0 -+#define MAFSA1H1 1 -+#define MAFSA1H2 2 -+#define MAFSA1H3 3 -+#define MAFSA1H4 4 -+#define MAFSA1H5 5 -+#define MAFSA1H6 6 -+#define MAFSA1H7 7 -+ -+#define MAFPA1L _SFR_MEM8(0x114) -+#define MAFPA1L0 0 -+#define MAFPA1L1 1 -+#define MAFPA1L2 2 -+#define MAFPA1L3 3 -+#define MAFPA1L4 4 -+#define MAFPA1L5 5 -+#define MAFPA1L6 6 -+#define MAFPA1L7 7 -+ -+#define MAFPA1H _SFR_MEM8(0x115) -+#define MAFPA1H0 0 -+#define MAFPA1H1 1 -+#define MAFPA1H2 2 -+#define MAFPA1H3 3 -+#define MAFPA1H4 4 -+#define MAFPA1H5 5 -+#define MAFPA1H6 6 -+#define MAFPA1H7 7 -+ -+#define MAFSA2L _SFR_MEM8(0x116) -+#define MAFSA2L0 0 -+#define MAFSA2L1 1 -+#define MAFSA2L2 2 -+#define MAFSA2L3 3 -+#define MAFSA2L4 4 -+#define MAFSA2L5 5 -+#define MAFSA2L6 6 -+#define MAFSA2L7 7 -+ -+#define MAFSA2H _SFR_MEM8(0x117) -+#define MAFSA2H0 0 -+#define MAFSA2H1 1 -+#define MAFSA2H2 2 -+#define MAFSA2H3 3 -+#define MAFSA2H4 4 -+#define MAFSA2H5 5 -+#define MAFSA2H6 6 -+#define MAFSA2H7 7 -+ -+#define MAFPA2L _SFR_MEM8(0x118) -+#define MAFPA2L0 0 -+#define MAFPA2L1 1 -+#define MAFPA2L2 2 -+#define MAFPA2L3 3 -+#define MAFPA2L4 4 -+#define MAFPA2L5 5 -+#define MAFPA2L6 6 -+#define MAFPA2L7 7 -+ -+#define MAFPA2H _SFR_MEM8(0x119) -+#define MAFPA2H0 0 -+#define MAFPA2H1 1 -+#define MAFPA2H2 2 -+#define MAFPA2H3 3 -+#define MAFPA2H4 4 -+#define MAFPA2H5 5 -+#define MAFPA2H6 6 -+#define MAFPA2H7 7 -+ -+#define MAFSA3L _SFR_MEM8(0x11A) -+#define MAFSA3L0 0 -+#define MAFSA3L1 1 -+#define MAFSA3L2 2 -+#define MAFSA3L3 3 -+#define MAFSA3L4 4 -+#define MAFSA3L5 5 -+#define MAFSA3L6 6 -+#define MAFSA3L7 7 -+ -+#define MAFSA3H _SFR_MEM8(0x11B) -+#define MAFSA3H0 0 -+#define MAFSA3H1 1 -+#define MAFSA3H2 2 -+#define MAFSA3H3 3 -+#define MAFSA3H4 4 -+#define MAFSA3H5 5 -+#define MAFSA3H6 6 -+#define MAFSA3H7 7 -+ -+#define MAFPA3L _SFR_MEM8(0x11C) -+#define MAFPA3L0 0 -+#define MAFPA3L1 1 -+#define MAFPA3L2 2 -+#define MAFPA3L3 3 -+#define MAFPA3L4 4 -+#define MAFPA3L5 5 -+#define MAFPA3L6 6 -+#define MAFPA3L7 7 -+ -+#define MAFPA3H _SFR_MEM8(0x11D) -+#define MAFPA3H0 0 -+#define MAFPA3H1 1 -+#define MAFPA3H2 2 -+#define MAFPA3H3 3 -+#define MAFPA3H4 4 -+#define MAFPA3H5 5 -+#define MAFPA3H6 6 -+#define MAFPA3H7 7 -+ -+/* Reserved [0x11E..0x11F] */ -+ -+#define TCCR5A _SFR_MEM8(0x120) -+#define WGM50 0 -+#define WGM51 1 -+#define COM5C0 2 -+#define COM5C1 3 -+#define COM5B0 4 -+#define COM5B1 5 -+#define COM5A0 6 -+#define COM5A1 7 -+ -+#define TCCR5B _SFR_MEM8(0x121) -+#define CS50 0 -+#define CS51 1 -+#define CS52 2 -+#define WGM52 3 -+#define WGM53 4 -+#define ICES5 6 -+#define ICNC5 7 -+ -+#define TCCR5C _SFR_MEM8(0x122) -+#define FOC5C 5 -+#define FOC5B 6 -+#define FOC5A 7 -+ -+/* Reserved [0x123] */ -+ -+/* Combine TCNT5L and TCNT5H */ -+#define TCNT5 _SFR_MEM16(0x124) -+ -+#define TCNT5L _SFR_MEM8(0x124) -+#define TCNT5H _SFR_MEM8(0x125) -+ -+/* Combine ICR5L and ICR5H */ -+#define ICR5 _SFR_MEM16(0x126) -+ -+#define ICR5L _SFR_MEM8(0x126) -+#define ICR5H _SFR_MEM8(0x127) -+ -+/* Combine OCR5AL and OCR5AH */ -+#define OCR5A _SFR_MEM16(0x128) -+ -+#define OCR5AL _SFR_MEM8(0x128) -+#define OCR5AH _SFR_MEM8(0x129) -+ -+/* Combine OCR5BL and OCR5BH */ -+#define OCR5B _SFR_MEM16(0x12A) -+ -+#define OCR5BL _SFR_MEM8(0x12A) -+#define OCR5BH _SFR_MEM8(0x12B) -+ -+/* Combine OCR5CL and OCR5CH */ -+#define OCR5C _SFR_MEM16(0x12C) -+ -+#define OCR5CL _SFR_MEM8(0x12C) -+#define OCR5CH _SFR_MEM8(0x12D) -+ -+/* Reserved [0x12E] */ -+ -+#define LLCR _SFR_MEM8(0x12F) -+#define LLENCAL 0 -+#define LLSHORT 1 -+#define LLTCO 2 -+#define LLCAL 3 -+#define LLCOMP 4 -+#define LLDONE 5 -+ -+#define LLDRL _SFR_MEM8(0x130) -+#define LLDRL0 0 -+#define LLDRL1 1 -+#define LLDRL2 2 -+#define LLDRL3 3 -+ -+#define LLDRH _SFR_MEM8(0x131) -+#define LLDRH0 0 -+#define LLDRH1 1 -+#define LLDRH2 2 -+#define LLDRH3 3 -+#define LLDRH4 4 -+ -+#define DRTRAM3 _SFR_MEM8(0x132) -+#define ENDRT 4 -+#define DRTSWOK 5 -+ -+#define DRTRAM2 _SFR_MEM8(0x133) -+ -+#define DRTRAM1 _SFR_MEM8(0x134) -+ -+#define DRTRAM0 _SFR_MEM8(0x135) -+ -+#define DPDS0 _SFR_MEM8(0x136) -+#define PBDRV0 0 -+#define PBDRV1 1 -+#define PDDRV0 2 -+#define PDDRV1 3 -+#define PEDRV0 4 -+#define PEDRV1 5 -+#define PFDRV0 6 -+#define PFDRV1 7 -+ -+#define DPDS1 _SFR_MEM8(0x137) -+#define PGDRV0 0 -+#define PGDRV1 1 -+ -+#define PARCR _SFR_MEM8(0x138) -+#define PARUFI 0 -+#define PARDFI 1 -+#define PALTU0 2 -+#define PALTU1 3 -+#define PALTU2 4 -+#define PALTD0 5 -+#define PALTD1 6 -+#define PALTD2 7 -+ -+#define TRXPR _SFR_MEM8(0x139) -+#define TRXRST 0 -+#define SLPTR 1 -+ -+/* Reserved [0x13A..0x13B] */ -+ -+#define AES_CTRL _SFR_MEM8(0x13C) -+#define AES_IM 2 -+#define AES_DIR 3 -+#define AES_MODE 5 -+#define AES_REQUEST 7 -+ -+#define AES_STATUS _SFR_MEM8(0x13D) -+#define AES_DONE 0 -+#define AES_ER 7 -+ -+#define AES_STATE _SFR_MEM8(0x13E) -+#define AES_STATE0 0 -+#define AES_STATE1 1 -+#define AES_STATE2 2 -+#define AES_STATE3 3 -+#define AES_STATE4 4 -+#define AES_STATE5 5 -+#define AES_STATE6 6 -+#define AES_STATE7 7 -+ -+#define AES_KEY _SFR_MEM8(0x13F) -+#define AES_KEY0 0 -+#define AES_KEY1 1 -+#define AES_KEY2 2 -+#define AES_KEY3 3 -+#define AES_KEY4 4 -+#define AES_KEY5 5 -+#define AES_KEY6 6 -+#define AES_KEY7 7 -+ -+/* Reserved [0x140] */ -+ -+#define TRX_STATUS _SFR_MEM8(0x141) -+#define TRX_STATUS0 0 -+#define TRX_STATUS1 1 -+#define TRX_STATUS2 2 -+#define TRX_STATUS3 3 -+#define TRX_STATUS4 4 -+#define TST_STATUS 5 -+#define CCA_STATUS 6 -+#define CCA_DONE 7 -+ -+#define TRX_STATE _SFR_MEM8(0x142) -+#define TRX_CMD0 0 -+#define TRX_CMD1 1 -+#define TRX_CMD2 2 -+#define TRX_CMD3 3 -+#define TRX_CMD4 4 -+#define TRAC_STATUS0 5 -+#define TRAC_STATUS1 6 -+#define TRAC_STATUS2 7 -+ -+#define TRX_CTRL_0 _SFR_MEM8(0x143) -+#define PMU_IF_INV 4 -+#define PMU_START 5 -+#define PMU_EN 6 -+#define Res7 7 -+ -+#define TRX_CTRL_1 _SFR_MEM8(0x144) -+#define PLL_TX_FLT 4 -+#define TX_AUTO_CRC_ON 5 -+#define IRQ_2_EXT_EN 6 -+#define PA_EXT_EN 7 -+ -+#define PHY_TX_PWR _SFR_MEM8(0x145) -+#define TX_PWR0 0 -+#define TX_PWR1 1 -+#define TX_PWR2 2 -+#define TX_PWR3 3 -+ -+#define PHY_RSSI _SFR_MEM8(0x146) -+#define RSSI0 0 -+#define RSSI1 1 -+#define RSSI2 2 -+#define RSSI3 3 -+#define RSSI4 4 -+#define RND_VALUE0 5 -+#define RND_VALUE1 6 -+#define RX_CRC_VALID 7 -+ -+#define PHY_ED_LEVEL _SFR_MEM8(0x147) -+#define ED_LEVEL0 0 -+#define ED_LEVEL1 1 -+#define ED_LEVEL2 2 -+#define ED_LEVEL3 3 -+#define ED_LEVEL4 4 -+#define ED_LEVEL5 5 -+#define ED_LEVEL6 6 -+#define ED_LEVEL7 7 -+ -+#define PHY_CC_CCA _SFR_MEM8(0x148) -+#define CHANNEL0 0 -+#define CHANNEL1 1 -+#define CHANNEL2 2 -+#define CHANNEL3 3 -+#define CHANNEL4 4 -+#define CCA_MODE0 5 -+#define CCA_MODE1 6 -+#define CCA_REQUEST 7 -+ -+#define CCA_THRES _SFR_MEM8(0x149) -+#define CCA_ED_THRES0 0 -+#define CCA_ED_THRES1 1 -+#define CCA_ED_THRES2 2 -+#define CCA_ED_THRES3 3 -+#define CCA_CS_THRES0 4 -+#define CCA_CS_THRES1 5 -+#define CCA_CS_THRES2 6 -+#define CCA_CS_THRES3 7 -+ -+#define RX_CTRL _SFR_MEM8(0x14A) -+#define PDT_THRES0 0 -+#define PDT_THRES1 1 -+#define PDT_THRES2 2 -+#define PDT_THRES3 3 -+ -+#define SFD_VALUE _SFR_MEM8(0x14B) -+#define SFD_VALUE0 0 -+#define SFD_VALUE1 1 -+#define SFD_VALUE2 2 -+#define SFD_VALUE3 3 -+#define SFD_VALUE4 4 -+#define SFD_VALUE5 5 -+#define SFD_VALUE6 6 -+#define SFD_VALUE7 7 -+ -+#define TRX_CTRL_2 _SFR_MEM8(0x14C) -+#define OQPSK_DATA_RATE0 0 -+#define OQPSK_DATA_RATE1 1 -+#define RX_SAFE_MODE 7 -+ -+#define ANT_DIV _SFR_MEM8(0x14D) -+#define ANT_CTRL0 0 -+#define ANT_CTRL1 1 -+#define ANT_EXT_SW_EN 2 -+#define ANT_DIV_EN 3 -+#define ANT_SEL 7 -+ -+#define IRQ_MASK _SFR_MEM8(0x14E) -+#define PLL_LOCK_EN 0 -+#define PLL_UNLOCK_EN 1 -+#define RX_START_EN 2 -+#define RX_END_EN 3 -+#define CCA_ED_DONE_EN 4 -+#define AMI_EN 5 -+#define TX_END_EN 6 -+#define AWAKE_EN 7 -+ -+#define IRQ_STATUS _SFR_MEM8(0x14F) -+#define PLL_LOCK 0 -+#define PLL_UNLOCK 1 -+#define RX_START 2 -+#define RX_END 3 -+#define CCA_ED_DONE 4 -+#define AMI 5 -+#define TX_END 6 -+#define AWAKE 7 -+ -+#define VREG_CTRL _SFR_MEM8(0x150) -+#define DVDD_OK 2 -+#define DVREG_EXT 3 -+#define AVDD_OK 6 -+#define AVREG_EXT 7 -+ -+#define BATMON _SFR_MEM8(0x151) -+#define BATMON_VTH0 0 -+#define BATMON_VTH1 1 -+#define BATMON_VTH2 2 -+#define BATMON_VTH3 3 -+#define BATMON_HR 4 -+#define BATMON_OK 5 -+#define BAT_LOW_EN 6 -+#define BAT_LOW 7 -+ -+#define XOSC_CTRL _SFR_MEM8(0x152) -+#define XTAL_TRIM0 0 -+#define XTAL_TRIM1 1 -+#define XTAL_TRIM2 2 -+#define XTAL_TRIM3 3 -+#define XTAL_MODE0 4 -+#define XTAL_MODE1 5 -+#define XTAL_MODE2 6 -+#define XTAL_MODE3 7 -+ -+#define CC_CTRL_0 _SFR_MEM8(0x153) -+#define CC_NUMBER0 0 -+#define CC_NUMBER1 1 -+#define CC_NUMBER2 2 -+#define CC_NUMBER3 3 -+#define CC_NUMBER4 4 -+#define CC_NUMBER5 5 -+#define CC_NUMBER6 6 -+#define CC_NUMBER7 7 -+ -+#define CC_CTRL_1 _SFR_MEM8(0x154) -+#define CC_BAND0 0 -+#define CC_BAND1 1 -+#define CC_BAND2 2 -+#define CC_BAND3 3 -+ -+#define RX_SYN _SFR_MEM8(0x155) -+#define RX_PDT_LEVEL0 0 -+#define RX_PDT_LEVEL1 1 -+#define RX_PDT_LEVEL2 2 -+#define RX_PDT_LEVEL3 3 -+#define RX_OVERRIDE 6 -+#define RX_PDT_DIS 7 -+ -+#define TRX_RPC _SFR_MEM8(0x156) -+#define XAH_RPC_EN 0 -+#define IPAN_RPC_EN 1 -+#define PLL_RPC_EN 3 -+#define PDT_RPC_EN 4 -+#define RX_RPC_EN 5 -+#define RX_RPC_CTRL0 6 -+#define RX_RPC_CTRL1 7 -+ -+#define XAH_CTRL_1 _SFR_MEM8(0x157) -+#define AACK_PROM_MODE 1 -+#define AACK_ACK_TIME 2 -+#define AACK_UPLD_RES_FT 4 -+#define AACK_FLTR_RES_FT 5 -+ -+#define FTN_CTRL _SFR_MEM8(0x158) -+#define FTN_START 7 -+ -+/* Reserved [0x159] */ -+ -+#define PLL_CF _SFR_MEM8(0x15A) -+#define PLL_CF_START 7 -+ -+#define PLL_DCU _SFR_MEM8(0x15B) -+#define PLL_DCU_START 7 -+ -+#define PART_NUM _SFR_MEM8(0x15C) -+#define PART_NUM0 0 -+#define PART_NUM1 1 -+#define PART_NUM2 2 -+#define PART_NUM3 3 -+#define PART_NUM4 4 -+#define PART_NUM5 5 -+#define PART_NUM6 6 -+#define PART_NUM7 7 -+ -+#define VERSION_NUM _SFR_MEM8(0x15D) -+#define VERSION_NUM0 0 -+#define VERSION_NUM1 1 -+#define VERSION_NUM2 2 -+#define VERSION_NUM3 3 -+#define VERSION_NUM4 4 -+#define VERSION_NUM5 5 -+#define VERSION_NUM6 6 -+#define VERSION_NUM7 7 -+ -+#define MAN_ID_0 _SFR_MEM8(0x15E) -+#define MAN_ID_00 0 -+#define MAN_ID_01 1 -+#define MAN_ID_02 2 -+#define MAN_ID_03 3 -+#define MAN_ID_04 4 -+#define MAN_ID_05 5 -+#define MAN_ID_06 6 -+#define MAN_ID_07 7 -+ -+#define MAN_ID_1 _SFR_MEM8(0x15F) -+#define MAN_ID_10 0 -+#define MAN_ID_11 1 -+#define MAN_ID_12 2 -+#define MAN_ID_13 3 -+#define MAN_ID_14 4 -+#define MAN_ID_15 5 -+#define MAN_ID_16 6 -+#define MAN_ID_17 7 -+ -+#define SHORT_ADDR_0 _SFR_MEM8(0x160) -+#define SHORT_ADDR_00 0 -+#define SHORT_ADDR_01 1 -+#define SHORT_ADDR_02 2 -+#define SHORT_ADDR_03 3 -+#define SHORT_ADDR_04 4 -+#define SHORT_ADDR_05 5 -+#define SHORT_ADDR_06 6 -+#define SHORT_ADDR_07 7 -+ -+#define SHORT_ADDR_1 _SFR_MEM8(0x161) -+#define SHORT_ADDR_10 0 -+#define SHORT_ADDR_11 1 -+#define SHORT_ADDR_12 2 -+#define SHORT_ADDR_13 3 -+#define SHORT_ADDR_14 4 -+#define SHORT_ADDR_15 5 -+#define SHORT_ADDR_16 6 -+#define SHORT_ADDR_17 7 -+ -+#define PAN_ID_0 _SFR_MEM8(0x162) -+#define PAN_ID_00 0 -+#define PAN_ID_01 1 -+#define PAN_ID_02 2 -+#define PAN_ID_03 3 -+#define PAN_ID_04 4 -+#define PAN_ID_05 5 -+#define PAN_ID_06 6 -+#define PAN_ID_07 7 -+ -+#define PAN_ID_1 _SFR_MEM8(0x163) -+#define PAN_ID_10 0 -+#define PAN_ID_11 1 -+#define PAN_ID_12 2 -+#define PAN_ID_13 3 -+#define PAN_ID_14 4 -+#define PAN_ID_15 5 -+#define PAN_ID_16 6 -+#define PAN_ID_17 7 -+ -+#define IEEE_ADDR_0 _SFR_MEM8(0x164) -+#define IEEE_ADDR_00 0 -+#define IEEE_ADDR_01 1 -+#define IEEE_ADDR_02 2 -+#define IEEE_ADDR_03 3 -+#define IEEE_ADDR_04 4 -+#define IEEE_ADDR_05 5 -+#define IEEE_ADDR_06 6 -+#define IEEE_ADDR_07 7 -+ -+#define IEEE_ADDR_1 _SFR_MEM8(0x165) -+#define IEEE_ADDR_10 0 -+#define IEEE_ADDR_11 1 -+#define IEEE_ADDR_12 2 -+#define IEEE_ADDR_13 3 -+#define IEEE_ADDR_14 4 -+#define IEEE_ADDR_15 5 -+#define IEEE_ADDR_16 6 -+#define IEEE_ADDR_17 7 -+ -+#define IEEE_ADDR_2 _SFR_MEM8(0x166) -+#define IEEE_ADDR_20 0 -+#define IEEE_ADDR_21 1 -+#define IEEE_ADDR_22 2 -+#define IEEE_ADDR_23 3 -+#define IEEE_ADDR_24 4 -+#define IEEE_ADDR_25 5 -+#define IEEE_ADDR_26 6 -+#define IEEE_ADDR_27 7 -+ -+#define IEEE_ADDR_3 _SFR_MEM8(0x167) -+#define IEEE_ADDR_30 0 -+#define IEEE_ADDR_31 1 -+#define IEEE_ADDR_32 2 -+#define IEEE_ADDR_33 3 -+#define IEEE_ADDR_34 4 -+#define IEEE_ADDR_35 5 -+#define IEEE_ADDR_36 6 -+#define IEEE_ADDR_37 7 -+ -+#define IEEE_ADDR_4 _SFR_MEM8(0x168) -+#define IEEE_ADDR_40 0 -+#define IEEE_ADDR_41 1 -+#define IEEE_ADDR_42 2 -+#define IEEE_ADDR_43 3 -+#define IEEE_ADDR_44 4 -+#define IEEE_ADDR_45 5 -+#define IEEE_ADDR_46 6 -+#define IEEE_ADDR_47 7 -+ -+#define IEEE_ADDR_5 _SFR_MEM8(0x169) -+#define IEEE_ADDR_50 0 -+#define IEEE_ADDR_51 1 -+#define IEEE_ADDR_52 2 -+#define IEEE_ADDR_53 3 -+#define IEEE_ADDR_54 4 -+#define IEEE_ADDR_55 5 -+#define IEEE_ADDR_56 6 -+#define IEEE_ADDR_57 7 -+ -+#define IEEE_ADDR_6 _SFR_MEM8(0x16A) -+#define IEEE_ADDR_60 0 -+#define IEEE_ADDR_61 1 -+#define IEEE_ADDR_62 2 -+#define IEEE_ADDR_63 3 -+#define IEEE_ADDR_64 4 -+#define IEEE_ADDR_65 5 -+#define IEEE_ADDR_66 6 -+#define IEEE_ADDR_67 7 -+ -+#define IEEE_ADDR_7 _SFR_MEM8(0x16B) -+#define IEEE_ADDR_70 0 -+#define IEEE_ADDR_71 1 -+#define IEEE_ADDR_72 2 -+#define IEEE_ADDR_73 3 -+#define IEEE_ADDR_74 4 -+#define IEEE_ADDR_75 5 -+#define IEEE_ADDR_76 6 -+#define IEEE_ADDR_77 7 -+ -+#define XAH_CTRL_0 _SFR_MEM8(0x16C) -+#define SLOTTED_OPERATION 0 -+#define MAX_CSMA_RETRIES0 1 -+#define MAX_CSMA_RETRIES1 2 -+#define MAX_CSMA_RETRIES2 3 -+#define MAX_FRAME_RETRIES0 4 -+#define MAX_FRAME_RETRIES1 5 -+#define MAX_FRAME_RETRIES2 6 -+#define MAX_FRAME_RETRIES3 7 -+ -+#define CSMA_SEED_0 _SFR_MEM8(0x16D) -+#define CSMA_SEED_00 0 -+#define CSMA_SEED_01 1 -+#define CSMA_SEED_02 2 -+#define CSMA_SEED_03 3 -+#define CSMA_SEED_04 4 -+#define CSMA_SEED_05 5 -+#define CSMA_SEED_06 6 -+#define CSMA_SEED_07 7 -+ -+#define CSMA_SEED_1 _SFR_MEM8(0x16E) -+#define CSMA_SEED_10 0 -+#define CSMA_SEED_11 1 -+#define CSMA_SEED_12 2 -+#define AACK_I_AM_COORD 3 -+#define AACK_DIS_ACK 4 -+#define AACK_SET_PD 5 -+#define AACK_FVN_MODE0 6 -+#define AACK_FVN_MODE1 7 -+ -+#define CSMA_BE _SFR_MEM8(0x16F) -+#define MIN_BE0 0 -+#define MIN_BE1 1 -+#define MIN_BE2 2 -+#define MIN_BE3 3 -+#define MAX_BE0 4 -+#define MAX_BE1 5 -+#define MAX_BE2 6 -+#define MAX_BE3 7 -+ -+/* Reserved [0x170..0x175] */ -+ -+#define TST_CTRL_DIGI _SFR_MEM8(0x176) -+#define TST_CTRL_DIG0 0 -+#define TST_CTRL_DIG1 1 -+#define TST_CTRL_DIG2 2 -+#define TST_CTRL_DIG3 3 -+ -+/* Reserved [0x177..0x17A] */ -+ -+#define TST_RX_LENGTH _SFR_MEM8(0x17B) -+#define RX_LENGTH0 0 -+#define RX_LENGTH1 1 -+#define RX_LENGTH2 2 -+#define RX_LENGTH3 3 -+#define RX_LENGTH4 4 -+#define RX_LENGTH5 5 -+#define RX_LENGTH6 6 -+#define RX_LENGTH7 7 -+ -+/* Reserved [0x17C..0x17F] */ -+ -+#define TRXFBST _SFR_MEM8(0x180) -+ -+/* Reserved [0x181..0x1FE] */ -+ -+#define TRXFBEND _SFR_MEM8(0x1FF) -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* External Interrupt Request 2 */ -+#define INT2_vect _VECTOR(3) -+#define INT2_vect_num 3 -+ -+/* External Interrupt Request 3 */ -+#define INT3_vect _VECTOR(4) -+#define INT3_vect_num 4 -+ -+/* External Interrupt Request 4 */ -+#define INT4_vect _VECTOR(5) -+#define INT4_vect_num 5 -+ -+/* External Interrupt Request 5 */ -+#define INT5_vect _VECTOR(6) -+#define INT5_vect_num 6 -+ -+/* External Interrupt Request 6 */ -+#define INT6_vect _VECTOR(7) -+#define INT6_vect_num 7 -+ -+/* External Interrupt Request 7 */ -+#define INT7_vect _VECTOR(8) -+#define INT7_vect_num 8 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(9) -+#define PCINT0_vect_num 9 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(10) -+#define PCINT1_vect_num 10 -+ -+/* Pin Change Interrupt Request 2 */ -+#define PCINT2_vect _VECTOR(11) -+#define PCINT2_vect_num 11 -+ -+/* Watchdog Time-out Interrupt */ -+#define WDT_vect _VECTOR(12) -+#define WDT_vect_num 12 -+ -+/* Timer/Counter2 Compare Match A */ -+#define TIMER2_COMPA_vect _VECTOR(13) -+#define TIMER2_COMPA_vect_num 13 -+ -+/* Timer/Counter2 Compare Match B */ -+#define TIMER2_COMPB_vect _VECTOR(14) -+#define TIMER2_COMPB_vect_num 14 -+ -+/* Timer/Counter2 Overflow */ -+#define TIMER2_OVF_vect _VECTOR(15) -+#define TIMER2_OVF_vect_num 15 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(16) -+#define TIMER1_CAPT_vect_num 16 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(17) -+#define TIMER1_COMPA_vect_num 17 -+ -+/* Timer/Counter1 Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(18) -+#define TIMER1_COMPB_vect_num 18 -+ -+/* Timer/Counter1 Compare Match C */ -+#define TIMER1_COMPC_vect _VECTOR(19) -+#define TIMER1_COMPC_vect_num 19 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(20) -+#define TIMER1_OVF_vect_num 20 -+ -+/* Timer/Counter0 Compare Match A */ -+#define TIMER0_COMPA_vect _VECTOR(21) -+#define TIMER0_COMPA_vect_num 21 -+ -+/* Timer/Counter0 Compare Match B */ -+#define TIMER0_COMPB_vect _VECTOR(22) -+#define TIMER0_COMPB_vect_num 22 -+ -+/* Timer/Counter0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(23) -+#define TIMER0_OVF_vect_num 23 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(24) -+#define SPI_STC_vect_num 24 -+ -+/* USART0, Rx Complete */ -+#define USART0_RX_vect _VECTOR(25) -+#define USART0_RX_vect_num 25 -+ -+/* USART0 Data register Empty */ -+#define USART0_UDRE_vect _VECTOR(26) -+#define USART0_UDRE_vect_num 26 -+ -+/* USART0, Tx Complete */ -+#define USART0_TX_vect _VECTOR(27) -+#define USART0_TX_vect_num 27 -+ -+/* Analog Comparator */ -+#define ANALOG_COMP_vect _VECTOR(28) -+#define ANALOG_COMP_vect_num 28 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(29) -+#define ADC_vect_num 29 -+ -+/* EEPROM Ready */ -+#define EE_READY_vect _VECTOR(30) -+#define EE_READY_vect_num 30 -+ -+/* Timer/Counter3 Capture Event */ -+#define TIMER3_CAPT_vect _VECTOR(31) -+#define TIMER3_CAPT_vect_num 31 -+ -+/* Timer/Counter3 Compare Match A */ -+#define TIMER3_COMPA_vect _VECTOR(32) -+#define TIMER3_COMPA_vect_num 32 -+ -+/* Timer/Counter3 Compare Match B */ -+#define TIMER3_COMPB_vect _VECTOR(33) -+#define TIMER3_COMPB_vect_num 33 -+ -+/* Timer/Counter3 Compare Match C */ -+#define TIMER3_COMPC_vect _VECTOR(34) -+#define TIMER3_COMPC_vect_num 34 -+ -+/* Timer/Counter3 Overflow */ -+#define TIMER3_OVF_vect _VECTOR(35) -+#define TIMER3_OVF_vect_num 35 -+ -+/* USART1, Rx Complete */ -+#define USART1_RX_vect _VECTOR(36) -+#define USART1_RX_vect_num 36 -+ -+/* USART1 Data register Empty */ -+#define USART1_UDRE_vect _VECTOR(37) -+#define USART1_UDRE_vect_num 37 -+ -+/* USART1, Tx Complete */ -+#define USART1_TX_vect _VECTOR(38) -+#define USART1_TX_vect_num 38 -+ -+/* 2-wire Serial Interface */ -+#define TWI_vect _VECTOR(39) -+#define TWI_vect_num 39 -+ -+/* Store Program Memory Read */ -+#define SPM_READY_vect _VECTOR(40) -+#define SPM_READY_vect_num 40 -+ -+/* Timer/Counter4 Capture Event */ -+#define TIMER4_CAPT_vect _VECTOR(41) -+#define TIMER4_CAPT_vect_num 41 -+ -+/* Timer/Counter4 Compare Match A */ -+#define TIMER4_COMPA_vect _VECTOR(42) -+#define TIMER4_COMPA_vect_num 42 -+ -+/* Timer/Counter4 Compare Match B */ -+#define TIMER4_COMPB_vect _VECTOR(43) -+#define TIMER4_COMPB_vect_num 43 -+ -+/* Timer/Counter4 Compare Match C */ -+#define TIMER4_COMPC_vect _VECTOR(44) -+#define TIMER4_COMPC_vect_num 44 -+ -+/* Timer/Counter4 Overflow */ -+#define TIMER4_OVF_vect _VECTOR(45) -+#define TIMER4_OVF_vect_num 45 -+ -+/* Timer/Counter5 Capture Event */ -+#define TIMER5_CAPT_vect _VECTOR(46) -+#define TIMER5_CAPT_vect_num 46 -+ -+/* Timer/Counter5 Compare Match A */ -+#define TIMER5_COMPA_vect _VECTOR(47) -+#define TIMER5_COMPA_vect_num 47 -+ -+/* Timer/Counter5 Compare Match B */ -+#define TIMER5_COMPB_vect _VECTOR(48) -+#define TIMER5_COMPB_vect_num 48 -+ -+/* Timer/Counter5 Compare Match C */ -+#define TIMER5_COMPC_vect _VECTOR(49) -+#define TIMER5_COMPC_vect_num 49 -+ -+/* Timer/Counter5 Overflow */ -+#define TIMER5_OVF_vect _VECTOR(50) -+#define TIMER5_OVF_vect_num 50 -+ -+/* USART2, Rx Complete */ -+#define USART2_RX_vect _VECTOR(51) -+#define USART2_RX_vect_num 51 -+ -+/* USART2 Data register Empty */ -+#define USART2_UDRE_vect _VECTOR(52) -+#define USART2_UDRE_vect_num 52 -+ -+/* USART2, Tx Complete */ -+#define USART2_TX_vect _VECTOR(53) -+#define USART2_TX_vect_num 53 -+ -+/* USART3, Rx Complete */ -+#define USART3_RX_vect _VECTOR(54) -+#define USART3_RX_vect_num 54 -+ -+/* USART3 Data register Empty */ -+#define USART3_UDRE_vect _VECTOR(55) -+#define USART3_UDRE_vect_num 55 -+ -+/* USART3, Tx Complete */ -+#define USART3_TX_vect _VECTOR(56) -+#define USART3_TX_vect_num 56 -+ -+/* TRX24 - PLL lock interrupt */ -+#define TRX24_PLL_LOCK_vect _VECTOR(57) -+#define TRX24_PLL_LOCK_vect_num 57 -+ -+/* TRX24 - PLL unlock interrupt */ -+#define TRX24_PLL_UNLOCK_vect _VECTOR(58) -+#define TRX24_PLL_UNLOCK_vect_num 58 -+ -+/* TRX24 - Receive start interrupt */ -+#define TRX24_RX_START_vect _VECTOR(59) -+#define TRX24_RX_START_vect_num 59 -+ -+/* TRX24 - RX_END interrupt */ -+#define TRX24_RX_END_vect _VECTOR(60) -+#define TRX24_RX_END_vect_num 60 -+ -+/* TRX24 - CCA/ED done interrupt */ -+#define TRX24_CCA_ED_DONE_vect _VECTOR(61) -+#define TRX24_CCA_ED_DONE_vect_num 61 -+ -+/* TRX24 - XAH - AMI */ -+#define TRX24_XAH_AMI_vect _VECTOR(62) -+#define TRX24_XAH_AMI_vect_num 62 -+ -+/* TRX24 - TX_END interrupt */ -+#define TRX24_TX_END_vect _VECTOR(63) -+#define TRX24_TX_END_vect_num 63 -+ -+/* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */ -+#define TRX24_AWAKE_vect _VECTOR(64) -+#define TRX24_AWAKE_vect_num 64 -+ -+/* Symbol counter - compare match 1 interrupt */ -+#define SCNT_CMP1_vect _VECTOR(65) -+#define SCNT_CMP1_vect_num 65 -+ -+/* Symbol counter - compare match 2 interrupt */ -+#define SCNT_CMP2_vect _VECTOR(66) -+#define SCNT_CMP2_vect_num 66 -+ -+/* Symbol counter - compare match 3 interrupt */ -+#define SCNT_CMP3_vect _VECTOR(67) -+#define SCNT_CMP3_vect_num 67 -+ -+/* Symbol counter - overflow interrupt */ -+#define SCNT_OVFL_vect _VECTOR(68) -+#define SCNT_OVFL_vect_num 68 -+ -+/* Symbol counter - backoff interrupt */ -+#define SCNT_BACKOFF_vect _VECTOR(69) -+#define SCNT_BACKOFF_vect_num 69 -+ -+/* AES engine ready interrupt */ -+#define AES_READY_vect _VECTOR(70) -+#define AES_READY_vect_num 70 -+ -+/* Battery monitor indicates supply voltage below threshold */ -+#define BAT_LOW_vect _VECTOR(71) -+#define BAT_LOW_vect_num 71 -+ -+/* TRX24 TX start interrupt */ -+#define TRX24_TX_START_vect _VECTOR(72) -+#define TRX24_TX_START_vect_num 72 -+ -+/* Address match interrupt of address filter 0 */ -+#define TRX24_AMI0_vect _VECTOR(73) -+#define TRX24_AMI0_vect_num 73 -+ -+/* Address match interrupt of address filter 1 */ -+#define TRX24_AMI1_vect _VECTOR(74) -+#define TRX24_AMI1_vect_num 74 -+ -+/* Address match interrupt of address filter 2 */ -+#define TRX24_AMI2_vect _VECTOR(75) -+#define TRX24_AMI2_vect_num 75 -+ -+/* Address match interrupt of address filter 3 */ -+#define TRX24_AMI3_vect _VECTOR(76) -+#define TRX24_AMI3_vect_num 76 -+ -+#define _VECTORS_SIZE 308 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 256 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x1FFFF -+#define RAMSTART 0x0200 -+#define RAMSIZE 16384 -+#define RAMEND 0x41FF -+#define E2START 0 -+#define E2SIZE 4096 -+#define E2PAGESIZE 8 -+#define E2END 0x0FFF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_CKSEL_SUT0 (unsigned char)~_BV(0) -+#define FUSE_CKSEL_SUT1 (unsigned char)~_BV(1) -+#define FUSE_CKSEL_SUT2 (unsigned char)~_BV(2) -+#define FUSE_CKSEL_SUT3 (unsigned char)~_BV(3) -+#define FUSE_CKSEL_SUT4 (unsigned char)~_BV(4) -+#define FUSE_CKSEL_SUT5 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_JTAGEN (unsigned char)~_BV(6) -+#define FUSE_OCDEN (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0xA7 -+#define SIGNATURE_2 0x02 -+ -+ -+#endif /* #ifdef _AVR_ATMEGA128RFR2_H_INCLUDED */ -+ -diff --git a/include/avr/iom164.h b/include/avr/iom164.h -index 9c64599..6a88ecb 100644 ---- a/include/avr/iom164.h -+++ b/include/avr/iom164.h -@@ -89,7 +89,7 @@ - /* Signature (ATmega164P) */ - #define SIGNATURE_0 0x1E - #define SIGNATURE_1 0x94 --#define SIGNATURE_2 0x0A -+#define SIGNATURE_2 0x0F - - - #endif /* _AVR_IOM164_H_ */ -diff --git a/include/avr/iom164a.h b/include/avr/iom164a.h -new file mode 100644 -index 0000000..1ece639 ---- /dev/null -+++ b/include/avr/iom164a.h -@@ -0,0 +1,34 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2011 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+#include "iom164.h" -diff --git a/include/avr/iom164p.h b/include/avr/iom164p.h -new file mode 100644 -index 0000000..1ece639 ---- /dev/null -+++ b/include/avr/iom164p.h -@@ -0,0 +1,34 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2011 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+#include "iom164.h" -diff --git a/include/avr/iom164pa.h b/include/avr/iom164pa.h -new file mode 100644 -index 0000000..b6c6a68 ---- /dev/null -+++ b/include/avr/iom164pa.h -@@ -0,0 +1,926 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATMEGA164PA_H_INCLUDED -+#define _AVR_ATMEGA164PA_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iom164pa.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINA _SFR_IO8(0x00) -+#define PINA7 7 -+#define PINA6 6 -+#define PINA5 5 -+#define PINA4 4 -+#define PINA3 3 -+#define PINA2 2 -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x01) -+#define DDRA7 7 -+#define DDRA6 6 -+#define DDRA5 5 -+#define DDRA4 4 -+#define DDRA3 3 -+#define DDRA2 2 -+#define DDRA1 1 -+#define DDRA0 0 -+ -+#define PORTA _SFR_IO8(0x02) -+#define PORTA7 7 -+#define PORTA6 6 -+#define PORTA5 5 -+#define PORTA4 4 -+#define PORTA3 3 -+#define PORTA2 2 -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x06) -+#define PINC7 7 -+#define PINC6 6 -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x07) -+#define DDRC7 7 -+#define DDRC6 6 -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x08) -+#define PORTC7 7 -+#define PORTC6 6 -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PIND _SFR_IO8(0x09) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0A) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x0B) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+/* Reserved [0x0C..0x14] */ -+ -+#define TIFR0 _SFR_IO8(0x15) -+#define TOV0 0 -+#define OCF0A 1 -+#define OCF0B 2 -+ -+#define TIFR1 _SFR_IO8(0x16) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define ICF1 5 -+ -+#define TIFR2 _SFR_IO8(0x17) -+#define TOV2 0 -+#define OCF2A 1 -+#define OCF2B 2 -+ -+/* Reserved [0x18..0x1A] */ -+ -+#define PCIFR _SFR_IO8(0x1B) -+#define PCIF0 0 -+#define PCIF1 1 -+#define PCIF2 2 -+#define PCIF3 3 -+ -+#define EIFR _SFR_IO8(0x1C) -+#define INTF0 0 -+#define INTF1 1 -+#define INTF2 2 -+ -+#define EIMSK _SFR_IO8(0x1D) -+#define INT0 0 -+#define INT1 1 -+#define INT2 2 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+#define GPIOR00 0 -+#define GPIOR01 1 -+#define GPIOR02 2 -+#define GPIOR03 3 -+#define GPIOR04 4 -+#define GPIOR05 5 -+#define GPIOR06 6 -+#define GPIOR07 7 -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEPE 1 -+#define EEMPE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSRSYNC 0 -+#define TSM 7 -+#define PSRASY 1 -+ -+#define TCCR0A _SFR_IO8(0x24) -+#define WGM00 0 -+#define WGM01 1 -+#define COM0B0 4 -+#define COM0B1 5 -+#define COM0A0 6 -+#define COM0A1 7 -+ -+#define TCCR0B _SFR_IO8(0x25) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define WGM02 3 -+#define FOC0B 6 -+#define FOC0A 7 -+ -+#define TCNT0 _SFR_IO8(0x26) -+ -+#define OCR0A _SFR_IO8(0x27) -+ -+#define OCR0B _SFR_IO8(0x28) -+ -+/* Reserved [0x29] */ -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+#define GPIOR10 0 -+#define GPIOR11 1 -+#define GPIOR12 2 -+#define GPIOR13 3 -+#define GPIOR14 4 -+#define GPIOR15 5 -+#define GPIOR16 6 -+#define GPIOR17 7 -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+#define GPIOR20 0 -+#define GPIOR21 1 -+#define GPIOR22 2 -+#define GPIOR23 3 -+#define GPIOR24 4 -+#define GPIOR25 5 -+#define GPIOR26 6 -+#define GPIOR27 7 -+ -+#define SPCR0 _SFR_IO8(0x2C) -+#define SPR00 0 -+#define SPR10 1 -+#define CPHA0 2 -+#define CPOL0 3 -+#define MSTR0 4 -+#define DORD0 5 -+#define SPE0 6 -+#define SPIE0 7 -+ -+#define SPSR0 _SFR_IO8(0x2D) -+#define SPI2X0 0 -+#define WCOL0 6 -+#define SPIF0 7 -+ -+#define SPDR0 _SFR_IO8(0x2E) -+ -+/* Reserved [0x2F] */ -+ -+#define ACSR _SFR_IO8(0x30) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACBG 6 -+#define ACD 7 -+ -+#define OCDR _SFR_IO8(0x31) -+#define OCDR7 7 -+#define OCDR6 6 -+#define OCDR5 5 -+#define OCDR4 4 -+#define OCDR3 3 -+#define OCDR2 2 -+#define OCDR1 1 -+#define OCDR0 0 -+ -+/* Reserved [0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define JTRF 4 -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define JTD 7 -+#define IVCE 0 -+#define IVSEL 1 -+#define PUD 4 -+#define BODSE 5 -+#define BODS 6 -+ -+/* Reserved [0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define SIGRD 5 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+/* Reserved [0x38..0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCSR _SFR_MEM8(0x60) -+#define WDE 3 -+#define WDCE 4 -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDP3 5 -+#define WDIE 6 -+#define WDIF 7 -+ -+#define CLKPR _SFR_MEM8(0x61) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+#define CLKPCE 7 -+ -+/* Reserved [0x62..0x63] */ -+ -+#define PRR0 _SFR_MEM8(0x64) -+#define PRADC 0 -+#define PRSPI 2 -+#define PRTIM1 3 -+#define PRUSART0 1 -+#define PRUSART1 4 -+#define PRTIM0 5 -+#define PRTIM2 6 -+#define PRTWI 7 -+ -+/* Reserved [0x65] */ -+ -+#define OSCCAL _SFR_MEM8(0x66) -+#define OSCCAL0 0 -+#define OSCCAL1 1 -+#define OSCCAL2 2 -+#define OSCCAL3 3 -+#define OSCCAL4 4 -+#define OSCCAL5 5 -+#define OSCCAL6 6 -+#define OSCCAL7 7 -+ -+/* Reserved [0x67] */ -+ -+#define PCICR _SFR_MEM8(0x68) -+#define PCIE0 0 -+#define PCIE1 1 -+#define PCIE2 2 -+#define PCIE3 3 -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+#define ISC20 4 -+#define ISC21 5 -+ -+/* Reserved [0x6A] */ -+ -+#define PCMSK0 _SFR_MEM8(0x6B) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6C) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+#define PCINT14 6 -+#define PCINT15 7 -+ -+#define PCMSK2 _SFR_MEM8(0x6D) -+#define PCINT16 0 -+#define PCINT17 1 -+#define PCINT18 2 -+#define PCINT19 3 -+#define PCINT20 4 -+#define PCINT21 5 -+#define PCINT22 6 -+#define PCINT23 7 -+ -+#define TIMSK0 _SFR_MEM8(0x6E) -+#define TOIE0 0 -+#define OCIE0A 1 -+#define OCIE0B 2 -+ -+#define TIMSK1 _SFR_MEM8(0x6F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define ICIE1 5 -+ -+#define TIMSK2 _SFR_MEM8(0x70) -+#define TOIE2 0 -+#define OCIE2A 1 -+#define OCIE2B 2 -+ -+/* Reserved [0x71..0x72] */ -+ -+#define PCMSK3 _SFR_MEM8(0x73) -+#define PCINT24 0 -+#define PCINT25 1 -+#define PCINT26 2 -+#define PCINT27 3 -+#define PCINT28 4 -+#define PCINT29 5 -+#define PCINT30 6 -+#define PCINT31 7 -+ -+/* Reserved [0x74..0x77] */ -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_MEM16(0x78) -+#endif -+#define ADCW _SFR_MEM16(0x78) -+ -+#define ADCL _SFR_MEM8(0x78) -+#define ADCH _SFR_MEM8(0x79) -+ -+#define ADCSRA _SFR_MEM8(0x7A) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADCSRB _SFR_MEM8(0x7B) -+#define ACME 6 -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+ -+#define ADMUX _SFR_MEM8(0x7C) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define MUX4 4 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+/* Reserved [0x7D] */ -+ -+#define DIDR0 _SFR_MEM8(0x7E) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+#define ADC6D 6 -+#define ADC7D 7 -+ -+#define DIDR1 _SFR_MEM8(0x7F) -+#define AIN0D 0 -+#define AIN1D 1 -+ -+#define TCCR1A _SFR_MEM8(0x80) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR1B _SFR_MEM8(0x81) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1C _SFR_MEM8(0x82) -+#define FOC1B 6 -+#define FOC1A 7 -+ -+/* Reserved [0x83] */ -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x84) -+ -+#define TCNT1L _SFR_MEM8(0x84) -+#define TCNT1H _SFR_MEM8(0x85) -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x86) -+ -+#define ICR1L _SFR_MEM8(0x86) -+#define ICR1H _SFR_MEM8(0x87) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_MEM16(0x88) -+ -+#define OCR1AL _SFR_MEM8(0x88) -+#define OCR1AH _SFR_MEM8(0x89) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_MEM16(0x8A) -+ -+#define OCR1BL _SFR_MEM8(0x8A) -+#define OCR1BH _SFR_MEM8(0x8B) -+ -+/* Reserved [0x8C..0xAF] */ -+ -+#define TCCR2A _SFR_MEM8(0xB0) -+#define WGM20 0 -+#define WGM21 1 -+#define COM2B0 4 -+#define COM2B1 5 -+#define COM2A0 6 -+#define COM2A1 7 -+ -+#define TCCR2B _SFR_MEM8(0xB1) -+#define CS20 0 -+#define CS21 1 -+#define CS22 2 -+#define WGM22 3 -+#define FOC2B 6 -+#define FOC2A 7 -+ -+#define TCNT2 _SFR_MEM8(0xB2) -+ -+#define OCR2A _SFR_MEM8(0xB3) -+ -+#define OCR2B _SFR_MEM8(0xB4) -+ -+/* Reserved [0xB5] */ -+ -+#define ASSR _SFR_MEM8(0xB6) -+#define TCR2BUB 0 -+#define TCR2AUB 1 -+#define OCR2BUB 2 -+#define OCR2AUB 3 -+#define TCN2UB 4 -+#define AS2 5 -+#define EXCLK 6 -+ -+/* Reserved [0xB7] */ -+ -+#define TWBR _SFR_MEM8(0xB8) -+ -+#define TWSR _SFR_MEM8(0xB9) -+#define TWPS0 0 -+#define TWPS1 1 -+#define TWS3 3 -+#define TWS4 4 -+#define TWS5 5 -+#define TWS6 6 -+#define TWS7 7 -+ -+#define TWAR _SFR_MEM8(0xBA) -+#define TWGCE 0 -+#define TWA0 1 -+#define TWA1 2 -+#define TWA2 3 -+#define TWA3 4 -+#define TWA4 5 -+#define TWA5 6 -+#define TWA6 7 -+ -+#define TWDR _SFR_MEM8(0xBB) -+ -+#define TWCR _SFR_MEM8(0xBC) -+#define TWIE 0 -+#define TWEN 2 -+#define TWWC 3 -+#define TWSTO 4 -+#define TWSTA 5 -+#define TWEA 6 -+#define TWINT 7 -+ -+#define TWAMR _SFR_MEM8(0xBD) -+#define TWAM0 1 -+#define TWAM1 2 -+#define TWAM2 3 -+#define TWAM3 4 -+#define TWAM4 5 -+#define TWAM5 6 -+#define TWAM6 7 -+ -+/* Reserved [0xBE..0xBF] */ -+ -+#define UCSR0A _SFR_MEM8(0xC0) -+#define MPCM0 0 -+#define U2X0 1 -+#define UPE0 2 -+#define DOR0 3 -+#define FE0 4 -+#define UDRE0 5 -+#define TXC0 6 -+#define RXC0 7 -+ -+#define UCSR0B _SFR_MEM8(0xC1) -+#define TXB80 0 -+#define RXB80 1 -+#define UCSZ02 2 -+#define TXEN0 3 -+#define RXEN0 4 -+#define UDRIE0 5 -+#define TXCIE0 6 -+#define RXCIE0 7 -+ -+#define UCSR0C _SFR_MEM8(0xC2) -+#define UCPOL0 0 -+#define UCSZ00 1 -+#define UCSZ01 2 -+#define USBS0 3 -+#define UPM00 4 -+#define UPM01 5 -+#define UMSEL00 6 -+#define UMSEL01 7 -+ -+/* Reserved [0xC3] */ -+ -+/* Combine UBRR0L and UBRR0H */ -+#define UBRR0 _SFR_MEM16(0xC4) -+ -+#define UBRR0L _SFR_MEM8(0xC4) -+#define UBRR0H _SFR_MEM8(0xC5) -+ -+#define UDR0 _SFR_MEM8(0xC6) -+ -+/* Reserved [0xC7] */ -+ -+#define UCSR1A _SFR_MEM8(0xC8) -+#define MPCM1 0 -+#define U2X1 1 -+#define UPE1 2 -+#define DOR1 3 -+#define FE1 4 -+#define UDRE1 5 -+#define TXC1 6 -+#define RXC1 7 -+ -+#define UCSR1B _SFR_MEM8(0xC9) -+#define TXB81 0 -+#define RXB81 1 -+#define UCSZ12 2 -+#define TXEN1 3 -+#define RXEN1 4 -+#define UDRIE1 5 -+#define TXCIE1 6 -+#define RXCIE1 7 -+ -+#define UCSR1C _SFR_MEM8(0xCA) -+#define UCPOL1 0 -+#define UCSZ10 1 -+#define UCSZ11 2 -+#define USBS1 3 -+#define UPM10 4 -+#define UPM11 5 -+#define UMSEL10 6 -+#define UMSEL11 7 -+ -+/* Reserved [0xCB] */ -+ -+/* Combine UBRR1L and UBRR1H */ -+#define UBRR1 _SFR_MEM16(0xCC) -+ -+#define UBRR1L _SFR_MEM8(0xCC) -+#define UBRR1H _SFR_MEM8(0xCD) -+ -+#define UDR1 _SFR_MEM8(0xCE) -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* External Interrupt Request 2 */ -+#define INT2_vect _VECTOR(3) -+#define INT2_vect_num 3 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(4) -+#define PCINT0_vect_num 4 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(5) -+#define PCINT1_vect_num 5 -+ -+/* Pin Change Interrupt Request 2 */ -+#define PCINT2_vect _VECTOR(6) -+#define PCINT2_vect_num 6 -+ -+/* Pin Change Interrupt Request 3 */ -+#define PCINT3_vect _VECTOR(7) -+#define PCINT3_vect_num 7 -+ -+/* Watchdog Time-out Interrupt */ -+#define WDT_vect _VECTOR(8) -+#define WDT_vect_num 8 -+ -+/* Timer/Counter2 Compare Match A */ -+#define TIMER2_COMPA_vect _VECTOR(9) -+#define TIMER2_COMPA_vect_num 9 -+ -+/* Timer/Counter2 Compare Match B */ -+#define TIMER2_COMPB_vect _VECTOR(10) -+#define TIMER2_COMPB_vect_num 10 -+ -+/* Timer/Counter2 Overflow */ -+#define TIMER2_OVF_vect _VECTOR(11) -+#define TIMER2_OVF_vect_num 11 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(12) -+#define TIMER1_CAPT_vect_num 12 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(13) -+#define TIMER1_COMPA_vect_num 13 -+ -+/* Timer/Counter1 Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(14) -+#define TIMER1_COMPB_vect_num 14 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(15) -+#define TIMER1_OVF_vect_num 15 -+ -+/* Timer/Counter0 Compare Match A */ -+#define TIMER0_COMPA_vect _VECTOR(16) -+#define TIMER0_COMPA_vect_num 16 -+ -+/* Timer/Counter0 Compare Match B */ -+#define TIMER0_COMPB_vect _VECTOR(17) -+#define TIMER0_COMPB_vect_num 17 -+ -+/* Timer/Counter0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(18) -+#define TIMER0_OVF_vect_num 18 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(19) -+#define SPI_STC_vect_num 19 -+ -+/* USART0, Rx Complete */ -+#define USART0_RX_vect _VECTOR(20) -+#define USART0_RX_vect_num 20 -+ -+/* USART0 Data register Empty */ -+#define USART0_UDRE_vect _VECTOR(21) -+#define USART0_UDRE_vect_num 21 -+ -+/* USART0, Tx Complete */ -+#define USART0_TX_vect _VECTOR(22) -+#define USART0_TX_vect_num 22 -+ -+/* Analog Comparator */ -+#define ANALOG_COMP_vect _VECTOR(23) -+#define ANALOG_COMP_vect_num 23 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(24) -+#define ADC_vect_num 24 -+ -+/* EEPROM Ready */ -+#define EE_READY_vect _VECTOR(25) -+#define EE_READY_vect_num 25 -+ -+/* 2-wire Serial Interface */ -+#define TWI_vect _VECTOR(26) -+#define TWI_vect_num 26 -+ -+/* Store Program Memory Read */ -+#define SPM_READY_vect _VECTOR(27) -+#define SPM_READY_vect_num 27 -+ -+/* USART1 RX complete */ -+#define USART1_RX_vect _VECTOR(28) -+#define USART1_RX_vect_num 28 -+ -+/* USART1 Data Register Empty */ -+#define USART1_UDRE_vect _VECTOR(29) -+#define USART1_UDRE_vect_num 29 -+ -+/* USART1 TX complete */ -+#define USART1_TX_vect _VECTOR(30) -+#define USART1_TX_vect_num 30 -+ -+#define _VECTORS_SIZE 124 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 128 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x3FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 1024 -+#define RAMEND 0x04FF -+#define E2START 0 -+#define E2SIZE 512 -+#define E2PAGESIZE 4 -+#define E2END 0x01FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -+#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_JTAGEN (unsigned char)~_BV(6) -+#define FUSE_OCDEN (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x94 -+#define SIGNATURE_2 0x0A -+ -+ -+#endif /* #ifdef _AVR_ATMEGA164PA_H_INCLUDED */ -+ -diff --git a/include/avr/iom165a.h b/include/avr/iom165a.h -new file mode 100644 -index 0000000..6f5f496 ---- /dev/null -+++ b/include/avr/iom165a.h -@@ -0,0 +1,44 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2011 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+#include "iom165.h" -+ -+#ifdef PCIE0 -+ #undef PCIE0 -+ #define PCIE0 4 -+#endif -+ -+#ifdef PCIE1 -+ #undef PCIE1 -+ #define PCIE 5 -+#endif -diff --git a/include/avr/iom165pa.h b/include/avr/iom165pa.h -new file mode 100644 -index 0000000..aabdbe5 ---- /dev/null -+++ b/include/avr/iom165pa.h -@@ -0,0 +1,821 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATMEGA165PA_H_INCLUDED -+#define _AVR_ATMEGA165PA_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iom165pa.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINA _SFR_IO8(0x00) -+#define PINA7 7 -+#define PINA6 6 -+#define PINA5 5 -+#define PINA4 4 -+#define PINA3 3 -+#define PINA2 2 -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x01) -+#define DDRA7 7 -+#define DDRA6 6 -+#define DDRA5 5 -+#define DDRA4 4 -+#define DDRA3 3 -+#define DDRA2 2 -+#define DDRA1 1 -+#define DDRA0 0 -+ -+#define PORTA _SFR_IO8(0x02) -+#define PORTA7 7 -+#define PORTA6 6 -+#define PORTA5 5 -+#define PORTA4 4 -+#define PORTA3 3 -+#define PORTA2 2 -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x06) -+#define PINC7 7 -+#define PINC6 6 -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x07) -+#define DDRC7 7 -+#define DDRC6 6 -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x08) -+#define PORTC7 7 -+#define PORTC6 6 -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PIND _SFR_IO8(0x09) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0A) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x0B) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+#define PINE _SFR_IO8(0x0C) -+#define PINE7 7 -+#define PINE6 6 -+#define PINE5 5 -+#define PINE4 4 -+#define PINE3 3 -+#define PINE2 2 -+#define PINE1 1 -+#define PINE0 0 -+ -+#define DDRE _SFR_IO8(0x0D) -+#define DDRE7 7 -+#define DDRE6 6 -+#define DDRE5 5 -+#define DDRE4 4 -+#define DDRE3 3 -+#define DDRE2 2 -+#define DDRE1 1 -+#define DDRE0 0 -+ -+#define PORTE _SFR_IO8(0x0E) -+#define PORTE7 7 -+#define PORTE6 6 -+#define PORTE5 5 -+#define PORTE4 4 -+#define PORTE3 3 -+#define PORTE2 2 -+#define PORTE1 1 -+#define PORTE0 0 -+ -+#define PINF _SFR_IO8(0x0F) -+#define PINF7 7 -+#define PINF6 6 -+#define PINF5 5 -+#define PINF4 4 -+#define PINF3 3 -+#define PINF2 2 -+#define PINF1 1 -+#define PINF0 0 -+ -+#define DDRF _SFR_IO8(0x10) -+#define DDRF7 7 -+#define DDRF6 6 -+#define DDRF5 5 -+#define DDRF4 4 -+#define DDRF3 3 -+#define DDRF2 2 -+#define DDRF1 1 -+#define DDRF0 0 -+ -+#define PORTF _SFR_IO8(0x11) -+#define PORTF7 7 -+#define PORTF6 6 -+#define PORTF5 5 -+#define PORTF4 4 -+#define PORTF3 3 -+#define PORTF2 2 -+#define PORTF1 1 -+#define PORTF0 0 -+ -+#define PING _SFR_IO8(0x12) -+#define PING5 5 -+#define PING4 4 -+#define PING3 3 -+#define PING2 2 -+#define PING1 1 -+#define PING0 0 -+ -+#define DDRG _SFR_IO8(0x13) -+#define DDRG4 4 -+#define DDRG3 3 -+#define DDRG2 2 -+#define DDRG1 1 -+#define DDRG0 0 -+ -+#define PORTG _SFR_IO8(0x14) -+#define PORTG4 4 -+#define PORTG3 3 -+#define PORTG2 2 -+#define PORTG1 1 -+#define PORTG0 0 -+ -+#define TIFR0 _SFR_IO8(0x15) -+#define TOV0 0 -+#define OCF0A 1 -+ -+#define TIFR1 _SFR_IO8(0x16) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define ICF1 5 -+ -+#define TIFR2 _SFR_IO8(0x17) -+#define TOV2 0 -+#define OCF2A 1 -+ -+/* Reserved [0x18..0x1B] */ -+ -+#define EIFR _SFR_IO8(0x1C) -+#define INTF0 0 -+#define PCIF0 4 -+#define PCIF1 5 -+ -+#define EIMSK _SFR_IO8(0x1D) -+#define INT0 0 -+#define PCIE0 4 -+#define PCIE1 5 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEWE 1 -+#define EEMWE 2 -+#define EERIE 3 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSR310 0 -+#define TSM 7 -+#define PSR2 1 -+ -+#define TCCR0A _SFR_IO8(0x24) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define WGM01 3 -+#define COM0A0 4 -+#define COM0A1 5 -+#define WGM00 6 -+#define FOC0A 7 -+ -+/* Reserved [0x25] */ -+ -+#define TCNT0 _SFR_IO8(0x26) -+ -+#define OCR0A _SFR_IO8(0x27) -+ -+/* Reserved [0x28..0x29] */ -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+/* Reserved [0x2F] */ -+ -+#define ACSR _SFR_IO8(0x30) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACBG 6 -+#define ACD 7 -+ -+#define OCDR _SFR_IO8(0x31) -+#define OCDR7 7 -+#define OCDR6 6 -+#define OCDR5 5 -+#define OCDR4 4 -+#define OCDR3 3 -+#define OCDR2 2 -+#define OCDR1 1 -+#define OCDR0 0 -+ -+/* Reserved [0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define JTRF 4 -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define JTD 7 -+#define IVCE 0 -+#define IVSEL 1 -+#define PUD 4 -+#define BODSE 5 -+#define BODS 6 -+ -+/* Reserved [0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+/* Reserved [0x38..0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCR _SFR_MEM8(0x60) -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDE 3 -+#define WDCE 4 -+ -+#define CLKPR _SFR_MEM8(0x61) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+#define CLKPCE 7 -+ -+/* Reserved [0x62..0x63] */ -+ -+#define PRR _SFR_MEM8(0x64) -+#define PRADC 0 -+#define PRUSART0 1 -+#define PRSPI 2 -+#define PRTIM1 3 -+ -+/* Reserved [0x65] */ -+ -+#define OSCCAL _SFR_MEM8(0x66) -+#define OSCCAL0 0 -+#define OSCCAL1 1 -+#define OSCCAL2 2 -+#define OSCCAL3 3 -+#define OSCCAL4 4 -+#define OSCCAL5 5 -+#define OSCCAL6 6 -+#define OSCCAL7 7 -+ -+/* Reserved [0x67..0x68] */ -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+ -+/* Reserved [0x6A] */ -+ -+#define PCMSK0 _SFR_MEM8(0x6B) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6C) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+#define PCINT14 6 -+#define PCINT15 7 -+ -+/* Reserved [0x6D] */ -+ -+#define TIMSK0 _SFR_MEM8(0x6E) -+#define TOIE0 0 -+#define OCIE0A 1 -+ -+#define TIMSK1 _SFR_MEM8(0x6F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define ICIE1 5 -+ -+#define TIMSK2 _SFR_MEM8(0x70) -+#define TOIE2 0 -+#define OCIE2A 1 -+ -+/* Reserved [0x71..0x77] */ -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_MEM16(0x78) -+#endif -+#define ADCW _SFR_MEM16(0x78) -+ -+#define ADCL _SFR_MEM8(0x78) -+#define ADCH _SFR_MEM8(0x79) -+ -+#define ADCSRA _SFR_MEM8(0x7A) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADCSRB _SFR_MEM8(0x7B) -+#define ACME 6 -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+ -+#define ADMUX _SFR_MEM8(0x7C) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define MUX4 4 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+/* Reserved [0x7D] */ -+ -+#define DIDR0 _SFR_MEM8(0x7E) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+#define ADC6D 6 -+#define ADC7D 7 -+ -+#define DIDR1 _SFR_MEM8(0x7F) -+#define AIN0D 0 -+#define AIN1D 1 -+ -+#define TCCR1A _SFR_MEM8(0x80) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR1B _SFR_MEM8(0x81) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1C _SFR_MEM8(0x82) -+#define FOC1B 6 -+#define FOC1A 7 -+ -+/* Reserved [0x83] */ -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x84) -+ -+#define TCNT1L _SFR_MEM8(0x84) -+#define TCNT1H _SFR_MEM8(0x85) -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x86) -+ -+#define ICR1L _SFR_MEM8(0x86) -+#define ICR1H _SFR_MEM8(0x87) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_MEM16(0x88) -+ -+#define OCR1AL _SFR_MEM8(0x88) -+#define OCR1AH _SFR_MEM8(0x89) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_MEM16(0x8A) -+ -+#define OCR1BL _SFR_MEM8(0x8A) -+#define OCR1BH _SFR_MEM8(0x8B) -+ -+/* Reserved [0x8C..0xAF] */ -+ -+#define TCCR2A _SFR_MEM8(0xB0) -+#define CS20 0 -+#define CS21 1 -+#define CS22 2 -+#define WGM21 3 -+#define COM2A0 4 -+#define COM2A1 5 -+#define WGM20 6 -+#define FOC2A 7 -+ -+/* Reserved [0xB1] */ -+ -+#define TCNT2 _SFR_MEM8(0xB2) -+ -+#define OCR2A _SFR_MEM8(0xB3) -+ -+/* Reserved [0xB4..0xB5] */ -+ -+#define ASSR _SFR_MEM8(0xB6) -+#define TCR2UB 0 -+#define OCR2UB 1 -+#define TCN2UB 2 -+#define AS2 3 -+#define EXCLK 4 -+ -+/* Reserved [0xB7] */ -+ -+#define USICR _SFR_MEM8(0xB8) -+#define USITC 0 -+#define USICLK 1 -+#define USICS0 2 -+#define USICS1 3 -+#define USIWM0 4 -+#define USIWM1 5 -+#define USIOIE 6 -+#define USISIE 7 -+ -+#define USISR _SFR_MEM8(0xB9) -+#define USICNT0 0 -+#define USICNT1 1 -+#define USICNT2 2 -+#define USICNT3 3 -+#define USIDC 4 -+#define USIPF 5 -+#define USIOIF 6 -+#define USISIF 7 -+ -+#define USIDR _SFR_MEM8(0xBA) -+ -+/* Reserved [0xBB..0xBF] */ -+ -+#define UCSR0A _SFR_MEM8(0xC0) -+#define MPCM0 0 -+#define U2X0 1 -+#define UPE0 2 -+#define DOR0 3 -+#define FE0 4 -+#define UDRE0 5 -+#define TXC0 6 -+#define RXC0 7 -+ -+#define UCSR0B _SFR_MEM8(0xC1) -+#define TXB80 0 -+#define RXB80 1 -+#define UCSZ02 2 -+#define TXEN0 3 -+#define RXEN0 4 -+#define UDRIE0 5 -+#define TXCIE0 6 -+#define RXCIE0 7 -+ -+#define UCSR0C _SFR_MEM8(0xC2) -+#define UCPOL0 0 -+#define UCSZ00 1 -+#define UCSZ01 2 -+#define USBS0 3 -+#define UPM00 4 -+#define UPM01 5 -+#define UMSEL0 6 -+ -+/* Reserved [0xC3] */ -+ -+/* Combine UBRR0L and UBRR0H */ -+#define UBRR0 _SFR_MEM16(0xC4) -+ -+#define UBRR0L _SFR_MEM8(0xC4) -+#define UBRR0H _SFR_MEM8(0xC5) -+ -+#define UDR0 _SFR_MEM8(0xC6) -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(2) -+#define PCINT0_vect_num 2 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(3) -+#define PCINT1_vect_num 3 -+ -+/* Timer/Counter2 Compare Match */ -+#define TIMER2_COMP_vect _VECTOR(4) -+#define TIMER2_COMP_vect_num 4 -+ -+/* Timer/Counter2 Overflow */ -+#define TIMER2_OVF_vect _VECTOR(5) -+#define TIMER2_OVF_vect_num 5 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(6) -+#define TIMER1_CAPT_vect_num 6 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(7) -+#define TIMER1_COMPA_vect_num 7 -+ -+/* Timer/Counter Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(8) -+#define TIMER1_COMPB_vect_num 8 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(9) -+#define TIMER1_OVF_vect_num 9 -+ -+/* Timer/Counter0 Compare Match */ -+#define TIMER0_COMP_vect _VECTOR(10) -+#define TIMER0_COMP_vect_num 10 -+ -+/* Timer/Counter0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(11) -+#define TIMER0_OVF_vect_num 11 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(12) -+#define SPI_STC_vect_num 12 -+ -+/* USART0, Rx Complete */ -+#define USART0_RX_vect _VECTOR(13) -+#define USART0_RX_vect_num 13 -+ -+/* USART0 Data register Empty */ -+#define USART0_UDRE_vect _VECTOR(14) -+#define USART0_UDRE_vect_num 14 -+ -+/* USART0, Tx Complete */ -+#define USART0_TX_vect _VECTOR(15) -+#define USART0_TX_vect_num 15 -+ -+/* USI Start Condition */ -+#define USI_START_vect _VECTOR(16) -+#define USI_START_vect_num 16 -+ -+/* USI Overflow */ -+#define USI_OVERFLOW_vect _VECTOR(17) -+#define USI_OVERFLOW_vect_num 17 -+ -+/* Analog Comparator */ -+#define ANALOG_COMP_vect _VECTOR(18) -+#define ANALOG_COMP_vect_num 18 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(19) -+#define ADC_vect_num 19 -+ -+/* EEPROM Ready */ -+#define EE_READY_vect _VECTOR(20) -+#define EE_READY_vect_num 20 -+ -+/* Store Program Memory Read */ -+#define SPM_READY_vect _VECTOR(21) -+#define SPM_READY_vect_num 21 -+ -+#define _VECTORS_SIZE 88 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 128 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x3FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 1024 -+#define RAMEND 0x04FF -+#define E2START 0 -+#define E2SIZE 512 -+#define E2PAGESIZE 4 -+#define E2END 0x01FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -+#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_JTAGEN (unsigned char)~_BV(6) -+#define FUSE_OCDEN (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x94 -+#define SIGNATURE_2 0x07 -+ -+ -+#endif /* #ifdef _AVR_ATMEGA165PA_H_INCLUDED */ -+ -diff --git a/include/avr/iom168a.h b/include/avr/iom168a.h -new file mode 100644 -index 0000000..2527910 ---- /dev/null -+++ b/include/avr/iom168a.h -@@ -0,0 +1,34 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2011 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+#include "iom168.h" -diff --git a/include/avr/iom168pa.h b/include/avr/iom168pa.h -new file mode 100644 -index 0000000..fc440ca ---- /dev/null -+++ b/include/avr/iom168pa.h -@@ -0,0 +1,771 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATMEGA168PA_H_INCLUDED -+#define _AVR_ATMEGA168PA_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iom168pa.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x06) -+#define PINC6 6 -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x07) -+#define DDRC6 6 -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x08) -+#define PORTC6 6 -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PIND _SFR_IO8(0x09) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0A) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x0B) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+/* Reserved [0x0C..0x14] */ -+ -+#define TIFR0 _SFR_IO8(0x15) -+#define TOV0 0 -+#define OCF0A 1 -+#define OCF0B 2 -+ -+#define TIFR1 _SFR_IO8(0x16) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define ICF1 5 -+ -+#define TIFR2 _SFR_IO8(0x17) -+#define TOV2 0 -+#define OCF2A 1 -+#define OCF2B 2 -+ -+/* Reserved [0x18..0x1A] */ -+ -+#define PCIFR _SFR_IO8(0x1B) -+#define PCIF0 0 -+#define PCIF1 1 -+#define PCIF2 2 -+ -+#define EIFR _SFR_IO8(0x1C) -+#define INTF0 0 -+#define INTF1 1 -+ -+#define EIMSK _SFR_IO8(0x1D) -+#define INT0 0 -+#define INT1 1 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEPE 1 -+#define EEMPE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSRSYNC 0 -+#define TSM 7 -+#define PSRASY 1 -+ -+#define TCCR0A _SFR_IO8(0x24) -+#define WGM00 0 -+#define WGM01 1 -+#define COM0B0 4 -+#define COM0B1 5 -+#define COM0A0 6 -+#define COM0A1 7 -+ -+#define TCCR0B _SFR_IO8(0x25) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define WGM02 3 -+#define FOC0B 6 -+#define FOC0A 7 -+ -+#define TCNT0 _SFR_IO8(0x26) -+ -+#define OCR0A _SFR_IO8(0x27) -+ -+#define OCR0B _SFR_IO8(0x28) -+ -+/* Reserved [0x29] */ -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+/* Reserved [0x2F] */ -+ -+#define ACSR _SFR_IO8(0x30) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACBG 6 -+#define ACD 7 -+ -+/* Reserved [0x31..0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define IVCE 0 -+#define IVSEL 1 -+#define PUD 4 -+#define BODSE 5 -+#define BODS 6 -+ -+/* Reserved [0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SELFPRGEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+/* Reserved [0x38..0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCSR _SFR_MEM8(0x60) -+#define WDE 3 -+#define WDCE 4 -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDP3 5 -+#define WDIE 6 -+#define WDIF 7 -+ -+#define CLKPR _SFR_MEM8(0x61) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+#define CLKPCE 7 -+ -+/* Reserved [0x62..0x63] */ -+ -+#define PRR _SFR_MEM8(0x64) -+#define PRADC 0 -+#define PRUSART0 1 -+#define PRSPI 2 -+#define PRTIM1 3 -+#define PRTIM0 5 -+#define PRTIM2 6 -+#define PRTWI 7 -+ -+/* Reserved [0x65] */ -+ -+#define OSCCAL _SFR_MEM8(0x66) -+#define OSCCAL0 0 -+#define OSCCAL1 1 -+#define OSCCAL2 2 -+#define OSCCAL3 3 -+#define OSCCAL4 4 -+#define OSCCAL5 5 -+#define OSCCAL6 6 -+#define OSCCAL7 7 -+ -+/* Reserved [0x67] */ -+ -+#define PCICR _SFR_MEM8(0x68) -+#define PCIE0 0 -+#define PCIE1 1 -+#define PCIE2 2 -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+ -+/* Reserved [0x6A] */ -+ -+#define PCMSK0 _SFR_MEM8(0x6B) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6C) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+#define PCINT14 6 -+ -+#define PCMSK2 _SFR_MEM8(0x6D) -+#define PCINT16 0 -+#define PCINT17 1 -+#define PCINT18 2 -+#define PCINT19 3 -+#define PCINT20 4 -+#define PCINT21 5 -+#define PCINT22 6 -+#define PCINT23 7 -+ -+#define TIMSK0 _SFR_MEM8(0x6E) -+#define TOIE0 0 -+#define OCIE0A 1 -+#define OCIE0B 2 -+ -+#define TIMSK1 _SFR_MEM8(0x6F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define ICIE1 5 -+ -+#define TIMSK2 _SFR_MEM8(0x70) -+#define TOIE2 0 -+#define OCIE2A 1 -+#define OCIE2B 2 -+ -+/* Reserved [0x71..0x77] */ -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_MEM16(0x78) -+#endif -+#define ADCW _SFR_MEM16(0x78) -+ -+#define ADCL _SFR_MEM8(0x78) -+#define ADCH _SFR_MEM8(0x79) -+ -+#define ADCSRA _SFR_MEM8(0x7A) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADCSRB _SFR_MEM8(0x7B) -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+#define ACME 6 -+ -+#define ADMUX _SFR_MEM8(0x7C) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+/* Reserved [0x7D] */ -+ -+#define DIDR0 _SFR_MEM8(0x7E) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+ -+#define DIDR1 _SFR_MEM8(0x7F) -+#define AIN0D 0 -+#define AIN1D 1 -+ -+#define TCCR1A _SFR_MEM8(0x80) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR1B _SFR_MEM8(0x81) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1C _SFR_MEM8(0x82) -+#define FOC1B 6 -+#define FOC1A 7 -+ -+/* Reserved [0x83] */ -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x84) -+ -+#define TCNT1L _SFR_MEM8(0x84) -+#define TCNT1H _SFR_MEM8(0x85) -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x86) -+ -+#define ICR1L _SFR_MEM8(0x86) -+#define ICR1H _SFR_MEM8(0x87) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_MEM16(0x88) -+ -+#define OCR1AL _SFR_MEM8(0x88) -+#define OCR1AH _SFR_MEM8(0x89) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_MEM16(0x8A) -+ -+#define OCR1BL _SFR_MEM8(0x8A) -+#define OCR1BH _SFR_MEM8(0x8B) -+ -+/* Reserved [0x8C..0xAF] */ -+ -+#define TCCR2A _SFR_MEM8(0xB0) -+#define WGM20 0 -+#define WGM21 1 -+#define COM2B0 4 -+#define COM2B1 5 -+#define COM2A0 6 -+#define COM2A1 7 -+ -+#define TCCR2B _SFR_MEM8(0xB1) -+#define CS20 0 -+#define CS21 1 -+#define CS22 2 -+#define WGM22 3 -+#define FOC2B 6 -+#define FOC2A 7 -+ -+#define TCNT2 _SFR_MEM8(0xB2) -+ -+#define OCR2A _SFR_MEM8(0xB3) -+ -+#define OCR2B _SFR_MEM8(0xB4) -+ -+/* Reserved [0xB5] */ -+ -+#define ASSR _SFR_MEM8(0xB6) -+#define TCR2BUB 0 -+#define TCR2AUB 1 -+#define OCR2BUB 2 -+#define OCR2AUB 3 -+#define TCN2UB 4 -+#define AS2 5 -+#define EXCLK 6 -+ -+/* Reserved [0xB7] */ -+ -+#define TWBR _SFR_MEM8(0xB8) -+ -+#define TWSR _SFR_MEM8(0xB9) -+#define TWPS0 0 -+#define TWPS1 1 -+#define TWS3 3 -+#define TWS4 4 -+#define TWS5 5 -+#define TWS6 6 -+#define TWS7 7 -+ -+#define TWAR _SFR_MEM8(0xBA) -+#define TWGCE 0 -+#define TWA0 1 -+#define TWA1 2 -+#define TWA2 3 -+#define TWA3 4 -+#define TWA4 5 -+#define TWA5 6 -+#define TWA6 7 -+ -+#define TWDR _SFR_MEM8(0xBB) -+ -+#define TWCR _SFR_MEM8(0xBC) -+#define TWIE 0 -+#define TWEN 2 -+#define TWWC 3 -+#define TWSTO 4 -+#define TWSTA 5 -+#define TWEA 6 -+#define TWINT 7 -+ -+#define TWAMR _SFR_MEM8(0xBD) -+#define TWAM0 1 -+#define TWAM1 2 -+#define TWAM2 3 -+#define TWAM3 4 -+#define TWAM4 5 -+#define TWAM5 6 -+#define TWAM6 7 -+ -+/* Reserved [0xBE..0xBF] */ -+ -+#define UCSR0A _SFR_MEM8(0xC0) -+#define MPCM0 0 -+#define U2X0 1 -+#define UPE0 2 -+#define DOR0 3 -+#define FE0 4 -+#define UDRE0 5 -+#define TXC0 6 -+#define RXC0 7 -+ -+#define UCSR0B _SFR_MEM8(0xC1) -+#define TXB80 0 -+#define RXB80 1 -+#define UCSZ02 2 -+#define TXEN0 3 -+#define RXEN0 4 -+#define UDRIE0 5 -+#define TXCIE0 6 -+#define RXCIE0 7 -+ -+#define UCSR0C _SFR_MEM8(0xC2) -+#define UCPOL0 0 -+#define UCSZ00 1 -+#define UCSZ01 2 -+#define USBS0 3 -+#define UPM00 4 -+#define UPM01 5 -+#define UMSEL00 6 -+#define UMSEL01 7 -+ -+/* Reserved [0xC3] */ -+ -+/* Combine UBRR0L and UBRR0H */ -+#define UBRR0 _SFR_MEM16(0xC4) -+ -+#define UBRR0L _SFR_MEM8(0xC4) -+#define UBRR0H _SFR_MEM8(0xC5) -+ -+#define UDR0 _SFR_MEM8(0xC6) -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(3) -+#define PCINT0_vect_num 3 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT1_vect _VECTOR(4) -+#define PCINT1_vect_num 4 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT2_vect _VECTOR(5) -+#define PCINT2_vect_num 5 -+ -+/* Watchdog Time-out Interrupt */ -+#define WDT_vect _VECTOR(6) -+#define WDT_vect_num 6 -+ -+/* Timer/Counter2 Compare Match A */ -+#define TIMER2_COMPA_vect _VECTOR(7) -+#define TIMER2_COMPA_vect_num 7 -+ -+/* Timer/Counter2 Compare Match A */ -+#define TIMER2_COMPB_vect _VECTOR(8) -+#define TIMER2_COMPB_vect_num 8 -+ -+/* Timer/Counter2 Overflow */ -+#define TIMER2_OVF_vect _VECTOR(9) -+#define TIMER2_OVF_vect_num 9 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(10) -+#define TIMER1_CAPT_vect_num 10 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(11) -+#define TIMER1_COMPA_vect_num 11 -+ -+/* Timer/Counter1 Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(12) -+#define TIMER1_COMPB_vect_num 12 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(13) -+#define TIMER1_OVF_vect_num 13 -+ -+/* TimerCounter0 Compare Match A */ -+#define TIMER0_COMPA_vect _VECTOR(14) -+#define TIMER0_COMPA_vect_num 14 -+ -+/* TimerCounter0 Compare Match B */ -+#define TIMER0_COMPB_vect _VECTOR(15) -+#define TIMER0_COMPB_vect_num 15 -+ -+/* Timer/Couner0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(16) -+#define TIMER0_OVF_vect_num 16 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(17) -+#define SPI_STC_vect_num 17 -+ -+/* USART Rx Complete */ -+#define USART_RX_vect _VECTOR(18) -+#define USART_RX_vect_num 18 -+ -+/* USART, Data Register Empty */ -+#define USART_UDRE_vect _VECTOR(19) -+#define USART_UDRE_vect_num 19 -+ -+/* USART Tx Complete */ -+#define USART_TX_vect _VECTOR(20) -+#define USART_TX_vect_num 20 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(21) -+#define ADC_vect_num 21 -+ -+/* EEPROM Ready */ -+#define EE_READY_vect _VECTOR(22) -+#define EE_READY_vect_num 22 -+ -+/* Analog Comparator */ -+#define ANALOG_COMP_vect _VECTOR(23) -+#define ANALOG_COMP_vect_num 23 -+ -+/* Two-wire Serial Interface */ -+#define TWI_vect _VECTOR(24) -+#define TWI_vect_num 24 -+ -+/* Store Program Memory Read */ -+#define SPM_Ready_vect _VECTOR(25) -+#define SPM_Ready_vect_num 25 -+ -+#define _VECTORS_SIZE 104 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 128 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x3FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 1024 -+#define RAMEND 0x04FF -+#define E2START 0 -+#define E2SIZE 512 -+#define E2PAGESIZE 4 -+#define E2END 0x01FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -+#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_DWEN (unsigned char)~_BV(6) -+#define FUSE_RSTDISBL (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x94 -+#define SIGNATURE_2 0x0B -+ -+ -+#endif /* #ifdef _AVR_ATMEGA168PA_H_INCLUDED */ -+ -diff --git a/include/avr/iom169a.h b/include/avr/iom169a.h -new file mode 100644 -index 0000000..5154162 ---- /dev/null -+++ b/include/avr/iom169a.h -@@ -0,0 +1,44 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2011 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+#include "iom169.h" -+ -+#ifdef PCIE1 -+ #undef PCIE1 -+ #define PCIE1 5 -+#endif -+ -+#ifdef PCIE0 -+ #undef PCIE0 -+ #define PCIE0 4 -+#endif -diff --git a/include/avr/iom16hvb.h b/include/avr/iom16hvb.h -index fecd6e3..8f8e021 100644 ---- a/include/avr/iom16hvb.h -+++ b/include/avr/iom16hvb.h -@@ -970,10 +970,10 @@ - #define VREF_PIN PINVREF - #define VREF_BIT VREF - --#define VREF_DDR DDRVREFGND --#define VREF_PORT PORTVREFGND --#define VREF_PIN PINVREFGND --#define VREF_BIT VREFGND -+#define VREFGND_DDR DDRVREFGND -+#define VREFGND_PORT PORTVREFGND -+#define VREFGND_PIN PINVREFGND -+#define VREFGND_BIT VREFGND - - #define PI_DDR DDRI - #define PI_PORT PORTI -diff --git a/include/avr/iom16u2.h b/include/avr/iom16u2.h -index 09a2cbc..544f64a 100644 ---- a/include/avr/iom16u2.h -+++ b/include/avr/iom16u2.h -@@ -474,6 +474,12 @@ - #define DIDR1 _SFR_MEM8(0x7F) - #define AIN0D 0 - #define AIN1D 1 -+#define AIN2D 2 -+#define AIN3D 3 -+#define AIN4D 4 -+#define AIN5D 5 -+#define AIN6D 6 -+#define AIN7D 7 - - #define TCCR1A _SFR_MEM8(0x80) - #define WGM10 0 -diff --git a/include/avr/iom16u4.h b/include/avr/iom16u4.h -index 7fafdee..237565d 100644 ---- a/include/avr/iom16u4.h -+++ b/include/avr/iom16u4.h -@@ -866,6 +866,47 @@ - #define OCR3CH6 6 - #define OCR3CH7 7 - -+#define TWBR _SFR_MEM8(0xB8) -+ -+#define TWSR _SFR_MEM8(0xB9) -+#define TWPS0 0 -+#define TWPS1 1 -+#define TWS3 3 -+#define TWS4 4 -+#define TWS5 5 -+#define TWS6 6 -+#define TWS7 7 -+ -+#define TWAR _SFR_MEM8(0xBA) -+#define TWGCE 0 -+#define TWA0 1 -+#define TWA1 2 -+#define TWA2 3 -+#define TWA3 4 -+#define TWA4 5 -+#define TWA5 6 -+#define TWA6 7 -+ -+#define TWDR _SFR_MEM8(0xBB) -+ -+#define TWCR _SFR_MEM8(0xBC) -+#define TWIE 0 -+#define TWEN 2 -+#define TWWC 3 -+#define TWSTO 4 -+#define TWSTA 5 -+#define TWEA 6 -+#define TWINT 7 -+ -+#define TWAMR _SFR_MEM8(0xBD) -+#define TWAM0 1 -+#define TWAM1 2 -+#define TWAM2 3 -+#define TWAM3 4 -+#define TWAM4 5 -+#define TWAM5 6 -+#define TWAM6 7 -+ - #define TCNT4 _SFR_MEM8(0xBE) - #define TC40 0 - #define TC41 1 -@@ -984,6 +1025,10 @@ - #define UMSEL10 6 - #define UMSEL11 7 - -+#define UCSR1D _SFR_MEM8(0xCB) -+#define RTSEN 0 -+#define CTSEN 1 -+ - #define UBRR1 _SFR_MEM16(0xCC) - - #define UBRR1L _SFR_MEM8(0xCC) -diff --git a/include/avr/iom2564rfr2.h b/include/avr/iom2564rfr2.h -new file mode 100644 -index 0000000..b7acdd5 ---- /dev/null -+++ b/include/avr/iom2564rfr2.h -@@ -0,0 +1,2564 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATMEGA2564RFR2_H_INCLUDED -+#define _AVR_ATMEGA2564RFR2_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iom2564rfr2.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINA _SFR_IO8(0x00) -+#define PINA7 7 -+#define PINA6 6 -+#define PINA5 5 -+#define PINA4 4 -+#define PINA3 3 -+#define PINA2 2 -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x01) -+#define DDRA7 7 -+#define DDRA6 6 -+#define DDRA5 5 -+#define DDRA4 4 -+#define DDRA3 3 -+#define DDRA2 2 -+#define DDRA1 1 -+#define DDRA0 0 -+ -+#define PORTA _SFR_IO8(0x02) -+#define PORTA7 7 -+#define PORTA6 6 -+#define PORTA5 5 -+#define PORTA4 4 -+#define PORTA3 3 -+#define PORTA2 2 -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x06) -+#define PINC7 7 -+#define PINC6 6 -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x07) -+#define DDRC7 7 -+#define DDRC6 6 -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x08) -+#define PORTC7 7 -+#define PORTC6 6 -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PIND _SFR_IO8(0x09) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0A) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x0B) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+#define PINE _SFR_IO8(0x0C) -+#define PINE7 7 -+#define PINE6 6 -+#define PINE5 5 -+#define PINE4 4 -+#define PINE3 3 -+#define PINE2 2 -+#define PINE1 1 -+#define PINE0 0 -+ -+#define DDRE _SFR_IO8(0x0D) -+#define DDRE7 7 -+#define DDRE6 6 -+#define DDRE5 5 -+#define DDRE4 4 -+#define DDRE3 3 -+#define DDRE2 2 -+#define DDRE1 1 -+#define DDRE0 0 -+ -+#define PORTE _SFR_IO8(0x0E) -+#define PORTE7 7 -+#define PORTE6 6 -+#define PORTE5 5 -+#define PORTE4 4 -+#define PORTE3 3 -+#define PORTE2 2 -+#define PORTE1 1 -+#define PORTE0 0 -+ -+#define PINF _SFR_IO8(0x0F) -+#define PINF7 7 -+#define PINF6 6 -+#define PINF5 5 -+#define PINF4 4 -+#define PINF3 3 -+#define PINF2 2 -+#define PINF1 1 -+#define PINF0 0 -+ -+#define DDRF _SFR_IO8(0x10) -+#define DDRF7 7 -+#define DDRF6 6 -+#define DDRF5 5 -+#define DDRF4 4 -+#define DDRF3 3 -+#define DDRF2 2 -+#define DDRF1 1 -+#define DDRF0 0 -+ -+#define PORTF _SFR_IO8(0x11) -+#define PORTF7 7 -+#define PORTF6 6 -+#define PORTF5 5 -+#define PORTF4 4 -+#define PORTF3 3 -+#define PORTF2 2 -+#define PORTF1 1 -+#define PORTF0 0 -+ -+#define PING _SFR_IO8(0x12) -+#define PING7 7 -+#define PING6 6 -+#define PING5 5 -+#define PING4 4 -+#define PING3 3 -+#define PING2 2 -+#define PING1 1 -+#define PING0 0 -+ -+#define DDRG _SFR_IO8(0x13) -+#define DDRG7 7 -+#define DDRG6 6 -+#define DDRG5 5 -+#define DDRG4 4 -+#define DDRG3 3 -+#define DDRG2 2 -+#define DDRG1 1 -+#define DDRG0 0 -+ -+#define PORTG _SFR_IO8(0x14) -+#define PORTG7 7 -+#define PORTG6 6 -+#define PORTG5 5 -+#define PORTG4 4 -+#define PORTG3 3 -+#define PORTG2 2 -+#define PORTG1 1 -+#define PORTG0 0 -+ -+#define TIFR0 _SFR_IO8(0x15) -+#define TOV0 0 -+#define OCF0A 1 -+#define OCF0B 2 -+#define Res0 3 -+#define Res1 4 -+#define Res2 5 -+#define Res3 6 -+#define Res4 7 -+ -+#define TIFR1 _SFR_IO8(0x16) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define OCF1C 3 -+#define ICF1 5 -+ -+#define TIFR2 _SFR_IO8(0x17) -+#define TOV2 0 -+#define OCF2A 1 -+#define OCF2B 2 -+ -+#define TIFR3 _SFR_IO8(0x18) -+#define TOV3 0 -+#define OCF3A 1 -+#define OCF3B 2 -+#define OCF3C 3 -+#define ICF3 5 -+ -+#define TIFR4 _SFR_IO8(0x19) -+#define TOV4 0 -+#define OCF4A 1 -+#define OCF4B 2 -+#define OCF4C 3 -+#define ICF4 5 -+ -+#define TIFR5 _SFR_IO8(0x1A) -+#define TOV5 0 -+#define OCF5A 1 -+#define OCF5B 2 -+#define OCF5C 3 -+#define ICF5 5 -+ -+#define PCIFR _SFR_IO8(0x1B) -+#define PCIF0 0 -+#define PCIF1 1 -+#define PCIF2 2 -+ -+#define EIFR _SFR_IO8(0x1C) -+#define INTF0 0 -+#define INTF1 1 -+#define INTF2 2 -+#define INTF3 3 -+#define INTF4 4 -+#define INTF5 5 -+#define INTF6 6 -+#define INTF7 7 -+ -+#define EIMSK _SFR_IO8(0x1D) -+#define INT0 0 -+#define INT1 1 -+#define INT2 2 -+#define INT3 3 -+#define INT4 4 -+#define INT5 5 -+#define INT6 6 -+#define INT7 7 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+#define GPIOR00 0 -+#define GPIOR01 1 -+#define GPIOR02 2 -+#define GPIOR03 3 -+#define GPIOR04 4 -+#define GPIOR05 5 -+#define GPIOR06 6 -+#define GPIOR07 7 -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEPE 1 -+#define EEMPE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSRSYNC 0 -+#define PSRASY 1 -+#define TSM 7 -+ -+#define TCCR0A _SFR_IO8(0x24) -+#define WGM00 0 -+#define WGM01 1 -+#define COM0B0 4 -+#define COM0B1 5 -+#define COM0A0 6 -+#define COM0A1 7 -+ -+#define TCCR0B _SFR_IO8(0x25) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define WGM02 3 -+#define FOC0B 6 -+#define FOC0A 7 -+ -+#define TCNT0 _SFR_IO8(0x26) -+ -+#define OCR0A _SFR_IO8(0x27) -+ -+#define OCR0B _SFR_IO8(0x28) -+ -+/* Reserved [0x29] */ -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+#define GPIOR10 0 -+#define GPIOR11 1 -+#define GPIOR12 2 -+#define GPIOR13 3 -+#define GPIOR14 4 -+#define GPIOR15 5 -+#define GPIOR16 6 -+#define GPIOR17 7 -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+#define GPIOR20 0 -+#define GPIOR21 1 -+#define GPIOR22 2 -+#define GPIOR23 3 -+#define GPIOR24 4 -+#define GPIOR25 5 -+#define GPIOR26 6 -+#define GPIOR27 7 -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+/* Reserved [0x2F] */ -+ -+#define ACSR _SFR_IO8(0x30) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACBG 6 -+#define ACD 7 -+ -+#define OCDR _SFR_IO8(0x31) -+#define OCDR0 0 -+#define OCDR1 1 -+#define OCDR2 2 -+#define OCDR3 3 -+#define OCDR4 4 -+#define OCDR5 5 -+#define OCDR6 6 -+#define OCDR7 7 -+ -+/* Reserved [0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define JTRF 4 -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define JTD 7 -+#define IVCE 0 -+#define IVSEL 1 -+#define PUD 4 -+ -+/* Reserved [0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define SIGRD 5 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+/* Reserved [0x38..0x3A] */ -+ -+#define RAMPZ _SFR_IO8(0x3B) -+#define RAMPZ0 0 -+#define RAMPZ1 1 -+#define Res5 7 -+ -+#define EIND _SFR_IO8(0x3C) -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCSR _SFR_MEM8(0x60) -+#define WDE 3 -+#define WDCE 4 -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDP3 5 -+#define WDIE 6 -+#define WDIF 7 -+ -+#define CLKPR _SFR_MEM8(0x61) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+#define CLKPCE 7 -+ -+/* Reserved [0x62] */ -+ -+#define PRR2 _SFR_MEM8(0x63) -+#define PRRAM0 0 -+#define PRRAM1 1 -+#define PRRAM2 2 -+#define PRRAM3 3 -+ -+#define PRR0 _SFR_MEM8(0x64) -+#define PRADC 0 -+#define PRUSART0 1 -+#define PRSPI 2 -+#define PRTIM1 3 -+#define PRPGA 4 -+#define PRTIM0 5 -+#define PRTIM2 6 -+#define PRTWI 7 -+ -+#define PRR1 _SFR_MEM8(0x65) -+#define PRUSART1 0 -+#define PRTIM3 3 -+#define PRTIM4 4 -+#define PRTIM5 5 -+#define PRTRX24 6 -+#define Res 7 -+ -+#define OSCCAL _SFR_MEM8(0x66) -+#define CAL0 0 -+#define CAL1 1 -+#define CAL2 2 -+#define CAL3 3 -+#define CAL4 4 -+#define CAL5 5 -+#define CAL6 6 -+#define CAL7 7 -+ -+#define BGCR _SFR_MEM8(0x67) -+#define BGCAL0 0 -+#define BGCAL1 1 -+#define BGCAL2 2 -+#define BGCAL_FINE0 3 -+#define BGCAL_FINE1 4 -+#define BGCAL_FINE2 5 -+#define BGCAL_FINE3 6 -+ -+#define PCICR _SFR_MEM8(0x68) -+#define PCIE0 0 -+#define PCIE1 1 -+#define PCIE2 2 -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+#define ISC20 4 -+#define ISC21 5 -+#define ISC30 6 -+#define ISC31 7 -+ -+#define EICRB _SFR_MEM8(0x6A) -+#define ISC40 0 -+#define ISC41 1 -+#define ISC50 2 -+#define ISC51 3 -+#define ISC60 4 -+#define ISC61 5 -+#define ISC70 6 -+#define ISC71 7 -+ -+#define PCMSK0 _SFR_MEM8(0x6B) -+ -+#define PCMSK1 _SFR_MEM8(0x6C) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+#define PCINT14 6 -+#define PCINT15 7 -+ -+#define PCMSK2 _SFR_MEM8(0x6D) -+#define PCINT16 0 -+#define PCINT17 1 -+#define PCINT18 2 -+#define PCINT19 3 -+#define PCINT20 4 -+#define PCINT21 5 -+#define PCINT22 6 -+#define PCINT23 7 -+ -+#define TIMSK0 _SFR_MEM8(0x6E) -+#define TOIE0 0 -+#define OCIE0A 1 -+#define OCIE0B 2 -+ -+#define TIMSK1 _SFR_MEM8(0x6F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define OCIE1C 3 -+#define ICIE1 5 -+ -+#define TIMSK2 _SFR_MEM8(0x70) -+#define TOIE2 0 -+#define OCIE2A 1 -+#define OCIE2B 2 -+ -+#define TIMSK3 _SFR_MEM8(0x71) -+#define TOIE3 0 -+#define OCIE3A 1 -+#define OCIE3B 2 -+#define OCIE3C 3 -+#define ICIE3 5 -+ -+#define TIMSK4 _SFR_MEM8(0x72) -+#define TOIE4 0 -+#define OCIE4A 1 -+#define OCIE4B 2 -+#define OCIE4C 3 -+#define ICIE4 5 -+ -+#define TIMSK5 _SFR_MEM8(0x73) -+#define TOIE5 0 -+#define OCIE5A 1 -+#define OCIE5B 2 -+#define OCIE5C 3 -+#define ICIE5 5 -+ -+/* Reserved [0x74] */ -+ -+#define NEMCR _SFR_MEM8(0x75) -+#define AEAM0 4 -+#define AEAM1 5 -+#define ENEAM 6 -+ -+/* Reserved [0x76] */ -+ -+#define ADCSRC _SFR_MEM8(0x77) -+#define ADSUT0 0 -+#define ADSUT1 1 -+#define ADSUT2 2 -+#define ADSUT3 3 -+#define ADSUT4 4 -+#define ADTHT0 6 -+#define ADTHT1 7 -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_MEM16(0x78) -+#endif -+#define ADCW _SFR_MEM16(0x78) -+ -+#define ADCL _SFR_MEM8(0x78) -+#define ADCH _SFR_MEM8(0x79) -+ -+#define ADCSRA _SFR_MEM8(0x7A) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADCSRB _SFR_MEM8(0x7B) -+#define ACME 6 -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+#define MUX5 3 -+#define ACCH 4 -+#define REFOK 5 -+#define AVDDOK 7 -+ -+#define ADMUX _SFR_MEM8(0x7C) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define MUX4 4 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+#define DIDR2 _SFR_MEM8(0x7D) -+#define ADC8D 0 -+#define ADC9D 1 -+#define ADC10D 2 -+#define ADC11D 3 -+#define ADC12D 4 -+#define ADC13D 5 -+#define ADC14D 6 -+#define ADC15D 7 -+ -+#define DIDR0 _SFR_MEM8(0x7E) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+#define ADC6D 6 -+#define ADC7D 7 -+ -+#define DIDR1 _SFR_MEM8(0x7F) -+#define AIN0D 0 -+#define AIN1D 1 -+ -+#define TCCR1A _SFR_MEM8(0x80) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1C0 2 -+#define COM1C1 3 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR1B _SFR_MEM8(0x81) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1C _SFR_MEM8(0x82) -+#define FOC1C 5 -+#define FOC1B 6 -+#define FOC1A 7 -+ -+/* Reserved [0x83] */ -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x84) -+ -+#define TCNT1L _SFR_MEM8(0x84) -+#define TCNT1H _SFR_MEM8(0x85) -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x86) -+ -+#define ICR1L _SFR_MEM8(0x86) -+#define ICR1H _SFR_MEM8(0x87) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_MEM16(0x88) -+ -+#define OCR1AL _SFR_MEM8(0x88) -+#define OCR1AH _SFR_MEM8(0x89) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_MEM16(0x8A) -+ -+#define OCR1BL _SFR_MEM8(0x8A) -+#define OCR1BH _SFR_MEM8(0x8B) -+ -+/* Combine OCR1CL and OCR1CH */ -+#define OCR1C _SFR_MEM16(0x8C) -+ -+#define OCR1CL _SFR_MEM8(0x8C) -+#define OCR1CH _SFR_MEM8(0x8D) -+ -+/* Reserved [0x8E..0x8F] */ -+ -+#define TCCR3A _SFR_MEM8(0x90) -+#define WGM30 0 -+#define WGM31 1 -+#define COM3C0 2 -+#define COM3C1 3 -+#define COM3B0 4 -+#define COM3B1 5 -+#define COM3A0 6 -+#define COM3A1 7 -+ -+#define TCCR3B _SFR_MEM8(0x91) -+#define CS30 0 -+#define CS31 1 -+#define CS32 2 -+#define WGM32 3 -+#define WGM33 4 -+#define ICES3 6 -+#define ICNC3 7 -+ -+#define TCCR3C _SFR_MEM8(0x92) -+#define FOC3C 5 -+#define FOC3B 6 -+#define FOC3A 7 -+ -+/* Reserved [0x93] */ -+ -+/* Combine TCNT3L and TCNT3H */ -+#define TCNT3 _SFR_MEM16(0x94) -+ -+#define TCNT3L _SFR_MEM8(0x94) -+#define TCNT3H _SFR_MEM8(0x95) -+ -+/* Combine ICR3L and ICR3H */ -+#define ICR3 _SFR_MEM16(0x96) -+ -+#define ICR3L _SFR_MEM8(0x96) -+#define ICR3H _SFR_MEM8(0x97) -+ -+/* Combine OCR3AL and OCR3AH */ -+#define OCR3A _SFR_MEM16(0x98) -+ -+#define OCR3AL _SFR_MEM8(0x98) -+#define OCR3AH _SFR_MEM8(0x99) -+ -+/* Combine OCR3BL and OCR3BH */ -+#define OCR3B _SFR_MEM16(0x9A) -+ -+#define OCR3BL _SFR_MEM8(0x9A) -+#define OCR3BH _SFR_MEM8(0x9B) -+ -+/* Combine OCR3CL and OCR3CH */ -+#define OCR3C _SFR_MEM16(0x9C) -+ -+#define OCR3CL _SFR_MEM8(0x9C) -+#define OCR3CH _SFR_MEM8(0x9D) -+ -+/* Reserved [0x9E..0x9F] */ -+ -+#define TCCR4A _SFR_MEM8(0xA0) -+#define WGM40 0 -+#define WGM41 1 -+#define COM4C0 2 -+#define COM4C1 3 -+#define COM4B0 4 -+#define COM4B1 5 -+#define COM4A0 6 -+#define COM4A1 7 -+ -+#define TCCR4B _SFR_MEM8(0xA1) -+#define CS40 0 -+#define CS41 1 -+#define CS42 2 -+#define WGM42 3 -+#define WGM43 4 -+#define ICES4 6 -+#define ICNC4 7 -+ -+#define TCCR4C _SFR_MEM8(0xA2) -+#define FOC4C 5 -+#define FOC4B 6 -+#define FOC4A 7 -+ -+/* Reserved [0xA3] */ -+ -+/* Combine TCNT4L and TCNT4H */ -+#define TCNT4 _SFR_MEM16(0xA4) -+ -+#define TCNT4L _SFR_MEM8(0xA4) -+#define TCNT4H _SFR_MEM8(0xA5) -+ -+/* Combine ICR4L and ICR4H */ -+#define ICR4 _SFR_MEM16(0xA6) -+ -+#define ICR4L _SFR_MEM8(0xA6) -+#define ICR4H _SFR_MEM8(0xA7) -+ -+/* Combine OCR4AL and OCR4AH */ -+#define OCR4A _SFR_MEM16(0xA8) -+ -+#define OCR4AL _SFR_MEM8(0xA8) -+#define OCR4AH _SFR_MEM8(0xA9) -+ -+/* Combine OCR4BL and OCR4BH */ -+#define OCR4B _SFR_MEM16(0xAA) -+ -+#define OCR4BL _SFR_MEM8(0xAA) -+#define OCR4BH _SFR_MEM8(0xAB) -+ -+/* Combine OCR4CL and OCR4CH */ -+#define OCR4C _SFR_MEM16(0xAC) -+ -+#define OCR4CL _SFR_MEM8(0xAC) -+#define OCR4CH _SFR_MEM8(0xAD) -+ -+/* Reserved [0xAE..0xAF] */ -+ -+#define TCCR2A _SFR_MEM8(0xB0) -+#define WGM20 0 -+#define WGM21 1 -+#define COM2B0 4 -+#define COM2B1 5 -+#define COM2A0 6 -+#define COM2A1 7 -+ -+#define TCCR2B _SFR_MEM8(0xB1) -+#define CS20 0 -+#define CS21 1 -+#define CS22 2 -+#define WGM22 3 -+#define FOC2B 6 -+#define FOC2A 7 -+ -+#define TCNT2 _SFR_MEM8(0xB2) -+ -+#define OCR2A _SFR_MEM8(0xB3) -+ -+#define OCR2B _SFR_MEM8(0xB4) -+ -+/* Reserved [0xB5] */ -+ -+#define ASSR _SFR_MEM8(0xB6) -+#define TCR2BUB 0 -+#define TCR2AUB 1 -+#define OCR2BUB 2 -+#define OCR2AUB 3 -+#define TCN2UB 4 -+#define AS2 5 -+#define EXCLK 6 -+#define EXCLKAMR 7 -+ -+/* Reserved [0xB7] */ -+ -+#define TWBR _SFR_MEM8(0xB8) -+ -+#define TWSR _SFR_MEM8(0xB9) -+#define TWPS0 0 -+#define TWPS1 1 -+#define TWS3 3 -+#define TWS4 4 -+#define TWS5 5 -+#define TWS6 6 -+#define TWS7 7 -+ -+#define TWAR _SFR_MEM8(0xBA) -+#define TWGCE 0 -+#define TWA0 1 -+#define TWA1 2 -+#define TWA2 3 -+#define TWA3 4 -+#define TWA4 5 -+#define TWA5 6 -+#define TWA6 7 -+ -+#define TWDR _SFR_MEM8(0xBB) -+ -+#define TWCR _SFR_MEM8(0xBC) -+#define TWIE 0 -+#define TWEN 2 -+#define TWWC 3 -+#define TWSTO 4 -+#define TWSTA 5 -+#define TWEA 6 -+#define TWINT 7 -+ -+#define TWAMR _SFR_MEM8(0xBD) -+#define TWAM0 1 -+#define TWAM1 2 -+#define TWAM2 3 -+#define TWAM3 4 -+#define TWAM4 5 -+#define TWAM5 6 -+#define TWAM6 7 -+ -+#define IRQ_MASK1 _SFR_MEM8(0xBE) -+#define TX_START_EN 0 -+#define MAF_0_AMI_EN 1 -+#define MAF_1_AMI_EN 2 -+#define MAF_2_AMI_EN 3 -+#define MAF_3_AMI_EN 4 -+ -+#define IRQ_STATUS1 _SFR_MEM8(0xBF) -+#define TX_START 0 -+#define MAF_0_AMI 1 -+#define MAF_1_AMI 2 -+#define MAF_2_AMI 3 -+#define MAF_3_AMI 4 -+ -+#define UCSR0A _SFR_MEM8(0xC0) -+#define MPCM0 0 -+#define U2X0 1 -+#define UPE0 2 -+#define DOR0 3 -+#define FE0 4 -+#define UDRE0 5 -+#define TXC0 6 -+#define RXC0 7 -+ -+#define UCSR0B _SFR_MEM8(0xC1) -+#define TXB80 0 -+#define RXB80 1 -+#define UCSZ02 2 -+#define TXEN0 3 -+#define RXEN0 4 -+#define UDRIE0 5 -+#define TXCIE0 6 -+#define RXCIE0 7 -+ -+#define UCSR0C _SFR_MEM8(0xC2) -+#define UCPOL0 0 -+#define UCSZ00 1 -+#define UCSZ01 2 -+#define USBS0 3 -+#define UPM00 4 -+#define UPM01 5 -+#define UMSEL00 6 -+#define UMSEL01 7 -+#define UCPHA0 1 -+#define UDORD0 2 -+ -+/* Reserved [0xC3] */ -+ -+/* Combine UBRR0L and UBRR0H */ -+#define UBRR0 _SFR_MEM16(0xC4) -+ -+#define UBRR0L _SFR_MEM8(0xC4) -+#define UBRR0H _SFR_MEM8(0xC5) -+ -+#define UDR0 _SFR_MEM8(0xC6) -+ -+/* Reserved [0xC7] */ -+ -+#define UCSR1A _SFR_MEM8(0xC8) -+#define MPCM1 0 -+#define U2X1 1 -+#define UPE1 2 -+#define DOR1 3 -+#define FE1 4 -+#define UDRE1 5 -+#define TXC1 6 -+#define RXC1 7 -+ -+#define UCSR1B _SFR_MEM8(0xC9) -+#define TXB81 0 -+#define RXB81 1 -+#define UCSZ12 2 -+#define TXEN1 3 -+#define RXEN1 4 -+#define UDRIE1 5 -+#define TXCIE1 6 -+#define RXCIE1 7 -+ -+#define UCSR1C _SFR_MEM8(0xCA) -+#define UCPOL1 0 -+#define UCSZ10 1 -+#define UCSZ11 2 -+#define USBS1 3 -+#define UPM10 4 -+#define UPM11 5 -+#define UMSEL10 6 -+#define UMSEL11 7 -+#define UCPHA1 1 -+#define UDORD1 2 -+ -+/* Reserved [0xCB] */ -+ -+/* Combine UBRR1L and UBRR1H */ -+#define UBRR1 _SFR_MEM16(0xCC) -+ -+#define UBRR1L _SFR_MEM8(0xCC) -+#define UBRR1H _SFR_MEM8(0xCD) -+ -+#define UDR1 _SFR_MEM8(0xCE) -+ -+/* Reserved [0xCF..0xD6] */ -+ -+#define SCRSTRLL _SFR_MEM8(0xD7) -+#define SCRSTRLL0 0 -+#define SCRSTRLL1 1 -+#define SCRSTRLL2 2 -+#define SCRSTRLL3 3 -+#define SCRSTRLL4 4 -+#define SCRSTRLL5 5 -+#define SCRSTRLL6 6 -+#define SCRSTRLL7 7 -+ -+#define SCRSTRLH _SFR_MEM8(0xD8) -+#define SCRSTRLH0 0 -+#define SCRSTRLH1 1 -+#define SCRSTRLH2 2 -+#define SCRSTRLH3 3 -+#define SCRSTRLH4 4 -+#define SCRSTRLH5 5 -+#define SCRSTRLH6 6 -+#define SCRSTRLH7 7 -+ -+#define SCRSTRHL _SFR_MEM8(0xD9) -+#define SCRSTRHL0 0 -+#define SCRSTRHL1 1 -+#define SCRSTRHL2 2 -+#define SCRSTRHL3 3 -+#define SCRSTRHL4 4 -+#define SCRSTRHL5 5 -+#define SCRSTRHL6 6 -+#define SCRSTRHL7 7 -+ -+#define SCRSTRHH _SFR_MEM8(0xDA) -+#define SCRSTRHH0 0 -+#define SCRSTRHH1 1 -+#define SCRSTRHH2 2 -+#define SCRSTRHH3 3 -+#define SCRSTRHH4 4 -+#define SCRSTRHH5 5 -+#define SCRSTRHH6 6 -+#define SCRSTRHH7 7 -+ -+#define SCCSR _SFR_MEM8(0xDB) -+#define SCCS10 0 -+#define SCCS11 1 -+#define SCCS20 2 -+#define SCCS21 3 -+#define SCCS30 4 -+#define SCCS31 5 -+ -+#define SCCR0 _SFR_MEM8(0xDC) -+#define SCCMP1 0 -+#define SCCMP2 1 -+#define SCCMP3 2 -+#define SCTSE 3 -+#define SCCKSEL 4 -+#define SCEN 5 -+#define SCMBTS 6 -+#define SCRES 7 -+ -+#define SCCR1 _SFR_MEM8(0xDD) -+#define SCENBO 0 -+#define SCEECLK 1 -+#define SCCKDIV0 2 -+#define SCCKDIV1 3 -+#define SCCKDIV2 4 -+#define SCBTSM 5 -+#define Res6 7 -+ -+#define SCSR _SFR_MEM8(0xDE) -+#define SCBSY 0 -+ -+#define SCIRQM _SFR_MEM8(0xDF) -+#define IRQMCP1 0 -+#define IRQMCP2 1 -+#define IRQMCP3 2 -+#define IRQMOF 3 -+#define IRQMBO 4 -+ -+#define SCIRQS _SFR_MEM8(0xE0) -+#define IRQSCP1 0 -+#define IRQSCP2 1 -+#define IRQSCP3 2 -+#define IRQSOF 3 -+#define IRQSBO 4 -+ -+#define SCCNTLL _SFR_MEM8(0xE1) -+#define SCCNTLL0 0 -+#define SCCNTLL1 1 -+#define SCCNTLL2 2 -+#define SCCNTLL3 3 -+#define SCCNTLL4 4 -+#define SCCNTLL5 5 -+#define SCCNTLL6 6 -+#define SCCNTLL7 7 -+ -+#define SCCNTLH _SFR_MEM8(0xE2) -+#define SCCNTLH0 0 -+#define SCCNTLH1 1 -+#define SCCNTLH2 2 -+#define SCCNTLH3 3 -+#define SCCNTLH4 4 -+#define SCCNTLH5 5 -+#define SCCNTLH6 6 -+#define SCCNTLH7 7 -+ -+#define SCCNTHL _SFR_MEM8(0xE3) -+#define SCCNTHL0 0 -+#define SCCNTHL1 1 -+#define SCCNTHL2 2 -+#define SCCNTHL3 3 -+#define SCCNTHL4 4 -+#define SCCNTHL5 5 -+#define SCCNTHL6 6 -+#define SCCNTHL7 7 -+ -+#define SCCNTHH _SFR_MEM8(0xE4) -+#define SCCNTHH0 0 -+#define SCCNTHH1 1 -+#define SCCNTHH2 2 -+#define SCCNTHH3 3 -+#define SCCNTHH4 4 -+#define SCCNTHH5 5 -+#define SCCNTHH6 6 -+#define SCCNTHH7 7 -+ -+#define SCBTSRLL _SFR_MEM8(0xE5) -+#define SCBTSRLL0 0 -+#define SCBTSRLL1 1 -+#define SCBTSRLL2 2 -+#define SCBTSRLL3 3 -+#define SCBTSRLL4 4 -+#define SCBTSRLL5 5 -+#define SCBTSRLL6 6 -+#define SCBTSRLL7 7 -+ -+#define SCBTSRLH _SFR_MEM8(0xE6) -+#define SCBTSRLH0 0 -+#define SCBTSRLH1 1 -+#define SCBTSRLH2 2 -+#define SCBTSRLH3 3 -+#define SCBTSRLH4 4 -+#define SCBTSRLH5 5 -+#define SCBTSRLH6 6 -+#define SCBTSRLH7 7 -+ -+#define SCBTSRHL _SFR_MEM8(0xE7) -+#define SCBTSRHL0 0 -+#define SCBTSRHL1 1 -+#define SCBTSRHL2 2 -+#define SCBTSRHL3 3 -+#define SCBTSRHL4 4 -+#define SCBTSRHL5 5 -+#define SCBTSRHL6 6 -+#define SCBTSRHL7 7 -+ -+#define SCBTSRHH _SFR_MEM8(0xE8) -+#define SCBTSRHH0 0 -+#define SCBTSRHH1 1 -+#define SCBTSRHH2 2 -+#define SCBTSRHH3 3 -+#define SCBTSRHH4 4 -+#define SCBTSRHH5 5 -+#define SCBTSRHH6 6 -+#define SCBTSRHH7 7 -+ -+#define SCTSRLL _SFR_MEM8(0xE9) -+#define SCTSRLL0 0 -+#define SCTSRLL1 1 -+#define SCTSRLL2 2 -+#define SCTSRLL3 3 -+#define SCTSRLL4 4 -+#define SCTSRLL5 5 -+#define SCTSRLL6 6 -+#define SCTSRLL7 7 -+ -+#define SCTSRLH _SFR_MEM8(0xEA) -+#define SCTSRLH0 0 -+#define SCTSRLH1 1 -+#define SCTSRLH2 2 -+#define SCTSRLH3 3 -+#define SCTSRLH4 4 -+#define SCTSRLH5 5 -+#define SCTSRLH6 6 -+#define SCTSRLH7 7 -+ -+#define SCTSRHL _SFR_MEM8(0xEB) -+#define SCTSRHL0 0 -+#define SCTSRHL1 1 -+#define SCTSRHL2 2 -+#define SCTSRHL3 3 -+#define SCTSRHL4 4 -+#define SCTSRHL5 5 -+#define SCTSRHL6 6 -+#define SCTSRHL7 7 -+ -+#define SCTSRHH _SFR_MEM8(0xEC) -+#define SCTSRHH0 0 -+#define SCTSRHH1 1 -+#define SCTSRHH2 2 -+#define SCTSRHH3 3 -+#define SCTSRHH4 4 -+#define SCTSRHH5 5 -+#define SCTSRHH6 6 -+#define SCTSRHH7 7 -+ -+#define SCOCR3LL _SFR_MEM8(0xED) -+#define SCOCR3LL0 0 -+#define SCOCR3LL1 1 -+#define SCOCR3LL2 2 -+#define SCOCR3LL3 3 -+#define SCOCR3LL4 4 -+#define SCOCR3LL5 5 -+#define SCOCR3LL6 6 -+#define SCOCR3LL7 7 -+ -+#define SCOCR3LH _SFR_MEM8(0xEE) -+#define SCOCR3LH0 0 -+#define SCOCR3LH1 1 -+#define SCOCR3LH2 2 -+#define SCOCR3LH3 3 -+#define SCOCR3LH4 4 -+#define SCOCR3LH5 5 -+#define SCOCR3LH6 6 -+#define SCOCR3LH7 7 -+ -+#define SCOCR3HL _SFR_MEM8(0xEF) -+#define SCOCR3HL0 0 -+#define SCOCR3HL1 1 -+#define SCOCR3HL2 2 -+#define SCOCR3HL3 3 -+#define SCOCR3HL4 4 -+#define SCOCR3HL5 5 -+#define SCOCR3HL6 6 -+#define SCOCR3HL7 7 -+ -+#define SCOCR3HH _SFR_MEM8(0xF0) -+#define SCOCR3HH0 0 -+#define SCOCR3HH1 1 -+#define SCOCR3HH2 2 -+#define SCOCR3HH3 3 -+#define SCOCR3HH4 4 -+#define SCOCR3HH5 5 -+#define SCOCR3HH6 6 -+#define SCOCR3HH7 7 -+ -+#define SCOCR2LL _SFR_MEM8(0xF1) -+#define SCOCR2LL0 0 -+#define SCOCR2LL1 1 -+#define SCOCR2LL2 2 -+#define SCOCR2LL3 3 -+#define SCOCR2LL4 4 -+#define SCOCR2LL5 5 -+#define SCOCR2LL6 6 -+#define SCOCR2LL7 7 -+ -+#define SCOCR2LH _SFR_MEM8(0xF2) -+#define SCOCR2LH0 0 -+#define SCOCR2LH1 1 -+#define SCOCR2LH2 2 -+#define SCOCR2LH3 3 -+#define SCOCR2LH4 4 -+#define SCOCR2LH5 5 -+#define SCOCR2LH6 6 -+#define SCOCR2LH7 7 -+ -+#define SCOCR2HL _SFR_MEM8(0xF3) -+#define SCOCR2HL0 0 -+#define SCOCR2HL1 1 -+#define SCOCR2HL2 2 -+#define SCOCR2HL3 3 -+#define SCOCR2HL4 4 -+#define SCOCR2HL5 5 -+#define SCOCR2HL6 6 -+#define SCOCR2HL7 7 -+ -+#define SCOCR2HH _SFR_MEM8(0xF4) -+#define SCOCR2HH0 0 -+#define SCOCR2HH1 1 -+#define SCOCR2HH2 2 -+#define SCOCR2HH3 3 -+#define SCOCR2HH4 4 -+#define SCOCR2HH5 5 -+#define SCOCR2HH6 6 -+#define SCOCR2HH7 7 -+ -+#define SCOCR1LL _SFR_MEM8(0xF5) -+#define SCOCR1LL0 0 -+#define SCOCR1LL1 1 -+#define SCOCR1LL2 2 -+#define SCOCR1LL3 3 -+#define SCOCR1LL4 4 -+#define SCOCR1LL5 5 -+#define SCOCR1LL6 6 -+#define SCOCR1LL7 7 -+ -+#define SCOCR1LH _SFR_MEM8(0xF6) -+#define SCOCR1LH0 0 -+#define SCOCR1LH1 1 -+#define SCOCR1LH2 2 -+#define SCOCR1LH3 3 -+#define SCOCR1LH4 4 -+#define SCOCR1LH5 5 -+#define SCOCR1LH6 6 -+#define SCOCR1LH7 7 -+ -+#define SCOCR1HL _SFR_MEM8(0xF7) -+#define SCOCR1HL0 0 -+#define SCOCR1HL1 1 -+#define SCOCR1HL2 2 -+#define SCOCR1HL3 3 -+#define SCOCR1HL4 4 -+#define SCOCR1HL5 5 -+#define SCOCR1HL6 6 -+#define SCOCR1HL7 7 -+ -+#define SCOCR1HH _SFR_MEM8(0xF8) -+#define SCOCR1HH0 0 -+#define SCOCR1HH1 1 -+#define SCOCR1HH2 2 -+#define SCOCR1HH3 3 -+#define SCOCR1HH4 4 -+#define SCOCR1HH5 5 -+#define SCOCR1HH6 6 -+#define SCOCR1HH7 7 -+ -+#define SCTSTRLL _SFR_MEM8(0xF9) -+#define SCTSTRLL0 0 -+#define SCTSTRLL1 1 -+#define SCTSTRLL2 2 -+#define SCTSTRLL3 3 -+#define SCTSTRLL4 4 -+#define SCTSTRLL5 5 -+#define SCTSTRLL6 6 -+#define SCTSTRLL7 7 -+ -+#define SCTSTRLH _SFR_MEM8(0xFA) -+#define SCTSTRLH0 0 -+#define SCTSTRLH1 1 -+#define SCTSTRLH2 2 -+#define SCTSTRLH3 3 -+#define SCTSTRLH4 4 -+#define SCTSTRLH5 5 -+#define SCTSTRLH6 6 -+#define SCTSTRLH7 7 -+ -+#define SCTSTRHL _SFR_MEM8(0xFB) -+#define SCTSTRHL0 0 -+#define SCTSTRHL1 1 -+#define SCTSTRHL2 2 -+#define SCTSTRHL3 3 -+#define SCTSTRHL4 4 -+#define SCTSTRHL5 5 -+#define SCTSTRHL6 6 -+#define SCTSTRHL7 7 -+ -+#define SCTSTRHH _SFR_MEM8(0xFC) -+#define SCTSTRHH0 0 -+#define SCTSTRHH1 1 -+#define SCTSTRHH2 2 -+#define SCTSTRHH3 3 -+#define SCTSTRHH4 4 -+#define SCTSTRHH5 5 -+#define SCTSTRHH6 6 -+#define SCTSTRHH7 7 -+ -+/* Reserved [0xFD..0x10B] */ -+ -+#define MAFCR0 _SFR_MEM8(0x10C) -+#define MAF0EN 0 -+#define MAF1EN 1 -+#define MAF2EN 2 -+#define MAF3EN 3 -+ -+#define MAFCR1 _SFR_MEM8(0x10D) -+#define AACK_0_I_AM_COORD 0 -+#define AACK_0_SET_PD 1 -+#define AACK_1_I_AM_COORD 2 -+#define AACK_1_SET_PD 3 -+#define AACK_2_I_AM_COORD 4 -+#define AACK_2_SET_PD 5 -+#define AACK_3_I_AM_COORD 6 -+#define AACK_3_SET_PD 7 -+ -+#define MAFSA0L _SFR_MEM8(0x10E) -+#define MAFSA0L0 0 -+#define MAFSA0L1 1 -+#define MAFSA0L2 2 -+#define MAFSA0L3 3 -+#define MAFSA0L4 4 -+#define MAFSA0L5 5 -+#define MAFSA0L6 6 -+#define MAFSA0L7 7 -+ -+#define MAFSA0H _SFR_MEM8(0x10F) -+#define MAFSA0H0 0 -+#define MAFSA0H1 1 -+#define MAFSA0H2 2 -+#define MAFSA0H3 3 -+#define MAFSA0H4 4 -+#define MAFSA0H5 5 -+#define MAFSA0H6 6 -+#define MAFSA0H7 7 -+ -+#define MAFPA0L _SFR_MEM8(0x110) -+#define MAFPA0L0 0 -+#define MAFPA0L1 1 -+#define MAFPA0L2 2 -+#define MAFPA0L3 3 -+#define MAFPA0L4 4 -+#define MAFPA0L5 5 -+#define MAFPA0L6 6 -+#define MAFPA0L7 7 -+ -+#define MAFPA0H _SFR_MEM8(0x111) -+#define MAFPA0H0 0 -+#define MAFPA0H1 1 -+#define MAFPA0H2 2 -+#define MAFPA0H3 3 -+#define MAFPA0H4 4 -+#define MAFPA0H5 5 -+#define MAFPA0H6 6 -+#define MAFPA0H7 7 -+ -+#define MAFSA1L _SFR_MEM8(0x112) -+#define MAFSA1L0 0 -+#define MAFSA1L1 1 -+#define MAFSA1L2 2 -+#define MAFSA1L3 3 -+#define MAFSA1L4 4 -+#define MAFSA1L5 5 -+#define MAFSA1L6 6 -+#define MAFSA1L7 7 -+ -+#define MAFSA1H _SFR_MEM8(0x113) -+#define MAFSA1H0 0 -+#define MAFSA1H1 1 -+#define MAFSA1H2 2 -+#define MAFSA1H3 3 -+#define MAFSA1H4 4 -+#define MAFSA1H5 5 -+#define MAFSA1H6 6 -+#define MAFSA1H7 7 -+ -+#define MAFPA1L _SFR_MEM8(0x114) -+#define MAFPA1L0 0 -+#define MAFPA1L1 1 -+#define MAFPA1L2 2 -+#define MAFPA1L3 3 -+#define MAFPA1L4 4 -+#define MAFPA1L5 5 -+#define MAFPA1L6 6 -+#define MAFPA1L7 7 -+ -+#define MAFPA1H _SFR_MEM8(0x115) -+#define MAFPA1H0 0 -+#define MAFPA1H1 1 -+#define MAFPA1H2 2 -+#define MAFPA1H3 3 -+#define MAFPA1H4 4 -+#define MAFPA1H5 5 -+#define MAFPA1H6 6 -+#define MAFPA1H7 7 -+ -+#define MAFSA2L _SFR_MEM8(0x116) -+#define MAFSA2L0 0 -+#define MAFSA2L1 1 -+#define MAFSA2L2 2 -+#define MAFSA2L3 3 -+#define MAFSA2L4 4 -+#define MAFSA2L5 5 -+#define MAFSA2L6 6 -+#define MAFSA2L7 7 -+ -+#define MAFSA2H _SFR_MEM8(0x117) -+#define MAFSA2H0 0 -+#define MAFSA2H1 1 -+#define MAFSA2H2 2 -+#define MAFSA2H3 3 -+#define MAFSA2H4 4 -+#define MAFSA2H5 5 -+#define MAFSA2H6 6 -+#define MAFSA2H7 7 -+ -+#define MAFPA2L _SFR_MEM8(0x118) -+#define MAFPA2L0 0 -+#define MAFPA2L1 1 -+#define MAFPA2L2 2 -+#define MAFPA2L3 3 -+#define MAFPA2L4 4 -+#define MAFPA2L5 5 -+#define MAFPA2L6 6 -+#define MAFPA2L7 7 -+ -+#define MAFPA2H _SFR_MEM8(0x119) -+#define MAFPA2H0 0 -+#define MAFPA2H1 1 -+#define MAFPA2H2 2 -+#define MAFPA2H3 3 -+#define MAFPA2H4 4 -+#define MAFPA2H5 5 -+#define MAFPA2H6 6 -+#define MAFPA2H7 7 -+ -+#define MAFSA3L _SFR_MEM8(0x11A) -+#define MAFSA3L0 0 -+#define MAFSA3L1 1 -+#define MAFSA3L2 2 -+#define MAFSA3L3 3 -+#define MAFSA3L4 4 -+#define MAFSA3L5 5 -+#define MAFSA3L6 6 -+#define MAFSA3L7 7 -+ -+#define MAFSA3H _SFR_MEM8(0x11B) -+#define MAFSA3H0 0 -+#define MAFSA3H1 1 -+#define MAFSA3H2 2 -+#define MAFSA3H3 3 -+#define MAFSA3H4 4 -+#define MAFSA3H5 5 -+#define MAFSA3H6 6 -+#define MAFSA3H7 7 -+ -+#define MAFPA3L _SFR_MEM8(0x11C) -+#define MAFPA3L0 0 -+#define MAFPA3L1 1 -+#define MAFPA3L2 2 -+#define MAFPA3L3 3 -+#define MAFPA3L4 4 -+#define MAFPA3L5 5 -+#define MAFPA3L6 6 -+#define MAFPA3L7 7 -+ -+#define MAFPA3H _SFR_MEM8(0x11D) -+#define MAFPA3H0 0 -+#define MAFPA3H1 1 -+#define MAFPA3H2 2 -+#define MAFPA3H3 3 -+#define MAFPA3H4 4 -+#define MAFPA3H5 5 -+#define MAFPA3H6 6 -+#define MAFPA3H7 7 -+ -+/* Reserved [0x11E..0x11F] */ -+ -+#define TCCR5A _SFR_MEM8(0x120) -+#define WGM50 0 -+#define WGM51 1 -+#define COM5C0 2 -+#define COM5C1 3 -+#define COM5B0 4 -+#define COM5B1 5 -+#define COM5A0 6 -+#define COM5A1 7 -+ -+#define TCCR5B _SFR_MEM8(0x121) -+#define CS50 0 -+#define CS51 1 -+#define CS52 2 -+#define WGM52 3 -+#define WGM53 4 -+#define ICES5 6 -+#define ICNC5 7 -+ -+#define TCCR5C _SFR_MEM8(0x122) -+#define FOC5C 5 -+#define FOC5B 6 -+#define FOC5A 7 -+ -+/* Reserved [0x123] */ -+ -+/* Combine TCNT5L and TCNT5H */ -+#define TCNT5 _SFR_MEM16(0x124) -+ -+#define TCNT5L _SFR_MEM8(0x124) -+#define TCNT5H _SFR_MEM8(0x125) -+ -+/* Combine ICR5L and ICR5H */ -+#define ICR5 _SFR_MEM16(0x126) -+ -+#define ICR5L _SFR_MEM8(0x126) -+#define ICR5H _SFR_MEM8(0x127) -+ -+/* Combine OCR5AL and OCR5AH */ -+#define OCR5A _SFR_MEM16(0x128) -+ -+#define OCR5AL _SFR_MEM8(0x128) -+#define OCR5AH _SFR_MEM8(0x129) -+ -+/* Combine OCR5BL and OCR5BH */ -+#define OCR5B _SFR_MEM16(0x12A) -+ -+#define OCR5BL _SFR_MEM8(0x12A) -+#define OCR5BH _SFR_MEM8(0x12B) -+ -+/* Combine OCR5CL and OCR5CH */ -+#define OCR5C _SFR_MEM16(0x12C) -+ -+#define OCR5CL _SFR_MEM8(0x12C) -+#define OCR5CH _SFR_MEM8(0x12D) -+ -+/* Reserved [0x12E] */ -+ -+#define LLCR _SFR_MEM8(0x12F) -+#define LLENCAL 0 -+#define LLSHORT 1 -+#define LLTCO 2 -+#define LLCAL 3 -+#define LLCOMP 4 -+#define LLDONE 5 -+ -+#define LLDRL _SFR_MEM8(0x130) -+#define LLDRL0 0 -+#define LLDRL1 1 -+#define LLDRL2 2 -+#define LLDRL3 3 -+ -+#define LLDRH _SFR_MEM8(0x131) -+#define LLDRH0 0 -+#define LLDRH1 1 -+#define LLDRH2 2 -+#define LLDRH3 3 -+#define LLDRH4 4 -+ -+#define DRTRAM3 _SFR_MEM8(0x132) -+#define ENDRT 4 -+#define DRTSWOK 5 -+ -+#define DRTRAM2 _SFR_MEM8(0x133) -+ -+#define DRTRAM1 _SFR_MEM8(0x134) -+ -+#define DRTRAM0 _SFR_MEM8(0x135) -+ -+#define DPDS0 _SFR_MEM8(0x136) -+#define PBDRV0 0 -+#define PBDRV1 1 -+#define PDDRV0 2 -+#define PDDRV1 3 -+#define PEDRV0 4 -+#define PEDRV1 5 -+#define PFDRV0 6 -+#define PFDRV1 7 -+ -+#define DPDS1 _SFR_MEM8(0x137) -+#define PGDRV0 0 -+#define PGDRV1 1 -+ -+#define PARCR _SFR_MEM8(0x138) -+#define PARUFI 0 -+#define PARDFI 1 -+#define PALTU0 2 -+#define PALTU1 3 -+#define PALTU2 4 -+#define PALTD0 5 -+#define PALTD1 6 -+#define PALTD2 7 -+ -+#define TRXPR _SFR_MEM8(0x139) -+#define TRXRST 0 -+#define SLPTR 1 -+ -+/* Reserved [0x13A..0x13B] */ -+ -+#define AES_CTRL _SFR_MEM8(0x13C) -+#define AES_IM 2 -+#define AES_DIR 3 -+#define AES_MODE 5 -+#define AES_REQUEST 7 -+ -+#define AES_STATUS _SFR_MEM8(0x13D) -+#define AES_DONE 0 -+#define AES_ER 7 -+ -+#define AES_STATE _SFR_MEM8(0x13E) -+#define AES_STATE0 0 -+#define AES_STATE1 1 -+#define AES_STATE2 2 -+#define AES_STATE3 3 -+#define AES_STATE4 4 -+#define AES_STATE5 5 -+#define AES_STATE6 6 -+#define AES_STATE7 7 -+ -+#define AES_KEY _SFR_MEM8(0x13F) -+#define AES_KEY0 0 -+#define AES_KEY1 1 -+#define AES_KEY2 2 -+#define AES_KEY3 3 -+#define AES_KEY4 4 -+#define AES_KEY5 5 -+#define AES_KEY6 6 -+#define AES_KEY7 7 -+ -+/* Reserved [0x140] */ -+ -+#define TRX_STATUS _SFR_MEM8(0x141) -+#define TRX_STATUS0 0 -+#define TRX_STATUS1 1 -+#define TRX_STATUS2 2 -+#define TRX_STATUS3 3 -+#define TRX_STATUS4 4 -+#define TST_STATUS 5 -+#define CCA_STATUS 6 -+#define CCA_DONE 7 -+ -+#define TRX_STATE _SFR_MEM8(0x142) -+#define TRX_CMD0 0 -+#define TRX_CMD1 1 -+#define TRX_CMD2 2 -+#define TRX_CMD3 3 -+#define TRX_CMD4 4 -+#define TRAC_STATUS0 5 -+#define TRAC_STATUS1 6 -+#define TRAC_STATUS2 7 -+ -+#define TRX_CTRL_0 _SFR_MEM8(0x143) -+#define PMU_IF_INV 4 -+#define PMU_START 5 -+#define PMU_EN 6 -+#define Res7 7 -+ -+#define TRX_CTRL_1 _SFR_MEM8(0x144) -+#define PLL_TX_FLT 4 -+#define TX_AUTO_CRC_ON 5 -+#define IRQ_2_EXT_EN 6 -+#define PA_EXT_EN 7 -+ -+#define PHY_TX_PWR _SFR_MEM8(0x145) -+#define TX_PWR0 0 -+#define TX_PWR1 1 -+#define TX_PWR2 2 -+#define TX_PWR3 3 -+ -+#define PHY_RSSI _SFR_MEM8(0x146) -+#define RSSI0 0 -+#define RSSI1 1 -+#define RSSI2 2 -+#define RSSI3 3 -+#define RSSI4 4 -+#define RND_VALUE0 5 -+#define RND_VALUE1 6 -+#define RX_CRC_VALID 7 -+ -+#define PHY_ED_LEVEL _SFR_MEM8(0x147) -+#define ED_LEVEL0 0 -+#define ED_LEVEL1 1 -+#define ED_LEVEL2 2 -+#define ED_LEVEL3 3 -+#define ED_LEVEL4 4 -+#define ED_LEVEL5 5 -+#define ED_LEVEL6 6 -+#define ED_LEVEL7 7 -+ -+#define PHY_CC_CCA _SFR_MEM8(0x148) -+#define CHANNEL0 0 -+#define CHANNEL1 1 -+#define CHANNEL2 2 -+#define CHANNEL3 3 -+#define CHANNEL4 4 -+#define CCA_MODE0 5 -+#define CCA_MODE1 6 -+#define CCA_REQUEST 7 -+ -+#define CCA_THRES _SFR_MEM8(0x149) -+#define CCA_ED_THRES0 0 -+#define CCA_ED_THRES1 1 -+#define CCA_ED_THRES2 2 -+#define CCA_ED_THRES3 3 -+#define CCA_CS_THRES0 4 -+#define CCA_CS_THRES1 5 -+#define CCA_CS_THRES2 6 -+#define CCA_CS_THRES3 7 -+ -+#define RX_CTRL _SFR_MEM8(0x14A) -+#define PDT_THRES0 0 -+#define PDT_THRES1 1 -+#define PDT_THRES2 2 -+#define PDT_THRES3 3 -+ -+#define SFD_VALUE _SFR_MEM8(0x14B) -+#define SFD_VALUE0 0 -+#define SFD_VALUE1 1 -+#define SFD_VALUE2 2 -+#define SFD_VALUE3 3 -+#define SFD_VALUE4 4 -+#define SFD_VALUE5 5 -+#define SFD_VALUE6 6 -+#define SFD_VALUE7 7 -+ -+#define TRX_CTRL_2 _SFR_MEM8(0x14C) -+#define OQPSK_DATA_RATE0 0 -+#define OQPSK_DATA_RATE1 1 -+#define RX_SAFE_MODE 7 -+ -+#define ANT_DIV _SFR_MEM8(0x14D) -+#define ANT_CTRL0 0 -+#define ANT_CTRL1 1 -+#define ANT_EXT_SW_EN 2 -+#define ANT_DIV_EN 3 -+#define ANT_SEL 7 -+ -+#define IRQ_MASK _SFR_MEM8(0x14E) -+#define PLL_LOCK_EN 0 -+#define PLL_UNLOCK_EN 1 -+#define RX_START_EN 2 -+#define RX_END_EN 3 -+#define CCA_ED_DONE_EN 4 -+#define AMI_EN 5 -+#define TX_END_EN 6 -+#define AWAKE_EN 7 -+ -+#define IRQ_STATUS _SFR_MEM8(0x14F) -+#define PLL_LOCK 0 -+#define PLL_UNLOCK 1 -+#define RX_START 2 -+#define RX_END 3 -+#define CCA_ED_DONE 4 -+#define AMI 5 -+#define TX_END 6 -+#define AWAKE 7 -+ -+#define VREG_CTRL _SFR_MEM8(0x150) -+#define DVDD_OK 2 -+#define DVREG_EXT 3 -+#define AVDD_OK 6 -+#define AVREG_EXT 7 -+ -+#define BATMON _SFR_MEM8(0x151) -+#define BATMON_VTH0 0 -+#define BATMON_VTH1 1 -+#define BATMON_VTH2 2 -+#define BATMON_VTH3 3 -+#define BATMON_HR 4 -+#define BATMON_OK 5 -+#define BAT_LOW_EN 6 -+#define BAT_LOW 7 -+ -+#define XOSC_CTRL _SFR_MEM8(0x152) -+#define XTAL_TRIM0 0 -+#define XTAL_TRIM1 1 -+#define XTAL_TRIM2 2 -+#define XTAL_TRIM3 3 -+#define XTAL_MODE0 4 -+#define XTAL_MODE1 5 -+#define XTAL_MODE2 6 -+#define XTAL_MODE3 7 -+ -+#define CC_CTRL_0 _SFR_MEM8(0x153) -+#define CC_NUMBER0 0 -+#define CC_NUMBER1 1 -+#define CC_NUMBER2 2 -+#define CC_NUMBER3 3 -+#define CC_NUMBER4 4 -+#define CC_NUMBER5 5 -+#define CC_NUMBER6 6 -+#define CC_NUMBER7 7 -+ -+#define CC_CTRL_1 _SFR_MEM8(0x154) -+#define CC_BAND0 0 -+#define CC_BAND1 1 -+#define CC_BAND2 2 -+#define CC_BAND3 3 -+ -+#define RX_SYN _SFR_MEM8(0x155) -+#define RX_PDT_LEVEL0 0 -+#define RX_PDT_LEVEL1 1 -+#define RX_PDT_LEVEL2 2 -+#define RX_PDT_LEVEL3 3 -+#define RX_OVERRIDE 6 -+#define RX_PDT_DIS 7 -+ -+#define TRX_RPC _SFR_MEM8(0x156) -+#define XAH_RPC_EN 0 -+#define IPAN_RPC_EN 1 -+#define PLL_RPC_EN 3 -+#define PDT_RPC_EN 4 -+#define RX_RPC_EN 5 -+#define RX_RPC_CTRL0 6 -+#define RX_RPC_CTRL1 7 -+ -+#define XAH_CTRL_1 _SFR_MEM8(0x157) -+#define AACK_PROM_MODE 1 -+#define AACK_ACK_TIME 2 -+#define AACK_UPLD_RES_FT 4 -+#define AACK_FLTR_RES_FT 5 -+ -+#define FTN_CTRL _SFR_MEM8(0x158) -+#define FTN_START 7 -+ -+/* Reserved [0x159] */ -+ -+#define PLL_CF _SFR_MEM8(0x15A) -+#define PLL_CF_START 7 -+ -+#define PLL_DCU _SFR_MEM8(0x15B) -+#define PLL_DCU_START 7 -+ -+#define PART_NUM _SFR_MEM8(0x15C) -+#define PART_NUM0 0 -+#define PART_NUM1 1 -+#define PART_NUM2 2 -+#define PART_NUM3 3 -+#define PART_NUM4 4 -+#define PART_NUM5 5 -+#define PART_NUM6 6 -+#define PART_NUM7 7 -+ -+#define VERSION_NUM _SFR_MEM8(0x15D) -+#define VERSION_NUM0 0 -+#define VERSION_NUM1 1 -+#define VERSION_NUM2 2 -+#define VERSION_NUM3 3 -+#define VERSION_NUM4 4 -+#define VERSION_NUM5 5 -+#define VERSION_NUM6 6 -+#define VERSION_NUM7 7 -+ -+#define MAN_ID_0 _SFR_MEM8(0x15E) -+#define MAN_ID_00 0 -+#define MAN_ID_01 1 -+#define MAN_ID_02 2 -+#define MAN_ID_03 3 -+#define MAN_ID_04 4 -+#define MAN_ID_05 5 -+#define MAN_ID_06 6 -+#define MAN_ID_07 7 -+ -+#define MAN_ID_1 _SFR_MEM8(0x15F) -+#define MAN_ID_10 0 -+#define MAN_ID_11 1 -+#define MAN_ID_12 2 -+#define MAN_ID_13 3 -+#define MAN_ID_14 4 -+#define MAN_ID_15 5 -+#define MAN_ID_16 6 -+#define MAN_ID_17 7 -+ -+#define SHORT_ADDR_0 _SFR_MEM8(0x160) -+#define SHORT_ADDR_00 0 -+#define SHORT_ADDR_01 1 -+#define SHORT_ADDR_02 2 -+#define SHORT_ADDR_03 3 -+#define SHORT_ADDR_04 4 -+#define SHORT_ADDR_05 5 -+#define SHORT_ADDR_06 6 -+#define SHORT_ADDR_07 7 -+ -+#define SHORT_ADDR_1 _SFR_MEM8(0x161) -+#define SHORT_ADDR_10 0 -+#define SHORT_ADDR_11 1 -+#define SHORT_ADDR_12 2 -+#define SHORT_ADDR_13 3 -+#define SHORT_ADDR_14 4 -+#define SHORT_ADDR_15 5 -+#define SHORT_ADDR_16 6 -+#define SHORT_ADDR_17 7 -+ -+#define PAN_ID_0 _SFR_MEM8(0x162) -+#define PAN_ID_00 0 -+#define PAN_ID_01 1 -+#define PAN_ID_02 2 -+#define PAN_ID_03 3 -+#define PAN_ID_04 4 -+#define PAN_ID_05 5 -+#define PAN_ID_06 6 -+#define PAN_ID_07 7 -+ -+#define PAN_ID_1 _SFR_MEM8(0x163) -+#define PAN_ID_10 0 -+#define PAN_ID_11 1 -+#define PAN_ID_12 2 -+#define PAN_ID_13 3 -+#define PAN_ID_14 4 -+#define PAN_ID_15 5 -+#define PAN_ID_16 6 -+#define PAN_ID_17 7 -+ -+#define IEEE_ADDR_0 _SFR_MEM8(0x164) -+#define IEEE_ADDR_00 0 -+#define IEEE_ADDR_01 1 -+#define IEEE_ADDR_02 2 -+#define IEEE_ADDR_03 3 -+#define IEEE_ADDR_04 4 -+#define IEEE_ADDR_05 5 -+#define IEEE_ADDR_06 6 -+#define IEEE_ADDR_07 7 -+ -+#define IEEE_ADDR_1 _SFR_MEM8(0x165) -+#define IEEE_ADDR_10 0 -+#define IEEE_ADDR_11 1 -+#define IEEE_ADDR_12 2 -+#define IEEE_ADDR_13 3 -+#define IEEE_ADDR_14 4 -+#define IEEE_ADDR_15 5 -+#define IEEE_ADDR_16 6 -+#define IEEE_ADDR_17 7 -+ -+#define IEEE_ADDR_2 _SFR_MEM8(0x166) -+#define IEEE_ADDR_20 0 -+#define IEEE_ADDR_21 1 -+#define IEEE_ADDR_22 2 -+#define IEEE_ADDR_23 3 -+#define IEEE_ADDR_24 4 -+#define IEEE_ADDR_25 5 -+#define IEEE_ADDR_26 6 -+#define IEEE_ADDR_27 7 -+ -+#define IEEE_ADDR_3 _SFR_MEM8(0x167) -+#define IEEE_ADDR_30 0 -+#define IEEE_ADDR_31 1 -+#define IEEE_ADDR_32 2 -+#define IEEE_ADDR_33 3 -+#define IEEE_ADDR_34 4 -+#define IEEE_ADDR_35 5 -+#define IEEE_ADDR_36 6 -+#define IEEE_ADDR_37 7 -+ -+#define IEEE_ADDR_4 _SFR_MEM8(0x168) -+#define IEEE_ADDR_40 0 -+#define IEEE_ADDR_41 1 -+#define IEEE_ADDR_42 2 -+#define IEEE_ADDR_43 3 -+#define IEEE_ADDR_44 4 -+#define IEEE_ADDR_45 5 -+#define IEEE_ADDR_46 6 -+#define IEEE_ADDR_47 7 -+ -+#define IEEE_ADDR_5 _SFR_MEM8(0x169) -+#define IEEE_ADDR_50 0 -+#define IEEE_ADDR_51 1 -+#define IEEE_ADDR_52 2 -+#define IEEE_ADDR_53 3 -+#define IEEE_ADDR_54 4 -+#define IEEE_ADDR_55 5 -+#define IEEE_ADDR_56 6 -+#define IEEE_ADDR_57 7 -+ -+#define IEEE_ADDR_6 _SFR_MEM8(0x16A) -+#define IEEE_ADDR_60 0 -+#define IEEE_ADDR_61 1 -+#define IEEE_ADDR_62 2 -+#define IEEE_ADDR_63 3 -+#define IEEE_ADDR_64 4 -+#define IEEE_ADDR_65 5 -+#define IEEE_ADDR_66 6 -+#define IEEE_ADDR_67 7 -+ -+#define IEEE_ADDR_7 _SFR_MEM8(0x16B) -+#define IEEE_ADDR_70 0 -+#define IEEE_ADDR_71 1 -+#define IEEE_ADDR_72 2 -+#define IEEE_ADDR_73 3 -+#define IEEE_ADDR_74 4 -+#define IEEE_ADDR_75 5 -+#define IEEE_ADDR_76 6 -+#define IEEE_ADDR_77 7 -+ -+#define XAH_CTRL_0 _SFR_MEM8(0x16C) -+#define SLOTTED_OPERATION 0 -+#define MAX_CSMA_RETRIES0 1 -+#define MAX_CSMA_RETRIES1 2 -+#define MAX_CSMA_RETRIES2 3 -+#define MAX_FRAME_RETRIES0 4 -+#define MAX_FRAME_RETRIES1 5 -+#define MAX_FRAME_RETRIES2 6 -+#define MAX_FRAME_RETRIES3 7 -+ -+#define CSMA_SEED_0 _SFR_MEM8(0x16D) -+#define CSMA_SEED_00 0 -+#define CSMA_SEED_01 1 -+#define CSMA_SEED_02 2 -+#define CSMA_SEED_03 3 -+#define CSMA_SEED_04 4 -+#define CSMA_SEED_05 5 -+#define CSMA_SEED_06 6 -+#define CSMA_SEED_07 7 -+ -+#define CSMA_SEED_1 _SFR_MEM8(0x16E) -+#define CSMA_SEED_10 0 -+#define CSMA_SEED_11 1 -+#define CSMA_SEED_12 2 -+#define AACK_I_AM_COORD 3 -+#define AACK_DIS_ACK 4 -+#define AACK_SET_PD 5 -+#define AACK_FVN_MODE0 6 -+#define AACK_FVN_MODE1 7 -+ -+#define CSMA_BE _SFR_MEM8(0x16F) -+#define MIN_BE0 0 -+#define MIN_BE1 1 -+#define MIN_BE2 2 -+#define MIN_BE3 3 -+#define MAX_BE0 4 -+#define MAX_BE1 5 -+#define MAX_BE2 6 -+#define MAX_BE3 7 -+ -+/* Reserved [0x170..0x175] */ -+ -+#define TST_CTRL_DIGI _SFR_MEM8(0x176) -+#define TST_CTRL_DIG0 0 -+#define TST_CTRL_DIG1 1 -+#define TST_CTRL_DIG2 2 -+#define TST_CTRL_DIG3 3 -+ -+/* Reserved [0x177..0x17A] */ -+ -+#define TST_RX_LENGTH _SFR_MEM8(0x17B) -+#define RX_LENGTH0 0 -+#define RX_LENGTH1 1 -+#define RX_LENGTH2 2 -+#define RX_LENGTH3 3 -+#define RX_LENGTH4 4 -+#define RX_LENGTH5 5 -+#define RX_LENGTH6 6 -+#define RX_LENGTH7 7 -+ -+/* Reserved [0x17C..0x17F] */ -+ -+#define TRXFBST _SFR_MEM8(0x180) -+ -+/* Reserved [0x181..0x1FE] */ -+ -+#define TRXFBEND _SFR_MEM8(0x1FF) -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* External Interrupt Request 2 */ -+#define INT2_vect _VECTOR(3) -+#define INT2_vect_num 3 -+ -+/* External Interrupt Request 3 */ -+#define INT3_vect _VECTOR(4) -+#define INT3_vect_num 4 -+ -+/* External Interrupt Request 4 */ -+#define INT4_vect _VECTOR(5) -+#define INT4_vect_num 5 -+ -+/* External Interrupt Request 5 */ -+#define INT5_vect _VECTOR(6) -+#define INT5_vect_num 6 -+ -+/* External Interrupt Request 6 */ -+#define INT6_vect _VECTOR(7) -+#define INT6_vect_num 7 -+ -+/* External Interrupt Request 7 */ -+#define INT7_vect _VECTOR(8) -+#define INT7_vect_num 8 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(9) -+#define PCINT0_vect_num 9 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(10) -+#define PCINT1_vect_num 10 -+ -+/* Pin Change Interrupt Request 2 */ -+#define PCINT2_vect _VECTOR(11) -+#define PCINT2_vect_num 11 -+ -+/* Watchdog Time-out Interrupt */ -+#define WDT_vect _VECTOR(12) -+#define WDT_vect_num 12 -+ -+/* Timer/Counter2 Compare Match A */ -+#define TIMER2_COMPA_vect _VECTOR(13) -+#define TIMER2_COMPA_vect_num 13 -+ -+/* Timer/Counter2 Compare Match B */ -+#define TIMER2_COMPB_vect _VECTOR(14) -+#define TIMER2_COMPB_vect_num 14 -+ -+/* Timer/Counter2 Overflow */ -+#define TIMER2_OVF_vect _VECTOR(15) -+#define TIMER2_OVF_vect_num 15 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(16) -+#define TIMER1_CAPT_vect_num 16 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(17) -+#define TIMER1_COMPA_vect_num 17 -+ -+/* Timer/Counter1 Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(18) -+#define TIMER1_COMPB_vect_num 18 -+ -+/* Timer/Counter1 Compare Match C */ -+#define TIMER1_COMPC_vect _VECTOR(19) -+#define TIMER1_COMPC_vect_num 19 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(20) -+#define TIMER1_OVF_vect_num 20 -+ -+/* Timer/Counter0 Compare Match A */ -+#define TIMER0_COMPA_vect _VECTOR(21) -+#define TIMER0_COMPA_vect_num 21 -+ -+/* Timer/Counter0 Compare Match B */ -+#define TIMER0_COMPB_vect _VECTOR(22) -+#define TIMER0_COMPB_vect_num 22 -+ -+/* Timer/Counter0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(23) -+#define TIMER0_OVF_vect_num 23 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(24) -+#define SPI_STC_vect_num 24 -+ -+/* USART0, Rx Complete */ -+#define USART0_RX_vect _VECTOR(25) -+#define USART0_RX_vect_num 25 -+ -+/* USART0 Data register Empty */ -+#define USART0_UDRE_vect _VECTOR(26) -+#define USART0_UDRE_vect_num 26 -+ -+/* USART0, Tx Complete */ -+#define USART0_TX_vect _VECTOR(27) -+#define USART0_TX_vect_num 27 -+ -+/* Analog Comparator */ -+#define ANALOG_COMP_vect _VECTOR(28) -+#define ANALOG_COMP_vect_num 28 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(29) -+#define ADC_vect_num 29 -+ -+/* EEPROM Ready */ -+#define EE_READY_vect _VECTOR(30) -+#define EE_READY_vect_num 30 -+ -+/* Timer/Counter3 Capture Event */ -+#define TIMER3_CAPT_vect _VECTOR(31) -+#define TIMER3_CAPT_vect_num 31 -+ -+/* Timer/Counter3 Compare Match A */ -+#define TIMER3_COMPA_vect _VECTOR(32) -+#define TIMER3_COMPA_vect_num 32 -+ -+/* Timer/Counter3 Compare Match B */ -+#define TIMER3_COMPB_vect _VECTOR(33) -+#define TIMER3_COMPB_vect_num 33 -+ -+/* Timer/Counter3 Compare Match C */ -+#define TIMER3_COMPC_vect _VECTOR(34) -+#define TIMER3_COMPC_vect_num 34 -+ -+/* Timer/Counter3 Overflow */ -+#define TIMER3_OVF_vect _VECTOR(35) -+#define TIMER3_OVF_vect_num 35 -+ -+/* USART1, Rx Complete */ -+#define USART1_RX_vect _VECTOR(36) -+#define USART1_RX_vect_num 36 -+ -+/* USART1 Data register Empty */ -+#define USART1_UDRE_vect _VECTOR(37) -+#define USART1_UDRE_vect_num 37 -+ -+/* USART1, Tx Complete */ -+#define USART1_TX_vect _VECTOR(38) -+#define USART1_TX_vect_num 38 -+ -+/* 2-wire Serial Interface */ -+#define TWI_vect _VECTOR(39) -+#define TWI_vect_num 39 -+ -+/* Store Program Memory Read */ -+#define SPM_READY_vect _VECTOR(40) -+#define SPM_READY_vect_num 40 -+ -+/* Timer/Counter4 Capture Event */ -+#define TIMER4_CAPT_vect _VECTOR(41) -+#define TIMER4_CAPT_vect_num 41 -+ -+/* Timer/Counter4 Compare Match A */ -+#define TIMER4_COMPA_vect _VECTOR(42) -+#define TIMER4_COMPA_vect_num 42 -+ -+/* Timer/Counter4 Compare Match B */ -+#define TIMER4_COMPB_vect _VECTOR(43) -+#define TIMER4_COMPB_vect_num 43 -+ -+/* Timer/Counter4 Compare Match C */ -+#define TIMER4_COMPC_vect _VECTOR(44) -+#define TIMER4_COMPC_vect_num 44 -+ -+/* Timer/Counter4 Overflow */ -+#define TIMER4_OVF_vect _VECTOR(45) -+#define TIMER4_OVF_vect_num 45 -+ -+/* Timer/Counter5 Capture Event */ -+#define TIMER5_CAPT_vect _VECTOR(46) -+#define TIMER5_CAPT_vect_num 46 -+ -+/* Timer/Counter5 Compare Match A */ -+#define TIMER5_COMPA_vect _VECTOR(47) -+#define TIMER5_COMPA_vect_num 47 -+ -+/* Timer/Counter5 Compare Match B */ -+#define TIMER5_COMPB_vect _VECTOR(48) -+#define TIMER5_COMPB_vect_num 48 -+ -+/* Timer/Counter5 Compare Match C */ -+#define TIMER5_COMPC_vect _VECTOR(49) -+#define TIMER5_COMPC_vect_num 49 -+ -+/* Timer/Counter5 Overflow */ -+#define TIMER5_OVF_vect _VECTOR(50) -+#define TIMER5_OVF_vect_num 50 -+ -+/* USART2, Rx Complete */ -+#define USART2_RX_vect _VECTOR(51) -+#define USART2_RX_vect_num 51 -+ -+/* USART2 Data register Empty */ -+#define USART2_UDRE_vect _VECTOR(52) -+#define USART2_UDRE_vect_num 52 -+ -+/* USART2, Tx Complete */ -+#define USART2_TX_vect _VECTOR(53) -+#define USART2_TX_vect_num 53 -+ -+/* USART3, Rx Complete */ -+#define USART3_RX_vect _VECTOR(54) -+#define USART3_RX_vect_num 54 -+ -+/* USART3 Data register Empty */ -+#define USART3_UDRE_vect _VECTOR(55) -+#define USART3_UDRE_vect_num 55 -+ -+/* USART3, Tx Complete */ -+#define USART3_TX_vect _VECTOR(56) -+#define USART3_TX_vect_num 56 -+ -+/* TRX24 - PLL lock interrupt */ -+#define TRX24_PLL_LOCK_vect _VECTOR(57) -+#define TRX24_PLL_LOCK_vect_num 57 -+ -+/* TRX24 - PLL unlock interrupt */ -+#define TRX24_PLL_UNLOCK_vect _VECTOR(58) -+#define TRX24_PLL_UNLOCK_vect_num 58 -+ -+/* TRX24 - Receive start interrupt */ -+#define TRX24_RX_START_vect _VECTOR(59) -+#define TRX24_RX_START_vect_num 59 -+ -+/* TRX24 - RX_END interrupt */ -+#define TRX24_RX_END_vect _VECTOR(60) -+#define TRX24_RX_END_vect_num 60 -+ -+/* TRX24 - CCA/ED done interrupt */ -+#define TRX24_CCA_ED_DONE_vect _VECTOR(61) -+#define TRX24_CCA_ED_DONE_vect_num 61 -+ -+/* TRX24 - XAH - AMI */ -+#define TRX24_XAH_AMI_vect _VECTOR(62) -+#define TRX24_XAH_AMI_vect_num 62 -+ -+/* TRX24 - TX_END interrupt */ -+#define TRX24_TX_END_vect _VECTOR(63) -+#define TRX24_TX_END_vect_num 63 -+ -+/* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */ -+#define TRX24_AWAKE_vect _VECTOR(64) -+#define TRX24_AWAKE_vect_num 64 -+ -+/* Symbol counter - compare match 1 interrupt */ -+#define SCNT_CMP1_vect _VECTOR(65) -+#define SCNT_CMP1_vect_num 65 -+ -+/* Symbol counter - compare match 2 interrupt */ -+#define SCNT_CMP2_vect _VECTOR(66) -+#define SCNT_CMP2_vect_num 66 -+ -+/* Symbol counter - compare match 3 interrupt */ -+#define SCNT_CMP3_vect _VECTOR(67) -+#define SCNT_CMP3_vect_num 67 -+ -+/* Symbol counter - overflow interrupt */ -+#define SCNT_OVFL_vect _VECTOR(68) -+#define SCNT_OVFL_vect_num 68 -+ -+/* Symbol counter - backoff interrupt */ -+#define SCNT_BACKOFF_vect _VECTOR(69) -+#define SCNT_BACKOFF_vect_num 69 -+ -+/* AES engine ready interrupt */ -+#define AES_READY_vect _VECTOR(70) -+#define AES_READY_vect_num 70 -+ -+/* Battery monitor indicates supply voltage below threshold */ -+#define BAT_LOW_vect _VECTOR(71) -+#define BAT_LOW_vect_num 71 -+ -+/* TRX24 TX start interrupt */ -+#define TRX24_TX_START_vect _VECTOR(72) -+#define TRX24_TX_START_vect_num 72 -+ -+/* Address match interrupt of address filter 0 */ -+#define TRX24_AMI0_vect _VECTOR(73) -+#define TRX24_AMI0_vect_num 73 -+ -+/* Address match interrupt of address filter 1 */ -+#define TRX24_AMI1_vect _VECTOR(74) -+#define TRX24_AMI1_vect_num 74 -+ -+/* Address match interrupt of address filter 2 */ -+#define TRX24_AMI2_vect _VECTOR(75) -+#define TRX24_AMI2_vect_num 75 -+ -+/* Address match interrupt of address filter 3 */ -+#define TRX24_AMI3_vect _VECTOR(76) -+#define TRX24_AMI3_vect_num 76 -+ -+#define _VECTORS_SIZE 308 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 256 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x3FFFF -+#define RAMSTART 0x0200 -+#define RAMSIZE 32768 -+#define RAMEND 0x81FF -+#define E2START 0 -+#define E2SIZE 8192 -+#define E2PAGESIZE 8 -+#define E2END 0x1FFF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_CKSEL_SUT0 (unsigned char)~_BV(0) -+#define FUSE_CKSEL_SUT1 (unsigned char)~_BV(1) -+#define FUSE_CKSEL_SUT2 (unsigned char)~_BV(2) -+#define FUSE_CKSEL_SUT3 (unsigned char)~_BV(3) -+#define FUSE_CKSEL_SUT4 (unsigned char)~_BV(4) -+#define FUSE_CKSEL_SUT5 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_JTAGEN (unsigned char)~_BV(6) -+#define FUSE_OCDEN (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0xA8 -+#define SIGNATURE_2 0x03 -+ -+ -+#endif /* #ifdef _AVR_ATMEGA2564RFR2_H_INCLUDED */ -+ -diff --git a/include/avr/iom256rfr2.h b/include/avr/iom256rfr2.h -new file mode 100644 -index 0000000..a28ce7c ---- /dev/null -+++ b/include/avr/iom256rfr2.h -@@ -0,0 +1,2580 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATMEGA256RFR2_H_INCLUDED -+#define _AVR_ATMEGA256RFR2_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iom256rfr2.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINA _SFR_IO8(0x00) -+#define PINA7 7 -+#define PINA6 6 -+#define PINA5 5 -+#define PINA4 4 -+#define PINA3 3 -+#define PINA2 2 -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x01) -+#define DDRA7 7 -+#define DDRA6 6 -+#define DDRA5 5 -+#define DDRA4 4 -+#define DDRA3 3 -+#define DDRA2 2 -+#define DDRA1 1 -+#define DDRA0 0 -+ -+#define PORTA _SFR_IO8(0x02) -+#define PORTA7 7 -+#define PORTA6 6 -+#define PORTA5 5 -+#define PORTA4 4 -+#define PORTA3 3 -+#define PORTA2 2 -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x06) -+#define PINC7 7 -+#define PINC6 6 -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x07) -+#define DDRC7 7 -+#define DDRC6 6 -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x08) -+#define PORTC7 7 -+#define PORTC6 6 -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PIND _SFR_IO8(0x09) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0A) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x0B) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+#define PINE _SFR_IO8(0x0C) -+#define PINE7 7 -+#define PINE6 6 -+#define PINE5 5 -+#define PINE4 4 -+#define PINE3 3 -+#define PINE2 2 -+#define PINE1 1 -+#define PINE0 0 -+ -+#define DDRE _SFR_IO8(0x0D) -+#define DDRE7 7 -+#define DDRE6 6 -+#define DDRE5 5 -+#define DDRE4 4 -+#define DDRE3 3 -+#define DDRE2 2 -+#define DDRE1 1 -+#define DDRE0 0 -+ -+#define PORTE _SFR_IO8(0x0E) -+#define PORTE7 7 -+#define PORTE6 6 -+#define PORTE5 5 -+#define PORTE4 4 -+#define PORTE3 3 -+#define PORTE2 2 -+#define PORTE1 1 -+#define PORTE0 0 -+ -+#define PINF _SFR_IO8(0x0F) -+#define PINF7 7 -+#define PINF6 6 -+#define PINF5 5 -+#define PINF4 4 -+#define PINF3 3 -+#define PINF2 2 -+#define PINF1 1 -+#define PINF0 0 -+ -+#define DDRF _SFR_IO8(0x10) -+#define DDRF7 7 -+#define DDRF6 6 -+#define DDRF5 5 -+#define DDRF4 4 -+#define DDRF3 3 -+#define DDRF2 2 -+#define DDRF1 1 -+#define DDRF0 0 -+ -+#define PORTF _SFR_IO8(0x11) -+#define PORTF7 7 -+#define PORTF6 6 -+#define PORTF5 5 -+#define PORTF4 4 -+#define PORTF3 3 -+#define PORTF2 2 -+#define PORTF1 1 -+#define PORTF0 0 -+ -+#define PING _SFR_IO8(0x12) -+#define PING7 7 -+#define PING6 6 -+#define PING5 5 -+#define PING4 4 -+#define PING3 3 -+#define PING2 2 -+#define PING1 1 -+#define PING0 0 -+ -+#define DDRG _SFR_IO8(0x13) -+#define DDRG7 7 -+#define DDRG6 6 -+#define DDRG5 5 -+#define DDRG4 4 -+#define DDRG3 3 -+#define DDRG2 2 -+#define DDRG1 1 -+#define DDRG0 0 -+ -+#define PORTG _SFR_IO8(0x14) -+#define PORTG7 7 -+#define PORTG6 6 -+#define PORTG5 5 -+#define PORTG4 4 -+#define PORTG3 3 -+#define PORTG2 2 -+#define PORTG1 1 -+#define PORTG0 0 -+ -+#define TIFR0 _SFR_IO8(0x15) -+#define TOV0 0 -+#define OCF0A 1 -+#define OCF0B 2 -+#define Res0 3 -+#define Res1 4 -+#define Res2 5 -+#define Res3 6 -+#define Res4 7 -+ -+#define TIFR1 _SFR_IO8(0x16) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define OCF1C 3 -+#define ICF1 5 -+ -+#define TIFR2 _SFR_IO8(0x17) -+#define TOV2 0 -+#define OCF2A 1 -+#define OCF2B 2 -+ -+#define TIFR3 _SFR_IO8(0x18) -+#define TOV3 0 -+#define OCF3A 1 -+#define OCF3B 2 -+#define OCF3C 3 -+#define ICF3 5 -+ -+#define TIFR4 _SFR_IO8(0x19) -+#define TOV4 0 -+#define OCF4A 1 -+#define OCF4B 2 -+#define OCF4C 3 -+#define ICF4 5 -+ -+#define TIFR5 _SFR_IO8(0x1A) -+#define TOV5 0 -+#define OCF5A 1 -+#define OCF5B 2 -+#define OCF5C 3 -+#define ICF5 5 -+ -+#define PCIFR _SFR_IO8(0x1B) -+#define PCIF0 0 -+#define PCIF1 1 -+#define PCIF2 2 -+ -+#define EIFR _SFR_IO8(0x1C) -+#define INTF0 0 -+#define INTF1 1 -+#define INTF2 2 -+#define INTF3 3 -+#define INTF4 4 -+#define INTF5 5 -+#define INTF6 6 -+#define INTF7 7 -+ -+#define EIMSK _SFR_IO8(0x1D) -+#define INT0 0 -+#define INT1 1 -+#define INT2 2 -+#define INT3 3 -+#define INT4 4 -+#define INT5 5 -+#define INT6 6 -+#define INT7 7 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+#define GPIOR00 0 -+#define GPIOR01 1 -+#define GPIOR02 2 -+#define GPIOR03 3 -+#define GPIOR04 4 -+#define GPIOR05 5 -+#define GPIOR06 6 -+#define GPIOR07 7 -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEPE 1 -+#define EEMPE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSRSYNC 0 -+#define PSRASY 1 -+#define TSM 7 -+ -+#define TCCR0A _SFR_IO8(0x24) -+#define WGM00 0 -+#define WGM01 1 -+#define COM0B0 4 -+#define COM0B1 5 -+#define COM0A0 6 -+#define COM0A1 7 -+ -+#define TCCR0B _SFR_IO8(0x25) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define WGM02 3 -+#define FOC0B 6 -+#define FOC0A 7 -+ -+#define TCNT0 _SFR_IO8(0x26) -+ -+#define OCR0A _SFR_IO8(0x27) -+ -+#define OCR0B _SFR_IO8(0x28) -+ -+/* Reserved [0x29] */ -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+#define GPIOR10 0 -+#define GPIOR11 1 -+#define GPIOR12 2 -+#define GPIOR13 3 -+#define GPIOR14 4 -+#define GPIOR15 5 -+#define GPIOR16 6 -+#define GPIOR17 7 -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+#define GPIOR20 0 -+#define GPIOR21 1 -+#define GPIOR22 2 -+#define GPIOR23 3 -+#define GPIOR24 4 -+#define GPIOR25 5 -+#define GPIOR26 6 -+#define GPIOR27 7 -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+/* Reserved [0x2F] */ -+ -+#define ACSR _SFR_IO8(0x30) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACBG 6 -+#define ACD 7 -+ -+#define OCDR _SFR_IO8(0x31) -+#define OCDR0 0 -+#define OCDR1 1 -+#define OCDR2 2 -+#define OCDR3 3 -+#define OCDR4 4 -+#define OCDR5 5 -+#define OCDR6 6 -+#define OCDR7 7 -+ -+/* Reserved [0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define JTRF 4 -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define JTD 7 -+#define IVCE 0 -+#define IVSEL 1 -+#define PUD 4 -+ -+/* Reserved [0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define SIGRD 5 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+/* Reserved [0x38..0x3A] */ -+ -+#define RAMPZ _SFR_IO8(0x3B) -+#define RAMPZ0 0 -+#define RAMPZ1 1 -+#define Res5 7 -+ -+#define EIND _SFR_IO8(0x3C) -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCSR _SFR_MEM8(0x60) -+#define WDE 3 -+#define WDCE 4 -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDP3 5 -+#define WDIE 6 -+#define WDIF 7 -+ -+#define CLKPR _SFR_MEM8(0x61) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+#define CLKPCE 7 -+ -+/* Reserved [0x62] */ -+ -+#define PRR2 _SFR_MEM8(0x63) -+#define PRRAM0 0 -+#define PRRAM1 1 -+#define PRRAM2 2 -+#define PRRAM3 3 -+ -+#define PRR0 _SFR_MEM8(0x64) -+#define PRADC 0 -+#define PRUSART0 1 -+#define PRSPI 2 -+#define PRTIM1 3 -+#define PRPGA 4 -+#define PRTIM0 5 -+#define PRTIM2 6 -+#define PRTWI 7 -+ -+#define PRR1 _SFR_MEM8(0x65) -+#define PRUSART1 0 -+#define PRTIM3 3 -+#define PRTIM4 4 -+#define PRTIM5 5 -+#define PRTRX24 6 -+#define Res 7 -+ -+#define OSCCAL _SFR_MEM8(0x66) -+#define CAL0 0 -+#define CAL1 1 -+#define CAL2 2 -+#define CAL3 3 -+#define CAL4 4 -+#define CAL5 5 -+#define CAL6 6 -+#define CAL7 7 -+#define OSCCAL0 0 -+#define OSCCAL1 1 -+#define OSCCAL2 2 -+#define OSCCAL3 3 -+#define OSCCAL4 4 -+#define OSCCAL5 5 -+#define OSCCAL6 6 -+#define OSCCAL7 7 -+ -+#define BGCR _SFR_MEM8(0x67) -+#define BGCAL0 0 -+#define BGCAL1 1 -+#define BGCAL2 2 -+#define BGCAL_FINE0 3 -+#define BGCAL_FINE1 4 -+#define BGCAL_FINE2 5 -+#define BGCAL_FINE3 6 -+ -+#define PCICR _SFR_MEM8(0x68) -+#define PCIE0 0 -+#define PCIE1 1 -+#define PCIE2 2 -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+#define ISC20 4 -+#define ISC21 5 -+#define ISC30 6 -+#define ISC31 7 -+ -+#define EICRB _SFR_MEM8(0x6A) -+#define ISC40 0 -+#define ISC41 1 -+#define ISC50 2 -+#define ISC51 3 -+#define ISC60 4 -+#define ISC61 5 -+#define ISC70 6 -+#define ISC71 7 -+ -+#define PCMSK0 _SFR_MEM8(0x6B) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6C) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+#define PCINT14 6 -+#define PCINT15 7 -+ -+#define PCMSK2 _SFR_MEM8(0x6D) -+#define PCINT16 0 -+#define PCINT17 1 -+#define PCINT18 2 -+#define PCINT19 3 -+#define PCINT20 4 -+#define PCINT21 5 -+#define PCINT22 6 -+#define PCINT23 7 -+ -+#define TIMSK0 _SFR_MEM8(0x6E) -+#define TOIE0 0 -+#define OCIE0A 1 -+#define OCIE0B 2 -+ -+#define TIMSK1 _SFR_MEM8(0x6F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define OCIE1C 3 -+#define ICIE1 5 -+ -+#define TIMSK2 _SFR_MEM8(0x70) -+#define TOIE2 0 -+#define OCIE2A 1 -+#define OCIE2B 2 -+ -+#define TIMSK3 _SFR_MEM8(0x71) -+#define TOIE3 0 -+#define OCIE3A 1 -+#define OCIE3B 2 -+#define OCIE3C 3 -+#define ICIE3 5 -+ -+#define TIMSK4 _SFR_MEM8(0x72) -+#define TOIE4 0 -+#define OCIE4A 1 -+#define OCIE4B 2 -+#define OCIE4C 3 -+#define ICIE4 5 -+ -+#define TIMSK5 _SFR_MEM8(0x73) -+#define TOIE5 0 -+#define OCIE5A 1 -+#define OCIE5B 2 -+#define OCIE5C 3 -+#define ICIE5 5 -+ -+/* Reserved [0x74] */ -+ -+#define NEMCR _SFR_MEM8(0x75) -+#define AEAM0 4 -+#define AEAM1 5 -+#define ENEAM 6 -+ -+/* Reserved [0x76] */ -+ -+#define ADCSRC _SFR_MEM8(0x77) -+#define ADSUT0 0 -+#define ADSUT1 1 -+#define ADSUT2 2 -+#define ADSUT3 3 -+#define ADSUT4 4 -+#define ADTHT0 6 -+#define ADTHT1 7 -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_MEM16(0x78) -+#endif -+#define ADCW _SFR_MEM16(0x78) -+ -+#define ADCL _SFR_MEM8(0x78) -+#define ADCH _SFR_MEM8(0x79) -+ -+#define ADCSRA _SFR_MEM8(0x7A) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADCSRB _SFR_MEM8(0x7B) -+#define ACME 6 -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+#define MUX5 3 -+#define ACCH 4 -+#define REFOK 5 -+#define AVDDOK 7 -+ -+#define ADMUX _SFR_MEM8(0x7C) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define MUX4 4 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+#define DIDR2 _SFR_MEM8(0x7D) -+#define ADC8D 0 -+#define ADC9D 1 -+#define ADC10D 2 -+#define ADC11D 3 -+#define ADC12D 4 -+#define ADC13D 5 -+#define ADC14D 6 -+#define ADC15D 7 -+ -+#define DIDR0 _SFR_MEM8(0x7E) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+#define ADC6D 6 -+#define ADC7D 7 -+ -+#define DIDR1 _SFR_MEM8(0x7F) -+#define AIN0D 0 -+#define AIN1D 1 -+ -+#define TCCR1A _SFR_MEM8(0x80) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1C0 2 -+#define COM1C1 3 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR1B _SFR_MEM8(0x81) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1C _SFR_MEM8(0x82) -+#define FOC1C 5 -+#define FOC1B 6 -+#define FOC1A 7 -+ -+/* Reserved [0x83] */ -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x84) -+ -+#define TCNT1L _SFR_MEM8(0x84) -+#define TCNT1H _SFR_MEM8(0x85) -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x86) -+ -+#define ICR1L _SFR_MEM8(0x86) -+#define ICR1H _SFR_MEM8(0x87) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_MEM16(0x88) -+ -+#define OCR1AL _SFR_MEM8(0x88) -+#define OCR1AH _SFR_MEM8(0x89) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_MEM16(0x8A) -+ -+#define OCR1BL _SFR_MEM8(0x8A) -+#define OCR1BH _SFR_MEM8(0x8B) -+ -+/* Combine OCR1CL and OCR1CH */ -+#define OCR1C _SFR_MEM16(0x8C) -+ -+#define OCR1CL _SFR_MEM8(0x8C) -+#define OCR1CH _SFR_MEM8(0x8D) -+ -+/* Reserved [0x8E..0x8F] */ -+ -+#define TCCR3A _SFR_MEM8(0x90) -+#define WGM30 0 -+#define WGM31 1 -+#define COM3C0 2 -+#define COM3C1 3 -+#define COM3B0 4 -+#define COM3B1 5 -+#define COM3A0 6 -+#define COM3A1 7 -+ -+#define TCCR3B _SFR_MEM8(0x91) -+#define CS30 0 -+#define CS31 1 -+#define CS32 2 -+#define WGM32 3 -+#define WGM33 4 -+#define ICES3 6 -+#define ICNC3 7 -+ -+#define TCCR3C _SFR_MEM8(0x92) -+#define FOC3C 5 -+#define FOC3B 6 -+#define FOC3A 7 -+ -+/* Reserved [0x93] */ -+ -+/* Combine TCNT3L and TCNT3H */ -+#define TCNT3 _SFR_MEM16(0x94) -+ -+#define TCNT3L _SFR_MEM8(0x94) -+#define TCNT3H _SFR_MEM8(0x95) -+ -+/* Combine ICR3L and ICR3H */ -+#define ICR3 _SFR_MEM16(0x96) -+ -+#define ICR3L _SFR_MEM8(0x96) -+#define ICR3H _SFR_MEM8(0x97) -+ -+/* Combine OCR3AL and OCR3AH */ -+#define OCR3A _SFR_MEM16(0x98) -+ -+#define OCR3AL _SFR_MEM8(0x98) -+#define OCR3AH _SFR_MEM8(0x99) -+ -+/* Combine OCR3BL and OCR3BH */ -+#define OCR3B _SFR_MEM16(0x9A) -+ -+#define OCR3BL _SFR_MEM8(0x9A) -+#define OCR3BH _SFR_MEM8(0x9B) -+ -+/* Combine OCR3CL and OCR3CH */ -+#define OCR3C _SFR_MEM16(0x9C) -+ -+#define OCR3CL _SFR_MEM8(0x9C) -+#define OCR3CH _SFR_MEM8(0x9D) -+ -+/* Reserved [0x9E..0x9F] */ -+ -+#define TCCR4A _SFR_MEM8(0xA0) -+#define WGM40 0 -+#define WGM41 1 -+#define COM4C0 2 -+#define COM4C1 3 -+#define COM4B0 4 -+#define COM4B1 5 -+#define COM4A0 6 -+#define COM4A1 7 -+ -+#define TCCR4B _SFR_MEM8(0xA1) -+#define CS40 0 -+#define CS41 1 -+#define CS42 2 -+#define WGM42 3 -+#define WGM43 4 -+#define ICES4 6 -+#define ICNC4 7 -+ -+#define TCCR4C _SFR_MEM8(0xA2) -+#define FOC4C 5 -+#define FOC4B 6 -+#define FOC4A 7 -+ -+/* Reserved [0xA3] */ -+ -+/* Combine TCNT4L and TCNT4H */ -+#define TCNT4 _SFR_MEM16(0xA4) -+ -+#define TCNT4L _SFR_MEM8(0xA4) -+#define TCNT4H _SFR_MEM8(0xA5) -+ -+/* Combine ICR4L and ICR4H */ -+#define ICR4 _SFR_MEM16(0xA6) -+ -+#define ICR4L _SFR_MEM8(0xA6) -+#define ICR4H _SFR_MEM8(0xA7) -+ -+/* Combine OCR4AL and OCR4AH */ -+#define OCR4A _SFR_MEM16(0xA8) -+ -+#define OCR4AL _SFR_MEM8(0xA8) -+#define OCR4AH _SFR_MEM8(0xA9) -+ -+/* Combine OCR4BL and OCR4BH */ -+#define OCR4B _SFR_MEM16(0xAA) -+ -+#define OCR4BL _SFR_MEM8(0xAA) -+#define OCR4BH _SFR_MEM8(0xAB) -+ -+/* Combine OCR4CL and OCR4CH */ -+#define OCR4C _SFR_MEM16(0xAC) -+ -+#define OCR4CL _SFR_MEM8(0xAC) -+#define OCR4CH _SFR_MEM8(0xAD) -+ -+/* Reserved [0xAE..0xAF] */ -+ -+#define TCCR2A _SFR_MEM8(0xB0) -+#define WGM20 0 -+#define WGM21 1 -+#define COM2B0 4 -+#define COM2B1 5 -+#define COM2A0 6 -+#define COM2A1 7 -+ -+#define TCCR2B _SFR_MEM8(0xB1) -+#define CS20 0 -+#define CS21 1 -+#define CS22 2 -+#define WGM22 3 -+#define FOC2B 6 -+#define FOC2A 7 -+ -+#define TCNT2 _SFR_MEM8(0xB2) -+ -+#define OCR2A _SFR_MEM8(0xB3) -+ -+#define OCR2B _SFR_MEM8(0xB4) -+ -+/* Reserved [0xB5] */ -+ -+#define ASSR _SFR_MEM8(0xB6) -+#define TCR2BUB 0 -+#define TCR2AUB 1 -+#define OCR2BUB 2 -+#define OCR2AUB 3 -+#define TCN2UB 4 -+#define AS2 5 -+#define EXCLK 6 -+#define EXCLKAMR 7 -+ -+/* Reserved [0xB7] */ -+ -+#define TWBR _SFR_MEM8(0xB8) -+ -+#define TWSR _SFR_MEM8(0xB9) -+#define TWPS0 0 -+#define TWPS1 1 -+#define TWS3 3 -+#define TWS4 4 -+#define TWS5 5 -+#define TWS6 6 -+#define TWS7 7 -+ -+#define TWAR _SFR_MEM8(0xBA) -+#define TWGCE 0 -+#define TWA0 1 -+#define TWA1 2 -+#define TWA2 3 -+#define TWA3 4 -+#define TWA4 5 -+#define TWA5 6 -+#define TWA6 7 -+ -+#define TWDR _SFR_MEM8(0xBB) -+ -+#define TWCR _SFR_MEM8(0xBC) -+#define TWIE 0 -+#define TWEN 2 -+#define TWWC 3 -+#define TWSTO 4 -+#define TWSTA 5 -+#define TWEA 6 -+#define TWINT 7 -+ -+#define TWAMR _SFR_MEM8(0xBD) -+#define TWAM0 1 -+#define TWAM1 2 -+#define TWAM2 3 -+#define TWAM3 4 -+#define TWAM4 5 -+#define TWAM5 6 -+#define TWAM6 7 -+ -+#define IRQ_MASK1 _SFR_MEM8(0xBE) -+#define TX_START_EN 0 -+#define MAF_0_AMI_EN 1 -+#define MAF_1_AMI_EN 2 -+#define MAF_2_AMI_EN 3 -+#define MAF_3_AMI_EN 4 -+ -+#define IRQ_STATUS1 _SFR_MEM8(0xBF) -+#define TX_START 0 -+#define MAF_0_AMI 1 -+#define MAF_1_AMI 2 -+#define MAF_2_AMI 3 -+#define MAF_3_AMI 4 -+ -+#define UCSR0A _SFR_MEM8(0xC0) -+#define MPCM0 0 -+#define U2X0 1 -+#define UPE0 2 -+#define DOR0 3 -+#define FE0 4 -+#define UDRE0 5 -+#define TXC0 6 -+#define RXC0 7 -+ -+#define UCSR0B _SFR_MEM8(0xC1) -+#define TXB80 0 -+#define RXB80 1 -+#define UCSZ02 2 -+#define TXEN0 3 -+#define RXEN0 4 -+#define UDRIE0 5 -+#define TXCIE0 6 -+#define RXCIE0 7 -+ -+#define UCSR0C _SFR_MEM8(0xC2) -+#define UCPOL0 0 -+#define UCSZ00 1 -+#define UCSZ01 2 -+#define USBS0 3 -+#define UPM00 4 -+#define UPM01 5 -+#define UMSEL00 6 -+#define UMSEL01 7 -+#define UCPHA0 1 -+#define UDORD0 2 -+ -+/* Reserved [0xC3] */ -+ -+/* Combine UBRR0L and UBRR0H */ -+#define UBRR0 _SFR_MEM16(0xC4) -+ -+#define UBRR0L _SFR_MEM8(0xC4) -+#define UBRR0H _SFR_MEM8(0xC5) -+ -+#define UDR0 _SFR_MEM8(0xC6) -+ -+/* Reserved [0xC7] */ -+ -+#define UCSR1A _SFR_MEM8(0xC8) -+#define MPCM1 0 -+#define U2X1 1 -+#define UPE1 2 -+#define DOR1 3 -+#define FE1 4 -+#define UDRE1 5 -+#define TXC1 6 -+#define RXC1 7 -+ -+#define UCSR1B _SFR_MEM8(0xC9) -+#define TXB81 0 -+#define RXB81 1 -+#define UCSZ12 2 -+#define TXEN1 3 -+#define RXEN1 4 -+#define UDRIE1 5 -+#define TXCIE1 6 -+#define RXCIE1 7 -+ -+#define UCSR1C _SFR_MEM8(0xCA) -+#define UCPOL1 0 -+#define UCSZ10 1 -+#define UCSZ11 2 -+#define USBS1 3 -+#define UPM10 4 -+#define UPM11 5 -+#define UMSEL10 6 -+#define UMSEL11 7 -+#define UCPHA1 1 -+#define UDORD1 2 -+ -+/* Reserved [0xCB] */ -+ -+/* Combine UBRR1L and UBRR1H */ -+#define UBRR1 _SFR_MEM16(0xCC) -+ -+#define UBRR1L _SFR_MEM8(0xCC) -+#define UBRR1H _SFR_MEM8(0xCD) -+ -+#define UDR1 _SFR_MEM8(0xCE) -+ -+/* Reserved [0xCF..0xD6] */ -+ -+#define SCRSTRLL _SFR_MEM8(0xD7) -+#define SCRSTRLL0 0 -+#define SCRSTRLL1 1 -+#define SCRSTRLL2 2 -+#define SCRSTRLL3 3 -+#define SCRSTRLL4 4 -+#define SCRSTRLL5 5 -+#define SCRSTRLL6 6 -+#define SCRSTRLL7 7 -+ -+#define SCRSTRLH _SFR_MEM8(0xD8) -+#define SCRSTRLH0 0 -+#define SCRSTRLH1 1 -+#define SCRSTRLH2 2 -+#define SCRSTRLH3 3 -+#define SCRSTRLH4 4 -+#define SCRSTRLH5 5 -+#define SCRSTRLH6 6 -+#define SCRSTRLH7 7 -+ -+#define SCRSTRHL _SFR_MEM8(0xD9) -+#define SCRSTRHL0 0 -+#define SCRSTRHL1 1 -+#define SCRSTRHL2 2 -+#define SCRSTRHL3 3 -+#define SCRSTRHL4 4 -+#define SCRSTRHL5 5 -+#define SCRSTRHL6 6 -+#define SCRSTRHL7 7 -+ -+#define SCRSTRHH _SFR_MEM8(0xDA) -+#define SCRSTRHH0 0 -+#define SCRSTRHH1 1 -+#define SCRSTRHH2 2 -+#define SCRSTRHH3 3 -+#define SCRSTRHH4 4 -+#define SCRSTRHH5 5 -+#define SCRSTRHH6 6 -+#define SCRSTRHH7 7 -+ -+#define SCCSR _SFR_MEM8(0xDB) -+#define SCCS10 0 -+#define SCCS11 1 -+#define SCCS20 2 -+#define SCCS21 3 -+#define SCCS30 4 -+#define SCCS31 5 -+ -+#define SCCR0 _SFR_MEM8(0xDC) -+#define SCCMP1 0 -+#define SCCMP2 1 -+#define SCCMP3 2 -+#define SCTSE 3 -+#define SCCKSEL 4 -+#define SCEN 5 -+#define SCMBTS 6 -+#define SCRES 7 -+ -+#define SCCR1 _SFR_MEM8(0xDD) -+#define SCENBO 0 -+#define SCEECLK 1 -+#define SCCKDIV0 2 -+#define SCCKDIV1 3 -+#define SCCKDIV2 4 -+#define SCBTSM 5 -+#define Res6 7 -+ -+#define SCSR _SFR_MEM8(0xDE) -+#define SCBSY 0 -+ -+#define SCIRQM _SFR_MEM8(0xDF) -+#define IRQMCP1 0 -+#define IRQMCP2 1 -+#define IRQMCP3 2 -+#define IRQMOF 3 -+#define IRQMBO 4 -+ -+#define SCIRQS _SFR_MEM8(0xE0) -+#define IRQSCP1 0 -+#define IRQSCP2 1 -+#define IRQSCP3 2 -+#define IRQSOF 3 -+#define IRQSBO 4 -+ -+#define SCCNTLL _SFR_MEM8(0xE1) -+#define SCCNTLL0 0 -+#define SCCNTLL1 1 -+#define SCCNTLL2 2 -+#define SCCNTLL3 3 -+#define SCCNTLL4 4 -+#define SCCNTLL5 5 -+#define SCCNTLL6 6 -+#define SCCNTLL7 7 -+ -+#define SCCNTLH _SFR_MEM8(0xE2) -+#define SCCNTLH0 0 -+#define SCCNTLH1 1 -+#define SCCNTLH2 2 -+#define SCCNTLH3 3 -+#define SCCNTLH4 4 -+#define SCCNTLH5 5 -+#define SCCNTLH6 6 -+#define SCCNTLH7 7 -+ -+#define SCCNTHL _SFR_MEM8(0xE3) -+#define SCCNTHL0 0 -+#define SCCNTHL1 1 -+#define SCCNTHL2 2 -+#define SCCNTHL3 3 -+#define SCCNTHL4 4 -+#define SCCNTHL5 5 -+#define SCCNTHL6 6 -+#define SCCNTHL7 7 -+ -+#define SCCNTHH _SFR_MEM8(0xE4) -+#define SCCNTHH0 0 -+#define SCCNTHH1 1 -+#define SCCNTHH2 2 -+#define SCCNTHH3 3 -+#define SCCNTHH4 4 -+#define SCCNTHH5 5 -+#define SCCNTHH6 6 -+#define SCCNTHH7 7 -+ -+#define SCBTSRLL _SFR_MEM8(0xE5) -+#define SCBTSRLL0 0 -+#define SCBTSRLL1 1 -+#define SCBTSRLL2 2 -+#define SCBTSRLL3 3 -+#define SCBTSRLL4 4 -+#define SCBTSRLL5 5 -+#define SCBTSRLL6 6 -+#define SCBTSRLL7 7 -+ -+#define SCBTSRLH _SFR_MEM8(0xE6) -+#define SCBTSRLH0 0 -+#define SCBTSRLH1 1 -+#define SCBTSRLH2 2 -+#define SCBTSRLH3 3 -+#define SCBTSRLH4 4 -+#define SCBTSRLH5 5 -+#define SCBTSRLH6 6 -+#define SCBTSRLH7 7 -+ -+#define SCBTSRHL _SFR_MEM8(0xE7) -+#define SCBTSRHL0 0 -+#define SCBTSRHL1 1 -+#define SCBTSRHL2 2 -+#define SCBTSRHL3 3 -+#define SCBTSRHL4 4 -+#define SCBTSRHL5 5 -+#define SCBTSRHL6 6 -+#define SCBTSRHL7 7 -+ -+#define SCBTSRHH _SFR_MEM8(0xE8) -+#define SCBTSRHH0 0 -+#define SCBTSRHH1 1 -+#define SCBTSRHH2 2 -+#define SCBTSRHH3 3 -+#define SCBTSRHH4 4 -+#define SCBTSRHH5 5 -+#define SCBTSRHH6 6 -+#define SCBTSRHH7 7 -+ -+#define SCTSRLL _SFR_MEM8(0xE9) -+#define SCTSRLL0 0 -+#define SCTSRLL1 1 -+#define SCTSRLL2 2 -+#define SCTSRLL3 3 -+#define SCTSRLL4 4 -+#define SCTSRLL5 5 -+#define SCTSRLL6 6 -+#define SCTSRLL7 7 -+ -+#define SCTSRLH _SFR_MEM8(0xEA) -+#define SCTSRLH0 0 -+#define SCTSRLH1 1 -+#define SCTSRLH2 2 -+#define SCTSRLH3 3 -+#define SCTSRLH4 4 -+#define SCTSRLH5 5 -+#define SCTSRLH6 6 -+#define SCTSRLH7 7 -+ -+#define SCTSRHL _SFR_MEM8(0xEB) -+#define SCTSRHL0 0 -+#define SCTSRHL1 1 -+#define SCTSRHL2 2 -+#define SCTSRHL3 3 -+#define SCTSRHL4 4 -+#define SCTSRHL5 5 -+#define SCTSRHL6 6 -+#define SCTSRHL7 7 -+ -+#define SCTSRHH _SFR_MEM8(0xEC) -+#define SCTSRHH0 0 -+#define SCTSRHH1 1 -+#define SCTSRHH2 2 -+#define SCTSRHH3 3 -+#define SCTSRHH4 4 -+#define SCTSRHH5 5 -+#define SCTSRHH6 6 -+#define SCTSRHH7 7 -+ -+#define SCOCR3LL _SFR_MEM8(0xED) -+#define SCOCR3LL0 0 -+#define SCOCR3LL1 1 -+#define SCOCR3LL2 2 -+#define SCOCR3LL3 3 -+#define SCOCR3LL4 4 -+#define SCOCR3LL5 5 -+#define SCOCR3LL6 6 -+#define SCOCR3LL7 7 -+ -+#define SCOCR3LH _SFR_MEM8(0xEE) -+#define SCOCR3LH0 0 -+#define SCOCR3LH1 1 -+#define SCOCR3LH2 2 -+#define SCOCR3LH3 3 -+#define SCOCR3LH4 4 -+#define SCOCR3LH5 5 -+#define SCOCR3LH6 6 -+#define SCOCR3LH7 7 -+ -+#define SCOCR3HL _SFR_MEM8(0xEF) -+#define SCOCR3HL0 0 -+#define SCOCR3HL1 1 -+#define SCOCR3HL2 2 -+#define SCOCR3HL3 3 -+#define SCOCR3HL4 4 -+#define SCOCR3HL5 5 -+#define SCOCR3HL6 6 -+#define SCOCR3HL7 7 -+ -+#define SCOCR3HH _SFR_MEM8(0xF0) -+#define SCOCR3HH0 0 -+#define SCOCR3HH1 1 -+#define SCOCR3HH2 2 -+#define SCOCR3HH3 3 -+#define SCOCR3HH4 4 -+#define SCOCR3HH5 5 -+#define SCOCR3HH6 6 -+#define SCOCR3HH7 7 -+ -+#define SCOCR2LL _SFR_MEM8(0xF1) -+#define SCOCR2LL0 0 -+#define SCOCR2LL1 1 -+#define SCOCR2LL2 2 -+#define SCOCR2LL3 3 -+#define SCOCR2LL4 4 -+#define SCOCR2LL5 5 -+#define SCOCR2LL6 6 -+#define SCOCR2LL7 7 -+ -+#define SCOCR2LH _SFR_MEM8(0xF2) -+#define SCOCR2LH0 0 -+#define SCOCR2LH1 1 -+#define SCOCR2LH2 2 -+#define SCOCR2LH3 3 -+#define SCOCR2LH4 4 -+#define SCOCR2LH5 5 -+#define SCOCR2LH6 6 -+#define SCOCR2LH7 7 -+ -+#define SCOCR2HL _SFR_MEM8(0xF3) -+#define SCOCR2HL0 0 -+#define SCOCR2HL1 1 -+#define SCOCR2HL2 2 -+#define SCOCR2HL3 3 -+#define SCOCR2HL4 4 -+#define SCOCR2HL5 5 -+#define SCOCR2HL6 6 -+#define SCOCR2HL7 7 -+ -+#define SCOCR2HH _SFR_MEM8(0xF4) -+#define SCOCR2HH0 0 -+#define SCOCR2HH1 1 -+#define SCOCR2HH2 2 -+#define SCOCR2HH3 3 -+#define SCOCR2HH4 4 -+#define SCOCR2HH5 5 -+#define SCOCR2HH6 6 -+#define SCOCR2HH7 7 -+ -+#define SCOCR1LL _SFR_MEM8(0xF5) -+#define SCOCR1LL0 0 -+#define SCOCR1LL1 1 -+#define SCOCR1LL2 2 -+#define SCOCR1LL3 3 -+#define SCOCR1LL4 4 -+#define SCOCR1LL5 5 -+#define SCOCR1LL6 6 -+#define SCOCR1LL7 7 -+ -+#define SCOCR1LH _SFR_MEM8(0xF6) -+#define SCOCR1LH0 0 -+#define SCOCR1LH1 1 -+#define SCOCR1LH2 2 -+#define SCOCR1LH3 3 -+#define SCOCR1LH4 4 -+#define SCOCR1LH5 5 -+#define SCOCR1LH6 6 -+#define SCOCR1LH7 7 -+ -+#define SCOCR1HL _SFR_MEM8(0xF7) -+#define SCOCR1HL0 0 -+#define SCOCR1HL1 1 -+#define SCOCR1HL2 2 -+#define SCOCR1HL3 3 -+#define SCOCR1HL4 4 -+#define SCOCR1HL5 5 -+#define SCOCR1HL6 6 -+#define SCOCR1HL7 7 -+ -+#define SCOCR1HH _SFR_MEM8(0xF8) -+#define SCOCR1HH0 0 -+#define SCOCR1HH1 1 -+#define SCOCR1HH2 2 -+#define SCOCR1HH3 3 -+#define SCOCR1HH4 4 -+#define SCOCR1HH5 5 -+#define SCOCR1HH6 6 -+#define SCOCR1HH7 7 -+ -+#define SCTSTRLL _SFR_MEM8(0xF9) -+#define SCTSTRLL0 0 -+#define SCTSTRLL1 1 -+#define SCTSTRLL2 2 -+#define SCTSTRLL3 3 -+#define SCTSTRLL4 4 -+#define SCTSTRLL5 5 -+#define SCTSTRLL6 6 -+#define SCTSTRLL7 7 -+ -+#define SCTSTRLH _SFR_MEM8(0xFA) -+#define SCTSTRLH0 0 -+#define SCTSTRLH1 1 -+#define SCTSTRLH2 2 -+#define SCTSTRLH3 3 -+#define SCTSTRLH4 4 -+#define SCTSTRLH5 5 -+#define SCTSTRLH6 6 -+#define SCTSTRLH7 7 -+ -+#define SCTSTRHL _SFR_MEM8(0xFB) -+#define SCTSTRHL0 0 -+#define SCTSTRHL1 1 -+#define SCTSTRHL2 2 -+#define SCTSTRHL3 3 -+#define SCTSTRHL4 4 -+#define SCTSTRHL5 5 -+#define SCTSTRHL6 6 -+#define SCTSTRHL7 7 -+ -+#define SCTSTRHH _SFR_MEM8(0xFC) -+#define SCTSTRHH0 0 -+#define SCTSTRHH1 1 -+#define SCTSTRHH2 2 -+#define SCTSTRHH3 3 -+#define SCTSTRHH4 4 -+#define SCTSTRHH5 5 -+#define SCTSTRHH6 6 -+#define SCTSTRHH7 7 -+ -+/* Reserved [0xFD..0x10B] */ -+ -+#define MAFCR0 _SFR_MEM8(0x10C) -+#define MAF0EN 0 -+#define MAF1EN 1 -+#define MAF2EN 2 -+#define MAF3EN 3 -+ -+#define MAFCR1 _SFR_MEM8(0x10D) -+#define AACK_0_I_AM_COORD 0 -+#define AACK_0_SET_PD 1 -+#define AACK_1_I_AM_COORD 2 -+#define AACK_1_SET_PD 3 -+#define AACK_2_I_AM_COORD 4 -+#define AACK_2_SET_PD 5 -+#define AACK_3_I_AM_COORD 6 -+#define AACK_3_SET_PD 7 -+ -+#define MAFSA0L _SFR_MEM8(0x10E) -+#define MAFSA0L0 0 -+#define MAFSA0L1 1 -+#define MAFSA0L2 2 -+#define MAFSA0L3 3 -+#define MAFSA0L4 4 -+#define MAFSA0L5 5 -+#define MAFSA0L6 6 -+#define MAFSA0L7 7 -+ -+#define MAFSA0H _SFR_MEM8(0x10F) -+#define MAFSA0H0 0 -+#define MAFSA0H1 1 -+#define MAFSA0H2 2 -+#define MAFSA0H3 3 -+#define MAFSA0H4 4 -+#define MAFSA0H5 5 -+#define MAFSA0H6 6 -+#define MAFSA0H7 7 -+ -+#define MAFPA0L _SFR_MEM8(0x110) -+#define MAFPA0L0 0 -+#define MAFPA0L1 1 -+#define MAFPA0L2 2 -+#define MAFPA0L3 3 -+#define MAFPA0L4 4 -+#define MAFPA0L5 5 -+#define MAFPA0L6 6 -+#define MAFPA0L7 7 -+ -+#define MAFPA0H _SFR_MEM8(0x111) -+#define MAFPA0H0 0 -+#define MAFPA0H1 1 -+#define MAFPA0H2 2 -+#define MAFPA0H3 3 -+#define MAFPA0H4 4 -+#define MAFPA0H5 5 -+#define MAFPA0H6 6 -+#define MAFPA0H7 7 -+ -+#define MAFSA1L _SFR_MEM8(0x112) -+#define MAFSA1L0 0 -+#define MAFSA1L1 1 -+#define MAFSA1L2 2 -+#define MAFSA1L3 3 -+#define MAFSA1L4 4 -+#define MAFSA1L5 5 -+#define MAFSA1L6 6 -+#define MAFSA1L7 7 -+ -+#define MAFSA1H _SFR_MEM8(0x113) -+#define MAFSA1H0 0 -+#define MAFSA1H1 1 -+#define MAFSA1H2 2 -+#define MAFSA1H3 3 -+#define MAFSA1H4 4 -+#define MAFSA1H5 5 -+#define MAFSA1H6 6 -+#define MAFSA1H7 7 -+ -+#define MAFPA1L _SFR_MEM8(0x114) -+#define MAFPA1L0 0 -+#define MAFPA1L1 1 -+#define MAFPA1L2 2 -+#define MAFPA1L3 3 -+#define MAFPA1L4 4 -+#define MAFPA1L5 5 -+#define MAFPA1L6 6 -+#define MAFPA1L7 7 -+ -+#define MAFPA1H _SFR_MEM8(0x115) -+#define MAFPA1H0 0 -+#define MAFPA1H1 1 -+#define MAFPA1H2 2 -+#define MAFPA1H3 3 -+#define MAFPA1H4 4 -+#define MAFPA1H5 5 -+#define MAFPA1H6 6 -+#define MAFPA1H7 7 -+ -+#define MAFSA2L _SFR_MEM8(0x116) -+#define MAFSA2L0 0 -+#define MAFSA2L1 1 -+#define MAFSA2L2 2 -+#define MAFSA2L3 3 -+#define MAFSA2L4 4 -+#define MAFSA2L5 5 -+#define MAFSA2L6 6 -+#define MAFSA2L7 7 -+ -+#define MAFSA2H _SFR_MEM8(0x117) -+#define MAFSA2H0 0 -+#define MAFSA2H1 1 -+#define MAFSA2H2 2 -+#define MAFSA2H3 3 -+#define MAFSA2H4 4 -+#define MAFSA2H5 5 -+#define MAFSA2H6 6 -+#define MAFSA2H7 7 -+ -+#define MAFPA2L _SFR_MEM8(0x118) -+#define MAFPA2L0 0 -+#define MAFPA2L1 1 -+#define MAFPA2L2 2 -+#define MAFPA2L3 3 -+#define MAFPA2L4 4 -+#define MAFPA2L5 5 -+#define MAFPA2L6 6 -+#define MAFPA2L7 7 -+ -+#define MAFPA2H _SFR_MEM8(0x119) -+#define MAFPA2H0 0 -+#define MAFPA2H1 1 -+#define MAFPA2H2 2 -+#define MAFPA2H3 3 -+#define MAFPA2H4 4 -+#define MAFPA2H5 5 -+#define MAFPA2H6 6 -+#define MAFPA2H7 7 -+ -+#define MAFSA3L _SFR_MEM8(0x11A) -+#define MAFSA3L0 0 -+#define MAFSA3L1 1 -+#define MAFSA3L2 2 -+#define MAFSA3L3 3 -+#define MAFSA3L4 4 -+#define MAFSA3L5 5 -+#define MAFSA3L6 6 -+#define MAFSA3L7 7 -+ -+#define MAFSA3H _SFR_MEM8(0x11B) -+#define MAFSA3H0 0 -+#define MAFSA3H1 1 -+#define MAFSA3H2 2 -+#define MAFSA3H3 3 -+#define MAFSA3H4 4 -+#define MAFSA3H5 5 -+#define MAFSA3H6 6 -+#define MAFSA3H7 7 -+ -+#define MAFPA3L _SFR_MEM8(0x11C) -+#define MAFPA3L0 0 -+#define MAFPA3L1 1 -+#define MAFPA3L2 2 -+#define MAFPA3L3 3 -+#define MAFPA3L4 4 -+#define MAFPA3L5 5 -+#define MAFPA3L6 6 -+#define MAFPA3L7 7 -+ -+#define MAFPA3H _SFR_MEM8(0x11D) -+#define MAFPA3H0 0 -+#define MAFPA3H1 1 -+#define MAFPA3H2 2 -+#define MAFPA3H3 3 -+#define MAFPA3H4 4 -+#define MAFPA3H5 5 -+#define MAFPA3H6 6 -+#define MAFPA3H7 7 -+ -+/* Reserved [0x11E..0x11F] */ -+ -+#define TCCR5A _SFR_MEM8(0x120) -+#define WGM50 0 -+#define WGM51 1 -+#define COM5C0 2 -+#define COM5C1 3 -+#define COM5B0 4 -+#define COM5B1 5 -+#define COM5A0 6 -+#define COM5A1 7 -+ -+#define TCCR5B _SFR_MEM8(0x121) -+#define CS50 0 -+#define CS51 1 -+#define CS52 2 -+#define WGM52 3 -+#define WGM53 4 -+#define ICES5 6 -+#define ICNC5 7 -+ -+#define TCCR5C _SFR_MEM8(0x122) -+#define FOC5C 5 -+#define FOC5B 6 -+#define FOC5A 7 -+ -+/* Reserved [0x123] */ -+ -+/* Combine TCNT5L and TCNT5H */ -+#define TCNT5 _SFR_MEM16(0x124) -+ -+#define TCNT5L _SFR_MEM8(0x124) -+#define TCNT5H _SFR_MEM8(0x125) -+ -+/* Combine ICR5L and ICR5H */ -+#define ICR5 _SFR_MEM16(0x126) -+ -+#define ICR5L _SFR_MEM8(0x126) -+#define ICR5H _SFR_MEM8(0x127) -+ -+/* Combine OCR5AL and OCR5AH */ -+#define OCR5A _SFR_MEM16(0x128) -+ -+#define OCR5AL _SFR_MEM8(0x128) -+#define OCR5AH _SFR_MEM8(0x129) -+ -+/* Combine OCR5BL and OCR5BH */ -+#define OCR5B _SFR_MEM16(0x12A) -+ -+#define OCR5BL _SFR_MEM8(0x12A) -+#define OCR5BH _SFR_MEM8(0x12B) -+ -+/* Combine OCR5CL and OCR5CH */ -+#define OCR5C _SFR_MEM16(0x12C) -+ -+#define OCR5CL _SFR_MEM8(0x12C) -+#define OCR5CH _SFR_MEM8(0x12D) -+ -+/* Reserved [0x12E] */ -+ -+#define LLCR _SFR_MEM8(0x12F) -+#define LLENCAL 0 -+#define LLSHORT 1 -+#define LLTCO 2 -+#define LLCAL 3 -+#define LLCOMP 4 -+#define LLDONE 5 -+ -+#define LLDRL _SFR_MEM8(0x130) -+#define LLDRL0 0 -+#define LLDRL1 1 -+#define LLDRL2 2 -+#define LLDRL3 3 -+ -+#define LLDRH _SFR_MEM8(0x131) -+#define LLDRH0 0 -+#define LLDRH1 1 -+#define LLDRH2 2 -+#define LLDRH3 3 -+#define LLDRH4 4 -+ -+#define DRTRAM3 _SFR_MEM8(0x132) -+#define ENDRT 4 -+#define DRTSWOK 5 -+ -+#define DRTRAM2 _SFR_MEM8(0x133) -+ -+#define DRTRAM1 _SFR_MEM8(0x134) -+ -+#define DRTRAM0 _SFR_MEM8(0x135) -+ -+#define DPDS0 _SFR_MEM8(0x136) -+#define PBDRV0 0 -+#define PBDRV1 1 -+#define PDDRV0 2 -+#define PDDRV1 3 -+#define PEDRV0 4 -+#define PEDRV1 5 -+#define PFDRV0 6 -+#define PFDRV1 7 -+ -+#define DPDS1 _SFR_MEM8(0x137) -+#define PGDRV0 0 -+#define PGDRV1 1 -+ -+#define PARCR _SFR_MEM8(0x138) -+#define PARUFI 0 -+#define PARDFI 1 -+#define PALTU0 2 -+#define PALTU1 3 -+#define PALTU2 4 -+#define PALTD0 5 -+#define PALTD1 6 -+#define PALTD2 7 -+ -+#define TRXPR _SFR_MEM8(0x139) -+#define TRXRST 0 -+#define SLPTR 1 -+ -+/* Reserved [0x13A..0x13B] */ -+ -+#define AES_CTRL _SFR_MEM8(0x13C) -+#define AES_IM 2 -+#define AES_DIR 3 -+#define AES_MODE 5 -+#define AES_REQUEST 7 -+ -+#define AES_STATUS _SFR_MEM8(0x13D) -+#define AES_DONE 0 -+#define AES_ER 7 -+ -+#define AES_STATE _SFR_MEM8(0x13E) -+#define AES_STATE0 0 -+#define AES_STATE1 1 -+#define AES_STATE2 2 -+#define AES_STATE3 3 -+#define AES_STATE4 4 -+#define AES_STATE5 5 -+#define AES_STATE6 6 -+#define AES_STATE7 7 -+ -+#define AES_KEY _SFR_MEM8(0x13F) -+#define AES_KEY0 0 -+#define AES_KEY1 1 -+#define AES_KEY2 2 -+#define AES_KEY3 3 -+#define AES_KEY4 4 -+#define AES_KEY5 5 -+#define AES_KEY6 6 -+#define AES_KEY7 7 -+ -+/* Reserved [0x140] */ -+ -+#define TRX_STATUS _SFR_MEM8(0x141) -+#define TRX_STATUS0 0 -+#define TRX_STATUS1 1 -+#define TRX_STATUS2 2 -+#define TRX_STATUS3 3 -+#define TRX_STATUS4 4 -+#define TST_STATUS 5 -+#define CCA_STATUS 6 -+#define CCA_DONE 7 -+ -+#define TRX_STATE _SFR_MEM8(0x142) -+#define TRX_CMD0 0 -+#define TRX_CMD1 1 -+#define TRX_CMD2 2 -+#define TRX_CMD3 3 -+#define TRX_CMD4 4 -+#define TRAC_STATUS0 5 -+#define TRAC_STATUS1 6 -+#define TRAC_STATUS2 7 -+ -+#define TRX_CTRL_0 _SFR_MEM8(0x143) -+#define PMU_IF_INV 4 -+#define PMU_START 5 -+#define PMU_EN 6 -+#define Res7 7 -+ -+#define TRX_CTRL_1 _SFR_MEM8(0x144) -+#define PLL_TX_FLT 4 -+#define TX_AUTO_CRC_ON 5 -+#define IRQ_2_EXT_EN 6 -+#define PA_EXT_EN 7 -+ -+#define PHY_TX_PWR _SFR_MEM8(0x145) -+#define TX_PWR0 0 -+#define TX_PWR1 1 -+#define TX_PWR2 2 -+#define TX_PWR3 3 -+ -+#define PHY_RSSI _SFR_MEM8(0x146) -+#define RSSI0 0 -+#define RSSI1 1 -+#define RSSI2 2 -+#define RSSI3 3 -+#define RSSI4 4 -+#define RND_VALUE0 5 -+#define RND_VALUE1 6 -+#define RX_CRC_VALID 7 -+ -+#define PHY_ED_LEVEL _SFR_MEM8(0x147) -+#define ED_LEVEL0 0 -+#define ED_LEVEL1 1 -+#define ED_LEVEL2 2 -+#define ED_LEVEL3 3 -+#define ED_LEVEL4 4 -+#define ED_LEVEL5 5 -+#define ED_LEVEL6 6 -+#define ED_LEVEL7 7 -+ -+#define PHY_CC_CCA _SFR_MEM8(0x148) -+#define CHANNEL0 0 -+#define CHANNEL1 1 -+#define CHANNEL2 2 -+#define CHANNEL3 3 -+#define CHANNEL4 4 -+#define CCA_MODE0 5 -+#define CCA_MODE1 6 -+#define CCA_REQUEST 7 -+ -+#define CCA_THRES _SFR_MEM8(0x149) -+#define CCA_ED_THRES0 0 -+#define CCA_ED_THRES1 1 -+#define CCA_ED_THRES2 2 -+#define CCA_ED_THRES3 3 -+#define CCA_CS_THRES0 4 -+#define CCA_CS_THRES1 5 -+#define CCA_CS_THRES2 6 -+#define CCA_CS_THRES3 7 -+ -+#define RX_CTRL _SFR_MEM8(0x14A) -+#define PDT_THRES0 0 -+#define PDT_THRES1 1 -+#define PDT_THRES2 2 -+#define PDT_THRES3 3 -+ -+#define SFD_VALUE _SFR_MEM8(0x14B) -+#define SFD_VALUE0 0 -+#define SFD_VALUE1 1 -+#define SFD_VALUE2 2 -+#define SFD_VALUE3 3 -+#define SFD_VALUE4 4 -+#define SFD_VALUE5 5 -+#define SFD_VALUE6 6 -+#define SFD_VALUE7 7 -+ -+#define TRX_CTRL_2 _SFR_MEM8(0x14C) -+#define OQPSK_DATA_RATE0 0 -+#define OQPSK_DATA_RATE1 1 -+#define RX_SAFE_MODE 7 -+ -+#define ANT_DIV _SFR_MEM8(0x14D) -+#define ANT_CTRL0 0 -+#define ANT_CTRL1 1 -+#define ANT_EXT_SW_EN 2 -+#define ANT_DIV_EN 3 -+#define ANT_SEL 7 -+ -+#define IRQ_MASK _SFR_MEM8(0x14E) -+#define PLL_LOCK_EN 0 -+#define PLL_UNLOCK_EN 1 -+#define RX_START_EN 2 -+#define RX_END_EN 3 -+#define CCA_ED_DONE_EN 4 -+#define AMI_EN 5 -+#define TX_END_EN 6 -+#define AWAKE_EN 7 -+ -+#define IRQ_STATUS _SFR_MEM8(0x14F) -+#define PLL_LOCK 0 -+#define PLL_UNLOCK 1 -+#define RX_START 2 -+#define RX_END 3 -+#define CCA_ED_DONE 4 -+#define AMI 5 -+#define TX_END 6 -+#define AWAKE 7 -+ -+#define VREG_CTRL _SFR_MEM8(0x150) -+#define DVDD_OK 2 -+#define DVREG_EXT 3 -+#define AVDD_OK 6 -+#define AVREG_EXT 7 -+ -+#define BATMON _SFR_MEM8(0x151) -+#define BATMON_VTH0 0 -+#define BATMON_VTH1 1 -+#define BATMON_VTH2 2 -+#define BATMON_VTH3 3 -+#define BATMON_HR 4 -+#define BATMON_OK 5 -+#define BAT_LOW_EN 6 -+#define BAT_LOW 7 -+ -+#define XOSC_CTRL _SFR_MEM8(0x152) -+#define XTAL_TRIM0 0 -+#define XTAL_TRIM1 1 -+#define XTAL_TRIM2 2 -+#define XTAL_TRIM3 3 -+#define XTAL_MODE0 4 -+#define XTAL_MODE1 5 -+#define XTAL_MODE2 6 -+#define XTAL_MODE3 7 -+ -+#define CC_CTRL_0 _SFR_MEM8(0x153) -+#define CC_NUMBER0 0 -+#define CC_NUMBER1 1 -+#define CC_NUMBER2 2 -+#define CC_NUMBER3 3 -+#define CC_NUMBER4 4 -+#define CC_NUMBER5 5 -+#define CC_NUMBER6 6 -+#define CC_NUMBER7 7 -+ -+#define CC_CTRL_1 _SFR_MEM8(0x154) -+#define CC_BAND0 0 -+#define CC_BAND1 1 -+#define CC_BAND2 2 -+#define CC_BAND3 3 -+ -+#define RX_SYN _SFR_MEM8(0x155) -+#define RX_PDT_LEVEL0 0 -+#define RX_PDT_LEVEL1 1 -+#define RX_PDT_LEVEL2 2 -+#define RX_PDT_LEVEL3 3 -+#define RX_OVERRIDE 6 -+#define RX_PDT_DIS 7 -+ -+#define TRX_RPC _SFR_MEM8(0x156) -+#define XAH_RPC_EN 0 -+#define IPAN_RPC_EN 1 -+#define PLL_RPC_EN 3 -+#define PDT_RPC_EN 4 -+#define RX_RPC_EN 5 -+#define RX_RPC_CTRL0 6 -+#define RX_RPC_CTRL1 7 -+ -+#define XAH_CTRL_1 _SFR_MEM8(0x157) -+#define AACK_PROM_MODE 1 -+#define AACK_ACK_TIME 2 -+#define AACK_UPLD_RES_FT 4 -+#define AACK_FLTR_RES_FT 5 -+ -+#define FTN_CTRL _SFR_MEM8(0x158) -+#define FTN_START 7 -+ -+/* Reserved [0x159] */ -+ -+#define PLL_CF _SFR_MEM8(0x15A) -+#define PLL_CF_START 7 -+ -+#define PLL_DCU _SFR_MEM8(0x15B) -+#define PLL_DCU_START 7 -+ -+#define PART_NUM _SFR_MEM8(0x15C) -+#define PART_NUM0 0 -+#define PART_NUM1 1 -+#define PART_NUM2 2 -+#define PART_NUM3 3 -+#define PART_NUM4 4 -+#define PART_NUM5 5 -+#define PART_NUM6 6 -+#define PART_NUM7 7 -+ -+#define VERSION_NUM _SFR_MEM8(0x15D) -+#define VERSION_NUM0 0 -+#define VERSION_NUM1 1 -+#define VERSION_NUM2 2 -+#define VERSION_NUM3 3 -+#define VERSION_NUM4 4 -+#define VERSION_NUM5 5 -+#define VERSION_NUM6 6 -+#define VERSION_NUM7 7 -+ -+#define MAN_ID_0 _SFR_MEM8(0x15E) -+#define MAN_ID_00 0 -+#define MAN_ID_01 1 -+#define MAN_ID_02 2 -+#define MAN_ID_03 3 -+#define MAN_ID_04 4 -+#define MAN_ID_05 5 -+#define MAN_ID_06 6 -+#define MAN_ID_07 7 -+ -+#define MAN_ID_1 _SFR_MEM8(0x15F) -+#define MAN_ID_10 0 -+#define MAN_ID_11 1 -+#define MAN_ID_12 2 -+#define MAN_ID_13 3 -+#define MAN_ID_14 4 -+#define MAN_ID_15 5 -+#define MAN_ID_16 6 -+#define MAN_ID_17 7 -+ -+#define SHORT_ADDR_0 _SFR_MEM8(0x160) -+#define SHORT_ADDR_00 0 -+#define SHORT_ADDR_01 1 -+#define SHORT_ADDR_02 2 -+#define SHORT_ADDR_03 3 -+#define SHORT_ADDR_04 4 -+#define SHORT_ADDR_05 5 -+#define SHORT_ADDR_06 6 -+#define SHORT_ADDR_07 7 -+ -+#define SHORT_ADDR_1 _SFR_MEM8(0x161) -+#define SHORT_ADDR_10 0 -+#define SHORT_ADDR_11 1 -+#define SHORT_ADDR_12 2 -+#define SHORT_ADDR_13 3 -+#define SHORT_ADDR_14 4 -+#define SHORT_ADDR_15 5 -+#define SHORT_ADDR_16 6 -+#define SHORT_ADDR_17 7 -+ -+#define PAN_ID_0 _SFR_MEM8(0x162) -+#define PAN_ID_00 0 -+#define PAN_ID_01 1 -+#define PAN_ID_02 2 -+#define PAN_ID_03 3 -+#define PAN_ID_04 4 -+#define PAN_ID_05 5 -+#define PAN_ID_06 6 -+#define PAN_ID_07 7 -+ -+#define PAN_ID_1 _SFR_MEM8(0x163) -+#define PAN_ID_10 0 -+#define PAN_ID_11 1 -+#define PAN_ID_12 2 -+#define PAN_ID_13 3 -+#define PAN_ID_14 4 -+#define PAN_ID_15 5 -+#define PAN_ID_16 6 -+#define PAN_ID_17 7 -+ -+#define IEEE_ADDR_0 _SFR_MEM8(0x164) -+#define IEEE_ADDR_00 0 -+#define IEEE_ADDR_01 1 -+#define IEEE_ADDR_02 2 -+#define IEEE_ADDR_03 3 -+#define IEEE_ADDR_04 4 -+#define IEEE_ADDR_05 5 -+#define IEEE_ADDR_06 6 -+#define IEEE_ADDR_07 7 -+ -+#define IEEE_ADDR_1 _SFR_MEM8(0x165) -+#define IEEE_ADDR_10 0 -+#define IEEE_ADDR_11 1 -+#define IEEE_ADDR_12 2 -+#define IEEE_ADDR_13 3 -+#define IEEE_ADDR_14 4 -+#define IEEE_ADDR_15 5 -+#define IEEE_ADDR_16 6 -+#define IEEE_ADDR_17 7 -+ -+#define IEEE_ADDR_2 _SFR_MEM8(0x166) -+#define IEEE_ADDR_20 0 -+#define IEEE_ADDR_21 1 -+#define IEEE_ADDR_22 2 -+#define IEEE_ADDR_23 3 -+#define IEEE_ADDR_24 4 -+#define IEEE_ADDR_25 5 -+#define IEEE_ADDR_26 6 -+#define IEEE_ADDR_27 7 -+ -+#define IEEE_ADDR_3 _SFR_MEM8(0x167) -+#define IEEE_ADDR_30 0 -+#define IEEE_ADDR_31 1 -+#define IEEE_ADDR_32 2 -+#define IEEE_ADDR_33 3 -+#define IEEE_ADDR_34 4 -+#define IEEE_ADDR_35 5 -+#define IEEE_ADDR_36 6 -+#define IEEE_ADDR_37 7 -+ -+#define IEEE_ADDR_4 _SFR_MEM8(0x168) -+#define IEEE_ADDR_40 0 -+#define IEEE_ADDR_41 1 -+#define IEEE_ADDR_42 2 -+#define IEEE_ADDR_43 3 -+#define IEEE_ADDR_44 4 -+#define IEEE_ADDR_45 5 -+#define IEEE_ADDR_46 6 -+#define IEEE_ADDR_47 7 -+ -+#define IEEE_ADDR_5 _SFR_MEM8(0x169) -+#define IEEE_ADDR_50 0 -+#define IEEE_ADDR_51 1 -+#define IEEE_ADDR_52 2 -+#define IEEE_ADDR_53 3 -+#define IEEE_ADDR_54 4 -+#define IEEE_ADDR_55 5 -+#define IEEE_ADDR_56 6 -+#define IEEE_ADDR_57 7 -+ -+#define IEEE_ADDR_6 _SFR_MEM8(0x16A) -+#define IEEE_ADDR_60 0 -+#define IEEE_ADDR_61 1 -+#define IEEE_ADDR_62 2 -+#define IEEE_ADDR_63 3 -+#define IEEE_ADDR_64 4 -+#define IEEE_ADDR_65 5 -+#define IEEE_ADDR_66 6 -+#define IEEE_ADDR_67 7 -+ -+#define IEEE_ADDR_7 _SFR_MEM8(0x16B) -+#define IEEE_ADDR_70 0 -+#define IEEE_ADDR_71 1 -+#define IEEE_ADDR_72 2 -+#define IEEE_ADDR_73 3 -+#define IEEE_ADDR_74 4 -+#define IEEE_ADDR_75 5 -+#define IEEE_ADDR_76 6 -+#define IEEE_ADDR_77 7 -+ -+#define XAH_CTRL_0 _SFR_MEM8(0x16C) -+#define SLOTTED_OPERATION 0 -+#define MAX_CSMA_RETRIES0 1 -+#define MAX_CSMA_RETRIES1 2 -+#define MAX_CSMA_RETRIES2 3 -+#define MAX_FRAME_RETRIES0 4 -+#define MAX_FRAME_RETRIES1 5 -+#define MAX_FRAME_RETRIES2 6 -+#define MAX_FRAME_RETRIES3 7 -+ -+#define CSMA_SEED_0 _SFR_MEM8(0x16D) -+#define CSMA_SEED_00 0 -+#define CSMA_SEED_01 1 -+#define CSMA_SEED_02 2 -+#define CSMA_SEED_03 3 -+#define CSMA_SEED_04 4 -+#define CSMA_SEED_05 5 -+#define CSMA_SEED_06 6 -+#define CSMA_SEED_07 7 -+ -+#define CSMA_SEED_1 _SFR_MEM8(0x16E) -+#define CSMA_SEED_10 0 -+#define CSMA_SEED_11 1 -+#define CSMA_SEED_12 2 -+#define AACK_I_AM_COORD 3 -+#define AACK_DIS_ACK 4 -+#define AACK_SET_PD 5 -+#define AACK_FVN_MODE0 6 -+#define AACK_FVN_MODE1 7 -+ -+#define CSMA_BE _SFR_MEM8(0x16F) -+#define MIN_BE0 0 -+#define MIN_BE1 1 -+#define MIN_BE2 2 -+#define MIN_BE3 3 -+#define MAX_BE0 4 -+#define MAX_BE1 5 -+#define MAX_BE2 6 -+#define MAX_BE3 7 -+ -+/* Reserved [0x170..0x175] */ -+ -+#define TST_CTRL_DIGI _SFR_MEM8(0x176) -+#define TST_CTRL_DIG0 0 -+#define TST_CTRL_DIG1 1 -+#define TST_CTRL_DIG2 2 -+#define TST_CTRL_DIG3 3 -+ -+/* Reserved [0x177..0x17A] */ -+ -+#define TST_RX_LENGTH _SFR_MEM8(0x17B) -+#define RX_LENGTH0 0 -+#define RX_LENGTH1 1 -+#define RX_LENGTH2 2 -+#define RX_LENGTH3 3 -+#define RX_LENGTH4 4 -+#define RX_LENGTH5 5 -+#define RX_LENGTH6 6 -+#define RX_LENGTH7 7 -+ -+/* Reserved [0x17C..0x17F] */ -+ -+#define TRXFBST _SFR_MEM8(0x180) -+ -+/* Reserved [0x181..0x1FE] */ -+ -+#define TRXFBEND _SFR_MEM8(0x1FF) -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* External Interrupt Request 2 */ -+#define INT2_vect _VECTOR(3) -+#define INT2_vect_num 3 -+ -+/* External Interrupt Request 3 */ -+#define INT3_vect _VECTOR(4) -+#define INT3_vect_num 4 -+ -+/* External Interrupt Request 4 */ -+#define INT4_vect _VECTOR(5) -+#define INT4_vect_num 5 -+ -+/* External Interrupt Request 5 */ -+#define INT5_vect _VECTOR(6) -+#define INT5_vect_num 6 -+ -+/* External Interrupt Request 6 */ -+#define INT6_vect _VECTOR(7) -+#define INT6_vect_num 7 -+ -+/* External Interrupt Request 7 */ -+#define INT7_vect _VECTOR(8) -+#define INT7_vect_num 8 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(9) -+#define PCINT0_vect_num 9 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(10) -+#define PCINT1_vect_num 10 -+ -+/* Pin Change Interrupt Request 2 */ -+#define PCINT2_vect _VECTOR(11) -+#define PCINT2_vect_num 11 -+ -+/* Watchdog Time-out Interrupt */ -+#define WDT_vect _VECTOR(12) -+#define WDT_vect_num 12 -+ -+/* Timer/Counter2 Compare Match A */ -+#define TIMER2_COMPA_vect _VECTOR(13) -+#define TIMER2_COMPA_vect_num 13 -+ -+/* Timer/Counter2 Compare Match B */ -+#define TIMER2_COMPB_vect _VECTOR(14) -+#define TIMER2_COMPB_vect_num 14 -+ -+/* Timer/Counter2 Overflow */ -+#define TIMER2_OVF_vect _VECTOR(15) -+#define TIMER2_OVF_vect_num 15 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(16) -+#define TIMER1_CAPT_vect_num 16 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(17) -+#define TIMER1_COMPA_vect_num 17 -+ -+/* Timer/Counter1 Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(18) -+#define TIMER1_COMPB_vect_num 18 -+ -+/* Timer/Counter1 Compare Match C */ -+#define TIMER1_COMPC_vect _VECTOR(19) -+#define TIMER1_COMPC_vect_num 19 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(20) -+#define TIMER1_OVF_vect_num 20 -+ -+/* Timer/Counter0 Compare Match A */ -+#define TIMER0_COMPA_vect _VECTOR(21) -+#define TIMER0_COMPA_vect_num 21 -+ -+/* Timer/Counter0 Compare Match B */ -+#define TIMER0_COMPB_vect _VECTOR(22) -+#define TIMER0_COMPB_vect_num 22 -+ -+/* Timer/Counter0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(23) -+#define TIMER0_OVF_vect_num 23 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(24) -+#define SPI_STC_vect_num 24 -+ -+/* USART0, Rx Complete */ -+#define USART0_RX_vect _VECTOR(25) -+#define USART0_RX_vect_num 25 -+ -+/* USART0 Data register Empty */ -+#define USART0_UDRE_vect _VECTOR(26) -+#define USART0_UDRE_vect_num 26 -+ -+/* USART0, Tx Complete */ -+#define USART0_TX_vect _VECTOR(27) -+#define USART0_TX_vect_num 27 -+ -+/* Analog Comparator */ -+#define ANALOG_COMP_vect _VECTOR(28) -+#define ANALOG_COMP_vect_num 28 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(29) -+#define ADC_vect_num 29 -+ -+/* EEPROM Ready */ -+#define EE_READY_vect _VECTOR(30) -+#define EE_READY_vect_num 30 -+ -+/* Timer/Counter3 Capture Event */ -+#define TIMER3_CAPT_vect _VECTOR(31) -+#define TIMER3_CAPT_vect_num 31 -+ -+/* Timer/Counter3 Compare Match A */ -+#define TIMER3_COMPA_vect _VECTOR(32) -+#define TIMER3_COMPA_vect_num 32 -+ -+/* Timer/Counter3 Compare Match B */ -+#define TIMER3_COMPB_vect _VECTOR(33) -+#define TIMER3_COMPB_vect_num 33 -+ -+/* Timer/Counter3 Compare Match C */ -+#define TIMER3_COMPC_vect _VECTOR(34) -+#define TIMER3_COMPC_vect_num 34 -+ -+/* Timer/Counter3 Overflow */ -+#define TIMER3_OVF_vect _VECTOR(35) -+#define TIMER3_OVF_vect_num 35 -+ -+/* USART1, Rx Complete */ -+#define USART1_RX_vect _VECTOR(36) -+#define USART1_RX_vect_num 36 -+ -+/* USART1 Data register Empty */ -+#define USART1_UDRE_vect _VECTOR(37) -+#define USART1_UDRE_vect_num 37 -+ -+/* USART1, Tx Complete */ -+#define USART1_TX_vect _VECTOR(38) -+#define USART1_TX_vect_num 38 -+ -+/* 2-wire Serial Interface */ -+#define TWI_vect _VECTOR(39) -+#define TWI_vect_num 39 -+ -+/* Store Program Memory Read */ -+#define SPM_READY_vect _VECTOR(40) -+#define SPM_READY_vect_num 40 -+ -+/* Timer/Counter4 Capture Event */ -+#define TIMER4_CAPT_vect _VECTOR(41) -+#define TIMER4_CAPT_vect_num 41 -+ -+/* Timer/Counter4 Compare Match A */ -+#define TIMER4_COMPA_vect _VECTOR(42) -+#define TIMER4_COMPA_vect_num 42 -+ -+/* Timer/Counter4 Compare Match B */ -+#define TIMER4_COMPB_vect _VECTOR(43) -+#define TIMER4_COMPB_vect_num 43 -+ -+/* Timer/Counter4 Compare Match C */ -+#define TIMER4_COMPC_vect _VECTOR(44) -+#define TIMER4_COMPC_vect_num 44 -+ -+/* Timer/Counter4 Overflow */ -+#define TIMER4_OVF_vect _VECTOR(45) -+#define TIMER4_OVF_vect_num 45 -+ -+/* Timer/Counter5 Capture Event */ -+#define TIMER5_CAPT_vect _VECTOR(46) -+#define TIMER5_CAPT_vect_num 46 -+ -+/* Timer/Counter5 Compare Match A */ -+#define TIMER5_COMPA_vect _VECTOR(47) -+#define TIMER5_COMPA_vect_num 47 -+ -+/* Timer/Counter5 Compare Match B */ -+#define TIMER5_COMPB_vect _VECTOR(48) -+#define TIMER5_COMPB_vect_num 48 -+ -+/* Timer/Counter5 Compare Match C */ -+#define TIMER5_COMPC_vect _VECTOR(49) -+#define TIMER5_COMPC_vect_num 49 -+ -+/* Timer/Counter5 Overflow */ -+#define TIMER5_OVF_vect _VECTOR(50) -+#define TIMER5_OVF_vect_num 50 -+ -+/* USART2, Rx Complete */ -+#define USART2_RX_vect _VECTOR(51) -+#define USART2_RX_vect_num 51 -+ -+/* USART2 Data register Empty */ -+#define USART2_UDRE_vect _VECTOR(52) -+#define USART2_UDRE_vect_num 52 -+ -+/* USART2, Tx Complete */ -+#define USART2_TX_vect _VECTOR(53) -+#define USART2_TX_vect_num 53 -+ -+/* USART3, Rx Complete */ -+#define USART3_RX_vect _VECTOR(54) -+#define USART3_RX_vect_num 54 -+ -+/* USART3 Data register Empty */ -+#define USART3_UDRE_vect _VECTOR(55) -+#define USART3_UDRE_vect_num 55 -+ -+/* USART3, Tx Complete */ -+#define USART3_TX_vect _VECTOR(56) -+#define USART3_TX_vect_num 56 -+ -+/* TRX24 - PLL lock interrupt */ -+#define TRX24_PLL_LOCK_vect _VECTOR(57) -+#define TRX24_PLL_LOCK_vect_num 57 -+ -+/* TRX24 - PLL unlock interrupt */ -+#define TRX24_PLL_UNLOCK_vect _VECTOR(58) -+#define TRX24_PLL_UNLOCK_vect_num 58 -+ -+/* TRX24 - Receive start interrupt */ -+#define TRX24_RX_START_vect _VECTOR(59) -+#define TRX24_RX_START_vect_num 59 -+ -+/* TRX24 - RX_END interrupt */ -+#define TRX24_RX_END_vect _VECTOR(60) -+#define TRX24_RX_END_vect_num 60 -+ -+/* TRX24 - CCA/ED done interrupt */ -+#define TRX24_CCA_ED_DONE_vect _VECTOR(61) -+#define TRX24_CCA_ED_DONE_vect_num 61 -+ -+/* TRX24 - XAH - AMI */ -+#define TRX24_XAH_AMI_vect _VECTOR(62) -+#define TRX24_XAH_AMI_vect_num 62 -+ -+/* TRX24 - TX_END interrupt */ -+#define TRX24_TX_END_vect _VECTOR(63) -+#define TRX24_TX_END_vect_num 63 -+ -+/* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */ -+#define TRX24_AWAKE_vect _VECTOR(64) -+#define TRX24_AWAKE_vect_num 64 -+ -+/* Symbol counter - compare match 1 interrupt */ -+#define SCNT_CMP1_vect _VECTOR(65) -+#define SCNT_CMP1_vect_num 65 -+ -+/* Symbol counter - compare match 2 interrupt */ -+#define SCNT_CMP2_vect _VECTOR(66) -+#define SCNT_CMP2_vect_num 66 -+ -+/* Symbol counter - compare match 3 interrupt */ -+#define SCNT_CMP3_vect _VECTOR(67) -+#define SCNT_CMP3_vect_num 67 -+ -+/* Symbol counter - overflow interrupt */ -+#define SCNT_OVFL_vect _VECTOR(68) -+#define SCNT_OVFL_vect_num 68 -+ -+/* Symbol counter - backoff interrupt */ -+#define SCNT_BACKOFF_vect _VECTOR(69) -+#define SCNT_BACKOFF_vect_num 69 -+ -+/* AES engine ready interrupt */ -+#define AES_READY_vect _VECTOR(70) -+#define AES_READY_vect_num 70 -+ -+/* Battery monitor indicates supply voltage below threshold */ -+#define BAT_LOW_vect _VECTOR(71) -+#define BAT_LOW_vect_num 71 -+ -+/* TRX24 TX start interrupt */ -+#define TRX24_TX_START_vect _VECTOR(72) -+#define TRX24_TX_START_vect_num 72 -+ -+/* Address match interrupt of address filter 0 */ -+#define TRX24_AMI0_vect _VECTOR(73) -+#define TRX24_AMI0_vect_num 73 -+ -+/* Address match interrupt of address filter 1 */ -+#define TRX24_AMI1_vect _VECTOR(74) -+#define TRX24_AMI1_vect_num 74 -+ -+/* Address match interrupt of address filter 2 */ -+#define TRX24_AMI2_vect _VECTOR(75) -+#define TRX24_AMI2_vect_num 75 -+ -+/* Address match interrupt of address filter 3 */ -+#define TRX24_AMI3_vect _VECTOR(76) -+#define TRX24_AMI3_vect_num 76 -+ -+#define _VECTORS_SIZE 308 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 256 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x3FFFF -+#define RAMSTART 0x0200 -+#define RAMSIZE 32768 -+#define RAMEND 0x81FF -+#define E2START 0 -+#define E2SIZE 8192 -+#define E2PAGESIZE 8 -+#define E2END 0x1FFF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_CKSEL_SUT0 (unsigned char)~_BV(0) -+#define FUSE_CKSEL_SUT1 (unsigned char)~_BV(1) -+#define FUSE_CKSEL_SUT2 (unsigned char)~_BV(2) -+#define FUSE_CKSEL_SUT3 (unsigned char)~_BV(3) -+#define FUSE_CKSEL_SUT4 (unsigned char)~_BV(4) -+#define FUSE_CKSEL_SUT5 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_JTAGEN (unsigned char)~_BV(6) -+#define FUSE_OCDEN (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0xA8 -+#define SIGNATURE_2 0x02 -+ -+ -+#endif /* #ifdef _AVR_ATMEGA256RFR2_H_INCLUDED */ -+ -diff --git a/include/avr/iom324a.h b/include/avr/iom324a.h -new file mode 100644 -index 0000000..85ddfb1 ---- /dev/null -+++ b/include/avr/iom324a.h -@@ -0,0 +1,924 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATMEGA324A_H_INCLUDED -+#define _AVR_ATMEGA324A_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iom324a.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINA _SFR_IO8(0x00) -+#define PINA7 7 -+#define PINA6 6 -+#define PINA5 5 -+#define PINA4 4 -+#define PINA3 3 -+#define PINA2 2 -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x01) -+#define DDRA7 7 -+#define DDRA6 6 -+#define DDRA5 5 -+#define DDRA4 4 -+#define DDRA3 3 -+#define DDRA2 2 -+#define DDRA1 1 -+#define DDRA0 0 -+ -+#define PORTA _SFR_IO8(0x02) -+#define PORTA7 7 -+#define PORTA6 6 -+#define PORTA5 5 -+#define PORTA4 4 -+#define PORTA3 3 -+#define PORTA2 2 -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x06) -+#define PINC7 7 -+#define PINC6 6 -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x07) -+#define DDRC7 7 -+#define DDRC6 6 -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x08) -+#define PORTC7 7 -+#define PORTC6 6 -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PIND _SFR_IO8(0x09) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0A) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x0B) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+/* Reserved [0x0C..0x14] */ -+ -+#define TIFR0 _SFR_IO8(0x15) -+#define TOV0 0 -+#define OCF0A 1 -+#define OCF0B 2 -+ -+#define TIFR1 _SFR_IO8(0x16) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define ICF1 5 -+ -+#define TIFR2 _SFR_IO8(0x17) -+#define TOV2 0 -+#define OCF2A 1 -+#define OCF2B 2 -+ -+/* Reserved [0x18..0x1A] */ -+ -+#define PCIFR _SFR_IO8(0x1B) -+#define PCIF0 0 -+#define PCIF1 1 -+#define PCIF2 2 -+#define PCIF3 3 -+ -+#define EIFR _SFR_IO8(0x1C) -+#define INTF0 0 -+#define INTF1 1 -+#define INTF2 2 -+ -+#define EIMSK _SFR_IO8(0x1D) -+#define INT0 0 -+#define INT1 1 -+#define INT2 2 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+#define GPIOR00 0 -+#define GPIOR01 1 -+#define GPIOR02 2 -+#define GPIOR03 3 -+#define GPIOR04 4 -+#define GPIOR05 5 -+#define GPIOR06 6 -+#define GPIOR07 7 -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEPE 1 -+#define EEMPE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSRSYNC 0 -+#define TSM 7 -+#define PSRASY 1 -+ -+#define TCCR0A _SFR_IO8(0x24) -+#define WGM00 0 -+#define WGM01 1 -+#define COM0B0 4 -+#define COM0B1 5 -+#define COM0A0 6 -+#define COM0A1 7 -+ -+#define TCCR0B _SFR_IO8(0x25) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define WGM02 3 -+#define FOC0B 6 -+#define FOC0A 7 -+ -+#define TCNT0 _SFR_IO8(0x26) -+ -+#define OCR0A _SFR_IO8(0x27) -+ -+#define OCR0B _SFR_IO8(0x28) -+ -+/* Reserved [0x29] */ -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+#define GPIOR10 0 -+#define GPIOR11 1 -+#define GPIOR12 2 -+#define GPIOR13 3 -+#define GPIOR14 4 -+#define GPIOR15 5 -+#define GPIOR16 6 -+#define GPIOR17 7 -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+#define GPIOR20 0 -+#define GPIOR21 1 -+#define GPIOR22 2 -+#define GPIOR23 3 -+#define GPIOR24 4 -+#define GPIOR25 5 -+#define GPIOR26 6 -+#define GPIOR27 7 -+ -+#define SPCR0 _SFR_IO8(0x2C) -+#define SPR00 0 -+#define SPR10 1 -+#define CPHA0 2 -+#define CPOL0 3 -+#define MSTR0 4 -+#define DORD0 5 -+#define SPE0 6 -+#define SPIE0 7 -+ -+#define SPSR0 _SFR_IO8(0x2D) -+#define SPI2X0 0 -+#define WCOL0 6 -+#define SPIF0 7 -+ -+#define SPDR0 _SFR_IO8(0x2E) -+ -+/* Reserved [0x2F] */ -+ -+#define ACSR _SFR_IO8(0x30) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACBG 6 -+#define ACD 7 -+ -+#define OCDR _SFR_IO8(0x31) -+#define OCDR7 7 -+#define OCDR6 6 -+#define OCDR5 5 -+#define OCDR4 4 -+#define OCDR3 3 -+#define OCDR2 2 -+#define OCDR1 1 -+#define OCDR0 0 -+ -+/* Reserved [0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define JTRF 4 -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define JTD 7 -+#define IVCE 0 -+#define IVSEL 1 -+#define PUD 4 -+ -+/* Reserved [0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define SIGRD 5 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+/* Reserved [0x38..0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCSR _SFR_MEM8(0x60) -+#define WDE 3 -+#define WDCE 4 -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDP3 5 -+#define WDIE 6 -+#define WDIF 7 -+ -+#define CLKPR _SFR_MEM8(0x61) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+#define CLKPCE 7 -+ -+/* Reserved [0x62..0x63] */ -+ -+#define PRR0 _SFR_MEM8(0x64) -+#define PRADC 0 -+#define PRUSART0 1 -+#define PRSPI 2 -+#define PRTIM1 3 -+#define PRUSART1 4 -+#define PRTIM0 5 -+#define PRTIM2 6 -+#define PRTWI 7 -+ -+/* Reserved [0x65] */ -+ -+#define OSCCAL _SFR_MEM8(0x66) -+#define OSCCAL0 0 -+#define OSCCAL1 1 -+#define OSCCAL2 2 -+#define OSCCAL3 3 -+#define OSCCAL4 4 -+#define OSCCAL5 5 -+#define OSCCAL6 6 -+#define OSCCAL7 7 -+ -+/* Reserved [0x67] */ -+ -+#define PCICR _SFR_MEM8(0x68) -+#define PCIE0 0 -+#define PCIE1 1 -+#define PCIE2 2 -+#define PCIE3 3 -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+#define ISC20 4 -+#define ISC21 5 -+ -+/* Reserved [0x6A] */ -+ -+#define PCMSK0 _SFR_MEM8(0x6B) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6C) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+#define PCINT14 6 -+#define PCINT15 7 -+ -+#define PCMSK2 _SFR_MEM8(0x6D) -+#define PCINT16 0 -+#define PCINT17 1 -+#define PCINT18 2 -+#define PCINT19 3 -+#define PCINT20 4 -+#define PCINT21 5 -+#define PCINT22 6 -+#define PCINT23 7 -+ -+#define TIMSK0 _SFR_MEM8(0x6E) -+#define TOIE0 0 -+#define OCIE0A 1 -+#define OCIE0B 2 -+ -+#define TIMSK1 _SFR_MEM8(0x6F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define ICIE1 5 -+ -+#define TIMSK2 _SFR_MEM8(0x70) -+#define TOIE2 0 -+#define OCIE2A 1 -+#define OCIE2B 2 -+ -+/* Reserved [0x71..0x72] */ -+ -+#define PCMSK3 _SFR_MEM8(0x73) -+#define PCINT24 0 -+#define PCINT25 1 -+#define PCINT26 2 -+#define PCINT27 3 -+#define PCINT28 4 -+#define PCINT29 5 -+#define PCINT30 6 -+#define PCINT31 7 -+ -+/* Reserved [0x74..0x77] */ -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_MEM16(0x78) -+#endif -+#define ADCW _SFR_MEM16(0x78) -+ -+#define ADCL _SFR_MEM8(0x78) -+#define ADCH _SFR_MEM8(0x79) -+ -+#define ADCSRA _SFR_MEM8(0x7A) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADCSRB _SFR_MEM8(0x7B) -+#define ACME 6 -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+ -+#define ADMUX _SFR_MEM8(0x7C) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define MUX4 4 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+/* Reserved [0x7D] */ -+ -+#define DIDR0 _SFR_MEM8(0x7E) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+#define ADC6D 6 -+#define ADC7D 7 -+ -+#define DIDR1 _SFR_MEM8(0x7F) -+#define AIN0D 0 -+#define AIN1D 1 -+ -+#define TCCR1A _SFR_MEM8(0x80) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR1B _SFR_MEM8(0x81) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1C _SFR_MEM8(0x82) -+#define FOC1B 6 -+#define FOC1A 7 -+ -+/* Reserved [0x83] */ -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x84) -+ -+#define TCNT1L _SFR_MEM8(0x84) -+#define TCNT1H _SFR_MEM8(0x85) -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x86) -+ -+#define ICR1L _SFR_MEM8(0x86) -+#define ICR1H _SFR_MEM8(0x87) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_MEM16(0x88) -+ -+#define OCR1AL _SFR_MEM8(0x88) -+#define OCR1AH _SFR_MEM8(0x89) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_MEM16(0x8A) -+ -+#define OCR1BL _SFR_MEM8(0x8A) -+#define OCR1BH _SFR_MEM8(0x8B) -+ -+/* Reserved [0x8C..0xAF] */ -+ -+#define TCCR2A _SFR_MEM8(0xB0) -+#define WGM20 0 -+#define WGM21 1 -+#define COM2B0 4 -+#define COM2B1 5 -+#define COM2A0 6 -+#define COM2A1 7 -+ -+#define TCCR2B _SFR_MEM8(0xB1) -+#define CS20 0 -+#define CS21 1 -+#define CS22 2 -+#define WGM22 3 -+#define FOC2B 6 -+#define FOC2A 7 -+ -+#define TCNT2 _SFR_MEM8(0xB2) -+ -+#define OCR2A _SFR_MEM8(0xB3) -+ -+#define OCR2B _SFR_MEM8(0xB4) -+ -+/* Reserved [0xB5] */ -+ -+#define ASSR _SFR_MEM8(0xB6) -+#define TCR2BUB 0 -+#define TCR2AUB 1 -+#define OCR2BUB 2 -+#define OCR2AUB 3 -+#define TCN2UB 4 -+#define AS2 5 -+#define EXCLK 6 -+ -+/* Reserved [0xB7] */ -+ -+#define TWBR _SFR_MEM8(0xB8) -+ -+#define TWSR _SFR_MEM8(0xB9) -+#define TWPS0 0 -+#define TWPS1 1 -+#define TWS3 3 -+#define TWS4 4 -+#define TWS5 5 -+#define TWS6 6 -+#define TWS7 7 -+ -+#define TWAR _SFR_MEM8(0xBA) -+#define TWGCE 0 -+#define TWA0 1 -+#define TWA1 2 -+#define TWA2 3 -+#define TWA3 4 -+#define TWA4 5 -+#define TWA5 6 -+#define TWA6 7 -+ -+#define TWDR _SFR_MEM8(0xBB) -+ -+#define TWCR _SFR_MEM8(0xBC) -+#define TWIE 0 -+#define TWEN 2 -+#define TWWC 3 -+#define TWSTO 4 -+#define TWSTA 5 -+#define TWEA 6 -+#define TWINT 7 -+ -+#define TWAMR _SFR_MEM8(0xBD) -+#define TWAM0 1 -+#define TWAM1 2 -+#define TWAM2 3 -+#define TWAM3 4 -+#define TWAM4 5 -+#define TWAM5 6 -+#define TWAM6 7 -+ -+/* Reserved [0xBE..0xBF] */ -+ -+#define UCSR0A _SFR_MEM8(0xC0) -+#define MPCM0 0 -+#define U2X0 1 -+#define UPE0 2 -+#define DOR0 3 -+#define FE0 4 -+#define UDRE0 5 -+#define TXC0 6 -+#define RXC0 7 -+ -+#define UCSR0B _SFR_MEM8(0xC1) -+#define TXB80 0 -+#define RXB80 1 -+#define UCSZ02 2 -+#define TXEN0 3 -+#define RXEN0 4 -+#define UDRIE0 5 -+#define TXCIE0 6 -+#define RXCIE0 7 -+ -+#define UCSR0C _SFR_MEM8(0xC2) -+#define UCPOL0 0 -+#define UCSZ00 1 -+#define UCSZ01 2 -+#define USBS0 3 -+#define UPM00 4 -+#define UPM01 5 -+#define UMSEL00 6 -+#define UMSEL01 7 -+ -+/* Reserved [0xC3] */ -+ -+/* Combine UBRR0L and UBRR0H */ -+#define UBRR0 _SFR_MEM16(0xC4) -+ -+#define UBRR0L _SFR_MEM8(0xC4) -+#define UBRR0H _SFR_MEM8(0xC5) -+ -+#define UDR0 _SFR_MEM8(0xC6) -+ -+/* Reserved [0xC7] */ -+ -+#define UCSR1A _SFR_MEM8(0xC8) -+#define MPCM1 0 -+#define U2X1 1 -+#define UPE1 2 -+#define DOR1 3 -+#define FE1 4 -+#define UDRE1 5 -+#define TXC1 6 -+#define RXC1 7 -+ -+#define UCSR1B _SFR_MEM8(0xC9) -+#define TXB81 0 -+#define RXB81 1 -+#define UCSZ12 2 -+#define TXEN1 3 -+#define RXEN1 4 -+#define UDRIE1 5 -+#define TXCIE1 6 -+#define RXCIE1 7 -+ -+#define UCSR1C _SFR_MEM8(0xCA) -+#define UCPOL1 0 -+#define UCSZ10 1 -+#define UCSZ11 2 -+#define USBS1 3 -+#define UPM10 4 -+#define UPM11 5 -+#define UMSEL10 6 -+#define UMSEL11 7 -+ -+/* Reserved [0xCB] */ -+ -+/* Combine UBRR1L and UBRR1H */ -+#define UBRR1 _SFR_MEM16(0xCC) -+ -+#define UBRR1L _SFR_MEM8(0xCC) -+#define UBRR1H _SFR_MEM8(0xCD) -+ -+#define UDR1 _SFR_MEM8(0xCE) -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* External Interrupt Request 2 */ -+#define INT2_vect _VECTOR(3) -+#define INT2_vect_num 3 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(4) -+#define PCINT0_vect_num 4 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(5) -+#define PCINT1_vect_num 5 -+ -+/* Pin Change Interrupt Request 2 */ -+#define PCINT2_vect _VECTOR(6) -+#define PCINT2_vect_num 6 -+ -+/* Pin Change Interrupt Request 3 */ -+#define PCINT3_vect _VECTOR(7) -+#define PCINT3_vect_num 7 -+ -+/* Watchdog Time-out Interrupt */ -+#define WDT_vect _VECTOR(8) -+#define WDT_vect_num 8 -+ -+/* Timer/Counter2 Compare Match A */ -+#define TIMER2_COMPA_vect _VECTOR(9) -+#define TIMER2_COMPA_vect_num 9 -+ -+/* Timer/Counter2 Compare Match B */ -+#define TIMER2_COMPB_vect _VECTOR(10) -+#define TIMER2_COMPB_vect_num 10 -+ -+/* Timer/Counter2 Overflow */ -+#define TIMER2_OVF_vect _VECTOR(11) -+#define TIMER2_OVF_vect_num 11 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(12) -+#define TIMER1_CAPT_vect_num 12 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(13) -+#define TIMER1_COMPA_vect_num 13 -+ -+/* Timer/Counter1 Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(14) -+#define TIMER1_COMPB_vect_num 14 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(15) -+#define TIMER1_OVF_vect_num 15 -+ -+/* Timer/Counter0 Compare Match A */ -+#define TIMER0_COMPA_vect _VECTOR(16) -+#define TIMER0_COMPA_vect_num 16 -+ -+/* Timer/Counter0 Compare Match B */ -+#define TIMER0_COMPB_vect _VECTOR(17) -+#define TIMER0_COMPB_vect_num 17 -+ -+/* Timer/Counter0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(18) -+#define TIMER0_OVF_vect_num 18 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(19) -+#define SPI_STC_vect_num 19 -+ -+/* USART0, Rx Complete */ -+#define USART0_RX_vect _VECTOR(20) -+#define USART0_RX_vect_num 20 -+ -+/* USART0 Data register Empty */ -+#define USART0_UDRE_vect _VECTOR(21) -+#define USART0_UDRE_vect_num 21 -+ -+/* USART0, Tx Complete */ -+#define USART0_TX_vect _VECTOR(22) -+#define USART0_TX_vect_num 22 -+ -+/* Analog Comparator */ -+#define ANALOG_COMP_vect _VECTOR(23) -+#define ANALOG_COMP_vect_num 23 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(24) -+#define ADC_vect_num 24 -+ -+/* EEPROM Ready */ -+#define EE_READY_vect _VECTOR(25) -+#define EE_READY_vect_num 25 -+ -+/* 2-wire Serial Interface */ -+#define TWI_vect _VECTOR(26) -+#define TWI_vect_num 26 -+ -+/* Store Program Memory Read */ -+#define SPM_READY_vect _VECTOR(27) -+#define SPM_READY_vect_num 27 -+ -+/* USART1 RX complete */ -+#define USART1_RX_vect _VECTOR(28) -+#define USART1_RX_vect_num 28 -+ -+/* USART1 Data Register Empty */ -+#define USART1_UDRE_vect _VECTOR(29) -+#define USART1_UDRE_vect_num 29 -+ -+/* USART1 TX complete */ -+#define USART1_TX_vect _VECTOR(30) -+#define USART1_TX_vect_num 30 -+ -+#define _VECTORS_SIZE 124 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 128 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x7FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 2048 -+#define RAMEND 0x08FF -+#define E2START 0 -+#define E2SIZE 1024 -+#define E2PAGESIZE 4 -+#define E2END 0x03FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -+#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_JTAGEN (unsigned char)~_BV(6) -+#define FUSE_OCDEN (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x95 -+#define SIGNATURE_2 0x15 -+ -+ -+#endif /* #ifdef _AVR_ATMEGA324A_H_INCLUDED */ -+ -diff --git a/include/avr/iom324p.h b/include/avr/iom324p.h -new file mode 100644 -index 0000000..a600715 ---- /dev/null -+++ b/include/avr/iom324p.h -@@ -0,0 +1,926 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATMEGA324P_H_INCLUDED -+#define _AVR_ATMEGA324P_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iom324p.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINA _SFR_IO8(0x00) -+#define PINA7 7 -+#define PINA6 6 -+#define PINA5 5 -+#define PINA4 4 -+#define PINA3 3 -+#define PINA2 2 -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x01) -+#define DDRA7 7 -+#define DDRA6 6 -+#define DDRA5 5 -+#define DDRA4 4 -+#define DDRA3 3 -+#define DDRA2 2 -+#define DDRA1 1 -+#define DDRA0 0 -+ -+#define PORTA _SFR_IO8(0x02) -+#define PORTA7 7 -+#define PORTA6 6 -+#define PORTA5 5 -+#define PORTA4 4 -+#define PORTA3 3 -+#define PORTA2 2 -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x06) -+#define PINC7 7 -+#define PINC6 6 -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x07) -+#define DDRC7 7 -+#define DDRC6 6 -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x08) -+#define PORTC7 7 -+#define PORTC6 6 -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PIND _SFR_IO8(0x09) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0A) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x0B) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+/* Reserved [0x0C..0x14] */ -+ -+#define TIFR0 _SFR_IO8(0x15) -+#define TOV0 0 -+#define OCF0A 1 -+#define OCF0B 2 -+ -+#define TIFR1 _SFR_IO8(0x16) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define ICF1 5 -+ -+#define TIFR2 _SFR_IO8(0x17) -+#define TOV2 0 -+#define OCF2A 1 -+#define OCF2B 2 -+ -+/* Reserved [0x18..0x1A] */ -+ -+#define PCIFR _SFR_IO8(0x1B) -+#define PCIF0 0 -+#define PCIF1 1 -+#define PCIF2 2 -+#define PCIF3 3 -+ -+#define EIFR _SFR_IO8(0x1C) -+#define INTF0 0 -+#define INTF1 1 -+#define INTF2 2 -+ -+#define EIMSK _SFR_IO8(0x1D) -+#define INT0 0 -+#define INT1 1 -+#define INT2 2 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+#define GPIOR00 0 -+#define GPIOR01 1 -+#define GPIOR02 2 -+#define GPIOR03 3 -+#define GPIOR04 4 -+#define GPIOR05 5 -+#define GPIOR06 6 -+#define GPIOR07 7 -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEPE 1 -+#define EEMPE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSRSYNC 0 -+#define TSM 7 -+#define PSRASY 1 -+ -+#define TCCR0A _SFR_IO8(0x24) -+#define WGM00 0 -+#define WGM01 1 -+#define COM0B0 4 -+#define COM0B1 5 -+#define COM0A0 6 -+#define COM0A1 7 -+ -+#define TCCR0B _SFR_IO8(0x25) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define WGM02 3 -+#define FOC0B 6 -+#define FOC0A 7 -+ -+#define TCNT0 _SFR_IO8(0x26) -+ -+#define OCR0A _SFR_IO8(0x27) -+ -+#define OCR0B _SFR_IO8(0x28) -+ -+/* Reserved [0x29] */ -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+#define GPIOR10 0 -+#define GPIOR11 1 -+#define GPIOR12 2 -+#define GPIOR13 3 -+#define GPIOR14 4 -+#define GPIOR15 5 -+#define GPIOR16 6 -+#define GPIOR17 7 -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+#define GPIOR20 0 -+#define GPIOR21 1 -+#define GPIOR22 2 -+#define GPIOR23 3 -+#define GPIOR24 4 -+#define GPIOR25 5 -+#define GPIOR26 6 -+#define GPIOR27 7 -+ -+#define SPCR0 _SFR_IO8(0x2C) -+#define SPR00 0 -+#define SPR10 1 -+#define CPHA0 2 -+#define CPOL0 3 -+#define MSTR0 4 -+#define DORD0 5 -+#define SPE0 6 -+#define SPIE0 7 -+ -+#define SPSR0 _SFR_IO8(0x2D) -+#define SPI2X0 0 -+#define WCOL0 6 -+#define SPIF0 7 -+ -+#define SPDR0 _SFR_IO8(0x2E) -+ -+/* Reserved [0x2F] */ -+ -+#define ACSR _SFR_IO8(0x30) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACBG 6 -+#define ACD 7 -+ -+#define OCDR _SFR_IO8(0x31) -+#define OCDR7 7 -+#define OCDR6 6 -+#define OCDR5 5 -+#define OCDR4 4 -+#define OCDR3 3 -+#define OCDR2 2 -+#define OCDR1 1 -+#define OCDR0 0 -+ -+/* Reserved [0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define JTRF 4 -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define JTD 7 -+#define IVCE 0 -+#define IVSEL 1 -+#define PUD 4 -+#define BODSE 5 -+#define BODS 6 -+ -+/* Reserved [0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define SIGRD 5 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+/* Reserved [0x38..0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCSR _SFR_MEM8(0x60) -+#define WDE 3 -+#define WDCE 4 -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDP3 5 -+#define WDIE 6 -+#define WDIF 7 -+ -+#define CLKPR _SFR_MEM8(0x61) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+#define CLKPCE 7 -+ -+/* Reserved [0x62..0x63] */ -+ -+#define PRR0 _SFR_MEM8(0x64) -+#define PRADC 0 -+#define PRUSART0 1 -+#define PRSPI 2 -+#define PRTIM1 3 -+#define PRUSART1 4 -+#define PRTIM0 5 -+#define PRTIM2 6 -+#define PRTWI 7 -+ -+/* Reserved [0x65] */ -+ -+#define OSCCAL _SFR_MEM8(0x66) -+#define OSCCAL0 0 -+#define OSCCAL1 1 -+#define OSCCAL2 2 -+#define OSCCAL3 3 -+#define OSCCAL4 4 -+#define OSCCAL5 5 -+#define OSCCAL6 6 -+#define OSCCAL7 7 -+ -+/* Reserved [0x67] */ -+ -+#define PCICR _SFR_MEM8(0x68) -+#define PCIE0 0 -+#define PCIE1 1 -+#define PCIE2 2 -+#define PCIE3 3 -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+#define ISC20 4 -+#define ISC21 5 -+ -+/* Reserved [0x6A] */ -+ -+#define PCMSK0 _SFR_MEM8(0x6B) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6C) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+#define PCINT14 6 -+#define PCINT15 7 -+ -+#define PCMSK2 _SFR_MEM8(0x6D) -+#define PCINT16 0 -+#define PCINT17 1 -+#define PCINT18 2 -+#define PCINT19 3 -+#define PCINT20 4 -+#define PCINT21 5 -+#define PCINT22 6 -+#define PCINT23 7 -+ -+#define TIMSK0 _SFR_MEM8(0x6E) -+#define TOIE0 0 -+#define OCIE0A 1 -+#define OCIE0B 2 -+ -+#define TIMSK1 _SFR_MEM8(0x6F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define ICIE1 5 -+ -+#define TIMSK2 _SFR_MEM8(0x70) -+#define TOIE2 0 -+#define OCIE2A 1 -+#define OCIE2B 2 -+ -+/* Reserved [0x71..0x72] */ -+ -+#define PCMSK3 _SFR_MEM8(0x73) -+#define PCINT24 0 -+#define PCINT25 1 -+#define PCINT26 2 -+#define PCINT27 3 -+#define PCINT28 4 -+#define PCINT29 5 -+#define PCINT30 6 -+#define PCINT31 7 -+ -+/* Reserved [0x74..0x77] */ -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_MEM16(0x78) -+#endif -+#define ADCW _SFR_MEM16(0x78) -+ -+#define ADCL _SFR_MEM8(0x78) -+#define ADCH _SFR_MEM8(0x79) -+ -+#define ADCSRA _SFR_MEM8(0x7A) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADCSRB _SFR_MEM8(0x7B) -+#define ACME 6 -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+ -+#define ADMUX _SFR_MEM8(0x7C) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define MUX4 4 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+/* Reserved [0x7D] */ -+ -+#define DIDR0 _SFR_MEM8(0x7E) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+#define ADC6D 6 -+#define ADC7D 7 -+ -+#define DIDR1 _SFR_MEM8(0x7F) -+#define AIN0D 0 -+#define AIN1D 1 -+ -+#define TCCR1A _SFR_MEM8(0x80) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR1B _SFR_MEM8(0x81) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1C _SFR_MEM8(0x82) -+#define FOC1B 6 -+#define FOC1A 7 -+ -+/* Reserved [0x83] */ -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x84) -+ -+#define TCNT1L _SFR_MEM8(0x84) -+#define TCNT1H _SFR_MEM8(0x85) -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x86) -+ -+#define ICR1L _SFR_MEM8(0x86) -+#define ICR1H _SFR_MEM8(0x87) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_MEM16(0x88) -+ -+#define OCR1AL _SFR_MEM8(0x88) -+#define OCR1AH _SFR_MEM8(0x89) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_MEM16(0x8A) -+ -+#define OCR1BL _SFR_MEM8(0x8A) -+#define OCR1BH _SFR_MEM8(0x8B) -+ -+/* Reserved [0x8C..0xAF] */ -+ -+#define TCCR2A _SFR_MEM8(0xB0) -+#define WGM20 0 -+#define WGM21 1 -+#define COM2B0 4 -+#define COM2B1 5 -+#define COM2A0 6 -+#define COM2A1 7 -+ -+#define TCCR2B _SFR_MEM8(0xB1) -+#define CS20 0 -+#define CS21 1 -+#define CS22 2 -+#define WGM22 3 -+#define FOC2B 6 -+#define FOC2A 7 -+ -+#define TCNT2 _SFR_MEM8(0xB2) -+ -+#define OCR2A _SFR_MEM8(0xB3) -+ -+#define OCR2B _SFR_MEM8(0xB4) -+ -+/* Reserved [0xB5] */ -+ -+#define ASSR _SFR_MEM8(0xB6) -+#define TCR2BUB 0 -+#define TCR2AUB 1 -+#define OCR2BUB 2 -+#define OCR2AUB 3 -+#define TCN2UB 4 -+#define AS2 5 -+#define EXCLK 6 -+ -+/* Reserved [0xB7] */ -+ -+#define TWBR _SFR_MEM8(0xB8) -+ -+#define TWSR _SFR_MEM8(0xB9) -+#define TWPS0 0 -+#define TWPS1 1 -+#define TWS3 3 -+#define TWS4 4 -+#define TWS5 5 -+#define TWS6 6 -+#define TWS7 7 -+ -+#define TWAR _SFR_MEM8(0xBA) -+#define TWGCE 0 -+#define TWA0 1 -+#define TWA1 2 -+#define TWA2 3 -+#define TWA3 4 -+#define TWA4 5 -+#define TWA5 6 -+#define TWA6 7 -+ -+#define TWDR _SFR_MEM8(0xBB) -+ -+#define TWCR _SFR_MEM8(0xBC) -+#define TWIE 0 -+#define TWEN 2 -+#define TWWC 3 -+#define TWSTO 4 -+#define TWSTA 5 -+#define TWEA 6 -+#define TWINT 7 -+ -+#define TWAMR _SFR_MEM8(0xBD) -+#define TWAM0 1 -+#define TWAM1 2 -+#define TWAM2 3 -+#define TWAM3 4 -+#define TWAM4 5 -+#define TWAM5 6 -+#define TWAM6 7 -+ -+/* Reserved [0xBE..0xBF] */ -+ -+#define UCSR0A _SFR_MEM8(0xC0) -+#define MPCM0 0 -+#define U2X0 1 -+#define UPE0 2 -+#define DOR0 3 -+#define FE0 4 -+#define UDRE0 5 -+#define TXC0 6 -+#define RXC0 7 -+ -+#define UCSR0B _SFR_MEM8(0xC1) -+#define TXB80 0 -+#define RXB80 1 -+#define UCSZ02 2 -+#define TXEN0 3 -+#define RXEN0 4 -+#define UDRIE0 5 -+#define TXCIE0 6 -+#define RXCIE0 7 -+ -+#define UCSR0C _SFR_MEM8(0xC2) -+#define UCPOL0 0 -+#define UCSZ00 1 -+#define UCSZ01 2 -+#define USBS0 3 -+#define UPM00 4 -+#define UPM01 5 -+#define UMSEL00 6 -+#define UMSEL01 7 -+ -+/* Reserved [0xC3] */ -+ -+/* Combine UBRR0L and UBRR0H */ -+#define UBRR0 _SFR_MEM16(0xC4) -+ -+#define UBRR0L _SFR_MEM8(0xC4) -+#define UBRR0H _SFR_MEM8(0xC5) -+ -+#define UDR0 _SFR_MEM8(0xC6) -+ -+/* Reserved [0xC7] */ -+ -+#define UCSR1A _SFR_MEM8(0xC8) -+#define MPCM1 0 -+#define U2X1 1 -+#define UPE1 2 -+#define DOR1 3 -+#define FE1 4 -+#define UDRE1 5 -+#define TXC1 6 -+#define RXC1 7 -+ -+#define UCSR1B _SFR_MEM8(0xC9) -+#define TXB81 0 -+#define RXB81 1 -+#define UCSZ12 2 -+#define TXEN1 3 -+#define RXEN1 4 -+#define UDRIE1 5 -+#define TXCIE1 6 -+#define RXCIE1 7 -+ -+#define UCSR1C _SFR_MEM8(0xCA) -+#define UCPOL1 0 -+#define UCSZ10 1 -+#define UCSZ11 2 -+#define USBS1 3 -+#define UPM10 4 -+#define UPM11 5 -+#define UMSEL10 6 -+#define UMSEL11 7 -+ -+/* Reserved [0xCB] */ -+ -+/* Combine UBRR1L and UBRR1H */ -+#define UBRR1 _SFR_MEM16(0xCC) -+ -+#define UBRR1L _SFR_MEM8(0xCC) -+#define UBRR1H _SFR_MEM8(0xCD) -+ -+#define UDR1 _SFR_MEM8(0xCE) -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* External Interrupt Request 2 */ -+#define INT2_vect _VECTOR(3) -+#define INT2_vect_num 3 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(4) -+#define PCINT0_vect_num 4 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(5) -+#define PCINT1_vect_num 5 -+ -+/* Pin Change Interrupt Request 2 */ -+#define PCINT2_vect _VECTOR(6) -+#define PCINT2_vect_num 6 -+ -+/* Pin Change Interrupt Request 3 */ -+#define PCINT3_vect _VECTOR(7) -+#define PCINT3_vect_num 7 -+ -+/* Watchdog Time-out Interrupt */ -+#define WDT_vect _VECTOR(8) -+#define WDT_vect_num 8 -+ -+/* Timer/Counter2 Compare Match A */ -+#define TIMER2_COMPA_vect _VECTOR(9) -+#define TIMER2_COMPA_vect_num 9 -+ -+/* Timer/Counter2 Compare Match B */ -+#define TIMER2_COMPB_vect _VECTOR(10) -+#define TIMER2_COMPB_vect_num 10 -+ -+/* Timer/Counter2 Overflow */ -+#define TIMER2_OVF_vect _VECTOR(11) -+#define TIMER2_OVF_vect_num 11 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(12) -+#define TIMER1_CAPT_vect_num 12 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(13) -+#define TIMER1_COMPA_vect_num 13 -+ -+/* Timer/Counter1 Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(14) -+#define TIMER1_COMPB_vect_num 14 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(15) -+#define TIMER1_OVF_vect_num 15 -+ -+/* Timer/Counter0 Compare Match A */ -+#define TIMER0_COMPA_vect _VECTOR(16) -+#define TIMER0_COMPA_vect_num 16 -+ -+/* Timer/Counter0 Compare Match B */ -+#define TIMER0_COMPB_vect _VECTOR(17) -+#define TIMER0_COMPB_vect_num 17 -+ -+/* Timer/Counter0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(18) -+#define TIMER0_OVF_vect_num 18 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(19) -+#define SPI_STC_vect_num 19 -+ -+/* USART0, Rx Complete */ -+#define USART0_RX_vect _VECTOR(20) -+#define USART0_RX_vect_num 20 -+ -+/* USART0 Data register Empty */ -+#define USART0_UDRE_vect _VECTOR(21) -+#define USART0_UDRE_vect_num 21 -+ -+/* USART0, Tx Complete */ -+#define USART0_TX_vect _VECTOR(22) -+#define USART0_TX_vect_num 22 -+ -+/* Analog Comparator */ -+#define ANALOG_COMP_vect _VECTOR(23) -+#define ANALOG_COMP_vect_num 23 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(24) -+#define ADC_vect_num 24 -+ -+/* EEPROM Ready */ -+#define EE_READY_vect _VECTOR(25) -+#define EE_READY_vect_num 25 -+ -+/* 2-wire Serial Interface */ -+#define TWI_vect _VECTOR(26) -+#define TWI_vect_num 26 -+ -+/* Store Program Memory Read */ -+#define SPM_READY_vect _VECTOR(27) -+#define SPM_READY_vect_num 27 -+ -+/* USART1 RX complete */ -+#define USART1_RX_vect _VECTOR(28) -+#define USART1_RX_vect_num 28 -+ -+/* USART1 Data Register Empty */ -+#define USART1_UDRE_vect _VECTOR(29) -+#define USART1_UDRE_vect_num 29 -+ -+/* USART1 TX complete */ -+#define USART1_TX_vect _VECTOR(30) -+#define USART1_TX_vect_num 30 -+ -+#define _VECTORS_SIZE 124 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 128 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x7FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 2048 -+#define RAMEND 0x08FF -+#define E2START 0 -+#define E2SIZE 1024 -+#define E2PAGESIZE 4 -+#define E2END 0x03FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -+#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_JTAGEN (unsigned char)~_BV(6) -+#define FUSE_OCDEN (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x95 -+#define SIGNATURE_2 0x08 -+ -+ -+#endif /* #ifdef _AVR_ATMEGA324P_H_INCLUDED */ -+ -diff --git a/include/avr/iom3250a.h b/include/avr/iom3250a.h -new file mode 100644 -index 0000000..5c3add4 ---- /dev/null -+++ b/include/avr/iom3250a.h -@@ -0,0 +1,34 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2011 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+#include "iom3250.h" -diff --git a/include/avr/iom3250p.h b/include/avr/iom3250p.h -new file mode 100644 -index 0000000..5c3add4 ---- /dev/null -+++ b/include/avr/iom3250p.h -@@ -0,0 +1,34 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2011 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+#include "iom3250.h" -diff --git a/include/avr/iom3250pa.h b/include/avr/iom3250pa.h -new file mode 100644 -index 0000000..df89de4 ---- /dev/null -+++ b/include/avr/iom3250pa.h -@@ -0,0 +1,884 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATMEGA3250PA_H_INCLUDED -+#define _AVR_ATMEGA3250PA_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iom3250pa.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINA _SFR_IO8(0x00) -+#define PINA7 7 -+#define PINA6 6 -+#define PINA5 5 -+#define PINA4 4 -+#define PINA3 3 -+#define PINA2 2 -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x01) -+#define DDRA7 7 -+#define DDRA6 6 -+#define DDRA5 5 -+#define DDRA4 4 -+#define DDRA3 3 -+#define DDRA2 2 -+#define DDRA1 1 -+#define DDRA0 0 -+ -+#define PORTA _SFR_IO8(0x02) -+#define PORTA7 7 -+#define PORTA6 6 -+#define PORTA5 5 -+#define PORTA4 4 -+#define PORTA3 3 -+#define PORTA2 2 -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x06) -+#define PINC7 7 -+#define PINC6 6 -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x07) -+#define DDRC7 7 -+#define DDRC6 6 -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x08) -+#define PORTC7 7 -+#define PORTC6 6 -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PIND _SFR_IO8(0x09) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0A) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x0B) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+#define PINE _SFR_IO8(0x0C) -+#define PINE7 7 -+#define PINE6 6 -+#define PINE5 5 -+#define PINE4 4 -+#define PINE3 3 -+#define PINE2 2 -+#define PINE1 1 -+#define PINE0 0 -+ -+#define DDRE _SFR_IO8(0x0D) -+#define DDRE7 7 -+#define DDRE6 6 -+#define DDRE5 5 -+#define DDRE4 4 -+#define DDRE3 3 -+#define DDRE2 2 -+#define DDRE1 1 -+#define DDRE0 0 -+ -+#define PORTE _SFR_IO8(0x0E) -+#define PORTE7 7 -+#define PORTE6 6 -+#define PORTE5 5 -+#define PORTE4 4 -+#define PORTE3 3 -+#define PORTE2 2 -+#define PORTE1 1 -+#define PORTE0 0 -+ -+#define PINF _SFR_IO8(0x0F) -+#define PINF7 7 -+#define PINF6 6 -+#define PINF5 5 -+#define PINF4 4 -+#define PINF3 3 -+#define PINF2 2 -+#define PINF1 1 -+#define PINF0 0 -+ -+#define DDRF _SFR_IO8(0x10) -+#define DDRF7 7 -+#define DDRF6 6 -+#define DDRF5 5 -+#define DDRF4 4 -+#define DDRF3 3 -+#define DDRF2 2 -+#define DDRF1 1 -+#define DDRF0 0 -+ -+#define PORTF _SFR_IO8(0x11) -+#define PORTF7 7 -+#define PORTF6 6 -+#define PORTF5 5 -+#define PORTF4 4 -+#define PORTF3 3 -+#define PORTF2 2 -+#define PORTF1 1 -+#define PORTF0 0 -+ -+#define PING _SFR_IO8(0x12) -+#define PING5 5 -+#define PING4 4 -+#define PING3 3 -+#define PING2 2 -+#define PING1 1 -+#define PING0 0 -+ -+#define DDRG _SFR_IO8(0x13) -+#define DDRG4 4 -+#define DDRG3 3 -+#define DDRG2 2 -+#define DDRG1 1 -+#define DDRG0 0 -+ -+#define PORTG _SFR_IO8(0x14) -+#define PORTG4 4 -+#define PORTG3 3 -+#define PORTG2 2 -+#define PORTG1 1 -+#define PORTG0 0 -+ -+#define TIFR0 _SFR_IO8(0x15) -+#define TOV0 0 -+#define OCF0A 1 -+ -+#define TIFR1 _SFR_IO8(0x16) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define ICF1 5 -+ -+#define TIFR2 _SFR_IO8(0x17) -+#define TOV2 0 -+#define OCF2A 1 -+ -+/* Reserved [0x18..0x1B] */ -+ -+#define EIFR _SFR_IO8(0x1C) -+#define INTF0 0 -+#define PCIF0 4 -+#define PCIF1 5 -+#define PCIF2 6 -+#define PCIF3 7 -+ -+#define EIMSK _SFR_IO8(0x1D) -+#define INT0 0 -+#define PCIE0 4 -+#define PCIE1 5 -+#define PCIE2 6 -+#define PCIE3 7 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEWE 1 -+#define EEMWE 2 -+#define EERIE 3 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSR310 0 -+#define TSM 7 -+#define PSR2 1 -+ -+#define TCCR0A _SFR_IO8(0x24) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define WGM01 3 -+#define COM0A0 4 -+#define COM0A1 5 -+#define WGM00 6 -+#define FOC0A 7 -+ -+/* Reserved [0x25] */ -+ -+#define TCNT0 _SFR_IO8(0x26) -+ -+#define OCR0A _SFR_IO8(0x27) -+ -+/* Reserved [0x28..0x29] */ -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+/* Reserved [0x2F] */ -+ -+#define ACSR _SFR_IO8(0x30) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACBG 6 -+#define ACD 7 -+ -+#define OCDR _SFR_IO8(0x31) -+#define OCDR7 7 -+#define OCDR6 6 -+#define OCDR5 5 -+#define OCDR4 4 -+#define OCDR3 3 -+#define OCDR2 2 -+#define OCDR1 1 -+#define OCDR0 0 -+ -+/* Reserved [0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define JTRF 4 -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define JTD 7 -+#define IVCE 0 -+#define IVSEL 1 -+#define PUD 4 -+#define BODSE 5 -+#define BODS 6 -+ -+/* Reserved [0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+/* Reserved [0x38..0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCR _SFR_MEM8(0x60) -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDE 3 -+#define WDCE 4 -+ -+#define CLKPR _SFR_MEM8(0x61) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+#define CLKPCE 7 -+ -+/* Reserved [0x62..0x63] */ -+ -+#define PRR _SFR_MEM8(0x64) -+#define PRADC 0 -+#define PRUSART0 1 -+#define PRSPI 2 -+#define PRTIM1 3 -+#define PRLCD 4 -+ -+/* Reserved [0x65] */ -+ -+#define OSCCAL _SFR_MEM8(0x66) -+#define OSCCAL0 0 -+#define OSCCAL1 1 -+#define OSCCAL2 2 -+#define OSCCAL3 3 -+#define OSCCAL4 4 -+#define OSCCAL5 5 -+#define OSCCAL6 6 -+#define OSCCAL7 7 -+ -+/* Reserved [0x67..0x68] */ -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+ -+/* Reserved [0x6A] */ -+ -+#define PCMSK0 _SFR_MEM8(0x6B) -+ -+#define PCMSK1 _SFR_MEM8(0x6C) -+ -+#define PCMSK2 _SFR_MEM8(0x6D) -+ -+#define TIMSK0 _SFR_MEM8(0x6E) -+#define TOIE0 0 -+#define OCIE0A 1 -+ -+#define TIMSK1 _SFR_MEM8(0x6F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define ICIE1 5 -+ -+#define TIMSK2 _SFR_MEM8(0x70) -+#define TOIE2 0 -+#define OCIE2A 1 -+ -+/* Reserved [0x71..0x72] */ -+ -+#define PCMSK3 _SFR_MEM8(0x73) -+ -+/* Reserved [0x74..0x77] */ -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_MEM16(0x78) -+#endif -+#define ADCW _SFR_MEM16(0x78) -+ -+#define ADCL _SFR_MEM8(0x78) -+#define ADCH _SFR_MEM8(0x79) -+ -+#define ADCSRA _SFR_MEM8(0x7A) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADCSRB _SFR_MEM8(0x7B) -+#define ACME 6 -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+ -+#define ADMUX _SFR_MEM8(0x7C) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define MUX4 4 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+/* Reserved [0x7D] */ -+ -+#define DIDR0 _SFR_MEM8(0x7E) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+#define ADC6D 6 -+#define ADC7D 7 -+ -+#define DIDR1 _SFR_MEM8(0x7F) -+#define AIN0D 0 -+#define AIN1D 1 -+ -+#define TCCR1A _SFR_MEM8(0x80) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR1B _SFR_MEM8(0x81) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1C _SFR_MEM8(0x82) -+#define FOC1B 6 -+#define FOC1A 7 -+ -+/* Reserved [0x83] */ -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x84) -+ -+#define TCNT1L _SFR_MEM8(0x84) -+#define TCNT1H _SFR_MEM8(0x85) -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x86) -+ -+#define ICR1L _SFR_MEM8(0x86) -+#define ICR1H _SFR_MEM8(0x87) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_MEM16(0x88) -+ -+#define OCR1AL _SFR_MEM8(0x88) -+#define OCR1AH _SFR_MEM8(0x89) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_MEM16(0x8A) -+ -+#define OCR1BL _SFR_MEM8(0x8A) -+#define OCR1BH _SFR_MEM8(0x8B) -+ -+/* Reserved [0x8C..0xAF] */ -+ -+#define TCCR2A _SFR_MEM8(0xB0) -+#define CS20 0 -+#define CS21 1 -+#define CS22 2 -+#define WGM21 3 -+#define COM2A0 4 -+#define COM2A1 5 -+#define WGM20 6 -+#define FOC2A 7 -+ -+/* Reserved [0xB1] */ -+ -+#define TCNT2 _SFR_MEM8(0xB2) -+ -+#define OCR2A _SFR_MEM8(0xB3) -+ -+/* Reserved [0xB4..0xB5] */ -+ -+#define ASSR _SFR_MEM8(0xB6) -+#define TCR2UB 0 -+#define OCR2UB 1 -+#define TCN2UB 2 -+#define AS2 3 -+#define EXCLK 4 -+ -+/* Reserved [0xB7] */ -+ -+#define USICR _SFR_MEM8(0xB8) -+#define USITC 0 -+#define USICLK 1 -+#define USICS0 2 -+#define USICS1 3 -+#define USIWM0 4 -+#define USIWM1 5 -+#define USIOIE 6 -+#define USISIE 7 -+ -+#define USISR _SFR_MEM8(0xB9) -+#define USICNT0 0 -+#define USICNT1 1 -+#define USICNT2 2 -+#define USICNT3 3 -+#define USIDC 4 -+#define USIPF 5 -+#define USIOIF 6 -+#define USISIF 7 -+ -+#define USIDR _SFR_MEM8(0xBA) -+ -+/* Reserved [0xBB..0xBF] */ -+ -+#define UCSR0A _SFR_MEM8(0xC0) -+#define MPCM0 0 -+#define U2X0 1 -+#define UPE0 2 -+#define DOR0 3 -+#define FE0 4 -+#define UDRE0 5 -+#define TXC0 6 -+#define RXC0 7 -+ -+#define UCSR0B _SFR_MEM8(0xC1) -+#define TXB80 0 -+#define RXB80 1 -+#define UCSZ02 2 -+#define TXEN0 3 -+#define RXEN0 4 -+#define UDRIE0 5 -+#define TXCIE0 6 -+#define RXCIE0 7 -+ -+#define UCSR0C _SFR_MEM8(0xC2) -+#define UCPOL0 0 -+#define UCSZ00 1 -+#define UCSZ01 2 -+#define USBS0 3 -+#define UPM00 4 -+#define UPM01 5 -+#define UMSEL0 6 -+ -+/* Reserved [0xC3] */ -+ -+/* Combine UBRR0L and UBRR0H */ -+#define UBRR0 _SFR_MEM16(0xC4) -+ -+#define UBRR0L _SFR_MEM8(0xC4) -+#define UBRR0H _SFR_MEM8(0xC5) -+ -+#define UDR0 _SFR_MEM8(0xC6) -+ -+/* Reserved [0xC7..0xD7] */ -+ -+#define PINH _SFR_MEM8(0xD8) -+#define PINH7 7 -+#define PINH6 6 -+#define PINH5 5 -+#define PINH4 4 -+#define PINH3 3 -+#define PINH2 2 -+#define PINH1 1 -+#define PINH0 0 -+ -+#define DDRH _SFR_MEM8(0xD9) -+#define DDRH7 7 -+#define DDRH6 6 -+#define DDRH5 5 -+#define DDRH4 4 -+#define DDRH3 3 -+#define DDRH2 2 -+#define DDRH1 1 -+#define DDRH0 0 -+ -+#define PORTH _SFR_MEM8(0xDA) -+#define PORTH7 7 -+#define PORTH6 6 -+#define PORTH5 5 -+#define PORTH4 4 -+#define PORTH3 3 -+#define PORTH2 2 -+#define PORTH1 1 -+#define PORTH0 0 -+ -+#define PINJ _SFR_MEM8(0xDB) -+#define PINJ6 6 -+#define PINJ5 5 -+#define PINJ4 4 -+#define PINJ3 3 -+#define PINJ2 2 -+#define PINJ1 1 -+#define PINJ0 0 -+ -+#define DDRJ _SFR_MEM8(0xDC) -+#define DDRJ6 6 -+#define DDRJ5 5 -+#define DDRJ4 4 -+#define DDRJ3 3 -+#define DDRJ2 2 -+#define DDRJ1 1 -+#define DDRJ0 0 -+ -+#define PORTJ _SFR_MEM8(0xDD) -+#define PORTJ6 6 -+#define PORTJ5 5 -+#define PORTJ4 4 -+#define PORTJ3 3 -+#define PORTJ2 2 -+#define PORTJ1 1 -+#define PORTJ0 0 -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(2) -+#define PCINT0_vect_num 2 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(3) -+#define PCINT1_vect_num 3 -+ -+/* Timer/Counter2 Compare Match */ -+#define TIMER2_COMP_vect _VECTOR(4) -+#define TIMER2_COMP_vect_num 4 -+ -+/* Timer/Counter2 Overflow */ -+#define TIMER2_OVF_vect _VECTOR(5) -+#define TIMER2_OVF_vect_num 5 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(6) -+#define TIMER1_CAPT_vect_num 6 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(7) -+#define TIMER1_COMPA_vect_num 7 -+ -+/* Timer/Counter Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(8) -+#define TIMER1_COMPB_vect_num 8 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(9) -+#define TIMER1_OVF_vect_num 9 -+ -+/* Timer/Counter0 Compare Match */ -+#define TIMER0_COMP_vect _VECTOR(10) -+#define TIMER0_COMP_vect_num 10 -+ -+/* Timer/Counter0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(11) -+#define TIMER0_OVF_vect_num 11 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(12) -+#define SPI_STC_vect_num 12 -+ -+/* USART, Rx Complete */ -+#define USART_RX_vect _VECTOR(13) -+#define USART_RX_vect_num 13 -+ -+/* USART Data register Empty */ -+#define USART_UDRE_vect _VECTOR(14) -+#define USART_UDRE_vect_num 14 -+ -+/* USART0, Tx Complete */ -+#define USART0_TX_vect _VECTOR(15) -+#define USART0_TX_vect_num 15 -+ -+/* USI Start Condition */ -+#define USI_START_vect _VECTOR(16) -+#define USI_START_vect_num 16 -+ -+/* USI Overflow */ -+#define USI_OVERFLOW_vect _VECTOR(17) -+#define USI_OVERFLOW_vect_num 17 -+ -+/* Analog Comparator */ -+#define ANALOG_COMP_vect _VECTOR(18) -+#define ANALOG_COMP_vect_num 18 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(19) -+#define ADC_vect_num 19 -+ -+/* EEPROM Ready */ -+#define EE_READY_vect _VECTOR(20) -+#define EE_READY_vect_num 20 -+ -+/* Store Program Memory Read */ -+#define SPM_READY_vect _VECTOR(21) -+#define SPM_READY_vect_num 21 -+ -+/* RESERVED */ -+#define NOT_USED_vect _VECTOR(22) -+#define NOT_USED_vect_num 22 -+ -+/* Pin Change Interrupt Request 2 */ -+#define PCINT2_vect _VECTOR(23) -+#define PCINT2_vect_num 23 -+ -+/* Pin Change Interrupt Request 3 */ -+#define PCINT3_vect _VECTOR(24) -+#define PCINT3_vect_num 24 -+ -+#define _VECTORS_SIZE 100 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 128 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x7FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 2048 -+#define RAMEND 0x08FF -+#define E2START 0 -+#define E2SIZE 1024 -+#define E2PAGESIZE 4 -+#define E2END 0x03FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -+#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_JTAGEN (unsigned char)~_BV(6) -+#define FUSE_OCDEN (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x95 -+#define SIGNATURE_2 0x0E -+ -+ -+#endif /* #ifdef _AVR_ATMEGA3250PA_H_INCLUDED */ -+ -diff --git a/include/avr/iom325a.h b/include/avr/iom325a.h -new file mode 100644 -index 0000000..011b678 ---- /dev/null -+++ b/include/avr/iom325a.h -@@ -0,0 +1,34 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2011 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+#include "iom325.h" -diff --git a/include/avr/iom325p.h b/include/avr/iom325p.h -new file mode 100644 -index 0000000..011b678 ---- /dev/null -+++ b/include/avr/iom325p.h -@@ -0,0 +1,34 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2011 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+#include "iom325.h" -diff --git a/include/avr/iom325pa.h b/include/avr/iom325pa.h -new file mode 100644 -index 0000000..64828b2 ---- /dev/null -+++ b/include/avr/iom325pa.h -@@ -0,0 +1,809 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATMEGA325PA_H_INCLUDED -+#define _AVR_ATMEGA325PA_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iom325pa.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINA _SFR_IO8(0x00) -+#define PINA7 7 -+#define PINA6 6 -+#define PINA5 5 -+#define PINA4 4 -+#define PINA3 3 -+#define PINA2 2 -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x01) -+#define DDRA7 7 -+#define DDRA6 6 -+#define DDRA5 5 -+#define DDRA4 4 -+#define DDRA3 3 -+#define DDRA2 2 -+#define DDRA1 1 -+#define DDRA0 0 -+ -+#define PORTA _SFR_IO8(0x02) -+#define PORTA7 7 -+#define PORTA6 6 -+#define PORTA5 5 -+#define PORTA4 4 -+#define PORTA3 3 -+#define PORTA2 2 -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x06) -+#define PINC7 7 -+#define PINC6 6 -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x07) -+#define DDRC7 7 -+#define DDRC6 6 -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x08) -+#define PORTC7 7 -+#define PORTC6 6 -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PIND _SFR_IO8(0x09) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0A) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x0B) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+#define PINE _SFR_IO8(0x0C) -+#define PINE7 7 -+#define PINE6 6 -+#define PINE5 5 -+#define PINE4 4 -+#define PINE3 3 -+#define PINE2 2 -+#define PINE1 1 -+#define PINE0 0 -+ -+#define DDRE _SFR_IO8(0x0D) -+#define DDRE7 7 -+#define DDRE6 6 -+#define DDRE5 5 -+#define DDRE4 4 -+#define DDRE3 3 -+#define DDRE2 2 -+#define DDRE1 1 -+#define DDRE0 0 -+ -+#define PORTE _SFR_IO8(0x0E) -+#define PORTE7 7 -+#define PORTE6 6 -+#define PORTE5 5 -+#define PORTE4 4 -+#define PORTE3 3 -+#define PORTE2 2 -+#define PORTE1 1 -+#define PORTE0 0 -+ -+#define PINF _SFR_IO8(0x0F) -+#define PINF7 7 -+#define PINF6 6 -+#define PINF5 5 -+#define PINF4 4 -+#define PINF3 3 -+#define PINF2 2 -+#define PINF1 1 -+#define PINF0 0 -+ -+#define DDRF _SFR_IO8(0x10) -+#define DDRF7 7 -+#define DDRF6 6 -+#define DDRF5 5 -+#define DDRF4 4 -+#define DDRF3 3 -+#define DDRF2 2 -+#define DDRF1 1 -+#define DDRF0 0 -+ -+#define PORTF _SFR_IO8(0x11) -+#define PORTF7 7 -+#define PORTF6 6 -+#define PORTF5 5 -+#define PORTF4 4 -+#define PORTF3 3 -+#define PORTF2 2 -+#define PORTF1 1 -+#define PORTF0 0 -+ -+#define PING _SFR_IO8(0x12) -+#define PING5 5 -+#define PING4 4 -+#define PING3 3 -+#define PING2 2 -+#define PING1 1 -+#define PING0 0 -+ -+#define DDRG _SFR_IO8(0x13) -+#define DDRG4 4 -+#define DDRG3 3 -+#define DDRG2 2 -+#define DDRG1 1 -+#define DDRG0 0 -+ -+#define PORTG _SFR_IO8(0x14) -+#define PORTG4 4 -+#define PORTG3 3 -+#define PORTG2 2 -+#define PORTG1 1 -+#define PORTG0 0 -+ -+#define TIFR0 _SFR_IO8(0x15) -+#define TOV0 0 -+#define OCF0A 1 -+ -+#define TIFR1 _SFR_IO8(0x16) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define ICF1 5 -+ -+#define TIFR2 _SFR_IO8(0x17) -+#define TOV2 0 -+#define OCF2A 1 -+ -+/* Reserved [0x18..0x1B] */ -+ -+#define EIFR _SFR_IO8(0x1C) -+#define INTF0 0 -+#define PCIF0 4 -+#define PCIF1 5 -+#define PCIF2 6 -+#define PCIF3 7 -+ -+#define EIMSK _SFR_IO8(0x1D) -+#define INT0 0 -+#define PCIE0 4 -+#define PCIE1 5 -+#define PCIE2 6 -+#define PCIE3 7 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEWE 1 -+#define EEMWE 2 -+#define EERIE 3 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSR310 0 -+#define TSM 7 -+#define PSR2 1 -+ -+#define TCCR0A _SFR_IO8(0x24) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define WGM01 3 -+#define COM0A0 4 -+#define COM0A1 5 -+#define WGM00 6 -+#define FOC0A 7 -+ -+/* Reserved [0x25] */ -+ -+#define TCNT0 _SFR_IO8(0x26) -+ -+#define OCR0A _SFR_IO8(0x27) -+ -+/* Reserved [0x28..0x29] */ -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+/* Reserved [0x2F] */ -+ -+#define ACSR _SFR_IO8(0x30) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACBG 6 -+#define ACD 7 -+ -+#define OCDR _SFR_IO8(0x31) -+#define OCDR7 7 -+#define OCDR6 6 -+#define OCDR5 5 -+#define OCDR4 4 -+#define OCDR3 3 -+#define OCDR2 2 -+#define OCDR1 1 -+#define OCDR0 0 -+ -+/* Reserved [0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define JTRF 4 -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define JTD 7 -+#define IVCE 0 -+#define IVSEL 1 -+#define PUD 4 -+#define BODSE 5 -+#define BODS 6 -+ -+/* Reserved [0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+/* Reserved [0x38..0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCR _SFR_MEM8(0x60) -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDE 3 -+#define WDCE 4 -+ -+#define CLKPR _SFR_MEM8(0x61) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+#define CLKPCE 7 -+ -+/* Reserved [0x62..0x63] */ -+ -+#define PRR _SFR_MEM8(0x64) -+#define PRADC 0 -+#define PRUSART0 1 -+#define PRSPI 2 -+#define PRTIM1 3 -+#define PRLCD 4 -+ -+/* Reserved [0x65] */ -+ -+#define OSCCAL _SFR_MEM8(0x66) -+#define OSCCAL0 0 -+#define OSCCAL1 1 -+#define OSCCAL2 2 -+#define OSCCAL3 3 -+#define OSCCAL4 4 -+#define OSCCAL5 5 -+#define OSCCAL6 6 -+#define OSCCAL7 7 -+ -+/* Reserved [0x67..0x68] */ -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+ -+/* Reserved [0x6A] */ -+ -+#define PCMSK0 _SFR_MEM8(0x6B) -+ -+#define PCMSK1 _SFR_MEM8(0x6C) -+ -+/* Reserved [0x6D] */ -+ -+#define TIMSK0 _SFR_MEM8(0x6E) -+#define TOIE0 0 -+#define OCIE0A 1 -+ -+#define TIMSK1 _SFR_MEM8(0x6F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define ICIE1 5 -+ -+#define TIMSK2 _SFR_MEM8(0x70) -+#define TOIE2 0 -+#define OCIE2A 1 -+ -+/* Reserved [0x71..0x77] */ -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_MEM16(0x78) -+#endif -+#define ADCW _SFR_MEM16(0x78) -+ -+#define ADCL _SFR_MEM8(0x78) -+#define ADCH _SFR_MEM8(0x79) -+ -+#define ADCSRA _SFR_MEM8(0x7A) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADCSRB _SFR_MEM8(0x7B) -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+#define ACME 6 -+ -+#define ADMUX _SFR_MEM8(0x7C) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define MUX4 4 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+/* Reserved [0x7D] */ -+ -+#define DIDR0 _SFR_MEM8(0x7E) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+#define ADC6D 6 -+#define ADC7D 7 -+ -+#define DIDR1 _SFR_MEM8(0x7F) -+#define AIN0D 0 -+#define AIN1D 1 -+ -+#define TCCR1A _SFR_MEM8(0x80) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR1B _SFR_MEM8(0x81) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1C _SFR_MEM8(0x82) -+#define FOC1B 6 -+#define FOC1A 7 -+ -+/* Reserved [0x83] */ -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x84) -+ -+#define TCNT1L _SFR_MEM8(0x84) -+#define TCNT1H _SFR_MEM8(0x85) -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x86) -+ -+#define ICR1L _SFR_MEM8(0x86) -+#define ICR1H _SFR_MEM8(0x87) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_MEM16(0x88) -+ -+#define OCR1AL _SFR_MEM8(0x88) -+#define OCR1AH _SFR_MEM8(0x89) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_MEM16(0x8A) -+ -+#define OCR1BL _SFR_MEM8(0x8A) -+#define OCR1BH _SFR_MEM8(0x8B) -+ -+/* Reserved [0x8C..0xAF] */ -+ -+#define TCCR2A _SFR_MEM8(0xB0) -+#define CS20 0 -+#define CS21 1 -+#define CS22 2 -+#define WGM21 3 -+#define COM2A0 4 -+#define COM2A1 5 -+#define WGM20 6 -+#define FOC2A 7 -+ -+/* Reserved [0xB1] */ -+ -+#define TCNT2 _SFR_MEM8(0xB2) -+ -+#define OCR2A _SFR_MEM8(0xB3) -+ -+/* Reserved [0xB4..0xB5] */ -+ -+#define ASSR _SFR_MEM8(0xB6) -+#define TCR2UB 0 -+#define OCR2UB 1 -+#define TCN2UB 2 -+#define AS2 3 -+#define EXCLK 4 -+ -+/* Reserved [0xB7] */ -+ -+#define USICR _SFR_MEM8(0xB8) -+#define USITC 0 -+#define USICLK 1 -+#define USICS0 2 -+#define USICS1 3 -+#define USIWM0 4 -+#define USIWM1 5 -+#define USIOIE 6 -+#define USISIE 7 -+ -+#define USISR _SFR_MEM8(0xB9) -+#define USICNT0 0 -+#define USICNT1 1 -+#define USICNT2 2 -+#define USICNT3 3 -+#define USIDC 4 -+#define USIPF 5 -+#define USIOIF 6 -+#define USISIF 7 -+ -+#define USIDR _SFR_MEM8(0xBA) -+ -+/* Reserved [0xBB..0xBF] */ -+ -+#define UCSR0A _SFR_MEM8(0xC0) -+#define MPCM0 0 -+#define U2X0 1 -+#define UPE0 2 -+#define DOR0 3 -+#define FE0 4 -+#define UDRE0 5 -+#define TXC0 6 -+#define RXC0 7 -+ -+#define UCSR0B _SFR_MEM8(0xC1) -+#define TXB80 0 -+#define RXB80 1 -+#define UCSZ02 2 -+#define TXEN0 3 -+#define RXEN0 4 -+#define UDRIE0 5 -+#define TXCIE0 6 -+#define RXCIE0 7 -+ -+#define UCSR0C _SFR_MEM8(0xC2) -+#define UCPOL0 0 -+#define UCSZ00 1 -+#define UCSZ01 2 -+#define USBS0 3 -+#define UPM00 4 -+#define UPM01 5 -+#define UMSEL0 6 -+ -+/* Reserved [0xC3] */ -+ -+/* Combine UBRR0L and UBRR0H */ -+#define UBRR0 _SFR_MEM16(0xC4) -+ -+#define UBRR0L _SFR_MEM8(0xC4) -+#define UBRR0H _SFR_MEM8(0xC5) -+ -+#define UDR0 _SFR_MEM8(0xC6) -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(2) -+#define PCINT0_vect_num 2 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(3) -+#define PCINT1_vect_num 3 -+ -+/* Timer/Counter2 Compare Match */ -+#define TIMER2_COMP_vect _VECTOR(4) -+#define TIMER2_COMP_vect_num 4 -+ -+/* Timer/Counter2 Overflow */ -+#define TIMER2_OVF_vect _VECTOR(5) -+#define TIMER2_OVF_vect_num 5 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(6) -+#define TIMER1_CAPT_vect_num 6 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(7) -+#define TIMER1_COMPA_vect_num 7 -+ -+/* Timer/Counter Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(8) -+#define TIMER1_COMPB_vect_num 8 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(9) -+#define TIMER1_OVF_vect_num 9 -+ -+/* Timer/Counter0 Compare Match */ -+#define TIMER0_COMP_vect _VECTOR(10) -+#define TIMER0_COMP_vect_num 10 -+ -+/* Timer/Counter0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(11) -+#define TIMER0_OVF_vect_num 11 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(12) -+#define SPI_STC_vect_num 12 -+ -+/* USART0, Rx Complete */ -+#define USART0_RX_vect _VECTOR(13) -+#define USART0_RX_vect_num 13 -+ -+/* USART0 Data register Empty */ -+#define USART0_UDRE_vect _VECTOR(14) -+#define USART0_UDRE_vect_num 14 -+ -+/* USART0, Tx Complete */ -+#define USART0_TX_vect _VECTOR(15) -+#define USART0_TX_vect_num 15 -+ -+/* USI Start Condition */ -+#define USI_START_vect _VECTOR(16) -+#define USI_START_vect_num 16 -+ -+/* USI Overflow */ -+#define USI_OVERFLOW_vect _VECTOR(17) -+#define USI_OVERFLOW_vect_num 17 -+ -+/* Analog Comparator */ -+#define ANALOG_COMP_vect _VECTOR(18) -+#define ANALOG_COMP_vect_num 18 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(19) -+#define ADC_vect_num 19 -+ -+/* EEPROM Ready */ -+#define EE_READY_vect _VECTOR(20) -+#define EE_READY_vect_num 20 -+ -+/* Store Program Memory Read */ -+#define SPM_READY_vect _VECTOR(21) -+#define SPM_READY_vect_num 21 -+ -+#define _VECTORS_SIZE 88 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 128 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x7FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 2048 -+#define RAMEND 0x08FF -+#define E2START 0 -+#define E2SIZE 1024 -+#define E2PAGESIZE 4 -+#define E2END 0x03FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -+#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_JTAGEN (unsigned char)~_BV(6) -+#define FUSE_OCDEN (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x95 -+#define SIGNATURE_2 0x0D -+ -+ -+#endif /* #ifdef _AVR_ATMEGA325PA_H_INCLUDED */ -+ -diff --git a/include/avr/iom328.h b/include/avr/iom328.h -new file mode 100644 -index 0000000..44b9b39 ---- /dev/null -+++ b/include/avr/iom328.h -@@ -0,0 +1,34 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2011 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+#include "iom328p.h" -diff --git a/include/avr/iom328p.h b/include/avr/iom328p.h -index 2c9c9fe..d4f4a3c 100644 ---- a/include/avr/iom328p.h -+++ b/include/avr/iom328p.h -@@ -344,6 +344,7 @@ - #define PGWRT 2 - #define BLBSET 3 - #define RWWSRE 4 -+#define SIGRD 5 - #define RWWSB 6 - #define SPMIE 7 - -@@ -893,21 +894,22 @@ - #define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - - /* High Fuse Byte */ +-#define PRSPI 2 /* Power Reduction Serial Peripheral Interface */ +-#define PRTIM0 3 /* Power Reduction Timer/Counter0 */ +-#define PRTIM1 4 /* Power Reduction Timer/Counter1 */ +-#define PRPSC0 5 /* Power Reduction PSC0 */ +-#define PRPSC1 6 /* Power Reduction PSC1 */ +-#define PRPSC2 7 /* Power Reduction PSC2 */ +- +-/* Oscillator Calibration Value */ +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +- +-/* External Interrupt Control Register A */ +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define ISC20 4 +-#define ISC21 5 +-#define ISC30 6 +-#define ISC31 7 +- +-/* Timer/Counter0 Interrupt Mask Register */ +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 /* Overflow Interrupt Enable */ +-#define OCIE0A 1 /* Output Compare Match A Interrupt Enable */ +-#define OCIE0B 2 /* Output Compare Match B Interrupt Enable */ +- +-/* Timer/Counter1 Interrupt Mask Register */ +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 /* Overflow Interrupt Enable */ +-#define OCIE1A 1 /* Output Compare Match A Interrupt Enable */ +-#define OCIE1B 2 /* Output Compare Match B Interrupt Enable */ +-#define ICIE1 5 /* Input Capture Interrupt Enable */ +- +-/* Amplifier 0 Control and Status register */ +-#define AMP0CSR _SFR_MEM8(0x76) +-#define AMP0TS0 0 +-#define AMP0TS1 1 +-#define AMP0G0 4 +-#define AMP0G1 5 +-#define AMP0IS 6 +-#define AMP0EN 7 +- +-/* Amplifier 1 Control and Status register */ +-#define AMP1CSR _SFR_MEM8(0x77) +-#define AMP1TS0 0 +-#define AMP1TS1 1 +-#define AMP1G0 4 +-#define AMP1G1 5 +-#define AMP1IS 6 +-#define AMP1EN 7 +- +-/* ADC Result Data Register */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +-#define ADCL _SFR_MEM8(0x78) +-#define ADCH _SFR_MEM8(0x79) +- +-/* ADC Control and Status Register A */ +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 /* ADC Prescaler Select bit0 */ +-#define ADPS1 1 /* ADC Prescaler Select bit1 */ +-#define ADPS2 2 /* ADC Prescaler Select bit2 */ +-#define ADIE 3 /* ADC Interrupt Enable */ +-#define ADIF 4 /* ADC Interrupt Flag */ +-#define ADATE 5 /* ADC Auto Trigger Enable */ +-#define ADSC 6 /* ADC Start Conversion */ +-#define ADEN 7 /* ADC Enable */ +- +-/* ADC Control and Status Register B */ +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 /* ADC Auto Trigger Source 0 */ +-#define ADTS1 1 /* ADC Auto Trigger Source 1 */ +-#define ADTS2 2 /* ADC Auto Trigger Source 2 */ +-#define ADTS3 3 /* ADC Auto Trigger Source 3 */ +-#define ADHSM 7 /* ADC High Speed Mode */ +- +-/* ADC multiplexer Selection Register */ +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 /* Analog Channel and Gain Selection bit0 */ +-#define MUX1 1 /* Analog Channel and Gain Selection bit1 */ +-#define MUX2 2 /* Analog Channel and Gain Selection bit2 */ +-#define MUX3 3 /* Analog Channel and Gain Selection bit3 */ +-#define ADLAR 5 /* Left Adjust Result */ +-#define REFS0 6 /* Reference Selection bit0 */ +-#define REFS1 7 /* Reference Selection bit1 */ +- +-/* Digital Input Disable Register 0 */ +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 /* ADC0 Digital input Disable */ +-#define ADC1D 1 /* ADC1 Digital input Disable */ +-#define ADC2D 2 /* ADC2 Digital input Disable */ +-#define ADC3D 3 /* ADC3 Digital input Disable */ +-#define ADC4D 4 /* ADC4 Digital input Disable */ +-#define ADC5D 5 /* ADC5 Digital input Disable */ +-#define ADC6D 6 /* ADC6 Digital input Disable */ +-#define ADC7D 7 /* ADC7 Digital input Disable */ +- +-/* Digital Input Disable Register 1 */ +-#define DIDR1 _SFR_MEM8(0x7F) +-#define ADC8D 0 /* ADC8 Digital input Disable */ +-#define ADC9D 1 /* ADC9 Digital input Disable */ +-#define ADC10D 2 /* ADC10 Digital input Disable */ +-#define AMP0ND 3 +-#define AMP0PD 4 +-#define ACMP0D 5 +- +-/* Timer/Counter1 Control Register A */ +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 /* Waveform Generation Mode */ +-#define WGM11 1 /* Waveform Generation Mode */ +-#define COM1B0 4 /* Compare Output Mode 1B, bit 0 */ +-#define COM1B1 5 /* Compare Output Mode 1B, bit 1 */ +-#define COM1A0 6 /* Comparet Ouput Mode 1A, bit 0 */ +-#define COM1A1 7 /* Comparet Ouput Mode 1A, bit 1 */ +- +-/* Timer/Counter1 Control Register B */ +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 /* Prescaler source of Timer/Counter 1 */ +-#define CS11 1 /* Prescaler source of Timer/Counter 1 */ +-#define CS12 2 /* Prescaler source of Timer/Counter 1 */ +-#define WGM12 3 /* Waveform Generation Mode */ +-#define WGM13 4 /* Waveform Generation Mode */ +-#define ICES1 6 /* Input Capture 1 Edge Select */ +-#define ICNC1 7 /* Input Capture 1 Noise Canceler */ +- +-/* Timer/Counter1 Control Register C */ +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 /* Force Output Compare for Channel B */ +-#define FOC1A 7 /* Force Output Compare for Channel A */ +- +-/* Timer/Counter1 */ +-#define TCNT1 _SFR_MEM16(0x84) +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT10 0 +-#define TCNT11 1 +-#define TCNT12 2 +-#define TCNT13 3 +-#define TCNT14 4 +-#define TCNT15 5 +-#define TCNT16 6 +-#define TCNT17 7 +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT18 0 +-#define TCNT19 1 +-#define TCNT110 2 +-#define TCNT111 3 +-#define TCNT112 4 +-#define TCNT113 5 +-#define TCNT114 6 +-#define TCNT115 7 +- +-/* Input Capture Register 1 */ +-#define ICR1 _SFR_MEM16(0x86) +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR17 7 +-#define ICR16 6 +-#define ICR15 5 +-#define ICR14 4 +-#define ICR13 3 +-#define ICR12 2 +-#define ICR11 1 +-#define ICR10 0 +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR115 7 +-#define ICR114 6 +-#define ICR113 5 +-#define ICR112 4 +-#define ICR111 3 +-#define ICR110 2 +-#define ICR19 1 +-#define ICR18 0 +- +-/* Output Compare Register 1 A */ +-#define OCR1A _SFR_MEM16(0x88) +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1A0 0 +-#define OCR1A1 1 +-#define OCR1A2 2 +-#define OCR1A3 3 +-#define OCR1A4 4 +-#define OCR1A5 5 +-#define OCR1A6 6 +-#define OCR1A7 7 +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1A8 0 +-#define OCR1A9 1 +-#define OCR1A10 2 +-#define OCR1A11 3 +-#define OCR1A12 4 +-#define OCR1A13 5 +-#define OCR1A14 6 +-#define OCR1A15 7 +- +-/* Output Compare Register 1 B */ +-#define OCR1B _SFR_MEM16(0x8A) +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1B0 0 +-#define OCR1B1 1 +-#define OCR1B2 2 +-#define OCR1B3 3 +-#define OCR1B4 4 +-#define OCR1B5 5 +-#define OCR1B6 6 +-#define OCR1B7 7 +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1B8 0 +-#define OCR1B9 1 +-#define OCR1B10 2 +-#define OCR1B11 3 +-#define OCR1B12 4 +-#define OCR1B13 5 +-#define OCR1B14 6 +-#define OCR1B15 7 +- +-/* PSC0 Interrupt Flag Register */ +-#define PIFR0 _SFR_MEM8(0xA0) +-#define PEOP0 0 /* End Of PSC0 Interrupt */ +-#define PRN00 1 /* PSC0 Ramp Number bit0 */ +-#define PRN01 2 /* PSC0 Ramp Number bit1 */ +-#define PEV0A 3 /* PSC0 External Event A Interrupt */ +-#define PEV0B 4 /* PSC0 External Event B Interrupt */ +-#define PSEI0 5 /* PSC0 Synchro Error Interrupt */ +-#define POAC0A 6 /* PSC0 Output A Activity */ +-#define POAC0B 7 /* PSC0 Output B Activity */ +- +-/* PSC0 Interrupt Mask Register */ +-#define PIM0 _SFR_MEM8(0xA1) +-#define PEOPE0 0 /* PSC0 End Of Cycle Interrupt Enable */ +-#define PEVE0A 3 /* PSC0 External Event A Interrupt Enable */ +-#define PEVE0B 4 /* PSC0 External Event B Interrupt Enable */ +-#define PSEIE0 5 /* PSC0 Synchro Error Interrupt Enable */ +- +-/* PSC1 Interrupt Flag Register */ +-#define PIFR1 _SFR_MEM8(0xA2) +- +-/* PSC1 Interrupt Mask Register */ +-#define PIM1 _SFR_MEM8(0xA3) +- +-/* PSC2 Interrupt Flag Register */ +-#define PIFR2 _SFR_MEM8(0xA4) +-#define PEOP2 0 /* End Of PSC2 Interrupt */ +-#define PRN20 1 /* PSC2 Ramp Number bit0 */ +-#define PRN21 2 /* PSC2 Ramp Number bit1 */ +-#define PEV2A 3 /* PSC2 External Event A Interrupt */ +-#define PEV2B 4 /* PSC2 External Event B Interrupt */ +-#define PSEI2 5 /* PSC2 Synchro Error Interrupt */ +-#define POAC2A 6 /* PSC2 Output A Activity */ +-#define POAC2B 7 /* PSC2 Output B Activity */ +- +-/* PSC2 Interrupt Mask Register */ +-#define PIM2 _SFR_MEM8(0xA5) +-#define PEOPE2 0 /* PSC2 End Of Cycle Interrupt Enable */ +-#define PEVE2A 3 /* PSC2 External Event A Interrupt Enable */ +-#define PEVE2B 4 /* PSC2 External Event B Interrupt Enable */ +-#define PSEIE2 5 /* PSC2 Synchro Error Interrupt Enable */ +- +-/* Digital to Analog Conversion Control Register */ +-#define DACON _SFR_MEM8(0xAA) +-#define DAEN 0 /* Digital to Analog Enable bit */ +-#define DAOE 1 /* Digital to Analog Output Enable bit */ +-#define DALA 2 /* Digital to Analog Left Adjust */ +-#define DATS0 4 /* DAC Trigger Selection bit0 */ +-#define DATS1 5 /* DAC Trigger Selection bit1 */ +-#define DATS2 6 /* DAC Trigger Selection bit2 */ +-#define DAATE 7 /* DAC Auto Trigger Enable bit */ +- +-/* Digital to Analog Converter input Register */ +-#define DAC _SFR_MEM16(0xAB) +-#define DACL _SFR_MEM8(0xAB) +-#define DACH _SFR_MEM8(0xAC) +- +-/* Analog Comparator 0 Control Register */ +-#define AC0CON _SFR_MEM8(0xAD) +-#define AC0M0 0 /* Analog Comparator 0 Multiplexer register bit0 */ +-#define AC0M1 1 /* Analog Comparator 0 Multiplexer register bit1 */ +-#define AC0M2 2 /* Analog Comparator 0 Multiplexer register bit2 */ +-#define AC0IS0 4 /* Analog Comparator 0 Interrupt Select bit0 */ +-#define AC0IS1 5 /* Analog Comparator 0 Interrupt Select bit1 */ +-#define AC0IE 6 /* Analog Comparator 0 Interrupt Enable bit */ +-#define AC0EN 7 /* Analog Comparator 0 Enable Bit */ +- +-/* Analog Comparator 1 Control Register */ +-#define AC1CON _SFR_MEM8(0xAE) +-#define AC1M0 0 /* Analog Comparator 1 Multiplexer register bit0 */ +-#define AC1M1 1 /* Analog Comparator 1 Multiplexer register bit1 */ +-#define AC1M2 2 /* Analog Comparator 1 Multiplexer register bit2 */ +-#define AC1ICE 3 /* Analog Comparator 1 Interrupt Capture Enable bit */ +-#define AC1IS0 4 /* Analog Comparator 1 Interrupt Select bit0 */ +-#define AC1IS1 5 /* Analog Comparator 1 Interrupt Select bit1 */ +-#define AC1IE 6 /* Analog Comparator 1 Interrupt Enable bit */ +-#define AC1EN 7 /* Analog Comparator 1 Enable Bit */ +- +-/* Analog Comparator 2 Control Register */ +-#define AC2CON _SFR_MEM8(0xAF) +-#define AC2M0 0 /* Analog Comparator 2 Multiplexer register bit0 */ +-#define AC2M1 1 /* Analog Comparator 2 Multiplexer register bit1 */ +-#define AC2M2 2 /* Analog Comparator 2 Multiplexer register bit2 */ +-#define AC2IS0 4 /* Analog Comparator 2 Interrupt Select bit0 */ +-#define AC2IS1 5 /* Analog Comparator 2 Interrupt Select bit1 */ +-#define AC2IE 6 /* Analog Comparator 2 Interrupt Enable bit */ +-#define AC2EN 7 /* Analog Comparator 2 Enable Bit */ +- +-/* USART Control and Status Register A */ +-#define UCSRA _SFR_MEM8(0xC0) +-#define MPCM 0 /* Multi-processor Communication Mode */ +-#define U2X 1 /* Double the USART Transmission Speed */ +-#define UPE 2 /* USART Parity Error */ +-#define DOR 3 /* Data OverRun */ +-#define FE 4 /* Frame Error */ +-#define UDRE 5 /* USART Data Register Empty */ +-#define TXC 6 /* USART Transmit Complete */ +-#define RXC 7 /* USART Receive Complete */ +- +-/* USART Control and Status Register B */ +-#define UCSRB _SFR_MEM8(0xC1) +-#define TXB8 0 /* Transmit Data Bit 8 */ +-#define RXB8 1 /* Receive Data Bit 8 */ +-#define UCSZ2 2 /* Character Size */ +-#define TXEN 3 /* Transmitter Enable */ +-#define RXEN 4 /* Receiver Enable */ +-#define UDRIE 5 /* USART Data Register Empty Interrupt Enable */ +-#define TXCIE 6 /* TX Complete Interrupt Enable */ +-#define RXCIE 7 /* RX Complete Interrupt Enable */ +- +-/* USART Control and Status Register C */ +-#define UCSRC _SFR_MEM8(0xC2) +-#define UCPOL 0 /* Clock Polarity */ +-#define UCSZ0 1 /* Character Size bit0 */ +-#define UCSZ1 2 /* Character Size bit1 */ +-#define USBS 3 /* Stop Bit Select */ +-#define UPM0 4 /* Parity Mode bit0 */ +-#define UPM1 5 /* Parity Mode bit1 */ +-#define UMSEL 6 /* USART Mode Select */ +- +-/* USART Baud Rate Register */ +-#define UBRR _SFR_MEM16(0xC4) +-#define UBRRL _SFR_MEM8(0xC4) +-#define UBRRH _SFR_MEM8(0xC5) +- +-/* USART I/O Data Register */ +-#define UDR _SFR_MEM8(0xC6) +- +-/* EUSART Control and Status Register A */ +-#define EUCSRA _SFR_MEM8(0xC8) +-#define URxS0 0 /* EUSART Receive Character Size bit0 */ +-#define URxS1 1 /* EUSART Receive Character Size bit1 */ +-#define URxS2 2 /* EUSART Receive Character Size bit2 */ +-#define URxS3 3 /* EUSART Receive Character Size bit3 */ +-#define UTxS0 4 /* EUSART Transmit Character Size bit0 */ +-#define UTxS1 5 /* EUSART Transmit Character Size bit1 */ +-#define UTxS2 6 /* EUSART Transmit Character Size bit2 */ +-#define UTxS3 7 /* EUSART Transmit Character Size bit3 */ +- +-/* EUSART Control and Status Register B */ +-#define EUCSRB _SFR_MEM8(0xC9) +-#define BODR 0 /* Bit Order */ +-#define EMCH 1 /* Manchester mode */ +-#define EUSBS 3 /* EUSBS Enable Bit */ +-#define EUSART 4 /* EUSART Enable Bit */ +- +-/* EUSART Control and Status Register C */ +-#define EUCSRC _SFR_MEM8(0xCA) +-#define STP0 0 /* Stop bits values bit0 */ +-#define STP1 1 /* Stop bits values bit1 */ +-#define F1617 2 +-#define FEM 3 /* Frame Error Manchester */ +- +-/* Manchester receiver Baud Rate Registers */ +-#define MUBRR _SFR_MEM16(0xCC) +-#define MUBRRL _SFR_MEM8(0xCC) +-#define MUBRRH _SFR_MEM8(0xCD) +- +-/* EUSART I/O Data Register */ +-#define EUDR _SFR_MEM8(0xCE) +- +-/* PSC 0 Synchro and Output Configuration */ +-#define PSOC0 _SFR_MEM8(0xD0) +-#define POEN0A 0 /* PSC 0 OUT Part A Output Enable */ +-#define POEN0B 2 /* PSC 0 OUT Part B Output Enable */ +-#define PSYNC00 4 /* Synchronization Out for ADC Selection bit0 */ +-#define PSYNC01 5 /* Synchronization Out for ADC Selection bit1 */ +- +-/* Output Compare SA Registers */ +-#define OCR0SA _SFR_MEM16(0xD2) +-#define OCR0SAL _SFR_MEM8(0xD2) +-#define OCR0SAH _SFR_MEM8(0xD3) +- +-/* Output Compare RA Registers */ +-#define OCR0RA _SFR_MEM16(0xD4) +-#define OCR0RAL _SFR_MEM8(0xD4) +-#define OCR0RAH _SFR_MEM8(0xD5) +- +-/* Output Compare SB Registers */ +-#define OCR0SB _SFR_MEM16(0xD6) +-#define OCR0SBL _SFR_MEM8(0xD6) +-#define OCR0SBH _SFR_MEM8(0xD7) +- +-/* Output Compare RB Registers */ +-#define OCR0RB _SFR_MEM16(0xD8) +-#define OCR0RBL _SFR_MEM8(0xD8) +-#define OCR0RBH _SFR_MEM8(0xD9) +- +-/* PSC 0 Configuration Register */ +-#define PCNF0 _SFR_MEM8(0xDA) +-#define PCLKSEL0 1 /* PSC 0 Input Clock Select */ +-#define POP0 2 /* PSC 0 Output Polarity */ +-#define PMODE00 3 /* PSC 0 Mode bit0 */ +-#define PMODE01 4 /* PSC 0 Mode bit1 */ +-#define PLOCK0 5 /* PSC 0 Lock */ +-#define PALOCK0 6 /* PSC 0 Autolock */ +-#define PFIFTY0 7 /* PSC 0 Fifty */ +- +-/* PSC 0 Control Register */ +-#define PCTL0 _SFR_MEM8(0xDB) +-#define PRUN0 0 /* PSC 0 Run */ +-#define PCCYC0 1 /* PSC 0 Complete Cycle */ +-#define PARUN0 2 /* PSC 0 Autorun */ +-#define PAOC0A 3 /* PSC 0 Asynchronous Output Control A */ +-#define PAOC0B 4 /* PSC 0 Asynchronous Output Control B */ +-#define PBFM0 5 /* Balance Flank Width Modulation */ +-#define PPRE00 6 /* PSC 0 Prescaler Select bit0 */ +-#define PPRE01 7 /* PSC 0 Prescaler Select bit1 */ +- +-/* PSC 0 Input A Control Register */ +-#define PFRC0A _SFR_MEM8(0xDC) +-#define PRFM0A0 0 /* PSC 0 Fault Mode bit0 */ +-#define PRFM0A1 1 /* PSC 0 Fault Mode bit1 */ +-#define PRFM0A2 2 /* PSC 0 Fault Mode bit2 */ +-#define PRFM0A3 3 /* PSC 0 Fault Mode bit3 */ +-#define PFLTE0A 4 /* PSC 0 Filter Enable on Input Part A */ +-#define PELEV0A 5 /* PSC 0 Edge Level Selector of Input Part A */ +-#define PISEL0A 6 /* PSC 0 Input Select for Part A */ +-#define PCAE0A 7 /* PSC 0 Capture Enable Input Part A */ +- +-/* PSC 0 Input B Control Register */ +-#define PFRC0B _SFR_MEM8(0xDD) +-#define PRFM0B0 0 /* PSC 0 Fault Mode bit0 */ +-#define PRFM0B1 1 /* PSC 0 Fault Mode bit1 */ +-#define PRFM0B2 2 /* PSC 0 Fault Mode bit2 */ +-#define PRFM0B3 3 /* PSC 0 Fault Mode bit3 */ +-#define PFLTE0B 4 /* PSC 0 Filter Enable on Input Part B */ +-#define PELEV0B 5 /* PSC 0 Edge Level Selector of Input Part B */ +-#define PISEL0B 6 /* PSC 0 Input Select for Part B */ +-#define PCAE0B 7 /* PSC 0 Capture Enable Input Part B */ +- +-/* PSC 0 Input Capture Registers */ +-#define PICR0 _SFR_MEM16(0xDE) +-#define PICR0L _SFR_MEM8(0xDE) +-#define PICR0H _SFR_MEM8(0xDF) +-#define PCST0 7 /* PSC Capture Software Trig bit */ +- +-/* PSC 1 Synchro and Output Configuration */ +-#define PSOC1 _SFR_MEM8(0xE0) +- +-/* Output Compare SA Registers */ +-#define OCR1SA _SFR_MEM16(0xE2) +-#define OCR1SAL _SFR_MEM8(0xE2) +-#define OCR1SAH _SFR_MEM8(0xE3) +- +-/* Output Compare RA Registers */ +-#define OCR1RA _SFR_MEM16(0xE4) +-#define OCR1RAL _SFR_MEM8(0xE4) +-#define OCR1RAH _SFR_MEM8(0xE5) +- +-/* Output Compare SB Registers */ +-#define OCR1SB _SFR_MEM16(0xE6) +-#define OCR1SBL _SFR_MEM8(0xE6) +-#define OCR1SBH _SFR_MEM8(0xE7) +- +-/* Output Compare RB Registers */ +-#define OCR1RB _SFR_MEM16(0xE8) +-#define OCR1RBL _SFR_MEM8(0xE8) +-#define OCR1RBH _SFR_MEM8(0xE9) +- +-/* PSC 1 Configuration Register */ +-#define PCNF1 _SFR_MEM8(0xEA) +- +-/* PSC 1 Control Register */ +-#define PCTL1 _SFR_MEM8(0xEB) +- +-/* PSC 1 Input A Control Register */ +-#define PFRC1A _SFR_MEM8(0xEC) +- +-/* PSC 1 Input B Control Register */ +-#define PFRC1B _SFR_MEM8(0xED) +- +-/* PSC 1 Input Capture Registers */ +-#define PICR1 _SFR_MEM16(0xEE) +-#define PICR1L _SFR_MEM8(0xEE) +-#define PICR1H _SFR_MEM8(0xEF) +- +-/* PSC 2 Synchro and Output Configuration */ +-#define PSOC2 _SFR_MEM8(0xF0) +-#define POEN2A 0 /* PSC 2 OUT Part A Output Enable */ +-#define POEN2C 1 /* PSCOUT22 Output Enable */ +-#define POEN2B 2 /* PSC 2 OUT Part B Output Enable */ +-#define POEN2D 3 /* PSCOUT23 Output Enable */ +-#define PSYNC20 4 /* Synchronization Out for ADC Selection bit0 */ +-#define PSYNC21 5 /* Synchronization Out for ADC Selection bit1 */ +-#define POS22 6 /* PSCOUT22 Selection */ +-#define POS23 7 /* PSCOUT23 Selection */ +- +-/* PSC 2 Output Matrix */ +-#define POM2 _SFR_MEM8(0xF1) +-#define POMV2A0 0 /* Output Matrix Output A Ramp 0 */ +-#define POMV2A1 1 /* Output Matrix Output A Ramp 1 */ +-#define POMV2A2 2 /* Output Matrix Output A Ramp 2 */ +-#define POMV2A3 3 /* Output Matrix Output A Ramp 3 */ +-#define POMV2B0 4 /* Output Matrix Output B Ramp 0 */ +-#define POMV2B1 5 /* Output Matrix Output B Ramp 1 */ +-#define POMV2B2 6 /* Output Matrix Output B Ramp 2 */ +-#define POMV2B3 7 /* Output Matrix Output B Ramp 3 */ +- +-/* Output Compare SA Registers */ +-#define OCR2SA _SFR_MEM16(0xF2) +-#define OCR2SAL _SFR_MEM8(0xF2) +-#define OCR2SAH _SFR_MEM8(0xF3) +- +-/* Output Compare RA Registers */ +-#define OCR2RA _SFR_MEM16(0xF4) +-#define OCR2RAL _SFR_MEM8(0xF4) +-#define OCR2RAH _SFR_MEM8(0xF5) +- +-/* Output Compare SB Registers */ +-#define OCR2SB _SFR_MEM16(0xF6) +-#define OCR2SBL _SFR_MEM8(0xF6) +-#define OCR2SBH _SFR_MEM8(0xF7) +- +-/* Output Compare RB Registers */ +-#define OCR2RB _SFR_MEM16(0xF8) +-#define OCR2RBL _SFR_MEM8(0xF8) +-#define OCR2RBH _SFR_MEM8(0xF9) +- +-/* PSC 2 Configuration Register */ +-#define PCNF2 _SFR_MEM8(0xFA) +-#define POME2 0 /* PSC 2 Output Matrix Enable */ +-#define PCLKSEL2 1 /* PSC 2 Input Clock Select */ +-#define POP2 2 /* PSC 2 Output Polarity */ +-#define PMODE20 3 /* PSC 2 Mode bit0 */ +-#define PMODE21 4 /* PSC 2 Mode bit1 */ +-#define PLOCK2 5 /* PSC 2 Lock */ +-#define PALOCK2 6 /* PSC 2 Autolock */ +-#define PFIFTY2 7 /* PSC 2 Fifty */ +- +-/* PSC 2 Control Register */ +-#define PCTL2 _SFR_MEM8(0xFB) +-#define PRUN2 0 /* PSC 2 Run */ +-#define PCCYC2 1 /* PSC 2 Complete Cycle */ +-#define PARUN2 2 /* PSC 2 Autorun */ +-#define PAOC2A 3 /* PSC 2 Asynchronous Output Control A */ +-#define PAOC2B 4 /* PSC 2 Asynchronous Output Control B */ +-#define PBFM2 5 /* Balance Flank Width Modulation */ +-#define PPRE20 6 /* PSC 2 Prescaler Select bit0 */ +-#define PPRE21 7 /* PSC 2 Prescaler Select bit1 */ +- +-/* PSC 2 Input A Control Register */ +-#define PFRC2A _SFR_MEM8(0xFC) +-#define PRFM2A0 0 /* PSC 2 Fault Mode bit0 */ +-#define PRFM2A1 1 /* PSC 2 Fault Mode bit1 */ +-#define PRFM2A2 2 /* PSC 2 Fault Mode bit2 */ +-#define PRFM2A3 3 /* PSC 2 Fault Mode bit3 */ +-#define PFLTE2A 4 /* PSC 2 Filter Enable on Input Part A */ +-#define PELEV2A 5 /* PSC 2 Edge Level Selector of Input Part A */ +-#define PISEL2A 6 /* PSC 2 Input Select for Part A */ +-#define PCAE2A 7 /* PSC 2 Capture Enable Input Part A */ +- +-/* PSC 2 Input B Control Register */ +-#define PFRC2B _SFR_MEM8(0xFD) +-#define PRFM2B0 0 /* PSC 2 Fault Mode bit0 */ +-#define PRFM2B1 1 /* PSC 2 Fault Mode bit1 */ +-#define PRFM2B2 2 /* PSC 2 Fault Mode bit2 */ +-#define PRFM2B3 3 /* PSC 2 Fault Mode bit3 */ +-#define PFLTE2B 4 /* PSC 2 Filter Enable on Input Part B */ +-#define PELEV2B 5 /* PSC 2 Edge Level Selector of Input Part B */ +-#define PISEL2B 6 /* PSC 2 Input Select for Part B */ +-#define PCAE2B 7 /* PSC 2 Capture Enable Input Part B */ +- +-/* PSC 2 Input Capture Registers */ +-#define PICR2 _SFR_MEM16(0xFE) +-#define PICR2L _SFR_MEM8(0xFE) +-#define PICR2H _SFR_MEM8(0xFF) +-#define PCST2 7 /* PSC Capture Software Trig bit */ +- +- +-/* Interrupt Vectors */ +-/* Interrupt 0 is the reset vector. */ +- +-/* PSC2 Capture Event */ +-#define PSC2_CAPT_vect_num 1 +-#define PSC2_CAPT_vect _VECTOR(1) +- +-/* PSC2 End Cycle */ +-#define PSC2_EC_vect_num 2 +-#define PSC2_EC_vect _VECTOR(2) +- +-/* PSC1 Capture Event */ +-#define PSC1_CAPT_vect_num 3 +-#define PSC1_CAPT_vect _VECTOR(3) +- +-/* PSC1 End Cycle */ +-#define PSC1_EC_vect_num 4 +-#define PSC1_EC_vect _VECTOR(4) +- +-/* PSC0 Capture Event */ +-#define PSC0_CAPT_vect_num 5 +-#define PSC0_CAPT_vect _VECTOR(5) +- +-/* PSC0 End Cycle */ +-#define PSC0_EC_vect_num 6 +-#define PSC0_EC_vect _VECTOR(6) +- +-/* Analog Comparator 0 */ +-#define ANALOG_COMP_0_vect_num 7 +-#define ANALOG_COMP_0_vect _VECTOR(7) +- +-/* Analog Comparator 1 */ +-#define ANALOG_COMP_1_vect_num 8 +-#define ANALOG_COMP_1_vect _VECTOR(8) +- +-/* Analog Comparator 2 */ +-#define ANALOG_COMP_2_vect_num 9 +-#define ANALOG_COMP_2_vect _VECTOR(9) +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 10 +-#define INT0_vect _VECTOR(10) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 11 +-#define TIMER1_CAPT_vect _VECTOR(11) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 12 +-#define TIMER1_COMPA_vect _VECTOR(12) +- +-/* Timer/Counter Compare Match B */ +-#define TIMER1_COMPB_vect_num 13 +-#define TIMER1_COMPB_vect _VECTOR(13) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 15 +-#define TIMER1_OVF_vect _VECTOR(15) +- +-/* Timer/Counter0 Compare Match A */ +-#define TIMER0_COMP_A_vect_num 16 +-#define TIMER0_COMP_A_vect _VECTOR(16) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 17 +-#define TIMER0_OVF_vect _VECTOR(17) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 18 +-#define ADC_vect _VECTOR(18) +- +-/* External Interrupt Request 1 */ +-#define INT1_vect_num 19 +-#define INT1_vect _VECTOR(19) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 20 +-#define SPI_STC_vect _VECTOR(20) +- +-/* USART, Rx Complete */ +-#define USART_RX_vect_num 21 +-#define USART_RX_vect _VECTOR(21) +- +-/* USART Data Register Empty */ +-#define USART_UDRE_vect_num 22 +-#define USART_UDRE_vect _VECTOR(22) +- +-/* USART, Tx Complete */ +-#define USART_TX_vect_num 23 +-#define USART_TX_vect _VECTOR(23) +- +-/* External Interrupt Request 2 */ +-#define INT2_vect_num 24 +-#define INT2_vect _VECTOR(24) +- +-/* Watchdog Timeout Interrupt */ +-#define WDT_vect_num 25 +-#define WDT_vect _VECTOR(25) +- +-/* EEPROM Ready */ +-#define EE_READY_vect_num 26 +-#define EE_READY_vect _VECTOR(26) +- +-/* Timer Counter 0 Compare Match B */ +-#define TIMER0_COMPB_vect_num 27 +-#define TIMER0_COMPB_vect _VECTOR(27) +- +-/* External Interrupt Request 3 */ +-#define INT3_vect_num 28 +-#define INT3_vect _VECTOR(28) +- +-/* Store Program Memory Read */ +-#define SPM_READY_vect_num 31 +-#define SPM_READY_vect _VECTOR(31) +- +-#define _VECTORS_SIZE (4 * 32) +- +-/* Constants */ +- +-#define RAMEND 0x4FF +-#define XRAMSIZE 0 +-#define XRAMEND RAMEND +-#define E2END 0x1FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x3FFF +-#define SPM_PAGESIZE 128 +- +- +-/* Fuse Information */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Diasble */ +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_PSCRV (unsigned char)~_BV(4) +-#define FUSE_PSC0RB (unsigned char)~_BV(5) +-#define FUSE_PSC1RB (unsigned char)~_BV(6) +-#define FUSE_PSC2RB (unsigned char)~_BV(7) +-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x94 +-#define SIGNATURE_2 0x83 +- +- +-#endif /* _AVR_IO90PWM216_H_ */ ++/* Copyright (c) 2007, Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: io90pwm216.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* avr/io90pwm216.h - definitions for AT90PWM216 */ ++ ++#ifndef _AVR_IO90PWM216_H_ ++#define _AVR_IO90PWM216_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "io90pwm216.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* Port B Input Pins Address */ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++/* Port B Data Direction Register */ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++/* Port B Data Register */ ++#define PORTB _SFR_IO8(0x05) ++#define PB0 0 ++#define PB1 1 ++#define PB2 2 ++#define PB3 3 ++#define PB4 4 ++#define PB5 5 ++#define PB6 6 ++#define PB7 7 ++ ++/* Port C Input Pins Address */ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++#define PINC7 7 ++ ++/* Port C Data Direction Register */ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++#define DDC7 7 ++ ++/* Port C Data Register */ ++#define PORTC _SFR_IO8(0x08) ++#define PC0 0 ++#define PC1 1 ++#define PC2 2 ++#define PC3 3 ++#define PC4 4 ++#define PC5 5 ++#define PC6 6 ++#define PC7 7 ++ ++/* Port D Input Pins Address */ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++/* Port D Data Direction Register */ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++/* Port D Data Register */ ++#define PORTD _SFR_IO8(0x0B) ++#define PD0 0 ++#define PD1 1 ++#define PD2 2 ++#define PD3 3 ++#define PD4 4 ++#define PD5 5 ++#define PD6 6 ++#define PD7 7 ++ ++/* Port E Input Pins Address */ ++#define PINE _SFR_IO8(0x0C) ++#define PINE0 0 ++#define PINE1 1 ++#define PINE2 2 ++ ++/* Port E Data Direction Register */ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE0 0 ++#define DDE1 1 ++#define DDE2 2 ++ ++/* Port E Data Register */ ++#define PORTE _SFR_IO8(0x0E) ++#define PE0 0 ++#define PE1 1 ++#define PE2 2 ++ ++/* Timer/Counter 0 Interrupt Flag Register */ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 /* Overflow Flag */ ++#define OCF0A 1 /* Output Compare Flag 0A */ ++#define OCF0B 2 /* Output Compare Flag 0B */ ++ ++/* Timer/Counter1 Interrupt Flag Register */ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 /* Overflow Flag */ ++#define OCF1A 1 /* Output Compare Flag 1A*/ ++#define OCF1B 2 /* Output Compare Flag 1B*/ ++#define ICF1 5 /* Input Capture Flag 1 */ ++ ++/* General Purpose I/O Register 1 */ ++#define GPIOR1 _SFR_IO8(0x19) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++/* General Purpose I/O Register 2 */ ++#define GPIOR2 _SFR_IO8(0x1A) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++/* General Purpose I/O Register 3 */ ++#define GPIOR3 _SFR_IO8(0x1B) ++#define GPIOR30 0 ++#define GPIOR31 1 ++#define GPIOR32 2 ++#define GPIOR33 3 ++#define GPIOR34 4 ++#define GPIOR35 5 ++#define GPIOR36 6 ++#define GPIOR37 7 ++ ++/* External Interrupt Flag Register */ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++ ++/* External Interrupt Mask Register */ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 /* External Interrupt Request 0 Enable */ ++#define INT1 1 /* External Interrupt Request 1 Enable */ ++#define INT2 2 /* External Interrupt Request 2 Enable */ ++#define INT3 3 /* External Interrupt Request 3 Enable */ ++ ++/* General Purpose I/O Register 0 */ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 /* EEPROM Read Enable */ ++#define EEWE 1 /* EEPROM Write Enable */ ++#define EEMWE 2 /* EEPROM Master Write Enable */ ++#define EERIE 3 /* EEPROM Ready Interrupt Enable */ ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++/* The EEPROM Address Registers */ ++#define EEAR _SFR_IO16(0x21) ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++#define EEAR9 1 ++#define EEAR10 2 ++#define EEAR11 3 ++ ++/* 6-char sequence denoting where to find the EEPROM registers in memory space. ++ Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM ++ subroutines. ++ First two letters: EECR address. ++ Second two letters: EEDR address. ++ Last two letters: EEAR address. */ ++#define __EEPROM_REG_LOCATIONS__ 1F2021 ++ ++/* General Timer/Counter Control Register */ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR10 0 /* Prescaler Reset Timer/Counter1 and Timer/Counter0 */ ++#define ICPSEL1 6 /* Timer1 Input Capture Selection Bit */ ++#define TSM 7 /* Timer/Counter Synchronization Mode */ ++ ++/* Timer/Counter Control Register A */ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 /* Waveform Generation Mode */ ++#define WGM01 1 /* Waveform Generation Mode */ ++#define COM0B0 4 /* Compare Output Mode, Fast PWm */ ++#define COM0B1 5 /* Compare Output Mode, Fast PWm */ ++#define COM0A0 6 /* Compare Output Mode, Phase Correct PWM Mode */ ++#define COM0A1 7 /* Compare Output Mode, Phase Correct PWM Mode */ ++ ++/* Timer/Counter Control Register B */ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 /* Clock Select */ ++#define CS01 1 /* Clock Select */ ++#define CS02 2 /* Clock Select */ ++#define WGM02 3 /* Waveform Generation Mode */ ++#define FOC0B 6 /* Force Output Compare B */ ++#define FOC0A 7 /* Force Output Compare A */ ++ ++/* Timer/Counter0 Register */ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT00 0 ++#define TCNT01 1 ++#define TCNT02 2 ++#define TCNT03 3 ++#define TCNT04 4 ++#define TCNT05 5 ++#define TCNT06 6 ++#define TCNT07 7 ++ ++/* Timer/Counter0 Output Compare Register A */ ++#define OCR0A _SFR_IO8(0x27) ++#define OCR0A0 0 ++#define OCR0A1 1 ++#define OCR0A2 2 ++#define OCR0A3 3 ++#define OCR0A4 4 ++#define OCR0A5 5 ++#define OCR0A6 6 ++#define OCR0A7 7 ++ ++/* Timer/Counter0 Output Compare Register B */ ++#define OCR0B _SFR_IO8(0x28) ++#define OCR0B0 0 ++#define OCR0B1 1 ++#define OCR0B2 2 ++#define OCR0B3 3 ++#define OCR0B4 4 ++#define OCR0B5 5 ++#define OCR0B6 6 ++#define OCR0B7 7 ++ ++/* PLL Control and Status Register */ ++#define PLLCSR _SFR_IO8(0x29) ++#define PLOCK 0 /* PLL Lock Detector */ ++#define PLLE 1 /* PLL Enable */ ++#define PLLF 2 /* PLL Factor */ ++ ++/* SPI Control Register */ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 /* SPI Clock Rate Select 0 */ ++#define SPR1 1 /* SPI Clock Rate Select 1 */ ++#define CPHA 2 /* Clock Phase */ ++#define CPOL 3 /* Clock polarity */ ++#define MSTR 4 /* Master/Slave Select */ ++#define DORD 5 /* Data Order */ ++#define SPE 6 /* SPI Enable */ ++#define SPIE 7 /* SPI Interrupt Enable */ ++ ++/* SPI Status Register */ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 /* Double SPI Speed Bit */ ++#define WCOL 6 /* Write Collision Flag */ ++#define SPIF 7 /* SPI Interrupt Flag */ ++ ++/* SPI Data Register */ ++#define SPDR _SFR_IO8(0x2E) ++#define SPD0 0 ++#define SPD1 1 ++#define SPD2 2 ++#define SPD3 3 ++#define SPD4 4 ++#define SPD5 5 ++#define SPD6 6 ++#define SPD7 7 ++ ++/* Analog Comparator Status Register */ ++#define ACSR _SFR_IO8(0x30) ++#define AC0O 0 /* Analog Comparator 0 Output Bit */ ++#define AC1O 1 /* Analog Comparator 1 Output Bit */ ++#define AC2O 2 /* Analog Comparator 2 Output Bit */ ++#define AC0IF 4 /* Analog Comparator 0 Interrupt Flag Bit */ ++#define AC1IF 5 /* Analog Comparator 1 Interrupt Flag Bit */ ++#define AC2IF 6 /* Analog Comparator 2 Interrupt Flag Bit */ ++#define ACCKDIV 7 /* Analog Comparator Clock Divider */ ++ ++/* Sleep Mode Control Register */ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 /* Sleep Enable */ ++#define SM0 1 /* Sleep Mode Select bit0 */ ++#define SM1 2 /* Sleep Mode Select bit1 */ ++#define SM2 3 /* Sleep Mode Select bit2 */ ++ ++/* MCU Status Register */ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 /* Power-on reset flag */ ++#define EXTRF 1 /* External Reset Flag */ ++#define BORF 2 /* Brown-out Reset Flag */ ++#define WDRF 3 /* Watchdog Reset Flag */ ++ ++/* MCU Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 /* Interrupt Vector Change Enable */ ++#define IVSEL 1 /* Interrupt Vector Select */ ++#define PUD 4 /* Pull-up disable */ ++#define SPIPS 7 /* SPI Pin Select */ ++ ++/* Store Program Memory Control Register */ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 /* Store Program Memory Enable */ ++#define PGERS 1 /* Page Erase */ ++#define PGWRT 2 /* Page Write */ ++#define BLBSET 3 /* Boot Lock Bit Set */ ++#define RWWSRE 4 /* Read While Write section read enable */ ++#define RWWSB 6 /* Read While Write Section Busy */ ++#define SPMIE 7 /* SPM Interrupt Enable */ ++ ++/* Watchdog Timer Control Register */ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 /* Watchdog Timer Prescaler bit0 */ ++#define WDP1 1 /* Watchdog Timer Prescaler bit1 */ ++#define WDP2 2 /* Watchdog Timer Prescaler bit2 */ ++#define WDE 3 /* Watchdog Enable */ ++#define WDCE 4 /* Watchdog Change Enable */ ++#define WDP3 5 /* Watchdog Timer Prescaler bit3 */ ++#define WDIE 6 /* Watchdog Timeout Interrupt Enable */ ++#define WDIF 7 /* Watchdog Timeout Interrupt Flag */ ++ ++/* Clock Prescaler Register */ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 /* Clock Prescaler Select bit0 */ ++#define CLKPS1 1 /* Clock Prescaler Select bit1 */ ++#define CLKPS2 2 /* Clock Prescaler Select bit2 */ ++#define CLKPS3 3 /* Clock Prescaler Select bit3 */ ++#define CLKPCE 7 /* Clock Prescaler Change Enable */ ++ ++/* Power Reduction Register */ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 /* Power Reduction ADC */ ++#define PRUSART0 1 /* Power Reduction USART0 */ ++#define PRSPI 2 /* Power Reduction Serial Peripheral Interface */ ++#define PRTIM0 3 /* Power Reduction Timer/Counter0 */ ++#define PRTIM1 4 /* Power Reduction Timer/Counter1 */ ++#define PRPSC0 5 /* Power Reduction PSC0 */ ++#define PRPSC1 6 /* Power Reduction PSC1 */ ++#define PRPSC2 7 /* Power Reduction PSC2 */ ++ ++/* Oscillator Calibration Value */ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++ ++/* External Interrupt Control Register A */ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++/* Timer/Counter0 Interrupt Mask Register */ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 /* Overflow Interrupt Enable */ ++#define OCIE0A 1 /* Output Compare Match A Interrupt Enable */ ++#define OCIE0B 2 /* Output Compare Match B Interrupt Enable */ ++ ++/* Timer/Counter1 Interrupt Mask Register */ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 /* Overflow Interrupt Enable */ ++#define OCIE1A 1 /* Output Compare Match A Interrupt Enable */ ++#define OCIE1B 2 /* Output Compare Match B Interrupt Enable */ ++#define ICIE1 5 /* Input Capture Interrupt Enable */ ++ ++/* Amplifier 0 Control and Status register */ ++#define AMP0CSR _SFR_MEM8(0x76) ++#define AMP0TS0 0 ++#define AMP0TS1 1 ++#define AMP0G0 4 ++#define AMP0G1 5 ++#define AMP0IS 6 ++#define AMP0EN 7 ++ ++/* Amplifier 1 Control and Status register */ ++#define AMP1CSR _SFR_MEM8(0x77) ++#define AMP1TS0 0 ++#define AMP1TS1 1 ++#define AMP1G0 4 ++#define AMP1G1 5 ++#define AMP1IS 6 ++#define AMP1EN 7 ++ ++/* ADC Result Data Register */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++/* ADC Control and Status Register A */ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 /* ADC Prescaler Select bit0 */ ++#define ADPS1 1 /* ADC Prescaler Select bit1 */ ++#define ADPS2 2 /* ADC Prescaler Select bit2 */ ++#define ADIE 3 /* ADC Interrupt Enable */ ++#define ADIF 4 /* ADC Interrupt Flag */ ++#define ADATE 5 /* ADC Auto Trigger Enable */ ++#define ADSC 6 /* ADC Start Conversion */ ++#define ADEN 7 /* ADC Enable */ ++ ++/* ADC Control and Status Register B */ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 /* ADC Auto Trigger Source 0 */ ++#define ADTS1 1 /* ADC Auto Trigger Source 1 */ ++#define ADTS2 2 /* ADC Auto Trigger Source 2 */ ++#define ADTS3 3 /* ADC Auto Trigger Source 3 */ ++#define ADHSM 7 /* ADC High Speed Mode */ ++ ++/* ADC multiplexer Selection Register */ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 /* Analog Channel and Gain Selection bit0 */ ++#define MUX1 1 /* Analog Channel and Gain Selection bit1 */ ++#define MUX2 2 /* Analog Channel and Gain Selection bit2 */ ++#define MUX3 3 /* Analog Channel and Gain Selection bit3 */ ++#define ADLAR 5 /* Left Adjust Result */ ++#define REFS0 6 /* Reference Selection bit0 */ ++#define REFS1 7 /* Reference Selection bit1 */ ++ ++/* Digital Input Disable Register 0 */ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 /* ADC0 Digital input Disable */ ++#define ADC1D 1 /* ADC1 Digital input Disable */ ++#define ADC2D 2 /* ADC2 Digital input Disable */ ++#define ADC3D 3 /* ADC3 Digital input Disable */ ++#define ADC4D 4 /* ADC4 Digital input Disable */ ++#define ADC5D 5 /* ADC5 Digital input Disable */ ++#define ADC6D 6 /* ADC6 Digital input Disable */ ++#define ADC7D 7 /* ADC7 Digital input Disable */ ++ ++/* Digital Input Disable Register 1 */ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define ADC8D 0 /* ADC8 Digital input Disable */ ++#define ADC9D 1 /* ADC9 Digital input Disable */ ++#define ADC10D 2 /* ADC10 Digital input Disable */ ++#define AMP0ND 3 ++#define AMP0PD 4 ++#define ACMP0D 5 ++ ++/* Timer/Counter1 Control Register A */ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 /* Waveform Generation Mode */ ++#define WGM11 1 /* Waveform Generation Mode */ ++#define COM1B0 4 /* Compare Output Mode 1B, bit 0 */ ++#define COM1B1 5 /* Compare Output Mode 1B, bit 1 */ ++#define COM1A0 6 /* Comparet Ouput Mode 1A, bit 0 */ ++#define COM1A1 7 /* Comparet Ouput Mode 1A, bit 1 */ ++ ++/* Timer/Counter1 Control Register B */ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 /* Prescaler source of Timer/Counter 1 */ ++#define CS11 1 /* Prescaler source of Timer/Counter 1 */ ++#define CS12 2 /* Prescaler source of Timer/Counter 1 */ ++#define WGM12 3 /* Waveform Generation Mode */ ++#define WGM13 4 /* Waveform Generation Mode */ ++#define ICES1 6 /* Input Capture 1 Edge Select */ ++#define ICNC1 7 /* Input Capture 1 Noise Canceler */ ++ ++/* Timer/Counter1 Control Register C */ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 /* Force Output Compare for Channel B */ ++#define FOC1A 7 /* Force Output Compare for Channel A */ ++ ++/* Timer/Counter1 */ ++#define TCNT1 _SFR_MEM16(0x84) ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT10 0 ++#define TCNT11 1 ++#define TCNT12 2 ++#define TCNT13 3 ++#define TCNT14 4 ++#define TCNT15 5 ++#define TCNT16 6 ++#define TCNT17 7 ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT18 0 ++#define TCNT19 1 ++#define TCNT110 2 ++#define TCNT111 3 ++#define TCNT112 4 ++#define TCNT113 5 ++#define TCNT114 6 ++#define TCNT115 7 ++ ++/* Input Capture Register 1 */ ++#define ICR1 _SFR_MEM16(0x86) ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR17 7 ++#define ICR16 6 ++#define ICR15 5 ++#define ICR14 4 ++#define ICR13 3 ++#define ICR12 2 ++#define ICR11 1 ++#define ICR10 0 ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR115 7 ++#define ICR114 6 ++#define ICR113 5 ++#define ICR112 4 ++#define ICR111 3 ++#define ICR110 2 ++#define ICR19 1 ++#define ICR18 0 ++ ++/* Output Compare Register 1 A */ ++#define OCR1A _SFR_MEM16(0x88) ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1A0 0 ++#define OCR1A1 1 ++#define OCR1A2 2 ++#define OCR1A3 3 ++#define OCR1A4 4 ++#define OCR1A5 5 ++#define OCR1A6 6 ++#define OCR1A7 7 ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1A8 0 ++#define OCR1A9 1 ++#define OCR1A10 2 ++#define OCR1A11 3 ++#define OCR1A12 4 ++#define OCR1A13 5 ++#define OCR1A14 6 ++#define OCR1A15 7 ++ ++/* Output Compare Register 1 B */ ++#define OCR1B _SFR_MEM16(0x8A) ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1B0 0 ++#define OCR1B1 1 ++#define OCR1B2 2 ++#define OCR1B3 3 ++#define OCR1B4 4 ++#define OCR1B5 5 ++#define OCR1B6 6 ++#define OCR1B7 7 ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1B8 0 ++#define OCR1B9 1 ++#define OCR1B10 2 ++#define OCR1B11 3 ++#define OCR1B12 4 ++#define OCR1B13 5 ++#define OCR1B14 6 ++#define OCR1B15 7 ++ ++/* PSC0 Interrupt Flag Register */ ++#define PIFR0 _SFR_MEM8(0xA0) ++#define PEOP0 0 /* End Of PSC0 Interrupt */ ++#define PRN00 1 /* PSC0 Ramp Number bit0 */ ++#define PRN01 2 /* PSC0 Ramp Number bit1 */ ++#define PEV0A 3 /* PSC0 External Event A Interrupt */ ++#define PEV0B 4 /* PSC0 External Event B Interrupt */ ++#define PSEI0 5 /* PSC0 Synchro Error Interrupt */ ++#define POAC0A 6 /* PSC0 Output A Activity */ ++#define POAC0B 7 /* PSC0 Output B Activity */ ++ ++/* PSC0 Interrupt Mask Register */ ++#define PIM0 _SFR_MEM8(0xA1) ++#define PEOPE0 0 /* PSC0 End Of Cycle Interrupt Enable */ ++#define PEVE0A 3 /* PSC0 External Event A Interrupt Enable */ ++#define PEVE0B 4 /* PSC0 External Event B Interrupt Enable */ ++#define PSEIE0 5 /* PSC0 Synchro Error Interrupt Enable */ ++ ++/* PSC1 Interrupt Flag Register */ ++#define PIFR1 _SFR_MEM8(0xA2) ++ ++/* PSC1 Interrupt Mask Register */ ++#define PIM1 _SFR_MEM8(0xA3) ++ ++/* PSC2 Interrupt Flag Register */ ++#define PIFR2 _SFR_MEM8(0xA4) ++#define PEOP2 0 /* End Of PSC2 Interrupt */ ++#define PRN20 1 /* PSC2 Ramp Number bit0 */ ++#define PRN21 2 /* PSC2 Ramp Number bit1 */ ++#define PEV2A 3 /* PSC2 External Event A Interrupt */ ++#define PEV2B 4 /* PSC2 External Event B Interrupt */ ++#define PSEI2 5 /* PSC2 Synchro Error Interrupt */ ++#define POAC2A 6 /* PSC2 Output A Activity */ ++#define POAC2B 7 /* PSC2 Output B Activity */ ++ ++/* PSC2 Interrupt Mask Register */ ++#define PIM2 _SFR_MEM8(0xA5) ++#define PEOPE2 0 /* PSC2 End Of Cycle Interrupt Enable */ ++#define PEVE2A 3 /* PSC2 External Event A Interrupt Enable */ ++#define PEVE2B 4 /* PSC2 External Event B Interrupt Enable */ ++#define PSEIE2 5 /* PSC2 Synchro Error Interrupt Enable */ ++ ++/* Digital to Analog Conversion Control Register */ ++#define DACON _SFR_MEM8(0xAA) ++#define DAEN 0 /* Digital to Analog Enable bit */ ++#define DAOE 1 /* Digital to Analog Output Enable bit */ ++#define DALA 2 /* Digital to Analog Left Adjust */ ++#define DATS0 4 /* DAC Trigger Selection bit0 */ ++#define DATS1 5 /* DAC Trigger Selection bit1 */ ++#define DATS2 6 /* DAC Trigger Selection bit2 */ ++#define DAATE 7 /* DAC Auto Trigger Enable bit */ ++ ++/* Digital to Analog Converter input Register */ ++#define DAC _SFR_MEM16(0xAB) ++#define DACL _SFR_MEM8(0xAB) ++#define DACH _SFR_MEM8(0xAC) ++ ++/* Analog Comparator 0 Control Register */ ++#define AC0CON _SFR_MEM8(0xAD) ++#define AC0M0 0 /* Analog Comparator 0 Multiplexer register bit0 */ ++#define AC0M1 1 /* Analog Comparator 0 Multiplexer register bit1 */ ++#define AC0M2 2 /* Analog Comparator 0 Multiplexer register bit2 */ ++#define AC0IS0 4 /* Analog Comparator 0 Interrupt Select bit0 */ ++#define AC0IS1 5 /* Analog Comparator 0 Interrupt Select bit1 */ ++#define AC0IE 6 /* Analog Comparator 0 Interrupt Enable bit */ ++#define AC0EN 7 /* Analog Comparator 0 Enable Bit */ ++ ++/* Analog Comparator 1 Control Register */ ++#define AC1CON _SFR_MEM8(0xAE) ++#define AC1M0 0 /* Analog Comparator 1 Multiplexer register bit0 */ ++#define AC1M1 1 /* Analog Comparator 1 Multiplexer register bit1 */ ++#define AC1M2 2 /* Analog Comparator 1 Multiplexer register bit2 */ ++#define AC1ICE 3 /* Analog Comparator 1 Interrupt Capture Enable bit */ ++#define AC1IS0 4 /* Analog Comparator 1 Interrupt Select bit0 */ ++#define AC1IS1 5 /* Analog Comparator 1 Interrupt Select bit1 */ ++#define AC1IE 6 /* Analog Comparator 1 Interrupt Enable bit */ ++#define AC1EN 7 /* Analog Comparator 1 Enable Bit */ ++ ++/* Analog Comparator 2 Control Register */ ++#define AC2CON _SFR_MEM8(0xAF) ++#define AC2M0 0 /* Analog Comparator 2 Multiplexer register bit0 */ ++#define AC2M1 1 /* Analog Comparator 2 Multiplexer register bit1 */ ++#define AC2M2 2 /* Analog Comparator 2 Multiplexer register bit2 */ ++#define AC2IS0 4 /* Analog Comparator 2 Interrupt Select bit0 */ ++#define AC2IS1 5 /* Analog Comparator 2 Interrupt Select bit1 */ ++#define AC2IE 6 /* Analog Comparator 2 Interrupt Enable bit */ ++#define AC2EN 7 /* Analog Comparator 2 Enable Bit */ ++ ++/* USART Control and Status Register A */ ++#define UCSRA _SFR_MEM8(0xC0) ++#define MPCM 0 /* Multi-processor Communication Mode */ ++#define U2X 1 /* Double the USART Transmission Speed */ ++#define UPE 2 /* USART Parity Error */ ++#define DOR 3 /* Data OverRun */ ++#define FE 4 /* Frame Error */ ++#define UDRE 5 /* USART Data Register Empty */ ++#define TXC 6 /* USART Transmit Complete */ ++#define RXC 7 /* USART Receive Complete */ ++ ++/* USART Control and Status Register B */ ++#define UCSRB _SFR_MEM8(0xC1) ++#define TXB8 0 /* Transmit Data Bit 8 */ ++#define RXB8 1 /* Receive Data Bit 8 */ ++#define UCSZ2 2 /* Character Size */ ++#define TXEN 3 /* Transmitter Enable */ ++#define RXEN 4 /* Receiver Enable */ ++#define UDRIE 5 /* USART Data Register Empty Interrupt Enable */ ++#define TXCIE 6 /* TX Complete Interrupt Enable */ ++#define RXCIE 7 /* RX Complete Interrupt Enable */ ++ ++/* USART Control and Status Register C */ ++#define UCSRC _SFR_MEM8(0xC2) ++#define UCPOL 0 /* Clock Polarity */ ++#define UCSZ0 1 /* Character Size bit0 */ ++#define UCSZ1 2 /* Character Size bit1 */ ++#define USBS 3 /* Stop Bit Select */ ++#define UPM0 4 /* Parity Mode bit0 */ ++#define UPM1 5 /* Parity Mode bit1 */ ++#define UMSEL 6 /* USART Mode Select */ ++ ++/* USART Baud Rate Register */ ++#define UBRR _SFR_MEM16(0xC4) ++#define UBRRL _SFR_MEM8(0xC4) ++#define UBRRH _SFR_MEM8(0xC5) ++ ++/* USART I/O Data Register */ ++#define UDR _SFR_MEM8(0xC6) ++ ++/* EUSART Control and Status Register A */ ++#define EUCSRA _SFR_MEM8(0xC8) ++#define URxS0 0 /* EUSART Receive Character Size bit0 */ ++#define URxS1 1 /* EUSART Receive Character Size bit1 */ ++#define URxS2 2 /* EUSART Receive Character Size bit2 */ ++#define URxS3 3 /* EUSART Receive Character Size bit3 */ ++#define UTxS0 4 /* EUSART Transmit Character Size bit0 */ ++#define UTxS1 5 /* EUSART Transmit Character Size bit1 */ ++#define UTxS2 6 /* EUSART Transmit Character Size bit2 */ ++#define UTxS3 7 /* EUSART Transmit Character Size bit3 */ ++ ++/* EUSART Control and Status Register B */ ++#define EUCSRB _SFR_MEM8(0xC9) ++#define BODR 0 /* Bit Order */ ++#define EMCH 1 /* Manchester mode */ ++#define EUSBS 3 /* EUSBS Enable Bit */ ++#define EUSART 4 /* EUSART Enable Bit */ ++ ++/* EUSART Control and Status Register C */ ++#define EUCSRC _SFR_MEM8(0xCA) ++#define STP0 0 /* Stop bits values bit0 */ ++#define STP1 1 /* Stop bits values bit1 */ ++#define F1617 2 ++#define FEM 3 /* Frame Error Manchester */ ++ ++/* Manchester receiver Baud Rate Registers */ ++#define MUBRR _SFR_MEM16(0xCC) ++#define MUBRRL _SFR_MEM8(0xCC) ++#define MUBRRH _SFR_MEM8(0xCD) ++ ++/* EUSART I/O Data Register */ ++#define EUDR _SFR_MEM8(0xCE) ++ ++/* PSC 0 Synchro and Output Configuration */ ++#define PSOC0 _SFR_MEM8(0xD0) ++#define POEN0A 0 /* PSC 0 OUT Part A Output Enable */ ++#define POEN0B 2 /* PSC 0 OUT Part B Output Enable */ ++#define PSYNC00 4 /* Synchronization Out for ADC Selection bit0 */ ++#define PSYNC01 5 /* Synchronization Out for ADC Selection bit1 */ ++ ++/* Output Compare SA Registers */ ++#define OCR0SA _SFR_MEM16(0xD2) ++#define OCR0SAL _SFR_MEM8(0xD2) ++#define OCR0SAH _SFR_MEM8(0xD3) ++ ++/* Output Compare RA Registers */ ++#define OCR0RA _SFR_MEM16(0xD4) ++#define OCR0RAL _SFR_MEM8(0xD4) ++#define OCR0RAH _SFR_MEM8(0xD5) ++ ++/* Output Compare SB Registers */ ++#define OCR0SB _SFR_MEM16(0xD6) ++#define OCR0SBL _SFR_MEM8(0xD6) ++#define OCR0SBH _SFR_MEM8(0xD7) ++ ++/* Output Compare RB Registers */ ++#define OCR0RB _SFR_MEM16(0xD8) ++#define OCR0RBL _SFR_MEM8(0xD8) ++#define OCR0RBH _SFR_MEM8(0xD9) ++ ++/* PSC 0 Configuration Register */ ++#define PCNF0 _SFR_MEM8(0xDA) ++#define PCLKSEL0 1 /* PSC 0 Input Clock Select */ ++#define POP0 2 /* PSC 0 Output Polarity */ ++#define PMODE00 3 /* PSC 0 Mode bit0 */ ++#define PMODE01 4 /* PSC 0 Mode bit1 */ ++#define PLOCK0 5 /* PSC 0 Lock */ ++#define PALOCK0 6 /* PSC 0 Autolock */ ++#define PFIFTY0 7 /* PSC 0 Fifty */ ++ ++/* PSC 0 Control Register */ ++#define PCTL0 _SFR_MEM8(0xDB) ++#define PRUN0 0 /* PSC 0 Run */ ++#define PCCYC0 1 /* PSC 0 Complete Cycle */ ++#define PARUN0 2 /* PSC 0 Autorun */ ++#define PAOC0A 3 /* PSC 0 Asynchronous Output Control A */ ++#define PAOC0B 4 /* PSC 0 Asynchronous Output Control B */ ++#define PBFM0 5 /* Balance Flank Width Modulation */ ++#define PPRE00 6 /* PSC 0 Prescaler Select bit0 */ ++#define PPRE01 7 /* PSC 0 Prescaler Select bit1 */ ++ ++/* PSC 0 Input A Control Register */ ++#define PFRC0A _SFR_MEM8(0xDC) ++#define PRFM0A0 0 /* PSC 0 Fault Mode bit0 */ ++#define PRFM0A1 1 /* PSC 0 Fault Mode bit1 */ ++#define PRFM0A2 2 /* PSC 0 Fault Mode bit2 */ ++#define PRFM0A3 3 /* PSC 0 Fault Mode bit3 */ ++#define PFLTE0A 4 /* PSC 0 Filter Enable on Input Part A */ ++#define PELEV0A 5 /* PSC 0 Edge Level Selector of Input Part A */ ++#define PISEL0A 6 /* PSC 0 Input Select for Part A */ ++#define PCAE0A 7 /* PSC 0 Capture Enable Input Part A */ ++ ++/* PSC 0 Input B Control Register */ ++#define PFRC0B _SFR_MEM8(0xDD) ++#define PRFM0B0 0 /* PSC 0 Fault Mode bit0 */ ++#define PRFM0B1 1 /* PSC 0 Fault Mode bit1 */ ++#define PRFM0B2 2 /* PSC 0 Fault Mode bit2 */ ++#define PRFM0B3 3 /* PSC 0 Fault Mode bit3 */ ++#define PFLTE0B 4 /* PSC 0 Filter Enable on Input Part B */ ++#define PELEV0B 5 /* PSC 0 Edge Level Selector of Input Part B */ ++#define PISEL0B 6 /* PSC 0 Input Select for Part B */ ++#define PCAE0B 7 /* PSC 0 Capture Enable Input Part B */ ++ ++/* PSC 0 Input Capture Registers */ ++#define PICR0 _SFR_MEM16(0xDE) ++#define PICR0L _SFR_MEM8(0xDE) ++#define PICR0H _SFR_MEM8(0xDF) ++#define PCST0 7 /* PSC Capture Software Trig bit */ ++ ++/* PSC 1 Synchro and Output Configuration */ ++#define PSOC1 _SFR_MEM8(0xE0) ++ ++/* Output Compare SA Registers */ ++#define OCR1SA _SFR_MEM16(0xE2) ++#define OCR1SAL _SFR_MEM8(0xE2) ++#define OCR1SAH _SFR_MEM8(0xE3) ++ ++/* Output Compare RA Registers */ ++#define OCR1RA _SFR_MEM16(0xE4) ++#define OCR1RAL _SFR_MEM8(0xE4) ++#define OCR1RAH _SFR_MEM8(0xE5) ++ ++/* Output Compare SB Registers */ ++#define OCR1SB _SFR_MEM16(0xE6) ++#define OCR1SBL _SFR_MEM8(0xE6) ++#define OCR1SBH _SFR_MEM8(0xE7) ++ ++/* Output Compare RB Registers */ ++#define OCR1RB _SFR_MEM16(0xE8) ++#define OCR1RBL _SFR_MEM8(0xE8) ++#define OCR1RBH _SFR_MEM8(0xE9) ++ ++/* PSC 1 Configuration Register */ ++#define PCNF1 _SFR_MEM8(0xEA) ++ ++/* PSC 1 Control Register */ ++#define PCTL1 _SFR_MEM8(0xEB) ++ ++/* PSC 1 Input A Control Register */ ++#define PFRC1A _SFR_MEM8(0xEC) ++ ++/* PSC 1 Input B Control Register */ ++#define PFRC1B _SFR_MEM8(0xED) ++ ++/* PSC 1 Input Capture Registers */ ++#define PICR1 _SFR_MEM16(0xEE) ++#define PICR1L _SFR_MEM8(0xEE) ++#define PICR1H _SFR_MEM8(0xEF) ++ ++/* PSC 2 Synchro and Output Configuration */ ++#define PSOC2 _SFR_MEM8(0xF0) ++#define POEN2A 0 /* PSC 2 OUT Part A Output Enable */ ++#define POEN2C 1 /* PSCOUT22 Output Enable */ ++#define POEN2B 2 /* PSC 2 OUT Part B Output Enable */ ++#define POEN2D 3 /* PSCOUT23 Output Enable */ ++#define PSYNC20 4 /* Synchronization Out for ADC Selection bit0 */ ++#define PSYNC21 5 /* Synchronization Out for ADC Selection bit1 */ ++#define POS22 6 /* PSCOUT22 Selection */ ++#define POS23 7 /* PSCOUT23 Selection */ ++ ++/* PSC 2 Output Matrix */ ++#define POM2 _SFR_MEM8(0xF1) ++#define POMV2A0 0 /* Output Matrix Output A Ramp 0 */ ++#define POMV2A1 1 /* Output Matrix Output A Ramp 1 */ ++#define POMV2A2 2 /* Output Matrix Output A Ramp 2 */ ++#define POMV2A3 3 /* Output Matrix Output A Ramp 3 */ ++#define POMV2B0 4 /* Output Matrix Output B Ramp 0 */ ++#define POMV2B1 5 /* Output Matrix Output B Ramp 1 */ ++#define POMV2B2 6 /* Output Matrix Output B Ramp 2 */ ++#define POMV2B3 7 /* Output Matrix Output B Ramp 3 */ ++ ++/* Output Compare SA Registers */ ++#define OCR2SA _SFR_MEM16(0xF2) ++#define OCR2SAL _SFR_MEM8(0xF2) ++#define OCR2SAH _SFR_MEM8(0xF3) ++ ++/* Output Compare RA Registers */ ++#define OCR2RA _SFR_MEM16(0xF4) ++#define OCR2RAL _SFR_MEM8(0xF4) ++#define OCR2RAH _SFR_MEM8(0xF5) ++ ++/* Output Compare SB Registers */ ++#define OCR2SB _SFR_MEM16(0xF6) ++#define OCR2SBL _SFR_MEM8(0xF6) ++#define OCR2SBH _SFR_MEM8(0xF7) ++ ++/* Output Compare RB Registers */ ++#define OCR2RB _SFR_MEM16(0xF8) ++#define OCR2RBL _SFR_MEM8(0xF8) ++#define OCR2RBH _SFR_MEM8(0xF9) ++ ++/* PSC 2 Configuration Register */ ++#define PCNF2 _SFR_MEM8(0xFA) ++#define POME2 0 /* PSC 2 Output Matrix Enable */ ++#define PCLKSEL2 1 /* PSC 2 Input Clock Select */ ++#define POP2 2 /* PSC 2 Output Polarity */ ++#define PMODE20 3 /* PSC 2 Mode bit0 */ ++#define PMODE21 4 /* PSC 2 Mode bit1 */ ++#define PLOCK2 5 /* PSC 2 Lock */ ++#define PALOCK2 6 /* PSC 2 Autolock */ ++#define PFIFTY2 7 /* PSC 2 Fifty */ ++ ++/* PSC 2 Control Register */ ++#define PCTL2 _SFR_MEM8(0xFB) ++#define PRUN2 0 /* PSC 2 Run */ ++#define PCCYC2 1 /* PSC 2 Complete Cycle */ ++#define PARUN2 2 /* PSC 2 Autorun */ ++#define PAOC2A 3 /* PSC 2 Asynchronous Output Control A */ ++#define PAOC2B 4 /* PSC 2 Asynchronous Output Control B */ ++#define PBFM2 5 /* Balance Flank Width Modulation */ ++#define PPRE20 6 /* PSC 2 Prescaler Select bit0 */ ++#define PPRE21 7 /* PSC 2 Prescaler Select bit1 */ ++ ++/* PSC 2 Input A Control Register */ ++#define PFRC2A _SFR_MEM8(0xFC) ++#define PRFM2A0 0 /* PSC 2 Fault Mode bit0 */ ++#define PRFM2A1 1 /* PSC 2 Fault Mode bit1 */ ++#define PRFM2A2 2 /* PSC 2 Fault Mode bit2 */ ++#define PRFM2A3 3 /* PSC 2 Fault Mode bit3 */ ++#define PFLTE2A 4 /* PSC 2 Filter Enable on Input Part A */ ++#define PELEV2A 5 /* PSC 2 Edge Level Selector of Input Part A */ ++#define PISEL2A 6 /* PSC 2 Input Select for Part A */ ++#define PCAE2A 7 /* PSC 2 Capture Enable Input Part A */ ++ ++/* PSC 2 Input B Control Register */ ++#define PFRC2B _SFR_MEM8(0xFD) ++#define PRFM2B0 0 /* PSC 2 Fault Mode bit0 */ ++#define PRFM2B1 1 /* PSC 2 Fault Mode bit1 */ ++#define PRFM2B2 2 /* PSC 2 Fault Mode bit2 */ ++#define PRFM2B3 3 /* PSC 2 Fault Mode bit3 */ ++#define PFLTE2B 4 /* PSC 2 Filter Enable on Input Part B */ ++#define PELEV2B 5 /* PSC 2 Edge Level Selector of Input Part B */ ++#define PISEL2B 6 /* PSC 2 Input Select for Part B */ ++#define PCAE2B 7 /* PSC 2 Capture Enable Input Part B */ ++ ++/* PSC 2 Input Capture Registers */ ++#define PICR2 _SFR_MEM16(0xFE) ++#define PICR2L _SFR_MEM8(0xFE) ++#define PICR2H _SFR_MEM8(0xFF) ++#define PCST2 7 /* PSC Capture Software Trig bit */ ++ ++ ++/* Interrupt Vectors */ ++/* Interrupt 0 is the reset vector. */ ++ ++/* PSC2 Capture Event */ ++#define PSC2_CAPT_vect_num 1 ++#define PSC2_CAPT_vect _VECTOR(1) ++ ++/* PSC2 End Cycle */ ++#define PSC2_EC_vect_num 2 ++#define PSC2_EC_vect _VECTOR(2) ++ ++/* PSC1 Capture Event */ ++#define PSC1_CAPT_vect_num 3 ++#define PSC1_CAPT_vect _VECTOR(3) ++ ++/* PSC1 End Cycle */ ++#define PSC1_EC_vect_num 4 ++#define PSC1_EC_vect _VECTOR(4) ++ ++/* PSC0 Capture Event */ ++#define PSC0_CAPT_vect_num 5 ++#define PSC0_CAPT_vect _VECTOR(5) ++ ++/* PSC0 End Cycle */ ++#define PSC0_EC_vect_num 6 ++#define PSC0_EC_vect _VECTOR(6) ++ ++/* Analog Comparator 0 */ ++#define ANALOG_COMP_0_vect_num 7 ++#define ANALOG_COMP_0_vect _VECTOR(7) ++ ++/* Analog Comparator 1 */ ++#define ANALOG_COMP_1_vect_num 8 ++#define ANALOG_COMP_1_vect _VECTOR(8) ++ ++/* Analog Comparator 2 */ ++#define ANALOG_COMP_2_vect_num 9 ++#define ANALOG_COMP_2_vect _VECTOR(9) ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 10 ++#define INT0_vect _VECTOR(10) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 11 ++#define TIMER1_CAPT_vect _VECTOR(11) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 12 ++#define TIMER1_COMPA_vect _VECTOR(12) ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect_num 13 ++#define TIMER1_COMPB_vect _VECTOR(13) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 15 ++#define TIMER1_OVF_vect _VECTOR(15) ++ ++/* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMP_A_vect_num 16 ++#define TIMER0_COMP_A_vect _VECTOR(16) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 17 ++#define TIMER0_OVF_vect _VECTOR(17) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 18 ++#define ADC_vect _VECTOR(18) ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect_num 19 ++#define INT1_vect _VECTOR(19) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 20 ++#define SPI_STC_vect _VECTOR(20) ++ ++/* USART, Rx Complete */ ++#define USART_RX_vect_num 21 ++#define USART_RX_vect _VECTOR(21) ++ ++/* USART Data Register Empty */ ++#define USART_UDRE_vect_num 22 ++#define USART_UDRE_vect _VECTOR(22) ++ ++/* USART, Tx Complete */ ++#define USART_TX_vect_num 23 ++#define USART_TX_vect _VECTOR(23) ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect_num 24 ++#define INT2_vect _VECTOR(24) ++ ++/* Watchdog Timeout Interrupt */ ++#define WDT_vect_num 25 ++#define WDT_vect _VECTOR(25) ++ ++/* EEPROM Ready */ ++#define EE_READY_vect_num 26 ++#define EE_READY_vect _VECTOR(26) ++ ++/* Timer Counter 0 Compare Match B */ ++#define TIMER0_COMPB_vect_num 27 ++#define TIMER0_COMPB_vect _VECTOR(27) ++ ++/* External Interrupt Request 3 */ ++#define INT3_vect_num 28 ++#define INT3_vect _VECTOR(28) ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect_num 31 ++#define SPM_READY_vect _VECTOR(31) ++ ++#define _VECTORS_SIZE (4 * 32) ++ ++/* Constants */ ++ ++#define RAMSTART 0x100 ++#define RAMEND 0x4FF ++#define XRAMSIZE 0 ++#define XRAMEND RAMEND ++#define E2END 0x1FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x3FFF ++#define SPM_PAGESIZE 128 ++ ++ ++/* Fuse Information */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Diasble */ ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_PSCRV (unsigned char)~_BV(4) ++#define FUSE_PSC0RB (unsigned char)~_BV(5) ++#define FUSE_PSC1RB (unsigned char)~_BV(6) ++#define FUSE_PSC2RB (unsigned char)~_BV(7) ++#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x83 ++ ++ ++#endif /* _AVR_IO90PWM216_H_ */ +diff --git a/include/avr/io90pwm2b.h b/include/avr/io90pwm2b.h +index fc51f2b..12384ed 100644 +--- a/include/avr/io90pwm2b.h ++++ b/include/avr/io90pwm2b.h +@@ -1,1451 +1,1452 @@ +-/* Copyright (c) 2007 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. +-*/ +- +-/* $Id: io90pwm2b.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* avr/io90pwm2b.h - definitions for AT90PWM2B */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "io90pwm2b.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_IO90PWM2B_H_ +-#define _AVR_IO90PWM2B_H_ 1 +- +-/* Registers and associated bit numbers */ +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +-#define PINC7 7 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC3 3 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +-#define DDC7 7 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC3 3 +-#define PORTC4 4 +-#define PORTC5 5 +-#define PORTC6 6 +-#define PORTC7 7 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define PINE _SFR_IO8(0x0C) +-#define PINE0 0 +-#define PINE1 1 +-#define PINE2 2 +- +-#define DDRE _SFR_IO8(0x0D) +-#define DDE0 0 +-#define DDE1 1 +-#define DDE2 2 +- +-#define PORTE _SFR_IO8(0x0E) +-#define PORTE0 0 +-#define PORTE1 1 +-#define PORTE2 2 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define GPIOR1 _SFR_IO8(0x19) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x1A) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define GPIOR3 _SFR_IO8(0x1B) +-#define GPIOR30 0 +-#define GPIOR31 1 +-#define GPIOR32 2 +-#define GPIOR33 3 +-#define GPIOR34 4 +-#define GPIOR35 5 +-#define GPIOR36 6 +-#define GPIOR37 7 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +-#define INTF2 2 +-#define INTF3 3 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +-#define INT2 2 +-#define INT3 3 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEWE 1 +-#define EEMWE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEARL0 0 +-#define EEARL1 1 +-#define EEARL2 2 +-#define EEARL3 3 +-#define EEARL4 4 +-#define EEARL5 5 +-#define EEARL6 6 +-#define EEARL7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +-#define EEAR9 1 +-#define EEAR10 2 +-#define EEAR11 3 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSR10 0 +-#define PSRSYNC 0 +-#define ICPSEL1 2 +-#define TSM 3 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define OCR0A _SFR_IO8(0x27) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define OCR0B _SFR_IO8(0x28) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define OCR0_0 0 /* Deprecated */ +-#define OCR0_1 1 /* Deprecated */ +-#define OCR0_2 2 /* Deprecated */ +-#define OCR0_3 3 /* Deprecated */ +-#define OCR0_4 4 /* Deprecated */ +-#define OCR0_5 5 /* Deprecated */ +-#define OCR0_6 6 /* Deprecated */ +-#define OCR0_7 7 /* Deprecated */ +- +-#define PLLCSR _SFR_IO8(0x29) +-#define PLOCK 0 +-#define PLLE 1 +-#define PLLF 2 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define ACSR _SFR_IO8(0x30) +-#define AC0O 0 +-#define AC1O 1 +-#define AC2O 2 +-#define AC0IF 4 +-#define AC1IF 5 +-#define AC2IF 6 +-#define ACCKDIV 7 +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define SPIPS 7 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM0 3 +-#define PRTIM1 4 +-#define PRPSC0 5 +-#define PRPSC1 6 +-#define PRPSC2 7 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define ISC20 4 +-#define ISC21 5 +-#define ISC30 6 +-#define ISC31 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define AMP0CSR _SFR_MEM8(0x76) +-#define AMP0TS0 0 +-#define AMP0TS1 1 +-#define AMP0G0 4 +-#define AMP0G1 5 +-#define AMP0IS 6 +-#define AMP0EN 7 +- +-#define AMP1CSR _SFR_MEM8(0x77) +-#define AMP1TS0 0 +-#define AMP1TS1 1 +-#define AMP1G0 4 +-#define AMP1G1 5 +-#define AMP1IS 6 +-#define AMP1EN 7 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +- +-#define ADCL _SFR_MEM8(0x78) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_MEM8(0x79) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ADTS3 3 +-#define ADASCR 4 +-#define ADHSM 7 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define ADC8D 0 +-#define ADC9D 1 +-#define ADC10D 2 +-#define AMP0ND 3 +-#define AMP0PD 4 +-#define ACMP0D 5 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define PIFR0 _SFR_MEM8(0xA0) +-#define PEOP0 0 +-#define PRN00 1 +-#define PRN01 2 +-#define PEV0A 3 +-#define PEV0B 4 +-#define PSEI0 5 +-#define POAC0A 6 +-#define POAC0B 7 +- +-#define PIM0 _SFR_MEM8(0xA1) +-#define PEOPE0 0 +-#define PEVE0A 3 +-#define PEVE0B 4 +-#define PSEIE0 5 +- +-#define PIFR1 _SFR_MEM8(0xA2) +-#define PEOP1 0 +-#define PRN10 1 +-#define PRN11 2 +-#define PEV1A 3 +-#define PEV1B 4 +-#define PSEI1 5 +-#define POAC1A 6 +-#define POAC1B 7 +- +-#define PIM1 _SFR_MEM8(0xA3) +-#define PEOPE1 0 +-#define PEVE1A 3 +-#define PEVE1B 4 +-#define PSEIE1 5 +- +-#define PIFR2 _SFR_MEM8(0xA4) +-#define PEOP2 0 +-#define PRN20 1 +-#define PRN21 2 +-#define PEV2A 3 +-#define PEV2B 4 +-#define PSEI2 5 +-#define POAC2A 6 +-#define POAC2B 7 +- +-#define PIM2 _SFR_MEM8(0xA5) +-#define PEOPE2 0 +-#define PEVE2A 3 +-#define PEVE2B 4 +-#define PSEIE2 5 +- +-#define DACON _SFR_MEM8(0xAA) +-#define DAEN 0 +-#define DAOE 1 +-#define DALA 2 +-#define DATS0 4 +-#define DATS1 5 +-#define DATS2 6 +-#define DAATE 7 +- +-#define DAC _SFR_MEM16(0xAB) +- +-#define DACL _SFR_MEM8(0xAB) +-#define DACL0 0 +-#define DACL1 1 +-#define DACL2 2 +-#define DACL3 3 +-#define DACL4 4 +-#define DACL5 5 +-#define DACL6 6 +-#define DACL7 7 +- +-#define DACH _SFR_MEM8(0xAC) +-#define DACH0 0 +-#define DACH1 1 +-#define DACH2 2 +-#define DACH3 3 +-#define DACH4 4 +-#define DACH5 5 +-#define DACH6 6 +-#define DACH7 7 +- +-#define AC0CON _SFR_MEM8(0xAD) +-#define AC0M0 0 +-#define AC0M1 1 +-#define AC0M2 2 +-#define AC0IS0 4 +-#define AC0IS1 5 +-#define AC0IE 6 +-#define AC0EN 7 +- +-#define AC1CON _SFR_MEM8(0xAE) +-#define AC1M0 0 +-#define AC1M1 1 +-#define AC1M2 2 +-#define AC1ICE 3 +-#define AC1IS0 4 +-#define AC1IS1 5 +-#define AC1IE 6 +-#define AC1EN 7 +- +-#define AC2CON _SFR_MEM8(0xAF) +-#define AC2M0 0 +-#define AC2M1 1 +-#define AC2M2 2 +-#define AC2IS0 4 +-#define AC2IS1 5 +-#define AC2IE 6 +-#define AC2EN 7 +- +-#define UCSRA _SFR_MEM8(0xC0) +-#define MPCM 0 +-#define U2X 1 +-#define UPE 2 +-#define DOR 3 +-#define FE 4 +-#define UDRE 5 +-#define TXC 6 +-#define RXC 7 +- +-#define UCSRB _SFR_MEM8(0xC1) +-#define TXB8 0 +-#define RXB8 1 +-#define UCSZ2 2 +-#define TXEN 3 +-#define RXEN 4 +-#define UDRIE 5 +-#define TXCIE 6 +-#define RXCIE 7 +- +-#define UCSRC _SFR_MEM8(0xC2) +-#define UCPOL 0 +-#define UCSZ0 1 +-#define UCSZ1 2 +-#define USBS 3 +-#define UPM0 4 +-#define UPM1 5 +-#define UMSEL0 6 +- +-#define UBRR _SFR_MEM16(0xC4) +- +-#define UBRRL _SFR_MEM8(0xC4) +-#define UBRR0 0 +-#define UBRR1 1 +-#define UBRR2 2 +-#define UBRR3 3 +-#define UBRR4 4 +-#define UBRR5 5 +-#define UBRR6 6 +-#define UBRR7 7 +- +-#define UBRRH _SFR_MEM8(0xC5) +-#define UBRR8 0 +-#define UBRR9 1 +-#define UBRR10 2 +-#define UBRR11 3 +- +-#define UDR _SFR_MEM8(0xC6) +-#define UDR0 0 +-#define UDR1 1 +-#define UDR2 2 +-#define UDR3 3 +-#define UDR4 4 +-#define UDR5 5 +-#define UDR6 6 +-#define UDR7 7 +- +-#define EUCSRA _SFR_MEM8(0xC8) +-#define URxS0 0 +-#define URxS1 1 +-#define URxS2 2 +-#define URxS3 3 +-#define UTxS0 4 +-#define UTxS1 5 +-#define UTxS2 6 +-#define UTxS3 7 +- +-#define EUCSRB _SFR_MEM8(0xC9) +-#define BODR 0 +-#define EMCH 1 +-#define EUSBS 3 +-#define EUSART 4 +- +-#define EUCSRC _SFR_MEM8(0xCA) +-#define STP0 0 +-#define STP1 1 +-#define F1617 2 +-#define FEM 3 +- +-#define MUBRR _SFR_MEM16(0xCC) +- +-#define MUBRRL _SFR_MEM8(0xCC) +-#define MUBRR0 0 +-#define MUBRR1 1 +-#define MUBRR2 2 +-#define MUBRR3 3 +-#define MUBRR4 4 +-#define MUBRR5 5 +-#define MUBRR6 6 +-#define MUBRR7 7 +- +-#define MUBRRH _SFR_MEM8(0xCD) +-#define MUBRR8 0 +-#define MUBRR9 1 +-#define MUBRR10 2 +-#define MUBRR11 3 +-#define MUBRR12 4 +-#define MUBRR13 5 +-#define MUBRR14 6 +-#define MUBRR15 7 +- +-#define EUDR _SFR_MEM8(0xCE) +-#define EUDR0 0 +-#define EUDR1 1 +-#define EUDR2 2 +-#define EUDR3 3 +-#define EUDR4 4 +-#define EUDR5 5 +-#define EUDR6 6 +-#define EUDR7 7 +- +-#define PSOC0 _SFR_MEM8(0xD0) +-#define POEN0A 0 +-#define POEN0B 2 +-#define PSYNC00 4 +-#define PSYNC01 5 +- +-#define OCR0SA _SFR_MEM16(0xD2) +- +-#define OCR0SAL _SFR_MEM8(0xD2) +-#define OCR0SA_0 0 +-#define OCR0SA_1 1 +-#define OCR0SA_2 2 +-#define OCR0SA_3 3 +-#define OCR0SA_4 4 +-#define OCR0SA_5 5 +-#define OCR0SA_6 6 +-#define OCR0SA_7 7 +- +-#define OCR0SAH _SFR_MEM8(0xD3) +-#define OCR0SA_8 0 +-#define OCR0SA_9 1 +-#define OCR0SA_00 2 +-#define OCR0SA_01 3 +- +-#define OCR0RA _SFR_MEM16(0xD4) +- +-#define OCR0RAL _SFR_MEM8(0xD4) +-#define OCR0RA_0 0 +-#define OCR0RA_1 1 +-#define OCR0RA_2 2 +-#define OCR0RA_3 3 +-#define OCR0RA_4 4 +-#define OCR0RA_5 5 +-#define OCR0RA_6 6 +-#define OCR0RA_7 7 +- +-#define OCR0RAH _SFR_MEM8(0xD5) +-#define OCR0RA_8 0 +-#define OCR0RA_9 1 +-#define OCR0RA_00 2 +-#define OCR0RA_01 3 +- +-#define OCR0SB _SFR_MEM16(0xD6) +- +-#define OCR0SBL _SFR_MEM8(0xD6) +-#define OCR0SB_0 0 +-#define OCR0SB_1 1 +-#define OCR0SB_2 2 +-#define OCR0SB_3 3 +-#define OCR0SB_4 4 +-#define OCR0SB_5 5 +-#define OCR0SB_6 6 +-#define OCR0SB_7 7 +- +-#define OCR0SBH _SFR_MEM8(0xD7) +-#define OCR0SB_8 0 +-#define OCR0SB_9 1 +-#define OCR0SB_00 2 +-#define OCR0SB_01 3 +- +-#define OCR0RB _SFR_MEM16(0xD8) +- +-#define OCR0RBL _SFR_MEM8(0xD8) +-#define OCR0RB_0 0 +-#define OCR0RB_1 1 +-#define OCR0RB_2 2 +-#define OCR0RB_3 3 +-#define OCR0RB_4 4 +-#define OCR0RB_5 5 +-#define OCR0RB_6 6 +-#define OCR0RB_7 7 +- +-#define OCR0RBH _SFR_MEM8(0xD9) +-#define OCR0RB_8 0 +-#define OCR0RB_9 1 +-#define OCR0RB_00 2 +-#define OCR0RB_01 3 +-#define OCR0RB_02 4 +-#define OCR0RB_03 5 +-#define OCR0RB_04 6 +-#define OCR0RB_05 7 +- +-#define PCNF0 _SFR_MEM8(0xDA) +-#define PCLKSEL0 1 +-#define POP0 2 +-#define PMODE00 3 +-#define PMODE01 4 +-#define PLOCK0 5 +-#define PALOCK0 6 +-#define PFIFTY0 7 +- +-#define PCTL0 _SFR_MEM8(0xDB) +-#define PRUN0 0 +-#define PCCYC0 1 +-#define PARUN0 2 +-#define PAOC0A 3 +-#define PAOC0B 4 +-#define PBFM0 5 +-#define PPRE00 6 +-#define PPRE01 7 +- +-#define PFRC0A _SFR_MEM8(0xDC) +-#define PRFM0A0 0 +-#define PRFM0A1 1 +-#define PRFM0A2 2 +-#define PRFM0A3 3 +-#define PFLTE0A 4 +-#define PELEV0A 5 +-#define PISEL0A 6 +-#define PCAE0A 7 +- +-#define PFRC0B _SFR_MEM8(0xDD) +-#define PRFM0B0 0 +-#define PRFM0B1 1 +-#define PRFM0B2 2 +-#define PRFM0B3 3 +-#define PFLTE0B 4 +-#define PELEV0B 5 +-#define PISEL0B 6 +-#define PCAE0B 7 +- +-#define PICR0 _SFR_MEM16(0xDE) +- +-#define PICR0L _SFR_MEM8(0xDE) +-#define PICR0_0 0 +-#define PICR0_1 1 +-#define PICR0_2 2 +-#define PICR0_3 3 +-#define PICR0_4 4 +-#define PICR0_5 5 +-#define PICR0_6 6 +-#define PICR0_7 7 +- +-#define PICR0H _SFR_MEM8(0xDF) +-#define PICR0_8 0 +-#define PICR0_9 1 +-#define PICR0_10 2 +-#define PICR0_11 3 +-#define PCST0 7 +- +-#define PSOC1 _SFR_MEM8(0xE0) +-#define POEN1A 0 +-#define POEN1B 2 +-#define PSYNC1_0 4 +-#define PSYNC1_1 5 +- +-#define OCR1SA _SFR_MEM16(0xE2) +- +-#define OCR1SAL _SFR_MEM8(0xE2) +-#define OCR1SA_0 0 +-#define OCR1SA_1 1 +-#define OCR1SA_2 2 +-#define OCR1SA_3 3 +-#define OCR1SA_4 4 +-#define OCR1SA_5 5 +-#define OCR1SA_6 6 +-#define OCR1SA_7 7 +- +-#define OCR1SAH _SFR_MEM8(0xE3) +-#define OCR1SA_8 0 +-#define OCR1SA_9 1 +-#define OCR1SA_10 2 +-#define OCR1SA_11 3 +- +-#define OCR1RA _SFR_MEM16(0xE4) +- +-#define OCR1RAL _SFR_MEM8(0xE4) +-#define OCR1RA_0 0 +-#define OCR1RA_1 1 +-#define OCR1RA_2 2 +-#define OCR1RA_3 3 +-#define OCR1RA_4 4 +-#define OCR1RA_5 5 +-#define OCR1RA_6 6 +-#define OCR1RA_7 7 +- +-#define OCR1RAH _SFR_MEM8(0xE5) +-#define OCR1RA_8 0 +-#define OCR1RA_9 1 +-#define OCR1RA_10 2 +-#define OCR1RA_11 3 +- +-#define OCR1SB _SFR_MEM16(0xE6) +- +-#define OCR1SBL _SFR_MEM8(0xE6) +-#define OCR1SB_0 0 +-#define OCR1SB_1 1 +-#define OCR1SB_2 2 +-#define OCR1SB_3 3 +-#define OCR1SB_4 4 +-#define OCR1SB_5 5 +-#define OCR1SB_6 6 +-#define OCR1SB_7 7 +- +-#define OCR1SBH _SFR_MEM8(0xE7) +-#define OCR1SB_8 0 +-#define OCR1SB_9 1 +-#define OCR1SB_10 2 +-#define OCR1SB_11 3 +- +-#define OCR1RB _SFR_MEM16(0xE8) +- +-#define OCR1RBL _SFR_MEM8(0xE8) +-#define OCR1RB_0 0 +-#define OCR1RB_1 1 +-#define OCR1RB_2 2 +-#define OCR1RB_3 3 +-#define OCR1RB_4 4 +-#define OCR1RB_5 5 +-#define OCR1RB_6 6 +-#define OCR1RB_7 7 +- +-#define OCR1RBH _SFR_MEM8(0xE9) +-#define OCR1RB_8 0 +-#define OCR1RB_9 1 +-#define OCR1RB_10 2 +-#define OCR1RB_11 3 +-#define OCR1RB_12 4 +-#define OCR1RB_13 5 +-#define OCR1RB_14 6 +-#define OCR1RB_15 7 +- +-#define PCNF1 _SFR_MEM8(0xEA) +-#define PCLKSEL1 1 +-#define POP1 2 +-#define PMODE10 3 +-#define PMODE11 4 +-#define PLOCK1 5 +-#define PALOCK1 6 +-#define PFIFTY1 7 +- +-#define PCTL1 _SFR_MEM8(0xEB) +-#define PRUN1 0 +-#define PCCYC1 1 +-#define PARUN1 2 +-#define PAOC1A 3 +-#define PAOC1B 4 +-#define PBFM1 5 +-#define PPRE10 6 +-#define PPRE11 7 +- +-#define PFRC1A _SFR_MEM8(0xEC) +-#define PRFM1A0 0 +-#define PRFM1A1 1 +-#define PRFM1A2 2 +-#define PRFM1A3 3 +-#define PFLTE1A 4 +-#define PELEV1A 5 +-#define PISEL1A 6 +-#define PCAE1A 7 +- +-#define PFRC1B _SFR_MEM8(0xED) +-#define PRFM1B0 0 +-#define PRFM1B1 1 +-#define PRFM1B2 2 +-#define PRFM1B3 3 +-#define PFLTE1B 4 +-#define PELEV1B 5 +-#define PISEL1B 6 +-#define PCAE1B 7 +- +-#define PICR1 _SFR_MEM16(0xEE) +- +-#define PICR1L _SFR_MEM8(0xEE) +-#define PICR1_0 0 +-#define PICR1_1 1 +-#define PICR1_2 2 +-#define PICR1_3 3 +-#define PICR1_4 4 +-#define PICR1_5 5 +-#define PICR1_6 6 +-#define PICR1_7 7 +- +-#define PICR1H _SFR_MEM8(0xEF) +-#define PICR1_8 0 +-#define PICR1_9 1 +-#define PICR1_10 2 +-#define PICR1_11 3 +-#define PCST1 7 +- +-#define PSOC2 _SFR_MEM8(0xF0) +-#define POEN2A 0 +-#define POEN2C 1 +-#define POEN2B 2 +-#define POEN2D 3 +-#define PSYNC2_0 4 +-#define PSYNC2_1 5 +-#define POS22 6 +-#define POS23 7 +- +-#define POM2 _SFR_MEM8(0xF1) +-#define POMV2A0 0 +-#define POMV2A1 1 +-#define POMV2A2 2 +-#define POMV2A3 3 +-#define POMV2B0 4 +-#define POMV2B1 5 +-#define POMV2B2 6 +-#define POMV2B3 7 +- +-#define OCR2SA _SFR_MEM16(0xF2) +- +-#define OCR2SAL _SFR_MEM8(0xF2) +-#define OCR2SA_0 0 +-#define OCR2SA_1 1 +-#define OCR2SA_2 2 +-#define OCR2SA_3 3 +-#define OCR2SA_4 4 +-#define OCR2SA_5 5 +-#define OCR2SA_6 6 +-#define OCR2SA_7 7 +- +-#define OCR2SAH _SFR_MEM8(0xF3) +-#define OCR2SA_8 0 +-#define OCR2SA_9 1 +-#define OCR2SA_10 2 +-#define OCR2SA_11 3 +- +-#define OCR2RA _SFR_MEM16(0xF4) +- +-#define OCR2RAL _SFR_MEM8(0xF4) +-#define OCR2RA_0 0 +-#define OCR2RA_1 1 +-#define OCR2RA_2 2 +-#define OCR2RA_3 3 +-#define OCR2RA_4 4 +-#define OCR2RA_5 5 +-#define OCR2RA_6 6 +-#define OCR2RA_7 7 +- +-#define OCR2RAH _SFR_MEM8(0xF5) +-#define OCR2RA_8 0 +-#define OCR2RA_9 1 +-#define OCR2RA_10 2 +-#define OCR2RA_11 3 +- +-#define OCR2SB _SFR_MEM16(0xF6) +- +-#define OCR2SBL _SFR_MEM8(0xF6) +-#define OCR2SB_0 0 +-#define OCR2SB_1 1 +-#define OCR2SB_2 2 +-#define OCR2SB_3 3 +-#define OCR2SB_4 4 +-#define OCR2SB_5 5 +-#define OCR2SB_6 6 +-#define OCR2SB_7 7 +- +-#define OCR2SBH _SFR_MEM8(0xF7) +-#define OCR2SB_8 0 +-#define OCR2SB_9 1 +-#define OCR2SB_10 2 +-#define OCR2SB_11 3 +- +-#define OCR2RB _SFR_MEM16(0xF8) +- +-#define OCR2RBL _SFR_MEM8(0xF8) +-#define OCR2RB_0 0 +-#define OCR2RB_1 1 +-#define OCR2RB_2 2 +-#define OCR2RB_3 3 +-#define OCR2RB_4 4 +-#define OCR2RB_5 5 +-#define OCR2RB_6 6 +-#define OCR2RB_7 7 +- +-#define OCR2RBH _SFR_MEM8(0xF9) +-#define OCR2RB_8 0 +-#define OCR2RB_9 1 +-#define OCR2RB_10 2 +-#define OCR2RB_11 3 +-#define OCR2RB_12 4 +-#define OCR2RB_13 5 +-#define OCR2RB_14 6 +-#define OCR2RB_15 7 +- +-#define PCNF2 _SFR_MEM8(0xFA) +-#define POME2 0 +-#define PCLKSEL2 1 +-#define POP2 2 +-#define PMODE20 3 +-#define PMODE21 4 +-#define PLOCK2 5 +-#define PALOCK2 6 +-#define PFIFTY2 7 +- +-#define PCTL2 _SFR_MEM8(0xFB) +-#define PRUN2 0 +-#define PCCYC2 1 +-#define PARUN2 2 +-#define PAOC2A 3 +-#define PAOC2B 4 +-#define PBFM2 5 +-#define PPRE20 6 +-#define PPRE21 7 +- +-#define PFRC2A _SFR_MEM8(0xFC) +-#define PRFM2A0 0 +-#define PRFM2A1 1 +-#define PRFM2A2 2 +-#define PRFM2A3 3 +-#define PFLTE2A 4 +-#define PELEV2A 5 +-#define PISEL2A 6 +-#define PCAE2A 7 +- +-#define PFRC2B _SFR_MEM8(0xFD) +-#define PRFM2B0 0 +-#define PRFM2B1 1 +-#define PRFM2B2 2 +-#define PRFM2B3 3 +-#define PFLTE2B 4 +-#define PELEV2B 5 +-#define PISEL2B 6 +-#define PCAE2B 7 +- +-#define PICR2 _SFR_MEM16(0xFE) +- +-#define PICR2L _SFR_MEM8(0xFE) +-#define PICR2_0 0 +-#define PICR2_1 1 +-#define PICR2_2 2 +-#define PICR2_3 3 +-#define PICR2_4 4 +-#define PICR2_5 5 +-#define PICR2_6 6 +-#define PICR2_7 7 +- +-#define PICR2H _SFR_MEM8(0xFF) +-#define PICR2_8 0 +-#define PICR2_9 1 +-#define PICR2_10 2 +-#define PICR2_11 3 +-#define PCST2 7 +- +- +- +-/* Interrupt Vectors */ +-/* Interrupt vector 0 is the reset vector. */ +- +-#define PSC2_CAPT_vect_num 1 +-#define PSC2_CAPT_vect _VECTOR(1) /* PSC2 Capture Event */ +- +-#define PSC2_EC_vect_num 2 +-#define PSC2_EC_vect _VECTOR(2) /* PSC2 End Cycle */ +- +-#define PSC1_CAPT_vect_num 3 +-#define PSC1_CAPT_vect _VECTOR(3) /* PSC1 Capture Event */ +- +-#define PSC1_EC_vect_num 4 +-#define PSC1_EC_vect _VECTOR(4) /* PSC1 End Cycle */ +- +-#define PSC0_CAPT_vect_num 5 +-#define PSC0_CAPT_vect _VECTOR(5) /* PSC0 Capture Event */ +- +-#define PSC0_EC_vect_num 6 +-#define PSC0_EC_vect _VECTOR(6) /* PSC0 End Cycle */ +- +-#define ANALOG_COMP_0_vect_num 7 +-#define ANALOG_COMP_0_vect _VECTOR(7) /* Analog Comparator 0 */ +- +-#define ANALOG_COMP_1_vect_num 8 +-#define ANALOG_COMP_1_vect _VECTOR(8) /* Analog Comparator 1 */ +- +-#define ANALOG_COMP_2_vect_num 9 +-#define ANALOG_COMP_2_vect _VECTOR(9) /* Analog Comparator 2 */ +- +-#define INT0_vect_num 10 +-#define INT0_vect _VECTOR(10) /* External Interrupt Request 0 */ +- +-#define TIMER1_CAPT_vect_num 11 +-#define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */ +- +-#define TIMER1_COMPA_vect_num 12 +-#define TIMER1_COMPA_vect _VECTOR(12) /* Timer/Counter1 Compare Match A */ +- +-#define TIMER1_COMPB_vect_num 13 +-#define TIMER1_COMPB_vect _VECTOR(13) /* Timer/Counter Compare Match B */ +- +-/* Vector 14, Reserved */ +- +-#define TIMER1_OVF_vect_num 15 +-#define TIMER1_OVF_vect _VECTOR(15) /* Timer/Counter1 Overflow */ +- +-#define TIMER0_COMPA_vect_num 16 +-#define TIMER0_COMPA_vect _VECTOR(16) /* Timer/Counter0 Compare Match A */ +- +-#define TIMER0_OVF_vect_num 17 +-#define TIMER0_OVF_vect _VECTOR(17) /* Timer/Counter0 Overflow */ +- +-#define ADC_vect_num 18 +-#define ADC_vect _VECTOR(18) /* ADC Conversion Complete */ +- +-#define INT1_vect_num 19 +-#define INT1_vect _VECTOR(19) /* External Interrupt Request 1 */ +- +-#define SPI_STC_vect_num 20 +-#define SPI_STC_vect _VECTOR(20) /* SPI Serial Transfer Complete */ +- +-#define USART_RX_vect_num 21 +-#define USART_RX_vect _VECTOR(21) /* USART, Rx Complete */ +- +-#define USART_UDRE_vect_num 22 +-#define USART_UDRE_vect _VECTOR(22) /* USART Data Register Empty */ +- +-#define USART_TX_vect_num 23 +-#define USART_TX_vect _VECTOR(23) /* USART, Tx Complete */ +- +-#define INT2_vect_num 24 +-#define INT2_vect _VECTOR(24) /* External Interrupt Request 2 */ +- +-#define WDT_vect_num 25 +-#define WDT_vect _VECTOR(25) /* Watchdog Timeout Interrupt */ +- +-#define EE_READY_vect_num 26 +-#define EE_READY_vect _VECTOR(26) /* EEPROM Ready */ +- +-#define TIMER0_COMPB_vect_num 27 +-#define TIMER0_COMPB_vect _VECTOR(27) /* Timer Counter 0 Compare Match B */ +- +-#define INT3_vect_num 28 +-#define INT3_vect _VECTOR(28) /* External Interrupt Request 3 */ +- +-/* Vector 29, Reserved */ +- +-/* Vector 30, Reserved */ +- +-#define SPM_READY_vect_num 31 +-#define SPM_READY_vect _VECTOR(31) /* Store Program Memory Read */ +- +-#define _VECTORS_SIZE 64 +- +- +- +-/* Memory Sizes */ +-#define RAMEND 0x2FF +-#define XRAMSIZE 0 +-#define XRAMEND RAMEND +-#define E2END 0x1FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x1FFF +-#define SPM_PAGESIZE 64 +- +- +- +-/* Fuse Information */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +- +-/* High Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ --#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) - #define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ - #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ - #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ - #define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ - #define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ --#define HFUSE_DEFAULT (FUSE_SPIEN) -+#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) - - /* Extended Fuse Byte */ --#define FUSE_BOOTRST (unsigned char)~_BV(0) --#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) --#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown out detector trigger level */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +- +-/* Extended Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_PSCRV (unsigned char)~_BV(4) /* PSCOUT Reset Value */ +-#define FUSE_PSC0RB (unsigned char)~_BV(5) /* PSC0 Reset Behaviour */ +-#define FUSE_PSC1RB (unsigned char)~_BV(6) /* PSC1 Reset Behaviour */ +-#define FUSE_PSC2RB (unsigned char)~_BV(7) /* PSC2 Reset Behaviour */ -#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ -+ -+#define EFUSE_DEFAULT () - - - -diff --git a/include/avr/iom3290a.h b/include/avr/iom3290a.h -new file mode 100644 -index 0000000..96f2bcd ---- /dev/null -+++ b/include/avr/iom3290a.h -@@ -0,0 +1,34 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2011 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+#include "iom3290.h" -diff --git a/include/avr/iom3290p.h b/include/avr/iom3290p.h -new file mode 100644 -index 0000000..96f2bcd ---- /dev/null -+++ b/include/avr/iom3290p.h -@@ -0,0 +1,34 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2011 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+#include "iom3290.h" -diff --git a/include/avr/iom3290pa.h b/include/avr/iom3290pa.h -new file mode 100644 -index 0000000..3cc79d9 ---- /dev/null -+++ b/include/avr/iom3290pa.h -@@ -0,0 +1,965 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATMEGA3290PA_H_INCLUDED -+#define _AVR_ATMEGA3290PA_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iom3290pa.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINA _SFR_IO8(0x00) -+#define PINA7 7 -+#define PINA6 6 -+#define PINA5 5 -+#define PINA4 4 -+#define PINA3 3 -+#define PINA2 2 -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x01) -+#define DDRA7 7 -+#define DDRA6 6 -+#define DDRA5 5 -+#define DDRA4 4 -+#define DDRA3 3 -+#define DDRA2 2 -+#define DDRA1 1 -+#define DDRA0 0 -+ -+#define PORTA _SFR_IO8(0x02) -+#define PORTA7 7 -+#define PORTA6 6 -+#define PORTA5 5 -+#define PORTA4 4 -+#define PORTA3 3 -+#define PORTA2 2 -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x06) -+#define PINC7 7 -+#define PINC6 6 -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x07) -+#define DDRC7 7 -+#define DDRC6 6 -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x08) -+#define PORTC7 7 -+#define PORTC6 6 -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PIND _SFR_IO8(0x09) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0A) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x0B) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+#define PINE _SFR_IO8(0x0C) -+#define PINE7 7 -+#define PINE6 6 -+#define PINE5 5 -+#define PINE4 4 -+#define PINE3 3 -+#define PINE2 2 -+#define PINE1 1 -+#define PINE0 0 -+ -+#define DDRE _SFR_IO8(0x0D) -+#define DDRE7 7 -+#define DDRE6 6 -+#define DDRE5 5 -+#define DDRE4 4 -+#define DDRE3 3 -+#define DDRE2 2 -+#define DDRE1 1 -+#define DDRE0 0 -+ -+#define PORTE _SFR_IO8(0x0E) -+#define PORTE7 7 -+#define PORTE6 6 -+#define PORTE5 5 -+#define PORTE4 4 -+#define PORTE3 3 -+#define PORTE2 2 -+#define PORTE1 1 -+#define PORTE0 0 -+ -+#define PINF _SFR_IO8(0x0F) -+#define PINF7 7 -+#define PINF6 6 -+#define PINF5 5 -+#define PINF4 4 -+#define PINF3 3 -+#define PINF2 2 -+#define PINF1 1 -+#define PINF0 0 -+ -+#define DDRF _SFR_IO8(0x10) -+#define DDRF7 7 -+#define DDRF6 6 -+#define DDRF5 5 -+#define DDRF4 4 -+#define DDRF3 3 -+#define DDRF2 2 -+#define DDRF1 1 -+#define DDRF0 0 -+ -+#define PORTF _SFR_IO8(0x11) -+#define PORTF7 7 -+#define PORTF6 6 -+#define PORTF5 5 -+#define PORTF4 4 -+#define PORTF3 3 -+#define PORTF2 2 -+#define PORTF1 1 -+#define PORTF0 0 -+ -+#define PING _SFR_IO8(0x12) -+#define PING5 5 -+#define PING4 4 -+#define PING3 3 -+#define PING2 2 -+#define PING1 1 -+#define PING0 0 -+ -+#define DDRG _SFR_IO8(0x13) -+#define DDRG4 4 -+#define DDRG3 3 -+#define DDRG2 2 -+#define DDRG1 1 -+#define DDRG0 0 -+ -+#define PORTG _SFR_IO8(0x14) -+#define PORTG4 4 -+#define PORTG3 3 -+#define PORTG2 2 -+#define PORTG1 1 -+#define PORTG0 0 -+ -+#define TIFR0 _SFR_IO8(0x15) -+#define TOV0 0 -+#define OCF0A 1 -+ -+#define TIFR1 _SFR_IO8(0x16) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define ICF1 5 -+ -+#define TIFR2 _SFR_IO8(0x17) -+#define TOV2 0 -+#define OCF2A 1 -+ -+/* Reserved [0x18..0x1B] */ -+ -+#define EIFR _SFR_IO8(0x1C) -+#define INTF0 0 -+#define PCIF0 4 -+#define PCIF1 5 -+#define PCIF2 6 -+#define PCIF3 7 -+ -+#define EIMSK _SFR_IO8(0x1D) -+#define INT0 0 -+#define PCIE0 4 -+#define PCIE1 5 -+#define PCIE2 6 -+#define PCIE3 7 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEWE 1 -+#define EEMWE 2 -+#define EERIE 3 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSR310 0 -+#define TSM 7 -+#define PSR2 1 -+ -+#define TCCR0A _SFR_IO8(0x24) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define WGM01 3 -+#define COM0A0 4 -+#define COM0A1 5 -+#define WGM00 6 -+#define FOC0A 7 -+ -+/* Reserved [0x25] */ -+ -+#define TCNT0 _SFR_IO8(0x26) -+ -+#define OCR0A _SFR_IO8(0x27) -+ -+/* Reserved [0x28..0x29] */ -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+/* Reserved [0x2F] */ -+ -+#define ACSR _SFR_IO8(0x30) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACBG 6 -+#define ACD 7 -+ -+#define OCDR _SFR_IO8(0x31) -+#define OCDR7 7 -+#define OCDR6 6 -+#define OCDR5 5 -+#define OCDR4 4 -+#define OCDR3 3 -+#define OCDR2 2 -+#define OCDR1 1 -+#define OCDR0 0 -+ -+/* Reserved [0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define JTRF 4 -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define JTD 7 -+#define IVCE 0 -+#define IVSEL 1 -+#define PUD 4 -+#define BODSE 5 -+#define BODS 6 -+ -+/* Reserved [0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+/* Reserved [0x38..0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCR _SFR_MEM8(0x60) -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDE 3 -+#define WDCE 4 -+ -+#define CLKPR _SFR_MEM8(0x61) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+#define CLKPCE 7 -+ -+/* Reserved [0x62..0x63] */ -+ -+#define PRR _SFR_MEM8(0x64) -+#define PRADC 0 -+#define PRUSART0 1 -+#define PRSPI 2 -+#define PRTIM1 3 -+#define PRLCD 4 -+ -+/* Reserved [0x65] */ -+ -+#define OSCCAL _SFR_MEM8(0x66) -+#define OSCCAL0 0 -+#define OSCCAL1 1 -+#define OSCCAL2 2 -+#define OSCCAL3 3 -+#define OSCCAL4 4 -+#define OSCCAL5 5 -+#define OSCCAL6 6 -+#define OSCCAL7 7 -+ -+/* Reserved [0x67..0x68] */ -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+ -+/* Reserved [0x6A] */ -+ -+#define PCMSK0 _SFR_MEM8(0x6B) -+ -+#define PCMSK1 _SFR_MEM8(0x6C) -+ -+#define PCMSK2 _SFR_MEM8(0x6D) -+ -+#define TIMSK0 _SFR_MEM8(0x6E) -+#define TOIE0 0 -+#define OCIE0A 1 -+ -+#define TIMSK1 _SFR_MEM8(0x6F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define ICIE1 5 -+ -+#define TIMSK2 _SFR_MEM8(0x70) -+#define TOIE2 0 -+#define OCIE2A 1 -+ -+/* Reserved [0x71..0x72] */ -+ -+#define PCMSK3 _SFR_MEM8(0x73) -+ -+/* Reserved [0x74..0x77] */ -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_MEM16(0x78) -+#endif -+#define ADCW _SFR_MEM16(0x78) -+ -+#define ADCL _SFR_MEM8(0x78) -+#define ADCH _SFR_MEM8(0x79) -+ -+#define ADCSRA _SFR_MEM8(0x7A) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADCSRB _SFR_MEM8(0x7B) -+#define ACME 6 -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+ -+#define ADMUX _SFR_MEM8(0x7C) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define MUX4 4 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+/* Reserved [0x7D] */ -+ -+#define DIDR0 _SFR_MEM8(0x7E) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+#define ADC6D 6 -+#define ADC7D 7 -+ -+#define DIDR1 _SFR_MEM8(0x7F) -+#define AIN0D 0 -+#define AIN1D 1 -+ -+#define TCCR1A _SFR_MEM8(0x80) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR1B _SFR_MEM8(0x81) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1C _SFR_MEM8(0x82) -+#define FOC1B 6 -+#define FOC1A 7 -+ -+/* Reserved [0x83] */ -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x84) -+ -+#define TCNT1L _SFR_MEM8(0x84) -+#define TCNT1H _SFR_MEM8(0x85) -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x86) -+ -+#define ICR1L _SFR_MEM8(0x86) -+#define ICR1H _SFR_MEM8(0x87) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_MEM16(0x88) -+ -+#define OCR1AL _SFR_MEM8(0x88) -+#define OCR1AH _SFR_MEM8(0x89) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_MEM16(0x8A) -+ -+#define OCR1BL _SFR_MEM8(0x8A) -+#define OCR1BH _SFR_MEM8(0x8B) -+ -+/* Reserved [0x8C..0xAF] */ -+ -+#define TCCR2A _SFR_MEM8(0xB0) -+#define CS20 0 -+#define CS21 1 -+#define CS22 2 -+#define WGM21 3 -+#define COM2A0 4 -+#define COM2A1 5 -+#define WGM20 6 -+#define FOC2A 7 -+ -+/* Reserved [0xB1] */ -+ -+#define TCNT2 _SFR_MEM8(0xB2) -+ -+#define OCR2A _SFR_MEM8(0xB3) -+ -+/* Reserved [0xB4..0xB5] */ -+ -+#define ASSR _SFR_MEM8(0xB6) -+#define TCR2UB 0 -+#define OCR2UB 1 -+#define TCN2UB 2 -+#define AS2 3 -+#define EXCLK 4 -+ -+/* Reserved [0xB7] */ -+ -+#define USICR _SFR_MEM8(0xB8) -+#define USITC 0 -+#define USICLK 1 -+#define USICS0 2 -+#define USICS1 3 -+#define USIWM0 4 -+#define USIWM1 5 -+#define USIOIE 6 -+#define USISIE 7 -+ -+#define USISR _SFR_MEM8(0xB9) -+#define USICNT0 0 -+#define USICNT1 1 -+#define USICNT2 2 -+#define USICNT3 3 -+#define USIDC 4 -+#define USIPF 5 -+#define USIOIF 6 -+#define USISIF 7 -+ -+#define USIDR _SFR_MEM8(0xBA) -+ -+/* Reserved [0xBB..0xBF] */ -+ -+#define UCSR0A _SFR_MEM8(0xC0) -+#define MPCM0 0 -+#define U2X0 1 -+#define UPE0 2 -+#define DOR0 3 -+#define FE0 4 -+#define UDRE0 5 -+#define TXC0 6 -+#define RXC0 7 -+ -+#define UCSR0B _SFR_MEM8(0xC1) -+#define TXB80 0 -+#define RXB80 1 -+#define UCSZ02 2 -+#define TXEN0 3 -+#define RXEN0 4 -+#define UDRIE0 5 -+#define TXCIE0 6 -+#define RXCIE0 7 -+ -+#define UCSR0C _SFR_MEM8(0xC2) -+#define UCPOL0 0 -+#define UCSZ00 1 -+#define UCSZ01 2 -+#define USBS0 3 -+#define UPM00 4 -+#define UPM01 5 -+#define UMSEL0 6 -+ -+/* Reserved [0xC3] */ -+ -+/* Combine UBRR0L and UBRR0H */ -+#define UBRR0 _SFR_MEM16(0xC4) -+ -+#define UBRR0L _SFR_MEM8(0xC4) -+#define UBRR0H _SFR_MEM8(0xC5) -+ -+#define UDR0 _SFR_MEM8(0xC6) -+ -+/* Reserved [0xC7..0xD7] */ -+ -+#define PINH _SFR_MEM8(0xD8) -+#define PINH7 7 -+#define PINH6 6 -+#define PINH5 5 -+#define PINH4 4 -+#define PINH3 3 -+#define PINH2 2 -+#define PINH1 1 -+#define PINH0 0 -+ -+#define DDRH _SFR_MEM8(0xD9) -+#define DDRH7 7 -+#define DDRH6 6 -+#define DDRH5 5 -+#define DDRH4 4 -+#define DDRH3 3 -+#define DDRH2 2 -+#define DDRH1 1 -+#define DDRH0 0 -+ -+#define PORTH _SFR_MEM8(0xDA) -+#define PORTH7 7 -+#define PORTH6 6 -+#define PORTH5 5 -+#define PORTH4 4 -+#define PORTH3 3 -+#define PORTH2 2 -+#define PORTH1 1 -+#define PORTH0 0 -+ -+#define PINJ _SFR_MEM8(0xDB) -+#define PINJ6 6 -+#define PINJ5 5 -+#define PINJ4 4 -+#define PINJ3 3 -+#define PINJ2 2 -+#define PINJ1 1 -+#define PINJ0 0 -+ -+#define DDRJ _SFR_MEM8(0xDC) -+#define DDRJ6 6 -+#define DDRJ5 5 -+#define DDRJ4 4 -+#define DDRJ3 3 -+#define DDRJ2 2 -+#define DDRJ1 1 -+#define DDRJ0 0 -+ -+#define PORTJ _SFR_MEM8(0xDD) -+#define PORTJ6 6 -+#define PORTJ5 5 -+#define PORTJ4 4 -+#define PORTJ3 3 -+#define PORTJ2 2 -+#define PORTJ1 1 -+#define PORTJ0 0 -+ -+/* Reserved [0xDE..0xE3] */ -+ -+#define LCDCRA _SFR_MEM8(0xE4) -+#define LCDBL 0 -+#define LCDCCD 1 -+#define LCDBD 2 -+#define LCDIE 3 -+#define LCDIF 4 -+#define LCDAB 6 -+#define LCDEN 7 -+ -+#define LCDCRB _SFR_MEM8(0xE5) -+#define LCDPM0 0 -+#define LCDPM1 1 -+#define LCDPM2 2 -+#define LCDPM3 3 -+#define LCDMUX0 4 -+#define LCDMUX1 5 -+#define LCD2B 6 -+#define LCDCS 7 -+ -+#define LCDFRR _SFR_MEM8(0xE6) -+#define LCDCD0 0 -+#define LCDCD1 1 -+#define LCDCD2 2 -+#define LCDPS0 4 -+#define LCDPS1 5 -+#define LCDPS2 6 -+ -+#define LCDCCR _SFR_MEM8(0xE7) -+#define LCDCC0 0 -+#define LCDCC1 1 -+#define LCDCC2 2 -+#define LCDCC3 3 -+#define LCDMDT 4 -+#define LCDDC0 5 -+#define LCDDC1 6 -+#define LCDDC2 7 -+ -+/* Reserved [0xE8..0xEB] */ -+ -+#define LCDDR0 _SFR_MEM8(0xEC) -+ -+#define LCDDR1 _SFR_MEM8(0xED) -+ -+#define LCDDR2 _SFR_MEM8(0xEE) -+ -+#define LCDDR3 _SFR_MEM8(0xEF) -+ -+#define LCDDR4 _SFR_MEM8(0xF0) -+ -+#define LCDDR5 _SFR_MEM8(0xF1) -+ -+#define LCDDR6 _SFR_MEM8(0xF2) -+ -+#define LCDDR7 _SFR_MEM8(0xF3) -+ -+#define LCDDR8 _SFR_MEM8(0xF4) -+ -+#define LCDDR9 _SFR_MEM8(0xF5) -+ -+#define LCDDR10 _SFR_MEM8(0xF6) -+ -+#define LCDDR11 _SFR_MEM8(0xF7) -+ -+#define LCDDR12 _SFR_MEM8(0xF8) -+ -+#define LCDDR13 _SFR_MEM8(0xF9) -+ -+#define LCDDR14 _SFR_MEM8(0xFA) -+ -+#define LCDDR15 _SFR_MEM8(0xFB) -+ -+#define LCDDR16 _SFR_MEM8(0xFC) -+ -+#define LCDDR17 _SFR_MEM8(0xFD) -+ -+#define LCDDR18 _SFR_MEM8(0xFE) -+ -+#define LCDDR19 _SFR_MEM8(0xFF) -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(2) -+#define PCINT0_vect_num 2 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(3) -+#define PCINT1_vect_num 3 -+ -+/* Timer/Counter2 Compare Match */ -+#define TIMER2_COMP_vect _VECTOR(4) -+#define TIMER2_COMP_vect_num 4 -+ -+/* Timer/Counter2 Overflow */ -+#define TIMER2_OVF_vect _VECTOR(5) -+#define TIMER2_OVF_vect_num 5 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(6) -+#define TIMER1_CAPT_vect_num 6 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(7) -+#define TIMER1_COMPA_vect_num 7 -+ -+/* Timer/Counter Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(8) -+#define TIMER1_COMPB_vect_num 8 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(9) -+#define TIMER1_OVF_vect_num 9 -+ -+/* Timer/Counter0 Compare Match */ -+#define TIMER0_COMP_vect _VECTOR(10) -+#define TIMER0_COMP_vect_num 10 -+ -+/* Timer/Counter0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(11) -+#define TIMER0_OVF_vect_num 11 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(12) -+#define SPI_STC_vect_num 12 -+ -+/* USART, Rx Complete */ -+#define USART_RX_vect _VECTOR(13) -+#define USART_RX_vect_num 13 -+ -+/* USART Data register Empty */ -+#define USART_UDRE_vect _VECTOR(14) -+#define USART_UDRE_vect_num 14 -+ -+/* USART0, Tx Complete */ -+#define USART0_TX_vect _VECTOR(15) -+#define USART0_TX_vect_num 15 -+ -+/* USI Start Condition */ -+#define USI_START_vect _VECTOR(16) -+#define USI_START_vect_num 16 -+ -+/* USI Overflow */ -+#define USI_OVERFLOW_vect _VECTOR(17) -+#define USI_OVERFLOW_vect_num 17 -+ -+/* Analog Comparator */ -+#define ANALOG_COMP_vect _VECTOR(18) -+#define ANALOG_COMP_vect_num 18 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(19) -+#define ADC_vect_num 19 -+ -+/* EEPROM Ready */ -+#define EE_READY_vect _VECTOR(20) -+#define EE_READY_vect_num 20 -+ -+/* Store Program Memory Read */ -+#define SPM_READY_vect _VECTOR(21) -+#define SPM_READY_vect_num 21 -+ -+/* LCD Start of Frame */ -+#define LCD_vect _VECTOR(22) -+#define LCD_vect_num 22 -+ -+/* Pin Change Interrupt Request 2 */ -+#define PCINT2_vect _VECTOR(23) -+#define PCINT2_vect_num 23 -+ -+/* Pin Change Interrupt Request 3 */ -+#define PCINT3_vect _VECTOR(24) -+#define PCINT3_vect_num 24 -+ -+#define _VECTORS_SIZE 100 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 128 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x7FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 2048 -+#define RAMEND 0x08FF -+#define E2START 0 -+#define E2SIZE 1024 -+#define E2PAGESIZE 4 -+#define E2END 0x03FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -+#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_JTAGEN (unsigned char)~_BV(6) -+#define FUSE_OCDEN (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x95 -+#define SIGNATURE_2 0x0C -+ -+ -+#endif /* #ifdef _AVR_ATMEGA3290PA_H_INCLUDED */ -+ -diff --git a/include/avr/iom329a.h b/include/avr/iom329a.h -new file mode 100644 -index 0000000..cf66083 ---- /dev/null -+++ b/include/avr/iom329a.h -@@ -0,0 +1,34 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2011 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+#include "iom329.h" -diff --git a/include/avr/iom329p.h b/include/avr/iom329p.h -new file mode 100644 -index 0000000..f456b09 ---- /dev/null -+++ b/include/avr/iom329p.h -@@ -0,0 +1,1035 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATMEGA329P_H_INCLUDED -+#define _AVR_ATMEGA329P_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iom329p.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINA _SFR_IO8(0x00) -+#define PINA7 7 -+#define PINA6 6 -+#define PINA5 5 -+#define PINA4 4 -+#define PINA3 3 -+#define PINA2 2 -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x01) -+#define DDRA7 7 -+#define DDRA6 6 -+#define DDRA5 5 -+#define DDRA4 4 -+#define DDRA3 3 -+#define DDRA2 2 -+#define DDRA1 1 -+#define DDRA0 0 -+ -+#define PORTA _SFR_IO8(0x02) -+#define PORTA7 7 -+#define PORTA6 6 -+#define PORTA5 5 -+#define PORTA4 4 -+#define PORTA3 3 -+#define PORTA2 2 -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x06) -+#define PINC7 7 -+#define PINC6 6 -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x07) -+#define DDRC7 7 -+#define DDRC6 6 -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x08) -+#define PORTC7 7 -+#define PORTC6 6 -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PIND _SFR_IO8(0x09) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0A) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x0B) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+#define PINE _SFR_IO8(0x0C) -+#define PINE7 7 -+#define PINE6 6 -+#define PINE5 5 -+#define PINE4 4 -+#define PINE3 3 -+#define PINE2 2 -+#define PINE1 1 -+#define PINE0 0 -+ -+#define DDRE _SFR_IO8(0x0D) -+#define DDRE7 7 -+#define DDRE6 6 -+#define DDRE5 5 -+#define DDRE4 4 -+#define DDRE3 3 -+#define DDRE2 2 -+#define DDRE1 1 -+#define DDRE0 0 -+ -+#define PORTE _SFR_IO8(0x0E) -+#define PORTE7 7 -+#define PORTE6 6 -+#define PORTE5 5 -+#define PORTE4 4 -+#define PORTE3 3 -+#define PORTE2 2 -+#define PORTE1 1 -+#define PORTE0 0 -+ -+#define PINF _SFR_IO8(0x0F) -+#define PINF7 7 -+#define PINF6 6 -+#define PINF5 5 -+#define PINF4 4 -+#define PINF3 3 -+#define PINF2 2 -+#define PINF1 1 -+#define PINF0 0 -+ -+#define DDRF _SFR_IO8(0x10) -+#define DDRF7 7 -+#define DDRF6 6 -+#define DDRF5 5 -+#define DDRF4 4 -+#define DDRF3 3 -+#define DDRF2 2 -+#define DDRF1 1 -+#define DDRF0 0 -+ -+#define PORTF _SFR_IO8(0x11) -+#define PORTF7 7 -+#define PORTF6 6 -+#define PORTF5 5 -+#define PORTF4 4 -+#define PORTF3 3 -+#define PORTF2 2 -+#define PORTF1 1 -+#define PORTF0 0 -+ -+#define PING _SFR_IO8(0x12) -+#define PING5 5 -+#define PING4 4 -+#define PING3 3 -+#define PING2 2 -+#define PING1 1 -+#define PING0 0 -+ -+#define DDRG _SFR_IO8(0x13) -+#define DDRG4 4 -+#define DDRG3 3 -+#define DDRG2 2 -+#define DDRG1 1 -+#define DDRG0 0 -+ -+#define PORTG _SFR_IO8(0x14) -+#define PORTG4 4 -+#define PORTG3 3 -+#define PORTG2 2 -+#define PORTG1 1 -+#define PORTG0 0 -+ -+#define TIFR0 _SFR_IO8(0x15) -+#define TOV0 0 -+#define OCF0A 1 -+ -+#define TIFR1 _SFR_IO8(0x16) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define ICF1 5 -+ -+#define TIFR2 _SFR_IO8(0x17) -+#define TOV2 0 -+#define OCF2A 1 -+ -+/* Reserved [0x18..0x1B] */ -+ -+#define EIFR _SFR_IO8(0x1C) -+#define INTF0 0 -+#define PCIF0 4 -+#define PCIF1 5 -+#define PCIF2 6 -+#define PCIF3 7 -+ -+#define EIMSK _SFR_IO8(0x1D) -+#define INT0 0 -+#define PCIE0 4 -+#define PCIE1 5 -+#define PCIE2 6 -+#define PCIE3 7 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEWE 1 -+#define EEMWE 2 -+#define EERIE 3 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSR310 0 -+#define TSM 7 -+#define PSR2 1 -+ -+#define TCCR0A _SFR_IO8(0x24) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define WGM01 3 -+#define COM0A0 4 -+#define COM0A1 5 -+#define WGM00 6 -+#define FOC0A 7 -+ -+/* Reserved [0x25] */ -+ -+#define TCNT0 _SFR_IO8(0x26) -+ -+#define OCR0A _SFR_IO8(0x27) -+ -+/* Reserved [0x28..0x29] */ -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+/* Reserved [0x2F] */ -+ -+#define ACSR _SFR_IO8(0x30) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACBG 6 -+#define ACD 7 -+ -+#define OCDR _SFR_IO8(0x31) -+#define OCDR7 7 -+#define OCDR6 6 -+#define OCDR5 5 -+#define OCDR4 4 -+#define OCDR3 3 -+#define OCDR2 2 -+#define OCDR1 1 -+#define OCDR0 0 -+ -+/* Reserved [0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define JTRF 4 -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define JTD 7 -+#define IVCE 0 -+#define IVSEL 1 -+#define PUD 4 -+#define BODSE 5 -+#define BODS 6 -+ -+/* Reserved [0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+/* Reserved [0x38..0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCR _SFR_MEM8(0x60) -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDE 3 -+#define WDCE 4 -+ -+#define CLKPR _SFR_MEM8(0x61) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+#define CLKPCE 7 -+ -+/* Reserved [0x62..0x63] */ -+ -+#define PRR _SFR_MEM8(0x64) -+#define PRADC 0 -+#define PRUSART0 1 -+#define PRSPI 2 -+#define PRTIM1 3 -+#define PRLCD 4 -+ -+/* Reserved [0x65] */ -+ -+#define OSCCAL _SFR_MEM8(0x66) -+#define OSCCAL0 0 -+#define OSCCAL1 1 -+#define OSCCAL2 2 -+#define OSCCAL3 3 -+#define OSCCAL4 4 -+#define OSCCAL5 5 -+#define OSCCAL6 6 -+#define OSCCAL7 7 -+ -+/* Reserved [0x67..0x68] */ -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+ -+/* Reserved [0x6A] */ -+ -+#define PCMSK0 _SFR_MEM8(0x6B) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6C) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+#define PCINT14 6 -+#define PCINT15 7 -+ -+/* Reserved [0x6D] */ -+ -+#define TIMSK0 _SFR_MEM8(0x6E) -+#define TOIE0 0 -+#define OCIE0A 1 -+ -+#define TIMSK1 _SFR_MEM8(0x6F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define ICIE1 5 -+ -+#define TIMSK2 _SFR_MEM8(0x70) -+#define TOIE2 0 -+#define OCIE2A 1 -+ -+/* Reserved [0x71..0x77] */ -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_MEM16(0x78) -+#endif -+#define ADCW _SFR_MEM16(0x78) -+ -+#define ADCL _SFR_MEM8(0x78) -+#define ADCH _SFR_MEM8(0x79) -+ -+#define ADCSRA _SFR_MEM8(0x7A) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADCSRB _SFR_MEM8(0x7B) -+#define ACME 6 -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+ -+#define ADMUX _SFR_MEM8(0x7C) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define MUX4 4 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+/* Reserved [0x7D] */ -+ -+#define DIDR0 _SFR_MEM8(0x7E) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+#define ADC6D 6 -+#define ADC7D 7 -+ -+#define DIDR1 _SFR_MEM8(0x7F) -+#define AIN0D 0 -+#define AIN1D 1 -+ -+#define TCCR1A _SFR_MEM8(0x80) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR1B _SFR_MEM8(0x81) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1C _SFR_MEM8(0x82) -+#define FOC1B 6 -+#define FOC1A 7 -+ -+/* Reserved [0x83] */ -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x84) -+ -+#define TCNT1L _SFR_MEM8(0x84) -+#define TCNT1H _SFR_MEM8(0x85) -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x86) -+ -+#define ICR1L _SFR_MEM8(0x86) -+#define ICR1H _SFR_MEM8(0x87) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_MEM16(0x88) -+ -+#define OCR1AL _SFR_MEM8(0x88) -+#define OCR1AH _SFR_MEM8(0x89) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_MEM16(0x8A) -+ -+#define OCR1BL _SFR_MEM8(0x8A) -+#define OCR1BH _SFR_MEM8(0x8B) -+ -+/* Reserved [0x8C..0xAF] */ -+ -+#define TCCR2A _SFR_MEM8(0xB0) -+#define CS20 0 -+#define CS21 1 -+#define CS22 2 -+#define WGM21 3 -+#define COM2A0 4 -+#define COM2A1 5 -+#define WGM20 6 -+#define FOC2A 7 -+ -+/* Reserved [0xB1] */ -+ -+#define TCNT2 _SFR_MEM8(0xB2) -+ -+#define OCR2A _SFR_MEM8(0xB3) -+ -+/* Reserved [0xB4..0xB5] */ -+ -+#define ASSR _SFR_MEM8(0xB6) -+#define TCR2UB 0 -+#define OCR2UB 1 -+#define TCN2UB 2 -+#define AS2 3 -+#define EXCLK 4 -+ -+/* Reserved [0xB7] */ -+ -+#define USICR _SFR_MEM8(0xB8) -+#define USITC 0 -+#define USICLK 1 -+#define USICS0 2 -+#define USICS1 3 -+#define USIWM0 4 -+#define USIWM1 5 -+#define USIOIE 6 -+#define USISIE 7 -+ -+#define USISR _SFR_MEM8(0xB9) -+#define USICNT0 0 -+#define USICNT1 1 -+#define USICNT2 2 -+#define USICNT3 3 -+#define USIDC 4 -+#define USIPF 5 -+#define USIOIF 6 -+#define USISIF 7 -+ -+#define USIDR _SFR_MEM8(0xBA) -+ -+/* Reserved [0xBB..0xBF] */ -+ -+#define UCSR0A _SFR_MEM8(0xC0) -+#define MPCM0 0 -+#define U2X0 1 -+#define UPE0 2 -+#define DOR0 3 -+#define FE0 4 -+#define UDRE0 5 -+#define TXC0 6 -+#define RXC0 7 -+ -+#define UCSR0B _SFR_MEM8(0xC1) -+#define TXB80 0 -+#define RXB80 1 -+#define UCSZ02 2 -+#define TXEN0 3 -+#define RXEN0 4 -+#define UDRIE0 5 -+#define TXCIE0 6 -+#define RXCIE0 7 -+ -+#define UCSR0C _SFR_MEM8(0xC2) -+#define UCPOL0 0 -+#define UCSZ00 1 -+#define UCSZ01 2 -+#define USBS0 3 -+#define UPM00 4 -+#define UPM01 5 -+#define UMSEL0 6 -+ -+/* Reserved [0xC3] */ -+ -+/* Combine UBRR0L and UBRR0H */ -+#define UBRR0 _SFR_MEM16(0xC4) -+ -+#define UBRR0L _SFR_MEM8(0xC4) -+#define UBRR0H _SFR_MEM8(0xC5) -+ -+#define UDR0 _SFR_MEM8(0xC6) -+ -+/* Reserved [0xC7..0xE3] */ -+ -+#define LCDCRA _SFR_MEM8(0xE4) -+#define LCDBL 0 -+#define LCDCCD 1 -+#define LCDBD 2 -+#define LCDIE 3 -+#define LCDIF 4 -+#define LCDAB 6 -+#define LCDEN 7 -+ -+#define LCDCRB _SFR_MEM8(0xE5) -+#define LCDPM0 0 -+#define LCDPM1 1 -+#define LCDPM2 2 -+#define LCDPM3 3 -+#define LCDMUX0 4 -+#define LCDMUX1 5 -+#define LCD2B 6 -+#define LCDCS 7 -+ -+#define LCDFRR _SFR_MEM8(0xE6) -+#define LCDCD0 0 -+#define LCDCD1 1 -+#define LCDCD2 2 -+#define LCDPS0 4 -+#define LCDPS1 5 -+#define LCDPS2 6 -+ -+#define LCDCCR _SFR_MEM8(0xE7) -+#define LCDCC0 0 -+#define LCDCC1 1 -+#define LCDCC2 2 -+#define LCDCC3 3 -+#define LCDMDT 4 -+#define LCDDC0 5 -+#define LCDDC1 6 -+#define LCDDC2 7 -+ -+/* Reserved [0xE8..0xEB] */ -+ -+#define LCDDR0 _SFR_MEM8(0xEC) -+#define SEG000 0 -+#define SEG001 1 -+#define SEG002 2 -+#define SEG003 3 -+#define SEG004 4 -+#define SEG005 5 -+#define SEG006 6 -+#define SEG007 7 -+ -+#define LCDDR1 _SFR_MEM8(0xED) -+#define SEG008 0 -+#define SEG009 1 -+#define SEG010 2 -+#define SEG011 3 -+#define SEG012 4 -+#define SEG013 5 -+#define SEG014 6 -+#define SEG015 7 -+ -+#define LCDDR2 _SFR_MEM8(0xEE) -+#define SEG016 0 -+#define SEG017 1 -+#define SEG018 2 -+#define SEG019 3 -+#define SEG020 4 -+#define SEG021 5 -+#define SEG022 6 -+#define SEG023 7 -+ -+#define LCDDR3 _SFR_MEM8(0xEF) -+#define SEG024 0 -+#define SEG025 1 -+#define SEG026 2 -+#define SEG027 3 -+#define SEG028 4 -+#define SEG029 5 -+#define SEG030 6 -+#define SEG031 7 -+ -+/* Reserved [0xF0] */ -+ -+#define LCDDR5 _SFR_MEM8(0xF1) -+#define SEG100 0 -+#define SEG101 1 -+#define SEG102 2 -+#define SEG103 3 -+#define SEG104 4 -+#define SEG105 5 -+#define SEG106 6 -+#define SEG107 7 -+ -+#define LCDDR6 _SFR_MEM8(0xF2) -+#define SEG108 0 -+#define SEG109 1 -+#define SEG110 2 -+#define SEG111 3 -+#define SEG112 4 -+#define SEG113 5 -+#define SEG114 6 -+#define SEG115 7 -+ -+#define LCDDR7 _SFR_MEM8(0xF3) -+#define SEG116 0 -+#define SEG117 1 -+#define SEG118 2 -+#define SEG119 3 -+#define SEG120 4 -+#define SEG121 5 -+#define SEG122 6 -+#define SEG123 7 -+ -+#define LCDDR8 _SFR_MEM8(0xF4) -+#define SEG124 0 -+#define SEG125 1 -+#define SEG126 2 -+#define SEG127 3 -+#define SEG128 4 -+#define SEG129 5 -+#define SEG130 6 -+#define SEG131 7 -+ -+/* Reserved [0xF5] */ -+ -+#define LCDDR10 _SFR_MEM8(0xF6) -+#define SEG200 0 -+#define SEG201 1 -+#define SEG202 2 -+#define SEG203 3 -+#define SEG204 4 -+#define SEG205 5 -+#define SEG206 6 -+#define SEG207 7 -+ -+#define LCDDR11 _SFR_MEM8(0xF7) -+#define SEG208 0 -+#define SEG209 1 -+#define SEG210 2 -+#define SEG211 3 -+#define SEG212 4 -+#define SEG213 5 -+#define SEG214 6 -+#define SEG215 7 -+ -+#define LCDDR12 _SFR_MEM8(0xF8) -+#define SEG216 0 -+#define SEG217 1 -+#define SEG218 2 -+#define SEG219 3 -+#define SEG220 4 -+#define SEG221 5 -+#define SEG222 6 -+#define SEG223 7 -+ -+#define LCDDR13 _SFR_MEM8(0xF9) -+#define SEG224 0 -+#define SEG225 1 -+#define SEG226 2 -+#define SEG227 3 -+#define SEG228 4 -+#define SEG229 5 -+#define SEG230 6 -+#define SEG231 7 -+ -+/* Reserved [0xFA] */ -+ -+#define LCDDR15 _SFR_MEM8(0xFB) -+#define SEG300 0 -+#define SEG301 1 -+#define SEG302 2 -+#define SEG304 4 -+#define SEG305 5 -+#define SEG306 6 -+#define SEG307 7 -+ -+#define LCDDR16 _SFR_MEM8(0xFC) -+#define SEG308 0 -+#define SEG309 1 -+#define SEG310 2 -+#define SEG311 3 -+#define SEG312 4 -+#define SEG313 5 -+#define SEG314 6 -+#define SEG315 7 -+ -+#define LCDDR17 _SFR_MEM8(0xFD) -+#define SEG316 0 -+#define SEG317 1 -+#define SEG318 2 -+#define SEG319 3 -+#define SEG320 4 -+#define SEG321 5 -+#define SEG322 6 -+#define SEG323 7 -+ -+#define LCDDR18 _SFR_MEM8(0xFE) -+#define SEG324 0 -+#define SEG325 1 -+#define SEG326 2 -+#define SEG327 3 -+#define SEG328 4 -+#define SEG329 5 -+#define SEG330 6 -+#define SEG331 7 -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(2) -+#define PCINT0_vect_num 2 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(3) -+#define PCINT1_vect_num 3 -+ -+/* Timer/Counter2 Compare Match */ -+#define TIMER2_COMP_vect _VECTOR(4) -+#define TIMER2_COMP_vect_num 4 -+ -+/* Timer/Counter2 Overflow */ -+#define TIMER2_OVF_vect _VECTOR(5) -+#define TIMER2_OVF_vect_num 5 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(6) -+#define TIMER1_CAPT_vect_num 6 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(7) -+#define TIMER1_COMPA_vect_num 7 -+ -+/* Timer/Counter Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(8) -+#define TIMER1_COMPB_vect_num 8 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(9) -+#define TIMER1_OVF_vect_num 9 -+ -+/* Timer/Counter0 Compare Match */ -+#define TIMER0_COMP_vect _VECTOR(10) -+#define TIMER0_COMP_vect_num 10 -+ -+/* Timer/Counter0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(11) -+#define TIMER0_OVF_vect_num 11 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(12) -+#define SPI_STC_vect_num 12 -+ -+/* USART0, Rx Complete */ -+#define USART0_RX_vect _VECTOR(13) -+#define USART0_RX_vect_num 13 -+ -+/* USART0 Data register Empty */ -+#define USART0_UDRE_vect _VECTOR(14) -+#define USART0_UDRE_vect_num 14 -+ -+/* USART0, Tx Complete */ -+#define USART0_TX_vect _VECTOR(15) -+#define USART0_TX_vect_num 15 -+ -+/* USI Start Condition */ -+#define USI_START_vect _VECTOR(16) -+#define USI_START_vect_num 16 -+ -+/* USI Overflow */ -+#define USI_OVERFLOW_vect _VECTOR(17) -+#define USI_OVERFLOW_vect_num 17 -+ -+/* Analog Comparator */ -+#define ANALOG_COMP_vect _VECTOR(18) -+#define ANALOG_COMP_vect_num 18 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(19) -+#define ADC_vect_num 19 -+ -+/* EEPROM Ready */ -+#define EE_READY_vect _VECTOR(20) -+#define EE_READY_vect_num 20 -+ -+/* Store Program Memory Read */ -+#define SPM_READY_vect _VECTOR(21) -+#define SPM_READY_vect_num 21 -+ -+/* LCD Start of Frame */ -+#define LCD_vect _VECTOR(22) -+#define LCD_vect_num 22 -+ -+#define _VECTORS_SIZE 92 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 128 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x7FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 2048 -+#define RAMEND 0x08FF -+#define E2START 0 -+#define E2SIZE 1024 -+#define E2PAGESIZE 4 -+#define E2END 0x03FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -+#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_JTAGEN (unsigned char)~_BV(6) -+#define FUSE_OCDEN (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x95 -+#define SIGNATURE_2 0x0B -+ -+ -+#endif /* #ifdef _AVR_ATMEGA329P_H_INCLUDED */ -+ -diff --git a/include/avr/iom329pa.h b/include/avr/iom329pa.h -new file mode 100644 -index 0000000..cf66083 ---- /dev/null -+++ b/include/avr/iom329pa.h -@@ -0,0 +1,34 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2011 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+#include "iom329.h" -diff --git a/include/avr/iom32a.h b/include/avr/iom32a.h -new file mode 100644 -index 0000000..be69994 ---- /dev/null -+++ b/include/avr/iom32a.h -@@ -0,0 +1,608 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATMEGA32A_H_INCLUDED -+#define _AVR_ATMEGA32A_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iom32a.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define TWBR _SFR_IO8(0x00) -+ -+#define TWSR _SFR_IO8(0x01) -+#define TWPS0 0 -+#define TWPS1 1 -+#define TWS3 3 -+#define TWS4 4 -+#define TWS5 5 -+#define TWS6 6 -+#define TWS7 7 -+ -+#define TWAR _SFR_IO8(0x02) -+ -+#define TWDR _SFR_IO8(0x03) -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_IO16(0x04) -+#endif -+#define ADCW _SFR_IO16(0x04) -+ -+#define ADCL _SFR_IO8(0x04) -+#define ADCH _SFR_IO8(0x05) -+ -+#define ADCSRA _SFR_IO8(0x06) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADMUX _SFR_IO8(0x07) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define MUX4 4 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+#define ACSR _SFR_IO8(0x08) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACBG 6 -+#define ACD 7 -+ -+#define UBRRL _SFR_IO8(0x09) -+ -+#define UCSRB _SFR_IO8(0x0A) -+#define TXB8 0 -+#define RXB8 1 -+#define UCSZ2 2 -+#define TXEN 3 -+#define RXEN 4 -+#define UDRIE 5 -+#define TXCIE 6 -+#define RXCIE 7 -+ -+#define UCSRA _SFR_IO8(0x0B) -+#define MPCM 0 -+#define U2X 1 -+#define UPE 2 -+#define DOR 3 -+#define FE 4 -+#define UDRE 5 -+#define TXC 6 -+#define RXC 7 -+ -+#define UDR _SFR_IO8(0x0C) -+ -+#define SPCR _SFR_IO8(0x0D) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x0E) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x0F) -+ -+#define PIND _SFR_IO8(0x10) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x11) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x12) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+#define PINC _SFR_IO8(0x13) -+#define PINC7 7 -+#define PINC6 6 -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x14) -+#define DDRC7 7 -+#define DDRC6 6 -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x15) -+#define PORTC7 7 -+#define PORTC6 6 -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PINB _SFR_IO8(0x16) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x17) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x18) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINA _SFR_IO8(0x19) -+#define PINA7 7 -+#define PINA6 6 -+#define PINA5 5 -+#define PINA4 4 -+#define PINA3 3 -+#define PINA2 2 -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x1A) -+#define DDRA7 7 -+#define DDRA6 6 -+#define DDRA5 5 -+#define DDRA4 4 -+#define DDRA3 3 -+#define DDRA2 2 -+#define DDRA1 1 -+#define DDRA0 0 -+ -+#define PORTA _SFR_IO8(0x1B) -+#define PORTA7 7 -+#define PORTA6 6 -+#define PORTA5 5 -+#define PORTA4 4 -+#define PORTA3 3 -+#define PORTA2 2 -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define EECR _SFR_IO8(0x1C) -+#define EERE 0 -+#define EEWE 1 -+#define EEMWE 2 -+#define EERIE 3 -+ -+#define EEDR _SFR_IO8(0x1D) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x1E) -+ -+#define EEARL _SFR_IO8(0x1E) -+#define EEARH _SFR_IO8(0x1F) -+ -+#define UCSRC _SFR_IO8(0x20) -+#define UCPOL 0 -+#define UCSZ0 1 -+#define UCSZ1 2 -+#define USBS 3 -+#define UPM0 4 -+#define UPM1 5 -+#define UMSEL 6 -+#define URSEL 7 -+ -+#define UBRRH _SFR_IO8(0x20) -+ -+#define WDTCR _SFR_IO8(0x21) -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDE 3 -+#define WDTOE 4 -+ -+#define ASSR _SFR_IO8(0x22) -+#define TCR2UB 0 -+#define OCR2UB 1 -+#define TCN2UB 2 -+#define AS2 3 -+ -+#define OCR2 _SFR_IO8(0x23) -+ -+#define TCNT2 _SFR_IO8(0x24) -+ -+#define TCCR2 _SFR_IO8(0x25) -+#define CS20 0 -+#define CS21 1 -+#define CS22 2 -+#define WGM21 3 -+#define COM20 4 -+#define COM21 5 -+#define WGM20 6 -+#define FOC2 7 -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_IO16(0x26) -+ -+#define ICR1L _SFR_IO8(0x26) -+#define ICR1H _SFR_IO8(0x27) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_IO16(0x28) -+ -+#define OCR1BL _SFR_IO8(0x28) -+#define OCR1BH _SFR_IO8(0x29) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_IO16(0x2A) -+ -+#define OCR1AL _SFR_IO8(0x2A) -+#define OCR1AH _SFR_IO8(0x2B) -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_IO16(0x2C) -+ -+#define TCNT1L _SFR_IO8(0x2C) -+#define TCNT1H _SFR_IO8(0x2D) -+ -+#define TCCR1B _SFR_IO8(0x2E) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1A _SFR_IO8(0x2F) -+#define WGM10 0 -+#define WGM11 1 -+#define FOC1B 2 -+#define FOC1A 3 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define SFIOR _SFR_IO8(0x30) -+#define PSR2 0 -+#define PSR10 0 -+#define PUD 2 -+#define ACME 3 -+#define ADTS0 5 -+#define ADTS1 6 -+#define ADTS2 7 -+ -+#define OSCCAL _SFR_IO8(0x31) -+#define OSCCAL0 0 -+#define OSCCAL1 1 -+#define OSCCAL2 2 -+#define OSCCAL3 3 -+#define OSCCAL4 4 -+#define OSCCAL5 5 -+#define OSCCAL6 6 -+#define OSCCAL7 7 -+ -+#define TCNT0 _SFR_IO8(0x32) -+ -+#define TCCR0 _SFR_IO8(0x33) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define WGM01 3 -+#define COM00 4 -+#define COM01 5 -+#define WGM00 6 -+#define FOC0 7 -+ -+#define MCUCSR _SFR_IO8(0x34) -+#define ISC2 6 -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+#define JTRF 4 -+#define JTD 7 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+#define SM0 4 -+#define SM1 5 -+#define SM2 6 -+#define SE 7 -+ -+#define TWCR _SFR_IO8(0x36) -+#define TWIE 0 -+#define TWEN 2 -+#define TWWC 3 -+#define TWSTO 4 -+#define TWSTA 5 -+#define TWEA 6 -+#define TWINT 7 -+ -+#define SPMCR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+#define TIFR _SFR_IO8(0x38) -+#define TOV0 0 -+#define OCF0 1 -+#define TOV2 6 -+#define OCF2 7 -+#define TOV1 2 -+#define OCF1B 3 -+#define OCF1A 4 -+#define ICF1 5 -+ -+#define TIMSK _SFR_IO8(0x39) -+#define TOIE0 0 -+#define OCIE0 1 -+#define TOIE2 6 -+#define OCIE2 7 -+#define TOIE1 2 -+#define OCIE1B 3 -+#define OCIE1A 4 -+#define TICIE1 5 -+ -+#define GIFR _SFR_IO8(0x3A) -+#define INTF2 5 -+#define INTF0 6 -+#define INTF1 7 -+ -+#define GICR _SFR_IO8(0x3B) -+#define IVCE 0 -+#define IVSEL 1 -+#define INT2 5 -+#define INT0 6 -+#define INT1 7 -+ -+#define OCR0 _SFR_IO8(0x3C) -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* External Interrupt Request 2 */ -+#define INT2_vect _VECTOR(3) -+#define INT2_vect_num 3 -+ -+/* Timer/Counter2 Compare Match */ -+#define TIMER2_COMP_vect _VECTOR(4) -+#define TIMER2_COMP_vect_num 4 -+ -+/* Timer/Counter2 Overflow */ -+#define TIMER2_OVF_vect _VECTOR(5) -+#define TIMER2_OVF_vect_num 5 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(6) -+#define TIMER1_CAPT_vect_num 6 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(7) -+#define TIMER1_COMPA_vect_num 7 -+ -+/* Timer/Counter1 Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(8) -+#define TIMER1_COMPB_vect_num 8 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(9) -+#define TIMER1_OVF_vect_num 9 -+ -+/* Timer/Counter0 Compare Match */ -+#define TIMER0_COMP_vect _VECTOR(10) -+#define TIMER0_COMP_vect_num 10 -+ -+/* Timer/Counter0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(11) -+#define TIMER0_OVF_vect_num 11 -+ -+/* Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(12) -+#define SPI_STC_vect_num 12 -+ -+/* USART, Rx Complete */ -+#define USART_RXC_vect _VECTOR(13) -+#define USART_RXC_vect_num 13 -+ -+/* USART Data Register Empty */ -+#define USART_UDRE_vect _VECTOR(14) -+#define USART_UDRE_vect_num 14 -+ -+/* USART, Tx Complete */ -+#define USART_TXC_vect _VECTOR(15) -+#define USART_TXC_vect_num 15 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(16) -+#define ADC_vect_num 16 -+ -+/* EEPROM Ready */ -+#define EE_RDY_vect _VECTOR(17) -+#define EE_RDY_vect_num 17 -+ -+/* Analog Comparator */ -+#define ANA_COMP_vect _VECTOR(18) -+#define ANA_COMP_vect_num 18 -+ -+/* 2-wire Serial Interface */ -+#define TWI_vect _VECTOR(19) -+#define TWI_vect_num 19 -+ -+/* Store Program Memory Ready */ -+#define SPM_RDY_vect _VECTOR(20) -+#define SPM_RDY_vect_num 20 -+ -+#define _VECTORS_SIZE 84 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 128 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x7FFF -+#define RAMSTART 0x0060 -+#define RAMSIZE 2048 -+#define RAMEND 0x085F -+#define E2START 0 -+#define E2SIZE 1024 -+#define E2PAGESIZE 4 -+#define E2END 0x03FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 2 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -+#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -+#define FUSE_BODEN (unsigned char)~_BV(6) -+#define FUSE_BODLEVEL (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_CKOPT (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_JTAGEN (unsigned char)~_BV(6) -+#define FUSE_OCDEN (unsigned char)~_BV(7) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x95 -+#define SIGNATURE_2 0x02 -+ -+ -+#endif /* #ifdef _AVR_ATMEGA32A_H_INCLUDED */ -+ -diff --git a/include/avr/iom32hvb.h b/include/avr/iom32hvb.h -index c63c4f0..6fa81f8 100644 ---- a/include/avr/iom32hvb.h -+++ b/include/avr/iom32hvb.h -@@ -970,10 +970,10 @@ - #define VREF_PIN PINVREF - #define VREF_BIT VREF - --#define VREF_DDR DDRVREFGND --#define VREF_PORT PORTVREFGND --#define VREF_PIN PINVREFGND --#define VREF_BIT VREFGND -+#define VREFGND_DDR DDRVREFGND -+#define VREFGND_PORT PORTVREFGND -+#define VREFGND_PIN PINVREFGND -+#define VREFGND_BIT VREFGND - - #define PI_DDR DDRI - #define PI_PORT PORTI -diff --git a/include/avr/iom32u2.h b/include/avr/iom32u2.h -index 249c3f0..56260bf 100644 ---- a/include/avr/iom32u2.h -+++ b/include/avr/iom32u2.h -@@ -474,6 +474,12 @@ - #define DIDR1 _SFR_MEM8(0x7F) - #define AIN0D 0 - #define AIN1D 1 -+#define AIN2D 2 -+#define AIN3D 3 -+#define AIN4D 4 -+#define AIN5D 5 -+#define AIN6D 6 -+#define AIN7D 7 - - #define TCCR1A _SFR_MEM8(0x80) - #define WGM10 0 -diff --git a/include/avr/iom32u4.h b/include/avr/iom32u4.h -index b73ccd7..8739387 100644 ---- a/include/avr/iom32u4.h -+++ b/include/avr/iom32u4.h -@@ -172,11 +172,6 @@ - #define OCF1C 3 - #define ICF1 5 - +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x93 +-#define SIGNATURE_2 0x83 +- +- +-#endif /* _AVR_IO90PWM2B_H_ */ ++/* Copyright (c) 2007 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++/* $Id: io90pwm2b.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* avr/io90pwm2b.h - definitions for AT90PWM2B */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "io90pwm2b.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_IO90PWM2B_H_ ++#define _AVR_IO90PWM2B_H_ 1 ++ ++/* Registers and associated bit numbers */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++#define PINC7 7 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++#define DDC7 7 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC3 3 ++#define PORTC4 4 ++#define PORTC5 5 ++#define PORTC6 6 ++#define PORTC7 7 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE0 0 ++#define PINE1 1 ++#define PINE2 2 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE0 0 ++#define DDE1 1 ++#define DDE2 2 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE0 0 ++#define PORTE1 1 ++#define PORTE2 2 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define GPIOR1 _SFR_IO8(0x19) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x1A) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define GPIOR3 _SFR_IO8(0x1B) ++#define GPIOR30 0 ++#define GPIOR31 1 ++#define GPIOR32 2 ++#define GPIOR33 3 ++#define GPIOR34 4 ++#define GPIOR35 5 ++#define GPIOR36 6 ++#define GPIOR37 7 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++#define INT3 3 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARL0 0 ++#define EEARL1 1 ++#define EEARL2 2 ++#define EEARL3 3 ++#define EEARL4 4 ++#define EEARL5 5 ++#define EEARL6 6 ++#define EEARL7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++#define EEAR9 1 ++#define EEAR10 2 ++#define EEAR11 3 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR10 0 ++#define PSRSYNC 0 ++#define ICPSEL1 2 ++#define TSM 3 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define OCR0A _SFR_IO8(0x27) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define OCR0B _SFR_IO8(0x28) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define OCR0_0 0 /* Deprecated */ ++#define OCR0_1 1 /* Deprecated */ ++#define OCR0_2 2 /* Deprecated */ ++#define OCR0_3 3 /* Deprecated */ ++#define OCR0_4 4 /* Deprecated */ ++#define OCR0_5 5 /* Deprecated */ ++#define OCR0_6 6 /* Deprecated */ ++#define OCR0_7 7 /* Deprecated */ ++ ++#define PLLCSR _SFR_IO8(0x29) ++#define PLOCK 0 ++#define PLLE 1 ++#define PLLF 2 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define ACSR _SFR_IO8(0x30) ++#define AC0O 0 ++#define AC1O 1 ++#define AC2O 2 ++#define AC0IF 4 ++#define AC1IF 5 ++#define AC2IF 6 ++#define ACCKDIV 7 ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define SPIPS 7 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM0 3 ++#define PRTIM1 4 ++#define PRPSC0 5 ++#define PRPSC1 6 ++#define PRPSC2 7 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define AMP0CSR _SFR_MEM8(0x76) ++#define AMP0TS0 0 ++#define AMP0TS1 1 ++#define AMP0G0 4 ++#define AMP0G1 5 ++#define AMP0IS 6 ++#define AMP0EN 7 ++ ++#define AMP1CSR _SFR_MEM8(0x77) ++#define AMP1TS0 0 ++#define AMP1TS1 1 ++#define AMP1G0 4 ++#define AMP1G1 5 ++#define AMP1IS 6 ++#define AMP1EN 7 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_MEM8(0x79) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ADTS3 3 ++#define ADASCR 4 ++#define ADHSM 7 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define ADC8D 0 ++#define ADC9D 1 ++#define ADC10D 2 ++#define AMP0ND 3 ++#define AMP0PD 4 ++#define ACMP0D 5 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define PIFR0 _SFR_MEM8(0xA0) ++#define PEOP0 0 ++#define PRN00 1 ++#define PRN01 2 ++#define PEV0A 3 ++#define PEV0B 4 ++#define PSEI0 5 ++#define POAC0A 6 ++#define POAC0B 7 ++ ++#define PIM0 _SFR_MEM8(0xA1) ++#define PEOPE0 0 ++#define PEVE0A 3 ++#define PEVE0B 4 ++#define PSEIE0 5 ++ ++#define PIFR1 _SFR_MEM8(0xA2) ++#define PEOP1 0 ++#define PRN10 1 ++#define PRN11 2 ++#define PEV1A 3 ++#define PEV1B 4 ++#define PSEI1 5 ++#define POAC1A 6 ++#define POAC1B 7 ++ ++#define PIM1 _SFR_MEM8(0xA3) ++#define PEOPE1 0 ++#define PEVE1A 3 ++#define PEVE1B 4 ++#define PSEIE1 5 ++ ++#define PIFR2 _SFR_MEM8(0xA4) ++#define PEOP2 0 ++#define PRN20 1 ++#define PRN21 2 ++#define PEV2A 3 ++#define PEV2B 4 ++#define PSEI2 5 ++#define POAC2A 6 ++#define POAC2B 7 ++ ++#define PIM2 _SFR_MEM8(0xA5) ++#define PEOPE2 0 ++#define PEVE2A 3 ++#define PEVE2B 4 ++#define PSEIE2 5 ++ ++#define DACON _SFR_MEM8(0xAA) ++#define DAEN 0 ++#define DAOE 1 ++#define DALA 2 ++#define DATS0 4 ++#define DATS1 5 ++#define DATS2 6 ++#define DAATE 7 ++ ++#define DAC _SFR_MEM16(0xAB) ++ ++#define DACL _SFR_MEM8(0xAB) ++#define DACL0 0 ++#define DACL1 1 ++#define DACL2 2 ++#define DACL3 3 ++#define DACL4 4 ++#define DACL5 5 ++#define DACL6 6 ++#define DACL7 7 ++ ++#define DACH _SFR_MEM8(0xAC) ++#define DACH0 0 ++#define DACH1 1 ++#define DACH2 2 ++#define DACH3 3 ++#define DACH4 4 ++#define DACH5 5 ++#define DACH6 6 ++#define DACH7 7 ++ ++#define AC0CON _SFR_MEM8(0xAD) ++#define AC0M0 0 ++#define AC0M1 1 ++#define AC0M2 2 ++#define AC0IS0 4 ++#define AC0IS1 5 ++#define AC0IE 6 ++#define AC0EN 7 ++ ++#define AC1CON _SFR_MEM8(0xAE) ++#define AC1M0 0 ++#define AC1M1 1 ++#define AC1M2 2 ++#define AC1ICE 3 ++#define AC1IS0 4 ++#define AC1IS1 5 ++#define AC1IE 6 ++#define AC1EN 7 ++ ++#define AC2CON _SFR_MEM8(0xAF) ++#define AC2M0 0 ++#define AC2M1 1 ++#define AC2M2 2 ++#define AC2IS0 4 ++#define AC2IS1 5 ++#define AC2IE 6 ++#define AC2EN 7 ++ ++#define UCSRA _SFR_MEM8(0xC0) ++#define MPCM 0 ++#define U2X 1 ++#define UPE 2 ++#define DOR 3 ++#define FE 4 ++#define UDRE 5 ++#define TXC 6 ++#define RXC 7 ++ ++#define UCSRB _SFR_MEM8(0xC1) ++#define TXB8 0 ++#define RXB8 1 ++#define UCSZ2 2 ++#define TXEN 3 ++#define RXEN 4 ++#define UDRIE 5 ++#define TXCIE 6 ++#define RXCIE 7 ++ ++#define UCSRC _SFR_MEM8(0xC2) ++#define UCPOL 0 ++#define UCSZ0 1 ++#define UCSZ1 2 ++#define USBS 3 ++#define UPM0 4 ++#define UPM1 5 ++#define UMSEL0 6 ++ ++#define UBRR _SFR_MEM16(0xC4) ++ ++#define UBRRL _SFR_MEM8(0xC4) ++#define UBRR0 0 ++#define UBRR1 1 ++#define UBRR2 2 ++#define UBRR3 3 ++#define UBRR4 4 ++#define UBRR5 5 ++#define UBRR6 6 ++#define UBRR7 7 ++ ++#define UBRRH _SFR_MEM8(0xC5) ++#define UBRR8 0 ++#define UBRR9 1 ++#define UBRR10 2 ++#define UBRR11 3 ++ ++#define UDR _SFR_MEM8(0xC6) ++#define UDR0 0 ++#define UDR1 1 ++#define UDR2 2 ++#define UDR3 3 ++#define UDR4 4 ++#define UDR5 5 ++#define UDR6 6 ++#define UDR7 7 ++ ++#define EUCSRA _SFR_MEM8(0xC8) ++#define URxS0 0 ++#define URxS1 1 ++#define URxS2 2 ++#define URxS3 3 ++#define UTxS0 4 ++#define UTxS1 5 ++#define UTxS2 6 ++#define UTxS3 7 ++ ++#define EUCSRB _SFR_MEM8(0xC9) ++#define BODR 0 ++#define EMCH 1 ++#define EUSBS 3 ++#define EUSART 4 ++ ++#define EUCSRC _SFR_MEM8(0xCA) ++#define STP0 0 ++#define STP1 1 ++#define F1617 2 ++#define FEM 3 ++ ++#define MUBRR _SFR_MEM16(0xCC) ++ ++#define MUBRRL _SFR_MEM8(0xCC) ++#define MUBRR0 0 ++#define MUBRR1 1 ++#define MUBRR2 2 ++#define MUBRR3 3 ++#define MUBRR4 4 ++#define MUBRR5 5 ++#define MUBRR6 6 ++#define MUBRR7 7 ++ ++#define MUBRRH _SFR_MEM8(0xCD) ++#define MUBRR8 0 ++#define MUBRR9 1 ++#define MUBRR10 2 ++#define MUBRR11 3 ++#define MUBRR12 4 ++#define MUBRR13 5 ++#define MUBRR14 6 ++#define MUBRR15 7 ++ ++#define EUDR _SFR_MEM8(0xCE) ++#define EUDR0 0 ++#define EUDR1 1 ++#define EUDR2 2 ++#define EUDR3 3 ++#define EUDR4 4 ++#define EUDR5 5 ++#define EUDR6 6 ++#define EUDR7 7 ++ ++#define PSOC0 _SFR_MEM8(0xD0) ++#define POEN0A 0 ++#define POEN0B 2 ++#define PSYNC00 4 ++#define PSYNC01 5 ++ ++#define OCR0SA _SFR_MEM16(0xD2) ++ ++#define OCR0SAL _SFR_MEM8(0xD2) ++#define OCR0SA_0 0 ++#define OCR0SA_1 1 ++#define OCR0SA_2 2 ++#define OCR0SA_3 3 ++#define OCR0SA_4 4 ++#define OCR0SA_5 5 ++#define OCR0SA_6 6 ++#define OCR0SA_7 7 ++ ++#define OCR0SAH _SFR_MEM8(0xD3) ++#define OCR0SA_8 0 ++#define OCR0SA_9 1 ++#define OCR0SA_00 2 ++#define OCR0SA_01 3 ++ ++#define OCR0RA _SFR_MEM16(0xD4) ++ ++#define OCR0RAL _SFR_MEM8(0xD4) ++#define OCR0RA_0 0 ++#define OCR0RA_1 1 ++#define OCR0RA_2 2 ++#define OCR0RA_3 3 ++#define OCR0RA_4 4 ++#define OCR0RA_5 5 ++#define OCR0RA_6 6 ++#define OCR0RA_7 7 ++ ++#define OCR0RAH _SFR_MEM8(0xD5) ++#define OCR0RA_8 0 ++#define OCR0RA_9 1 ++#define OCR0RA_00 2 ++#define OCR0RA_01 3 ++ ++#define OCR0SB _SFR_MEM16(0xD6) ++ ++#define OCR0SBL _SFR_MEM8(0xD6) ++#define OCR0SB_0 0 ++#define OCR0SB_1 1 ++#define OCR0SB_2 2 ++#define OCR0SB_3 3 ++#define OCR0SB_4 4 ++#define OCR0SB_5 5 ++#define OCR0SB_6 6 ++#define OCR0SB_7 7 ++ ++#define OCR0SBH _SFR_MEM8(0xD7) ++#define OCR0SB_8 0 ++#define OCR0SB_9 1 ++#define OCR0SB_00 2 ++#define OCR0SB_01 3 ++ ++#define OCR0RB _SFR_MEM16(0xD8) ++ ++#define OCR0RBL _SFR_MEM8(0xD8) ++#define OCR0RB_0 0 ++#define OCR0RB_1 1 ++#define OCR0RB_2 2 ++#define OCR0RB_3 3 ++#define OCR0RB_4 4 ++#define OCR0RB_5 5 ++#define OCR0RB_6 6 ++#define OCR0RB_7 7 ++ ++#define OCR0RBH _SFR_MEM8(0xD9) ++#define OCR0RB_8 0 ++#define OCR0RB_9 1 ++#define OCR0RB_00 2 ++#define OCR0RB_01 3 ++#define OCR0RB_02 4 ++#define OCR0RB_03 5 ++#define OCR0RB_04 6 ++#define OCR0RB_05 7 ++ ++#define PCNF0 _SFR_MEM8(0xDA) ++#define PCLKSEL0 1 ++#define POP0 2 ++#define PMODE00 3 ++#define PMODE01 4 ++#define PLOCK0 5 ++#define PALOCK0 6 ++#define PFIFTY0 7 ++ ++#define PCTL0 _SFR_MEM8(0xDB) ++#define PRUN0 0 ++#define PCCYC0 1 ++#define PARUN0 2 ++#define PAOC0A 3 ++#define PAOC0B 4 ++#define PBFM0 5 ++#define PPRE00 6 ++#define PPRE01 7 ++ ++#define PFRC0A _SFR_MEM8(0xDC) ++#define PRFM0A0 0 ++#define PRFM0A1 1 ++#define PRFM0A2 2 ++#define PRFM0A3 3 ++#define PFLTE0A 4 ++#define PELEV0A 5 ++#define PISEL0A 6 ++#define PCAE0A 7 ++ ++#define PFRC0B _SFR_MEM8(0xDD) ++#define PRFM0B0 0 ++#define PRFM0B1 1 ++#define PRFM0B2 2 ++#define PRFM0B3 3 ++#define PFLTE0B 4 ++#define PELEV0B 5 ++#define PISEL0B 6 ++#define PCAE0B 7 ++ ++#define PICR0 _SFR_MEM16(0xDE) ++ ++#define PICR0L _SFR_MEM8(0xDE) ++#define PICR0_0 0 ++#define PICR0_1 1 ++#define PICR0_2 2 ++#define PICR0_3 3 ++#define PICR0_4 4 ++#define PICR0_5 5 ++#define PICR0_6 6 ++#define PICR0_7 7 ++ ++#define PICR0H _SFR_MEM8(0xDF) ++#define PICR0_8 0 ++#define PICR0_9 1 ++#define PICR0_10 2 ++#define PICR0_11 3 ++#define PCST0 7 ++ ++#define PSOC1 _SFR_MEM8(0xE0) ++#define POEN1A 0 ++#define POEN1B 2 ++#define PSYNC1_0 4 ++#define PSYNC1_1 5 ++ ++#define OCR1SA _SFR_MEM16(0xE2) ++ ++#define OCR1SAL _SFR_MEM8(0xE2) ++#define OCR1SA_0 0 ++#define OCR1SA_1 1 ++#define OCR1SA_2 2 ++#define OCR1SA_3 3 ++#define OCR1SA_4 4 ++#define OCR1SA_5 5 ++#define OCR1SA_6 6 ++#define OCR1SA_7 7 ++ ++#define OCR1SAH _SFR_MEM8(0xE3) ++#define OCR1SA_8 0 ++#define OCR1SA_9 1 ++#define OCR1SA_10 2 ++#define OCR1SA_11 3 ++ ++#define OCR1RA _SFR_MEM16(0xE4) ++ ++#define OCR1RAL _SFR_MEM8(0xE4) ++#define OCR1RA_0 0 ++#define OCR1RA_1 1 ++#define OCR1RA_2 2 ++#define OCR1RA_3 3 ++#define OCR1RA_4 4 ++#define OCR1RA_5 5 ++#define OCR1RA_6 6 ++#define OCR1RA_7 7 ++ ++#define OCR1RAH _SFR_MEM8(0xE5) ++#define OCR1RA_8 0 ++#define OCR1RA_9 1 ++#define OCR1RA_10 2 ++#define OCR1RA_11 3 ++ ++#define OCR1SB _SFR_MEM16(0xE6) ++ ++#define OCR1SBL _SFR_MEM8(0xE6) ++#define OCR1SB_0 0 ++#define OCR1SB_1 1 ++#define OCR1SB_2 2 ++#define OCR1SB_3 3 ++#define OCR1SB_4 4 ++#define OCR1SB_5 5 ++#define OCR1SB_6 6 ++#define OCR1SB_7 7 ++ ++#define OCR1SBH _SFR_MEM8(0xE7) ++#define OCR1SB_8 0 ++#define OCR1SB_9 1 ++#define OCR1SB_10 2 ++#define OCR1SB_11 3 ++ ++#define OCR1RB _SFR_MEM16(0xE8) ++ ++#define OCR1RBL _SFR_MEM8(0xE8) ++#define OCR1RB_0 0 ++#define OCR1RB_1 1 ++#define OCR1RB_2 2 ++#define OCR1RB_3 3 ++#define OCR1RB_4 4 ++#define OCR1RB_5 5 ++#define OCR1RB_6 6 ++#define OCR1RB_7 7 ++ ++#define OCR1RBH _SFR_MEM8(0xE9) ++#define OCR1RB_8 0 ++#define OCR1RB_9 1 ++#define OCR1RB_10 2 ++#define OCR1RB_11 3 ++#define OCR1RB_12 4 ++#define OCR1RB_13 5 ++#define OCR1RB_14 6 ++#define OCR1RB_15 7 ++ ++#define PCNF1 _SFR_MEM8(0xEA) ++#define PCLKSEL1 1 ++#define POP1 2 ++#define PMODE10 3 ++#define PMODE11 4 ++#define PLOCK1 5 ++#define PALOCK1 6 ++#define PFIFTY1 7 ++ ++#define PCTL1 _SFR_MEM8(0xEB) ++#define PRUN1 0 ++#define PCCYC1 1 ++#define PARUN1 2 ++#define PAOC1A 3 ++#define PAOC1B 4 ++#define PBFM1 5 ++#define PPRE10 6 ++#define PPRE11 7 ++ ++#define PFRC1A _SFR_MEM8(0xEC) ++#define PRFM1A0 0 ++#define PRFM1A1 1 ++#define PRFM1A2 2 ++#define PRFM1A3 3 ++#define PFLTE1A 4 ++#define PELEV1A 5 ++#define PISEL1A 6 ++#define PCAE1A 7 ++ ++#define PFRC1B _SFR_MEM8(0xED) ++#define PRFM1B0 0 ++#define PRFM1B1 1 ++#define PRFM1B2 2 ++#define PRFM1B3 3 ++#define PFLTE1B 4 ++#define PELEV1B 5 ++#define PISEL1B 6 ++#define PCAE1B 7 ++ ++#define PICR1 _SFR_MEM16(0xEE) ++ ++#define PICR1L _SFR_MEM8(0xEE) ++#define PICR1_0 0 ++#define PICR1_1 1 ++#define PICR1_2 2 ++#define PICR1_3 3 ++#define PICR1_4 4 ++#define PICR1_5 5 ++#define PICR1_6 6 ++#define PICR1_7 7 ++ ++#define PICR1H _SFR_MEM8(0xEF) ++#define PICR1_8 0 ++#define PICR1_9 1 ++#define PICR1_10 2 ++#define PICR1_11 3 ++#define PCST1 7 ++ ++#define PSOC2 _SFR_MEM8(0xF0) ++#define POEN2A 0 ++#define POEN2C 1 ++#define POEN2B 2 ++#define POEN2D 3 ++#define PSYNC2_0 4 ++#define PSYNC2_1 5 ++#define POS22 6 ++#define POS23 7 ++ ++#define POM2 _SFR_MEM8(0xF1) ++#define POMV2A0 0 ++#define POMV2A1 1 ++#define POMV2A2 2 ++#define POMV2A3 3 ++#define POMV2B0 4 ++#define POMV2B1 5 ++#define POMV2B2 6 ++#define POMV2B3 7 ++ ++#define OCR2SA _SFR_MEM16(0xF2) ++ ++#define OCR2SAL _SFR_MEM8(0xF2) ++#define OCR2SA_0 0 ++#define OCR2SA_1 1 ++#define OCR2SA_2 2 ++#define OCR2SA_3 3 ++#define OCR2SA_4 4 ++#define OCR2SA_5 5 ++#define OCR2SA_6 6 ++#define OCR2SA_7 7 ++ ++#define OCR2SAH _SFR_MEM8(0xF3) ++#define OCR2SA_8 0 ++#define OCR2SA_9 1 ++#define OCR2SA_10 2 ++#define OCR2SA_11 3 ++ ++#define OCR2RA _SFR_MEM16(0xF4) ++ ++#define OCR2RAL _SFR_MEM8(0xF4) ++#define OCR2RA_0 0 ++#define OCR2RA_1 1 ++#define OCR2RA_2 2 ++#define OCR2RA_3 3 ++#define OCR2RA_4 4 ++#define OCR2RA_5 5 ++#define OCR2RA_6 6 ++#define OCR2RA_7 7 ++ ++#define OCR2RAH _SFR_MEM8(0xF5) ++#define OCR2RA_8 0 ++#define OCR2RA_9 1 ++#define OCR2RA_10 2 ++#define OCR2RA_11 3 ++ ++#define OCR2SB _SFR_MEM16(0xF6) ++ ++#define OCR2SBL _SFR_MEM8(0xF6) ++#define OCR2SB_0 0 ++#define OCR2SB_1 1 ++#define OCR2SB_2 2 ++#define OCR2SB_3 3 ++#define OCR2SB_4 4 ++#define OCR2SB_5 5 ++#define OCR2SB_6 6 ++#define OCR2SB_7 7 ++ ++#define OCR2SBH _SFR_MEM8(0xF7) ++#define OCR2SB_8 0 ++#define OCR2SB_9 1 ++#define OCR2SB_10 2 ++#define OCR2SB_11 3 ++ ++#define OCR2RB _SFR_MEM16(0xF8) ++ ++#define OCR2RBL _SFR_MEM8(0xF8) ++#define OCR2RB_0 0 ++#define OCR2RB_1 1 ++#define OCR2RB_2 2 ++#define OCR2RB_3 3 ++#define OCR2RB_4 4 ++#define OCR2RB_5 5 ++#define OCR2RB_6 6 ++#define OCR2RB_7 7 ++ ++#define OCR2RBH _SFR_MEM8(0xF9) ++#define OCR2RB_8 0 ++#define OCR2RB_9 1 ++#define OCR2RB_10 2 ++#define OCR2RB_11 3 ++#define OCR2RB_12 4 ++#define OCR2RB_13 5 ++#define OCR2RB_14 6 ++#define OCR2RB_15 7 ++ ++#define PCNF2 _SFR_MEM8(0xFA) ++#define POME2 0 ++#define PCLKSEL2 1 ++#define POP2 2 ++#define PMODE20 3 ++#define PMODE21 4 ++#define PLOCK2 5 ++#define PALOCK2 6 ++#define PFIFTY2 7 ++ ++#define PCTL2 _SFR_MEM8(0xFB) ++#define PRUN2 0 ++#define PCCYC2 1 ++#define PARUN2 2 ++#define PAOC2A 3 ++#define PAOC2B 4 ++#define PBFM2 5 ++#define PPRE20 6 ++#define PPRE21 7 ++ ++#define PFRC2A _SFR_MEM8(0xFC) ++#define PRFM2A0 0 ++#define PRFM2A1 1 ++#define PRFM2A2 2 ++#define PRFM2A3 3 ++#define PFLTE2A 4 ++#define PELEV2A 5 ++#define PISEL2A 6 ++#define PCAE2A 7 ++ ++#define PFRC2B _SFR_MEM8(0xFD) ++#define PRFM2B0 0 ++#define PRFM2B1 1 ++#define PRFM2B2 2 ++#define PRFM2B3 3 ++#define PFLTE2B 4 ++#define PELEV2B 5 ++#define PISEL2B 6 ++#define PCAE2B 7 ++ ++#define PICR2 _SFR_MEM16(0xFE) ++ ++#define PICR2L _SFR_MEM8(0xFE) ++#define PICR2_0 0 ++#define PICR2_1 1 ++#define PICR2_2 2 ++#define PICR2_3 3 ++#define PICR2_4 4 ++#define PICR2_5 5 ++#define PICR2_6 6 ++#define PICR2_7 7 ++ ++#define PICR2H _SFR_MEM8(0xFF) ++#define PICR2_8 0 ++#define PICR2_9 1 ++#define PICR2_10 2 ++#define PICR2_11 3 ++#define PCST2 7 ++ ++ ++ ++/* Interrupt Vectors */ ++/* Interrupt vector 0 is the reset vector. */ ++ ++#define PSC2_CAPT_vect_num 1 ++#define PSC2_CAPT_vect _VECTOR(1) /* PSC2 Capture Event */ ++ ++#define PSC2_EC_vect_num 2 ++#define PSC2_EC_vect _VECTOR(2) /* PSC2 End Cycle */ ++ ++#define PSC1_CAPT_vect_num 3 ++#define PSC1_CAPT_vect _VECTOR(3) /* PSC1 Capture Event */ ++ ++#define PSC1_EC_vect_num 4 ++#define PSC1_EC_vect _VECTOR(4) /* PSC1 End Cycle */ ++ ++#define PSC0_CAPT_vect_num 5 ++#define PSC0_CAPT_vect _VECTOR(5) /* PSC0 Capture Event */ ++ ++#define PSC0_EC_vect_num 6 ++#define PSC0_EC_vect _VECTOR(6) /* PSC0 End Cycle */ ++ ++#define ANALOG_COMP_0_vect_num 7 ++#define ANALOG_COMP_0_vect _VECTOR(7) /* Analog Comparator 0 */ ++ ++#define ANALOG_COMP_1_vect_num 8 ++#define ANALOG_COMP_1_vect _VECTOR(8) /* Analog Comparator 1 */ ++ ++#define ANALOG_COMP_2_vect_num 9 ++#define ANALOG_COMP_2_vect _VECTOR(9) /* Analog Comparator 2 */ ++ ++#define INT0_vect_num 10 ++#define INT0_vect _VECTOR(10) /* External Interrupt Request 0 */ ++ ++#define TIMER1_CAPT_vect_num 11 ++#define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */ ++ ++#define TIMER1_COMPA_vect_num 12 ++#define TIMER1_COMPA_vect _VECTOR(12) /* Timer/Counter1 Compare Match A */ ++ ++#define TIMER1_COMPB_vect_num 13 ++#define TIMER1_COMPB_vect _VECTOR(13) /* Timer/Counter Compare Match B */ ++ ++/* Vector 14, Reserved */ ++ ++#define TIMER1_OVF_vect_num 15 ++#define TIMER1_OVF_vect _VECTOR(15) /* Timer/Counter1 Overflow */ ++ ++#define TIMER0_COMPA_vect_num 16 ++#define TIMER0_COMPA_vect _VECTOR(16) /* Timer/Counter0 Compare Match A */ ++ ++#define TIMER0_OVF_vect_num 17 ++#define TIMER0_OVF_vect _VECTOR(17) /* Timer/Counter0 Overflow */ ++ ++#define ADC_vect_num 18 ++#define ADC_vect _VECTOR(18) /* ADC Conversion Complete */ ++ ++#define INT1_vect_num 19 ++#define INT1_vect _VECTOR(19) /* External Interrupt Request 1 */ ++ ++#define SPI_STC_vect_num 20 ++#define SPI_STC_vect _VECTOR(20) /* SPI Serial Transfer Complete */ ++ ++#define USART_RX_vect_num 21 ++#define USART_RX_vect _VECTOR(21) /* USART, Rx Complete */ ++ ++#define USART_UDRE_vect_num 22 ++#define USART_UDRE_vect _VECTOR(22) /* USART Data Register Empty */ ++ ++#define USART_TX_vect_num 23 ++#define USART_TX_vect _VECTOR(23) /* USART, Tx Complete */ ++ ++#define INT2_vect_num 24 ++#define INT2_vect _VECTOR(24) /* External Interrupt Request 2 */ ++ ++#define WDT_vect_num 25 ++#define WDT_vect _VECTOR(25) /* Watchdog Timeout Interrupt */ ++ ++#define EE_READY_vect_num 26 ++#define EE_READY_vect _VECTOR(26) /* EEPROM Ready */ ++ ++#define TIMER0_COMPB_vect_num 27 ++#define TIMER0_COMPB_vect _VECTOR(27) /* Timer Counter 0 Compare Match B */ ++ ++#define INT3_vect_num 28 ++#define INT3_vect _VECTOR(28) /* External Interrupt Request 3 */ ++ ++/* Vector 29, Reserved */ ++ ++/* Vector 30, Reserved */ ++ ++#define SPM_READY_vect_num 31 ++#define SPM_READY_vect _VECTOR(31) /* Store Program Memory Read */ ++ ++#define _VECTORS_SIZE 64 ++ ++ ++ ++/* Memory Sizes */ ++#define RAMSTART 0x100 ++#define RAMEND 0x2FF ++#define XRAMSIZE 0 ++#define XRAMEND RAMEND ++#define E2END 0x1FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x1FFF ++#define SPM_PAGESIZE 64 ++ ++ ++ ++/* Fuse Information */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown out detector trigger level */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++ ++/* Extended Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_PSCRV (unsigned char)~_BV(4) /* PSCOUT Reset Value */ ++#define FUSE_PSC0RB (unsigned char)~_BV(5) /* PSC0 Reset Behaviour */ ++#define FUSE_PSC1RB (unsigned char)~_BV(6) /* PSC1 Reset Behaviour */ ++#define FUSE_PSC2RB (unsigned char)~_BV(7) /* PSC2 Reset Behaviour */ ++#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x83 ++ ++ ++#endif /* _AVR_IO90PWM2B_H_ */ +diff --git a/include/avr/io90pwm316.h b/include/avr/io90pwm316.h +index ae0dda0..1569642 100644 +--- a/include/avr/io90pwm316.h ++++ b/include/avr/io90pwm316.h +@@ -1,1252 +1,1253 @@ +-/* Copyright (c) 2007, Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: io90pwm316.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* avr/io90pwm316.h - definitions for AT90PWM316 */ +- +-#ifndef _AVR_IO90PWM316_H_ +-#define _AVR_IO90PWM316_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "io90pwm316.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* Port B Input Pins Address */ +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-/* Port B Data Direction Register */ +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-/* Port B Data Register */ +-#define PORTB _SFR_IO8(0x05) +-#define PB0 0 +-#define PB1 1 +-#define PB2 2 +-#define PB3 3 +-#define PB4 4 +-#define PB5 5 +-#define PB6 6 +-#define PB7 7 +- +-/* Port C Input Pins Address */ +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +-#define PINC7 7 +- +-/* Port C Data Direction Register */ +-#define DDRC _SFR_IO8(0x07) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC3 3 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +-#define DDC7 7 +- +-/* Port C Data Register */ +-#define PORTC _SFR_IO8(0x08) +-#define PC0 0 +-#define PC1 1 +-#define PC2 2 +-#define PC3 3 +-#define PC4 4 +-#define PC5 5 +-#define PC6 6 +-#define PC7 7 +- +-/* Port D Input Pins Address */ +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-/* Port D Data Direction Register */ +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-/* Port D Data Register */ +-#define PORTD _SFR_IO8(0x0B) +-#define PD0 0 +-#define PD1 1 +-#define PD2 2 +-#define PD3 3 +-#define PD4 4 +-#define PD5 5 +-#define PD6 6 +-#define PD7 7 +- +-/* Port E Input Pins Address */ +-#define PINE _SFR_IO8(0x0C) +-#define PINE0 0 +-#define PINE1 1 +-#define PINE2 2 +- +-/* Port E Data Direction Register */ +-#define DDRE _SFR_IO8(0x0D) +-#define DDE0 0 +-#define DDE1 1 +-#define DDE2 2 +- +-/* Port E Data Register */ +-#define PORTE _SFR_IO8(0x0E) +-#define PE0 0 +-#define PE1 1 +-#define PE2 2 +- +-/* Timer/Counter 0 Interrupt Flag Register */ +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 /* Overflow Flag */ +-#define OCF0A 1 /* Output Compare Flag 0A */ +-#define OCF0B 2 /* Output Compare Flag 0B */ +- +-/* Timer/Counter1 Interrupt Flag Register */ +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 /* Overflow Flag */ +-#define OCF1A 1 /* Output Compare Flag 1A*/ +-#define OCF1B 2 /* Output Compare Flag 1B*/ +-#define ICF1 5 /* Input Capture Flag 1 */ +- +-/* General Purpose I/O Register 1 */ +-#define GPIOR1 _SFR_IO8(0x19) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-/* General Purpose I/O Register 2 */ +-#define GPIOR2 _SFR_IO8(0x1A) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-/* General Purpose I/O Register 3 */ +-#define GPIOR3 _SFR_IO8(0x1B) +-#define GPIOR30 0 +-#define GPIOR31 1 +-#define GPIOR32 2 +-#define GPIOR33 3 +-#define GPIOR34 4 +-#define GPIOR35 5 +-#define GPIOR36 6 +-#define GPIOR37 7 +- +-/* External Interrupt Flag Register */ +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +-#define INTF2 2 +-#define INTF3 3 +- +-/* External Interrupt Mask Register */ +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 /* External Interrupt Request 0 Enable */ +-#define INT1 1 /* External Interrupt Request 1 Enable */ +-#define INT2 2 /* External Interrupt Request 2 Enable */ +-#define INT3 3 /* External Interrupt Request 3 Enable */ +- +-/* General Purpose I/O Register 0 */ +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 /* EEPROM Read Enable */ +-#define EEWE 1 /* EEPROM Write Enable */ +-#define EEMWE 2 /* EEPROM Master Write Enable */ +-#define EERIE 3 /* EEPROM Ready Interrupt Enable */ +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-/* The EEPROM Address Registers */ +-#define EEAR _SFR_IO16(0x21) +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +-#define EEAR9 1 +-#define EEAR10 2 +-#define EEAR11 3 +- +-/* 6-char sequence denoting where to find the EEPROM registers in memory space. +- Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM +- subroutines. +- First two letters: EECR address. +- Second two letters: EEDR address. +- Last two letters: EEAR address. */ +-#define __EEPROM_REG_LOCATIONS__ 1F2021 +- +-/* General Timer/Counter Control Register */ +-#define GTCCR _SFR_IO8(0x23) +-#define PSR10 0 /* Prescaler Reset Timer/Counter1 and Timer/Counter0 */ +-#define ICPSEL1 6 /* Timer1 Input Capture Selection Bit */ +-#define TSM 7 /* Timer/Counter Synchronization Mode */ +- +-/* Timer/Counter Control Register A */ +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 /* Waveform Generation Mode */ +-#define WGM01 1 /* Waveform Generation Mode */ +-#define COM0B0 4 /* Compare Output Mode, Fast PWm */ +-#define COM0B1 5 /* Compare Output Mode, Fast PWm */ +-#define COM0A0 6 /* Compare Output Mode, Phase Correct PWM Mode */ +-#define COM0A1 7 /* Compare Output Mode, Phase Correct PWM Mode */ +- +-/* Timer/Counter Control Register B */ +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 /* Clock Select */ +-#define CS01 1 /* Clock Select */ +-#define CS02 2 /* Clock Select */ +-#define WGM02 3 /* Waveform Generation Mode */ +-#define FOC0B 6 /* Force Output Compare B */ +-#define FOC0A 7 /* Force Output Compare A */ +- +-/* Timer/Counter0 Register */ +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT00 0 +-#define TCNT01 1 +-#define TCNT02 2 +-#define TCNT03 3 +-#define TCNT04 4 +-#define TCNT05 5 +-#define TCNT06 6 +-#define TCNT07 7 +- +-/* Timer/Counter0 Output Compare Register A */ +-#define OCR0A _SFR_IO8(0x27) +-#define OCR0A0 0 +-#define OCR0A1 1 +-#define OCR0A2 2 +-#define OCR0A3 3 +-#define OCR0A4 4 +-#define OCR0A5 5 +-#define OCR0A6 6 +-#define OCR0A7 7 +- +-/* Timer/Counter0 Output Compare Register B */ +-#define OCR0B _SFR_IO8(0x28) +-#define OCR0B0 0 +-#define OCR0B1 1 +-#define OCR0B2 2 +-#define OCR0B3 3 +-#define OCR0B4 4 +-#define OCR0B5 5 +-#define OCR0B6 6 +-#define OCR0B7 7 +- +-/* PLL Control and Status Register */ +-#define PLLCSR _SFR_IO8(0x29) +-#define PLOCK 0 /* PLL Lock Detector */ +-#define PLLE 1 /* PLL Enable */ +-#define PLLF 2 /* PLL Factor */ +- +-/* SPI Control Register */ +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 /* SPI Clock Rate Select 0 */ +-#define SPR1 1 /* SPI Clock Rate Select 1 */ +-#define CPHA 2 /* Clock Phase */ +-#define CPOL 3 /* Clock polarity */ +-#define MSTR 4 /* Master/Slave Select */ +-#define DORD 5 /* Data Order */ +-#define SPE 6 /* SPI Enable */ +-#define SPIE 7 /* SPI Interrupt Enable */ +- +-/* SPI Status Register */ +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 /* Double SPI Speed Bit */ +-#define WCOL 6 /* Write Collision Flag */ +-#define SPIF 7 /* SPI Interrupt Flag */ +- +-/* SPI Data Register */ +-#define SPDR _SFR_IO8(0x2E) +-#define SPD0 0 +-#define SPD1 1 +-#define SPD2 2 +-#define SPD3 3 +-#define SPD4 4 +-#define SPD5 5 +-#define SPD6 6 +-#define SPD7 7 +- +-/* Analog Comparator Status Register */ +-#define ACSR _SFR_IO8(0x30) +-#define AC0O 0 /* Analog Comparator 0 Output Bit */ +-#define AC1O 1 /* Analog Comparator 1 Output Bit */ +-#define AC2O 2 /* Analog Comparator 2 Output Bit */ +-#define AC0IF 4 /* Analog Comparator 0 Interrupt Flag Bit */ +-#define AC1IF 5 /* Analog Comparator 1 Interrupt Flag Bit */ +-#define AC2IF 6 /* Analog Comparator 2 Interrupt Flag Bit */ +-#define ACCKDIV 7 /* Analog Comparator Clock Divider */ +- +-/* Sleep Mode Control Register */ +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 /* Sleep Enable */ +-#define SM0 1 /* Sleep Mode Select bit0 */ +-#define SM1 2 /* Sleep Mode Select bit1 */ +-#define SM2 3 /* Sleep Mode Select bit2 */ +- +-/* MCU Status Register */ +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 /* Power-on reset flag */ +-#define EXTRF 1 /* External Reset Flag */ +-#define BORF 2 /* Brown-out Reset Flag */ +-#define WDRF 3 /* Watchdog Reset Flag */ +- +-/* MCU Control Register */ +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 /* Interrupt Vector Change Enable */ +-#define IVSEL 1 /* Interrupt Vector Select */ +-#define PUD 4 /* Pull-up disable */ +-#define SPIPS 7 /* SPI Pin Select */ +- +-/* Store Program Memory Control Register */ +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 /* Store Program Memory Enable */ +-#define PGERS 1 /* Page Erase */ +-#define PGWRT 2 /* Page Write */ +-#define BLBSET 3 /* Boot Lock Bit Set */ +-#define RWWSRE 4 /* Read While Write section read enable */ +-#define RWWSB 6 /* Read While Write Section Busy */ +-#define SPMIE 7 /* SPM Interrupt Enable */ +- +-/* Watchdog Timer Control Register */ +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 /* Watchdog Timer Prescaler bit0 */ +-#define WDP1 1 /* Watchdog Timer Prescaler bit1 */ +-#define WDP2 2 /* Watchdog Timer Prescaler bit2 */ +-#define WDE 3 /* Watchdog Enable */ +-#define WDCE 4 /* Watchdog Change Enable */ +-#define WDP3 5 /* Watchdog Timer Prescaler bit3 */ +-#define WDIE 6 /* Watchdog Timeout Interrupt Enable */ +-#define WDIF 7 /* Watchdog Timeout Interrupt Flag */ +- +-/* Clock Prescaler Register */ +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 /* Clock Prescaler Select bit0 */ +-#define CLKPS1 1 /* Clock Prescaler Select bit1 */ +-#define CLKPS2 2 /* Clock Prescaler Select bit2 */ +-#define CLKPS3 3 /* Clock Prescaler Select bit3 */ +-#define CLKPCE 7 /* Clock Prescaler Change Enable */ +- +-/* Power Reduction Register */ +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 /* Power Reduction ADC */ +-#define PRUSART 1 /* Power Reduction USART */ +-#define PRSPI 2 /* Power Reduction Serial Peripheral Interface */ +-#define PRTIM0 3 /* Power Reduction Timer/Counter0 */ +-#define PRTIM1 4 /* Power Reduction Timer/Counter1 */ +-#define PRPSC0 5 /* Power Reduction PSC0 */ +-#define PRPSC1 6 /* Power Reduction PSC1 */ +-#define PRPSC2 7 /* Power Reduction PSC2 */ +- +-/* Oscillator Calibration Value */ +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +- +-/* External Interrupt Control Register A */ +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define ISC20 4 +-#define ISC21 5 +-#define ISC30 6 +-#define ISC31 7 +- +-/* Timer/Counter0 Interrupt Mask Register */ +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 /* Overflow Interrupt Enable */ +-#define OCIE0A 1 /* Output Compare Match A Interrupt Enable */ +-#define OCIE0B 2 /* Output Compare Match B Interrupt Enable */ +- +-/* Timer/Counter1 Interrupt Mask Register */ +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 /* Overflow Interrupt Enable */ +-#define OCIE1A 1 /* Output Compare Match A Interrupt Enable */ +-#define OCIE1B 2 /* Output Compare Match B Interrupt Enable */ +-#define ICIE1 5 /* Input Capture Interrupt Enable */ +- +-/* Amplifier 0 Control and Status register */ +-#define AMP0CSR _SFR_MEM8(0x76) +-#define AMP0TS0 0 +-#define AMP0TS1 1 +-#define AMP0G0 4 +-#define AMP0G1 5 +-#define AMP0IS 6 +-#define AMP0EN 7 +- +-/* Amplifier 1 Control and Status register */ +-#define AMP1CSR _SFR_MEM8(0x77) +-#define AMP1TS0 0 +-#define AMP1TS1 1 +-#define AMP1G0 4 +-#define AMP1G1 5 +-#define AMP1IS 6 +-#define AMP1EN 7 +- +-/* ADC Result Data Register */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +-#define ADCL _SFR_MEM8(0x78) +-#define ADCH _SFR_MEM8(0x79) +- +-/* ADC Control and Status Register A */ +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 /* ADC Prescaler Select bit0 */ +-#define ADPS1 1 /* ADC Prescaler Select bit1 */ +-#define ADPS2 2 /* ADC Prescaler Select bit2 */ +-#define ADIE 3 /* ADC Interrupt Enable */ +-#define ADIF 4 /* ADC Interrupt Flag */ +-#define ADATE 5 /* ADC Auto Trigger Enable */ +-#define ADSC 6 /* ADC Start Conversion */ +-#define ADEN 7 /* ADC Enable */ +- +-/* ADC Control and Status Register B */ +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 /* ADC Auto Trigger Source 0 */ +-#define ADTS1 1 /* ADC Auto Trigger Source 1 */ +-#define ADTS2 2 /* ADC Auto Trigger Source 2 */ +-#define ADTS3 3 /* ADC Auto Trigger Source 3 */ +-#define ADHSM 7 /* ADC High Speed Mode */ +- +-/* ADC multiplexer Selection Register */ +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 /* Analog Channel and Gain Selection bit0 */ +-#define MUX1 1 /* Analog Channel and Gain Selection bit1 */ +-#define MUX2 2 /* Analog Channel and Gain Selection bit2 */ +-#define MUX3 3 /* Analog Channel and Gain Selection bit3 */ +-#define ADLAR 5 /* Left Adjust Result */ +-#define REFS0 6 /* Reference Selection bit0 */ +-#define REFS1 7 /* Reference Selection bit1 */ +- +-/* Digital Input Disable Register 0 */ +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 /* ADC0 Digital input Disable */ +-#define ADC1D 1 /* ADC1 Digital input Disable */ +-#define ADC2D 2 /* ADC2 Digital input Disable */ +-#define ADC3D 3 /* ADC3 Digital input Disable */ +-#define ADC4D 4 /* ADC4 Digital input Disable */ +-#define ADC5D 5 /* ADC5 Digital input Disable */ +-#define ADC6D 6 /* ADC6 Digital input Disable */ +-#define ADC7D 7 /* ADC7 Digital input Disable */ +- +-/* Digital Input Disable Register 1 */ +-#define DIDR1 _SFR_MEM8(0x7F) +-#define ADC8D 0 /* ADC8 Digital input Disable */ +-#define ADC9D 1 /* ADC9 Digital input Disable */ +-#define ADC10D 2 /* ADC10 Digital input Disable */ +-#define AMP0ND 3 +-#define AMP0PD 4 +-#define ACMP0D 5 +- +-/* Timer/Counter1 Control Register A */ +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 /* Waveform Generation Mode */ +-#define WGM11 1 /* Waveform Generation Mode */ +-#define COM1B0 4 /* Compare Output Mode 1B, bit 0 */ +-#define COM1B1 5 /* Compare Output Mode 1B, bit 1 */ +-#define COM1A0 6 /* Comparet Ouput Mode 1A, bit 0 */ +-#define COM1A1 7 /* Comparet Ouput Mode 1A, bit 1 */ +- +-/* Timer/Counter1 Control Register B */ +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 /* Prescaler source of Timer/Counter 1 */ +-#define CS11 1 /* Prescaler source of Timer/Counter 1 */ +-#define CS12 2 /* Prescaler source of Timer/Counter 1 */ +-#define WGM12 3 /* Waveform Generation Mode */ +-#define WGM13 4 /* Waveform Generation Mode */ +-#define ICES1 6 /* Input Capture 1 Edge Select */ +-#define ICNC1 7 /* Input Capture 1 Noise Canceler */ +- +-/* Timer/Counter1 Control Register C */ +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 /* Force Output Compare for Channel B */ +-#define FOC1A 7 /* Force Output Compare for Channel A */ +- +-/* Timer/Counter1 */ +-#define TCNT1 _SFR_MEM16(0x84) +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT10 0 +-#define TCNT11 1 +-#define TCNT12 2 +-#define TCNT13 3 +-#define TCNT14 4 +-#define TCNT15 5 +-#define TCNT16 6 +-#define TCNT17 7 +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT18 0 +-#define TCNT19 1 +-#define TCNT110 2 +-#define TCNT111 3 +-#define TCNT112 4 +-#define TCNT113 5 +-#define TCNT114 6 +-#define TCNT115 7 +- +-/* Input Capture Register 1 */ +-#define ICR1 _SFR_MEM16(0x86) +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR17 7 +-#define ICR16 6 +-#define ICR15 5 +-#define ICR14 4 +-#define ICR13 3 +-#define ICR12 2 +-#define ICR11 1 +-#define ICR10 0 +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR115 7 +-#define ICR114 6 +-#define ICR113 5 +-#define ICR112 4 +-#define ICR111 3 +-#define ICR110 2 +-#define ICR19 1 +-#define ICR18 0 +- +-/* Output Compare Register 1 A */ +-#define OCR1A _SFR_MEM16(0x88) +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1A0 0 +-#define OCR1A1 1 +-#define OCR1A2 2 +-#define OCR1A3 3 +-#define OCR1A4 4 +-#define OCR1A5 5 +-#define OCR1A6 6 +-#define OCR1A7 7 +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1A8 0 +-#define OCR1A9 1 +-#define OCR1A10 2 +-#define OCR1A11 3 +-#define OCR1A12 4 +-#define OCR1A13 5 +-#define OCR1A14 6 +-#define OCR1A15 7 +- +-/* Output Compare Register 1 B */ +-#define OCR1B _SFR_MEM16(0x8A) +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1B0 0 +-#define OCR1B1 1 +-#define OCR1B2 2 +-#define OCR1B3 3 +-#define OCR1B4 4 +-#define OCR1B5 5 +-#define OCR1B6 6 +-#define OCR1B7 7 +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1B8 0 +-#define OCR1B9 1 +-#define OCR1B10 2 +-#define OCR1B11 3 +-#define OCR1B12 4 +-#define OCR1B13 5 +-#define OCR1B14 6 +-#define OCR1B15 7 +- +-/* PSC0 Interrupt Flag Register */ +-#define PIFR0 _SFR_MEM8(0xA0) +-#define PEOP0 0 /* End Of PSC0 Interrupt */ +-#define PRN00 1 /* PSC0 Ramp Number bit0 */ +-#define PRN01 2 /* PSC0 Ramp Number bit1 */ +-#define PEV0A 3 /* PSC0 External Event A Interrupt */ +-#define PEV0B 4 /* PSC0 External Event B Interrupt */ +-#define PSEI0 5 /* PSC0 Synchro Error Interrupt */ +-#define POAC0A 6 /* PSC0 Output A Activity */ +-#define POAC0B 7 /* PSC0 Output B Activity */ +- +-/* PSC0 Interrupt Mask Register */ +-#define PIM0 _SFR_MEM8(0xA1) +-#define PEOPE0 0 /* PSC0 End Of Cycle Interrupt Enable */ +-#define PEVE0A 3 /* PSC0 External Event A Interrupt Enable */ +-#define PEVE0B 4 /* PSC0 External Event B Interrupt Enable */ +-#define PSEIE0 5 /* PSC0 Synchro Error Interrupt Enable */ +- +-/* PSC1 Interrupt Flag Register */ +-#define PIFR1 _SFR_MEM8(0xA2) +-#define PEOP1 0 +-#define PRN10 1 +-#define PRN11 2 +-#define PEV1A 3 +-#define PEV1B 4 +-#define PSEI1 5 +-#define POAC1A 6 +-#define POAC1B 7 +- +-/* PSC1 Interrupt Mask Register */ +-#define PIM1 _SFR_MEM8(0xA3) +- +-/* PSC2 Interrupt Flag Register */ +-#define PIFR2 _SFR_MEM8(0xA4) +-#define PEOP2 0 /* End Of PSC2 Interrupt */ +-#define PRN20 1 /* PSC2 Ramp Number bit0 */ +-#define PRN21 2 /* PSC2 Ramp Number bit1 */ +-#define PEV2A 3 /* PSC2 External Event A Interrupt */ +-#define PEV2B 4 /* PSC2 External Event B Interrupt */ +-#define PSEI2 5 /* PSC2 Synchro Error Interrupt */ +-#define POAC2A 6 /* PSC2 Output A Activity */ +-#define POAC2B 7 /* PSC2 Output B Activity */ +- +-/* PSC2 Interrupt Mask Register */ +-#define PIM2 _SFR_MEM8(0xA5) +-#define PEOPE2 0 /* PSC2 End Of Cycle Interrupt Enable */ +-#define PEVE2A 3 /* PSC2 External Event A Interrupt Enable */ +-#define PEVE2B 4 /* PSC2 External Event B Interrupt Enable */ +-#define PSEIE2 5 /* PSC2 Synchro Error Interrupt Enable */ +- +-/* Digital to Analog Conversion Control Register */ +-#define DACON _SFR_MEM8(0xAA) +-#define DAEN 0 /* Digital to Analog Enable bit */ +-#define DAOE 1 /* Digital to Analog Output Enable bit */ +-#define DALA 2 /* Digital to Analog Left Adjust */ +-#define DATS0 4 /* DAC Trigger Selection bit0 */ +-#define DATS1 5 /* DAC Trigger Selection bit1 */ +-#define DATS2 6 /* DAC Trigger Selection bit2 */ +-#define DAATE 7 /* DAC Auto Trigger Enable bit */ +- +-/* Digital to Analog Converter input Register */ +-#define DAC _SFR_MEM16(0xAB) +-#define DACL _SFR_MEM8(0xAB) +-#define DACH _SFR_MEM8(0xAC) +- +-/* Analog Comparator 0 Control Register */ +-#define AC0CON _SFR_MEM8(0xAD) +-#define AC0M0 0 /* Analog Comparator 0 Multiplexer register bit0 */ +-#define AC0M1 1 /* Analog Comparator 0 Multiplexer register bit1 */ +-#define AC0M2 2 /* Analog Comparator 0 Multiplexer register bit2 */ +-#define AC0IS0 4 /* Analog Comparator 0 Interrupt Select bit0 */ +-#define AC0IS1 5 /* Analog Comparator 0 Interrupt Select bit1 */ +-#define AC0IE 6 /* Analog Comparator 0 Interrupt Enable bit */ +-#define AC0EN 7 /* Analog Comparator 0 Enable Bit */ +- +-/* Analog Comparator 1 Control Register */ +-#define AC1CON _SFR_MEM8(0xAE) +-#define AC1M0 0 /* Analog Comparator 1 Multiplexer register bit0 */ +-#define AC1M1 1 /* Analog Comparator 1 Multiplexer register bit1 */ +-#define AC1M2 2 /* Analog Comparator 1 Multiplexer register bit2 */ +-#define AC1ICE 3 /* Analog Comparator 1 Interrupt Capture Enable bit */ +-#define AC1IS0 4 /* Analog Comparator 1 Interrupt Select bit0 */ +-#define AC1IS1 5 /* Analog Comparator 1 Interrupt Select bit1 */ +-#define AC1IE 6 /* Analog Comparator 1 Interrupt Enable bit */ +-#define AC1EN 7 /* Analog Comparator 1 Enable Bit */ +- +-/* Analog Comparator 2 Control Register */ +-#define AC2CON _SFR_MEM8(0xAF) +-#define AC2M0 0 /* Analog Comparator 2 Multiplexer register bit0 */ +-#define AC2M1 1 /* Analog Comparator 2 Multiplexer register bit1 */ +-#define AC2M2 2 /* Analog Comparator 2 Multiplexer register bit2 */ +-#define AC2IS0 4 /* Analog Comparator 2 Interrupt Select bit0 */ +-#define AC2IS1 5 /* Analog Comparator 2 Interrupt Select bit1 */ +-#define AC2IE 6 /* Analog Comparator 2 Interrupt Enable bit */ +-#define AC2EN 7 /* Analog Comparator 2 Enable Bit */ +- +-/* USART Control and Status Register A */ +-#define UCSRA _SFR_MEM8(0xC0) +-#define MPCM 0 /* Multi-processor Communication Mode */ +-#define U2X 1 /* Double the USART Transmission Speed */ +-#define UPE 2 /* USART Parity Error */ +-#define DOR 3 /* Data OverRun */ +-#define FE 4 /* Frame Error */ +-#define UDRE 5 /* USART Data Register Empty */ +-#define TXC 6 /* USART Transmit Complete */ +-#define RXC 7 /* USART Receive Complete */ +- +-/* USART Control and Status Register B */ +-#define UCSRB _SFR_MEM8(0xC1) +-#define TXB8 0 /* Transmit Data Bit 8 */ +-#define RXB8 1 /* Receive Data Bit 8 */ +-#define UCSZ2 2 /* Character Size */ +-#define TXEN 3 /* Transmitter Enable */ +-#define RXEN 4 /* Receiver Enable */ +-#define UDRIE 5 /* USART Data Register Empty Interrupt Enable */ +-#define TXCIE 6 /* TX Complete Interrupt Enable */ +-#define RXCIE 7 /* RX Complete Interrupt Enable */ +- +-/* USART Control and Status Register C */ +-#define UCSRC _SFR_MEM8(0xC2) +-#define UCPOL 0 /* Clock Polarity */ +-#define UCSZ0 1 /* Character Size bit0 */ +-#define UCSZ1 2 /* Character Size bit1 */ +-#define USBS 3 /* Stop Bit Select */ +-#define UPM0 4 /* Parity Mode bit0 */ +-#define UPM1 5 /* Parity Mode bit1 */ +-#define UMSEL 6 /* USART Mode Select */ +- +-/* USART Baud Rate Register */ +-#define UBRR _SFR_MEM16(0xC4) +-#define UBRRL _SFR_MEM8(0xC4) +-#define UBRRH _SFR_MEM8(0xC5) +- +-/* USART I/O Data Register */ +-#define UDR _SFR_MEM8(0xC6) +- +-/* EUSART Control and Status Register A */ +-#define EUCSRA _SFR_MEM8(0xC8) +-#define URxS0 0 /* EUSART Receive Character Size bit0 */ +-#define URxS1 1 /* EUSART Receive Character Size bit1 */ +-#define URxS2 2 /* EUSART Receive Character Size bit2 */ +-#define URxS3 3 /* EUSART Receive Character Size bit3 */ +-#define UTxS0 4 /* EUSART Transmit Character Size bit0 */ +-#define UTxS1 5 /* EUSART Transmit Character Size bit1 */ +-#define UTxS2 6 /* EUSART Transmit Character Size bit2 */ +-#define UTxS3 7 /* EUSART Transmit Character Size bit3 */ +- +-/* EUSART Control and Status Register B */ +-#define EUCSRB _SFR_MEM8(0xC9) +-#define BODR 0 /* Bit Order */ +-#define EMCH 1 /* Manchester mode */ +-#define EUSBS 3 /* EUSBS Enable Bit */ +-#define EUSART 4 /* EUSART Enable Bit */ +- +-/* EUSART Control and Status Register C */ +-#define EUCSRC _SFR_MEM8(0xCA) +-#define STP0 0 /* Stop bits values bit0 */ +-#define STP1 1 /* Stop bits values bit1 */ +-#define F1617 2 +-#define FEM 3 /* Frame Error Manchester */ +- +-/* Manchester receiver Baud Rate Registers */ +-#define MUBRR _SFR_MEM16(0xCC) +-#define MUBRRL _SFR_MEM8(0xCC) +-#define MUBRRH _SFR_MEM8(0xCD) +- +-/* EUSART I/O Data Register */ +-#define EUDR _SFR_MEM8(0xCE) +- +-/* PSC 0 Synchro and Output Configuration */ +-#define PSOC0 _SFR_MEM8(0xD0) +-#define POEN0A 0 /* PSC 0 OUT Part A Output Enable */ +-#define POEN0B 2 /* PSC 0 OUT Part B Output Enable */ +-#define PSYNC00 4 /* Synchronization Out for ADC Selection bit0 */ +-#define PSYNC01 5 /* Synchronization Out for ADC Selection bit1 */ +- +-/* Output Compare SA Registers */ +-#define OCR0SA _SFR_MEM16(0xD2) +-#define OCR0SAL _SFR_MEM8(0xD2) +-#define OCR0SAH _SFR_MEM8(0xD3) +- +-/* Output Compare RA Registers */ +-#define OCR0RA _SFR_MEM16(0xD4) +-#define OCR0RAL _SFR_MEM8(0xD4) +-#define OCR0RAH _SFR_MEM8(0xD5) +- +-/* Output Compare SB Registers */ +-#define OCR0SB _SFR_MEM16(0xD6) +-#define OCR0SBL _SFR_MEM8(0xD6) +-#define OCR0SBH _SFR_MEM8(0xD7) +- +-/* Output Compare RB Registers */ +-#define OCR0RB _SFR_MEM16(0xD8) +-#define OCR0RBL _SFR_MEM8(0xD8) +-#define OCR0RBH _SFR_MEM8(0xD9) +- +-/* PSC 0 Configuration Register */ +-#define PCNF0 _SFR_MEM8(0xDA) +-#define PCLKSEL0 1 /* PSC 0 Input Clock Select */ +-#define POP0 2 /* PSC 0 Output Polarity */ +-#define PMODE00 3 /* PSC 0 Mode bit0 */ +-#define PMODE01 4 /* PSC 0 Mode bit1 */ +-#define PLOCK0 5 /* PSC 0 Lock */ +-#define PALOCK0 6 /* PSC 0 Autolock */ +-#define PFIFTY0 7 /* PSC 0 Fifty */ +- +-/* PSC 0 Control Register */ +-#define PCTL0 _SFR_MEM8(0xDB) +-#define PRUN0 0 /* PSC 0 Run */ +-#define PCCYC0 1 /* PSC 0 Complete Cycle */ +-#define PARUN0 2 /* PSC 0 Autorun */ +-#define PAOC0A 3 /* PSC 0 Asynchronous Output Control A */ +-#define PAOC0B 4 /* PSC 0 Asynchronous Output Control B */ +-#define PBFM0 5 /* Balance Flank Width Modulation */ +-#define PPRE00 6 /* PSC 0 Prescaler Select bit0 */ +-#define PPRE01 7 /* PSC 0 Prescaler Select bit1 */ +- +-/* PSC 0 Input A Control Register */ +-#define PFRC0A _SFR_MEM8(0xDC) +-#define PRFM0A0 0 /* PSC 0 Fault Mode bit0 */ +-#define PRFM0A1 1 /* PSC 0 Fault Mode bit1 */ +-#define PRFM0A2 2 /* PSC 0 Fault Mode bit2 */ +-#define PRFM0A3 3 /* PSC 0 Fault Mode bit3 */ +-#define PFLTE0A 4 /* PSC 0 Filter Enable on Input Part A */ +-#define PELEV0A 5 /* PSC 0 Edge Level Selector of Input Part A */ +-#define PISEL0A 6 /* PSC 0 Input Select for Part A */ +-#define PCAE0A 7 /* PSC 0 Capture Enable Input Part A */ +- +-/* PSC 0 Input B Control Register */ +-#define PFRC0B _SFR_MEM8(0xDD) +-#define PRFM0B0 0 /* PSC 0 Fault Mode bit0 */ +-#define PRFM0B1 1 /* PSC 0 Fault Mode bit1 */ +-#define PRFM0B2 2 /* PSC 0 Fault Mode bit2 */ +-#define PRFM0B3 3 /* PSC 0 Fault Mode bit3 */ +-#define PFLTE0B 4 /* PSC 0 Filter Enable on Input Part B */ +-#define PELEV0B 5 /* PSC 0 Edge Level Selector of Input Part B */ +-#define PISEL0B 6 /* PSC 0 Input Select for Part B */ +-#define PCAE0B 7 /* PSC 0 Capture Enable Input Part B */ +- +-/* PSC 0 Input Capture Registers */ +-#define PICR0 _SFR_MEM16(0xDE) +-#define PICR0L _SFR_MEM8(0xDE) +-#define PICR0H _SFR_MEM8(0xDF) +-#define PCST0 7 /* PSC Capture Software Trig bit */ +- +-/* PSC 1 Synchro and Output Configuration */ +-#define PSOC1 _SFR_MEM8(0xE0) +-#define POEN1A 0 +-#define POEN1B 2 +-#define PSYNC1_0 4 +-#define PSYNC1_1 5 +- +-/* Output Compare SA Registers */ +-#define OCR1SA _SFR_MEM16(0xE2) +-#define OCR1SAL _SFR_MEM8(0xE2) +-#define OCR1SAH _SFR_MEM8(0xE3) +- +-/* Output Compare RA Registers */ +-#define OCR1RA _SFR_MEM16(0xE4) +-#define OCR1RAL _SFR_MEM8(0xE4) +-#define OCR1RAH _SFR_MEM8(0xE5) +- +-/* Output Compare SB Registers */ +-#define OCR1SB _SFR_MEM16(0xE6) +-#define OCR1SBL _SFR_MEM8(0xE6) +-#define OCR1SBH _SFR_MEM8(0xE7) +- +-/* Output Compare RB Registers */ +-#define OCR1RB _SFR_MEM16(0xE8) +-#define OCR1RBL _SFR_MEM8(0xE8) +-#define OCR1RBH _SFR_MEM8(0xE9) +- +-/* PSC 1 Configuration Register */ +-#define PCNF1 _SFR_MEM8(0xEA) +-#define PCLKSEL1 1 +-#define POP1 2 +-#define PMODE10 3 +-#define PMODE11 4 +-#define PLOCK1 5 +-#define PALOCK1 6 +-#define PFIFTY1 7 +- +-/* PSC 1 Control Register */ +-#define PCTL1 _SFR_MEM8(0xEB) +-#define PRUN1 0 +-#define PCCYC1 1 +-#define PARUN1 2 +-#define PAOC1A 3 +-#define PAOC1B 4 +-#define PBFM1 5 +-#define PPRE10 6 +-#define PPRE11 7 +- +-/* PSC 1 Input A Control Register */ +-#define PFRC1A _SFR_MEM8(0xEC) +-#define PRFM1A0 0 +-#define PRFM1A1 1 +-#define PRFM1A2 2 +-#define PRFM1A3 3 +-#define PFLTE1A 4 +-#define PELEV1A 5 +-#define PISEL1A 6 +-#define PCAE1A 7 +- +-/* PSC 1 Input B Control Register */ +-#define PFRC1B _SFR_MEM8(0xED) +-#define PRFM1B0 0 +-#define PRFM1B1 1 +-#define PRFM1B2 2 +-#define PRFM1B3 3 +-#define PFLTE1B 4 +-#define PELEV1B 5 +-#define PISEL1B 6 +-#define PCAE1B 7 +- +-/* PSC 1 Input Capture Registers */ +-#define PICR1 _SFR_MEM16(0xEE) +-#define PICR1L _SFR_MEM8(0xEE) +-#define PICR1H _SFR_MEM8(0xEF) +- +-/* PSC 2 Synchro and Output Configuration */ +-#define PSOC2 _SFR_MEM8(0xF0) +-#define POEN2A 0 /* PSC 2 OUT Part A Output Enable */ +-#define POEN2C 1 /* PSCOUT22 Output Enable */ +-#define POEN2B 2 /* PSC 2 OUT Part B Output Enable */ +-#define POEN2D 3 /* PSCOUT23 Output Enable */ +-#define PSYNC20 4 /* Synchronization Out for ADC Selection bit0 */ +-#define PSYNC21 5 /* Synchronization Out for ADC Selection bit1 */ +-#define POS22 6 /* PSCOUT22 Selection */ +-#define POS23 7 /* PSCOUT23 Selection */ +- +-/* PSC 2 Output Matrix */ +-#define POM2 _SFR_MEM8(0xF1) +-#define POMV2A0 0 /* Output Matrix Output A Ramp 0 */ +-#define POMV2A1 1 /* Output Matrix Output A Ramp 1 */ +-#define POMV2A2 2 /* Output Matrix Output A Ramp 2 */ +-#define POMV2A3 3 /* Output Matrix Output A Ramp 3 */ +-#define POMV2B0 4 /* Output Matrix Output B Ramp 0 */ +-#define POMV2B1 5 /* Output Matrix Output B Ramp 1 */ +-#define POMV2B2 6 /* Output Matrix Output B Ramp 2 */ +-#define POMV2B3 7 /* Output Matrix Output B Ramp 3 */ +- +-/* Output Compare SA Registers */ +-#define OCR2SA _SFR_MEM16(0xF2) +-#define OCR2SAL _SFR_MEM8(0xF2) +-#define OCR2SAH _SFR_MEM8(0xF3) +- +-/* Output Compare RA Registers */ +-#define OCR2RA _SFR_MEM16(0xF4) +-#define OCR2RAL _SFR_MEM8(0xF4) +-#define OCR2RAH _SFR_MEM8(0xF5) +- +-/* Output Compare SB Registers */ +-#define OCR2SB _SFR_MEM16(0xF6) +-#define OCR2SBL _SFR_MEM8(0xF6) +-#define OCR2SBH _SFR_MEM8(0xF7) +- +-/* Output Compare RB Registers */ +-#define OCR2RB _SFR_MEM16(0xF8) +-#define OCR2RBL _SFR_MEM8(0xF8) +-#define OCR2RBH _SFR_MEM8(0xF9) +- +-/* PSC 2 Configuration Register */ +-#define PCNF2 _SFR_MEM8(0xFA) +-#define POME2 0 /* PSC 2 Output Matrix Enable */ +-#define PCLKSEL2 1 /* PSC 2 Input Clock Select */ +-#define POP2 2 /* PSC 2 Output Polarity */ +-#define PMODE20 3 /* PSC 2 Mode bit0 */ +-#define PMODE21 4 /* PSC 2 Mode bit1 */ +-#define PLOCK2 5 /* PSC 2 Lock */ +-#define PALOCK2 6 /* PSC 2 Autolock */ +-#define PFIFTY2 7 /* PSC 2 Fifty */ +- +-/* PSC 2 Control Register */ +-#define PCTL2 _SFR_MEM8(0xFB) +-#define PRUN2 0 /* PSC 2 Run */ +-#define PCCYC2 1 /* PSC 2 Complete Cycle */ +-#define PARUN2 2 /* PSC 2 Autorun */ +-#define PAOC2A 3 /* PSC 2 Asynchronous Output Control A */ +-#define PAOC2B 4 /* PSC 2 Asynchronous Output Control B */ +-#define PBFM2 5 /* Balance Flank Width Modulation */ +-#define PPRE20 6 /* PSC 2 Prescaler Select bit0 */ +-#define PPRE21 7 /* PSC 2 Prescaler Select bit1 */ +- +-/* PSC 2 Input A Control Register */ +-#define PFRC2A _SFR_MEM8(0xFC) +-#define PRFM2A0 0 /* PSC 2 Fault Mode bit0 */ +-#define PRFM2A1 1 /* PSC 2 Fault Mode bit1 */ +-#define PRFM2A2 2 /* PSC 2 Fault Mode bit2 */ +-#define PRFM2A3 3 /* PSC 2 Fault Mode bit3 */ +-#define PFLTE2A 4 /* PSC 2 Filter Enable on Input Part A */ +-#define PELEV2A 5 /* PSC 2 Edge Level Selector of Input Part A */ +-#define PISEL2A 6 /* PSC 2 Input Select for Part A */ +-#define PCAE2A 7 /* PSC 2 Capture Enable Input Part A */ +- +-/* PSC 2 Input B Control Register */ +-#define PFRC2B _SFR_MEM8(0xFD) +-#define PRFM2B0 0 /* PSC 2 Fault Mode bit0 */ +-#define PRFM2B1 1 /* PSC 2 Fault Mode bit1 */ +-#define PRFM2B2 2 /* PSC 2 Fault Mode bit2 */ +-#define PRFM2B3 3 /* PSC 2 Fault Mode bit3 */ +-#define PFLTE2B 4 /* PSC 2 Filter Enable on Input Part B */ +-#define PELEV2B 5 /* PSC 2 Edge Level Selector of Input Part B */ +-#define PISEL2B 6 /* PSC 2 Input Select for Part B */ +-#define PCAE2B 7 /* PSC 2 Capture Enable Input Part B */ +- +-/* PSC 2 Input Capture Registers */ +-#define PICR2 _SFR_MEM16(0xFE) +-#define PICR2L _SFR_MEM8(0xFE) +-#define PICR2H _SFR_MEM8(0xFF) +-#define PCST2 7 /* PSC Capture Software Trig bit */ +- +- +-/* Interrupt Vectors */ +-/* Interrupt 0 is the reset vector. */ +- +-/* PSC2 Capture Event */ +-#define PSC2_CAPT_vect_num 1 +-#define PSC2_CAPT_vect _VECTOR(1) +- +-/* PSC2 End Cycle */ +-#define PSC2_EC_vect_num 2 +-#define PSC2_EC_vect _VECTOR(2) +- +-/* PSC1 Capture Event */ +-#define PSC1_CAPT_vect_num 3 +-#define PSC1_CAPT_vect _VECTOR(3) +- +-/* PSC1 End Cycle */ +-#define PSC1_EC_vect_num 4 +-#define PSC1_EC_vect _VECTOR(4) +- +-/* PSC0 Capture Event */ +-#define PSC0_CAPT_vect_num 5 +-#define PSC0_CAPT_vect _VECTOR(5) +- +-/* PSC0 End Cycle */ +-#define PSC0_EC_vect_num 6 +-#define PSC0_EC_vect _VECTOR(6) +- +-/* Analog Comparator 0 */ +-#define ANALOG_COMP_0_vect_num 7 +-#define ANALOG_COMP_0_vect _VECTOR(7) +- +-/* Analog Comparator 1 */ +-#define ANALOG_COMP_1_vect_num 8 +-#define ANALOG_COMP_1_vect _VECTOR(8) +- +-/* Analog Comparator 2 */ +-#define ANALOG_COMP_2_vect_num 9 +-#define ANALOG_COMP_2_vect _VECTOR(9) +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 10 +-#define INT0_vect _VECTOR(10) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 11 +-#define TIMER1_CAPT_vect _VECTOR(11) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 12 +-#define TIMER1_COMPA_vect _VECTOR(12) +- +-/* Timer/Counter Compare Match B */ +-#define TIMER1_COMPB_vect_num 13 +-#define TIMER1_COMPB_vect _VECTOR(13) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 15 +-#define TIMER1_OVF_vect _VECTOR(15) +- +-/* Timer/Counter0 Compare Match A */ +-#define TIMER0_COMP_A_vect_num 16 +-#define TIMER0_COMP_A_vect _VECTOR(16) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 17 +-#define TIMER0_OVF_vect _VECTOR(17) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 18 +-#define ADC_vect _VECTOR(18) +- +-/* External Interrupt Request 1 */ +-#define INT1_vect_num 19 +-#define INT1_vect _VECTOR(19) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 20 +-#define SPI_STC_vect _VECTOR(20) +- +-/* USART, Rx Complete */ +-#define USART_RX_vect_num 21 +-#define USART_RX_vect _VECTOR(21) +- +-/* USART Data Register Empty */ +-#define USART_UDRE_vect_num 22 +-#define USART_UDRE_vect _VECTOR(22) +- +-/* USART, Tx Complete */ +-#define USART_TX_vect_num 23 +-#define USART_TX_vect _VECTOR(23) +- +-/* External Interrupt Request 2 */ +-#define INT2_vect_num 24 +-#define INT2_vect _VECTOR(24) +- +-/* Watchdog Timeout Interrupt */ +-#define WDT_vect_num 25 +-#define WDT_vect _VECTOR(25) +- +-/* EEPROM Ready */ +-#define EE_READY_vect_num 26 +-#define EE_READY_vect _VECTOR(26) +- +-/* Timer Counter 0 Compare Match B */ +-#define TIMER0_COMPB_vect_num 27 +-#define TIMER0_COMPB_vect _VECTOR(27) +- +-/* External Interrupt Request 3 */ +-#define INT3_vect_num 28 +-#define INT3_vect _VECTOR(28) +- +-/* Store Program Memory Read */ +-#define SPM_READY_vect_num 31 +-#define SPM_READY_vect _VECTOR(31) +- +-#define _VECTORS_SIZE (4 * 32) +- +-/* Constants */ +- +-#define RAMEND 0x4FF +-#define XRAMSIZE 0 +-#define XRAMEND RAMEND +-#define E2END 0x1FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x3FFF +-#define SPM_PAGESIZE 128 +- +- +-/* Fuse Information */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Diasble */ +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_PSCRV (unsigned char)~_BV(4) +-#define FUSE_PSC0RB (unsigned char)~_BV(5) +-#define FUSE_PSC1RB (unsigned char)~_BV(6) +-#define FUSE_PSC2RB (unsigned char)~_BV(7) +-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x94 +-#define SIGNATURE_2 0x83 +- +- +-#endif /* _AVR_IO90PWM316_H_ */ ++/* Copyright (c) 2007, Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: io90pwm316.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* avr/io90pwm316.h - definitions for AT90PWM316 */ ++ ++#ifndef _AVR_IO90PWM316_H_ ++#define _AVR_IO90PWM316_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "io90pwm316.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* Port B Input Pins Address */ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++/* Port B Data Direction Register */ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++/* Port B Data Register */ ++#define PORTB _SFR_IO8(0x05) ++#define PB0 0 ++#define PB1 1 ++#define PB2 2 ++#define PB3 3 ++#define PB4 4 ++#define PB5 5 ++#define PB6 6 ++#define PB7 7 ++ ++/* Port C Input Pins Address */ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++#define PINC7 7 ++ ++/* Port C Data Direction Register */ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++#define DDC7 7 ++ ++/* Port C Data Register */ ++#define PORTC _SFR_IO8(0x08) ++#define PC0 0 ++#define PC1 1 ++#define PC2 2 ++#define PC3 3 ++#define PC4 4 ++#define PC5 5 ++#define PC6 6 ++#define PC7 7 ++ ++/* Port D Input Pins Address */ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++/* Port D Data Direction Register */ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++/* Port D Data Register */ ++#define PORTD _SFR_IO8(0x0B) ++#define PD0 0 ++#define PD1 1 ++#define PD2 2 ++#define PD3 3 ++#define PD4 4 ++#define PD5 5 ++#define PD6 6 ++#define PD7 7 ++ ++/* Port E Input Pins Address */ ++#define PINE _SFR_IO8(0x0C) ++#define PINE0 0 ++#define PINE1 1 ++#define PINE2 2 ++ ++/* Port E Data Direction Register */ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE0 0 ++#define DDE1 1 ++#define DDE2 2 ++ ++/* Port E Data Register */ ++#define PORTE _SFR_IO8(0x0E) ++#define PE0 0 ++#define PE1 1 ++#define PE2 2 ++ ++/* Timer/Counter 0 Interrupt Flag Register */ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 /* Overflow Flag */ ++#define OCF0A 1 /* Output Compare Flag 0A */ ++#define OCF0B 2 /* Output Compare Flag 0B */ ++ ++/* Timer/Counter1 Interrupt Flag Register */ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 /* Overflow Flag */ ++#define OCF1A 1 /* Output Compare Flag 1A*/ ++#define OCF1B 2 /* Output Compare Flag 1B*/ ++#define ICF1 5 /* Input Capture Flag 1 */ ++ ++/* General Purpose I/O Register 1 */ ++#define GPIOR1 _SFR_IO8(0x19) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++/* General Purpose I/O Register 2 */ ++#define GPIOR2 _SFR_IO8(0x1A) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++/* General Purpose I/O Register 3 */ ++#define GPIOR3 _SFR_IO8(0x1B) ++#define GPIOR30 0 ++#define GPIOR31 1 ++#define GPIOR32 2 ++#define GPIOR33 3 ++#define GPIOR34 4 ++#define GPIOR35 5 ++#define GPIOR36 6 ++#define GPIOR37 7 ++ ++/* External Interrupt Flag Register */ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++ ++/* External Interrupt Mask Register */ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 /* External Interrupt Request 0 Enable */ ++#define INT1 1 /* External Interrupt Request 1 Enable */ ++#define INT2 2 /* External Interrupt Request 2 Enable */ ++#define INT3 3 /* External Interrupt Request 3 Enable */ ++ ++/* General Purpose I/O Register 0 */ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 /* EEPROM Read Enable */ ++#define EEWE 1 /* EEPROM Write Enable */ ++#define EEMWE 2 /* EEPROM Master Write Enable */ ++#define EERIE 3 /* EEPROM Ready Interrupt Enable */ ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++/* The EEPROM Address Registers */ ++#define EEAR _SFR_IO16(0x21) ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++#define EEAR9 1 ++#define EEAR10 2 ++#define EEAR11 3 ++ ++/* 6-char sequence denoting where to find the EEPROM registers in memory space. ++ Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM ++ subroutines. ++ First two letters: EECR address. ++ Second two letters: EEDR address. ++ Last two letters: EEAR address. */ ++#define __EEPROM_REG_LOCATIONS__ 1F2021 ++ ++/* General Timer/Counter Control Register */ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR10 0 /* Prescaler Reset Timer/Counter1 and Timer/Counter0 */ ++#define ICPSEL1 6 /* Timer1 Input Capture Selection Bit */ ++#define TSM 7 /* Timer/Counter Synchronization Mode */ ++ ++/* Timer/Counter Control Register A */ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 /* Waveform Generation Mode */ ++#define WGM01 1 /* Waveform Generation Mode */ ++#define COM0B0 4 /* Compare Output Mode, Fast PWm */ ++#define COM0B1 5 /* Compare Output Mode, Fast PWm */ ++#define COM0A0 6 /* Compare Output Mode, Phase Correct PWM Mode */ ++#define COM0A1 7 /* Compare Output Mode, Phase Correct PWM Mode */ ++ ++/* Timer/Counter Control Register B */ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 /* Clock Select */ ++#define CS01 1 /* Clock Select */ ++#define CS02 2 /* Clock Select */ ++#define WGM02 3 /* Waveform Generation Mode */ ++#define FOC0B 6 /* Force Output Compare B */ ++#define FOC0A 7 /* Force Output Compare A */ ++ ++/* Timer/Counter0 Register */ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT00 0 ++#define TCNT01 1 ++#define TCNT02 2 ++#define TCNT03 3 ++#define TCNT04 4 ++#define TCNT05 5 ++#define TCNT06 6 ++#define TCNT07 7 ++ ++/* Timer/Counter0 Output Compare Register A */ ++#define OCR0A _SFR_IO8(0x27) ++#define OCR0A0 0 ++#define OCR0A1 1 ++#define OCR0A2 2 ++#define OCR0A3 3 ++#define OCR0A4 4 ++#define OCR0A5 5 ++#define OCR0A6 6 ++#define OCR0A7 7 ++ ++/* Timer/Counter0 Output Compare Register B */ ++#define OCR0B _SFR_IO8(0x28) ++#define OCR0B0 0 ++#define OCR0B1 1 ++#define OCR0B2 2 ++#define OCR0B3 3 ++#define OCR0B4 4 ++#define OCR0B5 5 ++#define OCR0B6 6 ++#define OCR0B7 7 ++ ++/* PLL Control and Status Register */ ++#define PLLCSR _SFR_IO8(0x29) ++#define PLOCK 0 /* PLL Lock Detector */ ++#define PLLE 1 /* PLL Enable */ ++#define PLLF 2 /* PLL Factor */ ++ ++/* SPI Control Register */ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 /* SPI Clock Rate Select 0 */ ++#define SPR1 1 /* SPI Clock Rate Select 1 */ ++#define CPHA 2 /* Clock Phase */ ++#define CPOL 3 /* Clock polarity */ ++#define MSTR 4 /* Master/Slave Select */ ++#define DORD 5 /* Data Order */ ++#define SPE 6 /* SPI Enable */ ++#define SPIE 7 /* SPI Interrupt Enable */ ++ ++/* SPI Status Register */ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 /* Double SPI Speed Bit */ ++#define WCOL 6 /* Write Collision Flag */ ++#define SPIF 7 /* SPI Interrupt Flag */ ++ ++/* SPI Data Register */ ++#define SPDR _SFR_IO8(0x2E) ++#define SPD0 0 ++#define SPD1 1 ++#define SPD2 2 ++#define SPD3 3 ++#define SPD4 4 ++#define SPD5 5 ++#define SPD6 6 ++#define SPD7 7 ++ ++/* Analog Comparator Status Register */ ++#define ACSR _SFR_IO8(0x30) ++#define AC0O 0 /* Analog Comparator 0 Output Bit */ ++#define AC1O 1 /* Analog Comparator 1 Output Bit */ ++#define AC2O 2 /* Analog Comparator 2 Output Bit */ ++#define AC0IF 4 /* Analog Comparator 0 Interrupt Flag Bit */ ++#define AC1IF 5 /* Analog Comparator 1 Interrupt Flag Bit */ ++#define AC2IF 6 /* Analog Comparator 2 Interrupt Flag Bit */ ++#define ACCKDIV 7 /* Analog Comparator Clock Divider */ ++ ++/* Sleep Mode Control Register */ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 /* Sleep Enable */ ++#define SM0 1 /* Sleep Mode Select bit0 */ ++#define SM1 2 /* Sleep Mode Select bit1 */ ++#define SM2 3 /* Sleep Mode Select bit2 */ ++ ++/* MCU Status Register */ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 /* Power-on reset flag */ ++#define EXTRF 1 /* External Reset Flag */ ++#define BORF 2 /* Brown-out Reset Flag */ ++#define WDRF 3 /* Watchdog Reset Flag */ ++ ++/* MCU Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 /* Interrupt Vector Change Enable */ ++#define IVSEL 1 /* Interrupt Vector Select */ ++#define PUD 4 /* Pull-up disable */ ++#define SPIPS 7 /* SPI Pin Select */ ++ ++/* Store Program Memory Control Register */ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 /* Store Program Memory Enable */ ++#define PGERS 1 /* Page Erase */ ++#define PGWRT 2 /* Page Write */ ++#define BLBSET 3 /* Boot Lock Bit Set */ ++#define RWWSRE 4 /* Read While Write section read enable */ ++#define RWWSB 6 /* Read While Write Section Busy */ ++#define SPMIE 7 /* SPM Interrupt Enable */ ++ ++/* Watchdog Timer Control Register */ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 /* Watchdog Timer Prescaler bit0 */ ++#define WDP1 1 /* Watchdog Timer Prescaler bit1 */ ++#define WDP2 2 /* Watchdog Timer Prescaler bit2 */ ++#define WDE 3 /* Watchdog Enable */ ++#define WDCE 4 /* Watchdog Change Enable */ ++#define WDP3 5 /* Watchdog Timer Prescaler bit3 */ ++#define WDIE 6 /* Watchdog Timeout Interrupt Enable */ ++#define WDIF 7 /* Watchdog Timeout Interrupt Flag */ ++ ++/* Clock Prescaler Register */ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 /* Clock Prescaler Select bit0 */ ++#define CLKPS1 1 /* Clock Prescaler Select bit1 */ ++#define CLKPS2 2 /* Clock Prescaler Select bit2 */ ++#define CLKPS3 3 /* Clock Prescaler Select bit3 */ ++#define CLKPCE 7 /* Clock Prescaler Change Enable */ ++ ++/* Power Reduction Register */ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 /* Power Reduction ADC */ ++#define PRUSART0 1 /* Power Reduction USART0 */ ++#define PRSPI 2 /* Power Reduction Serial Peripheral Interface */ ++#define PRTIM0 3 /* Power Reduction Timer/Counter0 */ ++#define PRTIM1 4 /* Power Reduction Timer/Counter1 */ ++#define PRPSC0 5 /* Power Reduction PSC0 */ ++#define PRPSC1 6 /* Power Reduction PSC1 */ ++#define PRPSC2 7 /* Power Reduction PSC2 */ ++ ++/* Oscillator Calibration Value */ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++ ++/* External Interrupt Control Register A */ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++/* Timer/Counter0 Interrupt Mask Register */ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 /* Overflow Interrupt Enable */ ++#define OCIE0A 1 /* Output Compare Match A Interrupt Enable */ ++#define OCIE0B 2 /* Output Compare Match B Interrupt Enable */ ++ ++/* Timer/Counter1 Interrupt Mask Register */ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 /* Overflow Interrupt Enable */ ++#define OCIE1A 1 /* Output Compare Match A Interrupt Enable */ ++#define OCIE1B 2 /* Output Compare Match B Interrupt Enable */ ++#define ICIE1 5 /* Input Capture Interrupt Enable */ ++ ++/* Amplifier 0 Control and Status register */ ++#define AMP0CSR _SFR_MEM8(0x76) ++#define AMP0TS0 0 ++#define AMP0TS1 1 ++#define AMP0G0 4 ++#define AMP0G1 5 ++#define AMP0IS 6 ++#define AMP0EN 7 ++ ++/* Amplifier 1 Control and Status register */ ++#define AMP1CSR _SFR_MEM8(0x77) ++#define AMP1TS0 0 ++#define AMP1TS1 1 ++#define AMP1G0 4 ++#define AMP1G1 5 ++#define AMP1IS 6 ++#define AMP1EN 7 ++ ++/* ADC Result Data Register */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++/* ADC Control and Status Register A */ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 /* ADC Prescaler Select bit0 */ ++#define ADPS1 1 /* ADC Prescaler Select bit1 */ ++#define ADPS2 2 /* ADC Prescaler Select bit2 */ ++#define ADIE 3 /* ADC Interrupt Enable */ ++#define ADIF 4 /* ADC Interrupt Flag */ ++#define ADATE 5 /* ADC Auto Trigger Enable */ ++#define ADSC 6 /* ADC Start Conversion */ ++#define ADEN 7 /* ADC Enable */ ++ ++/* ADC Control and Status Register B */ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 /* ADC Auto Trigger Source 0 */ ++#define ADTS1 1 /* ADC Auto Trigger Source 1 */ ++#define ADTS2 2 /* ADC Auto Trigger Source 2 */ ++#define ADTS3 3 /* ADC Auto Trigger Source 3 */ ++#define ADHSM 7 /* ADC High Speed Mode */ ++ ++/* ADC multiplexer Selection Register */ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 /* Analog Channel and Gain Selection bit0 */ ++#define MUX1 1 /* Analog Channel and Gain Selection bit1 */ ++#define MUX2 2 /* Analog Channel and Gain Selection bit2 */ ++#define MUX3 3 /* Analog Channel and Gain Selection bit3 */ ++#define ADLAR 5 /* Left Adjust Result */ ++#define REFS0 6 /* Reference Selection bit0 */ ++#define REFS1 7 /* Reference Selection bit1 */ ++ ++/* Digital Input Disable Register 0 */ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 /* ADC0 Digital input Disable */ ++#define ADC1D 1 /* ADC1 Digital input Disable */ ++#define ADC2D 2 /* ADC2 Digital input Disable */ ++#define ADC3D 3 /* ADC3 Digital input Disable */ ++#define ADC4D 4 /* ADC4 Digital input Disable */ ++#define ADC5D 5 /* ADC5 Digital input Disable */ ++#define ADC6D 6 /* ADC6 Digital input Disable */ ++#define ADC7D 7 /* ADC7 Digital input Disable */ ++ ++/* Digital Input Disable Register 1 */ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define ADC8D 0 /* ADC8 Digital input Disable */ ++#define ADC9D 1 /* ADC9 Digital input Disable */ ++#define ADC10D 2 /* ADC10 Digital input Disable */ ++#define AMP0ND 3 ++#define AMP0PD 4 ++#define ACMP0D 5 ++ ++/* Timer/Counter1 Control Register A */ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 /* Waveform Generation Mode */ ++#define WGM11 1 /* Waveform Generation Mode */ ++#define COM1B0 4 /* Compare Output Mode 1B, bit 0 */ ++#define COM1B1 5 /* Compare Output Mode 1B, bit 1 */ ++#define COM1A0 6 /* Comparet Ouput Mode 1A, bit 0 */ ++#define COM1A1 7 /* Comparet Ouput Mode 1A, bit 1 */ ++ ++/* Timer/Counter1 Control Register B */ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 /* Prescaler source of Timer/Counter 1 */ ++#define CS11 1 /* Prescaler source of Timer/Counter 1 */ ++#define CS12 2 /* Prescaler source of Timer/Counter 1 */ ++#define WGM12 3 /* Waveform Generation Mode */ ++#define WGM13 4 /* Waveform Generation Mode */ ++#define ICES1 6 /* Input Capture 1 Edge Select */ ++#define ICNC1 7 /* Input Capture 1 Noise Canceler */ ++ ++/* Timer/Counter1 Control Register C */ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 /* Force Output Compare for Channel B */ ++#define FOC1A 7 /* Force Output Compare for Channel A */ ++ ++/* Timer/Counter1 */ ++#define TCNT1 _SFR_MEM16(0x84) ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT10 0 ++#define TCNT11 1 ++#define TCNT12 2 ++#define TCNT13 3 ++#define TCNT14 4 ++#define TCNT15 5 ++#define TCNT16 6 ++#define TCNT17 7 ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT18 0 ++#define TCNT19 1 ++#define TCNT110 2 ++#define TCNT111 3 ++#define TCNT112 4 ++#define TCNT113 5 ++#define TCNT114 6 ++#define TCNT115 7 ++ ++/* Input Capture Register 1 */ ++#define ICR1 _SFR_MEM16(0x86) ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR17 7 ++#define ICR16 6 ++#define ICR15 5 ++#define ICR14 4 ++#define ICR13 3 ++#define ICR12 2 ++#define ICR11 1 ++#define ICR10 0 ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR115 7 ++#define ICR114 6 ++#define ICR113 5 ++#define ICR112 4 ++#define ICR111 3 ++#define ICR110 2 ++#define ICR19 1 ++#define ICR18 0 ++ ++/* Output Compare Register 1 A */ ++#define OCR1A _SFR_MEM16(0x88) ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1A0 0 ++#define OCR1A1 1 ++#define OCR1A2 2 ++#define OCR1A3 3 ++#define OCR1A4 4 ++#define OCR1A5 5 ++#define OCR1A6 6 ++#define OCR1A7 7 ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1A8 0 ++#define OCR1A9 1 ++#define OCR1A10 2 ++#define OCR1A11 3 ++#define OCR1A12 4 ++#define OCR1A13 5 ++#define OCR1A14 6 ++#define OCR1A15 7 ++ ++/* Output Compare Register 1 B */ ++#define OCR1B _SFR_MEM16(0x8A) ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1B0 0 ++#define OCR1B1 1 ++#define OCR1B2 2 ++#define OCR1B3 3 ++#define OCR1B4 4 ++#define OCR1B5 5 ++#define OCR1B6 6 ++#define OCR1B7 7 ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1B8 0 ++#define OCR1B9 1 ++#define OCR1B10 2 ++#define OCR1B11 3 ++#define OCR1B12 4 ++#define OCR1B13 5 ++#define OCR1B14 6 ++#define OCR1B15 7 ++ ++/* PSC0 Interrupt Flag Register */ ++#define PIFR0 _SFR_MEM8(0xA0) ++#define PEOP0 0 /* End Of PSC0 Interrupt */ ++#define PRN00 1 /* PSC0 Ramp Number bit0 */ ++#define PRN01 2 /* PSC0 Ramp Number bit1 */ ++#define PEV0A 3 /* PSC0 External Event A Interrupt */ ++#define PEV0B 4 /* PSC0 External Event B Interrupt */ ++#define PSEI0 5 /* PSC0 Synchro Error Interrupt */ ++#define POAC0A 6 /* PSC0 Output A Activity */ ++#define POAC0B 7 /* PSC0 Output B Activity */ ++ ++/* PSC0 Interrupt Mask Register */ ++#define PIM0 _SFR_MEM8(0xA1) ++#define PEOPE0 0 /* PSC0 End Of Cycle Interrupt Enable */ ++#define PEVE0A 3 /* PSC0 External Event A Interrupt Enable */ ++#define PEVE0B 4 /* PSC0 External Event B Interrupt Enable */ ++#define PSEIE0 5 /* PSC0 Synchro Error Interrupt Enable */ ++ ++/* PSC1 Interrupt Flag Register */ ++#define PIFR1 _SFR_MEM8(0xA2) ++#define PEOP1 0 ++#define PRN10 1 ++#define PRN11 2 ++#define PEV1A 3 ++#define PEV1B 4 ++#define PSEI1 5 ++#define POAC1A 6 ++#define POAC1B 7 ++ ++/* PSC1 Interrupt Mask Register */ ++#define PIM1 _SFR_MEM8(0xA3) ++ ++/* PSC2 Interrupt Flag Register */ ++#define PIFR2 _SFR_MEM8(0xA4) ++#define PEOP2 0 /* End Of PSC2 Interrupt */ ++#define PRN20 1 /* PSC2 Ramp Number bit0 */ ++#define PRN21 2 /* PSC2 Ramp Number bit1 */ ++#define PEV2A 3 /* PSC2 External Event A Interrupt */ ++#define PEV2B 4 /* PSC2 External Event B Interrupt */ ++#define PSEI2 5 /* PSC2 Synchro Error Interrupt */ ++#define POAC2A 6 /* PSC2 Output A Activity */ ++#define POAC2B 7 /* PSC2 Output B Activity */ ++ ++/* PSC2 Interrupt Mask Register */ ++#define PIM2 _SFR_MEM8(0xA5) ++#define PEOPE2 0 /* PSC2 End Of Cycle Interrupt Enable */ ++#define PEVE2A 3 /* PSC2 External Event A Interrupt Enable */ ++#define PEVE2B 4 /* PSC2 External Event B Interrupt Enable */ ++#define PSEIE2 5 /* PSC2 Synchro Error Interrupt Enable */ ++ ++/* Digital to Analog Conversion Control Register */ ++#define DACON _SFR_MEM8(0xAA) ++#define DAEN 0 /* Digital to Analog Enable bit */ ++#define DAOE 1 /* Digital to Analog Output Enable bit */ ++#define DALA 2 /* Digital to Analog Left Adjust */ ++#define DATS0 4 /* DAC Trigger Selection bit0 */ ++#define DATS1 5 /* DAC Trigger Selection bit1 */ ++#define DATS2 6 /* DAC Trigger Selection bit2 */ ++#define DAATE 7 /* DAC Auto Trigger Enable bit */ ++ ++/* Digital to Analog Converter input Register */ ++#define DAC _SFR_MEM16(0xAB) ++#define DACL _SFR_MEM8(0xAB) ++#define DACH _SFR_MEM8(0xAC) ++ ++/* Analog Comparator 0 Control Register */ ++#define AC0CON _SFR_MEM8(0xAD) ++#define AC0M0 0 /* Analog Comparator 0 Multiplexer register bit0 */ ++#define AC0M1 1 /* Analog Comparator 0 Multiplexer register bit1 */ ++#define AC0M2 2 /* Analog Comparator 0 Multiplexer register bit2 */ ++#define AC0IS0 4 /* Analog Comparator 0 Interrupt Select bit0 */ ++#define AC0IS1 5 /* Analog Comparator 0 Interrupt Select bit1 */ ++#define AC0IE 6 /* Analog Comparator 0 Interrupt Enable bit */ ++#define AC0EN 7 /* Analog Comparator 0 Enable Bit */ ++ ++/* Analog Comparator 1 Control Register */ ++#define AC1CON _SFR_MEM8(0xAE) ++#define AC1M0 0 /* Analog Comparator 1 Multiplexer register bit0 */ ++#define AC1M1 1 /* Analog Comparator 1 Multiplexer register bit1 */ ++#define AC1M2 2 /* Analog Comparator 1 Multiplexer register bit2 */ ++#define AC1ICE 3 /* Analog Comparator 1 Interrupt Capture Enable bit */ ++#define AC1IS0 4 /* Analog Comparator 1 Interrupt Select bit0 */ ++#define AC1IS1 5 /* Analog Comparator 1 Interrupt Select bit1 */ ++#define AC1IE 6 /* Analog Comparator 1 Interrupt Enable bit */ ++#define AC1EN 7 /* Analog Comparator 1 Enable Bit */ ++ ++/* Analog Comparator 2 Control Register */ ++#define AC2CON _SFR_MEM8(0xAF) ++#define AC2M0 0 /* Analog Comparator 2 Multiplexer register bit0 */ ++#define AC2M1 1 /* Analog Comparator 2 Multiplexer register bit1 */ ++#define AC2M2 2 /* Analog Comparator 2 Multiplexer register bit2 */ ++#define AC2IS0 4 /* Analog Comparator 2 Interrupt Select bit0 */ ++#define AC2IS1 5 /* Analog Comparator 2 Interrupt Select bit1 */ ++#define AC2IE 6 /* Analog Comparator 2 Interrupt Enable bit */ ++#define AC2EN 7 /* Analog Comparator 2 Enable Bit */ ++ ++/* USART Control and Status Register A */ ++#define UCSRA _SFR_MEM8(0xC0) ++#define MPCM 0 /* Multi-processor Communication Mode */ ++#define U2X 1 /* Double the USART Transmission Speed */ ++#define UPE 2 /* USART Parity Error */ ++#define DOR 3 /* Data OverRun */ ++#define FE 4 /* Frame Error */ ++#define UDRE 5 /* USART Data Register Empty */ ++#define TXC 6 /* USART Transmit Complete */ ++#define RXC 7 /* USART Receive Complete */ ++ ++/* USART Control and Status Register B */ ++#define UCSRB _SFR_MEM8(0xC1) ++#define TXB8 0 /* Transmit Data Bit 8 */ ++#define RXB8 1 /* Receive Data Bit 8 */ ++#define UCSZ2 2 /* Character Size */ ++#define TXEN 3 /* Transmitter Enable */ ++#define RXEN 4 /* Receiver Enable */ ++#define UDRIE 5 /* USART Data Register Empty Interrupt Enable */ ++#define TXCIE 6 /* TX Complete Interrupt Enable */ ++#define RXCIE 7 /* RX Complete Interrupt Enable */ ++ ++/* USART Control and Status Register C */ ++#define UCSRC _SFR_MEM8(0xC2) ++#define UCPOL 0 /* Clock Polarity */ ++#define UCSZ0 1 /* Character Size bit0 */ ++#define UCSZ1 2 /* Character Size bit1 */ ++#define USBS 3 /* Stop Bit Select */ ++#define UPM0 4 /* Parity Mode bit0 */ ++#define UPM1 5 /* Parity Mode bit1 */ ++#define UMSEL 6 /* USART Mode Select */ ++ ++/* USART Baud Rate Register */ ++#define UBRR _SFR_MEM16(0xC4) ++#define UBRRL _SFR_MEM8(0xC4) ++#define UBRRH _SFR_MEM8(0xC5) ++ ++/* USART I/O Data Register */ ++#define UDR _SFR_MEM8(0xC6) ++ ++/* EUSART Control and Status Register A */ ++#define EUCSRA _SFR_MEM8(0xC8) ++#define URxS0 0 /* EUSART Receive Character Size bit0 */ ++#define URxS1 1 /* EUSART Receive Character Size bit1 */ ++#define URxS2 2 /* EUSART Receive Character Size bit2 */ ++#define URxS3 3 /* EUSART Receive Character Size bit3 */ ++#define UTxS0 4 /* EUSART Transmit Character Size bit0 */ ++#define UTxS1 5 /* EUSART Transmit Character Size bit1 */ ++#define UTxS2 6 /* EUSART Transmit Character Size bit2 */ ++#define UTxS3 7 /* EUSART Transmit Character Size bit3 */ ++ ++/* EUSART Control and Status Register B */ ++#define EUCSRB _SFR_MEM8(0xC9) ++#define BODR 0 /* Bit Order */ ++#define EMCH 1 /* Manchester mode */ ++#define EUSBS 3 /* EUSBS Enable Bit */ ++#define EUSART 4 /* EUSART Enable Bit */ ++ ++/* EUSART Control and Status Register C */ ++#define EUCSRC _SFR_MEM8(0xCA) ++#define STP0 0 /* Stop bits values bit0 */ ++#define STP1 1 /* Stop bits values bit1 */ ++#define F1617 2 ++#define FEM 3 /* Frame Error Manchester */ ++ ++/* Manchester receiver Baud Rate Registers */ ++#define MUBRR _SFR_MEM16(0xCC) ++#define MUBRRL _SFR_MEM8(0xCC) ++#define MUBRRH _SFR_MEM8(0xCD) ++ ++/* EUSART I/O Data Register */ ++#define EUDR _SFR_MEM8(0xCE) ++ ++/* PSC 0 Synchro and Output Configuration */ ++#define PSOC0 _SFR_MEM8(0xD0) ++#define POEN0A 0 /* PSC 0 OUT Part A Output Enable */ ++#define POEN0B 2 /* PSC 0 OUT Part B Output Enable */ ++#define PSYNC00 4 /* Synchronization Out for ADC Selection bit0 */ ++#define PSYNC01 5 /* Synchronization Out for ADC Selection bit1 */ ++ ++/* Output Compare SA Registers */ ++#define OCR0SA _SFR_MEM16(0xD2) ++#define OCR0SAL _SFR_MEM8(0xD2) ++#define OCR0SAH _SFR_MEM8(0xD3) ++ ++/* Output Compare RA Registers */ ++#define OCR0RA _SFR_MEM16(0xD4) ++#define OCR0RAL _SFR_MEM8(0xD4) ++#define OCR0RAH _SFR_MEM8(0xD5) ++ ++/* Output Compare SB Registers */ ++#define OCR0SB _SFR_MEM16(0xD6) ++#define OCR0SBL _SFR_MEM8(0xD6) ++#define OCR0SBH _SFR_MEM8(0xD7) ++ ++/* Output Compare RB Registers */ ++#define OCR0RB _SFR_MEM16(0xD8) ++#define OCR0RBL _SFR_MEM8(0xD8) ++#define OCR0RBH _SFR_MEM8(0xD9) ++ ++/* PSC 0 Configuration Register */ ++#define PCNF0 _SFR_MEM8(0xDA) ++#define PCLKSEL0 1 /* PSC 0 Input Clock Select */ ++#define POP0 2 /* PSC 0 Output Polarity */ ++#define PMODE00 3 /* PSC 0 Mode bit0 */ ++#define PMODE01 4 /* PSC 0 Mode bit1 */ ++#define PLOCK0 5 /* PSC 0 Lock */ ++#define PALOCK0 6 /* PSC 0 Autolock */ ++#define PFIFTY0 7 /* PSC 0 Fifty */ ++ ++/* PSC 0 Control Register */ ++#define PCTL0 _SFR_MEM8(0xDB) ++#define PRUN0 0 /* PSC 0 Run */ ++#define PCCYC0 1 /* PSC 0 Complete Cycle */ ++#define PARUN0 2 /* PSC 0 Autorun */ ++#define PAOC0A 3 /* PSC 0 Asynchronous Output Control A */ ++#define PAOC0B 4 /* PSC 0 Asynchronous Output Control B */ ++#define PBFM0 5 /* Balance Flank Width Modulation */ ++#define PPRE00 6 /* PSC 0 Prescaler Select bit0 */ ++#define PPRE01 7 /* PSC 0 Prescaler Select bit1 */ ++ ++/* PSC 0 Input A Control Register */ ++#define PFRC0A _SFR_MEM8(0xDC) ++#define PRFM0A0 0 /* PSC 0 Fault Mode bit0 */ ++#define PRFM0A1 1 /* PSC 0 Fault Mode bit1 */ ++#define PRFM0A2 2 /* PSC 0 Fault Mode bit2 */ ++#define PRFM0A3 3 /* PSC 0 Fault Mode bit3 */ ++#define PFLTE0A 4 /* PSC 0 Filter Enable on Input Part A */ ++#define PELEV0A 5 /* PSC 0 Edge Level Selector of Input Part A */ ++#define PISEL0A 6 /* PSC 0 Input Select for Part A */ ++#define PCAE0A 7 /* PSC 0 Capture Enable Input Part A */ ++ ++/* PSC 0 Input B Control Register */ ++#define PFRC0B _SFR_MEM8(0xDD) ++#define PRFM0B0 0 /* PSC 0 Fault Mode bit0 */ ++#define PRFM0B1 1 /* PSC 0 Fault Mode bit1 */ ++#define PRFM0B2 2 /* PSC 0 Fault Mode bit2 */ ++#define PRFM0B3 3 /* PSC 0 Fault Mode bit3 */ ++#define PFLTE0B 4 /* PSC 0 Filter Enable on Input Part B */ ++#define PELEV0B 5 /* PSC 0 Edge Level Selector of Input Part B */ ++#define PISEL0B 6 /* PSC 0 Input Select for Part B */ ++#define PCAE0B 7 /* PSC 0 Capture Enable Input Part B */ ++ ++/* PSC 0 Input Capture Registers */ ++#define PICR0 _SFR_MEM16(0xDE) ++#define PICR0L _SFR_MEM8(0xDE) ++#define PICR0H _SFR_MEM8(0xDF) ++#define PCST0 7 /* PSC Capture Software Trig bit */ ++ ++/* PSC 1 Synchro and Output Configuration */ ++#define PSOC1 _SFR_MEM8(0xE0) ++#define POEN1A 0 ++#define POEN1B 2 ++#define PSYNC1_0 4 ++#define PSYNC1_1 5 ++ ++/* Output Compare SA Registers */ ++#define OCR1SA _SFR_MEM16(0xE2) ++#define OCR1SAL _SFR_MEM8(0xE2) ++#define OCR1SAH _SFR_MEM8(0xE3) ++ ++/* Output Compare RA Registers */ ++#define OCR1RA _SFR_MEM16(0xE4) ++#define OCR1RAL _SFR_MEM8(0xE4) ++#define OCR1RAH _SFR_MEM8(0xE5) ++ ++/* Output Compare SB Registers */ ++#define OCR1SB _SFR_MEM16(0xE6) ++#define OCR1SBL _SFR_MEM8(0xE6) ++#define OCR1SBH _SFR_MEM8(0xE7) ++ ++/* Output Compare RB Registers */ ++#define OCR1RB _SFR_MEM16(0xE8) ++#define OCR1RBL _SFR_MEM8(0xE8) ++#define OCR1RBH _SFR_MEM8(0xE9) ++ ++/* PSC 1 Configuration Register */ ++#define PCNF1 _SFR_MEM8(0xEA) ++#define PCLKSEL1 1 ++#define POP1 2 ++#define PMODE10 3 ++#define PMODE11 4 ++#define PLOCK1 5 ++#define PALOCK1 6 ++#define PFIFTY1 7 ++ ++/* PSC 1 Control Register */ ++#define PCTL1 _SFR_MEM8(0xEB) ++#define PRUN1 0 ++#define PCCYC1 1 ++#define PARUN1 2 ++#define PAOC1A 3 ++#define PAOC1B 4 ++#define PBFM1 5 ++#define PPRE10 6 ++#define PPRE11 7 ++ ++/* PSC 1 Input A Control Register */ ++#define PFRC1A _SFR_MEM8(0xEC) ++#define PRFM1A0 0 ++#define PRFM1A1 1 ++#define PRFM1A2 2 ++#define PRFM1A3 3 ++#define PFLTE1A 4 ++#define PELEV1A 5 ++#define PISEL1A 6 ++#define PCAE1A 7 ++ ++/* PSC 1 Input B Control Register */ ++#define PFRC1B _SFR_MEM8(0xED) ++#define PRFM1B0 0 ++#define PRFM1B1 1 ++#define PRFM1B2 2 ++#define PRFM1B3 3 ++#define PFLTE1B 4 ++#define PELEV1B 5 ++#define PISEL1B 6 ++#define PCAE1B 7 ++ ++/* PSC 1 Input Capture Registers */ ++#define PICR1 _SFR_MEM16(0xEE) ++#define PICR1L _SFR_MEM8(0xEE) ++#define PICR1H _SFR_MEM8(0xEF) ++ ++/* PSC 2 Synchro and Output Configuration */ ++#define PSOC2 _SFR_MEM8(0xF0) ++#define POEN2A 0 /* PSC 2 OUT Part A Output Enable */ ++#define POEN2C 1 /* PSCOUT22 Output Enable */ ++#define POEN2B 2 /* PSC 2 OUT Part B Output Enable */ ++#define POEN2D 3 /* PSCOUT23 Output Enable */ ++#define PSYNC20 4 /* Synchronization Out for ADC Selection bit0 */ ++#define PSYNC21 5 /* Synchronization Out for ADC Selection bit1 */ ++#define POS22 6 /* PSCOUT22 Selection */ ++#define POS23 7 /* PSCOUT23 Selection */ ++ ++/* PSC 2 Output Matrix */ ++#define POM2 _SFR_MEM8(0xF1) ++#define POMV2A0 0 /* Output Matrix Output A Ramp 0 */ ++#define POMV2A1 1 /* Output Matrix Output A Ramp 1 */ ++#define POMV2A2 2 /* Output Matrix Output A Ramp 2 */ ++#define POMV2A3 3 /* Output Matrix Output A Ramp 3 */ ++#define POMV2B0 4 /* Output Matrix Output B Ramp 0 */ ++#define POMV2B1 5 /* Output Matrix Output B Ramp 1 */ ++#define POMV2B2 6 /* Output Matrix Output B Ramp 2 */ ++#define POMV2B3 7 /* Output Matrix Output B Ramp 3 */ ++ ++/* Output Compare SA Registers */ ++#define OCR2SA _SFR_MEM16(0xF2) ++#define OCR2SAL _SFR_MEM8(0xF2) ++#define OCR2SAH _SFR_MEM8(0xF3) ++ ++/* Output Compare RA Registers */ ++#define OCR2RA _SFR_MEM16(0xF4) ++#define OCR2RAL _SFR_MEM8(0xF4) ++#define OCR2RAH _SFR_MEM8(0xF5) ++ ++/* Output Compare SB Registers */ ++#define OCR2SB _SFR_MEM16(0xF6) ++#define OCR2SBL _SFR_MEM8(0xF6) ++#define OCR2SBH _SFR_MEM8(0xF7) ++ ++/* Output Compare RB Registers */ ++#define OCR2RB _SFR_MEM16(0xF8) ++#define OCR2RBL _SFR_MEM8(0xF8) ++#define OCR2RBH _SFR_MEM8(0xF9) ++ ++/* PSC 2 Configuration Register */ ++#define PCNF2 _SFR_MEM8(0xFA) ++#define POME2 0 /* PSC 2 Output Matrix Enable */ ++#define PCLKSEL2 1 /* PSC 2 Input Clock Select */ ++#define POP2 2 /* PSC 2 Output Polarity */ ++#define PMODE20 3 /* PSC 2 Mode bit0 */ ++#define PMODE21 4 /* PSC 2 Mode bit1 */ ++#define PLOCK2 5 /* PSC 2 Lock */ ++#define PALOCK2 6 /* PSC 2 Autolock */ ++#define PFIFTY2 7 /* PSC 2 Fifty */ ++ ++/* PSC 2 Control Register */ ++#define PCTL2 _SFR_MEM8(0xFB) ++#define PRUN2 0 /* PSC 2 Run */ ++#define PCCYC2 1 /* PSC 2 Complete Cycle */ ++#define PARUN2 2 /* PSC 2 Autorun */ ++#define PAOC2A 3 /* PSC 2 Asynchronous Output Control A */ ++#define PAOC2B 4 /* PSC 2 Asynchronous Output Control B */ ++#define PBFM2 5 /* Balance Flank Width Modulation */ ++#define PPRE20 6 /* PSC 2 Prescaler Select bit0 */ ++#define PPRE21 7 /* PSC 2 Prescaler Select bit1 */ ++ ++/* PSC 2 Input A Control Register */ ++#define PFRC2A _SFR_MEM8(0xFC) ++#define PRFM2A0 0 /* PSC 2 Fault Mode bit0 */ ++#define PRFM2A1 1 /* PSC 2 Fault Mode bit1 */ ++#define PRFM2A2 2 /* PSC 2 Fault Mode bit2 */ ++#define PRFM2A3 3 /* PSC 2 Fault Mode bit3 */ ++#define PFLTE2A 4 /* PSC 2 Filter Enable on Input Part A */ ++#define PELEV2A 5 /* PSC 2 Edge Level Selector of Input Part A */ ++#define PISEL2A 6 /* PSC 2 Input Select for Part A */ ++#define PCAE2A 7 /* PSC 2 Capture Enable Input Part A */ ++ ++/* PSC 2 Input B Control Register */ ++#define PFRC2B _SFR_MEM8(0xFD) ++#define PRFM2B0 0 /* PSC 2 Fault Mode bit0 */ ++#define PRFM2B1 1 /* PSC 2 Fault Mode bit1 */ ++#define PRFM2B2 2 /* PSC 2 Fault Mode bit2 */ ++#define PRFM2B3 3 /* PSC 2 Fault Mode bit3 */ ++#define PFLTE2B 4 /* PSC 2 Filter Enable on Input Part B */ ++#define PELEV2B 5 /* PSC 2 Edge Level Selector of Input Part B */ ++#define PISEL2B 6 /* PSC 2 Input Select for Part B */ ++#define PCAE2B 7 /* PSC 2 Capture Enable Input Part B */ ++ ++/* PSC 2 Input Capture Registers */ ++#define PICR2 _SFR_MEM16(0xFE) ++#define PICR2L _SFR_MEM8(0xFE) ++#define PICR2H _SFR_MEM8(0xFF) ++#define PCST2 7 /* PSC Capture Software Trig bit */ ++ ++ ++/* Interrupt Vectors */ ++/* Interrupt 0 is the reset vector. */ ++ ++/* PSC2 Capture Event */ ++#define PSC2_CAPT_vect_num 1 ++#define PSC2_CAPT_vect _VECTOR(1) ++ ++/* PSC2 End Cycle */ ++#define PSC2_EC_vect_num 2 ++#define PSC2_EC_vect _VECTOR(2) ++ ++/* PSC1 Capture Event */ ++#define PSC1_CAPT_vect_num 3 ++#define PSC1_CAPT_vect _VECTOR(3) ++ ++/* PSC1 End Cycle */ ++#define PSC1_EC_vect_num 4 ++#define PSC1_EC_vect _VECTOR(4) ++ ++/* PSC0 Capture Event */ ++#define PSC0_CAPT_vect_num 5 ++#define PSC0_CAPT_vect _VECTOR(5) ++ ++/* PSC0 End Cycle */ ++#define PSC0_EC_vect_num 6 ++#define PSC0_EC_vect _VECTOR(6) ++ ++/* Analog Comparator 0 */ ++#define ANALOG_COMP_0_vect_num 7 ++#define ANALOG_COMP_0_vect _VECTOR(7) ++ ++/* Analog Comparator 1 */ ++#define ANALOG_COMP_1_vect_num 8 ++#define ANALOG_COMP_1_vect _VECTOR(8) ++ ++/* Analog Comparator 2 */ ++#define ANALOG_COMP_2_vect_num 9 ++#define ANALOG_COMP_2_vect _VECTOR(9) ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 10 ++#define INT0_vect _VECTOR(10) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 11 ++#define TIMER1_CAPT_vect _VECTOR(11) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 12 ++#define TIMER1_COMPA_vect _VECTOR(12) ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect_num 13 ++#define TIMER1_COMPB_vect _VECTOR(13) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 15 ++#define TIMER1_OVF_vect _VECTOR(15) ++ ++/* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMP_A_vect_num 16 ++#define TIMER0_COMP_A_vect _VECTOR(16) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 17 ++#define TIMER0_OVF_vect _VECTOR(17) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 18 ++#define ADC_vect _VECTOR(18) ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect_num 19 ++#define INT1_vect _VECTOR(19) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 20 ++#define SPI_STC_vect _VECTOR(20) ++ ++/* USART, Rx Complete */ ++#define USART_RX_vect_num 21 ++#define USART_RX_vect _VECTOR(21) ++ ++/* USART Data Register Empty */ ++#define USART_UDRE_vect_num 22 ++#define USART_UDRE_vect _VECTOR(22) ++ ++/* USART, Tx Complete */ ++#define USART_TX_vect_num 23 ++#define USART_TX_vect _VECTOR(23) ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect_num 24 ++#define INT2_vect _VECTOR(24) ++ ++/* Watchdog Timeout Interrupt */ ++#define WDT_vect_num 25 ++#define WDT_vect _VECTOR(25) ++ ++/* EEPROM Ready */ ++#define EE_READY_vect_num 26 ++#define EE_READY_vect _VECTOR(26) ++ ++/* Timer Counter 0 Compare Match B */ ++#define TIMER0_COMPB_vect_num 27 ++#define TIMER0_COMPB_vect _VECTOR(27) ++ ++/* External Interrupt Request 3 */ ++#define INT3_vect_num 28 ++#define INT3_vect _VECTOR(28) ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect_num 31 ++#define SPM_READY_vect _VECTOR(31) ++ ++#define _VECTORS_SIZE (4 * 32) ++ ++/* Constants */ ++ ++#define RAMSTART 0x100 ++#define RAMEND 0x4FF ++#define XRAMSIZE 0 ++#define XRAMEND RAMEND ++#define E2END 0x1FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x3FFF ++#define SPM_PAGESIZE 128 ++ ++ ++/* Fuse Information */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Diasble */ ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_PSCRV (unsigned char)~_BV(4) ++#define FUSE_PSC0RB (unsigned char)~_BV(5) ++#define FUSE_PSC1RB (unsigned char)~_BV(6) ++#define FUSE_PSC2RB (unsigned char)~_BV(7) ++#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x83 ++ ++ ++#endif /* _AVR_IO90PWM316_H_ */ +diff --git a/include/avr/io90pwm3b.h b/include/avr/io90pwm3b.h +index 76cdaef..5d318e7 100644 +--- a/include/avr/io90pwm3b.h ++++ b/include/avr/io90pwm3b.h +@@ -1,1451 +1,1452 @@ +-/* Copyright (c) 2007 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. +-*/ +- +-/* $Id: io90pwm3b.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* avr/io90pwm3b.h - definitions for AT90PWM3B */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "io90pwm3b.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_IO90PWM3B_H_ +-#define _AVR_IO90PWM3B_H_ 1 +- +-/* Registers and associated bit numbers */ +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +-#define PINC7 7 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC3 3 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +-#define DDC7 7 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC3 3 +-#define PORTC4 4 +-#define PORTC5 5 +-#define PORTC6 6 +-#define PORTC7 7 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define PINE _SFR_IO8(0x0C) +-#define PINE0 0 +-#define PINE1 1 +-#define PINE2 2 +- +-#define DDRE _SFR_IO8(0x0D) +-#define DDE0 0 +-#define DDE1 1 +-#define DDE2 2 +- +-#define PORTE _SFR_IO8(0x0E) +-#define PORTE0 0 +-#define PORTE1 1 +-#define PORTE2 2 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define GPIOR1 _SFR_IO8(0x19) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x1A) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define GPIOR3 _SFR_IO8(0x1B) +-#define GPIOR30 0 +-#define GPIOR31 1 +-#define GPIOR32 2 +-#define GPIOR33 3 +-#define GPIOR34 4 +-#define GPIOR35 5 +-#define GPIOR36 6 +-#define GPIOR37 7 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +-#define INTF2 2 +-#define INTF3 3 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +-#define INT2 2 +-#define INT3 3 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEWE 1 +-#define EEMWE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEARL0 0 +-#define EEARL1 1 +-#define EEARL2 2 +-#define EEARL3 3 +-#define EEARL4 4 +-#define EEARL5 5 +-#define EEARL6 6 +-#define EEARL7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +-#define EEAR9 1 +-#define EEAR10 2 +-#define EEAR11 3 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSR10 0 +-#define PSRSYNC 0 +-#define ICPSEL1 2 +-#define TSM 3 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define OCR0A _SFR_IO8(0x27) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define OCR0B _SFR_IO8(0x28) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define OCR0_0 0 /* Deprecated */ +-#define OCR0_1 1 /* Deprecated */ +-#define OCR0_2 2 /* Deprecated */ +-#define OCR0_3 3 /* Deprecated */ +-#define OCR0_4 4 /* Deprecated */ +-#define OCR0_5 5 /* Deprecated */ +-#define OCR0_6 6 /* Deprecated */ +-#define OCR0_7 7 /* Deprecated */ +- +-#define PLLCSR _SFR_IO8(0x29) +-#define PLOCK 0 +-#define PLLE 1 +-#define PLLF 2 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define ACSR _SFR_IO8(0x30) +-#define AC0O 0 +-#define AC1O 1 +-#define AC2O 2 +-#define AC0IF 4 +-#define AC1IF 5 +-#define AC2IF 6 +-#define ACCKDIV 7 +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define SPIPS 7 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM0 3 +-#define PRTIM1 4 +-#define PRPSC0 5 +-#define PRPSC1 6 +-#define PRPSC2 7 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define ISC20 4 +-#define ISC21 5 +-#define ISC30 6 +-#define ISC31 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define AMP0CSR _SFR_MEM8(0x76) +-#define AMP0TS0 0 +-#define AMP0TS1 1 +-#define AMP0G0 4 +-#define AMP0G1 5 +-#define AMP0IS 6 +-#define AMP0EN 7 +- +-#define AMP1CSR _SFR_MEM8(0x77) +-#define AMP1TS0 0 +-#define AMP1TS1 1 +-#define AMP1G0 4 +-#define AMP1G1 5 +-#define AMP1IS 6 +-#define AMP1EN 7 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +- +-#define ADCL _SFR_MEM8(0x78) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_MEM8(0x79) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ADTS3 3 +-#define ADASCR 4 +-#define ADHSM 7 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define ADC8D 0 +-#define ADC9D 1 +-#define ADC10D 2 +-#define AMP0ND 3 +-#define AMP0PD 4 +-#define ACMP0D 5 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define PIFR0 _SFR_MEM8(0xA0) +-#define PEOP0 0 +-#define PRN00 1 +-#define PRN01 2 +-#define PEV0A 3 +-#define PEV0B 4 +-#define PSEI0 5 +-#define POAC0A 6 +-#define POAC0B 7 +- +-#define PIM0 _SFR_MEM8(0xA1) +-#define PEOPE0 0 +-#define PEVE0A 3 +-#define PEVE0B 4 +-#define PSEIE0 5 +- +-#define PIFR1 _SFR_MEM8(0xA2) +-#define PEOP1 0 +-#define PRN10 1 +-#define PRN11 2 +-#define PEV1A 3 +-#define PEV1B 4 +-#define PSEI1 5 +-#define POAC1A 6 +-#define POAC1B 7 +- +-#define PIM1 _SFR_MEM8(0xA3) +-#define PEOPE1 0 +-#define PEVE1A 3 +-#define PEVE1B 4 +-#define PSEIE1 5 +- +-#define PIFR2 _SFR_MEM8(0xA4) +-#define PEOP2 0 +-#define PRN20 1 +-#define PRN21 2 +-#define PEV2A 3 +-#define PEV2B 4 +-#define PSEI2 5 +-#define POAC2A 6 +-#define POAC2B 7 +- +-#define PIM2 _SFR_MEM8(0xA5) +-#define PEOPE2 0 +-#define PEVE2A 3 +-#define PEVE2B 4 +-#define PSEIE2 5 +- +-#define DACON _SFR_MEM8(0xAA) +-#define DAEN 0 +-#define DAOE 1 +-#define DALA 2 +-#define DATS0 4 +-#define DATS1 5 +-#define DATS2 6 +-#define DAATE 7 +- +-#define DAC _SFR_MEM16(0xAB) +- +-#define DACL _SFR_MEM8(0xAB) +-#define DACL0 0 +-#define DACL1 1 +-#define DACL2 2 +-#define DACL3 3 +-#define DACL4 4 +-#define DACL5 5 +-#define DACL6 6 +-#define DACL7 7 +- +-#define DACH _SFR_MEM8(0xAC) +-#define DACH0 0 +-#define DACH1 1 +-#define DACH2 2 +-#define DACH3 3 +-#define DACH4 4 +-#define DACH5 5 +-#define DACH6 6 +-#define DACH7 7 +- +-#define AC0CON _SFR_MEM8(0xAD) +-#define AC0M0 0 +-#define AC0M1 1 +-#define AC0M2 2 +-#define AC0IS0 4 +-#define AC0IS1 5 +-#define AC0IE 6 +-#define AC0EN 7 +- +-#define AC1CON _SFR_MEM8(0xAE) +-#define AC1M0 0 +-#define AC1M1 1 +-#define AC1M2 2 +-#define AC1ICE 3 +-#define AC1IS0 4 +-#define AC1IS1 5 +-#define AC1IE 6 +-#define AC1EN 7 +- +-#define AC2CON _SFR_MEM8(0xAF) +-#define AC2M0 0 +-#define AC2M1 1 +-#define AC2M2 2 +-#define AC2IS0 4 +-#define AC2IS1 5 +-#define AC2IE 6 +-#define AC2EN 7 +- +-#define UCSRA _SFR_MEM8(0xC0) +-#define MPCM 0 +-#define U2X 1 +-#define UPE 2 +-#define DOR 3 +-#define FE 4 +-#define UDRE 5 +-#define TXC 6 +-#define RXC 7 +- +-#define UCSRB _SFR_MEM8(0xC1) +-#define TXB8 0 +-#define RXB8 1 +-#define UCSZ2 2 +-#define TXEN 3 +-#define RXEN 4 +-#define UDRIE 5 +-#define TXCIE 6 +-#define RXCIE 7 +- +-#define UCSRC _SFR_MEM8(0xC2) +-#define UCPOL 0 +-#define UCSZ0 1 +-#define UCSZ1 2 +-#define USBS 3 +-#define UPM0 4 +-#define UPM1 5 +-#define UMSEL0 6 +- +-#define UBRR _SFR_MEM16(0xC4) +- +-#define UBRRL _SFR_MEM8(0xC4) +-#define UBRR0 0 +-#define UBRR1 1 +-#define UBRR2 2 +-#define UBRR3 3 +-#define UBRR4 4 +-#define UBRR5 5 +-#define UBRR6 6 +-#define UBRR7 7 +- +-#define UBRRH _SFR_MEM8(0xC5) +-#define UBRR8 0 +-#define UBRR9 1 +-#define UBRR10 2 +-#define UBRR11 3 +- +-#define UDR _SFR_MEM8(0xC6) +-#define UDR0 0 +-#define UDR1 1 +-#define UDR2 2 +-#define UDR3 3 +-#define UDR4 4 +-#define UDR5 5 +-#define UDR6 6 +-#define UDR7 7 +- +-#define EUCSRA _SFR_MEM8(0xC8) +-#define URxS0 0 +-#define URxS1 1 +-#define URxS2 2 +-#define URxS3 3 +-#define UTxS0 4 +-#define UTxS1 5 +-#define UTxS2 6 +-#define UTxS3 7 +- +-#define EUCSRB _SFR_MEM8(0xC9) +-#define BODR 0 +-#define EMCH 1 +-#define EUSBS 3 +-#define EUSART 4 +- +-#define EUCSRC _SFR_MEM8(0xCA) +-#define STP0 0 +-#define STP1 1 +-#define F1617 2 +-#define FEM 3 +- +-#define MUBRR _SFR_MEM16(0xCC) +- +-#define MUBRRL _SFR_MEM8(0xCC) +-#define MUBRR0 0 +-#define MUBRR1 1 +-#define MUBRR2 2 +-#define MUBRR3 3 +-#define MUBRR4 4 +-#define MUBRR5 5 +-#define MUBRR6 6 +-#define MUBRR7 7 +- +-#define MUBRRH _SFR_MEM8(0xCD) +-#define MUBRR8 0 +-#define MUBRR9 1 +-#define MUBRR10 2 +-#define MUBRR11 3 +-#define MUBRR12 4 +-#define MUBRR13 5 +-#define MUBRR14 6 +-#define MUBRR15 7 +- +-#define EUDR _SFR_MEM8(0xCE) +-#define EUDR0 0 +-#define EUDR1 1 +-#define EUDR2 2 +-#define EUDR3 3 +-#define EUDR4 4 +-#define EUDR5 5 +-#define EUDR6 6 +-#define EUDR7 7 +- +-#define PSOC0 _SFR_MEM8(0xD0) +-#define POEN0A 0 +-#define POEN0B 2 +-#define PSYNC00 4 +-#define PSYNC01 5 +- +-#define OCR0SA _SFR_MEM16(0xD2) +- +-#define OCR0SAL _SFR_MEM8(0xD2) +-#define OCR0SA_0 0 +-#define OCR0SA_1 1 +-#define OCR0SA_2 2 +-#define OCR0SA_3 3 +-#define OCR0SA_4 4 +-#define OCR0SA_5 5 +-#define OCR0SA_6 6 +-#define OCR0SA_7 7 +- +-#define OCR0SAH _SFR_MEM8(0xD3) +-#define OCR0SA_8 0 +-#define OCR0SA_9 1 +-#define OCR0SA_00 2 +-#define OCR0SA_01 3 +- +-#define OCR0RA _SFR_MEM16(0xD4) +- +-#define OCR0RAL _SFR_MEM8(0xD4) +-#define OCR0RA_0 0 +-#define OCR0RA_1 1 +-#define OCR0RA_2 2 +-#define OCR0RA_3 3 +-#define OCR0RA_4 4 +-#define OCR0RA_5 5 +-#define OCR0RA_6 6 +-#define OCR0RA_7 7 +- +-#define OCR0RAH _SFR_MEM8(0xD5) +-#define OCR0RA_8 0 +-#define OCR0RA_9 1 +-#define OCR0RA_00 2 +-#define OCR0RA_01 3 +- +-#define OCR0SB _SFR_MEM16(0xD6) +- +-#define OCR0SBL _SFR_MEM8(0xD6) +-#define OCR0SB_0 0 +-#define OCR0SB_1 1 +-#define OCR0SB_2 2 +-#define OCR0SB_3 3 +-#define OCR0SB_4 4 +-#define OCR0SB_5 5 +-#define OCR0SB_6 6 +-#define OCR0SB_7 7 +- +-#define OCR0SBH _SFR_MEM8(0xD7) +-#define OCR0SB_8 0 +-#define OCR0SB_9 1 +-#define OCR0SB_00 2 +-#define OCR0SB_01 3 +- +-#define OCR0RB _SFR_MEM16(0xD8) +- +-#define OCR0RBL _SFR_MEM8(0xD8) +-#define OCR0RB_0 0 +-#define OCR0RB_1 1 +-#define OCR0RB_2 2 +-#define OCR0RB_3 3 +-#define OCR0RB_4 4 +-#define OCR0RB_5 5 +-#define OCR0RB_6 6 +-#define OCR0RB_7 7 +- +-#define OCR0RBH _SFR_MEM8(0xD9) +-#define OCR0RB_8 0 +-#define OCR0RB_9 1 +-#define OCR0RB_00 2 +-#define OCR0RB_01 3 +-#define OCR0RB_02 4 +-#define OCR0RB_03 5 +-#define OCR0RB_04 6 +-#define OCR0RB_05 7 +- +-#define PCNF0 _SFR_MEM8(0xDA) +-#define PCLKSEL0 1 +-#define POP0 2 +-#define PMODE00 3 +-#define PMODE01 4 +-#define PLOCK0 5 +-#define PALOCK0 6 +-#define PFIFTY0 7 +- +-#define PCTL0 _SFR_MEM8(0xDB) +-#define PRUN0 0 +-#define PCCYC0 1 +-#define PARUN0 2 +-#define PAOC0A 3 +-#define PAOC0B 4 +-#define PBFM0 5 +-#define PPRE00 6 +-#define PPRE01 7 +- +-#define PFRC0A _SFR_MEM8(0xDC) +-#define PRFM0A0 0 +-#define PRFM0A1 1 +-#define PRFM0A2 2 +-#define PRFM0A3 3 +-#define PFLTE0A 4 +-#define PELEV0A 5 +-#define PISEL0A 6 +-#define PCAE0A 7 +- +-#define PFRC0B _SFR_MEM8(0xDD) +-#define PRFM0B0 0 +-#define PRFM0B1 1 +-#define PRFM0B2 2 +-#define PRFM0B3 3 +-#define PFLTE0B 4 +-#define PELEV0B 5 +-#define PISEL0B 6 +-#define PCAE0B 7 +- +-#define PICR0 _SFR_MEM16(0xDE) +- +-#define PICR0L _SFR_MEM8(0xDE) +-#define PICR0_0 0 +-#define PICR0_1 1 +-#define PICR0_2 2 +-#define PICR0_3 3 +-#define PICR0_4 4 +-#define PICR0_5 5 +-#define PICR0_6 6 +-#define PICR0_7 7 +- +-#define PICR0H _SFR_MEM8(0xDF) +-#define PICR0_8 0 +-#define PICR0_9 1 +-#define PICR0_10 2 +-#define PICR0_11 3 +-#define PCST0 7 +- +-#define PSOC1 _SFR_MEM8(0xE0) +-#define POEN1A 0 +-#define POEN1B 2 +-#define PSYNC1_0 4 +-#define PSYNC1_1 5 +- +-#define OCR1SA _SFR_MEM16(0xE2) +- +-#define OCR1SAL _SFR_MEM8(0xE2) +-#define OCR1SA_0 0 +-#define OCR1SA_1 1 +-#define OCR1SA_2 2 +-#define OCR1SA_3 3 +-#define OCR1SA_4 4 +-#define OCR1SA_5 5 +-#define OCR1SA_6 6 +-#define OCR1SA_7 7 +- +-#define OCR1SAH _SFR_MEM8(0xE3) +-#define OCR1SA_8 0 +-#define OCR1SA_9 1 +-#define OCR1SA_10 2 +-#define OCR1SA_11 3 +- +-#define OCR1RA _SFR_MEM16(0xE4) +- +-#define OCR1RAL _SFR_MEM8(0xE4) +-#define OCR1RA_0 0 +-#define OCR1RA_1 1 +-#define OCR1RA_2 2 +-#define OCR1RA_3 3 +-#define OCR1RA_4 4 +-#define OCR1RA_5 5 +-#define OCR1RA_6 6 +-#define OCR1RA_7 7 +- +-#define OCR1RAH _SFR_MEM8(0xE5) +-#define OCR1RA_8 0 +-#define OCR1RA_9 1 +-#define OCR1RA_10 2 +-#define OCR1RA_11 3 +- +-#define OCR1SB _SFR_MEM16(0xE6) +- +-#define OCR1SBL _SFR_MEM8(0xE6) +-#define OCR1SB_0 0 +-#define OCR1SB_1 1 +-#define OCR1SB_2 2 +-#define OCR1SB_3 3 +-#define OCR1SB_4 4 +-#define OCR1SB_5 5 +-#define OCR1SB_6 6 +-#define OCR1SB_7 7 +- +-#define OCR1SBH _SFR_MEM8(0xE7) +-#define OCR1SB_8 0 +-#define OCR1SB_9 1 +-#define OCR1SB_10 2 +-#define OCR1SB_11 3 +- +-#define OCR1RB _SFR_MEM16(0xE8) +- +-#define OCR1RBL _SFR_MEM8(0xE8) +-#define OCR1RB_0 0 +-#define OCR1RB_1 1 +-#define OCR1RB_2 2 +-#define OCR1RB_3 3 +-#define OCR1RB_4 4 +-#define OCR1RB_5 5 +-#define OCR1RB_6 6 +-#define OCR1RB_7 7 +- +-#define OCR1RBH _SFR_MEM8(0xE9) +-#define OCR1RB_8 0 +-#define OCR1RB_9 1 +-#define OCR1RB_10 2 +-#define OCR1RB_11 3 +-#define OCR1RB_12 4 +-#define OCR1RB_13 5 +-#define OCR1RB_14 6 +-#define OCR1RB_15 7 +- +-#define PCNF1 _SFR_MEM8(0xEA) +-#define PCLKSEL1 1 +-#define POP1 2 +-#define PMODE10 3 +-#define PMODE11 4 +-#define PLOCK1 5 +-#define PALOCK1 6 +-#define PFIFTY1 7 +- +-#define PCTL1 _SFR_MEM8(0xEB) +-#define PRUN1 0 +-#define PCCYC1 1 +-#define PARUN1 2 +-#define PAOC1A 3 +-#define PAOC1B 4 +-#define PBFM1 5 +-#define PPRE10 6 +-#define PPRE11 7 +- +-#define PFRC1A _SFR_MEM8(0xEC) +-#define PRFM1A0 0 +-#define PRFM1A1 1 +-#define PRFM1A2 2 +-#define PRFM1A3 3 +-#define PFLTE1A 4 +-#define PELEV1A 5 +-#define PISEL1A 6 +-#define PCAE1A 7 +- +-#define PFRC1B _SFR_MEM8(0xED) +-#define PRFM1B0 0 +-#define PRFM1B1 1 +-#define PRFM1B2 2 +-#define PRFM1B3 3 +-#define PFLTE1B 4 +-#define PELEV1B 5 +-#define PISEL1B 6 +-#define PCAE1B 7 +- +-#define PICR1 _SFR_MEM16(0xEE) +- +-#define PICR1L _SFR_MEM8(0xEE) +-#define PICR1_0 0 +-#define PICR1_1 1 +-#define PICR1_2 2 +-#define PICR1_3 3 +-#define PICR1_4 4 +-#define PICR1_5 5 +-#define PICR1_6 6 +-#define PICR1_7 7 +- +-#define PICR1H _SFR_MEM8(0xEF) +-#define PICR1_8 0 +-#define PICR1_9 1 +-#define PICR1_10 2 +-#define PICR1_11 3 +-#define PCST1 7 +- +-#define PSOC2 _SFR_MEM8(0xF0) +-#define POEN2A 0 +-#define POEN2C 1 +-#define POEN2B 2 +-#define POEN2D 3 +-#define PSYNC2_0 4 +-#define PSYNC2_1 5 +-#define POS22 6 +-#define POS23 7 +- +-#define POM2 _SFR_MEM8(0xF1) +-#define POMV2A0 0 +-#define POMV2A1 1 +-#define POMV2A2 2 +-#define POMV2A3 3 +-#define POMV2B0 4 +-#define POMV2B1 5 +-#define POMV2B2 6 +-#define POMV2B3 7 +- +-#define OCR2SA _SFR_MEM16(0xF2) +- +-#define OCR2SAL _SFR_MEM8(0xF2) +-#define OCR2SA_0 0 +-#define OCR2SA_1 1 +-#define OCR2SA_2 2 +-#define OCR2SA_3 3 +-#define OCR2SA_4 4 +-#define OCR2SA_5 5 +-#define OCR2SA_6 6 +-#define OCR2SA_7 7 +- +-#define OCR2SAH _SFR_MEM8(0xF3) +-#define OCR2SA_8 0 +-#define OCR2SA_9 1 +-#define OCR2SA_10 2 +-#define OCR2SA_11 3 +- +-#define OCR2RA _SFR_MEM16(0xF4) +- +-#define OCR2RAL _SFR_MEM8(0xF4) +-#define OCR2RA_0 0 +-#define OCR2RA_1 1 +-#define OCR2RA_2 2 +-#define OCR2RA_3 3 +-#define OCR2RA_4 4 +-#define OCR2RA_5 5 +-#define OCR2RA_6 6 +-#define OCR2RA_7 7 +- +-#define OCR2RAH _SFR_MEM8(0xF5) +-#define OCR2RA_8 0 +-#define OCR2RA_9 1 +-#define OCR2RA_10 2 +-#define OCR2RA_11 3 +- +-#define OCR2SB _SFR_MEM16(0xF6) +- +-#define OCR2SBL _SFR_MEM8(0xF6) +-#define OCR2SB_0 0 +-#define OCR2SB_1 1 +-#define OCR2SB_2 2 +-#define OCR2SB_3 3 +-#define OCR2SB_4 4 +-#define OCR2SB_5 5 +-#define OCR2SB_6 6 +-#define OCR2SB_7 7 +- +-#define OCR2SBH _SFR_MEM8(0xF7) +-#define OCR2SB_8 0 +-#define OCR2SB_9 1 +-#define OCR2SB_10 2 +-#define OCR2SB_11 3 +- +-#define OCR2RB _SFR_MEM16(0xF8) +- +-#define OCR2RBL _SFR_MEM8(0xF8) +-#define OCR2RB_0 0 +-#define OCR2RB_1 1 +-#define OCR2RB_2 2 +-#define OCR2RB_3 3 +-#define OCR2RB_4 4 +-#define OCR2RB_5 5 +-#define OCR2RB_6 6 +-#define OCR2RB_7 7 +- +-#define OCR2RBH _SFR_MEM8(0xF9) +-#define OCR2RB_8 0 +-#define OCR2RB_9 1 +-#define OCR2RB_10 2 +-#define OCR2RB_11 3 +-#define OCR2RB_12 4 +-#define OCR2RB_13 5 +-#define OCR2RB_14 6 +-#define OCR2RB_15 7 +- +-#define PCNF2 _SFR_MEM8(0xFA) +-#define POME2 0 +-#define PCLKSEL2 1 +-#define POP2 2 +-#define PMODE20 3 +-#define PMODE21 4 +-#define PLOCK2 5 +-#define PALOCK2 6 +-#define PFIFTY2 7 +- +-#define PCTL2 _SFR_MEM8(0xFB) +-#define PRUN2 0 +-#define PCCYC2 1 +-#define PARUN2 2 +-#define PAOC2A 3 +-#define PAOC2B 4 +-#define PBFM2 5 +-#define PPRE20 6 +-#define PPRE21 7 +- +-#define PFRC2A _SFR_MEM8(0xFC) +-#define PRFM2A0 0 +-#define PRFM2A1 1 +-#define PRFM2A2 2 +-#define PRFM2A3 3 +-#define PFLTE2A 4 +-#define PELEV2A 5 +-#define PISEL2A 6 +-#define PCAE2A 7 +- +-#define PFRC2B _SFR_MEM8(0xFD) +-#define PRFM2B0 0 +-#define PRFM2B1 1 +-#define PRFM2B2 2 +-#define PRFM2B3 3 +-#define PFLTE2B 4 +-#define PELEV2B 5 +-#define PISEL2B 6 +-#define PCAE2B 7 +- +-#define PICR2 _SFR_MEM16(0xFE) +- +-#define PICR2L _SFR_MEM8(0xFE) +-#define PICR2_0 0 +-#define PICR2_1 1 +-#define PICR2_2 2 +-#define PICR2_3 3 +-#define PICR2_4 4 +-#define PICR2_5 5 +-#define PICR2_6 6 +-#define PICR2_7 7 +- +-#define PICR2H _SFR_MEM8(0xFF) +-#define PICR2_8 0 +-#define PICR2_9 1 +-#define PICR2_10 2 +-#define PICR2_11 3 +-#define PCST2 7 +- +- +- +-/* Interrupt Vectors */ +-/* Interrupt vector 0 is the reset vector. */ +- +-#define PSC2_CAPT_vect_num 1 +-#define PSC2_CAPT_vect _VECTOR(1) /* PSC2 Capture Event */ +- +-#define PSC2_EC_vect_num 2 +-#define PSC2_EC_vect _VECTOR(2) /* PSC2 End Cycle */ +- +-#define PSC1_CAPT_vect_num 3 +-#define PSC1_CAPT_vect _VECTOR(3) /* PSC1 Capture Event */ +- +-#define PSC1_EC_vect_num 4 +-#define PSC1_EC_vect _VECTOR(4) /* PSC1 End Cycle */ +- +-#define PSC0_CAPT_vect_num 5 +-#define PSC0_CAPT_vect _VECTOR(5) /* PSC0 Capture Event */ +- +-#define PSC0_EC_vect_num 6 +-#define PSC0_EC_vect _VECTOR(6) /* PSC0 End Cycle */ +- +-#define ANALOG_COMP_0_vect_num 7 +-#define ANALOG_COMP_0_vect _VECTOR(7) /* Analog Comparator 0 */ +- +-#define ANALOG_COMP_1_vect_num 8 +-#define ANALOG_COMP_1_vect _VECTOR(8) /* Analog Comparator 1 */ +- +-#define ANALOG_COMP_2_vect_num 9 +-#define ANALOG_COMP_2_vect _VECTOR(9) /* Analog Comparator 2 */ +- +-#define INT0_vect_num 10 +-#define INT0_vect _VECTOR(10) /* External Interrupt Request 0 */ +- +-#define TIMER1_CAPT_vect_num 11 +-#define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */ +- +-#define TIMER1_COMPA_vect_num 12 +-#define TIMER1_COMPA_vect _VECTOR(12) /* Timer/Counter1 Compare Match A */ +- +-#define TIMER1_COMPB_vect_num 13 +-#define TIMER1_COMPB_vect _VECTOR(13) /* Timer/Counter Compare Match B */ +- +-/* Vector 14, Reserved */ +- +-#define TIMER1_OVF_vect_num 15 +-#define TIMER1_OVF_vect _VECTOR(15) /* Timer/Counter1 Overflow */ +- +-#define TIMER0_COMPA_vect_num 16 +-#define TIMER0_COMPA_vect _VECTOR(16) /* Timer/Counter0 Compare Match A */ +- +-#define TIMER0_OVF_vect_num 17 +-#define TIMER0_OVF_vect _VECTOR(17) /* Timer/Counter0 Overflow */ +- +-#define ADC_vect_num 18 +-#define ADC_vect _VECTOR(18) /* ADC Conversion Complete */ +- +-#define INT1_vect_num 19 +-#define INT1_vect _VECTOR(19) /* External Interrupt Request 1 */ +- +-#define SPI_STC_vect_num 20 +-#define SPI_STC_vect _VECTOR(20) /* SPI Serial Transfer Complete */ +- +-#define USART_RX_vect_num 21 +-#define USART_RX_vect _VECTOR(21) /* USART, Rx Complete */ +- +-#define USART_UDRE_vect_num 22 +-#define USART_UDRE_vect _VECTOR(22) /* USART Data Register Empty */ +- +-#define USART_TX_vect_num 23 +-#define USART_TX_vect _VECTOR(23) /* USART, Tx Complete */ +- +-#define INT2_vect_num 24 +-#define INT2_vect _VECTOR(24) /* External Interrupt Request 2 */ +- +-#define WDT_vect_num 25 +-#define WDT_vect _VECTOR(25) /* Watchdog Timeout Interrupt */ +- +-#define EE_READY_vect_num 26 +-#define EE_READY_vect _VECTOR(26) /* EEPROM Ready */ +- +-#define TIMER0_COMPB_vect_num 27 +-#define TIMER0_COMPB_vect _VECTOR(27) /* Timer Counter 0 Compare Match B */ +- +-#define INT3_vect_num 28 +-#define INT3_vect _VECTOR(28) /* External Interrupt Request 3 */ +- +-/* Vector 29, Reserved */ +- +-/* Vector 30, Reserved */ +- +-#define SPM_READY_vect_num 31 +-#define SPM_READY_vect _VECTOR(31) /* Store Program Memory Read */ +- +-#define _VECTORS_SIZE 64 +- +- +- +-/* Memory Sizes */ +-#define RAMEND 0x2FF +-#define XRAMSIZE 0 +-#define XRAMEND RAMEND +-#define E2END 0x1FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x1FFF +-#define SPM_PAGESIZE 64 +- +- +- +-/* Fuse Information */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown out detector trigger level */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +- +-/* Extended Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_PSCRV (unsigned char)~_BV(4) /* PSCOUT Reset Value */ +-#define FUSE_PSC0RB (unsigned char)~_BV(5) /* PSC0 Reset Behaviour */ +-#define FUSE_PSC1RB (unsigned char)~_BV(6) /* PSC1 Reset Behaviour */ +-#define FUSE_PSC2RB (unsigned char)~_BV(7) /* PSC2 Reset Behaviour */ +-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x93 +-#define SIGNATURE_2 0x83 +- +- +-#endif /* _AVR_IO90PWM3B_H_ */ ++/* Copyright (c) 2007 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++/* $Id: io90pwm3b.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* avr/io90pwm3b.h - definitions for AT90PWM3B */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "io90pwm3b.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_IO90PWM3B_H_ ++#define _AVR_IO90PWM3B_H_ 1 ++ ++/* Registers and associated bit numbers */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++#define PINC7 7 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++#define DDC7 7 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC3 3 ++#define PORTC4 4 ++#define PORTC5 5 ++#define PORTC6 6 ++#define PORTC7 7 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE0 0 ++#define PINE1 1 ++#define PINE2 2 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE0 0 ++#define DDE1 1 ++#define DDE2 2 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE0 0 ++#define PORTE1 1 ++#define PORTE2 2 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define GPIOR1 _SFR_IO8(0x19) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x1A) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define GPIOR3 _SFR_IO8(0x1B) ++#define GPIOR30 0 ++#define GPIOR31 1 ++#define GPIOR32 2 ++#define GPIOR33 3 ++#define GPIOR34 4 ++#define GPIOR35 5 ++#define GPIOR36 6 ++#define GPIOR37 7 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++#define INT3 3 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARL0 0 ++#define EEARL1 1 ++#define EEARL2 2 ++#define EEARL3 3 ++#define EEARL4 4 ++#define EEARL5 5 ++#define EEARL6 6 ++#define EEARL7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++#define EEAR9 1 ++#define EEAR10 2 ++#define EEAR11 3 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR10 0 ++#define PSRSYNC 0 ++#define ICPSEL1 2 ++#define TSM 3 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define OCR0A _SFR_IO8(0x27) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define OCR0B _SFR_IO8(0x28) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define OCR0_0 0 /* Deprecated */ ++#define OCR0_1 1 /* Deprecated */ ++#define OCR0_2 2 /* Deprecated */ ++#define OCR0_3 3 /* Deprecated */ ++#define OCR0_4 4 /* Deprecated */ ++#define OCR0_5 5 /* Deprecated */ ++#define OCR0_6 6 /* Deprecated */ ++#define OCR0_7 7 /* Deprecated */ ++ ++#define PLLCSR _SFR_IO8(0x29) ++#define PLOCK 0 ++#define PLLE 1 ++#define PLLF 2 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define ACSR _SFR_IO8(0x30) ++#define AC0O 0 ++#define AC1O 1 ++#define AC2O 2 ++#define AC0IF 4 ++#define AC1IF 5 ++#define AC2IF 6 ++#define ACCKDIV 7 ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define SPIPS 7 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM0 3 ++#define PRTIM1 4 ++#define PRPSC0 5 ++#define PRPSC1 6 ++#define PRPSC2 7 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define AMP0CSR _SFR_MEM8(0x76) ++#define AMP0TS0 0 ++#define AMP0TS1 1 ++#define AMP0G0 4 ++#define AMP0G1 5 ++#define AMP0IS 6 ++#define AMP0EN 7 ++ ++#define AMP1CSR _SFR_MEM8(0x77) ++#define AMP1TS0 0 ++#define AMP1TS1 1 ++#define AMP1G0 4 ++#define AMP1G1 5 ++#define AMP1IS 6 ++#define AMP1EN 7 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_MEM8(0x79) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ADTS3 3 ++#define ADASCR 4 ++#define ADHSM 7 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define ADC8D 0 ++#define ADC9D 1 ++#define ADC10D 2 ++#define AMP0ND 3 ++#define AMP0PD 4 ++#define ACMP0D 5 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define PIFR0 _SFR_MEM8(0xA0) ++#define PEOP0 0 ++#define PRN00 1 ++#define PRN01 2 ++#define PEV0A 3 ++#define PEV0B 4 ++#define PSEI0 5 ++#define POAC0A 6 ++#define POAC0B 7 ++ ++#define PIM0 _SFR_MEM8(0xA1) ++#define PEOPE0 0 ++#define PEVE0A 3 ++#define PEVE0B 4 ++#define PSEIE0 5 ++ ++#define PIFR1 _SFR_MEM8(0xA2) ++#define PEOP1 0 ++#define PRN10 1 ++#define PRN11 2 ++#define PEV1A 3 ++#define PEV1B 4 ++#define PSEI1 5 ++#define POAC1A 6 ++#define POAC1B 7 ++ ++#define PIM1 _SFR_MEM8(0xA3) ++#define PEOPE1 0 ++#define PEVE1A 3 ++#define PEVE1B 4 ++#define PSEIE1 5 ++ ++#define PIFR2 _SFR_MEM8(0xA4) ++#define PEOP2 0 ++#define PRN20 1 ++#define PRN21 2 ++#define PEV2A 3 ++#define PEV2B 4 ++#define PSEI2 5 ++#define POAC2A 6 ++#define POAC2B 7 ++ ++#define PIM2 _SFR_MEM8(0xA5) ++#define PEOPE2 0 ++#define PEVE2A 3 ++#define PEVE2B 4 ++#define PSEIE2 5 ++ ++#define DACON _SFR_MEM8(0xAA) ++#define DAEN 0 ++#define DAOE 1 ++#define DALA 2 ++#define DATS0 4 ++#define DATS1 5 ++#define DATS2 6 ++#define DAATE 7 ++ ++#define DAC _SFR_MEM16(0xAB) ++ ++#define DACL _SFR_MEM8(0xAB) ++#define DACL0 0 ++#define DACL1 1 ++#define DACL2 2 ++#define DACL3 3 ++#define DACL4 4 ++#define DACL5 5 ++#define DACL6 6 ++#define DACL7 7 ++ ++#define DACH _SFR_MEM8(0xAC) ++#define DACH0 0 ++#define DACH1 1 ++#define DACH2 2 ++#define DACH3 3 ++#define DACH4 4 ++#define DACH5 5 ++#define DACH6 6 ++#define DACH7 7 ++ ++#define AC0CON _SFR_MEM8(0xAD) ++#define AC0M0 0 ++#define AC0M1 1 ++#define AC0M2 2 ++#define AC0IS0 4 ++#define AC0IS1 5 ++#define AC0IE 6 ++#define AC0EN 7 ++ ++#define AC1CON _SFR_MEM8(0xAE) ++#define AC1M0 0 ++#define AC1M1 1 ++#define AC1M2 2 ++#define AC1ICE 3 ++#define AC1IS0 4 ++#define AC1IS1 5 ++#define AC1IE 6 ++#define AC1EN 7 ++ ++#define AC2CON _SFR_MEM8(0xAF) ++#define AC2M0 0 ++#define AC2M1 1 ++#define AC2M2 2 ++#define AC2IS0 4 ++#define AC2IS1 5 ++#define AC2IE 6 ++#define AC2EN 7 ++ ++#define UCSRA _SFR_MEM8(0xC0) ++#define MPCM 0 ++#define U2X 1 ++#define UPE 2 ++#define DOR 3 ++#define FE 4 ++#define UDRE 5 ++#define TXC 6 ++#define RXC 7 ++ ++#define UCSRB _SFR_MEM8(0xC1) ++#define TXB8 0 ++#define RXB8 1 ++#define UCSZ2 2 ++#define TXEN 3 ++#define RXEN 4 ++#define UDRIE 5 ++#define TXCIE 6 ++#define RXCIE 7 ++ ++#define UCSRC _SFR_MEM8(0xC2) ++#define UCPOL 0 ++#define UCSZ0 1 ++#define UCSZ1 2 ++#define USBS 3 ++#define UPM0 4 ++#define UPM1 5 ++#define UMSEL0 6 ++ ++#define UBRR _SFR_MEM16(0xC4) ++ ++#define UBRRL _SFR_MEM8(0xC4) ++#define UBRR0 0 ++#define UBRR1 1 ++#define UBRR2 2 ++#define UBRR3 3 ++#define UBRR4 4 ++#define UBRR5 5 ++#define UBRR6 6 ++#define UBRR7 7 ++ ++#define UBRRH _SFR_MEM8(0xC5) ++#define UBRR8 0 ++#define UBRR9 1 ++#define UBRR10 2 ++#define UBRR11 3 ++ ++#define UDR _SFR_MEM8(0xC6) ++#define UDR0 0 ++#define UDR1 1 ++#define UDR2 2 ++#define UDR3 3 ++#define UDR4 4 ++#define UDR5 5 ++#define UDR6 6 ++#define UDR7 7 ++ ++#define EUCSRA _SFR_MEM8(0xC8) ++#define URxS0 0 ++#define URxS1 1 ++#define URxS2 2 ++#define URxS3 3 ++#define UTxS0 4 ++#define UTxS1 5 ++#define UTxS2 6 ++#define UTxS3 7 ++ ++#define EUCSRB _SFR_MEM8(0xC9) ++#define BODR 0 ++#define EMCH 1 ++#define EUSBS 3 ++#define EUSART 4 ++ ++#define EUCSRC _SFR_MEM8(0xCA) ++#define STP0 0 ++#define STP1 1 ++#define F1617 2 ++#define FEM 3 ++ ++#define MUBRR _SFR_MEM16(0xCC) ++ ++#define MUBRRL _SFR_MEM8(0xCC) ++#define MUBRR0 0 ++#define MUBRR1 1 ++#define MUBRR2 2 ++#define MUBRR3 3 ++#define MUBRR4 4 ++#define MUBRR5 5 ++#define MUBRR6 6 ++#define MUBRR7 7 ++ ++#define MUBRRH _SFR_MEM8(0xCD) ++#define MUBRR8 0 ++#define MUBRR9 1 ++#define MUBRR10 2 ++#define MUBRR11 3 ++#define MUBRR12 4 ++#define MUBRR13 5 ++#define MUBRR14 6 ++#define MUBRR15 7 ++ ++#define EUDR _SFR_MEM8(0xCE) ++#define EUDR0 0 ++#define EUDR1 1 ++#define EUDR2 2 ++#define EUDR3 3 ++#define EUDR4 4 ++#define EUDR5 5 ++#define EUDR6 6 ++#define EUDR7 7 ++ ++#define PSOC0 _SFR_MEM8(0xD0) ++#define POEN0A 0 ++#define POEN0B 2 ++#define PSYNC00 4 ++#define PSYNC01 5 ++ ++#define OCR0SA _SFR_MEM16(0xD2) ++ ++#define OCR0SAL _SFR_MEM8(0xD2) ++#define OCR0SA_0 0 ++#define OCR0SA_1 1 ++#define OCR0SA_2 2 ++#define OCR0SA_3 3 ++#define OCR0SA_4 4 ++#define OCR0SA_5 5 ++#define OCR0SA_6 6 ++#define OCR0SA_7 7 ++ ++#define OCR0SAH _SFR_MEM8(0xD3) ++#define OCR0SA_8 0 ++#define OCR0SA_9 1 ++#define OCR0SA_00 2 ++#define OCR0SA_01 3 ++ ++#define OCR0RA _SFR_MEM16(0xD4) ++ ++#define OCR0RAL _SFR_MEM8(0xD4) ++#define OCR0RA_0 0 ++#define OCR0RA_1 1 ++#define OCR0RA_2 2 ++#define OCR0RA_3 3 ++#define OCR0RA_4 4 ++#define OCR0RA_5 5 ++#define OCR0RA_6 6 ++#define OCR0RA_7 7 ++ ++#define OCR0RAH _SFR_MEM8(0xD5) ++#define OCR0RA_8 0 ++#define OCR0RA_9 1 ++#define OCR0RA_00 2 ++#define OCR0RA_01 3 ++ ++#define OCR0SB _SFR_MEM16(0xD6) ++ ++#define OCR0SBL _SFR_MEM8(0xD6) ++#define OCR0SB_0 0 ++#define OCR0SB_1 1 ++#define OCR0SB_2 2 ++#define OCR0SB_3 3 ++#define OCR0SB_4 4 ++#define OCR0SB_5 5 ++#define OCR0SB_6 6 ++#define OCR0SB_7 7 ++ ++#define OCR0SBH _SFR_MEM8(0xD7) ++#define OCR0SB_8 0 ++#define OCR0SB_9 1 ++#define OCR0SB_00 2 ++#define OCR0SB_01 3 ++ ++#define OCR0RB _SFR_MEM16(0xD8) ++ ++#define OCR0RBL _SFR_MEM8(0xD8) ++#define OCR0RB_0 0 ++#define OCR0RB_1 1 ++#define OCR0RB_2 2 ++#define OCR0RB_3 3 ++#define OCR0RB_4 4 ++#define OCR0RB_5 5 ++#define OCR0RB_6 6 ++#define OCR0RB_7 7 ++ ++#define OCR0RBH _SFR_MEM8(0xD9) ++#define OCR0RB_8 0 ++#define OCR0RB_9 1 ++#define OCR0RB_00 2 ++#define OCR0RB_01 3 ++#define OCR0RB_02 4 ++#define OCR0RB_03 5 ++#define OCR0RB_04 6 ++#define OCR0RB_05 7 ++ ++#define PCNF0 _SFR_MEM8(0xDA) ++#define PCLKSEL0 1 ++#define POP0 2 ++#define PMODE00 3 ++#define PMODE01 4 ++#define PLOCK0 5 ++#define PALOCK0 6 ++#define PFIFTY0 7 ++ ++#define PCTL0 _SFR_MEM8(0xDB) ++#define PRUN0 0 ++#define PCCYC0 1 ++#define PARUN0 2 ++#define PAOC0A 3 ++#define PAOC0B 4 ++#define PBFM0 5 ++#define PPRE00 6 ++#define PPRE01 7 ++ ++#define PFRC0A _SFR_MEM8(0xDC) ++#define PRFM0A0 0 ++#define PRFM0A1 1 ++#define PRFM0A2 2 ++#define PRFM0A3 3 ++#define PFLTE0A 4 ++#define PELEV0A 5 ++#define PISEL0A 6 ++#define PCAE0A 7 ++ ++#define PFRC0B _SFR_MEM8(0xDD) ++#define PRFM0B0 0 ++#define PRFM0B1 1 ++#define PRFM0B2 2 ++#define PRFM0B3 3 ++#define PFLTE0B 4 ++#define PELEV0B 5 ++#define PISEL0B 6 ++#define PCAE0B 7 ++ ++#define PICR0 _SFR_MEM16(0xDE) ++ ++#define PICR0L _SFR_MEM8(0xDE) ++#define PICR0_0 0 ++#define PICR0_1 1 ++#define PICR0_2 2 ++#define PICR0_3 3 ++#define PICR0_4 4 ++#define PICR0_5 5 ++#define PICR0_6 6 ++#define PICR0_7 7 ++ ++#define PICR0H _SFR_MEM8(0xDF) ++#define PICR0_8 0 ++#define PICR0_9 1 ++#define PICR0_10 2 ++#define PICR0_11 3 ++#define PCST0 7 ++ ++#define PSOC1 _SFR_MEM8(0xE0) ++#define POEN1A 0 ++#define POEN1B 2 ++#define PSYNC1_0 4 ++#define PSYNC1_1 5 ++ ++#define OCR1SA _SFR_MEM16(0xE2) ++ ++#define OCR1SAL _SFR_MEM8(0xE2) ++#define OCR1SA_0 0 ++#define OCR1SA_1 1 ++#define OCR1SA_2 2 ++#define OCR1SA_3 3 ++#define OCR1SA_4 4 ++#define OCR1SA_5 5 ++#define OCR1SA_6 6 ++#define OCR1SA_7 7 ++ ++#define OCR1SAH _SFR_MEM8(0xE3) ++#define OCR1SA_8 0 ++#define OCR1SA_9 1 ++#define OCR1SA_10 2 ++#define OCR1SA_11 3 ++ ++#define OCR1RA _SFR_MEM16(0xE4) ++ ++#define OCR1RAL _SFR_MEM8(0xE4) ++#define OCR1RA_0 0 ++#define OCR1RA_1 1 ++#define OCR1RA_2 2 ++#define OCR1RA_3 3 ++#define OCR1RA_4 4 ++#define OCR1RA_5 5 ++#define OCR1RA_6 6 ++#define OCR1RA_7 7 ++ ++#define OCR1RAH _SFR_MEM8(0xE5) ++#define OCR1RA_8 0 ++#define OCR1RA_9 1 ++#define OCR1RA_10 2 ++#define OCR1RA_11 3 ++ ++#define OCR1SB _SFR_MEM16(0xE6) ++ ++#define OCR1SBL _SFR_MEM8(0xE6) ++#define OCR1SB_0 0 ++#define OCR1SB_1 1 ++#define OCR1SB_2 2 ++#define OCR1SB_3 3 ++#define OCR1SB_4 4 ++#define OCR1SB_5 5 ++#define OCR1SB_6 6 ++#define OCR1SB_7 7 ++ ++#define OCR1SBH _SFR_MEM8(0xE7) ++#define OCR1SB_8 0 ++#define OCR1SB_9 1 ++#define OCR1SB_10 2 ++#define OCR1SB_11 3 ++ ++#define OCR1RB _SFR_MEM16(0xE8) ++ ++#define OCR1RBL _SFR_MEM8(0xE8) ++#define OCR1RB_0 0 ++#define OCR1RB_1 1 ++#define OCR1RB_2 2 ++#define OCR1RB_3 3 ++#define OCR1RB_4 4 ++#define OCR1RB_5 5 ++#define OCR1RB_6 6 ++#define OCR1RB_7 7 ++ ++#define OCR1RBH _SFR_MEM8(0xE9) ++#define OCR1RB_8 0 ++#define OCR1RB_9 1 ++#define OCR1RB_10 2 ++#define OCR1RB_11 3 ++#define OCR1RB_12 4 ++#define OCR1RB_13 5 ++#define OCR1RB_14 6 ++#define OCR1RB_15 7 ++ ++#define PCNF1 _SFR_MEM8(0xEA) ++#define PCLKSEL1 1 ++#define POP1 2 ++#define PMODE10 3 ++#define PMODE11 4 ++#define PLOCK1 5 ++#define PALOCK1 6 ++#define PFIFTY1 7 ++ ++#define PCTL1 _SFR_MEM8(0xEB) ++#define PRUN1 0 ++#define PCCYC1 1 ++#define PARUN1 2 ++#define PAOC1A 3 ++#define PAOC1B 4 ++#define PBFM1 5 ++#define PPRE10 6 ++#define PPRE11 7 ++ ++#define PFRC1A _SFR_MEM8(0xEC) ++#define PRFM1A0 0 ++#define PRFM1A1 1 ++#define PRFM1A2 2 ++#define PRFM1A3 3 ++#define PFLTE1A 4 ++#define PELEV1A 5 ++#define PISEL1A 6 ++#define PCAE1A 7 ++ ++#define PFRC1B _SFR_MEM8(0xED) ++#define PRFM1B0 0 ++#define PRFM1B1 1 ++#define PRFM1B2 2 ++#define PRFM1B3 3 ++#define PFLTE1B 4 ++#define PELEV1B 5 ++#define PISEL1B 6 ++#define PCAE1B 7 ++ ++#define PICR1 _SFR_MEM16(0xEE) ++ ++#define PICR1L _SFR_MEM8(0xEE) ++#define PICR1_0 0 ++#define PICR1_1 1 ++#define PICR1_2 2 ++#define PICR1_3 3 ++#define PICR1_4 4 ++#define PICR1_5 5 ++#define PICR1_6 6 ++#define PICR1_7 7 ++ ++#define PICR1H _SFR_MEM8(0xEF) ++#define PICR1_8 0 ++#define PICR1_9 1 ++#define PICR1_10 2 ++#define PICR1_11 3 ++#define PCST1 7 ++ ++#define PSOC2 _SFR_MEM8(0xF0) ++#define POEN2A 0 ++#define POEN2C 1 ++#define POEN2B 2 ++#define POEN2D 3 ++#define PSYNC2_0 4 ++#define PSYNC2_1 5 ++#define POS22 6 ++#define POS23 7 ++ ++#define POM2 _SFR_MEM8(0xF1) ++#define POMV2A0 0 ++#define POMV2A1 1 ++#define POMV2A2 2 ++#define POMV2A3 3 ++#define POMV2B0 4 ++#define POMV2B1 5 ++#define POMV2B2 6 ++#define POMV2B3 7 ++ ++#define OCR2SA _SFR_MEM16(0xF2) ++ ++#define OCR2SAL _SFR_MEM8(0xF2) ++#define OCR2SA_0 0 ++#define OCR2SA_1 1 ++#define OCR2SA_2 2 ++#define OCR2SA_3 3 ++#define OCR2SA_4 4 ++#define OCR2SA_5 5 ++#define OCR2SA_6 6 ++#define OCR2SA_7 7 ++ ++#define OCR2SAH _SFR_MEM8(0xF3) ++#define OCR2SA_8 0 ++#define OCR2SA_9 1 ++#define OCR2SA_10 2 ++#define OCR2SA_11 3 ++ ++#define OCR2RA _SFR_MEM16(0xF4) ++ ++#define OCR2RAL _SFR_MEM8(0xF4) ++#define OCR2RA_0 0 ++#define OCR2RA_1 1 ++#define OCR2RA_2 2 ++#define OCR2RA_3 3 ++#define OCR2RA_4 4 ++#define OCR2RA_5 5 ++#define OCR2RA_6 6 ++#define OCR2RA_7 7 ++ ++#define OCR2RAH _SFR_MEM8(0xF5) ++#define OCR2RA_8 0 ++#define OCR2RA_9 1 ++#define OCR2RA_10 2 ++#define OCR2RA_11 3 ++ ++#define OCR2SB _SFR_MEM16(0xF6) ++ ++#define OCR2SBL _SFR_MEM8(0xF6) ++#define OCR2SB_0 0 ++#define OCR2SB_1 1 ++#define OCR2SB_2 2 ++#define OCR2SB_3 3 ++#define OCR2SB_4 4 ++#define OCR2SB_5 5 ++#define OCR2SB_6 6 ++#define OCR2SB_7 7 ++ ++#define OCR2SBH _SFR_MEM8(0xF7) ++#define OCR2SB_8 0 ++#define OCR2SB_9 1 ++#define OCR2SB_10 2 ++#define OCR2SB_11 3 ++ ++#define OCR2RB _SFR_MEM16(0xF8) ++ ++#define OCR2RBL _SFR_MEM8(0xF8) ++#define OCR2RB_0 0 ++#define OCR2RB_1 1 ++#define OCR2RB_2 2 ++#define OCR2RB_3 3 ++#define OCR2RB_4 4 ++#define OCR2RB_5 5 ++#define OCR2RB_6 6 ++#define OCR2RB_7 7 ++ ++#define OCR2RBH _SFR_MEM8(0xF9) ++#define OCR2RB_8 0 ++#define OCR2RB_9 1 ++#define OCR2RB_10 2 ++#define OCR2RB_11 3 ++#define OCR2RB_12 4 ++#define OCR2RB_13 5 ++#define OCR2RB_14 6 ++#define OCR2RB_15 7 ++ ++#define PCNF2 _SFR_MEM8(0xFA) ++#define POME2 0 ++#define PCLKSEL2 1 ++#define POP2 2 ++#define PMODE20 3 ++#define PMODE21 4 ++#define PLOCK2 5 ++#define PALOCK2 6 ++#define PFIFTY2 7 ++ ++#define PCTL2 _SFR_MEM8(0xFB) ++#define PRUN2 0 ++#define PCCYC2 1 ++#define PARUN2 2 ++#define PAOC2A 3 ++#define PAOC2B 4 ++#define PBFM2 5 ++#define PPRE20 6 ++#define PPRE21 7 ++ ++#define PFRC2A _SFR_MEM8(0xFC) ++#define PRFM2A0 0 ++#define PRFM2A1 1 ++#define PRFM2A2 2 ++#define PRFM2A3 3 ++#define PFLTE2A 4 ++#define PELEV2A 5 ++#define PISEL2A 6 ++#define PCAE2A 7 ++ ++#define PFRC2B _SFR_MEM8(0xFD) ++#define PRFM2B0 0 ++#define PRFM2B1 1 ++#define PRFM2B2 2 ++#define PRFM2B3 3 ++#define PFLTE2B 4 ++#define PELEV2B 5 ++#define PISEL2B 6 ++#define PCAE2B 7 ++ ++#define PICR2 _SFR_MEM16(0xFE) ++ ++#define PICR2L _SFR_MEM8(0xFE) ++#define PICR2_0 0 ++#define PICR2_1 1 ++#define PICR2_2 2 ++#define PICR2_3 3 ++#define PICR2_4 4 ++#define PICR2_5 5 ++#define PICR2_6 6 ++#define PICR2_7 7 ++ ++#define PICR2H _SFR_MEM8(0xFF) ++#define PICR2_8 0 ++#define PICR2_9 1 ++#define PICR2_10 2 ++#define PICR2_11 3 ++#define PCST2 7 ++ ++ ++ ++/* Interrupt Vectors */ ++/* Interrupt vector 0 is the reset vector. */ ++ ++#define PSC2_CAPT_vect_num 1 ++#define PSC2_CAPT_vect _VECTOR(1) /* PSC2 Capture Event */ ++ ++#define PSC2_EC_vect_num 2 ++#define PSC2_EC_vect _VECTOR(2) /* PSC2 End Cycle */ ++ ++#define PSC1_CAPT_vect_num 3 ++#define PSC1_CAPT_vect _VECTOR(3) /* PSC1 Capture Event */ ++ ++#define PSC1_EC_vect_num 4 ++#define PSC1_EC_vect _VECTOR(4) /* PSC1 End Cycle */ ++ ++#define PSC0_CAPT_vect_num 5 ++#define PSC0_CAPT_vect _VECTOR(5) /* PSC0 Capture Event */ ++ ++#define PSC0_EC_vect_num 6 ++#define PSC0_EC_vect _VECTOR(6) /* PSC0 End Cycle */ ++ ++#define ANALOG_COMP_0_vect_num 7 ++#define ANALOG_COMP_0_vect _VECTOR(7) /* Analog Comparator 0 */ ++ ++#define ANALOG_COMP_1_vect_num 8 ++#define ANALOG_COMP_1_vect _VECTOR(8) /* Analog Comparator 1 */ ++ ++#define ANALOG_COMP_2_vect_num 9 ++#define ANALOG_COMP_2_vect _VECTOR(9) /* Analog Comparator 2 */ ++ ++#define INT0_vect_num 10 ++#define INT0_vect _VECTOR(10) /* External Interrupt Request 0 */ ++ ++#define TIMER1_CAPT_vect_num 11 ++#define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */ ++ ++#define TIMER1_COMPA_vect_num 12 ++#define TIMER1_COMPA_vect _VECTOR(12) /* Timer/Counter1 Compare Match A */ ++ ++#define TIMER1_COMPB_vect_num 13 ++#define TIMER1_COMPB_vect _VECTOR(13) /* Timer/Counter Compare Match B */ ++ ++/* Vector 14, Reserved */ ++ ++#define TIMER1_OVF_vect_num 15 ++#define TIMER1_OVF_vect _VECTOR(15) /* Timer/Counter1 Overflow */ ++ ++#define TIMER0_COMPA_vect_num 16 ++#define TIMER0_COMPA_vect _VECTOR(16) /* Timer/Counter0 Compare Match A */ ++ ++#define TIMER0_OVF_vect_num 17 ++#define TIMER0_OVF_vect _VECTOR(17) /* Timer/Counter0 Overflow */ ++ ++#define ADC_vect_num 18 ++#define ADC_vect _VECTOR(18) /* ADC Conversion Complete */ ++ ++#define INT1_vect_num 19 ++#define INT1_vect _VECTOR(19) /* External Interrupt Request 1 */ ++ ++#define SPI_STC_vect_num 20 ++#define SPI_STC_vect _VECTOR(20) /* SPI Serial Transfer Complete */ ++ ++#define USART_RX_vect_num 21 ++#define USART_RX_vect _VECTOR(21) /* USART, Rx Complete */ ++ ++#define USART_UDRE_vect_num 22 ++#define USART_UDRE_vect _VECTOR(22) /* USART Data Register Empty */ ++ ++#define USART_TX_vect_num 23 ++#define USART_TX_vect _VECTOR(23) /* USART, Tx Complete */ ++ ++#define INT2_vect_num 24 ++#define INT2_vect _VECTOR(24) /* External Interrupt Request 2 */ ++ ++#define WDT_vect_num 25 ++#define WDT_vect _VECTOR(25) /* Watchdog Timeout Interrupt */ ++ ++#define EE_READY_vect_num 26 ++#define EE_READY_vect _VECTOR(26) /* EEPROM Ready */ ++ ++#define TIMER0_COMPB_vect_num 27 ++#define TIMER0_COMPB_vect _VECTOR(27) /* Timer Counter 0 Compare Match B */ ++ ++#define INT3_vect_num 28 ++#define INT3_vect _VECTOR(28) /* External Interrupt Request 3 */ ++ ++/* Vector 29, Reserved */ ++ ++/* Vector 30, Reserved */ ++ ++#define SPM_READY_vect_num 31 ++#define SPM_READY_vect _VECTOR(31) /* Store Program Memory Read */ ++ ++#define _VECTORS_SIZE 64 ++ ++ ++ ++/* Memory Sizes */ ++#define RAMSTART 0x100 ++#define RAMEND 0x2FF ++#define XRAMSIZE 0 ++#define XRAMEND RAMEND ++#define E2END 0x1FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x1FFF ++#define SPM_PAGESIZE 64 ++ ++ ++ ++/* Fuse Information */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown out detector trigger level */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++ ++/* Extended Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_PSCRV (unsigned char)~_BV(4) /* PSCOUT Reset Value */ ++#define FUSE_PSC0RB (unsigned char)~_BV(5) /* PSC0 Reset Behaviour */ ++#define FUSE_PSC1RB (unsigned char)~_BV(6) /* PSC1 Reset Behaviour */ ++#define FUSE_PSC2RB (unsigned char)~_BV(7) /* PSC2 Reset Behaviour */ ++#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x83 ++ ++ ++#endif /* _AVR_IO90PWM3B_H_ */ +diff --git a/include/avr/io90pwm81.h b/include/avr/io90pwm81.h +index c4b8941..7c6d01f 100644 +--- a/include/avr/io90pwm81.h ++++ b/include/avr/io90pwm81.h +@@ -1,1025 +1,1025 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: io90pwm81.h 2206 2011-02-11 06:58:02Z aboyapati $ */ +- +-/* avr/io90pwm81.h - definitions for AT90PWM81 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "io90pwm81.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_AT90PWM81_H_ +-#define _AVR_AT90PWM81_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define ACSR _SFR_IO8(0x00) +-#define AC1O 1 +-#define AC2O 2 +-#define AC3O 3 +-#define AC1IF 5 +-#define AC2IF 6 +-#define AC3IF 7 +- +-#define TIMSK1 _SFR_IO8(0x01) +-#define TOIE1 0 +-#define ICIE1 5 +- +-#define TIFR1 _SFR_IO8(0x02) +-#define TOV1 0 +-#define ICF1 5 +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define ADCSRA _SFR_IO8(0x06) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_IO8(0x07) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ADTS3 3 +-#define ADSSEN 4 +-#define ADNCDIS 6 +-#define ADHSM 7 +- +-#define ADMUX _SFR_IO8(0x08) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define PINE _SFR_IO8(0x0C) +-#define PINE0 0 +-#define PINE1 1 +-#define PINE2 2 +- +-#define DDRE _SFR_IO8(0x0D) +-#define DDE0 0 +-#define DDE1 1 +-#define DDE2 2 +- +-#define PORTE _SFR_IO8(0x0E) +-#define PORTE0 0 +-#define PORTE1 1 +-#define PORTE2 2 +- +-#define PIM0 _SFR_IO8(0x0F) +-#define PEOPE0 0 +-#define PEOEPE0 1 +-#define PEVE0A 3 +-#define PEVE0B 4 +- +-#define PIFR0 _SFR_IO8(0x10) +-#define PEOP0 0 +-#define PRN00 1 +-#define PRN01 2 +-#define PEV0A 3 +-#define PEV0B 4 +-#define POAC0A 6 +-#define POAC0B 7 +- +-#define PCNF0 _SFR_IO8(0x11) +-#define PCLKSEL0 1 +-#define POP0 2 +-#define PMODE00 3 +-#define PMODE01 4 +-#define PLOCK0 5 +-#define PALOCK0 6 +-#define PFIFTY0 7 +- +-#define PCTL0 _SFR_IO8(0x12) +-#define PRUN0 0 +-#define PCCYC0 1 +-#define PBFM00 2 +-#define PAOC0A 3 +-#define PAOC0B 4 +-#define PBFM01 5 +-#define PPRE00 6 +-#define PPRE01 7 +- +-#define PIM2 _SFR_IO8(0x13) +-#define PEOPE2 0 +-#define PEOEPE2 1 +-#define PEVE2A 3 +-#define PEVE2B 4 +-#define PSEIE2 5 +- +-#define PIFR2 _SFR_IO8(0x14) +-#define PEOP2 0 +-#define PRN20 1 +-#define PRN21 2 +-#define PEV2A 3 +-#define PEV2B 4 +-#define PSEI2 5 +-#define POAC2A 6 +-#define POAC2B 7 +- +-#define PCNF2 _SFR_IO8(0x15) +-#define POME2 0 +-#define PCLKSEL2 1 +-#define POP2 2 +-#define PMODE20 3 +-#define PMODE21 4 +-#define PLOCK2 5 +-#define PALOCK2 6 +-#define PFIFTY2 7 +- +-#define PCTL2 _SFR_IO8(0x16) +-#define PRUN2 0 +-#define PCCYC2 1 +-#define PARUN2 2 +-#define PAOC2A 3 +-#define PAOC2B 4 +-#define PBFM2 5 +-#define PPRE20 6 +-#define PPRE21 7 +- +-#define SPCR _SFR_IO8(0x17) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x18) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define GPIOR0 _SFR_IO8(0x19) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define GPIOR1 _SFR_IO8(0x1A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x1B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define EECR _SFR_IO8(0x1C) +-#define EERE 0 +-#define EEWE 1 +-#define EEMWE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +-#define EEPAGE 6 +-#define NVMBSY 7 +- +-#define EEDR _SFR_IO8(0x1D) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x1E) +- +-#define EEARL _SFR_IO8(0x1E) +-#define EEARL0 0 +-#define EEARL1 1 +-#define EEARL2 2 +-#define EEARL3 3 +-#define EEARL4 4 +-#define EEARL5 5 +-#define EEARL6 6 +-#define EEARL7 7 +- +-#define EEARH _SFR_IO8(0x1F) +-#define EEAR8 0 +- +-#define EIFR _SFR_IO8(0x20) +-#define INTF0 0 +-#define INTF1 1 +-#define INTF2 2 +- +-#define EIMSK _SFR_IO8(0x21) +-#define INT0 0 +-#define INT1 1 +-#define INT2 2 +- +-#define OCR0SB _SFR_IO16(0x22) +- +-#define OCR0SBL _SFR_IO8(0x22) +-#define OCR0SB_0 0 +-#define OCR0SB_1 1 +-#define OCR0SB_2 2 +-#define OCR0SB_3 3 +-#define OCR0SB_4 4 +-#define OCR0SB_5 5 +-#define OCR0SB_6 6 +-#define OCR0SB_7 7 +- +-#define OCR0SBH _SFR_IO8(0x23) +-#define OCR0SB_8 0 +-#define OCR0SB_9 1 +-#define OCR0SB_00 2 +-#define OCR0SB_01 3 +- +-#define OCR0RB _SFR_IO16(0x24) +- +-#define OCR0RBL _SFR_IO8(0x24) +-#define OCR0RB_0 0 +-#define OCR0RB_1 1 +-#define OCR0RB_2 2 +-#define OCR0RB_3 3 +-#define OCR0RB_4 4 +-#define OCR0RB_5 5 +-#define OCR0RB_6 6 +-#define OCR0RB_7 7 +- +-#define OCR0RBH _SFR_IO8(0x25) +-#define OCR0RB_8 0 +-#define OCR0RB_9 1 +-#define OCR0RB_00 2 +-#define OCR0RB_01 3 +-#define OCR0RB_02 4 +-#define OCR0RB_03 5 +-#define OCR0RB_04 6 +-#define OCR0RB_05 7 +- +-#define OCR2SB _SFR_IO16(0x26) +- +-#define OCR2SBL _SFR_IO8(0x26) +-#define OCR2SB_0 0 +-#define OCR2SB_1 1 +-#define OCR2SB_2 2 +-#define OCR2SB_3 3 +-#define OCR2SB_4 4 +-#define OCR2SB_5 5 +-#define OCR2SB_6 6 +-#define OCR2SB_7 7 +- +-#define OCR2SBH _SFR_IO8(0x27) +-#define OCR2SB_8 0 +-#define OCR2SB_9 1 +-#define OCR2SB_10 2 +-#define OCR2SB_11 3 +- +-#define OCR2RB _SFR_IO16(0x28) +- +-#define OCR2RBL _SFR_IO8(0x28) +-#define OCR2RB_0 0 +-#define OCR2RB_1 1 +-#define OCR2RB_2 2 +-#define OCR2RB_3 3 +-#define OCR2RB_4 4 +-#define OCR2RB_5 5 +-#define OCR2RB_6 6 +-#define OCR2RB_7 7 +- +-#define OCR2RBH _SFR_IO8(0x29) +-#define OCR2RB_8 0 +-#define OCR2RB_9 1 +-#define OCR2RB_10 2 +-#define OCR2RB_11 3 +-#define OCR2RB_12 4 +-#define OCR2RB_13 5 +-#define OCR2RB_14 6 +-#define OCR2RB_15 7 +- +-#define OCR0RA _SFR_IO16(0x2A) +- +-#define OCR0RAL _SFR_IO8(0x2A) +-#define OCR0RA_0 0 +-#define OCR0RA_1 1 +-#define OCR0RA_2 2 +-#define OCR0RA_3 3 +-#define OCR0RA_4 4 +-#define OCR0RA_5 5 +-#define OCR0RA_6 6 +-#define OCR0RA_7 7 +- +-#define OCR0RAH _SFR_IO8(0x2B) +-#define OCR0RA_8 0 +-#define OCR0RA_9 1 +-#define OCR0RA_00 2 +-#define OCR0RA_01 3 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x2C) +-#endif +-#define ADCW _SFR_IO16(0x2C) +- +-#define ADCL _SFR_IO8(0x2C) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_IO8(0x2D) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define OCR2RA _SFR_IO16(0x2E) +- +-#define OCR2RAL _SFR_IO8(0x2E) +-#define OCR2RA_0 0 +-#define OCR2RA_1 1 +-#define OCR2RA_2 2 +-#define OCR2RA_3 3 +-#define OCR2RA_4 4 +-#define OCR2RA_5 5 +-#define OCR2RA_6 6 +-#define OCR2RA_7 7 +- +-#define OCR2RAH _SFR_IO8(0x2F) +-#define OCR2RA_8 0 +-#define OCR2RA_9 1 +-#define OCR2RA_10 2 +-#define OCR2RA_11 3 +- +-#define DWDR _SFR_IO8(0x31) +- +-#define MSMCR _SFR_IO8(0x32) +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define CKRC81 2 +-#define RSTDIS 3 +-#define PUD 4 +- +-#define SPDR _SFR_IO8(0x36) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define SIGRD 5 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define DAC _SFR_IO16(0x38) +- +-#define DACL _SFR_IO8(0x38) +-#define DACL0 0 +-#define DACL1 1 +-#define DACL2 2 +-#define DACL3 3 +-#define DACL4 4 +-#define DACL5 5 +-#define DACL6 6 +-#define DACL7 7 +- +-#define DACH _SFR_IO8(0x39) +-#define DACH0 0 +-#define DACH1 1 +-#define DACH2 2 +-#define DACH3 3 +-#define DACH4 4 +-#define DACH5 5 +-#define DACH6 6 +-#define DACH7 7 +- +-#define TCNT1 _SFR_IO16(0x3A) +- +-#define TCNT1L _SFR_IO8(0x3A) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_IO8(0x3B) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define OCR0SA _SFR_MEM16(0x60) +- +-#define OCR0SAL _SFR_MEM8(0x60) +-#define OCR0SA_0 0 +-#define OCR0SA_1 1 +-#define OCR0SA_2 2 +-#define OCR0SA_3 3 +-#define OCR0SA_4 4 +-#define OCR0SA_5 5 +-#define OCR0SA_6 6 +-#define OCR0SA_7 7 +- +-#define OCR0SAH _SFR_MEM8(0x61) +-#define OCR0SA_8 0 +-#define OCR0SA_9 1 +-#define OCR0SA_00 2 +-#define OCR0SA_01 3 +- +-#define PFRC0A _SFR_MEM8(0x62) +-#define PRFM0A0 0 +-#define PRFM0A1 1 +-#define PRFM0A2 2 +-#define PRFM0A3 3 +-#define PFLTE0A 4 +-#define PELEV0A 5 +-#define PISEL0A 6 +-#define PCAE0A 7 +- +-#define PFRC0B _SFR_MEM8(0x63) +-#define PRFM0B0 0 +-#define PRFM0B1 1 +-#define PRFM0B2 2 +-#define PRFM0B3 3 +-#define PFLTE0B 4 +-#define PELEV0B 5 +-#define PISEL0B 6 +-#define PCAE0B 7 +- +-#define OCR2SA _SFR_MEM16(0x64) +- +-#define OCR2SAL _SFR_MEM8(0x64) +-#define OCR2SA_0 0 +-#define OCR2SA_1 1 +-#define OCR2SA_2 2 +-#define OCR2SA_3 3 +-#define OCR2SA_4 4 +-#define OCR2SA_5 5 +-#define OCR2SA_6 6 +-#define OCR2SA_7 7 +- +-#define OCR2SAH _SFR_MEM8(0x65) +-#define OCR2SA_8 0 +-#define OCR2SA_9 1 +-#define OCR2SA_10 2 +-#define OCR2SA_11 3 +- +-#define PFRC2A _SFR_MEM8(0x66) +-#define PRFM2A0 0 +-#define PRFM2A1 1 +-#define PRFM2A2 2 +-#define PRFM2A3 3 +-#define PFLTE2A 4 +-#define PELEV2A 5 +-#define PISEL2A 6 +-#define PCAE2A 7 +- +-#define PFRC2B _SFR_MEM8(0x67) +-#define PRFM2B0 0 +-#define PRFM2B1 1 +-#define PRFM2B2 2 +-#define PRFM2B3 3 +-#define PFLTE2B 4 +-#define PELEV2B 5 +-#define PISEL2B 6 +-#define PCAE2B 7 +- +-#define PICR0 _SFR_MEM16(0x68) +- +-#define PICR0L _SFR_MEM8(0x68) +-#define PICR0_0 0 +-#define PICR0_1 1 +-#define PICR0_2 2 +-#define PICR0_3 3 +-#define PICR0_4 4 +-#define PICR0_5 5 +-#define PICR0_6 6 +-#define PICR0_7 7 +- +-#define PICR0H _SFR_MEM8(0x69) +-#define PICR0_8 0 +-#define PICR0_9 1 +-#define PICR0_10 2 +-#define PICR0_11 3 +-#define PCST0 7 +- +-#define PSOC0 _SFR_MEM8(0x6A) +-#define POEN0A 0 +-#define POEN0B 2 +-#define PSYNC00 4 +-#define PSYNC01 5 +-#define PISEL0B1 6 +-#define PISEL0A1 7 +- +-#define PICR2 _SFR_MEM16(0x6C) +- +-#define PICR2L _SFR_MEM8(0x6C) +-#define PICR2_0 0 +-#define PICR2_1 1 +-#define PICR2_2 2 +-#define PICR2_3 3 +-#define PICR2_4 4 +-#define PICR2_5 5 +-#define PICR2_6 6 +-#define PICR2_7 7 +- +-#define PICR2H _SFR_MEM8(0x6D) +-#define PICR2_8 0 +-#define PICR2_9 1 +-#define PICR2_10 2 +-#define PICR2_11 3 +-#define PCST2 7 +- +-#define PSOC2 _SFR_MEM8(0x6E) +-#define POEN2A 0 +-#define POEN2C 1 +-#define POEN2B 2 +-#define POEN2D 3 +-#define PSYNC2_0 4 +-#define PSYNC2_1 5 +-#define POS22 6 +-#define POS23 7 +- +-#define POM2 _SFR_MEM8(0x6F) +-#define POMV2A0 0 +-#define POMV2A1 1 +-#define POMV2A2 2 +-#define POMV2A3 3 +-#define POMV2B0 4 +-#define POMV2B1 5 +-#define POMV2B2 6 +-#define POMV2B3 7 +- +-#define PCNFE2 _SFR_MEM8(0x70) +-#define PISEL2B1 0 +-#define PISEL2A1 1 +-#define PELEV2B1 2 +-#define PELEV2A1 3 +-#define PBFM21 4 +-#define PASDLK20 5 +-#define PASDLK21 6 +-#define PASDLK22 7 +- +-#define PASDLY2 _SFR_MEM8(0x71) +-#define PASDLY2_0 0 +-#define PASDLY2_1 1 +-#define PASDLY2_2 2 +-#define PASDLY2_3 3 +-#define PASDLY2_4 4 +-#define PASDLY2_5 5 +-#define PASDLY2_6 6 +-#define PASDLY2_7 7 +- +-#define DACON _SFR_MEM8(0x76) +-#define DAEN 0 +-#define DALA 2 +-#define DATS0 4 +-#define DATS1 5 +-#define DATS2 6 +-#define DAATE 7 +- +-#define DIDR0 _SFR_MEM8(0x77) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC7D 6 +-#define ADC8D 7 +- +-#define DIDR1 _SFR_MEM8(0x78) +-#define ADC9D 0 +-#define ADC10D 1 +-#define AMP0PD 2 +-#define ACMP1MD 3 +- +-#define AMP0CSR _SFR_MEM8(0x79) +-#define AMP0TS0 0 +-#define AMP0TS1 1 +-#define AMP0GS 3 +-#define AMP0G0 4 +-#define AMP0G1 5 +-#define AMP0IS 6 +-#define AMP0EN 7 +- +-#define AC1ECON _SFR_MEM8(0x7A) +-#define AC1H0 0 +-#define AC1H1 1 +-#define AC1H2 2 +-#define AC1ICE 3 +-#define AC1OE 4 +-#define AC1OI 5 +- +-#define AC2ECON _SFR_MEM8(0x7B) +-#define AC2H0 0 +-#define AC2H1 1 +-#define AC2H2 2 +-#define AC2OE 4 +-#define AC2OI 5 +- +-#define AC3ECON _SFR_MEM8(0x7C) +-#define AC3H0 0 +-#define AC3H1 1 +-#define AC3H2 2 +-#define AC3OE 4 +-#define AC3OI 5 +- +-#define AC1CON _SFR_MEM8(0x7D) +-#define AC1M0 0 +-#define AC1M1 1 +-#define AC1M2 2 +-#define AC1IS0 4 +-#define AC1IS1 5 +-#define AC1IE 6 +-#define AC1EN 7 +- +-#define AC2CON _SFR_MEM8(0x7E) +-#define AC2M0 0 +-#define AC2M1 1 +-#define AC2M2 2 +-#define AC2IS0 4 +-#define AC2IS1 5 +-#define AC2IE 6 +-#define AC2EN 7 +- +-#define AC3CON _SFR_MEM8(0x7F) +-#define AC3M0 0 +-#define AC3M1 1 +-#define AC3M2 2 +-#define AC3OEA 3 +-#define AC3IS0 4 +-#define AC3IS1 5 +-#define AC3IE 6 +-#define AC3EN 7 +- +-#define BGCRR _SFR_MEM8(0x80) +-#define BGCR0 0 +-#define BGCR1 1 +-#define BGCR2 2 +-#define BGCR3 3 +- +-#define BGCCR _SFR_MEM8(0x81) +-#define BGCC0 0 +-#define BGCC1 1 +-#define BGCC2 2 +-#define BGCC3 3 +- +-#define WDTCSR _SFR_MEM8(0x82) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x83) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define CLKCSR _SFR_MEM8(0x84) +-#define CLKC0 0 +-#define CLKC1 1 +-#define CLKC2 2 +-#define CLKC3 3 +-#define CLKRDY 4 +-#define CLKCCE 7 +- +-#define CLKSELR _SFR_MEM8(0x85) +-#define CKSEL0 0 +-#define CKSEL1 1 +-#define CKSEL2 2 +-#define CKSEL3 3 +-#define CSUT0 4 +-#define CSUT1 5 +-#define COUT 6 +- +-#define PRR _SFR_MEM8(0x86) +-#define PRADC 0 +-#define PRSPI 2 +-#define PRTIM1 4 +-#define PRPSCR 5 +-#define PRPSC2 7 +- +-#define PLLCSR _SFR_MEM8(0x87) +-#define PLOCK 0 +-#define PLLE 1 +-#define PLLF0 2 +-#define PLLF1 3 +-#define PLLF2 4 +-#define PLLF3 5 +- +-#define OSCCAL _SFR_MEM8(0x88) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define EICRA _SFR_MEM8(0x89) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define ISC20 4 +-#define ISC21 5 +- +-#define TCCR1B _SFR_MEM8(0x8A) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define ICR1 _SFR_MEM16(0x8C) +- +-#define ICR1L _SFR_MEM8(0x8C) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x8D) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define PSC2_CAPT_vect_num 1 +-#define PSC2_CAPT_vect _VECTOR(1) /* PSC2 Capture Event */ +-#define PSC2_EC_vect_num 2 +-#define PSC2_EC_vect _VECTOR(2) /* PSC2 End Cycle */ +-#define PSC2_EEC_vect_num 3 +-#define PSC2_EEC_vect _VECTOR(3) /* PSC2 End Of Enhanced Cycle */ +-#define PSC0_CAPT_vect_num 4 +-#define PSC0_CAPT_vect _VECTOR(4) /* PSC0 Capture Event */ +-#define PSC0_EC_vect_num 5 +-#define PSC0_EC_vect _VECTOR(5) /* PSC0 End Cycle */ +-#define PSC0_EEC_vect_num 6 +-#define PSC0_EEC_vect _VECTOR(6) /* PSC0 End Of Enhanced Cycle */ +-#define ANALOG_COMP_1_vect_num 7 +-#define ANALOG_COMP_1_vect _VECTOR(7) /* Analog Comparator 1 */ +-#define ANALOG_COMP_2_vect_num 8 +-#define ANALOG_COMP_2_vect _VECTOR(8) /* Analog Comparator 2 */ +-#define ANALOG_COMP_3_vect_num 9 +-#define ANALOG_COMP_3_vect _VECTOR(9) /* Analog Comparator 3 */ +-#define INT0_vect_num 10 +-#define INT0_vect _VECTOR(10) /* External Interrupt Request 0 */ +-#define TIMER1_CAPT_vect_num 11 +-#define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */ +-#define TIMER1_OVF_vect_num 12 +-#define TIMER1_OVF_vect _VECTOR(12) /* Timer/Counter1 Overflow */ +-#define ADC_vect_num 13 +-#define ADC_vect _VECTOR(13) /* ADC Conversion Complete */ +-#define INT1_vect_num 14 +-#define INT1_vect _VECTOR(14) /* External Interrupt Request 1 */ +-#define SPI_STC_vect_num 15 +-#define SPI_STC_vect _VECTOR(15) /* SPI Serial Transfer Complet */ +-#define INT2_vect_num 16 +-#define INT2_vect _VECTOR(16) /* External Interrupt Request 2 */ +-#define WDT_vect_num 17 +-#define WDT_vect _VECTOR(17) /* Watchdog Timeout Interrupt */ +-#define EE_READY_vect_num 18 +-#define EE_READY_vect _VECTOR(18) /* EEPROM Ready */ +-#define SPM_READY_vect_num 19 +-#define SPM_READY_vect _VECTOR(19) /* Store Program Memory Read */ +- +-#define _VECTOR_SIZE 2 /* Size of individual vector. */ +-#define _VECTORS_SIZE (20 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (64) +-#define RAMSTART (0x0100) +-#define RAMSIZE (256) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x1FF) +-#define E2PAGESIZE (4) +-#define FLASHEND (0x1FFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown out detector trigger level */ +-#define FUSE_PSCINRB (unsigned char)~_BV(3) /* PSC2 & PSC0 Input Reset Behavior */ +-#define FUSE_PSCRV (unsigned char)~_BV(4) /* PSCOUT Reset Value */ +-#define FUSE_PSC0RB (unsigned char)~_BV(5) /* PSC0 Reset Behaviour */ +-#define FUSE_PSC2RBA (unsigned char)~_BV(6) /* PSC2 Rest Behavior for out OUT22 & 23 */ +-#define FUSE_PSC2RB (unsigned char)~_BV(7) /* PSC2 Reset Behaviour */ +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x93 +-#define SIGNATURE_2 0x88 +- +- +-#endif /* _AVR_AT90PWM81_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: io90pwm81.h 2206 2011-02-11 06:58:02Z aboyapati $ */ ++ ++/* avr/io90pwm81.h - definitions for AT90PWM81 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "io90pwm81.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_AT90PWM81_H_ ++#define _AVR_AT90PWM81_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define ACSR _SFR_IO8(0x00) ++#define AC1O 1 ++#define AC2O 2 ++#define AC3O 3 ++#define AC1IF 5 ++#define AC2IF 6 ++#define AC3IF 7 ++ ++#define TIMSK1 _SFR_IO8(0x01) ++#define TOIE1 0 ++#define ICIE1 5 ++ ++#define TIFR1 _SFR_IO8(0x02) ++#define TOV1 0 ++#define ICF1 5 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define ADCSRA _SFR_IO8(0x06) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_IO8(0x07) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ADTS3 3 ++#define ADSSEN 4 ++#define ADNCDIS 6 ++#define ADHSM 7 ++ ++#define ADMUX _SFR_IO8(0x08) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE0 0 ++#define PINE1 1 ++#define PINE2 2 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE0 0 ++#define DDE1 1 ++#define DDE2 2 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE0 0 ++#define PORTE1 1 ++#define PORTE2 2 ++ ++#define PIM0 _SFR_IO8(0x0F) ++#define PEOPE0 0 ++#define PEOEPE0 1 ++#define PEVE0A 3 ++#define PEVE0B 4 ++ ++#define PIFR0 _SFR_IO8(0x10) ++#define PEOP0 0 ++#define PRN00 1 ++#define PRN01 2 ++#define PEV0A 3 ++#define PEV0B 4 ++#define POAC0A 6 ++#define POAC0B 7 ++ ++#define PCNF0 _SFR_IO8(0x11) ++#define PCLKSEL0 1 ++#define POP0 2 ++#define PMODE00 3 ++#define PMODE01 4 ++#define PLOCK0 5 ++#define PALOCK0 6 ++#define PFIFTY0 7 ++ ++#define PCTL0 _SFR_IO8(0x12) ++#define PRUN0 0 ++#define PCCYC0 1 ++#define PBFM00 2 ++#define PAOC0A 3 ++#define PAOC0B 4 ++#define PBFM01 5 ++#define PPRE00 6 ++#define PPRE01 7 ++ ++#define PIM2 _SFR_IO8(0x13) ++#define PEOPE2 0 ++#define PEOEPE2 1 ++#define PEVE2A 3 ++#define PEVE2B 4 ++#define PSEIE2 5 ++ ++#define PIFR2 _SFR_IO8(0x14) ++#define PEOP2 0 ++#define PRN20 1 ++#define PRN21 2 ++#define PEV2A 3 ++#define PEV2B 4 ++#define PSEI2 5 ++#define POAC2A 6 ++#define POAC2B 7 ++ ++#define PCNF2 _SFR_IO8(0x15) ++#define POME2 0 ++#define PCLKSEL2 1 ++#define POP2 2 ++#define PMODE20 3 ++#define PMODE21 4 ++#define PLOCK2 5 ++#define PALOCK2 6 ++#define PFIFTY2 7 ++ ++#define PCTL2 _SFR_IO8(0x16) ++#define PRUN2 0 ++#define PCCYC2 1 ++#define PARUN2 2 ++#define PAOC2A 3 ++#define PAOC2B 4 ++#define PBFM2 5 ++#define PPRE20 6 ++#define PPRE21 7 ++ ++#define SPCR _SFR_IO8(0x17) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x18) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define GPIOR0 _SFR_IO8(0x19) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define GPIOR1 _SFR_IO8(0x1A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x1B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define EECR _SFR_IO8(0x1C) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++#define EEPAGE 6 ++#define NVMBSY 7 ++ ++#define EEDR _SFR_IO8(0x1D) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x1E) ++ ++#define EEARL _SFR_IO8(0x1E) ++#define EEARL0 0 ++#define EEARL1 1 ++#define EEARL2 2 ++#define EEARL3 3 ++#define EEARL4 4 ++#define EEARL5 5 ++#define EEARL6 6 ++#define EEARL7 7 ++ ++#define EEARH _SFR_IO8(0x1F) ++#define EEAR8 0 ++ ++#define EIFR _SFR_IO8(0x20) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++ ++#define EIMSK _SFR_IO8(0x21) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++ ++#define OCR0SB _SFR_IO16(0x22) ++ ++#define OCR0SBL _SFR_IO8(0x22) ++#define OCR0SB_0 0 ++#define OCR0SB_1 1 ++#define OCR0SB_2 2 ++#define OCR0SB_3 3 ++#define OCR0SB_4 4 ++#define OCR0SB_5 5 ++#define OCR0SB_6 6 ++#define OCR0SB_7 7 ++ ++#define OCR0SBH _SFR_IO8(0x23) ++#define OCR0SB_8 0 ++#define OCR0SB_9 1 ++#define OCR0SB_00 2 ++#define OCR0SB_01 3 ++ ++#define OCR0RB _SFR_IO16(0x24) ++ ++#define OCR0RBL _SFR_IO8(0x24) ++#define OCR0RB_0 0 ++#define OCR0RB_1 1 ++#define OCR0RB_2 2 ++#define OCR0RB_3 3 ++#define OCR0RB_4 4 ++#define OCR0RB_5 5 ++#define OCR0RB_6 6 ++#define OCR0RB_7 7 ++ ++#define OCR0RBH _SFR_IO8(0x25) ++#define OCR0RB_8 0 ++#define OCR0RB_9 1 ++#define OCR0RB_00 2 ++#define OCR0RB_01 3 ++#define OCR0RB_02 4 ++#define OCR0RB_03 5 ++#define OCR0RB_04 6 ++#define OCR0RB_05 7 ++ ++#define OCR2SB _SFR_IO16(0x26) ++ ++#define OCR2SBL _SFR_IO8(0x26) ++#define OCR2SB_0 0 ++#define OCR2SB_1 1 ++#define OCR2SB_2 2 ++#define OCR2SB_3 3 ++#define OCR2SB_4 4 ++#define OCR2SB_5 5 ++#define OCR2SB_6 6 ++#define OCR2SB_7 7 ++ ++#define OCR2SBH _SFR_IO8(0x27) ++#define OCR2SB_8 0 ++#define OCR2SB_9 1 ++#define OCR2SB_10 2 ++#define OCR2SB_11 3 ++ ++#define OCR2RB _SFR_IO16(0x28) ++ ++#define OCR2RBL _SFR_IO8(0x28) ++#define OCR2RB_0 0 ++#define OCR2RB_1 1 ++#define OCR2RB_2 2 ++#define OCR2RB_3 3 ++#define OCR2RB_4 4 ++#define OCR2RB_5 5 ++#define OCR2RB_6 6 ++#define OCR2RB_7 7 ++ ++#define OCR2RBH _SFR_IO8(0x29) ++#define OCR2RB_8 0 ++#define OCR2RB_9 1 ++#define OCR2RB_10 2 ++#define OCR2RB_11 3 ++#define OCR2RB_12 4 ++#define OCR2RB_13 5 ++#define OCR2RB_14 6 ++#define OCR2RB_15 7 ++ ++#define OCR0RA _SFR_IO16(0x2A) ++ ++#define OCR0RAL _SFR_IO8(0x2A) ++#define OCR0RA_0 0 ++#define OCR0RA_1 1 ++#define OCR0RA_2 2 ++#define OCR0RA_3 3 ++#define OCR0RA_4 4 ++#define OCR0RA_5 5 ++#define OCR0RA_6 6 ++#define OCR0RA_7 7 ++ ++#define OCR0RAH _SFR_IO8(0x2B) ++#define OCR0RA_8 0 ++#define OCR0RA_9 1 ++#define OCR0RA_00 2 ++#define OCR0RA_01 3 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x2C) ++#endif ++#define ADCW _SFR_IO16(0x2C) ++ ++#define ADCL _SFR_IO8(0x2C) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_IO8(0x2D) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define OCR2RA _SFR_IO16(0x2E) ++ ++#define OCR2RAL _SFR_IO8(0x2E) ++#define OCR2RA_0 0 ++#define OCR2RA_1 1 ++#define OCR2RA_2 2 ++#define OCR2RA_3 3 ++#define OCR2RA_4 4 ++#define OCR2RA_5 5 ++#define OCR2RA_6 6 ++#define OCR2RA_7 7 ++ ++#define OCR2RAH _SFR_IO8(0x2F) ++#define OCR2RA_8 0 ++#define OCR2RA_9 1 ++#define OCR2RA_10 2 ++#define OCR2RA_11 3 ++ ++#define DWDR _SFR_IO8(0x31) ++ ++#define MSMCR _SFR_IO8(0x32) ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define CKRC81 2 ++#define RSTDIS 3 ++#define PUD 4 ++ ++#define SPDR _SFR_IO8(0x36) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define DAC _SFR_IO16(0x38) ++ ++#define DACL _SFR_IO8(0x38) ++#define DACL0 0 ++#define DACL1 1 ++#define DACL2 2 ++#define DACL3 3 ++#define DACL4 4 ++#define DACL5 5 ++#define DACL6 6 ++#define DACL7 7 ++ ++#define DACH _SFR_IO8(0x39) ++#define DACH0 0 ++#define DACH1 1 ++#define DACH2 2 ++#define DACH3 3 ++#define DACH4 4 ++#define DACH5 5 ++#define DACH6 6 ++#define DACH7 7 ++ ++#define TCNT1 _SFR_IO16(0x3A) ++ ++#define TCNT1L _SFR_IO8(0x3A) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_IO8(0x3B) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define OCR0SA _SFR_MEM16(0x60) ++ ++#define OCR0SAL _SFR_MEM8(0x60) ++#define OCR0SA_0 0 ++#define OCR0SA_1 1 ++#define OCR0SA_2 2 ++#define OCR0SA_3 3 ++#define OCR0SA_4 4 ++#define OCR0SA_5 5 ++#define OCR0SA_6 6 ++#define OCR0SA_7 7 ++ ++#define OCR0SAH _SFR_MEM8(0x61) ++#define OCR0SA_8 0 ++#define OCR0SA_9 1 ++#define OCR0SA_00 2 ++#define OCR0SA_01 3 ++ ++#define PFRC0A _SFR_MEM8(0x62) ++#define PRFM0A0 0 ++#define PRFM0A1 1 ++#define PRFM0A2 2 ++#define PRFM0A3 3 ++#define PFLTE0A 4 ++#define PELEV0A 5 ++#define PISEL0A 6 ++#define PCAE0A 7 ++ ++#define PFRC0B _SFR_MEM8(0x63) ++#define PRFM0B0 0 ++#define PRFM0B1 1 ++#define PRFM0B2 2 ++#define PRFM0B3 3 ++#define PFLTE0B 4 ++#define PELEV0B 5 ++#define PISEL0B 6 ++#define PCAE0B 7 ++ ++#define OCR2SA _SFR_MEM16(0x64) ++ ++#define OCR2SAL _SFR_MEM8(0x64) ++#define OCR2SA_0 0 ++#define OCR2SA_1 1 ++#define OCR2SA_2 2 ++#define OCR2SA_3 3 ++#define OCR2SA_4 4 ++#define OCR2SA_5 5 ++#define OCR2SA_6 6 ++#define OCR2SA_7 7 ++ ++#define OCR2SAH _SFR_MEM8(0x65) ++#define OCR2SA_8 0 ++#define OCR2SA_9 1 ++#define OCR2SA_10 2 ++#define OCR2SA_11 3 ++ ++#define PFRC2A _SFR_MEM8(0x66) ++#define PRFM2A0 0 ++#define PRFM2A1 1 ++#define PRFM2A2 2 ++#define PRFM2A3 3 ++#define PFLTE2A 4 ++#define PELEV2A 5 ++#define PISEL2A 6 ++#define PCAE2A 7 ++ ++#define PFRC2B _SFR_MEM8(0x67) ++#define PRFM2B0 0 ++#define PRFM2B1 1 ++#define PRFM2B2 2 ++#define PRFM2B3 3 ++#define PFLTE2B 4 ++#define PELEV2B 5 ++#define PISEL2B 6 ++#define PCAE2B 7 ++ ++#define PICR0 _SFR_MEM16(0x68) ++ ++#define PICR0L _SFR_MEM8(0x68) ++#define PICR0_0 0 ++#define PICR0_1 1 ++#define PICR0_2 2 ++#define PICR0_3 3 ++#define PICR0_4 4 ++#define PICR0_5 5 ++#define PICR0_6 6 ++#define PICR0_7 7 ++ ++#define PICR0H _SFR_MEM8(0x69) ++#define PICR0_8 0 ++#define PICR0_9 1 ++#define PICR0_10 2 ++#define PICR0_11 3 ++#define PCST0 7 ++ ++#define PSOC0 _SFR_MEM8(0x6A) ++#define POEN0A 0 ++#define POEN0B 2 ++#define PSYNC00 4 ++#define PSYNC01 5 ++#define PISEL0B1 6 ++#define PISEL0A1 7 ++ ++#define PICR2 _SFR_MEM16(0x6C) ++ ++#define PICR2L _SFR_MEM8(0x6C) ++#define PICR2_0 0 ++#define PICR2_1 1 ++#define PICR2_2 2 ++#define PICR2_3 3 ++#define PICR2_4 4 ++#define PICR2_5 5 ++#define PICR2_6 6 ++#define PICR2_7 7 ++ ++#define PICR2H _SFR_MEM8(0x6D) ++#define PICR2_8 0 ++#define PICR2_9 1 ++#define PICR2_10 2 ++#define PICR2_11 3 ++#define PCST2 7 ++ ++#define PSOC2 _SFR_MEM8(0x6E) ++#define POEN2A 0 ++#define POEN2C 1 ++#define POEN2B 2 ++#define POEN2D 3 ++#define PSYNC2_0 4 ++#define PSYNC2_1 5 ++#define POS22 6 ++#define POS23 7 ++ ++#define POM2 _SFR_MEM8(0x6F) ++#define POMV2A0 0 ++#define POMV2A1 1 ++#define POMV2A2 2 ++#define POMV2A3 3 ++#define POMV2B0 4 ++#define POMV2B1 5 ++#define POMV2B2 6 ++#define POMV2B3 7 ++ ++#define PCNFE2 _SFR_MEM8(0x70) ++#define PISEL2B1 0 ++#define PISEL2A1 1 ++#define PELEV2B1 2 ++#define PELEV2A1 3 ++#define PBFM21 4 ++#define PASDLK20 5 ++#define PASDLK21 6 ++#define PASDLK22 7 ++ ++#define PASDLY2 _SFR_MEM8(0x71) ++#define PASDLY2_0 0 ++#define PASDLY2_1 1 ++#define PASDLY2_2 2 ++#define PASDLY2_3 3 ++#define PASDLY2_4 4 ++#define PASDLY2_5 5 ++#define PASDLY2_6 6 ++#define PASDLY2_7 7 ++ ++#define DACON _SFR_MEM8(0x76) ++#define DAEN 0 ++#define DALA 2 ++#define DATS0 4 ++#define DATS1 5 ++#define DATS2 6 ++#define DAATE 7 ++ ++#define DIDR0 _SFR_MEM8(0x77) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC7D 6 ++#define ADC8D 7 ++ ++#define DIDR1 _SFR_MEM8(0x78) ++#define ADC9D 0 ++#define ADC10D 1 ++#define AMP0PD 2 ++#define ACMP1MD 3 ++ ++#define AMP0CSR _SFR_MEM8(0x79) ++#define AMP0TS0 0 ++#define AMP0TS1 1 ++#define AMP0GS 3 ++#define AMP0G0 4 ++#define AMP0G1 5 ++#define AMP0IS 6 ++#define AMP0EN 7 ++ ++#define AC1ECON _SFR_MEM8(0x7A) ++#define AC1H0 0 ++#define AC1H1 1 ++#define AC1H2 2 ++#define AC1ICE 3 ++#define AC1OE 4 ++#define AC1OI 5 ++ ++#define AC2ECON _SFR_MEM8(0x7B) ++#define AC2H0 0 ++#define AC2H1 1 ++#define AC2H2 2 ++#define AC2OE 4 ++#define AC2OI 5 ++ ++#define AC3ECON _SFR_MEM8(0x7C) ++#define AC3H0 0 ++#define AC3H1 1 ++#define AC3H2 2 ++#define AC3OE 4 ++#define AC3OI 5 ++ ++#define AC1CON _SFR_MEM8(0x7D) ++#define AC1M0 0 ++#define AC1M1 1 ++#define AC1M2 2 ++#define AC1IS0 4 ++#define AC1IS1 5 ++#define AC1IE 6 ++#define AC1EN 7 ++ ++#define AC2CON _SFR_MEM8(0x7E) ++#define AC2M0 0 ++#define AC2M1 1 ++#define AC2M2 2 ++#define AC2IS0 4 ++#define AC2IS1 5 ++#define AC2IE 6 ++#define AC2EN 7 ++ ++#define AC3CON _SFR_MEM8(0x7F) ++#define AC3M0 0 ++#define AC3M1 1 ++#define AC3M2 2 ++#define AC3OEA 3 ++#define AC3IS0 4 ++#define AC3IS1 5 ++#define AC3IE 6 ++#define AC3EN 7 ++ ++#define BGCRR _SFR_MEM8(0x80) ++#define BGCR0 0 ++#define BGCR1 1 ++#define BGCR2 2 ++#define BGCR3 3 ++ ++#define BGCCR _SFR_MEM8(0x81) ++#define BGCC0 0 ++#define BGCC1 1 ++#define BGCC2 2 ++#define BGCC3 3 ++ ++#define WDTCSR _SFR_MEM8(0x82) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x83) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define CLKCSR _SFR_MEM8(0x84) ++#define CLKC0 0 ++#define CLKC1 1 ++#define CLKC2 2 ++#define CLKC3 3 ++#define CLKRDY 4 ++#define CLKCCE 7 ++ ++#define CLKSELR _SFR_MEM8(0x85) ++#define CKSEL0 0 ++#define CKSEL1 1 ++#define CKSEL2 2 ++#define CKSEL3 3 ++#define CSUT0 4 ++#define CSUT1 5 ++#define COUT 6 ++ ++#define PRR _SFR_MEM8(0x86) ++#define PRADC 0 ++#define PRSPI 2 ++#define PRTIM1 4 ++#define PRPSCR 5 ++#define PRPSC2 7 ++ ++#define PLLCSR _SFR_MEM8(0x87) ++#define PLOCK 0 ++#define PLLE 1 ++#define PLLF0 2 ++#define PLLF1 3 ++#define PLLF2 4 ++#define PLLF3 5 ++ ++#define OSCCAL _SFR_MEM8(0x88) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define EICRA _SFR_MEM8(0x89) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++ ++#define TCCR1B _SFR_MEM8(0x8A) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define ICR1 _SFR_MEM16(0x8C) ++ ++#define ICR1L _SFR_MEM8(0x8C) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x8D) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define PSC2_CAPT_vect_num 1 ++#define PSC2_CAPT_vect _VECTOR(1) /* PSC2 Capture Event */ ++#define PSC2_EC_vect_num 2 ++#define PSC2_EC_vect _VECTOR(2) /* PSC2 End Cycle */ ++#define PSC2_EEC_vect_num 3 ++#define PSC2_EEC_vect _VECTOR(3) /* PSC2 End Of Enhanced Cycle */ ++#define PSC0_CAPT_vect_num 4 ++#define PSC0_CAPT_vect _VECTOR(4) /* PSC0 Capture Event */ ++#define PSC0_EC_vect_num 5 ++#define PSC0_EC_vect _VECTOR(5) /* PSC0 End Cycle */ ++#define PSC0_EEC_vect_num 6 ++#define PSC0_EEC_vect _VECTOR(6) /* PSC0 End Of Enhanced Cycle */ ++#define ANALOG_COMP_1_vect_num 7 ++#define ANALOG_COMP_1_vect _VECTOR(7) /* Analog Comparator 1 */ ++#define ANALOG_COMP_2_vect_num 8 ++#define ANALOG_COMP_2_vect _VECTOR(8) /* Analog Comparator 2 */ ++#define ANALOG_COMP_3_vect_num 9 ++#define ANALOG_COMP_3_vect _VECTOR(9) /* Analog Comparator 3 */ ++#define INT0_vect_num 10 ++#define INT0_vect _VECTOR(10) /* External Interrupt Request 0 */ ++#define TIMER1_CAPT_vect_num 11 ++#define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */ ++#define TIMER1_OVF_vect_num 12 ++#define TIMER1_OVF_vect _VECTOR(12) /* Timer/Counter1 Overflow */ ++#define ADC_vect_num 13 ++#define ADC_vect _VECTOR(13) /* ADC Conversion Complete */ ++#define INT1_vect_num 14 ++#define INT1_vect _VECTOR(14) /* External Interrupt Request 1 */ ++#define SPI_STC_vect_num 15 ++#define SPI_STC_vect _VECTOR(15) /* SPI Serial Transfer Complet */ ++#define INT2_vect_num 16 ++#define INT2_vect _VECTOR(16) /* External Interrupt Request 2 */ ++#define WDT_vect_num 17 ++#define WDT_vect _VECTOR(17) /* Watchdog Timeout Interrupt */ ++#define EE_READY_vect_num 18 ++#define EE_READY_vect _VECTOR(18) /* EEPROM Ready */ ++#define SPM_READY_vect_num 19 ++#define SPM_READY_vect _VECTOR(19) /* Store Program Memory Read */ ++ ++#define _VECTOR_SIZE 2 /* Size of individual vector. */ ++#define _VECTORS_SIZE (20 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (64) ++#define RAMSTART (0x0100) ++#define RAMSIZE (256) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x1FF) ++#define E2PAGESIZE (4) ++#define FLASHEND (0x1FFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown out detector trigger level */ ++#define FUSE_PSCINRB (unsigned char)~_BV(3) /* PSC2 & PSC0 Input Reset Behavior */ ++#define FUSE_PSCRV (unsigned char)~_BV(4) /* PSCOUT Reset Value */ ++#define FUSE_PSC0RB (unsigned char)~_BV(5) /* PSC0 Reset Behaviour */ ++#define FUSE_PSC2RBA (unsigned char)~_BV(6) /* PSC2 Rest Behavior for out OUT22 & 23 */ ++#define FUSE_PSC2RB (unsigned char)~_BV(7) /* PSC2 Reset Behaviour */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x88 ++ ++ ++#endif /* _AVR_AT90PWM81_H_ */ ++ +diff --git a/include/avr/io90pwmx.h b/include/avr/io90pwmx.h +index c0ce8e5..8dd107f 100644 +--- a/include/avr/io90pwmx.h ++++ b/include/avr/io90pwmx.h +@@ -1,1399 +1,1400 @@ +-/* Copyright (c) 2005, Andrey Pashchenko +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: io90pwmx.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* avr/io90pwmx.h - definitions for AT90PWM2(B) and AT90PWM3(B) */ +- +-#ifndef _AVR_IO90PWMX_H_ +-#define _AVR_IO90PWMX_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "io90pwmX.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* Port B Input Pins Address */ +-#define PINB _SFR_IO8(0x03) +-/* PINB */ +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* Port B Data Direction Register */ +-#define DDRB _SFR_IO8(0x04) +-/* DDRB */ +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* Port B Data Register */ +-#define PORTB _SFR_IO8(0x05) +-/* PORTB */ +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* Port C Input Pins Address */ +-#define PINC _SFR_IO8(0x06) +-/* PINC */ +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-/* Port C Data Direction Register */ +-#define DDRC _SFR_IO8(0x07) +-/* DDRC */ +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-/* Port C Data Register */ +-#define PORTC _SFR_IO8(0x08) +-/* PORTC */ +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-/* Port D Input Pins Address */ +-#define PIND _SFR_IO8(0x09) +-/* PIND */ +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-/* Port D Data Direction Register */ +-#define DDRD _SFR_IO8(0x0A) +-/* DDRD */ +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-/* Port D Data Register */ +-#define PORTD _SFR_IO8(0x0B) +-/* PORTD */ +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* Port E Input Pins Address */ +-#define PINE _SFR_IO8(0x0C) +-/* PINE */ +-#define PINE2 2 +-#define PINE1 1 +-#define PINE0 0 +- +-/* Port E Data Direction Register */ +-#define DDRE _SFR_IO8(0x0D) +-/* DDRE */ +-#define DDE2 2 +-#define DDE1 1 +-#define DDE0 0 +- +-/* Port E Data Register */ +-#define PORTE _SFR_IO8(0x0E) +-/* PORTE */ +-#define PE2 2 +-#define PE1 1 +-#define PE0 0 +- +-/* Timer/Counter 0 Interrupt Flag Register */ +-#define TIFR0 _SFR_IO8(0x15) +-/* TIFR0 */ +-#define OCF0B 2 /* Output Compare Flag 0B */ +-#define OCF0A 1 /* Output Compare Flag 0A */ +-#define TOV0 0 /* Overflow Flag */ +- +-/* Timer/Counter1 Interrupt Flag Register */ +-#define TIFR1 _SFR_IO8(0x16) +-/* TIFR1 */ +-#define ICF1 5 /* Input Capture Flag 1 */ +-#define OCF1B 2 /* Output Compare Flag 1B*/ +-#define OCF1A 1 /* Output Compare Flag 1A*/ +-#define TOV1 0 /* Overflow Flag */ +- +-/* General Purpose I/O Register 1 */ +-#define GPIOR1 _SFR_IO8(0x19) +-/* GPIOR1 */ +-#define GPIOR17 7 +-#define GPIOR16 6 +-#define GPIOR15 5 +-#define GPIOR14 4 +-#define GPIOR13 3 +-#define GPIOR12 2 +-#define GPIOR11 1 +-#define GPIOR10 0 +- +-/* General Purpose I/O Register 2 */ +-#define GPIOR2 _SFR_IO8(0x1A) +-/* GPIOR2 */ +-#define GPIOR27 7 +-#define GPIOR26 6 +-#define GPIOR25 5 +-#define GPIOR24 4 +-#define GPIOR23 3 +-#define GPIOR22 2 +-#define GPIOR21 1 +-#define GPIOR20 0 +- +-/* General Purpose I/O Register 3 */ +-#define GPIOR3 _SFR_IO8(0x1B) +-/* GPIOR3 */ +-#define GPIOR37 7 +-#define GPIOR36 6 +-#define GPIOR35 5 +-#define GPIOR34 4 +-#define GPIOR33 3 +-#define GPIOR32 2 +-#define GPIOR31 1 +-#define GPIOR30 0 +- +-/* External Interrupt Flag Register */ +-#define EIFR _SFR_IO8(0x1C) +-/* EIFR */ +-#define INTF3 3 +-#define INTF2 2 +-#define INTF1 1 +-#define INTF0 0 +- +-/* External Interrupt Mask Register */ +-#define EIMSK _SFR_IO8(0x1D) +-/* EIMSK */ +-#define INT3 3 /* External Interrupt Request 3 Enable */ +-#define INT2 2 /* External Interrupt Request 2 Enable */ +-#define INT1 1 /* External Interrupt Request 1 Enable */ +-#define INT0 0 /* External Interrupt Request 0 Enable */ +- +-/* General Purpose I/O Register 0 */ +-#define GPIOR0 _SFR_IO8(0x1E) +-/* GPIOR0 */ +-#define GPIOR07 7 +-#define GPIOR06 6 +-#define GPIOR05 5 +-#define GPIOR04 4 +-#define GPIOR03 3 +-#define GPIOR02 2 +-#define GPIOR01 1 +-#define GPIOR00 0 +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1F) +-/* EECR */ +-#define EERIE 3 /* EEPROM Ready Interrupt Enable */ +-#define EEMWE 2 /* EEPROM Master Write Enable */ +-#define EEWE 1 /* EEPROM Write Enable */ +-#define EERE 0 /* EEPROM Read Enable */ +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x20) +-/* EEDR */ +-#define EEDR7 7 +-#define EEDR6 6 +-#define EEDR5 5 +-#define EEDR4 4 +-#define EEDR3 3 +-#define EEDR2 2 +-#define EEDR1 1 +-#define EEDR0 0 +- +-/* The EEPROM Address Registers */ +-#define EEAR _SFR_IO16(0x21) +-#define EEARL _SFR_IO8(0x21) +-#define EEARH _SFR_IO8(0x22) +-/* EEARH */ +-#define EEAR11 3 +-#define EEAR10 2 +-#define EEAR9 1 +-#define EEAR8 0 +-/* EEARL */ +-#define EEAR7 7 +-#define EEAR6 6 +-#define EEAR5 5 +-#define EEAR4 4 +-#define EEAR3 3 +-#define EEAR2 2 +-#define EEAR1 1 +-#define EEAR0 0 +- +-/* 6-char sequence denoting where to find the EEPROM registers in memory space. +- Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM +- subroutines. +- First two letters: EECR address. +- Second two letters: EEDR address. +- Last two letters: EEAR address. */ +-#define __EEPROM_REG_LOCATIONS__ 1F2021 +- +-/* General Timer/Counter Control Register */ +-#define GTCCR _SFR_IO8(0x23) +-/* GTCCR */ +-#define TSM 7 /* Timer/Counter Synchronization Mode */ +-#define ICPSEL1 6 /* Timer1 Input Capture Selection Bit */ +-#define PSR10 0 /* Prescaler Reset Timer/Counter1 and Timer/Counter0 */ +- +-/* Timer/Counter Control Register A */ +-#define TCCR0A _SFR_IO8(0x24) +-/* TCCR0A */ +-#define COM0A1 7 /* Compare Output Mode, Phase Correct PWM Mode */ +-#define COM0A0 6 /* Compare Output Mode, Phase Correct PWM Mode */ +-#define COM0B1 5 /* Compare Output Mode, Fast PWm */ +-#define COM0B0 4 /* Compare Output Mode, Fast PWm */ +-#define WGM01 1 /* Waveform Generation Mode */ +-#define WGM00 0 /* Waveform Generation Mode */ +- +-/* Timer/Counter Control Register B */ +-#define TCCR0B _SFR_IO8(0x25) +-/* TCCR0B */ +-#define FOC0A 7 /* Force Output Compare A */ +-#define FOC0B 6 /* Force Output Compare B */ +-#define WGM02 3 /* Waveform Generation Mode */ +-#define CS02 2 /* Clock Select */ +-#define CS01 1 /* Clock Select */ +-#define CS00 0 /* Clock Select */ +- +-/* Timer/Counter0 Register */ +-#define TCNT0 _SFR_IO8(0x26) +-/* TCNT0 */ +-#define TCNT07 7 +-#define TCNT06 6 +-#define TCNT05 5 +-#define TCNT04 4 +-#define TCNT03 3 +-#define TCNT02 2 +-#define TCNT01 1 +-#define TCNT00 0 +- +-/* Timer/Counter0 Output Compare Register A */ +-#define OCR0A _SFR_IO8(0x27) +-/* OCR0A */ +-#define OCR0A7 7 +-#define OCR0A6 6 +-#define OCR0A5 5 +-#define OCR0A4 4 +-#define OCR0A3 3 +-#define OCR0A2 2 +-#define OCR0A1 1 +-#define OCR0A0 0 +- +-/* Timer/Counter0 Output Compare Register B */ +-#define OCR0B _SFR_IO8(0x28) +-/* OCR0B */ +-#define OCR0B7 7 +-#define OCR0B6 6 +-#define OCR0B5 5 +-#define OCR0B4 4 +-#define OCR0B3 3 +-#define OCR0B2 2 +-#define OCR0B1 1 +-#define OCR0B0 0 +- +-/* PLL Control and Status Register */ +-#define PLLCSR _SFR_IO8(0x29) +-/* PLLCSR */ +-#define PCKE 2 /* PCK Enable */ +-/* Bit 2 has been renamed in later versions of the datasheet. */ +-#define PLLF 2 /* PLL Factor */ +-#define PLLE 1 /* PLL Enable */ +-#define PLOCK 0 /* PLL Lock Detector */ +- +-/* SPI Control Register */ +-#define SPCR _SFR_IO8(0x2C) +-/* SPCR */ +-#define SPIE 7 /* SPI Interrupt Enable */ +-#define SPE 6 /* SPI Enable */ +-#define DORD 5 /* Data Order */ +-#define MSTR 4 /* Master/Slave Select */ +-#define CPOL 3 /* Clock polarity */ +-#define CPHA 2 /* Clock Phase */ +-#define SPR1 1 /* SPI Clock Rate Select 1 */ +-#define SPR0 0 /* SPI Clock Rate Select 0 */ +- +-/* SPI Status Register */ +-#define SPSR _SFR_IO8(0x2D) +-/* SPSR */ +-#define SPIF 7 /* SPI Interrupt Flag */ +-#define WCOL 6 /* Write Collision Flag */ +-#define SPI2X 0 /* Double SPI Speed Bit */ +- +-/* SPI Data Register */ +-#define SPDR _SFR_IO8(0x2E) +-/* SPDR */ +-#define SPD7 7 +-#define SPD6 6 +-#define SPD5 5 +-#define SPD4 4 +-#define SPD3 3 +-#define SPD2 2 +-#define SPD1 1 +-#define SPD0 0 +- +-/* Analog Comparator Status Register */ +-#define ACSR _SFR_IO8(0x30) +-/* ACSR */ +-#define ACCKDIV 7 /* Analog Comparator Clock Divider */ +-#define AC2IF 6 /* Analog Comparator 2 Interrupt Flag Bit */ +-#define AC1IF 5 /* Analog Comparator 1 Interrupt Flag Bit */ +-#define AC0IF 4 /* Analog Comparator 0 Interrupt Flag Bit */ +-#define AC2O 2 /* Analog Comparator 2 Output Bit */ +-#define AC1O 1 /* Analog Comparator 1 Output Bit */ +-#define AC0O 0 /* Analog Comparator 0 Output Bit */ +- +-/* Monitor Data Register */ +-#define MONDR _SFR_IO8(0x31) +- +-/* Monitor Stop Mode Control Register */ +-#define MSMCR _SFR_IO8(0x32) +- +-/* Sleep Mode Control Register */ +-#define SMCR _SFR_IO8(0x33) +-/* SMCR */ +-#define SM2 3 /* Sleep Mode Select bit2 */ +-#define SM1 2 /* Sleep Mode Select bit1 */ +-#define SM0 1 /* Sleep Mode Select bit0 */ +-#define SE 0 /* Sleep Enable */ +- +-/* MCU Status Register */ +-#define MCUSR _SFR_IO8(0x34) +-/* MCUSR */ +-#define WDRF 3 /* Watchdog Reset Flag */ +-#define BORF 2 /* Brown-out Reset Flag */ +-#define EXTRF 1 /* External Reset Flag */ +-#define PORF 0 /* Power-on reset flag */ +- +-/* MCU Control Register */ +-#define MCUCR _SFR_IO8(0x35) +-/* MCUCR */ +-#define SPIPS 7 /* SPI Pin Select */ +-#define PUD 4 /* Pull-up disable */ +-#define IVSEL 1 /* Interrupt Vector Select */ +-#define IVCE 0 /* Interrupt Vector Change Enable */ +- +-/* Store Program Memory Control Register */ +-#define SPMCSR _SFR_IO8(0x37) +-/* SPMCSR */ +-#define SPMIE 7 /* SPM Interrupt Enable */ +-#define RWWSB 6 /* Read While Write Section Busy */ +-#define RWWSRE 4 /* Read While Write section read enable */ +-#define BLBSET 3 /* Boot Lock Bit Set */ +-#define PGWRT 2 /* Page Write */ +-#define PGERS 1 /* Page Erase */ +-#define SPMEN 0 /* Store Program Memory Enable */ +- +-/* 0x3D..0x3E SP [defined in ] */ +-/* 0x3F SREG [defined in ] */ +- +-/* Watchdog Timer Control Register */ +-#define WDTCSR _SFR_MEM8(0x60) +-/* WDTCSR */ +-#define WDIF 7 /* Watchdog Timeout Interrupt Flag */ +-#define WDIE 6 /* Watchdog Timeout Interrupt Enable */ +-#define WDP3 5 /* Watchdog Timer Prescaler bit3 */ +-#define WDCE 4 /* Watchdog Change Enable */ +-#define WDE 3 /* Watchdog Enable */ +-#define WDP2 2 /* Watchdog Timer Prescaler bit2 */ +-#define WDP1 1 /* Watchdog Timer Prescaler bit1 */ +-#define WDP0 0 /* Watchdog Timer Prescaler bit0 */ +- +-/* Clock Prescaler Register */ +-#define CLKPR _SFR_MEM8(0x61) +-/* CLKPR */ +-#define CLKPCE 7 /* Clock Prescaler Change Enable */ +-#define CLKPS3 3 /* Clock Prescaler Select bit3 */ +-#define CLKPS2 2 /* Clock Prescaler Select bit2 */ +-#define CLKPS1 1 /* Clock Prescaler Select bit1 */ +-#define CLKPS0 0 /* Clock Prescaler Select bit0 */ +- +-/* Power Reduction Register */ +-#define PRR _SFR_MEM8(0x64) +-/* PRR */ +-#define PRPSC2 7 /* Power Reduction PSC2 */ +-#define PRPSC1 6 /* Power Reduction PSC1 */ +-#define PRPSC0 5 /* Power Reduction PSC0 */ +-#define PRTIM1 4 /* Power Reduction Timer/Counter1 */ +-#define PRTIM0 3 /* Power Reduction Timer/Counter0 */ +-#define PRSPI 2 /* Power Reduction Serial Peripheral Interface */ +-#define PRUSART 1 /* Power Reduction USART */ +-#define PRADC 0 /* Power Reduction ADC */ +- +-/* Oscillator Calibration Value */ +-#define OSCCAL _SFR_MEM8(0x66) +-/* OSCCAL */ +-#define CAL6 6 +-#define CAL5 5 +-#define CAL4 4 +-#define CAL3 3 +-#define CAL2 2 +-#define CAL1 1 +-#define CAL0 0 +- +-/* External Interrupt Control Register A */ +-#define EICRA _SFR_MEM8(0x69) +-/* EICRA */ +-#define ISC31 7 +-#define ISC30 6 +-#define ISC21 5 +-#define ISC20 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-/* Timer/Counter0 Interrupt Mask Register */ +-#define TIMSK0 _SFR_MEM8(0x6E) +-/* TIMSK0 */ +-#define OCIE0B 2 /* Output Compare Match B Interrupt Enable */ +-#define OCIE0A 1 /* Output Compare Match A Interrupt Enable */ +-#define TOIE0 0 /* Overflow Interrupt Enable */ +- +-/* Timer/Counter1 Interrupt Mask Register */ +-#define TIMSK1 _SFR_MEM8(0x6F) +-/* TIMSK1 */ +-#define ICIE1 5 /* Input Capture Interrupt Enable */ +-#define OCIE1B 2 /* Output Compare Match B Interrupt Enable */ +-#define OCIE1A 1 /* Output Compare Match A Interrupt Enable */ +-#define TOIE1 0 /* Overflow Interrupt Enable */ +- +-/* Amplifier 0 Control and Status register */ +-#define AMP0CSR _SFR_MEM8(0x76) +-#define AMP0EN 7 +-#define AMP0IS 6 +-#define AMP0G1 5 +-#define AMP0G0 4 +-#define AMP0TS1 1 +-#define AMP0TS0 0 +- +-/* Amplifier 1 Control and Status register */ +-#define AMP1CSR _SFR_MEM8(0x77) +-#define AMP1EN 7 +-#define AMP1IS 6 +-#define AMP1G1 5 +-#define AMP1G0 4 +-#define AMP1TS1 1 +-#define AMP1TS0 0 +- +-/* ADC Result Data Register */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +-#define ADCL _SFR_MEM8(0x78) +-#define ADCH _SFR_MEM8(0x79) +- +-/* ADC Control and Status Register A */ +-#define ADCSRA _SFR_MEM8(0x7A) +-/* ADCSRA */ +-#define ADEN 7 /* ADC Enable */ +-#define ADSC 6 /* ADC Start Conversion */ +-#define ADATE 5 /* ADC Auto Trigger Enable */ +-#define ADIF 4 /* ADC Interrupt Flag */ +-#define ADIE 3 /* ADC Interrupt Enable */ +-#define ADPS2 2 /* ADC Prescaler Select bit2 */ +-#define ADPS1 1 /* ADC Prescaler Select bit1 */ +-#define ADPS0 0 /* ADC Prescaler Select bit0 */ +- +-/* ADC Control and Status Register B */ +-#define ADCSRB _SFR_MEM8(0x7B) +-/* ADCSRB */ +-#define ADHSM 7 /* ADC High Speed Mode */ +-#define ADASCR 4 +-#define ADTS3 3 /* ADC Auto Trigger Source 3 */ +-#define ADTS2 2 /* ADC Auto Trigger Source 2 */ +-#define ADTS1 1 /* ADC Auto Trigger Source 1 */ +-#define ADTS0 0 /* ADC Auto Trigger Source 0 */ +- +-/* ADC multiplexer Selection Register */ +-#define ADMUX _SFR_MEM8(0x7C) +-/* ADMUX */ +-#define REFS1 7 /* Reference Selection bit1 */ +-#define REFS0 6 /* Reference Selection bit0 */ +-#define ADLAR 5 /* Left Adjust Result */ +-#define MUX3 3 /* Analog Channel and Gain Selection bit3 */ +-#define MUX2 2 /* Analog Channel and Gain Selection bit2 */ +-#define MUX1 1 /* Analog Channel and Gain Selection bit1 */ +-#define MUX0 0 /* Analog Channel and Gain Selection bit0 */ +- +-/* Digital Input Disable Register 0 */ +-#define DIDR0 _SFR_MEM8(0x7E) +-/* DIDR0 */ +-#define ADC7D 7 /* ADC7 Digital input Disable */ +-#define ADC6D 6 /* ADC6 Digital input Disable */ +-#define ADC5D 5 /* ADC5 Digital input Disable */ +-#define ADC4D 4 /* ADC4 Digital input Disable */ +-#define ADC3D 3 /* ADC3 Digital input Disable */ +-#define ADC2D 2 /* ADC2 Digital input Disable */ +-#define ADC1D 1 /* ADC1 Digital input Disable */ +-#define ADC0D 0 /* ADC0 Digital input Disable */ +- +-/* Digital Input Disable Register 1 */ +-#define DIDR1 _SFR_MEM8(0x7F) +-/* DIDR1 */ +-#define ACMP0D 5 +-#define AMP0PD 4 +-#define AMP0ND 3 +-#define ADC10D 2 /* ADC10 Digital input Disable */ +-#define ADC9D 1 /* ADC9 Digital input Disable */ +-#define ADC8D 0 /* ADC8 Digital input Disable */ +- +-/* Timer/Counter1 Control Register A */ +-#define TCCR1A _SFR_MEM8(0x80) +-/* TCCR1A */ +-#define COM1A1 7 /* Comparet Ouput Mode 1A, bit 1 */ +-#define COM1A0 6 /* Comparet Ouput Mode 1A, bit 0 */ +-#define COM1B1 5 /* Compare Output Mode 1B, bit 1 */ +-#define COM1B0 4 /* Compare Output Mode 1B, bit 0 */ +-#define WGM11 1 /* Waveform Generation Mode */ +-#define WGM10 0 /* Waveform Generation Mode */ +- +-/* Timer/Counter1 Control Register B */ +-#define TCCR1B _SFR_MEM8(0x81) +-/* TCCR1B */ +-#define ICNC1 7 /* Input Capture 1 Noise Canceler */ +-#define ICES1 6 /* Input Capture 1 Edge Select */ +-#define WGM13 4 /* Waveform Generation Mode */ +-#define WGM12 3 /* Waveform Generation Mode */ +-#define CS12 2 /* Prescaler source of Timer/Counter 1 */ +-#define CS11 1 /* Prescaler source of Timer/Counter 1 */ +-#define CS10 0 /* Prescaler source of Timer/Counter 1 */ +- +-/* Timer/Counter1 Control Register C */ +-#define TCCR1C _SFR_MEM8(0x82) +-/* TCCR1C */ +-#define FOC1A 7 /* Force Output Compare for Channel A */ +-#define FOC1B 6 /* Force Output Compare for Channel B */ +- +-/* Timer/Counter1 */ +-#define TCNT1 _SFR_MEM16(0x84) +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1H _SFR_MEM8(0x85) +-/* TCNT1H */ +-#define TCNT115 7 +-#define TCNT114 6 +-#define TCNT113 5 +-#define TCNT112 4 +-#define TCNT111 3 +-#define TCNT110 2 +-#define TCNT19 1 +-#define TCNT18 0 +-/* TCNT1L */ +-#define TCNT17 7 +-#define TCNT16 6 +-#define TCNT15 5 +-#define TCNT14 4 +-#define TCNT13 3 +-#define TCNT12 2 +-#define TCNT11 1 +-#define TCNT10 0 +- +-/* Input Capture Register 1 */ +-#define ICR1 _SFR_MEM16(0x86) +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1H _SFR_MEM8(0x87) +-/* ICR1H */ +-#define ICR115 7 +-#define ICR114 6 +-#define ICR113 5 +-#define ICR112 4 +-#define ICR111 3 +-#define ICR110 2 +-#define ICR19 1 +-#define ICR18 0 +-/* ICR1L */ +-#define ICR17 7 +-#define ICR16 6 +-#define ICR15 5 +-#define ICR14 4 +-#define ICR13 3 +-#define ICR12 2 +-#define ICR11 1 +-#define ICR10 0 +- +-/* Output Compare Register 1 A */ +-#define OCR1A _SFR_MEM16(0x88) +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AH _SFR_MEM8(0x89) +-/* OCR1AH */ +-#define OCR1A15 7 +-#define OCR1A14 6 +-#define OCR1A13 5 +-#define OCR1A12 4 +-#define OCR1A11 3 +-#define OCR1A10 2 +-#define OCR1A9 1 +-#define OCR1A8 0 +-/* OCR1AL */ +-#define OCR1A7 7 +-#define OCR1A6 6 +-#define OCR1A5 5 +-#define OCR1A4 4 +-#define OCR1A3 3 +-#define OCR1A2 2 +-#define OCR1A1 1 +-#define OCR1A0 0 +- +-/* Output Compare Register 1 B */ +-#define OCR1B _SFR_MEM16(0x8A) +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BH _SFR_MEM8(0x8B) +-/* OCR1BH */ +-#define OCR1B15 7 +-#define OCR1B14 6 +-#define OCR1B13 5 +-#define OCR1B12 4 +-#define OCR1B11 3 +-#define OCR1B10 2 +-#define OCR1B9 1 +-#define OCR1B8 0 +-/* OCR1BL */ +-#define OCR1B7 7 +-#define OCR1B6 6 +-#define OCR1B5 5 +-#define OCR1B4 4 +-#define OCR1B3 3 +-#define OCR1B2 2 +-#define OCR1B1 1 +-#define OCR1B0 0 +- +-/* PSC0 Interrupt Flag Register */ +-#define PIFR0 _SFR_MEM8(0xA0) +-/* PIFR0 */ +-#define POAC0B 7 /* PSC0 Output B Activity */ +-#define POAC0A 6 /* PSC0 Output A Activity */ +-#define PSEI0 5 /* PSC0 Synchro Error Interrupt */ +-#define PEV0B 4 /* PSC0 External Event B Interrupt */ +-#define PEV0A 3 /* PSC0 External Event A Interrupt */ +-#define PRN01 2 /* PSC0 Ramp Number bit1 */ +-#define PRN00 1 /* PSC0 Ramp Number bit0 */ +-#define PEOP0 0 /* End Of PSC0 Interrupt */ +- +-/* PSC0 Interrupt Mask Register */ +-#define PIM0 _SFR_MEM8(0xA1) +-/* PIM0 */ +-#define PSEIE0 5 /* PSC0 Synchro Error Interrupt Enable */ +-#define PEVE0B 4 /* PSC0 External Event B Interrupt Enable */ +-#define PEVE0A 3 /* PSC0 External Event A Interrupt Enable */ +-#define PEOPE0 0 /* PSC0 End Of Cycle Interrupt Enable */ +- +-/* PSC1 Interrupt Flag Register */ +-#define PIFR1 _SFR_MEM8(0xA2) +-/* PIFR1 */ +-#define POAC1B 7 /* PSC1 Output B Activity */ +-#define POAC1A 6 /* PSC1 Output A Activity */ +-#define PSEI1 5 /* PSC1 Synchro Error Interrupt */ +-#define PEV1B 4 /* PSC1 External Event B Interrupt */ +-#define PEV1A 3 /* PSC1 External Event A Interrupt */ +-#define PRN11 2 /* PSC1 Ramp Number bit1 */ +-#define PRN10 1 /* PSC1 Ramp Number bit0 */ +-#define PEOP1 0 /* End Of PSC1 Interrupt */ +- +-/* PSC1 Interrupt Mask Register */ +-#define PIM1 _SFR_MEM8(0xA3) +-/* PIM1 */ +-#define PSEIE1 5 /* PSC1 Synchro Error Interrupt Enable */ +-#define PEVE1B 4 /* PSC1 External Event B Interrupt Enable */ +-#define PEVE1A 3 /* PSC1 External Event A Interrupt Enable */ +-#define PEOPE1 0 /* PSC1 End Of Cycle Interrupt Enable */ +- +-/* PSC2 Interrupt Flag Register */ +-#define PIFR2 _SFR_MEM8(0xA4) +-/* PIFR2 */ +-#define POAC2B 7 /* PSC2 Output B Activity */ +-#define POAC2A 6 /* PSC2 Output A Activity */ +-#define PSEI2 5 /* PSC2 Synchro Error Interrupt */ +-#define PEV2B 4 /* PSC2 External Event B Interrupt */ +-#define PEV2A 3 /* PSC2 External Event A Interrupt */ +-#define PRN21 2 /* PSC2 Ramp Number bit1 */ +-#define PRN20 1 /* PSC2 Ramp Number bit0 */ +-#define PEOP2 0 /* End Of PSC2 Interrupt */ +- +-/* PSC2 Interrupt Mask Register */ +-#define PIM2 _SFR_MEM8(0xA5) +-/* PIM2 */ +-#define PSEIE2 5 /* PSC2 Synchro Error Interrupt Enable */ +-#define PEVE2B 4 /* PSC2 External Event B Interrupt Enable */ +-#define PEVE2A 3 /* PSC2 External Event A Interrupt Enable */ +-#define PEOPE2 0 /* PSC2 End Of Cycle Interrupt Enable */ +- +-/* Digital to Analog Conversion Control Register */ +-#define DACON _SFR_MEM8(0xAA) +-/* DACON */ +-#define DAATE 7 /* DAC Auto Trigger Enable bit */ +-#define DATS2 6 /* DAC Trigger Selection bit2 */ +-#define DATS1 5 /* DAC Trigger Selection bit1 */ +-#define DATS0 4 /* DAC Trigger Selection bit0 */ +-#define DALA 2 /* Digital to Analog Left Adjust */ +-#define DAOE 1 /* Digital to Analog Output Enable bit */ +-#define DAEN 0 /* Digital to Analog Enable bit */ +- +-/* Digital to Analog Converter input Register */ +-#define DAC _SFR_MEM16(0xAB) +-#define DACL _SFR_MEM8(0xAB) +-#define DACH _SFR_MEM8(0xAC) +- +-/* Analog Comparator 0 Control Register */ +-#define AC0CON _SFR_MEM8(0xAD) +-/* AC0CON */ +-#define AC0EN 7 /* Analog Comparator 0 Enable Bit */ +-#define AC0IE 6 /* Analog Comparator 0 Interrupt Enable bit */ +-#define AC0IS1 5 /* Analog Comparator 0 Interrupt Select bit1 */ +-#define AC0IS0 4 /* Analog Comparator 0 Interrupt Select bit0 */ +-#define AC0M2 2 /* Analog Comparator 0 Multiplexer register bit2 */ +-#define AC0M1 1 /* Analog Comparator 0 Multiplexer register bit1 */ +-#define AC0M0 0 /* Analog Comparator 0 Multiplexer register bit0 */ +- +-/* Analog Comparator 1 Control Register */ +-#define AC1CON _SFR_MEM8(0xAE) +-/* AC1CON */ +-#define AC1EN 7 /* Analog Comparator 1 Enable Bit */ +-#define AC1IE 6 /* Analog Comparator 1 Interrupt Enable bit */ +-#define AC1IS1 5 /* Analog Comparator 1 Interrupt Select bit1 */ +-#define AC1IS0 4 /* Analog Comparator 1 Interrupt Select bit0 */ +-#define AC1ICE 3 /* Analog Comparator 1 Interrupt Capture Enable bit */ +-#define AC1M2 2 /* Analog Comparator 1 Multiplexer register bit2 */ +-#define AC1M1 1 /* Analog Comparator 1 Multiplexer register bit1 */ +-#define AC1M0 0 /* Analog Comparator 1 Multiplexer register bit0 */ +- +-/* Analog Comparator 2 Control Register */ +-#define AC2CON _SFR_MEM8(0xAF) +-/* AC2CON */ +-#define AC2EN 7 /* Analog Comparator 2 Enable Bit */ +-#define AC2IE 6 /* Analog Comparator 2 Interrupt Enable bit */ +-#define AC2IS1 5 /* Analog Comparator 2 Interrupt Select bit1 */ +-#define AC2IS0 4 /* Analog Comparator 2 Interrupt Select bit0 */ +-#define AC2M2 2 /* Analog Comparator 2 Multiplexer register bit2 */ +-#define AC2M1 1 /* Analog Comparator 2 Multiplexer register bit1 */ +-#define AC2M0 0 /* Analog Comparator 2 Multiplexer register bit0 */ +- +-/* USART Control and Status Register A */ +-#define UCSRA _SFR_MEM8(0xC0) +-/* UCSRA */ +-#define RXC 7 /* USART Receive Complete */ +-#define TXC 6 /* USART Transmit Complete */ +-#define UDRE 5 /* USART Data Register Empty */ +-#define FE 4 /* Frame Error */ +-#define DOR 3 /* Data OverRun */ +-#define UPE 2 /* USART Parity Error */ +-#define U2X 1 /* Double the USART Transmission Speed */ +-#define MPCM 0 /* Multi-processor Communication Mode */ +- +-/* USART Control and Status Register B */ +-#define UCSRB _SFR_MEM8(0xC1) +-/* UCSRB */ +-#define RXCIE 7 /* RX Complete Interrupt Enable */ +-#define TXCIE 6 /* TX Complete Interrupt Enable */ +-#define UDRIE 5 /* USART Data Register Empty Interrupt Enable */ +-#define RXEN 4 /* Receiver Enable */ +-#define TXEN 3 /* Transmitter Enable */ +-#define UCSZ2 2 /* Character Size */ +-#define RXB8 1 /* Receive Data Bit 8 */ +-#define TXB8 0 /* Transmit Data Bit 8 */ +- +-/* USART Control and Status Register C */ +-#define UCSRC _SFR_MEM8(0xC2) +-/* UCSRC */ +-#define UMSEL 6 /* USART Mode Select */ +-#define UPM1 5 /* Parity Mode bit1 */ +-#define UPM0 4 /* Parity Mode bit0 */ +-#define USBS 3 /* Stop Bit Select */ +-#define UCSZ1 2 /* Character Size bit1 */ +-#define UCSZ0 1 /* Character Size bit0 */ +-#define UCPOL 0 /* Clock Polarity */ +- +-/* USART Baud Rate Register */ +-#define UBRR _SFR_MEM16(0xC4) +-#define UBRRL _SFR_MEM8(0xC4) +-#define UBRRH _SFR_MEM8(0xC5) +- +-/* USART I/O Data Register */ +-#define UDR _SFR_MEM8(0xC6) +- +-/* EUSART Control and Status Register A */ +-#define EUCSRA _SFR_MEM8(0xC8) +-/* EUCSRA */ +-#define UTxS3 7 /* EUSART Transmit Character Size bit3 */ +-#define UTxS2 6 /* EUSART Transmit Character Size bit2 */ +-#define UTxS1 5 /* EUSART Transmit Character Size bit1 */ +-#define UTxS0 4 /* EUSART Transmit Character Size bit0 */ +-#define URxS3 3 /* EUSART Receive Character Size bit3 */ +-#define URxS2 2 /* EUSART Receive Character Size bit2 */ +-#define URxS1 1 /* EUSART Receive Character Size bit1 */ +-#define URxS0 0 /* EUSART Receive Character Size bit0 */ +- +-/* EUSART Control and Status Register B */ +-#define EUCSRB _SFR_MEM8(0xC9) +-/* EUCSRB */ +-#define EUSART 4 /* EUSART Enable Bit */ +-#define EUSBS 3 /* EUSBS Enable Bit */ +-#define EMCH 1 /* Manchester mode */ +-#define BODR 0 /* Bit Order */ +- +-/* EUSART Control and Status Register C */ +-#define EUCSRC _SFR_MEM8(0xCA) +-/* EUCSRC */ +-#define FEM 3 /* Frame Error Manchester */ +-#define F1617 2 +-#define STP1 1 /* Stop bits values bit1 */ +-#define STP0 0 /* Stop bits values bit0 */ +- +-/* Manchester receiver Baud Rate Registers */ +-#define MUBRR _SFR_MEM16(0xCC) +-#define MUBRRL _SFR_MEM8(0xCC) +-#define MUBRRH _SFR_MEM8(0xCD) +- +-/* EUSART I/O Data Register */ +-#define EUDR _SFR_MEM8(0xCE) +- +-/* PSC 0 Synchro and Output Configuration */ +-#define PSOC0 _SFR_MEM8(0xD0) +-/* PSOC0 */ +-#define PSYNC01 5 /* Synchronization Out for ADC Selection bit1 */ +-#define PSYNC00 4 /* Synchronization Out for ADC Selection bit0 */ +-#define POEN0B 2 /* PSC 0 OUT Part B Output Enable */ +-#define POEN0A 0 /* PSC 0 OUT Part A Output Enable */ +- +-/* Output Compare SA Registers */ +-#define OCR0SA _SFR_MEM16(0xD2) +-#define OCR0SAL _SFR_MEM8(0xD2) +-#define OCR0SAH _SFR_MEM8(0xD3) +- +-/* Output Compare RA Registers */ +-#define OCR0RA _SFR_MEM16(0xD4) +-#define OCR0RAL _SFR_MEM8(0xD4) +-#define OCR0RAH _SFR_MEM8(0xD5) +- +-/* Output Compare SB Registers */ +-#define OCR0SB _SFR_MEM16(0xD6) +-#define OCR0SBL _SFR_MEM8(0xD6) +-#define OCR0SBH _SFR_MEM8(0xD7) +- +-/* Output Compare RB Registers */ +-#define OCR0RB _SFR_MEM16(0xD8) +-#define OCR0RBL _SFR_MEM8(0xD8) +-#define OCR0RBH _SFR_MEM8(0xD9) +- +-/* PSC 0 Configuration Register */ +-#define PCNF0 _SFR_MEM8(0xDA) +-/* PCNF0 */ +-#define PFIFTY0 7 /* PSC 0 Fifty */ +-#define PALOCK0 6 /* PSC 0 Autolock */ +-#define PLOCK0 5 /* PSC 0 Lock */ +-#define PMODE01 4 /* PSC 0 Mode bit1 */ +-#define PMODE00 3 /* PSC 0 Mode bit0 */ +-#define POP0 2 /* PSC 0 Output Polarity */ +-#define PCLKSEL0 1 /* PSC 0 Input Clock Select */ +- +-/* PSC 0 Control Register */ +-#define PCTL0 _SFR_MEM8(0xDB) +-/* PCTL0 */ +-#define PPRE01 7 /* PSC 0 Prescaler Select bit1 */ +-#define PPRE00 6 /* PSC 0 Prescaler Select bit0 */ +-#define PBFM0 5 /* Balance Flank Width Modulation */ +-#define PAOC0B 4 /* PSC 0 Asynchronous Output Control B */ +-#define PAOC0A 3 /* PSC 0 Asynchronous Output Control A */ +-#define PARUN0 2 /* PSC 0 Autorun */ +-#define PCCYC0 1 /* PSC 0 Complete Cycle */ +-#define PRUN0 0 /* PSC 0 Run */ +- +-/* PSC 0 Input A Control Register */ +-#define PFRC0A _SFR_MEM8(0xDC) +-/* PFRC0A */ +-#define PCAE0A 7 /* PSC 0 Capture Enable Input Part A */ +-#define PISEL0A 6 /* PSC 0 Input Select for Part A */ +-#define PELEV0A 5 /* PSC 0 Edge Level Selector of Input Part A */ +-#define PFLTE0A 4 /* PSC 0 Filter Enable on Input Part A */ +-#define PRFM0A3 3 /* PSC 0 Fault Mode bit3 */ +-#define PRFM0A2 2 /* PSC 0 Fault Mode bit2 */ +-#define PRFM0A1 1 /* PSC 0 Fault Mode bit1 */ +-#define PRFM0A0 0 /* PSC 0 Fault Mode bit0 */ +- +-/* PSC 0 Input B Control Register */ +-#define PFRC0B _SFR_MEM8(0xDD) +-/* PFRC0B */ +-#define PCAE0B 7 /* PSC 0 Capture Enable Input Part B */ +-#define PISEL0B 6 /* PSC 0 Input Select for Part B */ +-#define PELEV0B 5 /* PSC 0 Edge Level Selector of Input Part B */ +-#define PFLTE0B 4 /* PSC 0 Filter Enable on Input Part B */ +-#define PRFM0B3 3 /* PSC 0 Fault Mode bit3 */ +-#define PRFM0B2 2 /* PSC 0 Fault Mode bit2 */ +-#define PRFM0B1 1 /* PSC 0 Fault Mode bit1 */ +-#define PRFM0B0 0 /* PSC 0 Fault Mode bit0 */ +- +-/* PSC 0 Input Capture Registers */ +-#define PICR0 _SFR_MEM16(0xDE) +- +-#define PICR0L _SFR_MEM8(0xDE) +- +-#define PICR0H _SFR_MEM8(0xDF) +-#define PCST0 7 /* PSC Capture Software Trig bit */ +- /* not implemented on AT90PWM2/AT90PWM3 */ +- +-/* PSC 1 Synchro and Output Configuration */ +-#define PSOC1 _SFR_MEM8(0xE0) +-/* PSOC1 */ +-#define PSYNC11 5 /* Synchronization Out for ADC Selection bit1 */ +-#define PSYNC10 4 /* Synchronization Out for ADC Selection bit0 */ +-#define POEN1B 2 /* PSC 1 OUT Part B Output Enable */ +-#define POEN1A 0 /* PSC 1 OUT Part A Output Enable */ +- +-/* Output Compare SA Registers */ +-#define OCR1SA _SFR_MEM16(0xE2) +-#define OCR1SAL _SFR_MEM8(0xE2) +-#define OCR1SAH _SFR_MEM8(0xE3) +- +-/* Output Compare RA Registers */ +-#define OCR1RA _SFR_MEM16(0xE4) +-#define OCR1RAL _SFR_MEM8(0xE4) +-#define OCR1RAH _SFR_MEM8(0xE5) +- +-/* Output Compare SB Registers */ +-#define OCR1SB _SFR_MEM16(0xE6) +-#define OCR1SBL _SFR_MEM8(0xE6) +-#define OCR1SBH _SFR_MEM8(0xE7) +- +-/* Output Compare RB Registers */ +-#define OCR1RB _SFR_MEM16(0xE8) +-#define OCR1RBL _SFR_MEM8(0xE8) +-#define OCR1RBH _SFR_MEM8(0xE9) +- +-/* PSC 1 Configuration Register */ +-#define PCNF1 _SFR_MEM8(0xEA) +-/* PCNF1 */ +-#define PFIFTY1 7 /* PSC 1 Fifty */ +-#define PALOCK1 6 /* PSC 1 Autolock */ +-#define PLOCK1 5 /* PSC 1 Lock */ +-#define PMODE11 4 /* PSC 1 Mode bit1 */ +-#define PMODE10 3 /* PSC 1 Mode bit0 */ +-#define POP1 2 /* PSC 1 Output Polarity */ +-#define PCLKSEL1 1 /* PSC 1 Input Clock Select */ +- +-/* PSC 1 Control Register */ +-#define PCTL1 _SFR_MEM8(0xEB) +-/* PCTL1 */ +-#define PPRE11 7 /* PSC 1 Prescaler Select bit1 */ +-#define PPRE10 6 /* PSC 1 Prescaler Select bit0 */ +-#define PBFM1 5 /* Balance Flank Width Modulation */ +-#define PAOC1B 4 /* PSC 1 Asynchronous Output Control B */ +-#define PAOC1A 3 /* PSC 1 Asynchronous Output Control A */ +-#define PARUN1 2 /* PSC 1 Autorun */ +-#define PCCYC1 1 /* PSC 1 Complete Cycle */ +-#define PRUN1 0 /* PSC 1 Run */ +- +-/* PSC 1 Input A Control Register */ +-#define PFRC1A _SFR_MEM8(0xEC) +-/* PFRC1A */ +-#define PCAE1A 7 /* PSC 1 Capture Enable Input Part A */ +-#define PISEL1A 6 /* PSC 1 Input Select for Part A */ +-#define PELEV1A 5 /* PSC 1 Edge Level Selector of Input Part A */ +-#define PFLTE1A 4 /* PSC 1 Filter Enable on Input Part A */ +-#define PRFM1A3 3 /* PSC 1 Fault Mode bit3 */ +-#define PRFM1A2 2 /* PSC 1 Fault Mode bit2 */ +-#define PRFM1A1 1 /* PSC 1 Fault Mode bit1 */ +-#define PRFM1A0 0 /* PSC 1 Fault Mode bit0 */ +- +-/* PSC 1 Input B Control Register */ +-#define PFRC1B _SFR_MEM8(0xED) +-/* PFRC1B */ +-#define PCAE1B 7 /* PSC 1 Capture Enable Input Part B */ +-#define PISEL1B 6 /* PSC 1 Input Select for Part B */ +-#define PELEV1B 5 /* PSC 1 Edge Level Selector of Input Part B */ +-#define PFLTE1B 4 /* PSC 1 Filter Enable on Input Part B */ +-#define PRFM1B3 3 /* PSC 1 Fault Mode bit3 */ +-#define PRFM1B2 2 /* PSC 1 Fault Mode bit2 */ +-#define PRFM1B1 1 /* PSC 1 Fault Mode bit1 */ +-#define PRFM1B0 0 /* PSC 1 Fault Mode bit0 */ +- +-/* PSC 1 Input Capture Registers */ +-#define PICR1 _SFR_MEM16(0xEE) +- +-#define PICR1L _SFR_MEM8(0xEE) +- +-#define PICR1H _SFR_MEM8(0xEF) +-#define PCST1 7 /* PSC Capture Software Trig bit */ +- /* not implemented on AT90PWM2/AT90PWM3 */ +- +-/* PSC 2 Synchro and Output Configuration */ +-#define PSOC2 _SFR_MEM8(0xF0) +-/* PSOC2 */ +-#define POS23 7 /* PSCOUT23 Selection */ +-#define POS22 6 /* PSCOUT22 Selection */ +-#define PSYNC21 5 /* Synchronization Out for ADC Selection bit1 */ +-#define PSYNC20 4 /* Synchronization Out for ADC Selection bit0 */ +-#define POEN2D 3 /* PSCOUT23 Output Enable */ +-#define POEN2B 2 /* PSC 2 OUT Part B Output Enable */ +-#define POEN2C 1 /* PSCOUT22 Output Enable */ +-#define POEN2A 0 /* PSC 2 OUT Part A Output Enable */ +- +-/* PSC 2 Output Matrix */ +-#define POM2 _SFR_MEM8(0xF1) +-/* POM2 */ +-#define POMV2B3 7 /* Output Matrix Output B Ramp 3 */ +-#define POMV2B2 6 /* Output Matrix Output B Ramp 2 */ +-#define POMV2B1 5 /* Output Matrix Output B Ramp 1 */ +-#define POMV2B0 4 /* Output Matrix Output B Ramp 0 */ +-#define POMV2A3 3 /* Output Matrix Output A Ramp 3 */ +-#define POMV2A2 2 /* Output Matrix Output A Ramp 2 */ +-#define POMV2A1 1 /* Output Matrix Output A Ramp 1 */ +-#define POMV2A0 0 /* Output Matrix Output A Ramp 0 */ +- +-/* Output Compare SA Registers */ +-#define OCR2SA _SFR_MEM16(0xF2) +-#define OCR2SAL _SFR_MEM8(0xF2) +-#define OCR2SAH _SFR_MEM8(0xF3) +- +-/* Output Compare RA Registers */ +-#define OCR2RA _SFR_MEM16(0xF4) +-#define OCR2RAL _SFR_MEM8(0xF4) +-#define OCR2RAH _SFR_MEM8(0xF5) +- +-/* Output Compare SB Registers */ +-#define OCR2SB _SFR_MEM16(0xF6) +-#define OCR2SBL _SFR_MEM8(0xF6) +-#define OCR2SBH _SFR_MEM8(0xF7) +- +-/* Output Compare RB Registers */ +-#define OCR2RB _SFR_MEM16(0xF8) +-#define OCR2RBL _SFR_MEM8(0xF8) +-#define OCR2RBH _SFR_MEM8(0xF9) +- +-/* PSC 2 Configuration Register */ +-#define PCNF2 _SFR_MEM8(0xFA) +-/* PCNF2 */ +-#define PFIFTY2 7 /* PSC 2 Fifty */ +-#define PALOCK2 6 /* PSC 2 Autolock */ +-#define PLOCK2 5 /* PSC 2 Lock */ +-#define PMODE21 4 /* PSC 2 Mode bit1 */ +-#define PMODE20 3 /* PSC 2 Mode bit0 */ +-#define POP2 2 /* PSC 2 Output Polarity */ +-#define PCLKSEL2 1 /* PSC 2 Input Clock Select */ +-#define POME2 0 /* PSC 2 Output Matrix Enable */ +- +-/* PSC 2 Control Register */ +-#define PCTL2 _SFR_MEM8(0xFB) +-/* PCTL2 */ +-#define PPRE21 7 /* PSC 2 Prescaler Select bit1 */ +-#define PPRE20 6 /* PSC 2 Prescaler Select bit0 */ +-#define PBFM2 5 /* Balance Flank Width Modulation */ +-#define PAOC2B 4 /* PSC 2 Asynchronous Output Control B */ +-#define PAOC2A 3 /* PSC 2 Asynchronous Output Control A */ +-#define PARUN2 2 /* PSC 2 Autorun */ +-#define PCCYC2 1 /* PSC 2 Complete Cycle */ +-#define PRUN2 0 /* PSC 2 Run */ +- +-/* PSC 2 Input A Control Register */ +-#define PFRC2A _SFR_MEM8(0xFC) +-/* PFRC2A */ +-#define PCAE2A 7 /* PSC 2 Capture Enable Input Part A */ +-#define PISEL2A 6 /* PSC 2 Input Select for Part A */ +-#define PELEV2A 5 /* PSC 2 Edge Level Selector of Input Part A */ +-#define PFLTE2A 4 /* PSC 2 Filter Enable on Input Part A */ +-#define PRFM2A3 3 /* PSC 2 Fault Mode bit3 */ +-#define PRFM2A2 2 /* PSC 2 Fault Mode bit2 */ +-#define PRFM2A1 1 /* PSC 2 Fault Mode bit1 */ +-#define PRFM2A0 0 /* PSC 2 Fault Mode bit0 */ +- +-/* PSC 2 Input B Control Register */ +-#define PFRC2B _SFR_MEM8(0xFD) +-/* PFRC2B */ +-#define PCAE2B 7 /* PSC 2 Capture Enable Input Part B */ +-#define PISEL2B 6 /* PSC 2 Input Select for Part B */ +-#define PELEV2B 5 /* PSC 2 Edge Level Selector of Input Part B */ +-#define PFLTE2B 4 /* PSC 2 Filter Enable on Input Part B */ +-#define PRFM2B3 3 /* PSC 2 Fault Mode bit3 */ +-#define PRFM2B2 2 /* PSC 2 Fault Mode bit2 */ +-#define PRFM2B1 1 /* PSC 2 Fault Mode bit1 */ +-#define PRFM2B0 0 /* PSC 2 Fault Mode bit0 */ +- +-/* PSC 2 Input Capture Registers */ +-#define PICR2 _SFR_MEM16(0xFE) +- +-#define PICR2L _SFR_MEM8(0xFE) +- +-#define PICR2H _SFR_MEM8(0xFF) +-#define PCST2 7 /* PSC Capture Software Trig bit */ +- /* not implemented on AT90PWM2/AT90PWM3 */ +- +- +-/* Interrupt vectors */ +-/* PSC2 Capture Event */ +-#define PSC2_CAPT_vect_num 1 +-#define PSC2_CAPT_vect _VECTOR(1) +-#define SIG_PSC2_CAPTURE _VECTOR(1) +- +-/* PSC2 End Cycle */ +-#define PSC2_EC_vect_num 2 +-#define PSC2_EC_vect _VECTOR(2) +-#define SIG_PSC2_END_CYCLE _VECTOR(2) +- +-/* PSC1 Capture Event */ +-#define PSC1_CAPT_vect_num 3 +-#define PSC1_CAPT_vect _VECTOR(3) +-#define SIG_PSC1_CAPTURE _VECTOR(3) +- +-/* PSC1 End Cycle */ +-#define PSC1_EC_vect_num 4 +-#define PSC1_EC_vect _VECTOR(4) +-#define SIG_PSC1_END_CYCLE _VECTOR(4) +- +-/* PSC0 Capture Event */ +-#define PSC0_CAPT_vect_num 5 +-#define PSC0_CAPT_vect _VECTOR(5) +-#define SIG_PSC0_CAPTURE _VECTOR(5) +- +-/* PSC0 End Cycle */ +-#define PSC0_EC_vect_num 6 +-#define PSC0_EC_vect _VECTOR(6) +-#define SIG_PSC0_END_CYCLE _VECTOR(6) +- +-/* Analog Comparator 0 */ +-#define ANALOG_COMP_0_vect_num 7 +-#define ANALOG_COMP_0_vect _VECTOR(7) +-#define SIG_COMPARATOR0 _VECTOR(7) +- +-/* Analog Comparator 1 */ +-#define ANALOG_COMP_1_vect_num 8 +-#define ANALOG_COMP_1_vect _VECTOR(8) +-#define SIG_COMPARATOR1 _VECTOR(8) +- +-/* Analog Comparator 2 */ +-#define ANALOG_COMP_2_vect_num 9 +-#define ANALOG_COMP_2_vect _VECTOR(9) +-#define SIG_COMPARATOR2 _VECTOR(9) +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 10 +-#define INT0_vect _VECTOR(10) +-#define SIG_INTERRUPT0 _VECTOR(10) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 11 +-#define TIMER1_CAPT_vect _VECTOR(11) +-#define SIG_INPUT_CAPTURE1 _VECTOR(11) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num _VECTOR(12) +-#define TIMER1_COMPA_vect _VECTOR(12) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(12) +-#define SIG_OUTPUT_COMPARE1_A _VECTOR(12) +- +-/* Timer/Counter Compare Match B */ +-#define TIMER1_COMPB_vect_num 13 +-#define TIMER1_COMPB_vect _VECTOR(13) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(13) +-#define SIG_OUTPUT_COMPARE1_B _VECTOR(13) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 15 +-#define TIMER1_OVF_vect _VECTOR(15) +-#define SIG_OVERFLOW1 _VECTOR(15) +- +-/* Timer/Counter0 Compare Match A */ +-#define TIMER0_COMP_A_vect_num 16 +-#define TIMER0_COMP_A_vect _VECTOR(16) +-#define SIG_OUTPUT_COMPARE0A _VECTOR(16) +-#define SIG_OUTPUT_COMPARE0_A _VECTOR(16) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 17 +-#define TIMER0_OVF_vect _VECTOR(17) +-#define SIG_OVERFLOW0 _VECTOR(17) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 18 +-#define ADC_vect _VECTOR(18) +-#define SIG_ADC _VECTOR(18) +- +-/* External Interrupt Request 1 */ +-#define INT1_vect_num 19 +-#define INT1_vect _VECTOR(19) +-#define SIG_INTERRUPT1 _VECTOR(19) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 20 +-#define SPI_STC_vect _VECTOR(20) +-#define SIG_SPI _VECTOR(20) +- +-/* USART, Rx Complete */ +-#define USART_RX_vect_num 21 +-#define USART_RX_vect _VECTOR(21) +-#define SIG_USART_RECV _VECTOR(21) +-#define SIG_UART_RECV _VECTOR(21) +- +-/* USART Data Register Empty */ +-#define USART_UDRE_vect_num 22 +-#define USART_UDRE_vect _VECTOR(22) +-#define SIG_USART_DATA _VECTOR(22) +-#define SIG_UART_DATA _VECTOR(22) +- +-/* USART, Tx Complete */ +-#define USART_TX_vect_num 23 +-#define USART_TX_vect _VECTOR(23) +-#define SIG_USART_TRANS _VECTOR(23) +-#define SIG_UART_TRANS _VECTOR(23) +- +-/* External Interrupt Request 2 */ +-#define INT2_vect_num 24 +-#define INT2_vect _VECTOR(24) +-#define SIG_INTERRUPT2 _VECTOR(24) +- +-/* Watchdog Timeout Interrupt */ +-#define WDT_vect_num 25 +-#define WDT_vect _VECTOR(25) +-#define SIG_WDT _VECTOR(25) +-#define SIG_WATCHDOG_TIMEOUT _VECTOR(25) +- +-/* EEPROM Ready */ +-#define EE_READY_vect_num 26 +-#define EE_READY_vect _VECTOR(26) +-#define SIG_EEPROM_READY _VECTOR(26) +- +-/* Timer Counter 0 Compare Match B */ +-#define TIMER0_COMPB_vect_num 27 +-#define TIMER0_COMPB_vect _VECTOR(27) +-#define SIG_OUTPUT_COMPARE0B _VECTOR(27) +-#define SIG_OUTPUT_COMPARE0_B _VECTOR(27) +- +-/* External Interrupt Request 3 */ +-#define INT3_vect_num 28 +-#define INT3_vect _VECTOR(28) +-#define SIG_INTERRUPT3 _VECTOR(28) +- +-/* Store Program Memory Read */ +-#define SPM_READY_vect_num 31 +-#define SPM_READY_vect _VECTOR(31) +-#define SIG_SPM_READY _VECTOR(31) +- +-#define _VECTORS_SIZE 64 +- +-/* Constants */ +-#define SPM_PAGESIZE 64 +- +-#define RAMEND 0x02FF +-#define XRAMEND RAMEND +-#define E2END 0x01FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x0FFF +- +- +-/* Fuse Information */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Diasble */ +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_PSCRV (unsigned char)~_BV(4) +-#define FUSE_PSC0RB (unsigned char)~_BV(5) +-#define FUSE_PSC1RB (unsigned char)~_BV(6) +-#define FUSE_PSC2RB (unsigned char)~_BV(7) +-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-#endif /* _AVR_IO90PWMX_H_ */ ++/* Copyright (c) 2005, Andrey Pashchenko ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: io90pwmx.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* avr/io90pwmx.h - definitions for AT90PWM2(B) and AT90PWM3(B) */ ++ ++#ifndef _AVR_IO90PWMX_H_ ++#define _AVR_IO90PWMX_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "io90pwmX.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* Port B Input Pins Address */ ++#define PINB _SFR_IO8(0x03) ++/* PINB */ ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* Port B Data Direction Register */ ++#define DDRB _SFR_IO8(0x04) ++/* DDRB */ ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* Port B Data Register */ ++#define PORTB _SFR_IO8(0x05) ++/* PORTB */ ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* Port C Input Pins Address */ ++#define PINC _SFR_IO8(0x06) ++/* PINC */ ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++/* Port C Data Direction Register */ ++#define DDRC _SFR_IO8(0x07) ++/* DDRC */ ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++/* Port C Data Register */ ++#define PORTC _SFR_IO8(0x08) ++/* PORTC */ ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++/* Port D Input Pins Address */ ++#define PIND _SFR_IO8(0x09) ++/* PIND */ ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++/* Port D Data Direction Register */ ++#define DDRD _SFR_IO8(0x0A) ++/* DDRD */ ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++/* Port D Data Register */ ++#define PORTD _SFR_IO8(0x0B) ++/* PORTD */ ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* Port E Input Pins Address */ ++#define PINE _SFR_IO8(0x0C) ++/* PINE */ ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++/* Port E Data Direction Register */ ++#define DDRE _SFR_IO8(0x0D) ++/* DDRE */ ++#define DDE2 2 ++#define DDE1 1 ++#define DDE0 0 ++ ++/* Port E Data Register */ ++#define PORTE _SFR_IO8(0x0E) ++/* PORTE */ ++#define PE2 2 ++#define PE1 1 ++#define PE0 0 ++ ++/* Timer/Counter 0 Interrupt Flag Register */ ++#define TIFR0 _SFR_IO8(0x15) ++/* TIFR0 */ ++#define OCF0B 2 /* Output Compare Flag 0B */ ++#define OCF0A 1 /* Output Compare Flag 0A */ ++#define TOV0 0 /* Overflow Flag */ ++ ++/* Timer/Counter1 Interrupt Flag Register */ ++#define TIFR1 _SFR_IO8(0x16) ++/* TIFR1 */ ++#define ICF1 5 /* Input Capture Flag 1 */ ++#define OCF1B 2 /* Output Compare Flag 1B*/ ++#define OCF1A 1 /* Output Compare Flag 1A*/ ++#define TOV1 0 /* Overflow Flag */ ++ ++/* General Purpose I/O Register 1 */ ++#define GPIOR1 _SFR_IO8(0x19) ++/* GPIOR1 */ ++#define GPIOR17 7 ++#define GPIOR16 6 ++#define GPIOR15 5 ++#define GPIOR14 4 ++#define GPIOR13 3 ++#define GPIOR12 2 ++#define GPIOR11 1 ++#define GPIOR10 0 ++ ++/* General Purpose I/O Register 2 */ ++#define GPIOR2 _SFR_IO8(0x1A) ++/* GPIOR2 */ ++#define GPIOR27 7 ++#define GPIOR26 6 ++#define GPIOR25 5 ++#define GPIOR24 4 ++#define GPIOR23 3 ++#define GPIOR22 2 ++#define GPIOR21 1 ++#define GPIOR20 0 ++ ++/* General Purpose I/O Register 3 */ ++#define GPIOR3 _SFR_IO8(0x1B) ++/* GPIOR3 */ ++#define GPIOR37 7 ++#define GPIOR36 6 ++#define GPIOR35 5 ++#define GPIOR34 4 ++#define GPIOR33 3 ++#define GPIOR32 2 ++#define GPIOR31 1 ++#define GPIOR30 0 ++ ++/* External Interrupt Flag Register */ ++#define EIFR _SFR_IO8(0x1C) ++/* EIFR */ ++#define INTF3 3 ++#define INTF2 2 ++#define INTF1 1 ++#define INTF0 0 ++ ++/* External Interrupt Mask Register */ ++#define EIMSK _SFR_IO8(0x1D) ++/* EIMSK */ ++#define INT3 3 /* External Interrupt Request 3 Enable */ ++#define INT2 2 /* External Interrupt Request 2 Enable */ ++#define INT1 1 /* External Interrupt Request 1 Enable */ ++#define INT0 0 /* External Interrupt Request 0 Enable */ ++ ++/* General Purpose I/O Register 0 */ ++#define GPIOR0 _SFR_IO8(0x1E) ++/* GPIOR0 */ ++#define GPIOR07 7 ++#define GPIOR06 6 ++#define GPIOR05 5 ++#define GPIOR04 4 ++#define GPIOR03 3 ++#define GPIOR02 2 ++#define GPIOR01 1 ++#define GPIOR00 0 ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1F) ++/* EECR */ ++#define EERIE 3 /* EEPROM Ready Interrupt Enable */ ++#define EEMWE 2 /* EEPROM Master Write Enable */ ++#define EEWE 1 /* EEPROM Write Enable */ ++#define EERE 0 /* EEPROM Read Enable */ ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x20) ++/* EEDR */ ++#define EEDR7 7 ++#define EEDR6 6 ++#define EEDR5 5 ++#define EEDR4 4 ++#define EEDR3 3 ++#define EEDR2 2 ++#define EEDR1 1 ++#define EEDR0 0 ++ ++/* The EEPROM Address Registers */ ++#define EEAR _SFR_IO16(0x21) ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++/* EEARH */ ++#define EEAR11 3 ++#define EEAR10 2 ++#define EEAR9 1 ++#define EEAR8 0 ++/* EEARL */ ++#define EEAR7 7 ++#define EEAR6 6 ++#define EEAR5 5 ++#define EEAR4 4 ++#define EEAR3 3 ++#define EEAR2 2 ++#define EEAR1 1 ++#define EEAR0 0 ++ ++/* 6-char sequence denoting where to find the EEPROM registers in memory space. ++ Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM ++ subroutines. ++ First two letters: EECR address. ++ Second two letters: EEDR address. ++ Last two letters: EEAR address. */ ++#define __EEPROM_REG_LOCATIONS__ 1F2021 ++ ++/* General Timer/Counter Control Register */ ++#define GTCCR _SFR_IO8(0x23) ++/* GTCCR */ ++#define TSM 7 /* Timer/Counter Synchronization Mode */ ++#define ICPSEL1 6 /* Timer1 Input Capture Selection Bit */ ++#define PSR10 0 /* Prescaler Reset Timer/Counter1 and Timer/Counter0 */ ++ ++/* Timer/Counter Control Register A */ ++#define TCCR0A _SFR_IO8(0x24) ++/* TCCR0A */ ++#define COM0A1 7 /* Compare Output Mode, Phase Correct PWM Mode */ ++#define COM0A0 6 /* Compare Output Mode, Phase Correct PWM Mode */ ++#define COM0B1 5 /* Compare Output Mode, Fast PWm */ ++#define COM0B0 4 /* Compare Output Mode, Fast PWm */ ++#define WGM01 1 /* Waveform Generation Mode */ ++#define WGM00 0 /* Waveform Generation Mode */ ++ ++/* Timer/Counter Control Register B */ ++#define TCCR0B _SFR_IO8(0x25) ++/* TCCR0B */ ++#define FOC0A 7 /* Force Output Compare A */ ++#define FOC0B 6 /* Force Output Compare B */ ++#define WGM02 3 /* Waveform Generation Mode */ ++#define CS02 2 /* Clock Select */ ++#define CS01 1 /* Clock Select */ ++#define CS00 0 /* Clock Select */ ++ ++/* Timer/Counter0 Register */ ++#define TCNT0 _SFR_IO8(0x26) ++/* TCNT0 */ ++#define TCNT07 7 ++#define TCNT06 6 ++#define TCNT05 5 ++#define TCNT04 4 ++#define TCNT03 3 ++#define TCNT02 2 ++#define TCNT01 1 ++#define TCNT00 0 ++ ++/* Timer/Counter0 Output Compare Register A */ ++#define OCR0A _SFR_IO8(0x27) ++/* OCR0A */ ++#define OCR0A7 7 ++#define OCR0A6 6 ++#define OCR0A5 5 ++#define OCR0A4 4 ++#define OCR0A3 3 ++#define OCR0A2 2 ++#define OCR0A1 1 ++#define OCR0A0 0 ++ ++/* Timer/Counter0 Output Compare Register B */ ++#define OCR0B _SFR_IO8(0x28) ++/* OCR0B */ ++#define OCR0B7 7 ++#define OCR0B6 6 ++#define OCR0B5 5 ++#define OCR0B4 4 ++#define OCR0B3 3 ++#define OCR0B2 2 ++#define OCR0B1 1 ++#define OCR0B0 0 ++ ++/* PLL Control and Status Register */ ++#define PLLCSR _SFR_IO8(0x29) ++/* PLLCSR */ ++#define PCKE 2 /* PCK Enable */ ++/* Bit 2 has been renamed in later versions of the datasheet. */ ++#define PLLF 2 /* PLL Factor */ ++#define PLLE 1 /* PLL Enable */ ++#define PLOCK 0 /* PLL Lock Detector */ ++ ++/* SPI Control Register */ ++#define SPCR _SFR_IO8(0x2C) ++/* SPCR */ ++#define SPIE 7 /* SPI Interrupt Enable */ ++#define SPE 6 /* SPI Enable */ ++#define DORD 5 /* Data Order */ ++#define MSTR 4 /* Master/Slave Select */ ++#define CPOL 3 /* Clock polarity */ ++#define CPHA 2 /* Clock Phase */ ++#define SPR1 1 /* SPI Clock Rate Select 1 */ ++#define SPR0 0 /* SPI Clock Rate Select 0 */ ++ ++/* SPI Status Register */ ++#define SPSR _SFR_IO8(0x2D) ++/* SPSR */ ++#define SPIF 7 /* SPI Interrupt Flag */ ++#define WCOL 6 /* Write Collision Flag */ ++#define SPI2X 0 /* Double SPI Speed Bit */ ++ ++/* SPI Data Register */ ++#define SPDR _SFR_IO8(0x2E) ++/* SPDR */ ++#define SPD7 7 ++#define SPD6 6 ++#define SPD5 5 ++#define SPD4 4 ++#define SPD3 3 ++#define SPD2 2 ++#define SPD1 1 ++#define SPD0 0 ++ ++/* Analog Comparator Status Register */ ++#define ACSR _SFR_IO8(0x30) ++/* ACSR */ ++#define ACCKDIV 7 /* Analog Comparator Clock Divider */ ++#define AC2IF 6 /* Analog Comparator 2 Interrupt Flag Bit */ ++#define AC1IF 5 /* Analog Comparator 1 Interrupt Flag Bit */ ++#define AC0IF 4 /* Analog Comparator 0 Interrupt Flag Bit */ ++#define AC2O 2 /* Analog Comparator 2 Output Bit */ ++#define AC1O 1 /* Analog Comparator 1 Output Bit */ ++#define AC0O 0 /* Analog Comparator 0 Output Bit */ ++ ++/* Monitor Data Register */ ++#define MONDR _SFR_IO8(0x31) ++ ++/* Monitor Stop Mode Control Register */ ++#define MSMCR _SFR_IO8(0x32) ++ ++/* Sleep Mode Control Register */ ++#define SMCR _SFR_IO8(0x33) ++/* SMCR */ ++#define SM2 3 /* Sleep Mode Select bit2 */ ++#define SM1 2 /* Sleep Mode Select bit1 */ ++#define SM0 1 /* Sleep Mode Select bit0 */ ++#define SE 0 /* Sleep Enable */ ++ ++/* MCU Status Register */ ++#define MCUSR _SFR_IO8(0x34) ++/* MCUSR */ ++#define WDRF 3 /* Watchdog Reset Flag */ ++#define BORF 2 /* Brown-out Reset Flag */ ++#define EXTRF 1 /* External Reset Flag */ ++#define PORF 0 /* Power-on reset flag */ ++ ++/* MCU Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++/* MCUCR */ ++#define SPIPS 7 /* SPI Pin Select */ ++#define PUD 4 /* Pull-up disable */ ++#define IVSEL 1 /* Interrupt Vector Select */ ++#define IVCE 0 /* Interrupt Vector Change Enable */ ++ ++/* Store Program Memory Control Register */ ++#define SPMCSR _SFR_IO8(0x37) ++/* SPMCSR */ ++#define SPMIE 7 /* SPM Interrupt Enable */ ++#define RWWSB 6 /* Read While Write Section Busy */ ++#define RWWSRE 4 /* Read While Write section read enable */ ++#define BLBSET 3 /* Boot Lock Bit Set */ ++#define PGWRT 2 /* Page Write */ ++#define PGERS 1 /* Page Erase */ ++#define SPMEN 0 /* Store Program Memory Enable */ ++ ++/* 0x3D..0x3E SP [defined in ] */ ++/* 0x3F SREG [defined in ] */ ++ ++/* Watchdog Timer Control Register */ ++#define WDTCSR _SFR_MEM8(0x60) ++/* WDTCSR */ ++#define WDIF 7 /* Watchdog Timeout Interrupt Flag */ ++#define WDIE 6 /* Watchdog Timeout Interrupt Enable */ ++#define WDP3 5 /* Watchdog Timer Prescaler bit3 */ ++#define WDCE 4 /* Watchdog Change Enable */ ++#define WDE 3 /* Watchdog Enable */ ++#define WDP2 2 /* Watchdog Timer Prescaler bit2 */ ++#define WDP1 1 /* Watchdog Timer Prescaler bit1 */ ++#define WDP0 0 /* Watchdog Timer Prescaler bit0 */ ++ ++/* Clock Prescaler Register */ ++#define CLKPR _SFR_MEM8(0x61) ++/* CLKPR */ ++#define CLKPCE 7 /* Clock Prescaler Change Enable */ ++#define CLKPS3 3 /* Clock Prescaler Select bit3 */ ++#define CLKPS2 2 /* Clock Prescaler Select bit2 */ ++#define CLKPS1 1 /* Clock Prescaler Select bit1 */ ++#define CLKPS0 0 /* Clock Prescaler Select bit0 */ ++ ++/* Power Reduction Register */ ++#define PRR _SFR_MEM8(0x64) ++/* PRR */ ++#define PRPSC2 7 /* Power Reduction PSC2 */ ++#define PRPSC1 6 /* Power Reduction PSC1 */ ++#define PRPSC0 5 /* Power Reduction PSC0 */ ++#define PRTIM1 4 /* Power Reduction Timer/Counter1 */ ++#define PRTIM0 3 /* Power Reduction Timer/Counter0 */ ++#define PRSPI 2 /* Power Reduction Serial Peripheral Interface */ ++#define PRUSART0 1 /* Power Reduction USART */ ++#define PRADC 0 /* Power Reduction ADC */ ++ ++/* Oscillator Calibration Value */ ++#define OSCCAL _SFR_MEM8(0x66) ++/* OSCCAL */ ++#define CAL6 6 ++#define CAL5 5 ++#define CAL4 4 ++#define CAL3 3 ++#define CAL2 2 ++#define CAL1 1 ++#define CAL0 0 ++ ++/* External Interrupt Control Register A */ ++#define EICRA _SFR_MEM8(0x69) ++/* EICRA */ ++#define ISC31 7 ++#define ISC30 6 ++#define ISC21 5 ++#define ISC20 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* Timer/Counter0 Interrupt Mask Register */ ++#define TIMSK0 _SFR_MEM8(0x6E) ++/* TIMSK0 */ ++#define OCIE0B 2 /* Output Compare Match B Interrupt Enable */ ++#define OCIE0A 1 /* Output Compare Match A Interrupt Enable */ ++#define TOIE0 0 /* Overflow Interrupt Enable */ ++ ++/* Timer/Counter1 Interrupt Mask Register */ ++#define TIMSK1 _SFR_MEM8(0x6F) ++/* TIMSK1 */ ++#define ICIE1 5 /* Input Capture Interrupt Enable */ ++#define OCIE1B 2 /* Output Compare Match B Interrupt Enable */ ++#define OCIE1A 1 /* Output Compare Match A Interrupt Enable */ ++#define TOIE1 0 /* Overflow Interrupt Enable */ ++ ++/* Amplifier 0 Control and Status register */ ++#define AMP0CSR _SFR_MEM8(0x76) ++#define AMP0EN 7 ++#define AMP0IS 6 ++#define AMP0G1 5 ++#define AMP0G0 4 ++#define AMP0TS1 1 ++#define AMP0TS0 0 ++ ++/* Amplifier 1 Control and Status register */ ++#define AMP1CSR _SFR_MEM8(0x77) ++#define AMP1EN 7 ++#define AMP1IS 6 ++#define AMP1G1 5 ++#define AMP1G0 4 ++#define AMP1TS1 1 ++#define AMP1TS0 0 ++ ++/* ADC Result Data Register */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++/* ADC Control and Status Register A */ ++#define ADCSRA _SFR_MEM8(0x7A) ++/* ADCSRA */ ++#define ADEN 7 /* ADC Enable */ ++#define ADSC 6 /* ADC Start Conversion */ ++#define ADATE 5 /* ADC Auto Trigger Enable */ ++#define ADIF 4 /* ADC Interrupt Flag */ ++#define ADIE 3 /* ADC Interrupt Enable */ ++#define ADPS2 2 /* ADC Prescaler Select bit2 */ ++#define ADPS1 1 /* ADC Prescaler Select bit1 */ ++#define ADPS0 0 /* ADC Prescaler Select bit0 */ ++ ++/* ADC Control and Status Register B */ ++#define ADCSRB _SFR_MEM8(0x7B) ++/* ADCSRB */ ++#define ADHSM 7 /* ADC High Speed Mode */ ++#define ADASCR 4 ++#define ADTS3 3 /* ADC Auto Trigger Source 3 */ ++#define ADTS2 2 /* ADC Auto Trigger Source 2 */ ++#define ADTS1 1 /* ADC Auto Trigger Source 1 */ ++#define ADTS0 0 /* ADC Auto Trigger Source 0 */ ++ ++/* ADC multiplexer Selection Register */ ++#define ADMUX _SFR_MEM8(0x7C) ++/* ADMUX */ ++#define REFS1 7 /* Reference Selection bit1 */ ++#define REFS0 6 /* Reference Selection bit0 */ ++#define ADLAR 5 /* Left Adjust Result */ ++#define MUX3 3 /* Analog Channel and Gain Selection bit3 */ ++#define MUX2 2 /* Analog Channel and Gain Selection bit2 */ ++#define MUX1 1 /* Analog Channel and Gain Selection bit1 */ ++#define MUX0 0 /* Analog Channel and Gain Selection bit0 */ ++ ++/* Digital Input Disable Register 0 */ ++#define DIDR0 _SFR_MEM8(0x7E) ++/* DIDR0 */ ++#define ADC7D 7 /* ADC7 Digital input Disable */ ++#define ADC6D 6 /* ADC6 Digital input Disable */ ++#define ADC5D 5 /* ADC5 Digital input Disable */ ++#define ADC4D 4 /* ADC4 Digital input Disable */ ++#define ADC3D 3 /* ADC3 Digital input Disable */ ++#define ADC2D 2 /* ADC2 Digital input Disable */ ++#define ADC1D 1 /* ADC1 Digital input Disable */ ++#define ADC0D 0 /* ADC0 Digital input Disable */ ++ ++/* Digital Input Disable Register 1 */ ++#define DIDR1 _SFR_MEM8(0x7F) ++/* DIDR1 */ ++#define ACMP0D 5 ++#define AMP0PD 4 ++#define AMP0ND 3 ++#define ADC10D 2 /* ADC10 Digital input Disable */ ++#define ADC9D 1 /* ADC9 Digital input Disable */ ++#define ADC8D 0 /* ADC8 Digital input Disable */ ++ ++/* Timer/Counter1 Control Register A */ ++#define TCCR1A _SFR_MEM8(0x80) ++/* TCCR1A */ ++#define COM1A1 7 /* Comparet Ouput Mode 1A, bit 1 */ ++#define COM1A0 6 /* Comparet Ouput Mode 1A, bit 0 */ ++#define COM1B1 5 /* Compare Output Mode 1B, bit 1 */ ++#define COM1B0 4 /* Compare Output Mode 1B, bit 0 */ ++#define WGM11 1 /* Waveform Generation Mode */ ++#define WGM10 0 /* Waveform Generation Mode */ ++ ++/* Timer/Counter1 Control Register B */ ++#define TCCR1B _SFR_MEM8(0x81) ++/* TCCR1B */ ++#define ICNC1 7 /* Input Capture 1 Noise Canceler */ ++#define ICES1 6 /* Input Capture 1 Edge Select */ ++#define WGM13 4 /* Waveform Generation Mode */ ++#define WGM12 3 /* Waveform Generation Mode */ ++#define CS12 2 /* Prescaler source of Timer/Counter 1 */ ++#define CS11 1 /* Prescaler source of Timer/Counter 1 */ ++#define CS10 0 /* Prescaler source of Timer/Counter 1 */ ++ ++/* Timer/Counter1 Control Register C */ ++#define TCCR1C _SFR_MEM8(0x82) ++/* TCCR1C */ ++#define FOC1A 7 /* Force Output Compare for Channel A */ ++#define FOC1B 6 /* Force Output Compare for Channel B */ ++ ++/* Timer/Counter1 */ ++#define TCNT1 _SFR_MEM16(0x84) ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++/* TCNT1H */ ++#define TCNT115 7 ++#define TCNT114 6 ++#define TCNT113 5 ++#define TCNT112 4 ++#define TCNT111 3 ++#define TCNT110 2 ++#define TCNT19 1 ++#define TCNT18 0 ++/* TCNT1L */ ++#define TCNT17 7 ++#define TCNT16 6 ++#define TCNT15 5 ++#define TCNT14 4 ++#define TCNT13 3 ++#define TCNT12 2 ++#define TCNT11 1 ++#define TCNT10 0 ++ ++/* Input Capture Register 1 */ ++#define ICR1 _SFR_MEM16(0x86) ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++/* ICR1H */ ++#define ICR115 7 ++#define ICR114 6 ++#define ICR113 5 ++#define ICR112 4 ++#define ICR111 3 ++#define ICR110 2 ++#define ICR19 1 ++#define ICR18 0 ++/* ICR1L */ ++#define ICR17 7 ++#define ICR16 6 ++#define ICR15 5 ++#define ICR14 4 ++#define ICR13 3 ++#define ICR12 2 ++#define ICR11 1 ++#define ICR10 0 ++ ++/* Output Compare Register 1 A */ ++#define OCR1A _SFR_MEM16(0x88) ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++/* OCR1AH */ ++#define OCR1A15 7 ++#define OCR1A14 6 ++#define OCR1A13 5 ++#define OCR1A12 4 ++#define OCR1A11 3 ++#define OCR1A10 2 ++#define OCR1A9 1 ++#define OCR1A8 0 ++/* OCR1AL */ ++#define OCR1A7 7 ++#define OCR1A6 6 ++#define OCR1A5 5 ++#define OCR1A4 4 ++#define OCR1A3 3 ++#define OCR1A2 2 ++#define OCR1A1 1 ++#define OCR1A0 0 ++ ++/* Output Compare Register 1 B */ ++#define OCR1B _SFR_MEM16(0x8A) ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++/* OCR1BH */ ++#define OCR1B15 7 ++#define OCR1B14 6 ++#define OCR1B13 5 ++#define OCR1B12 4 ++#define OCR1B11 3 ++#define OCR1B10 2 ++#define OCR1B9 1 ++#define OCR1B8 0 ++/* OCR1BL */ ++#define OCR1B7 7 ++#define OCR1B6 6 ++#define OCR1B5 5 ++#define OCR1B4 4 ++#define OCR1B3 3 ++#define OCR1B2 2 ++#define OCR1B1 1 ++#define OCR1B0 0 ++ ++/* PSC0 Interrupt Flag Register */ ++#define PIFR0 _SFR_MEM8(0xA0) ++/* PIFR0 */ ++#define POAC0B 7 /* PSC0 Output B Activity */ ++#define POAC0A 6 /* PSC0 Output A Activity */ ++#define PSEI0 5 /* PSC0 Synchro Error Interrupt */ ++#define PEV0B 4 /* PSC0 External Event B Interrupt */ ++#define PEV0A 3 /* PSC0 External Event A Interrupt */ ++#define PRN01 2 /* PSC0 Ramp Number bit1 */ ++#define PRN00 1 /* PSC0 Ramp Number bit0 */ ++#define PEOP0 0 /* End Of PSC0 Interrupt */ ++ ++/* PSC0 Interrupt Mask Register */ ++#define PIM0 _SFR_MEM8(0xA1) ++/* PIM0 */ ++#define PSEIE0 5 /* PSC0 Synchro Error Interrupt Enable */ ++#define PEVE0B 4 /* PSC0 External Event B Interrupt Enable */ ++#define PEVE0A 3 /* PSC0 External Event A Interrupt Enable */ ++#define PEOPE0 0 /* PSC0 End Of Cycle Interrupt Enable */ ++ ++/* PSC1 Interrupt Flag Register */ ++#define PIFR1 _SFR_MEM8(0xA2) ++/* PIFR1 */ ++#define POAC1B 7 /* PSC1 Output B Activity */ ++#define POAC1A 6 /* PSC1 Output A Activity */ ++#define PSEI1 5 /* PSC1 Synchro Error Interrupt */ ++#define PEV1B 4 /* PSC1 External Event B Interrupt */ ++#define PEV1A 3 /* PSC1 External Event A Interrupt */ ++#define PRN11 2 /* PSC1 Ramp Number bit1 */ ++#define PRN10 1 /* PSC1 Ramp Number bit0 */ ++#define PEOP1 0 /* End Of PSC1 Interrupt */ ++ ++/* PSC1 Interrupt Mask Register */ ++#define PIM1 _SFR_MEM8(0xA3) ++/* PIM1 */ ++#define PSEIE1 5 /* PSC1 Synchro Error Interrupt Enable */ ++#define PEVE1B 4 /* PSC1 External Event B Interrupt Enable */ ++#define PEVE1A 3 /* PSC1 External Event A Interrupt Enable */ ++#define PEOPE1 0 /* PSC1 End Of Cycle Interrupt Enable */ ++ ++/* PSC2 Interrupt Flag Register */ ++#define PIFR2 _SFR_MEM8(0xA4) ++/* PIFR2 */ ++#define POAC2B 7 /* PSC2 Output B Activity */ ++#define POAC2A 6 /* PSC2 Output A Activity */ ++#define PSEI2 5 /* PSC2 Synchro Error Interrupt */ ++#define PEV2B 4 /* PSC2 External Event B Interrupt */ ++#define PEV2A 3 /* PSC2 External Event A Interrupt */ ++#define PRN21 2 /* PSC2 Ramp Number bit1 */ ++#define PRN20 1 /* PSC2 Ramp Number bit0 */ ++#define PEOP2 0 /* End Of PSC2 Interrupt */ ++ ++/* PSC2 Interrupt Mask Register */ ++#define PIM2 _SFR_MEM8(0xA5) ++/* PIM2 */ ++#define PSEIE2 5 /* PSC2 Synchro Error Interrupt Enable */ ++#define PEVE2B 4 /* PSC2 External Event B Interrupt Enable */ ++#define PEVE2A 3 /* PSC2 External Event A Interrupt Enable */ ++#define PEOPE2 0 /* PSC2 End Of Cycle Interrupt Enable */ ++ ++/* Digital to Analog Conversion Control Register */ ++#define DACON _SFR_MEM8(0xAA) ++/* DACON */ ++#define DAATE 7 /* DAC Auto Trigger Enable bit */ ++#define DATS2 6 /* DAC Trigger Selection bit2 */ ++#define DATS1 5 /* DAC Trigger Selection bit1 */ ++#define DATS0 4 /* DAC Trigger Selection bit0 */ ++#define DALA 2 /* Digital to Analog Left Adjust */ ++#define DAOE 1 /* Digital to Analog Output Enable bit */ ++#define DAEN 0 /* Digital to Analog Enable bit */ ++ ++/* Digital to Analog Converter input Register */ ++#define DAC _SFR_MEM16(0xAB) ++#define DACL _SFR_MEM8(0xAB) ++#define DACH _SFR_MEM8(0xAC) ++ ++/* Analog Comparator 0 Control Register */ ++#define AC0CON _SFR_MEM8(0xAD) ++/* AC0CON */ ++#define AC0EN 7 /* Analog Comparator 0 Enable Bit */ ++#define AC0IE 6 /* Analog Comparator 0 Interrupt Enable bit */ ++#define AC0IS1 5 /* Analog Comparator 0 Interrupt Select bit1 */ ++#define AC0IS0 4 /* Analog Comparator 0 Interrupt Select bit0 */ ++#define AC0M2 2 /* Analog Comparator 0 Multiplexer register bit2 */ ++#define AC0M1 1 /* Analog Comparator 0 Multiplexer register bit1 */ ++#define AC0M0 0 /* Analog Comparator 0 Multiplexer register bit0 */ ++ ++/* Analog Comparator 1 Control Register */ ++#define AC1CON _SFR_MEM8(0xAE) ++/* AC1CON */ ++#define AC1EN 7 /* Analog Comparator 1 Enable Bit */ ++#define AC1IE 6 /* Analog Comparator 1 Interrupt Enable bit */ ++#define AC1IS1 5 /* Analog Comparator 1 Interrupt Select bit1 */ ++#define AC1IS0 4 /* Analog Comparator 1 Interrupt Select bit0 */ ++#define AC1ICE 3 /* Analog Comparator 1 Interrupt Capture Enable bit */ ++#define AC1M2 2 /* Analog Comparator 1 Multiplexer register bit2 */ ++#define AC1M1 1 /* Analog Comparator 1 Multiplexer register bit1 */ ++#define AC1M0 0 /* Analog Comparator 1 Multiplexer register bit0 */ ++ ++/* Analog Comparator 2 Control Register */ ++#define AC2CON _SFR_MEM8(0xAF) ++/* AC2CON */ ++#define AC2EN 7 /* Analog Comparator 2 Enable Bit */ ++#define AC2IE 6 /* Analog Comparator 2 Interrupt Enable bit */ ++#define AC2IS1 5 /* Analog Comparator 2 Interrupt Select bit1 */ ++#define AC2IS0 4 /* Analog Comparator 2 Interrupt Select bit0 */ ++#define AC2M2 2 /* Analog Comparator 2 Multiplexer register bit2 */ ++#define AC2M1 1 /* Analog Comparator 2 Multiplexer register bit1 */ ++#define AC2M0 0 /* Analog Comparator 2 Multiplexer register bit0 */ ++ ++/* USART Control and Status Register A */ ++#define UCSRA _SFR_MEM8(0xC0) ++/* UCSRA */ ++#define RXC 7 /* USART Receive Complete */ ++#define TXC 6 /* USART Transmit Complete */ ++#define UDRE 5 /* USART Data Register Empty */ ++#define FE 4 /* Frame Error */ ++#define DOR 3 /* Data OverRun */ ++#define UPE 2 /* USART Parity Error */ ++#define U2X 1 /* Double the USART Transmission Speed */ ++#define MPCM 0 /* Multi-processor Communication Mode */ ++ ++/* USART Control and Status Register B */ ++#define UCSRB _SFR_MEM8(0xC1) ++/* UCSRB */ ++#define RXCIE 7 /* RX Complete Interrupt Enable */ ++#define TXCIE 6 /* TX Complete Interrupt Enable */ ++#define UDRIE 5 /* USART Data Register Empty Interrupt Enable */ ++#define RXEN 4 /* Receiver Enable */ ++#define TXEN 3 /* Transmitter Enable */ ++#define UCSZ2 2 /* Character Size */ ++#define RXB8 1 /* Receive Data Bit 8 */ ++#define TXB8 0 /* Transmit Data Bit 8 */ ++ ++/* USART Control and Status Register C */ ++#define UCSRC _SFR_MEM8(0xC2) ++/* UCSRC */ ++#define UMSEL 6 /* USART Mode Select */ ++#define UPM1 5 /* Parity Mode bit1 */ ++#define UPM0 4 /* Parity Mode bit0 */ ++#define USBS 3 /* Stop Bit Select */ ++#define UCSZ1 2 /* Character Size bit1 */ ++#define UCSZ0 1 /* Character Size bit0 */ ++#define UCPOL 0 /* Clock Polarity */ ++ ++/* USART Baud Rate Register */ ++#define UBRR _SFR_MEM16(0xC4) ++#define UBRRL _SFR_MEM8(0xC4) ++#define UBRRH _SFR_MEM8(0xC5) ++ ++/* USART I/O Data Register */ ++#define UDR _SFR_MEM8(0xC6) ++ ++/* EUSART Control and Status Register A */ ++#define EUCSRA _SFR_MEM8(0xC8) ++/* EUCSRA */ ++#define UTxS3 7 /* EUSART Transmit Character Size bit3 */ ++#define UTxS2 6 /* EUSART Transmit Character Size bit2 */ ++#define UTxS1 5 /* EUSART Transmit Character Size bit1 */ ++#define UTxS0 4 /* EUSART Transmit Character Size bit0 */ ++#define URxS3 3 /* EUSART Receive Character Size bit3 */ ++#define URxS2 2 /* EUSART Receive Character Size bit2 */ ++#define URxS1 1 /* EUSART Receive Character Size bit1 */ ++#define URxS0 0 /* EUSART Receive Character Size bit0 */ ++ ++/* EUSART Control and Status Register B */ ++#define EUCSRB _SFR_MEM8(0xC9) ++/* EUCSRB */ ++#define EUSART 4 /* EUSART Enable Bit */ ++#define EUSBS 3 /* EUSBS Enable Bit */ ++#define EMCH 1 /* Manchester mode */ ++#define BODR 0 /* Bit Order */ ++ ++/* EUSART Control and Status Register C */ ++#define EUCSRC _SFR_MEM8(0xCA) ++/* EUCSRC */ ++#define FEM 3 /* Frame Error Manchester */ ++#define F1617 2 ++#define STP1 1 /* Stop bits values bit1 */ ++#define STP0 0 /* Stop bits values bit0 */ ++ ++/* Manchester receiver Baud Rate Registers */ ++#define MUBRR _SFR_MEM16(0xCC) ++#define MUBRRL _SFR_MEM8(0xCC) ++#define MUBRRH _SFR_MEM8(0xCD) ++ ++/* EUSART I/O Data Register */ ++#define EUDR _SFR_MEM8(0xCE) ++ ++/* PSC 0 Synchro and Output Configuration */ ++#define PSOC0 _SFR_MEM8(0xD0) ++/* PSOC0 */ ++#define PSYNC01 5 /* Synchronization Out for ADC Selection bit1 */ ++#define PSYNC00 4 /* Synchronization Out for ADC Selection bit0 */ ++#define POEN0B 2 /* PSC 0 OUT Part B Output Enable */ ++#define POEN0A 0 /* PSC 0 OUT Part A Output Enable */ ++ ++/* Output Compare SA Registers */ ++#define OCR0SA _SFR_MEM16(0xD2) ++#define OCR0SAL _SFR_MEM8(0xD2) ++#define OCR0SAH _SFR_MEM8(0xD3) ++ ++/* Output Compare RA Registers */ ++#define OCR0RA _SFR_MEM16(0xD4) ++#define OCR0RAL _SFR_MEM8(0xD4) ++#define OCR0RAH _SFR_MEM8(0xD5) ++ ++/* Output Compare SB Registers */ ++#define OCR0SB _SFR_MEM16(0xD6) ++#define OCR0SBL _SFR_MEM8(0xD6) ++#define OCR0SBH _SFR_MEM8(0xD7) ++ ++/* Output Compare RB Registers */ ++#define OCR0RB _SFR_MEM16(0xD8) ++#define OCR0RBL _SFR_MEM8(0xD8) ++#define OCR0RBH _SFR_MEM8(0xD9) ++ ++/* PSC 0 Configuration Register */ ++#define PCNF0 _SFR_MEM8(0xDA) ++/* PCNF0 */ ++#define PFIFTY0 7 /* PSC 0 Fifty */ ++#define PALOCK0 6 /* PSC 0 Autolock */ ++#define PLOCK0 5 /* PSC 0 Lock */ ++#define PMODE01 4 /* PSC 0 Mode bit1 */ ++#define PMODE00 3 /* PSC 0 Mode bit0 */ ++#define POP0 2 /* PSC 0 Output Polarity */ ++#define PCLKSEL0 1 /* PSC 0 Input Clock Select */ ++ ++/* PSC 0 Control Register */ ++#define PCTL0 _SFR_MEM8(0xDB) ++/* PCTL0 */ ++#define PPRE01 7 /* PSC 0 Prescaler Select bit1 */ ++#define PPRE00 6 /* PSC 0 Prescaler Select bit0 */ ++#define PBFM0 5 /* Balance Flank Width Modulation */ ++#define PAOC0B 4 /* PSC 0 Asynchronous Output Control B */ ++#define PAOC0A 3 /* PSC 0 Asynchronous Output Control A */ ++#define PARUN0 2 /* PSC 0 Autorun */ ++#define PCCYC0 1 /* PSC 0 Complete Cycle */ ++#define PRUN0 0 /* PSC 0 Run */ ++ ++/* PSC 0 Input A Control Register */ ++#define PFRC0A _SFR_MEM8(0xDC) ++/* PFRC0A */ ++#define PCAE0A 7 /* PSC 0 Capture Enable Input Part A */ ++#define PISEL0A 6 /* PSC 0 Input Select for Part A */ ++#define PELEV0A 5 /* PSC 0 Edge Level Selector of Input Part A */ ++#define PFLTE0A 4 /* PSC 0 Filter Enable on Input Part A */ ++#define PRFM0A3 3 /* PSC 0 Fault Mode bit3 */ ++#define PRFM0A2 2 /* PSC 0 Fault Mode bit2 */ ++#define PRFM0A1 1 /* PSC 0 Fault Mode bit1 */ ++#define PRFM0A0 0 /* PSC 0 Fault Mode bit0 */ ++ ++/* PSC 0 Input B Control Register */ ++#define PFRC0B _SFR_MEM8(0xDD) ++/* PFRC0B */ ++#define PCAE0B 7 /* PSC 0 Capture Enable Input Part B */ ++#define PISEL0B 6 /* PSC 0 Input Select for Part B */ ++#define PELEV0B 5 /* PSC 0 Edge Level Selector of Input Part B */ ++#define PFLTE0B 4 /* PSC 0 Filter Enable on Input Part B */ ++#define PRFM0B3 3 /* PSC 0 Fault Mode bit3 */ ++#define PRFM0B2 2 /* PSC 0 Fault Mode bit2 */ ++#define PRFM0B1 1 /* PSC 0 Fault Mode bit1 */ ++#define PRFM0B0 0 /* PSC 0 Fault Mode bit0 */ ++ ++/* PSC 0 Input Capture Registers */ ++#define PICR0 _SFR_MEM16(0xDE) ++ ++#define PICR0L _SFR_MEM8(0xDE) ++ ++#define PICR0H _SFR_MEM8(0xDF) ++#define PCST0 7 /* PSC Capture Software Trig bit */ ++ /* not implemented on AT90PWM2/AT90PWM3 */ ++ ++/* PSC 1 Synchro and Output Configuration */ ++#define PSOC1 _SFR_MEM8(0xE0) ++/* PSOC1 */ ++#define PSYNC11 5 /* Synchronization Out for ADC Selection bit1 */ ++#define PSYNC10 4 /* Synchronization Out for ADC Selection bit0 */ ++#define POEN1B 2 /* PSC 1 OUT Part B Output Enable */ ++#define POEN1A 0 /* PSC 1 OUT Part A Output Enable */ ++ ++/* Output Compare SA Registers */ ++#define OCR1SA _SFR_MEM16(0xE2) ++#define OCR1SAL _SFR_MEM8(0xE2) ++#define OCR1SAH _SFR_MEM8(0xE3) ++ ++/* Output Compare RA Registers */ ++#define OCR1RA _SFR_MEM16(0xE4) ++#define OCR1RAL _SFR_MEM8(0xE4) ++#define OCR1RAH _SFR_MEM8(0xE5) ++ ++/* Output Compare SB Registers */ ++#define OCR1SB _SFR_MEM16(0xE6) ++#define OCR1SBL _SFR_MEM8(0xE6) ++#define OCR1SBH _SFR_MEM8(0xE7) ++ ++/* Output Compare RB Registers */ ++#define OCR1RB _SFR_MEM16(0xE8) ++#define OCR1RBL _SFR_MEM8(0xE8) ++#define OCR1RBH _SFR_MEM8(0xE9) ++ ++/* PSC 1 Configuration Register */ ++#define PCNF1 _SFR_MEM8(0xEA) ++/* PCNF1 */ ++#define PFIFTY1 7 /* PSC 1 Fifty */ ++#define PALOCK1 6 /* PSC 1 Autolock */ ++#define PLOCK1 5 /* PSC 1 Lock */ ++#define PMODE11 4 /* PSC 1 Mode bit1 */ ++#define PMODE10 3 /* PSC 1 Mode bit0 */ ++#define POP1 2 /* PSC 1 Output Polarity */ ++#define PCLKSEL1 1 /* PSC 1 Input Clock Select */ ++ ++/* PSC 1 Control Register */ ++#define PCTL1 _SFR_MEM8(0xEB) ++/* PCTL1 */ ++#define PPRE11 7 /* PSC 1 Prescaler Select bit1 */ ++#define PPRE10 6 /* PSC 1 Prescaler Select bit0 */ ++#define PBFM1 5 /* Balance Flank Width Modulation */ ++#define PAOC1B 4 /* PSC 1 Asynchronous Output Control B */ ++#define PAOC1A 3 /* PSC 1 Asynchronous Output Control A */ ++#define PARUN1 2 /* PSC 1 Autorun */ ++#define PCCYC1 1 /* PSC 1 Complete Cycle */ ++#define PRUN1 0 /* PSC 1 Run */ ++ ++/* PSC 1 Input A Control Register */ ++#define PFRC1A _SFR_MEM8(0xEC) ++/* PFRC1A */ ++#define PCAE1A 7 /* PSC 1 Capture Enable Input Part A */ ++#define PISEL1A 6 /* PSC 1 Input Select for Part A */ ++#define PELEV1A 5 /* PSC 1 Edge Level Selector of Input Part A */ ++#define PFLTE1A 4 /* PSC 1 Filter Enable on Input Part A */ ++#define PRFM1A3 3 /* PSC 1 Fault Mode bit3 */ ++#define PRFM1A2 2 /* PSC 1 Fault Mode bit2 */ ++#define PRFM1A1 1 /* PSC 1 Fault Mode bit1 */ ++#define PRFM1A0 0 /* PSC 1 Fault Mode bit0 */ ++ ++/* PSC 1 Input B Control Register */ ++#define PFRC1B _SFR_MEM8(0xED) ++/* PFRC1B */ ++#define PCAE1B 7 /* PSC 1 Capture Enable Input Part B */ ++#define PISEL1B 6 /* PSC 1 Input Select for Part B */ ++#define PELEV1B 5 /* PSC 1 Edge Level Selector of Input Part B */ ++#define PFLTE1B 4 /* PSC 1 Filter Enable on Input Part B */ ++#define PRFM1B3 3 /* PSC 1 Fault Mode bit3 */ ++#define PRFM1B2 2 /* PSC 1 Fault Mode bit2 */ ++#define PRFM1B1 1 /* PSC 1 Fault Mode bit1 */ ++#define PRFM1B0 0 /* PSC 1 Fault Mode bit0 */ ++ ++/* PSC 1 Input Capture Registers */ ++#define PICR1 _SFR_MEM16(0xEE) ++ ++#define PICR1L _SFR_MEM8(0xEE) ++ ++#define PICR1H _SFR_MEM8(0xEF) ++#define PCST1 7 /* PSC Capture Software Trig bit */ ++ /* not implemented on AT90PWM2/AT90PWM3 */ ++ ++/* PSC 2 Synchro and Output Configuration */ ++#define PSOC2 _SFR_MEM8(0xF0) ++/* PSOC2 */ ++#define POS23 7 /* PSCOUT23 Selection */ ++#define POS22 6 /* PSCOUT22 Selection */ ++#define PSYNC21 5 /* Synchronization Out for ADC Selection bit1 */ ++#define PSYNC20 4 /* Synchronization Out for ADC Selection bit0 */ ++#define POEN2D 3 /* PSCOUT23 Output Enable */ ++#define POEN2B 2 /* PSC 2 OUT Part B Output Enable */ ++#define POEN2C 1 /* PSCOUT22 Output Enable */ ++#define POEN2A 0 /* PSC 2 OUT Part A Output Enable */ ++ ++/* PSC 2 Output Matrix */ ++#define POM2 _SFR_MEM8(0xF1) ++/* POM2 */ ++#define POMV2B3 7 /* Output Matrix Output B Ramp 3 */ ++#define POMV2B2 6 /* Output Matrix Output B Ramp 2 */ ++#define POMV2B1 5 /* Output Matrix Output B Ramp 1 */ ++#define POMV2B0 4 /* Output Matrix Output B Ramp 0 */ ++#define POMV2A3 3 /* Output Matrix Output A Ramp 3 */ ++#define POMV2A2 2 /* Output Matrix Output A Ramp 2 */ ++#define POMV2A1 1 /* Output Matrix Output A Ramp 1 */ ++#define POMV2A0 0 /* Output Matrix Output A Ramp 0 */ ++ ++/* Output Compare SA Registers */ ++#define OCR2SA _SFR_MEM16(0xF2) ++#define OCR2SAL _SFR_MEM8(0xF2) ++#define OCR2SAH _SFR_MEM8(0xF3) ++ ++/* Output Compare RA Registers */ ++#define OCR2RA _SFR_MEM16(0xF4) ++#define OCR2RAL _SFR_MEM8(0xF4) ++#define OCR2RAH _SFR_MEM8(0xF5) ++ ++/* Output Compare SB Registers */ ++#define OCR2SB _SFR_MEM16(0xF6) ++#define OCR2SBL _SFR_MEM8(0xF6) ++#define OCR2SBH _SFR_MEM8(0xF7) ++ ++/* Output Compare RB Registers */ ++#define OCR2RB _SFR_MEM16(0xF8) ++#define OCR2RBL _SFR_MEM8(0xF8) ++#define OCR2RBH _SFR_MEM8(0xF9) ++ ++/* PSC 2 Configuration Register */ ++#define PCNF2 _SFR_MEM8(0xFA) ++/* PCNF2 */ ++#define PFIFTY2 7 /* PSC 2 Fifty */ ++#define PALOCK2 6 /* PSC 2 Autolock */ ++#define PLOCK2 5 /* PSC 2 Lock */ ++#define PMODE21 4 /* PSC 2 Mode bit1 */ ++#define PMODE20 3 /* PSC 2 Mode bit0 */ ++#define POP2 2 /* PSC 2 Output Polarity */ ++#define PCLKSEL2 1 /* PSC 2 Input Clock Select */ ++#define POME2 0 /* PSC 2 Output Matrix Enable */ ++ ++/* PSC 2 Control Register */ ++#define PCTL2 _SFR_MEM8(0xFB) ++/* PCTL2 */ ++#define PPRE21 7 /* PSC 2 Prescaler Select bit1 */ ++#define PPRE20 6 /* PSC 2 Prescaler Select bit0 */ ++#define PBFM2 5 /* Balance Flank Width Modulation */ ++#define PAOC2B 4 /* PSC 2 Asynchronous Output Control B */ ++#define PAOC2A 3 /* PSC 2 Asynchronous Output Control A */ ++#define PARUN2 2 /* PSC 2 Autorun */ ++#define PCCYC2 1 /* PSC 2 Complete Cycle */ ++#define PRUN2 0 /* PSC 2 Run */ ++ ++/* PSC 2 Input A Control Register */ ++#define PFRC2A _SFR_MEM8(0xFC) ++/* PFRC2A */ ++#define PCAE2A 7 /* PSC 2 Capture Enable Input Part A */ ++#define PISEL2A 6 /* PSC 2 Input Select for Part A */ ++#define PELEV2A 5 /* PSC 2 Edge Level Selector of Input Part A */ ++#define PFLTE2A 4 /* PSC 2 Filter Enable on Input Part A */ ++#define PRFM2A3 3 /* PSC 2 Fault Mode bit3 */ ++#define PRFM2A2 2 /* PSC 2 Fault Mode bit2 */ ++#define PRFM2A1 1 /* PSC 2 Fault Mode bit1 */ ++#define PRFM2A0 0 /* PSC 2 Fault Mode bit0 */ ++ ++/* PSC 2 Input B Control Register */ ++#define PFRC2B _SFR_MEM8(0xFD) ++/* PFRC2B */ ++#define PCAE2B 7 /* PSC 2 Capture Enable Input Part B */ ++#define PISEL2B 6 /* PSC 2 Input Select for Part B */ ++#define PELEV2B 5 /* PSC 2 Edge Level Selector of Input Part B */ ++#define PFLTE2B 4 /* PSC 2 Filter Enable on Input Part B */ ++#define PRFM2B3 3 /* PSC 2 Fault Mode bit3 */ ++#define PRFM2B2 2 /* PSC 2 Fault Mode bit2 */ ++#define PRFM2B1 1 /* PSC 2 Fault Mode bit1 */ ++#define PRFM2B0 0 /* PSC 2 Fault Mode bit0 */ ++ ++/* PSC 2 Input Capture Registers */ ++#define PICR2 _SFR_MEM16(0xFE) ++ ++#define PICR2L _SFR_MEM8(0xFE) ++ ++#define PICR2H _SFR_MEM8(0xFF) ++#define PCST2 7 /* PSC Capture Software Trig bit */ ++ /* not implemented on AT90PWM2/AT90PWM3 */ ++ ++ ++/* Interrupt vectors */ ++/* PSC2 Capture Event */ ++#define PSC2_CAPT_vect_num 1 ++#define PSC2_CAPT_vect _VECTOR(1) ++#define SIG_PSC2_CAPTURE _VECTOR(1) ++ ++/* PSC2 End Cycle */ ++#define PSC2_EC_vect_num 2 ++#define PSC2_EC_vect _VECTOR(2) ++#define SIG_PSC2_END_CYCLE _VECTOR(2) ++ ++/* PSC1 Capture Event */ ++#define PSC1_CAPT_vect_num 3 ++#define PSC1_CAPT_vect _VECTOR(3) ++#define SIG_PSC1_CAPTURE _VECTOR(3) ++ ++/* PSC1 End Cycle */ ++#define PSC1_EC_vect_num 4 ++#define PSC1_EC_vect _VECTOR(4) ++#define SIG_PSC1_END_CYCLE _VECTOR(4) ++ ++/* PSC0 Capture Event */ ++#define PSC0_CAPT_vect_num 5 ++#define PSC0_CAPT_vect _VECTOR(5) ++#define SIG_PSC0_CAPTURE _VECTOR(5) ++ ++/* PSC0 End Cycle */ ++#define PSC0_EC_vect_num 6 ++#define PSC0_EC_vect _VECTOR(6) ++#define SIG_PSC0_END_CYCLE _VECTOR(6) ++ ++/* Analog Comparator 0 */ ++#define ANALOG_COMP_0_vect_num 7 ++#define ANALOG_COMP_0_vect _VECTOR(7) ++#define SIG_COMPARATOR0 _VECTOR(7) ++ ++/* Analog Comparator 1 */ ++#define ANALOG_COMP_1_vect_num 8 ++#define ANALOG_COMP_1_vect _VECTOR(8) ++#define SIG_COMPARATOR1 _VECTOR(8) ++ ++/* Analog Comparator 2 */ ++#define ANALOG_COMP_2_vect_num 9 ++#define ANALOG_COMP_2_vect _VECTOR(9) ++#define SIG_COMPARATOR2 _VECTOR(9) ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 10 ++#define INT0_vect _VECTOR(10) ++#define SIG_INTERRUPT0 _VECTOR(10) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 11 ++#define TIMER1_CAPT_vect _VECTOR(11) ++#define SIG_INPUT_CAPTURE1 _VECTOR(11) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 12 ++#define TIMER1_COMPA_vect _VECTOR(12) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(12) ++#define SIG_OUTPUT_COMPARE1_A _VECTOR(12) ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect_num 13 ++#define TIMER1_COMPB_vect _VECTOR(13) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(13) ++#define SIG_OUTPUT_COMPARE1_B _VECTOR(13) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 15 ++#define TIMER1_OVF_vect _VECTOR(15) ++#define SIG_OVERFLOW1 _VECTOR(15) ++ ++/* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMP_A_vect_num 16 ++#define TIMER0_COMP_A_vect _VECTOR(16) ++#define SIG_OUTPUT_COMPARE0A _VECTOR(16) ++#define SIG_OUTPUT_COMPARE0_A _VECTOR(16) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 17 ++#define TIMER0_OVF_vect _VECTOR(17) ++#define SIG_OVERFLOW0 _VECTOR(17) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 18 ++#define ADC_vect _VECTOR(18) ++#define SIG_ADC _VECTOR(18) ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect_num 19 ++#define INT1_vect _VECTOR(19) ++#define SIG_INTERRUPT1 _VECTOR(19) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 20 ++#define SPI_STC_vect _VECTOR(20) ++#define SIG_SPI _VECTOR(20) ++ ++/* USART, Rx Complete */ ++#define USART_RX_vect_num 21 ++#define USART_RX_vect _VECTOR(21) ++#define SIG_USART_RECV _VECTOR(21) ++#define SIG_UART_RECV _VECTOR(21) ++ ++/* USART Data Register Empty */ ++#define USART_UDRE_vect_num 22 ++#define USART_UDRE_vect _VECTOR(22) ++#define SIG_USART_DATA _VECTOR(22) ++#define SIG_UART_DATA _VECTOR(22) ++ ++/* USART, Tx Complete */ ++#define USART_TX_vect_num 23 ++#define USART_TX_vect _VECTOR(23) ++#define SIG_USART_TRANS _VECTOR(23) ++#define SIG_UART_TRANS _VECTOR(23) ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect_num 24 ++#define INT2_vect _VECTOR(24) ++#define SIG_INTERRUPT2 _VECTOR(24) ++ ++/* Watchdog Timeout Interrupt */ ++#define WDT_vect_num 25 ++#define WDT_vect _VECTOR(25) ++#define SIG_WDT _VECTOR(25) ++#define SIG_WATCHDOG_TIMEOUT _VECTOR(25) ++ ++/* EEPROM Ready */ ++#define EE_READY_vect_num 26 ++#define EE_READY_vect _VECTOR(26) ++#define SIG_EEPROM_READY _VECTOR(26) ++ ++/* Timer Counter 0 Compare Match B */ ++#define TIMER0_COMPB_vect_num 27 ++#define TIMER0_COMPB_vect _VECTOR(27) ++#define SIG_OUTPUT_COMPARE0B _VECTOR(27) ++#define SIG_OUTPUT_COMPARE0_B _VECTOR(27) ++ ++/* External Interrupt Request 3 */ ++#define INT3_vect_num 28 ++#define INT3_vect _VECTOR(28) ++#define SIG_INTERRUPT3 _VECTOR(28) ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect_num 31 ++#define SPM_READY_vect _VECTOR(31) ++#define SIG_SPM_READY _VECTOR(31) ++ ++#define _VECTORS_SIZE 64 ++ ++/* Constants */ ++#define SPM_PAGESIZE 64 ++ ++#define RAMSTART 0x100 ++#define RAMEND 0x02FF ++#define XRAMEND RAMEND ++#define E2END 0x01FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x1FFF ++ ++ ++/* Fuse Information */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Diasble */ ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_PSCRV (unsigned char)~_BV(4) ++#define FUSE_PSC0RB (unsigned char)~_BV(5) ++#define FUSE_PSC1RB (unsigned char)~_BV(6) ++#define FUSE_PSC2RB (unsigned char)~_BV(7) ++#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++#endif /* _AVR_IO90PWMX_H_ */ +diff --git a/include/avr/io90scr100.h b/include/avr/io90scr100.h +index bb6a973..e425868 100644 +--- a/include/avr/io90scr100.h ++++ b/include/avr/io90scr100.h +@@ -1,1698 +1,1698 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: io90scr100.h 1910 2009-03-04 17:45:30Z arcanum $ */ +- +-/* avr/io90scr100.h - definitions for AT90SCR100 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "io90scr100.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_AT90SCR100_H_ +-#define _AVR_AT90SCR100_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +-#define PINA4 4 +-#define PINA5 5 +-#define PINA6 6 +-#define PINA7 7 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +-#define DDA4 4 +-#define DDA5 5 +-#define DDA6 6 +-#define DDA7 7 +- +-#define PORTA _SFR_IO8(0x02) +-#define PORTA0 0 +-#define PORTA1 1 +-#define PORTA2 2 +-#define PORTA3 3 +-#define PORTA4 4 +-#define PORTA5 5 +-#define PORTA6 6 +-#define PORTA7 7 +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +-#define PINC7 7 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC3 3 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +-#define DDC7 7 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC3 3 +-#define PORTC4 4 +-#define PORTC5 5 +-#define PORTC6 6 +-#define PORTC7 7 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define PINE _SFR_IO8(0x0C) +-#define PINE0 0 +-#define PINE1 1 +-#define PINE2 2 +-#define PINE3 3 +-#define PINE4 4 +-#define PINE5 5 +-#define PINE6 6 +-#define PINE7 7 +- +-#define DDRE _SFR_IO8(0x0D) +-#define DDE0 0 +-#define DDE1 1 +-#define DDE2 2 +-#define DDE3 3 +-#define DDE4 4 +-#define DDE5 5 +-#define DDE6 6 +-#define DDE7 7 +- +-#define PORTE _SFR_IO8(0x0E) +-#define PORTE0 0 +-#define PORTE1 1 +-#define PORTE2 2 +-#define PORTE3 3 +-#define PORTE4 4 +-#define PORTE5 5 +-#define PORTE6 6 +-#define PORTE7 7 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- -#define TIFR2 _SFR_IO8(0x17) -#define TOV2 0 -#define OCF2A 1 -#define OCF2B 2 - - #define TIFR3 _SFR_IO8(0x18) - #define TOV3 0 - #define OCF3A 1 -@@ -922,51 +917,6 @@ - - #define UPDATX _SFR_MEM8(0xAF) - +-#define EIRR _SFR_IO8(0x1A) +-#define INTD2 2 +-#define INTD3 3 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +-#define PCIF1 1 +-#define PCIF2 2 +-#define PCIF3 3 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +-#define INTF2 2 +-#define INTF3 3 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +-#define INT2 2 +-#define INT3 3 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +-#define EEAR9 1 +-#define EEAR10 2 +-#define EEAR11 3 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSRSYNC 0 +-#define PSRASY 1 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define OCR0A _SFR_IO8(0x27) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define OCR0B _SFR_IO8(0x28) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define OCDR _SFR_IO8(0x31) +-#define OCDR0 0 +-#define OCDR1 1 +-#define OCDR2 2 +-#define OCDR3 3 +-#define OCDR4 4 +-#define OCDR5 5 +-#define OCDR6 6 +-#define OCDR7 7 +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +-#define JTRF 4 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define BODSE 5 +-#define BODS 6 +-#define JTD 7 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define SIGRD 5 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define RAMPZ _SFR_IO8(0x3B) +-#define RAMPZ0 0 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define PLLCR _SFR_MEM8(0x62) +-#define ON 0 +-#define LOCK 1 +-#define PLLMUX 7 +- +-#define SMONCR _SFR_MEM8(0x63) +-#define SMONEN 0 +-#define SMONIE 1 +-#define SMONIF 4 +- +-#define PRR0 _SFR_MEM8(0x64) +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM1 3 +-#define PRTIM0 5 +-#define PRTIM2 6 +-#define PRTWI 7 +- +-#define PRR1 _SFR_MEM8(0x65) +-#define PRUSBH 0 +-#define PRUSB 1 +-#define PRHSSPI 2 +-#define PRSCI 3 +-#define PRAES 4 +-#define PRKB 5 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +-#define PCIE1 1 +-#define PCIE2 2 +-#define PCIE3 3 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define ISC20 4 +-#define ISC21 5 +-#define ISC30 6 +-#define ISC31 7 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-#define PCMSK2 _SFR_MEM8(0x6D) +-#define PCINT16 0 +-#define PCINT17 1 +-#define PCINT18 2 +-#define PCINT19 3 +-#define PCINT20 4 +-#define PCINT21 5 +-#define PCINT22 6 +-#define PCINT23 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define TIMSK2 _SFR_MEM8(0x70) +-#define TOIE2 0 +-#define OCIE2A 1 +-#define OCIE2B 2 +- +-#define PCMSK3 _SFR_MEM8(0x73) +- +-#define LEDCR _SFR_MEM8(0x75) +-#define LED00 0 +-#define LED01 1 +-#define LED10 2 +-#define LED11 3 +-#define LED20 4 +-#define LED21 5 +-#define lED30 6 +-#define LED31 7 +- +-#define AESCR _SFR_MEM8(0x78) +-#define AESGO 0 +-#define ENCRYPT 1 +-#define KS 3 +-#define KEYGN 4 +-#define AUTOKEY 5 +-#define AESIF 6 +-#define AESIE 7 +- +-#define AESACR _SFR_MEM8(0x79) +-#define KD 0 +-#define AUTOINC 1 +-#define MANINC 2 +-#define XOR 3 +- +-#define AESADDR _SFR_MEM8(0x7A) +-#define ADDR0 0 +-#define ADDR1 1 +-#define ADDR2 2 +-#define ADDR3 3 +-#define ADDR4 4 +-#define ADDR5 5 +-#define ADDR6 6 +-#define ADDR7 7 +- +-#define AESDR _SFR_MEM8(0x7B) +-#define DATA0 0 +-#define DATA1 1 +-#define DATA2 2 +-#define DATA3 3 +-#define DATA4 4 +-#define DATA5 5 +-#define DATA6 6 +-#define DATA7 7 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define KBLSR _SFR_MEM8(0x8D) +-#define KBLS0 0 +-#define KBLS1 1 +-#define KBLS2 2 +-#define KBLS3 3 +-#define KBLS4 4 +-#define KBLS5 5 +-#define KBLS6 6 +-#define KBLS7 7 +- +-#define KBER _SFR_MEM8(0x8E) +-#define KBE0 0 +-#define KBE1 1 +-#define KBE2 2 +-#define KBE3 3 +-#define KBE4 4 +-#define KBE5 5 +-#define KBE6 6 +-#define KBE7 7 +- +-#define KBFR _SFR_MEM8(0x8F) +-#define KBF0 0 +-#define KBF1 1 +-#define KBF2 2 +-#define KBF3 3 +-#define KBF4 4 +-#define KBF5 5 +-#define KBF6 6 +-#define KBF7 7 +- +-#define RDWDR _SFR_MEM8(0x90) +-#define RDD0 0 +-#define RDD1 1 +-#define RDD2 2 +-#define RDD3 3 +-#define RDD4 4 +-#define RDD5 5 +-#define RDD6 6 +-#define RDD7 7 +- +-#define LFSR0 _SFR_MEM8(0x91) +-#define LFSD0 0 +-#define LFSD1 1 +-#define LFSD2 2 +-#define LFSD3 3 +-#define LFSD4 4 +-#define LFSD5 5 +-#define LFSD6 6 +-#define LFSD7 7 +- +-#define LFSR1 _SFR_MEM8(0x92) +-#define LFSD8 0 +-#define LFSD9 1 +-#define LFSD10 2 +-#define LFSD11 3 +-#define LFSD12 4 +-#define LFSD13 5 +-#define LFSD14 6 +-#define LFSD15 7 +- +-#define LFSR2 _SFR_MEM8(0x93) +-#define LFSD16 0 +-#define LFSD17 1 +-#define LFSD18 2 +-#define LFSD19 3 +-#define LFSD20 4 +-#define LFSD21 5 +-#define LFSD22 6 +-#define LFSD23 7 +- +-#define LFSR3 _SFR_MEM8(0x94) +-#define LFSD24 0 +-#define LFSD25 1 +-#define LFSD26 2 +-#define LFSD27 3 +-#define LFSD28 4 +-#define LFSD29 5 +-#define LFSD30 6 +-#define LFSD31 7 +- +-#define RNGCR _SFR_MEM8(0x95) +-#define ROSCE 0 +- +-#define UHSR _SFR_MEM8(0x99) +-#define SPEED 3 +- +-#define UPINT _SFR_MEM8(0x9A) +-#define PINT0 0 +-#define PINT1 1 +-#define PINT2 2 +-#define PINT3 3 +- +-#define UPBCX _SFR_MEM16(0x9B) +- +-#define UPBCXL _SFR_MEM8(0x9B) +-#define PBYTCT0 0 +-#define PBYTCT1 1 +-#define PBYTCT2 2 +-#define PBYTCT3 3 +-#define PBYTCT4 4 +-#define PBYTCT5 5 +-#define PBYTCT6 6 +-#define PBYTCT7 7 +- +-#define UPBCXH _SFR_MEM8(0x9C) +-#define PBYTCT8 0 +-#define PBYTCT9 1 +-#define PBYTCT10 2 +- +-#define UPERRX _SFR_MEM8(0x9D) +-#define DATATGL 0 +-#define DATAPID 1 +-#define PID 2 +-#define PTIMEOUT 3 +-#define CRC16 4 +-#define COUNTER0 5 +-#define COUNTER1 6 +- +-#define UHCR _SFR_MEM8(0x9E) +-#define SOFEN 0 +-#define RESET 1 +-#define RESUME 2 +-#define FRZCLK 4 +-#define PAD0 5 +-#define PAD1 6 +-#define UHEN 7 +- +-#define UHINT _SFR_MEM8(0x9F) +-#define DCONNI 0 +-#define DDISCI 1 +-#define RSTI 2 +-#define RSMEDI 3 +-#define RXRSMI 4 +-#define HSOFI 5 +-#define HWUPI 6 +- +-#define UHIEN _SFR_MEM8(0xA0) +-#define DCONNE 0 +-#define DDISCE 1 +-#define RSTE 2 +-#define RSMEDE 3 +-#define RXRSME 4 +-#define HSOFE 5 +-#define HWUPE 6 +- +-#define UHADDR _SFR_MEM8(0xA1) +-#define HADDR0 0 +-#define HADDR1 1 +-#define HADDR2 2 +-#define HADDR3 3 +-#define HADDR4 4 +-#define HADDR5 5 +-#define HADDR6 6 +- +-#define UHFNUM _SFR_MEM16(0xA2) +- +-#define UHFNUML _SFR_MEM8(0xA2) +-#define FNUM0 0 +-#define FNUM1 1 +-#define FNUM2 2 +-#define FNUM3 3 +-#define FNUM4 4 +-#define FNUM5 5 +-#define FNUM6 6 +-#define FNUM7 7 +- +-#define UHFNUMH _SFR_MEM8(0xA3) +-#define FNUM8 0 +-#define FNUM9 1 +-#define FNUM10 2 +- +-#define UHFLEN _SFR_MEM8(0xA4) +-#define FLEN0 0 +-#define FLEN1 1 +-#define FLEN2 2 +-#define FLEN3 3 +-#define FLEN4 4 +-#define FLEN5 5 +-#define FLEN6 6 +-#define FLEN7 7 +- +-#define UPINRQX _SFR_MEM8(0xA5) +-#define INRQ0 0 +-#define INRQ1 1 +-#define INRQ2 2 +-#define INRQ3 3 +-#define INRQ4 4 +-#define INRQ5 5 +-#define INRQ6 6 +-#define INRQ7 7 +- +-#define UPINTX _SFR_MEM8(0xA6) +-#define RXINI 0 +-#define RXSTALLI 1 +-#define TXOUTI 2 +-#define TXSTPI 3 +-#define PERRI 4 +-#define RWAL 5 +-#define NAKEDI 6 +-#define FIFOCON 7 +- +-#define UPNUM _SFR_MEM8(0xA7) +-#define PNUM0 0 +-#define PNUM1 1 +- +-#define UPRST _SFR_MEM8(0xA8) +-#define P0RST 0 +-#define P1RST 1 +-#define P2RST 2 +-#define P3RST 3 +- +-#define UPCRX _SFR_MEM8(0xA9) +-#define PEN 0 +-#define RSTDT 3 +-#define INMODE 5 +-#define PFREEZE 6 +- +-#define UPCFG0X _SFR_MEM8(0xAA) +-#define PEPNUM0 0 +-#define PEPNUM1 1 +-#define PEPNUM2 2 +-#define PEPNUM3 3 +-#define PTOKEN0 4 +-#define PTOKEN1 5 +-#define PTYPE0 6 +-#define PTYPE1 7 +- +-#define UPCFG1X _SFR_MEM8(0xAB) +-#define ALLOC 1 +-#define PBK0 2 +-#define PBK1 3 +-#define PSIZE0 4 +-#define PSIZE1 5 +-#define PSIZE2 6 +- +-#define UPSTAX _SFR_MEM8(0xAC) +-#define NBUSYBK0 0 +-#define NBUSYBK1 1 +-#define DTSEQ0 2 +-#define DTSEQ1 3 +-#define UNDERFI 5 +-#define OVERFI 6 +-#define CFGOK 7 +- +-#define UPCFG2X _SFR_MEM8(0xAD) +-#define INTFRQ0 0 +-#define INTFRQ1 1 +-#define INTFRQ2 2 +-#define INTFRQ3 3 +-#define INTFRQ4 4 +-#define INTFRQ5 5 +-#define INTFRQ6 6 +-#define INTFRQ7 7 +- +-#define UPIENX _SFR_MEM8(0xAE) +-#define RXINE 0 +-#define RXSTALLE 1 +-#define TXOUTE 2 +-#define TXSTPE 3 +-#define PERRE 4 +-#define NAKEDE 6 +-#define FLERRE 7 +- +-#define UPDATX _SFR_MEM8(0xAF) +-#define PDAT0 0 +-#define PDAT1 1 +-#define PDAT2 2 +-#define PDAT3 3 +-#define PDAT4 4 +-#define PDAT5 5 +-#define PDAT6 6 +-#define PDAT7 7 +- +-#define TCCR2A _SFR_MEM8(0xB0) +-#define WGM20 0 +-#define WGM21 1 +-#define COM2B0 4 +-#define COM2B1 5 +-#define COM2A0 6 +-#define COM2A1 7 +- +-#define TCCR2B _SFR_MEM8(0xB1) +-#define CS20 0 +-#define CS21 1 +-#define CS22 2 +-#define WGM22 3 +-#define FOC2B 6 +-#define FOC2A 7 +- +-#define TCNT2 _SFR_MEM8(0xB2) +-#define TCNT2_0 0 +-#define TCNT2_1 1 +-#define TCNT2_2 2 +-#define TCNT2_3 3 +-#define TCNT2_4 4 +-#define TCNT2_5 5 +-#define TCNT2_6 6 +-#define TCNT2_7 7 +- +-#define OCR2A _SFR_MEM8(0xB3) +-#define OCR2A0 0 +-#define OCR2A1 1 +-#define OCR2A2 2 +-#define OCR2A3 3 +-#define OCR2A4 4 +-#define OCR2A5 5 +-#define OCR2A6 6 +-#define OCR2A7 7 +- +-#define OCR2B _SFR_MEM8(0xB4) +-#define OCR2B0 0 +-#define OCR2B1 1 +-#define OCR2B2 2 +-#define OCR2B3 3 +-#define OCR2B4 4 +-#define OCR2B5 5 +-#define OCR2B6 6 +-#define OCR2B7 7 +- +-#define ASSR _SFR_MEM8(0xB6) +-#define TCR2BUB 0 +-#define TCR2AUB 1 +-#define OCR2BUB 2 +-#define OCR2AUB 3 +-#define TCN2UB 4 +-#define AS2 5 +-#define EXCLK 6 +- +-#define TWBR _SFR_MEM8(0xB8) +-#define TWBR0 0 +-#define TWBR1 1 +-#define TWBR2 2 +-#define TWBR3 3 +-#define TWBR4 4 +-#define TWBR5 5 +-#define TWBR6 6 +-#define TWBR7 7 +- +-#define TWSR _SFR_MEM8(0xB9) +-#define TWPS0 0 +-#define TWPS1 1 +-#define TWS3 3 +-#define TWS4 4 +-#define TWS5 5 +-#define TWS6 6 +-#define TWS7 7 +- +-#define TWAR _SFR_MEM8(0xBA) +-#define TWGCE 0 +-#define TWA0 1 +-#define TWA1 2 +-#define TWA2 3 +-#define TWA3 4 +-#define TWA4 5 +-#define TWA5 6 +-#define TWA6 7 +- +-#define TWDR _SFR_MEM8(0xBB) +-#define TWD0 0 +-#define TWD1 1 +-#define TWD2 2 +-#define TWD3 3 +-#define TWD4 4 +-#define TWD5 5 +-#define TWD6 6 +-#define TWD7 7 +- +-#define TWCR _SFR_MEM8(0xBC) +-#define TWIE 0 +-#define TWEN 2 +-#define TWWC 3 +-#define TWSTO 4 +-#define TWSTA 5 +-#define TWEA 6 +-#define TWINT 7 +- +-#define TWAMR _SFR_MEM8(0xBD) +-#define TWAM0 1 +-#define TWAM1 2 +-#define TWAM2 3 +-#define TWAM3 4 +-#define TWAM4 5 +-#define TWAM5 6 +-#define TWAM6 7 +- +-#define UCSR0A _SFR_MEM8(0xC0) +-#define MPCM0 0 +-#define U2X0 1 +-#define UPE0 2 +-#define DOR0 3 +-#define FE0 4 +-#define UDRE0 5 +-#define TXC0 6 +-#define RXC0 7 +- +-#define UCSR0B _SFR_MEM8(0xC1) +-#define TXB80 0 +-#define RXB80 1 +-#define UCSZ02 2 +-#define TXEN0 3 +-#define RXEN0 4 +-#define UDRIE0 5 +-#define TXCIE0 6 +-#define RXCIE0 7 +- +-#define UCSR0C _SFR_MEM8(0xC2) +-#define UCPOL0 0 +-#define UCSZ00 1 +-#define UCSZ01 2 +-#define USBS0 3 +-#define UPM00 4 +-#define UPM01 5 +-#define UMSEL00 6 +-#define UMSEL01 7 +- +-#define UBRR0 _SFR_MEM16(0xC4) +- +-#define UBRR0L _SFR_MEM8(0xC4) +-#define UBRR00 0 +-#define UBRR01 1 +-#define UBRR02 2 +-#define UBRR03 3 +-#define UBRR04 4 +-#define UBRR05 5 +-#define UBRR06 6 +-#define UBRR07 7 +- +-#define UBRR0H _SFR_MEM8(0xC5) +-#define UBRR08 0 +-#define UBRR09 1 +-#define UBRR010 2 +-#define UBRR011 3 +- +-#define UDR0 _SFR_MEM8(0xC6) +-#define UDR00 0 +-#define UDR01 1 +-#define UDR02 2 +-#define UDR03 3 +-#define UDR04 4 +-#define UDR05 5 +-#define UDR06 6 +-#define UDR07 7 +- +-#define USBENUM _SFR_MEM8(0xCA) +-#define USBENUM0 0 +-#define USBENUM1 1 +-#define USBENUM2 2 +- +-#define USBCSEX _SFR_MEM8(0xCB) +-#define TXC 0 +-#define RCVD 1 +-#define RXSETUP 2 +-#define STSENT 3 +-#define TXPB 4 +-#define FSTALL 5 +-#define IERR 6 +- +-#define USBDBCEX _SFR_MEM8(0xCC) +-#define BCT0 0 +-#define BCT1 1 +-#define BCT2 2 +-#define BCT3 3 +-#define BCT4 4 +-#define BCT5 5 +-#define BCT6 6 +-#define BCT7 7 +- +-#define USBFCEX _SFR_MEM8(0xCD) +-#define EPTYP0 0 +-#define EPTYP1 1 +-#define EPDIR 2 +-#define EPE 7 +- +-#define HSSPITO _SFR_MEM16(0xD1) +- +-#define HSSPITOL _SFR_MEM8(0xD1) +-#define HSSPITOD0 0 +-#define HSSPITOD1 1 +-#define HSSPITOD2 2 +-#define HSSPITOD3 3 +-#define HSSPITOD4 4 +-#define HSSPITOD5 5 +-#define HSSPITOD6 6 +-#define HSSPITOD7 7 +- +-#define HSSPITOH _SFR_MEM8(0xD2) +-#define HSSPITOD8 0 +-#define HSSPITOD9 1 +-#define HSSPITOD10 2 +-#define HSSPITOD11 3 +-#define HSSPITOD12 4 +-#define HSSPITOD13 5 +-#define HSSPITOD14 6 +-#define HSSPITOD15 7 +- +-#define HSSPICNT _SFR_MEM8(0xD3) +-#define HSSPICNTD0 0 +-#define HSSPICNTD1 1 +-#define HSSPICNTD2 2 +-#define HSSPICNTD3 3 +-#define HSSPICNTD4 4 +- +-#define HSSPIIER _SFR_MEM8(0xD4) +-#define NSSIE 4 +-#define RCVOFIE 5 +-#define BTDIE 6 +-#define TIMEOUTIE 7 +- +-#define HSSPIGTR _SFR_MEM8(0xD5) +-#define HSSPIGTD0 0 +-#define HSSPIGTD1 1 +-#define HSSPIGTD2 2 +-#define HSSPIGTD3 3 +-#define HSSPIGTD4 4 +-#define HSSPIGTD5 5 +-#define HSSPIGTD6 6 +-#define HSSPIGTD7 7 +- +-#define HSSPIRDR _SFR_MEM8(0xD6) +-#define HSSPIRDD0 0 +-#define HSSPIRDD1 1 +-#define HSSPIRDD2 2 +-#define HSSPIRDD3 3 +-#define HSSPIRDD4 4 +-#define HSSPIRDD5 5 +-#define HSSPIRDD6 6 +-#define HSSPIRDD7 7 +- +-#define HSSPITDR _SFR_MEM8(0xD7) +-#define HSSPITDD0 0 +-#define HSSPITDD1 1 +-#define HSSPITDD2 2 +-#define HSSPITDD3 3 +-#define HSSPITDD4 4 +-#define HSSPITDD5 5 +-#define HSSPITDD6 6 +-#define HSSPITDD7 7 +- +-#define HSSPISR _SFR_MEM8(0xD8) +-#define SPICKRDY 0 +-#define TXBUFE 1 +-#define RXBUFF 2 +-#define NSS 3 +-#define DPRAMRDY 4 +- +-#define HSSPICFG _SFR_MEM8(0xD9) +-#define HSSPIEN 0 +-#define HSMSTR 1 +-#define HSCPOL 2 +-#define HSCPHA 3 +-#define DPRAM 4 +-#define SPICKDIV0 5 +-#define SPICKDIV1 6 +-#define SPICKDIV2 7 +- +-#define HSSPIIR _SFR_MEM8(0xDA) +-#define NSSFE 3 +-#define NSSRE 4 +-#define RCVOF 5 +-#define BTD 6 +-#define TIMEOUT 7 +- +-#define HSSPICR _SFR_MEM8(0xDB) +-#define CS 0 +-#define RETTO 1 +-#define STTTO 2 +- +-#define HSSPIDMACS _SFR_MEM8(0xDC) +-#define HSSPIDMAR 0 +-#define HSSPIDMADIR 1 +-#define HSSPIDMAERR 2 +- +-#define HSSPIDMAD _SFR_MEM16(0xDD) +- +-#define HSSPIDMADL _SFR_MEM8(0xDD) +-#define HSSPIDMAD0 0 +-#define HSSPIDMAD1 1 +-#define HSSPIDMAD2 2 +-#define HSSPIDMAD3 3 +-#define HSSPIDMAD4 4 +-#define HSSPIDMAD5 5 +-#define HSSPIDMAD6 6 +-#define HSSPIDMAD7 7 +- +-#define HSSPIDMADH _SFR_MEM8(0xDE) +-#define HSSPIDMAD8 0 +-#define HSSPIDMAD9 1 +-#define HSSPIDMAD10 2 +-#define HSSPIDMAD11 3 +-#define HSSPIDMAD12 4 +-#define HSSPIDMAD13 5 +- +-#define HSSPIDMAB _SFR_MEM8(0xDF) +-#define HSSPIDMAB0 0 +-#define HSSPIDMAB1 1 +-#define HSSPIDMAB2 2 +-#define HSSPIDMAB3 3 +-#define HSSPIDMAB4 4 +- +-#define USBCR _SFR_MEM8(0xE0) +-#define USBE 1 +-#define UPUC 5 +-#define URMWU 7 +- +-#define USBPI _SFR_MEM8(0xE1) +-#define SUSI 0 +-#define RESI 1 +-#define RMWUI 2 +-#define SOFI 3 +-#define FEURI 4 +- +-#define USBPIM _SFR_MEM8(0xE2) +-#define SUSIM 0 +-#define RESIM 1 +-#define RMWUIM 2 +-#define SOFIM 3 +- +-#define USBEI _SFR_MEM8(0xE3) +-#define EP0I 0 +-#define EP1I 1 +-#define EP2I 2 +-#define EP3I 3 +-#define EP4I 4 +-#define EP5I 5 +-#define EP6I 6 +-#define EP7I 7 +- +-#define USBEIM _SFR_MEM8(0xE4) +-#define EP0IM 0 +-#define EP1IM 1 +-#define EP2IM 2 +-#define EP3IM 3 +-#define EP4IM 4 +-#define EP5IM 5 +-#define EP6IM 6 +-#define EP7IM 7 +- +-#define USBRSTE _SFR_MEM8(0xE5) +-#define RSTE0 0 +-#define RSTE1 1 +-#define RSTE2 2 +-#define RSTE3 3 +-#define RSTE4 4 +-#define RSTE5 5 +-#define RSTE6 6 +-#define RST7 7 +- +-#define USBGS _SFR_MEM8(0xE6) +-#define FAF 0 +-#define FCF 1 +-#define RMWUE 2 +-#define RSMON 3 +- +-#define USBFA _SFR_MEM8(0xE7) +-#define FADD0 0 +-#define FADD1 1 +-#define FADD2 2 +-#define FADD3 3 +-#define FADD4 4 +-#define FADD5 5 +-#define FADD6 6 +- +-#define USBFN _SFR_MEM16(0xE8) +- +-#define USBFNL _SFR_MEM8(0xE8) +-#define FN0 0 +-#define FN1 1 +-#define FN2 2 +-#define FN3 3 +-#define FN4 4 +-#define FN5 5 +-#define FN6 6 +-#define FN7 7 +- +-#define USBFNH _SFR_MEM8(0xE9) +-#define FN8 0 +-#define FN9 1 +-#define FN10 2 +-#define FNERR 3 +-#define FNEND 4 +- +-#define USBDMACS _SFR_MEM8(0xEA) +-#define USBDMAR 0 +-#define USBDMADIR 1 +-#define USBDMAERR 2 +-#define EPS0 4 +-#define EPS1 5 +-#define EPS2 6 +- +-#define USBDMAD _SFR_MEM16(0xEB) +- +-#define USBDMADL _SFR_MEM8(0xEB) +-#define USBDMAD0 0 +-#define USBDMAD1 1 +-#define USBDMAD2 2 +-#define USBDMAD3 3 +-#define USBDMAD4 4 +-#define USBDMAD5 5 +-#define USBDMAD6 6 +-#define USBDMAD7 7 +- +-#define USBDMADH _SFR_MEM8(0xEC) +-#define USBDMAD8 0 +-#define USBDMAD9 1 +-#define USBDMAD10 2 +-#define USBDMAD11 3 +-#define USBDMAD12 4 +-#define USBDMAD13 5 +- +-#define USBDMAB _SFR_MEM8(0xED) +-#define USBDMAB0 0 +-#define USBDMAB1 1 +-#define USBDMAB2 2 +-#define USBDMAB3 3 +-#define USBDMAB4 4 +-#define USBDMAB5 5 +-#define USBDMAB6 6 +- +-#define DCCR _SFR_MEM8(0xEF) +-#define DCBUSY 5 +-#define DCRDY 6 +-#define DCON 7 +- +-#define SCICLK _SFR_MEM8(0xF0) +-#define SCICLK0 0 +-#define SCICLK1 1 +-#define SCICLK2 2 +-#define SCICLK3 3 +-#define SCICLK4 4 +-#define SCICLK5 5 +- +-#define SCWT0 _SFR_MEM8(0xF1) +-#define WT0 0 +-#define WT1 1 +-#define WT2 2 +-#define WT3 3 +-#define WT4 4 +-#define WT5 5 +-#define WT6 6 +-#define WT7 7 +- +-#define SCWT1 _SFR_MEM8(0xF2) +-#define WT8 0 +-#define WT9 1 +-#define WT10 2 +-#define WT11 3 +-#define WT12 4 +-#define WT13 5 +-#define WT14 6 +-#define WT15 7 +- +-#define SCWT2 _SFR_MEM8(0xF3) +-#define WT16 0 +-#define WT17 1 +-#define WT18 2 +-#define WT19 3 +-#define WT20 4 +-#define WT21 5 +-#define WT22 6 +-#define WT23 7 +- +-#define SCWT3 _SFR_MEM8(0xF4) +-#define WT24 0 +-#define WT25 1 +-#define WT26 2 +-#define WT27 3 +-#define WT28 4 +-#define WT29 5 +-#define WT30 6 +-#define WT31 7 +- +-#define SCGT _SFR_MEM16(0xF5) +- +-#define SCGTL _SFR_MEM8(0xF5) +-#define GT0 0 +-#define GT1 1 +-#define GT2 2 +-#define GT3 3 +-#define GT4 4 +-#define GT5 5 +-#define GT6 6 +-#define GT7 7 +- +-#define SCGTH _SFR_MEM8(0xF6) +-#define GT8 0 +- +-#define SCETU _SFR_MEM16(0xF7) +- +-#define SCETUL _SFR_MEM8(0xF7) +-#define ETU0 0 +-#define ETU1 1 +-#define ETU2 2 +-#define ETU3 3 +-#define ETU4 4 +-#define ETU5 5 +-#define ETU6 6 +-#define ETU7 7 +- +-#define SCETUH _SFR_MEM8(0xF8) +-#define ETU8 0 +-#define ETU9 1 +-#define ETU10 2 +-#define COMP 7 +- +-#define SCIBUF _SFR_MEM8(0xF9) +-#define SCIBUFD0 0 +-#define SCIBUFD1 1 +-#define SCIBUFD2 2 +-#define SCIBUFD3 3 +-#define SCIBUFD4 4 +-#define SCIBUFD5 5 +-#define SCIBUFD6 6 +-#define SCIBUFD7 7 +- +-#define SCSR _SFR_MEM8(0xFA) +-#define CPRESRES 3 +-#define CREPSEL 4 +-#define BGTEN 6 +- +-#define SCIER _SFR_MEM8(0xFB) +-#define ESCPI 0 +-#define ESCRI 1 +-#define ESCTI 2 +-#define ESCWTI 3 +-#define EVCARDER 4 +-#define CARDINE 6 +-#define ESCTBI 7 +- +-#define SCIIR _SFR_MEM8(0xFC) +-#define SCPI 0 +-#define SCRI 1 +-#define SCTI 2 +-#define SCWTI 3 +-#define VCARDERR 4 +-#define SCTBI 7 +- +-#define SCISR _SFR_MEM8(0xFD) +-#define SCPE 0 +-#define SCRC 1 +-#define SCTC 2 +-#define SCWTO 3 +-#define VCARDOK 4 +-#define CARDIN 6 +-#define SCTBE 7 +- +-#define SCCON _SFR_MEM8(0xFE) +-#define CARDVCC 0 +-#define CARDRST 1 +-#define CARDCLK 2 +-#define CARDIO 3 +-#define CARDC4 4 +-#define CARDC8 5 +-#define CLK 7 +- +-#define SCICR _SFR_MEM8(0xFF) +-#define CONV 0 +-#define CREP 1 +-#define WTEN 2 +-#define UART 3 +-#define VCARD0 4 +-#define VCARD1 5 +-#define CARDDET 6 +-#define SCIRESET 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ +-#define INT2_vect_num 3 +-#define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ +-#define INT3_vect_num 4 +-#define INT3_vect _VECTOR(4) /* External Interrupt Request 3 */ +-#define PCINT0_vect_num 5 +-#define PCINT0_vect _VECTOR(5) /* Pin Change Interrupt Request 0 */ +-#define PCINT1_vect_num 6 +-#define PCINT1_vect _VECTOR(6) /* Pin Change Interrupt Request 1 */ +-#define PCINT2_vect_num 7 +-#define PCINT2_vect _VECTOR(7) /* Pin Change Interrupt Request 2 */ +-#define WDT_vect_num 8 +-#define WDT_vect _VECTOR(8) /* Watchdog Time-out Interrupt */ +-#define TIMER2_COMPA_vect_num 9 +-#define TIMER2_COMPA_vect _VECTOR(9) /* Timer/Counter2 Compare Match A */ +-#define TIMER2_COMPB_vect_num 10 +-#define TIMER2_COMPB_vect _VECTOR(10) /* Timer/Counter2 Compare Match B */ +-#define TIMER2_OVF_vect_num 11 +-#define TIMER2_OVF_vect _VECTOR(11) /* Timer/Counter2 Overflow */ +-#define TIMER1_CAPT_vect_num 12 +-#define TIMER1_CAPT_vect _VECTOR(12) /* Timer/Counter1 Capture Event */ +-#define TIMER1_COMPA_vect_num 13 +-#define TIMER1_COMPA_vect _VECTOR(13) /* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPB_vect_num 14 +-#define TIMER1_COMPB_vect _VECTOR(14) /* Timer/Counter1 Compare Match B */ +-#define TIMER1_OVF_vect_num 15 +-#define TIMER1_OVF_vect _VECTOR(15) /* Timer/Counter1 Overflow */ +-#define TIMER0_COMPA_vect_num 16 +-#define TIMER0_COMPA_vect _VECTOR(16) /* Timer/Counter0 Compare Match A */ +-#define TIMER0_COMPB_vect_num 17 +-#define TIMER0_COMPB_vect _VECTOR(17) /* Timer/Counter0 Compare Match B */ +-#define TIMER0_OVF_vect_num 18 +-#define TIMER0_OVF_vect _VECTOR(18) /* Timer/Counter0 Overflow */ +-#define SPI_STC_vect_num 19 +-#define SPI_STC_vect _VECTOR(19) /* SPI Serial Transfer Complete */ +-#define USART0_RX_vect_num 20 +-#define USART0_RX_vect _VECTOR(20) /* USART0, Rx Complete */ +-#define USART0_UDRE_vect_num 21 +-#define USART0_UDRE_vect _VECTOR(21) /* USART0 Data register Empty */ +-#define USART0_TX_vect_num 22 +-#define USART0_TX_vect _VECTOR(22) /* USART0, Tx Complete */ +-#define SUPPLY_MON_vect_num 23 +-#define SUPPLY_MON_vect _VECTOR(23) /* Supply Monitor Interruption */ +-#define RFU_vect_num 24 +-#define RFU_vect _VECTOR(24) /* Reserved for Future Use */ +-#define EE_READY_vect_num 25 +-#define EE_READY_vect _VECTOR(25) /* EEPROM Ready */ +-#define TWI_vect_num 26 +-#define TWI_vect _VECTOR(26) /* 2-wire Serial Interface */ +-#define SPM_READY_vect_num 27 +-#define SPM_READY_vect _VECTOR(27) /* Store Program Memory Read */ +-#define KEYBOARD_vect_num 28 +-#define KEYBOARD_vect _VECTOR(28) /* Keyboard Input Changed */ +-#define AES_Operation_vect_num 29 +-#define AES_Operation_vect _VECTOR(29) /* AES Block Operation Ended */ +-#define HSSPI_vect_num 30 +-#define HSSPI_vect _VECTOR(30) /* High-Speed SPI Interruption */ +-#define USB_Endpoint_vect_num 31 +-#define USB_Endpoint_vect _VECTOR(31) /* USB Endpoint Related Interruption */ +-#define USB_Protocol_vect_num 32 +-#define USB_Protocol_vect _VECTOR(32) /* USB Protocol Related Interruption */ +-#define SCIB_vect_num 33 +-#define SCIB_vect _VECTOR(33) /* Smart Card Reader Interface */ +-#define USBHost_Control_vect_num 34 +-#define USBHost_Control_vect _VECTOR(34) /* USB Host Controller Interrupt */ +-#define USBHost_Pipe_vect_num 35 +-#define USBHost_Pipe_vect _VECTOR(35) /* USB Host Pipe Interrupt */ +-#define CPRES_vect_num 36 +-#define CPRES_vect _VECTOR(36) /* Card Presence Detection */ +-#define PCINT3_vect_num 37 +-#define PCINT3_vect _VECTOR(37) /* Pin Change Interrupt Request 3 */ +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (38 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (256) +-#define RAMSTART (0x100) +-#define RAMSIZE (4096) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (0x0) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x7FF) +-#define E2PAGESIZE (4) +-#define FLASHEND (0xFFFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Clock Selection */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Clock Selection */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ +-#define LFUSE_DEFAULT (FUSE_SUT0) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ +-#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ +-#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODENABLE (unsigned char)~_BV(0) /* Brown-out Detector Enable Signal */ +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x96 +-#define SIGNATURE_2 0xC1 +- +- +-#endif /* _AVR_AT90SCR100_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: io90scr100.h 1910 2009-03-04 17:45:30Z arcanum $ */ ++ ++/* avr/io90scr100.h - definitions for AT90SCR100 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "io90scr100.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_AT90SCR100_H_ ++#define _AVR_AT90SCR100_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++#define PINA4 4 ++#define PINA5 5 ++#define PINA6 6 ++#define PINA7 7 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++#define DDA4 4 ++#define DDA5 5 ++#define DDA6 6 ++#define DDA7 7 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA0 0 ++#define PORTA1 1 ++#define PORTA2 2 ++#define PORTA3 3 ++#define PORTA4 4 ++#define PORTA5 5 ++#define PORTA6 6 ++#define PORTA7 7 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++#define PINC7 7 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++#define DDC7 7 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC3 3 ++#define PORTC4 4 ++#define PORTC5 5 ++#define PORTC6 6 ++#define PORTC7 7 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE0 0 ++#define PINE1 1 ++#define PINE2 2 ++#define PINE3 3 ++#define PINE4 4 ++#define PINE5 5 ++#define PINE6 6 ++#define PINE7 7 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE0 0 ++#define DDE1 1 ++#define DDE2 2 ++#define DDE3 3 ++#define DDE4 4 ++#define DDE5 5 ++#define DDE6 6 ++#define DDE7 7 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE0 0 ++#define PORTE1 1 ++#define PORTE2 2 ++#define PORTE3 3 ++#define PORTE4 4 ++#define PORTE5 5 ++#define PORTE6 6 ++#define PORTE7 7 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++#define EIRR _SFR_IO8(0x1A) ++#define INTD2 2 ++#define INTD3 3 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++#define PCIF3 3 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++#define INT3 3 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++#define EEAR9 1 ++#define EEAR10 2 ++#define EEAR11 3 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define PSRASY 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define OCR0A _SFR_IO8(0x27) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define OCR0B _SFR_IO8(0x28) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCDR7 7 ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define JTRF 4 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++#define JTD 7 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define RAMPZ _SFR_IO8(0x3B) ++#define RAMPZ0 0 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define PLLCR _SFR_MEM8(0x62) ++#define ON 0 ++#define LOCK 1 ++#define PLLMUX 7 ++ ++#define SMONCR _SFR_MEM8(0x63) ++#define SMONEN 0 ++#define SMONIE 1 ++#define SMONIF 4 ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++#define PRR1 _SFR_MEM8(0x65) ++#define PRUSBH 0 ++#define PRUSB 1 ++#define PRHSSPI 2 ++#define PRSCI 3 ++#define PRAES 4 ++#define PRKB 5 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++#define PCIE3 3 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++#define PCMSK3 _SFR_MEM8(0x73) ++ ++#define LEDCR _SFR_MEM8(0x75) ++#define LED00 0 ++#define LED01 1 ++#define LED10 2 ++#define LED11 3 ++#define LED20 4 ++#define LED21 5 ++#define lED30 6 ++#define LED31 7 ++ ++#define AESCR _SFR_MEM8(0x78) ++#define AESGO 0 ++#define ENCRYPT 1 ++#define KS 3 ++#define KEYGN 4 ++#define AUTOKEY 5 ++#define AESIF 6 ++#define AESIE 7 ++ ++#define AESACR _SFR_MEM8(0x79) ++#define KD 0 ++#define AUTOINC 1 ++#define MANINC 2 ++#define XOR 3 ++ ++#define AESADDR _SFR_MEM8(0x7A) ++#define ADDR0 0 ++#define ADDR1 1 ++#define ADDR2 2 ++#define ADDR3 3 ++#define ADDR4 4 ++#define ADDR5 5 ++#define ADDR6 6 ++#define ADDR7 7 ++ ++#define AESDR _SFR_MEM8(0x7B) ++#define DATA0 0 ++#define DATA1 1 ++#define DATA2 2 ++#define DATA3 3 ++#define DATA4 4 ++#define DATA5 5 ++#define DATA6 6 ++#define DATA7 7 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define KBLSR _SFR_MEM8(0x8D) ++#define KBLS0 0 ++#define KBLS1 1 ++#define KBLS2 2 ++#define KBLS3 3 ++#define KBLS4 4 ++#define KBLS5 5 ++#define KBLS6 6 ++#define KBLS7 7 ++ ++#define KBER _SFR_MEM8(0x8E) ++#define KBE0 0 ++#define KBE1 1 ++#define KBE2 2 ++#define KBE3 3 ++#define KBE4 4 ++#define KBE5 5 ++#define KBE6 6 ++#define KBE7 7 ++ ++#define KBFR _SFR_MEM8(0x8F) ++#define KBF0 0 ++#define KBF1 1 ++#define KBF2 2 ++#define KBF3 3 ++#define KBF4 4 ++#define KBF5 5 ++#define KBF6 6 ++#define KBF7 7 ++ ++#define RDWDR _SFR_MEM8(0x90) ++#define RDD0 0 ++#define RDD1 1 ++#define RDD2 2 ++#define RDD3 3 ++#define RDD4 4 ++#define RDD5 5 ++#define RDD6 6 ++#define RDD7 7 ++ ++#define LFSR0 _SFR_MEM8(0x91) ++#define LFSD0 0 ++#define LFSD1 1 ++#define LFSD2 2 ++#define LFSD3 3 ++#define LFSD4 4 ++#define LFSD5 5 ++#define LFSD6 6 ++#define LFSD7 7 ++ ++#define LFSR1 _SFR_MEM8(0x92) ++#define LFSD8 0 ++#define LFSD9 1 ++#define LFSD10 2 ++#define LFSD11 3 ++#define LFSD12 4 ++#define LFSD13 5 ++#define LFSD14 6 ++#define LFSD15 7 ++ ++#define LFSR2 _SFR_MEM8(0x93) ++#define LFSD16 0 ++#define LFSD17 1 ++#define LFSD18 2 ++#define LFSD19 3 ++#define LFSD20 4 ++#define LFSD21 5 ++#define LFSD22 6 ++#define LFSD23 7 ++ ++#define LFSR3 _SFR_MEM8(0x94) ++#define LFSD24 0 ++#define LFSD25 1 ++#define LFSD26 2 ++#define LFSD27 3 ++#define LFSD28 4 ++#define LFSD29 5 ++#define LFSD30 6 ++#define LFSD31 7 ++ ++#define RNGCR _SFR_MEM8(0x95) ++#define ROSCE 0 ++ ++#define UHSR _SFR_MEM8(0x99) ++#define SPEED 3 ++ ++#define UPINT _SFR_MEM8(0x9A) ++#define PINT0 0 ++#define PINT1 1 ++#define PINT2 2 ++#define PINT3 3 ++ ++#define UPBCX _SFR_MEM16(0x9B) ++ ++#define UPBCXL _SFR_MEM8(0x9B) ++#define PBYTCT0 0 ++#define PBYTCT1 1 ++#define PBYTCT2 2 ++#define PBYTCT3 3 ++#define PBYTCT4 4 ++#define PBYTCT5 5 ++#define PBYTCT6 6 ++#define PBYTCT7 7 ++ ++#define UPBCXH _SFR_MEM8(0x9C) ++#define PBYTCT8 0 ++#define PBYTCT9 1 ++#define PBYTCT10 2 ++ ++#define UPERRX _SFR_MEM8(0x9D) ++#define DATATGL 0 ++#define DATAPID 1 ++#define PID 2 ++#define PTIMEOUT 3 ++#define CRC16 4 ++#define COUNTER0 5 ++#define COUNTER1 6 ++ ++#define UHCR _SFR_MEM8(0x9E) ++#define SOFEN 0 ++#define RESET 1 ++#define RESUME 2 ++#define FRZCLK 4 ++#define PAD0 5 ++#define PAD1 6 ++#define UHEN 7 ++ ++#define UHINT _SFR_MEM8(0x9F) ++#define DCONNI 0 ++#define DDISCI 1 ++#define RSTI 2 ++#define RSMEDI 3 ++#define RXRSMI 4 ++#define HSOFI 5 ++#define HWUPI 6 ++ ++#define UHIEN _SFR_MEM8(0xA0) ++#define DCONNE 0 ++#define DDISCE 1 ++#define RSTE 2 ++#define RSMEDE 3 ++#define RXRSME 4 ++#define HSOFE 5 ++#define HWUPE 6 ++ ++#define UHADDR _SFR_MEM8(0xA1) ++#define HADDR0 0 ++#define HADDR1 1 ++#define HADDR2 2 ++#define HADDR3 3 ++#define HADDR4 4 ++#define HADDR5 5 ++#define HADDR6 6 ++ ++#define UHFNUM _SFR_MEM16(0xA2) ++ ++#define UHFNUML _SFR_MEM8(0xA2) ++#define FNUM0 0 ++#define FNUM1 1 ++#define FNUM2 2 ++#define FNUM3 3 ++#define FNUM4 4 ++#define FNUM5 5 ++#define FNUM6 6 ++#define FNUM7 7 ++ ++#define UHFNUMH _SFR_MEM8(0xA3) ++#define FNUM8 0 ++#define FNUM9 1 ++#define FNUM10 2 ++ ++#define UHFLEN _SFR_MEM8(0xA4) ++#define FLEN0 0 ++#define FLEN1 1 ++#define FLEN2 2 ++#define FLEN3 3 ++#define FLEN4 4 ++#define FLEN5 5 ++#define FLEN6 6 ++#define FLEN7 7 ++ ++#define UPINRQX _SFR_MEM8(0xA5) ++#define INRQ0 0 ++#define INRQ1 1 ++#define INRQ2 2 ++#define INRQ3 3 ++#define INRQ4 4 ++#define INRQ5 5 ++#define INRQ6 6 ++#define INRQ7 7 ++ ++#define UPINTX _SFR_MEM8(0xA6) ++#define RXINI 0 ++#define RXSTALLI 1 ++#define TXOUTI 2 ++#define TXSTPI 3 ++#define PERRI 4 ++#define RWAL 5 ++#define NAKEDI 6 ++#define FIFOCON 7 ++ ++#define UPNUM _SFR_MEM8(0xA7) ++#define PNUM0 0 ++#define PNUM1 1 ++ ++#define UPRST _SFR_MEM8(0xA8) ++#define P0RST 0 ++#define P1RST 1 ++#define P2RST 2 ++#define P3RST 3 ++ ++#define UPCRX _SFR_MEM8(0xA9) ++#define PEN 0 ++#define RSTDT 3 ++#define INMODE 5 ++#define PFREEZE 6 ++ ++#define UPCFG0X _SFR_MEM8(0xAA) ++#define PEPNUM0 0 ++#define PEPNUM1 1 ++#define PEPNUM2 2 ++#define PEPNUM3 3 ++#define PTOKEN0 4 ++#define PTOKEN1 5 ++#define PTYPE0 6 ++#define PTYPE1 7 ++ ++#define UPCFG1X _SFR_MEM8(0xAB) ++#define ALLOC 1 ++#define PBK0 2 ++#define PBK1 3 ++#define PSIZE0 4 ++#define PSIZE1 5 ++#define PSIZE2 6 ++ ++#define UPSTAX _SFR_MEM8(0xAC) ++#define NBUSYBK0 0 ++#define NBUSYBK1 1 ++#define DTSEQ0 2 ++#define DTSEQ1 3 ++#define UNDERFI 5 ++#define OVERFI 6 ++#define CFGOK 7 ++ ++#define UPCFG2X _SFR_MEM8(0xAD) ++#define INTFRQ0 0 ++#define INTFRQ1 1 ++#define INTFRQ2 2 ++#define INTFRQ3 3 ++#define INTFRQ4 4 ++#define INTFRQ5 5 ++#define INTFRQ6 6 ++#define INTFRQ7 7 ++ ++#define UPIENX _SFR_MEM8(0xAE) ++#define RXINE 0 ++#define RXSTALLE 1 ++#define TXOUTE 2 ++#define TXSTPE 3 ++#define PERRE 4 ++#define NAKEDE 6 ++#define FLERRE 7 ++ ++#define UPDATX _SFR_MEM8(0xAF) ++#define PDAT0 0 ++#define PDAT1 1 ++#define PDAT2 2 ++#define PDAT3 3 ++#define PDAT4 4 ++#define PDAT5 5 ++#define PDAT6 6 ++#define PDAT7 7 ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++#define TCNT2_0 0 ++#define TCNT2_1 1 ++#define TCNT2_2 2 ++#define TCNT2_3 3 ++#define TCNT2_4 4 ++#define TCNT2_5 5 ++#define TCNT2_6 6 ++#define TCNT2_7 7 ++ ++#define OCR2A _SFR_MEM8(0xB3) ++#define OCR2A0 0 ++#define OCR2A1 1 ++#define OCR2A2 2 ++#define OCR2A3 3 ++#define OCR2A4 4 ++#define OCR2A5 5 ++#define OCR2A6 6 ++#define OCR2A7 7 ++ ++#define OCR2B _SFR_MEM8(0xB4) ++#define OCR2B0 0 ++#define OCR2B1 1 ++#define OCR2B2 2 ++#define OCR2B3 3 ++#define OCR2B4 4 ++#define OCR2B5 5 ++#define OCR2B6 6 ++#define OCR2B7 7 ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++ ++#define TWBR _SFR_MEM8(0xB8) ++#define TWBR0 0 ++#define TWBR1 1 ++#define TWBR2 2 ++#define TWBR3 3 ++#define TWBR4 4 ++#define TWBR5 5 ++#define TWBR6 6 ++#define TWBR7 7 ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++#define TWD0 0 ++#define TWD1 1 ++#define TWD2 2 ++#define TWD3 3 ++#define TWD4 4 ++#define TWD5 5 ++#define TWD6 6 ++#define TWD7 7 ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR00 0 ++#define UBRR01 1 ++#define UBRR02 2 ++#define UBRR03 3 ++#define UBRR04 4 ++#define UBRR05 5 ++#define UBRR06 6 ++#define UBRR07 7 ++ ++#define UBRR0H _SFR_MEM8(0xC5) ++#define UBRR08 0 ++#define UBRR09 1 ++#define UBRR010 2 ++#define UBRR011 3 ++ ++#define UDR0 _SFR_MEM8(0xC6) ++#define UDR00 0 ++#define UDR01 1 ++#define UDR02 2 ++#define UDR03 3 ++#define UDR04 4 ++#define UDR05 5 ++#define UDR06 6 ++#define UDR07 7 ++ ++#define USBENUM _SFR_MEM8(0xCA) ++#define USBENUM0 0 ++#define USBENUM1 1 ++#define USBENUM2 2 ++ ++#define USBCSEX _SFR_MEM8(0xCB) ++#define TXC 0 ++#define RCVD 1 ++#define RXSETUP 2 ++#define STSENT 3 ++#define TXPB 4 ++#define FSTALL 5 ++#define IERR 6 ++ ++#define USBDBCEX _SFR_MEM8(0xCC) ++#define BCT0 0 ++#define BCT1 1 ++#define BCT2 2 ++#define BCT3 3 ++#define BCT4 4 ++#define BCT5 5 ++#define BCT6 6 ++#define BCT7 7 ++ ++#define USBFCEX _SFR_MEM8(0xCD) ++#define EPTYP0 0 ++#define EPTYP1 1 ++#define EPDIR 2 ++#define EPE 7 ++ ++#define HSSPITO _SFR_MEM16(0xD1) ++ ++#define HSSPITOL _SFR_MEM8(0xD1) ++#define HSSPITOD0 0 ++#define HSSPITOD1 1 ++#define HSSPITOD2 2 ++#define HSSPITOD3 3 ++#define HSSPITOD4 4 ++#define HSSPITOD5 5 ++#define HSSPITOD6 6 ++#define HSSPITOD7 7 ++ ++#define HSSPITOH _SFR_MEM8(0xD2) ++#define HSSPITOD8 0 ++#define HSSPITOD9 1 ++#define HSSPITOD10 2 ++#define HSSPITOD11 3 ++#define HSSPITOD12 4 ++#define HSSPITOD13 5 ++#define HSSPITOD14 6 ++#define HSSPITOD15 7 ++ ++#define HSSPICNT _SFR_MEM8(0xD3) ++#define HSSPICNTD0 0 ++#define HSSPICNTD1 1 ++#define HSSPICNTD2 2 ++#define HSSPICNTD3 3 ++#define HSSPICNTD4 4 ++ ++#define HSSPIIER _SFR_MEM8(0xD4) ++#define NSSIE 4 ++#define RCVOFIE 5 ++#define BTDIE 6 ++#define TIMEOUTIE 7 ++ ++#define HSSPIGTR _SFR_MEM8(0xD5) ++#define HSSPIGTD0 0 ++#define HSSPIGTD1 1 ++#define HSSPIGTD2 2 ++#define HSSPIGTD3 3 ++#define HSSPIGTD4 4 ++#define HSSPIGTD5 5 ++#define HSSPIGTD6 6 ++#define HSSPIGTD7 7 ++ ++#define HSSPIRDR _SFR_MEM8(0xD6) ++#define HSSPIRDD0 0 ++#define HSSPIRDD1 1 ++#define HSSPIRDD2 2 ++#define HSSPIRDD3 3 ++#define HSSPIRDD4 4 ++#define HSSPIRDD5 5 ++#define HSSPIRDD6 6 ++#define HSSPIRDD7 7 ++ ++#define HSSPITDR _SFR_MEM8(0xD7) ++#define HSSPITDD0 0 ++#define HSSPITDD1 1 ++#define HSSPITDD2 2 ++#define HSSPITDD3 3 ++#define HSSPITDD4 4 ++#define HSSPITDD5 5 ++#define HSSPITDD6 6 ++#define HSSPITDD7 7 ++ ++#define HSSPISR _SFR_MEM8(0xD8) ++#define SPICKRDY 0 ++#define TXBUFE 1 ++#define RXBUFF 2 ++#define NSS 3 ++#define DPRAMRDY 4 ++ ++#define HSSPICFG _SFR_MEM8(0xD9) ++#define HSSPIEN 0 ++#define HSMSTR 1 ++#define HSCPOL 2 ++#define HSCPHA 3 ++#define DPRAM 4 ++#define SPICKDIV0 5 ++#define SPICKDIV1 6 ++#define SPICKDIV2 7 ++ ++#define HSSPIIR _SFR_MEM8(0xDA) ++#define NSSFE 3 ++#define NSSRE 4 ++#define RCVOF 5 ++#define BTD 6 ++#define TIMEOUT 7 ++ ++#define HSSPICR _SFR_MEM8(0xDB) ++#define CS 0 ++#define RETTO 1 ++#define STTTO 2 ++ ++#define HSSPIDMACS _SFR_MEM8(0xDC) ++#define HSSPIDMAR 0 ++#define HSSPIDMADIR 1 ++#define HSSPIDMAERR 2 ++ ++#define HSSPIDMAD _SFR_MEM16(0xDD) ++ ++#define HSSPIDMADL _SFR_MEM8(0xDD) ++#define HSSPIDMAD0 0 ++#define HSSPIDMAD1 1 ++#define HSSPIDMAD2 2 ++#define HSSPIDMAD3 3 ++#define HSSPIDMAD4 4 ++#define HSSPIDMAD5 5 ++#define HSSPIDMAD6 6 ++#define HSSPIDMAD7 7 ++ ++#define HSSPIDMADH _SFR_MEM8(0xDE) ++#define HSSPIDMAD8 0 ++#define HSSPIDMAD9 1 ++#define HSSPIDMAD10 2 ++#define HSSPIDMAD11 3 ++#define HSSPIDMAD12 4 ++#define HSSPIDMAD13 5 ++ ++#define HSSPIDMAB _SFR_MEM8(0xDF) ++#define HSSPIDMAB0 0 ++#define HSSPIDMAB1 1 ++#define HSSPIDMAB2 2 ++#define HSSPIDMAB3 3 ++#define HSSPIDMAB4 4 ++ ++#define USBCR _SFR_MEM8(0xE0) ++#define USBE 1 ++#define UPUC 5 ++#define URMWU 7 ++ ++#define USBPI _SFR_MEM8(0xE1) ++#define SUSI 0 ++#define RESI 1 ++#define RMWUI 2 ++#define SOFI 3 ++#define FEURI 4 ++ ++#define USBPIM _SFR_MEM8(0xE2) ++#define SUSIM 0 ++#define RESIM 1 ++#define RMWUIM 2 ++#define SOFIM 3 ++ ++#define USBEI _SFR_MEM8(0xE3) ++#define EP0I 0 ++#define EP1I 1 ++#define EP2I 2 ++#define EP3I 3 ++#define EP4I 4 ++#define EP5I 5 ++#define EP6I 6 ++#define EP7I 7 ++ ++#define USBEIM _SFR_MEM8(0xE4) ++#define EP0IM 0 ++#define EP1IM 1 ++#define EP2IM 2 ++#define EP3IM 3 ++#define EP4IM 4 ++#define EP5IM 5 ++#define EP6IM 6 ++#define EP7IM 7 ++ ++#define USBRSTE _SFR_MEM8(0xE5) ++#define RSTE0 0 ++#define RSTE1 1 ++#define RSTE2 2 ++#define RSTE3 3 ++#define RSTE4 4 ++#define RSTE5 5 ++#define RSTE6 6 ++#define RST7 7 ++ ++#define USBGS _SFR_MEM8(0xE6) ++#define FAF 0 ++#define FCF 1 ++#define RMWUE 2 ++#define RSMON 3 ++ ++#define USBFA _SFR_MEM8(0xE7) ++#define FADD0 0 ++#define FADD1 1 ++#define FADD2 2 ++#define FADD3 3 ++#define FADD4 4 ++#define FADD5 5 ++#define FADD6 6 ++ ++#define USBFN _SFR_MEM16(0xE8) ++ ++#define USBFNL _SFR_MEM8(0xE8) ++#define FN0 0 ++#define FN1 1 ++#define FN2 2 ++#define FN3 3 ++#define FN4 4 ++#define FN5 5 ++#define FN6 6 ++#define FN7 7 ++ ++#define USBFNH _SFR_MEM8(0xE9) ++#define FN8 0 ++#define FN9 1 ++#define FN10 2 ++#define FNERR 3 ++#define FNEND 4 ++ ++#define USBDMACS _SFR_MEM8(0xEA) ++#define USBDMAR 0 ++#define USBDMADIR 1 ++#define USBDMAERR 2 ++#define EPS0 4 ++#define EPS1 5 ++#define EPS2 6 ++ ++#define USBDMAD _SFR_MEM16(0xEB) ++ ++#define USBDMADL _SFR_MEM8(0xEB) ++#define USBDMAD0 0 ++#define USBDMAD1 1 ++#define USBDMAD2 2 ++#define USBDMAD3 3 ++#define USBDMAD4 4 ++#define USBDMAD5 5 ++#define USBDMAD6 6 ++#define USBDMAD7 7 ++ ++#define USBDMADH _SFR_MEM8(0xEC) ++#define USBDMAD8 0 ++#define USBDMAD9 1 ++#define USBDMAD10 2 ++#define USBDMAD11 3 ++#define USBDMAD12 4 ++#define USBDMAD13 5 ++ ++#define USBDMAB _SFR_MEM8(0xED) ++#define USBDMAB0 0 ++#define USBDMAB1 1 ++#define USBDMAB2 2 ++#define USBDMAB3 3 ++#define USBDMAB4 4 ++#define USBDMAB5 5 ++#define USBDMAB6 6 ++ ++#define DCCR _SFR_MEM8(0xEF) ++#define DCBUSY 5 ++#define DCRDY 6 ++#define DCON 7 ++ ++#define SCICLK _SFR_MEM8(0xF0) ++#define SCICLK0 0 ++#define SCICLK1 1 ++#define SCICLK2 2 ++#define SCICLK3 3 ++#define SCICLK4 4 ++#define SCICLK5 5 ++ ++#define SCWT0 _SFR_MEM8(0xF1) ++#define WT0 0 ++#define WT1 1 ++#define WT2 2 ++#define WT3 3 ++#define WT4 4 ++#define WT5 5 ++#define WT6 6 ++#define WT7 7 ++ ++#define SCWT1 _SFR_MEM8(0xF2) ++#define WT8 0 ++#define WT9 1 ++#define WT10 2 ++#define WT11 3 ++#define WT12 4 ++#define WT13 5 ++#define WT14 6 ++#define WT15 7 ++ ++#define SCWT2 _SFR_MEM8(0xF3) ++#define WT16 0 ++#define WT17 1 ++#define WT18 2 ++#define WT19 3 ++#define WT20 4 ++#define WT21 5 ++#define WT22 6 ++#define WT23 7 ++ ++#define SCWT3 _SFR_MEM8(0xF4) ++#define WT24 0 ++#define WT25 1 ++#define WT26 2 ++#define WT27 3 ++#define WT28 4 ++#define WT29 5 ++#define WT30 6 ++#define WT31 7 ++ ++#define SCGT _SFR_MEM16(0xF5) ++ ++#define SCGTL _SFR_MEM8(0xF5) ++#define GT0 0 ++#define GT1 1 ++#define GT2 2 ++#define GT3 3 ++#define GT4 4 ++#define GT5 5 ++#define GT6 6 ++#define GT7 7 ++ ++#define SCGTH _SFR_MEM8(0xF6) ++#define GT8 0 ++ ++#define SCETU _SFR_MEM16(0xF7) ++ ++#define SCETUL _SFR_MEM8(0xF7) ++#define ETU0 0 ++#define ETU1 1 ++#define ETU2 2 ++#define ETU3 3 ++#define ETU4 4 ++#define ETU5 5 ++#define ETU6 6 ++#define ETU7 7 ++ ++#define SCETUH _SFR_MEM8(0xF8) ++#define ETU8 0 ++#define ETU9 1 ++#define ETU10 2 ++#define COMP 7 ++ ++#define SCIBUF _SFR_MEM8(0xF9) ++#define SCIBUFD0 0 ++#define SCIBUFD1 1 ++#define SCIBUFD2 2 ++#define SCIBUFD3 3 ++#define SCIBUFD4 4 ++#define SCIBUFD5 5 ++#define SCIBUFD6 6 ++#define SCIBUFD7 7 ++ ++#define SCSR _SFR_MEM8(0xFA) ++#define CPRESRES 3 ++#define CREPSEL 4 ++#define BGTEN 6 ++ ++#define SCIER _SFR_MEM8(0xFB) ++#define ESCPI 0 ++#define ESCRI 1 ++#define ESCTI 2 ++#define ESCWTI 3 ++#define EVCARDER 4 ++#define CARDINE 6 ++#define ESCTBI 7 ++ ++#define SCIIR _SFR_MEM8(0xFC) ++#define SCPI 0 ++#define SCRI 1 ++#define SCTI 2 ++#define SCWTI 3 ++#define VCARDERR 4 ++#define SCTBI 7 ++ ++#define SCISR _SFR_MEM8(0xFD) ++#define SCPE 0 ++#define SCRC 1 ++#define SCTC 2 ++#define SCWTO 3 ++#define VCARDOK 4 ++#define CARDIN 6 ++#define SCTBE 7 ++ ++#define SCCON _SFR_MEM8(0xFE) ++#define CARDVCC 0 ++#define CARDRST 1 ++#define CARDCLK 2 ++#define CARDIO 3 ++#define CARDC4 4 ++#define CARDC8 5 ++#define CLK 7 ++ ++#define SCICR _SFR_MEM8(0xFF) ++#define CONV 0 ++#define CREP 1 ++#define WTEN 2 ++#define UART 3 ++#define VCARD0 4 ++#define VCARD1 5 ++#define CARDDET 6 ++#define SCIRESET 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ ++#define INT2_vect_num 3 ++#define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ ++#define INT3_vect_num 4 ++#define INT3_vect _VECTOR(4) /* External Interrupt Request 3 */ ++#define PCINT0_vect_num 5 ++#define PCINT0_vect _VECTOR(5) /* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect_num 6 ++#define PCINT1_vect _VECTOR(6) /* Pin Change Interrupt Request 1 */ ++#define PCINT2_vect_num 7 ++#define PCINT2_vect _VECTOR(7) /* Pin Change Interrupt Request 2 */ ++#define WDT_vect_num 8 ++#define WDT_vect _VECTOR(8) /* Watchdog Time-out Interrupt */ ++#define TIMER2_COMPA_vect_num 9 ++#define TIMER2_COMPA_vect _VECTOR(9) /* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPB_vect_num 10 ++#define TIMER2_COMPB_vect _VECTOR(10) /* Timer/Counter2 Compare Match B */ ++#define TIMER2_OVF_vect_num 11 ++#define TIMER2_OVF_vect _VECTOR(11) /* Timer/Counter2 Overflow */ ++#define TIMER1_CAPT_vect_num 12 ++#define TIMER1_CAPT_vect _VECTOR(12) /* Timer/Counter1 Capture Event */ ++#define TIMER1_COMPA_vect_num 13 ++#define TIMER1_COMPA_vect _VECTOR(13) /* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPB_vect_num 14 ++#define TIMER1_COMPB_vect _VECTOR(14) /* Timer/Counter1 Compare Match B */ ++#define TIMER1_OVF_vect_num 15 ++#define TIMER1_OVF_vect _VECTOR(15) /* Timer/Counter1 Overflow */ ++#define TIMER0_COMPA_vect_num 16 ++#define TIMER0_COMPA_vect _VECTOR(16) /* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPB_vect_num 17 ++#define TIMER0_COMPB_vect _VECTOR(17) /* Timer/Counter0 Compare Match B */ ++#define TIMER0_OVF_vect_num 18 ++#define TIMER0_OVF_vect _VECTOR(18) /* Timer/Counter0 Overflow */ ++#define SPI_STC_vect_num 19 ++#define SPI_STC_vect _VECTOR(19) /* SPI Serial Transfer Complete */ ++#define USART0_RX_vect_num 20 ++#define USART0_RX_vect _VECTOR(20) /* USART0, Rx Complete */ ++#define USART0_UDRE_vect_num 21 ++#define USART0_UDRE_vect _VECTOR(21) /* USART0 Data register Empty */ ++#define USART0_TX_vect_num 22 ++#define USART0_TX_vect _VECTOR(22) /* USART0, Tx Complete */ ++#define SUPPLY_MON_vect_num 23 ++#define SUPPLY_MON_vect _VECTOR(23) /* Supply Monitor Interruption */ ++#define RFU_vect_num 24 ++#define RFU_vect _VECTOR(24) /* Reserved for Future Use */ ++#define EE_READY_vect_num 25 ++#define EE_READY_vect _VECTOR(25) /* EEPROM Ready */ ++#define TWI_vect_num 26 ++#define TWI_vect _VECTOR(26) /* 2-wire Serial Interface */ ++#define SPM_READY_vect_num 27 ++#define SPM_READY_vect _VECTOR(27) /* Store Program Memory Read */ ++#define KEYBOARD_vect_num 28 ++#define KEYBOARD_vect _VECTOR(28) /* Keyboard Input Changed */ ++#define AES_Operation_vect_num 29 ++#define AES_Operation_vect _VECTOR(29) /* AES Block Operation Ended */ ++#define HSSPI_vect_num 30 ++#define HSSPI_vect _VECTOR(30) /* High-Speed SPI Interruption */ ++#define USB_Endpoint_vect_num 31 ++#define USB_Endpoint_vect _VECTOR(31) /* USB Endpoint Related Interruption */ ++#define USB_Protocol_vect_num 32 ++#define USB_Protocol_vect _VECTOR(32) /* USB Protocol Related Interruption */ ++#define SCIB_vect_num 33 ++#define SCIB_vect _VECTOR(33) /* Smart Card Reader Interface */ ++#define USBHost_Control_vect_num 34 ++#define USBHost_Control_vect _VECTOR(34) /* USB Host Controller Interrupt */ ++#define USBHost_Pipe_vect_num 35 ++#define USBHost_Pipe_vect _VECTOR(35) /* USB Host Pipe Interrupt */ ++#define CPRES_vect_num 36 ++#define CPRES_vect _VECTOR(36) /* Card Presence Detection */ ++#define PCINT3_vect_num 37 ++#define PCINT3_vect _VECTOR(37) /* Pin Change Interrupt Request 3 */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (38 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (256) ++#define RAMSTART (0x100) ++#define RAMSIZE (4096) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (0x0) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x7FF) ++#define E2PAGESIZE (4) ++#define FLASHEND (0xFFFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Clock Selection */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Clock Selection */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ ++#define LFUSE_DEFAULT (FUSE_SUT0) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ ++#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ ++#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODENABLE (unsigned char)~_BV(0) /* Brown-out Detector Enable Signal */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0xC1 ++ ++ ++#endif /* _AVR_AT90SCR100_H_ */ ++ +diff --git a/include/avr/ioa5272.h b/include/avr/ioa5272.h +new file mode 100644 +index 0000000..591fc88 +--- /dev/null ++++ b/include/avr/ioa5272.h +@@ -0,0 +1,745 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATA5272_H_INCLUDED ++#define _AVR_ATA5272_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "ioa5272.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDRA7 7 ++#define DDRA6 6 ++#define DDRA5 5 ++#define DDRA4 4 ++#define DDRA3 3 ++#define DDRA2 2 ++#define DDRA1 1 ++#define DDRA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++/* Reserved [0x06..0x11] */ ++ ++#define PORTCR _SFR_IO8(0x12) ++ ++/* Reserved [0x13..0x14] */ ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++/* Reserved [0x17..0x1A] */ ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR1 0 ++#define PSR0 1 ++#define TSM 7 ++ ++/* Reserved [0x24] */ ++ ++#define TCCR0A _SFR_IO8(0x25) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x26) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define FOC0A 7 ++ ++#define TCNT2 _SFR_IO8(0x27) ++ ++#define OCR0A _SFR_IO8(0x28) ++ ++/* Reserved [0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACIRS 6 ++#define ACD 7 ++ ++#define DWDR _SFR_IO8(0x31) ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define PUD 4 ++#define BODS 5 ++#define BODSE 6 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define RFLB 3 ++#define CTPB 4 ++#define SIGRD 5 ++#define RWWSB 6 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDE 3 ++#define WDCE 4 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define CLKCSR _SFR_MEM8(0x62) ++#define CLKC0 0 ++#define CLKC1 1 ++#define CLKC2 2 ++#define CLKC3 3 ++#define CLKRDY 4 ++#define CLKCCE 7 ++ ++#define CLKSELR _SFR_MEM8(0x63) ++#define CSEL0 0 ++#define CSEL1 1 ++#define CSEL2 2 ++#define CSEL3 3 ++#define CSUT0 4 ++#define CSUT1 5 ++#define COUT 6 ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSI 1 ++#define PRTIM0 2 ++#define PRTIM1 3 ++#define PRSPI 4 ++#define PRLIN 5 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++/* Reserved [0x67] */ ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++/* Reserved [0x6D] */ ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++/* Reserved [0x70..0x76] */ ++ ++#define AMISCR _SFR_MEM8(0x77) ++#define XREFEN 1 ++#define AREFEN 2 ++#define ISRCEN 0 ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define BIN 7 ++#define ACIR0 4 ++#define ACIR1 5 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define ADC8D 0 ++#define ADC9D 1 ++#define ADC10D 2 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCCR1D _SFR_MEM8(0x83) ++#define OC1AU 0 ++#define OC1AV 1 ++#define OC1AW 2 ++#define OC1AX 3 ++#define OC1BU 4 ++#define OC1BV 5 ++#define OC1BW 6 ++#define OC1BX 7 ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR0BUB 0 ++#define TCR0AUB 1 ++#define OCR0AUB 3 ++#define TCN0UB 4 ++#define AS0 5 ++#define EXCLK 6 ++ ++/* Reserved [0xB7] */ ++ ++#define USICR _SFR_MEM8(0xB8) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_MEM8(0xB9) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_MEM8(0xBA) ++ ++#define USIBR _SFR_MEM8(0xBB) ++ ++#define USIPP _SFR_MEM8(0xBC) ++ ++/* Reserved [0xBD..0xC7] */ ++ ++#define LINCR _SFR_MEM8(0xC8) ++#define LCMD0 0 ++#define LCMD1 1 ++#define LCMD2 2 ++#define LENA 3 ++#define LCONF0 4 ++#define LCONF1 5 ++#define LIN13 6 ++#define LSWRES 7 ++ ++#define LINSIR _SFR_MEM8(0xC9) ++#define LRXOK 0 ++#define LTXOK 1 ++#define LIDOK 2 ++#define LERR 3 ++#define LBUSY 4 ++#define LIDST0 5 ++#define LIDST1 6 ++#define LIDST2 7 ++ ++#define LINENIR _SFR_MEM8(0xCA) ++#define LENRXOK 0 ++#define LENTXOK 1 ++#define LENIDOK 2 ++#define LENERR 3 ++ ++#define LINERR _SFR_MEM8(0xCB) ++#define LBERR 0 ++#define LCERR 1 ++#define LPERR 2 ++#define LSERR 3 ++#define LFERR 4 ++#define LOVERR 5 ++#define LTOERR 6 ++#define LABORT 7 ++ ++#define LINBTR _SFR_MEM8(0xCC) ++#define LBT0 0 ++#define LBT1 1 ++#define LBT2 2 ++#define LBT3 3 ++#define LBT4 4 ++#define LBT5 5 ++#define LDISR 7 ++ ++#define LINBRRL _SFR_MEM8(0xCD) ++#define LDIV0 0 ++#define LDIV1 1 ++#define LDIV2 2 ++#define LDIV3 3 ++#define LDIV4 4 ++#define LDIV5 5 ++#define LDIV6 6 ++#define LDIV7 7 ++ ++#define LINBRRH _SFR_MEM8(0xCE) ++#define LDIV8 0 ++#define LDIV9 1 ++#define LDIV10 2 ++#define LDIV11 3 ++ ++#define LINDLR _SFR_MEM8(0xCF) ++#define LRXDL0 0 ++#define LRXDL1 1 ++#define LRXDL2 2 ++#define LRXDL3 3 ++#define LTXDL0 4 ++#define LTXDL1 5 ++#define LTXDL2 6 ++#define LTXDL3 7 ++ ++#define LINIDR _SFR_MEM8(0xD0) ++#define LID0 0 ++#define LID1 1 ++#define LID2 2 ++#define LID3 3 ++#define LID4 4 ++#define LID5 5 ++#define LP0 6 ++#define LP1 7 ++ ++#define LINSEL _SFR_MEM8(0xD1) ++#define LINDX0 0 ++#define LINDX1 1 ++#define LINDX2 2 ++#define LAINC 3 ++ ++#define LINDAT _SFR_MEM8(0xD2) ++#define LDATA0 0 ++#define LDATA1 1 ++#define LDATA2 2 ++#define LDATA3 3 ++#define LDATA4 4 ++#define LDATA5 5 ++#define LDATA6 6 ++#define LDATA7 7 ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(3) ++#define PCINT0_vect_num 3 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(4) ++#define PCINT1_vect_num 4 ++ ++/* Watchdog Time-Out Interrupt */ ++#define WDT_vect _VECTOR(5) ++#define WDT_vect_num 5 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define TIMER1_CAPT_vect_num 6 ++ ++/* Timer/Counter1 Compare Match 1A */ ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define TIMER1_COMPA_vect_num 7 ++ ++/* Timer/Counter1 Compare Match 1B */ ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define TIMER1_COMPB_vect_num 8 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(9) ++#define TIMER1_OVF_vect_num 9 ++ ++/* Timer/Counter0 Compare Match 0A */ ++#define TIMER0_COMPA_vect _VECTOR(10) ++#define TIMER0_COMPA_vect_num 10 ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(11) ++#define TIMER0_OVF_vect_num 11 ++ ++/* LIN Transfer Complete */ ++#define LIN_TC_vect _VECTOR(12) ++#define LIN_TC_vect_num 12 ++ ++/* LIN Error */ ++#define LIN_ERR_vect _VECTOR(13) ++#define LIN_ERR_vect_num 13 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(14) ++#define SPI_STC_vect_num 14 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(15) ++#define ADC_vect_num 15 ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect _VECTOR(16) ++#define EE_RDY_vect_num 16 ++ ++/* USI Overflow */ ++#define USI_OVF_vect _VECTOR(19) ++#define USI_OVF_vect_num 19 ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect _VECTOR(34) ++#define ANA_COMP_vect_num 34 ++ ++/* USI Start */ ++#define USI_START_vect _VECTOR(36) ++#define USI_START_vect_num 36 ++ ++#define _VECTORS_SIZE 74 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 128 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x1FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 512 ++#define RAMEND 0x02FF ++#define E2START 0 ++#define E2SIZE 512 ++#define E2PAGESIZE 4 ++#define E2END 0x01FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x87 ++ ++ ++#endif /* #ifdef _AVR_ATA5272_H_INCLUDED */ ++ +diff --git a/include/avr/ioa5505.h b/include/avr/ioa5505.h +new file mode 100644 +index 0000000..be78ae1 +--- /dev/null ++++ b/include/avr/ioa5505.h +@@ -0,0 +1,745 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATA5505_H_INCLUDED ++#define _AVR_ATA5505_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "ioa5505.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDRA7 7 ++#define DDRA6 6 ++#define DDRA5 5 ++#define DDRA4 4 ++#define DDRA3 3 ++#define DDRA2 2 ++#define DDRA1 1 ++#define DDRA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++/* Reserved [0x06..0x11] */ ++ ++#define PORTCR _SFR_IO8(0x12) ++ ++/* Reserved [0x13..0x14] */ ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++/* Reserved [0x17..0x1A] */ ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR1 0 ++#define PSR0 1 ++#define TSM 7 ++ ++/* Reserved [0x24] */ ++ ++#define TCCR0A _SFR_IO8(0x25) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x26) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define FOC0A 7 ++ ++#define TCNT2 _SFR_IO8(0x27) ++ ++#define OCR0A _SFR_IO8(0x28) ++ ++/* Reserved [0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACIRS 6 ++#define ACD 7 ++ ++#define DWDR _SFR_IO8(0x31) ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define PUD 4 ++#define BODS 5 ++#define BODSE 6 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define RFLB 3 ++#define CTPB 4 ++#define SIGRD 5 ++#define RWWSB 6 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDE 3 ++#define WDCE 4 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define CLKCSR _SFR_MEM8(0x62) ++#define CLKC0 0 ++#define CLKC1 1 ++#define CLKC2 2 ++#define CLKC3 3 ++#define CLKRDY 4 ++#define CLKCCE 7 ++ ++#define CLKSELR _SFR_MEM8(0x63) ++#define CSEL0 0 ++#define CSEL1 1 ++#define CSEL2 2 ++#define CSEL3 3 ++#define CSUT0 4 ++#define CSUT1 5 ++#define COUT 6 ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSI 1 ++#define PRTIM0 2 ++#define PRTIM1 3 ++#define PRSPI 4 ++#define PRLIN 5 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++/* Reserved [0x67] */ ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++/* Reserved [0x6D] */ ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++/* Reserved [0x70..0x76] */ ++ ++#define AMISCR _SFR_MEM8(0x77) ++#define XREFEN 1 ++#define AREFEN 2 ++#define ISRCEN 0 ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define BIN 7 ++#define ACIR0 4 ++#define ACIR1 5 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define ADC8D 0 ++#define ADC9D 1 ++#define ADC10D 2 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCCR1D _SFR_MEM8(0x83) ++#define OC1AU 0 ++#define OC1AV 1 ++#define OC1AW 2 ++#define OC1AX 3 ++#define OC1BU 4 ++#define OC1BV 5 ++#define OC1BW 6 ++#define OC1BX 7 ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR0BUB 0 ++#define TCR0AUB 1 ++#define OCR0AUB 3 ++#define TCN0UB 4 ++#define AS0 5 ++#define EXCLK 6 ++ ++/* Reserved [0xB7] */ ++ ++#define USICR _SFR_MEM8(0xB8) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_MEM8(0xB9) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_MEM8(0xBA) ++ ++#define USIBR _SFR_MEM8(0xBB) ++ ++#define USIPP _SFR_MEM8(0xBC) ++ ++/* Reserved [0xBD..0xC7] */ ++ ++#define LINCR _SFR_MEM8(0xC8) ++#define LCMD0 0 ++#define LCMD1 1 ++#define LCMD2 2 ++#define LENA 3 ++#define LCONF0 4 ++#define LCONF1 5 ++#define LIN13 6 ++#define LSWRES 7 ++ ++#define LINSIR _SFR_MEM8(0xC9) ++#define LRXOK 0 ++#define LTXOK 1 ++#define LIDOK 2 ++#define LERR 3 ++#define LBUSY 4 ++#define LIDST0 5 ++#define LIDST1 6 ++#define LIDST2 7 ++ ++#define LINENIR _SFR_MEM8(0xCA) ++#define LENRXOK 0 ++#define LENTXOK 1 ++#define LENIDOK 2 ++#define LENERR 3 ++ ++#define LINERR _SFR_MEM8(0xCB) ++#define LBERR 0 ++#define LCERR 1 ++#define LPERR 2 ++#define LSERR 3 ++#define LFERR 4 ++#define LOVERR 5 ++#define LTOERR 6 ++#define LABORT 7 ++ ++#define LINBTR _SFR_MEM8(0xCC) ++#define LBT0 0 ++#define LBT1 1 ++#define LBT2 2 ++#define LBT3 3 ++#define LBT4 4 ++#define LBT5 5 ++#define LDISR 7 ++ ++#define LINBRRL _SFR_MEM8(0xCD) ++#define LDIV0 0 ++#define LDIV1 1 ++#define LDIV2 2 ++#define LDIV3 3 ++#define LDIV4 4 ++#define LDIV5 5 ++#define LDIV6 6 ++#define LDIV7 7 ++ ++#define LINBRRH _SFR_MEM8(0xCE) ++#define LDIV8 0 ++#define LDIV9 1 ++#define LDIV10 2 ++#define LDIV11 3 ++ ++#define LINDLR _SFR_MEM8(0xCF) ++#define LRXDL0 0 ++#define LRXDL1 1 ++#define LRXDL2 2 ++#define LRXDL3 3 ++#define LTXDL0 4 ++#define LTXDL1 5 ++#define LTXDL2 6 ++#define LTXDL3 7 ++ ++#define LINIDR _SFR_MEM8(0xD0) ++#define LID0 0 ++#define LID1 1 ++#define LID2 2 ++#define LID3 3 ++#define LID4 4 ++#define LID5 5 ++#define LP0 6 ++#define LP1 7 ++ ++#define LINSEL _SFR_MEM8(0xD1) ++#define LINDX0 0 ++#define LINDX1 1 ++#define LINDX2 2 ++#define LAINC 3 ++ ++#define LINDAT _SFR_MEM8(0xD2) ++#define LDATA0 0 ++#define LDATA1 1 ++#define LDATA2 2 ++#define LDATA3 3 ++#define LDATA4 4 ++#define LDATA5 5 ++#define LDATA6 6 ++#define LDATA7 7 ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(3) ++#define PCINT0_vect_num 3 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(4) ++#define PCINT1_vect_num 4 ++ ++/* Watchdog Time-Out Interrupt */ ++#define WDT_vect _VECTOR(5) ++#define WDT_vect_num 5 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define TIMER1_CAPT_vect_num 6 ++ ++/* Timer/Counter1 Compare Match 1A */ ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define TIMER1_COMPA_vect_num 7 ++ ++/* Timer/Counter1 Compare Match 1B */ ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define TIMER1_COMPB_vect_num 8 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(9) ++#define TIMER1_OVF_vect_num 9 ++ ++/* Timer/Counter0 Compare Match 0A */ ++#define TIMER0_COMPA_vect _VECTOR(10) ++#define TIMER0_COMPA_vect_num 10 ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(11) ++#define TIMER0_OVF_vect_num 11 ++ ++/* LIN Transfer Complete */ ++#define LIN_TC_vect _VECTOR(12) ++#define LIN_TC_vect_num 12 ++ ++/* LIN Error */ ++#define LIN_ERR_vect _VECTOR(13) ++#define LIN_ERR_vect_num 13 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(14) ++#define SPI_STC_vect_num 14 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(15) ++#define ADC_vect_num 15 ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect _VECTOR(16) ++#define EE_RDY_vect_num 16 ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect _VECTOR(17) ++#define ANA_COMP_vect_num 17 ++ ++/* USI Start */ ++#define USI_START_vect _VECTOR(18) ++#define USI_START_vect_num 18 ++ ++/* USI Overflow */ ++#define USI_OVF_vect _VECTOR(19) ++#define USI_OVF_vect_num 19 ++ ++#define _VECTORS_SIZE 80 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 128 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x3FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 512 ++#define RAMEND 0x02FF ++#define E2START 0 ++#define E2SIZE 512 ++#define E2PAGESIZE 4 ++#define E2END 0x01FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x87 ++ ++ ++#endif /* #ifdef _AVR_ATA5505_H_INCLUDED */ ++ +diff --git a/include/avr/ioa5702m322.h b/include/avr/ioa5702m322.h +new file mode 100644 +index 0000000..65733b6 +--- /dev/null ++++ b/include/avr/ioa5702m322.h +@@ -0,0 +1,1903 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATA5702M322_H_INCLUDED ++#define _AVR_ATA5702M322_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "ioa5702m322.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define GPIOR0 _SFR_IO8(0x00) ++ ++#define PRR1 _SFR_IO8(0x01) ++#define PRT1 0 ++#define PRT2 1 ++#define PRT3 2 ++#define PRT4 3 ++#define PRT5 4 ++#define PRLFR 5 ++#define PRCI 6 ++ ++#define PRR2 _SFR_IO8(0x02) ++#define PRSF 2 ++#define PRDF 3 ++#define PRTM 6 ++#define PRSSM 7 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++#define TPCR2 _SFR_IO8(0x0C) ++#define TPMA 0 ++#define TPMOD 1 ++#define TPPSD 2 ++#define TPD 3 ++#define TPNFTO 4 ++#define TPWDLV0 5 ++#define TPWDLV1 6 ++ ++#define TPFR _SFR_IO8(0x0D) ++#define TPF 0 ++#define TPFTF 1 ++#define TPNFTF 2 ++#define TPBERF 3 ++ ++#define MCUCR _SFR_IO8(0x0E) ++#define IVCE 0 ++#define IVSEL 1 ++#define SPIIO 2 ++#define ENPS 3 ++#define PUD 4 ++#define TRCCE 5 ++#define TRCEN 6 ++ ++#define FSCR _SFR_IO8(0x0F) ++#define TXMOD 0 ++#define SFM 1 ++#define TXMS0 2 ++#define TXMS1 3 ++#define PAOER 4 ++#define PAON 7 ++ ++/* Reserved [0x10] */ ++ ++#define T1CR _SFR_IO8(0x11) ++#define T1OTM 0 ++#define T1CTM 1 ++#define T1CRM 2 ++#define T1TOP 4 ++#define T1RES 5 ++#define T1TOS 6 ++#define T1ENA 7 ++ ++#define T2CR _SFR_IO8(0x12) ++#define T2OTM 0 ++#define T2CTM 1 ++#define T2CRM 2 ++#define T2TOP 4 ++#define T2RES 5 ++#define T2TOS 6 ++#define T2ENA 7 ++ ++#define T3CR _SFR_IO8(0x13) ++#define T3OTM 0 ++#define T3CTM 1 ++#define T3CRM 2 ++#define T3CPRM 3 ++#define T3TOP 4 ++#define T3RES 5 ++#define T3TOS 6 ++#define T3ENA 7 ++ ++#define T4CR _SFR_IO8(0x14) ++#define T4OTM 0 ++#define T4CTM 1 ++#define T4CRM 2 ++#define T4CPRM 3 ++#define T4TOP 4 ++#define T4RES 5 ++#define T4TOS 6 ++#define T4ENA 7 ++ ++#define T1IFR _SFR_IO8(0x15) ++#define T1OFF 0 ++#define T1COF 1 ++ ++#define T2IFR _SFR_IO8(0x16) ++#define T2OFF 0 ++#define T2COF 1 ++ ++#define T3IFR _SFR_IO8(0x17) ++#define T3OFF 0 ++#define T3COF 1 ++#define T3ICF 2 ++ ++#define T4IFR _SFR_IO8(0x18) ++#define T4OFF 0 ++#define T4COF 1 ++#define T4ICF 2 ++ ++#define T5IFR _SFR_IO8(0x19) ++#define T5OFF 0 ++#define T5COF 1 ++ ++#define PRR0 _SFR_IO8(0x1A) ++#define PRSPI 0 ++#define PRTXDC 2 ++#define PRCRC 3 ++#define PRVM 4 ++#define PRCO 5 ++#define PRCU 6 ++#define PRTWI 7 ++ ++#define PHFR _SFR_IO8(0x1B) ++#define CRCEF 0 ++#define PHTBLF 1 ++#define PHDFF 2 ++#define PHIDFF 3 ++#define PHID0F 4 ++#define PHID1F 5 ++ ++#define LFFR _SFR_IO8(0x1C) ++#define LFSYDF 0 ++#define LFDEF 1 ++#define LFEOF 2 ++#define LFTOF 3 ++#define LFSD 6 ++#define LFES 7 ++ ++#define AESCR _SFR_IO8(0x1D) ++#define AESWK 0 ++#define AESWD 1 ++#define AESIM 2 ++#define AESD 3 ++#define AESXOR 4 ++#define AESRES 5 ++#define AESLKM 6 ++#define AESE 7 ++ ++#define AESSR _SFR_IO8(0x1E) ++#define AESRF 0 ++#define AESERF 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++#define EEPAGE 6 ++#define NVMBSY 7 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define EEPR _SFR_IO8(0x23) ++#define EEAP0 0 ++#define EEAP1 1 ++#define EEAP2 2 ++#define EEAP3 3 ++ ++#define GPIOR1 _SFR_IO8(0x24) ++ ++#define GPIOR2 _SFR_IO8(0x25) ++ ++#define PCICR _SFR_IO8(0x26) ++#define PCIE0 0 ++#define PCIE1 1 ++ ++#define EIMSK _SFR_IO8(0x27) ++#define INT0 0 ++#define INT1 1 ++ ++#define EIFR _SFR_IO8(0x28) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define CRCDIR _SFR_IO8(0x29) ++ ++#define VMSR _SFR_IO8(0x2A) ++#define VMF 0 ++ ++#define MCUSR _SFR_IO8(0x2B) ++#define PORF 0 ++#define EXTRF 1 ++#define BODRF 2 ++#define WDRF 3 ++#define TPRF 5 ++#define DVCCRF 6 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define RXIF 4 ++#define TXIF 5 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++#define LFCR0 _SFR_IO8(0x2F) ++#define LFCE1 0 ++#define LFCE2 1 ++#define LFCE3 2 ++#define LFBR0 3 ++#define LFBR1 4 ++#define LFMG 5 ++#define LFRRT0 6 ++#define LFRRT1 7 ++ ++#define LFCR1 _SFR_IO8(0x30) ++#define LFFM0 0 ++#define LFFM1 1 ++#define ARMDE 2 ++#define FLLEN 4 ++#define ADTHEN 5 ++#define LFPEEN 6 ++#define LFRE 7 ++ ++#define DWDR _SFR_IO8(0x31) ++ ++#define T0IFR _SFR_IO8(0x32) ++#define T0F 0 ++ ++/* Reserved [0x33..0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SELFPRGEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define SPMIE 7 ++ ++#define SMCR _SFR_IO8(0x38) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define TPSR _SFR_IO8(0x39) ++#define TPA 0 ++#define TPGAP 1 ++#define TPPSW 2 ++#define TPBCOK 3 ++ ++#define LFCR2 _SFR_IO8(0x3A) ++#define LFSEN0 0 ++#define LFSEN1 1 ++#define LFDAMP 2 ++#define LFVC0 5 ++#define LFVC1 6 ++#define LFVC2 7 ++ ++#define LFCR3 _SFR_IO8(0x3B) ++#define LFRCTEN 0 ++#define LFRCPCEN 1 ++#define LFRCPM 2 ++ ++/* Reserved [0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define FSEN _SFR_MEM8(0x60) ++#define SDPU 0 ++#define SDEN 1 ++#define GAEN 2 ++#define PEEN 3 ++#define ASEN 4 ++#define ANTT 5 ++ ++#define FSFCR _SFR_MEM8(0x61) ++#define BTSEL0 0 ++#define BTSEL1 1 ++#define ASDIV0 4 ++#define ASDIV1 5 ++#define ASDIV2 6 ++#define ASDIV3 7 ++ ++/* Combine GACDIVL and GACDIVH */ ++#define GACDIV _SFR_MEM16(0x62) ++ ++#define GACDIVL _SFR_MEM8(0x62) ++#define GACDIVH _SFR_MEM8(0x63) ++ ++#define FFREQ1L _SFR_MEM8(0x64) ++ ++#define FFREQ1M _SFR_MEM8(0x65) ++ ++#define FFREQ1H _SFR_MEM8(0x66) ++ ++#define FFREQ2L _SFR_MEM8(0x67) ++ ++#define FFREQ2M _SFR_MEM8(0x68) ++ ++#define FFREQ2H _SFR_MEM8(0x69) ++ ++/* Reserved [0x6A] */ ++ ++#define EICRA _SFR_MEM8(0x6B) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++#define PCMSK0 _SFR_MEM8(0x6C) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6D) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define WDTCR _SFR_MEM8(0x6E) ++#define WDPS0 0 ++#define WDPS1 1 ++#define WDPS2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define T1CNT _SFR_MEM8(0x6F) ++ ++#define T1COR _SFR_MEM8(0x70) ++ ++#define T1MR _SFR_MEM8(0x71) ++#define T1CS0 0 ++#define T1CS1 1 ++#define T1PS0 2 ++#define T1PS1 3 ++#define T1PS2 4 ++#define T1PS3 5 ++#define T1DC0 6 ++#define T1DC1 7 ++ ++#define T1IMR _SFR_MEM8(0x72) ++#define T1OIM 0 ++#define T1CIM 1 ++ ++#define T2CNT _SFR_MEM8(0x73) ++ ++#define T2COR _SFR_MEM8(0x74) ++ ++#define T2MR _SFR_MEM8(0x75) ++#define T2CS0 0 ++#define T2CS1 1 ++#define T2PS0 2 ++#define T2PS1 3 ++#define T2PS2 4 ++#define T2PS3 5 ++#define T2DC0 6 ++#define T2DC1 7 ++ ++#define T2IMR _SFR_MEM8(0x76) ++#define T2OIM 0 ++#define T2CIM 1 ++ ++/* Combine T3CNTL and T3CNTH */ ++#define T3CNT _SFR_MEM16(0x77) ++ ++#define T3CNTL _SFR_MEM8(0x77) ++#define T3CNTH _SFR_MEM8(0x78) ++ ++/* Combine T3CORL and T3CORH */ ++#define T3COR _SFR_MEM16(0x79) ++ ++#define T3CORL _SFR_MEM8(0x79) ++#define T3CORH _SFR_MEM8(0x7A) ++ ++/* Combine T3ICRL and T3ICRH */ ++#define T3ICR _SFR_MEM16(0x7B) ++ ++#define T3ICRL _SFR_MEM8(0x7B) ++#define T3ICRH _SFR_MEM8(0x7C) ++ ++#define T3MRA _SFR_MEM8(0x7D) ++#define T3CS0 0 ++#define T3CS1 1 ++#define T3PS0 2 ++#define T3PS1 3 ++#define T3PS2 4 ++ ++#define T3MRB _SFR_MEM8(0x7E) ++#define T3SCE 1 ++#define T3CNC 2 ++#define T3CE0 3 ++#define T3CE1 4 ++#define T3ICS0 5 ++#define T3ICS1 6 ++#define T3ICS2 7 ++ ++#define T3IMR _SFR_MEM8(0x7F) ++#define T3OIM 0 ++#define T3CIM 1 ++#define T3CPIM 2 ++ ++/* Combine T4CNTL and T4CNTH */ ++#define T4CNT _SFR_MEM16(0x80) ++ ++#define T4CNTL _SFR_MEM8(0x80) ++#define T4CNTH _SFR_MEM8(0x81) ++ ++/* Combine T4CORL and T4CORH */ ++#define T4COR _SFR_MEM16(0x82) ++ ++#define T4CORL _SFR_MEM8(0x82) ++#define T4CORH _SFR_MEM8(0x83) ++ ++/* Combine T4ICRL and T4ICRH */ ++#define T4ICR _SFR_MEM16(0x84) ++ ++#define T4ICRL _SFR_MEM8(0x84) ++#define T4ICRH _SFR_MEM8(0x85) ++ ++#define T4MRA _SFR_MEM8(0x86) ++#define T4CS0 0 ++#define T4CS1 1 ++#define T4PS0 2 ++#define T4PS1 3 ++#define T4PS2 4 ++ ++#define T4MRB _SFR_MEM8(0x87) ++#define T4SCE 1 ++#define T4CNC 2 ++#define T4CE0 3 ++#define T4CE1 4 ++#define T4ICS0 5 ++#define T4ICS1 6 ++#define T4ICS2 7 ++ ++#define T4IMR _SFR_MEM8(0x88) ++#define T4OIM 0 ++#define T4CIM 1 ++#define T4CPIM 2 ++ ++#define T5TEMP _SFR_MEM8(0x89) ++ ++/* Combine T5OCRL and T5OCRH */ ++#define T5OCR _SFR_MEM16(0x8A) ++ ++#define T5OCRL _SFR_MEM8(0x8A) ++#define T5OCRH _SFR_MEM8(0x8B) ++ ++#define T5CCR _SFR_MEM8(0x8C) ++#define T5CS0 0 ++#define T5CS1 1 ++#define T5CS2 2 ++#define T5CTC 3 ++ ++/* Combine T5CNTL and T5CNTH */ ++#define T5CNT _SFR_MEM16(0x8D) ++ ++#define T5CNTL _SFR_MEM8(0x8D) ++#define T5CNTH _SFR_MEM8(0x8E) ++ ++#define T5IMR _SFR_MEM8(0x8F) ++#define T5OIM 0 ++#define T5CIM 1 ++ ++#define GTCCR _SFR_MEM8(0x90) ++#define PSR10 0 ++#define TSM 7 ++ ++/* Reserved [0x91..0xC2] */ ++ ++#define CLKOD _SFR_MEM8(0xC3) ++ ++#define CLKOCR _SFR_MEM8(0xC4) ++#define CLKOS0 0 ++#define CLKOS1 1 ++#define CLKOEN 2 ++ ++/* Reserved [0xC5] */ ++ ++#define MRCCAL _SFR_MEM8(0xC6) ++ ++#define FRCCAL _SFR_MEM8(0xC7) ++ ++/* Reserved [0xC8] */ ++ ++#define CMSR _SFR_MEM8(0xC9) ++#define ECF 0 ++ ++#define CMOCR _SFR_MEM8(0xCA) ++#define FRCAO 0 ++#define MRCAO 1 ++#define FRCACT 2 ++ ++#define SUPFR _SFR_MEM8(0xCB) ++#define AVCCRF 0 ++#define AVCCLF 1 ++ ++#define SUPCR _SFR_MEM8(0xCC) ++#define AVCCRM 0 ++#define AVCCLM 1 ++#define PVEN 2 ++#define AVDIC 3 ++#define AVEN 4 ++#define DVHEN 5 ++ ++/* Reserved [0xCD..0xD1] */ ++ ++#define DFS _SFR_MEM8(0xD2) ++#define DFFLRF 0 ++#define DFUFL 1 ++#define DFOFL 2 ++ ++/* Combine DFTLL and DFTLH */ ++#define DFTL _SFR_MEM16(0xD3) ++ ++#define DFTLL _SFR_MEM8(0xD3) ++#define DFTLH _SFR_MEM8(0xD4) ++ ++#define DFL _SFR_MEM8(0xD5) ++#define DFFLS0 0 ++#define DFFLS1 1 ++#define DFFLS2 2 ++#define DFFLS3 3 ++#define DFFLS4 4 ++#define DFFLS5 5 ++#define DFCLR 7 ++ ++#define DFWP _SFR_MEM8(0xD6) ++ ++#define DFRP _SFR_MEM8(0xD7) ++ ++#define DFD _SFR_MEM8(0xD8) ++ ++#define DFI _SFR_MEM8(0xD9) ++#define DFFLIM 0 ++#define DFERIM 1 ++ ++#define DFC _SFR_MEM8(0xDA) ++#define DFFLC0 0 ++#define DFFLC1 1 ++#define DFFLC2 2 ++#define DFFLC3 3 ++#define DFFLC4 4 ++#define DFFLC5 5 ++#define DFDRA 7 ++ ++#define SFS _SFR_MEM8(0xDB) ++#define SFFLRF 0 ++#define SFUFL 1 ++#define SFOFL 2 ++ ++#define SFL _SFR_MEM8(0xDC) ++#define SFFLS0 0 ++#define SFFLS1 1 ++#define SFFLS2 2 ++#define SFFLS3 3 ++#define SFFLS4 4 ++#define SFCLR 7 ++ ++#define SFWP _SFR_MEM8(0xDD) ++ ++#define SFRP _SFR_MEM8(0xDE) ++ ++#define SFD _SFR_MEM8(0xDF) ++ ++#define SFI _SFR_MEM8(0xE0) ++#define SFFLIM 0 ++#define SFERIM 1 ++ ++#define SFC _SFR_MEM8(0xE1) ++#define SFFLC0 0 ++#define SFFLC1 1 ++#define SFFLC2 2 ++#define SFFLC3 3 ++#define SFFLC4 4 ++#define SFDRA 7 ++ ++#define SSMCR _SFR_MEM8(0xE2) ++#define SSMTGE 2 ++#define SSMTPE 3 ++#define SSMPVE 4 ++#define SSMTAE 5 ++ ++/* Reserved [0xE3] */ ++ ++#define SSMFBR _SFR_MEM8(0xE4) ++#define SSMPLDT 5 ++ ++#define SSMRR _SFR_MEM8(0xE5) ++#define SSMR 0 ++#define SSMST 1 ++ ++#define SSMSR _SFR_MEM8(0xE6) ++#define SSMESM0 0 ++#define SSMESM1 1 ++#define SSMESM2 2 ++#define SSMESM3 3 ++#define SSMERR 7 ++ ++#define SSMIFR _SFR_MEM8(0xE7) ++#define SSMIF 0 ++ ++#define SSMIMR _SFR_MEM8(0xE8) ++#define SSMIM 0 ++ ++#define MSMSTR _SFR_MEM8(0xE9) ++#define SSMMST0 0 ++#define SSMMST1 1 ++#define SSMMST2 2 ++#define SSMMST3 3 ++#define SSMMST4 4 ++ ++#define SSMSTR _SFR_MEM8(0xEA) ++#define SSMSTA0 0 ++#define SSMSTA1 1 ++#define SSMSTA2 2 ++#define SSMSTA3 3 ++#define SSMSTA4 4 ++#define SSMSTA5 5 ++ ++/* Reserved [0xEB] */ ++ ++#define MSMCR1 _SFR_MEM8(0xEC) ++#define MSMSM00 0 ++#define MSMSM01 1 ++#define MSMSM02 2 ++#define MSMSM03 3 ++#define MSMSM10 4 ++#define MSMSM11 5 ++#define MSMSM12 6 ++#define MSMSM13 7 ++ ++#define MSMCR2 _SFR_MEM8(0xED) ++#define MSMSM20 0 ++#define MSMSM21 1 ++#define MSMSM22 2 ++#define MSMSM23 3 ++#define MSMSM30 4 ++#define MSMSM31 5 ++#define MSMSM32 6 ++#define MSMSM33 7 ++ ++#define MSMCR3 _SFR_MEM8(0xEE) ++#define MSMSM40 0 ++#define MSMSM41 1 ++#define MSMSM42 2 ++#define MSMSM43 3 ++#define MSMSM50 4 ++#define MSMSM51 5 ++#define MSMSM52 6 ++#define MSMSM53 7 ++ ++#define MSMCR4 _SFR_MEM8(0xEF) ++#define MSMSM60 0 ++#define MSMSM61 1 ++#define MSMSM62 2 ++#define MSMSM63 3 ++#define MSMSM70 4 ++#define MSMSM71 5 ++#define MSMSM72 6 ++#define MSMSM73 7 ++ ++/* Reserved [0xF0..0xFB] */ ++ ++/* Combine TRCIDL and TRCIDH */ ++#define TRCID _SFR_MEM16(0xFC) ++ ++#define TRCIDL _SFR_MEM8(0xFC) ++#define TRCIDH _SFR_MEM8(0xFD) ++ ++/* Reserved [0xFE] */ ++ ++#define TRCDR _SFR_MEM8(0xFF) ++ ++#define FESR _SFR_MEM8(0x100) ++#define XRDY 2 ++#define PLCK 3 ++#define ANTS 4 ++ ++#define FEEN1 _SFR_MEM8(0x101) ++#define PLEN 0 ++#define PLCAL 1 ++#define XTOEN 2 ++#define PLSP1 6 ++#define ATEN 7 ++ ++#define FEEN2 _SFR_MEM8(0x102) ++#define PAEN 2 ++#define PLPEN 4 ++#define CPBIA 6 ++ ++/* Reserved [0x103] */ ++ ++#define FEAT _SFR_MEM8(0x104) ++#define ANTN0 0 ++#define ANTN1 1 ++#define ANTN2 2 ++#define ANTN3 3 ++ ++#define FEPAC _SFR_MEM8(0x105) ++#define PACR0 0 ++#define PACR1 1 ++#define PACR2 2 ++#define PACR3 3 ++#define PACR4 4 ++#define PACR5 5 ++#define PACR6 6 ++#define PACR7 7 ++ ++#define FEVCT _SFR_MEM8(0x106) ++ ++#define FEBT _SFR_MEM8(0x107) ++#define CTN20 0 ++#define CTN21 1 ++#define RTN20 2 ++#define RTN21 3 ++ ++#define FEMS _SFR_MEM8(0x108) ++#define PLLS0 0 ++#define PLLS1 1 ++#define PLLS2 2 ++#define PLLS3 3 ++#define PLLM0 4 ++#define PLLM1 5 ++#define PLLM2 6 ++#define PLLM3 7 ++ ++#define FETN4 _SFR_MEM8(0x109) ++#define CTN40 0 ++#define CTN41 1 ++#define CTN42 2 ++#define CTN43 3 ++#define RTN40 4 ++#define RTN41 5 ++#define RTN42 6 ++#define RTN43 7 ++ ++#define FECR _SFR_MEM8(0x10A) ++#define LBNHB 0 ++#define S4N3 1 ++#define PLCKG 4 ++#define ANPS 5 ++ ++#define FEVCO _SFR_MEM8(0x10B) ++#define CPCC0 0 ++#define CPCC1 1 ++#define CPCC2 2 ++#define CPCC3 3 ++#define VCOB0 4 ++#define VCOB1 5 ++#define VCOB2 6 ++#define VCOB3 7 ++ ++#define FEALR _SFR_MEM8(0x10C) ++#define RNGE0 0 ++#define RNGE1 1 ++ ++#define FEANT _SFR_MEM8(0x10D) ++#define LVLC0 0 ++#define LVLC1 1 ++#define LVLC2 2 ++#define LVLC3 3 ++ ++/* Reserved [0x10E..0x11F] */ ++ ++#define TMFSM _SFR_MEM8(0x120) ++#define TMSSM0 0 ++#define TMSSM1 1 ++#define TMSSM2 2 ++#define TMSSM3 3 ++#define TMMSM0 4 ++#define TMMSM1 5 ++#define TMMSM2 6 ++ ++/* Combine TMCRCL and TMCRCH */ ++#define TMCRC _SFR_MEM16(0x121) ++ ++#define TMCRCL _SFR_MEM8(0x121) ++#define TMCRCH _SFR_MEM8(0x122) ++ ++#define TMCSB _SFR_MEM8(0x123) ++ ++/* Combine TMCIL and TMCIH */ ++#define TMCI _SFR_MEM16(0x124) ++ ++#define TMCIL _SFR_MEM8(0x124) ++#define TMCIH _SFR_MEM8(0x125) ++ ++/* Combine TMCPL and TMCPH */ ++#define TMCP _SFR_MEM16(0x126) ++ ++#define TMCPL _SFR_MEM8(0x126) ++#define TMCPH _SFR_MEM8(0x127) ++ ++#define TMSHR _SFR_MEM8(0x128) ++ ++/* Combine TMTLLL and TMTLLH */ ++#define TMTLL _SFR_MEM16(0x129) ++ ++#define TMTLLL _SFR_MEM8(0x129) ++#define TMTLLH _SFR_MEM8(0x12A) ++ ++#define TMSSC _SFR_MEM8(0x12B) ++#define TMSSP0 0 ++#define TMSSP1 1 ++#define TMSSP2 2 ++#define TMSSP3 3 ++#define TMSSL0 4 ++#define TMSSL1 5 ++#define TMSSL2 6 ++#define TMSSH 7 ++ ++#define TMSR _SFR_MEM8(0x12C) ++#define TMTCF 0 ++ ++#define TMCR2 _SFR_MEM8(0x12D) ++#define TMCRCE 0 ++#define TMCRCSE0 1 ++#define TMCRCSE1 2 ++#define TMNRZE 3 ++#define TMPOL 4 ++#define TMSSE 5 ++#define TMLSB 6 ++ ++#define TMCR1 _SFR_MEM8(0x12E) ++#define TMPIS0 0 ++#define TMPIS1 1 ++#define TMPIS2 2 ++#define TMSCS 3 ++#define TMCIM 4 ++ ++/* Reserved [0x12F..0x144] */ ++ ++#define CRCCR _SFR_MEM8(0x145) ++#define CRCRS 0 ++#define REFLI 1 ++#define REFLO 2 ++ ++#define CRCDOR _SFR_MEM8(0x146) ++ ++/* Reserved [0x147..0x150] */ ++ ++#define LFDSRR _SFR_MEM8(0x151) ++#define SRCDT0 0 ++#define SRCDT1 1 ++#define SRCDT2 2 ++#define SRCDT3 3 ++#define SRCDT4 4 ++#define SRCDT5 5 ++#define SRCDT6 6 ++#define SRCDT7 7 ++ ++#define DBCR _SFR_MEM8(0x152) ++#define DBMD 0 ++#define DBCS 1 ++#define DBTMS 2 ++#define DBHA 3 ++ ++#define DBTC _SFR_MEM8(0x153) ++ ++#define DBENB _SFR_MEM8(0x154) ++ ++#define DBENC _SFR_MEM8(0x155) ++ ++#define DBGSW _SFR_MEM8(0x156) ++#define DBGGS0 0 ++#define DBGGS1 1 ++#define DBGGS2 2 ++#define DBGGS3 3 ++#define CPBFOS0 4 ++#define CPBFOS1 5 ++#define CPBF 6 ++#define ATEST 7 ++ ++#define SFFR _SFR_MEM8(0x157) ++#define RFL0 0 ++#define RFL1 1 ++#define RFL2 2 ++#define RFC 3 ++#define TFL0 4 ++#define TFL1 5 ++#define TFL2 6 ++#define TFC 7 ++ ++#define SFIR _SFR_MEM8(0x158) ++#define RIL0 0 ++#define RIL1 1 ++#define RIL2 2 ++#define SRIE 3 ++#define TIL0 4 ++#define TIL1 5 ++#define TIL2 6 ++#define STIE 7 ++ ++#define EECR2 _SFR_MEM8(0x159) ++#define EEBRE 0 ++#define E2CIM 1 ++#define E2FF 6 ++#define E2CF 7 ++ ++/* Reserved [0x15A] */ ++ ++#define EEST _SFR_MEM8(0x15B) ++#define EESYN0 0 ++#define EESYN1 1 ++#define EESYN2 2 ++#define EESYN3 3 ++ ++/* Reserved [0x15C..0x15F] */ ++ ++#define LFRSFR _SFR_MEM8(0x160) ++#define LFRSMF 0 ++#define LFRSTO1 1 ++#define LFRSTO2 2 ++#define LFRSTO3 3 ++ ++#define PCIFR _SFR_MEM8(0x161) ++#define PCIF0 0 ++#define PCIF1 1 ++ ++#define T0CR _SFR_MEM8(0x162) ++#define T0PS0 0 ++#define T0PS1 1 ++#define T0PS2 2 ++#define T0IE 3 ++#define T0PR 4 ++ ++/* Reserved [0x163] */ ++ ++#define DBEND _SFR_MEM8(0x164) ++ ++#define TPCR1 _SFR_MEM8(0x165) ++#define TPQPLM 2 ++#define TPBR 4 ++#define TPDFCP0 5 ++#define TPDFCP1 6 ++#define TPMODE 7 ++ ++#define TPIMR _SFR_MEM8(0x166) ++#define TPIM 0 ++#define TPFTIM 1 ++#define TPNFTIM 2 ++#define TPBERIM 3 ++ ++#define TPDCR1 _SFR_MEM8(0x167) ++#define TPDCL10 0 ++#define TPDCL11 1 ++#define TPDCL12 2 ++#define TPDCL13 3 ++#define TPDCL14 4 ++#define TPDCL15 5 ++ ++#define TPDCR2 _SFR_MEM8(0x168) ++#define TPDCL20 0 ++#define TPDCL21 1 ++#define TPDCL22 2 ++#define TPDCL23 3 ++#define TPDCL24 4 ++#define TPDCL25 5 ++ ++#define TPDCR3 _SFR_MEM8(0x169) ++#define TPDCL30 0 ++#define TPDCL31 1 ++#define TPDCL32 2 ++#define TPDCL33 3 ++#define TPDCL34 4 ++#define TPDCL35 5 ++ ++#define TPDCR4 _SFR_MEM8(0x16A) ++#define TPDCL40 0 ++#define TPDCL41 1 ++#define TPDCL42 2 ++#define TPDCL43 3 ++#define TPDCL44 4 ++#define TPDCL45 5 ++ ++#define TPDCR5 _SFR_MEM8(0x16B) ++#define TPDCL50 0 ++#define TPDCL51 1 ++#define TPDCL52 2 ++#define TPDCL53 3 ++#define TPDCL54 4 ++#define TPDCL55 5 ++ ++#define TPECR1 _SFR_MEM8(0x16C) ++#define TPECL10 0 ++#define TPECL11 1 ++#define TPECL12 2 ++#define TPECL13 3 ++#define TPECL14 4 ++#define TPECL15 5 ++#define TPECL16 6 ++#define TPECL17 7 ++ ++#define TPECR2 _SFR_MEM8(0x16D) ++#define TPECL20 0 ++#define TPECL21 1 ++#define TPECL22 2 ++#define TPECL23 3 ++#define TPECL24 4 ++#define TPECL25 5 ++#define TPECL26 6 ++#define TPECL27 7 ++ ++#define TPECR3 _SFR_MEM8(0x16E) ++#define TPECL30 0 ++#define TPECL31 1 ++#define TPECL32 2 ++#define TPECL33 3 ++#define TPECL34 4 ++#define TPECL35 5 ++#define TPECL36 6 ++#define TPECL37 7 ++ ++#define TPECR4 _SFR_MEM8(0x16F) ++#define TPECL40 0 ++#define TPECL41 1 ++#define TPECL42 2 ++#define TPECL43 3 ++#define TPECL44 4 ++#define TPECL45 5 ++#define TPECL46 6 ++#define TPECL47 7 ++ ++#define TPECMR _SFR_MEM8(0x170) ++#define TPECM10 0 ++#define TPECM11 1 ++#define TPECM20 2 ++#define TPECM21 3 ++#define TPECM30 4 ++#define TPECM31 5 ++#define TPECM40 6 ++#define TPECM41 7 ++ ++#define TPCR3 _SFR_MEM8(0x171) ++#define TPTD 0 ++#define TPRD 1 ++#define TPTLIW 2 ++#define TPRCD 5 ++ ++#define TPCR4 _SFR_MEM8(0x172) ++#define TPBCCS0 0 ++#define TPBCCS1 1 ++#define TPBCCS2 2 ++#define TPBCCS3 3 ++#define TPBCM 4 ++ ++#define TPCR5 _SFR_MEM8(0x173) ++#define TPMUD0 0 ++#define TPMUD1 1 ++#define TPMUD2 2 ++#define TPMD0 4 ++#define TPMD1 5 ++#define TPMD2 6 ++ ++#define LFRSMR _SFR_MEM8(0x174) ++#define LFRSM0 0 ++#define LFRSM1 1 ++#define LFRSM2 2 ++#define LFRSM3 3 ++#define LFRSCM 4 ++#define LFRSFD 5 ++#define LFRSD0 6 ++#define LFRSD1 7 ++ ++/* Reserved [0x175..0x17E] */ ++ ++#define AESDPR _SFR_MEM8(0x17F) ++ ++#define AESKR _SFR_MEM8(0x180) ++ ++#define AESDR _SFR_MEM8(0x181) ++ ++#define GPIOR3 _SFR_MEM8(0x182) ++ ++#define GPIOR4 _SFR_MEM8(0x183) ++ ++#define GPIOR5 _SFR_MEM8(0x184) ++ ++#define GPIOR6 _SFR_MEM8(0x185) ++ ++#define PHBCRR _SFR_MEM8(0x186) ++#define PHBCR0 0 ++#define PHBCR1 1 ++#define PHBCR2 2 ++#define PHBCR3 3 ++#define PHBCR4 4 ++#define PHBCR5 5 ++#define PHBCR6 6 ++#define PHBCR7 7 ++ ++#define LFRSCR _SFR_MEM8(0x187) ++#define LFRSA0 0 ++#define LFRSA1 1 ++#define LFRSA2 2 ++#define LFRSMS 3 ++#define LFRSIM 4 ++#define LFRSRS 5 ++ ++/* Combine LFRSC1L and LFRSC1H */ ++#define LFRSC1 _SFR_MEM16(0x188) ++ ++#define LFRSC1L _SFR_MEM8(0x188) ++#define LFRSC1H _SFR_MEM8(0x189) ++ ++/* Combine LFRSC2L and LFRSC2H */ ++#define LFRSC2 _SFR_MEM16(0x18A) ++ ++#define LFRSC2L _SFR_MEM8(0x18A) ++#define LFRSC2H _SFR_MEM8(0x18B) ++ ++/* Combine LFRSC3L and LFRSC3H */ ++#define LFRSC3 _SFR_MEM16(0x18C) ++ ++#define LFRSC3L _SFR_MEM8(0x18C) ++#define LFRSC3H _SFR_MEM8(0x18D) ++ ++#define LFCPR _SFR_MEM8(0x18E) ++#define LFCALP 0 ++#define LFCALRY 1 ++#define LFCPCE 7 ++ ++#define LFIMR _SFR_MEM8(0x18F) ++#define LFSYDIM 0 ++#define LFDEIM 1 ++#define LFEOIM 2 ++ ++#define PHID00 _SFR_MEM8(0x190) ++#define ID000 0 ++#define ID001 1 ++#define ID002 2 ++#define ID003 3 ++#define ID004 4 ++#define ID005 5 ++#define ID006 6 ++#define ID007 7 ++ ++#define PHID01 _SFR_MEM8(0x191) ++#define ID010 0 ++#define ID011 1 ++#define ID012 2 ++#define ID013 3 ++#define ID014 4 ++#define ID015 5 ++#define ID016 6 ++#define ID017 7 ++ ++#define PHID02 _SFR_MEM8(0x192) ++#define ID020 0 ++#define ID021 1 ++#define ID022 2 ++#define ID023 3 ++#define ID024 4 ++#define ID025 5 ++#define ID026 6 ++#define ID027 7 ++ ++#define PHID03 _SFR_MEM8(0x193) ++#define ID030 0 ++#define ID031 1 ++#define ID032 2 ++#define ID033 3 ++#define ID034 4 ++#define ID035 5 ++#define ID036 6 ++#define ID037 7 ++ ++#define PHID0L _SFR_MEM8(0x194) ++#define ID0FS0 0 ++#define ID0FS1 1 ++#define ID0FS2 2 ++#define ID0FS3 3 ++#define ID0FS4 4 ++#define ID0FS5 5 ++ ++#define PHID10 _SFR_MEM8(0x195) ++#define ID100 0 ++#define ID101 1 ++#define ID102 2 ++#define ID103 3 ++#define ID104 4 ++#define ID105 5 ++#define ID106 6 ++#define ID107 7 ++ ++#define PHID11 _SFR_MEM8(0x196) ++#define ID110 0 ++#define ID111 1 ++#define ID112 2 ++#define ID113 3 ++#define ID114 4 ++#define ID115 5 ++#define ID116 6 ++#define ID117 7 ++ ++#define PHID12 _SFR_MEM8(0x197) ++#define ID120 0 ++#define ID121 1 ++#define ID122 2 ++#define ID123 3 ++#define ID124 4 ++#define ID125 5 ++#define ID126 6 ++#define ID127 7 ++ ++#define PHID13 _SFR_MEM8(0x198) ++#define ID130 0 ++#define ID131 1 ++#define ID132 2 ++#define ID133 3 ++#define ID134 4 ++#define ID135 5 ++#define ID136 6 ++#define ID137 7 ++ ++#define PHID1L _SFR_MEM8(0x199) ++#define ID1FS0 0 ++#define ID1FS1 1 ++#define ID1FS2 2 ++#define ID1FS3 3 ++#define ID1FS4 4 ++#define ID1FS5 5 ++ ++#define PHIDFR _SFR_MEM8(0x19A) ++#define RDFS0 0 ++#define RDFS1 1 ++#define RDFS2 2 ++#define RDFS3 3 ++#define RDFS4 4 ++#define RDFS5 5 ++#define RDFS6 6 ++#define RDFS7 7 ++ ++#define LFSYSY0 _SFR_MEM8(0x19B) ++ ++#define LFSYSY1 _SFR_MEM8(0x19C) ++ ++#define LFSYSY2 _SFR_MEM8(0x19D) ++ ++#define LFSYSY3 _SFR_MEM8(0x19E) ++ ++#define LFSYLE _SFR_MEM8(0x19F) ++ ++#define LFSTOP _SFR_MEM8(0x1A0) ++#define LFSTSY0 0 ++#define LFSTSY1 1 ++#define LFSTSY2 2 ++#define LFSTSY3 3 ++#define LFSTL0 4 ++#define LFSTL1 5 ++#define LFSTL2 6 ++ ++#define PHTCOR _SFR_MEM8(0x1A1) ++ ++#define PHTCMR _SFR_MEM8(0x1A2) ++#define PHPS0 0 ++#define PHPS1 1 ++#define PHPS2 2 ++#define PHCRM 3 ++#define PHCIM 4 ++#define PHRES 5 ++#define PHSM 6 ++#define PHTE 7 ++ ++/* Reserved [0x1A3] */ ++ ++#define PHTBLR _SFR_MEM8(0x1A4) ++#define PHTBL0 0 ++#define PHTBL1 1 ++#define PHTBL2 2 ++#define PHTBL3 3 ++#define PHTBL4 4 ++#define PHTBL5 5 ++#define PHTBL6 6 ++#define PHTBL7 7 ++ ++#define PHDFR _SFR_MEM8(0x1A5) ++#define PHDF0 0 ++#define PHDF1 1 ++#define PHDF2 2 ++#define PHDF3 3 ++#define PHDF4 4 ++#define PHDF5 5 ++#define PHDF6 6 ++#define PHDF7 7 ++ ++#define PHTEMR _SFR_MEM8(0x1A6) ++#define ID0EM 0 ++#define ID1EM 1 ++#define IDFEM 2 ++#define DFEM 3 ++#define TBLEM 4 ++#define FLEM 5 ++#define EOFEM 6 ++#define PHCOF 7 ++ ++#define LFQC3 _SFR_MEM8(0x1A7) ++#define LFQS30 0 ++#define LFQS31 1 ++#define LFQS32 2 ++#define LFQS33 3 ++#define LFCS30 4 ++#define LFCS31 5 ++#define LFCS32 6 ++#define LFCS33 7 ++ ++#define LFQC2 _SFR_MEM8(0x1A8) ++#define LFQS20 0 ++#define LFQS21 1 ++#define LFQS22 2 ++#define LFQS23 3 ++#define LFCS20 4 ++#define LFCS21 5 ++#define LFCS22 6 ++#define LFCS23 7 ++ ++#define LFQC1 _SFR_MEM8(0x1A9) ++#define LFQS10 0 ++#define LFQS11 1 ++#define LFQS12 2 ++#define LFQS13 3 ++#define LFCS10 4 ++#define LFCS11 5 ++#define LFCS12 6 ++#define LFCS13 7 ++ ++/* Reserved [0x1AA..0x1D0] */ ++ ++#define PHFS _SFR_MEM8(0x1D1) ++#define FLRF 0 ++#define FUFL 1 ++#define FOFL 2 ++ ++#define PHFL _SFR_MEM8(0x1D2) ++#define FLS0 0 ++#define FLS1 1 ++#define FLS2 2 ++#define FLS3 3 ++#define FLS4 4 ++#define FLS5 5 ++#define PHCLR 7 ++ ++#define PHFWP _SFR_MEM8(0x1D3) ++#define FWP0 0 ++#define FWP1 1 ++#define FWP2 2 ++#define FWP3 3 ++#define FWP4 4 ++#define FWP5 5 ++ ++#define PHFRP _SFR_MEM8(0x1D4) ++#define FRP0 0 ++#define FRP1 1 ++#define FRP2 2 ++#define FRP3 3 ++#define FRP4 4 ++#define FRP5 5 ++ ++#define PHFD _SFR_MEM8(0x1D5) ++ ++#define PHFI _SFR_MEM8(0x1D6) ++#define FLIM 0 ++#define ERIM 1 ++ ++#define PHFC _SFR_MEM8(0x1D7) ++#define FLC0 0 ++#define FLC1 1 ++#define FLC2 2 ++#define FLC3 3 ++#define FLC4 4 ++#define FLC5 5 ++#define FFMSB 6 ++#define DRA 7 ++ ++#define PHIMR _SFR_MEM8(0x1D8) ++#define PHTBLIM 1 ++#define PHDFIM 2 ++#define PHIDFIM 3 ++#define PHID0IM 4 ++#define PHID1IM 5 ++ ++#define PHCRCR _SFR_MEM8(0x1D9) ++#define CRCFR 2 ++#define CRCMSB 3 ++#define CRCSE0 4 ++#define CRCSE1 5 ++#define STREN 6 ++#define CRCEN 7 ++ ++/* Combine PHCSTL and PHCSTH */ ++#define PHCST _SFR_MEM16(0x1DA) ++ ++#define PHCSTL _SFR_MEM8(0x1DA) ++#define PHCSTH _SFR_MEM8(0x1DB) ++ ++/* Combine PHCRPL and PHCRPH */ ++#define PHCRP _SFR_MEM16(0x1DC) ++ ++#define PHCRPL _SFR_MEM8(0x1DC) ++#define PHCRPH _SFR_MEM8(0x1DD) ++ ++/* Combine PHCSRL and PHCSRH */ ++#define PHCSR _SFR_MEM16(0x1DE) ++ ++#define PHCSRL _SFR_MEM8(0x1DE) ++#define PHCSRH _SFR_MEM8(0x1DF) ++ ++#define PHCKSR _SFR_MEM8(0x1E0) ++#define FIFO_SW 0 ++ ++#define PHCKCR _SFR_MEM8(0x1E1) ++#define FIFSCSW 0 ++#define FRFIFO 5 ++#define CPM 6 ++#define CSM 7 ++ ++/* Reserved [0x1E2] */ ++ ++#define CMCR _SFR_MEM8(0x1E3) ++#define CMM0 0 ++#define CMM1 1 ++#define CMM2 2 ++#define CCS 3 ++#define CMONEN 6 ++#define CMCCE 7 ++ ++#define CMIMR _SFR_MEM8(0x1E4) ++#define ECIE 0 ++ ++#define CLPR _SFR_MEM8(0x1E5) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLTPS0 3 ++#define CLTPS1 4 ++#define CLTPS2 5 ++#define CLPCE 7 ++ ++#define VMCR _SFR_MEM8(0x1E6) ++#define VMLS0 0 ++#define VMLS1 1 ++#define VMLS2 2 ++#define VMLS3 3 ++#define VMIM 4 ++#define VMPS0 5 ++#define VMPS1 6 ++#define VMRS 7 ++ ++/* Reserved [0x1E7..0x1E8] */ ++ ++#define TWBR _SFR_MEM8(0x1E9) ++ ++#define TWCR _SFR_MEM8(0x1EA) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWSR _SFR_MEM8(0x1EB) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS0 3 ++#define TWS1 4 ++#define TWS2 5 ++#define TWS3 6 ++#define TWS4 7 ++ ++#define TWDR _SFR_MEM8(0x1EC) ++ ++#define TWAR _SFR_MEM8(0x1ED) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWAMR _SFR_MEM8(0x1EE) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++#define PDSCR _SFR_MEM8(0x1EF) ++#define PDSC0 0 ++#define PDSC1 1 ++#define PDSC2 2 ++#define PDSC3 3 ++#define PDSC4 4 ++ ++#define TMOCR _SFR_MEM8(0x1F0) ++#define TO1PIS0 0 ++#define TO1PIS1 1 ++#define TO2PIS0 2 ++#define TO2PIS1 3 ++#define TO3PIS0 4 ++#define TO3PIS1 5 ++#define TO4PIS0 6 ++#define TO4PIS1 7 ++ ++#define SRCCAL _SFR_MEM8(0x1F1) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCI0_vect _VECTOR(3) ++#define PCI0_vect_num 3 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCI1_vect _VECTOR(4) ++#define PCI1_vect_num 4 ++ ++/* Voltage Monitoring Interrupt */ ++#define VMON_vect _VECTOR(5) ++#define VMON_vect_num 5 ++ ++/* AVCC Reset Interrupt */ ++#define AVCCR_vect _VECTOR(6) ++#define AVCCR_vect_num 6 ++ ++/* AVCC Low Interrupt */ ++#define AVCCL_vect _VECTOR(7) ++#define AVCCL_vect_num 7 ++ ++/* Timer0 Interval Interrupt */ ++#define T0INT_vect _VECTOR(8) ++#define T0INT_vect_num 8 ++ ++/* Timer/Counter1 Compare Match Interrupt */ ++#define T1COMP_vect _VECTOR(9) ++#define T1COMP_vect_num 9 ++ ++/* Timer/Counter1 Overflow Interrupt */ ++#define T1OVF_vect _VECTOR(10) ++#define T1OVF_vect_num 10 ++ ++/* Timer/Counter2 Compare Match Interrupt */ ++#define T2COMP_vect _VECTOR(11) ++#define T2COMP_vect_num 11 ++ ++/* Timer/Counter2 Overflow Interrupt */ ++#define T2OVF_vect _VECTOR(12) ++#define T2OVF_vect_num 12 ++ ++/* Timer/Counter3 Capture Event Interrupt */ ++#define T3CAP_vect _VECTOR(13) ++#define T3CAP_vect_num 13 ++ ++/* Timer/Counter3 Compare Match Interrupt */ ++#define T3COMP_vect _VECTOR(14) ++#define T3COMP_vect_num 14 ++ ++/* Timer/Counter3 Overflow Interrupt */ ++#define T3OVF_vect _VECTOR(15) ++#define T3OVF_vect_num 15 ++ ++/* Timer/Counter4 Capture Event Interrupt */ ++#define T4CAP_vect _VECTOR(16) ++#define T4CAP_vect_num 16 ++ ++/* Timer/Counter4 Compare Match Interrupt */ ++#define T4COMP_vect _VECTOR(17) ++#define T4COMP_vect_num 17 ++ ++/* Timer/Counter4 Overflow Interrupt */ ++#define T4OVF_vect _VECTOR(18) ++#define T4OVF_vect_num 18 ++ ++/* Timer/Counter5 Compare Match Interrupt */ ++#define T5COMP_vect _VECTOR(19) ++#define T5COMP_vect_num 19 ++ ++/* Timer/Counter5 Overflow Interrupt */ ++#define T5OVF_vect _VECTOR(20) ++#define T5OVF_vect_num 20 ++ ++/* SPI Serial Transfer Complete Interrupt */ ++#define SPI_vect _VECTOR(21) ++#define SPI_vect_num 21 ++ ++/* SPI Rx Buffer Interrupt */ ++#define SRX_FIFO_vect _VECTOR(22) ++#define SRX_FIFO_vect_num 22 ++ ++/* SPI Tx Buffer Interrupt */ ++#define STX_FIFO_vect _VECTOR(23) ++#define STX_FIFO_vect_num 23 ++ ++/* Sequencer State Machine Interrupt */ ++#define SSM_vect _VECTOR(24) ++#define SSM_vect_num 24 ++ ++/* Data FIFO fill level reached Interrupt */ ++#define DFFLR_vect _VECTOR(25) ++#define DFFLR_vect_num 25 ++ ++/* Data FIFO overflow or underflow error Interrupt */ ++#define DFOUE_vect _VECTOR(26) ++#define DFOUE_vect_num 26 ++ ++/* RSSI/Preamble FIFO fill level reached Interrupt */ ++#define SFFLR_vect _VECTOR(27) ++#define SFFLR_vect_num 27 ++ ++/* RSSI/Preamble FIFO overflow or underflow error Interrupt */ ++#define SFOUE_vect _VECTOR(28) ++#define SFOUE_vect_num 28 ++ ++/* Tx Modulator Telegram Finish Interrupt */ ++#define TMTCF_vect _VECTOR(29) ++#define TMTCF_vect_num 29 ++ ++/* AES Krypto Unit Interrupt */ ++#define AES_vect _VECTOR(30) ++#define AES_vect_num 30 ++ ++/* Transponder Mode Interrupt */ ++#define TPINT_vect _VECTOR(31) ++#define TPINT_vect_num 31 ++ ++/* Transponder Timeout Error Interrupt */ ++#define TPTOERR_vect _VECTOR(32) ++#define TPTOERR_vect_num 32 ++ ++/* LF receiver Identifier 0 Interrupt */ ++#define LFID0INT_vect _VECTOR(33) ++#define LFID0INT_vect_num 33 ++ ++/* LF receiver Identifier 1 Interrupt */ ++#define LFID1INT_vect _VECTOR(34) ++#define LFID1INT_vect_num 34 ++ ++/* LF receiver Frame End Interrupt */ ++#define LFFEINT_vect _VECTOR(35) ++#define LFFEINT_vect_num 35 ++ ++/* LF receiver Bit Count Reached Interrupt */ ++#define LFBCR_vect _VECTOR(36) ++#define LFBCR_vect_num 36 ++ ++/* LF receiver PreBurst Detected Interrupt */ ++#define LFPBD_vect _VECTOR(37) ++#define LFPBD_vect_num 37 ++ ++/* LF receiver Decoder Error Interrupt */ ++#define LFDE_vect _VECTOR(38) ++#define LFDE_vect_num 38 ++ ++/* LF receiver End of Telegram Interrupt */ ++#define LFEOT_vect _VECTOR(39) ++#define LFEOT_vect_num 39 ++ ++/* LF receiver Timer Compare Match Interrupt */ ++#define LFTCOR_vect _VECTOR(40) ++#define LFTCOR_vect_num 40 ++ ++/* LF receiver RSSI measurement Interrupt */ ++#define LFRSCO_vect _VECTOR(41) ++#define LFRSCO_vect_num 41 ++ ++/* Protocol Handler FIFO Fill Level Reached Interrupt */ ++#define PHFFLR_vect _VECTOR(42) ++#define PHFFLR_vect_num 42 ++ ++/* Protocol Handler FIFO Overflow or Underflow Error Interrupt */ ++#define PHFOUE_vect _VECTOR(43) ++#define PHFOUE_vect_num 43 ++ ++/* External input Clock monitoring Interrupt */ ++#define EXCM_vect _VECTOR(44) ++#define EXCM_vect_num 44 ++ ++/* EEPROM Error Correction Interrupt */ ++#define E2CINT_vect _VECTOR(45) ++#define E2CINT_vect_num 45 ++ ++/* EEPROM Ready Interrupt */ ++#define ERDY_vect _VECTOR(46) ++#define ERDY_vect_num 46 ++ ++/* Store Program Memory Ready */ ++#define SPMR_vect _VECTOR(47) ++#define SPMR_vect_num 47 ++ ++/* TWI Interrupt */ ++#define TWI_vect _VECTOR(48) ++#define TWI_vect_num 48 ++ ++#define _VECTORS_SIZE 196 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 32 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0xFFFF ++#define RAMSTART 0x0200 ++#define RAMSIZE 1024 ++#define RAMEND 0x05FF ++#define E2START 0 ++#define E2SIZE 2304 ++#define E2PAGESIZE 16 ++#define E2END 0x08FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Fuse Byte */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(128) ++#define FUSE_DWEN (unsigned char)~_BV(64) ++#define FUSE_SPIEN (unsigned char)~_BV(32) ++#define FUSE_WDTON (unsigned char)~_BV(16) ++#define FUSE_EESAVE (unsigned char)~_BV(8) ++#define FUSE_BOOTRST (unsigned char)~_BV(4) ++#define FUSE_EEACC (unsigned char)~_BV(2) ++#define FUSE_EXTCLKEN (unsigned char)~_BV(1) ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x69 ++ ++ ++#endif /* #ifdef _AVR_ATA5702M322_H_INCLUDED */ ++ +diff --git a/include/avr/ioa5781.h b/include/avr/ioa5781.h +new file mode 100644 +index 0000000..2ab7b48 +--- /dev/null ++++ b/include/avr/ioa5781.h +@@ -0,0 +1,1781 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATA5781_H_INCLUDED ++#define _AVR_ATA5781_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "ioa5781.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PRR0 _SFR_IO8(0x01) ++#define PRSPI 0 ++#define PRRXDC 1 ++#define PRTXDC 2 ++#define PRCRC 3 ++#define PRVM 4 ++#define PRCO 5 ++ ++#define PRR1 _SFR_IO8(0x02) ++#define PRT1 0 ++#define PRT2 1 ++#define PRT3 2 ++#define PRT4 3 ++#define PRT5 4 ++ ++#define PRR2 _SFR_IO8(0x03) ++#define PRXB 0 ++#define PRXA 1 ++#define PRSF 2 ++#define PRDF 3 ++#define PRIDS 4 ++#define PRRS 5 ++#define PRTM 6 ++#define PRSSM 7 ++ ++#define RDPR _SFR_IO8(0x04) ++#define PRPTB 0 ++#define PRPTA 1 ++#define PRFLT 2 ++#define PRTMP 3 ++#define APRPTB 4 ++#define APRPTA 5 ++#define ARDPRF 6 ++#define RDPRF 7 ++ ++#define PINB _SFR_IO8(0x05) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x06) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x07) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x08) ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x09) ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x0A) ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++/* Reserved [0x0B..0x0C] */ ++ ++#define RDSIFR _SFR_IO8(0x0D) ++#define NBITA 0 ++#define NBITB 1 ++#define EOTA 2 ++#define EOTB 3 ++#define SOTA 4 ++#define SOTB 5 ++#define WCOA 6 ++#define WCOB 7 ++ ++#define MCUCR _SFR_IO8(0x0E) ++#define IVCE 0 ++#define IVSEL 1 ++#define SPIIO 2 ++#define ENPS 3 ++#define PUD 4 ++#define PB4HS 5 ++#define PB7LS 6 ++#define PB7HS 7 ++ ++#define PCIFR _SFR_IO8(0x0F) ++#define PCIF0 0 ++#define PCIF1 1 ++ ++#define T0CR _SFR_IO8(0x10) ++#define T0PS0 0 ++#define T0PS1 1 ++#define T0PS2 2 ++#define T0IE 3 ++#define T0PR 4 ++ ++#define T1CR _SFR_IO8(0x11) ++#define T1OTM 0 ++#define T1CTM 1 ++#define T1CRM 2 ++#define T1TOP 4 ++#define T1RES 5 ++#define T1TOS 6 ++#define T1ENA 7 ++ ++#define T2CR _SFR_IO8(0x12) ++#define T2OTM 0 ++#define T2CTM 1 ++#define T2CRM 2 ++#define T2TOP 4 ++#define T2RES 5 ++#define T2TOS 6 ++#define T2ENA 7 ++ ++#define T3CR _SFR_IO8(0x13) ++#define T3OTM 0 ++#define T3CTM 1 ++#define T3CRM 2 ++#define T3CPRM 3 ++#define T3TOP 4 ++#define T3RES 5 ++#define T3TOS 6 ++#define T3ENA 7 ++ ++#define T4CR _SFR_IO8(0x14) ++#define T4OTM 0 ++#define T4CTM 1 ++#define T4CRM 2 ++#define T4CPRM 3 ++#define T4TOP 4 ++#define T4RES 5 ++#define T4TOS 6 ++#define T4ENA 7 ++ ++#define T1IFR _SFR_IO8(0x15) ++#define T1OFF 0 ++#define T1COF 1 ++ ++#define T2IFR _SFR_IO8(0x16) ++#define T2OFF 0 ++#define T2COF 1 ++ ++#define T3IFR _SFR_IO8(0x17) ++#define T3OFF 0 ++#define T3COF 1 ++#define T3ICF 2 ++ ++#define T4IFR _SFR_IO8(0x18) ++#define T4OFF 0 ++#define T4COF 1 ++#define T4ICF 2 ++ ++#define T5IFR _SFR_IO8(0x19) ++#define T5OFF 0 ++#define T5COF 1 ++ ++#define GPIOR0 _SFR_IO8(0x1A) ++ ++#define GPIOR3 _SFR_IO8(0x1B) ++ ++#define GPIOR4 _SFR_IO8(0x1C) ++ ++#define GPIOR5 _SFR_IO8(0x1D) ++ ++#define GPIOR6 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++#define EEPAGE 6 ++#define NVMBSY 7 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define EEPR _SFR_IO8(0x23) ++#define EEAP0 0 ++#define EEAP1 1 ++#define EEAP2 2 ++#define EEAP3 3 ++ ++#define GPIOR1 _SFR_IO8(0x24) ++ ++#define GPIOR2 _SFR_IO8(0x25) ++ ++#define PCICR _SFR_IO8(0x26) ++#define PCIE0 0 ++#define PCIE1 1 ++ ++#define EIMSK _SFR_IO8(0x27) ++#define INT0 0 ++#define INT1 1 ++ ++#define EIFR _SFR_IO8(0x28) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define CRCDIR _SFR_IO8(0x29) ++ ++#define VMCSR _SFR_IO8(0x2A) ++#define VMLS0 0 ++#define VMLS1 1 ++#define VMLS2 2 ++#define VMLS3 3 ++#define VMIM 4 ++#define VMF 5 ++ ++#define MCUSR _SFR_IO8(0x2B) ++#define PORF 0 ++#define EXTRF 1 ++#define WDRF 3 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define RXIF 4 ++#define TXIF 5 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++#define T0IFR _SFR_IO8(0x2F) ++#define T0F 0 ++ ++/* Reserved [0x30] */ ++ ++#define DWDR _SFR_IO8(0x31) ++ ++/* Reserved [0x32] */ ++ ++#define RDCR _SFR_IO8(0x33) ++#define RDPU 0 ++#define ADIVEN 1 ++#define RDEN 2 ++ ++#define EOTSA _SFR_IO8(0x34) ++#define CARFA 0 ++#define AMPFA 1 ++#define SYTFA 2 ++#define MANFA 3 ++#define TMOFA 4 ++#define TELRA 5 ++#define RRFA 6 ++#define EOTBF 7 ++ ++#define EOTCA _SFR_IO8(0x35) ++#define CARFEA 0 ++#define AMPFEA 1 ++#define SYTFEA 2 ++#define MANFEA 3 ++#define TMOFEA 4 ++#define TELREA 5 ++#define RRFEA 6 ++#define EOTBFE 7 ++ ++#define EOTSB _SFR_IO8(0x36) ++#define CARFB 0 ++#define AMPFB 1 ++#define SYTFB 2 ++#define MANFB 3 ++#define TMOFB 4 ++#define TELRB 5 ++#define RRFB 6 ++#define EOTAF 7 ++ ++#define EOTCB _SFR_IO8(0x37) ++#define CARFEB 0 ++#define AMPFEB 1 ++#define SYTFEB 2 ++#define MANFEB 3 ++#define TMOFEB 4 ++#define TELREB 5 ++#define RRFEB 6 ++#define EOTAFE 7 ++ ++#define SMCR _SFR_IO8(0x38) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define CMCR _SFR_IO8(0x39) ++#define CMM0 0 ++#define CMM1 1 ++#define CMM2 2 ++#define CCS 3 ++#define SRCD 4 ++#define CMONEN 6 ++#define CMCCE 7 ++ ++#define CMIMR _SFR_IO8(0x3A) ++#define ECIE 0 ++ ++#define CLPR _SFR_IO8(0x3B) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLTPS0 3 ++#define CLTPS1 4 ++#define CLTPS2 5 ++#define CLPCE 7 ++ ++#define SPMCSR _SFR_IO8(0x3C) ++#define SELFPRGEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define SPMIE 7 ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define FSEN _SFR_MEM8(0x60) ++#define SDPU 0 ++#define SDEN 1 ++ ++/* Reserved [0x61..0x63] */ ++ ++#define FFREQ1L _SFR_MEM8(0x64) ++ ++#define FFREQ1M _SFR_MEM8(0x65) ++ ++#define FFREQ1H _SFR_MEM8(0x66) ++ ++#define FFREQ2L _SFR_MEM8(0x67) ++ ++#define FFREQ2M _SFR_MEM8(0x68) ++ ++#define FFREQ2H _SFR_MEM8(0x69) ++ ++/* Reserved [0x6A] */ ++ ++#define EICRA _SFR_MEM8(0x6B) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++#define PCMSK0 _SFR_MEM8(0x6C) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6D) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++ ++#define WDTCR _SFR_MEM8(0x6E) ++#define WDPS0 0 ++#define WDPS1 1 ++#define WDPS2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define T1CNT _SFR_MEM8(0x6F) ++ ++#define T1COR _SFR_MEM8(0x70) ++ ++#define T1MR _SFR_MEM8(0x71) ++#define T1CS0 0 ++#define T1CS1 1 ++#define T1PS0 2 ++#define T1PS1 3 ++#define T1PS2 4 ++#define T1PS3 5 ++#define T1DC0 6 ++#define T1DC1 7 ++ ++#define T1IMR _SFR_MEM8(0x72) ++#define T1OIM 0 ++#define T1CIM 1 ++ ++#define T2CNT _SFR_MEM8(0x73) ++ ++#define T2COR _SFR_MEM8(0x74) ++ ++#define T2MR _SFR_MEM8(0x75) ++#define T2CS0 0 ++#define T2CS1 1 ++#define T2PS0 2 ++#define T2PS1 3 ++#define T2PS2 4 ++#define T2PS3 5 ++#define T2DC0 6 ++#define T2DC1 7 ++ ++#define T2IMR _SFR_MEM8(0x76) ++#define T2OIM 0 ++#define T2CIM 1 ++ ++/* Combine T3CNTL and T3CNTH */ ++#define T3CNT _SFR_MEM16(0x77) ++ ++#define T3CNTL _SFR_MEM8(0x77) ++#define T3CNTH _SFR_MEM8(0x78) ++ ++/* Combine T3CORL and T3CORH */ ++#define T3COR _SFR_MEM16(0x79) ++ ++#define T3CORL _SFR_MEM8(0x79) ++#define T3CORH _SFR_MEM8(0x7A) ++ ++/* Combine T3ICRL and T3ICRH */ ++#define T3ICR _SFR_MEM16(0x7B) ++ ++#define T3ICRL _SFR_MEM8(0x7B) ++#define T3ICRH _SFR_MEM8(0x7C) ++ ++#define T3MRA _SFR_MEM8(0x7D) ++#define T3CS0 0 ++#define T3CS1 1 ++#define T3PS0 2 ++#define T3PS1 3 ++#define T3PS2 4 ++ ++#define T3MRB _SFR_MEM8(0x7E) ++#define T3SCE 1 ++#define T3CNC 2 ++#define T3CE0 3 ++#define T3CE1 4 ++#define T3ICS0 5 ++#define T3ICS1 6 ++#define T3ICS2 7 ++ ++#define T3IMR _SFR_MEM8(0x7F) ++#define T3OIM 0 ++#define T3CIM 1 ++#define T3CPIM 2 ++ ++/* Combine T4CNTL and T4CNTH */ ++#define T4CNT _SFR_MEM16(0x80) ++ ++#define T4CNTL _SFR_MEM8(0x80) ++#define T4CNTH _SFR_MEM8(0x81) ++ ++/* Combine T4CORL and T4CORH */ ++#define T4COR _SFR_MEM16(0x82) ++ ++#define T4CORL _SFR_MEM8(0x82) ++#define T4CORH _SFR_MEM8(0x83) ++ ++/* Combine T4ICRL and T4ICRH */ ++#define T4ICR _SFR_MEM16(0x84) ++ ++#define T4ICRL _SFR_MEM8(0x84) ++#define T4ICRH _SFR_MEM8(0x85) ++ ++#define T4MRA _SFR_MEM8(0x86) ++#define T4CS0 0 ++#define T4CS1 1 ++#define T4PS0 2 ++#define T4PS1 3 ++#define T4PS2 4 ++ ++#define T4MRB _SFR_MEM8(0x87) ++#define T4SCE 1 ++#define T4CNC 2 ++#define T4CE0 3 ++#define T4CE1 4 ++#define T4ICS0 5 ++#define T4ICS1 6 ++#define T4ICS2 7 ++ ++#define T4IMR _SFR_MEM8(0x88) ++#define T4OIM 0 ++#define T4CIM 1 ++#define T4CPIM 2 ++ ++/* Reserved [0x89] */ ++ ++/* Combine T5OCRL and T5OCRH */ ++#define T5OCR _SFR_MEM16(0x8A) ++ ++#define T5OCRL _SFR_MEM8(0x8A) ++#define T5OCRH _SFR_MEM8(0x8B) ++ ++#define T5CCR _SFR_MEM8(0x8C) ++#define T5CS0 0 ++#define T5CS1 1 ++#define T5CS2 2 ++#define T5CTC 3 ++ ++/* Combine T5CNTL and T5CNTH */ ++#define T5CNT _SFR_MEM16(0x8D) ++ ++#define T5CNTL _SFR_MEM8(0x8D) ++#define T5CNTH _SFR_MEM8(0x8E) ++ ++#define T5IMR _SFR_MEM8(0x8F) ++#define T5OIM 0 ++#define T5CIM 1 ++ ++#define GTCCR _SFR_MEM8(0x90) ++#define PSR10 0 ++#define TSM 7 ++ ++#define SOTSB _SFR_MEM8(0x91) ++#define CAROB 0 ++#define AMPOB 1 ++#define SYTOB 2 ++#define MANOB 3 ++#define WUPOB 4 ++#define SFIDOB 5 ++#define RROB 6 ++#define WCOAO 7 ++ ++#define SOTSA _SFR_MEM8(0x92) ++#define CAROA 0 ++#define AMPOA 1 ++#define SYTOA 2 ++#define MANOA 3 ++#define WUPOA 4 ++#define SFIDOA 5 ++#define RROA 6 ++#define WCOBO 7 ++ ++#define SOTCB _SFR_MEM8(0x93) ++#define CAROEB 0 ++#define AMPOEB 1 ++#define SYTOEB 2 ++#define MANOEB 3 ++#define WUPEB 4 ++#define SFIDEB 5 ++#define RROEB 6 ++#define WCOAOE 7 ++ ++#define SOTCA _SFR_MEM8(0x94) ++#define CAROEA 0 ++#define AMPOEA 1 ++#define SYTOEA 2 ++#define MANOEA 3 ++#define WUPEA 4 ++#define SFIDEA 5 ++#define RROEA 6 ++#define WCOBOE 7 ++ ++#define TESRB _SFR_MEM8(0x95) ++#define CRCOB 0 ++#define EOTLB0 1 ++#define EOTLB1 2 ++ ++#define TESRA _SFR_MEM8(0x96) ++#define CRCOA 0 ++#define EOTLA0 1 ++#define EOTLA1 2 ++ ++/* Reserved [0x97] */ ++ ++#define RDSIMR _SFR_MEM8(0x98) ++#define NBITAM 0 ++#define NBITBM 1 ++#define EOTAM 2 ++#define EOTBM 3 ++#define SOTAM 4 ++#define SOTBM 5 ++#define WCOAM 6 ++#define WCOBM 7 ++ ++#define RDOCR _SFR_MEM8(0x99) ++#define TMDS0 1 ++#define TMDS1 2 ++#define ETRPA 3 ++#define ETRPB 4 ++#define RDSIDA 5 ++#define RDSIDB 6 ++ ++/* Reserved [0x9A] */ ++ ++#define TEMPL _SFR_MEM8(0x9B) ++ ++#define TEMPH _SFR_MEM8(0x9C) ++ ++#define SYCB _SFR_MEM8(0x9D) ++#define SYCSB0 0 ++#define SYCSB1 1 ++#define SYCSB2 2 ++#define SYCSB3 3 ++#define SYTLB0 4 ++#define SYTLB1 5 ++#define SYTLB2 6 ++#define SYTLB3 7 ++ ++#define SYCA _SFR_MEM8(0x9E) ++#define SYCSA0 0 ++#define SYCSA1 1 ++#define SYCSA2 2 ++#define SYCSA3 3 ++#define SYTLA0 4 ++#define SYTLA1 5 ++#define SYTLA2 6 ++#define SYTLA3 7 ++ ++#define RXFOB _SFR_MEM8(0x9F) ++ ++#define RXFOA _SFR_MEM8(0xA0) ++ ++#define DMMB _SFR_MEM8(0xA1) ++#define DMATB0 0 ++#define DMATB1 1 ++#define DMATB2 2 ++#define DMATB3 3 ++#define DMATB4 4 ++#define DMPB 5 ++#define DMHB 6 ++#define DMNEB 7 ++ ++#define DMMA _SFR_MEM8(0xA2) ++#define DMATA0 0 ++#define DMATA1 1 ++#define DMATA2 2 ++#define DMATA3 3 ++#define DMATA4 4 ++#define DMPA 5 ++#define DMHA 6 ++#define DMNEA 7 ++ ++#define DMCDB _SFR_MEM8(0xA3) ++#define DMCLB0 0 ++#define DMCLB1 1 ++#define DMCLB2 2 ++#define DMCLB3 3 ++#define DMCLB4 4 ++#define DMCTB0 5 ++#define DMCTB1 6 ++#define DMCTB2 7 ++ ++#define DMCDA _SFR_MEM8(0xA4) ++#define DMCLA0 0 ++#define DMCLA1 1 ++#define DMCLA2 2 ++#define DMCLA3 3 ++#define DMCLA4 4 ++#define DMCTA0 5 ++#define DMCTA1 6 ++#define DMCTA2 7 ++ ++#define DMCRB _SFR_MEM8(0xA5) ++#define DMPGB0 0 ++#define DMPGB1 1 ++#define DMPGB2 2 ++#define DMPGB3 3 ++#define DMPGB4 4 ++#define SASKB 5 ++#define SY1TB 6 ++#define DMARB 7 ++ ++#define DMCRA _SFR_MEM8(0xA6) ++#define DMPGA0 0 ++#define DMPGA1 1 ++#define DMPGA2 2 ++#define DMPGA3 3 ++#define DMPGA4 4 ++#define SASKA 5 ++#define SY1TA 6 ++#define DMARA 7 ++ ++#define DMDRB _SFR_MEM8(0xA7) ++#define DMAB0 0 ++#define DMAB1 1 ++#define DMAB2 2 ++#define DMAB3 3 ++#define DMDNB0 4 ++#define DMDNB1 5 ++#define DMDNB2 6 ++#define DMDNB3 7 ++ ++#define DMDRA _SFR_MEM8(0xA8) ++#define DMAA0 0 ++#define DMAA1 1 ++#define DMAA2 2 ++#define DMAA3 3 ++#define DMDNA0 4 ++#define DMDNA1 5 ++#define DMDNA2 6 ++#define DMDNA3 7 ++ ++#define CHCR _SFR_MEM8(0xA9) ++#define BWM0 0 ++#define BWM1 1 ++#define BWM2 2 ++#define BWM3 3 ++ ++#define CHDN _SFR_MEM8(0xAA) ++#define BBDN0 0 ++#define BBDN1 1 ++#define BBDN2 2 ++#define BBDN3 3 ++#define BBDN4 4 ++#define ADCDN 5 ++ ++#define SFIDCB _SFR_MEM8(0xAB) ++#define SFIDTB0 0 ++#define SFIDTB1 1 ++#define SFIDTB2 2 ++#define SFIDTB3 3 ++#define SFIDTB4 4 ++#define SEMEB 7 ++ ++#define SFIDLB _SFR_MEM8(0xAC) ++#define SFIDLB0 0 ++#define SFIDLB1 1 ++#define SFIDLB2 2 ++#define SFIDLB3 3 ++#define SFIDLB4 4 ++#define SFIDLB5 5 ++ ++#define WUPTB _SFR_MEM8(0xAD) ++#define WUPTB0 0 ++#define WUPTB1 1 ++#define WUPTB2 2 ++#define WUPTB3 3 ++#define WUPTB4 4 ++ ++#define WUPLB _SFR_MEM8(0xAE) ++#define WUPLB0 0 ++#define WUPLB1 1 ++#define WUPLB2 2 ++#define WUPLB3 3 ++#define WUPLB4 4 ++#define WUPLB5 5 ++ ++#define SFID1B _SFR_MEM8(0xAF) ++ ++#define SFID2B _SFR_MEM8(0xB0) ++ ++#define SFID3B _SFR_MEM8(0xB1) ++ ++#define SFID4B _SFR_MEM8(0xB2) ++ ++#define WUP1B _SFR_MEM8(0xB3) ++ ++#define WUP2B _SFR_MEM8(0xB4) ++ ++#define WUP3B _SFR_MEM8(0xB5) ++ ++#define WUP4B _SFR_MEM8(0xB6) ++ ++#define SFIDCA _SFR_MEM8(0xB7) ++#define SFIDTA0 0 ++#define SFIDTA1 1 ++#define SFIDTA2 2 ++#define SFIDTA3 3 ++#define SFIDTA4 4 ++#define SEMEA 7 ++ ++#define SFIDLA _SFR_MEM8(0xB8) ++#define SFIDLA0 0 ++#define SFIDLA1 1 ++#define SFIDLA2 2 ++#define SFIDLA3 3 ++#define SFIDLA4 4 ++#define SFIDLA5 5 ++ ++#define WUPTA _SFR_MEM8(0xB9) ++#define WUPTA0 0 ++#define WUPTA1 1 ++#define WUPTA2 2 ++#define WUPTA3 3 ++#define WUPTA4 4 ++ ++#define WUPLA _SFR_MEM8(0xBA) ++#define WUPLA0 0 ++#define WUPLA1 1 ++#define WUPLA2 2 ++#define WUPLA3 3 ++#define WUPLA4 4 ++#define WUPLA5 5 ++ ++#define SFID1A _SFR_MEM8(0xBB) ++ ++#define SFID2A _SFR_MEM8(0xBC) ++ ++#define SFID3A _SFR_MEM8(0xBD) ++ ++#define SFID4A _SFR_MEM8(0xBE) ++ ++#define WUP1A _SFR_MEM8(0xBF) ++ ++#define WUP2A _SFR_MEM8(0xC0) ++ ++#define WUP3A _SFR_MEM8(0xC1) ++ ++#define WUP4A _SFR_MEM8(0xC2) ++ ++#define CLKOD _SFR_MEM8(0xC3) ++ ++#define CLKOCR _SFR_MEM8(0xC4) ++#define CLKOS0 0 ++#define CLKOS1 1 ++#define CLKOEN 2 ++ ++#define XFUSE _SFR_MEM8(0xC5) ++ ++#define SRCCAL _SFR_MEM8(0xC6) ++#define SRCCAL0 0 ++#define SRCCAL1 1 ++#define SRCCAL2 2 ++#define SRCCAL3 3 ++#define SRCCAL4 4 ++#define SRCCAL5 5 ++#define SRCTC0 6 ++#define SRCTC1 7 ++ ++#define FRCCAL _SFR_MEM8(0xC7) ++#define FRCCAL0 0 ++#define FRCCAL1 1 ++#define FRCCAL2 2 ++#define FRCCAL3 3 ++#define FRCCAL4 4 ++#define FRCTC 5 ++ ++#define CMSR _SFR_MEM8(0xC8) ++#define ECF 0 ++ ++#define CMOCR _SFR_MEM8(0xC9) ++#define FRCAO 0 ++#define SRCAO 1 ++#define FRCACT 2 ++#define SRCACT 3 ++ ++#define SUPFR _SFR_MEM8(0xCA) ++#define AVCCRF 0 ++#define AVCCLF 1 ++ ++#define SUPCR _SFR_MEM8(0xCB) ++#define AVCCRM 0 ++#define AVCCLM 1 ++#define PVEN 2 ++#define DVDIS 4 ++#define AVEN 5 ++#define AVDIC 6 ++ ++/* Reserved [0xCC] */ ++ ++#define SUPCA2 _SFR_MEM8(0xCD) ++#define BGCAL0 0 ++#define BGCAL1 1 ++#define BGCAL2 2 ++#define BGCAL3 3 ++ ++#define SUPCA3 _SFR_MEM8(0xCE) ++#define ACAL4 0 ++#define ACAL5 1 ++#define ACAL6 2 ++#define ACAL7 3 ++#define DCAL4 4 ++#define DCAL5 5 ++#define DCAL6 6 ++ ++#define SUPCA4 _SFR_MEM8(0xCF) ++#define ACAL0 0 ++#define ACAL1 1 ++#define ACAL2 2 ++#define ACAL3 3 ++#define DCAL0 4 ++#define DCAL1 5 ++#define DCAL2 6 ++#define DCAL3 7 ++ ++#define CALRDY _SFR_MEM8(0xD0) ++ ++#define VMCAL _SFR_MEM8(0xD1) ++#define VMCAL0 0 ++#define VMCAL1 1 ++#define VMCAL2 2 ++ ++#define DFS _SFR_MEM8(0xD2) ++#define DFFLRF 0 ++#define DFUFL 1 ++#define DFOFL 2 ++ ++/* Combine DFTLL and DFTLH */ ++#define DFTL _SFR_MEM16(0xD3) ++ ++#define DFTLL _SFR_MEM8(0xD3) ++#define DFTLH _SFR_MEM8(0xD4) ++ ++#define DFL _SFR_MEM8(0xD5) ++#define DFFLS0 0 ++#define DFFLS1 1 ++#define DFFLS2 2 ++#define DFFLS3 3 ++#define DFFLS4 4 ++#define DFFLS5 5 ++#define DFCLR 7 ++ ++#define DFWP _SFR_MEM8(0xD6) ++#define DFWP0 0 ++#define DFWP1 1 ++#define DFWP2 2 ++#define DFWP3 3 ++#define DFWP4 4 ++#define DFWP5 5 ++ ++#define DFRP _SFR_MEM8(0xD7) ++#define DFRP0 0 ++#define DFRP1 1 ++#define DFRP2 2 ++#define DFRP3 3 ++#define DFRP4 4 ++#define DFRP5 5 ++ ++#define DFD _SFR_MEM8(0xD8) ++ ++#define DFI _SFR_MEM8(0xD9) ++#define DFFLIM 0 ++#define DFERIM 1 ++ ++#define DFC _SFR_MEM8(0xDA) ++#define DFFLC0 0 ++#define DFFLC1 1 ++#define DFFLC2 2 ++#define DFFLC3 3 ++#define DFFLC4 4 ++#define DFFLC5 5 ++#define DFDRA 7 ++ ++#define SFS _SFR_MEM8(0xDB) ++#define SFFLRF 0 ++#define SFUFL 1 ++#define SFOFL 2 ++ ++#define SFL _SFR_MEM8(0xDC) ++#define SFFLS0 0 ++#define SFFLS1 1 ++#define SFFLS2 2 ++#define SFFLS3 3 ++#define SFFLS4 4 ++#define SFCLR 7 ++ ++#define SFWP _SFR_MEM8(0xDD) ++#define SFWP0 0 ++#define SFWP1 1 ++#define SFWP2 2 ++#define SFWP3 3 ++#define SFWP4 4 ++ ++#define SFRP _SFR_MEM8(0xDE) ++#define SFRP0 0 ++#define SFRP1 1 ++#define SFRP2 2 ++#define SFRP3 3 ++#define SFRP4 4 ++ ++#define SFD _SFR_MEM8(0xDF) ++ ++#define SFI _SFR_MEM8(0xE0) ++#define SFFLIM 0 ++#define SFERIM 1 ++ ++#define SFC _SFR_MEM8(0xE1) ++#define SFFLC0 0 ++#define SFFLC1 1 ++#define SFFLC2 2 ++#define SFFLC3 3 ++#define SFFLC4 4 ++#define SFDRA 7 ++ ++#define SSMCR _SFR_MEM8(0xE2) ++#define SSMTX 0 ++#define SSMTM 1 ++#define SSMTGE 2 ++#define SSMTPE 3 ++#define SSMPVE 4 ++#define SSMTAE 5 ++#define SETRPA 6 ++#define SETRPB 7 ++ ++#define SSMRCR _SFR_MEM8(0xE3) ++#define SSMPA 0 ++#define SSMPB 1 ++#define SSMADA 2 ++#define SSMADB 3 ++#define SSMPVS 4 ++#define SSMIFA 5 ++#define SSMIDSE 6 ++#define SSMTMOE 7 ++ ++#define SSMFBR _SFR_MEM8(0xE4) ++#define SSMFID0 0 ++#define SSMFID1 1 ++#define SSMFID2 2 ++#define SSMDFDT 3 ++#define SSMHADT 4 ++#define SSMPLDT 5 ++ ++#define SSMRR _SFR_MEM8(0xE5) ++#define SSMR 0 ++#define SSMST 1 ++ ++#define SSMSR _SFR_MEM8(0xE6) ++#define SSMESM0 0 ++#define SSMESM1 1 ++#define SSMESM2 2 ++#define SSMESM3 3 ++#define SSMERR 7 ++ ++#define SSMIFR _SFR_MEM8(0xE7) ++#define SSMIF 0 ++ ++#define SSMIMR _SFR_MEM8(0xE8) ++#define SSMIM 0 ++ ++#define MSMSTR _SFR_MEM8(0xE9) ++#define SSMMST0 0 ++#define SSMMST1 1 ++#define SSMMST2 2 ++#define SSMMST3 3 ++#define SSMMST4 4 ++ ++#define SSMSTR _SFR_MEM8(0xEA) ++#define SSMSTA0 0 ++#define SSMSTA1 1 ++#define SSMSTA2 2 ++#define SSMSTA3 3 ++#define SSMSTA4 4 ++#define SSMSTA5 5 ++ ++#define SSMXSR _SFR_MEM8(0xEB) ++#define SSMSTB0 0 ++#define SSMSTB1 1 ++#define SSMSTB2 2 ++#define SSMSTB3 3 ++#define SSMSTB4 4 ++#define SSMSTB5 5 ++ ++#define MSMCR1 _SFR_MEM8(0xEC) ++#define MSMSM00 0 ++#define MSMSM01 1 ++#define MSMSM02 2 ++#define MSMSM03 3 ++#define MSMSM10 4 ++#define MSMSM11 5 ++#define MSMSM12 6 ++#define MSMSM13 7 ++ ++#define MSMCR2 _SFR_MEM8(0xED) ++#define MSMSM20 0 ++#define MSMSM21 1 ++#define MSMSM22 2 ++#define MSMSM23 3 ++#define MSMSM30 4 ++#define MSMSM31 5 ++#define MSMSM32 6 ++#define MSMSM33 7 ++ ++#define MSMCR3 _SFR_MEM8(0xEE) ++#define MSMSM40 0 ++#define MSMSM41 1 ++#define MSMSM42 2 ++#define MSMSM43 3 ++#define MSMSM50 4 ++#define MSMSM51 5 ++#define MSMSM52 6 ++#define MSMSM53 7 ++ ++#define MSMCR4 _SFR_MEM8(0xEF) ++#define MSMSM60 0 ++#define MSMSM61 1 ++#define MSMSM62 2 ++#define MSMSM63 3 ++#define MSMSM70 4 ++#define MSMSM71 5 ++#define MSMSM72 6 ++#define MSMSM73 7 ++ ++#define GTCR _SFR_MEM8(0xF0) ++#define RXTEHA 0 ++#define GAPMA 1 ++#define DARA 2 ++#define IWUPA 3 ++#define RXTEHB 4 ++#define GAPMB 5 ++#define DARB 6 ++#define IWUPB 7 ++ ++#define SOTC1A _SFR_MEM8(0xF1) ++#define CAROEA1 0 ++#define AMPOEA1 1 ++#define SYTOEA1 2 ++#define MANOEA1 3 ++#define WUPEA1 4 ++#define SFIDEA1 5 ++#define RROEA1 6 ++#define WCOBOE1 7 ++ ++#define SOTC2A _SFR_MEM8(0xF2) ++#define CAROEA2 0 ++#define AMPOEA2 1 ++#define SYTOEA2 2 ++#define MANOEA2 3 ++#define WUPEA2 4 ++#define SFIDEA2 5 ++#define RROEA2 6 ++#define WCOBOE2 7 ++ ++#define SOTC1B _SFR_MEM8(0xF3) ++#define CAROEB1 0 ++#define AMPOEB1 1 ++#define SYTOEB1 2 ++#define MANOEB1 3 ++#define WUPEB1 4 ++#define SFIDEB1 5 ++#define RROEB1 6 ++#define WCOAOE1 7 ++ ++#define SOTC2B _SFR_MEM8(0xF4) ++#define CAROEB2 0 ++#define AMPOEB2 1 ++#define SYTOEB2 2 ++#define MANOEB2 3 ++#define WUPEB2 4 ++#define SFIDEB2 5 ++#define RROEB2 6 ++#define WCOAOE2 7 ++ ++#define EOTC1A _SFR_MEM8(0xF5) ++#define CARFEA1 0 ++#define AMPFEA1 1 ++#define SYTFEA1 2 ++#define MANFEA1 3 ++#define TMOFEA1 4 ++#define TELREA1 5 ++#define RRFEA1 6 ++#define EOTBFE1 7 ++ ++#define EOTC2A _SFR_MEM8(0xF6) ++#define CARFEA2 0 ++#define AMPFEA2 1 ++#define SYTFEA2 2 ++#define MANFEA2 3 ++#define TMOFEA2 4 ++#define TELREA2 5 ++#define RRFEA2 6 ++#define EOTBFE2 7 ++ ++#define EOTC3A _SFR_MEM8(0xF7) ++#define CARFEA3 0 ++#define AMPFEA3 1 ++#define SYTFEA3 2 ++#define MANFEA3 3 ++#define TMOFEA3 4 ++#define TELREA3 5 ++#define RRFEA3 6 ++#define EOTBFE3 7 ++ ++#define EOTC1B _SFR_MEM8(0xF8) ++#define CARFEB1 0 ++#define AMPFEB1 1 ++#define SYTFEB1 2 ++#define MANFEB1 3 ++#define TMOFEB1 4 ++#define TELREB1 5 ++#define RRFEB1 6 ++#define EOTAFE1 7 ++ ++#define EOTC2B _SFR_MEM8(0xF9) ++#define CARFEB2 0 ++#define AMPFEB2 1 ++#define SYTFEB2 2 ++#define MANFEB2 3 ++#define TMOFEB2 4 ++#define TELREB2 5 ++#define RRFEB2 6 ++#define EOTAFE2 7 ++ ++#define EOTC3B _SFR_MEM8(0xFA) ++#define CARFEB3 0 ++#define AMPFEB3 1 ++#define SYTFEB3 2 ++#define MANFEB3 3 ++#define TMOFEB3 4 ++#define TELREB3 5 ++#define RRFEB3 6 ++#define EOTAFE3 7 ++ ++#define WCOTOA _SFR_MEM8(0xFB) ++ ++#define WCOTOB _SFR_MEM8(0xFC) ++ ++#define SOTTOA _SFR_MEM8(0xFD) ++ ++#define SOTTOB _SFR_MEM8(0xFE) ++ ++#define SSMFCR _SFR_MEM8(0xFF) ++#define SSMIDSO 0 ++#define SSMIDSF 1 ++ ++#define FESR _SFR_MEM8(0x100) ++#define LBSAT 0 ++#define HBSAT 1 ++#define XRDY 2 ++#define PLCK 3 ++ ++#define FEEN1 _SFR_MEM8(0x101) ++#define PLEN 0 ++#define PLCAL 1 ++#define XTOEN 2 ++#define LNAEN 3 ++#define ADEN 4 ++#define ADCLK 5 ++#define PLSP1 6 ++#define ATEN 7 ++ ++#define FEEN2 _SFR_MEM8(0x102) ++#define SDRX 0 ++#define SDRX2 1 ++#define PAEN 2 ++#define TMPM 3 ++#define PLPEN 4 ++#define XTPEN 5 ++ ++#define FELNA _SFR_MEM8(0x103) ++#define LBH0 0 ++#define LBH1 1 ++#define LBH2 2 ++#define LBH3 3 ++#define LBL0 4 ++#define LBL1 5 ++#define LBL2 6 ++#define LBL3 7 ++ ++/* Reserved [0x104..0x105] */ ++ ++#define FEVCT _SFR_MEM8(0x106) ++#define FEVCT0 0 ++#define FEVCT1 1 ++#define FEVCT2 2 ++#define FEVCT3 3 ++ ++#define FEBT _SFR_MEM8(0x107) ++#define CTN20 0 ++#define CTN21 1 ++#define RTN20 2 ++#define RTN21 3 ++ ++#define FEMS _SFR_MEM8(0x108) ++#define PLLS0 0 ++#define PLLS1 1 ++#define PLLS2 2 ++#define PLLS3 3 ++#define PLLM0 4 ++#define PLLM1 5 ++#define PLLM2 6 ++#define PLLM3 7 ++ ++#define FETN4 _SFR_MEM8(0x109) ++#define CTN40 0 ++#define CTN41 1 ++#define CTN42 2 ++#define CTN43 3 ++#define RTN40 4 ++#define RTN41 5 ++#define RTN42 6 ++#define RTN43 7 ++ ++#define FECR _SFR_MEM8(0x10A) ++#define LBNHB 0 ++#define S4N3 1 ++#define ANDP 2 ++#define ADHS 3 ++#define PLCKG 4 ++#define ANPS 5 ++ ++#define FEVCO _SFR_MEM8(0x10B) ++#define CPCC0 0 ++#define CPCC1 1 ++#define CPCC2 2 ++#define CPCC3 3 ++#define VCOB0 4 ++#define VCOB1 5 ++#define VCOB2 6 ++#define VCOB3 7 ++ ++#define FEALR _SFR_MEM8(0x10C) ++#define RNGE0 0 ++#define RNGE1 1 ++ ++#define FEANT _SFR_MEM8(0x10D) ++#define LVLC0 0 ++#define LVLC1 1 ++#define LVLC2 2 ++#define LVLC3 3 ++ ++#define FEBIA _SFR_MEM8(0x10E) ++#define IFAEN 7 ++ ++/* Reserved [0x10F..0x12E] */ ++ ++#define RXBC1 _SFR_MEM8(0x12F) ++#define RXCEA 0 ++#define RXCBLA0 1 ++#define RXCBLA1 2 ++#define RXMSBA 3 ++#define RXCEB 4 ++#define RXCBLB0 5 ++#define RXCBLB1 6 ++#define RXMSBB 7 ++ ++#define RXBC2 _SFR_MEM8(0x130) ++#define RXBPB 0 ++#define RXBF 1 ++#define RXBCLR 2 ++ ++#define RXTLLB _SFR_MEM8(0x131) ++ ++#define RXTLHB _SFR_MEM8(0x132) ++#define RXTLHB0 0 ++#define RXTLHB1 1 ++#define RXTLHB2 2 ++#define RXTLHB3 3 ++ ++#define RXCRLB _SFR_MEM8(0x133) ++ ++#define RXCRHB _SFR_MEM8(0x134) ++ ++#define RXCSBB _SFR_MEM8(0x135) ++ ++#define RXCILB _SFR_MEM8(0x136) ++ ++#define RXCIHB _SFR_MEM8(0x137) ++ ++#define RXCPLB _SFR_MEM8(0x138) ++ ++#define RXCPHB _SFR_MEM8(0x139) ++ ++#define RXDSB _SFR_MEM8(0x13A) ++ ++#define RXTLLA _SFR_MEM8(0x13B) ++ ++#define RXTLHA _SFR_MEM8(0x13C) ++#define RXTLHA0 0 ++#define RXTLHA1 1 ++#define RXTLHA2 2 ++#define RXTLHA3 3 ++ ++#define RXCRLA _SFR_MEM8(0x13D) ++ ++#define RXCRHA _SFR_MEM8(0x13E) ++ ++#define RXCSBA _SFR_MEM8(0x13F) ++ ++#define RXCILA _SFR_MEM8(0x140) ++ ++#define RXCIHA _SFR_MEM8(0x141) ++ ++#define RXCPLA _SFR_MEM8(0x142) ++ ++#define RXCPHA _SFR_MEM8(0x143) ++ ++#define RXDSA _SFR_MEM8(0x144) ++ ++#define CRCCR _SFR_MEM8(0x145) ++#define CRCRS 0 ++#define REFLI 1 ++#define REFLO 2 ++ ++#define CRCDOR _SFR_MEM8(0x146) ++ ++#define IDB0 _SFR_MEM8(0x147) ++ ++#define IDB1 _SFR_MEM8(0x148) ++ ++#define IDB2 _SFR_MEM8(0x149) ++ ++#define IDB3 _SFR_MEM8(0x14A) ++ ++#define IDC _SFR_MEM8(0x14B) ++#define IDL0 0 ++#define IDL1 1 ++#define IDBO0 2 ++#define IDBO1 3 ++#define IDFIM 5 ++#define IDCLR 6 ++#define IDCE 7 ++ ++#define IDS _SFR_MEM8(0x14C) ++#define IDOK 0 ++#define IDFULL 1 ++ ++#define RSSAV _SFR_MEM8(0x14D) ++ ++#define RSSPK _SFR_MEM8(0x14E) ++ ++#define RSSL _SFR_MEM8(0x14F) ++ ++#define RSSH _SFR_MEM8(0x150) ++ ++#define RSSC _SFR_MEM8(0x151) ++#define RSUP0 0 ++#define RSUP1 1 ++#define RSUP2 2 ++#define RSUP3 3 ++#define RSWLH 4 ++#define RSHRX 5 ++#define RSPKF 6 ++ ++#define DBCR _SFR_MEM8(0x152) ++#define DBMD 0 ++#define DBCS 1 ++#define DBTMS 2 ++#define DBHA 3 ++ ++#define DBTC _SFR_MEM8(0x153) ++ ++#define DBENB _SFR_MEM8(0x154) ++ ++#define DBENC _SFR_MEM8(0x155) ++ ++#define DBGSW _SFR_MEM8(0x156) ++#define DBGGS0 0 ++#define DBGGS1 1 ++#define DBGGS2 2 ++#define DBGGS3 3 ++#define CPBFOS0 4 ++#define CPBFOS1 5 ++#define CPBF 6 ++#define DBGSE 7 ++ ++#define SFFR _SFR_MEM8(0x157) ++#define RFL0 0 ++#define RFL1 1 ++#define RFL2 2 ++#define RFC 3 ++#define TFL0 4 ++#define TFL1 5 ++#define TFL2 6 ++#define TFC 7 ++ ++#define SFIR _SFR_MEM8(0x158) ++#define RIL0 0 ++#define RIL1 1 ++#define RIL2 2 ++#define SRIE 3 ++#define TIL0 4 ++#define TIL1 5 ++#define TIL2 6 ++#define STIE 7 ++ ++#define EECR2 _SFR_MEM8(0x159) ++#define EEBRE 0 ++ ++#define PGMST _SFR_MEM8(0x15A) ++#define PGMSYN0 0 ++#define PGMSYN1 1 ++#define PGMSYN2 2 ++#define PGMSYN3 3 ++#define PGMSYN4 4 ++ ++#define EEST _SFR_MEM8(0x15B) ++#define EESYN0 0 ++#define EESYN1 1 ++#define EESYN2 2 ++#define EESYN3 3 ++ ++#define RSIFG _SFR_MEM8(0x15C) ++ ++#define RSLDV _SFR_MEM8(0x15D) ++ ++#define RSHDV _SFR_MEM8(0x15E) ++ ++#define RSCOM _SFR_MEM8(0x15F) ++#define RSDC 0 ++#define RSIFC 1 ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCI0_vect _VECTOR(3) ++#define PCI0_vect_num 3 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCI1_vect _VECTOR(4) ++#define PCI1_vect_num 4 ++ ++/* Voltage Monitoring Interrupt */ ++#define VMON_vect _VECTOR(5) ++#define VMON_vect_num 5 ++ ++/* AVCC Reset Interrupt */ ++#define AVCCR_vect _VECTOR(6) ++#define AVCCR_vect_num 6 ++ ++/* AVCC Low Interrupt */ ++#define AVCCL_vect _VECTOR(7) ++#define AVCCL_vect_num 7 ++ ++/* Timer 0 Interval Interrupt */ ++#define T0INT_vect _VECTOR(8) ++#define T0INT_vect_num 8 ++ ++/* Timer/Counter1 Compare Match Interrupt */ ++#define T1COMP_vect _VECTOR(9) ++#define T1COMP_vect_num 9 ++ ++/* Timer/Counter1 Overflow Interrupt */ ++#define T1OVF_vect _VECTOR(10) ++#define T1OVF_vect_num 10 ++ ++/* Timer/Counter2 Compare Match Interrupt */ ++#define T2COMP_vect _VECTOR(11) ++#define T2COMP_vect_num 11 ++ ++/* Timer/Counter2 Overflow Interrupt */ ++#define T2OVF_vect _VECTOR(12) ++#define T2OVF_vect_num 12 ++ ++/* Timer/Counter3 Capture Event Interrupt */ ++#define T3CAP_vect _VECTOR(13) ++#define T3CAP_vect_num 13 ++ ++/* Timer/Counter3 Compare Match Interrupt */ ++#define T3COMP_vect _VECTOR(14) ++#define T3COMP_vect_num 14 ++ ++/* Timer/Counter3 Overflow Interrupt */ ++#define T3OVF_vect _VECTOR(15) ++#define T3OVF_vect_num 15 ++ ++/* Timer/Counter4 Capture Event Interrupt */ ++#define T4CAP_vect _VECTOR(16) ++#define T4CAP_vect_num 16 ++ ++/* Timer/Counter4 Compare Match Interrupt */ ++#define T4COMP_vect _VECTOR(17) ++#define T4COMP_vect_num 17 ++ ++/* Timer/Counter4 Overflow Interrupt */ ++#define T4OVF_vect _VECTOR(18) ++#define T4OVF_vect_num 18 ++ ++/* Timer/Counter5 Compare Match Interrupt */ ++#define T5COMP_vect _VECTOR(19) ++#define T5COMP_vect_num 19 ++ ++/* Timer/Counter5 Overflow Interrupt */ ++#define T5OVF_vect _VECTOR(20) ++#define T5OVF_vect_num 20 ++ ++/* SPI Serial Transfer Complete Interrupt */ ++#define SPI_vect _VECTOR(21) ++#define SPI_vect_num 21 ++ ++/* SPI Rx Buffer Interrupt */ ++#define SRX_FIFO_vect _VECTOR(22) ++#define SRX_FIFO_vect_num 22 ++ ++/* SPI Tx Buffer Interrupt */ ++#define STX_FIFO_vect _VECTOR(23) ++#define STX_FIFO_vect_num 23 ++ ++/* Sequencer State Machine Interrupt */ ++#define SSM_vect _VECTOR(24) ++#define SSM_vect_num 24 ++ ++/* Data FIFO fill level reached Interrupt */ ++#define DFFLR_vect _VECTOR(25) ++#define DFFLR_vect_num 25 ++ ++/* Data FIFO overflow or underflow error Interrupt */ ++#define DFOUE_vect _VECTOR(26) ++#define DFOUE_vect_num 26 ++ ++/* RSSI/Preamble FIFO fill level reached Interrupt */ ++#define SFFLR_vect _VECTOR(27) ++#define SFFLR_vect_num 27 ++ ++/* RSSI/Preamble FIFO overflow or underflow error Interrupt */ ++#define SFOUE_vect _VECTOR(28) ++#define SFOUE_vect_num 28 ++ ++/* Tx Modulator Telegram Finish Interrupt */ ++#define TMTCF_vect _VECTOR(29) ++#define TMTCF_vect_num 29 ++ ++/* UHF receiver wake up ok on Rx path B */ ++#define UHF_WCOB_vect _VECTOR(30) ++#define UHF_WCOB_vect_num 30 ++ ++/* UHF receiver wake up ok on Rx path A */ ++#define UHF_WCOA_vect _VECTOR(31) ++#define UHF_WCOA_vect_num 31 ++ ++/* UHF receiver start of telegram ok on Rx path B */ ++#define UHF_SOTB_vect _VECTOR(32) ++#define UHF_SOTB_vect_num 32 ++ ++/* UHF receiver start of telegram ok on Rx path A */ ++#define UHF_SOTA_vect _VECTOR(33) ++#define UHF_SOTA_vect_num 33 ++ ++/* UHF receiver end of telegram on Rx path B */ ++#define UHF_EOTB_vect _VECTOR(34) ++#define UHF_EOTB_vect_num 34 ++ ++/* UHF receiver end of telegram on Rx path A */ ++#define UHF_EOTA_vect _VECTOR(35) ++#define UHF_EOTA_vect_num 35 ++ ++/* UHF receiver new bit on Rx path B */ ++#define UHF_NBITB_vect _VECTOR(36) ++#define UHF_NBITB_vect_num 36 ++ ++/* UHF receiver new bit on Rx path A */ ++#define UHF_NBITA_vect _VECTOR(37) ++#define UHF_NBITA_vect_num 37 ++ ++/* External input Clock monitoring Interrupt */ ++#define EXCM_vect _VECTOR(38) ++#define EXCM_vect_num 38 ++ ++/* EEPROM Ready Interrupt */ ++#define ERDY_vect _VECTOR(39) ++#define ERDY_vect_num 39 ++ ++/* Store Program Memory Ready */ ++#define SPMR_vect _VECTOR(40) ++#define SPMR_vect_num 40 ++ ++/* IDSCAN Full Interrupt */ ++#define IDFULL_vect _VECTOR(41) ++#define IDFULL_vect_num 41 ++ ++#define _VECTORS_SIZE 168 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 64 ++#define FLASHSTART 0x8000 ++#define FLASHEND 0xCFFF ++#define RAMSTART 0x0200 ++#define RAMSIZE 1024 ++#define RAMEND 0x05FF ++#define E2START 0 ++#define E2SIZE 1152 ++#define E2PAGESIZE 16 ++#define E2END 0x047F ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Fuse Byte */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(128) ++#define FUSE_DWEN (unsigned char)~_BV(64) ++#define FUSE_SPIEN (unsigned char)~_BV(32) ++#define FUSE_WDTON (unsigned char)~_BV(16) ++#define FUSE_EESAVE (unsigned char)~_BV(8) ++#define FUSE_BOOTRST (unsigned char)~_BV(4) ++#define FUSE_RSTDISBL (unsigned char)~_BV(2) ++#define FUSE_EXTCLKEN (unsigned char)~_BV(1) ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x64 ++ ++ ++#endif /* #ifdef _AVR_ATA5781_H_INCLUDED */ ++ +diff --git a/include/avr/ioa5782.h b/include/avr/ioa5782.h +new file mode 100644 +index 0000000..6d6e4b4 +--- /dev/null ++++ b/include/avr/ioa5782.h +@@ -0,0 +1,1781 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATA5782_H_INCLUDED ++#define _AVR_ATA5782_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "ioa5782.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PRR0 _SFR_IO8(0x01) ++#define PRSPI 0 ++#define PRRXDC 1 ++#define PRTXDC 2 ++#define PRCRC 3 ++#define PRVM 4 ++#define PRCO 5 ++ ++#define PRR1 _SFR_IO8(0x02) ++#define PRT1 0 ++#define PRT2 1 ++#define PRT3 2 ++#define PRT4 3 ++#define PRT5 4 ++ ++#define PRR2 _SFR_IO8(0x03) ++#define PRXB 0 ++#define PRXA 1 ++#define PRSF 2 ++#define PRDF 3 ++#define PRIDS 4 ++#define PRRS 5 ++#define PRTM 6 ++#define PRSSM 7 ++ ++#define RDPR _SFR_IO8(0x04) ++#define PRPTB 0 ++#define PRPTA 1 ++#define PRFLT 2 ++#define PRTMP 3 ++#define APRPTB 4 ++#define APRPTA 5 ++#define ARDPRF 6 ++#define RDPRF 7 ++ ++#define PINB _SFR_IO8(0x05) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x06) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x07) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x08) ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x09) ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x0A) ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++/* Reserved [0x0B..0x0C] */ ++ ++#define RDSIFR _SFR_IO8(0x0D) ++#define NBITA 0 ++#define NBITB 1 ++#define EOTA 2 ++#define EOTB 3 ++#define SOTA 4 ++#define SOTB 5 ++#define WCOA 6 ++#define WCOB 7 ++ ++#define MCUCR _SFR_IO8(0x0E) ++#define IVCE 0 ++#define IVSEL 1 ++#define SPIIO 2 ++#define ENPS 3 ++#define PUD 4 ++#define PB4HS 5 ++#define PB7LS 6 ++#define PB7HS 7 ++ ++#define PCIFR _SFR_IO8(0x0F) ++#define PCIF0 0 ++#define PCIF1 1 ++ ++#define T0CR _SFR_IO8(0x10) ++#define T0PS0 0 ++#define T0PS1 1 ++#define T0PS2 2 ++#define T0IE 3 ++#define T0PR 4 ++ ++#define T1CR _SFR_IO8(0x11) ++#define T1OTM 0 ++#define T1CTM 1 ++#define T1CRM 2 ++#define T1TOP 4 ++#define T1RES 5 ++#define T1TOS 6 ++#define T1ENA 7 ++ ++#define T2CR _SFR_IO8(0x12) ++#define T2OTM 0 ++#define T2CTM 1 ++#define T2CRM 2 ++#define T2TOP 4 ++#define T2RES 5 ++#define T2TOS 6 ++#define T2ENA 7 ++ ++#define T3CR _SFR_IO8(0x13) ++#define T3OTM 0 ++#define T3CTM 1 ++#define T3CRM 2 ++#define T3CPRM 3 ++#define T3TOP 4 ++#define T3RES 5 ++#define T3TOS 6 ++#define T3ENA 7 ++ ++#define T4CR _SFR_IO8(0x14) ++#define T4OTM 0 ++#define T4CTM 1 ++#define T4CRM 2 ++#define T4CPRM 3 ++#define T4TOP 4 ++#define T4RES 5 ++#define T4TOS 6 ++#define T4ENA 7 ++ ++#define T1IFR _SFR_IO8(0x15) ++#define T1OFF 0 ++#define T1COF 1 ++ ++#define T2IFR _SFR_IO8(0x16) ++#define T2OFF 0 ++#define T2COF 1 ++ ++#define T3IFR _SFR_IO8(0x17) ++#define T3OFF 0 ++#define T3COF 1 ++#define T3ICF 2 ++ ++#define T4IFR _SFR_IO8(0x18) ++#define T4OFF 0 ++#define T4COF 1 ++#define T4ICF 2 ++ ++#define T5IFR _SFR_IO8(0x19) ++#define T5OFF 0 ++#define T5COF 1 ++ ++#define GPIOR0 _SFR_IO8(0x1A) ++ ++#define GPIOR3 _SFR_IO8(0x1B) ++ ++#define GPIOR4 _SFR_IO8(0x1C) ++ ++#define GPIOR5 _SFR_IO8(0x1D) ++ ++#define GPIOR6 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++#define EEPAGE 6 ++#define NVMBSY 7 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define EEPR _SFR_IO8(0x23) ++#define EEAP0 0 ++#define EEAP1 1 ++#define EEAP2 2 ++#define EEAP3 3 ++ ++#define GPIOR1 _SFR_IO8(0x24) ++ ++#define GPIOR2 _SFR_IO8(0x25) ++ ++#define PCICR _SFR_IO8(0x26) ++#define PCIE0 0 ++#define PCIE1 1 ++ ++#define EIMSK _SFR_IO8(0x27) ++#define INT0 0 ++#define INT1 1 ++ ++#define EIFR _SFR_IO8(0x28) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define CRCDIR _SFR_IO8(0x29) ++ ++#define VMCSR _SFR_IO8(0x2A) ++#define VMLS0 0 ++#define VMLS1 1 ++#define VMLS2 2 ++#define VMLS3 3 ++#define VMIM 4 ++#define VMF 5 ++ ++#define MCUSR _SFR_IO8(0x2B) ++#define PORF 0 ++#define EXTRF 1 ++#define WDRF 3 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define RXIF 4 ++#define TXIF 5 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++#define T0IFR _SFR_IO8(0x2F) ++#define T0F 0 ++ ++/* Reserved [0x30] */ ++ ++#define DWDR _SFR_IO8(0x31) ++ ++/* Reserved [0x32] */ ++ ++#define RDCR _SFR_IO8(0x33) ++#define RDPU 0 ++#define ADIVEN 1 ++#define RDEN 2 ++ ++#define EOTSA _SFR_IO8(0x34) ++#define CARFA 0 ++#define AMPFA 1 ++#define SYTFA 2 ++#define MANFA 3 ++#define TMOFA 4 ++#define TELRA 5 ++#define RRFA 6 ++#define EOTBF 7 ++ ++#define EOTCA _SFR_IO8(0x35) ++#define CARFEA 0 ++#define AMPFEA 1 ++#define SYTFEA 2 ++#define MANFEA 3 ++#define TMOFEA 4 ++#define TELREA 5 ++#define RRFEA 6 ++#define EOTBFE 7 ++ ++#define EOTSB _SFR_IO8(0x36) ++#define CARFB 0 ++#define AMPFB 1 ++#define SYTFB 2 ++#define MANFB 3 ++#define TMOFB 4 ++#define TELRB 5 ++#define RRFB 6 ++#define EOTAF 7 ++ ++#define EOTCB _SFR_IO8(0x37) ++#define CARFEB 0 ++#define AMPFEB 1 ++#define SYTFEB 2 ++#define MANFEB 3 ++#define TMOFEB 4 ++#define TELREB 5 ++#define RRFEB 6 ++#define EOTAFE 7 ++ ++#define SMCR _SFR_IO8(0x38) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define CMCR _SFR_IO8(0x39) ++#define CMM0 0 ++#define CMM1 1 ++#define CMM2 2 ++#define CCS 3 ++#define SRCD 4 ++#define CMONEN 6 ++#define CMCCE 7 ++ ++#define CMIMR _SFR_IO8(0x3A) ++#define ECIE 0 ++ ++#define CLPR _SFR_IO8(0x3B) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLTPS0 3 ++#define CLTPS1 4 ++#define CLTPS2 5 ++#define CLPCE 7 ++ ++#define SPMCSR _SFR_IO8(0x3C) ++#define SELFPRGEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define SPMIE 7 ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define FSEN _SFR_MEM8(0x60) ++#define SDPU 0 ++#define SDEN 1 ++ ++/* Reserved [0x61..0x63] */ ++ ++#define FFREQ1L _SFR_MEM8(0x64) ++ ++#define FFREQ1M _SFR_MEM8(0x65) ++ ++#define FFREQ1H _SFR_MEM8(0x66) ++ ++#define FFREQ2L _SFR_MEM8(0x67) ++ ++#define FFREQ2M _SFR_MEM8(0x68) ++ ++#define FFREQ2H _SFR_MEM8(0x69) ++ ++/* Reserved [0x6A] */ ++ ++#define EICRA _SFR_MEM8(0x6B) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++#define PCMSK0 _SFR_MEM8(0x6C) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6D) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++ ++#define WDTCR _SFR_MEM8(0x6E) ++#define WDPS0 0 ++#define WDPS1 1 ++#define WDPS2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define T1CNT _SFR_MEM8(0x6F) ++ ++#define T1COR _SFR_MEM8(0x70) ++ ++#define T1MR _SFR_MEM8(0x71) ++#define T1CS0 0 ++#define T1CS1 1 ++#define T1PS0 2 ++#define T1PS1 3 ++#define T1PS2 4 ++#define T1PS3 5 ++#define T1DC0 6 ++#define T1DC1 7 ++ ++#define T1IMR _SFR_MEM8(0x72) ++#define T1OIM 0 ++#define T1CIM 1 ++ ++#define T2CNT _SFR_MEM8(0x73) ++ ++#define T2COR _SFR_MEM8(0x74) ++ ++#define T2MR _SFR_MEM8(0x75) ++#define T2CS0 0 ++#define T2CS1 1 ++#define T2PS0 2 ++#define T2PS1 3 ++#define T2PS2 4 ++#define T2PS3 5 ++#define T2DC0 6 ++#define T2DC1 7 ++ ++#define T2IMR _SFR_MEM8(0x76) ++#define T2OIM 0 ++#define T2CIM 1 ++ ++/* Combine T3CNTL and T3CNTH */ ++#define T3CNT _SFR_MEM16(0x77) ++ ++#define T3CNTL _SFR_MEM8(0x77) ++#define T3CNTH _SFR_MEM8(0x78) ++ ++/* Combine T3CORL and T3CORH */ ++#define T3COR _SFR_MEM16(0x79) ++ ++#define T3CORL _SFR_MEM8(0x79) ++#define T3CORH _SFR_MEM8(0x7A) ++ ++/* Combine T3ICRL and T3ICRH */ ++#define T3ICR _SFR_MEM16(0x7B) ++ ++#define T3ICRL _SFR_MEM8(0x7B) ++#define T3ICRH _SFR_MEM8(0x7C) ++ ++#define T3MRA _SFR_MEM8(0x7D) ++#define T3CS0 0 ++#define T3CS1 1 ++#define T3PS0 2 ++#define T3PS1 3 ++#define T3PS2 4 ++ ++#define T3MRB _SFR_MEM8(0x7E) ++#define T3SCE 1 ++#define T3CNC 2 ++#define T3CE0 3 ++#define T3CE1 4 ++#define T3ICS0 5 ++#define T3ICS1 6 ++#define T3ICS2 7 ++ ++#define T3IMR _SFR_MEM8(0x7F) ++#define T3OIM 0 ++#define T3CIM 1 ++#define T3CPIM 2 ++ ++/* Combine T4CNTL and T4CNTH */ ++#define T4CNT _SFR_MEM16(0x80) ++ ++#define T4CNTL _SFR_MEM8(0x80) ++#define T4CNTH _SFR_MEM8(0x81) ++ ++/* Combine T4CORL and T4CORH */ ++#define T4COR _SFR_MEM16(0x82) ++ ++#define T4CORL _SFR_MEM8(0x82) ++#define T4CORH _SFR_MEM8(0x83) ++ ++/* Combine T4ICRL and T4ICRH */ ++#define T4ICR _SFR_MEM16(0x84) ++ ++#define T4ICRL _SFR_MEM8(0x84) ++#define T4ICRH _SFR_MEM8(0x85) ++ ++#define T4MRA _SFR_MEM8(0x86) ++#define T4CS0 0 ++#define T4CS1 1 ++#define T4PS0 2 ++#define T4PS1 3 ++#define T4PS2 4 ++ ++#define T4MRB _SFR_MEM8(0x87) ++#define T4SCE 1 ++#define T4CNC 2 ++#define T4CE0 3 ++#define T4CE1 4 ++#define T4ICS0 5 ++#define T4ICS1 6 ++#define T4ICS2 7 ++ ++#define T4IMR _SFR_MEM8(0x88) ++#define T4OIM 0 ++#define T4CIM 1 ++#define T4CPIM 2 ++ ++/* Reserved [0x89] */ ++ ++/* Combine T5OCRL and T5OCRH */ ++#define T5OCR _SFR_MEM16(0x8A) ++ ++#define T5OCRL _SFR_MEM8(0x8A) ++#define T5OCRH _SFR_MEM8(0x8B) ++ ++#define T5CCR _SFR_MEM8(0x8C) ++#define T5CS0 0 ++#define T5CS1 1 ++#define T5CS2 2 ++#define T5CTC 3 ++ ++/* Combine T5CNTL and T5CNTH */ ++#define T5CNT _SFR_MEM16(0x8D) ++ ++#define T5CNTL _SFR_MEM8(0x8D) ++#define T5CNTH _SFR_MEM8(0x8E) ++ ++#define T5IMR _SFR_MEM8(0x8F) ++#define T5OIM 0 ++#define T5CIM 1 ++ ++#define GTCCR _SFR_MEM8(0x90) ++#define PSR10 0 ++#define TSM 7 ++ ++#define SOTSB _SFR_MEM8(0x91) ++#define CAROB 0 ++#define AMPOB 1 ++#define SYTOB 2 ++#define MANOB 3 ++#define WUPOB 4 ++#define SFIDOB 5 ++#define RROB 6 ++#define WCOAO 7 ++ ++#define SOTSA _SFR_MEM8(0x92) ++#define CAROA 0 ++#define AMPOA 1 ++#define SYTOA 2 ++#define MANOA 3 ++#define WUPOA 4 ++#define SFIDOA 5 ++#define RROA 6 ++#define WCOBO 7 ++ ++#define SOTCB _SFR_MEM8(0x93) ++#define CAROEB 0 ++#define AMPOEB 1 ++#define SYTOEB 2 ++#define MANOEB 3 ++#define WUPEB 4 ++#define SFIDEB 5 ++#define RROEB 6 ++#define WCOAOE 7 ++ ++#define SOTCA _SFR_MEM8(0x94) ++#define CAROEA 0 ++#define AMPOEA 1 ++#define SYTOEA 2 ++#define MANOEA 3 ++#define WUPEA 4 ++#define SFIDEA 5 ++#define RROEA 6 ++#define WCOBOE 7 ++ ++#define TESRB _SFR_MEM8(0x95) ++#define CRCOB 0 ++#define EOTLB0 1 ++#define EOTLB1 2 ++ ++#define TESRA _SFR_MEM8(0x96) ++#define CRCOA 0 ++#define EOTLA0 1 ++#define EOTLA1 2 ++ ++/* Reserved [0x97] */ ++ ++#define RDSIMR _SFR_MEM8(0x98) ++#define NBITAM 0 ++#define NBITBM 1 ++#define EOTAM 2 ++#define EOTBM 3 ++#define SOTAM 4 ++#define SOTBM 5 ++#define WCOAM 6 ++#define WCOBM 7 ++ ++#define RDOCR _SFR_MEM8(0x99) ++#define TMDS0 1 ++#define TMDS1 2 ++#define ETRPA 3 ++#define ETRPB 4 ++#define RDSIDA 5 ++#define RDSIDB 6 ++ ++/* Reserved [0x9A] */ ++ ++#define TEMPL _SFR_MEM8(0x9B) ++ ++#define TEMPH _SFR_MEM8(0x9C) ++ ++#define SYCB _SFR_MEM8(0x9D) ++#define SYCSB0 0 ++#define SYCSB1 1 ++#define SYCSB2 2 ++#define SYCSB3 3 ++#define SYTLB0 4 ++#define SYTLB1 5 ++#define SYTLB2 6 ++#define SYTLB3 7 ++ ++#define SYCA _SFR_MEM8(0x9E) ++#define SYCSA0 0 ++#define SYCSA1 1 ++#define SYCSA2 2 ++#define SYCSA3 3 ++#define SYTLA0 4 ++#define SYTLA1 5 ++#define SYTLA2 6 ++#define SYTLA3 7 ++ ++#define RXFOB _SFR_MEM8(0x9F) ++ ++#define RXFOA _SFR_MEM8(0xA0) ++ ++#define DMMB _SFR_MEM8(0xA1) ++#define DMATB0 0 ++#define DMATB1 1 ++#define DMATB2 2 ++#define DMATB3 3 ++#define DMATB4 4 ++#define DMPB 5 ++#define DMHB 6 ++#define DMNEB 7 ++ ++#define DMMA _SFR_MEM8(0xA2) ++#define DMATA0 0 ++#define DMATA1 1 ++#define DMATA2 2 ++#define DMATA3 3 ++#define DMATA4 4 ++#define DMPA 5 ++#define DMHA 6 ++#define DMNEA 7 ++ ++#define DMCDB _SFR_MEM8(0xA3) ++#define DMCLB0 0 ++#define DMCLB1 1 ++#define DMCLB2 2 ++#define DMCLB3 3 ++#define DMCLB4 4 ++#define DMCTB0 5 ++#define DMCTB1 6 ++#define DMCTB2 7 ++ ++#define DMCDA _SFR_MEM8(0xA4) ++#define DMCLA0 0 ++#define DMCLA1 1 ++#define DMCLA2 2 ++#define DMCLA3 3 ++#define DMCLA4 4 ++#define DMCTA0 5 ++#define DMCTA1 6 ++#define DMCTA2 7 ++ ++#define DMCRB _SFR_MEM8(0xA5) ++#define DMPGB0 0 ++#define DMPGB1 1 ++#define DMPGB2 2 ++#define DMPGB3 3 ++#define DMPGB4 4 ++#define SASKB 5 ++#define SY1TB 6 ++#define DMARB 7 ++ ++#define DMCRA _SFR_MEM8(0xA6) ++#define DMPGA0 0 ++#define DMPGA1 1 ++#define DMPGA2 2 ++#define DMPGA3 3 ++#define DMPGA4 4 ++#define SASKA 5 ++#define SY1TA 6 ++#define DMARA 7 ++ ++#define DMDRB _SFR_MEM8(0xA7) ++#define DMAB0 0 ++#define DMAB1 1 ++#define DMAB2 2 ++#define DMAB3 3 ++#define DMDNB0 4 ++#define DMDNB1 5 ++#define DMDNB2 6 ++#define DMDNB3 7 ++ ++#define DMDRA _SFR_MEM8(0xA8) ++#define DMAA0 0 ++#define DMAA1 1 ++#define DMAA2 2 ++#define DMAA3 3 ++#define DMDNA0 4 ++#define DMDNA1 5 ++#define DMDNA2 6 ++#define DMDNA3 7 ++ ++#define CHCR _SFR_MEM8(0xA9) ++#define BWM0 0 ++#define BWM1 1 ++#define BWM2 2 ++#define BWM3 3 ++ ++#define CHDN _SFR_MEM8(0xAA) ++#define BBDN0 0 ++#define BBDN1 1 ++#define BBDN2 2 ++#define BBDN3 3 ++#define BBDN4 4 ++#define ADCDN 5 ++ ++#define SFIDCB _SFR_MEM8(0xAB) ++#define SFIDTB0 0 ++#define SFIDTB1 1 ++#define SFIDTB2 2 ++#define SFIDTB3 3 ++#define SFIDTB4 4 ++#define SEMEB 7 ++ ++#define SFIDLB _SFR_MEM8(0xAC) ++#define SFIDLB0 0 ++#define SFIDLB1 1 ++#define SFIDLB2 2 ++#define SFIDLB3 3 ++#define SFIDLB4 4 ++#define SFIDLB5 5 ++ ++#define WUPTB _SFR_MEM8(0xAD) ++#define WUPTB0 0 ++#define WUPTB1 1 ++#define WUPTB2 2 ++#define WUPTB3 3 ++#define WUPTB4 4 ++ ++#define WUPLB _SFR_MEM8(0xAE) ++#define WUPLB0 0 ++#define WUPLB1 1 ++#define WUPLB2 2 ++#define WUPLB3 3 ++#define WUPLB4 4 ++#define WUPLB5 5 ++ ++#define SFID1B _SFR_MEM8(0xAF) ++ ++#define SFID2B _SFR_MEM8(0xB0) ++ ++#define SFID3B _SFR_MEM8(0xB1) ++ ++#define SFID4B _SFR_MEM8(0xB2) ++ ++#define WUP1B _SFR_MEM8(0xB3) ++ ++#define WUP2B _SFR_MEM8(0xB4) ++ ++#define WUP3B _SFR_MEM8(0xB5) ++ ++#define WUP4B _SFR_MEM8(0xB6) ++ ++#define SFIDCA _SFR_MEM8(0xB7) ++#define SFIDTA0 0 ++#define SFIDTA1 1 ++#define SFIDTA2 2 ++#define SFIDTA3 3 ++#define SFIDTA4 4 ++#define SEMEA 7 ++ ++#define SFIDLA _SFR_MEM8(0xB8) ++#define SFIDLA0 0 ++#define SFIDLA1 1 ++#define SFIDLA2 2 ++#define SFIDLA3 3 ++#define SFIDLA4 4 ++#define SFIDLA5 5 ++ ++#define WUPTA _SFR_MEM8(0xB9) ++#define WUPTA0 0 ++#define WUPTA1 1 ++#define WUPTA2 2 ++#define WUPTA3 3 ++#define WUPTA4 4 ++ ++#define WUPLA _SFR_MEM8(0xBA) ++#define WUPLA0 0 ++#define WUPLA1 1 ++#define WUPLA2 2 ++#define WUPLA3 3 ++#define WUPLA4 4 ++#define WUPLA5 5 ++ ++#define SFID1A _SFR_MEM8(0xBB) ++ ++#define SFID2A _SFR_MEM8(0xBC) ++ ++#define SFID3A _SFR_MEM8(0xBD) ++ ++#define SFID4A _SFR_MEM8(0xBE) ++ ++#define WUP1A _SFR_MEM8(0xBF) ++ ++#define WUP2A _SFR_MEM8(0xC0) ++ ++#define WUP3A _SFR_MEM8(0xC1) ++ ++#define WUP4A _SFR_MEM8(0xC2) ++ ++#define CLKOD _SFR_MEM8(0xC3) ++ ++#define CLKOCR _SFR_MEM8(0xC4) ++#define CLKOS0 0 ++#define CLKOS1 1 ++#define CLKOEN 2 ++ ++#define XFUSE _SFR_MEM8(0xC5) ++ ++#define SRCCAL _SFR_MEM8(0xC6) ++#define SRCCAL0 0 ++#define SRCCAL1 1 ++#define SRCCAL2 2 ++#define SRCCAL3 3 ++#define SRCCAL4 4 ++#define SRCCAL5 5 ++#define SRCTC0 6 ++#define SRCTC1 7 ++ ++#define FRCCAL _SFR_MEM8(0xC7) ++#define FRCCAL0 0 ++#define FRCCAL1 1 ++#define FRCCAL2 2 ++#define FRCCAL3 3 ++#define FRCCAL4 4 ++#define FRCTC 5 ++ ++#define CMSR _SFR_MEM8(0xC8) ++#define ECF 0 ++ ++#define CMOCR _SFR_MEM8(0xC9) ++#define FRCAO 0 ++#define SRCAO 1 ++#define FRCACT 2 ++#define SRCACT 3 ++ ++#define SUPFR _SFR_MEM8(0xCA) ++#define AVCCRF 0 ++#define AVCCLF 1 ++ ++#define SUPCR _SFR_MEM8(0xCB) ++#define AVCCRM 0 ++#define AVCCLM 1 ++#define PVEN 2 ++#define DVDIS 4 ++#define AVEN 5 ++#define AVDIC 6 ++ ++/* Reserved [0xCC] */ ++ ++#define SUPCA2 _SFR_MEM8(0xCD) ++#define BGCAL0 0 ++#define BGCAL1 1 ++#define BGCAL2 2 ++#define BGCAL3 3 ++ ++#define SUPCA3 _SFR_MEM8(0xCE) ++#define ACAL4 0 ++#define ACAL5 1 ++#define ACAL6 2 ++#define ACAL7 3 ++#define DCAL4 4 ++#define DCAL5 5 ++#define DCAL6 6 ++ ++#define SUPCA4 _SFR_MEM8(0xCF) ++#define ACAL0 0 ++#define ACAL1 1 ++#define ACAL2 2 ++#define ACAL3 3 ++#define DCAL0 4 ++#define DCAL1 5 ++#define DCAL2 6 ++#define DCAL3 7 ++ ++#define CALRDY _SFR_MEM8(0xD0) ++ ++#define VMCAL _SFR_MEM8(0xD1) ++#define VMCAL0 0 ++#define VMCAL1 1 ++#define VMCAL2 2 ++ ++#define DFS _SFR_MEM8(0xD2) ++#define DFFLRF 0 ++#define DFUFL 1 ++#define DFOFL 2 ++ ++/* Combine DFTLL and DFTLH */ ++#define DFTL _SFR_MEM16(0xD3) ++ ++#define DFTLL _SFR_MEM8(0xD3) ++#define DFTLH _SFR_MEM8(0xD4) ++ ++#define DFL _SFR_MEM8(0xD5) ++#define DFFLS0 0 ++#define DFFLS1 1 ++#define DFFLS2 2 ++#define DFFLS3 3 ++#define DFFLS4 4 ++#define DFFLS5 5 ++#define DFCLR 7 ++ ++#define DFWP _SFR_MEM8(0xD6) ++#define DFWP0 0 ++#define DFWP1 1 ++#define DFWP2 2 ++#define DFWP3 3 ++#define DFWP4 4 ++#define DFWP5 5 ++ ++#define DFRP _SFR_MEM8(0xD7) ++#define DFRP0 0 ++#define DFRP1 1 ++#define DFRP2 2 ++#define DFRP3 3 ++#define DFRP4 4 ++#define DFRP5 5 ++ ++#define DFD _SFR_MEM8(0xD8) ++ ++#define DFI _SFR_MEM8(0xD9) ++#define DFFLIM 0 ++#define DFERIM 1 ++ ++#define DFC _SFR_MEM8(0xDA) ++#define DFFLC0 0 ++#define DFFLC1 1 ++#define DFFLC2 2 ++#define DFFLC3 3 ++#define DFFLC4 4 ++#define DFFLC5 5 ++#define DFDRA 7 ++ ++#define SFS _SFR_MEM8(0xDB) ++#define SFFLRF 0 ++#define SFUFL 1 ++#define SFOFL 2 ++ ++#define SFL _SFR_MEM8(0xDC) ++#define SFFLS0 0 ++#define SFFLS1 1 ++#define SFFLS2 2 ++#define SFFLS3 3 ++#define SFFLS4 4 ++#define SFCLR 7 ++ ++#define SFWP _SFR_MEM8(0xDD) ++#define SFWP0 0 ++#define SFWP1 1 ++#define SFWP2 2 ++#define SFWP3 3 ++#define SFWP4 4 ++ ++#define SFRP _SFR_MEM8(0xDE) ++#define SFRP0 0 ++#define SFRP1 1 ++#define SFRP2 2 ++#define SFRP3 3 ++#define SFRP4 4 ++ ++#define SFD _SFR_MEM8(0xDF) ++ ++#define SFI _SFR_MEM8(0xE0) ++#define SFFLIM 0 ++#define SFERIM 1 ++ ++#define SFC _SFR_MEM8(0xE1) ++#define SFFLC0 0 ++#define SFFLC1 1 ++#define SFFLC2 2 ++#define SFFLC3 3 ++#define SFFLC4 4 ++#define SFDRA 7 ++ ++#define SSMCR _SFR_MEM8(0xE2) ++#define SSMTX 0 ++#define SSMTM 1 ++#define SSMTGE 2 ++#define SSMTPE 3 ++#define SSMPVE 4 ++#define SSMTAE 5 ++#define SETRPA 6 ++#define SETRPB 7 ++ ++#define SSMRCR _SFR_MEM8(0xE3) ++#define SSMPA 0 ++#define SSMPB 1 ++#define SSMADA 2 ++#define SSMADB 3 ++#define SSMPVS 4 ++#define SSMIFA 5 ++#define SSMIDSE 6 ++#define SSMTMOE 7 ++ ++#define SSMFBR _SFR_MEM8(0xE4) ++#define SSMFID0 0 ++#define SSMFID1 1 ++#define SSMFID2 2 ++#define SSMDFDT 3 ++#define SSMHADT 4 ++#define SSMPLDT 5 ++ ++#define SSMRR _SFR_MEM8(0xE5) ++#define SSMR 0 ++#define SSMST 1 ++ ++#define SSMSR _SFR_MEM8(0xE6) ++#define SSMESM0 0 ++#define SSMESM1 1 ++#define SSMESM2 2 ++#define SSMESM3 3 ++#define SSMERR 7 ++ ++#define SSMIFR _SFR_MEM8(0xE7) ++#define SSMIF 0 ++ ++#define SSMIMR _SFR_MEM8(0xE8) ++#define SSMIM 0 ++ ++#define MSMSTR _SFR_MEM8(0xE9) ++#define SSMMST0 0 ++#define SSMMST1 1 ++#define SSMMST2 2 ++#define SSMMST3 3 ++#define SSMMST4 4 ++ ++#define SSMSTR _SFR_MEM8(0xEA) ++#define SSMSTA0 0 ++#define SSMSTA1 1 ++#define SSMSTA2 2 ++#define SSMSTA3 3 ++#define SSMSTA4 4 ++#define SSMSTA5 5 ++ ++#define SSMXSR _SFR_MEM8(0xEB) ++#define SSMSTB0 0 ++#define SSMSTB1 1 ++#define SSMSTB2 2 ++#define SSMSTB3 3 ++#define SSMSTB4 4 ++#define SSMSTB5 5 ++ ++#define MSMCR1 _SFR_MEM8(0xEC) ++#define MSMSM00 0 ++#define MSMSM01 1 ++#define MSMSM02 2 ++#define MSMSM03 3 ++#define MSMSM10 4 ++#define MSMSM11 5 ++#define MSMSM12 6 ++#define MSMSM13 7 ++ ++#define MSMCR2 _SFR_MEM8(0xED) ++#define MSMSM20 0 ++#define MSMSM21 1 ++#define MSMSM22 2 ++#define MSMSM23 3 ++#define MSMSM30 4 ++#define MSMSM31 5 ++#define MSMSM32 6 ++#define MSMSM33 7 ++ ++#define MSMCR3 _SFR_MEM8(0xEE) ++#define MSMSM40 0 ++#define MSMSM41 1 ++#define MSMSM42 2 ++#define MSMSM43 3 ++#define MSMSM50 4 ++#define MSMSM51 5 ++#define MSMSM52 6 ++#define MSMSM53 7 ++ ++#define MSMCR4 _SFR_MEM8(0xEF) ++#define MSMSM60 0 ++#define MSMSM61 1 ++#define MSMSM62 2 ++#define MSMSM63 3 ++#define MSMSM70 4 ++#define MSMSM71 5 ++#define MSMSM72 6 ++#define MSMSM73 7 ++ ++#define GTCR _SFR_MEM8(0xF0) ++#define RXTEHA 0 ++#define GAPMA 1 ++#define DARA 2 ++#define IWUPA 3 ++#define RXTEHB 4 ++#define GAPMB 5 ++#define DARB 6 ++#define IWUPB 7 ++ ++#define SOTC1A _SFR_MEM8(0xF1) ++#define CAROEA1 0 ++#define AMPOEA1 1 ++#define SYTOEA1 2 ++#define MANOEA1 3 ++#define WUPEA1 4 ++#define SFIDEA1 5 ++#define RROEA1 6 ++#define WCOBOE1 7 ++ ++#define SOTC2A _SFR_MEM8(0xF2) ++#define CAROEA2 0 ++#define AMPOEA2 1 ++#define SYTOEA2 2 ++#define MANOEA2 3 ++#define WUPEA2 4 ++#define SFIDEA2 5 ++#define RROEA2 6 ++#define WCOBOE2 7 ++ ++#define SOTC1B _SFR_MEM8(0xF3) ++#define CAROEB1 0 ++#define AMPOEB1 1 ++#define SYTOEB1 2 ++#define MANOEB1 3 ++#define WUPEB1 4 ++#define SFIDEB1 5 ++#define RROEB1 6 ++#define WCOAOE1 7 ++ ++#define SOTC2B _SFR_MEM8(0xF4) ++#define CAROEB2 0 ++#define AMPOEB2 1 ++#define SYTOEB2 2 ++#define MANOEB2 3 ++#define WUPEB2 4 ++#define SFIDEB2 5 ++#define RROEB2 6 ++#define WCOAOE2 7 ++ ++#define EOTC1A _SFR_MEM8(0xF5) ++#define CARFEA1 0 ++#define AMPFEA1 1 ++#define SYTFEA1 2 ++#define MANFEA1 3 ++#define TMOFEA1 4 ++#define TELREA1 5 ++#define RRFEA1 6 ++#define EOTBFE1 7 ++ ++#define EOTC2A _SFR_MEM8(0xF6) ++#define CARFEA2 0 ++#define AMPFEA2 1 ++#define SYTFEA2 2 ++#define MANFEA2 3 ++#define TMOFEA2 4 ++#define TELREA2 5 ++#define RRFEA2 6 ++#define EOTBFE2 7 ++ ++#define EOTC3A _SFR_MEM8(0xF7) ++#define CARFEA3 0 ++#define AMPFEA3 1 ++#define SYTFEA3 2 ++#define MANFEA3 3 ++#define TMOFEA3 4 ++#define TELREA3 5 ++#define RRFEA3 6 ++#define EOTBFE3 7 ++ ++#define EOTC1B _SFR_MEM8(0xF8) ++#define CARFEB1 0 ++#define AMPFEB1 1 ++#define SYTFEB1 2 ++#define MANFEB1 3 ++#define TMOFEB1 4 ++#define TELREB1 5 ++#define RRFEB1 6 ++#define EOTAFE1 7 ++ ++#define EOTC2B _SFR_MEM8(0xF9) ++#define CARFEB2 0 ++#define AMPFEB2 1 ++#define SYTFEB2 2 ++#define MANFEB2 3 ++#define TMOFEB2 4 ++#define TELREB2 5 ++#define RRFEB2 6 ++#define EOTAFE2 7 ++ ++#define EOTC3B _SFR_MEM8(0xFA) ++#define CARFEB3 0 ++#define AMPFEB3 1 ++#define SYTFEB3 2 ++#define MANFEB3 3 ++#define TMOFEB3 4 ++#define TELREB3 5 ++#define RRFEB3 6 ++#define EOTAFE3 7 ++ ++#define WCOTOA _SFR_MEM8(0xFB) ++ ++#define WCOTOB _SFR_MEM8(0xFC) ++ ++#define SOTTOA _SFR_MEM8(0xFD) ++ ++#define SOTTOB _SFR_MEM8(0xFE) ++ ++#define SSMFCR _SFR_MEM8(0xFF) ++#define SSMIDSO 0 ++#define SSMIDSF 1 ++ ++#define FESR _SFR_MEM8(0x100) ++#define LBSAT 0 ++#define HBSAT 1 ++#define XRDY 2 ++#define PLCK 3 ++ ++#define FEEN1 _SFR_MEM8(0x101) ++#define PLEN 0 ++#define PLCAL 1 ++#define XTOEN 2 ++#define LNAEN 3 ++#define ADEN 4 ++#define ADCLK 5 ++#define PLSP1 6 ++#define ATEN 7 ++ ++#define FEEN2 _SFR_MEM8(0x102) ++#define SDRX 0 ++#define SDRX2 1 ++#define PAEN 2 ++#define TMPM 3 ++#define PLPEN 4 ++#define XTPEN 5 ++ ++#define FELNA _SFR_MEM8(0x103) ++#define LBH0 0 ++#define LBH1 1 ++#define LBH2 2 ++#define LBH3 3 ++#define LBL0 4 ++#define LBL1 5 ++#define LBL2 6 ++#define LBL3 7 ++ ++/* Reserved [0x104..0x105] */ ++ ++#define FEVCT _SFR_MEM8(0x106) ++#define FEVCT0 0 ++#define FEVCT1 1 ++#define FEVCT2 2 ++#define FEVCT3 3 ++ ++#define FEBT _SFR_MEM8(0x107) ++#define CTN20 0 ++#define CTN21 1 ++#define RTN20 2 ++#define RTN21 3 ++ ++#define FEMS _SFR_MEM8(0x108) ++#define PLLS0 0 ++#define PLLS1 1 ++#define PLLS2 2 ++#define PLLS3 3 ++#define PLLM0 4 ++#define PLLM1 5 ++#define PLLM2 6 ++#define PLLM3 7 ++ ++#define FETN4 _SFR_MEM8(0x109) ++#define CTN40 0 ++#define CTN41 1 ++#define CTN42 2 ++#define CTN43 3 ++#define RTN40 4 ++#define RTN41 5 ++#define RTN42 6 ++#define RTN43 7 ++ ++#define FECR _SFR_MEM8(0x10A) ++#define LBNHB 0 ++#define S4N3 1 ++#define ANDP 2 ++#define ADHS 3 ++#define PLCKG 4 ++#define ANPS 5 ++ ++#define FEVCO _SFR_MEM8(0x10B) ++#define CPCC0 0 ++#define CPCC1 1 ++#define CPCC2 2 ++#define CPCC3 3 ++#define VCOB0 4 ++#define VCOB1 5 ++#define VCOB2 6 ++#define VCOB3 7 ++ ++#define FEALR _SFR_MEM8(0x10C) ++#define RNGE0 0 ++#define RNGE1 1 ++ ++#define FEANT _SFR_MEM8(0x10D) ++#define LVLC0 0 ++#define LVLC1 1 ++#define LVLC2 2 ++#define LVLC3 3 ++ ++#define FEBIA _SFR_MEM8(0x10E) ++#define IFAEN 7 ++ ++/* Reserved [0x10F..0x12E] */ ++ ++#define RXBC1 _SFR_MEM8(0x12F) ++#define RXCEA 0 ++#define RXCBLA0 1 ++#define RXCBLA1 2 ++#define RXMSBA 3 ++#define RXCEB 4 ++#define RXCBLB0 5 ++#define RXCBLB1 6 ++#define RXMSBB 7 ++ ++#define RXBC2 _SFR_MEM8(0x130) ++#define RXBPB 0 ++#define RXBF 1 ++#define RXBCLR 2 ++ ++#define RXTLLB _SFR_MEM8(0x131) ++ ++#define RXTLHB _SFR_MEM8(0x132) ++#define RXTLHB0 0 ++#define RXTLHB1 1 ++#define RXTLHB2 2 ++#define RXTLHB3 3 ++ ++#define RXCRLB _SFR_MEM8(0x133) ++ ++#define RXCRHB _SFR_MEM8(0x134) ++ ++#define RXCSBB _SFR_MEM8(0x135) ++ ++#define RXCILB _SFR_MEM8(0x136) ++ ++#define RXCIHB _SFR_MEM8(0x137) ++ ++#define RXCPLB _SFR_MEM8(0x138) ++ ++#define RXCPHB _SFR_MEM8(0x139) ++ ++#define RXDSB _SFR_MEM8(0x13A) ++ ++#define RXTLLA _SFR_MEM8(0x13B) ++ ++#define RXTLHA _SFR_MEM8(0x13C) ++#define RXTLHA0 0 ++#define RXTLHA1 1 ++#define RXTLHA2 2 ++#define RXTLHA3 3 ++ ++#define RXCRLA _SFR_MEM8(0x13D) ++ ++#define RXCRHA _SFR_MEM8(0x13E) ++ ++#define RXCSBA _SFR_MEM8(0x13F) ++ ++#define RXCILA _SFR_MEM8(0x140) ++ ++#define RXCIHA _SFR_MEM8(0x141) ++ ++#define RXCPLA _SFR_MEM8(0x142) ++ ++#define RXCPHA _SFR_MEM8(0x143) ++ ++#define RXDSA _SFR_MEM8(0x144) ++ ++#define CRCCR _SFR_MEM8(0x145) ++#define CRCRS 0 ++#define REFLI 1 ++#define REFLO 2 ++ ++#define CRCDOR _SFR_MEM8(0x146) ++ ++#define IDB0 _SFR_MEM8(0x147) ++ ++#define IDB1 _SFR_MEM8(0x148) ++ ++#define IDB2 _SFR_MEM8(0x149) ++ ++#define IDB3 _SFR_MEM8(0x14A) ++ ++#define IDC _SFR_MEM8(0x14B) ++#define IDL0 0 ++#define IDL1 1 ++#define IDBO0 2 ++#define IDBO1 3 ++#define IDFIM 5 ++#define IDCLR 6 ++#define IDCE 7 ++ ++#define IDS _SFR_MEM8(0x14C) ++#define IDOK 0 ++#define IDFULL 1 ++ ++#define RSSAV _SFR_MEM8(0x14D) ++ ++#define RSSPK _SFR_MEM8(0x14E) ++ ++#define RSSL _SFR_MEM8(0x14F) ++ ++#define RSSH _SFR_MEM8(0x150) ++ ++#define RSSC _SFR_MEM8(0x151) ++#define RSUP0 0 ++#define RSUP1 1 ++#define RSUP2 2 ++#define RSUP3 3 ++#define RSWLH 4 ++#define RSHRX 5 ++#define RSPKF 6 ++ ++#define DBCR _SFR_MEM8(0x152) ++#define DBMD 0 ++#define DBCS 1 ++#define DBTMS 2 ++#define DBHA 3 ++ ++#define DBTC _SFR_MEM8(0x153) ++ ++#define DBENB _SFR_MEM8(0x154) ++ ++#define DBENC _SFR_MEM8(0x155) ++ ++#define DBGSW _SFR_MEM8(0x156) ++#define DBGGS0 0 ++#define DBGGS1 1 ++#define DBGGS2 2 ++#define DBGGS3 3 ++#define CPBFOS0 4 ++#define CPBFOS1 5 ++#define CPBF 6 ++#define DBGSE 7 ++ ++#define SFFR _SFR_MEM8(0x157) ++#define RFL0 0 ++#define RFL1 1 ++#define RFL2 2 ++#define RFC 3 ++#define TFL0 4 ++#define TFL1 5 ++#define TFL2 6 ++#define TFC 7 ++ ++#define SFIR _SFR_MEM8(0x158) ++#define RIL0 0 ++#define RIL1 1 ++#define RIL2 2 ++#define SRIE 3 ++#define TIL0 4 ++#define TIL1 5 ++#define TIL2 6 ++#define STIE 7 ++ ++#define EECR2 _SFR_MEM8(0x159) ++#define EEBRE 0 ++ ++#define PGMST _SFR_MEM8(0x15A) ++#define PGMSYN0 0 ++#define PGMSYN1 1 ++#define PGMSYN2 2 ++#define PGMSYN3 3 ++#define PGMSYN4 4 ++ ++#define EEST _SFR_MEM8(0x15B) ++#define EESYN0 0 ++#define EESYN1 1 ++#define EESYN2 2 ++#define EESYN3 3 ++ ++#define RSIFG _SFR_MEM8(0x15C) ++ ++#define RSLDV _SFR_MEM8(0x15D) ++ ++#define RSHDV _SFR_MEM8(0x15E) ++ ++#define RSCOM _SFR_MEM8(0x15F) ++#define RSDC 0 ++#define RSIFC 1 ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCI0_vect _VECTOR(3) ++#define PCI0_vect_num 3 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCI1_vect _VECTOR(4) ++#define PCI1_vect_num 4 ++ ++/* Voltage Monitoring Interrupt */ ++#define VMON_vect _VECTOR(5) ++#define VMON_vect_num 5 ++ ++/* AVCC Reset Interrupt */ ++#define AVCCR_vect _VECTOR(6) ++#define AVCCR_vect_num 6 ++ ++/* AVCC Low Interrupt */ ++#define AVCCL_vect _VECTOR(7) ++#define AVCCL_vect_num 7 ++ ++/* Timer 0 Interval Interrupt */ ++#define T0INT_vect _VECTOR(8) ++#define T0INT_vect_num 8 ++ ++/* Timer/Counter1 Compare Match Interrupt */ ++#define T1COMP_vect _VECTOR(9) ++#define T1COMP_vect_num 9 ++ ++/* Timer/Counter1 Overflow Interrupt */ ++#define T1OVF_vect _VECTOR(10) ++#define T1OVF_vect_num 10 ++ ++/* Timer/Counter2 Compare Match Interrupt */ ++#define T2COMP_vect _VECTOR(11) ++#define T2COMP_vect_num 11 ++ ++/* Timer/Counter2 Overflow Interrupt */ ++#define T2OVF_vect _VECTOR(12) ++#define T2OVF_vect_num 12 ++ ++/* Timer/Counter3 Capture Event Interrupt */ ++#define T3CAP_vect _VECTOR(13) ++#define T3CAP_vect_num 13 ++ ++/* Timer/Counter3 Compare Match Interrupt */ ++#define T3COMP_vect _VECTOR(14) ++#define T3COMP_vect_num 14 ++ ++/* Timer/Counter3 Overflow Interrupt */ ++#define T3OVF_vect _VECTOR(15) ++#define T3OVF_vect_num 15 ++ ++/* Timer/Counter4 Capture Event Interrupt */ ++#define T4CAP_vect _VECTOR(16) ++#define T4CAP_vect_num 16 ++ ++/* Timer/Counter4 Compare Match Interrupt */ ++#define T4COMP_vect _VECTOR(17) ++#define T4COMP_vect_num 17 ++ ++/* Timer/Counter4 Overflow Interrupt */ ++#define T4OVF_vect _VECTOR(18) ++#define T4OVF_vect_num 18 ++ ++/* Timer/Counter5 Compare Match Interrupt */ ++#define T5COMP_vect _VECTOR(19) ++#define T5COMP_vect_num 19 ++ ++/* Timer/Counter5 Overflow Interrupt */ ++#define T5OVF_vect _VECTOR(20) ++#define T5OVF_vect_num 20 ++ ++/* SPI Serial Transfer Complete Interrupt */ ++#define SPI_vect _VECTOR(21) ++#define SPI_vect_num 21 ++ ++/* SPI Rx Buffer Interrupt */ ++#define SRX_FIFO_vect _VECTOR(22) ++#define SRX_FIFO_vect_num 22 ++ ++/* SPI Tx Buffer Interrupt */ ++#define STX_FIFO_vect _VECTOR(23) ++#define STX_FIFO_vect_num 23 ++ ++/* Sequencer State Machine Interrupt */ ++#define SSM_vect _VECTOR(24) ++#define SSM_vect_num 24 ++ ++/* Data FIFO fill level reached Interrupt */ ++#define DFFLR_vect _VECTOR(25) ++#define DFFLR_vect_num 25 ++ ++/* Data FIFO overflow or underflow error Interrupt */ ++#define DFOUE_vect _VECTOR(26) ++#define DFOUE_vect_num 26 ++ ++/* RSSI/Preamble FIFO fill level reached Interrupt */ ++#define SFFLR_vect _VECTOR(27) ++#define SFFLR_vect_num 27 ++ ++/* RSSI/Preamble FIFO overflow or underflow error Interrupt */ ++#define SFOUE_vect _VECTOR(28) ++#define SFOUE_vect_num 28 ++ ++/* Tx Modulator Telegram Finish Interrupt */ ++#define TMTCF_vect _VECTOR(29) ++#define TMTCF_vect_num 29 ++ ++/* UHF receiver wake up ok on Rx path B */ ++#define UHF_WCOB_vect _VECTOR(30) ++#define UHF_WCOB_vect_num 30 ++ ++/* UHF receiver wake up ok on Rx path A */ ++#define UHF_WCOA_vect _VECTOR(31) ++#define UHF_WCOA_vect_num 31 ++ ++/* UHF receiver start of telegram ok on Rx path B */ ++#define UHF_SOTB_vect _VECTOR(32) ++#define UHF_SOTB_vect_num 32 ++ ++/* UHF receiver start of telegram ok on Rx path A */ ++#define UHF_SOTA_vect _VECTOR(33) ++#define UHF_SOTA_vect_num 33 ++ ++/* UHF receiver end of telegram on Rx path B */ ++#define UHF_EOTB_vect _VECTOR(34) ++#define UHF_EOTB_vect_num 34 ++ ++/* UHF receiver end of telegram on Rx path A */ ++#define UHF_EOTA_vect _VECTOR(35) ++#define UHF_EOTA_vect_num 35 ++ ++/* UHF receiver new bit on Rx path B */ ++#define UHF_NBITB_vect _VECTOR(36) ++#define UHF_NBITB_vect_num 36 ++ ++/* UHF receiver new bit on Rx path A */ ++#define UHF_NBITA_vect _VECTOR(37) ++#define UHF_NBITA_vect_num 37 ++ ++/* External input Clock monitoring Interrupt */ ++#define EXCM_vect _VECTOR(38) ++#define EXCM_vect_num 38 ++ ++/* EEPROM Ready Interrupt */ ++#define ERDY_vect _VECTOR(39) ++#define ERDY_vect_num 39 ++ ++/* Store Program Memory Ready */ ++#define SPMR_vect _VECTOR(40) ++#define SPMR_vect_num 40 ++ ++/* IDSCAN Full Interrupt */ ++#define IDFULL_vect _VECTOR(41) ++#define IDFULL_vect_num 41 ++ ++#define _VECTORS_SIZE 168 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 64 ++#define FLASHSTART 0x8000 ++#define FLASHEND 0xCFFF ++#define RAMSTART 0x0200 ++#define RAMSIZE 1024 ++#define RAMEND 0x05FF ++#define E2START 0 ++#define E2SIZE 1152 ++#define E2PAGESIZE 16 ++#define E2END 0x047F ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Fuse Byte */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(128) ++#define FUSE_DWEN (unsigned char)~_BV(64) ++#define FUSE_SPIEN (unsigned char)~_BV(32) ++#define FUSE_WDTON (unsigned char)~_BV(16) ++#define FUSE_EESAVE (unsigned char)~_BV(8) ++#define FUSE_BOOTRST (unsigned char)~_BV(4) ++#define FUSE_RSTDISBL (unsigned char)~_BV(2) ++#define FUSE_EXTCLKEN (unsigned char)~_BV(1) ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x65 ++ ++ ++#endif /* #ifdef _AVR_ATA5782_H_INCLUDED */ ++ +diff --git a/include/avr/ioa5783.h b/include/avr/ioa5783.h +new file mode 100644 +index 0000000..fa8c8d2 +--- /dev/null ++++ b/include/avr/ioa5783.h +@@ -0,0 +1,1781 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATA5783_H_INCLUDED ++#define _AVR_ATA5783_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "ioa5783.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PRR0 _SFR_IO8(0x01) ++#define PRSPI 0 ++#define PRRXDC 1 ++#define PRTXDC 2 ++#define PRCRC 3 ++#define PRVM 4 ++#define PRCO 5 ++ ++#define PRR1 _SFR_IO8(0x02) ++#define PRT1 0 ++#define PRT2 1 ++#define PRT3 2 ++#define PRT4 3 ++#define PRT5 4 ++ ++#define PRR2 _SFR_IO8(0x03) ++#define PRXB 0 ++#define PRXA 1 ++#define PRSF 2 ++#define PRDF 3 ++#define PRIDS 4 ++#define PRRS 5 ++#define PRTM 6 ++#define PRSSM 7 ++ ++#define RDPR _SFR_IO8(0x04) ++#define PRPTB 0 ++#define PRPTA 1 ++#define PRFLT 2 ++#define PRTMP 3 ++#define APRPTB 4 ++#define APRPTA 5 ++#define ARDPRF 6 ++#define RDPRF 7 ++ ++#define PINB _SFR_IO8(0x05) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x06) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x07) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x08) ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x09) ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x0A) ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++/* Reserved [0x0B..0x0C] */ ++ ++#define RDSIFR _SFR_IO8(0x0D) ++#define NBITA 0 ++#define NBITB 1 ++#define EOTA 2 ++#define EOTB 3 ++#define SOTA 4 ++#define SOTB 5 ++#define WCOA 6 ++#define WCOB 7 ++ ++#define MCUCR _SFR_IO8(0x0E) ++#define IVCE 0 ++#define IVSEL 1 ++#define SPIIO 2 ++#define ENPS 3 ++#define PUD 4 ++#define PB4HS 5 ++#define PB7LS 6 ++#define PB7HS 7 ++ ++#define PCIFR _SFR_IO8(0x0F) ++#define PCIF0 0 ++#define PCIF1 1 ++ ++#define T0CR _SFR_IO8(0x10) ++#define T0PS0 0 ++#define T0PS1 1 ++#define T0PS2 2 ++#define T0IE 3 ++#define T0PR 4 ++ ++#define T1CR _SFR_IO8(0x11) ++#define T1OTM 0 ++#define T1CTM 1 ++#define T1CRM 2 ++#define T1TOP 4 ++#define T1RES 5 ++#define T1TOS 6 ++#define T1ENA 7 ++ ++#define T2CR _SFR_IO8(0x12) ++#define T2OTM 0 ++#define T2CTM 1 ++#define T2CRM 2 ++#define T2TOP 4 ++#define T2RES 5 ++#define T2TOS 6 ++#define T2ENA 7 ++ ++#define T3CR _SFR_IO8(0x13) ++#define T3OTM 0 ++#define T3CTM 1 ++#define T3CRM 2 ++#define T3CPRM 3 ++#define T3TOP 4 ++#define T3RES 5 ++#define T3TOS 6 ++#define T3ENA 7 ++ ++#define T4CR _SFR_IO8(0x14) ++#define T4OTM 0 ++#define T4CTM 1 ++#define T4CRM 2 ++#define T4CPRM 3 ++#define T4TOP 4 ++#define T4RES 5 ++#define T4TOS 6 ++#define T4ENA 7 ++ ++#define T1IFR _SFR_IO8(0x15) ++#define T1OFF 0 ++#define T1COF 1 ++ ++#define T2IFR _SFR_IO8(0x16) ++#define T2OFF 0 ++#define T2COF 1 ++ ++#define T3IFR _SFR_IO8(0x17) ++#define T3OFF 0 ++#define T3COF 1 ++#define T3ICF 2 ++ ++#define T4IFR _SFR_IO8(0x18) ++#define T4OFF 0 ++#define T4COF 1 ++#define T4ICF 2 ++ ++#define T5IFR _SFR_IO8(0x19) ++#define T5OFF 0 ++#define T5COF 1 ++ ++#define GPIOR0 _SFR_IO8(0x1A) ++ ++#define GPIOR3 _SFR_IO8(0x1B) ++ ++#define GPIOR4 _SFR_IO8(0x1C) ++ ++#define GPIOR5 _SFR_IO8(0x1D) ++ ++#define GPIOR6 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++#define EEPAGE 6 ++#define NVMBSY 7 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define EEPR _SFR_IO8(0x23) ++#define EEAP0 0 ++#define EEAP1 1 ++#define EEAP2 2 ++#define EEAP3 3 ++ ++#define GPIOR1 _SFR_IO8(0x24) ++ ++#define GPIOR2 _SFR_IO8(0x25) ++ ++#define PCICR _SFR_IO8(0x26) ++#define PCIE0 0 ++#define PCIE1 1 ++ ++#define EIMSK _SFR_IO8(0x27) ++#define INT0 0 ++#define INT1 1 ++ ++#define EIFR _SFR_IO8(0x28) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define CRCDIR _SFR_IO8(0x29) ++ ++#define VMCSR _SFR_IO8(0x2A) ++#define VMLS0 0 ++#define VMLS1 1 ++#define VMLS2 2 ++#define VMLS3 3 ++#define VMIM 4 ++#define VMF 5 ++ ++#define MCUSR _SFR_IO8(0x2B) ++#define PORF 0 ++#define EXTRF 1 ++#define WDRF 3 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define RXIF 4 ++#define TXIF 5 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++#define T0IFR _SFR_IO8(0x2F) ++#define T0F 0 ++ ++/* Reserved [0x30] */ ++ ++#define DWDR _SFR_IO8(0x31) ++ ++/* Reserved [0x32] */ ++ ++#define RDCR _SFR_IO8(0x33) ++#define RDPU 0 ++#define ADIVEN 1 ++#define RDEN 2 ++ ++#define EOTSA _SFR_IO8(0x34) ++#define CARFA 0 ++#define AMPFA 1 ++#define SYTFA 2 ++#define MANFA 3 ++#define TMOFA 4 ++#define TELRA 5 ++#define RRFA 6 ++#define EOTBF 7 ++ ++#define EOTCA _SFR_IO8(0x35) ++#define CARFEA 0 ++#define AMPFEA 1 ++#define SYTFEA 2 ++#define MANFEA 3 ++#define TMOFEA 4 ++#define TELREA 5 ++#define RRFEA 6 ++#define EOTBFE 7 ++ ++#define EOTSB _SFR_IO8(0x36) ++#define CARFB 0 ++#define AMPFB 1 ++#define SYTFB 2 ++#define MANFB 3 ++#define TMOFB 4 ++#define TELRB 5 ++#define RRFB 6 ++#define EOTAF 7 ++ ++#define EOTCB _SFR_IO8(0x37) ++#define CARFEB 0 ++#define AMPFEB 1 ++#define SYTFEB 2 ++#define MANFEB 3 ++#define TMOFEB 4 ++#define TELREB 5 ++#define RRFEB 6 ++#define EOTAFE 7 ++ ++#define SMCR _SFR_IO8(0x38) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define CMCR _SFR_IO8(0x39) ++#define CMM0 0 ++#define CMM1 1 ++#define CMM2 2 ++#define CCS 3 ++#define SRCD 4 ++#define CMONEN 6 ++#define CMCCE 7 ++ ++#define CMIMR _SFR_IO8(0x3A) ++#define ECIE 0 ++ ++#define CLPR _SFR_IO8(0x3B) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLTPS0 3 ++#define CLTPS1 4 ++#define CLTPS2 5 ++#define CLPCE 7 ++ ++#define SPMCSR _SFR_IO8(0x3C) ++#define SELFPRGEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define SPMIE 7 ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define FSEN _SFR_MEM8(0x60) ++#define SDPU 0 ++#define SDEN 1 ++ ++/* Reserved [0x61..0x63] */ ++ ++#define FFREQ1L _SFR_MEM8(0x64) ++ ++#define FFREQ1M _SFR_MEM8(0x65) ++ ++#define FFREQ1H _SFR_MEM8(0x66) ++ ++#define FFREQ2L _SFR_MEM8(0x67) ++ ++#define FFREQ2M _SFR_MEM8(0x68) ++ ++#define FFREQ2H _SFR_MEM8(0x69) ++ ++/* Reserved [0x6A] */ ++ ++#define EICRA _SFR_MEM8(0x6B) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++#define PCMSK0 _SFR_MEM8(0x6C) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6D) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++ ++#define WDTCR _SFR_MEM8(0x6E) ++#define WDPS0 0 ++#define WDPS1 1 ++#define WDPS2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define T1CNT _SFR_MEM8(0x6F) ++ ++#define T1COR _SFR_MEM8(0x70) ++ ++#define T1MR _SFR_MEM8(0x71) ++#define T1CS0 0 ++#define T1CS1 1 ++#define T1PS0 2 ++#define T1PS1 3 ++#define T1PS2 4 ++#define T1PS3 5 ++#define T1DC0 6 ++#define T1DC1 7 ++ ++#define T1IMR _SFR_MEM8(0x72) ++#define T1OIM 0 ++#define T1CIM 1 ++ ++#define T2CNT _SFR_MEM8(0x73) ++ ++#define T2COR _SFR_MEM8(0x74) ++ ++#define T2MR _SFR_MEM8(0x75) ++#define T2CS0 0 ++#define T2CS1 1 ++#define T2PS0 2 ++#define T2PS1 3 ++#define T2PS2 4 ++#define T2PS3 5 ++#define T2DC0 6 ++#define T2DC1 7 ++ ++#define T2IMR _SFR_MEM8(0x76) ++#define T2OIM 0 ++#define T2CIM 1 ++ ++/* Combine T3CNTL and T3CNTH */ ++#define T3CNT _SFR_MEM16(0x77) ++ ++#define T3CNTL _SFR_MEM8(0x77) ++#define T3CNTH _SFR_MEM8(0x78) ++ ++/* Combine T3CORL and T3CORH */ ++#define T3COR _SFR_MEM16(0x79) ++ ++#define T3CORL _SFR_MEM8(0x79) ++#define T3CORH _SFR_MEM8(0x7A) ++ ++/* Combine T3ICRL and T3ICRH */ ++#define T3ICR _SFR_MEM16(0x7B) ++ ++#define T3ICRL _SFR_MEM8(0x7B) ++#define T3ICRH _SFR_MEM8(0x7C) ++ ++#define T3MRA _SFR_MEM8(0x7D) ++#define T3CS0 0 ++#define T3CS1 1 ++#define T3PS0 2 ++#define T3PS1 3 ++#define T3PS2 4 ++ ++#define T3MRB _SFR_MEM8(0x7E) ++#define T3SCE 1 ++#define T3CNC 2 ++#define T3CE0 3 ++#define T3CE1 4 ++#define T3ICS0 5 ++#define T3ICS1 6 ++#define T3ICS2 7 ++ ++#define T3IMR _SFR_MEM8(0x7F) ++#define T3OIM 0 ++#define T3CIM 1 ++#define T3CPIM 2 ++ ++/* Combine T4CNTL and T4CNTH */ ++#define T4CNT _SFR_MEM16(0x80) ++ ++#define T4CNTL _SFR_MEM8(0x80) ++#define T4CNTH _SFR_MEM8(0x81) ++ ++/* Combine T4CORL and T4CORH */ ++#define T4COR _SFR_MEM16(0x82) ++ ++#define T4CORL _SFR_MEM8(0x82) ++#define T4CORH _SFR_MEM8(0x83) ++ ++/* Combine T4ICRL and T4ICRH */ ++#define T4ICR _SFR_MEM16(0x84) ++ ++#define T4ICRL _SFR_MEM8(0x84) ++#define T4ICRH _SFR_MEM8(0x85) ++ ++#define T4MRA _SFR_MEM8(0x86) ++#define T4CS0 0 ++#define T4CS1 1 ++#define T4PS0 2 ++#define T4PS1 3 ++#define T4PS2 4 ++ ++#define T4MRB _SFR_MEM8(0x87) ++#define T4SCE 1 ++#define T4CNC 2 ++#define T4CE0 3 ++#define T4CE1 4 ++#define T4ICS0 5 ++#define T4ICS1 6 ++#define T4ICS2 7 ++ ++#define T4IMR _SFR_MEM8(0x88) ++#define T4OIM 0 ++#define T4CIM 1 ++#define T4CPIM 2 ++ ++/* Reserved [0x89] */ ++ ++/* Combine T5OCRL and T5OCRH */ ++#define T5OCR _SFR_MEM16(0x8A) ++ ++#define T5OCRL _SFR_MEM8(0x8A) ++#define T5OCRH _SFR_MEM8(0x8B) ++ ++#define T5CCR _SFR_MEM8(0x8C) ++#define T5CS0 0 ++#define T5CS1 1 ++#define T5CS2 2 ++#define T5CTC 3 ++ ++/* Combine T5CNTL and T5CNTH */ ++#define T5CNT _SFR_MEM16(0x8D) ++ ++#define T5CNTL _SFR_MEM8(0x8D) ++#define T5CNTH _SFR_MEM8(0x8E) ++ ++#define T5IMR _SFR_MEM8(0x8F) ++#define T5OIM 0 ++#define T5CIM 1 ++ ++#define GTCCR _SFR_MEM8(0x90) ++#define PSR10 0 ++#define TSM 7 ++ ++#define SOTSB _SFR_MEM8(0x91) ++#define CAROB 0 ++#define AMPOB 1 ++#define SYTOB 2 ++#define MANOB 3 ++#define WUPOB 4 ++#define SFIDOB 5 ++#define RROB 6 ++#define WCOAO 7 ++ ++#define SOTSA _SFR_MEM8(0x92) ++#define CAROA 0 ++#define AMPOA 1 ++#define SYTOA 2 ++#define MANOA 3 ++#define WUPOA 4 ++#define SFIDOA 5 ++#define RROA 6 ++#define WCOBO 7 ++ ++#define SOTCB _SFR_MEM8(0x93) ++#define CAROEB 0 ++#define AMPOEB 1 ++#define SYTOEB 2 ++#define MANOEB 3 ++#define WUPEB 4 ++#define SFIDEB 5 ++#define RROEB 6 ++#define WCOAOE 7 ++ ++#define SOTCA _SFR_MEM8(0x94) ++#define CAROEA 0 ++#define AMPOEA 1 ++#define SYTOEA 2 ++#define MANOEA 3 ++#define WUPEA 4 ++#define SFIDEA 5 ++#define RROEA 6 ++#define WCOBOE 7 ++ ++#define TESRB _SFR_MEM8(0x95) ++#define CRCOB 0 ++#define EOTLB0 1 ++#define EOTLB1 2 ++ ++#define TESRA _SFR_MEM8(0x96) ++#define CRCOA 0 ++#define EOTLA0 1 ++#define EOTLA1 2 ++ ++/* Reserved [0x97] */ ++ ++#define RDSIMR _SFR_MEM8(0x98) ++#define NBITAM 0 ++#define NBITBM 1 ++#define EOTAM 2 ++#define EOTBM 3 ++#define SOTAM 4 ++#define SOTBM 5 ++#define WCOAM 6 ++#define WCOBM 7 ++ ++#define RDOCR _SFR_MEM8(0x99) ++#define TMDS0 1 ++#define TMDS1 2 ++#define ETRPA 3 ++#define ETRPB 4 ++#define RDSIDA 5 ++#define RDSIDB 6 ++ ++/* Reserved [0x9A] */ ++ ++#define TEMPL _SFR_MEM8(0x9B) ++ ++#define TEMPH _SFR_MEM8(0x9C) ++ ++#define SYCB _SFR_MEM8(0x9D) ++#define SYCSB0 0 ++#define SYCSB1 1 ++#define SYCSB2 2 ++#define SYCSB3 3 ++#define SYTLB0 4 ++#define SYTLB1 5 ++#define SYTLB2 6 ++#define SYTLB3 7 ++ ++#define SYCA _SFR_MEM8(0x9E) ++#define SYCSA0 0 ++#define SYCSA1 1 ++#define SYCSA2 2 ++#define SYCSA3 3 ++#define SYTLA0 4 ++#define SYTLA1 5 ++#define SYTLA2 6 ++#define SYTLA3 7 ++ ++#define RXFOB _SFR_MEM8(0x9F) ++ ++#define RXFOA _SFR_MEM8(0xA0) ++ ++#define DMMB _SFR_MEM8(0xA1) ++#define DMATB0 0 ++#define DMATB1 1 ++#define DMATB2 2 ++#define DMATB3 3 ++#define DMATB4 4 ++#define DMPB 5 ++#define DMHB 6 ++#define DMNEB 7 ++ ++#define DMMA _SFR_MEM8(0xA2) ++#define DMATA0 0 ++#define DMATA1 1 ++#define DMATA2 2 ++#define DMATA3 3 ++#define DMATA4 4 ++#define DMPA 5 ++#define DMHA 6 ++#define DMNEA 7 ++ ++#define DMCDB _SFR_MEM8(0xA3) ++#define DMCLB0 0 ++#define DMCLB1 1 ++#define DMCLB2 2 ++#define DMCLB3 3 ++#define DMCLB4 4 ++#define DMCTB0 5 ++#define DMCTB1 6 ++#define DMCTB2 7 ++ ++#define DMCDA _SFR_MEM8(0xA4) ++#define DMCLA0 0 ++#define DMCLA1 1 ++#define DMCLA2 2 ++#define DMCLA3 3 ++#define DMCLA4 4 ++#define DMCTA0 5 ++#define DMCTA1 6 ++#define DMCTA2 7 ++ ++#define DMCRB _SFR_MEM8(0xA5) ++#define DMPGB0 0 ++#define DMPGB1 1 ++#define DMPGB2 2 ++#define DMPGB3 3 ++#define DMPGB4 4 ++#define SASKB 5 ++#define SY1TB 6 ++#define DMARB 7 ++ ++#define DMCRA _SFR_MEM8(0xA6) ++#define DMPGA0 0 ++#define DMPGA1 1 ++#define DMPGA2 2 ++#define DMPGA3 3 ++#define DMPGA4 4 ++#define SASKA 5 ++#define SY1TA 6 ++#define DMARA 7 ++ ++#define DMDRB _SFR_MEM8(0xA7) ++#define DMAB0 0 ++#define DMAB1 1 ++#define DMAB2 2 ++#define DMAB3 3 ++#define DMDNB0 4 ++#define DMDNB1 5 ++#define DMDNB2 6 ++#define DMDNB3 7 ++ ++#define DMDRA _SFR_MEM8(0xA8) ++#define DMAA0 0 ++#define DMAA1 1 ++#define DMAA2 2 ++#define DMAA3 3 ++#define DMDNA0 4 ++#define DMDNA1 5 ++#define DMDNA2 6 ++#define DMDNA3 7 ++ ++#define CHCR _SFR_MEM8(0xA9) ++#define BWM0 0 ++#define BWM1 1 ++#define BWM2 2 ++#define BWM3 3 ++ ++#define CHDN _SFR_MEM8(0xAA) ++#define BBDN0 0 ++#define BBDN1 1 ++#define BBDN2 2 ++#define BBDN3 3 ++#define BBDN4 4 ++#define ADCDN 5 ++ ++#define SFIDCB _SFR_MEM8(0xAB) ++#define SFIDTB0 0 ++#define SFIDTB1 1 ++#define SFIDTB2 2 ++#define SFIDTB3 3 ++#define SFIDTB4 4 ++#define SEMEB 7 ++ ++#define SFIDLB _SFR_MEM8(0xAC) ++#define SFIDLB0 0 ++#define SFIDLB1 1 ++#define SFIDLB2 2 ++#define SFIDLB3 3 ++#define SFIDLB4 4 ++#define SFIDLB5 5 ++ ++#define WUPTB _SFR_MEM8(0xAD) ++#define WUPTB0 0 ++#define WUPTB1 1 ++#define WUPTB2 2 ++#define WUPTB3 3 ++#define WUPTB4 4 ++ ++#define WUPLB _SFR_MEM8(0xAE) ++#define WUPLB0 0 ++#define WUPLB1 1 ++#define WUPLB2 2 ++#define WUPLB3 3 ++#define WUPLB4 4 ++#define WUPLB5 5 ++ ++#define SFID1B _SFR_MEM8(0xAF) ++ ++#define SFID2B _SFR_MEM8(0xB0) ++ ++#define SFID3B _SFR_MEM8(0xB1) ++ ++#define SFID4B _SFR_MEM8(0xB2) ++ ++#define WUP1B _SFR_MEM8(0xB3) ++ ++#define WUP2B _SFR_MEM8(0xB4) ++ ++#define WUP3B _SFR_MEM8(0xB5) ++ ++#define WUP4B _SFR_MEM8(0xB6) ++ ++#define SFIDCA _SFR_MEM8(0xB7) ++#define SFIDTA0 0 ++#define SFIDTA1 1 ++#define SFIDTA2 2 ++#define SFIDTA3 3 ++#define SFIDTA4 4 ++#define SEMEA 7 ++ ++#define SFIDLA _SFR_MEM8(0xB8) ++#define SFIDLA0 0 ++#define SFIDLA1 1 ++#define SFIDLA2 2 ++#define SFIDLA3 3 ++#define SFIDLA4 4 ++#define SFIDLA5 5 ++ ++#define WUPTA _SFR_MEM8(0xB9) ++#define WUPTA0 0 ++#define WUPTA1 1 ++#define WUPTA2 2 ++#define WUPTA3 3 ++#define WUPTA4 4 ++ ++#define WUPLA _SFR_MEM8(0xBA) ++#define WUPLA0 0 ++#define WUPLA1 1 ++#define WUPLA2 2 ++#define WUPLA3 3 ++#define WUPLA4 4 ++#define WUPLA5 5 ++ ++#define SFID1A _SFR_MEM8(0xBB) ++ ++#define SFID2A _SFR_MEM8(0xBC) ++ ++#define SFID3A _SFR_MEM8(0xBD) ++ ++#define SFID4A _SFR_MEM8(0xBE) ++ ++#define WUP1A _SFR_MEM8(0xBF) ++ ++#define WUP2A _SFR_MEM8(0xC0) ++ ++#define WUP3A _SFR_MEM8(0xC1) ++ ++#define WUP4A _SFR_MEM8(0xC2) ++ ++#define CLKOD _SFR_MEM8(0xC3) ++ ++#define CLKOCR _SFR_MEM8(0xC4) ++#define CLKOS0 0 ++#define CLKOS1 1 ++#define CLKOEN 2 ++ ++#define XFUSE _SFR_MEM8(0xC5) ++ ++#define SRCCAL _SFR_MEM8(0xC6) ++#define SRCCAL0 0 ++#define SRCCAL1 1 ++#define SRCCAL2 2 ++#define SRCCAL3 3 ++#define SRCCAL4 4 ++#define SRCCAL5 5 ++#define SRCTC0 6 ++#define SRCTC1 7 ++ ++#define FRCCAL _SFR_MEM8(0xC7) ++#define FRCCAL0 0 ++#define FRCCAL1 1 ++#define FRCCAL2 2 ++#define FRCCAL3 3 ++#define FRCCAL4 4 ++#define FRCTC 5 ++ ++#define CMSR _SFR_MEM8(0xC8) ++#define ECF 0 ++ ++#define CMOCR _SFR_MEM8(0xC9) ++#define FRCAO 0 ++#define SRCAO 1 ++#define FRCACT 2 ++#define SRCACT 3 ++ ++#define SUPFR _SFR_MEM8(0xCA) ++#define AVCCRF 0 ++#define AVCCLF 1 ++ ++#define SUPCR _SFR_MEM8(0xCB) ++#define AVCCRM 0 ++#define AVCCLM 1 ++#define PVEN 2 ++#define DVDIS 4 ++#define AVEN 5 ++#define AVDIC 6 ++ ++/* Reserved [0xCC] */ ++ ++#define SUPCA2 _SFR_MEM8(0xCD) ++#define BGCAL0 0 ++#define BGCAL1 1 ++#define BGCAL2 2 ++#define BGCAL3 3 ++ ++#define SUPCA3 _SFR_MEM8(0xCE) ++#define ACAL4 0 ++#define ACAL5 1 ++#define ACAL6 2 ++#define ACAL7 3 ++#define DCAL4 4 ++#define DCAL5 5 ++#define DCAL6 6 ++ ++#define SUPCA4 _SFR_MEM8(0xCF) ++#define ACAL0 0 ++#define ACAL1 1 ++#define ACAL2 2 ++#define ACAL3 3 ++#define DCAL0 4 ++#define DCAL1 5 ++#define DCAL2 6 ++#define DCAL3 7 ++ ++#define CALRDY _SFR_MEM8(0xD0) ++ ++#define VMCAL _SFR_MEM8(0xD1) ++#define VMCAL0 0 ++#define VMCAL1 1 ++#define VMCAL2 2 ++ ++#define DFS _SFR_MEM8(0xD2) ++#define DFFLRF 0 ++#define DFUFL 1 ++#define DFOFL 2 ++ ++/* Combine DFTLL and DFTLH */ ++#define DFTL _SFR_MEM16(0xD3) ++ ++#define DFTLL _SFR_MEM8(0xD3) ++#define DFTLH _SFR_MEM8(0xD4) ++ ++#define DFL _SFR_MEM8(0xD5) ++#define DFFLS0 0 ++#define DFFLS1 1 ++#define DFFLS2 2 ++#define DFFLS3 3 ++#define DFFLS4 4 ++#define DFFLS5 5 ++#define DFCLR 7 ++ ++#define DFWP _SFR_MEM8(0xD6) ++#define DFWP0 0 ++#define DFWP1 1 ++#define DFWP2 2 ++#define DFWP3 3 ++#define DFWP4 4 ++#define DFWP5 5 ++ ++#define DFRP _SFR_MEM8(0xD7) ++#define DFRP0 0 ++#define DFRP1 1 ++#define DFRP2 2 ++#define DFRP3 3 ++#define DFRP4 4 ++#define DFRP5 5 ++ ++#define DFD _SFR_MEM8(0xD8) ++ ++#define DFI _SFR_MEM8(0xD9) ++#define DFFLIM 0 ++#define DFERIM 1 ++ ++#define DFC _SFR_MEM8(0xDA) ++#define DFFLC0 0 ++#define DFFLC1 1 ++#define DFFLC2 2 ++#define DFFLC3 3 ++#define DFFLC4 4 ++#define DFFLC5 5 ++#define DFDRA 7 ++ ++#define SFS _SFR_MEM8(0xDB) ++#define SFFLRF 0 ++#define SFUFL 1 ++#define SFOFL 2 ++ ++#define SFL _SFR_MEM8(0xDC) ++#define SFFLS0 0 ++#define SFFLS1 1 ++#define SFFLS2 2 ++#define SFFLS3 3 ++#define SFFLS4 4 ++#define SFCLR 7 ++ ++#define SFWP _SFR_MEM8(0xDD) ++#define SFWP0 0 ++#define SFWP1 1 ++#define SFWP2 2 ++#define SFWP3 3 ++#define SFWP4 4 ++ ++#define SFRP _SFR_MEM8(0xDE) ++#define SFRP0 0 ++#define SFRP1 1 ++#define SFRP2 2 ++#define SFRP3 3 ++#define SFRP4 4 ++ ++#define SFD _SFR_MEM8(0xDF) ++ ++#define SFI _SFR_MEM8(0xE0) ++#define SFFLIM 0 ++#define SFERIM 1 ++ ++#define SFC _SFR_MEM8(0xE1) ++#define SFFLC0 0 ++#define SFFLC1 1 ++#define SFFLC2 2 ++#define SFFLC3 3 ++#define SFFLC4 4 ++#define SFDRA 7 ++ ++#define SSMCR _SFR_MEM8(0xE2) ++#define SSMTX 0 ++#define SSMTM 1 ++#define SSMTGE 2 ++#define SSMTPE 3 ++#define SSMPVE 4 ++#define SSMTAE 5 ++#define SETRPA 6 ++#define SETRPB 7 ++ ++#define SSMRCR _SFR_MEM8(0xE3) ++#define SSMPA 0 ++#define SSMPB 1 ++#define SSMADA 2 ++#define SSMADB 3 ++#define SSMPVS 4 ++#define SSMIFA 5 ++#define SSMIDSE 6 ++#define SSMTMOE 7 ++ ++#define SSMFBR _SFR_MEM8(0xE4) ++#define SSMFID0 0 ++#define SSMFID1 1 ++#define SSMFID2 2 ++#define SSMDFDT 3 ++#define SSMHADT 4 ++#define SSMPLDT 5 ++ ++#define SSMRR _SFR_MEM8(0xE5) ++#define SSMR 0 ++#define SSMST 1 ++ ++#define SSMSR _SFR_MEM8(0xE6) ++#define SSMESM0 0 ++#define SSMESM1 1 ++#define SSMESM2 2 ++#define SSMESM3 3 ++#define SSMERR 7 ++ ++#define SSMIFR _SFR_MEM8(0xE7) ++#define SSMIF 0 ++ ++#define SSMIMR _SFR_MEM8(0xE8) ++#define SSMIM 0 ++ ++#define MSMSTR _SFR_MEM8(0xE9) ++#define SSMMST0 0 ++#define SSMMST1 1 ++#define SSMMST2 2 ++#define SSMMST3 3 ++#define SSMMST4 4 ++ ++#define SSMSTR _SFR_MEM8(0xEA) ++#define SSMSTA0 0 ++#define SSMSTA1 1 ++#define SSMSTA2 2 ++#define SSMSTA3 3 ++#define SSMSTA4 4 ++#define SSMSTA5 5 ++ ++#define SSMXSR _SFR_MEM8(0xEB) ++#define SSMSTB0 0 ++#define SSMSTB1 1 ++#define SSMSTB2 2 ++#define SSMSTB3 3 ++#define SSMSTB4 4 ++#define SSMSTB5 5 ++ ++#define MSMCR1 _SFR_MEM8(0xEC) ++#define MSMSM00 0 ++#define MSMSM01 1 ++#define MSMSM02 2 ++#define MSMSM03 3 ++#define MSMSM10 4 ++#define MSMSM11 5 ++#define MSMSM12 6 ++#define MSMSM13 7 ++ ++#define MSMCR2 _SFR_MEM8(0xED) ++#define MSMSM20 0 ++#define MSMSM21 1 ++#define MSMSM22 2 ++#define MSMSM23 3 ++#define MSMSM30 4 ++#define MSMSM31 5 ++#define MSMSM32 6 ++#define MSMSM33 7 ++ ++#define MSMCR3 _SFR_MEM8(0xEE) ++#define MSMSM40 0 ++#define MSMSM41 1 ++#define MSMSM42 2 ++#define MSMSM43 3 ++#define MSMSM50 4 ++#define MSMSM51 5 ++#define MSMSM52 6 ++#define MSMSM53 7 ++ ++#define MSMCR4 _SFR_MEM8(0xEF) ++#define MSMSM60 0 ++#define MSMSM61 1 ++#define MSMSM62 2 ++#define MSMSM63 3 ++#define MSMSM70 4 ++#define MSMSM71 5 ++#define MSMSM72 6 ++#define MSMSM73 7 ++ ++#define GTCR _SFR_MEM8(0xF0) ++#define RXTEHA 0 ++#define GAPMA 1 ++#define DARA 2 ++#define IWUPA 3 ++#define RXTEHB 4 ++#define GAPMB 5 ++#define DARB 6 ++#define IWUPB 7 ++ ++#define SOTC1A _SFR_MEM8(0xF1) ++#define CAROEA1 0 ++#define AMPOEA1 1 ++#define SYTOEA1 2 ++#define MANOEA1 3 ++#define WUPEA1 4 ++#define SFIDEA1 5 ++#define RROEA1 6 ++#define WCOBOE1 7 ++ ++#define SOTC2A _SFR_MEM8(0xF2) ++#define CAROEA2 0 ++#define AMPOEA2 1 ++#define SYTOEA2 2 ++#define MANOEA2 3 ++#define WUPEA2 4 ++#define SFIDEA2 5 ++#define RROEA2 6 ++#define WCOBOE2 7 ++ ++#define SOTC1B _SFR_MEM8(0xF3) ++#define CAROEB1 0 ++#define AMPOEB1 1 ++#define SYTOEB1 2 ++#define MANOEB1 3 ++#define WUPEB1 4 ++#define SFIDEB1 5 ++#define RROEB1 6 ++#define WCOAOE1 7 ++ ++#define SOTC2B _SFR_MEM8(0xF4) ++#define CAROEB2 0 ++#define AMPOEB2 1 ++#define SYTOEB2 2 ++#define MANOEB2 3 ++#define WUPEB2 4 ++#define SFIDEB2 5 ++#define RROEB2 6 ++#define WCOAOE2 7 ++ ++#define EOTC1A _SFR_MEM8(0xF5) ++#define CARFEA1 0 ++#define AMPFEA1 1 ++#define SYTFEA1 2 ++#define MANFEA1 3 ++#define TMOFEA1 4 ++#define TELREA1 5 ++#define RRFEA1 6 ++#define EOTBFE1 7 ++ ++#define EOTC2A _SFR_MEM8(0xF6) ++#define CARFEA2 0 ++#define AMPFEA2 1 ++#define SYTFEA2 2 ++#define MANFEA2 3 ++#define TMOFEA2 4 ++#define TELREA2 5 ++#define RRFEA2 6 ++#define EOTBFE2 7 ++ ++#define EOTC3A _SFR_MEM8(0xF7) ++#define CARFEA3 0 ++#define AMPFEA3 1 ++#define SYTFEA3 2 ++#define MANFEA3 3 ++#define TMOFEA3 4 ++#define TELREA3 5 ++#define RRFEA3 6 ++#define EOTBFE3 7 ++ ++#define EOTC1B _SFR_MEM8(0xF8) ++#define CARFEB1 0 ++#define AMPFEB1 1 ++#define SYTFEB1 2 ++#define MANFEB1 3 ++#define TMOFEB1 4 ++#define TELREB1 5 ++#define RRFEB1 6 ++#define EOTAFE1 7 ++ ++#define EOTC2B _SFR_MEM8(0xF9) ++#define CARFEB2 0 ++#define AMPFEB2 1 ++#define SYTFEB2 2 ++#define MANFEB2 3 ++#define TMOFEB2 4 ++#define TELREB2 5 ++#define RRFEB2 6 ++#define EOTAFE2 7 ++ ++#define EOTC3B _SFR_MEM8(0xFA) ++#define CARFEB3 0 ++#define AMPFEB3 1 ++#define SYTFEB3 2 ++#define MANFEB3 3 ++#define TMOFEB3 4 ++#define TELREB3 5 ++#define RRFEB3 6 ++#define EOTAFE3 7 ++ ++#define WCOTOA _SFR_MEM8(0xFB) ++ ++#define WCOTOB _SFR_MEM8(0xFC) ++ ++#define SOTTOA _SFR_MEM8(0xFD) ++ ++#define SOTTOB _SFR_MEM8(0xFE) ++ ++#define SSMFCR _SFR_MEM8(0xFF) ++#define SSMIDSO 0 ++#define SSMIDSF 1 ++ ++#define FESR _SFR_MEM8(0x100) ++#define LBSAT 0 ++#define HBSAT 1 ++#define XRDY 2 ++#define PLCK 3 ++ ++#define FEEN1 _SFR_MEM8(0x101) ++#define PLEN 0 ++#define PLCAL 1 ++#define XTOEN 2 ++#define LNAEN 3 ++#define ADEN 4 ++#define ADCLK 5 ++#define PLSP1 6 ++#define ATEN 7 ++ ++#define FEEN2 _SFR_MEM8(0x102) ++#define SDRX 0 ++#define SDRX2 1 ++#define PAEN 2 ++#define TMPM 3 ++#define PLPEN 4 ++#define XTPEN 5 ++ ++#define FELNA _SFR_MEM8(0x103) ++#define LBH0 0 ++#define LBH1 1 ++#define LBH2 2 ++#define LBH3 3 ++#define LBL0 4 ++#define LBL1 5 ++#define LBL2 6 ++#define LBL3 7 ++ ++/* Reserved [0x104..0x105] */ ++ ++#define FEVCT _SFR_MEM8(0x106) ++#define FEVCT0 0 ++#define FEVCT1 1 ++#define FEVCT2 2 ++#define FEVCT3 3 ++ ++#define FEBT _SFR_MEM8(0x107) ++#define CTN20 0 ++#define CTN21 1 ++#define RTN20 2 ++#define RTN21 3 ++ ++#define FEMS _SFR_MEM8(0x108) ++#define PLLS0 0 ++#define PLLS1 1 ++#define PLLS2 2 ++#define PLLS3 3 ++#define PLLM0 4 ++#define PLLM1 5 ++#define PLLM2 6 ++#define PLLM3 7 ++ ++#define FETN4 _SFR_MEM8(0x109) ++#define CTN40 0 ++#define CTN41 1 ++#define CTN42 2 ++#define CTN43 3 ++#define RTN40 4 ++#define RTN41 5 ++#define RTN42 6 ++#define RTN43 7 ++ ++#define FECR _SFR_MEM8(0x10A) ++#define LBNHB 0 ++#define S4N3 1 ++#define ANDP 2 ++#define ADHS 3 ++#define PLCKG 4 ++#define ANPS 5 ++ ++#define FEVCO _SFR_MEM8(0x10B) ++#define CPCC0 0 ++#define CPCC1 1 ++#define CPCC2 2 ++#define CPCC3 3 ++#define VCOB0 4 ++#define VCOB1 5 ++#define VCOB2 6 ++#define VCOB3 7 ++ ++#define FEALR _SFR_MEM8(0x10C) ++#define RNGE0 0 ++#define RNGE1 1 ++ ++#define FEANT _SFR_MEM8(0x10D) ++#define LVLC0 0 ++#define LVLC1 1 ++#define LVLC2 2 ++#define LVLC3 3 ++ ++#define FEBIA _SFR_MEM8(0x10E) ++#define IFAEN 7 ++ ++/* Reserved [0x10F..0x12E] */ ++ ++#define RXBC1 _SFR_MEM8(0x12F) ++#define RXCEA 0 ++#define RXCBLA0 1 ++#define RXCBLA1 2 ++#define RXMSBA 3 ++#define RXCEB 4 ++#define RXCBLB0 5 ++#define RXCBLB1 6 ++#define RXMSBB 7 ++ ++#define RXBC2 _SFR_MEM8(0x130) ++#define RXBPB 0 ++#define RXBF 1 ++#define RXBCLR 2 ++ ++#define RXTLLB _SFR_MEM8(0x131) ++ ++#define RXTLHB _SFR_MEM8(0x132) ++#define RXTLHB0 0 ++#define RXTLHB1 1 ++#define RXTLHB2 2 ++#define RXTLHB3 3 ++ ++#define RXCRLB _SFR_MEM8(0x133) ++ ++#define RXCRHB _SFR_MEM8(0x134) ++ ++#define RXCSBB _SFR_MEM8(0x135) ++ ++#define RXCILB _SFR_MEM8(0x136) ++ ++#define RXCIHB _SFR_MEM8(0x137) ++ ++#define RXCPLB _SFR_MEM8(0x138) ++ ++#define RXCPHB _SFR_MEM8(0x139) ++ ++#define RXDSB _SFR_MEM8(0x13A) ++ ++#define RXTLLA _SFR_MEM8(0x13B) ++ ++#define RXTLHA _SFR_MEM8(0x13C) ++#define RXTLHA0 0 ++#define RXTLHA1 1 ++#define RXTLHA2 2 ++#define RXTLHA3 3 ++ ++#define RXCRLA _SFR_MEM8(0x13D) ++ ++#define RXCRHA _SFR_MEM8(0x13E) ++ ++#define RXCSBA _SFR_MEM8(0x13F) ++ ++#define RXCILA _SFR_MEM8(0x140) ++ ++#define RXCIHA _SFR_MEM8(0x141) ++ ++#define RXCPLA _SFR_MEM8(0x142) ++ ++#define RXCPHA _SFR_MEM8(0x143) ++ ++#define RXDSA _SFR_MEM8(0x144) ++ ++#define CRCCR _SFR_MEM8(0x145) ++#define CRCRS 0 ++#define REFLI 1 ++#define REFLO 2 ++ ++#define CRCDOR _SFR_MEM8(0x146) ++ ++#define IDB0 _SFR_MEM8(0x147) ++ ++#define IDB1 _SFR_MEM8(0x148) ++ ++#define IDB2 _SFR_MEM8(0x149) ++ ++#define IDB3 _SFR_MEM8(0x14A) ++ ++#define IDC _SFR_MEM8(0x14B) ++#define IDL0 0 ++#define IDL1 1 ++#define IDBO0 2 ++#define IDBO1 3 ++#define IDFIM 5 ++#define IDCLR 6 ++#define IDCE 7 ++ ++#define IDS _SFR_MEM8(0x14C) ++#define IDOK 0 ++#define IDFULL 1 ++ ++#define RSSAV _SFR_MEM8(0x14D) ++ ++#define RSSPK _SFR_MEM8(0x14E) ++ ++#define RSSL _SFR_MEM8(0x14F) ++ ++#define RSSH _SFR_MEM8(0x150) ++ ++#define RSSC _SFR_MEM8(0x151) ++#define RSUP0 0 ++#define RSUP1 1 ++#define RSUP2 2 ++#define RSUP3 3 ++#define RSWLH 4 ++#define RSHRX 5 ++#define RSPKF 6 ++ ++#define DBCR _SFR_MEM8(0x152) ++#define DBMD 0 ++#define DBCS 1 ++#define DBTMS 2 ++#define DBHA 3 ++ ++#define DBTC _SFR_MEM8(0x153) ++ ++#define DBENB _SFR_MEM8(0x154) ++ ++#define DBENC _SFR_MEM8(0x155) ++ ++#define DBGSW _SFR_MEM8(0x156) ++#define DBGGS0 0 ++#define DBGGS1 1 ++#define DBGGS2 2 ++#define DBGGS3 3 ++#define CPBFOS0 4 ++#define CPBFOS1 5 ++#define CPBF 6 ++#define DBGSE 7 ++ ++#define SFFR _SFR_MEM8(0x157) ++#define RFL0 0 ++#define RFL1 1 ++#define RFL2 2 ++#define RFC 3 ++#define TFL0 4 ++#define TFL1 5 ++#define TFL2 6 ++#define TFC 7 ++ ++#define SFIR _SFR_MEM8(0x158) ++#define RIL0 0 ++#define RIL1 1 ++#define RIL2 2 ++#define SRIE 3 ++#define TIL0 4 ++#define TIL1 5 ++#define TIL2 6 ++#define STIE 7 ++ ++#define EECR2 _SFR_MEM8(0x159) ++#define EEBRE 0 ++ ++#define PGMST _SFR_MEM8(0x15A) ++#define PGMSYN0 0 ++#define PGMSYN1 1 ++#define PGMSYN2 2 ++#define PGMSYN3 3 ++#define PGMSYN4 4 ++ ++#define EEST _SFR_MEM8(0x15B) ++#define EESYN0 0 ++#define EESYN1 1 ++#define EESYN2 2 ++#define EESYN3 3 ++ ++#define RSIFG _SFR_MEM8(0x15C) ++ ++#define RSLDV _SFR_MEM8(0x15D) ++ ++#define RSHDV _SFR_MEM8(0x15E) ++ ++#define RSCOM _SFR_MEM8(0x15F) ++#define RSDC 0 ++#define RSIFC 1 ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCI0_vect _VECTOR(3) ++#define PCI0_vect_num 3 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCI1_vect _VECTOR(4) ++#define PCI1_vect_num 4 ++ ++/* Voltage Monitoring Interrupt */ ++#define VMON_vect _VECTOR(5) ++#define VMON_vect_num 5 ++ ++/* AVCC Reset Interrupt */ ++#define AVCCR_vect _VECTOR(6) ++#define AVCCR_vect_num 6 ++ ++/* AVCC Low Interrupt */ ++#define AVCCL_vect _VECTOR(7) ++#define AVCCL_vect_num 7 ++ ++/* Timer 0 Interval Interrupt */ ++#define T0INT_vect _VECTOR(8) ++#define T0INT_vect_num 8 ++ ++/* Timer/Counter1 Compare Match Interrupt */ ++#define T1COMP_vect _VECTOR(9) ++#define T1COMP_vect_num 9 ++ ++/* Timer/Counter1 Overflow Interrupt */ ++#define T1OVF_vect _VECTOR(10) ++#define T1OVF_vect_num 10 ++ ++/* Timer/Counter2 Compare Match Interrupt */ ++#define T2COMP_vect _VECTOR(11) ++#define T2COMP_vect_num 11 ++ ++/* Timer/Counter2 Overflow Interrupt */ ++#define T2OVF_vect _VECTOR(12) ++#define T2OVF_vect_num 12 ++ ++/* Timer/Counter3 Capture Event Interrupt */ ++#define T3CAP_vect _VECTOR(13) ++#define T3CAP_vect_num 13 ++ ++/* Timer/Counter3 Compare Match Interrupt */ ++#define T3COMP_vect _VECTOR(14) ++#define T3COMP_vect_num 14 ++ ++/* Timer/Counter3 Overflow Interrupt */ ++#define T3OVF_vect _VECTOR(15) ++#define T3OVF_vect_num 15 ++ ++/* Timer/Counter4 Capture Event Interrupt */ ++#define T4CAP_vect _VECTOR(16) ++#define T4CAP_vect_num 16 ++ ++/* Timer/Counter4 Compare Match Interrupt */ ++#define T4COMP_vect _VECTOR(17) ++#define T4COMP_vect_num 17 ++ ++/* Timer/Counter4 Overflow Interrupt */ ++#define T4OVF_vect _VECTOR(18) ++#define T4OVF_vect_num 18 ++ ++/* Timer/Counter5 Compare Match Interrupt */ ++#define T5COMP_vect _VECTOR(19) ++#define T5COMP_vect_num 19 ++ ++/* Timer/Counter5 Overflow Interrupt */ ++#define T5OVF_vect _VECTOR(20) ++#define T5OVF_vect_num 20 ++ ++/* SPI Serial Transfer Complete Interrupt */ ++#define SPI_vect _VECTOR(21) ++#define SPI_vect_num 21 ++ ++/* SPI Rx Buffer Interrupt */ ++#define SRX_FIFO_vect _VECTOR(22) ++#define SRX_FIFO_vect_num 22 ++ ++/* SPI Tx Buffer Interrupt */ ++#define STX_FIFO_vect _VECTOR(23) ++#define STX_FIFO_vect_num 23 ++ ++/* Sequencer State Machine Interrupt */ ++#define SSM_vect _VECTOR(24) ++#define SSM_vect_num 24 ++ ++/* Data FIFO fill level reached Interrupt */ ++#define DFFLR_vect _VECTOR(25) ++#define DFFLR_vect_num 25 ++ ++/* Data FIFO overflow or underflow error Interrupt */ ++#define DFOUE_vect _VECTOR(26) ++#define DFOUE_vect_num 26 ++ ++/* RSSI/Preamble FIFO fill level reached Interrupt */ ++#define SFFLR_vect _VECTOR(27) ++#define SFFLR_vect_num 27 ++ ++/* RSSI/Preamble FIFO overflow or underflow error Interrupt */ ++#define SFOUE_vect _VECTOR(28) ++#define SFOUE_vect_num 28 ++ ++/* Tx Modulator Telegram Finish Interrupt */ ++#define TMTCF_vect _VECTOR(29) ++#define TMTCF_vect_num 29 ++ ++/* UHF receiver wake up ok on Rx path B */ ++#define UHF_WCOB_vect _VECTOR(30) ++#define UHF_WCOB_vect_num 30 ++ ++/* UHF receiver wake up ok on Rx path A */ ++#define UHF_WCOA_vect _VECTOR(31) ++#define UHF_WCOA_vect_num 31 ++ ++/* UHF receiver start of telegram ok on Rx path B */ ++#define UHF_SOTB_vect _VECTOR(32) ++#define UHF_SOTB_vect_num 32 ++ ++/* UHF receiver start of telegram ok on Rx path A */ ++#define UHF_SOTA_vect _VECTOR(33) ++#define UHF_SOTA_vect_num 33 ++ ++/* UHF receiver end of telegram on Rx path B */ ++#define UHF_EOTB_vect _VECTOR(34) ++#define UHF_EOTB_vect_num 34 ++ ++/* UHF receiver end of telegram on Rx path A */ ++#define UHF_EOTA_vect _VECTOR(35) ++#define UHF_EOTA_vect_num 35 ++ ++/* UHF receiver new bit on Rx path B */ ++#define UHF_NBITB_vect _VECTOR(36) ++#define UHF_NBITB_vect_num 36 ++ ++/* UHF receiver new bit on Rx path A */ ++#define UHF_NBITA_vect _VECTOR(37) ++#define UHF_NBITA_vect_num 37 ++ ++/* External input Clock monitoring Interrupt */ ++#define EXCM_vect _VECTOR(38) ++#define EXCM_vect_num 38 ++ ++/* EEPROM Ready Interrupt */ ++#define ERDY_vect _VECTOR(39) ++#define ERDY_vect_num 39 ++ ++/* Store Program Memory Ready */ ++#define SPMR_vect _VECTOR(40) ++#define SPMR_vect_num 40 ++ ++/* IDSCAN Full Interrupt */ ++#define IDFULL_vect _VECTOR(41) ++#define IDFULL_vect_num 41 ++ ++#define _VECTORS_SIZE 168 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 64 ++#define FLASHSTART 0x8000 ++#define FLASHEND 0xCFFF ++#define RAMSTART 0x0200 ++#define RAMSIZE 1024 ++#define RAMEND 0x05FF ++#define E2START 0 ++#define E2SIZE 1152 ++#define E2PAGESIZE 16 ++#define E2END 0x047F ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Fuse Byte */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(128) ++#define FUSE_DWEN (unsigned char)~_BV(64) ++#define FUSE_SPIEN (unsigned char)~_BV(32) ++#define FUSE_WDTON (unsigned char)~_BV(16) ++#define FUSE_EESAVE (unsigned char)~_BV(8) ++#define FUSE_BOOTRST (unsigned char)~_BV(4) ++#define FUSE_RSTDISBL (unsigned char)~_BV(2) ++#define FUSE_EXTCLKEN (unsigned char)~_BV(1) ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x66 ++ ++ ++#endif /* #ifdef _AVR_ATA5783_H_INCLUDED */ ++ +diff --git a/include/avr/ioa5790.h b/include/avr/ioa5790.h +new file mode 100644 +index 0000000..52f659d +--- /dev/null ++++ b/include/avr/ioa5790.h +@@ -0,0 +1,834 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATA5790_H_INCLUDED ++#define _AVR_ATA5790_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "ioa5790.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDRC7 7 ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC7 7 ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++/* Reserved [0x0C] */ ++ ++#define TPCR _SFR_IO8(0x0D) ++#define TPMA 0 ++#define TPMOD 1 ++#define TPMS0 2 ++#define TPMS1 3 ++#define TPMD0 4 ++#define TPMD1 5 ++#define TPPSD 6 ++#define TPD 7 ++ ++#define TPFR _SFR_IO8(0x0E) ++#define TPF 0 ++#define TPA 1 ++#define TPGAP 2 ++#define TPPSW 3 ++ ++#define CMCR _SFR_IO8(0x0F) ++#define CMM0 0 ++#define CMM1 1 ++#define SRCD 2 ++#define CO32D 3 ++#define CCS 4 ++#define ECINS 5 ++#define CMONEN 6 ++#define CMCCE 7 ++ ++#define CMSR _SFR_IO8(0x10) ++#define ECF 0 ++#define SXF 1 ++#define RTCF 2 ++ ++#define T2CR _SFR_IO8(0x11) ++#define T2OTM 0 ++#define T2CTM 1 ++#define T2CRM 2 ++#define T2GRM 3 ++#define T2TOP 4 ++#define T2RES 5 ++#define T2TS 6 ++#define T2E 7 ++ ++#define T3CR _SFR_IO8(0x12) ++#define T3OTM 0 ++#define T3CTM 1 ++#define T3CRM 2 ++#define T3CPRM 3 ++#define T3TOP 4 ++#define T3RES 5 ++#define T3CPTM 6 ++#define T3E 7 ++ ++#define AESCR _SFR_IO8(0x13) ++#define AESWK 0 ++#define AESWD 1 ++#define AESIM 2 ++#define AESD 3 ++#define AESXOR 4 ++#define AESRES 5 ++#define AESE 7 ++ ++#define AESSR _SFR_IO8(0x14) ++#define AESRF 0 ++#define AESERF 7 ++ ++#define TMIFR _SFR_IO8(0x15) ++#define TMRXF 0 ++#define TMTXF 1 ++#define TMTCF 2 ++#define TMRXS 3 ++#define TMTXS 4 ++ ++#define VMSR _SFR_IO8(0x16) ++#define VMF 0 ++ ++#define PCIFR _SFR_IO8(0x17) ++#define PCIF0 0 ++#define PCIF1 1 ++ ++#define LFFR _SFR_IO8(0x18) ++#define LFID0F 0 ++#define LFID1F 1 ++#define LFFEF 2 ++#define LFDBF 3 ++#define LFRSF 4 ++#define LFSDF 5 ++#define LFMDF 6 ++#define LFCAF 7 ++ ++#define T0IFR _SFR_IO8(0x19) ++#define T0F 0 ++ ++#define T1IFR _SFR_IO8(0x1A) ++#define T1F 0 ++ ++#define T2IFR _SFR_IO8(0x1B) ++#define T2OFF 0 ++#define T2COF 1 ++ ++#define T3IFR _SFR_IO8(0x1C) ++#define T3OFF 0 ++#define T3COF 1 ++#define T3ICF 2 ++ ++#define EIFR _SFR_IO8(0x1D) ++#define INTF0 0 ++ ++#define GPIOR _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++#define EELP 6 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define EEPR _SFR_IO8(0x23) ++#define EEAP0 0 ++#define EEAP1 1 ++#define EEAP2 2 ++#define EEAP3 3 ++ ++#define EECCR _SFR_IO8(0x24) ++#define EEL0 0 ++#define EEL1 1 ++#define EEL2 2 ++#define EEL3 3 ++ ++/* Reserved [0x25] */ ++ ++#define PCICR _SFR_IO8(0x26) ++#define PCIE0 0 ++#define PCIE1 1 ++ ++#define EIMSK _SFR_IO8(0x27) ++#define INT0 0 ++ ++#define TMDR _SFR_IO8(0x28) ++ ++#define AESDR _SFR_IO8(0x29) ++ ++#define AESKR _SFR_IO8(0x2A) ++#define AESKR0 0 ++#define AESKR1 1 ++#define AESKR2 2 ++#define AESKR3 3 ++#define AESKR4 4 ++#define AESKR5 5 ++#define AESKR6 6 ++#define AESKR7 7 ++ ++#define VMCR _SFR_IO8(0x2B) ++#define VMLS0 0 ++#define VMLS1 1 ++#define VMLS2 2 ++#define VMLS3 3 ++#define VMIM 4 ++#define VMPS 5 ++#define BODPD 6 ++#define BODLS 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++#define LFCR0 _SFR_IO8(0x2F) ++#define LFCE1 0 ++#define LFCE2 1 ++#define LFCE3 2 ++#define LFBRS 3 ++#define LFRBS 4 ++#define LFMG 5 ++#define LFVC0 6 ++#define LFVC1 7 ++ ++#define LFCR1 _SFR_IO8(0x30) ++#define LFM0 0 ++#define LFM1 1 ++#define LFFM0 2 ++#define LFFM1 3 ++#define LFRMS 4 ++#define LFRMSA 5 ++#define LFQCE 6 ++#define LFRE 7 ++ ++/* Reserved [0x31] */ ++ ++#define LFRDB _SFR_IO8(0x32) ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define TPRF 5 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++ ++#define LFSR _SFR_IO8(0x36) ++#define LFES 0 ++#define LFSD 1 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define T1CR _SFR_IO8(0x38) ++#define T1PS0 0 ++#define T1PS1 1 ++#define T1IE 2 ++#define T1CS0 3 ++#define T1CS1 4 ++#define T1E 7 ++ ++#define T0CR _SFR_IO8(0x39) ++#define T0PS0 0 ++#define T0PS1 1 ++#define T0PS2 2 ++#define T0IE 3 ++#define T0PR 4 ++ ++/* Reserved [0x3A] */ ++ ++#define CMIMR _SFR_IO8(0x3B) ++#define ECIE 0 ++#define SXIE 1 ++#define RTCIE 2 ++ ++#define CLKPR _SFR_IO8(0x3C) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLTPS0 3 ++#define CLTPS1 4 ++#define CLTPS2 5 ++#define CLKPCE 7 ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDPS0 0 ++#define WDPS1 1 ++#define WDPS2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++/* Reserved [0x61..0x62] */ ++ ++#define PRR0 _SFR_MEM8(0x63) ++#define PRLFR 0 ++#define PRT1 1 ++#define PRT2 2 ++#define PRT3 3 ++#define PRTM 4 ++#define PRCU 5 ++#define PRDS 6 ++#define PRVM 7 ++ ++#define PRR1 _SFR_MEM8(0x64) ++#define PRCI 0 ++#define PRSPI 1 ++ ++#define SRCCAL _SFR_MEM8(0x65) ++ ++#define FRCCAL _SFR_MEM8(0x66) ++ ++/* Reserved [0x67..0x68] */ ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++ ++#define PCMSK0 _SFR_MEM8(0x6A) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6B) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++/* Reserved [0x6C] */ ++ ++#define LDCR _SFR_MEM8(0x6D) ++#define LDE 0 ++#define LDCS0 1 ++#define LDCS1 2 ++ ++/* Reserved [0x6E..0x6F] */ ++ ++#define T2CNT _SFR_MEM8(0x70) ++ ++#define T2COR _SFR_MEM8(0x71) ++ ++/* Reserved [0x72] */ ++ ++#define T2MR _SFR_MEM8(0x73) ++#define T2CS0 0 ++#define T2CS1 1 ++#define T2CS2 2 ++#define T2PS0 3 ++#define T2PS1 4 ++#define T2PS2 5 ++#define T2D0 6 ++#define T2D1 7 ++ ++#define T2IMR _SFR_MEM8(0x74) ++#define T2OIM 0 ++#define T2CIM 1 ++ ++/* Reserved [0x75] */ ++ ++#define T3CNT _SFR_MEM8(0x76) ++ ++#define T3COR _SFR_MEM8(0x77) ++ ++#define T3ICR _SFR_MEM8(0x78) ++ ++#define T3MRA _SFR_MEM8(0x79) ++#define T3CS0 0 ++#define T3CS1 1 ++#define T3SCE 2 ++#define T3CE0 3 ++#define T3CE1 4 ++#define T3CNC 5 ++#define T3ICS0 6 ++#define T3ICS1 7 ++ ++#define T3MRB _SFR_MEM8(0x7A) ++#define T3PS0 0 ++#define T3PS1 1 ++#define T3PS2 2 ++ ++#define T3IMR _SFR_MEM8(0x7B) ++#define T3OIM 0 ++#define T3CIM 1 ++#define T3CPIM 2 ++ ++/* Reserved [0x7C] */ ++ ++#define TMCR _SFR_MEM8(0x7D) ++#define MI1S0 0 ++#define MI1S1 1 ++#define MI2S0 2 ++#define MI2S1 3 ++#define MI4S0 4 ++#define MI4S1 5 ++#define TMCPOL 6 ++#define TMSSIE 7 ++ ++#define TMMR _SFR_MEM8(0x7E) ++#define MOS0 0 ++#define MOS1 1 ++#define MSCS0 2 ++#define MSCS1 3 ++#define MOUTC 4 ++#define TMMS0 5 ++#define TMMS1 6 ++#define TM12S 7 ++ ++#define TMIMR _SFR_MEM8(0x7F) ++#define TMRXIM 0 ++#define TMTXIM 1 ++#define TMTCIM 2 ++ ++/* Reserved [0x80..0x81] */ ++ ++#define LFIMR _SFR_MEM8(0x82) ++#define LFID0IM 0 ++#define LFID1IM 1 ++#define LFFEIM 2 ++#define LFDBIM 3 ++#define LFRSIM 4 ++#define LFSDIM 5 ++#define LFMDIM 6 ++ ++#define LFCAD _SFR_MEM8(0x83) ++ ++#define LFID00 _SFR_MEM8(0x84) ++ ++#define LFID01 _SFR_MEM8(0x85) ++ ++#define LFID02 _SFR_MEM8(0x86) ++ ++#define LFID03 _SFR_MEM8(0x87) ++ ++#define LFID10 _SFR_MEM8(0x88) ++ ++#define LFID11 _SFR_MEM8(0x89) ++ ++#define LFID12 _SFR_MEM8(0x8A) ++ ++#define LFID13 _SFR_MEM8(0x8B) ++ ++#define LFRD0 _SFR_MEM8(0x8C) ++ ++#define LFRD1 _SFR_MEM8(0x8D) ++ ++#define LFRD2 _SFR_MEM8(0x8E) ++ ++#define LFRD3 _SFR_MEM8(0x8F) ++ ++#define LFID0M _SFR_MEM8(0x90) ++#define ID0FS0 0 ++#define ID0FS1 1 ++#define ID0FS2 2 ++#define ID0FS3 3 ++#define ID0FS4 4 ++#define ID0E 7 ++ ++#define LFID1M _SFR_MEM8(0x91) ++#define ID1FS0 0 ++#define ID1FS1 1 ++#define ID1FS2 2 ++#define ID1FS3 3 ++#define ID1FS4 4 ++#define ID1E 7 ++ ++#define LFRDF _SFR_MEM8(0x92) ++#define RDFS0 0 ++#define RDFS1 1 ++#define RDFS2 2 ++#define RDFS3 3 ++#define RDFS4 4 ++#define RDFE 7 ++ ++#define LFRSD1 _SFR_MEM8(0x93) ++ ++#define LFRSD2 _SFR_MEM8(0x94) ++ ++#define LFRSD3 _SFR_MEM8(0x95) ++ ++#define LFCC1 _SFR_MEM8(0x96) ++ ++#define LFCC2 _SFR_MEM8(0x97) ++ ++#define LFCC3 _SFR_MEM8(0x98) ++ ++/* Reserved [0x99..0x9B] */ ++ ++#define TPIMR _SFR_MEM8(0x9C) ++#define TPIM 0 ++ ++/* Reserved [0x9D] */ ++ ++#define RTCCR _SFR_MEM8(0x9E) ++#define RTCR 0 ++ ++#define RTCDR _SFR_MEM8(0x9F) ++ ++/* Reserved [0xA0..0xA7] */ ++ ++#define TMMDR _SFR_MEM8(0xA8) ++ ++#define TMBDR _SFR_MEM8(0xA9) ++ ++#define TMTDR _SFR_MEM8(0xAA) ++ ++#define TMSR _SFR_MEM8(0xAB) ++ ++/* Reserved [0xAC] */ ++ ++#define CRCDR _SFR_MEM8(0xAD) ++ ++#define CRCCR _SFR_MEM8(0xAE) ++#define CRCN0 0 ++#define CRCN1 1 ++#define CRCN2 2 ++#define CRCSEL 3 ++#define REFLI 4 ++#define REFLO 5 ++#define CRCRS 7 ++ ++#define CRCSR _SFR_MEM8(0xAF) ++#define CRCBF 0 ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* Transponder Mode Interrupt */ ++#define TPINT_vect _VECTOR(1) ++#define TPINT_vect_num 1 ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(2) ++#define INT0_vect_num 2 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(3) ++#define PCINT0_vect_num 3 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(4) ++#define PCINT1_vect_num 4 ++ ++/* Voltage Monitoring Interrupt */ ++#define VMINT_vect _VECTOR(5) ++#define VMINT_vect_num 5 ++ ++/* Timer0 Interval Interrupt */ ++#define T0INT_vect _VECTOR(6) ++#define T0INT_vect_num 6 ++ ++/* LF-Receiver Identifier 0 Interrupt */ ++#define LFID0INT_vect _VECTOR(7) ++#define LFID0INT_vect_num 7 ++ ++/* LF-Receiver Identifier 1 Interrupt */ ++#define LFID1INT_vect _VECTOR(8) ++#define LFID1INT_vect_num 8 ++ ++/* LF-Receiver Frame End Interrupt */ ++#define LFFEINT_vect _VECTOR(9) ++#define LFFEINT_vect_num 9 ++ ++/* LF-Receiver Data Buffer full Interrupt */ ++#define LFDBINT_vect _VECTOR(10) ++#define LFDBINT_vect_num 10 ++ ++/* Timer/Counter3 Capture Event Interrupt */ ++#define T3CAPINT_vect _VECTOR(11) ++#define T3CAPINT_vect_num 11 ++ ++/* Timer/Counter3 Compare Match Interrupt */ ++#define T3COMINT_vect _VECTOR(12) ++#define T3COMINT_vect_num 12 ++ ++/* Timer/Counter3 Overflow Interrupt */ ++#define T3OVFINT_vect _VECTOR(13) ++#define T3OVFINT_vect_num 13 ++ ++/* Timer/Counter2 Compare Match Interrupt */ ++#define T2COMINT_vect _VECTOR(14) ++#define T2COMINT_vect_num 14 ++ ++/* Timer/Counter2 Overflow Interrupt */ ++#define T2OVFINT_vect _VECTOR(15) ++#define T2OVFINT_vect_num 15 ++ ++/* Timer 1 Interval Interrupt */ ++#define T1INT_vect _VECTOR(16) ++#define T1INT_vect_num 16 ++ ++/* SPI Serial Transfer Complete Interrupt */ ++#define SPISTC_vect _VECTOR(17) ++#define SPISTC_vect_num 17 ++ ++/* Timer Modulator SSI Receive Buffer Interrupt */ ++#define TMRXBINT_vect _VECTOR(18) ++#define TMRXBINT_vect_num 18 ++ ++/* Timer Modulator SSI Transmit Buffer Interrupt */ ++#define TMTXBINT_vect _VECTOR(19) ++#define TMTXBINT_vect_num 19 ++ ++/* Timer Modulator Transmit Complete Interrupt */ ++#define TMTXCINT_vect _VECTOR(20) ++#define TMTXCINT_vect_num 20 ++ ++/* AES Interrupt */ ++#define AESINT_vect _VECTOR(21) ++#define AESINT_vect_num 21 ++ ++/* LF-Receiver RSSi measurement Interrupt */ ++#define LFRSSINT_vect _VECTOR(22) ++#define LFRSSINT_vect_num 22 ++ ++/* LF-Receiver Signal Detect Interrupt */ ++#define LFSDINT_vect _VECTOR(23) ++#define LFSDINT_vect_num 23 ++ ++/* LF-Receiver Manchester Decoder error Interrupt */ ++#define LFMDINT_vect _VECTOR(24) ++#define LFMDINT_vect_num 24 ++ ++/* External Input Clock Monitoring Interrupt */ ++#define EXCMINT_vect _VECTOR(25) ++#define EXCMINT_vect_num 25 ++ ++/* External XTAL Oscillator Break Down Interrupt */ ++#define EXXMINT_vect _VECTOR(26) ++#define EXXMINT_vect_num 26 ++ ++/* Real Time Clock Interrupt */ ++#define RTCINT_vect _VECTOR(27) ++#define RTCINT_vect_num 27 ++ ++/* EEPROM Ready Interrupt */ ++#define EEREADY_vect _VECTOR(28) ++#define EEREADY_vect_num 28 ++ ++/* Store Program Memory Ready */ ++#define SPMREADY_vect _VECTOR(29) ++#define SPMREADY_vect_num 29 ++ ++#define _VECTORS_SIZE 120 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 128 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x3FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 512 ++#define RAMEND 0x02FF ++#define E2START 0 ++#define E2SIZE 2048 ++#define E2PAGESIZE 16 ++#define E2END 0x07FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Fuse Byte */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(128) ++#define FUSE_DWEN (unsigned char)~_BV(64) ++#define FUSE_SPIEN (unsigned char)~_BV(32) ++#define FUSE_WDTON (unsigned char)~_BV(16) ++#define FUSE_EESAVE (unsigned char)~_BV(8) ++#define FUSE_Reserved (unsigned char)~_BV(4) ++#define FUSE__32OEN (unsigned char)~_BV(2) ++#define FUSE_EXTCLKEN (unsigned char)~_BV(1) ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x61 ++ ++ ++#endif /* #ifdef _AVR_ATA5790_H_INCLUDED */ ++ +diff --git a/include/avr/ioa5790n.h b/include/avr/ioa5790n.h +new file mode 100644 +index 0000000..a09f375 +--- /dev/null ++++ b/include/avr/ioa5790n.h +@@ -0,0 +1,850 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATA5790N_H_INCLUDED ++#define _AVR_ATA5790N_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "ioa5790n.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDRC7 7 ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC7 7 ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++#define T3CR2 _SFR_IO8(0x0C) ++#define T3GRES 0 ++#define T3C2TM 1 ++#define T3C2RM 2 ++ ++#define TPCR _SFR_IO8(0x0D) ++#define TPMA 0 ++#define TPMOD 1 ++#define TPMS0 2 ++#define TPMS1 3 ++#define TPMD0 4 ++#define TPMD1 5 ++#define TPPSD 6 ++#define TPD 7 ++ ++#define TPFR _SFR_IO8(0x0E) ++#define TPF 0 ++#define TPA 1 ++#define TPGAP 2 ++#define TPPSW 3 ++ ++#define CMCR _SFR_IO8(0x0F) ++#define CMM0 0 ++#define CMM1 1 ++#define SRCD 2 ++#define CO32D 3 ++#define CCS 4 ++#define ECINS 5 ++#define CMONEN 6 ++#define CMCCE 7 ++ ++#define CMSR _SFR_IO8(0x10) ++#define ECF 0 ++#define SXF 1 ++#define RTCF 2 ++ ++#define T2CR _SFR_IO8(0x11) ++#define T2OTM 0 ++#define T2CTM 1 ++#define T2CRM 2 ++#define T2GRM 3 ++#define T2TOP 4 ++#define T2RES 5 ++#define T2TS 6 ++#define T2E 7 ++ ++#define T3CR _SFR_IO8(0x12) ++#define T3OTM 0 ++#define T3CTM 1 ++#define T3CRM 2 ++#define T3CPRM 3 ++#define T3TOP 4 ++#define T3RES 5 ++#define T3CPTM 6 ++#define T3E 7 ++ ++#define AESCR _SFR_IO8(0x13) ++#define AESWK 0 ++#define AESWD 1 ++#define AESIM 2 ++#define AESD 3 ++#define AESXOR 4 ++#define AESRES 5 ++#define AESE 7 ++ ++#define AESSR _SFR_IO8(0x14) ++#define AESRF 0 ++#define AESERF 7 ++ ++#define TMIFR _SFR_IO8(0x15) ++#define TMRXF 0 ++#define TMTXF 1 ++#define TMTCF 2 ++#define TMRXS 3 ++#define TMTXS 4 ++ ++#define VMSR _SFR_IO8(0x16) ++#define VMF 0 ++ ++#define PCIFR _SFR_IO8(0x17) ++#define PCIF0 0 ++#define PCIF1 1 ++ ++#define LFFR _SFR_IO8(0x18) ++#define LFID0F 0 ++#define LFID1F 1 ++#define LFFEF 2 ++#define LFDBF 3 ++#define LFRSF 4 ++#define LFSDF 5 ++#define LFMDF 6 ++#define LFCAF 7 ++ ++#define T0IFR _SFR_IO8(0x19) ++#define T0F 0 ++ ++#define T1IFR _SFR_IO8(0x1A) ++#define T1F 0 ++ ++#define T2IFR _SFR_IO8(0x1B) ++#define T2OFF 0 ++#define T2COF 1 ++ ++#define T3IFR _SFR_IO8(0x1C) ++#define T3OFF 0 ++#define T3COF 1 ++#define T3ICF 2 ++#define T3CO2F 3 ++ ++#define EIFR _SFR_IO8(0x1D) ++#define INTF0 0 ++ ++#define GPIOR _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++#define EELP 6 ++#define NVMBSY 7 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define EEPR _SFR_IO8(0x23) ++#define EEAP0 0 ++#define EEAP1 1 ++#define EEAP2 2 ++#define EEAP3 3 ++ ++#define EECCR _SFR_IO8(0x24) ++#define EEL0 0 ++#define EEL1 1 ++#define EEL2 2 ++#define EEL3 3 ++ ++#define EECR2 _SFR_IO8(0x25) ++#define EEBRE 0 ++#define EEPAGE 1 ++ ++#define PCICR _SFR_IO8(0x26) ++#define PCIE0 0 ++#define PCIE1 1 ++ ++#define EIMSK _SFR_IO8(0x27) ++#define INT0 0 ++ ++#define TMDR _SFR_IO8(0x28) ++ ++#define AESDR _SFR_IO8(0x29) ++ ++#define AESKR _SFR_IO8(0x2A) ++#define AESKR0 0 ++#define AESKR1 1 ++#define AESKR2 2 ++#define AESKR3 3 ++#define AESKR4 4 ++#define AESKR5 5 ++#define AESKR6 6 ++#define AESKR7 7 ++ ++#define VMCR _SFR_IO8(0x2B) ++#define VMLS0 0 ++#define VMLS1 1 ++#define VMLS2 2 ++#define VMLS3 3 ++#define VMIM 4 ++#define VMPS 5 ++#define BODPD 6 ++#define BODLS 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++#define LFCR0 _SFR_IO8(0x2F) ++#define LFCE1 0 ++#define LFCE2 1 ++#define LFCE3 2 ++#define LFBRS 3 ++#define LFRBS 4 ++#define LFMG 5 ++#define LFVC0 6 ++#define LFVC1 7 ++ ++#define LFCR1 _SFR_IO8(0x30) ++#define LFM0 0 ++#define LFM1 1 ++#define LFFM0 2 ++#define LFFM1 3 ++#define LFRMS 4 ++#define LFRMSA 5 ++#define LFQCE 6 ++#define LFRE 7 ++ ++/* Reserved [0x31] */ ++ ++#define LFRDB _SFR_IO8(0x32) ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define TPRF 5 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++ ++#define LFSR _SFR_IO8(0x36) ++#define LFES 0 ++#define LFSD 1 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define T1CR _SFR_IO8(0x38) ++#define T1PS0 0 ++#define T1PS1 1 ++#define T1IE 2 ++#define T1CS0 3 ++#define T1CS1 4 ++#define T1E 7 ++ ++#define T0CR _SFR_IO8(0x39) ++#define T0PS0 0 ++#define T0PS1 1 ++#define T0PS2 2 ++#define T0IE 3 ++#define T0PR 4 ++ ++/* Reserved [0x3A] */ ++ ++#define CMIMR _SFR_IO8(0x3B) ++#define ECIE 0 ++#define SXIE 1 ++#define RTCIE 2 ++ ++#define CLKPR _SFR_IO8(0x3C) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLTPS0 3 ++#define CLTPS1 4 ++#define CLTPS2 5 ++#define CLKPCE 7 ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDPS0 0 ++#define WDPS1 1 ++#define WDPS2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++/* Reserved [0x61..0x62] */ ++ ++#define PRR0 _SFR_MEM8(0x63) ++#define PRLFR 0 ++#define PRT1 1 ++#define PRT2 2 ++#define PRT3 3 ++#define PRTM 4 ++#define PRCU 5 ++#define PRDS 6 ++#define PRVM 7 ++ ++#define PRR1 _SFR_MEM8(0x64) ++#define PRCI 0 ++#define PRSPI 1 ++ ++#define SRCCAL _SFR_MEM8(0x65) ++ ++#define FRCCAL _SFR_MEM8(0x66) ++ ++/* Reserved [0x67..0x68] */ ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++ ++#define PCMSK0 _SFR_MEM8(0x6A) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6B) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++/* Reserved [0x6C] */ ++ ++#define LDCR _SFR_MEM8(0x6D) ++#define LDE 0 ++#define LDCS0 1 ++#define LDCS1 2 ++ ++/* Reserved [0x6E..0x6F] */ ++ ++#define T2CNT _SFR_MEM8(0x70) ++ ++#define T2COR _SFR_MEM8(0x71) ++ ++/* Reserved [0x72] */ ++ ++#define T2MR _SFR_MEM8(0x73) ++#define T2CS0 0 ++#define T2CS1 1 ++#define T2CS2 2 ++#define T2PS0 3 ++#define T2PS1 4 ++#define T2PS2 5 ++#define T2D0 6 ++#define T2D1 7 ++ ++#define T2IMR _SFR_MEM8(0x74) ++#define T2OIM 0 ++#define T2CIM 1 ++ ++#define T3CO2R _SFR_MEM8(0x75) ++ ++#define T3CNT _SFR_MEM8(0x76) ++ ++#define T3COR _SFR_MEM8(0x77) ++ ++#define T3ICR _SFR_MEM8(0x78) ++ ++#define T3MRA _SFR_MEM8(0x79) ++#define T3CS0 0 ++#define T3CS1 1 ++#define T3SCE 2 ++#define T3CE0 3 ++#define T3CE1 4 ++#define T3CNC 5 ++#define T3ICS0 6 ++#define T3ICS1 7 ++ ++#define T3MRB _SFR_MEM8(0x7A) ++#define T3PS0 0 ++#define T3PS1 1 ++#define T3PS2 2 ++ ++#define T3IMR _SFR_MEM8(0x7B) ++#define T3OIM 0 ++#define T3CIM 1 ++#define T3CPIM 2 ++#define T3C2IM 3 ++ ++/* Reserved [0x7C] */ ++ ++#define TMCR _SFR_MEM8(0x7D) ++#define MI1S0 0 ++#define MI1S1 1 ++#define MI2S0 2 ++#define MI2S1 3 ++#define MI4S0 4 ++#define MI4S1 5 ++#define TMCPOL 6 ++#define TMSSIE 7 ++ ++#define TMMR _SFR_MEM8(0x7E) ++#define MOS0 0 ++#define MOS1 1 ++#define MSCS0 2 ++#define MSCS1 3 ++#define MOUTC 4 ++#define TMMS0 5 ++#define TMMS1 6 ++#define TM12S 7 ++ ++#define TMIMR _SFR_MEM8(0x7F) ++#define TMRXIM 0 ++#define TMTXIM 1 ++#define TMTCIM 2 ++ ++/* Reserved [0x80..0x81] */ ++ ++#define LFIMR _SFR_MEM8(0x82) ++#define LFID0IM 0 ++#define LFID1IM 1 ++#define LFFEIM 2 ++#define LFDBIM 3 ++#define LFRSIM 4 ++#define LFSDIM 5 ++#define LFMDIM 6 ++ ++#define LFCAD _SFR_MEM8(0x83) ++ ++#define LFID00 _SFR_MEM8(0x84) ++ ++#define LFID01 _SFR_MEM8(0x85) ++ ++#define LFID02 _SFR_MEM8(0x86) ++ ++#define LFID03 _SFR_MEM8(0x87) ++ ++#define LFID10 _SFR_MEM8(0x88) ++ ++#define LFID11 _SFR_MEM8(0x89) ++ ++#define LFID12 _SFR_MEM8(0x8A) ++ ++#define LFID13 _SFR_MEM8(0x8B) ++ ++#define LFRD0 _SFR_MEM8(0x8C) ++ ++#define LFRD1 _SFR_MEM8(0x8D) ++ ++#define LFRD2 _SFR_MEM8(0x8E) ++ ++#define LFRD3 _SFR_MEM8(0x8F) ++ ++#define LFID0M _SFR_MEM8(0x90) ++#define ID0FS0 0 ++#define ID0FS1 1 ++#define ID0FS2 2 ++#define ID0FS3 3 ++#define ID0FS4 4 ++#define ID0E 7 ++ ++#define LFID1M _SFR_MEM8(0x91) ++#define ID1FS0 0 ++#define ID1FS1 1 ++#define ID1FS2 2 ++#define ID1FS3 3 ++#define ID1FS4 4 ++#define ID1E 7 ++ ++#define LFRDF _SFR_MEM8(0x92) ++#define RDFS0 0 ++#define RDFS1 1 ++#define RDFS2 2 ++#define RDFS3 3 ++#define RDFS4 4 ++#define RDFE 7 ++ ++#define LFRSD1 _SFR_MEM8(0x93) ++ ++#define LFRSD2 _SFR_MEM8(0x94) ++ ++#define LFRSD3 _SFR_MEM8(0x95) ++ ++#define LFCC1 _SFR_MEM8(0x96) ++ ++#define LFCC2 _SFR_MEM8(0x97) ++ ++#define LFCC3 _SFR_MEM8(0x98) ++ ++#define LFQCR _SFR_MEM8(0x99) ++#define LFQCLL 0 ++ ++/* Reserved [0x9A..0x9B] */ ++ ++#define TPIMR _SFR_MEM8(0x9C) ++#define TPIM 0 ++ ++/* Reserved [0x9D] */ ++ ++#define RTCCR _SFR_MEM8(0x9E) ++#define RTCR 0 ++ ++#define RTCDR _SFR_MEM8(0x9F) ++ ++/* Reserved [0xA0..0xA7] */ ++ ++#define TMMDR _SFR_MEM8(0xA8) ++ ++#define TMBDR _SFR_MEM8(0xA9) ++ ++#define TMTDR _SFR_MEM8(0xAA) ++ ++#define TMSR _SFR_MEM8(0xAB) ++ ++#define CRCPOL _SFR_MEM8(0xAC) ++ ++#define CRCDR _SFR_MEM8(0xAD) ++ ++#define CRCCR _SFR_MEM8(0xAE) ++#define CRCN0 0 ++#define CRCN1 1 ++#define CRCN2 2 ++#define CRCSEL 3 ++#define REFLI 4 ++#define REFLO 5 ++#define STVAL 6 ++#define CRCRS 7 ++ ++#define CRCSR _SFR_MEM8(0xAF) ++#define CRCBF 0 ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* Transponder Mode Interrupt */ ++#define TPINT_vect _VECTOR(1) ++#define TPINT_vect_num 1 ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(2) ++#define INT0_vect_num 2 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(3) ++#define PCINT0_vect_num 3 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(4) ++#define PCINT1_vect_num 4 ++ ++/* Voltage Monitoring Interrupt */ ++#define VMINT_vect _VECTOR(5) ++#define VMINT_vect_num 5 ++ ++/* Timer0 Interval Interrupt */ ++#define T0INT_vect _VECTOR(6) ++#define T0INT_vect_num 6 ++ ++/* LF-Receiver Identifier 0 Interrupt */ ++#define LFID0INT_vect _VECTOR(7) ++#define LFID0INT_vect_num 7 ++ ++/* LF-Receiver Identifier 1 Interrupt */ ++#define LFID1INT_vect _VECTOR(8) ++#define LFID1INT_vect_num 8 ++ ++/* LF-Receiver Frame End Interrupt */ ++#define LFFEINT_vect _VECTOR(9) ++#define LFFEINT_vect_num 9 ++ ++/* LF-Receiver Data Buffer full Interrupt */ ++#define LFDBINT_vect _VECTOR(10) ++#define LFDBINT_vect_num 10 ++ ++/* Timer/Counter3 Capture Event Interrupt */ ++#define T3CAPINT_vect _VECTOR(11) ++#define T3CAPINT_vect_num 11 ++ ++/* Timer/Counter3 Compare Match Interrupt */ ++#define T3COMINT_vect _VECTOR(12) ++#define T3COMINT_vect_num 12 ++ ++/* Timer/Counter3 Overflow Interrupt */ ++#define T3OVFINT_vect _VECTOR(13) ++#define T3OVFINT_vect_num 13 ++ ++/* Timer/Counter3 Compare Match 2 Interrupt */ ++#define T3COM2INT_vect _VECTOR(14) ++#define T3COM2INT_vect_num 14 ++ ++/* Timer/Counter2 Compare Match Interrupt */ ++#define T2COMINT_vect _VECTOR(15) ++#define T2COMINT_vect_num 15 ++ ++/* Timer/Counter2 Overflow Interrupt */ ++#define T2OVFINT_vect _VECTOR(16) ++#define T2OVFINT_vect_num 16 ++ ++/* Timer 1 Interval Interrupt */ ++#define T1INT_vect _VECTOR(17) ++#define T1INT_vect_num 17 ++ ++/* SPI Serial Transfer Complete Interrupt */ ++#define SPISTC_vect _VECTOR(18) ++#define SPISTC_vect_num 18 ++ ++/* Timer Modulator SSI Receive Buffer Interrupt */ ++#define TMRXBINT_vect _VECTOR(19) ++#define TMRXBINT_vect_num 19 ++ ++/* Timer Modulator SSI Transmit Buffer Interrupt */ ++#define TMTXBINT_vect _VECTOR(20) ++#define TMTXBINT_vect_num 20 ++ ++/* Timer Modulator Transmit Complete Interrupt */ ++#define TMTXCINT_vect _VECTOR(21) ++#define TMTXCINT_vect_num 21 ++ ++/* AES Interrupt */ ++#define AESINT_vect _VECTOR(22) ++#define AESINT_vect_num 22 ++ ++/* LF-Receiver RSSi measurement Interrupt */ ++#define LFRSSINT_vect _VECTOR(23) ++#define LFRSSINT_vect_num 23 ++ ++/* LF-Receiver Signal Detect Interrupt */ ++#define LFSDINT_vect _VECTOR(24) ++#define LFSDINT_vect_num 24 ++ ++/* LF-Receiver Manchester Decoder error Interrupt */ ++#define LFMDINT_vect _VECTOR(25) ++#define LFMDINT_vect_num 25 ++ ++/* External Input Clock Monitoring Interrupt */ ++#define EXCMINT_vect _VECTOR(26) ++#define EXCMINT_vect_num 26 ++ ++/* External XTAL Oscillator Break Down Interrupt */ ++#define EXXMINT_vect _VECTOR(27) ++#define EXXMINT_vect_num 27 ++ ++/* Real Time Clock Interrupt */ ++#define RTCINT_vect _VECTOR(28) ++#define RTCINT_vect_num 28 ++ ++/* EEPROM Ready Interrupt */ ++#define EEREADY_vect _VECTOR(29) ++#define EEREADY_vect_num 29 ++ ++/* Store Program Memory Ready */ ++#define SPMREADY_vect _VECTOR(30) ++#define SPMREADY_vect_num 30 ++ ++#define _VECTORS_SIZE 124 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 128 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x3FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 512 ++#define RAMEND 0x02FF ++#define E2START 0 ++#define E2SIZE 2048 ++#define E2PAGESIZE 16 ++#define E2END 0x07FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Fuse Byte */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(128) ++#define FUSE_DWEN (unsigned char)~_BV(64) ++#define FUSE_SPIEN (unsigned char)~_BV(32) ++#define FUSE_WDTON (unsigned char)~_BV(16) ++#define FUSE_EESAVE (unsigned char)~_BV(8) ++#define FUSE_Reserved (unsigned char)~_BV(4) ++#define FUSE__32OEN (unsigned char)~_BV(2) ++#define FUSE_EXTCLKEN (unsigned char)~_BV(1) ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x62 ++ ++ ++#endif /* #ifdef _AVR_ATA5790N_H_INCLUDED */ ++ +diff --git a/include/avr/ioa5795.h b/include/avr/ioa5795.h +new file mode 100644 +index 0000000..8988c5a +--- /dev/null ++++ b/include/avr/ioa5795.h +@@ -0,0 +1,691 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATA5795_H_INCLUDED ++#define _AVR_ATA5795_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "ioa5795.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++/* Reserved [0x0C] */ ++ ++#define TPCR _SFR_IO8(0x0D) ++#define TPMA 0 ++#define TPMOD 1 ++#define TPMS0 2 ++#define TPMS1 3 ++#define TPMD0 4 ++#define TPMD1 5 ++#define TPPSD 6 ++#define TPD 7 ++ ++#define TPFR _SFR_IO8(0x0E) ++#define TPF 0 ++#define TPA 1 ++#define TPGAP 2 ++#define TPPSW 3 ++ ++#define CMCR _SFR_IO8(0x0F) ++#define CMM0 0 ++#define CMM1 1 ++#define SRCD 2 ++#define CO32D 3 ++#define CCS 4 ++#define ECINS 5 ++#define CMONEN 6 ++#define CMCCE 7 ++ ++#define CMSR _SFR_IO8(0x10) ++#define ECF 0 ++#define SXF 1 ++#define RTCF 2 ++ ++#define T2CR _SFR_IO8(0x11) ++#define T2OTM 0 ++#define T2CTM 1 ++#define T2CRM 2 ++#define T2GRM 3 ++#define T2TOP 4 ++#define T2RES 5 ++#define T2TS 6 ++#define T2E 7 ++ ++#define T3CR _SFR_IO8(0x12) ++#define T3OTM 0 ++#define T3CTM 1 ++#define T3CRM 2 ++#define T3CPRM 3 ++#define T3TOP 4 ++#define T3RES 5 ++#define T3CPTM 6 ++#define T3E 7 ++ ++#define AESCR _SFR_IO8(0x13) ++#define AESWK 0 ++#define AESWD 1 ++#define AESIM 2 ++#define AESD 3 ++#define AESXOR 4 ++#define AESRES 5 ++#define AESE 7 ++ ++#define AESSR _SFR_IO8(0x14) ++#define AESRF 0 ++#define AESERF 7 ++ ++#define TMIFR _SFR_IO8(0x15) ++#define TMRXF 0 ++#define TMTXF 1 ++#define TMTCF 2 ++#define TMRXS 3 ++#define TMTXS 4 ++ ++#define VMSR _SFR_IO8(0x16) ++#define VMF 0 ++ ++#define PCIFR _SFR_IO8(0x17) ++#define PCIF0 0 ++#define PCIF1 1 ++ ++/* Reserved [0x18] */ ++ ++#define T0IFR _SFR_IO8(0x19) ++#define T0F 0 ++ ++#define T1IFR _SFR_IO8(0x1A) ++#define T1F 0 ++ ++#define T2IFR _SFR_IO8(0x1B) ++#define T2OFF 0 ++#define T2COF 1 ++ ++#define T3IFR _SFR_IO8(0x1C) ++#define T3OFF 0 ++#define T3COF 1 ++#define T3ICF 2 ++ ++#define EIFR _SFR_IO8(0x1D) ++#define INTF0 0 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++#define EELP 6 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define EEPR _SFR_IO8(0x23) ++#define EEAP0 0 ++#define EEAP1 1 ++#define EEAP2 2 ++#define EEAP3 3 ++ ++#define EECCR _SFR_IO8(0x24) ++#define EEL0 0 ++#define EEL1 1 ++#define EEL2 2 ++#define EEL3 3 ++ ++/* Reserved [0x25] */ ++ ++#define PCICR _SFR_IO8(0x26) ++#define PCIE0 0 ++#define PCIE1 1 ++ ++#define EIMSK _SFR_IO8(0x27) ++#define INT0 0 ++ ++#define TMDR _SFR_IO8(0x28) ++ ++#define AESDR _SFR_IO8(0x29) ++ ++#define AESKR _SFR_IO8(0x2A) ++#define AESKR0 0 ++#define AESKR1 1 ++#define AESKR2 2 ++#define AESKR3 3 ++#define AESKR4 4 ++#define AESKR5 5 ++#define AESKR6 6 ++#define AESKR7 7 ++ ++#define VMCR _SFR_IO8(0x2B) ++#define VMLS0 0 ++#define VMLS1 1 ++#define VMLS2 2 ++#define VMLS3 3 ++#define VMIM 4 ++#define VMPS 5 ++#define BODPD 6 ++#define BODLS 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F..0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define TPRF 5 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define T1CR _SFR_IO8(0x38) ++#define T1PS0 0 ++#define T1PS1 1 ++#define T1IE 2 ++#define T1CS0 3 ++#define T1CS1 4 ++#define T1E 7 ++ ++#define T0CR _SFR_IO8(0x39) ++#define T0PS0 0 ++#define T0PS1 1 ++#define T0PS2 2 ++#define T0IE 3 ++#define T0PR 4 ++ ++/* Reserved [0x3A] */ ++ ++#define CMIMR _SFR_IO8(0x3B) ++#define ECIE 0 ++#define SXIE 1 ++#define RTCIE 2 ++ ++#define CLKPR _SFR_IO8(0x3C) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLTPS0 3 ++#define CLTPS1 4 ++#define CLTPS2 5 ++#define CLKPCE 7 ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDPS0 0 ++#define WDPS1 1 ++#define WDPS2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++/* Reserved [0x61..0x62] */ ++ ++#define PRR0 _SFR_MEM8(0x63) ++#define PRT1 1 ++#define PRT2 2 ++#define PRT3 3 ++#define PRTM 4 ++#define PRCU 5 ++#define PRDS 6 ++#define PRVM 7 ++ ++#define PRR1 _SFR_MEM8(0x64) ++#define PRCI 0 ++#define PRSPI 1 ++ ++#define SRCCAL _SFR_MEM8(0x65) ++ ++#define FRCCAL _SFR_MEM8(0x66) ++ ++/* Reserved [0x67..0x68] */ ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++ ++#define PCMSK0 _SFR_MEM8(0x6A) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6B) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++/* Reserved [0x6C] */ ++ ++#define LDCR _SFR_MEM8(0x6D) ++#define LDE 0 ++#define LDCS0 1 ++#define LDCS1 2 ++ ++/* Reserved [0x6E..0x6F] */ ++ ++#define T2CNT _SFR_MEM8(0x70) ++ ++#define T2COR _SFR_MEM8(0x71) ++ ++/* Reserved [0x72] */ ++ ++#define T2MR _SFR_MEM8(0x73) ++#define T2CS0 0 ++#define T2CS1 1 ++#define T2CS2 2 ++#define T2PS0 3 ++#define T2PS1 4 ++#define T2PS2 5 ++#define T2D0 6 ++#define T2D1 7 ++ ++#define T2IMR _SFR_MEM8(0x74) ++#define T2OIM 0 ++#define T2CIM 1 ++ ++/* Reserved [0x75] */ ++ ++#define T3CNT _SFR_MEM8(0x76) ++ ++#define T3COR _SFR_MEM8(0x77) ++ ++#define T3ICR _SFR_MEM8(0x78) ++ ++#define T3MRA _SFR_MEM8(0x79) ++#define T3CS0 0 ++#define T3CS1 1 ++#define T3SCE 2 ++#define T3CE0 3 ++#define T3CE1 4 ++#define T3CNC 5 ++#define T3ICS0 6 ++#define T3ICS1 7 ++ ++#define T3MRB _SFR_MEM8(0x7A) ++#define T3PS0 0 ++#define T3PS1 1 ++#define T3PS2 2 ++ ++#define T3IMR _SFR_MEM8(0x7B) ++#define T3OIM 0 ++#define T3CIM 1 ++#define T3CPIM 2 ++ ++/* Reserved [0x7C] */ ++ ++#define TMCR _SFR_MEM8(0x7D) ++#define MI1S0 0 ++#define MI1S1 1 ++#define MI2S0 2 ++#define MI2S1 3 ++#define MI4S0 4 ++#define MI4S1 5 ++#define TMCPOL 6 ++#define TMSSIE 7 ++ ++#define TMMR _SFR_MEM8(0x7E) ++#define MOS0 0 ++#define MOS1 1 ++#define MSCS0 2 ++#define MSCS1 3 ++#define MOUTC 4 ++#define TMMS0 5 ++#define TMMS1 6 ++#define TM12S 7 ++ ++#define TMIMR _SFR_MEM8(0x7F) ++#define TMRXIM 0 ++#define TMTXIM 1 ++#define TMTCIM 2 ++ ++/* Reserved [0x80..0x9B] */ ++ ++#define TPIMR _SFR_MEM8(0x9C) ++#define TPIM 0 ++ ++/* Reserved [0x9D] */ ++ ++#define RTCCR _SFR_MEM8(0x9E) ++#define RTCR 0 ++ ++#define RTCDR _SFR_MEM8(0x9F) ++ ++/* Reserved [0xA0..0xA7] */ ++ ++#define TMMDR _SFR_MEM8(0xA8) ++ ++#define TMBDR _SFR_MEM8(0xA9) ++ ++#define TMTDR _SFR_MEM8(0xAA) ++ ++#define TMSR _SFR_MEM8(0xAB) ++ ++/* Reserved [0xAC] */ ++ ++#define CRCDR _SFR_MEM8(0xAD) ++ ++#define CRCCR _SFR_MEM8(0xAE) ++#define CRCN0 0 ++#define CRCN1 1 ++#define CRCN2 2 ++#define CRCSEL 3 ++#define REFLI 4 ++#define REFLO 5 ++#define CRCRS 7 ++ ++#define CRCSR _SFR_MEM8(0xAF) ++#define CRCBF 0 ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* Transponder Mode Interrupt */ ++#define TPINT_vect _VECTOR(2) ++#define TPINT_vect_num 2 ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(4) ++#define INT0_vect_num 4 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(6) ++#define PCINT0_vect_num 6 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(8) ++#define PCINT1_vect_num 8 ++ ++/* Voltage Monitor Interrupt */ ++#define VMINT_vect _VECTOR(10) ++#define VMINT_vect_num 10 ++ ++/* Timer0 Interval Interrupt */ ++#define T0INT_vect _VECTOR(12) ++#define T0INT_vect_num 12 ++ ++/* Timer3 Capture Interrupt */ ++#define T3CAPINT_vect _VECTOR(14) ++#define T3CAPINT_vect_num 14 ++ ++/* Timer3 Compare Match Interrupt */ ++#define T3COMINT_vect _VECTOR(16) ++#define T3COMINT_vect_num 16 ++ ++/* Timer3 Overflow Interrupt */ ++#define T3OVFINT_vect _VECTOR(18) ++#define T3OVFINT_vect_num 18 ++ ++/* Timer2 Compare Match Interrupt */ ++#define T2COMINT_vect _VECTOR(20) ++#define T2COMINT_vect_num 20 ++ ++/* Timer2 Overflow Interrupt */ ++#define T2OVFINT_vect _VECTOR(22) ++#define T2OVFINT_vect_num 22 ++ ++/* Timer1 Interval Interrupt */ ++#define T1INT_vect _VECTOR(24) ++#define T1INT_vect_num 24 ++ ++/* SPI Serial Transfer Complete */ ++#define SPISTC_vect _VECTOR(26) ++#define SPISTC_vect_num 26 ++ ++/* Timer Modulator SSI Receive Buffer Interrupt */ ++#define TMRXBINT_vect _VECTOR(28) ++#define TMRXBINT_vect_num 28 ++ ++/* Timer Modulator SSI Transmit Buffer Interrupt */ ++#define TMTXBINT_vect _VECTOR(30) ++#define TMTXBINT_vect_num 30 ++ ++/* Timer Modulator Transmit Complete Interrupt */ ++#define TMTXCINT_vect _VECTOR(32) ++#define TMTXCINT_vect_num 32 ++ ++/* AES Interrupt */ ++#define AESINT_vect _VECTOR(34) ++#define AESINT_vect_num 34 ++ ++/* External Input Clock Monitoring Interrupt */ ++#define EXCMINT_vect _VECTOR(36) ++#define EXCMINT_vect_num 36 ++ ++/* External XTAL Oscillator Break Down Interrupt */ ++#define EXXMINT_vect _VECTOR(38) ++#define EXXMINT_vect_num 38 ++ ++/* Real Time Clock Interrupt */ ++#define RTCINT_vect _VECTOR(40) ++#define RTCINT_vect_num 40 ++ ++/* EEPROM Ready Interrupt */ ++#define EEREADY_vect _VECTOR(42) ++#define EEREADY_vect_num 42 ++ ++/* Store Program Memory Ready */ ++#define SPMREADY_vect _VECTOR(44) ++#define SPMREADY_vect_num 44 ++ ++#define _VECTORS_SIZE 90 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 64 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x1FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 512 ++#define RAMEND 0x02FF ++#define E2START 0 ++#define E2SIZE 2048 ++#define E2PAGESIZE 16 ++#define E2END 0x07FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Fuse Byte */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(128) ++#define FUSE_DWEN (unsigned char)~_BV(64) ++#define FUSE_SPIEN (unsigned char)~_BV(32) ++#define FUSE_WDTON (unsigned char)~_BV(16) ++#define FUSE_EESAVE (unsigned char)~_BV(8) ++#define FUSE_Reserved (unsigned char)~_BV(4) ++#define FUSE__32OEN (unsigned char)~_BV(2) ++#define FUSE_EXTCLKEN (unsigned char)~_BV(1) ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x61 ++ ++ ++#endif /* #ifdef _AVR_ATA5795_H_INCLUDED */ ++ +diff --git a/include/avr/ioa5831.h b/include/avr/ioa5831.h +new file mode 100644 +index 0000000..c681681 +--- /dev/null ++++ b/include/avr/ioa5831.h +@@ -0,0 +1,1885 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATA5831_H_INCLUDED ++#define _AVR_ATA5831_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "ioa5831.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PRR0 _SFR_IO8(0x01) ++#define PRSPI 0 ++#define PRRXDC 1 ++#define PRTXDC 2 ++#define PRCRC 3 ++#define PRVM 4 ++#define PRCO 5 ++ ++#define PRR1 _SFR_IO8(0x02) ++#define PRT1 0 ++#define PRT2 1 ++#define PRT3 2 ++#define PRT4 3 ++#define PRT5 4 ++ ++#define PRR2 _SFR_IO8(0x03) ++#define PRXB 0 ++#define PRXA 1 ++#define PRSF 2 ++#define PRDF 3 ++#define PRIDS 4 ++#define PRRS 5 ++#define PRTM 6 ++#define PRSSM 7 ++ ++#define RDPR _SFR_IO8(0x04) ++#define PRPTB 0 ++#define PRPTA 1 ++#define PRFLT 2 ++#define PRTMP 3 ++#define APRPTB 4 ++#define APRPTA 5 ++#define ARDPRF 6 ++#define RDPRF 7 ++ ++#define PINB _SFR_IO8(0x05) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x06) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x07) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x08) ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x09) ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x0A) ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define FSCR _SFR_IO8(0x0B) ++#define TXMOD 0 ++#define SFM 1 ++#define TXMS0 2 ++#define TXMS1 3 ++#define PAOER 4 ++#define PAON 7 ++ ++/* Reserved [0x0C] */ ++ ++#define RDSIFR _SFR_IO8(0x0D) ++#define NBITA 0 ++#define NBITB 1 ++#define EOTA 2 ++#define EOTB 3 ++#define SOTA 4 ++#define SOTB 5 ++#define WCOA 6 ++#define WCOB 7 ++ ++#define MCUCR _SFR_IO8(0x0E) ++#define IVCE 0 ++#define IVSEL 1 ++#define SPIIO 2 ++#define ENPS 3 ++#define PUD 4 ++#define PB4HS 5 ++#define PB7LS 6 ++#define PB7HS 7 ++ ++#define PCIFR _SFR_IO8(0x0F) ++#define PCIF0 0 ++#define PCIF1 1 ++ ++#define T0CR _SFR_IO8(0x10) ++#define T0PS0 0 ++#define T0PS1 1 ++#define T0PS2 2 ++#define T0IE 3 ++#define T0PR 4 ++ ++#define T1CR _SFR_IO8(0x11) ++#define T1OTM 0 ++#define T1CTM 1 ++#define T1CRM 2 ++#define T1TOP 4 ++#define T1RES 5 ++#define T1TOS 6 ++#define T1ENA 7 ++ ++#define T2CR _SFR_IO8(0x12) ++#define T2OTM 0 ++#define T2CTM 1 ++#define T2CRM 2 ++#define T2TOP 4 ++#define T2RES 5 ++#define T2TOS 6 ++#define T2ENA 7 ++ ++#define T3CR _SFR_IO8(0x13) ++#define T3OTM 0 ++#define T3CTM 1 ++#define T3CRM 2 ++#define T3CPRM 3 ++#define T3TOP 4 ++#define T3RES 5 ++#define T3TOS 6 ++#define T3ENA 7 ++ ++#define T4CR _SFR_IO8(0x14) ++#define T4OTM 0 ++#define T4CTM 1 ++#define T4CRM 2 ++#define T4CPRM 3 ++#define T4TOP 4 ++#define T4RES 5 ++#define T4TOS 6 ++#define T4ENA 7 ++ ++#define T1IFR _SFR_IO8(0x15) ++#define T1OFF 0 ++#define T1COF 1 ++ ++#define T2IFR _SFR_IO8(0x16) ++#define T2OFF 0 ++#define T2COF 1 ++ ++#define T3IFR _SFR_IO8(0x17) ++#define T3OFF 0 ++#define T3COF 1 ++#define T3ICF 2 ++ ++#define T4IFR _SFR_IO8(0x18) ++#define T4OFF 0 ++#define T4COF 1 ++#define T4ICF 2 ++ ++#define T5IFR _SFR_IO8(0x19) ++#define T5OFF 0 ++#define T5COF 1 ++ ++#define GPIOR0 _SFR_IO8(0x1A) ++ ++#define GPIOR3 _SFR_IO8(0x1B) ++ ++#define GPIOR4 _SFR_IO8(0x1C) ++ ++#define GPIOR5 _SFR_IO8(0x1D) ++ ++#define GPIOR6 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++#define EEPAGE 6 ++#define NVMBSY 7 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define EEPR _SFR_IO8(0x23) ++#define EEAP0 0 ++#define EEAP1 1 ++#define EEAP2 2 ++#define EEAP3 3 ++ ++#define GPIOR1 _SFR_IO8(0x24) ++ ++#define GPIOR2 _SFR_IO8(0x25) ++ ++#define PCICR _SFR_IO8(0x26) ++#define PCIE0 0 ++#define PCIE1 1 ++ ++#define EIMSK _SFR_IO8(0x27) ++#define INT0 0 ++#define INT1 1 ++ ++#define EIFR _SFR_IO8(0x28) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define CRCDIR _SFR_IO8(0x29) ++ ++#define VMCSR _SFR_IO8(0x2A) ++#define VMLS0 0 ++#define VMLS1 1 ++#define VMLS2 2 ++#define VMLS3 3 ++#define VMIM 4 ++#define VMF 5 ++ ++#define MCUSR _SFR_IO8(0x2B) ++#define PORF 0 ++#define EXTRF 1 ++#define WDRF 3 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define RXIF 4 ++#define TXIF 5 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++#define T0IFR _SFR_IO8(0x2F) ++#define T0F 0 ++ ++/* Reserved [0x30] */ ++ ++#define DWDR _SFR_IO8(0x31) ++ ++/* Reserved [0x32] */ ++ ++#define RDCR _SFR_IO8(0x33) ++#define RDPU 0 ++#define ADIVEN 1 ++#define RDEN 2 ++ ++#define EOTSA _SFR_IO8(0x34) ++#define CARFA 0 ++#define AMPFA 1 ++#define SYTFA 2 ++#define MANFA 3 ++#define TMOFA 4 ++#define TELRA 5 ++#define RRFA 6 ++#define EOTBF 7 ++ ++#define EOTCA _SFR_IO8(0x35) ++#define CARFEA 0 ++#define AMPFEA 1 ++#define SYTFEA 2 ++#define MANFEA 3 ++#define TMOFEA 4 ++#define TELREA 5 ++#define RRFEA 6 ++#define EOTBFE 7 ++ ++#define EOTSB _SFR_IO8(0x36) ++#define CARFB 0 ++#define AMPFB 1 ++#define SYTFB 2 ++#define MANFB 3 ++#define TMOFB 4 ++#define TELRB 5 ++#define RRFB 6 ++#define EOTAF 7 ++ ++#define EOTCB _SFR_IO8(0x37) ++#define CARFEB 0 ++#define AMPFEB 1 ++#define SYTFEB 2 ++#define MANFEB 3 ++#define TMOFEB 4 ++#define TELREB 5 ++#define RRFEB 6 ++#define EOTAFE 7 ++ ++#define SMCR _SFR_IO8(0x38) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define CMCR _SFR_IO8(0x39) ++#define CMM0 0 ++#define CMM1 1 ++#define CMM2 2 ++#define CCS 3 ++#define SRCD 4 ++#define CMONEN 6 ++#define CMCCE 7 ++ ++#define CMIMR _SFR_IO8(0x3A) ++#define ECIE 0 ++ ++#define CLPR _SFR_IO8(0x3B) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLTPS0 3 ++#define CLTPS1 4 ++#define CLTPS2 5 ++#define CLPCE 7 ++ ++#define SPMCSR _SFR_IO8(0x3C) ++#define SELFPRGEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define SPMIE 7 ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define FSEN _SFR_MEM8(0x60) ++#define SDPU 0 ++#define SDEN 1 ++#define GAEN 2 ++#define PEEN 3 ++#define ASEN 4 ++#define ANTT 5 ++ ++#define FSFCR _SFR_MEM8(0x61) ++#define BTSEL0 0 ++#define BTSEL1 1 ++#define ASDIV0 4 ++#define ASDIV1 5 ++#define ASDIV2 6 ++#define ASDIV3 7 ++ ++/* Combine GACDIVL and GACDIVH */ ++#define GACDIV _SFR_MEM16(0x62) ++ ++#define GACDIVL _SFR_MEM8(0x62) ++#define GACDIVH _SFR_MEM8(0x63) ++ ++#define FFREQ1L _SFR_MEM8(0x64) ++ ++#define FFREQ1M _SFR_MEM8(0x65) ++ ++#define FFREQ1H _SFR_MEM8(0x66) ++ ++#define FFREQ2L _SFR_MEM8(0x67) ++ ++#define FFREQ2M _SFR_MEM8(0x68) ++ ++#define FFREQ2H _SFR_MEM8(0x69) ++ ++/* Reserved [0x6A] */ ++ ++#define EICRA _SFR_MEM8(0x6B) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++#define PCMSK0 _SFR_MEM8(0x6C) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6D) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++ ++#define WDTCR _SFR_MEM8(0x6E) ++#define WDPS0 0 ++#define WDPS1 1 ++#define WDPS2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define T1CNT _SFR_MEM8(0x6F) ++ ++#define T1COR _SFR_MEM8(0x70) ++ ++#define T1MR _SFR_MEM8(0x71) ++#define T1CS0 0 ++#define T1CS1 1 ++#define T1PS0 2 ++#define T1PS1 3 ++#define T1PS2 4 ++#define T1PS3 5 ++#define T1DC0 6 ++#define T1DC1 7 ++ ++#define T1IMR _SFR_MEM8(0x72) ++#define T1OIM 0 ++#define T1CIM 1 ++ ++#define T2CNT _SFR_MEM8(0x73) ++ ++#define T2COR _SFR_MEM8(0x74) ++ ++#define T2MR _SFR_MEM8(0x75) ++#define T2CS0 0 ++#define T2CS1 1 ++#define T2PS0 2 ++#define T2PS1 3 ++#define T2PS2 4 ++#define T2PS3 5 ++#define T2DC0 6 ++#define T2DC1 7 ++ ++#define T2IMR _SFR_MEM8(0x76) ++#define T2OIM 0 ++#define T2CIM 1 ++ ++/* Combine T3CNTL and T3CNTH */ ++#define T3CNT _SFR_MEM16(0x77) ++ ++#define T3CNTL _SFR_MEM8(0x77) ++#define T3CNTH _SFR_MEM8(0x78) ++ ++/* Combine T3CORL and T3CORH */ ++#define T3COR _SFR_MEM16(0x79) ++ ++#define T3CORL _SFR_MEM8(0x79) ++#define T3CORH _SFR_MEM8(0x7A) ++ ++/* Combine T3ICRL and T3ICRH */ ++#define T3ICR _SFR_MEM16(0x7B) ++ ++#define T3ICRL _SFR_MEM8(0x7B) ++#define T3ICRH _SFR_MEM8(0x7C) ++ ++#define T3MRA _SFR_MEM8(0x7D) ++#define T3CS0 0 ++#define T3CS1 1 ++#define T3PS0 2 ++#define T3PS1 3 ++#define T3PS2 4 ++ ++#define T3MRB _SFR_MEM8(0x7E) ++#define T3SCE 1 ++#define T3CNC 2 ++#define T3CE0 3 ++#define T3CE1 4 ++#define T3ICS0 5 ++#define T3ICS1 6 ++#define T3ICS2 7 ++ ++#define T3IMR _SFR_MEM8(0x7F) ++#define T3OIM 0 ++#define T3CIM 1 ++#define T3CPIM 2 ++ ++/* Combine T4CNTL and T4CNTH */ ++#define T4CNT _SFR_MEM16(0x80) ++ ++#define T4CNTL _SFR_MEM8(0x80) ++#define T4CNTH _SFR_MEM8(0x81) ++ ++/* Combine T4CORL and T4CORH */ ++#define T4COR _SFR_MEM16(0x82) ++ ++#define T4CORL _SFR_MEM8(0x82) ++#define T4CORH _SFR_MEM8(0x83) ++ ++/* Combine T4ICRL and T4ICRH */ ++#define T4ICR _SFR_MEM16(0x84) ++ ++#define T4ICRL _SFR_MEM8(0x84) ++#define T4ICRH _SFR_MEM8(0x85) ++ ++#define T4MRA _SFR_MEM8(0x86) ++#define T4CS0 0 ++#define T4CS1 1 ++#define T4PS0 2 ++#define T4PS1 3 ++#define T4PS2 4 ++ ++#define T4MRB _SFR_MEM8(0x87) ++#define T4SCE 1 ++#define T4CNC 2 ++#define T4CE0 3 ++#define T4CE1 4 ++#define T4ICS0 5 ++#define T4ICS1 6 ++#define T4ICS2 7 ++ ++#define T4IMR _SFR_MEM8(0x88) ++#define T4OIM 0 ++#define T4CIM 1 ++#define T4CPIM 2 ++ ++/* Reserved [0x89] */ ++ ++/* Combine T5OCRL and T5OCRH */ ++#define T5OCR _SFR_MEM16(0x8A) ++ ++#define T5OCRL _SFR_MEM8(0x8A) ++#define T5OCRH _SFR_MEM8(0x8B) ++ ++#define T5CCR _SFR_MEM8(0x8C) ++#define T5CS0 0 ++#define T5CS1 1 ++#define T5CS2 2 ++#define T5CTC 3 ++ ++/* Combine T5CNTL and T5CNTH */ ++#define T5CNT _SFR_MEM16(0x8D) ++ ++#define T5CNTL _SFR_MEM8(0x8D) ++#define T5CNTH _SFR_MEM8(0x8E) ++ ++#define T5IMR _SFR_MEM8(0x8F) ++#define T5OIM 0 ++#define T5CIM 1 ++ ++#define GTCCR _SFR_MEM8(0x90) ++#define PSR10 0 ++#define TSM 7 ++ ++#define SOTSB _SFR_MEM8(0x91) ++#define CAROB 0 ++#define AMPOB 1 ++#define SYTOB 2 ++#define MANOB 3 ++#define WUPOB 4 ++#define SFIDOB 5 ++#define RROB 6 ++#define WCOAO 7 ++ ++#define SOTSA _SFR_MEM8(0x92) ++#define CAROA 0 ++#define AMPOA 1 ++#define SYTOA 2 ++#define MANOA 3 ++#define WUPOA 4 ++#define SFIDOA 5 ++#define RROA 6 ++#define WCOBO 7 ++ ++#define SOTCB _SFR_MEM8(0x93) ++#define CAROEB 0 ++#define AMPOEB 1 ++#define SYTOEB 2 ++#define MANOEB 3 ++#define WUPEB 4 ++#define SFIDEB 5 ++#define RROEB 6 ++#define WCOAOE 7 ++ ++#define SOTCA _SFR_MEM8(0x94) ++#define CAROEA 0 ++#define AMPOEA 1 ++#define SYTOEA 2 ++#define MANOEA 3 ++#define WUPEA 4 ++#define SFIDEA 5 ++#define RROEA 6 ++#define WCOBOE 7 ++ ++#define TESRB _SFR_MEM8(0x95) ++#define CRCOB 0 ++#define EOTLB0 1 ++#define EOTLB1 2 ++ ++#define TESRA _SFR_MEM8(0x96) ++#define CRCOA 0 ++#define EOTLA0 1 ++#define EOTLA1 2 ++ ++/* Reserved [0x97] */ ++ ++#define RDSIMR _SFR_MEM8(0x98) ++#define NBITAM 0 ++#define NBITBM 1 ++#define EOTAM 2 ++#define EOTBM 3 ++#define SOTAM 4 ++#define SOTBM 5 ++#define WCOAM 6 ++#define WCOBM 7 ++ ++#define RDOCR _SFR_MEM8(0x99) ++#define TMDS0 1 ++#define TMDS1 2 ++#define ETRPA 3 ++#define ETRPB 4 ++#define RDSIDA 5 ++#define RDSIDB 6 ++ ++/* Reserved [0x9A] */ ++ ++#define TEMPL _SFR_MEM8(0x9B) ++ ++#define TEMPH _SFR_MEM8(0x9C) ++ ++#define SYCB _SFR_MEM8(0x9D) ++#define SYCSB0 0 ++#define SYCSB1 1 ++#define SYCSB2 2 ++#define SYCSB3 3 ++#define SYTLB0 4 ++#define SYTLB1 5 ++#define SYTLB2 6 ++#define SYTLB3 7 ++ ++#define SYCA _SFR_MEM8(0x9E) ++#define SYCSA0 0 ++#define SYCSA1 1 ++#define SYCSA2 2 ++#define SYCSA3 3 ++#define SYTLA0 4 ++#define SYTLA1 5 ++#define SYTLA2 6 ++#define SYTLA3 7 ++ ++#define RXFOB _SFR_MEM8(0x9F) ++ ++#define RXFOA _SFR_MEM8(0xA0) ++ ++#define DMMB _SFR_MEM8(0xA1) ++#define DMATB0 0 ++#define DMATB1 1 ++#define DMATB2 2 ++#define DMATB3 3 ++#define DMATB4 4 ++#define DMPB 5 ++#define DMHB 6 ++#define DMNEB 7 ++ ++#define DMMA _SFR_MEM8(0xA2) ++#define DMATA0 0 ++#define DMATA1 1 ++#define DMATA2 2 ++#define DMATA3 3 ++#define DMATA4 4 ++#define DMPA 5 ++#define DMHA 6 ++#define DMNEA 7 ++ ++#define DMCDB _SFR_MEM8(0xA3) ++#define DMCLB0 0 ++#define DMCLB1 1 ++#define DMCLB2 2 ++#define DMCLB3 3 ++#define DMCLB4 4 ++#define DMCTB0 5 ++#define DMCTB1 6 ++#define DMCTB2 7 ++ ++#define DMCDA _SFR_MEM8(0xA4) ++#define DMCLA0 0 ++#define DMCLA1 1 ++#define DMCLA2 2 ++#define DMCLA3 3 ++#define DMCLA4 4 ++#define DMCTA0 5 ++#define DMCTA1 6 ++#define DMCTA2 7 ++ ++#define DMCRB _SFR_MEM8(0xA5) ++#define DMPGB0 0 ++#define DMPGB1 1 ++#define DMPGB2 2 ++#define DMPGB3 3 ++#define DMPGB4 4 ++#define SASKB 5 ++#define SY1TB 6 ++#define DMARB 7 ++ ++#define DMCRA _SFR_MEM8(0xA6) ++#define DMPGA0 0 ++#define DMPGA1 1 ++#define DMPGA2 2 ++#define DMPGA3 3 ++#define DMPGA4 4 ++#define SASKA 5 ++#define SY1TA 6 ++#define DMARA 7 ++ ++#define DMDRB _SFR_MEM8(0xA7) ++#define DMAB0 0 ++#define DMAB1 1 ++#define DMAB2 2 ++#define DMAB3 3 ++#define DMDNB0 4 ++#define DMDNB1 5 ++#define DMDNB2 6 ++#define DMDNB3 7 ++ ++#define DMDRA _SFR_MEM8(0xA8) ++#define DMAA0 0 ++#define DMAA1 1 ++#define DMAA2 2 ++#define DMAA3 3 ++#define DMDNA0 4 ++#define DMDNA1 5 ++#define DMDNA2 6 ++#define DMDNA3 7 ++ ++#define CHCR _SFR_MEM8(0xA9) ++#define BWM0 0 ++#define BWM1 1 ++#define BWM2 2 ++#define BWM3 3 ++ ++#define CHDN _SFR_MEM8(0xAA) ++#define BBDN0 0 ++#define BBDN1 1 ++#define BBDN2 2 ++#define BBDN3 3 ++#define BBDN4 4 ++#define ADCDN 5 ++ ++#define SFIDCB _SFR_MEM8(0xAB) ++#define SFIDTB0 0 ++#define SFIDTB1 1 ++#define SFIDTB2 2 ++#define SFIDTB3 3 ++#define SFIDTB4 4 ++#define SEMEB 7 ++ ++#define SFIDLB _SFR_MEM8(0xAC) ++#define SFIDLB0 0 ++#define SFIDLB1 1 ++#define SFIDLB2 2 ++#define SFIDLB3 3 ++#define SFIDLB4 4 ++#define SFIDLB5 5 ++ ++#define WUPTB _SFR_MEM8(0xAD) ++#define WUPTB0 0 ++#define WUPTB1 1 ++#define WUPTB2 2 ++#define WUPTB3 3 ++#define WUPTB4 4 ++ ++#define WUPLB _SFR_MEM8(0xAE) ++#define WUPLB0 0 ++#define WUPLB1 1 ++#define WUPLB2 2 ++#define WUPLB3 3 ++#define WUPLB4 4 ++#define WUPLB5 5 ++ ++#define SFID1B _SFR_MEM8(0xAF) ++ ++#define SFID2B _SFR_MEM8(0xB0) ++ ++#define SFID3B _SFR_MEM8(0xB1) ++ ++#define SFID4B _SFR_MEM8(0xB2) ++ ++#define WUP1B _SFR_MEM8(0xB3) ++ ++#define WUP2B _SFR_MEM8(0xB4) ++ ++#define WUP3B _SFR_MEM8(0xB5) ++ ++#define WUP4B _SFR_MEM8(0xB6) ++ ++#define SFIDCA _SFR_MEM8(0xB7) ++#define SFIDTA0 0 ++#define SFIDTA1 1 ++#define SFIDTA2 2 ++#define SFIDTA3 3 ++#define SFIDTA4 4 ++#define SEMEA 7 ++ ++#define SFIDLA _SFR_MEM8(0xB8) ++#define SFIDLA0 0 ++#define SFIDLA1 1 ++#define SFIDLA2 2 ++#define SFIDLA3 3 ++#define SFIDLA4 4 ++#define SFIDLA5 5 ++ ++#define WUPTA _SFR_MEM8(0xB9) ++#define WUPTA0 0 ++#define WUPTA1 1 ++#define WUPTA2 2 ++#define WUPTA3 3 ++#define WUPTA4 4 ++ ++#define WUPLA _SFR_MEM8(0xBA) ++#define WUPLA0 0 ++#define WUPLA1 1 ++#define WUPLA2 2 ++#define WUPLA3 3 ++#define WUPLA4 4 ++#define WUPLA5 5 ++ ++#define SFID1A _SFR_MEM8(0xBB) ++ ++#define SFID2A _SFR_MEM8(0xBC) ++ ++#define SFID3A _SFR_MEM8(0xBD) ++ ++#define SFID4A _SFR_MEM8(0xBE) ++ ++#define WUP1A _SFR_MEM8(0xBF) ++ ++#define WUP2A _SFR_MEM8(0xC0) ++ ++#define WUP3A _SFR_MEM8(0xC1) ++ ++#define WUP4A _SFR_MEM8(0xC2) ++ ++#define CLKOD _SFR_MEM8(0xC3) ++ ++#define CLKOCR _SFR_MEM8(0xC4) ++#define CLKOS0 0 ++#define CLKOS1 1 ++#define CLKOEN 2 ++ ++#define XFUSE _SFR_MEM8(0xC5) ++ ++#define SRCCAL _SFR_MEM8(0xC6) ++#define SRCCAL0 0 ++#define SRCCAL1 1 ++#define SRCCAL2 2 ++#define SRCCAL3 3 ++#define SRCCAL4 4 ++#define SRCCAL5 5 ++#define SRCTC0 6 ++#define SRCTC1 7 ++ ++#define FRCCAL _SFR_MEM8(0xC7) ++#define FRCCAL0 0 ++#define FRCCAL1 1 ++#define FRCCAL2 2 ++#define FRCCAL3 3 ++#define FRCCAL4 4 ++#define FRCTC 5 ++ ++#define CMSR _SFR_MEM8(0xC8) ++#define ECF 0 ++ ++#define CMOCR _SFR_MEM8(0xC9) ++#define FRCAO 0 ++#define SRCAO 1 ++#define FRCACT 2 ++#define SRCACT 3 ++ ++#define SUPFR _SFR_MEM8(0xCA) ++#define AVCCRF 0 ++#define AVCCLF 1 ++ ++#define SUPCR _SFR_MEM8(0xCB) ++#define AVCCRM 0 ++#define AVCCLM 1 ++#define PVEN 2 ++#define DVDIS 4 ++#define AVEN 5 ++#define AVDIC 6 ++ ++#define SUPCA1 _SFR_MEM8(0xCC) ++#define PV22 2 ++#define PVDIC 3 ++#define PVCAL0 4 ++#define PVCAL1 5 ++#define PVCAL2 6 ++#define PVCAL3 7 ++ ++#define SUPCA2 _SFR_MEM8(0xCD) ++#define BGCAL0 0 ++#define BGCAL1 1 ++#define BGCAL2 2 ++#define BGCAL3 3 ++ ++#define SUPCA3 _SFR_MEM8(0xCE) ++#define ACAL4 0 ++#define ACAL5 1 ++#define ACAL6 2 ++#define ACAL7 3 ++#define DCAL4 4 ++#define DCAL5 5 ++#define DCAL6 6 ++ ++#define SUPCA4 _SFR_MEM8(0xCF) ++#define ACAL0 0 ++#define ACAL1 1 ++#define ACAL2 2 ++#define ACAL3 3 ++#define DCAL0 4 ++#define DCAL1 5 ++#define DCAL2 6 ++#define DCAL3 7 ++ ++#define CALRDY _SFR_MEM8(0xD0) ++ ++#define VMCAL _SFR_MEM8(0xD1) ++#define VMCAL0 0 ++#define VMCAL1 1 ++#define VMCAL2 2 ++ ++#define DFS _SFR_MEM8(0xD2) ++#define DFFLRF 0 ++#define DFUFL 1 ++#define DFOFL 2 ++ ++/* Combine DFTLL and DFTLH */ ++#define DFTL _SFR_MEM16(0xD3) ++ ++#define DFTLL _SFR_MEM8(0xD3) ++#define DFTLH _SFR_MEM8(0xD4) ++ ++#define DFL _SFR_MEM8(0xD5) ++#define DFFLS0 0 ++#define DFFLS1 1 ++#define DFFLS2 2 ++#define DFFLS3 3 ++#define DFFLS4 4 ++#define DFFLS5 5 ++#define DFCLR 7 ++ ++#define DFWP _SFR_MEM8(0xD6) ++#define DFWP0 0 ++#define DFWP1 1 ++#define DFWP2 2 ++#define DFWP3 3 ++#define DFWP4 4 ++#define DFWP5 5 ++ ++#define DFRP _SFR_MEM8(0xD7) ++#define DFRP0 0 ++#define DFRP1 1 ++#define DFRP2 2 ++#define DFRP3 3 ++#define DFRP4 4 ++#define DFRP5 5 ++ ++#define DFD _SFR_MEM8(0xD8) ++ ++#define DFI _SFR_MEM8(0xD9) ++#define DFFLIM 0 ++#define DFERIM 1 ++ ++#define DFC _SFR_MEM8(0xDA) ++#define DFFLC0 0 ++#define DFFLC1 1 ++#define DFFLC2 2 ++#define DFFLC3 3 ++#define DFFLC4 4 ++#define DFFLC5 5 ++#define DFDRA 7 ++ ++#define SFS _SFR_MEM8(0xDB) ++#define SFFLRF 0 ++#define SFUFL 1 ++#define SFOFL 2 ++ ++#define SFL _SFR_MEM8(0xDC) ++#define SFFLS0 0 ++#define SFFLS1 1 ++#define SFFLS2 2 ++#define SFFLS3 3 ++#define SFFLS4 4 ++#define SFCLR 7 ++ ++#define SFWP _SFR_MEM8(0xDD) ++#define SFWP0 0 ++#define SFWP1 1 ++#define SFWP2 2 ++#define SFWP3 3 ++#define SFWP4 4 ++ ++#define SFRP _SFR_MEM8(0xDE) ++#define SFRP0 0 ++#define SFRP1 1 ++#define SFRP2 2 ++#define SFRP3 3 ++#define SFRP4 4 ++ ++#define SFD _SFR_MEM8(0xDF) ++ ++#define SFI _SFR_MEM8(0xE0) ++#define SFFLIM 0 ++#define SFERIM 1 ++ ++#define SFC _SFR_MEM8(0xE1) ++#define SFFLC0 0 ++#define SFFLC1 1 ++#define SFFLC2 2 ++#define SFFLC3 3 ++#define SFFLC4 4 ++#define SFDRA 7 ++ ++#define SSMCR _SFR_MEM8(0xE2) ++#define SSMTX 0 ++#define SSMTM 1 ++#define SSMTGE 2 ++#define SSMTPE 3 ++#define SSMPVE 4 ++#define SSMTAE 5 ++#define SETRPA 6 ++#define SETRPB 7 ++ ++#define SSMRCR _SFR_MEM8(0xE3) ++#define SSMPA 0 ++#define SSMPB 1 ++#define SSMADA 2 ++#define SSMADB 3 ++#define SSMPVS 4 ++#define SSMIFA 5 ++#define SSMIDSE 6 ++#define SSMTMOE 7 ++ ++#define SSMFBR _SFR_MEM8(0xE4) ++#define SSMFID0 0 ++#define SSMFID1 1 ++#define SSMFID2 2 ++#define SSMDFDT 3 ++#define SSMHADT 4 ++#define SSMPLDT 5 ++ ++#define SSMRR _SFR_MEM8(0xE5) ++#define SSMR 0 ++#define SSMST 1 ++ ++#define SSMSR _SFR_MEM8(0xE6) ++#define SSMESM0 0 ++#define SSMESM1 1 ++#define SSMESM2 2 ++#define SSMESM3 3 ++#define SSMERR 7 ++ ++#define SSMIFR _SFR_MEM8(0xE7) ++#define SSMIF 0 ++ ++#define SSMIMR _SFR_MEM8(0xE8) ++#define SSMIM 0 ++ ++#define MSMSTR _SFR_MEM8(0xE9) ++#define SSMMST0 0 ++#define SSMMST1 1 ++#define SSMMST2 2 ++#define SSMMST3 3 ++#define SSMMST4 4 ++ ++#define SSMSTR _SFR_MEM8(0xEA) ++#define SSMSTA0 0 ++#define SSMSTA1 1 ++#define SSMSTA2 2 ++#define SSMSTA3 3 ++#define SSMSTA4 4 ++#define SSMSTA5 5 ++ ++#define SSMXSR _SFR_MEM8(0xEB) ++#define SSMSTB0 0 ++#define SSMSTB1 1 ++#define SSMSTB2 2 ++#define SSMSTB3 3 ++#define SSMSTB4 4 ++#define SSMSTB5 5 ++ ++#define MSMCR1 _SFR_MEM8(0xEC) ++#define MSMSM00 0 ++#define MSMSM01 1 ++#define MSMSM02 2 ++#define MSMSM03 3 ++#define MSMSM10 4 ++#define MSMSM11 5 ++#define MSMSM12 6 ++#define MSMSM13 7 ++ ++#define MSMCR2 _SFR_MEM8(0xED) ++#define MSMSM20 0 ++#define MSMSM21 1 ++#define MSMSM22 2 ++#define MSMSM23 3 ++#define MSMSM30 4 ++#define MSMSM31 5 ++#define MSMSM32 6 ++#define MSMSM33 7 ++ ++#define MSMCR3 _SFR_MEM8(0xEE) ++#define MSMSM40 0 ++#define MSMSM41 1 ++#define MSMSM42 2 ++#define MSMSM43 3 ++#define MSMSM50 4 ++#define MSMSM51 5 ++#define MSMSM52 6 ++#define MSMSM53 7 ++ ++#define MSMCR4 _SFR_MEM8(0xEF) ++#define MSMSM60 0 ++#define MSMSM61 1 ++#define MSMSM62 2 ++#define MSMSM63 3 ++#define MSMSM70 4 ++#define MSMSM71 5 ++#define MSMSM72 6 ++#define MSMSM73 7 ++ ++#define GTCR _SFR_MEM8(0xF0) ++#define RXTEHA 0 ++#define GAPMA 1 ++#define DARA 2 ++#define IWUPA 3 ++#define RXTEHB 4 ++#define GAPMB 5 ++#define DARB 6 ++#define IWUPB 7 ++ ++#define SOTC1A _SFR_MEM8(0xF1) ++#define CAROEA1 0 ++#define AMPOEA1 1 ++#define SYTOEA1 2 ++#define MANOEA1 3 ++#define WUPEA1 4 ++#define SFIDEA1 5 ++#define RROEA1 6 ++#define WCOBOE1 7 ++ ++#define SOTC2A _SFR_MEM8(0xF2) ++#define CAROEA2 0 ++#define AMPOEA2 1 ++#define SYTOEA2 2 ++#define MANOEA2 3 ++#define WUPEA2 4 ++#define SFIDEA2 5 ++#define RROEA2 6 ++#define WCOBOE2 7 ++ ++#define SOTC1B _SFR_MEM8(0xF3) ++#define CAROEB1 0 ++#define AMPOEB1 1 ++#define SYTOEB1 2 ++#define MANOEB1 3 ++#define WUPEB1 4 ++#define SFIDEB1 5 ++#define RROEB1 6 ++#define WCOAOE1 7 ++ ++#define SOTC2B _SFR_MEM8(0xF4) ++#define CAROEB2 0 ++#define AMPOEB2 1 ++#define SYTOEB2 2 ++#define MANOEB2 3 ++#define WUPEB2 4 ++#define SFIDEB2 5 ++#define RROEB2 6 ++#define WCOAOE2 7 ++ ++#define EOTC1A _SFR_MEM8(0xF5) ++#define CARFEA1 0 ++#define AMPFEA1 1 ++#define SYTFEA1 2 ++#define MANFEA1 3 ++#define TMOFEA1 4 ++#define TELREA1 5 ++#define RRFEA1 6 ++#define EOTBFE1 7 ++ ++#define EOTC2A _SFR_MEM8(0xF6) ++#define CARFEA2 0 ++#define AMPFEA2 1 ++#define SYTFEA2 2 ++#define MANFEA2 3 ++#define TMOFEA2 4 ++#define TELREA2 5 ++#define RRFEA2 6 ++#define EOTBFE2 7 ++ ++#define EOTC3A _SFR_MEM8(0xF7) ++#define CARFEA3 0 ++#define AMPFEA3 1 ++#define SYTFEA3 2 ++#define MANFEA3 3 ++#define TMOFEA3 4 ++#define TELREA3 5 ++#define RRFEA3 6 ++#define EOTBFE3 7 ++ ++#define EOTC1B _SFR_MEM8(0xF8) ++#define CARFEB1 0 ++#define AMPFEB1 1 ++#define SYTFEB1 2 ++#define MANFEB1 3 ++#define TMOFEB1 4 ++#define TELREB1 5 ++#define RRFEB1 6 ++#define EOTAFE1 7 ++ ++#define EOTC2B _SFR_MEM8(0xF9) ++#define CARFEB2 0 ++#define AMPFEB2 1 ++#define SYTFEB2 2 ++#define MANFEB2 3 ++#define TMOFEB2 4 ++#define TELREB2 5 ++#define RRFEB2 6 ++#define EOTAFE2 7 ++ ++#define EOTC3B _SFR_MEM8(0xFA) ++#define CARFEB3 0 ++#define AMPFEB3 1 ++#define SYTFEB3 2 ++#define MANFEB3 3 ++#define TMOFEB3 4 ++#define TELREB3 5 ++#define RRFEB3 6 ++#define EOTAFE3 7 ++ ++#define WCOTOA _SFR_MEM8(0xFB) ++ ++#define WCOTOB _SFR_MEM8(0xFC) ++ ++#define SOTTOA _SFR_MEM8(0xFD) ++ ++#define SOTTOB _SFR_MEM8(0xFE) ++ ++#define SSMFCR _SFR_MEM8(0xFF) ++#define SSMIDSO 0 ++#define SSMIDSF 1 ++ ++#define FESR _SFR_MEM8(0x100) ++#define LBSAT 0 ++#define HBSAT 1 ++#define XRDY 2 ++#define PLCK 3 ++#define ANTS 4 ++ ++#define FEEN1 _SFR_MEM8(0x101) ++#define PLEN 0 ++#define PLCAL 1 ++#define XTOEN 2 ++#define LNAEN 3 ++#define ADEN 4 ++#define ADCLK 5 ++#define PLSP1 6 ++#define ATEN 7 ++ ++#define FEEN2 _SFR_MEM8(0x102) ++#define SDRX 0 ++#define SDTX 1 ++#define PAEN 2 ++#define TMPM 3 ++#define PLPEN 4 ++#define XTPEN 5 ++#define CPBIA 6 ++ ++#define FELNA _SFR_MEM8(0x103) ++#define LBH0 0 ++#define LBH1 1 ++#define LBH2 2 ++#define LBH3 3 ++#define LBL0 4 ++#define LBL1 5 ++#define LBL2 6 ++#define LBL3 7 ++ ++#define FEAT _SFR_MEM8(0x104) ++#define ANTN0 0 ++#define ANTN1 1 ++#define ANTN2 2 ++#define ANTN3 3 ++ ++#define FEPAC _SFR_MEM8(0x105) ++ ++#define FEVCT _SFR_MEM8(0x106) ++#define FEVCT0 0 ++#define FEVCT1 1 ++#define FEVCT2 2 ++#define FEVCT3 3 ++ ++#define FEBT _SFR_MEM8(0x107) ++#define CTN20 0 ++#define CTN21 1 ++#define RTN20 2 ++#define RTN21 3 ++ ++#define FEMS _SFR_MEM8(0x108) ++#define PLLS0 0 ++#define PLLS1 1 ++#define PLLS2 2 ++#define PLLS3 3 ++#define PLLM0 4 ++#define PLLM1 5 ++#define PLLM2 6 ++#define PLLM3 7 ++ ++#define FETN4 _SFR_MEM8(0x109) ++#define CTN40 0 ++#define CTN41 1 ++#define CTN42 2 ++#define CTN43 3 ++#define RTN40 4 ++#define RTN41 5 ++#define RTN42 6 ++#define RTN43 7 ++ ++#define FECR _SFR_MEM8(0x10A) ++#define LBNHB 0 ++#define S4N3 1 ++#define ANDP 2 ++#define ADHS 3 ++#define PLCKG 4 ++#define ANPS 5 ++ ++#define FEVCO _SFR_MEM8(0x10B) ++#define CPCC0 0 ++#define CPCC1 1 ++#define CPCC2 2 ++#define CPCC3 3 ++#define VCOB0 4 ++#define VCOB1 5 ++#define VCOB2 6 ++#define VCOB3 7 ++ ++#define FEALR _SFR_MEM8(0x10C) ++#define RNGE0 0 ++#define RNGE1 1 ++ ++#define FEANT _SFR_MEM8(0x10D) ++#define LVLC0 0 ++#define LVLC1 1 ++#define LVLC2 2 ++#define LVLC3 3 ++ ++#define FEBIA _SFR_MEM8(0x10E) ++#define IFAEN 7 ++ ++/* Reserved [0x10F..0x11F] */ ++ ++#define TMFSM _SFR_MEM8(0x120) ++#define TMSSM0 0 ++#define TMSSM1 1 ++#define TMSSM2 2 ++#define TMSSM3 3 ++#define TMMSM0 4 ++#define TMMSM1 5 ++#define TMMSM2 6 ++ ++/* Combine TMCRL and TMCRH */ ++#define TMCR _SFR_MEM16(0x121) ++ ++#define TMCRL _SFR_MEM8(0x121) ++#define TMCRH _SFR_MEM8(0x122) ++ ++#define TMCSB _SFR_MEM8(0x123) ++ ++/* Combine TMCIL and TMCIH */ ++#define TMCI _SFR_MEM16(0x124) ++ ++#define TMCIL _SFR_MEM8(0x124) ++#define TMCIH _SFR_MEM8(0x125) ++ ++/* Combine TMCPL and TMCPH */ ++#define TMCP _SFR_MEM16(0x126) ++ ++#define TMCPL _SFR_MEM8(0x126) ++#define TMCPH _SFR_MEM8(0x127) ++ ++#define TMSHR _SFR_MEM8(0x128) ++ ++/* Combine TMTLL and TMTLH */ ++#define TMTL _SFR_MEM16(0x129) ++ ++#define TMTLL _SFR_MEM8(0x129) ++#define TMTLH _SFR_MEM8(0x12A) ++ ++#define TMSSC _SFR_MEM8(0x12B) ++#define TMSSP0 0 ++#define TMSSP1 1 ++#define TMSSP2 2 ++#define TMSSP3 3 ++#define TMSSL0 4 ++#define TMSSL1 5 ++#define TMSSL2 6 ++#define TMSSH 7 ++ ++#define TMSR _SFR_MEM8(0x12C) ++#define TMTCF 0 ++ ++#define TMCR2 _SFR_MEM8(0x12D) ++#define TMCRCE 0 ++#define TMCRCL0 1 ++#define TMCRCL1 2 ++#define TMNRZE 3 ++#define TMPOL 4 ++#define TMSSE 5 ++#define TMMSB 6 ++ ++#define TMCR1 _SFR_MEM8(0x12E) ++#define TMPIS0 0 ++#define TMPIS1 1 ++#define TMPIS2 2 ++#define TMSCS 3 ++#define TMCIM 4 ++ ++#define RXBC1 _SFR_MEM8(0x12F) ++#define RXCEA 0 ++#define RXCBLA0 1 ++#define RXCBLA1 2 ++#define RXMSBA 3 ++#define RXCEB 4 ++#define RXCBLB0 5 ++#define RXCBLB1 6 ++#define RXMSBB 7 ++ ++#define RXBC2 _SFR_MEM8(0x130) ++#define RXBPB 0 ++#define RXBF 1 ++#define RXBCLR 2 ++ ++#define RXTLLB _SFR_MEM8(0x131) ++ ++#define RXTLHB _SFR_MEM8(0x132) ++#define RXTLHB0 0 ++#define RXTLHB1 1 ++#define RXTLHB2 2 ++#define RXTLHB3 3 ++ ++#define RXCRLB _SFR_MEM8(0x133) ++ ++#define RXCRHB _SFR_MEM8(0x134) ++ ++#define RXCSBB _SFR_MEM8(0x135) ++ ++#define RXCILB _SFR_MEM8(0x136) ++ ++#define RXCIHB _SFR_MEM8(0x137) ++ ++#define RXCPLB _SFR_MEM8(0x138) ++ ++#define RXCPHB _SFR_MEM8(0x139) ++ ++#define RXDSB _SFR_MEM8(0x13A) ++ ++#define RXTLLA _SFR_MEM8(0x13B) ++ ++#define RXTLHA _SFR_MEM8(0x13C) ++#define RXTLHA0 0 ++#define RXTLHA1 1 ++#define RXTLHA2 2 ++#define RXTLHA3 3 ++ ++#define RXCRLA _SFR_MEM8(0x13D) ++ ++#define RXCRHA _SFR_MEM8(0x13E) ++ ++#define RXCSBA _SFR_MEM8(0x13F) ++ ++#define RXCILA _SFR_MEM8(0x140) ++ ++#define RXCIHA _SFR_MEM8(0x141) ++ ++#define RXCPLA _SFR_MEM8(0x142) ++ ++#define RXCPHA _SFR_MEM8(0x143) ++ ++#define RXDSA _SFR_MEM8(0x144) ++ ++#define CRCCR _SFR_MEM8(0x145) ++#define CRCRS 0 ++#define REFLI 1 ++#define REFLO 2 ++ ++#define CRCDOR _SFR_MEM8(0x146) ++ ++#define IDB0 _SFR_MEM8(0x147) ++ ++#define IDB1 _SFR_MEM8(0x148) ++ ++#define IDB2 _SFR_MEM8(0x149) ++ ++#define IDB3 _SFR_MEM8(0x14A) ++ ++#define IDC _SFR_MEM8(0x14B) ++#define IDL0 0 ++#define IDL1 1 ++#define IDBO0 2 ++#define IDBO1 3 ++#define IDFIM 5 ++#define IDCLR 6 ++#define IDCE 7 ++ ++#define IDS _SFR_MEM8(0x14C) ++#define IDOK 0 ++#define IDFULL 1 ++ ++#define RSSAV _SFR_MEM8(0x14D) ++ ++#define RSSPK _SFR_MEM8(0x14E) ++ ++#define RSSL _SFR_MEM8(0x14F) ++ ++#define RSSH _SFR_MEM8(0x150) ++ ++#define RSSC _SFR_MEM8(0x151) ++#define RSUP0 0 ++#define RSUP1 1 ++#define RSUP2 2 ++#define RSUP3 3 ++#define RSWLH 4 ++#define RSHRX 5 ++#define RSPKF 6 ++ ++#define DBCR _SFR_MEM8(0x152) ++#define DBMD 0 ++#define DBCS 1 ++#define DBTMS 2 ++#define DBHA 3 ++ ++#define DBTC _SFR_MEM8(0x153) ++ ++#define DBENB _SFR_MEM8(0x154) ++ ++#define DBENC _SFR_MEM8(0x155) ++ ++#define DBGSW _SFR_MEM8(0x156) ++#define DBGGS0 0 ++#define DBGGS1 1 ++#define DBGGS2 2 ++#define DBGGS3 3 ++#define CPBFOS0 4 ++#define CPBFOS1 5 ++#define CPBF 6 ++#define DBGSE 7 ++ ++#define SFFR _SFR_MEM8(0x157) ++#define RFL0 0 ++#define RFL1 1 ++#define RFL2 2 ++#define RFC 3 ++#define TFL0 4 ++#define TFL1 5 ++#define TFL2 6 ++#define TFC 7 ++ ++#define SFIR _SFR_MEM8(0x158) ++#define RIL0 0 ++#define RIL1 1 ++#define RIL2 2 ++#define SRIE 3 ++#define TIL0 4 ++#define TIL1 5 ++#define TIL2 6 ++#define STIE 7 ++ ++#define EECR2 _SFR_MEM8(0x159) ++#define EEBRE 0 ++ ++#define PGMST _SFR_MEM8(0x15A) ++#define PGMSYN0 0 ++#define PGMSYN1 1 ++#define PGMSYN2 2 ++#define PGMSYN3 3 ++#define PGMSYN4 4 ++ ++#define EEST _SFR_MEM8(0x15B) ++#define EESYN0 0 ++#define EESYN1 1 ++#define EESYN2 2 ++#define EESYN3 3 ++ ++#define RSIFG _SFR_MEM8(0x15C) ++ ++#define RSLDV _SFR_MEM8(0x15D) ++ ++#define RSHDV _SFR_MEM8(0x15E) ++ ++#define RSCOM _SFR_MEM8(0x15F) ++#define RSDC 0 ++#define RSIFC 1 ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCI0_vect _VECTOR(3) ++#define PCI0_vect_num 3 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCI1_vect _VECTOR(4) ++#define PCI1_vect_num 4 ++ ++/* Voltage Monitoring Interrupt */ ++#define VMON_vect _VECTOR(5) ++#define VMON_vect_num 5 ++ ++/* AVCC Reset Interrupt */ ++#define AVCCR_vect _VECTOR(6) ++#define AVCCR_vect_num 6 ++ ++/* AVCC Low Interrupt */ ++#define AVCCL_vect _VECTOR(7) ++#define AVCCL_vect_num 7 ++ ++/* Timer 0 Interval Interrupt */ ++#define T0INT_vect _VECTOR(8) ++#define T0INT_vect_num 8 ++ ++/* Timer/Counter1 Compare Match Interrupt */ ++#define T1COMP_vect _VECTOR(9) ++#define T1COMP_vect_num 9 ++ ++/* Timer/Counter1 Overflow Interrupt */ ++#define T1OVF_vect _VECTOR(10) ++#define T1OVF_vect_num 10 ++ ++/* Timer/Counter2 Compare Match Interrupt */ ++#define T2COMP_vect _VECTOR(11) ++#define T2COMP_vect_num 11 ++ ++/* Timer/Counter2 Overflow Interrupt */ ++#define T2OVF_vect _VECTOR(12) ++#define T2OVF_vect_num 12 ++ ++/* Timer/Counter3 Capture Event Interrupt */ ++#define T3CAP_vect _VECTOR(13) ++#define T3CAP_vect_num 13 ++ ++/* Timer/Counter3 Compare Match Interrupt */ ++#define T3COMP_vect _VECTOR(14) ++#define T3COMP_vect_num 14 ++ ++/* Timer/Counter3 Overflow Interrupt */ ++#define T3OVF_vect _VECTOR(15) ++#define T3OVF_vect_num 15 ++ ++/* Timer/Counter4 Capture Event Interrupt */ ++#define T4CAP_vect _VECTOR(16) ++#define T4CAP_vect_num 16 ++ ++/* Timer/Counter4 Compare Match Interrupt */ ++#define T4COMP_vect _VECTOR(17) ++#define T4COMP_vect_num 17 ++ ++/* Timer/Counter4 Overflow Interrupt */ ++#define T4OVF_vect _VECTOR(18) ++#define T4OVF_vect_num 18 ++ ++/* Timer/Counter5 Compare Match Interrupt */ ++#define T5COMP_vect _VECTOR(19) ++#define T5COMP_vect_num 19 ++ ++/* Timer/Counter5 Overflow Interrupt */ ++#define T5OVF_vect _VECTOR(20) ++#define T5OVF_vect_num 20 ++ ++/* SPI Serial Transfer Complete Interrupt */ ++#define SPI_vect _VECTOR(21) ++#define SPI_vect_num 21 ++ ++/* SPI Rx Buffer Interrupt */ ++#define SRX_FIFO_vect _VECTOR(22) ++#define SRX_FIFO_vect_num 22 ++ ++/* SPI Tx Buffer Interrupt */ ++#define STX_FIFO_vect _VECTOR(23) ++#define STX_FIFO_vect_num 23 ++ ++/* Sequencer State Machine Interrupt */ ++#define SSM_vect _VECTOR(24) ++#define SSM_vect_num 24 ++ ++/* Data FIFO fill level reached Interrupt */ ++#define DFFLR_vect _VECTOR(25) ++#define DFFLR_vect_num 25 ++ ++/* Data FIFO overflow or underflow error Interrupt */ ++#define DFOUE_vect _VECTOR(26) ++#define DFOUE_vect_num 26 ++ ++/* RSSI/Preamble FIFO fill level reached Interrupt */ ++#define SFFLR_vect _VECTOR(27) ++#define SFFLR_vect_num 27 ++ ++/* RSSI/Preamble FIFO overflow or underflow error Interrupt */ ++#define SFOUE_vect _VECTOR(28) ++#define SFOUE_vect_num 28 ++ ++/* Tx Modulator Telegram Finish Interrupt */ ++#define TMTCF_vect _VECTOR(29) ++#define TMTCF_vect_num 29 ++ ++/* UHF receiver wake up ok on Rx path B */ ++#define UHF_WCOB_vect _VECTOR(30) ++#define UHF_WCOB_vect_num 30 ++ ++/* UHF receiver wake up ok on Rx path A */ ++#define UHF_WCOA_vect _VECTOR(31) ++#define UHF_WCOA_vect_num 31 ++ ++/* UHF receiver start of telegram ok on Rx path B */ ++#define UHF_SOTB_vect _VECTOR(32) ++#define UHF_SOTB_vect_num 32 ++ ++/* UHF receiver start of telegram ok on Rx path A */ ++#define UHF_SOTA_vect _VECTOR(33) ++#define UHF_SOTA_vect_num 33 ++ ++/* UHF receiver end of telegram on Rx path B */ ++#define UHF_EOTB_vect _VECTOR(34) ++#define UHF_EOTB_vect_num 34 ++ ++/* UHF receiver end of telegram on Rx path A */ ++#define UHF_EOTA_vect _VECTOR(35) ++#define UHF_EOTA_vect_num 35 ++ ++/* UHF receiver new bit on Rx path B */ ++#define UHF_NBITB_vect _VECTOR(36) ++#define UHF_NBITB_vect_num 36 ++ ++/* UHF receiver new bit on Rx path A */ ++#define UHF_NBITA_vect _VECTOR(37) ++#define UHF_NBITA_vect_num 37 ++ ++/* External input Clock monitoring Interrupt */ ++#define EXCM_vect _VECTOR(38) ++#define EXCM_vect_num 38 ++ ++/* EEPROM Ready Interrupt */ ++#define ERDY_vect _VECTOR(39) ++#define ERDY_vect_num 39 ++ ++/* Store Program Memory Ready */ ++#define SPMR_vect _VECTOR(40) ++#define SPMR_vect_num 40 ++ ++/* IDSCAN Full Interrupt */ ++#define IDFULL_vect _VECTOR(41) ++#define IDFULL_vect_num 41 ++ ++#define _VECTORS_SIZE 168 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 64 ++#define FLASHSTART 0x8000 ++#define FLASHEND 0xCFFF ++#define RAMSTART 0x0200 ++#define RAMSIZE 1024 ++#define RAMEND 0x05FF ++#define E2START 0 ++#define E2SIZE 1152 ++#define E2PAGESIZE 16 ++#define E2END 0x047F ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Fuse Byte */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(128) ++#define FUSE_DWEN (unsigned char)~_BV(64) ++#define FUSE_SPIEN (unsigned char)~_BV(32) ++#define FUSE_WDTON (unsigned char)~_BV(16) ++#define FUSE_EESAVE (unsigned char)~_BV(8) ++#define FUSE_BOOTRST (unsigned char)~_BV(4) ++#define FUSE_RSTDISBL (unsigned char)~_BV(2) ++#define FUSE_EXTCLKEN (unsigned char)~_BV(1) ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x61 ++ ++ ++#endif /* #ifdef _AVR_ATA5831_H_INCLUDED */ ++ +diff --git a/include/avr/ioa5832.h b/include/avr/ioa5832.h +new file mode 100644 +index 0000000..826a202 +--- /dev/null ++++ b/include/avr/ioa5832.h +@@ -0,0 +1,1885 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATA5832_H_INCLUDED ++#define _AVR_ATA5832_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "ioa5832.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PRR0 _SFR_IO8(0x01) ++#define PRSPI 0 ++#define PRRXDC 1 ++#define PRTXDC 2 ++#define PRCRC 3 ++#define PRVM 4 ++#define PRCO 5 ++ ++#define PRR1 _SFR_IO8(0x02) ++#define PRT1 0 ++#define PRT2 1 ++#define PRT3 2 ++#define PRT4 3 ++#define PRT5 4 ++ ++#define PRR2 _SFR_IO8(0x03) ++#define PRXB 0 ++#define PRXA 1 ++#define PRSF 2 ++#define PRDF 3 ++#define PRIDS 4 ++#define PRRS 5 ++#define PRTM 6 ++#define PRSSM 7 ++ ++#define RDPR _SFR_IO8(0x04) ++#define PRPTB 0 ++#define PRPTA 1 ++#define PRFLT 2 ++#define PRTMP 3 ++#define APRPTB 4 ++#define APRPTA 5 ++#define ARDPRF 6 ++#define RDPRF 7 ++ ++#define PINB _SFR_IO8(0x05) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x06) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x07) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x08) ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x09) ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x0A) ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define FSCR _SFR_IO8(0x0B) ++#define TXMOD 0 ++#define SFM 1 ++#define TXMS0 2 ++#define TXMS1 3 ++#define PAOER 4 ++#define PAON 7 ++ ++/* Reserved [0x0C] */ ++ ++#define RDSIFR _SFR_IO8(0x0D) ++#define NBITA 0 ++#define NBITB 1 ++#define EOTA 2 ++#define EOTB 3 ++#define SOTA 4 ++#define SOTB 5 ++#define WCOA 6 ++#define WCOB 7 ++ ++#define MCUCR _SFR_IO8(0x0E) ++#define IVCE 0 ++#define IVSEL 1 ++#define SPIIO 2 ++#define ENPS 3 ++#define PUD 4 ++#define PB4HS 5 ++#define PB7LS 6 ++#define PB7HS 7 ++ ++#define PCIFR _SFR_IO8(0x0F) ++#define PCIF0 0 ++#define PCIF1 1 ++ ++#define T0CR _SFR_IO8(0x10) ++#define T0PS0 0 ++#define T0PS1 1 ++#define T0PS2 2 ++#define T0IE 3 ++#define T0PR 4 ++ ++#define T1CR _SFR_IO8(0x11) ++#define T1OTM 0 ++#define T1CTM 1 ++#define T1CRM 2 ++#define T1TOP 4 ++#define T1RES 5 ++#define T1TOS 6 ++#define T1ENA 7 ++ ++#define T2CR _SFR_IO8(0x12) ++#define T2OTM 0 ++#define T2CTM 1 ++#define T2CRM 2 ++#define T2TOP 4 ++#define T2RES 5 ++#define T2TOS 6 ++#define T2ENA 7 ++ ++#define T3CR _SFR_IO8(0x13) ++#define T3OTM 0 ++#define T3CTM 1 ++#define T3CRM 2 ++#define T3CPRM 3 ++#define T3TOP 4 ++#define T3RES 5 ++#define T3TOS 6 ++#define T3ENA 7 ++ ++#define T4CR _SFR_IO8(0x14) ++#define T4OTM 0 ++#define T4CTM 1 ++#define T4CRM 2 ++#define T4CPRM 3 ++#define T4TOP 4 ++#define T4RES 5 ++#define T4TOS 6 ++#define T4ENA 7 ++ ++#define T1IFR _SFR_IO8(0x15) ++#define T1OFF 0 ++#define T1COF 1 ++ ++#define T2IFR _SFR_IO8(0x16) ++#define T2OFF 0 ++#define T2COF 1 ++ ++#define T3IFR _SFR_IO8(0x17) ++#define T3OFF 0 ++#define T3COF 1 ++#define T3ICF 2 ++ ++#define T4IFR _SFR_IO8(0x18) ++#define T4OFF 0 ++#define T4COF 1 ++#define T4ICF 2 ++ ++#define T5IFR _SFR_IO8(0x19) ++#define T5OFF 0 ++#define T5COF 1 ++ ++#define GPIOR0 _SFR_IO8(0x1A) ++ ++#define GPIOR3 _SFR_IO8(0x1B) ++ ++#define GPIOR4 _SFR_IO8(0x1C) ++ ++#define GPIOR5 _SFR_IO8(0x1D) ++ ++#define GPIOR6 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++#define EEPAGE 6 ++#define NVMBSY 7 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define EEPR _SFR_IO8(0x23) ++#define EEAP0 0 ++#define EEAP1 1 ++#define EEAP2 2 ++#define EEAP3 3 ++ ++#define GPIOR1 _SFR_IO8(0x24) ++ ++#define GPIOR2 _SFR_IO8(0x25) ++ ++#define PCICR _SFR_IO8(0x26) ++#define PCIE0 0 ++#define PCIE1 1 ++ ++#define EIMSK _SFR_IO8(0x27) ++#define INT0 0 ++#define INT1 1 ++ ++#define EIFR _SFR_IO8(0x28) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define CRCDIR _SFR_IO8(0x29) ++ ++#define VMCSR _SFR_IO8(0x2A) ++#define VMLS0 0 ++#define VMLS1 1 ++#define VMLS2 2 ++#define VMLS3 3 ++#define VMIM 4 ++#define VMF 5 ++ ++#define MCUSR _SFR_IO8(0x2B) ++#define PORF 0 ++#define EXTRF 1 ++#define WDRF 3 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define RXIF 4 ++#define TXIF 5 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++#define T0IFR _SFR_IO8(0x2F) ++#define T0F 0 ++ ++/* Reserved [0x30] */ ++ ++#define DWDR _SFR_IO8(0x31) ++ ++/* Reserved [0x32] */ ++ ++#define RDCR _SFR_IO8(0x33) ++#define RDPU 0 ++#define ADIVEN 1 ++#define RDEN 2 ++ ++#define EOTSA _SFR_IO8(0x34) ++#define CARFA 0 ++#define AMPFA 1 ++#define SYTFA 2 ++#define MANFA 3 ++#define TMOFA 4 ++#define TELRA 5 ++#define RRFA 6 ++#define EOTBF 7 ++ ++#define EOTCA _SFR_IO8(0x35) ++#define CARFEA 0 ++#define AMPFEA 1 ++#define SYTFEA 2 ++#define MANFEA 3 ++#define TMOFEA 4 ++#define TELREA 5 ++#define RRFEA 6 ++#define EOTBFE 7 ++ ++#define EOTSB _SFR_IO8(0x36) ++#define CARFB 0 ++#define AMPFB 1 ++#define SYTFB 2 ++#define MANFB 3 ++#define TMOFB 4 ++#define TELRB 5 ++#define RRFB 6 ++#define EOTAF 7 ++ ++#define EOTCB _SFR_IO8(0x37) ++#define CARFEB 0 ++#define AMPFEB 1 ++#define SYTFEB 2 ++#define MANFEB 3 ++#define TMOFEB 4 ++#define TELREB 5 ++#define RRFEB 6 ++#define EOTAFE 7 ++ ++#define SMCR _SFR_IO8(0x38) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define CMCR _SFR_IO8(0x39) ++#define CMM0 0 ++#define CMM1 1 ++#define CMM2 2 ++#define CCS 3 ++#define SRCD 4 ++#define CMONEN 6 ++#define CMCCE 7 ++ ++#define CMIMR _SFR_IO8(0x3A) ++#define ECIE 0 ++ ++#define CLPR _SFR_IO8(0x3B) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLTPS0 3 ++#define CLTPS1 4 ++#define CLTPS2 5 ++#define CLPCE 7 ++ ++#define SPMCSR _SFR_IO8(0x3C) ++#define SELFPRGEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define SPMIE 7 ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define FSEN _SFR_MEM8(0x60) ++#define SDPU 0 ++#define SDEN 1 ++#define GAEN 2 ++#define PEEN 3 ++#define ASEN 4 ++#define ANTT 5 ++ ++#define FSFCR _SFR_MEM8(0x61) ++#define BTSEL0 0 ++#define BTSEL1 1 ++#define ASDIV0 4 ++#define ASDIV1 5 ++#define ASDIV2 6 ++#define ASDIV3 7 ++ ++/* Combine GACDIVL and GACDIVH */ ++#define GACDIV _SFR_MEM16(0x62) ++ ++#define GACDIVL _SFR_MEM8(0x62) ++#define GACDIVH _SFR_MEM8(0x63) ++ ++#define FFREQ1L _SFR_MEM8(0x64) ++ ++#define FFREQ1M _SFR_MEM8(0x65) ++ ++#define FFREQ1H _SFR_MEM8(0x66) ++ ++#define FFREQ2L _SFR_MEM8(0x67) ++ ++#define FFREQ2M _SFR_MEM8(0x68) ++ ++#define FFREQ2H _SFR_MEM8(0x69) ++ ++/* Reserved [0x6A] */ ++ ++#define EICRA _SFR_MEM8(0x6B) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++#define PCMSK0 _SFR_MEM8(0x6C) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6D) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++ ++#define WDTCR _SFR_MEM8(0x6E) ++#define WDPS0 0 ++#define WDPS1 1 ++#define WDPS2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define T1CNT _SFR_MEM8(0x6F) ++ ++#define T1COR _SFR_MEM8(0x70) ++ ++#define T1MR _SFR_MEM8(0x71) ++#define T1CS0 0 ++#define T1CS1 1 ++#define T1PS0 2 ++#define T1PS1 3 ++#define T1PS2 4 ++#define T1PS3 5 ++#define T1DC0 6 ++#define T1DC1 7 ++ ++#define T1IMR _SFR_MEM8(0x72) ++#define T1OIM 0 ++#define T1CIM 1 ++ ++#define T2CNT _SFR_MEM8(0x73) ++ ++#define T2COR _SFR_MEM8(0x74) ++ ++#define T2MR _SFR_MEM8(0x75) ++#define T2CS0 0 ++#define T2CS1 1 ++#define T2PS0 2 ++#define T2PS1 3 ++#define T2PS2 4 ++#define T2PS3 5 ++#define T2DC0 6 ++#define T2DC1 7 ++ ++#define T2IMR _SFR_MEM8(0x76) ++#define T2OIM 0 ++#define T2CIM 1 ++ ++/* Combine T3CNTL and T3CNTH */ ++#define T3CNT _SFR_MEM16(0x77) ++ ++#define T3CNTL _SFR_MEM8(0x77) ++#define T3CNTH _SFR_MEM8(0x78) ++ ++/* Combine T3CORL and T3CORH */ ++#define T3COR _SFR_MEM16(0x79) ++ ++#define T3CORL _SFR_MEM8(0x79) ++#define T3CORH _SFR_MEM8(0x7A) ++ ++/* Combine T3ICRL and T3ICRH */ ++#define T3ICR _SFR_MEM16(0x7B) ++ ++#define T3ICRL _SFR_MEM8(0x7B) ++#define T3ICRH _SFR_MEM8(0x7C) ++ ++#define T3MRA _SFR_MEM8(0x7D) ++#define T3CS0 0 ++#define T3CS1 1 ++#define T3PS0 2 ++#define T3PS1 3 ++#define T3PS2 4 ++ ++#define T3MRB _SFR_MEM8(0x7E) ++#define T3SCE 1 ++#define T3CNC 2 ++#define T3CE0 3 ++#define T3CE1 4 ++#define T3ICS0 5 ++#define T3ICS1 6 ++#define T3ICS2 7 ++ ++#define T3IMR _SFR_MEM8(0x7F) ++#define T3OIM 0 ++#define T3CIM 1 ++#define T3CPIM 2 ++ ++/* Combine T4CNTL and T4CNTH */ ++#define T4CNT _SFR_MEM16(0x80) ++ ++#define T4CNTL _SFR_MEM8(0x80) ++#define T4CNTH _SFR_MEM8(0x81) ++ ++/* Combine T4CORL and T4CORH */ ++#define T4COR _SFR_MEM16(0x82) ++ ++#define T4CORL _SFR_MEM8(0x82) ++#define T4CORH _SFR_MEM8(0x83) ++ ++/* Combine T4ICRL and T4ICRH */ ++#define T4ICR _SFR_MEM16(0x84) ++ ++#define T4ICRL _SFR_MEM8(0x84) ++#define T4ICRH _SFR_MEM8(0x85) ++ ++#define T4MRA _SFR_MEM8(0x86) ++#define T4CS0 0 ++#define T4CS1 1 ++#define T4PS0 2 ++#define T4PS1 3 ++#define T4PS2 4 ++ ++#define T4MRB _SFR_MEM8(0x87) ++#define T4SCE 1 ++#define T4CNC 2 ++#define T4CE0 3 ++#define T4CE1 4 ++#define T4ICS0 5 ++#define T4ICS1 6 ++#define T4ICS2 7 ++ ++#define T4IMR _SFR_MEM8(0x88) ++#define T4OIM 0 ++#define T4CIM 1 ++#define T4CPIM 2 ++ ++/* Reserved [0x89] */ ++ ++/* Combine T5OCRL and T5OCRH */ ++#define T5OCR _SFR_MEM16(0x8A) ++ ++#define T5OCRL _SFR_MEM8(0x8A) ++#define T5OCRH _SFR_MEM8(0x8B) ++ ++#define T5CCR _SFR_MEM8(0x8C) ++#define T5CS0 0 ++#define T5CS1 1 ++#define T5CS2 2 ++#define T5CTC 3 ++ ++/* Combine T5CNTL and T5CNTH */ ++#define T5CNT _SFR_MEM16(0x8D) ++ ++#define T5CNTL _SFR_MEM8(0x8D) ++#define T5CNTH _SFR_MEM8(0x8E) ++ ++#define T5IMR _SFR_MEM8(0x8F) ++#define T5OIM 0 ++#define T5CIM 1 ++ ++#define GTCCR _SFR_MEM8(0x90) ++#define PSR10 0 ++#define TSM 7 ++ ++#define SOTSB _SFR_MEM8(0x91) ++#define CAROB 0 ++#define AMPOB 1 ++#define SYTOB 2 ++#define MANOB 3 ++#define WUPOB 4 ++#define SFIDOB 5 ++#define RROB 6 ++#define WCOAO 7 ++ ++#define SOTSA _SFR_MEM8(0x92) ++#define CAROA 0 ++#define AMPOA 1 ++#define SYTOA 2 ++#define MANOA 3 ++#define WUPOA 4 ++#define SFIDOA 5 ++#define RROA 6 ++#define WCOBO 7 ++ ++#define SOTCB _SFR_MEM8(0x93) ++#define CAROEB 0 ++#define AMPOEB 1 ++#define SYTOEB 2 ++#define MANOEB 3 ++#define WUPEB 4 ++#define SFIDEB 5 ++#define RROEB 6 ++#define WCOAOE 7 ++ ++#define SOTCA _SFR_MEM8(0x94) ++#define CAROEA 0 ++#define AMPOEA 1 ++#define SYTOEA 2 ++#define MANOEA 3 ++#define WUPEA 4 ++#define SFIDEA 5 ++#define RROEA 6 ++#define WCOBOE 7 ++ ++#define TESRB _SFR_MEM8(0x95) ++#define CRCOB 0 ++#define EOTLB0 1 ++#define EOTLB1 2 ++ ++#define TESRA _SFR_MEM8(0x96) ++#define CRCOA 0 ++#define EOTLA0 1 ++#define EOTLA1 2 ++ ++/* Reserved [0x97] */ ++ ++#define RDSIMR _SFR_MEM8(0x98) ++#define NBITAM 0 ++#define NBITBM 1 ++#define EOTAM 2 ++#define EOTBM 3 ++#define SOTAM 4 ++#define SOTBM 5 ++#define WCOAM 6 ++#define WCOBM 7 ++ ++#define RDOCR _SFR_MEM8(0x99) ++#define TMDS0 1 ++#define TMDS1 2 ++#define ETRPA 3 ++#define ETRPB 4 ++#define RDSIDA 5 ++#define RDSIDB 6 ++ ++/* Reserved [0x9A] */ ++ ++#define TEMPL _SFR_MEM8(0x9B) ++ ++#define TEMPH _SFR_MEM8(0x9C) ++ ++#define SYCB _SFR_MEM8(0x9D) ++#define SYCSB0 0 ++#define SYCSB1 1 ++#define SYCSB2 2 ++#define SYCSB3 3 ++#define SYTLB0 4 ++#define SYTLB1 5 ++#define SYTLB2 6 ++#define SYTLB3 7 ++ ++#define SYCA _SFR_MEM8(0x9E) ++#define SYCSA0 0 ++#define SYCSA1 1 ++#define SYCSA2 2 ++#define SYCSA3 3 ++#define SYTLA0 4 ++#define SYTLA1 5 ++#define SYTLA2 6 ++#define SYTLA3 7 ++ ++#define RXFOB _SFR_MEM8(0x9F) ++ ++#define RXFOA _SFR_MEM8(0xA0) ++ ++#define DMMB _SFR_MEM8(0xA1) ++#define DMATB0 0 ++#define DMATB1 1 ++#define DMATB2 2 ++#define DMATB3 3 ++#define DMATB4 4 ++#define DMPB 5 ++#define DMHB 6 ++#define DMNEB 7 ++ ++#define DMMA _SFR_MEM8(0xA2) ++#define DMATA0 0 ++#define DMATA1 1 ++#define DMATA2 2 ++#define DMATA3 3 ++#define DMATA4 4 ++#define DMPA 5 ++#define DMHA 6 ++#define DMNEA 7 ++ ++#define DMCDB _SFR_MEM8(0xA3) ++#define DMCLB0 0 ++#define DMCLB1 1 ++#define DMCLB2 2 ++#define DMCLB3 3 ++#define DMCLB4 4 ++#define DMCTB0 5 ++#define DMCTB1 6 ++#define DMCTB2 7 ++ ++#define DMCDA _SFR_MEM8(0xA4) ++#define DMCLA0 0 ++#define DMCLA1 1 ++#define DMCLA2 2 ++#define DMCLA3 3 ++#define DMCLA4 4 ++#define DMCTA0 5 ++#define DMCTA1 6 ++#define DMCTA2 7 ++ ++#define DMCRB _SFR_MEM8(0xA5) ++#define DMPGB0 0 ++#define DMPGB1 1 ++#define DMPGB2 2 ++#define DMPGB3 3 ++#define DMPGB4 4 ++#define SASKB 5 ++#define SY1TB 6 ++#define DMARB 7 ++ ++#define DMCRA _SFR_MEM8(0xA6) ++#define DMPGA0 0 ++#define DMPGA1 1 ++#define DMPGA2 2 ++#define DMPGA3 3 ++#define DMPGA4 4 ++#define SASKA 5 ++#define SY1TA 6 ++#define DMARA 7 ++ ++#define DMDRB _SFR_MEM8(0xA7) ++#define DMAB0 0 ++#define DMAB1 1 ++#define DMAB2 2 ++#define DMAB3 3 ++#define DMDNB0 4 ++#define DMDNB1 5 ++#define DMDNB2 6 ++#define DMDNB3 7 ++ ++#define DMDRA _SFR_MEM8(0xA8) ++#define DMAA0 0 ++#define DMAA1 1 ++#define DMAA2 2 ++#define DMAA3 3 ++#define DMDNA0 4 ++#define DMDNA1 5 ++#define DMDNA2 6 ++#define DMDNA3 7 ++ ++#define CHCR _SFR_MEM8(0xA9) ++#define BWM0 0 ++#define BWM1 1 ++#define BWM2 2 ++#define BWM3 3 ++ ++#define CHDN _SFR_MEM8(0xAA) ++#define BBDN0 0 ++#define BBDN1 1 ++#define BBDN2 2 ++#define BBDN3 3 ++#define BBDN4 4 ++#define ADCDN 5 ++ ++#define SFIDCB _SFR_MEM8(0xAB) ++#define SFIDTB0 0 ++#define SFIDTB1 1 ++#define SFIDTB2 2 ++#define SFIDTB3 3 ++#define SFIDTB4 4 ++#define SEMEB 7 ++ ++#define SFIDLB _SFR_MEM8(0xAC) ++#define SFIDLB0 0 ++#define SFIDLB1 1 ++#define SFIDLB2 2 ++#define SFIDLB3 3 ++#define SFIDLB4 4 ++#define SFIDLB5 5 ++ ++#define WUPTB _SFR_MEM8(0xAD) ++#define WUPTB0 0 ++#define WUPTB1 1 ++#define WUPTB2 2 ++#define WUPTB3 3 ++#define WUPTB4 4 ++ ++#define WUPLB _SFR_MEM8(0xAE) ++#define WUPLB0 0 ++#define WUPLB1 1 ++#define WUPLB2 2 ++#define WUPLB3 3 ++#define WUPLB4 4 ++#define WUPLB5 5 ++ ++#define SFID1B _SFR_MEM8(0xAF) ++ ++#define SFID2B _SFR_MEM8(0xB0) ++ ++#define SFID3B _SFR_MEM8(0xB1) ++ ++#define SFID4B _SFR_MEM8(0xB2) ++ ++#define WUP1B _SFR_MEM8(0xB3) ++ ++#define WUP2B _SFR_MEM8(0xB4) ++ ++#define WUP3B _SFR_MEM8(0xB5) ++ ++#define WUP4B _SFR_MEM8(0xB6) ++ ++#define SFIDCA _SFR_MEM8(0xB7) ++#define SFIDTA0 0 ++#define SFIDTA1 1 ++#define SFIDTA2 2 ++#define SFIDTA3 3 ++#define SFIDTA4 4 ++#define SEMEA 7 ++ ++#define SFIDLA _SFR_MEM8(0xB8) ++#define SFIDLA0 0 ++#define SFIDLA1 1 ++#define SFIDLA2 2 ++#define SFIDLA3 3 ++#define SFIDLA4 4 ++#define SFIDLA5 5 ++ ++#define WUPTA _SFR_MEM8(0xB9) ++#define WUPTA0 0 ++#define WUPTA1 1 ++#define WUPTA2 2 ++#define WUPTA3 3 ++#define WUPTA4 4 ++ ++#define WUPLA _SFR_MEM8(0xBA) ++#define WUPLA0 0 ++#define WUPLA1 1 ++#define WUPLA2 2 ++#define WUPLA3 3 ++#define WUPLA4 4 ++#define WUPLA5 5 ++ ++#define SFID1A _SFR_MEM8(0xBB) ++ ++#define SFID2A _SFR_MEM8(0xBC) ++ ++#define SFID3A _SFR_MEM8(0xBD) ++ ++#define SFID4A _SFR_MEM8(0xBE) ++ ++#define WUP1A _SFR_MEM8(0xBF) ++ ++#define WUP2A _SFR_MEM8(0xC0) ++ ++#define WUP3A _SFR_MEM8(0xC1) ++ ++#define WUP4A _SFR_MEM8(0xC2) ++ ++#define CLKOD _SFR_MEM8(0xC3) ++ ++#define CLKOCR _SFR_MEM8(0xC4) ++#define CLKOS0 0 ++#define CLKOS1 1 ++#define CLKOEN 2 ++ ++#define XFUSE _SFR_MEM8(0xC5) ++ ++#define SRCCAL _SFR_MEM8(0xC6) ++#define SRCCAL0 0 ++#define SRCCAL1 1 ++#define SRCCAL2 2 ++#define SRCCAL3 3 ++#define SRCCAL4 4 ++#define SRCCAL5 5 ++#define SRCTC0 6 ++#define SRCTC1 7 ++ ++#define FRCCAL _SFR_MEM8(0xC7) ++#define FRCCAL0 0 ++#define FRCCAL1 1 ++#define FRCCAL2 2 ++#define FRCCAL3 3 ++#define FRCCAL4 4 ++#define FRCTC 5 ++ ++#define CMSR _SFR_MEM8(0xC8) ++#define ECF 0 ++ ++#define CMOCR _SFR_MEM8(0xC9) ++#define FRCAO 0 ++#define SRCAO 1 ++#define FRCACT 2 ++#define SRCACT 3 ++ ++#define SUPFR _SFR_MEM8(0xCA) ++#define AVCCRF 0 ++#define AVCCLF 1 ++ ++#define SUPCR _SFR_MEM8(0xCB) ++#define AVCCRM 0 ++#define AVCCLM 1 ++#define PVEN 2 ++#define DVDIS 4 ++#define AVEN 5 ++#define AVDIC 6 ++ ++#define SUPCA1 _SFR_MEM8(0xCC) ++#define PV22 2 ++#define PVDIC 3 ++#define PVCAL0 4 ++#define PVCAL1 5 ++#define PVCAL2 6 ++#define PVCAL3 7 ++ ++#define SUPCA2 _SFR_MEM8(0xCD) ++#define BGCAL0 0 ++#define BGCAL1 1 ++#define BGCAL2 2 ++#define BGCAL3 3 ++ ++#define SUPCA3 _SFR_MEM8(0xCE) ++#define ACAL4 0 ++#define ACAL5 1 ++#define ACAL6 2 ++#define ACAL7 3 ++#define DCAL4 4 ++#define DCAL5 5 ++#define DCAL6 6 ++ ++#define SUPCA4 _SFR_MEM8(0xCF) ++#define ACAL0 0 ++#define ACAL1 1 ++#define ACAL2 2 ++#define ACAL3 3 ++#define DCAL0 4 ++#define DCAL1 5 ++#define DCAL2 6 ++#define DCAL3 7 ++ ++#define CALRDY _SFR_MEM8(0xD0) ++ ++#define VMCAL _SFR_MEM8(0xD1) ++#define VMCAL0 0 ++#define VMCAL1 1 ++#define VMCAL2 2 ++ ++#define DFS _SFR_MEM8(0xD2) ++#define DFFLRF 0 ++#define DFUFL 1 ++#define DFOFL 2 ++ ++/* Combine DFTLL and DFTLH */ ++#define DFTL _SFR_MEM16(0xD3) ++ ++#define DFTLL _SFR_MEM8(0xD3) ++#define DFTLH _SFR_MEM8(0xD4) ++ ++#define DFL _SFR_MEM8(0xD5) ++#define DFFLS0 0 ++#define DFFLS1 1 ++#define DFFLS2 2 ++#define DFFLS3 3 ++#define DFFLS4 4 ++#define DFFLS5 5 ++#define DFCLR 7 ++ ++#define DFWP _SFR_MEM8(0xD6) ++#define DFWP0 0 ++#define DFWP1 1 ++#define DFWP2 2 ++#define DFWP3 3 ++#define DFWP4 4 ++#define DFWP5 5 ++ ++#define DFRP _SFR_MEM8(0xD7) ++#define DFRP0 0 ++#define DFRP1 1 ++#define DFRP2 2 ++#define DFRP3 3 ++#define DFRP4 4 ++#define DFRP5 5 ++ ++#define DFD _SFR_MEM8(0xD8) ++ ++#define DFI _SFR_MEM8(0xD9) ++#define DFFLIM 0 ++#define DFERIM 1 ++ ++#define DFC _SFR_MEM8(0xDA) ++#define DFFLC0 0 ++#define DFFLC1 1 ++#define DFFLC2 2 ++#define DFFLC3 3 ++#define DFFLC4 4 ++#define DFFLC5 5 ++#define DFDRA 7 ++ ++#define SFS _SFR_MEM8(0xDB) ++#define SFFLRF 0 ++#define SFUFL 1 ++#define SFOFL 2 ++ ++#define SFL _SFR_MEM8(0xDC) ++#define SFFLS0 0 ++#define SFFLS1 1 ++#define SFFLS2 2 ++#define SFFLS3 3 ++#define SFFLS4 4 ++#define SFCLR 7 ++ ++#define SFWP _SFR_MEM8(0xDD) ++#define SFWP0 0 ++#define SFWP1 1 ++#define SFWP2 2 ++#define SFWP3 3 ++#define SFWP4 4 ++ ++#define SFRP _SFR_MEM8(0xDE) ++#define SFRP0 0 ++#define SFRP1 1 ++#define SFRP2 2 ++#define SFRP3 3 ++#define SFRP4 4 ++ ++#define SFD _SFR_MEM8(0xDF) ++ ++#define SFI _SFR_MEM8(0xE0) ++#define SFFLIM 0 ++#define SFERIM 1 ++ ++#define SFC _SFR_MEM8(0xE1) ++#define SFFLC0 0 ++#define SFFLC1 1 ++#define SFFLC2 2 ++#define SFFLC3 3 ++#define SFFLC4 4 ++#define SFDRA 7 ++ ++#define SSMCR _SFR_MEM8(0xE2) ++#define SSMTX 0 ++#define SSMTM 1 ++#define SSMTGE 2 ++#define SSMTPE 3 ++#define SSMPVE 4 ++#define SSMTAE 5 ++#define SETRPA 6 ++#define SETRPB 7 ++ ++#define SSMRCR _SFR_MEM8(0xE3) ++#define SSMPA 0 ++#define SSMPB 1 ++#define SSMADA 2 ++#define SSMADB 3 ++#define SSMPVS 4 ++#define SSMIFA 5 ++#define SSMIDSE 6 ++#define SSMTMOE 7 ++ ++#define SSMFBR _SFR_MEM8(0xE4) ++#define SSMFID0 0 ++#define SSMFID1 1 ++#define SSMFID2 2 ++#define SSMDFDT 3 ++#define SSMHADT 4 ++#define SSMPLDT 5 ++ ++#define SSMRR _SFR_MEM8(0xE5) ++#define SSMR 0 ++#define SSMST 1 ++ ++#define SSMSR _SFR_MEM8(0xE6) ++#define SSMESM0 0 ++#define SSMESM1 1 ++#define SSMESM2 2 ++#define SSMESM3 3 ++#define SSMERR 7 ++ ++#define SSMIFR _SFR_MEM8(0xE7) ++#define SSMIF 0 ++ ++#define SSMIMR _SFR_MEM8(0xE8) ++#define SSMIM 0 ++ ++#define MSMSTR _SFR_MEM8(0xE9) ++#define SSMMST0 0 ++#define SSMMST1 1 ++#define SSMMST2 2 ++#define SSMMST3 3 ++#define SSMMST4 4 ++ ++#define SSMSTR _SFR_MEM8(0xEA) ++#define SSMSTA0 0 ++#define SSMSTA1 1 ++#define SSMSTA2 2 ++#define SSMSTA3 3 ++#define SSMSTA4 4 ++#define SSMSTA5 5 ++ ++#define SSMXSR _SFR_MEM8(0xEB) ++#define SSMSTB0 0 ++#define SSMSTB1 1 ++#define SSMSTB2 2 ++#define SSMSTB3 3 ++#define SSMSTB4 4 ++#define SSMSTB5 5 ++ ++#define MSMCR1 _SFR_MEM8(0xEC) ++#define MSMSM00 0 ++#define MSMSM01 1 ++#define MSMSM02 2 ++#define MSMSM03 3 ++#define MSMSM10 4 ++#define MSMSM11 5 ++#define MSMSM12 6 ++#define MSMSM13 7 ++ ++#define MSMCR2 _SFR_MEM8(0xED) ++#define MSMSM20 0 ++#define MSMSM21 1 ++#define MSMSM22 2 ++#define MSMSM23 3 ++#define MSMSM30 4 ++#define MSMSM31 5 ++#define MSMSM32 6 ++#define MSMSM33 7 ++ ++#define MSMCR3 _SFR_MEM8(0xEE) ++#define MSMSM40 0 ++#define MSMSM41 1 ++#define MSMSM42 2 ++#define MSMSM43 3 ++#define MSMSM50 4 ++#define MSMSM51 5 ++#define MSMSM52 6 ++#define MSMSM53 7 ++ ++#define MSMCR4 _SFR_MEM8(0xEF) ++#define MSMSM60 0 ++#define MSMSM61 1 ++#define MSMSM62 2 ++#define MSMSM63 3 ++#define MSMSM70 4 ++#define MSMSM71 5 ++#define MSMSM72 6 ++#define MSMSM73 7 ++ ++#define GTCR _SFR_MEM8(0xF0) ++#define RXTEHA 0 ++#define GAPMA 1 ++#define DARA 2 ++#define IWUPA 3 ++#define RXTEHB 4 ++#define GAPMB 5 ++#define DARB 6 ++#define IWUPB 7 ++ ++#define SOTC1A _SFR_MEM8(0xF1) ++#define CAROEA1 0 ++#define AMPOEA1 1 ++#define SYTOEA1 2 ++#define MANOEA1 3 ++#define WUPEA1 4 ++#define SFIDEA1 5 ++#define RROEA1 6 ++#define WCOBOE1 7 ++ ++#define SOTC2A _SFR_MEM8(0xF2) ++#define CAROEA2 0 ++#define AMPOEA2 1 ++#define SYTOEA2 2 ++#define MANOEA2 3 ++#define WUPEA2 4 ++#define SFIDEA2 5 ++#define RROEA2 6 ++#define WCOBOE2 7 ++ ++#define SOTC1B _SFR_MEM8(0xF3) ++#define CAROEB1 0 ++#define AMPOEB1 1 ++#define SYTOEB1 2 ++#define MANOEB1 3 ++#define WUPEB1 4 ++#define SFIDEB1 5 ++#define RROEB1 6 ++#define WCOAOE1 7 ++ ++#define SOTC2B _SFR_MEM8(0xF4) ++#define CAROEB2 0 ++#define AMPOEB2 1 ++#define SYTOEB2 2 ++#define MANOEB2 3 ++#define WUPEB2 4 ++#define SFIDEB2 5 ++#define RROEB2 6 ++#define WCOAOE2 7 ++ ++#define EOTC1A _SFR_MEM8(0xF5) ++#define CARFEA1 0 ++#define AMPFEA1 1 ++#define SYTFEA1 2 ++#define MANFEA1 3 ++#define TMOFEA1 4 ++#define TELREA1 5 ++#define RRFEA1 6 ++#define EOTBFE1 7 ++ ++#define EOTC2A _SFR_MEM8(0xF6) ++#define CARFEA2 0 ++#define AMPFEA2 1 ++#define SYTFEA2 2 ++#define MANFEA2 3 ++#define TMOFEA2 4 ++#define TELREA2 5 ++#define RRFEA2 6 ++#define EOTBFE2 7 ++ ++#define EOTC3A _SFR_MEM8(0xF7) ++#define CARFEA3 0 ++#define AMPFEA3 1 ++#define SYTFEA3 2 ++#define MANFEA3 3 ++#define TMOFEA3 4 ++#define TELREA3 5 ++#define RRFEA3 6 ++#define EOTBFE3 7 ++ ++#define EOTC1B _SFR_MEM8(0xF8) ++#define CARFEB1 0 ++#define AMPFEB1 1 ++#define SYTFEB1 2 ++#define MANFEB1 3 ++#define TMOFEB1 4 ++#define TELREB1 5 ++#define RRFEB1 6 ++#define EOTAFE1 7 ++ ++#define EOTC2B _SFR_MEM8(0xF9) ++#define CARFEB2 0 ++#define AMPFEB2 1 ++#define SYTFEB2 2 ++#define MANFEB2 3 ++#define TMOFEB2 4 ++#define TELREB2 5 ++#define RRFEB2 6 ++#define EOTAFE2 7 ++ ++#define EOTC3B _SFR_MEM8(0xFA) ++#define CARFEB3 0 ++#define AMPFEB3 1 ++#define SYTFEB3 2 ++#define MANFEB3 3 ++#define TMOFEB3 4 ++#define TELREB3 5 ++#define RRFEB3 6 ++#define EOTAFE3 7 ++ ++#define WCOTOA _SFR_MEM8(0xFB) ++ ++#define WCOTOB _SFR_MEM8(0xFC) ++ ++#define SOTTOA _SFR_MEM8(0xFD) ++ ++#define SOTTOB _SFR_MEM8(0xFE) ++ ++#define SSMFCR _SFR_MEM8(0xFF) ++#define SSMIDSO 0 ++#define SSMIDSF 1 ++ ++#define FESR _SFR_MEM8(0x100) ++#define LBSAT 0 ++#define HBSAT 1 ++#define XRDY 2 ++#define PLCK 3 ++#define ANTS 4 ++ ++#define FEEN1 _SFR_MEM8(0x101) ++#define PLEN 0 ++#define PLCAL 1 ++#define XTOEN 2 ++#define LNAEN 3 ++#define ADEN 4 ++#define ADCLK 5 ++#define PLSP1 6 ++#define ATEN 7 ++ ++#define FEEN2 _SFR_MEM8(0x102) ++#define SDRX 0 ++#define SDTX 1 ++#define PAEN 2 ++#define TMPM 3 ++#define PLPEN 4 ++#define XTPEN 5 ++#define CPBIA 6 ++ ++#define FELNA _SFR_MEM8(0x103) ++#define LBH0 0 ++#define LBH1 1 ++#define LBH2 2 ++#define LBH3 3 ++#define LBL0 4 ++#define LBL1 5 ++#define LBL2 6 ++#define LBL3 7 ++ ++#define FEAT _SFR_MEM8(0x104) ++#define ANTN0 0 ++#define ANTN1 1 ++#define ANTN2 2 ++#define ANTN3 3 ++ ++#define FEPAC _SFR_MEM8(0x105) ++ ++#define FEVCT _SFR_MEM8(0x106) ++#define FEVCT0 0 ++#define FEVCT1 1 ++#define FEVCT2 2 ++#define FEVCT3 3 ++ ++#define FEBT _SFR_MEM8(0x107) ++#define CTN20 0 ++#define CTN21 1 ++#define RTN20 2 ++#define RTN21 3 ++ ++#define FEMS _SFR_MEM8(0x108) ++#define PLLS0 0 ++#define PLLS1 1 ++#define PLLS2 2 ++#define PLLS3 3 ++#define PLLM0 4 ++#define PLLM1 5 ++#define PLLM2 6 ++#define PLLM3 7 ++ ++#define FETN4 _SFR_MEM8(0x109) ++#define CTN40 0 ++#define CTN41 1 ++#define CTN42 2 ++#define CTN43 3 ++#define RTN40 4 ++#define RTN41 5 ++#define RTN42 6 ++#define RTN43 7 ++ ++#define FECR _SFR_MEM8(0x10A) ++#define LBNHB 0 ++#define S4N3 1 ++#define ANDP 2 ++#define ADHS 3 ++#define PLCKG 4 ++#define ANPS 5 ++ ++#define FEVCO _SFR_MEM8(0x10B) ++#define CPCC0 0 ++#define CPCC1 1 ++#define CPCC2 2 ++#define CPCC3 3 ++#define VCOB0 4 ++#define VCOB1 5 ++#define VCOB2 6 ++#define VCOB3 7 ++ ++#define FEALR _SFR_MEM8(0x10C) ++#define RNGE0 0 ++#define RNGE1 1 ++ ++#define FEANT _SFR_MEM8(0x10D) ++#define LVLC0 0 ++#define LVLC1 1 ++#define LVLC2 2 ++#define LVLC3 3 ++ ++#define FEBIA _SFR_MEM8(0x10E) ++#define IFAEN 7 ++ ++/* Reserved [0x10F..0x11F] */ ++ ++#define TMFSM _SFR_MEM8(0x120) ++#define TMSSM0 0 ++#define TMSSM1 1 ++#define TMSSM2 2 ++#define TMSSM3 3 ++#define TMMSM0 4 ++#define TMMSM1 5 ++#define TMMSM2 6 ++ ++/* Combine TMCRL and TMCRH */ ++#define TMCR _SFR_MEM16(0x121) ++ ++#define TMCRL _SFR_MEM8(0x121) ++#define TMCRH _SFR_MEM8(0x122) ++ ++#define TMCSB _SFR_MEM8(0x123) ++ ++/* Combine TMCIL and TMCIH */ ++#define TMCI _SFR_MEM16(0x124) ++ ++#define TMCIL _SFR_MEM8(0x124) ++#define TMCIH _SFR_MEM8(0x125) ++ ++/* Combine TMCPL and TMCPH */ ++#define TMCP _SFR_MEM16(0x126) ++ ++#define TMCPL _SFR_MEM8(0x126) ++#define TMCPH _SFR_MEM8(0x127) ++ ++#define TMSHR _SFR_MEM8(0x128) ++ ++/* Combine TMTLL and TMTLH */ ++#define TMTL _SFR_MEM16(0x129) ++ ++#define TMTLL _SFR_MEM8(0x129) ++#define TMTLH _SFR_MEM8(0x12A) ++ ++#define TMSSC _SFR_MEM8(0x12B) ++#define TMSSP0 0 ++#define TMSSP1 1 ++#define TMSSP2 2 ++#define TMSSP3 3 ++#define TMSSL0 4 ++#define TMSSL1 5 ++#define TMSSL2 6 ++#define TMSSH 7 ++ ++#define TMSR _SFR_MEM8(0x12C) ++#define TMTCF 0 ++ ++#define TMCR2 _SFR_MEM8(0x12D) ++#define TMCRCE 0 ++#define TMCRCL0 1 ++#define TMCRCL1 2 ++#define TMNRZE 3 ++#define TMPOL 4 ++#define TMSSE 5 ++#define TMMSB 6 ++ ++#define TMCR1 _SFR_MEM8(0x12E) ++#define TMPIS0 0 ++#define TMPIS1 1 ++#define TMPIS2 2 ++#define TMSCS 3 ++#define TMCIM 4 ++ ++#define RXBC1 _SFR_MEM8(0x12F) ++#define RXCEA 0 ++#define RXCBLA0 1 ++#define RXCBLA1 2 ++#define RXMSBA 3 ++#define RXCEB 4 ++#define RXCBLB0 5 ++#define RXCBLB1 6 ++#define RXMSBB 7 ++ ++#define RXBC2 _SFR_MEM8(0x130) ++#define RXBPB 0 ++#define RXBF 1 ++#define RXBCLR 2 ++ ++#define RXTLLB _SFR_MEM8(0x131) ++ ++#define RXTLHB _SFR_MEM8(0x132) ++#define RXTLHB0 0 ++#define RXTLHB1 1 ++#define RXTLHB2 2 ++#define RXTLHB3 3 ++ ++#define RXCRLB _SFR_MEM8(0x133) ++ ++#define RXCRHB _SFR_MEM8(0x134) ++ ++#define RXCSBB _SFR_MEM8(0x135) ++ ++#define RXCILB _SFR_MEM8(0x136) ++ ++#define RXCIHB _SFR_MEM8(0x137) ++ ++#define RXCPLB _SFR_MEM8(0x138) ++ ++#define RXCPHB _SFR_MEM8(0x139) ++ ++#define RXDSB _SFR_MEM8(0x13A) ++ ++#define RXTLLA _SFR_MEM8(0x13B) ++ ++#define RXTLHA _SFR_MEM8(0x13C) ++#define RXTLHA0 0 ++#define RXTLHA1 1 ++#define RXTLHA2 2 ++#define RXTLHA3 3 ++ ++#define RXCRLA _SFR_MEM8(0x13D) ++ ++#define RXCRHA _SFR_MEM8(0x13E) ++ ++#define RXCSBA _SFR_MEM8(0x13F) ++ ++#define RXCILA _SFR_MEM8(0x140) ++ ++#define RXCIHA _SFR_MEM8(0x141) ++ ++#define RXCPLA _SFR_MEM8(0x142) ++ ++#define RXCPHA _SFR_MEM8(0x143) ++ ++#define RXDSA _SFR_MEM8(0x144) ++ ++#define CRCCR _SFR_MEM8(0x145) ++#define CRCRS 0 ++#define REFLI 1 ++#define REFLO 2 ++ ++#define CRCDOR _SFR_MEM8(0x146) ++ ++#define IDB0 _SFR_MEM8(0x147) ++ ++#define IDB1 _SFR_MEM8(0x148) ++ ++#define IDB2 _SFR_MEM8(0x149) ++ ++#define IDB3 _SFR_MEM8(0x14A) ++ ++#define IDC _SFR_MEM8(0x14B) ++#define IDL0 0 ++#define IDL1 1 ++#define IDBO0 2 ++#define IDBO1 3 ++#define IDFIM 5 ++#define IDCLR 6 ++#define IDCE 7 ++ ++#define IDS _SFR_MEM8(0x14C) ++#define IDOK 0 ++#define IDFULL 1 ++ ++#define RSSAV _SFR_MEM8(0x14D) ++ ++#define RSSPK _SFR_MEM8(0x14E) ++ ++#define RSSL _SFR_MEM8(0x14F) ++ ++#define RSSH _SFR_MEM8(0x150) ++ ++#define RSSC _SFR_MEM8(0x151) ++#define RSUP0 0 ++#define RSUP1 1 ++#define RSUP2 2 ++#define RSUP3 3 ++#define RSWLH 4 ++#define RSHRX 5 ++#define RSPKF 6 ++ ++#define DBCR _SFR_MEM8(0x152) ++#define DBMD 0 ++#define DBCS 1 ++#define DBTMS 2 ++#define DBHA 3 ++ ++#define DBTC _SFR_MEM8(0x153) ++ ++#define DBENB _SFR_MEM8(0x154) ++ ++#define DBENC _SFR_MEM8(0x155) ++ ++#define DBGSW _SFR_MEM8(0x156) ++#define DBGGS0 0 ++#define DBGGS1 1 ++#define DBGGS2 2 ++#define DBGGS3 3 ++#define CPBFOS0 4 ++#define CPBFOS1 5 ++#define CPBF 6 ++#define DBGSE 7 ++ ++#define SFFR _SFR_MEM8(0x157) ++#define RFL0 0 ++#define RFL1 1 ++#define RFL2 2 ++#define RFC 3 ++#define TFL0 4 ++#define TFL1 5 ++#define TFL2 6 ++#define TFC 7 ++ ++#define SFIR _SFR_MEM8(0x158) ++#define RIL0 0 ++#define RIL1 1 ++#define RIL2 2 ++#define SRIE 3 ++#define TIL0 4 ++#define TIL1 5 ++#define TIL2 6 ++#define STIE 7 ++ ++#define EECR2 _SFR_MEM8(0x159) ++#define EEBRE 0 ++ ++#define PGMST _SFR_MEM8(0x15A) ++#define PGMSYN0 0 ++#define PGMSYN1 1 ++#define PGMSYN2 2 ++#define PGMSYN3 3 ++#define PGMSYN4 4 ++ ++#define EEST _SFR_MEM8(0x15B) ++#define EESYN0 0 ++#define EESYN1 1 ++#define EESYN2 2 ++#define EESYN3 3 ++ ++#define RSIFG _SFR_MEM8(0x15C) ++ ++#define RSLDV _SFR_MEM8(0x15D) ++ ++#define RSHDV _SFR_MEM8(0x15E) ++ ++#define RSCOM _SFR_MEM8(0x15F) ++#define RSDC 0 ++#define RSIFC 1 ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCI0_vect _VECTOR(3) ++#define PCI0_vect_num 3 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCI1_vect _VECTOR(4) ++#define PCI1_vect_num 4 ++ ++/* Voltage Monitoring Interrupt */ ++#define VMON_vect _VECTOR(5) ++#define VMON_vect_num 5 ++ ++/* AVCC Reset Interrupt */ ++#define AVCCR_vect _VECTOR(6) ++#define AVCCR_vect_num 6 ++ ++/* AVCC Low Interrupt */ ++#define AVCCL_vect _VECTOR(7) ++#define AVCCL_vect_num 7 ++ ++/* Timer 0 Interval Interrupt */ ++#define T0INT_vect _VECTOR(8) ++#define T0INT_vect_num 8 ++ ++/* Timer/Counter1 Compare Match Interrupt */ ++#define T1COMP_vect _VECTOR(9) ++#define T1COMP_vect_num 9 ++ ++/* Timer/Counter1 Overflow Interrupt */ ++#define T1OVF_vect _VECTOR(10) ++#define T1OVF_vect_num 10 ++ ++/* Timer/Counter2 Compare Match Interrupt */ ++#define T2COMP_vect _VECTOR(11) ++#define T2COMP_vect_num 11 ++ ++/* Timer/Counter2 Overflow Interrupt */ ++#define T2OVF_vect _VECTOR(12) ++#define T2OVF_vect_num 12 ++ ++/* Timer/Counter3 Capture Event Interrupt */ ++#define T3CAP_vect _VECTOR(13) ++#define T3CAP_vect_num 13 ++ ++/* Timer/Counter3 Compare Match Interrupt */ ++#define T3COMP_vect _VECTOR(14) ++#define T3COMP_vect_num 14 ++ ++/* Timer/Counter3 Overflow Interrupt */ ++#define T3OVF_vect _VECTOR(15) ++#define T3OVF_vect_num 15 ++ ++/* Timer/Counter4 Capture Event Interrupt */ ++#define T4CAP_vect _VECTOR(16) ++#define T4CAP_vect_num 16 ++ ++/* Timer/Counter4 Compare Match Interrupt */ ++#define T4COMP_vect _VECTOR(17) ++#define T4COMP_vect_num 17 ++ ++/* Timer/Counter4 Overflow Interrupt */ ++#define T4OVF_vect _VECTOR(18) ++#define T4OVF_vect_num 18 ++ ++/* Timer/Counter5 Compare Match Interrupt */ ++#define T5COMP_vect _VECTOR(19) ++#define T5COMP_vect_num 19 ++ ++/* Timer/Counter5 Overflow Interrupt */ ++#define T5OVF_vect _VECTOR(20) ++#define T5OVF_vect_num 20 ++ ++/* SPI Serial Transfer Complete Interrupt */ ++#define SPI_vect _VECTOR(21) ++#define SPI_vect_num 21 ++ ++/* SPI Rx Buffer Interrupt */ ++#define SRX_FIFO_vect _VECTOR(22) ++#define SRX_FIFO_vect_num 22 ++ ++/* SPI Tx Buffer Interrupt */ ++#define STX_FIFO_vect _VECTOR(23) ++#define STX_FIFO_vect_num 23 ++ ++/* Sequencer State Machine Interrupt */ ++#define SSM_vect _VECTOR(24) ++#define SSM_vect_num 24 ++ ++/* Data FIFO fill level reached Interrupt */ ++#define DFFLR_vect _VECTOR(25) ++#define DFFLR_vect_num 25 ++ ++/* Data FIFO overflow or underflow error Interrupt */ ++#define DFOUE_vect _VECTOR(26) ++#define DFOUE_vect_num 26 ++ ++/* RSSI/Preamble FIFO fill level reached Interrupt */ ++#define SFFLR_vect _VECTOR(27) ++#define SFFLR_vect_num 27 ++ ++/* RSSI/Preamble FIFO overflow or underflow error Interrupt */ ++#define SFOUE_vect _VECTOR(28) ++#define SFOUE_vect_num 28 ++ ++/* Tx Modulator Telegram Finish Interrupt */ ++#define TMTCF_vect _VECTOR(29) ++#define TMTCF_vect_num 29 ++ ++/* UHF receiver wake up ok on Rx path B */ ++#define UHF_WCOB_vect _VECTOR(30) ++#define UHF_WCOB_vect_num 30 ++ ++/* UHF receiver wake up ok on Rx path A */ ++#define UHF_WCOA_vect _VECTOR(31) ++#define UHF_WCOA_vect_num 31 ++ ++/* UHF receiver start of telegram ok on Rx path B */ ++#define UHF_SOTB_vect _VECTOR(32) ++#define UHF_SOTB_vect_num 32 ++ ++/* UHF receiver start of telegram ok on Rx path A */ ++#define UHF_SOTA_vect _VECTOR(33) ++#define UHF_SOTA_vect_num 33 ++ ++/* UHF receiver end of telegram on Rx path B */ ++#define UHF_EOTB_vect _VECTOR(34) ++#define UHF_EOTB_vect_num 34 ++ ++/* UHF receiver end of telegram on Rx path A */ ++#define UHF_EOTA_vect _VECTOR(35) ++#define UHF_EOTA_vect_num 35 ++ ++/* UHF receiver new bit on Rx path B */ ++#define UHF_NBITB_vect _VECTOR(36) ++#define UHF_NBITB_vect_num 36 ++ ++/* UHF receiver new bit on Rx path A */ ++#define UHF_NBITA_vect _VECTOR(37) ++#define UHF_NBITA_vect_num 37 ++ ++/* External input Clock monitoring Interrupt */ ++#define EXCM_vect _VECTOR(38) ++#define EXCM_vect_num 38 ++ ++/* EEPROM Ready Interrupt */ ++#define ERDY_vect _VECTOR(39) ++#define ERDY_vect_num 39 ++ ++/* Store Program Memory Ready */ ++#define SPMR_vect _VECTOR(40) ++#define SPMR_vect_num 40 ++ ++/* IDSCAN Full Interrupt */ ++#define IDFULL_vect _VECTOR(41) ++#define IDFULL_vect_num 41 ++ ++#define _VECTORS_SIZE 168 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 64 ++#define FLASHSTART 0x8000 ++#define FLASHEND 0xCFFF ++#define RAMSTART 0x0200 ++#define RAMSIZE 1024 ++#define RAMEND 0x05FF ++#define E2START 0 ++#define E2SIZE 1152 ++#define E2PAGESIZE 16 ++#define E2END 0x047F ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Fuse Byte */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(128) ++#define FUSE_DWEN (unsigned char)~_BV(64) ++#define FUSE_SPIEN (unsigned char)~_BV(32) ++#define FUSE_WDTON (unsigned char)~_BV(16) ++#define FUSE_EESAVE (unsigned char)~_BV(8) ++#define FUSE_BOOTRST (unsigned char)~_BV(4) ++#define FUSE_RSTDISBL (unsigned char)~_BV(2) ++#define FUSE_EXTCLKEN (unsigned char)~_BV(1) ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x62 ++ ++ ++#endif /* #ifdef _AVR_ATA5832_H_INCLUDED */ ++ +diff --git a/include/avr/ioa5833.h b/include/avr/ioa5833.h +new file mode 100644 +index 0000000..d15fcc8 +--- /dev/null ++++ b/include/avr/ioa5833.h +@@ -0,0 +1,1885 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATA5833_H_INCLUDED ++#define _AVR_ATA5833_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "ioa5833.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PRR0 _SFR_IO8(0x01) ++#define PRSPI 0 ++#define PRRXDC 1 ++#define PRTXDC 2 ++#define PRCRC 3 ++#define PRVM 4 ++#define PRCO 5 ++ ++#define PRR1 _SFR_IO8(0x02) ++#define PRT1 0 ++#define PRT2 1 ++#define PRT3 2 ++#define PRT4 3 ++#define PRT5 4 ++ ++#define PRR2 _SFR_IO8(0x03) ++#define PRXB 0 ++#define PRXA 1 ++#define PRSF 2 ++#define PRDF 3 ++#define PRIDS 4 ++#define PRRS 5 ++#define PRTM 6 ++#define PRSSM 7 ++ ++#define RDPR _SFR_IO8(0x04) ++#define PRPTB 0 ++#define PRPTA 1 ++#define PRFLT 2 ++#define PRTMP 3 ++#define APRPTB 4 ++#define APRPTA 5 ++#define ARDPRF 6 ++#define RDPRF 7 ++ ++#define PINB _SFR_IO8(0x05) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x06) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x07) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x08) ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x09) ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x0A) ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define FSCR _SFR_IO8(0x0B) ++#define TXMOD 0 ++#define SFM 1 ++#define TXMS0 2 ++#define TXMS1 3 ++#define PAOER 4 ++#define PAON 7 ++ ++/* Reserved [0x0C] */ ++ ++#define RDSIFR _SFR_IO8(0x0D) ++#define NBITA 0 ++#define NBITB 1 ++#define EOTA 2 ++#define EOTB 3 ++#define SOTA 4 ++#define SOTB 5 ++#define WCOA 6 ++#define WCOB 7 ++ ++#define MCUCR _SFR_IO8(0x0E) ++#define IVCE 0 ++#define IVSEL 1 ++#define SPIIO 2 ++#define ENPS 3 ++#define PUD 4 ++#define PB4HS 5 ++#define PB7LS 6 ++#define PB7HS 7 ++ ++#define PCIFR _SFR_IO8(0x0F) ++#define PCIF0 0 ++#define PCIF1 1 ++ ++#define T0CR _SFR_IO8(0x10) ++#define T0PS0 0 ++#define T0PS1 1 ++#define T0PS2 2 ++#define T0IE 3 ++#define T0PR 4 ++ ++#define T1CR _SFR_IO8(0x11) ++#define T1OTM 0 ++#define T1CTM 1 ++#define T1CRM 2 ++#define T1TOP 4 ++#define T1RES 5 ++#define T1TOS 6 ++#define T1ENA 7 ++ ++#define T2CR _SFR_IO8(0x12) ++#define T2OTM 0 ++#define T2CTM 1 ++#define T2CRM 2 ++#define T2TOP 4 ++#define T2RES 5 ++#define T2TOS 6 ++#define T2ENA 7 ++ ++#define T3CR _SFR_IO8(0x13) ++#define T3OTM 0 ++#define T3CTM 1 ++#define T3CRM 2 ++#define T3CPRM 3 ++#define T3TOP 4 ++#define T3RES 5 ++#define T3TOS 6 ++#define T3ENA 7 ++ ++#define T4CR _SFR_IO8(0x14) ++#define T4OTM 0 ++#define T4CTM 1 ++#define T4CRM 2 ++#define T4CPRM 3 ++#define T4TOP 4 ++#define T4RES 5 ++#define T4TOS 6 ++#define T4ENA 7 ++ ++#define T1IFR _SFR_IO8(0x15) ++#define T1OFF 0 ++#define T1COF 1 ++ ++#define T2IFR _SFR_IO8(0x16) ++#define T2OFF 0 ++#define T2COF 1 ++ ++#define T3IFR _SFR_IO8(0x17) ++#define T3OFF 0 ++#define T3COF 1 ++#define T3ICF 2 ++ ++#define T4IFR _SFR_IO8(0x18) ++#define T4OFF 0 ++#define T4COF 1 ++#define T4ICF 2 ++ ++#define T5IFR _SFR_IO8(0x19) ++#define T5OFF 0 ++#define T5COF 1 ++ ++#define GPIOR0 _SFR_IO8(0x1A) ++ ++#define GPIOR3 _SFR_IO8(0x1B) ++ ++#define GPIOR4 _SFR_IO8(0x1C) ++ ++#define GPIOR5 _SFR_IO8(0x1D) ++ ++#define GPIOR6 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++#define EEPAGE 6 ++#define NVMBSY 7 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define EEPR _SFR_IO8(0x23) ++#define EEAP0 0 ++#define EEAP1 1 ++#define EEAP2 2 ++#define EEAP3 3 ++ ++#define GPIOR1 _SFR_IO8(0x24) ++ ++#define GPIOR2 _SFR_IO8(0x25) ++ ++#define PCICR _SFR_IO8(0x26) ++#define PCIE0 0 ++#define PCIE1 1 ++ ++#define EIMSK _SFR_IO8(0x27) ++#define INT0 0 ++#define INT1 1 ++ ++#define EIFR _SFR_IO8(0x28) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define CRCDIR _SFR_IO8(0x29) ++ ++#define VMCSR _SFR_IO8(0x2A) ++#define VMLS0 0 ++#define VMLS1 1 ++#define VMLS2 2 ++#define VMLS3 3 ++#define VMIM 4 ++#define VMF 5 ++ ++#define MCUSR _SFR_IO8(0x2B) ++#define PORF 0 ++#define EXTRF 1 ++#define WDRF 3 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define RXIF 4 ++#define TXIF 5 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++#define T0IFR _SFR_IO8(0x2F) ++#define T0F 0 ++ ++/* Reserved [0x30] */ ++ ++#define DWDR _SFR_IO8(0x31) ++ ++/* Reserved [0x32] */ ++ ++#define RDCR _SFR_IO8(0x33) ++#define RDPU 0 ++#define ADIVEN 1 ++#define RDEN 2 ++ ++#define EOTSA _SFR_IO8(0x34) ++#define CARFA 0 ++#define AMPFA 1 ++#define SYTFA 2 ++#define MANFA 3 ++#define TMOFA 4 ++#define TELRA 5 ++#define RRFA 6 ++#define EOTBF 7 ++ ++#define EOTCA _SFR_IO8(0x35) ++#define CARFEA 0 ++#define AMPFEA 1 ++#define SYTFEA 2 ++#define MANFEA 3 ++#define TMOFEA 4 ++#define TELREA 5 ++#define RRFEA 6 ++#define EOTBFE 7 ++ ++#define EOTSB _SFR_IO8(0x36) ++#define CARFB 0 ++#define AMPFB 1 ++#define SYTFB 2 ++#define MANFB 3 ++#define TMOFB 4 ++#define TELRB 5 ++#define RRFB 6 ++#define EOTAF 7 ++ ++#define EOTCB _SFR_IO8(0x37) ++#define CARFEB 0 ++#define AMPFEB 1 ++#define SYTFEB 2 ++#define MANFEB 3 ++#define TMOFEB 4 ++#define TELREB 5 ++#define RRFEB 6 ++#define EOTAFE 7 ++ ++#define SMCR _SFR_IO8(0x38) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define CMCR _SFR_IO8(0x39) ++#define CMM0 0 ++#define CMM1 1 ++#define CMM2 2 ++#define CCS 3 ++#define SRCD 4 ++#define CMONEN 6 ++#define CMCCE 7 ++ ++#define CMIMR _SFR_IO8(0x3A) ++#define ECIE 0 ++ ++#define CLPR _SFR_IO8(0x3B) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLTPS0 3 ++#define CLTPS1 4 ++#define CLTPS2 5 ++#define CLPCE 7 ++ ++#define SPMCSR _SFR_IO8(0x3C) ++#define SELFPRGEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define SPMIE 7 ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define FSEN _SFR_MEM8(0x60) ++#define SDPU 0 ++#define SDEN 1 ++#define GAEN 2 ++#define PEEN 3 ++#define ASEN 4 ++#define ANTT 5 ++ ++#define FSFCR _SFR_MEM8(0x61) ++#define BTSEL0 0 ++#define BTSEL1 1 ++#define ASDIV0 4 ++#define ASDIV1 5 ++#define ASDIV2 6 ++#define ASDIV3 7 ++ ++/* Combine GACDIVL and GACDIVH */ ++#define GACDIV _SFR_MEM16(0x62) ++ ++#define GACDIVL _SFR_MEM8(0x62) ++#define GACDIVH _SFR_MEM8(0x63) ++ ++#define FFREQ1L _SFR_MEM8(0x64) ++ ++#define FFREQ1M _SFR_MEM8(0x65) ++ ++#define FFREQ1H _SFR_MEM8(0x66) ++ ++#define FFREQ2L _SFR_MEM8(0x67) ++ ++#define FFREQ2M _SFR_MEM8(0x68) ++ ++#define FFREQ2H _SFR_MEM8(0x69) ++ ++/* Reserved [0x6A] */ ++ ++#define EICRA _SFR_MEM8(0x6B) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++#define PCMSK0 _SFR_MEM8(0x6C) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6D) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++ ++#define WDTCR _SFR_MEM8(0x6E) ++#define WDPS0 0 ++#define WDPS1 1 ++#define WDPS2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define T1CNT _SFR_MEM8(0x6F) ++ ++#define T1COR _SFR_MEM8(0x70) ++ ++#define T1MR _SFR_MEM8(0x71) ++#define T1CS0 0 ++#define T1CS1 1 ++#define T1PS0 2 ++#define T1PS1 3 ++#define T1PS2 4 ++#define T1PS3 5 ++#define T1DC0 6 ++#define T1DC1 7 ++ ++#define T1IMR _SFR_MEM8(0x72) ++#define T1OIM 0 ++#define T1CIM 1 ++ ++#define T2CNT _SFR_MEM8(0x73) ++ ++#define T2COR _SFR_MEM8(0x74) ++ ++#define T2MR _SFR_MEM8(0x75) ++#define T2CS0 0 ++#define T2CS1 1 ++#define T2PS0 2 ++#define T2PS1 3 ++#define T2PS2 4 ++#define T2PS3 5 ++#define T2DC0 6 ++#define T2DC1 7 ++ ++#define T2IMR _SFR_MEM8(0x76) ++#define T2OIM 0 ++#define T2CIM 1 ++ ++/* Combine T3CNTL and T3CNTH */ ++#define T3CNT _SFR_MEM16(0x77) ++ ++#define T3CNTL _SFR_MEM8(0x77) ++#define T3CNTH _SFR_MEM8(0x78) ++ ++/* Combine T3CORL and T3CORH */ ++#define T3COR _SFR_MEM16(0x79) ++ ++#define T3CORL _SFR_MEM8(0x79) ++#define T3CORH _SFR_MEM8(0x7A) ++ ++/* Combine T3ICRL and T3ICRH */ ++#define T3ICR _SFR_MEM16(0x7B) ++ ++#define T3ICRL _SFR_MEM8(0x7B) ++#define T3ICRH _SFR_MEM8(0x7C) ++ ++#define T3MRA _SFR_MEM8(0x7D) ++#define T3CS0 0 ++#define T3CS1 1 ++#define T3PS0 2 ++#define T3PS1 3 ++#define T3PS2 4 ++ ++#define T3MRB _SFR_MEM8(0x7E) ++#define T3SCE 1 ++#define T3CNC 2 ++#define T3CE0 3 ++#define T3CE1 4 ++#define T3ICS0 5 ++#define T3ICS1 6 ++#define T3ICS2 7 ++ ++#define T3IMR _SFR_MEM8(0x7F) ++#define T3OIM 0 ++#define T3CIM 1 ++#define T3CPIM 2 ++ ++/* Combine T4CNTL and T4CNTH */ ++#define T4CNT _SFR_MEM16(0x80) ++ ++#define T4CNTL _SFR_MEM8(0x80) ++#define T4CNTH _SFR_MEM8(0x81) ++ ++/* Combine T4CORL and T4CORH */ ++#define T4COR _SFR_MEM16(0x82) ++ ++#define T4CORL _SFR_MEM8(0x82) ++#define T4CORH _SFR_MEM8(0x83) ++ ++/* Combine T4ICRL and T4ICRH */ ++#define T4ICR _SFR_MEM16(0x84) ++ ++#define T4ICRL _SFR_MEM8(0x84) ++#define T4ICRH _SFR_MEM8(0x85) ++ ++#define T4MRA _SFR_MEM8(0x86) ++#define T4CS0 0 ++#define T4CS1 1 ++#define T4PS0 2 ++#define T4PS1 3 ++#define T4PS2 4 ++ ++#define T4MRB _SFR_MEM8(0x87) ++#define T4SCE 1 ++#define T4CNC 2 ++#define T4CE0 3 ++#define T4CE1 4 ++#define T4ICS0 5 ++#define T4ICS1 6 ++#define T4ICS2 7 ++ ++#define T4IMR _SFR_MEM8(0x88) ++#define T4OIM 0 ++#define T4CIM 1 ++#define T4CPIM 2 ++ ++/* Reserved [0x89] */ ++ ++/* Combine T5OCRL and T5OCRH */ ++#define T5OCR _SFR_MEM16(0x8A) ++ ++#define T5OCRL _SFR_MEM8(0x8A) ++#define T5OCRH _SFR_MEM8(0x8B) ++ ++#define T5CCR _SFR_MEM8(0x8C) ++#define T5CS0 0 ++#define T5CS1 1 ++#define T5CS2 2 ++#define T5CTC 3 ++ ++/* Combine T5CNTL and T5CNTH */ ++#define T5CNT _SFR_MEM16(0x8D) ++ ++#define T5CNTL _SFR_MEM8(0x8D) ++#define T5CNTH _SFR_MEM8(0x8E) ++ ++#define T5IMR _SFR_MEM8(0x8F) ++#define T5OIM 0 ++#define T5CIM 1 ++ ++#define GTCCR _SFR_MEM8(0x90) ++#define PSR10 0 ++#define TSM 7 ++ ++#define SOTSB _SFR_MEM8(0x91) ++#define CAROB 0 ++#define AMPOB 1 ++#define SYTOB 2 ++#define MANOB 3 ++#define WUPOB 4 ++#define SFIDOB 5 ++#define RROB 6 ++#define WCOAO 7 ++ ++#define SOTSA _SFR_MEM8(0x92) ++#define CAROA 0 ++#define AMPOA 1 ++#define SYTOA 2 ++#define MANOA 3 ++#define WUPOA 4 ++#define SFIDOA 5 ++#define RROA 6 ++#define WCOBO 7 ++ ++#define SOTCB _SFR_MEM8(0x93) ++#define CAROEB 0 ++#define AMPOEB 1 ++#define SYTOEB 2 ++#define MANOEB 3 ++#define WUPEB 4 ++#define SFIDEB 5 ++#define RROEB 6 ++#define WCOAOE 7 ++ ++#define SOTCA _SFR_MEM8(0x94) ++#define CAROEA 0 ++#define AMPOEA 1 ++#define SYTOEA 2 ++#define MANOEA 3 ++#define WUPEA 4 ++#define SFIDEA 5 ++#define RROEA 6 ++#define WCOBOE 7 ++ ++#define TESRB _SFR_MEM8(0x95) ++#define CRCOB 0 ++#define EOTLB0 1 ++#define EOTLB1 2 ++ ++#define TESRA _SFR_MEM8(0x96) ++#define CRCOA 0 ++#define EOTLA0 1 ++#define EOTLA1 2 ++ ++/* Reserved [0x97] */ ++ ++#define RDSIMR _SFR_MEM8(0x98) ++#define NBITAM 0 ++#define NBITBM 1 ++#define EOTAM 2 ++#define EOTBM 3 ++#define SOTAM 4 ++#define SOTBM 5 ++#define WCOAM 6 ++#define WCOBM 7 ++ ++#define RDOCR _SFR_MEM8(0x99) ++#define TMDS0 1 ++#define TMDS1 2 ++#define ETRPA 3 ++#define ETRPB 4 ++#define RDSIDA 5 ++#define RDSIDB 6 ++ ++/* Reserved [0x9A] */ ++ ++#define TEMPL _SFR_MEM8(0x9B) ++ ++#define TEMPH _SFR_MEM8(0x9C) ++ ++#define SYCB _SFR_MEM8(0x9D) ++#define SYCSB0 0 ++#define SYCSB1 1 ++#define SYCSB2 2 ++#define SYCSB3 3 ++#define SYTLB0 4 ++#define SYTLB1 5 ++#define SYTLB2 6 ++#define SYTLB3 7 ++ ++#define SYCA _SFR_MEM8(0x9E) ++#define SYCSA0 0 ++#define SYCSA1 1 ++#define SYCSA2 2 ++#define SYCSA3 3 ++#define SYTLA0 4 ++#define SYTLA1 5 ++#define SYTLA2 6 ++#define SYTLA3 7 ++ ++#define RXFOB _SFR_MEM8(0x9F) ++ ++#define RXFOA _SFR_MEM8(0xA0) ++ ++#define DMMB _SFR_MEM8(0xA1) ++#define DMATB0 0 ++#define DMATB1 1 ++#define DMATB2 2 ++#define DMATB3 3 ++#define DMATB4 4 ++#define DMPB 5 ++#define DMHB 6 ++#define DMNEB 7 ++ ++#define DMMA _SFR_MEM8(0xA2) ++#define DMATA0 0 ++#define DMATA1 1 ++#define DMATA2 2 ++#define DMATA3 3 ++#define DMATA4 4 ++#define DMPA 5 ++#define DMHA 6 ++#define DMNEA 7 ++ ++#define DMCDB _SFR_MEM8(0xA3) ++#define DMCLB0 0 ++#define DMCLB1 1 ++#define DMCLB2 2 ++#define DMCLB3 3 ++#define DMCLB4 4 ++#define DMCTB0 5 ++#define DMCTB1 6 ++#define DMCTB2 7 ++ ++#define DMCDA _SFR_MEM8(0xA4) ++#define DMCLA0 0 ++#define DMCLA1 1 ++#define DMCLA2 2 ++#define DMCLA3 3 ++#define DMCLA4 4 ++#define DMCTA0 5 ++#define DMCTA1 6 ++#define DMCTA2 7 ++ ++#define DMCRB _SFR_MEM8(0xA5) ++#define DMPGB0 0 ++#define DMPGB1 1 ++#define DMPGB2 2 ++#define DMPGB3 3 ++#define DMPGB4 4 ++#define SASKB 5 ++#define SY1TB 6 ++#define DMARB 7 ++ ++#define DMCRA _SFR_MEM8(0xA6) ++#define DMPGA0 0 ++#define DMPGA1 1 ++#define DMPGA2 2 ++#define DMPGA3 3 ++#define DMPGA4 4 ++#define SASKA 5 ++#define SY1TA 6 ++#define DMARA 7 ++ ++#define DMDRB _SFR_MEM8(0xA7) ++#define DMAB0 0 ++#define DMAB1 1 ++#define DMAB2 2 ++#define DMAB3 3 ++#define DMDNB0 4 ++#define DMDNB1 5 ++#define DMDNB2 6 ++#define DMDNB3 7 ++ ++#define DMDRA _SFR_MEM8(0xA8) ++#define DMAA0 0 ++#define DMAA1 1 ++#define DMAA2 2 ++#define DMAA3 3 ++#define DMDNA0 4 ++#define DMDNA1 5 ++#define DMDNA2 6 ++#define DMDNA3 7 ++ ++#define CHCR _SFR_MEM8(0xA9) ++#define BWM0 0 ++#define BWM1 1 ++#define BWM2 2 ++#define BWM3 3 ++ ++#define CHDN _SFR_MEM8(0xAA) ++#define BBDN0 0 ++#define BBDN1 1 ++#define BBDN2 2 ++#define BBDN3 3 ++#define BBDN4 4 ++#define ADCDN 5 ++ ++#define SFIDCB _SFR_MEM8(0xAB) ++#define SFIDTB0 0 ++#define SFIDTB1 1 ++#define SFIDTB2 2 ++#define SFIDTB3 3 ++#define SFIDTB4 4 ++#define SEMEB 7 ++ ++#define SFIDLB _SFR_MEM8(0xAC) ++#define SFIDLB0 0 ++#define SFIDLB1 1 ++#define SFIDLB2 2 ++#define SFIDLB3 3 ++#define SFIDLB4 4 ++#define SFIDLB5 5 ++ ++#define WUPTB _SFR_MEM8(0xAD) ++#define WUPTB0 0 ++#define WUPTB1 1 ++#define WUPTB2 2 ++#define WUPTB3 3 ++#define WUPTB4 4 ++ ++#define WUPLB _SFR_MEM8(0xAE) ++#define WUPLB0 0 ++#define WUPLB1 1 ++#define WUPLB2 2 ++#define WUPLB3 3 ++#define WUPLB4 4 ++#define WUPLB5 5 ++ ++#define SFID1B _SFR_MEM8(0xAF) ++ ++#define SFID2B _SFR_MEM8(0xB0) ++ ++#define SFID3B _SFR_MEM8(0xB1) ++ ++#define SFID4B _SFR_MEM8(0xB2) ++ ++#define WUP1B _SFR_MEM8(0xB3) ++ ++#define WUP2B _SFR_MEM8(0xB4) ++ ++#define WUP3B _SFR_MEM8(0xB5) ++ ++#define WUP4B _SFR_MEM8(0xB6) ++ ++#define SFIDCA _SFR_MEM8(0xB7) ++#define SFIDTA0 0 ++#define SFIDTA1 1 ++#define SFIDTA2 2 ++#define SFIDTA3 3 ++#define SFIDTA4 4 ++#define SEMEA 7 ++ ++#define SFIDLA _SFR_MEM8(0xB8) ++#define SFIDLA0 0 ++#define SFIDLA1 1 ++#define SFIDLA2 2 ++#define SFIDLA3 3 ++#define SFIDLA4 4 ++#define SFIDLA5 5 ++ ++#define WUPTA _SFR_MEM8(0xB9) ++#define WUPTA0 0 ++#define WUPTA1 1 ++#define WUPTA2 2 ++#define WUPTA3 3 ++#define WUPTA4 4 ++ ++#define WUPLA _SFR_MEM8(0xBA) ++#define WUPLA0 0 ++#define WUPLA1 1 ++#define WUPLA2 2 ++#define WUPLA3 3 ++#define WUPLA4 4 ++#define WUPLA5 5 ++ ++#define SFID1A _SFR_MEM8(0xBB) ++ ++#define SFID2A _SFR_MEM8(0xBC) ++ ++#define SFID3A _SFR_MEM8(0xBD) ++ ++#define SFID4A _SFR_MEM8(0xBE) ++ ++#define WUP1A _SFR_MEM8(0xBF) ++ ++#define WUP2A _SFR_MEM8(0xC0) ++ ++#define WUP3A _SFR_MEM8(0xC1) ++ ++#define WUP4A _SFR_MEM8(0xC2) ++ ++#define CLKOD _SFR_MEM8(0xC3) ++ ++#define CLKOCR _SFR_MEM8(0xC4) ++#define CLKOS0 0 ++#define CLKOS1 1 ++#define CLKOEN 2 ++ ++#define XFUSE _SFR_MEM8(0xC5) ++ ++#define SRCCAL _SFR_MEM8(0xC6) ++#define SRCCAL0 0 ++#define SRCCAL1 1 ++#define SRCCAL2 2 ++#define SRCCAL3 3 ++#define SRCCAL4 4 ++#define SRCCAL5 5 ++#define SRCTC0 6 ++#define SRCTC1 7 ++ ++#define FRCCAL _SFR_MEM8(0xC7) ++#define FRCCAL0 0 ++#define FRCCAL1 1 ++#define FRCCAL2 2 ++#define FRCCAL3 3 ++#define FRCCAL4 4 ++#define FRCTC 5 ++ ++#define CMSR _SFR_MEM8(0xC8) ++#define ECF 0 ++ ++#define CMOCR _SFR_MEM8(0xC9) ++#define FRCAO 0 ++#define SRCAO 1 ++#define FRCACT 2 ++#define SRCACT 3 ++ ++#define SUPFR _SFR_MEM8(0xCA) ++#define AVCCRF 0 ++#define AVCCLF 1 ++ ++#define SUPCR _SFR_MEM8(0xCB) ++#define AVCCRM 0 ++#define AVCCLM 1 ++#define PVEN 2 ++#define DVDIS 4 ++#define AVEN 5 ++#define AVDIC 6 ++ ++#define SUPCA1 _SFR_MEM8(0xCC) ++#define PV22 2 ++#define PVDIC 3 ++#define PVCAL0 4 ++#define PVCAL1 5 ++#define PVCAL2 6 ++#define PVCAL3 7 ++ ++#define SUPCA2 _SFR_MEM8(0xCD) ++#define BGCAL0 0 ++#define BGCAL1 1 ++#define BGCAL2 2 ++#define BGCAL3 3 ++ ++#define SUPCA3 _SFR_MEM8(0xCE) ++#define ACAL4 0 ++#define ACAL5 1 ++#define ACAL6 2 ++#define ACAL7 3 ++#define DCAL4 4 ++#define DCAL5 5 ++#define DCAL6 6 ++ ++#define SUPCA4 _SFR_MEM8(0xCF) ++#define ACAL0 0 ++#define ACAL1 1 ++#define ACAL2 2 ++#define ACAL3 3 ++#define DCAL0 4 ++#define DCAL1 5 ++#define DCAL2 6 ++#define DCAL3 7 ++ ++#define CALRDY _SFR_MEM8(0xD0) ++ ++#define VMCAL _SFR_MEM8(0xD1) ++#define VMCAL0 0 ++#define VMCAL1 1 ++#define VMCAL2 2 ++ ++#define DFS _SFR_MEM8(0xD2) ++#define DFFLRF 0 ++#define DFUFL 1 ++#define DFOFL 2 ++ ++/* Combine DFTLL and DFTLH */ ++#define DFTL _SFR_MEM16(0xD3) ++ ++#define DFTLL _SFR_MEM8(0xD3) ++#define DFTLH _SFR_MEM8(0xD4) ++ ++#define DFL _SFR_MEM8(0xD5) ++#define DFFLS0 0 ++#define DFFLS1 1 ++#define DFFLS2 2 ++#define DFFLS3 3 ++#define DFFLS4 4 ++#define DFFLS5 5 ++#define DFCLR 7 ++ ++#define DFWP _SFR_MEM8(0xD6) ++#define DFWP0 0 ++#define DFWP1 1 ++#define DFWP2 2 ++#define DFWP3 3 ++#define DFWP4 4 ++#define DFWP5 5 ++ ++#define DFRP _SFR_MEM8(0xD7) ++#define DFRP0 0 ++#define DFRP1 1 ++#define DFRP2 2 ++#define DFRP3 3 ++#define DFRP4 4 ++#define DFRP5 5 ++ ++#define DFD _SFR_MEM8(0xD8) ++ ++#define DFI _SFR_MEM8(0xD9) ++#define DFFLIM 0 ++#define DFERIM 1 ++ ++#define DFC _SFR_MEM8(0xDA) ++#define DFFLC0 0 ++#define DFFLC1 1 ++#define DFFLC2 2 ++#define DFFLC3 3 ++#define DFFLC4 4 ++#define DFFLC5 5 ++#define DFDRA 7 ++ ++#define SFS _SFR_MEM8(0xDB) ++#define SFFLRF 0 ++#define SFUFL 1 ++#define SFOFL 2 ++ ++#define SFL _SFR_MEM8(0xDC) ++#define SFFLS0 0 ++#define SFFLS1 1 ++#define SFFLS2 2 ++#define SFFLS3 3 ++#define SFFLS4 4 ++#define SFCLR 7 ++ ++#define SFWP _SFR_MEM8(0xDD) ++#define SFWP0 0 ++#define SFWP1 1 ++#define SFWP2 2 ++#define SFWP3 3 ++#define SFWP4 4 ++ ++#define SFRP _SFR_MEM8(0xDE) ++#define SFRP0 0 ++#define SFRP1 1 ++#define SFRP2 2 ++#define SFRP3 3 ++#define SFRP4 4 ++ ++#define SFD _SFR_MEM8(0xDF) ++ ++#define SFI _SFR_MEM8(0xE0) ++#define SFFLIM 0 ++#define SFERIM 1 ++ ++#define SFC _SFR_MEM8(0xE1) ++#define SFFLC0 0 ++#define SFFLC1 1 ++#define SFFLC2 2 ++#define SFFLC3 3 ++#define SFFLC4 4 ++#define SFDRA 7 ++ ++#define SSMCR _SFR_MEM8(0xE2) ++#define SSMTX 0 ++#define SSMTM 1 ++#define SSMTGE 2 ++#define SSMTPE 3 ++#define SSMPVE 4 ++#define SSMTAE 5 ++#define SETRPA 6 ++#define SETRPB 7 ++ ++#define SSMRCR _SFR_MEM8(0xE3) ++#define SSMPA 0 ++#define SSMPB 1 ++#define SSMADA 2 ++#define SSMADB 3 ++#define SSMPVS 4 ++#define SSMIFA 5 ++#define SSMIDSE 6 ++#define SSMTMOE 7 ++ ++#define SSMFBR _SFR_MEM8(0xE4) ++#define SSMFID0 0 ++#define SSMFID1 1 ++#define SSMFID2 2 ++#define SSMDFDT 3 ++#define SSMHADT 4 ++#define SSMPLDT 5 ++ ++#define SSMRR _SFR_MEM8(0xE5) ++#define SSMR 0 ++#define SSMST 1 ++ ++#define SSMSR _SFR_MEM8(0xE6) ++#define SSMESM0 0 ++#define SSMESM1 1 ++#define SSMESM2 2 ++#define SSMESM3 3 ++#define SSMERR 7 ++ ++#define SSMIFR _SFR_MEM8(0xE7) ++#define SSMIF 0 ++ ++#define SSMIMR _SFR_MEM8(0xE8) ++#define SSMIM 0 ++ ++#define MSMSTR _SFR_MEM8(0xE9) ++#define SSMMST0 0 ++#define SSMMST1 1 ++#define SSMMST2 2 ++#define SSMMST3 3 ++#define SSMMST4 4 ++ ++#define SSMSTR _SFR_MEM8(0xEA) ++#define SSMSTA0 0 ++#define SSMSTA1 1 ++#define SSMSTA2 2 ++#define SSMSTA3 3 ++#define SSMSTA4 4 ++#define SSMSTA5 5 ++ ++#define SSMXSR _SFR_MEM8(0xEB) ++#define SSMSTB0 0 ++#define SSMSTB1 1 ++#define SSMSTB2 2 ++#define SSMSTB3 3 ++#define SSMSTB4 4 ++#define SSMSTB5 5 ++ ++#define MSMCR1 _SFR_MEM8(0xEC) ++#define MSMSM00 0 ++#define MSMSM01 1 ++#define MSMSM02 2 ++#define MSMSM03 3 ++#define MSMSM10 4 ++#define MSMSM11 5 ++#define MSMSM12 6 ++#define MSMSM13 7 ++ ++#define MSMCR2 _SFR_MEM8(0xED) ++#define MSMSM20 0 ++#define MSMSM21 1 ++#define MSMSM22 2 ++#define MSMSM23 3 ++#define MSMSM30 4 ++#define MSMSM31 5 ++#define MSMSM32 6 ++#define MSMSM33 7 ++ ++#define MSMCR3 _SFR_MEM8(0xEE) ++#define MSMSM40 0 ++#define MSMSM41 1 ++#define MSMSM42 2 ++#define MSMSM43 3 ++#define MSMSM50 4 ++#define MSMSM51 5 ++#define MSMSM52 6 ++#define MSMSM53 7 ++ ++#define MSMCR4 _SFR_MEM8(0xEF) ++#define MSMSM60 0 ++#define MSMSM61 1 ++#define MSMSM62 2 ++#define MSMSM63 3 ++#define MSMSM70 4 ++#define MSMSM71 5 ++#define MSMSM72 6 ++#define MSMSM73 7 ++ ++#define GTCR _SFR_MEM8(0xF0) ++#define RXTEHA 0 ++#define GAPMA 1 ++#define DARA 2 ++#define IWUPA 3 ++#define RXTEHB 4 ++#define GAPMB 5 ++#define DARB 6 ++#define IWUPB 7 ++ ++#define SOTC1A _SFR_MEM8(0xF1) ++#define CAROEA1 0 ++#define AMPOEA1 1 ++#define SYTOEA1 2 ++#define MANOEA1 3 ++#define WUPEA1 4 ++#define SFIDEA1 5 ++#define RROEA1 6 ++#define WCOBOE1 7 ++ ++#define SOTC2A _SFR_MEM8(0xF2) ++#define CAROEA2 0 ++#define AMPOEA2 1 ++#define SYTOEA2 2 ++#define MANOEA2 3 ++#define WUPEA2 4 ++#define SFIDEA2 5 ++#define RROEA2 6 ++#define WCOBOE2 7 ++ ++#define SOTC1B _SFR_MEM8(0xF3) ++#define CAROEB1 0 ++#define AMPOEB1 1 ++#define SYTOEB1 2 ++#define MANOEB1 3 ++#define WUPEB1 4 ++#define SFIDEB1 5 ++#define RROEB1 6 ++#define WCOAOE1 7 ++ ++#define SOTC2B _SFR_MEM8(0xF4) ++#define CAROEB2 0 ++#define AMPOEB2 1 ++#define SYTOEB2 2 ++#define MANOEB2 3 ++#define WUPEB2 4 ++#define SFIDEB2 5 ++#define RROEB2 6 ++#define WCOAOE2 7 ++ ++#define EOTC1A _SFR_MEM8(0xF5) ++#define CARFEA1 0 ++#define AMPFEA1 1 ++#define SYTFEA1 2 ++#define MANFEA1 3 ++#define TMOFEA1 4 ++#define TELREA1 5 ++#define RRFEA1 6 ++#define EOTBFE1 7 ++ ++#define EOTC2A _SFR_MEM8(0xF6) ++#define CARFEA2 0 ++#define AMPFEA2 1 ++#define SYTFEA2 2 ++#define MANFEA2 3 ++#define TMOFEA2 4 ++#define TELREA2 5 ++#define RRFEA2 6 ++#define EOTBFE2 7 ++ ++#define EOTC3A _SFR_MEM8(0xF7) ++#define CARFEA3 0 ++#define AMPFEA3 1 ++#define SYTFEA3 2 ++#define MANFEA3 3 ++#define TMOFEA3 4 ++#define TELREA3 5 ++#define RRFEA3 6 ++#define EOTBFE3 7 ++ ++#define EOTC1B _SFR_MEM8(0xF8) ++#define CARFEB1 0 ++#define AMPFEB1 1 ++#define SYTFEB1 2 ++#define MANFEB1 3 ++#define TMOFEB1 4 ++#define TELREB1 5 ++#define RRFEB1 6 ++#define EOTAFE1 7 ++ ++#define EOTC2B _SFR_MEM8(0xF9) ++#define CARFEB2 0 ++#define AMPFEB2 1 ++#define SYTFEB2 2 ++#define MANFEB2 3 ++#define TMOFEB2 4 ++#define TELREB2 5 ++#define RRFEB2 6 ++#define EOTAFE2 7 ++ ++#define EOTC3B _SFR_MEM8(0xFA) ++#define CARFEB3 0 ++#define AMPFEB3 1 ++#define SYTFEB3 2 ++#define MANFEB3 3 ++#define TMOFEB3 4 ++#define TELREB3 5 ++#define RRFEB3 6 ++#define EOTAFE3 7 ++ ++#define WCOTOA _SFR_MEM8(0xFB) ++ ++#define WCOTOB _SFR_MEM8(0xFC) ++ ++#define SOTTOA _SFR_MEM8(0xFD) ++ ++#define SOTTOB _SFR_MEM8(0xFE) ++ ++#define SSMFCR _SFR_MEM8(0xFF) ++#define SSMIDSO 0 ++#define SSMIDSF 1 ++ ++#define FESR _SFR_MEM8(0x100) ++#define LBSAT 0 ++#define HBSAT 1 ++#define XRDY 2 ++#define PLCK 3 ++#define ANTS 4 ++ ++#define FEEN1 _SFR_MEM8(0x101) ++#define PLEN 0 ++#define PLCAL 1 ++#define XTOEN 2 ++#define LNAEN 3 ++#define ADEN 4 ++#define ADCLK 5 ++#define PLSP1 6 ++#define ATEN 7 ++ ++#define FEEN2 _SFR_MEM8(0x102) ++#define SDRX 0 ++#define SDTX 1 ++#define PAEN 2 ++#define TMPM 3 ++#define PLPEN 4 ++#define XTPEN 5 ++#define CPBIA 6 ++ ++#define FELNA _SFR_MEM8(0x103) ++#define LBH0 0 ++#define LBH1 1 ++#define LBH2 2 ++#define LBH3 3 ++#define LBL0 4 ++#define LBL1 5 ++#define LBL2 6 ++#define LBL3 7 ++ ++#define FEAT _SFR_MEM8(0x104) ++#define ANTN0 0 ++#define ANTN1 1 ++#define ANTN2 2 ++#define ANTN3 3 ++ ++#define FEPAC _SFR_MEM8(0x105) ++ ++#define FEVCT _SFR_MEM8(0x106) ++#define FEVCT0 0 ++#define FEVCT1 1 ++#define FEVCT2 2 ++#define FEVCT3 3 ++ ++#define FEBT _SFR_MEM8(0x107) ++#define CTN20 0 ++#define CTN21 1 ++#define RTN20 2 ++#define RTN21 3 ++ ++#define FEMS _SFR_MEM8(0x108) ++#define PLLS0 0 ++#define PLLS1 1 ++#define PLLS2 2 ++#define PLLS3 3 ++#define PLLM0 4 ++#define PLLM1 5 ++#define PLLM2 6 ++#define PLLM3 7 ++ ++#define FETN4 _SFR_MEM8(0x109) ++#define CTN40 0 ++#define CTN41 1 ++#define CTN42 2 ++#define CTN43 3 ++#define RTN40 4 ++#define RTN41 5 ++#define RTN42 6 ++#define RTN43 7 ++ ++#define FECR _SFR_MEM8(0x10A) ++#define LBNHB 0 ++#define S4N3 1 ++#define ANDP 2 ++#define ADHS 3 ++#define PLCKG 4 ++#define ANPS 5 ++ ++#define FEVCO _SFR_MEM8(0x10B) ++#define CPCC0 0 ++#define CPCC1 1 ++#define CPCC2 2 ++#define CPCC3 3 ++#define VCOB0 4 ++#define VCOB1 5 ++#define VCOB2 6 ++#define VCOB3 7 ++ ++#define FEALR _SFR_MEM8(0x10C) ++#define RNGE0 0 ++#define RNGE1 1 ++ ++#define FEANT _SFR_MEM8(0x10D) ++#define LVLC0 0 ++#define LVLC1 1 ++#define LVLC2 2 ++#define LVLC3 3 ++ ++#define FEBIA _SFR_MEM8(0x10E) ++#define IFAEN 7 ++ ++/* Reserved [0x10F..0x11F] */ ++ ++#define TMFSM _SFR_MEM8(0x120) ++#define TMSSM0 0 ++#define TMSSM1 1 ++#define TMSSM2 2 ++#define TMSSM3 3 ++#define TMMSM0 4 ++#define TMMSM1 5 ++#define TMMSM2 6 ++ ++/* Combine TMCRL and TMCRH */ ++#define TMCR _SFR_MEM16(0x121) ++ ++#define TMCRL _SFR_MEM8(0x121) ++#define TMCRH _SFR_MEM8(0x122) ++ ++#define TMCSB _SFR_MEM8(0x123) ++ ++/* Combine TMCIL and TMCIH */ ++#define TMCI _SFR_MEM16(0x124) ++ ++#define TMCIL _SFR_MEM8(0x124) ++#define TMCIH _SFR_MEM8(0x125) ++ ++/* Combine TMCPL and TMCPH */ ++#define TMCP _SFR_MEM16(0x126) ++ ++#define TMCPL _SFR_MEM8(0x126) ++#define TMCPH _SFR_MEM8(0x127) ++ ++#define TMSHR _SFR_MEM8(0x128) ++ ++/* Combine TMTLL and TMTLH */ ++#define TMTL _SFR_MEM16(0x129) ++ ++#define TMTLL _SFR_MEM8(0x129) ++#define TMTLH _SFR_MEM8(0x12A) ++ ++#define TMSSC _SFR_MEM8(0x12B) ++#define TMSSP0 0 ++#define TMSSP1 1 ++#define TMSSP2 2 ++#define TMSSP3 3 ++#define TMSSL0 4 ++#define TMSSL1 5 ++#define TMSSL2 6 ++#define TMSSH 7 ++ ++#define TMSR _SFR_MEM8(0x12C) ++#define TMTCF 0 ++ ++#define TMCR2 _SFR_MEM8(0x12D) ++#define TMCRCE 0 ++#define TMCRCL0 1 ++#define TMCRCL1 2 ++#define TMNRZE 3 ++#define TMPOL 4 ++#define TMSSE 5 ++#define TMMSB 6 ++ ++#define TMCR1 _SFR_MEM8(0x12E) ++#define TMPIS0 0 ++#define TMPIS1 1 ++#define TMPIS2 2 ++#define TMSCS 3 ++#define TMCIM 4 ++ ++#define RXBC1 _SFR_MEM8(0x12F) ++#define RXCEA 0 ++#define RXCBLA0 1 ++#define RXCBLA1 2 ++#define RXMSBA 3 ++#define RXCEB 4 ++#define RXCBLB0 5 ++#define RXCBLB1 6 ++#define RXMSBB 7 ++ ++#define RXBC2 _SFR_MEM8(0x130) ++#define RXBPB 0 ++#define RXBF 1 ++#define RXBCLR 2 ++ ++#define RXTLLB _SFR_MEM8(0x131) ++ ++#define RXTLHB _SFR_MEM8(0x132) ++#define RXTLHB0 0 ++#define RXTLHB1 1 ++#define RXTLHB2 2 ++#define RXTLHB3 3 ++ ++#define RXCRLB _SFR_MEM8(0x133) ++ ++#define RXCRHB _SFR_MEM8(0x134) ++ ++#define RXCSBB _SFR_MEM8(0x135) ++ ++#define RXCILB _SFR_MEM8(0x136) ++ ++#define RXCIHB _SFR_MEM8(0x137) ++ ++#define RXCPLB _SFR_MEM8(0x138) ++ ++#define RXCPHB _SFR_MEM8(0x139) ++ ++#define RXDSB _SFR_MEM8(0x13A) ++ ++#define RXTLLA _SFR_MEM8(0x13B) ++ ++#define RXTLHA _SFR_MEM8(0x13C) ++#define RXTLHA0 0 ++#define RXTLHA1 1 ++#define RXTLHA2 2 ++#define RXTLHA3 3 ++ ++#define RXCRLA _SFR_MEM8(0x13D) ++ ++#define RXCRHA _SFR_MEM8(0x13E) ++ ++#define RXCSBA _SFR_MEM8(0x13F) ++ ++#define RXCILA _SFR_MEM8(0x140) ++ ++#define RXCIHA _SFR_MEM8(0x141) ++ ++#define RXCPLA _SFR_MEM8(0x142) ++ ++#define RXCPHA _SFR_MEM8(0x143) ++ ++#define RXDSA _SFR_MEM8(0x144) ++ ++#define CRCCR _SFR_MEM8(0x145) ++#define CRCRS 0 ++#define REFLI 1 ++#define REFLO 2 ++ ++#define CRCDOR _SFR_MEM8(0x146) ++ ++#define IDB0 _SFR_MEM8(0x147) ++ ++#define IDB1 _SFR_MEM8(0x148) ++ ++#define IDB2 _SFR_MEM8(0x149) ++ ++#define IDB3 _SFR_MEM8(0x14A) ++ ++#define IDC _SFR_MEM8(0x14B) ++#define IDL0 0 ++#define IDL1 1 ++#define IDBO0 2 ++#define IDBO1 3 ++#define IDFIM 5 ++#define IDCLR 6 ++#define IDCE 7 ++ ++#define IDS _SFR_MEM8(0x14C) ++#define IDOK 0 ++#define IDFULL 1 ++ ++#define RSSAV _SFR_MEM8(0x14D) ++ ++#define RSSPK _SFR_MEM8(0x14E) ++ ++#define RSSL _SFR_MEM8(0x14F) ++ ++#define RSSH _SFR_MEM8(0x150) ++ ++#define RSSC _SFR_MEM8(0x151) ++#define RSUP0 0 ++#define RSUP1 1 ++#define RSUP2 2 ++#define RSUP3 3 ++#define RSWLH 4 ++#define RSHRX 5 ++#define RSPKF 6 ++ ++#define DBCR _SFR_MEM8(0x152) ++#define DBMD 0 ++#define DBCS 1 ++#define DBTMS 2 ++#define DBHA 3 ++ ++#define DBTC _SFR_MEM8(0x153) ++ ++#define DBENB _SFR_MEM8(0x154) ++ ++#define DBENC _SFR_MEM8(0x155) ++ ++#define DBGSW _SFR_MEM8(0x156) ++#define DBGGS0 0 ++#define DBGGS1 1 ++#define DBGGS2 2 ++#define DBGGS3 3 ++#define CPBFOS0 4 ++#define CPBFOS1 5 ++#define CPBF 6 ++#define DBGSE 7 ++ ++#define SFFR _SFR_MEM8(0x157) ++#define RFL0 0 ++#define RFL1 1 ++#define RFL2 2 ++#define RFC 3 ++#define TFL0 4 ++#define TFL1 5 ++#define TFL2 6 ++#define TFC 7 ++ ++#define SFIR _SFR_MEM8(0x158) ++#define RIL0 0 ++#define RIL1 1 ++#define RIL2 2 ++#define SRIE 3 ++#define TIL0 4 ++#define TIL1 5 ++#define TIL2 6 ++#define STIE 7 ++ ++#define EECR2 _SFR_MEM8(0x159) ++#define EEBRE 0 ++ ++#define PGMST _SFR_MEM8(0x15A) ++#define PGMSYN0 0 ++#define PGMSYN1 1 ++#define PGMSYN2 2 ++#define PGMSYN3 3 ++#define PGMSYN4 4 ++ ++#define EEST _SFR_MEM8(0x15B) ++#define EESYN0 0 ++#define EESYN1 1 ++#define EESYN2 2 ++#define EESYN3 3 ++ ++#define RSIFG _SFR_MEM8(0x15C) ++ ++#define RSLDV _SFR_MEM8(0x15D) ++ ++#define RSHDV _SFR_MEM8(0x15E) ++ ++#define RSCOM _SFR_MEM8(0x15F) ++#define RSDC 0 ++#define RSIFC 1 ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCI0_vect _VECTOR(3) ++#define PCI0_vect_num 3 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCI1_vect _VECTOR(4) ++#define PCI1_vect_num 4 ++ ++/* Voltage Monitoring Interrupt */ ++#define VMON_vect _VECTOR(5) ++#define VMON_vect_num 5 ++ ++/* AVCC Reset Interrupt */ ++#define AVCCR_vect _VECTOR(6) ++#define AVCCR_vect_num 6 ++ ++/* AVCC Low Interrupt */ ++#define AVCCL_vect _VECTOR(7) ++#define AVCCL_vect_num 7 ++ ++/* Timer 0 Interval Interrupt */ ++#define T0INT_vect _VECTOR(8) ++#define T0INT_vect_num 8 ++ ++/* Timer/Counter1 Compare Match Interrupt */ ++#define T1COMP_vect _VECTOR(9) ++#define T1COMP_vect_num 9 ++ ++/* Timer/Counter1 Overflow Interrupt */ ++#define T1OVF_vect _VECTOR(10) ++#define T1OVF_vect_num 10 ++ ++/* Timer/Counter2 Compare Match Interrupt */ ++#define T2COMP_vect _VECTOR(11) ++#define T2COMP_vect_num 11 ++ ++/* Timer/Counter2 Overflow Interrupt */ ++#define T2OVF_vect _VECTOR(12) ++#define T2OVF_vect_num 12 ++ ++/* Timer/Counter3 Capture Event Interrupt */ ++#define T3CAP_vect _VECTOR(13) ++#define T3CAP_vect_num 13 ++ ++/* Timer/Counter3 Compare Match Interrupt */ ++#define T3COMP_vect _VECTOR(14) ++#define T3COMP_vect_num 14 ++ ++/* Timer/Counter3 Overflow Interrupt */ ++#define T3OVF_vect _VECTOR(15) ++#define T3OVF_vect_num 15 ++ ++/* Timer/Counter4 Capture Event Interrupt */ ++#define T4CAP_vect _VECTOR(16) ++#define T4CAP_vect_num 16 ++ ++/* Timer/Counter4 Compare Match Interrupt */ ++#define T4COMP_vect _VECTOR(17) ++#define T4COMP_vect_num 17 ++ ++/* Timer/Counter4 Overflow Interrupt */ ++#define T4OVF_vect _VECTOR(18) ++#define T4OVF_vect_num 18 ++ ++/* Timer/Counter5 Compare Match Interrupt */ ++#define T5COMP_vect _VECTOR(19) ++#define T5COMP_vect_num 19 ++ ++/* Timer/Counter5 Overflow Interrupt */ ++#define T5OVF_vect _VECTOR(20) ++#define T5OVF_vect_num 20 ++ ++/* SPI Serial Transfer Complete Interrupt */ ++#define SPI_vect _VECTOR(21) ++#define SPI_vect_num 21 ++ ++/* SPI Rx Buffer Interrupt */ ++#define SRX_FIFO_vect _VECTOR(22) ++#define SRX_FIFO_vect_num 22 ++ ++/* SPI Tx Buffer Interrupt */ ++#define STX_FIFO_vect _VECTOR(23) ++#define STX_FIFO_vect_num 23 ++ ++/* Sequencer State Machine Interrupt */ ++#define SSM_vect _VECTOR(24) ++#define SSM_vect_num 24 ++ ++/* Data FIFO fill level reached Interrupt */ ++#define DFFLR_vect _VECTOR(25) ++#define DFFLR_vect_num 25 ++ ++/* Data FIFO overflow or underflow error Interrupt */ ++#define DFOUE_vect _VECTOR(26) ++#define DFOUE_vect_num 26 ++ ++/* RSSI/Preamble FIFO fill level reached Interrupt */ ++#define SFFLR_vect _VECTOR(27) ++#define SFFLR_vect_num 27 ++ ++/* RSSI/Preamble FIFO overflow or underflow error Interrupt */ ++#define SFOUE_vect _VECTOR(28) ++#define SFOUE_vect_num 28 ++ ++/* Tx Modulator Telegram Finish Interrupt */ ++#define TMTCF_vect _VECTOR(29) ++#define TMTCF_vect_num 29 ++ ++/* UHF receiver wake up ok on Rx path B */ ++#define UHF_WCOB_vect _VECTOR(30) ++#define UHF_WCOB_vect_num 30 ++ ++/* UHF receiver wake up ok on Rx path A */ ++#define UHF_WCOA_vect _VECTOR(31) ++#define UHF_WCOA_vect_num 31 ++ ++/* UHF receiver start of telegram ok on Rx path B */ ++#define UHF_SOTB_vect _VECTOR(32) ++#define UHF_SOTB_vect_num 32 ++ ++/* UHF receiver start of telegram ok on Rx path A */ ++#define UHF_SOTA_vect _VECTOR(33) ++#define UHF_SOTA_vect_num 33 ++ ++/* UHF receiver end of telegram on Rx path B */ ++#define UHF_EOTB_vect _VECTOR(34) ++#define UHF_EOTB_vect_num 34 ++ ++/* UHF receiver end of telegram on Rx path A */ ++#define UHF_EOTA_vect _VECTOR(35) ++#define UHF_EOTA_vect_num 35 ++ ++/* UHF receiver new bit on Rx path B */ ++#define UHF_NBITB_vect _VECTOR(36) ++#define UHF_NBITB_vect_num 36 ++ ++/* UHF receiver new bit on Rx path A */ ++#define UHF_NBITA_vect _VECTOR(37) ++#define UHF_NBITA_vect_num 37 ++ ++/* External input Clock monitoring Interrupt */ ++#define EXCM_vect _VECTOR(38) ++#define EXCM_vect_num 38 ++ ++/* EEPROM Ready Interrupt */ ++#define ERDY_vect _VECTOR(39) ++#define ERDY_vect_num 39 ++ ++/* Store Program Memory Ready */ ++#define SPMR_vect _VECTOR(40) ++#define SPMR_vect_num 40 ++ ++/* IDSCAN Full Interrupt */ ++#define IDFULL_vect _VECTOR(41) ++#define IDFULL_vect_num 41 ++ ++#define _VECTORS_SIZE 168 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 64 ++#define FLASHSTART 0x8000 ++#define FLASHEND 0xCFFF ++#define RAMSTART 0x0200 ++#define RAMSIZE 1024 ++#define RAMEND 0x05FF ++#define E2START 0 ++#define E2SIZE 1152 ++#define E2PAGESIZE 16 ++#define E2END 0x047F ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Fuse Byte */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(128) ++#define FUSE_DWEN (unsigned char)~_BV(64) ++#define FUSE_SPIEN (unsigned char)~_BV(32) ++#define FUSE_WDTON (unsigned char)~_BV(16) ++#define FUSE_EESAVE (unsigned char)~_BV(8) ++#define FUSE_BOOTRST (unsigned char)~_BV(4) ++#define FUSE_RSTDISBL (unsigned char)~_BV(2) ++#define FUSE_EXTCLKEN (unsigned char)~_BV(1) ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x63 ++ ++ ++#endif /* #ifdef _AVR_ATA5833_H_INCLUDED */ ++ +diff --git a/include/avr/ioa6285.h b/include/avr/ioa6285.h +new file mode 100644 +index 0000000..85432da +--- /dev/null ++++ b/include/avr/ioa6285.h +@@ -0,0 +1,691 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATA6285_H_INCLUDED ++#define _AVR_ATA6285_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "ioa6285.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++/* Reserved [0x0C..0x0E] */ ++ ++#define CMCR _SFR_IO8(0x0F) ++#define CMM0 0 ++#define CMM1 1 ++#define SRCD 2 ++#define CMONEN 3 ++#define CCS 4 ++#define ECINS 5 ++#define CMCCE 7 ++ ++#define CMSR _SFR_IO8(0x10) ++#define ECF 0 ++ ++#define T2CRA _SFR_IO8(0x11) ++#define T2OTM 0 ++#define T2CTM 1 ++#define T2CR 2 ++#define T2CRM 3 ++#define T2ICS 5 ++#define T2TS 6 ++#define T2E 7 ++ ++#define T2CRB _SFR_IO8(0x12) ++#define T2SCE 0 ++ ++/* Reserved [0x13] */ ++ ++#define T3CRA _SFR_IO8(0x14) ++#define T3AC 0 ++#define T3SCE 1 ++#define T3CR 2 ++#define T3TS 6 ++#define T3E 7 ++ ++/* Reserved [0x15] */ ++ ++#define VMCSR _SFR_IO8(0x16) ++#define VMEN 0 ++#define VMLS0 1 ++#define VMLS1 2 ++#define VMLS2 3 ++#define VMIM 4 ++#define VMF 5 ++#define BODPD 6 ++#define BODLS 7 ++ ++#define PCIFR _SFR_IO8(0x17) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++ ++#define LFFR _SFR_IO8(0x18) ++#define LFWPF 0 ++#define LFBF 1 ++#define LFEDF 2 ++#define LFRF 3 ++ ++#define SSFR _SFR_IO8(0x19) ++#define MSENF 0 ++#define MSENO 1 ++ ++#define T10IFR _SFR_IO8(0x1A) ++#define T0F 0 ++#define T1F 1 ++ ++#define T2IFR _SFR_IO8(0x1B) ++#define T2OFF 0 ++#define T2COF 1 ++#define T2ICF 2 ++#define T2RXF 3 ++#define T2TXF 4 ++#define T2TCF 5 ++ ++#define T3IFR _SFR_IO8(0x1C) ++#define T3OFF 0 ++#define T3COAF 1 ++#define T3COBF 2 ++#define T3ICF 3 ++ ++#define EIFR _SFR_IO8(0x1D) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define PCICR _SFR_IO8(0x23) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++ ++#define EIMSK _SFR_IO8(0x24) ++#define INT0 0 ++#define INT1 1 ++ ++/* Reserved [0x25..0x26] */ ++ ++#define SVCR _SFR_IO8(0x27) ++ ++#define SCR _SFR_IO8(0x28) ++#define SMS 0 ++#define SEN0 1 ++#define SEN1 2 ++#define SMEN 3 ++ ++#define SCCR _SFR_IO8(0x29) ++#define SRCC0 0 ++#define SRCC1 1 ++#define SCCS0 2 ++#define SCCS1 3 ++#define SCCS2 4 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++#define T2MDR _SFR_IO8(0x2F) ++ ++#define LFRR _SFR_IO8(0x30) ++ ++/* Reserved [0x31] */ ++ ++#define LFCDR _SFR_IO8(0x32) ++#define LFDO 0 ++#define LFRST 6 ++#define LFSCE 7 ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define TSRF 5 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++ ++#define LFRB _SFR_IO8(0x36) ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SELFPRGEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define T1CR _SFR_IO8(0x38) ++#define T1PS0 0 ++#define T1PS1 1 ++#define T1PS2 2 ++#define T1CS0 3 ++#define T1CS1 4 ++#define T1CS2 5 ++#define T1IE 7 ++ ++#define T0CR _SFR_IO8(0x39) ++#define T0PAS0 0 ++#define T0PAS1 1 ++#define T0PAS2 2 ++#define T0IE 3 ++#define T0PR 4 ++#define T0PBS0 5 ++#define T0PBS1 6 ++#define T0PBS2 7 ++ ++/* Reserved [0x3A] */ ++ ++#define CMIMR _SFR_IO8(0x3B) ++#define ECIE 0 ++ ++#define CLKPR _SFR_IO8(0x3C) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLTPS0 3 ++#define CLTPS1 4 ++#define CLTPS2 5 ++#define CLPCE 7 ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDPS0 0 ++#define WDPS1 1 ++#define WDPS2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define SIMSK _SFR_MEM8(0x61) ++#define MSIE 0 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define TSCR _SFR_MEM8(0x64) ++#define TSSD 0 ++ ++#define SRCCAL _SFR_MEM8(0x65) ++ ++#define FRCCAL _SFR_MEM8(0x66) ++ ++#define MSVCAL _SFR_MEM8(0x67) ++ ++/* Reserved [0x68] */ ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++#define PCMSK0 _SFR_MEM8(0x6A) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6B) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++ ++#define PCMSK2 _SFR_MEM8(0x6C) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++/* Reserved [0x6D] */ ++ ++#define T2ICRL _SFR_MEM8(0x6E) ++ ++#define T2ICR _SFR_MEM8(0x6F) ++ ++/* Combine T2CORL and T2CORH */ ++#define T2COR _SFR_MEM16(0x70) ++ ++#define T2CORL _SFR_MEM8(0x70) ++#define T2CORH _SFR_MEM8(0x71) ++ ++#define T2MRA _SFR_MEM8(0x72) ++#define T2CS0 0 ++#define T2CS1 1 ++#define T2CS2 2 ++#define T2CE0 3 ++#define T2CE1 4 ++#define T2CNC 5 ++#define T2TP0 6 ++#define T2TP1 7 ++ ++#define T2MRB _SFR_MEM8(0x73) ++#define T2M0 0 ++#define T2M1 1 ++#define T2M2 2 ++#define T2M3 3 ++#define T2TOP 4 ++#define T2CPOL 6 ++#define T2SSIE 7 ++ ++#define T2IMR _SFR_MEM8(0x74) ++#define T2OIM 0 ++#define T2CIM 1 ++#define T2CPIM 2 ++#define T2RXIM 3 ++#define T2TXIM 4 ++#define T2TCIM 5 ++ ++/* Reserved [0x75] */ ++ ++/* Combine T3ICRL and T3ICRH */ ++#define T3ICR _SFR_MEM16(0x76) ++ ++#define T3ICRL _SFR_MEM8(0x76) ++#define T3ICRH _SFR_MEM8(0x77) ++ ++/* Combine T3CORAL and T3CORAH */ ++#define T3CORA _SFR_MEM16(0x78) ++ ++#define T3CORAL _SFR_MEM8(0x78) ++#define T3CORAH _SFR_MEM8(0x79) ++ ++/* Combine T3CORBL and T3CORBH */ ++#define T3CORB _SFR_MEM16(0x7A) ++ ++#define T3CORBL _SFR_MEM8(0x7A) ++#define T3CORBH _SFR_MEM8(0x7B) ++ ++#define T3MRA _SFR_MEM8(0x7C) ++#define T3CS0 0 ++#define T3CS1 1 ++#define T3CS2 2 ++#define T3CE0 3 ++#define T3CE1 4 ++#define T3CNC 5 ++#define T3ICS0 6 ++#define T3ICS1 7 ++ ++#define T3MRB _SFR_MEM8(0x7D) ++#define T3M0 0 ++#define T3M1 1 ++#define T3M2 2 ++#define T3TOP 4 ++ ++#define T3CRB _SFR_MEM8(0x7E) ++#define T3CTMA 0 ++#define T3SAMA 1 ++#define T3CRMA 2 ++#define T3CTMB 3 ++#define T3SAMB 4 ++#define T3CRMB 5 ++#define T3CPRM 6 ++ ++#define T3IMR _SFR_MEM8(0x7F) ++#define T3OIM 0 ++#define T3CAIM 1 ++#define T3CBIM 2 ++#define T3CPIM 3 ++ ++/* Reserved [0x80] */ ++ ++#define LFIMR _SFR_MEM8(0x81) ++#define LFWIM 0 ++#define LFBIM 1 ++#define LFEIM 2 ++ ++#define LFRCR _SFR_MEM8(0x82) ++#define LFEN 0 ++#define LFBM 1 ++#define LFWM0 2 ++#define LFWM1 3 ++#define LFRSS 4 ++#define LFCS0 5 ++#define LFCS1 6 ++#define LFCS2 7 ++ ++#define LFHCR _SFR_MEM8(0x83) ++ ++/* Combine LFIDCL and LFIDCH */ ++#define LFIDC _SFR_MEM16(0x84) ++ ++#define LFIDCL _SFR_MEM8(0x84) ++#define LFIDCH _SFR_MEM8(0x85) ++ ++/* Combine LFCALL and LFCALH */ ++#define LFCAL _SFR_MEM16(0x86) ++ ++#define LFCALL _SFR_MEM8(0x86) ++#define LFCALH _SFR_MEM8(0x87) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(3) ++#define PCINT0_vect_num 3 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(4) ++#define PCINT1_vect_num 4 ++ ++/* Pin Change Interrupt Request 2 */ ++#define PCINT2_vect _VECTOR(5) ++#define PCINT2_vect_num 5 ++ ++/* Voltage Monitor Interrupt */ ++#define INTVM_vect _VECTOR(6) ++#define INTVM_vect_num 6 ++ ++/* Sensor Interface Interrupt */ ++#define SENINT_vect _VECTOR(7) ++#define SENINT_vect_num 7 ++ ++/* Timer0 Interval Interrupt */ ++#define INTT0_vect _VECTOR(8) ++#define INTT0_vect_num 8 ++ ++/* LF-Receiver Wake-up Interrupt */ ++#define LFWP_vect _VECTOR(9) ++#define LFWP_vect_num 9 ++ ++/* Timer/Counter3 Capture Event */ ++#define T3CAP_vect _VECTOR(10) ++#define T3CAP_vect_num 10 ++ ++/* Timer/Counter3 Compare Match A */ ++#define T3COMA_vect _VECTOR(11) ++#define T3COMA_vect_num 11 ++ ++/* Timer/Counter3 Compare Match B */ ++#define T3COMB_vect _VECTOR(12) ++#define T3COMB_vect_num 12 ++ ++/* Timer/Counter3 Overflow */ ++#define T3OVF_vect _VECTOR(13) ++#define T3OVF_vect_num 13 ++ ++/* Timer/Counter2 Capture Event */ ++#define T2CAP_vect _VECTOR(14) ++#define T2CAP_vect_num 14 ++ ++/* Timer/Counter2 Compare Match */ ++#define T2COM_vect _VECTOR(15) ++#define T2COM_vect_num 15 ++ ++/* Timer/Counter2 Overflow */ ++#define T2OVF_vect _VECTOR(16) ++#define T2OVF_vect_num 16 ++ ++/* SPI Serial Transfer Complete */ ++#define SPISTC_vect _VECTOR(17) ++#define SPISTC_vect_num 17 ++ ++/* LF Receive Buffer Interrupt */ ++#define LFRXB_vect _VECTOR(18) ++#define LFRXB_vect_num 18 ++ ++/* Timer1 Interval Interrupt */ ++#define INTT1_vect _VECTOR(19) ++#define INTT1_vect_num 19 ++ ++/* Timer2 SSI Receive Buffer Interrupt */ ++#define T2RXB_vect _VECTOR(20) ++#define T2RXB_vect_num 20 ++ ++/* Timer2 SSI Transmit Buffer Interrupt */ ++#define T2TXB_vect _VECTOR(21) ++#define T2TXB_vect_num 21 ++ ++/* Timer2 SSI Transmit Complete Interrupt */ ++#define T2TXC_vect _VECTOR(22) ++#define T2TXC_vect_num 22 ++ ++/* LF-Receiver End of Burst Interrupt */ ++#define LFREOB_vect _VECTOR(23) ++#define LFREOB_vect_num 23 ++ ++/* External Input Clock break down Interrupt */ ++#define EXCM_vect _VECTOR(24) ++#define EXCM_vect_num 24 ++ ++/* EEPROM Ready Interrupt */ ++#define EEREADY_vect _VECTOR(25) ++#define EEREADY_vect_num 25 ++ ++/* Store Program Memory Ready */ ++#define SPM_RDY_vect _VECTOR(26) ++#define SPM_RDY_vect_num 26 ++ ++#define _VECTORS_SIZE 54 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 64 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x1FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 512 ++#define RAMEND 0x02FF ++#define E2START 0 ++#define E2SIZE 320 ++#define E2PAGESIZE 4 ++#define E2END 0x013F ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 2 ++ ++/* Low Fuse Byte */ ++#define FUSE_TSRDI (unsigned char)~_BV(0) ++#define FUSE_BODEN (unsigned char)~_BV(1) ++#define FUSE_FRCFS (unsigned char)~_BV(2) ++#define FUSE_WDRCON (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_EELOCK (unsigned char)~_BV(7) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x82 ++ ++ ++#endif /* #ifdef _AVR_ATA6285_H_INCLUDED */ ++ +diff --git a/include/avr/ioa6286.h b/include/avr/ioa6286.h +new file mode 100644 +index 0000000..626106f +--- /dev/null ++++ b/include/avr/ioa6286.h +@@ -0,0 +1,691 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATA6286_H_INCLUDED ++#define _AVR_ATA6286_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "ioa6286.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++/* Reserved [0x0C..0x0E] */ ++ ++#define CMCR _SFR_IO8(0x0F) ++#define CMM0 0 ++#define CMM1 1 ++#define SRCD 2 ++#define CMONEN 3 ++#define CCS 4 ++#define ECINS 5 ++#define CMCCE 7 ++ ++#define CMSR _SFR_IO8(0x10) ++#define ECF 0 ++ ++#define T2CRA _SFR_IO8(0x11) ++#define T2OTM 0 ++#define T2CTM 1 ++#define T2CR 2 ++#define T2CRM 3 ++#define T2ICS 5 ++#define T2TS 6 ++#define T2E 7 ++ ++#define T2CRB _SFR_IO8(0x12) ++#define T2SCE 0 ++ ++/* Reserved [0x13] */ ++ ++#define T3CRA _SFR_IO8(0x14) ++#define T3AC 0 ++#define T3SCE 1 ++#define T3CR 2 ++#define T3TS 6 ++#define T3E 7 ++ ++/* Reserved [0x15] */ ++ ++#define VMCSR _SFR_IO8(0x16) ++#define VMEN 0 ++#define VMLS0 1 ++#define VMLS1 2 ++#define VMLS2 3 ++#define VMIM 4 ++#define VMF 5 ++#define BODPD 6 ++#define BODLS 7 ++ ++#define PCIFR _SFR_IO8(0x17) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++ ++#define LFFR _SFR_IO8(0x18) ++#define LFWPF 0 ++#define LFBF 1 ++#define LFEDF 2 ++#define LFRF 3 ++ ++#define SSFR _SFR_IO8(0x19) ++#define MSENF 0 ++#define MSENO 1 ++ ++#define T10IFR _SFR_IO8(0x1A) ++#define T0F 0 ++#define T1F 1 ++ ++#define T2IFR _SFR_IO8(0x1B) ++#define T2OFF 0 ++#define T2COF 1 ++#define T2ICF 2 ++#define T2RXF 3 ++#define T2TXF 4 ++#define T2TCF 5 ++ ++#define T3IFR _SFR_IO8(0x1C) ++#define T3OFF 0 ++#define T3COAF 1 ++#define T3COBF 2 ++#define T3ICF 3 ++ ++#define EIFR _SFR_IO8(0x1D) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define PCICR _SFR_IO8(0x23) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++ ++#define EIMSK _SFR_IO8(0x24) ++#define INT0 0 ++#define INT1 1 ++ ++/* Reserved [0x25..0x26] */ ++ ++#define SVCR _SFR_IO8(0x27) ++ ++#define SCR _SFR_IO8(0x28) ++#define SMS 0 ++#define SEN0 1 ++#define SEN1 2 ++#define SMEN 3 ++ ++#define SCCR _SFR_IO8(0x29) ++#define SRCC0 0 ++#define SRCC1 1 ++#define SCCS0 2 ++#define SCCS1 3 ++#define SCCS2 4 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++#define T2MDR _SFR_IO8(0x2F) ++ ++#define LFRR _SFR_IO8(0x30) ++ ++/* Reserved [0x31] */ ++ ++#define LFCDR _SFR_IO8(0x32) ++#define LFDO 0 ++#define LFRST 6 ++#define LFSCE 7 ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define TSRF 5 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++ ++#define LFRB _SFR_IO8(0x36) ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SELFPRGEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define T1CR _SFR_IO8(0x38) ++#define T1PS0 0 ++#define T1PS1 1 ++#define T1PS2 2 ++#define T1CS0 3 ++#define T1CS1 4 ++#define T1CS2 5 ++#define T1IE 7 ++ ++#define T0CR _SFR_IO8(0x39) ++#define T0PAS0 0 ++#define T0PAS1 1 ++#define T0PAS2 2 ++#define T0IE 3 ++#define T0PR 4 ++#define T0PBS0 5 ++#define T0PBS1 6 ++#define T0PBS2 7 ++ ++/* Reserved [0x3A] */ ++ ++#define CMIMR _SFR_IO8(0x3B) ++#define ECIE 0 ++ ++#define CLKPR _SFR_IO8(0x3C) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLTPS0 3 ++#define CLTPS1 4 ++#define CLTPS2 5 ++#define CLPCE 7 ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDPS0 0 ++#define WDPS1 1 ++#define WDPS2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define SIMSK _SFR_MEM8(0x61) ++#define MSIE 0 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define TSCR _SFR_MEM8(0x64) ++#define TSSD 0 ++ ++#define SRCCAL _SFR_MEM8(0x65) ++ ++#define FRCCAL _SFR_MEM8(0x66) ++ ++#define MSVCAL _SFR_MEM8(0x67) ++ ++/* Reserved [0x68] */ ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++#define PCMSK0 _SFR_MEM8(0x6A) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6B) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++ ++#define PCMSK2 _SFR_MEM8(0x6C) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++/* Reserved [0x6D] */ ++ ++#define T2ICRL _SFR_MEM8(0x6E) ++ ++#define T2ICR _SFR_MEM8(0x6F) ++ ++/* Combine T2CORL and T2CORH */ ++#define T2COR _SFR_MEM16(0x70) ++ ++#define T2CORL _SFR_MEM8(0x70) ++#define T2CORH _SFR_MEM8(0x71) ++ ++#define T2MRA _SFR_MEM8(0x72) ++#define T2CS0 0 ++#define T2CS1 1 ++#define T2CS2 2 ++#define T2CE0 3 ++#define T2CE1 4 ++#define T2CNC 5 ++#define T2TP0 6 ++#define T2TP1 7 ++ ++#define T2MRB _SFR_MEM8(0x73) ++#define T2M0 0 ++#define T2M1 1 ++#define T2M2 2 ++#define T2M3 3 ++#define T2TOP 4 ++#define T2CPOL 6 ++#define T2SSIE 7 ++ ++#define T2IMR _SFR_MEM8(0x74) ++#define T2OIM 0 ++#define T2CIM 1 ++#define T2CPIM 2 ++#define T2RXIM 3 ++#define T2TXIM 4 ++#define T2TCIM 5 ++ ++/* Reserved [0x75] */ ++ ++/* Combine T3ICRL and T3ICRH */ ++#define T3ICR _SFR_MEM16(0x76) ++ ++#define T3ICRL _SFR_MEM8(0x76) ++#define T3ICRH _SFR_MEM8(0x77) ++ ++/* Combine T3CORAL and T3CORAH */ ++#define T3CORA _SFR_MEM16(0x78) ++ ++#define T3CORAL _SFR_MEM8(0x78) ++#define T3CORAH _SFR_MEM8(0x79) ++ ++/* Combine T3CORBL and T3CORBH */ ++#define T3CORB _SFR_MEM16(0x7A) ++ ++#define T3CORBL _SFR_MEM8(0x7A) ++#define T3CORBH _SFR_MEM8(0x7B) ++ ++#define T3MRA _SFR_MEM8(0x7C) ++#define T3CS0 0 ++#define T3CS1 1 ++#define T3CS2 2 ++#define T3CE0 3 ++#define T3CE1 4 ++#define T3CNC 5 ++#define T3ICS0 6 ++#define T3ICS1 7 ++ ++#define T3MRB _SFR_MEM8(0x7D) ++#define T3M0 0 ++#define T3M1 1 ++#define T3M2 2 ++#define T3TOP 4 ++ ++#define T3CRB _SFR_MEM8(0x7E) ++#define T3CTMA 0 ++#define T3SAMA 1 ++#define T3CRMA 2 ++#define T3CTMB 3 ++#define T3SAMB 4 ++#define T3CRMB 5 ++#define T3CPRM 6 ++ ++#define T3IMR _SFR_MEM8(0x7F) ++#define T3OIM 0 ++#define T3CAIM 1 ++#define T3CBIM 2 ++#define T3CPIM 3 ++ ++/* Reserved [0x80] */ ++ ++#define LFIMR _SFR_MEM8(0x81) ++#define LFWIM 0 ++#define LFBIM 1 ++#define LFEIM 2 ++ ++#define LFRCR _SFR_MEM8(0x82) ++#define LFEN 0 ++#define LFBM 1 ++#define LFWM0 2 ++#define LFWM1 3 ++#define LFRSS 4 ++#define LFCS0 5 ++#define LFCS1 6 ++#define LFCS2 7 ++ ++#define LFHCR _SFR_MEM8(0x83) ++ ++/* Combine LFIDCL and LFIDCH */ ++#define LFIDC _SFR_MEM16(0x84) ++ ++#define LFIDCL _SFR_MEM8(0x84) ++#define LFIDCH _SFR_MEM8(0x85) ++ ++/* Combine LFCALL and LFCALH */ ++#define LFCAL _SFR_MEM16(0x86) ++ ++#define LFCALL _SFR_MEM8(0x86) ++#define LFCALH _SFR_MEM8(0x87) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(3) ++#define PCINT0_vect_num 3 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(4) ++#define PCINT1_vect_num 4 ++ ++/* Pin Change Interrupt Request 2 */ ++#define PCINT2_vect _VECTOR(5) ++#define PCINT2_vect_num 5 ++ ++/* Voltage Monitor Interrupt */ ++#define INTVM_vect _VECTOR(6) ++#define INTVM_vect_num 6 ++ ++/* Sensor Interface Interrupt */ ++#define SENINT_vect _VECTOR(7) ++#define SENINT_vect_num 7 ++ ++/* Timer0 Interval Interrupt */ ++#define INTT0_vect _VECTOR(8) ++#define INTT0_vect_num 8 ++ ++/* LF-Receiver Wake-up Interrupt */ ++#define LFWP_vect _VECTOR(9) ++#define LFWP_vect_num 9 ++ ++/* Timer/Counter3 Capture Event */ ++#define T3CAP_vect _VECTOR(10) ++#define T3CAP_vect_num 10 ++ ++/* Timer/Counter3 Compare Match A */ ++#define T3COMA_vect _VECTOR(11) ++#define T3COMA_vect_num 11 ++ ++/* Timer/Counter3 Compare Match B */ ++#define T3COMB_vect _VECTOR(12) ++#define T3COMB_vect_num 12 ++ ++/* Timer/Counter3 Overflow */ ++#define T3OVF_vect _VECTOR(13) ++#define T3OVF_vect_num 13 ++ ++/* Timer/Counter2 Capture Event */ ++#define T2CAP_vect _VECTOR(14) ++#define T2CAP_vect_num 14 ++ ++/* Timer/Counter2 Compare Match */ ++#define T2COM_vect _VECTOR(15) ++#define T2COM_vect_num 15 ++ ++/* Timer/Counter2 Overflow */ ++#define T2OVF_vect _VECTOR(16) ++#define T2OVF_vect_num 16 ++ ++/* SPI Serial Transfer Complete */ ++#define SPISTC_vect _VECTOR(17) ++#define SPISTC_vect_num 17 ++ ++/* LF Receive Buffer Interrupt */ ++#define LFRXB_vect _VECTOR(18) ++#define LFRXB_vect_num 18 ++ ++/* Timer1 Interval Interrupt */ ++#define INTT1_vect _VECTOR(19) ++#define INTT1_vect_num 19 ++ ++/* Timer2 SSI Receive Buffer Interrupt */ ++#define T2RXB_vect _VECTOR(20) ++#define T2RXB_vect_num 20 ++ ++/* Timer2 SSI Transmit Buffer Interrupt */ ++#define T2TXB_vect _VECTOR(21) ++#define T2TXB_vect_num 21 ++ ++/* Timer2 SSI Transmit Complete Interrupt */ ++#define T2TXC_vect _VECTOR(22) ++#define T2TXC_vect_num 22 ++ ++/* LF-Receiver End of Burst Interrupt */ ++#define LFREOB_vect _VECTOR(23) ++#define LFREOB_vect_num 23 ++ ++/* External Input Clock break down Interrupt */ ++#define EXCM_vect _VECTOR(24) ++#define EXCM_vect_num 24 ++ ++/* EEPROM Ready Interrupt */ ++#define EEREADY_vect _VECTOR(25) ++#define EEREADY_vect_num 25 ++ ++/* Store Program Memory Ready */ ++#define SPM_RDY_vect _VECTOR(26) ++#define SPM_RDY_vect_num 26 ++ ++#define _VECTORS_SIZE 54 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 64 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x1FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 512 ++#define RAMEND 0x02FF ++#define E2START 0 ++#define E2SIZE 320 ++#define E2PAGESIZE 4 ++#define E2END 0x013F ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 2 ++ ++/* Low Fuse Byte */ ++#define FUSE_TSRDI (unsigned char)~_BV(0) ++#define FUSE_BODEN (unsigned char)~_BV(1) ++#define FUSE_FRCFS (unsigned char)~_BV(2) ++#define FUSE_WDRCON (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_EELOCK (unsigned char)~_BV(7) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x82 ++ ++ ++#endif /* #ifdef _AVR_ATA6286_H_INCLUDED */ ++ +diff --git a/include/avr/ioa6289.h b/include/avr/ioa6289.h +index a38c649..1a322fc 100644 +--- a/include/avr/ioa6289.h ++++ b/include/avr/ioa6289.h +@@ -1,844 +1,844 @@ +-/* Copyright (c) 2008 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: ioa6289.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ +- +-/* avr/ioa6289.h - definitions for ATA6289 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "ioa6289.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATA6289_H_ +-#define _AVR_ATA6289_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +- +-#define DDRC _SFR_IO8(0x07) +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define CMCR _SFR_IO8(0x0F) +-#define CMM0 0 +-#define CMM1 1 +-#define SRCD 2 +-#define CMONEN 3 +-#define CCS 4 +-#define ECINS 5 +-#define CMCCE 7 +- +-#define CMSR _SFR_IO8(0x10) +-#define ECF 0 +- +-#define T2CRA _SFR_IO8(0x11) +-#define T2OTM 0 +-#define T2CTM 1 +-#define T2CR 2 +-#define T2CRM 3 +-#define T2CPRM 4 +-#define T2ICS 5 +-#define T2TS 6 +-#define T2E 7 +- +-#define T2CRB _SFR_IO8(0x12) +-#define T2SCE 0 +- +-#define T3CRA _SFR_IO8(0x14) +-#define T3AC 0 +-#define T3SCE 1 +-#define T3CR 2 +-#define T3TS 6 +-#define T3E 7 +- +-#define VMCSR _SFR_IO8(0x16) +-#define VMEN 0 +-#define VMLS0 1 +-#define VMLS1 2 +-#define VMLS2 3 +-#define VMIM 4 +-#define VMF 5 +-#define BODPD 6 +-#define BODLS 7 +- +-#define PCIFR _SFR_IO8(0x17) +-#define PCIF0 0 +-#define PCIF1 1 +-#define PCIF2 2 +- +-#define LFFR _SFR_IO8(0x18) +-#define LFWPF 0 +-#define LFBF 1 +-#define LFEDF 2 +-#define LFRF 3 +- +-#define SSFR _SFR_IO8(0x19) +-#define MSENF 0 +-#define MSENO 1 +- +-#define T10IFR _SFR_IO8(0x1A) +-#define T0F 0 +-#define T1F 1 +- +-#define T2IFR _SFR_IO8(0x1B) +-#define T2OFF 0 +-#define T2COF 1 +-#define T2ICF 2 +-#define T2RXF 3 +-#define T2TXF 4 +-#define T2TCF 5 +- +-#define T3IFR _SFR_IO8(0x1C) +-#define T3OFF 0 +-#define T3COAF 1 +-#define T3COBF 2 +-#define T3ICF 3 +- +-#define EIFR _SFR_IO8(0x1D) +-#define INTF0 0 +-#define INTF1 1 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEWE 1 +-#define EEMWE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +- +-#define PCICR _SFR_IO8(0x23) +-#define PCIE0 0 +-#define PCIE1 1 +-#define PCIE2 2 +- +-#define EIMSK _SFR_IO8(0x24) +-#define INT0 0 +-#define INT1 1 +- +-#define SVCR _SFR_IO8(0x27) +-#define SVCS0 0 +-#define SVCS1 1 +-#define SVCS2 2 +-#define SVCS3 3 +-#define SVCS4 4 +- +-#define SCR _SFR_IO8(0x28) +-#define SMS 0 +-#define SEN0 1 +-#define SEN1 2 +-#define SMEN 3 +- +-#define SCCR _SFR_IO8(0x29) +-#define SRCC0 0 +-#define SRCC1 1 +-#define SCCS0 2 +-#define SCCS1 3 +-#define SCCS2 4 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define T2MDR _SFR_IO8(0x2F) +-#define T2MDR0 0 +-#define T2MDR1 1 +-#define T2MDR2 2 +-#define T2MDR3 3 +-#define T2MDR4 4 +-#define T2MDR5 5 +-#define T2MDR6 6 +-#define T2MDR7 7 +- +-#define LFRR _SFR_IO8(0x30) +-#define LFRR0 0 +-#define LFRR1 1 +-#define LFRR2 2 +-#define LFRR3 3 +-#define LFRR4 4 +-#define LFRR5 5 +-#define LFRR6 6 +- +-#define LFCDR _SFR_IO8(0x32) +-#define LFDO 0 +-#define LFRST 6 +-#define LFSCE 7 +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +-#define TSRF 5 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +- +-#define LFRB _SFR_IO8(0x36) +-#define LFRB0 0 +-#define LFRB1 1 +-#define LFRB2 2 +-#define LFRB3 3 +-#define LFRB4 4 +-#define LFRB5 5 +-#define LFRB6 6 +-#define LFRB7 7 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SELFPRGEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define T1CR _SFR_IO8(0x38) +-#define T1PS0 0 +-#define T1PS1 1 +-#define T1PS2 2 +-#define T1CS0 3 +-#define T1CS1 4 +-#define T1CS2 5 +-#define T1IE 7 +- +-#define T0CR _SFR_IO8(0x39) +-#define T0PAS0 0 +-#define T0PAS1 1 +-#define T0PAS2 2 +-#define T0IE 3 +-#define T0PR 4 +-#define T0PBS0 5 +-#define T0PBS1 6 +-#define T0PBS2 7 +- +-#define CMIMR _SFR_IO8(0x3B) +-#define ECIE 0 +- +-#define CLKPR _SFR_IO8(0x3C) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLTPS0 3 +-#define CLTPS1 4 +-#define CLTPS2 5 +-#define CLPCE 7 +- +-#define WDTCR _SFR_MEM8(0x60) +-#define WDPS0 0 +-#define WDPS1 1 +-#define WDPS2 2 +-#define WDE 3 +-#define WDCE 4 +- +-#define SIMSK _SFR_MEM8(0x61) +-#define MSIE 0 +- +-#define TSCR _SFR_MEM8(0x64) +-#define TSSD 0 +- +-#define SRCCAL _SFR_MEM8(0x65) +-#define SCAL0 0 +-#define SCAL1 1 +-#define SCAL2 2 +-#define SCAL3 3 +-#define SCAL4 4 +-#define SCAL5 5 +-#define SCAL6 6 +-#define SCAL7 7 +- +-#define FRCCAL _SFR_MEM8(0x66) +-#define FCAL0 0 +-#define FCAL1 1 +-#define FCAL2 2 +-#define FCAL3 3 +-#define FCAL4 4 +-#define FCAL5 5 +-#define FCAL6 6 +-#define FCAL7 7 +- +-#define MSVCAL _SFR_MEM8(0x67) +-#define VRCAL0 0 +-#define VRCAL1 1 +-#define VRCAL2 2 +-#define VRCAL3 3 +-#define VRCAL4 4 +-#define VRCAL5 5 +-#define VRCAL6 6 +-#define VRCAL7 7 +- +-#define BGCAL _SFR_MEM8(0x68) +-#define BGCAL0 0 +-#define BGCAL1 1 +-#define BGCAL2 2 +-#define BGCAL3 3 +-#define BGCAL4 4 +-#define BGCAL5 5 +-#define BGCAL6 6 +-#define BGCAL7 7 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +- +-#define PCMSK0 _SFR_MEM8(0x6A) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6B) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +- +-#define PCMSK2 _SFR_MEM8(0x6C) +-#define PCINT16 0 +-#define PCINT17 1 +-#define PCINT18 2 +-#define PCINT19 3 +-#define PCINT20 4 +-#define PCINT21 5 +-#define PCINT22 6 +-#define PCINT23 7 +- +-#define T2ICR _SFR_MEM16(0x6E) +- +-#define T2ICRL _SFR_MEM8(0x6E) +-#define T2ICRL0 0 +-#define T2ICRL1 1 +-#define T2ICRL2 2 +-#define T2ICRL3 3 +-#define T2ICRL4 4 +-#define T2ICRL5 5 +-#define T2ICRL6 6 +-#define T2ICRL7 7 +- +-#define T2ICRH _SFR_MEM8(0x6F) +-#define T2ICRH0 0 +-#define T2ICRH1 1 +-#define T2ICRH2 2 +-#define T2ICRH3 3 +-#define T2ICRH4 4 +-#define T2ICRH5 5 +-#define T2ICRH6 6 +-#define T2ICRH7 7 +- +-#define T2COR _SFR_MEM16(0x70) +- +-#define T2CORL _SFR_MEM8(0x70) +-#define T2CORL0 0 +-#define T2CORL1 1 +-#define T2CORL2 2 +-#define T2CORL3 3 +-#define T2CORL4 4 +-#define T2CORL5 5 +-#define T2CORL6 6 +-#define T2CORL7 7 +- +-#define T2CORH _SFR_MEM8(0x71) +-#define T2CORH0 0 +-#define T2CORH1 1 +-#define T2CORH2 2 +-#define T2CORH3 3 +-#define T2CORH4 4 +-#define T2CORH5 5 +-#define T2CORH6 6 +-#define T2CORH7 7 +- +-#define T2MRA _SFR_MEM8(0x72) +-#define T2CS0 0 +-#define T2CS1 1 +-#define T2CS2 2 +-#define T2CE0 3 +-#define T2CE1 4 +-#define T2CNC 5 +-#define T2TP0 6 +-#define T2TP1 7 +- +-#define T2MRB _SFR_MEM8(0x73) +-#define T2M0 0 +-#define T2M1 1 +-#define T2M2 2 +-#define T2M3 3 +-#define T2TOP 4 +-#define T2CPOL 6 +-#define T2SSIE 7 +- +-#define T2IMR _SFR_MEM8(0x74) +-#define T2OIM 0 +-#define T2CIM 1 +-#define T2CPIM 2 +-#define T2RXIM 3 +-#define T2TXIM 4 +-#define T2TCIM 5 +- +-#define T3ICR _SFR_MEM16(0x76) +- +-#define T3ICRL _SFR_MEM8(0x76) +-#define T3ICRL0 0 +-#define T3ICRL1 1 +-#define T3ICRL2 2 +-#define T3ICRL3 3 +-#define T3ICRL4 4 +-#define T3ICRL5 5 +-#define T3ICRL6 6 +-#define T3ICRL7 7 +- +-#define T3ICRH _SFR_MEM8(0x77) +-#define T3ICRH0 0 +-#define T3ICRH1 1 +-#define T3ICRH2 2 +-#define T3ICRH3 3 +-#define T3ICRH4 4 +-#define T3ICRH5 5 +-#define T3ICRH6 6 +-#define T3ICRH7 7 +- +-#define T3CORA _SFR_MEM16(0x78) +- +-#define T3CORAL _SFR_MEM8(0x78) +-#define T3CORAL0 0 +-#define T3CORAL1 1 +-#define T3CORAL2 2 +-#define T3CORAL3 3 +-#define T3CORAL4 4 +-#define T3CORAL5 5 +-#define T3CORAL6 6 +-#define T3CORAL7 7 +- +-#define T3CORAH _SFR_MEM8(0x79) +-#define T3CORAH0 0 +-#define T3CORAH1 1 +-#define T3CORAH2 2 +-#define T3CORAH3 3 +-#define T3CORAH4 4 +-#define T3CORAH5 5 +-#define T3CORAH6 6 +-#define T3CORAH7 7 +- +-#define T3CORB _SFR_MEM16(0x7A) +- +-#define T3CORBL _SFR_MEM8(0x7A) +-#define T3CORBL0 0 +-#define T3CORBL1 1 +-#define T3CORBL2 2 +-#define T3CORBL3 3 +-#define T3CORBL4 4 +-#define T3CORBL5 5 +-#define T3CORBL6 6 +-#define T3CORBL7 7 +- +-#define T3CORBH _SFR_MEM8(0x7B) +-#define T3CORBH0 0 +-#define T3CORBH1 1 +-#define T3CORBH2 2 +-#define T3CORBH3 3 +-#define T3CORBH4 4 +-#define T3CORBH5 5 +-#define T3CORBH6 6 +-#define T3CORBH7 7 +- +-#define T3MRA _SFR_MEM8(0x7C) +-#define T3CS0 0 +-#define T3CS1 1 +-#define T3CS2 2 +-#define T3CE0 3 +-#define T3CE1 4 +-#define T3CNC 5 +-#define T3ICS0 6 +-#define T3ICS1 7 +- +-#define T3MRB _SFR_MEM8(0x7D) +-#define T3M0 0 +-#define T3M1 1 +-#define T3M2 2 +-#define T3TOP 4 +- +-#define T3CRB _SFR_MEM8(0x7E) +-#define T3CTMA 0 +-#define T3SAMA 1 +-#define T3CRMA 2 +-#define T3CTMB 3 +-#define T3SAMB 4 +-#define T3CRMB 5 +-#define T3CPRM 6 +- +-#define T3IMR _SFR_MEM8(0x7F) +-#define T3OIM 0 +-#define T3CAIM 1 +-#define T3CBIM 2 +-#define T3CPIM 3 +- +-#define LFIMR _SFR_MEM8(0x81) +-#define LFWIM 0 +-#define LFBIM 1 +-#define LFEIM 2 +- +-#define LFRCR _SFR_MEM8(0x82) +-#define LFEN 0 +-#define LFBM 1 +-#define LFWM0 2 +-#define LFWM1 3 +-#define LFRSS 4 +-#define LFCS0 5 +-#define LFCS1 6 +-#define LFCS2 7 +- +-#define LFHCR _SFR_MEM8(0x83) +-#define LFHCR0 0 +-#define LFHCR1 1 +-#define LFHCR2 2 +-#define LFHCR3 3 +-#define LFHCR4 4 +-#define LFHCR5 5 +-#define LFHCR6 6 +- +-#define LFIDC _SFR_MEM16(0x84) +- +-#define LFIDCL _SFR_MEM8(0x84) +-#define LFIDCL_0 0 +-#define LFIDCL_1 1 +-#define LFIDCL_2 2 +-#define LFIDCL_3 3 +-#define LFIDCL_4 4 +-#define LFIDCL_5 5 +-#define LFIDCL_6 6 +-#define LFIDCL_7 7 +- +-#define LFIDCH _SFR_MEM8(0x85) +-#define LFIDCH_8 0 +-#define LFIDCH_9 1 +-#define LFIDCH_10 2 +-#define LFIDCH_11 3 +-#define LFIDCH_12 4 +-#define LFIDCH_13 5 +-#define LFIDCH_14 6 +-#define LFIDCH_15 7 +- +-#define LFCAL _SFR_MEM16(0x86) +- +-#define LFCALL _SFR_MEM8(0x86) +-#define LFCAL_00 0 +-#define LFCAL_01 1 +-#define LFCAL_02 2 +-#define LFCAL_03 3 +-#define LFCAL_04 4 +-#define LFCAL_05 5 +-#define LFCAL_06 6 +-#define LFCAL_07 7 +- +-#define LFCALH _SFR_MEM8(0x87) +-#define LFCAL_08 0 +-#define LFCAL_09 1 +-#define LFCAL_10 2 +-#define LFCAL_11 3 +-#define LFCAL_12 4 +-#define LFCAL_13 5 +-#define LFCAL_14 6 +-#define LFCAL_15 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ +-#define PCINT0_vect_num 3 +-#define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ +-#define PCINT1_vect_num 4 +-#define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 1 */ +-#define PCINT2_vect_num 5 +-#define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 2 */ +-#define INTVM_vect_num 6 +-#define INTVM_vect _VECTOR(6) /* Voltage Monitor Interrupt */ +-#define SENINT_vect_num 7 +-#define SENINT_vect _VECTOR(7) /* Sensor Interface Interrupt */ +-#define INTT0_vect_num 8 +-#define INTT0_vect _VECTOR(8) /* Timer0 Interval Interrupt */ +-#define LFWP_vect_num 9 +-#define LFWP_vect _VECTOR(9) /* LF-Receiver Wake-up Interrupt */ +-#define T3CAP_vect_num 10 +-#define T3CAP_vect _VECTOR(10) /* Timer/Counter3 Capture Event */ +-#define T3COMA_vect_num 11 +-#define T3COMA_vect _VECTOR(11) /* Timer/Counter3 Compare Match A */ +-#define T3COMB_vect_num 12 +-#define T3COMB_vect _VECTOR(12) /* Timer/Counter3 Compare Match B */ +-#define T3OVF_vect_num 13 +-#define T3OVF_vect _VECTOR(13) /* Timer/Counter3 Overflow */ +-#define T2CAP_vect_num 14 +-#define T2CAP_vect _VECTOR(14) /* Timer/Counter2 Capture Event */ +-#define T2COM_vect_num 15 +-#define T2COM_vect _VECTOR(15) /* Timer/Counter2 Compare Match */ +-#define T2OVF_vect_num 16 +-#define T2OVF_vect _VECTOR(16) /* Timer/Counter2 Overflow */ +-#define SPISTC_vect_num 17 +-#define SPISTC_vect _VECTOR(17) /* SPI Serial Transfer Complete */ +-#define LFRXB_vect_num 18 +-#define LFRXB_vect _VECTOR(18) /* LF Receive Buffer Interrupt */ +-#define INTT1_vect_num 19 +-#define INTT1_vect _VECTOR(19) /* Timer1 Interval Interrupt */ +-#define T2RXB_vect_num 20 +-#define T2RXB_vect _VECTOR(20) /* Timer2 SSI Receive Buffer Interrupt */ +-#define T2TXB_vect_num 21 +-#define T2TXB_vect _VECTOR(21) /* Timer2 SSI Transmit Buffer Interrupt */ +-#define T2TXC_vect_num 22 +-#define T2TXC_vect _VECTOR(22) /* Timer2 SSI Transmit Complete Interrupt */ +-#define LFREOB_vect_num 23 +-#define LFREOB_vect _VECTOR(23) /* LF-Receiver End of Burst Interrupt */ +-#define EXCM_vect_num 24 +-#define EXCM_vect _VECTOR(24) /* External Input Clock break down Interrupt */ +-#define EEREADY_vect_num 25 +-#define EEREADY_vect _VECTOR(25) /* EEPROM Ready Interrupt */ +-#define SPM_RDY_vect_num 26 +-#define SPM_RDY_vect _VECTOR(26) /* Store Program Memory Ready */ +- +-#define _VECTOR_SIZE 2 /* Size of individual vector. */ +-#define _VECTORS_SIZE (27 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (64) +-#define RAMSTART (0x100) +-#define RAMSIZE (512) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (0) +-#define XRAMEND RAMEND +-#define E2END (320 - 1) +-#define E2PAGESIZE (4) +-#define FLASHEND (8192 - 1) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 2 +- +-/* Low Fuse Byte */ +-#define FUSE_TSRDI ~_BV(0) /* Disable Temperature shutdown Reset */ +-#define FUSE_BODEN ~_BV(1) /* Enable Brown-out detection */ +-#define FUSE_FRCFS ~_BV(2) /* Fast RC-Oscillator Frequency select */ +-#define FUSE_WDRCON ~_BV(3) /* Enable Watchdog RC-Oscillator */ +-#define FUSE_SUT0 ~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 ~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT ~_BV(6) /* Clock output */ +-#define FUSE_CKDIV8 ~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_WDRCON & FUSE_BODEN) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST ~_BV(0) /* Select reset vector */ +-#define FUSE_BOOTSZ0 ~_BV(1) /* Boot size select */ +-#define FUSE_BOOTSZ1 ~_BV(2) /* Boot size select */ +-#define FUSE_EESAVE ~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON ~_BV(4) /* Watchdog Timer Always On */ +-#define FUSE_SPIEN ~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_DWEN ~_BV(6) /* debugWIRE Enable */ +-#define FUSE_EELOCK ~_BV(7) /* Upper EEPROM Locked (disabled) */ +-#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x93 +-#define SIGNATURE_2 0x82 +- +- +-#endif /* _AVR_ATA6289_H_ */ +- ++/* Copyright (c) 2008 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: ioa6289.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ ++ ++/* avr/ioa6289.h - definitions for ATA6289 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "ioa6289.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATA6289_H_ ++#define _AVR_ATA6289_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++ ++#define DDRC _SFR_IO8(0x07) ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define CMCR _SFR_IO8(0x0F) ++#define CMM0 0 ++#define CMM1 1 ++#define SRCD 2 ++#define CMONEN 3 ++#define CCS 4 ++#define ECINS 5 ++#define CMCCE 7 ++ ++#define CMSR _SFR_IO8(0x10) ++#define ECF 0 ++ ++#define T2CRA _SFR_IO8(0x11) ++#define T2OTM 0 ++#define T2CTM 1 ++#define T2CR 2 ++#define T2CRM 3 ++#define T2CPRM 4 ++#define T2ICS 5 ++#define T2TS 6 ++#define T2E 7 ++ ++#define T2CRB _SFR_IO8(0x12) ++#define T2SCE 0 ++ ++#define T3CRA _SFR_IO8(0x14) ++#define T3AC 0 ++#define T3SCE 1 ++#define T3CR 2 ++#define T3TS 6 ++#define T3E 7 ++ ++#define VMCSR _SFR_IO8(0x16) ++#define VMEN 0 ++#define VMLS0 1 ++#define VMLS1 2 ++#define VMLS2 3 ++#define VMIM 4 ++#define VMF 5 ++#define BODPD 6 ++#define BODLS 7 ++ ++#define PCIFR _SFR_IO8(0x17) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++ ++#define LFFR _SFR_IO8(0x18) ++#define LFWPF 0 ++#define LFBF 1 ++#define LFEDF 2 ++#define LFRF 3 ++ ++#define SSFR _SFR_IO8(0x19) ++#define MSENF 0 ++#define MSENO 1 ++ ++#define T10IFR _SFR_IO8(0x1A) ++#define T0F 0 ++#define T1F 1 ++ ++#define T2IFR _SFR_IO8(0x1B) ++#define T2OFF 0 ++#define T2COF 1 ++#define T2ICF 2 ++#define T2RXF 3 ++#define T2TXF 4 ++#define T2TCF 5 ++ ++#define T3IFR _SFR_IO8(0x1C) ++#define T3OFF 0 ++#define T3COAF 1 ++#define T3COBF 2 ++#define T3ICF 3 ++ ++#define EIFR _SFR_IO8(0x1D) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++ ++#define PCICR _SFR_IO8(0x23) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++ ++#define EIMSK _SFR_IO8(0x24) ++#define INT0 0 ++#define INT1 1 ++ ++#define SVCR _SFR_IO8(0x27) ++#define SVCS0 0 ++#define SVCS1 1 ++#define SVCS2 2 ++#define SVCS3 3 ++#define SVCS4 4 ++ ++#define SCR _SFR_IO8(0x28) ++#define SMS 0 ++#define SEN0 1 ++#define SEN1 2 ++#define SMEN 3 ++ ++#define SCCR _SFR_IO8(0x29) ++#define SRCC0 0 ++#define SRCC1 1 ++#define SCCS0 2 ++#define SCCS1 3 ++#define SCCS2 4 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define T2MDR _SFR_IO8(0x2F) ++#define T2MDR0 0 ++#define T2MDR1 1 ++#define T2MDR2 2 ++#define T2MDR3 3 ++#define T2MDR4 4 ++#define T2MDR5 5 ++#define T2MDR6 6 ++#define T2MDR7 7 ++ ++#define LFRR _SFR_IO8(0x30) ++#define LFRR0 0 ++#define LFRR1 1 ++#define LFRR2 2 ++#define LFRR3 3 ++#define LFRR4 4 ++#define LFRR5 5 ++#define LFRR6 6 ++ ++#define LFCDR _SFR_IO8(0x32) ++#define LFDO 0 ++#define LFRST 6 ++#define LFSCE 7 ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define TSRF 5 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++ ++#define LFRB _SFR_IO8(0x36) ++#define LFRB0 0 ++#define LFRB1 1 ++#define LFRB2 2 ++#define LFRB3 3 ++#define LFRB4 4 ++#define LFRB5 5 ++#define LFRB6 6 ++#define LFRB7 7 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SELFPRGEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define T1CR _SFR_IO8(0x38) ++#define T1PS0 0 ++#define T1PS1 1 ++#define T1PS2 2 ++#define T1CS0 3 ++#define T1CS1 4 ++#define T1CS2 5 ++#define T1IE 7 ++ ++#define T0CR _SFR_IO8(0x39) ++#define T0PAS0 0 ++#define T0PAS1 1 ++#define T0PAS2 2 ++#define T0IE 3 ++#define T0PR 4 ++#define T0PBS0 5 ++#define T0PBS1 6 ++#define T0PBS2 7 ++ ++#define CMIMR _SFR_IO8(0x3B) ++#define ECIE 0 ++ ++#define CLKPR _SFR_IO8(0x3C) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLTPS0 3 ++#define CLTPS1 4 ++#define CLTPS2 5 ++#define CLPCE 7 ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDPS0 0 ++#define WDPS1 1 ++#define WDPS2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define SIMSK _SFR_MEM8(0x61) ++#define MSIE 0 ++ ++#define TSCR _SFR_MEM8(0x64) ++#define TSSD 0 ++ ++#define SRCCAL _SFR_MEM8(0x65) ++#define SCAL0 0 ++#define SCAL1 1 ++#define SCAL2 2 ++#define SCAL3 3 ++#define SCAL4 4 ++#define SCAL5 5 ++#define SCAL6 6 ++#define SCAL7 7 ++ ++#define FRCCAL _SFR_MEM8(0x66) ++#define FCAL0 0 ++#define FCAL1 1 ++#define FCAL2 2 ++#define FCAL3 3 ++#define FCAL4 4 ++#define FCAL5 5 ++#define FCAL6 6 ++#define FCAL7 7 ++ ++#define MSVCAL _SFR_MEM8(0x67) ++#define VRCAL0 0 ++#define VRCAL1 1 ++#define VRCAL2 2 ++#define VRCAL3 3 ++#define VRCAL4 4 ++#define VRCAL5 5 ++#define VRCAL6 6 ++#define VRCAL7 7 ++ ++#define BGCAL _SFR_MEM8(0x68) ++#define BGCAL0 0 ++#define BGCAL1 1 ++#define BGCAL2 2 ++#define BGCAL3 3 ++#define BGCAL4 4 ++#define BGCAL5 5 ++#define BGCAL6 6 ++#define BGCAL7 7 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++#define PCMSK0 _SFR_MEM8(0x6A) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6B) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++ ++#define PCMSK2 _SFR_MEM8(0x6C) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define T2ICR _SFR_MEM16(0x6E) ++ ++#define T2ICRL _SFR_MEM8(0x6E) ++#define T2ICRL0 0 ++#define T2ICRL1 1 ++#define T2ICRL2 2 ++#define T2ICRL3 3 ++#define T2ICRL4 4 ++#define T2ICRL5 5 ++#define T2ICRL6 6 ++#define T2ICRL7 7 ++ ++#define T2ICRH _SFR_MEM8(0x6F) ++#define T2ICRH0 0 ++#define T2ICRH1 1 ++#define T2ICRH2 2 ++#define T2ICRH3 3 ++#define T2ICRH4 4 ++#define T2ICRH5 5 ++#define T2ICRH6 6 ++#define T2ICRH7 7 ++ ++#define T2COR _SFR_MEM16(0x70) ++ ++#define T2CORL _SFR_MEM8(0x70) ++#define T2CORL0 0 ++#define T2CORL1 1 ++#define T2CORL2 2 ++#define T2CORL3 3 ++#define T2CORL4 4 ++#define T2CORL5 5 ++#define T2CORL6 6 ++#define T2CORL7 7 ++ ++#define T2CORH _SFR_MEM8(0x71) ++#define T2CORH0 0 ++#define T2CORH1 1 ++#define T2CORH2 2 ++#define T2CORH3 3 ++#define T2CORH4 4 ++#define T2CORH5 5 ++#define T2CORH6 6 ++#define T2CORH7 7 ++ ++#define T2MRA _SFR_MEM8(0x72) ++#define T2CS0 0 ++#define T2CS1 1 ++#define T2CS2 2 ++#define T2CE0 3 ++#define T2CE1 4 ++#define T2CNC 5 ++#define T2TP0 6 ++#define T2TP1 7 ++ ++#define T2MRB _SFR_MEM8(0x73) ++#define T2M0 0 ++#define T2M1 1 ++#define T2M2 2 ++#define T2M3 3 ++#define T2TOP 4 ++#define T2CPOL 6 ++#define T2SSIE 7 ++ ++#define T2IMR _SFR_MEM8(0x74) ++#define T2OIM 0 ++#define T2CIM 1 ++#define T2CPIM 2 ++#define T2RXIM 3 ++#define T2TXIM 4 ++#define T2TCIM 5 ++ ++#define T3ICR _SFR_MEM16(0x76) ++ ++#define T3ICRL _SFR_MEM8(0x76) ++#define T3ICRL0 0 ++#define T3ICRL1 1 ++#define T3ICRL2 2 ++#define T3ICRL3 3 ++#define T3ICRL4 4 ++#define T3ICRL5 5 ++#define T3ICRL6 6 ++#define T3ICRL7 7 ++ ++#define T3ICRH _SFR_MEM8(0x77) ++#define T3ICRH0 0 ++#define T3ICRH1 1 ++#define T3ICRH2 2 ++#define T3ICRH3 3 ++#define T3ICRH4 4 ++#define T3ICRH5 5 ++#define T3ICRH6 6 ++#define T3ICRH7 7 ++ ++#define T3CORA _SFR_MEM16(0x78) ++ ++#define T3CORAL _SFR_MEM8(0x78) ++#define T3CORAL0 0 ++#define T3CORAL1 1 ++#define T3CORAL2 2 ++#define T3CORAL3 3 ++#define T3CORAL4 4 ++#define T3CORAL5 5 ++#define T3CORAL6 6 ++#define T3CORAL7 7 ++ ++#define T3CORAH _SFR_MEM8(0x79) ++#define T3CORAH0 0 ++#define T3CORAH1 1 ++#define T3CORAH2 2 ++#define T3CORAH3 3 ++#define T3CORAH4 4 ++#define T3CORAH5 5 ++#define T3CORAH6 6 ++#define T3CORAH7 7 ++ ++#define T3CORB _SFR_MEM16(0x7A) ++ ++#define T3CORBL _SFR_MEM8(0x7A) ++#define T3CORBL0 0 ++#define T3CORBL1 1 ++#define T3CORBL2 2 ++#define T3CORBL3 3 ++#define T3CORBL4 4 ++#define T3CORBL5 5 ++#define T3CORBL6 6 ++#define T3CORBL7 7 ++ ++#define T3CORBH _SFR_MEM8(0x7B) ++#define T3CORBH0 0 ++#define T3CORBH1 1 ++#define T3CORBH2 2 ++#define T3CORBH3 3 ++#define T3CORBH4 4 ++#define T3CORBH5 5 ++#define T3CORBH6 6 ++#define T3CORBH7 7 ++ ++#define T3MRA _SFR_MEM8(0x7C) ++#define T3CS0 0 ++#define T3CS1 1 ++#define T3CS2 2 ++#define T3CE0 3 ++#define T3CE1 4 ++#define T3CNC 5 ++#define T3ICS0 6 ++#define T3ICS1 7 ++ ++#define T3MRB _SFR_MEM8(0x7D) ++#define T3M0 0 ++#define T3M1 1 ++#define T3M2 2 ++#define T3TOP 4 ++ ++#define T3CRB _SFR_MEM8(0x7E) ++#define T3CTMA 0 ++#define T3SAMA 1 ++#define T3CRMA 2 ++#define T3CTMB 3 ++#define T3SAMB 4 ++#define T3CRMB 5 ++#define T3CPRM 6 ++ ++#define T3IMR _SFR_MEM8(0x7F) ++#define T3OIM 0 ++#define T3CAIM 1 ++#define T3CBIM 2 ++#define T3CPIM 3 ++ ++#define LFIMR _SFR_MEM8(0x81) ++#define LFWIM 0 ++#define LFBIM 1 ++#define LFEIM 2 ++ ++#define LFRCR _SFR_MEM8(0x82) ++#define LFEN 0 ++#define LFBM 1 ++#define LFWM0 2 ++#define LFWM1 3 ++#define LFRSS 4 ++#define LFCS0 5 ++#define LFCS1 6 ++#define LFCS2 7 ++ ++#define LFHCR _SFR_MEM8(0x83) ++#define LFHCR0 0 ++#define LFHCR1 1 ++#define LFHCR2 2 ++#define LFHCR3 3 ++#define LFHCR4 4 ++#define LFHCR5 5 ++#define LFHCR6 6 ++ ++#define LFIDC _SFR_MEM16(0x84) ++ ++#define LFIDCL _SFR_MEM8(0x84) ++#define LFIDCL_0 0 ++#define LFIDCL_1 1 ++#define LFIDCL_2 2 ++#define LFIDCL_3 3 ++#define LFIDCL_4 4 ++#define LFIDCL_5 5 ++#define LFIDCL_6 6 ++#define LFIDCL_7 7 ++ ++#define LFIDCH _SFR_MEM8(0x85) ++#define LFIDCH_8 0 ++#define LFIDCH_9 1 ++#define LFIDCH_10 2 ++#define LFIDCH_11 3 ++#define LFIDCH_12 4 ++#define LFIDCH_13 5 ++#define LFIDCH_14 6 ++#define LFIDCH_15 7 ++ ++#define LFCAL _SFR_MEM16(0x86) ++ ++#define LFCALL _SFR_MEM8(0x86) ++#define LFCAL_00 0 ++#define LFCAL_01 1 ++#define LFCAL_02 2 ++#define LFCAL_03 3 ++#define LFCAL_04 4 ++#define LFCAL_05 5 ++#define LFCAL_06 6 ++#define LFCAL_07 7 ++ ++#define LFCALH _SFR_MEM8(0x87) ++#define LFCAL_08 0 ++#define LFCAL_09 1 ++#define LFCAL_10 2 ++#define LFCAL_11 3 ++#define LFCAL_12 4 ++#define LFCAL_13 5 ++#define LFCAL_14 6 ++#define LFCAL_15 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ ++#define PCINT0_vect_num 3 ++#define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect_num 4 ++#define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 1 */ ++#define PCINT2_vect_num 5 ++#define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 2 */ ++#define INTVM_vect_num 6 ++#define INTVM_vect _VECTOR(6) /* Voltage Monitor Interrupt */ ++#define SENINT_vect_num 7 ++#define SENINT_vect _VECTOR(7) /* Sensor Interface Interrupt */ ++#define INTT0_vect_num 8 ++#define INTT0_vect _VECTOR(8) /* Timer0 Interval Interrupt */ ++#define LFWP_vect_num 9 ++#define LFWP_vect _VECTOR(9) /* LF-Receiver Wake-up Interrupt */ ++#define T3CAP_vect_num 10 ++#define T3CAP_vect _VECTOR(10) /* Timer/Counter3 Capture Event */ ++#define T3COMA_vect_num 11 ++#define T3COMA_vect _VECTOR(11) /* Timer/Counter3 Compare Match A */ ++#define T3COMB_vect_num 12 ++#define T3COMB_vect _VECTOR(12) /* Timer/Counter3 Compare Match B */ ++#define T3OVF_vect_num 13 ++#define T3OVF_vect _VECTOR(13) /* Timer/Counter3 Overflow */ ++#define T2CAP_vect_num 14 ++#define T2CAP_vect _VECTOR(14) /* Timer/Counter2 Capture Event */ ++#define T2COM_vect_num 15 ++#define T2COM_vect _VECTOR(15) /* Timer/Counter2 Compare Match */ ++#define T2OVF_vect_num 16 ++#define T2OVF_vect _VECTOR(16) /* Timer/Counter2 Overflow */ ++#define SPISTC_vect_num 17 ++#define SPISTC_vect _VECTOR(17) /* SPI Serial Transfer Complete */ ++#define LFRXB_vect_num 18 ++#define LFRXB_vect _VECTOR(18) /* LF Receive Buffer Interrupt */ ++#define INTT1_vect_num 19 ++#define INTT1_vect _VECTOR(19) /* Timer1 Interval Interrupt */ ++#define T2RXB_vect_num 20 ++#define T2RXB_vect _VECTOR(20) /* Timer2 SSI Receive Buffer Interrupt */ ++#define T2TXB_vect_num 21 ++#define T2TXB_vect _VECTOR(21) /* Timer2 SSI Transmit Buffer Interrupt */ ++#define T2TXC_vect_num 22 ++#define T2TXC_vect _VECTOR(22) /* Timer2 SSI Transmit Complete Interrupt */ ++#define LFREOB_vect_num 23 ++#define LFREOB_vect _VECTOR(23) /* LF-Receiver End of Burst Interrupt */ ++#define EXCM_vect_num 24 ++#define EXCM_vect _VECTOR(24) /* External Input Clock break down Interrupt */ ++#define EEREADY_vect_num 25 ++#define EEREADY_vect _VECTOR(25) /* EEPROM Ready Interrupt */ ++#define SPM_RDY_vect_num 26 ++#define SPM_RDY_vect _VECTOR(26) /* Store Program Memory Ready */ ++ ++#define _VECTOR_SIZE 2 /* Size of individual vector. */ ++#define _VECTORS_SIZE (27 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (64) ++#define RAMSTART (0x100) ++#define RAMSIZE (512) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (0) ++#define XRAMEND RAMEND ++#define E2END (320 - 1) ++#define E2PAGESIZE (4) ++#define FLASHEND (8192 - 1) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 2 ++ ++/* Low Fuse Byte */ ++#define FUSE_TSRDI ~_BV(0) /* Disable Temperature shutdown Reset */ ++#define FUSE_BODEN ~_BV(1) /* Enable Brown-out detection */ ++#define FUSE_FRCFS ~_BV(2) /* Fast RC-Oscillator Frequency select */ ++#define FUSE_WDRCON ~_BV(3) /* Enable Watchdog RC-Oscillator */ ++#define FUSE_SUT0 ~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 ~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT ~_BV(6) /* Clock output */ ++#define FUSE_CKDIV8 ~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_WDRCON & FUSE_BODEN) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST ~_BV(0) /* Select reset vector */ ++#define FUSE_BOOTSZ0 ~_BV(1) /* Boot size select */ ++#define FUSE_BOOTSZ1 ~_BV(2) /* Boot size select */ ++#define FUSE_EESAVE ~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON ~_BV(4) /* Watchdog Timer Always On */ ++#define FUSE_SPIEN ~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_DWEN ~_BV(6) /* debugWIRE Enable */ ++#define FUSE_EELOCK ~_BV(7) /* Upper EEPROM Locked (disabled) */ ++#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x82 ++ ++ ++#endif /* _AVR_ATA6289_H_ */ ++ +diff --git a/include/avr/ioa6612c.h b/include/avr/ioa6612c.h +new file mode 100644 +index 0000000..defe58d +--- /dev/null ++++ b/include/avr/ioa6612c.h +@@ -0,0 +1,771 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATA6612C_H_INCLUDED ++#define _AVR_ATA6612C_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "ioa6612c.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++/* Reserved [0x0C..0x14] */ ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++/* Reserved [0x18..0x1A] */ ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define TSM 7 ++#define PSRASY 1 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++ ++#define OCR0A _SFR_IO8(0x27) ++ ++#define OCR0B _SFR_IO8(0x28) ++ ++/* Reserved [0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++/* Reserved [0x31..0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SELFPRGEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDE 3 ++#define WDCE 4 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++/* Reserved [0x67] */ ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++/* Reserved [0x71..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++#define OCR2B _SFR_MEM8(0xB4) ++ ++/* Reserved [0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++ ++/* Reserved [0xB7] */ ++ ++#define TWBR _SFR_MEM8(0xB8) ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++/* Reserved [0xBE..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCPHA0 1 ++#define UDORD0 2 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0xC6) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(3) ++#define PCINT0_vect_num 3 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect _VECTOR(4) ++#define PCINT1_vect_num 4 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT2_vect _VECTOR(5) ++#define PCINT2_vect_num 5 ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect _VECTOR(6) ++#define WDT_vect_num 6 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPA_vect _VECTOR(7) ++#define TIMER2_COMPA_vect_num 7 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPB_vect _VECTOR(8) ++#define TIMER2_COMPB_vect_num 8 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(9) ++#define TIMER2_OVF_vect_num 9 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(10) ++#define TIMER1_CAPT_vect_num 10 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(11) ++#define TIMER1_COMPA_vect_num 11 ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(12) ++#define TIMER1_COMPB_vect_num 12 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(13) ++#define TIMER1_OVF_vect_num 13 ++ ++/* TimerCounter0 Compare Match A */ ++#define TIMER0_COMPA_vect _VECTOR(14) ++#define TIMER0_COMPA_vect_num 14 ++ ++/* TimerCounter0 Compare Match B */ ++#define TIMER0_COMPB_vect _VECTOR(15) ++#define TIMER0_COMPB_vect_num 15 ++ ++/* Timer/Couner0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(16) ++#define TIMER0_OVF_vect_num 16 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(17) ++#define SPI_STC_vect_num 17 ++ ++/* USART Rx Complete */ ++#define USART_RX_vect _VECTOR(18) ++#define USART_RX_vect_num 18 ++ ++/* USART, Data Register Empty */ ++#define USART_UDRE_vect _VECTOR(19) ++#define USART_UDRE_vect_num 19 ++ ++/* USART Tx Complete */ ++#define USART_TX_vect _VECTOR(20) ++#define USART_TX_vect_num 20 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(21) ++#define ADC_vect_num 21 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(22) ++#define EE_READY_vect_num 22 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(23) ++#define ANALOG_COMP_vect_num 23 ++ ++/* Two-wire Serial Interface */ ++#define TWI_vect _VECTOR(24) ++#define TWI_vect_num 24 ++ ++/* Store Program Memory Read */ ++#define SPM_Ready_vect _VECTOR(25) ++#define SPM_Ready_vect_num 25 ++ ++#define _VECTORS_SIZE 52 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 64 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x1FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 1024 ++#define RAMEND 0x04FF ++#define E2START 0 ++#define E2SIZE 512 ++#define E2PAGESIZE 4 ++#define E2END 0x01FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x0A ++ ++ ++#endif /* #ifdef _AVR_ATA6612C_H_INCLUDED */ ++ +diff --git a/include/avr/ioa6613c.h b/include/avr/ioa6613c.h +new file mode 100644 +index 0000000..64fc2c1 +--- /dev/null ++++ b/include/avr/ioa6613c.h +@@ -0,0 +1,771 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATA6613C_H_INCLUDED ++#define _AVR_ATA6613C_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "ioa6613c.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++/* Reserved [0x0C..0x14] */ ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++/* Reserved [0x18..0x1A] */ ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define TSM 7 ++#define PSRASY 1 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++ ++#define OCR0A _SFR_IO8(0x27) ++ ++#define OCR0B _SFR_IO8(0x28) ++ ++/* Reserved [0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++/* Reserved [0x31..0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SELFPRGEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDE 3 ++#define WDCE 4 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++/* Reserved [0x67] */ ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++/* Reserved [0x71..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++#define OCR2B _SFR_MEM8(0xB4) ++ ++/* Reserved [0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++ ++/* Reserved [0xB7] */ ++ ++#define TWBR _SFR_MEM8(0xB8) ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++/* Reserved [0xBE..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCPHA0 1 ++#define UDORD0 2 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0xC6) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(3) ++#define PCINT0_vect_num 3 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect _VECTOR(4) ++#define PCINT1_vect_num 4 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT2_vect _VECTOR(5) ++#define PCINT2_vect_num 5 ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect _VECTOR(6) ++#define WDT_vect_num 6 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPA_vect _VECTOR(7) ++#define TIMER2_COMPA_vect_num 7 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPB_vect _VECTOR(8) ++#define TIMER2_COMPB_vect_num 8 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(9) ++#define TIMER2_OVF_vect_num 9 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(10) ++#define TIMER1_CAPT_vect_num 10 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(11) ++#define TIMER1_COMPA_vect_num 11 ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(12) ++#define TIMER1_COMPB_vect_num 12 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(13) ++#define TIMER1_OVF_vect_num 13 ++ ++/* TimerCounter0 Compare Match A */ ++#define TIMER0_COMPA_vect _VECTOR(14) ++#define TIMER0_COMPA_vect_num 14 ++ ++/* TimerCounter0 Compare Match B */ ++#define TIMER0_COMPB_vect _VECTOR(15) ++#define TIMER0_COMPB_vect_num 15 ++ ++/* Timer/Couner0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(16) ++#define TIMER0_OVF_vect_num 16 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(17) ++#define SPI_STC_vect_num 17 ++ ++/* USART Rx Complete */ ++#define USART_RX_vect _VECTOR(18) ++#define USART_RX_vect_num 18 ++ ++/* USART, Data Register Empty */ ++#define USART_UDRE_vect _VECTOR(19) ++#define USART_UDRE_vect_num 19 ++ ++/* USART Tx Complete */ ++#define USART_TX_vect _VECTOR(20) ++#define USART_TX_vect_num 20 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(21) ++#define ADC_vect_num 21 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(22) ++#define EE_READY_vect_num 22 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(23) ++#define ANALOG_COMP_vect_num 23 ++ ++/* Two-wire Serial Interface */ ++#define TWI_vect _VECTOR(24) ++#define TWI_vect_num 24 ++ ++/* Store Program Memory Read */ ++#define SPM_Ready_vect _VECTOR(25) ++#define SPM_Ready_vect_num 25 ++ ++#define _VECTORS_SIZE 104 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 128 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x3FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 1024 ++#define RAMEND 0x04FF ++#define E2START 0 ++#define E2SIZE 512 ++#define E2PAGESIZE 4 ++#define E2END 0x01FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x06 ++ ++ ++#endif /* #ifdef _AVR_ATA6613C_H_INCLUDED */ ++ +diff --git a/include/avr/ioa6614q.h b/include/avr/ioa6614q.h +new file mode 100644 +index 0000000..42c37d1 +--- /dev/null ++++ b/include/avr/ioa6614q.h +@@ -0,0 +1,773 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATA6614Q_H_INCLUDED ++#define _AVR_ATA6614Q_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "ioa6614q.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++/* Reserved [0x0C..0x14] */ ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++/* Reserved [0x18..0x1A] */ ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define TSM 7 ++#define PSRASY 1 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++ ++#define OCR0A _SFR_IO8(0x27) ++ ++#define OCR0B _SFR_IO8(0x28) ++ ++/* Reserved [0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++/* Reserved [0x31..0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SELFPRGEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDE 3 ++#define WDCE 4 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++/* Reserved [0x67] */ ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++/* Reserved [0x71..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++#define OCR2B _SFR_MEM8(0xB4) ++ ++/* Reserved [0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++ ++/* Reserved [0xB7] */ ++ ++#define TWBR _SFR_MEM8(0xB8) ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++/* Reserved [0xBE..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCPHA0 1 ++#define UDORD0 2 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0xC6) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(3) ++#define PCINT0_vect_num 3 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect _VECTOR(4) ++#define PCINT1_vect_num 4 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT2_vect _VECTOR(5) ++#define PCINT2_vect_num 5 ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect _VECTOR(6) ++#define WDT_vect_num 6 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPA_vect _VECTOR(7) ++#define TIMER2_COMPA_vect_num 7 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPB_vect _VECTOR(8) ++#define TIMER2_COMPB_vect_num 8 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(9) ++#define TIMER2_OVF_vect_num 9 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(10) ++#define TIMER1_CAPT_vect_num 10 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(11) ++#define TIMER1_COMPA_vect_num 11 ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(12) ++#define TIMER1_COMPB_vect_num 12 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(13) ++#define TIMER1_OVF_vect_num 13 ++ ++/* TimerCounter0 Compare Match A */ ++#define TIMER0_COMPA_vect _VECTOR(14) ++#define TIMER0_COMPA_vect_num 14 ++ ++/* TimerCounter0 Compare Match B */ ++#define TIMER0_COMPB_vect _VECTOR(15) ++#define TIMER0_COMPB_vect_num 15 ++ ++/* Timer/Couner0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(16) ++#define TIMER0_OVF_vect_num 16 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(17) ++#define SPI_STC_vect_num 17 ++ ++/* USART Rx Complete */ ++#define USART_RX_vect _VECTOR(18) ++#define USART_RX_vect_num 18 ++ ++/* USART, Data Register Empty */ ++#define USART_UDRE_vect _VECTOR(19) ++#define USART_UDRE_vect_num 19 ++ ++/* USART Tx Complete */ ++#define USART_TX_vect _VECTOR(20) ++#define USART_TX_vect_num 20 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(21) ++#define ADC_vect_num 21 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(22) ++#define EE_READY_vect_num 22 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(23) ++#define ANALOG_COMP_vect_num 23 ++ ++/* Two-wire Serial Interface */ ++#define TWI_vect _VECTOR(24) ++#define TWI_vect_num 24 ++ ++/* Store Program Memory Read */ ++#define SPM_Ready_vect _VECTOR(25) ++#define SPM_Ready_vect_num 25 ++ ++#define _VECTORS_SIZE 104 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 128 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x7FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 2048 ++#define RAMEND 0x08FF ++#define E2START 0 ++#define E2SIZE 1024 ++#define E2PAGESIZE 4 ++#define E2END 0x03FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x0F ++ ++ ++#endif /* #ifdef _AVR_ATA6614Q_H_INCLUDED */ ++ +diff --git a/include/avr/ioa6616c.h b/include/avr/ioa6616c.h +new file mode 100644 +index 0000000..00f8a8d +--- /dev/null ++++ b/include/avr/ioa6616c.h +@@ -0,0 +1,844 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATA6616C_H_INCLUDED ++#define _AVR_ATA6616C_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "ioa6616c.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++#define DDA4 4 ++#define DDA5 5 ++#define DDA6 6 ++#define DDA7 7 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++/* Reserved [0x06..0x11] */ ++ ++#define PORTCR _SFR_IO8(0x12) ++#define PUDA 0 ++#define PUDB 1 ++#define BBMA 4 ++#define BBMB 5 ++ ++/* Reserved [0x13..0x14] */ ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++/* Reserved [0x17..0x1A] */ ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR1 0 ++#define PSR0 1 ++#define TSM 7 ++ ++/* Reserved [0x24] */ ++ ++#define TCCR0A _SFR_IO8(0x25) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x26) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x27) ++#define TCNT00 0 ++#define TCNT01 1 ++#define TCNT02 2 ++#define TCNT03 3 ++#define TCNT04 4 ++#define TCNT05 5 ++#define TCNT06 6 ++#define TCNT07 7 ++ ++#define OCR0A _SFR_IO8(0x28) ++#define OCR00 0 ++#define OCR01 1 ++#define OCR02 2 ++#define OCR03 3 ++#define OCR04 4 ++#define OCR05 5 ++#define OCR06 6 ++#define OCR07 7 ++ ++/* Reserved [0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACIRS 6 ++#define ACD 7 ++ ++#define DWDR _SFR_IO8(0x31) ++#define DWDR0 0 ++#define DWDR1 1 ++#define DWDR2 2 ++#define DWDR3 3 ++#define DWDR4 4 ++#define DWDR5 5 ++#define DWDR6 6 ++#define DWDR7 7 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define RFLB 3 ++#define CTPB 4 ++#define SIGRD 5 ++#define RWWSB 6 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDE 3 ++#define WDCE 4 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define CLKCSR _SFR_MEM8(0x62) ++#define CLKC0 0 ++#define CLKC1 1 ++#define CLKC2 2 ++#define CLKC3 3 ++#define CLKRDY 4 ++#define CLKCCE 7 ++ ++#define CLKSELR _SFR_MEM8(0x63) ++#define CSEL0 0 ++#define CSEL1 1 ++#define CSEL2 2 ++#define CSEL3 3 ++#define CSUT0 4 ++#define CSUT1 5 ++#define COUT 6 ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSI 1 ++#define PRTIM0 2 ++#define PRTIM1 3 ++#define PRSPI 4 ++#define PRLIN 5 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++/* Reserved [0x67] */ ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++/* Reserved [0x6D] */ ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++/* Reserved [0x70..0x76] */ ++ ++#define AMISCR _SFR_MEM8(0x77) ++#define XREFEN 1 ++#define AREFEN 2 ++#define ISRCEN 0 ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define BIN 7 ++#define ACIR0 4 ++#define ACIR1 5 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define ADC8D 0 ++#define ADC9D 1 ++#define ADC10D 2 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCCR1D _SFR_MEM8(0x83) ++#define OC1AU 0 ++#define OC1AV 1 ++#define OC1AW 2 ++#define OC1AX 3 ++#define OC1BU 4 ++#define OC1BV 5 ++#define OC1BW 6 ++#define OC1BX 7 ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR0BUB 0 ++#define TCR0AUB 1 ++#define OCR0AUB 3 ++#define TCN0UB 4 ++#define AS0 5 ++#define EXCLK 6 ++ ++/* Reserved [0xB7] */ ++ ++#define USICR _SFR_MEM8(0xB8) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_MEM8(0xB9) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_MEM8(0xBA) ++#define USIDR0 0 ++#define USIDR1 1 ++#define USIDR2 2 ++#define USIDR3 3 ++#define USIDR4 4 ++#define USIDR5 5 ++#define USIDR6 6 ++#define USIDR7 7 ++ ++#define USIBR _SFR_MEM8(0xBB) ++#define USIBR0 0 ++#define USIBR1 1 ++#define USIBR2 2 ++#define USIBR3 3 ++#define USIBR4 4 ++#define USIBR5 5 ++#define USIBR6 6 ++#define USIBR7 7 ++ ++#define USIPP _SFR_MEM8(0xBC) ++#define USIPOS 0 ++ ++/* Reserved [0xBD..0xC7] */ ++ ++#define LINCR _SFR_MEM8(0xC8) ++#define LCMD0 0 ++#define LCMD1 1 ++#define LCMD2 2 ++#define LENA 3 ++#define LCONF0 4 ++#define LCONF1 5 ++#define LIN13 6 ++#define LSWRES 7 ++ ++#define LINSIR _SFR_MEM8(0xC9) ++#define LRXOK 0 ++#define LTXOK 1 ++#define LIDOK 2 ++#define LERR 3 ++#define LBUSY 4 ++#define LIDST0 5 ++#define LIDST1 6 ++#define LIDST2 7 ++ ++#define LINENIR _SFR_MEM8(0xCA) ++#define LENRXOK 0 ++#define LENTXOK 1 ++#define LENIDOK 2 ++#define LENERR 3 ++ ++#define LINERR _SFR_MEM8(0xCB) ++#define LBERR 0 ++#define LCERR 1 ++#define LPERR 2 ++#define LSERR 3 ++#define LFERR 4 ++#define LOVERR 5 ++#define LTOERR 6 ++#define LABORT 7 ++ ++#define LINBTR _SFR_MEM8(0xCC) ++#define LBT0 0 ++#define LBT1 1 ++#define LBT2 2 ++#define LBT3 3 ++#define LBT4 4 ++#define LBT5 5 ++#define LDISR 7 ++ ++/* Combine LINBRRL and LINBRRH */ ++#define LINBRR _SFR_MEM16(0xCD) ++ ++#define LINBRRL _SFR_MEM8(0xCD) ++#define LINBRRH _SFR_MEM8(0xCE) ++ ++#define LINBRRL _SFR_MEM8(0xCD) ++#define LDIV0 0 ++#define LDIV1 1 ++#define LDIV2 2 ++#define LDIV3 3 ++#define LDIV4 4 ++#define LDIV5 5 ++#define LDIV6 6 ++#define LDIV7 7 ++ ++#define LINBRRH _SFR_MEM8(0xCE) ++#define LDIV8 0 ++#define LDIV9 1 ++#define LDIV10 2 ++#define LDIV11 3 ++ ++#define LINDLR _SFR_MEM8(0xCF) ++#define LRXDL0 0 ++#define LRXDL1 1 ++#define LRXDL2 2 ++#define LRXDL3 3 ++#define LTXDL0 4 ++#define LTXDL1 5 ++#define LTXDL2 6 ++#define LTXDL3 7 ++ ++#define LINIDR _SFR_MEM8(0xD0) ++#define LID0 0 ++#define LID1 1 ++#define LID2 2 ++#define LID3 3 ++#define LID4 4 ++#define LID5 5 ++#define LP0 6 ++#define LP1 7 ++ ++#define LINSEL _SFR_MEM8(0xD1) ++#define LINDX0 0 ++#define LINDX1 1 ++#define LINDX2 2 ++#define LAINC 3 ++ ++#define LINDAT _SFR_MEM8(0xD2) ++#define LDATA0 0 ++#define LDATA1 1 ++#define LDATA2 2 ++#define LDATA3 3 ++#define LDATA4 4 ++#define LDATA5 5 ++#define LDATA6 6 ++#define LDATA7 7 ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(3) ++#define PCINT0_vect_num 3 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(4) ++#define PCINT1_vect_num 4 ++ ++/* Watchdog Time-Out Interrupt */ ++#define WDT_vect _VECTOR(5) ++#define WDT_vect_num 5 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define TIMER1_CAPT_vect_num 6 ++ ++/* Timer/Counter1 Compare Match 1A */ ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define TIMER1_COMPA_vect_num 7 ++ ++/* Timer/Counter1 Compare Match 1B */ ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define TIMER1_COMPB_vect_num 8 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(9) ++#define TIMER1_OVF_vect_num 9 ++ ++/* Timer/Counter0 Compare Match 0A */ ++#define TIMER0_COMPA_vect _VECTOR(10) ++#define TIMER0_COMPA_vect_num 10 ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(11) ++#define TIMER0_OVF_vect_num 11 ++ ++/* LIN Transfer Complete */ ++#define LIN_TC_vect _VECTOR(12) ++#define LIN_TC_vect_num 12 ++ ++/* LIN Error */ ++#define LIN_ERR_vect _VECTOR(13) ++#define LIN_ERR_vect_num 13 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(14) ++#define SPI_STC_vect_num 14 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(15) ++#define ADC_vect_num 15 ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect _VECTOR(16) ++#define EE_RDY_vect_num 16 ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect _VECTOR(17) ++#define ANA_COMP_vect_num 17 ++ ++/* USI Start */ ++#define USI_START_vect _VECTOR(18) ++#define USI_START_vect_num 18 ++ ++/* USI Overflow */ ++#define USI_OVF_vect _VECTOR(19) ++#define USI_OVF_vect_num 19 ++ ++#define _VECTORS_SIZE 40 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 128 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x1FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 512 ++#define RAMEND 0x02FF ++#define E2START 0 ++#define E2SIZE 512 ++#define E2PAGESIZE 4 ++#define E2END 0x01FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x87 ++ ++ ++#endif /* #ifdef _AVR_ATA6616C_H_INCLUDED */ ++ +diff --git a/include/avr/ioa6617c.h b/include/avr/ioa6617c.h +new file mode 100644 +index 0000000..4e4588d +--- /dev/null ++++ b/include/avr/ioa6617c.h +@@ -0,0 +1,756 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATA6617C_H_INCLUDED ++#define _AVR_ATA6617C_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "ioa6617c.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++#define DDA4 4 ++#define DDA5 5 ++#define DDA6 6 ++#define DDA7 7 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++/* Reserved [0x06..0x11] */ ++ ++#define PORTCR _SFR_IO8(0x12) ++#define PUDA 0 ++#define PUDB 1 ++#define BBMA 4 ++#define BBMB 5 ++ ++/* Reserved [0x13..0x14] */ ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++/* Reserved [0x17..0x1A] */ ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR1 0 ++#define PSR0 1 ++#define TSM 7 ++ ++/* Reserved [0x24] */ ++ ++#define TCCR0A _SFR_IO8(0x25) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x26) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x27) ++ ++#define OCR0A _SFR_IO8(0x28) ++ ++/* Reserved [0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACIRS 6 ++#define ACD 7 ++ ++#define DWDR _SFR_IO8(0x31) ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define RFLB 3 ++#define CTPB 4 ++#define SIGRD 5 ++#define RWWSB 6 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDE 3 ++#define WDCE 4 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define CLKCSR _SFR_MEM8(0x62) ++#define CLKC0 0 ++#define CLKC1 1 ++#define CLKC2 2 ++#define CLKC3 3 ++#define CLKRDY 4 ++#define CLKCCE 7 ++ ++#define CLKSELR _SFR_MEM8(0x63) ++#define CSEL0 0 ++#define CSEL1 1 ++#define CSEL2 2 ++#define CSEL3 3 ++#define CSUT0 4 ++#define CSUT1 5 ++#define COUT 6 ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSI 1 ++#define PRTIM0 2 ++#define PRTIM1 3 ++#define PRSPI 4 ++#define PRLIN 5 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++/* Reserved [0x67] */ ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++/* Reserved [0x6D] */ ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++/* Reserved [0x70..0x76] */ ++ ++#define AMISCR _SFR_MEM8(0x77) ++#define XREFEN 1 ++#define AREFEN 2 ++#define ISRCEN 0 ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define BIN 7 ++#define ACIR0 4 ++#define ACIR1 5 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define ADC8D 0 ++#define ADC9D 1 ++#define ADC10D 2 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCCR1D _SFR_MEM8(0x83) ++#define OC1AU 0 ++#define OC1AV 1 ++#define OC1AW 2 ++#define OC1AX 3 ++#define OC1BU 4 ++#define OC1BV 5 ++#define OC1BW 6 ++#define OC1BX 7 ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR0BUB 0 ++#define TCR0AUB 1 ++#define OCR0AUB 3 ++#define TCN0UB 4 ++#define AS0 5 ++#define EXCLK 6 ++ ++/* Reserved [0xB7] */ ++ ++#define USICR _SFR_MEM8(0xB8) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_MEM8(0xB9) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_MEM8(0xBA) ++ ++#define USIBR _SFR_MEM8(0xBB) ++ ++#define USIPP _SFR_MEM8(0xBC) ++#define USIPOS 0 ++ ++/* Reserved [0xBD..0xC7] */ ++ ++#define LINCR _SFR_MEM8(0xC8) ++#define LCMD0 0 ++#define LCMD1 1 ++#define LCMD2 2 ++#define LENA 3 ++#define LCONF0 4 ++#define LCONF1 5 ++#define LIN13 6 ++#define LSWRES 7 ++ ++#define LINSIR _SFR_MEM8(0xC9) ++#define LRXOK 0 ++#define LTXOK 1 ++#define LIDOK 2 ++#define LERR 3 ++#define LBUSY 4 ++#define LIDST0 5 ++#define LIDST1 6 ++#define LIDST2 7 ++ ++#define LINENIR _SFR_MEM8(0xCA) ++#define LENRXOK 0 ++#define LENTXOK 1 ++#define LENIDOK 2 ++#define LENERR 3 ++ ++#define LINERR _SFR_MEM8(0xCB) ++#define LBERR 0 ++#define LCERR 1 ++#define LPERR 2 ++#define LSERR 3 ++#define LFERR 4 ++#define LOVERR 5 ++#define LTOERR 6 ++#define LABORT 7 ++ ++#define LINBTR _SFR_MEM8(0xCC) ++#define LBT0 0 ++#define LBT1 1 ++#define LBT2 2 ++#define LBT3 3 ++#define LBT4 4 ++#define LBT5 5 ++#define LDISR 7 ++ ++/* Combine LINBRRL and LINBRRH */ ++#define LINBRR _SFR_MEM16(0xCD) ++ ++#define LINBRRL _SFR_MEM8(0xCD) ++#define LINBRRH _SFR_MEM8(0xCE) ++ ++#define LINBRRL _SFR_MEM8(0xCD) ++#define LDIV0 0 ++#define LDIV1 1 ++#define LDIV2 2 ++#define LDIV3 3 ++#define LDIV4 4 ++#define LDIV5 5 ++#define LDIV6 6 ++#define LDIV7 7 ++ ++#define LINBRRH _SFR_MEM8(0xCE) ++#define LDIV8 0 ++#define LDIV9 1 ++#define LDIV10 2 ++#define LDIV11 3 ++ ++#define LINDLR _SFR_MEM8(0xCF) ++#define LRXDL0 0 ++#define LRXDL1 1 ++#define LRXDL2 2 ++#define LRXDL3 3 ++#define LTXDL0 4 ++#define LTXDL1 5 ++#define LTXDL2 6 ++#define LTXDL3 7 ++ ++#define LINIDR _SFR_MEM8(0xD0) ++#define LID0 0 ++#define LID1 1 ++#define LID2 2 ++#define LID3 3 ++#define LID4 4 ++#define LID5 5 ++#define LP0 6 ++#define LP1 7 ++ ++#define LINSEL _SFR_MEM8(0xD1) ++#define LINDX0 0 ++#define LINDX1 1 ++#define LINDX2 2 ++#define LAINC 3 ++ ++#define LINDAT _SFR_MEM8(0xD2) ++#define LDATA0 0 ++#define LDATA1 1 ++#define LDATA2 2 ++#define LDATA3 3 ++#define LDATA4 4 ++#define LDATA5 5 ++#define LDATA6 6 ++#define LDATA7 7 ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(3) ++#define PCINT0_vect_num 3 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(4) ++#define PCINT1_vect_num 4 ++ ++/* Watchdog Time-Out Interrupt */ ++#define WDT_vect _VECTOR(5) ++#define WDT_vect_num 5 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define TIMER1_CAPT_vect_num 6 ++ ++/* Timer/Counter1 Compare Match 1A */ ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define TIMER1_COMPA_vect_num 7 ++ ++/* Timer/Counter1 Compare Match 1B */ ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define TIMER1_COMPB_vect_num 8 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(9) ++#define TIMER1_OVF_vect_num 9 ++ ++/* Timer/Counter0 Compare Match 0A */ ++#define TIMER0_COMPA_vect _VECTOR(10) ++#define TIMER0_COMPA_vect_num 10 ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(11) ++#define TIMER0_OVF_vect_num 11 ++ ++/* LIN Transfer Complete */ ++#define LIN_TC_vect _VECTOR(12) ++#define LIN_TC_vect_num 12 ++ ++/* LIN Error */ ++#define LIN_ERR_vect _VECTOR(13) ++#define LIN_ERR_vect_num 13 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(14) ++#define SPI_STC_vect_num 14 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(15) ++#define ADC_vect_num 15 ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect _VECTOR(16) ++#define EE_RDY_vect_num 16 ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect _VECTOR(17) ++#define ANA_COMP_vect_num 17 ++ ++/* USI Start */ ++#define USI_START_vect _VECTOR(18) ++#define USI_START_vect_num 18 ++ ++/* USI Overflow */ ++#define USI_OVF_vect _VECTOR(19) ++#define USI_OVF_vect_num 19 ++ ++#define _VECTORS_SIZE 80 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 128 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x3FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 512 ++#define RAMEND 0x02FF ++#define E2START 0 ++#define E2SIZE 512 ++#define E2PAGESIZE 4 ++#define E2END 0x01FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x87 ++ ++ ++#endif /* #ifdef _AVR_ATA6617C_H_INCLUDED */ ++ +diff --git a/include/avr/ioa664251.h b/include/avr/ioa664251.h +new file mode 100644 +index 0000000..2349896 +--- /dev/null ++++ b/include/avr/ioa664251.h +@@ -0,0 +1,754 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATA664251_H_INCLUDED ++#define _AVR_ATA664251_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "ioa664251.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++#define DDA4 4 ++#define DDA5 5 ++#define DDA6 6 ++#define DDA7 7 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++/* Reserved [0x06..0x11] */ ++ ++#define PORTCR _SFR_IO8(0x12) ++#define PUDA 0 ++#define PUDB 1 ++#define BBMA 4 ++#define BBMB 5 ++ ++/* Reserved [0x13..0x14] */ ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++/* Reserved [0x17..0x1A] */ ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR1 0 ++#define PSR0 1 ++#define TSM 7 ++ ++/* Reserved [0x24] */ ++ ++#define TCCR0A _SFR_IO8(0x25) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x26) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x27) ++ ++#define OCR0A _SFR_IO8(0x28) ++ ++/* Reserved [0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACIRS 6 ++#define ACD 7 ++ ++#define OSCCAL _SFR_IO8(0x31) ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++#define DWDR _SFR_IO8(0x31) ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define RFLB 3 ++#define CTPB 4 ++#define SIGRD 5 ++#define RWWSB 6 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDE 3 ++#define WDCE 4 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define CLKCSR _SFR_MEM8(0x62) ++#define CLKC0 0 ++#define CLKC1 1 ++#define CLKC2 2 ++#define CLKC3 3 ++#define CLKRDY 4 ++#define CLKCCE 7 ++ ++#define CLKSELR _SFR_MEM8(0x63) ++#define CSEL0 0 ++#define CSEL1 1 ++#define CSEL2 2 ++#define CSEL3 3 ++#define CSUT0 4 ++#define CSUT1 5 ++#define COUT 6 ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSI 1 ++#define PRTIM0 2 ++#define PRTIM1 3 ++#define PRSPI 4 ++#define PRLIN 5 ++ ++/* Reserved [0x65..0x67] */ ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++/* Reserved [0x6D] */ ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++/* Reserved [0x70..0x76] */ ++ ++#define AMISCR _SFR_MEM8(0x77) ++#define XREFEN 1 ++#define AREFEN 2 ++#define ISRCEN 0 ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define BIN 7 ++#define ACIR0 4 ++#define ACIR1 5 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define ADC8D 0 ++#define ADC9D 1 ++#define ADC10D 2 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCCR1D _SFR_MEM8(0x83) ++#define OC1AU 0 ++#define OC1AV 1 ++#define OC1AW 2 ++#define OC1AX 3 ++#define OC1BU 4 ++#define OC1BV 5 ++#define OC1BW 6 ++#define OC1BX 7 ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR0BUB 0 ++#define TCR0AUB 1 ++#define OCR0AUB 3 ++#define TCN0UB 4 ++#define AS0 5 ++#define EXCLK 6 ++ ++/* Reserved [0xB7] */ ++ ++#define USICR _SFR_MEM8(0xB8) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_MEM8(0xB9) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_MEM8(0xBA) ++ ++#define USIBR _SFR_MEM8(0xBB) ++ ++#define USIPP _SFR_MEM8(0xBC) ++#define USIPOS 0 ++ ++/* Reserved [0xBD..0xC7] */ ++ ++#define LINCR _SFR_MEM8(0xC8) ++#define LCMD0 0 ++#define LCMD1 1 ++#define LCMD2 2 ++#define LENA 3 ++#define LCONF0 4 ++#define LCONF1 5 ++#define LIN13 6 ++#define LSWRES 7 ++ ++#define LINSIR _SFR_MEM8(0xC9) ++#define LRXOK 0 ++#define LTXOK 1 ++#define LIDOK 2 ++#define LERR 3 ++#define LBUSY 4 ++#define LIDST0 5 ++#define LIDST1 6 ++#define LIDST2 7 ++ ++#define LINENIR _SFR_MEM8(0xCA) ++#define LENRXOK 0 ++#define LENTXOK 1 ++#define LENIDOK 2 ++#define LENERR 3 ++ ++#define LINERR _SFR_MEM8(0xCB) ++#define LBERR 0 ++#define LCERR 1 ++#define LPERR 2 ++#define LSERR 3 ++#define LFERR 4 ++#define LOVERR 5 ++#define LTOERR 6 ++#define LABORT 7 ++ ++#define LINBTR _SFR_MEM8(0xCC) ++#define LBT0 0 ++#define LBT1 1 ++#define LBT2 2 ++#define LBT3 3 ++#define LBT4 4 ++#define LBT5 5 ++#define LDISR 7 ++ ++/* Combine LINBRRL and LINBRRH */ ++#define LINBRR _SFR_MEM16(0xCD) ++ ++#define LINBRRL _SFR_MEM8(0xCD) ++#define LINBRRH _SFR_MEM8(0xCE) ++ ++#define LINBRRL _SFR_MEM8(0xCD) ++#define LDIV0 0 ++#define LDIV1 1 ++#define LDIV2 2 ++#define LDIV3 3 ++#define LDIV4 4 ++#define LDIV5 5 ++#define LDIV6 6 ++#define LDIV7 7 ++ ++#define LINBRRH _SFR_MEM8(0xCE) ++#define LDIV8 0 ++#define LDIV9 1 ++#define LDIV10 2 ++#define LDIV11 3 ++ ++#define LINDLR _SFR_MEM8(0xCF) ++#define LRXDL0 0 ++#define LRXDL1 1 ++#define LRXDL2 2 ++#define LRXDL3 3 ++#define LTXDL0 4 ++#define LTXDL1 5 ++#define LTXDL2 6 ++#define LTXDL3 7 ++ ++#define LINIDR _SFR_MEM8(0xD0) ++#define LID0 0 ++#define LID1 1 ++#define LID2 2 ++#define LID3 3 ++#define LID4 4 ++#define LID5 5 ++#define LP0 6 ++#define LP1 7 ++ ++#define LINSEL _SFR_MEM8(0xD1) ++#define LINDX0 0 ++#define LINDX1 1 ++#define LINDX2 2 ++#define LAINC 3 ++ ++#define LINDAT _SFR_MEM8(0xD2) ++#define LDATA0 0 ++#define LDATA1 1 ++#define LDATA2 2 ++#define LDATA3 3 ++#define LDATA4 4 ++#define LDATA5 5 ++#define LDATA6 6 ++#define LDATA7 7 ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(3) ++#define PCINT0_vect_num 3 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(4) ++#define PCINT1_vect_num 4 ++ ++/* Watchdog Time-Out Interrupt */ ++#define WDT_vect _VECTOR(5) ++#define WDT_vect_num 5 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define TIMER1_CAPT_vect_num 6 ++ ++/* Timer/Counter1 Compare Match 1A */ ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define TIMER1_COMPA_vect_num 7 ++ ++/* Timer/Counter1 Compare Match 1B */ ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define TIMER1_COMPB_vect_num 8 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(9) ++#define TIMER1_OVF_vect_num 9 ++ ++/* Timer/Counter0 Compare Match 0A */ ++#define TIMER0_COMPA_vect _VECTOR(10) ++#define TIMER0_COMPA_vect_num 10 ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(11) ++#define TIMER0_OVF_vect_num 11 ++ ++/* LIN Transfer Complete */ ++#define LIN_TC_vect _VECTOR(12) ++#define LIN_TC_vect_num 12 ++ ++/* LIN Error */ ++#define LIN_ERR_vect _VECTOR(13) ++#define LIN_ERR_vect_num 13 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(14) ++#define SPI_STC_vect_num 14 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(15) ++#define ADC_vect_num 15 ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect _VECTOR(16) ++#define EE_RDY_vect_num 16 ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect _VECTOR(17) ++#define ANA_COMP_vect_num 17 ++ ++/* USI Start */ ++#define USI_START_vect _VECTOR(18) ++#define USI_START_vect_num 18 ++ ++/* USI Overflow */ ++#define USI_OVF_vect _VECTOR(19) ++#define USI_OVF_vect_num 19 ++ ++#define _VECTORS_SIZE 80 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 128 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x3FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 512 ++#define RAMEND 0x02FF ++#define E2START 0 ++#define E2SIZE 512 ++#define E2PAGESIZE 4 ++#define E2END 0x01FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x87 ++ ++ ++#endif /* #ifdef _AVR_ATA664251_H_INCLUDED */ ++ +diff --git a/include/avr/ioat94k.h b/include/avr/ioat94k.h +index 1ae20cf..2cff82d 100644 +--- a/include/avr/ioat94k.h ++++ b/include/avr/ioat94k.h +@@ -1,557 +1,561 @@ +-/* Copyright (c) 2002, Marek Michalkiewicz +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: ioat94k.h 602 2004-11-01 22:23:56Z arcanum $ */ +- +-/* avr/ioat94k.h - definitions for AT94K series FPSLIC(tm) */ +- +-#ifndef _AVR_IOAT94K_H_ +-#define _AVR_IOAT94K_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "ioat94k.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* UART1 Baud Rate Register */ +-#define UBRR1 _SFR_IO8(0x00) +- +-/* UART1 Control and Status Registers */ +-#define UCSR1B _SFR_IO8(0x01) +-#define UCSR1A _SFR_IO8(0x02) +- +-/* UART1 I/O Data Register */ +-#define UDR1 _SFR_IO8(0x03) +- +-/* 0x04 reserved */ +- +-/* Input Pins, Port E */ +-#define PINE _SFR_IO8(0x05) +- +-/* Data Direction Register, Port E */ +-#define DDRE _SFR_IO8(0x06) +- +-/* Data Register, Port E */ +-#define PORTE _SFR_IO8(0x07) +- +-/* On Chip Debug Register (reserved) */ +-#define OCDR _SFR_IO8(0x08) +- +-/* UART0 Baud Rate Register */ +-#define UBRR0 _SFR_IO8(0x09) +- +-/* UART0 Control and Status Registers */ +-#define UCSR0B _SFR_IO8(0x0A) +-#define UCSR0A _SFR_IO8(0x0B) +- +-/* UART0 I/O Data Register */ +-#define UDR0 _SFR_IO8(0x0C) +- +-/* 0x0D..0x0F reserved */ +- +-/* Input Pins, Port D */ +-#define PIND _SFR_IO8(0x10) +- +-/* Data Direction Register, Port D */ +-#define DDRD _SFR_IO8(0x11) +- +-/* Data Register, Port D */ +-#define PORTD _SFR_IO8(0x12) +- +-/* FPGA I/O Select Control Register */ +-#define FISCR _SFR_IO8(0x13) +- +-/* FPGA I/O Select Registers A, B, C, D */ +-#define FISUA _SFR_IO8(0x14) +-#define FISUB _SFR_IO8(0x15) +-#define FISUC _SFR_IO8(0x16) +-#define FISUD _SFR_IO8(0x17) +- +-/* FPGA Cache Logic(R) registers (top secret, under NDA) */ +-#define FPGAX _SFR_IO8(0x18) +-#define FPGAY _SFR_IO8(0x19) +-#define FPGAZ _SFR_IO8(0x1A) +-#define FPGAD _SFR_IO8(0x1B) +- +-/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ +- +-/* 2-wire Serial Bit Rate Register */ +-#define TWBR _SFR_IO8(0x1C) +- +-/* 2-wire Serial Status Register */ +-#define TWSR _SFR_IO8(0x1D) +- +-/* 2-wire Serial (Slave) Address Register */ +-#define TWAR _SFR_IO8(0x1E) +- +-/* 2-wire Serial Data Register */ +-#define TWDR _SFR_IO8(0x1F) +- +-/* UART Baud Register High */ +-#define UBRRH _SFR_IO8(0x20) +-#define UBRRHI UBRRH /* New name in datasheet (1138F-FPSLI-06/02) */ +- +-/* Watchdog Timer Control Register */ +-#define WDTCR _SFR_IO8(0x21) +- +-/* Timer/Counter2 Output Compare Register */ +-#define OCR2 _SFR_IO8(0x22) +- +-/* Timer/Counter2 (8-bit) */ +-#define TCNT2 _SFR_IO8(0x23) +- +-/* Timer/Counter1 Input Capture Register */ +-#define ICR1 _SFR_IO16(0x24) +-#define ICR1L _SFR_IO8(0x24) +-#define ICR1H _SFR_IO8(0x25) +- +-/* Asynchronous mode StatuS Register */ +-#define ASSR _SFR_IO8(0x26) +- +-/* Timer/Counter2 Control Register */ +-#define TCCR2 _SFR_IO8(0x27) +- +-/* Timer/Counter1 Output Compare RegisterB */ +-#define OCR1B _SFR_IO16(0x28) +-#define OCR1BL _SFR_IO8(0x28) +-#define OCR1BH _SFR_IO8(0x29) +- +-/* Timer/Counter1 Output Compare RegisterA */ +-#define OCR1A _SFR_IO16(0x2A) +-#define OCR1AL _SFR_IO8(0x2A) +-#define OCR1AH _SFR_IO8(0x2B) +- +-/* Timer/Counter1 */ +-#define TCNT1 _SFR_IO16(0x2C) +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1H _SFR_IO8(0x2D) +- +-/* Timer/Counter1 Control Register B */ +-#define TCCR1B _SFR_IO8(0x2E) +- +-/* Timer/Counter1 Control Register A */ +-#define TCCR1A _SFR_IO8(0x2F) +- +-/* Special Function IO Register */ +-#define SFIOR _SFR_IO8(0x30) +- +-/* Timer/Counter0 Output Compare Register */ +-#define OCR0 _SFR_IO8(0x31) +- +-/* Timer/Counter0 (8-bit) */ +-#define TCNT0 _SFR_IO8(0x32) +- +-/* Timer/Counter0 Control Register */ +-#define TCCR0 _SFR_IO8(0x33) +- +-/* 0x34 reserved */ +- +-/* MCU Control/Status Register */ +-#define MCUR _SFR_IO8(0x35) +- +-/* 2-wire Serial Control Register */ +-#define TWCR _SFR_IO8(0x36) +- +-/* 0x37 reserved */ +- +-/* Timer/Counter Interrupt Flag Register */ +-#define TIFR _SFR_IO8(0x38) +- +-/* Timer/Counter Interrupt MaSK Register */ +-#define TIMSK _SFR_IO8(0x39) +- +-/* Software Control Register */ +-#define SFTCR _SFR_IO8(0x3A) +- +-/* External Interrupt Mask/Flag Register */ +-#define EIMF _SFR_IO8(0x3B) +- +-/* 0x3C reserved */ +- +-/* 0x3D..0x3E SP */ +- +-/* 0x3F SREG */ +- +-/* Interrupt vectors */ +- +-#define SIG_FPGA_INTERRUPT0 _VECTOR(1) /* FPGA_INT0 */ +-#define SIG_INTERRUPT0 _VECTOR(2) /* EXT_INT0 */ +-#define SIG_FPGA_INTERRUPT1 _VECTOR(3) /* FPGA_INT1 */ +-#define SIG_INTERRUPT1 _VECTOR(4) /* EXT_INT1 */ +-#define SIG_FPGA_INTERRUPT2 _VECTOR(5) /* FPGA_INT2 */ +-#define SIG_INTERRUPT2 _VECTOR(6) /* EXT_INT2 */ +-#define SIG_FPGA_INTERRUPT3 _VECTOR(7) /* FPGA_INT3 */ +-#define SIG_INTERRUPT3 _VECTOR(8) /* EXT_INT3 */ +-#define SIG_OUTPUT_COMPARE2 _VECTOR(9) /* TIM2_COMP */ +-#define SIG_OVERFLOW2 _VECTOR(10) /* TIM2_OVF */ +-#define SIG_INPUT_CAPTURE1 _VECTOR(11) /* TIM1_CAPT */ +-#define SIG_OUTPUT_COMPARE1A _VECTOR(12) /* TIM1_COMPA */ +-#define SIG_OUTPUT_COMPARE1B _VECTOR(13) /* TIM1_COMPB */ +-#define SIG_OVERFLOW1 _VECTOR(14) /* TIM1_OVF */ +-#define SIG_OUTPUT_COMPARE0 _VECTOR(15) /* TIM0_COMP */ +-#define SIG_OVERFLOW0 _VECTOR(16) /* TIM0_OVF */ +-#define SIG_FPGA_INTERRUPT4 _VECTOR(17) /* FPGA_INT4 */ +-#define SIG_FPGA_INTERRUPT5 _VECTOR(18) /* FPGA_INT5 */ +-#define SIG_FPGA_INTERRUPT6 _VECTOR(19) /* FPGA_INT6 */ +-#define SIG_FPGA_INTERRUPT7 _VECTOR(20) /* FPGA_INT7 */ +-#define SIG_UART0_RECV _VECTOR(21) /* UART0_RXC */ +-#define SIG_UART0_DATA _VECTOR(22) /* UART0_DRE */ +-#define SIG_UART0_TRANS _VECTOR(23) /* UART0_TXC */ +-#define SIG_FPGA_INTERRUPT8 _VECTOR(24) /* FPGA_INT8 */ +-#define SIG_FPGA_INTERRUPT9 _VECTOR(25) /* FPGA_INT9 */ +-#define SIG_FPGA_INTERRUPT10 _VECTOR(26) /* FPGA_INT10 */ +-#define SIG_FPGA_INTERRUPT11 _VECTOR(27) /* FPGA_INT11 */ +-#define SIG_UART1_RECV _VECTOR(28) /* UART1_RXC */ +-#define SIG_UART1_DATA _VECTOR(29) /* UART1_DRE */ +-#define SIG_UART1_TRANS _VECTOR(30) /* UART1_TXC */ +-#define SIG_FPGA_INTERRUPT12 _VECTOR(31) /* FPGA_INT12 */ +-#define SIG_FPGA_INTERRUPT13 _VECTOR(32) /* FPGA_INT13 */ +-#define SIG_FPGA_INTERRUPT14 _VECTOR(33) /* FPGA_INT14 */ +-#define SIG_FPGA_INTERRUPT15 _VECTOR(34) /* FPGA_INT15 */ +-#define SIG_2WIRE_SERIAL _VECTOR(35) /* TWS_INT */ +- +-#define _VECTORS_SIZE 144 +- +-/* Bit numbers (SFRs alphabetically sorted) */ +- +-/* ASSR */ +-#define AS2 3 +-#define TCN2UB 2 +-#define OCR2UB 1 +-#define TCR2UB 0 +- +-/* DDRD */ +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-/* DDRE */ +-#define DDE7 7 +-#define DDE6 6 +-#define DDE5 5 +-#define DDE4 4 +-#define DDE3 3 +-#define DDE2 2 +-#define DDE1 1 +-#define DDE0 0 +- +-/* EIMF */ +-#define INTF3 7 +-#define INTF2 6 +-#define INTF1 5 +-#define INTF0 4 +-#define INT3 3 +-#define INT2 2 +-#define INT1 1 +-#define INT0 0 +- +-/* FISCR */ +-#define FIADR 7 +-#define XFIS1 1 +-#define XFIS0 0 +- +-/* FISUA */ +-#define FIF3 7 +-#define FIF2 6 +-#define FIF1 5 +-#define FIF0 4 +-#define FINT3 3 +-#define FINT2 2 +-#define FINT1 1 +-#define FINT0 0 +- +-/* FISUB */ +-#define FIF7 7 +-#define FIF6 6 +-#define FIF5 5 +-#define FIF4 4 +-#define FINT7 3 +-#define FINT6 2 +-#define FINT5 1 +-#define FINT4 0 +- +-/* FISUC */ +-#define FIF11 7 +-#define FIF10 6 +-#define FIF9 5 +-#define FIF8 4 +-#define FINT11 3 +-#define FINT10 2 +-#define FINT9 1 +-#define FINT8 0 +- +-/* FISUD */ +-#define FIF15 7 +-#define FIF14 6 +-#define FIF13 5 +-#define FIF12 4 +-#define FINT15 3 +-#define FINT14 2 +-#define FINT13 1 +-#define FINT12 0 +- +-/* MCUR */ +-#define JTRF 7 +-#define JTD 6 +-#define SE 5 +-#define SM1 4 +-#define SM0 3 +-#define PORF 2 +-#define WDRF 1 +-#define EXTRF 0 +- +-/* OCDR (reserved) */ +-#define IDRD 7 +- +-/* PIND */ +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-/* PINE */ +-#define PINE7 7 +-#define PINE6 6 +-#define PINE5 5 +-#define PINE4 4 +-#define PINE3 3 +-#define PINE2 2 +-#define PINE1 1 +-#define PINE0 0 +- +-/* PORTD */ +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* PORTE */ +-/* +- PE7 = IC1 / INT3 (alternate) +- PE6 = OC1A / INT2 (alternate) +- PE5 = OC1B / INT1 (alternate) +- PE4 = ET11 / INT0 (alternate) +- PE3 = OC2 / RX1 (alternate) +- PE2 = / TX1 (alternate) +- PE1 = OC0 / RX0 (alternate) +- PE0 = ET0 / TX0 (alternate) +- */ +-#define PE7 7 +-#define PE6 6 +-#define PE5 5 +-#define PE4 4 +-#define PE3 3 +-#define PE2 2 +-#define PE1 1 +-#define PE0 0 +- +-/* SFIOR */ +-#define PSR2 1 +-#define PSR10 0 +- +-/* SFTCR */ +-#define FMXOR 3 +-#define WDTS 2 +-#define DBG 1 +-#define SRST 0 +- +-/* TCCR0 */ +-#define FOC0 7 +-#define PWM0 6 +-#define COM01 5 +-#define COM00 4 +-#define CTC0 3 +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* TCCR1A */ +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define FOC1A 3 +-#define FOC1B 2 +-#define PWM11 1 +-#define PWM10 0 +- +-/* TCCR1B */ +-#define ICNC1 7 +-#define ICES1 6 +-#define ICPE 5 +-#define CTC1 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* TCCR2 */ +-#define FOC2 7 +-#define PWM2 6 +-#define COM21 5 +-#define COM20 4 +-#define CTC2 3 +-#define CS22 2 +-#define CS21 1 +-#define CS20 0 +- +-/* TIFR */ +-#define TOV1 7 +-#define OCF1A 6 +-#define OCF1B 5 +-#define TOV2 4 +-#define ICF1 3 +-#define OCF2 2 +-#define TOV0 1 +-#define OCF0 0 +- +-/* TIMSK */ +-#define TOIE1 7 +-#define OCIE1A 6 +-#define OCIE1B 5 +-#define TOIE2 4 +-#define TICIE1 3 +-#define OCIE2 2 +-#define TOIE0 1 +-#define OCIE0 0 +- +-/* TWAR */ +-/* #define TWA 1 */ /* TWA is bits 7:1 */ +-#define TWGCE 0 +- +-/* TWCR */ +-#define TWINT 7 +-#define TWEA 6 +-#define TWSTA 5 +-#define TWSTO 4 +-#define TWWC 3 +-#define TWEN 2 +-#define TWIE 0 +- +-/* TWSR */ +-#define TWS7 7 +-#define TWS6 6 +-#define TWS5 5 +-#define TWS4 4 +-#define TWS3 3 +- +-/* UBRRHI +- Bits 11..8 of UART1 are bits 7..4 of UBRRHI. +- Bits 11..8 of UART0 are bits 3..0 of UBRRHI. */ +-/* #define UBRRHI1 4 */ +-/* #define UBRRHI0 0 */ +- +-/* UCSR0A */ +-#define RXC0 7 +-#define TXC0 6 +-#define UDRE0 5 +-#define FE0 4 +-#define OR0 3 +-#define U2X0 1 +-#define MPCM0 0 +- +-/* UCSR0B */ +-#define RXCIE0 7 +-#define TXCIE0 6 +-#define UDRIE0 5 +-#define RXEN0 4 +-#define TXEN0 3 +-#define CHR90 2 +-#define RXB80 1 +-#define TXB80 0 +- +-/* UCSR1A */ +-#define RXC1 7 +-#define TXC1 6 +-#define UDRE1 5 +-#define FE1 4 +-#define OR1 3 +-#define U2X1 1 +-#define MPCM1 0 +- +-/* UCSR1B */ +-#define RXCIE1 7 +-#define TXCIE1 6 +-#define UDRIE1 5 +-#define RXEN1 4 +-#define TXEN1 3 +-#define CHR91 2 +-#define RXB81 1 +-#define TXB81 0 +- +-/* WDTCR */ +-#define WDTOE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* +- Last memory addresses - depending on configuration, it is possible +- to have 20K-32K of program memory and 4K-16K of data memory +- (all in the same 36K total of SRAM, loaded from external EEPROM). +- */ +- +-#ifndef RAMEND +-#define RAMEND 0x0FFF +-#endif +- +-#ifndef XRAMEND +-#define XRAMEND RAMEND +-#endif +- +-#define E2END 0 +- +-#ifndef FLASHEND +-#define FLASHEND 0x7FFF +-#endif +- +-#endif /* _AVR_IOAT94K_H_ */ ++/* Copyright (c) 2002, Marek Michalkiewicz ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: ioat94k.h 602 2004-11-01 22:23:56Z arcanum $ */ ++ ++/* avr/ioat94k.h - definitions for AT94K series FPSLIC(tm) */ ++ ++#ifndef _AVR_IOAT94K_H_ ++#define _AVR_IOAT94K_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "ioat94k.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* UART1 Baud Rate Register */ ++#define UBRR1 _SFR_IO8(0x00) ++ ++/* UART1 Control and Status Registers */ ++#define UCSR1B _SFR_IO8(0x01) ++#define UCSR1A _SFR_IO8(0x02) ++ ++/* UART1 I/O Data Register */ ++#define UDR1 _SFR_IO8(0x03) ++ ++/* 0x04 reserved */ ++ ++/* Input Pins, Port E */ ++#define PINE _SFR_IO8(0x05) ++ ++/* Data Direction Register, Port E */ ++#define DDRE _SFR_IO8(0x06) ++ ++/* Data Register, Port E */ ++#define PORTE _SFR_IO8(0x07) ++ ++/* On Chip Debug Register (reserved) */ ++#define OCDR _SFR_IO8(0x08) ++ ++/* UART0 Baud Rate Register */ ++#define UBRR0 _SFR_IO8(0x09) ++ ++/* UART0 Control and Status Registers */ ++#define UCSR0B _SFR_IO8(0x0A) ++#define UCSR0A _SFR_IO8(0x0B) ++ ++/* UART0 I/O Data Register */ ++#define UDR0 _SFR_IO8(0x0C) ++ ++/* 0x0D..0x0F reserved */ ++ ++/* Input Pins, Port D */ ++#define PIND _SFR_IO8(0x10) ++ ++/* Data Direction Register, Port D */ ++#define DDRD _SFR_IO8(0x11) ++ ++/* Data Register, Port D */ ++#define PORTD _SFR_IO8(0x12) ++ ++/* FPGA I/O Select Control Register */ ++#define FISCR _SFR_IO8(0x13) ++ ++/* FPGA I/O Select Registers A, B, C, D */ ++#define FISUA _SFR_IO8(0x14) ++#define FISUB _SFR_IO8(0x15) ++#define FISUC _SFR_IO8(0x16) ++#define FISUD _SFR_IO8(0x17) ++ ++/* FPGA Cache Logic(R) registers (top secret, under NDA) */ ++#define FPGAX _SFR_IO8(0x18) ++#define FPGAY _SFR_IO8(0x19) ++#define FPGAZ _SFR_IO8(0x1A) ++#define FPGAD _SFR_IO8(0x1B) ++ ++/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ ++ ++/* 2-wire Serial Bit Rate Register */ ++#define TWBR _SFR_IO8(0x1C) ++ ++/* 2-wire Serial Status Register */ ++#define TWSR _SFR_IO8(0x1D) ++ ++/* 2-wire Serial (Slave) Address Register */ ++#define TWAR _SFR_IO8(0x1E) ++ ++/* 2-wire Serial Data Register */ ++#define TWDR _SFR_IO8(0x1F) ++ ++/* UART Baud Register High */ ++#define UBRRH _SFR_IO8(0x20) ++#define UBRRHI UBRRH /* New name in datasheet (1138F-FPSLI-06/02) */ ++ ++/* Watchdog Timer Control Register */ ++#define WDTCR _SFR_IO8(0x21) ++ ++/* Timer/Counter2 Output Compare Register */ ++#define OCR2 _SFR_IO8(0x22) ++ ++/* Timer/Counter2 (8-bit) */ ++#define TCNT2 _SFR_IO8(0x23) ++ ++/* Timer/Counter1 Input Capture Register */ ++#define ICR1 _SFR_IO16(0x24) ++#define ICR1L _SFR_IO8(0x24) ++#define ICR1H _SFR_IO8(0x25) ++ ++/* Asynchronous mode StatuS Register */ ++#define ASSR _SFR_IO8(0x26) ++ ++/* Timer/Counter2 Control Register */ ++#define TCCR2 _SFR_IO8(0x27) ++ ++/* Timer/Counter1 Output Compare RegisterB */ ++#define OCR1B _SFR_IO16(0x28) ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BH _SFR_IO8(0x29) ++ ++/* Timer/Counter1 Output Compare RegisterA */ ++#define OCR1A _SFR_IO16(0x2A) ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++ ++/* Timer/Counter1 */ ++#define TCNT1 _SFR_IO16(0x2C) ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++ ++/* Timer/Counter1 Control Register B */ ++#define TCCR1B _SFR_IO8(0x2E) ++ ++/* Timer/Counter1 Control Register A */ ++#define TCCR1A _SFR_IO8(0x2F) ++ ++/* Special Function IO Register */ ++#define SFIOR _SFR_IO8(0x30) ++ ++/* Timer/Counter0 Output Compare Register */ ++#define OCR0 _SFR_IO8(0x31) ++ ++/* Timer/Counter0 (8-bit) */ ++#define TCNT0 _SFR_IO8(0x32) ++ ++/* Timer/Counter0 Control Register */ ++#define TCCR0 _SFR_IO8(0x33) ++ ++/* 0x34 reserved */ ++ ++/* MCU Control/Status Register */ ++#define MCUR _SFR_IO8(0x35) ++ ++/* 2-wire Serial Control Register */ ++#define TWCR _SFR_IO8(0x36) ++ ++/* 0x37 reserved */ ++ ++/* Timer/Counter Interrupt Flag Register */ ++#define TIFR _SFR_IO8(0x38) ++ ++/* Timer/Counter Interrupt MaSK Register */ ++#define TIMSK _SFR_IO8(0x39) ++ ++/* Software Control Register */ ++#define SFTCR _SFR_IO8(0x3A) ++ ++/* External Interrupt Mask/Flag Register */ ++#define EIMF _SFR_IO8(0x3B) ++ ++/* 0x3C reserved */ ++ ++/* 0x3D..0x3E SP */ ++ ++/* 0x3F SREG */ ++ ++/* Interrupt vectors */ ++ ++#define SIG_FPGA_INTERRUPT0 _VECTOR(1) /* FPGA_INT0 */ ++#define SIG_INTERRUPT0 _VECTOR(2) /* EXT_INT0 */ ++#define SIG_FPGA_INTERRUPT1 _VECTOR(3) /* FPGA_INT1 */ ++#define SIG_INTERRUPT1 _VECTOR(4) /* EXT_INT1 */ ++#define SIG_FPGA_INTERRUPT2 _VECTOR(5) /* FPGA_INT2 */ ++#define SIG_INTERRUPT2 _VECTOR(6) /* EXT_INT2 */ ++#define SIG_FPGA_INTERRUPT3 _VECTOR(7) /* FPGA_INT3 */ ++#define SIG_INTERRUPT3 _VECTOR(8) /* EXT_INT3 */ ++#define SIG_OUTPUT_COMPARE2 _VECTOR(9) /* TIM2_COMP */ ++#define SIG_OVERFLOW2 _VECTOR(10) /* TIM2_OVF */ ++#define SIG_INPUT_CAPTURE1 _VECTOR(11) /* TIM1_CAPT */ ++#define SIG_OUTPUT_COMPARE1A _VECTOR(12) /* TIM1_COMPA */ ++#define SIG_OUTPUT_COMPARE1B _VECTOR(13) /* TIM1_COMPB */ ++#define SIG_OVERFLOW1 _VECTOR(14) /* TIM1_OVF */ ++#define SIG_OUTPUT_COMPARE0 _VECTOR(15) /* TIM0_COMP */ ++#define SIG_OVERFLOW0 _VECTOR(16) /* TIM0_OVF */ ++#define SIG_FPGA_INTERRUPT4 _VECTOR(17) /* FPGA_INT4 */ ++#define SIG_FPGA_INTERRUPT5 _VECTOR(18) /* FPGA_INT5 */ ++#define SIG_FPGA_INTERRUPT6 _VECTOR(19) /* FPGA_INT6 */ ++#define SIG_FPGA_INTERRUPT7 _VECTOR(20) /* FPGA_INT7 */ ++#define SIG_UART0_RECV _VECTOR(21) /* UART0_RXC */ ++#define SIG_UART0_DATA _VECTOR(22) /* UART0_DRE */ ++#define SIG_UART0_TRANS _VECTOR(23) /* UART0_TXC */ ++#define SIG_FPGA_INTERRUPT8 _VECTOR(24) /* FPGA_INT8 */ ++#define SIG_FPGA_INTERRUPT9 _VECTOR(25) /* FPGA_INT9 */ ++#define SIG_FPGA_INTERRUPT10 _VECTOR(26) /* FPGA_INT10 */ ++#define SIG_FPGA_INTERRUPT11 _VECTOR(27) /* FPGA_INT11 */ ++#define SIG_UART1_RECV _VECTOR(28) /* UART1_RXC */ ++#define SIG_UART1_DATA _VECTOR(29) /* UART1_DRE */ ++#define SIG_UART1_TRANS _VECTOR(30) /* UART1_TXC */ ++#define SIG_FPGA_INTERRUPT12 _VECTOR(31) /* FPGA_INT12 */ ++#define SIG_FPGA_INTERRUPT13 _VECTOR(32) /* FPGA_INT13 */ ++#define SIG_FPGA_INTERRUPT14 _VECTOR(33) /* FPGA_INT14 */ ++#define SIG_FPGA_INTERRUPT15 _VECTOR(34) /* FPGA_INT15 */ ++#define SIG_2WIRE_SERIAL _VECTOR(35) /* TWS_INT */ ++ ++#define _VECTORS_SIZE 144 ++ ++/* Bit numbers (SFRs alphabetically sorted) */ ++ ++/* ASSR */ ++#define AS2 3 ++#define TCN2UB 2 ++#define OCR2UB 1 ++#define TCR2UB 0 ++ ++/* DDRD */ ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++/* DDRE */ ++#define DDE7 7 ++#define DDE6 6 ++#define DDE5 5 ++#define DDE4 4 ++#define DDE3 3 ++#define DDE2 2 ++#define DDE1 1 ++#define DDE0 0 ++ ++/* EIMF */ ++#define INTF3 7 ++#define INTF2 6 ++#define INTF1 5 ++#define INTF0 4 ++#define INT3 3 ++#define INT2 2 ++#define INT1 1 ++#define INT0 0 ++ ++/* FISCR */ ++#define FIADR 7 ++#define XFIS1 1 ++#define XFIS0 0 ++ ++/* FISUA */ ++#define FIF3 7 ++#define FIF2 6 ++#define FIF1 5 ++#define FIF0 4 ++#define FINT3 3 ++#define FINT2 2 ++#define FINT1 1 ++#define FINT0 0 ++ ++/* FISUB */ ++#define FIF7 7 ++#define FIF6 6 ++#define FIF5 5 ++#define FIF4 4 ++#define FINT7 3 ++#define FINT6 2 ++#define FINT5 1 ++#define FINT4 0 ++ ++/* FISUC */ ++#define FIF11 7 ++#define FIF10 6 ++#define FIF9 5 ++#define FIF8 4 ++#define FINT11 3 ++#define FINT10 2 ++#define FINT9 1 ++#define FINT8 0 ++ ++/* FISUD */ ++#define FIF15 7 ++#define FIF14 6 ++#define FIF13 5 ++#define FIF12 4 ++#define FINT15 3 ++#define FINT14 2 ++#define FINT13 1 ++#define FINT12 0 ++ ++/* MCUR */ ++#define JTRF 7 ++#define JTD 6 ++#define SE 5 ++#define SM1 4 ++#define SM0 3 ++#define PORF 2 ++#define WDRF 1 ++#define EXTRF 0 ++ ++/* OCDR (reserved) */ ++#define IDRD 7 ++ ++/* PIND */ ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++/* PINE */ ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++/* PORTD */ ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* PORTE */ ++/* ++ PE7 = IC1 / INT3 (alternate) ++ PE6 = OC1A / INT2 (alternate) ++ PE5 = OC1B / INT1 (alternate) ++ PE4 = ET11 / INT0 (alternate) ++ PE3 = OC2 / RX1 (alternate) ++ PE2 = / TX1 (alternate) ++ PE1 = OC0 / RX0 (alternate) ++ PE0 = ET0 / TX0 (alternate) ++ */ ++#define PE7 7 ++#define PE6 6 ++#define PE5 5 ++#define PE4 4 ++#define PE3 3 ++#define PE2 2 ++#define PE1 1 ++#define PE0 0 ++ ++/* SFIOR */ ++#define PSR2 1 ++#define PSR10 0 ++ ++/* SFTCR */ ++#define FMXOR 3 ++#define WDTS 2 ++#define DBG 1 ++#define SRST 0 ++ ++/* TCCR0 */ ++#define FOC0 7 ++#define PWM0 6 ++#define COM01 5 ++#define COM00 4 ++#define CTC0 3 ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* TCCR1A */ ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define FOC1A 3 ++#define FOC1B 2 ++#define PWM11 1 ++#define PWM10 0 ++ ++/* TCCR1B */ ++#define ICNC1 7 ++#define ICES1 6 ++#define ICPE 5 ++#define CTC1 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* TCCR2 */ ++#define FOC2 7 ++#define PWM2 6 ++#define COM21 5 ++#define COM20 4 ++#define CTC2 3 ++#define CS22 2 ++#define CS21 1 ++#define CS20 0 ++ ++/* TIFR */ ++#define TOV1 7 ++#define OCF1A 6 ++#define OCF1B 5 ++#define TOV2 4 ++#define ICF1 3 ++#define OCF2 2 ++#define TOV0 1 ++#define OCF0 0 ++ ++/* TIMSK */ ++#define TOIE1 7 ++#define OCIE1A 6 ++#define OCIE1B 5 ++#define TOIE2 4 ++#define TICIE1 3 ++#define OCIE2 2 ++#define TOIE0 1 ++#define OCIE0 0 ++ ++/* TWAR */ ++/* #define TWA 1 */ /* TWA is bits 7:1 */ ++#define TWGCE 0 ++ ++/* TWCR */ ++#define TWINT 7 ++#define TWEA 6 ++#define TWSTA 5 ++#define TWSTO 4 ++#define TWWC 3 ++#define TWEN 2 ++#define TWIE 0 ++ ++/* TWSR */ ++#define TWS7 7 ++#define TWS6 6 ++#define TWS5 5 ++#define TWS4 4 ++#define TWS3 3 ++ ++/* UBRRHI ++ Bits 11..8 of UART1 are bits 7..4 of UBRRHI. ++ Bits 11..8 of UART0 are bits 3..0 of UBRRHI. */ ++/* #define UBRRHI1 4 */ ++/* #define UBRRHI0 0 */ ++ ++/* UCSR0A */ ++#define RXC0 7 ++#define TXC0 6 ++#define UDRE0 5 ++#define FE0 4 ++#define OR0 3 ++#define U2X0 1 ++#define MPCM0 0 ++ ++/* UCSR0B */ ++#define RXCIE0 7 ++#define TXCIE0 6 ++#define UDRIE0 5 ++#define RXEN0 4 ++#define TXEN0 3 ++#define CHR90 2 ++#define RXB80 1 ++#define TXB80 0 ++ ++/* UCSR1A */ ++#define RXC1 7 ++#define TXC1 6 ++#define UDRE1 5 ++#define FE1 4 ++#define OR1 3 ++#define U2X1 1 ++#define MPCM1 0 ++ ++/* UCSR1B */ ++#define RXCIE1 7 ++#define TXCIE1 6 ++#define UDRIE1 5 ++#define RXEN1 4 ++#define TXEN1 3 ++#define CHR91 2 ++#define RXB81 1 ++#define TXB81 0 ++ ++/* WDTCR */ ++#define WDTOE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* ++ Last memory addresses - depending on configuration, it is possible ++ to have 20K-32K of program memory and 4K-16K of data memory ++ (all in the same 36K total of SRAM, loaded from external EEPROM). ++ */ ++ ++#ifndef RAMSTART ++#define RAMSTART 0x60 ++#endif ++ ++#ifndef RAMEND ++#define RAMEND 0x0FFF ++#endif ++ ++#ifndef XRAMEND ++#define XRAMEND RAMEND ++#endif ++ ++#define E2END 0 ++ ++#ifndef FLASHEND ++#define FLASHEND 0x7FFF ++#endif ++ ++#endif /* _AVR_IOAT94K_H_ */ +diff --git a/include/avr/iocan128.h b/include/avr/iocan128.h +index c2c1268..dd5405a 100644 +--- a/include/avr/iocan128.h ++++ b/include/avr/iocan128.h +@@ -1,94 +1,95 @@ +-/* Copyright (c) 2004,2005, Colin O'Flynn +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iocan128.h 1767 2008-10-17 23:27:53Z arcanum $ */ +- +-/* iocan128.h - definitions for CAN128 */ +- +-#ifndef _AVR_IOCAN128_H_ +-#define _AVR_IOCAN128_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 256 +-#define RAMEND 0x10FF /* Last On-Chip SRAM Location */ +-#define XRAMEND 0xFFFF +-#define E2END 0x0FFF +-#define E2PAGESIZE 8 +-#define FLASHEND 0x1FFFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x97 +-#define SIGNATURE_2 0x81 +- +- +-#endif /* _AVR_IOCAN128_H_ */ ++/* Copyright (c) 2004,2005, Colin O'Flynn ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iocan128.h 1767 2008-10-17 23:27:53Z arcanum $ */ ++ ++/* iocan128.h - definitions for CAN128 */ ++ ++#ifndef _AVR_IOCAN128_H_ ++#define _AVR_IOCAN128_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 256 ++#define RAMSTART 0x100 ++#define RAMEND 0x10FF /* Last On-Chip SRAM Location */ ++#define XRAMEND 0xFFFF ++#define E2END 0x0FFF ++#define E2PAGESIZE 8 ++#define FLASHEND 0x1FFFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x97 ++#define SIGNATURE_2 0x81 ++ ++ ++#endif /* _AVR_IOCAN128_H_ */ +diff --git a/include/avr/iocan32.h b/include/avr/iocan32.h +index 9cfa375..adce6ad 100644 +--- a/include/avr/iocan32.h ++++ b/include/avr/iocan32.h +@@ -1,94 +1,95 @@ +-/* Copyright (c) 2004,2005, Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iocan32.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ +- +-/* iocan32.h - definitions for CAN32 */ +- +-#ifndef _AVR_IOCAN32_H_ +-#define _AVR_IOCAN32_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 256 +-#define RAMEND 0x08FF /* Last On-Chip SRAM Location */ +-#define XRAMEND 0xFFFF +-#define E2END 0x03FF +-#define E2PAGESIZE 8 +-#define FLASHEND 0x7FFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x95 +-#define SIGNATURE_2 0x81 +- +- +-#endif /* _AVR_IOCAN32_H_ */ ++/* Copyright (c) 2004,2005, Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iocan32.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ ++ ++/* iocan32.h - definitions for CAN32 */ ++ ++#ifndef _AVR_IOCAN32_H_ ++#define _AVR_IOCAN32_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 256 ++#define RAMSTART 0x100 ++#define RAMEND 0x08FF /* Last On-Chip SRAM Location */ ++#define XRAMEND 0xFFFF ++#define E2END 0x03FF ++#define E2PAGESIZE 8 ++#define FLASHEND 0x7FFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x81 ++ ++ ++#endif /* _AVR_IOCAN32_H_ */ +diff --git a/include/avr/iocan64.h b/include/avr/iocan64.h +index ccc45ee..856539a 100644 +--- a/include/avr/iocan64.h ++++ b/include/avr/iocan64.h +@@ -1,94 +1,95 @@ +-/* Copyright (c) 2004,2005, Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iocan64.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ +- +-/* iocan64.h - definitions for CAN64 */ +- +-#ifndef _AVR_IOCAN64_H_ +-#define _AVR_IOCAN64_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 256 +-#define RAMEND 0x10FF /* Last On-Chip SRAM Location */ +-#define XRAMEND 0xFFFF +-#define E2END 0x07FF +-#define E2PAGESIZE 8 +-#define FLASHEND 0xFFFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x96 +-#define SIGNATURE_2 0x81 +- +- +-#endif /* _AVR_IOCAN64_H_ */ ++/* Copyright (c) 2004,2005, Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iocan64.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ ++ ++/* iocan64.h - definitions for CAN64 */ ++ ++#ifndef _AVR_IOCAN64_H_ ++#define _AVR_IOCAN64_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 256 ++#define RAMSTART 0x100 ++#define RAMEND 0x10FF /* Last On-Chip SRAM Location */ ++#define XRAMEND 0xFFFF ++#define E2END 0x07FF ++#define E2PAGESIZE 8 ++#define FLASHEND 0xFFFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x81 ++ ++ ++#endif /* _AVR_IOCAN64_H_ */ +diff --git a/include/avr/iocanxx.h b/include/avr/iocanxx.h +index fe5c15a..cb58e1b 100644 +--- a/include/avr/iocanxx.h ++++ b/include/avr/iocanxx.h +@@ -1,2020 +1,2020 @@ +-/* Copyright (c) 2004,2005,2006 Colin O'Flynn +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iocanxx.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* This file is based largely on: +- - iom128.h by Peter Jansen (bit defines) +- - iom169.h by Juergen Schilling +- (register addresses) +- - AT90CAN128 Datasheet (bit defines and register addresses) +- - Appnote on Mega128 --> AT90Can128 Conversion (for what registers I need +- to change) */ +- +-/* iocanxx.h - definitions for AT90CAN32, AT90CAN64 and AT90CAN128 */ +- +-#ifndef _AVR_IOCANXX_H_ +-#define _AVR_IOCANXX_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iocanxx.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers and bit definitions. */ +- +-/* RegDef: Port A */ +-#define PINA _SFR_IO8(0x00) +-#define DDRA _SFR_IO8(0x01) +-#define PORTA _SFR_IO8(0x02) +- +-/* RegDef: Port B */ +-#define PINB _SFR_IO8(0x03) +-#define DDRB _SFR_IO8(0x04) +-#define PORTB _SFR_IO8(0x05) +- +-/* RegDef: Port C */ +-#define PINC _SFR_IO8(0x06) +-#define DDRC _SFR_IO8(0x07) +-#define PORTC _SFR_IO8(0x08) +- +-/* RegDef: Port D */ +-#define PIND _SFR_IO8(0x09) +-#define DDRD _SFR_IO8(0x0A) +-#define PORTD _SFR_IO8(0x0B) +- +-/* RegDef: Port E */ +-#define PINE _SFR_IO8(0x0C) +-#define DDRE _SFR_IO8(0x0D) +-#define PORTE _SFR_IO8(0x0E) +- +-/* RegDef: Port F */ +-#define PINF _SFR_IO8(0x0F) +-#define DDRF _SFR_IO8(0x10) +-#define PORTF _SFR_IO8(0x11) +- +-/* RegDef: Port G */ +-#define PING _SFR_IO8(0x12) +-#define DDRG _SFR_IO8(0x13) +-#define PORTG _SFR_IO8(0x14) +- +-/* RegDef: Timer/Counter 0 interrupt Flag Register */ +-#define TIFR0 _SFR_IO8(0x15) +- +-/* RegDef: Timer/Counter 1 interrupt Flag Register */ +-#define TIFR1 _SFR_IO8(0x16) +- +-/* RegDef: Timer/Counter 2 interrupt Flag Register */ +-#define TIFR2 _SFR_IO8(0x17) +- +-/* RegDef: Timer/Counter 3 interrupt Flag Register */ +-#define TIFR3 _SFR_IO8(0x18) +- +-/* RegDef: External Interrupt Flag Register */ +-#define EIFR _SFR_IO8(0x1C) +- +-/* RegDef: External Interrupt Mask Register */ +-#define EIMSK _SFR_IO8(0x1D) +- +-/* RegDef: General Purpose I/O Register 0 */ +-#define GPIOR0 _SFR_IO8(0x1E) +- +-/* RegDef: EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1F) +- +-/* RegDef: EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x20) +- +-/* RegDef: EEPROM Address Register */ +-#define EEAR _SFR_IO16(0x21) +-#define EEARL _SFR_IO8(0x21) +-#define EEARH _SFR_IO8(0x22) +- +-/* 6-char sequence denoting where to find the EEPROM registers in memory space. +- Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM +- subroutines. +- First two letters: EECR address. +- Second two letters: EEDR address. +- Last two letters: EEAR address. */ +-#define __EEPROM_REG_LOCATIONS__ 1F2021 +- +-/* RegDef: General Timer/Counter Control Register */ +-#define GTCCR _SFR_IO8(0x23) +- +-/* RegDef: Timer/Counter Control Register A */ +-#define TCCR0A _SFR_IO8(0x24) +- +-/* RegDef: Timer/Counter Register */ +-#define TCNT0 _SFR_IO8(0x26) +- +-/* RegDef: Output Compare Register A */ +-#define OCR0A _SFR_IO8(0x27) +- +-/* RegDef: General Purpose I/O Register 1 */ +-#define GPIOR1 _SFR_IO8(0x2A) +- +-/* RegDef: General Purpose I/O Register 2 */ +-#define GPIOR2 _SFR_IO8(0x2B) +- +-/* RegDef: SPI Control Register */ +-#define SPCR _SFR_IO8(0x2C) +- +-/* RegDef: SPI Status Register */ +-#define SPSR _SFR_IO8(0x2D) +- +-/* RegDef: SPI Data Register */ +-#define SPDR _SFR_IO8(0x2E) +- +-/* RegDef: Analog Comperator Control and Status Register */ +-#define ACSR _SFR_IO8(0x30) +- +-/* RegDef: On-chip Debug Register */ +-#define OCDR _SFR_IO8(0x31) +- +-/* RegDef: Sleep Mode Control Register */ +-#define SMCR _SFR_IO8(0x33) +- +-/* RegDef: MCU Status Register */ +-#define MCUSR _SFR_IO8(0x34) +- +-/* RegDef: MCU Control Rgeister */ +-#define MCUCR _SFR_IO8(0x35) +- +-/* RegDef: Store Program Memory Control and Status Register */ +-#define SPMCSR _SFR_IO8(0x37) +- +-/* RegDef: RAMPZ register. */ +-#define RAMPZ _SFR_IO8(0x3B) +- +-/* RegDef: Watchdog Timer Control Register */ +-#define WDTCR _SFR_MEM8(0x60) +- +-/* RegDef: Clock Prescale Register */ +-#define CLKPR _SFR_MEM8(0x61) +- +-/* RegDef: Oscillator Calibration Register */ +-#define OSCCAL _SFR_MEM8(0x66) +- +-/* RegDef: External Interrupt Control Register A */ +-#define EICRA _SFR_MEM8(0x69) +- +-/* RegDef: External Interrupt Control Register B */ +-#define EICRB _SFR_MEM8(0x6A) +- +-/* RegDef: Timer/Counter 0 Interrupt Mask Register */ +-#define TIMSK0 _SFR_MEM8(0x6E) +- +-/* RegDef: Timer/Counter 1 Interrupt Mask Register */ +-#define TIMSK1 _SFR_MEM8(0x6F) +- +-/* RegDef: Timer/Counter 2 Interrupt Mask Register */ +-#define TIMSK2 _SFR_MEM8(0x70) +- +-/* RegDef: Timer/Counter 3 Interrupt Mask Register */ +-#define TIMSK3 _SFR_MEM8(0x71) +- +-/* RegDef: External Memory Control Register A */ +-#define XMCRA _SFR_MEM8(0x74) +- +-/* RegDef: External Memory Control Register A */ +-#define XMCRB _SFR_MEM8(0x75) +- +-/* RegDef: ADC Data Register */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +-#define ADCL _SFR_MEM8(0x78) +-#define ADCH _SFR_MEM8(0x79) +- +-/* RegDef: ADC Control and Status Register A */ +-#define ADCSRA _SFR_MEM8(0x7A) +- +-/* RegDef: ADC Control and Status Register B */ +-#define ADCSRB _SFR_MEM8(0x7B) +- +-/* RegDef: ADC Multiplex Selection Register */ +-#define ADMUX _SFR_MEM8(0x7C) +- +-/* RegDef: Digital Input Disable Register 0 */ +-#define DIDR0 _SFR_MEM8(0x7E) +- +-/* RegDef: Digital Input Disable Register 1 */ +-#define DIDR1 _SFR_MEM8(0x7F) +- +-/* RegDef: Timer/Counter1 Control Register A */ +-#define TCCR1A _SFR_MEM8(0x80) +- +-/* RegDef: Timer/Counter1 Control Register B */ +-#define TCCR1B _SFR_MEM8(0x81) +- +-/* RegDef: Timer/Counter1 Control Register C */ +-#define TCCR1C _SFR_MEM8(0x82) +- +-/* RegDef: Timer/Counter1 Register */ +-#define TCNT1 _SFR_MEM16(0x84) +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1H _SFR_MEM8(0x85) +- +-/* RegDef: Timer/Counter1 Input Capture Register */ +-#define ICR1 _SFR_MEM16(0x86) +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1H _SFR_MEM8(0x87) +- +-/* RegDef: Timer/Counter1 Output Compare Register A */ +-#define OCR1A _SFR_MEM16(0x88) +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AH _SFR_MEM8(0x89) +- +-/* RegDef: Timer/Counter1 Output Compare Register B */ +-#define OCR1B _SFR_MEM16(0x8A) +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BH _SFR_MEM8(0x8B) +- +-/* RegDef: Timer/Counter1 Output Compare Register C */ +-#define OCR1C _SFR_MEM16(0x8C) +-#define OCR1CL _SFR_MEM8(0x8C) +-#define OCR1CH _SFR_MEM8(0x8D) +- +-/* RegDef: Timer/Counter3 Control Register A */ +-#define TCCR3A _SFR_MEM8(0x90) +- +-/* RegDef: Timer/Counter3 Control Register B */ +-#define TCCR3B _SFR_MEM8(0x91) +- +-/* RegDef: Timer/Counter3 Control Register C */ +-#define TCCR3C _SFR_MEM8(0x92) +- +-/* RegDef: Timer/Counter3 Register */ +-#define TCNT3 _SFR_MEM16(0x94) +-#define TCNT3L _SFR_MEM8(0x94) +-#define TCNT3H _SFR_MEM8(0x95) +- +-/* RegDef: Timer/Counter3 Input Capture Register */ +-#define ICR3 _SFR_MEM16(0x96) +-#define ICR3L _SFR_MEM8(0x96) +-#define ICR3H _SFR_MEM8(0x97) +- +-/* RegDef: Timer/Counter3 Output Compare Register A */ +-#define OCR3A _SFR_MEM16(0x98) +-#define OCR3AL _SFR_MEM8(0x98) +-#define OCR3AH _SFR_MEM8(0x99) +- +-/* RegDef: Timer/Counter3 Output Compare Register B */ +-#define OCR3B _SFR_MEM16(0x9A) +-#define OCR3BL _SFR_MEM8(0x9A) +-#define OCR3BH _SFR_MEM8(0x9B) +- +-/* RegDef: Timer/Counter3 Output Compare Register C */ +-#define OCR3C _SFR_MEM16(0x9C) +-#define OCR3CL _SFR_MEM8(0x9C) +-#define OCR3CH _SFR_MEM8(0x9D) +- +-/* RegDef: Timer/Counter2 Control Register A */ +-#define TCCR2A _SFR_MEM8(0xB0) +- +-/* RegDef: Timer/Counter2 Register */ +-#define TCNT2 _SFR_MEM8(0xB2) +- +-/* RegDef: Timer/Counter2 Output Compare Register */ +-#define OCR2A _SFR_MEM8(0xB3) +- +-/* RegDef: Asynchronous Status Register */ +-#define ASSR _SFR_MEM8(0xB6) +- +-/* RegDef: TWI Bit Rate Register */ +-#define TWBR _SFR_MEM8(0xB8) +- +-/* RegDef: TWI Status Register */ +-#define TWSR _SFR_MEM8(0xB9) +- +-/* RegDef: TWI (Slave) Address Register */ +-#define TWAR _SFR_MEM8(0xBA) +- +-/* RegDef: TWI Data Register */ +-#define TWDR _SFR_MEM8(0xBB) +- +-/* RegDef: TWI Control Register */ +-#define TWCR _SFR_MEM8(0xBC) +- +-/* RegDef: USART0 Control and Status Register A */ +-#define UCSR0A _SFR_MEM8(0xC0) +- +-/* RegDef: USART0 Control and Status Register B */ +-#define UCSR0B _SFR_MEM8(0xC1) +- +-/* RegDef: USART0 Control and Status Register C */ +-#define UCSR0C _SFR_MEM8(0xC2) +- +-/* RegDef: USART0 Baud Rate Register */ +-#define UBRR0 _SFR_MEM16(0xC4) +-#define UBRR0L _SFR_MEM8(0xC4) +-#define UBRR0H _SFR_MEM8(0xC5) +- +-/* RegDef: USART0 I/O Data Register */ +-#define UDR0 _SFR_MEM8(0xC6) +- +-/* RegDef: USART1 Control and Status Register A */ +-#define UCSR1A _SFR_MEM8(0xC8) +- +-/* RegDef: USART1 Control and Status Register B */ +-#define UCSR1B _SFR_MEM8(0xC9) +- +-/* RegDef: USART1 Control and Status Register C */ +-#define UCSR1C _SFR_MEM8(0xCA) +- +-/* RegDef: USART1 Baud Rate Register */ +-#define UBRR1 _SFR_MEM16(0xCC) +-#define UBRR1L _SFR_MEM8(0xCC) +-#define UBRR1H _SFR_MEM8(0xCD) +- +-/* RegDef: USART1 I/O Data Register */ +-#define UDR1 _SFR_MEM8(0xCE) +- +-/* RegDef: CAN General Control Register*/ +-#define CANGCON _SFR_MEM8(0xD8) +- +-/* RegDef: CAN General Status Register*/ +-#define CANGSTA _SFR_MEM8(0xD9) +- +-/* RegDef: CAN General Interrupt Register*/ +-#define CANGIT _SFR_MEM8(0xDA) +- +-/* RegDef: CAN General Interrupt Enable Register*/ +-#define CANGIE _SFR_MEM8(0xDB) +- +-/* Word Definition: CAN Enable MOb Register*/ +-#define CANEN _SFR_MEM16(0xDC) +- +-/* RegDef: CAN Enable MOb Register*/ +-#define CANEN2 _SFR_MEM8(0xDC) +- +-/* RegDef: CAN Enable MOb Register*/ +-#define CANEN1 _SFR_MEM8(0xDD) +- +-/* Word Definition: CAN Enable Interrupt MOb Register*/ +-#define CANIE _SFR_MEM16(0xDE) +- +-/* RegDef: CAN Enable Interrupt MOb Register*/ +-#define CANIE2 _SFR_MEM8(0xDE) +- +-/* RegDef: CAN Enable Interrupt MOb Register*/ +-#define CANIE1 _SFR_MEM8(0xDF) +- +-/* RegDef: CAN Status Interrupt MOb Register*/ +-/* +- * WARNING: Do not apply the SIT8...SIT14 constants to bits in the CANSIT +- * register. +- */ +-#define CANSIT _SFR_MEM16(0xE0) +-#define CANSIT2 _SFR_MEM8(0xE0) +-#define CANSIT1 _SFR_MEM8(0xE1) +- +-/* RegDef: CAN Bit Timing Register 1*/ +-#define CANBT1 _SFR_MEM8(0xE2) +- +-/* RegDef: CAN Bit Timing Register 2*/ +-#define CANBT2 _SFR_MEM8(0xE3) +- +-/* RegDef: CAN Bit Timing Register 3*/ +-#define CANBT3 _SFR_MEM8(0xE4) +- +-/* RegDef: CAN Timer Control Register*/ +-#define CANTCON _SFR_MEM8(0xE5) +- +-/* RegDef: CAN Timer Register*/ +-#define CANTIM _SFR_MEM16(0xE6) +-#define CANTIML _SFR_MEM8(0xE6) +-#define CANTIMH _SFR_MEM8(0xE7) +- +-/* RegDef: CAN TTC Timer Register*/ +-#define CANTTC _SFR_MEM16(0xE8) +-#define CANTTCL _SFR_MEM8(0xE8) +-#define CANTTCH _SFR_MEM8(0xE9) +- +-/* RegDef: CAN Transmitt Error Counter Register*/ +-#define CANTEC _SFR_MEM8(0xEA) +- +-/* RegDef: CAN Receive Error Counter Register*/ +-#define CANREC _SFR_MEM8(0xEB) +- +-/* RegDef: CAN Highest Priority MOb Register*/ +-#define CANHPMOB _SFR_MEM8(0xEC) +- +-/* RegDef: CAN Page MOb Register*/ +-#define CANPAGE _SFR_MEM8(0xED) +- +-/* RegDef: CAN MOb Status Register*/ +-#define CANSTMOB _SFR_MEM8(0xEE) +- +-/* RegDef: CAN MOb Control and DLC Register*/ +-#define CANCDMOB _SFR_MEM8(0xEF) +- +-/* RegDef: CAN Identifier Tag Registers*/ +-#define CANIDT _SFR_MEM32(0xF0) +- +-#define CANIDT4 _SFR_MEM8(0xF0) +-#define CANIDT3 _SFR_MEM8(0xF1) +-#define CANIDT2 _SFR_MEM8(0xF2) +-#define CANIDT1 _SFR_MEM8(0xF3) +- +-/* RegDef: CAN Identifier Mask Registers */ +-#define CANIDM _SFR_MEM32(0xF4) +- +-#define CANIDM4 _SFR_MEM8(0xF4) +-#define CANIDM3 _SFR_MEM8(0xF5) +-#define CANIDM2 _SFR_MEM8(0xF6) +-#define CANIDM1 _SFR_MEM8(0xF7) +- +-/* RegDef: CAN TTC Timer Register*/ +-#define CANSTM _SFR_MEM16(0xF8) +-#define CANSTML _SFR_MEM8(0xF8) +-#define CANSTMH _SFR_MEM8(0xF9) +- +-/* RegDef: CAN Message Register*/ +-#define CANMSG _SFR_MEM8(0xFA) +- +-/* Interrupt vectors */ +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt Request 1 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +-#define SIG_INTERRUPT1 _VECTOR(2) +- +-/* External Interrupt Request 2 */ +-#define INT2_vect_num 3 +-#define INT2_vect _VECTOR(3) +-#define SIG_INTERRUPT2 _VECTOR(3) +- +-/* External Interrupt Request 3 */ +-#define INT3_vect_num 4 +-#define INT3_vect _VECTOR(4) +-#define SIG_INTERRUPT3 _VECTOR(4) +- +-/* External Interrupt Request 4 */ +-#define INT4_vect_num 5 +-#define INT4_vect _VECTOR(5) +-#define SIG_INTERRUPT4 _VECTOR(5) +- +-/* External Interrupt Request 5 */ +-#define INT5_vect_num 6 +-#define INT5_vect _VECTOR(6) +-#define SIG_INTERRUPT5 _VECTOR(6) +- +-/* External Interrupt Request 6 */ +-#define INT6_vect_num 7 +-#define INT6_vect _VECTOR(7) +-#define SIG_INTERRUPT6 _VECTOR(7) +- +-/* External Interrupt Request 7 */ +-#define INT7_vect_num 8 +-#define INT7_vect _VECTOR(8) +-#define SIG_INTERRUPT7 _VECTOR(8) +- +-/* Timer/Counter2 Compare Match */ +-#define TIMER2_COMP_vect_num 9 +-#define TIMER2_COMP_vect _VECTOR(9) +-#define SIG_OUTPUT_COMPARE2 _VECTOR(9) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 10 +-#define TIMER2_OVF_vect _VECTOR(10) +-#define SIG_OVERFLOW2 _VECTOR(10) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 11 +-#define TIMER1_CAPT_vect _VECTOR(11) +-#define SIG_INPUT_CAPTURE1 _VECTOR(11) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 12 +-#define TIMER1_COMPA_vect _VECTOR(12) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(12) +- +-/* Timer/Counter Compare Match B */ +-#define TIMER1_COMPB_vect_num 13 +-#define TIMER1_COMPB_vect _VECTOR(13) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(13) +- +-/* Timer/Counter1 Compare Match C */ +-#define TIMER1_COMPC_vect_num 14 +-#define TIMER1_COMPC_vect _VECTOR(14) +-#define SIG_OUTPUT_COMPARE1C _VECTOR(14) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 15 +-#define TIMER1_OVF_vect _VECTOR(15) +-#define SIG_OVERFLOW1 _VECTOR(15) +- +-/* Timer/Counter0 Compare Match */ +-#define TIMER0_COMP_vect_num 16 +-#define TIMER0_COMP_vect _VECTOR(16) +-#define SIG_OUTPUT_COMPARE0 _VECTOR(16) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 17 +-#define TIMER0_OVF_vect _VECTOR(17) +-#define SIG_OVERFLOW0 _VECTOR(17) +- +-/* CAN Transfer Complete or Error */ +-#define CANIT_vect_num 18 +-#define CANIT_vect _VECTOR(18) +-#define SIG_CAN_INTERRUPT1 _VECTOR(18) +- +-/* CAN Timer Overrun */ +-#define OVRIT_vect_num 19 +-#define OVRIT_vect _VECTOR(19) +-#define SIG_CAN_OVERFLOW1 _VECTOR(19) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 20 +-#define SPI_STC_vect _VECTOR(20) +-#define SIG_SPI _VECTOR(20) +- +-/* USART0, Rx Complete */ +-#define USART0_RX_vect_num 21 +-#define USART0_RX_vect _VECTOR(21) +-#define SIG_UART0_RECV _VECTOR(21) +-#define SIG_USART0_RECV _VECTOR(21) +- +-/* USART0 Data Register Empty */ +-#define USART0_UDRE_vect_num 22 +-#define USART0_UDRE_vect _VECTOR(22) +-#define SIG_UART0_DATA _VECTOR(22) +-#define SIG_USART0_DATA _VECTOR(22) +- +-/* USART0, Tx Complete */ +-#define USART0_TX_vect_num 23 +-#define USART0_TX_vect _VECTOR(23) +-#define SIG_UART0_TRANS _VECTOR(23) +-#define SIG_USART0_TRANS _VECTOR(23) +- +-/* Analog Comparator */ +-#define ANALOG_COMP_vect_num 24 +-#define ANALOG_COMP_vect _VECTOR(24) +-#define SIG_COMPARATOR _VECTOR(24) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 25 +-#define ADC_vect _VECTOR(25) +-#define SIG_ADC _VECTOR(25) +- +-/* EEPROM Ready */ +-#define EE_READY_vect_num 26 +-#define EE_READY_vect _VECTOR(26) +-#define SIG_EEPROM_READY _VECTOR(26) +- +-/* Timer/Counter3 Capture Event */ +-#define TIMER3_CAPT_vect_num 27 +-#define TIMER3_CAPT_vect _VECTOR(27) +-#define SIG_INPUT_CAPTURE3 _VECTOR(27) +- +-/* Timer/Counter3 Compare Match A */ +-#define TIMER3_COMPA_vect_num 28 +-#define TIMER3_COMPA_vect _VECTOR(28) +-#define SIG_OUTPUT_COMPARE3A _VECTOR(28) +- +-/* Timer/Counter3 Compare Match B */ +-#define TIMER3_COMPB_vect_num 29 +-#define TIMER3_COMPB_vect _VECTOR(29) +-#define SIG_OUTPUT_COMPARE3B _VECTOR(29) +- +-/* Timer/Counter3 Compare Match C */ +-#define TIMER3_COMPC_vect_num 30 +-#define TIMER3_COMPC_vect _VECTOR(30) +-#define SIG_OUTPUT_COMPARE3C _VECTOR(30) +- +-/* Timer/Counter3 Overflow */ +-#define TIMER3_OVF_vect_num 31 +-#define TIMER3_OVF_vect _VECTOR(31) +-#define SIG_OVERFLOW3 _VECTOR(31) +- +-/* USART1, Rx Complete */ +-#define USART1_RX_vect_num 32 +-#define USART1_RX_vect _VECTOR(32) +-#define SIG_UART1_RECV _VECTOR(32) +-#define SIG_USART1_RECV _VECTOR(32) +- +-/* USART1, Data Register Empty */ +-#define USART1_UDRE_vect_num 33 +-#define USART1_UDRE_vect _VECTOR(33) +-#define SIG_UART1_DATA _VECTOR(33) +-#define SIG_USART1_DATA _VECTOR(33) +- +-/* USART1, Tx Complete */ +-#define USART1_TX_vect_num 34 +-#define USART1_TX_vect _VECTOR(34) +-#define SIG_UART1_TRANS _VECTOR(34) +-#define SIG_USART1_TRANS _VECTOR(34) +- +-/* 2-wire Serial Interface */ +-#define TWI_vect_num 35 +-#define TWI_vect _VECTOR(35) +-#define SIG_2WIRE_SERIAL _VECTOR(35) +- +-/* Store Program Memory Read */ +-#define SPM_READY_vect_num 36 +-#define SPM_READY_vect _VECTOR(36) +-#define SIG_SPM_READY _VECTOR(36) +- +-#define _VECTORS_SIZE 148 +- +-/* The Register Bit names are represented by their bit number (0-7). */ +- +-/* Register Bits [ASSR] */ +-/* Asynchronous Status Register */ +-#define EXCLK 4 +-#define AS2 3 +-#define TCN2UB 2 +-#define OCR2UB 1 +-#define TCR2UB 0 +-/* End Register Bits */ +- +-/* Register Bits [TWCR] */ +-/* 2-wire Control Register - TWCR */ +-#define TWINT 7 +-#define TWEA 6 +-#define TWSTA 5 +-#define TWSTO 4 +-#define TWWC 3 +-#define TWEN 2 +-#define TWIE 0 +-/* End Register Bits */ +- +-/* Register Bits [TWAR] */ +-/* 2-wire Address Register - TWAR */ +-#define TWA6 7 +-#define TWA5 6 +-#define TWA4 5 +-#define TWA3 4 +-#define TWA2 3 +-#define TWA1 2 +-#define TWA0 1 +-#define TWGCE 0 +-/* End Register Bits */ +- +-/* Register Bits [TWSR] */ +-/* 2-wire Status Register - TWSR */ +-#define TWS7 7 +-#define TWS6 6 +-#define TWS5 5 +-#define TWS4 4 +-#define TWS3 3 +-#define TWPS1 1 +-#define TWPS0 0 +-/* End Register Bits */ +- +-/* Register Bits [XMCRB] */ +-/* External Memory Control Register B - XMCRB */ +-#define XMBK 7 +-#define XMM2 2 +-#define XMM1 1 +-#define XMM0 0 +-/* End Register Bits */ +- +-/* Register Bits [XMCRA] */ +-/* External Memory Control Register A - XMCRA */ +-#define SRE 7 +-#define SRL2 6 +-#define SRL1 5 +-#define SRL0 4 +-#define SRW11 3 +-#define SRW10 2 +-#define SRW01 1 +-#define SRW00 0 +-/* End Register Bits */ +- +-/* Register Bits [RAMPZ] */ +-/* RAM Page Z select register - RAMPZ */ +-#define RAMPZ0 0 +-/* End Register Bits */ +- +-/* Register Bits [EICRA] */ +-/* External Interrupt Control Register A - EICRA */ +-#define ISC31 7 +-#define ISC30 6 +-#define ISC21 5 +-#define ISC20 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +-/* End Register Bits */ +- +-/* Register Bits [EICRB] */ +-/* External Interrupt Control Register B - EICRB */ +-#define ISC71 7 +-#define ISC70 6 +-#define ISC61 5 +-#define ISC60 4 +-#define ISC51 3 +-#define ISC50 2 +-#define ISC41 1 +-#define ISC40 0 +-/* End Register Bits */ +- +-/* Register Bits [SPMCSR] */ +-/* Store Program Memory Control Register - SPMCSR, SPMCR */ +-#define SPMIE 7 +-#define RWWSB 6 +-#define RWWSRE 4 +-#define BLBSET 3 +-#define PGWRT 2 +-#define PGERS 1 +-#define SPMEN 0 +-/* End Register Bits */ +- +-/* Register Bits [EIMSK] */ +-/* External Interrupt MaSK register - EIMSK */ +-#define INT7 7 +-#define INT6 6 +-#define INT5 5 +-#define INT4 4 +-#define INT3 3 +-#define INT2 2 +-#define INT1 1 +-#define INT0 0 +-/* End Register Bits */ +- +-/* Register Bits [EIFR] */ +-/* External Interrupt Flag Register - EIFR */ +-#define INTF7 7 +-#define INTF6 6 +-#define INTF5 5 +-#define INTF4 4 +-#define INTF3 3 +-#define INTF2 2 +-#define INTF1 1 +-#define INTF0 0 +-/* End Register Bits */ +- +-/* Register Bits [TCCR2] */ +-/* Timer/Counter 2 Control Register - TCCR2 */ +-#define FOC2A 7 +-#define WGM20 6 +-#define COM2A1 5 +-#define COM2A0 4 +-#define WGM21 3 +-#define CS22 2 +-#define CS21 1 +-#define CS20 0 +-/* End Register Bits */ +- +-/* Register Bits [TCCR1A] */ +-/* Timer/Counter 1 Control and Status Register A - TCCR1A */ +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define COM1C1 3 +-#define COM1C0 2 +-#define WGM11 1 +-#define WGM10 0 +-/* End Register Bits */ +- +-/* Register Bits [TCCR3A] */ +-/* Timer/Counter 3 Control and Status Register A - TCCR3A */ +-#define COM3A1 7 +-#define COM3A0 6 +-#define COM3B1 5 +-#define COM3B0 4 +-#define COM3C1 3 +-#define COM3C0 2 +-#define WGM31 1 +-#define WGM30 0 +-/* End Register Bits */ +- +-/* Register Bits [TCCR1B] */ +-/* Timer/Counter 1 Control and Status Register B - TCCR1B */ +-#define ICNC1 7 +-#define ICES1 6 +-#define WGM13 4 +-#define WGM12 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +-/* End Register Bits */ +- +-/* Register Bits [TCCR3B] */ +-/* Timer/Counter 3 Control and Status Register B - TCCR3B */ +-#define ICNC3 7 +-#define ICES3 6 +-#define WGM33 4 +-#define WGM32 3 +-#define CS32 2 +-#define CS31 1 +-#define CS30 0 +-/* End Register Bits */ +- +-/* Register Bits [TCCR3C] */ +-/* Timer/Counter 3 Control Register C - TCCR3C */ +-#define FOC3A 7 +-#define FOC3B 6 +-#define FOC3C 5 +-/* End Register Bits */ +- +-/* Register Bits [TCCR1C] */ +-/* Timer/Counter 1 Control Register C - TCCR1C */ +-#define FOC1A 7 +-#define FOC1B 6 +-#define FOC1C 5 +-/* End Register Bits */ +- +-/* Register Bits [OCDR] */ +-/* On-chip Debug Register - OCDR */ +-#define IDRD 7 +-#define OCDR7 7 +-#define OCDR6 6 +-#define OCDR5 5 +-#define OCDR4 4 +-#define OCDR3 3 +-#define OCDR2 2 +-#define OCDR1 1 +-#define OCDR0 0 +-/* End Register Bits */ +- +-/* Register Bits [WDTCR] */ +-/* Watchdog Timer Control Register - WDTCR */ +-#define WDCE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +-/* End Register Bits */ +- +-/* Register Bits [SPSR] */ +-/* SPI Status Register - SPSR */ +-#define SPIF 7 +-#define WCOL 6 +-#define SPI2X 0 +-/* End Register Bits */ +- +-/* Register Bits [SPCR] */ +-/* SPI Control Register - SPCR */ +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +-/* End Register Bits */ +- +-/* Register Bits [UCSR1C] */ +-/* USART1 Register C - UCSR1C */ +-#define UMSEL1 6 +-#define UPM11 5 +-#define UPM10 4 +-#define USBS1 3 +-#define UCSZ11 2 +-#define UCSZ10 1 +-#define UCPOL1 0 +-/* End Register Bits */ +- +-/* Register Bits [UCSR0C] */ +-/* USART0 Register C - UCSR0C */ +-#define UMSEL0 6 +-#define UPM01 5 +-#define UPM00 4 +-#define USBS0 3 +-#define UCSZ01 2 +-#define UCSZ00 1 +-#define UCPOL0 0 +-/* End Register Bits */ +- +-/* Register Bits [UCSR1A] */ +-/* USART1 Status Register A - UCSR1A */ +-#define RXC1 7 +-#define TXC1 6 +-#define UDRE1 5 +-#define FE1 4 +-#define DOR1 3 +-#define UPE1 2 +-#define U2X1 1 +-#define MPCM1 0 +-/* End Register Bits */ +- +-/* Register Bits [UCSR0A] */ +-/* USART0 Status Register A - UCSR0A */ +-#define RXC0 7 +-#define TXC0 6 +-#define UDRE0 5 +-#define FE0 4 +-#define DOR0 3 +-#define UPE0 2 +-#define U2X0 1 +-#define MPCM0 0 +-/* End Register Bits */ +- +-/* Register Bits [UCSR1B] */ +-/* USART1 Control Register B - UCSR1B */ +-#define RXCIE1 7 +-#define TXCIE1 6 +-#define UDRIE1 5 +-#define RXEN1 4 +-#define TXEN1 3 +-#define UCSZ12 2 +-#define RXB81 1 +-#define TXB81 0 +-/* End Register Bits */ +- +-/* Register Bits [UCSR0B] */ +-/* USART0 Control Register B - UCSR0B */ +-#define RXCIE0 7 +-#define TXCIE0 6 +-#define UDRIE0 5 +-#define RXEN0 4 +-#define TXEN0 3 +-#define UCSZ02 2 +-#define RXB80 1 +-#define TXB80 0 +-/* End Register Bits */ +- +-/* Register Bits [ACSR] */ +-/* Analog Comparator Control and Status Register - ACSR */ +-#define ACD 7 +-#define ACBG 6 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +-/* End Register Bits */ +- +-/* Register Bits [ADCSRA] */ +-/* ADC Control and status register - ADCSRA */ +-#define ADEN 7 +-#define ADSC 6 +-#define ADATE 5 +-#define ADIF 4 +-#define ADIE 3 +-#define ADPS2 2 +-#define ADPS1 1 +-#define ADPS0 0 +-/* End Register Bits */ +- +-/* +- The ADHSM bit has been removed from all documentation, +- as being not needed at all since the comparator has proven +- to be fast enough even without feeding it more power. +-*/ +- +-/* Register Bits [ADCSRB] */ +-/* ADC Control and status register - ADCSRB */ +-#define ACME 6 +-#define ADTS2 2 +-#define ADTS1 1 +-#define ADTS0 0 +-/* End Register Bits */ +- +-/* Register Bits [ADMUX] */ +-/* ADC Multiplexer select - ADMUX */ +-#define REFS1 7 +-#define REFS0 6 +-#define ADLAR 5 +-#define MUX4 4 +-#define MUX3 3 +-#define MUX2 2 +-#define MUX1 1 +-#define MUX0 0 +-/* End Register Bits */ +- +-/* Register Bits [DIDR0] */ +-/* Digital Input Disable Register 0 */ +-#define ADC7D 7 +-#define ADC6D 6 +-#define ADC5D 5 +-#define ADC4D 4 +-#define ADC3D 3 +-#define ADC2D 2 +-#define ADC1D 1 +-#define ADC0D 0 +-/* End Register Bits */ +- +-/* Register Bits [DIDR1] */ +-/* Digital Input Disable Register 1 */ +-#define AIN1D 1 +-#define AIN0D 0 +-/* End Register Bits */ +- +-/* Register Bits [PORTA] */ +-/* Port A Data Register - PORTA */ +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +-/* End Register Bits */ +- +-/* Register Bits [DDRA] */ +-/* Port A Data Direction Register - DDRA */ +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +-/* End Register Bits */ +- +-/* Register Bits [PINA] */ +-/* Port A Input Pins - PINA */ +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +-/* End Register Bits */ +- +-/* Register Bits [PORTB] */ +-/* Port B Data Register - PORTB */ +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +-/* End Register Bits */ +- +-/* Register Bits [DDRB] */ +-/* Port B Data Direction Register - DDRB */ +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +-/* End Register Bits */ +- +-/* Register Bits [PINB] */ +-/* Port B Input Pins - PINB */ +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +-/* End Register Bits */ +- +-/* Register Bits [PORTC] */ +-/* Port C Data Register - PORTC */ +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +-/* End Register Bits */ +- +-/* Register Bits [DDRC] */ +-/* Port C Data Direction Register - DDRC */ +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +-/* End Register Bits */ +- +-/* Register Bits [PINC] */ +-/* Port C Input Pins - PINC */ +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +-/* End Register Bits */ +- +-/* Register Bits [PORTD] */ +-/* Port D Data Register - PORTD */ +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +-/* End Register Bits */ +- +-/* Register Bits [DDRD] */ +-/* Port D Data Direction Register - DDRD */ +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +-/* End Register Bits */ +- +-/* Register Bits [PIND] */ +-/* Port D Input Pins - PIND */ +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +-/* End Register Bits */ +- +-/* Register Bits [PORTE] */ +-/* Port E Data Register - PORTE */ +-#define PE7 7 +-#define PE6 6 +-#define PE5 5 +-#define PE4 4 +-#define PE3 3 +-#define PE2 2 +-#define PE1 1 +-#define PE0 0 +-/* End Register Bits */ +- +-/* Register Bits [DDRE] */ +-/* Port E Data Direction Register - DDRE */ +-#define DDE7 7 +-#define DDE6 6 +-#define DDE5 5 +-#define DDE4 4 +-#define DDE3 3 +-#define DDE2 2 +-#define DDE1 1 +-#define DDE0 0 +-/* End Register Bits */ +- +-/* Register Bits [PINE] */ +-/* Port E Input Pins - PINE */ +-#define PINE7 7 +-#define PINE6 6 +-#define PINE5 5 +-#define PINE4 4 +-#define PINE3 3 +-#define PINE2 2 +-#define PINE1 1 +-#define PINE0 0 +-/* End Register Bits */ +- +-/* Register Bits [PORTF] */ +-/* Port F Data Register - PORTF */ +-#define PF7 7 +-#define PF6 6 +-#define PF5 5 +-#define PF4 4 +-#define PF3 3 +-#define PF2 2 +-#define PF1 1 +-#define PF0 0 +-/* End Register Bits */ +- +-/* Register Bits [DDRF] */ +-/* Port F Data Direction Register - DDRF */ +-#define DDF7 7 +-#define DDF6 6 +-#define DDF5 5 +-#define DDF4 4 +-#define DDF3 3 +-#define DDF2 2 +-#define DDF1 1 +-#define DDF0 0 +-/* End Register Bits */ +- +-/* Register Bits [PINF] */ +-/* Port F Input Pins - PINF */ +-#define PINF7 7 +-#define PINF6 6 +-#define PINF5 5 +-#define PINF4 4 +-#define PINF3 3 +-#define PINF2 2 +-#define PINF1 1 +-#define PINF0 0 +-/* End Register Bits */ +- +-/* Register Bits [PORTG] */ +-/* Port G Data Register - PORTG */ +-#define PG4 4 +-#define PG3 3 +-#define PG2 2 +-#define PG1 1 +-#define PG0 0 +-/* End Register Bits */ +- +-/* Register Bits [DDRG] */ +-/* Port G Data Direction Register - DDRG */ +-#define DDG4 4 +-#define DDG3 3 +-#define DDG2 2 +-#define DDG1 1 +-#define DDG0 0 +-/* End Register Bits */ +- +-/* Register Bits [PING] */ +-/* Port G Input Pins - PING */ +-#define PING4 4 +-#define PING3 3 +-#define PING2 2 +-#define PING1 1 +-#define PING0 0 +-/* End Register Bits */ +- +- +-/* Register Bits [TIFR0] */ +-/* Timer/Counter 0 interrupt Flag Register */ +-#define OCF0A 1 +-#define TOV0 0 +-/* End Register Bits */ +- +-/* Register Bits [TIFR1] */ +-/* Timer/Counter 1 interrupt Flag Register */ +-#define ICF1 5 +-#define OCF1C 3 +-#define OCF1B 2 +-#define OCF1A 1 +-#define TOV1 0 +-/* End Register Bits */ +- +-/* Register Bits [TIFR2] */ +-/* Timer/Counter 2 interrupt Flag Register */ +-#define OCF2A 1 +-#define TOV2 0 +-/* End Register Bits */ +- +-/* Register Bits [TIFR3] */ +-/* Timer/Counter 3 interrupt Flag Register */ +-#define ICF3 5 +-#define OCF3C 3 +-#define OCF3B 2 +-#define OCF3A 1 +-#define TOV3 0 +-/* End Register Bits */ +- +-/* Register Bits [GPIOR0] */ +-/* General Purpose I/O Register 0 */ +-#define GPIOR07 7 +-#define GPIOR06 6 +-#define GPIOR05 5 +-#define GPIOR04 4 +-#define GPIOR03 3 +-#define GPIOR02 2 +-#define GPIOR01 1 +-#define GPIOR00 0 +-/* End Register Bits */ +- +-/* Register Bits [GPIOR1] */ +-/* General Purpose I/O Register 1 */ +-#define GPIOR17 7 +-#define GPIOR16 6 +-#define GPIOR15 5 +-#define GPIOR14 4 +-#define GPIOR13 3 +-#define GPIOR12 2 +-#define GPIOR11 1 +-#define GPIOR10 0 +-/* End Register Bits */ +- +-/* Register Bits [GPIOR2] */ +-/* General Purpose I/O Register 2 */ +-#define GPIOR27 7 +-#define GPIOR26 6 +-#define GPIOR25 5 +-#define GPIOR24 4 +-#define GPIOR23 3 +-#define GPIOR22 2 +-#define GPIOR21 1 +-#define GPIOR20 0 +-/* End Register Bits */ +- +-/* Register Bits [EECR] */ +-/* EEPROM Control Register */ +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +-/* End Register Bits */ +- +-/* Register Bits [EEDR] */ +-/* EEPROM Data Register */ +-#define EEDR7 7 +-#define EEDR6 6 +-#define EEDR5 5 +-#define EEDR4 4 +-#define EEDR3 3 +-#define EEDR2 2 +-#define EEDR1 1 +-#define EEDR0 0 +-/* End Register Bits */ +- +-/* Register Bits [EEARL] */ +-/* EEPROM Address Register */ +-#define EEAR7 7 +-#define EEAR6 6 +-#define EEAR5 5 +-#define EEAR4 4 +-#define EEAR3 3 +-#define EEAR2 2 +-#define EEAR1 1 +-#define EEAR0 0 +-/* End Register Bits */ +- +-/* Register Bits [EEARH] */ +-/* EEPROM Address Register */ +-#define EEAR11 3 +-#define EEAR10 2 +-#define EEAR9 1 +-#define EEAR8 0 +-/* End Register Bits */ +- +-/* Register Bits [GTCCR] */ +-/* General Timer/Counter Control Register */ +-#define TSM 7 +-#define PSR2 1 +-#define PSR310 0 +-/* End Register Bits */ +- +-/* Register Bits [TCCR0A] */ +-/* Timer/Counter Control Register A */ +-/* ALSO COVERED IN GENERIC SECTION */ +-#define FOC0A 7 +-#define WGM00 6 +-#define COM0A1 5 +-#define COM0A0 4 +-#define WGM01 3 +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +-/* End Register Bits */ +- +-/* Register Bits [OCR0A] */ +-/* Output Compare Register A */ +-#define OCR0A7 7 +-#define OCR0A6 6 +-#define OCR0A5 5 +-#define OCR0A4 4 +-#define OCR0A3 3 +-#define OCR0A2 2 +-#define OCR0A1 1 +-#define OCR0A0 0 +-/* End Register Bits */ +- +- +-/* Register Bits [SPIDR] */ +-/* SPI Data Register */ +-#define SPD7 7 +-#define SPD6 6 +-#define SPD5 5 +-#define SPD4 4 +-#define SPD3 3 +-#define SPD2 2 +-#define SPD1 1 +-#define SPD0 0 +-/* End Register Bits */ +- +-/* Register Bits [SMCR] */ +-/* Sleep Mode Control Register */ +-#define SM2 3 +-#define SM1 2 +-#define SM0 1 +-#define SE 0 +-/* End Register Bits */ +- +-/* Register Bits [MCUSR] */ +-/* MCU Status Register */ +-#define JTRF 4 +-#define WDRF 3 +-#define BORF 2 +-#define EXTRF 1 +-#define PORF 0 +-/* End Register Bits */ +- +-/* Register Bits [MCUCR] */ +-/* MCU Control Register */ +-#define JTD 7 +-#define PUD 4 +-#define IVSEL 1 +-#define IVCE 0 +-/* End Register Bits */ +- +-/* Register Bits [CLKPR] */ +-/* Clock Prescale Register */ +-#define CLKPCE 7 +-#define CLKPS3 3 +-#define CLKPS2 2 +-#define CLKPS1 1 +-#define CLKPS0 0 +-/* End Register Bits */ +- +-/* Register Bits [OSCCAL] */ +-/* Oscillator Calibration Register */ +-#define CAL6 6 +-#define CAL5 5 +-#define CAL4 4 +-#define CAL3 3 +-#define CAL2 2 +-#define CAL1 1 +-#define CAL0 0 +-/* End Register Bits */ +- +-/* Register Bits [TIMSK0] */ +-/* Timer/Counter 0 interrupt mask Register */ +-#define OCIE0A 1 +-#define TOIE0 0 +-/* End Register Bits */ +- +-/* Register Bits [TIMSK1] */ +-/* Timer/Counter 1 interrupt mask Register */ +-#define ICIE1 5 +-#define OCIE1C 3 +-#define OCIE1B 2 +-#define OCIE1A 1 +-#define TOIE1 0 +-/* End Register Bits */ +- +-/* Register Bits [TIMSK2] */ +-/* Timer/Counter 2 interrupt mask Register */ +-#define OCIE2A 1 +-#define TOIE2 0 +-/* End Register Bits */ +- +-/* Register Bits [TIMSK3] */ +-/* Timer/Counter 3 interrupt mask Register */ +-#define ICIE3 5 +-#define OCIE3C 3 +-#define OCIE3B 2 +-#define OCIE3A 1 +-#define TOIE3 0 +-/* End Register Bits */ +- +-//Begin CAN specific parts +- +-/* Register Bits [CANGCON] */ +-/* CAN General Control Register */ +-#define ABRQ 7 +-#define OVRQ 6 +-#define TTC 5 +-#define SYNTTC 4 +-#define LISTEN 3 +-#define TEST 2 +-#define ENASTB 1 +-#define SWRES 0 +-/* End Register Bits */ +- +-/* Register Bits [CANGSTA] */ +-/* CAN General Status Register */ +-#define OVFG 6 +-#define OVRG 6 +-#define TXBSY 4 +-#define RXBSY 3 +-#define ENFG 2 +-#define BOFF 1 +-#define ERRP 0 +-/* End Register Bits */ +- +-/* Register Bits [CANGIT] */ +-/* CAN General Interrupt Register */ +-#define CANIT 7 +-#define BOFFIT 6 +-#define OVRTIM 5 +-#define BXOK 4 +-#define SERG 3 +-#define CERG 2 +-#define FERG 1 +-#define AERG 0 +-/* End Register Bits */ +- +-/* Register Bits [CANGIE] */ +-/* CAN General Interrupt Enable */ +-#define ENIT 7 +-#define ENBOFF 6 +-#define ENRX 5 +-#define ENTX 4 +-#define ENERR 3 +-#define ENBX 2 +-#define ENERG 1 +-#define ENOVRT 0 +-/* End Register Bits */ +- +-/* Register Bits [CANEN2] */ +-/* CAN Enable MOb Register */ +-#define ENMOB7 7 +-#define ENMOB6 6 +-#define ENMOB5 5 +-#define ENMOB4 4 +-#define ENMOB3 3 +-#define ENMOB2 2 +-#define ENMOB1 1 +-#define ENMOB0 0 +-/* End Register Bits */ +- +-/* Register Bits [CANEN1] */ +-/* CAN Enable MOb Register */ +-#define ENMOB14 6 +-#define ENMOB13 5 +-#define ENMOB12 4 +-#define ENMOB11 3 +-#define ENMOB10 2 +-#define ENMOB9 1 +-#define ENMOB8 0 +-/* End Register Bits */ +- +-/* Register Bits [CANIE2] */ +-/* CAN Interrupt Enable MOb Register */ +-#define IEMOB7 7 +-#define IEMOB6 6 +-#define IEMOB5 5 +-#define IEMOB4 4 +-#define IEMOB3 3 +-#define IEMOB2 2 +-#define IEMOB1 1 +-#define IEMOB0 0 +-/* End Register Bits */ +- +-/* Register Bits [CANIE1] */ +-/* CAN Interrupt Enable MOb Register */ +-#define IEMOB14 6 +-#define IEMOB13 5 +-#define IEMOB12 4 +-#define IEMOB11 3 +-#define IEMOB10 2 +-#define IEMOB9 1 +-#define IEMOB8 0 +-/* End Register Bits */ +- +-/* Register Bits [CANSIT2] */ +-/* CAN Status Interrupt MOb Register */ +-#define SIT7 7 +-#define SIT6 6 +-#define SIT5 5 +-#define SIT4 4 +-#define SIT3 3 +-#define SIT2 2 +-#define SIT1 1 +-#define SIT0 0 +-/* End Register Bits */ +- +-/* Register Bits [CANSIT1] */ +-/* CAN Status Interrupt MOb Register */ +-#define SIT14 6 +-#define SIT13 5 +-#define SIT12 4 +-#define SIT11 3 +-#define SIT10 2 +-#define SIT9 1 +-#define SIT8 0 +-/* End Register Bits */ +- +-/* Register Bits [CANBT1] */ +-/* Bit Timing Register 1 */ +-#define BRP5 6 +-#define BRP4 5 +-#define BRP3 4 +-#define BRP2 3 +-#define BRP1 2 +-#define BRP0 1 +-/* End Register Bits */ +- +-/* Register Bits [CANBT2] */ +-/* Bit Timing Register 2 */ +-#define SJW1 6 +-#define SJW0 5 +-#define PRS2 3 +-#define PRS1 2 +-#define PRS0 1 +-/* End Register Bits */ +- +-/* Register Bits [CANBT3] */ +-/* Bit Timing Register 3 */ +-#define PHS22 6 +-#define PHS21 5 +-#define PHS20 4 +-#define PHS12 3 +-#define PHS11 2 +-#define PHS10 1 +-#define SMP 0 +-/* End Register Bits */ +- +-/* Register Bits [CANTCON] */ +-/* CAN Timer Control Register */ +-#define TPRSC7 7 +-#define TPRSC6 6 +-#define TPRSC5 5 +-#define TPRSC4 4 +-#define TPRSC3 3 +-#define TPRSC2 2 +-#define TPRSC1 1 +-#define TPRSC0 0 +-/* End Register Bits */ +- +-/* Register Bits [CANTIML] */ +-/* CAN Timer Register Low */ +-#define CANTIM7 7 +-#define CANTIM6 6 +-#define CANTIM5 5 +-#define CANTIM4 4 +-#define CANTIM3 3 +-#define CANTIM2 2 +-#define CANTIM1 1 +-#define CANTIM0 0 +-/* End Register Bits */ +- +-/* Register Bits [CANTIMH] */ +-/* CAN Timer Register High */ +-#define CANTIM15 7 +-#define CANTIM14 6 +-#define CANTIM13 5 +-#define CANTIM12 4 +-#define CANTIM11 3 +-#define CANTIM10 2 +-#define CANTIM9 1 +-#define CANTIM8 0 +-/* End Register Bits */ +- +-/* Register Bits [CANTTCL] */ +-/* CAN TTC Timer Register Low */ +-#define TIMTTC7 7 +-#define TIMTTC6 6 +-#define TIMTTC5 5 +-#define TIMTTC4 4 +-#define TIMTTC3 3 +-#define TIMTTC2 2 +-#define TIMTTC1 1 +-#define TIMTTC0 0 +-/* End Register Bits */ +- +-/* Register Bits [CANTTCH] */ +-/* CAN TTC Timer Register High */ +-#define TIMTTC15 7 +-#define TIMTTC14 6 +-#define TIMTTC13 5 +-#define TIMTTC12 4 +-#define TIMTTC11 3 +-#define TIMTTC10 2 +-#define TIMTTC9 1 +-#define TIMTTC8 0 +-/* End Register Bits */ +- +-/* Register Bits [CANTEC] */ +-/* CAN Transmitt Error Counter */ +-#define TEC7 7 +-#define TEC6 6 +-#define TEC5 5 +-#define TEC4 4 +-#define TEC3 3 +-#define TEC2 2 +-#define TEC1 1 +-#define TEC0 0 +-/* End Register Bits */ +- +-/* Register Bits [CANREC] */ +-/* CAN Receive Error Counter */ +-#define REC7 7 +-#define REC6 6 +-#define REC5 5 +-#define REC4 4 +-#define REC3 3 +-#define REC2 2 +-#define REC1 1 +-#define REC0 0 +-/* End Register Bits */ +- +-/* Register Bits [CANHPMOB] */ +-/* Highest Priority MOb */ +-#define HPMOB3 7 +-#define HPMOB2 6 +-#define HPMOB1 5 +-#define HPMOB0 4 +-#define CGP3 3 +-#define CGP2 2 +-#define CGP1 1 +-#define CGP0 0 +-/* End Register Bits */ +- +-/* Register Bits [CANPAGE] */ +-/* CAN Page MOb Register */ +-#define MOBNB3 7 +-#define MOBNB2 6 +-#define MOBNB1 5 +-#define MOBNB0 4 +-#define AINC 3 +-#define INDX2 2 +-#define INDX1 1 +-#define INDX0 0 +-/* End Register Bits */ +- +-/* Register Bits [CANSTMOB] */ +-/* CAN MOb Status Register */ +-#define DLCW 7 +-#define TXOK 6 +-#define RXOK 5 +-#define BERR 4 +-#define SERR 3 +-#define CERR 2 +-#define FERR 1 +-#define AERR 0 +-/* End Register Bits */ +- +-/* Register Bits [CANCDMOB] */ +-/* CAN MOb Control and DLC Register */ +-#define CONMOB1 7 +-#define CONMOB0 6 +-#define RPLV 5 +-#define IDE 4 +-#define DLC3 3 +-#define DLC2 2 +-#define DLC1 1 +-#define DLC0 0 +-/* End Register Bits */ +- +-/* Register Bits [CANIDT4] */ +-/* CAN Identifier Tag Register 4 */ +-#define IDT4 7 +-#define IDT3 6 +-#define IDT2 5 +-#define IDT1 4 +-#define IDT0 3 +-#define RTRTAG 2 +-#define RB1TAG 1 +-#define RB0TAG 0 +-/* End Register Bits */ +- +-/* Register Bits [CANIDT3] */ +-/* CAN Identifier Tag Register 3 */ +-#define IDT12 7 +-#define IDT11 6 +-#define IDT10 5 +-#define IDT9 4 +-#define IDT8 3 +-#define IDT7 2 +-#define IDT6 1 +-#define IDT5 0 +-/* End Register Bits */ +- +-/* Register Bits [CANIDT2] */ +-/* CAN Identifier Tag Register 2 */ +-#define IDT20 7 +-#define IDT19 6 +-#define IDT18 5 +-#define IDT17 4 +-#define IDT16 3 +-#define IDT15 2 +-#define IDT14 1 +-#define IDT13 0 +-/* End Register Bits */ +- +-/* Register Bits [CANIDT1] */ +-/* CAN Identifier Tag Register 1 */ +-#define IDT28 7 +-#define IDT27 6 +-#define IDT26 5 +-#define IDT25 4 +-#define IDT24 3 +-#define IDT23 2 +-#define IDT22 1 +-#define IDT21 0 +-/* End Register Bits */ +- +-/* Register Bits [CANIDM4] */ +-/* CAN Identifier Mask Register 4 */ +-#define IDMSK4 7 +-#define IDMSK3 6 +-#define IDMSK2 5 +-#define IDMSK1 4 +-#define IDMSK0 3 +-#define RTRMSK 2 +-#define IDEMSK 0 +-/* End Register Bits */ +- +-/* Register Bits [CANIDM3] */ +-/* CAN Identifier Mask Register 3 */ +-#define IDMSK12 7 +-#define IDMSK11 6 +-#define IDMSK10 5 +-#define IDMSK9 4 +-#define IDMSK8 3 +-#define IDMSK7 2 +-#define IDMSK6 1 +-#define IDMSK5 0 +-/* End Register Bits */ +- +-/* Register Bits [CANIDM2] */ +-/* CAN Identifier Mask Register 2 */ +-#define IDMSK20 7 +-#define IDMSK19 6 +-#define IDMSK18 5 +-#define IDMSK17 4 +-#define IDMSK16 3 +-#define IDMSK15 2 +-#define IDMSK14 1 +-#define IDMSK13 0 +-/* End Register Bits */ +- +-/* Register Bits [CANIDM1] */ +-/* CAN Identifier Mask Register 1 */ +-#define IDMSK28 7 +-#define IDMSK27 6 +-#define IDMSK26 5 +-#define IDMSK25 4 +-#define IDMSK24 3 +-#define IDMSK23 2 +-#define IDMSK22 1 +-#define IDMSK21 0 +-/* End Register Bits */ +- +-/* Register Bits [CANSTML] */ +-/* CAN Timer Register of some sort, low*/ +-#define TIMSTM7 7 +-#define TIMSTM6 6 +-#define TIMSTM5 5 +-#define TIMSTM4 4 +-#define TIMSTM3 3 +-#define TIMSTM2 2 +-#define TIMSTM1 1 +-#define TIMSTM0 0 +-/* End Register Bits */ +- +-/* Register Bits [CANSTMH] */ +-/* CAN Timer Register of some sort, high */ +-#define TIMSTM15 7 +-#define TIMSTM14 6 +-#define TIMSTM13 5 +-#define TIMSTM12 4 +-#define TIMSTM11 3 +-#define TIMSTM10 2 +-#define TIMSTM9 1 +-#define TIMSTM8 0 +-/* End Register Bits */ +- +-/* Register Bits [CANMSG] */ +-/* CAN Message Register */ +-#define MSG7 7 +-#define MSG6 6 +-#define MSG5 5 +-#define MSG4 4 +-#define MSG3 3 +-#define MSG2 2 +-#define MSG1 1 +-#define MSG0 0 +-/* End Register Bits */ +- +-/* Begin Verbatim */ +- +-/* Timer/Counter Control Register (generic) */ +-#define FOC 7 +-#define WGM0 6 +-#define COM1 5 +-#define COM0 4 +-#define WGM1 3 +-#define CS2 2 +-#define CS1 1 +-#define CS0 0 +- +-/* Timer/Counter Control Register A (generic) */ +-#define COMA1 7 +-#define COMA0 6 +-#define COMB1 5 +-#define COMB0 4 +-#define COMC1 3 +-#define COMC0 2 +-#define WGMA1 1 +-#define WGMA0 0 +- +-/* Timer/Counter Control and Status Register B (generic) */ +-#define ICNC 7 +-#define ICES 6 +-#define WGMB3 4 +-#define WGMB2 3 +-#define CSB2 2 +-#define CSB1 1 +-#define CSB0 0 +- +-/* Timer/Counter Control Register C (generic) */ +-#define FOCA 7 +-#define FOCB 6 +-#define FOCC 5 +- +-/* Port Data Register (generic) */ +-#define PORT7 7 +-#define PORT6 6 +-#define PORT5 5 +-#define PORT4 4 +-#define PORT3 3 +-#define PORT2 2 +-#define PORT1 1 +-#define PORT0 0 +- +-/* Port Data Direction Register (generic) */ +-#define DD7 7 +-#define DD6 6 +-#define DD5 5 +-#define DD4 4 +-#define DD3 3 +-#define DD2 2 +-#define DD1 1 +-#define DD0 0 +- +-/* Port Input Pins (generic) */ +-#define PIN7 7 +-#define PIN6 6 +-#define PIN5 5 +-#define PIN4 4 +-#define PIN3 3 +-#define PIN2 2 +-#define PIN1 1 +-#define PIN0 0 +- +-/* USART Status Register A (generic) */ +-#define RXC 7 +-#define TXC 6 +-#define UDRE 5 +-#define FE 4 +-#define DOR 3 +-#define UPE 2 +-#define U2X 1 +-#define MPCM 0 +- +-/* USART Control Register B (generic) */ +-#define RXCIE 7 +-#define TXCIE 6 +-#define UDRIE 5 +-#define RXEN 4 +-#define TXEN 3 +-#define UCSZ 2 +-#define UCSZ2 2 /* new name in datasheet (2467E-AVR-05/02) */ +-#define RXB8 1 +-#define TXB8 0 +- +-/* USART Register C (generic) */ +-#define UMSEL 6 +-#define UPM1 5 +-#define UPM0 4 +-#define USBS 3 +-#define UCSZ1 2 +-#define UCSZ0 1 +-#define UCPOL 0 +- +-/* End Verbatim */ +- +-#endif /* _AVR_IOCANXX_H_ */ ++/* Copyright (c) 2004,2005,2006 Colin O'Flynn ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iocanxx.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* This file is based largely on: ++ - iom128.h by Peter Jansen (bit defines) ++ - iom169.h by Juergen Schilling ++ (register addresses) ++ - AT90CAN128 Datasheet (bit defines and register addresses) ++ - Appnote on Mega128 --> AT90Can128 Conversion (for what registers I need ++ to change) */ ++ ++/* iocanxx.h - definitions for AT90CAN32, AT90CAN64 and AT90CAN128 */ ++ ++#ifndef _AVR_IOCANXX_H_ ++#define _AVR_IOCANXX_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iocanxx.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers and bit definitions. */ ++ ++/* RegDef: Port A */ ++#define PINA _SFR_IO8(0x00) ++#define DDRA _SFR_IO8(0x01) ++#define PORTA _SFR_IO8(0x02) ++ ++/* RegDef: Port B */ ++#define PINB _SFR_IO8(0x03) ++#define DDRB _SFR_IO8(0x04) ++#define PORTB _SFR_IO8(0x05) ++ ++/* RegDef: Port C */ ++#define PINC _SFR_IO8(0x06) ++#define DDRC _SFR_IO8(0x07) ++#define PORTC _SFR_IO8(0x08) ++ ++/* RegDef: Port D */ ++#define PIND _SFR_IO8(0x09) ++#define DDRD _SFR_IO8(0x0A) ++#define PORTD _SFR_IO8(0x0B) ++ ++/* RegDef: Port E */ ++#define PINE _SFR_IO8(0x0C) ++#define DDRE _SFR_IO8(0x0D) ++#define PORTE _SFR_IO8(0x0E) ++ ++/* RegDef: Port F */ ++#define PINF _SFR_IO8(0x0F) ++#define DDRF _SFR_IO8(0x10) ++#define PORTF _SFR_IO8(0x11) ++ ++/* RegDef: Port G */ ++#define PING _SFR_IO8(0x12) ++#define DDRG _SFR_IO8(0x13) ++#define PORTG _SFR_IO8(0x14) ++ ++/* RegDef: Timer/Counter 0 interrupt Flag Register */ ++#define TIFR0 _SFR_IO8(0x15) ++ ++/* RegDef: Timer/Counter 1 interrupt Flag Register */ ++#define TIFR1 _SFR_IO8(0x16) ++ ++/* RegDef: Timer/Counter 2 interrupt Flag Register */ ++#define TIFR2 _SFR_IO8(0x17) ++ ++/* RegDef: Timer/Counter 3 interrupt Flag Register */ ++#define TIFR3 _SFR_IO8(0x18) ++ ++/* RegDef: External Interrupt Flag Register */ ++#define EIFR _SFR_IO8(0x1C) ++ ++/* RegDef: External Interrupt Mask Register */ ++#define EIMSK _SFR_IO8(0x1D) ++ ++/* RegDef: General Purpose I/O Register 0 */ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++/* RegDef: EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1F) ++ ++/* RegDef: EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x20) ++ ++/* RegDef: EEPROM Address Register */ ++#define EEAR _SFR_IO16(0x21) ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++/* 6-char sequence denoting where to find the EEPROM registers in memory space. ++ Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM ++ subroutines. ++ First two letters: EECR address. ++ Second two letters: EEDR address. ++ Last two letters: EEAR address. */ ++#define __EEPROM_REG_LOCATIONS__ 1F2021 ++ ++/* RegDef: General Timer/Counter Control Register */ ++#define GTCCR _SFR_IO8(0x23) ++ ++/* RegDef: Timer/Counter Control Register A */ ++#define TCCR0A _SFR_IO8(0x24) ++ ++/* RegDef: Timer/Counter Register */ ++#define TCNT0 _SFR_IO8(0x26) ++ ++/* RegDef: Output Compare Register A */ ++#define OCR0A _SFR_IO8(0x27) ++ ++/* RegDef: General Purpose I/O Register 1 */ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++/* RegDef: General Purpose I/O Register 2 */ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++/* RegDef: SPI Control Register */ ++#define SPCR _SFR_IO8(0x2C) ++ ++/* RegDef: SPI Status Register */ ++#define SPSR _SFR_IO8(0x2D) ++ ++/* RegDef: SPI Data Register */ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* RegDef: Analog Comperator Control and Status Register */ ++#define ACSR _SFR_IO8(0x30) ++ ++/* RegDef: On-chip Debug Register */ ++#define OCDR _SFR_IO8(0x31) ++ ++/* RegDef: Sleep Mode Control Register */ ++#define SMCR _SFR_IO8(0x33) ++ ++/* RegDef: MCU Status Register */ ++#define MCUSR _SFR_IO8(0x34) ++ ++/* RegDef: MCU Control Rgeister */ ++#define MCUCR _SFR_IO8(0x35) ++ ++/* RegDef: Store Program Memory Control and Status Register */ ++#define SPMCSR _SFR_IO8(0x37) ++ ++/* RegDef: RAMPZ register. */ ++#define RAMPZ _SFR_IO8(0x3B) ++ ++/* RegDef: Watchdog Timer Control Register */ ++#define WDTCR _SFR_MEM8(0x60) ++ ++/* RegDef: Clock Prescale Register */ ++#define CLKPR _SFR_MEM8(0x61) ++ ++/* RegDef: Oscillator Calibration Register */ ++#define OSCCAL _SFR_MEM8(0x66) ++ ++/* RegDef: External Interrupt Control Register A */ ++#define EICRA _SFR_MEM8(0x69) ++ ++/* RegDef: External Interrupt Control Register B */ ++#define EICRB _SFR_MEM8(0x6A) ++ ++/* RegDef: Timer/Counter 0 Interrupt Mask Register */ ++#define TIMSK0 _SFR_MEM8(0x6E) ++ ++/* RegDef: Timer/Counter 1 Interrupt Mask Register */ ++#define TIMSK1 _SFR_MEM8(0x6F) ++ ++/* RegDef: Timer/Counter 2 Interrupt Mask Register */ ++#define TIMSK2 _SFR_MEM8(0x70) ++ ++/* RegDef: Timer/Counter 3 Interrupt Mask Register */ ++#define TIMSK3 _SFR_MEM8(0x71) ++ ++/* RegDef: External Memory Control Register A */ ++#define XMCRA _SFR_MEM8(0x74) ++ ++/* RegDef: External Memory Control Register A */ ++#define XMCRB _SFR_MEM8(0x75) ++ ++/* RegDef: ADC Data Register */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++/* RegDef: ADC Control and Status Register A */ ++#define ADCSRA _SFR_MEM8(0x7A) ++ ++/* RegDef: ADC Control and Status Register B */ ++#define ADCSRB _SFR_MEM8(0x7B) ++ ++/* RegDef: ADC Multiplex Selection Register */ ++#define ADMUX _SFR_MEM8(0x7C) ++ ++/* RegDef: Digital Input Disable Register 0 */ ++#define DIDR0 _SFR_MEM8(0x7E) ++ ++/* RegDef: Digital Input Disable Register 1 */ ++#define DIDR1 _SFR_MEM8(0x7F) ++ ++/* RegDef: Timer/Counter1 Control Register A */ ++#define TCCR1A _SFR_MEM8(0x80) ++ ++/* RegDef: Timer/Counter1 Control Register B */ ++#define TCCR1B _SFR_MEM8(0x81) ++ ++/* RegDef: Timer/Counter1 Control Register C */ ++#define TCCR1C _SFR_MEM8(0x82) ++ ++/* RegDef: Timer/Counter1 Register */ ++#define TCNT1 _SFR_MEM16(0x84) ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* RegDef: Timer/Counter1 Input Capture Register */ ++#define ICR1 _SFR_MEM16(0x86) ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* RegDef: Timer/Counter1 Output Compare Register A */ ++#define OCR1A _SFR_MEM16(0x88) ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* RegDef: Timer/Counter1 Output Compare Register B */ ++#define OCR1B _SFR_MEM16(0x8A) ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* RegDef: Timer/Counter1 Output Compare Register C */ ++#define OCR1C _SFR_MEM16(0x8C) ++#define OCR1CL _SFR_MEM8(0x8C) ++#define OCR1CH _SFR_MEM8(0x8D) ++ ++/* RegDef: Timer/Counter3 Control Register A */ ++#define TCCR3A _SFR_MEM8(0x90) ++ ++/* RegDef: Timer/Counter3 Control Register B */ ++#define TCCR3B _SFR_MEM8(0x91) ++ ++/* RegDef: Timer/Counter3 Control Register C */ ++#define TCCR3C _SFR_MEM8(0x92) ++ ++/* RegDef: Timer/Counter3 Register */ ++#define TCNT3 _SFR_MEM16(0x94) ++#define TCNT3L _SFR_MEM8(0x94) ++#define TCNT3H _SFR_MEM8(0x95) ++ ++/* RegDef: Timer/Counter3 Input Capture Register */ ++#define ICR3 _SFR_MEM16(0x96) ++#define ICR3L _SFR_MEM8(0x96) ++#define ICR3H _SFR_MEM8(0x97) ++ ++/* RegDef: Timer/Counter3 Output Compare Register A */ ++#define OCR3A _SFR_MEM16(0x98) ++#define OCR3AL _SFR_MEM8(0x98) ++#define OCR3AH _SFR_MEM8(0x99) ++ ++/* RegDef: Timer/Counter3 Output Compare Register B */ ++#define OCR3B _SFR_MEM16(0x9A) ++#define OCR3BL _SFR_MEM8(0x9A) ++#define OCR3BH _SFR_MEM8(0x9B) ++ ++/* RegDef: Timer/Counter3 Output Compare Register C */ ++#define OCR3C _SFR_MEM16(0x9C) ++#define OCR3CL _SFR_MEM8(0x9C) ++#define OCR3CH _SFR_MEM8(0x9D) ++ ++/* RegDef: Timer/Counter2 Control Register A */ ++#define TCCR2A _SFR_MEM8(0xB0) ++ ++/* RegDef: Timer/Counter2 Register */ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++/* RegDef: Timer/Counter2 Output Compare Register */ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++/* RegDef: Asynchronous Status Register */ ++#define ASSR _SFR_MEM8(0xB6) ++ ++/* RegDef: TWI Bit Rate Register */ ++#define TWBR _SFR_MEM8(0xB8) ++ ++/* RegDef: TWI Status Register */ ++#define TWSR _SFR_MEM8(0xB9) ++ ++/* RegDef: TWI (Slave) Address Register */ ++#define TWAR _SFR_MEM8(0xBA) ++ ++/* RegDef: TWI Data Register */ ++#define TWDR _SFR_MEM8(0xBB) ++ ++/* RegDef: TWI Control Register */ ++#define TWCR _SFR_MEM8(0xBC) ++ ++/* RegDef: USART0 Control and Status Register A */ ++#define UCSR0A _SFR_MEM8(0xC0) ++ ++/* RegDef: USART0 Control and Status Register B */ ++#define UCSR0B _SFR_MEM8(0xC1) ++ ++/* RegDef: USART0 Control and Status Register C */ ++#define UCSR0C _SFR_MEM8(0xC2) ++ ++/* RegDef: USART0 Baud Rate Register */ ++#define UBRR0 _SFR_MEM16(0xC4) ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++/* RegDef: USART0 I/O Data Register */ ++#define UDR0 _SFR_MEM8(0xC6) ++ ++/* RegDef: USART1 Control and Status Register A */ ++#define UCSR1A _SFR_MEM8(0xC8) ++ ++/* RegDef: USART1 Control and Status Register B */ ++#define UCSR1B _SFR_MEM8(0xC9) ++ ++/* RegDef: USART1 Control and Status Register C */ ++#define UCSR1C _SFR_MEM8(0xCA) ++ ++/* RegDef: USART1 Baud Rate Register */ ++#define UBRR1 _SFR_MEM16(0xCC) ++#define UBRR1L _SFR_MEM8(0xCC) ++#define UBRR1H _SFR_MEM8(0xCD) ++ ++/* RegDef: USART1 I/O Data Register */ ++#define UDR1 _SFR_MEM8(0xCE) ++ ++/* RegDef: CAN General Control Register*/ ++#define CANGCON _SFR_MEM8(0xD8) ++ ++/* RegDef: CAN General Status Register*/ ++#define CANGSTA _SFR_MEM8(0xD9) ++ ++/* RegDef: CAN General Interrupt Register*/ ++#define CANGIT _SFR_MEM8(0xDA) ++ ++/* RegDef: CAN General Interrupt Enable Register*/ ++#define CANGIE _SFR_MEM8(0xDB) ++ ++/* Word Definition: CAN Enable MOb Register*/ ++#define CANEN _SFR_MEM16(0xDC) ++ ++/* RegDef: CAN Enable MOb Register*/ ++#define CANEN2 _SFR_MEM8(0xDC) ++ ++/* RegDef: CAN Enable MOb Register*/ ++#define CANEN1 _SFR_MEM8(0xDD) ++ ++/* Word Definition: CAN Enable Interrupt MOb Register*/ ++#define CANIE _SFR_MEM16(0xDE) ++ ++/* RegDef: CAN Enable Interrupt MOb Register*/ ++#define CANIE2 _SFR_MEM8(0xDE) ++ ++/* RegDef: CAN Enable Interrupt MOb Register*/ ++#define CANIE1 _SFR_MEM8(0xDF) ++ ++/* RegDef: CAN Status Interrupt MOb Register*/ ++/* ++ * WARNING: Do not apply the SIT8...SIT14 constants to bits in the CANSIT ++ * register. ++ */ ++#define CANSIT _SFR_MEM16(0xE0) ++#define CANSIT2 _SFR_MEM8(0xE0) ++#define CANSIT1 _SFR_MEM8(0xE1) ++ ++/* RegDef: CAN Bit Timing Register 1*/ ++#define CANBT1 _SFR_MEM8(0xE2) ++ ++/* RegDef: CAN Bit Timing Register 2*/ ++#define CANBT2 _SFR_MEM8(0xE3) ++ ++/* RegDef: CAN Bit Timing Register 3*/ ++#define CANBT3 _SFR_MEM8(0xE4) ++ ++/* RegDef: CAN Timer Control Register*/ ++#define CANTCON _SFR_MEM8(0xE5) ++ ++/* RegDef: CAN Timer Register*/ ++#define CANTIM _SFR_MEM16(0xE6) ++#define CANTIML _SFR_MEM8(0xE6) ++#define CANTIMH _SFR_MEM8(0xE7) ++ ++/* RegDef: CAN TTC Timer Register*/ ++#define CANTTC _SFR_MEM16(0xE8) ++#define CANTTCL _SFR_MEM8(0xE8) ++#define CANTTCH _SFR_MEM8(0xE9) ++ ++/* RegDef: CAN Transmitt Error Counter Register*/ ++#define CANTEC _SFR_MEM8(0xEA) ++ ++/* RegDef: CAN Receive Error Counter Register*/ ++#define CANREC _SFR_MEM8(0xEB) ++ ++/* RegDef: CAN Highest Priority MOb Register*/ ++#define CANHPMOB _SFR_MEM8(0xEC) ++ ++/* RegDef: CAN Page MOb Register*/ ++#define CANPAGE _SFR_MEM8(0xED) ++ ++/* RegDef: CAN MOb Status Register*/ ++#define CANSTMOB _SFR_MEM8(0xEE) ++ ++/* RegDef: CAN MOb Control and DLC Register*/ ++#define CANCDMOB _SFR_MEM8(0xEF) ++ ++/* RegDef: CAN Identifier Tag Registers*/ ++#define CANIDT _SFR_MEM32(0xF0) ++ ++#define CANIDT4 _SFR_MEM8(0xF0) ++#define CANIDT3 _SFR_MEM8(0xF1) ++#define CANIDT2 _SFR_MEM8(0xF2) ++#define CANIDT1 _SFR_MEM8(0xF3) ++ ++/* RegDef: CAN Identifier Mask Registers */ ++#define CANIDM _SFR_MEM32(0xF4) ++ ++#define CANIDM4 _SFR_MEM8(0xF4) ++#define CANIDM3 _SFR_MEM8(0xF5) ++#define CANIDM2 _SFR_MEM8(0xF6) ++#define CANIDM1 _SFR_MEM8(0xF7) ++ ++/* RegDef: CAN TTC Timer Register*/ ++#define CANSTM _SFR_MEM16(0xF8) ++#define CANSTML _SFR_MEM8(0xF8) ++#define CANSTMH _SFR_MEM8(0xF9) ++ ++/* RegDef: CAN Message Register*/ ++#define CANMSG _SFR_MEM8(0xFA) ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++#define SIG_INTERRUPT1 _VECTOR(2) ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect_num 3 ++#define INT2_vect _VECTOR(3) ++#define SIG_INTERRUPT2 _VECTOR(3) ++ ++/* External Interrupt Request 3 */ ++#define INT3_vect_num 4 ++#define INT3_vect _VECTOR(4) ++#define SIG_INTERRUPT3 _VECTOR(4) ++ ++/* External Interrupt Request 4 */ ++#define INT4_vect_num 5 ++#define INT4_vect _VECTOR(5) ++#define SIG_INTERRUPT4 _VECTOR(5) ++ ++/* External Interrupt Request 5 */ ++#define INT5_vect_num 6 ++#define INT5_vect _VECTOR(6) ++#define SIG_INTERRUPT5 _VECTOR(6) ++ ++/* External Interrupt Request 6 */ ++#define INT6_vect_num 7 ++#define INT6_vect _VECTOR(7) ++#define SIG_INTERRUPT6 _VECTOR(7) ++ ++/* External Interrupt Request 7 */ ++#define INT7_vect_num 8 ++#define INT7_vect _VECTOR(8) ++#define SIG_INTERRUPT7 _VECTOR(8) ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect_num 9 ++#define TIMER2_COMP_vect _VECTOR(9) ++#define SIG_OUTPUT_COMPARE2 _VECTOR(9) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 10 ++#define TIMER2_OVF_vect _VECTOR(10) ++#define SIG_OVERFLOW2 _VECTOR(10) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 11 ++#define TIMER1_CAPT_vect _VECTOR(11) ++#define SIG_INPUT_CAPTURE1 _VECTOR(11) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 12 ++#define TIMER1_COMPA_vect _VECTOR(12) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(12) ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect_num 13 ++#define TIMER1_COMPB_vect _VECTOR(13) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(13) ++ ++/* Timer/Counter1 Compare Match C */ ++#define TIMER1_COMPC_vect_num 14 ++#define TIMER1_COMPC_vect _VECTOR(14) ++#define SIG_OUTPUT_COMPARE1C _VECTOR(14) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 15 ++#define TIMER1_OVF_vect _VECTOR(15) ++#define SIG_OVERFLOW1 _VECTOR(15) ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect_num 16 ++#define TIMER0_COMP_vect _VECTOR(16) ++#define SIG_OUTPUT_COMPARE0 _VECTOR(16) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 17 ++#define TIMER0_OVF_vect _VECTOR(17) ++#define SIG_OVERFLOW0 _VECTOR(17) ++ ++/* CAN Transfer Complete or Error */ ++#define CANIT_vect_num 18 ++#define CANIT_vect _VECTOR(18) ++#define SIG_CAN_INTERRUPT1 _VECTOR(18) ++ ++/* CAN Timer Overrun */ ++#define OVRIT_vect_num 19 ++#define OVRIT_vect _VECTOR(19) ++#define SIG_CAN_OVERFLOW1 _VECTOR(19) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 20 ++#define SPI_STC_vect _VECTOR(20) ++#define SIG_SPI _VECTOR(20) ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect_num 21 ++#define USART0_RX_vect _VECTOR(21) ++#define SIG_UART0_RECV _VECTOR(21) ++#define SIG_USART0_RECV _VECTOR(21) ++ ++/* USART0 Data Register Empty */ ++#define USART0_UDRE_vect_num 22 ++#define USART0_UDRE_vect _VECTOR(22) ++#define SIG_UART0_DATA _VECTOR(22) ++#define SIG_USART0_DATA _VECTOR(22) ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect_num 23 ++#define USART0_TX_vect _VECTOR(23) ++#define SIG_UART0_TRANS _VECTOR(23) ++#define SIG_USART0_TRANS _VECTOR(23) ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect_num 24 ++#define ANALOG_COMP_vect _VECTOR(24) ++#define SIG_COMPARATOR _VECTOR(24) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 25 ++#define ADC_vect _VECTOR(25) ++#define SIG_ADC _VECTOR(25) ++ ++/* EEPROM Ready */ ++#define EE_READY_vect_num 26 ++#define EE_READY_vect _VECTOR(26) ++#define SIG_EEPROM_READY _VECTOR(26) ++ ++/* Timer/Counter3 Capture Event */ ++#define TIMER3_CAPT_vect_num 27 ++#define TIMER3_CAPT_vect _VECTOR(27) ++#define SIG_INPUT_CAPTURE3 _VECTOR(27) ++ ++/* Timer/Counter3 Compare Match A */ ++#define TIMER3_COMPA_vect_num 28 ++#define TIMER3_COMPA_vect _VECTOR(28) ++#define SIG_OUTPUT_COMPARE3A _VECTOR(28) ++ ++/* Timer/Counter3 Compare Match B */ ++#define TIMER3_COMPB_vect_num 29 ++#define TIMER3_COMPB_vect _VECTOR(29) ++#define SIG_OUTPUT_COMPARE3B _VECTOR(29) ++ ++/* Timer/Counter3 Compare Match C */ ++#define TIMER3_COMPC_vect_num 30 ++#define TIMER3_COMPC_vect _VECTOR(30) ++#define SIG_OUTPUT_COMPARE3C _VECTOR(30) ++ ++/* Timer/Counter3 Overflow */ ++#define TIMER3_OVF_vect_num 31 ++#define TIMER3_OVF_vect _VECTOR(31) ++#define SIG_OVERFLOW3 _VECTOR(31) ++ ++/* USART1, Rx Complete */ ++#define USART1_RX_vect_num 32 ++#define USART1_RX_vect _VECTOR(32) ++#define SIG_UART1_RECV _VECTOR(32) ++#define SIG_USART1_RECV _VECTOR(32) ++ ++/* USART1, Data Register Empty */ ++#define USART1_UDRE_vect_num 33 ++#define USART1_UDRE_vect _VECTOR(33) ++#define SIG_UART1_DATA _VECTOR(33) ++#define SIG_USART1_DATA _VECTOR(33) ++ ++/* USART1, Tx Complete */ ++#define USART1_TX_vect_num 34 ++#define USART1_TX_vect _VECTOR(34) ++#define SIG_UART1_TRANS _VECTOR(34) ++#define SIG_USART1_TRANS _VECTOR(34) ++ ++/* 2-wire Serial Interface */ ++#define TWI_vect_num 35 ++#define TWI_vect _VECTOR(35) ++#define SIG_2WIRE_SERIAL _VECTOR(35) ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect_num 36 ++#define SPM_READY_vect _VECTOR(36) ++#define SIG_SPM_READY _VECTOR(36) ++ ++#define _VECTORS_SIZE 148 ++ ++/* The Register Bit names are represented by their bit number (0-7). */ ++ ++/* Register Bits [ASSR] */ ++/* Asynchronous Status Register */ ++#define EXCLK 4 ++#define AS2 3 ++#define TCN2UB 2 ++#define OCR2UB 1 ++#define TCR2UB 0 ++/* End Register Bits */ ++ ++/* Register Bits [TWCR] */ ++/* 2-wire Control Register - TWCR */ ++#define TWINT 7 ++#define TWEA 6 ++#define TWSTA 5 ++#define TWSTO 4 ++#define TWWC 3 ++#define TWEN 2 ++#define TWIE 0 ++/* End Register Bits */ ++ ++/* Register Bits [TWAR] */ ++/* 2-wire Address Register - TWAR */ ++#define TWA6 7 ++#define TWA5 6 ++#define TWA4 5 ++#define TWA3 4 ++#define TWA2 3 ++#define TWA1 2 ++#define TWA0 1 ++#define TWGCE 0 ++/* End Register Bits */ ++ ++/* Register Bits [TWSR] */ ++/* 2-wire Status Register - TWSR */ ++#define TWS7 7 ++#define TWS6 6 ++#define TWS5 5 ++#define TWS4 4 ++#define TWS3 3 ++#define TWPS1 1 ++#define TWPS0 0 ++/* End Register Bits */ ++ ++/* Register Bits [XMCRB] */ ++/* External Memory Control Register B - XMCRB */ ++#define XMBK 7 ++#define XMM2 2 ++#define XMM1 1 ++#define XMM0 0 ++/* End Register Bits */ ++ ++/* Register Bits [XMCRA] */ ++/* External Memory Control Register A - XMCRA */ ++#define SRE 7 ++#define SRL2 6 ++#define SRL1 5 ++#define SRL0 4 ++#define SRW11 3 ++#define SRW10 2 ++#define SRW01 1 ++#define SRW00 0 ++/* End Register Bits */ ++ ++/* Register Bits [RAMPZ] */ ++/* RAM Page Z select register - RAMPZ */ ++#define RAMPZ0 0 ++/* End Register Bits */ ++ ++/* Register Bits [EICRA] */ ++/* External Interrupt Control Register A - EICRA */ ++#define ISC31 7 ++#define ISC30 6 ++#define ISC21 5 ++#define ISC20 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++/* End Register Bits */ ++ ++/* Register Bits [EICRB] */ ++/* External Interrupt Control Register B - EICRB */ ++#define ISC71 7 ++#define ISC70 6 ++#define ISC61 5 ++#define ISC60 4 ++#define ISC51 3 ++#define ISC50 2 ++#define ISC41 1 ++#define ISC40 0 ++/* End Register Bits */ ++ ++/* Register Bits [SPMCSR] */ ++/* Store Program Memory Control Register - SPMCSR, SPMCR */ ++#define SPMIE 7 ++#define RWWSB 6 ++#define RWWSRE 4 ++#define BLBSET 3 ++#define PGWRT 2 ++#define PGERS 1 ++#define SPMEN 0 ++/* End Register Bits */ ++ ++/* Register Bits [EIMSK] */ ++/* External Interrupt MaSK register - EIMSK */ ++#define INT7 7 ++#define INT6 6 ++#define INT5 5 ++#define INT4 4 ++#define INT3 3 ++#define INT2 2 ++#define INT1 1 ++#define INT0 0 ++/* End Register Bits */ ++ ++/* Register Bits [EIFR] */ ++/* External Interrupt Flag Register - EIFR */ ++#define INTF7 7 ++#define INTF6 6 ++#define INTF5 5 ++#define INTF4 4 ++#define INTF3 3 ++#define INTF2 2 ++#define INTF1 1 ++#define INTF0 0 ++/* End Register Bits */ ++ ++/* Register Bits [TCCR2] */ ++/* Timer/Counter 2 Control Register - TCCR2 */ ++#define FOC2A 7 ++#define WGM20 6 ++#define COM2A1 5 ++#define COM2A0 4 ++#define WGM21 3 ++#define CS22 2 ++#define CS21 1 ++#define CS20 0 ++/* End Register Bits */ ++ ++/* Register Bits [TCCR1A] */ ++/* Timer/Counter 1 Control and Status Register A - TCCR1A */ ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define COM1C1 3 ++#define COM1C0 2 ++#define WGM11 1 ++#define WGM10 0 ++/* End Register Bits */ ++ ++/* Register Bits [TCCR3A] */ ++/* Timer/Counter 3 Control and Status Register A - TCCR3A */ ++#define COM3A1 7 ++#define COM3A0 6 ++#define COM3B1 5 ++#define COM3B0 4 ++#define COM3C1 3 ++#define COM3C0 2 ++#define WGM31 1 ++#define WGM30 0 ++/* End Register Bits */ ++ ++/* Register Bits [TCCR1B] */ ++/* Timer/Counter 1 Control and Status Register B - TCCR1B */ ++#define ICNC1 7 ++#define ICES1 6 ++#define WGM13 4 ++#define WGM12 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++/* End Register Bits */ ++ ++/* Register Bits [TCCR3B] */ ++/* Timer/Counter 3 Control and Status Register B - TCCR3B */ ++#define ICNC3 7 ++#define ICES3 6 ++#define WGM33 4 ++#define WGM32 3 ++#define CS32 2 ++#define CS31 1 ++#define CS30 0 ++/* End Register Bits */ ++ ++/* Register Bits [TCCR3C] */ ++/* Timer/Counter 3 Control Register C - TCCR3C */ ++#define FOC3A 7 ++#define FOC3B 6 ++#define FOC3C 5 ++/* End Register Bits */ ++ ++/* Register Bits [TCCR1C] */ ++/* Timer/Counter 1 Control Register C - TCCR1C */ ++#define FOC1A 7 ++#define FOC1B 6 ++#define FOC1C 5 ++/* End Register Bits */ ++ ++/* Register Bits [OCDR] */ ++/* On-chip Debug Register - OCDR */ ++#define IDRD 7 ++#define OCDR7 7 ++#define OCDR6 6 ++#define OCDR5 5 ++#define OCDR4 4 ++#define OCDR3 3 ++#define OCDR2 2 ++#define OCDR1 1 ++#define OCDR0 0 ++/* End Register Bits */ ++ ++/* Register Bits [WDTCR] */ ++/* Watchdog Timer Control Register - WDTCR */ ++#define WDCE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++/* End Register Bits */ ++ ++/* Register Bits [SPSR] */ ++/* SPI Status Register - SPSR */ ++#define SPIF 7 ++#define WCOL 6 ++#define SPI2X 0 ++/* End Register Bits */ ++ ++/* Register Bits [SPCR] */ ++/* SPI Control Register - SPCR */ ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++/* End Register Bits */ ++ ++/* Register Bits [UCSR1C] */ ++/* USART1 Register C - UCSR1C */ ++#define UMSEL1 6 ++#define UPM11 5 ++#define UPM10 4 ++#define USBS1 3 ++#define UCSZ11 2 ++#define UCSZ10 1 ++#define UCPOL1 0 ++/* End Register Bits */ ++ ++/* Register Bits [UCSR0C] */ ++/* USART0 Register C - UCSR0C */ ++#define UMSEL0 6 ++#define UPM01 5 ++#define UPM00 4 ++#define USBS0 3 ++#define UCSZ01 2 ++#define UCSZ00 1 ++#define UCPOL0 0 ++/* End Register Bits */ ++ ++/* Register Bits [UCSR1A] */ ++/* USART1 Status Register A - UCSR1A */ ++#define RXC1 7 ++#define TXC1 6 ++#define UDRE1 5 ++#define FE1 4 ++#define DOR1 3 ++#define UPE1 2 ++#define U2X1 1 ++#define MPCM1 0 ++/* End Register Bits */ ++ ++/* Register Bits [UCSR0A] */ ++/* USART0 Status Register A - UCSR0A */ ++#define RXC0 7 ++#define TXC0 6 ++#define UDRE0 5 ++#define FE0 4 ++#define DOR0 3 ++#define UPE0 2 ++#define U2X0 1 ++#define MPCM0 0 ++/* End Register Bits */ ++ ++/* Register Bits [UCSR1B] */ ++/* USART1 Control Register B - UCSR1B */ ++#define RXCIE1 7 ++#define TXCIE1 6 ++#define UDRIE1 5 ++#define RXEN1 4 ++#define TXEN1 3 ++#define UCSZ12 2 ++#define RXB81 1 ++#define TXB81 0 ++/* End Register Bits */ ++ ++/* Register Bits [UCSR0B] */ ++/* USART0 Control Register B - UCSR0B */ ++#define RXCIE0 7 ++#define TXCIE0 6 ++#define UDRIE0 5 ++#define RXEN0 4 ++#define TXEN0 3 ++#define UCSZ02 2 ++#define RXB80 1 ++#define TXB80 0 ++/* End Register Bits */ ++ ++/* Register Bits [ACSR] */ ++/* Analog Comparator Control and Status Register - ACSR */ ++#define ACD 7 ++#define ACBG 6 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++/* End Register Bits */ ++ ++/* Register Bits [ADCSRA] */ ++/* ADC Control and status register - ADCSRA */ ++#define ADEN 7 ++#define ADSC 6 ++#define ADATE 5 ++#define ADIF 4 ++#define ADIE 3 ++#define ADPS2 2 ++#define ADPS1 1 ++#define ADPS0 0 ++/* End Register Bits */ ++ ++/* ++ The ADHSM bit has been removed from all documentation, ++ as being not needed at all since the comparator has proven ++ to be fast enough even without feeding it more power. ++*/ ++ ++/* Register Bits [ADCSRB] */ ++/* ADC Control and status register - ADCSRB */ ++#define ACME 6 ++#define ADTS2 2 ++#define ADTS1 1 ++#define ADTS0 0 ++/* End Register Bits */ ++ ++/* Register Bits [ADMUX] */ ++/* ADC Multiplexer select - ADMUX */ ++#define REFS1 7 ++#define REFS0 6 ++#define ADLAR 5 ++#define MUX4 4 ++#define MUX3 3 ++#define MUX2 2 ++#define MUX1 1 ++#define MUX0 0 ++/* End Register Bits */ ++ ++/* Register Bits [DIDR0] */ ++/* Digital Input Disable Register 0 */ ++#define ADC7D 7 ++#define ADC6D 6 ++#define ADC5D 5 ++#define ADC4D 4 ++#define ADC3D 3 ++#define ADC2D 2 ++#define ADC1D 1 ++#define ADC0D 0 ++/* End Register Bits */ ++ ++/* Register Bits [DIDR1] */ ++/* Digital Input Disable Register 1 */ ++#define AIN1D 1 ++#define AIN0D 0 ++/* End Register Bits */ ++ ++/* Register Bits [PORTA] */ ++/* Port A Data Register - PORTA */ ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++/* End Register Bits */ ++ ++/* Register Bits [DDRA] */ ++/* Port A Data Direction Register - DDRA */ ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++/* End Register Bits */ ++ ++/* Register Bits [PINA] */ ++/* Port A Input Pins - PINA */ ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++/* End Register Bits */ ++ ++/* Register Bits [PORTB] */ ++/* Port B Data Register - PORTB */ ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++/* End Register Bits */ ++ ++/* Register Bits [DDRB] */ ++/* Port B Data Direction Register - DDRB */ ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++/* End Register Bits */ ++ ++/* Register Bits [PINB] */ ++/* Port B Input Pins - PINB */ ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++/* End Register Bits */ ++ ++/* Register Bits [PORTC] */ ++/* Port C Data Register - PORTC */ ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++/* End Register Bits */ ++ ++/* Register Bits [DDRC] */ ++/* Port C Data Direction Register - DDRC */ ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++/* End Register Bits */ ++ ++/* Register Bits [PINC] */ ++/* Port C Input Pins - PINC */ ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++/* End Register Bits */ ++ ++/* Register Bits [PORTD] */ ++/* Port D Data Register - PORTD */ ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++/* End Register Bits */ ++ ++/* Register Bits [DDRD] */ ++/* Port D Data Direction Register - DDRD */ ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++/* End Register Bits */ ++ ++/* Register Bits [PIND] */ ++/* Port D Input Pins - PIND */ ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++/* End Register Bits */ ++ ++/* Register Bits [PORTE] */ ++/* Port E Data Register - PORTE */ ++#define PE7 7 ++#define PE6 6 ++#define PE5 5 ++#define PE4 4 ++#define PE3 3 ++#define PE2 2 ++#define PE1 1 ++#define PE0 0 ++/* End Register Bits */ ++ ++/* Register Bits [DDRE] */ ++/* Port E Data Direction Register - DDRE */ ++#define DDE7 7 ++#define DDE6 6 ++#define DDE5 5 ++#define DDE4 4 ++#define DDE3 3 ++#define DDE2 2 ++#define DDE1 1 ++#define DDE0 0 ++/* End Register Bits */ ++ ++/* Register Bits [PINE] */ ++/* Port E Input Pins - PINE */ ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++/* End Register Bits */ ++ ++/* Register Bits [PORTF] */ ++/* Port F Data Register - PORTF */ ++#define PF7 7 ++#define PF6 6 ++#define PF5 5 ++#define PF4 4 ++#define PF3 3 ++#define PF2 2 ++#define PF1 1 ++#define PF0 0 ++/* End Register Bits */ ++ ++/* Register Bits [DDRF] */ ++/* Port F Data Direction Register - DDRF */ ++#define DDF7 7 ++#define DDF6 6 ++#define DDF5 5 ++#define DDF4 4 ++#define DDF3 3 ++#define DDF2 2 ++#define DDF1 1 ++#define DDF0 0 ++/* End Register Bits */ ++ ++/* Register Bits [PINF] */ ++/* Port F Input Pins - PINF */ ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++/* End Register Bits */ ++ ++/* Register Bits [PORTG] */ ++/* Port G Data Register - PORTG */ ++#define PG4 4 ++#define PG3 3 ++#define PG2 2 ++#define PG1 1 ++#define PG0 0 ++/* End Register Bits */ ++ ++/* Register Bits [DDRG] */ ++/* Port G Data Direction Register - DDRG */ ++#define DDG4 4 ++#define DDG3 3 ++#define DDG2 2 ++#define DDG1 1 ++#define DDG0 0 ++/* End Register Bits */ ++ ++/* Register Bits [PING] */ ++/* Port G Input Pins - PING */ ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++/* End Register Bits */ ++ ++ ++/* Register Bits [TIFR0] */ ++/* Timer/Counter 0 interrupt Flag Register */ ++#define OCF0A 1 ++#define TOV0 0 ++/* End Register Bits */ ++ ++/* Register Bits [TIFR1] */ ++/* Timer/Counter 1 interrupt Flag Register */ ++#define ICF1 5 ++#define OCF1C 3 ++#define OCF1B 2 ++#define OCF1A 1 ++#define TOV1 0 ++/* End Register Bits */ ++ ++/* Register Bits [TIFR2] */ ++/* Timer/Counter 2 interrupt Flag Register */ ++#define OCF2A 1 ++#define TOV2 0 ++/* End Register Bits */ ++ ++/* Register Bits [TIFR3] */ ++/* Timer/Counter 3 interrupt Flag Register */ ++#define ICF3 5 ++#define OCF3C 3 ++#define OCF3B 2 ++#define OCF3A 1 ++#define TOV3 0 ++/* End Register Bits */ ++ ++/* Register Bits [GPIOR0] */ ++/* General Purpose I/O Register 0 */ ++#define GPIOR07 7 ++#define GPIOR06 6 ++#define GPIOR05 5 ++#define GPIOR04 4 ++#define GPIOR03 3 ++#define GPIOR02 2 ++#define GPIOR01 1 ++#define GPIOR00 0 ++/* End Register Bits */ ++ ++/* Register Bits [GPIOR1] */ ++/* General Purpose I/O Register 1 */ ++#define GPIOR17 7 ++#define GPIOR16 6 ++#define GPIOR15 5 ++#define GPIOR14 4 ++#define GPIOR13 3 ++#define GPIOR12 2 ++#define GPIOR11 1 ++#define GPIOR10 0 ++/* End Register Bits */ ++ ++/* Register Bits [GPIOR2] */ ++/* General Purpose I/O Register 2 */ ++#define GPIOR27 7 ++#define GPIOR26 6 ++#define GPIOR25 5 ++#define GPIOR24 4 ++#define GPIOR23 3 ++#define GPIOR22 2 ++#define GPIOR21 1 ++#define GPIOR20 0 ++/* End Register Bits */ ++ ++/* Register Bits [EECR] */ ++/* EEPROM Control Register */ ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++/* End Register Bits */ ++ ++/* Register Bits [EEDR] */ ++/* EEPROM Data Register */ ++#define EEDR7 7 ++#define EEDR6 6 ++#define EEDR5 5 ++#define EEDR4 4 ++#define EEDR3 3 ++#define EEDR2 2 ++#define EEDR1 1 ++#define EEDR0 0 ++/* End Register Bits */ ++ ++/* Register Bits [EEARL] */ ++/* EEPROM Address Register */ ++#define EEAR7 7 ++#define EEAR6 6 ++#define EEAR5 5 ++#define EEAR4 4 ++#define EEAR3 3 ++#define EEAR2 2 ++#define EEAR1 1 ++#define EEAR0 0 ++/* End Register Bits */ ++ ++/* Register Bits [EEARH] */ ++/* EEPROM Address Register */ ++#define EEAR11 3 ++#define EEAR10 2 ++#define EEAR9 1 ++#define EEAR8 0 ++/* End Register Bits */ ++ ++/* Register Bits [GTCCR] */ ++/* General Timer/Counter Control Register */ ++#define TSM 7 ++#define PSR2 1 ++#define PSR310 0 ++/* End Register Bits */ ++ ++/* Register Bits [TCCR0A] */ ++/* Timer/Counter Control Register A */ ++/* ALSO COVERED IN GENERIC SECTION */ ++#define FOC0A 7 ++#define WGM00 6 ++#define COM0A1 5 ++#define COM0A0 4 ++#define WGM01 3 ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++/* End Register Bits */ ++ ++/* Register Bits [OCR0A] */ ++/* Output Compare Register A */ ++#define OCR0A7 7 ++#define OCR0A6 6 ++#define OCR0A5 5 ++#define OCR0A4 4 ++#define OCR0A3 3 ++#define OCR0A2 2 ++#define OCR0A1 1 ++#define OCR0A0 0 ++/* End Register Bits */ ++ ++ ++/* Register Bits [SPIDR] */ ++/* SPI Data Register */ ++#define SPD7 7 ++#define SPD6 6 ++#define SPD5 5 ++#define SPD4 4 ++#define SPD3 3 ++#define SPD2 2 ++#define SPD1 1 ++#define SPD0 0 ++/* End Register Bits */ ++ ++/* Register Bits [SMCR] */ ++/* Sleep Mode Control Register */ ++#define SM2 3 ++#define SM1 2 ++#define SM0 1 ++#define SE 0 ++/* End Register Bits */ ++ ++/* Register Bits [MCUSR] */ ++/* MCU Status Register */ ++#define JTRF 4 ++#define WDRF 3 ++#define BORF 2 ++#define EXTRF 1 ++#define PORF 0 ++/* End Register Bits */ ++ ++/* Register Bits [MCUCR] */ ++/* MCU Control Register */ ++#define JTD 7 ++#define PUD 4 ++#define IVSEL 1 ++#define IVCE 0 ++/* End Register Bits */ ++ ++/* Register Bits [CLKPR] */ ++/* Clock Prescale Register */ ++#define CLKPCE 7 ++#define CLKPS3 3 ++#define CLKPS2 2 ++#define CLKPS1 1 ++#define CLKPS0 0 ++/* End Register Bits */ ++ ++/* Register Bits [OSCCAL] */ ++/* Oscillator Calibration Register */ ++#define CAL6 6 ++#define CAL5 5 ++#define CAL4 4 ++#define CAL3 3 ++#define CAL2 2 ++#define CAL1 1 ++#define CAL0 0 ++/* End Register Bits */ ++ ++/* Register Bits [TIMSK0] */ ++/* Timer/Counter 0 interrupt mask Register */ ++#define OCIE0A 1 ++#define TOIE0 0 ++/* End Register Bits */ ++ ++/* Register Bits [TIMSK1] */ ++/* Timer/Counter 1 interrupt mask Register */ ++#define ICIE1 5 ++#define OCIE1C 3 ++#define OCIE1B 2 ++#define OCIE1A 1 ++#define TOIE1 0 ++/* End Register Bits */ ++ ++/* Register Bits [TIMSK2] */ ++/* Timer/Counter 2 interrupt mask Register */ ++#define OCIE2A 1 ++#define TOIE2 0 ++/* End Register Bits */ ++ ++/* Register Bits [TIMSK3] */ ++/* Timer/Counter 3 interrupt mask Register */ ++#define ICIE3 5 ++#define OCIE3C 3 ++#define OCIE3B 2 ++#define OCIE3A 1 ++#define TOIE3 0 ++/* End Register Bits */ ++ ++//Begin CAN specific parts ++ ++/* Register Bits [CANGCON] */ ++/* CAN General Control Register */ ++#define ABRQ 7 ++#define OVRQ 6 ++#define TTC 5 ++#define SYNTTC 4 ++#define LISTEN 3 ++#define TEST 2 ++#define ENASTB 1 ++#define SWRES 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANGSTA] */ ++/* CAN General Status Register */ ++#define OVFG 6 ++#define OVRG 6 ++#define TXBSY 4 ++#define RXBSY 3 ++#define ENFG 2 ++#define BOFF 1 ++#define ERRP 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANGIT] */ ++/* CAN General Interrupt Register */ ++#define CANIT 7 ++#define BOFFIT 6 ++#define OVRTIM 5 ++#define BXOK 4 ++#define SERG 3 ++#define CERG 2 ++#define FERG 1 ++#define AERG 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANGIE] */ ++/* CAN General Interrupt Enable */ ++#define ENIT 7 ++#define ENBOFF 6 ++#define ENRX 5 ++#define ENTX 4 ++#define ENERR 3 ++#define ENBX 2 ++#define ENERG 1 ++#define ENOVRT 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANEN2] */ ++/* CAN Enable MOb Register */ ++#define ENMOB7 7 ++#define ENMOB6 6 ++#define ENMOB5 5 ++#define ENMOB4 4 ++#define ENMOB3 3 ++#define ENMOB2 2 ++#define ENMOB1 1 ++#define ENMOB0 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANEN1] */ ++/* CAN Enable MOb Register */ ++#define ENMOB14 6 ++#define ENMOB13 5 ++#define ENMOB12 4 ++#define ENMOB11 3 ++#define ENMOB10 2 ++#define ENMOB9 1 ++#define ENMOB8 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANIE2] */ ++/* CAN Interrupt Enable MOb Register */ ++#define IEMOB7 7 ++#define IEMOB6 6 ++#define IEMOB5 5 ++#define IEMOB4 4 ++#define IEMOB3 3 ++#define IEMOB2 2 ++#define IEMOB1 1 ++#define IEMOB0 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANIE1] */ ++/* CAN Interrupt Enable MOb Register */ ++#define IEMOB14 6 ++#define IEMOB13 5 ++#define IEMOB12 4 ++#define IEMOB11 3 ++#define IEMOB10 2 ++#define IEMOB9 1 ++#define IEMOB8 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANSIT2] */ ++/* CAN Status Interrupt MOb Register */ ++#define SIT7 7 ++#define SIT6 6 ++#define SIT5 5 ++#define SIT4 4 ++#define SIT3 3 ++#define SIT2 2 ++#define SIT1 1 ++#define SIT0 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANSIT1] */ ++/* CAN Status Interrupt MOb Register */ ++#define SIT14 6 ++#define SIT13 5 ++#define SIT12 4 ++#define SIT11 3 ++#define SIT10 2 ++#define SIT9 1 ++#define SIT8 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANBT1] */ ++/* Bit Timing Register 1 */ ++#define BRP5 6 ++#define BRP4 5 ++#define BRP3 4 ++#define BRP2 3 ++#define BRP1 2 ++#define BRP0 1 ++/* End Register Bits */ ++ ++/* Register Bits [CANBT2] */ ++/* Bit Timing Register 2 */ ++#define SJW1 6 ++#define SJW0 5 ++#define PRS2 3 ++#define PRS1 2 ++#define PRS0 1 ++/* End Register Bits */ ++ ++/* Register Bits [CANBT3] */ ++/* Bit Timing Register 3 */ ++#define PHS22 6 ++#define PHS21 5 ++#define PHS20 4 ++#define PHS12 3 ++#define PHS11 2 ++#define PHS10 1 ++#define SMP 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANTCON] */ ++/* CAN Timer Control Register */ ++#define TPRSC7 7 ++#define TPRSC6 6 ++#define TPRSC5 5 ++#define TPRSC4 4 ++#define TPRSC3 3 ++#define TPRSC2 2 ++#define TPRSC1 1 ++#define TPRSC0 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANTIML] */ ++/* CAN Timer Register Low */ ++#define CANTIM7 7 ++#define CANTIM6 6 ++#define CANTIM5 5 ++#define CANTIM4 4 ++#define CANTIM3 3 ++#define CANTIM2 2 ++#define CANTIM1 1 ++#define CANTIM0 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANTIMH] */ ++/* CAN Timer Register High */ ++#define CANTIM15 7 ++#define CANTIM14 6 ++#define CANTIM13 5 ++#define CANTIM12 4 ++#define CANTIM11 3 ++#define CANTIM10 2 ++#define CANTIM9 1 ++#define CANTIM8 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANTTCL] */ ++/* CAN TTC Timer Register Low */ ++#define TIMTTC7 7 ++#define TIMTTC6 6 ++#define TIMTTC5 5 ++#define TIMTTC4 4 ++#define TIMTTC3 3 ++#define TIMTTC2 2 ++#define TIMTTC1 1 ++#define TIMTTC0 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANTTCH] */ ++/* CAN TTC Timer Register High */ ++#define TIMTTC15 7 ++#define TIMTTC14 6 ++#define TIMTTC13 5 ++#define TIMTTC12 4 ++#define TIMTTC11 3 ++#define TIMTTC10 2 ++#define TIMTTC9 1 ++#define TIMTTC8 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANTEC] */ ++/* CAN Transmitt Error Counter */ ++#define TEC7 7 ++#define TEC6 6 ++#define TEC5 5 ++#define TEC4 4 ++#define TEC3 3 ++#define TEC2 2 ++#define TEC1 1 ++#define TEC0 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANREC] */ ++/* CAN Receive Error Counter */ ++#define REC7 7 ++#define REC6 6 ++#define REC5 5 ++#define REC4 4 ++#define REC3 3 ++#define REC2 2 ++#define REC1 1 ++#define REC0 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANHPMOB] */ ++/* Highest Priority MOb */ ++#define HPMOB3 7 ++#define HPMOB2 6 ++#define HPMOB1 5 ++#define HPMOB0 4 ++#define CGP3 3 ++#define CGP2 2 ++#define CGP1 1 ++#define CGP0 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANPAGE] */ ++/* CAN Page MOb Register */ ++#define MOBNB3 7 ++#define MOBNB2 6 ++#define MOBNB1 5 ++#define MOBNB0 4 ++#define AINC 3 ++#define INDX2 2 ++#define INDX1 1 ++#define INDX0 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANSTMOB] */ ++/* CAN MOb Status Register */ ++#define DLCW 7 ++#define TXOK 6 ++#define RXOK 5 ++#define BERR 4 ++#define SERR 3 ++#define CERR 2 ++#define FERR 1 ++#define AERR 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANCDMOB] */ ++/* CAN MOb Control and DLC Register */ ++#define CONMOB1 7 ++#define CONMOB0 6 ++#define RPLV 5 ++#define IDE 4 ++#define DLC3 3 ++#define DLC2 2 ++#define DLC1 1 ++#define DLC0 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANIDT4] */ ++/* CAN Identifier Tag Register 4 */ ++#define IDT4 7 ++#define IDT3 6 ++#define IDT2 5 ++#define IDT1 4 ++#define IDT0 3 ++#define RTRTAG 2 ++#define RB1TAG 1 ++#define RB0TAG 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANIDT3] */ ++/* CAN Identifier Tag Register 3 */ ++#define IDT12 7 ++#define IDT11 6 ++#define IDT10 5 ++#define IDT9 4 ++#define IDT8 3 ++#define IDT7 2 ++#define IDT6 1 ++#define IDT5 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANIDT2] */ ++/* CAN Identifier Tag Register 2 */ ++#define IDT20 7 ++#define IDT19 6 ++#define IDT18 5 ++#define IDT17 4 ++#define IDT16 3 ++#define IDT15 2 ++#define IDT14 1 ++#define IDT13 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANIDT1] */ ++/* CAN Identifier Tag Register 1 */ ++#define IDT28 7 ++#define IDT27 6 ++#define IDT26 5 ++#define IDT25 4 ++#define IDT24 3 ++#define IDT23 2 ++#define IDT22 1 ++#define IDT21 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANIDM4] */ ++/* CAN Identifier Mask Register 4 */ ++#define IDMSK4 7 ++#define IDMSK3 6 ++#define IDMSK2 5 ++#define IDMSK1 4 ++#define IDMSK0 3 ++#define RTRMSK 2 ++#define IDEMSK 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANIDM3] */ ++/* CAN Identifier Mask Register 3 */ ++#define IDMSK12 7 ++#define IDMSK11 6 ++#define IDMSK10 5 ++#define IDMSK9 4 ++#define IDMSK8 3 ++#define IDMSK7 2 ++#define IDMSK6 1 ++#define IDMSK5 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANIDM2] */ ++/* CAN Identifier Mask Register 2 */ ++#define IDMSK20 7 ++#define IDMSK19 6 ++#define IDMSK18 5 ++#define IDMSK17 4 ++#define IDMSK16 3 ++#define IDMSK15 2 ++#define IDMSK14 1 ++#define IDMSK13 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANIDM1] */ ++/* CAN Identifier Mask Register 1 */ ++#define IDMSK28 7 ++#define IDMSK27 6 ++#define IDMSK26 5 ++#define IDMSK25 4 ++#define IDMSK24 3 ++#define IDMSK23 2 ++#define IDMSK22 1 ++#define IDMSK21 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANSTML] */ ++/* CAN Timer Register of some sort, low*/ ++#define TIMSTM7 7 ++#define TIMSTM6 6 ++#define TIMSTM5 5 ++#define TIMSTM4 4 ++#define TIMSTM3 3 ++#define TIMSTM2 2 ++#define TIMSTM1 1 ++#define TIMSTM0 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANSTMH] */ ++/* CAN Timer Register of some sort, high */ ++#define TIMSTM15 7 ++#define TIMSTM14 6 ++#define TIMSTM13 5 ++#define TIMSTM12 4 ++#define TIMSTM11 3 ++#define TIMSTM10 2 ++#define TIMSTM9 1 ++#define TIMSTM8 0 ++/* End Register Bits */ ++ ++/* Register Bits [CANMSG] */ ++/* CAN Message Register */ ++#define MSG7 7 ++#define MSG6 6 ++#define MSG5 5 ++#define MSG4 4 ++#define MSG3 3 ++#define MSG2 2 ++#define MSG1 1 ++#define MSG0 0 ++/* End Register Bits */ ++ ++/* Begin Verbatim */ ++ ++/* Timer/Counter Control Register (generic) */ ++#define FOC 7 ++#define WGM0 6 ++#define COM1 5 ++#define COM0 4 ++#define WGM1 3 ++#define CS2 2 ++#define CS1 1 ++#define CS0 0 ++ ++/* Timer/Counter Control Register A (generic) */ ++#define COMA1 7 ++#define COMA0 6 ++#define COMB1 5 ++#define COMB0 4 ++#define COMC1 3 ++#define COMC0 2 ++#define WGMA1 1 ++#define WGMA0 0 ++ ++/* Timer/Counter Control and Status Register B (generic) */ ++#define ICNC 7 ++#define ICES 6 ++#define WGMB3 4 ++#define WGMB2 3 ++#define CSB2 2 ++#define CSB1 1 ++#define CSB0 0 ++ ++/* Timer/Counter Control Register C (generic) */ ++#define FOCA 7 ++#define FOCB 6 ++#define FOCC 5 ++ ++/* Port Data Register (generic) */ ++#define PORT7 7 ++#define PORT6 6 ++#define PORT5 5 ++#define PORT4 4 ++#define PORT3 3 ++#define PORT2 2 ++#define PORT1 1 ++#define PORT0 0 ++ ++/* Port Data Direction Register (generic) */ ++#define DD7 7 ++#define DD6 6 ++#define DD5 5 ++#define DD4 4 ++#define DD3 3 ++#define DD2 2 ++#define DD1 1 ++#define DD0 0 ++ ++/* Port Input Pins (generic) */ ++#define PIN7 7 ++#define PIN6 6 ++#define PIN5 5 ++#define PIN4 4 ++#define PIN3 3 ++#define PIN2 2 ++#define PIN1 1 ++#define PIN0 0 ++ ++/* USART Status Register A (generic) */ ++#define RXC 7 ++#define TXC 6 ++#define UDRE 5 ++#define FE 4 ++#define DOR 3 ++#define UPE 2 ++#define U2X 1 ++#define MPCM 0 ++ ++/* USART Control Register B (generic) */ ++#define RXCIE 7 ++#define TXCIE 6 ++#define UDRIE 5 ++#define RXEN 4 ++#define TXEN 3 ++#define UCSZ 2 ++#define UCSZ2 2 /* new name in datasheet (2467E-AVR-05/02) */ ++#define RXB8 1 ++#define TXB8 0 ++ ++/* USART Register C (generic) */ ++#define UMSEL 6 ++#define UPM1 5 ++#define UPM0 4 ++#define USBS 3 ++#define UCSZ1 2 ++#define UCSZ0 1 ++#define UCPOL 0 ++ ++/* End Verbatim */ ++ ++#endif /* _AVR_IOCANXX_H_ */ +diff --git a/include/avr/iom103.h b/include/avr/iom103.h +index b79a9b0..7d84ceb 100644 +--- a/include/avr/iom103.h ++++ b/include/avr/iom103.h +@@ -1,731 +1,732 @@ +-/* Copyright (c) 2002, Marek Michalkiewicz +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom103.h 2227 2011-03-04 19:35:10Z arcanum $ */ +- +-/* avr/iom103.h - definitions for ATmega103 */ +- +-#ifndef _AVR_IOM103_H_ +-#define _AVR_IOM103_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom103.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* Input Pins, Port F */ +-#define PINF _SFR_IO8(0x00) +- +-/* Input Pins, Port E */ +-#define PINE _SFR_IO8(0x01) +- +-/* Data Direction Register, Port E */ +-#define DDRE _SFR_IO8(0x02) +- +-/* Data Register, Port E */ +-#define PORTE _SFR_IO8(0x03) +- +-/* ADC Data Register */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x04) +-#endif +-#define ADCW _SFR_IO16(0x04) +-#define ADCL _SFR_IO8(0x04) +-#define ADCH _SFR_IO8(0x05) +- +-/* ADC Control and status register */ +-#define ADCSR _SFR_IO8(0x06) +- +-/* ADC Multiplexer select */ +-#define ADMUX _SFR_IO8(0x07) +- +-/* Analog Comparator Control and Status Register */ +-#define ACSR _SFR_IO8(0x08) +- +-/* UART Baud Rate Register */ +-#define UBRR _SFR_IO8(0x09) +- +-/* UART Control Register */ +-#define UCR _SFR_IO8(0x0A) +- +-/* UART Status Register */ +-#define USR _SFR_IO8(0x0B) +- +-/* UART I/O Data Register */ +-#define UDR _SFR_IO8(0x0C) +- +-/* SPI Control Register */ +-#define SPCR _SFR_IO8(0x0D) +- +-/* SPI Status Register */ +-#define SPSR _SFR_IO8(0x0E) +- +-/* SPI I/O Data Register */ +-#define SPDR _SFR_IO8(0x0F) +- +-/* Input Pins, Port D */ +-#define PIND _SFR_IO8(0x10) +- +-/* Data Direction Register, Port D */ +-#define DDRD _SFR_IO8(0x11) +- +-/* Data Register, Port D */ +-#define PORTD _SFR_IO8(0x12) +- +-/* Data Register, Port C */ +-#define PORTC _SFR_IO8(0x15) +- +-/* Input Pins, Port B */ +-#define PINB _SFR_IO8(0x16) +- +-/* Data Direction Register, Port B */ +-#define DDRB _SFR_IO8(0x17) +- +-/* Data Register, Port B */ +-#define PORTB _SFR_IO8(0x18) +- +-/* Input Pins, Port A */ +-#define PINA _SFR_IO8(0x19) +- +-/* Data Direction Register, Port A */ +-#define DDRA _SFR_IO8(0x1A) +- +-/* Data Register, Port A */ +-#define PORTA _SFR_IO8(0x1B) +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO16(0x1E) +-#define EEARL _SFR_IO8(0x1E) +-#define EEARH _SFR_IO8(0x1F) +- +-/* Watchdog Timer Control Register */ +-#define WDTCR _SFR_IO8(0x21) +- +-/* Timer2 Output Compare Register */ +-#define OCR2 _SFR_IO8(0x23) +- +-/* Timer/Counter 2 */ +-#define TCNT2 _SFR_IO8(0x24) +- +-/* Timer/Counter 2 Control register */ +-#define TCCR2 _SFR_IO8(0x25) +- +-/* T/C 1 Input Capture Register */ +-#define ICR1 _SFR_IO16(0x26) +-#define ICR1L _SFR_IO8(0x26) +-#define ICR1H _SFR_IO8(0x27) +- +-/* Timer/Counter1 Output Compare Register B */ +-#define OCR1B _SFR_IO16(0x28) +-#define OCR1BL _SFR_IO8(0x28) +-#define OCR1BH _SFR_IO8(0x29) +- +-/* Timer/Counter1 Output Compare Register A */ +-#define OCR1A _SFR_IO16(0x2A) +-#define OCR1AL _SFR_IO8(0x2A) +-#define OCR1AH _SFR_IO8(0x2B) +- +-/* Timer/Counter 1 */ +-#define TCNT1 _SFR_IO16(0x2C) +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1H _SFR_IO8(0x2D) +- +-/* Timer/Counter 1 Control and Status Register */ +-#define TCCR1B _SFR_IO8(0x2E) +- +-/* Timer/Counter 1 Control Register */ +-#define TCCR1A _SFR_IO8(0x2F) +- +-/* Timer/Counter 0 Asynchronous Control & Status Register */ +-#define ASSR _SFR_IO8(0x30) +- +-/* Output Compare Register 0 */ +-#define OCR0 _SFR_IO8(0x31) +- +-/* Timer/Counter 0 */ +-#define TCNT0 _SFR_IO8(0x32) +- +-/* Timer/Counter 0 Control Register */ +-#define TCCR0 _SFR_IO8(0x33) +- +-/* MCU Status Register */ +-#define MCUSR _SFR_IO8(0x34) +- +-/* MCU general Control Register */ +-#define MCUCR _SFR_IO8(0x35) +- +-/* Timer/Counter Interrupt Flag Register */ +-#define TIFR _SFR_IO8(0x36) +- +-/* Timer/Counter Interrupt MaSK register */ +-#define TIMSK _SFR_IO8(0x37) +- +-/* Èxternal Interrupt Flag Register */ +-#define EIFR _SFR_IO8(0x38) +- +-/* External Interrupt MaSK register */ +-#define EIMSK _SFR_IO8(0x39) +- +-/* External Interrupt Control Register */ +-#define EICR _SFR_IO8(0x3A) +- +-/* RAM Page Z select register */ +-#define RAMPZ _SFR_IO8(0x3B) +- +-/* XDIV Divide control register */ +-#define XDIV _SFR_IO8(0x3C) +- +-/* 0x3D..0x3E SP */ +- +-/* 0x3F SREG */ +- +-/* Interrupt vectors */ +- +-/* External Interrupt 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt 1 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +-#define SIG_INTERRUPT1 _VECTOR(2) +- +-/* External Interrupt 2 */ +-#define INT2_vect_num 3 +-#define INT2_vect _VECTOR(3) +-#define SIG_INTERRUPT2 _VECTOR(3) +- +-/* External Interrupt 3 */ +-#define INT3_vect_num 4 +-#define INT3_vect _VECTOR(4) +-#define SIG_INTERRUPT3 _VECTOR(4) +- +-/* External Interrupt 4 */ +-#define INT4_vect_num 5 +-#define INT4_vect _VECTOR(5) +-#define SIG_INTERRUPT4 _VECTOR(5) +- +-/* External Interrupt 5 */ +-#define INT5_vect_num 6 +-#define INT5_vect _VECTOR(6) +-#define SIG_INTERRUPT5 _VECTOR(6) +- +-/* External Interrupt 6 */ +-#define INT6_vect_num 7 +-#define INT6_vect _VECTOR(7) +-#define SIG_INTERRUPT6 _VECTOR(7) +- +-/* External Interrupt 7 */ +-#define INT7_vect_num 8 +-#define INT7_vect _VECTOR(8) +-#define SIG_INTERRUPT7 _VECTOR(8) +- +-/* Timer/Counter2 Compare Match */ +-#define TIMER2_COMP_vect_num 9 +-#define TIMER2_COMP_vect _VECTOR(9) +-#define SIG_OUTPUT_COMPARE2 _VECTOR(9) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 10 +-#define TIMER2_OVF_vect _VECTOR(10) +-#define SIG_OVERFLOW2 _VECTOR(10) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 11 +-#define TIMER1_CAPT_vect _VECTOR(11) +-#define SIG_INPUT_CAPTURE1 _VECTOR(11) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 12 +-#define TIMER1_COMPA_vect _VECTOR(12) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(12) +- +-/* Timer/Counter1 Compare Match B */ +-#define TIMER1_COMPB_vect_num 13 +-#define TIMER1_COMPB_vect _VECTOR(13) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(13) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 14 +-#define TIMER1_OVF_vect _VECTOR(14) +-#define SIG_OVERFLOW1 _VECTOR(14) +- +-/* Timer/Counter0 Compare Match */ +-#define TIMER0_COMP_vect_num 15 +-#define TIMER0_COMP_vect _VECTOR(15) +-#define SIG_OUTPUT_COMPARE0 _VECTOR(15) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 16 +-#define TIMER0_OVF_vect _VECTOR(16) +-#define SIG_OVERFLOW0 _VECTOR(16) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 17 +-#define SPI_STC_vect _VECTOR(17) +-#define SIG_SPI _VECTOR(17) +- +-/* UART, Rx Complete */ +-#define UART_RX_vect_num 18 +-#define UART_RX_vect _VECTOR(18) +-#define SIG_UART_RECV _VECTOR(18) +- +-/* UART Data Register Empty */ +-#define UART_UDRE_vect_num 19 +-#define UART_UDRE_vect _VECTOR(19) +-#define SIG_UART_DATA _VECTOR(19) +- +-/* UART, Tx Complete */ +-#define UART_TX_vect_num 20 +-#define UART_TX_vect _VECTOR(20) +-#define SIG_UART_TRANS _VECTOR(20) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 21 +-#define ADC_vect _VECTOR(21) +-#define SIG_ADC _VECTOR(21) +- +-/* EEPROM Ready */ +-#define EE_READY_vect_num 22 +-#define EE_READY_vect _VECTOR(22) +-#define SIG_EEPROM_READY _VECTOR(22) +- +-/* Analog Comparator */ +-#define ANALOG_COMP_vect_num 23 +-#define ANALOG_COMP_vect _VECTOR(23) +-#define SIG_COMPARATOR _VECTOR(23) +- +-#define _VECTORS_SIZE 96 +- +-/* +- The Register Bit names are represented by their bit number (0-7). +-*/ +- +-/* XDIV Divide control register*/ +-#define XDIVEN 7 +-#define XDIV6 6 +-#define XDIV5 5 +-#define XDIV4 4 +-#define XDIV3 3 +-#define XDIV2 2 +-#define XDIV1 1 +-#define XDIV0 0 +- +-/* RAM Page Z select register */ +-#define RAMPZ0 0 +- +-/* External Interrupt Control Register */ +-#define ISC71 7 +-#define ISC70 6 +-#define ISC61 5 +-#define ISC60 4 +-#define ISC51 3 +-#define ISC50 2 +-#define ISC41 1 +-#define ISC40 0 +- +-/* External Interrupt MaSK register */ +-#define INT7 7 +-#define INT6 6 +-#define INT5 5 +-#define INT4 4 +-#define INT3 3 +-#define INT2 2 +-#define INT1 1 +-#define INT0 0 +- +-/* Èxternal Interrupt Flag Register */ +-#define INTF7 7 +-#define INTF6 6 +-#define INTF5 5 +-#define INTF4 4 +- +-/* Timer/Counter Interrupt MaSK register */ +-#define OCIE2 7 +-#define TOIE2 6 +-#define TICIE1 5 +-#define OCIE1A 4 +-#define OCIE1B 3 +-#define TOIE1 2 +-#define OCIE0 1 +-#define TOIE0 0 +- +-/* Timer/Counter Interrupt Flag Register */ +-#define OCF2 7 +-#define TOV2 6 +-#define ICF1 5 +-#define OCF1A 4 +-#define OCF1B 3 +-#define TOV1 2 +-#define OCF0 1 +-#define TOV0 0 +- +-/* MCU general Control Register */ +-#define SRE 7 +-#define SRW 6 +-#define SE 5 +-#define SM1 4 +-#define SM0 3 +- +-/* MCU Status Register */ +-#define EXTRF 1 +-#define PORF 0 +- +-/* Timer/Counter 0 Control Register */ +-#define PWM0 6 +-#define COM01 5 +-#define COM00 4 +-#define CTC0 3 +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* Timer/Counter 0 Asynchronous Control & Status Register */ +-#define AS0 3 +-#define TCN0UB 2 +-#define OCR0UB 1 +-#define TCR0UB 0 +- +-/* Timer/Counter 1 Control Register */ +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define PWM11 1 +-#define PWM10 0 +- +-/* Timer/Counter 1 Control and Status Register */ +-#define ICNC1 7 +-#define ICES1 6 +-#define CTC1 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* Timer/Counter 2 Control register */ +-#define PWM2 6 +-#define COM21 5 +-#define COM20 4 +-#define CTC2 3 +-#define CS22 2 +-#define CS21 1 +-#define CS20 0 +- +-/* Watchdog Timer Control Register */ +-#define WDTOE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* Data Register, Port A */ +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-/* Data Direction Register, Port A */ +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-/* Input Pins, Port A */ +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-/* Data Register, Port B */ +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* Data Direction Register, Port B */ +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* Input Pins, Port B */ +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* Data Register, Port C */ +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-/* Data Register, Port D */ +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* Data Direction Register, Port D */ +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-/* Input Pins, Port D */ +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-/* Data Register, Port E */ +-#define PE7 7 +-#define PE6 6 +-#define PE5 5 +-#define PE4 4 +-#define PE3 3 +-#define PE2 2 +-#define PE1 1 +-#define PE0 0 +- +-/* Data Direction Register, Port E */ +-#define DDE7 7 +-#define DDE6 6 +-#define DDE5 5 +-#define DDE4 4 +-#define DDE3 3 +-#define DDE2 2 +-#define DDE1 1 +-#define DDE0 0 +- +-/* Input Pins, Port E */ +-#define PINE7 7 +-#define PINE6 6 +-#define PINE5 5 +-#define PINE4 4 +-#define PINE3 3 +-#define PINE2 2 +-#define PINE1 1 +-#define PINE0 0 +- +-/* Input Pins, Port F */ +-#define PINF7 7 +-#define PINF6 6 +-#define PINF5 5 +-#define PINF4 4 +-#define PINF3 3 +-#define PINF2 2 +-#define PINF1 1 +-#define PINF0 0 +- +-/* SPI Status Register */ +-#define SPIF 7 +-#define WCOL 6 +- +-/* SPI Control Register */ +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +-/* UART Status Register */ +-#define RXC 7 +-#define TXC 6 +-#define UDRE 5 +-#define FE 4 +-#define DOR 3 +- +-/* UART Control Register */ +-#define RXCIE 7 +-#define TXCIE 6 +-#define UDRIE 5 +-#define RXEN 4 +-#define TXEN 3 +-#define CHR9 2 +-#define RXB8 1 +-#define TXB8 0 +- +-/* Analog Comparator Control and Status Register */ +-#define ACD 7 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +- +-/* ADC Control and status register */ +-#define ADEN 7 +-#define ADSC 6 +-#define ADFR 5 +-#define ADIF 4 +-#define ADIE 3 +-#define ADPS2 2 +-#define ADPS1 1 +-#define ADPS0 0 +- +-/* ADC Multiplexer select */ +-#define MUX2 2 +-#define MUX1 1 +-#define MUX0 0 +- +-/* EEPROM Control Register */ +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-/* Constants */ +-#define RAMEND 0x0FFF /*Last On-Chip SRAM Location*/ +-#define XRAMEND 0xFFFF +-#define E2END 0x0FFF +-#define E2PAGESIZE 0 +-#define FLASHEND 0x1FFFF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 1 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_BODEN (unsigned char)~_BV(6) /* Brown out detector enable */ +-#define FUSE_BODLEVEL (unsigned char)~_BV(7) /* Brown out detector trigger level */ +-#define LFUSE_DEFAULT (FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x97 +-#define SIGNATURE_2 0x01 +- +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_INTERRUPT1 +-#pragma GCC poison SIG_INTERRUPT2 +-#pragma GCC poison SIG_INTERRUPT3 +-#pragma GCC poison SIG_INTERRUPT4 +-#pragma GCC poison SIG_INTERRUPT5 +-#pragma GCC poison SIG_INTERRUPT6 +-#pragma GCC poison SIG_INTERRUPT7 +-#pragma GCC poison SIG_OUTPUT_COMPARE2 +-#pragma GCC poison SIG_OVERFLOW2 +-#pragma GCC poison SIG_INPUT_CAPTURE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OUTPUT_COMPARE0 +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_SPI +-#pragma GCC poison SIG_UART_RECV +-#pragma GCC poison SIG_UART_DATA +-#pragma GCC poison SIG_UART_TRANS +-#pragma GCC poison SIG_ADC +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_COMPARATOR +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +-#endif /* _AVR_IOM103_H_ */ ++/* Copyright (c) 2002, Marek Michalkiewicz ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom103.h 2227 2011-03-04 19:35:10Z arcanum $ */ ++ ++/* avr/iom103.h - definitions for ATmega103 */ ++ ++#ifndef _AVR_IOM103_H_ ++#define _AVR_IOM103_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom103.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* Input Pins, Port F */ ++#define PINF _SFR_IO8(0x00) ++ ++/* Input Pins, Port E */ ++#define PINE _SFR_IO8(0x01) ++ ++/* Data Direction Register, Port E */ ++#define DDRE _SFR_IO8(0x02) ++ ++/* Data Register, Port E */ ++#define PORTE _SFR_IO8(0x03) ++ ++/* ADC Data Register */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCW _SFR_IO16(0x04) ++#define ADCL _SFR_IO8(0x04) ++#define ADCH _SFR_IO8(0x05) ++ ++/* ADC Control and status register */ ++#define ADCSR _SFR_IO8(0x06) ++ ++/* ADC Multiplexer select */ ++#define ADMUX _SFR_IO8(0x07) ++ ++/* Analog Comparator Control and Status Register */ ++#define ACSR _SFR_IO8(0x08) ++ ++/* UART Baud Rate Register */ ++#define UBRR _SFR_IO8(0x09) ++ ++/* UART Control Register */ ++#define UCR _SFR_IO8(0x0A) ++ ++/* UART Status Register */ ++#define USR _SFR_IO8(0x0B) ++ ++/* UART I/O Data Register */ ++#define UDR _SFR_IO8(0x0C) ++ ++/* SPI Control Register */ ++#define SPCR _SFR_IO8(0x0D) ++ ++/* SPI Status Register */ ++#define SPSR _SFR_IO8(0x0E) ++ ++/* SPI I/O Data Register */ ++#define SPDR _SFR_IO8(0x0F) ++ ++/* Input Pins, Port D */ ++#define PIND _SFR_IO8(0x10) ++ ++/* Data Direction Register, Port D */ ++#define DDRD _SFR_IO8(0x11) ++ ++/* Data Register, Port D */ ++#define PORTD _SFR_IO8(0x12) ++ ++/* Data Register, Port C */ ++#define PORTC _SFR_IO8(0x15) ++ ++/* Input Pins, Port B */ ++#define PINB _SFR_IO8(0x16) ++ ++/* Data Direction Register, Port B */ ++#define DDRB _SFR_IO8(0x17) ++ ++/* Data Register, Port B */ ++#define PORTB _SFR_IO8(0x18) ++ ++/* Input Pins, Port A */ ++#define PINA _SFR_IO8(0x19) ++ ++/* Data Direction Register, Port A */ ++#define DDRA _SFR_IO8(0x1A) ++ ++/* Data Register, Port A */ ++#define PORTA _SFR_IO8(0x1B) ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO16(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++#define EEARH _SFR_IO8(0x1F) ++ ++/* Watchdog Timer Control Register */ ++#define WDTCR _SFR_IO8(0x21) ++ ++/* Timer2 Output Compare Register */ ++#define OCR2 _SFR_IO8(0x23) ++ ++/* Timer/Counter 2 */ ++#define TCNT2 _SFR_IO8(0x24) ++ ++/* Timer/Counter 2 Control register */ ++#define TCCR2 _SFR_IO8(0x25) ++ ++/* T/C 1 Input Capture Register */ ++#define ICR1 _SFR_IO16(0x26) ++#define ICR1L _SFR_IO8(0x26) ++#define ICR1H _SFR_IO8(0x27) ++ ++/* Timer/Counter1 Output Compare Register B */ ++#define OCR1B _SFR_IO16(0x28) ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BH _SFR_IO8(0x29) ++ ++/* Timer/Counter1 Output Compare Register A */ ++#define OCR1A _SFR_IO16(0x2A) ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++ ++/* Timer/Counter 1 */ ++#define TCNT1 _SFR_IO16(0x2C) ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++ ++/* Timer/Counter 1 Control and Status Register */ ++#define TCCR1B _SFR_IO8(0x2E) ++ ++/* Timer/Counter 1 Control Register */ ++#define TCCR1A _SFR_IO8(0x2F) ++ ++/* Timer/Counter 0 Asynchronous Control & Status Register */ ++#define ASSR _SFR_IO8(0x30) ++ ++/* Output Compare Register 0 */ ++#define OCR0 _SFR_IO8(0x31) ++ ++/* Timer/Counter 0 */ ++#define TCNT0 _SFR_IO8(0x32) ++ ++/* Timer/Counter 0 Control Register */ ++#define TCCR0 _SFR_IO8(0x33) ++ ++/* MCU Status Register */ ++#define MCUSR _SFR_IO8(0x34) ++ ++/* MCU general Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++ ++/* Timer/Counter Interrupt Flag Register */ ++#define TIFR _SFR_IO8(0x36) ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define TIMSK _SFR_IO8(0x37) ++ ++/* �xternal Interrupt Flag Register */ ++#define EIFR _SFR_IO8(0x38) ++ ++/* External Interrupt MaSK register */ ++#define EIMSK _SFR_IO8(0x39) ++ ++/* External Interrupt Control Register */ ++#define EICR _SFR_IO8(0x3A) ++ ++/* RAM Page Z select register */ ++#define RAMPZ _SFR_IO8(0x3B) ++ ++/* XDIV Divide control register */ ++#define XDIV _SFR_IO8(0x3C) ++ ++/* 0x3D..0x3E SP */ ++ ++/* 0x3F SREG */ ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt 1 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++#define SIG_INTERRUPT1 _VECTOR(2) ++ ++/* External Interrupt 2 */ ++#define INT2_vect_num 3 ++#define INT2_vect _VECTOR(3) ++#define SIG_INTERRUPT2 _VECTOR(3) ++ ++/* External Interrupt 3 */ ++#define INT3_vect_num 4 ++#define INT3_vect _VECTOR(4) ++#define SIG_INTERRUPT3 _VECTOR(4) ++ ++/* External Interrupt 4 */ ++#define INT4_vect_num 5 ++#define INT4_vect _VECTOR(5) ++#define SIG_INTERRUPT4 _VECTOR(5) ++ ++/* External Interrupt 5 */ ++#define INT5_vect_num 6 ++#define INT5_vect _VECTOR(6) ++#define SIG_INTERRUPT5 _VECTOR(6) ++ ++/* External Interrupt 6 */ ++#define INT6_vect_num 7 ++#define INT6_vect _VECTOR(7) ++#define SIG_INTERRUPT6 _VECTOR(7) ++ ++/* External Interrupt 7 */ ++#define INT7_vect_num 8 ++#define INT7_vect _VECTOR(8) ++#define SIG_INTERRUPT7 _VECTOR(8) ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect_num 9 ++#define TIMER2_COMP_vect _VECTOR(9) ++#define SIG_OUTPUT_COMPARE2 _VECTOR(9) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 10 ++#define TIMER2_OVF_vect _VECTOR(10) ++#define SIG_OVERFLOW2 _VECTOR(10) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 11 ++#define TIMER1_CAPT_vect _VECTOR(11) ++#define SIG_INPUT_CAPTURE1 _VECTOR(11) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 12 ++#define TIMER1_COMPA_vect _VECTOR(12) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(12) ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect_num 13 ++#define TIMER1_COMPB_vect _VECTOR(13) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(13) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 14 ++#define TIMER1_OVF_vect _VECTOR(14) ++#define SIG_OVERFLOW1 _VECTOR(14) ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect_num 15 ++#define TIMER0_COMP_vect _VECTOR(15) ++#define SIG_OUTPUT_COMPARE0 _VECTOR(15) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 16 ++#define TIMER0_OVF_vect _VECTOR(16) ++#define SIG_OVERFLOW0 _VECTOR(16) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 17 ++#define SPI_STC_vect _VECTOR(17) ++#define SIG_SPI _VECTOR(17) ++ ++/* UART, Rx Complete */ ++#define UART_RX_vect_num 18 ++#define UART_RX_vect _VECTOR(18) ++#define SIG_UART_RECV _VECTOR(18) ++ ++/* UART Data Register Empty */ ++#define UART_UDRE_vect_num 19 ++#define UART_UDRE_vect _VECTOR(19) ++#define SIG_UART_DATA _VECTOR(19) ++ ++/* UART, Tx Complete */ ++#define UART_TX_vect_num 20 ++#define UART_TX_vect _VECTOR(20) ++#define SIG_UART_TRANS _VECTOR(20) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 21 ++#define ADC_vect _VECTOR(21) ++#define SIG_ADC _VECTOR(21) ++ ++/* EEPROM Ready */ ++#define EE_READY_vect_num 22 ++#define EE_READY_vect _VECTOR(22) ++#define SIG_EEPROM_READY _VECTOR(22) ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect_num 23 ++#define ANALOG_COMP_vect _VECTOR(23) ++#define SIG_COMPARATOR _VECTOR(23) ++ ++#define _VECTORS_SIZE 96 ++ ++/* ++ The Register Bit names are represented by their bit number (0-7). ++*/ ++ ++/* XDIV Divide control register*/ ++#define XDIVEN 7 ++#define XDIV6 6 ++#define XDIV5 5 ++#define XDIV4 4 ++#define XDIV3 3 ++#define XDIV2 2 ++#define XDIV1 1 ++#define XDIV0 0 ++ ++/* RAM Page Z select register */ ++#define RAMPZ0 0 ++ ++/* External Interrupt Control Register */ ++#define ISC71 7 ++#define ISC70 6 ++#define ISC61 5 ++#define ISC60 4 ++#define ISC51 3 ++#define ISC50 2 ++#define ISC41 1 ++#define ISC40 0 ++ ++/* External Interrupt MaSK register */ ++#define INT7 7 ++#define INT6 6 ++#define INT5 5 ++#define INT4 4 ++#define INT3 3 ++#define INT2 2 ++#define INT1 1 ++#define INT0 0 ++ ++/* �xternal Interrupt Flag Register */ ++#define INTF7 7 ++#define INTF6 6 ++#define INTF5 5 ++#define INTF4 4 ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define OCIE2 7 ++#define TOIE2 6 ++#define TICIE1 5 ++#define OCIE1A 4 ++#define OCIE1B 3 ++#define TOIE1 2 ++#define OCIE0 1 ++#define TOIE0 0 ++ ++/* Timer/Counter Interrupt Flag Register */ ++#define OCF2 7 ++#define TOV2 6 ++#define ICF1 5 ++#define OCF1A 4 ++#define OCF1B 3 ++#define TOV1 2 ++#define OCF0 1 ++#define TOV0 0 ++ ++/* MCU general Control Register */ ++#define SRE 7 ++#define SRW 6 ++#define SE 5 ++#define SM1 4 ++#define SM0 3 ++ ++/* MCU Status Register */ ++#define EXTRF 1 ++#define PORF 0 ++ ++/* Timer/Counter 0 Control Register */ ++#define PWM0 6 ++#define COM01 5 ++#define COM00 4 ++#define CTC0 3 ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* Timer/Counter 0 Asynchronous Control & Status Register */ ++#define AS0 3 ++#define TCN0UB 2 ++#define OCR0UB 1 ++#define TCR0UB 0 ++ ++/* Timer/Counter 1 Control Register */ ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define PWM11 1 ++#define PWM10 0 ++ ++/* Timer/Counter 1 Control and Status Register */ ++#define ICNC1 7 ++#define ICES1 6 ++#define CTC1 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* Timer/Counter 2 Control register */ ++#define PWM2 6 ++#define COM21 5 ++#define COM20 4 ++#define CTC2 3 ++#define CS22 2 ++#define CS21 1 ++#define CS20 0 ++ ++/* Watchdog Timer Control Register */ ++#define WDTOE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* Data Register, Port A */ ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++/* Data Direction Register, Port A */ ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++/* Input Pins, Port A */ ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++/* Data Register, Port B */ ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* Data Direction Register, Port B */ ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* Input Pins, Port B */ ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* Data Register, Port C */ ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++/* Data Register, Port D */ ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* Data Direction Register, Port D */ ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++/* Input Pins, Port D */ ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++/* Data Register, Port E */ ++#define PE7 7 ++#define PE6 6 ++#define PE5 5 ++#define PE4 4 ++#define PE3 3 ++#define PE2 2 ++#define PE1 1 ++#define PE0 0 ++ ++/* Data Direction Register, Port E */ ++#define DDE7 7 ++#define DDE6 6 ++#define DDE5 5 ++#define DDE4 4 ++#define DDE3 3 ++#define DDE2 2 ++#define DDE1 1 ++#define DDE0 0 ++ ++/* Input Pins, Port E */ ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++/* Input Pins, Port F */ ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++/* SPI Status Register */ ++#define SPIF 7 ++#define WCOL 6 ++ ++/* SPI Control Register */ ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++/* UART Status Register */ ++#define RXC 7 ++#define TXC 6 ++#define UDRE 5 ++#define FE 4 ++#define DOR 3 ++ ++/* UART Control Register */ ++#define RXCIE 7 ++#define TXCIE 6 ++#define UDRIE 5 ++#define RXEN 4 ++#define TXEN 3 ++#define CHR9 2 ++#define RXB8 1 ++#define TXB8 0 ++ ++/* Analog Comparator Control and Status Register */ ++#define ACD 7 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++/* ADC Control and status register */ ++#define ADEN 7 ++#define ADSC 6 ++#define ADFR 5 ++#define ADIF 4 ++#define ADIE 3 ++#define ADPS2 2 ++#define ADPS1 1 ++#define ADPS0 0 ++ ++/* ADC Multiplexer select */ ++#define MUX2 2 ++#define MUX1 1 ++#define MUX0 0 ++ ++/* EEPROM Control Register */ ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++/* Constants */ ++#define RAMSTART 0x60 ++#define RAMEND 0x0FFF /*Last On-Chip SRAM Location*/ ++#define XRAMEND 0xFFFF ++#define E2END 0x0FFF ++#define E2PAGESIZE 0 ++#define FLASHEND 0x1FFFF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_BODEN (unsigned char)~_BV(6) /* Brown out detector enable */ ++#define FUSE_BODLEVEL (unsigned char)~_BV(7) /* Brown out detector trigger level */ ++#define LFUSE_DEFAULT (FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x97 ++#define SIGNATURE_2 0x01 ++ ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_INTERRUPT1 ++#pragma GCC poison SIG_INTERRUPT2 ++#pragma GCC poison SIG_INTERRUPT3 ++#pragma GCC poison SIG_INTERRUPT4 ++#pragma GCC poison SIG_INTERRUPT5 ++#pragma GCC poison SIG_INTERRUPT6 ++#pragma GCC poison SIG_INTERRUPT7 ++#pragma GCC poison SIG_OUTPUT_COMPARE2 ++#pragma GCC poison SIG_OVERFLOW2 ++#pragma GCC poison SIG_INPUT_CAPTURE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OUTPUT_COMPARE0 ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_SPI ++#pragma GCC poison SIG_UART_RECV ++#pragma GCC poison SIG_UART_DATA ++#pragma GCC poison SIG_UART_TRANS ++#pragma GCC poison SIG_ADC ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_COMPARATOR ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++#endif /* _AVR_IOM103_H_ */ +diff --git a/include/avr/iom128.h b/include/avr/iom128.h +index 7eac0e0..7b6e3d4 100644 +--- a/include/avr/iom128.h ++++ b/include/avr/iom128.h +@@ -1,1294 +1,1295 @@ +-/* Copyright (c) 2002, Peter Jansen +- Copyright (c) 2007, Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom128.h 2226 2011-03-04 17:47:16Z arcanum $ */ +- +-/* avr/iom128.h - defines for ATmega128 +- +- As of 2002-08-27: +- - This should be up to date with data sheet 2467E-AVR-05/02 */ +- +-#ifndef _AVR_IOM128_H_ +-#define _AVR_IOM128_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom128.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* Input Pins, Port F */ +-#define PINF _SFR_IO8(0x00) +- +-/* Input Pins, Port E */ +-#define PINE _SFR_IO8(0x01) +- +-/* Data Direction Register, Port E */ +-#define DDRE _SFR_IO8(0x02) +- +-/* Data Register, Port E */ +-#define PORTE _SFR_IO8(0x03) +- +-/* ADC Data Register */ +-#define ADCW _SFR_IO16(0x04) /* for backwards compatibility */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x04) +-#endif +-#define ADCL _SFR_IO8(0x04) +-#define ADCH _SFR_IO8(0x05) +- +-/* ADC Control and status register */ +-#define ADCSR _SFR_IO8(0x06) +-#define ADCSRA _SFR_IO8(0x06) /* new name in datasheet (2467E-AVR-05/02) */ +- +-/* ADC Multiplexer select */ +-#define ADMUX _SFR_IO8(0x07) +- +-/* Analog Comparator Control and Status Register */ +-#define ACSR _SFR_IO8(0x08) +- +-/* USART0 Baud Rate Register Low */ +-#define UBRR0L _SFR_IO8(0x09) +- +-/* USART0 Control and Status Register B */ +-#define UCSR0B _SFR_IO8(0x0A) +- +-/* USART0 Control and Status Register A */ +-#define UCSR0A _SFR_IO8(0x0B) +- +-/* USART0 I/O Data Register */ +-#define UDR0 _SFR_IO8(0x0C) +- +-/* SPI Control Register */ +-#define SPCR _SFR_IO8(0x0D) +- +-/* SPI Status Register */ +-#define SPSR _SFR_IO8(0x0E) +- +-/* SPI I/O Data Register */ +-#define SPDR _SFR_IO8(0x0F) +- +-/* Input Pins, Port D */ +-#define PIND _SFR_IO8(0x10) +- +-/* Data Direction Register, Port D */ +-#define DDRD _SFR_IO8(0x11) +- +-/* Data Register, Port D */ +-#define PORTD _SFR_IO8(0x12) +- +-/* Input Pins, Port C */ +-#define PINC _SFR_IO8(0x13) +- +-/* Data Direction Register, Port C */ +-#define DDRC _SFR_IO8(0x14) +- +-/* Data Register, Port C */ +-#define PORTC _SFR_IO8(0x15) +- +-/* Input Pins, Port B */ +-#define PINB _SFR_IO8(0x16) +- +-/* Data Direction Register, Port B */ +-#define DDRB _SFR_IO8(0x17) +- +-/* Data Register, Port B */ +-#define PORTB _SFR_IO8(0x18) +- +-/* Input Pins, Port A */ +-#define PINA _SFR_IO8(0x19) +- +-/* Data Direction Register, Port A */ +-#define DDRA _SFR_IO8(0x1A) +- +-/* Data Register, Port A */ +-#define PORTA _SFR_IO8(0x1B) +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO16(0x1E) +-#define EEARL _SFR_IO8(0x1E) +-#define EEARH _SFR_IO8(0x1F) +- +-/* Special Function I/O Register */ +-#define SFIOR _SFR_IO8(0x20) +- +-/* Watchdog Timer Control Register */ +-#define WDTCR _SFR_IO8(0x21) +- +-/* On-chip Debug Register */ +-#define OCDR _SFR_IO8(0x22) +- +-/* Timer2 Output Compare Register */ +-#define OCR2 _SFR_IO8(0x23) +- +-/* Timer/Counter 2 */ +-#define TCNT2 _SFR_IO8(0x24) +- +-/* Timer/Counter 2 Control register */ +-#define TCCR2 _SFR_IO8(0x25) +- +-/* T/C 1 Input Capture Register */ +-#define ICR1 _SFR_IO16(0x26) +-#define ICR1L _SFR_IO8(0x26) +-#define ICR1H _SFR_IO8(0x27) +- +-/* Timer/Counter1 Output Compare Register B */ +-#define OCR1B _SFR_IO16(0x28) +-#define OCR1BL _SFR_IO8(0x28) +-#define OCR1BH _SFR_IO8(0x29) +- +-/* Timer/Counter1 Output Compare Register A */ +-#define OCR1A _SFR_IO16(0x2A) +-#define OCR1AL _SFR_IO8(0x2A) +-#define OCR1AH _SFR_IO8(0x2B) +- +-/* Timer/Counter 1 */ +-#define TCNT1 _SFR_IO16(0x2C) +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1H _SFR_IO8(0x2D) +- +-/* Timer/Counter 1 Control and Status Register */ +-#define TCCR1B _SFR_IO8(0x2E) +- +-/* Timer/Counter 1 Control Register */ +-#define TCCR1A _SFR_IO8(0x2F) +- +-/* Timer/Counter 0 Asynchronous Control & Status Register */ +-#define ASSR _SFR_IO8(0x30) +- +-/* Output Compare Register 0 */ +-#define OCR0 _SFR_IO8(0x31) +- +-/* Timer/Counter 0 */ +-#define TCNT0 _SFR_IO8(0x32) +- +-/* Timer/Counter 0 Control Register */ +-#define TCCR0 _SFR_IO8(0x33) +- +-/* MCU Status Register */ +-#define MCUSR _SFR_IO8(0x34) +-#define MCUCSR _SFR_IO8(0x34) /* new name in datasheet (2467E-AVR-05/02) */ +- +-/* MCU general Control Register */ +-#define MCUCR _SFR_IO8(0x35) +- +-/* Timer/Counter Interrupt Flag Register */ +-#define TIFR _SFR_IO8(0x36) +- +-/* Timer/Counter Interrupt MaSK register */ +-#define TIMSK _SFR_IO8(0x37) +- +-/* External Interrupt Flag Register */ +-#define EIFR _SFR_IO8(0x38) +- +-/* External Interrupt MaSK register */ +-#define EIMSK _SFR_IO8(0x39) +- +-/* External Interrupt Control Register B */ +-#define EICRB _SFR_IO8(0x3A) +- +-/* RAM Page Z select register */ +-#define RAMPZ _SFR_IO8(0x3B) +- +-/* XDIV Divide control register */ +-#define XDIV _SFR_IO8(0x3C) +- +-/* 0x3D..0x3E SP */ +- +-/* 0x3F SREG */ +- +-/* Extended I/O registers */ +- +-/* Data Direction Register, Port F */ +-#define DDRF _SFR_MEM8(0x61) +- +-/* Data Register, Port F */ +-#define PORTF _SFR_MEM8(0x62) +- +-/* Input Pins, Port G */ +-#define PING _SFR_MEM8(0x63) +- +-/* Data Direction Register, Port G */ +-#define DDRG _SFR_MEM8(0x64) +- +-/* Data Register, Port G */ +-#define PORTG _SFR_MEM8(0x65) +- +-/* Store Program Memory Control and Status Register */ +-#define SPMCR _SFR_MEM8(0x68) +-#define SPMCSR _SFR_MEM8(0x68) /* new name in datasheet (2467E-AVR-05/02) */ +- +-/* External Interrupt Control Register A */ +-#define EICRA _SFR_MEM8(0x6A) +- +-/* External Memory Control Register B */ +-#define XMCRB _SFR_MEM8(0x6C) +- +-/* External Memory Control Register A */ +-#define XMCRA _SFR_MEM8(0x6D) +- +-/* Oscillator Calibration Register */ +-#define OSCCAL _SFR_MEM8(0x6F) +- +-/* 2-wire Serial Interface Bit Rate Register */ +-#define TWBR _SFR_MEM8(0x70) +- +-/* 2-wire Serial Interface Status Register */ +-#define TWSR _SFR_MEM8(0x71) +- +-/* 2-wire Serial Interface Address Register */ +-#define TWAR _SFR_MEM8(0x72) +- +-/* 2-wire Serial Interface Data Register */ +-#define TWDR _SFR_MEM8(0x73) +- +-/* 2-wire Serial Interface Control Register */ +-#define TWCR _SFR_MEM8(0x74) +- +-/* Time Counter 1 Output Compare Register C */ +-#define OCR1C _SFR_MEM16(0x78) +-#define OCR1CL _SFR_MEM8(0x78) +-#define OCR1CH _SFR_MEM8(0x79) +- +-/* Timer/Counter 1 Control Register C */ +-#define TCCR1C _SFR_MEM8(0x7A) +- +-/* Extended Timer Interrupt Flag Register */ +-#define ETIFR _SFR_MEM8(0x7C) +- +-/* Extended Timer Interrupt Mask Register */ +-#define ETIMSK _SFR_MEM8(0x7D) +- +-/* Timer/Counter 3 Input Capture Register */ +-#define ICR3 _SFR_MEM16(0x80) +-#define ICR3L _SFR_MEM8(0x80) +-#define ICR3H _SFR_MEM8(0x81) +- +-/* Timer/Counter 3 Output Compare Register C */ +-#define OCR3C _SFR_MEM16(0x82) +-#define OCR3CL _SFR_MEM8(0x82) +-#define OCR3CH _SFR_MEM8(0x83) +- +-/* Timer/Counter 3 Output Compare Register B */ +-#define OCR3B _SFR_MEM16(0x84) +-#define OCR3BL _SFR_MEM8(0x84) +-#define OCR3BH _SFR_MEM8(0x85) +- +-/* Timer/Counter 3 Output Compare Register A */ +-#define OCR3A _SFR_MEM16(0x86) +-#define OCR3AL _SFR_MEM8(0x86) +-#define OCR3AH _SFR_MEM8(0x87) +- +-/* Timer/Counter 3 Counter Register */ +-#define TCNT3 _SFR_MEM16(0x88) +-#define TCNT3L _SFR_MEM8(0x88) +-#define TCNT3H _SFR_MEM8(0x89) +- +-/* Timer/Counter 3 Control Register B */ +-#define TCCR3B _SFR_MEM8(0x8A) +- +-/* Timer/Counter 3 Control Register A */ +-#define TCCR3A _SFR_MEM8(0x8B) +- +-/* Timer/Counter 3 Control Register C */ +-#define TCCR3C _SFR_MEM8(0x8C) +- +-/* USART0 Baud Rate Register High */ +-#define UBRR0H _SFR_MEM8(0x90) +- +-/* USART0 Control and Status Register C */ +-#define UCSR0C _SFR_MEM8(0x95) +- +-/* USART1 Baud Rate Register High */ +-#define UBRR1H _SFR_MEM8(0x98) +- +-/* USART1 Baud Rate Register Low*/ +-#define UBRR1L _SFR_MEM8(0x99) +- +-/* USART1 Control and Status Register B */ +-#define UCSR1B _SFR_MEM8(0x9A) +- +-/* USART1 Control and Status Register A */ +-#define UCSR1A _SFR_MEM8(0x9B) +- +-/* USART1 I/O Data Register */ +-#define UDR1 _SFR_MEM8(0x9C) +- +-/* USART1 Control and Status Register C */ +-#define UCSR1C _SFR_MEM8(0x9D) +- +-/* Interrupt vectors */ +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt Request 1 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +-#define SIG_INTERRUPT1 _VECTOR(2) +- +-/* External Interrupt Request 2 */ +-#define INT2_vect_num 3 +-#define INT2_vect _VECTOR(3) +-#define SIG_INTERRUPT2 _VECTOR(3) +- +-/* External Interrupt Request 3 */ +-#define INT3_vect_num 4 +-#define INT3_vect _VECTOR(4) +-#define SIG_INTERRUPT3 _VECTOR(4) +- +-/* External Interrupt Request 4 */ +-#define INT4_vect_num 5 +-#define INT4_vect _VECTOR(5) +-#define SIG_INTERRUPT4 _VECTOR(5) +- +-/* External Interrupt Request 5 */ +-#define INT5_vect_num 6 +-#define INT5_vect _VECTOR(6) +-#define SIG_INTERRUPT5 _VECTOR(6) +- +-/* External Interrupt Request 6 */ +-#define INT6_vect_num 7 +-#define INT6_vect _VECTOR(7) +-#define SIG_INTERRUPT6 _VECTOR(7) +- +-/* External Interrupt Request 7 */ +-#define INT7_vect_num 8 +-#define INT7_vect _VECTOR(8) +-#define SIG_INTERRUPT7 _VECTOR(8) +- +-/* Timer/Counter2 Compare Match */ +-#define TIMER2_COMP_vect_num 9 +-#define TIMER2_COMP_vect _VECTOR(9) +-#define SIG_OUTPUT_COMPARE2 _VECTOR(9) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 10 +-#define TIMER2_OVF_vect _VECTOR(10) +-#define SIG_OVERFLOW2 _VECTOR(10) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 11 +-#define TIMER1_CAPT_vect _VECTOR(11) +-#define SIG_INPUT_CAPTURE1 _VECTOR(11) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 12 +-#define TIMER1_COMPA_vect _VECTOR(12) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(12) +- +-/* Timer/Counter Compare Match B */ +-#define TIMER1_COMPB_vect_num 13 +-#define TIMER1_COMPB_vect _VECTOR(13) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(13) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 14 +-#define TIMER1_OVF_vect _VECTOR(14) +-#define SIG_OVERFLOW1 _VECTOR(14) +- +-/* Timer/Counter0 Compare Match */ +-#define TIMER0_COMP_vect_num 15 +-#define TIMER0_COMP_vect _VECTOR(15) +-#define SIG_OUTPUT_COMPARE0 _VECTOR(15) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 16 +-#define TIMER0_OVF_vect _VECTOR(16) +-#define SIG_OVERFLOW0 _VECTOR(16) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 17 +-#define SPI_STC_vect _VECTOR(17) +-#define SIG_SPI _VECTOR(17) +- +-/* USART0, Rx Complete */ +-#define USART0_RX_vect_num 18 +-#define USART0_RX_vect _VECTOR(18) +-#define SIG_USART0_RECV _VECTOR(18) +-#define SIG_UART0_RECV _VECTOR(18) +- +-/* USART0 Data Register Empty */ +-#define USART0_UDRE_vect_num 19 +-#define USART0_UDRE_vect _VECTOR(19) +-#define SIG_USART0_DATA _VECTOR(19) +-#define SIG_UART0_DATA _VECTOR(19) +- +-/* USART0, Tx Complete */ +-#define USART0_TX_vect_num 20 +-#define USART0_TX_vect _VECTOR(20) +-#define SIG_USART0_TRANS _VECTOR(20) +-#define SIG_UART0_TRANS _VECTOR(20) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 21 +-#define ADC_vect _VECTOR(21) +-#define SIG_ADC _VECTOR(21) +- +-/* EEPROM Ready */ +-#define EE_READY_vect _VECTOR(22) +-#define EE_READY_vect _VECTOR(22) +-#define SIG_EEPROM_READY _VECTOR(22) +- +-/* Analog Comparator */ +-#define ANALOG_COMP_vect_num 23 +-#define ANALOG_COMP_vect _VECTOR(23) +-#define SIG_COMPARATOR _VECTOR(23) +- +-/* Timer/Counter1 Compare Match C */ +-#define TIMER1_COMPC_vect_num 24 +-#define TIMER1_COMPC_vect _VECTOR(24) +-#define SIG_OUTPUT_COMPARE1C _VECTOR(24) +- +-/* Timer/Counter3 Capture Event */ +-#define TIMER3_CAPT_vect_num 25 +-#define TIMER3_CAPT_vect _VECTOR(25) +-#define SIG_INPUT_CAPTURE3 _VECTOR(25) +- +-/* Timer/Counter3 Compare Match A */ +-#define TIMER3_COMPA_vect_num 26 +-#define TIMER3_COMPA_vect _VECTOR(26) +-#define SIG_OUTPUT_COMPARE3A _VECTOR(26) +- +-/* Timer/Counter3 Compare Match B */ +-#define TIMER3_COMPB_vect_num 27 +-#define TIMER3_COMPB_vect _VECTOR(27) +-#define SIG_OUTPUT_COMPARE3B _VECTOR(27) +- +-/* Timer/Counter3 Compare Match C */ +-#define TIMER3_COMPC_vect_num 28 +-#define TIMER3_COMPC_vect _VECTOR(28) +-#define SIG_OUTPUT_COMPARE3C _VECTOR(28) +- +-/* Timer/Counter3 Overflow */ +-#define TIMER3_OVF_vect_num 29 +-#define TIMER3_OVF_vect _VECTOR(29) +-#define SIG_OVERFLOW3 _VECTOR(29) +- +-/* USART1, Rx Complete */ +-#define USART1_RX_vect_num 30 +-#define USART1_RX_vect _VECTOR(30) +-#define SIG_USART1_RECV _VECTOR(30) +-#define SIG_UART1_RECV _VECTOR(30) +- +-/* USART1, Data Register Empty */ +-#define USART1_UDRE_vect_num 31 +-#define USART1_UDRE_vect _VECTOR(31) +-#define SIG_USART1_DATA _VECTOR(31) +-#define SIG_UART1_DATA _VECTOR(31) +- +-/* USART1, Tx Complete */ +-#define USART1_TX_vect_num 32 +-#define USART1_TX_vect _VECTOR(32) +-#define SIG_USART1_TRANS _VECTOR(32) +-#define SIG_UART1_TRANS _VECTOR(32) +- +-/* 2-wire Serial Interface */ +-#define TWI_vect_num 33 +-#define TWI_vect _VECTOR(33) +-#define SIG_2WIRE_SERIAL _VECTOR(33) +- +-/* Store Program Memory Read */ +-#define SPM_READY_vect_num 34 +-#define SPM_READY_vect _VECTOR(34) +-#define SPM_READY_vect _VECTOR(34) +-#define SIG_SPM_READY _VECTOR(34) +- +-#define _VECTORS_SIZE 140 +- +-/* +- The Register Bit names are represented by their bit number (0-7). +-*/ +- +-/* 2-wire Control Register - TWCR */ +-#define TWINT 7 +-#define TWEA 6 +-#define TWSTA 5 +-#define TWSTO 4 +-#define TWWC 3 +-#define TWEN 2 +-#define TWIE 0 +- +-/* 2-wire Address Register - TWAR */ +-#define TWA6 7 +-#define TWA5 6 +-#define TWA4 5 +-#define TWA3 4 +-#define TWA2 3 +-#define TWA1 2 +-#define TWA0 1 +-#define TWGCE 0 +- +-/* 2-wire Status Register - TWSR */ +-#define TWS7 7 +-#define TWS6 6 +-#define TWS5 5 +-#define TWS4 4 +-#define TWS3 3 +-#define TWPS1 1 +-#define TWPS0 0 +- +-/* External Memory Control Register A - XMCRA */ +-#define SRL2 6 +-#define SRL1 5 +-#define SRL0 4 +-#define SRW01 3 +-#define SRW00 2 +-#define SRW11 1 +- +-/* External Memory Control Register B - XMCRA */ +-#define XMBK 7 +-#define XMM2 2 +-#define XMM1 1 +-#define XMM0 0 +- +-/* XDIV Divide control register - XDIV */ +-#define XDIVEN 7 +-#define XDIV6 6 +-#define XDIV5 5 +-#define XDIV4 4 +-#define XDIV3 3 +-#define XDIV2 2 +-#define XDIV1 1 +-#define XDIV0 0 +- +-/* RAM Page Z select register - RAMPZ */ +-#define RAMPZ0 0 +- +-/* External Interrupt Control Register A - EICRA */ +-#define ISC31 7 +-#define ISC30 6 +-#define ISC21 5 +-#define ISC20 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-/* External Interrupt Control Register B - EICRB */ +-#define ISC71 7 +-#define ISC70 6 +-#define ISC61 5 +-#define ISC60 4 +-#define ISC51 3 +-#define ISC50 2 +-#define ISC41 1 +-#define ISC40 0 +- +-/* Store Program Memory Control Register - SPMCSR, SPMCR */ +-#define SPMIE 7 +-#define RWWSB 6 +-#define RWWSRE 4 +-#define BLBSET 3 +-#define PGWRT 2 +-#define PGERS 1 +-#define SPMEN 0 +- +-/* External Interrupt MaSK register - EIMSK */ +-#define INT7 7 +-#define INT6 6 +-#define INT5 5 +-#define INT4 4 +-#define INT3 3 +-#define INT2 2 +-#define INT1 1 +-#define INT0 0 +- +-/* External Interrupt Flag Register - EIFR */ +-#define INTF7 7 +-#define INTF6 6 +-#define INTF5 5 +-#define INTF4 4 +-#define INTF3 3 +-#define INTF2 2 +-#define INTF1 1 +-#define INTF0 0 +- +-/* Timer/Counter Interrupt MaSK register - TIMSK */ +-#define OCIE2 7 +-#define TOIE2 6 +-#define TICIE1 5 +-#define OCIE1A 4 +-#define OCIE1B 3 +-#define TOIE1 2 +-#define OCIE0 1 +-#define TOIE0 0 +- +-/* Timer/Counter Interrupt Flag Register - TIFR */ +-#define OCF2 7 +-#define TOV2 6 +-#define ICF1 5 +-#define OCF1A 4 +-#define OCF1B 3 +-#define TOV1 2 +-#define OCF0 1 +-#define TOV0 0 +- +-/* Extended Timer Interrupt MaSK register - ETIMSK */ +-#define TICIE3 5 +-#define OCIE3A 4 +-#define OCIE3B 3 +-#define TOIE3 2 +-#define OCIE3C 1 +-#define OCIE1C 0 +- +-/* Extended Timer Interrupt Flag Register - ETIFR */ +-#define ICF3 5 +-#define OCF3A 4 +-#define OCF3B 3 +-#define TOV3 2 +-#define OCF3C 1 +-#define OCF1C 0 +- +-/* MCU general Control Register - MCUCR */ +-#define SRE 7 +-#define SRW 6 +-#define SRW10 6 /* new name in datasheet (2467E-AVR-05/02) */ +-#define SE 5 +-#define SM1 4 +-#define SM0 3 +-#define SM2 2 +-#define IVSEL 1 +-#define IVCE 0 +- +-/* MCU Status Register - MCUSR, MCUCSR */ +-#define JTD 7 +-#define JTRF 4 +-#define WDRF 3 +-#define BORF 2 +-#define EXTRF 1 +-#define PORF 0 +- +-/* Timer/Counter Control Register (generic) */ +-#define FOC 7 +-#define WGM0 6 +-#define COM1 5 +-#define COM0 4 +-#define WGM1 3 +-#define CS2 2 +-#define CS1 1 +-#define CS0 0 +- +-/* Timer/Counter 0 Control Register - TCCR0 */ +-#define FOC0 7 +-#define WGM00 6 +-#define COM01 5 +-#define COM00 4 +-#define WGM01 3 +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* Timer/Counter 2 Control Register - TCCR2 */ +-#define FOC2 7 +-#define WGM20 6 +-#define COM21 5 +-#define COM20 4 +-#define WGM21 3 +-#define CS22 2 +-#define CS21 1 +-#define CS20 0 +- +-/* Timer/Counter 0 Asynchronous Control & Status Register - ASSR */ +-#define AS0 3 +-#define TCN0UB 2 +-#define OCR0UB 1 +-#define TCR0UB 0 +- +-/* Timer/Counter Control Register A (generic) */ +-#define COMA1 7 +-#define COMA0 6 +-#define COMB1 5 +-#define COMB0 4 +-#define COMC1 3 +-#define COMC0 2 +-#define WGMA1 1 +-#define WGMA0 0 +- +-/* Timer/Counter 1 Control and Status Register A - TCCR1A */ +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define COM1C1 3 +-#define COM1C0 2 +-#define WGM11 1 +-#define WGM10 0 +- +-/* Timer/Counter 3 Control and Status Register A - TCCR3A */ +-#define COM3A1 7 +-#define COM3A0 6 +-#define COM3B1 5 +-#define COM3B0 4 +-#define COM3C1 3 +-#define COM3C0 2 +-#define WGM31 1 +-#define WGM30 0 +- +-/* Timer/Counter Control and Status Register B (generic) */ +-#define ICNC 7 +-#define ICES 6 +-#define WGMB3 4 +-#define WGMB2 3 +-#define CSB2 2 +-#define CSB1 1 +-#define CSB0 0 +- +-/* Timer/Counter 1 Control and Status Register B - TCCR1B */ +-#define ICNC1 7 +-#define ICES1 6 +-#define WGM13 4 +-#define WGM12 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* Timer/Counter 3 Control and Status Register B - TCCR3B */ +-#define ICNC3 7 +-#define ICES3 6 +-#define WGM33 4 +-#define WGM32 3 +-#define CS32 2 +-#define CS31 1 +-#define CS30 0 +- +-/* Timer/Counter Control Register C (generic) */ +-#define FOCA 7 +-#define FOCB 6 +-#define FOCC 5 +- +-/* Timer/Counter 3 Control Register C - TCCR3C */ +-#define FOC3A 7 +-#define FOC3B 6 +-#define FOC3C 5 +- +-/* Timer/Counter 1 Control Register C - TCCR1C */ +-#define FOC1A 7 +-#define FOC1B 6 +-#define FOC1C 5 +- +-/* On-chip Debug Register - OCDR */ +-#define IDRD 7 +-#define OCDR7 7 +-#define OCDR6 6 +-#define OCDR5 5 +-#define OCDR4 4 +-#define OCDR3 3 +-#define OCDR2 2 +-#define OCDR1 1 +-#define OCDR0 0 +- +-/* Watchdog Timer Control Register - WDTCR */ +-#define WDCE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* +- The ADHSM bit has been removed from all documentation, +- as being not needed at all since the comparator has proven +- to be fast enough even without feeding it more power. +-*/ +- +-/* Special Function I/O Register - SFIOR */ +-#define TSM 7 +-#define ACME 3 +-#define PUD 2 +-#define PSR0 1 +-#define PSR321 0 +- +-/* SPI Status Register - SPSR */ +-#define SPIF 7 +-#define WCOL 6 +-#define SPI2X 0 +- +-/* SPI Control Register - SPCR */ +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +-/* USART Register C (generic) */ +-#define UMSEL 6 +-#define UPM1 5 +-#define UPM0 4 +-#define USBS 3 +-#define UCSZ1 2 +-#define UCSZ0 1 +-#define UCPOL 0 +- +-/* USART1 Register C - UCSR1C */ +-#define UMSEL1 6 +-#define UPM11 5 +-#define UPM10 4 +-#define USBS1 3 +-#define UCSZ11 2 +-#define UCSZ10 1 +-#define UCPOL1 0 +- +-/* USART0 Register C - UCSR0C */ +-#define UMSEL0 6 +-#define UPM01 5 +-#define UPM00 4 +-#define USBS0 3 +-#define UCSZ01 2 +-#define UCSZ00 1 +-#define UCPOL0 0 +- +-/* USART Status Register A (generic) */ +-#define RXC 7 +-#define TXC 6 +-#define UDRE 5 +-#define FE 4 +-#define DOR 3 +-#define UPE 2 +-#define U2X 1 +-#define MPCM 0 +- +-/* USART1 Status Register A - UCSR1A */ +-#define RXC1 7 +-#define TXC1 6 +-#define UDRE1 5 +-#define FE1 4 +-#define DOR1 3 +-#define UPE1 2 +-#define U2X1 1 +-#define MPCM1 0 +- +-/* USART0 Status Register A - UCSR0A */ +-#define RXC0 7 +-#define TXC0 6 +-#define UDRE0 5 +-#define FE0 4 +-#define DOR0 3 +-#define UPE0 2 +-#define U2X0 1 +-#define MPCM0 0 +- +-/* USART Control Register B (generic) */ +-#define RXCIE 7 +-#define TXCIE 6 +-#define UDRIE 5 +-#define RXEN 4 +-#define TXEN 3 +-#define UCSZ 2 +-#define UCSZ2 2 /* new name in datasheet (2467E-AVR-05/02) */ +-#define RXB8 1 +-#define TXB8 0 +- +-/* USART1 Control Register B - UCSR1B */ +-#define RXCIE1 7 +-#define TXCIE1 6 +-#define UDRIE1 5 +-#define RXEN1 4 +-#define TXEN1 3 +-#define UCSZ12 2 +-#define RXB81 1 +-#define TXB81 0 +- +-/* USART0 Control Register B - UCSR0B */ +-#define RXCIE0 7 +-#define TXCIE0 6 +-#define UDRIE0 5 +-#define RXEN0 4 +-#define TXEN0 3 +-#define UCSZ02 2 +-#define RXB80 1 +-#define TXB80 0 +- +-/* Analog Comparator Control and Status Register - ACSR */ +-#define ACD 7 +-#define ACBG 6 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +- +-/* ADC Control and status register - ADCSRA */ +-#define ADEN 7 +-#define ADSC 6 +-#define ADFR 5 +-#define ADIF 4 +-#define ADIE 3 +-#define ADPS2 2 +-#define ADPS1 1 +-#define ADPS0 0 +- +-/* ADC Multiplexer select - ADMUX */ +-#define REFS1 7 +-#define REFS0 6 +-#define ADLAR 5 +-#define MUX4 4 +-#define MUX3 3 +-#define MUX2 2 +-#define MUX1 1 +-#define MUX0 0 +- +-/* Port A Data Register - PORTA */ +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-/* Port A Data Direction Register - DDRA */ +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-/* Port A Input Pins - PINA */ +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-/* Port B Data Register - PORTB */ +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* Port B Data Direction Register - DDRB */ +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* Port B Input Pins - PINB */ +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* Port C Data Register - PORTC */ +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-/* Port C Data Direction Register - DDRC */ +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-/* Port C Input Pins - PINC */ +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-/* Port D Data Register - PORTD */ +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* Port D Data Direction Register - DDRD */ +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-/* Port D Input Pins - PIND */ +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-/* Port E Data Register - PORTE */ +-#define PE7 7 +-#define PE6 6 +-#define PE5 5 +-#define PE4 4 +-#define PE3 3 +-#define PE2 2 +-#define PE1 1 +-#define PE0 0 +- +-/* Port E Data Direction Register - DDRE */ +-#define DDE7 7 +-#define DDE6 6 +-#define DDE5 5 +-#define DDE4 4 +-#define DDE3 3 +-#define DDE2 2 +-#define DDE1 1 +-#define DDE0 0 +- +-/* Port E Input Pins - PINE */ +-#define PINE7 7 +-#define PINE6 6 +-#define PINE5 5 +-#define PINE4 4 +-#define PINE3 3 +-#define PINE2 2 +-#define PINE1 1 +-#define PINE0 0 +- +-/* Port F Data Register - PORTF */ +-#define PF7 7 +-#define PF6 6 +-#define PF5 5 +-#define PF4 4 +-#define PF3 3 +-#define PF2 2 +-#define PF1 1 +-#define PF0 0 +- +-/* Port F Data Direction Register - DDRF */ +-#define DDF7 7 +-#define DDF6 6 +-#define DDF5 5 +-#define DDF4 4 +-#define DDF3 3 +-#define DDF2 2 +-#define DDF1 1 +-#define DDF0 0 +- +-/* Port F Input Pins - PINF */ +-#define PINF7 7 +-#define PINF6 6 +-#define PINF5 5 +-#define PINF4 4 +-#define PINF3 3 +-#define PINF2 2 +-#define PINF1 1 +-#define PINF0 0 +- +-/* Port G Data Register - PORTG */ +-#define PG4 4 +-#define PG3 3 +-#define PG2 2 +-#define PG1 1 +-#define PG0 0 +- +-/* Port G Data Direction Register - DDRG */ +-#define DDG4 4 +-#define DDG3 3 +-#define DDG2 2 +-#define DDG1 1 +-#define DDG0 0 +- +-/* Port G Input Pins - PING */ +-#define PING4 4 +-#define PING3 3 +-#define PING2 2 +-#define PING1 1 +-#define PING0 0 +- +-/* EEPROM Control Register */ +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-/* Constants */ +-#define SPM_PAGESIZE 256 +-#define RAMEND 0x10FF /* Last On-Chip SRAM Location */ +-#define XRAMEND 0xFFFF +-#define E2END 0x0FFF +-#define E2PAGESIZE 8 +-#define FLASHEND 0x1FFFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_BODEN (unsigned char)~_BV(6) +-#define FUSE_BODLEVEL (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_CKOPT (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_WDTON (unsigned char)~_BV(0) +-#define FUSE_M103C (unsigned char)~_BV(1) +-#define EFUSE_DEFAULT (FUSE_M103C) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x97 +-#define SIGNATURE_2 0x02 +- +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison ADCW +-#pragma GCC poison MCUSR +-#pragma GCC poison SPMCR +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_INTERRUPT1 +-#pragma GCC poison SIG_INTERRUPT2 +-#pragma GCC poison SIG_INTERRUPT3 +-#pragma GCC poison SIG_INTERRUPT4 +-#pragma GCC poison SIG_INTERRUPT5 +-#pragma GCC poison SIG_INTERRUPT6 +-#pragma GCC poison SIG_INTERRUPT7 +-#pragma GCC poison SIG_OUTPUT_COMPARE2 +-#pragma GCC poison SIG_OVERFLOW2 +-#pragma GCC poison SIG_INPUT_CAPTURE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OUTPUT_COMPARE0 +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_SPI +-#pragma GCC poison SIG_USART0_RECV +-#pragma GCC poison SIG_UART0_RECV +-#pragma GCC poison SIG_USART0_DATA +-#pragma GCC poison SIG_UART0_DATA +-#pragma GCC poison SIG_USART0_TRANS +-#pragma GCC poison SIG_UART0_TRANS +-#pragma GCC poison SIG_ADC +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_OUTPUT_COMPARE1C +-#pragma GCC poison SIG_INPUT_CAPTURE3 +-#pragma GCC poison SIG_OUTPUT_COMPARE3A +-#pragma GCC poison SIG_OUTPUT_COMPARE3B +-#pragma GCC poison SIG_OUTPUT_COMPARE3C +-#pragma GCC poison SIG_OVERFLOW3 +-#pragma GCC poison SIG_USART1_RECV +-#pragma GCC poison SIG_UART1_RECV +-#pragma GCC poison SIG_USART1_DATA +-#pragma GCC poison SIG_UART1_DATA +-#pragma GCC poison SIG_USART1_TRANS +-#pragma GCC poison SIG_UART1_TRANS +-#pragma GCC poison SIG_2WIRE_SERIAL +-#pragma GCC poison SIG_SPM_READY +- +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +- +-#endif /* _AVR_IOM128_H_ */ ++/* Copyright (c) 2002, Peter Jansen ++ Copyright (c) 2007, Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom128.h 2226 2011-03-04 17:47:16Z arcanum $ */ ++ ++/* avr/iom128.h - defines for ATmega128 ++ ++ As of 2002-08-27: ++ - This should be up to date with data sheet 2467E-AVR-05/02 */ ++ ++#ifndef _AVR_IOM128_H_ ++#define _AVR_IOM128_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom128.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* Input Pins, Port F */ ++#define PINF _SFR_IO8(0x00) ++ ++/* Input Pins, Port E */ ++#define PINE _SFR_IO8(0x01) ++ ++/* Data Direction Register, Port E */ ++#define DDRE _SFR_IO8(0x02) ++ ++/* Data Register, Port E */ ++#define PORTE _SFR_IO8(0x03) ++ ++/* ADC Data Register */ ++#define ADCW _SFR_IO16(0x04) /* for backwards compatibility */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCL _SFR_IO8(0x04) ++#define ADCH _SFR_IO8(0x05) ++ ++/* ADC Control and status register */ ++#define ADCSR _SFR_IO8(0x06) ++#define ADCSRA _SFR_IO8(0x06) /* new name in datasheet (2467E-AVR-05/02) */ ++ ++/* ADC Multiplexer select */ ++#define ADMUX _SFR_IO8(0x07) ++ ++/* Analog Comparator Control and Status Register */ ++#define ACSR _SFR_IO8(0x08) ++ ++/* USART0 Baud Rate Register Low */ ++#define UBRR0L _SFR_IO8(0x09) ++ ++/* USART0 Control and Status Register B */ ++#define UCSR0B _SFR_IO8(0x0A) ++ ++/* USART0 Control and Status Register A */ ++#define UCSR0A _SFR_IO8(0x0B) ++ ++/* USART0 I/O Data Register */ ++#define UDR0 _SFR_IO8(0x0C) ++ ++/* SPI Control Register */ ++#define SPCR _SFR_IO8(0x0D) ++ ++/* SPI Status Register */ ++#define SPSR _SFR_IO8(0x0E) ++ ++/* SPI I/O Data Register */ ++#define SPDR _SFR_IO8(0x0F) ++ ++/* Input Pins, Port D */ ++#define PIND _SFR_IO8(0x10) ++ ++/* Data Direction Register, Port D */ ++#define DDRD _SFR_IO8(0x11) ++ ++/* Data Register, Port D */ ++#define PORTD _SFR_IO8(0x12) ++ ++/* Input Pins, Port C */ ++#define PINC _SFR_IO8(0x13) ++ ++/* Data Direction Register, Port C */ ++#define DDRC _SFR_IO8(0x14) ++ ++/* Data Register, Port C */ ++#define PORTC _SFR_IO8(0x15) ++ ++/* Input Pins, Port B */ ++#define PINB _SFR_IO8(0x16) ++ ++/* Data Direction Register, Port B */ ++#define DDRB _SFR_IO8(0x17) ++ ++/* Data Register, Port B */ ++#define PORTB _SFR_IO8(0x18) ++ ++/* Input Pins, Port A */ ++#define PINA _SFR_IO8(0x19) ++ ++/* Data Direction Register, Port A */ ++#define DDRA _SFR_IO8(0x1A) ++ ++/* Data Register, Port A */ ++#define PORTA _SFR_IO8(0x1B) ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO16(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++#define EEARH _SFR_IO8(0x1F) ++ ++/* Special Function I/O Register */ ++#define SFIOR _SFR_IO8(0x20) ++ ++/* Watchdog Timer Control Register */ ++#define WDTCR _SFR_IO8(0x21) ++ ++/* On-chip Debug Register */ ++#define OCDR _SFR_IO8(0x22) ++ ++/* Timer2 Output Compare Register */ ++#define OCR2 _SFR_IO8(0x23) ++ ++/* Timer/Counter 2 */ ++#define TCNT2 _SFR_IO8(0x24) ++ ++/* Timer/Counter 2 Control register */ ++#define TCCR2 _SFR_IO8(0x25) ++ ++/* T/C 1 Input Capture Register */ ++#define ICR1 _SFR_IO16(0x26) ++#define ICR1L _SFR_IO8(0x26) ++#define ICR1H _SFR_IO8(0x27) ++ ++/* Timer/Counter1 Output Compare Register B */ ++#define OCR1B _SFR_IO16(0x28) ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BH _SFR_IO8(0x29) ++ ++/* Timer/Counter1 Output Compare Register A */ ++#define OCR1A _SFR_IO16(0x2A) ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++ ++/* Timer/Counter 1 */ ++#define TCNT1 _SFR_IO16(0x2C) ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++ ++/* Timer/Counter 1 Control and Status Register */ ++#define TCCR1B _SFR_IO8(0x2E) ++ ++/* Timer/Counter 1 Control Register */ ++#define TCCR1A _SFR_IO8(0x2F) ++ ++/* Timer/Counter 0 Asynchronous Control & Status Register */ ++#define ASSR _SFR_IO8(0x30) ++ ++/* Output Compare Register 0 */ ++#define OCR0 _SFR_IO8(0x31) ++ ++/* Timer/Counter 0 */ ++#define TCNT0 _SFR_IO8(0x32) ++ ++/* Timer/Counter 0 Control Register */ ++#define TCCR0 _SFR_IO8(0x33) ++ ++/* MCU Status Register */ ++#define MCUSR _SFR_IO8(0x34) ++#define MCUCSR _SFR_IO8(0x34) /* new name in datasheet (2467E-AVR-05/02) */ ++ ++/* MCU general Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++ ++/* Timer/Counter Interrupt Flag Register */ ++#define TIFR _SFR_IO8(0x36) ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define TIMSK _SFR_IO8(0x37) ++ ++/* External Interrupt Flag Register */ ++#define EIFR _SFR_IO8(0x38) ++ ++/* External Interrupt MaSK register */ ++#define EIMSK _SFR_IO8(0x39) ++ ++/* External Interrupt Control Register B */ ++#define EICRB _SFR_IO8(0x3A) ++ ++/* RAM Page Z select register */ ++#define RAMPZ _SFR_IO8(0x3B) ++ ++/* XDIV Divide control register */ ++#define XDIV _SFR_IO8(0x3C) ++ ++/* 0x3D..0x3E SP */ ++ ++/* 0x3F SREG */ ++ ++/* Extended I/O registers */ ++ ++/* Data Direction Register, Port F */ ++#define DDRF _SFR_MEM8(0x61) ++ ++/* Data Register, Port F */ ++#define PORTF _SFR_MEM8(0x62) ++ ++/* Input Pins, Port G */ ++#define PING _SFR_MEM8(0x63) ++ ++/* Data Direction Register, Port G */ ++#define DDRG _SFR_MEM8(0x64) ++ ++/* Data Register, Port G */ ++#define PORTG _SFR_MEM8(0x65) ++ ++/* Store Program Memory Control and Status Register */ ++#define SPMCR _SFR_MEM8(0x68) ++#define SPMCSR _SFR_MEM8(0x68) /* new name in datasheet (2467E-AVR-05/02) */ ++ ++/* External Interrupt Control Register A */ ++#define EICRA _SFR_MEM8(0x6A) ++ ++/* External Memory Control Register B */ ++#define XMCRB _SFR_MEM8(0x6C) ++ ++/* External Memory Control Register A */ ++#define XMCRA _SFR_MEM8(0x6D) ++ ++/* Oscillator Calibration Register */ ++#define OSCCAL _SFR_MEM8(0x6F) ++ ++/* 2-wire Serial Interface Bit Rate Register */ ++#define TWBR _SFR_MEM8(0x70) ++ ++/* 2-wire Serial Interface Status Register */ ++#define TWSR _SFR_MEM8(0x71) ++ ++/* 2-wire Serial Interface Address Register */ ++#define TWAR _SFR_MEM8(0x72) ++ ++/* 2-wire Serial Interface Data Register */ ++#define TWDR _SFR_MEM8(0x73) ++ ++/* 2-wire Serial Interface Control Register */ ++#define TWCR _SFR_MEM8(0x74) ++ ++/* Time Counter 1 Output Compare Register C */ ++#define OCR1C _SFR_MEM16(0x78) ++#define OCR1CL _SFR_MEM8(0x78) ++#define OCR1CH _SFR_MEM8(0x79) ++ ++/* Timer/Counter 1 Control Register C */ ++#define TCCR1C _SFR_MEM8(0x7A) ++ ++/* Extended Timer Interrupt Flag Register */ ++#define ETIFR _SFR_MEM8(0x7C) ++ ++/* Extended Timer Interrupt Mask Register */ ++#define ETIMSK _SFR_MEM8(0x7D) ++ ++/* Timer/Counter 3 Input Capture Register */ ++#define ICR3 _SFR_MEM16(0x80) ++#define ICR3L _SFR_MEM8(0x80) ++#define ICR3H _SFR_MEM8(0x81) ++ ++/* Timer/Counter 3 Output Compare Register C */ ++#define OCR3C _SFR_MEM16(0x82) ++#define OCR3CL _SFR_MEM8(0x82) ++#define OCR3CH _SFR_MEM8(0x83) ++ ++/* Timer/Counter 3 Output Compare Register B */ ++#define OCR3B _SFR_MEM16(0x84) ++#define OCR3BL _SFR_MEM8(0x84) ++#define OCR3BH _SFR_MEM8(0x85) ++ ++/* Timer/Counter 3 Output Compare Register A */ ++#define OCR3A _SFR_MEM16(0x86) ++#define OCR3AL _SFR_MEM8(0x86) ++#define OCR3AH _SFR_MEM8(0x87) ++ ++/* Timer/Counter 3 Counter Register */ ++#define TCNT3 _SFR_MEM16(0x88) ++#define TCNT3L _SFR_MEM8(0x88) ++#define TCNT3H _SFR_MEM8(0x89) ++ ++/* Timer/Counter 3 Control Register B */ ++#define TCCR3B _SFR_MEM8(0x8A) ++ ++/* Timer/Counter 3 Control Register A */ ++#define TCCR3A _SFR_MEM8(0x8B) ++ ++/* Timer/Counter 3 Control Register C */ ++#define TCCR3C _SFR_MEM8(0x8C) ++ ++/* USART0 Baud Rate Register High */ ++#define UBRR0H _SFR_MEM8(0x90) ++ ++/* USART0 Control and Status Register C */ ++#define UCSR0C _SFR_MEM8(0x95) ++ ++/* USART1 Baud Rate Register High */ ++#define UBRR1H _SFR_MEM8(0x98) ++ ++/* USART1 Baud Rate Register Low*/ ++#define UBRR1L _SFR_MEM8(0x99) ++ ++/* USART1 Control and Status Register B */ ++#define UCSR1B _SFR_MEM8(0x9A) ++ ++/* USART1 Control and Status Register A */ ++#define UCSR1A _SFR_MEM8(0x9B) ++ ++/* USART1 I/O Data Register */ ++#define UDR1 _SFR_MEM8(0x9C) ++ ++/* USART1 Control and Status Register C */ ++#define UCSR1C _SFR_MEM8(0x9D) ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++#define SIG_INTERRUPT1 _VECTOR(2) ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect_num 3 ++#define INT2_vect _VECTOR(3) ++#define SIG_INTERRUPT2 _VECTOR(3) ++ ++/* External Interrupt Request 3 */ ++#define INT3_vect_num 4 ++#define INT3_vect _VECTOR(4) ++#define SIG_INTERRUPT3 _VECTOR(4) ++ ++/* External Interrupt Request 4 */ ++#define INT4_vect_num 5 ++#define INT4_vect _VECTOR(5) ++#define SIG_INTERRUPT4 _VECTOR(5) ++ ++/* External Interrupt Request 5 */ ++#define INT5_vect_num 6 ++#define INT5_vect _VECTOR(6) ++#define SIG_INTERRUPT5 _VECTOR(6) ++ ++/* External Interrupt Request 6 */ ++#define INT6_vect_num 7 ++#define INT6_vect _VECTOR(7) ++#define SIG_INTERRUPT6 _VECTOR(7) ++ ++/* External Interrupt Request 7 */ ++#define INT7_vect_num 8 ++#define INT7_vect _VECTOR(8) ++#define SIG_INTERRUPT7 _VECTOR(8) ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect_num 9 ++#define TIMER2_COMP_vect _VECTOR(9) ++#define SIG_OUTPUT_COMPARE2 _VECTOR(9) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 10 ++#define TIMER2_OVF_vect _VECTOR(10) ++#define SIG_OVERFLOW2 _VECTOR(10) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 11 ++#define TIMER1_CAPT_vect _VECTOR(11) ++#define SIG_INPUT_CAPTURE1 _VECTOR(11) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 12 ++#define TIMER1_COMPA_vect _VECTOR(12) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(12) ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect_num 13 ++#define TIMER1_COMPB_vect _VECTOR(13) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(13) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 14 ++#define TIMER1_OVF_vect _VECTOR(14) ++#define SIG_OVERFLOW1 _VECTOR(14) ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect_num 15 ++#define TIMER0_COMP_vect _VECTOR(15) ++#define SIG_OUTPUT_COMPARE0 _VECTOR(15) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 16 ++#define TIMER0_OVF_vect _VECTOR(16) ++#define SIG_OVERFLOW0 _VECTOR(16) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 17 ++#define SPI_STC_vect _VECTOR(17) ++#define SIG_SPI _VECTOR(17) ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect_num 18 ++#define USART0_RX_vect _VECTOR(18) ++#define SIG_USART0_RECV _VECTOR(18) ++#define SIG_UART0_RECV _VECTOR(18) ++ ++/* USART0 Data Register Empty */ ++#define USART0_UDRE_vect_num 19 ++#define USART0_UDRE_vect _VECTOR(19) ++#define SIG_USART0_DATA _VECTOR(19) ++#define SIG_UART0_DATA _VECTOR(19) ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect_num 20 ++#define USART0_TX_vect _VECTOR(20) ++#define SIG_USART0_TRANS _VECTOR(20) ++#define SIG_UART0_TRANS _VECTOR(20) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 21 ++#define ADC_vect _VECTOR(21) ++#define SIG_ADC _VECTOR(21) ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(22) ++#define EE_READY_vect _VECTOR(22) ++#define SIG_EEPROM_READY _VECTOR(22) ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect_num 23 ++#define ANALOG_COMP_vect _VECTOR(23) ++#define SIG_COMPARATOR _VECTOR(23) ++ ++/* Timer/Counter1 Compare Match C */ ++#define TIMER1_COMPC_vect_num 24 ++#define TIMER1_COMPC_vect _VECTOR(24) ++#define SIG_OUTPUT_COMPARE1C _VECTOR(24) ++ ++/* Timer/Counter3 Capture Event */ ++#define TIMER3_CAPT_vect_num 25 ++#define TIMER3_CAPT_vect _VECTOR(25) ++#define SIG_INPUT_CAPTURE3 _VECTOR(25) ++ ++/* Timer/Counter3 Compare Match A */ ++#define TIMER3_COMPA_vect_num 26 ++#define TIMER3_COMPA_vect _VECTOR(26) ++#define SIG_OUTPUT_COMPARE3A _VECTOR(26) ++ ++/* Timer/Counter3 Compare Match B */ ++#define TIMER3_COMPB_vect_num 27 ++#define TIMER3_COMPB_vect _VECTOR(27) ++#define SIG_OUTPUT_COMPARE3B _VECTOR(27) ++ ++/* Timer/Counter3 Compare Match C */ ++#define TIMER3_COMPC_vect_num 28 ++#define TIMER3_COMPC_vect _VECTOR(28) ++#define SIG_OUTPUT_COMPARE3C _VECTOR(28) ++ ++/* Timer/Counter3 Overflow */ ++#define TIMER3_OVF_vect_num 29 ++#define TIMER3_OVF_vect _VECTOR(29) ++#define SIG_OVERFLOW3 _VECTOR(29) ++ ++/* USART1, Rx Complete */ ++#define USART1_RX_vect_num 30 ++#define USART1_RX_vect _VECTOR(30) ++#define SIG_USART1_RECV _VECTOR(30) ++#define SIG_UART1_RECV _VECTOR(30) ++ ++/* USART1, Data Register Empty */ ++#define USART1_UDRE_vect_num 31 ++#define USART1_UDRE_vect _VECTOR(31) ++#define SIG_USART1_DATA _VECTOR(31) ++#define SIG_UART1_DATA _VECTOR(31) ++ ++/* USART1, Tx Complete */ ++#define USART1_TX_vect_num 32 ++#define USART1_TX_vect _VECTOR(32) ++#define SIG_USART1_TRANS _VECTOR(32) ++#define SIG_UART1_TRANS _VECTOR(32) ++ ++/* 2-wire Serial Interface */ ++#define TWI_vect_num 33 ++#define TWI_vect _VECTOR(33) ++#define SIG_2WIRE_SERIAL _VECTOR(33) ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect_num 34 ++#define SPM_READY_vect _VECTOR(34) ++#define SPM_READY_vect _VECTOR(34) ++#define SIG_SPM_READY _VECTOR(34) ++ ++#define _VECTORS_SIZE 140 ++ ++/* ++ The Register Bit names are represented by their bit number (0-7). ++*/ ++ ++/* 2-wire Control Register - TWCR */ ++#define TWINT 7 ++#define TWEA 6 ++#define TWSTA 5 ++#define TWSTO 4 ++#define TWWC 3 ++#define TWEN 2 ++#define TWIE 0 ++ ++/* 2-wire Address Register - TWAR */ ++#define TWA6 7 ++#define TWA5 6 ++#define TWA4 5 ++#define TWA3 4 ++#define TWA2 3 ++#define TWA1 2 ++#define TWA0 1 ++#define TWGCE 0 ++ ++/* 2-wire Status Register - TWSR */ ++#define TWS7 7 ++#define TWS6 6 ++#define TWS5 5 ++#define TWS4 4 ++#define TWS3 3 ++#define TWPS1 1 ++#define TWPS0 0 ++ ++/* External Memory Control Register A - XMCRA */ ++#define SRL2 6 ++#define SRL1 5 ++#define SRL0 4 ++#define SRW01 3 ++#define SRW00 2 ++#define SRW11 1 ++ ++/* External Memory Control Register B - XMCRA */ ++#define XMBK 7 ++#define XMM2 2 ++#define XMM1 1 ++#define XMM0 0 ++ ++/* XDIV Divide control register - XDIV */ ++#define XDIVEN 7 ++#define XDIV6 6 ++#define XDIV5 5 ++#define XDIV4 4 ++#define XDIV3 3 ++#define XDIV2 2 ++#define XDIV1 1 ++#define XDIV0 0 ++ ++/* RAM Page Z select register - RAMPZ */ ++#define RAMPZ0 0 ++ ++/* External Interrupt Control Register A - EICRA */ ++#define ISC31 7 ++#define ISC30 6 ++#define ISC21 5 ++#define ISC20 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* External Interrupt Control Register B - EICRB */ ++#define ISC71 7 ++#define ISC70 6 ++#define ISC61 5 ++#define ISC60 4 ++#define ISC51 3 ++#define ISC50 2 ++#define ISC41 1 ++#define ISC40 0 ++ ++/* Store Program Memory Control Register - SPMCSR, SPMCR */ ++#define SPMIE 7 ++#define RWWSB 6 ++#define RWWSRE 4 ++#define BLBSET 3 ++#define PGWRT 2 ++#define PGERS 1 ++#define SPMEN 0 ++ ++/* External Interrupt MaSK register - EIMSK */ ++#define INT7 7 ++#define INT6 6 ++#define INT5 5 ++#define INT4 4 ++#define INT3 3 ++#define INT2 2 ++#define INT1 1 ++#define INT0 0 ++ ++/* External Interrupt Flag Register - EIFR */ ++#define INTF7 7 ++#define INTF6 6 ++#define INTF5 5 ++#define INTF4 4 ++#define INTF3 3 ++#define INTF2 2 ++#define INTF1 1 ++#define INTF0 0 ++ ++/* Timer/Counter Interrupt MaSK register - TIMSK */ ++#define OCIE2 7 ++#define TOIE2 6 ++#define TICIE1 5 ++#define OCIE1A 4 ++#define OCIE1B 3 ++#define TOIE1 2 ++#define OCIE0 1 ++#define TOIE0 0 ++ ++/* Timer/Counter Interrupt Flag Register - TIFR */ ++#define OCF2 7 ++#define TOV2 6 ++#define ICF1 5 ++#define OCF1A 4 ++#define OCF1B 3 ++#define TOV1 2 ++#define OCF0 1 ++#define TOV0 0 ++ ++/* Extended Timer Interrupt MaSK register - ETIMSK */ ++#define TICIE3 5 ++#define OCIE3A 4 ++#define OCIE3B 3 ++#define TOIE3 2 ++#define OCIE3C 1 ++#define OCIE1C 0 ++ ++/* Extended Timer Interrupt Flag Register - ETIFR */ ++#define ICF3 5 ++#define OCF3A 4 ++#define OCF3B 3 ++#define TOV3 2 ++#define OCF3C 1 ++#define OCF1C 0 ++ ++/* MCU general Control Register - MCUCR */ ++#define SRE 7 ++#define SRW 6 ++#define SRW10 6 /* new name in datasheet (2467E-AVR-05/02) */ ++#define SE 5 ++#define SM1 4 ++#define SM0 3 ++#define SM2 2 ++#define IVSEL 1 ++#define IVCE 0 ++ ++/* MCU Status Register - MCUSR, MCUCSR */ ++#define JTD 7 ++#define JTRF 4 ++#define WDRF 3 ++#define BORF 2 ++#define EXTRF 1 ++#define PORF 0 ++ ++/* Timer/Counter Control Register (generic) */ ++#define FOC 7 ++#define WGM0 6 ++#define COM1 5 ++#define COM0 4 ++#define WGM1 3 ++#define CS2 2 ++#define CS1 1 ++#define CS0 0 ++ ++/* Timer/Counter 0 Control Register - TCCR0 */ ++#define FOC0 7 ++#define WGM00 6 ++#define COM01 5 ++#define COM00 4 ++#define WGM01 3 ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* Timer/Counter 2 Control Register - TCCR2 */ ++#define FOC2 7 ++#define WGM20 6 ++#define COM21 5 ++#define COM20 4 ++#define WGM21 3 ++#define CS22 2 ++#define CS21 1 ++#define CS20 0 ++ ++/* Timer/Counter 0 Asynchronous Control & Status Register - ASSR */ ++#define AS0 3 ++#define TCN0UB 2 ++#define OCR0UB 1 ++#define TCR0UB 0 ++ ++/* Timer/Counter Control Register A (generic) */ ++#define COMA1 7 ++#define COMA0 6 ++#define COMB1 5 ++#define COMB0 4 ++#define COMC1 3 ++#define COMC0 2 ++#define WGMA1 1 ++#define WGMA0 0 ++ ++/* Timer/Counter 1 Control and Status Register A - TCCR1A */ ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define COM1C1 3 ++#define COM1C0 2 ++#define WGM11 1 ++#define WGM10 0 ++ ++/* Timer/Counter 3 Control and Status Register A - TCCR3A */ ++#define COM3A1 7 ++#define COM3A0 6 ++#define COM3B1 5 ++#define COM3B0 4 ++#define COM3C1 3 ++#define COM3C0 2 ++#define WGM31 1 ++#define WGM30 0 ++ ++/* Timer/Counter Control and Status Register B (generic) */ ++#define ICNC 7 ++#define ICES 6 ++#define WGMB3 4 ++#define WGMB2 3 ++#define CSB2 2 ++#define CSB1 1 ++#define CSB0 0 ++ ++/* Timer/Counter 1 Control and Status Register B - TCCR1B */ ++#define ICNC1 7 ++#define ICES1 6 ++#define WGM13 4 ++#define WGM12 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* Timer/Counter 3 Control and Status Register B - TCCR3B */ ++#define ICNC3 7 ++#define ICES3 6 ++#define WGM33 4 ++#define WGM32 3 ++#define CS32 2 ++#define CS31 1 ++#define CS30 0 ++ ++/* Timer/Counter Control Register C (generic) */ ++#define FOCA 7 ++#define FOCB 6 ++#define FOCC 5 ++ ++/* Timer/Counter 3 Control Register C - TCCR3C */ ++#define FOC3A 7 ++#define FOC3B 6 ++#define FOC3C 5 ++ ++/* Timer/Counter 1 Control Register C - TCCR1C */ ++#define FOC1A 7 ++#define FOC1B 6 ++#define FOC1C 5 ++ ++/* On-chip Debug Register - OCDR */ ++#define IDRD 7 ++#define OCDR7 7 ++#define OCDR6 6 ++#define OCDR5 5 ++#define OCDR4 4 ++#define OCDR3 3 ++#define OCDR2 2 ++#define OCDR1 1 ++#define OCDR0 0 ++ ++/* Watchdog Timer Control Register - WDTCR */ ++#define WDCE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* ++ The ADHSM bit has been removed from all documentation, ++ as being not needed at all since the comparator has proven ++ to be fast enough even without feeding it more power. ++*/ ++ ++/* Special Function I/O Register - SFIOR */ ++#define TSM 7 ++#define ACME 3 ++#define PUD 2 ++#define PSR0 1 ++#define PSR321 0 ++ ++/* SPI Status Register - SPSR */ ++#define SPIF 7 ++#define WCOL 6 ++#define SPI2X 0 ++ ++/* SPI Control Register - SPCR */ ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++/* USART Register C (generic) */ ++#define UMSEL 6 ++#define UPM1 5 ++#define UPM0 4 ++#define USBS 3 ++#define UCSZ1 2 ++#define UCSZ0 1 ++#define UCPOL 0 ++ ++/* USART1 Register C - UCSR1C */ ++#define UMSEL1 6 ++#define UPM11 5 ++#define UPM10 4 ++#define USBS1 3 ++#define UCSZ11 2 ++#define UCSZ10 1 ++#define UCPOL1 0 ++ ++/* USART0 Register C - UCSR0C */ ++#define UMSEL0 6 ++#define UPM01 5 ++#define UPM00 4 ++#define USBS0 3 ++#define UCSZ01 2 ++#define UCSZ00 1 ++#define UCPOL0 0 ++ ++/* USART Status Register A (generic) */ ++#define RXC 7 ++#define TXC 6 ++#define UDRE 5 ++#define FE 4 ++#define DOR 3 ++#define UPE 2 ++#define U2X 1 ++#define MPCM 0 ++ ++/* USART1 Status Register A - UCSR1A */ ++#define RXC1 7 ++#define TXC1 6 ++#define UDRE1 5 ++#define FE1 4 ++#define DOR1 3 ++#define UPE1 2 ++#define U2X1 1 ++#define MPCM1 0 ++ ++/* USART0 Status Register A - UCSR0A */ ++#define RXC0 7 ++#define TXC0 6 ++#define UDRE0 5 ++#define FE0 4 ++#define DOR0 3 ++#define UPE0 2 ++#define U2X0 1 ++#define MPCM0 0 ++ ++/* USART Control Register B (generic) */ ++#define RXCIE 7 ++#define TXCIE 6 ++#define UDRIE 5 ++#define RXEN 4 ++#define TXEN 3 ++#define UCSZ 2 ++#define UCSZ2 2 /* new name in datasheet (2467E-AVR-05/02) */ ++#define RXB8 1 ++#define TXB8 0 ++ ++/* USART1 Control Register B - UCSR1B */ ++#define RXCIE1 7 ++#define TXCIE1 6 ++#define UDRIE1 5 ++#define RXEN1 4 ++#define TXEN1 3 ++#define UCSZ12 2 ++#define RXB81 1 ++#define TXB81 0 ++ ++/* USART0 Control Register B - UCSR0B */ ++#define RXCIE0 7 ++#define TXCIE0 6 ++#define UDRIE0 5 ++#define RXEN0 4 ++#define TXEN0 3 ++#define UCSZ02 2 ++#define RXB80 1 ++#define TXB80 0 ++ ++/* Analog Comparator Control and Status Register - ACSR */ ++#define ACD 7 ++#define ACBG 6 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++/* ADC Control and status register - ADCSRA */ ++#define ADEN 7 ++#define ADSC 6 ++#define ADFR 5 ++#define ADIF 4 ++#define ADIE 3 ++#define ADPS2 2 ++#define ADPS1 1 ++#define ADPS0 0 ++ ++/* ADC Multiplexer select - ADMUX */ ++#define REFS1 7 ++#define REFS0 6 ++#define ADLAR 5 ++#define MUX4 4 ++#define MUX3 3 ++#define MUX2 2 ++#define MUX1 1 ++#define MUX0 0 ++ ++/* Port A Data Register - PORTA */ ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++/* Port A Data Direction Register - DDRA */ ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++/* Port A Input Pins - PINA */ ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++/* Port B Data Register - PORTB */ ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* Port B Data Direction Register - DDRB */ ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* Port B Input Pins - PINB */ ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* Port C Data Register - PORTC */ ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++/* Port C Data Direction Register - DDRC */ ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++/* Port C Input Pins - PINC */ ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++/* Port D Data Register - PORTD */ ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* Port D Data Direction Register - DDRD */ ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++/* Port D Input Pins - PIND */ ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++/* Port E Data Register - PORTE */ ++#define PE7 7 ++#define PE6 6 ++#define PE5 5 ++#define PE4 4 ++#define PE3 3 ++#define PE2 2 ++#define PE1 1 ++#define PE0 0 ++ ++/* Port E Data Direction Register - DDRE */ ++#define DDE7 7 ++#define DDE6 6 ++#define DDE5 5 ++#define DDE4 4 ++#define DDE3 3 ++#define DDE2 2 ++#define DDE1 1 ++#define DDE0 0 ++ ++/* Port E Input Pins - PINE */ ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++/* Port F Data Register - PORTF */ ++#define PF7 7 ++#define PF6 6 ++#define PF5 5 ++#define PF4 4 ++#define PF3 3 ++#define PF2 2 ++#define PF1 1 ++#define PF0 0 ++ ++/* Port F Data Direction Register - DDRF */ ++#define DDF7 7 ++#define DDF6 6 ++#define DDF5 5 ++#define DDF4 4 ++#define DDF3 3 ++#define DDF2 2 ++#define DDF1 1 ++#define DDF0 0 ++ ++/* Port F Input Pins - PINF */ ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++/* Port G Data Register - PORTG */ ++#define PG4 4 ++#define PG3 3 ++#define PG2 2 ++#define PG1 1 ++#define PG0 0 ++ ++/* Port G Data Direction Register - DDRG */ ++#define DDG4 4 ++#define DDG3 3 ++#define DDG2 2 ++#define DDG1 1 ++#define DDG0 0 ++ ++/* Port G Input Pins - PING */ ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++/* EEPROM Control Register */ ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++/* Constants */ ++#define SPM_PAGESIZE 256 ++#define RAMSTART 0x100 ++#define RAMEND 0x10FF /* Last On-Chip SRAM Location */ ++#define XRAMEND 0xFFFF ++#define E2END 0x0FFF ++#define E2PAGESIZE 8 ++#define FLASHEND 0x1FFFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_BODEN (unsigned char)~_BV(6) ++#define FUSE_BODLEVEL (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_CKOPT (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_WDTON (unsigned char)~_BV(0) ++#define FUSE_M103C (unsigned char)~_BV(1) ++#define EFUSE_DEFAULT (FUSE_M103C) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x97 ++#define SIGNATURE_2 0x02 ++ ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison ADCW ++#pragma GCC poison MCUSR ++#pragma GCC poison SPMCR ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_INTERRUPT1 ++#pragma GCC poison SIG_INTERRUPT2 ++#pragma GCC poison SIG_INTERRUPT3 ++#pragma GCC poison SIG_INTERRUPT4 ++#pragma GCC poison SIG_INTERRUPT5 ++#pragma GCC poison SIG_INTERRUPT6 ++#pragma GCC poison SIG_INTERRUPT7 ++#pragma GCC poison SIG_OUTPUT_COMPARE2 ++#pragma GCC poison SIG_OVERFLOW2 ++#pragma GCC poison SIG_INPUT_CAPTURE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OUTPUT_COMPARE0 ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_SPI ++#pragma GCC poison SIG_USART0_RECV ++#pragma GCC poison SIG_UART0_RECV ++#pragma GCC poison SIG_USART0_DATA ++#pragma GCC poison SIG_UART0_DATA ++#pragma GCC poison SIG_USART0_TRANS ++#pragma GCC poison SIG_UART0_TRANS ++#pragma GCC poison SIG_ADC ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_OUTPUT_COMPARE1C ++#pragma GCC poison SIG_INPUT_CAPTURE3 ++#pragma GCC poison SIG_OUTPUT_COMPARE3A ++#pragma GCC poison SIG_OUTPUT_COMPARE3B ++#pragma GCC poison SIG_OUTPUT_COMPARE3C ++#pragma GCC poison SIG_OVERFLOW3 ++#pragma GCC poison SIG_USART1_RECV ++#pragma GCC poison SIG_UART1_RECV ++#pragma GCC poison SIG_USART1_DATA ++#pragma GCC poison SIG_UART1_DATA ++#pragma GCC poison SIG_USART1_TRANS ++#pragma GCC poison SIG_UART1_TRANS ++#pragma GCC poison SIG_2WIRE_SERIAL ++#pragma GCC poison SIG_SPM_READY ++ ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++ ++#endif /* _AVR_IOM128_H_ */ +diff --git a/include/avr/iom1280.h b/include/avr/iom1280.h +index b271040..a21f3be 100644 +--- a/include/avr/iom1280.h ++++ b/include/avr/iom1280.h +@@ -1,94 +1,95 @@ +-/* Copyright (c) 2005 Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom1280.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ +- +-/* avr/iom1280.h - definitions for ATmega1280 */ +- +-#ifndef _AVR_IOM1280_H_ +-#define _AVR_IOM1280_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 256 +-#define RAMEND 0x21FF +-#define XRAMEND 0xFFFF +-#define E2END 0xFFF +-#define E2PAGESIZE 8 +-#define FLASHEND 0x1FFFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x97 +-#define SIGNATURE_2 0x03 +- +- +-#endif /* _AVR_IOM1280_H_ */ ++/* Copyright (c) 2005 Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom1280.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ ++ ++/* avr/iom1280.h - definitions for ATmega1280 */ ++ ++#ifndef _AVR_IOM1280_H_ ++#define _AVR_IOM1280_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 256 ++#define RAMSTART 0x200 ++#define RAMEND 0x21FF ++#define XRAMEND 0xFFFF ++#define E2END 0xFFF ++#define E2PAGESIZE 8 ++#define FLASHEND 0x1FFFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x97 ++#define SIGNATURE_2 0x03 ++ ++ ++#endif /* _AVR_IOM1280_H_ */ +diff --git a/include/avr/iom1281.h b/include/avr/iom1281.h +index 3e031de..7f395f9 100644 +--- a/include/avr/iom1281.h ++++ b/include/avr/iom1281.h +@@ -1,95 +1,95 @@ +-/* Copyright (c) 2005 Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom1281.h 2115 2010-04-05 23:19:53Z arcanum $ */ +- +-/* avr/iom1281.h - definitions for ATmega1281 */ +- +-#ifndef _AVR_IOM1281_H_ +-#define _AVR_IOM1281_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 256 +-#define RAMSTART (0x200) +-#define RAMEND 0x21FF +-#define XRAMEND 0xFFFF +-#define E2END 0xFFF +-#define E2PAGESIZE 8 +-#define FLASHEND 0x1FFFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x97 +-#define SIGNATURE_2 0x04 +- +- +-#endif /* _AVR_IOM1281_H_ */ ++/* Copyright (c) 2005 Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom1281.h 2115 2010-04-05 23:19:53Z arcanum $ */ ++ ++/* avr/iom1281.h - definitions for ATmega1281 */ ++ ++#ifndef _AVR_IOM1281_H_ ++#define _AVR_IOM1281_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 256 ++#define RAMSTART (0x200) ++#define RAMEND 0x21FF ++#define XRAMEND 0xFFFF ++#define E2END 0xFFF ++#define E2PAGESIZE 8 ++#define FLASHEND 0x1FFFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x97 ++#define SIGNATURE_2 0x04 ++ ++ ++#endif /* _AVR_IOM1281_H_ */ +diff --git a/include/avr/iom1284.h b/include/avr/iom1284.h +new file mode 100644 +index 0000000..b980463 +--- /dev/null ++++ b/include/avr/iom1284.h +@@ -0,0 +1,1006 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATMEGA1284_H_INCLUDED ++#define _AVR_ATMEGA1284_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom1284.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDRA7 7 ++#define DDRA6 6 ++#define DDRA5 5 ++#define DDRA4 4 ++#define DDRA3 3 ++#define DDRA2 2 ++#define DDRA1 1 ++#define DDRA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDRC7 7 ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC7 7 ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++/* Reserved [0x0C..0x14] */ ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++#define TIFR3 _SFR_IO8(0x18) ++#define TOV3 0 ++#define OCF3A 1 ++#define OCF3B 2 ++#define ICF3 5 ++ ++/* Reserved [0x19..0x1A] */ ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++#define PCIF3 3 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define TSM 7 ++#define PSRASY 1 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++ ++#define OCR0A _SFR_IO8(0x27) ++ ++#define OCR0B _SFR_IO8(0x28) ++ ++/* Reserved [0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR7 7 ++#define OCDR6 6 ++#define OCDR5 5 ++#define OCDR4 4 ++#define OCDR3 3 ++#define OCDR2 2 ++#define OCDR1 1 ++#define OCDR0 0 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define JTRF 4 ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define JTD 7 ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3A] */ ++ ++#define RAMPZ _SFR_IO8(0x3B) ++ ++/* Reserved [0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDE 3 ++#define WDCE 4 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRUSART0 1 ++#define PRUSART1 4 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++#define PRR1 _SFR_MEM8(0x65) ++#define PRTIM3 0 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++/* Reserved [0x67] */ ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++#define PCIE3 3 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++#define TIMSK3 _SFR_MEM8(0x71) ++#define TOIE3 0 ++#define OCIE3A 1 ++#define OCIE3B 2 ++#define ICIE3 5 ++ ++/* Reserved [0x72] */ ++ ++#define PCMSK3 _SFR_MEM8(0x73) ++#define PCINT24 0 ++#define PCINT25 1 ++#define PCINT26 2 ++#define PCINT27 3 ++#define PCINT28 4 ++#define PCINT29 5 ++#define PCINT30 6 ++#define PCINT31 7 ++ ++/* Reserved [0x74..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ACME 6 ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0x8F] */ ++ ++#define TCCR3A _SFR_MEM8(0x90) ++#define WGM30 0 ++#define WGM31 1 ++#define COM3B0 4 ++#define COM3B1 5 ++#define COM3A0 6 ++#define COM3A1 7 ++ ++#define TCCR3B _SFR_MEM8(0x91) ++#define CS30 0 ++#define CS31 1 ++#define CS32 2 ++#define WGM32 3 ++#define WGM33 4 ++#define ICES3 6 ++#define ICNC3 7 ++ ++#define TCCR3C _SFR_MEM8(0x92) ++#define FOC3B 6 ++#define FOC3A 7 ++ ++/* Reserved [0x93] */ ++ ++/* Combine TCNT3L and TCNT3H */ ++#define TCNT3 _SFR_MEM16(0x94) ++ ++#define TCNT3L _SFR_MEM8(0x94) ++#define TCNT3H _SFR_MEM8(0x95) ++ ++/* Combine ICR3L and ICR3H */ ++#define ICR3 _SFR_MEM16(0x96) ++ ++#define ICR3L _SFR_MEM8(0x96) ++#define ICR3H _SFR_MEM8(0x97) ++ ++/* Combine OCR3AL and OCR3AH */ ++#define OCR3A _SFR_MEM16(0x98) ++ ++#define OCR3AL _SFR_MEM8(0x98) ++#define OCR3AH _SFR_MEM8(0x99) ++ ++/* Combine OCR3BL and OCR3BH */ ++#define OCR3B _SFR_MEM16(0x9A) ++ ++#define OCR3BL _SFR_MEM8(0x9A) ++#define OCR3BH _SFR_MEM8(0x9B) ++ ++/* Reserved [0x9C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++#define OCR2B _SFR_MEM8(0xB4) ++ ++/* Reserved [0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++ ++/* Reserved [0xB7] */ ++ ++#define TWBR _SFR_MEM8(0xB8) ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++/* Reserved [0xBE..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0xC6) ++ ++/* Reserved [0xC7] */ ++ ++#define UCSR1A _SFR_MEM8(0xC8) ++#define MPCM1 0 ++#define U2X1 1 ++#define UPE1 2 ++#define DOR1 3 ++#define FE1 4 ++#define UDRE1 5 ++#define TXC1 6 ++#define RXC1 7 ++ ++#define UCSR1B _SFR_MEM8(0xC9) ++#define TXB81 0 ++#define RXB81 1 ++#define UCSZ12 2 ++#define TXEN1 3 ++#define RXEN1 4 ++#define UDRIE1 5 ++#define TXCIE1 6 ++#define RXCIE1 7 ++ ++#define UCSR1C _SFR_MEM8(0xCA) ++#define UCPOL1 0 ++#define UCSZ10 1 ++#define UCSZ11 2 ++#define USBS1 3 ++#define UPM10 4 ++#define UPM11 5 ++#define UMSEL10 6 ++#define UMSEL11 7 ++ ++/* Reserved [0xCB] */ ++ ++/* Combine UBRR1L and UBRR1H */ ++#define UBRR1 _SFR_MEM16(0xCC) ++ ++#define UBRR1L _SFR_MEM8(0xCC) ++#define UBRR1H _SFR_MEM8(0xCD) ++ ++#define UDR1 _SFR_MEM8(0xCE) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect _VECTOR(3) ++#define INT2_vect_num 3 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(4) ++#define PCINT0_vect_num 4 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(5) ++#define PCINT1_vect_num 5 ++ ++/* Pin Change Interrupt Request 2 */ ++#define PCINT2_vect _VECTOR(6) ++#define PCINT2_vect_num 6 ++ ++/* Pin Change Interrupt Request 3 */ ++#define PCINT3_vect _VECTOR(7) ++#define PCINT3_vect_num 7 ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect _VECTOR(8) ++#define WDT_vect_num 8 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPA_vect _VECTOR(9) ++#define TIMER2_COMPA_vect_num 9 ++ ++/* Timer/Counter2 Compare Match B */ ++#define TIMER2_COMPB_vect _VECTOR(10) ++#define TIMER2_COMPB_vect_num 10 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(11) ++#define TIMER2_OVF_vect_num 11 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(12) ++#define TIMER1_CAPT_vect_num 12 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(13) ++#define TIMER1_COMPA_vect_num 13 ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(14) ++#define TIMER1_COMPB_vect_num 14 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(15) ++#define TIMER1_OVF_vect_num 15 ++ ++/* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPA_vect _VECTOR(16) ++#define TIMER0_COMPA_vect_num 16 ++ ++/* Timer/Counter0 Compare Match B */ ++#define TIMER0_COMPB_vect _VECTOR(17) ++#define TIMER0_COMPB_vect_num 17 ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(18) ++#define TIMER0_OVF_vect_num 18 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(19) ++#define SPI_STC_vect_num 19 ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect _VECTOR(20) ++#define USART0_RX_vect_num 20 ++ ++/* USART0 Data register Empty */ ++#define USART0_UDRE_vect _VECTOR(21) ++#define USART0_UDRE_vect_num 21 ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect _VECTOR(22) ++#define USART0_TX_vect_num 22 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(23) ++#define ANALOG_COMP_vect_num 23 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(24) ++#define ADC_vect_num 24 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(25) ++#define EE_READY_vect_num 25 ++ ++/* 2-wire Serial Interface */ ++#define TWI_vect _VECTOR(26) ++#define TWI_vect_num 26 ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect _VECTOR(27) ++#define SPM_READY_vect_num 27 ++ ++/* USART1 RX complete */ ++#define USART1_RX_vect _VECTOR(28) ++#define USART1_RX_vect_num 28 ++ ++/* USART1 Data Register Empty */ ++#define USART1_UDRE_vect _VECTOR(29) ++#define USART1_UDRE_vect_num 29 ++ ++/* USART1 TX complete */ ++#define USART1_TX_vect _VECTOR(30) ++#define USART1_TX_vect_num 30 ++ ++/* Timer/Counter3 Capture Event */ ++#define TIMER3_CAPT_vect _VECTOR(31) ++#define TIMER3_CAPT_vect_num 31 ++ ++/* Timer/Counter3 Compare Match A */ ++#define TIMER3_COMPA_vect _VECTOR(32) ++#define TIMER3_COMPA_vect_num 32 ++ ++/* Timer/Counter3 Compare Match B */ ++#define TIMER3_COMPB_vect _VECTOR(33) ++#define TIMER3_COMPB_vect_num 33 ++ ++/* Timer/Counter3 Overflow */ ++#define TIMER3_OVF_vect _VECTOR(34) ++#define TIMER3_OVF_vect_num 34 ++ ++#define _VECTORS_SIZE 140 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 256 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x1FFFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 16384 ++#define RAMEND 0x40FF ++#define E2START 0 ++#define E2SIZE 4096 ++#define E2PAGESIZE 8 ++#define E2END 0x0FFF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x97 ++#define SIGNATURE_2 0x06 ++ ++ ++#endif /* #ifdef _AVR_ATMEGA1284_H_INCLUDED */ ++ +diff --git a/include/avr/iom1284p.h b/include/avr/iom1284p.h +index 5c32d43..2bd8811 100644 +--- a/include/avr/iom1284p.h ++++ b/include/avr/iom1284p.h +@@ -1,1200 +1,1200 @@ +-/* Copyright (c) 2007 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. +-*/ +- +-/* $Id: iom1284p.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* avr/iom1284p.h - definitions for ATmega1284P. */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom1284p.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_IOM1284P_H_ +-#define _AVR_IOM1284P_H_ 1 +- +- +-/* Registers and associated bit numbers */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +-#define PINA4 4 +-#define PINA5 5 +-#define PINA6 6 +-#define PINA7 7 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +-#define DDA4 4 +-#define DDA5 5 +-#define DDA6 6 +-#define DDA7 7 +- +-#define PORTA _SFR_IO8(0x02) +-#define PORTA0 0 +-#define PORTA1 1 +-#define PORTA2 2 +-#define PORTA3 3 +-#define PORTA4 4 +-#define PORTA5 5 +-#define PORTA6 6 +-#define PORTA7 7 +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +-#define PINC7 7 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC3 3 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +-#define DDC7 7 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC3 3 +-#define PORTC4 4 +-#define PORTC5 5 +-#define PORTC6 6 +-#define PORTC7 7 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define TIFR2 _SFR_IO8(0x17) +-#define TOV2 0 +-#define OCF2A 1 +-#define OCF2B 2 +- +-#define TIFR3 _SFR_IO8(0x18) +-#define TOV3 0 +-#define OCF3A 1 +-#define OCF3B 2 +-#define ICF3 5 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +-#define PCIF1 1 +-#define PCIF2 2 +-#define PCIF3 3 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +-#define INTF2 2 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +-#define INT2 2 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +-#define EEAR9 1 +-#define EEAR10 2 +-#define EEAR11 3 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSRSYNC 0 +-#define PSRASY 1 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define OCR0A _SFR_IO8(0x27) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define OCR0B _SFR_IO8(0x28) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define OCDR _SFR_IO8(0x31) +-#define OCDR0 0 +-#define OCDR1 1 +-#define OCDR2 2 +-#define OCDR3 3 +-#define OCDR4 4 +-#define OCDR5 5 +-#define OCDR6 6 +-#define OCDR7 7 +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +-#define JTRF 4 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define BODSE 5 +-#define BODS 6 +-#define JTD 7 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define SIGRD 5 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define RAMPZ _SFR_IO8(0x3B) +-#define RAMPZ0 0 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define PRR0 _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM1 3 +-#define PRUSART1 4 +-#define PRTIM0 5 +-#define PRTIM2 6 +-#define PRTWI 7 +- +-#define PRR1 _SFR_MEM8(0x65) +-#define PRTIM3 0 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +-#define PCIE1 1 +-#define PCIE2 2 +-#define PCIE3 3 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define ISC20 4 +-#define ISC21 5 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-#define PCMSK2 _SFR_MEM8(0x6D) +-#define PCINT16 0 +-#define PCINT17 1 +-#define PCINT18 2 +-#define PCINT19 3 +-#define PCINT20 4 +-#define PCINT21 5 +-#define PCINT22 6 +-#define PCINT23 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define TIMSK2 _SFR_MEM8(0x70) +-#define TOIE2 0 +-#define OCIE2A 1 +-#define OCIE2B 2 +- +-#define TIMSK3 _SFR_MEM8(0x71) +-#define TOIE3 0 +-#define OCIE3A 1 +-#define OCIE3B 2 +-#define ICIE3 5 +- +-#define PCMSK3 _SFR_MEM8(0x73) +-#define PCINT24 0 +-#define PCINT25 1 +-#define PCINT26 2 +-#define PCINT27 3 +-#define PCINT28 4 +-#define PCINT29 5 +-#define PCINT30 6 +-#define PCINT31 7 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +- +-#define ADCL _SFR_MEM8(0x78) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_MEM8(0x79) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ACME 6 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define TCCR3A _SFR_MEM8(0x90) +-#define WGM30 0 +-#define WGM31 1 +-#define COM3B0 4 +-#define COM3B1 5 +-#define COM3A0 6 +-#define COM3A1 7 +- +-#define TCCR3B _SFR_MEM8(0x91) +-#define CS30 0 +-#define CS31 1 +-#define CS32 2 +-#define WGM32 3 +-#define WGM33 4 +-#define ICES3 6 +-#define ICNC3 7 +- +-#define TCCR3C _SFR_MEM8(0x92) +-#define FOC3B 6 +-#define FOC3A 7 +- +-#define TCNT3 _SFR_MEM16(0x94) +- +-#define TCNT3L _SFR_MEM8(0x94) +-#define TCNT3L0 0 +-#define TCNT3L1 1 +-#define TCNT3L2 2 +-#define TCNT3L3 3 +-#define TCNT3L4 4 +-#define TCNT3L5 5 +-#define TCNT3L6 6 +-#define TCNT3L7 7 +- +-#define TCNT3H _SFR_MEM8(0x95) +-#define TCNT3H0 0 +-#define TCNT3H1 1 +-#define TCNT3H2 2 +-#define TCNT3H3 3 +-#define TCNT3H4 4 +-#define TCNT3H5 5 +-#define TCNT3H6 6 +-#define TCNT3H7 7 +- +-#define ICR3 _SFR_MEM16(0x96) +- +-#define ICR3L _SFR_MEM8(0x96) +-#define ICR3L0 0 +-#define ICR3L1 1 +-#define ICR3L2 2 +-#define ICR3L3 3 +-#define ICR3L4 4 +-#define ICR3L5 5 +-#define ICR3L6 6 +-#define ICR3L7 7 +- +-#define ICR3H _SFR_MEM8(0x97) +-#define ICR3H0 0 +-#define ICR3H1 1 +-#define ICR3H2 2 +-#define ICR3H3 3 +-#define ICR3H4 4 +-#define ICR3H5 5 +-#define ICR3H6 6 +-#define ICR3H7 7 +- +-#define OCR3A _SFR_MEM16(0x98) +- +-#define OCR3AL _SFR_MEM8(0x98) +-#define OCR3AL0 0 +-#define OCR3AL1 1 +-#define OCR3AL2 2 +-#define OCR3AL3 3 +-#define OCR3AL4 4 +-#define OCR3AL5 5 +-#define OCR3AL6 6 +-#define OCR3AL7 7 +- +-#define OCR3AH _SFR_MEM8(0x99) +-#define OCR3AH0 0 +-#define OCR3AH1 1 +-#define OCR3AH2 2 +-#define OCR3AH3 3 +-#define OCR3AH4 4 +-#define OCR3AH5 5 +-#define OCR3AH6 6 +-#define OCR3AH7 7 +- +-#define OCR3B _SFR_MEM16(0x9A) +- +-#define OCR3BL _SFR_MEM8(0x9A) +-#define OCR3AL0 0 +-#define OCR3AL1 1 +-#define OCR3AL2 2 +-#define OCR3AL3 3 +-#define OCR3AL4 4 +-#define OCR3AL5 5 +-#define OCR3AL6 6 +-#define OCR3AL7 7 +- +-#define OCR3BH _SFR_MEM8(0x9B) +-#define OCR3AH0 0 +-#define OCR3AH1 1 +-#define OCR3AH2 2 +-#define OCR3AH3 3 +-#define OCR3AH4 4 +-#define OCR3AH5 5 +-#define OCR3AH6 6 +-#define OCR3AH7 7 +- -#define TCCR2A _SFR_MEM8(0xB0) -#define WGM20 0 -#define WGM21 1 @@ -52603,9693 +78060,168919 @@ index b73ccd7..8739387 100644 -#define OCR2_5 5 -#define OCR2_6 6 -#define OCR2_7 7 - - #define TWBR _SFR_MEM8(0xB8) - #define TWBR0 0 -@@ -1146,6 +1096,10 @@ - #define UMSEL10 6 - #define UMSEL11 7 - -+#define UCSR1D _SFR_MEM8(0xCB) -+#define RTSEN 0 -+#define CTSEN 1 -+ - #define UBRR1 _SFR_MEM16(0xCC) - - #define UBRR1L _SFR_MEM8(0xCC) +- +-#define ASSR _SFR_MEM8(0xB6) +-#define TCR2BUB 0 +-#define TCR2AUB 1 +-#define OCR2BUB 2 +-#define OCR2AUB 3 +-#define TCN2UB 4 +-#define AS2 5 +-#define EXCLK 6 +- +-#define TWBR _SFR_MEM8(0xB8) +-#define TWBR0 0 +-#define TWBR1 1 +-#define TWBR2 2 +-#define TWBR3 3 +-#define TWBR4 4 +-#define TWBR5 5 +-#define TWBR6 6 +-#define TWBR7 7 +- +-#define TWSR _SFR_MEM8(0xB9) +-#define TWPS0 0 +-#define TWPS1 1 +-#define TWS3 3 +-#define TWS4 4 +-#define TWS5 5 +-#define TWS6 6 +-#define TWS7 7 +- +-#define TWAR _SFR_MEM8(0xBA) +-#define TWGCE 0 +-#define TWA0 1 +-#define TWA1 2 +-#define TWA2 3 +-#define TWA3 4 +-#define TWA4 5 +-#define TWA5 6 +-#define TWA6 7 +- +-#define TWDR _SFR_MEM8(0xBB) +-#define TWD0 0 +-#define TWD1 1 +-#define TWD2 2 +-#define TWD3 3 +-#define TWD4 4 +-#define TWD5 5 +-#define TWD6 6 +-#define TWD7 7 +- +-#define TWCR _SFR_MEM8(0xBC) +-#define TWIE 0 +-#define TWEN 2 +-#define TWWC 3 +-#define TWSTO 4 +-#define TWSTA 5 +-#define TWEA 6 +-#define TWINT 7 +- +-#define TWAMR _SFR_MEM8(0xBD) +-#define TWAM0 1 +-#define TWAM1 2 +-#define TWAM2 3 +-#define TWAM3 4 +-#define TWAM4 5 +-#define TWAM5 6 +-#define TWAM6 7 +- +-#define UCSR0A _SFR_MEM8(0xC0) +-#define MPCM0 0 +-#define U2X0 1 +-#define UPE0 2 +-#define DOR0 3 +-#define FE0 4 +-#define UDRE0 5 +-#define TXC0 6 +-#define RXC0 7 +- +-#define UCSR0B _SFR_MEM8(0xC1) +-#define TXB80 0 +-#define RXB80 1 +-#define UCSZ02 2 +-#define TXEN0 3 +-#define RXEN0 4 +-#define UDRIE0 5 +-#define TXCIE0 6 +-#define RXCIE0 7 +- +-#define UCSR0C _SFR_MEM8(0xC2) +-#define UCPOL0 0 +-#define UCSZ00 1 +-#define UCSZ01 2 +-#define USBS0 3 +-#define UPM00 4 +-#define UPM01 5 +-#define UMSEL00 6 +-#define UMSEL01 7 +- +-#define UBRR0 _SFR_MEM16(0xC4) +- +-#define UBRR0L _SFR_MEM8(0xC4) +-#define UBRR0_0 0 +-#define UBRR0_1 1 +-#define UBRR0_2 2 +-#define UBRR0_3 3 +-#define UBRR0_4 4 +-#define UBRR0_5 5 +-#define UBRR0_6 6 +-#define UBRR0_7 7 +- +-#define UBRR0H _SFR_MEM8(0xC5) +-#define UBRR0_8 0 +-#define UBRR0_9 1 +-#define UBRR0_10 2 +-#define UBRR0_11 3 +- +-#define UDR0 _SFR_MEM8(0xC6) +-#define UDR0_0 0 +-#define UDR0_1 1 +-#define UDR0_2 2 +-#define UDR0_3 3 +-#define UDR0_4 4 +-#define UDR0_5 5 +-#define UDR0_6 6 +-#define UDR0_7 7 +- +-#define UCSR1A _SFR_MEM8(0xC8) +-#define MPCM1 0 +-#define U2X1 1 +-#define UPE1 2 +-#define DOR1 3 +-#define FE1 4 +-#define UDRE1 5 +-#define TXC1 6 +-#define RXC1 7 +- +-#define UCSR1B _SFR_MEM8(0xC9) +-#define TXB81 0 +-#define RXB81 1 +-#define UCSZ12 2 +-#define TXEN1 3 +-#define RXEN1 4 +-#define UDRIE1 5 +-#define TXCIE1 6 +-#define RXCIE1 7 +- +-#define UCSR1C _SFR_MEM8(0xCA) +-#define UCPOL1 0 +-#define UCSZ10 1 +-#define UCSZ11 2 +-#define USBS1 3 +-#define UPM10 4 +-#define UPM11 5 +-#define UMSEL10 6 +-#define UMSEL11 7 +- +-#define UBRR1 _SFR_MEM16(0xCC) +- +-#define UBRR1L _SFR_MEM8(0xCC) +-#define UBRR1_0 0 +-#define UBRR1_1 1 +-#define UBRR1_2 2 +-#define UBRR1_3 3 +-#define UBRR1_4 4 +-#define UBRR1_5 5 +-#define UBRR1_6 6 +-#define UBRR1_7 7 +- +-#define UBRR1H _SFR_MEM8(0xCD) +-#define UBRR1_8 0 +-#define UBRR1_9 1 +-#define UBRR1_10 2 +-#define UBRR1_11 3 +- +-#define UDR1 _SFR_MEM8(0xCE) +-#define UDR1_0 0 +-#define UDR1_1 1 +-#define UDR1_2 2 +-#define UDR1_3 3 +-#define UDR1_4 4 +-#define UDR1_5 5 +-#define UDR1_6 6 +-#define UDR1_7 7 +- +- +-/* Interrupt Vectors */ +-/* Interrupt Vector 0 is the reset vector. */ +- +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +- +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ +- +-#define INT2_vect_num 3 +-#define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ +- +-#define PCINT0_vect_num 4 +-#define PCINT0_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */ +- +-#define PCINT1_vect_num 5 +-#define PCINT1_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */ +- +-#define PCINT2_vect_num 6 +-#define PCINT2_vect _VECTOR(6) /* Pin Change Interrupt Request 2 */ +- +-#define PCINT3_vect_num 7 +-#define PCINT3_vect _VECTOR(7) /* Pin Change Interrupt Request 3 */ +- +-#define WDT_vect_num 8 +-#define WDT_vect _VECTOR(8) /* Watchdog Time-out Interrupt */ +- +-#define TIMER2_COMPA_vect_num 9 +-#define TIMER2_COMPA_vect _VECTOR(9) /* Timer/Counter2 Compare Match A */ +- +-#define TIMER2_COMPB_vect_num 10 +-#define TIMER2_COMPB_vect _VECTOR(10) /* Timer/Counter2 Compare Match B */ +- +-#define TIMER2_OVF_vect_num 11 +-#define TIMER2_OVF_vect _VECTOR(11) /* Timer/Counter2 Overflow */ +- +-#define TIMER1_CAPT_vect_num 12 +-#define TIMER1_CAPT_vect _VECTOR(12) /* Timer/Counter1 Capture Event */ +- +-#define TIMER1_COMPA_vect_num 13 +-#define TIMER1_COMPA_vect _VECTOR(13) /* Timer/Counter1 Compare Match A */ +- +-#define TIMER1_COMPB_vect_num 14 +-#define TIMER1_COMPB_vect _VECTOR(14) /* Timer/Counter1 Compare Match B */ +- +-#define TIMER1_OVF_vect_num 15 +-#define TIMER1_OVF_vect _VECTOR(15) /* Timer/Counter1 Overflow */ +- +-#define TIMER0_COMPA_vect_num 16 +-#define TIMER0_COMPA_vect _VECTOR(16) /* Timer/Counter0 Compare Match A */ +- +-#define TIMER0_COMPB_vect_num 17 +-#define TIMER0_COMPB_vect _VECTOR(17) /* Timer/Counter0 Compare Match B */ +- +-#define TIMER0_OVF_vect_num 18 +-#define TIMER0_OVF_vect _VECTOR(18) /* Timer/Counter0 Overflow */ +- +-#define SPI_STC_vect_num 19 +-#define SPI_STC_vect _VECTOR(19) /* SPI Serial Transfer Complete */ +- +-#define USART0_RX_vect_num 20 +-#define USART0_RX_vect _VECTOR(20) /* USART0, Rx Complete */ +- +-#define USART0_UDRE_vect_num 21 +-#define USART0_UDRE_vect _VECTOR(21) /* USART0 Data register Empty */ +- +-#define USART0_TX_vect_num 22 +-#define USART0_TX_vect _VECTOR(22) /* USART0, Tx Complete */ +- +-#define ANALOG_COMP_vect_num 23 +-#define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */ +- +-#define ADC_vect_num 24 +-#define ADC_vect _VECTOR(24) /* ADC Conversion Complete */ +- +-#define EE_READY_vect_num 25 +-#define EE_READY_vect _VECTOR(25) /* EEPROM Ready */ +- +-#define TWI_vect_num 26 +-#define TWI_vect _VECTOR(26) /* 2-wire Serial Interface */ +- +-#define SPM_READY_vect_num 27 +-#define SPM_READY_vect _VECTOR(27) /* Store Program Memory Read */ +- +-#define USART1_RX_vect_num 28 +-#define USART1_RX_vect _VECTOR(28) /* USART1 RX complete */ +- +-#define USART1_UDRE_vect_num 29 +-#define USART1_UDRE_vect _VECTOR(29) /* USART1 Data Register Empty */ +- +-#define USART1_TX_vect_num 30 +-#define USART1_TX_vect _VECTOR(30) /* USART1 TX complete */ +- +-#define TIMER3_CAPT_vect_num 31 +-#define TIMER3_CAPT_vect _VECTOR(31) /* Timer/Counter3 Capture Event */ +- +-#define TIMER3_COMPA_vect_num 32 +-#define TIMER3_COMPA_vect _VECTOR(32) /* Timer/Counter3 Compare Match A */ +- +-#define TIMER3_COMPB_vect_num 33 +-#define TIMER3_COMPB_vect _VECTOR(33) /* Timer/Counter3 Compare Match B */ +- +-#define TIMER3_OVF_vect_num 34 +-#define TIMER3_OVF_vect _VECTOR(34) /* Timer/Counter3 Overflow */ +- +-#define _VECTORS_SIZE (35 * 4) +- +- +-/* Constants */ +-#define SPM_PAGESIZE 256 +-#define RAMSTART (0x100) +-#define RAMEND 0x40FF /* Last On-Chip SRAM Location */ +-#define XRAMSIZE 0 +-#define XRAMEND RAMEND +-#define E2END 0xFFF +-#define E2PAGESIZE 8 +-#define FLASHEND 0x1FFFF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ +-#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x97 +-#define SIGNATURE_2 0x05 +- +- +-#endif /* _AVR_IOM1284P_H_ */ ++/* Copyright (c) 2007 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++/* $Id: iom1284p.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* avr/iom1284p.h - definitions for ATmega1284P. */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom1284p.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_IOM1284P_H_ ++#define _AVR_IOM1284P_H_ 1 ++ ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++#define PINA4 4 ++#define PINA5 5 ++#define PINA6 6 ++#define PINA7 7 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++#define DDA4 4 ++#define DDA5 5 ++#define DDA6 6 ++#define DDA7 7 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA0 0 ++#define PORTA1 1 ++#define PORTA2 2 ++#define PORTA3 3 ++#define PORTA4 4 ++#define PORTA5 5 ++#define PORTA6 6 ++#define PORTA7 7 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++#define PINC7 7 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++#define DDC7 7 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC3 3 ++#define PORTC4 4 ++#define PORTC5 5 ++#define PORTC6 6 ++#define PORTC7 7 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++#define TIFR3 _SFR_IO8(0x18) ++#define TOV3 0 ++#define OCF3A 1 ++#define OCF3B 2 ++#define ICF3 5 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++#define PCIF3 3 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++#define EEAR9 1 ++#define EEAR10 2 ++#define EEAR11 3 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define PSRASY 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define OCR0A _SFR_IO8(0x27) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define OCR0B _SFR_IO8(0x28) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCDR7 7 ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define JTRF 4 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++#define JTD 7 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define RAMPZ _SFR_IO8(0x3B) ++#define RAMPZ0 0 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRUSART1 4 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++#define PRR1 _SFR_MEM8(0x65) ++#define PRTIM3 0 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++#define PCIE3 3 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++#define TIMSK3 _SFR_MEM8(0x71) ++#define TOIE3 0 ++#define OCIE3A 1 ++#define OCIE3B 2 ++#define ICIE3 5 ++ ++#define PCMSK3 _SFR_MEM8(0x73) ++#define PCINT24 0 ++#define PCINT25 1 ++#define PCINT26 2 ++#define PCINT27 3 ++#define PCINT28 4 ++#define PCINT29 5 ++#define PCINT30 6 ++#define PCINT31 7 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_MEM8(0x79) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define TCCR3A _SFR_MEM8(0x90) ++#define WGM30 0 ++#define WGM31 1 ++#define COM3B0 4 ++#define COM3B1 5 ++#define COM3A0 6 ++#define COM3A1 7 ++ ++#define TCCR3B _SFR_MEM8(0x91) ++#define CS30 0 ++#define CS31 1 ++#define CS32 2 ++#define WGM32 3 ++#define WGM33 4 ++#define ICES3 6 ++#define ICNC3 7 ++ ++#define TCCR3C _SFR_MEM8(0x92) ++#define FOC3B 6 ++#define FOC3A 7 ++ ++#define TCNT3 _SFR_MEM16(0x94) ++ ++#define TCNT3L _SFR_MEM8(0x94) ++#define TCNT3L0 0 ++#define TCNT3L1 1 ++#define TCNT3L2 2 ++#define TCNT3L3 3 ++#define TCNT3L4 4 ++#define TCNT3L5 5 ++#define TCNT3L6 6 ++#define TCNT3L7 7 ++ ++#define TCNT3H _SFR_MEM8(0x95) ++#define TCNT3H0 0 ++#define TCNT3H1 1 ++#define TCNT3H2 2 ++#define TCNT3H3 3 ++#define TCNT3H4 4 ++#define TCNT3H5 5 ++#define TCNT3H6 6 ++#define TCNT3H7 7 ++ ++#define ICR3 _SFR_MEM16(0x96) ++ ++#define ICR3L _SFR_MEM8(0x96) ++#define ICR3L0 0 ++#define ICR3L1 1 ++#define ICR3L2 2 ++#define ICR3L3 3 ++#define ICR3L4 4 ++#define ICR3L5 5 ++#define ICR3L6 6 ++#define ICR3L7 7 ++ ++#define ICR3H _SFR_MEM8(0x97) ++#define ICR3H0 0 ++#define ICR3H1 1 ++#define ICR3H2 2 ++#define ICR3H3 3 ++#define ICR3H4 4 ++#define ICR3H5 5 ++#define ICR3H6 6 ++#define ICR3H7 7 ++ ++#define OCR3A _SFR_MEM16(0x98) ++ ++#define OCR3AL _SFR_MEM8(0x98) ++#define OCR3AL0 0 ++#define OCR3AL1 1 ++#define OCR3AL2 2 ++#define OCR3AL3 3 ++#define OCR3AL4 4 ++#define OCR3AL5 5 ++#define OCR3AL6 6 ++#define OCR3AL7 7 ++ ++#define OCR3AH _SFR_MEM8(0x99) ++#define OCR3AH0 0 ++#define OCR3AH1 1 ++#define OCR3AH2 2 ++#define OCR3AH3 3 ++#define OCR3AH4 4 ++#define OCR3AH5 5 ++#define OCR3AH6 6 ++#define OCR3AH7 7 ++ ++#define OCR3B _SFR_MEM16(0x9A) ++ ++#define OCR3BL _SFR_MEM8(0x9A) ++#define OCR3AL0 0 ++#define OCR3AL1 1 ++#define OCR3AL2 2 ++#define OCR3AL3 3 ++#define OCR3AL4 4 ++#define OCR3AL5 5 ++#define OCR3AL6 6 ++#define OCR3AL7 7 ++ ++#define OCR3BH _SFR_MEM8(0x9B) ++#define OCR3AH0 0 ++#define OCR3AH1 1 ++#define OCR3AH2 2 ++#define OCR3AH3 3 ++#define OCR3AH4 4 ++#define OCR3AH5 5 ++#define OCR3AH6 6 ++#define OCR3AH7 7 ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++#define TCNT2_0 0 ++#define TCNT2_1 1 ++#define TCNT2_2 2 ++#define TCNT2_3 3 ++#define TCNT2_4 4 ++#define TCNT2_5 5 ++#define TCNT2_6 6 ++#define TCNT2_7 7 ++ ++#define OCR2A _SFR_MEM8(0xB3) ++#define OCR2_0 0 ++#define OCR2_1 1 ++#define OCR2_2 2 ++#define OCR2_3 3 ++#define OCR2_4 4 ++#define OCR2_5 5 ++#define OCR2_6 6 ++#define OCR2_7 7 ++ ++#define OCR2B _SFR_MEM8(0xB4) ++#define OCR2_0 0 ++#define OCR2_1 1 ++#define OCR2_2 2 ++#define OCR2_3 3 ++#define OCR2_4 4 ++#define OCR2_5 5 ++#define OCR2_6 6 ++#define OCR2_7 7 ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++ ++#define TWBR _SFR_MEM8(0xB8) ++#define TWBR0 0 ++#define TWBR1 1 ++#define TWBR2 2 ++#define TWBR3 3 ++#define TWBR4 4 ++#define TWBR5 5 ++#define TWBR6 6 ++#define TWBR7 7 ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++#define TWD0 0 ++#define TWD1 1 ++#define TWD2 2 ++#define TWD3 3 ++#define TWD4 4 ++#define TWD5 5 ++#define TWD6 6 ++#define TWD7 7 ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0_0 0 ++#define UBRR0_1 1 ++#define UBRR0_2 2 ++#define UBRR0_3 3 ++#define UBRR0_4 4 ++#define UBRR0_5 5 ++#define UBRR0_6 6 ++#define UBRR0_7 7 ++ ++#define UBRR0H _SFR_MEM8(0xC5) ++#define UBRR0_8 0 ++#define UBRR0_9 1 ++#define UBRR0_10 2 ++#define UBRR0_11 3 ++ ++#define UDR0 _SFR_MEM8(0xC6) ++#define UDR0_0 0 ++#define UDR0_1 1 ++#define UDR0_2 2 ++#define UDR0_3 3 ++#define UDR0_4 4 ++#define UDR0_5 5 ++#define UDR0_6 6 ++#define UDR0_7 7 ++ ++#define UCSR1A _SFR_MEM8(0xC8) ++#define MPCM1 0 ++#define U2X1 1 ++#define UPE1 2 ++#define DOR1 3 ++#define FE1 4 ++#define UDRE1 5 ++#define TXC1 6 ++#define RXC1 7 ++ ++#define UCSR1B _SFR_MEM8(0xC9) ++#define TXB81 0 ++#define RXB81 1 ++#define UCSZ12 2 ++#define TXEN1 3 ++#define RXEN1 4 ++#define UDRIE1 5 ++#define TXCIE1 6 ++#define RXCIE1 7 ++ ++#define UCSR1C _SFR_MEM8(0xCA) ++#define UCPOL1 0 ++#define UCSZ10 1 ++#define UCSZ11 2 ++#define USBS1 3 ++#define UPM10 4 ++#define UPM11 5 ++#define UMSEL10 6 ++#define UMSEL11 7 ++ ++#define UBRR1 _SFR_MEM16(0xCC) ++ ++#define UBRR1L _SFR_MEM8(0xCC) ++#define UBRR1_0 0 ++#define UBRR1_1 1 ++#define UBRR1_2 2 ++#define UBRR1_3 3 ++#define UBRR1_4 4 ++#define UBRR1_5 5 ++#define UBRR1_6 6 ++#define UBRR1_7 7 ++ ++#define UBRR1H _SFR_MEM8(0xCD) ++#define UBRR1_8 0 ++#define UBRR1_9 1 ++#define UBRR1_10 2 ++#define UBRR1_11 3 ++ ++#define UDR1 _SFR_MEM8(0xCE) ++#define UDR1_0 0 ++#define UDR1_1 1 ++#define UDR1_2 2 ++#define UDR1_3 3 ++#define UDR1_4 4 ++#define UDR1_5 5 ++#define UDR1_6 6 ++#define UDR1_7 7 ++ ++ ++/* Interrupt Vectors */ ++/* Interrupt Vector 0 is the reset vector. */ ++ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ ++ ++#define INT2_vect_num 3 ++#define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ ++ ++#define PCINT0_vect_num 4 ++#define PCINT0_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */ ++ ++#define PCINT1_vect_num 5 ++#define PCINT1_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */ ++ ++#define PCINT2_vect_num 6 ++#define PCINT2_vect _VECTOR(6) /* Pin Change Interrupt Request 2 */ ++ ++#define PCINT3_vect_num 7 ++#define PCINT3_vect _VECTOR(7) /* Pin Change Interrupt Request 3 */ ++ ++#define WDT_vect_num 8 ++#define WDT_vect _VECTOR(8) /* Watchdog Time-out Interrupt */ ++ ++#define TIMER2_COMPA_vect_num 9 ++#define TIMER2_COMPA_vect _VECTOR(9) /* Timer/Counter2 Compare Match A */ ++ ++#define TIMER2_COMPB_vect_num 10 ++#define TIMER2_COMPB_vect _VECTOR(10) /* Timer/Counter2 Compare Match B */ ++ ++#define TIMER2_OVF_vect_num 11 ++#define TIMER2_OVF_vect _VECTOR(11) /* Timer/Counter2 Overflow */ ++ ++#define TIMER1_CAPT_vect_num 12 ++#define TIMER1_CAPT_vect _VECTOR(12) /* Timer/Counter1 Capture Event */ ++ ++#define TIMER1_COMPA_vect_num 13 ++#define TIMER1_COMPA_vect _VECTOR(13) /* Timer/Counter1 Compare Match A */ ++ ++#define TIMER1_COMPB_vect_num 14 ++#define TIMER1_COMPB_vect _VECTOR(14) /* Timer/Counter1 Compare Match B */ ++ ++#define TIMER1_OVF_vect_num 15 ++#define TIMER1_OVF_vect _VECTOR(15) /* Timer/Counter1 Overflow */ ++ ++#define TIMER0_COMPA_vect_num 16 ++#define TIMER0_COMPA_vect _VECTOR(16) /* Timer/Counter0 Compare Match A */ ++ ++#define TIMER0_COMPB_vect_num 17 ++#define TIMER0_COMPB_vect _VECTOR(17) /* Timer/Counter0 Compare Match B */ ++ ++#define TIMER0_OVF_vect_num 18 ++#define TIMER0_OVF_vect _VECTOR(18) /* Timer/Counter0 Overflow */ ++ ++#define SPI_STC_vect_num 19 ++#define SPI_STC_vect _VECTOR(19) /* SPI Serial Transfer Complete */ ++ ++#define USART0_RX_vect_num 20 ++#define USART0_RX_vect _VECTOR(20) /* USART0, Rx Complete */ ++ ++#define USART0_UDRE_vect_num 21 ++#define USART0_UDRE_vect _VECTOR(21) /* USART0 Data register Empty */ ++ ++#define USART0_TX_vect_num 22 ++#define USART0_TX_vect _VECTOR(22) /* USART0, Tx Complete */ ++ ++#define ANALOG_COMP_vect_num 23 ++#define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */ ++ ++#define ADC_vect_num 24 ++#define ADC_vect _VECTOR(24) /* ADC Conversion Complete */ ++ ++#define EE_READY_vect_num 25 ++#define EE_READY_vect _VECTOR(25) /* EEPROM Ready */ ++ ++#define TWI_vect_num 26 ++#define TWI_vect _VECTOR(26) /* 2-wire Serial Interface */ ++ ++#define SPM_READY_vect_num 27 ++#define SPM_READY_vect _VECTOR(27) /* Store Program Memory Read */ ++ ++#define USART1_RX_vect_num 28 ++#define USART1_RX_vect _VECTOR(28) /* USART1 RX complete */ ++ ++#define USART1_UDRE_vect_num 29 ++#define USART1_UDRE_vect _VECTOR(29) /* USART1 Data Register Empty */ ++ ++#define USART1_TX_vect_num 30 ++#define USART1_TX_vect _VECTOR(30) /* USART1 TX complete */ ++ ++#define TIMER3_CAPT_vect_num 31 ++#define TIMER3_CAPT_vect _VECTOR(31) /* Timer/Counter3 Capture Event */ ++ ++#define TIMER3_COMPA_vect_num 32 ++#define TIMER3_COMPA_vect _VECTOR(32) /* Timer/Counter3 Compare Match A */ ++ ++#define TIMER3_COMPB_vect_num 33 ++#define TIMER3_COMPB_vect _VECTOR(33) /* Timer/Counter3 Compare Match B */ ++ ++#define TIMER3_OVF_vect_num 34 ++#define TIMER3_OVF_vect _VECTOR(34) /* Timer/Counter3 Overflow */ ++ ++#define _VECTORS_SIZE (35 * 4) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE 256 ++#define RAMSTART (0x100) ++#define RAMEND 0x40FF /* Last On-Chip SRAM Location */ ++#define XRAMSIZE 0 ++#define XRAMEND RAMEND ++#define E2END 0xFFF ++#define E2PAGESIZE 8 ++#define FLASHEND 0x1FFFF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ ++#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x97 ++#define SIGNATURE_2 0x05 ++ ++ ++#endif /* _AVR_IOM1284P_H_ */ +diff --git a/include/avr/iom1284rfr2.h b/include/avr/iom1284rfr2.h +new file mode 100644 +index 0000000..16677e3 +--- /dev/null ++++ b/include/avr/iom1284rfr2.h +@@ -0,0 +1,2539 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATMEGA1284RFR2_H_INCLUDED ++#define _AVR_ATMEGA1284RFR2_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom1284rfr2.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDRA7 7 ++#define DDRA6 6 ++#define DDRA5 5 ++#define DDRA4 4 ++#define DDRA3 3 ++#define DDRA2 2 ++#define DDRA1 1 ++#define DDRA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDRC7 7 ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC7 7 ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDRE7 7 ++#define DDRE6 6 ++#define DDRE5 5 ++#define DDRE4 4 ++#define DDRE3 3 ++#define DDRE2 2 ++#define DDRE1 1 ++#define DDRE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE7 7 ++#define PORTE6 6 ++#define PORTE5 5 ++#define PORTE4 4 ++#define PORTE3 3 ++#define PORTE2 2 ++#define PORTE1 1 ++#define PORTE0 0 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDRF7 7 ++#define DDRF6 6 ++#define DDRF5 5 ++#define DDRF4 4 ++#define DDRF3 3 ++#define DDRF2 2 ++#define DDRF1 1 ++#define DDRF0 0 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PORTF7 7 ++#define PORTF6 6 ++#define PORTF5 5 ++#define PORTF4 4 ++#define PORTF3 3 ++#define PORTF2 2 ++#define PORTF1 1 ++#define PORTF0 0 ++ ++#define PING _SFR_IO8(0x12) ++#define PING7 7 ++#define PING6 6 ++#define PING5 5 ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++#define DDRG _SFR_IO8(0x13) ++#define DDRG7 7 ++#define DDRG6 6 ++#define DDRG5 5 ++#define DDRG4 4 ++#define DDRG3 3 ++#define DDRG2 2 ++#define DDRG1 1 ++#define DDRG0 0 ++ ++#define PORTG _SFR_IO8(0x14) ++#define PORTG7 7 ++#define PORTG6 6 ++#define PORTG5 5 ++#define PORTG4 4 ++#define PORTG3 3 ++#define PORTG2 2 ++#define PORTG1 1 ++#define PORTG0 0 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++#define Res0 3 ++#define Res1 4 ++#define Res2 5 ++#define Res3 6 ++#define Res4 7 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define OCF1C 3 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++#define TIFR3 _SFR_IO8(0x18) ++#define TOV3 0 ++#define OCF3A 1 ++#define OCF3B 2 ++#define OCF3C 3 ++#define ICF3 5 ++ ++#define TIFR4 _SFR_IO8(0x19) ++#define TOV4 0 ++#define OCF4A 1 ++#define OCF4B 2 ++#define OCF4C 3 ++#define ICF4 5 ++ ++#define TIFR5 _SFR_IO8(0x1A) ++#define TOV5 0 ++#define OCF5A 1 ++#define OCF5B 2 ++#define OCF5C 3 ++#define ICF5 5 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++#define INTF4 4 ++#define INTF5 5 ++#define INTF6 6 ++#define INTF7 7 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++#define INT3 3 ++#define INT4 4 ++#define INT5 5 ++#define INT6 6 ++#define INT7 7 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define PSRASY 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++ ++#define OCR0A _SFR_IO8(0x27) ++ ++#define OCR0B _SFR_IO8(0x28) ++ ++/* Reserved [0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCDR7 7 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define JTRF 4 ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define JTD 7 ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3A] */ ++ ++#define RAMPZ _SFR_IO8(0x3B) ++#define RAMPZ0 0 ++#define Res5 6 ++#define Res6 7 ++ ++/* Reserved [0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDE 3 ++#define WDCE 4 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62] */ ++ ++#define PRR2 _SFR_MEM8(0x63) ++#define PRRAM0 0 ++#define PRRAM1 1 ++#define PRRAM2 2 ++#define PRRAM3 3 ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRPGA 4 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++#define PRR1 _SFR_MEM8(0x65) ++#define PRUSART1 0 ++#define PRTIM3 3 ++#define PRTIM4 4 ++#define PRTIM5 5 ++#define PRTRX24 6 ++#define Res 7 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define BGCR _SFR_MEM8(0x67) ++#define BGCAL0 0 ++#define BGCAL1 1 ++#define BGCAL2 2 ++#define BGCAL_FINE0 3 ++#define BGCAL_FINE1 4 ++#define BGCAL_FINE2 5 ++#define BGCAL_FINE3 6 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++#define EICRB _SFR_MEM8(0x6A) ++#define ISC40 0 ++#define ISC41 1 ++#define ISC50 2 ++#define ISC51 3 ++#define ISC60 4 ++#define ISC61 5 ++#define ISC70 6 ++#define ISC71 7 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define OCIE1C 3 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++#define TIMSK3 _SFR_MEM8(0x71) ++#define TOIE3 0 ++#define OCIE3A 1 ++#define OCIE3B 2 ++#define OCIE3C 3 ++#define ICIE3 5 ++ ++#define TIMSK4 _SFR_MEM8(0x72) ++#define TOIE4 0 ++#define OCIE4A 1 ++#define OCIE4B 2 ++#define OCIE4C 3 ++#define ICIE4 5 ++ ++#define TIMSK5 _SFR_MEM8(0x73) ++#define TOIE5 0 ++#define OCIE5A 1 ++#define OCIE5B 2 ++#define OCIE5C 3 ++#define ICIE5 5 ++ ++/* Reserved [0x74] */ ++ ++#define NEMCR _SFR_MEM8(0x75) ++#define AEAM0 4 ++#define AEAM1 5 ++#define ENEAM 6 ++ ++/* Reserved [0x76] */ ++ ++#define ADCSRC _SFR_MEM8(0x77) ++#define ADSUT0 0 ++#define ADSUT1 1 ++#define ADSUT2 2 ++#define ADSUT3 3 ++#define ADSUT4 4 ++#define ADTHT0 6 ++#define ADTHT1 7 ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ACME 6 ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define MUX5 3 ++#define ACCH 4 ++#define REFOK 5 ++#define AVDDOK 7 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR2 _SFR_MEM8(0x7D) ++#define ADC8D 0 ++#define ADC9D 1 ++#define ADC10D 2 ++#define ADC11D 3 ++#define ADC12D 4 ++#define ADC13D 5 ++#define ADC14D 6 ++#define ADC15D 7 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1C0 2 ++#define COM1C1 3 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1C 5 ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Combine OCR1CL and OCR1CH */ ++#define OCR1C _SFR_MEM16(0x8C) ++ ++#define OCR1CL _SFR_MEM8(0x8C) ++#define OCR1CH _SFR_MEM8(0x8D) ++ ++/* Reserved [0x8E..0x8F] */ ++ ++#define TCCR3A _SFR_MEM8(0x90) ++#define WGM30 0 ++#define WGM31 1 ++#define COM3C0 2 ++#define COM3C1 3 ++#define COM3B0 4 ++#define COM3B1 5 ++#define COM3A0 6 ++#define COM3A1 7 ++ ++#define TCCR3B _SFR_MEM8(0x91) ++#define CS30 0 ++#define CS31 1 ++#define CS32 2 ++#define WGM32 3 ++#define WGM33 4 ++#define ICES3 6 ++#define ICNC3 7 ++ ++#define TCCR3C _SFR_MEM8(0x92) ++#define FOC3C 5 ++#define FOC3B 6 ++#define FOC3A 7 ++ ++/* Reserved [0x93] */ ++ ++/* Combine TCNT3L and TCNT3H */ ++#define TCNT3 _SFR_MEM16(0x94) ++ ++#define TCNT3L _SFR_MEM8(0x94) ++#define TCNT3H _SFR_MEM8(0x95) ++ ++/* Combine ICR3L and ICR3H */ ++#define ICR3 _SFR_MEM16(0x96) ++ ++#define ICR3L _SFR_MEM8(0x96) ++#define ICR3H _SFR_MEM8(0x97) ++ ++/* Combine OCR3AL and OCR3AH */ ++#define OCR3A _SFR_MEM16(0x98) ++ ++#define OCR3AL _SFR_MEM8(0x98) ++#define OCR3AH _SFR_MEM8(0x99) ++ ++/* Combine OCR3BL and OCR3BH */ ++#define OCR3B _SFR_MEM16(0x9A) ++ ++#define OCR3BL _SFR_MEM8(0x9A) ++#define OCR3BH _SFR_MEM8(0x9B) ++ ++/* Combine OCR3CL and OCR3CH */ ++#define OCR3C _SFR_MEM16(0x9C) ++ ++#define OCR3CL _SFR_MEM8(0x9C) ++#define OCR3CH _SFR_MEM8(0x9D) ++ ++/* Reserved [0x9E..0x9F] */ ++ ++#define TCCR4A _SFR_MEM8(0xA0) ++#define WGM40 0 ++#define WGM41 1 ++#define COM4C0 2 ++#define COM4C1 3 ++#define COM4B0 4 ++#define COM4B1 5 ++#define COM4A0 6 ++#define COM4A1 7 ++ ++#define TCCR4B _SFR_MEM8(0xA1) ++#define CS40 0 ++#define CS41 1 ++#define CS42 2 ++#define WGM42 3 ++#define WGM43 4 ++#define ICES4 6 ++#define ICNC4 7 ++ ++#define TCCR4C _SFR_MEM8(0xA2) ++#define FOC4C 5 ++#define FOC4B 6 ++#define FOC4A 7 ++ ++/* Reserved [0xA3] */ ++ ++/* Combine TCNT4L and TCNT4H */ ++#define TCNT4 _SFR_MEM16(0xA4) ++ ++#define TCNT4L _SFR_MEM8(0xA4) ++#define TCNT4H _SFR_MEM8(0xA5) ++ ++/* Combine ICR4L and ICR4H */ ++#define ICR4 _SFR_MEM16(0xA6) ++ ++#define ICR4L _SFR_MEM8(0xA6) ++#define ICR4H _SFR_MEM8(0xA7) ++ ++/* Combine OCR4AL and OCR4AH */ ++#define OCR4A _SFR_MEM16(0xA8) ++ ++#define OCR4AL _SFR_MEM8(0xA8) ++#define OCR4AH _SFR_MEM8(0xA9) ++ ++/* Combine OCR4BL and OCR4BH */ ++#define OCR4B _SFR_MEM16(0xAA) ++ ++#define OCR4BL _SFR_MEM8(0xAA) ++#define OCR4BH _SFR_MEM8(0xAB) ++ ++/* Combine OCR4CL and OCR4CH */ ++#define OCR4C _SFR_MEM16(0xAC) ++ ++#define OCR4CL _SFR_MEM8(0xAC) ++#define OCR4CH _SFR_MEM8(0xAD) ++ ++/* Reserved [0xAE..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++#define OCR2B _SFR_MEM8(0xB4) ++ ++/* Reserved [0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++#define EXCLKAMR 7 ++ ++/* Reserved [0xB7] */ ++ ++#define TWBR _SFR_MEM8(0xB8) ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++#define IRQ_MASK1 _SFR_MEM8(0xBE) ++#define TX_START_EN 0 ++#define MAF_0_AMI_EN 1 ++#define MAF_1_AMI_EN 2 ++#define MAF_2_AMI_EN 3 ++#define MAF_3_AMI_EN 4 ++ ++#define IRQ_STATUS1 _SFR_MEM8(0xBF) ++#define TX_START 0 ++#define MAF_0_AMI 1 ++#define MAF_1_AMI 2 ++#define MAF_2_AMI 3 ++#define MAF_3_AMI 4 ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++#define UCPHA0 1 ++#define UDORD0 2 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0xC6) ++ ++/* Reserved [0xC7] */ ++ ++#define UCSR1A _SFR_MEM8(0xC8) ++#define MPCM1 0 ++#define U2X1 1 ++#define UPE1 2 ++#define DOR1 3 ++#define FE1 4 ++#define UDRE1 5 ++#define TXC1 6 ++#define RXC1 7 ++ ++#define UCSR1B _SFR_MEM8(0xC9) ++#define TXB81 0 ++#define RXB81 1 ++#define UCSZ12 2 ++#define TXEN1 3 ++#define RXEN1 4 ++#define UDRIE1 5 ++#define TXCIE1 6 ++#define RXCIE1 7 ++ ++#define UCSR1C _SFR_MEM8(0xCA) ++#define UCPOL1 0 ++#define UCSZ10 1 ++#define UCSZ11 2 ++#define USBS1 3 ++#define UPM10 4 ++#define UPM11 5 ++#define UMSEL10 6 ++#define UMSEL11 7 ++#define UCPHA1 1 ++#define UDORD1 2 ++ ++/* Reserved [0xCB] */ ++ ++/* Combine UBRR1L and UBRR1H */ ++#define UBRR1 _SFR_MEM16(0xCC) ++ ++#define UBRR1L _SFR_MEM8(0xCC) ++#define UBRR1H _SFR_MEM8(0xCD) ++ ++#define UDR1 _SFR_MEM8(0xCE) ++ ++/* Reserved [0xCF..0xD6] */ ++ ++#define SCRSTRLL _SFR_MEM8(0xD7) ++#define SCRSTRLL0 0 ++#define SCRSTRLL1 1 ++#define SCRSTRLL2 2 ++#define SCRSTRLL3 3 ++#define SCRSTRLL4 4 ++#define SCRSTRLL5 5 ++#define SCRSTRLL6 6 ++#define SCRSTRLL7 7 ++ ++#define SCRSTRLH _SFR_MEM8(0xD8) ++#define SCRSTRLH0 0 ++#define SCRSTRLH1 1 ++#define SCRSTRLH2 2 ++#define SCRSTRLH3 3 ++#define SCRSTRLH4 4 ++#define SCRSTRLH5 5 ++#define SCRSTRLH6 6 ++#define SCRSTRLH7 7 ++ ++#define SCRSTRHL _SFR_MEM8(0xD9) ++#define SCRSTRHL0 0 ++#define SCRSTRHL1 1 ++#define SCRSTRHL2 2 ++#define SCRSTRHL3 3 ++#define SCRSTRHL4 4 ++#define SCRSTRHL5 5 ++#define SCRSTRHL6 6 ++#define SCRSTRHL7 7 ++ ++#define SCRSTRHH _SFR_MEM8(0xDA) ++#define SCRSTRHH0 0 ++#define SCRSTRHH1 1 ++#define SCRSTRHH2 2 ++#define SCRSTRHH3 3 ++#define SCRSTRHH4 4 ++#define SCRSTRHH5 5 ++#define SCRSTRHH6 6 ++#define SCRSTRHH7 7 ++ ++#define SCCSR _SFR_MEM8(0xDB) ++#define SCCS10 0 ++#define SCCS11 1 ++#define SCCS20 2 ++#define SCCS21 3 ++#define SCCS30 4 ++#define SCCS31 5 ++ ++#define SCCR0 _SFR_MEM8(0xDC) ++#define SCCMP1 0 ++#define SCCMP2 1 ++#define SCCMP3 2 ++#define SCTSE 3 ++#define SCCKSEL 4 ++#define SCEN 5 ++#define SCMBTS 6 ++#define SCRES 7 ++ ++#define SCCR1 _SFR_MEM8(0xDD) ++#define SCENBO 0 ++#define SCEECLK 1 ++#define SCCKDIV0 2 ++#define SCCKDIV1 3 ++#define SCCKDIV2 4 ++#define SCBTSM 5 ++ ++#define SCSR _SFR_MEM8(0xDE) ++#define SCBSY 0 ++ ++#define SCIRQM _SFR_MEM8(0xDF) ++#define IRQMCP1 0 ++#define IRQMCP2 1 ++#define IRQMCP3 2 ++#define IRQMOF 3 ++#define IRQMBO 4 ++ ++#define SCIRQS _SFR_MEM8(0xE0) ++#define IRQSCP1 0 ++#define IRQSCP2 1 ++#define IRQSCP3 2 ++#define IRQSOF 3 ++#define IRQSBO 4 ++ ++#define SCCNTLL _SFR_MEM8(0xE1) ++#define SCCNTLL0 0 ++#define SCCNTLL1 1 ++#define SCCNTLL2 2 ++#define SCCNTLL3 3 ++#define SCCNTLL4 4 ++#define SCCNTLL5 5 ++#define SCCNTLL6 6 ++#define SCCNTLL7 7 ++ ++#define SCCNTLH _SFR_MEM8(0xE2) ++#define SCCNTLH0 0 ++#define SCCNTLH1 1 ++#define SCCNTLH2 2 ++#define SCCNTLH3 3 ++#define SCCNTLH4 4 ++#define SCCNTLH5 5 ++#define SCCNTLH6 6 ++#define SCCNTLH7 7 ++ ++#define SCCNTHL _SFR_MEM8(0xE3) ++#define SCCNTHL0 0 ++#define SCCNTHL1 1 ++#define SCCNTHL2 2 ++#define SCCNTHL3 3 ++#define SCCNTHL4 4 ++#define SCCNTHL5 5 ++#define SCCNTHL6 6 ++#define SCCNTHL7 7 ++ ++#define SCCNTHH _SFR_MEM8(0xE4) ++#define SCCNTHH0 0 ++#define SCCNTHH1 1 ++#define SCCNTHH2 2 ++#define SCCNTHH3 3 ++#define SCCNTHH4 4 ++#define SCCNTHH5 5 ++#define SCCNTHH6 6 ++#define SCCNTHH7 7 ++ ++#define SCBTSRLL _SFR_MEM8(0xE5) ++#define SCBTSRLL0 0 ++#define SCBTSRLL1 1 ++#define SCBTSRLL2 2 ++#define SCBTSRLL3 3 ++#define SCBTSRLL4 4 ++#define SCBTSRLL5 5 ++#define SCBTSRLL6 6 ++#define SCBTSRLL7 7 ++ ++#define SCBTSRLH _SFR_MEM8(0xE6) ++#define SCBTSRLH0 0 ++#define SCBTSRLH1 1 ++#define SCBTSRLH2 2 ++#define SCBTSRLH3 3 ++#define SCBTSRLH4 4 ++#define SCBTSRLH5 5 ++#define SCBTSRLH6 6 ++#define SCBTSRLH7 7 ++ ++#define SCBTSRHL _SFR_MEM8(0xE7) ++#define SCBTSRHL0 0 ++#define SCBTSRHL1 1 ++#define SCBTSRHL2 2 ++#define SCBTSRHL3 3 ++#define SCBTSRHL4 4 ++#define SCBTSRHL5 5 ++#define SCBTSRHL6 6 ++#define SCBTSRHL7 7 ++ ++#define SCBTSRHH _SFR_MEM8(0xE8) ++#define SCBTSRHH0 0 ++#define SCBTSRHH1 1 ++#define SCBTSRHH2 2 ++#define SCBTSRHH3 3 ++#define SCBTSRHH4 4 ++#define SCBTSRHH5 5 ++#define SCBTSRHH6 6 ++#define SCBTSRHH7 7 ++ ++#define SCTSRLL _SFR_MEM8(0xE9) ++#define SCTSRLL0 0 ++#define SCTSRLL1 1 ++#define SCTSRLL2 2 ++#define SCTSRLL3 3 ++#define SCTSRLL4 4 ++#define SCTSRLL5 5 ++#define SCTSRLL6 6 ++#define SCTSRLL7 7 ++ ++#define SCTSRLH _SFR_MEM8(0xEA) ++#define SCTSRLH0 0 ++#define SCTSRLH1 1 ++#define SCTSRLH2 2 ++#define SCTSRLH3 3 ++#define SCTSRLH4 4 ++#define SCTSRLH5 5 ++#define SCTSRLH6 6 ++#define SCTSRLH7 7 ++ ++#define SCTSRHL _SFR_MEM8(0xEB) ++#define SCTSRHL0 0 ++#define SCTSRHL1 1 ++#define SCTSRHL2 2 ++#define SCTSRHL3 3 ++#define SCTSRHL4 4 ++#define SCTSRHL5 5 ++#define SCTSRHL6 6 ++#define SCTSRHL7 7 ++ ++#define SCTSRHH _SFR_MEM8(0xEC) ++#define SCTSRHH0 0 ++#define SCTSRHH1 1 ++#define SCTSRHH2 2 ++#define SCTSRHH3 3 ++#define SCTSRHH4 4 ++#define SCTSRHH5 5 ++#define SCTSRHH6 6 ++#define SCTSRHH7 7 ++ ++#define SCOCR3LL _SFR_MEM8(0xED) ++#define SCOCR3LL0 0 ++#define SCOCR3LL1 1 ++#define SCOCR3LL2 2 ++#define SCOCR3LL3 3 ++#define SCOCR3LL4 4 ++#define SCOCR3LL5 5 ++#define SCOCR3LL6 6 ++#define SCOCR3LL7 7 ++ ++#define SCOCR3LH _SFR_MEM8(0xEE) ++#define SCOCR3LH0 0 ++#define SCOCR3LH1 1 ++#define SCOCR3LH2 2 ++#define SCOCR3LH3 3 ++#define SCOCR3LH4 4 ++#define SCOCR3LH5 5 ++#define SCOCR3LH6 6 ++#define SCOCR3LH7 7 ++ ++#define SCOCR3HL _SFR_MEM8(0xEF) ++#define SCOCR3HL0 0 ++#define SCOCR3HL1 1 ++#define SCOCR3HL2 2 ++#define SCOCR3HL3 3 ++#define SCOCR3HL4 4 ++#define SCOCR3HL5 5 ++#define SCOCR3HL6 6 ++#define SCOCR3HL7 7 ++ ++#define SCOCR3HH _SFR_MEM8(0xF0) ++#define SCOCR3HH0 0 ++#define SCOCR3HH1 1 ++#define SCOCR3HH2 2 ++#define SCOCR3HH3 3 ++#define SCOCR3HH4 4 ++#define SCOCR3HH5 5 ++#define SCOCR3HH6 6 ++#define SCOCR3HH7 7 ++ ++#define SCOCR2LL _SFR_MEM8(0xF1) ++#define SCOCR2LL0 0 ++#define SCOCR2LL1 1 ++#define SCOCR2LL2 2 ++#define SCOCR2LL3 3 ++#define SCOCR2LL4 4 ++#define SCOCR2LL5 5 ++#define SCOCR2LL6 6 ++#define SCOCR2LL7 7 ++ ++#define SCOCR2LH _SFR_MEM8(0xF2) ++#define SCOCR2LH0 0 ++#define SCOCR2LH1 1 ++#define SCOCR2LH2 2 ++#define SCOCR2LH3 3 ++#define SCOCR2LH4 4 ++#define SCOCR2LH5 5 ++#define SCOCR2LH6 6 ++#define SCOCR2LH7 7 ++ ++#define SCOCR2HL _SFR_MEM8(0xF3) ++#define SCOCR2HL0 0 ++#define SCOCR2HL1 1 ++#define SCOCR2HL2 2 ++#define SCOCR2HL3 3 ++#define SCOCR2HL4 4 ++#define SCOCR2HL5 5 ++#define SCOCR2HL6 6 ++#define SCOCR2HL7 7 ++ ++#define SCOCR2HH _SFR_MEM8(0xF4) ++#define SCOCR2HH0 0 ++#define SCOCR2HH1 1 ++#define SCOCR2HH2 2 ++#define SCOCR2HH3 3 ++#define SCOCR2HH4 4 ++#define SCOCR2HH5 5 ++#define SCOCR2HH6 6 ++#define SCOCR2HH7 7 ++ ++#define SCOCR1LL _SFR_MEM8(0xF5) ++#define SCOCR1LL0 0 ++#define SCOCR1LL1 1 ++#define SCOCR1LL2 2 ++#define SCOCR1LL3 3 ++#define SCOCR1LL4 4 ++#define SCOCR1LL5 5 ++#define SCOCR1LL6 6 ++#define SCOCR1LL7 7 ++ ++#define SCOCR1LH _SFR_MEM8(0xF6) ++#define SCOCR1LH0 0 ++#define SCOCR1LH1 1 ++#define SCOCR1LH2 2 ++#define SCOCR1LH3 3 ++#define SCOCR1LH4 4 ++#define SCOCR1LH5 5 ++#define SCOCR1LH6 6 ++#define SCOCR1LH7 7 ++ ++#define SCOCR1HL _SFR_MEM8(0xF7) ++#define SCOCR1HL0 0 ++#define SCOCR1HL1 1 ++#define SCOCR1HL2 2 ++#define SCOCR1HL3 3 ++#define SCOCR1HL4 4 ++#define SCOCR1HL5 5 ++#define SCOCR1HL6 6 ++#define SCOCR1HL7 7 ++ ++#define SCOCR1HH _SFR_MEM8(0xF8) ++#define SCOCR1HH0 0 ++#define SCOCR1HH1 1 ++#define SCOCR1HH2 2 ++#define SCOCR1HH3 3 ++#define SCOCR1HH4 4 ++#define SCOCR1HH5 5 ++#define SCOCR1HH6 6 ++#define SCOCR1HH7 7 ++ ++#define SCTSTRLL _SFR_MEM8(0xF9) ++#define SCTSTRLL0 0 ++#define SCTSTRLL1 1 ++#define SCTSTRLL2 2 ++#define SCTSTRLL3 3 ++#define SCTSTRLL4 4 ++#define SCTSTRLL5 5 ++#define SCTSTRLL6 6 ++#define SCTSTRLL7 7 ++ ++#define SCTSTRLH _SFR_MEM8(0xFA) ++#define SCTSTRLH0 0 ++#define SCTSTRLH1 1 ++#define SCTSTRLH2 2 ++#define SCTSTRLH3 3 ++#define SCTSTRLH4 4 ++#define SCTSTRLH5 5 ++#define SCTSTRLH6 6 ++#define SCTSTRLH7 7 ++ ++#define SCTSTRHL _SFR_MEM8(0xFB) ++#define SCTSTRHL0 0 ++#define SCTSTRHL1 1 ++#define SCTSTRHL2 2 ++#define SCTSTRHL3 3 ++#define SCTSTRHL4 4 ++#define SCTSTRHL5 5 ++#define SCTSTRHL6 6 ++#define SCTSTRHL7 7 ++ ++#define SCTSTRHH _SFR_MEM8(0xFC) ++#define SCTSTRHH0 0 ++#define SCTSTRHH1 1 ++#define SCTSTRHH2 2 ++#define SCTSTRHH3 3 ++#define SCTSTRHH4 4 ++#define SCTSTRHH5 5 ++#define SCTSTRHH6 6 ++#define SCTSTRHH7 7 ++ ++/* Reserved [0xFD..0x10B] */ ++ ++#define MAFCR0 _SFR_MEM8(0x10C) ++#define MAF0EN 0 ++#define MAF1EN 1 ++#define MAF2EN 2 ++#define MAF3EN 3 ++ ++#define MAFCR1 _SFR_MEM8(0x10D) ++#define AACK_0_I_AM_COORD 0 ++#define AACK_0_SET_PD 1 ++#define AACK_1_I_AM_COORD 2 ++#define AACK_1_SET_PD 3 ++#define AACK_2_I_AM_COORD 4 ++#define AACK_2_SET_PD 5 ++#define AACK_3_I_AM_COORD 6 ++#define AACK_3_SET_PD 7 ++ ++#define MAFSA0L _SFR_MEM8(0x10E) ++#define MAFSA0L0 0 ++#define MAFSA0L1 1 ++#define MAFSA0L2 2 ++#define MAFSA0L3 3 ++#define MAFSA0L4 4 ++#define MAFSA0L5 5 ++#define MAFSA0L6 6 ++#define MAFSA0L7 7 ++ ++#define MAFSA0H _SFR_MEM8(0x10F) ++#define MAFSA0H0 0 ++#define MAFSA0H1 1 ++#define MAFSA0H2 2 ++#define MAFSA0H3 3 ++#define MAFSA0H4 4 ++#define MAFSA0H5 5 ++#define MAFSA0H6 6 ++#define MAFSA0H7 7 ++ ++#define MAFPA0L _SFR_MEM8(0x110) ++#define MAFPA0L0 0 ++#define MAFPA0L1 1 ++#define MAFPA0L2 2 ++#define MAFPA0L3 3 ++#define MAFPA0L4 4 ++#define MAFPA0L5 5 ++#define MAFPA0L6 6 ++#define MAFPA0L7 7 ++ ++#define MAFPA0H _SFR_MEM8(0x111) ++#define MAFPA0H0 0 ++#define MAFPA0H1 1 ++#define MAFPA0H2 2 ++#define MAFPA0H3 3 ++#define MAFPA0H4 4 ++#define MAFPA0H5 5 ++#define MAFPA0H6 6 ++#define MAFPA0H7 7 ++ ++#define MAFSA1L _SFR_MEM8(0x112) ++#define MAFSA1L0 0 ++#define MAFSA1L1 1 ++#define MAFSA1L2 2 ++#define MAFSA1L3 3 ++#define MAFSA1L4 4 ++#define MAFSA1L5 5 ++#define MAFSA1L6 6 ++#define MAFSA1L7 7 ++ ++#define MAFSA1H _SFR_MEM8(0x113) ++#define MAFSA1H0 0 ++#define MAFSA1H1 1 ++#define MAFSA1H2 2 ++#define MAFSA1H3 3 ++#define MAFSA1H4 4 ++#define MAFSA1H5 5 ++#define MAFSA1H6 6 ++#define MAFSA1H7 7 ++ ++#define MAFPA1L _SFR_MEM8(0x114) ++#define MAFPA1L0 0 ++#define MAFPA1L1 1 ++#define MAFPA1L2 2 ++#define MAFPA1L3 3 ++#define MAFPA1L4 4 ++#define MAFPA1L5 5 ++#define MAFPA1L6 6 ++#define MAFPA1L7 7 ++ ++#define MAFPA1H _SFR_MEM8(0x115) ++#define MAFPA1H0 0 ++#define MAFPA1H1 1 ++#define MAFPA1H2 2 ++#define MAFPA1H3 3 ++#define MAFPA1H4 4 ++#define MAFPA1H5 5 ++#define MAFPA1H6 6 ++#define MAFPA1H7 7 ++ ++#define MAFSA2L _SFR_MEM8(0x116) ++#define MAFSA2L0 0 ++#define MAFSA2L1 1 ++#define MAFSA2L2 2 ++#define MAFSA2L3 3 ++#define MAFSA2L4 4 ++#define MAFSA2L5 5 ++#define MAFSA2L6 6 ++#define MAFSA2L7 7 ++ ++#define MAFSA2H _SFR_MEM8(0x117) ++#define MAFSA2H0 0 ++#define MAFSA2H1 1 ++#define MAFSA2H2 2 ++#define MAFSA2H3 3 ++#define MAFSA2H4 4 ++#define MAFSA2H5 5 ++#define MAFSA2H6 6 ++#define MAFSA2H7 7 ++ ++#define MAFPA2L _SFR_MEM8(0x118) ++#define MAFPA2L0 0 ++#define MAFPA2L1 1 ++#define MAFPA2L2 2 ++#define MAFPA2L3 3 ++#define MAFPA2L4 4 ++#define MAFPA2L5 5 ++#define MAFPA2L6 6 ++#define MAFPA2L7 7 ++ ++#define MAFPA2H _SFR_MEM8(0x119) ++#define MAFPA2H0 0 ++#define MAFPA2H1 1 ++#define MAFPA2H2 2 ++#define MAFPA2H3 3 ++#define MAFPA2H4 4 ++#define MAFPA2H5 5 ++#define MAFPA2H6 6 ++#define MAFPA2H7 7 ++ ++#define MAFSA3L _SFR_MEM8(0x11A) ++#define MAFSA3L0 0 ++#define MAFSA3L1 1 ++#define MAFSA3L2 2 ++#define MAFSA3L3 3 ++#define MAFSA3L4 4 ++#define MAFSA3L5 5 ++#define MAFSA3L6 6 ++#define MAFSA3L7 7 ++ ++#define MAFSA3H _SFR_MEM8(0x11B) ++#define MAFSA3H0 0 ++#define MAFSA3H1 1 ++#define MAFSA3H2 2 ++#define MAFSA3H3 3 ++#define MAFSA3H4 4 ++#define MAFSA3H5 5 ++#define MAFSA3H6 6 ++#define MAFSA3H7 7 ++ ++#define MAFPA3L _SFR_MEM8(0x11C) ++#define MAFPA3L0 0 ++#define MAFPA3L1 1 ++#define MAFPA3L2 2 ++#define MAFPA3L3 3 ++#define MAFPA3L4 4 ++#define MAFPA3L5 5 ++#define MAFPA3L6 6 ++#define MAFPA3L7 7 ++ ++#define MAFPA3H _SFR_MEM8(0x11D) ++#define MAFPA3H0 0 ++#define MAFPA3H1 1 ++#define MAFPA3H2 2 ++#define MAFPA3H3 3 ++#define MAFPA3H4 4 ++#define MAFPA3H5 5 ++#define MAFPA3H6 6 ++#define MAFPA3H7 7 ++ ++/* Reserved [0x11E..0x11F] */ ++ ++#define TCCR5A _SFR_MEM8(0x120) ++#define WGM50 0 ++#define WGM51 1 ++#define COM5C0 2 ++#define COM5C1 3 ++#define COM5B0 4 ++#define COM5B1 5 ++#define COM5A0 6 ++#define COM5A1 7 ++ ++#define TCCR5B _SFR_MEM8(0x121) ++#define CS50 0 ++#define CS51 1 ++#define CS52 2 ++#define WGM52 3 ++#define WGM53 4 ++#define ICES5 6 ++#define ICNC5 7 ++ ++#define TCCR5C _SFR_MEM8(0x122) ++#define FOC5C 5 ++#define FOC5B 6 ++#define FOC5A 7 ++ ++/* Reserved [0x123] */ ++ ++/* Combine TCNT5L and TCNT5H */ ++#define TCNT5 _SFR_MEM16(0x124) ++ ++#define TCNT5L _SFR_MEM8(0x124) ++#define TCNT5H _SFR_MEM8(0x125) ++ ++/* Combine ICR5L and ICR5H */ ++#define ICR5 _SFR_MEM16(0x126) ++ ++#define ICR5L _SFR_MEM8(0x126) ++#define ICR5H _SFR_MEM8(0x127) ++ ++/* Combine OCR5AL and OCR5AH */ ++#define OCR5A _SFR_MEM16(0x128) ++ ++#define OCR5AL _SFR_MEM8(0x128) ++#define OCR5AH _SFR_MEM8(0x129) ++ ++/* Combine OCR5BL and OCR5BH */ ++#define OCR5B _SFR_MEM16(0x12A) ++ ++#define OCR5BL _SFR_MEM8(0x12A) ++#define OCR5BH _SFR_MEM8(0x12B) ++ ++/* Combine OCR5CL and OCR5CH */ ++#define OCR5C _SFR_MEM16(0x12C) ++ ++#define OCR5CL _SFR_MEM8(0x12C) ++#define OCR5CH _SFR_MEM8(0x12D) ++ ++/* Reserved [0x12E] */ ++ ++#define LLCR _SFR_MEM8(0x12F) ++#define LLENCAL 0 ++#define LLSHORT 1 ++#define LLTCO 2 ++#define LLCAL 3 ++#define LLCOMP 4 ++#define LLDONE 5 ++ ++#define LLDRL _SFR_MEM8(0x130) ++#define LLDRL0 0 ++#define LLDRL1 1 ++#define LLDRL2 2 ++#define LLDRL3 3 ++ ++#define LLDRH _SFR_MEM8(0x131) ++#define LLDRH0 0 ++#define LLDRH1 1 ++#define LLDRH2 2 ++#define LLDRH3 3 ++#define LLDRH4 4 ++ ++#define DRTRAM3 _SFR_MEM8(0x132) ++#define ENDRT 4 ++#define DRTSWOK 5 ++ ++#define DRTRAM2 _SFR_MEM8(0x133) ++ ++#define DRTRAM1 _SFR_MEM8(0x134) ++ ++#define DRTRAM0 _SFR_MEM8(0x135) ++ ++#define DPDS0 _SFR_MEM8(0x136) ++#define PBDRV0 0 ++#define PBDRV1 1 ++#define PDDRV0 2 ++#define PDDRV1 3 ++#define PEDRV0 4 ++#define PEDRV1 5 ++#define PFDRV0 6 ++#define PFDRV1 7 ++ ++#define DPDS1 _SFR_MEM8(0x137) ++#define PGDRV0 0 ++#define PGDRV1 1 ++ ++#define PARCR _SFR_MEM8(0x138) ++#define PARUFI 0 ++#define PARDFI 1 ++#define PALTU0 2 ++#define PALTU1 3 ++#define PALTU2 4 ++#define PALTD0 5 ++#define PALTD1 6 ++#define PALTD2 7 ++ ++#define TRXPR _SFR_MEM8(0x139) ++#define TRXRST 0 ++#define SLPTR 1 ++ ++/* Reserved [0x13A..0x13B] */ ++ ++#define AES_CTRL _SFR_MEM8(0x13C) ++#define AES_IM 2 ++#define AES_DIR 3 ++#define AES_MODE 5 ++#define AES_REQUEST 7 ++ ++#define AES_STATUS _SFR_MEM8(0x13D) ++#define AES_DONE 0 ++#define AES_ER 7 ++ ++#define AES_STATE _SFR_MEM8(0x13E) ++#define AES_STATE0 0 ++#define AES_STATE1 1 ++#define AES_STATE2 2 ++#define AES_STATE3 3 ++#define AES_STATE4 4 ++#define AES_STATE5 5 ++#define AES_STATE6 6 ++#define AES_STATE7 7 ++ ++#define AES_KEY _SFR_MEM8(0x13F) ++#define AES_KEY0 0 ++#define AES_KEY1 1 ++#define AES_KEY2 2 ++#define AES_KEY3 3 ++#define AES_KEY4 4 ++#define AES_KEY5 5 ++#define AES_KEY6 6 ++#define AES_KEY7 7 ++ ++/* Reserved [0x140] */ ++ ++#define TRX_STATUS _SFR_MEM8(0x141) ++#define TRX_STATUS0 0 ++#define TRX_STATUS1 1 ++#define TRX_STATUS2 2 ++#define TRX_STATUS3 3 ++#define TRX_STATUS4 4 ++#define TST_STATUS 5 ++#define CCA_STATUS 6 ++#define CCA_DONE 7 ++ ++#define TRX_STATE _SFR_MEM8(0x142) ++#define TRX_CMD0 0 ++#define TRX_CMD1 1 ++#define TRX_CMD2 2 ++#define TRX_CMD3 3 ++#define TRX_CMD4 4 ++#define TRAC_STATUS0 5 ++#define TRAC_STATUS1 6 ++#define TRAC_STATUS2 7 ++ ++#define TRX_CTRL_0 _SFR_MEM8(0x143) ++#define PMU_IF_INV 4 ++#define PMU_START 5 ++#define PMU_EN 6 ++#define Res7 7 ++ ++#define TRX_CTRL_1 _SFR_MEM8(0x144) ++#define PLL_TX_FLT 4 ++#define TX_AUTO_CRC_ON 5 ++#define IRQ_2_EXT_EN 6 ++#define PA_EXT_EN 7 ++ ++#define PHY_TX_PWR _SFR_MEM8(0x145) ++#define TX_PWR0 0 ++#define TX_PWR1 1 ++#define TX_PWR2 2 ++#define TX_PWR3 3 ++ ++#define PHY_RSSI _SFR_MEM8(0x146) ++#define RSSI0 0 ++#define RSSI1 1 ++#define RSSI2 2 ++#define RSSI3 3 ++#define RSSI4 4 ++#define RND_VALUE0 5 ++#define RND_VALUE1 6 ++#define RX_CRC_VALID 7 ++ ++#define PHY_ED_LEVEL _SFR_MEM8(0x147) ++#define ED_LEVEL0 0 ++#define ED_LEVEL1 1 ++#define ED_LEVEL2 2 ++#define ED_LEVEL3 3 ++#define ED_LEVEL4 4 ++#define ED_LEVEL5 5 ++#define ED_LEVEL6 6 ++#define ED_LEVEL7 7 ++ ++#define PHY_CC_CCA _SFR_MEM8(0x148) ++#define CHANNEL0 0 ++#define CHANNEL1 1 ++#define CHANNEL2 2 ++#define CHANNEL3 3 ++#define CHANNEL4 4 ++#define CCA_MODE0 5 ++#define CCA_MODE1 6 ++#define CCA_REQUEST 7 ++ ++#define CCA_THRES _SFR_MEM8(0x149) ++#define CCA_ED_THRES0 0 ++#define CCA_ED_THRES1 1 ++#define CCA_ED_THRES2 2 ++#define CCA_ED_THRES3 3 ++#define CCA_CS_THRES0 4 ++#define CCA_CS_THRES1 5 ++#define CCA_CS_THRES2 6 ++#define CCA_CS_THRES3 7 ++ ++#define RX_CTRL _SFR_MEM8(0x14A) ++#define PDT_THRES0 0 ++#define PDT_THRES1 1 ++#define PDT_THRES2 2 ++#define PDT_THRES3 3 ++ ++#define SFD_VALUE _SFR_MEM8(0x14B) ++#define SFD_VALUE0 0 ++#define SFD_VALUE1 1 ++#define SFD_VALUE2 2 ++#define SFD_VALUE3 3 ++#define SFD_VALUE4 4 ++#define SFD_VALUE5 5 ++#define SFD_VALUE6 6 ++#define SFD_VALUE7 7 ++ ++#define TRX_CTRL_2 _SFR_MEM8(0x14C) ++#define OQPSK_DATA_RATE0 0 ++#define OQPSK_DATA_RATE1 1 ++#define RX_SAFE_MODE 7 ++ ++#define ANT_DIV _SFR_MEM8(0x14D) ++#define ANT_CTRL0 0 ++#define ANT_CTRL1 1 ++#define ANT_EXT_SW_EN 2 ++#define ANT_DIV_EN 3 ++#define ANT_SEL 7 ++ ++#define IRQ_MASK _SFR_MEM8(0x14E) ++#define PLL_LOCK_EN 0 ++#define PLL_UNLOCK_EN 1 ++#define RX_START_EN 2 ++#define RX_END_EN 3 ++#define CCA_ED_DONE_EN 4 ++#define AMI_EN 5 ++#define TX_END_EN 6 ++#define AWAKE_EN 7 ++ ++#define IRQ_STATUS _SFR_MEM8(0x14F) ++#define PLL_LOCK 0 ++#define PLL_UNLOCK 1 ++#define RX_START 2 ++#define RX_END 3 ++#define CCA_ED_DONE 4 ++#define AMI 5 ++#define TX_END 6 ++#define AWAKE 7 ++ ++#define VREG_CTRL _SFR_MEM8(0x150) ++#define DVDD_OK 2 ++#define DVREG_EXT 3 ++#define AVDD_OK 6 ++#define AVREG_EXT 7 ++ ++#define BATMON _SFR_MEM8(0x151) ++#define BATMON_VTH0 0 ++#define BATMON_VTH1 1 ++#define BATMON_VTH2 2 ++#define BATMON_VTH3 3 ++#define BATMON_HR 4 ++#define BATMON_OK 5 ++#define BAT_LOW_EN 6 ++#define BAT_LOW 7 ++ ++#define XOSC_CTRL _SFR_MEM8(0x152) ++#define XTAL_TRIM0 0 ++#define XTAL_TRIM1 1 ++#define XTAL_TRIM2 2 ++#define XTAL_TRIM3 3 ++#define XTAL_MODE0 4 ++#define XTAL_MODE1 5 ++#define XTAL_MODE2 6 ++#define XTAL_MODE3 7 ++ ++#define CC_CTRL_0 _SFR_MEM8(0x153) ++#define CC_NUMBER0 0 ++#define CC_NUMBER1 1 ++#define CC_NUMBER2 2 ++#define CC_NUMBER3 3 ++#define CC_NUMBER4 4 ++#define CC_NUMBER5 5 ++#define CC_NUMBER6 6 ++#define CC_NUMBER7 7 ++ ++#define CC_CTRL_1 _SFR_MEM8(0x154) ++#define CC_BAND0 0 ++#define CC_BAND1 1 ++#define CC_BAND2 2 ++#define CC_BAND3 3 ++ ++#define RX_SYN _SFR_MEM8(0x155) ++#define RX_PDT_LEVEL0 0 ++#define RX_PDT_LEVEL1 1 ++#define RX_PDT_LEVEL2 2 ++#define RX_PDT_LEVEL3 3 ++#define RX_OVERRIDE 6 ++#define RX_PDT_DIS 7 ++ ++#define TRX_RPC _SFR_MEM8(0x156) ++#define XAH_RPC_EN 0 ++#define IPAN_RPC_EN 1 ++#define PLL_RPC_EN 3 ++#define PDT_RPC_EN 4 ++#define RX_RPC_EN 5 ++#define RX_RPC_CTRL0 6 ++#define RX_RPC_CTRL1 7 ++ ++#define XAH_CTRL_1 _SFR_MEM8(0x157) ++#define AACK_PROM_MODE 1 ++#define AACK_ACK_TIME 2 ++#define AACK_UPLD_RES_FT 4 ++#define AACK_FLTR_RES_FT 5 ++ ++#define FTN_CTRL _SFR_MEM8(0x158) ++#define FTN_START 7 ++ ++/* Reserved [0x159] */ ++ ++#define PLL_CF _SFR_MEM8(0x15A) ++#define PLL_CF_START 7 ++ ++#define PLL_DCU _SFR_MEM8(0x15B) ++#define PLL_DCU_START 7 ++ ++#define PART_NUM _SFR_MEM8(0x15C) ++#define PART_NUM0 0 ++#define PART_NUM1 1 ++#define PART_NUM2 2 ++#define PART_NUM3 3 ++#define PART_NUM4 4 ++#define PART_NUM5 5 ++#define PART_NUM6 6 ++#define PART_NUM7 7 ++ ++#define VERSION_NUM _SFR_MEM8(0x15D) ++#define VERSION_NUM0 0 ++#define VERSION_NUM1 1 ++#define VERSION_NUM2 2 ++#define VERSION_NUM3 3 ++#define VERSION_NUM4 4 ++#define VERSION_NUM5 5 ++#define VERSION_NUM6 6 ++#define VERSION_NUM7 7 ++ ++#define MAN_ID_0 _SFR_MEM8(0x15E) ++#define MAN_ID_00 0 ++#define MAN_ID_01 1 ++#define MAN_ID_02 2 ++#define MAN_ID_03 3 ++#define MAN_ID_04 4 ++#define MAN_ID_05 5 ++#define MAN_ID_06 6 ++#define MAN_ID_07 7 ++ ++#define MAN_ID_1 _SFR_MEM8(0x15F) ++#define MAN_ID_10 0 ++#define MAN_ID_11 1 ++#define MAN_ID_12 2 ++#define MAN_ID_13 3 ++#define MAN_ID_14 4 ++#define MAN_ID_15 5 ++#define MAN_ID_16 6 ++#define MAN_ID_17 7 ++ ++#define SHORT_ADDR_0 _SFR_MEM8(0x160) ++#define SHORT_ADDR_00 0 ++#define SHORT_ADDR_01 1 ++#define SHORT_ADDR_02 2 ++#define SHORT_ADDR_03 3 ++#define SHORT_ADDR_04 4 ++#define SHORT_ADDR_05 5 ++#define SHORT_ADDR_06 6 ++#define SHORT_ADDR_07 7 ++ ++#define SHORT_ADDR_1 _SFR_MEM8(0x161) ++#define SHORT_ADDR_10 0 ++#define SHORT_ADDR_11 1 ++#define SHORT_ADDR_12 2 ++#define SHORT_ADDR_13 3 ++#define SHORT_ADDR_14 4 ++#define SHORT_ADDR_15 5 ++#define SHORT_ADDR_16 6 ++#define SHORT_ADDR_17 7 ++ ++#define PAN_ID_0 _SFR_MEM8(0x162) ++#define PAN_ID_00 0 ++#define PAN_ID_01 1 ++#define PAN_ID_02 2 ++#define PAN_ID_03 3 ++#define PAN_ID_04 4 ++#define PAN_ID_05 5 ++#define PAN_ID_06 6 ++#define PAN_ID_07 7 ++ ++#define PAN_ID_1 _SFR_MEM8(0x163) ++#define PAN_ID_10 0 ++#define PAN_ID_11 1 ++#define PAN_ID_12 2 ++#define PAN_ID_13 3 ++#define PAN_ID_14 4 ++#define PAN_ID_15 5 ++#define PAN_ID_16 6 ++#define PAN_ID_17 7 ++ ++#define IEEE_ADDR_0 _SFR_MEM8(0x164) ++#define IEEE_ADDR_00 0 ++#define IEEE_ADDR_01 1 ++#define IEEE_ADDR_02 2 ++#define IEEE_ADDR_03 3 ++#define IEEE_ADDR_04 4 ++#define IEEE_ADDR_05 5 ++#define IEEE_ADDR_06 6 ++#define IEEE_ADDR_07 7 ++ ++#define IEEE_ADDR_1 _SFR_MEM8(0x165) ++#define IEEE_ADDR_10 0 ++#define IEEE_ADDR_11 1 ++#define IEEE_ADDR_12 2 ++#define IEEE_ADDR_13 3 ++#define IEEE_ADDR_14 4 ++#define IEEE_ADDR_15 5 ++#define IEEE_ADDR_16 6 ++#define IEEE_ADDR_17 7 ++ ++#define IEEE_ADDR_2 _SFR_MEM8(0x166) ++#define IEEE_ADDR_20 0 ++#define IEEE_ADDR_21 1 ++#define IEEE_ADDR_22 2 ++#define IEEE_ADDR_23 3 ++#define IEEE_ADDR_24 4 ++#define IEEE_ADDR_25 5 ++#define IEEE_ADDR_26 6 ++#define IEEE_ADDR_27 7 ++ ++#define IEEE_ADDR_3 _SFR_MEM8(0x167) ++#define IEEE_ADDR_30 0 ++#define IEEE_ADDR_31 1 ++#define IEEE_ADDR_32 2 ++#define IEEE_ADDR_33 3 ++#define IEEE_ADDR_34 4 ++#define IEEE_ADDR_35 5 ++#define IEEE_ADDR_36 6 ++#define IEEE_ADDR_37 7 ++ ++#define IEEE_ADDR_4 _SFR_MEM8(0x168) ++#define IEEE_ADDR_40 0 ++#define IEEE_ADDR_41 1 ++#define IEEE_ADDR_42 2 ++#define IEEE_ADDR_43 3 ++#define IEEE_ADDR_44 4 ++#define IEEE_ADDR_45 5 ++#define IEEE_ADDR_46 6 ++#define IEEE_ADDR_47 7 ++ ++#define IEEE_ADDR_5 _SFR_MEM8(0x169) ++#define IEEE_ADDR_50 0 ++#define IEEE_ADDR_51 1 ++#define IEEE_ADDR_52 2 ++#define IEEE_ADDR_53 3 ++#define IEEE_ADDR_54 4 ++#define IEEE_ADDR_55 5 ++#define IEEE_ADDR_56 6 ++#define IEEE_ADDR_57 7 ++ ++#define IEEE_ADDR_6 _SFR_MEM8(0x16A) ++#define IEEE_ADDR_60 0 ++#define IEEE_ADDR_61 1 ++#define IEEE_ADDR_62 2 ++#define IEEE_ADDR_63 3 ++#define IEEE_ADDR_64 4 ++#define IEEE_ADDR_65 5 ++#define IEEE_ADDR_66 6 ++#define IEEE_ADDR_67 7 ++ ++#define IEEE_ADDR_7 _SFR_MEM8(0x16B) ++#define IEEE_ADDR_70 0 ++#define IEEE_ADDR_71 1 ++#define IEEE_ADDR_72 2 ++#define IEEE_ADDR_73 3 ++#define IEEE_ADDR_74 4 ++#define IEEE_ADDR_75 5 ++#define IEEE_ADDR_76 6 ++#define IEEE_ADDR_77 7 ++ ++#define XAH_CTRL_0 _SFR_MEM8(0x16C) ++#define SLOTTED_OPERATION 0 ++#define MAX_CSMA_RETRIES0 1 ++#define MAX_CSMA_RETRIES1 2 ++#define MAX_CSMA_RETRIES2 3 ++#define MAX_FRAME_RETRIES0 4 ++#define MAX_FRAME_RETRIES1 5 ++#define MAX_FRAME_RETRIES2 6 ++#define MAX_FRAME_RETRIES3 7 ++ ++#define CSMA_SEED_0 _SFR_MEM8(0x16D) ++#define CSMA_SEED_00 0 ++#define CSMA_SEED_01 1 ++#define CSMA_SEED_02 2 ++#define CSMA_SEED_03 3 ++#define CSMA_SEED_04 4 ++#define CSMA_SEED_05 5 ++#define CSMA_SEED_06 6 ++#define CSMA_SEED_07 7 ++ ++#define CSMA_SEED_1 _SFR_MEM8(0x16E) ++#define CSMA_SEED_10 0 ++#define CSMA_SEED_11 1 ++#define CSMA_SEED_12 2 ++#define AACK_I_AM_COORD 3 ++#define AACK_DIS_ACK 4 ++#define AACK_SET_PD 5 ++#define AACK_FVN_MODE0 6 ++#define AACK_FVN_MODE1 7 ++ ++#define CSMA_BE _SFR_MEM8(0x16F) ++#define MIN_BE0 0 ++#define MIN_BE1 1 ++#define MIN_BE2 2 ++#define MIN_BE3 3 ++#define MAX_BE0 4 ++#define MAX_BE1 5 ++#define MAX_BE2 6 ++#define MAX_BE3 7 ++ ++/* Reserved [0x170..0x175] */ ++ ++#define TST_CTRL_DIGI _SFR_MEM8(0x176) ++#define TST_CTRL_DIG0 0 ++#define TST_CTRL_DIG1 1 ++#define TST_CTRL_DIG2 2 ++#define TST_CTRL_DIG3 3 ++ ++/* Reserved [0x177..0x17A] */ ++ ++#define TST_RX_LENGTH _SFR_MEM8(0x17B) ++#define RX_LENGTH0 0 ++#define RX_LENGTH1 1 ++#define RX_LENGTH2 2 ++#define RX_LENGTH3 3 ++#define RX_LENGTH4 4 ++#define RX_LENGTH5 5 ++#define RX_LENGTH6 6 ++#define RX_LENGTH7 7 ++ ++/* Reserved [0x17C..0x17F] */ ++ ++#define TRXFBST _SFR_MEM8(0x180) ++ ++/* Reserved [0x181..0x1FE] */ ++ ++#define TRXFBEND _SFR_MEM8(0x1FF) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect _VECTOR(3) ++#define INT2_vect_num 3 ++ ++/* External Interrupt Request 3 */ ++#define INT3_vect _VECTOR(4) ++#define INT3_vect_num 4 ++ ++/* External Interrupt Request 4 */ ++#define INT4_vect _VECTOR(5) ++#define INT4_vect_num 5 ++ ++/* External Interrupt Request 5 */ ++#define INT5_vect _VECTOR(6) ++#define INT5_vect_num 6 ++ ++/* External Interrupt Request 6 */ ++#define INT6_vect _VECTOR(7) ++#define INT6_vect_num 7 ++ ++/* External Interrupt Request 7 */ ++#define INT7_vect _VECTOR(8) ++#define INT7_vect_num 8 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(9) ++#define PCINT0_vect_num 9 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(10) ++#define PCINT1_vect_num 10 ++ ++/* Pin Change Interrupt Request 2 */ ++#define PCINT2_vect _VECTOR(11) ++#define PCINT2_vect_num 11 ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect _VECTOR(12) ++#define WDT_vect_num 12 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPA_vect _VECTOR(13) ++#define TIMER2_COMPA_vect_num 13 ++ ++/* Timer/Counter2 Compare Match B */ ++#define TIMER2_COMPB_vect _VECTOR(14) ++#define TIMER2_COMPB_vect_num 14 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(15) ++#define TIMER2_OVF_vect_num 15 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(16) ++#define TIMER1_CAPT_vect_num 16 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(17) ++#define TIMER1_COMPA_vect_num 17 ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(18) ++#define TIMER1_COMPB_vect_num 18 ++ ++/* Timer/Counter1 Compare Match C */ ++#define TIMER1_COMPC_vect _VECTOR(19) ++#define TIMER1_COMPC_vect_num 19 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(20) ++#define TIMER1_OVF_vect_num 20 ++ ++/* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPA_vect _VECTOR(21) ++#define TIMER0_COMPA_vect_num 21 ++ ++/* Timer/Counter0 Compare Match B */ ++#define TIMER0_COMPB_vect _VECTOR(22) ++#define TIMER0_COMPB_vect_num 22 ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(23) ++#define TIMER0_OVF_vect_num 23 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(24) ++#define SPI_STC_vect_num 24 ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect _VECTOR(25) ++#define USART0_RX_vect_num 25 ++ ++/* USART0 Data register Empty */ ++#define USART0_UDRE_vect _VECTOR(26) ++#define USART0_UDRE_vect_num 26 ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect _VECTOR(27) ++#define USART0_TX_vect_num 27 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(28) ++#define ANALOG_COMP_vect_num 28 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(29) ++#define ADC_vect_num 29 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(30) ++#define EE_READY_vect_num 30 ++ ++/* Timer/Counter3 Capture Event */ ++#define TIMER3_CAPT_vect _VECTOR(31) ++#define TIMER3_CAPT_vect_num 31 ++ ++/* Timer/Counter3 Compare Match A */ ++#define TIMER3_COMPA_vect _VECTOR(32) ++#define TIMER3_COMPA_vect_num 32 ++ ++/* Timer/Counter3 Compare Match B */ ++#define TIMER3_COMPB_vect _VECTOR(33) ++#define TIMER3_COMPB_vect_num 33 ++ ++/* Timer/Counter3 Compare Match C */ ++#define TIMER3_COMPC_vect _VECTOR(34) ++#define TIMER3_COMPC_vect_num 34 ++ ++/* Timer/Counter3 Overflow */ ++#define TIMER3_OVF_vect _VECTOR(35) ++#define TIMER3_OVF_vect_num 35 ++ ++/* USART1, Rx Complete */ ++#define USART1_RX_vect _VECTOR(36) ++#define USART1_RX_vect_num 36 ++ ++/* USART1 Data register Empty */ ++#define USART1_UDRE_vect _VECTOR(37) ++#define USART1_UDRE_vect_num 37 ++ ++/* USART1, Tx Complete */ ++#define USART1_TX_vect _VECTOR(38) ++#define USART1_TX_vect_num 38 ++ ++/* 2-wire Serial Interface */ ++#define TWI_vect _VECTOR(39) ++#define TWI_vect_num 39 ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect _VECTOR(40) ++#define SPM_READY_vect_num 40 ++ ++/* Timer/Counter4 Capture Event */ ++#define TIMER4_CAPT_vect _VECTOR(41) ++#define TIMER4_CAPT_vect_num 41 ++ ++/* Timer/Counter4 Compare Match A */ ++#define TIMER4_COMPA_vect _VECTOR(42) ++#define TIMER4_COMPA_vect_num 42 ++ ++/* Timer/Counter4 Compare Match B */ ++#define TIMER4_COMPB_vect _VECTOR(43) ++#define TIMER4_COMPB_vect_num 43 ++ ++/* Timer/Counter4 Compare Match C */ ++#define TIMER4_COMPC_vect _VECTOR(44) ++#define TIMER4_COMPC_vect_num 44 ++ ++/* Timer/Counter4 Overflow */ ++#define TIMER4_OVF_vect _VECTOR(45) ++#define TIMER4_OVF_vect_num 45 ++ ++/* Timer/Counter5 Capture Event */ ++#define TIMER5_CAPT_vect _VECTOR(46) ++#define TIMER5_CAPT_vect_num 46 ++ ++/* Timer/Counter5 Compare Match A */ ++#define TIMER5_COMPA_vect _VECTOR(47) ++#define TIMER5_COMPA_vect_num 47 ++ ++/* Timer/Counter5 Compare Match B */ ++#define TIMER5_COMPB_vect _VECTOR(48) ++#define TIMER5_COMPB_vect_num 48 ++ ++/* Timer/Counter5 Compare Match C */ ++#define TIMER5_COMPC_vect _VECTOR(49) ++#define TIMER5_COMPC_vect_num 49 ++ ++/* Timer/Counter5 Overflow */ ++#define TIMER5_OVF_vect _VECTOR(50) ++#define TIMER5_OVF_vect_num 50 ++ ++/* TRX24 - PLL lock interrupt */ ++#define TRX24_PLL_LOCK_vect _VECTOR(57) ++#define TRX24_PLL_LOCK_vect_num 57 ++ ++/* TRX24 - PLL unlock interrupt */ ++#define TRX24_PLL_UNLOCK_vect _VECTOR(58) ++#define TRX24_PLL_UNLOCK_vect_num 58 ++ ++/* TRX24 - Receive start interrupt */ ++#define TRX24_RX_START_vect _VECTOR(59) ++#define TRX24_RX_START_vect_num 59 ++ ++/* TRX24 - RX_END interrupt */ ++#define TRX24_RX_END_vect _VECTOR(60) ++#define TRX24_RX_END_vect_num 60 ++ ++/* TRX24 - CCA/ED done interrupt */ ++#define TRX24_CCA_ED_DONE_vect _VECTOR(61) ++#define TRX24_CCA_ED_DONE_vect_num 61 ++ ++/* TRX24 - XAH - AMI */ ++#define TRX24_XAH_AMI_vect _VECTOR(62) ++#define TRX24_XAH_AMI_vect_num 62 ++ ++/* TRX24 - TX_END interrupt */ ++#define TRX24_TX_END_vect _VECTOR(63) ++#define TRX24_TX_END_vect_num 63 ++ ++/* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */ ++#define TRX24_AWAKE_vect _VECTOR(64) ++#define TRX24_AWAKE_vect_num 64 ++ ++/* Symbol counter - compare match 1 interrupt */ ++#define SCNT_CMP1_vect _VECTOR(65) ++#define SCNT_CMP1_vect_num 65 ++ ++/* Symbol counter - compare match 2 interrupt */ ++#define SCNT_CMP2_vect _VECTOR(66) ++#define SCNT_CMP2_vect_num 66 ++ ++/* Symbol counter - compare match 3 interrupt */ ++#define SCNT_CMP3_vect _VECTOR(67) ++#define SCNT_CMP3_vect_num 67 ++ ++/* Symbol counter - overflow interrupt */ ++#define SCNT_OVFL_vect _VECTOR(68) ++#define SCNT_OVFL_vect_num 68 ++ ++/* Symbol counter - backoff interrupt */ ++#define SCNT_BACKOFF_vect _VECTOR(69) ++#define SCNT_BACKOFF_vect_num 69 ++ ++/* AES engine ready interrupt */ ++#define AES_READY_vect _VECTOR(70) ++#define AES_READY_vect_num 70 ++ ++/* Battery monitor indicates supply voltage below threshold */ ++#define BAT_LOW_vect _VECTOR(71) ++#define BAT_LOW_vect_num 71 ++ ++/* TRX24 TX start interrupt */ ++#define TRX24_TX_START_vect _VECTOR(72) ++#define TRX24_TX_START_vect_num 72 ++ ++/* Address match interrupt of address filter 0 */ ++#define TRX24_AMI0_vect _VECTOR(73) ++#define TRX24_AMI0_vect_num 73 ++ ++/* Address match interrupt of address filter 1 */ ++#define TRX24_AMI1_vect _VECTOR(74) ++#define TRX24_AMI1_vect_num 74 ++ ++/* Address match interrupt of address filter 2 */ ++#define TRX24_AMI2_vect _VECTOR(75) ++#define TRX24_AMI2_vect_num 75 ++ ++/* Address match interrupt of address filter 3 */ ++#define TRX24_AMI3_vect _VECTOR(76) ++#define TRX24_AMI3_vect_num 76 ++ ++#define _VECTORS_SIZE 308 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 256 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x1FFFF ++#define RAMSTART 0x0200 ++#define RAMSIZE 16384 ++#define RAMEND 0x41FF ++#define E2START 0 ++#define E2SIZE 4096 ++#define E2PAGESIZE 8 ++#define E2END 0x0FFF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL_SUT0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL_SUT1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL_SUT2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL_SUT3 (unsigned char)~_BV(3) ++#define FUSE_CKSEL_SUT4 (unsigned char)~_BV(4) ++#define FUSE_CKSEL_SUT5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0xA7 ++#define SIGNATURE_2 0x03 ++ ++ ++#endif /* #ifdef _AVR_ATMEGA1284RFR2_H_INCLUDED */ ++ +diff --git a/include/avr/iom128a.h b/include/avr/iom128a.h +new file mode 100644 +index 0000000..4586f1f +--- /dev/null ++++ b/include/avr/iom128a.h +@@ -0,0 +1,948 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATMEGA128A_H_INCLUDED ++#define _AVR_ATMEGA128A_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom128a.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINF _SFR_IO8(0x00) ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++#define PINE _SFR_IO8(0x01) ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x02) ++#define DDRE7 7 ++#define DDRE6 6 ++#define DDRE5 5 ++#define DDRE4 4 ++#define DDRE3 3 ++#define DDRE2 2 ++#define DDRE1 1 ++#define DDRE0 0 ++ ++#define PORTE _SFR_IO8(0x03) ++#define PORTE7 7 ++#define PORTE6 6 ++#define PORTE5 5 ++#define PORTE4 4 ++#define PORTE3 3 ++#define PORTE2 2 ++#define PORTE1 1 ++#define PORTE0 0 ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCW _SFR_IO16(0x04) ++ ++#define ADCL _SFR_IO8(0x04) ++#define ADCH _SFR_IO8(0x05) ++ ++#define ADCSRA _SFR_IO8(0x06) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADFR 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADMUX _SFR_IO8(0x07) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define ACSR _SFR_IO8(0x08) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define UBRR0L _SFR_IO8(0x09) ++ ++#define UCSR0B _SFR_IO8(0x0A) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0A _SFR_IO8(0x0B) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UDR0 _SFR_IO8(0x0C) ++ ++#define SPCR _SFR_IO8(0x0D) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x0E) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x0F) ++ ++#define PIND _SFR_IO8(0x10) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x11) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x12) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++#define PINC _SFR_IO8(0x13) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x14) ++#define DDRC7 7 ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x15) ++#define PORTC7 7 ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PINB _SFR_IO8(0x16) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x17) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x18) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINA _SFR_IO8(0x19) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x1A) ++#define DDRA7 7 ++#define DDRA6 6 ++#define DDRA5 5 ++#define DDRA4 4 ++#define DDRA3 3 ++#define DDRA2 2 ++#define DDRA1 1 ++#define DDRA0 0 ++ ++#define PORTA _SFR_IO8(0x1B) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define EECR _SFR_IO8(0x1C) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x1E) ++ ++#define EEARL _SFR_IO8(0x1E) ++#define EEARH _SFR_IO8(0x1F) ++ ++#define SFIOR _SFR_IO8(0x20) ++#define ACME 3 ++#define PSR321 0 ++#define PSR0 1 ++#define PUD 2 ++#define TSM 7 ++ ++#define WDTCR _SFR_IO8(0x21) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define OCDR _SFR_IO8(0x22) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCDR7 7 ++ ++#define OCR2 _SFR_IO8(0x23) ++ ++#define TCNT2 _SFR_IO8(0x24) ++ ++#define TCCR2 _SFR_IO8(0x25) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM21 3 ++#define COM20 4 ++#define COM21 5 ++#define WGM20 6 ++#define FOC2 7 ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_IO16(0x26) ++ ++#define ICR1L _SFR_IO8(0x26) ++#define ICR1H _SFR_IO8(0x27) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_IO16(0x28) ++ ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BH _SFR_IO8(0x29) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_IO16(0x2A) ++ ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_IO16(0x2C) ++ ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++ ++#define TCCR1B _SFR_IO8(0x2E) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1A _SFR_IO8(0x2F) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1C0 2 ++#define COM1C1 3 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define ASSR _SFR_IO8(0x30) ++#define TCR0UB 0 ++#define OCR0UB 1 ++#define TCN0UB 2 ++#define AS0 3 ++ ++#define OCR0 _SFR_IO8(0x31) ++ ++#define TCNT0 _SFR_IO8(0x32) ++ ++#define TCCR0 _SFR_IO8(0x33) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM01 3 ++#define COM00 4 ++#define COM01 5 ++#define WGM00 6 ++#define FOC0 7 ++ ++#define MCUCSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define JTRF 4 ++#define JTD 7 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define SM2 2 ++#define SM0 3 ++#define SM1 4 ++#define SE 5 ++#define SRW10 6 ++#define SRE 7 ++ ++#define TIFR _SFR_IO8(0x36) ++#define TOV0 0 ++#define OCF0 1 ++#define TOV1 2 ++#define OCF1B 3 ++#define OCF1A 4 ++#define ICF1 5 ++#define TOV2 6 ++#define OCF2 7 ++ ++#define TIMSK _SFR_IO8(0x37) ++#define TOIE0 0 ++#define OCIE0 1 ++#define TOIE1 2 ++#define OCIE1B 3 ++#define OCIE1A 4 ++#define TICIE1 5 ++#define TOIE2 6 ++#define OCIE2 7 ++ ++#define EIFR _SFR_IO8(0x38) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++#define INTF4 4 ++#define INTF5 5 ++#define INTF6 6 ++#define INTF7 7 ++ ++#define EIMSK _SFR_IO8(0x39) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++#define INT3 3 ++#define INT4 4 ++#define INT5 5 ++#define INT6 6 ++#define INT7 7 ++ ++#define EICRB _SFR_IO8(0x3A) ++#define ISC40 0 ++#define ISC41 1 ++#define ISC50 2 ++#define ISC51 3 ++#define ISC60 4 ++#define ISC61 5 ++#define ISC70 6 ++#define ISC71 7 ++ ++#define RAMPZ _SFR_IO8(0x3B) ++#define RAMPZ0 0 ++ ++#define XDIV _SFR_IO8(0x3C) ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++/* Reserved [0x40..0x60] */ ++ ++#define DDRF _SFR_MEM8(0x61) ++#define DDRF7 7 ++#define DDRF6 6 ++#define DDRF5 5 ++#define DDRF4 4 ++#define DDRF3 3 ++#define DDRF2 2 ++#define DDRF1 1 ++#define DDRF0 0 ++ ++#define PORTF _SFR_MEM8(0x62) ++#define PORTF7 7 ++#define PORTF6 6 ++#define PORTF5 5 ++#define PORTF4 4 ++#define PORTF3 3 ++#define PORTF2 2 ++#define PORTF1 1 ++#define PORTF0 0 ++ ++#define PING _SFR_MEM8(0x63) ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++#define DDRG _SFR_MEM8(0x64) ++#define DDRG4 4 ++#define DDRG3 3 ++#define DDRG2 2 ++#define DDRG1 1 ++#define DDRG0 0 ++ ++#define PORTG _SFR_MEM8(0x65) ++#define PORTG4 4 ++#define PORTG3 3 ++#define PORTG2 2 ++#define PORTG1 1 ++#define PORTG0 0 ++ ++/* Reserved [0x66..0x67] */ ++ ++#define SPMCSR _SFR_MEM8(0x68) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x69] */ ++ ++#define EICRA _SFR_MEM8(0x6A) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++/* Reserved [0x6B] */ ++ ++#define XMCRB _SFR_MEM8(0x6C) ++#define XMM0 0 ++#define XMM1 1 ++#define XMM2 2 ++#define XMBK 7 ++ ++#define XMCRA _SFR_MEM8(0x6D) ++#define SRW11 1 ++#define SRW00 2 ++#define SRW01 3 ++#define SRL0 4 ++#define SRL1 5 ++#define SRL2 6 ++ ++/* Reserved [0x6E] */ ++ ++#define OSCCAL _SFR_MEM8(0x6F) ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++#define TWBR _SFR_MEM8(0x70) ++ ++#define TWSR _SFR_MEM8(0x71) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0x72) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0x73) ++ ++#define TWCR _SFR_MEM8(0x74) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++/* Reserved [0x75..0x77] */ ++ ++/* Combine OCR1CL and OCR1CH */ ++#define OCR1C _SFR_MEM16(0x78) ++ ++#define OCR1CL _SFR_MEM8(0x78) ++#define OCR1CH _SFR_MEM8(0x79) ++ ++#define TCCR1C _SFR_MEM8(0x7A) ++#define FOC1C 5 ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x7B] */ ++ ++#define ETIFR _SFR_MEM8(0x7C) ++#define OCF1C 0 ++#define OCF3C 1 ++#define TOV3 2 ++#define OCF3B 3 ++#define OCF3A 4 ++#define ICF3 5 ++ ++#define ETIMSK _SFR_MEM8(0x7D) ++#define OCIE1C 0 ++#define OCIE3C 1 ++#define TOIE3 2 ++#define OCIE3B 3 ++#define OCIE3A 4 ++#define TICIE3 5 ++ ++/* Reserved [0x7E..0x7F] */ ++ ++/* Combine ICR3L and ICR3H */ ++#define ICR3 _SFR_MEM16(0x80) ++ ++#define ICR3L _SFR_MEM8(0x80) ++#define ICR3H _SFR_MEM8(0x81) ++ ++/* Combine OCR3CL and OCR3CH */ ++#define OCR3C _SFR_MEM16(0x82) ++ ++#define OCR3CL _SFR_MEM8(0x82) ++#define OCR3CH _SFR_MEM8(0x83) ++ ++/* Combine OCR3BL and OCR3BH */ ++#define OCR3B _SFR_MEM16(0x84) ++ ++#define OCR3BL _SFR_MEM8(0x84) ++#define OCR3BH _SFR_MEM8(0x85) ++ ++/* Combine OCR3AL and OCR3AH */ ++#define OCR3A _SFR_MEM16(0x86) ++ ++#define OCR3AL _SFR_MEM8(0x86) ++#define OCR3AH _SFR_MEM8(0x87) ++ ++/* Combine TCNT3L and TCNT3H */ ++#define TCNT3 _SFR_MEM16(0x88) ++ ++#define TCNT3L _SFR_MEM8(0x88) ++#define TCNT3H _SFR_MEM8(0x89) ++ ++#define TCCR3B _SFR_MEM8(0x8A) ++#define CS30 0 ++#define CS31 1 ++#define CS32 2 ++#define WGM32 3 ++#define WGM33 4 ++#define ICES3 6 ++#define ICNC3 7 ++ ++#define TCCR3A _SFR_MEM8(0x8B) ++#define WGM30 0 ++#define WGM31 1 ++#define COM3C0 2 ++#define COM3C1 3 ++#define COM3B0 4 ++#define COM3B1 5 ++#define COM3A0 6 ++#define COM3A1 7 ++ ++#define TCCR3C _SFR_MEM8(0x8C) ++#define FOC3C 5 ++#define FOC3B 6 ++#define FOC3A 7 ++ ++/* Reserved [0x8D..0x8F] */ ++ ++#define UBRR0H _SFR_MEM8(0x90) ++ ++/* Reserved [0x91..0x94] */ ++ ++#define UCSR0C _SFR_MEM8(0x95) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL0 6 ++ ++/* Reserved [0x96..0x97] */ ++ ++#define UBRR1H _SFR_MEM8(0x98) ++ ++#define UBRR1L _SFR_MEM8(0x99) ++ ++#define UCSR1B _SFR_MEM8(0x9A) ++#define TXB81 0 ++#define RXB81 1 ++#define UCSZ12 2 ++#define TXEN1 3 ++#define RXEN1 4 ++#define UDRIE1 5 ++#define TXCIE1 6 ++#define RXCIE1 7 ++ ++#define UCSR1A _SFR_MEM8(0x9B) ++#define MPCM1 0 ++#define U2X1 1 ++#define UPE1 2 ++#define DOR1 3 ++#define FE1 4 ++#define UDRE1 5 ++#define TXC1 6 ++#define RXC1 7 ++ ++#define UDR1 _SFR_MEM8(0x9C) ++ ++#define UCSR1C _SFR_MEM8(0x9D) ++#define UCPOL1 0 ++#define UCSZ10 1 ++#define UCSZ11 2 ++#define USBS1 3 ++#define UPM10 4 ++#define UPM11 5 ++#define UMSEL1 6 ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect _VECTOR(3) ++#define INT2_vect_num 3 ++ ++/* External Interrupt Request 3 */ ++#define INT3_vect _VECTOR(4) ++#define INT3_vect_num 4 ++ ++/* External Interrupt Request 4 */ ++#define INT4_vect _VECTOR(5) ++#define INT4_vect_num 5 ++ ++/* External Interrupt Request 5 */ ++#define INT5_vect _VECTOR(6) ++#define INT5_vect_num 6 ++ ++/* External Interrupt Request 6 */ ++#define INT6_vect _VECTOR(7) ++#define INT6_vect_num 7 ++ ++/* External Interrupt Request 7 */ ++#define INT7_vect _VECTOR(8) ++#define INT7_vect_num 8 ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect _VECTOR(9) ++#define TIMER2_COMP_vect_num 9 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(10) ++#define TIMER2_OVF_vect_num 10 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(11) ++#define TIMER1_CAPT_vect_num 11 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(12) ++#define TIMER1_COMPA_vect_num 12 ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(13) ++#define TIMER1_COMPB_vect_num 13 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(14) ++#define TIMER1_OVF_vect_num 14 ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect _VECTOR(15) ++#define TIMER0_COMP_vect_num 15 ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(16) ++#define TIMER0_OVF_vect_num 16 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(17) ++#define SPI_STC_vect_num 17 ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect _VECTOR(18) ++#define USART0_RX_vect_num 18 ++ ++/* USART0 Data Register Empty */ ++#define USART0_UDRE_vect _VECTOR(19) ++#define USART0_UDRE_vect_num 19 ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect _VECTOR(20) ++#define USART0_TX_vect_num 20 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(21) ++#define ADC_vect_num 21 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(22) ++#define EE_READY_vect_num 22 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(23) ++#define ANALOG_COMP_vect_num 23 ++ ++/* Timer/Counter1 Compare Match C */ ++#define TIMER1_COMPC_vect _VECTOR(24) ++#define TIMER1_COMPC_vect_num 24 ++ ++/* Timer/Counter3 Capture Event */ ++#define TIMER3_CAPT_vect _VECTOR(25) ++#define TIMER3_CAPT_vect_num 25 ++ ++/* Timer/Counter3 Compare Match A */ ++#define TIMER3_COMPA_vect _VECTOR(26) ++#define TIMER3_COMPA_vect_num 26 ++ ++/* Timer/Counter3 Compare Match B */ ++#define TIMER3_COMPB_vect _VECTOR(27) ++#define TIMER3_COMPB_vect_num 27 ++ ++/* Timer/Counter3 Compare Match C */ ++#define TIMER3_COMPC_vect _VECTOR(28) ++#define TIMER3_COMPC_vect_num 28 ++ ++/* Timer/Counter3 Overflow */ ++#define TIMER3_OVF_vect _VECTOR(29) ++#define TIMER3_OVF_vect_num 29 ++ ++/* USART1, Rx Complete */ ++#define USART1_RX_vect _VECTOR(30) ++#define USART1_RX_vect_num 30 ++ ++/* USART1, Data Register Empty */ ++#define USART1_UDRE_vect _VECTOR(31) ++#define USART1_UDRE_vect_num 31 ++ ++/* USART1, Tx Complete */ ++#define USART1_TX_vect _VECTOR(32) ++#define USART1_TX_vect_num 32 ++ ++/* 2-wire Serial Interface */ ++#define TWI_vect _VECTOR(33) ++#define TWI_vect_num 33 ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect _VECTOR(34) ++#define SPM_READY_vect_num 34 ++ ++#define _VECTORS_SIZE 140 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 256 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x1FFFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 4096 ++#define RAMEND 0x10FF ++#define E2START 0 ++#define E2SIZE 4096 ++#define E2PAGESIZE 8 ++#define E2END 0x0FFF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_BODEN (unsigned char)~_BV(6) ++#define FUSE_BODLEVEL (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_CKOPT (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_WDTON (unsigned char)~_BV(0) ++#define FUSE_M103C (unsigned char)~_BV(1) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x97 ++#define SIGNATURE_2 0x02 ++ ++ ++#endif /* #ifdef _AVR_ATMEGA128A_H_INCLUDED */ ++ +diff --git a/include/avr/iom128rfa1.h b/include/avr/iom128rfa1.h +index 1630807..de1b5ae 100644 +--- a/include/avr/iom128rfa1.h ++++ b/include/avr/iom128rfa1.h +@@ -1,5373 +1,5373 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom128rfa1.h 2009 2009-07-01 14:57:41Z joerg_wunsch $ */ +- +-/* avr/iom128rfa1.h - definitions for ATmega128RFA1 */ +- +-#ifndef _AVR_IOM128RFA1_H_ +-#define _AVR_IOM128RFA1_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom128rfa1.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-#include +- +-#ifndef __ASSEMBLER__ +-# define _MMIO_BYTE_STRUCT(mem_addr,type) (*(volatile type *)(mem_addr)) +-# define _SFR_IO8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr) + 0x20, type) +-# define _SFR_MEM8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr), type) +-#endif /* __ASSEMBLER__ */ +- +-/* +- * USAGE: +- * +- * simple register assignment: +- * TIFR1 = 0x17 +- * subregister assignment: +- * TIFR1_struct.ocf1a = 1 +- * (subregister names are converted to small letters) +- */ +- +- +-/* Port A Input Pins Address */ +-#define PINA _SFR_IO8(0x00) +- +- /* PINA */ +- +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +-#define PINA4 4 +-#define PINA5 5 +-#define PINA6 6 +-#define PINA7 7 +- +-/* Port A Data Direction Register */ +-#define DDRA _SFR_IO8(0x01) +- +- /* DDRA */ +- +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +-#define DDA4 4 +-#define DDA5 5 +-#define DDA6 6 +-#define DDA7 7 +- +-/* Port A Data Register */ +-#define PORTA _SFR_IO8(0x02) +- +- /* PORTA */ +- +-#define PORTA0 0 +-#define PA0 0 +-#define PORTA1 1 +-#define PA1 1 +-#define PORTA2 2 +-#define PA2 2 +-#define PORTA3 3 +-#define PA3 3 +-#define PORTA4 4 +-#define PA4 4 +-#define PORTA5 5 +-#define PA5 5 +-#define PORTA6 6 +-#define PA6 6 +-#define PORTA7 7 +-#define PA7 7 +- +-/* Port B Input Pins Address */ +-#define PINB _SFR_IO8(0x03) +- +- /* PINB */ +- +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-/* Port B Data Direction Register */ +-#define DDRB _SFR_IO8(0x04) +- +- /* DDRB */ +- +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-/* Port B Data Register */ +-#define PORTB _SFR_IO8(0x05) +- +- /* PORTB */ +- +-#define PORTB0 0 +-#define PB0 0 +-#define PORTB1 1 +-#define PB1 1 +-#define PORTB2 2 +-#define PB2 2 +-#define PORTB3 3 +-#define PB3 3 +-#define PORTB4 4 +-#define PB4 4 +-#define PORTB5 5 +-#define PB5 5 +-#define PORTB6 6 +-#define PB6 6 +-#define PORTB7 7 +-#define PB7 7 +- +-/* Port C Input Pins Address */ +-#define PINC _SFR_IO8(0x06) +- +- /* PINC */ +- +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +-#define PINC7 7 +- +-/* Port C Data Direction Register */ +-#define DDRC _SFR_IO8(0x07) +- +- /* DDRC */ +- +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC3 3 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +-#define DDC7 7 +- +-/* Port C Data Register */ +-#define PORTC _SFR_IO8(0x08) +- +- /* PORTC */ +- +-#define PORTC0 0 +-#define PC0 0 +-#define PORTC1 1 +-#define PC1 1 +-#define PORTC2 2 +-#define PC2 2 +-#define PORTC3 3 +-#define PC3 3 +-#define PORTC4 4 +-#define PC4 4 +-#define PORTC5 5 +-#define PC5 5 +-#define PORTC6 6 +-#define PC6 6 +-#define PORTC7 7 +-#define PC7 7 +- +-/* Port D Input Pins Address */ +-#define PIND _SFR_IO8(0x09) +- +- /* PIND */ +- +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-/* Port D Data Direction Register */ +-#define DDRD _SFR_IO8(0x0A) +- +- /* DDRD */ +- +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-/* Port D Data Register */ +-#define PORTD _SFR_IO8(0x0B) +- +- /* PORTD */ +- +-#define PORTD0 0 +-#define PD0 0 +-#define PORTD1 1 +-#define PD1 1 +-#define PORTD2 2 +-#define PD2 2 +-#define PORTD3 3 +-#define PD3 3 +-#define PORTD4 4 +-#define PD4 4 +-#define PORTD5 5 +-#define PD5 5 +-#define PORTD6 6 +-#define PD6 6 +-#define PORTD7 7 +-#define PD7 7 +- +-/* Port E Input Pins Address */ +-#define PINE _SFR_IO8(0x0C) +- +- /* PINE */ +- +-#define PINE0 0 +-#define PINE1 1 +-#define PINE2 2 +-#define PINE3 3 +-#define PINE4 4 +-#define PINE5 5 +-#define PINE6 6 +-#define PINE7 7 +- +-/* Port E Data Direction Register */ +-#define DDRE _SFR_IO8(0x0D) +- +- /* DDRE */ +- +-#define DDE0 0 +-#define DDE1 1 +-#define DDE2 2 +-#define DDE3 3 +-#define DDE4 4 +-#define DDE5 5 +-#define DDE6 6 +-#define DDE7 7 +- +-/* Port E Data Register */ +-#define PORTE _SFR_IO8(0x0E) +- +- /* PORTE */ +- +-#define PORTE0 0 +-#define PE0 0 +-#define PORTE1 1 +-#define PE1 1 +-#define PORTE2 2 +-#define PE2 2 +-#define PORTE3 3 +-#define PE3 3 +-#define PORTE4 4 +-#define PE4 4 +-#define PORTE5 5 +-#define PE5 5 +-#define PORTE6 6 +-#define PE6 6 +-#define PORTE7 7 +-#define PE7 7 +- +-/* Port F Input Pins Address */ +-#define PINF _SFR_IO8(0x0F) +- +- /* PINF */ +- +-#define PINF0 0 +-#define PINF1 1 +-#define PINF2 2 +-#define PINF3 3 +-#define PINF4 4 +-#define PINF5 5 +-#define PINF6 6 +-#define PINF7 7 +- +-/* Port F Data Direction Register */ +-#define DDRF _SFR_IO8(0x10) +- +- /* DDRF */ +- +-#define DDF0 0 +-#define DDF1 1 +-#define DDF2 2 +-#define DDF3 3 +-#define DDF4 4 +-#define DDF5 5 +-#define DDF6 6 +-#define DDF7 7 +- +-/* Port F Data Register */ +-#define PORTF _SFR_IO8(0x11) +- +- /* PORTF */ +- +-#define PORTF0 0 +-#define PF0 0 +-#define PORTF1 1 +-#define PF1 1 +-#define PORTF2 2 +-#define PF2 2 +-#define PORTF3 3 +-#define PF3 3 +-#define PORTF4 4 +-#define PF4 4 +-#define PORTF5 5 +-#define PF5 5 +-#define PORTF6 6 +-#define PF6 6 +-#define PORTF7 7 +-#define PF7 7 +- +-/* Port G Input Pins Address */ +-#define PING _SFR_IO8(0x12) +- +- /* PING */ +- +-#define PING0 0 +-#define PING1 1 +-#define PING2 2 +-#define PING3 3 +-#define PING4 4 +-#define PING5 5 +- +-/* Port G Data Direction Register */ +-#define DDRG _SFR_IO8(0x13) +- +- /* DDRG */ +- +-#define DDG0 0 +-#define DDG1 1 +-#define DDG2 2 +-#define DDG3 3 +-#define DDG4 4 +-#define DDG5 5 +- +-/* Port G Data Register */ +-#define PORTG _SFR_IO8(0x14) +- +- /* PORTG */ +- +-#define PORTG0 0 +-#define PG0 0 +-#define PORTG1 1 +-#define PG1 1 +-#define PORTG2 2 +-#define PG2 2 +-#define PORTG3 3 +-#define PG3 3 +-#define PORTG4 4 +-#define PG4 4 +-#define PORTG5 5 +-#define PG5 5 +- +-/* Timer/Counter0 Interrupt Flag Register */ +-#define TIFR0 _SFR_IO8(0x15) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TIFR0 { +- unsigned int tov0 : 1; /* Timer/Counter0 Overflow Flag */ +- unsigned int ocf0a : 1; /* Timer/Counter0 Output Compare A Match Flag */ +- unsigned int ocf0b : 1; /* Timer/Counter0 Output Compare B Match Flag */ +- unsigned int : 5; +-}; +- +-#define TIFR0_struct _SFR_IO8_STRUCT(0x15, struct __reg_TIFR0) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TIFR0 */ +- +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-/* Timer/Counter1 Interrupt Flag Register */ +-#define TIFR1 _SFR_IO8(0x16) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TIFR1 { +- unsigned int tov1 : 1; /* Timer/Counter1 Overflow Flag */ +- unsigned int ocf1a : 1; /* Timer/Counter1 Output Compare A Match Flag */ +- unsigned int ocf1b : 1; /* Timer/Counter1 Output Compare B Match Flag */ +- unsigned int ocf1c : 1; /* Timer/Counter1 Output Compare C Match Flag */ +- unsigned int : 1; +- unsigned int icf1 : 1; /* Timer/Counter1 Input Capture Flag */ +- unsigned int : 2; +-}; +- +-#define TIFR1_struct _SFR_IO8_STRUCT(0x16, struct __reg_TIFR1) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TIFR1 */ +- +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define OCF1C 3 +-#define ICF1 5 +- +-/* Timer/Counter Interrupt Flag Register */ +-#define TIFR2 _SFR_IO8(0x17) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TIFR2 { +- unsigned int tov2 : 1; /* Timer/Counter2 Overflow Flag */ +- unsigned int ocf2a : 1; /* Output Compare Flag 2 A */ +- unsigned int ocf2b : 1; /* Output Compare Flag 2 B */ +- unsigned int : 5; +-}; +- +-#define TIFR2_struct _SFR_IO8_STRUCT(0x17, struct __reg_TIFR2) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TIFR2 */ +- +-#define TOV2 0 +-#define OCF2A 1 +-#define OCF2B 2 +- +-/* Timer/Counter3 Interrupt Flag Register */ +-#define TIFR3 _SFR_IO8(0x18) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TIFR3 { +- unsigned int tov3 : 1; /* Timer/Counter3 Overflow Flag */ +- unsigned int ocf3a : 1; /* Timer/Counter3 Output Compare A Match Flag */ +- unsigned int ocf3b : 1; /* Timer/Counter3 Output Compare B Match Flag */ +- unsigned int ocf3c : 1; /* Timer/Counter3 Output Compare C Match Flag */ +- unsigned int : 1; +- unsigned int icf3 : 1; /* Timer/Counter3 Input Capture Flag */ +- unsigned int : 2; +-}; +- +-#define TIFR3_struct _SFR_IO8_STRUCT(0x18, struct __reg_TIFR3) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TIFR3 */ +- +-#define TOV3 0 +-#define OCF3A 1 +-#define OCF3B 2 +-#define OCF3C 3 +-#define ICF3 5 +- +-/* Timer/Counter4 Interrupt Flag Register */ +-#define TIFR4 _SFR_IO8(0x19) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TIFR4 { +- unsigned int tov4 : 1; /* Timer/Counter4 Overflow Flag */ +- unsigned int ocf4a : 1; /* Timer/Counter4 Output Compare A Match Flag */ +- unsigned int ocf4b : 1; /* Timer/Counter4 Output Compare B Match Flag */ +- unsigned int ocf4c : 1; /* Timer/Counter4 Output Compare C Match Flag */ +- unsigned int : 1; +- unsigned int icf4 : 1; /* Timer/Counter4 Input Capture Flag */ +- unsigned int : 2; +-}; +- +-#define TIFR4_struct _SFR_IO8_STRUCT(0x19, struct __reg_TIFR4) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TIFR4 */ +- +-#define TOV4 0 +-#define OCF4A 1 +-#define OCF4B 2 +-#define OCF4C 3 +-#define ICF4 5 +- +-/* Timer/Counter5 Interrupt Flag Register */ +-#define TIFR5 _SFR_IO8(0x1A) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TIFR5 { +- unsigned int tov5 : 1; /* Timer/Counter5 Overflow Flag */ +- unsigned int ocf5a : 1; /* Timer/Counter5 Output Compare A Match Flag */ +- unsigned int ocf5b : 1; /* Timer/Counter5 Output Compare B Match Flag */ +- unsigned int ocf5c : 1; /* Timer/Counter5 Output Compare C Match Flag */ +- unsigned int : 1; +- unsigned int icf5 : 1; /* Timer/Counter5 Input Capture Flag */ +- unsigned int : 2; +-}; +- +-#define TIFR5_struct _SFR_IO8_STRUCT(0x1a, struct __reg_TIFR5) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TIFR5 */ +- +-#define TOV5 0 +-#define OCF5A 1 +-#define OCF5B 2 +-#define OCF5C 3 +-#define ICF5 5 +- +-/* Pin Change Interrupt Flag Register */ +-#define PCIFR _SFR_IO8(0x1B) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_PCIFR { +- unsigned int pcif : 3; /* Pin Change Interrupt Flag 2 */ +- unsigned int : 5; +-}; +- +-#define PCIFR_struct _SFR_IO8_STRUCT(0x1b, struct __reg_PCIFR) +- +-#endif /* __ASSEMBLER__ */ +- +- /* PCIFR */ +- +-#define PCIF0 0 +-#define PCIF1 1 +-#define PCIF2 2 +- +-/* External Interrupt Flag Register */ +-#define EIFR _SFR_IO8(0x1C) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_EIFR { +- unsigned int intf : 8; /* External Interrupt Flag */ +-}; +- +-#define EIFR_struct _SFR_IO8_STRUCT(0x1c, struct __reg_EIFR) +- +-#endif /* __ASSEMBLER__ */ +- +- /* EIFR */ +- +-#define INTF0 0 +-#define INTF1 1 +-#define INTF2 2 +-#define INTF3 3 +-#define INTF4 4 +-#define INTF5 5 +-#define INTF6 6 +-#define INTF7 7 +- +-/* External Interrupt Mask Register */ +-#define EIMSK _SFR_IO8(0x1D) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_EIMSK { +- unsigned int intm : 8; /* External Interrupt Request Enable */ +-}; +- +-#define EIMSK_struct _SFR_IO8_STRUCT(0x1d, struct __reg_EIMSK) +- +-#endif /* __ASSEMBLER__ */ +- +- /* EIMSK */ +- +-#define INT0 0 +-#define INT1 1 +-#define INT2 2 +-#define INT3 3 +-#define INT4 4 +-#define INT5 5 +-#define INT6 6 +-#define INT7 7 +- +-/* General Purpose IO Register 0 */ +-#define GPIOR0 _SFR_IO8(0x1E) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_GPIOR0 { +- unsigned int gpior0 : 8; /* General Purpose I/O Register 0 Value */ +-}; +- +-#define GPIOR0_struct _SFR_IO8_STRUCT(0x1e, struct __reg_GPIOR0) +- +-#endif /* __ASSEMBLER__ */ +- +- /* GPIOR0 */ +- +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-/* 6-char sequence denoting where to find the EEPROM registers in memory space. +- Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM +- subroutines. +- First two letters: EECR address. +- Second two letters: EEDR address. +- Last two letters: EEAR address. */ +- +-#define __EEPROM_REG_LOCATIONS__ 1F2021 +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1F) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_EECR { +- unsigned int eere : 1; /* EEPROM Read Enable */ +- unsigned int eepe : 1; /* EEPROM Programming Enable */ +- unsigned int eempe : 1; /* EEPROM Master Write Enable */ +- unsigned int eerie : 1; /* EEPROM Ready Interrupt Enable */ +- unsigned int eepm : 2; /* EEPROM Programming Mode */ +- unsigned int : 2; +-}; +- +-#define EECR_struct _SFR_IO8_STRUCT(0x1f, struct __reg_EECR) +- +-#endif /* __ASSEMBLER__ */ +- +- /* EECR */ +- +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x20) +- +- /* EEDR */ +- +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-/* EEPROM Address Register Bytes */ +-#define EEAR _SFR_IO16(0x21) +-#define EEARL _SFR_IO8(0x21) +-#define EEARH _SFR_IO8(0x22) +- +-/* General Timer/Counter Control Register */ +-#define GTCCR _SFR_IO8(0x23) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_GTCCR { +- unsigned int psrsync : 1; /* Prescaler Reset for Synchronous Timer/Counters */ +- unsigned int psrasy : 1; /* Prescaler Reset Timer/Counter2 */ +- unsigned int : 5; +- unsigned int tsm : 1; /* Timer/Counter Synchronization Mode */ +-}; +- +-#define GTCCR_struct _SFR_IO8_STRUCT(0x23, struct __reg_GTCCR) +- +-#endif /* __ASSEMBLER__ */ +- +- /* GTCCR */ +- +-#define PSRSYNC 0 +-#define PSR10 0 +-#define PSRASY 1 +-#define PSR2 1 +-#define TSM 7 +- +-/* Timer/Counter0 Control Register A */ +-#define TCCR0A _SFR_IO8(0x24) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TCCR0A { +- unsigned int wgm0 : 2; /* Waveform Generation Mode */ +- unsigned int : 2; +- unsigned int com0b : 2; /* Compare Match Output B Mode */ +- unsigned int com0a : 2; /* Compare Match Output A Mode */ +-}; +- +-#define TCCR0A_struct _SFR_IO8_STRUCT(0x24, struct __reg_TCCR0A) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TCCR0A */ +- +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-/* Timer/Counter0 Control Register B */ +-#define TCCR0B _SFR_IO8(0x25) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TCCR0B { +- unsigned int cs0 : 3; /* Clock Select */ +- unsigned int wgm02 : 1; /* */ +- unsigned int : 2; +- unsigned int foc0b : 1; /* Force Output Compare B */ +- unsigned int foc0a : 1; /* Force Output Compare A */ +-}; +- +-#define TCCR0B_struct _SFR_IO8_STRUCT(0x25, struct __reg_TCCR0B) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TCCR0B */ +- +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-/* Timer/Counter0 Register */ +-#define TCNT0 _SFR_IO8(0x26) +- +- /* TCNT0 */ +- +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-/* Timer/Counter0 Output Compare Register */ +-#define OCR0A _SFR_IO8(0x27) +- +- /* OCR0A */ +- +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-/* Timer/Counter0 Output Compare Register B */ +-#define OCR0B _SFR_IO8(0x28) +- +- /* OCR0B */ +- +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-/* General Purpose IO Register 1 */ +-#define GPIOR1 _SFR_IO8(0x2A) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_GPIOR1 { +- unsigned int gpior1 : 8; /* General Purpose I/O Register 1 Value */ +-}; +- +-#define GPIOR1_struct _SFR_IO8_STRUCT(0x2a, struct __reg_GPIOR1) +- +-#endif /* __ASSEMBLER__ */ +- +- /* GPIOR1 */ +- +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-/* General Purpose I/O Register 2 */ +-#define GPIOR2 _SFR_IO8(0x2B) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_GPIOR2 { +- unsigned int gpior2 : 8; /* General Purpose I/O Register 2 Value */ +-}; +- +-#define GPIOR2_struct _SFR_IO8_STRUCT(0x2b, struct __reg_GPIOR2) +- +-#endif /* __ASSEMBLER__ */ +- +- /* GPIOR2 */ +- +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-/* SPI Control Register */ +-#define SPCR _SFR_IO8(0x2C) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SPCR { +- unsigned int spr : 2; /* SPI Clock Rate Select 1 and 0 */ +- unsigned int cpha : 1; /* Clock Phase */ +- unsigned int cpol : 1; /* Clock polarity */ +- unsigned int mstr : 1; /* Master/Slave Select */ +- unsigned int dord : 1; /* Data Order */ +- unsigned int spe : 1; /* SPI Enable */ +- unsigned int spie : 1; /* SPI Interrupt Enable */ +-}; +- +-#define SPCR_struct _SFR_IO8_STRUCT(0x2c, struct __reg_SPCR) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SPCR */ +- +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-/* SPI Status Register */ +-#define SPSR _SFR_IO8(0x2D) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SPSR { +- unsigned int spi2x : 1; /* Double SPI Speed Bit */ +- unsigned int : 5; +- unsigned int wcol : 1; /* Write Collision Flag */ +- unsigned int spif : 1; /* SPI Interrupt Flag */ +-}; +- +-#define SPSR_struct _SFR_IO8_STRUCT(0x2d, struct __reg_SPSR) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SPSR */ +- +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-/* SPI Data Register */ +-#define SPDR _SFR_IO8(0x2E) +- +- /* SPDR */ +- +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-/* Analog Comparator Control And Status Register */ +-#define ACSR _SFR_IO8(0x30) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_ACSR { +- unsigned int acis : 2; /* Analog Comparator Interrupt Mode Select */ +- unsigned int acic : 1; /* Analog Comparator Input Capture Enable */ +- unsigned int acie : 1; /* Analog Comparator Interrupt Enable */ +- unsigned int aci : 1; /* Analog Comparator Interrupt Flag */ +- unsigned int aco : 1; /* Analog Compare Output */ +- unsigned int acbg : 1; /* Analog Comparator Bandgap Select */ +- unsigned int acd : 1; /* Analog Comparator Disable */ +-}; +- +-#define ACSR_struct _SFR_IO8_STRUCT(0x30, struct __reg_ACSR) +- +-#endif /* __ASSEMBLER__ */ +- +- /* ACSR */ +- +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-/* On-Chip Debug Register */ +-#define OCDR _SFR_IO8(0x31) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_OCDR { +- unsigned int ocdr : 8; /* On-Chip Debug Register Data */ +-}; +- +-#define OCDR_struct _SFR_IO8_STRUCT(0x31, struct __reg_OCDR) +- +-#endif /* __ASSEMBLER__ */ +- +- /* OCDR */ +- +-#define OCDR0 0 +-#define OCDR1 1 +-#define OCDR2 2 +-#define OCDR3 3 +-#define OCDR4 4 +-#define OCDR5 5 +-#define OCDR6 6 +-#define OCDR7 7 +-#define IDRD 7 +- +-/* Sleep Mode Control Register */ +-#define SMCR _SFR_IO8(0x33) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SMCR { +- unsigned int se : 1; /* Sleep Enable */ +- unsigned int sm : 3; /* Sleep Mode Select bits */ +- unsigned int : 4; +-}; +- +-#define SMCR_struct _SFR_IO8_STRUCT(0x33, struct __reg_SMCR) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SMCR */ +- +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-/* MCU Status Register */ +-#define MCUSR _SFR_IO8(0x34) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_MCUSR { +- unsigned int porf : 1; /* Power-on Reset Flag */ +- unsigned int extrf : 1; /* External Reset Flag */ +- unsigned int borf : 1; /* Brown-out Reset Flag */ +- unsigned int wdrf : 1; /* Watchdog Reset Flag */ +- unsigned int jtrf : 1; /* JTAG Reset Flag */ +- unsigned int : 3; +-}; +- +-#define MCUSR_struct _SFR_IO8_STRUCT(0x34, struct __reg_MCUSR) +- +-#endif /* __ASSEMBLER__ */ +- +- /* MCUSR */ +- +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +-#define JTRF 4 +- +-/* MCU Control Register */ +-#define MCUCR _SFR_IO8(0x35) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_MCUCR { +- unsigned int ivce : 1; /* Interrupt Vector Change Enable */ +- unsigned int ivsel : 1; /* Interrupt Vector Select */ +- unsigned int : 2; +- unsigned int pud : 1; /* Pull-up Disable */ +- unsigned int : 2; +- unsigned int jtd : 1; /* JTAG Interface Disable */ +-}; +- +-#define MCUCR_struct _SFR_IO8_STRUCT(0x35, struct __reg_MCUCR) +- +-#endif /* __ASSEMBLER__ */ +- +- /* MCUCR */ +- +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define JTD 7 +- +-/* Store Program Memory Control Register */ +-#define SPMCSR _SFR_IO8(0x37) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SPMCSR { +- unsigned int spmen : 1; /* Store Program Memory Enable */ +- unsigned int pgers : 1; /* Page Erase */ +- unsigned int pgwrt : 1; /* Page Write */ +- unsigned int blbset : 1; /* Boot Lock Bit Set */ +- unsigned int rwwsre : 1; /* Read While Write Section Read Enable */ +- unsigned int sigrd : 1; /* Signature Row Read */ +- unsigned int rwwsb : 1; /* Read While Write Section Busy */ +- unsigned int spmie : 1; /* SPM Interrupt Enable */ +-}; +- +-#define SPMCSR_struct _SFR_IO8_STRUCT(0x37, struct __reg_SPMCSR) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SPMCSR */ +- +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define SIGRD 5 +-#define RWWSB 6 +-#define SPMIE 7 +- +-/* Extended Z-pointer Register for ELPM/SPM */ +-#define RAMPZ _SFR_IO8(0x3B) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_RAMPZ { +- unsigned int rampz : 2; /* Extended Z-Pointer Value */ +- unsigned int : 6; +-}; +- +-#define RAMPZ_struct _SFR_IO8_STRUCT(0x3b, struct __reg_RAMPZ) +- +-#endif /* __ASSEMBLER__ */ +- +- /* RAMPZ */ +- +-#define RAMPZ0 0 +-#define RAMPZ1 1 +- +-/* Stack Pointer */ +-#define SP _SFR_IO16(0x3D) +-#define SPL _SFR_IO8(0x3D) +-#define SPH _SFR_IO8(0x3E) +- +-/* Status Register */ +-#define SREG _SFR_IO8(0x3F) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SREG { +- unsigned int c : 1; /* Carry Flag */ +- unsigned int z : 1; /* Zero Flag */ +- unsigned int n : 1; /* Negative Flag */ +- unsigned int v : 1; /* Two's Complement Overflow Flag */ +- unsigned int s : 1; /* Sign Bit */ +- unsigned int h : 1; /* Half Carry Flag */ +- unsigned int t : 1; /* Bit Copy Storage */ +- unsigned int i : 1; /* Global Interrupt Enable */ +-}; +- +-#define SREG_struct _SFR_IO8_STRUCT(0x3f, struct __reg_SREG) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SREG */ +- +-#define SREG_C 0 +-#define SREG_Z 1 +-#define SREG_N 2 +-#define SREG_V 3 +-#define SREG_S 4 +-#define SREG_H 5 +-#define SREG_T 6 +-#define SREG_I 7 +- +-/* Watchdog Timer Control Register */ +-#define WDTCSR _SFR_MEM8(0x60) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_WDTCSR { +- unsigned int wdp : 3; /* Watchdog Timer Prescaler bits */ +- unsigned int wde : 1; /* Watch Dog Enable */ +- unsigned int wdce : 1; /* Watchdog Change Enable */ +- unsigned int : 1; +- unsigned int wdie : 1; /* Watchdog Timeout Interrupt Enable */ +- unsigned int wdif : 1; /* Watchdog Timeout Interrupt Flag */ +-}; +- +-#define WDTCSR_struct _SFR_MEM8_STRUCT(0x60, struct __reg_WDTCSR) +- +-#endif /* __ASSEMBLER__ */ +- +- /* WDTCSR */ +- +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-/* Clock Prescale Register */ +-#define CLKPR _SFR_MEM8(0x61) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_CLKPR { +- unsigned int clkps : 4; /* Clock Prescaler Select Bits */ +- unsigned int : 3; +- unsigned int clkpce : 1; /* Clock Prescaler Change Enable */ +-}; +- +-#define CLKPR_struct _SFR_MEM8_STRUCT(0x61, struct __reg_CLKPR) +- +-#endif /* __ASSEMBLER__ */ +- +- /* CLKPR */ +- +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-/* Power Reduction Register 2 */ +-#define PRR2 _SFR_MEM8(0x63) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_PRR2 { +- unsigned int prram : 4; /* Power Reduction SRAM 3 */ +- unsigned int : 4; +-}; +- +-#define PRR2_struct _SFR_MEM8_STRUCT(0x63, struct __reg_PRR2) +- +-#endif /* __ASSEMBLER__ */ +- +- /* PRR2 */ +- +-#define PRRAM0 0 +-#define PRRAM1 1 +-#define PRRAM2 2 +-#define PRRAM3 3 +- +-/* Power Reduction Register0 */ +-#define PRR0 _SFR_MEM8(0x64) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_PRR0 { +- unsigned int pradc : 1; /* Power Reduction ADC */ +- unsigned int prusart0 : 1; /* Power Reduction USART */ +- unsigned int prspi : 1; /* Power Reduction Serial Peripheral Interface */ +- unsigned int prtim1 : 1; /* Power Reduction Timer/Counter1 */ +- unsigned int prpga : 1; /* Power Reduction PGA */ +- unsigned int prtim0 : 1; /* Power Reduction Timer/Counter0 */ +- unsigned int prtim2 : 1; /* Power Reduction Timer/Counter2 */ +- unsigned int prtwi : 1; /* Power Reduction TWI */ +-}; +- +-#define PRR0_struct _SFR_MEM8_STRUCT(0x64, struct __reg_PRR0) +- +-#endif /* __ASSEMBLER__ */ +- +- /* PRR0 */ +- +-#define PRADC 0 +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM1 3 +-#define PRPGA 4 +-#define PRTIM0 5 +-#define PRTIM2 6 +-#define PRTWI 7 +- +-/* Power Reduction Register 1 */ +-#define PRR1 _SFR_MEM8(0x65) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_PRR1 { +- unsigned int prusart : 3; /* Reserved */ +- unsigned int prtim3 : 1; /* Power Reduction Timer/Counter3 */ +- unsigned int prtim4 : 1; /* Power Reduction Timer/Counter4 */ +- unsigned int prtim5 : 1; /* Power Reduction Timer/Counter5 */ +- unsigned int prtrx24 : 1; /* Power Reduction Transceiver */ +- unsigned int : 1; +-}; +- +-#define PRR1_struct _SFR_MEM8_STRUCT(0x65, struct __reg_PRR1) +- +-#endif /* __ASSEMBLER__ */ +- +- /* PRR1 */ +- +-#define PRUSART1 0 +-#define PRUSART2 1 +-#define PRUSART3 2 +-#define PRTIM3 3 +-#define PRTIM4 4 +-#define PRTIM5 5 +-#define PRTRX24 6 +- +-/* Oscillator Calibration Value */ +-#define OSCCAL _SFR_MEM8(0x66) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_OSCCAL { +- unsigned int cal : 8; /* Oscillator Calibration Tuning Value */ +-}; +- +-#define OSCCAL_struct _SFR_MEM8_STRUCT(0x66, struct __reg_OSCCAL) +- +-#endif /* __ASSEMBLER__ */ +- +- /* OSCCAL */ +- +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-/* Reference Voltage Calibration Register */ +-#define BGCR _SFR_MEM8(0x67) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_BGCR { +- unsigned int bgcal : 3; /* Coarse Calibration Bits */ +- unsigned int bgcal_fine : 4; /* Fine Calibration Bits */ +- unsigned int : 1; +-}; +- +-#define BGCR_struct _SFR_MEM8_STRUCT(0x67, struct __reg_BGCR) +- +-#endif /* __ASSEMBLER__ */ +- +- /* BGCR */ +- +-#define BGCAL0 0 +-#define BGCAL1 1 +-#define BGCAL2 2 +-#define BGCAL_FINE0 3 +-#define BGCAL_FINE1 4 +-#define BGCAL_FINE2 5 +-#define BGCAL_FINE3 6 +- +-/* Pin Change Interrupt Control Register */ +-#define PCICR _SFR_MEM8(0x68) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_PCICR { +- unsigned int pcie : 3; /* Pin Change Interrupt Enable 2 */ +- unsigned int : 5; +-}; +- +-#define PCICR_struct _SFR_MEM8_STRUCT(0x68, struct __reg_PCICR) +- +-#endif /* __ASSEMBLER__ */ +- +- /* PCICR */ +- +-#define PCIE0 0 +-#define PCIE1 1 +-#define PCIE2 2 +- +-/* External Interrupt Control Register A */ +-#define EICRA _SFR_MEM8(0x69) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_EICRA { +- unsigned int isc0 : 2; /* External Interrupt 0 Sense Control Bit */ +- unsigned int isc1 : 2; /* External Interrupt 1 Sense Control Bit */ +- unsigned int isc2 : 2; /* External Interrupt 2 Sense Control Bit */ +- unsigned int isc3 : 2; /* External Interrupt 3 Sense Control Bit */ +-}; +- +-#define EICRA_struct _SFR_MEM8_STRUCT(0x69, struct __reg_EICRA) +- +-#endif /* __ASSEMBLER__ */ +- +- /* EICRA */ +- +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define ISC20 4 +-#define ISC21 5 +-#define ISC30 6 +-#define ISC31 7 +- +-/* External Interrupt Control Register B */ +-#define EICRB _SFR_MEM8(0x6A) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_EICRB { +- unsigned int isc4 : 2; /* External Interrupt 4 Sense Control Bit */ +- unsigned int isc5 : 2; /* External Interrupt 5 Sense Control Bit */ +- unsigned int isc6 : 2; /* External Interrupt 6 Sense Control Bit */ +- unsigned int isc7 : 2; /* External Interrupt 7 Sense Control Bit */ +-}; +- +-#define EICRB_struct _SFR_MEM8_STRUCT(0x6a, struct __reg_EICRB) +- +-#endif /* __ASSEMBLER__ */ +- +- /* EICRB */ +- +-#define ISC40 0 +-#define ISC41 1 +-#define ISC50 2 +-#define ISC51 3 +-#define ISC60 4 +-#define ISC61 5 +-#define ISC70 6 +-#define ISC71 7 +- +-/* Pin Change Mask Register 0 */ +-#define PCMSK0 _SFR_MEM8(0x6B) +- +- /* PCMSK0 */ +- +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-/* Pin Change Mask Register 1 */ +-#define PCMSK1 _SFR_MEM8(0x6C) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_PCMSK1 { +- unsigned int pcint : 2; /* Pin Change Enable Mask */ +- unsigned int pcint1 : 6; /* Pin Change Enable Mask */ +-}; +- +-#define PCMSK1_struct _SFR_MEM8_STRUCT(0x6c, struct __reg_PCMSK1) +- +-#endif /* __ASSEMBLER__ */ +- +- /* PCMSK1 */ +- +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-/* Pin Change Mask Register 2 */ +-#define PCMSK2 _SFR_MEM8(0x6D) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_PCMSK2 { +- unsigned int pcint1 : 4; /* Pin Change Enable Mask */ +- unsigned int pcint2 : 4; /* Pin Change Enable Mask */ +-}; +- +-#define PCMSK2_struct _SFR_MEM8_STRUCT(0x6d, struct __reg_PCMSK2) +- +-#endif /* __ASSEMBLER__ */ +- +- /* PCMSK2 */ +- +-#define PCINT16 0 +-#define PCINT17 1 +-#define PCINT18 2 +-#define PCINT19 3 +-#define PCINT20 4 +-#define PCINT21 5 +-#define PCINT22 6 +-#define PCINT23 7 +- +-/* Timer/Counter0 Interrupt Mask Register */ +-#define TIMSK0 _SFR_MEM8(0x6E) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TIMSK0 { +- unsigned int toie0 : 1; /* Timer/Counter0 Overflow Interrupt Enable */ +- unsigned int ocie0a : 1; /* Timer/Counter0 Output Compare Match A Interrupt Enable */ +- unsigned int ocie0b : 1; /* Timer/Counter0 Output Compare Match B Interrupt Enable */ +- unsigned int : 5; +-}; +- +-#define TIMSK0_struct _SFR_MEM8_STRUCT(0x6e, struct __reg_TIMSK0) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TIMSK0 */ +- +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-/* Timer/Counter1 Interrupt Mask Register */ +-#define TIMSK1 _SFR_MEM8(0x6F) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TIMSK1 { +- unsigned int toie1 : 1; /* Timer/Counter1 Overflow Interrupt Enable */ +- unsigned int ocie1a : 1; /* Timer/Counter1 Output Compare A Match Interrupt Enable */ +- unsigned int ocie1b : 1; /* Timer/Counter1 Output Compare B Match Interrupt Enable */ +- unsigned int ocie1c : 1; /* Timer/Counter1 Output Compare C Match Interrupt Enable */ +- unsigned int : 1; +- unsigned int icie1 : 1; /* Timer/Counter1 Input Capture Interrupt Enable */ +- unsigned int : 2; +-}; +- +-#define TIMSK1_struct _SFR_MEM8_STRUCT(0x6f, struct __reg_TIMSK1) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TIMSK1 */ +- +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define OCIE1C 3 +-#define ICIE1 5 +- +-/* Timer/Counter Interrupt Mask register */ +-#define TIMSK2 _SFR_MEM8(0x70) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TIMSK2 { +- unsigned int toie2 : 1; /* Timer/Counter2 Overflow Interrupt Enable */ +- unsigned int ocie2a : 1; /* Timer/Counter2 Output Compare Match A Interrupt Enable */ +- unsigned int ocie2b : 1; /* Timer/Counter2 Output Compare Match B Interrupt Enable */ +- unsigned int : 5; +-}; +- +-#define TIMSK2_struct _SFR_MEM8_STRUCT(0x70, struct __reg_TIMSK2) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TIMSK2 */ +- +-#define TOIE2 0 +-#define TOIE2A 0 +-#define OCIE2A 1 +-#define OCIE2B 2 +- +-/* Timer/Counter3 Interrupt Mask Register */ +-#define TIMSK3 _SFR_MEM8(0x71) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TIMSK3 { +- unsigned int toie3 : 1; /* Timer/Counter3 Overflow Interrupt Enable */ +- unsigned int ocie3a : 1; /* Timer/Counter3 Output Compare A Match Interrupt Enable */ +- unsigned int ocie3b : 1; /* Timer/Counter3 Output Compare B Match Interrupt Enable */ +- unsigned int ocie3c : 1; /* Timer/Counter3 Output Compare C Match Interrupt Enable */ +- unsigned int : 1; +- unsigned int icie3 : 1; /* Timer/Counter3 Input Capture Interrupt Enable */ +- unsigned int : 2; +-}; +- +-#define TIMSK3_struct _SFR_MEM8_STRUCT(0x71, struct __reg_TIMSK3) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TIMSK3 */ +- +-#define TOIE3 0 +-#define OCIE3A 1 +-#define OCIE3B 2 +-#define OCIE3C 3 +-#define ICIE3 5 +- +-/* Timer/Counter4 Interrupt Mask Register */ +-#define TIMSK4 _SFR_MEM8(0x72) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TIMSK4 { +- unsigned int toie4 : 1; /* Timer/Counter4 Overflow Interrupt Enable */ +- unsigned int ocie4a : 1; /* Timer/Counter4 Output Compare A Match Interrupt Enable */ +- unsigned int ocie4b : 1; /* Timer/Counter4 Output Compare B Match Interrupt Enable */ +- unsigned int ocie4c : 1; /* Timer/Counter4 Output Compare C Match Interrupt Enable */ +- unsigned int : 1; +- unsigned int icie4 : 1; /* Timer/Counter4 Input Capture Interrupt Enable */ +- unsigned int : 2; +-}; +- +-#define TIMSK4_struct _SFR_MEM8_STRUCT(0x72, struct __reg_TIMSK4) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TIMSK4 */ +- +-#define TOIE4 0 +-#define OCIE4A 1 +-#define OCIE4B 2 +-#define OCIE4C 3 +-#define ICIE4 5 +- +-/* Timer/Counter5 Interrupt Mask Register */ +-#define TIMSK5 _SFR_MEM8(0x73) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TIMSK5 { +- unsigned int toie5 : 1; /* Timer/Counter5 Overflow Interrupt Enable */ +- unsigned int ocie5a : 1; /* Timer/Counter5 Output Compare A Match Interrupt Enable */ +- unsigned int ocie5b : 1; /* Timer/Counter5 Output Compare B Match Interrupt Enable */ +- unsigned int ocie5c : 1; /* Timer/Counter5 Output Compare C Match Interrupt Enable */ +- unsigned int : 1; +- unsigned int icie5 : 1; /* Timer/Counter5 Input Capture Interrupt Enable */ +- unsigned int : 2; +-}; +- +-#define TIMSK5_struct _SFR_MEM8_STRUCT(0x73, struct __reg_TIMSK5) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TIMSK5 */ +- +-#define TOIE5 0 +-#define OCIE5A 1 +-#define OCIE5B 2 +-#define OCIE5C 3 +-#define ICIE5 5 +- +-/* Flash Extended-Mode Control-Register */ +-#define NEMCR _SFR_MEM8(0x75) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_NEMCR { +- unsigned int : 4; +- unsigned int aeam : 2; /* Address for Extended Address Mode of Extra Rows */ +- unsigned int eneam : 1; /* Enable Extended Address Mode for Extra Rows */ +- unsigned int : 1; +-}; +- +-#define NEMCR_struct _SFR_MEM8_STRUCT(0x75, struct __reg_NEMCR) +- +-#endif /* __ASSEMBLER__ */ +- +- /* NEMCR */ +- +-#define AEAM0 4 +-#define AEAM1 5 +-#define ENEAM 6 +- +-/* The ADC Control and Status Register C */ +-#define ADCSRC _SFR_MEM8(0x77) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_ADCSRC { +- unsigned int adsut : 5; /* ADC Start-up Time */ +- unsigned int res0 : 1; /* Reserved */ +- unsigned int adtht : 2; /* ADC Track-and-Hold Time */ +-}; +- +-#define ADCSRC_struct _SFR_MEM8_STRUCT(0x77, struct __reg_ADCSRC) +- +-#endif /* __ASSEMBLER__ */ +- +- /* ADCSRC */ +- +-#define ADSUT0 0 +-#define ADSUT1 1 +-#define ADSUT2 2 +-#define ADSUT3 3 +-#define ADSUT4 4 +-#define ADTHT0 6 +-#define ADTHT1 7 +- +-/* ADC Data Register Bytes */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#define ADCL _SFR_MEM8(0x78) +-#define ADCH _SFR_MEM8(0x79) +-#endif /* __ASSEMBLER__ */ +-#define ADCW _SFR_MEM16(0x78) +-#define ADCWL _SFR_MEM8(0x78) +-#define ADCWH _SFR_MEM8(0x79) +- +-/* The ADC Control and Status Register A */ +-#define ADCSRA _SFR_MEM8(0x7A) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_ADCSRA { +- unsigned int adps : 3; /* ADC Prescaler Select Bits */ +- unsigned int adie : 1; /* ADC Interrupt Enable */ +- unsigned int adif : 1; /* ADC Interrupt Flag */ +- unsigned int adate : 1; /* ADC Auto Trigger Enable */ +- unsigned int adsc : 1; /* ADC Start Conversion */ +- unsigned int aden : 1; /* ADC Enable */ +-}; +- +-#define ADCSRA_struct _SFR_MEM8_STRUCT(0x7a, struct __reg_ADCSRA) +- +-#endif /* __ASSEMBLER__ */ +- +- /* ADCSRA */ +- +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-/* ADC Control and Status Register B */ +-#define ADCSRB _SFR_MEM8(0x7B) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_ADCSRB { +- unsigned int adts : 3; /* ADC Auto Trigger Source */ +- unsigned int mux5 : 1; /* Analog Channel and Gain Selection Bits */ +- unsigned int acch : 1; /* Analog Channel Change */ +- unsigned int refok : 1; /* Reference Voltage OK */ +- unsigned int acme : 1; /* Analog Comparator Multiplexer Enable */ +- unsigned int avddok : 1; /* AVDD Supply Voltage OK */ +-}; +- +-#define ADCSRB_struct _SFR_MEM8_STRUCT(0x7b, struct __reg_ADCSRB) +- +-#endif /* __ASSEMBLER__ */ +- +- /* ADCSRB */ +- +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define MUX5 3 +-#define ACCH 4 +-#define REFOK 5 +-#define ACME 6 +-#define AVDDOK 7 +- +-/* The ADC Multiplexer Selection Register */ +-#define ADMUX _SFR_MEM8(0x7C) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_ADMUX { +- unsigned int mux : 5; /* Analog Channel and Gain Selection Bits */ +- unsigned int adlar : 1; /* ADC Left Adjust Result */ +- unsigned int refs : 2; /* Reference Selection Bits */ +-}; +- +-#define ADMUX_struct _SFR_MEM8_STRUCT(0x7c, struct __reg_ADMUX) +- +-#endif /* __ASSEMBLER__ */ +- +- /* ADMUX */ +- +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-/* Digital Input Disable Register 2 */ +-#define DIDR2 _SFR_MEM8(0x7D) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_DIDR2 { +- unsigned int adc8d : 1; /* Reserved Bits */ +- unsigned int adc9d : 1; /* Reserved Bits */ +- unsigned int adc10d : 1; /* Reserved Bits */ +- unsigned int adc11d : 1; /* Reserved Bits */ +- unsigned int adc12d : 1; /* Reserved Bits */ +- unsigned int adc13d : 1; /* Reserved Bits */ +- unsigned int adc14d : 1; /* Reserved Bits */ +- unsigned int adc15d : 1; /* Reserved Bits */ +-}; +- +-#define DIDR2_struct _SFR_MEM8_STRUCT(0x7d, struct __reg_DIDR2) +- +-#endif /* __ASSEMBLER__ */ +- +- /* DIDR2 */ +- +-#define ADC8D 0 +-#define ADC9D 1 +-#define ADC10D 2 +-#define ADC11D 3 +-#define ADC12D 4 +-#define ADC13D 5 +-#define ADC14D 6 +-#define ADC15D 7 +- +-/* Digital Input Disable Register 0 */ +-#define DIDR0 _SFR_MEM8(0x7E) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_DIDR0 { +- unsigned int adc0d : 1; /* Disable ADC7:0 Digital Input */ +- unsigned int adc1d : 1; /* Disable ADC7:0 Digital Input */ +- unsigned int adc2d : 1; /* Disable ADC7:0 Digital Input */ +- unsigned int adc3d : 1; /* Disable ADC7:0 Digital Input */ +- unsigned int adc4d : 1; /* Disable ADC7:0 Digital Input */ +- unsigned int adc5d : 1; /* Disable ADC7:0 Digital Input */ +- unsigned int adc6d : 1; /* Disable ADC7:0 Digital Input */ +- unsigned int adc7d : 1; /* Disable ADC7:0 Digital Input */ +-}; +- +-#define DIDR0_struct _SFR_MEM8_STRUCT(0x7e, struct __reg_DIDR0) +- +-#endif /* __ASSEMBLER__ */ +- +- /* DIDR0 */ +- +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-/* Digital Input Disable Register 1 */ +-#define DIDR1 _SFR_MEM8(0x7F) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_DIDR1 { +- unsigned int ain0d : 1; /* AIN0 Digital Input Disable */ +- unsigned int ain1d : 1; /* AIN1 Digital Input Disable */ +- unsigned int : 6; +-}; +- +-#define DIDR1_struct _SFR_MEM8_STRUCT(0x7f, struct __reg_DIDR1) +- +-#endif /* __ASSEMBLER__ */ +- +- /* DIDR1 */ +- +-#define AIN0D 0 +-#define AIN1D 1 +- +-/* Timer/Counter1 Control Register A */ +-#define TCCR1A _SFR_MEM8(0x80) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TCCR1A { +- unsigned int wgm1 : 2; /* Waveform Generation Mode */ +- unsigned int com1c : 2; /* Compare Output Mode for Channel C */ +- unsigned int com1b : 2; /* Compare Output Mode for Channel B */ +- unsigned int com1a : 2; /* Compare Output Mode for Channel A */ +-}; +- +-#define TCCR1A_struct _SFR_MEM8_STRUCT(0x80, struct __reg_TCCR1A) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TCCR1A */ +- +-#define WGM10 0 +-#define WGM11 1 +-#define COM1C0 2 +-#define COM1C1 3 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-/* Timer/Counter1 Control Register B */ +-#define TCCR1B _SFR_MEM8(0x81) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TCCR1B { +- unsigned int cs1 : 3; /* Clock Select */ +- unsigned int wgm1 : 2; /* Waveform Generation Mode */ +- unsigned int : 1; +- unsigned int ices1 : 1; /* Input Capture 1 Edge Select */ +- unsigned int icnc1 : 1; /* Input Capture 1 Noise Canceller */ +-}; +- +-#define TCCR1B_struct _SFR_MEM8_STRUCT(0x81, struct __reg_TCCR1B) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TCCR1B */ +- +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-/* Timer/Counter1 Control Register C */ +-#define TCCR1C _SFR_MEM8(0x82) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TCCR1C { +- unsigned int : 5; +- unsigned int foc1c : 1; /* Force Output Compare for Channel C */ +- unsigned int foc1b : 1; /* Force Output Compare for Channel B */ +- unsigned int foc1a : 1; /* Force Output Compare for Channel A */ +-}; +- +-#define TCCR1C_struct _SFR_MEM8_STRUCT(0x82, struct __reg_TCCR1C) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TCCR1C */ +- +-#define FOC1C 5 +-#define FOC1B 6 +-#define FOC1A 7 +- +-/* Timer/Counter1 Bytes */ +-#define TCNT1 _SFR_MEM16(0x84) +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1H _SFR_MEM8(0x85) +- +-/* Timer/Counter1 Input Capture Register Bytes */ +-#define ICR1 _SFR_MEM16(0x86) +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1H _SFR_MEM8(0x87) +- +-/* Timer/Counter1 Output Compare Register A Bytes */ +-#define OCR1A _SFR_MEM16(0x88) +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AH _SFR_MEM8(0x89) +- +-/* Timer/Counter1 Output Compare Register B Bytes */ +-#define OCR1B _SFR_MEM16(0x8A) +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BH _SFR_MEM8(0x8B) +- +-/* Timer/Counter1 Output Compare Register C Bytes */ +-#define OCR1C _SFR_MEM16(0x8C) +-#define OCR1CL _SFR_MEM8(0x8C) +-#define OCR1CH _SFR_MEM8(0x8D) +- +-/* Timer/Counter3 Control Register A */ +-#define TCCR3A _SFR_MEM8(0x90) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TCCR3A { +- unsigned int wgm3 : 2; /* Waveform Generation Mode */ +- unsigned int com3c : 2; /* Compare Output Mode for Channel C */ +- unsigned int com3b : 2; /* Compare Output Mode for Channel B */ +- unsigned int com3a : 2; /* Compare Output Mode for Channel A */ +-}; +- +-#define TCCR3A_struct _SFR_MEM8_STRUCT(0x90, struct __reg_TCCR3A) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TCCR3A */ +- +-#define WGM30 0 +-#define WGM31 1 +-#define COM3C0 2 +-#define COM3C1 3 +-#define COM3B0 4 +-#define COM3B1 5 +-#define COM3A0 6 +-#define COM3A1 7 +- +-/* Timer/Counter3 Control Register B */ +-#define TCCR3B _SFR_MEM8(0x91) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TCCR3B { +- unsigned int cs3 : 3; /* Clock Select */ +- unsigned int wgm3 : 2; /* Waveform Generation Mode */ +- unsigned int : 1; +- unsigned int ices3 : 1; /* Input Capture 3 Edge Select */ +- unsigned int icnc3 : 1; /* Input Capture 3 Noise Canceller */ +-}; +- +-#define TCCR3B_struct _SFR_MEM8_STRUCT(0x91, struct __reg_TCCR3B) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TCCR3B */ +- +-#define CS30 0 +-#define CS31 1 +-#define CS32 2 +-#define WGM32 3 +-#define WGM33 4 +-#define ICES3 6 +-#define ICNC3 7 +- +-/* Timer/Counter3 Control Register C */ +-#define TCCR3C _SFR_MEM8(0x92) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TCCR3C { +- unsigned int : 5; +- unsigned int foc3c : 1; /* Force Output Compare for Channel C */ +- unsigned int foc3b : 1; /* Force Output Compare for Channel B */ +- unsigned int foc3a : 1; /* Force Output Compare for Channel A */ +-}; +- +-#define TCCR3C_struct _SFR_MEM8_STRUCT(0x92, struct __reg_TCCR3C) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TCCR3C */ +- +-#define FOC3C 5 +-#define FOC3B 6 +-#define FOC3A 7 +- +-/* Timer/Counter3 Bytes */ +-#define TCNT3 _SFR_MEM16(0x94) +-#define TCNT3L _SFR_MEM8(0x94) +-#define TCNT3H _SFR_MEM8(0x95) +- +-/* Timer/Counter3 Input Capture Register Bytes */ +-#define ICR3 _SFR_MEM16(0x96) +-#define ICR3L _SFR_MEM8(0x96) +-#define ICR3H _SFR_MEM8(0x97) +- +-/* Timer/Counter3 Output Compare Register A Bytes */ +-#define OCR3A _SFR_MEM16(0x98) +-#define OCR3AL _SFR_MEM8(0x98) +-#define OCR3AH _SFR_MEM8(0x99) +- +-/* Timer/Counter3 Output Compare Register B Bytes */ +-#define OCR3B _SFR_MEM16(0x9A) +-#define OCR3BL _SFR_MEM8(0x9A) +-#define OCR3BH _SFR_MEM8(0x9B) +- +-/* Timer/Counter3 Output Compare Register C Bytes */ +-#define OCR3C _SFR_MEM16(0x9C) +-#define OCR3CL _SFR_MEM8(0x9C) +-#define OCR3CH _SFR_MEM8(0x9D) +- +-/* Timer/Counter4 Control Register A */ +-#define TCCR4A _SFR_MEM8(0xA0) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TCCR4A { +- unsigned int wgm4 : 2; /* Waveform Generation Mode */ +- unsigned int com4c : 2; /* Compare Output Mode for Channel C */ +- unsigned int com4b : 2; /* Compare Output Mode for Channel B */ +- unsigned int com4a : 2; /* Compare Output Mode for Channel A */ +-}; +- +-#define TCCR4A_struct _SFR_MEM8_STRUCT(0xa0, struct __reg_TCCR4A) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TCCR4A */ +- +-#define WGM40 0 +-#define WGM41 1 +-#define COM4C0 2 +-#define COM4C1 3 +-#define COM4B0 4 +-#define COM4B1 5 +-#define COM4A0 6 +-#define COM4A1 7 +- +-/* Timer/Counter4 Control Register B */ +-#define TCCR4B _SFR_MEM8(0xA1) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TCCR4B { +- unsigned int cs4 : 3; /* Clock Select */ +- unsigned int wgm4 : 2; /* Waveform Generation Mode */ +- unsigned int : 1; +- unsigned int ices4 : 1; /* Input Capture 4 Edge Select */ +- unsigned int icnc4 : 1; /* Input Capture 4 Noise Canceller */ +-}; +- +-#define TCCR4B_struct _SFR_MEM8_STRUCT(0xa1, struct __reg_TCCR4B) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TCCR4B */ +- +-#define CS40 0 +-#define CS41 1 +-#define CS42 2 +-#define WGM42 3 +-#define WGM43 4 +-#define ICES4 6 +-#define ICNC4 7 +- +-/* Timer/Counter4 Control Register C */ +-#define TCCR4C _SFR_MEM8(0xA2) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TCCR4C { +- unsigned int : 5; +- unsigned int foc4c : 1; /* Force Output Compare for Channel C */ +- unsigned int foc4b : 1; /* Force Output Compare for Channel B */ +- unsigned int foc4a : 1; /* Force Output Compare for Channel A */ +-}; +- +-#define TCCR4C_struct _SFR_MEM8_STRUCT(0xa2, struct __reg_TCCR4C) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TCCR4C */ +- +-#define FOC4C 5 +-#define FOC4B 6 +-#define FOC4A 7 +- +-/* Timer/Counter4 Bytes */ +-#define TCNT4 _SFR_MEM16(0xA4) +-#define TCNT4L _SFR_MEM8(0xA4) +-#define TCNT4H _SFR_MEM8(0xA5) +- +-/* Timer/Counter4 Input Capture Register Bytes */ +-#define ICR4 _SFR_MEM16(0xA6) +-#define ICR4L _SFR_MEM8(0xA6) +-#define ICR4H _SFR_MEM8(0xA7) +- +-/* Timer/Counter4 Output Compare Register A Bytes */ +-#define OCR4A _SFR_MEM16(0xA8) +-#define OCR4AL _SFR_MEM8(0xA8) +-#define OCR4AH _SFR_MEM8(0xA9) +- +-/* Timer/Counter4 Output Compare Register B Bytes */ +-#define OCR4B _SFR_MEM16(0xAA) +-#define OCR4BL _SFR_MEM8(0xAA) +-#define OCR4BH _SFR_MEM8(0xAB) +- +-/* Timer/Counter4 Output Compare Register C Bytes */ +-#define OCR4C _SFR_MEM16(0xAC) +-#define OCR4CL _SFR_MEM8(0xAC) +-#define OCR4CH _SFR_MEM8(0xAD) +- +-/* Timer/Counter2 Control Register A */ +-#define TCCR2A _SFR_MEM8(0xB0) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TCCR2A { +- unsigned int wgm2 : 2; /* Waveform Generation Mode */ +- unsigned int : 2; +- unsigned int com2b : 2; /* Compare Match Output B Mode */ +- unsigned int com2a : 2; /* Compare Match Output A Mode */ +-}; +- +-#define TCCR2A_struct _SFR_MEM8_STRUCT(0xb0, struct __reg_TCCR2A) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TCCR2A */ +- +-#define WGM20 0 +-#define WGM21 1 +-#define COM2B0 4 +-#define COM2B1 5 +-#define COM2A0 6 +-#define COM2A1 7 +- +-/* Timer/Counter2 Control Register B */ +-#define TCCR2B _SFR_MEM8(0xB1) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TCCR2B { +- unsigned int cs2 : 3; /* Clock Select */ +- unsigned int wgm22 : 1; /* Waveform Generation Mode */ +- unsigned int : 2; +- unsigned int foc2b : 1; /* Force Output Compare B */ +- unsigned int foc2a : 1; /* Force Output Compare A */ +-}; +- +-#define TCCR2B_struct _SFR_MEM8_STRUCT(0xb1, struct __reg_TCCR2B) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TCCR2B */ +- +-#define CS20 0 +-#define CS21 1 +-#define CS22 2 +-#define WGM22 3 +-#define FOC2B 6 +-#define FOC2A 7 +- +-/* Timer/Counter2 */ +-#define TCNT2 _SFR_MEM8(0xB2) +- +- /* TCNT2 */ +- +-#define TCNT20 0 +-#define TCNT21 1 +-#define TCNT22 2 +-#define TCNT23 3 +-#define TCNT24 4 +-#define TCNT25 5 +-#define TCNT26 6 +-#define TCNT27 7 +- +-/* Timer/Counter2 Output Compare Register A */ +-#define OCR2A _SFR_MEM8(0xB3) +- +- /* OCR2A */ +- +-#define OCR2A0 0 +-#define OCR2A1 1 +-#define OCR2A2 2 +-#define OCR2A3 3 +-#define OCR2A4 4 +-#define OCR2A5 5 +-#define OCR2A6 6 +-#define OCR2A7 7 +- +-/* Timer/Counter2 Output Compare Register B */ +-#define OCR2B _SFR_MEM8(0xB4) +- +- /* OCR2B */ +- +-#define OCR2B0 0 +-#define OCR2B1 1 +-#define OCR2B2 2 +-#define OCR2B3 3 +-#define OCR2B4 4 +-#define OCR2B5 5 +-#define OCR2B6 6 +-#define OCR2B7 7 +- +-/* Asynchronous Status Register */ +-#define ASSR _SFR_MEM8(0xB6) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_ASSR { +- unsigned int tcr2bub : 1; /* Timer/Counter2 Control Register B Update Busy */ +- unsigned int tcr2aub : 1; /* Timer/Counter2 Control Register A Update Busy */ +- unsigned int ocr2bub : 1; /* Timer/Counter2 Output Compare Register B Update Busy */ +- unsigned int ocr2aub : 1; /* Timer/Counter2 Output Compare Register A Update Busy */ +- unsigned int tcn2ub : 1; /* Timer/Counter2 Update Busy */ +- unsigned int as2 : 1; /* Timer/Counter2 Asynchronous Mode */ +- unsigned int exclk : 1; /* Enable External Clock Input */ +- unsigned int exclkamr : 1; /* Enable External Clock Input for AMR */ +-}; +- +-#define ASSR_struct _SFR_MEM8_STRUCT(0xb6, struct __reg_ASSR) +- +-#endif /* __ASSEMBLER__ */ +- +- /* ASSR */ +- +-#define TCR2BUB 0 +-#define TCR2AUB 1 +-#define OCR2BUB 2 +-#define OCR2AUB 3 +-#define TCN2UB 4 +-#define AS2 5 +-#define EXCLK 6 +-#define EXCLKAMR 7 +- +-/* TWI Bit Rate Register */ +-#define TWBR _SFR_MEM8(0xB8) +- +- /* TWBR */ +- +-#define TWBR0 0 +-#define TWBR1 1 +-#define TWBR2 2 +-#define TWBR3 3 +-#define TWBR4 4 +-#define TWBR5 5 +-#define TWBR6 6 +-#define TWBR7 7 +- +-/* TWI Status Register */ +-#define TWSR _SFR_MEM8(0xB9) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TWSR { +- unsigned int twps : 2; /* TWI Prescaler Bits */ +- unsigned int : 1; +- unsigned int tws : 5; /* TWI Status */ +-}; +- +-#define TWSR_struct _SFR_MEM8_STRUCT(0xb9, struct __reg_TWSR) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TWSR */ +- +-#define TWPS0 0 +-#define TWPS1 1 +-#define TWS3 3 +-#define TWS4 4 +-#define TWS5 5 +-#define TWS6 6 +-#define TWS7 7 +- +-/* TWI (Slave) Address Register */ +-#define TWAR _SFR_MEM8(0xBA) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TWAR { +- unsigned int twgce : 1; /* TWI General Call Recognition Enable Bit */ +- unsigned int twa : 7; /* TWI (Slave) Address */ +-}; +- +-#define TWAR_struct _SFR_MEM8_STRUCT(0xba, struct __reg_TWAR) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TWAR */ +- +-#define TWGCE 0 +-#define TWA0 1 +-#define TWA1 2 +-#define TWA2 3 +-#define TWA3 4 +-#define TWA4 5 +-#define TWA5 6 +-#define TWA6 7 +- +-/* TWI Data Register */ +-#define TWDR _SFR_MEM8(0xBB) +- +- /* TWDR */ +- +-#define TWD0 0 +-#define TWD1 1 +-#define TWD2 2 +-#define TWD3 3 +-#define TWD4 4 +-#define TWD5 5 +-#define TWD6 6 +-#define TWD7 7 +- +-/* TWI Control Register */ +-#define TWCR _SFR_MEM8(0xBC) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TWCR { +- unsigned int twie : 1; /* TWI Interrupt Enable */ +- unsigned int : 1; +- unsigned int twen : 1; /* TWI Enable Bit */ +- unsigned int twwc : 1; /* TWI Write Collision Flag */ +- unsigned int twsto : 1; /* TWI STOP Condition Bit */ +- unsigned int twsta : 1; /* TWI START Condition Bit */ +- unsigned int twea : 1; /* TWI Enable Acknowledge Bit */ +- unsigned int twint : 1; /* TWI Interrupt Flag */ +-}; +- +-#define TWCR_struct _SFR_MEM8_STRUCT(0xbc, struct __reg_TWCR) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TWCR */ +- +-#define TWIE 0 +-#define TWEN 2 +-#define TWWC 3 +-#define TWSTO 4 +-#define TWSTA 5 +-#define TWEA 6 +-#define TWINT 7 +- +-/* TWI (Slave) Address Mask Register */ +-#define TWAMR _SFR_MEM8(0xBD) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TWAMR { +- unsigned int : 1; +- unsigned int twam : 7; /* TWI Address Mask */ +-}; +- +-#define TWAMR_struct _SFR_MEM8_STRUCT(0xbd, struct __reg_TWAMR) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TWAMR */ +- +-#define TWAM0 1 +-#define TWAMR0 1 +-#define TWAM1 2 +-#define TWAMR1 2 +-#define TWAM2 3 +-#define TWAMR2 3 +-#define TWAM3 4 +-#define TWAMR3 4 +-#define TWAM4 5 +-#define TWAMR4 5 +-#define TWAM5 6 +-#define TWAMR5 6 +-#define TWAM6 7 +-#define TWAMR6 7 +- +-/* USART0 Control and Status Register A */ +-#define UCSR0A _SFR_MEM8(0xC0) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_UCSR0A { +- unsigned int mpcm0 : 1; /* Multi-processor Communication Mode */ +- unsigned int u2x0 : 1; /* Double the USART Transmission Speed */ +- unsigned int upe0 : 1; /* USART Parity Error */ +- unsigned int dor0 : 1; /* Data OverRun */ +- unsigned int fe0 : 1; /* Frame Error */ +- unsigned int udre0 : 1; /* USART Data Register Empty */ +- unsigned int txc0 : 1; /* USART Transmit Complete */ +- unsigned int rxc0 : 1; /* USART Receive Complete */ +-}; +- +-#define UCSR0A_struct _SFR_MEM8_STRUCT(0xc0, struct __reg_UCSR0A) +- +-#endif /* __ASSEMBLER__ */ +- +- /* UCSR0A */ +- +-#define MPCM0 0 +-#define U2X0 1 +-#define UPE0 2 +-#define DOR0 3 +-#define FE0 4 +-#define UDRE0 5 +-#define TXC0 6 +-#define RXC0 7 +- +-/* USART0 Control and Status Register B */ +-#define UCSR0B _SFR_MEM8(0xC1) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_UCSR0B { +- unsigned int txb80 : 1; /* Transmit Data Bit 8 */ +- unsigned int rxb80 : 1; /* Receive Data Bit 8 */ +- unsigned int ucsz02 : 1; /* Character Size */ +- unsigned int txen0 : 1; /* Transmitter Enable */ +- unsigned int rxen0 : 1; /* Receiver Enable */ +- unsigned int udrie0 : 1; /* USART Data Register Empty Interrupt Enable */ +- unsigned int txcie0 : 1; /* TX Complete Interrupt Enable */ +- unsigned int rxcie0 : 1; /* RX Complete Interrupt Enable */ +-}; +- +-#define UCSR0B_struct _SFR_MEM8_STRUCT(0xc1, struct __reg_UCSR0B) +- +-#endif /* __ASSEMBLER__ */ +- +- /* UCSR0B */ +- +-#define TXB80 0 +-#define RXB80 1 +-#define UCSZ02 2 +-#define TXEN0 3 +-#define RXEN0 4 +-#define UDRIE0 5 +-#define TXCIE0 6 +-#define RXCIE0 7 +- +-/* USART0 Control and Status Register C */ +-#define UCSR0C _SFR_MEM8(0xC2) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_UCSR0C { +- unsigned int ucpol0 : 1; /* Clock Polarity */ +- unsigned int ucsz0 : 2; /* Character Size */ +- unsigned int ucpha0 : 1; /* Clock Phase */ +- unsigned int udord0 : 1; /* Data Order */ +- unsigned int usbs0 : 1; /* Stop Bit Select */ +- unsigned int upm0 : 2; /* Parity Mode */ +- unsigned int umsel0 : 2; /* USART Mode Select */ +-}; +- +-#define UCSR0C_struct _SFR_MEM8_STRUCT(0xc2, struct __reg_UCSR0C) +- +-#endif /* __ASSEMBLER__ */ +- +- /* UCSR0C */ +- +-#define UCPOL0 0 +-#define UCPHA0 1 +-#define UCPHA0 1 +-#define UCSZ00 1 +-#define UDORD0 2 +-#define UDORD0 2 +-#define UCSZ01 2 +-#define USBS0 3 +-#define UPM00 4 +-#define UPM01 5 +-#define UMSEL00 6 +-#define UMSEL0 6 +-#define UMSEL01 7 +-#define UMSEL1 7 +- +-/* USART0 Baud Rate Register Bytes */ +-#define UBRR0 _SFR_MEM16(0xC4) +-#define UBRR0L _SFR_MEM8(0xC4) +-#define UBRR0H _SFR_MEM8(0xC5) +- +-/* USART0 I/O Data Register */ +-#define UDR0 _SFR_MEM8(0xC6) +- +- /* UDR0 */ +- +-#define UDR00 0 +-#define UDR01 1 +-#define UDR02 2 +-#define UDR03 3 +-#define UDR04 4 +-#define UDR05 5 +-#define UDR06 6 +-#define UDR07 7 +- +-/* USART1 Control and Status Register A */ +-#define UCSR1A _SFR_MEM8(0xC8) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_UCSR1A { +- unsigned int mpcm1 : 1; /* Multi-processor Communication Mode */ +- unsigned int u2x1 : 1; /* Double the USART Transmission Speed */ +- unsigned int upe1 : 1; /* USART Parity Error */ +- unsigned int dor1 : 1; /* Data OverRun */ +- unsigned int fe1 : 1; /* Frame Error */ +- unsigned int udre1 : 1; /* USART Data Register Empty */ +- unsigned int txc1 : 1; /* USART Transmit Complete */ +- unsigned int rxc1 : 1; /* USART Receive Complete */ +-}; +- +-#define UCSR1A_struct _SFR_MEM8_STRUCT(0xc8, struct __reg_UCSR1A) +- +-#endif /* __ASSEMBLER__ */ +- +- /* UCSR1A */ +- +-#define MPCM1 0 +-#define U2X1 1 +-#define UPE1 2 +-#define DOR1 3 +-#define FE1 4 +-#define UDRE1 5 +-#define TXC1 6 +-#define RXC1 7 +- +-/* USART1 Control and Status Register B */ +-#define UCSR1B _SFR_MEM8(0xC9) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_UCSR1B { +- unsigned int txb81 : 1; /* Transmit Data Bit 8 */ +- unsigned int rxb81 : 1; /* Receive Data Bit 8 */ +- unsigned int ucsz12 : 1; /* Character Size */ +- unsigned int txen1 : 1; /* Transmitter Enable */ +- unsigned int rxen1 : 1; /* Receiver Enable */ +- unsigned int udrie1 : 1; /* USART Data Register Empty Interrupt Enable */ +- unsigned int txcie1 : 1; /* TX Complete Interrupt Enable */ +- unsigned int rxcie1 : 1; /* RX Complete Interrupt Enable */ +-}; +- +-#define UCSR1B_struct _SFR_MEM8_STRUCT(0xc9, struct __reg_UCSR1B) +- +-#endif /* __ASSEMBLER__ */ +- +- /* UCSR1B */ +- +-#define TXB81 0 +-#define RXB81 1 +-#define UCSZ12 2 +-#define TXEN1 3 +-#define RXEN1 4 +-#define UDRIE1 5 +-#define TXCIE1 6 +-#define RXCIE1 7 +- +-/* USART1 Control and Status Register C */ +-#define UCSR1C _SFR_MEM8(0xCA) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_UCSR1C { +- unsigned int ucpol1 : 1; /* Clock Polarity */ +- unsigned int ucsz1 : 2; /* Character Size */ +- unsigned int ucpha1 : 1; /* Clock Phase */ +- unsigned int udord1 : 1; /* Data Order */ +- unsigned int usbs1 : 1; /* Stop Bit Select */ +- unsigned int upm1 : 2; /* Parity Mode */ +- unsigned int umsel1 : 2; /* USART Mode Select */ +-}; +- +-#define UCSR1C_struct _SFR_MEM8_STRUCT(0xca, struct __reg_UCSR1C) +- +-#endif /* __ASSEMBLER__ */ +- +- /* UCSR1C */ +- +-#define UCPOL1 0 +-#define UCPHA1 1 +-#define UCPHA1 1 +-#define UCSZ10 1 +-#define UDORD1 2 +-#define UDORD1 2 +-#define UCSZ11 2 +-#define USBS1 3 +-#define UPM10 4 +-#define UPM11 5 +-#define UMSEL10 6 +-#define UMSEL11 7 +- +-/* USART1 Baud Rate Register Bytes */ +-#define UBRR1 _SFR_MEM16(0xCC) +-#define UBRR1L _SFR_MEM8(0xCC) +-#define UBRR1H _SFR_MEM8(0xCD) +- +-/* USART1 I/O Data Register */ +-#define UDR1 _SFR_MEM8(0xCE) +- +- /* UDR1 */ +- +-#define UDR10 0 +-#define UDR11 1 +-#define UDR12 2 +-#define UDR13 3 +-#define UDR14 4 +-#define UDR15 5 +-#define UDR16 6 +-#define UDR17 7 +- +-/* Symbol Counter Control Register 0 */ +-#define SCCR0 _SFR_MEM8(0xDC) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCCR0 { +- unsigned int sccmp : 3; /* Symbol Counter Compare Unit 3 Mode select */ +- unsigned int sctse : 1; /* Symbol Counter Automatic Timestamping enable */ +- unsigned int sccksel : 1; /* Symbol Counter Clock Source select */ +- unsigned int scen : 1; /* Symbol Counter enable */ +- unsigned int scmbts : 1; /* Manual Beacon Timestamp */ +- unsigned int scres : 1; /* Symbol Counter Synchronization */ +-}; +- +-#define SCCR0_struct _SFR_MEM8_STRUCT(0xdc, struct __reg_SCCR0) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCCR0 */ +- +-#define SCCMP1 0 +-#define SCCMP2 1 +-#define SCCMP3 2 +-#define SCTSE 3 +-#define SCCKSEL 4 +-#define SCEN 5 +-#define SCMBTS 6 +-#define SCRES 7 +- +-/* Symbol Counter Control Register 1 */ +-#define SCCR1 _SFR_MEM8(0xDD) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCCR1 { +- unsigned int scenbo : 1; /* Backoff Slot Counter enable */ +- unsigned int : 7; +-}; +- +-#define SCCR1_struct _SFR_MEM8_STRUCT(0xdd, struct __reg_SCCR1) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCCR1 */ +- +-#define SCENBO 0 +- +-/* Symbol Counter Status Register */ +-#define SCSR _SFR_MEM8(0xDE) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCSR { +- unsigned int scbsy : 1; /* Symbol Counter busy */ +- unsigned int : 7; +-}; +- +-#define SCSR_struct _SFR_MEM8_STRUCT(0xde, struct __reg_SCSR) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCSR */ +- +-#define SCBSY 0 +- +-/* Symbol Counter Interrupt Mask Register */ +-#define SCIRQM _SFR_MEM8(0xDF) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCIRQM { +- unsigned int irqmcp : 3; /* Symbol Counter Compare Match 3 IRQ enable */ +- unsigned int irqmof : 1; /* Symbol Counter Overflow IRQ enable */ +- unsigned int irqmbo : 1; /* Backoff Slot Counter IRQ enable */ +- unsigned int : 3; +-}; +- +-#define SCIRQM_struct _SFR_MEM8_STRUCT(0xdf, struct __reg_SCIRQM) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCIRQM */ +- +-#define IRQMCP1 0 +-#define IRQMCP2 1 +-#define IRQMCP3 2 +-#define IRQMOF 3 +-#define IRQMBO 4 +- +-/* Symbol Counter Interrupt Status Register */ +-#define SCIRQS _SFR_MEM8(0xE0) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCIRQS { +- unsigned int irqscp : 3; /* Compare Unit 3 Compare Match IRQ */ +- unsigned int irqsof : 1; /* Symbol Counter Overflow IRQ */ +- unsigned int irqsbo : 1; /* Backoff Slot Counter IRQ */ +- unsigned int : 3; +-}; +- +-#define SCIRQS_struct _SFR_MEM8_STRUCT(0xe0, struct __reg_SCIRQS) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCIRQS */ +- +-#define IRQSCP1 0 +-#define IRQSCP2 1 +-#define IRQSCP3 2 +-#define IRQSOF 3 +-#define IRQSBO 4 +- +-/* Symbol Counter Register LL-Byte */ +-#define SCCNTLL _SFR_MEM8(0xE1) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCCNTLL { +- unsigned int sccntll : 8; /* Symbol Counter Register LL-Byte */ +-}; +- +-#define SCCNTLL_struct _SFR_MEM8_STRUCT(0xe1, struct __reg_SCCNTLL) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCCNTLL */ +- +-#define SCCNTLL0 0 +-#define SCCNTLL1 1 +-#define SCCNTLL2 2 +-#define SCCNTLL3 3 +-#define SCCNTLL4 4 +-#define SCCNTLL5 5 +-#define SCCNTLL6 6 +-#define SCCNTLL7 7 +- +-/* Symbol Counter Register LH-Byte */ +-#define SCCNTLH _SFR_MEM8(0xE2) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCCNTLH { +- unsigned int sccntlh : 8; /* Symbol Counter Register LH-Byte */ +-}; +- +-#define SCCNTLH_struct _SFR_MEM8_STRUCT(0xe2, struct __reg_SCCNTLH) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCCNTLH */ +- +-#define SCCNTLH0 0 +-#define SCCNTLH1 1 +-#define SCCNTLH2 2 +-#define SCCNTLH3 3 +-#define SCCNTLH4 4 +-#define SCCNTLH5 5 +-#define SCCNTLH6 6 +-#define SCCNTLH7 7 +- +-/* Symbol Counter Register HL-Byte */ +-#define SCCNTHL _SFR_MEM8(0xE3) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCCNTHL { +- unsigned int sccnthl : 8; /* Symbol Counter Register HL-Byte */ +-}; +- +-#define SCCNTHL_struct _SFR_MEM8_STRUCT(0xe3, struct __reg_SCCNTHL) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCCNTHL */ +- +-#define SCCNTHL0 0 +-#define SCCNTHL1 1 +-#define SCCNTHL2 2 +-#define SCCNTHL3 3 +-#define SCCNTHL4 4 +-#define SCCNTHL5 5 +-#define SCCNTHL6 6 +-#define SCCNTHL7 7 +- +-/* Symbol Counter Register HH-Byte */ +-#define SCCNTHH _SFR_MEM8(0xE4) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCCNTHH { +- unsigned int sccnthh : 8; /* Symbol Counter Register HH-Byte */ +-}; +- +-#define SCCNTHH_struct _SFR_MEM8_STRUCT(0xe4, struct __reg_SCCNTHH) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCCNTHH */ +- +-#define SCCNTHH0 0 +-#define SCCNTHH1 1 +-#define SCCNTHH2 2 +-#define SCCNTHH3 3 +-#define SCCNTHH4 4 +-#define SCCNTHH5 5 +-#define SCCNTHH6 6 +-#define SCCNTHH7 7 +- +-/* Symbol Counter Beacon Timestamp Register LL-Byte */ +-#define SCBTSRLL _SFR_MEM8(0xE5) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCBTSRLL { +- unsigned int scbtsrll : 8; /* Symbol Counter Beacon Timestamp Register LL-Byte */ +-}; +- +-#define SCBTSRLL_struct _SFR_MEM8_STRUCT(0xe5, struct __reg_SCBTSRLL) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCBTSRLL */ +- +-#define SCBTSRLL0 0 +-#define SCBTSRLL1 1 +-#define SCBTSRLL2 2 +-#define SCBTSRLL3 3 +-#define SCBTSRLL4 4 +-#define SCBTSRLL5 5 +-#define SCBTSRLL6 6 +-#define SCBTSRLL7 7 +- +-/* Symbol Counter Beacon Timestamp Register LH-Byte */ +-#define SCBTSRLH _SFR_MEM8(0xE6) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCBTSRLH { +- unsigned int scbtsrlh : 8; /* Symbol Counter Beacon Timestamp Register LH-Byte */ +-}; +- +-#define SCBTSRLH_struct _SFR_MEM8_STRUCT(0xe6, struct __reg_SCBTSRLH) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCBTSRLH */ +- +-#define SCBTSRLH0 0 +-#define SCBTSRLH1 1 +-#define SCBTSRLH2 2 +-#define SCBTSRLH3 3 +-#define SCBTSRLH4 4 +-#define SCBTSRLH5 5 +-#define SCBTSRLH6 6 +-#define SCBTSRLH7 7 +- +-/* Symbol Counter Beacon Timestamp Register HL-Byte */ +-#define SCBTSRHL _SFR_MEM8(0xE7) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCBTSRHL { +- unsigned int scbtsrhl : 8; /* Symbol Counter Beacon Timestamp Register HL-Byte */ +-}; +- +-#define SCBTSRHL_struct _SFR_MEM8_STRUCT(0xe7, struct __reg_SCBTSRHL) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCBTSRHL */ +- +-#define SCBTSRHL0 0 +-#define SCBTSRHL1 1 +-#define SCBTSRHL2 2 +-#define SCBTSRHL3 3 +-#define SCBTSRHL4 4 +-#define SCBTSRHL5 5 +-#define SCBTSRHL6 6 +-#define SCBTSRHL7 7 +- +-/* Symbol Counter Beacon Timestamp Register HH-Byte */ +-#define SCBTSRHH _SFR_MEM8(0xE8) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCBTSRHH { +- unsigned int scbtsrhh : 8; /* Symbol Counter Beacon Timestamp Register HH-Byte */ +-}; +- +-#define SCBTSRHH_struct _SFR_MEM8_STRUCT(0xe8, struct __reg_SCBTSRHH) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCBTSRHH */ +- +-#define SCBTSRHH0 0 +-#define SCBTSRHH1 1 +-#define SCBTSRHH2 2 +-#define SCBTSRHH3 3 +-#define SCBTSRHH4 4 +-#define SCBTSRHH5 5 +-#define SCBTSRHH6 6 +-#define SCBTSRHH7 7 +- +-/* Symbol Counter Frame Timestamp Register LL-Byte */ +-#define SCTSRLL _SFR_MEM8(0xE9) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCTSRLL { +- unsigned int sctsrll : 8; /* Symbol Counter Frame Timestamp Register LL-Byte */ +-}; +- +-#define SCTSRLL_struct _SFR_MEM8_STRUCT(0xe9, struct __reg_SCTSRLL) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCTSRLL */ +- +-#define SCTSRLL0 0 +-#define SCTSRLL1 1 +-#define SCTSRLL2 2 +-#define SCTSRLL3 3 +-#define SCTSRLL4 4 +-#define SCTSRLL5 5 +-#define SCTSRLL6 6 +-#define SCTSRLL7 7 +- +-/* Symbol Counter Frame Timestamp Register LH-Byte */ +-#define SCTSRLH _SFR_MEM8(0xEA) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCTSRLH { +- unsigned int sctsrlh : 8; /* Symbol Counter Frame Timestamp Register LH-Byte */ +-}; +- +-#define SCTSRLH_struct _SFR_MEM8_STRUCT(0xea, struct __reg_SCTSRLH) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCTSRLH */ +- +-#define SCTSRLH0 0 +-#define SCTSRLH1 1 +-#define SCTSRLH2 2 +-#define SCTSRLH3 3 +-#define SCTSRLH4 4 +-#define SCTSRLH5 5 +-#define SCTSRLH6 6 +-#define SCTSRLH7 7 +- +-/* Symbol Counter Frame Timestamp Register HL-Byte */ +-#define SCTSRHL _SFR_MEM8(0xEB) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCTSRHL { +- unsigned int sctsrhl : 8; /* Symbol Counter Frame Timestamp Register HL-Byte */ +-}; +- +-#define SCTSRHL_struct _SFR_MEM8_STRUCT(0xeb, struct __reg_SCTSRHL) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCTSRHL */ +- +-#define SCTSRHL0 0 +-#define SCTSRHL1 1 +-#define SCTSRHL2 2 +-#define SCTSRHL3 3 +-#define SCTSRHL4 4 +-#define SCTSRHL5 5 +-#define SCTSRHL6 6 +-#define SCTSRHL7 7 +- +-/* Symbol Counter Frame Timestamp Register HH-Byte */ +-#define SCTSRHH _SFR_MEM8(0xEC) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCTSRHH { +- unsigned int sctsrhh : 8; /* Symbol Counter Frame Timestamp Register HH-Byte */ +-}; +- +-#define SCTSRHH_struct _SFR_MEM8_STRUCT(0xec, struct __reg_SCTSRHH) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCTSRHH */ +- +-#define SCTSRHH0 0 +-#define SCTSRHH1 1 +-#define SCTSRHH2 2 +-#define SCTSRHH3 3 +-#define SCTSRHH4 4 +-#define SCTSRHH5 5 +-#define SCTSRHH6 6 +-#define SCTSRHH7 7 +- +-/* Symbol Counter Output Compare Register 3 LL-Byte */ +-#define SCOCR3LL _SFR_MEM8(0xED) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCOCR3LL { +- unsigned int scocr3ll : 8; /* Symbol Counter Output Compare Register 3 LL-Byte */ +-}; +- +-#define SCOCR3LL_struct _SFR_MEM8_STRUCT(0xed, struct __reg_SCOCR3LL) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCOCR3LL */ +- +-#define SCOCR3LL0 0 +-#define SCOCR3LL1 1 +-#define SCOCR3LL2 2 +-#define SCOCR3LL3 3 +-#define SCOCR3LL4 4 +-#define SCOCR3LL5 5 +-#define SCOCR3LL6 6 +-#define SCOCR3LL7 7 +- +-/* Symbol Counter Output Compare Register 3 LH-Byte */ +-#define SCOCR3LH _SFR_MEM8(0xEE) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCOCR3LH { +- unsigned int scocr3lh : 8; /* Symbol Counter Output Compare Register 3 LH-Byte */ +-}; +- +-#define SCOCR3LH_struct _SFR_MEM8_STRUCT(0xee, struct __reg_SCOCR3LH) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCOCR3LH */ +- +-#define SCOCR3LH0 0 +-#define SCOCR3LH1 1 +-#define SCOCR3LH2 2 +-#define SCOCR3LH3 3 +-#define SCOCR3LH4 4 +-#define SCOCR3LH5 5 +-#define SCOCR3LH6 6 +-#define SCOCR3LH7 7 +- +-/* Symbol Counter Output Compare Register 3 HL-Byte */ +-#define SCOCR3HL _SFR_MEM8(0xEF) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCOCR3HL { +- unsigned int scocr3hl : 8; /* Symbol Counter Output Compare Register 3 HL-Byte */ +-}; +- +-#define SCOCR3HL_struct _SFR_MEM8_STRUCT(0xef, struct __reg_SCOCR3HL) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCOCR3HL */ +- +-#define SCOCR3HL0 0 +-#define SCOCR3HL1 1 +-#define SCOCR3HL2 2 +-#define SCOCR3HL3 3 +-#define SCOCR3HL4 4 +-#define SCOCR3HL5 5 +-#define SCOCR3HL6 6 +-#define SCOCR3HL7 7 +- +-/* Symbol Counter Output Compare Register 3 HH-Byte */ +-#define SCOCR3HH _SFR_MEM8(0xF0) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCOCR3HH { +- unsigned int scocr3hh : 8; /* Symbol Counter Output Compare Register 3 HH-Byte */ +-}; +- +-#define SCOCR3HH_struct _SFR_MEM8_STRUCT(0xf0, struct __reg_SCOCR3HH) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCOCR3HH */ +- +-#define SCOCR3HH0 0 +-#define SCOCR3HH1 1 +-#define SCOCR3HH2 2 +-#define SCOCR3HH3 3 +-#define SCOCR3HH4 4 +-#define SCOCR3HH5 5 +-#define SCOCR3HH6 6 +-#define SCOCR3HH7 7 +- +-/* Symbol Counter Output Compare Register 2 LL-Byte */ +-#define SCOCR2LL _SFR_MEM8(0xF1) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCOCR2LL { +- unsigned int scocr2ll : 8; /* Symbol Counter Output Compare Register 2 LL-Byte */ +-}; +- +-#define SCOCR2LL_struct _SFR_MEM8_STRUCT(0xf1, struct __reg_SCOCR2LL) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCOCR2LL */ +- +-#define SCOCR2LL0 0 +-#define SCOCR2LL1 1 +-#define SCOCR2LL2 2 +-#define SCOCR2LL3 3 +-#define SCOCR2LL4 4 +-#define SCOCR2LL5 5 +-#define SCOCR2LL6 6 +-#define SCOCR2LL7 7 +- +-/* Symbol Counter Output Compare Register 2 LH-Byte */ +-#define SCOCR2LH _SFR_MEM8(0xF2) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCOCR2LH { +- unsigned int scocr2lh : 8; /* Symbol Counter Output Compare Register 2 LH-Byte */ +-}; +- +-#define SCOCR2LH_struct _SFR_MEM8_STRUCT(0xf2, struct __reg_SCOCR2LH) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCOCR2LH */ +- +-#define SCOCR2LH0 0 +-#define SCOCR2LH1 1 +-#define SCOCR2LH2 2 +-#define SCOCR2LH3 3 +-#define SCOCR2LH4 4 +-#define SCOCR2LH5 5 +-#define SCOCR2LH6 6 +-#define SCOCR2LH7 7 +- +-/* Symbol Counter Output Compare Register 2 HL-Byte */ +-#define SCOCR2HL _SFR_MEM8(0xF3) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCOCR2HL { +- unsigned int scocr2hl : 8; /* Symbol Counter Output Compare Register 2 HL-Byte */ +-}; +- +-#define SCOCR2HL_struct _SFR_MEM8_STRUCT(0xf3, struct __reg_SCOCR2HL) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCOCR2HL */ +- +-#define SCOCR2HL0 0 +-#define SCOCR2HL1 1 +-#define SCOCR2HL2 2 +-#define SCOCR2HL3 3 +-#define SCOCR2HL4 4 +-#define SCOCR2HL5 5 +-#define SCOCR2HL6 6 +-#define SCOCR2HL7 7 +- +-/* Symbol Counter Output Compare Register 2 HH-Byte */ +-#define SCOCR2HH _SFR_MEM8(0xF4) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCOCR2HH { +- unsigned int scocr2hh : 8; /* Symbol Counter Output Compare Register 2 HH-Byte */ +-}; +- +-#define SCOCR2HH_struct _SFR_MEM8_STRUCT(0xf4, struct __reg_SCOCR2HH) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCOCR2HH */ +- +-#define SCOCR2HH0 0 +-#define SCOCR2HH1 1 +-#define SCOCR2HH2 2 +-#define SCOCR2HH3 3 +-#define SCOCR2HH4 4 +-#define SCOCR2HH5 5 +-#define SCOCR2HH6 6 +-#define SCOCR2HH7 7 +- +-/* Symbol Counter Output Compare Register 1 LL-Byte */ +-#define SCOCR1LL _SFR_MEM8(0xF5) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCOCR1LL { +- unsigned int scocr1ll : 8; /* Symbol Counter Output Compare Register 1 LL-Byte */ +-}; +- +-#define SCOCR1LL_struct _SFR_MEM8_STRUCT(0xf5, struct __reg_SCOCR1LL) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCOCR1LL */ +- +-#define SCOCR1LL0 0 +-#define SCOCR1LL1 1 +-#define SCOCR1LL2 2 +-#define SCOCR1LL3 3 +-#define SCOCR1LL4 4 +-#define SCOCR1LL5 5 +-#define SCOCR1LL6 6 +-#define SCOCR1LL7 7 +- +-/* Symbol Counter Output Compare Register 1 LH-Byte */ +-#define SCOCR1LH _SFR_MEM8(0xF6) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCOCR1LH { +- unsigned int scocr1lh : 8; /* Symbol Counter Output Compare Register 1 LH-Byte */ +-}; +- +-#define SCOCR1LH_struct _SFR_MEM8_STRUCT(0xf6, struct __reg_SCOCR1LH) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCOCR1LH */ +- +-#define SCOCR1LH0 0 +-#define SCOCR1LH1 1 +-#define SCOCR1LH2 2 +-#define SCOCR1LH3 3 +-#define SCOCR1LH4 4 +-#define SCOCR1LH5 5 +-#define SCOCR1LH6 6 +-#define SCOCR1LH7 7 +- +-/* Symbol Counter Output Compare Register 1 HL-Byte */ +-#define SCOCR1HL _SFR_MEM8(0xF7) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCOCR1HL { +- unsigned int scocr1hl : 8; /* Symbol Counter Output Compare Register 1 HL-Byte */ +-}; +- +-#define SCOCR1HL_struct _SFR_MEM8_STRUCT(0xf7, struct __reg_SCOCR1HL) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCOCR1HL */ +- +-#define SCOCR1HL0 0 +-#define SCOCR1HL1 1 +-#define SCOCR1HL2 2 +-#define SCOCR1HL3 3 +-#define SCOCR1HL4 4 +-#define SCOCR1HL5 5 +-#define SCOCR1HL6 6 +-#define SCOCR1HL7 7 +- +-/* Symbol Counter Output Compare Register 1 HH-Byte */ +-#define SCOCR1HH _SFR_MEM8(0xF8) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SCOCR1HH { +- unsigned int scocr1hh : 8; /* Symbol Counter Output Compare Register 1 HH-Byte */ +-}; +- +-#define SCOCR1HH_struct _SFR_MEM8_STRUCT(0xf8, struct __reg_SCOCR1HH) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SCOCR1HH */ +- +-#define SCOCR1HH0 0 +-#define SCOCR1HH1 1 +-#define SCOCR1HH2 2 +-#define SCOCR1HH3 3 +-#define SCOCR1HH4 4 +-#define SCOCR1HH5 5 +-#define SCOCR1HH6 6 +-#define SCOCR1HH7 7 +- +-/* Timer/Counter5 Control Register A */ +-#define TCCR5A _SFR_MEM8(0x120) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TCCR5A { +- unsigned int wgm5 : 2; /* Waveform Generation Mode */ +- unsigned int com5c : 2; /* Compare Output Mode for Channel C */ +- unsigned int com5b : 2; /* Compare Output Mode for Channel B */ +- unsigned int com5a : 2; /* Compare Output Mode for Channel A */ +-}; +- +-#define TCCR5A_struct _SFR_MEM8_STRUCT(0x120, struct __reg_TCCR5A) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TCCR5A */ +- +-#define WGM50 0 +-#define WGM51 1 +-#define COM5C0 2 +-#define COM5C1 3 +-#define COM5B0 4 +-#define COM5B1 5 +-#define COM5A0 6 +-#define COM5A1 7 +- +-/* Timer/Counter5 Control Register B */ +-#define TCCR5B _SFR_MEM8(0x121) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TCCR5B { +- unsigned int cs5 : 3; /* Clock Select */ +- unsigned int wgm5 : 2; /* Waveform Generation Mode */ +- unsigned int : 1; +- unsigned int ices5 : 1; /* Input Capture 5 Edge Select */ +- unsigned int icnc5 : 1; /* Input Capture 5 Noise Canceller */ +-}; +- +-#define TCCR5B_struct _SFR_MEM8_STRUCT(0x121, struct __reg_TCCR5B) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TCCR5B */ +- +-#define CS50 0 +-#define CS51 1 +-#define CS52 2 +-#define WGM52 3 +-#define WGM53 4 +-#define ICES5 6 +-#define ICNC5 7 +- +-/* Timer/Counter5 Control Register C */ +-#define TCCR5C _SFR_MEM8(0x122) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TCCR5C { +- unsigned int : 5; +- unsigned int foc5c : 1; /* Force Output Compare for Channel C */ +- unsigned int foc5b : 1; /* Force Output Compare for Channel B */ +- unsigned int foc5a : 1; /* Force Output Compare for Channel A */ +-}; +- +-#define TCCR5C_struct _SFR_MEM8_STRUCT(0x122, struct __reg_TCCR5C) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TCCR5C */ +- +-#define FOC5C 5 +-#define FOC5B 6 +-#define FOC5A 7 +- +-/* Timer/Counter5 Bytes */ +-#define TCNT5 _SFR_MEM16(0x124) +-#define TCNT5L _SFR_MEM8(0x124) +-#define TCNT5H _SFR_MEM8(0x125) +- +-/* Timer/Counter5 Input Capture Register Bytes */ +-#define ICR5 _SFR_MEM16(0x126) +-#define ICR5L _SFR_MEM8(0x126) +-#define ICR5H _SFR_MEM8(0x127) +- +-/* Timer/Counter5 Output Compare Register A Bytes */ +-#define OCR5A _SFR_MEM16(0x128) +-#define OCR5AL _SFR_MEM8(0x128) +-#define OCR5AH _SFR_MEM8(0x129) +- +-/* Timer/Counter5 Output Compare Register B Bytes */ +-#define OCR5B _SFR_MEM16(0x12A) +-#define OCR5BL _SFR_MEM8(0x12A) +-#define OCR5BH _SFR_MEM8(0x12B) +- +-/* Timer/Counter5 Output Compare Register C Bytes */ +-#define OCR5C _SFR_MEM16(0x12C) +-#define OCR5CL _SFR_MEM8(0x12C) +-#define OCR5CH _SFR_MEM8(0x12D) +- +-/* Low Leakage Voltage Regulator Control Register */ +-#define LLCR _SFR_MEM8(0x12F) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_LLCR { +- unsigned int llencal : 1; /* Enable Automatic Calibration */ +- unsigned int llshort : 1; /* Short Lower Calibration Circuit */ +- unsigned int lltco : 1; /* Temperature Coefficient of Current Source */ +- unsigned int llcal : 1; /* Calibration Active */ +- unsigned int llcomp : 1; /* Comparator Output */ +- unsigned int lldone : 1; /* Calibration Done */ +- unsigned int : 2; +-}; +- +-#define LLCR_struct _SFR_MEM8_STRUCT(0x12f, struct __reg_LLCR) +- +-#endif /* __ASSEMBLER__ */ +- +- /* LLCR */ +- +-#define LLENCAL 0 +-#define LLSHORT 1 +-#define LLTCO 2 +-#define LLCAL 3 +-#define LLCOMP 4 +-#define LLDONE 5 +- +-/* Low Leakage Voltage Regulator Data Register (Low-Byte) */ +-#define LLDRL _SFR_MEM8(0x130) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_LLDRL { +- unsigned int lldrl : 4; /* Low-Byte Data Register Bits */ +- unsigned int : 4; +-}; +- +-#define LLDRL_struct _SFR_MEM8_STRUCT(0x130, struct __reg_LLDRL) +- +-#endif /* __ASSEMBLER__ */ +- +- /* LLDRL */ +- +-#define LLDRL0 0 +-#define LLDRL1 1 +-#define LLDRL2 2 +-#define LLDRL3 3 +- +-/* Low Leakage Voltage Regulator Data Register (High-Byte) */ +-#define LLDRH _SFR_MEM8(0x131) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_LLDRH { +- unsigned int lldrh : 5; /* High-Byte Data Register Bits */ +- unsigned int : 3; +-}; +- +-#define LLDRH_struct _SFR_MEM8_STRUCT(0x131, struct __reg_LLDRH) +- +-#endif /* __ASSEMBLER__ */ +- +- /* LLDRH */ +- +-#define LLDRH0 0 +-#define LLDRH1 1 +-#define LLDRH2 2 +-#define LLDRH3 3 +-#define LLDRH4 4 +- +-/* Data Retention Configuration Register of SRAM 3 */ +-#define DRTRAM3 _SFR_MEM8(0x132) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_DRTRAM3 { +- unsigned int : 4; +- unsigned int endrt : 1; /* Enable SRAM Data Retention */ +- unsigned int drtswok : 1; /* DRT Switch OK */ +- unsigned int : 2; +-}; +- +-#define DRTRAM3_struct _SFR_MEM8_STRUCT(0x132, struct __reg_DRTRAM3) +- +-#endif /* __ASSEMBLER__ */ +- +- /* DRTRAM3 */ +- +-#define ENDRT 4 +-#define DRTSWOK 5 +- +-/* Data Retention Configuration Register of SRAM 2 */ +-#define DRTRAM2 _SFR_MEM8(0x133) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_DRTRAM2 { +- unsigned int : 4; +- unsigned int endrt : 1; /* Enable SRAM Data Retention */ +- unsigned int drtswok : 1; /* DRT Switch OK */ +- unsigned int : 2; +-}; +- +-#define DRTRAM2_struct _SFR_MEM8_STRUCT(0x133, struct __reg_DRTRAM2) +- +-#endif /* __ASSEMBLER__ */ +- +- /* DRTRAM2 */ +- +-#define ENDRT 4 +-#define DRTSWOK 5 +- +-/* Data Retention Configuration Register of SRAM 1 */ +-#define DRTRAM1 _SFR_MEM8(0x134) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_DRTRAM1 { +- unsigned int : 4; +- unsigned int endrt : 1; /* Enable SRAM Data Retention */ +- unsigned int drtswok : 1; /* DRT Switch OK */ +- unsigned int : 2; +-}; +- +-#define DRTRAM1_struct _SFR_MEM8_STRUCT(0x134, struct __reg_DRTRAM1) +- +-#endif /* __ASSEMBLER__ */ +- +- /* DRTRAM1 */ +- +-#define ENDRT 4 +-#define DRTSWOK 5 +- +-/* Data Retention Configuration Register of SRAM 0 */ +-#define DRTRAM0 _SFR_MEM8(0x135) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_DRTRAM0 { +- unsigned int : 4; +- unsigned int endrt : 1; /* Enable SRAM Data Retention */ +- unsigned int drtswok : 1; /* DRT Switch OK */ +- unsigned int : 2; +-}; +- +-#define DRTRAM0_struct _SFR_MEM8_STRUCT(0x135, struct __reg_DRTRAM0) +- +-#endif /* __ASSEMBLER__ */ +- +- /* DRTRAM0 */ +- +-#define ENDRT 4 +-#define DRTSWOK 5 +- +-/* Port Driver Strength Register 0 */ +-#define DPDS0 _SFR_MEM8(0x136) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_DPDS0 { +- unsigned int pbdrv : 2; /* Driver Strength Port B */ +- unsigned int pddrv : 2; /* Driver Strength Port D */ +- unsigned int pedrv : 2; /* Driver Strength Port E */ +- unsigned int pfdrv : 2; /* Driver Strength Port F */ +-}; +- +-#define DPDS0_struct _SFR_MEM8_STRUCT(0x136, struct __reg_DPDS0) +- +-#endif /* __ASSEMBLER__ */ +- +- /* DPDS0 */ +- +-#define PBDRV0 0 +-#define PBDRV1 1 +-#define PDDRV0 2 +-#define PDDRV1 3 +-#define PEDRV0 4 +-#define PEDRV1 5 +-#define PFDRV0 6 +-#define PFDRV1 7 +- +-/* Port Driver Strength Register 1 */ +-#define DPDS1 _SFR_MEM8(0x137) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_DPDS1 { +- unsigned int pgdrv : 2; /* Driver Strength Port G */ +- unsigned int : 6; +-}; +- +-#define DPDS1_struct _SFR_MEM8_STRUCT(0x137, struct __reg_DPDS1) +- +-#endif /* __ASSEMBLER__ */ +- +- /* DPDS1 */ +- +-#define PGDRV0 0 +-#define PGDRV1 1 +- +-/* Transceiver Pin Register */ +-#define TRXPR _SFR_MEM8(0x139) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TRXPR { +- unsigned int trxrst : 1; /* Force Transceiver Reset */ +- unsigned int slptr : 1; /* Multi-purpose Transceiver Control Bit */ +- unsigned int : 6; +-}; +- +-#define TRXPR_struct _SFR_MEM8_STRUCT(0x139, struct __reg_TRXPR) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TRXPR */ +- +-#define TRXRST 0 +-#define SLPTR 1 +- +-/* AES Control Register */ +-#define AES_CTRL _SFR_MEM8(0x13C) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_AES_CTRL { +- unsigned int : 2; +- unsigned int aes_im : 1; /* AES Interrupt Enable */ +- unsigned int aes_dir : 1; /* Set AES Operation Direction */ +- unsigned int : 1; +- unsigned int aes_mode : 1; /* Set AES Operation Mode */ +- unsigned int : 1; +- unsigned int aes_request : 1; /* Request AES Operation. */ +-}; +- +-#define AES_CTRL_struct _SFR_MEM8_STRUCT(0x13c, struct __reg_AES_CTRL) +- +-/* symbolic names */ +- +-#define AES_DIR_ENC 0 +-#define AES_DIR_DEC 1 +-#define AES_MODE_ECB 0 +-#define AES_MODE_CBC 1 +- +-#endif /* __ASSEMBLER__ */ +- +- /* AES_CTRL */ +- +-#define AES_IM 2 +-#define AES_DIR 3 +-#define AES_MODE 5 +-#define AES_REQUEST 7 +- +-/* AES Status Register */ +-#define AES_STATUS _SFR_MEM8(0x13D) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_AES_STATUS { +- unsigned int aes_done : 1; /* AES Operation Finished with Success */ +- unsigned int : 6; +- unsigned int aes_er : 1; /* AES Operation Finished with Error */ +-}; +- +-#define AES_STATUS_struct _SFR_MEM8_STRUCT(0x13d, struct __reg_AES_STATUS) +- +-#endif /* __ASSEMBLER__ */ +- +- /* AES_STATUS */ +- +-#define AES_DONE 0 +-#define AES_ER 7 +- +-/* AES Plain and Cipher Text Buffer Register */ +-#define AES_STATE _SFR_MEM8(0x13E) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_AES_STATE { +- unsigned int aes_state : 8; /* AES Plain and Cipher Text Buffer */ +-}; +- +-#define AES_STATE_struct _SFR_MEM8_STRUCT(0x13e, struct __reg_AES_STATE) +- +-#endif /* __ASSEMBLER__ */ +- +- /* AES_STATE */ +- +-#define AES_STATE0 0 +-#define AES_STATE1 1 +-#define AES_STATE2 2 +-#define AES_STATE3 3 +-#define AES_STATE4 4 +-#define AES_STATE5 5 +-#define AES_STATE6 6 +-#define AES_STATE7 7 +- +-/* AES Encryption and Decryption Key Buffer Register */ +-#define AES_KEY _SFR_MEM8(0x13F) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_AES_KEY { +- unsigned int aes_key : 8; /* AES Encryption/Decryption Key Buffer */ +-}; +- +-#define AES_KEY_struct _SFR_MEM8_STRUCT(0x13f, struct __reg_AES_KEY) +- +-#endif /* __ASSEMBLER__ */ +- +- /* AES_KEY */ +- +-#define AES_KEY0 0 +-#define AES_KEY1 1 +-#define AES_KEY2 2 +-#define AES_KEY3 3 +-#define AES_KEY4 4 +-#define AES_KEY5 5 +-#define AES_KEY6 6 +-#define AES_KEY7 7 +- +-/* Transceiver Status Register */ +-#define TRX_STATUS _SFR_MEM8(0x141) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TRX_STATUS { +- unsigned int trx_status : 5; /* Transceiver Main Status */ +- unsigned int tst_status : 1; /* Test mode status */ +- unsigned int cca_status : 1; /* CCA Status Result */ +- unsigned int cca_done : 1; /* CCA Algorithm Status */ +-}; +- +-#define TRX_STATUS_struct _SFR_MEM8_STRUCT(0x141, struct __reg_TRX_STATUS) +- +-/* symbolic names */ +- +-#define P_ON 0 +-#define BUSY_RX 1 +-#define BUSY_TX 2 +-#define RX_ON 6 +-#define TRX_OFF 8 +-#define PLL_ON 9 +-#define SLEEP 15 +-#define BUSY_RX_AACK 17 +-#define BUSY_TX_ARET 18 +-#define RX_AACK_ON 22 +-#define TX_ARET_ON 25 +-#define STATE_TRANSITION_IN_PROGRESS 31 +-#define TST_DISABLED 0 +-#define TST_ENABLED 1 +-#define CCA_BUSY 0 +-#define CCA_IDLE 1 +-#define CCA_NOT_FIN 0 +-#define CCA_FIN 1 +- +-#endif /* __ASSEMBLER__ */ +- +- /* TRX_STATUS */ +- +-#define TRX_STATUS0 0 +-#define TRX_STATUS1 1 +-#define TRX_STATUS2 2 +-#define TRX_STATUS3 3 +-#define TRX_STATUS4 4 +-#define TST_STATUS 5 +-#define CCA_STATUS 6 +-#define CCA_DONE 7 +- +-/* Transceiver State Control Register */ +-#define TRX_STATE _SFR_MEM8(0x142) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TRX_STATE { +- unsigned int trx_cmd : 5; /* State Control Command */ +- unsigned int trac_status : 3; /* Transaction Status */ +-}; +- +-#define TRX_STATE_struct _SFR_MEM8_STRUCT(0x142, struct __reg_TRX_STATE) +- +-/* symbolic names */ +- +-#define CMD_NOP 0 +-#define CMD_TX_START 2 +-#define CMD_FORCE_TRX_OFF 3 +-#define CMD_FORCE_PLL_ON 4 +-#define CMD_RX_ON 6 +-#define CMD_TRX_OFF 8 +-#define CMD_PLL_ON 9 +-#define CMD_RX_AACK_ON 22 +-#define CMD_TX_ARET_ON 25 +-#define TRAC_SUCCESS 0 +-#define TRAC_SUCCESS_DATA_PENDING 1 +-#define TRAC_SUCCESS_WAIT_FOR_ACK 2 +-#define TRAC_CHANNEL_ACCESS_FAILURE 3 +-#define TRAC_NO_ACK 5 +-#define TRAC_INVALID 7 +- +-#endif /* __ASSEMBLER__ */ +- +- /* TRX_STATE */ +- +-#define TRX_CMD0 0 +-#define TRX_CMD1 1 +-#define TRX_CMD2 2 +-#define TRX_CMD3 3 +-#define TRX_CMD4 4 +-#define TRAC_STATUS0 5 +-#define TRAC_STATUS1 6 +-#define TRAC_STATUS2 7 +- +-/* Reserved */ +-#define TRX_CTRL_0 _SFR_MEM8(0x143) +- +-/* Transceiver Control Register 1 */ +-#define TRX_CTRL_1 _SFR_MEM8(0x144) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TRX_CTRL_1 { +- unsigned int : 5; +- unsigned int tx_auto_crc_on : 1; /* Enable Automatic CRC Calculation */ +- unsigned int irq_2_ext_en : 1; /* Connect Frame Start IRQ to TC1 */ +- unsigned int pa_ext_en : 1; /* External PA support enable */ +-}; +- +-#define TRX_CTRL_1_struct _SFR_MEM8_STRUCT(0x144, struct __reg_TRX_CTRL_1) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TRX_CTRL_1 */ +- +-#define TX_AUTO_CRC_ON 5 +-#define IRQ_2_EXT_EN 6 +-#define PA_EXT_EN 7 +- +-/* Transceiver Transmit Power Control Register */ +-#define PHY_TX_PWR _SFR_MEM8(0x145) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_PHY_TX_PWR { +- unsigned int tx_pwr : 4; /* Transmit Power Setting */ +- unsigned int pa_lt : 2; /* Power Amplifier Lead Time */ +- unsigned int pa_buf_lt : 2; /* Power Amplifier Buffer Lead Time */ +-}; +- +-#define PHY_TX_PWR_struct _SFR_MEM8_STRUCT(0x145, struct __reg_PHY_TX_PWR) +- +-/* symbolic names */ +- +-#define PA_LT_2US 0 +-#define PA_LT_4US 1 +-#define PA_LT_6US 2 +-#define PA_LT_8US 3 +-#define PA_BUF_LT_0US 0 +-#define PA_BUF_LT_2US 1 +-#define PA_BUF_LT_4US 2 +-#define PA_BUF_LT_6US 3 +- +-#endif /* __ASSEMBLER__ */ +- +- /* PHY_TX_PWR */ +- +-#define TX_PWR0 0 +-#define TX_PWR1 1 +-#define TX_PWR2 2 +-#define TX_PWR3 3 +-#define PA_LT0 4 +-#define PA_LT1 5 +-#define PA_BUF_LT0 6 +-#define PA_BUF_LT1 7 +- +-/* Receiver Signal Strength Indicator Register */ +-#define PHY_RSSI _SFR_MEM8(0x146) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_PHY_RSSI { +- unsigned int rssi : 5; /* Receiver Signal Strength Indicator */ +- unsigned int rnd_value : 2; /* Random Value */ +- unsigned int rx_crc_valid : 1; /* Received Frame CRC Status */ +-}; +- +-#define PHY_RSSI_struct _SFR_MEM8_STRUCT(0x146, struct __reg_PHY_RSSI) +- +-/* symbolic names */ +- +-#define RSSI_MIN 0 +-#define RSSI_MIN_PLUS_3dB 1 +-#define RSSI_MAX 28 +-#define CRC_INVALID 0 +-#define CRC_VALID 1 +- +-#endif /* __ASSEMBLER__ */ +- +- /* PHY_RSSI */ +- +-#define RSSI0 0 +-#define RSSI1 1 +-#define RSSI2 2 +-#define RSSI3 3 +-#define RSSI4 4 +-#define RND_VALUE0 5 +-#define RND_VALUE1 6 +-#define RX_CRC_VALID 7 +- +-/* Transceiver Energy Detection Level Register */ +-#define PHY_ED_LEVEL _SFR_MEM8(0x147) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_PHY_ED_LEVEL { +- unsigned int ed_level : 8; /* Energy Detection Level */ +-}; +- +-#define PHY_ED_LEVEL_struct _SFR_MEM8_STRUCT(0x147, struct __reg_PHY_ED_LEVEL) +- +-/* symbolic names */ +- +-#define ED_MIN 0 +-#define ED_MIN_PLUS_1dB 1 +-#define ED_MAX 84 +-#define ED_RESET 255 +- +-#endif /* __ASSEMBLER__ */ +- +- /* PHY_ED_LEVEL */ +- +-#define ED_LEVEL0 0 +-#define ED_LEVEL1 1 +-#define ED_LEVEL2 2 +-#define ED_LEVEL3 3 +-#define ED_LEVEL4 4 +-#define ED_LEVEL5 5 +-#define ED_LEVEL6 6 +-#define ED_LEVEL7 7 +- +-/* Transceiver Clear Channel Assessment (CCA) Control Register */ +-#define PHY_CC_CCA _SFR_MEM8(0x148) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_PHY_CC_CCA { +- unsigned int channel : 5; /* RX/TX Channel Selection */ +- unsigned int cca_mode : 2; /* Select CCA Measurement Mode */ +- unsigned int cca_request : 1; /* Manual CCA Measurement Request */ +-}; +- +-#define PHY_CC_CCA_struct _SFR_MEM8_STRUCT(0x148, struct __reg_PHY_CC_CCA) +- +-/* symbolic names */ +- +-#define F_2405MHZ 11 +-#define F_2410MHZ 12 +-#define F_2415MHZ 13 +-#define F_2420MHZ 14 +-#define F_2425MHZ 15 +-#define F_2430MHZ 16 +-#define F_2435MHZ 17 +-#define F_2440MHZ 18 +-#define F_2445MHZ 19 +-#define F_2450MHZ 20 +-#define F_2455MHZ 21 +-#define F_2460MHZ 22 +-#define F_2465MHZ 23 +-#define F_2470MHZ 24 +-#define F_2475MHZ 25 +-#define F_2480MHZ 26 +-#define CCA_CS_OR_ED 0 +-#define CCA_ED 1 +-#define CCA_CS 2 +-#define CCA_CS_AND_ED 3 +- +-#endif /* __ASSEMBLER__ */ +- +- /* PHY_CC_CCA */ +- +-#define CHANNEL0 0 +-#define CHANNEL1 1 +-#define CHANNEL2 2 +-#define CHANNEL3 3 +-#define CHANNEL4 4 +-#define CCA_MODE0 5 +-#define CCA_MODE1 6 +-#define CCA_REQUEST 7 +- +-/* Transceiver CCA Threshold Setting Register */ +-#define CCA_THRES _SFR_MEM8(0x149) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_CCA_THRES { +- unsigned int cca_ed_thres : 4; /* ED Threshold Level for CCA Measurement */ +- unsigned int cca_cs_thres : 4; /* CS Threshold Level for CCA Measurement */ +-}; +- +-#define CCA_THRES_struct _SFR_MEM8_STRUCT(0x149, struct __reg_CCA_THRES) +- +-#endif /* __ASSEMBLER__ */ +- +- /* CCA_THRES */ +- +-#define CCA_ED_THRES0 0 +-#define CCA_ED_THRES1 1 +-#define CCA_ED_THRES2 2 +-#define CCA_ED_THRES3 3 +-#define CCA_CS_THRES0 4 +-#define CCA_CS_THRES1 5 +-#define CCA_CS_THRES2 6 +-#define CCA_CS_THRES3 7 +- +-/* Transceiver Receive Control Register */ +-#define RX_CTRL _SFR_MEM8(0x14A) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_RX_CTRL { +- unsigned int pdt_thres : 4; /* Receiver Sensitivity Control */ +- unsigned int : 4; +-}; +- +-#define RX_CTRL_struct _SFR_MEM8_STRUCT(0x14a, struct __reg_RX_CTRL) +- +-/* symbolic names */ +- +-#define PDT_THRES_ANT_DIV_OFF 7 +-#define PDT_THRES_ANT_DIV_ON 3 +- +-#endif /* __ASSEMBLER__ */ +- +- /* RX_CTRL */ +- +-#define PDT_THRES0 0 +-#define PDT_THRES1 1 +-#define PDT_THRES2 2 +-#define PDT_THRES3 3 +- +-/* Start of Frame Delimiter Value Register */ +-#define SFD_VALUE _SFR_MEM8(0x14B) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SFD_VALUE { +- unsigned int sfd_value : 8; /* Start of Frame Delimiter Value */ +-}; +- +-#define SFD_VALUE_struct _SFR_MEM8_STRUCT(0x14b, struct __reg_SFD_VALUE) +- +-/* symbolic names */ +- +-#define IEEE_SFD 167 +- +-#endif /* __ASSEMBLER__ */ +- +- /* SFD_VALUE */ +- +-#define SFD_VALUE0 0 +-#define SFD_VALUE1 1 +-#define SFD_VALUE2 2 +-#define SFD_VALUE3 3 +-#define SFD_VALUE4 4 +-#define SFD_VALUE5 5 +-#define SFD_VALUE6 6 +-#define SFD_VALUE7 7 +- +-/* Transceiver Control Register 2 */ +-#define TRX_CTRL_2 _SFR_MEM8(0x14C) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TRX_CTRL_2 { +- unsigned int oqpsk_data_rate : 2; /* Data Rate Selection */ +- unsigned int : 5; +- unsigned int rx_safe_mode : 1; /* RX Safe Mode */ +-}; +- +-#define TRX_CTRL_2_struct _SFR_MEM8_STRUCT(0x14c, struct __reg_TRX_CTRL_2) +- +-/* symbolic names */ +- +-#define RATE_250KB 0 +-#define RATE_500KB 1 +-#define RATE_1000KB 2 +-#define RATE_2000KB 3 +- +-#endif /* __ASSEMBLER__ */ +- +- /* TRX_CTRL_2 */ +- +-#define OQPSK_DATA_RATE0 0 +-#define OQPSK_DATA_RATE1 1 +-#define RX_SAFE_MODE 7 +- +-/* Antenna Diversity Control Register */ +-#define ANT_DIV _SFR_MEM8(0x14D) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_ANT_DIV { +- unsigned int ant_ctrl : 2; /* Static Antenna Diversity Switch Control */ +- unsigned int ant_ext_sw_en : 1; /* Enable External Antenna Switch Control */ +- unsigned int ant_div_en : 1; /* Enable Antenna Diversity */ +- unsigned int : 3; +- unsigned int ant_sel : 1; /* Antenna Diversity Antenna Status */ +-}; +- +-#define ANT_DIV_struct _SFR_MEM8_STRUCT(0x14d, struct __reg_ANT_DIV) +- +-/* symbolic names */ +- +-#define ANT_1 1 +-#define ANT_0 2 +-#define ANT_RESET 3 +-#define ANT_DIV_EXT_SW_DIS 0 +-#define ANT_DIV_EXT_SW_EN 1 +-#define ANTENNA_0 0 +-#define ANTENNA_1 1 +- +-#endif /* __ASSEMBLER__ */ +- +- /* ANT_DIV */ +- +-#define ANT_CTRL0 0 +-#define ANT_CTRL1 1 +-#define ANT_EXT_SW_EN 2 +-#define ANT_DIV_EN 3 +-#define ANT_SEL 7 +- +-/* Transceiver Interrupt Enable Register */ +-#define IRQ_MASK _SFR_MEM8(0x14E) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_IRQ_MASK { +- unsigned int pll_lock_en : 1; /* PLL Lock Interrupt Enable */ +- unsigned int pll_unlock_en : 1; /* PLL Unlock Interrupt Enable */ +- unsigned int rx_start_en : 1; /* RX_START Interrupt Enable */ +- unsigned int rx_end_en : 1; /* RX_END Interrupt Enable */ +- unsigned int cca_ed_done_en : 1; /* End of ED Measurement Interrupt Enable */ +- unsigned int ami_en : 1; /* Address Match Interrupt Enable */ +- unsigned int tx_end_en : 1; /* TX_END Interrupt Enable */ +- unsigned int awake_en : 1; /* Awake Interrupt Enable */ +-}; +- +-#define IRQ_MASK_struct _SFR_MEM8_STRUCT(0x14e, struct __reg_IRQ_MASK) +- +-#endif /* __ASSEMBLER__ */ +- +- /* IRQ_MASK */ +- +-#define PLL_LOCK_EN 0 +-#define PLL_UNLOCK_EN 1 +-#define RX_START_EN 2 +-#define RX_END_EN 3 +-#define CCA_ED_DONE_EN 4 +-#define AMI_EN 5 +-#define TX_END_EN 6 +-#define AWAKE_EN 7 +- +-/* Transceiver Interrupt Status Register */ +-#define IRQ_STATUS _SFR_MEM8(0x14F) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_IRQ_STATUS { +- unsigned int pll_lock : 1; /* PLL Lock Interrupt Status */ +- unsigned int pll_unlock : 1; /* PLL Unlock Interrupt Status */ +- unsigned int rx_start : 1; /* RX_START Interrupt Status */ +- unsigned int rx_end : 1; /* RX_END Interrupt Status */ +- unsigned int cca_ed_done : 1; /* End of ED Measurement Interrupt Status */ +- unsigned int ami : 1; /* Address Match Interrupt Status */ +- unsigned int tx_end : 1; /* TX_END Interrupt Status */ +- unsigned int awake : 1; /* Awake Interrupt Status */ +-}; +- +-#define IRQ_STATUS_struct _SFR_MEM8_STRUCT(0x14f, struct __reg_IRQ_STATUS) +- +-#endif /* __ASSEMBLER__ */ +- +- /* IRQ_STATUS */ +- +-#define PLL_LOCK 0 +-#define PLL_UNLOCK 1 +-#define RX_START 2 +-#define RX_END 3 +-#define CCA_ED_DONE 4 +-#define AMI 5 +-#define TX_END 6 +-#define AWAKE 7 +- +-/* Voltage Regulator Control and Status Register */ +-#define VREG_CTRL _SFR_MEM8(0x150) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_VREG_CTRL { +- unsigned int : 2; +- unsigned int dvdd_ok : 1; /* DVDD Supply Voltage Valid */ +- unsigned int dvreg_ext : 1; /* Use External DVDD Regulator */ +- unsigned int : 2; +- unsigned int avdd_ok : 1; /* AVDD Supply Voltage Valid */ +- unsigned int avreg_ext : 1; /* Use External AVDD Regulator */ +-}; +- +-#define VREG_CTRL_struct _SFR_MEM8_STRUCT(0x150, struct __reg_VREG_CTRL) +- +-/* symbolic names */ +- +-#define DVDD_INT 0 +-#define DVDD_EXT 1 +-#define AVDD_INT 0 +-#define AVDD_EXT 1 +- +-#endif /* __ASSEMBLER__ */ +- +- /* VREG_CTRL */ +- +-#define DVDD_OK 2 +-#define DVREG_EXT 3 +-#define AVDD_OK 6 +-#define AVREG_EXT 7 +- +-/* Battery Monitor Control and Status Register */ +-#define BATMON _SFR_MEM8(0x151) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_BATMON { +- unsigned int batmon_vth : 4; /* Battery Monitor Threshold Voltage */ +- unsigned int batmon_hr : 1; /* Battery Monitor Voltage Range */ +- unsigned int batmon_ok : 1; /* Battery Monitor Status */ +- unsigned int bat_low_en : 1; /* Battery Monitor Interrupt Enable */ +- unsigned int bat_low : 1; /* Battery Monitor Interrupt Status */ +-}; +- +-#define BATMON_struct _SFR_MEM8_STRUCT(0x151, struct __reg_BATMON) +- +-/* symbolic names */ +- +-#define BATMON_HR_DIS 0 +-#define BATMON_HR_EN 1 +- +-#endif /* __ASSEMBLER__ */ +- +- /* BATMON */ +- +-#define BATMON_VTH0 0 +-#define BATMON_VTH1 1 +-#define BATMON_VTH2 2 +-#define BATMON_VTH3 3 +-#define BATMON_HR 4 +-#define BATMON_OK 5 +-#define BAT_LOW_EN 6 +-#define BAT_LOW 7 +- +-/* Crystal Oscillator Control Register */ +-#define XOSC_CTRL _SFR_MEM8(0x152) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_XOSC_CTRL { +- unsigned int xtal_trim : 4; /* Crystal Oscillator Load Capacitance Trimming */ +- unsigned int xtal_mode : 4; /* Crystal Oscillator Operating Mode */ +-}; +- +-#define XOSC_CTRL_struct _SFR_MEM8_STRUCT(0x152, struct __reg_XOSC_CTRL) +- +-/* symbolic names */ +- +-#define XTAL_TRIM_MIN 0 +-#define XTAL_TRIM_MAX 15 +- +-#endif /* __ASSEMBLER__ */ +- +- /* XOSC_CTRL */ +- +-#define XTAL_TRIM0 0 +-#define XTAL_TRIM1 1 +-#define XTAL_TRIM2 2 +-#define XTAL_TRIM3 3 +-#define XTAL_MODE0 4 +-#define XTAL_MODE1 5 +-#define XTAL_MODE2 6 +-#define XTAL_MODE3 7 +- +-/* Transceiver Receiver Sensitivity Control Register */ +-#define RX_SYN _SFR_MEM8(0x155) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_RX_SYN { +- unsigned int rx_pdt_level : 4; /* Reduce Receiver Sensitivity */ +- unsigned int : 3; +- unsigned int rx_pdt_dis : 1; /* Prevent Frame Reception */ +-}; +- +-#define RX_SYN_struct _SFR_MEM8_STRUCT(0x155, struct __reg_RX_SYN) +- +-/* symbolic names */ +- +-#define RX_PDT_LEVEL_MIN 0 +-#define RX_PDT_LEVEL_MAX 15 +- +-#endif /* __ASSEMBLER__ */ +- +- /* RX_SYN */ +- +-#define RX_PDT_LEVEL0 0 +-#define RX_PDT_LEVEL1 1 +-#define RX_PDT_LEVEL2 2 +-#define RX_PDT_LEVEL3 3 +-#define RX_PDT_DIS 7 +- +-/* Transceiver Acknowledgment Frame Control Register 1 */ +-#define XAH_CTRL_1 _SFR_MEM8(0x157) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_XAH_CTRL_1 { +- unsigned int : 1; +- unsigned int aack_prom_mode : 1; /* Enable Promiscuous Mode */ +- unsigned int aack_ack_time : 1; /* Reduce Acknowledgment Time */ +- unsigned int : 1; +- unsigned int aack_upld_res_ft : 1; /* Process Reserved Frames */ +- unsigned int aack_fltr_res_ft : 1; /* Filter Reserved Frames */ +- unsigned int : 2; +-}; +- +-#define XAH_CTRL_1_struct _SFR_MEM8_STRUCT(0x157, struct __reg_XAH_CTRL_1) +- +-/* symbolic names */ +- +-#define AACK_ACK_TIME_12_SYM 0 +-#define AACK_ACK_TIME_2_SYM 1 +- +-#endif /* __ASSEMBLER__ */ +- +- /* XAH_CTRL_1 */ +- +-#define AACK_PROM_MODE 1 +-#define AACK_ACK_TIME 2 +-#define AACK_UPLD_RES_FT 4 +-#define AACK_FLTR_RES_FT 5 +- +-/* Transceiver Filter Tuning Control Register */ +-#define FTN_CTRL _SFR_MEM8(0x158) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_FTN_CTRL { +- unsigned int : 7; +- unsigned int ftn_start : 1; /* Start Calibration Loop of Filter Tuning Network */ +-}; +- +-#define FTN_CTRL_struct _SFR_MEM8_STRUCT(0x158, struct __reg_FTN_CTRL) +- +-#endif /* __ASSEMBLER__ */ +- +- /* FTN_CTRL */ +- +-#define FTN_START 7 +- +-/* Transceiver Center Frequency Calibration Control Register */ +-#define PLL_CF _SFR_MEM8(0x15A) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_PLL_CF { +- unsigned int : 7; +- unsigned int pll_cf_start : 1; /* Start Center Frequency Calibration */ +-}; +- +-#define PLL_CF_struct _SFR_MEM8_STRUCT(0x15a, struct __reg_PLL_CF) +- +-#endif /* __ASSEMBLER__ */ +- +- /* PLL_CF */ +- +-#define PLL_CF_START 7 +- +-/* Transceiver Delay Cell Calibration Control Register */ +-#define PLL_DCU _SFR_MEM8(0x15B) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_PLL_DCU { +- unsigned int : 7; +- unsigned int pll_dcu_start : 1; /* Start Delay Cell Calibration */ +-}; +- +-#define PLL_DCU_struct _SFR_MEM8_STRUCT(0x15b, struct __reg_PLL_DCU) +- +-#endif /* __ASSEMBLER__ */ +- +- /* PLL_DCU */ +- +-#define PLL_DCU_START 7 +- +-/* Device Identification Register (Part Number) */ +-#define PART_NUM _SFR_MEM8(0x15C) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_PART_NUM { +- unsigned int part_num : 8; /* Part Number */ +-}; +- +-#define PART_NUM_struct _SFR_MEM8_STRUCT(0x15c, struct __reg_PART_NUM) +- +-/* symbolic names */ +- +-#define P_ATmega128RFA1 131 +- +-#endif /* __ASSEMBLER__ */ +- +- /* PART_NUM */ +- +-#define PART_NUM0 0 +-#define PART_NUM1 1 +-#define PART_NUM2 2 +-#define PART_NUM3 3 +-#define PART_NUM4 4 +-#define PART_NUM5 5 +-#define PART_NUM6 6 +-#define PART_NUM7 7 +- +-/* Device Identification Register (Version Number) */ +-#define VERSION_NUM _SFR_MEM8(0x15D) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_VERSION_NUM { +- unsigned int version_num : 8; /* Version Number */ +-}; +- +-#define VERSION_NUM_struct _SFR_MEM8_STRUCT(0x15d, struct __reg_VERSION_NUM) +- +-/* symbolic names */ +- +-#define REV_A 2 +-#define REV_B 3 +- +-#endif /* __ASSEMBLER__ */ +- +- /* VERSION_NUM */ +- +-#define VERSION_NUM0 0 +-#define VERSION_NUM1 1 +-#define VERSION_NUM2 2 +-#define VERSION_NUM3 3 +-#define VERSION_NUM4 4 +-#define VERSION_NUM5 5 +-#define VERSION_NUM6 6 +-#define VERSION_NUM7 7 +- +-/* Device Identification Register (Manufacture ID Low Byte) */ +-#define MAN_ID_0 _SFR_MEM8(0x15E) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_MAN_ID_0 { +- unsigned int man_id_0 : 8; /* Manufacturer ID (Low Byte) */ +-}; +- +-#define MAN_ID_0_struct _SFR_MEM8_STRUCT(0x15e, struct __reg_MAN_ID_0) +- +-/* symbolic names */ +- +-#define ATMEL_BYTE_0 31 +- +-#endif /* __ASSEMBLER__ */ +- +- /* MAN_ID_0 */ +- +-#define MAN_ID_00 0 +-#define MAN_ID_01 1 +-#define MAN_ID_02 2 +-#define MAN_ID_03 3 +-#define MAN_ID_04 4 +-#define MAN_ID_05 5 +-#define MAN_ID_06 6 +-#define MAN_ID_07 7 +- +-/* Device Identification Register (Manufacture ID High Byte) */ +-#define MAN_ID_1 _SFR_MEM8(0x15F) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_MAN_ID_1 { +- unsigned int man_id_1 : 8; /* Manufacturer ID (High Byte) */ +-}; +- +-#define MAN_ID_1_struct _SFR_MEM8_STRUCT(0x15f, struct __reg_MAN_ID_1) +- +-/* symbolic names */ +- +-#define ATMEL_BYTE_1 0 +- +-#endif /* __ASSEMBLER__ */ +- +- /* MAN_ID_1 */ +- +-#define MAN_ID_10 0 +-#define MAN_ID_11 1 +-#define MAN_ID_12 2 +-#define MAN_ID_13 3 +-#define MAN_ID_14 4 +-#define MAN_ID_15 5 +-#define MAN_ID_16 6 +-#define MAN_ID_17 7 +- +-/* Transceiver MAC Short Address Register (Low Byte) */ +-#define SHORT_ADDR_0 _SFR_MEM8(0x160) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SHORT_ADDR_0 { +- unsigned int short_addr_0 : 8; /* MAC Short Address */ +-}; +- +-#define SHORT_ADDR_0_struct _SFR_MEM8_STRUCT(0x160, struct __reg_SHORT_ADDR_0) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SHORT_ADDR_0 */ +- +-#define SHORT_ADDR_00 0 +-#define SHORT_ADDR_01 1 +-#define SHORT_ADDR_02 2 +-#define SHORT_ADDR_03 3 +-#define SHORT_ADDR_04 4 +-#define SHORT_ADDR_05 5 +-#define SHORT_ADDR_06 6 +-#define SHORT_ADDR_07 7 +- +-/* Transceiver MAC Short Address Register (High Byte) */ +-#define SHORT_ADDR_1 _SFR_MEM8(0x161) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_SHORT_ADDR_1 { +- unsigned int short_addr_1 : 8; /* MAC Short Address */ +-}; +- +-#define SHORT_ADDR_1_struct _SFR_MEM8_STRUCT(0x161, struct __reg_SHORT_ADDR_1) +- +-#endif /* __ASSEMBLER__ */ +- +- /* SHORT_ADDR_1 */ +- +-#define SHORT_ADDR_10 0 +-#define SHORT_ADDR_11 1 +-#define SHORT_ADDR_12 2 +-#define SHORT_ADDR_13 3 +-#define SHORT_ADDR_14 4 +-#define SHORT_ADDR_15 5 +-#define SHORT_ADDR_16 6 +-#define SHORT_ADDR_17 7 +- +-/* Transceiver Personal Area Network ID Register (Low Byte) */ +-#define PAN_ID_0 _SFR_MEM8(0x162) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_PAN_ID_0 { +- unsigned int pan_id_0 : 8; /* MAC Personal Area Network ID */ +-}; +- +-#define PAN_ID_0_struct _SFR_MEM8_STRUCT(0x162, struct __reg_PAN_ID_0) +- +-#endif /* __ASSEMBLER__ */ +- +- /* PAN_ID_0 */ +- +-#define PAN_ID_00 0 +-#define PAN_ID_01 1 +-#define PAN_ID_02 2 +-#define PAN_ID_03 3 +-#define PAN_ID_04 4 +-#define PAN_ID_05 5 +-#define PAN_ID_06 6 +-#define PAN_ID_07 7 +- +-/* Transceiver Personal Area Network ID Register (High Byte) */ +-#define PAN_ID_1 _SFR_MEM8(0x163) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_PAN_ID_1 { +- unsigned int pan_id_1 : 8; /* MAC Personal Area Network ID */ +-}; +- +-#define PAN_ID_1_struct _SFR_MEM8_STRUCT(0x163, struct __reg_PAN_ID_1) +- +-#endif /* __ASSEMBLER__ */ +- +- /* PAN_ID_1 */ +- +-#define PAN_ID_10 0 +-#define PAN_ID_11 1 +-#define PAN_ID_12 2 +-#define PAN_ID_13 3 +-#define PAN_ID_14 4 +-#define PAN_ID_15 5 +-#define PAN_ID_16 6 +-#define PAN_ID_17 7 +- +-/* Transceiver MAC IEEE Address Register 0 */ +-#define IEEE_ADDR_0 _SFR_MEM8(0x164) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_IEEE_ADDR_0 { +- unsigned int ieee_addr_0 : 8; /* MAC IEEE Address */ +-}; +- +-#define IEEE_ADDR_0_struct _SFR_MEM8_STRUCT(0x164, struct __reg_IEEE_ADDR_0) +- +-#endif /* __ASSEMBLER__ */ +- +- /* IEEE_ADDR_0 */ +- +-#define IEEE_ADDR_00 0 +-#define IEEE_ADDR_01 1 +-#define IEEE_ADDR_02 2 +-#define IEEE_ADDR_03 3 +-#define IEEE_ADDR_04 4 +-#define IEEE_ADDR_05 5 +-#define IEEE_ADDR_06 6 +-#define IEEE_ADDR_07 7 +- +-/* Transceiver MAC IEEE Address Register 1 */ +-#define IEEE_ADDR_1 _SFR_MEM8(0x165) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_IEEE_ADDR_1 { +- unsigned int ieee_addr_1 : 8; /* MAC IEEE Address */ +-}; +- +-#define IEEE_ADDR_1_struct _SFR_MEM8_STRUCT(0x165, struct __reg_IEEE_ADDR_1) +- +-#endif /* __ASSEMBLER__ */ +- +- /* IEEE_ADDR_1 */ +- +-#define IEEE_ADDR_10 0 +-#define IEEE_ADDR_11 1 +-#define IEEE_ADDR_12 2 +-#define IEEE_ADDR_13 3 +-#define IEEE_ADDR_14 4 +-#define IEEE_ADDR_15 5 +-#define IEEE_ADDR_16 6 +-#define IEEE_ADDR_17 7 +- +-/* Transceiver MAC IEEE Address Register 2 */ +-#define IEEE_ADDR_2 _SFR_MEM8(0x166) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_IEEE_ADDR_2 { +- unsigned int ieee_addr_2 : 8; /* MAC IEEE Address */ +-}; +- +-#define IEEE_ADDR_2_struct _SFR_MEM8_STRUCT(0x166, struct __reg_IEEE_ADDR_2) +- +-#endif /* __ASSEMBLER__ */ +- +- /* IEEE_ADDR_2 */ +- +-#define IEEE_ADDR_20 0 +-#define IEEE_ADDR_21 1 +-#define IEEE_ADDR_22 2 +-#define IEEE_ADDR_23 3 +-#define IEEE_ADDR_24 4 +-#define IEEE_ADDR_25 5 +-#define IEEE_ADDR_26 6 +-#define IEEE_ADDR_27 7 +- +-/* Transceiver MAC IEEE Address Register 3 */ +-#define IEEE_ADDR_3 _SFR_MEM8(0x167) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_IEEE_ADDR_3 { +- unsigned int ieee_addr_3 : 8; /* MAC IEEE Address */ +-}; +- +-#define IEEE_ADDR_3_struct _SFR_MEM8_STRUCT(0x167, struct __reg_IEEE_ADDR_3) +- +-#endif /* __ASSEMBLER__ */ +- +- /* IEEE_ADDR_3 */ +- +-#define IEEE_ADDR_30 0 +-#define IEEE_ADDR_31 1 +-#define IEEE_ADDR_32 2 +-#define IEEE_ADDR_33 3 +-#define IEEE_ADDR_34 4 +-#define IEEE_ADDR_35 5 +-#define IEEE_ADDR_36 6 +-#define IEEE_ADDR_37 7 +- +-/* Transceiver MAC IEEE Address Register 4 */ +-#define IEEE_ADDR_4 _SFR_MEM8(0x168) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_IEEE_ADDR_4 { +- unsigned int ieee_addr_4 : 8; /* MAC IEEE Address */ +-}; +- +-#define IEEE_ADDR_4_struct _SFR_MEM8_STRUCT(0x168, struct __reg_IEEE_ADDR_4) +- +-#endif /* __ASSEMBLER__ */ +- +- /* IEEE_ADDR_4 */ +- +-#define IEEE_ADDR_40 0 +-#define IEEE_ADDR_41 1 +-#define IEEE_ADDR_42 2 +-#define IEEE_ADDR_43 3 +-#define IEEE_ADDR_44 4 +-#define IEEE_ADDR_45 5 +-#define IEEE_ADDR_46 6 +-#define IEEE_ADDR_47 7 +- +-/* Transceiver MAC IEEE Address Register 5 */ +-#define IEEE_ADDR_5 _SFR_MEM8(0x169) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_IEEE_ADDR_5 { +- unsigned int ieee_addr_5 : 8; /* MAC IEEE Address */ +-}; +- +-#define IEEE_ADDR_5_struct _SFR_MEM8_STRUCT(0x169, struct __reg_IEEE_ADDR_5) +- +-#endif /* __ASSEMBLER__ */ +- +- /* IEEE_ADDR_5 */ +- +-#define IEEE_ADDR_50 0 +-#define IEEE_ADDR_51 1 +-#define IEEE_ADDR_52 2 +-#define IEEE_ADDR_53 3 +-#define IEEE_ADDR_54 4 +-#define IEEE_ADDR_55 5 +-#define IEEE_ADDR_56 6 +-#define IEEE_ADDR_57 7 +- +-/* Transceiver MAC IEEE Address Register 6 */ +-#define IEEE_ADDR_6 _SFR_MEM8(0x16A) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_IEEE_ADDR_6 { +- unsigned int ieee_addr_6 : 8; /* MAC IEEE Address */ +-}; +- +-#define IEEE_ADDR_6_struct _SFR_MEM8_STRUCT(0x16a, struct __reg_IEEE_ADDR_6) +- +-#endif /* __ASSEMBLER__ */ +- +- /* IEEE_ADDR_6 */ +- +-#define IEEE_ADDR_60 0 +-#define IEEE_ADDR_61 1 +-#define IEEE_ADDR_62 2 +-#define IEEE_ADDR_63 3 +-#define IEEE_ADDR_64 4 +-#define IEEE_ADDR_65 5 +-#define IEEE_ADDR_66 6 +-#define IEEE_ADDR_67 7 +- +-/* Transceiver MAC IEEE Address Register 7 */ +-#define IEEE_ADDR_7 _SFR_MEM8(0x16B) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_IEEE_ADDR_7 { +- unsigned int ieee_addr_7 : 8; /* MAC IEEE Address */ +-}; +- +-#define IEEE_ADDR_7_struct _SFR_MEM8_STRUCT(0x16b, struct __reg_IEEE_ADDR_7) +- +-#endif /* __ASSEMBLER__ */ +- +- /* IEEE_ADDR_7 */ +- +-#define IEEE_ADDR_70 0 +-#define IEEE_ADDR_71 1 +-#define IEEE_ADDR_72 2 +-#define IEEE_ADDR_73 3 +-#define IEEE_ADDR_74 4 +-#define IEEE_ADDR_75 5 +-#define IEEE_ADDR_76 6 +-#define IEEE_ADDR_77 7 +- +-/* Transceiver Extended Operating Mode Control Register */ +-#define XAH_CTRL_0 _SFR_MEM8(0x16C) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_XAH_CTRL_0 { +- unsigned int slotted_operation : 1; /* Set Slotted Acknowledgment */ +- unsigned int max_csma_retries : 3; /* Maximum Number of CSMA-CA Procedure Repetition Attempts */ +- unsigned int max_frame_retries : 4; /* Maximum Number of Frame Re-transmission Attempts */ +-}; +- +-#define XAH_CTRL_0_struct _SFR_MEM8_STRUCT(0x16c, struct __reg_XAH_CTRL_0) +- +-/* symbolic names */ +- +-#define SLOTTED_OP_DIS 0 +-#define SLOTTED_OP_EN 1 +- +-#endif /* __ASSEMBLER__ */ +- +- /* XAH_CTRL_0 */ +- +-#define SLOTTED_OPERATION 0 +-#define MAX_CSMA_RETRIES0 1 +-#define MAX_CSMA_RETRIES1 2 +-#define MAX_CSMA_RETRIES2 3 +-#define MAX_FRAME_RETRIES0 4 +-#define MAX_FRAME_RETRIES1 5 +-#define MAX_FRAME_RETRIES2 6 +-#define MAX_FRAME_RETRIES3 7 +- +-/* Transceiver CSMA-CA Random Number Generator Seed Register */ +-#define CSMA_SEED_0 _SFR_MEM8(0x16D) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_CSMA_SEED_0 { +- unsigned int csma_seed_0 : 8; /* Seed Value for CSMA Random Number Generator */ +-}; +- +-#define CSMA_SEED_0_struct _SFR_MEM8_STRUCT(0x16d, struct __reg_CSMA_SEED_0) +- +-#endif /* __ASSEMBLER__ */ +- +- /* CSMA_SEED_0 */ +- +-#define CSMA_SEED_00 0 +-#define CSMA_SEED_01 1 +-#define CSMA_SEED_02 2 +-#define CSMA_SEED_03 3 +-#define CSMA_SEED_04 4 +-#define CSMA_SEED_05 5 +-#define CSMA_SEED_06 6 +-#define CSMA_SEED_07 7 +- +-/* Transceiver Acknowledgment Frame Control Register 2 */ +-#define CSMA_SEED_1 _SFR_MEM8(0x16E) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_CSMA_SEED_1 { +- unsigned int csma_seed_1 : 3; /* Seed Value for CSMA Random Number Generator */ +- unsigned int aack_i_am_coord : 1; /* Set Personal Area Network Coordinator */ +- unsigned int aack_dis_ack : 1; /* Disable Acknowledgment Frame Transmission */ +- unsigned int aack_set_pd : 1; /* Set Frame Pending Sub-field */ +- unsigned int aack_fvn_mode : 2; /* Acknowledgment Frame Filter Mode */ +-}; +- +-#define CSMA_SEED_1_struct _SFR_MEM8_STRUCT(0x16e, struct __reg_CSMA_SEED_1) +- +-#endif /* __ASSEMBLER__ */ +- +- /* CSMA_SEED_1 */ +- +-#define CSMA_SEED_10 0 +-#define CSMA_SEED_11 1 +-#define CSMA_SEED_12 2 +-#define AACK_I_AM_COORD 3 +-#define AACK_DIS_ACK 4 +-#define AACK_SET_PD 5 +-#define AACK_FVN_MODE0 6 +-#define AACK_FVN_MODE1 7 +- +-/* Transceiver CSMA-CA Back-off Exponent Control Register */ +-#define CSMA_BE _SFR_MEM8(0x16F) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_CSMA_BE { +- unsigned int min_be : 4; /* Minimum Back-off Exponent */ +- unsigned int max_be : 4; /* Maximum Back-off Exponent */ +-}; +- +-#define CSMA_BE_struct _SFR_MEM8_STRUCT(0x16f, struct __reg_CSMA_BE) +- +-#endif /* __ASSEMBLER__ */ +- +- /* CSMA_BE */ +- +-#define MIN_BE0 0 +-#define MIN_BE1 1 +-#define MIN_BE2 2 +-#define MIN_BE3 3 +-#define MAX_BE0 4 +-#define MAX_BE1 5 +-#define MAX_BE2 6 +-#define MAX_BE3 7 +- +-/* Transceiver Digital Test Control Register */ +-#define TST_CTRL_DIGI _SFR_MEM8(0x176) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TST_CTRL_DIGI { +- unsigned int tst_ctrl_dig : 4; /* Digital Test Controller Register */ +- unsigned int : 4; +-}; +- +-#define TST_CTRL_DIGI_struct _SFR_MEM8_STRUCT(0x176, struct __reg_TST_CTRL_DIGI) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TST_CTRL_DIGI */ +- +-#define TST_CTRL_DIG0 0 +-#define TST_CTRL_DIG1 1 +-#define TST_CTRL_DIG2 2 +-#define TST_CTRL_DIG3 3 +- +-/* Transceiver Received Frame Length Register */ +-#define TST_RX_LENGTH _SFR_MEM8(0x17B) +- +-#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) +- +-struct __reg_TST_RX_LENGTH { +- unsigned int rx_length : 8; /* Received Frame Length */ +-}; +- +-#define TST_RX_LENGTH_struct _SFR_MEM8_STRUCT(0x17b, struct __reg_TST_RX_LENGTH) +- +-#endif /* __ASSEMBLER__ */ +- +- /* TST_RX_LENGTH */ +- +-#define RX_LENGTH0 0 +-#define RX_LENGTH1 1 +-#define RX_LENGTH2 2 +-#define RX_LENGTH3 3 +-#define RX_LENGTH4 4 +-#define RX_LENGTH5 5 +-#define RX_LENGTH6 6 +-#define RX_LENGTH7 7 +- +-/* Start of frame buffer */ +-#define TRXFBST _SFR_MEM8(0x180) +- +- /* TRXFBST */ +- +-#define TRXFBST0 0 +-#define TRXFBST1 1 +-#define TRXFBST2 2 +-#define TRXFBST3 3 +-#define TRXFBST4 4 +-#define TRXFBST5 5 +-#define TRXFBST6 6 +-#define TRXFBST7 7 +- +-/* End of frame buffer */ +-#define TRXFBEND _SFR_MEM8(0x1FF) +- +- /* TRXFBEND */ +- +-#define TRXFBEND0 0 +-#define TRXFBEND1 1 +-#define TRXFBEND2 2 +-#define TRXFBEND3 3 +-#define TRXFBEND4 4 +-#define TRXFBEND5 5 +-#define TRXFBEND6 6 +-#define TRXFBEND7 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +- +-#define _VECTORS_SIZE 288 +- +-/* External Interrupt Request 0 */ +-#define INT0_vect _VECTOR(1) +-#define INT0_vect_num 1 +- +-/* External Interrupt Request 1 */ +-#define INT1_vect _VECTOR(2) +-#define INT1_vect_num 2 +- +-/* External Interrupt Request 2 */ +-#define INT2_vect _VECTOR(3) +-#define INT2_vect_num 3 +- +-/* External Interrupt Request 3 */ +-#define INT3_vect _VECTOR(4) +-#define INT3_vect_num 4 +- +-/* External Interrupt Request 4 */ +-#define INT4_vect _VECTOR(5) +-#define INT4_vect_num 5 +- +-/* External Interrupt Request 5 */ +-#define INT5_vect _VECTOR(6) +-#define INT5_vect_num 6 +- +-/* External Interrupt Request 6 */ +-#define INT6_vect _VECTOR(7) +-#define INT6_vect_num 7 +- +-/* External Interrupt Request 7 */ +-#define INT7_vect _VECTOR(8) +-#define INT7_vect_num 8 +- +-/* Pin Change Interrupt Request 0 */ +-#define PCINT0_vect _VECTOR(9) +-#define PCINT0_vect_num 9 +- +-/* Pin Change Interrupt Request 1 */ +-#define PCINT1_vect _VECTOR(10) +-#define PCINT1_vect_num 10 +- +-/* Pin Change Interrupt Request 2 */ +-#define PCINT2_vect _VECTOR(11) +-#define PCINT2_vect_num 11 +- +-/* Watchdog Time-out Interrupt */ +-#define WDT_vect _VECTOR(12) +-#define WDT_vect_num 12 +- +-/* Timer/Counter2 Compare Match A */ +-#define TIMER2_COMPA_vect _VECTOR(13) +-#define TIMER2_COMPA_vect_num 13 +- +-/* Timer/Counter2 Compare Match B */ +-#define TIMER2_COMPB_vect _VECTOR(14) +-#define TIMER2_COMPB_vect_num 14 +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect _VECTOR(15) +-#define TIMER2_OVF_vect_num 15 +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect _VECTOR(16) +-#define TIMER1_CAPT_vect_num 16 +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect _VECTOR(17) +-#define TIMER1_COMPA_vect_num 17 +- +-/* Timer/Counter1 Compare Match B */ +-#define TIMER1_COMPB_vect _VECTOR(18) +-#define TIMER1_COMPB_vect_num 18 +- +-/* Timer/Counter1 Compare Match C */ +-#define TIMER1_COMPC_vect _VECTOR(19) +-#define TIMER1_COMPC_vect_num 19 +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect _VECTOR(20) +-#define TIMER1_OVF_vect_num 20 +- +-/* Timer/Counter0 Compare Match A */ +-#define TIMER0_COMPA_vect _VECTOR(21) +-#define TIMER0_COMPA_vect_num 21 +- +-/* Timer/Counter0 Compare Match B */ +-#define TIMER0_COMPB_vect _VECTOR(22) +-#define TIMER0_COMPB_vect_num 22 +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect _VECTOR(23) +-#define TIMER0_OVF_vect_num 23 +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect _VECTOR(24) +-#define SPI_STC_vect_num 24 +- +-/* USART0, Rx Complete */ +-#define USART0_RX_vect _VECTOR(25) +-#define USART0_RX_vect_num 25 +- +-/* USART0 Data register Empty */ +-#define USART0_UDRE_vect _VECTOR(26) +-#define USART0_UDRE_vect_num 26 +- +-/* USART0, Tx Complete */ +-#define USART0_TX_vect _VECTOR(27) +-#define USART0_TX_vect_num 27 +- +-/* Analog Comparator */ +-#define ANALOG_COMP_vect _VECTOR(28) +-#define ANALOG_COMP_vect_num 28 +- +-/* ADC Conversion Complete */ +-#define ADC_vect _VECTOR(29) +-#define ADC_vect_num 29 +- +-/* EEPROM Ready */ +-#define EE_READY_vect _VECTOR(30) +-#define EE_READY_vect_num 30 +- +-/* Timer/Counter3 Capture Event */ +-#define TIMER3_CAPT_vect _VECTOR(31) +-#define TIMER3_CAPT_vect_num 31 +- +-/* Timer/Counter3 Compare Match A */ +-#define TIMER3_COMPA_vect _VECTOR(32) +-#define TIMER3_COMPA_vect_num 32 +- +-/* Timer/Counter3 Compare Match B */ +-#define TIMER3_COMPB_vect _VECTOR(33) +-#define TIMER3_COMPB_vect_num 33 +- +-/* Timer/Counter3 Compare Match C */ +-#define TIMER3_COMPC_vect _VECTOR(34) +-#define TIMER3_COMPC_vect_num 34 +- +-/* Timer/Counter3 Overflow */ +-#define TIMER3_OVF_vect _VECTOR(35) +-#define TIMER3_OVF_vect_num 35 +- +-/* USART1, Rx Complete */ +-#define USART1_RX_vect _VECTOR(36) +-#define USART1_RX_vect_num 36 +- +-/* USART1 Data register Empty */ +-#define USART1_UDRE_vect _VECTOR(37) +-#define USART1_UDRE_vect_num 37 +- +-/* USART1, Tx Complete */ +-#define USART1_TX_vect _VECTOR(38) +-#define USART1_TX_vect_num 38 +- +-/* 2-wire Serial Interface */ +-#define TWI_vect _VECTOR(39) +-#define TWI_vect_num 39 +- +-/* Store Program Memory Read */ +-#define SPM_READY_vect _VECTOR(40) +-#define SPM_READY_vect_num 40 +- +-/* Timer/Counter4 Capture Event */ +-#define TIMER4_CAPT_vect _VECTOR(41) +-#define TIMER4_CAPT_vect_num 41 +- +-/* Timer/Counter4 Compare Match A */ +-#define TIMER4_COMPA_vect _VECTOR(42) +-#define TIMER4_COMPA_vect_num 42 +- +-/* Timer/Counter4 Compare Match B */ +-#define TIMER4_COMPB_vect _VECTOR(43) +-#define TIMER4_COMPB_vect_num 43 +- +-/* Timer/Counter4 Compare Match C */ +-#define TIMER4_COMPC_vect _VECTOR(44) +-#define TIMER4_COMPC_vect_num 44 +- +-/* Timer/Counter4 Overflow */ +-#define TIMER4_OVF_vect _VECTOR(45) +-#define TIMER4_OVF_vect_num 45 +- +-/* Timer/Counter5 Capture Event */ +-#define TIMER5_CAPT_vect _VECTOR(46) +-#define TIMER5_CAPT_vect_num 46 +- +-/* Timer/Counter5 Compare Match A */ +-#define TIMER5_COMPA_vect _VECTOR(47) +-#define TIMER5_COMPA_vect_num 47 +- +-/* Timer/Counter5 Compare Match B */ +-#define TIMER5_COMPB_vect _VECTOR(48) +-#define TIMER5_COMPB_vect_num 48 +- +-/* Timer/Counter5 Compare Match C */ +-#define TIMER5_COMPC_vect _VECTOR(49) +-#define TIMER5_COMPC_vect_num 49 +- +-/* Timer/Counter5 Overflow */ +-#define TIMER5_OVF_vect _VECTOR(50) +-#define TIMER5_OVF_vect_num 50 +- +-/* USART2, Rx Complete */ +-#define USART2_RX_vect _VECTOR(51) +-#define USART2_RX_vect_num 51 +- +-/* USART2 Data register Empty */ +-#define USART2_UDRE_vect _VECTOR(52) +-#define USART2_UDRE_vect_num 52 +- +-/* USART2, Tx Complete */ +-#define USART2_TX_vect _VECTOR(53) +-#define USART2_TX_vect_num 53 +- +-/* USART3, Rx Complete */ +-#define USART3_RX_vect _VECTOR(54) +-#define USART3_RX_vect_num 54 +- +-/* USART3 Data register Empty */ +-#define USART3_UDRE_vect _VECTOR(55) +-#define USART3_UDRE_vect_num 55 +- +-/* USART3, Tx Complete */ +-#define USART3_TX_vect _VECTOR(56) +-#define USART3_TX_vect_num 56 +- +-/* TRX24 - PLL lock interrupt */ +-#define TRX24_PLL_LOCK_vect _VECTOR(57) +-#define TRX24_PLL_LOCK_vect_num 57 +- +-/* TRX24 - PLL unlock interrupt */ +-#define TRX24_PLL_UNLOCK_vect _VECTOR(58) +-#define TRX24_PLL_UNLOCK_vect_num 58 +- +-/* TRX24 - Receive start interrupt */ +-#define TRX24_RX_START_vect _VECTOR(59) +-#define TRX24_RX_START_vect_num 59 +- +-/* TRX24 - RX_END interrupt */ +-#define TRX24_RX_END_vect _VECTOR(60) +-#define TRX24_RX_END_vect_num 60 +- +-/* TRX24 - CCA/ED done interrupt */ +-#define TRX24_CCA_ED_DONE_vect _VECTOR(61) +-#define TRX24_CCA_ED_DONE_vect_num 61 +- +-/* TRX24 - XAH - AMI */ +-#define TRX24_XAH_AMI_vect _VECTOR(62) +-#define TRX24_XAH_AMI_vect_num 62 +- +-/* TRX24 - TX_END interrupt */ +-#define TRX24_TX_END_vect _VECTOR(63) +-#define TRX24_TX_END_vect_num 63 +- +-/* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */ +-#define TRX24_AWAKE_vect _VECTOR(64) +-#define TRX24_AWAKE_vect_num 64 +- +-/* Symbol counter - compare match 1 interrupt */ +-#define SCNT_CMP1_vect _VECTOR(65) +-#define SCNT_CMP1_vect_num 65 +- +-/* Symbol counter - compare match 2 interrupt */ +-#define SCNT_CMP2_vect _VECTOR(66) +-#define SCNT_CMP2_vect_num 66 +- +-/* Symbol counter - compare match 3 interrupt */ +-#define SCNT_CMP3_vect _VECTOR(67) +-#define SCNT_CMP3_vect_num 67 +- +-/* Symbol counter - overflow interrupt */ +-#define SCNT_OVFL_vect _VECTOR(68) +-#define SCNT_OVFL_vect_num 68 +- +-/* Symbol counter - backoff interrupt */ +-#define SCNT_BACKOFF_vect _VECTOR(69) +-#define SCNT_BACKOFF_vect_num 69 +- +-/* AES engine ready interrupt */ +-#define AES_READY_vect _VECTOR(70) +-#define AES_READY_vect_num 70 +- +-/* Battery monitor indicates supply voltage below threshold */ +-#define BAT_LOW_vect _VECTOR(71) +-#define BAT_LOW_vect_num 71 +- +- +-/* memory parameters */ +- +-#define SPM_PAGESIZE (256) +-#define RAMSTART (0x200) +-#define RAMSIZE (0x4000) +-#define RAMEND (0x41FF) +-#define XRAMSTART (0x0000) +-#define XRAMSIZE (0x0000) +-#define XRAMEND RAMEND +-#define E2END (0xFFF) +-#define E2PAGESIZE (0x08) +-#define FLASHEND (0x1ffff) +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* LFUSE Byte */ +-#define FUSE_CKSEL0 ~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 ~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 ~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 ~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 ~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 ~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT ~_BV(6) /* Clock output */ +-#define FUSE_CKDIV8 ~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) +- +-/* HFUSE Byte */ +-#define FUSE_BOOTRST ~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 ~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 ~_BV(2) /* Select Boot Size */ +-#define FUSE_EESAVE ~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON ~_BV(4) /* Watchdog timer always on */ +-#define FUSE_SPIEN ~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_JTAGEN ~_BV(6) /* Enable JTAG */ +-#define FUSE_OCDEN ~_BV(7) /* Enable OCD */ +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* EFUSE Byte */ +-#define FUSE_BODLEVEL0 ~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 ~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 ~_BV(2) /* Brown-out Detector trigger level */ +-#define EFUSE_DEFAULT (0xFF) +- +- +- +-/* Lock Bits */ +- +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +- +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0xA7 +-#define SIGNATURE_2 0x01 +- +-#endif /* _AVR_IOM128RFA1_H_ */ ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom128rfa1.h 2009 2009-07-01 14:57:41Z joerg_wunsch $ */ ++ ++/* avr/iom128rfa1.h - definitions for ATmega128RFA1 */ ++ ++#ifndef _AVR_IOM128RFA1_H_ ++#define _AVR_IOM128RFA1_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom128rfa1.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#include ++ ++#ifndef __ASSEMBLER__ ++# define _MMIO_BYTE_STRUCT(mem_addr,type) (*(volatile type *)(mem_addr)) ++# define _SFR_IO8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr) + 0x20, type) ++# define _SFR_MEM8_STRUCT(io_addr,type) _MMIO_BYTE_STRUCT((io_addr), type) ++#endif /* __ASSEMBLER__ */ ++ ++/* ++ * USAGE: ++ * ++ * simple register assignment: ++ * TIFR1 = 0x17 ++ * subregister assignment: ++ * TIFR1_struct.ocf1a = 1 ++ * (subregister names are converted to small letters) ++ */ ++ ++ ++/* Port A Input Pins Address */ ++#define PINA _SFR_IO8(0x00) ++ ++ /* PINA */ ++ ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++#define PINA4 4 ++#define PINA5 5 ++#define PINA6 6 ++#define PINA7 7 ++ ++/* Port A Data Direction Register */ ++#define DDRA _SFR_IO8(0x01) ++ ++ /* DDRA */ ++ ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++#define DDA4 4 ++#define DDA5 5 ++#define DDA6 6 ++#define DDA7 7 ++ ++/* Port A Data Register */ ++#define PORTA _SFR_IO8(0x02) ++ ++ /* PORTA */ ++ ++#define PORTA0 0 ++#define PA0 0 ++#define PORTA1 1 ++#define PA1 1 ++#define PORTA2 2 ++#define PA2 2 ++#define PORTA3 3 ++#define PA3 3 ++#define PORTA4 4 ++#define PA4 4 ++#define PORTA5 5 ++#define PA5 5 ++#define PORTA6 6 ++#define PA6 6 ++#define PORTA7 7 ++#define PA7 7 ++ ++/* Port B Input Pins Address */ ++#define PINB _SFR_IO8(0x03) ++ ++ /* PINB */ ++ ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++/* Port B Data Direction Register */ ++#define DDRB _SFR_IO8(0x04) ++ ++ /* DDRB */ ++ ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++/* Port B Data Register */ ++#define PORTB _SFR_IO8(0x05) ++ ++ /* PORTB */ ++ ++#define PORTB0 0 ++#define PB0 0 ++#define PORTB1 1 ++#define PB1 1 ++#define PORTB2 2 ++#define PB2 2 ++#define PORTB3 3 ++#define PB3 3 ++#define PORTB4 4 ++#define PB4 4 ++#define PORTB5 5 ++#define PB5 5 ++#define PORTB6 6 ++#define PB6 6 ++#define PORTB7 7 ++#define PB7 7 ++ ++/* Port C Input Pins Address */ ++#define PINC _SFR_IO8(0x06) ++ ++ /* PINC */ ++ ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++#define PINC7 7 ++ ++/* Port C Data Direction Register */ ++#define DDRC _SFR_IO8(0x07) ++ ++ /* DDRC */ ++ ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++#define DDC7 7 ++ ++/* Port C Data Register */ ++#define PORTC _SFR_IO8(0x08) ++ ++ /* PORTC */ ++ ++#define PORTC0 0 ++#define PC0 0 ++#define PORTC1 1 ++#define PC1 1 ++#define PORTC2 2 ++#define PC2 2 ++#define PORTC3 3 ++#define PC3 3 ++#define PORTC4 4 ++#define PC4 4 ++#define PORTC5 5 ++#define PC5 5 ++#define PORTC6 6 ++#define PC6 6 ++#define PORTC7 7 ++#define PC7 7 ++ ++/* Port D Input Pins Address */ ++#define PIND _SFR_IO8(0x09) ++ ++ /* PIND */ ++ ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++/* Port D Data Direction Register */ ++#define DDRD _SFR_IO8(0x0A) ++ ++ /* DDRD */ ++ ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++/* Port D Data Register */ ++#define PORTD _SFR_IO8(0x0B) ++ ++ /* PORTD */ ++ ++#define PORTD0 0 ++#define PD0 0 ++#define PORTD1 1 ++#define PD1 1 ++#define PORTD2 2 ++#define PD2 2 ++#define PORTD3 3 ++#define PD3 3 ++#define PORTD4 4 ++#define PD4 4 ++#define PORTD5 5 ++#define PD5 5 ++#define PORTD6 6 ++#define PD6 6 ++#define PORTD7 7 ++#define PD7 7 ++ ++/* Port E Input Pins Address */ ++#define PINE _SFR_IO8(0x0C) ++ ++ /* PINE */ ++ ++#define PINE0 0 ++#define PINE1 1 ++#define PINE2 2 ++#define PINE3 3 ++#define PINE4 4 ++#define PINE5 5 ++#define PINE6 6 ++#define PINE7 7 ++ ++/* Port E Data Direction Register */ ++#define DDRE _SFR_IO8(0x0D) ++ ++ /* DDRE */ ++ ++#define DDE0 0 ++#define DDE1 1 ++#define DDE2 2 ++#define DDE3 3 ++#define DDE4 4 ++#define DDE5 5 ++#define DDE6 6 ++#define DDE7 7 ++ ++/* Port E Data Register */ ++#define PORTE _SFR_IO8(0x0E) ++ ++ /* PORTE */ ++ ++#define PORTE0 0 ++#define PE0 0 ++#define PORTE1 1 ++#define PE1 1 ++#define PORTE2 2 ++#define PE2 2 ++#define PORTE3 3 ++#define PE3 3 ++#define PORTE4 4 ++#define PE4 4 ++#define PORTE5 5 ++#define PE5 5 ++#define PORTE6 6 ++#define PE6 6 ++#define PORTE7 7 ++#define PE7 7 ++ ++/* Port F Input Pins Address */ ++#define PINF _SFR_IO8(0x0F) ++ ++ /* PINF */ ++ ++#define PINF0 0 ++#define PINF1 1 ++#define PINF2 2 ++#define PINF3 3 ++#define PINF4 4 ++#define PINF5 5 ++#define PINF6 6 ++#define PINF7 7 ++ ++/* Port F Data Direction Register */ ++#define DDRF _SFR_IO8(0x10) ++ ++ /* DDRF */ ++ ++#define DDF0 0 ++#define DDF1 1 ++#define DDF2 2 ++#define DDF3 3 ++#define DDF4 4 ++#define DDF5 5 ++#define DDF6 6 ++#define DDF7 7 ++ ++/* Port F Data Register */ ++#define PORTF _SFR_IO8(0x11) ++ ++ /* PORTF */ ++ ++#define PORTF0 0 ++#define PF0 0 ++#define PORTF1 1 ++#define PF1 1 ++#define PORTF2 2 ++#define PF2 2 ++#define PORTF3 3 ++#define PF3 3 ++#define PORTF4 4 ++#define PF4 4 ++#define PORTF5 5 ++#define PF5 5 ++#define PORTF6 6 ++#define PF6 6 ++#define PORTF7 7 ++#define PF7 7 ++ ++/* Port G Input Pins Address */ ++#define PING _SFR_IO8(0x12) ++ ++ /* PING */ ++ ++#define PING0 0 ++#define PING1 1 ++#define PING2 2 ++#define PING3 3 ++#define PING4 4 ++#define PING5 5 ++ ++/* Port G Data Direction Register */ ++#define DDRG _SFR_IO8(0x13) ++ ++ /* DDRG */ ++ ++#define DDG0 0 ++#define DDG1 1 ++#define DDG2 2 ++#define DDG3 3 ++#define DDG4 4 ++#define DDG5 5 ++ ++/* Port G Data Register */ ++#define PORTG _SFR_IO8(0x14) ++ ++ /* PORTG */ ++ ++#define PORTG0 0 ++#define PG0 0 ++#define PORTG1 1 ++#define PG1 1 ++#define PORTG2 2 ++#define PG2 2 ++#define PORTG3 3 ++#define PG3 3 ++#define PORTG4 4 ++#define PG4 4 ++#define PORTG5 5 ++#define PG5 5 ++ ++/* Timer/Counter0 Interrupt Flag Register */ ++#define TIFR0 _SFR_IO8(0x15) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TIFR0 { ++ unsigned int tov0 : 1; /* Timer/Counter0 Overflow Flag */ ++ unsigned int ocf0a : 1; /* Timer/Counter0 Output Compare A Match Flag */ ++ unsigned int ocf0b : 1; /* Timer/Counter0 Output Compare B Match Flag */ ++ unsigned int : 5; ++}; ++ ++#define TIFR0_struct _SFR_IO8_STRUCT(0x15, struct __reg_TIFR0) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TIFR0 */ ++ ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++/* Timer/Counter1 Interrupt Flag Register */ ++#define TIFR1 _SFR_IO8(0x16) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TIFR1 { ++ unsigned int tov1 : 1; /* Timer/Counter1 Overflow Flag */ ++ unsigned int ocf1a : 1; /* Timer/Counter1 Output Compare A Match Flag */ ++ unsigned int ocf1b : 1; /* Timer/Counter1 Output Compare B Match Flag */ ++ unsigned int ocf1c : 1; /* Timer/Counter1 Output Compare C Match Flag */ ++ unsigned int : 1; ++ unsigned int icf1 : 1; /* Timer/Counter1 Input Capture Flag */ ++ unsigned int : 2; ++}; ++ ++#define TIFR1_struct _SFR_IO8_STRUCT(0x16, struct __reg_TIFR1) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TIFR1 */ ++ ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define OCF1C 3 ++#define ICF1 5 ++ ++/* Timer/Counter Interrupt Flag Register */ ++#define TIFR2 _SFR_IO8(0x17) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TIFR2 { ++ unsigned int tov2 : 1; /* Timer/Counter2 Overflow Flag */ ++ unsigned int ocf2a : 1; /* Output Compare Flag 2 A */ ++ unsigned int ocf2b : 1; /* Output Compare Flag 2 B */ ++ unsigned int : 5; ++}; ++ ++#define TIFR2_struct _SFR_IO8_STRUCT(0x17, struct __reg_TIFR2) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TIFR2 */ ++ ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++/* Timer/Counter3 Interrupt Flag Register */ ++#define TIFR3 _SFR_IO8(0x18) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TIFR3 { ++ unsigned int tov3 : 1; /* Timer/Counter3 Overflow Flag */ ++ unsigned int ocf3a : 1; /* Timer/Counter3 Output Compare A Match Flag */ ++ unsigned int ocf3b : 1; /* Timer/Counter3 Output Compare B Match Flag */ ++ unsigned int ocf3c : 1; /* Timer/Counter3 Output Compare C Match Flag */ ++ unsigned int : 1; ++ unsigned int icf3 : 1; /* Timer/Counter3 Input Capture Flag */ ++ unsigned int : 2; ++}; ++ ++#define TIFR3_struct _SFR_IO8_STRUCT(0x18, struct __reg_TIFR3) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TIFR3 */ ++ ++#define TOV3 0 ++#define OCF3A 1 ++#define OCF3B 2 ++#define OCF3C 3 ++#define ICF3 5 ++ ++/* Timer/Counter4 Interrupt Flag Register */ ++#define TIFR4 _SFR_IO8(0x19) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TIFR4 { ++ unsigned int tov4 : 1; /* Timer/Counter4 Overflow Flag */ ++ unsigned int ocf4a : 1; /* Timer/Counter4 Output Compare A Match Flag */ ++ unsigned int ocf4b : 1; /* Timer/Counter4 Output Compare B Match Flag */ ++ unsigned int ocf4c : 1; /* Timer/Counter4 Output Compare C Match Flag */ ++ unsigned int : 1; ++ unsigned int icf4 : 1; /* Timer/Counter4 Input Capture Flag */ ++ unsigned int : 2; ++}; ++ ++#define TIFR4_struct _SFR_IO8_STRUCT(0x19, struct __reg_TIFR4) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TIFR4 */ ++ ++#define TOV4 0 ++#define OCF4A 1 ++#define OCF4B 2 ++#define OCF4C 3 ++#define ICF4 5 ++ ++/* Timer/Counter5 Interrupt Flag Register */ ++#define TIFR5 _SFR_IO8(0x1A) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TIFR5 { ++ unsigned int tov5 : 1; /* Timer/Counter5 Overflow Flag */ ++ unsigned int ocf5a : 1; /* Timer/Counter5 Output Compare A Match Flag */ ++ unsigned int ocf5b : 1; /* Timer/Counter5 Output Compare B Match Flag */ ++ unsigned int ocf5c : 1; /* Timer/Counter5 Output Compare C Match Flag */ ++ unsigned int : 1; ++ unsigned int icf5 : 1; /* Timer/Counter5 Input Capture Flag */ ++ unsigned int : 2; ++}; ++ ++#define TIFR5_struct _SFR_IO8_STRUCT(0x1a, struct __reg_TIFR5) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TIFR5 */ ++ ++#define TOV5 0 ++#define OCF5A 1 ++#define OCF5B 2 ++#define OCF5C 3 ++#define ICF5 5 ++ ++/* Pin Change Interrupt Flag Register */ ++#define PCIFR _SFR_IO8(0x1B) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_PCIFR { ++ unsigned int pcif : 3; /* Pin Change Interrupt Flag 2 */ ++ unsigned int : 5; ++}; ++ ++#define PCIFR_struct _SFR_IO8_STRUCT(0x1b, struct __reg_PCIFR) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* PCIFR */ ++ ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++ ++/* External Interrupt Flag Register */ ++#define EIFR _SFR_IO8(0x1C) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_EIFR { ++ unsigned int intf : 8; /* External Interrupt Flag */ ++}; ++ ++#define EIFR_struct _SFR_IO8_STRUCT(0x1c, struct __reg_EIFR) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* EIFR */ ++ ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++#define INTF4 4 ++#define INTF5 5 ++#define INTF6 6 ++#define INTF7 7 ++ ++/* External Interrupt Mask Register */ ++#define EIMSK _SFR_IO8(0x1D) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_EIMSK { ++ unsigned int intm : 8; /* External Interrupt Request Enable */ ++}; ++ ++#define EIMSK_struct _SFR_IO8_STRUCT(0x1d, struct __reg_EIMSK) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* EIMSK */ ++ ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++#define INT3 3 ++#define INT4 4 ++#define INT5 5 ++#define INT6 6 ++#define INT7 7 ++ ++/* General Purpose IO Register 0 */ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_GPIOR0 { ++ unsigned int gpior0 : 8; /* General Purpose I/O Register 0 Value */ ++}; ++ ++#define GPIOR0_struct _SFR_IO8_STRUCT(0x1e, struct __reg_GPIOR0) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* GPIOR0 */ ++ ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++/* 6-char sequence denoting where to find the EEPROM registers in memory space. ++ Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM ++ subroutines. ++ First two letters: EECR address. ++ Second two letters: EEDR address. ++ Last two letters: EEAR address. */ ++ ++#define __EEPROM_REG_LOCATIONS__ 1F2021 ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1F) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_EECR { ++ unsigned int eere : 1; /* EEPROM Read Enable */ ++ unsigned int eepe : 1; /* EEPROM Programming Enable */ ++ unsigned int eempe : 1; /* EEPROM Master Write Enable */ ++ unsigned int eerie : 1; /* EEPROM Ready Interrupt Enable */ ++ unsigned int eepm : 2; /* EEPROM Programming Mode */ ++ unsigned int : 2; ++}; ++ ++#define EECR_struct _SFR_IO8_STRUCT(0x1f, struct __reg_EECR) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* EECR */ ++ ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x20) ++ ++ /* EEDR */ ++ ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++/* EEPROM Address Register Bytes */ ++#define EEAR _SFR_IO16(0x21) ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++/* General Timer/Counter Control Register */ ++#define GTCCR _SFR_IO8(0x23) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_GTCCR { ++ unsigned int psrsync : 1; /* Prescaler Reset for Synchronous Timer/Counters */ ++ unsigned int psrasy : 1; /* Prescaler Reset Timer/Counter2 */ ++ unsigned int : 5; ++ unsigned int tsm : 1; /* Timer/Counter Synchronization Mode */ ++}; ++ ++#define GTCCR_struct _SFR_IO8_STRUCT(0x23, struct __reg_GTCCR) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* GTCCR */ ++ ++#define PSRSYNC 0 ++#define PSR10 0 ++#define PSRASY 1 ++#define PSR2 1 ++#define TSM 7 ++ ++/* Timer/Counter0 Control Register A */ ++#define TCCR0A _SFR_IO8(0x24) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TCCR0A { ++ unsigned int wgm0 : 2; /* Waveform Generation Mode */ ++ unsigned int : 2; ++ unsigned int com0b : 2; /* Compare Match Output B Mode */ ++ unsigned int com0a : 2; /* Compare Match Output A Mode */ ++}; ++ ++#define TCCR0A_struct _SFR_IO8_STRUCT(0x24, struct __reg_TCCR0A) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TCCR0A */ ++ ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++/* Timer/Counter0 Control Register B */ ++#define TCCR0B _SFR_IO8(0x25) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TCCR0B { ++ unsigned int cs0 : 3; /* Clock Select */ ++ unsigned int wgm02 : 1; /* */ ++ unsigned int : 2; ++ unsigned int foc0b : 1; /* Force Output Compare B */ ++ unsigned int foc0a : 1; /* Force Output Compare A */ ++}; ++ ++#define TCCR0B_struct _SFR_IO8_STRUCT(0x25, struct __reg_TCCR0B) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TCCR0B */ ++ ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++/* Timer/Counter0 Register */ ++#define TCNT0 _SFR_IO8(0x26) ++ ++ /* TCNT0 */ ++ ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++/* Timer/Counter0 Output Compare Register */ ++#define OCR0A _SFR_IO8(0x27) ++ ++ /* OCR0A */ ++ ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++/* Timer/Counter0 Output Compare Register B */ ++#define OCR0B _SFR_IO8(0x28) ++ ++ /* OCR0B */ ++ ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++/* General Purpose IO Register 1 */ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_GPIOR1 { ++ unsigned int gpior1 : 8; /* General Purpose I/O Register 1 Value */ ++}; ++ ++#define GPIOR1_struct _SFR_IO8_STRUCT(0x2a, struct __reg_GPIOR1) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* GPIOR1 */ ++ ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++/* General Purpose I/O Register 2 */ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_GPIOR2 { ++ unsigned int gpior2 : 8; /* General Purpose I/O Register 2 Value */ ++}; ++ ++#define GPIOR2_struct _SFR_IO8_STRUCT(0x2b, struct __reg_GPIOR2) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* GPIOR2 */ ++ ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++/* SPI Control Register */ ++#define SPCR _SFR_IO8(0x2C) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SPCR { ++ unsigned int spr : 2; /* SPI Clock Rate Select 1 and 0 */ ++ unsigned int cpha : 1; /* Clock Phase */ ++ unsigned int cpol : 1; /* Clock polarity */ ++ unsigned int mstr : 1; /* Master/Slave Select */ ++ unsigned int dord : 1; /* Data Order */ ++ unsigned int spe : 1; /* SPI Enable */ ++ unsigned int spie : 1; /* SPI Interrupt Enable */ ++}; ++ ++#define SPCR_struct _SFR_IO8_STRUCT(0x2c, struct __reg_SPCR) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SPCR */ ++ ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++/* SPI Status Register */ ++#define SPSR _SFR_IO8(0x2D) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SPSR { ++ unsigned int spi2x : 1; /* Double SPI Speed Bit */ ++ unsigned int : 5; ++ unsigned int wcol : 1; /* Write Collision Flag */ ++ unsigned int spif : 1; /* SPI Interrupt Flag */ ++}; ++ ++#define SPSR_struct _SFR_IO8_STRUCT(0x2d, struct __reg_SPSR) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SPSR */ ++ ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++/* SPI Data Register */ ++#define SPDR _SFR_IO8(0x2E) ++ ++ /* SPDR */ ++ ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++/* Analog Comparator Control And Status Register */ ++#define ACSR _SFR_IO8(0x30) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_ACSR { ++ unsigned int acis : 2; /* Analog Comparator Interrupt Mode Select */ ++ unsigned int acic : 1; /* Analog Comparator Input Capture Enable */ ++ unsigned int acie : 1; /* Analog Comparator Interrupt Enable */ ++ unsigned int aci : 1; /* Analog Comparator Interrupt Flag */ ++ unsigned int aco : 1; /* Analog Compare Output */ ++ unsigned int acbg : 1; /* Analog Comparator Bandgap Select */ ++ unsigned int acd : 1; /* Analog Comparator Disable */ ++}; ++ ++#define ACSR_struct _SFR_IO8_STRUCT(0x30, struct __reg_ACSR) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* ACSR */ ++ ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++/* On-Chip Debug Register */ ++#define OCDR _SFR_IO8(0x31) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_OCDR { ++ unsigned int ocdr : 8; /* On-Chip Debug Register Data */ ++}; ++ ++#define OCDR_struct _SFR_IO8_STRUCT(0x31, struct __reg_OCDR) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* OCDR */ ++ ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCDR7 7 ++#define IDRD 7 ++ ++/* Sleep Mode Control Register */ ++#define SMCR _SFR_IO8(0x33) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SMCR { ++ unsigned int se : 1; /* Sleep Enable */ ++ unsigned int sm : 3; /* Sleep Mode Select bits */ ++ unsigned int : 4; ++}; ++ ++#define SMCR_struct _SFR_IO8_STRUCT(0x33, struct __reg_SMCR) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SMCR */ ++ ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++/* MCU Status Register */ ++#define MCUSR _SFR_IO8(0x34) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_MCUSR { ++ unsigned int porf : 1; /* Power-on Reset Flag */ ++ unsigned int extrf : 1; /* External Reset Flag */ ++ unsigned int borf : 1; /* Brown-out Reset Flag */ ++ unsigned int wdrf : 1; /* Watchdog Reset Flag */ ++ unsigned int jtrf : 1; /* JTAG Reset Flag */ ++ unsigned int : 3; ++}; ++ ++#define MCUSR_struct _SFR_IO8_STRUCT(0x34, struct __reg_MCUSR) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* MCUSR */ ++ ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define JTRF 4 ++ ++/* MCU Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_MCUCR { ++ unsigned int ivce : 1; /* Interrupt Vector Change Enable */ ++ unsigned int ivsel : 1; /* Interrupt Vector Select */ ++ unsigned int : 2; ++ unsigned int pud : 1; /* Pull-up Disable */ ++ unsigned int : 2; ++ unsigned int jtd : 1; /* JTAG Interface Disable */ ++}; ++ ++#define MCUCR_struct _SFR_IO8_STRUCT(0x35, struct __reg_MCUCR) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* MCUCR */ ++ ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define JTD 7 ++ ++/* Store Program Memory Control Register */ ++#define SPMCSR _SFR_IO8(0x37) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SPMCSR { ++ unsigned int spmen : 1; /* Store Program Memory Enable */ ++ unsigned int pgers : 1; /* Page Erase */ ++ unsigned int pgwrt : 1; /* Page Write */ ++ unsigned int blbset : 1; /* Boot Lock Bit Set */ ++ unsigned int rwwsre : 1; /* Read While Write Section Read Enable */ ++ unsigned int sigrd : 1; /* Signature Row Read */ ++ unsigned int rwwsb : 1; /* Read While Write Section Busy */ ++ unsigned int spmie : 1; /* SPM Interrupt Enable */ ++}; ++ ++#define SPMCSR_struct _SFR_IO8_STRUCT(0x37, struct __reg_SPMCSR) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SPMCSR */ ++ ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Extended Z-pointer Register for ELPM/SPM */ ++#define RAMPZ _SFR_IO8(0x3B) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_RAMPZ { ++ unsigned int rampz : 2; /* Extended Z-Pointer Value */ ++ unsigned int : 6; ++}; ++ ++#define RAMPZ_struct _SFR_IO8_STRUCT(0x3b, struct __reg_RAMPZ) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* RAMPZ */ ++ ++#define RAMPZ0 0 ++#define RAMPZ1 1 ++ ++/* Stack Pointer */ ++#define SP _SFR_IO16(0x3D) ++#define SPL _SFR_IO8(0x3D) ++#define SPH _SFR_IO8(0x3E) ++ ++/* Status Register */ ++#define SREG _SFR_IO8(0x3F) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SREG { ++ unsigned int c : 1; /* Carry Flag */ ++ unsigned int z : 1; /* Zero Flag */ ++ unsigned int n : 1; /* Negative Flag */ ++ unsigned int v : 1; /* Two's Complement Overflow Flag */ ++ unsigned int s : 1; /* Sign Bit */ ++ unsigned int h : 1; /* Half Carry Flag */ ++ unsigned int t : 1; /* Bit Copy Storage */ ++ unsigned int i : 1; /* Global Interrupt Enable */ ++}; ++ ++#define SREG_struct _SFR_IO8_STRUCT(0x3f, struct __reg_SREG) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SREG */ ++ ++#define SREG_C 0 ++#define SREG_Z 1 ++#define SREG_N 2 ++#define SREG_V 3 ++#define SREG_S 4 ++#define SREG_H 5 ++#define SREG_T 6 ++#define SREG_I 7 ++ ++/* Watchdog Timer Control Register */ ++#define WDTCSR _SFR_MEM8(0x60) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_WDTCSR { ++ unsigned int wdp : 3; /* Watchdog Timer Prescaler bits */ ++ unsigned int wde : 1; /* Watch Dog Enable */ ++ unsigned int wdce : 1; /* Watchdog Change Enable */ ++ unsigned int : 1; ++ unsigned int wdie : 1; /* Watchdog Timeout Interrupt Enable */ ++ unsigned int wdif : 1; /* Watchdog Timeout Interrupt Flag */ ++}; ++ ++#define WDTCSR_struct _SFR_MEM8_STRUCT(0x60, struct __reg_WDTCSR) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* WDTCSR */ ++ ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++/* Clock Prescale Register */ ++#define CLKPR _SFR_MEM8(0x61) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_CLKPR { ++ unsigned int clkps : 4; /* Clock Prescaler Select Bits */ ++ unsigned int : 3; ++ unsigned int clkpce : 1; /* Clock Prescaler Change Enable */ ++}; ++ ++#define CLKPR_struct _SFR_MEM8_STRUCT(0x61, struct __reg_CLKPR) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* CLKPR */ ++ ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Power Reduction Register 2 */ ++#define PRR2 _SFR_MEM8(0x63) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_PRR2 { ++ unsigned int prram : 4; /* Power Reduction SRAM 3 */ ++ unsigned int : 4; ++}; ++ ++#define PRR2_struct _SFR_MEM8_STRUCT(0x63, struct __reg_PRR2) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* PRR2 */ ++ ++#define PRRAM0 0 ++#define PRRAM1 1 ++#define PRRAM2 2 ++#define PRRAM3 3 ++ ++/* Power Reduction Register0 */ ++#define PRR0 _SFR_MEM8(0x64) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_PRR0 { ++ unsigned int pradc : 1; /* Power Reduction ADC */ ++ unsigned int prusart0 : 1; /* Power Reduction USART */ ++ unsigned int prspi : 1; /* Power Reduction Serial Peripheral Interface */ ++ unsigned int prtim1 : 1; /* Power Reduction Timer/Counter1 */ ++ unsigned int prpga : 1; /* Power Reduction PGA */ ++ unsigned int prtim0 : 1; /* Power Reduction Timer/Counter0 */ ++ unsigned int prtim2 : 1; /* Power Reduction Timer/Counter2 */ ++ unsigned int prtwi : 1; /* Power Reduction TWI */ ++}; ++ ++#define PRR0_struct _SFR_MEM8_STRUCT(0x64, struct __reg_PRR0) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* PRR0 */ ++ ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRPGA 4 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++/* Power Reduction Register 1 */ ++#define PRR1 _SFR_MEM8(0x65) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_PRR1 { ++ unsigned int prusart : 3; /* Reserved */ ++ unsigned int prtim3 : 1; /* Power Reduction Timer/Counter3 */ ++ unsigned int prtim4 : 1; /* Power Reduction Timer/Counter4 */ ++ unsigned int prtim5 : 1; /* Power Reduction Timer/Counter5 */ ++ unsigned int prtrx24 : 1; /* Power Reduction Transceiver */ ++ unsigned int : 1; ++}; ++ ++#define PRR1_struct _SFR_MEM8_STRUCT(0x65, struct __reg_PRR1) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* PRR1 */ ++ ++#define PRUSART1 0 ++#define PRUSART2 1 ++#define PRUSART3 2 ++#define PRTIM3 3 ++#define PRTIM4 4 ++#define PRTIM5 5 ++#define PRTRX24 6 ++ ++/* Oscillator Calibration Value */ ++#define OSCCAL _SFR_MEM8(0x66) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_OSCCAL { ++ unsigned int cal : 8; /* Oscillator Calibration Tuning Value */ ++}; ++ ++#define OSCCAL_struct _SFR_MEM8_STRUCT(0x66, struct __reg_OSCCAL) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* OSCCAL */ ++ ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++/* Reference Voltage Calibration Register */ ++#define BGCR _SFR_MEM8(0x67) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_BGCR { ++ unsigned int bgcal : 3; /* Coarse Calibration Bits */ ++ unsigned int bgcal_fine : 4; /* Fine Calibration Bits */ ++ unsigned int : 1; ++}; ++ ++#define BGCR_struct _SFR_MEM8_STRUCT(0x67, struct __reg_BGCR) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* BGCR */ ++ ++#define BGCAL0 0 ++#define BGCAL1 1 ++#define BGCAL2 2 ++#define BGCAL_FINE0 3 ++#define BGCAL_FINE1 4 ++#define BGCAL_FINE2 5 ++#define BGCAL_FINE3 6 ++ ++/* Pin Change Interrupt Control Register */ ++#define PCICR _SFR_MEM8(0x68) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_PCICR { ++ unsigned int pcie : 3; /* Pin Change Interrupt Enable 2 */ ++ unsigned int : 5; ++}; ++ ++#define PCICR_struct _SFR_MEM8_STRUCT(0x68, struct __reg_PCICR) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* PCICR */ ++ ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++ ++/* External Interrupt Control Register A */ ++#define EICRA _SFR_MEM8(0x69) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_EICRA { ++ unsigned int isc0 : 2; /* External Interrupt 0 Sense Control Bit */ ++ unsigned int isc1 : 2; /* External Interrupt 1 Sense Control Bit */ ++ unsigned int isc2 : 2; /* External Interrupt 2 Sense Control Bit */ ++ unsigned int isc3 : 2; /* External Interrupt 3 Sense Control Bit */ ++}; ++ ++#define EICRA_struct _SFR_MEM8_STRUCT(0x69, struct __reg_EICRA) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* EICRA */ ++ ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++/* External Interrupt Control Register B */ ++#define EICRB _SFR_MEM8(0x6A) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_EICRB { ++ unsigned int isc4 : 2; /* External Interrupt 4 Sense Control Bit */ ++ unsigned int isc5 : 2; /* External Interrupt 5 Sense Control Bit */ ++ unsigned int isc6 : 2; /* External Interrupt 6 Sense Control Bit */ ++ unsigned int isc7 : 2; /* External Interrupt 7 Sense Control Bit */ ++}; ++ ++#define EICRB_struct _SFR_MEM8_STRUCT(0x6a, struct __reg_EICRB) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* EICRB */ ++ ++#define ISC40 0 ++#define ISC41 1 ++#define ISC50 2 ++#define ISC51 3 ++#define ISC60 4 ++#define ISC61 5 ++#define ISC70 6 ++#define ISC71 7 ++ ++/* Pin Change Mask Register 0 */ ++#define PCMSK0 _SFR_MEM8(0x6B) ++ ++ /* PCMSK0 */ ++ ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++/* Pin Change Mask Register 1 */ ++#define PCMSK1 _SFR_MEM8(0x6C) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_PCMSK1 { ++ unsigned int pcint : 2; /* Pin Change Enable Mask */ ++ unsigned int pcint1 : 6; /* Pin Change Enable Mask */ ++}; ++ ++#define PCMSK1_struct _SFR_MEM8_STRUCT(0x6c, struct __reg_PCMSK1) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* PCMSK1 */ ++ ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++/* Pin Change Mask Register 2 */ ++#define PCMSK2 _SFR_MEM8(0x6D) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_PCMSK2 { ++ unsigned int pcint1 : 4; /* Pin Change Enable Mask */ ++ unsigned int pcint2 : 4; /* Pin Change Enable Mask */ ++}; ++ ++#define PCMSK2_struct _SFR_MEM8_STRUCT(0x6d, struct __reg_PCMSK2) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* PCMSK2 */ ++ ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++/* Timer/Counter0 Interrupt Mask Register */ ++#define TIMSK0 _SFR_MEM8(0x6E) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TIMSK0 { ++ unsigned int toie0 : 1; /* Timer/Counter0 Overflow Interrupt Enable */ ++ unsigned int ocie0a : 1; /* Timer/Counter0 Output Compare Match A Interrupt Enable */ ++ unsigned int ocie0b : 1; /* Timer/Counter0 Output Compare Match B Interrupt Enable */ ++ unsigned int : 5; ++}; ++ ++#define TIMSK0_struct _SFR_MEM8_STRUCT(0x6e, struct __reg_TIMSK0) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TIMSK0 */ ++ ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++/* Timer/Counter1 Interrupt Mask Register */ ++#define TIMSK1 _SFR_MEM8(0x6F) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TIMSK1 { ++ unsigned int toie1 : 1; /* Timer/Counter1 Overflow Interrupt Enable */ ++ unsigned int ocie1a : 1; /* Timer/Counter1 Output Compare A Match Interrupt Enable */ ++ unsigned int ocie1b : 1; /* Timer/Counter1 Output Compare B Match Interrupt Enable */ ++ unsigned int ocie1c : 1; /* Timer/Counter1 Output Compare C Match Interrupt Enable */ ++ unsigned int : 1; ++ unsigned int icie1 : 1; /* Timer/Counter1 Input Capture Interrupt Enable */ ++ unsigned int : 2; ++}; ++ ++#define TIMSK1_struct _SFR_MEM8_STRUCT(0x6f, struct __reg_TIMSK1) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TIMSK1 */ ++ ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define OCIE1C 3 ++#define ICIE1 5 ++ ++/* Timer/Counter Interrupt Mask register */ ++#define TIMSK2 _SFR_MEM8(0x70) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TIMSK2 { ++ unsigned int toie2 : 1; /* Timer/Counter2 Overflow Interrupt Enable */ ++ unsigned int ocie2a : 1; /* Timer/Counter2 Output Compare Match A Interrupt Enable */ ++ unsigned int ocie2b : 1; /* Timer/Counter2 Output Compare Match B Interrupt Enable */ ++ unsigned int : 5; ++}; ++ ++#define TIMSK2_struct _SFR_MEM8_STRUCT(0x70, struct __reg_TIMSK2) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TIMSK2 */ ++ ++#define TOIE2 0 ++#define TOIE2A 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++/* Timer/Counter3 Interrupt Mask Register */ ++#define TIMSK3 _SFR_MEM8(0x71) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TIMSK3 { ++ unsigned int toie3 : 1; /* Timer/Counter3 Overflow Interrupt Enable */ ++ unsigned int ocie3a : 1; /* Timer/Counter3 Output Compare A Match Interrupt Enable */ ++ unsigned int ocie3b : 1; /* Timer/Counter3 Output Compare B Match Interrupt Enable */ ++ unsigned int ocie3c : 1; /* Timer/Counter3 Output Compare C Match Interrupt Enable */ ++ unsigned int : 1; ++ unsigned int icie3 : 1; /* Timer/Counter3 Input Capture Interrupt Enable */ ++ unsigned int : 2; ++}; ++ ++#define TIMSK3_struct _SFR_MEM8_STRUCT(0x71, struct __reg_TIMSK3) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TIMSK3 */ ++ ++#define TOIE3 0 ++#define OCIE3A 1 ++#define OCIE3B 2 ++#define OCIE3C 3 ++#define ICIE3 5 ++ ++/* Timer/Counter4 Interrupt Mask Register */ ++#define TIMSK4 _SFR_MEM8(0x72) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TIMSK4 { ++ unsigned int toie4 : 1; /* Timer/Counter4 Overflow Interrupt Enable */ ++ unsigned int ocie4a : 1; /* Timer/Counter4 Output Compare A Match Interrupt Enable */ ++ unsigned int ocie4b : 1; /* Timer/Counter4 Output Compare B Match Interrupt Enable */ ++ unsigned int ocie4c : 1; /* Timer/Counter4 Output Compare C Match Interrupt Enable */ ++ unsigned int : 1; ++ unsigned int icie4 : 1; /* Timer/Counter4 Input Capture Interrupt Enable */ ++ unsigned int : 2; ++}; ++ ++#define TIMSK4_struct _SFR_MEM8_STRUCT(0x72, struct __reg_TIMSK4) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TIMSK4 */ ++ ++#define TOIE4 0 ++#define OCIE4A 1 ++#define OCIE4B 2 ++#define OCIE4C 3 ++#define ICIE4 5 ++ ++/* Timer/Counter5 Interrupt Mask Register */ ++#define TIMSK5 _SFR_MEM8(0x73) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TIMSK5 { ++ unsigned int toie5 : 1; /* Timer/Counter5 Overflow Interrupt Enable */ ++ unsigned int ocie5a : 1; /* Timer/Counter5 Output Compare A Match Interrupt Enable */ ++ unsigned int ocie5b : 1; /* Timer/Counter5 Output Compare B Match Interrupt Enable */ ++ unsigned int ocie5c : 1; /* Timer/Counter5 Output Compare C Match Interrupt Enable */ ++ unsigned int : 1; ++ unsigned int icie5 : 1; /* Timer/Counter5 Input Capture Interrupt Enable */ ++ unsigned int : 2; ++}; ++ ++#define TIMSK5_struct _SFR_MEM8_STRUCT(0x73, struct __reg_TIMSK5) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TIMSK5 */ ++ ++#define TOIE5 0 ++#define OCIE5A 1 ++#define OCIE5B 2 ++#define OCIE5C 3 ++#define ICIE5 5 ++ ++/* Flash Extended-Mode Control-Register */ ++#define NEMCR _SFR_MEM8(0x75) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_NEMCR { ++ unsigned int : 4; ++ unsigned int aeam : 2; /* Address for Extended Address Mode of Extra Rows */ ++ unsigned int eneam : 1; /* Enable Extended Address Mode for Extra Rows */ ++ unsigned int : 1; ++}; ++ ++#define NEMCR_struct _SFR_MEM8_STRUCT(0x75, struct __reg_NEMCR) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* NEMCR */ ++ ++#define AEAM0 4 ++#define AEAM1 5 ++#define ENEAM 6 ++ ++/* The ADC Control and Status Register C */ ++#define ADCSRC _SFR_MEM8(0x77) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_ADCSRC { ++ unsigned int adsut : 5; /* ADC Start-up Time */ ++ unsigned int res0 : 1; /* Reserved */ ++ unsigned int adtht : 2; /* ADC Track-and-Hold Time */ ++}; ++ ++#define ADCSRC_struct _SFR_MEM8_STRUCT(0x77, struct __reg_ADCSRC) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* ADCSRC */ ++ ++#define ADSUT0 0 ++#define ADSUT1 1 ++#define ADSUT2 2 ++#define ADSUT3 3 ++#define ADSUT4 4 ++#define ADTHT0 6 ++#define ADTHT1 7 ++ ++/* ADC Data Register Bytes */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++#endif /* __ASSEMBLER__ */ ++#define ADCW _SFR_MEM16(0x78) ++#define ADCWL _SFR_MEM8(0x78) ++#define ADCWH _SFR_MEM8(0x79) ++ ++/* The ADC Control and Status Register A */ ++#define ADCSRA _SFR_MEM8(0x7A) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_ADCSRA { ++ unsigned int adps : 3; /* ADC Prescaler Select Bits */ ++ unsigned int adie : 1; /* ADC Interrupt Enable */ ++ unsigned int adif : 1; /* ADC Interrupt Flag */ ++ unsigned int adate : 1; /* ADC Auto Trigger Enable */ ++ unsigned int adsc : 1; /* ADC Start Conversion */ ++ unsigned int aden : 1; /* ADC Enable */ ++}; ++ ++#define ADCSRA_struct _SFR_MEM8_STRUCT(0x7a, struct __reg_ADCSRA) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* ADCSRA */ ++ ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++/* ADC Control and Status Register B */ ++#define ADCSRB _SFR_MEM8(0x7B) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_ADCSRB { ++ unsigned int adts : 3; /* ADC Auto Trigger Source */ ++ unsigned int mux5 : 1; /* Analog Channel and Gain Selection Bits */ ++ unsigned int acch : 1; /* Analog Channel Change */ ++ unsigned int refok : 1; /* Reference Voltage OK */ ++ unsigned int acme : 1; /* Analog Comparator Multiplexer Enable */ ++ unsigned int avddok : 1; /* AVDD Supply Voltage OK */ ++}; ++ ++#define ADCSRB_struct _SFR_MEM8_STRUCT(0x7b, struct __reg_ADCSRB) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* ADCSRB */ ++ ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define MUX5 3 ++#define ACCH 4 ++#define REFOK 5 ++#define ACME 6 ++#define AVDDOK 7 ++ ++/* The ADC Multiplexer Selection Register */ ++#define ADMUX _SFR_MEM8(0x7C) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_ADMUX { ++ unsigned int mux : 5; /* Analog Channel and Gain Selection Bits */ ++ unsigned int adlar : 1; /* ADC Left Adjust Result */ ++ unsigned int refs : 2; /* Reference Selection Bits */ ++}; ++ ++#define ADMUX_struct _SFR_MEM8_STRUCT(0x7c, struct __reg_ADMUX) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* ADMUX */ ++ ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Digital Input Disable Register 2 */ ++#define DIDR2 _SFR_MEM8(0x7D) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_DIDR2 { ++ unsigned int adc8d : 1; /* Reserved Bits */ ++ unsigned int adc9d : 1; /* Reserved Bits */ ++ unsigned int adc10d : 1; /* Reserved Bits */ ++ unsigned int adc11d : 1; /* Reserved Bits */ ++ unsigned int adc12d : 1; /* Reserved Bits */ ++ unsigned int adc13d : 1; /* Reserved Bits */ ++ unsigned int adc14d : 1; /* Reserved Bits */ ++ unsigned int adc15d : 1; /* Reserved Bits */ ++}; ++ ++#define DIDR2_struct _SFR_MEM8_STRUCT(0x7d, struct __reg_DIDR2) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* DIDR2 */ ++ ++#define ADC8D 0 ++#define ADC9D 1 ++#define ADC10D 2 ++#define ADC11D 3 ++#define ADC12D 4 ++#define ADC13D 5 ++#define ADC14D 6 ++#define ADC15D 7 ++ ++/* Digital Input Disable Register 0 */ ++#define DIDR0 _SFR_MEM8(0x7E) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_DIDR0 { ++ unsigned int adc0d : 1; /* Disable ADC7:0 Digital Input */ ++ unsigned int adc1d : 1; /* Disable ADC7:0 Digital Input */ ++ unsigned int adc2d : 1; /* Disable ADC7:0 Digital Input */ ++ unsigned int adc3d : 1; /* Disable ADC7:0 Digital Input */ ++ unsigned int adc4d : 1; /* Disable ADC7:0 Digital Input */ ++ unsigned int adc5d : 1; /* Disable ADC7:0 Digital Input */ ++ unsigned int adc6d : 1; /* Disable ADC7:0 Digital Input */ ++ unsigned int adc7d : 1; /* Disable ADC7:0 Digital Input */ ++}; ++ ++#define DIDR0_struct _SFR_MEM8_STRUCT(0x7e, struct __reg_DIDR0) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* DIDR0 */ ++ ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++/* Digital Input Disable Register 1 */ ++#define DIDR1 _SFR_MEM8(0x7F) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_DIDR1 { ++ unsigned int ain0d : 1; /* AIN0 Digital Input Disable */ ++ unsigned int ain1d : 1; /* AIN1 Digital Input Disable */ ++ unsigned int : 6; ++}; ++ ++#define DIDR1_struct _SFR_MEM8_STRUCT(0x7f, struct __reg_DIDR1) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* DIDR1 */ ++ ++#define AIN0D 0 ++#define AIN1D 1 ++ ++/* Timer/Counter1 Control Register A */ ++#define TCCR1A _SFR_MEM8(0x80) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TCCR1A { ++ unsigned int wgm1 : 2; /* Waveform Generation Mode */ ++ unsigned int com1c : 2; /* Compare Output Mode for Channel C */ ++ unsigned int com1b : 2; /* Compare Output Mode for Channel B */ ++ unsigned int com1a : 2; /* Compare Output Mode for Channel A */ ++}; ++ ++#define TCCR1A_struct _SFR_MEM8_STRUCT(0x80, struct __reg_TCCR1A) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TCCR1A */ ++ ++#define WGM10 0 ++#define WGM11 1 ++#define COM1C0 2 ++#define COM1C1 3 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++/* Timer/Counter1 Control Register B */ ++#define TCCR1B _SFR_MEM8(0x81) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TCCR1B { ++ unsigned int cs1 : 3; /* Clock Select */ ++ unsigned int wgm1 : 2; /* Waveform Generation Mode */ ++ unsigned int : 1; ++ unsigned int ices1 : 1; /* Input Capture 1 Edge Select */ ++ unsigned int icnc1 : 1; /* Input Capture 1 Noise Canceller */ ++}; ++ ++#define TCCR1B_struct _SFR_MEM8_STRUCT(0x81, struct __reg_TCCR1B) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TCCR1B */ ++ ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++/* Timer/Counter1 Control Register C */ ++#define TCCR1C _SFR_MEM8(0x82) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TCCR1C { ++ unsigned int : 5; ++ unsigned int foc1c : 1; /* Force Output Compare for Channel C */ ++ unsigned int foc1b : 1; /* Force Output Compare for Channel B */ ++ unsigned int foc1a : 1; /* Force Output Compare for Channel A */ ++}; ++ ++#define TCCR1C_struct _SFR_MEM8_STRUCT(0x82, struct __reg_TCCR1C) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TCCR1C */ ++ ++#define FOC1C 5 ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Timer/Counter1 Bytes */ ++#define TCNT1 _SFR_MEM16(0x84) ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Timer/Counter1 Input Capture Register Bytes */ ++#define ICR1 _SFR_MEM16(0x86) ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Timer/Counter1 Output Compare Register A Bytes */ ++#define OCR1A _SFR_MEM16(0x88) ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Timer/Counter1 Output Compare Register B Bytes */ ++#define OCR1B _SFR_MEM16(0x8A) ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Timer/Counter1 Output Compare Register C Bytes */ ++#define OCR1C _SFR_MEM16(0x8C) ++#define OCR1CL _SFR_MEM8(0x8C) ++#define OCR1CH _SFR_MEM8(0x8D) ++ ++/* Timer/Counter3 Control Register A */ ++#define TCCR3A _SFR_MEM8(0x90) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TCCR3A { ++ unsigned int wgm3 : 2; /* Waveform Generation Mode */ ++ unsigned int com3c : 2; /* Compare Output Mode for Channel C */ ++ unsigned int com3b : 2; /* Compare Output Mode for Channel B */ ++ unsigned int com3a : 2; /* Compare Output Mode for Channel A */ ++}; ++ ++#define TCCR3A_struct _SFR_MEM8_STRUCT(0x90, struct __reg_TCCR3A) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TCCR3A */ ++ ++#define WGM30 0 ++#define WGM31 1 ++#define COM3C0 2 ++#define COM3C1 3 ++#define COM3B0 4 ++#define COM3B1 5 ++#define COM3A0 6 ++#define COM3A1 7 ++ ++/* Timer/Counter3 Control Register B */ ++#define TCCR3B _SFR_MEM8(0x91) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TCCR3B { ++ unsigned int cs3 : 3; /* Clock Select */ ++ unsigned int wgm3 : 2; /* Waveform Generation Mode */ ++ unsigned int : 1; ++ unsigned int ices3 : 1; /* Input Capture 3 Edge Select */ ++ unsigned int icnc3 : 1; /* Input Capture 3 Noise Canceller */ ++}; ++ ++#define TCCR3B_struct _SFR_MEM8_STRUCT(0x91, struct __reg_TCCR3B) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TCCR3B */ ++ ++#define CS30 0 ++#define CS31 1 ++#define CS32 2 ++#define WGM32 3 ++#define WGM33 4 ++#define ICES3 6 ++#define ICNC3 7 ++ ++/* Timer/Counter3 Control Register C */ ++#define TCCR3C _SFR_MEM8(0x92) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TCCR3C { ++ unsigned int : 5; ++ unsigned int foc3c : 1; /* Force Output Compare for Channel C */ ++ unsigned int foc3b : 1; /* Force Output Compare for Channel B */ ++ unsigned int foc3a : 1; /* Force Output Compare for Channel A */ ++}; ++ ++#define TCCR3C_struct _SFR_MEM8_STRUCT(0x92, struct __reg_TCCR3C) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TCCR3C */ ++ ++#define FOC3C 5 ++#define FOC3B 6 ++#define FOC3A 7 ++ ++/* Timer/Counter3 Bytes */ ++#define TCNT3 _SFR_MEM16(0x94) ++#define TCNT3L _SFR_MEM8(0x94) ++#define TCNT3H _SFR_MEM8(0x95) ++ ++/* Timer/Counter3 Input Capture Register Bytes */ ++#define ICR3 _SFR_MEM16(0x96) ++#define ICR3L _SFR_MEM8(0x96) ++#define ICR3H _SFR_MEM8(0x97) ++ ++/* Timer/Counter3 Output Compare Register A Bytes */ ++#define OCR3A _SFR_MEM16(0x98) ++#define OCR3AL _SFR_MEM8(0x98) ++#define OCR3AH _SFR_MEM8(0x99) ++ ++/* Timer/Counter3 Output Compare Register B Bytes */ ++#define OCR3B _SFR_MEM16(0x9A) ++#define OCR3BL _SFR_MEM8(0x9A) ++#define OCR3BH _SFR_MEM8(0x9B) ++ ++/* Timer/Counter3 Output Compare Register C Bytes */ ++#define OCR3C _SFR_MEM16(0x9C) ++#define OCR3CL _SFR_MEM8(0x9C) ++#define OCR3CH _SFR_MEM8(0x9D) ++ ++/* Timer/Counter4 Control Register A */ ++#define TCCR4A _SFR_MEM8(0xA0) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TCCR4A { ++ unsigned int wgm4 : 2; /* Waveform Generation Mode */ ++ unsigned int com4c : 2; /* Compare Output Mode for Channel C */ ++ unsigned int com4b : 2; /* Compare Output Mode for Channel B */ ++ unsigned int com4a : 2; /* Compare Output Mode for Channel A */ ++}; ++ ++#define TCCR4A_struct _SFR_MEM8_STRUCT(0xa0, struct __reg_TCCR4A) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TCCR4A */ ++ ++#define WGM40 0 ++#define WGM41 1 ++#define COM4C0 2 ++#define COM4C1 3 ++#define COM4B0 4 ++#define COM4B1 5 ++#define COM4A0 6 ++#define COM4A1 7 ++ ++/* Timer/Counter4 Control Register B */ ++#define TCCR4B _SFR_MEM8(0xA1) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TCCR4B { ++ unsigned int cs4 : 3; /* Clock Select */ ++ unsigned int wgm4 : 2; /* Waveform Generation Mode */ ++ unsigned int : 1; ++ unsigned int ices4 : 1; /* Input Capture 4 Edge Select */ ++ unsigned int icnc4 : 1; /* Input Capture 4 Noise Canceller */ ++}; ++ ++#define TCCR4B_struct _SFR_MEM8_STRUCT(0xa1, struct __reg_TCCR4B) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TCCR4B */ ++ ++#define CS40 0 ++#define CS41 1 ++#define CS42 2 ++#define WGM42 3 ++#define WGM43 4 ++#define ICES4 6 ++#define ICNC4 7 ++ ++/* Timer/Counter4 Control Register C */ ++#define TCCR4C _SFR_MEM8(0xA2) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TCCR4C { ++ unsigned int : 5; ++ unsigned int foc4c : 1; /* Force Output Compare for Channel C */ ++ unsigned int foc4b : 1; /* Force Output Compare for Channel B */ ++ unsigned int foc4a : 1; /* Force Output Compare for Channel A */ ++}; ++ ++#define TCCR4C_struct _SFR_MEM8_STRUCT(0xa2, struct __reg_TCCR4C) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TCCR4C */ ++ ++#define FOC4C 5 ++#define FOC4B 6 ++#define FOC4A 7 ++ ++/* Timer/Counter4 Bytes */ ++#define TCNT4 _SFR_MEM16(0xA4) ++#define TCNT4L _SFR_MEM8(0xA4) ++#define TCNT4H _SFR_MEM8(0xA5) ++ ++/* Timer/Counter4 Input Capture Register Bytes */ ++#define ICR4 _SFR_MEM16(0xA6) ++#define ICR4L _SFR_MEM8(0xA6) ++#define ICR4H _SFR_MEM8(0xA7) ++ ++/* Timer/Counter4 Output Compare Register A Bytes */ ++#define OCR4A _SFR_MEM16(0xA8) ++#define OCR4AL _SFR_MEM8(0xA8) ++#define OCR4AH _SFR_MEM8(0xA9) ++ ++/* Timer/Counter4 Output Compare Register B Bytes */ ++#define OCR4B _SFR_MEM16(0xAA) ++#define OCR4BL _SFR_MEM8(0xAA) ++#define OCR4BH _SFR_MEM8(0xAB) ++ ++/* Timer/Counter4 Output Compare Register C Bytes */ ++#define OCR4C _SFR_MEM16(0xAC) ++#define OCR4CL _SFR_MEM8(0xAC) ++#define OCR4CH _SFR_MEM8(0xAD) ++ ++/* Timer/Counter2 Control Register A */ ++#define TCCR2A _SFR_MEM8(0xB0) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TCCR2A { ++ unsigned int wgm2 : 2; /* Waveform Generation Mode */ ++ unsigned int : 2; ++ unsigned int com2b : 2; /* Compare Match Output B Mode */ ++ unsigned int com2a : 2; /* Compare Match Output A Mode */ ++}; ++ ++#define TCCR2A_struct _SFR_MEM8_STRUCT(0xb0, struct __reg_TCCR2A) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TCCR2A */ ++ ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++/* Timer/Counter2 Control Register B */ ++#define TCCR2B _SFR_MEM8(0xB1) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TCCR2B { ++ unsigned int cs2 : 3; /* Clock Select */ ++ unsigned int wgm22 : 1; /* Waveform Generation Mode */ ++ unsigned int : 2; ++ unsigned int foc2b : 1; /* Force Output Compare B */ ++ unsigned int foc2a : 1; /* Force Output Compare A */ ++}; ++ ++#define TCCR2B_struct _SFR_MEM8_STRUCT(0xb1, struct __reg_TCCR2B) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TCCR2B */ ++ ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++/* Timer/Counter2 */ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++ /* TCNT2 */ ++ ++#define TCNT20 0 ++#define TCNT21 1 ++#define TCNT22 2 ++#define TCNT23 3 ++#define TCNT24 4 ++#define TCNT25 5 ++#define TCNT26 6 ++#define TCNT27 7 ++ ++/* Timer/Counter2 Output Compare Register A */ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++ /* OCR2A */ ++ ++#define OCR2A0 0 ++#define OCR2A1 1 ++#define OCR2A2 2 ++#define OCR2A3 3 ++#define OCR2A4 4 ++#define OCR2A5 5 ++#define OCR2A6 6 ++#define OCR2A7 7 ++ ++/* Timer/Counter2 Output Compare Register B */ ++#define OCR2B _SFR_MEM8(0xB4) ++ ++ /* OCR2B */ ++ ++#define OCR2B0 0 ++#define OCR2B1 1 ++#define OCR2B2 2 ++#define OCR2B3 3 ++#define OCR2B4 4 ++#define OCR2B5 5 ++#define OCR2B6 6 ++#define OCR2B7 7 ++ ++/* Asynchronous Status Register */ ++#define ASSR _SFR_MEM8(0xB6) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_ASSR { ++ unsigned int tcr2bub : 1; /* Timer/Counter2 Control Register B Update Busy */ ++ unsigned int tcr2aub : 1; /* Timer/Counter2 Control Register A Update Busy */ ++ unsigned int ocr2bub : 1; /* Timer/Counter2 Output Compare Register B Update Busy */ ++ unsigned int ocr2aub : 1; /* Timer/Counter2 Output Compare Register A Update Busy */ ++ unsigned int tcn2ub : 1; /* Timer/Counter2 Update Busy */ ++ unsigned int as2 : 1; /* Timer/Counter2 Asynchronous Mode */ ++ unsigned int exclk : 1; /* Enable External Clock Input */ ++ unsigned int exclkamr : 1; /* Enable External Clock Input for AMR */ ++}; ++ ++#define ASSR_struct _SFR_MEM8_STRUCT(0xb6, struct __reg_ASSR) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* ASSR */ ++ ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++#define EXCLKAMR 7 ++ ++/* TWI Bit Rate Register */ ++#define TWBR _SFR_MEM8(0xB8) ++ ++ /* TWBR */ ++ ++#define TWBR0 0 ++#define TWBR1 1 ++#define TWBR2 2 ++#define TWBR3 3 ++#define TWBR4 4 ++#define TWBR5 5 ++#define TWBR6 6 ++#define TWBR7 7 ++ ++/* TWI Status Register */ ++#define TWSR _SFR_MEM8(0xB9) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TWSR { ++ unsigned int twps : 2; /* TWI Prescaler Bits */ ++ unsigned int : 1; ++ unsigned int tws : 5; /* TWI Status */ ++}; ++ ++#define TWSR_struct _SFR_MEM8_STRUCT(0xb9, struct __reg_TWSR) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TWSR */ ++ ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++/* TWI (Slave) Address Register */ ++#define TWAR _SFR_MEM8(0xBA) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TWAR { ++ unsigned int twgce : 1; /* TWI General Call Recognition Enable Bit */ ++ unsigned int twa : 7; /* TWI (Slave) Address */ ++}; ++ ++#define TWAR_struct _SFR_MEM8_STRUCT(0xba, struct __reg_TWAR) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TWAR */ ++ ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++/* TWI Data Register */ ++#define TWDR _SFR_MEM8(0xBB) ++ ++ /* TWDR */ ++ ++#define TWD0 0 ++#define TWD1 1 ++#define TWD2 2 ++#define TWD3 3 ++#define TWD4 4 ++#define TWD5 5 ++#define TWD6 6 ++#define TWD7 7 ++ ++/* TWI Control Register */ ++#define TWCR _SFR_MEM8(0xBC) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TWCR { ++ unsigned int twie : 1; /* TWI Interrupt Enable */ ++ unsigned int : 1; ++ unsigned int twen : 1; /* TWI Enable Bit */ ++ unsigned int twwc : 1; /* TWI Write Collision Flag */ ++ unsigned int twsto : 1; /* TWI STOP Condition Bit */ ++ unsigned int twsta : 1; /* TWI START Condition Bit */ ++ unsigned int twea : 1; /* TWI Enable Acknowledge Bit */ ++ unsigned int twint : 1; /* TWI Interrupt Flag */ ++}; ++ ++#define TWCR_struct _SFR_MEM8_STRUCT(0xbc, struct __reg_TWCR) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TWCR */ ++ ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++/* TWI (Slave) Address Mask Register */ ++#define TWAMR _SFR_MEM8(0xBD) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TWAMR { ++ unsigned int : 1; ++ unsigned int twam : 7; /* TWI Address Mask */ ++}; ++ ++#define TWAMR_struct _SFR_MEM8_STRUCT(0xbd, struct __reg_TWAMR) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TWAMR */ ++ ++#define TWAM0 1 ++#define TWAMR0 1 ++#define TWAM1 2 ++#define TWAMR1 2 ++#define TWAM2 3 ++#define TWAMR2 3 ++#define TWAM3 4 ++#define TWAMR3 4 ++#define TWAM4 5 ++#define TWAMR4 5 ++#define TWAM5 6 ++#define TWAMR5 6 ++#define TWAM6 7 ++#define TWAMR6 7 ++ ++/* USART0 Control and Status Register A */ ++#define UCSR0A _SFR_MEM8(0xC0) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_UCSR0A { ++ unsigned int mpcm0 : 1; /* Multi-processor Communication Mode */ ++ unsigned int u2x0 : 1; /* Double the USART Transmission Speed */ ++ unsigned int upe0 : 1; /* USART Parity Error */ ++ unsigned int dor0 : 1; /* Data OverRun */ ++ unsigned int fe0 : 1; /* Frame Error */ ++ unsigned int udre0 : 1; /* USART Data Register Empty */ ++ unsigned int txc0 : 1; /* USART Transmit Complete */ ++ unsigned int rxc0 : 1; /* USART Receive Complete */ ++}; ++ ++#define UCSR0A_struct _SFR_MEM8_STRUCT(0xc0, struct __reg_UCSR0A) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* UCSR0A */ ++ ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++/* USART0 Control and Status Register B */ ++#define UCSR0B _SFR_MEM8(0xC1) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_UCSR0B { ++ unsigned int txb80 : 1; /* Transmit Data Bit 8 */ ++ unsigned int rxb80 : 1; /* Receive Data Bit 8 */ ++ unsigned int ucsz02 : 1; /* Character Size */ ++ unsigned int txen0 : 1; /* Transmitter Enable */ ++ unsigned int rxen0 : 1; /* Receiver Enable */ ++ unsigned int udrie0 : 1; /* USART Data Register Empty Interrupt Enable */ ++ unsigned int txcie0 : 1; /* TX Complete Interrupt Enable */ ++ unsigned int rxcie0 : 1; /* RX Complete Interrupt Enable */ ++}; ++ ++#define UCSR0B_struct _SFR_MEM8_STRUCT(0xc1, struct __reg_UCSR0B) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* UCSR0B */ ++ ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++/* USART0 Control and Status Register C */ ++#define UCSR0C _SFR_MEM8(0xC2) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_UCSR0C { ++ unsigned int ucpol0 : 1; /* Clock Polarity */ ++ unsigned int ucsz0 : 2; /* Character Size */ ++ unsigned int ucpha0 : 1; /* Clock Phase */ ++ unsigned int udord0 : 1; /* Data Order */ ++ unsigned int usbs0 : 1; /* Stop Bit Select */ ++ unsigned int upm0 : 2; /* Parity Mode */ ++ unsigned int umsel0 : 2; /* USART Mode Select */ ++}; ++ ++#define UCSR0C_struct _SFR_MEM8_STRUCT(0xc2, struct __reg_UCSR0C) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* UCSR0C */ ++ ++#define UCPOL0 0 ++#define UCPHA0 1 ++#define UCPHA0 1 ++#define UCSZ00 1 ++#define UDORD0 2 ++#define UDORD0 2 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL0 6 ++#define UMSEL01 7 ++#define UMSEL1 7 ++ ++/* USART0 Baud Rate Register Bytes */ ++#define UBRR0 _SFR_MEM16(0xC4) ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++/* USART0 I/O Data Register */ ++#define UDR0 _SFR_MEM8(0xC6) ++ ++ /* UDR0 */ ++ ++#define UDR00 0 ++#define UDR01 1 ++#define UDR02 2 ++#define UDR03 3 ++#define UDR04 4 ++#define UDR05 5 ++#define UDR06 6 ++#define UDR07 7 ++ ++/* USART1 Control and Status Register A */ ++#define UCSR1A _SFR_MEM8(0xC8) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_UCSR1A { ++ unsigned int mpcm1 : 1; /* Multi-processor Communication Mode */ ++ unsigned int u2x1 : 1; /* Double the USART Transmission Speed */ ++ unsigned int upe1 : 1; /* USART Parity Error */ ++ unsigned int dor1 : 1; /* Data OverRun */ ++ unsigned int fe1 : 1; /* Frame Error */ ++ unsigned int udre1 : 1; /* USART Data Register Empty */ ++ unsigned int txc1 : 1; /* USART Transmit Complete */ ++ unsigned int rxc1 : 1; /* USART Receive Complete */ ++}; ++ ++#define UCSR1A_struct _SFR_MEM8_STRUCT(0xc8, struct __reg_UCSR1A) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* UCSR1A */ ++ ++#define MPCM1 0 ++#define U2X1 1 ++#define UPE1 2 ++#define DOR1 3 ++#define FE1 4 ++#define UDRE1 5 ++#define TXC1 6 ++#define RXC1 7 ++ ++/* USART1 Control and Status Register B */ ++#define UCSR1B _SFR_MEM8(0xC9) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_UCSR1B { ++ unsigned int txb81 : 1; /* Transmit Data Bit 8 */ ++ unsigned int rxb81 : 1; /* Receive Data Bit 8 */ ++ unsigned int ucsz12 : 1; /* Character Size */ ++ unsigned int txen1 : 1; /* Transmitter Enable */ ++ unsigned int rxen1 : 1; /* Receiver Enable */ ++ unsigned int udrie1 : 1; /* USART Data Register Empty Interrupt Enable */ ++ unsigned int txcie1 : 1; /* TX Complete Interrupt Enable */ ++ unsigned int rxcie1 : 1; /* RX Complete Interrupt Enable */ ++}; ++ ++#define UCSR1B_struct _SFR_MEM8_STRUCT(0xc9, struct __reg_UCSR1B) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* UCSR1B */ ++ ++#define TXB81 0 ++#define RXB81 1 ++#define UCSZ12 2 ++#define TXEN1 3 ++#define RXEN1 4 ++#define UDRIE1 5 ++#define TXCIE1 6 ++#define RXCIE1 7 ++ ++/* USART1 Control and Status Register C */ ++#define UCSR1C _SFR_MEM8(0xCA) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_UCSR1C { ++ unsigned int ucpol1 : 1; /* Clock Polarity */ ++ unsigned int ucsz1 : 2; /* Character Size */ ++ unsigned int ucpha1 : 1; /* Clock Phase */ ++ unsigned int udord1 : 1; /* Data Order */ ++ unsigned int usbs1 : 1; /* Stop Bit Select */ ++ unsigned int upm1 : 2; /* Parity Mode */ ++ unsigned int umsel1 : 2; /* USART Mode Select */ ++}; ++ ++#define UCSR1C_struct _SFR_MEM8_STRUCT(0xca, struct __reg_UCSR1C) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* UCSR1C */ ++ ++#define UCPOL1 0 ++#define UCPHA1 1 ++#define UCPHA1 1 ++#define UCSZ10 1 ++#define UDORD1 2 ++#define UDORD1 2 ++#define UCSZ11 2 ++#define USBS1 3 ++#define UPM10 4 ++#define UPM11 5 ++#define UMSEL10 6 ++#define UMSEL11 7 ++ ++/* USART1 Baud Rate Register Bytes */ ++#define UBRR1 _SFR_MEM16(0xCC) ++#define UBRR1L _SFR_MEM8(0xCC) ++#define UBRR1H _SFR_MEM8(0xCD) ++ ++/* USART1 I/O Data Register */ ++#define UDR1 _SFR_MEM8(0xCE) ++ ++ /* UDR1 */ ++ ++#define UDR10 0 ++#define UDR11 1 ++#define UDR12 2 ++#define UDR13 3 ++#define UDR14 4 ++#define UDR15 5 ++#define UDR16 6 ++#define UDR17 7 ++ ++/* Symbol Counter Control Register 0 */ ++#define SCCR0 _SFR_MEM8(0xDC) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCCR0 { ++ unsigned int sccmp : 3; /* Symbol Counter Compare Unit 3 Mode select */ ++ unsigned int sctse : 1; /* Symbol Counter Automatic Timestamping enable */ ++ unsigned int sccksel : 1; /* Symbol Counter Clock Source select */ ++ unsigned int scen : 1; /* Symbol Counter enable */ ++ unsigned int scmbts : 1; /* Manual Beacon Timestamp */ ++ unsigned int scres : 1; /* Symbol Counter Synchronization */ ++}; ++ ++#define SCCR0_struct _SFR_MEM8_STRUCT(0xdc, struct __reg_SCCR0) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCCR0 */ ++ ++#define SCCMP1 0 ++#define SCCMP2 1 ++#define SCCMP3 2 ++#define SCTSE 3 ++#define SCCKSEL 4 ++#define SCEN 5 ++#define SCMBTS 6 ++#define SCRES 7 ++ ++/* Symbol Counter Control Register 1 */ ++#define SCCR1 _SFR_MEM8(0xDD) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCCR1 { ++ unsigned int scenbo : 1; /* Backoff Slot Counter enable */ ++ unsigned int : 7; ++}; ++ ++#define SCCR1_struct _SFR_MEM8_STRUCT(0xdd, struct __reg_SCCR1) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCCR1 */ ++ ++#define SCENBO 0 ++ ++/* Symbol Counter Status Register */ ++#define SCSR _SFR_MEM8(0xDE) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCSR { ++ unsigned int scbsy : 1; /* Symbol Counter busy */ ++ unsigned int : 7; ++}; ++ ++#define SCSR_struct _SFR_MEM8_STRUCT(0xde, struct __reg_SCSR) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCSR */ ++ ++#define SCBSY 0 ++ ++/* Symbol Counter Interrupt Mask Register */ ++#define SCIRQM _SFR_MEM8(0xDF) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCIRQM { ++ unsigned int irqmcp : 3; /* Symbol Counter Compare Match 3 IRQ enable */ ++ unsigned int irqmof : 1; /* Symbol Counter Overflow IRQ enable */ ++ unsigned int irqmbo : 1; /* Backoff Slot Counter IRQ enable */ ++ unsigned int : 3; ++}; ++ ++#define SCIRQM_struct _SFR_MEM8_STRUCT(0xdf, struct __reg_SCIRQM) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCIRQM */ ++ ++#define IRQMCP1 0 ++#define IRQMCP2 1 ++#define IRQMCP3 2 ++#define IRQMOF 3 ++#define IRQMBO 4 ++ ++/* Symbol Counter Interrupt Status Register */ ++#define SCIRQS _SFR_MEM8(0xE0) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCIRQS { ++ unsigned int irqscp : 3; /* Compare Unit 3 Compare Match IRQ */ ++ unsigned int irqsof : 1; /* Symbol Counter Overflow IRQ */ ++ unsigned int irqsbo : 1; /* Backoff Slot Counter IRQ */ ++ unsigned int : 3; ++}; ++ ++#define SCIRQS_struct _SFR_MEM8_STRUCT(0xe0, struct __reg_SCIRQS) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCIRQS */ ++ ++#define IRQSCP1 0 ++#define IRQSCP2 1 ++#define IRQSCP3 2 ++#define IRQSOF 3 ++#define IRQSBO 4 ++ ++/* Symbol Counter Register LL-Byte */ ++#define SCCNTLL _SFR_MEM8(0xE1) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCCNTLL { ++ unsigned int sccntll : 8; /* Symbol Counter Register LL-Byte */ ++}; ++ ++#define SCCNTLL_struct _SFR_MEM8_STRUCT(0xe1, struct __reg_SCCNTLL) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCCNTLL */ ++ ++#define SCCNTLL0 0 ++#define SCCNTLL1 1 ++#define SCCNTLL2 2 ++#define SCCNTLL3 3 ++#define SCCNTLL4 4 ++#define SCCNTLL5 5 ++#define SCCNTLL6 6 ++#define SCCNTLL7 7 ++ ++/* Symbol Counter Register LH-Byte */ ++#define SCCNTLH _SFR_MEM8(0xE2) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCCNTLH { ++ unsigned int sccntlh : 8; /* Symbol Counter Register LH-Byte */ ++}; ++ ++#define SCCNTLH_struct _SFR_MEM8_STRUCT(0xe2, struct __reg_SCCNTLH) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCCNTLH */ ++ ++#define SCCNTLH0 0 ++#define SCCNTLH1 1 ++#define SCCNTLH2 2 ++#define SCCNTLH3 3 ++#define SCCNTLH4 4 ++#define SCCNTLH5 5 ++#define SCCNTLH6 6 ++#define SCCNTLH7 7 ++ ++/* Symbol Counter Register HL-Byte */ ++#define SCCNTHL _SFR_MEM8(0xE3) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCCNTHL { ++ unsigned int sccnthl : 8; /* Symbol Counter Register HL-Byte */ ++}; ++ ++#define SCCNTHL_struct _SFR_MEM8_STRUCT(0xe3, struct __reg_SCCNTHL) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCCNTHL */ ++ ++#define SCCNTHL0 0 ++#define SCCNTHL1 1 ++#define SCCNTHL2 2 ++#define SCCNTHL3 3 ++#define SCCNTHL4 4 ++#define SCCNTHL5 5 ++#define SCCNTHL6 6 ++#define SCCNTHL7 7 ++ ++/* Symbol Counter Register HH-Byte */ ++#define SCCNTHH _SFR_MEM8(0xE4) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCCNTHH { ++ unsigned int sccnthh : 8; /* Symbol Counter Register HH-Byte */ ++}; ++ ++#define SCCNTHH_struct _SFR_MEM8_STRUCT(0xe4, struct __reg_SCCNTHH) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCCNTHH */ ++ ++#define SCCNTHH0 0 ++#define SCCNTHH1 1 ++#define SCCNTHH2 2 ++#define SCCNTHH3 3 ++#define SCCNTHH4 4 ++#define SCCNTHH5 5 ++#define SCCNTHH6 6 ++#define SCCNTHH7 7 ++ ++/* Symbol Counter Beacon Timestamp Register LL-Byte */ ++#define SCBTSRLL _SFR_MEM8(0xE5) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCBTSRLL { ++ unsigned int scbtsrll : 8; /* Symbol Counter Beacon Timestamp Register LL-Byte */ ++}; ++ ++#define SCBTSRLL_struct _SFR_MEM8_STRUCT(0xe5, struct __reg_SCBTSRLL) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCBTSRLL */ ++ ++#define SCBTSRLL0 0 ++#define SCBTSRLL1 1 ++#define SCBTSRLL2 2 ++#define SCBTSRLL3 3 ++#define SCBTSRLL4 4 ++#define SCBTSRLL5 5 ++#define SCBTSRLL6 6 ++#define SCBTSRLL7 7 ++ ++/* Symbol Counter Beacon Timestamp Register LH-Byte */ ++#define SCBTSRLH _SFR_MEM8(0xE6) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCBTSRLH { ++ unsigned int scbtsrlh : 8; /* Symbol Counter Beacon Timestamp Register LH-Byte */ ++}; ++ ++#define SCBTSRLH_struct _SFR_MEM8_STRUCT(0xe6, struct __reg_SCBTSRLH) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCBTSRLH */ ++ ++#define SCBTSRLH0 0 ++#define SCBTSRLH1 1 ++#define SCBTSRLH2 2 ++#define SCBTSRLH3 3 ++#define SCBTSRLH4 4 ++#define SCBTSRLH5 5 ++#define SCBTSRLH6 6 ++#define SCBTSRLH7 7 ++ ++/* Symbol Counter Beacon Timestamp Register HL-Byte */ ++#define SCBTSRHL _SFR_MEM8(0xE7) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCBTSRHL { ++ unsigned int scbtsrhl : 8; /* Symbol Counter Beacon Timestamp Register HL-Byte */ ++}; ++ ++#define SCBTSRHL_struct _SFR_MEM8_STRUCT(0xe7, struct __reg_SCBTSRHL) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCBTSRHL */ ++ ++#define SCBTSRHL0 0 ++#define SCBTSRHL1 1 ++#define SCBTSRHL2 2 ++#define SCBTSRHL3 3 ++#define SCBTSRHL4 4 ++#define SCBTSRHL5 5 ++#define SCBTSRHL6 6 ++#define SCBTSRHL7 7 ++ ++/* Symbol Counter Beacon Timestamp Register HH-Byte */ ++#define SCBTSRHH _SFR_MEM8(0xE8) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCBTSRHH { ++ unsigned int scbtsrhh : 8; /* Symbol Counter Beacon Timestamp Register HH-Byte */ ++}; ++ ++#define SCBTSRHH_struct _SFR_MEM8_STRUCT(0xe8, struct __reg_SCBTSRHH) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCBTSRHH */ ++ ++#define SCBTSRHH0 0 ++#define SCBTSRHH1 1 ++#define SCBTSRHH2 2 ++#define SCBTSRHH3 3 ++#define SCBTSRHH4 4 ++#define SCBTSRHH5 5 ++#define SCBTSRHH6 6 ++#define SCBTSRHH7 7 ++ ++/* Symbol Counter Frame Timestamp Register LL-Byte */ ++#define SCTSRLL _SFR_MEM8(0xE9) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCTSRLL { ++ unsigned int sctsrll : 8; /* Symbol Counter Frame Timestamp Register LL-Byte */ ++}; ++ ++#define SCTSRLL_struct _SFR_MEM8_STRUCT(0xe9, struct __reg_SCTSRLL) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCTSRLL */ ++ ++#define SCTSRLL0 0 ++#define SCTSRLL1 1 ++#define SCTSRLL2 2 ++#define SCTSRLL3 3 ++#define SCTSRLL4 4 ++#define SCTSRLL5 5 ++#define SCTSRLL6 6 ++#define SCTSRLL7 7 ++ ++/* Symbol Counter Frame Timestamp Register LH-Byte */ ++#define SCTSRLH _SFR_MEM8(0xEA) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCTSRLH { ++ unsigned int sctsrlh : 8; /* Symbol Counter Frame Timestamp Register LH-Byte */ ++}; ++ ++#define SCTSRLH_struct _SFR_MEM8_STRUCT(0xea, struct __reg_SCTSRLH) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCTSRLH */ ++ ++#define SCTSRLH0 0 ++#define SCTSRLH1 1 ++#define SCTSRLH2 2 ++#define SCTSRLH3 3 ++#define SCTSRLH4 4 ++#define SCTSRLH5 5 ++#define SCTSRLH6 6 ++#define SCTSRLH7 7 ++ ++/* Symbol Counter Frame Timestamp Register HL-Byte */ ++#define SCTSRHL _SFR_MEM8(0xEB) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCTSRHL { ++ unsigned int sctsrhl : 8; /* Symbol Counter Frame Timestamp Register HL-Byte */ ++}; ++ ++#define SCTSRHL_struct _SFR_MEM8_STRUCT(0xeb, struct __reg_SCTSRHL) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCTSRHL */ ++ ++#define SCTSRHL0 0 ++#define SCTSRHL1 1 ++#define SCTSRHL2 2 ++#define SCTSRHL3 3 ++#define SCTSRHL4 4 ++#define SCTSRHL5 5 ++#define SCTSRHL6 6 ++#define SCTSRHL7 7 ++ ++/* Symbol Counter Frame Timestamp Register HH-Byte */ ++#define SCTSRHH _SFR_MEM8(0xEC) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCTSRHH { ++ unsigned int sctsrhh : 8; /* Symbol Counter Frame Timestamp Register HH-Byte */ ++}; ++ ++#define SCTSRHH_struct _SFR_MEM8_STRUCT(0xec, struct __reg_SCTSRHH) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCTSRHH */ ++ ++#define SCTSRHH0 0 ++#define SCTSRHH1 1 ++#define SCTSRHH2 2 ++#define SCTSRHH3 3 ++#define SCTSRHH4 4 ++#define SCTSRHH5 5 ++#define SCTSRHH6 6 ++#define SCTSRHH7 7 ++ ++/* Symbol Counter Output Compare Register 3 LL-Byte */ ++#define SCOCR3LL _SFR_MEM8(0xED) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCOCR3LL { ++ unsigned int scocr3ll : 8; /* Symbol Counter Output Compare Register 3 LL-Byte */ ++}; ++ ++#define SCOCR3LL_struct _SFR_MEM8_STRUCT(0xed, struct __reg_SCOCR3LL) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCOCR3LL */ ++ ++#define SCOCR3LL0 0 ++#define SCOCR3LL1 1 ++#define SCOCR3LL2 2 ++#define SCOCR3LL3 3 ++#define SCOCR3LL4 4 ++#define SCOCR3LL5 5 ++#define SCOCR3LL6 6 ++#define SCOCR3LL7 7 ++ ++/* Symbol Counter Output Compare Register 3 LH-Byte */ ++#define SCOCR3LH _SFR_MEM8(0xEE) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCOCR3LH { ++ unsigned int scocr3lh : 8; /* Symbol Counter Output Compare Register 3 LH-Byte */ ++}; ++ ++#define SCOCR3LH_struct _SFR_MEM8_STRUCT(0xee, struct __reg_SCOCR3LH) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCOCR3LH */ ++ ++#define SCOCR3LH0 0 ++#define SCOCR3LH1 1 ++#define SCOCR3LH2 2 ++#define SCOCR3LH3 3 ++#define SCOCR3LH4 4 ++#define SCOCR3LH5 5 ++#define SCOCR3LH6 6 ++#define SCOCR3LH7 7 ++ ++/* Symbol Counter Output Compare Register 3 HL-Byte */ ++#define SCOCR3HL _SFR_MEM8(0xEF) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCOCR3HL { ++ unsigned int scocr3hl : 8; /* Symbol Counter Output Compare Register 3 HL-Byte */ ++}; ++ ++#define SCOCR3HL_struct _SFR_MEM8_STRUCT(0xef, struct __reg_SCOCR3HL) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCOCR3HL */ ++ ++#define SCOCR3HL0 0 ++#define SCOCR3HL1 1 ++#define SCOCR3HL2 2 ++#define SCOCR3HL3 3 ++#define SCOCR3HL4 4 ++#define SCOCR3HL5 5 ++#define SCOCR3HL6 6 ++#define SCOCR3HL7 7 ++ ++/* Symbol Counter Output Compare Register 3 HH-Byte */ ++#define SCOCR3HH _SFR_MEM8(0xF0) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCOCR3HH { ++ unsigned int scocr3hh : 8; /* Symbol Counter Output Compare Register 3 HH-Byte */ ++}; ++ ++#define SCOCR3HH_struct _SFR_MEM8_STRUCT(0xf0, struct __reg_SCOCR3HH) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCOCR3HH */ ++ ++#define SCOCR3HH0 0 ++#define SCOCR3HH1 1 ++#define SCOCR3HH2 2 ++#define SCOCR3HH3 3 ++#define SCOCR3HH4 4 ++#define SCOCR3HH5 5 ++#define SCOCR3HH6 6 ++#define SCOCR3HH7 7 ++ ++/* Symbol Counter Output Compare Register 2 LL-Byte */ ++#define SCOCR2LL _SFR_MEM8(0xF1) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCOCR2LL { ++ unsigned int scocr2ll : 8; /* Symbol Counter Output Compare Register 2 LL-Byte */ ++}; ++ ++#define SCOCR2LL_struct _SFR_MEM8_STRUCT(0xf1, struct __reg_SCOCR2LL) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCOCR2LL */ ++ ++#define SCOCR2LL0 0 ++#define SCOCR2LL1 1 ++#define SCOCR2LL2 2 ++#define SCOCR2LL3 3 ++#define SCOCR2LL4 4 ++#define SCOCR2LL5 5 ++#define SCOCR2LL6 6 ++#define SCOCR2LL7 7 ++ ++/* Symbol Counter Output Compare Register 2 LH-Byte */ ++#define SCOCR2LH _SFR_MEM8(0xF2) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCOCR2LH { ++ unsigned int scocr2lh : 8; /* Symbol Counter Output Compare Register 2 LH-Byte */ ++}; ++ ++#define SCOCR2LH_struct _SFR_MEM8_STRUCT(0xf2, struct __reg_SCOCR2LH) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCOCR2LH */ ++ ++#define SCOCR2LH0 0 ++#define SCOCR2LH1 1 ++#define SCOCR2LH2 2 ++#define SCOCR2LH3 3 ++#define SCOCR2LH4 4 ++#define SCOCR2LH5 5 ++#define SCOCR2LH6 6 ++#define SCOCR2LH7 7 ++ ++/* Symbol Counter Output Compare Register 2 HL-Byte */ ++#define SCOCR2HL _SFR_MEM8(0xF3) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCOCR2HL { ++ unsigned int scocr2hl : 8; /* Symbol Counter Output Compare Register 2 HL-Byte */ ++}; ++ ++#define SCOCR2HL_struct _SFR_MEM8_STRUCT(0xf3, struct __reg_SCOCR2HL) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCOCR2HL */ ++ ++#define SCOCR2HL0 0 ++#define SCOCR2HL1 1 ++#define SCOCR2HL2 2 ++#define SCOCR2HL3 3 ++#define SCOCR2HL4 4 ++#define SCOCR2HL5 5 ++#define SCOCR2HL6 6 ++#define SCOCR2HL7 7 ++ ++/* Symbol Counter Output Compare Register 2 HH-Byte */ ++#define SCOCR2HH _SFR_MEM8(0xF4) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCOCR2HH { ++ unsigned int scocr2hh : 8; /* Symbol Counter Output Compare Register 2 HH-Byte */ ++}; ++ ++#define SCOCR2HH_struct _SFR_MEM8_STRUCT(0xf4, struct __reg_SCOCR2HH) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCOCR2HH */ ++ ++#define SCOCR2HH0 0 ++#define SCOCR2HH1 1 ++#define SCOCR2HH2 2 ++#define SCOCR2HH3 3 ++#define SCOCR2HH4 4 ++#define SCOCR2HH5 5 ++#define SCOCR2HH6 6 ++#define SCOCR2HH7 7 ++ ++/* Symbol Counter Output Compare Register 1 LL-Byte */ ++#define SCOCR1LL _SFR_MEM8(0xF5) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCOCR1LL { ++ unsigned int scocr1ll : 8; /* Symbol Counter Output Compare Register 1 LL-Byte */ ++}; ++ ++#define SCOCR1LL_struct _SFR_MEM8_STRUCT(0xf5, struct __reg_SCOCR1LL) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCOCR1LL */ ++ ++#define SCOCR1LL0 0 ++#define SCOCR1LL1 1 ++#define SCOCR1LL2 2 ++#define SCOCR1LL3 3 ++#define SCOCR1LL4 4 ++#define SCOCR1LL5 5 ++#define SCOCR1LL6 6 ++#define SCOCR1LL7 7 ++ ++/* Symbol Counter Output Compare Register 1 LH-Byte */ ++#define SCOCR1LH _SFR_MEM8(0xF6) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCOCR1LH { ++ unsigned int scocr1lh : 8; /* Symbol Counter Output Compare Register 1 LH-Byte */ ++}; ++ ++#define SCOCR1LH_struct _SFR_MEM8_STRUCT(0xf6, struct __reg_SCOCR1LH) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCOCR1LH */ ++ ++#define SCOCR1LH0 0 ++#define SCOCR1LH1 1 ++#define SCOCR1LH2 2 ++#define SCOCR1LH3 3 ++#define SCOCR1LH4 4 ++#define SCOCR1LH5 5 ++#define SCOCR1LH6 6 ++#define SCOCR1LH7 7 ++ ++/* Symbol Counter Output Compare Register 1 HL-Byte */ ++#define SCOCR1HL _SFR_MEM8(0xF7) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCOCR1HL { ++ unsigned int scocr1hl : 8; /* Symbol Counter Output Compare Register 1 HL-Byte */ ++}; ++ ++#define SCOCR1HL_struct _SFR_MEM8_STRUCT(0xf7, struct __reg_SCOCR1HL) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCOCR1HL */ ++ ++#define SCOCR1HL0 0 ++#define SCOCR1HL1 1 ++#define SCOCR1HL2 2 ++#define SCOCR1HL3 3 ++#define SCOCR1HL4 4 ++#define SCOCR1HL5 5 ++#define SCOCR1HL6 6 ++#define SCOCR1HL7 7 ++ ++/* Symbol Counter Output Compare Register 1 HH-Byte */ ++#define SCOCR1HH _SFR_MEM8(0xF8) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SCOCR1HH { ++ unsigned int scocr1hh : 8; /* Symbol Counter Output Compare Register 1 HH-Byte */ ++}; ++ ++#define SCOCR1HH_struct _SFR_MEM8_STRUCT(0xf8, struct __reg_SCOCR1HH) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SCOCR1HH */ ++ ++#define SCOCR1HH0 0 ++#define SCOCR1HH1 1 ++#define SCOCR1HH2 2 ++#define SCOCR1HH3 3 ++#define SCOCR1HH4 4 ++#define SCOCR1HH5 5 ++#define SCOCR1HH6 6 ++#define SCOCR1HH7 7 ++ ++/* Timer/Counter5 Control Register A */ ++#define TCCR5A _SFR_MEM8(0x120) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TCCR5A { ++ unsigned int wgm5 : 2; /* Waveform Generation Mode */ ++ unsigned int com5c : 2; /* Compare Output Mode for Channel C */ ++ unsigned int com5b : 2; /* Compare Output Mode for Channel B */ ++ unsigned int com5a : 2; /* Compare Output Mode for Channel A */ ++}; ++ ++#define TCCR5A_struct _SFR_MEM8_STRUCT(0x120, struct __reg_TCCR5A) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TCCR5A */ ++ ++#define WGM50 0 ++#define WGM51 1 ++#define COM5C0 2 ++#define COM5C1 3 ++#define COM5B0 4 ++#define COM5B1 5 ++#define COM5A0 6 ++#define COM5A1 7 ++ ++/* Timer/Counter5 Control Register B */ ++#define TCCR5B _SFR_MEM8(0x121) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TCCR5B { ++ unsigned int cs5 : 3; /* Clock Select */ ++ unsigned int wgm5 : 2; /* Waveform Generation Mode */ ++ unsigned int : 1; ++ unsigned int ices5 : 1; /* Input Capture 5 Edge Select */ ++ unsigned int icnc5 : 1; /* Input Capture 5 Noise Canceller */ ++}; ++ ++#define TCCR5B_struct _SFR_MEM8_STRUCT(0x121, struct __reg_TCCR5B) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TCCR5B */ ++ ++#define CS50 0 ++#define CS51 1 ++#define CS52 2 ++#define WGM52 3 ++#define WGM53 4 ++#define ICES5 6 ++#define ICNC5 7 ++ ++/* Timer/Counter5 Control Register C */ ++#define TCCR5C _SFR_MEM8(0x122) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TCCR5C { ++ unsigned int : 5; ++ unsigned int foc5c : 1; /* Force Output Compare for Channel C */ ++ unsigned int foc5b : 1; /* Force Output Compare for Channel B */ ++ unsigned int foc5a : 1; /* Force Output Compare for Channel A */ ++}; ++ ++#define TCCR5C_struct _SFR_MEM8_STRUCT(0x122, struct __reg_TCCR5C) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TCCR5C */ ++ ++#define FOC5C 5 ++#define FOC5B 6 ++#define FOC5A 7 ++ ++/* Timer/Counter5 Bytes */ ++#define TCNT5 _SFR_MEM16(0x124) ++#define TCNT5L _SFR_MEM8(0x124) ++#define TCNT5H _SFR_MEM8(0x125) ++ ++/* Timer/Counter5 Input Capture Register Bytes */ ++#define ICR5 _SFR_MEM16(0x126) ++#define ICR5L _SFR_MEM8(0x126) ++#define ICR5H _SFR_MEM8(0x127) ++ ++/* Timer/Counter5 Output Compare Register A Bytes */ ++#define OCR5A _SFR_MEM16(0x128) ++#define OCR5AL _SFR_MEM8(0x128) ++#define OCR5AH _SFR_MEM8(0x129) ++ ++/* Timer/Counter5 Output Compare Register B Bytes */ ++#define OCR5B _SFR_MEM16(0x12A) ++#define OCR5BL _SFR_MEM8(0x12A) ++#define OCR5BH _SFR_MEM8(0x12B) ++ ++/* Timer/Counter5 Output Compare Register C Bytes */ ++#define OCR5C _SFR_MEM16(0x12C) ++#define OCR5CL _SFR_MEM8(0x12C) ++#define OCR5CH _SFR_MEM8(0x12D) ++ ++/* Low Leakage Voltage Regulator Control Register */ ++#define LLCR _SFR_MEM8(0x12F) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_LLCR { ++ unsigned int llencal : 1; /* Enable Automatic Calibration */ ++ unsigned int llshort : 1; /* Short Lower Calibration Circuit */ ++ unsigned int lltco : 1; /* Temperature Coefficient of Current Source */ ++ unsigned int llcal : 1; /* Calibration Active */ ++ unsigned int llcomp : 1; /* Comparator Output */ ++ unsigned int lldone : 1; /* Calibration Done */ ++ unsigned int : 2; ++}; ++ ++#define LLCR_struct _SFR_MEM8_STRUCT(0x12f, struct __reg_LLCR) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* LLCR */ ++ ++#define LLENCAL 0 ++#define LLSHORT 1 ++#define LLTCO 2 ++#define LLCAL 3 ++#define LLCOMP 4 ++#define LLDONE 5 ++ ++/* Low Leakage Voltage Regulator Data Register (Low-Byte) */ ++#define LLDRL _SFR_MEM8(0x130) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_LLDRL { ++ unsigned int lldrl : 4; /* Low-Byte Data Register Bits */ ++ unsigned int : 4; ++}; ++ ++#define LLDRL_struct _SFR_MEM8_STRUCT(0x130, struct __reg_LLDRL) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* LLDRL */ ++ ++#define LLDRL0 0 ++#define LLDRL1 1 ++#define LLDRL2 2 ++#define LLDRL3 3 ++ ++/* Low Leakage Voltage Regulator Data Register (High-Byte) */ ++#define LLDRH _SFR_MEM8(0x131) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_LLDRH { ++ unsigned int lldrh : 5; /* High-Byte Data Register Bits */ ++ unsigned int : 3; ++}; ++ ++#define LLDRH_struct _SFR_MEM8_STRUCT(0x131, struct __reg_LLDRH) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* LLDRH */ ++ ++#define LLDRH0 0 ++#define LLDRH1 1 ++#define LLDRH2 2 ++#define LLDRH3 3 ++#define LLDRH4 4 ++ ++/* Data Retention Configuration Register of SRAM 3 */ ++#define DRTRAM3 _SFR_MEM8(0x132) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_DRTRAM3 { ++ unsigned int : 4; ++ unsigned int endrt : 1; /* Enable SRAM Data Retention */ ++ unsigned int drtswok : 1; /* DRT Switch OK */ ++ unsigned int : 2; ++}; ++ ++#define DRTRAM3_struct _SFR_MEM8_STRUCT(0x132, struct __reg_DRTRAM3) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* DRTRAM3 */ ++ ++#define ENDRT 4 ++#define DRTSWOK 5 ++ ++/* Data Retention Configuration Register of SRAM 2 */ ++#define DRTRAM2 _SFR_MEM8(0x133) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_DRTRAM2 { ++ unsigned int : 4; ++ unsigned int endrt : 1; /* Enable SRAM Data Retention */ ++ unsigned int drtswok : 1; /* DRT Switch OK */ ++ unsigned int : 2; ++}; ++ ++#define DRTRAM2_struct _SFR_MEM8_STRUCT(0x133, struct __reg_DRTRAM2) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* DRTRAM2 */ ++ ++#define ENDRT 4 ++#define DRTSWOK 5 ++ ++/* Data Retention Configuration Register of SRAM 1 */ ++#define DRTRAM1 _SFR_MEM8(0x134) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_DRTRAM1 { ++ unsigned int : 4; ++ unsigned int endrt : 1; /* Enable SRAM Data Retention */ ++ unsigned int drtswok : 1; /* DRT Switch OK */ ++ unsigned int : 2; ++}; ++ ++#define DRTRAM1_struct _SFR_MEM8_STRUCT(0x134, struct __reg_DRTRAM1) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* DRTRAM1 */ ++ ++#define ENDRT 4 ++#define DRTSWOK 5 ++ ++/* Data Retention Configuration Register of SRAM 0 */ ++#define DRTRAM0 _SFR_MEM8(0x135) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_DRTRAM0 { ++ unsigned int : 4; ++ unsigned int endrt : 1; /* Enable SRAM Data Retention */ ++ unsigned int drtswok : 1; /* DRT Switch OK */ ++ unsigned int : 2; ++}; ++ ++#define DRTRAM0_struct _SFR_MEM8_STRUCT(0x135, struct __reg_DRTRAM0) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* DRTRAM0 */ ++ ++#define ENDRT 4 ++#define DRTSWOK 5 ++ ++/* Port Driver Strength Register 0 */ ++#define DPDS0 _SFR_MEM8(0x136) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_DPDS0 { ++ unsigned int pbdrv : 2; /* Driver Strength Port B */ ++ unsigned int pddrv : 2; /* Driver Strength Port D */ ++ unsigned int pedrv : 2; /* Driver Strength Port E */ ++ unsigned int pfdrv : 2; /* Driver Strength Port F */ ++}; ++ ++#define DPDS0_struct _SFR_MEM8_STRUCT(0x136, struct __reg_DPDS0) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* DPDS0 */ ++ ++#define PBDRV0 0 ++#define PBDRV1 1 ++#define PDDRV0 2 ++#define PDDRV1 3 ++#define PEDRV0 4 ++#define PEDRV1 5 ++#define PFDRV0 6 ++#define PFDRV1 7 ++ ++/* Port Driver Strength Register 1 */ ++#define DPDS1 _SFR_MEM8(0x137) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_DPDS1 { ++ unsigned int pgdrv : 2; /* Driver Strength Port G */ ++ unsigned int : 6; ++}; ++ ++#define DPDS1_struct _SFR_MEM8_STRUCT(0x137, struct __reg_DPDS1) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* DPDS1 */ ++ ++#define PGDRV0 0 ++#define PGDRV1 1 ++ ++/* Transceiver Pin Register */ ++#define TRXPR _SFR_MEM8(0x139) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TRXPR { ++ unsigned int trxrst : 1; /* Force Transceiver Reset */ ++ unsigned int slptr : 1; /* Multi-purpose Transceiver Control Bit */ ++ unsigned int : 6; ++}; ++ ++#define TRXPR_struct _SFR_MEM8_STRUCT(0x139, struct __reg_TRXPR) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TRXPR */ ++ ++#define TRXRST 0 ++#define SLPTR 1 ++ ++/* AES Control Register */ ++#define AES_CTRL _SFR_MEM8(0x13C) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_AES_CTRL { ++ unsigned int : 2; ++ unsigned int aes_im : 1; /* AES Interrupt Enable */ ++ unsigned int aes_dir : 1; /* Set AES Operation Direction */ ++ unsigned int : 1; ++ unsigned int aes_mode : 1; /* Set AES Operation Mode */ ++ unsigned int : 1; ++ unsigned int aes_request : 1; /* Request AES Operation. */ ++}; ++ ++#define AES_CTRL_struct _SFR_MEM8_STRUCT(0x13c, struct __reg_AES_CTRL) ++ ++/* symbolic names */ ++ ++#define AES_DIR_ENC 0 ++#define AES_DIR_DEC 1 ++#define AES_MODE_ECB 0 ++#define AES_MODE_CBC 1 ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* AES_CTRL */ ++ ++#define AES_IM 2 ++#define AES_DIR 3 ++#define AES_MODE 5 ++#define AES_REQUEST 7 ++ ++/* AES Status Register */ ++#define AES_STATUS _SFR_MEM8(0x13D) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_AES_STATUS { ++ unsigned int aes_done : 1; /* AES Operation Finished with Success */ ++ unsigned int : 6; ++ unsigned int aes_er : 1; /* AES Operation Finished with Error */ ++}; ++ ++#define AES_STATUS_struct _SFR_MEM8_STRUCT(0x13d, struct __reg_AES_STATUS) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* AES_STATUS */ ++ ++#define AES_DONE 0 ++#define AES_ER 7 ++ ++/* AES Plain and Cipher Text Buffer Register */ ++#define AES_STATE _SFR_MEM8(0x13E) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_AES_STATE { ++ unsigned int aes_state : 8; /* AES Plain and Cipher Text Buffer */ ++}; ++ ++#define AES_STATE_struct _SFR_MEM8_STRUCT(0x13e, struct __reg_AES_STATE) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* AES_STATE */ ++ ++#define AES_STATE0 0 ++#define AES_STATE1 1 ++#define AES_STATE2 2 ++#define AES_STATE3 3 ++#define AES_STATE4 4 ++#define AES_STATE5 5 ++#define AES_STATE6 6 ++#define AES_STATE7 7 ++ ++/* AES Encryption and Decryption Key Buffer Register */ ++#define AES_KEY _SFR_MEM8(0x13F) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_AES_KEY { ++ unsigned int aes_key : 8; /* AES Encryption/Decryption Key Buffer */ ++}; ++ ++#define AES_KEY_struct _SFR_MEM8_STRUCT(0x13f, struct __reg_AES_KEY) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* AES_KEY */ ++ ++#define AES_KEY0 0 ++#define AES_KEY1 1 ++#define AES_KEY2 2 ++#define AES_KEY3 3 ++#define AES_KEY4 4 ++#define AES_KEY5 5 ++#define AES_KEY6 6 ++#define AES_KEY7 7 ++ ++/* Transceiver Status Register */ ++#define TRX_STATUS _SFR_MEM8(0x141) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TRX_STATUS { ++ unsigned int trx_status : 5; /* Transceiver Main Status */ ++ unsigned int tst_status : 1; /* Test mode status */ ++ unsigned int cca_status : 1; /* CCA Status Result */ ++ unsigned int cca_done : 1; /* CCA Algorithm Status */ ++}; ++ ++#define TRX_STATUS_struct _SFR_MEM8_STRUCT(0x141, struct __reg_TRX_STATUS) ++ ++/* symbolic names */ ++ ++#define P_ON 0 ++#define BUSY_RX 1 ++#define BUSY_TX 2 ++#define RX_ON 6 ++#define TRX_OFF 8 ++#define PLL_ON 9 ++#define SLEEP 15 ++#define BUSY_RX_AACK 17 ++#define BUSY_TX_ARET 18 ++#define RX_AACK_ON 22 ++#define TX_ARET_ON 25 ++#define STATE_TRANSITION_IN_PROGRESS 31 ++#define TST_DISABLED 0 ++#define TST_ENABLED 1 ++#define CCA_BUSY 0 ++#define CCA_IDLE 1 ++#define CCA_NOT_FIN 0 ++#define CCA_FIN 1 ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TRX_STATUS */ ++ ++#define TRX_STATUS0 0 ++#define TRX_STATUS1 1 ++#define TRX_STATUS2 2 ++#define TRX_STATUS3 3 ++#define TRX_STATUS4 4 ++#define TST_STATUS 5 ++#define CCA_STATUS 6 ++#define CCA_DONE 7 ++ ++/* Transceiver State Control Register */ ++#define TRX_STATE _SFR_MEM8(0x142) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TRX_STATE { ++ unsigned int trx_cmd : 5; /* State Control Command */ ++ unsigned int trac_status : 3; /* Transaction Status */ ++}; ++ ++#define TRX_STATE_struct _SFR_MEM8_STRUCT(0x142, struct __reg_TRX_STATE) ++ ++/* symbolic names */ ++ ++#define CMD_NOP 0 ++#define CMD_TX_START 2 ++#define CMD_FORCE_TRX_OFF 3 ++#define CMD_FORCE_PLL_ON 4 ++#define CMD_RX_ON 6 ++#define CMD_TRX_OFF 8 ++#define CMD_PLL_ON 9 ++#define CMD_RX_AACK_ON 22 ++#define CMD_TX_ARET_ON 25 ++#define TRAC_SUCCESS 0 ++#define TRAC_SUCCESS_DATA_PENDING 1 ++#define TRAC_SUCCESS_WAIT_FOR_ACK 2 ++#define TRAC_CHANNEL_ACCESS_FAILURE 3 ++#define TRAC_NO_ACK 5 ++#define TRAC_INVALID 7 ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TRX_STATE */ ++ ++#define TRX_CMD0 0 ++#define TRX_CMD1 1 ++#define TRX_CMD2 2 ++#define TRX_CMD3 3 ++#define TRX_CMD4 4 ++#define TRAC_STATUS0 5 ++#define TRAC_STATUS1 6 ++#define TRAC_STATUS2 7 ++ ++/* Reserved */ ++#define TRX_CTRL_0 _SFR_MEM8(0x143) ++ ++/* Transceiver Control Register 1 */ ++#define TRX_CTRL_1 _SFR_MEM8(0x144) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TRX_CTRL_1 { ++ unsigned int : 5; ++ unsigned int tx_auto_crc_on : 1; /* Enable Automatic CRC Calculation */ ++ unsigned int irq_2_ext_en : 1; /* Connect Frame Start IRQ to TC1 */ ++ unsigned int pa_ext_en : 1; /* External PA support enable */ ++}; ++ ++#define TRX_CTRL_1_struct _SFR_MEM8_STRUCT(0x144, struct __reg_TRX_CTRL_1) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TRX_CTRL_1 */ ++ ++#define TX_AUTO_CRC_ON 5 ++#define IRQ_2_EXT_EN 6 ++#define PA_EXT_EN 7 ++ ++/* Transceiver Transmit Power Control Register */ ++#define PHY_TX_PWR _SFR_MEM8(0x145) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_PHY_TX_PWR { ++ unsigned int tx_pwr : 4; /* Transmit Power Setting */ ++ unsigned int pa_lt : 2; /* Power Amplifier Lead Time */ ++ unsigned int pa_buf_lt : 2; /* Power Amplifier Buffer Lead Time */ ++}; ++ ++#define PHY_TX_PWR_struct _SFR_MEM8_STRUCT(0x145, struct __reg_PHY_TX_PWR) ++ ++/* symbolic names */ ++ ++#define PA_LT_2US 0 ++#define PA_LT_4US 1 ++#define PA_LT_6US 2 ++#define PA_LT_8US 3 ++#define PA_BUF_LT_0US 0 ++#define PA_BUF_LT_2US 1 ++#define PA_BUF_LT_4US 2 ++#define PA_BUF_LT_6US 3 ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* PHY_TX_PWR */ ++ ++#define TX_PWR0 0 ++#define TX_PWR1 1 ++#define TX_PWR2 2 ++#define TX_PWR3 3 ++#define PA_LT0 4 ++#define PA_LT1 5 ++#define PA_BUF_LT0 6 ++#define PA_BUF_LT1 7 ++ ++/* Receiver Signal Strength Indicator Register */ ++#define PHY_RSSI _SFR_MEM8(0x146) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_PHY_RSSI { ++ unsigned int rssi : 5; /* Receiver Signal Strength Indicator */ ++ unsigned int rnd_value : 2; /* Random Value */ ++ unsigned int rx_crc_valid : 1; /* Received Frame CRC Status */ ++}; ++ ++#define PHY_RSSI_struct _SFR_MEM8_STRUCT(0x146, struct __reg_PHY_RSSI) ++ ++/* symbolic names */ ++ ++#define RSSI_MIN 0 ++#define RSSI_MIN_PLUS_3dB 1 ++#define RSSI_MAX 28 ++#define CRC_INVALID 0 ++#define CRC_VALID 1 ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* PHY_RSSI */ ++ ++#define RSSI0 0 ++#define RSSI1 1 ++#define RSSI2 2 ++#define RSSI3 3 ++#define RSSI4 4 ++#define RND_VALUE0 5 ++#define RND_VALUE1 6 ++#define RX_CRC_VALID 7 ++ ++/* Transceiver Energy Detection Level Register */ ++#define PHY_ED_LEVEL _SFR_MEM8(0x147) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_PHY_ED_LEVEL { ++ unsigned int ed_level : 8; /* Energy Detection Level */ ++}; ++ ++#define PHY_ED_LEVEL_struct _SFR_MEM8_STRUCT(0x147, struct __reg_PHY_ED_LEVEL) ++ ++/* symbolic names */ ++ ++#define ED_MIN 0 ++#define ED_MIN_PLUS_1dB 1 ++#define ED_MAX 84 ++#define ED_RESET 255 ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* PHY_ED_LEVEL */ ++ ++#define ED_LEVEL0 0 ++#define ED_LEVEL1 1 ++#define ED_LEVEL2 2 ++#define ED_LEVEL3 3 ++#define ED_LEVEL4 4 ++#define ED_LEVEL5 5 ++#define ED_LEVEL6 6 ++#define ED_LEVEL7 7 ++ ++/* Transceiver Clear Channel Assessment (CCA) Control Register */ ++#define PHY_CC_CCA _SFR_MEM8(0x148) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_PHY_CC_CCA { ++ unsigned int channel : 5; /* RX/TX Channel Selection */ ++ unsigned int cca_mode : 2; /* Select CCA Measurement Mode */ ++ unsigned int cca_request : 1; /* Manual CCA Measurement Request */ ++}; ++ ++#define PHY_CC_CCA_struct _SFR_MEM8_STRUCT(0x148, struct __reg_PHY_CC_CCA) ++ ++/* symbolic names */ ++ ++#define F_2405MHZ 11 ++#define F_2410MHZ 12 ++#define F_2415MHZ 13 ++#define F_2420MHZ 14 ++#define F_2425MHZ 15 ++#define F_2430MHZ 16 ++#define F_2435MHZ 17 ++#define F_2440MHZ 18 ++#define F_2445MHZ 19 ++#define F_2450MHZ 20 ++#define F_2455MHZ 21 ++#define F_2460MHZ 22 ++#define F_2465MHZ 23 ++#define F_2470MHZ 24 ++#define F_2475MHZ 25 ++#define F_2480MHZ 26 ++#define CCA_CS_OR_ED 0 ++#define CCA_ED 1 ++#define CCA_CS 2 ++#define CCA_CS_AND_ED 3 ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* PHY_CC_CCA */ ++ ++#define CHANNEL0 0 ++#define CHANNEL1 1 ++#define CHANNEL2 2 ++#define CHANNEL3 3 ++#define CHANNEL4 4 ++#define CCA_MODE0 5 ++#define CCA_MODE1 6 ++#define CCA_REQUEST 7 ++ ++/* Transceiver CCA Threshold Setting Register */ ++#define CCA_THRES _SFR_MEM8(0x149) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_CCA_THRES { ++ unsigned int cca_ed_thres : 4; /* ED Threshold Level for CCA Measurement */ ++ unsigned int cca_cs_thres : 4; /* CS Threshold Level for CCA Measurement */ ++}; ++ ++#define CCA_THRES_struct _SFR_MEM8_STRUCT(0x149, struct __reg_CCA_THRES) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* CCA_THRES */ ++ ++#define CCA_ED_THRES0 0 ++#define CCA_ED_THRES1 1 ++#define CCA_ED_THRES2 2 ++#define CCA_ED_THRES3 3 ++#define CCA_CS_THRES0 4 ++#define CCA_CS_THRES1 5 ++#define CCA_CS_THRES2 6 ++#define CCA_CS_THRES3 7 ++ ++/* Transceiver Receive Control Register */ ++#define RX_CTRL _SFR_MEM8(0x14A) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_RX_CTRL { ++ unsigned int pdt_thres : 4; /* Receiver Sensitivity Control */ ++ unsigned int : 4; ++}; ++ ++#define RX_CTRL_struct _SFR_MEM8_STRUCT(0x14a, struct __reg_RX_CTRL) ++ ++/* symbolic names */ ++ ++#define PDT_THRES_ANT_DIV_OFF 7 ++#define PDT_THRES_ANT_DIV_ON 3 ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* RX_CTRL */ ++ ++#define PDT_THRES0 0 ++#define PDT_THRES1 1 ++#define PDT_THRES2 2 ++#define PDT_THRES3 3 ++ ++/* Start of Frame Delimiter Value Register */ ++#define SFD_VALUE _SFR_MEM8(0x14B) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SFD_VALUE { ++ unsigned int sfd_value : 8; /* Start of Frame Delimiter Value */ ++}; ++ ++#define SFD_VALUE_struct _SFR_MEM8_STRUCT(0x14b, struct __reg_SFD_VALUE) ++ ++/* symbolic names */ ++ ++#define IEEE_SFD 167 ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SFD_VALUE */ ++ ++#define SFD_VALUE0 0 ++#define SFD_VALUE1 1 ++#define SFD_VALUE2 2 ++#define SFD_VALUE3 3 ++#define SFD_VALUE4 4 ++#define SFD_VALUE5 5 ++#define SFD_VALUE6 6 ++#define SFD_VALUE7 7 ++ ++/* Transceiver Control Register 2 */ ++#define TRX_CTRL_2 _SFR_MEM8(0x14C) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TRX_CTRL_2 { ++ unsigned int oqpsk_data_rate : 2; /* Data Rate Selection */ ++ unsigned int : 5; ++ unsigned int rx_safe_mode : 1; /* RX Safe Mode */ ++}; ++ ++#define TRX_CTRL_2_struct _SFR_MEM8_STRUCT(0x14c, struct __reg_TRX_CTRL_2) ++ ++/* symbolic names */ ++ ++#define RATE_250KB 0 ++#define RATE_500KB 1 ++#define RATE_1000KB 2 ++#define RATE_2000KB 3 ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TRX_CTRL_2 */ ++ ++#define OQPSK_DATA_RATE0 0 ++#define OQPSK_DATA_RATE1 1 ++#define RX_SAFE_MODE 7 ++ ++/* Antenna Diversity Control Register */ ++#define ANT_DIV _SFR_MEM8(0x14D) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_ANT_DIV { ++ unsigned int ant_ctrl : 2; /* Static Antenna Diversity Switch Control */ ++ unsigned int ant_ext_sw_en : 1; /* Enable External Antenna Switch Control */ ++ unsigned int ant_div_en : 1; /* Enable Antenna Diversity */ ++ unsigned int : 3; ++ unsigned int ant_sel : 1; /* Antenna Diversity Antenna Status */ ++}; ++ ++#define ANT_DIV_struct _SFR_MEM8_STRUCT(0x14d, struct __reg_ANT_DIV) ++ ++/* symbolic names */ ++ ++#define ANT_1 1 ++#define ANT_0 2 ++#define ANT_RESET 3 ++#define ANT_DIV_EXT_SW_DIS 0 ++#define ANT_DIV_EXT_SW_EN 1 ++#define ANTENNA_0 0 ++#define ANTENNA_1 1 ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* ANT_DIV */ ++ ++#define ANT_CTRL0 0 ++#define ANT_CTRL1 1 ++#define ANT_EXT_SW_EN 2 ++#define ANT_DIV_EN 3 ++#define ANT_SEL 7 ++ ++/* Transceiver Interrupt Enable Register */ ++#define IRQ_MASK _SFR_MEM8(0x14E) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_IRQ_MASK { ++ unsigned int pll_lock_en : 1; /* PLL Lock Interrupt Enable */ ++ unsigned int pll_unlock_en : 1; /* PLL Unlock Interrupt Enable */ ++ unsigned int rx_start_en : 1; /* RX_START Interrupt Enable */ ++ unsigned int rx_end_en : 1; /* RX_END Interrupt Enable */ ++ unsigned int cca_ed_done_en : 1; /* End of ED Measurement Interrupt Enable */ ++ unsigned int ami_en : 1; /* Address Match Interrupt Enable */ ++ unsigned int tx_end_en : 1; /* TX_END Interrupt Enable */ ++ unsigned int awake_en : 1; /* Awake Interrupt Enable */ ++}; ++ ++#define IRQ_MASK_struct _SFR_MEM8_STRUCT(0x14e, struct __reg_IRQ_MASK) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* IRQ_MASK */ ++ ++#define PLL_LOCK_EN 0 ++#define PLL_UNLOCK_EN 1 ++#define RX_START_EN 2 ++#define RX_END_EN 3 ++#define CCA_ED_DONE_EN 4 ++#define AMI_EN 5 ++#define TX_END_EN 6 ++#define AWAKE_EN 7 ++ ++/* Transceiver Interrupt Status Register */ ++#define IRQ_STATUS _SFR_MEM8(0x14F) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_IRQ_STATUS { ++ unsigned int pll_lock : 1; /* PLL Lock Interrupt Status */ ++ unsigned int pll_unlock : 1; /* PLL Unlock Interrupt Status */ ++ unsigned int rx_start : 1; /* RX_START Interrupt Status */ ++ unsigned int rx_end : 1; /* RX_END Interrupt Status */ ++ unsigned int cca_ed_done : 1; /* End of ED Measurement Interrupt Status */ ++ unsigned int ami : 1; /* Address Match Interrupt Status */ ++ unsigned int tx_end : 1; /* TX_END Interrupt Status */ ++ unsigned int awake : 1; /* Awake Interrupt Status */ ++}; ++ ++#define IRQ_STATUS_struct _SFR_MEM8_STRUCT(0x14f, struct __reg_IRQ_STATUS) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* IRQ_STATUS */ ++ ++#define PLL_LOCK 0 ++#define PLL_UNLOCK 1 ++#define RX_START 2 ++#define RX_END 3 ++#define CCA_ED_DONE 4 ++#define AMI 5 ++#define TX_END 6 ++#define AWAKE 7 ++ ++/* Voltage Regulator Control and Status Register */ ++#define VREG_CTRL _SFR_MEM8(0x150) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_VREG_CTRL { ++ unsigned int : 2; ++ unsigned int dvdd_ok : 1; /* DVDD Supply Voltage Valid */ ++ unsigned int dvreg_ext : 1; /* Use External DVDD Regulator */ ++ unsigned int : 2; ++ unsigned int avdd_ok : 1; /* AVDD Supply Voltage Valid */ ++ unsigned int avreg_ext : 1; /* Use External AVDD Regulator */ ++}; ++ ++#define VREG_CTRL_struct _SFR_MEM8_STRUCT(0x150, struct __reg_VREG_CTRL) ++ ++/* symbolic names */ ++ ++#define DVDD_INT 0 ++#define DVDD_EXT 1 ++#define AVDD_INT 0 ++#define AVDD_EXT 1 ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* VREG_CTRL */ ++ ++#define DVDD_OK 2 ++#define DVREG_EXT 3 ++#define AVDD_OK 6 ++#define AVREG_EXT 7 ++ ++/* Battery Monitor Control and Status Register */ ++#define BATMON _SFR_MEM8(0x151) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_BATMON { ++ unsigned int batmon_vth : 4; /* Battery Monitor Threshold Voltage */ ++ unsigned int batmon_hr : 1; /* Battery Monitor Voltage Range */ ++ unsigned int batmon_ok : 1; /* Battery Monitor Status */ ++ unsigned int bat_low_en : 1; /* Battery Monitor Interrupt Enable */ ++ unsigned int bat_low : 1; /* Battery Monitor Interrupt Status */ ++}; ++ ++#define BATMON_struct _SFR_MEM8_STRUCT(0x151, struct __reg_BATMON) ++ ++/* symbolic names */ ++ ++#define BATMON_HR_DIS 0 ++#define BATMON_HR_EN 1 ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* BATMON */ ++ ++#define BATMON_VTH0 0 ++#define BATMON_VTH1 1 ++#define BATMON_VTH2 2 ++#define BATMON_VTH3 3 ++#define BATMON_HR 4 ++#define BATMON_OK 5 ++#define BAT_LOW_EN 6 ++#define BAT_LOW 7 ++ ++/* Crystal Oscillator Control Register */ ++#define XOSC_CTRL _SFR_MEM8(0x152) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_XOSC_CTRL { ++ unsigned int xtal_trim : 4; /* Crystal Oscillator Load Capacitance Trimming */ ++ unsigned int xtal_mode : 4; /* Crystal Oscillator Operating Mode */ ++}; ++ ++#define XOSC_CTRL_struct _SFR_MEM8_STRUCT(0x152, struct __reg_XOSC_CTRL) ++ ++/* symbolic names */ ++ ++#define XTAL_TRIM_MIN 0 ++#define XTAL_TRIM_MAX 15 ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* XOSC_CTRL */ ++ ++#define XTAL_TRIM0 0 ++#define XTAL_TRIM1 1 ++#define XTAL_TRIM2 2 ++#define XTAL_TRIM3 3 ++#define XTAL_MODE0 4 ++#define XTAL_MODE1 5 ++#define XTAL_MODE2 6 ++#define XTAL_MODE3 7 ++ ++/* Transceiver Receiver Sensitivity Control Register */ ++#define RX_SYN _SFR_MEM8(0x155) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_RX_SYN { ++ unsigned int rx_pdt_level : 4; /* Reduce Receiver Sensitivity */ ++ unsigned int : 3; ++ unsigned int rx_pdt_dis : 1; /* Prevent Frame Reception */ ++}; ++ ++#define RX_SYN_struct _SFR_MEM8_STRUCT(0x155, struct __reg_RX_SYN) ++ ++/* symbolic names */ ++ ++#define RX_PDT_LEVEL_MIN 0 ++#define RX_PDT_LEVEL_MAX 15 ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* RX_SYN */ ++ ++#define RX_PDT_LEVEL0 0 ++#define RX_PDT_LEVEL1 1 ++#define RX_PDT_LEVEL2 2 ++#define RX_PDT_LEVEL3 3 ++#define RX_PDT_DIS 7 ++ ++/* Transceiver Acknowledgment Frame Control Register 1 */ ++#define XAH_CTRL_1 _SFR_MEM8(0x157) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_XAH_CTRL_1 { ++ unsigned int : 1; ++ unsigned int aack_prom_mode : 1; /* Enable Promiscuous Mode */ ++ unsigned int aack_ack_time : 1; /* Reduce Acknowledgment Time */ ++ unsigned int : 1; ++ unsigned int aack_upld_res_ft : 1; /* Process Reserved Frames */ ++ unsigned int aack_fltr_res_ft : 1; /* Filter Reserved Frames */ ++ unsigned int : 2; ++}; ++ ++#define XAH_CTRL_1_struct _SFR_MEM8_STRUCT(0x157, struct __reg_XAH_CTRL_1) ++ ++/* symbolic names */ ++ ++#define AACK_ACK_TIME_12_SYM 0 ++#define AACK_ACK_TIME_2_SYM 1 ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* XAH_CTRL_1 */ ++ ++#define AACK_PROM_MODE 1 ++#define AACK_ACK_TIME 2 ++#define AACK_UPLD_RES_FT 4 ++#define AACK_FLTR_RES_FT 5 ++ ++/* Transceiver Filter Tuning Control Register */ ++#define FTN_CTRL _SFR_MEM8(0x158) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_FTN_CTRL { ++ unsigned int : 7; ++ unsigned int ftn_start : 1; /* Start Calibration Loop of Filter Tuning Network */ ++}; ++ ++#define FTN_CTRL_struct _SFR_MEM8_STRUCT(0x158, struct __reg_FTN_CTRL) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* FTN_CTRL */ ++ ++#define FTN_START 7 ++ ++/* Transceiver Center Frequency Calibration Control Register */ ++#define PLL_CF _SFR_MEM8(0x15A) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_PLL_CF { ++ unsigned int : 7; ++ unsigned int pll_cf_start : 1; /* Start Center Frequency Calibration */ ++}; ++ ++#define PLL_CF_struct _SFR_MEM8_STRUCT(0x15a, struct __reg_PLL_CF) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* PLL_CF */ ++ ++#define PLL_CF_START 7 ++ ++/* Transceiver Delay Cell Calibration Control Register */ ++#define PLL_DCU _SFR_MEM8(0x15B) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_PLL_DCU { ++ unsigned int : 7; ++ unsigned int pll_dcu_start : 1; /* Start Delay Cell Calibration */ ++}; ++ ++#define PLL_DCU_struct _SFR_MEM8_STRUCT(0x15b, struct __reg_PLL_DCU) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* PLL_DCU */ ++ ++#define PLL_DCU_START 7 ++ ++/* Device Identification Register (Part Number) */ ++#define PART_NUM _SFR_MEM8(0x15C) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_PART_NUM { ++ unsigned int part_num : 8; /* Part Number */ ++}; ++ ++#define PART_NUM_struct _SFR_MEM8_STRUCT(0x15c, struct __reg_PART_NUM) ++ ++/* symbolic names */ ++ ++#define P_ATmega128RFA1 131 ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* PART_NUM */ ++ ++#define PART_NUM0 0 ++#define PART_NUM1 1 ++#define PART_NUM2 2 ++#define PART_NUM3 3 ++#define PART_NUM4 4 ++#define PART_NUM5 5 ++#define PART_NUM6 6 ++#define PART_NUM7 7 ++ ++/* Device Identification Register (Version Number) */ ++#define VERSION_NUM _SFR_MEM8(0x15D) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_VERSION_NUM { ++ unsigned int version_num : 8; /* Version Number */ ++}; ++ ++#define VERSION_NUM_struct _SFR_MEM8_STRUCT(0x15d, struct __reg_VERSION_NUM) ++ ++/* symbolic names */ ++ ++#define REV_A 2 ++#define REV_B 3 ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* VERSION_NUM */ ++ ++#define VERSION_NUM0 0 ++#define VERSION_NUM1 1 ++#define VERSION_NUM2 2 ++#define VERSION_NUM3 3 ++#define VERSION_NUM4 4 ++#define VERSION_NUM5 5 ++#define VERSION_NUM6 6 ++#define VERSION_NUM7 7 ++ ++/* Device Identification Register (Manufacture ID Low Byte) */ ++#define MAN_ID_0 _SFR_MEM8(0x15E) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_MAN_ID_0 { ++ unsigned int man_id_0 : 8; /* Manufacturer ID (Low Byte) */ ++}; ++ ++#define MAN_ID_0_struct _SFR_MEM8_STRUCT(0x15e, struct __reg_MAN_ID_0) ++ ++/* symbolic names */ ++ ++#define ATMEL_BYTE_0 31 ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* MAN_ID_0 */ ++ ++#define MAN_ID_00 0 ++#define MAN_ID_01 1 ++#define MAN_ID_02 2 ++#define MAN_ID_03 3 ++#define MAN_ID_04 4 ++#define MAN_ID_05 5 ++#define MAN_ID_06 6 ++#define MAN_ID_07 7 ++ ++/* Device Identification Register (Manufacture ID High Byte) */ ++#define MAN_ID_1 _SFR_MEM8(0x15F) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_MAN_ID_1 { ++ unsigned int man_id_1 : 8; /* Manufacturer ID (High Byte) */ ++}; ++ ++#define MAN_ID_1_struct _SFR_MEM8_STRUCT(0x15f, struct __reg_MAN_ID_1) ++ ++/* symbolic names */ ++ ++#define ATMEL_BYTE_1 0 ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* MAN_ID_1 */ ++ ++#define MAN_ID_10 0 ++#define MAN_ID_11 1 ++#define MAN_ID_12 2 ++#define MAN_ID_13 3 ++#define MAN_ID_14 4 ++#define MAN_ID_15 5 ++#define MAN_ID_16 6 ++#define MAN_ID_17 7 ++ ++/* Transceiver MAC Short Address Register (Low Byte) */ ++#define SHORT_ADDR_0 _SFR_MEM8(0x160) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SHORT_ADDR_0 { ++ unsigned int short_addr_0 : 8; /* MAC Short Address */ ++}; ++ ++#define SHORT_ADDR_0_struct _SFR_MEM8_STRUCT(0x160, struct __reg_SHORT_ADDR_0) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SHORT_ADDR_0 */ ++ ++#define SHORT_ADDR_00 0 ++#define SHORT_ADDR_01 1 ++#define SHORT_ADDR_02 2 ++#define SHORT_ADDR_03 3 ++#define SHORT_ADDR_04 4 ++#define SHORT_ADDR_05 5 ++#define SHORT_ADDR_06 6 ++#define SHORT_ADDR_07 7 ++ ++/* Transceiver MAC Short Address Register (High Byte) */ ++#define SHORT_ADDR_1 _SFR_MEM8(0x161) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_SHORT_ADDR_1 { ++ unsigned int short_addr_1 : 8; /* MAC Short Address */ ++}; ++ ++#define SHORT_ADDR_1_struct _SFR_MEM8_STRUCT(0x161, struct __reg_SHORT_ADDR_1) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* SHORT_ADDR_1 */ ++ ++#define SHORT_ADDR_10 0 ++#define SHORT_ADDR_11 1 ++#define SHORT_ADDR_12 2 ++#define SHORT_ADDR_13 3 ++#define SHORT_ADDR_14 4 ++#define SHORT_ADDR_15 5 ++#define SHORT_ADDR_16 6 ++#define SHORT_ADDR_17 7 ++ ++/* Transceiver Personal Area Network ID Register (Low Byte) */ ++#define PAN_ID_0 _SFR_MEM8(0x162) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_PAN_ID_0 { ++ unsigned int pan_id_0 : 8; /* MAC Personal Area Network ID */ ++}; ++ ++#define PAN_ID_0_struct _SFR_MEM8_STRUCT(0x162, struct __reg_PAN_ID_0) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* PAN_ID_0 */ ++ ++#define PAN_ID_00 0 ++#define PAN_ID_01 1 ++#define PAN_ID_02 2 ++#define PAN_ID_03 3 ++#define PAN_ID_04 4 ++#define PAN_ID_05 5 ++#define PAN_ID_06 6 ++#define PAN_ID_07 7 ++ ++/* Transceiver Personal Area Network ID Register (High Byte) */ ++#define PAN_ID_1 _SFR_MEM8(0x163) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_PAN_ID_1 { ++ unsigned int pan_id_1 : 8; /* MAC Personal Area Network ID */ ++}; ++ ++#define PAN_ID_1_struct _SFR_MEM8_STRUCT(0x163, struct __reg_PAN_ID_1) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* PAN_ID_1 */ ++ ++#define PAN_ID_10 0 ++#define PAN_ID_11 1 ++#define PAN_ID_12 2 ++#define PAN_ID_13 3 ++#define PAN_ID_14 4 ++#define PAN_ID_15 5 ++#define PAN_ID_16 6 ++#define PAN_ID_17 7 ++ ++/* Transceiver MAC IEEE Address Register 0 */ ++#define IEEE_ADDR_0 _SFR_MEM8(0x164) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_IEEE_ADDR_0 { ++ unsigned int ieee_addr_0 : 8; /* MAC IEEE Address */ ++}; ++ ++#define IEEE_ADDR_0_struct _SFR_MEM8_STRUCT(0x164, struct __reg_IEEE_ADDR_0) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* IEEE_ADDR_0 */ ++ ++#define IEEE_ADDR_00 0 ++#define IEEE_ADDR_01 1 ++#define IEEE_ADDR_02 2 ++#define IEEE_ADDR_03 3 ++#define IEEE_ADDR_04 4 ++#define IEEE_ADDR_05 5 ++#define IEEE_ADDR_06 6 ++#define IEEE_ADDR_07 7 ++ ++/* Transceiver MAC IEEE Address Register 1 */ ++#define IEEE_ADDR_1 _SFR_MEM8(0x165) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_IEEE_ADDR_1 { ++ unsigned int ieee_addr_1 : 8; /* MAC IEEE Address */ ++}; ++ ++#define IEEE_ADDR_1_struct _SFR_MEM8_STRUCT(0x165, struct __reg_IEEE_ADDR_1) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* IEEE_ADDR_1 */ ++ ++#define IEEE_ADDR_10 0 ++#define IEEE_ADDR_11 1 ++#define IEEE_ADDR_12 2 ++#define IEEE_ADDR_13 3 ++#define IEEE_ADDR_14 4 ++#define IEEE_ADDR_15 5 ++#define IEEE_ADDR_16 6 ++#define IEEE_ADDR_17 7 ++ ++/* Transceiver MAC IEEE Address Register 2 */ ++#define IEEE_ADDR_2 _SFR_MEM8(0x166) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_IEEE_ADDR_2 { ++ unsigned int ieee_addr_2 : 8; /* MAC IEEE Address */ ++}; ++ ++#define IEEE_ADDR_2_struct _SFR_MEM8_STRUCT(0x166, struct __reg_IEEE_ADDR_2) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* IEEE_ADDR_2 */ ++ ++#define IEEE_ADDR_20 0 ++#define IEEE_ADDR_21 1 ++#define IEEE_ADDR_22 2 ++#define IEEE_ADDR_23 3 ++#define IEEE_ADDR_24 4 ++#define IEEE_ADDR_25 5 ++#define IEEE_ADDR_26 6 ++#define IEEE_ADDR_27 7 ++ ++/* Transceiver MAC IEEE Address Register 3 */ ++#define IEEE_ADDR_3 _SFR_MEM8(0x167) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_IEEE_ADDR_3 { ++ unsigned int ieee_addr_3 : 8; /* MAC IEEE Address */ ++}; ++ ++#define IEEE_ADDR_3_struct _SFR_MEM8_STRUCT(0x167, struct __reg_IEEE_ADDR_3) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* IEEE_ADDR_3 */ ++ ++#define IEEE_ADDR_30 0 ++#define IEEE_ADDR_31 1 ++#define IEEE_ADDR_32 2 ++#define IEEE_ADDR_33 3 ++#define IEEE_ADDR_34 4 ++#define IEEE_ADDR_35 5 ++#define IEEE_ADDR_36 6 ++#define IEEE_ADDR_37 7 ++ ++/* Transceiver MAC IEEE Address Register 4 */ ++#define IEEE_ADDR_4 _SFR_MEM8(0x168) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_IEEE_ADDR_4 { ++ unsigned int ieee_addr_4 : 8; /* MAC IEEE Address */ ++}; ++ ++#define IEEE_ADDR_4_struct _SFR_MEM8_STRUCT(0x168, struct __reg_IEEE_ADDR_4) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* IEEE_ADDR_4 */ ++ ++#define IEEE_ADDR_40 0 ++#define IEEE_ADDR_41 1 ++#define IEEE_ADDR_42 2 ++#define IEEE_ADDR_43 3 ++#define IEEE_ADDR_44 4 ++#define IEEE_ADDR_45 5 ++#define IEEE_ADDR_46 6 ++#define IEEE_ADDR_47 7 ++ ++/* Transceiver MAC IEEE Address Register 5 */ ++#define IEEE_ADDR_5 _SFR_MEM8(0x169) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_IEEE_ADDR_5 { ++ unsigned int ieee_addr_5 : 8; /* MAC IEEE Address */ ++}; ++ ++#define IEEE_ADDR_5_struct _SFR_MEM8_STRUCT(0x169, struct __reg_IEEE_ADDR_5) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* IEEE_ADDR_5 */ ++ ++#define IEEE_ADDR_50 0 ++#define IEEE_ADDR_51 1 ++#define IEEE_ADDR_52 2 ++#define IEEE_ADDR_53 3 ++#define IEEE_ADDR_54 4 ++#define IEEE_ADDR_55 5 ++#define IEEE_ADDR_56 6 ++#define IEEE_ADDR_57 7 ++ ++/* Transceiver MAC IEEE Address Register 6 */ ++#define IEEE_ADDR_6 _SFR_MEM8(0x16A) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_IEEE_ADDR_6 { ++ unsigned int ieee_addr_6 : 8; /* MAC IEEE Address */ ++}; ++ ++#define IEEE_ADDR_6_struct _SFR_MEM8_STRUCT(0x16a, struct __reg_IEEE_ADDR_6) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* IEEE_ADDR_6 */ ++ ++#define IEEE_ADDR_60 0 ++#define IEEE_ADDR_61 1 ++#define IEEE_ADDR_62 2 ++#define IEEE_ADDR_63 3 ++#define IEEE_ADDR_64 4 ++#define IEEE_ADDR_65 5 ++#define IEEE_ADDR_66 6 ++#define IEEE_ADDR_67 7 ++ ++/* Transceiver MAC IEEE Address Register 7 */ ++#define IEEE_ADDR_7 _SFR_MEM8(0x16B) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_IEEE_ADDR_7 { ++ unsigned int ieee_addr_7 : 8; /* MAC IEEE Address */ ++}; ++ ++#define IEEE_ADDR_7_struct _SFR_MEM8_STRUCT(0x16b, struct __reg_IEEE_ADDR_7) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* IEEE_ADDR_7 */ ++ ++#define IEEE_ADDR_70 0 ++#define IEEE_ADDR_71 1 ++#define IEEE_ADDR_72 2 ++#define IEEE_ADDR_73 3 ++#define IEEE_ADDR_74 4 ++#define IEEE_ADDR_75 5 ++#define IEEE_ADDR_76 6 ++#define IEEE_ADDR_77 7 ++ ++/* Transceiver Extended Operating Mode Control Register */ ++#define XAH_CTRL_0 _SFR_MEM8(0x16C) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_XAH_CTRL_0 { ++ unsigned int slotted_operation : 1; /* Set Slotted Acknowledgment */ ++ unsigned int max_csma_retries : 3; /* Maximum Number of CSMA-CA Procedure Repetition Attempts */ ++ unsigned int max_frame_retries : 4; /* Maximum Number of Frame Re-transmission Attempts */ ++}; ++ ++#define XAH_CTRL_0_struct _SFR_MEM8_STRUCT(0x16c, struct __reg_XAH_CTRL_0) ++ ++/* symbolic names */ ++ ++#define SLOTTED_OP_DIS 0 ++#define SLOTTED_OP_EN 1 ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* XAH_CTRL_0 */ ++ ++#define SLOTTED_OPERATION 0 ++#define MAX_CSMA_RETRIES0 1 ++#define MAX_CSMA_RETRIES1 2 ++#define MAX_CSMA_RETRIES2 3 ++#define MAX_FRAME_RETRIES0 4 ++#define MAX_FRAME_RETRIES1 5 ++#define MAX_FRAME_RETRIES2 6 ++#define MAX_FRAME_RETRIES3 7 ++ ++/* Transceiver CSMA-CA Random Number Generator Seed Register */ ++#define CSMA_SEED_0 _SFR_MEM8(0x16D) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_CSMA_SEED_0 { ++ unsigned int csma_seed_0 : 8; /* Seed Value for CSMA Random Number Generator */ ++}; ++ ++#define CSMA_SEED_0_struct _SFR_MEM8_STRUCT(0x16d, struct __reg_CSMA_SEED_0) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* CSMA_SEED_0 */ ++ ++#define CSMA_SEED_00 0 ++#define CSMA_SEED_01 1 ++#define CSMA_SEED_02 2 ++#define CSMA_SEED_03 3 ++#define CSMA_SEED_04 4 ++#define CSMA_SEED_05 5 ++#define CSMA_SEED_06 6 ++#define CSMA_SEED_07 7 ++ ++/* Transceiver Acknowledgment Frame Control Register 2 */ ++#define CSMA_SEED_1 _SFR_MEM8(0x16E) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_CSMA_SEED_1 { ++ unsigned int csma_seed_1 : 3; /* Seed Value for CSMA Random Number Generator */ ++ unsigned int aack_i_am_coord : 1; /* Set Personal Area Network Coordinator */ ++ unsigned int aack_dis_ack : 1; /* Disable Acknowledgment Frame Transmission */ ++ unsigned int aack_set_pd : 1; /* Set Frame Pending Sub-field */ ++ unsigned int aack_fvn_mode : 2; /* Acknowledgment Frame Filter Mode */ ++}; ++ ++#define CSMA_SEED_1_struct _SFR_MEM8_STRUCT(0x16e, struct __reg_CSMA_SEED_1) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* CSMA_SEED_1 */ ++ ++#define CSMA_SEED_10 0 ++#define CSMA_SEED_11 1 ++#define CSMA_SEED_12 2 ++#define AACK_I_AM_COORD 3 ++#define AACK_DIS_ACK 4 ++#define AACK_SET_PD 5 ++#define AACK_FVN_MODE0 6 ++#define AACK_FVN_MODE1 7 ++ ++/* Transceiver CSMA-CA Back-off Exponent Control Register */ ++#define CSMA_BE _SFR_MEM8(0x16F) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_CSMA_BE { ++ unsigned int min_be : 4; /* Minimum Back-off Exponent */ ++ unsigned int max_be : 4; /* Maximum Back-off Exponent */ ++}; ++ ++#define CSMA_BE_struct _SFR_MEM8_STRUCT(0x16f, struct __reg_CSMA_BE) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* CSMA_BE */ ++ ++#define MIN_BE0 0 ++#define MIN_BE1 1 ++#define MIN_BE2 2 ++#define MIN_BE3 3 ++#define MAX_BE0 4 ++#define MAX_BE1 5 ++#define MAX_BE2 6 ++#define MAX_BE3 7 ++ ++/* Transceiver Digital Test Control Register */ ++#define TST_CTRL_DIGI _SFR_MEM8(0x176) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TST_CTRL_DIGI { ++ unsigned int tst_ctrl_dig : 4; /* Digital Test Controller Register */ ++ unsigned int : 4; ++}; ++ ++#define TST_CTRL_DIGI_struct _SFR_MEM8_STRUCT(0x176, struct __reg_TST_CTRL_DIGI) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TST_CTRL_DIGI */ ++ ++#define TST_CTRL_DIG0 0 ++#define TST_CTRL_DIG1 1 ++#define TST_CTRL_DIG2 2 ++#define TST_CTRL_DIG3 3 ++ ++/* Transceiver Received Frame Length Register */ ++#define TST_RX_LENGTH _SFR_MEM8(0x17B) ++ ++#if !(defined(__ASSEMBLER__) || defined(__NOSTRUCT__)) ++ ++struct __reg_TST_RX_LENGTH { ++ unsigned int rx_length : 8; /* Received Frame Length */ ++}; ++ ++#define TST_RX_LENGTH_struct _SFR_MEM8_STRUCT(0x17b, struct __reg_TST_RX_LENGTH) ++ ++#endif /* __ASSEMBLER__ */ ++ ++ /* TST_RX_LENGTH */ ++ ++#define RX_LENGTH0 0 ++#define RX_LENGTH1 1 ++#define RX_LENGTH2 2 ++#define RX_LENGTH3 3 ++#define RX_LENGTH4 4 ++#define RX_LENGTH5 5 ++#define RX_LENGTH6 6 ++#define RX_LENGTH7 7 ++ ++/* Start of frame buffer */ ++#define TRXFBST _SFR_MEM8(0x180) ++ ++ /* TRXFBST */ ++ ++#define TRXFBST0 0 ++#define TRXFBST1 1 ++#define TRXFBST2 2 ++#define TRXFBST3 3 ++#define TRXFBST4 4 ++#define TRXFBST5 5 ++#define TRXFBST6 6 ++#define TRXFBST7 7 ++ ++/* End of frame buffer */ ++#define TRXFBEND _SFR_MEM8(0x1FF) ++ ++ /* TRXFBEND */ ++ ++#define TRXFBEND0 0 ++#define TRXFBEND1 1 ++#define TRXFBEND2 2 ++#define TRXFBEND3 3 ++#define TRXFBEND4 4 ++#define TRXFBEND5 5 ++#define TRXFBEND6 6 ++#define TRXFBEND7 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++ ++#define _VECTORS_SIZE 288 ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect _VECTOR(3) ++#define INT2_vect_num 3 ++ ++/* External Interrupt Request 3 */ ++#define INT3_vect _VECTOR(4) ++#define INT3_vect_num 4 ++ ++/* External Interrupt Request 4 */ ++#define INT4_vect _VECTOR(5) ++#define INT4_vect_num 5 ++ ++/* External Interrupt Request 5 */ ++#define INT5_vect _VECTOR(6) ++#define INT5_vect_num 6 ++ ++/* External Interrupt Request 6 */ ++#define INT6_vect _VECTOR(7) ++#define INT6_vect_num 7 ++ ++/* External Interrupt Request 7 */ ++#define INT7_vect _VECTOR(8) ++#define INT7_vect_num 8 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(9) ++#define PCINT0_vect_num 9 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(10) ++#define PCINT1_vect_num 10 ++ ++/* Pin Change Interrupt Request 2 */ ++#define PCINT2_vect _VECTOR(11) ++#define PCINT2_vect_num 11 ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect _VECTOR(12) ++#define WDT_vect_num 12 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPA_vect _VECTOR(13) ++#define TIMER2_COMPA_vect_num 13 ++ ++/* Timer/Counter2 Compare Match B */ ++#define TIMER2_COMPB_vect _VECTOR(14) ++#define TIMER2_COMPB_vect_num 14 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(15) ++#define TIMER2_OVF_vect_num 15 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(16) ++#define TIMER1_CAPT_vect_num 16 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(17) ++#define TIMER1_COMPA_vect_num 17 ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(18) ++#define TIMER1_COMPB_vect_num 18 ++ ++/* Timer/Counter1 Compare Match C */ ++#define TIMER1_COMPC_vect _VECTOR(19) ++#define TIMER1_COMPC_vect_num 19 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(20) ++#define TIMER1_OVF_vect_num 20 ++ ++/* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPA_vect _VECTOR(21) ++#define TIMER0_COMPA_vect_num 21 ++ ++/* Timer/Counter0 Compare Match B */ ++#define TIMER0_COMPB_vect _VECTOR(22) ++#define TIMER0_COMPB_vect_num 22 ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(23) ++#define TIMER0_OVF_vect_num 23 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(24) ++#define SPI_STC_vect_num 24 ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect _VECTOR(25) ++#define USART0_RX_vect_num 25 ++ ++/* USART0 Data register Empty */ ++#define USART0_UDRE_vect _VECTOR(26) ++#define USART0_UDRE_vect_num 26 ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect _VECTOR(27) ++#define USART0_TX_vect_num 27 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(28) ++#define ANALOG_COMP_vect_num 28 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(29) ++#define ADC_vect_num 29 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(30) ++#define EE_READY_vect_num 30 ++ ++/* Timer/Counter3 Capture Event */ ++#define TIMER3_CAPT_vect _VECTOR(31) ++#define TIMER3_CAPT_vect_num 31 ++ ++/* Timer/Counter3 Compare Match A */ ++#define TIMER3_COMPA_vect _VECTOR(32) ++#define TIMER3_COMPA_vect_num 32 ++ ++/* Timer/Counter3 Compare Match B */ ++#define TIMER3_COMPB_vect _VECTOR(33) ++#define TIMER3_COMPB_vect_num 33 ++ ++/* Timer/Counter3 Compare Match C */ ++#define TIMER3_COMPC_vect _VECTOR(34) ++#define TIMER3_COMPC_vect_num 34 ++ ++/* Timer/Counter3 Overflow */ ++#define TIMER3_OVF_vect _VECTOR(35) ++#define TIMER3_OVF_vect_num 35 ++ ++/* USART1, Rx Complete */ ++#define USART1_RX_vect _VECTOR(36) ++#define USART1_RX_vect_num 36 ++ ++/* USART1 Data register Empty */ ++#define USART1_UDRE_vect _VECTOR(37) ++#define USART1_UDRE_vect_num 37 ++ ++/* USART1, Tx Complete */ ++#define USART1_TX_vect _VECTOR(38) ++#define USART1_TX_vect_num 38 ++ ++/* 2-wire Serial Interface */ ++#define TWI_vect _VECTOR(39) ++#define TWI_vect_num 39 ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect _VECTOR(40) ++#define SPM_READY_vect_num 40 ++ ++/* Timer/Counter4 Capture Event */ ++#define TIMER4_CAPT_vect _VECTOR(41) ++#define TIMER4_CAPT_vect_num 41 ++ ++/* Timer/Counter4 Compare Match A */ ++#define TIMER4_COMPA_vect _VECTOR(42) ++#define TIMER4_COMPA_vect_num 42 ++ ++/* Timer/Counter4 Compare Match B */ ++#define TIMER4_COMPB_vect _VECTOR(43) ++#define TIMER4_COMPB_vect_num 43 ++ ++/* Timer/Counter4 Compare Match C */ ++#define TIMER4_COMPC_vect _VECTOR(44) ++#define TIMER4_COMPC_vect_num 44 ++ ++/* Timer/Counter4 Overflow */ ++#define TIMER4_OVF_vect _VECTOR(45) ++#define TIMER4_OVF_vect_num 45 ++ ++/* Timer/Counter5 Capture Event */ ++#define TIMER5_CAPT_vect _VECTOR(46) ++#define TIMER5_CAPT_vect_num 46 ++ ++/* Timer/Counter5 Compare Match A */ ++#define TIMER5_COMPA_vect _VECTOR(47) ++#define TIMER5_COMPA_vect_num 47 ++ ++/* Timer/Counter5 Compare Match B */ ++#define TIMER5_COMPB_vect _VECTOR(48) ++#define TIMER5_COMPB_vect_num 48 ++ ++/* Timer/Counter5 Compare Match C */ ++#define TIMER5_COMPC_vect _VECTOR(49) ++#define TIMER5_COMPC_vect_num 49 ++ ++/* Timer/Counter5 Overflow */ ++#define TIMER5_OVF_vect _VECTOR(50) ++#define TIMER5_OVF_vect_num 50 ++ ++/* USART2, Rx Complete */ ++#define USART2_RX_vect _VECTOR(51) ++#define USART2_RX_vect_num 51 ++ ++/* USART2 Data register Empty */ ++#define USART2_UDRE_vect _VECTOR(52) ++#define USART2_UDRE_vect_num 52 ++ ++/* USART2, Tx Complete */ ++#define USART2_TX_vect _VECTOR(53) ++#define USART2_TX_vect_num 53 ++ ++/* USART3, Rx Complete */ ++#define USART3_RX_vect _VECTOR(54) ++#define USART3_RX_vect_num 54 ++ ++/* USART3 Data register Empty */ ++#define USART3_UDRE_vect _VECTOR(55) ++#define USART3_UDRE_vect_num 55 ++ ++/* USART3, Tx Complete */ ++#define USART3_TX_vect _VECTOR(56) ++#define USART3_TX_vect_num 56 ++ ++/* TRX24 - PLL lock interrupt */ ++#define TRX24_PLL_LOCK_vect _VECTOR(57) ++#define TRX24_PLL_LOCK_vect_num 57 ++ ++/* TRX24 - PLL unlock interrupt */ ++#define TRX24_PLL_UNLOCK_vect _VECTOR(58) ++#define TRX24_PLL_UNLOCK_vect_num 58 ++ ++/* TRX24 - Receive start interrupt */ ++#define TRX24_RX_START_vect _VECTOR(59) ++#define TRX24_RX_START_vect_num 59 ++ ++/* TRX24 - RX_END interrupt */ ++#define TRX24_RX_END_vect _VECTOR(60) ++#define TRX24_RX_END_vect_num 60 ++ ++/* TRX24 - CCA/ED done interrupt */ ++#define TRX24_CCA_ED_DONE_vect _VECTOR(61) ++#define TRX24_CCA_ED_DONE_vect_num 61 ++ ++/* TRX24 - XAH - AMI */ ++#define TRX24_XAH_AMI_vect _VECTOR(62) ++#define TRX24_XAH_AMI_vect_num 62 ++ ++/* TRX24 - TX_END interrupt */ ++#define TRX24_TX_END_vect _VECTOR(63) ++#define TRX24_TX_END_vect_num 63 ++ ++/* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */ ++#define TRX24_AWAKE_vect _VECTOR(64) ++#define TRX24_AWAKE_vect_num 64 ++ ++/* Symbol counter - compare match 1 interrupt */ ++#define SCNT_CMP1_vect _VECTOR(65) ++#define SCNT_CMP1_vect_num 65 ++ ++/* Symbol counter - compare match 2 interrupt */ ++#define SCNT_CMP2_vect _VECTOR(66) ++#define SCNT_CMP2_vect_num 66 ++ ++/* Symbol counter - compare match 3 interrupt */ ++#define SCNT_CMP3_vect _VECTOR(67) ++#define SCNT_CMP3_vect_num 67 ++ ++/* Symbol counter - overflow interrupt */ ++#define SCNT_OVFL_vect _VECTOR(68) ++#define SCNT_OVFL_vect_num 68 ++ ++/* Symbol counter - backoff interrupt */ ++#define SCNT_BACKOFF_vect _VECTOR(69) ++#define SCNT_BACKOFF_vect_num 69 ++ ++/* AES engine ready interrupt */ ++#define AES_READY_vect _VECTOR(70) ++#define AES_READY_vect_num 70 ++ ++/* Battery monitor indicates supply voltage below threshold */ ++#define BAT_LOW_vect _VECTOR(71) ++#define BAT_LOW_vect_num 71 ++ ++ ++/* memory parameters */ ++ ++#define SPM_PAGESIZE (256) ++#define RAMSTART (0x200) ++#define RAMSIZE (0x4000) ++#define RAMEND (0x41FF) ++#define XRAMSTART (0x0000) ++#define XRAMSIZE (0x0000) ++#define XRAMEND RAMEND ++#define E2END (0xFFF) ++#define E2PAGESIZE (0x08) ++#define FLASHEND (0x1ffff) ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* LFUSE Byte */ ++#define FUSE_CKSEL0 ~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 ~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 ~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 ~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 ~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 ~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT ~_BV(6) /* Clock output */ ++#define FUSE_CKDIV8 ~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) ++ ++/* HFUSE Byte */ ++#define FUSE_BOOTRST ~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 ~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 ~_BV(2) /* Select Boot Size */ ++#define FUSE_EESAVE ~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON ~_BV(4) /* Watchdog timer always on */ ++#define FUSE_SPIEN ~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_JTAGEN ~_BV(6) /* Enable JTAG */ ++#define FUSE_OCDEN ~_BV(7) /* Enable OCD */ ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* EFUSE Byte */ ++#define FUSE_BODLEVEL0 ~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 ~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 ~_BV(2) /* Brown-out Detector trigger level */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++ ++/* Lock Bits */ ++ ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0xA7 ++#define SIGNATURE_2 0x01 ++ ++#endif /* _AVR_IOM128RFA1_H_ */ +diff --git a/include/avr/iom128rfr2.h b/include/avr/iom128rfr2.h +new file mode 100644 +index 0000000..85c8da4 +--- /dev/null ++++ b/include/avr/iom128rfr2.h +@@ -0,0 +1,2555 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATMEGA128RFR2_H_INCLUDED ++#define _AVR_ATMEGA128RFR2_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom128rfr2.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDRA7 7 ++#define DDRA6 6 ++#define DDRA5 5 ++#define DDRA4 4 ++#define DDRA3 3 ++#define DDRA2 2 ++#define DDRA1 1 ++#define DDRA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDRC7 7 ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC7 7 ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDRE7 7 ++#define DDRE6 6 ++#define DDRE5 5 ++#define DDRE4 4 ++#define DDRE3 3 ++#define DDRE2 2 ++#define DDRE1 1 ++#define DDRE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE7 7 ++#define PORTE6 6 ++#define PORTE5 5 ++#define PORTE4 4 ++#define PORTE3 3 ++#define PORTE2 2 ++#define PORTE1 1 ++#define PORTE0 0 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDRF7 7 ++#define DDRF6 6 ++#define DDRF5 5 ++#define DDRF4 4 ++#define DDRF3 3 ++#define DDRF2 2 ++#define DDRF1 1 ++#define DDRF0 0 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PORTF7 7 ++#define PORTF6 6 ++#define PORTF5 5 ++#define PORTF4 4 ++#define PORTF3 3 ++#define PORTF2 2 ++#define PORTF1 1 ++#define PORTF0 0 ++ ++#define PING _SFR_IO8(0x12) ++#define PING7 7 ++#define PING6 6 ++#define PING5 5 ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++#define DDRG _SFR_IO8(0x13) ++#define DDRG7 7 ++#define DDRG6 6 ++#define DDRG5 5 ++#define DDRG4 4 ++#define DDRG3 3 ++#define DDRG2 2 ++#define DDRG1 1 ++#define DDRG0 0 ++ ++#define PORTG _SFR_IO8(0x14) ++#define PORTG7 7 ++#define PORTG6 6 ++#define PORTG5 5 ++#define PORTG4 4 ++#define PORTG3 3 ++#define PORTG2 2 ++#define PORTG1 1 ++#define PORTG0 0 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++#define Res0 3 ++#define Res1 4 ++#define Res2 5 ++#define Res3 6 ++#define Res4 7 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define OCF1C 3 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++#define TIFR3 _SFR_IO8(0x18) ++#define TOV3 0 ++#define OCF3A 1 ++#define OCF3B 2 ++#define OCF3C 3 ++#define ICF3 5 ++ ++#define TIFR4 _SFR_IO8(0x19) ++#define TOV4 0 ++#define OCF4A 1 ++#define OCF4B 2 ++#define OCF4C 3 ++#define ICF4 5 ++ ++#define TIFR5 _SFR_IO8(0x1A) ++#define TOV5 0 ++#define OCF5A 1 ++#define OCF5B 2 ++#define OCF5C 3 ++#define ICF5 5 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++#define INTF4 4 ++#define INTF5 5 ++#define INTF6 6 ++#define INTF7 7 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++#define INT3 3 ++#define INT4 4 ++#define INT5 5 ++#define INT6 6 ++#define INT7 7 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define PSRASY 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++ ++#define OCR0A _SFR_IO8(0x27) ++ ++#define OCR0B _SFR_IO8(0x28) ++ ++/* Reserved [0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCDR7 7 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define JTRF 4 ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define JTD 7 ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3A] */ ++ ++#define RAMPZ _SFR_IO8(0x3B) ++#define RAMPZ0 0 ++#define Res5 6 ++#define Res6 7 ++ ++/* Reserved [0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDE 3 ++#define WDCE 4 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62] */ ++ ++#define PRR2 _SFR_MEM8(0x63) ++#define PRRAM0 0 ++#define PRRAM1 1 ++#define PRRAM2 2 ++#define PRRAM3 3 ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRPGA 4 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++#define PRR1 _SFR_MEM8(0x65) ++#define PRUSART1 0 ++#define PRTIM3 3 ++#define PRTIM4 4 ++#define PRTIM5 5 ++#define PRTRX24 6 ++#define Res 7 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++#define BGCR _SFR_MEM8(0x67) ++#define BGCAL0 0 ++#define BGCAL1 1 ++#define BGCAL2 2 ++#define BGCAL_FINE0 3 ++#define BGCAL_FINE1 4 ++#define BGCAL_FINE2 5 ++#define BGCAL_FINE3 6 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++#define EICRB _SFR_MEM8(0x6A) ++#define ISC40 0 ++#define ISC41 1 ++#define ISC50 2 ++#define ISC51 3 ++#define ISC60 4 ++#define ISC61 5 ++#define ISC70 6 ++#define ISC71 7 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define OCIE1C 3 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++#define TIMSK3 _SFR_MEM8(0x71) ++#define TOIE3 0 ++#define OCIE3A 1 ++#define OCIE3B 2 ++#define OCIE3C 3 ++#define ICIE3 5 ++ ++#define TIMSK4 _SFR_MEM8(0x72) ++#define TOIE4 0 ++#define OCIE4A 1 ++#define OCIE4B 2 ++#define OCIE4C 3 ++#define ICIE4 5 ++ ++#define TIMSK5 _SFR_MEM8(0x73) ++#define TOIE5 0 ++#define OCIE5A 1 ++#define OCIE5B 2 ++#define OCIE5C 3 ++#define ICIE5 5 ++ ++/* Reserved [0x74] */ ++ ++#define NEMCR _SFR_MEM8(0x75) ++#define AEAM0 4 ++#define AEAM1 5 ++#define ENEAM 6 ++ ++/* Reserved [0x76] */ ++ ++#define ADCSRC _SFR_MEM8(0x77) ++#define ADSUT0 0 ++#define ADSUT1 1 ++#define ADSUT2 2 ++#define ADSUT3 3 ++#define ADSUT4 4 ++#define ADTHT0 6 ++#define ADTHT1 7 ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ACME 6 ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define MUX5 3 ++#define ACCH 4 ++#define REFOK 5 ++#define AVDDOK 7 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR2 _SFR_MEM8(0x7D) ++#define ADC8D 0 ++#define ADC9D 1 ++#define ADC10D 2 ++#define ADC11D 3 ++#define ADC12D 4 ++#define ADC13D 5 ++#define ADC14D 6 ++#define ADC15D 7 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1C0 2 ++#define COM1C1 3 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1C 5 ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Combine OCR1CL and OCR1CH */ ++#define OCR1C _SFR_MEM16(0x8C) ++ ++#define OCR1CL _SFR_MEM8(0x8C) ++#define OCR1CH _SFR_MEM8(0x8D) ++ ++/* Reserved [0x8E..0x8F] */ ++ ++#define TCCR3A _SFR_MEM8(0x90) ++#define WGM30 0 ++#define WGM31 1 ++#define COM3C0 2 ++#define COM3C1 3 ++#define COM3B0 4 ++#define COM3B1 5 ++#define COM3A0 6 ++#define COM3A1 7 ++ ++#define TCCR3B _SFR_MEM8(0x91) ++#define CS30 0 ++#define CS31 1 ++#define CS32 2 ++#define WGM32 3 ++#define WGM33 4 ++#define ICES3 6 ++#define ICNC3 7 ++ ++#define TCCR3C _SFR_MEM8(0x92) ++#define FOC3C 5 ++#define FOC3B 6 ++#define FOC3A 7 ++ ++/* Reserved [0x93] */ ++ ++/* Combine TCNT3L and TCNT3H */ ++#define TCNT3 _SFR_MEM16(0x94) ++ ++#define TCNT3L _SFR_MEM8(0x94) ++#define TCNT3H _SFR_MEM8(0x95) ++ ++/* Combine ICR3L and ICR3H */ ++#define ICR3 _SFR_MEM16(0x96) ++ ++#define ICR3L _SFR_MEM8(0x96) ++#define ICR3H _SFR_MEM8(0x97) ++ ++/* Combine OCR3AL and OCR3AH */ ++#define OCR3A _SFR_MEM16(0x98) ++ ++#define OCR3AL _SFR_MEM8(0x98) ++#define OCR3AH _SFR_MEM8(0x99) ++ ++/* Combine OCR3BL and OCR3BH */ ++#define OCR3B _SFR_MEM16(0x9A) ++ ++#define OCR3BL _SFR_MEM8(0x9A) ++#define OCR3BH _SFR_MEM8(0x9B) ++ ++/* Combine OCR3CL and OCR3CH */ ++#define OCR3C _SFR_MEM16(0x9C) ++ ++#define OCR3CL _SFR_MEM8(0x9C) ++#define OCR3CH _SFR_MEM8(0x9D) ++ ++/* Reserved [0x9E..0x9F] */ ++ ++#define TCCR4A _SFR_MEM8(0xA0) ++#define WGM40 0 ++#define WGM41 1 ++#define COM4C0 2 ++#define COM4C1 3 ++#define COM4B0 4 ++#define COM4B1 5 ++#define COM4A0 6 ++#define COM4A1 7 ++ ++#define TCCR4B _SFR_MEM8(0xA1) ++#define CS40 0 ++#define CS41 1 ++#define CS42 2 ++#define WGM42 3 ++#define WGM43 4 ++#define ICES4 6 ++#define ICNC4 7 ++ ++#define TCCR4C _SFR_MEM8(0xA2) ++#define FOC4C 5 ++#define FOC4B 6 ++#define FOC4A 7 ++ ++/* Reserved [0xA3] */ ++ ++/* Combine TCNT4L and TCNT4H */ ++#define TCNT4 _SFR_MEM16(0xA4) ++ ++#define TCNT4L _SFR_MEM8(0xA4) ++#define TCNT4H _SFR_MEM8(0xA5) ++ ++/* Combine ICR4L and ICR4H */ ++#define ICR4 _SFR_MEM16(0xA6) ++ ++#define ICR4L _SFR_MEM8(0xA6) ++#define ICR4H _SFR_MEM8(0xA7) ++ ++/* Combine OCR4AL and OCR4AH */ ++#define OCR4A _SFR_MEM16(0xA8) ++ ++#define OCR4AL _SFR_MEM8(0xA8) ++#define OCR4AH _SFR_MEM8(0xA9) ++ ++/* Combine OCR4BL and OCR4BH */ ++#define OCR4B _SFR_MEM16(0xAA) ++ ++#define OCR4BL _SFR_MEM8(0xAA) ++#define OCR4BH _SFR_MEM8(0xAB) ++ ++/* Combine OCR4CL and OCR4CH */ ++#define OCR4C _SFR_MEM16(0xAC) ++ ++#define OCR4CL _SFR_MEM8(0xAC) ++#define OCR4CH _SFR_MEM8(0xAD) ++ ++/* Reserved [0xAE..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++#define OCR2B _SFR_MEM8(0xB4) ++ ++/* Reserved [0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++#define EXCLKAMR 7 ++ ++/* Reserved [0xB7] */ ++ ++#define TWBR _SFR_MEM8(0xB8) ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++#define IRQ_MASK1 _SFR_MEM8(0xBE) ++#define TX_START_EN 0 ++#define MAF_0_AMI_EN 1 ++#define MAF_1_AMI_EN 2 ++#define MAF_2_AMI_EN 3 ++#define MAF_3_AMI_EN 4 ++ ++#define IRQ_STATUS1 _SFR_MEM8(0xBF) ++#define TX_START 0 ++#define MAF_0_AMI 1 ++#define MAF_1_AMI 2 ++#define MAF_2_AMI 3 ++#define MAF_3_AMI 4 ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++#define UCPHA0 1 ++#define UDORD0 2 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0xC6) ++ ++/* Reserved [0xC7] */ ++ ++#define UCSR1A _SFR_MEM8(0xC8) ++#define MPCM1 0 ++#define U2X1 1 ++#define UPE1 2 ++#define DOR1 3 ++#define FE1 4 ++#define UDRE1 5 ++#define TXC1 6 ++#define RXC1 7 ++ ++#define UCSR1B _SFR_MEM8(0xC9) ++#define TXB81 0 ++#define RXB81 1 ++#define UCSZ12 2 ++#define TXEN1 3 ++#define RXEN1 4 ++#define UDRIE1 5 ++#define TXCIE1 6 ++#define RXCIE1 7 ++ ++#define UCSR1C _SFR_MEM8(0xCA) ++#define UCPOL1 0 ++#define UCSZ10 1 ++#define UCSZ11 2 ++#define USBS1 3 ++#define UPM10 4 ++#define UPM11 5 ++#define UMSEL10 6 ++#define UMSEL11 7 ++#define UCPHA1 1 ++#define UDORD1 2 ++ ++/* Reserved [0xCB] */ ++ ++/* Combine UBRR1L and UBRR1H */ ++#define UBRR1 _SFR_MEM16(0xCC) ++ ++#define UBRR1L _SFR_MEM8(0xCC) ++#define UBRR1H _SFR_MEM8(0xCD) ++ ++#define UDR1 _SFR_MEM8(0xCE) ++ ++/* Reserved [0xCF..0xD6] */ ++ ++#define SCRSTRLL _SFR_MEM8(0xD7) ++#define SCRSTRLL0 0 ++#define SCRSTRLL1 1 ++#define SCRSTRLL2 2 ++#define SCRSTRLL3 3 ++#define SCRSTRLL4 4 ++#define SCRSTRLL5 5 ++#define SCRSTRLL6 6 ++#define SCRSTRLL7 7 ++ ++#define SCRSTRLH _SFR_MEM8(0xD8) ++#define SCRSTRLH0 0 ++#define SCRSTRLH1 1 ++#define SCRSTRLH2 2 ++#define SCRSTRLH3 3 ++#define SCRSTRLH4 4 ++#define SCRSTRLH5 5 ++#define SCRSTRLH6 6 ++#define SCRSTRLH7 7 ++ ++#define SCRSTRHL _SFR_MEM8(0xD9) ++#define SCRSTRHL0 0 ++#define SCRSTRHL1 1 ++#define SCRSTRHL2 2 ++#define SCRSTRHL3 3 ++#define SCRSTRHL4 4 ++#define SCRSTRHL5 5 ++#define SCRSTRHL6 6 ++#define SCRSTRHL7 7 ++ ++#define SCRSTRHH _SFR_MEM8(0xDA) ++#define SCRSTRHH0 0 ++#define SCRSTRHH1 1 ++#define SCRSTRHH2 2 ++#define SCRSTRHH3 3 ++#define SCRSTRHH4 4 ++#define SCRSTRHH5 5 ++#define SCRSTRHH6 6 ++#define SCRSTRHH7 7 ++ ++#define SCCSR _SFR_MEM8(0xDB) ++#define SCCS10 0 ++#define SCCS11 1 ++#define SCCS20 2 ++#define SCCS21 3 ++#define SCCS30 4 ++#define SCCS31 5 ++ ++#define SCCR0 _SFR_MEM8(0xDC) ++#define SCCMP1 0 ++#define SCCMP2 1 ++#define SCCMP3 2 ++#define SCTSE 3 ++#define SCCKSEL 4 ++#define SCEN 5 ++#define SCMBTS 6 ++#define SCRES 7 ++ ++#define SCCR1 _SFR_MEM8(0xDD) ++#define SCENBO 0 ++#define SCEECLK 1 ++#define SCCKDIV0 2 ++#define SCCKDIV1 3 ++#define SCCKDIV2 4 ++#define SCBTSM 5 ++ ++#define SCSR _SFR_MEM8(0xDE) ++#define SCBSY 0 ++ ++#define SCIRQM _SFR_MEM8(0xDF) ++#define IRQMCP1 0 ++#define IRQMCP2 1 ++#define IRQMCP3 2 ++#define IRQMOF 3 ++#define IRQMBO 4 ++ ++#define SCIRQS _SFR_MEM8(0xE0) ++#define IRQSCP1 0 ++#define IRQSCP2 1 ++#define IRQSCP3 2 ++#define IRQSOF 3 ++#define IRQSBO 4 ++ ++#define SCCNTLL _SFR_MEM8(0xE1) ++#define SCCNTLL0 0 ++#define SCCNTLL1 1 ++#define SCCNTLL2 2 ++#define SCCNTLL3 3 ++#define SCCNTLL4 4 ++#define SCCNTLL5 5 ++#define SCCNTLL6 6 ++#define SCCNTLL7 7 ++ ++#define SCCNTLH _SFR_MEM8(0xE2) ++#define SCCNTLH0 0 ++#define SCCNTLH1 1 ++#define SCCNTLH2 2 ++#define SCCNTLH3 3 ++#define SCCNTLH4 4 ++#define SCCNTLH5 5 ++#define SCCNTLH6 6 ++#define SCCNTLH7 7 ++ ++#define SCCNTHL _SFR_MEM8(0xE3) ++#define SCCNTHL0 0 ++#define SCCNTHL1 1 ++#define SCCNTHL2 2 ++#define SCCNTHL3 3 ++#define SCCNTHL4 4 ++#define SCCNTHL5 5 ++#define SCCNTHL6 6 ++#define SCCNTHL7 7 ++ ++#define SCCNTHH _SFR_MEM8(0xE4) ++#define SCCNTHH0 0 ++#define SCCNTHH1 1 ++#define SCCNTHH2 2 ++#define SCCNTHH3 3 ++#define SCCNTHH4 4 ++#define SCCNTHH5 5 ++#define SCCNTHH6 6 ++#define SCCNTHH7 7 ++ ++#define SCBTSRLL _SFR_MEM8(0xE5) ++#define SCBTSRLL0 0 ++#define SCBTSRLL1 1 ++#define SCBTSRLL2 2 ++#define SCBTSRLL3 3 ++#define SCBTSRLL4 4 ++#define SCBTSRLL5 5 ++#define SCBTSRLL6 6 ++#define SCBTSRLL7 7 ++ ++#define SCBTSRLH _SFR_MEM8(0xE6) ++#define SCBTSRLH0 0 ++#define SCBTSRLH1 1 ++#define SCBTSRLH2 2 ++#define SCBTSRLH3 3 ++#define SCBTSRLH4 4 ++#define SCBTSRLH5 5 ++#define SCBTSRLH6 6 ++#define SCBTSRLH7 7 ++ ++#define SCBTSRHL _SFR_MEM8(0xE7) ++#define SCBTSRHL0 0 ++#define SCBTSRHL1 1 ++#define SCBTSRHL2 2 ++#define SCBTSRHL3 3 ++#define SCBTSRHL4 4 ++#define SCBTSRHL5 5 ++#define SCBTSRHL6 6 ++#define SCBTSRHL7 7 ++ ++#define SCBTSRHH _SFR_MEM8(0xE8) ++#define SCBTSRHH0 0 ++#define SCBTSRHH1 1 ++#define SCBTSRHH2 2 ++#define SCBTSRHH3 3 ++#define SCBTSRHH4 4 ++#define SCBTSRHH5 5 ++#define SCBTSRHH6 6 ++#define SCBTSRHH7 7 ++ ++#define SCTSRLL _SFR_MEM8(0xE9) ++#define SCTSRLL0 0 ++#define SCTSRLL1 1 ++#define SCTSRLL2 2 ++#define SCTSRLL3 3 ++#define SCTSRLL4 4 ++#define SCTSRLL5 5 ++#define SCTSRLL6 6 ++#define SCTSRLL7 7 ++ ++#define SCTSRLH _SFR_MEM8(0xEA) ++#define SCTSRLH0 0 ++#define SCTSRLH1 1 ++#define SCTSRLH2 2 ++#define SCTSRLH3 3 ++#define SCTSRLH4 4 ++#define SCTSRLH5 5 ++#define SCTSRLH6 6 ++#define SCTSRLH7 7 ++ ++#define SCTSRHL _SFR_MEM8(0xEB) ++#define SCTSRHL0 0 ++#define SCTSRHL1 1 ++#define SCTSRHL2 2 ++#define SCTSRHL3 3 ++#define SCTSRHL4 4 ++#define SCTSRHL5 5 ++#define SCTSRHL6 6 ++#define SCTSRHL7 7 ++ ++#define SCTSRHH _SFR_MEM8(0xEC) ++#define SCTSRHH0 0 ++#define SCTSRHH1 1 ++#define SCTSRHH2 2 ++#define SCTSRHH3 3 ++#define SCTSRHH4 4 ++#define SCTSRHH5 5 ++#define SCTSRHH6 6 ++#define SCTSRHH7 7 ++ ++#define SCOCR3LL _SFR_MEM8(0xED) ++#define SCOCR3LL0 0 ++#define SCOCR3LL1 1 ++#define SCOCR3LL2 2 ++#define SCOCR3LL3 3 ++#define SCOCR3LL4 4 ++#define SCOCR3LL5 5 ++#define SCOCR3LL6 6 ++#define SCOCR3LL7 7 ++ ++#define SCOCR3LH _SFR_MEM8(0xEE) ++#define SCOCR3LH0 0 ++#define SCOCR3LH1 1 ++#define SCOCR3LH2 2 ++#define SCOCR3LH3 3 ++#define SCOCR3LH4 4 ++#define SCOCR3LH5 5 ++#define SCOCR3LH6 6 ++#define SCOCR3LH7 7 ++ ++#define SCOCR3HL _SFR_MEM8(0xEF) ++#define SCOCR3HL0 0 ++#define SCOCR3HL1 1 ++#define SCOCR3HL2 2 ++#define SCOCR3HL3 3 ++#define SCOCR3HL4 4 ++#define SCOCR3HL5 5 ++#define SCOCR3HL6 6 ++#define SCOCR3HL7 7 ++ ++#define SCOCR3HH _SFR_MEM8(0xF0) ++#define SCOCR3HH0 0 ++#define SCOCR3HH1 1 ++#define SCOCR3HH2 2 ++#define SCOCR3HH3 3 ++#define SCOCR3HH4 4 ++#define SCOCR3HH5 5 ++#define SCOCR3HH6 6 ++#define SCOCR3HH7 7 ++ ++#define SCOCR2LL _SFR_MEM8(0xF1) ++#define SCOCR2LL0 0 ++#define SCOCR2LL1 1 ++#define SCOCR2LL2 2 ++#define SCOCR2LL3 3 ++#define SCOCR2LL4 4 ++#define SCOCR2LL5 5 ++#define SCOCR2LL6 6 ++#define SCOCR2LL7 7 ++ ++#define SCOCR2LH _SFR_MEM8(0xF2) ++#define SCOCR2LH0 0 ++#define SCOCR2LH1 1 ++#define SCOCR2LH2 2 ++#define SCOCR2LH3 3 ++#define SCOCR2LH4 4 ++#define SCOCR2LH5 5 ++#define SCOCR2LH6 6 ++#define SCOCR2LH7 7 ++ ++#define SCOCR2HL _SFR_MEM8(0xF3) ++#define SCOCR2HL0 0 ++#define SCOCR2HL1 1 ++#define SCOCR2HL2 2 ++#define SCOCR2HL3 3 ++#define SCOCR2HL4 4 ++#define SCOCR2HL5 5 ++#define SCOCR2HL6 6 ++#define SCOCR2HL7 7 ++ ++#define SCOCR2HH _SFR_MEM8(0xF4) ++#define SCOCR2HH0 0 ++#define SCOCR2HH1 1 ++#define SCOCR2HH2 2 ++#define SCOCR2HH3 3 ++#define SCOCR2HH4 4 ++#define SCOCR2HH5 5 ++#define SCOCR2HH6 6 ++#define SCOCR2HH7 7 ++ ++#define SCOCR1LL _SFR_MEM8(0xF5) ++#define SCOCR1LL0 0 ++#define SCOCR1LL1 1 ++#define SCOCR1LL2 2 ++#define SCOCR1LL3 3 ++#define SCOCR1LL4 4 ++#define SCOCR1LL5 5 ++#define SCOCR1LL6 6 ++#define SCOCR1LL7 7 ++ ++#define SCOCR1LH _SFR_MEM8(0xF6) ++#define SCOCR1LH0 0 ++#define SCOCR1LH1 1 ++#define SCOCR1LH2 2 ++#define SCOCR1LH3 3 ++#define SCOCR1LH4 4 ++#define SCOCR1LH5 5 ++#define SCOCR1LH6 6 ++#define SCOCR1LH7 7 ++ ++#define SCOCR1HL _SFR_MEM8(0xF7) ++#define SCOCR1HL0 0 ++#define SCOCR1HL1 1 ++#define SCOCR1HL2 2 ++#define SCOCR1HL3 3 ++#define SCOCR1HL4 4 ++#define SCOCR1HL5 5 ++#define SCOCR1HL6 6 ++#define SCOCR1HL7 7 ++ ++#define SCOCR1HH _SFR_MEM8(0xF8) ++#define SCOCR1HH0 0 ++#define SCOCR1HH1 1 ++#define SCOCR1HH2 2 ++#define SCOCR1HH3 3 ++#define SCOCR1HH4 4 ++#define SCOCR1HH5 5 ++#define SCOCR1HH6 6 ++#define SCOCR1HH7 7 ++ ++#define SCTSTRLL _SFR_MEM8(0xF9) ++#define SCTSTRLL0 0 ++#define SCTSTRLL1 1 ++#define SCTSTRLL2 2 ++#define SCTSTRLL3 3 ++#define SCTSTRLL4 4 ++#define SCTSTRLL5 5 ++#define SCTSTRLL6 6 ++#define SCTSTRLL7 7 ++ ++#define SCTSTRLH _SFR_MEM8(0xFA) ++#define SCTSTRLH0 0 ++#define SCTSTRLH1 1 ++#define SCTSTRLH2 2 ++#define SCTSTRLH3 3 ++#define SCTSTRLH4 4 ++#define SCTSTRLH5 5 ++#define SCTSTRLH6 6 ++#define SCTSTRLH7 7 ++ ++#define SCTSTRHL _SFR_MEM8(0xFB) ++#define SCTSTRHL0 0 ++#define SCTSTRHL1 1 ++#define SCTSTRHL2 2 ++#define SCTSTRHL3 3 ++#define SCTSTRHL4 4 ++#define SCTSTRHL5 5 ++#define SCTSTRHL6 6 ++#define SCTSTRHL7 7 ++ ++#define SCTSTRHH _SFR_MEM8(0xFC) ++#define SCTSTRHH0 0 ++#define SCTSTRHH1 1 ++#define SCTSTRHH2 2 ++#define SCTSTRHH3 3 ++#define SCTSTRHH4 4 ++#define SCTSTRHH5 5 ++#define SCTSTRHH6 6 ++#define SCTSTRHH7 7 ++ ++/* Reserved [0xFD..0x10B] */ ++ ++#define MAFCR0 _SFR_MEM8(0x10C) ++#define MAF0EN 0 ++#define MAF1EN 1 ++#define MAF2EN 2 ++#define MAF3EN 3 ++ ++#define MAFCR1 _SFR_MEM8(0x10D) ++#define AACK_0_I_AM_COORD 0 ++#define AACK_0_SET_PD 1 ++#define AACK_1_I_AM_COORD 2 ++#define AACK_1_SET_PD 3 ++#define AACK_2_I_AM_COORD 4 ++#define AACK_2_SET_PD 5 ++#define AACK_3_I_AM_COORD 6 ++#define AACK_3_SET_PD 7 ++ ++#define MAFSA0L _SFR_MEM8(0x10E) ++#define MAFSA0L0 0 ++#define MAFSA0L1 1 ++#define MAFSA0L2 2 ++#define MAFSA0L3 3 ++#define MAFSA0L4 4 ++#define MAFSA0L5 5 ++#define MAFSA0L6 6 ++#define MAFSA0L7 7 ++ ++#define MAFSA0H _SFR_MEM8(0x10F) ++#define MAFSA0H0 0 ++#define MAFSA0H1 1 ++#define MAFSA0H2 2 ++#define MAFSA0H3 3 ++#define MAFSA0H4 4 ++#define MAFSA0H5 5 ++#define MAFSA0H6 6 ++#define MAFSA0H7 7 ++ ++#define MAFPA0L _SFR_MEM8(0x110) ++#define MAFPA0L0 0 ++#define MAFPA0L1 1 ++#define MAFPA0L2 2 ++#define MAFPA0L3 3 ++#define MAFPA0L4 4 ++#define MAFPA0L5 5 ++#define MAFPA0L6 6 ++#define MAFPA0L7 7 ++ ++#define MAFPA0H _SFR_MEM8(0x111) ++#define MAFPA0H0 0 ++#define MAFPA0H1 1 ++#define MAFPA0H2 2 ++#define MAFPA0H3 3 ++#define MAFPA0H4 4 ++#define MAFPA0H5 5 ++#define MAFPA0H6 6 ++#define MAFPA0H7 7 ++ ++#define MAFSA1L _SFR_MEM8(0x112) ++#define MAFSA1L0 0 ++#define MAFSA1L1 1 ++#define MAFSA1L2 2 ++#define MAFSA1L3 3 ++#define MAFSA1L4 4 ++#define MAFSA1L5 5 ++#define MAFSA1L6 6 ++#define MAFSA1L7 7 ++ ++#define MAFSA1H _SFR_MEM8(0x113) ++#define MAFSA1H0 0 ++#define MAFSA1H1 1 ++#define MAFSA1H2 2 ++#define MAFSA1H3 3 ++#define MAFSA1H4 4 ++#define MAFSA1H5 5 ++#define MAFSA1H6 6 ++#define MAFSA1H7 7 ++ ++#define MAFPA1L _SFR_MEM8(0x114) ++#define MAFPA1L0 0 ++#define MAFPA1L1 1 ++#define MAFPA1L2 2 ++#define MAFPA1L3 3 ++#define MAFPA1L4 4 ++#define MAFPA1L5 5 ++#define MAFPA1L6 6 ++#define MAFPA1L7 7 ++ ++#define MAFPA1H _SFR_MEM8(0x115) ++#define MAFPA1H0 0 ++#define MAFPA1H1 1 ++#define MAFPA1H2 2 ++#define MAFPA1H3 3 ++#define MAFPA1H4 4 ++#define MAFPA1H5 5 ++#define MAFPA1H6 6 ++#define MAFPA1H7 7 ++ ++#define MAFSA2L _SFR_MEM8(0x116) ++#define MAFSA2L0 0 ++#define MAFSA2L1 1 ++#define MAFSA2L2 2 ++#define MAFSA2L3 3 ++#define MAFSA2L4 4 ++#define MAFSA2L5 5 ++#define MAFSA2L6 6 ++#define MAFSA2L7 7 ++ ++#define MAFSA2H _SFR_MEM8(0x117) ++#define MAFSA2H0 0 ++#define MAFSA2H1 1 ++#define MAFSA2H2 2 ++#define MAFSA2H3 3 ++#define MAFSA2H4 4 ++#define MAFSA2H5 5 ++#define MAFSA2H6 6 ++#define MAFSA2H7 7 ++ ++#define MAFPA2L _SFR_MEM8(0x118) ++#define MAFPA2L0 0 ++#define MAFPA2L1 1 ++#define MAFPA2L2 2 ++#define MAFPA2L3 3 ++#define MAFPA2L4 4 ++#define MAFPA2L5 5 ++#define MAFPA2L6 6 ++#define MAFPA2L7 7 ++ ++#define MAFPA2H _SFR_MEM8(0x119) ++#define MAFPA2H0 0 ++#define MAFPA2H1 1 ++#define MAFPA2H2 2 ++#define MAFPA2H3 3 ++#define MAFPA2H4 4 ++#define MAFPA2H5 5 ++#define MAFPA2H6 6 ++#define MAFPA2H7 7 ++ ++#define MAFSA3L _SFR_MEM8(0x11A) ++#define MAFSA3L0 0 ++#define MAFSA3L1 1 ++#define MAFSA3L2 2 ++#define MAFSA3L3 3 ++#define MAFSA3L4 4 ++#define MAFSA3L5 5 ++#define MAFSA3L6 6 ++#define MAFSA3L7 7 ++ ++#define MAFSA3H _SFR_MEM8(0x11B) ++#define MAFSA3H0 0 ++#define MAFSA3H1 1 ++#define MAFSA3H2 2 ++#define MAFSA3H3 3 ++#define MAFSA3H4 4 ++#define MAFSA3H5 5 ++#define MAFSA3H6 6 ++#define MAFSA3H7 7 ++ ++#define MAFPA3L _SFR_MEM8(0x11C) ++#define MAFPA3L0 0 ++#define MAFPA3L1 1 ++#define MAFPA3L2 2 ++#define MAFPA3L3 3 ++#define MAFPA3L4 4 ++#define MAFPA3L5 5 ++#define MAFPA3L6 6 ++#define MAFPA3L7 7 ++ ++#define MAFPA3H _SFR_MEM8(0x11D) ++#define MAFPA3H0 0 ++#define MAFPA3H1 1 ++#define MAFPA3H2 2 ++#define MAFPA3H3 3 ++#define MAFPA3H4 4 ++#define MAFPA3H5 5 ++#define MAFPA3H6 6 ++#define MAFPA3H7 7 ++ ++/* Reserved [0x11E..0x11F] */ ++ ++#define TCCR5A _SFR_MEM8(0x120) ++#define WGM50 0 ++#define WGM51 1 ++#define COM5C0 2 ++#define COM5C1 3 ++#define COM5B0 4 ++#define COM5B1 5 ++#define COM5A0 6 ++#define COM5A1 7 ++ ++#define TCCR5B _SFR_MEM8(0x121) ++#define CS50 0 ++#define CS51 1 ++#define CS52 2 ++#define WGM52 3 ++#define WGM53 4 ++#define ICES5 6 ++#define ICNC5 7 ++ ++#define TCCR5C _SFR_MEM8(0x122) ++#define FOC5C 5 ++#define FOC5B 6 ++#define FOC5A 7 ++ ++/* Reserved [0x123] */ ++ ++/* Combine TCNT5L and TCNT5H */ ++#define TCNT5 _SFR_MEM16(0x124) ++ ++#define TCNT5L _SFR_MEM8(0x124) ++#define TCNT5H _SFR_MEM8(0x125) ++ ++/* Combine ICR5L and ICR5H */ ++#define ICR5 _SFR_MEM16(0x126) ++ ++#define ICR5L _SFR_MEM8(0x126) ++#define ICR5H _SFR_MEM8(0x127) ++ ++/* Combine OCR5AL and OCR5AH */ ++#define OCR5A _SFR_MEM16(0x128) ++ ++#define OCR5AL _SFR_MEM8(0x128) ++#define OCR5AH _SFR_MEM8(0x129) ++ ++/* Combine OCR5BL and OCR5BH */ ++#define OCR5B _SFR_MEM16(0x12A) ++ ++#define OCR5BL _SFR_MEM8(0x12A) ++#define OCR5BH _SFR_MEM8(0x12B) ++ ++/* Combine OCR5CL and OCR5CH */ ++#define OCR5C _SFR_MEM16(0x12C) ++ ++#define OCR5CL _SFR_MEM8(0x12C) ++#define OCR5CH _SFR_MEM8(0x12D) ++ ++/* Reserved [0x12E] */ ++ ++#define LLCR _SFR_MEM8(0x12F) ++#define LLENCAL 0 ++#define LLSHORT 1 ++#define LLTCO 2 ++#define LLCAL 3 ++#define LLCOMP 4 ++#define LLDONE 5 ++ ++#define LLDRL _SFR_MEM8(0x130) ++#define LLDRL0 0 ++#define LLDRL1 1 ++#define LLDRL2 2 ++#define LLDRL3 3 ++ ++#define LLDRH _SFR_MEM8(0x131) ++#define LLDRH0 0 ++#define LLDRH1 1 ++#define LLDRH2 2 ++#define LLDRH3 3 ++#define LLDRH4 4 ++ ++#define DRTRAM3 _SFR_MEM8(0x132) ++#define ENDRT 4 ++#define DRTSWOK 5 ++ ++#define DRTRAM2 _SFR_MEM8(0x133) ++ ++#define DRTRAM1 _SFR_MEM8(0x134) ++ ++#define DRTRAM0 _SFR_MEM8(0x135) ++ ++#define DPDS0 _SFR_MEM8(0x136) ++#define PBDRV0 0 ++#define PBDRV1 1 ++#define PDDRV0 2 ++#define PDDRV1 3 ++#define PEDRV0 4 ++#define PEDRV1 5 ++#define PFDRV0 6 ++#define PFDRV1 7 ++ ++#define DPDS1 _SFR_MEM8(0x137) ++#define PGDRV0 0 ++#define PGDRV1 1 ++ ++#define PARCR _SFR_MEM8(0x138) ++#define PARUFI 0 ++#define PARDFI 1 ++#define PALTU0 2 ++#define PALTU1 3 ++#define PALTU2 4 ++#define PALTD0 5 ++#define PALTD1 6 ++#define PALTD2 7 ++ ++#define TRXPR _SFR_MEM8(0x139) ++#define TRXRST 0 ++#define SLPTR 1 ++ ++/* Reserved [0x13A..0x13B] */ ++ ++#define AES_CTRL _SFR_MEM8(0x13C) ++#define AES_IM 2 ++#define AES_DIR 3 ++#define AES_MODE 5 ++#define AES_REQUEST 7 ++ ++#define AES_STATUS _SFR_MEM8(0x13D) ++#define AES_DONE 0 ++#define AES_ER 7 ++ ++#define AES_STATE _SFR_MEM8(0x13E) ++#define AES_STATE0 0 ++#define AES_STATE1 1 ++#define AES_STATE2 2 ++#define AES_STATE3 3 ++#define AES_STATE4 4 ++#define AES_STATE5 5 ++#define AES_STATE6 6 ++#define AES_STATE7 7 ++ ++#define AES_KEY _SFR_MEM8(0x13F) ++#define AES_KEY0 0 ++#define AES_KEY1 1 ++#define AES_KEY2 2 ++#define AES_KEY3 3 ++#define AES_KEY4 4 ++#define AES_KEY5 5 ++#define AES_KEY6 6 ++#define AES_KEY7 7 ++ ++/* Reserved [0x140] */ ++ ++#define TRX_STATUS _SFR_MEM8(0x141) ++#define TRX_STATUS0 0 ++#define TRX_STATUS1 1 ++#define TRX_STATUS2 2 ++#define TRX_STATUS3 3 ++#define TRX_STATUS4 4 ++#define TST_STATUS 5 ++#define CCA_STATUS 6 ++#define CCA_DONE 7 ++ ++#define TRX_STATE _SFR_MEM8(0x142) ++#define TRX_CMD0 0 ++#define TRX_CMD1 1 ++#define TRX_CMD2 2 ++#define TRX_CMD3 3 ++#define TRX_CMD4 4 ++#define TRAC_STATUS0 5 ++#define TRAC_STATUS1 6 ++#define TRAC_STATUS2 7 ++ ++#define TRX_CTRL_0 _SFR_MEM8(0x143) ++#define PMU_IF_INV 4 ++#define PMU_START 5 ++#define PMU_EN 6 ++#define Res7 7 ++ ++#define TRX_CTRL_1 _SFR_MEM8(0x144) ++#define PLL_TX_FLT 4 ++#define TX_AUTO_CRC_ON 5 ++#define IRQ_2_EXT_EN 6 ++#define PA_EXT_EN 7 ++ ++#define PHY_TX_PWR _SFR_MEM8(0x145) ++#define TX_PWR0 0 ++#define TX_PWR1 1 ++#define TX_PWR2 2 ++#define TX_PWR3 3 ++ ++#define PHY_RSSI _SFR_MEM8(0x146) ++#define RSSI0 0 ++#define RSSI1 1 ++#define RSSI2 2 ++#define RSSI3 3 ++#define RSSI4 4 ++#define RND_VALUE0 5 ++#define RND_VALUE1 6 ++#define RX_CRC_VALID 7 ++ ++#define PHY_ED_LEVEL _SFR_MEM8(0x147) ++#define ED_LEVEL0 0 ++#define ED_LEVEL1 1 ++#define ED_LEVEL2 2 ++#define ED_LEVEL3 3 ++#define ED_LEVEL4 4 ++#define ED_LEVEL5 5 ++#define ED_LEVEL6 6 ++#define ED_LEVEL7 7 ++ ++#define PHY_CC_CCA _SFR_MEM8(0x148) ++#define CHANNEL0 0 ++#define CHANNEL1 1 ++#define CHANNEL2 2 ++#define CHANNEL3 3 ++#define CHANNEL4 4 ++#define CCA_MODE0 5 ++#define CCA_MODE1 6 ++#define CCA_REQUEST 7 ++ ++#define CCA_THRES _SFR_MEM8(0x149) ++#define CCA_ED_THRES0 0 ++#define CCA_ED_THRES1 1 ++#define CCA_ED_THRES2 2 ++#define CCA_ED_THRES3 3 ++#define CCA_CS_THRES0 4 ++#define CCA_CS_THRES1 5 ++#define CCA_CS_THRES2 6 ++#define CCA_CS_THRES3 7 ++ ++#define RX_CTRL _SFR_MEM8(0x14A) ++#define PDT_THRES0 0 ++#define PDT_THRES1 1 ++#define PDT_THRES2 2 ++#define PDT_THRES3 3 ++ ++#define SFD_VALUE _SFR_MEM8(0x14B) ++#define SFD_VALUE0 0 ++#define SFD_VALUE1 1 ++#define SFD_VALUE2 2 ++#define SFD_VALUE3 3 ++#define SFD_VALUE4 4 ++#define SFD_VALUE5 5 ++#define SFD_VALUE6 6 ++#define SFD_VALUE7 7 ++ ++#define TRX_CTRL_2 _SFR_MEM8(0x14C) ++#define OQPSK_DATA_RATE0 0 ++#define OQPSK_DATA_RATE1 1 ++#define RX_SAFE_MODE 7 ++ ++#define ANT_DIV _SFR_MEM8(0x14D) ++#define ANT_CTRL0 0 ++#define ANT_CTRL1 1 ++#define ANT_EXT_SW_EN 2 ++#define ANT_DIV_EN 3 ++#define ANT_SEL 7 ++ ++#define IRQ_MASK _SFR_MEM8(0x14E) ++#define PLL_LOCK_EN 0 ++#define PLL_UNLOCK_EN 1 ++#define RX_START_EN 2 ++#define RX_END_EN 3 ++#define CCA_ED_DONE_EN 4 ++#define AMI_EN 5 ++#define TX_END_EN 6 ++#define AWAKE_EN 7 ++ ++#define IRQ_STATUS _SFR_MEM8(0x14F) ++#define PLL_LOCK 0 ++#define PLL_UNLOCK 1 ++#define RX_START 2 ++#define RX_END 3 ++#define CCA_ED_DONE 4 ++#define AMI 5 ++#define TX_END 6 ++#define AWAKE 7 ++ ++#define VREG_CTRL _SFR_MEM8(0x150) ++#define DVDD_OK 2 ++#define DVREG_EXT 3 ++#define AVDD_OK 6 ++#define AVREG_EXT 7 ++ ++#define BATMON _SFR_MEM8(0x151) ++#define BATMON_VTH0 0 ++#define BATMON_VTH1 1 ++#define BATMON_VTH2 2 ++#define BATMON_VTH3 3 ++#define BATMON_HR 4 ++#define BATMON_OK 5 ++#define BAT_LOW_EN 6 ++#define BAT_LOW 7 ++ ++#define XOSC_CTRL _SFR_MEM8(0x152) ++#define XTAL_TRIM0 0 ++#define XTAL_TRIM1 1 ++#define XTAL_TRIM2 2 ++#define XTAL_TRIM3 3 ++#define XTAL_MODE0 4 ++#define XTAL_MODE1 5 ++#define XTAL_MODE2 6 ++#define XTAL_MODE3 7 ++ ++#define CC_CTRL_0 _SFR_MEM8(0x153) ++#define CC_NUMBER0 0 ++#define CC_NUMBER1 1 ++#define CC_NUMBER2 2 ++#define CC_NUMBER3 3 ++#define CC_NUMBER4 4 ++#define CC_NUMBER5 5 ++#define CC_NUMBER6 6 ++#define CC_NUMBER7 7 ++ ++#define CC_CTRL_1 _SFR_MEM8(0x154) ++#define CC_BAND0 0 ++#define CC_BAND1 1 ++#define CC_BAND2 2 ++#define CC_BAND3 3 ++ ++#define RX_SYN _SFR_MEM8(0x155) ++#define RX_PDT_LEVEL0 0 ++#define RX_PDT_LEVEL1 1 ++#define RX_PDT_LEVEL2 2 ++#define RX_PDT_LEVEL3 3 ++#define RX_OVERRIDE 6 ++#define RX_PDT_DIS 7 ++ ++#define TRX_RPC _SFR_MEM8(0x156) ++#define XAH_RPC_EN 0 ++#define IPAN_RPC_EN 1 ++#define PLL_RPC_EN 3 ++#define PDT_RPC_EN 4 ++#define RX_RPC_EN 5 ++#define RX_RPC_CTRL0 6 ++#define RX_RPC_CTRL1 7 ++ ++#define XAH_CTRL_1 _SFR_MEM8(0x157) ++#define AACK_PROM_MODE 1 ++#define AACK_ACK_TIME 2 ++#define AACK_UPLD_RES_FT 4 ++#define AACK_FLTR_RES_FT 5 ++ ++#define FTN_CTRL _SFR_MEM8(0x158) ++#define FTN_START 7 ++ ++/* Reserved [0x159] */ ++ ++#define PLL_CF _SFR_MEM8(0x15A) ++#define PLL_CF_START 7 ++ ++#define PLL_DCU _SFR_MEM8(0x15B) ++#define PLL_DCU_START 7 ++ ++#define PART_NUM _SFR_MEM8(0x15C) ++#define PART_NUM0 0 ++#define PART_NUM1 1 ++#define PART_NUM2 2 ++#define PART_NUM3 3 ++#define PART_NUM4 4 ++#define PART_NUM5 5 ++#define PART_NUM6 6 ++#define PART_NUM7 7 ++ ++#define VERSION_NUM _SFR_MEM8(0x15D) ++#define VERSION_NUM0 0 ++#define VERSION_NUM1 1 ++#define VERSION_NUM2 2 ++#define VERSION_NUM3 3 ++#define VERSION_NUM4 4 ++#define VERSION_NUM5 5 ++#define VERSION_NUM6 6 ++#define VERSION_NUM7 7 ++ ++#define MAN_ID_0 _SFR_MEM8(0x15E) ++#define MAN_ID_00 0 ++#define MAN_ID_01 1 ++#define MAN_ID_02 2 ++#define MAN_ID_03 3 ++#define MAN_ID_04 4 ++#define MAN_ID_05 5 ++#define MAN_ID_06 6 ++#define MAN_ID_07 7 ++ ++#define MAN_ID_1 _SFR_MEM8(0x15F) ++#define MAN_ID_10 0 ++#define MAN_ID_11 1 ++#define MAN_ID_12 2 ++#define MAN_ID_13 3 ++#define MAN_ID_14 4 ++#define MAN_ID_15 5 ++#define MAN_ID_16 6 ++#define MAN_ID_17 7 ++ ++#define SHORT_ADDR_0 _SFR_MEM8(0x160) ++#define SHORT_ADDR_00 0 ++#define SHORT_ADDR_01 1 ++#define SHORT_ADDR_02 2 ++#define SHORT_ADDR_03 3 ++#define SHORT_ADDR_04 4 ++#define SHORT_ADDR_05 5 ++#define SHORT_ADDR_06 6 ++#define SHORT_ADDR_07 7 ++ ++#define SHORT_ADDR_1 _SFR_MEM8(0x161) ++#define SHORT_ADDR_10 0 ++#define SHORT_ADDR_11 1 ++#define SHORT_ADDR_12 2 ++#define SHORT_ADDR_13 3 ++#define SHORT_ADDR_14 4 ++#define SHORT_ADDR_15 5 ++#define SHORT_ADDR_16 6 ++#define SHORT_ADDR_17 7 ++ ++#define PAN_ID_0 _SFR_MEM8(0x162) ++#define PAN_ID_00 0 ++#define PAN_ID_01 1 ++#define PAN_ID_02 2 ++#define PAN_ID_03 3 ++#define PAN_ID_04 4 ++#define PAN_ID_05 5 ++#define PAN_ID_06 6 ++#define PAN_ID_07 7 ++ ++#define PAN_ID_1 _SFR_MEM8(0x163) ++#define PAN_ID_10 0 ++#define PAN_ID_11 1 ++#define PAN_ID_12 2 ++#define PAN_ID_13 3 ++#define PAN_ID_14 4 ++#define PAN_ID_15 5 ++#define PAN_ID_16 6 ++#define PAN_ID_17 7 ++ ++#define IEEE_ADDR_0 _SFR_MEM8(0x164) ++#define IEEE_ADDR_00 0 ++#define IEEE_ADDR_01 1 ++#define IEEE_ADDR_02 2 ++#define IEEE_ADDR_03 3 ++#define IEEE_ADDR_04 4 ++#define IEEE_ADDR_05 5 ++#define IEEE_ADDR_06 6 ++#define IEEE_ADDR_07 7 ++ ++#define IEEE_ADDR_1 _SFR_MEM8(0x165) ++#define IEEE_ADDR_10 0 ++#define IEEE_ADDR_11 1 ++#define IEEE_ADDR_12 2 ++#define IEEE_ADDR_13 3 ++#define IEEE_ADDR_14 4 ++#define IEEE_ADDR_15 5 ++#define IEEE_ADDR_16 6 ++#define IEEE_ADDR_17 7 ++ ++#define IEEE_ADDR_2 _SFR_MEM8(0x166) ++#define IEEE_ADDR_20 0 ++#define IEEE_ADDR_21 1 ++#define IEEE_ADDR_22 2 ++#define IEEE_ADDR_23 3 ++#define IEEE_ADDR_24 4 ++#define IEEE_ADDR_25 5 ++#define IEEE_ADDR_26 6 ++#define IEEE_ADDR_27 7 ++ ++#define IEEE_ADDR_3 _SFR_MEM8(0x167) ++#define IEEE_ADDR_30 0 ++#define IEEE_ADDR_31 1 ++#define IEEE_ADDR_32 2 ++#define IEEE_ADDR_33 3 ++#define IEEE_ADDR_34 4 ++#define IEEE_ADDR_35 5 ++#define IEEE_ADDR_36 6 ++#define IEEE_ADDR_37 7 ++ ++#define IEEE_ADDR_4 _SFR_MEM8(0x168) ++#define IEEE_ADDR_40 0 ++#define IEEE_ADDR_41 1 ++#define IEEE_ADDR_42 2 ++#define IEEE_ADDR_43 3 ++#define IEEE_ADDR_44 4 ++#define IEEE_ADDR_45 5 ++#define IEEE_ADDR_46 6 ++#define IEEE_ADDR_47 7 ++ ++#define IEEE_ADDR_5 _SFR_MEM8(0x169) ++#define IEEE_ADDR_50 0 ++#define IEEE_ADDR_51 1 ++#define IEEE_ADDR_52 2 ++#define IEEE_ADDR_53 3 ++#define IEEE_ADDR_54 4 ++#define IEEE_ADDR_55 5 ++#define IEEE_ADDR_56 6 ++#define IEEE_ADDR_57 7 ++ ++#define IEEE_ADDR_6 _SFR_MEM8(0x16A) ++#define IEEE_ADDR_60 0 ++#define IEEE_ADDR_61 1 ++#define IEEE_ADDR_62 2 ++#define IEEE_ADDR_63 3 ++#define IEEE_ADDR_64 4 ++#define IEEE_ADDR_65 5 ++#define IEEE_ADDR_66 6 ++#define IEEE_ADDR_67 7 ++ ++#define IEEE_ADDR_7 _SFR_MEM8(0x16B) ++#define IEEE_ADDR_70 0 ++#define IEEE_ADDR_71 1 ++#define IEEE_ADDR_72 2 ++#define IEEE_ADDR_73 3 ++#define IEEE_ADDR_74 4 ++#define IEEE_ADDR_75 5 ++#define IEEE_ADDR_76 6 ++#define IEEE_ADDR_77 7 ++ ++#define XAH_CTRL_0 _SFR_MEM8(0x16C) ++#define SLOTTED_OPERATION 0 ++#define MAX_CSMA_RETRIES0 1 ++#define MAX_CSMA_RETRIES1 2 ++#define MAX_CSMA_RETRIES2 3 ++#define MAX_FRAME_RETRIES0 4 ++#define MAX_FRAME_RETRIES1 5 ++#define MAX_FRAME_RETRIES2 6 ++#define MAX_FRAME_RETRIES3 7 ++ ++#define CSMA_SEED_0 _SFR_MEM8(0x16D) ++#define CSMA_SEED_00 0 ++#define CSMA_SEED_01 1 ++#define CSMA_SEED_02 2 ++#define CSMA_SEED_03 3 ++#define CSMA_SEED_04 4 ++#define CSMA_SEED_05 5 ++#define CSMA_SEED_06 6 ++#define CSMA_SEED_07 7 ++ ++#define CSMA_SEED_1 _SFR_MEM8(0x16E) ++#define CSMA_SEED_10 0 ++#define CSMA_SEED_11 1 ++#define CSMA_SEED_12 2 ++#define AACK_I_AM_COORD 3 ++#define AACK_DIS_ACK 4 ++#define AACK_SET_PD 5 ++#define AACK_FVN_MODE0 6 ++#define AACK_FVN_MODE1 7 ++ ++#define CSMA_BE _SFR_MEM8(0x16F) ++#define MIN_BE0 0 ++#define MIN_BE1 1 ++#define MIN_BE2 2 ++#define MIN_BE3 3 ++#define MAX_BE0 4 ++#define MAX_BE1 5 ++#define MAX_BE2 6 ++#define MAX_BE3 7 ++ ++/* Reserved [0x170..0x175] */ ++ ++#define TST_CTRL_DIGI _SFR_MEM8(0x176) ++#define TST_CTRL_DIG0 0 ++#define TST_CTRL_DIG1 1 ++#define TST_CTRL_DIG2 2 ++#define TST_CTRL_DIG3 3 ++ ++/* Reserved [0x177..0x17A] */ ++ ++#define TST_RX_LENGTH _SFR_MEM8(0x17B) ++#define RX_LENGTH0 0 ++#define RX_LENGTH1 1 ++#define RX_LENGTH2 2 ++#define RX_LENGTH3 3 ++#define RX_LENGTH4 4 ++#define RX_LENGTH5 5 ++#define RX_LENGTH6 6 ++#define RX_LENGTH7 7 ++ ++/* Reserved [0x17C..0x17F] */ ++ ++#define TRXFBST _SFR_MEM8(0x180) ++ ++/* Reserved [0x181..0x1FE] */ ++ ++#define TRXFBEND _SFR_MEM8(0x1FF) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect _VECTOR(3) ++#define INT2_vect_num 3 ++ ++/* External Interrupt Request 3 */ ++#define INT3_vect _VECTOR(4) ++#define INT3_vect_num 4 ++ ++/* External Interrupt Request 4 */ ++#define INT4_vect _VECTOR(5) ++#define INT4_vect_num 5 ++ ++/* External Interrupt Request 5 */ ++#define INT5_vect _VECTOR(6) ++#define INT5_vect_num 6 ++ ++/* External Interrupt Request 6 */ ++#define INT6_vect _VECTOR(7) ++#define INT6_vect_num 7 ++ ++/* External Interrupt Request 7 */ ++#define INT7_vect _VECTOR(8) ++#define INT7_vect_num 8 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(9) ++#define PCINT0_vect_num 9 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(10) ++#define PCINT1_vect_num 10 ++ ++/* Pin Change Interrupt Request 2 */ ++#define PCINT2_vect _VECTOR(11) ++#define PCINT2_vect_num 11 ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect _VECTOR(12) ++#define WDT_vect_num 12 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPA_vect _VECTOR(13) ++#define TIMER2_COMPA_vect_num 13 ++ ++/* Timer/Counter2 Compare Match B */ ++#define TIMER2_COMPB_vect _VECTOR(14) ++#define TIMER2_COMPB_vect_num 14 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(15) ++#define TIMER2_OVF_vect_num 15 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(16) ++#define TIMER1_CAPT_vect_num 16 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(17) ++#define TIMER1_COMPA_vect_num 17 ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(18) ++#define TIMER1_COMPB_vect_num 18 ++ ++/* Timer/Counter1 Compare Match C */ ++#define TIMER1_COMPC_vect _VECTOR(19) ++#define TIMER1_COMPC_vect_num 19 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(20) ++#define TIMER1_OVF_vect_num 20 ++ ++/* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPA_vect _VECTOR(21) ++#define TIMER0_COMPA_vect_num 21 ++ ++/* Timer/Counter0 Compare Match B */ ++#define TIMER0_COMPB_vect _VECTOR(22) ++#define TIMER0_COMPB_vect_num 22 ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(23) ++#define TIMER0_OVF_vect_num 23 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(24) ++#define SPI_STC_vect_num 24 ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect _VECTOR(25) ++#define USART0_RX_vect_num 25 ++ ++/* USART0 Data register Empty */ ++#define USART0_UDRE_vect _VECTOR(26) ++#define USART0_UDRE_vect_num 26 ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect _VECTOR(27) ++#define USART0_TX_vect_num 27 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(28) ++#define ANALOG_COMP_vect_num 28 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(29) ++#define ADC_vect_num 29 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(30) ++#define EE_READY_vect_num 30 ++ ++/* Timer/Counter3 Capture Event */ ++#define TIMER3_CAPT_vect _VECTOR(31) ++#define TIMER3_CAPT_vect_num 31 ++ ++/* Timer/Counter3 Compare Match A */ ++#define TIMER3_COMPA_vect _VECTOR(32) ++#define TIMER3_COMPA_vect_num 32 ++ ++/* Timer/Counter3 Compare Match B */ ++#define TIMER3_COMPB_vect _VECTOR(33) ++#define TIMER3_COMPB_vect_num 33 ++ ++/* Timer/Counter3 Compare Match C */ ++#define TIMER3_COMPC_vect _VECTOR(34) ++#define TIMER3_COMPC_vect_num 34 ++ ++/* Timer/Counter3 Overflow */ ++#define TIMER3_OVF_vect _VECTOR(35) ++#define TIMER3_OVF_vect_num 35 ++ ++/* USART1, Rx Complete */ ++#define USART1_RX_vect _VECTOR(36) ++#define USART1_RX_vect_num 36 ++ ++/* USART1 Data register Empty */ ++#define USART1_UDRE_vect _VECTOR(37) ++#define USART1_UDRE_vect_num 37 ++ ++/* USART1, Tx Complete */ ++#define USART1_TX_vect _VECTOR(38) ++#define USART1_TX_vect_num 38 ++ ++/* 2-wire Serial Interface */ ++#define TWI_vect _VECTOR(39) ++#define TWI_vect_num 39 ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect _VECTOR(40) ++#define SPM_READY_vect_num 40 ++ ++/* Timer/Counter4 Capture Event */ ++#define TIMER4_CAPT_vect _VECTOR(41) ++#define TIMER4_CAPT_vect_num 41 ++ ++/* Timer/Counter4 Compare Match A */ ++#define TIMER4_COMPA_vect _VECTOR(42) ++#define TIMER4_COMPA_vect_num 42 ++ ++/* Timer/Counter4 Compare Match B */ ++#define TIMER4_COMPB_vect _VECTOR(43) ++#define TIMER4_COMPB_vect_num 43 ++ ++/* Timer/Counter4 Compare Match C */ ++#define TIMER4_COMPC_vect _VECTOR(44) ++#define TIMER4_COMPC_vect_num 44 ++ ++/* Timer/Counter4 Overflow */ ++#define TIMER4_OVF_vect _VECTOR(45) ++#define TIMER4_OVF_vect_num 45 ++ ++/* Timer/Counter5 Capture Event */ ++#define TIMER5_CAPT_vect _VECTOR(46) ++#define TIMER5_CAPT_vect_num 46 ++ ++/* Timer/Counter5 Compare Match A */ ++#define TIMER5_COMPA_vect _VECTOR(47) ++#define TIMER5_COMPA_vect_num 47 ++ ++/* Timer/Counter5 Compare Match B */ ++#define TIMER5_COMPB_vect _VECTOR(48) ++#define TIMER5_COMPB_vect_num 48 ++ ++/* Timer/Counter5 Compare Match C */ ++#define TIMER5_COMPC_vect _VECTOR(49) ++#define TIMER5_COMPC_vect_num 49 ++ ++/* Timer/Counter5 Overflow */ ++#define TIMER5_OVF_vect _VECTOR(50) ++#define TIMER5_OVF_vect_num 50 ++ ++/* TRX24 - PLL lock interrupt */ ++#define TRX24_PLL_LOCK_vect _VECTOR(57) ++#define TRX24_PLL_LOCK_vect_num 57 ++ ++/* TRX24 - PLL unlock interrupt */ ++#define TRX24_PLL_UNLOCK_vect _VECTOR(58) ++#define TRX24_PLL_UNLOCK_vect_num 58 ++ ++/* TRX24 - Receive start interrupt */ ++#define TRX24_RX_START_vect _VECTOR(59) ++#define TRX24_RX_START_vect_num 59 ++ ++/* TRX24 - RX_END interrupt */ ++#define TRX24_RX_END_vect _VECTOR(60) ++#define TRX24_RX_END_vect_num 60 ++ ++/* TRX24 - CCA/ED done interrupt */ ++#define TRX24_CCA_ED_DONE_vect _VECTOR(61) ++#define TRX24_CCA_ED_DONE_vect_num 61 ++ ++/* TRX24 - XAH - AMI */ ++#define TRX24_XAH_AMI_vect _VECTOR(62) ++#define TRX24_XAH_AMI_vect_num 62 ++ ++/* TRX24 - TX_END interrupt */ ++#define TRX24_TX_END_vect _VECTOR(63) ++#define TRX24_TX_END_vect_num 63 ++ ++/* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */ ++#define TRX24_AWAKE_vect _VECTOR(64) ++#define TRX24_AWAKE_vect_num 64 ++ ++/* Symbol counter - compare match 1 interrupt */ ++#define SCNT_CMP1_vect _VECTOR(65) ++#define SCNT_CMP1_vect_num 65 ++ ++/* Symbol counter - compare match 2 interrupt */ ++#define SCNT_CMP2_vect _VECTOR(66) ++#define SCNT_CMP2_vect_num 66 ++ ++/* Symbol counter - compare match 3 interrupt */ ++#define SCNT_CMP3_vect _VECTOR(67) ++#define SCNT_CMP3_vect_num 67 ++ ++/* Symbol counter - overflow interrupt */ ++#define SCNT_OVFL_vect _VECTOR(68) ++#define SCNT_OVFL_vect_num 68 ++ ++/* Symbol counter - backoff interrupt */ ++#define SCNT_BACKOFF_vect _VECTOR(69) ++#define SCNT_BACKOFF_vect_num 69 ++ ++/* AES engine ready interrupt */ ++#define AES_READY_vect _VECTOR(70) ++#define AES_READY_vect_num 70 ++ ++/* Battery monitor indicates supply voltage below threshold */ ++#define BAT_LOW_vect _VECTOR(71) ++#define BAT_LOW_vect_num 71 ++ ++/* TRX24 TX start interrupt */ ++#define TRX24_TX_START_vect _VECTOR(72) ++#define TRX24_TX_START_vect_num 72 ++ ++/* Address match interrupt of address filter 0 */ ++#define TRX24_AMI0_vect _VECTOR(73) ++#define TRX24_AMI0_vect_num 73 ++ ++/* Address match interrupt of address filter 1 */ ++#define TRX24_AMI1_vect _VECTOR(74) ++#define TRX24_AMI1_vect_num 74 ++ ++/* Address match interrupt of address filter 2 */ ++#define TRX24_AMI2_vect _VECTOR(75) ++#define TRX24_AMI2_vect_num 75 ++ ++/* Address match interrupt of address filter 3 */ ++#define TRX24_AMI3_vect _VECTOR(76) ++#define TRX24_AMI3_vect_num 76 ++ ++#define _VECTORS_SIZE 308 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 256 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x1FFFF ++#define RAMSTART 0x0200 ++#define RAMSIZE 16384 ++#define RAMEND 0x41FF ++#define E2START 0 ++#define E2SIZE 4096 ++#define E2PAGESIZE 8 ++#define E2END 0x0FFF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL_SUT0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL_SUT1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL_SUT2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL_SUT3 (unsigned char)~_BV(3) ++#define FUSE_CKSEL_SUT4 (unsigned char)~_BV(4) ++#define FUSE_CKSEL_SUT5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0xA7 ++#define SIGNATURE_2 0x02 ++ ++ ++#endif /* #ifdef _AVR_ATMEGA128RFR2_H_INCLUDED */ ++ +diff --git a/include/avr/iom16.h b/include/avr/iom16.h +index af7e9f8..3f27da2 100644 +--- a/include/avr/iom16.h ++++ b/include/avr/iom16.h +@@ -1,670 +1,670 @@ +-/* Copyright (c) 2004 Eric B. Weddington +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom16.h 2228 2011-03-05 15:33:19Z arcanum $ */ +- +-/* avr/iom16.h - definitions for ATmega16 */ +- +-#ifndef _AVR_IOM16_H_ +-#define _AVR_IOM16_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom16.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* Registers and associated bit numbers */ +- +-#define TWBR _SFR_IO8(0x00) +- +-#define TWSR _SFR_IO8(0x01) +-#define TWPS0 0 +-#define TWPS1 1 +-#define TWS3 3 +-#define TWS4 4 +-#define TWS5 5 +-#define TWS6 6 +-#define TWS7 7 +- +-#define TWAR _SFR_IO8(0x02) +-#define TWGCE 0 +-#define TWA0 1 +-#define TWA1 2 +-#define TWA2 3 +-#define TWA3 4 +-#define TWA4 5 +-#define TWA5 6 +-#define TWA6 7 +- +-#define TWDR _SFR_IO8(0x03) +- +-/* Combine ADCL and ADCH */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x04) +-#endif +-#define ADCW _SFR_IO16(0x04) +-#define ADCL _SFR_IO8(0x04) +-#define ADCH _SFR_IO8(0x05) +- +-#define ADCSRA _SFR_IO8(0x06) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADMUX _SFR_IO8(0x07) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define ACSR _SFR_IO8(0x08) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define UBRRL _SFR_IO8(0x09) +- +-#define UCSRB _SFR_IO8(0x0A) +-#define TXB8 0 +-#define RXB8 1 +-#define UCSZ2 2 +-#define TXEN 3 +-#define RXEN 4 +-#define UDRIE 5 +-#define TXCIE 6 +-#define RXCIE 7 +- +-#define UCSRA _SFR_IO8(0x0B) +-#define MPCM 0 +-#define U2X 1 +-#define PE 2 +-#define DOR 3 +-#define FE 4 +-#define UDRE 5 +-#define TXC 6 +-#define RXC 7 +- +-#define UDR _SFR_IO8(0x0C) +- +-#define SPCR _SFR_IO8(0x0D) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x0E) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x0F) +- +-#define PIND _SFR_IO8(0x10) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x11) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x12) +-#define PD0 0 +-#define PD1 1 +-#define PD2 2 +-#define PD3 3 +-#define PD4 4 +-#define PD5 5 +-#define PD6 6 +-#define PD7 7 +- +-#define PINC _SFR_IO8(0x13) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +-#define PINC7 7 +- +-#define DDRC _SFR_IO8(0x14) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC3 3 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +-#define DDC7 7 +- +-#define PORTC _SFR_IO8(0x15) +-#define PC0 0 +-#define PC1 1 +-#define PC2 2 +-#define PC3 3 +-#define PC4 4 +-#define PC5 5 +-#define PC6 6 +-#define PC7 7 +- +-#define PINB _SFR_IO8(0x16) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x17) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x18) +-#define PB0 0 +-#define PB1 1 +-#define PB2 2 +-#define PB3 3 +-#define PB4 4 +-#define PB5 5 +-#define PB6 6 +-#define PB7 7 +- +-#define PINA _SFR_IO8(0x19) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +-#define PINA4 4 +-#define PINA5 5 +-#define PINA6 6 +-#define PINA7 7 +- +-#define DDRA _SFR_IO8(0x1A) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +-#define DDA4 4 +-#define DDA5 5 +-#define DDA6 6 +-#define DDA7 7 +- +-#define PORTA _SFR_IO8(0x1B) +-#define PA0 0 +-#define PA1 1 +-#define PA2 2 +-#define PA3 3 +-#define PA4 4 +-#define PA5 5 +-#define PA6 6 +-#define PA7 7 +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +-#define EERE 0 +-#define EEWE 1 +-#define EEMWE 2 +-#define EERIE 3 +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO16(0x1E) +-#define EEARL _SFR_IO8(0x1E) +-#define EEARH _SFR_IO8(0x1F) +- +-#define UCSRC _SFR_IO8(0x20) +-#define UCPOL 0 +-#define UCSZ0 1 +-#define UCSZ1 2 +-#define USBS 3 +-#define UPM0 4 +-#define UPM1 5 +-#define UMSEL 6 +-#define URSEL 7 +- +-#define UBRRH _SFR_IO8(0x20) +-#define URSEL 7 +- +-#define WDTCR _SFR_IO8(0x21) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDTOE 4 +- +-#define ASSR _SFR_IO8(0x22) +-#define TCR2UB 0 +-#define OCR2UB 1 +-#define TCN2UB 2 +-#define AS2 3 +- +-#define OCR2 _SFR_IO8(0x23) +- +-#define TCNT2 _SFR_IO8(0x24) +- +-#define TCCR2 _SFR_IO8(0x25) +-#define CS20 0 +-#define CS21 1 +-#define CS22 2 +-#define WGM21 3 +-#define COM20 4 +-#define COM21 5 +-#define WGM20 6 +-#define FOC2 7 +- +-/* Combine ICR1L and ICR1H */ +-#define ICR1 _SFR_IO16(0x26) +- +-#define ICR1L _SFR_IO8(0x26) +-#define ICR1H _SFR_IO8(0x27) +- +-/* Combine OCR1BL and OCR1BH */ +-#define OCR1B _SFR_IO16(0x28) +- +-#define OCR1BL _SFR_IO8(0x28) +-#define OCR1BH _SFR_IO8(0x29) +- +-/* Combine OCR1AL and OCR1AH */ +-#define OCR1A _SFR_IO16(0x2A) +- +-#define OCR1AL _SFR_IO8(0x2A) +-#define OCR1AH _SFR_IO8(0x2B) +- +-/* Combine TCNT1L and TCNT1H */ +-#define TCNT1 _SFR_IO16(0x2C) +- +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1H _SFR_IO8(0x2D) +- +-#define TCCR1B _SFR_IO8(0x2E) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1A _SFR_IO8(0x2F) +-#define WGM10 0 +-#define WGM11 1 +-#define FOC1B 2 +-#define FOC1A 3 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-/* +- The ADHSM bit has been removed from all documentation, +- as being not needed at all since the comparator has proven +- to be fast enough even without feeding it more power. +-*/ +- +-#define SFIOR _SFR_IO8(0x30) +-#define PSR10 0 +-#define PSR2 1 +-#define PUD 2 +-#define ACME 3 +-#define ADTS0 5 +-#define ADTS1 6 +-#define ADTS2 7 +- +-#define OSCCAL _SFR_IO8(0x31) +- +-#define OCDR _SFR_IO8(0x31) +- +-#define TCNT0 _SFR_IO8(0x32) +- +-#define TCCR0 _SFR_IO8(0x33) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM01 3 +-#define COM00 4 +-#define COM01 5 +-#define WGM00 6 +-#define FOC0 7 +- +-#define MCUCSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +-#define JTRF 4 +-#define ISC2 6 +-#define JTD 7 +- +-#define MCUCR _SFR_IO8(0x35) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define SM0 4 +-#define SM1 5 +-#define SE 6 +-#define SM2 7 +- +-#define TWCR _SFR_IO8(0x36) +-#define TWIE 0 +-#define TWEN 2 +-#define TWWC 3 +-#define TWSTO 4 +-#define TWSTA 5 +-#define TWEA 6 +-#define TWINT 7 +- +-#define SPMCR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define TIFR _SFR_IO8(0x38) +-#define TOV0 0 +-#define OCF0 1 +-#define TOV1 2 +-#define OCF1B 3 +-#define OCF1A 4 +-#define ICF1 5 +-#define TOV2 6 +-#define OCF2 7 +- +-#define TIMSK _SFR_IO8(0x39) +-#define TOIE0 0 +-#define OCIE0 1 +-#define TOIE1 2 +-#define OCIE1B 3 +-#define OCIE1A 4 +-#define TICIE1 5 +-#define TOIE2 6 +-#define OCIE2 7 +- +-#define GIFR _SFR_IO8(0x3A) +-#define INTF2 5 +-#define INTF0 6 +-#define INTF1 7 +- +-#define GICR _SFR_IO8(0x3B) +-#define IVCE 0 +-#define IVSEL 1 +-#define INT2 5 +-#define INT0 6 +-#define INT1 7 +- +-#define OCR0 _SFR_IO8(0x3C) +- +-/* SP [0x3D..0x3E] */ +-/* SREG [0x3F] */ +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector. */ +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt Request 1 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +-#define SIG_INTERRUPT1 _VECTOR(2) +- +-/* Timer/Counter2 Compare Match */ +-#define TIMER2_COMP_vect_num 3 +-#define TIMER2_COMP_vect _VECTOR(3) +-#define SIG_OUTPUT_COMPARE2 _VECTOR(3) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 4 +-#define TIMER2_OVF_vect _VECTOR(4) +-#define SIG_OVERFLOW2 _VECTOR(4) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 5 +-#define TIMER1_CAPT_vect _VECTOR(5) +-#define SIG_INPUT_CAPTURE1 _VECTOR(5) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 6 +-#define TIMER1_COMPA_vect _VECTOR(6) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(6) +- +-/* Timer/Counter1 Compare Match B */ +-#define TIMER1_COMPB_vect_num 7 +-#define TIMER1_COMPB_vect _VECTOR(7) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(7) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 8 +-#define TIMER1_OVF_vect _VECTOR(8) +-#define SIG_OVERFLOW1 _VECTOR(8) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 9 +-#define TIMER0_OVF_vect _VECTOR(9) +-#define SIG_OVERFLOW0 _VECTOR(9) +- +-/* Serial Transfer Complete */ +-#define SPI_STC_vect_num 10 +-#define SPI_STC_vect _VECTOR(10) +-#define SIG_SPI _VECTOR(10) +- +-/* USART, Rx Complete */ +-#define USART_RXC_vect_num 11 +-#define USART_RXC_vect _VECTOR(11) +-#define SIG_USART_RECV _VECTOR(11) +-#define SIG_UART_RECV _VECTOR(11) +- +-/* USART Data Register Empty */ +-#define USART_UDRE_vect_num 12 +-#define USART_UDRE_vect _VECTOR(12) +-#define SIG_USART_DATA _VECTOR(12) +-#define SIG_UART_DATA _VECTOR(12) +- +-/* USART, Tx Complete */ +-#define USART_TXC_vect_num 13 +-#define USART_TXC_vect _VECTOR(13) +-#define SIG_USART_TRANS _VECTOR(13) +-#define SIG_UART_TRANS _VECTOR(13) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 14 +-#define ADC_vect _VECTOR(14) +-#define SIG_ADC _VECTOR(14) +- +-/* EEPROM Ready */ +-#define EE_RDY_vect_num 15 +-#define EE_RDY_vect _VECTOR(15) +-#define SIG_EEPROM_READY _VECTOR(15) +- +-/* Analog Comparator */ +-#define ANA_COMP_vect_num 16 +-#define ANA_COMP_vect _VECTOR(16) +-#define SIG_COMPARATOR _VECTOR(16) +- +-/* 2-wire Serial Interface */ +-#define TWI_vect_num 17 +-#define TWI_vect _VECTOR(17) +-#define SIG_2WIRE_SERIAL _VECTOR(17) +- +-/* External Interrupt Request 2 */ +-#define INT2_vect_num 18 +-#define INT2_vect _VECTOR(18) +-#define SIG_INTERRUPT2 _VECTOR(18) +- +-/* Timer/Counter0 Compare Match */ +-#define TIMER0_COMP_vect_num 19 +-#define TIMER0_COMP_vect _VECTOR(19) +-#define SIG_OUTPUT_COMPARE0 _VECTOR(19) +- +-/* Store Program Memory Ready */ +-#define SPM_RDY_vect_num 20 +-#define SPM_RDY_vect _VECTOR(20) +-#define SIG_SPM_READY _VECTOR(20) +- +-#define _VECTORS_SIZE 84 +- +- +-/* Constants */ +-#define SPM_PAGESIZE 128 +-#define RAMSTART (0x60) +-#define RAMEND 0x45F +-#define XRAMEND RAMEND +-#define E2END 0x1FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x3FFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 2 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_BODEN (unsigned char)~_BV(6) +-#define FUSE_BODLEVEL (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_CKOPT (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x94 +-#define SIGNATURE_2 0x03 +- +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_INTERRUPT1 +-#pragma GCC poison SIG_OUTPUT_COMPARE2 +-#pragma GCC poison SIG_OVERFLOW2 +-#pragma GCC poison SIG_INPUT_CAPTURE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_SPI +-#pragma GCC poison SIG_USART_RECV +-#pragma GCC poison SIG_UART_RECV +-#pragma GCC poison SIG_USART_DATA +-#pragma GCC poison SIG_UART_DATA +-#pragma GCC poison SIG_USART_TRANS +-#pragma GCC poison SIG_UART_TRANS +-#pragma GCC poison SIG_ADC +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_2WIRE_SERIAL +-#pragma GCC poison SIG_INTERRUPT2 +-#pragma GCC poison SIG_OUTPUT_COMPARE0 +-#pragma GCC poison SIG_SPM_READY +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +-#endif /* _AVR_IOM16_H_ */ ++/* Copyright (c) 2004 Eric B. Weddington ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom16.h 2228 2011-03-05 15:33:19Z arcanum $ */ ++ ++/* avr/iom16.h - definitions for ATmega16 */ ++ ++#ifndef _AVR_IOM16_H_ ++#define _AVR_IOM16_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom16.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define TWBR _SFR_IO8(0x00) ++ ++#define TWSR _SFR_IO8(0x01) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_IO8(0x02) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_IO8(0x03) ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCW _SFR_IO16(0x04) ++#define ADCL _SFR_IO8(0x04) ++#define ADCH _SFR_IO8(0x05) ++ ++#define ADCSRA _SFR_IO8(0x06) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADMUX _SFR_IO8(0x07) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define ACSR _SFR_IO8(0x08) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define UBRRL _SFR_IO8(0x09) ++ ++#define UCSRB _SFR_IO8(0x0A) ++#define TXB8 0 ++#define RXB8 1 ++#define UCSZ2 2 ++#define TXEN 3 ++#define RXEN 4 ++#define UDRIE 5 ++#define TXCIE 6 ++#define RXCIE 7 ++ ++#define UCSRA _SFR_IO8(0x0B) ++#define MPCM 0 ++#define U2X 1 ++#define PE 2 ++#define DOR 3 ++#define FE 4 ++#define UDRE 5 ++#define TXC 6 ++#define RXC 7 ++ ++#define UDR _SFR_IO8(0x0C) ++ ++#define SPCR _SFR_IO8(0x0D) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x0E) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x0F) ++ ++#define PIND _SFR_IO8(0x10) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x11) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x12) ++#define PD0 0 ++#define PD1 1 ++#define PD2 2 ++#define PD3 3 ++#define PD4 4 ++#define PD5 5 ++#define PD6 6 ++#define PD7 7 ++ ++#define PINC _SFR_IO8(0x13) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++#define PINC7 7 ++ ++#define DDRC _SFR_IO8(0x14) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++#define DDC7 7 ++ ++#define PORTC _SFR_IO8(0x15) ++#define PC0 0 ++#define PC1 1 ++#define PC2 2 ++#define PC3 3 ++#define PC4 4 ++#define PC5 5 ++#define PC6 6 ++#define PC7 7 ++ ++#define PINB _SFR_IO8(0x16) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x17) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x18) ++#define PB0 0 ++#define PB1 1 ++#define PB2 2 ++#define PB3 3 ++#define PB4 4 ++#define PB5 5 ++#define PB6 6 ++#define PB7 7 ++ ++#define PINA _SFR_IO8(0x19) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++#define PINA4 4 ++#define PINA5 5 ++#define PINA6 6 ++#define PINA7 7 ++ ++#define DDRA _SFR_IO8(0x1A) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++#define DDA4 4 ++#define DDA5 5 ++#define DDA6 6 ++#define DDA7 7 ++ ++#define PORTA _SFR_IO8(0x1B) ++#define PA0 0 ++#define PA1 1 ++#define PA2 2 ++#define PA3 3 ++#define PA4 4 ++#define PA5 5 ++#define PA6 6 ++#define PA7 7 ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO16(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++#define EEARH _SFR_IO8(0x1F) ++ ++#define UCSRC _SFR_IO8(0x20) ++#define UCPOL 0 ++#define UCSZ0 1 ++#define UCSZ1 2 ++#define USBS 3 ++#define UPM0 4 ++#define UPM1 5 ++#define UMSEL 6 ++#define URSEL 7 ++ ++#define UBRRH _SFR_IO8(0x20) ++#define URSEL 7 ++ ++#define WDTCR _SFR_IO8(0x21) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDTOE 4 ++ ++#define ASSR _SFR_IO8(0x22) ++#define TCR2UB 0 ++#define OCR2UB 1 ++#define TCN2UB 2 ++#define AS2 3 ++ ++#define OCR2 _SFR_IO8(0x23) ++ ++#define TCNT2 _SFR_IO8(0x24) ++ ++#define TCCR2 _SFR_IO8(0x25) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM21 3 ++#define COM20 4 ++#define COM21 5 ++#define WGM20 6 ++#define FOC2 7 ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_IO16(0x26) ++ ++#define ICR1L _SFR_IO8(0x26) ++#define ICR1H _SFR_IO8(0x27) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_IO16(0x28) ++ ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BH _SFR_IO8(0x29) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_IO16(0x2A) ++ ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_IO16(0x2C) ++ ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++ ++#define TCCR1B _SFR_IO8(0x2E) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1A _SFR_IO8(0x2F) ++#define WGM10 0 ++#define WGM11 1 ++#define FOC1B 2 ++#define FOC1A 3 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++/* ++ The ADHSM bit has been removed from all documentation, ++ as being not needed at all since the comparator has proven ++ to be fast enough even without feeding it more power. ++*/ ++ ++#define SFIOR _SFR_IO8(0x30) ++#define PSR10 0 ++#define PSR2 1 ++#define PUD 2 ++#define ACME 3 ++#define ADTS0 5 ++#define ADTS1 6 ++#define ADTS2 7 ++ ++#define OSCCAL _SFR_IO8(0x31) ++ ++#define OCDR _SFR_IO8(0x31) ++ ++#define TCNT0 _SFR_IO8(0x32) ++ ++#define TCCR0 _SFR_IO8(0x33) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM01 3 ++#define COM00 4 ++#define COM01 5 ++#define WGM00 6 ++#define FOC0 7 ++ ++#define MCUCSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define JTRF 4 ++#define ISC2 6 ++#define JTD 7 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define SM0 4 ++#define SM1 5 ++#define SE 6 ++#define SM2 7 ++ ++#define TWCR _SFR_IO8(0x36) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define SPMCR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define TIFR _SFR_IO8(0x38) ++#define TOV0 0 ++#define OCF0 1 ++#define TOV1 2 ++#define OCF1B 3 ++#define OCF1A 4 ++#define ICF1 5 ++#define TOV2 6 ++#define OCF2 7 ++ ++#define TIMSK _SFR_IO8(0x39) ++#define TOIE0 0 ++#define OCIE0 1 ++#define TOIE1 2 ++#define OCIE1B 3 ++#define OCIE1A 4 ++#define TICIE1 5 ++#define TOIE2 6 ++#define OCIE2 7 ++ ++#define GIFR _SFR_IO8(0x3A) ++#define INTF2 5 ++#define INTF0 6 ++#define INTF1 7 ++ ++#define GICR _SFR_IO8(0x3B) ++#define IVCE 0 ++#define IVSEL 1 ++#define INT2 5 ++#define INT0 6 ++#define INT1 7 ++ ++#define OCR0 _SFR_IO8(0x3C) ++ ++/* SP [0x3D..0x3E] */ ++/* SREG [0x3F] */ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector. */ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++#define SIG_INTERRUPT1 _VECTOR(2) ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect_num 3 ++#define TIMER2_COMP_vect _VECTOR(3) ++#define SIG_OUTPUT_COMPARE2 _VECTOR(3) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 4 ++#define TIMER2_OVF_vect _VECTOR(4) ++#define SIG_OVERFLOW2 _VECTOR(4) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 5 ++#define TIMER1_CAPT_vect _VECTOR(5) ++#define SIG_INPUT_CAPTURE1 _VECTOR(5) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 6 ++#define TIMER1_COMPA_vect _VECTOR(6) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(6) ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect_num 7 ++#define TIMER1_COMPB_vect _VECTOR(7) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(7) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 8 ++#define TIMER1_OVF_vect _VECTOR(8) ++#define SIG_OVERFLOW1 _VECTOR(8) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 9 ++#define TIMER0_OVF_vect _VECTOR(9) ++#define SIG_OVERFLOW0 _VECTOR(9) ++ ++/* Serial Transfer Complete */ ++#define SPI_STC_vect_num 10 ++#define SPI_STC_vect _VECTOR(10) ++#define SIG_SPI _VECTOR(10) ++ ++/* USART, Rx Complete */ ++#define USART_RXC_vect_num 11 ++#define USART_RXC_vect _VECTOR(11) ++#define SIG_USART_RECV _VECTOR(11) ++#define SIG_UART_RECV _VECTOR(11) ++ ++/* USART Data Register Empty */ ++#define USART_UDRE_vect_num 12 ++#define USART_UDRE_vect _VECTOR(12) ++#define SIG_USART_DATA _VECTOR(12) ++#define SIG_UART_DATA _VECTOR(12) ++ ++/* USART, Tx Complete */ ++#define USART_TXC_vect_num 13 ++#define USART_TXC_vect _VECTOR(13) ++#define SIG_USART_TRANS _VECTOR(13) ++#define SIG_UART_TRANS _VECTOR(13) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 14 ++#define ADC_vect _VECTOR(14) ++#define SIG_ADC _VECTOR(14) ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect_num 15 ++#define EE_RDY_vect _VECTOR(15) ++#define SIG_EEPROM_READY _VECTOR(15) ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect_num 16 ++#define ANA_COMP_vect _VECTOR(16) ++#define SIG_COMPARATOR _VECTOR(16) ++ ++/* 2-wire Serial Interface */ ++#define TWI_vect_num 17 ++#define TWI_vect _VECTOR(17) ++#define SIG_2WIRE_SERIAL _VECTOR(17) ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect_num 18 ++#define INT2_vect _VECTOR(18) ++#define SIG_INTERRUPT2 _VECTOR(18) ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect_num 19 ++#define TIMER0_COMP_vect _VECTOR(19) ++#define SIG_OUTPUT_COMPARE0 _VECTOR(19) ++ ++/* Store Program Memory Ready */ ++#define SPM_RDY_vect_num 20 ++#define SPM_RDY_vect _VECTOR(20) ++#define SIG_SPM_READY _VECTOR(20) ++ ++#define _VECTORS_SIZE 84 ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE 128 ++#define RAMSTART (0x60) ++#define RAMEND 0x45F ++#define XRAMEND RAMEND ++#define E2END 0x1FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x3FFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 2 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_BODEN (unsigned char)~_BV(6) ++#define FUSE_BODLEVEL (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_CKOPT (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x03 ++ ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_INTERRUPT1 ++#pragma GCC poison SIG_OUTPUT_COMPARE2 ++#pragma GCC poison SIG_OVERFLOW2 ++#pragma GCC poison SIG_INPUT_CAPTURE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_SPI ++#pragma GCC poison SIG_USART_RECV ++#pragma GCC poison SIG_UART_RECV ++#pragma GCC poison SIG_USART_DATA ++#pragma GCC poison SIG_UART_DATA ++#pragma GCC poison SIG_USART_TRANS ++#pragma GCC poison SIG_UART_TRANS ++#pragma GCC poison SIG_ADC ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_2WIRE_SERIAL ++#pragma GCC poison SIG_INTERRUPT2 ++#pragma GCC poison SIG_OUTPUT_COMPARE0 ++#pragma GCC poison SIG_SPM_READY ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++#endif /* _AVR_IOM16_H_ */ +diff --git a/include/avr/iom161.h b/include/avr/iom161.h +index 7f0cdaf..8403e9a 100644 +--- a/include/avr/iom161.h ++++ b/include/avr/iom161.h +@@ -1,722 +1,723 @@ +-/* Copyright (c) 2002, Marek Michalkiewicz +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom161.h 2229 2011-03-05 17:00:18Z arcanum $ */ +- +-/* avr/iom161.h - definitions for ATmega161 */ +- +-#ifndef _AVR_IOM161_H_ +-#define _AVR_IOM161_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom161.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* UART1 Baud Rate Register */ +-#define UBRR1 _SFR_IO8(0x00) +- +-/* UART1 Control and Status Registers */ +-#define UCSR1B _SFR_IO8(0x01) +-#define UCSR1A _SFR_IO8(0x02) +- +-/* UART1 I/O Data Register */ +-#define UDR1 _SFR_IO8(0x03) +- +-/* 0x04 reserved */ +- +-/* Input Pins, Port E */ +-#define PINE _SFR_IO8(0x05) +- +-/* Data Direction Register, Port E */ +-#define DDRE _SFR_IO8(0x06) +- +-/* Data Register, Port E */ +-#define PORTE _SFR_IO8(0x07) +- +-/* Analog Comparator Control and Status Register */ +-#define ACSR _SFR_IO8(0x08) +- +-/* UART0 Baud Rate Register */ +-#define UBRR0 _SFR_IO8(0x09) +- +-/* UART0 Control and Status Registers */ +-#define UCSR0B _SFR_IO8(0x0A) +-#define UCSR0A _SFR_IO8(0x0B) +- +-/* UART0 I/O Data Register */ +-#define UDR0 _SFR_IO8(0x0C) +- +-/* SPI Control Register */ +-#define SPCR _SFR_IO8(0x0D) +- +-/* SPI Status Register */ +-#define SPSR _SFR_IO8(0x0E) +- +-/* SPI I/O Data Register */ +-#define SPDR _SFR_IO8(0x0F) +- +-/* Input Pins, Port D */ +-#define PIND _SFR_IO8(0x10) +- +-/* Data Direction Register, Port D */ +-#define DDRD _SFR_IO8(0x11) +- +-/* Data Register, Port D */ +-#define PORTD _SFR_IO8(0x12) +- +-/* Input Pins, Port C */ +-#define PINC _SFR_IO8(0x13) +- +-/* Data Direction Register, Port C */ +-#define DDRC _SFR_IO8(0x14) +- +-/* Data Register, Port C */ +-#define PORTC _SFR_IO8(0x15) +- +-/* Input Pins, Port B */ +-#define PINB _SFR_IO8(0x16) +- +-/* Data Direction Register, Port B */ +-#define DDRB _SFR_IO8(0x17) +- +-/* Data Register, Port B */ +-#define PORTB _SFR_IO8(0x18) +- +-/* Input Pins, Port A */ +-#define PINA _SFR_IO8(0x19) +- +-/* Data Direction Register, Port A */ +-#define DDRA _SFR_IO8(0x1A) +- +-/* Data Register, Port A */ +-#define PORTA _SFR_IO8(0x1B) +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO16(0x1E) +-#define EEARL _SFR_IO8(0x1E) +-#define EEARH _SFR_IO8(0x1F) +- +-/* UART Baud Register HIgh */ +-#define UBRRH _SFR_IO8(0x20) +- +-/* Watchdog Timer Control Register */ +-#define WDTCR _SFR_IO8(0x21) +- +-/* Timer/Counter2 Output Compare Register */ +-#define OCR2 _SFR_IO8(0x22) +- +-/* Timer/Counter2 (8-bit) */ +-#define TCNT2 _SFR_IO8(0x23) +- +-/* Timer/Counter1 Input Capture Register */ +-#define ICR1 _SFR_IO16(0x24) +-#define ICR1L _SFR_IO8(0x24) +-#define ICR1H _SFR_IO8(0x25) +- +-/* ASynchronous mode Status Register */ +-#define ASSR _SFR_IO8(0x26) +- +-/* Timer/Counter2 Control Register */ +-#define TCCR2 _SFR_IO8(0x27) +- +-/* Timer/Counter1 Output Compare RegisterB */ +-#define OCR1B _SFR_IO16(0x28) +-#define OCR1BL _SFR_IO8(0x28) +-#define OCR1BH _SFR_IO8(0x29) +- +-/* Timer/Counter1 Output Compare RegisterA */ +-#define OCR1A _SFR_IO16(0x2A) +-#define OCR1AL _SFR_IO8(0x2A) +-#define OCR1AH _SFR_IO8(0x2B) +- +-/* Timer/Counter1 */ +-#define TCNT1 _SFR_IO16(0x2C) +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1H _SFR_IO8(0x2D) +- +-/* Timer/Counter1 Control Register B */ +-#define TCCR1B _SFR_IO8(0x2E) +- +-/* Timer/Counter1 Control Register A */ +-#define TCCR1A _SFR_IO8(0x2F) +- +-/* Special Function IO Register */ +-#define SFIOR _SFR_IO8(0x30) +- +-/* Timer/Counter0 Output Compare Register */ +-#define OCR0 _SFR_IO8(0x31) +- +-/* Timer/Counter0 (8-bit) */ +-#define TCNT0 _SFR_IO8(0x32) +- +-/* Timer/Counter0 Control Register */ +-#define TCCR0 _SFR_IO8(0x33) +- +-/* MCU general Status Register */ +-#define MCUSR _SFR_IO8(0x34) +- +-/* MCU general Control Register */ +-#define MCUCR _SFR_IO8(0x35) +- +-/* Extended MCU general Control Register */ +-#define EMCUCR _SFR_IO8(0x36) +- +-/* Store Program Memory Control Register */ +-#define SPMCR _SFR_IO8(0x37) +- +-/* Timer/Counter Interrupt Flag Register */ +-#define TIFR _SFR_IO8(0x38) +- +-/* Timer/Counter Interrupt MaSK Register */ +-#define TIMSK _SFR_IO8(0x39) +- +-/* General Interrupt Flag Register */ +-#define GIFR _SFR_IO8(0x3A) +- +-/* General Interrupt MaSK register */ +-#define GIMSK _SFR_IO8(0x3B) +- +-/* 0x3C reserved */ +- +-/* 0x3D..0x3E SP */ +- +-/* 0x3F SREG */ +- +-/* Interrupt vectors */ +- +-/* External Interrupt 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt 1 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +-#define SIG_INTERRUPT1 _VECTOR(2) +- +-/* External Interrupt 2 */ +-#define INT2_vect_num 3 +-#define INT2_vect _VECTOR(3) +-#define SIG_INTERRUPT2 _VECTOR(3) +- +-/* Timer/Counter2 Compare Match */ +-#define TIMER2_COMP_vect_num 4 +-#define TIMER2_COMP_vect _VECTOR(4) +-#define SIG_OUTPUT_COMPARE2 _VECTOR(4) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 5 +-#define TIMER2_OVF_vect _VECTOR(5) +-#define SIG_OVERFLOW2 _VECTOR(5) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 6 +-#define TIMER1_CAPT_vect _VECTOR(6) +-#define SIG_INPUT_CAPTURE1 _VECTOR(6) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 7 +-#define TIMER1_COMPA_vect _VECTOR(7) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(7) +- +-/* Timer/Counter1 Compare Match B */ +-#define TIMER1_COMPB_vect_num 8 +-#define TIMER1_COMPB_vect _VECTOR(8) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(8) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 9 +-#define TIMER1_OVF_vect _VECTOR(9) +-#define SIG_OVERFLOW1 _VECTOR(9) +- +-/* Timer/Counter0 Compare Match */ +-#define TIMER0_COMP_vect_num 10 +-#define TIMER0_COMP_vect _VECTOR(10) +-#define SIG_OUTPUT_COMPARE0 _VECTOR(10) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 11 +-#define TIMER0_OVF_vect _VECTOR(11) +-#define SIG_OVERFLOW0 _VECTOR(11) +- +-/* Serial Transfer Complete */ +-#define SPI_STC_vect_num 12 +-#define SPI_STC_vect _VECTOR(12) +-#define SIG_SPI _VECTOR(12) +- +-/* UART0, Rx Complete */ +-#define UART0_RX_vect_num 13 +-#define UART0_RX_vect _VECTOR(13) +-#define SIG_UART0_RECV _VECTOR(13) +- +-/* UART1, Rx Complete */ +-#define UART1_RX_vect_num 14 +-#define UART1_RX_vect _VECTOR(14) +-#define SIG_UART1_RECV _VECTOR(14) +- +-/* UART0 Data Register Empty */ +-#define UART0_UDRE_vect_num 15 +-#define UART0_UDRE_vect _VECTOR(15) +-#define SIG_UART0_DATA _VECTOR(15) +- +-/* UART1 Data Register Empty */ +-#define UART1_UDRE_vect_num 16 +-#define UART1_UDRE_vect _VECTOR(16) +-#define SIG_UART1_DATA _VECTOR(16) +- +-/* UART0, Tx Complete */ +-#define UART0_TX_vect_num 17 +-#define UART0_TX_vect _VECTOR(17) +-#define SIG_UART0_TRANS _VECTOR(17) +- +-/* UART1, Tx Complete */ +-#define UART1_TX_vect_num 18 +-#define UART1_TX_vect _VECTOR(18) +-#define SIG_UART1_TRANS _VECTOR(18) +- +-/* EEPROM Ready */ +-#define EE_RDY_vect_num 19 +-#define EE_RDY_vect _VECTOR(19) +-#define SIG_EEPROM_READY _VECTOR(19) +- +-/* Analog Comparator */ +-#define ANA_COMP_vect_num 20 +-#define ANA_COMP_vect _VECTOR(20) +-#define SIG_COMPARATOR _VECTOR(20) +- +-#define _VECTORS_SIZE 84 +- +-/* Bit numbers */ +- +-/* GIMSK */ +-#define INT1 7 +-#define INT0 6 +-#define INT2 5 +- +-/* GIFR */ +-#define INTF1 7 +-#define INTF0 6 +-#define INTF2 5 +- +-/* TIMSK */ +-#define TOIE1 7 +-#define OCIE1A 6 +-#define OCIE1B 5 +-#define TOIE2 4 +-#define TICIE1 3 +-#define OCIE2 2 +-#define TOIE0 1 +-#define OCIE0 0 +- +-/* TIFR */ +-#define TOV1 7 +-#define OCF1A 6 +-#define OCF1B 5 +-#define TOV2 4 +-#define ICF1 3 +-#define OCF2 2 +-#define TOV0 1 +-#define OCF0 0 +- +-/* MCUCR */ +-#define SRE 7 +-#define SRW10 6 +-#define SE 5 +-#define SM1 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-/* EMCUCR */ +-#define SM0 7 +-#define SRL2 6 +-#define SRL1 5 +-#define SRL0 4 +-#define SRW01 3 +-#define SRW00 2 +-#define SRW11 1 +-#define ISC2 0 +- +-/* SPMCR */ +-#define BLBSET 3 +-#define PGWRT 2 +-#define PGERS 1 +-#define SPMEN 0 +- +-/* SFIOR */ +-#define PSR2 1 +-#define PSR10 0 +- +-/* TCCR0 */ +-#define FOC0 7 +-#define PWM0 6 +-#define COM01 5 +-#define COM00 4 +-#define CTC0 3 +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* TCCR2 */ +-#define FOC2 7 +-#define PWM2 6 +-#define COM21 5 +-#define COM20 4 +-#define CTC2 3 +-#define CS22 2 +-#define CS21 1 +-#define CS20 0 +- +-/* ASSR */ +-#define AS2 3 +-#define TCN2UB 2 +-#define OCR2UB 1 +-#define TCR2UB 0 +- +-/* TCCR1A */ +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define FOC1A 3 +-#define FOC1B 2 +-#define PWM11 1 +-#define PWM10 0 +- +-/* TCCR1B */ +-#define ICNC1 7 +-#define ICES1 6 +-#define CTC1 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* WDTCR */ +-#define WDTOE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* PORTA */ +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-/* DDRA */ +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-/* PINA */ +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-/* +- PB7 = SCK +- PB6 = MISO +- PB5 = MOSI +- PB4 = SS# +- PB3 = TXD1 / AIN1 +- PB2 = RXD1 / AIN0 +- PB1 = OC2 / T1 +- PB0 = OC0 / T0 +- */ +- +-/* PORTB */ +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* DDRB */ +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* PINB */ +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* PORTC */ +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-/* DDRC */ +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-/* PINC */ +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-/* +- PD7 = RD# +- PD6 = WR# +- PD5 = TOSC2 / OC1A +- PD4 = TOSC1 +- PD3 = INT1 +- PD2 = INT0 +- PD1 = TXD0 +- PD0 = RXD0 +- */ +- +-/* PORTD */ +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* DDRD */ +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-/* PIND */ +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-/* +- PE2 = ALE +- PE1 = OC1B +- PE0 = ICP / INT2 +- */ +- +-/* PORTE */ +-#define PE2 2 +-#define PE1 1 +-#define PE0 0 +- +-/* DDRE */ +-#define DDE2 2 +-#define DDE1 1 +-#define DDE0 0 +- +-/* PINE */ +-#define PINE2 2 +-#define PINE1 1 +-#define PINE0 0 +- +-/* SPSR */ +-#define SPIF 7 +-#define WCOL 6 +-#define SPI2X 0 +- +-/* SPCR */ +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +-/* UCSR0A, UCSR1A */ +-#define RXC 7 +-#define TXC 6 +-#define UDRE 5 +-#define FE 4 +-#define DOR 3 +-#define U2X 1 +-#define MPCM 0 +- +-/* UCSR0B, UCSR1B */ +-#define RXCIE 7 +-#define TXCIE 6 +-#define UDRIE 5 +-#define RXEN 4 +-#define TXEN 3 +-#define CHR9 2 +-#define RXB8 1 +-#define TXB8 0 +- +-/* ACSR */ +-#define ACD 7 +-#define AINBG 6 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +- +-/* EEPROM Control Register */ +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-/* Constants */ +-#define SPM_PAGESIZE 128 +-#define RAMEND 0x45F +-#define XRAMEND 0xFFFF +-#define E2END 0x1FF +-#define E2PAGESIZE 0 +-#define FLASHEND 0x3FFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 1 +- +-/* Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_SUT (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_BOOTRST (unsigned char)~_BV(6) +-#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_SPIEN) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x94 +-#define SIGNATURE_2 0x01 +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_INTERRUPT1 +-#pragma GCC poison SIG_INTERRUPT2 +-#pragma GCC poison SIG_OUTPUT_COMPARE2 +-#pragma GCC poison SIG_OVERFLOW2 +-#pragma GCC poison SIG_INPUT_CAPTURE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OUTPUT_COMPARE0 +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_SPI +-#pragma GCC poison SIG_UART0_RECV +-#pragma GCC poison SIG_UART1_RECV +-#pragma GCC poison SIG_UART0_DATA +-#pragma GCC poison SIG_UART1_DATA +-#pragma GCC poison SIG_UART0_TRANS +-#pragma GCC poison SIG_UART1_TRANS +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_COMPARATOR +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +-#endif /* _AVR_IOM161_H_ */ ++/* Copyright (c) 2002, Marek Michalkiewicz ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom161.h 2229 2011-03-05 17:00:18Z arcanum $ */ ++ ++/* avr/iom161.h - definitions for ATmega161 */ ++ ++#ifndef _AVR_IOM161_H_ ++#define _AVR_IOM161_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom161.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* UART1 Baud Rate Register */ ++#define UBRR1 _SFR_IO8(0x00) ++ ++/* UART1 Control and Status Registers */ ++#define UCSR1B _SFR_IO8(0x01) ++#define UCSR1A _SFR_IO8(0x02) ++ ++/* UART1 I/O Data Register */ ++#define UDR1 _SFR_IO8(0x03) ++ ++/* 0x04 reserved */ ++ ++/* Input Pins, Port E */ ++#define PINE _SFR_IO8(0x05) ++ ++/* Data Direction Register, Port E */ ++#define DDRE _SFR_IO8(0x06) ++ ++/* Data Register, Port E */ ++#define PORTE _SFR_IO8(0x07) ++ ++/* Analog Comparator Control and Status Register */ ++#define ACSR _SFR_IO8(0x08) ++ ++/* UART0 Baud Rate Register */ ++#define UBRR0 _SFR_IO8(0x09) ++ ++/* UART0 Control and Status Registers */ ++#define UCSR0B _SFR_IO8(0x0A) ++#define UCSR0A _SFR_IO8(0x0B) ++ ++/* UART0 I/O Data Register */ ++#define UDR0 _SFR_IO8(0x0C) ++ ++/* SPI Control Register */ ++#define SPCR _SFR_IO8(0x0D) ++ ++/* SPI Status Register */ ++#define SPSR _SFR_IO8(0x0E) ++ ++/* SPI I/O Data Register */ ++#define SPDR _SFR_IO8(0x0F) ++ ++/* Input Pins, Port D */ ++#define PIND _SFR_IO8(0x10) ++ ++/* Data Direction Register, Port D */ ++#define DDRD _SFR_IO8(0x11) ++ ++/* Data Register, Port D */ ++#define PORTD _SFR_IO8(0x12) ++ ++/* Input Pins, Port C */ ++#define PINC _SFR_IO8(0x13) ++ ++/* Data Direction Register, Port C */ ++#define DDRC _SFR_IO8(0x14) ++ ++/* Data Register, Port C */ ++#define PORTC _SFR_IO8(0x15) ++ ++/* Input Pins, Port B */ ++#define PINB _SFR_IO8(0x16) ++ ++/* Data Direction Register, Port B */ ++#define DDRB _SFR_IO8(0x17) ++ ++/* Data Register, Port B */ ++#define PORTB _SFR_IO8(0x18) ++ ++/* Input Pins, Port A */ ++#define PINA _SFR_IO8(0x19) ++ ++/* Data Direction Register, Port A */ ++#define DDRA _SFR_IO8(0x1A) ++ ++/* Data Register, Port A */ ++#define PORTA _SFR_IO8(0x1B) ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO16(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++#define EEARH _SFR_IO8(0x1F) ++ ++/* UART Baud Register HIgh */ ++#define UBRRH _SFR_IO8(0x20) ++ ++/* Watchdog Timer Control Register */ ++#define WDTCR _SFR_IO8(0x21) ++ ++/* Timer/Counter2 Output Compare Register */ ++#define OCR2 _SFR_IO8(0x22) ++ ++/* Timer/Counter2 (8-bit) */ ++#define TCNT2 _SFR_IO8(0x23) ++ ++/* Timer/Counter1 Input Capture Register */ ++#define ICR1 _SFR_IO16(0x24) ++#define ICR1L _SFR_IO8(0x24) ++#define ICR1H _SFR_IO8(0x25) ++ ++/* ASynchronous mode Status Register */ ++#define ASSR _SFR_IO8(0x26) ++ ++/* Timer/Counter2 Control Register */ ++#define TCCR2 _SFR_IO8(0x27) ++ ++/* Timer/Counter1 Output Compare RegisterB */ ++#define OCR1B _SFR_IO16(0x28) ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BH _SFR_IO8(0x29) ++ ++/* Timer/Counter1 Output Compare RegisterA */ ++#define OCR1A _SFR_IO16(0x2A) ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++ ++/* Timer/Counter1 */ ++#define TCNT1 _SFR_IO16(0x2C) ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++ ++/* Timer/Counter1 Control Register B */ ++#define TCCR1B _SFR_IO8(0x2E) ++ ++/* Timer/Counter1 Control Register A */ ++#define TCCR1A _SFR_IO8(0x2F) ++ ++/* Special Function IO Register */ ++#define SFIOR _SFR_IO8(0x30) ++ ++/* Timer/Counter0 Output Compare Register */ ++#define OCR0 _SFR_IO8(0x31) ++ ++/* Timer/Counter0 (8-bit) */ ++#define TCNT0 _SFR_IO8(0x32) ++ ++/* Timer/Counter0 Control Register */ ++#define TCCR0 _SFR_IO8(0x33) ++ ++/* MCU general Status Register */ ++#define MCUSR _SFR_IO8(0x34) ++ ++/* MCU general Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++ ++/* Extended MCU general Control Register */ ++#define EMCUCR _SFR_IO8(0x36) ++ ++/* Store Program Memory Control Register */ ++#define SPMCR _SFR_IO8(0x37) ++ ++/* Timer/Counter Interrupt Flag Register */ ++#define TIFR _SFR_IO8(0x38) ++ ++/* Timer/Counter Interrupt MaSK Register */ ++#define TIMSK _SFR_IO8(0x39) ++ ++/* General Interrupt Flag Register */ ++#define GIFR _SFR_IO8(0x3A) ++ ++/* General Interrupt MaSK register */ ++#define GIMSK _SFR_IO8(0x3B) ++ ++/* 0x3C reserved */ ++ ++/* 0x3D..0x3E SP */ ++ ++/* 0x3F SREG */ ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt 1 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++#define SIG_INTERRUPT1 _VECTOR(2) ++ ++/* External Interrupt 2 */ ++#define INT2_vect_num 3 ++#define INT2_vect _VECTOR(3) ++#define SIG_INTERRUPT2 _VECTOR(3) ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect_num 4 ++#define TIMER2_COMP_vect _VECTOR(4) ++#define SIG_OUTPUT_COMPARE2 _VECTOR(4) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 5 ++#define TIMER2_OVF_vect _VECTOR(5) ++#define SIG_OVERFLOW2 _VECTOR(5) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 6 ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define SIG_INPUT_CAPTURE1 _VECTOR(6) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 7 ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(7) ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect_num 8 ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(8) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 9 ++#define TIMER1_OVF_vect _VECTOR(9) ++#define SIG_OVERFLOW1 _VECTOR(9) ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect_num 10 ++#define TIMER0_COMP_vect _VECTOR(10) ++#define SIG_OUTPUT_COMPARE0 _VECTOR(10) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 11 ++#define TIMER0_OVF_vect _VECTOR(11) ++#define SIG_OVERFLOW0 _VECTOR(11) ++ ++/* Serial Transfer Complete */ ++#define SPI_STC_vect_num 12 ++#define SPI_STC_vect _VECTOR(12) ++#define SIG_SPI _VECTOR(12) ++ ++/* UART0, Rx Complete */ ++#define UART0_RX_vect_num 13 ++#define UART0_RX_vect _VECTOR(13) ++#define SIG_UART0_RECV _VECTOR(13) ++ ++/* UART1, Rx Complete */ ++#define UART1_RX_vect_num 14 ++#define UART1_RX_vect _VECTOR(14) ++#define SIG_UART1_RECV _VECTOR(14) ++ ++/* UART0 Data Register Empty */ ++#define UART0_UDRE_vect_num 15 ++#define UART0_UDRE_vect _VECTOR(15) ++#define SIG_UART0_DATA _VECTOR(15) ++ ++/* UART1 Data Register Empty */ ++#define UART1_UDRE_vect_num 16 ++#define UART1_UDRE_vect _VECTOR(16) ++#define SIG_UART1_DATA _VECTOR(16) ++ ++/* UART0, Tx Complete */ ++#define UART0_TX_vect_num 17 ++#define UART0_TX_vect _VECTOR(17) ++#define SIG_UART0_TRANS _VECTOR(17) ++ ++/* UART1, Tx Complete */ ++#define UART1_TX_vect_num 18 ++#define UART1_TX_vect _VECTOR(18) ++#define SIG_UART1_TRANS _VECTOR(18) ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect_num 19 ++#define EE_RDY_vect _VECTOR(19) ++#define SIG_EEPROM_READY _VECTOR(19) ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect_num 20 ++#define ANA_COMP_vect _VECTOR(20) ++#define SIG_COMPARATOR _VECTOR(20) ++ ++#define _VECTORS_SIZE 84 ++ ++/* Bit numbers */ ++ ++/* GIMSK */ ++#define INT1 7 ++#define INT0 6 ++#define INT2 5 ++ ++/* GIFR */ ++#define INTF1 7 ++#define INTF0 6 ++#define INTF2 5 ++ ++/* TIMSK */ ++#define TOIE1 7 ++#define OCIE1A 6 ++#define OCIE1B 5 ++#define TOIE2 4 ++#define TICIE1 3 ++#define OCIE2 2 ++#define TOIE0 1 ++#define OCIE0 0 ++ ++/* TIFR */ ++#define TOV1 7 ++#define OCF1A 6 ++#define OCF1B 5 ++#define TOV2 4 ++#define ICF1 3 ++#define OCF2 2 ++#define TOV0 1 ++#define OCF0 0 ++ ++/* MCUCR */ ++#define SRE 7 ++#define SRW10 6 ++#define SE 5 ++#define SM1 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* EMCUCR */ ++#define SM0 7 ++#define SRL2 6 ++#define SRL1 5 ++#define SRL0 4 ++#define SRW01 3 ++#define SRW00 2 ++#define SRW11 1 ++#define ISC2 0 ++ ++/* SPMCR */ ++#define BLBSET 3 ++#define PGWRT 2 ++#define PGERS 1 ++#define SPMEN 0 ++ ++/* SFIOR */ ++#define PSR2 1 ++#define PSR10 0 ++ ++/* TCCR0 */ ++#define FOC0 7 ++#define PWM0 6 ++#define COM01 5 ++#define COM00 4 ++#define CTC0 3 ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* TCCR2 */ ++#define FOC2 7 ++#define PWM2 6 ++#define COM21 5 ++#define COM20 4 ++#define CTC2 3 ++#define CS22 2 ++#define CS21 1 ++#define CS20 0 ++ ++/* ASSR */ ++#define AS2 3 ++#define TCN2UB 2 ++#define OCR2UB 1 ++#define TCR2UB 0 ++ ++/* TCCR1A */ ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define FOC1A 3 ++#define FOC1B 2 ++#define PWM11 1 ++#define PWM10 0 ++ ++/* TCCR1B */ ++#define ICNC1 7 ++#define ICES1 6 ++#define CTC1 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* WDTCR */ ++#define WDTOE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* PORTA */ ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++/* DDRA */ ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++/* PINA */ ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++/* ++ PB7 = SCK ++ PB6 = MISO ++ PB5 = MOSI ++ PB4 = SS# ++ PB3 = TXD1 / AIN1 ++ PB2 = RXD1 / AIN0 ++ PB1 = OC2 / T1 ++ PB0 = OC0 / T0 ++ */ ++ ++/* PORTB */ ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* DDRB */ ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* PINB */ ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* PORTC */ ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++/* DDRC */ ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++/* PINC */ ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++/* ++ PD7 = RD# ++ PD6 = WR# ++ PD5 = TOSC2 / OC1A ++ PD4 = TOSC1 ++ PD3 = INT1 ++ PD2 = INT0 ++ PD1 = TXD0 ++ PD0 = RXD0 ++ */ ++ ++/* PORTD */ ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* DDRD */ ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++/* PIND */ ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++/* ++ PE2 = ALE ++ PE1 = OC1B ++ PE0 = ICP / INT2 ++ */ ++ ++/* PORTE */ ++#define PE2 2 ++#define PE1 1 ++#define PE0 0 ++ ++/* DDRE */ ++#define DDE2 2 ++#define DDE1 1 ++#define DDE0 0 ++ ++/* PINE */ ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++/* SPSR */ ++#define SPIF 7 ++#define WCOL 6 ++#define SPI2X 0 ++ ++/* SPCR */ ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++/* UCSR0A, UCSR1A */ ++#define RXC 7 ++#define TXC 6 ++#define UDRE 5 ++#define FE 4 ++#define DOR 3 ++#define U2X 1 ++#define MPCM 0 ++ ++/* UCSR0B, UCSR1B */ ++#define RXCIE 7 ++#define TXCIE 6 ++#define UDRIE 5 ++#define RXEN 4 ++#define TXEN 3 ++#define CHR9 2 ++#define RXB8 1 ++#define TXB8 0 ++ ++/* ACSR */ ++#define ACD 7 ++#define AINBG 6 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++/* EEPROM Control Register */ ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++/* Constants */ ++#define SPM_PAGESIZE 128 ++#define RAMSTART 0x60 ++#define RAMEND 0x45F ++#define XRAMEND 0xFFFF ++#define E2END 0x1FF ++#define E2PAGESIZE 0 ++#define FLASHEND 0x3FFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_BOOTRST (unsigned char)~_BV(6) ++#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_SPIEN) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x01 ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_INTERRUPT1 ++#pragma GCC poison SIG_INTERRUPT2 ++#pragma GCC poison SIG_OUTPUT_COMPARE2 ++#pragma GCC poison SIG_OVERFLOW2 ++#pragma GCC poison SIG_INPUT_CAPTURE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OUTPUT_COMPARE0 ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_SPI ++#pragma GCC poison SIG_UART0_RECV ++#pragma GCC poison SIG_UART1_RECV ++#pragma GCC poison SIG_UART0_DATA ++#pragma GCC poison SIG_UART1_DATA ++#pragma GCC poison SIG_UART0_TRANS ++#pragma GCC poison SIG_UART1_TRANS ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_COMPARATOR ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++#endif /* _AVR_IOM161_H_ */ +diff --git a/include/avr/iom162.h b/include/avr/iom162.h +index 8cd454a..bc67f2a 100644 +--- a/include/avr/iom162.h ++++ b/include/avr/iom162.h +@@ -1,1015 +1,1016 @@ +-/* Copyright (c) 2002, Nils Kristian Strom +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom162.h 2230 2011-03-06 02:42:04Z arcanum $ */ +- +-/* iom162.h - definitions for ATmega162 */ +- +-#ifndef _AVR_IOM162_H_ +-#define _AVR_IOM162_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom162.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* Memory mapped I/O registers */ +- +-/* Timer/Counter3 Control Register A */ +-#define TCCR3A _SFR_MEM8(0x8B) +- +-/* Timer/Counter3 Control Register B */ +-#define TCCR3B _SFR_MEM8(0x8A) +- +-/* Timer/Counter3 - Counter Register */ +-#define TCNT3H _SFR_MEM8(0x89) +-#define TCNT3L _SFR_MEM8(0x88) +-#define TCNT3 _SFR_MEM16(0x88) +- +-/* Timer/Counter3 - Output Compare Register A */ +-#define OCR3AH _SFR_MEM8(0x87) +-#define OCR3AL _SFR_MEM8(0x86) +-#define OCR3A _SFR_MEM16(0x86) +- +-/* Timer/Counter3 - Output Compare Register B */ +-#define OCR3BH _SFR_MEM8(0x85) +-#define OCR3BL _SFR_MEM8(0x84) +-#define OCR3B _SFR_MEM16(0x84) +- +-/* Timer/Counter3 - Input Capture Register */ +-#define ICR3H _SFR_MEM8(0x81) +-#define ICR3L _SFR_MEM8(0x80) +-#define ICR3 _SFR_MEM16(0x80) +- +-/* Extended Timer/Counter Interrupt Mask */ +-#define ETIMSK _SFR_MEM8(0x7D) +- +-/* Extended Timer/Counter Interrupt Flag Register */ +-#define ETIFR _SFR_MEM8(0x7C) +- +-/* Pin Change Mask Register 1 */ +-#define PCMSK1 _SFR_MEM8(0x6C) +- +-/* Pin Change Mask Register 0 */ +-#define PCMSK0 _SFR_MEM8(0x6B) +- +-/* Clock PRescale */ +-#define CLKPR _SFR_MEM8(0x61) +- +- +-/* Standard I/O registers */ +- +-/* 0x3F SREG */ +-/* 0x3D..0x3E SP */ +-#define UBRR1H _SFR_IO8(0x3C) /* USART 1 Baud Rate Register High Byte, Shared with UCSR1C */ +-#define UCSR1C _SFR_IO8(0x3C) /* USART 1 Control and Status Register, Shared with UBRR1H */ +-#define GICR _SFR_IO8(0x3B) /* General Interrupt Control Register */ +-#define GIFR _SFR_IO8(0x3A) /* General Interrupt Flag Register */ +-#define TIMSK _SFR_IO8(0x39) /* Timer Interrupt Mask */ +-#define TIFR _SFR_IO8(0x38) /* Timer Interrupt Flag Register */ +-#define SPMCR _SFR_IO8(0x37) /* Store Program Memory Control Register */ +-#define EMCUCR _SFR_IO8(0x36) /* Extended MCU Control Register */ +-#define MCUCR _SFR_IO8(0x35) /* MCU Control Register */ +-#define MCUCSR _SFR_IO8(0x34) /* MCU Control and Status Register */ +-#define TCCR0 _SFR_IO8(0x33) /* Timer/Counter 0 Control Register */ +-#define TCNT0 _SFR_IO8(0x32) /* TImer/Counter 0 */ +-#define OCR0 _SFR_IO8(0x31) /* Output Compare Register 0 */ +-#define SFIOR _SFR_IO8(0x30) /* Special Function I/O Register */ +-#define TCCR1A _SFR_IO8(0x2F) /* Timer/Counter 1 Control Register A */ +-#define TCCR1B _SFR_IO8(0x2E) /* Timer/Counter 1 Control Register A */ +-#define TCNT1H _SFR_IO8(0x2D) /* Timer/Counter 1 High Byte */ +-#define TCNT1L _SFR_IO8(0x2C) /* Timer/Counter 1 Low Byte */ +-#define TCNT1 _SFR_IO16(0x2C) /* Timer/Counter 1 */ +-#define OCR1AH _SFR_IO8(0x2B) /* Timer/Counter 1 Output Compare Register A High Byte */ +-#define OCR1AL _SFR_IO8(0x2A) /* Timer/Counter 1 Output Compare Register A Low Byte */ +-#define OCR1A _SFR_IO16(0x2A) /* Timer/Counter 1 Output Compare Register A */ +-#define OCR1BH _SFR_IO8(0x29) /* Timer/Counter 1 Output Compare Register B High Byte */ +-#define OCR1BL _SFR_IO8(0x28) /* Timer/Counter 1 Output Compare Register B Low Byte */ +-#define OCR1B _SFR_IO16(0x28) /* Timer/Counter 1 Output Compare Register B */ +-#define TCCR2 _SFR_IO8(0x27) /* Timer/Counter 2 Control Register */ +-#define ASSR _SFR_IO8(0x26) /* Asynchronous Status Register */ +-#define ICR1H _SFR_IO8(0x25) /* Input Capture Register 1 High Byte */ +-#define ICR1L _SFR_IO8(0x24) /* Input Capture Register 1 Low Byte */ +-#define ICR1 _SFR_IO16(0x24) /* Input Capture Register 1 */ +-#define TCNT2 _SFR_IO8(0x23) /* Timer/Counter 2 */ +-#define OCR2 _SFR_IO8(0x22) /* Timer/Counter 2 Output Compare Register */ +-#define WDTCR _SFR_IO8(0x21) /* Watchdow Timer Control Register */ +-#define UBRR0H _SFR_IO8(0x20) /* USART 0 Baud-Rate Register High Byte, Shared with UCSR0C */ +-#define UCSR0C _SFR_IO8(0x20) /* USART 0 Control and Status Register C, Shared with UBRR0H */ +-#define EEARH _SFR_IO8(0x1F) /* EEPROM Address Register High Byte */ +-#define EEARL _SFR_IO8(0x1E) /* EEPROM Address Register Low Byte */ +-#define EEAR _SFR_IO16(0x1E) /* EEPROM Address Register */ +-#define EEDR _SFR_IO8(0x1D) /* EEPROM Data Register */ +-#define EECR _SFR_IO8(0x1C) /* EEPROM Control Register */ +-#define PORTA _SFR_IO8(0x1B) /* Port A */ +-#define DDRA _SFR_IO8(0x1A) /* Port A Data Direction Register */ +-#define PINA _SFR_IO8(0x19) /* Port A Pin Register */ +-#define PORTB _SFR_IO8(0x18) /* Port B */ +-#define DDRB _SFR_IO8(0x17) /* Port B Data Direction Register */ +-#define PINB _SFR_IO8(0x16) /* Port B Pin Register */ +-#define PORTC _SFR_IO8(0x15) /* Port C */ +-#define DDRC _SFR_IO8(0x14) /* Port C Data Direction Register */ +-#define PINC _SFR_IO8(0x13) /* Port C Pin Register */ +-#define PORTD _SFR_IO8(0x12) /* Port D */ +-#define DDRD _SFR_IO8(0x11) /* Port D Data Direction Register */ +-#define PIND _SFR_IO8(0x10) /* Port D Pin Register */ +-#define SPDR _SFR_IO8(0x0F) /* SPI Data Register */ +-#define SPSR _SFR_IO8(0x0E) /* SPI Status Register */ +-#define SPCR _SFR_IO8(0x0D) /* SPI Control Register */ +-#define UDR0 _SFR_IO8(0x0C) /* USART 0 Data Register */ +-#define UCSR0A _SFR_IO8(0x0B) /* USART 0 Control and Status Register A */ +-#define UCSR0B _SFR_IO8(0x0A) /* USART 0 Control and Status Register B */ +-#define UBRR0L _SFR_IO8(0x09) /* USART 0 Baud-Rate Register Low Byte */ +-#define ACSR _SFR_IO8(0x08) /* Analog Comparator Status Register */ +-#define PORTE _SFR_IO8(0x07) /* Port E */ +-#define DDRE _SFR_IO8(0x06) /* Port E Data Direction Register */ +-#define PINE _SFR_IO8(0x05) /* Port E Pin Register */ +-#define OSCCAL _SFR_IO8(0x04) /* Oscillator Calibration, Shared with OCDR */ +-#define OCDR _SFR_IO8(0x04) /* On-Chip Debug Register, Shared with OSCCAL */ +-#define UDR1 _SFR_IO8(0x03) /* USART 1 Data Register */ +-#define UCSR1A _SFR_IO8(0x02) /* USART 1 Control and Status Register A */ +-#define UCSR1B _SFR_IO8(0x01) /* USART 1 Control and Status Register B */ +-#define UBRR1L _SFR_IO8(0x00) /* USART 0 Baud Rate Register High Byte */ +- +- +-/* Interrupt vectors (byte addresses) */ +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt Request 1 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +-#define SIG_INTERRUPT1 _VECTOR(2) +- +-/* External Interrupt Request 2 */ +-#define INT2_vect_num 3 +-#define INT2_vect _VECTOR(3) +-#define SIG_INTERRUPT2 _VECTOR(3) +- +-/* Pin Change Interrupt Request 0 */ +-#define PCINT0_vect_num 4 +-#define PCINT0_vect _VECTOR(4) +-#define SIG_PIN_CHANGE0 _VECTOR(4) +- +-/* Pin Change Interrupt Request 1 */ +-#define PCINT1_vect_num 5 +-#define PCINT1_vect _VECTOR(5) +-#define SIG_PIN_CHANGE1 _VECTOR(5) +- +-/* Timer/Counter3 Capture Event */ +-#define TIMER3_CAPT_vect_num 6 +-#define TIMER3_CAPT_vect _VECTOR(6) +-#define SIG_INPUT_CAPTURE3 _VECTOR(6) +- +-/* Timer/Counter3 Compare Match A */ +-#define TIMER3_COMPA_vect_num 7 +-#define TIMER3_COMPA_vect _VECTOR(7) +-#define SIG_OUTPUT_COMPARE3A _VECTOR(7) +- +-/* Timer/Counter3 Compare Match B */ +-#define TIMER3_COMPB_vect_num 8 +-#define TIMER3_COMPB_vect _VECTOR(8) +-#define SIG_OUTPUT_COMPARE3B _VECTOR(8) +- +-/* Timer/Counter3 Overflow */ +-#define TIMER3_OVF_vect_num 9 +-#define TIMER3_OVF_vect _VECTOR(9) +-#define SIG_OVERFLOW3 _VECTOR(9) +- +-/* Timer/Counter2 Compare Match */ +-#define TIMER2_COMP_vect_num 10 +-#define TIMER2_COMP_vect _VECTOR(10) +-#define SIG_OUTPUT_COMPARE2 _VECTOR(10) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 11 +-#define TIMER2_OVF_vect _VECTOR(11) +-#define SIG_OVERFLOW2 _VECTOR(11) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 12 +-#define TIMER1_CAPT_vect _VECTOR(12) +-#define SIG_INPUT_CAPTURE1 _VECTOR(12) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 13 +-#define TIMER1_COMPA_vect _VECTOR(13) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(13) +- +-/* Timer/Counter Compare Match B */ +-#define TIMER1_COMPB_vect_num 14 +-#define TIMER1_COMPB_vect _VECTOR(14) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(14) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 15 +-#define TIMER1_OVF_vect _VECTOR(15) +-#define SIG_OVERFLOW1 _VECTOR(15) +- +-/* Timer/Counter0 Compare Match */ +-#define TIMER0_COMP_vect_num 16 +-#define TIMER0_COMP_vect _VECTOR(16) +-#define SIG_OUTPUT_COMPARE0 _VECTOR(16) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 17 +-#define TIMER0_OVF_vect _VECTOR(17) +-#define SIG_OVERFLOW0 _VECTOR(17) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 18 +-#define SPI_STC_vect _VECTOR(18) +-#define SIG_SPI _VECTOR(18) +- +-/* USART0, Rx Complete */ +-#define USART0_RXC_vect_num 19 +-#define USART0_RXC_vect _VECTOR(19) +-#define SIG_USART0_RECV _VECTOR(19) +- +-/* USART1, Rx Complete */ +-#define USART1_RXC_vect_num 20 +-#define USART1_RXC_vect _VECTOR(20) +-#define SIG_USART1_RECV _VECTOR(20) +- +-/* USART0 Data register Empty */ +-#define USART0_UDRE_vect_num 21 +-#define USART0_UDRE_vect _VECTOR(21) +-#define SIG_USART0_DATA _VECTOR(21) +- +-/* USART1, Data register Empty */ +-#define USART1_UDRE_vect_num 22 +-#define USART1_UDRE_vect _VECTOR(22) +-#define SIG_USART1_DATA _VECTOR(22) +- +-/* USART0, Tx Complete */ +-#define USART0_TXC_vect_num 23 +-#define USART0_TXC_vect _VECTOR(23) +-#define SIG_USART0_TRANS _VECTOR(23) +- +-/* USART1, Tx Complete */ +-#define USART1_TXC_vect_num 24 +-#define USART1_TXC_vect _VECTOR(24) +-#define SIG_USART1_TRANS _VECTOR(24) +- +-/* EEPROM Ready */ +-#define EE_RDY_vect_num 25 +-#define EE_RDY_vect _VECTOR(25) +-#define SIG_EEPROM_READY _VECTOR(25) +- +-/* Analog Comparator */ +-#define ANA_COMP_vect_num 26 +-#define ANA_COMP_vect _VECTOR(26) +-#define SIG_COMPARATOR _VECTOR(26) +- +-/* Store Program Memory Read */ +-#define SPM_RDY_vect_num 27 +-#define SPM_RDY_vect _VECTOR(27) +-#define SIG_SPM_READY _VECTOR(27) +- +-#define _VECTORS_SIZE 112 /* = (num vec+1) * 4 */ +- +- +- +- +- +-/* TCCR3B bit definitions, memory mapped I/O */ +- +-#define ICNC3 7 +-#define ICES3 6 +-#define WGM33 4 +-#define WGM32 3 +-#define CS32 2 +-#define CS31 1 +-#define CS30 0 +- +- +- +-/* TCCR3A bit definitions, memory mapped I/O */ +- +-#define COM3A1 7 +-#define COM3A0 6 +-#define COM3B1 5 +-#define COM3B0 4 +-#define FOC3A 3 +-#define FOC3B 2 +-#define WGM31 1 +-#define WGM30 0 +- +- +- +-/* ETIMSK bit definitions, memory mapped I/O */ +- +-#define TICIE3 5 +-#define OCIE3A 4 +-#define OCIE3B 3 +-#define TOIE3 2 +- +- +- +-/* ETIFR bit definitions, memory mapped I/O */ +- +-#define ICF3 5 +-#define OCF3A 4 +-#define OCF3B 3 +-#define TOV3 2 +- +- +- +-/* PCMSK1 bit definitions, memory mapped I/O */ +-#define PCINT15 7 +-#define PCINT14 6 +-#define PCINT13 5 +-#define PCINT12 4 +-#define PCINT11 3 +-#define PCINT10 2 +-#define PCINT9 1 +-#define PCINT8 0 +- +- +- +-/* PCMSK0 bit definitions, memory mapped I/O */ +- +-#define PCINT7 7 +-#define PCINT6 6 +-#define PCINT5 5 +-#define PCINT4 4 +-#define PCINT3 3 +-#define PCINT2 2 +-#define PCINT1 1 +-#define PCINT0 0 +- +- +- +-/* CLKPR bit definitions, memory mapped I/O */ +- +-#define CLKPCE 7 +-#define CLKPS3 3 +-#define CLKPS2 2 +-#define CLKPS1 1 +-#define CLKPS0 0 +- +- +- +-/* SPH bit definitions */ +- +-#define SP15 15 +-#define SP14 14 +-#define SP13 13 +-#define SP12 12 +-#define SP11 11 +-#define SP10 10 +-#define SP9 9 +-#define SP8 8 +- +- +- +-/* SPL bit definitions */ +- +-#define SP7 7 +-#define SP6 6 +-#define SP5 5 +-#define SP4 4 +-#define SP3 3 +-#define SP2 2 +-#define SP1 1 +-#define SP0 0 +- +- +- +-/* UBRR1H bit definitions */ +- +-#define URSEL1 7 +-#define UBRR111 3 +-#define UBRR110 2 +-#define UBRR19 1 +-#define UBRR18 0 +- +- +- +-/* UCSR1C bit definitions */ +- +-#define URSEL1 7 +-#define UMSEL1 6 +-#define UPM11 5 +-#define UPM10 4 +-#define USBS1 3 +-#define UCSZ11 2 +-#define UCSZ10 1 +-#define UCPOL1 0 +- +- +- +-/* GICR bit definitions */ +- +-#define INT1 7 +-#define INT0 6 +-#define INT2 5 +-#define PCIE1 4 +-#define PCIE0 3 +-#define IVSEL 1 +-#define IVCE 0 +- +- +- +-/* GIFR bit definitions */ +- +-#define INTF1 7 +-#define INTF0 6 +-#define INTF2 5 +-#define PCIF1 4 +-#define PCIF0 3 +- +- +- +-/* TIMSK bit definitions */ +- +-#define TOIE1 7 +-#define OCIE1A 6 +-#define OCIE1B 5 +-#define OCIE2 4 +-#define TICIE1 3 +-#define TOIE2 2 +-#define TOIE0 1 +-#define OCIE0 0 +- +- +- +-/* TIFR bit definitions */ +- +-#define TOV1 7 +-#define OCF1A 6 +-#define OCF1B 5 +-#define OCF2 4 +-#define ICF1 3 +-#define TOV2 2 +-#define TOV0 1 +-#define OCF0 0 +- +- +- +-/* SPMCR bit definitions */ +- +-#define SPMIE 7 +-#define RWWSB 6 +-#define RWWSRE 4 +-#define BLBSET 3 +-#define PGWRT 2 +-#define PGERS 1 +-#define SPMEN 0 +- +- +- +-/* EMCUCR bit definitions */ +- +-#define SM0 7 +-#define SRL2 6 +-#define SRL1 5 +-#define SRL0 4 +-#define SRW01 3 +-#define SRW00 2 +-#define SRW11 1 +-#define ISC2 0 +- +- +- +-/* MCUCR bit definitions */ +- +-#define SRE 7 +-#define SRW10 6 +-#define SE 5 +-#define SM1 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +- +- +-/* MCUCSR bit definitions */ +- +-#define JTD 7 +-#define SM2 5 +-#define JTRF 4 +-#define WDRF 3 +-#define BORF 2 +-#define EXTRF 1 +-#define PORF 0 +- +- +- +-/* TCCR0 bit definitions */ +- +-#define FOC0 7 +-#define WGM00 6 +-#define COM01 5 +-#define COM00 4 +-#define WGM01 3 +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +- +- +-/* SFIOR bit definitions */ +- +-#define TSM 7 +-#define XMBK 6 +-#define XMM2 5 +-#define XMM1 4 +-#define XMM0 3 +-#define PUD 2 +-#define PSR2 1 +-#define PSR310 0 +- +- +- +-/* TCCR1A bit definitions */ +- +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define FOC1A 3 +-#define FOC1B 2 +-#define WGM11 1 +-#define WGM10 0 +- +- +- +- +-/* TCCR1B bit definitions */ +- +-#define ICNC1 7 /* Input Capture Noise Canceler */ +-#define ICES1 6 /* Input Capture Edge Select */ +-#define WGM13 4 /* Waveform Generation Mode 3 */ +-#define WGM12 3 /* Waveform Generation Mode 2 */ +-#define CS12 2 /* Clock Select 2 */ +-#define CS11 1 /* Clock Select 1 */ +-#define CS10 0 /* Clock Select 0 */ +- +- +- +-/* TCCR2 bit definitions */ +- +-#define FOC2 7 +-#define WGM20 6 +-#define COM21 5 +-#define COM20 4 +-#define WGM21 3 +-#define CS22 2 +-#define CS21 1 +-#define CS20 0 +- +- +- +-/* ASSR bit definitions */ +- +-#define AS2 3 +-#define TCN2UB 2 +-#define TCON2UB 2 /* Kept for backwards compatibility. */ +-#define OCR2UB 1 +-#define TCR2UB 0 +- +- +- +-/* WDTCR bit definitions */ +- +-#define WDCE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +- +- +-/* UBRR0H bif definitions */ +- +-#define URSEL0 7 +-#define UBRR011 3 +-#define UBRR010 2 +-#define UBRR09 1 +-#define UBRR08 0 +- +- +- +-/* UCSR0C bit definitions */ +- +-#define URSEL0 7 +-#define UMSEL0 6 +-#define UPM01 5 +-#define UPM00 4 +-#define USBS0 3 +-#define UCSZ01 2 +-#define UCSZ00 1 +-#define UCPOL0 0 +- +- +- +-/* EEARH bit definitions */ +- +-#define EEAR8 0 +- +- +- +-/* EECR bit definitions */ +- +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +- +- +-/* PORTA bit definitions */ +- +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +- +- +-/* DDRA bit definitions */ +- +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +- +- +-/* PINA bit definitions */ +- +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +- +-/* PORTB bit definitions */ +- +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +- +- +-/* DDRB bit definitions */ +- +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +- +- +-/* PINB bit definitions */ +- +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +- +- +-/* PORTC bit definitions */ +- +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +- +- +-/* DDRC bit definitions */ +- +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +- +- +-/* PINC bit definitions */ +- +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +- +- +-/* PORTD bit definitions */ +- +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +- +- +-/* DDRD bit definitions */ +- +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +- +- +-/* PIND bit definitions */ +- +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +- +- +-/* SPSR bit definitions */ +- +-#define SPIF 7 +-#define WCOL 6 +-#define SPI2X 0 +- +- +- +-/* SPCR bit definitions */ +- +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +- +- +-/* UCSR0A bit definitions */ +- +-#define RXC0 7 +-#define TXC0 6 +-#define UDRE0 5 +-#define FE0 4 +-#define DOR0 3 +-#define UPE0 2 +-#define U2X0 1 +-#define MPCM0 0 +- +- +- +-/* UCSR0B bit definitions */ +- +-#define RXCIE0 7 +-#define TXCIE0 6 +-#define UDRIE0 5 +-#define RXEN0 4 +-#define TXEN0 3 +-#define UCSZ02 2 +-#define RXB80 1 +-#define TXB80 0 +- +- +- +-/* ACSR bit definitions */ +- +-#define ACD 7 +-#define ACBG 6 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +- +- +- +-/* PORTE bit definitions */ +- +-#define PE2 2 +-#define PE1 1 +-#define PE0 0 +- +- +- +-/* DDRE bit definitions */ +- +-#define DDE2 2 +-#define DDE1 1 +-#define DDE0 0 +- +- +- +-/* PINE bit definitions */ +- +-#define PINE2 2 +-#define PINE1 1 +-#define PINE0 0 +- +- +- +-/* UCSR1A bit definitions */ +- +-#define RXC1 7 +-#define TXC1 6 +-#define UDRE1 5 +-#define FE1 4 +-#define DOR1 3 +-#define UPE1 2 +-#define U2X1 1 +-#define MPCM1 0 +- +- +- +-/* UCSR1B bit definitions */ +- +-#define RXCIE1 7 +-#define TXCIE1 6 +-#define UDRIE1 5 +-#define RXEN1 4 +-#define TXEN1 3 +-#define UCSZ12 2 +-#define RXB81 1 +-#define TXB81 0 +- +- +-/* Constants */ +-#define SPM_PAGESIZE 128 +-#define RAMEND 0x4FF +-#define XRAMEND 0xFFFF +-#define E2END 0x1FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x3FFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) +-#define FUSE_M161C (unsigned char)~_BV(4) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x94 +-#define SIGNATURE_2 0x04 +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_INTERRUPT1 +-#pragma GCC poison SIG_INTERRUPT2 +-#pragma GCC poison SIG_PIN_CHANGE0 +-#pragma GCC poison SIG_PIN_CHANGE1 +-#pragma GCC poison SIG_INPUT_CAPTURE3 +-#pragma GCC poison SIG_OUTPUT_COMPARE3A +-#pragma GCC poison SIG_OUTPUT_COMPARE3B +-#pragma GCC poison SIG_OVERFLOW3 +-#pragma GCC poison SIG_OUTPUT_COMPARE2 +-#pragma GCC poison SIG_OVERFLOW2 +-#pragma GCC poison SIG_INPUT_CAPTURE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OUTPUT_COMPARE0 +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_SPI +-#pragma GCC poison SIG_USART0_RECV +-#pragma GCC poison SIG_USART1_RECV +-#pragma GCC poison SIG_USART0_DATA +-#pragma GCC poison SIG_USART1_DATA +-#pragma GCC poison SIG_USART0_TRANS +-#pragma GCC poison SIG_USART1_TRANS +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_SPM_READY +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +-#endif /* _AVR_IOM162_H_ */ ++/* Copyright (c) 2002, Nils Kristian Strom ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom162.h 2230 2011-03-06 02:42:04Z arcanum $ */ ++ ++/* iom162.h - definitions for ATmega162 */ ++ ++#ifndef _AVR_IOM162_H_ ++#define _AVR_IOM162_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom162.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Memory mapped I/O registers */ ++ ++/* Timer/Counter3 Control Register A */ ++#define TCCR3A _SFR_MEM8(0x8B) ++ ++/* Timer/Counter3 Control Register B */ ++#define TCCR3B _SFR_MEM8(0x8A) ++ ++/* Timer/Counter3 - Counter Register */ ++#define TCNT3H _SFR_MEM8(0x89) ++#define TCNT3L _SFR_MEM8(0x88) ++#define TCNT3 _SFR_MEM16(0x88) ++ ++/* Timer/Counter3 - Output Compare Register A */ ++#define OCR3AH _SFR_MEM8(0x87) ++#define OCR3AL _SFR_MEM8(0x86) ++#define OCR3A _SFR_MEM16(0x86) ++ ++/* Timer/Counter3 - Output Compare Register B */ ++#define OCR3BH _SFR_MEM8(0x85) ++#define OCR3BL _SFR_MEM8(0x84) ++#define OCR3B _SFR_MEM16(0x84) ++ ++/* Timer/Counter3 - Input Capture Register */ ++#define ICR3H _SFR_MEM8(0x81) ++#define ICR3L _SFR_MEM8(0x80) ++#define ICR3 _SFR_MEM16(0x80) ++ ++/* Extended Timer/Counter Interrupt Mask */ ++#define ETIMSK _SFR_MEM8(0x7D) ++ ++/* Extended Timer/Counter Interrupt Flag Register */ ++#define ETIFR _SFR_MEM8(0x7C) ++ ++/* Pin Change Mask Register 1 */ ++#define PCMSK1 _SFR_MEM8(0x6C) ++ ++/* Pin Change Mask Register 0 */ ++#define PCMSK0 _SFR_MEM8(0x6B) ++ ++/* Clock PRescale */ ++#define CLKPR _SFR_MEM8(0x61) ++ ++ ++/* Standard I/O registers */ ++ ++/* 0x3F SREG */ ++/* 0x3D..0x3E SP */ ++#define UBRR1H _SFR_IO8(0x3C) /* USART 1 Baud Rate Register High Byte, Shared with UCSR1C */ ++#define UCSR1C _SFR_IO8(0x3C) /* USART 1 Control and Status Register, Shared with UBRR1H */ ++#define GICR _SFR_IO8(0x3B) /* General Interrupt Control Register */ ++#define GIFR _SFR_IO8(0x3A) /* General Interrupt Flag Register */ ++#define TIMSK _SFR_IO8(0x39) /* Timer Interrupt Mask */ ++#define TIFR _SFR_IO8(0x38) /* Timer Interrupt Flag Register */ ++#define SPMCR _SFR_IO8(0x37) /* Store Program Memory Control Register */ ++#define EMCUCR _SFR_IO8(0x36) /* Extended MCU Control Register */ ++#define MCUCR _SFR_IO8(0x35) /* MCU Control Register */ ++#define MCUCSR _SFR_IO8(0x34) /* MCU Control and Status Register */ ++#define TCCR0 _SFR_IO8(0x33) /* Timer/Counter 0 Control Register */ ++#define TCNT0 _SFR_IO8(0x32) /* TImer/Counter 0 */ ++#define OCR0 _SFR_IO8(0x31) /* Output Compare Register 0 */ ++#define SFIOR _SFR_IO8(0x30) /* Special Function I/O Register */ ++#define TCCR1A _SFR_IO8(0x2F) /* Timer/Counter 1 Control Register A */ ++#define TCCR1B _SFR_IO8(0x2E) /* Timer/Counter 1 Control Register A */ ++#define TCNT1H _SFR_IO8(0x2D) /* Timer/Counter 1 High Byte */ ++#define TCNT1L _SFR_IO8(0x2C) /* Timer/Counter 1 Low Byte */ ++#define TCNT1 _SFR_IO16(0x2C) /* Timer/Counter 1 */ ++#define OCR1AH _SFR_IO8(0x2B) /* Timer/Counter 1 Output Compare Register A High Byte */ ++#define OCR1AL _SFR_IO8(0x2A) /* Timer/Counter 1 Output Compare Register A Low Byte */ ++#define OCR1A _SFR_IO16(0x2A) /* Timer/Counter 1 Output Compare Register A */ ++#define OCR1BH _SFR_IO8(0x29) /* Timer/Counter 1 Output Compare Register B High Byte */ ++#define OCR1BL _SFR_IO8(0x28) /* Timer/Counter 1 Output Compare Register B Low Byte */ ++#define OCR1B _SFR_IO16(0x28) /* Timer/Counter 1 Output Compare Register B */ ++#define TCCR2 _SFR_IO8(0x27) /* Timer/Counter 2 Control Register */ ++#define ASSR _SFR_IO8(0x26) /* Asynchronous Status Register */ ++#define ICR1H _SFR_IO8(0x25) /* Input Capture Register 1 High Byte */ ++#define ICR1L _SFR_IO8(0x24) /* Input Capture Register 1 Low Byte */ ++#define ICR1 _SFR_IO16(0x24) /* Input Capture Register 1 */ ++#define TCNT2 _SFR_IO8(0x23) /* Timer/Counter 2 */ ++#define OCR2 _SFR_IO8(0x22) /* Timer/Counter 2 Output Compare Register */ ++#define WDTCR _SFR_IO8(0x21) /* Watchdow Timer Control Register */ ++#define UBRR0H _SFR_IO8(0x20) /* USART 0 Baud-Rate Register High Byte, Shared with UCSR0C */ ++#define UCSR0C _SFR_IO8(0x20) /* USART 0 Control and Status Register C, Shared with UBRR0H */ ++#define EEARH _SFR_IO8(0x1F) /* EEPROM Address Register High Byte */ ++#define EEARL _SFR_IO8(0x1E) /* EEPROM Address Register Low Byte */ ++#define EEAR _SFR_IO16(0x1E) /* EEPROM Address Register */ ++#define EEDR _SFR_IO8(0x1D) /* EEPROM Data Register */ ++#define EECR _SFR_IO8(0x1C) /* EEPROM Control Register */ ++#define PORTA _SFR_IO8(0x1B) /* Port A */ ++#define DDRA _SFR_IO8(0x1A) /* Port A Data Direction Register */ ++#define PINA _SFR_IO8(0x19) /* Port A Pin Register */ ++#define PORTB _SFR_IO8(0x18) /* Port B */ ++#define DDRB _SFR_IO8(0x17) /* Port B Data Direction Register */ ++#define PINB _SFR_IO8(0x16) /* Port B Pin Register */ ++#define PORTC _SFR_IO8(0x15) /* Port C */ ++#define DDRC _SFR_IO8(0x14) /* Port C Data Direction Register */ ++#define PINC _SFR_IO8(0x13) /* Port C Pin Register */ ++#define PORTD _SFR_IO8(0x12) /* Port D */ ++#define DDRD _SFR_IO8(0x11) /* Port D Data Direction Register */ ++#define PIND _SFR_IO8(0x10) /* Port D Pin Register */ ++#define SPDR _SFR_IO8(0x0F) /* SPI Data Register */ ++#define SPSR _SFR_IO8(0x0E) /* SPI Status Register */ ++#define SPCR _SFR_IO8(0x0D) /* SPI Control Register */ ++#define UDR0 _SFR_IO8(0x0C) /* USART 0 Data Register */ ++#define UCSR0A _SFR_IO8(0x0B) /* USART 0 Control and Status Register A */ ++#define UCSR0B _SFR_IO8(0x0A) /* USART 0 Control and Status Register B */ ++#define UBRR0L _SFR_IO8(0x09) /* USART 0 Baud-Rate Register Low Byte */ ++#define ACSR _SFR_IO8(0x08) /* Analog Comparator Status Register */ ++#define PORTE _SFR_IO8(0x07) /* Port E */ ++#define DDRE _SFR_IO8(0x06) /* Port E Data Direction Register */ ++#define PINE _SFR_IO8(0x05) /* Port E Pin Register */ ++#define OSCCAL _SFR_IO8(0x04) /* Oscillator Calibration, Shared with OCDR */ ++#define OCDR _SFR_IO8(0x04) /* On-Chip Debug Register, Shared with OSCCAL */ ++#define UDR1 _SFR_IO8(0x03) /* USART 1 Data Register */ ++#define UCSR1A _SFR_IO8(0x02) /* USART 1 Control and Status Register A */ ++#define UCSR1B _SFR_IO8(0x01) /* USART 1 Control and Status Register B */ ++#define UBRR1L _SFR_IO8(0x00) /* USART 0 Baud Rate Register High Byte */ ++ ++ ++/* Interrupt vectors (byte addresses) */ ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++#define SIG_INTERRUPT1 _VECTOR(2) ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect_num 3 ++#define INT2_vect _VECTOR(3) ++#define SIG_INTERRUPT2 _VECTOR(3) ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect_num 4 ++#define PCINT0_vect _VECTOR(4) ++#define SIG_PIN_CHANGE0 _VECTOR(4) ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect_num 5 ++#define PCINT1_vect _VECTOR(5) ++#define SIG_PIN_CHANGE1 _VECTOR(5) ++ ++/* Timer/Counter3 Capture Event */ ++#define TIMER3_CAPT_vect_num 6 ++#define TIMER3_CAPT_vect _VECTOR(6) ++#define SIG_INPUT_CAPTURE3 _VECTOR(6) ++ ++/* Timer/Counter3 Compare Match A */ ++#define TIMER3_COMPA_vect_num 7 ++#define TIMER3_COMPA_vect _VECTOR(7) ++#define SIG_OUTPUT_COMPARE3A _VECTOR(7) ++ ++/* Timer/Counter3 Compare Match B */ ++#define TIMER3_COMPB_vect_num 8 ++#define TIMER3_COMPB_vect _VECTOR(8) ++#define SIG_OUTPUT_COMPARE3B _VECTOR(8) ++ ++/* Timer/Counter3 Overflow */ ++#define TIMER3_OVF_vect_num 9 ++#define TIMER3_OVF_vect _VECTOR(9) ++#define SIG_OVERFLOW3 _VECTOR(9) ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect_num 10 ++#define TIMER2_COMP_vect _VECTOR(10) ++#define SIG_OUTPUT_COMPARE2 _VECTOR(10) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 11 ++#define TIMER2_OVF_vect _VECTOR(11) ++#define SIG_OVERFLOW2 _VECTOR(11) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 12 ++#define TIMER1_CAPT_vect _VECTOR(12) ++#define SIG_INPUT_CAPTURE1 _VECTOR(12) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 13 ++#define TIMER1_COMPA_vect _VECTOR(13) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(13) ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect_num 14 ++#define TIMER1_COMPB_vect _VECTOR(14) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(14) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 15 ++#define TIMER1_OVF_vect _VECTOR(15) ++#define SIG_OVERFLOW1 _VECTOR(15) ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect_num 16 ++#define TIMER0_COMP_vect _VECTOR(16) ++#define SIG_OUTPUT_COMPARE0 _VECTOR(16) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 17 ++#define TIMER0_OVF_vect _VECTOR(17) ++#define SIG_OVERFLOW0 _VECTOR(17) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 18 ++#define SPI_STC_vect _VECTOR(18) ++#define SIG_SPI _VECTOR(18) ++ ++/* USART0, Rx Complete */ ++#define USART0_RXC_vect_num 19 ++#define USART0_RXC_vect _VECTOR(19) ++#define SIG_USART0_RECV _VECTOR(19) ++ ++/* USART1, Rx Complete */ ++#define USART1_RXC_vect_num 20 ++#define USART1_RXC_vect _VECTOR(20) ++#define SIG_USART1_RECV _VECTOR(20) ++ ++/* USART0 Data register Empty */ ++#define USART0_UDRE_vect_num 21 ++#define USART0_UDRE_vect _VECTOR(21) ++#define SIG_USART0_DATA _VECTOR(21) ++ ++/* USART1, Data register Empty */ ++#define USART1_UDRE_vect_num 22 ++#define USART1_UDRE_vect _VECTOR(22) ++#define SIG_USART1_DATA _VECTOR(22) ++ ++/* USART0, Tx Complete */ ++#define USART0_TXC_vect_num 23 ++#define USART0_TXC_vect _VECTOR(23) ++#define SIG_USART0_TRANS _VECTOR(23) ++ ++/* USART1, Tx Complete */ ++#define USART1_TXC_vect_num 24 ++#define USART1_TXC_vect _VECTOR(24) ++#define SIG_USART1_TRANS _VECTOR(24) ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect_num 25 ++#define EE_RDY_vect _VECTOR(25) ++#define SIG_EEPROM_READY _VECTOR(25) ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect_num 26 ++#define ANA_COMP_vect _VECTOR(26) ++#define SIG_COMPARATOR _VECTOR(26) ++ ++/* Store Program Memory Read */ ++#define SPM_RDY_vect_num 27 ++#define SPM_RDY_vect _VECTOR(27) ++#define SIG_SPM_READY _VECTOR(27) ++ ++#define _VECTORS_SIZE 112 /* = (num vec+1) * 4 */ ++ ++ ++ ++ ++ ++/* TCCR3B bit definitions, memory mapped I/O */ ++ ++#define ICNC3 7 ++#define ICES3 6 ++#define WGM33 4 ++#define WGM32 3 ++#define CS32 2 ++#define CS31 1 ++#define CS30 0 ++ ++ ++ ++/* TCCR3A bit definitions, memory mapped I/O */ ++ ++#define COM3A1 7 ++#define COM3A0 6 ++#define COM3B1 5 ++#define COM3B0 4 ++#define FOC3A 3 ++#define FOC3B 2 ++#define WGM31 1 ++#define WGM30 0 ++ ++ ++ ++/* ETIMSK bit definitions, memory mapped I/O */ ++ ++#define TICIE3 5 ++#define OCIE3A 4 ++#define OCIE3B 3 ++#define TOIE3 2 ++ ++ ++ ++/* ETIFR bit definitions, memory mapped I/O */ ++ ++#define ICF3 5 ++#define OCF3A 4 ++#define OCF3B 3 ++#define TOV3 2 ++ ++ ++ ++/* PCMSK1 bit definitions, memory mapped I/O */ ++#define PCINT15 7 ++#define PCINT14 6 ++#define PCINT13 5 ++#define PCINT12 4 ++#define PCINT11 3 ++#define PCINT10 2 ++#define PCINT9 1 ++#define PCINT8 0 ++ ++ ++ ++/* PCMSK0 bit definitions, memory mapped I/O */ ++ ++#define PCINT7 7 ++#define PCINT6 6 ++#define PCINT5 5 ++#define PCINT4 4 ++#define PCINT3 3 ++#define PCINT2 2 ++#define PCINT1 1 ++#define PCINT0 0 ++ ++ ++ ++/* CLKPR bit definitions, memory mapped I/O */ ++ ++#define CLKPCE 7 ++#define CLKPS3 3 ++#define CLKPS2 2 ++#define CLKPS1 1 ++#define CLKPS0 0 ++ ++ ++ ++/* SPH bit definitions */ ++ ++#define SP15 15 ++#define SP14 14 ++#define SP13 13 ++#define SP12 12 ++#define SP11 11 ++#define SP10 10 ++#define SP9 9 ++#define SP8 8 ++ ++ ++ ++/* SPL bit definitions */ ++ ++#define SP7 7 ++#define SP6 6 ++#define SP5 5 ++#define SP4 4 ++#define SP3 3 ++#define SP2 2 ++#define SP1 1 ++#define SP0 0 ++ ++ ++ ++/* UBRR1H bit definitions */ ++ ++#define URSEL1 7 ++#define UBRR111 3 ++#define UBRR110 2 ++#define UBRR19 1 ++#define UBRR18 0 ++ ++ ++ ++/* UCSR1C bit definitions */ ++ ++#define URSEL1 7 ++#define UMSEL1 6 ++#define UPM11 5 ++#define UPM10 4 ++#define USBS1 3 ++#define UCSZ11 2 ++#define UCSZ10 1 ++#define UCPOL1 0 ++ ++ ++ ++/* GICR bit definitions */ ++ ++#define INT1 7 ++#define INT0 6 ++#define INT2 5 ++#define PCIE1 4 ++#define PCIE0 3 ++#define IVSEL 1 ++#define IVCE 0 ++ ++ ++ ++/* GIFR bit definitions */ ++ ++#define INTF1 7 ++#define INTF0 6 ++#define INTF2 5 ++#define PCIF1 4 ++#define PCIF0 3 ++ ++ ++ ++/* TIMSK bit definitions */ ++ ++#define TOIE1 7 ++#define OCIE1A 6 ++#define OCIE1B 5 ++#define OCIE2 4 ++#define TICIE1 3 ++#define TOIE2 2 ++#define TOIE0 1 ++#define OCIE0 0 ++ ++ ++ ++/* TIFR bit definitions */ ++ ++#define TOV1 7 ++#define OCF1A 6 ++#define OCF1B 5 ++#define OCF2 4 ++#define ICF1 3 ++#define TOV2 2 ++#define TOV0 1 ++#define OCF0 0 ++ ++ ++ ++/* SPMCR bit definitions */ ++ ++#define SPMIE 7 ++#define RWWSB 6 ++#define RWWSRE 4 ++#define BLBSET 3 ++#define PGWRT 2 ++#define PGERS 1 ++#define SPMEN 0 ++ ++ ++ ++/* EMCUCR bit definitions */ ++ ++#define SM0 7 ++#define SRL2 6 ++#define SRL1 5 ++#define SRL0 4 ++#define SRW01 3 ++#define SRW00 2 ++#define SRW11 1 ++#define ISC2 0 ++ ++ ++ ++/* MCUCR bit definitions */ ++ ++#define SRE 7 ++#define SRW10 6 ++#define SE 5 ++#define SM1 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++ ++ ++/* MCUCSR bit definitions */ ++ ++#define JTD 7 ++#define SM2 5 ++#define JTRF 4 ++#define WDRF 3 ++#define BORF 2 ++#define EXTRF 1 ++#define PORF 0 ++ ++ ++ ++/* TCCR0 bit definitions */ ++ ++#define FOC0 7 ++#define WGM00 6 ++#define COM01 5 ++#define COM00 4 ++#define WGM01 3 ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++ ++ ++/* SFIOR bit definitions */ ++ ++#define TSM 7 ++#define XMBK 6 ++#define XMM2 5 ++#define XMM1 4 ++#define XMM0 3 ++#define PUD 2 ++#define PSR2 1 ++#define PSR310 0 ++ ++ ++ ++/* TCCR1A bit definitions */ ++ ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define FOC1A 3 ++#define FOC1B 2 ++#define WGM11 1 ++#define WGM10 0 ++ ++ ++ ++ ++/* TCCR1B bit definitions */ ++ ++#define ICNC1 7 /* Input Capture Noise Canceler */ ++#define ICES1 6 /* Input Capture Edge Select */ ++#define WGM13 4 /* Waveform Generation Mode 3 */ ++#define WGM12 3 /* Waveform Generation Mode 2 */ ++#define CS12 2 /* Clock Select 2 */ ++#define CS11 1 /* Clock Select 1 */ ++#define CS10 0 /* Clock Select 0 */ ++ ++ ++ ++/* TCCR2 bit definitions */ ++ ++#define FOC2 7 ++#define WGM20 6 ++#define COM21 5 ++#define COM20 4 ++#define WGM21 3 ++#define CS22 2 ++#define CS21 1 ++#define CS20 0 ++ ++ ++ ++/* ASSR bit definitions */ ++ ++#define AS2 3 ++#define TCN2UB 2 ++#define TCON2UB 2 /* Kept for backwards compatibility. */ ++#define OCR2UB 1 ++#define TCR2UB 0 ++ ++ ++ ++/* WDTCR bit definitions */ ++ ++#define WDCE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++ ++ ++/* UBRR0H bif definitions */ ++ ++#define URSEL0 7 ++#define UBRR011 3 ++#define UBRR010 2 ++#define UBRR09 1 ++#define UBRR08 0 ++ ++ ++ ++/* UCSR0C bit definitions */ ++ ++#define URSEL0 7 ++#define UMSEL0 6 ++#define UPM01 5 ++#define UPM00 4 ++#define USBS0 3 ++#define UCSZ01 2 ++#define UCSZ00 1 ++#define UCPOL0 0 ++ ++ ++ ++/* EEARH bit definitions */ ++ ++#define EEAR8 0 ++ ++ ++ ++/* EECR bit definitions */ ++ ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++ ++ ++/* PORTA bit definitions */ ++ ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++ ++ ++/* DDRA bit definitions */ ++ ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++ ++ ++/* PINA bit definitions */ ++ ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++ ++/* PORTB bit definitions */ ++ ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++ ++ ++/* DDRB bit definitions */ ++ ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++ ++ ++/* PINB bit definitions */ ++ ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++ ++ ++/* PORTC bit definitions */ ++ ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++ ++ ++/* DDRC bit definitions */ ++ ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++ ++ ++/* PINC bit definitions */ ++ ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++ ++ ++/* PORTD bit definitions */ ++ ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++ ++ ++/* DDRD bit definitions */ ++ ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++ ++ ++/* PIND bit definitions */ ++ ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++ ++ ++/* SPSR bit definitions */ ++ ++#define SPIF 7 ++#define WCOL 6 ++#define SPI2X 0 ++ ++ ++ ++/* SPCR bit definitions */ ++ ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++ ++ ++/* UCSR0A bit definitions */ ++ ++#define RXC0 7 ++#define TXC0 6 ++#define UDRE0 5 ++#define FE0 4 ++#define DOR0 3 ++#define UPE0 2 ++#define U2X0 1 ++#define MPCM0 0 ++ ++ ++ ++/* UCSR0B bit definitions */ ++ ++#define RXCIE0 7 ++#define TXCIE0 6 ++#define UDRIE0 5 ++#define RXEN0 4 ++#define TXEN0 3 ++#define UCSZ02 2 ++#define RXB80 1 ++#define TXB80 0 ++ ++ ++ ++/* ACSR bit definitions */ ++ ++#define ACD 7 ++#define ACBG 6 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++ ++ ++/* PORTE bit definitions */ ++ ++#define PE2 2 ++#define PE1 1 ++#define PE0 0 ++ ++ ++ ++/* DDRE bit definitions */ ++ ++#define DDE2 2 ++#define DDE1 1 ++#define DDE0 0 ++ ++ ++ ++/* PINE bit definitions */ ++ ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++ ++ ++/* UCSR1A bit definitions */ ++ ++#define RXC1 7 ++#define TXC1 6 ++#define UDRE1 5 ++#define FE1 4 ++#define DOR1 3 ++#define UPE1 2 ++#define U2X1 1 ++#define MPCM1 0 ++ ++ ++ ++/* UCSR1B bit definitions */ ++ ++#define RXCIE1 7 ++#define TXCIE1 6 ++#define UDRIE1 5 ++#define RXEN1 4 ++#define TXEN1 3 ++#define UCSZ12 2 ++#define RXB81 1 ++#define TXB81 0 ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE 128 ++#define RAMSTART 0x100 ++#define RAMEND 0x4FF ++#define XRAMEND 0xFFFF ++#define E2END 0x1FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x3FFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) ++#define FUSE_M161C (unsigned char)~_BV(4) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x04 ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_INTERRUPT1 ++#pragma GCC poison SIG_INTERRUPT2 ++#pragma GCC poison SIG_PIN_CHANGE0 ++#pragma GCC poison SIG_PIN_CHANGE1 ++#pragma GCC poison SIG_INPUT_CAPTURE3 ++#pragma GCC poison SIG_OUTPUT_COMPARE3A ++#pragma GCC poison SIG_OUTPUT_COMPARE3B ++#pragma GCC poison SIG_OVERFLOW3 ++#pragma GCC poison SIG_OUTPUT_COMPARE2 ++#pragma GCC poison SIG_OVERFLOW2 ++#pragma GCC poison SIG_INPUT_CAPTURE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OUTPUT_COMPARE0 ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_SPI ++#pragma GCC poison SIG_USART0_RECV ++#pragma GCC poison SIG_USART1_RECV ++#pragma GCC poison SIG_USART0_DATA ++#pragma GCC poison SIG_USART1_DATA ++#pragma GCC poison SIG_USART0_TRANS ++#pragma GCC poison SIG_USART1_TRANS ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_SPM_READY ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++#endif /* _AVR_IOM162_H_ */ +diff --git a/include/avr/iom163.h b/include/avr/iom163.h +index 22a3f9d..6172fea 100644 +--- a/include/avr/iom163.h ++++ b/include/avr/iom163.h +@@ -1,684 +1,685 @@ +-/* Copyright (c) 2002, Marek Michalkiewicz +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom163.h 2231 2011-03-07 05:06:55Z arcanum $ */ +- +-/* avr/iom163.h - definitions for ATmega163 */ +- +-#ifndef _AVR_IOM163_H_ +-#define _AVR_IOM163_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom163.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-#define TWBR _SFR_IO8(0x00) +-#define TWSR _SFR_IO8(0x01) +-#define TWAR _SFR_IO8(0x02) +-#define TWDR _SFR_IO8(0x03) +- +-/* ADC */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x04) +-#endif +-#define ADCW _SFR_IO16(0x04) +-#define ADCL _SFR_IO8(0x04) +-#define ADCH _SFR_IO8(0x05) +-#define ADCSR _SFR_IO8(0x06) +-#define ADMUX _SFR_IO8(0x07) +- +-/* analog comparator */ +-#define ACSR _SFR_IO8(0x08) +- +-/* UART */ +-#define UBRR _SFR_IO8(0x09) +-#define UCSRB _SFR_IO8(0x0A) +-#define UCSRA _SFR_IO8(0x0B) +-#define UDR _SFR_IO8(0x0C) +- +-/* SPI */ +-#define SPCR _SFR_IO8(0x0D) +-#define SPSR _SFR_IO8(0x0E) +-#define SPDR _SFR_IO8(0x0F) +- +-/* Port D */ +-#define PIND _SFR_IO8(0x10) +-#define DDRD _SFR_IO8(0x11) +-#define PORTD _SFR_IO8(0x12) +- +-/* Port C */ +-#define PINC _SFR_IO8(0x13) +-#define DDRC _SFR_IO8(0x14) +-#define PORTC _SFR_IO8(0x15) +- +-/* Port B */ +-#define PINB _SFR_IO8(0x16) +-#define DDRB _SFR_IO8(0x17) +-#define PORTB _SFR_IO8(0x18) +- +-/* Port A */ +-#define PINA _SFR_IO8(0x19) +-#define DDRA _SFR_IO8(0x1A) +-#define PORTA _SFR_IO8(0x1B) +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO16(0x1E) +-#define EEARL _SFR_IO8(0x1E) +-#define EEARH _SFR_IO8(0x1F) +- +-#define UBRRHI _SFR_IO8(0x20) +- +-#define WDTCR _SFR_IO8(0x21) +- +-#define ASSR _SFR_IO8(0x22) +- +-/* Timer 2 */ +-#define OCR2 _SFR_IO8(0x23) +-#define TCNT2 _SFR_IO8(0x24) +-#define TCCR2 _SFR_IO8(0x25) +- +-/* Timer 1 */ +-#define ICR1 _SFR_IO16(0x26) +-#define ICR1L _SFR_IO8(0x26) +-#define ICR1H _SFR_IO8(0x27) +-#define OCR1B _SFR_IO16(0x28) +-#define OCR1BL _SFR_IO8(0x28) +-#define OCR1BH _SFR_IO8(0x29) +-#define OCR1A _SFR_IO16(0x2A) +-#define OCR1AL _SFR_IO8(0x2A) +-#define OCR1AH _SFR_IO8(0x2B) +-#define TCNT1 _SFR_IO16(0x2C) +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1H _SFR_IO8(0x2D) +-#define TCCR1B _SFR_IO8(0x2E) +-#define TCCR1A _SFR_IO8(0x2F) +- +-#define SFIOR _SFR_IO8(0x30) +- +-#define OSCCAL _SFR_IO8(0x31) +- +-/* Timer 0 */ +-#define TCNT0 _SFR_IO8(0x32) +-#define TCCR0 _SFR_IO8(0x33) +- +-#define MCUSR _SFR_IO8(0x34) +-#define MCUCR _SFR_IO8(0x35) +- +-#define TWCR _SFR_IO8(0x36) +- +-#define SPMCR _SFR_IO8(0x37) +- +-#define TIFR _SFR_IO8(0x38) +-#define TIMSK _SFR_IO8(0x39) +- +-#define GIFR _SFR_IO8(0x3A) +-#define GIMSK _SFR_IO8(0x3B) +- +-/* 0x3C reserved */ +- +-/* 0x3D..0x3E SP */ +- +-/* 0x3F SREG */ +- +-/* Interrupt vectors */ +- +-/* External Interrupt 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt 1 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +-#define SIG_INTERRUPT1 _VECTOR(2) +- +-/* Timer/Counter2 Compare Match */ +-#define TIMER2_COMP_vect_num 3 +-#define TIMER2_COMP_vect _VECTOR(3) +-#define SIG_OUTPUT_COMPARE2 _VECTOR(3) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 4 +-#define TIMER2_OVF_vect _VECTOR(4) +-#define SIG_OVERFLOW2 _VECTOR(4) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 5 +-#define TIMER1_CAPT_vect _VECTOR(5) +-#define SIG_INPUT_CAPTURE1 _VECTOR(5) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 6 +-#define TIMER1_COMPA_vect _VECTOR(6) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(6) +- +-/* Timer/Counter1 Compare Match B */ +-#define TIMER1_COMPB_vect_num 7 +-#define TIMER1_COMPB_vect _VECTOR(7) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(7) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 8 +-#define TIMER1_OVF_vect _VECTOR(8) +-#define SIG_OVERFLOW1 _VECTOR(8) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 9 +-#define TIMER0_OVF_vect _VECTOR(9) +-#define SIG_OVERFLOW0 _VECTOR(9) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 10 +-#define SPI_STC_vect _VECTOR(10) +-#define SIG_SPI _VECTOR(10) +- +-/* UART, RX Complete */ +-#define UART_RX_vect_num 11 +-#define UART_RX_vect _VECTOR(11) +-#define SIG_UART_RECV _VECTOR(11) +- +-/* UART Data Register Empty */ +-#define UART_UDRE_vect_num 12 +-#define UART_UDRE_vect _VECTOR(12) +-#define SIG_UART_DATA _VECTOR(12) +- +-/* UART, TX Complete */ +-#define UART_TX_vect_num 13 +-#define UART_TX_vect _VECTOR(13) +-#define SIG_UART_TRANS _VECTOR(13) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 14 +-#define ADC_vect _VECTOR(14) +-#define SIG_ADC _VECTOR(14) +- +-/* EEPROM Ready */ +-#define EE_RDY_vect_num 15 +-#define EE_RDY_vect _VECTOR(15) +-#define SIG_EEPROM_READY _VECTOR(15) +- +-/* Analog Comparator */ +-#define ANA_COMP_vect_num 16 +-#define ANA_COMP_vect _VECTOR(16) +-#define SIG_COMPARATOR _VECTOR(16) +- +-/* 2-Wire Serial Interface */ +-#define TWI_vect_num 17 +-#define TWI_vect _VECTOR(17) +-#define SIG_2WIRE_SERIAL _VECTOR(17) +- +-#define _VECTORS_SIZE 72 +- +-/* Bit numbers */ +- +-/* GIMSK */ +-#define INT1 7 +-#define INT0 6 +-/* bit 5 reserved, undefined */ +-/* bits 4-0 reserved */ +- +-/* GIFR */ +-#define INTF1 7 +-#define INTF0 6 +-/* bits 5-0 reserved */ +- +-/* TIMSK */ +-#define OCIE2 7 +-#define TOIE2 6 +-#define TICIE1 5 +-#define OCIE1A 4 +-#define OCIE1B 3 +-#define TOIE1 2 +-/* bit 1 reserved */ +-#define TOIE0 0 +- +-/* TIFR */ +-#define OCF2 7 +-#define TOV2 6 +-#define ICF1 5 +-#define OCF1A 4 +-#define OCF1B 3 +-#define TOV1 2 +-/* bit 1 reserved, undefined */ +-#define TOV0 0 +- +-/* SPMCR */ +-/* bit 7 reserved */ +-#define ASB 6 +-/* bit 5 reserved */ +-#define ASRE 4 +-#define BLBSET 3 +-#define PGWRT 2 +-#define PGERS 1 +-#define SPMEN 0 +- +-/* TWCR */ +-#define TWINT 7 +-#define TWEA 6 +-#define TWSTA 5 +-#define TWSTO 4 +-#define TWWC 3 +-#define TWEN 2 +-/* bit 1 reserved */ +-#define TWIE 0 +- +-/* TWAR */ +-#define TWGCE 0 +- +-/* TWSR */ +-#define TWS7 7 +-#define TWS6 6 +-#define TWS5 5 +-#define TWS4 4 +-#define TWS3 3 +-/* bits 2-0 reserved */ +- +-/* MCUCR */ +-/* bit 7 reserved */ +-#define SE 6 +-#define SM1 5 +-#define SM0 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-/* MCUSR */ +-/* bits 7-4 reserved */ +-#define WDRF 3 +-#define BORF 2 +-#define EXTRF 1 +-#define PORF 0 +- +-/* SFIOR */ +-/* bits 7-4 reserved */ +-#define ACME 3 +-#define PUD 2 +-#define PSR2 1 +-#define PSR10 0 +- +-/* TCCR0 */ +-/* bits 7-3 reserved */ +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* TCCR2 */ +-#define FOC2 7 +-#define PWM2 6 +-#define COM21 5 +-#define COM20 4 +-#define CTC2 3 +-#define CS22 2 +-#define CS21 1 +-#define CS20 0 +- +-/* ASSR */ +-/* bits 7-4 reserved */ +-#define AS2 3 +-#define TCN2UB 2 +-#define OCR2UB 1 +-#define TCR2UB 0 +- +-/* TCCR1A */ +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define FOC1A 3 +-#define FOC1B 2 +-#define PWM11 1 +-#define PWM10 0 +- +-/* TCCR1B */ +-#define ICNC1 7 +-#define ICES1 6 +-/* bits 5-4 reserved */ +-#define CTC1 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* WDTCR */ +-/* bits 7-5 reserved */ +-#define WDTOE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* PA7-PA0 = ADC7-ADC0 */ +-/* PORTA */ +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-/* DDRA */ +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-/* PINA */ +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-/* +- PB7 = SCK +- PB6 = MISO +- PB5 = MOSI +- PB4 = SS# +- PB3 = AIN1 +- PB2 = AIN0 +- PB1 = T1 +- PB0 = T0 +- */ +- +-/* PORTB */ +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* DDRB */ +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* PINB */ +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* +- PC7 = TOSC2 +- PC6 = TOSC1 +- PC1 = SDA +- PC0 = SCL +- */ +-/* PORTC */ +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-/* DDRC */ +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-/* PINC */ +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-/* +- PD7 = OC2 +- PD6 = ICP +- PD5 = OC1A +- PD4 = OC1B +- PD3 = INT1 +- PD2 = INT0 +- PD1 = TXD +- PD0 = RXD +- */ +- +-/* PORTD */ +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* DDRD */ +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-/* PIND */ +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-/* SPSR */ +-#define SPIF 7 +-#define WCOL 6 +-/* bits 5-1 reserved */ +-#define SPI2X 0 +- +-/* SPCR */ +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +-/* UCSRA */ +-#define RXC 7 +-#define TXC 6 +-#define UDRE 5 +-#define FE 4 +-#define DOR 3 +-/* bit 2 reserved */ +-#define U2X 1 +-#define MPCM 0 +- +-/* UCSRB */ +-#define RXCIE 7 +-#define TXCIE 6 +-#define UDRIE 5 +-#define RXEN 4 +-#define TXEN 3 +-#define CHR9 2 +-#define RXB8 1 +-#define TXB8 0 +- +-/* ACSR */ +-#define ACD 7 +-#define AINBG 6 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +- +-/* ADCSR */ +-#define ADEN 7 +-#define ADSC 6 +-#define ADFR 5 +-#define ADIF 4 +-#define ADIE 3 +-#define ADPS2 2 +-#define ADPS1 1 +-#define ADPS0 0 +- +-/* ADMUX */ +-#define REFS1 7 +-#define REFS0 6 +-#define ADLAR 5 +-#define MUX4 4 +-#define MUX3 3 +-#define MUX2 2 +-#define MUX1 1 +-#define MUX0 0 +- +-/* EEPROM Control Register */ +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-/* Constants */ +-#define SPM_PAGESIZE 128 +-#define RAMEND 0x45F +-#define XRAMEND RAMEND +-#define E2END 0x1FF +-#define E2PAGESIZE 0 +-#define FLASHEND 0x3FFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 2 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_BODEN (unsigned char)~_BV(6) +-#define FUSE_BODLEVEL (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SPIEN) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define HFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x94 +-#define SIGNATURE_2 0x02 +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_INTERRUPT1 +-#pragma GCC poison SIG_OUTPUT_COMPARE2 +-#pragma GCC poison SIG_OVERFLOW2 +-#pragma GCC poison SIG_INPUT_CAPTURE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_SPI +-#pragma GCC poison SIG_UART_RECV +-#pragma GCC poison SIG_UART_DATA +-#pragma GCC poison SIG_UART_TRANS +-#pragma GCC poison SIG_ADC +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_2WIRE_SERIAL +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +- +- +-#endif /* _AVR_IOM163_H_ */ ++/* Copyright (c) 2002, Marek Michalkiewicz ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom163.h 2231 2011-03-07 05:06:55Z arcanum $ */ ++ ++/* avr/iom163.h - definitions for ATmega163 */ ++ ++#ifndef _AVR_IOM163_H_ ++#define _AVR_IOM163_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom163.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++#define TWBR _SFR_IO8(0x00) ++#define TWSR _SFR_IO8(0x01) ++#define TWAR _SFR_IO8(0x02) ++#define TWDR _SFR_IO8(0x03) ++ ++/* ADC */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCW _SFR_IO16(0x04) ++#define ADCL _SFR_IO8(0x04) ++#define ADCH _SFR_IO8(0x05) ++#define ADCSR _SFR_IO8(0x06) ++#define ADMUX _SFR_IO8(0x07) ++ ++/* analog comparator */ ++#define ACSR _SFR_IO8(0x08) ++ ++/* UART */ ++#define UBRR _SFR_IO8(0x09) ++#define UCSRB _SFR_IO8(0x0A) ++#define UCSRA _SFR_IO8(0x0B) ++#define UDR _SFR_IO8(0x0C) ++ ++/* SPI */ ++#define SPCR _SFR_IO8(0x0D) ++#define SPSR _SFR_IO8(0x0E) ++#define SPDR _SFR_IO8(0x0F) ++ ++/* Port D */ ++#define PIND _SFR_IO8(0x10) ++#define DDRD _SFR_IO8(0x11) ++#define PORTD _SFR_IO8(0x12) ++ ++/* Port C */ ++#define PINC _SFR_IO8(0x13) ++#define DDRC _SFR_IO8(0x14) ++#define PORTC _SFR_IO8(0x15) ++ ++/* Port B */ ++#define PINB _SFR_IO8(0x16) ++#define DDRB _SFR_IO8(0x17) ++#define PORTB _SFR_IO8(0x18) ++ ++/* Port A */ ++#define PINA _SFR_IO8(0x19) ++#define DDRA _SFR_IO8(0x1A) ++#define PORTA _SFR_IO8(0x1B) ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO16(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++#define EEARH _SFR_IO8(0x1F) ++ ++#define UBRRHI _SFR_IO8(0x20) ++ ++#define WDTCR _SFR_IO8(0x21) ++ ++#define ASSR _SFR_IO8(0x22) ++ ++/* Timer 2 */ ++#define OCR2 _SFR_IO8(0x23) ++#define TCNT2 _SFR_IO8(0x24) ++#define TCCR2 _SFR_IO8(0x25) ++ ++/* Timer 1 */ ++#define ICR1 _SFR_IO16(0x26) ++#define ICR1L _SFR_IO8(0x26) ++#define ICR1H _SFR_IO8(0x27) ++#define OCR1B _SFR_IO16(0x28) ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BH _SFR_IO8(0x29) ++#define OCR1A _SFR_IO16(0x2A) ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++#define TCNT1 _SFR_IO16(0x2C) ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++#define TCCR1B _SFR_IO8(0x2E) ++#define TCCR1A _SFR_IO8(0x2F) ++ ++#define SFIOR _SFR_IO8(0x30) ++ ++#define OSCCAL _SFR_IO8(0x31) ++ ++/* Timer 0 */ ++#define TCNT0 _SFR_IO8(0x32) ++#define TCCR0 _SFR_IO8(0x33) ++ ++#define MCUSR _SFR_IO8(0x34) ++#define MCUCR _SFR_IO8(0x35) ++ ++#define TWCR _SFR_IO8(0x36) ++ ++#define SPMCR _SFR_IO8(0x37) ++ ++#define TIFR _SFR_IO8(0x38) ++#define TIMSK _SFR_IO8(0x39) ++ ++#define GIFR _SFR_IO8(0x3A) ++#define GIMSK _SFR_IO8(0x3B) ++ ++/* 0x3C reserved */ ++ ++/* 0x3D..0x3E SP */ ++ ++/* 0x3F SREG */ ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt 1 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++#define SIG_INTERRUPT1 _VECTOR(2) ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect_num 3 ++#define TIMER2_COMP_vect _VECTOR(3) ++#define SIG_OUTPUT_COMPARE2 _VECTOR(3) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 4 ++#define TIMER2_OVF_vect _VECTOR(4) ++#define SIG_OVERFLOW2 _VECTOR(4) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 5 ++#define TIMER1_CAPT_vect _VECTOR(5) ++#define SIG_INPUT_CAPTURE1 _VECTOR(5) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 6 ++#define TIMER1_COMPA_vect _VECTOR(6) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(6) ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect_num 7 ++#define TIMER1_COMPB_vect _VECTOR(7) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(7) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 8 ++#define TIMER1_OVF_vect _VECTOR(8) ++#define SIG_OVERFLOW1 _VECTOR(8) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 9 ++#define TIMER0_OVF_vect _VECTOR(9) ++#define SIG_OVERFLOW0 _VECTOR(9) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 10 ++#define SPI_STC_vect _VECTOR(10) ++#define SIG_SPI _VECTOR(10) ++ ++/* UART, RX Complete */ ++#define UART_RX_vect_num 11 ++#define UART_RX_vect _VECTOR(11) ++#define SIG_UART_RECV _VECTOR(11) ++ ++/* UART Data Register Empty */ ++#define UART_UDRE_vect_num 12 ++#define UART_UDRE_vect _VECTOR(12) ++#define SIG_UART_DATA _VECTOR(12) ++ ++/* UART, TX Complete */ ++#define UART_TX_vect_num 13 ++#define UART_TX_vect _VECTOR(13) ++#define SIG_UART_TRANS _VECTOR(13) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 14 ++#define ADC_vect _VECTOR(14) ++#define SIG_ADC _VECTOR(14) ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect_num 15 ++#define EE_RDY_vect _VECTOR(15) ++#define SIG_EEPROM_READY _VECTOR(15) ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect_num 16 ++#define ANA_COMP_vect _VECTOR(16) ++#define SIG_COMPARATOR _VECTOR(16) ++ ++/* 2-Wire Serial Interface */ ++#define TWI_vect_num 17 ++#define TWI_vect _VECTOR(17) ++#define SIG_2WIRE_SERIAL _VECTOR(17) ++ ++#define _VECTORS_SIZE 72 ++ ++/* Bit numbers */ ++ ++/* GIMSK */ ++#define INT1 7 ++#define INT0 6 ++/* bit 5 reserved, undefined */ ++/* bits 4-0 reserved */ ++ ++/* GIFR */ ++#define INTF1 7 ++#define INTF0 6 ++/* bits 5-0 reserved */ ++ ++/* TIMSK */ ++#define OCIE2 7 ++#define TOIE2 6 ++#define TICIE1 5 ++#define OCIE1A 4 ++#define OCIE1B 3 ++#define TOIE1 2 ++/* bit 1 reserved */ ++#define TOIE0 0 ++ ++/* TIFR */ ++#define OCF2 7 ++#define TOV2 6 ++#define ICF1 5 ++#define OCF1A 4 ++#define OCF1B 3 ++#define TOV1 2 ++/* bit 1 reserved, undefined */ ++#define TOV0 0 ++ ++/* SPMCR */ ++/* bit 7 reserved */ ++#define ASB 6 ++/* bit 5 reserved */ ++#define ASRE 4 ++#define BLBSET 3 ++#define PGWRT 2 ++#define PGERS 1 ++#define SPMEN 0 ++ ++/* TWCR */ ++#define TWINT 7 ++#define TWEA 6 ++#define TWSTA 5 ++#define TWSTO 4 ++#define TWWC 3 ++#define TWEN 2 ++/* bit 1 reserved */ ++#define TWIE 0 ++ ++/* TWAR */ ++#define TWGCE 0 ++ ++/* TWSR */ ++#define TWS7 7 ++#define TWS6 6 ++#define TWS5 5 ++#define TWS4 4 ++#define TWS3 3 ++/* bits 2-0 reserved */ ++ ++/* MCUCR */ ++/* bit 7 reserved */ ++#define SE 6 ++#define SM1 5 ++#define SM0 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* MCUSR */ ++/* bits 7-4 reserved */ ++#define WDRF 3 ++#define BORF 2 ++#define EXTRF 1 ++#define PORF 0 ++ ++/* SFIOR */ ++/* bits 7-4 reserved */ ++#define ACME 3 ++#define PUD 2 ++#define PSR2 1 ++#define PSR10 0 ++ ++/* TCCR0 */ ++/* bits 7-3 reserved */ ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* TCCR2 */ ++#define FOC2 7 ++#define PWM2 6 ++#define COM21 5 ++#define COM20 4 ++#define CTC2 3 ++#define CS22 2 ++#define CS21 1 ++#define CS20 0 ++ ++/* ASSR */ ++/* bits 7-4 reserved */ ++#define AS2 3 ++#define TCN2UB 2 ++#define OCR2UB 1 ++#define TCR2UB 0 ++ ++/* TCCR1A */ ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define FOC1A 3 ++#define FOC1B 2 ++#define PWM11 1 ++#define PWM10 0 ++ ++/* TCCR1B */ ++#define ICNC1 7 ++#define ICES1 6 ++/* bits 5-4 reserved */ ++#define CTC1 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* WDTCR */ ++/* bits 7-5 reserved */ ++#define WDTOE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* PA7-PA0 = ADC7-ADC0 */ ++/* PORTA */ ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++/* DDRA */ ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++/* PINA */ ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++/* ++ PB7 = SCK ++ PB6 = MISO ++ PB5 = MOSI ++ PB4 = SS# ++ PB3 = AIN1 ++ PB2 = AIN0 ++ PB1 = T1 ++ PB0 = T0 ++ */ ++ ++/* PORTB */ ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* DDRB */ ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* PINB */ ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* ++ PC7 = TOSC2 ++ PC6 = TOSC1 ++ PC1 = SDA ++ PC0 = SCL ++ */ ++/* PORTC */ ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++/* DDRC */ ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++/* PINC */ ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++/* ++ PD7 = OC2 ++ PD6 = ICP ++ PD5 = OC1A ++ PD4 = OC1B ++ PD3 = INT1 ++ PD2 = INT0 ++ PD1 = TXD ++ PD0 = RXD ++ */ ++ ++/* PORTD */ ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* DDRD */ ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++/* PIND */ ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++/* SPSR */ ++#define SPIF 7 ++#define WCOL 6 ++/* bits 5-1 reserved */ ++#define SPI2X 0 ++ ++/* SPCR */ ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++/* UCSRA */ ++#define RXC 7 ++#define TXC 6 ++#define UDRE 5 ++#define FE 4 ++#define DOR 3 ++/* bit 2 reserved */ ++#define U2X 1 ++#define MPCM 0 ++ ++/* UCSRB */ ++#define RXCIE 7 ++#define TXCIE 6 ++#define UDRIE 5 ++#define RXEN 4 ++#define TXEN 3 ++#define CHR9 2 ++#define RXB8 1 ++#define TXB8 0 ++ ++/* ACSR */ ++#define ACD 7 ++#define AINBG 6 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++/* ADCSR */ ++#define ADEN 7 ++#define ADSC 6 ++#define ADFR 5 ++#define ADIF 4 ++#define ADIE 3 ++#define ADPS2 2 ++#define ADPS1 1 ++#define ADPS0 0 ++ ++/* ADMUX */ ++#define REFS1 7 ++#define REFS0 6 ++#define ADLAR 5 ++#define MUX4 4 ++#define MUX3 3 ++#define MUX2 2 ++#define MUX1 1 ++#define MUX0 0 ++ ++/* EEPROM Control Register */ ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++/* Constants */ ++#define SPM_PAGESIZE 128 ++#define RAMSTART 0x60 ++#define RAMEND 0x45F ++#define XRAMEND RAMEND ++#define E2END 0x1FF ++#define E2PAGESIZE 0 ++#define FLASHEND 0x3FFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 2 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_BODEN (unsigned char)~_BV(6) ++#define FUSE_BODLEVEL (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SPIEN) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define HFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x02 ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_INTERRUPT1 ++#pragma GCC poison SIG_OUTPUT_COMPARE2 ++#pragma GCC poison SIG_OVERFLOW2 ++#pragma GCC poison SIG_INPUT_CAPTURE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_SPI ++#pragma GCC poison SIG_UART_RECV ++#pragma GCC poison SIG_UART_DATA ++#pragma GCC poison SIG_UART_TRANS ++#pragma GCC poison SIG_ADC ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_2WIRE_SERIAL ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++ ++ ++#endif /* _AVR_IOM163_H_ */ +diff --git a/include/avr/iom164.h b/include/avr/iom164.h +index 9c64599..9f3a17a 100644 +--- a/include/avr/iom164.h ++++ b/include/avr/iom164.h +@@ -1,95 +1,95 @@ +-/* Copyright (c) 2005, 2006 Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* avr/iom164.h - definitions for ATmega164 */ +- +-/* $Id: iom164.h 2115 2010-04-05 23:19:53Z arcanum $ */ +- +-#ifndef _AVR_IOM164_H_ +-#define _AVR_IOM164_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 128 +-#define RAMSTART (0x100) +-#define RAMEND 0x04FF +-#define XRAMEND RAMEND +-#define E2END 0x1FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x3FFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature (ATmega164P) */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x94 +-#define SIGNATURE_2 0x0A +- +- +-#endif /* _AVR_IOM164_H_ */ ++/* Copyright (c) 2005, 2006 Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* avr/iom164.h - definitions for ATmega164 */ ++ ++/* $Id: iom164.h 2115 2010-04-05 23:19:53Z arcanum $ */ ++ ++#ifndef _AVR_IOM164_H_ ++#define _AVR_IOM164_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 128 ++#define RAMSTART (0x100) ++#define RAMEND 0x04FF ++#define XRAMEND RAMEND ++#define E2END 0x1FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x3FFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature (ATmega164P) */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x0A ++ ++ ++#endif /* _AVR_IOM164_H_ */ +diff --git a/include/avr/iom164a.h b/include/avr/iom164a.h +new file mode 100644 +index 0000000..4b9d790 +--- /dev/null ++++ b/include/avr/iom164a.h +@@ -0,0 +1,34 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2011 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++#include "iom164.h" +diff --git a/include/avr/iom164p.h b/include/avr/iom164p.h +new file mode 100644 +index 0000000..4b9d790 +--- /dev/null ++++ b/include/avr/iom164p.h +@@ -0,0 +1,34 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2011 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++#include "iom164.h" +diff --git a/include/avr/iom164pa.h b/include/avr/iom164pa.h +new file mode 100644 +index 0000000..16d264d +--- /dev/null ++++ b/include/avr/iom164pa.h +@@ -0,0 +1,926 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATMEGA164PA_H_INCLUDED ++#define _AVR_ATMEGA164PA_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom164pa.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDRA7 7 ++#define DDRA6 6 ++#define DDRA5 5 ++#define DDRA4 4 ++#define DDRA3 3 ++#define DDRA2 2 ++#define DDRA1 1 ++#define DDRA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDRC7 7 ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC7 7 ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++/* Reserved [0x0C..0x14] */ ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++/* Reserved [0x18..0x1A] */ ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++#define PCIF3 3 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define TSM 7 ++#define PSRASY 1 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++ ++#define OCR0A _SFR_IO8(0x27) ++ ++#define OCR0B _SFR_IO8(0x28) ++ ++/* Reserved [0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR0 _SFR_IO8(0x2C) ++#define SPR00 0 ++#define SPR10 1 ++#define CPHA0 2 ++#define CPOL0 3 ++#define MSTR0 4 ++#define DORD0 5 ++#define SPE0 6 ++#define SPIE0 7 ++ ++#define SPSR0 _SFR_IO8(0x2D) ++#define SPI2X0 0 ++#define WCOL0 6 ++#define SPIF0 7 ++ ++#define SPDR0 _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR7 7 ++#define OCDR6 6 ++#define OCDR5 5 ++#define OCDR4 4 ++#define OCDR3 3 ++#define OCDR2 2 ++#define OCDR1 1 ++#define OCDR0 0 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define JTRF 4 ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define JTD 7 ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDE 3 ++#define WDCE 4 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRUSART0 1 ++#define PRUSART1 4 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++/* Reserved [0x67] */ ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++#define PCIE3 3 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++/* Reserved [0x71..0x72] */ ++ ++#define PCMSK3 _SFR_MEM8(0x73) ++#define PCINT24 0 ++#define PCINT25 1 ++#define PCINT26 2 ++#define PCINT27 3 ++#define PCINT28 4 ++#define PCINT29 5 ++#define PCINT30 6 ++#define PCINT31 7 ++ ++/* Reserved [0x74..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ACME 6 ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++#define OCR2B _SFR_MEM8(0xB4) ++ ++/* Reserved [0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++ ++/* Reserved [0xB7] */ ++ ++#define TWBR _SFR_MEM8(0xB8) ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++/* Reserved [0xBE..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0xC6) ++ ++/* Reserved [0xC7] */ ++ ++#define UCSR1A _SFR_MEM8(0xC8) ++#define MPCM1 0 ++#define U2X1 1 ++#define UPE1 2 ++#define DOR1 3 ++#define FE1 4 ++#define UDRE1 5 ++#define TXC1 6 ++#define RXC1 7 ++ ++#define UCSR1B _SFR_MEM8(0xC9) ++#define TXB81 0 ++#define RXB81 1 ++#define UCSZ12 2 ++#define TXEN1 3 ++#define RXEN1 4 ++#define UDRIE1 5 ++#define TXCIE1 6 ++#define RXCIE1 7 ++ ++#define UCSR1C _SFR_MEM8(0xCA) ++#define UCPOL1 0 ++#define UCSZ10 1 ++#define UCSZ11 2 ++#define USBS1 3 ++#define UPM10 4 ++#define UPM11 5 ++#define UMSEL10 6 ++#define UMSEL11 7 ++ ++/* Reserved [0xCB] */ ++ ++/* Combine UBRR1L and UBRR1H */ ++#define UBRR1 _SFR_MEM16(0xCC) ++ ++#define UBRR1L _SFR_MEM8(0xCC) ++#define UBRR1H _SFR_MEM8(0xCD) ++ ++#define UDR1 _SFR_MEM8(0xCE) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect _VECTOR(3) ++#define INT2_vect_num 3 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(4) ++#define PCINT0_vect_num 4 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(5) ++#define PCINT1_vect_num 5 ++ ++/* Pin Change Interrupt Request 2 */ ++#define PCINT2_vect _VECTOR(6) ++#define PCINT2_vect_num 6 ++ ++/* Pin Change Interrupt Request 3 */ ++#define PCINT3_vect _VECTOR(7) ++#define PCINT3_vect_num 7 ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect _VECTOR(8) ++#define WDT_vect_num 8 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPA_vect _VECTOR(9) ++#define TIMER2_COMPA_vect_num 9 ++ ++/* Timer/Counter2 Compare Match B */ ++#define TIMER2_COMPB_vect _VECTOR(10) ++#define TIMER2_COMPB_vect_num 10 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(11) ++#define TIMER2_OVF_vect_num 11 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(12) ++#define TIMER1_CAPT_vect_num 12 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(13) ++#define TIMER1_COMPA_vect_num 13 ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(14) ++#define TIMER1_COMPB_vect_num 14 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(15) ++#define TIMER1_OVF_vect_num 15 ++ ++/* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPA_vect _VECTOR(16) ++#define TIMER0_COMPA_vect_num 16 ++ ++/* Timer/Counter0 Compare Match B */ ++#define TIMER0_COMPB_vect _VECTOR(17) ++#define TIMER0_COMPB_vect_num 17 ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(18) ++#define TIMER0_OVF_vect_num 18 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(19) ++#define SPI_STC_vect_num 19 ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect _VECTOR(20) ++#define USART0_RX_vect_num 20 ++ ++/* USART0 Data register Empty */ ++#define USART0_UDRE_vect _VECTOR(21) ++#define USART0_UDRE_vect_num 21 ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect _VECTOR(22) ++#define USART0_TX_vect_num 22 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(23) ++#define ANALOG_COMP_vect_num 23 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(24) ++#define ADC_vect_num 24 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(25) ++#define EE_READY_vect_num 25 ++ ++/* 2-wire Serial Interface */ ++#define TWI_vect _VECTOR(26) ++#define TWI_vect_num 26 ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect _VECTOR(27) ++#define SPM_READY_vect_num 27 ++ ++/* USART1 RX complete */ ++#define USART1_RX_vect _VECTOR(28) ++#define USART1_RX_vect_num 28 ++ ++/* USART1 Data Register Empty */ ++#define USART1_UDRE_vect _VECTOR(29) ++#define USART1_UDRE_vect_num 29 ++ ++/* USART1 TX complete */ ++#define USART1_TX_vect _VECTOR(30) ++#define USART1_TX_vect_num 30 ++ ++#define _VECTORS_SIZE 124 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 128 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x3FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 1024 ++#define RAMEND 0x04FF ++#define E2START 0 ++#define E2SIZE 512 ++#define E2PAGESIZE 4 ++#define E2END 0x01FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x0A ++ ++ ++#endif /* #ifdef _AVR_ATMEGA164PA_H_INCLUDED */ ++ +diff --git a/include/avr/iom165.h b/include/avr/iom165.h +index 855e39a..657758f 100644 +--- a/include/avr/iom165.h ++++ b/include/avr/iom165.h +@@ -1,874 +1,875 @@ +-/* Copyright (c) 2004,2005,2006 Eric B. Weddington +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom165.h 2231 2011-03-07 05:06:55Z arcanum $ */ +- +-/* avr/iom165.h - definitions for ATmega165 */ +- +-#ifndef _AVR_IOM165_H_ +-#define _AVR_IOM165_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom165.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* Registers and associated bit numbers */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-#define PORTA _SFR_IO8(0x02) +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-#define PINB _SFR_IO8(0x03) +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-#define PORTB _SFR_IO8(0x05) +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-#define PORTC _SFR_IO8(0x08) +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-#define PINE _SFR_IO8(0x0C) +-#define PINE7 7 +-#define PINE6 6 +-#define PINE5 5 +-#define PINE4 4 +-#define PINE3 3 +-#define PINE2 2 +-#define PINE1 1 +-#define PINE0 0 +- +-#define DDRE _SFR_IO8(0x0D) +-#define DDE7 7 +-#define DDE6 6 +-#define DDE5 5 +-#define DDE4 4 +-#define DDE3 3 +-#define DDE2 2 +-#define DDE1 1 +-#define DDE0 0 +- +-#define PORTE _SFR_IO8(0x0E) +-#define PE7 7 +-#define PE6 6 +-#define PE5 5 +-#define PE4 4 +-#define PE3 3 +-#define PE2 2 +-#define PE1 1 +-#define PE0 0 +- +-#define PINF _SFR_IO8(0x0F) +-#define PINF7 7 +-#define PINF6 6 +-#define PINF5 5 +-#define PINF4 4 +-#define PINF3 3 +-#define PINF2 2 +-#define PINF1 1 +-#define PINF0 0 +- +-#define DDRF _SFR_IO8(0x10) +-#define DDF7 7 +-#define DDF6 6 +-#define DDF5 5 +-#define DDF4 4 +-#define DDF3 3 +-#define DDF2 2 +-#define DDF1 1 +-#define DDF0 0 +- +-#define PORTF _SFR_IO8(0x11) +-#define PF7 7 +-#define PF6 6 +-#define PF5 5 +-#define PF4 4 +-#define PF3 3 +-#define PF2 2 +-#define PF1 1 +-#define PF0 0 +- +-#define PING _SFR_IO8(0x12) +-#define PING4 4 +-#define PING3 3 +-#define PING2 2 +-#define PING1 1 +-#define PING0 0 +- +-#define DDRG _SFR_IO8(0x13) +-#define DDG4 4 +-#define DDG3 3 +-#define DDG2 2 +-#define DDG1 1 +-#define DDG0 0 +- +-#define PORTG _SFR_IO8(0x14) +-#define PG4 4 +-#define PG3 3 +-#define PG2 2 +-#define PG1 1 +-#define PG0 0 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define TIFR2 _SFR_IO8(0x17) +-#define TOV2 0 +-#define OCF2A 1 +- +-/* Reserved [0x18..0x1B] */ +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define PCIF0 6 +-#define PCIF1 7 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define PCIE0 6 +-#define PCIE1 7 +- +-#define GPIOR0 _SFR_IO8(0x1E) +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEWE 1 +-#define EEMWE 2 +-#define EERIE 3 +- +-#define EEDR _SFR_IO8(0X20) +- +-/* Combine EEARL and EEARH */ +-#define EEAR _SFR_IO16(0x21) +-#define EEARL _SFR_IO8(0x21) +-#define EEARH _SFR_IO8(0X22) +- +-/* 6-char sequence denoting where to find the EEPROM registers in memory space. +- Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM +- subroutines. +- First two letters: EECR address. +- Second two letters: EEDR address. +- Last two letters: EEAR address. */ +-#define __EEPROM_REG_LOCATIONS__ 1F2021 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSR10 0 +-#define PSR2 1 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM01 3 +-#define COM0A0 4 +-#define COM0A1 5 +-#define WGM00 6 +-#define FOC0A 7 +- +-/* Reserved [0x25] */ +- +-#define TCNT0 _SFR_IO8(0X26) +- +-#define OCR0A _SFR_IO8(0X27) +- +-/* Reserved [0x28..0x29] */ +- +-#define GPIOR1 _SFR_IO8(0x2A) +- +-#define GPIOR2 _SFR_IO8(0x2B) +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0X2E) +- +-/* Reserved [0x2F] */ +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define OCDR _SFR_IO8(0x31) +-#define OCDR0 0 +-#define OCDR1 1 +-#define OCDR2 2 +-#define OCDR3 3 +-#define OCDR4 4 +-#define OCDR5 5 +-#define OCDR6 6 +-#define OCD 7 // The datasheet defines this but IMO it should be OCDR7. +-#define OCDR7 7 +-#define IDRD 7 +- +-/* Reserved [0x32] */ +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +-#define JTRF 4 +- +-#define MCUCR _SFR_IO8(0X35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define JTD 7 +- +-/* Reserved [0x36] */ +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define RWWSB 6 +-#define SPMIE 7 +- +-/* Reserved [0x38..0x3C] */ +- +-/* SP [0x3D..0x3E] */ +-/* SREG [0x3F] */ +- +-#define WDTCR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-/* Reserved [0x62..0x63] */ +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM1 3 +- +-/* Reserved [0x65] */ +- +-#define OSCCAL _SFR_MEM8(0x66) +- +-/* Reserved [0x67..0x68] */ +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +- +-/* Reserved [0x6A] */ +- +-/* Combine PCMSK0 and PCMSK1 */ +-#define PCMSK _SFR_MEM16(0x6B) +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-/* Reserved [0x6D] */ +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define TIMSK2 _SFR_MEM8(0x70) +-#define TOIE2 0 +-#define OCIE2A 1 +- +-/* Reserved [0x71..0x77] */ +- +-/* Combine ADCL and ADCH */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +-#define ADCL _SFR_MEM8(0x78) +-#define ADCH _SFR_MEM8(0x79) +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ACME 6 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-/* Reserved [0x7D] */ +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0X80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0X81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-/* Reserved [0x83] */ +- +-/* Combine TCNT1L and TCNT1H */ +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1H _SFR_MEM8(0x85) +- +-/* Combine ICR1L and ICR1H */ +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1H _SFR_MEM8(0x87) +- +-/* Combine OCR1AL and OCR1AH */ +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AH _SFR_MEM8(0x89) +- +-/* Combine OCR1BL and OCR1BH */ +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BH _SFR_MEM8(0x8B) +- +-/* Reserved [0x8C..0xAF] */ +- +-#define TCCR2A _SFR_MEM8(0xB0) +-#define CS20 0 +-#define CS21 1 +-#define CS22 2 +-#define WGM21 3 +-#define COM2A0 4 +-#define COM2A1 5 +-#define WGM20 6 +-#define FOC2A 7 +- +-/* Reserved [0xB1] */ +- +-#define TCNT2 _SFR_MEM8(0xB2) +- +-#define OCR2A _SFR_MEM8(0xB3) +- +-/* Reserved [0xB4..0xB5] */ +- +-#define ASSR _SFR_MEM8(0xB6) +-#define TCR2UB 0 +-#define OCR2UB 1 +-#define TCN2UB 2 +-#define AS2 3 +-#define EXCLK 4 +- +-/* Reserved [0xB7] */ +- +-#define USICR _SFR_MEM8(0xB8) +-#define USITC 0 +-#define USICLK 1 +-#define USICS0 2 +-#define USICS1 3 +-#define USIWM0 4 +-#define USIWM1 5 +-#define USIOIE 6 +-#define USISIE 7 +- +-#define USISR _SFR_MEM8(0xB9) +-#define USICNT0 0 +-#define USICNT1 1 +-#define USICNT2 2 +-#define USICNT3 3 +-#define USIDC 4 +-#define USIPF 5 +-#define USIOIF 6 +-#define USISIF 7 +- +-#define USIDR _SFR_MEM8(0xBA) +- +-/* Reserved [0xBB..0xBF] */ +- +-#define UCSRA _SFR_MEM8(0xC0) +-#define MPCM 0 +-#define U2X 1 +-#define UPE 2 +-#define DOR 3 +-#define FE 4 +-#define UDRE 5 +-#define TXC 6 +-#define RXC 7 +- +-#define UCSRB _SFR_MEM8(0XC1) +-#define TXB8 0 +-#define RXB8 1 +-#define UCSZ2 2 +-#define TXEN 3 +-#define RXEN 4 +-#define UDRIE 5 +-#define TXCIE 6 +-#define RXCIE 7 +- +-#define UCSRC _SFR_MEM8(0xC2) +-#define UCPOL 0 +-#define UCSZ0 1 +-#define UCSZ1 2 +-#define USBS 3 +-#define UPM0 4 +-#define UPM1 5 +-#define UMSEL 6 +- +-/* Reserved [0xC3] */ +- +-/* Combine UBRRL and UBRRH */ +-#define UBRR _SFR_MEM16(0xC4) +- +-#define UBRRL _SFR_MEM8(0xC4) +-#define UBRRH _SFR_MEM8(0xC5) +- +-#define UDR _SFR_MEM8(0XC6) +- +-/* Reserved [0xC7..0xFF] */ +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* Pin Change Interrupt Request 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) +-#define SIG_PIN_CHANGE0 _VECTOR(2) +- +-/* Pin Change Interrupt Request 1 */ +-#define PCINT1_vect_num 3 +-#define PCINT1_vect _VECTOR(3) +-#define SIG_PIN_CHANGE1 _VECTOR(3) +- +-/* Timer/Counter2 Compare Match */ +-#define TIMER2_COMP_vect_num 4 +-#define TIMER2_COMP_vect _VECTOR(4) +-#define SIG_OUTPUT_COMPARE2 _VECTOR(4) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 5 +-#define TIMER2_OVF_vect _VECTOR(5) +-#define SIG_OVERFLOW2 _VECTOR(5) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 6 +-#define TIMER1_CAPT_vect _VECTOR(6) +-#define SIG_INPUT_CAPTURE1 _VECTOR(6) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 7 +-#define TIMER1_COMPA_vect _VECTOR(7) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(7) +- +-/* Timer/Counter Compare Match B */ +-#define TIMER1_COMPB_vect_num 8 +-#define TIMER1_COMPB_vect _VECTOR(8) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(8) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 9 +-#define TIMER1_OVF_vect _VECTOR(9) +-#define SIG_OVERFLOW1 _VECTOR(9) +- +-/* Timer/Counter0 Compare Match */ +-#define TIMER0_COMP_vect_num 10 +-#define TIMER0_COMP_vect _VECTOR(10) +-#define SIG_OUTPUT_COMPARE0 _VECTOR(10) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 11 +-#define TIMER0_OVF_vect _VECTOR(11) +-#define SIG_OVERFLOW0 _VECTOR(11) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 12 +-#define SPI_STC_vect _VECTOR(12) +-#define SIG_SPI _VECTOR(12) +- +-/* USART0, Rx Complete */ +-#define USART0_RX_vect_num 13 +-#define USART0_RX_vect _VECTOR(13) +-#define USART_RX_vect _VECTOR(13) /* Alias */ +-#define SIG_UART_RECV _VECTOR(13) +- +-/* USART0 Data register Empty */ +-#define USART0_UDRE_vect_num 14 +-#define USART0_UDRE_vect _VECTOR(14) +-#define USART_UDRE_vect _VECTOR(14) /* Alias */ +-#define SIG_UART_DATA _VECTOR(14) +- +-/* USART0, Tx Complete */ +-#define USART0_TX_vect_num 15 +-#define USART0_TX_vect _VECTOR(15) +-#define USART_TX_vect _VECTOR(15) /* Alias */ +-#define SIG_UART_TRANS _VECTOR(15) +- +-/* USI Start Condition */ +-#define USI_START_vect_num 16 +-#define USI_START_vect _VECTOR(16) +-#define SIG_USI_START _VECTOR(16) +- +-/* USI Overflow */ +-#define USI_OVERFLOW_vect_num 17 +-#define USI_OVERFLOW_vect _VECTOR(17) +-#define SIG_USI_OVERFLOW _VECTOR(17) +- +-/* Analog Comparator */ +-#define ANALOG_COMP_vect_num 18 +-#define ANALOG_COMP_vect _VECTOR(18) +-#define SIG_COMPARATOR _VECTOR(18) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 19 +-#define ADC_vect _VECTOR(19) +-#define SIG_ADC _VECTOR(19) +- +-/* EEPROM Ready */ +-#define EE_READY_vect_num 20 +-#define EE_READY_vect _VECTOR(20) +-#define SIG_EEPROM_READY _VECTOR(20) +- +-/* Store Program Memory Read */ +-#define SPM_READY_vect_num 21 +-#define SPM_READY_vect _VECTOR(21) +-#define SIG_SPM_READY _VECTOR(21) +- +-#define _VECTORS_SIZE 88 +- +- +-/* Constants */ +-#define SPM_PAGESIZE 128 +-#define RAMEND 0x4FF +-#define XRAMEND RAMEND +-#define E2END 0x1FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x3FFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x94 +-#define SIGNATURE_2 0x07 +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_PIN_CHANGE0 +-#pragma GCC poison SIG_PIN_CHANGE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE2 +-#pragma GCC poison SIG_OVERFLOW2 +-#pragma GCC poison SIG_INPUT_CAPTURE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OUTPUT_COMPARE0 +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_SPI +-#pragma GCC poison USART_RX_vect +-#pragma GCC poison SIG_UART_RECV +-#pragma GCC poison USART_UDRE_vect +-#pragma GCC poison SIG_UART_DATA +-#pragma GCC poison USART_TX_vect +-#pragma GCC poison SIG_UART_TRANS +-#pragma GCC poison SIG_USI_START +-#pragma GCC poison SIG_USI_OVERFLOW +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_ADC +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_SPM_READY +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +-#endif /* _AVR_IOM165_H_ */ ++/* Copyright (c) 2004,2005,2006 Eric B. Weddington ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom165.h 2231 2011-03-07 05:06:55Z arcanum $ */ ++ ++/* avr/iom165.h - definitions for ATmega165 */ ++ ++#ifndef _AVR_IOM165_H_ ++#define _AVR_IOM165_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom165.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE7 7 ++#define DDE6 6 ++#define DDE5 5 ++#define DDE4 4 ++#define DDE3 3 ++#define DDE2 2 ++#define DDE1 1 ++#define DDE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PE7 7 ++#define PE6 6 ++#define PE5 5 ++#define PE4 4 ++#define PE3 3 ++#define PE2 2 ++#define PE1 1 ++#define PE0 0 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDF7 7 ++#define DDF6 6 ++#define DDF5 5 ++#define DDF4 4 ++#define DDF3 3 ++#define DDF2 2 ++#define DDF1 1 ++#define DDF0 0 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PF7 7 ++#define PF6 6 ++#define PF5 5 ++#define PF4 4 ++#define PF3 3 ++#define PF2 2 ++#define PF1 1 ++#define PF0 0 ++ ++#define PING _SFR_IO8(0x12) ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++#define DDRG _SFR_IO8(0x13) ++#define DDG4 4 ++#define DDG3 3 ++#define DDG2 2 ++#define DDG1 1 ++#define DDG0 0 ++ ++#define PORTG _SFR_IO8(0x14) ++#define PG4 4 ++#define PG3 3 ++#define PG2 2 ++#define PG1 1 ++#define PG0 0 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++ ++/* Reserved [0x18..0x1B] */ ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define PCIF0 6 ++#define PCIF1 7 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define PCIE0 6 ++#define PCIE1 7 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++ ++#define EEDR _SFR_IO8(0X20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0X22) ++ ++/* 6-char sequence denoting where to find the EEPROM registers in memory space. ++ Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM ++ subroutines. ++ First two letters: EECR address. ++ Second two letters: EEDR address. ++ Last two letters: EEAR address. */ ++#define __EEPROM_REG_LOCATIONS__ 1F2021 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR10 0 ++#define PSR2 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM01 3 ++#define COM0A0 4 ++#define COM0A1 5 ++#define WGM00 6 ++#define FOC0A 7 ++ ++/* Reserved [0x25] */ ++ ++#define TCNT0 _SFR_IO8(0X26) ++ ++#define OCR0A _SFR_IO8(0X27) ++ ++/* Reserved [0x28..0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0X2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCD 7 // The datasheet defines this but IMO it should be OCDR7. ++#define OCDR7 7 ++#define IDRD 7 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define JTRF 4 ++ ++#define MCUCR _SFR_IO8(0X35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define JTD 7 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++/* SREG [0x3F] */ ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++ ++/* Reserved [0x67..0x68] */ ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++ ++/* Reserved [0x6A] */ ++ ++/* Combine PCMSK0 and PCMSK1 */ ++#define PCMSK _SFR_MEM16(0x6B) ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++/* Reserved [0x6D] */ ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++ ++/* Reserved [0x71..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0X80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0X81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM21 3 ++#define COM2A0 4 ++#define COM2A1 5 ++#define WGM20 6 ++#define FOC2A 7 ++ ++/* Reserved [0xB1] */ ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++/* Reserved [0xB4..0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2UB 0 ++#define OCR2UB 1 ++#define TCN2UB 2 ++#define AS2 3 ++#define EXCLK 4 ++ ++/* Reserved [0xB7] */ ++ ++#define USICR _SFR_MEM8(0xB8) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_MEM8(0xB9) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_MEM8(0xBA) ++ ++/* Reserved [0xBB..0xBF] */ ++ ++#define UCSRA _SFR_MEM8(0xC0) ++#define MPCM 0 ++#define U2X 1 ++#define UPE 2 ++#define DOR 3 ++#define FE 4 ++#define UDRE 5 ++#define TXC 6 ++#define RXC 7 ++ ++#define UCSRB _SFR_MEM8(0XC1) ++#define TXB8 0 ++#define RXB8 1 ++#define UCSZ2 2 ++#define TXEN 3 ++#define RXEN 4 ++#define UDRIE 5 ++#define TXCIE 6 ++#define RXCIE 7 ++ ++#define UCSRC _SFR_MEM8(0xC2) ++#define UCPOL 0 ++#define UCSZ0 1 ++#define UCSZ1 2 ++#define USBS 3 ++#define UPM0 4 ++#define UPM1 5 ++#define UMSEL 6 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRRL and UBRRH */ ++#define UBRR _SFR_MEM16(0xC4) ++ ++#define UBRRL _SFR_MEM8(0xC4) ++#define UBRRH _SFR_MEM8(0xC5) ++ ++#define UDR _SFR_MEM8(0XC6) ++ ++/* Reserved [0xC7..0xFF] */ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) ++#define SIG_PIN_CHANGE0 _VECTOR(2) ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect_num 3 ++#define PCINT1_vect _VECTOR(3) ++#define SIG_PIN_CHANGE1 _VECTOR(3) ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect_num 4 ++#define TIMER2_COMP_vect _VECTOR(4) ++#define SIG_OUTPUT_COMPARE2 _VECTOR(4) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 5 ++#define TIMER2_OVF_vect _VECTOR(5) ++#define SIG_OVERFLOW2 _VECTOR(5) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 6 ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define SIG_INPUT_CAPTURE1 _VECTOR(6) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 7 ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(7) ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect_num 8 ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(8) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 9 ++#define TIMER1_OVF_vect _VECTOR(9) ++#define SIG_OVERFLOW1 _VECTOR(9) ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect_num 10 ++#define TIMER0_COMP_vect _VECTOR(10) ++#define SIG_OUTPUT_COMPARE0 _VECTOR(10) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 11 ++#define TIMER0_OVF_vect _VECTOR(11) ++#define SIG_OVERFLOW0 _VECTOR(11) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 12 ++#define SPI_STC_vect _VECTOR(12) ++#define SIG_SPI _VECTOR(12) ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect_num 13 ++#define USART0_RX_vect _VECTOR(13) ++#define USART_RX_vect _VECTOR(13) /* Alias */ ++#define SIG_UART_RECV _VECTOR(13) ++ ++/* USART0 Data register Empty */ ++#define USART0_UDRE_vect_num 14 ++#define USART0_UDRE_vect _VECTOR(14) ++#define USART_UDRE_vect _VECTOR(14) /* Alias */ ++#define SIG_UART_DATA _VECTOR(14) ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect_num 15 ++#define USART0_TX_vect _VECTOR(15) ++#define USART_TX_vect _VECTOR(15) /* Alias */ ++#define SIG_UART_TRANS _VECTOR(15) ++ ++/* USI Start Condition */ ++#define USI_START_vect_num 16 ++#define USI_START_vect _VECTOR(16) ++#define SIG_USI_START _VECTOR(16) ++ ++/* USI Overflow */ ++#define USI_OVERFLOW_vect_num 17 ++#define USI_OVERFLOW_vect _VECTOR(17) ++#define SIG_USI_OVERFLOW _VECTOR(17) ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect_num 18 ++#define ANALOG_COMP_vect _VECTOR(18) ++#define SIG_COMPARATOR _VECTOR(18) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 19 ++#define ADC_vect _VECTOR(19) ++#define SIG_ADC _VECTOR(19) ++ ++/* EEPROM Ready */ ++#define EE_READY_vect_num 20 ++#define EE_READY_vect _VECTOR(20) ++#define SIG_EEPROM_READY _VECTOR(20) ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect_num 21 ++#define SPM_READY_vect _VECTOR(21) ++#define SIG_SPM_READY _VECTOR(21) ++ ++#define _VECTORS_SIZE 88 ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE 128 ++#define RAMSTART 0x100 ++#define RAMEND 0x4FF ++#define XRAMEND RAMEND ++#define E2END 0x1FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x3FFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x05 ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_PIN_CHANGE0 ++#pragma GCC poison SIG_PIN_CHANGE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE2 ++#pragma GCC poison SIG_OVERFLOW2 ++#pragma GCC poison SIG_INPUT_CAPTURE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OUTPUT_COMPARE0 ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_SPI ++#pragma GCC poison USART_RX_vect ++#pragma GCC poison SIG_UART_RECV ++#pragma GCC poison USART_UDRE_vect ++#pragma GCC poison SIG_UART_DATA ++#pragma GCC poison USART_TX_vect ++#pragma GCC poison SIG_UART_TRANS ++#pragma GCC poison SIG_USI_START ++#pragma GCC poison SIG_USI_OVERFLOW ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_ADC ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_SPM_READY ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++#endif /* _AVR_IOM165_H_ */ +diff --git a/include/avr/iom165a.h b/include/avr/iom165a.h +new file mode 100644 +index 0000000..6a62ad6 +--- /dev/null ++++ b/include/avr/iom165a.h +@@ -0,0 +1,823 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++/* $Id: iom165a.h 2442 2014-08-11 21:42:11Z joerg_wunsch $ */ ++ ++#ifndef _AVR_ATMEGA165A_H_INCLUDED ++#define _AVR_ATMEGA165A_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom165a.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDRA7 7 ++#define DDRA6 6 ++#define DDRA5 5 ++#define DDRA4 4 ++#define DDRA3 3 ++#define DDRA2 2 ++#define DDRA1 1 ++#define DDRA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDRC7 7 ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC7 7 ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDRE7 7 ++#define DDRE6 6 ++#define DDRE5 5 ++#define DDRE4 4 ++#define DDRE3 3 ++#define DDRE2 2 ++#define DDRE1 1 ++#define DDRE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE7 7 ++#define PORTE6 6 ++#define PORTE5 5 ++#define PORTE4 4 ++#define PORTE3 3 ++#define PORTE2 2 ++#define PORTE1 1 ++#define PORTE0 0 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDRF7 7 ++#define DDRF6 6 ++#define DDRF5 5 ++#define DDRF4 4 ++#define DDRF3 3 ++#define DDRF2 2 ++#define DDRF1 1 ++#define DDRF0 0 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PORTF7 7 ++#define PORTF6 6 ++#define PORTF5 5 ++#define PORTF4 4 ++#define PORTF3 3 ++#define PORTF2 2 ++#define PORTF1 1 ++#define PORTF0 0 ++ ++#define PING _SFR_IO8(0x12) ++#define PING5 5 ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++#define DDRG _SFR_IO8(0x13) ++#define DDRG4 4 ++#define DDRG3 3 ++#define DDRG2 2 ++#define DDRG1 1 ++#define DDRG0 0 ++ ++#define PORTG _SFR_IO8(0x14) ++#define PORTG4 4 ++#define PORTG3 3 ++#define PORTG2 2 ++#define PORTG1 1 ++#define PORTG0 0 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++ ++/* Reserved [0x18..0x1B] */ ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define PCIF0 4 ++#define PCIF1 5 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define PCIE0 4 ++#define PCIE1 5 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR310 0 ++#define TSM 7 ++#define PSR2 1 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM01 3 ++#define COM0A0 4 ++#define COM0A1 5 ++#define WGM00 6 ++#define FOC0A 7 ++ ++/* Reserved [0x25] */ ++ ++#define TCNT0 _SFR_IO8(0x26) ++ ++#define OCR0A _SFR_IO8(0x27) ++ ++/* Reserved [0x28..0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR7 7 ++#define OCDR6 6 ++#define OCDR5 5 ++#define OCDR4 4 ++#define OCDR3 3 ++#define OCDR2 2 ++#define OCDR1 1 ++#define OCDR0 0 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define JTRF 4 ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define JTD 7 ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++/* Reserved [0x67..0x68] */ ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++/* Reserved [0x6D] */ ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++ ++/* Reserved [0x71..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ACME 6 ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM21 3 ++#define COM2A0 4 ++#define COM2A1 5 ++#define WGM20 6 ++#define FOC2A 7 ++ ++/* Reserved [0xB1] */ ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++/* Reserved [0xB4..0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2UB 0 ++#define OCR2UB 1 ++#define TCN2UB 2 ++#define AS2 3 ++#define EXCLK 4 ++ ++/* Reserved [0xB7] */ ++ ++#define USICR _SFR_MEM8(0xB8) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_MEM8(0xB9) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_MEM8(0xBA) ++ ++/* Reserved [0xBB..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL0 6 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0xC6) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(2) ++#define PCINT0_vect_num 2 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(3) ++#define PCINT1_vect_num 3 ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect _VECTOR(4) ++#define TIMER2_COMP_vect_num 4 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(5) ++#define TIMER2_OVF_vect_num 5 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define TIMER1_CAPT_vect_num 6 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define TIMER1_COMPA_vect_num 7 ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define TIMER1_COMPB_vect_num 8 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(9) ++#define TIMER1_OVF_vect_num 9 ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect _VECTOR(10) ++#define TIMER0_COMP_vect_num 10 ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(11) ++#define TIMER0_OVF_vect_num 11 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(12) ++#define SPI_STC_vect_num 12 ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect _VECTOR(13) ++#define USART0_RX_vect_num 13 ++ ++/* USART0 Data register Empty */ ++#define USART0_UDRE_vect _VECTOR(14) ++#define USART0_UDRE_vect_num 14 ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect _VECTOR(15) ++#define USART0_TX_vect_num 15 ++ ++/* USI Start Condition */ ++#define USI_START_vect _VECTOR(16) ++#define USI_START_vect_num 16 ++ ++/* USI Overflow */ ++#define USI_OVERFLOW_vect _VECTOR(17) ++#define USI_OVERFLOW_vect_num 17 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(18) ++#define ANALOG_COMP_vect_num 18 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(19) ++#define ADC_vect_num 19 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(20) ++#define EE_READY_vect_num 20 ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect _VECTOR(21) ++#define SPM_READY_vect_num 21 ++ ++#define _VECTORS_SIZE 88 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 128 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x3FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 1024 ++#define RAMEND 0x04FF ++#define E2START 0 ++#define E2SIZE 512 ++#define E2PAGESIZE 4 ++#define E2END 0x01FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x10 ++ ++ ++#endif /* #ifdef _AVR_ATMEGA165A_H_INCLUDED */ ++ +diff --git a/include/avr/iom165p.h b/include/avr/iom165p.h +index b9ea6e5..2b74e0d 100644 +--- a/include/avr/iom165p.h ++++ b/include/avr/iom165p.h +@@ -1,877 +1,878 @@ +-/* Copyright (c) 2004,2005,2006 Eric B. Weddington +- Copyright (c) 2006 Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom165p.h 2231 2011-03-07 05:06:55Z arcanum $ */ +- +-/* avr/iom165p.h - definitions for ATmega165P */ +- +-#ifndef _AVR_IOM165P_H_ +-#define _AVR_IOM165P_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom165p.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* Registers and associated bit numbers */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-#define PORTA _SFR_IO8(0x02) +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-#define PINB _SFR_IO8(0x03) +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-#define PORTB _SFR_IO8(0x05) +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-#define PORTC _SFR_IO8(0x08) +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-#define PINE _SFR_IO8(0x0C) +-#define PINE7 7 +-#define PINE6 6 +-#define PINE5 5 +-#define PINE4 4 +-#define PINE3 3 +-#define PINE2 2 +-#define PINE1 1 +-#define PINE0 0 +- +-#define DDRE _SFR_IO8(0x0D) +-#define DDE7 7 +-#define DDE6 6 +-#define DDE5 5 +-#define DDE4 4 +-#define DDE3 3 +-#define DDE2 2 +-#define DDE1 1 +-#define DDE0 0 +- +-#define PORTE _SFR_IO8(0x0E) +-#define PE7 7 +-#define PE6 6 +-#define PE5 5 +-#define PE4 4 +-#define PE3 3 +-#define PE2 2 +-#define PE1 1 +-#define PE0 0 +- +-#define PINF _SFR_IO8(0x0F) +-#define PINF7 7 +-#define PINF6 6 +-#define PINF5 5 +-#define PINF4 4 +-#define PINF3 3 +-#define PINF2 2 +-#define PINF1 1 +-#define PINF0 0 +- +-#define DDRF _SFR_IO8(0x10) +-#define DDF7 7 +-#define DDF6 6 +-#define DDF5 5 +-#define DDF4 4 +-#define DDF3 3 +-#define DDF2 2 +-#define DDF1 1 +-#define DDF0 0 +- +-#define PORTF _SFR_IO8(0x11) +-#define PF7 7 +-#define PF6 6 +-#define PF5 5 +-#define PF4 4 +-#define PF3 3 +-#define PF2 2 +-#define PF1 1 +-#define PF0 0 +- +-#define PING _SFR_IO8(0x12) +-#define PING5 5 +-#define PING4 4 +-#define PING3 3 +-#define PING2 2 +-#define PING1 1 +-#define PING0 0 +- +-#define DDRG _SFR_IO8(0x13) +-#define DDG4 4 +-#define DDG3 3 +-#define DDG2 2 +-#define DDG1 1 +-#define DDG0 0 +- +-#define PORTG _SFR_IO8(0x14) +-#define PG4 4 +-#define PG3 3 +-#define PG2 2 +-#define PG1 1 +-#define PG0 0 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define TIFR2 _SFR_IO8(0x17) +-#define TOV2 0 +-#define OCF2A 1 +- +-/* Reserved [0x18..0x1B] */ +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define PCIF0 6 +-#define PCIF1 7 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define PCIE0 6 +-#define PCIE1 7 +- +-#define GPIOR0 _SFR_IO8(0x1E) +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEWE 1 +-#define EEMWE 2 +-#define EERIE 3 +- +-#define EEDR _SFR_IO8(0X20) +- +-/* Combine EEARL and EEARH */ +-#define EEAR _SFR_IO16(0x21) +-#define EEARL _SFR_IO8(0x21) +-#define EEARH _SFR_IO8(0X22) +- +-/* 6-char sequence denoting where to find the EEPROM registers in memory space. +- Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM +- subroutines. +- First two letters: EECR address. +- Second two letters: EEDR address. +- Last two letters: EEAR address. */ +-#define __EEPROM_REG_LOCATIONS__ 1F2021 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSR10 0 +-#define PSR2 1 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM01 3 +-#define COM0A0 4 +-#define COM0A1 5 +-#define WGM00 6 +-#define FOC0A 7 +- +-/* Reserved [0x25] */ +- +-#define TCNT0 _SFR_IO8(0X26) +- +-#define OCR0A _SFR_IO8(0X27) +- +-/* Reserved [0x28..0x29] */ +- +-#define GPIOR1 _SFR_IO8(0x2A) +- +-#define GPIOR2 _SFR_IO8(0x2B) +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0X2E) +- +-/* Reserved [0x2F] */ +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define OCDR _SFR_IO8(0x31) +-#define OCDR0 0 +-#define OCDR1 1 +-#define OCDR2 2 +-#define OCDR3 3 +-#define OCDR4 4 +-#define OCDR5 5 +-#define OCDR6 6 +-#define OCD 7 // The datasheet defines this but IMO it should be OCDR7. +-#define OCDR7 7 +-#define IDRD 7 +- +-/* Reserved [0x32] */ +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +-#define JTRF 4 +- +-#define MCUCR _SFR_IO8(0X35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define JTD 7 +- +-/* Reserved [0x36] */ +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define RWWSB 6 +-#define SPMIE 7 +- +-/* Reserved [0x38..0x3C] */ +- +-/* SP [0x3D..0x3E] */ +-/* SREG [0x3F] */ +- +-#define WDTCR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-/* Reserved [0x62..0x63] */ +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM1 3 +- +-/* Reserved [0x65] */ +- +-#define OSCCAL _SFR_MEM8(0x66) +- +-/* Reserved [0x67..0x68] */ +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +- +-/* Reserved [0x6A] */ +- +-/* Combine PCMSK0 and PCMSK1 */ +-#define PCMSK _SFR_MEM16(0x6B) +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-/* Reserved [0x6D] */ +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define TIMSK2 _SFR_MEM8(0x70) +-#define TOIE2 0 +-#define OCIE2A 1 +- +-/* Reserved [0x71..0x77] */ +- +-/* Combine ADCL and ADCH */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +-#define ADCL _SFR_MEM8(0x78) +-#define ADCH _SFR_MEM8(0x79) +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ACME 6 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-/* Reserved [0x7D] */ +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0X80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0X81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-/* Reserved [0x83] */ +- +-/* Combine TCNT1L and TCNT1H */ +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1H _SFR_MEM8(0x85) +- +-/* Combine ICR1L and ICR1H */ +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1H _SFR_MEM8(0x87) +- +-/* Combine OCR1AL and OCR1AH */ +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AH _SFR_MEM8(0x89) +- +-/* Combine OCR1BL and OCR1BH */ +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BH _SFR_MEM8(0x8B) +- +-/* Reserved [0x8C..0xAF] */ +- +-#define TCCR2A _SFR_MEM8(0xB0) +-#define CS20 0 +-#define CS21 1 +-#define CS22 2 +-#define WGM21 3 +-#define COM2A0 4 +-#define COM2A1 5 +-#define WGM20 6 +-#define FOC2A 7 +- +-/* Reserved [0xB1] */ +- +-#define TCNT2 _SFR_MEM8(0xB2) +- +-#define OCR2A _SFR_MEM8(0xB3) +- +-/* Reserved [0xB4..0xB5] */ +- +-#define ASSR _SFR_MEM8(0xB6) +-#define TCR2UB 0 +-#define OCR2UB 1 +-#define TCN2UB 2 +-#define AS2 3 +-#define EXCLK 4 +- +-/* Reserved [0xB7] */ +- +-#define USICR _SFR_MEM8(0xB8) +-#define USITC 0 +-#define USICLK 1 +-#define USICS0 2 +-#define USICS1 3 +-#define USIWM0 4 +-#define USIWM1 5 +-#define USIOIE 6 +-#define USISIE 7 +- +-#define USISR _SFR_MEM8(0xB9) +-#define USICNT0 0 +-#define USICNT1 1 +-#define USICNT2 2 +-#define USICNT3 3 +-#define USIDC 4 +-#define USIPF 5 +-#define USIOIF 6 +-#define USISIF 7 +- +-#define USIDR _SFR_MEM8(0xBA) +- +-/* Reserved [0xBB..0xBF] */ +- +-#define UCSR0A _SFR_MEM8(0xC0) +-#define MPCM0 0 +-#define U2X0 1 +-#define UPE0 2 +-#define DOR0 3 +-#define FE0 4 +-#define UDRE0 5 +-#define TXC0 6 +-#define RXC0 7 +- +-#define UCSR0B _SFR_MEM8(0XC1) +-#define TXB80 0 +-#define RXB80 1 +-#define UCSZ02 2 +-#define TXEN0 3 +-#define RXEN0 4 +-#define UDRIE0 5 +-#define TXCIE0 6 +-#define RXCIE0 7 +- +-#define UCSR0C _SFR_MEM8(0xC2) +-#define UCPOL0 0 +-#define UCSZ00 1 +-#define UCSZ01 2 +-#define USBS0 3 +-#define UPM00 4 +-#define UPM01 5 +-#define UMSEL0 6 +- +-/* Reserved [0xC3] */ +- +-/* Combine UBRRL and UBRRH */ +-#define UBRR0 _SFR_MEM16(0xC4) +- +-#define UBRR0L _SFR_MEM8(0xC4) +-#define UBRR0H _SFR_MEM8(0xC5) +- +-#define UDR0 _SFR_MEM8(0XC6) +- +-/* Reserved [0xC7..0xFF] */ +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* Pin Change Interrupt Request 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) +-#define SIG_PIN_CHANGE0 _VECTOR(2) +- +-/* Pin Change Interrupt Request 1 */ +-#define PCINT1_vect_num 3 +-#define PCINT1_vect _VECTOR(3) +-#define SIG_PIN_CHANGE1 _VECTOR(3) +- +-/* Timer/Counter2 Compare Match */ +-#define TIMER2_COMP_vect_num 4 +-#define TIMER2_COMP_vect _VECTOR(4) +-#define SIG_OUTPUT_COMPARE2 _VECTOR(4) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 5 +-#define TIMER2_OVF_vect _VECTOR(5) +-#define SIG_OVERFLOW2 _VECTOR(5) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 6 +-#define TIMER1_CAPT_vect _VECTOR(6) +-#define SIG_INPUT_CAPTURE1 _VECTOR(6) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 7 +-#define TIMER1_COMPA_vect _VECTOR(7) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(7) +- +-/* Timer/Counter Compare Match B */ +-#define TIMER1_COMPB_vect_num 8 +-#define TIMER1_COMPB_vect _VECTOR(8) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(8) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 9 +-#define TIMER1_OVF_vect _VECTOR(9) +-#define SIG_OVERFLOW1 _VECTOR(9) +- +-/* Timer/Counter0 Compare Match */ +-#define TIMER0_COMP_vect_num 10 +-#define TIMER0_COMP_vect _VECTOR(10) +-#define SIG_OUTPUT_COMPARE0 _VECTOR(10) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 11 +-#define TIMER0_OVF_vect _VECTOR(11) +-#define SIG_OVERFLOW0 _VECTOR(11) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 12 +-#define SPI_STC_vect _VECTOR(12) +-#define SIG_SPI _VECTOR(12) +- +-/* USART0, Rx Complete */ +-#define USART0_RX_vect_num 13 +-#define USART0_RX_vect _VECTOR(13) +-#define USART_RX_vect _VECTOR(13) /* Alias */ +-#define SIG_UART_RECV _VECTOR(13) +- +-/* USART0 Data register Empty */ +-#define USART0_UDRE_vect_num 14 +-#define USART0_UDRE_vect _VECTOR(14) +-#define USART_UDRE_vect _VECTOR(14) /* Alias */ +-#define SIG_UART_DATA _VECTOR(14) +- +-/* USART0, Tx Complete */ +-#define USART0_TX_vect_num 15 +-#define USART0_TX_vect _VECTOR(15) +-#define USART_TX_vect _VECTOR(15) /* Alias */ +-#define SIG_UART_TRANS _VECTOR(15) +- +-/* USI Start Condition */ +-#define USI_START_vect_num 16 +-#define USI_START_vect _VECTOR(16) +-#define SIG_USI_START _VECTOR(16) +- +-/* USI Overflow */ +-#define USI_OVERFLOW_vect_num 17 +-#define USI_OVERFLOW_vect _VECTOR(17) +-#define SIG_USI_OVERFLOW _VECTOR(17) +- +-/* Analog Comparator */ +-#define ANALOG_COMP_vect_num 18 +-#define ANALOG_COMP_vect _VECTOR(18) +-#define SIG_COMPARATOR _VECTOR(18) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 19 +-#define ADC_vect _VECTOR(19) +-#define SIG_ADC _VECTOR(19) +- +-/* EEPROM Ready */ +-#define EE_READY_vect_num 20 +-#define EE_READY_vect _VECTOR(20) +-#define SIG_EEPROM_READY _VECTOR(20) +- +-/* Store Program Memory Read */ +-#define SPM_READY_vect_num 21 +-#define SPM_READY_vect _VECTOR(21) +-#define SIG_SPM_READY _VECTOR(21) +- +-#define _VECTORS_SIZE 88 +- +- +-/* Constants */ +-#define SPM_PAGESIZE 128 +-#define RAMEND 0x4FF +-#define XRAMEND RAMEND +-#define E2END 0x1FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x3FFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x94 +-#define SIGNATURE_2 0x07 +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_PIN_CHANGE0 +-#pragma GCC poison SIG_PIN_CHANGE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE2 +-#pragma GCC poison SIG_OVERFLOW2 +-#pragma GCC poison SIG_INPUT_CAPTURE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OUTPUT_COMPARE0 +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_SPI +-#pragma GCC poison USART_RX_vect +-#pragma GCC poison SIG_UART_RECV +-#pragma GCC poison USART_UDRE_vect +-#pragma GCC poison SIG_UART_DATA +-#pragma GCC poison USART_TX_vect +-#pragma GCC poison SIG_UART_TRANS +-#pragma GCC poison SIG_USI_START +-#pragma GCC poison SIG_USI_OVERFLOW +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_ADC +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_SPM_READY +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +-#endif /* _AVR_IOM165P_H_ */ ++/* Copyright (c) 2004,2005,2006 Eric B. Weddington ++ Copyright (c) 2006 Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom165p.h 2231 2011-03-07 05:06:55Z arcanum $ */ ++ ++/* avr/iom165p.h - definitions for ATmega165P */ ++ ++#ifndef _AVR_IOM165P_H_ ++#define _AVR_IOM165P_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom165p.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE7 7 ++#define DDE6 6 ++#define DDE5 5 ++#define DDE4 4 ++#define DDE3 3 ++#define DDE2 2 ++#define DDE1 1 ++#define DDE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PE7 7 ++#define PE6 6 ++#define PE5 5 ++#define PE4 4 ++#define PE3 3 ++#define PE2 2 ++#define PE1 1 ++#define PE0 0 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDF7 7 ++#define DDF6 6 ++#define DDF5 5 ++#define DDF4 4 ++#define DDF3 3 ++#define DDF2 2 ++#define DDF1 1 ++#define DDF0 0 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PF7 7 ++#define PF6 6 ++#define PF5 5 ++#define PF4 4 ++#define PF3 3 ++#define PF2 2 ++#define PF1 1 ++#define PF0 0 ++ ++#define PING _SFR_IO8(0x12) ++#define PING5 5 ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++#define DDRG _SFR_IO8(0x13) ++#define DDG4 4 ++#define DDG3 3 ++#define DDG2 2 ++#define DDG1 1 ++#define DDG0 0 ++ ++#define PORTG _SFR_IO8(0x14) ++#define PG4 4 ++#define PG3 3 ++#define PG2 2 ++#define PG1 1 ++#define PG0 0 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++ ++/* Reserved [0x18..0x1B] */ ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define PCIF0 6 ++#define PCIF1 7 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define PCIE0 6 ++#define PCIE1 7 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++ ++#define EEDR _SFR_IO8(0X20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0X22) ++ ++/* 6-char sequence denoting where to find the EEPROM registers in memory space. ++ Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM ++ subroutines. ++ First two letters: EECR address. ++ Second two letters: EEDR address. ++ Last two letters: EEAR address. */ ++#define __EEPROM_REG_LOCATIONS__ 1F2021 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR10 0 ++#define PSR2 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM01 3 ++#define COM0A0 4 ++#define COM0A1 5 ++#define WGM00 6 ++#define FOC0A 7 ++ ++/* Reserved [0x25] */ ++ ++#define TCNT0 _SFR_IO8(0X26) ++ ++#define OCR0A _SFR_IO8(0X27) ++ ++/* Reserved [0x28..0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0X2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCD 7 // The datasheet defines this but IMO it should be OCDR7. ++#define OCDR7 7 ++#define IDRD 7 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define JTRF 4 ++ ++#define MCUCR _SFR_IO8(0X35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define JTD 7 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++/* SREG [0x3F] */ ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++ ++/* Reserved [0x67..0x68] */ ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++ ++/* Reserved [0x6A] */ ++ ++/* Combine PCMSK0 and PCMSK1 */ ++#define PCMSK _SFR_MEM16(0x6B) ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++/* Reserved [0x6D] */ ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++ ++/* Reserved [0x71..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0X80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0X81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM21 3 ++#define COM2A0 4 ++#define COM2A1 5 ++#define WGM20 6 ++#define FOC2A 7 ++ ++/* Reserved [0xB1] */ ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++/* Reserved [0xB4..0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2UB 0 ++#define OCR2UB 1 ++#define TCN2UB 2 ++#define AS2 3 ++#define EXCLK 4 ++ ++/* Reserved [0xB7] */ ++ ++#define USICR _SFR_MEM8(0xB8) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_MEM8(0xB9) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_MEM8(0xBA) ++ ++/* Reserved [0xBB..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0XC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL0 6 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRRL and UBRRH */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0XC6) ++ ++/* Reserved [0xC7..0xFF] */ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) ++#define SIG_PIN_CHANGE0 _VECTOR(2) ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect_num 3 ++#define PCINT1_vect _VECTOR(3) ++#define SIG_PIN_CHANGE1 _VECTOR(3) ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect_num 4 ++#define TIMER2_COMP_vect _VECTOR(4) ++#define SIG_OUTPUT_COMPARE2 _VECTOR(4) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 5 ++#define TIMER2_OVF_vect _VECTOR(5) ++#define SIG_OVERFLOW2 _VECTOR(5) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 6 ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define SIG_INPUT_CAPTURE1 _VECTOR(6) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 7 ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(7) ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect_num 8 ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(8) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 9 ++#define TIMER1_OVF_vect _VECTOR(9) ++#define SIG_OVERFLOW1 _VECTOR(9) ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect_num 10 ++#define TIMER0_COMP_vect _VECTOR(10) ++#define SIG_OUTPUT_COMPARE0 _VECTOR(10) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 11 ++#define TIMER0_OVF_vect _VECTOR(11) ++#define SIG_OVERFLOW0 _VECTOR(11) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 12 ++#define SPI_STC_vect _VECTOR(12) ++#define SIG_SPI _VECTOR(12) ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect_num 13 ++#define USART0_RX_vect _VECTOR(13) ++#define USART_RX_vect _VECTOR(13) /* Alias */ ++#define SIG_UART_RECV _VECTOR(13) ++ ++/* USART0 Data register Empty */ ++#define USART0_UDRE_vect_num 14 ++#define USART0_UDRE_vect _VECTOR(14) ++#define USART_UDRE_vect _VECTOR(14) /* Alias */ ++#define SIG_UART_DATA _VECTOR(14) ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect_num 15 ++#define USART0_TX_vect _VECTOR(15) ++#define USART_TX_vect _VECTOR(15) /* Alias */ ++#define SIG_UART_TRANS _VECTOR(15) ++ ++/* USI Start Condition */ ++#define USI_START_vect_num 16 ++#define USI_START_vect _VECTOR(16) ++#define SIG_USI_START _VECTOR(16) ++ ++/* USI Overflow */ ++#define USI_OVERFLOW_vect_num 17 ++#define USI_OVERFLOW_vect _VECTOR(17) ++#define SIG_USI_OVERFLOW _VECTOR(17) ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect_num 18 ++#define ANALOG_COMP_vect _VECTOR(18) ++#define SIG_COMPARATOR _VECTOR(18) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 19 ++#define ADC_vect _VECTOR(19) ++#define SIG_ADC _VECTOR(19) ++ ++/* EEPROM Ready */ ++#define EE_READY_vect_num 20 ++#define EE_READY_vect _VECTOR(20) ++#define SIG_EEPROM_READY _VECTOR(20) ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect_num 21 ++#define SPM_READY_vect _VECTOR(21) ++#define SIG_SPM_READY _VECTOR(21) ++ ++#define _VECTORS_SIZE 88 ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE 128 ++#define RAMSTART 0x100 ++#define RAMEND 0x4FF ++#define XRAMEND RAMEND ++#define E2END 0x1FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x3FFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x07 ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_PIN_CHANGE0 ++#pragma GCC poison SIG_PIN_CHANGE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE2 ++#pragma GCC poison SIG_OVERFLOW2 ++#pragma GCC poison SIG_INPUT_CAPTURE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OUTPUT_COMPARE0 ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_SPI ++#pragma GCC poison USART_RX_vect ++#pragma GCC poison SIG_UART_RECV ++#pragma GCC poison USART_UDRE_vect ++#pragma GCC poison SIG_UART_DATA ++#pragma GCC poison USART_TX_vect ++#pragma GCC poison SIG_UART_TRANS ++#pragma GCC poison SIG_USI_START ++#pragma GCC poison SIG_USI_OVERFLOW ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_ADC ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_SPM_READY ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++#endif /* _AVR_IOM165P_H_ */ +diff --git a/include/avr/iom165pa.h b/include/avr/iom165pa.h +new file mode 100644 +index 0000000..2581cc5 +--- /dev/null ++++ b/include/avr/iom165pa.h +@@ -0,0 +1,821 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATMEGA165PA_H_INCLUDED ++#define _AVR_ATMEGA165PA_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom165pa.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDRA7 7 ++#define DDRA6 6 ++#define DDRA5 5 ++#define DDRA4 4 ++#define DDRA3 3 ++#define DDRA2 2 ++#define DDRA1 1 ++#define DDRA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDRC7 7 ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC7 7 ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDRE7 7 ++#define DDRE6 6 ++#define DDRE5 5 ++#define DDRE4 4 ++#define DDRE3 3 ++#define DDRE2 2 ++#define DDRE1 1 ++#define DDRE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE7 7 ++#define PORTE6 6 ++#define PORTE5 5 ++#define PORTE4 4 ++#define PORTE3 3 ++#define PORTE2 2 ++#define PORTE1 1 ++#define PORTE0 0 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDRF7 7 ++#define DDRF6 6 ++#define DDRF5 5 ++#define DDRF4 4 ++#define DDRF3 3 ++#define DDRF2 2 ++#define DDRF1 1 ++#define DDRF0 0 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PORTF7 7 ++#define PORTF6 6 ++#define PORTF5 5 ++#define PORTF4 4 ++#define PORTF3 3 ++#define PORTF2 2 ++#define PORTF1 1 ++#define PORTF0 0 ++ ++#define PING _SFR_IO8(0x12) ++#define PING5 5 ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++#define DDRG _SFR_IO8(0x13) ++#define DDRG4 4 ++#define DDRG3 3 ++#define DDRG2 2 ++#define DDRG1 1 ++#define DDRG0 0 ++ ++#define PORTG _SFR_IO8(0x14) ++#define PORTG4 4 ++#define PORTG3 3 ++#define PORTG2 2 ++#define PORTG1 1 ++#define PORTG0 0 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++ ++/* Reserved [0x18..0x1B] */ ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define PCIF0 4 ++#define PCIF1 5 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define PCIE0 4 ++#define PCIE1 5 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR310 0 ++#define TSM 7 ++#define PSR2 1 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM01 3 ++#define COM0A0 4 ++#define COM0A1 5 ++#define WGM00 6 ++#define FOC0A 7 ++ ++/* Reserved [0x25] */ ++ ++#define TCNT0 _SFR_IO8(0x26) ++ ++#define OCR0A _SFR_IO8(0x27) ++ ++/* Reserved [0x28..0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR7 7 ++#define OCDR6 6 ++#define OCDR5 5 ++#define OCDR4 4 ++#define OCDR3 3 ++#define OCDR2 2 ++#define OCDR1 1 ++#define OCDR0 0 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define JTRF 4 ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define JTD 7 ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++/* Reserved [0x67..0x68] */ ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++/* Reserved [0x6D] */ ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++ ++/* Reserved [0x71..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ACME 6 ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM21 3 ++#define COM2A0 4 ++#define COM2A1 5 ++#define WGM20 6 ++#define FOC2A 7 ++ ++/* Reserved [0xB1] */ ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++/* Reserved [0xB4..0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2UB 0 ++#define OCR2UB 1 ++#define TCN2UB 2 ++#define AS2 3 ++#define EXCLK 4 ++ ++/* Reserved [0xB7] */ ++ ++#define USICR _SFR_MEM8(0xB8) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_MEM8(0xB9) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_MEM8(0xBA) ++ ++/* Reserved [0xBB..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL0 6 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0xC6) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(2) ++#define PCINT0_vect_num 2 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(3) ++#define PCINT1_vect_num 3 ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect _VECTOR(4) ++#define TIMER2_COMP_vect_num 4 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(5) ++#define TIMER2_OVF_vect_num 5 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define TIMER1_CAPT_vect_num 6 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define TIMER1_COMPA_vect_num 7 ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define TIMER1_COMPB_vect_num 8 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(9) ++#define TIMER1_OVF_vect_num 9 ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect _VECTOR(10) ++#define TIMER0_COMP_vect_num 10 ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(11) ++#define TIMER0_OVF_vect_num 11 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(12) ++#define SPI_STC_vect_num 12 ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect _VECTOR(13) ++#define USART0_RX_vect_num 13 ++ ++/* USART0 Data register Empty */ ++#define USART0_UDRE_vect _VECTOR(14) ++#define USART0_UDRE_vect_num 14 ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect _VECTOR(15) ++#define USART0_TX_vect_num 15 ++ ++/* USI Start Condition */ ++#define USI_START_vect _VECTOR(16) ++#define USI_START_vect_num 16 ++ ++/* USI Overflow */ ++#define USI_OVERFLOW_vect _VECTOR(17) ++#define USI_OVERFLOW_vect_num 17 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(18) ++#define ANALOG_COMP_vect_num 18 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(19) ++#define ADC_vect_num 19 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(20) ++#define EE_READY_vect_num 20 ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect _VECTOR(21) ++#define SPM_READY_vect_num 21 ++ ++#define _VECTORS_SIZE 88 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 128 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x3FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 1024 ++#define RAMEND 0x04FF ++#define E2START 0 ++#define E2SIZE 512 ++#define E2PAGESIZE 4 ++#define E2END 0x01FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x07 ++ ++ ++#endif /* #ifdef _AVR_ATMEGA165PA_H_INCLUDED */ ++ +diff --git a/include/avr/iom168.h b/include/avr/iom168.h +index 7bf016a..e16e914 100644 +--- a/include/avr/iom168.h ++++ b/include/avr/iom168.h +@@ -1,92 +1,92 @@ +-/* Copyright (c) 2004, Theodore A. Roth +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom168.h 2115 2010-04-05 23:19:53Z arcanum $ */ +- +-#ifndef _AVR_IOM168_H_ +-#define _AVR_IOM168_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 128 +-#define RAMSTART (0x100) +-#define RAMEND 0x4FF +-#define XRAMEND RAMEND +-#define E2END 0x1FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x3FFF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x94 +-#define SIGNATURE_2 0x06 +- +- +-#endif /* _AVR_IOM168_H_ */ ++/* Copyright (c) 2004, Theodore A. Roth ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom168.h 2115 2010-04-05 23:19:53Z arcanum $ */ ++ ++#ifndef _AVR_IOM168_H_ ++#define _AVR_IOM168_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 128 ++#define RAMSTART (0x100) ++#define RAMEND 0x4FF ++#define XRAMEND RAMEND ++#define E2END 0x1FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x3FFF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x06 ++ ++ ++#endif /* _AVR_IOM168_H_ */ +diff --git a/include/avr/iom168a.h b/include/avr/iom168a.h +new file mode 100644 +index 0000000..b130eac +--- /dev/null ++++ b/include/avr/iom168a.h +@@ -0,0 +1,34 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2011 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++#include "iom168.h" +diff --git a/include/avr/iom168p.h b/include/avr/iom168p.h +index 528a12d..b03c1f4 100644 +--- a/include/avr/iom168p.h ++++ b/include/avr/iom168p.h +@@ -1,925 +1,927 @@ +-/* Copyright (c) 2007 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. +-*/ +- +-/* $Id: iom168p.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* avr/iom168p.h - definitions for ATmega168P. */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom168p.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_IOM168P_H_ +-#define _AVR_IOM168P_H_ 1 +- +-/* Registers and associated bit numbers */ +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC3 3 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC3 3 +-#define PORTC4 4 +-#define PORTC5 5 +-#define PORTC6 6 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define TIFR2 _SFR_IO8(0x17) +-#define TOV2 0 +-#define OCF2A 1 +-#define OCF2B 2 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +-#define PCIF1 1 +-#define PCIF2 2 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +- +-#define EEPROM_REG_LOCATIONS 1F2021 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSRSYNC 0 +-#define PSRASY 1 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define OCR0A _SFR_IO8(0x27) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define OCR0B _SFR_IO8(0x28) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define BODSE 5 +-#define BODS 6 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SELFPRGEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM1 3 +-#define PRTIM0 5 +-#define PRTIM2 6 +-#define PRTWI 7 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +-#define PCIE1 1 +-#define PCIE2 2 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +- +-#define PCMSK2 _SFR_MEM8(0x6D) +-#define PCINT16 0 +-#define PCINT17 1 +-#define PCINT18 2 +-#define PCINT19 3 +-#define PCINT20 4 +-#define PCINT21 5 +-#define PCINT22 6 +-#define PCINT23 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define TIMSK2 _SFR_MEM8(0x70) +-#define TOIE2 0 +-#define OCIE2A 1 +-#define OCIE2B 2 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +- +-#define ADCL _SFR_MEM8(0x78) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_MEM8(0x79) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ACME 6 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define TCCR2A _SFR_MEM8(0xB0) +-#define WGM20 0 +-#define WGM21 1 +-#define COM2B0 4 +-#define COM2B1 5 +-#define COM2A0 6 +-#define COM2A1 7 +- +-#define TCCR2B _SFR_MEM8(0xB1) +-#define CS20 0 +-#define CS21 1 +-#define CS22 2 +-#define WGM22 3 +-#define FOC2B 6 +-#define FOC2A 7 +- +-#define TCNT2 _SFR_MEM8(0xB2) +-#define TCNT2_0 0 +-#define TCNT2_1 1 +-#define TCNT2_2 2 +-#define TCNT2_3 3 +-#define TCNT2_4 4 +-#define TCNT2_5 5 +-#define TCNT2_6 6 +-#define TCNT2_7 7 +- +-#define OCR2A _SFR_MEM8(0xB3) +-#define OCR2_0 0 +-#define OCR2_1 1 +-#define OCR2_2 2 +-#define OCR2_3 3 +-#define OCR2_4 4 +-#define OCR2_5 5 +-#define OCR2_6 6 +-#define OCR2_7 7 +- +-#define OCR2B _SFR_MEM8(0xB4) +-#define OCR2_0 0 +-#define OCR2_1 1 +-#define OCR2_2 2 +-#define OCR2_3 3 +-#define OCR2_4 4 +-#define OCR2_5 5 +-#define OCR2_6 6 +-#define OCR2_7 7 +- +-#define ASSR _SFR_MEM8(0xB6) +-#define TCR2BUB 0 +-#define TCR2AUB 1 +-#define OCR2BUB 2 +-#define OCR2AUB 3 +-#define TCN2UB 4 +-#define AS2 5 +-#define EXCLK 6 +- +-#define TWBR _SFR_MEM8(0xB8) +-#define TWBR0 0 +-#define TWBR1 1 +-#define TWBR2 2 +-#define TWBR3 3 +-#define TWBR4 4 +-#define TWBR5 5 +-#define TWBR6 6 +-#define TWBR7 7 +- +-#define TWSR _SFR_MEM8(0xB9) +-#define TWPS0 0 +-#define TWPS1 1 +-#define TWS3 3 +-#define TWS4 4 +-#define TWS5 5 +-#define TWS6 6 +-#define TWS7 7 +- +-#define TWAR _SFR_MEM8(0xBA) +-#define TWGCE 0 +-#define TWA0 1 +-#define TWA1 2 +-#define TWA2 3 +-#define TWA3 4 +-#define TWA4 5 +-#define TWA5 6 +-#define TWA6 7 +- +-#define TWDR _SFR_MEM8(0xBB) +-#define TWD0 0 +-#define TWD1 1 +-#define TWD2 2 +-#define TWD3 3 +-#define TWD4 4 +-#define TWD5 5 +-#define TWD6 6 +-#define TWD7 7 +- +-#define TWCR _SFR_MEM8(0xBC) +-#define TWIE 0 +-#define TWEN 2 +-#define TWWC 3 +-#define TWSTO 4 +-#define TWSTA 5 +-#define TWEA 6 +-#define TWINT 7 +- +-#define TWAMR _SFR_MEM8(0xBD) +-#define TWAM0 0 +-#define TWAM1 1 +-#define TWAM2 2 +-#define TWAM3 3 +-#define TWAM4 4 +-#define TWAM5 5 +-#define TWAM6 6 +- +-#define UCSR0A _SFR_MEM8(0xC0) +-#define MPCM0 0 +-#define U2X0 1 +-#define UPE0 2 +-#define DOR0 3 +-#define FE0 4 +-#define UDRE0 5 +-#define TXC0 6 +-#define RXC0 7 +- +-#define UCSR0B _SFR_MEM8(0xC1) +-#define TXB80 0 +-#define RXB80 1 +-#define UCSZ02 2 +-#define TXEN0 3 +-#define RXEN0 4 +-#define UDRIE0 5 +-#define TXCIE0 6 +-#define RXCIE0 7 +- +-#define UCSR0C _SFR_MEM8(0xC2) +-#define UCPOL0 0 +-#define UCSZ00 1 +-#define UCPHA0 1 +-#define UCSZ01 2 +-#define UDORD0 2 +-#define USBS0 3 +-#define UPM00 4 +-#define UPM01 5 +-#define UMSEL00 6 +-#define UMSEL01 7 +- +-#define UBRR0 _SFR_MEM16(0xC4) +- +-#define UBRR0L _SFR_MEM8(0xC4) +-#define UBRR0_0 0 +-#define UBRR0_1 1 +-#define UBRR0_2 2 +-#define UBRR0_3 3 +-#define UBRR0_4 4 +-#define UBRR0_5 5 +-#define UBRR0_6 6 +-#define UBRR0_7 7 +- +-#define UBRR0H _SFR_MEM8(0xC5) +-#define UBRR0_8 0 +-#define UBRR0_9 1 +-#define UBRR0_10 2 +-#define UBRR0_11 3 +- +-#define UDR0 _SFR_MEM8(0xC6) +-#define UDR0_0 0 +-#define UDR0_1 1 +-#define UDR0_2 2 +-#define UDR0_3 3 +-#define UDR0_4 4 +-#define UDR0_5 5 +-#define UDR0_6 6 +-#define UDR0_7 7 +- +- +- +-/* Interrupt Vectors */ +-/* Interrupt Vector 0 is the reset vector. */ +- +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +- +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ +- +-#define PCINT0_vect_num 3 +-#define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ +- +-#define PCINT1_vect_num 4 +-#define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */ +- +-#define PCINT2_vect_num 5 +-#define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */ +- +-#define WDT_vect_num 6 +-#define WDT_vect _VECTOR(6) /* Watchdog Time-out Interrupt */ +- +-#define TIMER2_COMPA_vect_num 7 +-#define TIMER2_COMPA_vect _VECTOR(7) /* Timer/Counter2 Compare Match A */ +- +-#define TIMER2_COMPB_vect_num 8 +-#define TIMER2_COMPB_vect _VECTOR(8) /* Timer/Counter2 Compare Match A */ +- +-#define TIMER2_OVF_vect_num 9 +-#define TIMER2_OVF_vect _VECTOR(9) /* Timer/Counter2 Overflow */ +- +-#define TIMER1_CAPT_vect_num 10 +-#define TIMER1_CAPT_vect _VECTOR(10) /* Timer/Counter1 Capture Event */ +- +-#define TIMER1_COMPA_vect_num 11 +-#define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */ +- +-#define TIMER1_COMPB_vect_num 12 +-#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */ +- +-#define TIMER1_OVF_vect_num 13 +-#define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */ +- +-#define TIMER0_COMPA_vect_num 14 +-#define TIMER0_COMPA_vect _VECTOR(14) /* TimerCounter0 Compare Match A */ +- +-#define TIMER0_COMPB_vect_num 15 +-#define TIMER0_COMPB_vect _VECTOR(15) /* TimerCounter0 Compare Match B */ +- +-#define TIMER0_OVF_vect_num 16 +-#define TIMER0_OVF_vect _VECTOR(16) /* Timer/Couner0 Overflow */ +- +-#define SPI_STC_vect_num 17 +-#define SPI_STC_vect _VECTOR(17) /* SPI Serial Transfer Complete */ +- +-#define USART_RX_vect_num 18 +-#define USART_RX_vect _VECTOR(18) /* USART Rx Complete */ +- +-#define USART_UDRE_vect_num 19 +-#define USART_UDRE_vect _VECTOR(19) /* USART, Data Register Empty */ +- +-#define USART_TX_vect_num 20 +-#define USART_TX_vect _VECTOR(20) /* USART Tx Complete */ +- +-#define ADC_vect_num 21 +-#define ADC_vect _VECTOR(21) /* ADC Conversion Complete */ +- +-#define EE_READY_vect_num 22 +-#define EE_READY_vect _VECTOR(22) /* EEPROM Ready */ +- +-#define ANALOG_COMP_vect_num 23 +-#define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */ +- +-#define TWI_vect_num 24 +-#define TWI_vect _VECTOR(24) /* Two-wire Serial Interface */ +- +-#define SPM_READY_vect_num 25 +-#define SPM_READY_vect _VECTOR(25) /* Store Program Memory Read */ +- +-#define _VECTORS_SIZE (26 * 4) +- +- +- +-/* Constants */ +-#define SPM_PAGESIZE 128 +-#define RAMSTART (0x100) +-#define RAMEND 0x4FF /* Last On-Chip SRAM Location */ +-#define XRAMSIZE 0 +-#define XRAMEND RAMEND +-#define E2END 0x1FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x3FFF +- +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) +- +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x94 +-#define SIGNATURE_2 0x0B +- +- +-#endif /* _AVR_IOM168P_H_ */ ++/* Copyright (c) 2007 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++/* $Id: iom168p.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* avr/iom168p.h - definitions for ATmega168P. */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom168p.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_IOM168P_H_ ++#define _AVR_IOM168P_H_ 1 ++ ++/* Registers and associated bit numbers */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC3 3 ++#define PORTC4 4 ++#define PORTC5 5 ++#define PORTC6 6 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++ ++#define EEPROM_REG_LOCATIONS 1F2021 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define PSRASY 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define OCR0A _SFR_IO8(0x27) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define OCR0B _SFR_IO8(0x28) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SELFPRGEN 0 ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_MEM8(0x79) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++#define TCNT2_0 0 ++#define TCNT2_1 1 ++#define TCNT2_2 2 ++#define TCNT2_3 3 ++#define TCNT2_4 4 ++#define TCNT2_5 5 ++#define TCNT2_6 6 ++#define TCNT2_7 7 ++ ++#define OCR2A _SFR_MEM8(0xB3) ++#define OCR2_0 0 ++#define OCR2_1 1 ++#define OCR2_2 2 ++#define OCR2_3 3 ++#define OCR2_4 4 ++#define OCR2_5 5 ++#define OCR2_6 6 ++#define OCR2_7 7 ++ ++#define OCR2B _SFR_MEM8(0xB4) ++#define OCR2_0 0 ++#define OCR2_1 1 ++#define OCR2_2 2 ++#define OCR2_3 3 ++#define OCR2_4 4 ++#define OCR2_5 5 ++#define OCR2_6 6 ++#define OCR2_7 7 ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++ ++#define TWBR _SFR_MEM8(0xB8) ++#define TWBR0 0 ++#define TWBR1 1 ++#define TWBR2 2 ++#define TWBR3 3 ++#define TWBR4 4 ++#define TWBR5 5 ++#define TWBR6 6 ++#define TWBR7 7 ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++#define TWD0 0 ++#define TWD1 1 ++#define TWD2 2 ++#define TWD3 3 ++#define TWD4 4 ++#define TWD5 5 ++#define TWD6 6 ++#define TWD7 7 ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 0 ++#define TWAM1 1 ++#define TWAM2 2 ++#define TWAM3 3 ++#define TWAM4 4 ++#define TWAM5 5 ++#define TWAM6 6 ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCPHA0 1 ++#define UCSZ01 2 ++#define UDORD0 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0_0 0 ++#define UBRR0_1 1 ++#define UBRR0_2 2 ++#define UBRR0_3 3 ++#define UBRR0_4 4 ++#define UBRR0_5 5 ++#define UBRR0_6 6 ++#define UBRR0_7 7 ++ ++#define UBRR0H _SFR_MEM8(0xC5) ++#define UBRR0_8 0 ++#define UBRR0_9 1 ++#define UBRR0_10 2 ++#define UBRR0_11 3 ++ ++#define UDR0 _SFR_MEM8(0xC6) ++#define UDR0_0 0 ++#define UDR0_1 1 ++#define UDR0_2 2 ++#define UDR0_3 3 ++#define UDR0_4 4 ++#define UDR0_5 5 ++#define UDR0_6 6 ++#define UDR0_7 7 ++ ++ ++ ++/* Interrupt Vectors */ ++/* Interrupt Vector 0 is the reset vector. */ ++ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ ++ ++#define PCINT0_vect_num 3 ++#define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ ++ ++#define PCINT1_vect_num 4 ++#define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */ ++ ++#define PCINT2_vect_num 5 ++#define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */ ++ ++#define WDT_vect_num 6 ++#define WDT_vect _VECTOR(6) /* Watchdog Time-out Interrupt */ ++ ++#define TIMER2_COMPA_vect_num 7 ++#define TIMER2_COMPA_vect _VECTOR(7) /* Timer/Counter2 Compare Match A */ ++ ++#define TIMER2_COMPB_vect_num 8 ++#define TIMER2_COMPB_vect _VECTOR(8) /* Timer/Counter2 Compare Match A */ ++ ++#define TIMER2_OVF_vect_num 9 ++#define TIMER2_OVF_vect _VECTOR(9) /* Timer/Counter2 Overflow */ ++ ++#define TIMER1_CAPT_vect_num 10 ++#define TIMER1_CAPT_vect _VECTOR(10) /* Timer/Counter1 Capture Event */ ++ ++#define TIMER1_COMPA_vect_num 11 ++#define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */ ++ ++#define TIMER1_COMPB_vect_num 12 ++#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */ ++ ++#define TIMER1_OVF_vect_num 13 ++#define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */ ++ ++#define TIMER0_COMPA_vect_num 14 ++#define TIMER0_COMPA_vect _VECTOR(14) /* TimerCounter0 Compare Match A */ ++ ++#define TIMER0_COMPB_vect_num 15 ++#define TIMER0_COMPB_vect _VECTOR(15) /* TimerCounter0 Compare Match B */ ++ ++#define TIMER0_OVF_vect_num 16 ++#define TIMER0_OVF_vect _VECTOR(16) /* Timer/Couner0 Overflow */ ++ ++#define SPI_STC_vect_num 17 ++#define SPI_STC_vect _VECTOR(17) /* SPI Serial Transfer Complete */ ++ ++#define USART_RX_vect_num 18 ++#define USART_RX_vect _VECTOR(18) /* USART Rx Complete */ ++ ++#define USART_UDRE_vect_num 19 ++#define USART_UDRE_vect _VECTOR(19) /* USART, Data Register Empty */ ++ ++#define USART_TX_vect_num 20 ++#define USART_TX_vect _VECTOR(20) /* USART Tx Complete */ ++ ++#define ADC_vect_num 21 ++#define ADC_vect _VECTOR(21) /* ADC Conversion Complete */ ++ ++#define EE_READY_vect_num 22 ++#define EE_READY_vect _VECTOR(22) /* EEPROM Ready */ ++ ++#define ANALOG_COMP_vect_num 23 ++#define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */ ++ ++#define TWI_vect_num 24 ++#define TWI_vect _VECTOR(24) /* Two-wire Serial Interface */ ++ ++#define SPM_READY_vect_num 25 ++#define SPM_READY_vect _VECTOR(25) /* Store Program Memory Read */ ++ ++#define _VECTORS_SIZE (26 * 4) ++ ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE 128 ++#define RAMSTART (0x100) ++#define RAMEND 0x4FF /* Last On-Chip SRAM Location */ ++#define XRAMSIZE 0 ++#define XRAMEND RAMEND ++#define E2END 0x1FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x3FFF ++ ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) ++ ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x0B ++ ++ ++#endif /* _AVR_IOM168P_H_ */ +diff --git a/include/avr/iom168pa.h b/include/avr/iom168pa.h +new file mode 100644 +index 0000000..3ddeb9e +--- /dev/null ++++ b/include/avr/iom168pa.h +@@ -0,0 +1,771 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATMEGA168PA_H_INCLUDED ++#define _AVR_ATMEGA168PA_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom168pa.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++/* Reserved [0x0C..0x14] */ ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++/* Reserved [0x18..0x1A] */ ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define TSM 7 ++#define PSRASY 1 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++ ++#define OCR0A _SFR_IO8(0x27) ++ ++#define OCR0B _SFR_IO8(0x28) ++ ++/* Reserved [0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++/* Reserved [0x31..0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SELFPRGEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDE 3 ++#define WDCE 4 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++/* Reserved [0x67] */ ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++/* Reserved [0x71..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++#define OCR2B _SFR_MEM8(0xB4) ++ ++/* Reserved [0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++ ++/* Reserved [0xB7] */ ++ ++#define TWBR _SFR_MEM8(0xB8) ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++/* Reserved [0xBE..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0xC6) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(3) ++#define PCINT0_vect_num 3 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect _VECTOR(4) ++#define PCINT1_vect_num 4 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT2_vect _VECTOR(5) ++#define PCINT2_vect_num 5 ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect _VECTOR(6) ++#define WDT_vect_num 6 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPA_vect _VECTOR(7) ++#define TIMER2_COMPA_vect_num 7 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPB_vect _VECTOR(8) ++#define TIMER2_COMPB_vect_num 8 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(9) ++#define TIMER2_OVF_vect_num 9 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(10) ++#define TIMER1_CAPT_vect_num 10 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(11) ++#define TIMER1_COMPA_vect_num 11 ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(12) ++#define TIMER1_COMPB_vect_num 12 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(13) ++#define TIMER1_OVF_vect_num 13 ++ ++/* TimerCounter0 Compare Match A */ ++#define TIMER0_COMPA_vect _VECTOR(14) ++#define TIMER0_COMPA_vect_num 14 ++ ++/* TimerCounter0 Compare Match B */ ++#define TIMER0_COMPB_vect _VECTOR(15) ++#define TIMER0_COMPB_vect_num 15 ++ ++/* Timer/Couner0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(16) ++#define TIMER0_OVF_vect_num 16 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(17) ++#define SPI_STC_vect_num 17 ++ ++/* USART Rx Complete */ ++#define USART_RX_vect _VECTOR(18) ++#define USART_RX_vect_num 18 ++ ++/* USART, Data Register Empty */ ++#define USART_UDRE_vect _VECTOR(19) ++#define USART_UDRE_vect_num 19 ++ ++/* USART Tx Complete */ ++#define USART_TX_vect _VECTOR(20) ++#define USART_TX_vect_num 20 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(21) ++#define ADC_vect_num 21 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(22) ++#define EE_READY_vect_num 22 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(23) ++#define ANALOG_COMP_vect_num 23 ++ ++/* Two-wire Serial Interface */ ++#define TWI_vect _VECTOR(24) ++#define TWI_vect_num 24 ++ ++/* Store Program Memory Read */ ++#define SPM_Ready_vect _VECTOR(25) ++#define SPM_Ready_vect_num 25 ++ ++#define _VECTORS_SIZE 104 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 128 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x3FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 1024 ++#define RAMEND 0x04FF ++#define E2START 0 ++#define E2SIZE 512 ++#define E2PAGESIZE 4 ++#define E2END 0x01FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x0B ++ ++ ++#endif /* #ifdef _AVR_ATMEGA168PA_H_INCLUDED */ ++ +diff --git a/include/avr/iom168pb.h b/include/avr/iom168pb.h +new file mode 100644 +index 0000000..57d082d +--- /dev/null ++++ b/include/avr/iom168pb.h +@@ -0,0 +1,815 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATMEGA168PB_H_INCLUDED ++#define _AVR_ATMEGA168PB_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom168pb.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDRE3 3 ++#define DDRE2 2 ++#define DDRE1 1 ++#define DDRE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE3 3 ++#define PORTE2 2 ++#define PORTE1 1 ++#define PORTE0 0 ++ ++#define ACSRB _SFR_IO8(0x0F) ++#define ACOE 0 ++ ++/* Reserved [0x10..0x14] */ ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++/* Reserved [0x18..0x1A] */ ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define TSM 7 ++#define PSRASY 1 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++ ++#define OCR0A _SFR_IO8(0x27) ++ ++#define OCR0B _SFR_IO8(0x28) ++ ++/* Reserved [0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++/* Reserved [0x31..0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SELFPRGEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDE 3 ++#define WDCE 4 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++/* Reserved [0x67] */ ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++/* Reserved [0x71..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++#define OCR2B _SFR_MEM8(0xB4) ++ ++/* Reserved [0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++ ++/* Reserved [0xB7] */ ++ ++#define TWBR _SFR_MEM8(0xB8) ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++/* Reserved [0xBE..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++ ++#define UCSR0D _SFR_MEM8(0xC3) ++#define SFDE 5 ++#define RXS 6 ++#define RXSIE 7 ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0xC6) ++ ++/* Reserved [0xC7..0xEF] */ ++ ++#define DEVID0 _SFR_MEM8(0xF0) ++ ++#define DEVID1 _SFR_MEM8(0xF1) ++ ++#define DEVID2 _SFR_MEM8(0xF2) ++ ++#define DEVID3 _SFR_MEM8(0xF3) ++ ++#define DEVID4 _SFR_MEM8(0xF4) ++ ++#define DEVID5 _SFR_MEM8(0xF5) ++ ++#define DEVID6 _SFR_MEM8(0xF6) ++ ++#define DEVID7 _SFR_MEM8(0xF7) ++ ++#define DEVID8 _SFR_MEM8(0xF8) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(3) ++#define PCINT0_vect_num 3 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect _VECTOR(4) ++#define PCINT1_vect_num 4 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT2_vect _VECTOR(5) ++#define PCINT2_vect_num 5 ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect _VECTOR(6) ++#define WDT_vect_num 6 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPA_vect _VECTOR(7) ++#define TIMER2_COMPA_vect_num 7 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPB_vect _VECTOR(8) ++#define TIMER2_COMPB_vect_num 8 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(9) ++#define TIMER2_OVF_vect_num 9 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(10) ++#define TIMER1_CAPT_vect_num 10 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(11) ++#define TIMER1_COMPA_vect_num 11 ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(12) ++#define TIMER1_COMPB_vect_num 12 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(13) ++#define TIMER1_OVF_vect_num 13 ++ ++/* TimerCounter0 Compare Match A */ ++#define TIMER0_COMPA_vect _VECTOR(14) ++#define TIMER0_COMPA_vect_num 14 ++ ++/* TimerCounter0 Compare Match B */ ++#define TIMER0_COMPB_vect _VECTOR(15) ++#define TIMER0_COMPB_vect_num 15 ++ ++/* Timer/Couner0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(16) ++#define TIMER0_OVF_vect_num 16 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(17) ++#define SPI_STC_vect_num 17 ++ ++/* USART Rx Complete */ ++#define USART_RX_vect _VECTOR(18) ++#define USART_RX_vect_num 18 ++ ++/* USART, Data Register Empty */ ++#define USART_UDRE_vect _VECTOR(19) ++#define USART_UDRE_vect_num 19 ++ ++/* USART Tx Complete */ ++#define USART_TX_vect _VECTOR(20) ++#define USART_TX_vect_num 20 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(21) ++#define ADC_vect_num 21 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(22) ++#define EE_READY_vect_num 22 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(23) ++#define ANALOG_COMP_vect_num 23 ++ ++/* Two-wire Serial Interface */ ++#define TWI_vect _VECTOR(24) ++#define TWI_vect_num 24 ++ ++/* Store Program Memory Read */ ++#define SPM_Ready_vect _VECTOR(25) ++#define SPM_Ready_vect_num 25 ++ ++#define _VECTORS_SIZE 104 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 128 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x3FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 1024 ++#define RAMEND 0x04FF ++#define E2START 0 ++#define E2SIZE 512 ++#define E2PAGESIZE 4 ++#define E2END 0x01FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x15 ++ ++ ++#endif /* #ifdef _AVR_ATMEGA168PB_H_INCLUDED */ ++ +diff --git a/include/avr/iom169.h b/include/avr/iom169.h +index 210faaf..2e77d47 100644 +--- a/include/avr/iom169.h ++++ b/include/avr/iom169.h +@@ -1,1161 +1,1162 @@ +-/* Copyright (c) 2002, 2003, 2004, 2005 +- Juergen Schilling +- Eric B. Weddington +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom169.h 2231 2011-03-07 05:06:55Z arcanum $ */ +- +-/* iom169.h - definitions for ATmega169 */ +- +-/* This should be up to date with data sheet version 2514J-AVR-12/03. */ +- +-#ifndef _AVR_IOM169_H_ +-#define _AVR_IOM169_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom169.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* Port A */ +-#define PINA _SFR_IO8(0x00) +-#define DDRA _SFR_IO8(0x01) +-#define PORTA _SFR_IO8(0x02) +- +-/* Port B */ +-#define PINB _SFR_IO8(0x03) +-#define DDRB _SFR_IO8(0x04) +-#define PORTB _SFR_IO8(0x05) +- +-/* Port C */ +-#define PINC _SFR_IO8(0x06) +-#define DDRC _SFR_IO8(0x07) +-#define PORTC _SFR_IO8(0x08) +- +-/* Port D */ +-#define PIND _SFR_IO8(0x09) +-#define DDRD _SFR_IO8(0x0A) +-#define PORTD _SFR_IO8(0x0B) +- +-/* Port E */ +-#define PINE _SFR_IO8(0x0C) +-#define DDRE _SFR_IO8(0x0D) +-#define PORTE _SFR_IO8(0x0E) +- +-/* Port F */ +-#define PINF _SFR_IO8(0x0F) +-#define DDRF _SFR_IO8(0x10) +-#define PORTF _SFR_IO8(0x11) +- +-/* Port G */ +-#define PING _SFR_IO8(0x12) +-#define DDRG _SFR_IO8(0x13) +-#define PORTG _SFR_IO8(0x14) +- +-/* Timer/Counter 0 interrupt Flag Register */ +-#define TIFR0 _SFR_IO8(0x15) +- +-/* Timer/Counter 1 interrupt Flag Register */ +-#define TIFR1 _SFR_IO8(0x16) +- +-/* Timer/Counter 2 interrupt Flag Register */ +-#define TIFR2 _SFR_IO8(0x17) +- +-/* External Interrupt Flag Register */ +-#define EIFR _SFR_IO8(0x1C) +- +-/* External Interrupt Mask Register */ +-#define EIMSK _SFR_IO8(0x1D) +- +-/* General Purpose I/O Register 0 */ +-#define GPIOR0 _SFR_IO8(0x1E) +- +-#define EECR _SFR_IO8(0x1F) +- +-#define EEDR _SFR_IO8(0X20) +- +-/* Combine EEARL and EEARH */ +-#define EEAR _SFR_IO16(0x21) +-#define EEARL _SFR_IO8(0x21) +-#define EEARH _SFR_IO8(0X22) +- +-/* 6-char sequence denoting where to find the EEPROM registers in memory space. +- Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM +- subroutines. +- First two letters: EECR address. +- Second two letters: EEDR address. +- Last two letters: EEAR address. */ +-#define __EEPROM_REG_LOCATIONS__ 1F2021 +- +-/* General Timer/Counter Control Register */ +-#define GTCCR _SFR_IO8(0x23) +- +-/* Timer/Counter Control Register A */ +-#define TCCR0A _SFR_IO8(0x24) +- +-/* Timer/Counter Register */ +-#define TCNT0 _SFR_IO8(0x26) +- +-/* Output Compare Register A */ +-#define OCR0A _SFR_IO8(0x27) +- +-/* General Purpose I/O Register 1 */ +-#define GPIOR1 _SFR_IO8(0x2A) +- +-/* General Purpose I/O Register 2 */ +-#define GPIOR2 _SFR_IO8(0x2B) +- +-/* SPI Control Register */ +-#define SPCR _SFR_IO8(0x2C) +- +-/* SPI Status Register */ +-#define SPSR _SFR_IO8(0x2D) +- +-/* SPI Data Register */ +-#define SPDR _SFR_IO8(0x2E) +- +-/* Analog Comperator Control and Status Register */ +-#define ACSR _SFR_IO8(0x30) +- +-/* On-chip Debug Register */ +-#define OCDR _SFR_IO8(0x31) +- +-/* Sleep Mode Control Register */ +-#define SMCR _SFR_IO8(0x33) +- +-/* MCU Status Register */ +-#define MCUSR _SFR_IO8(0x34) +- +-/* MCU Control Rgeister */ +-#define MCUCR _SFR_IO8(0x35) +- +-/* Store Program Memory Control and Status Register */ +-#define SPMCSR _SFR_IO8(0x37) +- +-/* Watchdog Timer Control Register */ +-#define WDTCR _SFR_MEM8(0x60) +- +-/* Clock Prescale Register */ +-#define CLKPR _SFR_MEM8(0x61) +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM1 3 +-#define PRLCD 4 +- +-/* Oscillator Calibration Register */ +-#define OSCCAL _SFR_MEM8(0x66) +- +-/* External Interrupt Control Register A */ +-#define EICRA _SFR_MEM8(0x69) +- +-/* Pin Change Mask Register */ +-#define PCMSK _SFR_MEM16(0x6B) +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCMSK1 _SFR_MEM8(0x6C) +- +-/* Timer/Counter 0 Interrupt Mask Register */ +-#define TIMSK0 _SFR_MEM8(0x6E) +- +-/* Timer/Counter 1 Interrupt Mask Register */ +-#define TIMSK1 _SFR_MEM8(0x6F) +- +-/* Timer/Counter 2 Interrupt Mask Register */ +-#define TIMSK2 _SFR_MEM8(0x70) +- +-/* ADC Data Register */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +-#define ADCL _SFR_MEM8(0x78) +-#define ADCH _SFR_MEM8(0x79) +- +-/* ADC Control and Status Register A */ +-#define ADCSRA _SFR_MEM8(0x7A) +- +-/* ADC Control and Status Register B */ +-#define ADCSRB _SFR_MEM8(0x7B) +- +-/* ADC Multiplex Selection Register */ +-#define ADMUX _SFR_MEM8(0x7C) +- +-/* NOTE: DIDR0 and DIDR1 are swapped in the register summary of the data sheet +- (2514D-AVR-01/03), but seem to be correct in the discussions of the +- registers. */ +- +-/* Digital Input Disable Register 0 */ +-#define DIDR0 _SFR_MEM8(0x7E) +- +-/* Digital Input Disable Register 1 */ +-#define DIDR1 _SFR_MEM8(0x7F) +- +-/* Timer/Counter1 Control Register A */ +-#define TCCR1A _SFR_MEM8(0x80) +- +-/* Timer/Counter1 Control Register B */ +-#define TCCR1B _SFR_MEM8(0x81) +- +-/* Timer/Counter1 Control Register C */ +-#define TCCR1C _SFR_MEM8(0x82) +- +-/* Timer/Counter1 Register */ +-#define TCNT1 _SFR_MEM16(0x84) +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1H _SFR_MEM8(0x85) +- +-/* Timer/Counter1 Input Capture Register */ +-#define ICR1 _SFR_MEM16(0x86) +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1H _SFR_MEM8(0x87) +- +-/* Timer/Counter1 Output Compare Register A */ +-#define OCR1A _SFR_MEM16(0x88) +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AH _SFR_MEM8(0x89) +- +-/* Timer/Counter1 Output Compare Registare B */ +-#define OCR1B _SFR_MEM16(0x8A) +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BH _SFR_MEM8(0x8B) +- +-/* Timer/Counter2 Control Register A */ +-#define TCCR2A _SFR_MEM8(0xB0) +- +-/* Timer/Counter2 Register */ +-#define TCNT2 _SFR_MEM8(0xB2) +- +-/* Timer/Counter2 Output Compare Register */ +-#define OCR2A _SFR_MEM8(0xB3) +- +-/* Asynchronous Status Register */ +-#define ASSR _SFR_MEM8(0xB6) +- +-/* USI Control Register */ +-#define USICR _SFR_MEM8(0xB8) +- +-/* USI Status Register */ +-#define USISR _SFR_MEM8(0xB9) +- +-/* USI Data Register */ +-#define USIDR _SFR_MEM8(0xBA) +- +-/* USART0 Control and Status Register A */ +-#define UCSRA _SFR_MEM8(0xC0) +- +-/* USART0 Control and Status Register B */ +-#define UCSRB _SFR_MEM8(0xC1) +- +-/* USART0 Control and Status Register C */ +-#define UCSRC _SFR_MEM8(0xC2) +- +-/* USART0 Baud Rate Register */ +-#define UBRR _SFR_MEM16(0xC4) +-#define UBRRL _SFR_MEM8(0xC4) +-#define UBRRH _SFR_MEM8(0xC5) +- +-/* USART0 I/O Data Register */ +-#define UDR _SFR_MEM8(0xC6) +- +-/* LCD Control and Status Register A */ +-#define LCDCRA _SFR_MEM8(0xE4) +- +-/* LCD Control and Status Register B */ +-#define LCDCRB _SFR_MEM8(0xE5) +- +-/* LCD Frame Rate Register */ +-#define LCDFRR _SFR_MEM8(0xE6) +- +-/* LCD Contrast Control Register */ +-#define LCDCCR _SFR_MEM8(0xE7) +- +-/* LCD Memory mapping */ +-#define LCDDR0 _SFR_MEM8(0xEC) +-#define LCDDR1 _SFR_MEM8(0xED) +-#define LCDDR2 _SFR_MEM8(0xEE) +-#define LCDDR3 _SFR_MEM8(0xEF) +-#define LCDDR5 _SFR_MEM8(0xF1) +-#define LCDDR6 _SFR_MEM8(0xF2) +-#define LCDDR7 _SFR_MEM8(0xF3) +-#define LCDDR8 _SFR_MEM8(0xF4) +-#define LCDDR10 _SFR_MEM8(0xF6) +-#define LCDDR11 _SFR_MEM8(0xF7) +-#define LCDDR12 _SFR_MEM8(0xF8) +-#define LCDDR13 _SFR_MEM8(0xF9) +-#define LCDDR15 _SFR_MEM8(0xFB) +-#define LCDDR16 _SFR_MEM8(0xFC) +-#define LCDDR17 _SFR_MEM8(0xFD) +-#define LCDDR18 _SFR_MEM8(0xFE) +- +-/* Interrupt vectors */ +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* Pin Change Interrupt Request 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) +-#define SIG_PIN_CHANGE0 _VECTOR(2) +- +-/* Pin Change Interrupt Request 1 */ +-#define PCINT1_vect_num 3 +-#define PCINT1_vect _VECTOR(3) +-#define SIG_PIN_CHANGE1 _VECTOR(3) +- +-/* Timer/Counter2 Compare Match */ +-#define TIMER2_COMP_vect_num 4 +-#define TIMER2_COMP_vect _VECTOR(4) +-#define SIG_OUTPUT_COMPARE2 _VECTOR(4) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 5 +-#define TIMER2_OVF_vect _VECTOR(5) +-#define SIG_OVERFLOW2 _VECTOR(5) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 6 +-#define TIMER1_CAPT_vect _VECTOR(6) +-#define SIG_INPUT_CAPTURE1 _VECTOR(6) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 7 +-#define TIMER1_COMPA_vect _VECTOR(7) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(7) +- +-/* Timer/Counter Compare Match B */ +-#define TIMER1_COMPB_vect_num 8 +-#define TIMER1_COMPB_vect _VECTOR(8) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(8) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 9 +-#define TIMER1_OVF_vect _VECTOR(9) +-#define SIG_OVERFLOW1 _VECTOR(9) +- +-/* Timer/Counter0 Compare Match */ +-#define TIMER0_COMP_vect_num 10 +-#define TIMER0_COMP_vect _VECTOR(10) +-#define SIG_OUTPUT_COMPARE0 _VECTOR(10) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 11 +-#define TIMER0_OVF_vect _VECTOR(11) +-#define SIG_OVERFLOW0 _VECTOR(11) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 12 +-#define SPI_STC_vect _VECTOR(12) +-#define SIG_SPI _VECTOR(12) +- +-/* USART0, Rx Complete */ +-#define USART0_RX_vect_num 13 +-#define USART0_RX_vect _VECTOR(13) +-#define SIG_USART_RECV _VECTOR(13) +- +-/* USART0 Data register Empty */ +-#define USART0_UDRE_vect_num 14 +-#define USART0_UDRE_vect _VECTOR(14) +-#define SIG_USART_DATA _VECTOR(14) +- +-/* USART0, Tx Complete */ +-#define USART0_TX_vect_num 15 +-#define USART0_TX_vect _VECTOR(15) +-#define SIG_USART_TRANS _VECTOR(15) +- +-/* USI Start Condition */ +-#define USI_START_vect_num 16 +-#define USI_START_vect _VECTOR(16) +-#define SIG_USI_START _VECTOR(16) +- +-/* USI Overflow */ +-#define USI_OVERFLOW_vect_num 17 +-#define USI_OVERFLOW_vect _VECTOR(17) +-#define SIG_USI_OVERFLOW _VECTOR(17) +- +-/* Analog Comparator */ +-#define ANALOG_COMP_vect_num 18 +-#define ANALOG_COMP_vect _VECTOR(18) +-#define SIG_COMPARATOR _VECTOR(18) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 19 +-#define ADC_vect _VECTOR(19) +-#define SIG_ADC _VECTOR(19) +- +-/* EEPROM Ready */ +-#define EE_READY_vect_num 20 +-#define EE_READY_vect _VECTOR(20) +-#define SIG_EEPROM_READY _VECTOR(20) +- +-/* Store Program Memory Read */ +-#define SPM_READY_vect_num 21 +-#define SPM_READY_vect _VECTOR(21) +-#define SIG_SPM_READY _VECTOR(21) +- +-/* LCD Start of Frame */ +-#define LCD_vect_num 22 +-#define LCD_vect _VECTOR(22) +-#define SIG_LCD _VECTOR(22) +- +-#define _VECTORS_SIZE 92 +- +-/* Bit numbers */ +- +-/* +- PA7 = SEG3 +- PA6 = SEG2 +- PA5 = SEG1 +- PA4 = SEG0 +- PA3 = COM3 +- PA2 = COM2 +- PA1 = COM1 +- PA0 = COM0 +-*/ +- +-/* PORTA */ +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-/* DDRA */ +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-/* PINA */ +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-/* +- PB7 = OC2A / PCINT15 +- PB6 = OC1B / PCINT14 +- PB5 = OC1A / PCINT13 +- PB4 = OC0A / PCINT12 +- PB3 = MISO / PCINT11 +- PB2 = MOSI / PCINT10 +- PB1 = SCK / PCINT9 +- PB0 = SS# / PCINT8 +- */ +- +-/* PORTB */ +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* DDRB */ +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* PINB */ +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* +- PC7 = SEG5 +- PC6 = SEG6 +- PC5 = SEG7 +- PC4 = SEG8 +- PC3 = SEG9 +- PC2 = SEG10 +- PC1 = SEG11 +- PC0 = SEG12 +-*/ +- +-/* PORTC */ +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-/* DDRC */ +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-/* PINC */ +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-/* +- PD7 = SEG15 +- PD6 = SEG16 +- PD5 = SEG17 +- PD4 = SEG18 +- PD3 = SEG19 +- PD2 = SEG20 +- PD1 = INT0 / SEG21 +- PD0 = ICP / SEG22 +- */ +- +-/* PORTD */ +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* DDRD */ +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-/* PIND */ +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-/* +- PE7 = CLK0 / PCINT7 +- PE6 = DO / PCINT6 +- PE5 = DI / SDA / PCINT5 +- PE4 = USCK / SCL / PCINT4 +- PE3 = AIN1 / PCINT3 +- PE2 = XCK / AIN0 / PCINT2 +- PE1 = TXD / PCINT1 +- PE0 = RXD / PCINT0 +- */ +- +-/* PORTE */ +-#define PE7 7 +-#define PE6 6 +-#define PE5 5 +-#define PE4 4 +-#define PE3 3 +-#define PE2 2 +-#define PE1 1 +-#define PE0 0 +- +-/* DDRE */ +-#define DDE7 7 +-#define DDE6 6 +-#define DDE5 5 +-#define DDE4 4 +-#define DDE3 3 +-#define DDE2 2 +-#define DDE1 1 +-#define DDE0 0 +- +-/* PINE */ +-#define PINE7 7 +-#define PINE6 6 +-#define PINE5 5 +-#define PINE4 4 +-#define PINE3 3 +-#define PINE2 2 +-#define PINE1 1 +-#define PINE0 0 +- +-/* +- PF7 = ADC7 / TDI +- PF6 = ADC6 / TDO +- PF5 = ADC5 / TMS +- PF4 = ADC4 / TCK +- PF3 = ADC3 +- PF2 = ADC2 +- PF1 = ADC1 +- PF0 = ADC0 +- */ +- +-/* PORTF */ +-#define PF7 7 +-#define PF6 6 +-#define PF5 5 +-#define PF4 4 +-#define PF3 3 +-#define PF2 2 +-#define PF1 1 +-#define PF0 0 +- +-/* DDRF */ +-#define DDF7 7 +-#define DDF6 6 +-#define DDF5 5 +-#define DDF4 4 +-#define DDF3 3 +-#define DDF2 2 +-#define DDF1 1 +-#define DDF0 0 +- +-/* PINF */ +-#define PINF7 7 +-#define PINF6 6 +-#define PINF5 5 +-#define PINF4 4 +-#define PINF3 3 +-#define PINF2 2 +-#define PINF1 1 +-#define PINF0 0 +- +-/* +- PG5 = RESET# +- PG4 = T0 / SEG23 +- PG3 = T1 / SEG24 +- PG2 = SEG4 +- PG1 = SEG13 +- PG0 = SEG14 +- */ +- +-/* PORTG */ +-#define PG4 4 +-#define PG3 3 +-#define PG2 2 +-#define PG1 1 +-#define PG0 0 +- +-/* DDRG */ +-#define DDG4 4 +-#define DDG3 3 +-#define DDG2 2 +-#define DDG1 1 +-#define DDG0 0 +- +-/* PING */ +-#define PING5 5 +-#define PING4 4 +-#define PING3 3 +-#define PING2 2 +-#define PING1 1 +-#define PING0 0 +- +-/* TIFR0 */ +-#define OCF0A 1 +-#define TOV0 0 +- +-/* TIFR1 */ +-#define ICF1 5 +-#define OCF1B 2 +-#define OCF1A 1 +-#define TOV1 0 +- +-/* TIFR2 */ +-#define OCF2A 1 +-#define TOV2 0 +- +-/* EIFR */ +-#define PCIF1 7 +-#define PCIF0 6 +-#define INTF0 0 +- +-/* EIMSK */ +-#define PCIE1 7 +-#define PCIE0 6 +-#define INT0 0 +- +-/* EECR */ +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-/* GTCCR */ +-#define TSM 7 +-#define PSR2 1 +-#define PSR10 0 +- +-/* TCCR0A */ +-#define FOC0A 7 +-#define WGM00 6 +-#define COM0A1 5 +-#define COM0A0 4 +-#define WGM01 3 +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* SPCR */ +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +-/* SPSR */ +-#define SPIF 7 +-#define WCOL 6 +-#define SPI2X 0 +- +-/* ACSR */ +-#define ACD 7 +-#define ACBG 6 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +- +-/* OCDR */ +-#define IDRD 7 +-#define OCD 7 +-#define OCDR6 6 +-#define OCDR5 5 +-#define OCDR4 4 +-#define OCDR3 3 +-#define OCDR2 2 +-#define OCDR1 1 +-#define OCDR0 0 +- +-/* SMCR */ +-#define SM2 3 +-#define SM1 2 +-#define SM0 1 +-#define SE 0 +- +-/* MCUSR */ +-#define JTRF 4 +-#define WDRF 3 +-#define BORF 2 +-#define EXTRF 1 +-#define PORF 0 +- +-/* MCUCR */ +-#define JTD 7 +-#define PUD 4 +-#define IVSEL 1 +-#define IVCE 0 +- +-/* SPMCSR */ +-#define SPMIE 7 +-#define RWWSB 6 +-#define RWWSRE 4 +-#define BLBSET 3 +-#define PGWRT 2 +-#define PGERS 1 +-#define SPMEN 0 +- +-/* WDTCR */ +-#define WDCE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* CLKPR */ +-#define CLKPCE 7 +-#define CLKPS3 3 +-#define CLKPS2 2 +-#define CLKPS1 1 +-#define CLKPS0 0 +- +-/* EICRA */ +-#define ISC01 1 +-#define ISC00 0 +- +-/* PCMSK0 */ +-#define PCINT7 7 +-#define PCINT6 6 +-#define PCINT5 5 +-#define PCINT4 4 +-#define PCINT3 3 +-#define PCINT2 2 +-#define PCINT1 1 +-#define PCINT0 0 +- +-/* PCMSK1 */ +-#define PCINT15 7 +-#define PCINT14 6 +-#define PCINT13 5 +-#define PCINT12 4 +-#define PCINT11 3 +-#define PCINT10 2 +-#define PCINT9 1 +-#define PCINT8 0 +- +-/* TIMSK0 */ +-#define OCIE0A 1 +-#define TOIE0 0 +- +-/* TIMSK1 */ +-#define ICIE1 5 +-#define OCIE1B 2 +-#define OCIE1A 1 +-#define TOIE1 0 +- +-/* TIMSK2 */ +-#define OCIE2A 1 +-#define TOIE2 0 +- +-/* ADCSRA */ +-#define ADEN 7 +-#define ADSC 6 +-#define ADATE 5 +-#define ADIF 4 +-#define ADIE 3 +-#define ADPS2 2 +-#define ADPS1 1 +-#define ADPS0 0 +- +-/* ADCSRB */ +-#define ACME 6 +-#define ADTS2 2 +-#define ADTS1 1 +-#define ADTS0 0 +- +-/* ADMUX */ +-#define REFS1 7 +-#define REFS0 6 +-#define ADLAR 5 +-#define MUX4 4 +-#define MUX3 3 +-#define MUX2 2 +-#define MUX1 1 +-#define MUX0 0 +- +-/* DIDR1 */ +-#define AIN1D 1 +-#define AIN0D 0 +- +-/* DIDR0 */ +-#define ADC7D 7 +-#define ADC6D 6 +-#define ADC5D 5 +-#define ADC4D 4 +-#define ADC3D 3 +-#define ADC2D 2 +-#define ADC1D 1 +-#define ADC0D 0 +- +-/* TCCR1A */ +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define WGM11 1 +-#define WGM10 0 +- +-/* TCCR1B */ +-#define ICNC1 7 +-#define ICES1 6 +-#define WGM13 4 +-#define WGM12 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* TCCR1C */ +-#define FOC1A 7 +-#define FOC1B 6 +- +-/* TCCR2A */ +-#define FOC2A 7 +-#define WGM20 6 +-#define COM2A1 5 +-#define COM2A0 4 +-#define WGM21 3 +-#define CS22 2 +-#define CS21 1 +-#define CS20 0 +- +-/* ASSR */ +-#define EXCLK 4 +-#define AS2 3 +-#define TCN2UB 2 +-#define OCR2UB 1 +-#define TCR2UB 0 +- +-/* USICR */ +-#define USISIE 7 +-#define USIOIE 6 +-#define USIWM1 5 +-#define USIWM0 4 +-#define USICS1 3 +-#define USICS0 2 +-#define USICLK 1 +-#define USITC 0 +- +-/* USISR */ +-#define USISIF 7 +-#define USIOIF 6 +-#define USIPF 5 +-#define USIDC 4 +-#define USICNT3 3 +-#define USICNT2 2 +-#define USICNT1 1 +-#define USICNT0 0 +- +-/* UCSRA */ +-#define RXC 7 +-#define TXC 6 +-#define UDRE 5 +-#define FE 4 +-#define DOR 3 +-#define UPE 2 +-#define U2X 1 +-#define MPCM 0 +- +-/* UCSRB */ +-#define RXCIE 7 +-#define TXCIE 6 +-#define UDRIE 5 +-#define RXEN 4 +-#define TXEN 3 +-#define UCSZ2 2 +-#define RXB8 1 +-#define TXB8 0 +- +-/* UCSRC */ +-#define UMSEL 6 +-#define UPM1 5 +-#define UPM0 4 +-#define USBS 3 +-#define UCSZ1 2 +-#define UCSZ0 1 +-#define UCPOL 0 +- +-/* LCDCRA */ +-#define LCDEN 7 +-#define LCDAB 6 +-#define LCDIF 4 +-#define LCDIE 3 +-#define LCDBD 2 /* Only in Rev. F */ +-#define LCDCCD 1 /* Only in Rev. F */ +-#define LCDBL 0 +- +-/* LCDCRB */ +-#define LCDCS 7 +-#define LCD2B 6 +-#define LCDMUX1 5 +-#define LCDMUX0 4 +-#define LCDPM2 2 +-#define LCDPM1 1 +-#define LCDPM0 0 +- +-/* LCDFRR */ +-#define LCDPS2 6 +-#define LCDPS1 5 +-#define LCDPS0 4 +-#define LCDCD2 2 +-#define LCDCD1 1 +-#define LCDCD0 0 +- +-/* LCDCCR */ +-#define LCDDC2 7 +-#define LCDDC1 6 +-#define LCDDC0 5 +-#define LCDMDT 4 /* Only in Rev. F */ +-#define LCDCC3 3 +-#define LCDCC2 2 +-#define LCDCC1 1 +-#define LCDCC0 0 +- +-/* LCDDR0-18 */ +-#define SEG24 0 +- +-#define SEG23 7 +-#define SEG22 6 +-#define SEG21 5 +-#define SEG20 4 +-#define SEG19 3 +-#define SEG18 2 +-#define SEG17 1 +-#define SEG16 0 +- +-#define SEG15 7 +-#define SEG14 6 +-#define SEG13 5 +-#define SEG12 4 +-#define SEG11 3 +-#define SEG10 2 +-#define SEG9 1 +-#define SEG8 0 +- +-#define SEG7 7 +-#define SEG6 6 +-#define SEG5 5 +-#define SEG4 4 +-#define SEG3 3 +-#define SEG2 2 +-#define SEG1 1 +-#define SEG0 0 +- +-/* Constants */ +-#define SPM_PAGESIZE 128 +-#define RAMEND 0x4FF +-#define XRAMEND RAMEND +-#define E2END 0x1FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x3FFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x94 +-#define SIGNATURE_2 0x05 +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_PIN_CHANGE0 +-#pragma GCC poison SIG_PIN_CHANGE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE2 +-#pragma GCC poison SIG_OVERFLOW2 +-#pragma GCC poison SIG_INPUT_CAPTURE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OUTPUT_COMPARE0 +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_SPI +-#pragma GCC poison SIG_USART_RECV +-#pragma GCC poison SIG_USART_DATA +-#pragma GCC poison SIG_USART_TRANS +-#pragma GCC poison SIG_USI_START +-#pragma GCC poison SIG_USI_OVERFLOW +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_ADC +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_SPM_READY +-#pragma GCC poison SIG_LCD +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +- +-#endif /* _AVR_IOM169_H_ */ ++/* Copyright (c) 2002, 2003, 2004, 2005 ++ Juergen Schilling ++ Eric B. Weddington ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom169.h 2231 2011-03-07 05:06:55Z arcanum $ */ ++ ++/* iom169.h - definitions for ATmega169 */ ++ ++/* This should be up to date with data sheet version 2514J-AVR-12/03. */ ++ ++#ifndef _AVR_IOM169_H_ ++#define _AVR_IOM169_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom169.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* Port A */ ++#define PINA _SFR_IO8(0x00) ++#define DDRA _SFR_IO8(0x01) ++#define PORTA _SFR_IO8(0x02) ++ ++/* Port B */ ++#define PINB _SFR_IO8(0x03) ++#define DDRB _SFR_IO8(0x04) ++#define PORTB _SFR_IO8(0x05) ++ ++/* Port C */ ++#define PINC _SFR_IO8(0x06) ++#define DDRC _SFR_IO8(0x07) ++#define PORTC _SFR_IO8(0x08) ++ ++/* Port D */ ++#define PIND _SFR_IO8(0x09) ++#define DDRD _SFR_IO8(0x0A) ++#define PORTD _SFR_IO8(0x0B) ++ ++/* Port E */ ++#define PINE _SFR_IO8(0x0C) ++#define DDRE _SFR_IO8(0x0D) ++#define PORTE _SFR_IO8(0x0E) ++ ++/* Port F */ ++#define PINF _SFR_IO8(0x0F) ++#define DDRF _SFR_IO8(0x10) ++#define PORTF _SFR_IO8(0x11) ++ ++/* Port G */ ++#define PING _SFR_IO8(0x12) ++#define DDRG _SFR_IO8(0x13) ++#define PORTG _SFR_IO8(0x14) ++ ++/* Timer/Counter 0 interrupt Flag Register */ ++#define TIFR0 _SFR_IO8(0x15) ++ ++/* Timer/Counter 1 interrupt Flag Register */ ++#define TIFR1 _SFR_IO8(0x16) ++ ++/* Timer/Counter 2 interrupt Flag Register */ ++#define TIFR2 _SFR_IO8(0x17) ++ ++/* External Interrupt Flag Register */ ++#define EIFR _SFR_IO8(0x1C) ++ ++/* External Interrupt Mask Register */ ++#define EIMSK _SFR_IO8(0x1D) ++ ++/* General Purpose I/O Register 0 */ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++ ++#define EEDR _SFR_IO8(0X20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0X22) ++ ++/* 6-char sequence denoting where to find the EEPROM registers in memory space. ++ Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM ++ subroutines. ++ First two letters: EECR address. ++ Second two letters: EEDR address. ++ Last two letters: EEAR address. */ ++#define __EEPROM_REG_LOCATIONS__ 1F2021 ++ ++/* General Timer/Counter Control Register */ ++#define GTCCR _SFR_IO8(0x23) ++ ++/* Timer/Counter Control Register A */ ++#define TCCR0A _SFR_IO8(0x24) ++ ++/* Timer/Counter Register */ ++#define TCNT0 _SFR_IO8(0x26) ++ ++/* Output Compare Register A */ ++#define OCR0A _SFR_IO8(0x27) ++ ++/* General Purpose I/O Register 1 */ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++/* General Purpose I/O Register 2 */ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++/* SPI Control Register */ ++#define SPCR _SFR_IO8(0x2C) ++ ++/* SPI Status Register */ ++#define SPSR _SFR_IO8(0x2D) ++ ++/* SPI Data Register */ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Analog Comperator Control and Status Register */ ++#define ACSR _SFR_IO8(0x30) ++ ++/* On-chip Debug Register */ ++#define OCDR _SFR_IO8(0x31) ++ ++/* Sleep Mode Control Register */ ++#define SMCR _SFR_IO8(0x33) ++ ++/* MCU Status Register */ ++#define MCUSR _SFR_IO8(0x34) ++ ++/* MCU Control Rgeister */ ++#define MCUCR _SFR_IO8(0x35) ++ ++/* Store Program Memory Control and Status Register */ ++#define SPMCSR _SFR_IO8(0x37) ++ ++/* Watchdog Timer Control Register */ ++#define WDTCR _SFR_MEM8(0x60) ++ ++/* Clock Prescale Register */ ++#define CLKPR _SFR_MEM8(0x61) ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRLCD 4 ++ ++/* Oscillator Calibration Register */ ++#define OSCCAL _SFR_MEM8(0x66) ++ ++/* External Interrupt Control Register A */ ++#define EICRA _SFR_MEM8(0x69) ++ ++/* Pin Change Mask Register */ ++#define PCMSK _SFR_MEM16(0x6B) ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCMSK1 _SFR_MEM8(0x6C) ++ ++/* Timer/Counter 0 Interrupt Mask Register */ ++#define TIMSK0 _SFR_MEM8(0x6E) ++ ++/* Timer/Counter 1 Interrupt Mask Register */ ++#define TIMSK1 _SFR_MEM8(0x6F) ++ ++/* Timer/Counter 2 Interrupt Mask Register */ ++#define TIMSK2 _SFR_MEM8(0x70) ++ ++/* ADC Data Register */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++/* ADC Control and Status Register A */ ++#define ADCSRA _SFR_MEM8(0x7A) ++ ++/* ADC Control and Status Register B */ ++#define ADCSRB _SFR_MEM8(0x7B) ++ ++/* ADC Multiplex Selection Register */ ++#define ADMUX _SFR_MEM8(0x7C) ++ ++/* NOTE: DIDR0 and DIDR1 are swapped in the register summary of the data sheet ++ (2514D-AVR-01/03), but seem to be correct in the discussions of the ++ registers. */ ++ ++/* Digital Input Disable Register 0 */ ++#define DIDR0 _SFR_MEM8(0x7E) ++ ++/* Digital Input Disable Register 1 */ ++#define DIDR1 _SFR_MEM8(0x7F) ++ ++/* Timer/Counter1 Control Register A */ ++#define TCCR1A _SFR_MEM8(0x80) ++ ++/* Timer/Counter1 Control Register B */ ++#define TCCR1B _SFR_MEM8(0x81) ++ ++/* Timer/Counter1 Control Register C */ ++#define TCCR1C _SFR_MEM8(0x82) ++ ++/* Timer/Counter1 Register */ ++#define TCNT1 _SFR_MEM16(0x84) ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Timer/Counter1 Input Capture Register */ ++#define ICR1 _SFR_MEM16(0x86) ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Timer/Counter1 Output Compare Register A */ ++#define OCR1A _SFR_MEM16(0x88) ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Timer/Counter1 Output Compare Registare B */ ++#define OCR1B _SFR_MEM16(0x8A) ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Timer/Counter2 Control Register A */ ++#define TCCR2A _SFR_MEM8(0xB0) ++ ++/* Timer/Counter2 Register */ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++/* Timer/Counter2 Output Compare Register */ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++/* Asynchronous Status Register */ ++#define ASSR _SFR_MEM8(0xB6) ++ ++/* USI Control Register */ ++#define USICR _SFR_MEM8(0xB8) ++ ++/* USI Status Register */ ++#define USISR _SFR_MEM8(0xB9) ++ ++/* USI Data Register */ ++#define USIDR _SFR_MEM8(0xBA) ++ ++/* USART0 Control and Status Register A */ ++#define UCSRA _SFR_MEM8(0xC0) ++ ++/* USART0 Control and Status Register B */ ++#define UCSRB _SFR_MEM8(0xC1) ++ ++/* USART0 Control and Status Register C */ ++#define UCSRC _SFR_MEM8(0xC2) ++ ++/* USART0 Baud Rate Register */ ++#define UBRR _SFR_MEM16(0xC4) ++#define UBRRL _SFR_MEM8(0xC4) ++#define UBRRH _SFR_MEM8(0xC5) ++ ++/* USART0 I/O Data Register */ ++#define UDR _SFR_MEM8(0xC6) ++ ++/* LCD Control and Status Register A */ ++#define LCDCRA _SFR_MEM8(0xE4) ++ ++/* LCD Control and Status Register B */ ++#define LCDCRB _SFR_MEM8(0xE5) ++ ++/* LCD Frame Rate Register */ ++#define LCDFRR _SFR_MEM8(0xE6) ++ ++/* LCD Contrast Control Register */ ++#define LCDCCR _SFR_MEM8(0xE7) ++ ++/* LCD Memory mapping */ ++#define LCDDR0 _SFR_MEM8(0xEC) ++#define LCDDR1 _SFR_MEM8(0xED) ++#define LCDDR2 _SFR_MEM8(0xEE) ++#define LCDDR3 _SFR_MEM8(0xEF) ++#define LCDDR5 _SFR_MEM8(0xF1) ++#define LCDDR6 _SFR_MEM8(0xF2) ++#define LCDDR7 _SFR_MEM8(0xF3) ++#define LCDDR8 _SFR_MEM8(0xF4) ++#define LCDDR10 _SFR_MEM8(0xF6) ++#define LCDDR11 _SFR_MEM8(0xF7) ++#define LCDDR12 _SFR_MEM8(0xF8) ++#define LCDDR13 _SFR_MEM8(0xF9) ++#define LCDDR15 _SFR_MEM8(0xFB) ++#define LCDDR16 _SFR_MEM8(0xFC) ++#define LCDDR17 _SFR_MEM8(0xFD) ++#define LCDDR18 _SFR_MEM8(0xFE) ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) ++#define SIG_PIN_CHANGE0 _VECTOR(2) ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect_num 3 ++#define PCINT1_vect _VECTOR(3) ++#define SIG_PIN_CHANGE1 _VECTOR(3) ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect_num 4 ++#define TIMER2_COMP_vect _VECTOR(4) ++#define SIG_OUTPUT_COMPARE2 _VECTOR(4) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 5 ++#define TIMER2_OVF_vect _VECTOR(5) ++#define SIG_OVERFLOW2 _VECTOR(5) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 6 ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define SIG_INPUT_CAPTURE1 _VECTOR(6) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 7 ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(7) ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect_num 8 ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(8) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 9 ++#define TIMER1_OVF_vect _VECTOR(9) ++#define SIG_OVERFLOW1 _VECTOR(9) ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect_num 10 ++#define TIMER0_COMP_vect _VECTOR(10) ++#define SIG_OUTPUT_COMPARE0 _VECTOR(10) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 11 ++#define TIMER0_OVF_vect _VECTOR(11) ++#define SIG_OVERFLOW0 _VECTOR(11) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 12 ++#define SPI_STC_vect _VECTOR(12) ++#define SIG_SPI _VECTOR(12) ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect_num 13 ++#define USART0_RX_vect _VECTOR(13) ++#define SIG_USART_RECV _VECTOR(13) ++ ++/* USART0 Data register Empty */ ++#define USART0_UDRE_vect_num 14 ++#define USART0_UDRE_vect _VECTOR(14) ++#define SIG_USART_DATA _VECTOR(14) ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect_num 15 ++#define USART0_TX_vect _VECTOR(15) ++#define SIG_USART_TRANS _VECTOR(15) ++ ++/* USI Start Condition */ ++#define USI_START_vect_num 16 ++#define USI_START_vect _VECTOR(16) ++#define SIG_USI_START _VECTOR(16) ++ ++/* USI Overflow */ ++#define USI_OVERFLOW_vect_num 17 ++#define USI_OVERFLOW_vect _VECTOR(17) ++#define SIG_USI_OVERFLOW _VECTOR(17) ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect_num 18 ++#define ANALOG_COMP_vect _VECTOR(18) ++#define SIG_COMPARATOR _VECTOR(18) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 19 ++#define ADC_vect _VECTOR(19) ++#define SIG_ADC _VECTOR(19) ++ ++/* EEPROM Ready */ ++#define EE_READY_vect_num 20 ++#define EE_READY_vect _VECTOR(20) ++#define SIG_EEPROM_READY _VECTOR(20) ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect_num 21 ++#define SPM_READY_vect _VECTOR(21) ++#define SIG_SPM_READY _VECTOR(21) ++ ++/* LCD Start of Frame */ ++#define LCD_vect_num 22 ++#define LCD_vect _VECTOR(22) ++#define SIG_LCD _VECTOR(22) ++ ++#define _VECTORS_SIZE 92 ++ ++/* Bit numbers */ ++ ++/* ++ PA7 = SEG3 ++ PA6 = SEG2 ++ PA5 = SEG1 ++ PA4 = SEG0 ++ PA3 = COM3 ++ PA2 = COM2 ++ PA1 = COM1 ++ PA0 = COM0 ++*/ ++ ++/* PORTA */ ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++/* DDRA */ ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++/* PINA */ ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++/* ++ PB7 = OC2A / PCINT15 ++ PB6 = OC1B / PCINT14 ++ PB5 = OC1A / PCINT13 ++ PB4 = OC0A / PCINT12 ++ PB3 = MISO / PCINT11 ++ PB2 = MOSI / PCINT10 ++ PB1 = SCK / PCINT9 ++ PB0 = SS# / PCINT8 ++ */ ++ ++/* PORTB */ ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* DDRB */ ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* PINB */ ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* ++ PC7 = SEG5 ++ PC6 = SEG6 ++ PC5 = SEG7 ++ PC4 = SEG8 ++ PC3 = SEG9 ++ PC2 = SEG10 ++ PC1 = SEG11 ++ PC0 = SEG12 ++*/ ++ ++/* PORTC */ ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++/* DDRC */ ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++/* PINC */ ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++/* ++ PD7 = SEG15 ++ PD6 = SEG16 ++ PD5 = SEG17 ++ PD4 = SEG18 ++ PD3 = SEG19 ++ PD2 = SEG20 ++ PD1 = INT0 / SEG21 ++ PD0 = ICP / SEG22 ++ */ ++ ++/* PORTD */ ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* DDRD */ ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++/* PIND */ ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++/* ++ PE7 = CLK0 / PCINT7 ++ PE6 = DO / PCINT6 ++ PE5 = DI / SDA / PCINT5 ++ PE4 = USCK / SCL / PCINT4 ++ PE3 = AIN1 / PCINT3 ++ PE2 = XCK / AIN0 / PCINT2 ++ PE1 = TXD / PCINT1 ++ PE0 = RXD / PCINT0 ++ */ ++ ++/* PORTE */ ++#define PE7 7 ++#define PE6 6 ++#define PE5 5 ++#define PE4 4 ++#define PE3 3 ++#define PE2 2 ++#define PE1 1 ++#define PE0 0 ++ ++/* DDRE */ ++#define DDE7 7 ++#define DDE6 6 ++#define DDE5 5 ++#define DDE4 4 ++#define DDE3 3 ++#define DDE2 2 ++#define DDE1 1 ++#define DDE0 0 ++ ++/* PINE */ ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++/* ++ PF7 = ADC7 / TDI ++ PF6 = ADC6 / TDO ++ PF5 = ADC5 / TMS ++ PF4 = ADC4 / TCK ++ PF3 = ADC3 ++ PF2 = ADC2 ++ PF1 = ADC1 ++ PF0 = ADC0 ++ */ ++ ++/* PORTF */ ++#define PF7 7 ++#define PF6 6 ++#define PF5 5 ++#define PF4 4 ++#define PF3 3 ++#define PF2 2 ++#define PF1 1 ++#define PF0 0 ++ ++/* DDRF */ ++#define DDF7 7 ++#define DDF6 6 ++#define DDF5 5 ++#define DDF4 4 ++#define DDF3 3 ++#define DDF2 2 ++#define DDF1 1 ++#define DDF0 0 ++ ++/* PINF */ ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++/* ++ PG5 = RESET# ++ PG4 = T0 / SEG23 ++ PG3 = T1 / SEG24 ++ PG2 = SEG4 ++ PG1 = SEG13 ++ PG0 = SEG14 ++ */ ++ ++/* PORTG */ ++#define PG4 4 ++#define PG3 3 ++#define PG2 2 ++#define PG1 1 ++#define PG0 0 ++ ++/* DDRG */ ++#define DDG4 4 ++#define DDG3 3 ++#define DDG2 2 ++#define DDG1 1 ++#define DDG0 0 ++ ++/* PING */ ++#define PING5 5 ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++/* TIFR0 */ ++#define OCF0A 1 ++#define TOV0 0 ++ ++/* TIFR1 */ ++#define ICF1 5 ++#define OCF1B 2 ++#define OCF1A 1 ++#define TOV1 0 ++ ++/* TIFR2 */ ++#define OCF2A 1 ++#define TOV2 0 ++ ++/* EIFR */ ++#define PCIF1 7 ++#define PCIF0 6 ++#define INTF0 0 ++ ++/* EIMSK */ ++#define PCIE1 7 ++#define PCIE0 6 ++#define INT0 0 ++ ++/* EECR */ ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++/* GTCCR */ ++#define TSM 7 ++#define PSR2 1 ++#define PSR10 0 ++ ++/* TCCR0A */ ++#define FOC0A 7 ++#define WGM00 6 ++#define COM0A1 5 ++#define COM0A0 4 ++#define WGM01 3 ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* SPCR */ ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++/* SPSR */ ++#define SPIF 7 ++#define WCOL 6 ++#define SPI2X 0 ++ ++/* ACSR */ ++#define ACD 7 ++#define ACBG 6 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++/* OCDR */ ++#define IDRD 7 ++#define OCD 7 ++#define OCDR6 6 ++#define OCDR5 5 ++#define OCDR4 4 ++#define OCDR3 3 ++#define OCDR2 2 ++#define OCDR1 1 ++#define OCDR0 0 ++ ++/* SMCR */ ++#define SM2 3 ++#define SM1 2 ++#define SM0 1 ++#define SE 0 ++ ++/* MCUSR */ ++#define JTRF 4 ++#define WDRF 3 ++#define BORF 2 ++#define EXTRF 1 ++#define PORF 0 ++ ++/* MCUCR */ ++#define JTD 7 ++#define PUD 4 ++#define IVSEL 1 ++#define IVCE 0 ++ ++/* SPMCSR */ ++#define SPMIE 7 ++#define RWWSB 6 ++#define RWWSRE 4 ++#define BLBSET 3 ++#define PGWRT 2 ++#define PGERS 1 ++#define SPMEN 0 ++ ++/* WDTCR */ ++#define WDCE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* CLKPR */ ++#define CLKPCE 7 ++#define CLKPS3 3 ++#define CLKPS2 2 ++#define CLKPS1 1 ++#define CLKPS0 0 ++ ++/* EICRA */ ++#define ISC01 1 ++#define ISC00 0 ++ ++/* PCMSK0 */ ++#define PCINT7 7 ++#define PCINT6 6 ++#define PCINT5 5 ++#define PCINT4 4 ++#define PCINT3 3 ++#define PCINT2 2 ++#define PCINT1 1 ++#define PCINT0 0 ++ ++/* PCMSK1 */ ++#define PCINT15 7 ++#define PCINT14 6 ++#define PCINT13 5 ++#define PCINT12 4 ++#define PCINT11 3 ++#define PCINT10 2 ++#define PCINT9 1 ++#define PCINT8 0 ++ ++/* TIMSK0 */ ++#define OCIE0A 1 ++#define TOIE0 0 ++ ++/* TIMSK1 */ ++#define ICIE1 5 ++#define OCIE1B 2 ++#define OCIE1A 1 ++#define TOIE1 0 ++ ++/* TIMSK2 */ ++#define OCIE2A 1 ++#define TOIE2 0 ++ ++/* ADCSRA */ ++#define ADEN 7 ++#define ADSC 6 ++#define ADATE 5 ++#define ADIF 4 ++#define ADIE 3 ++#define ADPS2 2 ++#define ADPS1 1 ++#define ADPS0 0 ++ ++/* ADCSRB */ ++#define ACME 6 ++#define ADTS2 2 ++#define ADTS1 1 ++#define ADTS0 0 ++ ++/* ADMUX */ ++#define REFS1 7 ++#define REFS0 6 ++#define ADLAR 5 ++#define MUX4 4 ++#define MUX3 3 ++#define MUX2 2 ++#define MUX1 1 ++#define MUX0 0 ++ ++/* DIDR1 */ ++#define AIN1D 1 ++#define AIN0D 0 ++ ++/* DIDR0 */ ++#define ADC7D 7 ++#define ADC6D 6 ++#define ADC5D 5 ++#define ADC4D 4 ++#define ADC3D 3 ++#define ADC2D 2 ++#define ADC1D 1 ++#define ADC0D 0 ++ ++/* TCCR1A */ ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define WGM11 1 ++#define WGM10 0 ++ ++/* TCCR1B */ ++#define ICNC1 7 ++#define ICES1 6 ++#define WGM13 4 ++#define WGM12 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* TCCR1C */ ++#define FOC1A 7 ++#define FOC1B 6 ++ ++/* TCCR2A */ ++#define FOC2A 7 ++#define WGM20 6 ++#define COM2A1 5 ++#define COM2A0 4 ++#define WGM21 3 ++#define CS22 2 ++#define CS21 1 ++#define CS20 0 ++ ++/* ASSR */ ++#define EXCLK 4 ++#define AS2 3 ++#define TCN2UB 2 ++#define OCR2UB 1 ++#define TCR2UB 0 ++ ++/* USICR */ ++#define USISIE 7 ++#define USIOIE 6 ++#define USIWM1 5 ++#define USIWM0 4 ++#define USICS1 3 ++#define USICS0 2 ++#define USICLK 1 ++#define USITC 0 ++ ++/* USISR */ ++#define USISIF 7 ++#define USIOIF 6 ++#define USIPF 5 ++#define USIDC 4 ++#define USICNT3 3 ++#define USICNT2 2 ++#define USICNT1 1 ++#define USICNT0 0 ++ ++/* UCSRA */ ++#define RXC 7 ++#define TXC 6 ++#define UDRE 5 ++#define FE 4 ++#define DOR 3 ++#define UPE 2 ++#define U2X 1 ++#define MPCM 0 ++ ++/* UCSRB */ ++#define RXCIE 7 ++#define TXCIE 6 ++#define UDRIE 5 ++#define RXEN 4 ++#define TXEN 3 ++#define UCSZ2 2 ++#define RXB8 1 ++#define TXB8 0 ++ ++/* UCSRC */ ++#define UMSEL 6 ++#define UPM1 5 ++#define UPM0 4 ++#define USBS 3 ++#define UCSZ1 2 ++#define UCSZ0 1 ++#define UCPOL 0 ++ ++/* LCDCRA */ ++#define LCDEN 7 ++#define LCDAB 6 ++#define LCDIF 4 ++#define LCDIE 3 ++#define LCDBD 2 /* Only in Rev. F */ ++#define LCDCCD 1 /* Only in Rev. F */ ++#define LCDBL 0 ++ ++/* LCDCRB */ ++#define LCDCS 7 ++#define LCD2B 6 ++#define LCDMUX1 5 ++#define LCDMUX0 4 ++#define LCDPM2 2 ++#define LCDPM1 1 ++#define LCDPM0 0 ++ ++/* LCDFRR */ ++#define LCDPS2 6 ++#define LCDPS1 5 ++#define LCDPS0 4 ++#define LCDCD2 2 ++#define LCDCD1 1 ++#define LCDCD0 0 ++ ++/* LCDCCR */ ++#define LCDDC2 7 ++#define LCDDC1 6 ++#define LCDDC0 5 ++#define LCDMDT 4 /* Only in Rev. F */ ++#define LCDCC3 3 ++#define LCDCC2 2 ++#define LCDCC1 1 ++#define LCDCC0 0 ++ ++/* LCDDR0-18 */ ++#define SEG24 0 ++ ++#define SEG23 7 ++#define SEG22 6 ++#define SEG21 5 ++#define SEG20 4 ++#define SEG19 3 ++#define SEG18 2 ++#define SEG17 1 ++#define SEG16 0 ++ ++#define SEG15 7 ++#define SEG14 6 ++#define SEG13 5 ++#define SEG12 4 ++#define SEG11 3 ++#define SEG10 2 ++#define SEG9 1 ++#define SEG8 0 ++ ++#define SEG7 7 ++#define SEG6 6 ++#define SEG5 5 ++#define SEG4 4 ++#define SEG3 3 ++#define SEG2 2 ++#define SEG1 1 ++#define SEG0 0 ++ ++/* Constants */ ++#define SPM_PAGESIZE 128 ++#define RAMSTART 0x100 ++#define RAMEND 0x4FF ++#define XRAMEND RAMEND ++#define E2END 0x1FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x3FFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x05 ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_PIN_CHANGE0 ++#pragma GCC poison SIG_PIN_CHANGE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE2 ++#pragma GCC poison SIG_OVERFLOW2 ++#pragma GCC poison SIG_INPUT_CAPTURE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OUTPUT_COMPARE0 ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_SPI ++#pragma GCC poison SIG_USART_RECV ++#pragma GCC poison SIG_USART_DATA ++#pragma GCC poison SIG_USART_TRANS ++#pragma GCC poison SIG_USI_START ++#pragma GCC poison SIG_USI_OVERFLOW ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_ADC ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_SPM_READY ++#pragma GCC poison SIG_LCD ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++ ++#endif /* _AVR_IOM169_H_ */ +diff --git a/include/avr/iom169a.h b/include/avr/iom169a.h +new file mode 100644 +index 0000000..5c42fb6 +--- /dev/null ++++ b/include/avr/iom169a.h +@@ -0,0 +1,44 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2011 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++#include "iom169.h" ++ ++#ifdef PCIE1 ++ #undef PCIE1 ++ #define PCIE1 5 ++#endif ++ ++#ifdef PCIE0 ++ #undef PCIE0 ++ #define PCIE0 4 ++#endif +diff --git a/include/avr/iom169p.h b/include/avr/iom169p.h +index 52148db..4b0a354 100644 +--- a/include/avr/iom169p.h ++++ b/include/avr/iom169p.h +@@ -1,1084 +1,1085 @@ +-/* Copyright (c) 2002, 2003, 2004, 2005, 2006 +- Juergen Schilling +- Eric B. Weddington +- Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom169p.h 2231 2011-03-07 05:06:55Z arcanum $ */ +- +-/* iom169p.h - definitions for ATmega169P */ +- +-#ifndef _AVR_IOM169P_H_ +-#define _AVR_IOM169P_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom169p.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* Port A */ +-#define PINA _SFR_IO8(0x00) +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-#define PORTA _SFR_IO8(0x02) +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-/* Port B */ +-#define PINB _SFR_IO8(0x03) +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-#define PORTB _SFR_IO8(0x05) +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* Port C */ +-#define PINC _SFR_IO8(0x06) +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-#define PORTC _SFR_IO8(0x08) +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-/* Port D */ +-#define PIND _SFR_IO8(0x09) +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* Port E */ +-#define PINE _SFR_IO8(0x0C) +-#define PINE7 7 +-#define PINE6 6 +-#define PINE5 5 +-#define PINE4 4 +-#define PINE3 3 +-#define PINE2 2 +-#define PINE1 1 +-#define PINE0 0 +- +-#define DDRE _SFR_IO8(0x0D) +-#define DDE7 7 +-#define DDE6 6 +-#define DDE5 5 +-#define DDE4 4 +-#define DDE3 3 +-#define DDE2 2 +-#define DDE1 1 +-#define DDE0 0 +- +-#define PORTE _SFR_IO8(0x0E) +-#define PE7 7 +-#define PE6 6 +-#define PE5 5 +-#define PE4 4 +-#define PE3 3 +-#define PE2 2 +-#define PE1 1 +-#define PE0 0 +- +-/* Port F */ +-#define PINF _SFR_IO8(0x0F) +-#define PINF7 7 +-#define PINF6 6 +-#define PINF5 5 +-#define PINF4 4 +-#define PINF3 3 +-#define PINF2 2 +-#define PINF1 1 +-#define PINF0 0 +- +-#define DDRF _SFR_IO8(0x10) +-#define DDF7 7 +-#define DDF6 6 +-#define DDF5 5 +-#define DDF4 4 +-#define DDF3 3 +-#define DDF2 2 +-#define DDF1 1 +-#define DDF0 0 +- +-#define PORTF _SFR_IO8(0x11) +-#define PF7 7 +-#define PF6 6 +-#define PF5 5 +-#define PF4 4 +-#define PF3 3 +-#define PF2 2 +-#define PF1 1 +-#define PF0 0 +- +-/* Port G */ +-#define PING _SFR_IO8(0x12) +-#define PING5 5 +-#define PING4 4 +-#define PING3 3 +-#define PING2 2 +-#define PING1 1 +-#define PING0 0 +- +-#define DDRG _SFR_IO8(0x13) +-#define DDG4 4 +-#define DDG3 3 +-#define DDG2 2 +-#define DDG1 1 +-#define DDG0 0 +- +-#define PORTG _SFR_IO8(0x14) +-#define PG4 4 +-#define PG3 3 +-#define PG2 2 +-#define PG1 1 +-#define PG0 0 +- +-/* Timer/Counter 0 interrupt Flag Register */ +-#define TIFR0 _SFR_IO8(0x15) +-#define OCF0A 1 +-#define TOV0 0 +- +-/* Timer/Counter 1 interrupt Flag Register */ +-#define TIFR1 _SFR_IO8(0x16) +-#define ICF1 5 +-#define OCF1B 2 +-#define OCF1A 1 +-#define TOV1 0 +- +-/* Timer/Counter 2 interrupt Flag Register */ +-#define TIFR2 _SFR_IO8(0x17) +-#define OCF2A 1 +-#define TOV2 0 +- +-/* External Interrupt Flag Register */ +-#define EIFR _SFR_IO8(0x1C) +-#define PCIF1 7 +-#define PCIF0 6 +-#define INTF0 0 +- +-/* External Interrupt Mask Register */ +-#define EIMSK _SFR_IO8(0x1D) +-#define PCIE1 7 +-#define PCIE0 6 +-#define INT0 0 +- +-/* General Purpose I/O Register 0 */ +-#define GPIOR0 _SFR_IO8(0x1E) +- +-#define EECR _SFR_IO8(0x1F) +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-#define EEDR _SFR_IO8(0X20) +- +-/* Combine EEARL and EEARH */ +-#define EEAR _SFR_IO16(0x21) +-#define EEARL _SFR_IO8(0x21) +-#define EEARH _SFR_IO8(0X22) +- +-/* 6-char sequence denoting where to find the EEPROM registers in memory space. +- Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM +- subroutines. +- First two letters: EECR address. +- Second two letters: EEDR address. +- Last two letters: EEAR address. */ +-#define __EEPROM_REG_LOCATIONS__ 1F2021 +- +-/* General Timer/Counter Control Register */ +-#define GTCCR _SFR_IO8(0x23) +-#define TSM 7 +-#define PSR2 1 +-#define PSR10 0 +- +-/* Timer/Counter Control Register A */ +-#define TCCR0A _SFR_IO8(0x24) +-#define FOC0A 7 +-#define WGM00 6 +-#define COM0A1 5 +-#define COM0A0 4 +-#define WGM01 3 +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* Timer/Counter Register */ +-#define TCNT0 _SFR_IO8(0x26) +- +-/* Output Compare Register A */ +-#define OCR0A _SFR_IO8(0x27) +- +-/* General Purpose I/O Register 1 */ +-#define GPIOR1 _SFR_IO8(0x2A) +- +-/* General Purpose I/O Register 2 */ +-#define GPIOR2 _SFR_IO8(0x2B) +- +-/* SPI Control Register */ +-#define SPCR _SFR_IO8(0x2C) +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +-/* SPI Status Register */ +-#define SPSR _SFR_IO8(0x2D) +-#define SPIF 7 +-#define WCOL 6 +-#define SPI2X 0 +- +-/* SPI Data Register */ +-#define SPDR _SFR_IO8(0x2E) +- +-/* Analog Comperator Control and Status Register */ +-#define ACSR _SFR_IO8(0x30) +-#define ACD 7 +-#define ACBG 6 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +- +-/* On-chip Debug Register */ +-#define OCDR _SFR_IO8(0x31) +-#define IDRD 7 +-#define OCDR7 7 +-#define OCDR6 6 +-#define OCDR5 5 +-#define OCDR4 4 +-#define OCDR3 3 +-#define OCDR2 2 +-#define OCDR1 1 +-#define OCDR0 0 +- +-/* Sleep Mode Control Register */ +-#define SMCR _SFR_IO8(0x33) +-#define SM2 3 +-#define SM1 2 +-#define SM0 1 +-#define SE 0 +- +-/* MCU Status Register */ +-#define MCUSR _SFR_IO8(0x34) +-#define JTRF 4 +-#define WDRF 3 +-#define BORF 2 +-#define EXTRF 1 +-#define PORF 0 +- +-/* MCU Control Rgeister */ +-#define MCUCR _SFR_IO8(0x35) +-#define JTD 7 +-#define PUD 4 +-#define IVSEL 1 +-#define IVCE 0 +- +-/* Store Program Memory Control and Status Register */ +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMIE 7 +-#define RWWSB 6 +-#define RWWSRE 4 +-#define BLBSET 3 +-#define PGWRT 2 +-#define PGERS 1 +-#define SPMEN 0 +- +-/* Watchdog Timer Control Register */ +-#define WDTCR _SFR_MEM8(0x60) +-#define WDCE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* Clock Prescale Register */ +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPCE 7 +-#define CLKPS3 3 +-#define CLKPS2 2 +-#define CLKPS1 1 +-#define CLKPS0 0 +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM1 3 +-#define PRLCD 4 +- +-/* Oscillator Calibration Register */ +-#define OSCCAL _SFR_MEM8(0x66) +- +-/* External Interrupt Control Register A */ +-#define EICRA _SFR_MEM8(0x69) +-#define ISC01 1 +-#define ISC00 0 +- +-/* Pin Change Mask Register */ +-#define PCMSK _SFR_MEM16(0x6B) +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT7 7 +-#define PCINT6 6 +-#define PCINT5 5 +-#define PCINT4 4 +-#define PCINT3 3 +-#define PCINT2 2 +-#define PCINT1 1 +-#define PCINT0 0 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT15 7 +-#define PCINT14 6 +-#define PCINT13 5 +-#define PCINT12 4 +-#define PCINT11 3 +-#define PCINT10 2 +-#define PCINT9 1 +-#define PCINT8 0 +- +-/* Timer/Counter 0 Interrupt Mask Register */ +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define OCIE0A 1 +-#define TOIE0 0 +- +-/* Timer/Counter 1 Interrupt Mask Register */ +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define ICIE1 5 +-#define OCIE1B 2 +-#define OCIE1A 1 +-#define TOIE1 0 +- +-/* Timer/Counter 2 Interrupt Mask Register */ +-#define TIMSK2 _SFR_MEM8(0x70) +-#define OCIE2A 1 +-#define TOIE2 0 +- +-/* ADC Data Register */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +-#define ADCL _SFR_MEM8(0x78) +-#define ADCH _SFR_MEM8(0x79) +- +-/* ADC Control and Status Register A */ +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADEN 7 +-#define ADSC 6 +-#define ADATE 5 +-#define ADIF 4 +-#define ADIE 3 +-#define ADPS2 2 +-#define ADPS1 1 +-#define ADPS0 0 +- +- +-/* ADC Control and Status Register B */ +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ACME 6 +-#define ADTS2 2 +-#define ADTS1 1 +-#define ADTS0 0 +- +-/* ADC Multiplex Selection Register */ +-#define ADMUX _SFR_MEM8(0x7C) +-/* ADMUX */ +-#define REFS1 7 +-#define REFS0 6 +-#define ADLAR 5 +-#define MUX4 4 +-#define MUX3 3 +-#define MUX2 2 +-#define MUX1 1 +-#define MUX0 0 +- +-/* Digital Input Disable Register 0 */ +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC7D 7 +-#define ADC6D 6 +-#define ADC5D 5 +-#define ADC4D 4 +-#define ADC3D 3 +-#define ADC2D 2 +-#define ADC1D 1 +-#define ADC0D 0 +- +-/* Digital Input Disable Register 1 */ +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN1D 1 +-#define AIN0D 0 +- +-/* Timer/Counter1 Control Register A */ +-#define TCCR1A _SFR_MEM8(0x80) +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define WGM11 1 +-#define WGM10 0 +- +-/* Timer/Counter1 Control Register B */ +-#define TCCR1B _SFR_MEM8(0x81) +-#define ICNC1 7 +-#define ICES1 6 +-#define WGM13 4 +-#define WGM12 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* Timer/Counter1 Control Register C */ +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1A 7 +-#define FOC1B 6 +- +-/* Timer/Counter1 Register */ +-#define TCNT1 _SFR_MEM16(0x84) +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1H _SFR_MEM8(0x85) +- +-/* Timer/Counter1 Input Capture Register */ +-#define ICR1 _SFR_MEM16(0x86) +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1H _SFR_MEM8(0x87) +- +-/* Timer/Counter1 Output Compare Register A */ +-#define OCR1A _SFR_MEM16(0x88) +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AH _SFR_MEM8(0x89) +- +-/* Timer/Counter1 Output Compare Registare B */ +-#define OCR1B _SFR_MEM16(0x8A) +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BH _SFR_MEM8(0x8B) +- +-/* Timer/Counter2 Control Register A */ +-#define TCCR2A _SFR_MEM8(0xB0) +-#define FOC2A 7 +-#define WGM20 6 +-#define COM2A1 5 +-#define COM2A0 4 +-#define WGM21 3 +-#define CS22 2 +-#define CS21 1 +-#define CS20 0 +- +-/* Timer/Counter2 Register */ +-#define TCNT2 _SFR_MEM8(0xB2) +- +-/* Timer/Counter2 Output Compare Register */ +-#define OCR2A _SFR_MEM8(0xB3) +- +-/* Asynchronous Status Register */ +-#define ASSR _SFR_MEM8(0xB6) +-#define EXCLK 4 +-#define AS2 3 +-#define TCN2UB 2 +-#define OCR2UB 1 +-#define TCR2UB 0 +- +-/* USI Control Register */ +-#define USICR _SFR_MEM8(0xB8) +-#define USISIE 7 +-#define USIOIE 6 +-#define USIWM1 5 +-#define USIWM0 4 +-#define USICS1 3 +-#define USICS0 2 +-#define USICLK 1 +-#define USITC 0 +- +-/* USI Status Register */ +-#define USISR _SFR_MEM8(0xB9) +-#define USISIF 7 +-#define USIOIF 6 +-#define USIPF 5 +-#define USIDC 4 +-#define USICNT3 3 +-#define USICNT2 2 +-#define USICNT1 1 +-#define USICNT0 0 +- +-/* USI Data Register */ +-#define USIDR _SFR_MEM8(0xBA) +- +-/* USART0 Control and Status Register A */ +-#define UCSR0A _SFR_MEM8(0xC0) +-#define RXC0 7 +-#define TXC0 6 +-#define UDRE0 5 +-#define FE0 4 +-#define DOR0 3 +-#define UPE0 2 +-#define U2X0 1 +-#define MPCM0 0 +- +-/* USART0 Control and Status Register B */ +-#define UCSR0B _SFR_MEM8(0xC1) +-#define RXCIE0 7 +-#define TXCIE0 6 +-#define UDRIE0 5 +-#define RXEN0 4 +-#define TXEN0 3 +-#define UCSZ02 2 +-#define RXB80 1 +-#define TXB80 0 +- +-/* USART0 Control and Status Register C */ +-#define UCSR0C _SFR_MEM8(0xC2) +-#define UMSEL0 6 +-#define UPM01 5 +-#define UPM00 4 +-#define USBS0 3 +-#define UCSZ01 2 +-#define UCSZ00 1 +-#define UCPOL0 0 +- +-/* USART0 Baud Rate Register */ +-#define UBRR0 _SFR_MEM16(0xC4) +-#define UBRR0L _SFR_MEM8(0xC4) +-#define UBRR0H _SFR_MEM8(0xC5) +- +-/* USART0 I/O Data Register */ +-#define UDR0 _SFR_MEM8(0xC6) +- +-/* LCD Control and Status Register A */ +-#define LCDCRA _SFR_MEM8(0xE4) +-#define LCDEN 7 +-#define LCDAB 6 +-#define LCDIF 4 +-#define LCDIE 3 +-#define LCDBD 2 +-#define LCDCCD 1 +-#define LCDBL 0 +- +-/* LCD Control and Status Register B */ +-#define LCDCRB _SFR_MEM8(0xE5) +-#define LCDCS 7 +-#define LCD2B 6 +-#define LCDMUX1 5 +-#define LCDMUX0 4 +-#define LCDPM2 2 +-#define LCDPM1 1 +-#define LCDPM0 0 +- +-/* LCD Frame Rate Register */ +-#define LCDFRR _SFR_MEM8(0xE6) +-#define LCDPS2 6 +-#define LCDPS1 5 +-#define LCDPS0 4 +-#define LCDCD2 2 +-#define LCDCD1 1 +-#define LCDCD0 0 +- +-/* LCD Contrast Control Register */ +-#define LCDCCR _SFR_MEM8(0xE7) +-#define LCDDC2 7 +-#define LCDDC1 6 +-#define LCDDC0 5 +-#define LCDMDT 4 +-#define LCDCC3 3 +-#define LCDCC2 2 +-#define LCDCC1 1 +-#define LCDCC0 0 +- +-/* LCD Memory mapping */ +-#define LCDDR0 _SFR_MEM8(0xEC) +-#define SEG007 7 +-#define SEG006 6 +-#define SEG005 5 +-#define SEG004 4 +-#define SEG003 3 +-#define SEG002 2 +-#define SEG001 1 +-#define SEG000 0 +- +-#define LCDDR1 _SFR_MEM8(0xED) +-#define SEG015 7 +-#define SEG014 6 +-#define SEG013 5 +-#define SEG012 4 +-#define SEG011 3 +-#define SEG010 2 +-#define SEG009 1 +-#define SEG008 0 +- +-#define LCDDR2 _SFR_MEM8(0xEE) +-#define SEG023 7 +-#define SEG022 6 +-#define SEG021 5 +-#define SEG020 4 +-#define SEG019 3 +-#define SEG018 2 +-#define SEG017 1 +-#define SEG016 0 +- +-#define LCDDR3 _SFR_MEM8(0xEF) +-#define SEG024 0 +- +-#define LCDDR5 _SFR_MEM8(0xF1) +-#define SEG107 7 +-#define SEG106 6 +-#define SEG105 5 +-#define SEG104 4 +-#define SEG103 3 +-#define SEG102 2 +-#define SEG101 1 +-#define SEG100 0 +- +-#define LCDDR6 _SFR_MEM8(0xF2) +-#define SEG115 7 +-#define SEG114 6 +-#define SEG113 5 +-#define SEG112 4 +-#define SEG111 3 +-#define SEG110 2 +-#define SEG109 1 +-#define SEG108 0 +- +-#define LCDDR7 _SFR_MEM8(0xF3) +-#define SEG123 7 +-#define SEG122 6 +-#define SEG121 5 +-#define SEG120 4 +-#define SEG119 3 +-#define SEG118 2 +-#define SEG117 1 +-#define SEG116 0 +- +-#define LCDDR8 _SFR_MEM8(0xF4) +-#define SEG124 0 +- +-#define LCDDR10 _SFR_MEM8(0xF6) +-#define SEG207 7 +-#define SEG206 6 +-#define SEG205 5 +-#define SEG204 4 +-#define SEG203 3 +-#define SEG202 2 +-#define SEG201 1 +-#define SEG200 0 +- +-#define LCDDR11 _SFR_MEM8(0xF7) +-#define SEG215 7 +-#define SEG214 6 +-#define SEG213 5 +-#define SEG212 4 +-#define SEG211 3 +-#define SEG210 2 +-#define SEG209 1 +-#define SEG208 0 +- +-#define LCDDR12 _SFR_MEM8(0xF8) +-#define SEG223 7 +-#define SEG222 6 +-#define SEG221 5 +-#define SEG220 4 +-#define SEG219 3 +-#define SEG218 2 +-#define SEG217 1 +-#define SEG216 0 +- +-#define LCDDR13 _SFR_MEM8(0xF9) +-#define SEG224 0 +- +-#define LCDDR15 _SFR_MEM8(0xFB) +-#define SEG307 7 +-#define SEG306 6 +-#define SEG305 5 +-#define SEG304 4 +-#define SEG303 3 +-#define SEG302 2 +-#define SEG301 1 +-#define SEG300 0 +- +-#define LCDDR16 _SFR_MEM8(0xFC) +-#define SEG315 7 +-#define SEG314 6 +-#define SEG313 5 +-#define SEG312 4 +-#define SEG311 3 +-#define SEG310 2 +-#define SEG309 1 +-#define SEG308 0 +- +-#define LCDDR17 _SFR_MEM8(0xFD) +-#define SEG323 7 +-#define SEG322 6 +-#define SEG321 5 +-#define SEG320 4 +-#define SEG319 3 +-#define SEG318 2 +-#define SEG317 1 +-#define SEG316 0 +- +-#define LCDDR18 _SFR_MEM8(0xFE) +-#define SEG324 0 +- +-/* LCDDR0-18 */ +-#define SEG24 0 +- +-#define SEG23 7 +-#define SEG22 6 +-#define SEG21 5 +-#define SEG20 4 +-#define SEG19 3 +-#define SEG18 2 +-#define SEG17 1 +-#define SEG16 0 +- +-#define SEG15 7 +-#define SEG14 6 +-#define SEG13 5 +-#define SEG12 4 +-#define SEG11 3 +-#define SEG10 2 +-#define SEG9 1 +-#define SEG8 0 +- +-#define SEG7 7 +-#define SEG6 6 +-#define SEG5 5 +-#define SEG4 4 +-#define SEG3 3 +-#define SEG2 2 +-#define SEG1 1 +-#define SEG0 0 +- +-/* Interrupt vectors */ +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* Pin Change Interrupt Request 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) +-#define SIG_PIN_CHANGE0 _VECTOR(2) +- +-/* Pin Change Interrupt Request 1 */ +-#define PCINT1_vect_num 3 +-#define PCINT1_vect _VECTOR(3) +-#define SIG_PIN_CHANGE1 _VECTOR(3) +- +-/* Timer/Counter2 Compare Match */ +-#define TIMER2_COMP_vect_num 4 +-#define TIMER2_COMP_vect _VECTOR(4) +-#define SIG_OUTPUT_COMPARE2 _VECTOR(4) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 5 +-#define TIMER2_OVF_vect _VECTOR(5) +-#define SIG_OVERFLOW2 _VECTOR(5) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 6 +-#define TIMER1_CAPT_vect _VECTOR(6) +-#define SIG_INPUT_CAPTURE1 _VECTOR(6) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 7 +-#define TIMER1_COMPA_vect _VECTOR(7) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(7) +- +-/* Timer/Counter Compare Match B */ +-#define TIMER1_COMPB_vect_num 8 +-#define TIMER1_COMPB_vect _VECTOR(8) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(8) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 9 +-#define TIMER1_OVF_vect _VECTOR(9) +-#define SIG_OVERFLOW1 _VECTOR(9) +- +-/* Timer/Counter0 Compare Match */ +-#define TIMER0_COMP_vect_num 10 +-#define TIMER0_COMP_vect _VECTOR(10) +-#define SIG_OUTPUT_COMPARE0 _VECTOR(10) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 11 +-#define TIMER0_OVF_vect _VECTOR(11) +-#define SIG_OVERFLOW0 _VECTOR(11) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 12 +-#define SPI_STC_vect _VECTOR(12) +-#define SIG_SPI _VECTOR(12) +- +-/* USART0, Rx Complete */ +-#define USART0_RX_vect_num 13 +-#define USART0_RX_vect _VECTOR(13) +-#define SIG_USART_RECV _VECTOR(13) +- +-/* USART0 Data register Empty */ +-#define USART0_UDRE_vect_num 14 +-#define USART0_UDRE_vect _VECTOR(14) +-#define SIG_USART_DATA _VECTOR(14) +- +-/* USART0, Tx Complete */ +-#define USART0_TX_vect_num 15 +-#define USART0_TX_vect _VECTOR(15) +-#define SIG_USART_TRANS _VECTOR(15) +- +-/* USI Start Condition */ +-#define USI_START_vect_num 16 +-#define USI_START_vect _VECTOR(16) +-#define SIG_USI_START _VECTOR(16) +- +-/* USI Overflow */ +-#define USI_OVERFLOW_vect_num 17 +-#define USI_OVERFLOW_vect _VECTOR(17) +-#define SIG_USI_OVERFLOW _VECTOR(17) +- +-/* Analog Comparator */ +-#define ANALOG_COMP_vect_num 18 +-#define ANALOG_COMP_vect _VECTOR(18) +-#define SIG_COMPARATOR _VECTOR(18) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 19 +-#define ADC_vect _VECTOR(19) +-#define SIG_ADC _VECTOR(19) +- +-/* EEPROM Ready */ +-#define EE_READY_vect_num 20 +-#define EE_READY_vect _VECTOR(20) +-#define SIG_EEPROM_READY _VECTOR(20) +- +-/* Store Program Memory Read */ +-#define SPM_READY_vect_num 21 +-#define SPM_READY_vect _VECTOR(21) +-#define SIG_SPM_READY _VECTOR(21) +- +-/* LCD Start of Frame */ +-#define LCD_vect_num 22 +-#define LCD_vect _VECTOR(22) +-#define SIG_LCD _VECTOR(22) +- +-#define _VECTORS_SIZE 92 +- +-/* Constants */ +-#define SPM_PAGESIZE 128 +-#define RAMEND 0x4FF +-#define XRAMEND RAMEND +-#define E2END 0x1FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x3FFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x94 +-#define SIGNATURE_2 0x05 +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_PIN_CHANGE0 +-#pragma GCC poison SIG_PIN_CHANGE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE2 +-#pragma GCC poison SIG_OVERFLOW2 +-#pragma GCC poison SIG_INPUT_CAPTURE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OUTPUT_COMPARE0 +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_SPI +-#pragma GCC poison SIG_USART_RECV +-#pragma GCC poison SIG_USART_DATA +-#pragma GCC poison SIG_USART_TRANS +-#pragma GCC poison SIG_USI_START +-#pragma GCC poison SIG_USI_OVERFLOW +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_ADC +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_SPM_READY +-#pragma GCC poison SIG_LCD +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +- +-#endif /* _AVR_IOM169P_H_ */ ++/* Copyright (c) 2002, 2003, 2004, 2005, 2006 ++ Juergen Schilling ++ Eric B. Weddington ++ Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom169p.h 2231 2011-03-07 05:06:55Z arcanum $ */ ++ ++/* iom169p.h - definitions for ATmega169P */ ++ ++#ifndef _AVR_IOM169P_H_ ++#define _AVR_IOM169P_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom169p.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* Port A */ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++/* Port B */ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* Port C */ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++/* Port D */ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* Port E */ ++#define PINE _SFR_IO8(0x0C) ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE7 7 ++#define DDE6 6 ++#define DDE5 5 ++#define DDE4 4 ++#define DDE3 3 ++#define DDE2 2 ++#define DDE1 1 ++#define DDE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PE7 7 ++#define PE6 6 ++#define PE5 5 ++#define PE4 4 ++#define PE3 3 ++#define PE2 2 ++#define PE1 1 ++#define PE0 0 ++ ++/* Port F */ ++#define PINF _SFR_IO8(0x0F) ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDF7 7 ++#define DDF6 6 ++#define DDF5 5 ++#define DDF4 4 ++#define DDF3 3 ++#define DDF2 2 ++#define DDF1 1 ++#define DDF0 0 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PF7 7 ++#define PF6 6 ++#define PF5 5 ++#define PF4 4 ++#define PF3 3 ++#define PF2 2 ++#define PF1 1 ++#define PF0 0 ++ ++/* Port G */ ++#define PING _SFR_IO8(0x12) ++#define PING5 5 ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++#define DDRG _SFR_IO8(0x13) ++#define DDG4 4 ++#define DDG3 3 ++#define DDG2 2 ++#define DDG1 1 ++#define DDG0 0 ++ ++#define PORTG _SFR_IO8(0x14) ++#define PG4 4 ++#define PG3 3 ++#define PG2 2 ++#define PG1 1 ++#define PG0 0 ++ ++/* Timer/Counter 0 interrupt Flag Register */ ++#define TIFR0 _SFR_IO8(0x15) ++#define OCF0A 1 ++#define TOV0 0 ++ ++/* Timer/Counter 1 interrupt Flag Register */ ++#define TIFR1 _SFR_IO8(0x16) ++#define ICF1 5 ++#define OCF1B 2 ++#define OCF1A 1 ++#define TOV1 0 ++ ++/* Timer/Counter 2 interrupt Flag Register */ ++#define TIFR2 _SFR_IO8(0x17) ++#define OCF2A 1 ++#define TOV2 0 ++ ++/* External Interrupt Flag Register */ ++#define EIFR _SFR_IO8(0x1C) ++#define PCIF1 7 ++#define PCIF0 6 ++#define INTF0 0 ++ ++/* External Interrupt Mask Register */ ++#define EIMSK _SFR_IO8(0x1D) ++#define PCIE1 7 ++#define PCIE0 6 ++#define INT0 0 ++ ++/* General Purpose I/O Register 0 */ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++#define EEDR _SFR_IO8(0X20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0X22) ++ ++/* 6-char sequence denoting where to find the EEPROM registers in memory space. ++ Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM ++ subroutines. ++ First two letters: EECR address. ++ Second two letters: EEDR address. ++ Last two letters: EEAR address. */ ++#define __EEPROM_REG_LOCATIONS__ 1F2021 ++ ++/* General Timer/Counter Control Register */ ++#define GTCCR _SFR_IO8(0x23) ++#define TSM 7 ++#define PSR2 1 ++#define PSR10 0 ++ ++/* Timer/Counter Control Register A */ ++#define TCCR0A _SFR_IO8(0x24) ++#define FOC0A 7 ++#define WGM00 6 ++#define COM0A1 5 ++#define COM0A0 4 ++#define WGM01 3 ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* Timer/Counter Register */ ++#define TCNT0 _SFR_IO8(0x26) ++ ++/* Output Compare Register A */ ++#define OCR0A _SFR_IO8(0x27) ++ ++/* General Purpose I/O Register 1 */ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++/* General Purpose I/O Register 2 */ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++/* SPI Control Register */ ++#define SPCR _SFR_IO8(0x2C) ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++/* SPI Status Register */ ++#define SPSR _SFR_IO8(0x2D) ++#define SPIF 7 ++#define WCOL 6 ++#define SPI2X 0 ++ ++/* SPI Data Register */ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Analog Comperator Control and Status Register */ ++#define ACSR _SFR_IO8(0x30) ++#define ACD 7 ++#define ACBG 6 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++/* On-chip Debug Register */ ++#define OCDR _SFR_IO8(0x31) ++#define IDRD 7 ++#define OCDR7 7 ++#define OCDR6 6 ++#define OCDR5 5 ++#define OCDR4 4 ++#define OCDR3 3 ++#define OCDR2 2 ++#define OCDR1 1 ++#define OCDR0 0 ++ ++/* Sleep Mode Control Register */ ++#define SMCR _SFR_IO8(0x33) ++#define SM2 3 ++#define SM1 2 ++#define SM0 1 ++#define SE 0 ++ ++/* MCU Status Register */ ++#define MCUSR _SFR_IO8(0x34) ++#define JTRF 4 ++#define WDRF 3 ++#define BORF 2 ++#define EXTRF 1 ++#define PORF 0 ++ ++/* MCU Control Rgeister */ ++#define MCUCR _SFR_IO8(0x35) ++#define JTD 7 ++#define PUD 4 ++#define IVSEL 1 ++#define IVCE 0 ++ ++/* Store Program Memory Control and Status Register */ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMIE 7 ++#define RWWSB 6 ++#define RWWSRE 4 ++#define BLBSET 3 ++#define PGWRT 2 ++#define PGERS 1 ++#define SPMEN 0 ++ ++/* Watchdog Timer Control Register */ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDCE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* Clock Prescale Register */ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPCE 7 ++#define CLKPS3 3 ++#define CLKPS2 2 ++#define CLKPS1 1 ++#define CLKPS0 0 ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRLCD 4 ++ ++/* Oscillator Calibration Register */ ++#define OSCCAL _SFR_MEM8(0x66) ++ ++/* External Interrupt Control Register A */ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC01 1 ++#define ISC00 0 ++ ++/* Pin Change Mask Register */ ++#define PCMSK _SFR_MEM16(0x6B) ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT7 7 ++#define PCINT6 6 ++#define PCINT5 5 ++#define PCINT4 4 ++#define PCINT3 3 ++#define PCINT2 2 ++#define PCINT1 1 ++#define PCINT0 0 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT15 7 ++#define PCINT14 6 ++#define PCINT13 5 ++#define PCINT12 4 ++#define PCINT11 3 ++#define PCINT10 2 ++#define PCINT9 1 ++#define PCINT8 0 ++ ++/* Timer/Counter 0 Interrupt Mask Register */ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define OCIE0A 1 ++#define TOIE0 0 ++ ++/* Timer/Counter 1 Interrupt Mask Register */ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define ICIE1 5 ++#define OCIE1B 2 ++#define OCIE1A 1 ++#define TOIE1 0 ++ ++/* Timer/Counter 2 Interrupt Mask Register */ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define OCIE2A 1 ++#define TOIE2 0 ++ ++/* ADC Data Register */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++/* ADC Control and Status Register A */ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADEN 7 ++#define ADSC 6 ++#define ADATE 5 ++#define ADIF 4 ++#define ADIE 3 ++#define ADPS2 2 ++#define ADPS1 1 ++#define ADPS0 0 ++ ++ ++/* ADC Control and Status Register B */ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ACME 6 ++#define ADTS2 2 ++#define ADTS1 1 ++#define ADTS0 0 ++ ++/* ADC Multiplex Selection Register */ ++#define ADMUX _SFR_MEM8(0x7C) ++/* ADMUX */ ++#define REFS1 7 ++#define REFS0 6 ++#define ADLAR 5 ++#define MUX4 4 ++#define MUX3 3 ++#define MUX2 2 ++#define MUX1 1 ++#define MUX0 0 ++ ++/* Digital Input Disable Register 0 */ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC7D 7 ++#define ADC6D 6 ++#define ADC5D 5 ++#define ADC4D 4 ++#define ADC3D 3 ++#define ADC2D 2 ++#define ADC1D 1 ++#define ADC0D 0 ++ ++/* Digital Input Disable Register 1 */ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN1D 1 ++#define AIN0D 0 ++ ++/* Timer/Counter1 Control Register A */ ++#define TCCR1A _SFR_MEM8(0x80) ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define WGM11 1 ++#define WGM10 0 ++ ++/* Timer/Counter1 Control Register B */ ++#define TCCR1B _SFR_MEM8(0x81) ++#define ICNC1 7 ++#define ICES1 6 ++#define WGM13 4 ++#define WGM12 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* Timer/Counter1 Control Register C */ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1A 7 ++#define FOC1B 6 ++ ++/* Timer/Counter1 Register */ ++#define TCNT1 _SFR_MEM16(0x84) ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Timer/Counter1 Input Capture Register */ ++#define ICR1 _SFR_MEM16(0x86) ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Timer/Counter1 Output Compare Register A */ ++#define OCR1A _SFR_MEM16(0x88) ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Timer/Counter1 Output Compare Registare B */ ++#define OCR1B _SFR_MEM16(0x8A) ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Timer/Counter2 Control Register A */ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define FOC2A 7 ++#define WGM20 6 ++#define COM2A1 5 ++#define COM2A0 4 ++#define WGM21 3 ++#define CS22 2 ++#define CS21 1 ++#define CS20 0 ++ ++/* Timer/Counter2 Register */ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++/* Timer/Counter2 Output Compare Register */ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++/* Asynchronous Status Register */ ++#define ASSR _SFR_MEM8(0xB6) ++#define EXCLK 4 ++#define AS2 3 ++#define TCN2UB 2 ++#define OCR2UB 1 ++#define TCR2UB 0 ++ ++/* USI Control Register */ ++#define USICR _SFR_MEM8(0xB8) ++#define USISIE 7 ++#define USIOIE 6 ++#define USIWM1 5 ++#define USIWM0 4 ++#define USICS1 3 ++#define USICS0 2 ++#define USICLK 1 ++#define USITC 0 ++ ++/* USI Status Register */ ++#define USISR _SFR_MEM8(0xB9) ++#define USISIF 7 ++#define USIOIF 6 ++#define USIPF 5 ++#define USIDC 4 ++#define USICNT3 3 ++#define USICNT2 2 ++#define USICNT1 1 ++#define USICNT0 0 ++ ++/* USI Data Register */ ++#define USIDR _SFR_MEM8(0xBA) ++ ++/* USART0 Control and Status Register A */ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define RXC0 7 ++#define TXC0 6 ++#define UDRE0 5 ++#define FE0 4 ++#define DOR0 3 ++#define UPE0 2 ++#define U2X0 1 ++#define MPCM0 0 ++ ++/* USART0 Control and Status Register B */ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define RXCIE0 7 ++#define TXCIE0 6 ++#define UDRIE0 5 ++#define RXEN0 4 ++#define TXEN0 3 ++#define UCSZ02 2 ++#define RXB80 1 ++#define TXB80 0 ++ ++/* USART0 Control and Status Register C */ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UMSEL0 6 ++#define UPM01 5 ++#define UPM00 4 ++#define USBS0 3 ++#define UCSZ01 2 ++#define UCSZ00 1 ++#define UCPOL0 0 ++ ++/* USART0 Baud Rate Register */ ++#define UBRR0 _SFR_MEM16(0xC4) ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++/* USART0 I/O Data Register */ ++#define UDR0 _SFR_MEM8(0xC6) ++ ++/* LCD Control and Status Register A */ ++#define LCDCRA _SFR_MEM8(0xE4) ++#define LCDEN 7 ++#define LCDAB 6 ++#define LCDIF 4 ++#define LCDIE 3 ++#define LCDBD 2 ++#define LCDCCD 1 ++#define LCDBL 0 ++ ++/* LCD Control and Status Register B */ ++#define LCDCRB _SFR_MEM8(0xE5) ++#define LCDCS 7 ++#define LCD2B 6 ++#define LCDMUX1 5 ++#define LCDMUX0 4 ++#define LCDPM2 2 ++#define LCDPM1 1 ++#define LCDPM0 0 ++ ++/* LCD Frame Rate Register */ ++#define LCDFRR _SFR_MEM8(0xE6) ++#define LCDPS2 6 ++#define LCDPS1 5 ++#define LCDPS0 4 ++#define LCDCD2 2 ++#define LCDCD1 1 ++#define LCDCD0 0 ++ ++/* LCD Contrast Control Register */ ++#define LCDCCR _SFR_MEM8(0xE7) ++#define LCDDC2 7 ++#define LCDDC1 6 ++#define LCDDC0 5 ++#define LCDMDT 4 ++#define LCDCC3 3 ++#define LCDCC2 2 ++#define LCDCC1 1 ++#define LCDCC0 0 ++ ++/* LCD Memory mapping */ ++#define LCDDR0 _SFR_MEM8(0xEC) ++#define SEG007 7 ++#define SEG006 6 ++#define SEG005 5 ++#define SEG004 4 ++#define SEG003 3 ++#define SEG002 2 ++#define SEG001 1 ++#define SEG000 0 ++ ++#define LCDDR1 _SFR_MEM8(0xED) ++#define SEG015 7 ++#define SEG014 6 ++#define SEG013 5 ++#define SEG012 4 ++#define SEG011 3 ++#define SEG010 2 ++#define SEG009 1 ++#define SEG008 0 ++ ++#define LCDDR2 _SFR_MEM8(0xEE) ++#define SEG023 7 ++#define SEG022 6 ++#define SEG021 5 ++#define SEG020 4 ++#define SEG019 3 ++#define SEG018 2 ++#define SEG017 1 ++#define SEG016 0 ++ ++#define LCDDR3 _SFR_MEM8(0xEF) ++#define SEG024 0 ++ ++#define LCDDR5 _SFR_MEM8(0xF1) ++#define SEG107 7 ++#define SEG106 6 ++#define SEG105 5 ++#define SEG104 4 ++#define SEG103 3 ++#define SEG102 2 ++#define SEG101 1 ++#define SEG100 0 ++ ++#define LCDDR6 _SFR_MEM8(0xF2) ++#define SEG115 7 ++#define SEG114 6 ++#define SEG113 5 ++#define SEG112 4 ++#define SEG111 3 ++#define SEG110 2 ++#define SEG109 1 ++#define SEG108 0 ++ ++#define LCDDR7 _SFR_MEM8(0xF3) ++#define SEG123 7 ++#define SEG122 6 ++#define SEG121 5 ++#define SEG120 4 ++#define SEG119 3 ++#define SEG118 2 ++#define SEG117 1 ++#define SEG116 0 ++ ++#define LCDDR8 _SFR_MEM8(0xF4) ++#define SEG124 0 ++ ++#define LCDDR10 _SFR_MEM8(0xF6) ++#define SEG207 7 ++#define SEG206 6 ++#define SEG205 5 ++#define SEG204 4 ++#define SEG203 3 ++#define SEG202 2 ++#define SEG201 1 ++#define SEG200 0 ++ ++#define LCDDR11 _SFR_MEM8(0xF7) ++#define SEG215 7 ++#define SEG214 6 ++#define SEG213 5 ++#define SEG212 4 ++#define SEG211 3 ++#define SEG210 2 ++#define SEG209 1 ++#define SEG208 0 ++ ++#define LCDDR12 _SFR_MEM8(0xF8) ++#define SEG223 7 ++#define SEG222 6 ++#define SEG221 5 ++#define SEG220 4 ++#define SEG219 3 ++#define SEG218 2 ++#define SEG217 1 ++#define SEG216 0 ++ ++#define LCDDR13 _SFR_MEM8(0xF9) ++#define SEG224 0 ++ ++#define LCDDR15 _SFR_MEM8(0xFB) ++#define SEG307 7 ++#define SEG306 6 ++#define SEG305 5 ++#define SEG304 4 ++#define SEG303 3 ++#define SEG302 2 ++#define SEG301 1 ++#define SEG300 0 ++ ++#define LCDDR16 _SFR_MEM8(0xFC) ++#define SEG315 7 ++#define SEG314 6 ++#define SEG313 5 ++#define SEG312 4 ++#define SEG311 3 ++#define SEG310 2 ++#define SEG309 1 ++#define SEG308 0 ++ ++#define LCDDR17 _SFR_MEM8(0xFD) ++#define SEG323 7 ++#define SEG322 6 ++#define SEG321 5 ++#define SEG320 4 ++#define SEG319 3 ++#define SEG318 2 ++#define SEG317 1 ++#define SEG316 0 ++ ++#define LCDDR18 _SFR_MEM8(0xFE) ++#define SEG324 0 ++ ++/* LCDDR0-18 */ ++#define SEG24 0 ++ ++#define SEG23 7 ++#define SEG22 6 ++#define SEG21 5 ++#define SEG20 4 ++#define SEG19 3 ++#define SEG18 2 ++#define SEG17 1 ++#define SEG16 0 ++ ++#define SEG15 7 ++#define SEG14 6 ++#define SEG13 5 ++#define SEG12 4 ++#define SEG11 3 ++#define SEG10 2 ++#define SEG9 1 ++#define SEG8 0 ++ ++#define SEG7 7 ++#define SEG6 6 ++#define SEG5 5 ++#define SEG4 4 ++#define SEG3 3 ++#define SEG2 2 ++#define SEG1 1 ++#define SEG0 0 ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) ++#define SIG_PIN_CHANGE0 _VECTOR(2) ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect_num 3 ++#define PCINT1_vect _VECTOR(3) ++#define SIG_PIN_CHANGE1 _VECTOR(3) ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect_num 4 ++#define TIMER2_COMP_vect _VECTOR(4) ++#define SIG_OUTPUT_COMPARE2 _VECTOR(4) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 5 ++#define TIMER2_OVF_vect _VECTOR(5) ++#define SIG_OVERFLOW2 _VECTOR(5) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 6 ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define SIG_INPUT_CAPTURE1 _VECTOR(6) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 7 ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(7) ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect_num 8 ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(8) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 9 ++#define TIMER1_OVF_vect _VECTOR(9) ++#define SIG_OVERFLOW1 _VECTOR(9) ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect_num 10 ++#define TIMER0_COMP_vect _VECTOR(10) ++#define SIG_OUTPUT_COMPARE0 _VECTOR(10) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 11 ++#define TIMER0_OVF_vect _VECTOR(11) ++#define SIG_OVERFLOW0 _VECTOR(11) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 12 ++#define SPI_STC_vect _VECTOR(12) ++#define SIG_SPI _VECTOR(12) ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect_num 13 ++#define USART0_RX_vect _VECTOR(13) ++#define SIG_USART_RECV _VECTOR(13) ++ ++/* USART0 Data register Empty */ ++#define USART0_UDRE_vect_num 14 ++#define USART0_UDRE_vect _VECTOR(14) ++#define SIG_USART_DATA _VECTOR(14) ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect_num 15 ++#define USART0_TX_vect _VECTOR(15) ++#define SIG_USART_TRANS _VECTOR(15) ++ ++/* USI Start Condition */ ++#define USI_START_vect_num 16 ++#define USI_START_vect _VECTOR(16) ++#define SIG_USI_START _VECTOR(16) ++ ++/* USI Overflow */ ++#define USI_OVERFLOW_vect_num 17 ++#define USI_OVERFLOW_vect _VECTOR(17) ++#define SIG_USI_OVERFLOW _VECTOR(17) ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect_num 18 ++#define ANALOG_COMP_vect _VECTOR(18) ++#define SIG_COMPARATOR _VECTOR(18) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 19 ++#define ADC_vect _VECTOR(19) ++#define SIG_ADC _VECTOR(19) ++ ++/* EEPROM Ready */ ++#define EE_READY_vect_num 20 ++#define EE_READY_vect _VECTOR(20) ++#define SIG_EEPROM_READY _VECTOR(20) ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect_num 21 ++#define SPM_READY_vect _VECTOR(21) ++#define SIG_SPM_READY _VECTOR(21) ++ ++/* LCD Start of Frame */ ++#define LCD_vect_num 22 ++#define LCD_vect _VECTOR(22) ++#define SIG_LCD _VECTOR(22) ++ ++#define _VECTORS_SIZE 92 ++ ++/* Constants */ ++#define SPM_PAGESIZE 128 ++#define RAMSTART 0x100 ++#define RAMEND 0x4FF ++#define XRAMEND RAMEND ++#define E2END 0x1FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x3FFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x05 ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_PIN_CHANGE0 ++#pragma GCC poison SIG_PIN_CHANGE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE2 ++#pragma GCC poison SIG_OVERFLOW2 ++#pragma GCC poison SIG_INPUT_CAPTURE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OUTPUT_COMPARE0 ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_SPI ++#pragma GCC poison SIG_USART_RECV ++#pragma GCC poison SIG_USART_DATA ++#pragma GCC poison SIG_USART_TRANS ++#pragma GCC poison SIG_USI_START ++#pragma GCC poison SIG_USI_OVERFLOW ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_ADC ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_SPM_READY ++#pragma GCC poison SIG_LCD ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++ ++#endif /* _AVR_IOM169P_H_ */ +diff --git a/include/avr/iom169pa.h b/include/avr/iom169pa.h +index e419272..0aa406a 100644 +--- a/include/avr/iom169pa.h ++++ b/include/avr/iom169pa.h +@@ -1,1472 +1,1472 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom169pa.h 2192 2010-11-08 13:53:24Z arcanum $ */ +- +-/* avr/iom169pa.h - definitions for ATmega169PA */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom169pa.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATmega169PA_H_ +-#define _AVR_ATmega169PA_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +-#define PINA4 4 +-#define PINA5 5 +-#define PINA6 6 +-#define PINA7 7 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +-#define DDA4 4 +-#define DDA5 5 +-#define DDA6 6 +-#define DDA7 7 +- +-#define PORTA _SFR_IO8(0x02) +-#define PORTA0 0 +-#define PORTA1 1 +-#define PORTA2 2 +-#define PORTA3 3 +-#define PORTA4 4 +-#define PORTA5 5 +-#define PORTA6 6 +-#define PORTA7 7 +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +-#define PINC7 7 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC3 3 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +-#define DDC7 7 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC3 3 +-#define PORTC4 4 +-#define PORTC5 5 +-#define PORTC6 6 +-#define PORTC7 7 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define PINE _SFR_IO8(0x0C) +-#define PINE0 0 +-#define PINE1 1 +-#define PINE2 2 +-#define PINE3 3 +-#define PINE4 4 +-#define PINE5 5 +-#define PINE6 6 +-#define PINE7 7 +- +-#define DDRE _SFR_IO8(0x0D) +-#define DDE0 0 +-#define DDE1 1 +-#define DDE2 2 +-#define DDE3 3 +-#define DDE4 4 +-#define DDE5 5 +-#define DDE6 6 +-#define DDE7 7 +- +-#define PORTE _SFR_IO8(0x0E) +-#define PORTE0 0 +-#define PORTE1 1 +-#define PORTE2 2 +-#define PORTE3 3 +-#define PORTE4 4 +-#define PORTE5 5 +-#define PORTE6 6 +-#define PORTE7 7 +- +-#define PINF _SFR_IO8(0x0F) +-#define PINF0 0 +-#define PINF1 1 +-#define PINF2 2 +-#define PINF3 3 +-#define PINF4 4 +-#define PINF5 5 +-#define PINF6 6 +-#define PINF7 7 +- +-#define DDRF _SFR_IO8(0x10) +-#define DDF0 0 +-#define DDF1 1 +-#define DDF2 2 +-#define DDF3 3 +-#define DDF4 4 +-#define DDF5 5 +-#define DDF6 6 +-#define DDF7 7 +- +-#define PORTF _SFR_IO8(0x11) +-#define PORTF0 0 +-#define PORTF1 1 +-#define PORTF2 2 +-#define PORTF3 3 +-#define PORTF4 4 +-#define PORTF5 5 +-#define PORTF6 6 +-#define PORTF7 7 +- +-#define PING _SFR_IO8(0x12) +-#define PING0 0 +-#define PING1 1 +-#define PING2 2 +-#define PING3 3 +-#define PING4 4 +-#define PING5 5 +- +-#define DDRG _SFR_IO8(0x13) +-#define DDG0 0 +-#define DDG1 1 +-#define DDG2 2 +-#define DDG3 3 +-#define DDG4 4 +-#define DDG5 5 +- +-#define PORTG _SFR_IO8(0x14) +-#define PORTG0 0 +-#define PORTG1 1 +-#define PORTG2 2 +-#define PORTG3 3 +-#define PORTG4 4 +-#define PORTG5 5 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define TIFR2 _SFR_IO8(0x17) +-#define TOV2 0 +-#define OCF2A 1 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define PCIF0 4 +-#define PCIF1 5 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define PCIE0 4 +-#define PCIE1 5 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEWE 1 +-#define EEMWE 2 +-#define EERIE 3 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSR310 0 +-#define PSR2 1 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM01 3 +-#define COM0A0 4 +-#define COM0A1 5 +-#define WGM00 6 +-#define FOC0A 7 +- +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define OCR0A _SFR_IO8(0x27) +-#define OCR0A0 0 +-#define OCR0A1 1 +-#define OCR0A2 2 +-#define OCR0A3 3 +-#define OCR0A4 4 +-#define OCR0A5 5 +-#define OCR0A6 6 +-#define OCR0A7 7 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define OCDR _SFR_IO8(0x31) +-#define OCDR0 0 +-#define OCDR1 1 +-#define OCDR2 2 +-#define OCDR3 3 +-#define OCDR4 4 +-#define OCDR5 5 +-#define OCDR6 6 +-#define OCDR7 7 +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +-#define JTRF 4 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define BODSE 5 +-#define BODS 6 +-#define JTD 7 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define WDTCR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM1 3 +-#define PRLCD 4 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define TIMSK2 _SFR_MEM8(0x70) +-#define TOIE2 0 +-#define OCIE2A 1 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +- +-#define ADCL _SFR_MEM8(0x78) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_MEM8(0x79) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ACME 6 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define TCCR2A _SFR_MEM8(0xB0) +-#define CS20 0 +-#define CS21 1 +-#define CS22 2 +-#define WGM21 3 +-#define COM2A0 4 +-#define COM2A1 5 +-#define WGM20 6 +-#define FOC2A 7 +- +-#define TCCR2B _SFR_MEM8(0xB1) +- +-#define TCNT2 _SFR_MEM8(0xB2) +-#define TCNT2_0 0 +-#define TCNT2_1 1 +-#define TCNT2_2 2 +-#define TCNT2_3 3 +-#define TCNT2_4 4 +-#define TCNT2_5 5 +-#define TCNT2_6 6 +-#define TCNT2_7 7 +- +-#define OCR2A _SFR_MEM8(0xB3) +-#define OCR2A0 0 +-#define OCR2A1 1 +-#define OCR2A2 2 +-#define OCR2A3 3 +-#define OCR2A4 4 +-#define OCR2A5 5 +-#define OCR2A6 6 +-#define OCR2A7 7 +- +-#define ASSR _SFR_MEM8(0xB6) +-#define TCR2UB 0 +-#define OCR2UB 1 +-#define TCN2UB 2 +-#define AS2 3 +-#define EXCLK 4 +- +-#define USICR _SFR_MEM8(0xB8) +-#define USITC 0 +-#define USICLK 1 +-#define USICS0 2 +-#define USICS1 3 +-#define USIWM0 4 +-#define USIWM1 5 +-#define USIOIE 6 +-#define USISIE 7 +- +-#define USISR _SFR_MEM8(0xB9) +-#define USICNT0 0 +-#define USICNT1 1 +-#define USICNT2 2 +-#define USICNT3 3 +-#define USIDC 4 +-#define USIPF 5 +-#define USIOIF 6 +-#define USISIF 7 +- +-#define USIDR _SFR_MEM8(0xBA) +-#define USIDR0 0 +-#define USIDR1 1 +-#define USIDR2 2 +-#define USIDR3 3 +-#define USIDR4 4 +-#define USIDR5 5 +-#define USIDR6 6 +-#define USIDR7 7 +- +-#define UCSR0A _SFR_MEM8(0xC0) +-#define MPCM0 0 +-#define U2X0 1 +-#define UPE0 2 +-#define DOR0 3 +-#define FE0 4 +-#define UDRE0 5 +-#define TXC0 6 +-#define RXC0 7 +- +-#define UCSR0B _SFR_MEM8(0xC1) +-#define TXB80 0 +-#define RXB80 1 +-#define UCSZ02 2 +-#define TXEN0 3 +-#define RXEN0 4 +-#define UDRIE0 5 +-#define TXCIE0 6 +-#define RXCIE0 7 +- +-#define UCSR0C _SFR_MEM8(0xC2) +-#define UCPOL0 0 +-#define UCSZ00 1 +-#define UCSZ01 2 +-#define USBS0 3 +-#define UPM00 4 +-#define UPM01 5 +-#define UMSEL0 6 +- +-#define UBRR0 _SFR_MEM16(0xC4) +- +-#define UBRR0L _SFR_MEM8(0xC4) +-#define UBRR0_0 0 +-#define UBRR0_1 1 +-#define UBRR0_2 2 +-#define UBRR0_3 3 +-#define UBRR0_4 4 +-#define UBRR0_5 5 +-#define UBRR0_6 6 +-#define UBRR0_7 7 +- +-#define UBRR0H _SFR_MEM8(0xC5) +-#define UBRR0_8 0 +-#define UBRR0_9 1 +-#define UBRR0_10 2 +-#define UBRR0_11 3 +- +-#define UDR0 _SFR_MEM8(0xC6) +-#define UDR00 0 +-#define UDR01 1 +-#define UDR02 2 +-#define UDR03 3 +-#define UDR04 4 +-#define UDR05 5 +-#define UDR06 6 +-#define UDR07 7 +- +-#define LCDCRA _SFR_MEM8(0xE4) +-#define LCDBL 0 +-#define LCDCCD 1 +-#define LCDBD 2 +-#define LCDIE 3 +-#define LCDIF 4 +-#define LCDAB 6 +-#define LCDEN 7 +- +-#define LCDCRB _SFR_MEM8(0xE5) +-#define LCDPM0 0 +-#define LCDPM1 1 +-#define LCDPM2 2 +-#define LCDMUX0 4 +-#define LCDMUX1 5 +-#define LCD2B 6 +-#define LCDCS 7 +- +-#define LCDFRR _SFR_MEM8(0xE6) +-#define LCDCD0 0 +-#define LCDCD1 1 +-#define LCDCD2 2 +-#define LCDPS0 4 +-#define LCDPS1 5 +-#define LCDPS2 6 +- +-#define LCDCCR _SFR_MEM8(0xE7) +-#define LCDCC0 0 +-#define LCDCC1 1 +-#define LCDCC2 2 +-#define LCDCC3 3 +-#define LCDMDT 4 +-#define LCDDC0 5 +-#define LCDDC1 6 +-#define LCDDC2 7 +- +-#define LCDDR0 _SFR_MEM8(0xEC) +-#define SEG000 0 +-#define SEG001 1 +-#define SEG002 2 +-#define SEG003 3 +-#define SEG004 4 +-#define SEG005 5 +-#define SEG006 6 +-#define SEG007 7 +- +-#define LCDDR1 _SFR_MEM8(0xED) +-#define SEG008 0 +-#define SEG009 1 +-#define SEG010 2 +-#define SEG011 3 +-#define SEG012 4 +-#define SEG013 5 +-#define SEG014 6 +-#define SEG015 7 +- +-#define LCDDR2 _SFR_MEM8(0xEE) +-#define SEG016 0 +-#define SEG017 1 +-#define SEG018 2 +-#define SEG019 3 +-#define SEG020 4 +-#define SEG021 5 +-#define SEG022 6 +-#define SEG023 7 +- +-#define LCDDR3 _SFR_MEM8(0xEF) +-#define SEG024 0 +- +-#define LCDDR5 _SFR_MEM8(0xF1) +-#define SEG100 0 +-#define SEG101 1 +-#define SEG102 2 +-#define SEG103 3 +-#define SEG104 4 +-#define SEG105 5 +-#define SEG106 6 +-#define SEG107 7 +- +-#define LCDDR6 _SFR_MEM8(0xF2) +-#define SEG108 0 +-#define SEG109 1 +-#define SEG110 2 +-#define SEG111 3 +-#define SEG112 4 +-#define SEG113 5 +-#define SEG114 6 +-#define SEG115 7 +- +-#define LCDDR7 _SFR_MEM8(0xF3) +-#define SEG116 0 +-#define SEG117 1 +-#define SEG118 2 +-#define SEG119 3 +-#define SEG120 4 +-#define SEG121 5 +-#define SEG122 6 +-#define SEG123 7 +- +-#define LCDDR8 _SFR_MEM8(0xF4) +-#define SEG124 0 +- +-#define LCDDR10 _SFR_MEM8(0xF6) +-#define SEG200 0 +-#define SEG201 1 +-#define SEG202 2 +-#define SEG203 3 +-#define SEG204 4 +-#define SEG205 5 +-#define SEG206 6 +-#define SEG207 7 +- +-#define LCDDR11 _SFR_MEM8(0xF7) +-#define SEG208 0 +-#define SEG209 1 +-#define SEG210 2 +-#define SEG211 3 +-#define SEG212 4 +-#define SEG213 5 +-#define SEG214 6 +-#define SEG215 7 +- +-#define LCDDR12 _SFR_MEM8(0xF8) +-#define SEG216 0 +-#define SEG217 1 +-#define SEG218 2 +-#define SEG219 3 +-#define SEG220 4 +-#define SEG221 5 +-#define SEG222 6 +-#define SEG223 7 +- +-#define LCDDR13 _SFR_MEM8(0xF9) +-#define SEG224 0 +- +-#define LCDDR15 _SFR_MEM8(0xFB) +-#define SEG300 0 +-#define SEG301 1 +-#define SEG302 2 +-#define SEG303 3 +-#define SEG304 4 +-#define SEG305 5 +-#define SEG306 6 +-#define SEG307 7 +- +-#define LCDDR16 _SFR_MEM8(0xFC) +-#define SEG308 0 +-#define SEG309 1 +-#define SEG310 2 +-#define SEG311 3 +-#define SEG312 4 +-#define SEG313 5 +-#define SEG314 6 +-#define SEG315 7 +- +-#define LCDDR17 _SFR_MEM8(0xFD) +-#define SEG316 0 +-#define SEG317 1 +-#define SEG318 2 +-#define SEG319 3 +-#define SEG320 4 +-#define SEG321 5 +-#define SEG322 6 +-#define SEG323 7 +- +-#define LCDDR18 _SFR_MEM8(0xFE) +-#define SEG324 0 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ +-#define PCINT1_vect_num 3 +-#define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */ +-#define TIMER2_COMP_vect_num 4 +-#define TIMER2_COMP_vect _VECTOR(4) /* Timer/Counter2 Compare Match */ +-#define TIMER2_OVF_vect_num 5 +-#define TIMER2_OVF_vect _VECTOR(5) /* Timer/Counter2 Overflow */ +-#define TIMER1_CAPT_vect_num 6 +-#define TIMER1_CAPT_vect _VECTOR(6) /* Timer/Counter1 Capture Event */ +-#define TIMER1_COMPA_vect_num 7 +-#define TIMER1_COMPA_vect _VECTOR(7) /* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPB_vect_num 8 +-#define TIMER1_COMPB_vect _VECTOR(8) /* Timer/Counter Compare Match B */ +-#define TIMER1_OVF_vect_num 9 +-#define TIMER1_OVF_vect _VECTOR(9) /* Timer/Counter1 Overflow */ +-#define TIMER0_COMP_vect_num 10 +-#define TIMER0_COMP_vect _VECTOR(10) /* Timer/Counter0 Compare Match */ +-#define TIMER0_OVF_vect_num 11 +-#define TIMER0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ +-#define SPI_STC_vect_num 12 +-#define SPI_STC_vect _VECTOR(12) /* SPI Serial Transfer Complete */ +-#define USART0_RX_vect_num 13 +-#define USART0_RX_vect _VECTOR(13) /* USART0, Rx Complete */ +-#define USART0_UDRE_vect_num 14 +-#define USART0_UDRE_vect _VECTOR(14) /* USART0 Data register Empty */ +-#define USART0_TX_vect_num 15 +-#define USART0_TX_vect _VECTOR(15) /* USART0, Tx Complete */ +-#define USI_START_vect_num 16 +-#define USI_START_vect _VECTOR(16) /* USI Start Condition */ +-#define USI_OVERFLOW_vect_num 17 +-#define USI_OVERFLOW_vect _VECTOR(17) /* USI Overflow */ +-#define ANALOG_COMP_vect_num 18 +-#define ANALOG_COMP_vect _VECTOR(18) /* Analog Comparator */ +-#define ADC_vect_num 19 +-#define ADC_vect _VECTOR(19) /* ADC Conversion Complete */ +-#define EE_READY_vect_num 20 +-#define EE_READY_vect _VECTOR(20) /* EEPROM Ready */ +-#define SPM_READY_vect_num 21 +-#define SPM_READY_vect _VECTOR(21) /* Store Program Memory Read */ +-#define LCD_vect_num 22 +-#define LCD_vect _VECTOR(22) /* LCD Start of Frame */ +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (23 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (128) +-#define RAMSTART (0x100) +-#define RAMSIZE (1024) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x1FF) +-#define E2PAGESIZE (4) +-#define FLASHEND (0x3FFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ +-#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ +-#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) +- +-/* Extended Fuse Byte */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(0) /* Disable external reset */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) /* Brown out detector trigger level */ +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x94 +-#define SIGNATURE_2 0x05 +- +- +-/* Device Pin Definitions */ +-#define RXD_DDR DDRE +-#define RXD_PORT PORTE +-#define RXD_PIN PINE +-#define RXD_BIT 0 +- +-#define PCINT0_DDR DDRE +-#define PCINT0_PORT PORTE +-#define PCINT0_PIN PINE +-#define PCINT0_BIT 0 +- +-#define TXD_DDR DDRE +-#define TXD_PORT PORTE +-#define TXD_PIN PINE +-#define TXD_BIT 1 +- +-#define PCINT1_DDR DDRE +-#define PCINT1_PORT PORTE +-#define PCINT1_PIN PINE +-#define PCINT1_BIT 1 +- +-#define XCK_DDR DDRE +-#define XCK_PORT PORTE +-#define XCK_PIN PINE +-#define XCK_BIT 2 +- +-#define AIN0_DDR DDRE +-#define AIN0_PORT PORTE +-#define AIN0_PIN PINE +-#define AIN0_BIT 2 +- +-#define PCINT2_DDR DDRE +-#define PCINT2_PORT PORTE +-#define PCINT2_PIN PINE +-#define PCINT2_BIT 2 +- +-#define AIN1_DDR DDRE +-#define AIN1_PORT PORTE +-#define AIN1_PIN PINE +-#define AIN1_BIT 3 +- +-#define PCINT3_DDR DDRE +-#define PCINT3_PORT PORTE +-#define PCINT3_PIN PINE +-#define PCINT3_BIT 3 +- +-#define USCK_DDR DDRE +-#define USCK_PORT PORTE +-#define USCK_PIN PINE +-#define USCK_BIT 4 +- +-#define SCL_DDR DDRE +-#define SCL_PORT PORTE +-#define SCL_PIN PINE +-#define SCL_BIT 4 +- +-#define PCINT4_DDR DDRE +-#define PCINT4_PORT PORTE +-#define PCINT4_PIN PINE +-#define PCINT4_BIT 4 +- +-#define DI_DDR DDRE +-#define DI_PORT PORTE +-#define DI_PIN PINE +-#define DI_BIT 5 +- +-#define SDA_DDR DDRE +-#define SDA_PORT PORTE +-#define SDA_PIN PINE +-#define SDA_BIT 5 +- +-#define PCINT5_DDR DDRE +-#define PCINT5_PORT PORTE +-#define PCINT5_PIN PINE +-#define PCINT5_BIT 5 +- +-#define DO_DDR DDRE +-#define DO_PORT PORTE +-#define DO_PIN PINE +-#define DO_BIT 6 +- +-#define PCINT6_DDR DDRE +-#define PCINT6_PORT PORTE +-#define PCINT6_PIN PINE +-#define PCINT6_BIT 6 +- +-#define PCINT7_DDR DDRE +-#define PCINT7_PORT PORTE +-#define PCINT7_PIN PINE +-#define PCINT7_BIT 7 +- +-#define SS_DDR DDRB +-#define SS_PORT PORTB +-#define SS_PIN PINB +-#define SS_BIT 0 +- +-#define PCINT8_DDR DDRB +-#define PCINT8_PORT PORTB +-#define PCINT8_PIN PINB +-#define PCINT8_BIT 0 +- +-#define SCK_DDR DDRB +-#define SCK_PORT PORTB +-#define SCK_PIN PINB +-#define SCK_BIT 1 +- +-#define PCINT9_DDR DDRB +-#define PCINT9_PORT PORTB +-#define PCINT9_PIN PINB +-#define PCINT9_BIT 1 +- +-#define MOSI_DDR DDRB +-#define MOSI_PORT PORTB +-#define MOSI_PIN PINB +-#define MOSI_BIT 2 +- +-#define PCINT10_DDR DDRB +-#define PCINT10_PORT PORTB +-#define PCINT10_PIN PINB +-#define PCINT10_BIT 2 +- +-#define MISO_DDR DDRB +-#define MISO_PORT PORTB +-#define MISO_PIN PINB +-#define MISO_BIT 3 +- +-#define PCINT11_DDR DDRB +-#define PCINT11_PORT PORTB +-#define PCINT11_PIN PINB +-#define PCINT11_BIT 3 +- +-#define OC0_DDR DDRB +-#define OC0_PORT PORTB +-#define OC0_PIN PINB +-#define OC0_BIT 4 +- +-#define PCINT12_DDR DDRB +-#define PCINT12_PORT PORTB +-#define PCINT12_PIN PINB +-#define PCINT12_BIT 4 +- +-#define OC1A_DDR DDRB +-#define OC1A_PORT PORTB +-#define OC1A_PIN PINB +-#define OC1A_BIT 5 +- +-#define PCINT13_DDR DDRB +-#define PCINT13_PORT PORTB +-#define PCINT13_PIN PINB +-#define PCINT13_BIT 5 +- +-#define OC1B_DDR DDRB +-#define OC1B_PORT PORTB +-#define OC1B_PIN PINB +-#define OC1B_BIT 6 +- +-#define PCINT14_DDR DDRB +-#define PCINT14_PORT PORTB +-#define PCINT14_PIN PINB +-#define PCINT14_BIT 6 +- +-#define OC2_DDR DDRB +-#define OC2_PORT PORTB +-#define OC2_PIN PINB +-#define OC2_BIT 7 +- +-#define PCINT15_DDR DDRB +-#define PCINT15_PORT PORTB +-#define PCINT15_PIN PINB +-#define PCINT15_BIT 7 +- +-#define T1_DDR DDRG +-#define T1_PORT PORTG +-#define T1_PIN PING +-#define T1_BIT 3 +- +-#define SEG24_DDR DDRG +-#define SEG24_PORT PORTG +-#define SEG24_PIN PING +-#define SEG24_BIT 3 +- +-#define T0_DDR DDRG +-#define T0_PORT PORTG +-#define T0_PIN PING +-#define T0_BIT 4 +- +-#define SEG23_DDR DDRG +-#define SEG23_PORT PORTG +-#define SEG23_PIN PING +-#define SEG23_BIT 4 +- +-#define SEG22_DDR DDRD +-#define SEG22_PORT PORTD +-#define SEG22_PIN PIND +-#define SEG22_BIT 0 +- +-#define SEG21_DDR DDRD +-#define SEG21_PORT PORTD +-#define SEG21_PIN PIND +-#define SEG21_BIT 1 +- +-#define SEG20_DDR DDRD +-#define SEG20_PORT PORTD +-#define SEG20_PIN PIND +-#define SEG20_BIT 2 +- +-#define SEG19_DDR DDRD +-#define SEG19_PORT PORTD +-#define SEG19_PIN PIND +-#define SEG19_BIT 3 +- +-#define SEG18_DDR DDRD +-#define SEG18_PORT PORTD +-#define SEG18_PIN PIND +-#define SEG18_BIT 4 +- +-#define SEG17_DDR DDRD +-#define SEG17_PORT PORTD +-#define SEG17_PIN PIND +-#define SEG17_BIT 5 +- +-#define SEG16_DDR DDRD +-#define SEG16_PORT PORTD +-#define SEG16_PIN PIND +-#define SEG16_BIT 6 +- +-#define SEG15_DDR DDRD +-#define SEG15_PORT PORTD +-#define SEG15_PIN PIND +-#define SEG15_BIT 7 +- +-#define SEG14_DDR DDRG +-#define SEG14_PORT PORTG +-#define SEG14_PIN PING +-#define SEG14_BIT 0 +- +-#define SEG13_DDR DDRG +-#define SEG13_PORT PORTG +-#define SEG13_PIN PING +-#define SEG13_BIT 1 +- +-#define SEG12_DDR DDRC +-#define SEG12_PORT PORTC +-#define SEG12_PIN PINC +-#define SEG12_BIT 0 +- +-#define SEG11_DDR DDRC +-#define SEG11_PORT PORTC +-#define SEG11_PIN PINC +-#define SEG11_BIT 1 +- +-#define SEG10_DDR DDRC +-#define SEG10_PORT PORTC +-#define SEG10_PIN PINC +-#define SEG10_BIT 2 +- +-#define SEG9_DDR DDRC +-#define SEG9_PORT PORTC +-#define SEG9_PIN PINC +-#define SEG9_BIT 3 +- +-#define SEG8_DDR DDRC +-#define SEG8_PORT PORTC +-#define SEG8_PIN PINC +-#define SEG8_BIT 4 +- +-#define SEG7_DDR DDRC +-#define SEG7_PORT PORTC +-#define SEG7_PIN PINC +-#define SEG7_BIT 5 +- +-#define SEG6_DDR DDRC +-#define SEG6_PORT PORTC +-#define SEG6_PIN PINC +-#define SEG6_BIT 6 +- +-#define SEG5_DDR DDRC +-#define SEG5_PORT PORTC +-#define SEG5_PIN PINC +-#define SEG5_BIT 7 +- +-#define SEG4_DDR DDRG +-#define SEG4_PORT PORTG +-#define SEG4_PIN PING +-#define SEG4_BIT 2 +- +-#define SEG3_DDR DDRA +-#define SEG3_PORT PORTA +-#define SEG3_PIN PINA +-#define SEG3_BIT 7 +- +-#define SEG2_DDR DDRA +-#define SEG2_PORT PORTA +-#define SEG2_PIN PINA +-#define SEG2_BIT 6 +- +-#define SEG1_DDR DDRA +-#define SEG1_PORT PORTA +-#define SEG1_PIN PINA +-#define SEG1_BIT 5 +- +-#define SEG0_DDR DDRA +-#define SEG0_PORT PORTA +-#define SEG0_PIN PINA +-#define SEG0_BIT 4 +- +-#define COM3_DDR DDRA +-#define COM3_PORT PORTA +-#define COM3_PIN PINA +-#define COM3_BIT 3 +- +-#define COM2_DDR DDRA +-#define COM2_PORT PORTA +-#define COM2_PIN PINA +-#define COM2_BIT 2 +- +-#define COM1_DDR DDRA +-#define COM1_PORT PORTA +-#define COM1_PIN PINA +-#define COM1_BIT 1 +- +-#define COM0_DDR DDRA +-#define COM0_PORT PORTA +-#define COM0_PIN PINA +-#define COM0_BIT 0 +- +-#define ADC7_DDR DDRF +-#define ADC7_PORT PORTF +-#define ADC7_PIN PINF +-#define ADC7_BIT 7 +- +-#define ADC6_DDR DDRF +-#define ADC6_PORT PORTF +-#define ADC6_PIN PINF +-#define ADC6_BIT 6 +- +-#define TD0_DDR DDRF +-#define TD0_PORT PORTF +-#define TD0_PIN PINF +-#define TD0_BIT 6 +- +-#define ADC5_DDR DDRF +-#define ADC5_PORT PORTF +-#define ADC5_PIN PINF +-#define ADC5_BIT 5 +- +-#define ADC4_DDR DDRF +-#define ADC4_PORT PORTF +-#define ADC4_PIN PINF +-#define ADC4_BIT 4 +- +-#define ADC3_DDR DDRF +-#define ADC3_PORT PORTF +-#define ADC3_PIN PINF +-#define ADC3_BIT 3 +- +-#define ADC2_DDR DDRF +-#define ADC2_PORT PORTF +-#define ADC2_PIN PINF +-#define ADC2_BIT 2 +- +-#define ADC1_DDR DDRF +-#define ADC1_PORT PORTF +-#define ADC1_PIN PINF +-#define ADC1_BIT 1 +- +-#define ADC0_DDR DDRF +-#define ADC0_PORT PORTF +-#define ADC0_PIN PINF +-#define ADC0_BIT 0 +- +-#endif /* _AVR_ATmega169PA_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom169pa.h 2192 2010-11-08 13:53:24Z arcanum $ */ ++ ++/* avr/iom169pa.h - definitions for ATmega169PA */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom169pa.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATmega169PA_H_ ++#define _AVR_ATmega169PA_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++#define PINA4 4 ++#define PINA5 5 ++#define PINA6 6 ++#define PINA7 7 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++#define DDA4 4 ++#define DDA5 5 ++#define DDA6 6 ++#define DDA7 7 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA0 0 ++#define PORTA1 1 ++#define PORTA2 2 ++#define PORTA3 3 ++#define PORTA4 4 ++#define PORTA5 5 ++#define PORTA6 6 ++#define PORTA7 7 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++#define PINC7 7 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++#define DDC7 7 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC3 3 ++#define PORTC4 4 ++#define PORTC5 5 ++#define PORTC6 6 ++#define PORTC7 7 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE0 0 ++#define PINE1 1 ++#define PINE2 2 ++#define PINE3 3 ++#define PINE4 4 ++#define PINE5 5 ++#define PINE6 6 ++#define PINE7 7 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE0 0 ++#define DDE1 1 ++#define DDE2 2 ++#define DDE3 3 ++#define DDE4 4 ++#define DDE5 5 ++#define DDE6 6 ++#define DDE7 7 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE0 0 ++#define PORTE1 1 ++#define PORTE2 2 ++#define PORTE3 3 ++#define PORTE4 4 ++#define PORTE5 5 ++#define PORTE6 6 ++#define PORTE7 7 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF0 0 ++#define PINF1 1 ++#define PINF2 2 ++#define PINF3 3 ++#define PINF4 4 ++#define PINF5 5 ++#define PINF6 6 ++#define PINF7 7 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDF0 0 ++#define DDF1 1 ++#define DDF2 2 ++#define DDF3 3 ++#define DDF4 4 ++#define DDF5 5 ++#define DDF6 6 ++#define DDF7 7 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PORTF0 0 ++#define PORTF1 1 ++#define PORTF2 2 ++#define PORTF3 3 ++#define PORTF4 4 ++#define PORTF5 5 ++#define PORTF6 6 ++#define PORTF7 7 ++ ++#define PING _SFR_IO8(0x12) ++#define PING0 0 ++#define PING1 1 ++#define PING2 2 ++#define PING3 3 ++#define PING4 4 ++#define PING5 5 ++ ++#define DDRG _SFR_IO8(0x13) ++#define DDG0 0 ++#define DDG1 1 ++#define DDG2 2 ++#define DDG3 3 ++#define DDG4 4 ++#define DDG5 5 ++ ++#define PORTG _SFR_IO8(0x14) ++#define PORTG0 0 ++#define PORTG1 1 ++#define PORTG2 2 ++#define PORTG3 3 ++#define PORTG4 4 ++#define PORTG5 5 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define PCIF0 4 ++#define PCIF1 5 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define PCIE0 4 ++#define PCIE1 5 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR310 0 ++#define PSR2 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM01 3 ++#define COM0A0 4 ++#define COM0A1 5 ++#define WGM00 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define OCR0A _SFR_IO8(0x27) ++#define OCR0A0 0 ++#define OCR0A1 1 ++#define OCR0A2 2 ++#define OCR0A3 3 ++#define OCR0A4 4 ++#define OCR0A5 5 ++#define OCR0A6 6 ++#define OCR0A7 7 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCDR7 7 ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define JTRF 4 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++#define JTD 7 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRLCD 4 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_MEM8(0x79) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM21 3 ++#define COM2A0 4 ++#define COM2A1 5 ++#define WGM20 6 ++#define FOC2A 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++#define TCNT2_0 0 ++#define TCNT2_1 1 ++#define TCNT2_2 2 ++#define TCNT2_3 3 ++#define TCNT2_4 4 ++#define TCNT2_5 5 ++#define TCNT2_6 6 ++#define TCNT2_7 7 ++ ++#define OCR2A _SFR_MEM8(0xB3) ++#define OCR2A0 0 ++#define OCR2A1 1 ++#define OCR2A2 2 ++#define OCR2A3 3 ++#define OCR2A4 4 ++#define OCR2A5 5 ++#define OCR2A6 6 ++#define OCR2A7 7 ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2UB 0 ++#define OCR2UB 1 ++#define TCN2UB 2 ++#define AS2 3 ++#define EXCLK 4 ++ ++#define USICR _SFR_MEM8(0xB8) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_MEM8(0xB9) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_MEM8(0xBA) ++#define USIDR0 0 ++#define USIDR1 1 ++#define USIDR2 2 ++#define USIDR3 3 ++#define USIDR4 4 ++#define USIDR5 5 ++#define USIDR6 6 ++#define USIDR7 7 ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL0 6 ++ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0_0 0 ++#define UBRR0_1 1 ++#define UBRR0_2 2 ++#define UBRR0_3 3 ++#define UBRR0_4 4 ++#define UBRR0_5 5 ++#define UBRR0_6 6 ++#define UBRR0_7 7 ++ ++#define UBRR0H _SFR_MEM8(0xC5) ++#define UBRR0_8 0 ++#define UBRR0_9 1 ++#define UBRR0_10 2 ++#define UBRR0_11 3 ++ ++#define UDR0 _SFR_MEM8(0xC6) ++#define UDR00 0 ++#define UDR01 1 ++#define UDR02 2 ++#define UDR03 3 ++#define UDR04 4 ++#define UDR05 5 ++#define UDR06 6 ++#define UDR07 7 ++ ++#define LCDCRA _SFR_MEM8(0xE4) ++#define LCDBL 0 ++#define LCDCCD 1 ++#define LCDBD 2 ++#define LCDIE 3 ++#define LCDIF 4 ++#define LCDAB 6 ++#define LCDEN 7 ++ ++#define LCDCRB _SFR_MEM8(0xE5) ++#define LCDPM0 0 ++#define LCDPM1 1 ++#define LCDPM2 2 ++#define LCDMUX0 4 ++#define LCDMUX1 5 ++#define LCD2B 6 ++#define LCDCS 7 ++ ++#define LCDFRR _SFR_MEM8(0xE6) ++#define LCDCD0 0 ++#define LCDCD1 1 ++#define LCDCD2 2 ++#define LCDPS0 4 ++#define LCDPS1 5 ++#define LCDPS2 6 ++ ++#define LCDCCR _SFR_MEM8(0xE7) ++#define LCDCC0 0 ++#define LCDCC1 1 ++#define LCDCC2 2 ++#define LCDCC3 3 ++#define LCDMDT 4 ++#define LCDDC0 5 ++#define LCDDC1 6 ++#define LCDDC2 7 ++ ++#define LCDDR0 _SFR_MEM8(0xEC) ++#define SEG000 0 ++#define SEG001 1 ++#define SEG002 2 ++#define SEG003 3 ++#define SEG004 4 ++#define SEG005 5 ++#define SEG006 6 ++#define SEG007 7 ++ ++#define LCDDR1 _SFR_MEM8(0xED) ++#define SEG008 0 ++#define SEG009 1 ++#define SEG010 2 ++#define SEG011 3 ++#define SEG012 4 ++#define SEG013 5 ++#define SEG014 6 ++#define SEG015 7 ++ ++#define LCDDR2 _SFR_MEM8(0xEE) ++#define SEG016 0 ++#define SEG017 1 ++#define SEG018 2 ++#define SEG019 3 ++#define SEG020 4 ++#define SEG021 5 ++#define SEG022 6 ++#define SEG023 7 ++ ++#define LCDDR3 _SFR_MEM8(0xEF) ++#define SEG024 0 ++ ++#define LCDDR5 _SFR_MEM8(0xF1) ++#define SEG100 0 ++#define SEG101 1 ++#define SEG102 2 ++#define SEG103 3 ++#define SEG104 4 ++#define SEG105 5 ++#define SEG106 6 ++#define SEG107 7 ++ ++#define LCDDR6 _SFR_MEM8(0xF2) ++#define SEG108 0 ++#define SEG109 1 ++#define SEG110 2 ++#define SEG111 3 ++#define SEG112 4 ++#define SEG113 5 ++#define SEG114 6 ++#define SEG115 7 ++ ++#define LCDDR7 _SFR_MEM8(0xF3) ++#define SEG116 0 ++#define SEG117 1 ++#define SEG118 2 ++#define SEG119 3 ++#define SEG120 4 ++#define SEG121 5 ++#define SEG122 6 ++#define SEG123 7 ++ ++#define LCDDR8 _SFR_MEM8(0xF4) ++#define SEG124 0 ++ ++#define LCDDR10 _SFR_MEM8(0xF6) ++#define SEG200 0 ++#define SEG201 1 ++#define SEG202 2 ++#define SEG203 3 ++#define SEG204 4 ++#define SEG205 5 ++#define SEG206 6 ++#define SEG207 7 ++ ++#define LCDDR11 _SFR_MEM8(0xF7) ++#define SEG208 0 ++#define SEG209 1 ++#define SEG210 2 ++#define SEG211 3 ++#define SEG212 4 ++#define SEG213 5 ++#define SEG214 6 ++#define SEG215 7 ++ ++#define LCDDR12 _SFR_MEM8(0xF8) ++#define SEG216 0 ++#define SEG217 1 ++#define SEG218 2 ++#define SEG219 3 ++#define SEG220 4 ++#define SEG221 5 ++#define SEG222 6 ++#define SEG223 7 ++ ++#define LCDDR13 _SFR_MEM8(0xF9) ++#define SEG224 0 ++ ++#define LCDDR15 _SFR_MEM8(0xFB) ++#define SEG300 0 ++#define SEG301 1 ++#define SEG302 2 ++#define SEG303 3 ++#define SEG304 4 ++#define SEG305 5 ++#define SEG306 6 ++#define SEG307 7 ++ ++#define LCDDR16 _SFR_MEM8(0xFC) ++#define SEG308 0 ++#define SEG309 1 ++#define SEG310 2 ++#define SEG311 3 ++#define SEG312 4 ++#define SEG313 5 ++#define SEG314 6 ++#define SEG315 7 ++ ++#define LCDDR17 _SFR_MEM8(0xFD) ++#define SEG316 0 ++#define SEG317 1 ++#define SEG318 2 ++#define SEG319 3 ++#define SEG320 4 ++#define SEG321 5 ++#define SEG322 6 ++#define SEG323 7 ++ ++#define LCDDR18 _SFR_MEM8(0xFE) ++#define SEG324 0 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect_num 3 ++#define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */ ++#define TIMER2_COMP_vect_num 4 ++#define TIMER2_COMP_vect _VECTOR(4) /* Timer/Counter2 Compare Match */ ++#define TIMER2_OVF_vect_num 5 ++#define TIMER2_OVF_vect _VECTOR(5) /* Timer/Counter2 Overflow */ ++#define TIMER1_CAPT_vect_num 6 ++#define TIMER1_CAPT_vect _VECTOR(6) /* Timer/Counter1 Capture Event */ ++#define TIMER1_COMPA_vect_num 7 ++#define TIMER1_COMPA_vect _VECTOR(7) /* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPB_vect_num 8 ++#define TIMER1_COMPB_vect _VECTOR(8) /* Timer/Counter Compare Match B */ ++#define TIMER1_OVF_vect_num 9 ++#define TIMER1_OVF_vect _VECTOR(9) /* Timer/Counter1 Overflow */ ++#define TIMER0_COMP_vect_num 10 ++#define TIMER0_COMP_vect _VECTOR(10) /* Timer/Counter0 Compare Match */ ++#define TIMER0_OVF_vect_num 11 ++#define TIMER0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ ++#define SPI_STC_vect_num 12 ++#define SPI_STC_vect _VECTOR(12) /* SPI Serial Transfer Complete */ ++#define USART0_RX_vect_num 13 ++#define USART0_RX_vect _VECTOR(13) /* USART0, Rx Complete */ ++#define USART0_UDRE_vect_num 14 ++#define USART0_UDRE_vect _VECTOR(14) /* USART0 Data register Empty */ ++#define USART0_TX_vect_num 15 ++#define USART0_TX_vect _VECTOR(15) /* USART0, Tx Complete */ ++#define USI_START_vect_num 16 ++#define USI_START_vect _VECTOR(16) /* USI Start Condition */ ++#define USI_OVERFLOW_vect_num 17 ++#define USI_OVERFLOW_vect _VECTOR(17) /* USI Overflow */ ++#define ANALOG_COMP_vect_num 18 ++#define ANALOG_COMP_vect _VECTOR(18) /* Analog Comparator */ ++#define ADC_vect_num 19 ++#define ADC_vect _VECTOR(19) /* ADC Conversion Complete */ ++#define EE_READY_vect_num 20 ++#define EE_READY_vect _VECTOR(20) /* EEPROM Ready */ ++#define SPM_READY_vect_num 21 ++#define SPM_READY_vect _VECTOR(21) /* Store Program Memory Read */ ++#define LCD_vect_num 22 ++#define LCD_vect _VECTOR(22) /* LCD Start of Frame */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (23 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (128) ++#define RAMSTART (0x100) ++#define RAMSIZE (1024) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x1FF) ++#define E2PAGESIZE (4) ++#define FLASHEND (0x3FFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ ++#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ ++#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) ++ ++/* Extended Fuse Byte */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(0) /* Disable external reset */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) /* Brown out detector trigger level */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x05 ++ ++ ++/* Device Pin Definitions */ ++#define RXD_DDR DDRE ++#define RXD_PORT PORTE ++#define RXD_PIN PINE ++#define RXD_BIT 0 ++ ++#define PCINT0_DDR DDRE ++#define PCINT0_PORT PORTE ++#define PCINT0_PIN PINE ++#define PCINT0_BIT 0 ++ ++#define TXD_DDR DDRE ++#define TXD_PORT PORTE ++#define TXD_PIN PINE ++#define TXD_BIT 1 ++ ++#define PCINT1_DDR DDRE ++#define PCINT1_PORT PORTE ++#define PCINT1_PIN PINE ++#define PCINT1_BIT 1 ++ ++#define XCK_DDR DDRE ++#define XCK_PORT PORTE ++#define XCK_PIN PINE ++#define XCK_BIT 2 ++ ++#define AIN0_DDR DDRE ++#define AIN0_PORT PORTE ++#define AIN0_PIN PINE ++#define AIN0_BIT 2 ++ ++#define PCINT2_DDR DDRE ++#define PCINT2_PORT PORTE ++#define PCINT2_PIN PINE ++#define PCINT2_BIT 2 ++ ++#define AIN1_DDR DDRE ++#define AIN1_PORT PORTE ++#define AIN1_PIN PINE ++#define AIN1_BIT 3 ++ ++#define PCINT3_DDR DDRE ++#define PCINT3_PORT PORTE ++#define PCINT3_PIN PINE ++#define PCINT3_BIT 3 ++ ++#define USCK_DDR DDRE ++#define USCK_PORT PORTE ++#define USCK_PIN PINE ++#define USCK_BIT 4 ++ ++#define SCL_DDR DDRE ++#define SCL_PORT PORTE ++#define SCL_PIN PINE ++#define SCL_BIT 4 ++ ++#define PCINT4_DDR DDRE ++#define PCINT4_PORT PORTE ++#define PCINT4_PIN PINE ++#define PCINT4_BIT 4 ++ ++#define DI_DDR DDRE ++#define DI_PORT PORTE ++#define DI_PIN PINE ++#define DI_BIT 5 ++ ++#define SDA_DDR DDRE ++#define SDA_PORT PORTE ++#define SDA_PIN PINE ++#define SDA_BIT 5 ++ ++#define PCINT5_DDR DDRE ++#define PCINT5_PORT PORTE ++#define PCINT5_PIN PINE ++#define PCINT5_BIT 5 ++ ++#define DO_DDR DDRE ++#define DO_PORT PORTE ++#define DO_PIN PINE ++#define DO_BIT 6 ++ ++#define PCINT6_DDR DDRE ++#define PCINT6_PORT PORTE ++#define PCINT6_PIN PINE ++#define PCINT6_BIT 6 ++ ++#define PCINT7_DDR DDRE ++#define PCINT7_PORT PORTE ++#define PCINT7_PIN PINE ++#define PCINT7_BIT 7 ++ ++#define SS_DDR DDRB ++#define SS_PORT PORTB ++#define SS_PIN PINB ++#define SS_BIT 0 ++ ++#define PCINT8_DDR DDRB ++#define PCINT8_PORT PORTB ++#define PCINT8_PIN PINB ++#define PCINT8_BIT 0 ++ ++#define SCK_DDR DDRB ++#define SCK_PORT PORTB ++#define SCK_PIN PINB ++#define SCK_BIT 1 ++ ++#define PCINT9_DDR DDRB ++#define PCINT9_PORT PORTB ++#define PCINT9_PIN PINB ++#define PCINT9_BIT 1 ++ ++#define MOSI_DDR DDRB ++#define MOSI_PORT PORTB ++#define MOSI_PIN PINB ++#define MOSI_BIT 2 ++ ++#define PCINT10_DDR DDRB ++#define PCINT10_PORT PORTB ++#define PCINT10_PIN PINB ++#define PCINT10_BIT 2 ++ ++#define MISO_DDR DDRB ++#define MISO_PORT PORTB ++#define MISO_PIN PINB ++#define MISO_BIT 3 ++ ++#define PCINT11_DDR DDRB ++#define PCINT11_PORT PORTB ++#define PCINT11_PIN PINB ++#define PCINT11_BIT 3 ++ ++#define OC0_DDR DDRB ++#define OC0_PORT PORTB ++#define OC0_PIN PINB ++#define OC0_BIT 4 ++ ++#define PCINT12_DDR DDRB ++#define PCINT12_PORT PORTB ++#define PCINT12_PIN PINB ++#define PCINT12_BIT 4 ++ ++#define OC1A_DDR DDRB ++#define OC1A_PORT PORTB ++#define OC1A_PIN PINB ++#define OC1A_BIT 5 ++ ++#define PCINT13_DDR DDRB ++#define PCINT13_PORT PORTB ++#define PCINT13_PIN PINB ++#define PCINT13_BIT 5 ++ ++#define OC1B_DDR DDRB ++#define OC1B_PORT PORTB ++#define OC1B_PIN PINB ++#define OC1B_BIT 6 ++ ++#define PCINT14_DDR DDRB ++#define PCINT14_PORT PORTB ++#define PCINT14_PIN PINB ++#define PCINT14_BIT 6 ++ ++#define OC2_DDR DDRB ++#define OC2_PORT PORTB ++#define OC2_PIN PINB ++#define OC2_BIT 7 ++ ++#define PCINT15_DDR DDRB ++#define PCINT15_PORT PORTB ++#define PCINT15_PIN PINB ++#define PCINT15_BIT 7 ++ ++#define T1_DDR DDRG ++#define T1_PORT PORTG ++#define T1_PIN PING ++#define T1_BIT 3 ++ ++#define SEG24_DDR DDRG ++#define SEG24_PORT PORTG ++#define SEG24_PIN PING ++#define SEG24_BIT 3 ++ ++#define T0_DDR DDRG ++#define T0_PORT PORTG ++#define T0_PIN PING ++#define T0_BIT 4 ++ ++#define SEG23_DDR DDRG ++#define SEG23_PORT PORTG ++#define SEG23_PIN PING ++#define SEG23_BIT 4 ++ ++#define SEG22_DDR DDRD ++#define SEG22_PORT PORTD ++#define SEG22_PIN PIND ++#define SEG22_BIT 0 ++ ++#define SEG21_DDR DDRD ++#define SEG21_PORT PORTD ++#define SEG21_PIN PIND ++#define SEG21_BIT 1 ++ ++#define SEG20_DDR DDRD ++#define SEG20_PORT PORTD ++#define SEG20_PIN PIND ++#define SEG20_BIT 2 ++ ++#define SEG19_DDR DDRD ++#define SEG19_PORT PORTD ++#define SEG19_PIN PIND ++#define SEG19_BIT 3 ++ ++#define SEG18_DDR DDRD ++#define SEG18_PORT PORTD ++#define SEG18_PIN PIND ++#define SEG18_BIT 4 ++ ++#define SEG17_DDR DDRD ++#define SEG17_PORT PORTD ++#define SEG17_PIN PIND ++#define SEG17_BIT 5 ++ ++#define SEG16_DDR DDRD ++#define SEG16_PORT PORTD ++#define SEG16_PIN PIND ++#define SEG16_BIT 6 ++ ++#define SEG15_DDR DDRD ++#define SEG15_PORT PORTD ++#define SEG15_PIN PIND ++#define SEG15_BIT 7 ++ ++#define SEG14_DDR DDRG ++#define SEG14_PORT PORTG ++#define SEG14_PIN PING ++#define SEG14_BIT 0 ++ ++#define SEG13_DDR DDRG ++#define SEG13_PORT PORTG ++#define SEG13_PIN PING ++#define SEG13_BIT 1 ++ ++#define SEG12_DDR DDRC ++#define SEG12_PORT PORTC ++#define SEG12_PIN PINC ++#define SEG12_BIT 0 ++ ++#define SEG11_DDR DDRC ++#define SEG11_PORT PORTC ++#define SEG11_PIN PINC ++#define SEG11_BIT 1 ++ ++#define SEG10_DDR DDRC ++#define SEG10_PORT PORTC ++#define SEG10_PIN PINC ++#define SEG10_BIT 2 ++ ++#define SEG9_DDR DDRC ++#define SEG9_PORT PORTC ++#define SEG9_PIN PINC ++#define SEG9_BIT 3 ++ ++#define SEG8_DDR DDRC ++#define SEG8_PORT PORTC ++#define SEG8_PIN PINC ++#define SEG8_BIT 4 ++ ++#define SEG7_DDR DDRC ++#define SEG7_PORT PORTC ++#define SEG7_PIN PINC ++#define SEG7_BIT 5 ++ ++#define SEG6_DDR DDRC ++#define SEG6_PORT PORTC ++#define SEG6_PIN PINC ++#define SEG6_BIT 6 ++ ++#define SEG5_DDR DDRC ++#define SEG5_PORT PORTC ++#define SEG5_PIN PINC ++#define SEG5_BIT 7 ++ ++#define SEG4_DDR DDRG ++#define SEG4_PORT PORTG ++#define SEG4_PIN PING ++#define SEG4_BIT 2 ++ ++#define SEG3_DDR DDRA ++#define SEG3_PORT PORTA ++#define SEG3_PIN PINA ++#define SEG3_BIT 7 ++ ++#define SEG2_DDR DDRA ++#define SEG2_PORT PORTA ++#define SEG2_PIN PINA ++#define SEG2_BIT 6 ++ ++#define SEG1_DDR DDRA ++#define SEG1_PORT PORTA ++#define SEG1_PIN PINA ++#define SEG1_BIT 5 ++ ++#define SEG0_DDR DDRA ++#define SEG0_PORT PORTA ++#define SEG0_PIN PINA ++#define SEG0_BIT 4 ++ ++#define COM3_DDR DDRA ++#define COM3_PORT PORTA ++#define COM3_PIN PINA ++#define COM3_BIT 3 ++ ++#define COM2_DDR DDRA ++#define COM2_PORT PORTA ++#define COM2_PIN PINA ++#define COM2_BIT 2 ++ ++#define COM1_DDR DDRA ++#define COM1_PORT PORTA ++#define COM1_PIN PINA ++#define COM1_BIT 1 ++ ++#define COM0_DDR DDRA ++#define COM0_PORT PORTA ++#define COM0_PIN PINA ++#define COM0_BIT 0 ++ ++#define ADC7_DDR DDRF ++#define ADC7_PORT PORTF ++#define ADC7_PIN PINF ++#define ADC7_BIT 7 ++ ++#define ADC6_DDR DDRF ++#define ADC6_PORT PORTF ++#define ADC6_PIN PINF ++#define ADC6_BIT 6 ++ ++#define TD0_DDR DDRF ++#define TD0_PORT PORTF ++#define TD0_PIN PINF ++#define TD0_BIT 6 ++ ++#define ADC5_DDR DDRF ++#define ADC5_PORT PORTF ++#define ADC5_PIN PINF ++#define ADC5_BIT 5 ++ ++#define ADC4_DDR DDRF ++#define ADC4_PORT PORTF ++#define ADC4_PIN PINF ++#define ADC4_BIT 4 ++ ++#define ADC3_DDR DDRF ++#define ADC3_PORT PORTF ++#define ADC3_PIN PINF ++#define ADC3_BIT 3 ++ ++#define ADC2_DDR DDRF ++#define ADC2_PORT PORTF ++#define ADC2_PIN PINF ++#define ADC2_BIT 2 ++ ++#define ADC1_DDR DDRF ++#define ADC1_PORT PORTF ++#define ADC1_PIN PINF ++#define ADC1_BIT 1 ++ ++#define ADC0_DDR DDRF ++#define ADC0_PORT PORTF ++#define ADC0_PIN PINF ++#define ADC0_BIT 0 ++ ++#endif /* _AVR_ATmega169PA_H_ */ ++ +diff --git a/include/avr/iom16a.h b/include/avr/iom16a.h +index 2093610..091bdba 100644 +--- a/include/avr/iom16a.h ++++ b/include/avr/iom16a.h +@@ -1,916 +1,916 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom16a.h 2248 2011-05-23 19:54:32Z joerg_wunsch $ */ +- +-/* avr/iom16a.h - definitions for ATmega16A */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom16a.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATmega16A_H_ +-#define _AVR_ATmega16A_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define TWBR _SFR_IO8(0x00) +-#define TWBR0 0 +-#define TWBR1 1 +-#define TWBR2 2 +-#define TWBR3 3 +-#define TWBR4 4 +-#define TWBR5 5 +-#define TWBR6 6 +-#define TWBR7 7 +- +-#define TWSR _SFR_IO8(0x01) +-#define TWPS0 0 +-#define TWPS1 1 +-#define TWS3 3 +-#define TWS4 4 +-#define TWS5 5 +-#define TWS6 6 +-#define TWS7 7 +- +-#define TWAR _SFR_IO8(0x02) +-#define TWGCE 0 +-#define TWA0 1 +-#define TWA1 2 +-#define TWA2 3 +-#define TWA3 4 +-#define TWA4 5 +-#define TWA5 6 +-#define TWA6 7 +- +-#define TWDR _SFR_IO8(0x03) +-#define TWD0 0 +-#define TWD1 1 +-#define TWD2 2 +-#define TWD3 3 +-#define TWD4 4 +-#define TWD5 5 +-#define TWD6 6 +-#define TWD7 7 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x04) +-#endif +-#define ADCW _SFR_IO16(0x04) +- +-#define ADCL _SFR_IO8(0x04) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_IO8(0x05) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_IO8(0x06) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADMUX _SFR_IO8(0x07) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define ACSR _SFR_IO8(0x08) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define UBRRL _SFR_IO8(0x09) +-#define UBRR0 0 +-#define UBRR1 1 +-#define UBRR2 2 +-#define UBRR3 3 +-#define UBRR4 4 +-#define UBRR5 5 +-#define UBRR6 6 +-#define UBRR7 7 +- +-#define UCSRB _SFR_IO8(0x0A) +-#define TXB8 0 +-#define RXB8 1 +-#define UCSZ2 2 +-#define TXEN 3 +-#define RXEN 4 +-#define UDRIE 5 +-#define TXCIE 6 +-#define RXCIE 7 +- +-#define UCSRA _SFR_IO8(0x0B) +-#define MPCM 0 +-#define U2X 1 +-#define UPE 2 +-#define DOR 3 +-#define FE 4 +-#define UDRE 5 +-#define TXC 6 +-#define RXC 7 +- +-#define UDR _SFR_IO8(0x0C) +-#define UDR0 0 +-#define UDR1 1 +-#define UDR2 2 +-#define UDR3 3 +-#define UDR4 4 +-#define UDR5 5 +-#define UDR6 6 +-#define UDR7 7 +- +-#define SPCR _SFR_IO8(0x0D) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x0E) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x0F) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define PIND _SFR_IO8(0x10) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x11) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x12) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define PINC _SFR_IO8(0x13) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +-#define PINC7 7 +- +-#define DDRC _SFR_IO8(0x14) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC3 3 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +-#define DDC7 7 +- +-#define PORTC _SFR_IO8(0x15) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC3 3 +-#define PORTC4 4 +-#define PORTC5 5 +-#define PORTC6 6 +-#define PORTC7 7 +- +-#define PINB _SFR_IO8(0x16) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x17) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x18) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINA _SFR_IO8(0x19) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +-#define PINA4 4 +-#define PINA5 5 +-#define PINA6 6 +-#define PINA7 7 +- +-#define DDRA _SFR_IO8(0x1A) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +-#define DDA4 4 +-#define DDA5 5 +-#define DDA6 6 +-#define DDA7 7 +- +-#define PORTA _SFR_IO8(0x1B) +-#define PORTA0 0 +-#define PORTA1 1 +-#define PORTA2 2 +-#define PORTA3 3 +-#define PORTA4 4 +-#define PORTA5 5 +-#define PORTA6 6 +-#define PORTA7 7 +- +-#define EECR _SFR_IO8(0x1C) +-#define EERE 0 +-#define EEWE 1 +-#define EEMWE 2 +-#define EERIE 3 +- +-#define EEDR _SFR_IO8(0x1D) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x1E) +- +-#define EEARL _SFR_IO8(0x1E) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x1F) +-#define EEAR8 0 +- +-#define UBRRH _SFR_IO8(0x20) +-#define UBRR8 0 +-#define UBRR9 1 +-#define UBRR10 2 +-#define UBRR11 3 +- +-#define UCSRC _SFR_IO8(0x20) +-#define UCPOL 0 +-#define UCSZ0 1 +-#define UCSZ1 2 +-#define USBS 3 +-#define UPM0 4 +-#define UPM1 5 +-#define UMSEL 6 +-#define URSEL 7 +- +-#define WDTCR _SFR_IO8(0x21) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDTOE 4 +- +-#define ASSR _SFR_IO8(0x22) +-#define TCR2UB 0 +-#define OCR2UB 1 +-#define TCN2UB 2 +-#define AS2 3 +- +-#define OCR2 _SFR_IO8(0x23) +-#define OCR2_0 0 +-#define OCR2_1 1 +-#define OCR2_2 2 +-#define OCR2_3 3 +-#define OCR2_4 4 +-#define OCR2_5 5 +-#define OCR2_6 6 +-#define OCR2_7 7 +- +-#define TCNT2 _SFR_IO8(0x24) +-#define TCNT2_0 0 +-#define TCNT2_1 1 +-#define TCNT2_2 2 +-#define TCNT2_3 3 +-#define TCNT2_4 4 +-#define TCNT2_5 5 +-#define TCNT2_6 6 +-#define TCNT2_7 7 +- +-#define TCCR2 _SFR_IO8(0x25) +-#define CS20 0 +-#define CS21 1 +-#define CS22 2 +-#define WGM21 3 +-#define COM20 4 +-#define COM21 5 +-#define WGM20 6 +-#define FOC2 7 +- +-#define ICR1 _SFR_IO16(0x26) +- +-#define ICR1L _SFR_IO8(0x26) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_IO8(0x27) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1B _SFR_IO16(0x28) +- +-#define OCR1BL _SFR_IO8(0x28) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_IO8(0x29) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define OCR1A _SFR_IO16(0x2A) +- +-#define OCR1AL _SFR_IO8(0x2A) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_IO8(0x2B) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define TCNT1 _SFR_IO16(0x2C) +- +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_IO8(0x2D) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define TCCR1B _SFR_IO8(0x2E) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1A _SFR_IO8(0x2F) +-#define WGM10 0 +-#define WGM11 1 +-#define FOC1B 2 +-#define FOC1A 3 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define SFIOR _SFR_IO8(0x30) +-#define PSR10 0 +-#define PSR2 1 +-#define PUD 2 +-#define ACME 3 +-#define ADTS0 5 +-#define ADTS1 6 +-#define ADTS2 7 +- +-#define OSCCAL _SFR_IO8(0x31) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define OCDR _SFR_IO8(0x31) +-#define OCDR0 0 +-#define OCDR1 1 +-#define OCDR2 2 +-#define OCDR3 3 +-#define OCDR4 4 +-#define OCDR5 5 +-#define OCDR6 6 +-#define OCDR7 7 +- +-#define TCNT0 _SFR_IO8(0x32) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define TCCR0 _SFR_IO8(0x33) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM01 3 +-#define COM00 4 +-#define COM01 5 +-#define WGM00 6 +-#define FOC0 7 +- +-#define MCUCSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +-#define JTRF 4 +-#define ISC2 6 +-#define JTD 7 +- +-#define MCUCR _SFR_IO8(0x35) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define SM0 4 +-#define SM1 5 +-#define SE 6 +-#define SM2 7 +- +-#define TWCR _SFR_IO8(0x36) +-#define TWIE 0 +-#define TWEN 2 +-#define TWWC 3 +-#define TWSTO 4 +-#define TWSTA 5 +-#define TWEA 6 +-#define TWINT 7 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define TIFR _SFR_IO8(0x38) +-#define TOV0 0 +-#define OCF0 1 +-#define TOV1 2 +-#define OCF1B 3 +-#define OCF1A 4 +-#define ICF1 5 +-#define TOV2 6 +-#define OCF2 7 +- +-#define TIMSK _SFR_IO8(0x39) +-#define TOIE0 0 +-#define OCIE0 1 +-#define TOIE1 2 +-#define OCIE1B 3 +-#define OCIE1A 4 +-#define TICIE1 5 +-#define TOIE2 6 +-#define OCIE2 7 +- +-#define GIFR _SFR_IO8(0x3A) +-#define INTF2 5 +-#define INTF0 6 +-#define INTF1 7 +- +-#define GICR _SFR_IO8(0x3B) +-#define IVCE 0 +-#define IVSEL 1 +-#define INT2 5 +-#define INT0 6 +-#define INT1 7 +- +-#define OCR0 _SFR_IO8(0x3C) +-#define OCR0_0 0 +-#define OCR0_1 1 +-#define OCR0_2 2 +-#define OCR0_3 3 +-#define OCR0_4 4 +-#define OCR0_5 5 +-#define OCR0_6 6 +-#define OCR0_7 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ +-#define TIMER2_COMP_vect_num 3 +-#define TIMER2_COMP_vect _VECTOR(3) /* Timer/Counter2 Compare Match */ +-#define TIMER2_OVF_vect_num 4 +-#define TIMER2_OVF_vect _VECTOR(4) /* Timer/Counter2 Overflow */ +-#define TIMER1_CAPT_vect_num 5 +-#define TIMER1_CAPT_vect _VECTOR(5) /* Timer/Counter1 Capture Event */ +-#define TIMER1_COMPA_vect_num 6 +-#define TIMER1_COMPA_vect _VECTOR(6) /* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPB_vect_num 7 +-#define TIMER1_COMPB_vect _VECTOR(7) /* Timer/Counter1 Compare Match B */ +-#define TIMER1_OVF_vect_num 8 +-#define TIMER1_OVF_vect _VECTOR(8) /* Timer/Counter1 Overflow */ +-#define TIMER0_OVF_vect_num 9 +-#define TIMER0_OVF_vect _VECTOR(9) /* Timer/Counter0 Overflow */ +-#define SPISTC_vect_num 10 +-#define SPISTC_vect _VECTOR(10) /* Serial Transfer Complete */ +- +-/* The following vectors use an inconsistent (to the ATmega16 etc.) +- naming scheme. The inconsistent names are preserved here for softwares +- that already use them: */ +-#define USARTRXC_vect_num 11 +-#define USARTRXC_vect _VECTOR(11) /* USART, Rx Complete */ +-#define USARTUDRE_vect_num 12 +-#define USARTUDRE_vect _VECTOR(12) /* USART Data Register Empty */ +-#define USARTTXC_vect_num 13 +-#define USARTTXC_vect _VECTOR(13) /* USART, Tx Complete */ +-/* The "classic" designators: */ +-#define USART_RXC_vect_num 11 +-#define USART_RXC_vect _VECTOR(11) /* USART, Rx Complete */ +-#define USART_UDRE_vect_num 12 +-#define USART_UDRE_vect _VECTOR(12) /* USART Data Register Empty */ +-#define USART_TXC_vect_num 13 +-#define USART_TXC_vect _VECTOR(13) /* USART, Tx Complete */ +- +-#define ADC_vect_num 14 +-#define ADC_vect _VECTOR(14) /* ADC Conversion Complete */ +-#define EE_RDY_vect_num 15 +-#define EE_RDY_vect _VECTOR(15) /* EEPROM Ready */ +-#define ANA_COMP_vect_num 16 +-#define ANA_COMP_vect _VECTOR(16) /* Analog Comparator */ +-#define TWI_vect_num 17 +-#define TWI_vect _VECTOR(17) /* 2-wire Serial Interface */ +-#define INT2_vect_num 18 +-#define INT2_vect _VECTOR(18) /* External Interrupt Request 2 */ +-#define TIMER0_COMP_vect_num 19 +-#define TIMER0_COMP_vect _VECTOR(19) /* Timer/Counter0 Compare Match */ +-#define SPM_RDY_vect_num 20 +-#define SPM_RDY_vect _VECTOR(20) /* Store Program Memory Ready */ +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (21 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (128) +-#define RAMSTART (0x60) +-#define RAMSIZE (1024) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x1FF) +-#define E2PAGESIZE (4) +-#define FLASHEND (0x3FFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 2 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_BODEN (unsigned char)~_BV(6) /* Brown out detector enable */ +-#define FUSE_BODLEVEL (unsigned char)~_BV(7) /* Brown out detector trigger level */ +-#define LFUSE_DEFAULT (FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_CKOPT (unsigned char)~_BV(4) /* Oscillator Options */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ +-#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ +-#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x94 +-#define SIGNATURE_2 0x03 +- +- +-/* Device Pin Definitions */ +-#define MOSI_DDR DDRB +-#define MOSI_PORT PORTB +-#define MOSI_PIN PINB +-#define MOSI_BIT 5 +- +-#define MISO_DDR DDRB +-#define MISO_PORT PORTB +-#define MISO_PIN PINB +-#define MISO_BIT 6 +- +-#define PB7_SCK_DDR DDRB7_SCK +-#define PB7_SCK_PORT PORTB7_SCK +-#define PB7_SCK_PIN PINB7_SCK +-#define PB7_SCK_BIT 7_SCK +- +-#define RXD_DDR DDRD +-#define RXD_PORT PORTD +-#define RXD_PIN PIND +-#define RXD_BIT 0 +- +-#define TXD_DDR DDRD +-#define TXD_PORT PORTD +-#define TXD_PIN PIND +-#define TXD_BIT 1 +- +-#define INT0_DDR DDRD +-#define INT0_PORT PORTD +-#define INT0_PIN PIND +-#define INT0_BIT 2 +- +-#define INT1_DDR DDRD +-#define INT1_PORT PORTD +-#define INT1_PIN PIND +-#define INT1_BIT 3 +- +-#define OC1B_DDR DDRD +-#define OC1B_PORT PORTD +-#define OC1B_PIN PIND +-#define OC1B_BIT 4 +- +-#define OC1A_DDR DDRD +-#define OC1A_PORT PORTD +-#define OC1A_PIN PIND +-#define OC1A_BIT 5 +- +-#define ICP_DDR DDRD +-#define ICP_PORT PORTD +-#define ICP_PIN PIND +-#define ICP_BIT 6 +- +-#define OC2_DDR DDRD +-#define OC2_PORT PORTD +-#define OC2_PIN PIND +-#define OC2_BIT 7 +- +-#define SCL_DDR DDRC +-#define SCL_PORT PORTC +-#define SCL_PIN PINC +-#define SCL_BIT 0 +- +-#define SDA_DDR DDRC +-#define SDA_PORT PORTC +-#define SDA_PIN PINC +-#define SDA_BIT 1 +- +-#define PC3_DDR DDRC +-#define PC3_PORT PORTC +-#define PC3_PIN PINC +-#define PC3_BIT 3 +- +-#define PC4_DDR DDRC +-#define PC4_PORT PORTC +-#define PC4_PIN PINC +-#define PC4_BIT 4 +- +-#define PC5_DDR DDRC +-#define PC5_PORT PORTC +-#define PC5_PIN PINC +-#define PC5_BIT 5 +- +-#define ADC7_DDR DDRA +-#define ADC7_PORT PORTA +-#define ADC7_PIN PINA +-#define ADC7_BIT 7 +- +-#define ADC6_DDR DDRA +-#define ADC6_PORT PORTA +-#define ADC6_PIN PINA +-#define ADC6_BIT 6 +- +-#define ADc5_DDR DDRA +-#define ADc5_PORT PORTA +-#define ADc5_PIN PINA +-#define ADc5_BIT 5 +- +-#define ADC4_DDR DDRA +-#define ADC4_PORT PORTA +-#define ADC4_PIN PINA +-#define ADC4_BIT 4 +- +-#define ADC3_DDR DDRA +-#define ADC3_PORT PORTA +-#define ADC3_PIN PINA +-#define ADC3_BIT 3 +- +-#define ADC2_DDR DDRA +-#define ADC2_PORT PORTA +-#define ADC2_PIN PINA +-#define ADC2_BIT 2 +- +-#define ADC1_DDR DDRA +-#define ADC1_PORT PORTA +-#define ADC1_PIN PINA +-#define ADC1_BIT 1 +- +-#define ADC0_DDR DDRA +-#define ADC0_PORT PORTA +-#define ADC0_PIN PINA +-#define ADC0_BIT 0 +- +-#define T0_DDR DDRB +-#define T0_PORT PORTB +-#define T0_PIN PINB +-#define T0_BIT 0 +- +-#define T1_DDR DDRB +-#define T1_PORT PORTB +-#define T1_PIN PINB +-#define T1_BIT 1 +- +-#define AIN0_DDR DDRB +-#define AIN0_PORT PORTB +-#define AIN0_PIN PINB +-#define AIN0_BIT 2 +- +-#define AIN1_DDR DDRB +-#define AIN1_PORT PORTB +-#define AIN1_PIN PINB +-#define AIN1_BIT 3 +- +-#define SS_DDR DDRB +-#define SS_PORT PORTB +-#define SS_PIN PINB +-#define SS_BIT 4 +- +-#endif /* _AVR_ATmega16A_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom16a.h 2248 2011-05-23 19:54:32Z joerg_wunsch $ */ ++ ++/* avr/iom16a.h - definitions for ATmega16A */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom16a.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATmega16A_H_ ++#define _AVR_ATmega16A_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define TWBR _SFR_IO8(0x00) ++#define TWBR0 0 ++#define TWBR1 1 ++#define TWBR2 2 ++#define TWBR3 3 ++#define TWBR4 4 ++#define TWBR5 5 ++#define TWBR6 6 ++#define TWBR7 7 ++ ++#define TWSR _SFR_IO8(0x01) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_IO8(0x02) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_IO8(0x03) ++#define TWD0 0 ++#define TWD1 1 ++#define TWD2 2 ++#define TWD3 3 ++#define TWD4 4 ++#define TWD5 5 ++#define TWD6 6 ++#define TWD7 7 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCW _SFR_IO16(0x04) ++ ++#define ADCL _SFR_IO8(0x04) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_IO8(0x05) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_IO8(0x06) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADMUX _SFR_IO8(0x07) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define ACSR _SFR_IO8(0x08) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define UBRRL _SFR_IO8(0x09) ++#define UBRR0 0 ++#define UBRR1 1 ++#define UBRR2 2 ++#define UBRR3 3 ++#define UBRR4 4 ++#define UBRR5 5 ++#define UBRR6 6 ++#define UBRR7 7 ++ ++#define UCSRB _SFR_IO8(0x0A) ++#define TXB8 0 ++#define RXB8 1 ++#define UCSZ2 2 ++#define TXEN 3 ++#define RXEN 4 ++#define UDRIE 5 ++#define TXCIE 6 ++#define RXCIE 7 ++ ++#define UCSRA _SFR_IO8(0x0B) ++#define MPCM 0 ++#define U2X 1 ++#define UPE 2 ++#define DOR 3 ++#define FE 4 ++#define UDRE 5 ++#define TXC 6 ++#define RXC 7 ++ ++#define UDR _SFR_IO8(0x0C) ++#define UDR0 0 ++#define UDR1 1 ++#define UDR2 2 ++#define UDR3 3 ++#define UDR4 4 ++#define UDR5 5 ++#define UDR6 6 ++#define UDR7 7 ++ ++#define SPCR _SFR_IO8(0x0D) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x0E) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x0F) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define PIND _SFR_IO8(0x10) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x11) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x12) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define PINC _SFR_IO8(0x13) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++#define PINC7 7 ++ ++#define DDRC _SFR_IO8(0x14) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++#define DDC7 7 ++ ++#define PORTC _SFR_IO8(0x15) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC3 3 ++#define PORTC4 4 ++#define PORTC5 5 ++#define PORTC6 6 ++#define PORTC7 7 ++ ++#define PINB _SFR_IO8(0x16) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x17) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x18) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINA _SFR_IO8(0x19) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++#define PINA4 4 ++#define PINA5 5 ++#define PINA6 6 ++#define PINA7 7 ++ ++#define DDRA _SFR_IO8(0x1A) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++#define DDA4 4 ++#define DDA5 5 ++#define DDA6 6 ++#define DDA7 7 ++ ++#define PORTA _SFR_IO8(0x1B) ++#define PORTA0 0 ++#define PORTA1 1 ++#define PORTA2 2 ++#define PORTA3 3 ++#define PORTA4 4 ++#define PORTA5 5 ++#define PORTA6 6 ++#define PORTA7 7 ++ ++#define EECR _SFR_IO8(0x1C) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++ ++#define EEDR _SFR_IO8(0x1D) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x1E) ++ ++#define EEARL _SFR_IO8(0x1E) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x1F) ++#define EEAR8 0 ++ ++#define UBRRH _SFR_IO8(0x20) ++#define UBRR8 0 ++#define UBRR9 1 ++#define UBRR10 2 ++#define UBRR11 3 ++ ++#define UCSRC _SFR_IO8(0x20) ++#define UCPOL 0 ++#define UCSZ0 1 ++#define UCSZ1 2 ++#define USBS 3 ++#define UPM0 4 ++#define UPM1 5 ++#define UMSEL 6 ++#define URSEL 7 ++ ++#define WDTCR _SFR_IO8(0x21) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDTOE 4 ++ ++#define ASSR _SFR_IO8(0x22) ++#define TCR2UB 0 ++#define OCR2UB 1 ++#define TCN2UB 2 ++#define AS2 3 ++ ++#define OCR2 _SFR_IO8(0x23) ++#define OCR2_0 0 ++#define OCR2_1 1 ++#define OCR2_2 2 ++#define OCR2_3 3 ++#define OCR2_4 4 ++#define OCR2_5 5 ++#define OCR2_6 6 ++#define OCR2_7 7 ++ ++#define TCNT2 _SFR_IO8(0x24) ++#define TCNT2_0 0 ++#define TCNT2_1 1 ++#define TCNT2_2 2 ++#define TCNT2_3 3 ++#define TCNT2_4 4 ++#define TCNT2_5 5 ++#define TCNT2_6 6 ++#define TCNT2_7 7 ++ ++#define TCCR2 _SFR_IO8(0x25) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM21 3 ++#define COM20 4 ++#define COM21 5 ++#define WGM20 6 ++#define FOC2 7 ++ ++#define ICR1 _SFR_IO16(0x26) ++ ++#define ICR1L _SFR_IO8(0x26) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_IO8(0x27) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1B _SFR_IO16(0x28) ++ ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_IO8(0x29) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define OCR1A _SFR_IO16(0x2A) ++ ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_IO8(0x2B) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define TCNT1 _SFR_IO16(0x2C) ++ ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_IO8(0x2D) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define TCCR1B _SFR_IO8(0x2E) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1A _SFR_IO8(0x2F) ++#define WGM10 0 ++#define WGM11 1 ++#define FOC1B 2 ++#define FOC1A 3 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define SFIOR _SFR_IO8(0x30) ++#define PSR10 0 ++#define PSR2 1 ++#define PUD 2 ++#define ACME 3 ++#define ADTS0 5 ++#define ADTS1 6 ++#define ADTS2 7 ++ ++#define OSCCAL _SFR_IO8(0x31) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCDR7 7 ++ ++#define TCNT0 _SFR_IO8(0x32) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define TCCR0 _SFR_IO8(0x33) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM01 3 ++#define COM00 4 ++#define COM01 5 ++#define WGM00 6 ++#define FOC0 7 ++ ++#define MCUCSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define JTRF 4 ++#define ISC2 6 ++#define JTD 7 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define SM0 4 ++#define SM1 5 ++#define SE 6 ++#define SM2 7 ++ ++#define TWCR _SFR_IO8(0x36) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define TIFR _SFR_IO8(0x38) ++#define TOV0 0 ++#define OCF0 1 ++#define TOV1 2 ++#define OCF1B 3 ++#define OCF1A 4 ++#define ICF1 5 ++#define TOV2 6 ++#define OCF2 7 ++ ++#define TIMSK _SFR_IO8(0x39) ++#define TOIE0 0 ++#define OCIE0 1 ++#define TOIE1 2 ++#define OCIE1B 3 ++#define OCIE1A 4 ++#define TICIE1 5 ++#define TOIE2 6 ++#define OCIE2 7 ++ ++#define GIFR _SFR_IO8(0x3A) ++#define INTF2 5 ++#define INTF0 6 ++#define INTF1 7 ++ ++#define GICR _SFR_IO8(0x3B) ++#define IVCE 0 ++#define IVSEL 1 ++#define INT2 5 ++#define INT0 6 ++#define INT1 7 ++ ++#define OCR0 _SFR_IO8(0x3C) ++#define OCR0_0 0 ++#define OCR0_1 1 ++#define OCR0_2 2 ++#define OCR0_3 3 ++#define OCR0_4 4 ++#define OCR0_5 5 ++#define OCR0_6 6 ++#define OCR0_7 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ ++#define TIMER2_COMP_vect_num 3 ++#define TIMER2_COMP_vect _VECTOR(3) /* Timer/Counter2 Compare Match */ ++#define TIMER2_OVF_vect_num 4 ++#define TIMER2_OVF_vect _VECTOR(4) /* Timer/Counter2 Overflow */ ++#define TIMER1_CAPT_vect_num 5 ++#define TIMER1_CAPT_vect _VECTOR(5) /* Timer/Counter1 Capture Event */ ++#define TIMER1_COMPA_vect_num 6 ++#define TIMER1_COMPA_vect _VECTOR(6) /* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPB_vect_num 7 ++#define TIMER1_COMPB_vect _VECTOR(7) /* Timer/Counter1 Compare Match B */ ++#define TIMER1_OVF_vect_num 8 ++#define TIMER1_OVF_vect _VECTOR(8) /* Timer/Counter1 Overflow */ ++#define TIMER0_OVF_vect_num 9 ++#define TIMER0_OVF_vect _VECTOR(9) /* Timer/Counter0 Overflow */ ++#define SPISTC_vect_num 10 ++#define SPISTC_vect _VECTOR(10) /* Serial Transfer Complete */ ++ ++/* The following vectors use an inconsistent (to the ATmega16 etc.) ++ naming scheme. The inconsistent names are preserved here for softwares ++ that already use them: */ ++#define USARTRXC_vect_num 11 ++#define USARTRXC_vect _VECTOR(11) /* USART, Rx Complete */ ++#define USARTUDRE_vect_num 12 ++#define USARTUDRE_vect _VECTOR(12) /* USART Data Register Empty */ ++#define USARTTXC_vect_num 13 ++#define USARTTXC_vect _VECTOR(13) /* USART, Tx Complete */ ++/* The "classic" designators: */ ++#define USART_RXC_vect_num 11 ++#define USART_RXC_vect _VECTOR(11) /* USART, Rx Complete */ ++#define USART_UDRE_vect_num 12 ++#define USART_UDRE_vect _VECTOR(12) /* USART Data Register Empty */ ++#define USART_TXC_vect_num 13 ++#define USART_TXC_vect _VECTOR(13) /* USART, Tx Complete */ ++ ++#define ADC_vect_num 14 ++#define ADC_vect _VECTOR(14) /* ADC Conversion Complete */ ++#define EE_RDY_vect_num 15 ++#define EE_RDY_vect _VECTOR(15) /* EEPROM Ready */ ++#define ANA_COMP_vect_num 16 ++#define ANA_COMP_vect _VECTOR(16) /* Analog Comparator */ ++#define TWI_vect_num 17 ++#define TWI_vect _VECTOR(17) /* 2-wire Serial Interface */ ++#define INT2_vect_num 18 ++#define INT2_vect _VECTOR(18) /* External Interrupt Request 2 */ ++#define TIMER0_COMP_vect_num 19 ++#define TIMER0_COMP_vect _VECTOR(19) /* Timer/Counter0 Compare Match */ ++#define SPM_RDY_vect_num 20 ++#define SPM_RDY_vect _VECTOR(20) /* Store Program Memory Ready */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (21 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (128) ++#define RAMSTART (0x60) ++#define RAMSIZE (1024) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x1FF) ++#define E2PAGESIZE (4) ++#define FLASHEND (0x3FFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 2 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_BODEN (unsigned char)~_BV(6) /* Brown out detector enable */ ++#define FUSE_BODLEVEL (unsigned char)~_BV(7) /* Brown out detector trigger level */ ++#define LFUSE_DEFAULT (FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_CKOPT (unsigned char)~_BV(4) /* Oscillator Options */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ ++#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ ++#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x03 ++ ++ ++/* Device Pin Definitions */ ++#define MOSI_DDR DDRB ++#define MOSI_PORT PORTB ++#define MOSI_PIN PINB ++#define MOSI_BIT 5 ++ ++#define MISO_DDR DDRB ++#define MISO_PORT PORTB ++#define MISO_PIN PINB ++#define MISO_BIT 6 ++ ++#define PB7_SCK_DDR DDRB7_SCK ++#define PB7_SCK_PORT PORTB7_SCK ++#define PB7_SCK_PIN PINB7_SCK ++#define PB7_SCK_BIT 7_SCK ++ ++#define RXD_DDR DDRD ++#define RXD_PORT PORTD ++#define RXD_PIN PIND ++#define RXD_BIT 0 ++ ++#define TXD_DDR DDRD ++#define TXD_PORT PORTD ++#define TXD_PIN PIND ++#define TXD_BIT 1 ++ ++#define INT0_DDR DDRD ++#define INT0_PORT PORTD ++#define INT0_PIN PIND ++#define INT0_BIT 2 ++ ++#define INT1_DDR DDRD ++#define INT1_PORT PORTD ++#define INT1_PIN PIND ++#define INT1_BIT 3 ++ ++#define OC1B_DDR DDRD ++#define OC1B_PORT PORTD ++#define OC1B_PIN PIND ++#define OC1B_BIT 4 ++ ++#define OC1A_DDR DDRD ++#define OC1A_PORT PORTD ++#define OC1A_PIN PIND ++#define OC1A_BIT 5 ++ ++#define ICP_DDR DDRD ++#define ICP_PORT PORTD ++#define ICP_PIN PIND ++#define ICP_BIT 6 ++ ++#define OC2_DDR DDRD ++#define OC2_PORT PORTD ++#define OC2_PIN PIND ++#define OC2_BIT 7 ++ ++#define SCL_DDR DDRC ++#define SCL_PORT PORTC ++#define SCL_PIN PINC ++#define SCL_BIT 0 ++ ++#define SDA_DDR DDRC ++#define SDA_PORT PORTC ++#define SDA_PIN PINC ++#define SDA_BIT 1 ++ ++#define PC3_DDR DDRC ++#define PC3_PORT PORTC ++#define PC3_PIN PINC ++#define PC3_BIT 3 ++ ++#define PC4_DDR DDRC ++#define PC4_PORT PORTC ++#define PC4_PIN PINC ++#define PC4_BIT 4 ++ ++#define PC5_DDR DDRC ++#define PC5_PORT PORTC ++#define PC5_PIN PINC ++#define PC5_BIT 5 ++ ++#define ADC7_DDR DDRA ++#define ADC7_PORT PORTA ++#define ADC7_PIN PINA ++#define ADC7_BIT 7 ++ ++#define ADC6_DDR DDRA ++#define ADC6_PORT PORTA ++#define ADC6_PIN PINA ++#define ADC6_BIT 6 ++ ++#define ADc5_DDR DDRA ++#define ADc5_PORT PORTA ++#define ADc5_PIN PINA ++#define ADc5_BIT 5 ++ ++#define ADC4_DDR DDRA ++#define ADC4_PORT PORTA ++#define ADC4_PIN PINA ++#define ADC4_BIT 4 ++ ++#define ADC3_DDR DDRA ++#define ADC3_PORT PORTA ++#define ADC3_PIN PINA ++#define ADC3_BIT 3 ++ ++#define ADC2_DDR DDRA ++#define ADC2_PORT PORTA ++#define ADC2_PIN PINA ++#define ADC2_BIT 2 ++ ++#define ADC1_DDR DDRA ++#define ADC1_PORT PORTA ++#define ADC1_PIN PINA ++#define ADC1_BIT 1 ++ ++#define ADC0_DDR DDRA ++#define ADC0_PORT PORTA ++#define ADC0_PIN PINA ++#define ADC0_BIT 0 ++ ++#define T0_DDR DDRB ++#define T0_PORT PORTB ++#define T0_PIN PINB ++#define T0_BIT 0 ++ ++#define T1_DDR DDRB ++#define T1_PORT PORTB ++#define T1_PIN PINB ++#define T1_BIT 1 ++ ++#define AIN0_DDR DDRB ++#define AIN0_PORT PORTB ++#define AIN0_PIN PINB ++#define AIN0_BIT 2 ++ ++#define AIN1_DDR DDRB ++#define AIN1_PORT PORTB ++#define AIN1_PIN PINB ++#define AIN1_BIT 3 ++ ++#define SS_DDR DDRB ++#define SS_PORT PORTB ++#define SS_PIN PINB ++#define SS_BIT 4 ++ ++#endif /* _AVR_ATmega16A_H_ */ ++ +diff --git a/include/avr/iom16hva.h b/include/avr/iom16hva.h +index c278cc8..e0a14db 100644 +--- a/include/avr/iom16hva.h ++++ b/include/avr/iom16hva.h +@@ -1,75 +1,76 @@ +-/* Copyright (c) 2007, Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom16hva.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ +- +-/* iom16hva.h - definitions for ATmega16HVA. */ +- +-#ifndef _AVR_IOM16HVA_H_ +-#define _AVR_IOM16HVA_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 128 +-#define RAMEND 0x2FF +-#define XRAMEND RAMEND +-#define E2END 0xFF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x3FFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 1 +- +-/* Low Fuse Byte */ +-#define FUSE_SUT0 (unsigned char)~_BV(0) +-#define FUSE_SUT1 (unsigned char)~_BV(1) +-#define FUSE_SUT2 (unsigned char)~_BV(2) +-#define FUSE_SELFPRGEN (unsigned char)~_BV(3) +-#define FUSE_DWEN (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_EESAVE (unsigned char)~_BV(6) +-#define FUSE_WDTON (unsigned char)~_BV(7) +-#define FUSE_DEFAULT (FUSE_SPIEN) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x94 +-#define SIGNATURE_2 0x0C +- +- +-#endif /* _AVR_IOM16HVA_H_ */ ++/* Copyright (c) 2007, Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom16hva.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ ++ ++/* iom16hva.h - definitions for ATmega16HVA. */ ++ ++#ifndef _AVR_IOM16HVA_H_ ++#define _AVR_IOM16HVA_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 128 ++#define RAMSTART 0x100 ++#define RAMEND 0x2FF ++#define XRAMEND RAMEND ++#define E2END 0xFF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x3FFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT0 (unsigned char)~_BV(0) ++#define FUSE_SUT1 (unsigned char)~_BV(1) ++#define FUSE_SUT2 (unsigned char)~_BV(2) ++#define FUSE_SELFPRGEN (unsigned char)~_BV(3) ++#define FUSE_DWEN (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_EESAVE (unsigned char)~_BV(6) ++#define FUSE_WDTON (unsigned char)~_BV(7) ++#define FUSE_DEFAULT (FUSE_SPIEN) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x0C ++ ++ ++#endif /* _AVR_IOM16HVA_H_ */ +diff --git a/include/avr/iom16hva2.h b/include/avr/iom16hva2.h +index d7c1274..ecbebbb 100644 +--- a/include/avr/iom16hva2.h ++++ b/include/avr/iom16hva2.h +@@ -1,871 +1,871 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom16hva2.h 2192 2010-11-08 13:53:24Z arcanum $ */ +- +-/* avr/iom16hva2.h - definitions for ATmega16HVA2 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom16hva2.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATmega16HVA2_H_ +-#define _AVR_ATmega16HVA2_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA0 0 +-#define PINA1 1 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA0 0 +-#define DDA1 1 +- +-#define PORTA _SFR_IO8(0x02) +-#define PORTA0 0 +-#define PORTA1 1 +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +-#define ICF0 3 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 3 +- +-#define OSICSR _SFR_IO8(0x17) +-#define OSIEN 0 +-#define OSIST 1 +-#define OSISEL0 4 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +-#define INTF2 2 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +-#define INT2 2 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSRSYNC 0 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define ICS0 3 +-#define ICES0 4 +-#define ICNC0 5 +-#define ICEN0 6 +-#define TCW0 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +- +-#define TCNT0 _SFR_IO16(0x26) +- +-#define TCNT0L _SFR_IO8(0x26) +-#define TCNT0L0 0 +-#define TCNT0L1 1 +-#define TCNT0L2 2 +-#define TCNT0L3 3 +-#define TCNT0L4 4 +-#define TCNT0L5 5 +-#define TCNT0L6 6 +-#define TCNT0L7 7 +- +-#define TCNT0H _SFR_IO8(0x27) +-#define TCNT0H0 0 +-#define TCNT0H1 1 +-#define TCNT0H2 2 +-#define TCNT0H3 3 +-#define TCNT0H4 4 +-#define TCNT0H5 5 +-#define TCNT0H6 6 +-#define TCNT0H7 7 +- +-#define OCR0A _SFR_IO8(0x28) +-#define OCR0A0 0 +-#define OCR0A1 1 +-#define OCR0A2 2 +-#define OCR0A3 3 +-#define OCR0A4 4 +-#define OCR0A5 5 +-#define OCR0A6 6 +-#define OCR0A7 7 +- +-#define OCR0B _SFR_IO8(0x29) +-#define OCR0B0 0 +-#define OCR0B1 1 +-#define OCR0B2 2 +-#define OCR0B3 3 +-#define OCR0B4 4 +-#define OCR0B5 5 +-#define OCR0B6 6 +-#define OCR0B7 7 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define DWDR _SFR_IO8(0x31) +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BODRF 2 +-#define WDRF 3 +-#define OCDRF 4 +- +-#define MCUCR _SFR_IO8(0x35) +-#define PUD 4 +-#define CKOE 5 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define RFLB 3 +-#define CTPB 4 +-#define SIGRD 5 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPCE 7 +- +-#define PRR0 _SFR_MEM8(0x64) +-#define PRVADC 0 +-#define PRTIM0 1 +-#define PRTIM1 2 +-#define PRSPI 3 +-#define PRVRM 5 +- +-#define FOSCCAL _SFR_MEM8(0x66) +-#define FCAL0 0 +-#define FCAL1 1 +-#define FCAL2 2 +-#define FCAL3 3 +-#define FCAL4 4 +-#define FCAL5 5 +-#define FCAL6 6 +-#define FCAL7 7 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define ISC20 4 +-#define ISC21 5 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +-#define ICIE0 3 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 3 +- +-#define VADC _SFR_MEM16(0x78) +- +-#define VADCL _SFR_MEM8(0x78) +-#define VADC0 0 +-#define VADC1 1 +-#define VADC2 2 +-#define VADC3 3 +-#define VADC4 4 +-#define VADC5 5 +-#define VADC6 6 +-#define VADC7 7 +- +-#define VADCH _SFR_MEM8(0x79) +-#define VADC8 0 +-#define VADC9 1 +-#define VADC10 2 +-#define VADC11 3 +- +-#define VADCSR _SFR_MEM8(0x7A) +-#define VADCCIE 0 +-#define VADCCIF 1 +-#define VADSC 2 +-#define VADEN 3 +- +-#define VADMUX _SFR_MEM8(0x7C) +-#define VADMUX0 0 +-#define VADMUX1 1 +-#define VADMUX2 2 +-#define VADMUX3 3 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define PA0DID 0 +-#define PA1DID 1 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define ICS1 3 +-#define ICES1 4 +-#define ICNC1 5 +-#define ICEN1 6 +-#define TCW1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define OCR1A _SFR_MEM8(0x88) +-#define OCR1A0 0 +-#define OCR1A1 1 +-#define OCR1A2 2 +-#define OCR1A3 3 +-#define OCR1A4 4 +-#define OCR1A5 5 +-#define OCR1A6 6 +-#define OCR1A7 7 +- +-#define OCR1B _SFR_MEM8(0x89) +-#define OCR1B0 0 +-#define OCR1B1 1 +-#define OCR1B2 2 +-#define OCR1B3 3 +-#define OCR1B4 4 +-#define OCR1B5 5 +-#define OCR1B6 6 +-#define OCR1B7 7 +- +-#define ROCR _SFR_MEM8(0xC8) +-#define ROCWIE 0 +-#define ROCWIF 1 +-#define ROCS 7 +- +-#define BGCCR _SFR_MEM8(0xD0) +-#define BGCC0 0 +-#define BGCC1 1 +-#define BGCC2 2 +-#define BGCC3 3 +-#define BGCC4 4 +-#define BGCC5 5 +-#define BGD 7 +- +-#define BGCRR _SFR_MEM8(0xD1) +-#define BGCR0 0 +-#define BGCR1 1 +-#define BGCR2 2 +-#define BGCR3 3 +-#define BGCR4 4 +-#define BGCR5 5 +-#define BGCR6 6 +-#define BGCR7 7 +- +-#define CADAC0 _SFR_MEM8(0xE0) +-#define CADAC00 0 +-#define CADAC01 1 +-#define CADAC02 2 +-#define CADAC03 3 +-#define CADAC04 4 +-#define CADAC05 5 +-#define CADAC06 6 +-#define CADAC07 7 +- +-#define CADAC1 _SFR_MEM8(0xE1) +-#define CADAC08 0 +-#define CADAC09 1 +-#define CADAC10 2 +-#define CADAC11 3 +-#define CADAC12 4 +-#define CADAC13 5 +-#define CADAC14 6 +-#define CADAC15 7 +- +-#define CADAC2 _SFR_MEM8(0xE2) +-#define CADAC16 0 +-#define CADAC17 1 +-#define CADAC18 2 +-#define CADAC19 3 +-#define CADAC20 4 +-#define CADAC21 5 +-#define CADAC22 6 +-#define CADAC23 7 +- +-#define CADAC3 _SFR_MEM8(0xE3) +-#define CADAC24 0 +-#define CADAC25 1 +-#define CADAC26 2 +-#define CADAC27 3 +-#define CADAC28 4 +-#define CADAC29 5 +-#define CADAC30 6 +-#define CADAC31 7 +- +-#define CADCSRA _SFR_MEM8(0xE4) +-#define CADSE 0 +-#define CADSI0 1 +-#define CADSI1 2 +-#define CADAS0 3 +-#define CADAS1 4 +-#define CADUB 5 +-#define CADPOL 6 +-#define CADEN 7 +- +-#define CADCSRB _SFR_MEM8(0xE5) +-#define CADICIF 0 +-#define CADRCIF 1 +-#define CADACIF 2 +-#define CADICIE 4 +-#define CADRCIE 5 +-#define CADACIE 6 +- +-#define CADRC _SFR_MEM8(0xE6) +-#define CADRC0 0 +-#define CADRC1 1 +-#define CADRC2 2 +-#define CADRC3 3 +-#define CADRC4 4 +-#define CADRC5 5 +-#define CADRC6 6 +-#define CADRC7 7 +- +-#define CADIC _SFR_MEM16(0xE8) +- +-#define CADICL _SFR_MEM8(0xE8) +-#define CADICL0 0 +-#define CADICL1 1 +-#define CADICL2 2 +-#define CADICL3 3 +-#define CADICL4 4 +-#define CADICL5 5 +-#define CADICL6 6 +-#define CADICL7 7 +- +-#define CADICH _SFR_MEM8(0xE9) +-#define CADICH0 0 +-#define CADICH1 1 +-#define CADICH2 2 +-#define CADICH3 3 +-#define CADICH4 4 +-#define CADICH5 5 +-#define CADICH6 6 +-#define CADICH7 7 +- +-#define FCSR _SFR_MEM8(0xF0) +-#define CFE 0 +-#define DFE 1 +-#define CPS 2 +-#define DUVRD 3 +- +-#define BPIMSK _SFR_MEM8(0xF2) +-#define CHCIE 0 +-#define DHCIE 1 +-#define COCIE 2 +-#define DOCIE 3 +-#define SCIE 4 +- +-#define BPIFR _SFR_MEM8(0xF3) +-#define CHCIF 0 +-#define DHCIF 1 +-#define COCIF 2 +-#define DOCIF 3 +-#define SCIF 4 +- +-#define BPSCD _SFR_MEM8(0xF5) +-#define SCDL0 0 +-#define SCDL1 1 +-#define SCDL2 2 +-#define SCDL3 3 +-#define SCDL4 4 +-#define SCDL5 5 +-#define SCDL6 6 +-#define SCDL7 7 +- +-#define BPDOCD _SFR_MEM8(0xF6) +-#define DOCDL0 0 +-#define DOCDL1 1 +-#define DOCDL2 2 +-#define DOCDL3 3 +-#define DOCDL4 4 +-#define DOCDL5 5 +-#define DOCDL6 6 +-#define DOCDL7 7 +- +-#define BPCOCD _SFR_MEM8(0xF7) +-#define COCDL0 0 +-#define COCDL1 1 +-#define COCDL2 2 +-#define COCDL3 3 +-#define COCDL4 4 +-#define COCDL5 5 +-#define COCDL6 6 +-#define COCDL7 7 +- +-#define BPDHCD _SFR_MEM8(0xF8) +-#define DHCDL0 0 +-#define DHCDL1 1 +-#define DHCDL2 2 +-#define DHCDL3 3 +-#define DHCDL4 4 +-#define DHCDL5 5 +-#define DHCDL6 6 +-#define DHCDL7 7 +- +-#define BPCHCD _SFR_MEM8(0xF9) +-#define CHCDL0 0 +-#define CHCDL1 1 +-#define CHCDL2 2 +-#define CHCDL3 3 +-#define CHCDL4 4 +-#define CHCDL5 5 +-#define CHCDL6 6 +-#define CHCDL7 7 +- +-#define BPSCTR _SFR_MEM8(0xFA) +-#define SCPT0 0 +-#define SCPT1 1 +-#define SCPT2 2 +-#define SCPT3 3 +-#define SCPT4 4 +-#define SCPT5 5 +-#define SCPT6 6 +- +-#define BPOCTR _SFR_MEM8(0xFB) +-#define OCPT0 0 +-#define OCPT1 1 +-#define OCPT2 2 +-#define OCPT3 3 +-#define OCPT4 4 +-#define OCPT5 5 +- +-#define BPHCTR _SFR_MEM8(0xFC) +-#define HCPT0 0 +-#define HCPT1 1 +-#define HCPT2 2 +-#define HCPT3 3 +-#define HCPT4 4 +-#define HCPT5 5 +- +-#define BPCR _SFR_MEM8(0xFD) +-#define CHCD 0 +-#define DHCD 1 +-#define COCD 2 +-#define DOCD 3 +-#define SCD 4 +-#define PRMD 7 +- +-#define BPPLR _SFR_MEM8(0xFE) +-#define BPPL 0 +-#define BPPLE 1 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define BPINT_vect_num 1 +-#define BPINT_vect _VECTOR(1) /* Battery Protection Interrupt */ +-#define VREGMON_vect_num 2 +-#define VREGMON_vect _VECTOR(2) /* Voltage regulator monitor interrupt */ +-#define INT0_vect_num 3 +-#define INT0_vect _VECTOR(3) /* External Interrupt Request 0 */ +-#define INT1_vect_num 4 +-#define INT1_vect _VECTOR(4) /* External Interrupt Request 1 */ +-#define INT2_vect_num 5 +-#define INT2_vect _VECTOR(5) /* External Interrupt Request 2 */ +-#define PCINT0_vect_num 6 +-#define PCINT0_vect _VECTOR(6) /* Pin Change Interrupt Request 0 */ +-#define WDT_vect_num 7 +-#define WDT_vect _VECTOR(7) /* Watchdog Timeout Interrupt */ +-#define TIMER1_IC_vect_num 8 +-#define TIMER1_IC_vect _VECTOR(8) /* Timer 1 Input capture */ +-#define TIMER1_COMPA_vect_num 9 +-#define TIMER1_COMPA_vect _VECTOR(9) /* Timer 1 Compare Match A */ +-#define TIMER1_COMPB_vect_num 10 +-#define TIMER1_COMPB_vect _VECTOR(10) /* Timer 1 Compare Match B */ +-#define TIMER1_OVF_vect_num 11 +-#define TIMER1_OVF_vect _VECTOR(11) /* Timer 1 overflow */ +-#define TIMER0_IC_vect_num 12 +-#define TIMER0_IC_vect _VECTOR(12) /* Timer 0 Input Capture */ +-#define TIMER0_COMPA_vect_num 13 +-#define TIMER0_COMPA_vect _VECTOR(13) /* Timer 0 Comapre Match A */ +-#define TIMER0_COMPB_vect_num 14 +-#define TIMER0_COMPB_vect _VECTOR(14) /* Timer 0 Compare Match B */ +-#define TIMER0_OVF_vect_num 15 +-#define TIMER0_OVF_vect _VECTOR(15) /* Timer 0 Overflow */ +-#define SPI_STC_vect_num 16 +-#define SPI_STC_vect _VECTOR(16) /* SPI Serial transfer complete */ +-#define VADC_vect_num 17 +-#define VADC_vect _VECTOR(17) /* Voltage ADC Conversion Complete */ +-#define CCADC_CONV_vect_num 18 +-#define CCADC_CONV_vect _VECTOR(18) /* Coulomb Counter ADC Conversion Complete */ +-#define CCADC_REG_CUR_vect_num 19 +-#define CCADC_REG_CUR_vect _VECTOR(19) /* Coloumb Counter ADC Regular Current */ +-#define CCADC_ACC_vect_num 20 +-#define CCADC_ACC_vect _VECTOR(20) /* Coloumb Counter ADC Accumulator */ +-#define EE_READY_vect_num 21 +-#define EE_READY_vect _VECTOR(21) /* EEPROM Ready */ +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (22 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (128) +-#define RAMSTART (0x100) +-#define RAMSIZE (1024) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (NA) +-#define XRAMEND (RAMEND) +-#define E2END (0xFF) +-#define E2PAGESIZE (4) +-#define FLASHEND (0x3FFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 2 +- +-/* Low Fuse Byte */ +-#define FUSE_SUT0 (unsigned char)~_BV(0) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(1) /* Select start-up time */ +-#define FUSE_SUT2 (unsigned char)~_BV(2) /* Select start-up time */ +-#define FUSE_SELFPRGEN (unsigned char)~_BV(3) /* Enable self programming */ +-#define FUSE_DWEN (unsigned char)~_BV(4) /* Enable debugWIRE */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_EESAVE (unsigned char)~_BV(6) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(7) /* Watchdog Timer Always On */ +-#define LFUSE_DEFAULT (FUSE_SPIEN) +- +-/* High Fuse Byte */ +-#define FUSE_OSCSEL0 (unsigned char)~_BV(0) /* Oscillator Select 0 */ +-#define FUSE_OSCSEL1 (unsigned char)~_BV(1) /* Oscillator Select 1 */ +-#define FUSE_COMPMODE (unsigned char)~_BV(2) /* Compatibility mode */ +-#define HFUSE_DEFAULT (FUSE_COMPMODE & FUSE_OSCSEL1) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x94 +-#define SIGNATURE_2 0x0E +- +- +-/* Device Pin Definitions */ +-#define PV2_DDR DDRV +-#define PV2_PORT PORTV +-#define PV2_PIN PINV +-#define PV2_BIT 2 +- +-#define PV1_DDR DDRV +-#define PV1_PORT PORTV +-#define PV1_PIN PINV +-#define PV1_BIT 1 +- +-#define NV_DDR DDRNV +-#define NV_PORT PORTNV +-#define NV_PIN PINNV +-#define NV_BIT NV +- +-#define VFET_DDR DDRVFET +-#define VFET_PORT PORTVFET +-#define VFET_PIN PINVFET +-#define VFET_BIT VFET +- +-#define CF1P_DDR DDRCF1P +-#define CF1P_PORT PORTCF1P +-#define CF1P_PIN PINCF1P +-#define CF1P_BIT CF1P +- +-#define CF1N_DDR DDRCF1N +-#define CF1N_PORT PORTCF1N +-#define CF1N_PIN PINCF1N +-#define CF1N_BIT CF1N +- +-#define CF2P_DDR DDRCF2P +-#define CF2P_PORT PORTCF2P +-#define CF2P_PIN PINCF2P +-#define CF2P_BIT CF2P +- +-#define CF2N_DDR DDRCF2N +-#define CF2N_PORT PORTCF2N +-#define CF2N_PIN PINCF2N +-#define CF2N_BIT CF2N +- +-#define VREG_DDR DDRVREG +-#define VREG_PORT PORTVREG +-#define VREG_PIN PINVREG +-#define VREG_BIT VREG +- +-#define VREF_DDR DDRVREF +-#define VREF_PORT PORTVREF +-#define VREF_PIN PINVREF +-#define VREF_BIT VREF +- +-#define VREFGND_DDR DDRVREFGND +-#define VREFGND_PORT PORTVREFGND +-#define VREFGND_PIN PINVREFGND +-#define VREFGND_BIT VREFGND +- +-#define PI_DDR DDRI +-#define PI_PORT PORTI +-#define PI_PIN PINI +-#define PI_BIT +- +-#define NI_DDR DDRNI +-#define NI_PORT PORTNI +-#define NI_PIN PINNI +-#define NI_BIT NI +- +-#define PA0_DDR DDRA +-#define PA0_PORT PORTA +-#define PA0_PIN PINA +-#define PA0_BIT 0 +- +-#define PA1_DDR DDRA +-#define PA1_PORT PORTA +-#define PA1_PIN PINA +-#define PA1_BIT 1 +- +-#define PA2_DDR DDRA +-#define PA2_PORT PORTA +-#define PA2_PIN PINA +-#define PA2_BIT 2 +- +-#define PB0_DDR DDRB +-#define PB0_PORT PORTB +-#define PB0_PIN PINB +-#define PB0_BIT 0 +- +-#define PB1_DDR DDRB +-#define PB1_PORT PORTB +-#define PB1_PIN PINB +-#define PB1_BIT 1 +- +-#define PB2_DDR DDRB +-#define PB2_PORT PORTB +-#define PB2_PIN PINB +-#define PB2_BIT 2 +- +-#define PB3_DDR DDRB +-#define PB3_PORT PORTB +-#define PB3_PIN PINB +-#define PB3_BIT 3 +- +-#define PC0_DDR DDRC +-#define PC0_PORT PORTC +-#define PC0_PIN PINC +-#define PC0_BIT 0 +- +-#define BATT_DDR DDRBATT +-#define BATT_PORT PORTBATT +-#define BATT_PIN PINBATT +-#define BATT_BIT BATT +- +-#define OC_DDR DDROC +-#define OC_PORT PORTOC +-#define OC_PIN PINOC +-#define OC_BIT OC +- +-#endif /* _AVR_ATmega16HVA2_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom16hva2.h 2192 2010-11-08 13:53:24Z arcanum $ */ ++ ++/* avr/iom16hva2.h - definitions for ATmega16HVA2 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom16hva2.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATmega16HVA2_H_ ++#define _AVR_ATmega16HVA2_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA0 0 ++#define PINA1 1 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA0 0 ++#define DDA1 1 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA0 0 ++#define PORTA1 1 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++#define ICF0 3 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 3 ++ ++#define OSICSR _SFR_IO8(0x17) ++#define OSIEN 0 ++#define OSIST 1 ++#define OSISEL0 4 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define ICS0 3 ++#define ICES0 4 ++#define ICNC0 5 ++#define ICEN0 6 ++#define TCW0 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++ ++#define TCNT0 _SFR_IO16(0x26) ++ ++#define TCNT0L _SFR_IO8(0x26) ++#define TCNT0L0 0 ++#define TCNT0L1 1 ++#define TCNT0L2 2 ++#define TCNT0L3 3 ++#define TCNT0L4 4 ++#define TCNT0L5 5 ++#define TCNT0L6 6 ++#define TCNT0L7 7 ++ ++#define TCNT0H _SFR_IO8(0x27) ++#define TCNT0H0 0 ++#define TCNT0H1 1 ++#define TCNT0H2 2 ++#define TCNT0H3 3 ++#define TCNT0H4 4 ++#define TCNT0H5 5 ++#define TCNT0H6 6 ++#define TCNT0H7 7 ++ ++#define OCR0A _SFR_IO8(0x28) ++#define OCR0A0 0 ++#define OCR0A1 1 ++#define OCR0A2 2 ++#define OCR0A3 3 ++#define OCR0A4 4 ++#define OCR0A5 5 ++#define OCR0A6 6 ++#define OCR0A7 7 ++ ++#define OCR0B _SFR_IO8(0x29) ++#define OCR0B0 0 ++#define OCR0B1 1 ++#define OCR0B2 2 ++#define OCR0B3 3 ++#define OCR0B4 4 ++#define OCR0B5 5 ++#define OCR0B6 6 ++#define OCR0B7 7 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define DWDR _SFR_IO8(0x31) ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BODRF 2 ++#define WDRF 3 ++#define OCDRF 4 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define PUD 4 ++#define CKOE 5 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define RFLB 3 ++#define CTPB 4 ++#define SIGRD 5 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPCE 7 ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRVADC 0 ++#define PRTIM0 1 ++#define PRTIM1 2 ++#define PRSPI 3 ++#define PRVRM 5 ++ ++#define FOSCCAL _SFR_MEM8(0x66) ++#define FCAL0 0 ++#define FCAL1 1 ++#define FCAL2 2 ++#define FCAL3 3 ++#define FCAL4 4 ++#define FCAL5 5 ++#define FCAL6 6 ++#define FCAL7 7 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++#define ICIE0 3 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 3 ++ ++#define VADC _SFR_MEM16(0x78) ++ ++#define VADCL _SFR_MEM8(0x78) ++#define VADC0 0 ++#define VADC1 1 ++#define VADC2 2 ++#define VADC3 3 ++#define VADC4 4 ++#define VADC5 5 ++#define VADC6 6 ++#define VADC7 7 ++ ++#define VADCH _SFR_MEM8(0x79) ++#define VADC8 0 ++#define VADC9 1 ++#define VADC10 2 ++#define VADC11 3 ++ ++#define VADCSR _SFR_MEM8(0x7A) ++#define VADCCIE 0 ++#define VADCCIF 1 ++#define VADSC 2 ++#define VADEN 3 ++ ++#define VADMUX _SFR_MEM8(0x7C) ++#define VADMUX0 0 ++#define VADMUX1 1 ++#define VADMUX2 2 ++#define VADMUX3 3 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define PA0DID 0 ++#define PA1DID 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define ICS1 3 ++#define ICES1 4 ++#define ICNC1 5 ++#define ICEN1 6 ++#define TCW1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define OCR1A _SFR_MEM8(0x88) ++#define OCR1A0 0 ++#define OCR1A1 1 ++#define OCR1A2 2 ++#define OCR1A3 3 ++#define OCR1A4 4 ++#define OCR1A5 5 ++#define OCR1A6 6 ++#define OCR1A7 7 ++ ++#define OCR1B _SFR_MEM8(0x89) ++#define OCR1B0 0 ++#define OCR1B1 1 ++#define OCR1B2 2 ++#define OCR1B3 3 ++#define OCR1B4 4 ++#define OCR1B5 5 ++#define OCR1B6 6 ++#define OCR1B7 7 ++ ++#define ROCR _SFR_MEM8(0xC8) ++#define ROCWIE 0 ++#define ROCWIF 1 ++#define ROCS 7 ++ ++#define BGCCR _SFR_MEM8(0xD0) ++#define BGCC0 0 ++#define BGCC1 1 ++#define BGCC2 2 ++#define BGCC3 3 ++#define BGCC4 4 ++#define BGCC5 5 ++#define BGD 7 ++ ++#define BGCRR _SFR_MEM8(0xD1) ++#define BGCR0 0 ++#define BGCR1 1 ++#define BGCR2 2 ++#define BGCR3 3 ++#define BGCR4 4 ++#define BGCR5 5 ++#define BGCR6 6 ++#define BGCR7 7 ++ ++#define CADAC0 _SFR_MEM8(0xE0) ++#define CADAC00 0 ++#define CADAC01 1 ++#define CADAC02 2 ++#define CADAC03 3 ++#define CADAC04 4 ++#define CADAC05 5 ++#define CADAC06 6 ++#define CADAC07 7 ++ ++#define CADAC1 _SFR_MEM8(0xE1) ++#define CADAC08 0 ++#define CADAC09 1 ++#define CADAC10 2 ++#define CADAC11 3 ++#define CADAC12 4 ++#define CADAC13 5 ++#define CADAC14 6 ++#define CADAC15 7 ++ ++#define CADAC2 _SFR_MEM8(0xE2) ++#define CADAC16 0 ++#define CADAC17 1 ++#define CADAC18 2 ++#define CADAC19 3 ++#define CADAC20 4 ++#define CADAC21 5 ++#define CADAC22 6 ++#define CADAC23 7 ++ ++#define CADAC3 _SFR_MEM8(0xE3) ++#define CADAC24 0 ++#define CADAC25 1 ++#define CADAC26 2 ++#define CADAC27 3 ++#define CADAC28 4 ++#define CADAC29 5 ++#define CADAC30 6 ++#define CADAC31 7 ++ ++#define CADCSRA _SFR_MEM8(0xE4) ++#define CADSE 0 ++#define CADSI0 1 ++#define CADSI1 2 ++#define CADAS0 3 ++#define CADAS1 4 ++#define CADUB 5 ++#define CADPOL 6 ++#define CADEN 7 ++ ++#define CADCSRB _SFR_MEM8(0xE5) ++#define CADICIF 0 ++#define CADRCIF 1 ++#define CADACIF 2 ++#define CADICIE 4 ++#define CADRCIE 5 ++#define CADACIE 6 ++ ++#define CADRC _SFR_MEM8(0xE6) ++#define CADRC0 0 ++#define CADRC1 1 ++#define CADRC2 2 ++#define CADRC3 3 ++#define CADRC4 4 ++#define CADRC5 5 ++#define CADRC6 6 ++#define CADRC7 7 ++ ++#define CADIC _SFR_MEM16(0xE8) ++ ++#define CADICL _SFR_MEM8(0xE8) ++#define CADICL0 0 ++#define CADICL1 1 ++#define CADICL2 2 ++#define CADICL3 3 ++#define CADICL4 4 ++#define CADICL5 5 ++#define CADICL6 6 ++#define CADICL7 7 ++ ++#define CADICH _SFR_MEM8(0xE9) ++#define CADICH0 0 ++#define CADICH1 1 ++#define CADICH2 2 ++#define CADICH3 3 ++#define CADICH4 4 ++#define CADICH5 5 ++#define CADICH6 6 ++#define CADICH7 7 ++ ++#define FCSR _SFR_MEM8(0xF0) ++#define CFE 0 ++#define DFE 1 ++#define CPS 2 ++#define DUVRD 3 ++ ++#define BPIMSK _SFR_MEM8(0xF2) ++#define CHCIE 0 ++#define DHCIE 1 ++#define COCIE 2 ++#define DOCIE 3 ++#define SCIE 4 ++ ++#define BPIFR _SFR_MEM8(0xF3) ++#define CHCIF 0 ++#define DHCIF 1 ++#define COCIF 2 ++#define DOCIF 3 ++#define SCIF 4 ++ ++#define BPSCD _SFR_MEM8(0xF5) ++#define SCDL0 0 ++#define SCDL1 1 ++#define SCDL2 2 ++#define SCDL3 3 ++#define SCDL4 4 ++#define SCDL5 5 ++#define SCDL6 6 ++#define SCDL7 7 ++ ++#define BPDOCD _SFR_MEM8(0xF6) ++#define DOCDL0 0 ++#define DOCDL1 1 ++#define DOCDL2 2 ++#define DOCDL3 3 ++#define DOCDL4 4 ++#define DOCDL5 5 ++#define DOCDL6 6 ++#define DOCDL7 7 ++ ++#define BPCOCD _SFR_MEM8(0xF7) ++#define COCDL0 0 ++#define COCDL1 1 ++#define COCDL2 2 ++#define COCDL3 3 ++#define COCDL4 4 ++#define COCDL5 5 ++#define COCDL6 6 ++#define COCDL7 7 ++ ++#define BPDHCD _SFR_MEM8(0xF8) ++#define DHCDL0 0 ++#define DHCDL1 1 ++#define DHCDL2 2 ++#define DHCDL3 3 ++#define DHCDL4 4 ++#define DHCDL5 5 ++#define DHCDL6 6 ++#define DHCDL7 7 ++ ++#define BPCHCD _SFR_MEM8(0xF9) ++#define CHCDL0 0 ++#define CHCDL1 1 ++#define CHCDL2 2 ++#define CHCDL3 3 ++#define CHCDL4 4 ++#define CHCDL5 5 ++#define CHCDL6 6 ++#define CHCDL7 7 ++ ++#define BPSCTR _SFR_MEM8(0xFA) ++#define SCPT0 0 ++#define SCPT1 1 ++#define SCPT2 2 ++#define SCPT3 3 ++#define SCPT4 4 ++#define SCPT5 5 ++#define SCPT6 6 ++ ++#define BPOCTR _SFR_MEM8(0xFB) ++#define OCPT0 0 ++#define OCPT1 1 ++#define OCPT2 2 ++#define OCPT3 3 ++#define OCPT4 4 ++#define OCPT5 5 ++ ++#define BPHCTR _SFR_MEM8(0xFC) ++#define HCPT0 0 ++#define HCPT1 1 ++#define HCPT2 2 ++#define HCPT3 3 ++#define HCPT4 4 ++#define HCPT5 5 ++ ++#define BPCR _SFR_MEM8(0xFD) ++#define CHCD 0 ++#define DHCD 1 ++#define COCD 2 ++#define DOCD 3 ++#define SCD 4 ++#define PRMD 7 ++ ++#define BPPLR _SFR_MEM8(0xFE) ++#define BPPL 0 ++#define BPPLE 1 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define BPINT_vect_num 1 ++#define BPINT_vect _VECTOR(1) /* Battery Protection Interrupt */ ++#define VREGMON_vect_num 2 ++#define VREGMON_vect _VECTOR(2) /* Voltage regulator monitor interrupt */ ++#define INT0_vect_num 3 ++#define INT0_vect _VECTOR(3) /* External Interrupt Request 0 */ ++#define INT1_vect_num 4 ++#define INT1_vect _VECTOR(4) /* External Interrupt Request 1 */ ++#define INT2_vect_num 5 ++#define INT2_vect _VECTOR(5) /* External Interrupt Request 2 */ ++#define PCINT0_vect_num 6 ++#define PCINT0_vect _VECTOR(6) /* Pin Change Interrupt Request 0 */ ++#define WDT_vect_num 7 ++#define WDT_vect _VECTOR(7) /* Watchdog Timeout Interrupt */ ++#define TIMER1_IC_vect_num 8 ++#define TIMER1_IC_vect _VECTOR(8) /* Timer 1 Input capture */ ++#define TIMER1_COMPA_vect_num 9 ++#define TIMER1_COMPA_vect _VECTOR(9) /* Timer 1 Compare Match A */ ++#define TIMER1_COMPB_vect_num 10 ++#define TIMER1_COMPB_vect _VECTOR(10) /* Timer 1 Compare Match B */ ++#define TIMER1_OVF_vect_num 11 ++#define TIMER1_OVF_vect _VECTOR(11) /* Timer 1 overflow */ ++#define TIMER0_IC_vect_num 12 ++#define TIMER0_IC_vect _VECTOR(12) /* Timer 0 Input Capture */ ++#define TIMER0_COMPA_vect_num 13 ++#define TIMER0_COMPA_vect _VECTOR(13) /* Timer 0 Comapre Match A */ ++#define TIMER0_COMPB_vect_num 14 ++#define TIMER0_COMPB_vect _VECTOR(14) /* Timer 0 Compare Match B */ ++#define TIMER0_OVF_vect_num 15 ++#define TIMER0_OVF_vect _VECTOR(15) /* Timer 0 Overflow */ ++#define SPI_STC_vect_num 16 ++#define SPI_STC_vect _VECTOR(16) /* SPI Serial transfer complete */ ++#define VADC_vect_num 17 ++#define VADC_vect _VECTOR(17) /* Voltage ADC Conversion Complete */ ++#define CCADC_CONV_vect_num 18 ++#define CCADC_CONV_vect _VECTOR(18) /* Coulomb Counter ADC Conversion Complete */ ++#define CCADC_REG_CUR_vect_num 19 ++#define CCADC_REG_CUR_vect _VECTOR(19) /* Coloumb Counter ADC Regular Current */ ++#define CCADC_ACC_vect_num 20 ++#define CCADC_ACC_vect _VECTOR(20) /* Coloumb Counter ADC Accumulator */ ++#define EE_READY_vect_num 21 ++#define EE_READY_vect _VECTOR(21) /* EEPROM Ready */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (22 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (128) ++#define RAMSTART (0x100) ++#define RAMSIZE (1024) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (NA) ++#define XRAMEND (RAMEND) ++#define E2END (0xFF) ++#define E2PAGESIZE (4) ++#define FLASHEND (0x3FFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 2 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT0 (unsigned char)~_BV(0) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(1) /* Select start-up time */ ++#define FUSE_SUT2 (unsigned char)~_BV(2) /* Select start-up time */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(3) /* Enable self programming */ ++#define FUSE_DWEN (unsigned char)~_BV(4) /* Enable debugWIRE */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_EESAVE (unsigned char)~_BV(6) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(7) /* Watchdog Timer Always On */ ++#define LFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* High Fuse Byte */ ++#define FUSE_OSCSEL0 (unsigned char)~_BV(0) /* Oscillator Select 0 */ ++#define FUSE_OSCSEL1 (unsigned char)~_BV(1) /* Oscillator Select 1 */ ++#define FUSE_COMPMODE (unsigned char)~_BV(2) /* Compatibility mode */ ++#define HFUSE_DEFAULT (FUSE_COMPMODE & FUSE_OSCSEL1) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x0E ++ ++ ++/* Device Pin Definitions */ ++#define PV2_DDR DDRV ++#define PV2_PORT PORTV ++#define PV2_PIN PINV ++#define PV2_BIT 2 ++ ++#define PV1_DDR DDRV ++#define PV1_PORT PORTV ++#define PV1_PIN PINV ++#define PV1_BIT 1 ++ ++#define NV_DDR DDRNV ++#define NV_PORT PORTNV ++#define NV_PIN PINNV ++#define NV_BIT NV ++ ++#define VFET_DDR DDRVFET ++#define VFET_PORT PORTVFET ++#define VFET_PIN PINVFET ++#define VFET_BIT VFET ++ ++#define CF1P_DDR DDRCF1P ++#define CF1P_PORT PORTCF1P ++#define CF1P_PIN PINCF1P ++#define CF1P_BIT CF1P ++ ++#define CF1N_DDR DDRCF1N ++#define CF1N_PORT PORTCF1N ++#define CF1N_PIN PINCF1N ++#define CF1N_BIT CF1N ++ ++#define CF2P_DDR DDRCF2P ++#define CF2P_PORT PORTCF2P ++#define CF2P_PIN PINCF2P ++#define CF2P_BIT CF2P ++ ++#define CF2N_DDR DDRCF2N ++#define CF2N_PORT PORTCF2N ++#define CF2N_PIN PINCF2N ++#define CF2N_BIT CF2N ++ ++#define VREG_DDR DDRVREG ++#define VREG_PORT PORTVREG ++#define VREG_PIN PINVREG ++#define VREG_BIT VREG ++ ++#define VREF_DDR DDRVREF ++#define VREF_PORT PORTVREF ++#define VREF_PIN PINVREF ++#define VREF_BIT VREF ++ ++#define VREFGND_DDR DDRVREFGND ++#define VREFGND_PORT PORTVREFGND ++#define VREFGND_PIN PINVREFGND ++#define VREFGND_BIT VREFGND ++ ++#define PI_DDR DDRI ++#define PI_PORT PORTI ++#define PI_PIN PINI ++#define PI_BIT ++ ++#define NI_DDR DDRNI ++#define NI_PORT PORTNI ++#define NI_PIN PINNI ++#define NI_BIT NI ++ ++#define PA0_DDR DDRA ++#define PA0_PORT PORTA ++#define PA0_PIN PINA ++#define PA0_BIT 0 ++ ++#define PA1_DDR DDRA ++#define PA1_PORT PORTA ++#define PA1_PIN PINA ++#define PA1_BIT 1 ++ ++#define PA2_DDR DDRA ++#define PA2_PORT PORTA ++#define PA2_PIN PINA ++#define PA2_BIT 2 ++ ++#define PB0_DDR DDRB ++#define PB0_PORT PORTB ++#define PB0_PIN PINB ++#define PB0_BIT 0 ++ ++#define PB1_DDR DDRB ++#define PB1_PORT PORTB ++#define PB1_PIN PINB ++#define PB1_BIT 1 ++ ++#define PB2_DDR DDRB ++#define PB2_PORT PORTB ++#define PB2_PIN PINB ++#define PB2_BIT 2 ++ ++#define PB3_DDR DDRB ++#define PB3_PORT PORTB ++#define PB3_PIN PINB ++#define PB3_BIT 3 ++ ++#define PC0_DDR DDRC ++#define PC0_PORT PORTC ++#define PC0_PIN PINC ++#define PC0_BIT 0 ++ ++#define BATT_DDR DDRBATT ++#define BATT_PORT PORTBATT ++#define BATT_PIN PINBATT ++#define BATT_BIT BATT ++ ++#define OC_DDR DDROC ++#define OC_PORT PORTOC ++#define OC_PIN PINOC ++#define OC_BIT OC ++ ++#endif /* _AVR_ATmega16HVA2_H_ */ ++ +diff --git a/include/avr/iom16hvb.h b/include/avr/iom16hvb.h +index fecd6e3..6022553 100644 +--- a/include/avr/iom16hvb.h ++++ b/include/avr/iom16hvb.h +@@ -1,1039 +1,1039 @@ +-/* Copyright (c) 2011 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom16hvb.h 2211 2011-02-14 14:04:25Z aboyapati $ */ +- +-/* avr/iom16hvb.h - definitions for ATmega16HVB */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom16hvb.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATmega16HVB_H_ +-#define _AVR_ATmega16HVB_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +- +-#define PORTA _SFR_IO8(0x02) +-#define PORTA0 0 +-#define PORTA1 1 +-#define PORTA2 2 +-#define PORTA3 3 +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC3 3 +-#define PORTC4 4 +-#define PORTC5 5 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +-#define ICF0 3 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 3 +- +-#define OSICSR _SFR_IO8(0x17) +-#define OSIEN 0 +-#define OSIST 1 +-#define OSISEL0 4 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +-#define PCIF1 1 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +-#define INTF2 2 +-#define INTF3 3 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +-#define INT2 2 +-#define INT3 3 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +-#define EEAR9 1 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSRSYNC 0 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define ICS0 3 +-#define ICES0 4 +-#define ICNC0 5 +-#define ICEN0 6 +-#define TCW0 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +- +-#define TCNT0 _SFR_IO16(0x26) +- +-#define TCNT0L _SFR_IO8(0x26) +-#define TCNT0L0 0 +-#define TCNT0L1 1 +-#define TCNT0L2 2 +-#define TCNT0L3 3 +-#define TCNT0L4 4 +-#define TCNT0L5 5 +-#define TCNT0L6 6 +-#define TCNT0L7 7 +- +-#define TCNT0H _SFR_IO8(0x27) +-#define TCNT0H0 0 +-#define TCNT0H1 1 +-#define TCNT0H2 2 +-#define TCNT0H3 3 +-#define TCNT0H4 4 +-#define TCNT0H5 5 +-#define TCNT0H6 6 +-#define TCNT0H7 7 +- +-#define OCR0A _SFR_IO8(0x28) +-#define OCR0A0 0 +-#define OCR0A1 1 +-#define OCR0A2 2 +-#define OCR0A3 3 +-#define OCR0A4 4 +-#define OCR0A5 5 +-#define OCR0A6 6 +-#define OCR0A7 7 +- +-#define OCR0B _SFR_IO8(0x29) +-#define OCR0B0 0 +-#define OCR0B1 1 +-#define OCR0B2 2 +-#define OCR0B3 3 +-#define OCR0B4 4 +-#define OCR0B5 5 +-#define OCR0B6 6 +-#define OCR0B7 7 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define DWDR _SFR_IO8(0x31) +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BODRF 2 +-#define WDRF 3 +-#define OCDRF 4 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define CKOE 5 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define LBSET 3 +-#define RWWSRE 4 +-#define SIGRD 5 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPCE 7 +- +-#define PRR0 _SFR_MEM8(0x64) +-#define PRVADC 0 +-#define PRTIM0 1 +-#define PRTIM1 2 +-#define PRSPI 3 +-#define PRVRM 5 +-#define PRTWI 6 +- +-#define FOSCCAL _SFR_MEM8(0x66) +-#define FCAL0 0 +-#define FCAL1 1 +-#define FCAL2 2 +-#define FCAL3 3 +-#define FCAL4 4 +-#define FCAL5 5 +-#define FCAL6 6 +-#define FCAL7 7 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +-#define PCIE1 1 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define ISC20 4 +-#define ISC21 5 +-#define ISC30 6 +-#define ISC31 7 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT4 0 +-#define PCINT5 1 +-#define PCINT6 2 +-#define PCINT7 3 +-#define PCINT8 4 +-#define PCINT9 5 +-#define PCINT10 6 +-#define PCINT11 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +-#define ICIE0 3 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 3 +- +-#define VADC _SFR_MEM16(0x78) +- +-#define VADCL _SFR_MEM8(0x78) +-#define VADC0 0 +-#define VADC1 1 +-#define VADC2 2 +-#define VADC3 3 +-#define VADC4 4 +-#define VADC5 5 +-#define VADC6 6 +-#define VADC7 7 +- +-#define VADCH _SFR_MEM8(0x79) +-#define VADC8 0 +-#define VADC9 1 +-#define VADC10 2 +-#define VADC11 3 +- +-#define VADCSR _SFR_MEM8(0x7A) +-#define VADCCIE 0 +-#define VADCCIF 1 +-#define VADSC 2 +-#define VADEN 3 +- +-#define VADMUX _SFR_MEM8(0x7C) +-#define VADMUX0 0 +-#define VADMUX1 1 +-#define VADMUX2 2 +-#define VADMUX3 3 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define PA0DID 0 +-#define PA1DID 1 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define ICS1 3 +-#define ICES1 4 +-#define ICNC1 5 +-#define ICEN1 6 +-#define TCW1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define OCR1A _SFR_MEM8(0x88) +-#define OCR1A0 0 +-#define OCR1A1 1 +-#define OCR1A2 2 +-#define OCR1A3 3 +-#define OCR1A4 4 +-#define OCR1A5 5 +-#define OCR1A6 6 +-#define OCR1A7 7 +- +-#define OCR1B _SFR_MEM8(0x89) +-#define OCR1B0 0 +-#define OCR1B1 1 +-#define OCR1B2 2 +-#define OCR1B3 3 +-#define OCR1B4 4 +-#define OCR1B5 5 +-#define OCR1B6 6 +-#define OCR1B7 7 +- +-#define TWBR _SFR_MEM8(0xB8) +-#define TWBR0 0 +-#define TWBR1 1 +-#define TWBR2 2 +-#define TWBR3 3 +-#define TWBR4 4 +-#define TWBR5 5 +-#define TWBR6 6 +-#define TWBR7 7 +- +-#define TWSR _SFR_MEM8(0xB9) +-#define TWPS0 0 +-#define TWPS1 1 +-#define TWS3 3 +-#define TWS4 4 +-#define TWS5 5 +-#define TWS6 6 +-#define TWS7 7 +- +-#define TWAR _SFR_MEM8(0xBA) +-#define TWGCE 0 +-#define TWA0 1 +-#define TWA1 2 +-#define TWA2 3 +-#define TWA3 4 +-#define TWA4 5 +-#define TWA5 6 +-#define TWA6 7 +- +-#define TWDR _SFR_MEM8(0xBB) +-#define TWD0 0 +-#define TWD1 1 +-#define TWD2 2 +-#define TWD3 3 +-#define TWD4 4 +-#define TWD5 5 +-#define TWD6 6 +-#define TWD7 7 +- +-#define TWCR _SFR_MEM8(0xBC) +-#define TWIE 0 +-#define TWEN 2 +-#define TWWC 3 +-#define TWSTO 4 +-#define TWSTA 5 +-#define TWEA 6 +-#define TWINT 7 +- +-#define TWAMR _SFR_MEM8(0xBD) +-#define TWAM0 1 +-#define TWAM1 2 +-#define TWAM2 3 +-#define TWAM3 4 +-#define TWAM4 5 +-#define TWAM5 6 +-#define TWAM6 7 +- +-#define TWBCSR _SFR_MEM8(0xBE) +-#define TWBCIP 0 +-#define TWBDT0 1 +-#define TWBDT1 2 +-#define TWBCIE 6 +-#define TWBCIF 7 +- +-#define ROCR _SFR_MEM8(0xC8) +-#define ROCWIE 0 +-#define ROCWIF 1 +-#define ROCD 4 +-#define ROCS 7 +- +-#define BGCCR _SFR_MEM8(0xD0) +-#define BGCC0 0 +-#define BGCC1 1 +-#define BGCC2 2 +-#define BGCC3 3 +-#define BGCC4 4 +-#define BGCC5 5 +- +-#define BGCRR _SFR_MEM8(0xD1) +-#define BGCR0 0 +-#define BGCR1 1 +-#define BGCR2 2 +-#define BGCR3 3 +-#define BGCR4 4 +-#define BGCR5 5 +-#define BGCR6 6 +-#define BGCR7 7 +- +-#define BGCSR _SFR_MEM8(0xD2) +-#define BGSCDIE 0 +-#define BGSCDIF 1 +-#define BGSCDE 4 +-#define BGD 5 +- +-#define CHGDCSR _SFR_MEM8(0xD4) +-#define CHGDIE 0 +-#define CHGDIF 1 +-#define CHGDISC0 2 +-#define CHGDISC1 3 +-#define BATTPVL 4 +- +-#define CADAC0 _SFR_MEM8(0xE0) +-#define CADAC00 0 +-#define CADAC01 1 +-#define CADAC02 2 +-#define CADAC03 3 +-#define CADAC04 4 +-#define CADAC05 5 +-#define CADAC06 6 +-#define CADAC07 7 +- +-#define CADAC1 _SFR_MEM8(0xE1) +-#define CADAC08 0 +-#define CADAC09 1 +-#define CADAC10 2 +-#define CADAC11 3 +-#define CADAC12 4 +-#define CADAC13 5 +-#define CADAC14 6 +-#define CADAC15 7 +- +-#define CADAC2 _SFR_MEM8(0xE2) +-#define CADAC16 0 +-#define CADAC17 1 +-#define CADAC18 2 +-#define CADAC19 3 +-#define CADAC20 4 +-#define CADAC21 5 +-#define CADAC22 6 +-#define CADAC23 7 +- +-#define CADAC3 _SFR_MEM8(0xE3) +-#define CADAC24 0 +-#define CADAC25 1 +-#define CADAC26 2 +-#define CADAC27 3 +-#define CADAC28 4 +-#define CADAC29 5 +-#define CADAC30 6 +-#define CADAC31 7 +- +-#define CADIC _SFR_MEM16(0xE4) +- +-#define CADICL _SFR_MEM8(0xE4) +-#define CADICL0 0 +-#define CADICL1 1 +-#define CADICL2 2 +-#define CADICL3 3 +-#define CADICL4 4 +-#define CADICL5 5 +-#define CADICL6 6 +-#define CADICL7 7 +- +-#define CADICH _SFR_MEM8(0xE5) +-#define CADICH0 0 +-#define CADICH1 1 +-#define CADICH2 2 +-#define CADICH3 3 +-#define CADICH4 4 +-#define CADICH5 5 +-#define CADICH6 6 +-#define CADICH7 7 +- +-#define CADCSRA _SFR_MEM8(0xE6) +-#define CADSE 0 +-#define CADSI0 1 +-#define CADSI1 2 +-#define CADAS0 3 +-#define CADAS1 4 +-#define CADUB 5 +-#define CADPOL 6 +-#define CADEN 7 +- +-#define CADCSRB _SFR_MEM8(0xE7) +-#define CADICIF 0 +-#define CADRCIF 1 +-#define CADACIF 2 +-#define CADICIE 4 +-#define CADRCIE 5 +-#define CADACIE 6 +- +-#define CADCSRC _SFR_MEM8(0xE8) +-#define CADVSE 0 +- +-#define CADRCC _SFR_MEM8(0xE9) +-#define CADRCC0 0 +-#define CADRCC1 1 +-#define CADRCC2 2 +-#define CADRCC3 3 +-#define CADRCC4 4 +-#define CADRCC5 5 +-#define CADRCC6 6 +-#define CADRCC7 7 +- +-#define CADRDC _SFR_MEM8(0xEA) +-#define CADRDC0 0 +-#define CADRDC1 1 +-#define CADRDC2 2 +-#define CADRDC3 3 +-#define CADRDC4 4 +-#define CADRDC5 5 +-#define CADRDC6 6 +-#define CADRDC7 7 +- +-#define FCSR _SFR_MEM8(0xF0) +-#define CFE 0 +-#define DFE 1 +-#define CPS 2 +-#define DUVRD 3 +- +-#define CBCR _SFR_MEM8(0xF1) +-#define CBE1 0 +-#define CBE2 1 +-#define CBE3 2 +-#define CBE4 3 +- +-#define BPIMSK _SFR_MEM8(0xF2) +-#define CHCIE 0 +-#define DHCIE 1 +-#define COCIE 2 +-#define DOCIE 3 +-#define SCIE 4 +- +-#define BPIFR _SFR_MEM8(0xF3) +-#define CHCIF 0 +-#define DHCIF 1 +-#define COCIF 2 +-#define DOCIF 3 +-#define SCIF 4 +- +-#define BPSCD _SFR_MEM8(0xF5) +-#define SCDL0 0 +-#define SCDL1 1 +-#define SCDL2 2 +-#define SCDL3 3 +-#define SCDL4 4 +-#define SCDL5 5 +-#define SCDL6 6 +-#define SCDL7 7 +- +-#define BPDOCD _SFR_MEM8(0xF6) +-#define DOCDL0 0 +-#define DOCDL1 1 +-#define DOCDL2 2 +-#define DOCDL3 3 +-#define DOCDL4 4 +-#define DOCDL5 5 +-#define DOCDL6 6 +-#define DOCDL7 7 +- +-#define BPCOCD _SFR_MEM8(0xF7) +-#define COCDL0 0 +-#define COCDL1 1 +-#define COCDL2 2 +-#define COCDL3 3 +-#define COCDL4 4 +-#define COCDL5 5 +-#define COCDL6 6 +-#define COCDL7 7 +- +-#define BPDHCD _SFR_MEM8(0xF8) +-#define DHCDL0 0 +-#define DHCDL1 1 +-#define DHCDL2 2 +-#define DHCDL3 3 +-#define DHCDL4 4 +-#define DHCDL5 5 +-#define DHCDL6 6 +-#define DHCDL7 7 +- +-#define BPCHCD _SFR_MEM8(0xF9) +-#define CHCDL0 0 +-#define CHCDL1 1 +-#define CHCDL2 2 +-#define CHCDL3 3 +-#define CHCDL4 4 +-#define CHCDL5 5 +-#define CHCDL6 6 +-#define CHCDL7 7 +- +-#define BPSCTR _SFR_MEM8(0xFA) +-#define SCPT0 0 +-#define SCPT1 1 +-#define SCPT2 2 +-#define SCPT3 3 +-#define SCPT4 4 +-#define SCPT5 5 +-#define SCPT6 6 +- +-#define BPOCTR _SFR_MEM8(0xFB) +-#define OCPT0 0 +-#define OCPT1 1 +-#define OCPT2 2 +-#define OCPT3 3 +-#define OCPT4 4 +-#define OCPT5 5 +- +-#define BPHCTR _SFR_MEM8(0xFC) +-#define HCPT0 0 +-#define HCPT1 1 +-#define HCPT2 2 +-#define HCPT3 3 +-#define HCPT4 4 +-#define HCPT5 5 +- +-#define BPCR _SFR_MEM8(0xFD) +-#define CHCD 0 +-#define DHCD 1 +-#define COCD 2 +-#define DOCD 3 +-#define SCD 4 +-#define EPID 5 +- +-#define BPPLR _SFR_MEM8(0xFE) +-#define BPPL 0 +-#define BPPLE 1 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define BPINT_vect_num 1 +-#define BPINT_vect _VECTOR(1) /* Battery Protection Interrupt */ +-#define VREGMON_vect_num 2 +-#define VREGMON_vect _VECTOR(2) /* Voltage regulator monitor interrupt */ +-#define INT0_vect_num 3 +-#define INT0_vect _VECTOR(3) /* External Interrupt Request 0 */ +-#define INT1_vect_num 4 +-#define INT1_vect _VECTOR(4) /* External Interrupt Request 1 */ +-#define INT2_vect_num 5 +-#define INT2_vect _VECTOR(5) /* External Interrupt Request 2 */ +-#define INT3_vect_num 6 +-#define INT3_vect _VECTOR(6) /* External Interrupt Request 3 */ +-#define PCINT0_vect_num 7 +-#define PCINT0_vect _VECTOR(7) /* Pin Change Interrupt 0 */ +-#define PCINT1_vect_num 8 +-#define PCINT1_vect _VECTOR(8) /* Pin Change Interrupt 1 */ +-#define WDT_vect_num 9 +-#define WDT_vect _VECTOR(9) /* Watchdog Timeout Interrupt */ +-#define BGSCD_vect_num 10 +-#define BGSCD_vect _VECTOR(10) /* Bandgap Buffer Short Circuit Detected */ +-#define CHDET_vect_num 11 +-#define CHDET_vect _VECTOR(11) /* Charger Detect */ +-#define TIMER1_IC_vect_num 12 +-#define TIMER1_IC_vect _VECTOR(12) /* Timer 1 Input capture */ +-#define TIMER1_COMPA_vect_num 13 +-#define TIMER1_COMPA_vect _VECTOR(13) /* Timer 1 Compare Match A */ +-#define TIMER1_COMPB_vect_num 14 +-#define TIMER1_COMPB_vect _VECTOR(14) /* Timer 1 Compare Match B */ +-#define TIMER1_OVF_vect_num 15 +-#define TIMER1_OVF_vect _VECTOR(15) /* Timer 1 overflow */ +-#define TIMER0_IC_vect_num 16 +-#define TIMER0_IC_vect _VECTOR(16) /* Timer 0 Input Capture */ +-#define TIMER0_COMPA_vect_num 17 +-#define TIMER0_COMPA_vect _VECTOR(17) /* Timer 0 Comapre Match A */ +-#define TIMER0_COMPB_vect_num 18 +-#define TIMER0_COMPB_vect _VECTOR(18) /* Timer 0 Compare Match B */ +-#define TIMER0_OVF_vect_num 19 +-#define TIMER0_OVF_vect _VECTOR(19) /* Timer 0 Overflow */ +-#define TWIBUSCD_vect_num 20 +-#define TWIBUSCD_vect _VECTOR(20) /* Two-Wire Bus Connect/Disconnect */ +-#define TWI_vect_num 21 +-#define TWI_vect _VECTOR(21) /* Two-Wire Serial Interface */ +-#define SPI_STC_vect_num 22 +-#define SPI_STC_vect _VECTOR(22) /* SPI Serial transfer complete */ +-#define VADC_vect_num 23 +-#define VADC_vect _VECTOR(23) /* Voltage ADC Conversion Complete */ +-#define CCADC_CONV_vect_num 24 +-#define CCADC_CONV_vect _VECTOR(24) /* Coulomb Counter ADC Conversion Complete */ +-#define CCADC_REG_CUR_vect_num 25 +-#define CCADC_REG_CUR_vect _VECTOR(25) /* Coloumb Counter ADC Regular Current */ +-#define CCADC_ACC_vect_num 26 +-#define CCADC_ACC_vect _VECTOR(26) /* Coloumb Counter ADC Accumulator */ +-#define EE_READY_vect_num 27 +-#define EE_READY_vect _VECTOR(27) /* EEPROM Ready */ +-#define SPM_vect_num 28 +-#define SPM_vect _VECTOR(28) /* SPM Ready */ +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (29 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (128) +-#define RAMSTART (0x100) +-#define RAMSIZE (1024) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (NA) +-#define XRAMEND (RAMEND) +-#define E2END (0x1FF) +-#define E2PAGESIZE (4) +-#define FLASHEND (0x3FFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 2 +- +-/* Low Fuse Byte */ +-#define FUSE_OSCSEL0 (unsigned char)~_BV(0) /* Oscillator Select */ +-#define FUSE_OSCSEL1 (unsigned char)~_BV(1) /* Oscillator Select */ +-#define FUSE_SUT0 (unsigned char)~_BV(2) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(3) /* Select start-up time */ +-#define FUSE_SUT2 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_EESAVE (unsigned char)~_BV(6) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(7) /* Watchdog Timer Always On */ +-#define LFUSE_DEFAULT (FUSE_SPIEN & FUSE_OSCSEL0) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_DWEN (unsigned char)~_BV(3) /* Enable debugWire */ +-#define FUSE_CKDIV (unsigned char)~_BV(4) /* Clock Divide Register */ +-#define HFUSE_DEFAULT (FUSE_CKDIV & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x94 +-#define SIGNATURE_2 0x0D +- +- +-/* Device Pin Definitions */ +-#define PV2_DDR DDRV +-#define PV2_PORT PORTV +-#define PV2_PIN PINV +-#define PV2_BIT 2 +- +-#define PV1_DDR DDRV +-#define PV1_PORT PORTV +-#define PV1_PIN PINV +-#define PV1_BIT 1 +- +-#define NV_DDR DDRNV +-#define NV_PORT PORTNV +-#define NV_PIN PINNV +-#define NV_BIT NV +- +-#define VFET_DDR DDRVFET +-#define VFET_PORT PORTVFET +-#define VFET_PIN PINVFET +-#define VFET_BIT VFET +- +-#define CF1P_DDR DDRCF1P +-#define CF1P_PORT PORTCF1P +-#define CF1P_PIN PINCF1P +-#define CF1P_BIT CF1P +- +-#define CF1N_DDR DDRCF1N +-#define CF1N_PORT PORTCF1N +-#define CF1N_PIN PINCF1N +-#define CF1N_BIT CF1N +- +-#define CF2P_DDR DDRCF2P +-#define CF2P_PORT PORTCF2P +-#define CF2P_PIN PINCF2P +-#define CF2P_BIT CF2P +- +-#define CF2N_DDR DDRCF2N +-#define CF2N_PORT PORTCF2N +-#define CF2N_PIN PINCF2N +-#define CF2N_BIT CF2N +- +-#define VREG_DDR DDRVREG +-#define VREG_PORT PORTVREG +-#define VREG_PIN PINVREG +-#define VREG_BIT VREG +- +-#define VREF_DDR DDRVREF +-#define VREF_PORT PORTVREF +-#define VREF_PIN PINVREF +-#define VREF_BIT VREF +- +-#define VREF_DDR DDRVREFGND +-#define VREF_PORT PORTVREFGND +-#define VREF_PIN PINVREFGND +-#define VREF_BIT VREFGND +- +-#define PI_DDR DDRI +-#define PI_PORT PORTI +-#define PI_PIN PINI +-#define PI_BIT +- +-#define NI_DDR DDRNI +-#define NI_PORT PORTNI +-#define NI_PIN PINNI +-#define NI_BIT NI +- +-#define PA0_DDR DDRA +-#define PA0_PORT PORTA +-#define PA0_PIN PINA +-#define PA0_BIT 0 +- +-#define PA1_DDR DDRA +-#define PA1_PORT PORTA +-#define PA1_PIN PINA +-#define PA1_BIT 1 +- +-#define PA2_DDR DDRA +-#define PA2_PORT PORTA +-#define PA2_PIN PINA +-#define PA2_BIT 2 +- +-#define PB0_DDR DDRB +-#define PB0_PORT PORTB +-#define PB0_PIN PINB +-#define PB0_BIT 0 +- +-#define PB1_DDR DDRB +-#define PB1_PORT PORTB +-#define PB1_PIN PINB +-#define PB1_BIT 1 +- +-#define PB2_DDR DDRB +-#define PB2_PORT PORTB +-#define PB2_PIN PINB +-#define PB2_BIT 2 +- +-#define PB3_DDR DDRB +-#define PB3_PORT PORTB +-#define PB3_PIN PINB +-#define PB3_BIT 3 +- +-#define PC0_DDR DDRC +-#define PC0_PORT PORTC +-#define PC0_PIN PINC +-#define PC0_BIT 0 +- +-#define BATT_DDR DDRBATT +-#define BATT_PORT PORTBATT +-#define BATT_PIN PINBATT +-#define BATT_BIT BATT +- +-#define OC_DDR DDROC +-#define OC_PORT PORTOC +-#define OC_PIN PINOC +-#define OC_BIT OC +- +-#endif /* _AVR_ATmega16HVB_H_ */ +- ++/* Copyright (c) 2011 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom16hvb.h 2211 2011-02-14 14:04:25Z aboyapati $ */ ++ ++/* avr/iom16hvb.h - definitions for ATmega16HVB */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom16hvb.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATmega16HVB_H_ ++#define _AVR_ATmega16HVB_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA0 0 ++#define PORTA1 1 ++#define PORTA2 2 ++#define PORTA3 3 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC3 3 ++#define PORTC4 4 ++#define PORTC5 5 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++#define ICF0 3 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 3 ++ ++#define OSICSR _SFR_IO8(0x17) ++#define OSIEN 0 ++#define OSIST 1 ++#define OSISEL0 4 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++#define INT3 3 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++#define EEAR9 1 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define ICS0 3 ++#define ICES0 4 ++#define ICNC0 5 ++#define ICEN0 6 ++#define TCW0 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++ ++#define TCNT0 _SFR_IO16(0x26) ++ ++#define TCNT0L _SFR_IO8(0x26) ++#define TCNT0L0 0 ++#define TCNT0L1 1 ++#define TCNT0L2 2 ++#define TCNT0L3 3 ++#define TCNT0L4 4 ++#define TCNT0L5 5 ++#define TCNT0L6 6 ++#define TCNT0L7 7 ++ ++#define TCNT0H _SFR_IO8(0x27) ++#define TCNT0H0 0 ++#define TCNT0H1 1 ++#define TCNT0H2 2 ++#define TCNT0H3 3 ++#define TCNT0H4 4 ++#define TCNT0H5 5 ++#define TCNT0H6 6 ++#define TCNT0H7 7 ++ ++#define OCR0A _SFR_IO8(0x28) ++#define OCR0A0 0 ++#define OCR0A1 1 ++#define OCR0A2 2 ++#define OCR0A3 3 ++#define OCR0A4 4 ++#define OCR0A5 5 ++#define OCR0A6 6 ++#define OCR0A7 7 ++ ++#define OCR0B _SFR_IO8(0x29) ++#define OCR0B0 0 ++#define OCR0B1 1 ++#define OCR0B2 2 ++#define OCR0B3 3 ++#define OCR0B4 4 ++#define OCR0B5 5 ++#define OCR0B6 6 ++#define OCR0B7 7 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define DWDR _SFR_IO8(0x31) ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BODRF 2 ++#define WDRF 3 ++#define OCDRF 4 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define CKOE 5 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define LBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPCE 7 ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRVADC 0 ++#define PRTIM0 1 ++#define PRTIM1 2 ++#define PRSPI 3 ++#define PRVRM 5 ++#define PRTWI 6 ++ ++#define FOSCCAL _SFR_MEM8(0x66) ++#define FCAL0 0 ++#define FCAL1 1 ++#define FCAL2 2 ++#define FCAL3 3 ++#define FCAL4 4 ++#define FCAL5 5 ++#define FCAL6 6 ++#define FCAL7 7 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT4 0 ++#define PCINT5 1 ++#define PCINT6 2 ++#define PCINT7 3 ++#define PCINT8 4 ++#define PCINT9 5 ++#define PCINT10 6 ++#define PCINT11 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++#define ICIE0 3 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 3 ++ ++#define VADC _SFR_MEM16(0x78) ++ ++#define VADCL _SFR_MEM8(0x78) ++#define VADC0 0 ++#define VADC1 1 ++#define VADC2 2 ++#define VADC3 3 ++#define VADC4 4 ++#define VADC5 5 ++#define VADC6 6 ++#define VADC7 7 ++ ++#define VADCH _SFR_MEM8(0x79) ++#define VADC8 0 ++#define VADC9 1 ++#define VADC10 2 ++#define VADC11 3 ++ ++#define VADCSR _SFR_MEM8(0x7A) ++#define VADCCIE 0 ++#define VADCCIF 1 ++#define VADSC 2 ++#define VADEN 3 ++ ++#define VADMUX _SFR_MEM8(0x7C) ++#define VADMUX0 0 ++#define VADMUX1 1 ++#define VADMUX2 2 ++#define VADMUX3 3 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define PA0DID 0 ++#define PA1DID 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define ICS1 3 ++#define ICES1 4 ++#define ICNC1 5 ++#define ICEN1 6 ++#define TCW1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define OCR1A _SFR_MEM8(0x88) ++#define OCR1A0 0 ++#define OCR1A1 1 ++#define OCR1A2 2 ++#define OCR1A3 3 ++#define OCR1A4 4 ++#define OCR1A5 5 ++#define OCR1A6 6 ++#define OCR1A7 7 ++ ++#define OCR1B _SFR_MEM8(0x89) ++#define OCR1B0 0 ++#define OCR1B1 1 ++#define OCR1B2 2 ++#define OCR1B3 3 ++#define OCR1B4 4 ++#define OCR1B5 5 ++#define OCR1B6 6 ++#define OCR1B7 7 ++ ++#define TWBR _SFR_MEM8(0xB8) ++#define TWBR0 0 ++#define TWBR1 1 ++#define TWBR2 2 ++#define TWBR3 3 ++#define TWBR4 4 ++#define TWBR5 5 ++#define TWBR6 6 ++#define TWBR7 7 ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++#define TWD0 0 ++#define TWD1 1 ++#define TWD2 2 ++#define TWD3 3 ++#define TWD4 4 ++#define TWD5 5 ++#define TWD6 6 ++#define TWD7 7 ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++#define TWBCSR _SFR_MEM8(0xBE) ++#define TWBCIP 0 ++#define TWBDT0 1 ++#define TWBDT1 2 ++#define TWBCIE 6 ++#define TWBCIF 7 ++ ++#define ROCR _SFR_MEM8(0xC8) ++#define ROCWIE 0 ++#define ROCWIF 1 ++#define ROCD 4 ++#define ROCS 7 ++ ++#define BGCCR _SFR_MEM8(0xD0) ++#define BGCC0 0 ++#define BGCC1 1 ++#define BGCC2 2 ++#define BGCC3 3 ++#define BGCC4 4 ++#define BGCC5 5 ++ ++#define BGCRR _SFR_MEM8(0xD1) ++#define BGCR0 0 ++#define BGCR1 1 ++#define BGCR2 2 ++#define BGCR3 3 ++#define BGCR4 4 ++#define BGCR5 5 ++#define BGCR6 6 ++#define BGCR7 7 ++ ++#define BGCSR _SFR_MEM8(0xD2) ++#define BGSCDIE 0 ++#define BGSCDIF 1 ++#define BGSCDE 4 ++#define BGD 5 ++ ++#define CHGDCSR _SFR_MEM8(0xD4) ++#define CHGDIE 0 ++#define CHGDIF 1 ++#define CHGDISC0 2 ++#define CHGDISC1 3 ++#define BATTPVL 4 ++ ++#define CADAC0 _SFR_MEM8(0xE0) ++#define CADAC00 0 ++#define CADAC01 1 ++#define CADAC02 2 ++#define CADAC03 3 ++#define CADAC04 4 ++#define CADAC05 5 ++#define CADAC06 6 ++#define CADAC07 7 ++ ++#define CADAC1 _SFR_MEM8(0xE1) ++#define CADAC08 0 ++#define CADAC09 1 ++#define CADAC10 2 ++#define CADAC11 3 ++#define CADAC12 4 ++#define CADAC13 5 ++#define CADAC14 6 ++#define CADAC15 7 ++ ++#define CADAC2 _SFR_MEM8(0xE2) ++#define CADAC16 0 ++#define CADAC17 1 ++#define CADAC18 2 ++#define CADAC19 3 ++#define CADAC20 4 ++#define CADAC21 5 ++#define CADAC22 6 ++#define CADAC23 7 ++ ++#define CADAC3 _SFR_MEM8(0xE3) ++#define CADAC24 0 ++#define CADAC25 1 ++#define CADAC26 2 ++#define CADAC27 3 ++#define CADAC28 4 ++#define CADAC29 5 ++#define CADAC30 6 ++#define CADAC31 7 ++ ++#define CADIC _SFR_MEM16(0xE4) ++ ++#define CADICL _SFR_MEM8(0xE4) ++#define CADICL0 0 ++#define CADICL1 1 ++#define CADICL2 2 ++#define CADICL3 3 ++#define CADICL4 4 ++#define CADICL5 5 ++#define CADICL6 6 ++#define CADICL7 7 ++ ++#define CADICH _SFR_MEM8(0xE5) ++#define CADICH0 0 ++#define CADICH1 1 ++#define CADICH2 2 ++#define CADICH3 3 ++#define CADICH4 4 ++#define CADICH5 5 ++#define CADICH6 6 ++#define CADICH7 7 ++ ++#define CADCSRA _SFR_MEM8(0xE6) ++#define CADSE 0 ++#define CADSI0 1 ++#define CADSI1 2 ++#define CADAS0 3 ++#define CADAS1 4 ++#define CADUB 5 ++#define CADPOL 6 ++#define CADEN 7 ++ ++#define CADCSRB _SFR_MEM8(0xE7) ++#define CADICIF 0 ++#define CADRCIF 1 ++#define CADACIF 2 ++#define CADICIE 4 ++#define CADRCIE 5 ++#define CADACIE 6 ++ ++#define CADCSRC _SFR_MEM8(0xE8) ++#define CADVSE 0 ++ ++#define CADRCC _SFR_MEM8(0xE9) ++#define CADRCC0 0 ++#define CADRCC1 1 ++#define CADRCC2 2 ++#define CADRCC3 3 ++#define CADRCC4 4 ++#define CADRCC5 5 ++#define CADRCC6 6 ++#define CADRCC7 7 ++ ++#define CADRDC _SFR_MEM8(0xEA) ++#define CADRDC0 0 ++#define CADRDC1 1 ++#define CADRDC2 2 ++#define CADRDC3 3 ++#define CADRDC4 4 ++#define CADRDC5 5 ++#define CADRDC6 6 ++#define CADRDC7 7 ++ ++#define FCSR _SFR_MEM8(0xF0) ++#define CFE 0 ++#define DFE 1 ++#define CPS 2 ++#define DUVRD 3 ++ ++#define CBCR _SFR_MEM8(0xF1) ++#define CBE1 0 ++#define CBE2 1 ++#define CBE3 2 ++#define CBE4 3 ++ ++#define BPIMSK _SFR_MEM8(0xF2) ++#define CHCIE 0 ++#define DHCIE 1 ++#define COCIE 2 ++#define DOCIE 3 ++#define SCIE 4 ++ ++#define BPIFR _SFR_MEM8(0xF3) ++#define CHCIF 0 ++#define DHCIF 1 ++#define COCIF 2 ++#define DOCIF 3 ++#define SCIF 4 ++ ++#define BPSCD _SFR_MEM8(0xF5) ++#define SCDL0 0 ++#define SCDL1 1 ++#define SCDL2 2 ++#define SCDL3 3 ++#define SCDL4 4 ++#define SCDL5 5 ++#define SCDL6 6 ++#define SCDL7 7 ++ ++#define BPDOCD _SFR_MEM8(0xF6) ++#define DOCDL0 0 ++#define DOCDL1 1 ++#define DOCDL2 2 ++#define DOCDL3 3 ++#define DOCDL4 4 ++#define DOCDL5 5 ++#define DOCDL6 6 ++#define DOCDL7 7 ++ ++#define BPCOCD _SFR_MEM8(0xF7) ++#define COCDL0 0 ++#define COCDL1 1 ++#define COCDL2 2 ++#define COCDL3 3 ++#define COCDL4 4 ++#define COCDL5 5 ++#define COCDL6 6 ++#define COCDL7 7 ++ ++#define BPDHCD _SFR_MEM8(0xF8) ++#define DHCDL0 0 ++#define DHCDL1 1 ++#define DHCDL2 2 ++#define DHCDL3 3 ++#define DHCDL4 4 ++#define DHCDL5 5 ++#define DHCDL6 6 ++#define DHCDL7 7 ++ ++#define BPCHCD _SFR_MEM8(0xF9) ++#define CHCDL0 0 ++#define CHCDL1 1 ++#define CHCDL2 2 ++#define CHCDL3 3 ++#define CHCDL4 4 ++#define CHCDL5 5 ++#define CHCDL6 6 ++#define CHCDL7 7 ++ ++#define BPSCTR _SFR_MEM8(0xFA) ++#define SCPT0 0 ++#define SCPT1 1 ++#define SCPT2 2 ++#define SCPT3 3 ++#define SCPT4 4 ++#define SCPT5 5 ++#define SCPT6 6 ++ ++#define BPOCTR _SFR_MEM8(0xFB) ++#define OCPT0 0 ++#define OCPT1 1 ++#define OCPT2 2 ++#define OCPT3 3 ++#define OCPT4 4 ++#define OCPT5 5 ++ ++#define BPHCTR _SFR_MEM8(0xFC) ++#define HCPT0 0 ++#define HCPT1 1 ++#define HCPT2 2 ++#define HCPT3 3 ++#define HCPT4 4 ++#define HCPT5 5 ++ ++#define BPCR _SFR_MEM8(0xFD) ++#define CHCD 0 ++#define DHCD 1 ++#define COCD 2 ++#define DOCD 3 ++#define SCD 4 ++#define EPID 5 ++ ++#define BPPLR _SFR_MEM8(0xFE) ++#define BPPL 0 ++#define BPPLE 1 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define BPINT_vect_num 1 ++#define BPINT_vect _VECTOR(1) /* Battery Protection Interrupt */ ++#define VREGMON_vect_num 2 ++#define VREGMON_vect _VECTOR(2) /* Voltage regulator monitor interrupt */ ++#define INT0_vect_num 3 ++#define INT0_vect _VECTOR(3) /* External Interrupt Request 0 */ ++#define INT1_vect_num 4 ++#define INT1_vect _VECTOR(4) /* External Interrupt Request 1 */ ++#define INT2_vect_num 5 ++#define INT2_vect _VECTOR(5) /* External Interrupt Request 2 */ ++#define INT3_vect_num 6 ++#define INT3_vect _VECTOR(6) /* External Interrupt Request 3 */ ++#define PCINT0_vect_num 7 ++#define PCINT0_vect _VECTOR(7) /* Pin Change Interrupt 0 */ ++#define PCINT1_vect_num 8 ++#define PCINT1_vect _VECTOR(8) /* Pin Change Interrupt 1 */ ++#define WDT_vect_num 9 ++#define WDT_vect _VECTOR(9) /* Watchdog Timeout Interrupt */ ++#define BGSCD_vect_num 10 ++#define BGSCD_vect _VECTOR(10) /* Bandgap Buffer Short Circuit Detected */ ++#define CHDET_vect_num 11 ++#define CHDET_vect _VECTOR(11) /* Charger Detect */ ++#define TIMER1_IC_vect_num 12 ++#define TIMER1_IC_vect _VECTOR(12) /* Timer 1 Input capture */ ++#define TIMER1_COMPA_vect_num 13 ++#define TIMER1_COMPA_vect _VECTOR(13) /* Timer 1 Compare Match A */ ++#define TIMER1_COMPB_vect_num 14 ++#define TIMER1_COMPB_vect _VECTOR(14) /* Timer 1 Compare Match B */ ++#define TIMER1_OVF_vect_num 15 ++#define TIMER1_OVF_vect _VECTOR(15) /* Timer 1 overflow */ ++#define TIMER0_IC_vect_num 16 ++#define TIMER0_IC_vect _VECTOR(16) /* Timer 0 Input Capture */ ++#define TIMER0_COMPA_vect_num 17 ++#define TIMER0_COMPA_vect _VECTOR(17) /* Timer 0 Comapre Match A */ ++#define TIMER0_COMPB_vect_num 18 ++#define TIMER0_COMPB_vect _VECTOR(18) /* Timer 0 Compare Match B */ ++#define TIMER0_OVF_vect_num 19 ++#define TIMER0_OVF_vect _VECTOR(19) /* Timer 0 Overflow */ ++#define TWIBUSCD_vect_num 20 ++#define TWIBUSCD_vect _VECTOR(20) /* Two-Wire Bus Connect/Disconnect */ ++#define TWI_vect_num 21 ++#define TWI_vect _VECTOR(21) /* Two-Wire Serial Interface */ ++#define SPI_STC_vect_num 22 ++#define SPI_STC_vect _VECTOR(22) /* SPI Serial transfer complete */ ++#define VADC_vect_num 23 ++#define VADC_vect _VECTOR(23) /* Voltage ADC Conversion Complete */ ++#define CCADC_CONV_vect_num 24 ++#define CCADC_CONV_vect _VECTOR(24) /* Coulomb Counter ADC Conversion Complete */ ++#define CCADC_REG_CUR_vect_num 25 ++#define CCADC_REG_CUR_vect _VECTOR(25) /* Coloumb Counter ADC Regular Current */ ++#define CCADC_ACC_vect_num 26 ++#define CCADC_ACC_vect _VECTOR(26) /* Coloumb Counter ADC Accumulator */ ++#define EE_READY_vect_num 27 ++#define EE_READY_vect _VECTOR(27) /* EEPROM Ready */ ++#define SPM_vect_num 28 ++#define SPM_vect _VECTOR(28) /* SPM Ready */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (29 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (128) ++#define RAMSTART (0x100) ++#define RAMSIZE (1024) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (NA) ++#define XRAMEND (RAMEND) ++#define E2END (0x1FF) ++#define E2PAGESIZE (4) ++#define FLASHEND (0x3FFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 2 ++ ++/* Low Fuse Byte */ ++#define FUSE_OSCSEL0 (unsigned char)~_BV(0) /* Oscillator Select */ ++#define FUSE_OSCSEL1 (unsigned char)~_BV(1) /* Oscillator Select */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Select start-up time */ ++#define FUSE_SUT2 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_EESAVE (unsigned char)~_BV(6) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(7) /* Watchdog Timer Always On */ ++#define LFUSE_DEFAULT (FUSE_SPIEN & FUSE_OSCSEL0) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_DWEN (unsigned char)~_BV(3) /* Enable debugWire */ ++#define FUSE_CKDIV (unsigned char)~_BV(4) /* Clock Divide Register */ ++#define HFUSE_DEFAULT (FUSE_CKDIV & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x0D ++ ++ ++/* Device Pin Definitions */ ++#define PV2_DDR DDRV ++#define PV2_PORT PORTV ++#define PV2_PIN PINV ++#define PV2_BIT 2 ++ ++#define PV1_DDR DDRV ++#define PV1_PORT PORTV ++#define PV1_PIN PINV ++#define PV1_BIT 1 ++ ++#define NV_DDR DDRNV ++#define NV_PORT PORTNV ++#define NV_PIN PINNV ++#define NV_BIT NV ++ ++#define VFET_DDR DDRVFET ++#define VFET_PORT PORTVFET ++#define VFET_PIN PINVFET ++#define VFET_BIT VFET ++ ++#define CF1P_DDR DDRCF1P ++#define CF1P_PORT PORTCF1P ++#define CF1P_PIN PINCF1P ++#define CF1P_BIT CF1P ++ ++#define CF1N_DDR DDRCF1N ++#define CF1N_PORT PORTCF1N ++#define CF1N_PIN PINCF1N ++#define CF1N_BIT CF1N ++ ++#define CF2P_DDR DDRCF2P ++#define CF2P_PORT PORTCF2P ++#define CF2P_PIN PINCF2P ++#define CF2P_BIT CF2P ++ ++#define CF2N_DDR DDRCF2N ++#define CF2N_PORT PORTCF2N ++#define CF2N_PIN PINCF2N ++#define CF2N_BIT CF2N ++ ++#define VREG_DDR DDRVREG ++#define VREG_PORT PORTVREG ++#define VREG_PIN PINVREG ++#define VREG_BIT VREG ++ ++#define VREF_DDR DDRVREF ++#define VREF_PORT PORTVREF ++#define VREF_PIN PINVREF ++#define VREF_BIT VREF ++ ++#define VREFGND_DDR DDRVREFGND ++#define VREFGND_PORT PORTVREFGND ++#define VREFGND_PIN PINVREFGND ++#define VREFGND_BIT VREFGND ++ ++#define PI_DDR DDRI ++#define PI_PORT PORTI ++#define PI_PIN PINI ++#define PI_BIT ++ ++#define NI_DDR DDRNI ++#define NI_PORT PORTNI ++#define NI_PIN PINNI ++#define NI_BIT NI ++ ++#define PA0_DDR DDRA ++#define PA0_PORT PORTA ++#define PA0_PIN PINA ++#define PA0_BIT 0 ++ ++#define PA1_DDR DDRA ++#define PA1_PORT PORTA ++#define PA1_PIN PINA ++#define PA1_BIT 1 ++ ++#define PA2_DDR DDRA ++#define PA2_PORT PORTA ++#define PA2_PIN PINA ++#define PA2_BIT 2 ++ ++#define PB0_DDR DDRB ++#define PB0_PORT PORTB ++#define PB0_PIN PINB ++#define PB0_BIT 0 ++ ++#define PB1_DDR DDRB ++#define PB1_PORT PORTB ++#define PB1_PIN PINB ++#define PB1_BIT 1 ++ ++#define PB2_DDR DDRB ++#define PB2_PORT PORTB ++#define PB2_PIN PINB ++#define PB2_BIT 2 ++ ++#define PB3_DDR DDRB ++#define PB3_PORT PORTB ++#define PB3_PIN PINB ++#define PB3_BIT 3 ++ ++#define PC0_DDR DDRC ++#define PC0_PORT PORTC ++#define PC0_PIN PINC ++#define PC0_BIT 0 ++ ++#define BATT_DDR DDRBATT ++#define BATT_PORT PORTBATT ++#define BATT_PIN PINBATT ++#define BATT_BIT BATT ++ ++#define OC_DDR DDROC ++#define OC_PORT PORTOC ++#define OC_PIN PINOC ++#define OC_BIT OC ++ ++#endif /* _AVR_ATmega16HVB_H_ */ ++ +diff --git a/include/avr/iom16hvbrevb.h b/include/avr/iom16hvbrevb.h +index e58f984..b958706 100755 +--- a/include/avr/iom16hvbrevb.h ++++ b/include/avr/iom16hvbrevb.h +@@ -1,1039 +1,1039 @@ +-/* Copyright (c) 2009, 2011 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom16hvbrevb.h 2086 2009-12-15 03:24:16Z arcanum $ */ +- +-/* avr/iom16hvbrevb.h - definitions for ATmega16HVB revision B */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom16hvbrevb.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATmega16HVBREVB_H_ +-#define _AVR_ATmega16HVBREVB_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +- +-#define PORTA _SFR_IO8(0x02) +-#define PORTA0 0 +-#define PORTA1 1 +-#define PORTA2 2 +-#define PORTA3 3 +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC3 3 +-#define PORTC4 4 +-#define PORTC5 5 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +-#define ICF0 3 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 3 +- +-#define OSICSR _SFR_IO8(0x17) +-#define OSIEN 0 +-#define OSIST 1 +-#define OSISEL0 4 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +-#define PCIF1 1 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +-#define INTF2 2 +-#define INTF3 3 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +-#define INT2 2 +-#define INT3 3 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +-#define EEAR9 1 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSRSYNC 0 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define ICS0 3 +-#define ICES0 4 +-#define ICNC0 5 +-#define ICEN0 6 +-#define TCW0 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +- +-#define TCNT0 _SFR_IO16(0x26) +- +-#define TCNT0L _SFR_IO8(0x26) +-#define TCNT0L0 0 +-#define TCNT0L1 1 +-#define TCNT0L2 2 +-#define TCNT0L3 3 +-#define TCNT0L4 4 +-#define TCNT0L5 5 +-#define TCNT0L6 6 +-#define TCNT0L7 7 +- +-#define TCNT0H _SFR_IO8(0x27) +-#define TCNT0H0 0 +-#define TCNT0H1 1 +-#define TCNT0H2 2 +-#define TCNT0H3 3 +-#define TCNT0H4 4 +-#define TCNT0H5 5 +-#define TCNT0H6 6 +-#define TCNT0H7 7 +- +-#define OCR0A _SFR_IO8(0x28) +-#define OCR0A0 0 +-#define OCR0A1 1 +-#define OCR0A2 2 +-#define OCR0A3 3 +-#define OCR0A4 4 +-#define OCR0A5 5 +-#define OCR0A6 6 +-#define OCR0A7 7 +- +-#define OCR0B _SFR_IO8(0x29) +-#define OCR0B0 0 +-#define OCR0B1 1 +-#define OCR0B2 2 +-#define OCR0B3 3 +-#define OCR0B4 4 +-#define OCR0B5 5 +-#define OCR0B6 6 +-#define OCR0B7 7 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define DWDR _SFR_IO8(0x31) +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BODRF 2 +-#define WDRF 3 +-#define OCDRF 4 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define CKOE 5 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define LBSET 3 +-#define RWWSRE 4 +-#define SIGRD 5 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPCE 7 +- +-#define PRR0 _SFR_MEM8(0x64) +-#define PRVADC 0 +-#define PRTIM0 1 +-#define PRTIM1 2 +-#define PRSPI 3 +-#define PRVRM 5 +-#define PRTWI 6 +- +-#define FOSCCAL _SFR_MEM8(0x66) +-#define FCAL0 0 +-#define FCAL1 1 +-#define FCAL2 2 +-#define FCAL3 3 +-#define FCAL4 4 +-#define FCAL5 5 +-#define FCAL6 6 +-#define FCAL7 7 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +-#define PCIE1 1 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define ISC20 4 +-#define ISC21 5 +-#define ISC30 6 +-#define ISC31 7 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT4 0 +-#define PCINT5 1 +-#define PCINT6 2 +-#define PCINT7 3 +-#define PCINT8 4 +-#define PCINT9 5 +-#define PCINT10 6 +-#define PCINT11 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +-#define ICIE0 3 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 3 +- +-#define VADC _SFR_MEM16(0x78) +- +-#define VADCL _SFR_MEM8(0x78) +-#define VADC0 0 +-#define VADC1 1 +-#define VADC2 2 +-#define VADC3 3 +-#define VADC4 4 +-#define VADC5 5 +-#define VADC6 6 +-#define VADC7 7 +- +-#define VADCH _SFR_MEM8(0x79) +-#define VADC8 0 +-#define VADC9 1 +-#define VADC10 2 +-#define VADC11 3 +- +-#define VADCSR _SFR_MEM8(0x7A) +-#define VADCCIE 0 +-#define VADCCIF 1 +-#define VADSC 2 +-#define VADEN 3 +- +-#define VADMUX _SFR_MEM8(0x7C) +-#define VADMUX0 0 +-#define VADMUX1 1 +-#define VADMUX2 2 +-#define VADMUX3 3 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define PA0DID 0 +-#define PA1DID 1 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define ICS1 3 +-#define ICES1 4 +-#define ICNC1 5 +-#define ICEN1 6 +-#define TCW1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define OCR1A _SFR_MEM8(0x88) +-#define OCR1A0 0 +-#define OCR1A1 1 +-#define OCR1A2 2 +-#define OCR1A3 3 +-#define OCR1A4 4 +-#define OCR1A5 5 +-#define OCR1A6 6 +-#define OCR1A7 7 +- +-#define OCR1B _SFR_MEM8(0x89) +-#define OCR1B0 0 +-#define OCR1B1 1 +-#define OCR1B2 2 +-#define OCR1B3 3 +-#define OCR1B4 4 +-#define OCR1B5 5 +-#define OCR1B6 6 +-#define OCR1B7 7 +- +-#define TWBR _SFR_MEM8(0xB8) +-#define TWBR0 0 +-#define TWBR1 1 +-#define TWBR2 2 +-#define TWBR3 3 +-#define TWBR4 4 +-#define TWBR5 5 +-#define TWBR6 6 +-#define TWBR7 7 +- +-#define TWSR _SFR_MEM8(0xB9) +-#define TWPS0 0 +-#define TWPS1 1 +-#define TWS3 3 +-#define TWS4 4 +-#define TWS5 5 +-#define TWS6 6 +-#define TWS7 7 +- +-#define TWAR _SFR_MEM8(0xBA) +-#define TWGCE 0 +-#define TWA0 1 +-#define TWA1 2 +-#define TWA2 3 +-#define TWA3 4 +-#define TWA4 5 +-#define TWA5 6 +-#define TWA6 7 +- +-#define TWDR _SFR_MEM8(0xBB) +-#define TWD0 0 +-#define TWD1 1 +-#define TWD2 2 +-#define TWD3 3 +-#define TWD4 4 +-#define TWD5 5 +-#define TWD6 6 +-#define TWD7 7 +- +-#define TWCR _SFR_MEM8(0xBC) +-#define TWIE 0 +-#define TWEN 2 +-#define TWWC 3 +-#define TWSTO 4 +-#define TWSTA 5 +-#define TWEA 6 +-#define TWINT 7 +- +-#define TWAMR _SFR_MEM8(0xBD) +-#define TWAM0 1 +-#define TWAM1 2 +-#define TWAM2 3 +-#define TWAM3 4 +-#define TWAM4 5 +-#define TWAM5 6 +-#define TWAM6 7 +- +-#define TWBCSR _SFR_MEM8(0xBE) +-#define TWBCIP 0 +-#define TWBDT0 1 +-#define TWBDT1 2 +-#define TWBCIE 6 +-#define TWBCIF 7 +- +-#define ROCR _SFR_MEM8(0xC8) +-#define ROCWIE 0 +-#define ROCWIF 1 +-#define ROCD 4 +-#define ROCS 7 +- +-#define BGCCR _SFR_MEM8(0xD0) +-#define BGCC0 0 +-#define BGCC1 1 +-#define BGCC2 2 +-#define BGCC3 3 +-#define BGCC4 4 +-#define BGCC5 5 +- +-#define BGCRR _SFR_MEM8(0xD1) +-#define BGCR0 0 +-#define BGCR1 1 +-#define BGCR2 2 +-#define BGCR3 3 +-#define BGCR4 4 +-#define BGCR5 5 +-#define BGCR6 6 +-#define BGCR7 7 +- +-#define BGCSR _SFR_MEM8(0xD2) +-#define BGSCDIE 0 +-#define BGSCDIF 1 +-#define BGSCDE 4 +-#define BGD 5 +- +-#define CHGDCSR _SFR_MEM8(0xD4) +-#define CHGDIE 0 +-#define CHGDIF 1 +-#define CHGDISC0 2 +-#define CHGDISC1 3 +-#define BATTPVL 4 +- +-#define CADAC0 _SFR_MEM8(0xE0) +-#define CADAC00 0 +-#define CADAC01 1 +-#define CADAC02 2 +-#define CADAC03 3 +-#define CADAC04 4 +-#define CADAC05 5 +-#define CADAC06 6 +-#define CADAC07 7 +- +-#define CADAC1 _SFR_MEM8(0xE1) +-#define CADAC08 0 +-#define CADAC09 1 +-#define CADAC10 2 +-#define CADAC11 3 +-#define CADAC12 4 +-#define CADAC13 5 +-#define CADAC14 6 +-#define CADAC15 7 +- +-#define CADAC2 _SFR_MEM8(0xE2) +-#define CADAC16 0 +-#define CADAC17 1 +-#define CADAC18 2 +-#define CADAC19 3 +-#define CADAC20 4 +-#define CADAC21 5 +-#define CADAC22 6 +-#define CADAC23 7 +- +-#define CADAC3 _SFR_MEM8(0xE3) +-#define CADAC24 0 +-#define CADAC25 1 +-#define CADAC26 2 +-#define CADAC27 3 +-#define CADAC28 4 +-#define CADAC29 5 +-#define CADAC30 6 +-#define CADAC31 7 +- +-#define CADIC _SFR_MEM16(0xE4) +- +-#define CADICL _SFR_MEM8(0xE4) +-#define CADICL0 0 +-#define CADICL1 1 +-#define CADICL2 2 +-#define CADICL3 3 +-#define CADICL4 4 +-#define CADICL5 5 +-#define CADICL6 6 +-#define CADICL7 7 +- +-#define CADICH _SFR_MEM8(0xE5) +-#define CADICH0 0 +-#define CADICH1 1 +-#define CADICH2 2 +-#define CADICH3 3 +-#define CADICH4 4 +-#define CADICH5 5 +-#define CADICH6 6 +-#define CADICH7 7 +- +-#define CADCSRA _SFR_MEM8(0xE6) +-#define CADSE 0 +-#define CADSI0 1 +-#define CADSI1 2 +-#define CADAS0 3 +-#define CADAS1 4 +-#define CADUB 5 +-#define CADPOL 6 +-#define CADEN 7 +- +-#define CADCSRB _SFR_MEM8(0xE7) +-#define CADICIF 0 +-#define CADRCIF 1 +-#define CADACIF 2 +-#define CADICIE 4 +-#define CADRCIE 5 +-#define CADACIE 6 +- +-#define CADCSRC _SFR_MEM8(0xE8) +-#define CADVSE 0 +- +-#define CADRCC _SFR_MEM8(0xE9) +-#define CADRCC0 0 +-#define CADRCC1 1 +-#define CADRCC2 2 +-#define CADRCC3 3 +-#define CADRCC4 4 +-#define CADRCC5 5 +-#define CADRCC6 6 +-#define CADRCC7 7 +- +-#define CADRDC _SFR_MEM8(0xEA) +-#define CADRDC0 0 +-#define CADRDC1 1 +-#define CADRDC2 2 +-#define CADRDC3 3 +-#define CADRDC4 4 +-#define CADRDC5 5 +-#define CADRDC6 6 +-#define CADRDC7 7 +- +-#define FCSR _SFR_MEM8(0xF0) +-#define CFE 0 +-#define DFE 1 +-#define CPS 2 +-#define DUVRD 3 +- +-#define CBCR _SFR_MEM8(0xF1) +-#define CBE1 0 +-#define CBE2 1 +-#define CBE3 2 +-#define CBE4 3 +- +-#define BPIMSK _SFR_MEM8(0xF2) +-#define CHCIE 0 +-#define DHCIE 1 +-#define COCIE 2 +-#define DOCIE 3 +-#define SCIE 4 +- +-#define BPIFR _SFR_MEM8(0xF3) +-#define CHCIF 0 +-#define DHCIF 1 +-#define COCIF 2 +-#define DOCIF 3 +-#define SCIF 4 +- +-#define BPSCD _SFR_MEM8(0xF5) +-#define SCDL0 0 +-#define SCDL1 1 +-#define SCDL2 2 +-#define SCDL3 3 +-#define SCDL4 4 +-#define SCDL5 5 +-#define SCDL6 6 +-#define SCDL7 7 +- +-#define BPDOCD _SFR_MEM8(0xF6) +-#define DOCDL0 0 +-#define DOCDL1 1 +-#define DOCDL2 2 +-#define DOCDL3 3 +-#define DOCDL4 4 +-#define DOCDL5 5 +-#define DOCDL6 6 +-#define DOCDL7 7 +- +-#define BPCOCD _SFR_MEM8(0xF7) +-#define COCDL0 0 +-#define COCDL1 1 +-#define COCDL2 2 +-#define COCDL3 3 +-#define COCDL4 4 +-#define COCDL5 5 +-#define COCDL6 6 +-#define COCDL7 7 +- +-#define BPDHCD _SFR_MEM8(0xF8) +-#define DHCDL0 0 +-#define DHCDL1 1 +-#define DHCDL2 2 +-#define DHCDL3 3 +-#define DHCDL4 4 +-#define DHCDL5 5 +-#define DHCDL6 6 +-#define DHCDL7 7 +- +-#define BPCHCD _SFR_MEM8(0xF9) +-#define CHCDL0 0 +-#define CHCDL1 1 +-#define CHCDL2 2 +-#define CHCDL3 3 +-#define CHCDL4 4 +-#define CHCDL5 5 +-#define CHCDL6 6 +-#define CHCDL7 7 +- +-#define BPSCTR _SFR_MEM8(0xFA) +-#define SCPT0 0 +-#define SCPT1 1 +-#define SCPT2 2 +-#define SCPT3 3 +-#define SCPT4 4 +-#define SCPT5 5 +-#define SCPT6 6 +- +-#define BPOCTR _SFR_MEM8(0xFB) +-#define OCPT0 0 +-#define OCPT1 1 +-#define OCPT2 2 +-#define OCPT3 3 +-#define OCPT4 4 +-#define OCPT5 5 +- +-#define BPHCTR _SFR_MEM8(0xFC) +-#define HCPT0 0 +-#define HCPT1 1 +-#define HCPT2 2 +-#define HCPT3 3 +-#define HCPT4 4 +-#define HCPT5 5 +- +-#define BPCR _SFR_MEM8(0xFD) +-#define CHCD 0 +-#define DHCD 1 +-#define COCD 2 +-#define DOCD 3 +-#define SCD 4 +-#define EPID 5 +- +-#define BPPLR _SFR_MEM8(0xFE) +-#define BPPL 0 +-#define BPPLE 1 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define BPINT_vect_num 1 +-#define BPINT_vect _VECTOR(1) /* Battery Protection Interrupt */ +-#define VREGMON_vect_num 2 +-#define VREGMON_vect _VECTOR(2) /* Voltage regulator monitor interrupt */ +-#define INT0_vect_num 3 +-#define INT0_vect _VECTOR(3) /* External Interrupt Request 0 */ +-#define INT1_vect_num 4 +-#define INT1_vect _VECTOR(4) /* External Interrupt Request 1 */ +-#define INT2_vect_num 5 +-#define INT2_vect _VECTOR(5) /* External Interrupt Request 2 */ +-#define INT3_vect_num 6 +-#define INT3_vect _VECTOR(6) /* External Interrupt Request 3 */ +-#define PCINT0_vect_num 7 +-#define PCINT0_vect _VECTOR(7) /* Pin Change Interrupt 0 */ +-#define PCINT1_vect_num 8 +-#define PCINT1_vect _VECTOR(8) /* Pin Change Interrupt 1 */ +-#define WDT_vect_num 9 +-#define WDT_vect _VECTOR(9) /* Watchdog Timeout Interrupt */ +-#define BGSCD_vect_num 10 +-#define BGSCD_vect _VECTOR(10) /* Bandgap Buffer Short Circuit Detected */ +-#define CHDET_vect_num 11 +-#define CHDET_vect _VECTOR(11) /* Charger Detect */ +-#define TIMER1_IC_vect_num 12 +-#define TIMER1_IC_vect _VECTOR(12) /* Timer 1 Input capture */ +-#define TIMER1_COMPA_vect_num 13 +-#define TIMER1_COMPA_vect _VECTOR(13) /* Timer 1 Compare Match A */ +-#define TIMER1_COMPB_vect_num 14 +-#define TIMER1_COMPB_vect _VECTOR(14) /* Timer 1 Compare Match B */ +-#define TIMER1_OVF_vect_num 15 +-#define TIMER1_OVF_vect _VECTOR(15) /* Timer 1 overflow */ +-#define TIMER0_IC_vect_num 16 +-#define TIMER0_IC_vect _VECTOR(16) /* Timer 0 Input Capture */ +-#define TIMER0_COMPA_vect_num 17 +-#define TIMER0_COMPA_vect _VECTOR(17) /* Timer 0 Comapre Match A */ +-#define TIMER0_COMPB_vect_num 18 +-#define TIMER0_COMPB_vect _VECTOR(18) /* Timer 0 Compare Match B */ +-#define TIMER0_OVF_vect_num 19 +-#define TIMER0_OVF_vect _VECTOR(19) /* Timer 0 Overflow */ +-#define TWIBUSCD_vect_num 20 +-#define TWIBUSCD_vect _VECTOR(20) /* Two-Wire Bus Connect/Disconnect */ +-#define TWI_vect_num 21 +-#define TWI_vect _VECTOR(21) /* Two-Wire Serial Interface */ +-#define SPI_STC_vect_num 22 +-#define SPI_STC_vect _VECTOR(22) /* SPI Serial transfer complete */ +-#define VADC_vect_num 23 +-#define VADC_vect _VECTOR(23) /* Voltage ADC Conversion Complete */ +-#define CCADC_CONV_vect_num 24 +-#define CCADC_CONV_vect _VECTOR(24) /* Coulomb Counter ADC Conversion Complete */ +-#define CCADC_REG_CUR_vect_num 25 +-#define CCADC_REG_CUR_vect _VECTOR(25) /* Coloumb Counter ADC Regular Current */ +-#define CCADC_ACC_vect_num 26 +-#define CCADC_ACC_vect _VECTOR(26) /* Coloumb Counter ADC Accumulator */ +-#define EE_READY_vect_num 27 +-#define EE_READY_vect _VECTOR(27) /* EEPROM Ready */ +-#define SPM_vect_num 28 +-#define SPM_vect _VECTOR(28) /* SPM Ready */ +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (29 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (128) +-#define RAMSTART (0x100) +-#define RAMSIZE (1024) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (NA) +-#define XRAMEND (RAMEND) +-#define E2END (0x1FF) +-#define E2PAGESIZE (4) +-#define FLASHEND (0x3FFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 2 +- +-/* Low Fuse Byte */ +-#define FUSE_OSCSEL0 (unsigned char)~_BV(0) /* Oscillator Select */ +-#define FUSE_OSCSEL1 (unsigned char)~_BV(1) /* Oscillator Select */ +-#define FUSE_SUT0 (unsigned char)~_BV(2) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(3) /* Select start-up time */ +-#define FUSE_SUT2 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_EESAVE (unsigned char)~_BV(6) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(7) /* Watchdog Timer Always On */ +-#define LFUSE_DEFAULT (FUSE_SPIEN & FUSE_OSCSEL0) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_DWEN (unsigned char)~_BV(3) /* Enable debugWire */ +-#define FUSE_DUVRDINIT (unsigned char)~_BV(4) /* Reset Value of DUVRDRegister */ +-#define HFUSE_DEFAULT (FUSE_DUVRDINIT & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x94 +-#define SIGNATURE_2 0x0D +- +- +-/* Device Pin Definitions */ +-#define PV2_DDR DDRV +-#define PV2_PORT PORTV +-#define PV2_PIN PINV +-#define PV2_BIT 2 +- +-#define PV1_DDR DDRV +-#define PV1_PORT PORTV +-#define PV1_PIN PINV +-#define PV1_BIT 1 +- +-#define NV_DDR DDRNV +-#define NV_PORT PORTNV +-#define NV_PIN PINNV +-#define NV_BIT NV +- +-#define VFET_DDR DDRVFET +-#define VFET_PORT PORTVFET +-#define VFET_PIN PINVFET +-#define VFET_BIT VFET +- +-#define CF1P_DDR DDRCF1P +-#define CF1P_PORT PORTCF1P +-#define CF1P_PIN PINCF1P +-#define CF1P_BIT CF1P +- +-#define CF1N_DDR DDRCF1N +-#define CF1N_PORT PORTCF1N +-#define CF1N_PIN PINCF1N +-#define CF1N_BIT CF1N +- +-#define CF2P_DDR DDRCF2P +-#define CF2P_PORT PORTCF2P +-#define CF2P_PIN PINCF2P +-#define CF2P_BIT CF2P +- +-#define CF2N_DDR DDRCF2N +-#define CF2N_PORT PORTCF2N +-#define CF2N_PIN PINCF2N +-#define CF2N_BIT CF2N +- +-#define VREG_DDR DDRVREG +-#define VREG_PORT PORTVREG +-#define VREG_PIN PINVREG +-#define VREG_BIT VREG +- +-#define VREF_DDR DDRVREF +-#define VREF_PORT PORTVREF +-#define VREF_PIN PINVREF +-#define VREF_BIT VREF +- +-#define VREFGND_DDR DDRVREFGND +-#define VREFGND_PORT PORTVREFGND +-#define VREFGND_PIN PINVREFGND +-#define VREFGND_BIT VREFGND +- +-#define PI_DDR DDRI +-#define PI_PORT PORTI +-#define PI_PIN PINI +-#define PI_BIT +- +-#define NI_DDR DDRNI +-#define NI_PORT PORTNI +-#define NI_PIN PINNI +-#define NI_BIT NI +- +-#define PA0_DDR DDRA +-#define PA0_PORT PORTA +-#define PA0_PIN PINA +-#define PA0_BIT 0 +- +-#define PA1_DDR DDRA +-#define PA1_PORT PORTA +-#define PA1_PIN PINA +-#define PA1_BIT 1 +- +-#define PA2_DDR DDRA +-#define PA2_PORT PORTA +-#define PA2_PIN PINA +-#define PA2_BIT 2 +- +-#define PB0_DDR DDRB +-#define PB0_PORT PORTB +-#define PB0_PIN PINB +-#define PB0_BIT 0 +- +-#define PB1_DDR DDRB +-#define PB1_PORT PORTB +-#define PB1_PIN PINB +-#define PB1_BIT 1 +- +-#define PB2_DDR DDRB +-#define PB2_PORT PORTB +-#define PB2_PIN PINB +-#define PB2_BIT 2 +- +-#define PB3_DDR DDRB +-#define PB3_PORT PORTB +-#define PB3_PIN PINB +-#define PB3_BIT 3 +- +-#define PC0_DDR DDRC +-#define PC0_PORT PORTC +-#define PC0_PIN PINC +-#define PC0_BIT 0 +- +-#define BATT_DDR DDRBATT +-#define BATT_PORT PORTBATT +-#define BATT_PIN PINBATT +-#define BATT_BIT BATT +- +-#define OC_DDR DDROC +-#define OC_PORT PORTOC +-#define OC_PIN PINOC +-#define OC_BIT OC +- +-#endif /* _AVR_ATmega16HVBREVB_H_ */ +- ++/* Copyright (c) 2009, 2011 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom16hvbrevb.h 2086 2009-12-15 03:24:16Z arcanum $ */ ++ ++/* avr/iom16hvbrevb.h - definitions for ATmega16HVB revision B */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom16hvbrevb.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATmega16HVBREVB_H_ ++#define _AVR_ATmega16HVBREVB_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA0 0 ++#define PORTA1 1 ++#define PORTA2 2 ++#define PORTA3 3 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC3 3 ++#define PORTC4 4 ++#define PORTC5 5 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++#define ICF0 3 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 3 ++ ++#define OSICSR _SFR_IO8(0x17) ++#define OSIEN 0 ++#define OSIST 1 ++#define OSISEL0 4 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++#define INT3 3 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++#define EEAR9 1 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define ICS0 3 ++#define ICES0 4 ++#define ICNC0 5 ++#define ICEN0 6 ++#define TCW0 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++ ++#define TCNT0 _SFR_IO16(0x26) ++ ++#define TCNT0L _SFR_IO8(0x26) ++#define TCNT0L0 0 ++#define TCNT0L1 1 ++#define TCNT0L2 2 ++#define TCNT0L3 3 ++#define TCNT0L4 4 ++#define TCNT0L5 5 ++#define TCNT0L6 6 ++#define TCNT0L7 7 ++ ++#define TCNT0H _SFR_IO8(0x27) ++#define TCNT0H0 0 ++#define TCNT0H1 1 ++#define TCNT0H2 2 ++#define TCNT0H3 3 ++#define TCNT0H4 4 ++#define TCNT0H5 5 ++#define TCNT0H6 6 ++#define TCNT0H7 7 ++ ++#define OCR0A _SFR_IO8(0x28) ++#define OCR0A0 0 ++#define OCR0A1 1 ++#define OCR0A2 2 ++#define OCR0A3 3 ++#define OCR0A4 4 ++#define OCR0A5 5 ++#define OCR0A6 6 ++#define OCR0A7 7 ++ ++#define OCR0B _SFR_IO8(0x29) ++#define OCR0B0 0 ++#define OCR0B1 1 ++#define OCR0B2 2 ++#define OCR0B3 3 ++#define OCR0B4 4 ++#define OCR0B5 5 ++#define OCR0B6 6 ++#define OCR0B7 7 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define DWDR _SFR_IO8(0x31) ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BODRF 2 ++#define WDRF 3 ++#define OCDRF 4 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define CKOE 5 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define LBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPCE 7 ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRVADC 0 ++#define PRTIM0 1 ++#define PRTIM1 2 ++#define PRSPI 3 ++#define PRVRM 5 ++#define PRTWI 6 ++ ++#define FOSCCAL _SFR_MEM8(0x66) ++#define FCAL0 0 ++#define FCAL1 1 ++#define FCAL2 2 ++#define FCAL3 3 ++#define FCAL4 4 ++#define FCAL5 5 ++#define FCAL6 6 ++#define FCAL7 7 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT4 0 ++#define PCINT5 1 ++#define PCINT6 2 ++#define PCINT7 3 ++#define PCINT8 4 ++#define PCINT9 5 ++#define PCINT10 6 ++#define PCINT11 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++#define ICIE0 3 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 3 ++ ++#define VADC _SFR_MEM16(0x78) ++ ++#define VADCL _SFR_MEM8(0x78) ++#define VADC0 0 ++#define VADC1 1 ++#define VADC2 2 ++#define VADC3 3 ++#define VADC4 4 ++#define VADC5 5 ++#define VADC6 6 ++#define VADC7 7 ++ ++#define VADCH _SFR_MEM8(0x79) ++#define VADC8 0 ++#define VADC9 1 ++#define VADC10 2 ++#define VADC11 3 ++ ++#define VADCSR _SFR_MEM8(0x7A) ++#define VADCCIE 0 ++#define VADCCIF 1 ++#define VADSC 2 ++#define VADEN 3 ++ ++#define VADMUX _SFR_MEM8(0x7C) ++#define VADMUX0 0 ++#define VADMUX1 1 ++#define VADMUX2 2 ++#define VADMUX3 3 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define PA0DID 0 ++#define PA1DID 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define ICS1 3 ++#define ICES1 4 ++#define ICNC1 5 ++#define ICEN1 6 ++#define TCW1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define OCR1A _SFR_MEM8(0x88) ++#define OCR1A0 0 ++#define OCR1A1 1 ++#define OCR1A2 2 ++#define OCR1A3 3 ++#define OCR1A4 4 ++#define OCR1A5 5 ++#define OCR1A6 6 ++#define OCR1A7 7 ++ ++#define OCR1B _SFR_MEM8(0x89) ++#define OCR1B0 0 ++#define OCR1B1 1 ++#define OCR1B2 2 ++#define OCR1B3 3 ++#define OCR1B4 4 ++#define OCR1B5 5 ++#define OCR1B6 6 ++#define OCR1B7 7 ++ ++#define TWBR _SFR_MEM8(0xB8) ++#define TWBR0 0 ++#define TWBR1 1 ++#define TWBR2 2 ++#define TWBR3 3 ++#define TWBR4 4 ++#define TWBR5 5 ++#define TWBR6 6 ++#define TWBR7 7 ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++#define TWD0 0 ++#define TWD1 1 ++#define TWD2 2 ++#define TWD3 3 ++#define TWD4 4 ++#define TWD5 5 ++#define TWD6 6 ++#define TWD7 7 ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++#define TWBCSR _SFR_MEM8(0xBE) ++#define TWBCIP 0 ++#define TWBDT0 1 ++#define TWBDT1 2 ++#define TWBCIE 6 ++#define TWBCIF 7 ++ ++#define ROCR _SFR_MEM8(0xC8) ++#define ROCWIE 0 ++#define ROCWIF 1 ++#define ROCD 4 ++#define ROCS 7 ++ ++#define BGCCR _SFR_MEM8(0xD0) ++#define BGCC0 0 ++#define BGCC1 1 ++#define BGCC2 2 ++#define BGCC3 3 ++#define BGCC4 4 ++#define BGCC5 5 ++ ++#define BGCRR _SFR_MEM8(0xD1) ++#define BGCR0 0 ++#define BGCR1 1 ++#define BGCR2 2 ++#define BGCR3 3 ++#define BGCR4 4 ++#define BGCR5 5 ++#define BGCR6 6 ++#define BGCR7 7 ++ ++#define BGCSR _SFR_MEM8(0xD2) ++#define BGSCDIE 0 ++#define BGSCDIF 1 ++#define BGSCDE 4 ++#define BGD 5 ++ ++#define CHGDCSR _SFR_MEM8(0xD4) ++#define CHGDIE 0 ++#define CHGDIF 1 ++#define CHGDISC0 2 ++#define CHGDISC1 3 ++#define BATTPVL 4 ++ ++#define CADAC0 _SFR_MEM8(0xE0) ++#define CADAC00 0 ++#define CADAC01 1 ++#define CADAC02 2 ++#define CADAC03 3 ++#define CADAC04 4 ++#define CADAC05 5 ++#define CADAC06 6 ++#define CADAC07 7 ++ ++#define CADAC1 _SFR_MEM8(0xE1) ++#define CADAC08 0 ++#define CADAC09 1 ++#define CADAC10 2 ++#define CADAC11 3 ++#define CADAC12 4 ++#define CADAC13 5 ++#define CADAC14 6 ++#define CADAC15 7 ++ ++#define CADAC2 _SFR_MEM8(0xE2) ++#define CADAC16 0 ++#define CADAC17 1 ++#define CADAC18 2 ++#define CADAC19 3 ++#define CADAC20 4 ++#define CADAC21 5 ++#define CADAC22 6 ++#define CADAC23 7 ++ ++#define CADAC3 _SFR_MEM8(0xE3) ++#define CADAC24 0 ++#define CADAC25 1 ++#define CADAC26 2 ++#define CADAC27 3 ++#define CADAC28 4 ++#define CADAC29 5 ++#define CADAC30 6 ++#define CADAC31 7 ++ ++#define CADIC _SFR_MEM16(0xE4) ++ ++#define CADICL _SFR_MEM8(0xE4) ++#define CADICL0 0 ++#define CADICL1 1 ++#define CADICL2 2 ++#define CADICL3 3 ++#define CADICL4 4 ++#define CADICL5 5 ++#define CADICL6 6 ++#define CADICL7 7 ++ ++#define CADICH _SFR_MEM8(0xE5) ++#define CADICH0 0 ++#define CADICH1 1 ++#define CADICH2 2 ++#define CADICH3 3 ++#define CADICH4 4 ++#define CADICH5 5 ++#define CADICH6 6 ++#define CADICH7 7 ++ ++#define CADCSRA _SFR_MEM8(0xE6) ++#define CADSE 0 ++#define CADSI0 1 ++#define CADSI1 2 ++#define CADAS0 3 ++#define CADAS1 4 ++#define CADUB 5 ++#define CADPOL 6 ++#define CADEN 7 ++ ++#define CADCSRB _SFR_MEM8(0xE7) ++#define CADICIF 0 ++#define CADRCIF 1 ++#define CADACIF 2 ++#define CADICIE 4 ++#define CADRCIE 5 ++#define CADACIE 6 ++ ++#define CADCSRC _SFR_MEM8(0xE8) ++#define CADVSE 0 ++ ++#define CADRCC _SFR_MEM8(0xE9) ++#define CADRCC0 0 ++#define CADRCC1 1 ++#define CADRCC2 2 ++#define CADRCC3 3 ++#define CADRCC4 4 ++#define CADRCC5 5 ++#define CADRCC6 6 ++#define CADRCC7 7 ++ ++#define CADRDC _SFR_MEM8(0xEA) ++#define CADRDC0 0 ++#define CADRDC1 1 ++#define CADRDC2 2 ++#define CADRDC3 3 ++#define CADRDC4 4 ++#define CADRDC5 5 ++#define CADRDC6 6 ++#define CADRDC7 7 ++ ++#define FCSR _SFR_MEM8(0xF0) ++#define CFE 0 ++#define DFE 1 ++#define CPS 2 ++#define DUVRD 3 ++ ++#define CBCR _SFR_MEM8(0xF1) ++#define CBE1 0 ++#define CBE2 1 ++#define CBE3 2 ++#define CBE4 3 ++ ++#define BPIMSK _SFR_MEM8(0xF2) ++#define CHCIE 0 ++#define DHCIE 1 ++#define COCIE 2 ++#define DOCIE 3 ++#define SCIE 4 ++ ++#define BPIFR _SFR_MEM8(0xF3) ++#define CHCIF 0 ++#define DHCIF 1 ++#define COCIF 2 ++#define DOCIF 3 ++#define SCIF 4 ++ ++#define BPSCD _SFR_MEM8(0xF5) ++#define SCDL0 0 ++#define SCDL1 1 ++#define SCDL2 2 ++#define SCDL3 3 ++#define SCDL4 4 ++#define SCDL5 5 ++#define SCDL6 6 ++#define SCDL7 7 ++ ++#define BPDOCD _SFR_MEM8(0xF6) ++#define DOCDL0 0 ++#define DOCDL1 1 ++#define DOCDL2 2 ++#define DOCDL3 3 ++#define DOCDL4 4 ++#define DOCDL5 5 ++#define DOCDL6 6 ++#define DOCDL7 7 ++ ++#define BPCOCD _SFR_MEM8(0xF7) ++#define COCDL0 0 ++#define COCDL1 1 ++#define COCDL2 2 ++#define COCDL3 3 ++#define COCDL4 4 ++#define COCDL5 5 ++#define COCDL6 6 ++#define COCDL7 7 ++ ++#define BPDHCD _SFR_MEM8(0xF8) ++#define DHCDL0 0 ++#define DHCDL1 1 ++#define DHCDL2 2 ++#define DHCDL3 3 ++#define DHCDL4 4 ++#define DHCDL5 5 ++#define DHCDL6 6 ++#define DHCDL7 7 ++ ++#define BPCHCD _SFR_MEM8(0xF9) ++#define CHCDL0 0 ++#define CHCDL1 1 ++#define CHCDL2 2 ++#define CHCDL3 3 ++#define CHCDL4 4 ++#define CHCDL5 5 ++#define CHCDL6 6 ++#define CHCDL7 7 ++ ++#define BPSCTR _SFR_MEM8(0xFA) ++#define SCPT0 0 ++#define SCPT1 1 ++#define SCPT2 2 ++#define SCPT3 3 ++#define SCPT4 4 ++#define SCPT5 5 ++#define SCPT6 6 ++ ++#define BPOCTR _SFR_MEM8(0xFB) ++#define OCPT0 0 ++#define OCPT1 1 ++#define OCPT2 2 ++#define OCPT3 3 ++#define OCPT4 4 ++#define OCPT5 5 ++ ++#define BPHCTR _SFR_MEM8(0xFC) ++#define HCPT0 0 ++#define HCPT1 1 ++#define HCPT2 2 ++#define HCPT3 3 ++#define HCPT4 4 ++#define HCPT5 5 ++ ++#define BPCR _SFR_MEM8(0xFD) ++#define CHCD 0 ++#define DHCD 1 ++#define COCD 2 ++#define DOCD 3 ++#define SCD 4 ++#define EPID 5 ++ ++#define BPPLR _SFR_MEM8(0xFE) ++#define BPPL 0 ++#define BPPLE 1 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define BPINT_vect_num 1 ++#define BPINT_vect _VECTOR(1) /* Battery Protection Interrupt */ ++#define VREGMON_vect_num 2 ++#define VREGMON_vect _VECTOR(2) /* Voltage regulator monitor interrupt */ ++#define INT0_vect_num 3 ++#define INT0_vect _VECTOR(3) /* External Interrupt Request 0 */ ++#define INT1_vect_num 4 ++#define INT1_vect _VECTOR(4) /* External Interrupt Request 1 */ ++#define INT2_vect_num 5 ++#define INT2_vect _VECTOR(5) /* External Interrupt Request 2 */ ++#define INT3_vect_num 6 ++#define INT3_vect _VECTOR(6) /* External Interrupt Request 3 */ ++#define PCINT0_vect_num 7 ++#define PCINT0_vect _VECTOR(7) /* Pin Change Interrupt 0 */ ++#define PCINT1_vect_num 8 ++#define PCINT1_vect _VECTOR(8) /* Pin Change Interrupt 1 */ ++#define WDT_vect_num 9 ++#define WDT_vect _VECTOR(9) /* Watchdog Timeout Interrupt */ ++#define BGSCD_vect_num 10 ++#define BGSCD_vect _VECTOR(10) /* Bandgap Buffer Short Circuit Detected */ ++#define CHDET_vect_num 11 ++#define CHDET_vect _VECTOR(11) /* Charger Detect */ ++#define TIMER1_IC_vect_num 12 ++#define TIMER1_IC_vect _VECTOR(12) /* Timer 1 Input capture */ ++#define TIMER1_COMPA_vect_num 13 ++#define TIMER1_COMPA_vect _VECTOR(13) /* Timer 1 Compare Match A */ ++#define TIMER1_COMPB_vect_num 14 ++#define TIMER1_COMPB_vect _VECTOR(14) /* Timer 1 Compare Match B */ ++#define TIMER1_OVF_vect_num 15 ++#define TIMER1_OVF_vect _VECTOR(15) /* Timer 1 overflow */ ++#define TIMER0_IC_vect_num 16 ++#define TIMER0_IC_vect _VECTOR(16) /* Timer 0 Input Capture */ ++#define TIMER0_COMPA_vect_num 17 ++#define TIMER0_COMPA_vect _VECTOR(17) /* Timer 0 Comapre Match A */ ++#define TIMER0_COMPB_vect_num 18 ++#define TIMER0_COMPB_vect _VECTOR(18) /* Timer 0 Compare Match B */ ++#define TIMER0_OVF_vect_num 19 ++#define TIMER0_OVF_vect _VECTOR(19) /* Timer 0 Overflow */ ++#define TWIBUSCD_vect_num 20 ++#define TWIBUSCD_vect _VECTOR(20) /* Two-Wire Bus Connect/Disconnect */ ++#define TWI_vect_num 21 ++#define TWI_vect _VECTOR(21) /* Two-Wire Serial Interface */ ++#define SPI_STC_vect_num 22 ++#define SPI_STC_vect _VECTOR(22) /* SPI Serial transfer complete */ ++#define VADC_vect_num 23 ++#define VADC_vect _VECTOR(23) /* Voltage ADC Conversion Complete */ ++#define CCADC_CONV_vect_num 24 ++#define CCADC_CONV_vect _VECTOR(24) /* Coulomb Counter ADC Conversion Complete */ ++#define CCADC_REG_CUR_vect_num 25 ++#define CCADC_REG_CUR_vect _VECTOR(25) /* Coloumb Counter ADC Regular Current */ ++#define CCADC_ACC_vect_num 26 ++#define CCADC_ACC_vect _VECTOR(26) /* Coloumb Counter ADC Accumulator */ ++#define EE_READY_vect_num 27 ++#define EE_READY_vect _VECTOR(27) /* EEPROM Ready */ ++#define SPM_vect_num 28 ++#define SPM_vect _VECTOR(28) /* SPM Ready */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (29 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (128) ++#define RAMSTART (0x100) ++#define RAMSIZE (1024) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (NA) ++#define XRAMEND (RAMEND) ++#define E2END (0x1FF) ++#define E2PAGESIZE (4) ++#define FLASHEND (0x3FFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 2 ++ ++/* Low Fuse Byte */ ++#define FUSE_OSCSEL0 (unsigned char)~_BV(0) /* Oscillator Select */ ++#define FUSE_OSCSEL1 (unsigned char)~_BV(1) /* Oscillator Select */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Select start-up time */ ++#define FUSE_SUT2 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_EESAVE (unsigned char)~_BV(6) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(7) /* Watchdog Timer Always On */ ++#define LFUSE_DEFAULT (FUSE_SPIEN & FUSE_OSCSEL0) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_DWEN (unsigned char)~_BV(3) /* Enable debugWire */ ++#define FUSE_DUVRDINIT (unsigned char)~_BV(4) /* Reset Value of DUVRDRegister */ ++#define HFUSE_DEFAULT (FUSE_DUVRDINIT & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x0D ++ ++ ++/* Device Pin Definitions */ ++#define PV2_DDR DDRV ++#define PV2_PORT PORTV ++#define PV2_PIN PINV ++#define PV2_BIT 2 ++ ++#define PV1_DDR DDRV ++#define PV1_PORT PORTV ++#define PV1_PIN PINV ++#define PV1_BIT 1 ++ ++#define NV_DDR DDRNV ++#define NV_PORT PORTNV ++#define NV_PIN PINNV ++#define NV_BIT NV ++ ++#define VFET_DDR DDRVFET ++#define VFET_PORT PORTVFET ++#define VFET_PIN PINVFET ++#define VFET_BIT VFET ++ ++#define CF1P_DDR DDRCF1P ++#define CF1P_PORT PORTCF1P ++#define CF1P_PIN PINCF1P ++#define CF1P_BIT CF1P ++ ++#define CF1N_DDR DDRCF1N ++#define CF1N_PORT PORTCF1N ++#define CF1N_PIN PINCF1N ++#define CF1N_BIT CF1N ++ ++#define CF2P_DDR DDRCF2P ++#define CF2P_PORT PORTCF2P ++#define CF2P_PIN PINCF2P ++#define CF2P_BIT CF2P ++ ++#define CF2N_DDR DDRCF2N ++#define CF2N_PORT PORTCF2N ++#define CF2N_PIN PINCF2N ++#define CF2N_BIT CF2N ++ ++#define VREG_DDR DDRVREG ++#define VREG_PORT PORTVREG ++#define VREG_PIN PINVREG ++#define VREG_BIT VREG ++ ++#define VREF_DDR DDRVREF ++#define VREF_PORT PORTVREF ++#define VREF_PIN PINVREF ++#define VREF_BIT VREF ++ ++#define VREFGND_DDR DDRVREFGND ++#define VREFGND_PORT PORTVREFGND ++#define VREFGND_PIN PINVREFGND ++#define VREFGND_BIT VREFGND ++ ++#define PI_DDR DDRI ++#define PI_PORT PORTI ++#define PI_PIN PINI ++#define PI_BIT ++ ++#define NI_DDR DDRNI ++#define NI_PORT PORTNI ++#define NI_PIN PINNI ++#define NI_BIT NI ++ ++#define PA0_DDR DDRA ++#define PA0_PORT PORTA ++#define PA0_PIN PINA ++#define PA0_BIT 0 ++ ++#define PA1_DDR DDRA ++#define PA1_PORT PORTA ++#define PA1_PIN PINA ++#define PA1_BIT 1 ++ ++#define PA2_DDR DDRA ++#define PA2_PORT PORTA ++#define PA2_PIN PINA ++#define PA2_BIT 2 ++ ++#define PB0_DDR DDRB ++#define PB0_PORT PORTB ++#define PB0_PIN PINB ++#define PB0_BIT 0 ++ ++#define PB1_DDR DDRB ++#define PB1_PORT PORTB ++#define PB1_PIN PINB ++#define PB1_BIT 1 ++ ++#define PB2_DDR DDRB ++#define PB2_PORT PORTB ++#define PB2_PIN PINB ++#define PB2_BIT 2 ++ ++#define PB3_DDR DDRB ++#define PB3_PORT PORTB ++#define PB3_PIN PINB ++#define PB3_BIT 3 ++ ++#define PC0_DDR DDRC ++#define PC0_PORT PORTC ++#define PC0_PIN PINC ++#define PC0_BIT 0 ++ ++#define BATT_DDR DDRBATT ++#define BATT_PORT PORTBATT ++#define BATT_PIN PINBATT ++#define BATT_BIT BATT ++ ++#define OC_DDR DDROC ++#define OC_PORT PORTOC ++#define OC_PIN PINOC ++#define OC_BIT OC ++ ++#endif /* _AVR_ATmega16HVBREVB_H_ */ ++ +diff --git a/include/avr/iom16m1.h b/include/avr/iom16m1.h +index 9c052b3..54305e1 100644 +--- a/include/avr/iom16m1.h ++++ b/include/avr/iom16m1.h +@@ -1,1557 +1,1557 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom16m1.h 2183 2010-09-21 05:37:46Z aboyapati $ */ +- +-/* avr/iom16m1.h - definitions for ATmega16M1 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom16m1.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATmega16M1_H_ +-#define _AVR_ATmega16M1_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +-#define PINC7 7 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC3 3 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +-#define DDC7 7 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC3 3 +-#define PORTC4 4 +-#define PORTC5 5 +-#define PORTC6 6 +-#define PORTC7 7 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define PINE _SFR_IO8(0x0C) +-#define PINE0 0 +-#define PINE1 1 +-#define PINE2 2 +- +-#define DDRE _SFR_IO8(0x0D) +-#define DDE0 0 +-#define DDE1 1 +-#define DDE2 2 +- +-#define PORTE _SFR_IO8(0x0E) +-#define PORTE0 0 +-#define PORTE1 1 +-#define PORTE2 2 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define GPIOR1 _SFR_IO8(0x19) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x1A) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +-#define PCIF1 1 +-#define PCIF2 2 +-#define PCIF3 3 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +-#define INTF2 2 +-#define INTF3 3 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +-#define INT2 2 +-#define INT3 3 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEWE 1 +-#define EEMWE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +-#define EEAR9 1 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSR10 0 +-#define PSRSYNC 0 +-#define ICPSEL1 6 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define OCR0A _SFR_IO8(0x27) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define OCR0B _SFR_IO8(0x28) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define PLLCSR _SFR_IO8(0x29) +-#define PLOCK 0 +-#define PLLE 1 +-#define PLLF 2 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define ACSR _SFR_IO8(0x30) +-#define AC0O 0 +-#define AC1O 1 +-#define AC2O 2 +-#define AC3O 3 +-#define AC0IF 4 +-#define AC1IF 5 +-#define AC2IF 6 +-#define AC3IF 7 +- +-#define DWDR _SFR_IO8(0x31) +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define SPIPS 7 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define SIGRD 5 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRLIN 1 +-#define PRSPI 2 +-#define PRTIM0 3 +-#define PRTIM1 4 +-#define PRPSC 5 +-#define PRCAN 6 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +-#define PCIE1 1 +-#define PCIE2 2 +-#define PCIE3 3 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define ISC20 4 +-#define ISC21 5 +-#define ISC30 6 +-#define ISC31 7 +- +-#define PCMSK0 _SFR_MEM8(0x6A) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6B) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-#define PCMSK2 _SFR_MEM8(0x6C) +-#define PCINT16 0 +-#define PCINT17 1 +-#define PCINT18 2 +-#define PCINT19 3 +-#define PCINT20 4 +-#define PCINT21 5 +-#define PCINT22 6 +-#define PCINT23 7 +- +-#define PCMSK3 _SFR_MEM8(0x6D) +-#define PCINT24 0 +-#define PCINT25 1 +-#define PCINT26 2 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define AMP0CSR _SFR_MEM8(0x75) +-#define AMP0TS0 0 +-#define AMP0TS1 1 +-#define AMP0TS2 2 +-#define AMPCMP0 3 +-#define AMP0G0 4 +-#define AMP0G1 5 +-#define AMP0IS 6 +-#define AMP0EN 7 +- +-#define AMP1CSR _SFR_MEM8(0x76) +-#define AMP1TS0 0 +-#define AMP1TS1 1 +-#define AMP1TS2 2 +-#define AMPCMP1 3 +-#define AMP1G0 4 +-#define AMP1G1 5 +-#define AMP1IS 6 +-#define AMP1EN 7 +- +-#define AMP2CSR _SFR_MEM8(0x77) +-#define AMP2TS0 0 +-#define AMP2TS1 1 +-#define AMP2TS2 2 +-#define AMPCMP2 3 +-#define AMP2G0 4 +-#define AMP2G1 5 +-#define AMP2IS 6 +-#define AMP2EN 7 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +- +-#define ADCL _SFR_MEM8(0x78) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_MEM8(0x79) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ADTS3 3 +-#define AREFEN 5 +-#define ISRCEN 6 +-#define ADHSM 7 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define ADC8D 0 +-#define ADC9D 1 +-#define ADC10D 2 +-#define AMP0ND 3 +-#define AMP0PD 4 +-#define ACMP0D 5 +-#define AMP2PD 6 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define DACON _SFR_MEM8(0x90) +-#define DAEN 0 +-#define DAOE 1 +-#define DALA 2 +-#define DATS0 4 +-#define DATS1 5 +-#define DATS2 6 +-#define DAATE 7 +- +-#define DAC _SFR_MEM16(0x91) +- +-#define DACL _SFR_MEM8(0x91) +-#define DACL0 0 +-#define DACL1 1 +-#define DACL2 2 +-#define DACL3 3 +-#define DACL4 4 +-#define DACL5 5 +-#define DACL6 6 +-#define DACL7 7 +- +-#define DACH _SFR_MEM8(0x92) +-#define DACH0 0 +-#define DACH1 1 +-#define DACH2 2 +-#define DACH3 3 +-#define DACH4 4 +-#define DACH5 5 +-#define DACH6 6 +-#define DACH7 7 +- +-#define AC0CON _SFR_MEM8(0x94) +-#define AC0M0 0 +-#define AC0M1 1 +-#define AC0M2 2 +-#define ACCKSEL 3 +-#define AC0IS0 4 +-#define AC0IS1 5 +-#define AC0IE 6 +-#define AC0EN 7 +- +-#define AC1CON _SFR_MEM8(0x95) +-#define AC1M0 0 +-#define AC1M1 1 +-#define AC1M2 2 +-#define AC1ICE 3 +-#define AC1IS0 4 +-#define AC1IS1 5 +-#define AC1IE 6 +-#define AC1EN 7 +- +-#define AC2CON _SFR_MEM8(0x96) +-#define AC2M0 0 +-#define AC2M1 1 +-#define AC2M2 2 +-#define AC2IS0 4 +-#define AC2IS1 5 +-#define AC2IE 6 +-#define AC2EN 7 +- +-#define AC3CON _SFR_MEM8(0x97) +-#define AC3M0 0 +-#define AC3M1 1 +-#define AC3M2 2 +-#define AC3IS0 4 +-#define AC3IS1 5 +-#define AC3IE 6 +-#define AC3EN 7 +- +-#define POCR0SA _SFR_MEM16(0xA0) +- +-#define POCR0SAL _SFR_MEM8(0xA0) +-#define POCR0SA_0 0 +-#define POCR0SA_1 1 +-#define POCR0SA_2 2 +-#define POCR0SA_3 3 +-#define POCR0SA_4 4 +-#define POCR0SA_5 5 +-#define POCR0SA_6 6 +-#define POCR0SA_7 7 +- +-#define POCR0SAH _SFR_MEM8(0xA1) +-#define POCR0SA_8 0 +-#define POCR0SA_9 1 +-#define POCR0SA_10 2 +-#define POCR0SA_11 3 +- +-#define POCR0RA _SFR_MEM16(0xA2) +- +-#define POCR0RAL _SFR_MEM8(0xA2) +-#define POCR0RA_0 0 +-#define POCR0RA_1 1 +-#define POCR0RA_2 2 +-#define POCR0RA_3 3 +-#define POCR0RA_4 4 +-#define POCR0RA_5 5 +-#define POCR0RA_6 6 +-#define POCR0RA_7 7 +- +-#define POCR0RAH _SFR_MEM8(0xA3) +-#define POCR0RA_8 0 +-#define POCR0RA_9 1 +-#define POCR0RA_10 2 +-#define POCR0RA_11 3 +- +-#define POCR0SB _SFR_MEM16(0xA4) +- +-#define POCR0SBL _SFR_MEM8(0xA4) +-#define POCR0SB_0 0 +-#define POCR0SB_1 1 +-#define POCR0SB_2 2 +-#define POCR0SB_3 3 +-#define POCR0SB_4 4 +-#define POCR0SB_5 5 +-#define POCR0SB_6 6 +-#define POCR0SB_7 7 +- +-#define POCR0SBH _SFR_MEM8(0xA5) +-#define POCR0SB_8 0 +-#define POCR0SB_9 1 +-#define POCR0SB_10 2 +-#define POCR0SB_11 3 +- +-#define POCR1SA _SFR_MEM16(0xA6) +- +-#define POCR1SAL _SFR_MEM8(0xA6) +-#define POCR1SA_0 0 +-#define POCR1SA_1 1 +-#define POCR1SA_2 2 +-#define POCR1SA_3 3 +-#define POCR1SA_4 4 +-#define POCR1SA_5 5 +-#define POCR1SA_6 6 +-#define POCR1SA_7 7 +- +-#define POCR1SAH _SFR_MEM8(0xA7) +-#define POCR1SA_8 0 +-#define POCR1SA_9 1 +-#define POCR1SA_10 2 +-#define POCR1SA_11 3 +- +-#define POCR1RA _SFR_MEM16(0xA8) +- +-#define POCR1RAL _SFR_MEM8(0xA8) +-#define POCR1RA_0 0 +-#define POCR1RA_1 1 +-#define POCR1RA_2 2 +-#define POCR1RA_3 3 +-#define POCR1RA_4 4 +-#define POCR1RA_5 5 +-#define POCR1RA_6 6 +-#define POCR1RA_7 7 +- +-#define POCR1RAH _SFR_MEM8(0xA9) +-#define POCR1RA_8 0 +-#define POCR1RA_9 1 +-#define POCR1RA_10 2 +-#define POCR1RA_11 3 +- +-#define POCR1SB _SFR_MEM16(0xAA) +- +-#define POCR1SBL _SFR_MEM8(0xAA) +-#define POCR1SB_0 0 +-#define POCR1SB_1 1 +-#define POCR1SB_2 2 +-#define POCR1SB_3 3 +-#define POCR1SB_4 4 +-#define POCR1SB_5 5 +-#define POCR1SB_6 6 +-#define POCR1SB_7 7 +- +-#define POCR1SBH _SFR_MEM8(0xAB) +-#define POCR1SB_8 0 +-#define POCR1SB_9 1 +-#define POCR1SB_10 2 +-#define POCR1SB_11 3 +- +-#define POCR2SA _SFR_MEM16(0xAC) +- +-#define POCR2SAL _SFR_MEM8(0xAC) +-#define POCR2SA_0 0 +-#define POCR2SA_1 1 +-#define POCR2SA_2 2 +-#define POCR2SA_3 3 +-#define POCR2SA_4 4 +-#define POCR2SA_5 5 +-#define POCR2SA_6 6 +-#define POCR2SA_7 7 +- +-#define POCR2SAH _SFR_MEM8(0xAD) +-#define POCR2SA_8 0 +-#define POCR2SA_9 1 +-#define POCR2SA_10 2 +-#define POCR2SA_11 3 +- +-#define POCR2RA _SFR_MEM16(0xAE) +- +-#define POCR2RAL _SFR_MEM8(0xAE) +-#define POCR2RA_0 0 +-#define POCR2RA_1 1 +-#define POCR2RA_2 2 +-#define POCR2RA_3 3 +-#define POCR2RA_4 4 +-#define POCR2RA_5 5 +-#define POCR2RA_6 6 +-#define POCR2RA_7 7 +- +-#define POCR2RAH _SFR_MEM8(0xAF) +-#define POCR2RA_8 0 +-#define POCR2RA_9 1 +-#define POCR2RA_10 2 +-#define POCR2RA_11 3 +- +-#define POCR2SB _SFR_MEM16(0xB0) +- +-#define POCR2SBL _SFR_MEM8(0xB0) +-#define POCR2SB_0 0 +-#define POCR2SB_1 1 +-#define POCR2SB_2 2 +-#define POCR2SB_3 3 +-#define POCR2SB_4 4 +-#define POCR2SB_5 5 +-#define POCR2SB_6 6 +-#define POCR2SB_7 7 +- +-#define POCR2SBH _SFR_MEM8(0xB1) +-#define POCR2SB_8 0 +-#define POCR2SB_9 1 +-#define POCR2SB_10 2 +-#define POCR2SB_11 3 +- +-#define POCR_RB _SFR_MEM16(0xB2) +- +-#define POCR_RBL _SFR_MEM8(0xB2) +-#define POCR_RB_0 0 +-#define POCR_RB_1 1 +-#define POCR_RB_2 2 +-#define POCR_RB_3 3 +-#define POCR_RB_4 4 +-#define POCR_RB_5 5 +-#define POCR_RB_6 6 +-#define POCR_RB_7 7 +- +-#define POCR_RBH _SFR_MEM8(0xB3) +-#define POCR_RB_8 0 +-#define POCR_RB_9 1 +-#define POCR_RB_10 2 +-#define POCR_RB_11 3 +- +-#define PSYNC _SFR_MEM8(0xB4) +-#define PSYNC00 0 +-#define PSYNC01 1 +-#define PSYNC10 2 +-#define PSYNC11 3 +-#define PSYNC20 4 +-#define PSYNC21 5 +- +-#define PCNF _SFR_MEM8(0xB5) +-#define POPA 2 +-#define POPB 3 +-#define PMODE 4 +-#define PULOCK 5 +- +-#define POC _SFR_MEM8(0xB6) +-#define POEN0A 0 +-#define POEN0B 1 +-#define POEN1A 2 +-#define POEN1B 3 +-#define POEN2A 4 +-#define POEN2B 5 +- +-#define PCTL _SFR_MEM8(0xB7) +-#define PRUN 0 +-#define PCCYC 1 +-#define PCLKSEL 5 +-#define PPRE0 6 +-#define PPRE1 7 +- +-#define PMIC0 _SFR_MEM8(0xB8) +-#define PRFM00 0 +-#define PRFM01 1 +-#define PRFM02 2 +-#define PAOC0 3 +-#define PFLTE0 4 +-#define PELEV0 5 +-#define PISEL0 6 +-#define POVEN0 7 +- +-#define PMIC1 _SFR_MEM8(0xB9) +-#define PRFM10 0 +-#define PRFM11 1 +-#define PRFM12 2 +-#define PAOC1 3 +-#define PFLTE1 4 +-#define PELEV1 5 +-#define PISEL1 6 +-#define POVEN1 7 +- +-#define PMIC2 _SFR_MEM8(0xBA) +-#define PRFM20 0 +-#define PRFM21 1 +-#define PRFM22 2 +-#define PAOC2 3 +-#define PFLTE2 4 +-#define PELEV2 5 +-#define PISEL2 6 +-#define POVEN2 7 +- +-#define PIM _SFR_MEM8(0xBB) +-#define PEOPE 0 +-#define PEVE0 1 +-#define PEVE1 2 +-#define PEVE2 3 +- +-#define PIFR _SFR_MEM8(0xBC) +-#define PEOP 0 +-#define PEV0 1 +-#define PEV1 2 +-#define PEV2 3 +- +-#define LINCR _SFR_MEM8(0xC8) +-#define LCMD0 0 +-#define LCMD1 1 +-#define LCMD2 2 +-#define LENA 3 +-#define LCONF0 4 +-#define LCONF1 5 +-#define LIN13 6 +-#define LSWRES 7 +- +-#define LINSIR _SFR_MEM8(0xC9) +-#define LRXOK 0 +-#define LTXOK 1 +-#define LIDOK 2 +-#define LERR 3 +-#define LBUSY 4 +-#define LIDST0 5 +-#define LIDST1 6 +-#define LIDST2 7 +- +-#define LINENIR _SFR_MEM8(0xCA) +-#define LENRXOK 0 +-#define LENTXOK 1 +-#define LENIDOK 2 +-#define LENERR 3 +- +-#define LINERR _SFR_MEM8(0xCB) +-#define LBERR 0 +-#define LCERR 1 +-#define LPERR 2 +-#define LSERR 3 +-#define LFERR 4 +-#define LOVERR 5 +-#define LTOERR 6 +-#define LABORT 7 +- +-#define LINBTR _SFR_MEM8(0xCC) +-#define LBT0 0 +-#define LBT1 1 +-#define LBT2 2 +-#define LBT3 3 +-#define LBT4 4 +-#define LBT5 5 +-#define LDISR 7 +- +-#define LINBRR _SFR_MEM16(0xCD) +- +-#define LINBRRL _SFR_MEM8(0xCD) +-#define LDIV0 0 +-#define LDIV1 1 +-#define LDIV2 2 +-#define LDIV3 3 +-#define LDIV4 4 +-#define LDIV5 5 +-#define LDIV6 6 +-#define LDIV7 7 +- +-#define LINBRRH _SFR_MEM8(0xCE) +-#define LDIV8 0 +-#define LDIV9 1 +-#define LDIV10 2 +-#define LDIV11 3 +- +-#define LINDLR _SFR_MEM8(0xCF) +-#define LRXDL0 0 +-#define LRXDL1 1 +-#define LRXDL2 2 +-#define LRXDL3 3 +-#define LTXDL0 4 +-#define LTXDL1 5 +-#define LTXDL2 6 +-#define LTXDL3 7 +- +-#define LINIDR _SFR_MEM8(0xD0) +-#define LID0 0 +-#define LID1 1 +-#define LID2 2 +-#define LID3 3 +-#define LID4 4 +-#define LID5 5 +-#define LP0 6 +-#define LP1 7 +- +-#define LINSEL _SFR_MEM8(0xD1) +-#define LINDX0 0 +-#define LINDX1 1 +-#define LINDX2 2 +-#define LAINC 3 +- +-#define LINDAT _SFR_MEM8(0xD2) +-#define LDATA0 0 +-#define LDATA1 1 +-#define LDATA2 2 +-#define LDATA3 3 +-#define LDATA4 4 +-#define LDATA5 5 +-#define LDATA6 6 +-#define LDATA7 7 +- +-#define CANGCON _SFR_MEM8(0xD8) +-#define SWRES 0 +-#define ENASTB 1 +-#define TEST 2 +-#define LISTEN 3 +-#define SYNTTC 4 +-#define TTC 5 +-#define OVRQ 6 +-#define ABRQ 7 +- +-#define CANGSTA _SFR_MEM8(0xD9) +-#define ERRP 0 +-#define BOFF 1 +-#define ENFG 2 +-#define RXBSY 3 +-#define TXBSY 4 +-#define OVFG 6 +- +-#define CANGIT _SFR_MEM8(0xDA) +-#define AERG 0 +-#define FERG 1 +-#define CERG 2 +-#define SERG 3 +-#define BXOK 4 +-#define OVRTIM 5 +-#define BOFFIT 6 +-#define CANIT 7 +- +-#define CANGIE _SFR_MEM8(0xDB) +-#define ENOVRT 0 +-#define ENERG 1 +-#define ENBX 2 +-#define ENERR 3 +-#define ENTX 4 +-#define ENRX 5 +-#define ENBOFF 6 +-#define ENIT 7 +- +-#define CANEN2 _SFR_MEM8(0xDC) +-#define ENMOB0 0 +-#define ENMOB1 1 +-#define ENMOB2 2 +-#define ENMOB3 3 +-#define ENMOB4 4 +-#define ENMOB5 5 +- +-#define CANEN1 _SFR_MEM8(0xDD) +- +-#define CANIE2 _SFR_MEM8(0xDE) +-#define IEMOB0 0 +-#define IEMOB1 1 +-#define IEMOB2 2 +-#define IEMOB3 3 +-#define IEMOB4 4 +-#define IEMOB5 5 +- +-#define CANIE1 _SFR_MEM8(0xDF) +- +-/* RegDef: CAN Status Interrupt MOb Register*/ +-#define CANSIT _SFR_MEM16(0xE0) +- +-#define CANSIT2 _SFR_MEM8(0xE0) +-#define SIT0 0 +-#define SIT1 1 +-#define SIT2 2 +-#define SIT3 3 +-#define SIT4 4 +-#define SIT5 5 +- +-#define CANSIT1 _SFR_MEM8(0xE1) +- +-#define CANBT1 _SFR_MEM8(0xE2) +-#define BRP0 1 +-#define BRP1 2 +-#define BRP2 3 +-#define BRP3 4 +-#define BRP4 5 +-#define BRP5 6 +- +-#define CANBT2 _SFR_MEM8(0xE3) +-#define PRS0 1 +-#define PRS1 2 +-#define PRS2 3 +-#define SJW0 5 +-#define SJW1 6 +- +-#define CANBT3 _SFR_MEM8(0xE4) +-#define SMP 0 +-#define PHS10 1 +-#define PHS11 2 +-#define PHS12 3 +-#define PHS20 4 +-#define PHS21 5 +-#define PHS22 6 +- +-#define CANTCON _SFR_MEM8(0xE5) +-#define TPRSC0 0 +-#define TPRSC1 1 +-#define TPRSC2 2 +-#define TPRSC3 3 +-#define TPRSC4 4 +-#define TPRSC5 5 +-#define TPRSC6 6 +-#define TPRSC7 7 +- +-#define CANTIM _SFR_MEM16(0xE6) +- +-#define CANTIML _SFR_MEM8(0xE6) +-#define CANTIM0 0 +-#define CANTIM1 1 +-#define CANTIM2 2 +-#define CANTIM3 3 +-#define CANTIM4 4 +-#define CANTIM5 5 +-#define CANTIM6 6 +-#define CANTIM7 7 +- +-#define CANTIMH _SFR_MEM8(0xE7) +-#define CANTIM8 0 +-#define CANTIM9 1 +-#define CANTIM10 2 +-#define CANTIM11 3 +-#define CANTIM12 4 +-#define CANTIM13 5 +-#define CANTIM14 6 +-#define CANTIM15 7 +- +-#define CANTTC _SFR_MEM16(0xE8) +- +-#define CANTTCL _SFR_MEM8(0xE8) +-#define TIMTCC0 0 +-#define TIMTCC1 1 +-#define TIMTCC2 2 +-#define TIMTCC3 3 +-#define TIMTCC4 4 +-#define TIMTCC5 5 +-#define TIMTCC6 6 +-#define TIMTCC7 7 +- +-#define CANTTCH _SFR_MEM8(0xE9) +-#define TIMTCC8 0 +-#define TIMTCC9 1 +-#define TIMTCC10 2 +-#define TIMTCC11 3 +-#define TIMTCC12 4 +-#define TIMTCC13 5 +-#define TIMTCC14 6 +-#define TIMTCC15 7 +- +-#define CANTEC _SFR_MEM8(0xEA) +-#define TEC0 0 +-#define TEC1 1 +-#define TEC2 2 +-#define TEC3 3 +-#define TEC4 4 +-#define TEC5 5 +-#define TEC6 6 +-#define TEC7 7 +- +-#define CANREC _SFR_MEM8(0xEB) +-#define REC0 0 +-#define REC1 1 +-#define REC2 2 +-#define REC3 3 +-#define REC4 4 +-#define REC5 5 +-#define REC6 6 +-#define REC7 7 +- +-#define CANHPMOB _SFR_MEM8(0xEC) +-#define CGP0 0 +-#define CGP1 1 +-#define CGP2 2 +-#define CGP3 3 +-#define HPMOB0 4 +-#define HPMOB1 5 +-#define HPMOB2 6 +-#define HPMOB3 7 +- +-#define CANPAGE _SFR_MEM8(0xED) +-#define INDX0 0 +-#define INDX1 1 +-#define INDX2 2 +-#define AINC 3 +-#define MOBNB0 4 +-#define MOBNB1 5 +-#define MOBNB2 6 +-#define MOBNB3 7 +- +-#define CANSTMOB _SFR_MEM8(0xEE) +-#define AERR 0 +-#define FERR 1 +-#define CERR 2 +-#define SERR 3 +-#define BERR 4 +-#define RXOK 5 +-#define TXOK 6 +-#define DLCW 7 +- +-#define CANCDMOB _SFR_MEM8(0xEF) +-#define DLC0 0 +-#define DLC1 1 +-#define DLC2 2 +-#define DLC3 3 +-#define IDE 4 +-#define RPLV 5 +-#define CONMOB0 6 +-#define CONMOB1 7 +- +-/* RegDef: CAN Identifier Tag Registers*/ +-#define CANIDT _SFR_MEM32(0xF0) +- +-#define CANIDT4 _SFR_MEM8(0xF0) +-#define RB0TAG 0 +-#define RB1TAG 1 +-#define RTRTAG 2 +-#define IDT0 3 +-#define IDT1 4 +-#define IDT2 5 +-#define IDT3 6 +-#define IDT4 7 +- +-#define CANIDT3 _SFR_MEM8(0xF1) +-#define IDT5 0 +-#define IDT6 1 +-#define IDT7 2 +-#define IDT8 3 +-#define IDT9 4 +-#define IDT10 5 +-#define IDT11 6 +-#define IDT12 7 +- +-#define CANIDT2 _SFR_MEM8(0xF2) +-#define IDT13 0 +-#define IDT14 1 +-#define IDT15 2 +-#define IDT16 3 +-#define IDT17 4 +-#define IDT18 5 +-#define IDT19 6 +-#define IDT20 7 +- +-#define CANIDT1 _SFR_MEM8(0xF3) +-#define IDT21 0 +-#define IDT22 1 +-#define IDT23 2 +-#define IDT24 3 +-#define IDT25 4 +-#define IDT26 5 +-#define IDT27 6 +-#define IDT28 7 +- +-/* RegDef: CAN Identifier Mask Registers */ +-#define CANIDM _SFR_MEM32(0xF4) +- +-#define CANIDM4 _SFR_MEM8(0xF4) +-#define IDEMSK 0 +-#define RTRMSK 2 +-#define IDMSK0 3 +-#define IDMSK1 4 +-#define IDMSK2 5 +-#define IDMSK3 6 +-#define IDMSK4 7 +- +-#define CANIDM3 _SFR_MEM8(0xF5) +-#define IDMSK5 0 +-#define IDMSK6 1 +-#define IDMSK7 2 +-#define IDMSK8 3 +-#define IDMSK9 4 +-#define IDMSK10 5 +-#define IDMSK11 6 +-#define IDMSK12 7 +- +-#define CANIDM2 _SFR_MEM8(0xF6) +-#define IDMSK13 0 +-#define IDMSK14 1 +-#define IDMSK15 2 +-#define IDMSK16 3 +-#define IDMSK17 4 +-#define IDMSK18 5 +-#define IDMSK19 6 +-#define IDMSK20 7 +- +-#define CANIDM1 _SFR_MEM8(0xF7) +-#define IDMSK21 0 +-#define IDMSK22 1 +-#define IDMSK23 2 +-#define IDMSK24 3 +-#define IDMSK25 4 +-#define IDMSK26 5 +-#define IDMSK27 6 +-#define IDMSK28 7 +- +-#define CANSTM _SFR_MEM16(0xF8) +- +-#define CANSTML _SFR_MEM8(0xF8) +-#define TIMSTM0 0 +-#define TIMSTM1 1 +-#define TIMSTM2 2 +-#define TIMSTM3 3 +-#define TIMSTM4 4 +-#define TIMSTM5 5 +-#define TIMSTM6 6 +-#define TIMSTM7 7 +- +-#define CANSTMH _SFR_MEM8(0xF9) +-#define TIMSTM8 0 +-#define TIMSTM9 1 +-#define TIMSTM10 2 +-#define TIMSTM11 3 +-#define TIMSTM12 4 +-#define TIMSTM13 5 +-#define TIMSTM14 6 +-#define TIMSTM15 7 +- +-#define CANMSG _SFR_MEM8(0xFA) +-#define MSG0 0 +-#define MSG1 1 +-#define MSG2 2 +-#define MSG3 3 +-#define MSG4 4 +-#define MSG5 5 +-#define MSG6 6 +-#define MSG7 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define ANACOMP0_vect_num 1 +-#define ANACOMP0_vect _VECTOR(1) /* Analog Comparator 0 */ +-#define ANACOMP1_vect_num 2 +-#define ANACOMP1_vect _VECTOR(2) /* Analog Comparator 1 */ +-#define ANACOMP2_vect_num 3 +-#define ANACOMP2_vect _VECTOR(3) /* Analog Comparator 2 */ +-#define ANACOMP3_vect_num 4 +-#define ANACOMP3_vect _VECTOR(4) /* Analog Comparator 3 */ +-#define PSC_FAULT_vect_num 5 +-#define PSC_FAULT_vect _VECTOR(5) /* PSC Fault */ +-#define PSC_EC_vect_num 6 +-#define PSC_EC_vect _VECTOR(6) /* PSC End of Cycle */ +-#define INT0_vect_num 7 +-#define INT0_vect _VECTOR(7) /* External Interrupt Request 0 */ +-#define INT1_vect_num 8 +-#define INT1_vect _VECTOR(8) /* External Interrupt Request 1 */ +-#define INT2_vect_num 9 +-#define INT2_vect _VECTOR(9) /* External Interrupt Request 2 */ +-#define INT3_vect_num 10 +-#define INT3_vect _VECTOR(10) /* External Interrupt Request 3 */ +-#define TIMER1_CAPT_vect_num 11 +-#define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */ +-#define TIMER1_COMPA_vect_num 12 +-#define TIMER1_COMPA_vect _VECTOR(12) /* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPB_vect_num 13 +-#define TIMER1_COMPB_vect _VECTOR(13) /* Timer/Counter1 Compare Match B */ +-#define TIMER1_OVF_vect_num 14 +-#define TIMER1_OVF_vect _VECTOR(14) /* Timer1/Counter1 Overflow */ +-#define TIMER0_COMPA_vect_num 15 +-#define TIMER0_COMPA_vect _VECTOR(15) /* Timer/Counter0 Compare Match A */ +-#define TIMER0_COMPB_vect_num 16 +-#define TIMER0_COMPB_vect _VECTOR(16) /* Timer/Counter0 Compare Match B */ +-#define TIMER0_OVF_vect_num 17 +-#define TIMER0_OVF_vect _VECTOR(17) /* Timer/Counter0 Overflow */ +-#define CAN_INT_vect_num 18 +-#define CAN_INT_vect _VECTOR(18) /* CAN MOB, Burst, General Errors */ +-#define CAN_TOVF_vect_num 19 +-#define CAN_TOVF_vect _VECTOR(19) /* CAN Timer Overflow */ +-#define LIN_TC_vect_num 20 +-#define LIN_TC_vect _VECTOR(20) /* LIN Transfer Complete */ +-#define LIN_ERR_vect_num 21 +-#define LIN_ERR_vect _VECTOR(21) /* LIN Error */ +-#define PCINT0_vect_num 22 +-#define PCINT0_vect _VECTOR(22) /* Pin Change Interrupt Request 0 */ +-#define PCINT1_vect_num 23 +-#define PCINT1_vect _VECTOR(23) /* Pin Change Interrupt Request 1 */ +-#define PCINT2_vect_num 24 +-#define PCINT2_vect _VECTOR(24) /* Pin Change Interrupt Request 2 */ +-#define PCINT3_vect_num 25 +-#define PCINT3_vect _VECTOR(25) /* Pin Change Interrupt Request 3 */ +-#define SPI_STC_vect_num 26 +-#define SPI_STC_vect _VECTOR(26) /* SPI Serial Transfer Complete */ +-#define ADC_vect_num 27 +-#define ADC_vect _VECTOR(27) /* ADC Conversion Complete */ +-#define WDT_vect_num 28 +-#define WDT_vect _VECTOR(28) /* Watchdog Time-Out Interrupt */ +-#define EE_READY_vect_num 29 +-#define EE_READY_vect _VECTOR(29) /* EEPROM Ready */ +-#define SPM_READY_vect_num 30 +-#define SPM_READY_vect _VECTOR(30) /* Store Program Memory Read */ +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (31 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (128) +-#define RAMSTART (0x0100) +-#define RAMSIZE (1024) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (0x0) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x1FF) +-#define E2PAGESIZE (4) +-#define FLASHEND (0x3FFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector Trigger Level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector Trigger Level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector Trigger Level */ +-#define FUSE_PSCRVB (unsigned char)~_BV(3) /* PSC Outputs xB Reset Value */ +-#define FUSE_PSCRVA (unsigned char)~_BV(4) /* PSC Outputs xA Reset Value */ +-#define FUSE_PSCRB (unsigned char)~_BV(5) /* PSC Reset Behavior */ +-#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_BODLEVEL1) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x94 +-#define SIGNATURE_2 0x84 +- +- +-#endif /* _AVR_ATmega16M1_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom16m1.h 2183 2010-09-21 05:37:46Z aboyapati $ */ ++ ++/* avr/iom16m1.h - definitions for ATmega16M1 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom16m1.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATmega16M1_H_ ++#define _AVR_ATmega16M1_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++#define PINC7 7 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++#define DDC7 7 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC3 3 ++#define PORTC4 4 ++#define PORTC5 5 ++#define PORTC6 6 ++#define PORTC7 7 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE0 0 ++#define PINE1 1 ++#define PINE2 2 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE0 0 ++#define DDE1 1 ++#define DDE2 2 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE0 0 ++#define PORTE1 1 ++#define PORTE2 2 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define GPIOR1 _SFR_IO8(0x19) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x1A) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++#define PCIF3 3 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++#define INT3 3 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++#define EEAR9 1 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR10 0 ++#define PSRSYNC 0 ++#define ICPSEL1 6 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define OCR0A _SFR_IO8(0x27) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define OCR0B _SFR_IO8(0x28) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define PLLCSR _SFR_IO8(0x29) ++#define PLOCK 0 ++#define PLLE 1 ++#define PLLF 2 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define ACSR _SFR_IO8(0x30) ++#define AC0O 0 ++#define AC1O 1 ++#define AC2O 2 ++#define AC3O 3 ++#define AC0IF 4 ++#define AC1IF 5 ++#define AC2IF 6 ++#define AC3IF 7 ++ ++#define DWDR _SFR_IO8(0x31) ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define SPIPS 7 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRLIN 1 ++#define PRSPI 2 ++#define PRTIM0 3 ++#define PRTIM1 4 ++#define PRPSC 5 ++#define PRCAN 6 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++#define PCIE3 3 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++#define PCMSK0 _SFR_MEM8(0x6A) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6B) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK2 _SFR_MEM8(0x6C) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define PCMSK3 _SFR_MEM8(0x6D) ++#define PCINT24 0 ++#define PCINT25 1 ++#define PCINT26 2 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define AMP0CSR _SFR_MEM8(0x75) ++#define AMP0TS0 0 ++#define AMP0TS1 1 ++#define AMP0TS2 2 ++#define AMPCMP0 3 ++#define AMP0G0 4 ++#define AMP0G1 5 ++#define AMP0IS 6 ++#define AMP0EN 7 ++ ++#define AMP1CSR _SFR_MEM8(0x76) ++#define AMP1TS0 0 ++#define AMP1TS1 1 ++#define AMP1TS2 2 ++#define AMPCMP1 3 ++#define AMP1G0 4 ++#define AMP1G1 5 ++#define AMP1IS 6 ++#define AMP1EN 7 ++ ++#define AMP2CSR _SFR_MEM8(0x77) ++#define AMP2TS0 0 ++#define AMP2TS1 1 ++#define AMP2TS2 2 ++#define AMPCMP2 3 ++#define AMP2G0 4 ++#define AMP2G1 5 ++#define AMP2IS 6 ++#define AMP2EN 7 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_MEM8(0x79) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ADTS3 3 ++#define AREFEN 5 ++#define ISRCEN 6 ++#define ADHSM 7 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define ADC8D 0 ++#define ADC9D 1 ++#define ADC10D 2 ++#define AMP0ND 3 ++#define AMP0PD 4 ++#define ACMP0D 5 ++#define AMP2PD 6 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define DACON _SFR_MEM8(0x90) ++#define DAEN 0 ++#define DAOE 1 ++#define DALA 2 ++#define DATS0 4 ++#define DATS1 5 ++#define DATS2 6 ++#define DAATE 7 ++ ++#define DAC _SFR_MEM16(0x91) ++ ++#define DACL _SFR_MEM8(0x91) ++#define DACL0 0 ++#define DACL1 1 ++#define DACL2 2 ++#define DACL3 3 ++#define DACL4 4 ++#define DACL5 5 ++#define DACL6 6 ++#define DACL7 7 ++ ++#define DACH _SFR_MEM8(0x92) ++#define DACH0 0 ++#define DACH1 1 ++#define DACH2 2 ++#define DACH3 3 ++#define DACH4 4 ++#define DACH5 5 ++#define DACH6 6 ++#define DACH7 7 ++ ++#define AC0CON _SFR_MEM8(0x94) ++#define AC0M0 0 ++#define AC0M1 1 ++#define AC0M2 2 ++#define ACCKSEL 3 ++#define AC0IS0 4 ++#define AC0IS1 5 ++#define AC0IE 6 ++#define AC0EN 7 ++ ++#define AC1CON _SFR_MEM8(0x95) ++#define AC1M0 0 ++#define AC1M1 1 ++#define AC1M2 2 ++#define AC1ICE 3 ++#define AC1IS0 4 ++#define AC1IS1 5 ++#define AC1IE 6 ++#define AC1EN 7 ++ ++#define AC2CON _SFR_MEM8(0x96) ++#define AC2M0 0 ++#define AC2M1 1 ++#define AC2M2 2 ++#define AC2IS0 4 ++#define AC2IS1 5 ++#define AC2IE 6 ++#define AC2EN 7 ++ ++#define AC3CON _SFR_MEM8(0x97) ++#define AC3M0 0 ++#define AC3M1 1 ++#define AC3M2 2 ++#define AC3IS0 4 ++#define AC3IS1 5 ++#define AC3IE 6 ++#define AC3EN 7 ++ ++#define POCR0SA _SFR_MEM16(0xA0) ++ ++#define POCR0SAL _SFR_MEM8(0xA0) ++#define POCR0SA_0 0 ++#define POCR0SA_1 1 ++#define POCR0SA_2 2 ++#define POCR0SA_3 3 ++#define POCR0SA_4 4 ++#define POCR0SA_5 5 ++#define POCR0SA_6 6 ++#define POCR0SA_7 7 ++ ++#define POCR0SAH _SFR_MEM8(0xA1) ++#define POCR0SA_8 0 ++#define POCR0SA_9 1 ++#define POCR0SA_10 2 ++#define POCR0SA_11 3 ++ ++#define POCR0RA _SFR_MEM16(0xA2) ++ ++#define POCR0RAL _SFR_MEM8(0xA2) ++#define POCR0RA_0 0 ++#define POCR0RA_1 1 ++#define POCR0RA_2 2 ++#define POCR0RA_3 3 ++#define POCR0RA_4 4 ++#define POCR0RA_5 5 ++#define POCR0RA_6 6 ++#define POCR0RA_7 7 ++ ++#define POCR0RAH _SFR_MEM8(0xA3) ++#define POCR0RA_8 0 ++#define POCR0RA_9 1 ++#define POCR0RA_10 2 ++#define POCR0RA_11 3 ++ ++#define POCR0SB _SFR_MEM16(0xA4) ++ ++#define POCR0SBL _SFR_MEM8(0xA4) ++#define POCR0SB_0 0 ++#define POCR0SB_1 1 ++#define POCR0SB_2 2 ++#define POCR0SB_3 3 ++#define POCR0SB_4 4 ++#define POCR0SB_5 5 ++#define POCR0SB_6 6 ++#define POCR0SB_7 7 ++ ++#define POCR0SBH _SFR_MEM8(0xA5) ++#define POCR0SB_8 0 ++#define POCR0SB_9 1 ++#define POCR0SB_10 2 ++#define POCR0SB_11 3 ++ ++#define POCR1SA _SFR_MEM16(0xA6) ++ ++#define POCR1SAL _SFR_MEM8(0xA6) ++#define POCR1SA_0 0 ++#define POCR1SA_1 1 ++#define POCR1SA_2 2 ++#define POCR1SA_3 3 ++#define POCR1SA_4 4 ++#define POCR1SA_5 5 ++#define POCR1SA_6 6 ++#define POCR1SA_7 7 ++ ++#define POCR1SAH _SFR_MEM8(0xA7) ++#define POCR1SA_8 0 ++#define POCR1SA_9 1 ++#define POCR1SA_10 2 ++#define POCR1SA_11 3 ++ ++#define POCR1RA _SFR_MEM16(0xA8) ++ ++#define POCR1RAL _SFR_MEM8(0xA8) ++#define POCR1RA_0 0 ++#define POCR1RA_1 1 ++#define POCR1RA_2 2 ++#define POCR1RA_3 3 ++#define POCR1RA_4 4 ++#define POCR1RA_5 5 ++#define POCR1RA_6 6 ++#define POCR1RA_7 7 ++ ++#define POCR1RAH _SFR_MEM8(0xA9) ++#define POCR1RA_8 0 ++#define POCR1RA_9 1 ++#define POCR1RA_10 2 ++#define POCR1RA_11 3 ++ ++#define POCR1SB _SFR_MEM16(0xAA) ++ ++#define POCR1SBL _SFR_MEM8(0xAA) ++#define POCR1SB_0 0 ++#define POCR1SB_1 1 ++#define POCR1SB_2 2 ++#define POCR1SB_3 3 ++#define POCR1SB_4 4 ++#define POCR1SB_5 5 ++#define POCR1SB_6 6 ++#define POCR1SB_7 7 ++ ++#define POCR1SBH _SFR_MEM8(0xAB) ++#define POCR1SB_8 0 ++#define POCR1SB_9 1 ++#define POCR1SB_10 2 ++#define POCR1SB_11 3 ++ ++#define POCR2SA _SFR_MEM16(0xAC) ++ ++#define POCR2SAL _SFR_MEM8(0xAC) ++#define POCR2SA_0 0 ++#define POCR2SA_1 1 ++#define POCR2SA_2 2 ++#define POCR2SA_3 3 ++#define POCR2SA_4 4 ++#define POCR2SA_5 5 ++#define POCR2SA_6 6 ++#define POCR2SA_7 7 ++ ++#define POCR2SAH _SFR_MEM8(0xAD) ++#define POCR2SA_8 0 ++#define POCR2SA_9 1 ++#define POCR2SA_10 2 ++#define POCR2SA_11 3 ++ ++#define POCR2RA _SFR_MEM16(0xAE) ++ ++#define POCR2RAL _SFR_MEM8(0xAE) ++#define POCR2RA_0 0 ++#define POCR2RA_1 1 ++#define POCR2RA_2 2 ++#define POCR2RA_3 3 ++#define POCR2RA_4 4 ++#define POCR2RA_5 5 ++#define POCR2RA_6 6 ++#define POCR2RA_7 7 ++ ++#define POCR2RAH _SFR_MEM8(0xAF) ++#define POCR2RA_8 0 ++#define POCR2RA_9 1 ++#define POCR2RA_10 2 ++#define POCR2RA_11 3 ++ ++#define POCR2SB _SFR_MEM16(0xB0) ++ ++#define POCR2SBL _SFR_MEM8(0xB0) ++#define POCR2SB_0 0 ++#define POCR2SB_1 1 ++#define POCR2SB_2 2 ++#define POCR2SB_3 3 ++#define POCR2SB_4 4 ++#define POCR2SB_5 5 ++#define POCR2SB_6 6 ++#define POCR2SB_7 7 ++ ++#define POCR2SBH _SFR_MEM8(0xB1) ++#define POCR2SB_8 0 ++#define POCR2SB_9 1 ++#define POCR2SB_10 2 ++#define POCR2SB_11 3 ++ ++#define POCR_RB _SFR_MEM16(0xB2) ++ ++#define POCR_RBL _SFR_MEM8(0xB2) ++#define POCR_RB_0 0 ++#define POCR_RB_1 1 ++#define POCR_RB_2 2 ++#define POCR_RB_3 3 ++#define POCR_RB_4 4 ++#define POCR_RB_5 5 ++#define POCR_RB_6 6 ++#define POCR_RB_7 7 ++ ++#define POCR_RBH _SFR_MEM8(0xB3) ++#define POCR_RB_8 0 ++#define POCR_RB_9 1 ++#define POCR_RB_10 2 ++#define POCR_RB_11 3 ++ ++#define PSYNC _SFR_MEM8(0xB4) ++#define PSYNC00 0 ++#define PSYNC01 1 ++#define PSYNC10 2 ++#define PSYNC11 3 ++#define PSYNC20 4 ++#define PSYNC21 5 ++ ++#define PCNF _SFR_MEM8(0xB5) ++#define POPA 2 ++#define POPB 3 ++#define PMODE 4 ++#define PULOCK 5 ++ ++#define POC _SFR_MEM8(0xB6) ++#define POEN0A 0 ++#define POEN0B 1 ++#define POEN1A 2 ++#define POEN1B 3 ++#define POEN2A 4 ++#define POEN2B 5 ++ ++#define PCTL _SFR_MEM8(0xB7) ++#define PRUN 0 ++#define PCCYC 1 ++#define PCLKSEL 5 ++#define PPRE0 6 ++#define PPRE1 7 ++ ++#define PMIC0 _SFR_MEM8(0xB8) ++#define PRFM00 0 ++#define PRFM01 1 ++#define PRFM02 2 ++#define PAOC0 3 ++#define PFLTE0 4 ++#define PELEV0 5 ++#define PISEL0 6 ++#define POVEN0 7 ++ ++#define PMIC1 _SFR_MEM8(0xB9) ++#define PRFM10 0 ++#define PRFM11 1 ++#define PRFM12 2 ++#define PAOC1 3 ++#define PFLTE1 4 ++#define PELEV1 5 ++#define PISEL1 6 ++#define POVEN1 7 ++ ++#define PMIC2 _SFR_MEM8(0xBA) ++#define PRFM20 0 ++#define PRFM21 1 ++#define PRFM22 2 ++#define PAOC2 3 ++#define PFLTE2 4 ++#define PELEV2 5 ++#define PISEL2 6 ++#define POVEN2 7 ++ ++#define PIM _SFR_MEM8(0xBB) ++#define PEOPE 0 ++#define PEVE0 1 ++#define PEVE1 2 ++#define PEVE2 3 ++ ++#define PIFR _SFR_MEM8(0xBC) ++#define PEOP 0 ++#define PEV0 1 ++#define PEV1 2 ++#define PEV2 3 ++ ++#define LINCR _SFR_MEM8(0xC8) ++#define LCMD0 0 ++#define LCMD1 1 ++#define LCMD2 2 ++#define LENA 3 ++#define LCONF0 4 ++#define LCONF1 5 ++#define LIN13 6 ++#define LSWRES 7 ++ ++#define LINSIR _SFR_MEM8(0xC9) ++#define LRXOK 0 ++#define LTXOK 1 ++#define LIDOK 2 ++#define LERR 3 ++#define LBUSY 4 ++#define LIDST0 5 ++#define LIDST1 6 ++#define LIDST2 7 ++ ++#define LINENIR _SFR_MEM8(0xCA) ++#define LENRXOK 0 ++#define LENTXOK 1 ++#define LENIDOK 2 ++#define LENERR 3 ++ ++#define LINERR _SFR_MEM8(0xCB) ++#define LBERR 0 ++#define LCERR 1 ++#define LPERR 2 ++#define LSERR 3 ++#define LFERR 4 ++#define LOVERR 5 ++#define LTOERR 6 ++#define LABORT 7 ++ ++#define LINBTR _SFR_MEM8(0xCC) ++#define LBT0 0 ++#define LBT1 1 ++#define LBT2 2 ++#define LBT3 3 ++#define LBT4 4 ++#define LBT5 5 ++#define LDISR 7 ++ ++#define LINBRR _SFR_MEM16(0xCD) ++ ++#define LINBRRL _SFR_MEM8(0xCD) ++#define LDIV0 0 ++#define LDIV1 1 ++#define LDIV2 2 ++#define LDIV3 3 ++#define LDIV4 4 ++#define LDIV5 5 ++#define LDIV6 6 ++#define LDIV7 7 ++ ++#define LINBRRH _SFR_MEM8(0xCE) ++#define LDIV8 0 ++#define LDIV9 1 ++#define LDIV10 2 ++#define LDIV11 3 ++ ++#define LINDLR _SFR_MEM8(0xCF) ++#define LRXDL0 0 ++#define LRXDL1 1 ++#define LRXDL2 2 ++#define LRXDL3 3 ++#define LTXDL0 4 ++#define LTXDL1 5 ++#define LTXDL2 6 ++#define LTXDL3 7 ++ ++#define LINIDR _SFR_MEM8(0xD0) ++#define LID0 0 ++#define LID1 1 ++#define LID2 2 ++#define LID3 3 ++#define LID4 4 ++#define LID5 5 ++#define LP0 6 ++#define LP1 7 ++ ++#define LINSEL _SFR_MEM8(0xD1) ++#define LINDX0 0 ++#define LINDX1 1 ++#define LINDX2 2 ++#define LAINC 3 ++ ++#define LINDAT _SFR_MEM8(0xD2) ++#define LDATA0 0 ++#define LDATA1 1 ++#define LDATA2 2 ++#define LDATA3 3 ++#define LDATA4 4 ++#define LDATA5 5 ++#define LDATA6 6 ++#define LDATA7 7 ++ ++#define CANGCON _SFR_MEM8(0xD8) ++#define SWRES 0 ++#define ENASTB 1 ++#define TEST 2 ++#define LISTEN 3 ++#define SYNTTC 4 ++#define TTC 5 ++#define OVRQ 6 ++#define ABRQ 7 ++ ++#define CANGSTA _SFR_MEM8(0xD9) ++#define ERRP 0 ++#define BOFF 1 ++#define ENFG 2 ++#define RXBSY 3 ++#define TXBSY 4 ++#define OVFG 6 ++ ++#define CANGIT _SFR_MEM8(0xDA) ++#define AERG 0 ++#define FERG 1 ++#define CERG 2 ++#define SERG 3 ++#define BXOK 4 ++#define OVRTIM 5 ++#define BOFFIT 6 ++#define CANIT 7 ++ ++#define CANGIE _SFR_MEM8(0xDB) ++#define ENOVRT 0 ++#define ENERG 1 ++#define ENBX 2 ++#define ENERR 3 ++#define ENTX 4 ++#define ENRX 5 ++#define ENBOFF 6 ++#define ENIT 7 ++ ++#define CANEN2 _SFR_MEM8(0xDC) ++#define ENMOB0 0 ++#define ENMOB1 1 ++#define ENMOB2 2 ++#define ENMOB3 3 ++#define ENMOB4 4 ++#define ENMOB5 5 ++ ++#define CANEN1 _SFR_MEM8(0xDD) ++ ++#define CANIE2 _SFR_MEM8(0xDE) ++#define IEMOB0 0 ++#define IEMOB1 1 ++#define IEMOB2 2 ++#define IEMOB3 3 ++#define IEMOB4 4 ++#define IEMOB5 5 ++ ++#define CANIE1 _SFR_MEM8(0xDF) ++ ++/* RegDef: CAN Status Interrupt MOb Register*/ ++#define CANSIT _SFR_MEM16(0xE0) ++ ++#define CANSIT2 _SFR_MEM8(0xE0) ++#define SIT0 0 ++#define SIT1 1 ++#define SIT2 2 ++#define SIT3 3 ++#define SIT4 4 ++#define SIT5 5 ++ ++#define CANSIT1 _SFR_MEM8(0xE1) ++ ++#define CANBT1 _SFR_MEM8(0xE2) ++#define BRP0 1 ++#define BRP1 2 ++#define BRP2 3 ++#define BRP3 4 ++#define BRP4 5 ++#define BRP5 6 ++ ++#define CANBT2 _SFR_MEM8(0xE3) ++#define PRS0 1 ++#define PRS1 2 ++#define PRS2 3 ++#define SJW0 5 ++#define SJW1 6 ++ ++#define CANBT3 _SFR_MEM8(0xE4) ++#define SMP 0 ++#define PHS10 1 ++#define PHS11 2 ++#define PHS12 3 ++#define PHS20 4 ++#define PHS21 5 ++#define PHS22 6 ++ ++#define CANTCON _SFR_MEM8(0xE5) ++#define TPRSC0 0 ++#define TPRSC1 1 ++#define TPRSC2 2 ++#define TPRSC3 3 ++#define TPRSC4 4 ++#define TPRSC5 5 ++#define TPRSC6 6 ++#define TPRSC7 7 ++ ++#define CANTIM _SFR_MEM16(0xE6) ++ ++#define CANTIML _SFR_MEM8(0xE6) ++#define CANTIM0 0 ++#define CANTIM1 1 ++#define CANTIM2 2 ++#define CANTIM3 3 ++#define CANTIM4 4 ++#define CANTIM5 5 ++#define CANTIM6 6 ++#define CANTIM7 7 ++ ++#define CANTIMH _SFR_MEM8(0xE7) ++#define CANTIM8 0 ++#define CANTIM9 1 ++#define CANTIM10 2 ++#define CANTIM11 3 ++#define CANTIM12 4 ++#define CANTIM13 5 ++#define CANTIM14 6 ++#define CANTIM15 7 ++ ++#define CANTTC _SFR_MEM16(0xE8) ++ ++#define CANTTCL _SFR_MEM8(0xE8) ++#define TIMTCC0 0 ++#define TIMTCC1 1 ++#define TIMTCC2 2 ++#define TIMTCC3 3 ++#define TIMTCC4 4 ++#define TIMTCC5 5 ++#define TIMTCC6 6 ++#define TIMTCC7 7 ++ ++#define CANTTCH _SFR_MEM8(0xE9) ++#define TIMTCC8 0 ++#define TIMTCC9 1 ++#define TIMTCC10 2 ++#define TIMTCC11 3 ++#define TIMTCC12 4 ++#define TIMTCC13 5 ++#define TIMTCC14 6 ++#define TIMTCC15 7 ++ ++#define CANTEC _SFR_MEM8(0xEA) ++#define TEC0 0 ++#define TEC1 1 ++#define TEC2 2 ++#define TEC3 3 ++#define TEC4 4 ++#define TEC5 5 ++#define TEC6 6 ++#define TEC7 7 ++ ++#define CANREC _SFR_MEM8(0xEB) ++#define REC0 0 ++#define REC1 1 ++#define REC2 2 ++#define REC3 3 ++#define REC4 4 ++#define REC5 5 ++#define REC6 6 ++#define REC7 7 ++ ++#define CANHPMOB _SFR_MEM8(0xEC) ++#define CGP0 0 ++#define CGP1 1 ++#define CGP2 2 ++#define CGP3 3 ++#define HPMOB0 4 ++#define HPMOB1 5 ++#define HPMOB2 6 ++#define HPMOB3 7 ++ ++#define CANPAGE _SFR_MEM8(0xED) ++#define INDX0 0 ++#define INDX1 1 ++#define INDX2 2 ++#define AINC 3 ++#define MOBNB0 4 ++#define MOBNB1 5 ++#define MOBNB2 6 ++#define MOBNB3 7 ++ ++#define CANSTMOB _SFR_MEM8(0xEE) ++#define AERR 0 ++#define FERR 1 ++#define CERR 2 ++#define SERR 3 ++#define BERR 4 ++#define RXOK 5 ++#define TXOK 6 ++#define DLCW 7 ++ ++#define CANCDMOB _SFR_MEM8(0xEF) ++#define DLC0 0 ++#define DLC1 1 ++#define DLC2 2 ++#define DLC3 3 ++#define IDE 4 ++#define RPLV 5 ++#define CONMOB0 6 ++#define CONMOB1 7 ++ ++/* RegDef: CAN Identifier Tag Registers*/ ++#define CANIDT _SFR_MEM32(0xF0) ++ ++#define CANIDT4 _SFR_MEM8(0xF0) ++#define RB0TAG 0 ++#define RB1TAG 1 ++#define RTRTAG 2 ++#define IDT0 3 ++#define IDT1 4 ++#define IDT2 5 ++#define IDT3 6 ++#define IDT4 7 ++ ++#define CANIDT3 _SFR_MEM8(0xF1) ++#define IDT5 0 ++#define IDT6 1 ++#define IDT7 2 ++#define IDT8 3 ++#define IDT9 4 ++#define IDT10 5 ++#define IDT11 6 ++#define IDT12 7 ++ ++#define CANIDT2 _SFR_MEM8(0xF2) ++#define IDT13 0 ++#define IDT14 1 ++#define IDT15 2 ++#define IDT16 3 ++#define IDT17 4 ++#define IDT18 5 ++#define IDT19 6 ++#define IDT20 7 ++ ++#define CANIDT1 _SFR_MEM8(0xF3) ++#define IDT21 0 ++#define IDT22 1 ++#define IDT23 2 ++#define IDT24 3 ++#define IDT25 4 ++#define IDT26 5 ++#define IDT27 6 ++#define IDT28 7 ++ ++/* RegDef: CAN Identifier Mask Registers */ ++#define CANIDM _SFR_MEM32(0xF4) ++ ++#define CANIDM4 _SFR_MEM8(0xF4) ++#define IDEMSK 0 ++#define RTRMSK 2 ++#define IDMSK0 3 ++#define IDMSK1 4 ++#define IDMSK2 5 ++#define IDMSK3 6 ++#define IDMSK4 7 ++ ++#define CANIDM3 _SFR_MEM8(0xF5) ++#define IDMSK5 0 ++#define IDMSK6 1 ++#define IDMSK7 2 ++#define IDMSK8 3 ++#define IDMSK9 4 ++#define IDMSK10 5 ++#define IDMSK11 6 ++#define IDMSK12 7 ++ ++#define CANIDM2 _SFR_MEM8(0xF6) ++#define IDMSK13 0 ++#define IDMSK14 1 ++#define IDMSK15 2 ++#define IDMSK16 3 ++#define IDMSK17 4 ++#define IDMSK18 5 ++#define IDMSK19 6 ++#define IDMSK20 7 ++ ++#define CANIDM1 _SFR_MEM8(0xF7) ++#define IDMSK21 0 ++#define IDMSK22 1 ++#define IDMSK23 2 ++#define IDMSK24 3 ++#define IDMSK25 4 ++#define IDMSK26 5 ++#define IDMSK27 6 ++#define IDMSK28 7 ++ ++#define CANSTM _SFR_MEM16(0xF8) ++ ++#define CANSTML _SFR_MEM8(0xF8) ++#define TIMSTM0 0 ++#define TIMSTM1 1 ++#define TIMSTM2 2 ++#define TIMSTM3 3 ++#define TIMSTM4 4 ++#define TIMSTM5 5 ++#define TIMSTM6 6 ++#define TIMSTM7 7 ++ ++#define CANSTMH _SFR_MEM8(0xF9) ++#define TIMSTM8 0 ++#define TIMSTM9 1 ++#define TIMSTM10 2 ++#define TIMSTM11 3 ++#define TIMSTM12 4 ++#define TIMSTM13 5 ++#define TIMSTM14 6 ++#define TIMSTM15 7 ++ ++#define CANMSG _SFR_MEM8(0xFA) ++#define MSG0 0 ++#define MSG1 1 ++#define MSG2 2 ++#define MSG3 3 ++#define MSG4 4 ++#define MSG5 5 ++#define MSG6 6 ++#define MSG7 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define ANACOMP0_vect_num 1 ++#define ANACOMP0_vect _VECTOR(1) /* Analog Comparator 0 */ ++#define ANACOMP1_vect_num 2 ++#define ANACOMP1_vect _VECTOR(2) /* Analog Comparator 1 */ ++#define ANACOMP2_vect_num 3 ++#define ANACOMP2_vect _VECTOR(3) /* Analog Comparator 2 */ ++#define ANACOMP3_vect_num 4 ++#define ANACOMP3_vect _VECTOR(4) /* Analog Comparator 3 */ ++#define PSC_FAULT_vect_num 5 ++#define PSC_FAULT_vect _VECTOR(5) /* PSC Fault */ ++#define PSC_EC_vect_num 6 ++#define PSC_EC_vect _VECTOR(6) /* PSC End of Cycle */ ++#define INT0_vect_num 7 ++#define INT0_vect _VECTOR(7) /* External Interrupt Request 0 */ ++#define INT1_vect_num 8 ++#define INT1_vect _VECTOR(8) /* External Interrupt Request 1 */ ++#define INT2_vect_num 9 ++#define INT2_vect _VECTOR(9) /* External Interrupt Request 2 */ ++#define INT3_vect_num 10 ++#define INT3_vect _VECTOR(10) /* External Interrupt Request 3 */ ++#define TIMER1_CAPT_vect_num 11 ++#define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */ ++#define TIMER1_COMPA_vect_num 12 ++#define TIMER1_COMPA_vect _VECTOR(12) /* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPB_vect_num 13 ++#define TIMER1_COMPB_vect _VECTOR(13) /* Timer/Counter1 Compare Match B */ ++#define TIMER1_OVF_vect_num 14 ++#define TIMER1_OVF_vect _VECTOR(14) /* Timer1/Counter1 Overflow */ ++#define TIMER0_COMPA_vect_num 15 ++#define TIMER0_COMPA_vect _VECTOR(15) /* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPB_vect_num 16 ++#define TIMER0_COMPB_vect _VECTOR(16) /* Timer/Counter0 Compare Match B */ ++#define TIMER0_OVF_vect_num 17 ++#define TIMER0_OVF_vect _VECTOR(17) /* Timer/Counter0 Overflow */ ++#define CAN_INT_vect_num 18 ++#define CAN_INT_vect _VECTOR(18) /* CAN MOB, Burst, General Errors */ ++#define CAN_TOVF_vect_num 19 ++#define CAN_TOVF_vect _VECTOR(19) /* CAN Timer Overflow */ ++#define LIN_TC_vect_num 20 ++#define LIN_TC_vect _VECTOR(20) /* LIN Transfer Complete */ ++#define LIN_ERR_vect_num 21 ++#define LIN_ERR_vect _VECTOR(21) /* LIN Error */ ++#define PCINT0_vect_num 22 ++#define PCINT0_vect _VECTOR(22) /* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect_num 23 ++#define PCINT1_vect _VECTOR(23) /* Pin Change Interrupt Request 1 */ ++#define PCINT2_vect_num 24 ++#define PCINT2_vect _VECTOR(24) /* Pin Change Interrupt Request 2 */ ++#define PCINT3_vect_num 25 ++#define PCINT3_vect _VECTOR(25) /* Pin Change Interrupt Request 3 */ ++#define SPI_STC_vect_num 26 ++#define SPI_STC_vect _VECTOR(26) /* SPI Serial Transfer Complete */ ++#define ADC_vect_num 27 ++#define ADC_vect _VECTOR(27) /* ADC Conversion Complete */ ++#define WDT_vect_num 28 ++#define WDT_vect _VECTOR(28) /* Watchdog Time-Out Interrupt */ ++#define EE_READY_vect_num 29 ++#define EE_READY_vect _VECTOR(29) /* EEPROM Ready */ ++#define SPM_READY_vect_num 30 ++#define SPM_READY_vect _VECTOR(30) /* Store Program Memory Read */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (31 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (128) ++#define RAMSTART (0x0100) ++#define RAMSIZE (1024) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (0x0) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x1FF) ++#define E2PAGESIZE (4) ++#define FLASHEND (0x3FFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector Trigger Level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector Trigger Level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector Trigger Level */ ++#define FUSE_PSCRVB (unsigned char)~_BV(3) /* PSC Outputs xB Reset Value */ ++#define FUSE_PSCRVA (unsigned char)~_BV(4) /* PSC Outputs xA Reset Value */ ++#define FUSE_PSCRB (unsigned char)~_BV(5) /* PSC Reset Behavior */ ++#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_BODLEVEL1) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x84 ++ ++ ++#endif /* _AVR_ATmega16M1_H_ */ ++ +diff --git a/include/avr/iom16u2.h b/include/avr/iom16u2.h +index 09a2cbc..2a6f4b4 100644 +--- a/include/avr/iom16u2.h ++++ b/include/avr/iom16u2.h +@@ -1,980 +1,986 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom16u2.h 2240 2011-05-09 22:18:18Z arcanum $ */ +- +-/* avr/iom16u2.h - definitions for ATmega16U2 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom16u2.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATmega16U2_H_ +-#define _AVR_ATmega16U2_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +-#define PINC7 7 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +-#define DDC7 7 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC4 4 +-#define PORTC5 5 +-#define PORTC6 6 +-#define PORTC7 7 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define OCF1C 3 +-#define ICF1 5 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +-#define PCIF1 1 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +-#define INTF2 2 +-#define INTF3 3 +-#define INTF4 4 +-#define INTF5 5 +-#define INTF6 6 +-#define INTF7 7 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +-#define INT2 2 +-#define INT3 3 +-#define INT4 4 +-#define INT5 5 +-#define INT6 6 +-#define INT7 7 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +-#define EEAR9 1 +-#define EEAR10 2 +-#define EEAR11 3 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSRSYNC 0 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define OCR0A _SFR_IO8(0x27) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define OCR0B _SFR_IO8(0x28) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define PLLCSR _SFR_IO8(0x29) +-#define PLOCK 0 +-#define PLLE 1 +-#define PLLP0 2 +-#define PLLP1 3 +-#define PLLP2 4 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define DWDR _SFR_IO8(0x31) +-#define DWDR0 0 +-#define DWDR1 1 +-#define DWDR2 2 +-#define DWDR3 3 +-#define DWDR4 4 +-#define DWDR5 5 +-#define DWDR6 6 +-#define DWDR7 7 +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +-#define USBRF 5 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define SIGRD 5 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define EIND _SFR_IO8(0x3C) +-#define EIND0 0 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define WDTCKD _SFR_MEM8(0x62) +-#define WCLKD0 0 +-#define WCLKD1 1 +-#define WDEWIE 2 +-#define WDEWIF 3 +- +-#define REGCR _SFR_MEM8(0x63) +-#define REGDIS 0 +- +-#define PRR0 _SFR_MEM8(0x64) +-#define PRSPI 2 +-#define PRTIM1 3 +-#define PRTIM0 5 +- +-#define PRR1 _SFR_MEM8(0x65) +-#define PRUSART1 0 +-#define PRUSB 7 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +-#define PCIE1 1 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define ISC20 4 +-#define ISC21 5 +-#define ISC30 6 +-#define ISC31 7 +- +-#define EICRB _SFR_MEM8(0x6A) +-#define ISC40 0 +-#define ISC41 1 +-#define ISC50 2 +-#define ISC51 3 +-#define ISC60 4 +-#define ISC61 5 +-#define ISC70 6 +-#define ISC71 7 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define OCIE1C 3 +-#define ICIE1 5 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1C0 2 +-#define COM1C1 3 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1C 5 +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define OCR1C _SFR_MEM16(0x8C) +- +-#define OCR1CL _SFR_MEM8(0x8C) +-#define OCR1CL0 0 +-#define OCR1CL1 1 +-#define OCR1CL2 2 +-#define OCR1CL3 3 +-#define OCR1CL4 4 +-#define OCR1CL5 5 +-#define OCR1CL6 6 +-#define OCR1CL7 7 +- +-#define OCR1CH _SFR_MEM8(0x8D) +-#define OCR1CH0 0 +-#define OCR1CH1 1 +-#define OCR1CH2 2 +-#define OCR1CH3 3 +-#define OCR1CH4 4 +-#define OCR1CH5 5 +-#define OCR1CH6 6 +-#define OCR1CH7 7 +- +-#define UCSR1A _SFR_MEM8(0xC8) +-#define MPCM1 0 +-#define U2X1 1 +-#define UPE1 2 +-#define DOR1 3 +-#define FE1 4 +-#define UDRE1 5 +-#define TXC1 6 +-#define RXC1 7 +- +-#define UCSR1B _SFR_MEM8(0xC9) +-#define TXB81 0 +-#define RXB81 1 +-#define UCSZ12 2 +-#define TXEN1 3 +-#define RXEN1 4 +-#define UDRIE1 5 +-#define TXCIE1 6 +-#define RXCIE1 7 +- +-#define UCSR1C _SFR_MEM8(0xCA) +-#define UCPOL1 0 +-#define UCSZ10 1 +-#define UCSZ11 2 +-#define USBS1 3 +-#define UPM10 4 +-#define UPM11 5 +-#define UMSEL10 6 +-#define UMSEL11 7 +- +-#define UCSR1D _SFR_MEM8(0xCB) +-#define RTSEN 0 +-#define CTSEN 1 +- +-#define UBRR1 _SFR_MEM16(0xCC) +- +-#define UBRR1L _SFR_MEM8(0xCC) +-#define UBRR1_0 0 +-#define UBRR1_1 1 +-#define UBRR1_2 2 +-#define UBRR1_3 3 +-#define UBRR1_4 4 +-#define UBRR1_5 5 +-#define UBRR1_6 6 +-#define UBRR1_7 7 +- +-#define UBRR1H _SFR_MEM8(0xCD) +-#define UBRR1_8 0 +-#define UBRR1_9 1 +-#define UBRR1_10 2 +-#define UBRR1_11 3 +- +-#define UDR1 _SFR_MEM8(0xCE) +-#define UDR1_0 0 +-#define UDR1_1 1 +-#define UDR1_2 2 +-#define UDR1_3 3 +-#define UDR1_4 4 +-#define UDR1_5 5 +-#define UDR1_6 6 +-#define UDR1_7 7 +- +-#define CLKSEL0 _SFR_MEM8(0xD0) +-#define CLKS 0 +-#define EXTE 2 +-#define RCE 3 +-#define EXSUT0 4 +-#define EXSUT1 5 +-#define RCSUT0 6 +-#define RCSUT1 7 +- +-#define CLKSEL1 _SFR_MEM8(0xD1) +-#define EXCKSEL0 0 +-#define EXCKSEL1 1 +-#define EXCKSEL2 2 +-#define EXCKSEL3 3 +-#define RCCKSEL0 4 +-#define RCCKSEL1 5 +-#define RCCKSEL2 6 +-#define RCCKSEL3 7 +- +-#define CLKSTA _SFR_MEM8(0xD2) +-#define EXTON 0 +-#define RCON 1 +- +-#define USBCON _SFR_MEM8(0xD8) +-#define FRZCLK 5 +-#define USBE 7 +- +-#define UDCON _SFR_MEM8(0xE0) +-#define DETACH 0 +-#define RMWKUP 1 +-#define RSTCPU 2 +- +-#define UDINT _SFR_MEM8(0xE1) +-#define SUSPI 0 +-#define SOFI 2 +-#define EORSTI 3 +-#define WAKEUPI 4 +-#define EORSMI 5 +-#define UPRSMI 6 +- +-#define UDIEN _SFR_MEM8(0xE2) +-#define SUSPE 0 +-#define SOFE 2 +-#define EORSTE 3 +-#define WAKEUPE 4 +-#define EORSME 5 +-#define UPRSME 6 +- +-#define UDADDR _SFR_MEM8(0xE3) +-#define UADD0 0 +-#define UADD1 1 +-#define UADD2 2 +-#define UADD3 3 +-#define UADD4 4 +-#define UADD5 5 +-#define UADD6 6 +-#define ADDEN 7 +- +-#define UDFNUM _SFR_MEM16(0xE4) +- +-#define UDFNUML _SFR_MEM8(0xE4) +-#define FNUM0 0 +-#define FNUM1 1 +-#define FNUM2 2 +-#define FNUM3 3 +-#define FNUM4 4 +-#define FNUM5 5 +-#define FNUM6 6 +-#define FNUM7 7 +- +-#define UDFNUMH _SFR_MEM8(0xE5) +-#define FNUM8 0 +-#define FNUM9 1 +-#define FNUM10 2 +- +-#define UDMFN _SFR_MEM8(0xE6) +-#define FNCERR 4 +- +-#define UEINTX _SFR_MEM8(0xE8) +-#define TXINI 0 +-#define STALLEDI 1 +-#define RXOUTI 2 +-#define RXSTPI 3 +-#define NAKOUTI 4 +-#define RWAL 5 +-#define NAKINI 6 +-#define FIFOCON 7 +- +-#define UENUM _SFR_MEM8(0xE9) +-#define EPNUM0 0 +-#define EPNUM1 1 +-#define EPNUM2 2 +- +-#define UERST _SFR_MEM8(0xEA) +-#define EPRST0 0 +-#define EPRST1 1 +-#define EPRST2 2 +-#define EPRST3 3 +-#define EPRST4 4 +- +-#define UECONX _SFR_MEM8(0xEB) +-#define EPEN 0 +-#define RSTDT 3 +-#define STALLRQC 4 +-#define STALLRQ 5 +- +-#define UECFG0X _SFR_MEM8(0xEC) +-#define EPDIR 0 +-#define EPTYPE0 6 +-#define EPTYPE1 7 +- +-#define UECFG1X _SFR_MEM8(0xED) +-#define ALLOC 1 +-#define EPBK0 2 +-#define EPBK1 3 +-#define EPSIZE0 4 +-#define EPSIZE1 5 +-#define EPSIZE2 6 +- +-#define UESTA0X _SFR_MEM8(0xEE) +-#define NBUSYBK0 0 +-#define NBUSYBK1 1 +-#define DTSEQ0 2 +-#define DTSEQ1 3 +-#define UNDERFI 5 +-#define OVERFI 6 +-#define CFGOK 7 +- +-#define UESTA1X _SFR_MEM8(0xEF) +-#define CURRBK0 0 +-#define CURRBK1 1 +-#define CTRLDIR 2 +- +-#define UEIENX _SFR_MEM8(0xF0) +-#define TXINE 0 +-#define STALLEDE 1 +-#define RXOUTE 2 +-#define RXSTPE 3 +-#define NAKOUTE 4 +-#define NAKINE 6 +-#define FLERRE 7 +- +-#define UEDATX _SFR_MEM8(0xF1) +-#define DAT0 0 +-#define DAT1 1 +-#define DAT2 2 +-#define DAT3 3 +-#define DAT4 4 +-#define DAT5 5 +-#define DAT6 6 +-#define DAT7 7 +- +-#define UEBCLX _SFR_MEM8(0xF2) +-#define BYCT0 0 +-#define BYCT1 1 +-#define BYCT2 2 +-#define BYCT3 3 +-#define BYCT4 4 +-#define BYCT5 5 +-#define BYCT6 6 +-#define BYCT7 7 +- +-#define UEINT _SFR_MEM8(0xF4) +-#define EPINT0 0 +-#define EPINT1 1 +-#define EPINT2 2 +-#define EPINT3 3 +-#define EPINT4 4 +- +-#define PS2CON _SFR_MEM8(0xFA) +-#define PS2EN 0 +- +-#define UPOE _SFR_MEM8(0xFB) +-#define DMI 0 +-#define DPI 1 +-#define DATAI 2 +-#define SCKI 3 +-#define UPDRV0 4 +-#define UPDRV1 5 +-#define UPWE0 6 +-#define UPWE1 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ +-#define INT2_vect_num 3 +-#define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ +-#define INT3_vect_num 4 +-#define INT3_vect _VECTOR(4) /* External Interrupt Request 3 */ +-#define INT4_vect_num 5 +-#define INT4_vect _VECTOR(5) /* External Interrupt Request 4 */ +-#define INT5_vect_num 6 +-#define INT5_vect _VECTOR(6) /* External Interrupt Request 5 */ +-#define INT6_vect_num 7 +-#define INT6_vect _VECTOR(7) /* External Interrupt Request 6 */ +-#define INT7_vect_num 8 +-#define INT7_vect _VECTOR(8) /* External Interrupt Request 7 */ +-#define PCINT0_vect_num 9 +-#define PCINT0_vect _VECTOR(9) /* Pin Change Interrupt Request 0 */ +-#define PCINT1_vect_num 10 +-#define PCINT1_vect _VECTOR(10) /* Pin Change Interrupt Request 1 */ +-#define USB_GEN_vect_num 11 +-#define USB_GEN_vect _VECTOR(11) /* USB General Interrupt Request */ +-#define USB_COM_vect_num 12 +-#define USB_COM_vect _VECTOR(12) /* USB Endpoint/Pipe Interrupt Communication Request */ +-#define WDT_vect_num 13 +-#define WDT_vect _VECTOR(13) /* Watchdog Time-out Interrupt */ +-#define TIMER1_CAPT_vect_num 14 +-#define TIMER1_CAPT_vect _VECTOR(14) /* Timer/Counter2 Capture Event */ +-#define TIMER1_COMPA_vect_num 15 +-#define TIMER1_COMPA_vect _VECTOR(15) /* Timer/Counter2 Compare Match B */ +-#define TIMER0_COMPA_vect_num 19 +-#define TIMER0_COMPA_vect _VECTOR(19) /* Timer/Counter0 Compare Match A */ +-#define TIMER0_COMPB_vect_num 20 +-#define TIMER0_COMPB_vect _VECTOR(20) /* Timer/Counter0 Compare Match B */ +-#define TIMER0_OVF_vect_num 21 +-#define TIMER0_OVF_vect _VECTOR(21) /* Timer/Counter0 Overflow */ +-#define SPI_STC_vect_num 22 +-#define SPI_STC_vect _VECTOR(22) /* SPI Serial Transfer Complete */ +-#define USART1_RX_vect_num 23 +-#define USART1_RX_vect _VECTOR(23) /* USART1, Rx Complete */ +-#define USART1_UDRE_vect_num 24 +-#define USART1_UDRE_vect _VECTOR(24) /* USART1 Data register Empty */ +-#define USART1_TX_vect_num 25 +-#define USART1_TX_vect _VECTOR(25) /* USART1, Tx Complete */ +-#define ANALOG_COMP_vect_num 26 +-#define ANALOG_COMP_vect _VECTOR(26) /* Analog Comparator */ +-#define EE_READY_vect_num 27 +-#define EE_READY_vect _VECTOR(27) /* EEPROM Ready */ +-#define SPM_READY_vect_num 28 +-#define SPM_READY_vect _VECTOR(28) /* Store Program Memory Read */ +-#define TIMER1_COMPB_vect_num 16 +-#define TIMER1_COMPB_vect _VECTOR(16) /* Timer/Counter2 Compare Match B */ +-#define TIMER1_COMPC_vect_num 17 +-#define TIMER1_COMPC_vect _VECTOR(17) /* Timer/Counter2 Compare Match C */ +-#define TIMER1_OVF_vect_num 18 +-#define TIMER1_OVF_vect _VECTOR(18) /* Timer/Counter1 Overflow */ +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (29 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (128) +-#define RAMSTART (0x100) +-#define RAMSIZE (512) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x1FF) +-#define E2PAGESIZE (4) +-#define FLASHEND (0x3FFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(6) /* External Reset Disable */ +-#define FUSE_DWEN (unsigned char)~_BV(7) /* dwbugWIRE Enable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define FUSE_HWBE (unsigned char)~_BV(3) /* Hardware Boot Enable */ +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x94 +-#define SIGNATURE_2 0x89 +- +- +-/* Device Pin Definitions */ +-#endif /* _AVR_ATmega16U2_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom16u2.h 2240 2011-05-09 22:18:18Z arcanum $ */ ++ ++/* avr/iom16u2.h - definitions for ATmega16U2 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom16u2.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATmega16U2_H_ ++#define _AVR_ATmega16U2_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++#define PINC7 7 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++#define DDC7 7 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC4 4 ++#define PORTC5 5 ++#define PORTC6 6 ++#define PORTC7 7 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define OCF1C 3 ++#define ICF1 5 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++#define INTF4 4 ++#define INTF5 5 ++#define INTF6 6 ++#define INTF7 7 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++#define INT3 3 ++#define INT4 4 ++#define INT5 5 ++#define INT6 6 ++#define INT7 7 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++#define EEAR9 1 ++#define EEAR10 2 ++#define EEAR11 3 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define OCR0A _SFR_IO8(0x27) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define OCR0B _SFR_IO8(0x28) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define PLLCSR _SFR_IO8(0x29) ++#define PLOCK 0 ++#define PLLE 1 ++#define PLLP0 2 ++#define PLLP1 3 ++#define PLLP2 4 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define DWDR _SFR_IO8(0x31) ++#define DWDR0 0 ++#define DWDR1 1 ++#define DWDR2 2 ++#define DWDR3 3 ++#define DWDR4 4 ++#define DWDR5 5 ++#define DWDR6 6 ++#define DWDR7 7 ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define USBRF 5 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define EIND _SFR_IO8(0x3C) ++#define EIND0 0 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define WDTCKD _SFR_MEM8(0x62) ++#define WCLKD0 0 ++#define WCLKD1 1 ++#define WDEWIE 2 ++#define WDEWIF 3 ++ ++#define REGCR _SFR_MEM8(0x63) ++#define REGDIS 0 ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRTIM0 5 ++ ++#define PRR1 _SFR_MEM8(0x65) ++#define PRUSART1 0 ++#define PRUSB 7 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++#define EICRB _SFR_MEM8(0x6A) ++#define ISC40 0 ++#define ISC41 1 ++#define ISC50 2 ++#define ISC51 3 ++#define ISC60 4 ++#define ISC61 5 ++#define ISC70 6 ++#define ISC71 7 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define OCIE1C 3 ++#define ICIE1 5 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++#define AIN2D 2 ++#define AIN3D 3 ++#define AIN4D 4 ++#define AIN5D 5 ++#define AIN6D 6 ++#define AIN7D 7 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1C0 2 ++#define COM1C1 3 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1C 5 ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define OCR1C _SFR_MEM16(0x8C) ++ ++#define OCR1CL _SFR_MEM8(0x8C) ++#define OCR1CL0 0 ++#define OCR1CL1 1 ++#define OCR1CL2 2 ++#define OCR1CL3 3 ++#define OCR1CL4 4 ++#define OCR1CL5 5 ++#define OCR1CL6 6 ++#define OCR1CL7 7 ++ ++#define OCR1CH _SFR_MEM8(0x8D) ++#define OCR1CH0 0 ++#define OCR1CH1 1 ++#define OCR1CH2 2 ++#define OCR1CH3 3 ++#define OCR1CH4 4 ++#define OCR1CH5 5 ++#define OCR1CH6 6 ++#define OCR1CH7 7 ++ ++#define UCSR1A _SFR_MEM8(0xC8) ++#define MPCM1 0 ++#define U2X1 1 ++#define UPE1 2 ++#define DOR1 3 ++#define FE1 4 ++#define UDRE1 5 ++#define TXC1 6 ++#define RXC1 7 ++ ++#define UCSR1B _SFR_MEM8(0xC9) ++#define TXB81 0 ++#define RXB81 1 ++#define UCSZ12 2 ++#define TXEN1 3 ++#define RXEN1 4 ++#define UDRIE1 5 ++#define TXCIE1 6 ++#define RXCIE1 7 ++ ++#define UCSR1C _SFR_MEM8(0xCA) ++#define UCPOL1 0 ++#define UCSZ10 1 ++#define UCSZ11 2 ++#define USBS1 3 ++#define UPM10 4 ++#define UPM11 5 ++#define UMSEL10 6 ++#define UMSEL11 7 ++ ++#define UCSR1D _SFR_MEM8(0xCB) ++#define RTSEN 0 ++#define CTSEN 1 ++ ++#define UBRR1 _SFR_MEM16(0xCC) ++ ++#define UBRR1L _SFR_MEM8(0xCC) ++#define UBRR1_0 0 ++#define UBRR1_1 1 ++#define UBRR1_2 2 ++#define UBRR1_3 3 ++#define UBRR1_4 4 ++#define UBRR1_5 5 ++#define UBRR1_6 6 ++#define UBRR1_7 7 ++ ++#define UBRR1H _SFR_MEM8(0xCD) ++#define UBRR1_8 0 ++#define UBRR1_9 1 ++#define UBRR1_10 2 ++#define UBRR1_11 3 ++ ++#define UDR1 _SFR_MEM8(0xCE) ++#define UDR1_0 0 ++#define UDR1_1 1 ++#define UDR1_2 2 ++#define UDR1_3 3 ++#define UDR1_4 4 ++#define UDR1_5 5 ++#define UDR1_6 6 ++#define UDR1_7 7 ++ ++#define CLKSEL0 _SFR_MEM8(0xD0) ++#define CLKS 0 ++#define EXTE 2 ++#define RCE 3 ++#define EXSUT0 4 ++#define EXSUT1 5 ++#define RCSUT0 6 ++#define RCSUT1 7 ++ ++#define CLKSEL1 _SFR_MEM8(0xD1) ++#define EXCKSEL0 0 ++#define EXCKSEL1 1 ++#define EXCKSEL2 2 ++#define EXCKSEL3 3 ++#define RCCKSEL0 4 ++#define RCCKSEL1 5 ++#define RCCKSEL2 6 ++#define RCCKSEL3 7 ++ ++#define CLKSTA _SFR_MEM8(0xD2) ++#define EXTON 0 ++#define RCON 1 ++ ++#define USBCON _SFR_MEM8(0xD8) ++#define FRZCLK 5 ++#define USBE 7 ++ ++#define UDCON _SFR_MEM8(0xE0) ++#define DETACH 0 ++#define RMWKUP 1 ++#define RSTCPU 2 ++ ++#define UDINT _SFR_MEM8(0xE1) ++#define SUSPI 0 ++#define SOFI 2 ++#define EORSTI 3 ++#define WAKEUPI 4 ++#define EORSMI 5 ++#define UPRSMI 6 ++ ++#define UDIEN _SFR_MEM8(0xE2) ++#define SUSPE 0 ++#define SOFE 2 ++#define EORSTE 3 ++#define WAKEUPE 4 ++#define EORSME 5 ++#define UPRSME 6 ++ ++#define UDADDR _SFR_MEM8(0xE3) ++#define UADD0 0 ++#define UADD1 1 ++#define UADD2 2 ++#define UADD3 3 ++#define UADD4 4 ++#define UADD5 5 ++#define UADD6 6 ++#define ADDEN 7 ++ ++#define UDFNUM _SFR_MEM16(0xE4) ++ ++#define UDFNUML _SFR_MEM8(0xE4) ++#define FNUM0 0 ++#define FNUM1 1 ++#define FNUM2 2 ++#define FNUM3 3 ++#define FNUM4 4 ++#define FNUM5 5 ++#define FNUM6 6 ++#define FNUM7 7 ++ ++#define UDFNUMH _SFR_MEM8(0xE5) ++#define FNUM8 0 ++#define FNUM9 1 ++#define FNUM10 2 ++ ++#define UDMFN _SFR_MEM8(0xE6) ++#define FNCERR 4 ++ ++#define UEINTX _SFR_MEM8(0xE8) ++#define TXINI 0 ++#define STALLEDI 1 ++#define RXOUTI 2 ++#define RXSTPI 3 ++#define NAKOUTI 4 ++#define RWAL 5 ++#define NAKINI 6 ++#define FIFOCON 7 ++ ++#define UENUM _SFR_MEM8(0xE9) ++#define EPNUM0 0 ++#define EPNUM1 1 ++#define EPNUM2 2 ++ ++#define UERST _SFR_MEM8(0xEA) ++#define EPRST0 0 ++#define EPRST1 1 ++#define EPRST2 2 ++#define EPRST3 3 ++#define EPRST4 4 ++ ++#define UECONX _SFR_MEM8(0xEB) ++#define EPEN 0 ++#define RSTDT 3 ++#define STALLRQC 4 ++#define STALLRQ 5 ++ ++#define UECFG0X _SFR_MEM8(0xEC) ++#define EPDIR 0 ++#define EPTYPE0 6 ++#define EPTYPE1 7 ++ ++#define UECFG1X _SFR_MEM8(0xED) ++#define ALLOC 1 ++#define EPBK0 2 ++#define EPBK1 3 ++#define EPSIZE0 4 ++#define EPSIZE1 5 ++#define EPSIZE2 6 ++ ++#define UESTA0X _SFR_MEM8(0xEE) ++#define NBUSYBK0 0 ++#define NBUSYBK1 1 ++#define DTSEQ0 2 ++#define DTSEQ1 3 ++#define UNDERFI 5 ++#define OVERFI 6 ++#define CFGOK 7 ++ ++#define UESTA1X _SFR_MEM8(0xEF) ++#define CURRBK0 0 ++#define CURRBK1 1 ++#define CTRLDIR 2 ++ ++#define UEIENX _SFR_MEM8(0xF0) ++#define TXINE 0 ++#define STALLEDE 1 ++#define RXOUTE 2 ++#define RXSTPE 3 ++#define NAKOUTE 4 ++#define NAKINE 6 ++#define FLERRE 7 ++ ++#define UEDATX _SFR_MEM8(0xF1) ++#define DAT0 0 ++#define DAT1 1 ++#define DAT2 2 ++#define DAT3 3 ++#define DAT4 4 ++#define DAT5 5 ++#define DAT6 6 ++#define DAT7 7 ++ ++#define UEBCLX _SFR_MEM8(0xF2) ++#define BYCT0 0 ++#define BYCT1 1 ++#define BYCT2 2 ++#define BYCT3 3 ++#define BYCT4 4 ++#define BYCT5 5 ++#define BYCT6 6 ++#define BYCT7 7 ++ ++#define UEINT _SFR_MEM8(0xF4) ++#define EPINT0 0 ++#define EPINT1 1 ++#define EPINT2 2 ++#define EPINT3 3 ++#define EPINT4 4 ++ ++#define PS2CON _SFR_MEM8(0xFA) ++#define PS2EN 0 ++ ++#define UPOE _SFR_MEM8(0xFB) ++#define DMI 0 ++#define DPI 1 ++#define DATAI 2 ++#define SCKI 3 ++#define UPDRV0 4 ++#define UPDRV1 5 ++#define UPWE0 6 ++#define UPWE1 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ ++#define INT2_vect_num 3 ++#define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ ++#define INT3_vect_num 4 ++#define INT3_vect _VECTOR(4) /* External Interrupt Request 3 */ ++#define INT4_vect_num 5 ++#define INT4_vect _VECTOR(5) /* External Interrupt Request 4 */ ++#define INT5_vect_num 6 ++#define INT5_vect _VECTOR(6) /* External Interrupt Request 5 */ ++#define INT6_vect_num 7 ++#define INT6_vect _VECTOR(7) /* External Interrupt Request 6 */ ++#define INT7_vect_num 8 ++#define INT7_vect _VECTOR(8) /* External Interrupt Request 7 */ ++#define PCINT0_vect_num 9 ++#define PCINT0_vect _VECTOR(9) /* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect_num 10 ++#define PCINT1_vect _VECTOR(10) /* Pin Change Interrupt Request 1 */ ++#define USB_GEN_vect_num 11 ++#define USB_GEN_vect _VECTOR(11) /* USB General Interrupt Request */ ++#define USB_COM_vect_num 12 ++#define USB_COM_vect _VECTOR(12) /* USB Endpoint/Pipe Interrupt Communication Request */ ++#define WDT_vect_num 13 ++#define WDT_vect _VECTOR(13) /* Watchdog Time-out Interrupt */ ++#define TIMER1_CAPT_vect_num 14 ++#define TIMER1_CAPT_vect _VECTOR(14) /* Timer/Counter2 Capture Event */ ++#define TIMER1_COMPA_vect_num 15 ++#define TIMER1_COMPA_vect _VECTOR(15) /* Timer/Counter2 Compare Match B */ ++#define TIMER0_COMPA_vect_num 19 ++#define TIMER0_COMPA_vect _VECTOR(19) /* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPB_vect_num 20 ++#define TIMER0_COMPB_vect _VECTOR(20) /* Timer/Counter0 Compare Match B */ ++#define TIMER0_OVF_vect_num 21 ++#define TIMER0_OVF_vect _VECTOR(21) /* Timer/Counter0 Overflow */ ++#define SPI_STC_vect_num 22 ++#define SPI_STC_vect _VECTOR(22) /* SPI Serial Transfer Complete */ ++#define USART1_RX_vect_num 23 ++#define USART1_RX_vect _VECTOR(23) /* USART1, Rx Complete */ ++#define USART1_UDRE_vect_num 24 ++#define USART1_UDRE_vect _VECTOR(24) /* USART1 Data register Empty */ ++#define USART1_TX_vect_num 25 ++#define USART1_TX_vect _VECTOR(25) /* USART1, Tx Complete */ ++#define ANALOG_COMP_vect_num 26 ++#define ANALOG_COMP_vect _VECTOR(26) /* Analog Comparator */ ++#define EE_READY_vect_num 27 ++#define EE_READY_vect _VECTOR(27) /* EEPROM Ready */ ++#define SPM_READY_vect_num 28 ++#define SPM_READY_vect _VECTOR(28) /* Store Program Memory Read */ ++#define TIMER1_COMPB_vect_num 16 ++#define TIMER1_COMPB_vect _VECTOR(16) /* Timer/Counter2 Compare Match B */ ++#define TIMER1_COMPC_vect_num 17 ++#define TIMER1_COMPC_vect _VECTOR(17) /* Timer/Counter2 Compare Match C */ ++#define TIMER1_OVF_vect_num 18 ++#define TIMER1_OVF_vect _VECTOR(18) /* Timer/Counter1 Overflow */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (29 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (128) ++#define RAMSTART (0x100) ++#define RAMSIZE (512) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x1FF) ++#define E2PAGESIZE (4) ++#define FLASHEND (0x3FFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(6) /* External Reset Disable */ ++#define FUSE_DWEN (unsigned char)~_BV(7) /* dwbugWIRE Enable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define FUSE_HWBE (unsigned char)~_BV(3) /* Hardware Boot Enable */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x89 ++ ++ ++/* Device Pin Definitions */ ++#endif /* _AVR_ATmega16U2_H_ */ ++ +diff --git a/include/avr/iom16u4.h b/include/avr/iom16u4.h +index 7fafdee..e28d9fe 100644 +--- a/include/avr/iom16u4.h ++++ b/include/avr/iom16u4.h +@@ -1,1357 +1,1402 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom16u4.h 2185 2010-09-22 07:06:35Z aboyapati $ */ +- +-/* avr/iom16u4.h - definitions for ATmega16U4 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom16u4.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATmega16U4_H_ +-#define _AVR_ATmega16U4_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC6 6 +-#define PINC7 7 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC6 6 +-#define DDC7 7 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC6 6 +-#define PORTC7 7 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define PINE _SFR_IO8(0x0C) +-#define PINE2 2 +-#define PINE6 6 +- +-#define DDRE _SFR_IO8(0x0D) +-#define DDE2 2 +-#define DDE6 6 +- +-#define PORTE _SFR_IO8(0x0E) +-#define PORTE2 2 +-#define PORTE6 6 +- +-#define PINF _SFR_IO8(0x0F) +-#define PINF0 0 +-#define PINF1 1 +-#define PINF4 4 +-#define PINF5 5 +-#define PINF6 6 +-#define PINF7 7 +- +-#define DDRF _SFR_IO8(0x10) +-#define DDF0 0 +-#define DDF1 1 +-#define DDF4 4 +-#define DDF5 5 +-#define DDF6 6 +-#define DDF7 7 +- +-#define PORTF _SFR_IO8(0x11) +-#define PORTF0 0 +-#define PORTF1 1 +-#define PORTF4 4 +-#define PORTF5 5 +-#define PORTF6 6 +-#define PORTF7 7 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define OCF1C 3 +-#define ICF1 5 +- +-#define TIFR2 _SFR_IO8(0x17) +- +-#define TIFR3 _SFR_IO8(0x18) +-#define TOV3 0 +-#define OCF3A 1 +-#define OCF3B 2 +-#define OCF3C 3 +-#define ICF3 5 +- +-#define TIFR4 _SFR_IO8(0x19) +-#define TOV4 2 +-#define OCF4B 5 +-#define OCF4A 6 +-#define OCF4D 7 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +-#define INTF2 2 +-#define INTF3 3 +-#define INTF4 4 +-#define INTF5 5 +-#define INTF6 6 +-#define INTF7 7 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +-#define INT2 2 +-#define INT3 3 +-#define INT4 4 +-#define INT5 5 +-#define INT6 6 +-#define INT7 7 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +-#define EEAR9 1 +-#define EEAR10 2 +-#define EEAR11 3 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSRSYNC 0 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define OCR0A _SFR_IO8(0x27) +-#define OCROA_0 0 +-#define OCROA_1 1 +-#define OCROA_2 2 +-#define OCROA_3 3 +-#define OCROA_4 4 +-#define OCROA_5 5 +-#define OCROA_6 6 +-#define OCROA_7 7 +- +-#define OCR0B _SFR_IO8(0x28) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define PLLCSR _SFR_IO8(0x29) +-#define PLOCK 0 +-#define PLLE 1 +-#define PINDIV 4 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define OCDR _SFR_IO8(0x31) +-#define OCDR0 0 +-#define OCDR1 1 +-#define OCDR2 2 +-#define OCDR3 3 +-#define OCDR4 4 +-#define OCDR5 5 +-#define OCDR6 6 +-#define OCDR7 7 +- +-#define PLLFRQ _SFR_IO8(0x32) +-#define PDIV0 0 +-#define PDIV1 1 +-#define PDIV2 2 +-#define PDIV3 3 +-#define PLLTM0 4 +-#define PLLTM1 5 +-#define PLLUSB 6 +-#define PINMUX 7 +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +-#define JTRF 4 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define JTD 7 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define SIGRD 5 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define RAMPZ _SFR_IO8(0x3B) +-#define RAMPZ0 0 +- +-#define EIND _SFR_IO8(0x3C) +-#define EIND0 0 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define PRR0 _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM1 3 +-#define PRTIM0 5 +-#define PRTIM2 6 +-#define PRTWI 7 +- +-#define PRR1 _SFR_MEM8(0x65) +-#define PRUSART1 0 +-#define PRTIM3 3 +-#define PRUSB 7 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define RCCTRL _SFR_MEM8(0x67) +-#define RCFREQ 0 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define ISC20 4 +-#define ISC21 5 +-#define ISC30 6 +-#define ISC31 7 +- +-#define EICRB _SFR_MEM8(0x6A) +-#define ISC40 0 +-#define ISC41 1 +-#define ISC50 2 +-#define ISC51 3 +-#define ISC60 4 +-#define ISC61 5 +-#define ISC70 6 +-#define ISC71 7 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define OCIE1C 3 +-#define ICIE1 5 +- +-#define TIMSK3 _SFR_MEM8(0x71) +-#define TOIE3 0 +-#define OCIE3A 1 +-#define OCIE3B 2 +-#define OCIE3C 3 +-#define ICIE3 5 +- +-#define TIMSK4 _SFR_MEM8(0x72) +-#define TOIE4 2 +-#define OCIE4B 5 +-#define OCIE4A 6 +-#define OCIE4D 7 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +- +-#define ADCL _SFR_MEM8(0x78) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_MEM8(0x79) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ADTS3 3 +-#define MUX5 5 +-#define ACME 6 +-#define ADHSM 7 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define DIDR2 _SFR_MEM8(0x7D) +-#define ADC8D 0 +-#define ADC9D 1 +-#define ADC10D 2 +-#define ADC11D 3 +-#define ADC12D 4 +-#define ADC13D 5 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1C0 2 +-#define COM1C1 3 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1C 5 +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define OCR1C _SFR_MEM16(0x8C) +- +-#define OCR1CL _SFR_MEM8(0x8C) +-#define OCR1CL0 0 +-#define OCR1CL1 1 +-#define OCR1CL2 2 +-#define OCR1CL3 3 +-#define OCR1CL4 4 +-#define OCR1CL5 5 +-#define OCR1CL6 6 +-#define OCR1CL7 7 +- +-#define OCR1CH _SFR_MEM8(0x8D) +-#define OCR1CH0 0 +-#define OCR1CH1 1 +-#define OCR1CH2 2 +-#define OCR1CH3 3 +-#define OCR1CH4 4 +-#define OCR1CH5 5 +-#define OCR1CH6 6 +-#define OCR1CH7 7 +- +-#define TCCR3A _SFR_MEM8(0x90) +-#define WGM30 0 +-#define WGM31 1 +-#define COM3C0 2 +-#define COM3C1 3 +-#define COM3B0 4 +-#define COM3B1 5 +-#define COM3A0 6 +-#define COM3A1 7 +- +-#define TCCR3B _SFR_MEM8(0x91) +-#define CS30 0 +-#define CS31 1 +-#define CS32 2 +-#define WGM32 3 +-#define WGM33 4 +-#define ICES3 6 +-#define ICNC3 7 +- +-#define TCCR3C _SFR_MEM8(0x92) +-#define FOC3C 5 +-#define FOC3B 6 +-#define FOC3A 7 +- +-#define TCNT3 _SFR_MEM16(0x94) +- +-#define TCNT3L _SFR_MEM8(0x94) +-#define TCNT3L0 0 +-#define TCNT3L1 1 +-#define TCNT3L2 2 +-#define TCNT3L3 3 +-#define TCNT3L4 4 +-#define TCNT3L5 5 +-#define TCNT3L6 6 +-#define TCNT3L7 7 +- +-#define TCNT3H _SFR_MEM8(0x95) +-#define TCNT3H0 0 +-#define TCNT3H1 1 +-#define TCNT3H2 2 +-#define TCNT3H3 3 +-#define TCNT3H4 4 +-#define TCNT3H5 5 +-#define TCNT3H6 6 +-#define TCNT3H7 7 +- +-#define ICR3 _SFR_MEM16(0x96) +- +-#define ICR3L _SFR_MEM8(0x96) +-#define ICR3L0 0 +-#define ICR3L1 1 +-#define ICR3L2 2 +-#define ICR3L3 3 +-#define ICR3L4 4 +-#define ICR3L5 5 +-#define ICR3L6 6 +-#define ICR3L7 7 +- +-#define ICR3H _SFR_MEM8(0x97) +-#define ICR3H0 0 +-#define ICR3H1 1 +-#define ICR3H2 2 +-#define ICR3H3 3 +-#define ICR3H4 4 +-#define ICR3H5 5 +-#define ICR3H6 6 +-#define ICR3H7 7 +- +-#define OCR3A _SFR_MEM16(0x98) +- +-#define OCR3AL _SFR_MEM8(0x98) +-#define OCR3AL0 0 +-#define OCR3AL1 1 +-#define OCR3AL2 2 +-#define OCR3AL3 3 +-#define OCR3AL4 4 +-#define OCR3AL5 5 +-#define OCR3AL6 6 +-#define OCR3AL7 7 +- +-#define OCR3AH _SFR_MEM8(0x99) +-#define OCR3AH0 0 +-#define OCR3AH1 1 +-#define OCR3AH2 2 +-#define OCR3AH3 3 +-#define OCR3AH4 4 +-#define OCR3AH5 5 +-#define OCR3AH6 6 +-#define OCR3AH7 7 +- +-#define OCR3B _SFR_MEM16(0x9A) +- +-#define OCR3BL _SFR_MEM8(0x9A) +-#define OCR3BL0 0 +-#define OCR3BL1 1 +-#define OCR3BL2 2 +-#define OCR3BL3 3 +-#define OCR3BL4 4 +-#define OCR3BL5 5 +-#define OCR3BL6 6 +-#define OCR3BL7 7 +- +-#define OCR3BH _SFR_MEM8(0x9B) +-#define OCR3BH0 0 +-#define OCR3BH1 1 +-#define OCR3BH2 2 +-#define OCR3BH3 3 +-#define OCR3BH4 4 +-#define OCR3BH5 5 +-#define OCR3BH6 6 +-#define OCR3BH7 7 +- +-#define OCR3C _SFR_MEM16(0x9C) +- +-#define OCR3CL _SFR_MEM8(0x9C) +-#define OCR3CL0 0 +-#define OCR3CL1 1 +-#define OCR3CL2 2 +-#define OCR3CL3 3 +-#define OCR3CL4 4 +-#define OCR3CL5 5 +-#define OCR3CL6 6 +-#define OCR3CL7 7 +- +-#define OCR3CH _SFR_MEM8(0x9D) +-#define OCR3CH0 0 +-#define OCR3CH1 1 +-#define OCR3CH2 2 +-#define OCR3CH3 3 +-#define OCR3CH4 4 +-#define OCR3CH5 5 +-#define OCR3CH6 6 +-#define OCR3CH7 7 +- +-#define TCNT4 _SFR_MEM8(0xBE) +-#define TC40 0 +-#define TC41 1 +-#define TC42 2 +-#define TC43 3 +-#define TC44 4 +-#define TC45 5 +-#define TC46 6 +-#define TC47 7 +- +-#define TC4H _SFR_MEM8(0xBF) +-#define TC48 0 +-#define TC49 1 +-#define TC410 2 +- +-#define TCCR4A _SFR_MEM8(0xC0) +-#define PWM4B 0 +-#define PWM4A 1 +-#define FOC4B 2 +-#define FOC4A 3 +-#define COM4B0 4 +-#define COM4B1 5 +-#define COM4A0 6 +-#define COM4A1 7 +- +-#define TCCR4B _SFR_MEM8(0xC1) +-#define CS40 0 +-#define CS41 1 +-#define CS42 2 +-#define CS43 3 +-#define DTPS40 4 +-#define DTPS41 5 +-#define PSR4 6 +-#define PWM4X 7 +- +-#define TCCR4C _SFR_MEM8(0xC2) +-#define PWM4D 0 +-#define FOC4D 1 +-#define COM4D0 2 +-#define COM4D1 3 +-#define COM4B0S 4 +-#define COM4B1S 5 +-#define COM4A0S 6 +-#define COM4A1S 7 +- +-#define TCCR4D _SFR_MEM8(0xC3) +-#define WGM40 0 +-#define WGM41 1 +-#define FPF4 2 +-#define FPAC4 3 +-#define FPES4 4 +-#define FPNC4 5 +-#define FPEN4 6 +-#define FPIE4 7 +- +-#define TCCR4E _SFR_MEM8(0xC4) +-#define OC4OE0 0 +-#define OC4OE1 1 +-#define OC4OE2 2 +-#define OC4OE3 3 +-#define OC4OE4 4 +-#define OC4OE5 5 +-#define ENHC4 6 +-#define TLOCK4 7 +- +-#define CLKSEL0 _SFR_MEM8(0xC5) +-#define CLKS 0 +-#define EXTE 2 +-#define RCE 3 +-#define EXSUT0 4 +-#define EXSUT1 5 +-#define RCSUT0 6 +-#define RCSUT1 7 +- +-#define CLKSEL1 _SFR_MEM8(0xC6) +-#define EXCKSEL0 0 +-#define EXCKSEL1 1 +-#define EXCKSEL2 2 +-#define EXCKSEL3 3 +-#define RCCKSEL0 4 +-#define RCCKSEL1 5 +-#define RCCKSEL2 6 +-#define RCCKSEL3 7 +- +-#define CLKSTA _SFR_MEM8(0xC7) +-#define EXTON 0 +-#define RCON 1 +- +-#define UCSR1A _SFR_MEM8(0xC8) +-#define MPCM1 0 +-#define U2X1 1 +-#define UPE1 2 +-#define DOR1 3 +-#define FE1 4 +-#define UDRE1 5 +-#define TXC1 6 +-#define RXC1 7 +- +-#define UCSR1B _SFR_MEM8(0xC9) +-#define TXB81 0 +-#define RXB81 1 +-#define UCSZ12 2 +-#define TXEN1 3 +-#define RXEN1 4 +-#define UDRIE1 5 +-#define TXCIE1 6 +-#define RXCIE1 7 +- +-#define UCSR1C _SFR_MEM8(0xCA) +-#define UCPOL1 0 +-#define UCSZ10 1 +-#define UCSZ11 2 +-#define USBS1 3 +-#define UPM10 4 +-#define UPM11 5 +-#define UMSEL10 6 +-#define UMSEL11 7 +- +-#define UBRR1 _SFR_MEM16(0xCC) +- +-#define UBRR1L _SFR_MEM8(0xCC) +- +-#define UBRR1H _SFR_MEM8(0xCD) +- +-#define UDR1 _SFR_MEM8(0xCE) +-#define UDR1_0 0 +-#define UDR1_1 1 +-#define UDR1_2 2 +-#define UDR1_3 3 +-#define UDR1_4 4 +-#define UDR1_5 5 +-#define UDR1_6 6 +-#define UDR1_7 7 +- +-#define OCR4A _SFR_MEM8(0xCF) +-#define OCR4A0 0 +-#define OCR4A1 1 +-#define OCR4A2 2 +-#define OCR4A3 3 +-#define OCR4A4 4 +-#define OCR4A5 5 +-#define OCR4A6 6 +-#define OCR4A7 7 +- +-#define OCR4B _SFR_MEM8(0xD0) +-#define OCR4B0 0 +-#define OCR4B1 1 +-#define OCR4B2 2 +-#define OCR4B3 3 +-#define OCR4B4 4 +-#define OCR4B5 5 +-#define OCR4B6 6 +-#define OCR4B7 7 +- +-#define OCR4C _SFR_MEM8(0xD1) +-#define OCR4C0 0 +-#define OCR4C1 1 +-#define OCR4C2 2 +-#define OCR4C3 3 +-#define OCR4C4 4 +-#define OCR4C5 5 +-#define OCR4C6 6 +-#define OCR4C7 7 +- +-#define OCR4D _SFR_MEM8(0xD2) +-#define OCR4D0 0 +-#define OCR4D1 1 +-#define OCR4D2 2 +-#define OCR4D3 3 +-#define OCR4D4 4 +-#define OCR4D5 5 +-#define OCR4D6 6 +-#define OCR4D7 7 +- +-#define DT4 _SFR_MEM8(0xD4) +-#define DT4L0 0 +-#define DT4L1 1 +-#define DT4L2 2 +-#define DT4L3 3 +-#define DT4L4 4 +-#define DT4L5 5 +-#define DT4L6 6 +-#define DT4L7 7 +- +-#define UHWCON _SFR_MEM8(0xD7) +-#define UVREGE 0 +- +-#define USBCON _SFR_MEM8(0xD8) +-#define VBUSTE 0 +-#define OTGPADE 4 +-#define FRZCLK 5 +-#define USBE 7 +- +-#define USBSTA _SFR_MEM8(0xD9) +-#define VBUS 0 +-#define SPEED 3 +- +-#define USBINT _SFR_MEM8(0xDA) +-#define VBUSTI 0 +- +-#define UDCON _SFR_MEM8(0xE0) +-#define DETACH 0 +-#define RMWKUP 1 +-#define LSM 2 +-#define RSTCPU 3 +- +-#define UDINT _SFR_MEM8(0xE1) +-#define SUSPI 0 +-#define SOFI 2 +-#define EORSTI 3 +-#define WAKEUPI 4 +-#define EORSMI 5 +-#define UPRSMI 6 +- +-#define UDIEN _SFR_MEM8(0xE2) +-#define SUSPE 0 +-#define SOFE 2 +-#define EORSTE 3 +-#define WAKEUPE 4 +-#define EORSME 5 +-#define UPRSME 6 +- +-#define UDADDR _SFR_MEM8(0xE3) +-#define UADD0 0 +-#define UADD1 1 +-#define UADD2 2 +-#define UADD3 3 +-#define UADD4 4 +-#define UADD5 5 +-#define UADD6 6 +-#define ADDEN 7 +- +-#define UDFNUM _SFR_MEM16(0xE4) +- +-#define UDFNUML _SFR_MEM8(0xE4) +-#define FNUM0 0 +-#define FNUM1 1 +-#define FNUM2 2 +-#define FNUM3 3 +-#define FNUM4 4 +-#define FNUM5 5 +-#define FNUM6 6 +-#define FNUM7 7 +- +-#define UDFNUMH _SFR_MEM8(0xE5) +-#define FNUM8 0 +-#define FNUM9 1 +-#define FNUM10 2 +- +-#define UDMFN _SFR_MEM8(0xE6) +-#define FNCERR 4 +- +-#define UEINTX _SFR_MEM8(0xE8) +-#define TXINI 0 +-#define STALLEDI 1 +-#define RXOUTI 2 +-#define RXSTPI 3 +-#define NAKOUTI 4 +-#define RWAL 5 +-#define NAKINI 6 +-#define FIFOCON 7 +- +-#define UENUM _SFR_MEM8(0xE9) +-#define UENUM_0 0 +-#define UENUM_1 1 +-#define UENUM_2 2 +- +-#define UERST _SFR_MEM8(0xEA) +-#define EPRST0 0 +-#define EPRST1 1 +-#define EPRST2 2 +-#define EPRST3 3 +-#define EPRST4 4 +-#define EPRST5 5 +-#define EPRST6 6 +- +-#define UECONX _SFR_MEM8(0xEB) +-#define EPEN 0 +-#define RSTDT 3 +-#define STALLRQC 4 +-#define STALLRQ 5 +- +-#define UECFG0X _SFR_MEM8(0xEC) +-#define EPDIR 0 +-#define EPTYPE0 6 +-#define EPTYPE1 7 +- +-#define UECFG1X _SFR_MEM8(0xED) +-#define ALLOC 1 +-#define EPBK0 2 +-#define EPBK1 3 +-#define EPSIZE0 4 +-#define EPSIZE1 5 +-#define EPSIZE2 6 +- +-#define UESTA0X _SFR_MEM8(0xEE) +-#define NBUSYBK0 0 +-#define NBUSYBK1 1 +-#define DTSEQ0 2 +-#define DTSEQ1 3 +-#define UNDERFI 5 +-#define OVERFI 6 +-#define CFGOK 7 +- +-#define UESTA1X _SFR_MEM8(0xEF) +-#define CURRBK0 0 +-#define CURRBK1 1 +-#define CTRLDIR 2 +- +-#define UEIENX _SFR_MEM8(0xF0) +-#define TXINE 0 +-#define STALLEDE 1 +-#define RXOUTE 2 +-#define RXSTPE 3 +-#define NAKOUTE 4 +-#define NAKINE 6 +-#define FLERRE 7 +- +-#define UEDATX _SFR_MEM8(0xF1) +-#define DAT0 0 +-#define DAT1 1 +-#define DAT2 2 +-#define DAT3 3 +-#define DAT4 4 +-#define DAT5 5 +-#define DAT6 6 +-#define DAT7 7 +- +-#define UEBCLX _SFR_MEM8(0xF2) +-#define BYCT0 0 +-#define BYCT1 1 +-#define BYCT2 2 +-#define BYCT3 3 +-#define BYCT4 4 +-#define BYCT5 5 +-#define BYCT6 6 +-#define BYCT7 7 +- +-#define UEBCHX _SFR_MEM8(0xF3) +- +-#define UEINT _SFR_MEM8(0xF4) +-#define EPINT0 0 +-#define EPINT1 1 +-#define EPINT2 2 +-#define EPINT3 3 +-#define EPINT4 4 +-#define EPINT5 5 +-#define EPINT6 6 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ +-#define INT2_vect_num 3 +-#define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ +-#define INT3_vect_num 4 +-#define INT3_vect _VECTOR(4) /* External Interrupt Request 3 */ +-#define INT6_vect_num 7 +-#define INT6_vect _VECTOR(7) /* External Interrupt Request 6 */ +-#define PCINT0_vect_num 9 +-#define PCINT0_vect _VECTOR(9) /* Pin Change Interrupt Request 0 */ +-#define USB_GEN_vect_num 10 +-#define USB_GEN_vect _VECTOR(10) /* USB General Interrupt Request */ +-#define USB_COM_vect_num 11 +-#define USB_COM_vect _VECTOR(11) /* USB Endpoint/Pipe Interrupt Communication Request */ +-#define WDT_vect_num 12 +-#define WDT_vect _VECTOR(12) /* Watchdog Time-out Interrupt */ +-#define TIMER1_CAPT_vect_num 16 +-#define TIMER1_CAPT_vect _VECTOR(16) /* Timer/Counter1 Capture Event */ +-#define TIMER1_COMPA_vect_num 17 +-#define TIMER1_COMPA_vect _VECTOR(17) /* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPB_vect_num 18 +-#define TIMER1_COMPB_vect _VECTOR(18) /* Timer/Counter1 Compare Match B */ +-#define TIMER1_COMPC_vect_num 19 +-#define TIMER1_COMPC_vect _VECTOR(19) /* Timer/Counter1 Compare Match C */ +-#define TIMER1_OVF_vect_num 20 +-#define TIMER1_OVF_vect _VECTOR(20) /* Timer/Counter1 Overflow */ +-#define TIMER0_COMPA_vect_num 21 +-#define TIMER0_COMPA_vect _VECTOR(21) /* Timer/Counter0 Compare Match A */ +-#define TIMER0_COMPB_vect_num 22 +-#define TIMER0_COMPB_vect _VECTOR(22) /* Timer/Counter0 Compare Match B */ +-#define TIMER0_OVF_vect_num 23 +-#define TIMER0_OVF_vect _VECTOR(23) /* Timer/Counter0 Overflow */ +-#define SPI_STC_vect_num 24 +-#define SPI_STC_vect _VECTOR(24) /* SPI Serial Transfer Complete */ +-#define USART1_RX_vect_num 25 +-#define USART1_RX_vect _VECTOR(25) /* USART1, Rx Complete */ +-#define USART1_UDRE_vect_num 26 +-#define USART1_UDRE_vect _VECTOR(26) /* USART1 Data register Empty */ +-#define USART1_TX_vect_num 27 +-#define USART1_TX_vect _VECTOR(27) /* USART1, Tx Complete */ +-#define ANALOG_COMP_vect_num 28 +-#define ANALOG_COMP_vect _VECTOR(28) /* Analog Comparator */ +-#define ADC_vect_num 29 +-#define ADC_vect _VECTOR(29) /* ADC Conversion Complete */ +-#define EE_READY_vect_num 30 +-#define EE_READY_vect _VECTOR(30) /* EEPROM Ready */ +-#define TIMER3_CAPT_vect_num 31 +-#define TIMER3_CAPT_vect _VECTOR(31) /* Timer/Counter3 Capture Event */ +-#define TIMER3_COMPA_vect_num 32 +-#define TIMER3_COMPA_vect _VECTOR(32) /* Timer/Counter3 Compare Match A */ +-#define TIMER3_COMPB_vect_num 33 +-#define TIMER3_COMPB_vect _VECTOR(33) /* Timer/Counter3 Compare Match B */ +-#define TIMER3_COMPC_vect_num 34 +-#define TIMER3_COMPC_vect _VECTOR(34) /* Timer/Counter3 Compare Match C */ +-#define TIMER3_OVF_vect_num 35 +-#define TIMER3_OVF_vect _VECTOR(35) /* Timer/Counter3 Overflow */ +-#define TWI_vect_num 36 +-#define TWI_vect _VECTOR(36) /* 2-wire Serial Interface */ +-#define SPM_READY_vect_num 37 +-#define SPM_READY_vect _VECTOR(37) /* Store Program Memory Read */ +-#define TIMER4_COMPA_vect_num 38 +-#define TIMER4_COMPA_vect _VECTOR(38) /* Timer/Counter4 Compare Match A */ +-#define TIMER4_COMPB_vect_num 39 +-#define TIMER4_COMPB_vect _VECTOR(39) /* Timer/Counter4 Compare Match B */ +-#define TIMER4_COMPD_vect_num 40 +-#define TIMER4_COMPD_vect _VECTOR(40) /* Timer/Counter4 Compare Match D */ +-#define TIMER4_OVF_vect_num 41 +-#define TIMER4_OVF_vect _VECTOR(41) /* Timer/Counter4 Overflow */ +-#define TIMER4_FPF_vect_num 42 +-#define TIMER4_FPF_vect _VECTOR(42) /* Timer/Counter4 Fault Protection Interrupt */ +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (43 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (128) +-#define RAMSTART (0x100) +-#define RAMSIZE (1280) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x1FF) +-#define E2PAGESIZE (4) +-#define FLASHEND (0x3FFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ +-#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ +-#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define FUSE_HWBE (unsigned char)~_BV(3) /* Hardware Boot Enable */ +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x94 +-#define SIGNATURE_2 0x88 +- +- +-#endif /* _AVR_ATmega16U4_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom16u4.h 2185 2010-09-22 07:06:35Z aboyapati $ */ ++ ++/* avr/iom16u4.h - definitions for ATmega16U4 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom16u4.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATmega16U4_H_ ++#define _AVR_ATmega16U4_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC6 6 ++#define PINC7 7 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC6 6 ++#define DDC7 7 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC6 6 ++#define PORTC7 7 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE2 2 ++#define PINE6 6 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE2 2 ++#define DDE6 6 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE2 2 ++#define PORTE6 6 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF0 0 ++#define PINF1 1 ++#define PINF4 4 ++#define PINF5 5 ++#define PINF6 6 ++#define PINF7 7 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDF0 0 ++#define DDF1 1 ++#define DDF4 4 ++#define DDF5 5 ++#define DDF6 6 ++#define DDF7 7 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PORTF0 0 ++#define PORTF1 1 ++#define PORTF4 4 ++#define PORTF5 5 ++#define PORTF6 6 ++#define PORTF7 7 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define OCF1C 3 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++ ++#define TIFR3 _SFR_IO8(0x18) ++#define TOV3 0 ++#define OCF3A 1 ++#define OCF3B 2 ++#define OCF3C 3 ++#define ICF3 5 ++ ++#define TIFR4 _SFR_IO8(0x19) ++#define TOV4 2 ++#define OCF4B 5 ++#define OCF4A 6 ++#define OCF4D 7 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++#define INTF4 4 ++#define INTF5 5 ++#define INTF6 6 ++#define INTF7 7 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++#define INT3 3 ++#define INT4 4 ++#define INT5 5 ++#define INT6 6 ++#define INT7 7 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++#define EEAR9 1 ++#define EEAR10 2 ++#define EEAR11 3 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define OCR0A _SFR_IO8(0x27) ++#define OCROA_0 0 ++#define OCROA_1 1 ++#define OCROA_2 2 ++#define OCROA_3 3 ++#define OCROA_4 4 ++#define OCROA_5 5 ++#define OCROA_6 6 ++#define OCROA_7 7 ++ ++#define OCR0B _SFR_IO8(0x28) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define PLLCSR _SFR_IO8(0x29) ++#define PLOCK 0 ++#define PLLE 1 ++#define PINDIV 4 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCDR7 7 ++ ++#define PLLFRQ _SFR_IO8(0x32) ++#define PDIV0 0 ++#define PDIV1 1 ++#define PDIV2 2 ++#define PDIV3 3 ++#define PLLTM0 4 ++#define PLLTM1 5 ++#define PLLUSB 6 ++#define PINMUX 7 ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define JTRF 4 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define JTD 7 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define RAMPZ _SFR_IO8(0x3B) ++#define RAMPZ0 0 ++ ++#define EIND _SFR_IO8(0x3C) ++#define EIND0 0 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++#define PRR1 _SFR_MEM8(0x65) ++#define PRUSART1 0 ++#define PRTIM3 3 ++#define PRUSB 7 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define RCCTRL _SFR_MEM8(0x67) ++#define RCFREQ 0 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++#define EICRB _SFR_MEM8(0x6A) ++#define ISC40 0 ++#define ISC41 1 ++#define ISC50 2 ++#define ISC51 3 ++#define ISC60 4 ++#define ISC61 5 ++#define ISC70 6 ++#define ISC71 7 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define OCIE1C 3 ++#define ICIE1 5 ++ ++#define TIMSK3 _SFR_MEM8(0x71) ++#define TOIE3 0 ++#define OCIE3A 1 ++#define OCIE3B 2 ++#define OCIE3C 3 ++#define ICIE3 5 ++ ++#define TIMSK4 _SFR_MEM8(0x72) ++#define TOIE4 2 ++#define OCIE4B 5 ++#define OCIE4A 6 ++#define OCIE4D 7 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_MEM8(0x79) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ADTS3 3 ++#define MUX5 5 ++#define ACME 6 ++#define ADHSM 7 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR2 _SFR_MEM8(0x7D) ++#define ADC8D 0 ++#define ADC9D 1 ++#define ADC10D 2 ++#define ADC11D 3 ++#define ADC12D 4 ++#define ADC13D 5 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1C0 2 ++#define COM1C1 3 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1C 5 ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define OCR1C _SFR_MEM16(0x8C) ++ ++#define OCR1CL _SFR_MEM8(0x8C) ++#define OCR1CL0 0 ++#define OCR1CL1 1 ++#define OCR1CL2 2 ++#define OCR1CL3 3 ++#define OCR1CL4 4 ++#define OCR1CL5 5 ++#define OCR1CL6 6 ++#define OCR1CL7 7 ++ ++#define OCR1CH _SFR_MEM8(0x8D) ++#define OCR1CH0 0 ++#define OCR1CH1 1 ++#define OCR1CH2 2 ++#define OCR1CH3 3 ++#define OCR1CH4 4 ++#define OCR1CH5 5 ++#define OCR1CH6 6 ++#define OCR1CH7 7 ++ ++#define TCCR3A _SFR_MEM8(0x90) ++#define WGM30 0 ++#define WGM31 1 ++#define COM3C0 2 ++#define COM3C1 3 ++#define COM3B0 4 ++#define COM3B1 5 ++#define COM3A0 6 ++#define COM3A1 7 ++ ++#define TCCR3B _SFR_MEM8(0x91) ++#define CS30 0 ++#define CS31 1 ++#define CS32 2 ++#define WGM32 3 ++#define WGM33 4 ++#define ICES3 6 ++#define ICNC3 7 ++ ++#define TCCR3C _SFR_MEM8(0x92) ++#define FOC3C 5 ++#define FOC3B 6 ++#define FOC3A 7 ++ ++#define TCNT3 _SFR_MEM16(0x94) ++ ++#define TCNT3L _SFR_MEM8(0x94) ++#define TCNT3L0 0 ++#define TCNT3L1 1 ++#define TCNT3L2 2 ++#define TCNT3L3 3 ++#define TCNT3L4 4 ++#define TCNT3L5 5 ++#define TCNT3L6 6 ++#define TCNT3L7 7 ++ ++#define TCNT3H _SFR_MEM8(0x95) ++#define TCNT3H0 0 ++#define TCNT3H1 1 ++#define TCNT3H2 2 ++#define TCNT3H3 3 ++#define TCNT3H4 4 ++#define TCNT3H5 5 ++#define TCNT3H6 6 ++#define TCNT3H7 7 ++ ++#define ICR3 _SFR_MEM16(0x96) ++ ++#define ICR3L _SFR_MEM8(0x96) ++#define ICR3L0 0 ++#define ICR3L1 1 ++#define ICR3L2 2 ++#define ICR3L3 3 ++#define ICR3L4 4 ++#define ICR3L5 5 ++#define ICR3L6 6 ++#define ICR3L7 7 ++ ++#define ICR3H _SFR_MEM8(0x97) ++#define ICR3H0 0 ++#define ICR3H1 1 ++#define ICR3H2 2 ++#define ICR3H3 3 ++#define ICR3H4 4 ++#define ICR3H5 5 ++#define ICR3H6 6 ++#define ICR3H7 7 ++ ++#define OCR3A _SFR_MEM16(0x98) ++ ++#define OCR3AL _SFR_MEM8(0x98) ++#define OCR3AL0 0 ++#define OCR3AL1 1 ++#define OCR3AL2 2 ++#define OCR3AL3 3 ++#define OCR3AL4 4 ++#define OCR3AL5 5 ++#define OCR3AL6 6 ++#define OCR3AL7 7 ++ ++#define OCR3AH _SFR_MEM8(0x99) ++#define OCR3AH0 0 ++#define OCR3AH1 1 ++#define OCR3AH2 2 ++#define OCR3AH3 3 ++#define OCR3AH4 4 ++#define OCR3AH5 5 ++#define OCR3AH6 6 ++#define OCR3AH7 7 ++ ++#define OCR3B _SFR_MEM16(0x9A) ++ ++#define OCR3BL _SFR_MEM8(0x9A) ++#define OCR3BL0 0 ++#define OCR3BL1 1 ++#define OCR3BL2 2 ++#define OCR3BL3 3 ++#define OCR3BL4 4 ++#define OCR3BL5 5 ++#define OCR3BL6 6 ++#define OCR3BL7 7 ++ ++#define OCR3BH _SFR_MEM8(0x9B) ++#define OCR3BH0 0 ++#define OCR3BH1 1 ++#define OCR3BH2 2 ++#define OCR3BH3 3 ++#define OCR3BH4 4 ++#define OCR3BH5 5 ++#define OCR3BH6 6 ++#define OCR3BH7 7 ++ ++#define OCR3C _SFR_MEM16(0x9C) ++ ++#define OCR3CL _SFR_MEM8(0x9C) ++#define OCR3CL0 0 ++#define OCR3CL1 1 ++#define OCR3CL2 2 ++#define OCR3CL3 3 ++#define OCR3CL4 4 ++#define OCR3CL5 5 ++#define OCR3CL6 6 ++#define OCR3CL7 7 ++ ++#define OCR3CH _SFR_MEM8(0x9D) ++#define OCR3CH0 0 ++#define OCR3CH1 1 ++#define OCR3CH2 2 ++#define OCR3CH3 3 ++#define OCR3CH4 4 ++#define OCR3CH5 5 ++#define OCR3CH6 6 ++#define OCR3CH7 7 ++ ++#define TWBR _SFR_MEM8(0xB8) ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++#define TCNT4 _SFR_MEM8(0xBE) ++#define TC40 0 ++#define TC41 1 ++#define TC42 2 ++#define TC43 3 ++#define TC44 4 ++#define TC45 5 ++#define TC46 6 ++#define TC47 7 ++ ++#define TC4H _SFR_MEM8(0xBF) ++#define TC48 0 ++#define TC49 1 ++#define TC410 2 ++ ++#define TCCR4A _SFR_MEM8(0xC0) ++#define PWM4B 0 ++#define PWM4A 1 ++#define FOC4B 2 ++#define FOC4A 3 ++#define COM4B0 4 ++#define COM4B1 5 ++#define COM4A0 6 ++#define COM4A1 7 ++ ++#define TCCR4B _SFR_MEM8(0xC1) ++#define CS40 0 ++#define CS41 1 ++#define CS42 2 ++#define CS43 3 ++#define DTPS40 4 ++#define DTPS41 5 ++#define PSR4 6 ++#define PWM4X 7 ++ ++#define TCCR4C _SFR_MEM8(0xC2) ++#define PWM4D 0 ++#define FOC4D 1 ++#define COM4D0 2 ++#define COM4D1 3 ++#define COM4B0S 4 ++#define COM4B1S 5 ++#define COM4A0S 6 ++#define COM4A1S 7 ++ ++#define TCCR4D _SFR_MEM8(0xC3) ++#define WGM40 0 ++#define WGM41 1 ++#define FPF4 2 ++#define FPAC4 3 ++#define FPES4 4 ++#define FPNC4 5 ++#define FPEN4 6 ++#define FPIE4 7 ++ ++#define TCCR4E _SFR_MEM8(0xC4) ++#define OC4OE0 0 ++#define OC4OE1 1 ++#define OC4OE2 2 ++#define OC4OE3 3 ++#define OC4OE4 4 ++#define OC4OE5 5 ++#define ENHC4 6 ++#define TLOCK4 7 ++ ++#define CLKSEL0 _SFR_MEM8(0xC5) ++#define CLKS 0 ++#define EXTE 2 ++#define RCE 3 ++#define EXSUT0 4 ++#define EXSUT1 5 ++#define RCSUT0 6 ++#define RCSUT1 7 ++ ++#define CLKSEL1 _SFR_MEM8(0xC6) ++#define EXCKSEL0 0 ++#define EXCKSEL1 1 ++#define EXCKSEL2 2 ++#define EXCKSEL3 3 ++#define RCCKSEL0 4 ++#define RCCKSEL1 5 ++#define RCCKSEL2 6 ++#define RCCKSEL3 7 ++ ++#define CLKSTA _SFR_MEM8(0xC7) ++#define EXTON 0 ++#define RCON 1 ++ ++#define UCSR1A _SFR_MEM8(0xC8) ++#define MPCM1 0 ++#define U2X1 1 ++#define UPE1 2 ++#define DOR1 3 ++#define FE1 4 ++#define UDRE1 5 ++#define TXC1 6 ++#define RXC1 7 ++ ++#define UCSR1B _SFR_MEM8(0xC9) ++#define TXB81 0 ++#define RXB81 1 ++#define UCSZ12 2 ++#define TXEN1 3 ++#define RXEN1 4 ++#define UDRIE1 5 ++#define TXCIE1 6 ++#define RXCIE1 7 ++ ++#define UCSR1C _SFR_MEM8(0xCA) ++#define UCPOL1 0 ++#define UCSZ10 1 ++#define UCSZ11 2 ++#define USBS1 3 ++#define UPM10 4 ++#define UPM11 5 ++#define UMSEL10 6 ++#define UMSEL11 7 ++ ++#define UCSR1D _SFR_MEM8(0xCB) ++#define RTSEN 0 ++#define CTSEN 1 ++ ++#define UBRR1 _SFR_MEM16(0xCC) ++ ++#define UBRR1L _SFR_MEM8(0xCC) ++ ++#define UBRR1H _SFR_MEM8(0xCD) ++ ++#define UDR1 _SFR_MEM8(0xCE) ++#define UDR1_0 0 ++#define UDR1_1 1 ++#define UDR1_2 2 ++#define UDR1_3 3 ++#define UDR1_4 4 ++#define UDR1_5 5 ++#define UDR1_6 6 ++#define UDR1_7 7 ++ ++#define OCR4A _SFR_MEM8(0xCF) ++#define OCR4A0 0 ++#define OCR4A1 1 ++#define OCR4A2 2 ++#define OCR4A3 3 ++#define OCR4A4 4 ++#define OCR4A5 5 ++#define OCR4A6 6 ++#define OCR4A7 7 ++ ++#define OCR4B _SFR_MEM8(0xD0) ++#define OCR4B0 0 ++#define OCR4B1 1 ++#define OCR4B2 2 ++#define OCR4B3 3 ++#define OCR4B4 4 ++#define OCR4B5 5 ++#define OCR4B6 6 ++#define OCR4B7 7 ++ ++#define OCR4C _SFR_MEM8(0xD1) ++#define OCR4C0 0 ++#define OCR4C1 1 ++#define OCR4C2 2 ++#define OCR4C3 3 ++#define OCR4C4 4 ++#define OCR4C5 5 ++#define OCR4C6 6 ++#define OCR4C7 7 ++ ++#define OCR4D _SFR_MEM8(0xD2) ++#define OCR4D0 0 ++#define OCR4D1 1 ++#define OCR4D2 2 ++#define OCR4D3 3 ++#define OCR4D4 4 ++#define OCR4D5 5 ++#define OCR4D6 6 ++#define OCR4D7 7 ++ ++#define DT4 _SFR_MEM8(0xD4) ++#define DT4L0 0 ++#define DT4L1 1 ++#define DT4L2 2 ++#define DT4L3 3 ++#define DT4L4 4 ++#define DT4L5 5 ++#define DT4L6 6 ++#define DT4L7 7 ++ ++#define UHWCON _SFR_MEM8(0xD7) ++#define UVREGE 0 ++ ++#define USBCON _SFR_MEM8(0xD8) ++#define VBUSTE 0 ++#define OTGPADE 4 ++#define FRZCLK 5 ++#define USBE 7 ++ ++#define USBSTA _SFR_MEM8(0xD9) ++#define VBUS 0 ++#define SPEED 3 ++ ++#define USBINT _SFR_MEM8(0xDA) ++#define VBUSTI 0 ++ ++#define UDCON _SFR_MEM8(0xE0) ++#define DETACH 0 ++#define RMWKUP 1 ++#define LSM 2 ++#define RSTCPU 3 ++ ++#define UDINT _SFR_MEM8(0xE1) ++#define SUSPI 0 ++#define SOFI 2 ++#define EORSTI 3 ++#define WAKEUPI 4 ++#define EORSMI 5 ++#define UPRSMI 6 ++ ++#define UDIEN _SFR_MEM8(0xE2) ++#define SUSPE 0 ++#define SOFE 2 ++#define EORSTE 3 ++#define WAKEUPE 4 ++#define EORSME 5 ++#define UPRSME 6 ++ ++#define UDADDR _SFR_MEM8(0xE3) ++#define UADD0 0 ++#define UADD1 1 ++#define UADD2 2 ++#define UADD3 3 ++#define UADD4 4 ++#define UADD5 5 ++#define UADD6 6 ++#define ADDEN 7 ++ ++#define UDFNUM _SFR_MEM16(0xE4) ++ ++#define UDFNUML _SFR_MEM8(0xE4) ++#define FNUM0 0 ++#define FNUM1 1 ++#define FNUM2 2 ++#define FNUM3 3 ++#define FNUM4 4 ++#define FNUM5 5 ++#define FNUM6 6 ++#define FNUM7 7 ++ ++#define UDFNUMH _SFR_MEM8(0xE5) ++#define FNUM8 0 ++#define FNUM9 1 ++#define FNUM10 2 ++ ++#define UDMFN _SFR_MEM8(0xE6) ++#define FNCERR 4 ++ ++#define UEINTX _SFR_MEM8(0xE8) ++#define TXINI 0 ++#define STALLEDI 1 ++#define RXOUTI 2 ++#define RXSTPI 3 ++#define NAKOUTI 4 ++#define RWAL 5 ++#define NAKINI 6 ++#define FIFOCON 7 ++ ++#define UENUM _SFR_MEM8(0xE9) ++#define UENUM_0 0 ++#define UENUM_1 1 ++#define UENUM_2 2 ++ ++#define UERST _SFR_MEM8(0xEA) ++#define EPRST0 0 ++#define EPRST1 1 ++#define EPRST2 2 ++#define EPRST3 3 ++#define EPRST4 4 ++#define EPRST5 5 ++#define EPRST6 6 ++ ++#define UECONX _SFR_MEM8(0xEB) ++#define EPEN 0 ++#define RSTDT 3 ++#define STALLRQC 4 ++#define STALLRQ 5 ++ ++#define UECFG0X _SFR_MEM8(0xEC) ++#define EPDIR 0 ++#define EPTYPE0 6 ++#define EPTYPE1 7 ++ ++#define UECFG1X _SFR_MEM8(0xED) ++#define ALLOC 1 ++#define EPBK0 2 ++#define EPBK1 3 ++#define EPSIZE0 4 ++#define EPSIZE1 5 ++#define EPSIZE2 6 ++ ++#define UESTA0X _SFR_MEM8(0xEE) ++#define NBUSYBK0 0 ++#define NBUSYBK1 1 ++#define DTSEQ0 2 ++#define DTSEQ1 3 ++#define UNDERFI 5 ++#define OVERFI 6 ++#define CFGOK 7 ++ ++#define UESTA1X _SFR_MEM8(0xEF) ++#define CURRBK0 0 ++#define CURRBK1 1 ++#define CTRLDIR 2 ++ ++#define UEIENX _SFR_MEM8(0xF0) ++#define TXINE 0 ++#define STALLEDE 1 ++#define RXOUTE 2 ++#define RXSTPE 3 ++#define NAKOUTE 4 ++#define NAKINE 6 ++#define FLERRE 7 ++ ++#define UEDATX _SFR_MEM8(0xF1) ++#define DAT0 0 ++#define DAT1 1 ++#define DAT2 2 ++#define DAT3 3 ++#define DAT4 4 ++#define DAT5 5 ++#define DAT6 6 ++#define DAT7 7 ++ ++#define UEBCLX _SFR_MEM8(0xF2) ++#define BYCT0 0 ++#define BYCT1 1 ++#define BYCT2 2 ++#define BYCT3 3 ++#define BYCT4 4 ++#define BYCT5 5 ++#define BYCT6 6 ++#define BYCT7 7 ++ ++#define UEBCHX _SFR_MEM8(0xF3) ++ ++#define UEINT _SFR_MEM8(0xF4) ++#define EPINT0 0 ++#define EPINT1 1 ++#define EPINT2 2 ++#define EPINT3 3 ++#define EPINT4 4 ++#define EPINT5 5 ++#define EPINT6 6 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ ++#define INT2_vect_num 3 ++#define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ ++#define INT3_vect_num 4 ++#define INT3_vect _VECTOR(4) /* External Interrupt Request 3 */ ++#define INT6_vect_num 7 ++#define INT6_vect _VECTOR(7) /* External Interrupt Request 6 */ ++#define PCINT0_vect_num 9 ++#define PCINT0_vect _VECTOR(9) /* Pin Change Interrupt Request 0 */ ++#define USB_GEN_vect_num 10 ++#define USB_GEN_vect _VECTOR(10) /* USB General Interrupt Request */ ++#define USB_COM_vect_num 11 ++#define USB_COM_vect _VECTOR(11) /* USB Endpoint/Pipe Interrupt Communication Request */ ++#define WDT_vect_num 12 ++#define WDT_vect _VECTOR(12) /* Watchdog Time-out Interrupt */ ++#define TIMER1_CAPT_vect_num 16 ++#define TIMER1_CAPT_vect _VECTOR(16) /* Timer/Counter1 Capture Event */ ++#define TIMER1_COMPA_vect_num 17 ++#define TIMER1_COMPA_vect _VECTOR(17) /* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPB_vect_num 18 ++#define TIMER1_COMPB_vect _VECTOR(18) /* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPC_vect_num 19 ++#define TIMER1_COMPC_vect _VECTOR(19) /* Timer/Counter1 Compare Match C */ ++#define TIMER1_OVF_vect_num 20 ++#define TIMER1_OVF_vect _VECTOR(20) /* Timer/Counter1 Overflow */ ++#define TIMER0_COMPA_vect_num 21 ++#define TIMER0_COMPA_vect _VECTOR(21) /* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPB_vect_num 22 ++#define TIMER0_COMPB_vect _VECTOR(22) /* Timer/Counter0 Compare Match B */ ++#define TIMER0_OVF_vect_num 23 ++#define TIMER0_OVF_vect _VECTOR(23) /* Timer/Counter0 Overflow */ ++#define SPI_STC_vect_num 24 ++#define SPI_STC_vect _VECTOR(24) /* SPI Serial Transfer Complete */ ++#define USART1_RX_vect_num 25 ++#define USART1_RX_vect _VECTOR(25) /* USART1, Rx Complete */ ++#define USART1_UDRE_vect_num 26 ++#define USART1_UDRE_vect _VECTOR(26) /* USART1 Data register Empty */ ++#define USART1_TX_vect_num 27 ++#define USART1_TX_vect _VECTOR(27) /* USART1, Tx Complete */ ++#define ANALOG_COMP_vect_num 28 ++#define ANALOG_COMP_vect _VECTOR(28) /* Analog Comparator */ ++#define ADC_vect_num 29 ++#define ADC_vect _VECTOR(29) /* ADC Conversion Complete */ ++#define EE_READY_vect_num 30 ++#define EE_READY_vect _VECTOR(30) /* EEPROM Ready */ ++#define TIMER3_CAPT_vect_num 31 ++#define TIMER3_CAPT_vect _VECTOR(31) /* Timer/Counter3 Capture Event */ ++#define TIMER3_COMPA_vect_num 32 ++#define TIMER3_COMPA_vect _VECTOR(32) /* Timer/Counter3 Compare Match A */ ++#define TIMER3_COMPB_vect_num 33 ++#define TIMER3_COMPB_vect _VECTOR(33) /* Timer/Counter3 Compare Match B */ ++#define TIMER3_COMPC_vect_num 34 ++#define TIMER3_COMPC_vect _VECTOR(34) /* Timer/Counter3 Compare Match C */ ++#define TIMER3_OVF_vect_num 35 ++#define TIMER3_OVF_vect _VECTOR(35) /* Timer/Counter3 Overflow */ ++#define TWI_vect_num 36 ++#define TWI_vect _VECTOR(36) /* 2-wire Serial Interface */ ++#define SPM_READY_vect_num 37 ++#define SPM_READY_vect _VECTOR(37) /* Store Program Memory Read */ ++#define TIMER4_COMPA_vect_num 38 ++#define TIMER4_COMPA_vect _VECTOR(38) /* Timer/Counter4 Compare Match A */ ++#define TIMER4_COMPB_vect_num 39 ++#define TIMER4_COMPB_vect _VECTOR(39) /* Timer/Counter4 Compare Match B */ ++#define TIMER4_COMPD_vect_num 40 ++#define TIMER4_COMPD_vect _VECTOR(40) /* Timer/Counter4 Compare Match D */ ++#define TIMER4_OVF_vect_num 41 ++#define TIMER4_OVF_vect _VECTOR(41) /* Timer/Counter4 Overflow */ ++#define TIMER4_FPF_vect_num 42 ++#define TIMER4_FPF_vect _VECTOR(42) /* Timer/Counter4 Fault Protection Interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (43 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (128) ++#define RAMSTART (0x100) ++#define RAMSIZE (1280) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x1FF) ++#define E2PAGESIZE (4) ++#define FLASHEND (0x3FFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ ++#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ ++#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define FUSE_HWBE (unsigned char)~_BV(3) /* Hardware Boot Enable */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x88 ++ ++ ++#endif /* _AVR_ATmega16U4_H_ */ ++ +diff --git a/include/avr/iom2560.h b/include/avr/iom2560.h +index 07039ad..57ec9b7 100644 +--- a/include/avr/iom2560.h ++++ b/include/avr/iom2560.h +@@ -1,94 +1,95 @@ +-/* Copyright (c) 2005 Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id */ +- +-/* avr/iom2560.h - definitions for ATmega2560 */ +- +-#ifndef _AVR_IOM2560_H_ +-#define _AVR_IOM2560_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 256 +-#define RAMEND 0x21FF +-#define XRAMEND 0xFFFF +-#define E2END 0xFFF +-#define E2PAGESIZE 8 +-#define FLASHEND 0x3FFFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x98 +-#define SIGNATURE_2 0x01 +- +- +-#endif /* _AVR_IOM2560_H_ */ ++/* Copyright (c) 2005 Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id */ ++ ++/* avr/iom2560.h - definitions for ATmega2560 */ ++ ++#ifndef _AVR_IOM2560_H_ ++#define _AVR_IOM2560_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 256 ++#define RAMSTART 0x200 ++#define RAMEND 0x21FF ++#define XRAMEND 0xFFFF ++#define E2END 0xFFF ++#define E2PAGESIZE 8 ++#define FLASHEND 0x3FFFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x98 ++#define SIGNATURE_2 0x01 ++ ++ ++#endif /* _AVR_IOM2560_H_ */ +diff --git a/include/avr/iom2561.h b/include/avr/iom2561.h +index fd379a2..49fc93a 100644 +--- a/include/avr/iom2561.h ++++ b/include/avr/iom2561.h +@@ -1,94 +1,95 @@ +-/* Copyright (c) 2005 Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id */ +- +-/* avr/iom2561.h - definitions for ATmega2561 */ +- +-#ifndef _AVR_IOM2561_H_ +-#define _AVR_IOM2561_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 256 +-#define RAMEND 0x21FF +-#define XRAMEND 0xFFFF +-#define E2END 0xFFF +-#define E2PAGESIZE 8 +-#define FLASHEND 0x3FFFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x98 +-#define SIGNATURE_2 0x02 +- +- +-#endif /* _AVR_IOM2561_H_ */ ++/* Copyright (c) 2005 Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id */ ++ ++/* avr/iom2561.h - definitions for ATmega2561 */ ++ ++#ifndef _AVR_IOM2561_H_ ++#define _AVR_IOM2561_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 256 ++#define RAMSTART 0x200 ++#define RAMEND 0x21FF ++#define XRAMEND 0xFFFF ++#define E2END 0xFFF ++#define E2PAGESIZE 8 ++#define FLASHEND 0x3FFFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x98 ++#define SIGNATURE_2 0x02 ++ ++ ++#endif /* _AVR_IOM2561_H_ */ +diff --git a/include/avr/iom2564rfr2.h b/include/avr/iom2564rfr2.h +new file mode 100644 +index 0000000..edda8c0 +--- /dev/null ++++ b/include/avr/iom2564rfr2.h +@@ -0,0 +1,2540 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATMEGA2564RFR2_H_INCLUDED ++#define _AVR_ATMEGA2564RFR2_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom2564rfr2.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDRA7 7 ++#define DDRA6 6 ++#define DDRA5 5 ++#define DDRA4 4 ++#define DDRA3 3 ++#define DDRA2 2 ++#define DDRA1 1 ++#define DDRA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDRC7 7 ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC7 7 ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDRE7 7 ++#define DDRE6 6 ++#define DDRE5 5 ++#define DDRE4 4 ++#define DDRE3 3 ++#define DDRE2 2 ++#define DDRE1 1 ++#define DDRE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE7 7 ++#define PORTE6 6 ++#define PORTE5 5 ++#define PORTE4 4 ++#define PORTE3 3 ++#define PORTE2 2 ++#define PORTE1 1 ++#define PORTE0 0 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDRF7 7 ++#define DDRF6 6 ++#define DDRF5 5 ++#define DDRF4 4 ++#define DDRF3 3 ++#define DDRF2 2 ++#define DDRF1 1 ++#define DDRF0 0 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PORTF7 7 ++#define PORTF6 6 ++#define PORTF5 5 ++#define PORTF4 4 ++#define PORTF3 3 ++#define PORTF2 2 ++#define PORTF1 1 ++#define PORTF0 0 ++ ++#define PING _SFR_IO8(0x12) ++#define PING7 7 ++#define PING6 6 ++#define PING5 5 ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++#define DDRG _SFR_IO8(0x13) ++#define DDRG7 7 ++#define DDRG6 6 ++#define DDRG5 5 ++#define DDRG4 4 ++#define DDRG3 3 ++#define DDRG2 2 ++#define DDRG1 1 ++#define DDRG0 0 ++ ++#define PORTG _SFR_IO8(0x14) ++#define PORTG7 7 ++#define PORTG6 6 ++#define PORTG5 5 ++#define PORTG4 4 ++#define PORTG3 3 ++#define PORTG2 2 ++#define PORTG1 1 ++#define PORTG0 0 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++#define Res0 3 ++#define Res1 4 ++#define Res2 5 ++#define Res3 6 ++#define Res4 7 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define OCF1C 3 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++#define TIFR3 _SFR_IO8(0x18) ++#define TOV3 0 ++#define OCF3A 1 ++#define OCF3B 2 ++#define OCF3C 3 ++#define ICF3 5 ++ ++#define TIFR4 _SFR_IO8(0x19) ++#define TOV4 0 ++#define OCF4A 1 ++#define OCF4B 2 ++#define OCF4C 3 ++#define ICF4 5 ++ ++#define TIFR5 _SFR_IO8(0x1A) ++#define TOV5 0 ++#define OCF5A 1 ++#define OCF5B 2 ++#define OCF5C 3 ++#define ICF5 5 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++#define INTF4 4 ++#define INTF5 5 ++#define INTF6 6 ++#define INTF7 7 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++#define INT3 3 ++#define INT4 4 ++#define INT5 5 ++#define INT6 6 ++#define INT7 7 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define PSRASY 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++ ++#define OCR0A _SFR_IO8(0x27) ++ ++#define OCR0B _SFR_IO8(0x28) ++ ++/* Reserved [0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCDR7 7 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define JTRF 4 ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define JTD 7 ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3A] */ ++ ++#define RAMPZ _SFR_IO8(0x3B) ++#define RAMPZ0 0 ++#define RAMPZ1 1 ++#define Res5 7 ++ ++#define EIND _SFR_IO8(0x3C) ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDE 3 ++#define WDCE 4 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62] */ ++ ++#define PRR2 _SFR_MEM8(0x63) ++#define PRRAM0 0 ++#define PRRAM1 1 ++#define PRRAM2 2 ++#define PRRAM3 3 ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRPGA 4 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++#define PRR1 _SFR_MEM8(0x65) ++#define PRUSART1 0 ++#define PRTIM3 3 ++#define PRTIM4 4 ++#define PRTIM5 5 ++#define PRTRX24 6 ++#define Res 7 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define BGCR _SFR_MEM8(0x67) ++#define BGCAL0 0 ++#define BGCAL1 1 ++#define BGCAL2 2 ++#define BGCAL_FINE0 3 ++#define BGCAL_FINE1 4 ++#define BGCAL_FINE2 5 ++#define BGCAL_FINE3 6 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++#define EICRB _SFR_MEM8(0x6A) ++#define ISC40 0 ++#define ISC41 1 ++#define ISC50 2 ++#define ISC51 3 ++#define ISC60 4 ++#define ISC61 5 ++#define ISC70 6 ++#define ISC71 7 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define OCIE1C 3 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++#define TIMSK3 _SFR_MEM8(0x71) ++#define TOIE3 0 ++#define OCIE3A 1 ++#define OCIE3B 2 ++#define OCIE3C 3 ++#define ICIE3 5 ++ ++#define TIMSK4 _SFR_MEM8(0x72) ++#define TOIE4 0 ++#define OCIE4A 1 ++#define OCIE4B 2 ++#define OCIE4C 3 ++#define ICIE4 5 ++ ++#define TIMSK5 _SFR_MEM8(0x73) ++#define TOIE5 0 ++#define OCIE5A 1 ++#define OCIE5B 2 ++#define OCIE5C 3 ++#define ICIE5 5 ++ ++/* Reserved [0x74] */ ++ ++#define NEMCR _SFR_MEM8(0x75) ++#define AEAM0 4 ++#define AEAM1 5 ++#define ENEAM 6 ++ ++/* Reserved [0x76] */ ++ ++#define ADCSRC _SFR_MEM8(0x77) ++#define ADSUT0 0 ++#define ADSUT1 1 ++#define ADSUT2 2 ++#define ADSUT3 3 ++#define ADSUT4 4 ++#define ADTHT0 6 ++#define ADTHT1 7 ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ACME 6 ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define MUX5 3 ++#define ACCH 4 ++#define REFOK 5 ++#define AVDDOK 7 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR2 _SFR_MEM8(0x7D) ++#define ADC8D 0 ++#define ADC9D 1 ++#define ADC10D 2 ++#define ADC11D 3 ++#define ADC12D 4 ++#define ADC13D 5 ++#define ADC14D 6 ++#define ADC15D 7 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1C0 2 ++#define COM1C1 3 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1C 5 ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Combine OCR1CL and OCR1CH */ ++#define OCR1C _SFR_MEM16(0x8C) ++ ++#define OCR1CL _SFR_MEM8(0x8C) ++#define OCR1CH _SFR_MEM8(0x8D) ++ ++/* Reserved [0x8E..0x8F] */ ++ ++#define TCCR3A _SFR_MEM8(0x90) ++#define WGM30 0 ++#define WGM31 1 ++#define COM3C0 2 ++#define COM3C1 3 ++#define COM3B0 4 ++#define COM3B1 5 ++#define COM3A0 6 ++#define COM3A1 7 ++ ++#define TCCR3B _SFR_MEM8(0x91) ++#define CS30 0 ++#define CS31 1 ++#define CS32 2 ++#define WGM32 3 ++#define WGM33 4 ++#define ICES3 6 ++#define ICNC3 7 ++ ++#define TCCR3C _SFR_MEM8(0x92) ++#define FOC3C 5 ++#define FOC3B 6 ++#define FOC3A 7 ++ ++/* Reserved [0x93] */ ++ ++/* Combine TCNT3L and TCNT3H */ ++#define TCNT3 _SFR_MEM16(0x94) ++ ++#define TCNT3L _SFR_MEM8(0x94) ++#define TCNT3H _SFR_MEM8(0x95) ++ ++/* Combine ICR3L and ICR3H */ ++#define ICR3 _SFR_MEM16(0x96) ++ ++#define ICR3L _SFR_MEM8(0x96) ++#define ICR3H _SFR_MEM8(0x97) ++ ++/* Combine OCR3AL and OCR3AH */ ++#define OCR3A _SFR_MEM16(0x98) ++ ++#define OCR3AL _SFR_MEM8(0x98) ++#define OCR3AH _SFR_MEM8(0x99) ++ ++/* Combine OCR3BL and OCR3BH */ ++#define OCR3B _SFR_MEM16(0x9A) ++ ++#define OCR3BL _SFR_MEM8(0x9A) ++#define OCR3BH _SFR_MEM8(0x9B) ++ ++/* Combine OCR3CL and OCR3CH */ ++#define OCR3C _SFR_MEM16(0x9C) ++ ++#define OCR3CL _SFR_MEM8(0x9C) ++#define OCR3CH _SFR_MEM8(0x9D) ++ ++/* Reserved [0x9E..0x9F] */ ++ ++#define TCCR4A _SFR_MEM8(0xA0) ++#define WGM40 0 ++#define WGM41 1 ++#define COM4C0 2 ++#define COM4C1 3 ++#define COM4B0 4 ++#define COM4B1 5 ++#define COM4A0 6 ++#define COM4A1 7 ++ ++#define TCCR4B _SFR_MEM8(0xA1) ++#define CS40 0 ++#define CS41 1 ++#define CS42 2 ++#define WGM42 3 ++#define WGM43 4 ++#define ICES4 6 ++#define ICNC4 7 ++ ++#define TCCR4C _SFR_MEM8(0xA2) ++#define FOC4C 5 ++#define FOC4B 6 ++#define FOC4A 7 ++ ++/* Reserved [0xA3] */ ++ ++/* Combine TCNT4L and TCNT4H */ ++#define TCNT4 _SFR_MEM16(0xA4) ++ ++#define TCNT4L _SFR_MEM8(0xA4) ++#define TCNT4H _SFR_MEM8(0xA5) ++ ++/* Combine ICR4L and ICR4H */ ++#define ICR4 _SFR_MEM16(0xA6) ++ ++#define ICR4L _SFR_MEM8(0xA6) ++#define ICR4H _SFR_MEM8(0xA7) ++ ++/* Combine OCR4AL and OCR4AH */ ++#define OCR4A _SFR_MEM16(0xA8) ++ ++#define OCR4AL _SFR_MEM8(0xA8) ++#define OCR4AH _SFR_MEM8(0xA9) ++ ++/* Combine OCR4BL and OCR4BH */ ++#define OCR4B _SFR_MEM16(0xAA) ++ ++#define OCR4BL _SFR_MEM8(0xAA) ++#define OCR4BH _SFR_MEM8(0xAB) ++ ++/* Combine OCR4CL and OCR4CH */ ++#define OCR4C _SFR_MEM16(0xAC) ++ ++#define OCR4CL _SFR_MEM8(0xAC) ++#define OCR4CH _SFR_MEM8(0xAD) ++ ++/* Reserved [0xAE..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++#define OCR2B _SFR_MEM8(0xB4) ++ ++/* Reserved [0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++#define EXCLKAMR 7 ++ ++/* Reserved [0xB7] */ ++ ++#define TWBR _SFR_MEM8(0xB8) ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++#define IRQ_MASK1 _SFR_MEM8(0xBE) ++#define TX_START_EN 0 ++#define MAF_0_AMI_EN 1 ++#define MAF_1_AMI_EN 2 ++#define MAF_2_AMI_EN 3 ++#define MAF_3_AMI_EN 4 ++ ++#define IRQ_STATUS1 _SFR_MEM8(0xBF) ++#define TX_START 0 ++#define MAF_0_AMI 1 ++#define MAF_1_AMI 2 ++#define MAF_2_AMI 3 ++#define MAF_3_AMI 4 ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++#define UCPHA0 1 ++#define UDORD0 2 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0xC6) ++ ++/* Reserved [0xC7] */ ++ ++#define UCSR1A _SFR_MEM8(0xC8) ++#define MPCM1 0 ++#define U2X1 1 ++#define UPE1 2 ++#define DOR1 3 ++#define FE1 4 ++#define UDRE1 5 ++#define TXC1 6 ++#define RXC1 7 ++ ++#define UCSR1B _SFR_MEM8(0xC9) ++#define TXB81 0 ++#define RXB81 1 ++#define UCSZ12 2 ++#define TXEN1 3 ++#define RXEN1 4 ++#define UDRIE1 5 ++#define TXCIE1 6 ++#define RXCIE1 7 ++ ++#define UCSR1C _SFR_MEM8(0xCA) ++#define UCPOL1 0 ++#define UCSZ10 1 ++#define UCSZ11 2 ++#define USBS1 3 ++#define UPM10 4 ++#define UPM11 5 ++#define UMSEL10 6 ++#define UMSEL11 7 ++#define UCPHA1 1 ++#define UDORD1 2 ++ ++/* Reserved [0xCB] */ ++ ++/* Combine UBRR1L and UBRR1H */ ++#define UBRR1 _SFR_MEM16(0xCC) ++ ++#define UBRR1L _SFR_MEM8(0xCC) ++#define UBRR1H _SFR_MEM8(0xCD) ++ ++#define UDR1 _SFR_MEM8(0xCE) ++ ++/* Reserved [0xCF..0xD6] */ ++ ++#define SCRSTRLL _SFR_MEM8(0xD7) ++#define SCRSTRLL0 0 ++#define SCRSTRLL1 1 ++#define SCRSTRLL2 2 ++#define SCRSTRLL3 3 ++#define SCRSTRLL4 4 ++#define SCRSTRLL5 5 ++#define SCRSTRLL6 6 ++#define SCRSTRLL7 7 ++ ++#define SCRSTRLH _SFR_MEM8(0xD8) ++#define SCRSTRLH0 0 ++#define SCRSTRLH1 1 ++#define SCRSTRLH2 2 ++#define SCRSTRLH3 3 ++#define SCRSTRLH4 4 ++#define SCRSTRLH5 5 ++#define SCRSTRLH6 6 ++#define SCRSTRLH7 7 ++ ++#define SCRSTRHL _SFR_MEM8(0xD9) ++#define SCRSTRHL0 0 ++#define SCRSTRHL1 1 ++#define SCRSTRHL2 2 ++#define SCRSTRHL3 3 ++#define SCRSTRHL4 4 ++#define SCRSTRHL5 5 ++#define SCRSTRHL6 6 ++#define SCRSTRHL7 7 ++ ++#define SCRSTRHH _SFR_MEM8(0xDA) ++#define SCRSTRHH0 0 ++#define SCRSTRHH1 1 ++#define SCRSTRHH2 2 ++#define SCRSTRHH3 3 ++#define SCRSTRHH4 4 ++#define SCRSTRHH5 5 ++#define SCRSTRHH6 6 ++#define SCRSTRHH7 7 ++ ++#define SCCSR _SFR_MEM8(0xDB) ++#define SCCS10 0 ++#define SCCS11 1 ++#define SCCS20 2 ++#define SCCS21 3 ++#define SCCS30 4 ++#define SCCS31 5 ++ ++#define SCCR0 _SFR_MEM8(0xDC) ++#define SCCMP1 0 ++#define SCCMP2 1 ++#define SCCMP3 2 ++#define SCTSE 3 ++#define SCCKSEL 4 ++#define SCEN 5 ++#define SCMBTS 6 ++#define SCRES 7 ++ ++#define SCCR1 _SFR_MEM8(0xDD) ++#define SCENBO 0 ++#define SCEECLK 1 ++#define SCCKDIV0 2 ++#define SCCKDIV1 3 ++#define SCCKDIV2 4 ++#define SCBTSM 5 ++#define Res6 7 ++ ++#define SCSR _SFR_MEM8(0xDE) ++#define SCBSY 0 ++ ++#define SCIRQM _SFR_MEM8(0xDF) ++#define IRQMCP1 0 ++#define IRQMCP2 1 ++#define IRQMCP3 2 ++#define IRQMOF 3 ++#define IRQMBO 4 ++ ++#define SCIRQS _SFR_MEM8(0xE0) ++#define IRQSCP1 0 ++#define IRQSCP2 1 ++#define IRQSCP3 2 ++#define IRQSOF 3 ++#define IRQSBO 4 ++ ++#define SCCNTLL _SFR_MEM8(0xE1) ++#define SCCNTLL0 0 ++#define SCCNTLL1 1 ++#define SCCNTLL2 2 ++#define SCCNTLL3 3 ++#define SCCNTLL4 4 ++#define SCCNTLL5 5 ++#define SCCNTLL6 6 ++#define SCCNTLL7 7 ++ ++#define SCCNTLH _SFR_MEM8(0xE2) ++#define SCCNTLH0 0 ++#define SCCNTLH1 1 ++#define SCCNTLH2 2 ++#define SCCNTLH3 3 ++#define SCCNTLH4 4 ++#define SCCNTLH5 5 ++#define SCCNTLH6 6 ++#define SCCNTLH7 7 ++ ++#define SCCNTHL _SFR_MEM8(0xE3) ++#define SCCNTHL0 0 ++#define SCCNTHL1 1 ++#define SCCNTHL2 2 ++#define SCCNTHL3 3 ++#define SCCNTHL4 4 ++#define SCCNTHL5 5 ++#define SCCNTHL6 6 ++#define SCCNTHL7 7 ++ ++#define SCCNTHH _SFR_MEM8(0xE4) ++#define SCCNTHH0 0 ++#define SCCNTHH1 1 ++#define SCCNTHH2 2 ++#define SCCNTHH3 3 ++#define SCCNTHH4 4 ++#define SCCNTHH5 5 ++#define SCCNTHH6 6 ++#define SCCNTHH7 7 ++ ++#define SCBTSRLL _SFR_MEM8(0xE5) ++#define SCBTSRLL0 0 ++#define SCBTSRLL1 1 ++#define SCBTSRLL2 2 ++#define SCBTSRLL3 3 ++#define SCBTSRLL4 4 ++#define SCBTSRLL5 5 ++#define SCBTSRLL6 6 ++#define SCBTSRLL7 7 ++ ++#define SCBTSRLH _SFR_MEM8(0xE6) ++#define SCBTSRLH0 0 ++#define SCBTSRLH1 1 ++#define SCBTSRLH2 2 ++#define SCBTSRLH3 3 ++#define SCBTSRLH4 4 ++#define SCBTSRLH5 5 ++#define SCBTSRLH6 6 ++#define SCBTSRLH7 7 ++ ++#define SCBTSRHL _SFR_MEM8(0xE7) ++#define SCBTSRHL0 0 ++#define SCBTSRHL1 1 ++#define SCBTSRHL2 2 ++#define SCBTSRHL3 3 ++#define SCBTSRHL4 4 ++#define SCBTSRHL5 5 ++#define SCBTSRHL6 6 ++#define SCBTSRHL7 7 ++ ++#define SCBTSRHH _SFR_MEM8(0xE8) ++#define SCBTSRHH0 0 ++#define SCBTSRHH1 1 ++#define SCBTSRHH2 2 ++#define SCBTSRHH3 3 ++#define SCBTSRHH4 4 ++#define SCBTSRHH5 5 ++#define SCBTSRHH6 6 ++#define SCBTSRHH7 7 ++ ++#define SCTSRLL _SFR_MEM8(0xE9) ++#define SCTSRLL0 0 ++#define SCTSRLL1 1 ++#define SCTSRLL2 2 ++#define SCTSRLL3 3 ++#define SCTSRLL4 4 ++#define SCTSRLL5 5 ++#define SCTSRLL6 6 ++#define SCTSRLL7 7 ++ ++#define SCTSRLH _SFR_MEM8(0xEA) ++#define SCTSRLH0 0 ++#define SCTSRLH1 1 ++#define SCTSRLH2 2 ++#define SCTSRLH3 3 ++#define SCTSRLH4 4 ++#define SCTSRLH5 5 ++#define SCTSRLH6 6 ++#define SCTSRLH7 7 ++ ++#define SCTSRHL _SFR_MEM8(0xEB) ++#define SCTSRHL0 0 ++#define SCTSRHL1 1 ++#define SCTSRHL2 2 ++#define SCTSRHL3 3 ++#define SCTSRHL4 4 ++#define SCTSRHL5 5 ++#define SCTSRHL6 6 ++#define SCTSRHL7 7 ++ ++#define SCTSRHH _SFR_MEM8(0xEC) ++#define SCTSRHH0 0 ++#define SCTSRHH1 1 ++#define SCTSRHH2 2 ++#define SCTSRHH3 3 ++#define SCTSRHH4 4 ++#define SCTSRHH5 5 ++#define SCTSRHH6 6 ++#define SCTSRHH7 7 ++ ++#define SCOCR3LL _SFR_MEM8(0xED) ++#define SCOCR3LL0 0 ++#define SCOCR3LL1 1 ++#define SCOCR3LL2 2 ++#define SCOCR3LL3 3 ++#define SCOCR3LL4 4 ++#define SCOCR3LL5 5 ++#define SCOCR3LL6 6 ++#define SCOCR3LL7 7 ++ ++#define SCOCR3LH _SFR_MEM8(0xEE) ++#define SCOCR3LH0 0 ++#define SCOCR3LH1 1 ++#define SCOCR3LH2 2 ++#define SCOCR3LH3 3 ++#define SCOCR3LH4 4 ++#define SCOCR3LH5 5 ++#define SCOCR3LH6 6 ++#define SCOCR3LH7 7 ++ ++#define SCOCR3HL _SFR_MEM8(0xEF) ++#define SCOCR3HL0 0 ++#define SCOCR3HL1 1 ++#define SCOCR3HL2 2 ++#define SCOCR3HL3 3 ++#define SCOCR3HL4 4 ++#define SCOCR3HL5 5 ++#define SCOCR3HL6 6 ++#define SCOCR3HL7 7 ++ ++#define SCOCR3HH _SFR_MEM8(0xF0) ++#define SCOCR3HH0 0 ++#define SCOCR3HH1 1 ++#define SCOCR3HH2 2 ++#define SCOCR3HH3 3 ++#define SCOCR3HH4 4 ++#define SCOCR3HH5 5 ++#define SCOCR3HH6 6 ++#define SCOCR3HH7 7 ++ ++#define SCOCR2LL _SFR_MEM8(0xF1) ++#define SCOCR2LL0 0 ++#define SCOCR2LL1 1 ++#define SCOCR2LL2 2 ++#define SCOCR2LL3 3 ++#define SCOCR2LL4 4 ++#define SCOCR2LL5 5 ++#define SCOCR2LL6 6 ++#define SCOCR2LL7 7 ++ ++#define SCOCR2LH _SFR_MEM8(0xF2) ++#define SCOCR2LH0 0 ++#define SCOCR2LH1 1 ++#define SCOCR2LH2 2 ++#define SCOCR2LH3 3 ++#define SCOCR2LH4 4 ++#define SCOCR2LH5 5 ++#define SCOCR2LH6 6 ++#define SCOCR2LH7 7 ++ ++#define SCOCR2HL _SFR_MEM8(0xF3) ++#define SCOCR2HL0 0 ++#define SCOCR2HL1 1 ++#define SCOCR2HL2 2 ++#define SCOCR2HL3 3 ++#define SCOCR2HL4 4 ++#define SCOCR2HL5 5 ++#define SCOCR2HL6 6 ++#define SCOCR2HL7 7 ++ ++#define SCOCR2HH _SFR_MEM8(0xF4) ++#define SCOCR2HH0 0 ++#define SCOCR2HH1 1 ++#define SCOCR2HH2 2 ++#define SCOCR2HH3 3 ++#define SCOCR2HH4 4 ++#define SCOCR2HH5 5 ++#define SCOCR2HH6 6 ++#define SCOCR2HH7 7 ++ ++#define SCOCR1LL _SFR_MEM8(0xF5) ++#define SCOCR1LL0 0 ++#define SCOCR1LL1 1 ++#define SCOCR1LL2 2 ++#define SCOCR1LL3 3 ++#define SCOCR1LL4 4 ++#define SCOCR1LL5 5 ++#define SCOCR1LL6 6 ++#define SCOCR1LL7 7 ++ ++#define SCOCR1LH _SFR_MEM8(0xF6) ++#define SCOCR1LH0 0 ++#define SCOCR1LH1 1 ++#define SCOCR1LH2 2 ++#define SCOCR1LH3 3 ++#define SCOCR1LH4 4 ++#define SCOCR1LH5 5 ++#define SCOCR1LH6 6 ++#define SCOCR1LH7 7 ++ ++#define SCOCR1HL _SFR_MEM8(0xF7) ++#define SCOCR1HL0 0 ++#define SCOCR1HL1 1 ++#define SCOCR1HL2 2 ++#define SCOCR1HL3 3 ++#define SCOCR1HL4 4 ++#define SCOCR1HL5 5 ++#define SCOCR1HL6 6 ++#define SCOCR1HL7 7 ++ ++#define SCOCR1HH _SFR_MEM8(0xF8) ++#define SCOCR1HH0 0 ++#define SCOCR1HH1 1 ++#define SCOCR1HH2 2 ++#define SCOCR1HH3 3 ++#define SCOCR1HH4 4 ++#define SCOCR1HH5 5 ++#define SCOCR1HH6 6 ++#define SCOCR1HH7 7 ++ ++#define SCTSTRLL _SFR_MEM8(0xF9) ++#define SCTSTRLL0 0 ++#define SCTSTRLL1 1 ++#define SCTSTRLL2 2 ++#define SCTSTRLL3 3 ++#define SCTSTRLL4 4 ++#define SCTSTRLL5 5 ++#define SCTSTRLL6 6 ++#define SCTSTRLL7 7 ++ ++#define SCTSTRLH _SFR_MEM8(0xFA) ++#define SCTSTRLH0 0 ++#define SCTSTRLH1 1 ++#define SCTSTRLH2 2 ++#define SCTSTRLH3 3 ++#define SCTSTRLH4 4 ++#define SCTSTRLH5 5 ++#define SCTSTRLH6 6 ++#define SCTSTRLH7 7 ++ ++#define SCTSTRHL _SFR_MEM8(0xFB) ++#define SCTSTRHL0 0 ++#define SCTSTRHL1 1 ++#define SCTSTRHL2 2 ++#define SCTSTRHL3 3 ++#define SCTSTRHL4 4 ++#define SCTSTRHL5 5 ++#define SCTSTRHL6 6 ++#define SCTSTRHL7 7 ++ ++#define SCTSTRHH _SFR_MEM8(0xFC) ++#define SCTSTRHH0 0 ++#define SCTSTRHH1 1 ++#define SCTSTRHH2 2 ++#define SCTSTRHH3 3 ++#define SCTSTRHH4 4 ++#define SCTSTRHH5 5 ++#define SCTSTRHH6 6 ++#define SCTSTRHH7 7 ++ ++/* Reserved [0xFD..0x10B] */ ++ ++#define MAFCR0 _SFR_MEM8(0x10C) ++#define MAF0EN 0 ++#define MAF1EN 1 ++#define MAF2EN 2 ++#define MAF3EN 3 ++ ++#define MAFCR1 _SFR_MEM8(0x10D) ++#define AACK_0_I_AM_COORD 0 ++#define AACK_0_SET_PD 1 ++#define AACK_1_I_AM_COORD 2 ++#define AACK_1_SET_PD 3 ++#define AACK_2_I_AM_COORD 4 ++#define AACK_2_SET_PD 5 ++#define AACK_3_I_AM_COORD 6 ++#define AACK_3_SET_PD 7 ++ ++#define MAFSA0L _SFR_MEM8(0x10E) ++#define MAFSA0L0 0 ++#define MAFSA0L1 1 ++#define MAFSA0L2 2 ++#define MAFSA0L3 3 ++#define MAFSA0L4 4 ++#define MAFSA0L5 5 ++#define MAFSA0L6 6 ++#define MAFSA0L7 7 ++ ++#define MAFSA0H _SFR_MEM8(0x10F) ++#define MAFSA0H0 0 ++#define MAFSA0H1 1 ++#define MAFSA0H2 2 ++#define MAFSA0H3 3 ++#define MAFSA0H4 4 ++#define MAFSA0H5 5 ++#define MAFSA0H6 6 ++#define MAFSA0H7 7 ++ ++#define MAFPA0L _SFR_MEM8(0x110) ++#define MAFPA0L0 0 ++#define MAFPA0L1 1 ++#define MAFPA0L2 2 ++#define MAFPA0L3 3 ++#define MAFPA0L4 4 ++#define MAFPA0L5 5 ++#define MAFPA0L6 6 ++#define MAFPA0L7 7 ++ ++#define MAFPA0H _SFR_MEM8(0x111) ++#define MAFPA0H0 0 ++#define MAFPA0H1 1 ++#define MAFPA0H2 2 ++#define MAFPA0H3 3 ++#define MAFPA0H4 4 ++#define MAFPA0H5 5 ++#define MAFPA0H6 6 ++#define MAFPA0H7 7 ++ ++#define MAFSA1L _SFR_MEM8(0x112) ++#define MAFSA1L0 0 ++#define MAFSA1L1 1 ++#define MAFSA1L2 2 ++#define MAFSA1L3 3 ++#define MAFSA1L4 4 ++#define MAFSA1L5 5 ++#define MAFSA1L6 6 ++#define MAFSA1L7 7 ++ ++#define MAFSA1H _SFR_MEM8(0x113) ++#define MAFSA1H0 0 ++#define MAFSA1H1 1 ++#define MAFSA1H2 2 ++#define MAFSA1H3 3 ++#define MAFSA1H4 4 ++#define MAFSA1H5 5 ++#define MAFSA1H6 6 ++#define MAFSA1H7 7 ++ ++#define MAFPA1L _SFR_MEM8(0x114) ++#define MAFPA1L0 0 ++#define MAFPA1L1 1 ++#define MAFPA1L2 2 ++#define MAFPA1L3 3 ++#define MAFPA1L4 4 ++#define MAFPA1L5 5 ++#define MAFPA1L6 6 ++#define MAFPA1L7 7 ++ ++#define MAFPA1H _SFR_MEM8(0x115) ++#define MAFPA1H0 0 ++#define MAFPA1H1 1 ++#define MAFPA1H2 2 ++#define MAFPA1H3 3 ++#define MAFPA1H4 4 ++#define MAFPA1H5 5 ++#define MAFPA1H6 6 ++#define MAFPA1H7 7 ++ ++#define MAFSA2L _SFR_MEM8(0x116) ++#define MAFSA2L0 0 ++#define MAFSA2L1 1 ++#define MAFSA2L2 2 ++#define MAFSA2L3 3 ++#define MAFSA2L4 4 ++#define MAFSA2L5 5 ++#define MAFSA2L6 6 ++#define MAFSA2L7 7 ++ ++#define MAFSA2H _SFR_MEM8(0x117) ++#define MAFSA2H0 0 ++#define MAFSA2H1 1 ++#define MAFSA2H2 2 ++#define MAFSA2H3 3 ++#define MAFSA2H4 4 ++#define MAFSA2H5 5 ++#define MAFSA2H6 6 ++#define MAFSA2H7 7 ++ ++#define MAFPA2L _SFR_MEM8(0x118) ++#define MAFPA2L0 0 ++#define MAFPA2L1 1 ++#define MAFPA2L2 2 ++#define MAFPA2L3 3 ++#define MAFPA2L4 4 ++#define MAFPA2L5 5 ++#define MAFPA2L6 6 ++#define MAFPA2L7 7 ++ ++#define MAFPA2H _SFR_MEM8(0x119) ++#define MAFPA2H0 0 ++#define MAFPA2H1 1 ++#define MAFPA2H2 2 ++#define MAFPA2H3 3 ++#define MAFPA2H4 4 ++#define MAFPA2H5 5 ++#define MAFPA2H6 6 ++#define MAFPA2H7 7 ++ ++#define MAFSA3L _SFR_MEM8(0x11A) ++#define MAFSA3L0 0 ++#define MAFSA3L1 1 ++#define MAFSA3L2 2 ++#define MAFSA3L3 3 ++#define MAFSA3L4 4 ++#define MAFSA3L5 5 ++#define MAFSA3L6 6 ++#define MAFSA3L7 7 ++ ++#define MAFSA3H _SFR_MEM8(0x11B) ++#define MAFSA3H0 0 ++#define MAFSA3H1 1 ++#define MAFSA3H2 2 ++#define MAFSA3H3 3 ++#define MAFSA3H4 4 ++#define MAFSA3H5 5 ++#define MAFSA3H6 6 ++#define MAFSA3H7 7 ++ ++#define MAFPA3L _SFR_MEM8(0x11C) ++#define MAFPA3L0 0 ++#define MAFPA3L1 1 ++#define MAFPA3L2 2 ++#define MAFPA3L3 3 ++#define MAFPA3L4 4 ++#define MAFPA3L5 5 ++#define MAFPA3L6 6 ++#define MAFPA3L7 7 ++ ++#define MAFPA3H _SFR_MEM8(0x11D) ++#define MAFPA3H0 0 ++#define MAFPA3H1 1 ++#define MAFPA3H2 2 ++#define MAFPA3H3 3 ++#define MAFPA3H4 4 ++#define MAFPA3H5 5 ++#define MAFPA3H6 6 ++#define MAFPA3H7 7 ++ ++/* Reserved [0x11E..0x11F] */ ++ ++#define TCCR5A _SFR_MEM8(0x120) ++#define WGM50 0 ++#define WGM51 1 ++#define COM5C0 2 ++#define COM5C1 3 ++#define COM5B0 4 ++#define COM5B1 5 ++#define COM5A0 6 ++#define COM5A1 7 ++ ++#define TCCR5B _SFR_MEM8(0x121) ++#define CS50 0 ++#define CS51 1 ++#define CS52 2 ++#define WGM52 3 ++#define WGM53 4 ++#define ICES5 6 ++#define ICNC5 7 ++ ++#define TCCR5C _SFR_MEM8(0x122) ++#define FOC5C 5 ++#define FOC5B 6 ++#define FOC5A 7 ++ ++/* Reserved [0x123] */ ++ ++/* Combine TCNT5L and TCNT5H */ ++#define TCNT5 _SFR_MEM16(0x124) ++ ++#define TCNT5L _SFR_MEM8(0x124) ++#define TCNT5H _SFR_MEM8(0x125) ++ ++/* Combine ICR5L and ICR5H */ ++#define ICR5 _SFR_MEM16(0x126) ++ ++#define ICR5L _SFR_MEM8(0x126) ++#define ICR5H _SFR_MEM8(0x127) ++ ++/* Combine OCR5AL and OCR5AH */ ++#define OCR5A _SFR_MEM16(0x128) ++ ++#define OCR5AL _SFR_MEM8(0x128) ++#define OCR5AH _SFR_MEM8(0x129) ++ ++/* Combine OCR5BL and OCR5BH */ ++#define OCR5B _SFR_MEM16(0x12A) ++ ++#define OCR5BL _SFR_MEM8(0x12A) ++#define OCR5BH _SFR_MEM8(0x12B) ++ ++/* Combine OCR5CL and OCR5CH */ ++#define OCR5C _SFR_MEM16(0x12C) ++ ++#define OCR5CL _SFR_MEM8(0x12C) ++#define OCR5CH _SFR_MEM8(0x12D) ++ ++/* Reserved [0x12E] */ ++ ++#define LLCR _SFR_MEM8(0x12F) ++#define LLENCAL 0 ++#define LLSHORT 1 ++#define LLTCO 2 ++#define LLCAL 3 ++#define LLCOMP 4 ++#define LLDONE 5 ++ ++#define LLDRL _SFR_MEM8(0x130) ++#define LLDRL0 0 ++#define LLDRL1 1 ++#define LLDRL2 2 ++#define LLDRL3 3 ++ ++#define LLDRH _SFR_MEM8(0x131) ++#define LLDRH0 0 ++#define LLDRH1 1 ++#define LLDRH2 2 ++#define LLDRH3 3 ++#define LLDRH4 4 ++ ++#define DRTRAM3 _SFR_MEM8(0x132) ++#define ENDRT 4 ++#define DRTSWOK 5 ++ ++#define DRTRAM2 _SFR_MEM8(0x133) ++ ++#define DRTRAM1 _SFR_MEM8(0x134) ++ ++#define DRTRAM0 _SFR_MEM8(0x135) ++ ++#define DPDS0 _SFR_MEM8(0x136) ++#define PBDRV0 0 ++#define PBDRV1 1 ++#define PDDRV0 2 ++#define PDDRV1 3 ++#define PEDRV0 4 ++#define PEDRV1 5 ++#define PFDRV0 6 ++#define PFDRV1 7 ++ ++#define DPDS1 _SFR_MEM8(0x137) ++#define PGDRV0 0 ++#define PGDRV1 1 ++ ++#define PARCR _SFR_MEM8(0x138) ++#define PARUFI 0 ++#define PARDFI 1 ++#define PALTU0 2 ++#define PALTU1 3 ++#define PALTU2 4 ++#define PALTD0 5 ++#define PALTD1 6 ++#define PALTD2 7 ++ ++#define TRXPR _SFR_MEM8(0x139) ++#define TRXRST 0 ++#define SLPTR 1 ++ ++/* Reserved [0x13A..0x13B] */ ++ ++#define AES_CTRL _SFR_MEM8(0x13C) ++#define AES_IM 2 ++#define AES_DIR 3 ++#define AES_MODE 5 ++#define AES_REQUEST 7 ++ ++#define AES_STATUS _SFR_MEM8(0x13D) ++#define AES_DONE 0 ++#define AES_ER 7 ++ ++#define AES_STATE _SFR_MEM8(0x13E) ++#define AES_STATE0 0 ++#define AES_STATE1 1 ++#define AES_STATE2 2 ++#define AES_STATE3 3 ++#define AES_STATE4 4 ++#define AES_STATE5 5 ++#define AES_STATE6 6 ++#define AES_STATE7 7 ++ ++#define AES_KEY _SFR_MEM8(0x13F) ++#define AES_KEY0 0 ++#define AES_KEY1 1 ++#define AES_KEY2 2 ++#define AES_KEY3 3 ++#define AES_KEY4 4 ++#define AES_KEY5 5 ++#define AES_KEY6 6 ++#define AES_KEY7 7 ++ ++/* Reserved [0x140] */ ++ ++#define TRX_STATUS _SFR_MEM8(0x141) ++#define TRX_STATUS0 0 ++#define TRX_STATUS1 1 ++#define TRX_STATUS2 2 ++#define TRX_STATUS3 3 ++#define TRX_STATUS4 4 ++#define TST_STATUS 5 ++#define CCA_STATUS 6 ++#define CCA_DONE 7 ++ ++#define TRX_STATE _SFR_MEM8(0x142) ++#define TRX_CMD0 0 ++#define TRX_CMD1 1 ++#define TRX_CMD2 2 ++#define TRX_CMD3 3 ++#define TRX_CMD4 4 ++#define TRAC_STATUS0 5 ++#define TRAC_STATUS1 6 ++#define TRAC_STATUS2 7 ++ ++#define TRX_CTRL_0 _SFR_MEM8(0x143) ++#define PMU_IF_INV 4 ++#define PMU_START 5 ++#define PMU_EN 6 ++#define Res7 7 ++ ++#define TRX_CTRL_1 _SFR_MEM8(0x144) ++#define PLL_TX_FLT 4 ++#define TX_AUTO_CRC_ON 5 ++#define IRQ_2_EXT_EN 6 ++#define PA_EXT_EN 7 ++ ++#define PHY_TX_PWR _SFR_MEM8(0x145) ++#define TX_PWR0 0 ++#define TX_PWR1 1 ++#define TX_PWR2 2 ++#define TX_PWR3 3 ++ ++#define PHY_RSSI _SFR_MEM8(0x146) ++#define RSSI0 0 ++#define RSSI1 1 ++#define RSSI2 2 ++#define RSSI3 3 ++#define RSSI4 4 ++#define RND_VALUE0 5 ++#define RND_VALUE1 6 ++#define RX_CRC_VALID 7 ++ ++#define PHY_ED_LEVEL _SFR_MEM8(0x147) ++#define ED_LEVEL0 0 ++#define ED_LEVEL1 1 ++#define ED_LEVEL2 2 ++#define ED_LEVEL3 3 ++#define ED_LEVEL4 4 ++#define ED_LEVEL5 5 ++#define ED_LEVEL6 6 ++#define ED_LEVEL7 7 ++ ++#define PHY_CC_CCA _SFR_MEM8(0x148) ++#define CHANNEL0 0 ++#define CHANNEL1 1 ++#define CHANNEL2 2 ++#define CHANNEL3 3 ++#define CHANNEL4 4 ++#define CCA_MODE0 5 ++#define CCA_MODE1 6 ++#define CCA_REQUEST 7 ++ ++#define CCA_THRES _SFR_MEM8(0x149) ++#define CCA_ED_THRES0 0 ++#define CCA_ED_THRES1 1 ++#define CCA_ED_THRES2 2 ++#define CCA_ED_THRES3 3 ++#define CCA_CS_THRES0 4 ++#define CCA_CS_THRES1 5 ++#define CCA_CS_THRES2 6 ++#define CCA_CS_THRES3 7 ++ ++#define RX_CTRL _SFR_MEM8(0x14A) ++#define PDT_THRES0 0 ++#define PDT_THRES1 1 ++#define PDT_THRES2 2 ++#define PDT_THRES3 3 ++ ++#define SFD_VALUE _SFR_MEM8(0x14B) ++#define SFD_VALUE0 0 ++#define SFD_VALUE1 1 ++#define SFD_VALUE2 2 ++#define SFD_VALUE3 3 ++#define SFD_VALUE4 4 ++#define SFD_VALUE5 5 ++#define SFD_VALUE6 6 ++#define SFD_VALUE7 7 ++ ++#define TRX_CTRL_2 _SFR_MEM8(0x14C) ++#define OQPSK_DATA_RATE0 0 ++#define OQPSK_DATA_RATE1 1 ++#define RX_SAFE_MODE 7 ++ ++#define ANT_DIV _SFR_MEM8(0x14D) ++#define ANT_CTRL0 0 ++#define ANT_CTRL1 1 ++#define ANT_EXT_SW_EN 2 ++#define ANT_DIV_EN 3 ++#define ANT_SEL 7 ++ ++#define IRQ_MASK _SFR_MEM8(0x14E) ++#define PLL_LOCK_EN 0 ++#define PLL_UNLOCK_EN 1 ++#define RX_START_EN 2 ++#define RX_END_EN 3 ++#define CCA_ED_DONE_EN 4 ++#define AMI_EN 5 ++#define TX_END_EN 6 ++#define AWAKE_EN 7 ++ ++#define IRQ_STATUS _SFR_MEM8(0x14F) ++#define PLL_LOCK 0 ++#define PLL_UNLOCK 1 ++#define RX_START 2 ++#define RX_END 3 ++#define CCA_ED_DONE 4 ++#define AMI 5 ++#define TX_END 6 ++#define AWAKE 7 ++ ++#define VREG_CTRL _SFR_MEM8(0x150) ++#define DVDD_OK 2 ++#define DVREG_EXT 3 ++#define AVDD_OK 6 ++#define AVREG_EXT 7 ++ ++#define BATMON _SFR_MEM8(0x151) ++#define BATMON_VTH0 0 ++#define BATMON_VTH1 1 ++#define BATMON_VTH2 2 ++#define BATMON_VTH3 3 ++#define BATMON_HR 4 ++#define BATMON_OK 5 ++#define BAT_LOW_EN 6 ++#define BAT_LOW 7 ++ ++#define XOSC_CTRL _SFR_MEM8(0x152) ++#define XTAL_TRIM0 0 ++#define XTAL_TRIM1 1 ++#define XTAL_TRIM2 2 ++#define XTAL_TRIM3 3 ++#define XTAL_MODE0 4 ++#define XTAL_MODE1 5 ++#define XTAL_MODE2 6 ++#define XTAL_MODE3 7 ++ ++#define CC_CTRL_0 _SFR_MEM8(0x153) ++#define CC_NUMBER0 0 ++#define CC_NUMBER1 1 ++#define CC_NUMBER2 2 ++#define CC_NUMBER3 3 ++#define CC_NUMBER4 4 ++#define CC_NUMBER5 5 ++#define CC_NUMBER6 6 ++#define CC_NUMBER7 7 ++ ++#define CC_CTRL_1 _SFR_MEM8(0x154) ++#define CC_BAND0 0 ++#define CC_BAND1 1 ++#define CC_BAND2 2 ++#define CC_BAND3 3 ++ ++#define RX_SYN _SFR_MEM8(0x155) ++#define RX_PDT_LEVEL0 0 ++#define RX_PDT_LEVEL1 1 ++#define RX_PDT_LEVEL2 2 ++#define RX_PDT_LEVEL3 3 ++#define RX_OVERRIDE 6 ++#define RX_PDT_DIS 7 ++ ++#define TRX_RPC _SFR_MEM8(0x156) ++#define XAH_RPC_EN 0 ++#define IPAN_RPC_EN 1 ++#define PLL_RPC_EN 3 ++#define PDT_RPC_EN 4 ++#define RX_RPC_EN 5 ++#define RX_RPC_CTRL0 6 ++#define RX_RPC_CTRL1 7 ++ ++#define XAH_CTRL_1 _SFR_MEM8(0x157) ++#define AACK_PROM_MODE 1 ++#define AACK_ACK_TIME 2 ++#define AACK_UPLD_RES_FT 4 ++#define AACK_FLTR_RES_FT 5 ++ ++#define FTN_CTRL _SFR_MEM8(0x158) ++#define FTN_START 7 ++ ++/* Reserved [0x159] */ ++ ++#define PLL_CF _SFR_MEM8(0x15A) ++#define PLL_CF_START 7 ++ ++#define PLL_DCU _SFR_MEM8(0x15B) ++#define PLL_DCU_START 7 ++ ++#define PART_NUM _SFR_MEM8(0x15C) ++#define PART_NUM0 0 ++#define PART_NUM1 1 ++#define PART_NUM2 2 ++#define PART_NUM3 3 ++#define PART_NUM4 4 ++#define PART_NUM5 5 ++#define PART_NUM6 6 ++#define PART_NUM7 7 ++ ++#define VERSION_NUM _SFR_MEM8(0x15D) ++#define VERSION_NUM0 0 ++#define VERSION_NUM1 1 ++#define VERSION_NUM2 2 ++#define VERSION_NUM3 3 ++#define VERSION_NUM4 4 ++#define VERSION_NUM5 5 ++#define VERSION_NUM6 6 ++#define VERSION_NUM7 7 ++ ++#define MAN_ID_0 _SFR_MEM8(0x15E) ++#define MAN_ID_00 0 ++#define MAN_ID_01 1 ++#define MAN_ID_02 2 ++#define MAN_ID_03 3 ++#define MAN_ID_04 4 ++#define MAN_ID_05 5 ++#define MAN_ID_06 6 ++#define MAN_ID_07 7 ++ ++#define MAN_ID_1 _SFR_MEM8(0x15F) ++#define MAN_ID_10 0 ++#define MAN_ID_11 1 ++#define MAN_ID_12 2 ++#define MAN_ID_13 3 ++#define MAN_ID_14 4 ++#define MAN_ID_15 5 ++#define MAN_ID_16 6 ++#define MAN_ID_17 7 ++ ++#define SHORT_ADDR_0 _SFR_MEM8(0x160) ++#define SHORT_ADDR_00 0 ++#define SHORT_ADDR_01 1 ++#define SHORT_ADDR_02 2 ++#define SHORT_ADDR_03 3 ++#define SHORT_ADDR_04 4 ++#define SHORT_ADDR_05 5 ++#define SHORT_ADDR_06 6 ++#define SHORT_ADDR_07 7 ++ ++#define SHORT_ADDR_1 _SFR_MEM8(0x161) ++#define SHORT_ADDR_10 0 ++#define SHORT_ADDR_11 1 ++#define SHORT_ADDR_12 2 ++#define SHORT_ADDR_13 3 ++#define SHORT_ADDR_14 4 ++#define SHORT_ADDR_15 5 ++#define SHORT_ADDR_16 6 ++#define SHORT_ADDR_17 7 ++ ++#define PAN_ID_0 _SFR_MEM8(0x162) ++#define PAN_ID_00 0 ++#define PAN_ID_01 1 ++#define PAN_ID_02 2 ++#define PAN_ID_03 3 ++#define PAN_ID_04 4 ++#define PAN_ID_05 5 ++#define PAN_ID_06 6 ++#define PAN_ID_07 7 ++ ++#define PAN_ID_1 _SFR_MEM8(0x163) ++#define PAN_ID_10 0 ++#define PAN_ID_11 1 ++#define PAN_ID_12 2 ++#define PAN_ID_13 3 ++#define PAN_ID_14 4 ++#define PAN_ID_15 5 ++#define PAN_ID_16 6 ++#define PAN_ID_17 7 ++ ++#define IEEE_ADDR_0 _SFR_MEM8(0x164) ++#define IEEE_ADDR_00 0 ++#define IEEE_ADDR_01 1 ++#define IEEE_ADDR_02 2 ++#define IEEE_ADDR_03 3 ++#define IEEE_ADDR_04 4 ++#define IEEE_ADDR_05 5 ++#define IEEE_ADDR_06 6 ++#define IEEE_ADDR_07 7 ++ ++#define IEEE_ADDR_1 _SFR_MEM8(0x165) ++#define IEEE_ADDR_10 0 ++#define IEEE_ADDR_11 1 ++#define IEEE_ADDR_12 2 ++#define IEEE_ADDR_13 3 ++#define IEEE_ADDR_14 4 ++#define IEEE_ADDR_15 5 ++#define IEEE_ADDR_16 6 ++#define IEEE_ADDR_17 7 ++ ++#define IEEE_ADDR_2 _SFR_MEM8(0x166) ++#define IEEE_ADDR_20 0 ++#define IEEE_ADDR_21 1 ++#define IEEE_ADDR_22 2 ++#define IEEE_ADDR_23 3 ++#define IEEE_ADDR_24 4 ++#define IEEE_ADDR_25 5 ++#define IEEE_ADDR_26 6 ++#define IEEE_ADDR_27 7 ++ ++#define IEEE_ADDR_3 _SFR_MEM8(0x167) ++#define IEEE_ADDR_30 0 ++#define IEEE_ADDR_31 1 ++#define IEEE_ADDR_32 2 ++#define IEEE_ADDR_33 3 ++#define IEEE_ADDR_34 4 ++#define IEEE_ADDR_35 5 ++#define IEEE_ADDR_36 6 ++#define IEEE_ADDR_37 7 ++ ++#define IEEE_ADDR_4 _SFR_MEM8(0x168) ++#define IEEE_ADDR_40 0 ++#define IEEE_ADDR_41 1 ++#define IEEE_ADDR_42 2 ++#define IEEE_ADDR_43 3 ++#define IEEE_ADDR_44 4 ++#define IEEE_ADDR_45 5 ++#define IEEE_ADDR_46 6 ++#define IEEE_ADDR_47 7 ++ ++#define IEEE_ADDR_5 _SFR_MEM8(0x169) ++#define IEEE_ADDR_50 0 ++#define IEEE_ADDR_51 1 ++#define IEEE_ADDR_52 2 ++#define IEEE_ADDR_53 3 ++#define IEEE_ADDR_54 4 ++#define IEEE_ADDR_55 5 ++#define IEEE_ADDR_56 6 ++#define IEEE_ADDR_57 7 ++ ++#define IEEE_ADDR_6 _SFR_MEM8(0x16A) ++#define IEEE_ADDR_60 0 ++#define IEEE_ADDR_61 1 ++#define IEEE_ADDR_62 2 ++#define IEEE_ADDR_63 3 ++#define IEEE_ADDR_64 4 ++#define IEEE_ADDR_65 5 ++#define IEEE_ADDR_66 6 ++#define IEEE_ADDR_67 7 ++ ++#define IEEE_ADDR_7 _SFR_MEM8(0x16B) ++#define IEEE_ADDR_70 0 ++#define IEEE_ADDR_71 1 ++#define IEEE_ADDR_72 2 ++#define IEEE_ADDR_73 3 ++#define IEEE_ADDR_74 4 ++#define IEEE_ADDR_75 5 ++#define IEEE_ADDR_76 6 ++#define IEEE_ADDR_77 7 ++ ++#define XAH_CTRL_0 _SFR_MEM8(0x16C) ++#define SLOTTED_OPERATION 0 ++#define MAX_CSMA_RETRIES0 1 ++#define MAX_CSMA_RETRIES1 2 ++#define MAX_CSMA_RETRIES2 3 ++#define MAX_FRAME_RETRIES0 4 ++#define MAX_FRAME_RETRIES1 5 ++#define MAX_FRAME_RETRIES2 6 ++#define MAX_FRAME_RETRIES3 7 ++ ++#define CSMA_SEED_0 _SFR_MEM8(0x16D) ++#define CSMA_SEED_00 0 ++#define CSMA_SEED_01 1 ++#define CSMA_SEED_02 2 ++#define CSMA_SEED_03 3 ++#define CSMA_SEED_04 4 ++#define CSMA_SEED_05 5 ++#define CSMA_SEED_06 6 ++#define CSMA_SEED_07 7 ++ ++#define CSMA_SEED_1 _SFR_MEM8(0x16E) ++#define CSMA_SEED_10 0 ++#define CSMA_SEED_11 1 ++#define CSMA_SEED_12 2 ++#define AACK_I_AM_COORD 3 ++#define AACK_DIS_ACK 4 ++#define AACK_SET_PD 5 ++#define AACK_FVN_MODE0 6 ++#define AACK_FVN_MODE1 7 ++ ++#define CSMA_BE _SFR_MEM8(0x16F) ++#define MIN_BE0 0 ++#define MIN_BE1 1 ++#define MIN_BE2 2 ++#define MIN_BE3 3 ++#define MAX_BE0 4 ++#define MAX_BE1 5 ++#define MAX_BE2 6 ++#define MAX_BE3 7 ++ ++/* Reserved [0x170..0x175] */ ++ ++#define TST_CTRL_DIGI _SFR_MEM8(0x176) ++#define TST_CTRL_DIG0 0 ++#define TST_CTRL_DIG1 1 ++#define TST_CTRL_DIG2 2 ++#define TST_CTRL_DIG3 3 ++ ++/* Reserved [0x177..0x17A] */ ++ ++#define TST_RX_LENGTH _SFR_MEM8(0x17B) ++#define RX_LENGTH0 0 ++#define RX_LENGTH1 1 ++#define RX_LENGTH2 2 ++#define RX_LENGTH3 3 ++#define RX_LENGTH4 4 ++#define RX_LENGTH5 5 ++#define RX_LENGTH6 6 ++#define RX_LENGTH7 7 ++ ++/* Reserved [0x17C..0x17F] */ ++ ++#define TRXFBST _SFR_MEM8(0x180) ++ ++/* Reserved [0x181..0x1FE] */ ++ ++#define TRXFBEND _SFR_MEM8(0x1FF) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect _VECTOR(3) ++#define INT2_vect_num 3 ++ ++/* External Interrupt Request 3 */ ++#define INT3_vect _VECTOR(4) ++#define INT3_vect_num 4 ++ ++/* External Interrupt Request 4 */ ++#define INT4_vect _VECTOR(5) ++#define INT4_vect_num 5 ++ ++/* External Interrupt Request 5 */ ++#define INT5_vect _VECTOR(6) ++#define INT5_vect_num 6 ++ ++/* External Interrupt Request 6 */ ++#define INT6_vect _VECTOR(7) ++#define INT6_vect_num 7 ++ ++/* External Interrupt Request 7 */ ++#define INT7_vect _VECTOR(8) ++#define INT7_vect_num 8 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(9) ++#define PCINT0_vect_num 9 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(10) ++#define PCINT1_vect_num 10 ++ ++/* Pin Change Interrupt Request 2 */ ++#define PCINT2_vect _VECTOR(11) ++#define PCINT2_vect_num 11 ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect _VECTOR(12) ++#define WDT_vect_num 12 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPA_vect _VECTOR(13) ++#define TIMER2_COMPA_vect_num 13 ++ ++/* Timer/Counter2 Compare Match B */ ++#define TIMER2_COMPB_vect _VECTOR(14) ++#define TIMER2_COMPB_vect_num 14 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(15) ++#define TIMER2_OVF_vect_num 15 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(16) ++#define TIMER1_CAPT_vect_num 16 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(17) ++#define TIMER1_COMPA_vect_num 17 ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(18) ++#define TIMER1_COMPB_vect_num 18 ++ ++/* Timer/Counter1 Compare Match C */ ++#define TIMER1_COMPC_vect _VECTOR(19) ++#define TIMER1_COMPC_vect_num 19 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(20) ++#define TIMER1_OVF_vect_num 20 ++ ++/* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPA_vect _VECTOR(21) ++#define TIMER0_COMPA_vect_num 21 ++ ++/* Timer/Counter0 Compare Match B */ ++#define TIMER0_COMPB_vect _VECTOR(22) ++#define TIMER0_COMPB_vect_num 22 ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(23) ++#define TIMER0_OVF_vect_num 23 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(24) ++#define SPI_STC_vect_num 24 ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect _VECTOR(25) ++#define USART0_RX_vect_num 25 ++ ++/* USART0 Data register Empty */ ++#define USART0_UDRE_vect _VECTOR(26) ++#define USART0_UDRE_vect_num 26 ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect _VECTOR(27) ++#define USART0_TX_vect_num 27 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(28) ++#define ANALOG_COMP_vect_num 28 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(29) ++#define ADC_vect_num 29 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(30) ++#define EE_READY_vect_num 30 ++ ++/* Timer/Counter3 Capture Event */ ++#define TIMER3_CAPT_vect _VECTOR(31) ++#define TIMER3_CAPT_vect_num 31 ++ ++/* Timer/Counter3 Compare Match A */ ++#define TIMER3_COMPA_vect _VECTOR(32) ++#define TIMER3_COMPA_vect_num 32 ++ ++/* Timer/Counter3 Compare Match B */ ++#define TIMER3_COMPB_vect _VECTOR(33) ++#define TIMER3_COMPB_vect_num 33 ++ ++/* Timer/Counter3 Compare Match C */ ++#define TIMER3_COMPC_vect _VECTOR(34) ++#define TIMER3_COMPC_vect_num 34 ++ ++/* Timer/Counter3 Overflow */ ++#define TIMER3_OVF_vect _VECTOR(35) ++#define TIMER3_OVF_vect_num 35 ++ ++/* USART1, Rx Complete */ ++#define USART1_RX_vect _VECTOR(36) ++#define USART1_RX_vect_num 36 ++ ++/* USART1 Data register Empty */ ++#define USART1_UDRE_vect _VECTOR(37) ++#define USART1_UDRE_vect_num 37 ++ ++/* USART1, Tx Complete */ ++#define USART1_TX_vect _VECTOR(38) ++#define USART1_TX_vect_num 38 ++ ++/* 2-wire Serial Interface */ ++#define TWI_vect _VECTOR(39) ++#define TWI_vect_num 39 ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect _VECTOR(40) ++#define SPM_READY_vect_num 40 ++ ++/* Timer/Counter4 Capture Event */ ++#define TIMER4_CAPT_vect _VECTOR(41) ++#define TIMER4_CAPT_vect_num 41 ++ ++/* Timer/Counter4 Compare Match A */ ++#define TIMER4_COMPA_vect _VECTOR(42) ++#define TIMER4_COMPA_vect_num 42 ++ ++/* Timer/Counter4 Compare Match B */ ++#define TIMER4_COMPB_vect _VECTOR(43) ++#define TIMER4_COMPB_vect_num 43 ++ ++/* Timer/Counter4 Compare Match C */ ++#define TIMER4_COMPC_vect _VECTOR(44) ++#define TIMER4_COMPC_vect_num 44 ++ ++/* Timer/Counter4 Overflow */ ++#define TIMER4_OVF_vect _VECTOR(45) ++#define TIMER4_OVF_vect_num 45 ++ ++/* Timer/Counter5 Capture Event */ ++#define TIMER5_CAPT_vect _VECTOR(46) ++#define TIMER5_CAPT_vect_num 46 ++ ++/* Timer/Counter5 Compare Match A */ ++#define TIMER5_COMPA_vect _VECTOR(47) ++#define TIMER5_COMPA_vect_num 47 ++ ++/* Timer/Counter5 Compare Match B */ ++#define TIMER5_COMPB_vect _VECTOR(48) ++#define TIMER5_COMPB_vect_num 48 ++ ++/* Timer/Counter5 Compare Match C */ ++#define TIMER5_COMPC_vect _VECTOR(49) ++#define TIMER5_COMPC_vect_num 49 ++ ++/* Timer/Counter5 Overflow */ ++#define TIMER5_OVF_vect _VECTOR(50) ++#define TIMER5_OVF_vect_num 50 ++ ++/* TRX24 - PLL lock interrupt */ ++#define TRX24_PLL_LOCK_vect _VECTOR(57) ++#define TRX24_PLL_LOCK_vect_num 57 ++ ++/* TRX24 - PLL unlock interrupt */ ++#define TRX24_PLL_UNLOCK_vect _VECTOR(58) ++#define TRX24_PLL_UNLOCK_vect_num 58 ++ ++/* TRX24 - Receive start interrupt */ ++#define TRX24_RX_START_vect _VECTOR(59) ++#define TRX24_RX_START_vect_num 59 ++ ++/* TRX24 - RX_END interrupt */ ++#define TRX24_RX_END_vect _VECTOR(60) ++#define TRX24_RX_END_vect_num 60 ++ ++/* TRX24 - CCA/ED done interrupt */ ++#define TRX24_CCA_ED_DONE_vect _VECTOR(61) ++#define TRX24_CCA_ED_DONE_vect_num 61 ++ ++/* TRX24 - XAH - AMI */ ++#define TRX24_XAH_AMI_vect _VECTOR(62) ++#define TRX24_XAH_AMI_vect_num 62 ++ ++/* TRX24 - TX_END interrupt */ ++#define TRX24_TX_END_vect _VECTOR(63) ++#define TRX24_TX_END_vect_num 63 ++ ++/* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */ ++#define TRX24_AWAKE_vect _VECTOR(64) ++#define TRX24_AWAKE_vect_num 64 ++ ++/* Symbol counter - compare match 1 interrupt */ ++#define SCNT_CMP1_vect _VECTOR(65) ++#define SCNT_CMP1_vect_num 65 ++ ++/* Symbol counter - compare match 2 interrupt */ ++#define SCNT_CMP2_vect _VECTOR(66) ++#define SCNT_CMP2_vect_num 66 ++ ++/* Symbol counter - compare match 3 interrupt */ ++#define SCNT_CMP3_vect _VECTOR(67) ++#define SCNT_CMP3_vect_num 67 ++ ++/* Symbol counter - overflow interrupt */ ++#define SCNT_OVFL_vect _VECTOR(68) ++#define SCNT_OVFL_vect_num 68 ++ ++/* Symbol counter - backoff interrupt */ ++#define SCNT_BACKOFF_vect _VECTOR(69) ++#define SCNT_BACKOFF_vect_num 69 ++ ++/* AES engine ready interrupt */ ++#define AES_READY_vect _VECTOR(70) ++#define AES_READY_vect_num 70 ++ ++/* Battery monitor indicates supply voltage below threshold */ ++#define BAT_LOW_vect _VECTOR(71) ++#define BAT_LOW_vect_num 71 ++ ++/* TRX24 TX start interrupt */ ++#define TRX24_TX_START_vect _VECTOR(72) ++#define TRX24_TX_START_vect_num 72 ++ ++/* Address match interrupt of address filter 0 */ ++#define TRX24_AMI0_vect _VECTOR(73) ++#define TRX24_AMI0_vect_num 73 ++ ++/* Address match interrupt of address filter 1 */ ++#define TRX24_AMI1_vect _VECTOR(74) ++#define TRX24_AMI1_vect_num 74 ++ ++/* Address match interrupt of address filter 2 */ ++#define TRX24_AMI2_vect _VECTOR(75) ++#define TRX24_AMI2_vect_num 75 ++ ++/* Address match interrupt of address filter 3 */ ++#define TRX24_AMI3_vect _VECTOR(76) ++#define TRX24_AMI3_vect_num 76 ++ ++#define _VECTORS_SIZE 308 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 256 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x3FFFF ++#define RAMSTART 0x0200 ++#define RAMSIZE 32768 ++#define RAMEND 0x81FF ++#define E2START 0 ++#define E2SIZE 8192 ++#define E2PAGESIZE 8 ++#define E2END 0x1FFF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL_SUT0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL_SUT1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL_SUT2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL_SUT3 (unsigned char)~_BV(3) ++#define FUSE_CKSEL_SUT4 (unsigned char)~_BV(4) ++#define FUSE_CKSEL_SUT5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0xA8 ++#define SIGNATURE_2 0x03 ++ ++ ++#endif /* #ifdef _AVR_ATMEGA2564RFR2_H_INCLUDED */ ++ +diff --git a/include/avr/iom256rfr2.h b/include/avr/iom256rfr2.h +new file mode 100644 +index 0000000..b91973d +--- /dev/null ++++ b/include/avr/iom256rfr2.h +@@ -0,0 +1,2556 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATMEGA256RFR2_H_INCLUDED ++#define _AVR_ATMEGA256RFR2_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom256rfr2.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDRA7 7 ++#define DDRA6 6 ++#define DDRA5 5 ++#define DDRA4 4 ++#define DDRA3 3 ++#define DDRA2 2 ++#define DDRA1 1 ++#define DDRA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDRC7 7 ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC7 7 ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDRE7 7 ++#define DDRE6 6 ++#define DDRE5 5 ++#define DDRE4 4 ++#define DDRE3 3 ++#define DDRE2 2 ++#define DDRE1 1 ++#define DDRE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE7 7 ++#define PORTE6 6 ++#define PORTE5 5 ++#define PORTE4 4 ++#define PORTE3 3 ++#define PORTE2 2 ++#define PORTE1 1 ++#define PORTE0 0 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDRF7 7 ++#define DDRF6 6 ++#define DDRF5 5 ++#define DDRF4 4 ++#define DDRF3 3 ++#define DDRF2 2 ++#define DDRF1 1 ++#define DDRF0 0 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PORTF7 7 ++#define PORTF6 6 ++#define PORTF5 5 ++#define PORTF4 4 ++#define PORTF3 3 ++#define PORTF2 2 ++#define PORTF1 1 ++#define PORTF0 0 ++ ++#define PING _SFR_IO8(0x12) ++#define PING7 7 ++#define PING6 6 ++#define PING5 5 ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++#define DDRG _SFR_IO8(0x13) ++#define DDRG7 7 ++#define DDRG6 6 ++#define DDRG5 5 ++#define DDRG4 4 ++#define DDRG3 3 ++#define DDRG2 2 ++#define DDRG1 1 ++#define DDRG0 0 ++ ++#define PORTG _SFR_IO8(0x14) ++#define PORTG7 7 ++#define PORTG6 6 ++#define PORTG5 5 ++#define PORTG4 4 ++#define PORTG3 3 ++#define PORTG2 2 ++#define PORTG1 1 ++#define PORTG0 0 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++#define Res0 3 ++#define Res1 4 ++#define Res2 5 ++#define Res3 6 ++#define Res4 7 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define OCF1C 3 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++#define TIFR3 _SFR_IO8(0x18) ++#define TOV3 0 ++#define OCF3A 1 ++#define OCF3B 2 ++#define OCF3C 3 ++#define ICF3 5 ++ ++#define TIFR4 _SFR_IO8(0x19) ++#define TOV4 0 ++#define OCF4A 1 ++#define OCF4B 2 ++#define OCF4C 3 ++#define ICF4 5 ++ ++#define TIFR5 _SFR_IO8(0x1A) ++#define TOV5 0 ++#define OCF5A 1 ++#define OCF5B 2 ++#define OCF5C 3 ++#define ICF5 5 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++#define INTF4 4 ++#define INTF5 5 ++#define INTF6 6 ++#define INTF7 7 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++#define INT3 3 ++#define INT4 4 ++#define INT5 5 ++#define INT6 6 ++#define INT7 7 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define PSRASY 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++ ++#define OCR0A _SFR_IO8(0x27) ++ ++#define OCR0B _SFR_IO8(0x28) ++ ++/* Reserved [0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCDR7 7 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define JTRF 4 ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define JTD 7 ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3A] */ ++ ++#define RAMPZ _SFR_IO8(0x3B) ++#define RAMPZ0 0 ++#define RAMPZ1 1 ++#define Res5 7 ++ ++#define EIND _SFR_IO8(0x3C) ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDE 3 ++#define WDCE 4 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62] */ ++ ++#define PRR2 _SFR_MEM8(0x63) ++#define PRRAM0 0 ++#define PRRAM1 1 ++#define PRRAM2 2 ++#define PRRAM3 3 ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRPGA 4 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++#define PRR1 _SFR_MEM8(0x65) ++#define PRUSART1 0 ++#define PRTIM3 3 ++#define PRTIM4 4 ++#define PRTIM5 5 ++#define PRTRX24 6 ++#define Res 7 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++#define BGCR _SFR_MEM8(0x67) ++#define BGCAL0 0 ++#define BGCAL1 1 ++#define BGCAL2 2 ++#define BGCAL_FINE0 3 ++#define BGCAL_FINE1 4 ++#define BGCAL_FINE2 5 ++#define BGCAL_FINE3 6 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++#define EICRB _SFR_MEM8(0x6A) ++#define ISC40 0 ++#define ISC41 1 ++#define ISC50 2 ++#define ISC51 3 ++#define ISC60 4 ++#define ISC61 5 ++#define ISC70 6 ++#define ISC71 7 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define OCIE1C 3 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++#define TIMSK3 _SFR_MEM8(0x71) ++#define TOIE3 0 ++#define OCIE3A 1 ++#define OCIE3B 2 ++#define OCIE3C 3 ++#define ICIE3 5 ++ ++#define TIMSK4 _SFR_MEM8(0x72) ++#define TOIE4 0 ++#define OCIE4A 1 ++#define OCIE4B 2 ++#define OCIE4C 3 ++#define ICIE4 5 ++ ++#define TIMSK5 _SFR_MEM8(0x73) ++#define TOIE5 0 ++#define OCIE5A 1 ++#define OCIE5B 2 ++#define OCIE5C 3 ++#define ICIE5 5 ++ ++/* Reserved [0x74] */ ++ ++#define NEMCR _SFR_MEM8(0x75) ++#define AEAM0 4 ++#define AEAM1 5 ++#define ENEAM 6 ++ ++/* Reserved [0x76] */ ++ ++#define ADCSRC _SFR_MEM8(0x77) ++#define ADSUT0 0 ++#define ADSUT1 1 ++#define ADSUT2 2 ++#define ADSUT3 3 ++#define ADSUT4 4 ++#define ADTHT0 6 ++#define ADTHT1 7 ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ACME 6 ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define MUX5 3 ++#define ACCH 4 ++#define REFOK 5 ++#define AVDDOK 7 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR2 _SFR_MEM8(0x7D) ++#define ADC8D 0 ++#define ADC9D 1 ++#define ADC10D 2 ++#define ADC11D 3 ++#define ADC12D 4 ++#define ADC13D 5 ++#define ADC14D 6 ++#define ADC15D 7 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1C0 2 ++#define COM1C1 3 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1C 5 ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Combine OCR1CL and OCR1CH */ ++#define OCR1C _SFR_MEM16(0x8C) ++ ++#define OCR1CL _SFR_MEM8(0x8C) ++#define OCR1CH _SFR_MEM8(0x8D) ++ ++/* Reserved [0x8E..0x8F] */ ++ ++#define TCCR3A _SFR_MEM8(0x90) ++#define WGM30 0 ++#define WGM31 1 ++#define COM3C0 2 ++#define COM3C1 3 ++#define COM3B0 4 ++#define COM3B1 5 ++#define COM3A0 6 ++#define COM3A1 7 ++ ++#define TCCR3B _SFR_MEM8(0x91) ++#define CS30 0 ++#define CS31 1 ++#define CS32 2 ++#define WGM32 3 ++#define WGM33 4 ++#define ICES3 6 ++#define ICNC3 7 ++ ++#define TCCR3C _SFR_MEM8(0x92) ++#define FOC3C 5 ++#define FOC3B 6 ++#define FOC3A 7 ++ ++/* Reserved [0x93] */ ++ ++/* Combine TCNT3L and TCNT3H */ ++#define TCNT3 _SFR_MEM16(0x94) ++ ++#define TCNT3L _SFR_MEM8(0x94) ++#define TCNT3H _SFR_MEM8(0x95) ++ ++/* Combine ICR3L and ICR3H */ ++#define ICR3 _SFR_MEM16(0x96) ++ ++#define ICR3L _SFR_MEM8(0x96) ++#define ICR3H _SFR_MEM8(0x97) ++ ++/* Combine OCR3AL and OCR3AH */ ++#define OCR3A _SFR_MEM16(0x98) ++ ++#define OCR3AL _SFR_MEM8(0x98) ++#define OCR3AH _SFR_MEM8(0x99) ++ ++/* Combine OCR3BL and OCR3BH */ ++#define OCR3B _SFR_MEM16(0x9A) ++ ++#define OCR3BL _SFR_MEM8(0x9A) ++#define OCR3BH _SFR_MEM8(0x9B) ++ ++/* Combine OCR3CL and OCR3CH */ ++#define OCR3C _SFR_MEM16(0x9C) ++ ++#define OCR3CL _SFR_MEM8(0x9C) ++#define OCR3CH _SFR_MEM8(0x9D) ++ ++/* Reserved [0x9E..0x9F] */ ++ ++#define TCCR4A _SFR_MEM8(0xA0) ++#define WGM40 0 ++#define WGM41 1 ++#define COM4C0 2 ++#define COM4C1 3 ++#define COM4B0 4 ++#define COM4B1 5 ++#define COM4A0 6 ++#define COM4A1 7 ++ ++#define TCCR4B _SFR_MEM8(0xA1) ++#define CS40 0 ++#define CS41 1 ++#define CS42 2 ++#define WGM42 3 ++#define WGM43 4 ++#define ICES4 6 ++#define ICNC4 7 ++ ++#define TCCR4C _SFR_MEM8(0xA2) ++#define FOC4C 5 ++#define FOC4B 6 ++#define FOC4A 7 ++ ++/* Reserved [0xA3] */ ++ ++/* Combine TCNT4L and TCNT4H */ ++#define TCNT4 _SFR_MEM16(0xA4) ++ ++#define TCNT4L _SFR_MEM8(0xA4) ++#define TCNT4H _SFR_MEM8(0xA5) ++ ++/* Combine ICR4L and ICR4H */ ++#define ICR4 _SFR_MEM16(0xA6) ++ ++#define ICR4L _SFR_MEM8(0xA6) ++#define ICR4H _SFR_MEM8(0xA7) ++ ++/* Combine OCR4AL and OCR4AH */ ++#define OCR4A _SFR_MEM16(0xA8) ++ ++#define OCR4AL _SFR_MEM8(0xA8) ++#define OCR4AH _SFR_MEM8(0xA9) ++ ++/* Combine OCR4BL and OCR4BH */ ++#define OCR4B _SFR_MEM16(0xAA) ++ ++#define OCR4BL _SFR_MEM8(0xAA) ++#define OCR4BH _SFR_MEM8(0xAB) ++ ++/* Combine OCR4CL and OCR4CH */ ++#define OCR4C _SFR_MEM16(0xAC) ++ ++#define OCR4CL _SFR_MEM8(0xAC) ++#define OCR4CH _SFR_MEM8(0xAD) ++ ++/* Reserved [0xAE..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++#define OCR2B _SFR_MEM8(0xB4) ++ ++/* Reserved [0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++#define EXCLKAMR 7 ++ ++/* Reserved [0xB7] */ ++ ++#define TWBR _SFR_MEM8(0xB8) ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++#define IRQ_MASK1 _SFR_MEM8(0xBE) ++#define TX_START_EN 0 ++#define MAF_0_AMI_EN 1 ++#define MAF_1_AMI_EN 2 ++#define MAF_2_AMI_EN 3 ++#define MAF_3_AMI_EN 4 ++ ++#define IRQ_STATUS1 _SFR_MEM8(0xBF) ++#define TX_START 0 ++#define MAF_0_AMI 1 ++#define MAF_1_AMI 2 ++#define MAF_2_AMI 3 ++#define MAF_3_AMI 4 ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++#define UCPHA0 1 ++#define UDORD0 2 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0xC6) ++ ++/* Reserved [0xC7] */ ++ ++#define UCSR1A _SFR_MEM8(0xC8) ++#define MPCM1 0 ++#define U2X1 1 ++#define UPE1 2 ++#define DOR1 3 ++#define FE1 4 ++#define UDRE1 5 ++#define TXC1 6 ++#define RXC1 7 ++ ++#define UCSR1B _SFR_MEM8(0xC9) ++#define TXB81 0 ++#define RXB81 1 ++#define UCSZ12 2 ++#define TXEN1 3 ++#define RXEN1 4 ++#define UDRIE1 5 ++#define TXCIE1 6 ++#define RXCIE1 7 ++ ++#define UCSR1C _SFR_MEM8(0xCA) ++#define UCPOL1 0 ++#define UCSZ10 1 ++#define UCSZ11 2 ++#define USBS1 3 ++#define UPM10 4 ++#define UPM11 5 ++#define UMSEL10 6 ++#define UMSEL11 7 ++#define UCPHA1 1 ++#define UDORD1 2 ++ ++/* Reserved [0xCB] */ ++ ++/* Combine UBRR1L and UBRR1H */ ++#define UBRR1 _SFR_MEM16(0xCC) ++ ++#define UBRR1L _SFR_MEM8(0xCC) ++#define UBRR1H _SFR_MEM8(0xCD) ++ ++#define UDR1 _SFR_MEM8(0xCE) ++ ++/* Reserved [0xCF..0xD6] */ ++ ++#define SCRSTRLL _SFR_MEM8(0xD7) ++#define SCRSTRLL0 0 ++#define SCRSTRLL1 1 ++#define SCRSTRLL2 2 ++#define SCRSTRLL3 3 ++#define SCRSTRLL4 4 ++#define SCRSTRLL5 5 ++#define SCRSTRLL6 6 ++#define SCRSTRLL7 7 ++ ++#define SCRSTRLH _SFR_MEM8(0xD8) ++#define SCRSTRLH0 0 ++#define SCRSTRLH1 1 ++#define SCRSTRLH2 2 ++#define SCRSTRLH3 3 ++#define SCRSTRLH4 4 ++#define SCRSTRLH5 5 ++#define SCRSTRLH6 6 ++#define SCRSTRLH7 7 ++ ++#define SCRSTRHL _SFR_MEM8(0xD9) ++#define SCRSTRHL0 0 ++#define SCRSTRHL1 1 ++#define SCRSTRHL2 2 ++#define SCRSTRHL3 3 ++#define SCRSTRHL4 4 ++#define SCRSTRHL5 5 ++#define SCRSTRHL6 6 ++#define SCRSTRHL7 7 ++ ++#define SCRSTRHH _SFR_MEM8(0xDA) ++#define SCRSTRHH0 0 ++#define SCRSTRHH1 1 ++#define SCRSTRHH2 2 ++#define SCRSTRHH3 3 ++#define SCRSTRHH4 4 ++#define SCRSTRHH5 5 ++#define SCRSTRHH6 6 ++#define SCRSTRHH7 7 ++ ++#define SCCSR _SFR_MEM8(0xDB) ++#define SCCS10 0 ++#define SCCS11 1 ++#define SCCS20 2 ++#define SCCS21 3 ++#define SCCS30 4 ++#define SCCS31 5 ++ ++#define SCCR0 _SFR_MEM8(0xDC) ++#define SCCMP1 0 ++#define SCCMP2 1 ++#define SCCMP3 2 ++#define SCTSE 3 ++#define SCCKSEL 4 ++#define SCEN 5 ++#define SCMBTS 6 ++#define SCRES 7 ++ ++#define SCCR1 _SFR_MEM8(0xDD) ++#define SCENBO 0 ++#define SCEECLK 1 ++#define SCCKDIV0 2 ++#define SCCKDIV1 3 ++#define SCCKDIV2 4 ++#define SCBTSM 5 ++#define Res6 7 ++ ++#define SCSR _SFR_MEM8(0xDE) ++#define SCBSY 0 ++ ++#define SCIRQM _SFR_MEM8(0xDF) ++#define IRQMCP1 0 ++#define IRQMCP2 1 ++#define IRQMCP3 2 ++#define IRQMOF 3 ++#define IRQMBO 4 ++ ++#define SCIRQS _SFR_MEM8(0xE0) ++#define IRQSCP1 0 ++#define IRQSCP2 1 ++#define IRQSCP3 2 ++#define IRQSOF 3 ++#define IRQSBO 4 ++ ++#define SCCNTLL _SFR_MEM8(0xE1) ++#define SCCNTLL0 0 ++#define SCCNTLL1 1 ++#define SCCNTLL2 2 ++#define SCCNTLL3 3 ++#define SCCNTLL4 4 ++#define SCCNTLL5 5 ++#define SCCNTLL6 6 ++#define SCCNTLL7 7 ++ ++#define SCCNTLH _SFR_MEM8(0xE2) ++#define SCCNTLH0 0 ++#define SCCNTLH1 1 ++#define SCCNTLH2 2 ++#define SCCNTLH3 3 ++#define SCCNTLH4 4 ++#define SCCNTLH5 5 ++#define SCCNTLH6 6 ++#define SCCNTLH7 7 ++ ++#define SCCNTHL _SFR_MEM8(0xE3) ++#define SCCNTHL0 0 ++#define SCCNTHL1 1 ++#define SCCNTHL2 2 ++#define SCCNTHL3 3 ++#define SCCNTHL4 4 ++#define SCCNTHL5 5 ++#define SCCNTHL6 6 ++#define SCCNTHL7 7 ++ ++#define SCCNTHH _SFR_MEM8(0xE4) ++#define SCCNTHH0 0 ++#define SCCNTHH1 1 ++#define SCCNTHH2 2 ++#define SCCNTHH3 3 ++#define SCCNTHH4 4 ++#define SCCNTHH5 5 ++#define SCCNTHH6 6 ++#define SCCNTHH7 7 ++ ++#define SCBTSRLL _SFR_MEM8(0xE5) ++#define SCBTSRLL0 0 ++#define SCBTSRLL1 1 ++#define SCBTSRLL2 2 ++#define SCBTSRLL3 3 ++#define SCBTSRLL4 4 ++#define SCBTSRLL5 5 ++#define SCBTSRLL6 6 ++#define SCBTSRLL7 7 ++ ++#define SCBTSRLH _SFR_MEM8(0xE6) ++#define SCBTSRLH0 0 ++#define SCBTSRLH1 1 ++#define SCBTSRLH2 2 ++#define SCBTSRLH3 3 ++#define SCBTSRLH4 4 ++#define SCBTSRLH5 5 ++#define SCBTSRLH6 6 ++#define SCBTSRLH7 7 ++ ++#define SCBTSRHL _SFR_MEM8(0xE7) ++#define SCBTSRHL0 0 ++#define SCBTSRHL1 1 ++#define SCBTSRHL2 2 ++#define SCBTSRHL3 3 ++#define SCBTSRHL4 4 ++#define SCBTSRHL5 5 ++#define SCBTSRHL6 6 ++#define SCBTSRHL7 7 ++ ++#define SCBTSRHH _SFR_MEM8(0xE8) ++#define SCBTSRHH0 0 ++#define SCBTSRHH1 1 ++#define SCBTSRHH2 2 ++#define SCBTSRHH3 3 ++#define SCBTSRHH4 4 ++#define SCBTSRHH5 5 ++#define SCBTSRHH6 6 ++#define SCBTSRHH7 7 ++ ++#define SCTSRLL _SFR_MEM8(0xE9) ++#define SCTSRLL0 0 ++#define SCTSRLL1 1 ++#define SCTSRLL2 2 ++#define SCTSRLL3 3 ++#define SCTSRLL4 4 ++#define SCTSRLL5 5 ++#define SCTSRLL6 6 ++#define SCTSRLL7 7 ++ ++#define SCTSRLH _SFR_MEM8(0xEA) ++#define SCTSRLH0 0 ++#define SCTSRLH1 1 ++#define SCTSRLH2 2 ++#define SCTSRLH3 3 ++#define SCTSRLH4 4 ++#define SCTSRLH5 5 ++#define SCTSRLH6 6 ++#define SCTSRLH7 7 ++ ++#define SCTSRHL _SFR_MEM8(0xEB) ++#define SCTSRHL0 0 ++#define SCTSRHL1 1 ++#define SCTSRHL2 2 ++#define SCTSRHL3 3 ++#define SCTSRHL4 4 ++#define SCTSRHL5 5 ++#define SCTSRHL6 6 ++#define SCTSRHL7 7 ++ ++#define SCTSRHH _SFR_MEM8(0xEC) ++#define SCTSRHH0 0 ++#define SCTSRHH1 1 ++#define SCTSRHH2 2 ++#define SCTSRHH3 3 ++#define SCTSRHH4 4 ++#define SCTSRHH5 5 ++#define SCTSRHH6 6 ++#define SCTSRHH7 7 ++ ++#define SCOCR3LL _SFR_MEM8(0xED) ++#define SCOCR3LL0 0 ++#define SCOCR3LL1 1 ++#define SCOCR3LL2 2 ++#define SCOCR3LL3 3 ++#define SCOCR3LL4 4 ++#define SCOCR3LL5 5 ++#define SCOCR3LL6 6 ++#define SCOCR3LL7 7 ++ ++#define SCOCR3LH _SFR_MEM8(0xEE) ++#define SCOCR3LH0 0 ++#define SCOCR3LH1 1 ++#define SCOCR3LH2 2 ++#define SCOCR3LH3 3 ++#define SCOCR3LH4 4 ++#define SCOCR3LH5 5 ++#define SCOCR3LH6 6 ++#define SCOCR3LH7 7 ++ ++#define SCOCR3HL _SFR_MEM8(0xEF) ++#define SCOCR3HL0 0 ++#define SCOCR3HL1 1 ++#define SCOCR3HL2 2 ++#define SCOCR3HL3 3 ++#define SCOCR3HL4 4 ++#define SCOCR3HL5 5 ++#define SCOCR3HL6 6 ++#define SCOCR3HL7 7 ++ ++#define SCOCR3HH _SFR_MEM8(0xF0) ++#define SCOCR3HH0 0 ++#define SCOCR3HH1 1 ++#define SCOCR3HH2 2 ++#define SCOCR3HH3 3 ++#define SCOCR3HH4 4 ++#define SCOCR3HH5 5 ++#define SCOCR3HH6 6 ++#define SCOCR3HH7 7 ++ ++#define SCOCR2LL _SFR_MEM8(0xF1) ++#define SCOCR2LL0 0 ++#define SCOCR2LL1 1 ++#define SCOCR2LL2 2 ++#define SCOCR2LL3 3 ++#define SCOCR2LL4 4 ++#define SCOCR2LL5 5 ++#define SCOCR2LL6 6 ++#define SCOCR2LL7 7 ++ ++#define SCOCR2LH _SFR_MEM8(0xF2) ++#define SCOCR2LH0 0 ++#define SCOCR2LH1 1 ++#define SCOCR2LH2 2 ++#define SCOCR2LH3 3 ++#define SCOCR2LH4 4 ++#define SCOCR2LH5 5 ++#define SCOCR2LH6 6 ++#define SCOCR2LH7 7 ++ ++#define SCOCR2HL _SFR_MEM8(0xF3) ++#define SCOCR2HL0 0 ++#define SCOCR2HL1 1 ++#define SCOCR2HL2 2 ++#define SCOCR2HL3 3 ++#define SCOCR2HL4 4 ++#define SCOCR2HL5 5 ++#define SCOCR2HL6 6 ++#define SCOCR2HL7 7 ++ ++#define SCOCR2HH _SFR_MEM8(0xF4) ++#define SCOCR2HH0 0 ++#define SCOCR2HH1 1 ++#define SCOCR2HH2 2 ++#define SCOCR2HH3 3 ++#define SCOCR2HH4 4 ++#define SCOCR2HH5 5 ++#define SCOCR2HH6 6 ++#define SCOCR2HH7 7 ++ ++#define SCOCR1LL _SFR_MEM8(0xF5) ++#define SCOCR1LL0 0 ++#define SCOCR1LL1 1 ++#define SCOCR1LL2 2 ++#define SCOCR1LL3 3 ++#define SCOCR1LL4 4 ++#define SCOCR1LL5 5 ++#define SCOCR1LL6 6 ++#define SCOCR1LL7 7 ++ ++#define SCOCR1LH _SFR_MEM8(0xF6) ++#define SCOCR1LH0 0 ++#define SCOCR1LH1 1 ++#define SCOCR1LH2 2 ++#define SCOCR1LH3 3 ++#define SCOCR1LH4 4 ++#define SCOCR1LH5 5 ++#define SCOCR1LH6 6 ++#define SCOCR1LH7 7 ++ ++#define SCOCR1HL _SFR_MEM8(0xF7) ++#define SCOCR1HL0 0 ++#define SCOCR1HL1 1 ++#define SCOCR1HL2 2 ++#define SCOCR1HL3 3 ++#define SCOCR1HL4 4 ++#define SCOCR1HL5 5 ++#define SCOCR1HL6 6 ++#define SCOCR1HL7 7 ++ ++#define SCOCR1HH _SFR_MEM8(0xF8) ++#define SCOCR1HH0 0 ++#define SCOCR1HH1 1 ++#define SCOCR1HH2 2 ++#define SCOCR1HH3 3 ++#define SCOCR1HH4 4 ++#define SCOCR1HH5 5 ++#define SCOCR1HH6 6 ++#define SCOCR1HH7 7 ++ ++#define SCTSTRLL _SFR_MEM8(0xF9) ++#define SCTSTRLL0 0 ++#define SCTSTRLL1 1 ++#define SCTSTRLL2 2 ++#define SCTSTRLL3 3 ++#define SCTSTRLL4 4 ++#define SCTSTRLL5 5 ++#define SCTSTRLL6 6 ++#define SCTSTRLL7 7 ++ ++#define SCTSTRLH _SFR_MEM8(0xFA) ++#define SCTSTRLH0 0 ++#define SCTSTRLH1 1 ++#define SCTSTRLH2 2 ++#define SCTSTRLH3 3 ++#define SCTSTRLH4 4 ++#define SCTSTRLH5 5 ++#define SCTSTRLH6 6 ++#define SCTSTRLH7 7 ++ ++#define SCTSTRHL _SFR_MEM8(0xFB) ++#define SCTSTRHL0 0 ++#define SCTSTRHL1 1 ++#define SCTSTRHL2 2 ++#define SCTSTRHL3 3 ++#define SCTSTRHL4 4 ++#define SCTSTRHL5 5 ++#define SCTSTRHL6 6 ++#define SCTSTRHL7 7 ++ ++#define SCTSTRHH _SFR_MEM8(0xFC) ++#define SCTSTRHH0 0 ++#define SCTSTRHH1 1 ++#define SCTSTRHH2 2 ++#define SCTSTRHH3 3 ++#define SCTSTRHH4 4 ++#define SCTSTRHH5 5 ++#define SCTSTRHH6 6 ++#define SCTSTRHH7 7 ++ ++/* Reserved [0xFD..0x10B] */ ++ ++#define MAFCR0 _SFR_MEM8(0x10C) ++#define MAF0EN 0 ++#define MAF1EN 1 ++#define MAF2EN 2 ++#define MAF3EN 3 ++ ++#define MAFCR1 _SFR_MEM8(0x10D) ++#define AACK_0_I_AM_COORD 0 ++#define AACK_0_SET_PD 1 ++#define AACK_1_I_AM_COORD 2 ++#define AACK_1_SET_PD 3 ++#define AACK_2_I_AM_COORD 4 ++#define AACK_2_SET_PD 5 ++#define AACK_3_I_AM_COORD 6 ++#define AACK_3_SET_PD 7 ++ ++#define MAFSA0L _SFR_MEM8(0x10E) ++#define MAFSA0L0 0 ++#define MAFSA0L1 1 ++#define MAFSA0L2 2 ++#define MAFSA0L3 3 ++#define MAFSA0L4 4 ++#define MAFSA0L5 5 ++#define MAFSA0L6 6 ++#define MAFSA0L7 7 ++ ++#define MAFSA0H _SFR_MEM8(0x10F) ++#define MAFSA0H0 0 ++#define MAFSA0H1 1 ++#define MAFSA0H2 2 ++#define MAFSA0H3 3 ++#define MAFSA0H4 4 ++#define MAFSA0H5 5 ++#define MAFSA0H6 6 ++#define MAFSA0H7 7 ++ ++#define MAFPA0L _SFR_MEM8(0x110) ++#define MAFPA0L0 0 ++#define MAFPA0L1 1 ++#define MAFPA0L2 2 ++#define MAFPA0L3 3 ++#define MAFPA0L4 4 ++#define MAFPA0L5 5 ++#define MAFPA0L6 6 ++#define MAFPA0L7 7 ++ ++#define MAFPA0H _SFR_MEM8(0x111) ++#define MAFPA0H0 0 ++#define MAFPA0H1 1 ++#define MAFPA0H2 2 ++#define MAFPA0H3 3 ++#define MAFPA0H4 4 ++#define MAFPA0H5 5 ++#define MAFPA0H6 6 ++#define MAFPA0H7 7 ++ ++#define MAFSA1L _SFR_MEM8(0x112) ++#define MAFSA1L0 0 ++#define MAFSA1L1 1 ++#define MAFSA1L2 2 ++#define MAFSA1L3 3 ++#define MAFSA1L4 4 ++#define MAFSA1L5 5 ++#define MAFSA1L6 6 ++#define MAFSA1L7 7 ++ ++#define MAFSA1H _SFR_MEM8(0x113) ++#define MAFSA1H0 0 ++#define MAFSA1H1 1 ++#define MAFSA1H2 2 ++#define MAFSA1H3 3 ++#define MAFSA1H4 4 ++#define MAFSA1H5 5 ++#define MAFSA1H6 6 ++#define MAFSA1H7 7 ++ ++#define MAFPA1L _SFR_MEM8(0x114) ++#define MAFPA1L0 0 ++#define MAFPA1L1 1 ++#define MAFPA1L2 2 ++#define MAFPA1L3 3 ++#define MAFPA1L4 4 ++#define MAFPA1L5 5 ++#define MAFPA1L6 6 ++#define MAFPA1L7 7 ++ ++#define MAFPA1H _SFR_MEM8(0x115) ++#define MAFPA1H0 0 ++#define MAFPA1H1 1 ++#define MAFPA1H2 2 ++#define MAFPA1H3 3 ++#define MAFPA1H4 4 ++#define MAFPA1H5 5 ++#define MAFPA1H6 6 ++#define MAFPA1H7 7 ++ ++#define MAFSA2L _SFR_MEM8(0x116) ++#define MAFSA2L0 0 ++#define MAFSA2L1 1 ++#define MAFSA2L2 2 ++#define MAFSA2L3 3 ++#define MAFSA2L4 4 ++#define MAFSA2L5 5 ++#define MAFSA2L6 6 ++#define MAFSA2L7 7 ++ ++#define MAFSA2H _SFR_MEM8(0x117) ++#define MAFSA2H0 0 ++#define MAFSA2H1 1 ++#define MAFSA2H2 2 ++#define MAFSA2H3 3 ++#define MAFSA2H4 4 ++#define MAFSA2H5 5 ++#define MAFSA2H6 6 ++#define MAFSA2H7 7 ++ ++#define MAFPA2L _SFR_MEM8(0x118) ++#define MAFPA2L0 0 ++#define MAFPA2L1 1 ++#define MAFPA2L2 2 ++#define MAFPA2L3 3 ++#define MAFPA2L4 4 ++#define MAFPA2L5 5 ++#define MAFPA2L6 6 ++#define MAFPA2L7 7 ++ ++#define MAFPA2H _SFR_MEM8(0x119) ++#define MAFPA2H0 0 ++#define MAFPA2H1 1 ++#define MAFPA2H2 2 ++#define MAFPA2H3 3 ++#define MAFPA2H4 4 ++#define MAFPA2H5 5 ++#define MAFPA2H6 6 ++#define MAFPA2H7 7 ++ ++#define MAFSA3L _SFR_MEM8(0x11A) ++#define MAFSA3L0 0 ++#define MAFSA3L1 1 ++#define MAFSA3L2 2 ++#define MAFSA3L3 3 ++#define MAFSA3L4 4 ++#define MAFSA3L5 5 ++#define MAFSA3L6 6 ++#define MAFSA3L7 7 ++ ++#define MAFSA3H _SFR_MEM8(0x11B) ++#define MAFSA3H0 0 ++#define MAFSA3H1 1 ++#define MAFSA3H2 2 ++#define MAFSA3H3 3 ++#define MAFSA3H4 4 ++#define MAFSA3H5 5 ++#define MAFSA3H6 6 ++#define MAFSA3H7 7 ++ ++#define MAFPA3L _SFR_MEM8(0x11C) ++#define MAFPA3L0 0 ++#define MAFPA3L1 1 ++#define MAFPA3L2 2 ++#define MAFPA3L3 3 ++#define MAFPA3L4 4 ++#define MAFPA3L5 5 ++#define MAFPA3L6 6 ++#define MAFPA3L7 7 ++ ++#define MAFPA3H _SFR_MEM8(0x11D) ++#define MAFPA3H0 0 ++#define MAFPA3H1 1 ++#define MAFPA3H2 2 ++#define MAFPA3H3 3 ++#define MAFPA3H4 4 ++#define MAFPA3H5 5 ++#define MAFPA3H6 6 ++#define MAFPA3H7 7 ++ ++/* Reserved [0x11E..0x11F] */ ++ ++#define TCCR5A _SFR_MEM8(0x120) ++#define WGM50 0 ++#define WGM51 1 ++#define COM5C0 2 ++#define COM5C1 3 ++#define COM5B0 4 ++#define COM5B1 5 ++#define COM5A0 6 ++#define COM5A1 7 ++ ++#define TCCR5B _SFR_MEM8(0x121) ++#define CS50 0 ++#define CS51 1 ++#define CS52 2 ++#define WGM52 3 ++#define WGM53 4 ++#define ICES5 6 ++#define ICNC5 7 ++ ++#define TCCR5C _SFR_MEM8(0x122) ++#define FOC5C 5 ++#define FOC5B 6 ++#define FOC5A 7 ++ ++/* Reserved [0x123] */ ++ ++/* Combine TCNT5L and TCNT5H */ ++#define TCNT5 _SFR_MEM16(0x124) ++ ++#define TCNT5L _SFR_MEM8(0x124) ++#define TCNT5H _SFR_MEM8(0x125) ++ ++/* Combine ICR5L and ICR5H */ ++#define ICR5 _SFR_MEM16(0x126) ++ ++#define ICR5L _SFR_MEM8(0x126) ++#define ICR5H _SFR_MEM8(0x127) ++ ++/* Combine OCR5AL and OCR5AH */ ++#define OCR5A _SFR_MEM16(0x128) ++ ++#define OCR5AL _SFR_MEM8(0x128) ++#define OCR5AH _SFR_MEM8(0x129) ++ ++/* Combine OCR5BL and OCR5BH */ ++#define OCR5B _SFR_MEM16(0x12A) ++ ++#define OCR5BL _SFR_MEM8(0x12A) ++#define OCR5BH _SFR_MEM8(0x12B) ++ ++/* Combine OCR5CL and OCR5CH */ ++#define OCR5C _SFR_MEM16(0x12C) ++ ++#define OCR5CL _SFR_MEM8(0x12C) ++#define OCR5CH _SFR_MEM8(0x12D) ++ ++/* Reserved [0x12E] */ ++ ++#define LLCR _SFR_MEM8(0x12F) ++#define LLENCAL 0 ++#define LLSHORT 1 ++#define LLTCO 2 ++#define LLCAL 3 ++#define LLCOMP 4 ++#define LLDONE 5 ++ ++#define LLDRL _SFR_MEM8(0x130) ++#define LLDRL0 0 ++#define LLDRL1 1 ++#define LLDRL2 2 ++#define LLDRL3 3 ++ ++#define LLDRH _SFR_MEM8(0x131) ++#define LLDRH0 0 ++#define LLDRH1 1 ++#define LLDRH2 2 ++#define LLDRH3 3 ++#define LLDRH4 4 ++ ++#define DRTRAM3 _SFR_MEM8(0x132) ++#define ENDRT 4 ++#define DRTSWOK 5 ++ ++#define DRTRAM2 _SFR_MEM8(0x133) ++ ++#define DRTRAM1 _SFR_MEM8(0x134) ++ ++#define DRTRAM0 _SFR_MEM8(0x135) ++ ++#define DPDS0 _SFR_MEM8(0x136) ++#define PBDRV0 0 ++#define PBDRV1 1 ++#define PDDRV0 2 ++#define PDDRV1 3 ++#define PEDRV0 4 ++#define PEDRV1 5 ++#define PFDRV0 6 ++#define PFDRV1 7 ++ ++#define DPDS1 _SFR_MEM8(0x137) ++#define PGDRV0 0 ++#define PGDRV1 1 ++ ++#define PARCR _SFR_MEM8(0x138) ++#define PARUFI 0 ++#define PARDFI 1 ++#define PALTU0 2 ++#define PALTU1 3 ++#define PALTU2 4 ++#define PALTD0 5 ++#define PALTD1 6 ++#define PALTD2 7 ++ ++#define TRXPR _SFR_MEM8(0x139) ++#define TRXRST 0 ++#define SLPTR 1 ++ ++/* Reserved [0x13A..0x13B] */ ++ ++#define AES_CTRL _SFR_MEM8(0x13C) ++#define AES_IM 2 ++#define AES_DIR 3 ++#define AES_MODE 5 ++#define AES_REQUEST 7 ++ ++#define AES_STATUS _SFR_MEM8(0x13D) ++#define AES_DONE 0 ++#define AES_ER 7 ++ ++#define AES_STATE _SFR_MEM8(0x13E) ++#define AES_STATE0 0 ++#define AES_STATE1 1 ++#define AES_STATE2 2 ++#define AES_STATE3 3 ++#define AES_STATE4 4 ++#define AES_STATE5 5 ++#define AES_STATE6 6 ++#define AES_STATE7 7 ++ ++#define AES_KEY _SFR_MEM8(0x13F) ++#define AES_KEY0 0 ++#define AES_KEY1 1 ++#define AES_KEY2 2 ++#define AES_KEY3 3 ++#define AES_KEY4 4 ++#define AES_KEY5 5 ++#define AES_KEY6 6 ++#define AES_KEY7 7 ++ ++/* Reserved [0x140] */ ++ ++#define TRX_STATUS _SFR_MEM8(0x141) ++#define TRX_STATUS0 0 ++#define TRX_STATUS1 1 ++#define TRX_STATUS2 2 ++#define TRX_STATUS3 3 ++#define TRX_STATUS4 4 ++#define TST_STATUS 5 ++#define CCA_STATUS 6 ++#define CCA_DONE 7 ++ ++#define TRX_STATE _SFR_MEM8(0x142) ++#define TRX_CMD0 0 ++#define TRX_CMD1 1 ++#define TRX_CMD2 2 ++#define TRX_CMD3 3 ++#define TRX_CMD4 4 ++#define TRAC_STATUS0 5 ++#define TRAC_STATUS1 6 ++#define TRAC_STATUS2 7 ++ ++#define TRX_CTRL_0 _SFR_MEM8(0x143) ++#define PMU_IF_INV 4 ++#define PMU_START 5 ++#define PMU_EN 6 ++#define Res7 7 ++ ++#define TRX_CTRL_1 _SFR_MEM8(0x144) ++#define PLL_TX_FLT 4 ++#define TX_AUTO_CRC_ON 5 ++#define IRQ_2_EXT_EN 6 ++#define PA_EXT_EN 7 ++ ++#define PHY_TX_PWR _SFR_MEM8(0x145) ++#define TX_PWR0 0 ++#define TX_PWR1 1 ++#define TX_PWR2 2 ++#define TX_PWR3 3 ++ ++#define PHY_RSSI _SFR_MEM8(0x146) ++#define RSSI0 0 ++#define RSSI1 1 ++#define RSSI2 2 ++#define RSSI3 3 ++#define RSSI4 4 ++#define RND_VALUE0 5 ++#define RND_VALUE1 6 ++#define RX_CRC_VALID 7 ++ ++#define PHY_ED_LEVEL _SFR_MEM8(0x147) ++#define ED_LEVEL0 0 ++#define ED_LEVEL1 1 ++#define ED_LEVEL2 2 ++#define ED_LEVEL3 3 ++#define ED_LEVEL4 4 ++#define ED_LEVEL5 5 ++#define ED_LEVEL6 6 ++#define ED_LEVEL7 7 ++ ++#define PHY_CC_CCA _SFR_MEM8(0x148) ++#define CHANNEL0 0 ++#define CHANNEL1 1 ++#define CHANNEL2 2 ++#define CHANNEL3 3 ++#define CHANNEL4 4 ++#define CCA_MODE0 5 ++#define CCA_MODE1 6 ++#define CCA_REQUEST 7 ++ ++#define CCA_THRES _SFR_MEM8(0x149) ++#define CCA_ED_THRES0 0 ++#define CCA_ED_THRES1 1 ++#define CCA_ED_THRES2 2 ++#define CCA_ED_THRES3 3 ++#define CCA_CS_THRES0 4 ++#define CCA_CS_THRES1 5 ++#define CCA_CS_THRES2 6 ++#define CCA_CS_THRES3 7 ++ ++#define RX_CTRL _SFR_MEM8(0x14A) ++#define PDT_THRES0 0 ++#define PDT_THRES1 1 ++#define PDT_THRES2 2 ++#define PDT_THRES3 3 ++ ++#define SFD_VALUE _SFR_MEM8(0x14B) ++#define SFD_VALUE0 0 ++#define SFD_VALUE1 1 ++#define SFD_VALUE2 2 ++#define SFD_VALUE3 3 ++#define SFD_VALUE4 4 ++#define SFD_VALUE5 5 ++#define SFD_VALUE6 6 ++#define SFD_VALUE7 7 ++ ++#define TRX_CTRL_2 _SFR_MEM8(0x14C) ++#define OQPSK_DATA_RATE0 0 ++#define OQPSK_DATA_RATE1 1 ++#define RX_SAFE_MODE 7 ++ ++#define ANT_DIV _SFR_MEM8(0x14D) ++#define ANT_CTRL0 0 ++#define ANT_CTRL1 1 ++#define ANT_EXT_SW_EN 2 ++#define ANT_DIV_EN 3 ++#define ANT_SEL 7 ++ ++#define IRQ_MASK _SFR_MEM8(0x14E) ++#define PLL_LOCK_EN 0 ++#define PLL_UNLOCK_EN 1 ++#define RX_START_EN 2 ++#define RX_END_EN 3 ++#define CCA_ED_DONE_EN 4 ++#define AMI_EN 5 ++#define TX_END_EN 6 ++#define AWAKE_EN 7 ++ ++#define IRQ_STATUS _SFR_MEM8(0x14F) ++#define PLL_LOCK 0 ++#define PLL_UNLOCK 1 ++#define RX_START 2 ++#define RX_END 3 ++#define CCA_ED_DONE 4 ++#define AMI 5 ++#define TX_END 6 ++#define AWAKE 7 ++ ++#define VREG_CTRL _SFR_MEM8(0x150) ++#define DVDD_OK 2 ++#define DVREG_EXT 3 ++#define AVDD_OK 6 ++#define AVREG_EXT 7 ++ ++#define BATMON _SFR_MEM8(0x151) ++#define BATMON_VTH0 0 ++#define BATMON_VTH1 1 ++#define BATMON_VTH2 2 ++#define BATMON_VTH3 3 ++#define BATMON_HR 4 ++#define BATMON_OK 5 ++#define BAT_LOW_EN 6 ++#define BAT_LOW 7 ++ ++#define XOSC_CTRL _SFR_MEM8(0x152) ++#define XTAL_TRIM0 0 ++#define XTAL_TRIM1 1 ++#define XTAL_TRIM2 2 ++#define XTAL_TRIM3 3 ++#define XTAL_MODE0 4 ++#define XTAL_MODE1 5 ++#define XTAL_MODE2 6 ++#define XTAL_MODE3 7 ++ ++#define CC_CTRL_0 _SFR_MEM8(0x153) ++#define CC_NUMBER0 0 ++#define CC_NUMBER1 1 ++#define CC_NUMBER2 2 ++#define CC_NUMBER3 3 ++#define CC_NUMBER4 4 ++#define CC_NUMBER5 5 ++#define CC_NUMBER6 6 ++#define CC_NUMBER7 7 ++ ++#define CC_CTRL_1 _SFR_MEM8(0x154) ++#define CC_BAND0 0 ++#define CC_BAND1 1 ++#define CC_BAND2 2 ++#define CC_BAND3 3 ++ ++#define RX_SYN _SFR_MEM8(0x155) ++#define RX_PDT_LEVEL0 0 ++#define RX_PDT_LEVEL1 1 ++#define RX_PDT_LEVEL2 2 ++#define RX_PDT_LEVEL3 3 ++#define RX_OVERRIDE 6 ++#define RX_PDT_DIS 7 ++ ++#define TRX_RPC _SFR_MEM8(0x156) ++#define XAH_RPC_EN 0 ++#define IPAN_RPC_EN 1 ++#define PLL_RPC_EN 3 ++#define PDT_RPC_EN 4 ++#define RX_RPC_EN 5 ++#define RX_RPC_CTRL0 6 ++#define RX_RPC_CTRL1 7 ++ ++#define XAH_CTRL_1 _SFR_MEM8(0x157) ++#define AACK_PROM_MODE 1 ++#define AACK_ACK_TIME 2 ++#define AACK_UPLD_RES_FT 4 ++#define AACK_FLTR_RES_FT 5 ++ ++#define FTN_CTRL _SFR_MEM8(0x158) ++#define FTN_START 7 ++ ++/* Reserved [0x159] */ ++ ++#define PLL_CF _SFR_MEM8(0x15A) ++#define PLL_CF_START 7 ++ ++#define PLL_DCU _SFR_MEM8(0x15B) ++#define PLL_DCU_START 7 ++ ++#define PART_NUM _SFR_MEM8(0x15C) ++#define PART_NUM0 0 ++#define PART_NUM1 1 ++#define PART_NUM2 2 ++#define PART_NUM3 3 ++#define PART_NUM4 4 ++#define PART_NUM5 5 ++#define PART_NUM6 6 ++#define PART_NUM7 7 ++ ++#define VERSION_NUM _SFR_MEM8(0x15D) ++#define VERSION_NUM0 0 ++#define VERSION_NUM1 1 ++#define VERSION_NUM2 2 ++#define VERSION_NUM3 3 ++#define VERSION_NUM4 4 ++#define VERSION_NUM5 5 ++#define VERSION_NUM6 6 ++#define VERSION_NUM7 7 ++ ++#define MAN_ID_0 _SFR_MEM8(0x15E) ++#define MAN_ID_00 0 ++#define MAN_ID_01 1 ++#define MAN_ID_02 2 ++#define MAN_ID_03 3 ++#define MAN_ID_04 4 ++#define MAN_ID_05 5 ++#define MAN_ID_06 6 ++#define MAN_ID_07 7 ++ ++#define MAN_ID_1 _SFR_MEM8(0x15F) ++#define MAN_ID_10 0 ++#define MAN_ID_11 1 ++#define MAN_ID_12 2 ++#define MAN_ID_13 3 ++#define MAN_ID_14 4 ++#define MAN_ID_15 5 ++#define MAN_ID_16 6 ++#define MAN_ID_17 7 ++ ++#define SHORT_ADDR_0 _SFR_MEM8(0x160) ++#define SHORT_ADDR_00 0 ++#define SHORT_ADDR_01 1 ++#define SHORT_ADDR_02 2 ++#define SHORT_ADDR_03 3 ++#define SHORT_ADDR_04 4 ++#define SHORT_ADDR_05 5 ++#define SHORT_ADDR_06 6 ++#define SHORT_ADDR_07 7 ++ ++#define SHORT_ADDR_1 _SFR_MEM8(0x161) ++#define SHORT_ADDR_10 0 ++#define SHORT_ADDR_11 1 ++#define SHORT_ADDR_12 2 ++#define SHORT_ADDR_13 3 ++#define SHORT_ADDR_14 4 ++#define SHORT_ADDR_15 5 ++#define SHORT_ADDR_16 6 ++#define SHORT_ADDR_17 7 ++ ++#define PAN_ID_0 _SFR_MEM8(0x162) ++#define PAN_ID_00 0 ++#define PAN_ID_01 1 ++#define PAN_ID_02 2 ++#define PAN_ID_03 3 ++#define PAN_ID_04 4 ++#define PAN_ID_05 5 ++#define PAN_ID_06 6 ++#define PAN_ID_07 7 ++ ++#define PAN_ID_1 _SFR_MEM8(0x163) ++#define PAN_ID_10 0 ++#define PAN_ID_11 1 ++#define PAN_ID_12 2 ++#define PAN_ID_13 3 ++#define PAN_ID_14 4 ++#define PAN_ID_15 5 ++#define PAN_ID_16 6 ++#define PAN_ID_17 7 ++ ++#define IEEE_ADDR_0 _SFR_MEM8(0x164) ++#define IEEE_ADDR_00 0 ++#define IEEE_ADDR_01 1 ++#define IEEE_ADDR_02 2 ++#define IEEE_ADDR_03 3 ++#define IEEE_ADDR_04 4 ++#define IEEE_ADDR_05 5 ++#define IEEE_ADDR_06 6 ++#define IEEE_ADDR_07 7 ++ ++#define IEEE_ADDR_1 _SFR_MEM8(0x165) ++#define IEEE_ADDR_10 0 ++#define IEEE_ADDR_11 1 ++#define IEEE_ADDR_12 2 ++#define IEEE_ADDR_13 3 ++#define IEEE_ADDR_14 4 ++#define IEEE_ADDR_15 5 ++#define IEEE_ADDR_16 6 ++#define IEEE_ADDR_17 7 ++ ++#define IEEE_ADDR_2 _SFR_MEM8(0x166) ++#define IEEE_ADDR_20 0 ++#define IEEE_ADDR_21 1 ++#define IEEE_ADDR_22 2 ++#define IEEE_ADDR_23 3 ++#define IEEE_ADDR_24 4 ++#define IEEE_ADDR_25 5 ++#define IEEE_ADDR_26 6 ++#define IEEE_ADDR_27 7 ++ ++#define IEEE_ADDR_3 _SFR_MEM8(0x167) ++#define IEEE_ADDR_30 0 ++#define IEEE_ADDR_31 1 ++#define IEEE_ADDR_32 2 ++#define IEEE_ADDR_33 3 ++#define IEEE_ADDR_34 4 ++#define IEEE_ADDR_35 5 ++#define IEEE_ADDR_36 6 ++#define IEEE_ADDR_37 7 ++ ++#define IEEE_ADDR_4 _SFR_MEM8(0x168) ++#define IEEE_ADDR_40 0 ++#define IEEE_ADDR_41 1 ++#define IEEE_ADDR_42 2 ++#define IEEE_ADDR_43 3 ++#define IEEE_ADDR_44 4 ++#define IEEE_ADDR_45 5 ++#define IEEE_ADDR_46 6 ++#define IEEE_ADDR_47 7 ++ ++#define IEEE_ADDR_5 _SFR_MEM8(0x169) ++#define IEEE_ADDR_50 0 ++#define IEEE_ADDR_51 1 ++#define IEEE_ADDR_52 2 ++#define IEEE_ADDR_53 3 ++#define IEEE_ADDR_54 4 ++#define IEEE_ADDR_55 5 ++#define IEEE_ADDR_56 6 ++#define IEEE_ADDR_57 7 ++ ++#define IEEE_ADDR_6 _SFR_MEM8(0x16A) ++#define IEEE_ADDR_60 0 ++#define IEEE_ADDR_61 1 ++#define IEEE_ADDR_62 2 ++#define IEEE_ADDR_63 3 ++#define IEEE_ADDR_64 4 ++#define IEEE_ADDR_65 5 ++#define IEEE_ADDR_66 6 ++#define IEEE_ADDR_67 7 ++ ++#define IEEE_ADDR_7 _SFR_MEM8(0x16B) ++#define IEEE_ADDR_70 0 ++#define IEEE_ADDR_71 1 ++#define IEEE_ADDR_72 2 ++#define IEEE_ADDR_73 3 ++#define IEEE_ADDR_74 4 ++#define IEEE_ADDR_75 5 ++#define IEEE_ADDR_76 6 ++#define IEEE_ADDR_77 7 ++ ++#define XAH_CTRL_0 _SFR_MEM8(0x16C) ++#define SLOTTED_OPERATION 0 ++#define MAX_CSMA_RETRIES0 1 ++#define MAX_CSMA_RETRIES1 2 ++#define MAX_CSMA_RETRIES2 3 ++#define MAX_FRAME_RETRIES0 4 ++#define MAX_FRAME_RETRIES1 5 ++#define MAX_FRAME_RETRIES2 6 ++#define MAX_FRAME_RETRIES3 7 ++ ++#define CSMA_SEED_0 _SFR_MEM8(0x16D) ++#define CSMA_SEED_00 0 ++#define CSMA_SEED_01 1 ++#define CSMA_SEED_02 2 ++#define CSMA_SEED_03 3 ++#define CSMA_SEED_04 4 ++#define CSMA_SEED_05 5 ++#define CSMA_SEED_06 6 ++#define CSMA_SEED_07 7 ++ ++#define CSMA_SEED_1 _SFR_MEM8(0x16E) ++#define CSMA_SEED_10 0 ++#define CSMA_SEED_11 1 ++#define CSMA_SEED_12 2 ++#define AACK_I_AM_COORD 3 ++#define AACK_DIS_ACK 4 ++#define AACK_SET_PD 5 ++#define AACK_FVN_MODE0 6 ++#define AACK_FVN_MODE1 7 ++ ++#define CSMA_BE _SFR_MEM8(0x16F) ++#define MIN_BE0 0 ++#define MIN_BE1 1 ++#define MIN_BE2 2 ++#define MIN_BE3 3 ++#define MAX_BE0 4 ++#define MAX_BE1 5 ++#define MAX_BE2 6 ++#define MAX_BE3 7 ++ ++/* Reserved [0x170..0x175] */ ++ ++#define TST_CTRL_DIGI _SFR_MEM8(0x176) ++#define TST_CTRL_DIG0 0 ++#define TST_CTRL_DIG1 1 ++#define TST_CTRL_DIG2 2 ++#define TST_CTRL_DIG3 3 ++ ++/* Reserved [0x177..0x17A] */ ++ ++#define TST_RX_LENGTH _SFR_MEM8(0x17B) ++#define RX_LENGTH0 0 ++#define RX_LENGTH1 1 ++#define RX_LENGTH2 2 ++#define RX_LENGTH3 3 ++#define RX_LENGTH4 4 ++#define RX_LENGTH5 5 ++#define RX_LENGTH6 6 ++#define RX_LENGTH7 7 ++ ++/* Reserved [0x17C..0x17F] */ ++ ++#define TRXFBST _SFR_MEM8(0x180) ++ ++/* Reserved [0x181..0x1FE] */ ++ ++#define TRXFBEND _SFR_MEM8(0x1FF) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect _VECTOR(3) ++#define INT2_vect_num 3 ++ ++/* External Interrupt Request 3 */ ++#define INT3_vect _VECTOR(4) ++#define INT3_vect_num 4 ++ ++/* External Interrupt Request 4 */ ++#define INT4_vect _VECTOR(5) ++#define INT4_vect_num 5 ++ ++/* External Interrupt Request 5 */ ++#define INT5_vect _VECTOR(6) ++#define INT5_vect_num 6 ++ ++/* External Interrupt Request 6 */ ++#define INT6_vect _VECTOR(7) ++#define INT6_vect_num 7 ++ ++/* External Interrupt Request 7 */ ++#define INT7_vect _VECTOR(8) ++#define INT7_vect_num 8 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(9) ++#define PCINT0_vect_num 9 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(10) ++#define PCINT1_vect_num 10 ++ ++/* Pin Change Interrupt Request 2 */ ++#define PCINT2_vect _VECTOR(11) ++#define PCINT2_vect_num 11 ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect _VECTOR(12) ++#define WDT_vect_num 12 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPA_vect _VECTOR(13) ++#define TIMER2_COMPA_vect_num 13 ++ ++/* Timer/Counter2 Compare Match B */ ++#define TIMER2_COMPB_vect _VECTOR(14) ++#define TIMER2_COMPB_vect_num 14 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(15) ++#define TIMER2_OVF_vect_num 15 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(16) ++#define TIMER1_CAPT_vect_num 16 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(17) ++#define TIMER1_COMPA_vect_num 17 ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(18) ++#define TIMER1_COMPB_vect_num 18 ++ ++/* Timer/Counter1 Compare Match C */ ++#define TIMER1_COMPC_vect _VECTOR(19) ++#define TIMER1_COMPC_vect_num 19 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(20) ++#define TIMER1_OVF_vect_num 20 ++ ++/* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPA_vect _VECTOR(21) ++#define TIMER0_COMPA_vect_num 21 ++ ++/* Timer/Counter0 Compare Match B */ ++#define TIMER0_COMPB_vect _VECTOR(22) ++#define TIMER0_COMPB_vect_num 22 ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(23) ++#define TIMER0_OVF_vect_num 23 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(24) ++#define SPI_STC_vect_num 24 ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect _VECTOR(25) ++#define USART0_RX_vect_num 25 ++ ++/* USART0 Data register Empty */ ++#define USART0_UDRE_vect _VECTOR(26) ++#define USART0_UDRE_vect_num 26 ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect _VECTOR(27) ++#define USART0_TX_vect_num 27 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(28) ++#define ANALOG_COMP_vect_num 28 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(29) ++#define ADC_vect_num 29 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(30) ++#define EE_READY_vect_num 30 ++ ++/* Timer/Counter3 Capture Event */ ++#define TIMER3_CAPT_vect _VECTOR(31) ++#define TIMER3_CAPT_vect_num 31 ++ ++/* Timer/Counter3 Compare Match A */ ++#define TIMER3_COMPA_vect _VECTOR(32) ++#define TIMER3_COMPA_vect_num 32 ++ ++/* Timer/Counter3 Compare Match B */ ++#define TIMER3_COMPB_vect _VECTOR(33) ++#define TIMER3_COMPB_vect_num 33 ++ ++/* Timer/Counter3 Compare Match C */ ++#define TIMER3_COMPC_vect _VECTOR(34) ++#define TIMER3_COMPC_vect_num 34 ++ ++/* Timer/Counter3 Overflow */ ++#define TIMER3_OVF_vect _VECTOR(35) ++#define TIMER3_OVF_vect_num 35 ++ ++/* USART1, Rx Complete */ ++#define USART1_RX_vect _VECTOR(36) ++#define USART1_RX_vect_num 36 ++ ++/* USART1 Data register Empty */ ++#define USART1_UDRE_vect _VECTOR(37) ++#define USART1_UDRE_vect_num 37 ++ ++/* USART1, Tx Complete */ ++#define USART1_TX_vect _VECTOR(38) ++#define USART1_TX_vect_num 38 ++ ++/* 2-wire Serial Interface */ ++#define TWI_vect _VECTOR(39) ++#define TWI_vect_num 39 ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect _VECTOR(40) ++#define SPM_READY_vect_num 40 ++ ++/* Timer/Counter4 Capture Event */ ++#define TIMER4_CAPT_vect _VECTOR(41) ++#define TIMER4_CAPT_vect_num 41 ++ ++/* Timer/Counter4 Compare Match A */ ++#define TIMER4_COMPA_vect _VECTOR(42) ++#define TIMER4_COMPA_vect_num 42 ++ ++/* Timer/Counter4 Compare Match B */ ++#define TIMER4_COMPB_vect _VECTOR(43) ++#define TIMER4_COMPB_vect_num 43 ++ ++/* Timer/Counter4 Compare Match C */ ++#define TIMER4_COMPC_vect _VECTOR(44) ++#define TIMER4_COMPC_vect_num 44 ++ ++/* Timer/Counter4 Overflow */ ++#define TIMER4_OVF_vect _VECTOR(45) ++#define TIMER4_OVF_vect_num 45 ++ ++/* Timer/Counter5 Capture Event */ ++#define TIMER5_CAPT_vect _VECTOR(46) ++#define TIMER5_CAPT_vect_num 46 ++ ++/* Timer/Counter5 Compare Match A */ ++#define TIMER5_COMPA_vect _VECTOR(47) ++#define TIMER5_COMPA_vect_num 47 ++ ++/* Timer/Counter5 Compare Match B */ ++#define TIMER5_COMPB_vect _VECTOR(48) ++#define TIMER5_COMPB_vect_num 48 ++ ++/* Timer/Counter5 Compare Match C */ ++#define TIMER5_COMPC_vect _VECTOR(49) ++#define TIMER5_COMPC_vect_num 49 ++ ++/* Timer/Counter5 Overflow */ ++#define TIMER5_OVF_vect _VECTOR(50) ++#define TIMER5_OVF_vect_num 50 ++ ++/* TRX24 - PLL lock interrupt */ ++#define TRX24_PLL_LOCK_vect _VECTOR(57) ++#define TRX24_PLL_LOCK_vect_num 57 ++ ++/* TRX24 - PLL unlock interrupt */ ++#define TRX24_PLL_UNLOCK_vect _VECTOR(58) ++#define TRX24_PLL_UNLOCK_vect_num 58 ++ ++/* TRX24 - Receive start interrupt */ ++#define TRX24_RX_START_vect _VECTOR(59) ++#define TRX24_RX_START_vect_num 59 ++ ++/* TRX24 - RX_END interrupt */ ++#define TRX24_RX_END_vect _VECTOR(60) ++#define TRX24_RX_END_vect_num 60 ++ ++/* TRX24 - CCA/ED done interrupt */ ++#define TRX24_CCA_ED_DONE_vect _VECTOR(61) ++#define TRX24_CCA_ED_DONE_vect_num 61 ++ ++/* TRX24 - XAH - AMI */ ++#define TRX24_XAH_AMI_vect _VECTOR(62) ++#define TRX24_XAH_AMI_vect_num 62 ++ ++/* TRX24 - TX_END interrupt */ ++#define TRX24_TX_END_vect _VECTOR(63) ++#define TRX24_TX_END_vect_num 63 ++ ++/* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */ ++#define TRX24_AWAKE_vect _VECTOR(64) ++#define TRX24_AWAKE_vect_num 64 ++ ++/* Symbol counter - compare match 1 interrupt */ ++#define SCNT_CMP1_vect _VECTOR(65) ++#define SCNT_CMP1_vect_num 65 ++ ++/* Symbol counter - compare match 2 interrupt */ ++#define SCNT_CMP2_vect _VECTOR(66) ++#define SCNT_CMP2_vect_num 66 ++ ++/* Symbol counter - compare match 3 interrupt */ ++#define SCNT_CMP3_vect _VECTOR(67) ++#define SCNT_CMP3_vect_num 67 ++ ++/* Symbol counter - overflow interrupt */ ++#define SCNT_OVFL_vect _VECTOR(68) ++#define SCNT_OVFL_vect_num 68 ++ ++/* Symbol counter - backoff interrupt */ ++#define SCNT_BACKOFF_vect _VECTOR(69) ++#define SCNT_BACKOFF_vect_num 69 ++ ++/* AES engine ready interrupt */ ++#define AES_READY_vect _VECTOR(70) ++#define AES_READY_vect_num 70 ++ ++/* Battery monitor indicates supply voltage below threshold */ ++#define BAT_LOW_vect _VECTOR(71) ++#define BAT_LOW_vect_num 71 ++ ++/* TRX24 TX start interrupt */ ++#define TRX24_TX_START_vect _VECTOR(72) ++#define TRX24_TX_START_vect_num 72 ++ ++/* Address match interrupt of address filter 0 */ ++#define TRX24_AMI0_vect _VECTOR(73) ++#define TRX24_AMI0_vect_num 73 ++ ++/* Address match interrupt of address filter 1 */ ++#define TRX24_AMI1_vect _VECTOR(74) ++#define TRX24_AMI1_vect_num 74 ++ ++/* Address match interrupt of address filter 2 */ ++#define TRX24_AMI2_vect _VECTOR(75) ++#define TRX24_AMI2_vect_num 75 ++ ++/* Address match interrupt of address filter 3 */ ++#define TRX24_AMI3_vect _VECTOR(76) ++#define TRX24_AMI3_vect_num 76 ++ ++#define _VECTORS_SIZE 308 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 256 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x3FFFF ++#define RAMSTART 0x0200 ++#define RAMSIZE 32768 ++#define RAMEND 0x81FF ++#define E2START 0 ++#define E2SIZE 8192 ++#define E2PAGESIZE 8 ++#define E2END 0x1FFF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL_SUT0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL_SUT1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL_SUT2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL_SUT3 (unsigned char)~_BV(3) ++#define FUSE_CKSEL_SUT4 (unsigned char)~_BV(4) ++#define FUSE_CKSEL_SUT5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0xA8 ++#define SIGNATURE_2 0x02 ++ ++ ++#endif /* #ifdef _AVR_ATMEGA256RFR2_H_INCLUDED */ ++ +diff --git a/include/avr/iom3000.h b/include/avr/iom3000.h +index 61f63e3..8ebd1ea 100644 +--- a/include/avr/iom3000.h ++++ b/include/avr/iom3000.h +@@ -1,236 +1,237 @@ +-/* Copyright (c) 2010, Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id$ */ +- +-/* avr/iom3000.h - definitions for M3000 from Intelligent Motion Systems . */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom3000.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_IOM3000_H_ +-#define _AVR_IOM3000_H_ 1 +- +-/* Registers and associated bit numbers */ +- +-#define IPD _SFR_IO16(0x00) +-#define IPDL _SFR_IO8(0x00) +-#define IPDH _SFR_IO8(0x01) +-#define IPA _SFR_IO16(0x02) +-#define IPAL _SFR_IO8(0x02) +-#define IPAH _SFR_IO8(0x03) +-#define IPCR _SFR_IO8(0x04) +-#define ADRSLT _SFR_IO16(0x05) +-#define ADRSLTL _SFR_IO8(0x05) /* Alias. */ +-#define ADRSLTH _SFR_IO8(0x06) /* Alias. */ +-#define ADRSLTLO _SFR_IO8(0x05) /* Name according to datasheet. */ +-#define ADRSLTHI _SFR_IO8(0x06) /* Name according to datasheet. */ +-#define ADCSR _SFR_IO8(0x07) +-#define AMUXCTL _SFR_IO8(0x0B) +-#define MSPCR _SFR_IO8(0x0C) +-#define USPCR _SFR_IO8(0x0C) +-#define MSPSR _SFR_IO8(0x0D) +-#define USPSR _SFR_IO8(0x0D) +-#define MSPDR _SFR_IO8(0x0E) +-#define USPDR _SFR_IO8(0x0E) +-#define WDTCR _SFR_IO8(0x0F) +-#define USR _SFR_IO8(0x11) +-#define UCRA _SFR_IO8(0x12) +-#define UCRB _SFR_IO8(0x13) +-#define UBRR _SFR_IO8(0x14) +-#define UBRRL _SFR_IO8(0x14) /* Alias. */ +-#define UBRRH _SFR_IO8(0x15) /* Alias. */ +-#define UBRRLO _SFR_IO8(0x14) /* Name according to datasheet. */ +-#define UBRRHI _SFR_IO8(0x15) /* Name according to datasheet. */ +-#define GIFR _SFR_IO8(0x16) +-#define GIMSK _SFR_IO8(0x17) +-#define DACVAL _SFR_IO16(0x18) +-#define DACVALL _SFR_IO8(0x18) /* Alias. */ +-#define DACVALH _SFR_IO8(0x19) /* Alias. */ +-#define DACVALLO _SFR_IO8(0x18) /* Name according to datasheet. */ +-#define DACVALHI _SFR_IO8(0x19) /* Name according to datasheet. */ +-#define BGPPIN _SFR_IO8(0x1A) +-#define BGPDDR _SFR_IO8(0x1B) +-#define BGPPORT _SFR_IO8(0x1C) +-#define AGPPIN _SFR_IO8(0x1D) +-#define AGPDDR _SFR_IO8(0x1E) +-#define AGPPORT _SFR_IO8(0x1F) +-#define EXTCCR1A _SFR_IO8(0x20) +-#define EXTCCR1B _SFR_IO8(0x21) +-#define EXTCNT1 _SFR_IO16(0x22) +-#define EXTCNT1L _SFR_IO8(0x22) +-#define EXTCNT1H _SFR_IO8(0x23) +-#define EXOCR1A _SFR_IO16(0x24) +-#define EXOCR1AL _SFR_IO8(0x24) +-#define EXOCR1AH _SFR_IO8(0x25) +-#define EXOCR1B _SFR_IO16(0x26) +-#define EXOCR1BL _SFR_IO8(0x26) +-#define EXOCR1BH _SFR_IO8(0x27) +-#define EXTIFR _SFR_IO8(0x2A) +-#define EXTIMSK _SFR_IO8(0x2B) +-#define EXTCNT _SFR_IO8(0x2C) +-#define EXTCCR0 _SFR_IO8(0x2D) +-#define CGPPIN _SFR_IO8(0x30) +-#define CGPDDR _SFR_IO8(0x31) +-#define CGPPORT _SFR_IO8(0x32) +-#define MCSR _SFR_IO8(0x33) +- +- +-#define CDIVCAN _SFR_MEM8(0x100) +-#define CBTR1 _SFR_MEM8(0x101) +-#define CBTR2 _SFR_MEM8(0x102) +-#define CBTR3 _SFR_MEM8(0x103) +-#define CMCR _SFR_MEM8(0x104) +-#define CRAFEN _SFR_MEM8(0x105) +-#define CTARR _SFR_MEM8(0x106) +-#define CIER _SFR_MEM8(0x107) +-#define CCFLG _SFR_MEM8(0x108) +-#define CCISR _SFR_MEM8(0x109) +-#define CIDAH0 _SFR_MEM8(0x10A) +-#define CIDAH1 _SFR_MEM8(0x10B) +-#define CEFR _SFR_MEM8(0x10C) +-#define CRXERR _SFR_MEM8(0x10D) +-#define CTXERR _SFR_MEM8(0x10E) +-#define CVER _SFR_MEM8(0x10F) +-#define CIDAC0R _SFR_MEM32(0x110) +-#define CIDM0R _SFR_MEM32(0x114) +-#define CIDAC1R _SFR_MEM32(0x118) +-#define CIDM1R _SFR_MEM32(0x11C) +-#define CIDAC2R _SFR_MEM32(0x120) +-#define CIDM2R _SFR_MEM32(0x124) +-#define CIDAC3R _SFR_MEM32(0x128) +-#define CIDM3R _SFR_MEM32(0x12C) +-#define CIDAC4R _SFR_MEM32(0x130) +-#define CIDM4R _SFR_MEM32(0x134) +-#define CIDAC5R _SFR_MEM32(0x138) +-#define CIDM5R _SFR_MEM32(0x13C) +-#define CIDAC6R _SFR_MEM32(0x140) +-#define CIDM6R _SFR_MEM32(0x144) +-#define CTXB0 ((volatile uint8_t [16])(0x150)) +-#define CTXB1 ((volatile uint8_t [16])(0x160)) +-#define CTXB2 ((volatile uint8_t [16])(0x170)) +-#define CRXB0 ((volatile uint8_t [16])(0x180)) +-#define CRXB1 ((volatile uint8_t [16])(0x190)) +-#define PWMMSK _SFR_MEM8(0x200) +-#define PWMPER _SFR_MEM8(0x201) +-#define PWMSFRQ _SFR_MEM8(0x202) +-#define PWMCTL _SFR_MEM8(0x203) +-#define CURIRUN _SFR_MEM8(0x204) +-#define CURIRED _SFR_MEM8(0x205) +-#define CURRDLY _SFR_MEM16(0x206) +-#define VELLOW1 _SFR_MEM8(0x208) +-#define VELLOW2 _SFR_MEM8(0x209) +-#define VELLOW3 _SFR_MEM8(0x20A) +-#define VELHI1 _SFR_MEM8(0x20B) +-#define VELHI2 _SFR_MEM8(0x20C) +-#define VELHI3 _SFR_MEM8(0x20D) +-#define VELDEC1 _SFR_MEM8(0x20E) +-#define VELDEC2 _SFR_MEM8(0x20F) +-#define VELDEC3 _SFR_MEM8(0x210) +-#define VELACC1 _SFR_MEM8(0x211) +-#define VELACC2 _SFR_MEM8(0x212) +-#define VELACC3 _SFR_MEM8(0x213) +-#define VELCVEL _SFR_MEM8(0x214) +-/* +-#define VELCVEL _SFR_MEM8(0x215) +-#define VELCVEL _SFR_MEM8(0x216) +-*/ +-#define VELTVEL _SFR_MEM8(0x217) +-/* +-#define VELTVEL _SFR_MEM8(0x218) +-#define VELTVEL _SFR_MEM8(0x219) +-*/ +-#define VELVGCTL _SFR_MEM8(0x21A) +-#define VELSTB _SFR_MEM8(0x21B) +-#define VELIFLG _SFR_MEM8(0x21C) +-#define VELIMSK _SFR_MEM8(0x21D) +-#define IDXTRT _SFR_MEM32(0x21E) +-#define IDXENT _SFR_MEM32(0x222) +-#define IDXMSDT _SFR_MEM16(0x226) +-#define IDXPOT _SFR_MEM32(0x228) +-#define IDXPOS _SFR_MEM32(0x22C) +-#define IDXENC _SFR_MEM32(0x230) +-#define IDXCTRL _SFR_MEM8(0x234) +-#define IDXSTRB _SFR_MEM8(0x235) +-#define IDXCPTP _SFR_MEM32(0x236) +-#define IDXIFLG _SFR_MEM8(0x23A) +-#define IDXIMSK _SFR_MEM8(0x23B) +-#define SCIO _SFR_MEM8(0x23C) +-#define SCSW _SFR_MEM8(0x23D) +-#define SCRF _SFR_MEM32(0x23E) +-#define IOF _SFR_MEM8(0x242) +-#define MSELR _SFR_MEM8(0x243) +-#define STAT _SFR_MEM8(0x244) +-#define SPWMCTL _SFR_MEM8(0x245) +-#define SINDAC _SFR_MEM16(0x280) +-#define SINDACL _SFR_MEM8(0x280) +-#define SINDACH _SFR_MEM8(0x281) +-#define COSDAC _SFR_MEM8(0x282) +-#define COSDACL _SFR_MEM8(0x282) +-#define COSDACH _SFR_MEM8(0x283) +-#define GAINDAC _SFR_MEM8(0x284) +-#define DACCTRL _SFR_MEM8(0x285) +-#define INTCCR1A _SFR_MEM8(0x800) +-#define INTCCR1B _SFR_MEM8(0x801) +-#define INTCNT1 _SFR_MEM16(0x802) +-#define INTCNT1L _SFR_MEM8(0x802) +-#define INTCNT1H _SFR_MEM8(0x803) +-#define INOCR1A _SFR_MEM16(0x804) +-#define INOCR1AL _SFR_MEM8(0x804) +-#define INOCR1AH _SFR_MEM8(0x805) +-#define INOCR1B _SFR_MEM16(0x806) /* Data sheet says 0x807-0x808, but I believe this is wrong due to conflict with INTCNT. */ +-#define INOCR1BL _SFR_MEM8(0x806) +-#define INOCR1BH _SFR_MEM8(0x807) +-#define INTCNT _SFR_MEM8(0x808) +-#define INTCCR0 _SFR_MEM8(0x809) +-#define INTIFR _SFR_MEM8(0x80A) +-#define INTIMSK _SFR_MEM8(0x80B) +- +- +-/* Constants */ +-#define RAMEND 0xFFF /* Last On-Chip SRAM Location */ +-#define E2END 0x0 +-#define E2PAGESIZE 0 +-#define FLASHEND 0xFFFF +-#define _VECTORS_SIZE 0 +- +- +-#endif /* _AVR_IOM3000_H_ */ +- ++/* Copyright (c) 2010, Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id$ */ ++ ++/* avr/iom3000.h - definitions for M3000 from Intelligent Motion Systems . */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom3000.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_IOM3000_H_ ++#define _AVR_IOM3000_H_ 1 ++ ++/* Registers and associated bit numbers */ ++ ++#define IPD _SFR_IO16(0x00) ++#define IPDL _SFR_IO8(0x00) ++#define IPDH _SFR_IO8(0x01) ++#define IPA _SFR_IO16(0x02) ++#define IPAL _SFR_IO8(0x02) ++#define IPAH _SFR_IO8(0x03) ++#define IPCR _SFR_IO8(0x04) ++#define ADRSLT _SFR_IO16(0x05) ++#define ADRSLTL _SFR_IO8(0x05) /* Alias. */ ++#define ADRSLTH _SFR_IO8(0x06) /* Alias. */ ++#define ADRSLTLO _SFR_IO8(0x05) /* Name according to datasheet. */ ++#define ADRSLTHI _SFR_IO8(0x06) /* Name according to datasheet. */ ++#define ADCSR _SFR_IO8(0x07) ++#define AMUXCTL _SFR_IO8(0x0B) ++#define MSPCR _SFR_IO8(0x0C) ++#define USPCR _SFR_IO8(0x0C) ++#define MSPSR _SFR_IO8(0x0D) ++#define USPSR _SFR_IO8(0x0D) ++#define MSPDR _SFR_IO8(0x0E) ++#define USPDR _SFR_IO8(0x0E) ++#define WDTCR _SFR_IO8(0x0F) ++#define USR _SFR_IO8(0x11) ++#define UCRA _SFR_IO8(0x12) ++#define UCRB _SFR_IO8(0x13) ++#define UBRR _SFR_IO8(0x14) ++#define UBRRL _SFR_IO8(0x14) /* Alias. */ ++#define UBRRH _SFR_IO8(0x15) /* Alias. */ ++#define UBRRLO _SFR_IO8(0x14) /* Name according to datasheet. */ ++#define UBRRHI _SFR_IO8(0x15) /* Name according to datasheet. */ ++#define GIFR _SFR_IO8(0x16) ++#define GIMSK _SFR_IO8(0x17) ++#define DACVAL _SFR_IO16(0x18) ++#define DACVALL _SFR_IO8(0x18) /* Alias. */ ++#define DACVALH _SFR_IO8(0x19) /* Alias. */ ++#define DACVALLO _SFR_IO8(0x18) /* Name according to datasheet. */ ++#define DACVALHI _SFR_IO8(0x19) /* Name according to datasheet. */ ++#define BGPPIN _SFR_IO8(0x1A) ++#define BGPDDR _SFR_IO8(0x1B) ++#define BGPPORT _SFR_IO8(0x1C) ++#define AGPPIN _SFR_IO8(0x1D) ++#define AGPDDR _SFR_IO8(0x1E) ++#define AGPPORT _SFR_IO8(0x1F) ++#define EXTCCR1A _SFR_IO8(0x20) ++#define EXTCCR1B _SFR_IO8(0x21) ++#define EXTCNT1 _SFR_IO16(0x22) ++#define EXTCNT1L _SFR_IO8(0x22) ++#define EXTCNT1H _SFR_IO8(0x23) ++#define EXOCR1A _SFR_IO16(0x24) ++#define EXOCR1AL _SFR_IO8(0x24) ++#define EXOCR1AH _SFR_IO8(0x25) ++#define EXOCR1B _SFR_IO16(0x26) ++#define EXOCR1BL _SFR_IO8(0x26) ++#define EXOCR1BH _SFR_IO8(0x27) ++#define EXTIFR _SFR_IO8(0x2A) ++#define EXTIMSK _SFR_IO8(0x2B) ++#define EXTCNT _SFR_IO8(0x2C) ++#define EXTCCR0 _SFR_IO8(0x2D) ++#define CGPPIN _SFR_IO8(0x30) ++#define CGPDDR _SFR_IO8(0x31) ++#define CGPPORT _SFR_IO8(0x32) ++#define MCSR _SFR_IO8(0x33) ++ ++ ++#define CDIVCAN _SFR_MEM8(0x100) ++#define CBTR1 _SFR_MEM8(0x101) ++#define CBTR2 _SFR_MEM8(0x102) ++#define CBTR3 _SFR_MEM8(0x103) ++#define CMCR _SFR_MEM8(0x104) ++#define CRAFEN _SFR_MEM8(0x105) ++#define CTARR _SFR_MEM8(0x106) ++#define CIER _SFR_MEM8(0x107) ++#define CCFLG _SFR_MEM8(0x108) ++#define CCISR _SFR_MEM8(0x109) ++#define CIDAH0 _SFR_MEM8(0x10A) ++#define CIDAH1 _SFR_MEM8(0x10B) ++#define CEFR _SFR_MEM8(0x10C) ++#define CRXERR _SFR_MEM8(0x10D) ++#define CTXERR _SFR_MEM8(0x10E) ++#define CVER _SFR_MEM8(0x10F) ++#define CIDAC0R _SFR_MEM32(0x110) ++#define CIDM0R _SFR_MEM32(0x114) ++#define CIDAC1R _SFR_MEM32(0x118) ++#define CIDM1R _SFR_MEM32(0x11C) ++#define CIDAC2R _SFR_MEM32(0x120) ++#define CIDM2R _SFR_MEM32(0x124) ++#define CIDAC3R _SFR_MEM32(0x128) ++#define CIDM3R _SFR_MEM32(0x12C) ++#define CIDAC4R _SFR_MEM32(0x130) ++#define CIDM4R _SFR_MEM32(0x134) ++#define CIDAC5R _SFR_MEM32(0x138) ++#define CIDM5R _SFR_MEM32(0x13C) ++#define CIDAC6R _SFR_MEM32(0x140) ++#define CIDM6R _SFR_MEM32(0x144) ++#define CTXB0 ((volatile uint8_t [16])(0x150)) ++#define CTXB1 ((volatile uint8_t [16])(0x160)) ++#define CTXB2 ((volatile uint8_t [16])(0x170)) ++#define CRXB0 ((volatile uint8_t [16])(0x180)) ++#define CRXB1 ((volatile uint8_t [16])(0x190)) ++#define PWMMSK _SFR_MEM8(0x200) ++#define PWMPER _SFR_MEM8(0x201) ++#define PWMSFRQ _SFR_MEM8(0x202) ++#define PWMCTL _SFR_MEM8(0x203) ++#define CURIRUN _SFR_MEM8(0x204) ++#define CURIRED _SFR_MEM8(0x205) ++#define CURRDLY _SFR_MEM16(0x206) ++#define VELLOW1 _SFR_MEM8(0x208) ++#define VELLOW2 _SFR_MEM8(0x209) ++#define VELLOW3 _SFR_MEM8(0x20A) ++#define VELHI1 _SFR_MEM8(0x20B) ++#define VELHI2 _SFR_MEM8(0x20C) ++#define VELHI3 _SFR_MEM8(0x20D) ++#define VELDEC1 _SFR_MEM8(0x20E) ++#define VELDEC2 _SFR_MEM8(0x20F) ++#define VELDEC3 _SFR_MEM8(0x210) ++#define VELACC1 _SFR_MEM8(0x211) ++#define VELACC2 _SFR_MEM8(0x212) ++#define VELACC3 _SFR_MEM8(0x213) ++#define VELCVEL _SFR_MEM8(0x214) ++/* ++#define VELCVEL _SFR_MEM8(0x215) ++#define VELCVEL _SFR_MEM8(0x216) ++*/ ++#define VELTVEL _SFR_MEM8(0x217) ++/* ++#define VELTVEL _SFR_MEM8(0x218) ++#define VELTVEL _SFR_MEM8(0x219) ++*/ ++#define VELVGCTL _SFR_MEM8(0x21A) ++#define VELSTB _SFR_MEM8(0x21B) ++#define VELIFLG _SFR_MEM8(0x21C) ++#define VELIMSK _SFR_MEM8(0x21D) ++#define IDXTRT _SFR_MEM32(0x21E) ++#define IDXENT _SFR_MEM32(0x222) ++#define IDXMSDT _SFR_MEM16(0x226) ++#define IDXPOT _SFR_MEM32(0x228) ++#define IDXPOS _SFR_MEM32(0x22C) ++#define IDXENC _SFR_MEM32(0x230) ++#define IDXCTRL _SFR_MEM8(0x234) ++#define IDXSTRB _SFR_MEM8(0x235) ++#define IDXCPTP _SFR_MEM32(0x236) ++#define IDXIFLG _SFR_MEM8(0x23A) ++#define IDXIMSK _SFR_MEM8(0x23B) ++#define SCIO _SFR_MEM8(0x23C) ++#define SCSW _SFR_MEM8(0x23D) ++#define SCRF _SFR_MEM32(0x23E) ++#define IOF _SFR_MEM8(0x242) ++#define MSELR _SFR_MEM8(0x243) ++#define STAT _SFR_MEM8(0x244) ++#define SPWMCTL _SFR_MEM8(0x245) ++#define SINDAC _SFR_MEM16(0x280) ++#define SINDACL _SFR_MEM8(0x280) ++#define SINDACH _SFR_MEM8(0x281) ++#define COSDAC _SFR_MEM8(0x282) ++#define COSDACL _SFR_MEM8(0x282) ++#define COSDACH _SFR_MEM8(0x283) ++#define GAINDAC _SFR_MEM8(0x284) ++#define DACCTRL _SFR_MEM8(0x285) ++#define INTCCR1A _SFR_MEM8(0x800) ++#define INTCCR1B _SFR_MEM8(0x801) ++#define INTCNT1 _SFR_MEM16(0x802) ++#define INTCNT1L _SFR_MEM8(0x802) ++#define INTCNT1H _SFR_MEM8(0x803) ++#define INOCR1A _SFR_MEM16(0x804) ++#define INOCR1AL _SFR_MEM8(0x804) ++#define INOCR1AH _SFR_MEM8(0x805) ++#define INOCR1B _SFR_MEM16(0x806) /* Data sheet says 0x807-0x808, but I believe this is wrong due to conflict with INTCNT. */ ++#define INOCR1BL _SFR_MEM8(0x806) ++#define INOCR1BH _SFR_MEM8(0x807) ++#define INTCNT _SFR_MEM8(0x808) ++#define INTCCR0 _SFR_MEM8(0x809) ++#define INTIFR _SFR_MEM8(0x80A) ++#define INTIMSK _SFR_MEM8(0x80B) ++ ++ ++/* Constants */ ++#define RAMSTART 0x1000 ++#define RAMEND 0x1FFF /* Last On-Chip SRAM Location */ ++#define E2END 0x0 ++#define E2PAGESIZE 0 ++#define FLASHEND 0xFFFF ++#define _VECTORS_SIZE 0 ++ ++ ++#endif /* _AVR_IOM3000_H_ */ ++ +diff --git a/include/avr/iom32.h b/include/avr/iom32.h +index d5aae07..c773964 100644 +--- a/include/avr/iom32.h ++++ b/include/avr/iom32.h +@@ -1,749 +1,749 @@ +-/* Copyright (c) 2002, Steinar Haugen +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom32.h 2233 2011-03-15 15:49:50Z arcanum $ */ +- +-/* avr/iom32.h - definitions for ATmega32 */ +- +-#ifndef _AVR_IOM32_H_ +-#define _AVR_IOM32_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom32.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ +-#define TWBR _SFR_IO8(0x00) +-#define TWSR _SFR_IO8(0x01) +-#define TWAR _SFR_IO8(0x02) +-#define TWDR _SFR_IO8(0x03) +- +-/* ADC */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x04) +-#endif +-#define ADCW _SFR_IO16(0x04) +-#define ADCL _SFR_IO8(0x04) +-#define ADCH _SFR_IO8(0x05) +-#define ADCSRA _SFR_IO8(0x06) +-#define ADMUX _SFR_IO8(0x07) +- +-/* analog comparator */ +-#define ACSR _SFR_IO8(0x08) +- +-/* USART */ +-#define UBRRL _SFR_IO8(0x09) +-#define UCSRB _SFR_IO8(0x0A) +-#define UCSRA _SFR_IO8(0x0B) +-#define UDR _SFR_IO8(0x0C) +- +-/* SPI */ +-#define SPCR _SFR_IO8(0x0D) +-#define SPSR _SFR_IO8(0x0E) +-#define SPDR _SFR_IO8(0x0F) +- +-/* Port D */ +-#define PIND _SFR_IO8(0x10) +-#define DDRD _SFR_IO8(0x11) +-#define PORTD _SFR_IO8(0x12) +- +-/* Port C */ +-#define PINC _SFR_IO8(0x13) +-#define DDRC _SFR_IO8(0x14) +-#define PORTC _SFR_IO8(0x15) +- +-/* Port B */ +-#define PINB _SFR_IO8(0x16) +-#define DDRB _SFR_IO8(0x17) +-#define PORTB _SFR_IO8(0x18) +- +-/* Port A */ +-#define PINA _SFR_IO8(0x19) +-#define DDRA _SFR_IO8(0x1A) +-#define PORTA _SFR_IO8(0x1B) +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO16(0x1E) +-#define EEARL _SFR_IO8(0x1E) +-#define EEARH _SFR_IO8(0x1F) +- +-#define UBRRH _SFR_IO8(0x20) +-#define UCSRC UBRRH +- +-#define WDTCR _SFR_IO8(0x21) +- +-#define ASSR _SFR_IO8(0x22) +- +-/* Timer 2 */ +-#define OCR2 _SFR_IO8(0x23) +-#define TCNT2 _SFR_IO8(0x24) +-#define TCCR2 _SFR_IO8(0x25) +- +-/* Timer 1 */ +-#define ICR1 _SFR_IO16(0x26) +-#define ICR1L _SFR_IO8(0x26) +-#define ICR1H _SFR_IO8(0x27) +-#define OCR1B _SFR_IO16(0x28) +-#define OCR1BL _SFR_IO8(0x28) +-#define OCR1BH _SFR_IO8(0x29) +-#define OCR1A _SFR_IO16(0x2A) +-#define OCR1AL _SFR_IO8(0x2A) +-#define OCR1AH _SFR_IO8(0x2B) +-#define TCNT1 _SFR_IO16(0x2C) +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1H _SFR_IO8(0x2D) +-#define TCCR1B _SFR_IO8(0x2E) +-#define TCCR1A _SFR_IO8(0x2F) +- +-#define SFIOR _SFR_IO8(0x30) +- +-#define OSCCAL _SFR_IO8(0x31) +-#define OCDR OSCCAL +- +-/* Timer 0 */ +-#define TCNT0 _SFR_IO8(0x32) +-#define TCCR0 _SFR_IO8(0x33) +- +-#define MCUSR _SFR_IO8(0x34) +-#define MCUCSR MCUSR +-#define MCUCR _SFR_IO8(0x35) +- +-#define TWCR _SFR_IO8(0x36) +- +-#define SPMCR _SFR_IO8(0x37) +- +-#define TIFR _SFR_IO8(0x38) +-#define TIMSK _SFR_IO8(0x39) +- +-#define GIFR _SFR_IO8(0x3A) +-#define GIMSK _SFR_IO8(0x3B) +-#define GICR GIMSK +- +-#define OCR0 _SFR_IO8(0x3C) +- +-/* 0x3D..0x3E SP */ +- +-/* 0x3F SREG */ +- +-/* Interrupt vectors */ +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt Request 1 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +-#define SIG_INTERRUPT1 _VECTOR(2) +- +-/* External Interrupt Request 2 */ +-#define INT2_vect_num 3 +-#define INT2_vect _VECTOR(3) +-#define SIG_INTERRUPT2 _VECTOR(3) +- +-/* Timer/Counter2 Compare Match */ +-#define TIMER2_COMP_vect_num 4 +-#define TIMER2_COMP_vect _VECTOR(4) +-#define SIG_OUTPUT_COMPARE2 _VECTOR(4) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 5 +-#define TIMER2_OVF_vect _VECTOR(5) +-#define SIG_OVERFLOW2 _VECTOR(5) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 6 +-#define TIMER1_CAPT_vect _VECTOR(6) +-#define SIG_INPUT_CAPTURE1 _VECTOR(6) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 7 +-#define TIMER1_COMPA_vect _VECTOR(7) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(7) +- +-/* Timer/Counter1 Compare Match B */ +-#define TIMER1_COMPB_vect_num 8 +-#define TIMER1_COMPB_vect _VECTOR(8) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(8) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 9 +-#define TIMER1_OVF_vect _VECTOR(9) +-#define SIG_OVERFLOW1 _VECTOR(9) +- +-/* Timer/Counter0 Compare Match */ +-#define TIMER0_COMP_vect_num 10 +-#define TIMER0_COMP_vect _VECTOR(10) +-#define SIG_OUTPUT_COMPARE0 _VECTOR(10) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 11 +-#define TIMER0_OVF_vect _VECTOR(11) +-#define SIG_OVERFLOW0 _VECTOR(11) +- +-/* Serial Transfer Complete */ +-#define SPI_STC_vect_num 12 +-#define SPI_STC_vect _VECTOR(12) +-#define SIG_SPI _VECTOR(12) +- +-/* USART, Rx Complete */ +-#define USART_RXC_vect_num 13 +-#define USART_RXC_vect _VECTOR(13) +-#define SIG_USART_RECV _VECTOR(13) +-#define SIG_UART_RECV _VECTOR(13) +- +-/* USART Data Register Empty */ +-#define USART_UDRE_vect_num 14 +-#define USART_UDRE_vect _VECTOR(14) +-#define SIG_USART_DATA _VECTOR(14) +-#define SIG_UART_DATA _VECTOR(14) +- +-/* USART, Tx Complete */ +-#define USART_TXC_vect_num 15 +-#define USART_TXC_vect _VECTOR(15) +-#define SIG_USART_TRANS _VECTOR(15) +-#define SIG_UART_TRANS _VECTOR(15) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 16 +-#define ADC_vect _VECTOR(16) +-#define SIG_ADC _VECTOR(16) +- +-/* EEPROM Ready */ +-#define EE_RDY_vect_num 17 +-#define EE_RDY_vect _VECTOR(17) +-#define SIG_EEPROM_READY _VECTOR(17) +- +-/* Analog Comparator */ +-#define ANA_COMP_vect_num 18 +-#define ANA_COMP_vect _VECTOR(18) +-#define SIG_COMPARATOR _VECTOR(18) +- +-/* 2-wire Serial Interface */ +-#define TWI_vect_num 19 +-#define TWI_vect _VECTOR(19) +-#define SIG_2WIRE_SERIAL _VECTOR(19) +- +-/* Store Program Memory Ready */ +-#define SPM_RDY_vect_num 20 +-#define SPM_RDY_vect _VECTOR(20) +-#define SIG_SPM_READY _VECTOR(20) +- +-#define _VECTORS_SIZE 84 +- +-/* Bit numbers */ +- +-/* GICR */ +-#define INT1 7 +-#define INT0 6 +-#define INT2 5 +-#define IVSEL 1 +-#define IVCE 0 +- +-/* GIFR */ +-#define INTF1 7 +-#define INTF0 6 +-#define INTF2 5 +- +-/* TIMSK */ +-#define OCIE2 7 +-#define TOIE2 6 +-#define TICIE1 5 +-#define OCIE1A 4 +-#define OCIE1B 3 +-#define TOIE1 2 +-#define OCIE0 1 +-#define TOIE0 0 +- +-/* TIFR */ +-#define OCF2 7 +-#define TOV2 6 +-#define ICF1 5 +-#define OCF1A 4 +-#define OCF1B 3 +-#define TOV1 2 +-#define OCF0 1 +-#define TOV0 0 +- +-/* SPMCR */ +-#define SPMIE 7 +-#define RWWSB 6 +-/* bit 5 reserved */ +-#define RWWSRE 4 +-#define BLBSET 3 +-#define PGWRT 2 +-#define PGERS 1 +-#define SPMEN 0 +- +-/* TWCR */ +-#define TWINT 7 +-#define TWEA 6 +-#define TWSTA 5 +-#define TWSTO 4 +-#define TWWC 3 +-#define TWEN 2 +-/* bit 1 reserved */ +-#define TWIE 0 +- +-/* TWAR */ +-#define TWA6 7 +-#define TWA5 6 +-#define TWA4 5 +-#define TWA3 4 +-#define TWA2 3 +-#define TWA1 2 +-#define TWA0 1 +-#define TWGCE 0 +- +-/* TWSR */ +-#define TWS7 7 +-#define TWS6 6 +-#define TWS5 5 +-#define TWS4 4 +-#define TWS3 3 +-/* bit 2 reserved */ +-#define TWPS1 1 +-#define TWPS0 0 +- +-/* MCUCR */ +-#define SE 7 +-#define SM2 6 +-#define SM1 5 +-#define SM0 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-/* MCUCSR */ +-#define JTD 7 +-#define ISC2 6 +-/* bit 5 reserved */ +-#define JTRF 4 +-#define WDRF 3 +-#define BORF 2 +-#define EXTRF 1 +-#define PORF 0 +- +-/* SFIOR */ +-#define ADTS2 7 +-#define ADTS1 6 +-#define ADTS0 5 +-/* bit 4 reserved */ +-#define ACME 3 +-#define PUD 2 +-#define PSR2 1 +-#define PSR10 0 +- +-/* TCCR0 */ +-#define FOC0 7 +-#define WGM00 6 +-#define COM01 5 +-#define COM00 4 +-#define WGM01 3 +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* TCCR2 */ +-#define FOC2 7 +-#define WGM20 6 +-#define COM21 5 +-#define COM20 4 +-#define WGM21 3 +-#define CS22 2 +-#define CS21 1 +-#define CS20 0 +- +-/* ASSR */ +-/* bits 7-4 reserved */ +-#define AS2 3 +-#define TCN2UB 2 +-#define OCR2UB 1 +-#define TCR2UB 0 +- +-/* TCCR1A */ +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define FOC1A 3 +-#define FOC1B 2 +-#define WGM11 1 +-#define WGM10 0 +- +-/* TCCR1B */ +-#define ICNC1 7 +-#define ICES1 6 +-/* bit 5 reserved */ +-#define WGM13 4 +-#define WGM12 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* WDTCR */ +-/* bits 7-5 reserved */ +-#define WDTOE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* PA7-PA0 = ADC7-ADC0 */ +-/* PORTA */ +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-/* DDRA */ +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-/* PINA */ +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-/* +- PB7 = SCK +- PB6 = MISO +- PB5 = MOSI +- PB4 = SS# +- PB3 = OC0/AIN1 +- PB2 = INT2/AIN0 +- PB1 = T1 +- PB0 = XCK/T0 +- */ +- +-/* PORTB */ +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* DDRB */ +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* PINB */ +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* +- PC7 = TOSC2 +- PC6 = TOSC1 +- PC1 = SDA +- PC0 = SCL +- */ +-/* PORTC */ +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-/* DDRC */ +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-/* PINC */ +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-/* +- PD7 = OC2 +- PD6 = ICP +- PD5 = OC1A +- PD4 = OC1B +- PD3 = INT1 +- PD2 = INT0 +- PD1 = TXD +- PD0 = RXD +- */ +- +-/* PORTD */ +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* DDRD */ +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-/* PIND */ +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-/* SPSR */ +-#define SPIF 7 +-#define WCOL 6 +-/* bits 5-1 reserved */ +-#define SPI2X 0 +- +-/* SPCR */ +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +-/* UCSRA */ +-#define RXC 7 +-#define TXC 6 +-#define UDRE 5 +-#define FE 4 +-#define DOR 3 +-#define PE 2 +-#define U2X 1 +-#define MPCM 0 +- +-/* UCSRB */ +-#define RXCIE 7 +-#define TXCIE 6 +-#define UDRIE 5 +-#define RXEN 4 +-#define TXEN 3 +-#define UCSZ2 2 +-#define RXB8 1 +-#define TXB8 0 +- +-/* UCSRC */ +-#define URSEL 7 +-#define UMSEL 6 +-#define UPM1 5 +-#define UPM0 4 +-#define USBS 3 +-#define UCSZ1 2 +-#define UCSZ0 1 +-#define UCPOL 0 +- +-/* ACSR */ +-#define ACD 7 +-#define ACBG 6 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +- +-/* ADCSRA */ +-#define ADEN 7 +-#define ADSC 6 +-#define ADATE 5 +-#define ADIF 4 +-#define ADIE 3 +-#define ADPS2 2 +-#define ADPS1 1 +-#define ADPS0 0 +- +-/* ADMUX */ +-#define REFS1 7 +-#define REFS0 6 +-#define ADLAR 5 +-#define MUX4 4 +-#define MUX3 3 +-#define MUX2 2 +-#define MUX1 1 +-#define MUX0 0 +- +-/* EEPROM Control Register */ +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-/* Constants */ +-#define SPM_PAGESIZE 128 +-#define RAMSTART (0x60) +-#define RAMEND 0x85F +-#define XRAMEND RAMEND +-#define E2END 0x3FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x7FFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 2 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_BODEN (unsigned char)~_BV(6) +-#define FUSE_BODLEVEL (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_CKOPT (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x95 +-#define SIGNATURE_2 0x02 +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_INTERRUPT1 +-#pragma GCC poison SIG_INTERRUPT2 +-#pragma GCC poison SIG_OUTPUT_COMPARE2 +-#pragma GCC poison SIG_OVERFLOW2 +-#pragma GCC poison SIG_INPUT_CAPTURE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OUTPUT_COMPARE0 +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_SPI +-#pragma GCC poison SIG_USART_RECV +-#pragma GCC poison SIG_UART_RECV +-#pragma GCC poison SIG_USART_DATA +-#pragma GCC poison SIG_UART_DATA +-#pragma GCC poison SIG_USART_TRANS +-#pragma GCC poison SIG_UART_TRANS +-#pragma GCC poison SIG_ADC +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_2WIRE_SERIAL +-#pragma GCC poison SIG_SPM_READY +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +-#endif /* _AVR_IOM32_H_ */ ++/* Copyright (c) 2002, Steinar Haugen ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom32.h 2233 2011-03-15 15:49:50Z arcanum $ */ ++ ++/* avr/iom32.h - definitions for ATmega32 */ ++ ++#ifndef _AVR_IOM32_H_ ++#define _AVR_IOM32_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom32.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ ++#define TWBR _SFR_IO8(0x00) ++#define TWSR _SFR_IO8(0x01) ++#define TWAR _SFR_IO8(0x02) ++#define TWDR _SFR_IO8(0x03) ++ ++/* ADC */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCW _SFR_IO16(0x04) ++#define ADCL _SFR_IO8(0x04) ++#define ADCH _SFR_IO8(0x05) ++#define ADCSRA _SFR_IO8(0x06) ++#define ADMUX _SFR_IO8(0x07) ++ ++/* analog comparator */ ++#define ACSR _SFR_IO8(0x08) ++ ++/* USART */ ++#define UBRRL _SFR_IO8(0x09) ++#define UCSRB _SFR_IO8(0x0A) ++#define UCSRA _SFR_IO8(0x0B) ++#define UDR _SFR_IO8(0x0C) ++ ++/* SPI */ ++#define SPCR _SFR_IO8(0x0D) ++#define SPSR _SFR_IO8(0x0E) ++#define SPDR _SFR_IO8(0x0F) ++ ++/* Port D */ ++#define PIND _SFR_IO8(0x10) ++#define DDRD _SFR_IO8(0x11) ++#define PORTD _SFR_IO8(0x12) ++ ++/* Port C */ ++#define PINC _SFR_IO8(0x13) ++#define DDRC _SFR_IO8(0x14) ++#define PORTC _SFR_IO8(0x15) ++ ++/* Port B */ ++#define PINB _SFR_IO8(0x16) ++#define DDRB _SFR_IO8(0x17) ++#define PORTB _SFR_IO8(0x18) ++ ++/* Port A */ ++#define PINA _SFR_IO8(0x19) ++#define DDRA _SFR_IO8(0x1A) ++#define PORTA _SFR_IO8(0x1B) ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO16(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++#define EEARH _SFR_IO8(0x1F) ++ ++#define UBRRH _SFR_IO8(0x20) ++#define UCSRC UBRRH ++ ++#define WDTCR _SFR_IO8(0x21) ++ ++#define ASSR _SFR_IO8(0x22) ++ ++/* Timer 2 */ ++#define OCR2 _SFR_IO8(0x23) ++#define TCNT2 _SFR_IO8(0x24) ++#define TCCR2 _SFR_IO8(0x25) ++ ++/* Timer 1 */ ++#define ICR1 _SFR_IO16(0x26) ++#define ICR1L _SFR_IO8(0x26) ++#define ICR1H _SFR_IO8(0x27) ++#define OCR1B _SFR_IO16(0x28) ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BH _SFR_IO8(0x29) ++#define OCR1A _SFR_IO16(0x2A) ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++#define TCNT1 _SFR_IO16(0x2C) ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++#define TCCR1B _SFR_IO8(0x2E) ++#define TCCR1A _SFR_IO8(0x2F) ++ ++#define SFIOR _SFR_IO8(0x30) ++ ++#define OSCCAL _SFR_IO8(0x31) ++#define OCDR OSCCAL ++ ++/* Timer 0 */ ++#define TCNT0 _SFR_IO8(0x32) ++#define TCCR0 _SFR_IO8(0x33) ++ ++#define MCUSR _SFR_IO8(0x34) ++#define MCUCSR MCUSR ++#define MCUCR _SFR_IO8(0x35) ++ ++#define TWCR _SFR_IO8(0x36) ++ ++#define SPMCR _SFR_IO8(0x37) ++ ++#define TIFR _SFR_IO8(0x38) ++#define TIMSK _SFR_IO8(0x39) ++ ++#define GIFR _SFR_IO8(0x3A) ++#define GIMSK _SFR_IO8(0x3B) ++#define GICR GIMSK ++ ++#define OCR0 _SFR_IO8(0x3C) ++ ++/* 0x3D..0x3E SP */ ++ ++/* 0x3F SREG */ ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++#define SIG_INTERRUPT1 _VECTOR(2) ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect_num 3 ++#define INT2_vect _VECTOR(3) ++#define SIG_INTERRUPT2 _VECTOR(3) ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect_num 4 ++#define TIMER2_COMP_vect _VECTOR(4) ++#define SIG_OUTPUT_COMPARE2 _VECTOR(4) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 5 ++#define TIMER2_OVF_vect _VECTOR(5) ++#define SIG_OVERFLOW2 _VECTOR(5) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 6 ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define SIG_INPUT_CAPTURE1 _VECTOR(6) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 7 ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(7) ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect_num 8 ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(8) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 9 ++#define TIMER1_OVF_vect _VECTOR(9) ++#define SIG_OVERFLOW1 _VECTOR(9) ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect_num 10 ++#define TIMER0_COMP_vect _VECTOR(10) ++#define SIG_OUTPUT_COMPARE0 _VECTOR(10) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 11 ++#define TIMER0_OVF_vect _VECTOR(11) ++#define SIG_OVERFLOW0 _VECTOR(11) ++ ++/* Serial Transfer Complete */ ++#define SPI_STC_vect_num 12 ++#define SPI_STC_vect _VECTOR(12) ++#define SIG_SPI _VECTOR(12) ++ ++/* USART, Rx Complete */ ++#define USART_RXC_vect_num 13 ++#define USART_RXC_vect _VECTOR(13) ++#define SIG_USART_RECV _VECTOR(13) ++#define SIG_UART_RECV _VECTOR(13) ++ ++/* USART Data Register Empty */ ++#define USART_UDRE_vect_num 14 ++#define USART_UDRE_vect _VECTOR(14) ++#define SIG_USART_DATA _VECTOR(14) ++#define SIG_UART_DATA _VECTOR(14) ++ ++/* USART, Tx Complete */ ++#define USART_TXC_vect_num 15 ++#define USART_TXC_vect _VECTOR(15) ++#define SIG_USART_TRANS _VECTOR(15) ++#define SIG_UART_TRANS _VECTOR(15) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 16 ++#define ADC_vect _VECTOR(16) ++#define SIG_ADC _VECTOR(16) ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect_num 17 ++#define EE_RDY_vect _VECTOR(17) ++#define SIG_EEPROM_READY _VECTOR(17) ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect_num 18 ++#define ANA_COMP_vect _VECTOR(18) ++#define SIG_COMPARATOR _VECTOR(18) ++ ++/* 2-wire Serial Interface */ ++#define TWI_vect_num 19 ++#define TWI_vect _VECTOR(19) ++#define SIG_2WIRE_SERIAL _VECTOR(19) ++ ++/* Store Program Memory Ready */ ++#define SPM_RDY_vect_num 20 ++#define SPM_RDY_vect _VECTOR(20) ++#define SIG_SPM_READY _VECTOR(20) ++ ++#define _VECTORS_SIZE 84 ++ ++/* Bit numbers */ ++ ++/* GICR */ ++#define INT1 7 ++#define INT0 6 ++#define INT2 5 ++#define IVSEL 1 ++#define IVCE 0 ++ ++/* GIFR */ ++#define INTF1 7 ++#define INTF0 6 ++#define INTF2 5 ++ ++/* TIMSK */ ++#define OCIE2 7 ++#define TOIE2 6 ++#define TICIE1 5 ++#define OCIE1A 4 ++#define OCIE1B 3 ++#define TOIE1 2 ++#define OCIE0 1 ++#define TOIE0 0 ++ ++/* TIFR */ ++#define OCF2 7 ++#define TOV2 6 ++#define ICF1 5 ++#define OCF1A 4 ++#define OCF1B 3 ++#define TOV1 2 ++#define OCF0 1 ++#define TOV0 0 ++ ++/* SPMCR */ ++#define SPMIE 7 ++#define RWWSB 6 ++/* bit 5 reserved */ ++#define RWWSRE 4 ++#define BLBSET 3 ++#define PGWRT 2 ++#define PGERS 1 ++#define SPMEN 0 ++ ++/* TWCR */ ++#define TWINT 7 ++#define TWEA 6 ++#define TWSTA 5 ++#define TWSTO 4 ++#define TWWC 3 ++#define TWEN 2 ++/* bit 1 reserved */ ++#define TWIE 0 ++ ++/* TWAR */ ++#define TWA6 7 ++#define TWA5 6 ++#define TWA4 5 ++#define TWA3 4 ++#define TWA2 3 ++#define TWA1 2 ++#define TWA0 1 ++#define TWGCE 0 ++ ++/* TWSR */ ++#define TWS7 7 ++#define TWS6 6 ++#define TWS5 5 ++#define TWS4 4 ++#define TWS3 3 ++/* bit 2 reserved */ ++#define TWPS1 1 ++#define TWPS0 0 ++ ++/* MCUCR */ ++#define SE 7 ++#define SM2 6 ++#define SM1 5 ++#define SM0 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* MCUCSR */ ++#define JTD 7 ++#define ISC2 6 ++/* bit 5 reserved */ ++#define JTRF 4 ++#define WDRF 3 ++#define BORF 2 ++#define EXTRF 1 ++#define PORF 0 ++ ++/* SFIOR */ ++#define ADTS2 7 ++#define ADTS1 6 ++#define ADTS0 5 ++/* bit 4 reserved */ ++#define ACME 3 ++#define PUD 2 ++#define PSR2 1 ++#define PSR10 0 ++ ++/* TCCR0 */ ++#define FOC0 7 ++#define WGM00 6 ++#define COM01 5 ++#define COM00 4 ++#define WGM01 3 ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* TCCR2 */ ++#define FOC2 7 ++#define WGM20 6 ++#define COM21 5 ++#define COM20 4 ++#define WGM21 3 ++#define CS22 2 ++#define CS21 1 ++#define CS20 0 ++ ++/* ASSR */ ++/* bits 7-4 reserved */ ++#define AS2 3 ++#define TCN2UB 2 ++#define OCR2UB 1 ++#define TCR2UB 0 ++ ++/* TCCR1A */ ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define FOC1A 3 ++#define FOC1B 2 ++#define WGM11 1 ++#define WGM10 0 ++ ++/* TCCR1B */ ++#define ICNC1 7 ++#define ICES1 6 ++/* bit 5 reserved */ ++#define WGM13 4 ++#define WGM12 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* WDTCR */ ++/* bits 7-5 reserved */ ++#define WDTOE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* PA7-PA0 = ADC7-ADC0 */ ++/* PORTA */ ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++/* DDRA */ ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++/* PINA */ ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++/* ++ PB7 = SCK ++ PB6 = MISO ++ PB5 = MOSI ++ PB4 = SS# ++ PB3 = OC0/AIN1 ++ PB2 = INT2/AIN0 ++ PB1 = T1 ++ PB0 = XCK/T0 ++ */ ++ ++/* PORTB */ ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* DDRB */ ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* PINB */ ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* ++ PC7 = TOSC2 ++ PC6 = TOSC1 ++ PC1 = SDA ++ PC0 = SCL ++ */ ++/* PORTC */ ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++/* DDRC */ ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++/* PINC */ ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++/* ++ PD7 = OC2 ++ PD6 = ICP ++ PD5 = OC1A ++ PD4 = OC1B ++ PD3 = INT1 ++ PD2 = INT0 ++ PD1 = TXD ++ PD0 = RXD ++ */ ++ ++/* PORTD */ ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* DDRD */ ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++/* PIND */ ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++/* SPSR */ ++#define SPIF 7 ++#define WCOL 6 ++/* bits 5-1 reserved */ ++#define SPI2X 0 ++ ++/* SPCR */ ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++/* UCSRA */ ++#define RXC 7 ++#define TXC 6 ++#define UDRE 5 ++#define FE 4 ++#define DOR 3 ++#define PE 2 ++#define U2X 1 ++#define MPCM 0 ++ ++/* UCSRB */ ++#define RXCIE 7 ++#define TXCIE 6 ++#define UDRIE 5 ++#define RXEN 4 ++#define TXEN 3 ++#define UCSZ2 2 ++#define RXB8 1 ++#define TXB8 0 ++ ++/* UCSRC */ ++#define URSEL 7 ++#define UMSEL 6 ++#define UPM1 5 ++#define UPM0 4 ++#define USBS 3 ++#define UCSZ1 2 ++#define UCSZ0 1 ++#define UCPOL 0 ++ ++/* ACSR */ ++#define ACD 7 ++#define ACBG 6 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++/* ADCSRA */ ++#define ADEN 7 ++#define ADSC 6 ++#define ADATE 5 ++#define ADIF 4 ++#define ADIE 3 ++#define ADPS2 2 ++#define ADPS1 1 ++#define ADPS0 0 ++ ++/* ADMUX */ ++#define REFS1 7 ++#define REFS0 6 ++#define ADLAR 5 ++#define MUX4 4 ++#define MUX3 3 ++#define MUX2 2 ++#define MUX1 1 ++#define MUX0 0 ++ ++/* EEPROM Control Register */ ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++/* Constants */ ++#define SPM_PAGESIZE 128 ++#define RAMSTART (0x60) ++#define RAMEND 0x85F ++#define XRAMEND RAMEND ++#define E2END 0x3FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x7FFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 2 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_BODEN (unsigned char)~_BV(6) ++#define FUSE_BODLEVEL (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_CKOPT (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x02 ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_INTERRUPT1 ++#pragma GCC poison SIG_INTERRUPT2 ++#pragma GCC poison SIG_OUTPUT_COMPARE2 ++#pragma GCC poison SIG_OVERFLOW2 ++#pragma GCC poison SIG_INPUT_CAPTURE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OUTPUT_COMPARE0 ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_SPI ++#pragma GCC poison SIG_USART_RECV ++#pragma GCC poison SIG_UART_RECV ++#pragma GCC poison SIG_USART_DATA ++#pragma GCC poison SIG_UART_DATA ++#pragma GCC poison SIG_USART_TRANS ++#pragma GCC poison SIG_UART_TRANS ++#pragma GCC poison SIG_ADC ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_2WIRE_SERIAL ++#pragma GCC poison SIG_SPM_READY ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++#endif /* _AVR_IOM32_H_ */ +diff --git a/include/avr/iom323.h b/include/avr/iom323.h +index 6e6eebf..da8dc2f 100644 +--- a/include/avr/iom323.h ++++ b/include/avr/iom323.h +@@ -1,737 +1,738 @@ +-/* Copyright (c) 2002, Marek Michalkiewicz +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom323.h 2234 2011-03-16 04:32:21Z arcanum $ */ +- +-/* avr/iom323.h - definitions for ATmega323 */ +- +-#ifndef _AVR_IOM323_H_ +-#define _AVR_IOM323_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom323.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ +-#define TWBR _SFR_IO8(0x00) +-#define TWSR _SFR_IO8(0x01) +-#define TWAR _SFR_IO8(0x02) +-#define TWDR _SFR_IO8(0x03) +- +-/* ADC */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x04) +-#endif +-#define ADCW _SFR_IO16(0x04) +-#define ADCL _SFR_IO8(0x04) +-#define ADCH _SFR_IO8(0x05) +-#define ADCSR _SFR_IO8(0x06) +-#define ADMUX _SFR_IO8(0x07) +- +-/* analog comparator */ +-#define ACSR _SFR_IO8(0x08) +- +-/* UART */ +-#define UBRR _SFR_IO8(0x09) +-#define UBRRL UBRR +-#define UCSRB _SFR_IO8(0x0A) +-#define UCSRA _SFR_IO8(0x0B) +-#define UDR _SFR_IO8(0x0C) +- +-/* SPI */ +-#define SPCR _SFR_IO8(0x0D) +-#define SPSR _SFR_IO8(0x0E) +-#define SPDR _SFR_IO8(0x0F) +- +-/* Port D */ +-#define PIND _SFR_IO8(0x10) +-#define DDRD _SFR_IO8(0x11) +-#define PORTD _SFR_IO8(0x12) +- +-/* Port C */ +-#define PINC _SFR_IO8(0x13) +-#define DDRC _SFR_IO8(0x14) +-#define PORTC _SFR_IO8(0x15) +- +-/* Port B */ +-#define PINB _SFR_IO8(0x16) +-#define DDRB _SFR_IO8(0x17) +-#define PORTB _SFR_IO8(0x18) +- +-/* Port A */ +-#define PINA _SFR_IO8(0x19) +-#define DDRA _SFR_IO8(0x1A) +-#define PORTA _SFR_IO8(0x1B) +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO16(0x1E) +-#define EEARL _SFR_IO8(0x1E) +-#define EEARH _SFR_IO8(0x1F) +- +-#define UBRRH _SFR_IO8(0x20) +-#define UCSRC UBRRH +- +-#define WDTCR _SFR_IO8(0x21) +- +-#define ASSR _SFR_IO8(0x22) +- +-/* Timer 2 */ +-#define OCR2 _SFR_IO8(0x23) +-#define TCNT2 _SFR_IO8(0x24) +-#define TCCR2 _SFR_IO8(0x25) +- +-/* Timer 1 */ +-#define ICR1 _SFR_IO16(0x26) +-#define ICR1L _SFR_IO8(0x26) +-#define ICR1H _SFR_IO8(0x27) +-#define OCR1B _SFR_IO16(0x28) +-#define OCR1BL _SFR_IO8(0x28) +-#define OCR1BH _SFR_IO8(0x29) +-#define OCR1A _SFR_IO16(0x2A) +-#define OCR1AL _SFR_IO8(0x2A) +-#define OCR1AH _SFR_IO8(0x2B) +-#define TCNT1 _SFR_IO16(0x2C) +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1H _SFR_IO8(0x2D) +-#define TCCR1B _SFR_IO8(0x2E) +-#define TCCR1A _SFR_IO8(0x2F) +- +-#define SFIOR _SFR_IO8(0x30) +- +-#define OSCCAL _SFR_IO8(0x31) +- +-/* Timer 0 */ +-#define TCNT0 _SFR_IO8(0x32) +-#define TCCR0 _SFR_IO8(0x33) +- +-#define MCUSR _SFR_IO8(0x34) +-#define MCUCSR MCUSR +-#define MCUCR _SFR_IO8(0x35) +- +-#define TWCR _SFR_IO8(0x36) +- +-#define SPMCR _SFR_IO8(0x37) +- +-#define TIFR _SFR_IO8(0x38) +-#define TIMSK _SFR_IO8(0x39) +- +-#define GIFR _SFR_IO8(0x3A) +-#define GIMSK _SFR_IO8(0x3B) +-#define GICR GIMSK +- +-#define OCR0 _SFR_IO8(0x3C) +- +-/* 0x3D..0x3E SP */ +- +-/* 0x3F SREG */ +- +-/* Interrupt vectors */ +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt Request 1 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +-#define SIG_INTERRUPT1 _VECTOR(2) +- +-/* External Interrupt Request 2 */ +-#define INT2_vect_num 3 +-#define INT2_vect _VECTOR(3) +-#define SIG_INTERRUPT2 _VECTOR(3) +- +-/* Timer/Counter2 Compare Match */ +-#define TIMER2_COMP_vect_num 4 +-#define TIMER2_COMP_vect _VECTOR(4) +-#define SIG_OUTPUT_COMPARE2 _VECTOR(4) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 5 +-#define TIMER2_OVF_vect _VECTOR(5) +-#define SIG_OVERFLOW2 _VECTOR(5) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 6 +-#define TIMER1_CAPT_vect _VECTOR(6) +-#define SIG_INPUT_CAPTURE1 _VECTOR(6) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 7 +-#define TIMER1_COMPA_vect _VECTOR(7) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(7) +- +-/* Timer/Counter1 Compare Match B */ +-#define TIMER1_COMPB_vect_num 8 +-#define TIMER1_COMPB_vect _VECTOR(8) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(8) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 9 +-#define TIMER1_OVF_vect _VECTOR(9) +-#define SIG_OVERFLOW1 _VECTOR(9) +- +-/* Timer/Counter0 Compare Match */ +-#define TIMER0_COMP_vect_num 10 +-#define TIMER0_COMP_vect _VECTOR(10) +-#define SIG_OUTPUT_COMPARE0 _VECTOR(10) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 11 +-#define TIMER0_OVF_vect _VECTOR(11) +-#define SIG_OVERFLOW0 _VECTOR(11) +- +-/* Serial Transfer Complete */ +-#define SPI_STC_vect_num 12 +-#define SPI_STC_vect _VECTOR(12) +-#define SIG_SPI _VECTOR(12) +- +-/* USART, Rx Complete */ +-#define USART_RXC_vect_num 13 +-#define USART_RXC_vect _VECTOR(13) +-#define SIG_UART_RECV _VECTOR(13) +- +-/* USART Data Register Empty */ +-#define USART_UDRE_vect_num 14 +-#define USART_UDRE_vect _VECTOR(14) +-#define SIG_UART_DATA _VECTOR(14) +- +-/* USART, Tx Complete */ +-#define USART_TXC_vect_num 15 +-#define USART_TXC_vect _VECTOR(15) +-#define SIG_UART_TRANS _VECTOR(15) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 16 +-#define ADC_vect _VECTOR(16) +-#define SIG_ADC _VECTOR(16) +- +-/* EEPROM Ready */ +-#define EE_RDY_vect_num 17 +-#define EE_RDY_vect _VECTOR(17) +-#define SIG_EEPROM_READY _VECTOR(17) +- +-/* Analog Comparator */ +-#define ANA_COMP_vect_num 18 +-#define ANA_COMP_vect _VECTOR(18) +-#define SIG_COMPARATOR _VECTOR(18) +- +-/* 2-wire Serial Interface */ +-#define TWI_vect_num 19 +-#define TWI_vect _VECTOR(19) +-#define SIG_2WIRE_SERIAL _VECTOR(19) +- +-/* Store Program Memory Ready */ +-#define SPM_RDY_vect_num 20 +-#define SPM_RDY_vect _VECTOR(20) +- +-#define _VECTORS_SIZE 80 +- +- +-/* Bit numbers */ +- +-/* GIMSK */ +-#define INT1 7 +-#define INT0 6 +-#define INT2 5 +-#define IVSEL 1 +-#define IVCE 0 +- +-/* GIFR */ +-#define INTF1 7 +-#define INTF0 6 +-#define INTF2 5 +- +-/* TIMSK */ +-#define OCIE2 7 +-#define TOIE2 6 +-#define TICIE1 5 +-#define OCIE1A 4 +-#define OCIE1B 3 +-#define TOIE1 2 +-#define OCIE0 1 +-#define TOIE0 0 +- +-/* TIFR */ +-#define OCF2 7 +-#define TOV2 6 +-#define ICF1 5 +-#define OCF1A 4 +-#define OCF1B 3 +-#define TOV1 2 +-#define OCF0 1 +-#define TOV0 0 +- +-/* SPMCR */ +-#define SPMIE 7 +-#define ASB 6 +-/* bit 5 reserved */ +-#define ASRE 4 +-#define BLBSET 3 +-#define PGWRT 2 +-#define PGERS 1 +-#define SPMEN 0 +- +-/* TWCR */ +-#define TWINT 7 +-#define TWEA 6 +-#define TWSTA 5 +-#define TWSTO 4 +-#define TWWC 3 +-#define TWEN 2 +-#define TWI_TST 1 +-#define TWIE 0 +- +-/* TWAR */ +-#define TWGCE 0 +- +-/* TWSR */ +-#define TWS7 7 +-#define TWS6 6 +-#define TWS5 5 +-#define TWS4 4 +-#define TWS3 3 +-/* bits 2-0 reserved */ +- +-/* MCUCR */ +-/* bit 7 reserved (SM2?) */ +-#define SE 7 +-#define SM2 6 +-#define SM1 5 +-#define SM0 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-/* MCUCSR */ +-#define JTD 7 +-#define ISC2 6 +-#define EIH 5 +-#define JTRF 4 +-#define WDRF 3 +-#define BORF 2 +-#define EXTRF 1 +-#define PORF 0 +- +-/* SFIOR */ +-#define RPDD 7 +-#define RPDC 6 +-#define RPDB 5 +-#define RPDA 4 +-#define ACME 3 +-#define PUD 2 +-#define PSR2 1 +-#define PSR10 0 +- +-/* TCCR0 */ +-#define FOC0 7 +-#define PWM0 6 +-#define COM01 5 +-#define COM00 4 +-#define CTC0 3 +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* TCCR2 */ +-#define FOC2 7 +-#define PWM2 6 +-#define COM21 5 +-#define COM20 4 +-#define CTC2 3 +-#define CS22 2 +-#define CS21 1 +-#define CS20 0 +- +-/* ASSR */ +-/* bits 7-4 reserved */ +-#define AS2 3 +-#define TCN2UB 2 +-#define OCR2UB 1 +-#define TCR2UB 0 +- +-/* TCCR1A */ +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define FOC1A 3 +-#define FOC1B 2 +-#define PWM11 1 +-#define PWM10 0 +- +-/* TCCR1B */ +-#define ICNC1 7 +-#define ICES1 6 +-/* bit 5 reserved */ +-#define CTC11 4 +-#define CTC10 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* WDTCR */ +-/* bits 7-5 reserved */ +-#define WDTOE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* PA7-PA0 = ADC7-ADC0 */ +-/* PORTA */ +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-/* DDRA */ +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-/* PINA */ +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-/* +- PB7 = SCK +- PB6 = MISO +- PB5 = MOSI +- PB4 = SS# +- PB3 = AIN1 +- PB2 = AIN0 +- PB1 = T1 +- PB0 = T0 +- */ +- +-/* PORTB */ +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* DDRB */ +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* PINB */ +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* +- PC7 = TOSC2 +- PC6 = TOSC1 +- PC1 = SDA +- PC0 = SCL +- */ +-/* PORTC */ +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-/* DDRC */ +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-/* PINC */ +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-/* +- PD7 = OC2 +- PD6 = ICP +- PD5 = OC1A +- PD4 = OC1B +- PD3 = INT1 +- PD2 = INT0 +- PD1 = TXD +- PD0 = RXD +- */ +- +-/* PORTD */ +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* DDRD */ +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-/* PIND */ +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-/* +- PE2 = ALE +- PE1 = OC1B +- PE0 = ICP / INT2 +- */ +- +-/* SPSR */ +-#define SPIF 7 +-#define WCOL 6 +-#define SPI2X 0 +- +-/* SPCR */ +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +-/* UCSRA */ +-#define RXC 7 +-#define TXC 6 +-#define UDRE 5 +-#define FE 4 +-#define DOR 3 +-#define PE 2 +-#define U2X 1 +-#define MPCM 0 +- +-/* UCSRB */ +-#define RXCIE 7 +-#define TXCIE 6 +-#define UDRIE 5 +-#define RXEN 4 +-#define TXEN 3 +-#define UCSZ2 2 +-#define CHR9 2 +-#define RXB8 1 +-#define TXB8 0 +- +-/* UCSRC */ +-#define URSEL 7 +-#define UMSEL 6 +-#define UPM1 5 +-#define UPM0 4 +-#define USBS 3 +-#define UCSZ1 2 +-#define UCSZ0 1 +-#define UCPOL 0 +- +-/* ACSR */ +-#define ACD 7 +-#define AINBG 6 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +- +-/* ADCSR */ +-#define ADEN 7 +-#define ADSC 6 +-#define ADFR 5 +-#define ADIF 4 +-#define ADIE 3 +-#define ADPS2 2 +-#define ADPS1 1 +-#define ADPS0 0 +- +-/* ADMUX */ +-#define REFS1 7 +-#define REFS0 6 +-#define ADLAR 5 +-#define MUX4 4 +-#define MUX3 3 +-#define MUX2 2 +-#define MUX1 1 +-#define MUX0 0 +- +-/* EEPROM Control Register */ +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-/* Constants */ +-#define SPM_PAGESIZE 128 +-#define RAMEND 0x85F +-#define XRAMEND RAMEND +-#define E2END 0x3FF +-#define E2PAGESIZE 0 +-#define FLASHEND 0x7FFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 2 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_BODEN (unsigned char)~_BV(6) +-#define FUSE_BODLEVEL (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_JTAGEN) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x95 +-#define SIGNATURE_2 0x01 +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_INTERRUPT1 +-#pragma GCC poison SIG_INTERRUPT2 +-#pragma GCC poison SIG_OUTPUT_COMPARE2 +-#pragma GCC poison SIG_OVERFLOW2 +-#pragma GCC poison SIG_INPUT_CAPTURE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OUTPUT_COMPARE0 +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_SPI +-#pragma GCC poison SIG_UART_RECV +-#pragma GCC poison SIG_UART_DATA +-#pragma GCC poison SIG_UART_TRANS +-#pragma GCC poison SIG_ADC +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_2WIRE_SERIAL +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +- +-#endif /* _AVR_IOM323_H_ */ ++/* Copyright (c) 2002, Marek Michalkiewicz ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom323.h 2234 2011-03-16 04:32:21Z arcanum $ */ ++ ++/* avr/iom323.h - definitions for ATmega323 */ ++ ++#ifndef _AVR_IOM323_H_ ++#define _AVR_IOM323_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom323.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ ++#define TWBR _SFR_IO8(0x00) ++#define TWSR _SFR_IO8(0x01) ++#define TWAR _SFR_IO8(0x02) ++#define TWDR _SFR_IO8(0x03) ++ ++/* ADC */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCW _SFR_IO16(0x04) ++#define ADCL _SFR_IO8(0x04) ++#define ADCH _SFR_IO8(0x05) ++#define ADCSR _SFR_IO8(0x06) ++#define ADMUX _SFR_IO8(0x07) ++ ++/* analog comparator */ ++#define ACSR _SFR_IO8(0x08) ++ ++/* UART */ ++#define UBRR _SFR_IO8(0x09) ++#define UBRRL UBRR ++#define UCSRB _SFR_IO8(0x0A) ++#define UCSRA _SFR_IO8(0x0B) ++#define UDR _SFR_IO8(0x0C) ++ ++/* SPI */ ++#define SPCR _SFR_IO8(0x0D) ++#define SPSR _SFR_IO8(0x0E) ++#define SPDR _SFR_IO8(0x0F) ++ ++/* Port D */ ++#define PIND _SFR_IO8(0x10) ++#define DDRD _SFR_IO8(0x11) ++#define PORTD _SFR_IO8(0x12) ++ ++/* Port C */ ++#define PINC _SFR_IO8(0x13) ++#define DDRC _SFR_IO8(0x14) ++#define PORTC _SFR_IO8(0x15) ++ ++/* Port B */ ++#define PINB _SFR_IO8(0x16) ++#define DDRB _SFR_IO8(0x17) ++#define PORTB _SFR_IO8(0x18) ++ ++/* Port A */ ++#define PINA _SFR_IO8(0x19) ++#define DDRA _SFR_IO8(0x1A) ++#define PORTA _SFR_IO8(0x1B) ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO16(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++#define EEARH _SFR_IO8(0x1F) ++ ++#define UBRRH _SFR_IO8(0x20) ++#define UCSRC UBRRH ++ ++#define WDTCR _SFR_IO8(0x21) ++ ++#define ASSR _SFR_IO8(0x22) ++ ++/* Timer 2 */ ++#define OCR2 _SFR_IO8(0x23) ++#define TCNT2 _SFR_IO8(0x24) ++#define TCCR2 _SFR_IO8(0x25) ++ ++/* Timer 1 */ ++#define ICR1 _SFR_IO16(0x26) ++#define ICR1L _SFR_IO8(0x26) ++#define ICR1H _SFR_IO8(0x27) ++#define OCR1B _SFR_IO16(0x28) ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BH _SFR_IO8(0x29) ++#define OCR1A _SFR_IO16(0x2A) ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++#define TCNT1 _SFR_IO16(0x2C) ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++#define TCCR1B _SFR_IO8(0x2E) ++#define TCCR1A _SFR_IO8(0x2F) ++ ++#define SFIOR _SFR_IO8(0x30) ++ ++#define OSCCAL _SFR_IO8(0x31) ++ ++/* Timer 0 */ ++#define TCNT0 _SFR_IO8(0x32) ++#define TCCR0 _SFR_IO8(0x33) ++ ++#define MCUSR _SFR_IO8(0x34) ++#define MCUCSR MCUSR ++#define MCUCR _SFR_IO8(0x35) ++ ++#define TWCR _SFR_IO8(0x36) ++ ++#define SPMCR _SFR_IO8(0x37) ++ ++#define TIFR _SFR_IO8(0x38) ++#define TIMSK _SFR_IO8(0x39) ++ ++#define GIFR _SFR_IO8(0x3A) ++#define GIMSK _SFR_IO8(0x3B) ++#define GICR GIMSK ++ ++#define OCR0 _SFR_IO8(0x3C) ++ ++/* 0x3D..0x3E SP */ ++ ++/* 0x3F SREG */ ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++#define SIG_INTERRUPT1 _VECTOR(2) ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect_num 3 ++#define INT2_vect _VECTOR(3) ++#define SIG_INTERRUPT2 _VECTOR(3) ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect_num 4 ++#define TIMER2_COMP_vect _VECTOR(4) ++#define SIG_OUTPUT_COMPARE2 _VECTOR(4) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 5 ++#define TIMER2_OVF_vect _VECTOR(5) ++#define SIG_OVERFLOW2 _VECTOR(5) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 6 ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define SIG_INPUT_CAPTURE1 _VECTOR(6) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 7 ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(7) ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect_num 8 ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(8) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 9 ++#define TIMER1_OVF_vect _VECTOR(9) ++#define SIG_OVERFLOW1 _VECTOR(9) ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect_num 10 ++#define TIMER0_COMP_vect _VECTOR(10) ++#define SIG_OUTPUT_COMPARE0 _VECTOR(10) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 11 ++#define TIMER0_OVF_vect _VECTOR(11) ++#define SIG_OVERFLOW0 _VECTOR(11) ++ ++/* Serial Transfer Complete */ ++#define SPI_STC_vect_num 12 ++#define SPI_STC_vect _VECTOR(12) ++#define SIG_SPI _VECTOR(12) ++ ++/* USART, Rx Complete */ ++#define USART_RXC_vect_num 13 ++#define USART_RXC_vect _VECTOR(13) ++#define SIG_UART_RECV _VECTOR(13) ++ ++/* USART Data Register Empty */ ++#define USART_UDRE_vect_num 14 ++#define USART_UDRE_vect _VECTOR(14) ++#define SIG_UART_DATA _VECTOR(14) ++ ++/* USART, Tx Complete */ ++#define USART_TXC_vect_num 15 ++#define USART_TXC_vect _VECTOR(15) ++#define SIG_UART_TRANS _VECTOR(15) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 16 ++#define ADC_vect _VECTOR(16) ++#define SIG_ADC _VECTOR(16) ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect_num 17 ++#define EE_RDY_vect _VECTOR(17) ++#define SIG_EEPROM_READY _VECTOR(17) ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect_num 18 ++#define ANA_COMP_vect _VECTOR(18) ++#define SIG_COMPARATOR _VECTOR(18) ++ ++/* 2-wire Serial Interface */ ++#define TWI_vect_num 19 ++#define TWI_vect _VECTOR(19) ++#define SIG_2WIRE_SERIAL _VECTOR(19) ++ ++/* Store Program Memory Ready */ ++#define SPM_RDY_vect_num 20 ++#define SPM_RDY_vect _VECTOR(20) ++ ++#define _VECTORS_SIZE 80 ++ ++ ++/* Bit numbers */ ++ ++/* GIMSK */ ++#define INT1 7 ++#define INT0 6 ++#define INT2 5 ++#define IVSEL 1 ++#define IVCE 0 ++ ++/* GIFR */ ++#define INTF1 7 ++#define INTF0 6 ++#define INTF2 5 ++ ++/* TIMSK */ ++#define OCIE2 7 ++#define TOIE2 6 ++#define TICIE1 5 ++#define OCIE1A 4 ++#define OCIE1B 3 ++#define TOIE1 2 ++#define OCIE0 1 ++#define TOIE0 0 ++ ++/* TIFR */ ++#define OCF2 7 ++#define TOV2 6 ++#define ICF1 5 ++#define OCF1A 4 ++#define OCF1B 3 ++#define TOV1 2 ++#define OCF0 1 ++#define TOV0 0 ++ ++/* SPMCR */ ++#define SPMIE 7 ++#define ASB 6 ++/* bit 5 reserved */ ++#define ASRE 4 ++#define BLBSET 3 ++#define PGWRT 2 ++#define PGERS 1 ++#define SPMEN 0 ++ ++/* TWCR */ ++#define TWINT 7 ++#define TWEA 6 ++#define TWSTA 5 ++#define TWSTO 4 ++#define TWWC 3 ++#define TWEN 2 ++#define TWI_TST 1 ++#define TWIE 0 ++ ++/* TWAR */ ++#define TWGCE 0 ++ ++/* TWSR */ ++#define TWS7 7 ++#define TWS6 6 ++#define TWS5 5 ++#define TWS4 4 ++#define TWS3 3 ++/* bits 2-0 reserved */ ++ ++/* MCUCR */ ++/* bit 7 reserved (SM2?) */ ++#define SE 7 ++#define SM2 6 ++#define SM1 5 ++#define SM0 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* MCUCSR */ ++#define JTD 7 ++#define ISC2 6 ++#define EIH 5 ++#define JTRF 4 ++#define WDRF 3 ++#define BORF 2 ++#define EXTRF 1 ++#define PORF 0 ++ ++/* SFIOR */ ++#define RPDD 7 ++#define RPDC 6 ++#define RPDB 5 ++#define RPDA 4 ++#define ACME 3 ++#define PUD 2 ++#define PSR2 1 ++#define PSR10 0 ++ ++/* TCCR0 */ ++#define FOC0 7 ++#define PWM0 6 ++#define COM01 5 ++#define COM00 4 ++#define CTC0 3 ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* TCCR2 */ ++#define FOC2 7 ++#define PWM2 6 ++#define COM21 5 ++#define COM20 4 ++#define CTC2 3 ++#define CS22 2 ++#define CS21 1 ++#define CS20 0 ++ ++/* ASSR */ ++/* bits 7-4 reserved */ ++#define AS2 3 ++#define TCN2UB 2 ++#define OCR2UB 1 ++#define TCR2UB 0 ++ ++/* TCCR1A */ ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define FOC1A 3 ++#define FOC1B 2 ++#define PWM11 1 ++#define PWM10 0 ++ ++/* TCCR1B */ ++#define ICNC1 7 ++#define ICES1 6 ++/* bit 5 reserved */ ++#define CTC11 4 ++#define CTC10 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* WDTCR */ ++/* bits 7-5 reserved */ ++#define WDTOE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* PA7-PA0 = ADC7-ADC0 */ ++/* PORTA */ ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++/* DDRA */ ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++/* PINA */ ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++/* ++ PB7 = SCK ++ PB6 = MISO ++ PB5 = MOSI ++ PB4 = SS# ++ PB3 = AIN1 ++ PB2 = AIN0 ++ PB1 = T1 ++ PB0 = T0 ++ */ ++ ++/* PORTB */ ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* DDRB */ ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* PINB */ ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* ++ PC7 = TOSC2 ++ PC6 = TOSC1 ++ PC1 = SDA ++ PC0 = SCL ++ */ ++/* PORTC */ ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++/* DDRC */ ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++/* PINC */ ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++/* ++ PD7 = OC2 ++ PD6 = ICP ++ PD5 = OC1A ++ PD4 = OC1B ++ PD3 = INT1 ++ PD2 = INT0 ++ PD1 = TXD ++ PD0 = RXD ++ */ ++ ++/* PORTD */ ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* DDRD */ ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++/* PIND */ ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++/* ++ PE2 = ALE ++ PE1 = OC1B ++ PE0 = ICP / INT2 ++ */ ++ ++/* SPSR */ ++#define SPIF 7 ++#define WCOL 6 ++#define SPI2X 0 ++ ++/* SPCR */ ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++/* UCSRA */ ++#define RXC 7 ++#define TXC 6 ++#define UDRE 5 ++#define FE 4 ++#define DOR 3 ++#define PE 2 ++#define U2X 1 ++#define MPCM 0 ++ ++/* UCSRB */ ++#define RXCIE 7 ++#define TXCIE 6 ++#define UDRIE 5 ++#define RXEN 4 ++#define TXEN 3 ++#define UCSZ2 2 ++#define CHR9 2 ++#define RXB8 1 ++#define TXB8 0 ++ ++/* UCSRC */ ++#define URSEL 7 ++#define UMSEL 6 ++#define UPM1 5 ++#define UPM0 4 ++#define USBS 3 ++#define UCSZ1 2 ++#define UCSZ0 1 ++#define UCPOL 0 ++ ++/* ACSR */ ++#define ACD 7 ++#define AINBG 6 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++/* ADCSR */ ++#define ADEN 7 ++#define ADSC 6 ++#define ADFR 5 ++#define ADIF 4 ++#define ADIE 3 ++#define ADPS2 2 ++#define ADPS1 1 ++#define ADPS0 0 ++ ++/* ADMUX */ ++#define REFS1 7 ++#define REFS0 6 ++#define ADLAR 5 ++#define MUX4 4 ++#define MUX3 3 ++#define MUX2 2 ++#define MUX1 1 ++#define MUX0 0 ++ ++/* EEPROM Control Register */ ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++/* Constants */ ++#define SPM_PAGESIZE 128 ++#define RAMSTART 0x60 ++#define RAMEND 0x85F ++#define XRAMEND RAMEND ++#define E2END 0x3FF ++#define E2PAGESIZE 0 ++#define FLASHEND 0x7FFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 2 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_BODEN (unsigned char)~_BV(6) ++#define FUSE_BODLEVEL (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_JTAGEN) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x01 ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_INTERRUPT1 ++#pragma GCC poison SIG_INTERRUPT2 ++#pragma GCC poison SIG_OUTPUT_COMPARE2 ++#pragma GCC poison SIG_OVERFLOW2 ++#pragma GCC poison SIG_INPUT_CAPTURE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OUTPUT_COMPARE0 ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_SPI ++#pragma GCC poison SIG_UART_RECV ++#pragma GCC poison SIG_UART_DATA ++#pragma GCC poison SIG_UART_TRANS ++#pragma GCC poison SIG_ADC ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_2WIRE_SERIAL ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++ ++#endif /* _AVR_IOM323_H_ */ +diff --git a/include/avr/iom324.h b/include/avr/iom324.h +index 47d76cf..4f9cd70 100644 +--- a/include/avr/iom324.h ++++ b/include/avr/iom324.h +@@ -1,95 +1,95 @@ +-/* Copyright (c) 2005, 2006 Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* avr/iom324.h - definitions for ATmega324 */ +- +-/* $Id: iom324.h 2115 2010-04-05 23:19:53Z arcanum $ */ +- +-#ifndef _AVR_IOM324_H_ +-#define _AVR_IOM324_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 128 +-#define RAMSTART (0x100) +-#define RAMEND 0x08FF +-#define XRAMEND RAMEND +-#define E2END 0x3FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x7FFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature (ATmega324P) */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x95 +-#define SIGNATURE_2 0x08 +- +- +-#endif /* _AVR_IOM324_H_ */ ++/* Copyright (c) 2005, 2006 Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* avr/iom324.h - definitions for ATmega324 */ ++ ++/* $Id: iom324.h 2115 2010-04-05 23:19:53Z arcanum $ */ ++ ++#ifndef _AVR_IOM324_H_ ++#define _AVR_IOM324_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 128 ++#define RAMSTART (0x100) ++#define RAMEND 0x08FF ++#define XRAMEND RAMEND ++#define E2END 0x3FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x7FFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature (ATmega324P) */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x08 ++ ++ ++#endif /* _AVR_IOM324_H_ */ +diff --git a/include/avr/iom324a.h b/include/avr/iom324a.h +new file mode 100644 +index 0000000..a4f8ea8 +--- /dev/null ++++ b/include/avr/iom324a.h +@@ -0,0 +1,924 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATMEGA324A_H_INCLUDED ++#define _AVR_ATMEGA324A_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom324a.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDRA7 7 ++#define DDRA6 6 ++#define DDRA5 5 ++#define DDRA4 4 ++#define DDRA3 3 ++#define DDRA2 2 ++#define DDRA1 1 ++#define DDRA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDRC7 7 ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC7 7 ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++/* Reserved [0x0C..0x14] */ ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++/* Reserved [0x18..0x1A] */ ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++#define PCIF3 3 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define TSM 7 ++#define PSRASY 1 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++ ++#define OCR0A _SFR_IO8(0x27) ++ ++#define OCR0B _SFR_IO8(0x28) ++ ++/* Reserved [0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR0 _SFR_IO8(0x2C) ++#define SPR00 0 ++#define SPR10 1 ++#define CPHA0 2 ++#define CPOL0 3 ++#define MSTR0 4 ++#define DORD0 5 ++#define SPE0 6 ++#define SPIE0 7 ++ ++#define SPSR0 _SFR_IO8(0x2D) ++#define SPI2X0 0 ++#define WCOL0 6 ++#define SPIF0 7 ++ ++#define SPDR0 _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR7 7 ++#define OCDR6 6 ++#define OCDR5 5 ++#define OCDR4 4 ++#define OCDR3 3 ++#define OCDR2 2 ++#define OCDR1 1 ++#define OCDR0 0 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define JTRF 4 ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define JTD 7 ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDE 3 ++#define WDCE 4 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRUSART1 4 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++/* Reserved [0x67] */ ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++#define PCIE3 3 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++/* Reserved [0x71..0x72] */ ++ ++#define PCMSK3 _SFR_MEM8(0x73) ++#define PCINT24 0 ++#define PCINT25 1 ++#define PCINT26 2 ++#define PCINT27 3 ++#define PCINT28 4 ++#define PCINT29 5 ++#define PCINT30 6 ++#define PCINT31 7 ++ ++/* Reserved [0x74..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ACME 6 ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++#define OCR2B _SFR_MEM8(0xB4) ++ ++/* Reserved [0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++ ++/* Reserved [0xB7] */ ++ ++#define TWBR _SFR_MEM8(0xB8) ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++/* Reserved [0xBE..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0xC6) ++ ++/* Reserved [0xC7] */ ++ ++#define UCSR1A _SFR_MEM8(0xC8) ++#define MPCM1 0 ++#define U2X1 1 ++#define UPE1 2 ++#define DOR1 3 ++#define FE1 4 ++#define UDRE1 5 ++#define TXC1 6 ++#define RXC1 7 ++ ++#define UCSR1B _SFR_MEM8(0xC9) ++#define TXB81 0 ++#define RXB81 1 ++#define UCSZ12 2 ++#define TXEN1 3 ++#define RXEN1 4 ++#define UDRIE1 5 ++#define TXCIE1 6 ++#define RXCIE1 7 ++ ++#define UCSR1C _SFR_MEM8(0xCA) ++#define UCPOL1 0 ++#define UCSZ10 1 ++#define UCSZ11 2 ++#define USBS1 3 ++#define UPM10 4 ++#define UPM11 5 ++#define UMSEL10 6 ++#define UMSEL11 7 ++ ++/* Reserved [0xCB] */ ++ ++/* Combine UBRR1L and UBRR1H */ ++#define UBRR1 _SFR_MEM16(0xCC) ++ ++#define UBRR1L _SFR_MEM8(0xCC) ++#define UBRR1H _SFR_MEM8(0xCD) ++ ++#define UDR1 _SFR_MEM8(0xCE) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect _VECTOR(3) ++#define INT2_vect_num 3 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(4) ++#define PCINT0_vect_num 4 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(5) ++#define PCINT1_vect_num 5 ++ ++/* Pin Change Interrupt Request 2 */ ++#define PCINT2_vect _VECTOR(6) ++#define PCINT2_vect_num 6 ++ ++/* Pin Change Interrupt Request 3 */ ++#define PCINT3_vect _VECTOR(7) ++#define PCINT3_vect_num 7 ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect _VECTOR(8) ++#define WDT_vect_num 8 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPA_vect _VECTOR(9) ++#define TIMER2_COMPA_vect_num 9 ++ ++/* Timer/Counter2 Compare Match B */ ++#define TIMER2_COMPB_vect _VECTOR(10) ++#define TIMER2_COMPB_vect_num 10 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(11) ++#define TIMER2_OVF_vect_num 11 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(12) ++#define TIMER1_CAPT_vect_num 12 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(13) ++#define TIMER1_COMPA_vect_num 13 ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(14) ++#define TIMER1_COMPB_vect_num 14 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(15) ++#define TIMER1_OVF_vect_num 15 ++ ++/* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPA_vect _VECTOR(16) ++#define TIMER0_COMPA_vect_num 16 ++ ++/* Timer/Counter0 Compare Match B */ ++#define TIMER0_COMPB_vect _VECTOR(17) ++#define TIMER0_COMPB_vect_num 17 ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(18) ++#define TIMER0_OVF_vect_num 18 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(19) ++#define SPI_STC_vect_num 19 ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect _VECTOR(20) ++#define USART0_RX_vect_num 20 ++ ++/* USART0 Data register Empty */ ++#define USART0_UDRE_vect _VECTOR(21) ++#define USART0_UDRE_vect_num 21 ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect _VECTOR(22) ++#define USART0_TX_vect_num 22 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(23) ++#define ANALOG_COMP_vect_num 23 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(24) ++#define ADC_vect_num 24 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(25) ++#define EE_READY_vect_num 25 ++ ++/* 2-wire Serial Interface */ ++#define TWI_vect _VECTOR(26) ++#define TWI_vect_num 26 ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect _VECTOR(27) ++#define SPM_READY_vect_num 27 ++ ++/* USART1 RX complete */ ++#define USART1_RX_vect _VECTOR(28) ++#define USART1_RX_vect_num 28 ++ ++/* USART1 Data Register Empty */ ++#define USART1_UDRE_vect _VECTOR(29) ++#define USART1_UDRE_vect_num 29 ++ ++/* USART1 TX complete */ ++#define USART1_TX_vect _VECTOR(30) ++#define USART1_TX_vect_num 30 ++ ++#define _VECTORS_SIZE 124 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 128 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x7FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 2048 ++#define RAMEND 0x08FF ++#define E2START 0 ++#define E2SIZE 1024 ++#define E2PAGESIZE 4 ++#define E2END 0x03FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x15 ++ ++ ++#endif /* #ifdef _AVR_ATMEGA324A_H_INCLUDED */ ++ +diff --git a/include/avr/iom324p.h b/include/avr/iom324p.h +new file mode 100644 +index 0000000..6561f7b +--- /dev/null ++++ b/include/avr/iom324p.h +@@ -0,0 +1,926 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATMEGA324P_H_INCLUDED ++#define _AVR_ATMEGA324P_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom324p.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDRA7 7 ++#define DDRA6 6 ++#define DDRA5 5 ++#define DDRA4 4 ++#define DDRA3 3 ++#define DDRA2 2 ++#define DDRA1 1 ++#define DDRA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDRC7 7 ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC7 7 ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++/* Reserved [0x0C..0x14] */ ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++/* Reserved [0x18..0x1A] */ ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++#define PCIF3 3 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define TSM 7 ++#define PSRASY 1 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++ ++#define OCR0A _SFR_IO8(0x27) ++ ++#define OCR0B _SFR_IO8(0x28) ++ ++/* Reserved [0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR0 _SFR_IO8(0x2C) ++#define SPR00 0 ++#define SPR10 1 ++#define CPHA0 2 ++#define CPOL0 3 ++#define MSTR0 4 ++#define DORD0 5 ++#define SPE0 6 ++#define SPIE0 7 ++ ++#define SPSR0 _SFR_IO8(0x2D) ++#define SPI2X0 0 ++#define WCOL0 6 ++#define SPIF0 7 ++ ++#define SPDR0 _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR7 7 ++#define OCDR6 6 ++#define OCDR5 5 ++#define OCDR4 4 ++#define OCDR3 3 ++#define OCDR2 2 ++#define OCDR1 1 ++#define OCDR0 0 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define JTRF 4 ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define JTD 7 ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDE 3 ++#define WDCE 4 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRUSART1 4 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++/* Reserved [0x67] */ ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++#define PCIE3 3 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++/* Reserved [0x71..0x72] */ ++ ++#define PCMSK3 _SFR_MEM8(0x73) ++#define PCINT24 0 ++#define PCINT25 1 ++#define PCINT26 2 ++#define PCINT27 3 ++#define PCINT28 4 ++#define PCINT29 5 ++#define PCINT30 6 ++#define PCINT31 7 ++ ++/* Reserved [0x74..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ACME 6 ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++#define OCR2B _SFR_MEM8(0xB4) ++ ++/* Reserved [0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++ ++/* Reserved [0xB7] */ ++ ++#define TWBR _SFR_MEM8(0xB8) ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++/* Reserved [0xBE..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0xC6) ++ ++/* Reserved [0xC7] */ ++ ++#define UCSR1A _SFR_MEM8(0xC8) ++#define MPCM1 0 ++#define U2X1 1 ++#define UPE1 2 ++#define DOR1 3 ++#define FE1 4 ++#define UDRE1 5 ++#define TXC1 6 ++#define RXC1 7 ++ ++#define UCSR1B _SFR_MEM8(0xC9) ++#define TXB81 0 ++#define RXB81 1 ++#define UCSZ12 2 ++#define TXEN1 3 ++#define RXEN1 4 ++#define UDRIE1 5 ++#define TXCIE1 6 ++#define RXCIE1 7 ++ ++#define UCSR1C _SFR_MEM8(0xCA) ++#define UCPOL1 0 ++#define UCSZ10 1 ++#define UCSZ11 2 ++#define USBS1 3 ++#define UPM10 4 ++#define UPM11 5 ++#define UMSEL10 6 ++#define UMSEL11 7 ++ ++/* Reserved [0xCB] */ ++ ++/* Combine UBRR1L and UBRR1H */ ++#define UBRR1 _SFR_MEM16(0xCC) ++ ++#define UBRR1L _SFR_MEM8(0xCC) ++#define UBRR1H _SFR_MEM8(0xCD) ++ ++#define UDR1 _SFR_MEM8(0xCE) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect _VECTOR(3) ++#define INT2_vect_num 3 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(4) ++#define PCINT0_vect_num 4 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(5) ++#define PCINT1_vect_num 5 ++ ++/* Pin Change Interrupt Request 2 */ ++#define PCINT2_vect _VECTOR(6) ++#define PCINT2_vect_num 6 ++ ++/* Pin Change Interrupt Request 3 */ ++#define PCINT3_vect _VECTOR(7) ++#define PCINT3_vect_num 7 ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect _VECTOR(8) ++#define WDT_vect_num 8 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPA_vect _VECTOR(9) ++#define TIMER2_COMPA_vect_num 9 ++ ++/* Timer/Counter2 Compare Match B */ ++#define TIMER2_COMPB_vect _VECTOR(10) ++#define TIMER2_COMPB_vect_num 10 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(11) ++#define TIMER2_OVF_vect_num 11 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(12) ++#define TIMER1_CAPT_vect_num 12 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(13) ++#define TIMER1_COMPA_vect_num 13 ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(14) ++#define TIMER1_COMPB_vect_num 14 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(15) ++#define TIMER1_OVF_vect_num 15 ++ ++/* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPA_vect _VECTOR(16) ++#define TIMER0_COMPA_vect_num 16 ++ ++/* Timer/Counter0 Compare Match B */ ++#define TIMER0_COMPB_vect _VECTOR(17) ++#define TIMER0_COMPB_vect_num 17 ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(18) ++#define TIMER0_OVF_vect_num 18 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(19) ++#define SPI_STC_vect_num 19 ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect _VECTOR(20) ++#define USART0_RX_vect_num 20 ++ ++/* USART0 Data register Empty */ ++#define USART0_UDRE_vect _VECTOR(21) ++#define USART0_UDRE_vect_num 21 ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect _VECTOR(22) ++#define USART0_TX_vect_num 22 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(23) ++#define ANALOG_COMP_vect_num 23 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(24) ++#define ADC_vect_num 24 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(25) ++#define EE_READY_vect_num 25 ++ ++/* 2-wire Serial Interface */ ++#define TWI_vect _VECTOR(26) ++#define TWI_vect_num 26 ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect _VECTOR(27) ++#define SPM_READY_vect_num 27 ++ ++/* USART1 RX complete */ ++#define USART1_RX_vect _VECTOR(28) ++#define USART1_RX_vect_num 28 ++ ++/* USART1 Data Register Empty */ ++#define USART1_UDRE_vect _VECTOR(29) ++#define USART1_UDRE_vect_num 29 ++ ++/* USART1 TX complete */ ++#define USART1_TX_vect _VECTOR(30) ++#define USART1_TX_vect_num 30 ++ ++#define _VECTORS_SIZE 124 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 128 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x7FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 2048 ++#define RAMEND 0x08FF ++#define E2START 0 ++#define E2SIZE 1024 ++#define E2PAGESIZE 4 ++#define E2END 0x03FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x08 ++ ++ ++#endif /* #ifdef _AVR_ATMEGA324P_H_INCLUDED */ ++ +diff --git a/include/avr/iom324pa.h b/include/avr/iom324pa.h +index fb617db..6d771ea 100644 +--- a/include/avr/iom324pa.h ++++ b/include/avr/iom324pa.h +@@ -1,1355 +1,1355 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom324pa.h 2063 2009-11-18 22:06:28Z arcanum $ */ +- +-/* avr/iom324pa.h - definitions for ATmega324PA */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom324pa.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATmega324PA_H_ +-#define _AVR_ATmega324PA_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +-#define PINA4 4 +-#define PINA5 5 +-#define PINA6 6 +-#define PINA7 7 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +-#define DDA4 4 +-#define DDA5 5 +-#define DDA6 6 +-#define DDA7 7 +- +-#define PORTA _SFR_IO8(0x02) +-#define PORTA0 0 +-#define PORTA1 1 +-#define PORTA2 2 +-#define PORTA3 3 +-#define PORTA4 4 +-#define PORTA5 5 +-#define PORTA6 6 +-#define PORTA7 7 +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +-#define PINC7 7 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC3 3 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +-#define DDC7 7 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC3 3 +-#define PORTC4 4 +-#define PORTC5 5 +-#define PORTC6 6 +-#define PORTC7 7 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define TIFR2 _SFR_IO8(0x17) +-#define TOV2 0 +-#define OCF2A 1 +-#define OCF2B 2 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +-#define PCIF1 1 +-#define PCIF2 2 +-#define PCIF3 3 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +-#define INTF2 2 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +-#define INT2 2 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +-#define EEAR9 1 +-#define EEAR10 2 +-#define EEAR11 3 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSRSYNC 0 +-#define PSRASY 1 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define OCR0A _SFR_IO8(0x27) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define OCR0B _SFR_IO8(0x28) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR0 _SFR_IO8(0x2C) +-#define SPR00 0 +-#define SPR10 1 +-#define CPHA0 2 +-#define CPOL0 3 +-#define MSTR0 4 +-#define DORD0 5 +-#define SPE0 6 +-#define SPIE0 7 +- +-#define SPSR0 _SFR_IO8(0x2D) +-#define SPI2X0 0 +-#define WCOL0 6 +-#define SPIF0 7 +- +-#define SPDR0 _SFR_IO8(0x2E) +-#define SPDRB0 0 +-#define SPDRB1 1 +-#define SPDRB2 2 +-#define SPDRB3 3 +-#define SPDRB4 4 +-#define SPDRB5 5 +-#define SPDRB6 6 +-#define SPDRB7 7 +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define OCDR _SFR_IO8(0x31) +-#define OCDR0 0 +-#define OCDR1 1 +-#define OCDR2 2 +-#define OCDR3 3 +-#define OCDR4 4 +-#define OCDR5 5 +-#define OCDR6 6 +-#define OCDR7 7 +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +-#define JTRF 4 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define BODSE 5 +-#define BODS 6 +-#define JTD 7 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define SIGRD 5 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define PRR0 _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM1 3 +-#define PRUSART1 4 +-#define PRTIM0 5 +-#define PRTIM2 6 +-#define PRTWI 7 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +-#define PCIE1 1 +-#define PCIE2 2 +-#define PCIE3 3 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define ISC20 4 +-#define ISC21 5 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-#define PCMSK2 _SFR_MEM8(0x6D) +-#define PCINT16 0 +-#define PCINT17 1 +-#define PCINT18 2 +-#define PCINT19 3 +-#define PCINT20 4 +-#define PCINT21 5 +-#define PCINT22 6 +-#define PCINT23 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define TIMSK2 _SFR_MEM8(0x70) +-#define TOIE2 0 +-#define OCIE2A 1 +-#define OCIE2B 2 +- +-#define PCMSK3 _SFR_MEM8(0x73) +-#define PCINT24 0 +-#define PCINT25 1 +-#define PCINT26 2 +-#define PCINT27 3 +-#define PCINT28 4 +-#define PCINT29 5 +-#define PCINT30 6 +-#define PCINT31 7 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +- +-#define ADCL _SFR_MEM8(0x78) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_MEM8(0x79) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ACME 6 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define TCCR2A _SFR_MEM8(0xB0) +-#define WGM20 0 +-#define WGM21 1 +-#define COM2B0 4 +-#define COM2B1 5 +-#define COM2A0 6 +-#define COM2A1 7 +- +-#define TCCR2B _SFR_MEM8(0xB1) +-#define CS20 0 +-#define CS21 1 +-#define CS22 2 +-#define WGM22 3 +-#define FOC2B 6 +-#define FOC2A 7 +- +-#define TCNT2 _SFR_MEM8(0xB2) +-#define TCNT2_0 0 +-#define TCNT2_1 1 +-#define TCNT2_2 2 +-#define TCNT2_3 3 +-#define TCNT2_4 4 +-#define TCNT2_5 5 +-#define TCNT2_6 6 +-#define TCNT2_7 7 +- +-#define OCR2A _SFR_MEM8(0xB3) +-#define OCR2A_0 0 +-#define OCR2A_1 1 +-#define OCR2A_2 2 +-#define OCR2A_3 3 +-#define OCR2A_4 4 +-#define OCR2A_5 5 +-#define OCR2A_6 6 +-#define OCR2A_7 7 +- +-#define OCR2B _SFR_MEM8(0xB4) +-#define OCR2B_0 0 +-#define OCR2B_1 1 +-#define OCR2B_2 2 +-#define OCR2B_3 3 +-#define OCR2B_4 4 +-#define OCR2B_5 5 +-#define OCR2B_6 6 +-#define OCR2B_7 7 +- +-#define ASSR _SFR_MEM8(0xB6) +-#define TCR2BUB 0 +-#define TCR2AUB 1 +-#define OCR2BUB 2 +-#define OCR2AUB 3 +-#define TCN2UB 4 +-#define AS2 5 +-#define EXCLK 6 +- +-#define TWBR _SFR_MEM8(0xB8) +-#define TWBR0 0 +-#define TWBR1 1 +-#define TWBR2 2 +-#define TWBR3 3 +-#define TWBR4 4 +-#define TWBR5 5 +-#define TWBR6 6 +-#define TWBR7 7 +- +-#define TWSR _SFR_MEM8(0xB9) +-#define TWPS0 0 +-#define TWPS1 1 +-#define TWS3 3 +-#define TWS4 4 +-#define TWS5 5 +-#define TWS6 6 +-#define TWS7 7 +- +-#define TWAR _SFR_MEM8(0xBA) +-#define TWGCE 0 +-#define TWA0 1 +-#define TWA1 2 +-#define TWA2 3 +-#define TWA3 4 +-#define TWA4 5 +-#define TWA5 6 +-#define TWA6 7 +- +-#define TWDR _SFR_MEM8(0xBB) +-#define TWD0 0 +-#define TWD1 1 +-#define TWD2 2 +-#define TWD3 3 +-#define TWD4 4 +-#define TWD5 5 +-#define TWD6 6 +-#define TWD7 7 +- +-#define TWCR _SFR_MEM8(0xBC) +-#define TWIE 0 +-#define TWEN 2 +-#define TWWC 3 +-#define TWSTO 4 +-#define TWSTA 5 +-#define TWEA 6 +-#define TWINT 7 +- +-#define TWAMR _SFR_MEM8(0xBD) +-#define TWAM0 1 +-#define TWAM1 2 +-#define TWAM2 3 +-#define TWAM3 4 +-#define TWAM4 5 +-#define TWAM5 6 +-#define TWAM6 7 +- +-#define UCSR0A _SFR_MEM8(0xC0) +-#define MPCM0 0 +-#define U2X0 1 +-#define UPE0 2 +-#define DOR0 3 +-#define FE0 4 +-#define UDRE0 5 +-#define TXC0 6 +-#define RXC0 7 +- +-#define UCSR0B _SFR_MEM8(0xC1) +-#define TXB80 0 +-#define RXB80 1 +-#define UCSZ02 2 +-#define TXEN0 3 +-#define RXEN0 4 +-#define UDRIE0 5 +-#define TXCIE0 6 +-#define RXCIE0 7 +- +-#define UCSR0C _SFR_MEM8(0xC2) +-#define UCPOL0 0 +-#define UCSZ00 1 +-#define UCSZ01 2 +-#define USBS0 3 +-#define UPM00 4 +-#define UPM01 5 +-#define UMSEL00 6 +-#define UMSEL01 7 +- +-#define UBRR0 _SFR_MEM16(0xC4) +- +-#define UBRR0L _SFR_MEM8(0xC4) +-#define _UBRR0 0 +-#define _UBRR1 1 +-#define UBRR2 2 +-#define UBRR3 3 +-#define UBRR4 4 +-#define UBRR5 5 +-#define UBRR6 6 +-#define UBRR7 7 +- +-#define UBRR0H _SFR_MEM8(0xC5) +-#define UBRR8 0 +-#define UBRR9 1 +-#define UBRR10 2 +-#define UBRR11 3 +- +-#define UDR0 _SFR_MEM8(0xC6) +-#define UDR0_0 0 +-#define UDR0_1 1 +-#define UDR0_2 2 +-#define UDR0_3 3 +-#define UDR0_4 4 +-#define UDR0_5 5 +-#define UDR0_6 6 +-#define UDR0_7 7 +- +-#define UCSR1A _SFR_MEM8(0xC8) +-#define MPCM1 0 +-#define U2X1 1 +-#define UPE1 2 +-#define DOR1 3 +-#define FE1 4 +-#define UDRE1 5 +-#define TXC1 6 +-#define RXC1 7 +- +-#define UCSR1B _SFR_MEM8(0xC9) +-#define TXB81 0 +-#define RXB81 1 +-#define UCSZ12 2 +-#define TXEN1 3 +-#define RXEN1 4 +-#define UDRIE1 5 +-#define TXCIE1 6 +-#define RXCIE1 7 +- +-#define UCSR1C _SFR_MEM8(0xCA) +-#define UCPOL1 0 +-#define UCSZ10 1 +-#define UCSZ11 2 +-#define USBS1 3 +-#define UPM10 4 +-#define UPM11 5 +-#define UMSEL10 6 +-#define UMSEL11 7 +- +-#define UBRR1 _SFR_MEM16(0xCC) +- +-#define UBRR1L _SFR_MEM8(0xCC) +-#define UBRR_0 0 +-#define UBRR_1 1 +-#define UBRR_2 2 +-#define UBRR_3 3 +-#define UBRR_4 4 +-#define UBRR_5 5 +-#define UBRR_6 6 +-#define UBRR_7 7 +- +-#define UBRR1H _SFR_MEM8(0xCD) +-#define UBRR_8 0 +-#define UBRR_9 1 +-#define UBRR_10 2 +-#define UBRR_11 3 +- +-#define UDR1 _SFR_MEM8(0xCE) +-#define UDR1_0 0 +-#define UDR1_1 1 +-#define UDR1_2 2 +-#define UDR1_3 3 +-#define UDR1_4 4 +-#define UDR1_5 5 +-#define UDR1_6 6 +-#define UDR1_7 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ +-#define INT2_vect_num 3 +-#define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ +-#define PCINT0_vect_num 4 +-#define PCINT0_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */ +-#define PCINT1_vect_num 5 +-#define PCINT1_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */ +-#define PCINT2_vect_num 6 +-#define PCINT2_vect _VECTOR(6) /* Pin Change Interrupt Request 2 */ +-#define PCINT3_vect_num 7 +-#define PCINT3_vect _VECTOR(7) /* Pin Change Interrupt Request 3 */ +-#define WDT_vect_num 8 +-#define WDT_vect _VECTOR(8) /* Watchdog Time-out Interrupt */ +-#define TIMER2_COMPA_vect_num 9 +-#define TIMER2_COMPA_vect _VECTOR(9) /* Timer/Counter2 Compare Match A */ +-#define TIMER2_COMPB_vect_num 10 +-#define TIMER2_COMPB_vect _VECTOR(10) /* Timer/Counter2 Compare Match B */ +-#define TIMER2_OVF_vect_num 11 +-#define TIMER2_OVF_vect _VECTOR(11) /* Timer/Counter2 Overflow */ +-#define TIMER1_CAPT_vect_num 12 +-#define TIMER1_CAPT_vect _VECTOR(12) /* Timer/Counter1 Capture Event */ +-#define TIMER1_COMPA_vect_num 13 +-#define TIMER1_COMPA_vect _VECTOR(13) /* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPB_vect_num 14 +-#define TIMER1_COMPB_vect _VECTOR(14) /* Timer/Counter1 Compare Match B */ +-#define TIMER1_OVF_vect_num 15 +-#define TIMER1_OVF_vect _VECTOR(15) /* Timer/Counter1 Overflow */ +-#define TIMER0_COMPA_vect_num 16 +-#define TIMER0_COMPA_vect _VECTOR(16) /* Timer/Counter0 Compare Match A */ +-#define TIMER0_COMPB_vect_num 17 +-#define TIMER0_COMPB_vect _VECTOR(17) /* Timer/Counter0 Compare Match B */ +-#define TIMER0_OVF_vect_num 18 +-#define TIMER0_OVF_vect _VECTOR(18) /* Timer/Counter0 Overflow */ +-#define SPI_STC_vect_num 19 +-#define SPI_STC_vect _VECTOR(19) /* SPI Serial Transfer Complete */ +-#define USART0_RX_vect_num 20 +-#define USART0_RX_vect _VECTOR(20) /* USART0, Rx Complete */ +-#define USART0_UDRE_vect_num 21 +-#define USART0_UDRE_vect _VECTOR(21) /* USART0 Data register Empty */ +-#define USART0_TX_vect_num 22 +-#define USART0_TX_vect _VECTOR(22) /* USART0, Tx Complete */ +-#define ANALOG_COMP_vect_num 23 +-#define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */ +-#define ADC_vect_num 24 +-#define ADC_vect _VECTOR(24) /* ADC Conversion Complete */ +-#define EE_READY_vect_num 25 +-#define EE_READY_vect _VECTOR(25) /* EEPROM Ready */ +-#define TWI_vect_num 26 +-#define TWI_vect _VECTOR(26) /* 2-wire Serial Interface */ +-#define SPM_READY_vect_num 27 +-#define SPM_READY_vect _VECTOR(27) /* Store Program Memory Read */ +-#define USART1_RX_vect_num 28 +-#define USART1_RX_vect _VECTOR(28) /* USART1 RX complete */ +-#define USART1_UDRE_vect_num 29 +-#define USART1_UDRE_vect _VECTOR(29) /* USART1 Data Register Empty */ +-#define USART1_TX_vect_num 30 +-#define USART1_TX_vect _VECTOR(30) /* USART1 TX complete */ +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (31 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (128) +-#define RAMSTART (0x100) +-#define RAMSIZE (2048) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (0x0) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x3FF) +-#define E2PAGESIZE (4) +-#define FLASHEND (0x7FFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ +-#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ +-#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x95 +-#define SIGNATURE_2 0x11 +- +- +-/* Device Pin Definitions */ +-#define MOSI_DDR DDRB +-#define MOSI_PORT PORTB +-#define MOSI_PIN PINB +-#define MOSI_BIT 5 +- +-#define PCINT13_DDR DDRB +-#define PCINT13_PORT PORTB +-#define PCINT13_PIN PINB +-#define PCINT13_BIT 5 +- +-#define MISO_DDR DDRB +-#define MISO_PORT PORTB +-#define MISO_PIN PINB +-#define MISO_BIT 6 +- +-#define PCINT14_DDR DDRB +-#define PCINT14_PORT PORTB +-#define PCINT14_PIN PINB +-#define PCINT14_BIT 6 +- +-#define SCK_DDR DDRB +-#define SCK_PORT PORTB +-#define SCK_PIN PINB +-#define SCK_BIT 7 +- +-#define PCINT15_DDR DDRB +-#define PCINT15_PORT PORTB +-#define PCINT15_PIN PINB +-#define PCINT15_BIT 7 +- +-#define RXD_DDR DDRD +-#define RXD_PORT PORTD +-#define RXD_PIN PIND +-#define RXD_BIT 0 +- +-#define PCINT24_DDR DDRD +-#define PCINT24_PORT PORTD +-#define PCINT24_PIN PIND +-#define PCINT24_BIT 0 +- +-#define TXD_DDR DDRD +-#define TXD_PORT PORTD +-#define TXD_PIN PIND +-#define TXD_BIT 1 +- +-#define PCINT25_DDR DDRD +-#define PCINT25_PORT PORTD +-#define PCINT25_PIN PIND +-#define PCINT25_BIT 1 +- +-#define INT0_DDR DDRD +-#define INT0_PORT PORTD +-#define INT0_PIN PIND +-#define INT0_BIT 2 +- +-#define PCINT26_DDR DDRD +-#define PCINT26_PORT PORTD +-#define PCINT26_PIN PIND +-#define PCINT26_BIT 2 +- +-#define INT1_DDR DDRD +-#define INT1_PORT PORTD +-#define INT1_PIN PIND +-#define INT1_BIT 3 +- +-#define PCINT27_DDR DDRD +-#define PCINT27_PORT PORTD +-#define PCINT27_PIN PIND +-#define PCINT27_BIT 3 +- +-#define OC1B_DDR DDRD +-#define OC1B_PORT PORTD +-#define OC1B_PIN PIND +-#define OC1B_BIT 4 +- +-#define PCINT28_DDR DDRD +-#define PCINT28_PORT PORTD +-#define PCINT28_PIN PIND +-#define PCINT28_BIT 4 +- +-#define OC1A_DDR DDRD +-#define OC1A_PORT PORTD +-#define OC1A_PIN PIND +-#define OC1A_BIT 5 +- +-#define PCINT29_DDR DDRD +-#define PCINT29_PORT PORTD +-#define PCINT29_PIN PIND +-#define PCINT29_BIT 5 +- +-#define ICP_DDR DDRD +-#define ICP_PORT PORTD +-#define ICP_PIN PIND +-#define ICP_BIT 6 +- +-#define OC2B_DDR DDRD +-#define OC2B_PORT PORTD +-#define OC2B_PIN PIND +-#define OC2B_BIT 6 +- +-#define PCINT30_DDR DDRD +-#define PCINT30_PORT PORTD +-#define PCINT30_PIN PIND +-#define PCINT30_BIT 6 +- +-#define OC2A_DDR DDRD +-#define OC2A_PORT PORTD +-#define OC2A_PIN PIND +-#define OC2A_BIT 7 +- +-#define PCINT31_DDR DDRD +-#define PCINT31_PORT PORTD +-#define PCINT31_PIN PIND +-#define PCINT31_BIT 7 +- +-#define SCL_DDR DDRC +-#define SCL_PORT PORTC +-#define SCL_PIN PINC +-#define SCL_BIT 0 +- +-#define PCINT16_DDR DDRC +-#define PCINT16_PORT PORTC +-#define PCINT16_PIN PINC +-#define PCINT16_BIT 0 +- +-#define SDA_DDR DDRC +-#define SDA_PORT PORTC +-#define SDA_PIN PINC +-#define SDA_BIT 1 +- +-#define PCINT17_DDR DDRC +-#define PCINT17_PORT PORTC +-#define PCINT17_PIN PINC +-#define PCINT17_BIT 1 +- +-#define PCINT18_DDR DDRC +-#define PCINT18_PORT PORTC +-#define PCINT18_PIN PINC +-#define PCINT18_BIT 2 +- +-#define PCINT19_DDR DDRC +-#define PCINT19_PORT PORTC +-#define PCINT19_PIN PINC +-#define PCINT19_BIT 3 +- +-#define PCINT20_DDR DDRC +-#define PCINT20_PORT PORTC +-#define PCINT20_PIN PINC +-#define PCINT20_BIT 4 +- +-#define PCINT21_DDR DDRC +-#define PCINT21_PORT PORTC +-#define PCINT21_PIN PINC +-#define PCINT21_BIT 5 +- +-#define PCINT22_DDR DDRC +-#define PCINT22_PORT PORTC +-#define PCINT22_PIN PINC +-#define PCINT22_BIT 6 +- +-#define PCINT23_DDR DDRC +-#define PCINT23_PORT PORTC +-#define PCINT23_PIN PINC +-#define PCINT23_BIT 7 +- +-#define ADC7_DDR DDRA +-#define ADC7_PORT PORTA +-#define ADC7_PIN PINA +-#define ADC7_BIT 7 +- +-#define PCINT7_DDR DDRA +-#define PCINT7_PORT PORTA +-#define PCINT7_PIN PINA +-#define PCINT7_BIT 7 +- +-#define ADC6_DDR DDRA +-#define ADC6_PORT PORTA +-#define ADC6_PIN PINA +-#define ADC6_BIT 6 +- +-#define PCINT6_DDR DDRA +-#define PCINT6_PORT PORTA +-#define PCINT6_PIN PINA +-#define PCINT6_BIT 6 +- +-#define ADC5_DDR DDRA +-#define ADC5_PORT PORTA +-#define ADC5_PIN PINA +-#define ADC5_BIT 5 +- +-#define PCINT5_DDR DDRA +-#define PCINT5_PORT PORTA +-#define PCINT5_PIN PINA +-#define PCINT5_BIT 5 +- +-#define ADC4_DDR DDRA +-#define ADC4_PORT PORTA +-#define ADC4_PIN PINA +-#define ADC4_BIT 4 +- +-#define PCINT4_DDR DDRA +-#define PCINT4_PORT PORTA +-#define PCINT4_PIN PINA +-#define PCINT4_BIT 4 +- +-#define ADC3_DDR DDRA +-#define ADC3_PORT PORTA +-#define ADC3_PIN PINA +-#define ADC3_BIT 3 +- +-#define PCINT3_DDR DDRA +-#define PCINT3_PORT PORTA +-#define PCINT3_PIN PINA +-#define PCINT3_BIT 3 +- +-#define ADC2_DDR DDRA +-#define ADC2_PORT PORTA +-#define ADC2_PIN PINA +-#define ADC2_BIT 2 +- +-#define PCINT2_DDR DDRA +-#define PCINT2_PORT PORTA +-#define PCINT2_PIN PINA +-#define PCINT2_BIT 2 +- +-#define ADC1_DDR DDRA +-#define ADC1_PORT PORTA +-#define ADC1_PIN PINA +-#define ADC1_BIT 1 +- +-#define PCINT1_DDR DDRA +-#define PCINT1_PORT PORTA +-#define PCINT1_PIN PINA +-#define PCINT1_BIT 1 +- +-#define ADC0_DDR DDRA +-#define ADC0_PORT PORTA +-#define ADC0_PIN PINA +-#define ADC0_BIT 0 +- +-#define PCINT0_DDR DDRA +-#define PCINT0_PORT PORTA +-#define PCINT0_PIN PINA +-#define PCINT0_BIT 0 +- +-#define XCK_DDR DDRB +-#define XCK_PORT PORTB +-#define XCK_PIN PINB +-#define XCK_BIT 0 +- +-#define T0_DDR DDRB +-#define T0_PORT PORTB +-#define T0_PIN PINB +-#define T0_BIT 0 +- +-#define PCINT8_DDR DDRB +-#define PCINT8_PORT PORTB +-#define PCINT8_PIN PINB +-#define PCINT8_BIT 0 +- +-#define T1_DDR DDRB +-#define T1_PORT PORTB +-#define T1_PIN PINB +-#define T1_BIT 1 +- +-#define CLKO_DDR DDRB +-#define CLKO_PORT PORTB +-#define CLKO_PIN PINB +-#define CLKO_BIT 1 +- +-#define PCINT9_DDR DDRB +-#define PCINT9_PORT PORTB +-#define PCINT9_PIN PINB +-#define PCINT9_BIT 1 +- +-#define AIN0_DDR DDRB +-#define AIN0_PORT PORTB +-#define AIN0_PIN PINB +-#define AIN0_BIT 2 +- +-#define INT2_DDR DDRB +-#define INT2_PORT PORTB +-#define INT2_PIN PINB +-#define INT2_BIT 2 +- +-#define PCINT10_DDR DDRB +-#define PCINT10_PORT PORTB +-#define PCINT10_PIN PINB +-#define PCINT10_BIT 2 +- +-#define AIN1_DDR DDRB +-#define AIN1_PORT PORTB +-#define AIN1_PIN PINB +-#define AIN1_BIT 3 +- +-#define OC0A_DDR DDRB +-#define OC0A_PORT PORTB +-#define OC0A_PIN PINB +-#define OC0A_BIT 3 +- +-#define PCINT11_DDR DDRB +-#define PCINT11_PORT PORTB +-#define PCINT11_PIN PINB +-#define PCINT11_BIT 3 +- +-#define SS_DDR DDRB +-#define SS_PORT PORTB +-#define SS_PIN PINB +-#define SS_BIT 4 +- +-#define OC0B_DDR DDRB +-#define OC0B_PORT PORTB +-#define OC0B_PIN PINB +-#define OC0B_BIT 4 +- +-#define PCINT12_DDR DDRB +-#define PCINT12_PORT PORTB +-#define PCINT12_PIN PINB +-#define PCINT12_BIT 4 +- +-#endif /* _AVR_ATmega324PA_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom324pa.h 2063 2009-11-18 22:06:28Z arcanum $ */ ++ ++/* avr/iom324pa.h - definitions for ATmega324PA */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom324pa.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATmega324PA_H_ ++#define _AVR_ATmega324PA_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++#define PINA4 4 ++#define PINA5 5 ++#define PINA6 6 ++#define PINA7 7 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++#define DDA4 4 ++#define DDA5 5 ++#define DDA6 6 ++#define DDA7 7 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA0 0 ++#define PORTA1 1 ++#define PORTA2 2 ++#define PORTA3 3 ++#define PORTA4 4 ++#define PORTA5 5 ++#define PORTA6 6 ++#define PORTA7 7 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++#define PINC7 7 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++#define DDC7 7 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC3 3 ++#define PORTC4 4 ++#define PORTC5 5 ++#define PORTC6 6 ++#define PORTC7 7 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++#define PCIF3 3 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++#define EEAR9 1 ++#define EEAR10 2 ++#define EEAR11 3 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define PSRASY 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define OCR0A _SFR_IO8(0x27) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define OCR0B _SFR_IO8(0x28) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR0 _SFR_IO8(0x2C) ++#define SPR00 0 ++#define SPR10 1 ++#define CPHA0 2 ++#define CPOL0 3 ++#define MSTR0 4 ++#define DORD0 5 ++#define SPE0 6 ++#define SPIE0 7 ++ ++#define SPSR0 _SFR_IO8(0x2D) ++#define SPI2X0 0 ++#define WCOL0 6 ++#define SPIF0 7 ++ ++#define SPDR0 _SFR_IO8(0x2E) ++#define SPDRB0 0 ++#define SPDRB1 1 ++#define SPDRB2 2 ++#define SPDRB3 3 ++#define SPDRB4 4 ++#define SPDRB5 5 ++#define SPDRB6 6 ++#define SPDRB7 7 ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCDR7 7 ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define JTRF 4 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++#define JTD 7 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRUSART1 4 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++#define PCIE3 3 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++#define PCMSK3 _SFR_MEM8(0x73) ++#define PCINT24 0 ++#define PCINT25 1 ++#define PCINT26 2 ++#define PCINT27 3 ++#define PCINT28 4 ++#define PCINT29 5 ++#define PCINT30 6 ++#define PCINT31 7 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_MEM8(0x79) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++#define TCNT2_0 0 ++#define TCNT2_1 1 ++#define TCNT2_2 2 ++#define TCNT2_3 3 ++#define TCNT2_4 4 ++#define TCNT2_5 5 ++#define TCNT2_6 6 ++#define TCNT2_7 7 ++ ++#define OCR2A _SFR_MEM8(0xB3) ++#define OCR2A_0 0 ++#define OCR2A_1 1 ++#define OCR2A_2 2 ++#define OCR2A_3 3 ++#define OCR2A_4 4 ++#define OCR2A_5 5 ++#define OCR2A_6 6 ++#define OCR2A_7 7 ++ ++#define OCR2B _SFR_MEM8(0xB4) ++#define OCR2B_0 0 ++#define OCR2B_1 1 ++#define OCR2B_2 2 ++#define OCR2B_3 3 ++#define OCR2B_4 4 ++#define OCR2B_5 5 ++#define OCR2B_6 6 ++#define OCR2B_7 7 ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++ ++#define TWBR _SFR_MEM8(0xB8) ++#define TWBR0 0 ++#define TWBR1 1 ++#define TWBR2 2 ++#define TWBR3 3 ++#define TWBR4 4 ++#define TWBR5 5 ++#define TWBR6 6 ++#define TWBR7 7 ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++#define TWD0 0 ++#define TWD1 1 ++#define TWD2 2 ++#define TWD3 3 ++#define TWD4 4 ++#define TWD5 5 ++#define TWD6 6 ++#define TWD7 7 ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define _UBRR0 0 ++#define _UBRR1 1 ++#define UBRR2 2 ++#define UBRR3 3 ++#define UBRR4 4 ++#define UBRR5 5 ++#define UBRR6 6 ++#define UBRR7 7 ++ ++#define UBRR0H _SFR_MEM8(0xC5) ++#define UBRR8 0 ++#define UBRR9 1 ++#define UBRR10 2 ++#define UBRR11 3 ++ ++#define UDR0 _SFR_MEM8(0xC6) ++#define UDR0_0 0 ++#define UDR0_1 1 ++#define UDR0_2 2 ++#define UDR0_3 3 ++#define UDR0_4 4 ++#define UDR0_5 5 ++#define UDR0_6 6 ++#define UDR0_7 7 ++ ++#define UCSR1A _SFR_MEM8(0xC8) ++#define MPCM1 0 ++#define U2X1 1 ++#define UPE1 2 ++#define DOR1 3 ++#define FE1 4 ++#define UDRE1 5 ++#define TXC1 6 ++#define RXC1 7 ++ ++#define UCSR1B _SFR_MEM8(0xC9) ++#define TXB81 0 ++#define RXB81 1 ++#define UCSZ12 2 ++#define TXEN1 3 ++#define RXEN1 4 ++#define UDRIE1 5 ++#define TXCIE1 6 ++#define RXCIE1 7 ++ ++#define UCSR1C _SFR_MEM8(0xCA) ++#define UCPOL1 0 ++#define UCSZ10 1 ++#define UCSZ11 2 ++#define USBS1 3 ++#define UPM10 4 ++#define UPM11 5 ++#define UMSEL10 6 ++#define UMSEL11 7 ++ ++#define UBRR1 _SFR_MEM16(0xCC) ++ ++#define UBRR1L _SFR_MEM8(0xCC) ++#define UBRR_0 0 ++#define UBRR_1 1 ++#define UBRR_2 2 ++#define UBRR_3 3 ++#define UBRR_4 4 ++#define UBRR_5 5 ++#define UBRR_6 6 ++#define UBRR_7 7 ++ ++#define UBRR1H _SFR_MEM8(0xCD) ++#define UBRR_8 0 ++#define UBRR_9 1 ++#define UBRR_10 2 ++#define UBRR_11 3 ++ ++#define UDR1 _SFR_MEM8(0xCE) ++#define UDR1_0 0 ++#define UDR1_1 1 ++#define UDR1_2 2 ++#define UDR1_3 3 ++#define UDR1_4 4 ++#define UDR1_5 5 ++#define UDR1_6 6 ++#define UDR1_7 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ ++#define INT2_vect_num 3 ++#define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ ++#define PCINT0_vect_num 4 ++#define PCINT0_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect_num 5 ++#define PCINT1_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */ ++#define PCINT2_vect_num 6 ++#define PCINT2_vect _VECTOR(6) /* Pin Change Interrupt Request 2 */ ++#define PCINT3_vect_num 7 ++#define PCINT3_vect _VECTOR(7) /* Pin Change Interrupt Request 3 */ ++#define WDT_vect_num 8 ++#define WDT_vect _VECTOR(8) /* Watchdog Time-out Interrupt */ ++#define TIMER2_COMPA_vect_num 9 ++#define TIMER2_COMPA_vect _VECTOR(9) /* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPB_vect_num 10 ++#define TIMER2_COMPB_vect _VECTOR(10) /* Timer/Counter2 Compare Match B */ ++#define TIMER2_OVF_vect_num 11 ++#define TIMER2_OVF_vect _VECTOR(11) /* Timer/Counter2 Overflow */ ++#define TIMER1_CAPT_vect_num 12 ++#define TIMER1_CAPT_vect _VECTOR(12) /* Timer/Counter1 Capture Event */ ++#define TIMER1_COMPA_vect_num 13 ++#define TIMER1_COMPA_vect _VECTOR(13) /* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPB_vect_num 14 ++#define TIMER1_COMPB_vect _VECTOR(14) /* Timer/Counter1 Compare Match B */ ++#define TIMER1_OVF_vect_num 15 ++#define TIMER1_OVF_vect _VECTOR(15) /* Timer/Counter1 Overflow */ ++#define TIMER0_COMPA_vect_num 16 ++#define TIMER0_COMPA_vect _VECTOR(16) /* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPB_vect_num 17 ++#define TIMER0_COMPB_vect _VECTOR(17) /* Timer/Counter0 Compare Match B */ ++#define TIMER0_OVF_vect_num 18 ++#define TIMER0_OVF_vect _VECTOR(18) /* Timer/Counter0 Overflow */ ++#define SPI_STC_vect_num 19 ++#define SPI_STC_vect _VECTOR(19) /* SPI Serial Transfer Complete */ ++#define USART0_RX_vect_num 20 ++#define USART0_RX_vect _VECTOR(20) /* USART0, Rx Complete */ ++#define USART0_UDRE_vect_num 21 ++#define USART0_UDRE_vect _VECTOR(21) /* USART0 Data register Empty */ ++#define USART0_TX_vect_num 22 ++#define USART0_TX_vect _VECTOR(22) /* USART0, Tx Complete */ ++#define ANALOG_COMP_vect_num 23 ++#define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */ ++#define ADC_vect_num 24 ++#define ADC_vect _VECTOR(24) /* ADC Conversion Complete */ ++#define EE_READY_vect_num 25 ++#define EE_READY_vect _VECTOR(25) /* EEPROM Ready */ ++#define TWI_vect_num 26 ++#define TWI_vect _VECTOR(26) /* 2-wire Serial Interface */ ++#define SPM_READY_vect_num 27 ++#define SPM_READY_vect _VECTOR(27) /* Store Program Memory Read */ ++#define USART1_RX_vect_num 28 ++#define USART1_RX_vect _VECTOR(28) /* USART1 RX complete */ ++#define USART1_UDRE_vect_num 29 ++#define USART1_UDRE_vect _VECTOR(29) /* USART1 Data Register Empty */ ++#define USART1_TX_vect_num 30 ++#define USART1_TX_vect _VECTOR(30) /* USART1 TX complete */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (31 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (128) ++#define RAMSTART (0x100) ++#define RAMSIZE (2048) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (0x0) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x3FF) ++#define E2PAGESIZE (4) ++#define FLASHEND (0x7FFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ ++#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ ++#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x11 ++ ++ ++/* Device Pin Definitions */ ++#define MOSI_DDR DDRB ++#define MOSI_PORT PORTB ++#define MOSI_PIN PINB ++#define MOSI_BIT 5 ++ ++#define PCINT13_DDR DDRB ++#define PCINT13_PORT PORTB ++#define PCINT13_PIN PINB ++#define PCINT13_BIT 5 ++ ++#define MISO_DDR DDRB ++#define MISO_PORT PORTB ++#define MISO_PIN PINB ++#define MISO_BIT 6 ++ ++#define PCINT14_DDR DDRB ++#define PCINT14_PORT PORTB ++#define PCINT14_PIN PINB ++#define PCINT14_BIT 6 ++ ++#define SCK_DDR DDRB ++#define SCK_PORT PORTB ++#define SCK_PIN PINB ++#define SCK_BIT 7 ++ ++#define PCINT15_DDR DDRB ++#define PCINT15_PORT PORTB ++#define PCINT15_PIN PINB ++#define PCINT15_BIT 7 ++ ++#define RXD_DDR DDRD ++#define RXD_PORT PORTD ++#define RXD_PIN PIND ++#define RXD_BIT 0 ++ ++#define PCINT24_DDR DDRD ++#define PCINT24_PORT PORTD ++#define PCINT24_PIN PIND ++#define PCINT24_BIT 0 ++ ++#define TXD_DDR DDRD ++#define TXD_PORT PORTD ++#define TXD_PIN PIND ++#define TXD_BIT 1 ++ ++#define PCINT25_DDR DDRD ++#define PCINT25_PORT PORTD ++#define PCINT25_PIN PIND ++#define PCINT25_BIT 1 ++ ++#define INT0_DDR DDRD ++#define INT0_PORT PORTD ++#define INT0_PIN PIND ++#define INT0_BIT 2 ++ ++#define PCINT26_DDR DDRD ++#define PCINT26_PORT PORTD ++#define PCINT26_PIN PIND ++#define PCINT26_BIT 2 ++ ++#define INT1_DDR DDRD ++#define INT1_PORT PORTD ++#define INT1_PIN PIND ++#define INT1_BIT 3 ++ ++#define PCINT27_DDR DDRD ++#define PCINT27_PORT PORTD ++#define PCINT27_PIN PIND ++#define PCINT27_BIT 3 ++ ++#define OC1B_DDR DDRD ++#define OC1B_PORT PORTD ++#define OC1B_PIN PIND ++#define OC1B_BIT 4 ++ ++#define PCINT28_DDR DDRD ++#define PCINT28_PORT PORTD ++#define PCINT28_PIN PIND ++#define PCINT28_BIT 4 ++ ++#define OC1A_DDR DDRD ++#define OC1A_PORT PORTD ++#define OC1A_PIN PIND ++#define OC1A_BIT 5 ++ ++#define PCINT29_DDR DDRD ++#define PCINT29_PORT PORTD ++#define PCINT29_PIN PIND ++#define PCINT29_BIT 5 ++ ++#define ICP_DDR DDRD ++#define ICP_PORT PORTD ++#define ICP_PIN PIND ++#define ICP_BIT 6 ++ ++#define OC2B_DDR DDRD ++#define OC2B_PORT PORTD ++#define OC2B_PIN PIND ++#define OC2B_BIT 6 ++ ++#define PCINT30_DDR DDRD ++#define PCINT30_PORT PORTD ++#define PCINT30_PIN PIND ++#define PCINT30_BIT 6 ++ ++#define OC2A_DDR DDRD ++#define OC2A_PORT PORTD ++#define OC2A_PIN PIND ++#define OC2A_BIT 7 ++ ++#define PCINT31_DDR DDRD ++#define PCINT31_PORT PORTD ++#define PCINT31_PIN PIND ++#define PCINT31_BIT 7 ++ ++#define SCL_DDR DDRC ++#define SCL_PORT PORTC ++#define SCL_PIN PINC ++#define SCL_BIT 0 ++ ++#define PCINT16_DDR DDRC ++#define PCINT16_PORT PORTC ++#define PCINT16_PIN PINC ++#define PCINT16_BIT 0 ++ ++#define SDA_DDR DDRC ++#define SDA_PORT PORTC ++#define SDA_PIN PINC ++#define SDA_BIT 1 ++ ++#define PCINT17_DDR DDRC ++#define PCINT17_PORT PORTC ++#define PCINT17_PIN PINC ++#define PCINT17_BIT 1 ++ ++#define PCINT18_DDR DDRC ++#define PCINT18_PORT PORTC ++#define PCINT18_PIN PINC ++#define PCINT18_BIT 2 ++ ++#define PCINT19_DDR DDRC ++#define PCINT19_PORT PORTC ++#define PCINT19_PIN PINC ++#define PCINT19_BIT 3 ++ ++#define PCINT20_DDR DDRC ++#define PCINT20_PORT PORTC ++#define PCINT20_PIN PINC ++#define PCINT20_BIT 4 ++ ++#define PCINT21_DDR DDRC ++#define PCINT21_PORT PORTC ++#define PCINT21_PIN PINC ++#define PCINT21_BIT 5 ++ ++#define PCINT22_DDR DDRC ++#define PCINT22_PORT PORTC ++#define PCINT22_PIN PINC ++#define PCINT22_BIT 6 ++ ++#define PCINT23_DDR DDRC ++#define PCINT23_PORT PORTC ++#define PCINT23_PIN PINC ++#define PCINT23_BIT 7 ++ ++#define ADC7_DDR DDRA ++#define ADC7_PORT PORTA ++#define ADC7_PIN PINA ++#define ADC7_BIT 7 ++ ++#define PCINT7_DDR DDRA ++#define PCINT7_PORT PORTA ++#define PCINT7_PIN PINA ++#define PCINT7_BIT 7 ++ ++#define ADC6_DDR DDRA ++#define ADC6_PORT PORTA ++#define ADC6_PIN PINA ++#define ADC6_BIT 6 ++ ++#define PCINT6_DDR DDRA ++#define PCINT6_PORT PORTA ++#define PCINT6_PIN PINA ++#define PCINT6_BIT 6 ++ ++#define ADC5_DDR DDRA ++#define ADC5_PORT PORTA ++#define ADC5_PIN PINA ++#define ADC5_BIT 5 ++ ++#define PCINT5_DDR DDRA ++#define PCINT5_PORT PORTA ++#define PCINT5_PIN PINA ++#define PCINT5_BIT 5 ++ ++#define ADC4_DDR DDRA ++#define ADC4_PORT PORTA ++#define ADC4_PIN PINA ++#define ADC4_BIT 4 ++ ++#define PCINT4_DDR DDRA ++#define PCINT4_PORT PORTA ++#define PCINT4_PIN PINA ++#define PCINT4_BIT 4 ++ ++#define ADC3_DDR DDRA ++#define ADC3_PORT PORTA ++#define ADC3_PIN PINA ++#define ADC3_BIT 3 ++ ++#define PCINT3_DDR DDRA ++#define PCINT3_PORT PORTA ++#define PCINT3_PIN PINA ++#define PCINT3_BIT 3 ++ ++#define ADC2_DDR DDRA ++#define ADC2_PORT PORTA ++#define ADC2_PIN PINA ++#define ADC2_BIT 2 ++ ++#define PCINT2_DDR DDRA ++#define PCINT2_PORT PORTA ++#define PCINT2_PIN PINA ++#define PCINT2_BIT 2 ++ ++#define ADC1_DDR DDRA ++#define ADC1_PORT PORTA ++#define ADC1_PIN PINA ++#define ADC1_BIT 1 ++ ++#define PCINT1_DDR DDRA ++#define PCINT1_PORT PORTA ++#define PCINT1_PIN PINA ++#define PCINT1_BIT 1 ++ ++#define ADC0_DDR DDRA ++#define ADC0_PORT PORTA ++#define ADC0_PIN PINA ++#define ADC0_BIT 0 ++ ++#define PCINT0_DDR DDRA ++#define PCINT0_PORT PORTA ++#define PCINT0_PIN PINA ++#define PCINT0_BIT 0 ++ ++#define XCK_DDR DDRB ++#define XCK_PORT PORTB ++#define XCK_PIN PINB ++#define XCK_BIT 0 ++ ++#define T0_DDR DDRB ++#define T0_PORT PORTB ++#define T0_PIN PINB ++#define T0_BIT 0 ++ ++#define PCINT8_DDR DDRB ++#define PCINT8_PORT PORTB ++#define PCINT8_PIN PINB ++#define PCINT8_BIT 0 ++ ++#define T1_DDR DDRB ++#define T1_PORT PORTB ++#define T1_PIN PINB ++#define T1_BIT 1 ++ ++#define CLKO_DDR DDRB ++#define CLKO_PORT PORTB ++#define CLKO_PIN PINB ++#define CLKO_BIT 1 ++ ++#define PCINT9_DDR DDRB ++#define PCINT9_PORT PORTB ++#define PCINT9_PIN PINB ++#define PCINT9_BIT 1 ++ ++#define AIN0_DDR DDRB ++#define AIN0_PORT PORTB ++#define AIN0_PIN PINB ++#define AIN0_BIT 2 ++ ++#define INT2_DDR DDRB ++#define INT2_PORT PORTB ++#define INT2_PIN PINB ++#define INT2_BIT 2 ++ ++#define PCINT10_DDR DDRB ++#define PCINT10_PORT PORTB ++#define PCINT10_PIN PINB ++#define PCINT10_BIT 2 ++ ++#define AIN1_DDR DDRB ++#define AIN1_PORT PORTB ++#define AIN1_PIN PINB ++#define AIN1_BIT 3 ++ ++#define OC0A_DDR DDRB ++#define OC0A_PORT PORTB ++#define OC0A_PIN PINB ++#define OC0A_BIT 3 ++ ++#define PCINT11_DDR DDRB ++#define PCINT11_PORT PORTB ++#define PCINT11_PIN PINB ++#define PCINT11_BIT 3 ++ ++#define SS_DDR DDRB ++#define SS_PORT PORTB ++#define SS_PIN PINB ++#define SS_BIT 4 ++ ++#define OC0B_DDR DDRB ++#define OC0B_PORT PORTB ++#define OC0B_PIN PINB ++#define OC0B_BIT 4 ++ ++#define PCINT12_DDR DDRB ++#define PCINT12_PORT PORTB ++#define PCINT12_PIN PINB ++#define PCINT12_BIT 4 ++ ++#endif /* _AVR_ATmega324PA_H_ */ ++ +diff --git a/include/avr/iom325.h b/include/avr/iom325.h +index cbecaf2..d4ce3a3 100644 +--- a/include/avr/iom325.h ++++ b/include/avr/iom325.h +@@ -1,875 +1,875 @@ +-/* Copyright (c) 2004, 2005, 2006, 2007 Eric B. Weddington +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom325.h 2234 2011-03-16 04:32:21Z arcanum $ */ +- +-/* avr/iom325.h - definitions for ATmega325 and ATmega325P. */ +- +-#ifndef _AVR_IOM325_H_ +-#define _AVR_IOM325_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom325.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* Registers and associated bit numbers */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-#define PORTA _SFR_IO8(0x02) +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-#define PINB _SFR_IO8(0x03) +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-#define PORTB _SFR_IO8(0x05) +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-#define PORTC _SFR_IO8(0x08) +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-#define PINE _SFR_IO8(0x0C) +-#define PINE7 7 +-#define PINE6 6 +-#define PINE5 5 +-#define PINE4 4 +-#define PINE3 3 +-#define PINE2 2 +-#define PINE1 1 +-#define PINE0 0 +- +-#define DDRE _SFR_IO8(0x0D) +-#define DDE7 7 +-#define DDE6 6 +-#define DDE5 5 +-#define DDE4 4 +-#define DDE3 3 +-#define DDE2 2 +-#define DDE1 1 +-#define DDE0 0 +- +-#define PORTE _SFR_IO8(0x0E) +-#define PE7 7 +-#define PE6 6 +-#define PE5 5 +-#define PE4 4 +-#define PE3 3 +-#define PE2 2 +-#define PE1 1 +-#define PE0 0 +- +-#define PINF _SFR_IO8(0x0F) +-#define PINF7 7 +-#define PINF6 6 +-#define PINF5 5 +-#define PINF4 4 +-#define PINF3 3 +-#define PINF2 2 +-#define PINF1 1 +-#define PINF0 0 +- +-#define DDRF _SFR_IO8(0x10) +-#define DDF7 7 +-#define DDF6 6 +-#define DDF5 5 +-#define DDF4 4 +-#define DDF3 3 +-#define DDF2 2 +-#define DDF1 1 +-#define DDF0 0 +- +-#define PORTF _SFR_IO8(0x11) +-#define PF7 7 +-#define PF6 6 +-#define PF5 5 +-#define PF4 4 +-#define PF3 3 +-#define PF2 2 +-#define PF1 1 +-#define PF0 0 +- +-#define PING _SFR_IO8(0x12) +-#define PING5 5 +-#define PING4 4 +-#define PING3 3 +-#define PING2 2 +-#define PING1 1 +-#define PING0 0 +- +-#define DDRG _SFR_IO8(0x13) +-#define DDG4 4 +-#define DDG3 3 +-#define DDG2 2 +-#define DDG1 1 +-#define DDG0 0 +- +-#define PORTG _SFR_IO8(0x14) +-#define PG4 4 +-#define PG3 3 +-#define PG2 2 +-#define PG1 1 +-#define PG0 0 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define TIFR2 _SFR_IO8(0x17) +-#define TOV2 0 +-#define OCF2A 1 +- +-/* Reserved [0x18..0x1B] */ +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define PCIF0 4 +-#define PCIF1 5 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define PCIE0 4 +-#define PCIE1 5 +- +-#define GPIOR0 _SFR_IO8(0x1E) +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEWE 1 +-#define EEMWE 2 +-#define EERIE 3 +- +-#define EEDR _SFR_IO8(0X20) +- +-/* Combine EEARL and EEARH */ +-#define EEAR _SFR_IO16(0x21) +-#define EEARL _SFR_IO8(0x21) +-#define EEARH _SFR_IO8(0X22) +- +-/* 6-char sequence denoting where to find the EEPROM registers in memory space. +- Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM +- subroutines. +- First two letters: EECR address. +- Second two letters: EEDR address. +- Last two letters: EEAR address. */ +-#define __EEPROM_REG_LOCATIONS__ 1F2021 +- +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSR10 0 +-#define PSR2 1 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM01 3 +-#define COM0A0 4 +-#define COM0A1 5 +-#define WGM00 6 +-#define FOC0A 7 +- +-/* Reserved [0x25] */ +- +-#define TCNT0 _SFR_IO8(0X26) +- +-#define OCR0A _SFR_IO8(0X27) +- +-/* Reserved [0x28..0x29] */ +- +-#define GPIOR1 _SFR_IO8(0x2A) +- +-#define GPIOR2 _SFR_IO8(0x2B) +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0X2E) +- +-/* Reserved [0x2F] */ +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define OCDR _SFR_IO8(0x31) +-#define OCDR0 0 +-#define OCDR1 1 +-#define OCDR2 2 +-#define OCDR3 3 +-#define OCDR4 4 +-#define OCDR5 5 +-#define OCDR6 6 +-#define OCDR7 7 +-#define IDRD 7 +- +-/* Reserved [0x32] */ +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +-#define JTRF 4 +- +-#define MCUCR _SFR_IO8(0X35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#if defined(__AVR_ATmega325P__) +-#define BODSE 5 +-#define BODS 6 +-#endif +-#define JTD 7 +- +-/* Reserved [0x36] */ +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define RWWSB 6 +-#define SPMIE 7 +- +-/* Reserved [0x38..0x3C] */ +- +-/* SP [0x3D..0x3E] */ +-/* SREG [0x3F] */ +- +-#define WDTCR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-/* Reserved [0x62..0x63] */ +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM1 3 +- +-/* Reserved [0x65] */ +- +-#define OSCCAL _SFR_MEM8(0x66) +- +-/* Reserved [0x67..0x68] */ +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +- +-/* Reserved [0x6A] */ +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-/* Reserved [0x6D] */ +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define TIMSK2 _SFR_MEM8(0x70) +-#define TOIE2 0 +-#define OCIE2A 1 +- +-/* Reserved [0x71..0x77] */ +- +-/* Combine ADCL and ADCH */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +-#define ADCL _SFR_MEM8(0x78) +-#define ADCH _SFR_MEM8(0x79) +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ACME 6 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-/* Reserved [0x7D] */ +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0X80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0X81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-/* Reserved [0x83] */ +- +-/* Combine TCNT1L and TCNT1H */ +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1H _SFR_MEM8(0x85) +- +-/* Combine ICR1L and ICR1H */ +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1H _SFR_MEM8(0x87) +- +-/* Combine OCR1AL and OCR1AH */ +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AH _SFR_MEM8(0x89) +- +-/* Combine OCR1BL and OCR1BH */ +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BH _SFR_MEM8(0x8B) +- +-/* Reserved [0x8C..0xAF] */ +- +-#define TCCR2A _SFR_MEM8(0xB0) +-#define CS20 0 +-#define CS21 1 +-#define CS22 2 +-#define WGM21 3 +-#define COM2A0 4 +-#define COM2A1 5 +-#define WGM20 6 +-#define FOC2A 7 +- +-/* Reserved [0xB1] */ +- +-#define TCNT2 _SFR_MEM8(0xB2) +- +-#define OCR2A _SFR_MEM8(0xB3) +- +-/* Reserved [0xB4..0xB5] */ +- +-#define ASSR _SFR_MEM8(0xB6) +-#define TCR2UB 0 +-#define OCR2UB 1 +-#define TCN2UB 2 +-#define AS2 3 +-#define EXCLK 4 +- +-/* Reserved [0xB7] */ +- +-#define USICR _SFR_MEM8(0xB8) +-#define USITC 0 +-#define USICLK 1 +-#define USICS0 2 +-#define USICS1 3 +-#define USIWM0 4 +-#define USIWM1 5 +-#define USIOIE 6 +-#define USISIE 7 +- +-#define USISR _SFR_MEM8(0xB9) +-#define USICNT0 0 +-#define USICNT1 1 +-#define USICNT2 2 +-#define USICNT3 3 +-#define USIDC 4 +-#define USIPF 5 +-#define USIOIF 6 +-#define USISIF 7 +- +-#define USIDR _SFR_MEM8(0xBA) +- +-/* Reserved [0xBB..0xBF] */ +- +-#define UCSR0A _SFR_MEM8(0xC0) +-#define MPCM0 0 +-#define U2X0 1 +-#define UPE0 2 +-#define DOR0 3 +-#define FE0 4 +-#define UDRE0 5 +-#define TXC0 6 +-#define RXC0 7 +- +-#define UCSR0B _SFR_MEM8(0XC1) +-#define TXB80 0 +-#define RXB80 1 +-#define UCSZ02 2 +-#define TXEN0 3 +-#define RXEN0 4 +-#define UDRIE0 5 +-#define TXCIE0 6 +-#define RXCIE0 7 +- +-#define UCSR0C _SFR_MEM8(0xC2) +-#define UCPOL0 0 +-#define UCSZ00 1 +-#define UCSZ01 2 +-#define USBS0 3 +-#define UPM00 4 +-#define UPM01 5 +-#define UMSEL0 6 +- +-/* Reserved [0xC3] */ +- +-/* Combine UBRR0L and UBRR0H */ +-#define UBRR0 _SFR_MEM16(0xC4) +- +-#define UBRR0L _SFR_MEM8(0xC4) +-#define UBRR0H _SFR_MEM8(0xC5) +- +-#define UDR0 _SFR_MEM8(0XC6) +- +-/* Reserved [0xC7..0xFF] */ +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* Pin Change Interrupt Request 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) +-#define SIG_PIN_CHANGE0 _VECTOR(2) +- +-/* Pin Change Interrupt Request 1 */ +-#define PCINT1_vect_num 3 +-#define PCINT1_vect _VECTOR(3) +-#define SIG_PIN_CHANGE1 _VECTOR(3) +- +-/* Timer/Counter2 Compare Match */ +-#define TIMER2_COMP_vect_num 4 +-#define TIMER2_COMP_vect _VECTOR(4) +-#define SIG_OUTPUT_COMPARE2 _VECTOR(4) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 5 +-#define TIMER2_OVF_vect _VECTOR(5) +-#define SIG_OVERFLOW2 _VECTOR(5) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 6 +-#define TIMER1_CAPT_vect _VECTOR(6) +-#define SIG_INPUT_CAPTURE1 _VECTOR(6) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 7 +-#define TIMER1_COMPA_vect _VECTOR(7) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(7) +- +-/* Timer/Counter Compare Match B */ +-#define TIMER1_COMPB_vect_num 8 +-#define TIMER1_COMPB_vect _VECTOR(8) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(8) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 9 +-#define TIMER1_OVF_vect _VECTOR(9) +-#define SIG_OVERFLOW1 _VECTOR(9) +- +-/* Timer/Counter0 Compare Match */ +-#define TIMER0_COMP_vect_num 10 +-#define TIMER0_COMP_vect _VECTOR(10) +-#define SIG_OUTPUT_COMPARE0 _VECTOR(10) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 11 +-#define TIMER0_OVF_vect _VECTOR(11) +-#define SIG_OVERFLOW0 _VECTOR(11) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 12 +-#define SPI_STC_vect _VECTOR(12) +-#define SIG_SPI _VECTOR(12) +- +-/* USART0, Rx Complete */ +-#define USART0_RX_vect_num 13 +-#define USART0_RX_vect _VECTOR(13) +-#define SIG_UART_RECV _VECTOR(13) +- +-/* USART0 Data register Empty */ +-#define USART0_UDRE_vect_num 14 +-#define USART0_UDRE_vect _VECTOR(14) +-#define SIG_UART_DATA _VECTOR(14) +- +-/* USART0, Tx Complete */ +-#define USART0_TX_vect_num 15 +-#define USART0_TX_vect _VECTOR(15) +-#define SIG_UART_TRANS _VECTOR(15) +- +-/* USI Start Condition */ +-#define USI_START_vect_num 16 +-#define USI_START_vect _VECTOR(16) +-#define SIG_USI_START _VECTOR(16) +- +-/* USI Overflow */ +-#define USI_OVERFLOW_vect_num 17 +-#define USI_OVERFLOW_vect _VECTOR(17) +-#define SIG_USI_OVERFLOW _VECTOR(17) +- +-/* Analog Comparator */ +-#define ANALOG_COMP_vect_num 18 +-#define ANALOG_COMP_vect _VECTOR(18) +-#define SIG_COMPARATOR _VECTOR(18) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 19 +-#define ADC_vect _VECTOR(19) +-#define SIG_ADC _VECTOR(19) +- +-/* EEPROM Ready */ +-#define EE_READY_vect_num 20 +-#define EE_READY_vect _VECTOR(20) +-#define SIG_EEPROM_READY _VECTOR(20) +- +-/* Store Program Memory Read */ +-#define SPM_READY_vect_num 21 +-#define SPM_READY_vect _VECTOR(21) +-#define SIG_SPM_READY _VECTOR(21) +- +-/* Vector 22 is Reserved */ +- +-#define _VECTORS_SIZE 92 +- +- +-/* Constants */ +-#define SPM_PAGESIZE 128 +-#define RAMSTART (0x100) +-#define RAMEND 0x8FF +-#define XRAMEND RAMEND +-#define E2END 0x3FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x7FFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x95 +-#define SIGNATURE_2 0x05 +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_PIN_CHANGE0 +-#pragma GCC poison SIG_PIN_CHANGE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE2 +-#pragma GCC poison SIG_OVERFLOW2 +-#pragma GCC poison SIG_INPUT_CAPTURE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OUTPUT_COMPARE0 +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_SPI +-#pragma GCC poison SIG_UART_RECV +-#pragma GCC poison SIG_UART_DATA +-#pragma GCC poison SIG_UART_TRANS +-#pragma GCC poison SIG_USI_START +-#pragma GCC poison SIG_USI_OVERFLOW +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_ADC +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_SPM_READY +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +- +-#endif /* _AVR_IOM325_H_ */ ++/* Copyright (c) 2004, 2005, 2006, 2007 Eric B. Weddington ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom325.h 2234 2011-03-16 04:32:21Z arcanum $ */ ++ ++/* avr/iom325.h - definitions for ATmega325 and ATmega325P. */ ++ ++#ifndef _AVR_IOM325_H_ ++#define _AVR_IOM325_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom325.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE7 7 ++#define DDE6 6 ++#define DDE5 5 ++#define DDE4 4 ++#define DDE3 3 ++#define DDE2 2 ++#define DDE1 1 ++#define DDE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PE7 7 ++#define PE6 6 ++#define PE5 5 ++#define PE4 4 ++#define PE3 3 ++#define PE2 2 ++#define PE1 1 ++#define PE0 0 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDF7 7 ++#define DDF6 6 ++#define DDF5 5 ++#define DDF4 4 ++#define DDF3 3 ++#define DDF2 2 ++#define DDF1 1 ++#define DDF0 0 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PF7 7 ++#define PF6 6 ++#define PF5 5 ++#define PF4 4 ++#define PF3 3 ++#define PF2 2 ++#define PF1 1 ++#define PF0 0 ++ ++#define PING _SFR_IO8(0x12) ++#define PING5 5 ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++#define DDRG _SFR_IO8(0x13) ++#define DDG4 4 ++#define DDG3 3 ++#define DDG2 2 ++#define DDG1 1 ++#define DDG0 0 ++ ++#define PORTG _SFR_IO8(0x14) ++#define PG4 4 ++#define PG3 3 ++#define PG2 2 ++#define PG1 1 ++#define PG0 0 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++ ++/* Reserved [0x18..0x1B] */ ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define PCIF0 4 ++#define PCIF1 5 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define PCIE0 4 ++#define PCIE1 5 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++ ++#define EEDR _SFR_IO8(0X20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0X22) ++ ++/* 6-char sequence denoting where to find the EEPROM registers in memory space. ++ Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM ++ subroutines. ++ First two letters: EECR address. ++ Second two letters: EEDR address. ++ Last two letters: EEAR address. */ ++#define __EEPROM_REG_LOCATIONS__ 1F2021 ++ ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR10 0 ++#define PSR2 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM01 3 ++#define COM0A0 4 ++#define COM0A1 5 ++#define WGM00 6 ++#define FOC0A 7 ++ ++/* Reserved [0x25] */ ++ ++#define TCNT0 _SFR_IO8(0X26) ++ ++#define OCR0A _SFR_IO8(0X27) ++ ++/* Reserved [0x28..0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0X2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCDR7 7 ++#define IDRD 7 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define JTRF 4 ++ ++#define MCUCR _SFR_IO8(0X35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#if defined(__AVR_ATmega325P__) ++#define BODSE 5 ++#define BODS 6 ++#endif ++#define JTD 7 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++/* SREG [0x3F] */ ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++ ++/* Reserved [0x67..0x68] */ ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++/* Reserved [0x6D] */ ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++ ++/* Reserved [0x71..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0X80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0X81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM21 3 ++#define COM2A0 4 ++#define COM2A1 5 ++#define WGM20 6 ++#define FOC2A 7 ++ ++/* Reserved [0xB1] */ ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++/* Reserved [0xB4..0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2UB 0 ++#define OCR2UB 1 ++#define TCN2UB 2 ++#define AS2 3 ++#define EXCLK 4 ++ ++/* Reserved [0xB7] */ ++ ++#define USICR _SFR_MEM8(0xB8) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_MEM8(0xB9) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_MEM8(0xBA) ++ ++/* Reserved [0xBB..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0XC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL0 6 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0XC6) ++ ++/* Reserved [0xC7..0xFF] */ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) ++#define SIG_PIN_CHANGE0 _VECTOR(2) ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect_num 3 ++#define PCINT1_vect _VECTOR(3) ++#define SIG_PIN_CHANGE1 _VECTOR(3) ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect_num 4 ++#define TIMER2_COMP_vect _VECTOR(4) ++#define SIG_OUTPUT_COMPARE2 _VECTOR(4) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 5 ++#define TIMER2_OVF_vect _VECTOR(5) ++#define SIG_OVERFLOW2 _VECTOR(5) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 6 ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define SIG_INPUT_CAPTURE1 _VECTOR(6) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 7 ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(7) ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect_num 8 ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(8) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 9 ++#define TIMER1_OVF_vect _VECTOR(9) ++#define SIG_OVERFLOW1 _VECTOR(9) ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect_num 10 ++#define TIMER0_COMP_vect _VECTOR(10) ++#define SIG_OUTPUT_COMPARE0 _VECTOR(10) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 11 ++#define TIMER0_OVF_vect _VECTOR(11) ++#define SIG_OVERFLOW0 _VECTOR(11) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 12 ++#define SPI_STC_vect _VECTOR(12) ++#define SIG_SPI _VECTOR(12) ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect_num 13 ++#define USART0_RX_vect _VECTOR(13) ++#define SIG_UART_RECV _VECTOR(13) ++ ++/* USART0 Data register Empty */ ++#define USART0_UDRE_vect_num 14 ++#define USART0_UDRE_vect _VECTOR(14) ++#define SIG_UART_DATA _VECTOR(14) ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect_num 15 ++#define USART0_TX_vect _VECTOR(15) ++#define SIG_UART_TRANS _VECTOR(15) ++ ++/* USI Start Condition */ ++#define USI_START_vect_num 16 ++#define USI_START_vect _VECTOR(16) ++#define SIG_USI_START _VECTOR(16) ++ ++/* USI Overflow */ ++#define USI_OVERFLOW_vect_num 17 ++#define USI_OVERFLOW_vect _VECTOR(17) ++#define SIG_USI_OVERFLOW _VECTOR(17) ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect_num 18 ++#define ANALOG_COMP_vect _VECTOR(18) ++#define SIG_COMPARATOR _VECTOR(18) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 19 ++#define ADC_vect _VECTOR(19) ++#define SIG_ADC _VECTOR(19) ++ ++/* EEPROM Ready */ ++#define EE_READY_vect_num 20 ++#define EE_READY_vect _VECTOR(20) ++#define SIG_EEPROM_READY _VECTOR(20) ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect_num 21 ++#define SPM_READY_vect _VECTOR(21) ++#define SIG_SPM_READY _VECTOR(21) ++ ++/* Vector 22 is Reserved */ ++ ++#define _VECTORS_SIZE 92 ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE 128 ++#define RAMSTART (0x100) ++#define RAMEND 0x8FF ++#define XRAMEND RAMEND ++#define E2END 0x3FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x7FFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x05 ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_PIN_CHANGE0 ++#pragma GCC poison SIG_PIN_CHANGE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE2 ++#pragma GCC poison SIG_OVERFLOW2 ++#pragma GCC poison SIG_INPUT_CAPTURE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OUTPUT_COMPARE0 ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_SPI ++#pragma GCC poison SIG_UART_RECV ++#pragma GCC poison SIG_UART_DATA ++#pragma GCC poison SIG_UART_TRANS ++#pragma GCC poison SIG_USI_START ++#pragma GCC poison SIG_USI_OVERFLOW ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_ADC ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_SPM_READY ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++ ++#endif /* _AVR_IOM325_H_ */ +diff --git a/include/avr/iom3250.h b/include/avr/iom3250.h +index f640f8e..69c9ca8 100644 +--- a/include/avr/iom3250.h ++++ b/include/avr/iom3250.h +@@ -1,971 +1,971 @@ +-/* Copyright (c) 2004, 2005, 2006, 2007 Eric B. Weddington +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom3250.h 2234 2011-03-16 04:32:21Z arcanum $ */ +- +-/* avr/iom3250.h - definitions for ATmega3250 and ATmega3250P. */ +- +-#ifndef _AVR_IOM3250_H_ +-#define _AVR_IOM3250_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom3250.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* Registers and associated bit numbers */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-#define PORTA _SFR_IO8(0x02) +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-#define PINB _SFR_IO8(0x03) +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-#define PORTB _SFR_IO8(0x05) +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-#define PORTC _SFR_IO8(0x08) +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-#define PINE _SFR_IO8(0x0C) +-#define PINE7 7 +-#define PINE6 6 +-#define PINE5 5 +-#define PINE4 4 +-#define PINE3 3 +-#define PINE2 2 +-#define PINE1 1 +-#define PINE0 0 +- +-#define DDRE _SFR_IO8(0x0D) +-#define DDE7 7 +-#define DDE6 6 +-#define DDE5 5 +-#define DDE4 4 +-#define DDE3 3 +-#define DDE2 2 +-#define DDE1 1 +-#define DDE0 0 +- +-#define PORTE _SFR_IO8(0x0E) +-#define PE7 7 +-#define PE6 6 +-#define PE5 5 +-#define PE4 4 +-#define PE3 3 +-#define PE2 2 +-#define PE1 1 +-#define PE0 0 +- +-#define PINF _SFR_IO8(0x0F) +-#define PINF7 7 +-#define PINF6 6 +-#define PINF5 5 +-#define PINF4 4 +-#define PINF3 3 +-#define PINF2 2 +-#define PINF1 1 +-#define PINF0 0 +- +-#define DDRF _SFR_IO8(0x10) +-#define DDF7 7 +-#define DDF6 6 +-#define DDF5 5 +-#define DDF4 4 +-#define DDF3 3 +-#define DDF2 2 +-#define DDF1 1 +-#define DDF0 0 +- +-#define PORTF _SFR_IO8(0x11) +-#define PF7 7 +-#define PF6 6 +-#define PF5 5 +-#define PF4 4 +-#define PF3 3 +-#define PF2 2 +-#define PF1 1 +-#define PF0 0 +- +-#define PING _SFR_IO8(0x12) +-#define PING5 5 +-#define PING4 4 +-#define PING3 3 +-#define PING2 2 +-#define PING1 1 +-#define PING0 0 +- +-#define DDRG _SFR_IO8(0x13) +-#define DDG4 4 +-#define DDG3 3 +-#define DDG2 2 +-#define DDG1 1 +-#define DDG0 0 +- +-#define PORTG _SFR_IO8(0x14) +-#define PG4 4 +-#define PG3 3 +-#define PG2 2 +-#define PG1 1 +-#define PG0 0 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define TIFR2 _SFR_IO8(0x17) +-#define TOV2 0 +-#define OCF2A 1 +- +-/* Reserved [0x18..0x1B] */ +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define PCIF0 4 +-#define PCIF1 5 +-#define PCIF2 6 +-#define PCIF3 7 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define PCIE0 4 +-#define PCIE1 5 +-#define PCIE2 6 +-#define PCIE3 7 +- +-#define GPIOR0 _SFR_IO8(0x1E) +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEWE 1 +-#define EEMWE 2 +-#define EERIE 3 +- +-#define EEDR _SFR_IO8(0X20) +- +-/* Combine EEARL and EEARH */ +-#define EEAR _SFR_IO16(0x21) +-#define EEARL _SFR_IO8(0x21) +-#define EEARH _SFR_IO8(0X22) +- +-/* 6-char sequence denoting where to find the EEPROM registers in memory space. +- Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM +- subroutines. +- First two letters: EECR address. +- Second two letters: EEDR address. +- Last two letters: EEAR address. */ +-#define __EEPROM_REG_LOCATIONS__ 1F2021 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSR10 0 +-#define PSR2 1 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM01 3 +-#define COM0A0 4 +-#define COM0A1 5 +-#define WGM00 6 +-#define FOC0A 7 +- +-/* Reserved [0x25] */ +- +-#define TCNT0 _SFR_IO8(0X26) +- +-#define OCR0A _SFR_IO8(0X27) +- +-/* Reserved [0x28..0x29] */ +- +-#define GPIOR1 _SFR_IO8(0x2A) +- +-#define GPIOR2 _SFR_IO8(0x2B) +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0X2E) +- +-/* Reserved [0x2F] */ +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define OCDR _SFR_IO8(0x31) +-#define OCDR0 0 +-#define OCDR1 1 +-#define OCDR2 2 +-#define OCDR3 3 +-#define OCDR4 4 +-#define OCDR5 5 +-#define OCDR6 6 +-#define OCDR7 7 +-#define IDRD 7 +- +-/* Reserved [0x32] */ +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +-#define JTRF 4 +- +-#define MCUCR _SFR_IO8(0X35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#if defined(__AVR_ATmega3250P__) +-#define BODSE 5 +-#define BODS 6 +-#endif +-#define JTD 7 +- +-/* Reserved [0x36] */ +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define RWWSB 6 +-#define SPMIE 7 +- +-/* Reserved [0x38..0x3C] */ +- +-/* SP [0x3D..0x3E] */ +-/* SREG [0x3F] */ +- +-#define WDTCR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-/* Reserved [0x62..0x63] */ +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM1 3 +- +-/* Reserved [0x65] */ +- +-#define OSCCAL _SFR_MEM8(0x66) +- +-/* Reserved [0x67..0x68] */ +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +- +-/* Reserved [0x6A] */ +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-#define PCMSK2 _SFR_MEM8(0x6D) +-#define PCINT16 0 +-#define PCINT17 1 +-#define PCINT18 2 +-#define PCINT19 3 +-#define PCINT20 4 +-#define PCINT21 5 +-#define PCINT22 6 +-#define PCINT23 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define TIMSK2 _SFR_MEM8(0x70) +-#define TOIE2 0 +-#define OCIE2A 1 +- +-/* Reserved [0x71..0x72] */ +- +-#define PCMSK3 _SFR_MEM8(0x73) +-#define PCINT24 0 +-#define PCINT25 1 +-#define PCINT26 2 +-#define PCINT27 3 +-#define PCINT28 4 +-#define PCINT29 5 +-#define PCINT30 6 +- +-/* Reserved [0x74..0x77] */ +- +-/* Combine ADCL and ADCH */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +-#define ADCL _SFR_MEM8(0x78) +-#define ADCH _SFR_MEM8(0x79) +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ACME 6 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-/* Reserved [0x7D] */ +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0X80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0X81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-/* Reserved [0x83] */ +- +-/* Combine TCNT1L and TCNT1H */ +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1H _SFR_MEM8(0x85) +- +-/* Combine ICR1L and ICR1H */ +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1H _SFR_MEM8(0x87) +- +-/* Combine OCR1AL and OCR1AH */ +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AH _SFR_MEM8(0x89) +- +-/* Combine OCR1BL and OCR1BH */ +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BH _SFR_MEM8(0x8B) +- +-/* Reserved [0x8C..0xAF] */ +- +-#define TCCR2A _SFR_MEM8(0xB0) +-#define CS20 0 +-#define CS21 1 +-#define CS22 2 +-#define WGM21 3 +-#define COM2A0 4 +-#define COM2A1 5 +-#define WGM20 6 +-#define FOC2A 7 +- +-/* Reserved [0xB1] */ +- +-#define TCNT2 _SFR_MEM8(0xB2) +- +-#define OCR2A _SFR_MEM8(0xB3) +- +-/* Reserved [0xB4..0xB5] */ +- +-#define ASSR _SFR_MEM8(0xB6) +-#define TCR2UB 0 +-#define OCR2UB 1 +-#define TCN2UB 2 +-#define AS2 3 +-#define EXCLK 4 +- +-/* Reserved [0xB7] */ +- +-#define USICR _SFR_MEM8(0xB8) +-#define USITC 0 +-#define USICLK 1 +-#define USICS0 2 +-#define USICS1 3 +-#define USIWM0 4 +-#define USIWM1 5 +-#define USIOIE 6 +-#define USISIE 7 +- +-#define USISR _SFR_MEM8(0xB9) +-#define USICNT0 0 +-#define USICNT1 1 +-#define USICNT2 2 +-#define USICNT3 3 +-#define USIDC 4 +-#define USIPF 5 +-#define USIOIF 6 +-#define USISIF 7 +- +-#define USIDR _SFR_MEM8(0xBA) +- +-/* Reserved [0xBB..0xBF] */ +- +-#define UCSR0A _SFR_MEM8(0xC0) +-#define MPCM0 0 +-#define U2X0 1 +-#define UPE0 2 +-#define DOR0 3 +-#define FE0 4 +-#define UDRE0 5 +-#define TXC0 6 +-#define RXC0 7 +- +-#define UCSR0B _SFR_MEM8(0XC1) +-#define TXB80 0 +-#define RXB80 1 +-#define UCSZ02 2 +-#define TXEN0 3 +-#define RXEN0 4 +-#define UDRIE0 5 +-#define TXCIE0 6 +-#define RXCIE0 7 +- +-#define UCSR0C _SFR_MEM8(0xC2) +-#define UCPOL0 0 +-#define UCSZ00 1 +-#define UCSZ01 2 +-#define USBS0 3 +-#define UPM00 4 +-#define UPM01 5 +-#define UMSEL0 6 +- +-/* Reserved [0xC3] */ +- +-/* Combine UBRR0L and UBRR0H */ +-#define UBRR0 _SFR_MEM16(0xC4) +- +-#define UBRR0L _SFR_MEM8(0xC4) +-#define UBRR0H _SFR_MEM8(0xC5) +- +-#define UDR0 _SFR_MEM8(0XC6) +- +-/* Reserved [0xC7..0xD7] */ +- +-#define PINH _SFR_MEM8(0xD8) +-#define PINH7 7 +-#define PINH6 6 +-#define PINH5 5 +-#define PINH4 4 +-#define PINH3 3 +-#define PINH2 2 +-#define PINH1 1 +-#define PINH0 0 +- +-#define DDRH _SFR_MEM8(0xD9) +-#define DDH7 7 +-#define DDH6 6 +-#define DDH5 5 +-#define DDH4 4 +-#define DDH3 3 +-#define DDH2 2 +-#define DDH1 1 +-#define DDH0 0 +- +-#define PORTH _SFR_MEM8(0xDA) +-#define PH7 7 +-#define PH6 6 +-#define PH5 5 +-#define PH4 4 +-#define PH3 3 +-#define PH2 2 +-#define PH1 1 +-#define PH0 0 +- +-#define PINJ _SFR_MEM8(0xDB) +-#define PINJ6 6 +-#define PINJ5 5 +-#define PINJ4 4 +-#define PINJ3 3 +-#define PINJ2 2 +-#define PINJ1 1 +-#define PINJ0 0 +- +-#define DDRJ _SFR_MEM8(0xDC) +-#define DDJ6 6 +-#define DDJ5 5 +-#define DDJ4 4 +-#define DDJ3 3 +-#define DDJ2 2 +-#define DDJ1 1 +-#define DDJ0 0 +- +-#define PORTJ _SFR_MEM8(0xDD) +-#define PJ6 6 +-#define PJ5 5 +-#define PJ4 4 +-#define PJ3 3 +-#define PJ2 2 +-#define PJ1 1 +-#define PJ0 0 +- +-/* Reserved [0xDE..0xFF] */ +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* Pin Change Interrupt Request 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) +-#define SIG_PIN_CHANGE0 _VECTOR(2) +- +-/* Pin Change Interrupt Request 1 */ +-#define PCINT1_vect_num 3 +-#define PCINT1_vect _VECTOR(3) +-#define SIG_PIN_CHANGE1 _VECTOR(3) +- +-/* Timer/Counter2 Compare Match */ +-#define TIMER2_COMP_vect_num 4 +-#define TIMER2_COMP_vect _VECTOR(4) +-#define SIG_OUTPUT_COMPARE2 _VECTOR(4) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 5 +-#define TIMER2_OVF_vect _VECTOR(5) +-#define SIG_OVERFLOW2 _VECTOR(5) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 6 +-#define TIMER1_CAPT_vect _VECTOR(6) +-#define SIG_INPUT_CAPTURE1 _VECTOR(6) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 7 +-#define TIMER1_COMPA_vect _VECTOR(7) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(7) +- +-/* Timer/Counter Compare Match B */ +-#define TIMER1_COMPB_vect_num 8 +-#define TIMER1_COMPB_vect _VECTOR(8) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(8) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 9 +-#define TIMER1_OVF_vect _VECTOR(9) +-#define SIG_OVERFLOW1 _VECTOR(9) +- +-/* Timer/Counter0 Compare Match */ +-#define TIMER0_COMP_vect_num 10 +-#define TIMER0_COMP_vect _VECTOR(10) +-#define SIG_OUTPUT_COMPARE0 _VECTOR(10) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 11 +-#define TIMER0_OVF_vect _VECTOR(11) +-#define SIG_OVERFLOW0 _VECTOR(11) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 12 +-#define SPI_STC_vect _VECTOR(12) +-#define SIG_SPI _VECTOR(12) +- +-/* USART, Rx Complete */ +-#define USART_RX_vect_num 13 +-#define USART_RX_vect _VECTOR(13) +-#define USART0_RX_vect _VECTOR(13) /* Alias */ +-#define SIG_UART_RECV _VECTOR(13) +- +-/* USART Data register Empty */ +-#define USART_UDRE_vect_num 14 +-#define USART_UDRE_vect _VECTOR(14) +-#define USART0_UDRE_vect _VECTOR(14) /* Alias */ +-#define SIG_UART_DATA _VECTOR(14) +- +-/* USART0, Tx Complete */ +-#define USART0_TX_vect_num 15 +-#define USART0_TX_vect _VECTOR(15) +-#define USART_TX_vect _VECTOR(15) /* Alias */ +-#define SIG_UART_TRANS _VECTOR(15) +- +-/* USI Start Condition */ +-#define USI_START_vect_num 16 +-#define USI_START_vect _VECTOR(16) +-#define SIG_USI_START _VECTOR(16) +- +-/* USI Overflow */ +-#define USI_OVERFLOW_vect_num 17 +-#define USI_OVERFLOW_vect _VECTOR(17) +-#define SIG_USI_OVERFLOW _VECTOR(17) +- +-/* Analog Comparator */ +-#define ANALOG_COMP_vect_num 18 +-#define ANALOG_COMP_vect _VECTOR(18) +-#define SIG_COMPARATOR _VECTOR(18) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 19 +-#define ADC_vect _VECTOR(19) +-#define SIG_ADC _VECTOR(19) +- +-/* EEPROM Ready */ +-#define EE_READY_vect_num 20 +-#define EE_READY_vect _VECTOR(20) +-#define SIG_EEPROM_READY _VECTOR(20) +- +-/* Store Program Memory Read */ +-#define SPM_READY_vect_num 21 +-#define SPM_READY_vect _VECTOR(21) +-#define SIG_SPM_READY _VECTOR(21) +- +-/* Pin Change Interrupt Request 2 */ +-#define PCINT2_vect_num 23 +-#define PCINT2_vect _VECTOR(23) +-#define SIG_PIN_CHANGE2 _VECTOR(23) +- +-/* Pin Change Interrupt Request 3 */ +-#define PCINT3_vect_num 24 +-#define PCINT3_vect _VECTOR(24) +-#define SIG_PIN_CHANGE3 _VECTOR(24) +- +-#define _VECTORS_SIZE 100 +- +- +-/* Constants */ +-#define SPM_PAGESIZE 128 +-#define RAMSTART (0x100) +-#define RAMEND 0x8FF +-#define XRAMEND RAMEND +-#define E2END 0x3FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x7FFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x95 +-#define SIGNATURE_2 0x06 +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_PIN_CHANGE0 +-#pragma GCC poison SIG_PIN_CHANGE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE2 +-#pragma GCC poison SIG_OVERFLOW2 +-#pragma GCC poison SIG_INPUT_CAPTURE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OUTPUT_COMPARE0 +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_SPI +-#pragma GCC poison USART0_RX_vect +-#pragma GCC poison SIG_UART_RECV +-#pragma GCC poison USART0_UDRE_vect +-#pragma GCC poison SIG_UART_DATA +-#pragma GCC poison USART_TX_vect +-#pragma GCC poison SIG_UART_TRANS +-#pragma GCC poison SIG_USI_START +-#pragma GCC poison SIG_USI_OVERFLOW +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_ADC +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_SPM_READY +-#pragma GCC poison SIG_PIN_CHANGE2 +-#pragma GCC poison SIG_PIN_CHANGE3 +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +-#endif /* _AVR_IOM3250_H_ */ ++/* Copyright (c) 2004, 2005, 2006, 2007 Eric B. Weddington ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom3250.h 2234 2011-03-16 04:32:21Z arcanum $ */ ++ ++/* avr/iom3250.h - definitions for ATmega3250 and ATmega3250P. */ ++ ++#ifndef _AVR_IOM3250_H_ ++#define _AVR_IOM3250_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom3250.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE7 7 ++#define DDE6 6 ++#define DDE5 5 ++#define DDE4 4 ++#define DDE3 3 ++#define DDE2 2 ++#define DDE1 1 ++#define DDE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PE7 7 ++#define PE6 6 ++#define PE5 5 ++#define PE4 4 ++#define PE3 3 ++#define PE2 2 ++#define PE1 1 ++#define PE0 0 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDF7 7 ++#define DDF6 6 ++#define DDF5 5 ++#define DDF4 4 ++#define DDF3 3 ++#define DDF2 2 ++#define DDF1 1 ++#define DDF0 0 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PF7 7 ++#define PF6 6 ++#define PF5 5 ++#define PF4 4 ++#define PF3 3 ++#define PF2 2 ++#define PF1 1 ++#define PF0 0 ++ ++#define PING _SFR_IO8(0x12) ++#define PING5 5 ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++#define DDRG _SFR_IO8(0x13) ++#define DDG4 4 ++#define DDG3 3 ++#define DDG2 2 ++#define DDG1 1 ++#define DDG0 0 ++ ++#define PORTG _SFR_IO8(0x14) ++#define PG4 4 ++#define PG3 3 ++#define PG2 2 ++#define PG1 1 ++#define PG0 0 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++ ++/* Reserved [0x18..0x1B] */ ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define PCIF0 4 ++#define PCIF1 5 ++#define PCIF2 6 ++#define PCIF3 7 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define PCIE0 4 ++#define PCIE1 5 ++#define PCIE2 6 ++#define PCIE3 7 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++ ++#define EEDR _SFR_IO8(0X20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0X22) ++ ++/* 6-char sequence denoting where to find the EEPROM registers in memory space. ++ Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM ++ subroutines. ++ First two letters: EECR address. ++ Second two letters: EEDR address. ++ Last two letters: EEAR address. */ ++#define __EEPROM_REG_LOCATIONS__ 1F2021 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR10 0 ++#define PSR2 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM01 3 ++#define COM0A0 4 ++#define COM0A1 5 ++#define WGM00 6 ++#define FOC0A 7 ++ ++/* Reserved [0x25] */ ++ ++#define TCNT0 _SFR_IO8(0X26) ++ ++#define OCR0A _SFR_IO8(0X27) ++ ++/* Reserved [0x28..0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0X2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCDR7 7 ++#define IDRD 7 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define JTRF 4 ++ ++#define MCUCR _SFR_IO8(0X35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#if defined(__AVR_ATmega3250P__) ++#define BODSE 5 ++#define BODS 6 ++#endif ++#define JTD 7 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++/* SREG [0x3F] */ ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++ ++/* Reserved [0x67..0x68] */ ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++ ++/* Reserved [0x71..0x72] */ ++ ++#define PCMSK3 _SFR_MEM8(0x73) ++#define PCINT24 0 ++#define PCINT25 1 ++#define PCINT26 2 ++#define PCINT27 3 ++#define PCINT28 4 ++#define PCINT29 5 ++#define PCINT30 6 ++ ++/* Reserved [0x74..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0X80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0X81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM21 3 ++#define COM2A0 4 ++#define COM2A1 5 ++#define WGM20 6 ++#define FOC2A 7 ++ ++/* Reserved [0xB1] */ ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++/* Reserved [0xB4..0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2UB 0 ++#define OCR2UB 1 ++#define TCN2UB 2 ++#define AS2 3 ++#define EXCLK 4 ++ ++/* Reserved [0xB7] */ ++ ++#define USICR _SFR_MEM8(0xB8) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_MEM8(0xB9) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_MEM8(0xBA) ++ ++/* Reserved [0xBB..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0XC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL0 6 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0XC6) ++ ++/* Reserved [0xC7..0xD7] */ ++ ++#define PINH _SFR_MEM8(0xD8) ++#define PINH7 7 ++#define PINH6 6 ++#define PINH5 5 ++#define PINH4 4 ++#define PINH3 3 ++#define PINH2 2 ++#define PINH1 1 ++#define PINH0 0 ++ ++#define DDRH _SFR_MEM8(0xD9) ++#define DDH7 7 ++#define DDH6 6 ++#define DDH5 5 ++#define DDH4 4 ++#define DDH3 3 ++#define DDH2 2 ++#define DDH1 1 ++#define DDH0 0 ++ ++#define PORTH _SFR_MEM8(0xDA) ++#define PH7 7 ++#define PH6 6 ++#define PH5 5 ++#define PH4 4 ++#define PH3 3 ++#define PH2 2 ++#define PH1 1 ++#define PH0 0 ++ ++#define PINJ _SFR_MEM8(0xDB) ++#define PINJ6 6 ++#define PINJ5 5 ++#define PINJ4 4 ++#define PINJ3 3 ++#define PINJ2 2 ++#define PINJ1 1 ++#define PINJ0 0 ++ ++#define DDRJ _SFR_MEM8(0xDC) ++#define DDJ6 6 ++#define DDJ5 5 ++#define DDJ4 4 ++#define DDJ3 3 ++#define DDJ2 2 ++#define DDJ1 1 ++#define DDJ0 0 ++ ++#define PORTJ _SFR_MEM8(0xDD) ++#define PJ6 6 ++#define PJ5 5 ++#define PJ4 4 ++#define PJ3 3 ++#define PJ2 2 ++#define PJ1 1 ++#define PJ0 0 ++ ++/* Reserved [0xDE..0xFF] */ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) ++#define SIG_PIN_CHANGE0 _VECTOR(2) ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect_num 3 ++#define PCINT1_vect _VECTOR(3) ++#define SIG_PIN_CHANGE1 _VECTOR(3) ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect_num 4 ++#define TIMER2_COMP_vect _VECTOR(4) ++#define SIG_OUTPUT_COMPARE2 _VECTOR(4) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 5 ++#define TIMER2_OVF_vect _VECTOR(5) ++#define SIG_OVERFLOW2 _VECTOR(5) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 6 ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define SIG_INPUT_CAPTURE1 _VECTOR(6) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 7 ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(7) ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect_num 8 ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(8) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 9 ++#define TIMER1_OVF_vect _VECTOR(9) ++#define SIG_OVERFLOW1 _VECTOR(9) ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect_num 10 ++#define TIMER0_COMP_vect _VECTOR(10) ++#define SIG_OUTPUT_COMPARE0 _VECTOR(10) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 11 ++#define TIMER0_OVF_vect _VECTOR(11) ++#define SIG_OVERFLOW0 _VECTOR(11) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 12 ++#define SPI_STC_vect _VECTOR(12) ++#define SIG_SPI _VECTOR(12) ++ ++/* USART, Rx Complete */ ++#define USART_RX_vect_num 13 ++#define USART_RX_vect _VECTOR(13) ++#define USART0_RX_vect _VECTOR(13) /* Alias */ ++#define SIG_UART_RECV _VECTOR(13) ++ ++/* USART Data register Empty */ ++#define USART_UDRE_vect_num 14 ++#define USART_UDRE_vect _VECTOR(14) ++#define USART0_UDRE_vect _VECTOR(14) /* Alias */ ++#define SIG_UART_DATA _VECTOR(14) ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect_num 15 ++#define USART0_TX_vect _VECTOR(15) ++#define USART_TX_vect _VECTOR(15) /* Alias */ ++#define SIG_UART_TRANS _VECTOR(15) ++ ++/* USI Start Condition */ ++#define USI_START_vect_num 16 ++#define USI_START_vect _VECTOR(16) ++#define SIG_USI_START _VECTOR(16) ++ ++/* USI Overflow */ ++#define USI_OVERFLOW_vect_num 17 ++#define USI_OVERFLOW_vect _VECTOR(17) ++#define SIG_USI_OVERFLOW _VECTOR(17) ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect_num 18 ++#define ANALOG_COMP_vect _VECTOR(18) ++#define SIG_COMPARATOR _VECTOR(18) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 19 ++#define ADC_vect _VECTOR(19) ++#define SIG_ADC _VECTOR(19) ++ ++/* EEPROM Ready */ ++#define EE_READY_vect_num 20 ++#define EE_READY_vect _VECTOR(20) ++#define SIG_EEPROM_READY _VECTOR(20) ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect_num 21 ++#define SPM_READY_vect _VECTOR(21) ++#define SIG_SPM_READY _VECTOR(21) ++ ++/* Pin Change Interrupt Request 2 */ ++#define PCINT2_vect_num 23 ++#define PCINT2_vect _VECTOR(23) ++#define SIG_PIN_CHANGE2 _VECTOR(23) ++ ++/* Pin Change Interrupt Request 3 */ ++#define PCINT3_vect_num 24 ++#define PCINT3_vect _VECTOR(24) ++#define SIG_PIN_CHANGE3 _VECTOR(24) ++ ++#define _VECTORS_SIZE 100 ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE 128 ++#define RAMSTART (0x100) ++#define RAMEND 0x8FF ++#define XRAMEND RAMEND ++#define E2END 0x3FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x7FFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x06 ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_PIN_CHANGE0 ++#pragma GCC poison SIG_PIN_CHANGE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE2 ++#pragma GCC poison SIG_OVERFLOW2 ++#pragma GCC poison SIG_INPUT_CAPTURE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OUTPUT_COMPARE0 ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_SPI ++#pragma GCC poison USART0_RX_vect ++#pragma GCC poison SIG_UART_RECV ++#pragma GCC poison USART0_UDRE_vect ++#pragma GCC poison SIG_UART_DATA ++#pragma GCC poison USART_TX_vect ++#pragma GCC poison SIG_UART_TRANS ++#pragma GCC poison SIG_USI_START ++#pragma GCC poison SIG_USI_OVERFLOW ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_ADC ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_SPM_READY ++#pragma GCC poison SIG_PIN_CHANGE2 ++#pragma GCC poison SIG_PIN_CHANGE3 ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++#endif /* _AVR_IOM3250_H_ */ +diff --git a/include/avr/iom3250a.h b/include/avr/iom3250a.h +new file mode 100644 +index 0000000..6cbc110 +--- /dev/null ++++ b/include/avr/iom3250a.h +@@ -0,0 +1,34 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2011 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++#include "iom3250.h" +diff --git a/include/avr/iom3250p.h b/include/avr/iom3250p.h +new file mode 100644 +index 0000000..6cbc110 +--- /dev/null ++++ b/include/avr/iom3250p.h +@@ -0,0 +1,34 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2011 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++#include "iom3250.h" +diff --git a/include/avr/iom3250pa.h b/include/avr/iom3250pa.h +new file mode 100644 +index 0000000..a4d8ef9 +--- /dev/null ++++ b/include/avr/iom3250pa.h +@@ -0,0 +1,884 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATMEGA3250PA_H_INCLUDED ++#define _AVR_ATMEGA3250PA_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom3250pa.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDRA7 7 ++#define DDRA6 6 ++#define DDRA5 5 ++#define DDRA4 4 ++#define DDRA3 3 ++#define DDRA2 2 ++#define DDRA1 1 ++#define DDRA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDRC7 7 ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC7 7 ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDRE7 7 ++#define DDRE6 6 ++#define DDRE5 5 ++#define DDRE4 4 ++#define DDRE3 3 ++#define DDRE2 2 ++#define DDRE1 1 ++#define DDRE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE7 7 ++#define PORTE6 6 ++#define PORTE5 5 ++#define PORTE4 4 ++#define PORTE3 3 ++#define PORTE2 2 ++#define PORTE1 1 ++#define PORTE0 0 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDRF7 7 ++#define DDRF6 6 ++#define DDRF5 5 ++#define DDRF4 4 ++#define DDRF3 3 ++#define DDRF2 2 ++#define DDRF1 1 ++#define DDRF0 0 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PORTF7 7 ++#define PORTF6 6 ++#define PORTF5 5 ++#define PORTF4 4 ++#define PORTF3 3 ++#define PORTF2 2 ++#define PORTF1 1 ++#define PORTF0 0 ++ ++#define PING _SFR_IO8(0x12) ++#define PING5 5 ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++#define DDRG _SFR_IO8(0x13) ++#define DDRG4 4 ++#define DDRG3 3 ++#define DDRG2 2 ++#define DDRG1 1 ++#define DDRG0 0 ++ ++#define PORTG _SFR_IO8(0x14) ++#define PORTG4 4 ++#define PORTG3 3 ++#define PORTG2 2 ++#define PORTG1 1 ++#define PORTG0 0 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++ ++/* Reserved [0x18..0x1B] */ ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define PCIF0 4 ++#define PCIF1 5 ++#define PCIF2 6 ++#define PCIF3 7 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define PCIE0 4 ++#define PCIE1 5 ++#define PCIE2 6 ++#define PCIE3 7 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR310 0 ++#define TSM 7 ++#define PSR2 1 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM01 3 ++#define COM0A0 4 ++#define COM0A1 5 ++#define WGM00 6 ++#define FOC0A 7 ++ ++/* Reserved [0x25] */ ++ ++#define TCNT0 _SFR_IO8(0x26) ++ ++#define OCR0A _SFR_IO8(0x27) ++ ++/* Reserved [0x28..0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR7 7 ++#define OCDR6 6 ++#define OCDR5 5 ++#define OCDR4 4 ++#define OCDR3 3 ++#define OCDR2 2 ++#define OCDR1 1 ++#define OCDR0 0 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define JTRF 4 ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define JTD 7 ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRLCD 4 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++/* Reserved [0x67..0x68] */ ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++ ++/* Reserved [0x71..0x72] */ ++ ++#define PCMSK3 _SFR_MEM8(0x73) ++ ++/* Reserved [0x74..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ACME 6 ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM21 3 ++#define COM2A0 4 ++#define COM2A1 5 ++#define WGM20 6 ++#define FOC2A 7 ++ ++/* Reserved [0xB1] */ ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++/* Reserved [0xB4..0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2UB 0 ++#define OCR2UB 1 ++#define TCN2UB 2 ++#define AS2 3 ++#define EXCLK 4 ++ ++/* Reserved [0xB7] */ ++ ++#define USICR _SFR_MEM8(0xB8) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_MEM8(0xB9) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_MEM8(0xBA) ++ ++/* Reserved [0xBB..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL0 6 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0xC6) ++ ++/* Reserved [0xC7..0xD7] */ ++ ++#define PINH _SFR_MEM8(0xD8) ++#define PINH7 7 ++#define PINH6 6 ++#define PINH5 5 ++#define PINH4 4 ++#define PINH3 3 ++#define PINH2 2 ++#define PINH1 1 ++#define PINH0 0 ++ ++#define DDRH _SFR_MEM8(0xD9) ++#define DDRH7 7 ++#define DDRH6 6 ++#define DDRH5 5 ++#define DDRH4 4 ++#define DDRH3 3 ++#define DDRH2 2 ++#define DDRH1 1 ++#define DDRH0 0 ++ ++#define PORTH _SFR_MEM8(0xDA) ++#define PORTH7 7 ++#define PORTH6 6 ++#define PORTH5 5 ++#define PORTH4 4 ++#define PORTH3 3 ++#define PORTH2 2 ++#define PORTH1 1 ++#define PORTH0 0 ++ ++#define PINJ _SFR_MEM8(0xDB) ++#define PINJ6 6 ++#define PINJ5 5 ++#define PINJ4 4 ++#define PINJ3 3 ++#define PINJ2 2 ++#define PINJ1 1 ++#define PINJ0 0 ++ ++#define DDRJ _SFR_MEM8(0xDC) ++#define DDRJ6 6 ++#define DDRJ5 5 ++#define DDRJ4 4 ++#define DDRJ3 3 ++#define DDRJ2 2 ++#define DDRJ1 1 ++#define DDRJ0 0 ++ ++#define PORTJ _SFR_MEM8(0xDD) ++#define PORTJ6 6 ++#define PORTJ5 5 ++#define PORTJ4 4 ++#define PORTJ3 3 ++#define PORTJ2 2 ++#define PORTJ1 1 ++#define PORTJ0 0 ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(2) ++#define PCINT0_vect_num 2 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(3) ++#define PCINT1_vect_num 3 ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect _VECTOR(4) ++#define TIMER2_COMP_vect_num 4 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(5) ++#define TIMER2_OVF_vect_num 5 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define TIMER1_CAPT_vect_num 6 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define TIMER1_COMPA_vect_num 7 ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define TIMER1_COMPB_vect_num 8 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(9) ++#define TIMER1_OVF_vect_num 9 ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect _VECTOR(10) ++#define TIMER0_COMP_vect_num 10 ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(11) ++#define TIMER0_OVF_vect_num 11 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(12) ++#define SPI_STC_vect_num 12 ++ ++/* USART, Rx Complete */ ++#define USART_RX_vect _VECTOR(13) ++#define USART_RX_vect_num 13 ++ ++/* USART Data register Empty */ ++#define USART_UDRE_vect _VECTOR(14) ++#define USART_UDRE_vect_num 14 ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect _VECTOR(15) ++#define USART0_TX_vect_num 15 ++ ++/* USI Start Condition */ ++#define USI_START_vect _VECTOR(16) ++#define USI_START_vect_num 16 ++ ++/* USI Overflow */ ++#define USI_OVERFLOW_vect _VECTOR(17) ++#define USI_OVERFLOW_vect_num 17 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(18) ++#define ANALOG_COMP_vect_num 18 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(19) ++#define ADC_vect_num 19 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(20) ++#define EE_READY_vect_num 20 ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect _VECTOR(21) ++#define SPM_READY_vect_num 21 ++ ++/* RESERVED */ ++#define NOT_USED_vect _VECTOR(22) ++#define NOT_USED_vect_num 22 ++ ++/* Pin Change Interrupt Request 2 */ ++#define PCINT2_vect _VECTOR(23) ++#define PCINT2_vect_num 23 ++ ++/* Pin Change Interrupt Request 3 */ ++#define PCINT3_vect _VECTOR(24) ++#define PCINT3_vect_num 24 ++ ++#define _VECTORS_SIZE 100 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 128 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x7FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 2048 ++#define RAMEND 0x08FF ++#define E2START 0 ++#define E2SIZE 1024 ++#define E2PAGESIZE 4 ++#define E2END 0x03FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x0E ++ ++ ++#endif /* #ifdef _AVR_ATMEGA3250PA_H_INCLUDED */ ++ +diff --git a/include/avr/iom325a.h b/include/avr/iom325a.h +new file mode 100644 +index 0000000..7c7d788 +--- /dev/null ++++ b/include/avr/iom325a.h +@@ -0,0 +1,34 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2011 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++#include "iom325.h" +diff --git a/include/avr/iom325p.h b/include/avr/iom325p.h +new file mode 100644 +index 0000000..7c7d788 +--- /dev/null ++++ b/include/avr/iom325p.h +@@ -0,0 +1,34 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2011 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++#include "iom325.h" +diff --git a/include/avr/iom325pa.h b/include/avr/iom325pa.h +new file mode 100644 +index 0000000..6a1959b +--- /dev/null ++++ b/include/avr/iom325pa.h +@@ -0,0 +1,809 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATMEGA325PA_H_INCLUDED ++#define _AVR_ATMEGA325PA_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom325pa.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDRA7 7 ++#define DDRA6 6 ++#define DDRA5 5 ++#define DDRA4 4 ++#define DDRA3 3 ++#define DDRA2 2 ++#define DDRA1 1 ++#define DDRA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDRC7 7 ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC7 7 ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDRE7 7 ++#define DDRE6 6 ++#define DDRE5 5 ++#define DDRE4 4 ++#define DDRE3 3 ++#define DDRE2 2 ++#define DDRE1 1 ++#define DDRE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE7 7 ++#define PORTE6 6 ++#define PORTE5 5 ++#define PORTE4 4 ++#define PORTE3 3 ++#define PORTE2 2 ++#define PORTE1 1 ++#define PORTE0 0 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDRF7 7 ++#define DDRF6 6 ++#define DDRF5 5 ++#define DDRF4 4 ++#define DDRF3 3 ++#define DDRF2 2 ++#define DDRF1 1 ++#define DDRF0 0 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PORTF7 7 ++#define PORTF6 6 ++#define PORTF5 5 ++#define PORTF4 4 ++#define PORTF3 3 ++#define PORTF2 2 ++#define PORTF1 1 ++#define PORTF0 0 ++ ++#define PING _SFR_IO8(0x12) ++#define PING5 5 ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++#define DDRG _SFR_IO8(0x13) ++#define DDRG4 4 ++#define DDRG3 3 ++#define DDRG2 2 ++#define DDRG1 1 ++#define DDRG0 0 ++ ++#define PORTG _SFR_IO8(0x14) ++#define PORTG4 4 ++#define PORTG3 3 ++#define PORTG2 2 ++#define PORTG1 1 ++#define PORTG0 0 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++ ++/* Reserved [0x18..0x1B] */ ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define PCIF0 4 ++#define PCIF1 5 ++#define PCIF2 6 ++#define PCIF3 7 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define PCIE0 4 ++#define PCIE1 5 ++#define PCIE2 6 ++#define PCIE3 7 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR310 0 ++#define TSM 7 ++#define PSR2 1 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM01 3 ++#define COM0A0 4 ++#define COM0A1 5 ++#define WGM00 6 ++#define FOC0A 7 ++ ++/* Reserved [0x25] */ ++ ++#define TCNT0 _SFR_IO8(0x26) ++ ++#define OCR0A _SFR_IO8(0x27) ++ ++/* Reserved [0x28..0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR7 7 ++#define OCDR6 6 ++#define OCDR5 5 ++#define OCDR4 4 ++#define OCDR3 3 ++#define OCDR2 2 ++#define OCDR1 1 ++#define OCDR0 0 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define JTRF 4 ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define JTD 7 ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRLCD 4 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++/* Reserved [0x67..0x68] */ ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++ ++/* Reserved [0x6D] */ ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++ ++/* Reserved [0x71..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM21 3 ++#define COM2A0 4 ++#define COM2A1 5 ++#define WGM20 6 ++#define FOC2A 7 ++ ++/* Reserved [0xB1] */ ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++/* Reserved [0xB4..0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2UB 0 ++#define OCR2UB 1 ++#define TCN2UB 2 ++#define AS2 3 ++#define EXCLK 4 ++ ++/* Reserved [0xB7] */ ++ ++#define USICR _SFR_MEM8(0xB8) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_MEM8(0xB9) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_MEM8(0xBA) ++ ++/* Reserved [0xBB..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL0 6 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0xC6) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(2) ++#define PCINT0_vect_num 2 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(3) ++#define PCINT1_vect_num 3 ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect _VECTOR(4) ++#define TIMER2_COMP_vect_num 4 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(5) ++#define TIMER2_OVF_vect_num 5 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define TIMER1_CAPT_vect_num 6 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define TIMER1_COMPA_vect_num 7 ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define TIMER1_COMPB_vect_num 8 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(9) ++#define TIMER1_OVF_vect_num 9 ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect _VECTOR(10) ++#define TIMER0_COMP_vect_num 10 ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(11) ++#define TIMER0_OVF_vect_num 11 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(12) ++#define SPI_STC_vect_num 12 ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect _VECTOR(13) ++#define USART0_RX_vect_num 13 ++ ++/* USART0 Data register Empty */ ++#define USART0_UDRE_vect _VECTOR(14) ++#define USART0_UDRE_vect_num 14 ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect _VECTOR(15) ++#define USART0_TX_vect_num 15 ++ ++/* USI Start Condition */ ++#define USI_START_vect _VECTOR(16) ++#define USI_START_vect_num 16 ++ ++/* USI Overflow */ ++#define USI_OVERFLOW_vect _VECTOR(17) ++#define USI_OVERFLOW_vect_num 17 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(18) ++#define ANALOG_COMP_vect_num 18 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(19) ++#define ADC_vect_num 19 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(20) ++#define EE_READY_vect_num 20 ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect _VECTOR(21) ++#define SPM_READY_vect_num 21 ++ ++#define _VECTORS_SIZE 88 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 128 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x7FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 2048 ++#define RAMEND 0x08FF ++#define E2START 0 ++#define E2SIZE 1024 ++#define E2PAGESIZE 4 ++#define E2END 0x03FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x0D ++ ++ ++#endif /* #ifdef _AVR_ATMEGA325PA_H_INCLUDED */ ++ +diff --git a/include/avr/iom328.h b/include/avr/iom328.h +new file mode 100644 +index 0000000..61cf2ce +--- /dev/null ++++ b/include/avr/iom328.h +@@ -0,0 +1,34 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2011 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++#include "iom328p.h" +diff --git a/include/avr/iom328p.h b/include/avr/iom328p.h +index 2c9c9fe..e73efa3 100644 +--- a/include/avr/iom328p.h ++++ b/include/avr/iom328p.h +@@ -1,926 +1,933 @@ +-/* Copyright (c) 2007 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. +-*/ +- +-/* $Id: iom328p.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* avr/iom328p.h - definitions for ATmega328P. */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom328p.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_IOM328P_H_ +-#define _AVR_IOM328P_H_ 1 +- +-/* Registers and associated bit numbers */ +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC3 3 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC3 3 +-#define PORTC4 4 +-#define PORTC5 5 +-#define PORTC6 6 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define TIFR2 _SFR_IO8(0x17) +-#define TOV2 0 +-#define OCF2A 1 +-#define OCF2B 2 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +-#define PCIF1 1 +-#define PCIF2 2 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +-#define EEAR9 1 +- +-#define _EEPROM_REG_LOCATIONS_ 1F2021 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSRSYNC 0 +-#define PSRASY 1 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define OCR0A _SFR_IO8(0x27) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define OCR0B _SFR_IO8(0x28) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define BODSE 5 +-#define BODS 6 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SELFPRGEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM1 3 +-#define PRTIM0 5 +-#define PRTIM2 6 +-#define PRTWI 7 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +-#define PCIE1 1 +-#define PCIE2 2 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +- +-#define PCMSK2 _SFR_MEM8(0x6D) +-#define PCINT16 0 +-#define PCINT17 1 +-#define PCINT18 2 +-#define PCINT19 3 +-#define PCINT20 4 +-#define PCINT21 5 +-#define PCINT22 6 +-#define PCINT23 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define TIMSK2 _SFR_MEM8(0x70) +-#define TOIE2 0 +-#define OCIE2A 1 +-#define OCIE2B 2 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +- +-#define ADCL _SFR_MEM8(0x78) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_MEM8(0x79) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ACME 6 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define TCCR2A _SFR_MEM8(0xB0) +-#define WGM20 0 +-#define WGM21 1 +-#define COM2B0 4 +-#define COM2B1 5 +-#define COM2A0 6 +-#define COM2A1 7 +- +-#define TCCR2B _SFR_MEM8(0xB1) +-#define CS20 0 +-#define CS21 1 +-#define CS22 2 +-#define WGM22 3 +-#define FOC2B 6 +-#define FOC2A 7 +- +-#define TCNT2 _SFR_MEM8(0xB2) +-#define TCNT2_0 0 +-#define TCNT2_1 1 +-#define TCNT2_2 2 +-#define TCNT2_3 3 +-#define TCNT2_4 4 +-#define TCNT2_5 5 +-#define TCNT2_6 6 +-#define TCNT2_7 7 +- +-#define OCR2A _SFR_MEM8(0xB3) +-#define OCR2_0 0 +-#define OCR2_1 1 +-#define OCR2_2 2 +-#define OCR2_3 3 +-#define OCR2_4 4 +-#define OCR2_5 5 +-#define OCR2_6 6 +-#define OCR2_7 7 +- +-#define OCR2B _SFR_MEM8(0xB4) +-#define OCR2_0 0 +-#define OCR2_1 1 +-#define OCR2_2 2 +-#define OCR2_3 3 +-#define OCR2_4 4 +-#define OCR2_5 5 +-#define OCR2_6 6 +-#define OCR2_7 7 +- +-#define ASSR _SFR_MEM8(0xB6) +-#define TCR2BUB 0 +-#define TCR2AUB 1 +-#define OCR2BUB 2 +-#define OCR2AUB 3 +-#define TCN2UB 4 +-#define AS2 5 +-#define EXCLK 6 +- +-#define TWBR _SFR_MEM8(0xB8) +-#define TWBR0 0 +-#define TWBR1 1 +-#define TWBR2 2 +-#define TWBR3 3 +-#define TWBR4 4 +-#define TWBR5 5 +-#define TWBR6 6 +-#define TWBR7 7 +- +-#define TWSR _SFR_MEM8(0xB9) +-#define TWPS0 0 +-#define TWPS1 1 +-#define TWS3 3 +-#define TWS4 4 +-#define TWS5 5 +-#define TWS6 6 +-#define TWS7 7 +- +-#define TWAR _SFR_MEM8(0xBA) +-#define TWGCE 0 +-#define TWA0 1 +-#define TWA1 2 +-#define TWA2 3 +-#define TWA3 4 +-#define TWA4 5 +-#define TWA5 6 +-#define TWA6 7 +- +-#define TWDR _SFR_MEM8(0xBB) +-#define TWD0 0 +-#define TWD1 1 +-#define TWD2 2 +-#define TWD3 3 +-#define TWD4 4 +-#define TWD5 5 +-#define TWD6 6 +-#define TWD7 7 +- +-#define TWCR _SFR_MEM8(0xBC) +-#define TWIE 0 +-#define TWEN 2 +-#define TWWC 3 +-#define TWSTO 4 +-#define TWSTA 5 +-#define TWEA 6 +-#define TWINT 7 +- +-#define TWAMR _SFR_MEM8(0xBD) +-#define TWAM0 0 +-#define TWAM1 1 +-#define TWAM2 2 +-#define TWAM3 3 +-#define TWAM4 4 +-#define TWAM5 5 +-#define TWAM6 6 +- +-#define UCSR0A _SFR_MEM8(0xC0) +-#define MPCM0 0 +-#define U2X0 1 +-#define UPE0 2 +-#define DOR0 3 +-#define FE0 4 +-#define UDRE0 5 +-#define TXC0 6 +-#define RXC0 7 +- +-#define UCSR0B _SFR_MEM8(0xC1) +-#define TXB80 0 +-#define RXB80 1 +-#define UCSZ02 2 +-#define TXEN0 3 +-#define RXEN0 4 +-#define UDRIE0 5 +-#define TXCIE0 6 +-#define RXCIE0 7 +- +-#define UCSR0C _SFR_MEM8(0xC2) +-#define UCPOL0 0 +-#define UCSZ00 1 +-#define UCPHA0 1 +-#define UCSZ01 2 +-#define UDORD0 2 +-#define USBS0 3 +-#define UPM00 4 +-#define UPM01 5 +-#define UMSEL00 6 +-#define UMSEL01 7 +- +-#define UBRR0 _SFR_MEM16(0xC4) +- +-#define UBRR0L _SFR_MEM8(0xC4) +-#define UBRR0_0 0 +-#define UBRR0_1 1 +-#define UBRR0_2 2 +-#define UBRR0_3 3 +-#define UBRR0_4 4 +-#define UBRR0_5 5 +-#define UBRR0_6 6 +-#define UBRR0_7 7 +- +-#define UBRR0H _SFR_MEM8(0xC5) +-#define UBRR0_8 0 +-#define UBRR0_9 1 +-#define UBRR0_10 2 +-#define UBRR0_11 3 +- +-#define UDR0 _SFR_MEM8(0xC6) +-#define UDR0_0 0 +-#define UDR0_1 1 +-#define UDR0_2 2 +-#define UDR0_3 3 +-#define UDR0_4 4 +-#define UDR0_5 5 +-#define UDR0_6 6 +-#define UDR0_7 7 +- +- +- +-/* Interrupt Vectors */ +-/* Interrupt Vector 0 is the reset vector. */ +- +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +- +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ +- +-#define PCINT0_vect_num 3 +-#define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ +- +-#define PCINT1_vect_num 4 +-#define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */ +- +-#define PCINT2_vect_num 5 +-#define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */ +- +-#define WDT_vect_num 6 +-#define WDT_vect _VECTOR(6) /* Watchdog Time-out Interrupt */ +- +-#define TIMER2_COMPA_vect_num 7 +-#define TIMER2_COMPA_vect _VECTOR(7) /* Timer/Counter2 Compare Match A */ +- +-#define TIMER2_COMPB_vect_num 8 +-#define TIMER2_COMPB_vect _VECTOR(8) /* Timer/Counter2 Compare Match A */ +- +-#define TIMER2_OVF_vect_num 9 +-#define TIMER2_OVF_vect _VECTOR(9) /* Timer/Counter2 Overflow */ +- +-#define TIMER1_CAPT_vect_num 10 +-#define TIMER1_CAPT_vect _VECTOR(10) /* Timer/Counter1 Capture Event */ +- +-#define TIMER1_COMPA_vect_num 11 +-#define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */ +- +-#define TIMER1_COMPB_vect_num 12 +-#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */ +- +-#define TIMER1_OVF_vect_num 13 +-#define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */ +- +-#define TIMER0_COMPA_vect_num 14 +-#define TIMER0_COMPA_vect _VECTOR(14) /* TimerCounter0 Compare Match A */ +- +-#define TIMER0_COMPB_vect_num 15 +-#define TIMER0_COMPB_vect _VECTOR(15) /* TimerCounter0 Compare Match B */ +- +-#define TIMER0_OVF_vect_num 16 +-#define TIMER0_OVF_vect _VECTOR(16) /* Timer/Couner0 Overflow */ +- +-#define SPI_STC_vect_num 17 +-#define SPI_STC_vect _VECTOR(17) /* SPI Serial Transfer Complete */ +- +-#define USART_RX_vect_num 18 +-#define USART_RX_vect _VECTOR(18) /* USART Rx Complete */ +- +-#define USART_UDRE_vect_num 19 +-#define USART_UDRE_vect _VECTOR(19) /* USART, Data Register Empty */ +- +-#define USART_TX_vect_num 20 +-#define USART_TX_vect _VECTOR(20) /* USART Tx Complete */ +- +-#define ADC_vect_num 21 +-#define ADC_vect _VECTOR(21) /* ADC Conversion Complete */ +- +-#define EE_READY_vect_num 22 +-#define EE_READY_vect _VECTOR(22) /* EEPROM Ready */ +- +-#define ANALOG_COMP_vect_num 23 +-#define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */ +- +-#define TWI_vect_num 24 +-#define TWI_vect _VECTOR(24) /* Two-wire Serial Interface */ +- +-#define SPM_READY_vect_num 25 +-#define SPM_READY_vect _VECTOR(25) /* Store Program Memory Read */ +- +-#define _VECTORS_SIZE (26 * 4) +- +- +- +-/* Constants */ +-#define SPM_PAGESIZE 128 +-#define RAMSTART (0x100) +-#define RAMEND 0x8FF /* Last On-Chip SRAM Location */ +-#define XRAMSIZE 0 +-#define XRAMEND RAMEND +-#define E2END 0x3FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x7FFF +- +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) +- +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x95 +-#define SIGNATURE_2 0x0F +- +- +-#endif /* _AVR_IOM328P_H_ */ ++/* Copyright (c) 2007 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++/* $Id: iom328p.h 2444 2014-08-11 22:10:47Z joerg_wunsch $ */ ++ ++/* avr/iom328p.h - definitions for ATmega328P. */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom328p.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_IOM328P_H_ ++#define _AVR_IOM328P_H_ 1 ++ ++/* Registers and associated bit numbers */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC3 3 ++#define PORTC4 4 ++#define PORTC5 5 ++#define PORTC6 6 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++#define EEAR9 1 ++ ++#define _EEPROM_REG_LOCATIONS_ 1F2021 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define PSRASY 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define OCR0A _SFR_IO8(0x27) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define OCR0B _SFR_IO8(0x28) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SELFPRGEN 0 /* only for backwards compatibility with previous ++ * avr-libc versions; not an official name */ ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_MEM8(0x79) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++#define TCNT2_0 0 ++#define TCNT2_1 1 ++#define TCNT2_2 2 ++#define TCNT2_3 3 ++#define TCNT2_4 4 ++#define TCNT2_5 5 ++#define TCNT2_6 6 ++#define TCNT2_7 7 ++ ++#define OCR2A _SFR_MEM8(0xB3) ++#define OCR2_0 0 ++#define OCR2_1 1 ++#define OCR2_2 2 ++#define OCR2_3 3 ++#define OCR2_4 4 ++#define OCR2_5 5 ++#define OCR2_6 6 ++#define OCR2_7 7 ++ ++#define OCR2B _SFR_MEM8(0xB4) ++#define OCR2_0 0 ++#define OCR2_1 1 ++#define OCR2_2 2 ++#define OCR2_3 3 ++#define OCR2_4 4 ++#define OCR2_5 5 ++#define OCR2_6 6 ++#define OCR2_7 7 ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++ ++#define TWBR _SFR_MEM8(0xB8) ++#define TWBR0 0 ++#define TWBR1 1 ++#define TWBR2 2 ++#define TWBR3 3 ++#define TWBR4 4 ++#define TWBR5 5 ++#define TWBR6 6 ++#define TWBR7 7 ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++#define TWD0 0 ++#define TWD1 1 ++#define TWD2 2 ++#define TWD3 3 ++#define TWD4 4 ++#define TWD5 5 ++#define TWD6 6 ++#define TWD7 7 ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 0 ++#define TWAM1 1 ++#define TWAM2 2 ++#define TWAM3 3 ++#define TWAM4 4 ++#define TWAM5 5 ++#define TWAM6 6 ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCPHA0 1 ++#define UCSZ01 2 ++#define UDORD0 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0_0 0 ++#define UBRR0_1 1 ++#define UBRR0_2 2 ++#define UBRR0_3 3 ++#define UBRR0_4 4 ++#define UBRR0_5 5 ++#define UBRR0_6 6 ++#define UBRR0_7 7 ++ ++#define UBRR0H _SFR_MEM8(0xC5) ++#define UBRR0_8 0 ++#define UBRR0_9 1 ++#define UBRR0_10 2 ++#define UBRR0_11 3 ++ ++#define UDR0 _SFR_MEM8(0xC6) ++#define UDR0_0 0 ++#define UDR0_1 1 ++#define UDR0_2 2 ++#define UDR0_3 3 ++#define UDR0_4 4 ++#define UDR0_5 5 ++#define UDR0_6 6 ++#define UDR0_7 7 ++ ++ ++ ++/* Interrupt Vectors */ ++/* Interrupt Vector 0 is the reset vector. */ ++ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ ++ ++#define PCINT0_vect_num 3 ++#define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ ++ ++#define PCINT1_vect_num 4 ++#define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */ ++ ++#define PCINT2_vect_num 5 ++#define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */ ++ ++#define WDT_vect_num 6 ++#define WDT_vect _VECTOR(6) /* Watchdog Time-out Interrupt */ ++ ++#define TIMER2_COMPA_vect_num 7 ++#define TIMER2_COMPA_vect _VECTOR(7) /* Timer/Counter2 Compare Match A */ ++ ++#define TIMER2_COMPB_vect_num 8 ++#define TIMER2_COMPB_vect _VECTOR(8) /* Timer/Counter2 Compare Match A */ ++ ++#define TIMER2_OVF_vect_num 9 ++#define TIMER2_OVF_vect _VECTOR(9) /* Timer/Counter2 Overflow */ ++ ++#define TIMER1_CAPT_vect_num 10 ++#define TIMER1_CAPT_vect _VECTOR(10) /* Timer/Counter1 Capture Event */ ++ ++#define TIMER1_COMPA_vect_num 11 ++#define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */ ++ ++#define TIMER1_COMPB_vect_num 12 ++#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */ ++ ++#define TIMER1_OVF_vect_num 13 ++#define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */ ++ ++#define TIMER0_COMPA_vect_num 14 ++#define TIMER0_COMPA_vect _VECTOR(14) /* TimerCounter0 Compare Match A */ ++ ++#define TIMER0_COMPB_vect_num 15 ++#define TIMER0_COMPB_vect _VECTOR(15) /* TimerCounter0 Compare Match B */ ++ ++#define TIMER0_OVF_vect_num 16 ++#define TIMER0_OVF_vect _VECTOR(16) /* Timer/Couner0 Overflow */ ++ ++#define SPI_STC_vect_num 17 ++#define SPI_STC_vect _VECTOR(17) /* SPI Serial Transfer Complete */ ++ ++#define USART_RX_vect_num 18 ++#define USART_RX_vect _VECTOR(18) /* USART Rx Complete */ ++ ++#define USART_UDRE_vect_num 19 ++#define USART_UDRE_vect _VECTOR(19) /* USART, Data Register Empty */ ++ ++#define USART_TX_vect_num 20 ++#define USART_TX_vect _VECTOR(20) /* USART Tx Complete */ ++ ++#define ADC_vect_num 21 ++#define ADC_vect _VECTOR(21) /* ADC Conversion Complete */ ++ ++#define EE_READY_vect_num 22 ++#define EE_READY_vect _VECTOR(22) /* EEPROM Ready */ ++ ++#define ANALOG_COMP_vect_num 23 ++#define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */ ++ ++#define TWI_vect_num 24 ++#define TWI_vect _VECTOR(24) /* Two-wire Serial Interface */ ++ ++#define SPM_READY_vect_num 25 ++#define SPM_READY_vect _VECTOR(25) /* Store Program Memory Read */ ++ ++#define _VECTORS_SIZE (26 * 4) ++ ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE 128 ++#define RAMSTART (0x100) ++#define RAMEND 0x8FF /* Last On-Chip SRAM Location */ ++#define XRAMSIZE 0 ++#define XRAMEND RAMEND ++#define E2END 0x3FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x7FFF ++ ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#if defined(__AVR_ATmega328__) ++# define SIGNATURE_2 0x14 ++#else /* ATmega328P */ ++# define SIGNATURE_2 0x0F ++#endif ++ ++ ++#endif /* _AVR_IOM328P_H_ */ +diff --git a/include/avr/iom329.h b/include/avr/iom329.h +index 17fdf7a..5527c8a 100644 +--- a/include/avr/iom329.h ++++ b/include/avr/iom329.h +@@ -1,1056 +1,1057 @@ +-/* Copyright (c) 2004 Eric B. Weddington +- Copyright (c) 2005, 2006, 2007 Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* avr/iom329.h - definitions for ATmega329 and ATmega329P. */ +- +-#ifndef _AVR_IOM329_H_ +-#define _AVR_IOM329_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom329.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* Registers and associated bit numbers */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-#define PORTA _SFR_IO8(0x02) +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-#define PINB _SFR_IO8(0x03) +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-#define PORTB _SFR_IO8(0x05) +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-#define PORTC _SFR_IO8(0x08) +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-#define PINE _SFR_IO8(0x0C) +-#define PINE7 7 +-#define PINE6 6 +-#define PINE5 5 +-#define PINE4 4 +-#define PINE3 3 +-#define PINE2 2 +-#define PINE1 1 +-#define PINE0 0 +- +-#define DDRE _SFR_IO8(0x0D) +-#define DDE7 7 +-#define DDE6 6 +-#define DDE5 5 +-#define DDE4 4 +-#define DDE3 3 +-#define DDE2 2 +-#define DDE1 1 +-#define DDE0 0 +- +-#define PORTE _SFR_IO8(0x0E) +-#define PE7 7 +-#define PE6 6 +-#define PE5 5 +-#define PE4 4 +-#define PE3 3 +-#define PE2 2 +-#define PE1 1 +-#define PE0 0 +- +-#define PINF _SFR_IO8(0x0F) +-#define PINF7 7 +-#define PINF6 6 +-#define PINF5 5 +-#define PINF4 4 +-#define PINF3 3 +-#define PINF2 2 +-#define PINF1 1 +-#define PINF0 0 +- +-#define DDRF _SFR_IO8(0x10) +-#define DDF7 7 +-#define DDF6 6 +-#define DDF5 5 +-#define DDF4 4 +-#define DDF3 3 +-#define DDF2 2 +-#define DDF1 1 +-#define DDF0 0 +- +-#define PORTF _SFR_IO8(0x11) +-#define PF7 7 +-#define PF6 6 +-#define PF5 5 +-#define PF4 4 +-#define PF3 3 +-#define PF2 2 +-#define PF1 1 +-#define PF0 0 +- +-#define PING _SFR_IO8(0x12) +-#define PING5 5 +-#define PING4 4 +-#define PING3 3 +-#define PING2 2 +-#define PING1 1 +-#define PING0 0 +- +-#define DDRG _SFR_IO8(0x13) +-#define DDG4 4 +-#define DDG3 3 +-#define DDG2 2 +-#define DDG1 1 +-#define DDG0 0 +- +-#define PORTG _SFR_IO8(0x14) +-#define PG4 4 +-#define PG3 3 +-#define PG2 2 +-#define PG1 1 +-#define PG0 0 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define TIFR2 _SFR_IO8(0x17) +-#define TOV2 0 +-#define OCF2A 1 +- +-/* Reserved [0x18..0x1B] */ +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define PCIF0 4 +-#define PCIF1 5 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define PCIE0 4 +-#define PCIE1 5 +- +-#define GPIOR0 _SFR_IO8(0x1E) +- +-#define EECR _SFR_IO8(0x1F) +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-#define EEDR _SFR_IO8(0X20) +- +-/* Combine EEARL and EEARH */ +-#define EEAR _SFR_IO16(0x21) +-#define EEARL _SFR_IO8(0x21) +-#define EEARH _SFR_IO8(0X22) +- +-/* 6-char sequence denoting where to find the EEPROM registers in memory space. +- Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM +- subroutines. +- First two letters: EECR address. +- Second two letters: EEDR address. +- Last two letters: EEAR address. */ +-#define __EEPROM_REG_LOCATIONS__ 1F2021 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSR10 0 +-#define PSR2 1 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM01 3 +-#define COM0A0 4 +-#define COM0A1 5 +-#define WGM00 6 +-#define FOC0A 7 +- +-/* Reserved [0x25] */ +- +-#define TCNT0 _SFR_IO8(0X26) +- +-#define OCR0A _SFR_IO8(0X27) +- +-/* Reserved [0x28..0x29] */ +- +-#define GPIOR1 _SFR_IO8(0x2A) +- +-#define GPIOR2 _SFR_IO8(0x2B) +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0X2E) +- +-/* Reserved [0x2F] */ +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define OCDR _SFR_IO8(0x31) +-#define OCDR0 0 +-#define OCDR1 1 +-#define OCDR2 2 +-#define OCDR3 3 +-#define OCDR4 4 +-#define OCDR5 5 +-#define OCDR6 6 +-#define OCDR7 7 +-#define IDRD 7 +- +-/* Reserved [0x32] */ +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +-#define JTRF 4 +- +-#define MCUCR _SFR_IO8(0X35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#if defined(__AVR_ATmega329P__) +-#define BODSE 5 +-#define BODS 6 +-#endif +-#define JTD 7 +- +-/* Reserved [0x36] */ +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define RWWSB 6 +-#define SPMIE 7 +- +-/* Reserved [0x38..0x3C] */ +- +-/* SP [0x3D..0x3E] */ +-/* SREG [0x3F] */ +- +-#define WDTCR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-/* Reserved [0x62..0x63] */ +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM1 3 +-#define PRLCD 4 +- +-/* Reserved [0x65] */ +- +-#define OSCCAL _SFR_MEM8(0x66) +- +-/* Reserved [0x67..0x68] */ +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +- +-/* Reserved [0x6A] */ +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-/* Reserved [0x6D] */ +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define TIMSK2 _SFR_MEM8(0x70) +-#define TOIE2 0 +-#define OCIE2A 1 +- +-/* Reserved [0x71..0x77] */ +- +-/* Combine ADCL and ADCH */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +-#define ADCL _SFR_MEM8(0x78) +-#define ADCH _SFR_MEM8(0x79) +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ACME 6 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-/* Reserved [0x7D] */ +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0X80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0X81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-/* Reserved [0x83] */ +- +-/* Combine TCNT1L and TCNT1H */ +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1H _SFR_MEM8(0x85) +- +-/* Combine ICR1L and ICR1H */ +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1H _SFR_MEM8(0x87) +- +-/* Combine OCR1AL and OCR1AH */ +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AH _SFR_MEM8(0x89) +- +-/* Combine OCR1BL and OCR1BH */ +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BH _SFR_MEM8(0x8B) +- +-/* Reserved [0x8C..0xAF] */ +- +-#define TCCR2A _SFR_MEM8(0xB0) +-#define CS20 0 +-#define CS21 1 +-#define CS22 2 +-#define WGM21 3 +-#define COM2A0 4 +-#define COM2A1 5 +-#define WGM20 6 +-#define FOC2A 7 +- +-/* Reserved [0xB1] */ +- +-#define TCNT2 _SFR_MEM8(0xB2) +- +-#define OCR2A _SFR_MEM8(0xB3) +- +-/* Reserved [0xB4..0xB5] */ +- +-#define ASSR _SFR_MEM8(0xB6) +-#define TCR2UB 0 +-#define OCR2UB 1 +-#define TCN2UB 2 +-#define AS2 3 +-#define EXCLK 4 +- +-/* Reserved [0xB7] */ +- +-#define USICR _SFR_MEM8(0xB8) +-#define USITC 0 +-#define USICLK 1 +-#define USICS0 2 +-#define USICS1 3 +-#define USIWM0 4 +-#define USIWM1 5 +-#define USIOIE 6 +-#define USISIE 7 +- +-#define USISR _SFR_MEM8(0xB9) +-#define USICNT0 0 +-#define USICNT1 1 +-#define USICNT2 2 +-#define USICNT3 3 +-#define USIDC 4 +-#define USIPF 5 +-#define USIOIF 6 +-#define USISIF 7 +- +-#define USIDR _SFR_MEM8(0xBA) +- +-/* Reserved [0xBB..0xBF] */ +- +-#define UCSR0A _SFR_MEM8(0xC0) +-#define MPCM0 0 +-#define U2X0 1 +-#define UPE0 2 +-#define DOR0 3 +-#define FE0 4 +-#define UDRE0 5 +-#define TXC0 6 +-#define RXC0 7 +- +-#define UCSR0B _SFR_MEM8(0XC1) +-#define TXB80 0 +-#define RXB80 1 +-#define UCSZ02 2 +-#define TXEN0 3 +-#define RXEN0 4 +-#define UDRIE0 5 +-#define TXCIE0 6 +-#define RXCIE0 7 +- +-#define UCSR0C _SFR_MEM8(0xC2) +-#define UCPOL0 0 +-#define UCSZ00 1 +-#define UCSZ01 2 +-#define USBS0 3 +-#define UPM00 4 +-#define UPM01 5 +-#define UMSEL0 6 +- +-/* Reserved [0xC3] */ +- +-/* Combine UBRR0L and UBRR0H */ +-#define UBRR0 _SFR_MEM16(0xC4) +- +-#define UBRR0L _SFR_MEM8(0xC4) +-#define UBRR0H _SFR_MEM8(0xC5) +- +-#define UDR0 _SFR_MEM8(0XC6) +- +-/* Reserved [0xC7..0xE3] */ +- +-#define LCDCRA _SFR_MEM8(0XE4) +-#define LCDBL 0 +-#if defined(__AVR_ATmega329P__) +-#define LCDCCD 1 +-#define LCDBD 2 +-#endif +-#define LCDIE 3 +-#define LCDIF 4 +-#define LCDAB 6 +-#define LCDEN 7 +- +-#define LCDCRB _SFR_MEM8(0XE5) +-#define LCDPM0 0 +-#define LCDPM1 1 +-#define LCDPM2 2 +-#define LCDMUX0 4 +-#define LCDMUX1 5 +-#define LCD2B 6 +-#define LCDCS 7 +- +-#define LCDFRR _SFR_MEM8(0XE6) +-#define LCDCD0 0 +-#define LCDCD1 1 +-#define LCDCD2 2 +-#define LCDPS0 4 +-#define LCDPS1 5 +-#define LCDPS2 6 +- +-#define LCDCCR _SFR_MEM8(0XE7) +-#define LCDCC0 0 +-#define LCDCC1 1 +-#define LCDCC2 2 +-#define LCDCC3 3 +-#if defined(__AVR_ATmega329P__) +-#define LCDMDT 4 +-#endif +-#define LCDDC0 5 +-#define LCDDC1 6 +-#define LCDDC2 7 +- +-/* Reserved [0xE8..0xEB] */ +- +-#define LCDDR00 _SFR_MEM8(0XEC) +-#define SEG000 0 +-#define SEG001 1 +-#define SEG002 2 +-#define SEG003 3 +-#define SEG004 4 +-#define SEG005 5 +-#define SEG006 6 +-#define SEG007 7 +- +-#define LCDDR01 _SFR_MEM8(0XED) +-#define SEG008 0 +-#define SEG009 1 +-#define SEG010 2 +-#define SEG011 3 +-#define SEG012 4 +-#define SEG013 5 +-#define SEG014 6 +-#define SEG015 7 +- +-#define LCDDR02 _SFR_MEM8(0XEE) +-#define SEG016 0 +-#define SEG017 1 +-#define SEG018 2 +-#define SEG019 3 +-#define SEG020 4 +-#define SEG021 5 +-#define SEG022 6 +-#define SEG023 7 +- +-#define LCDDR03 _SFR_MEM8(0XEF) +-#define SEG024 0 +- +-/* Reserved [0xF0] */ +- +-#define LCDDR05 _SFR_MEM8(0XF1) +-#define SEG100 0 +-#define SEG101 1 +-#define SEG102 2 +-#define SEG103 3 +-#define SEG104 4 +-#define SEG105 5 +-#define SEG106 6 +-#define SEG107 7 +- +-#define LCDDR06 _SFR_MEM8(0XF2) +-#define SEG108 0 +-#define SEG109 1 +-#define SEG110 2 +-#define SEG111 3 +-#define SEG112 4 +-#define SEG113 5 +-#define SEG114 6 +-#define SEG115 7 +- +-#define LCDDR07 _SFR_MEM8(0XF3) +-#define SEG116 0 +-#define SEG117 1 +-#define SEG118 2 +-#define SEG119 3 +-#define SEG120 4 +-#define SEG121 5 +-#define SEG122 6 +-#define SEG123 7 +- +-#define LCDDR08 _SFR_MEM8(0XF4) +-#define SEG124 0 +- +-/* Reserved [0xF5] */ +- +-#define LCDDR10 _SFR_MEM8(0XF6) +-#define SEG200 0 +-#define SEG201 1 +-#define SEG202 2 +-#define SEG203 3 +-#define SEG204 4 +-#define SEG205 5 +-#define SEG206 6 +-#define SEG207 7 +- +-#define LCDDR11 _SFR_MEM8(0XF7) +-#define SEG208 0 +-#define SEG209 1 +-#define SEG210 2 +-#define SEG211 3 +-#define SEG212 4 +-#define SEG213 5 +-#define SEG214 6 +-#define SEG215 7 +- +-#define LCDDR12 _SFR_MEM8(0XF8) +-#define SEG216 0 +-#define SEG217 1 +-#define SEG218 2 +-#define SEG219 3 +-#define SEG220 4 +-#define SEG221 5 +-#define SEG222 6 +-#define SEG223 7 +- +-#define LCDDR13 _SFR_MEM8(0XF9) +-#define SEG224 0 +- +-/* Reserved [0xFA] */ +- +-#define LCDDR15 _SFR_MEM8(0XFB) +-#define SEG300 0 +-#define SEG301 1 +-#define SEG302 2 +-#define SEG303 3 +-#define SEG304 4 +-#define SEG305 5 +-#define SEG306 6 +-#define SEG307 7 +- +-#define LCDDR16 _SFR_MEM8(0XFC) +-#define SEG308 0 +-#define SEG309 1 +-#define SEG310 2 +-#define SEG311 3 +-#define SEG312 4 +-#define SEG313 5 +-#define SEG314 6 +-#define SEG315 7 +- +-#define LCDDR17 _SFR_MEM8(0XFD) +-#define SEG316 0 +-#define SEG217 1 +-#define SEG318 2 +-#define SEG319 3 +-#define SEG320 4 +-#define SEG321 5 +-#define SEG322 6 +-#define SEG323 7 +- +-#define LCDDR18 _SFR_MEM8(0XFE) +-#define SEG324 0 +- +-/* Reserved [0xFF] */ +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* Pin Change Interrupt Request 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) +-#define SIG_PIN_CHANGE0 _VECTOR(2) +- +-/* Pin Change Interrupt Request 1 */ +-#define PCINT1_vect_num 3 +-#define PCINT1_vect _VECTOR(3) +-#define SIG_PIN_CHANGE1 _VECTOR(3) +- +-/* Timer/Counter2 Compare Match */ +-#define TIMER2_COMP_vect_num 4 +-#define TIMER2_COMP_vect _VECTOR(4) +-#define SIG_OUTPUT_COMPARE2 _VECTOR(4) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 5 +-#define TIMER2_OVF_vect _VECTOR(5) +-#define SIG_OVERFLOW2 _VECTOR(5) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 6 +-#define TIMER1_CAPT_vect _VECTOR(6) +-#define SIG_INPUT_CAPTURE1 _VECTOR(6) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 7 +-#define TIMER1_COMPA_vect _VECTOR(7) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(7) +- +-/* Timer/Counter Compare Match B */ +-#define TIMER1_COMPB_vect_num 8 +-#define TIMER1_COMPB_vect _VECTOR(8) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(8) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 9 +-#define TIMER1_OVF_vect _VECTOR(9) +-#define SIG_OVERFLOW1 _VECTOR(9) +- +-/* Timer/Counter0 Compare Match */ +-#define TIMER0_COMP_vect_num 10 +-#define TIMER0_COMP_vect _VECTOR(10) +-#define SIG_OUTPUT_COMPARE0 _VECTOR(10) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 11 +-#define TIMER0_OVF_vect _VECTOR(11) +-#define SIG_OVERFLOW0 _VECTOR(11) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 12 +-#define SPI_STC_vect _VECTOR(12) +-#define SIG_SPI _VECTOR(12) +- +-/* USART0, Rx Complete */ +-#define USART0_RX_vect_num 13 +-#define USART0_RX_vect _VECTOR(13) +-#define SIG_UART_RECV _VECTOR(13) +- +-/* USART0 Data register Empty */ +-#define USART0_UDRE_vect_num 14 +-#define USART0_UDRE_vect _VECTOR(14) +-#define SIG_UART_DATA _VECTOR(14) +- +-/* USART0, Tx Complete */ +-#define USART0_TX_vect_num 15 +-#define USART0_TX_vect _VECTOR(15) +-#define SIG_UART_TRANS _VECTOR(15) +- +-/* USI Start Condition */ +-#define USI_START_vect_num 16 +-#define USI_START_vect _VECTOR(16) +-#define SIG_USI_START _VECTOR(16) +- +-/* USI Overflow */ +-#define USI_OVERFLOW_vect_num 17 +-#define USI_OVERFLOW_vect _VECTOR(17) +-#define SIG_USI_OVERFLOW _VECTOR(17) +- +-/* Analog Comparator */ +-#define ANALOG_COMP_vect_num 18 +-#define ANALOG_COMP_vect _VECTOR(18) +-#define SIG_COMPARATOR _VECTOR(18) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 19 +-#define ADC_vect _VECTOR(19) +-#define SIG_ADC _VECTOR(19) +- +-/* EEPROM Ready */ +-#define EE_READY_vect_num 20 +-#define EE_READY_vect _VECTOR(20) +-#define SIG_EEPROM_READY _VECTOR(20) +- +-/* Store Program Memory Read */ +-#define SPM_READY_vect_num 21 +-#define SPM_READY_vect _VECTOR(21) +-#define SIG_SPM_READY _VECTOR(21) +- +-/* LCD Start of Frame */ +-#define LCD_vect_num 22 +-#define LCD_vect _VECTOR(22) +-#define SIG_LCD _VECTOR(22) +- +-#define _VECTORS_SIZE 92 +- +- +-/* Constants */ +-#define SPM_PAGESIZE 128 +-#define RAMEND 0x8FF +-#define XRAMEND RAMEND +-#define E2END 0x3FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x7FFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x95 +-#define SIGNATURE_2 0x03 +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_PIN_CHANGE0 +-#pragma GCC poison SIG_PIN_CHANGE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE2 +-#pragma GCC poison SIG_OVERFLOW2 +-#pragma GCC poison SIG_INPUT_CAPTURE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OUTPUT_COMPARE0 +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_SPI +-#pragma GCC poison SIG_UART_RECV +-#pragma GCC poison SIG_UART_DATA +-#pragma GCC poison SIG_UART_TRANS +-#pragma GCC poison SIG_USI_START +-#pragma GCC poison SIG_USI_OVERFLOW +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_ADC +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_SPM_READY +-#pragma GCC poison SIG_LCD +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +-#endif /* _AVR_IOM329_H_ */ ++/* Copyright (c) 2004 Eric B. Weddington ++ Copyright (c) 2005, 2006, 2007 Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* avr/iom329.h - definitions for ATmega329 and ATmega329P. */ ++ ++#ifndef _AVR_IOM329_H_ ++#define _AVR_IOM329_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom329.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE7 7 ++#define DDE6 6 ++#define DDE5 5 ++#define DDE4 4 ++#define DDE3 3 ++#define DDE2 2 ++#define DDE1 1 ++#define DDE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PE7 7 ++#define PE6 6 ++#define PE5 5 ++#define PE4 4 ++#define PE3 3 ++#define PE2 2 ++#define PE1 1 ++#define PE0 0 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDF7 7 ++#define DDF6 6 ++#define DDF5 5 ++#define DDF4 4 ++#define DDF3 3 ++#define DDF2 2 ++#define DDF1 1 ++#define DDF0 0 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PF7 7 ++#define PF6 6 ++#define PF5 5 ++#define PF4 4 ++#define PF3 3 ++#define PF2 2 ++#define PF1 1 ++#define PF0 0 ++ ++#define PING _SFR_IO8(0x12) ++#define PING5 5 ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++#define DDRG _SFR_IO8(0x13) ++#define DDG4 4 ++#define DDG3 3 ++#define DDG2 2 ++#define DDG1 1 ++#define DDG0 0 ++ ++#define PORTG _SFR_IO8(0x14) ++#define PG4 4 ++#define PG3 3 ++#define PG2 2 ++#define PG1 1 ++#define PG0 0 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++ ++/* Reserved [0x18..0x1B] */ ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define PCIF0 4 ++#define PCIF1 5 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define PCIE0 4 ++#define PCIE1 5 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++#define EEDR _SFR_IO8(0X20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0X22) ++ ++/* 6-char sequence denoting where to find the EEPROM registers in memory space. ++ Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM ++ subroutines. ++ First two letters: EECR address. ++ Second two letters: EEDR address. ++ Last two letters: EEAR address. */ ++#define __EEPROM_REG_LOCATIONS__ 1F2021 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR10 0 ++#define PSR2 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM01 3 ++#define COM0A0 4 ++#define COM0A1 5 ++#define WGM00 6 ++#define FOC0A 7 ++ ++/* Reserved [0x25] */ ++ ++#define TCNT0 _SFR_IO8(0X26) ++ ++#define OCR0A _SFR_IO8(0X27) ++ ++/* Reserved [0x28..0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0X2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCDR7 7 ++#define IDRD 7 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define JTRF 4 ++ ++#define MCUCR _SFR_IO8(0X35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#if defined(__AVR_ATmega329P__) ++#define BODSE 5 ++#define BODS 6 ++#endif ++#define JTD 7 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++/* SREG [0x3F] */ ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRLCD 4 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++ ++/* Reserved [0x67..0x68] */ ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++/* Reserved [0x6D] */ ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++ ++/* Reserved [0x71..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0X80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0X81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM21 3 ++#define COM2A0 4 ++#define COM2A1 5 ++#define WGM20 6 ++#define FOC2A 7 ++ ++/* Reserved [0xB1] */ ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++/* Reserved [0xB4..0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2UB 0 ++#define OCR2UB 1 ++#define TCN2UB 2 ++#define AS2 3 ++#define EXCLK 4 ++ ++/* Reserved [0xB7] */ ++ ++#define USICR _SFR_MEM8(0xB8) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_MEM8(0xB9) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_MEM8(0xBA) ++ ++/* Reserved [0xBB..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0XC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL0 6 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0XC6) ++ ++/* Reserved [0xC7..0xE3] */ ++ ++#define LCDCRA _SFR_MEM8(0XE4) ++#define LCDBL 0 ++#if defined(__AVR_ATmega329P__) ++#define LCDCCD 1 ++#define LCDBD 2 ++#endif ++#define LCDIE 3 ++#define LCDIF 4 ++#define LCDAB 6 ++#define LCDEN 7 ++ ++#define LCDCRB _SFR_MEM8(0XE5) ++#define LCDPM0 0 ++#define LCDPM1 1 ++#define LCDPM2 2 ++#define LCDMUX0 4 ++#define LCDMUX1 5 ++#define LCD2B 6 ++#define LCDCS 7 ++ ++#define LCDFRR _SFR_MEM8(0XE6) ++#define LCDCD0 0 ++#define LCDCD1 1 ++#define LCDCD2 2 ++#define LCDPS0 4 ++#define LCDPS1 5 ++#define LCDPS2 6 ++ ++#define LCDCCR _SFR_MEM8(0XE7) ++#define LCDCC0 0 ++#define LCDCC1 1 ++#define LCDCC2 2 ++#define LCDCC3 3 ++#if defined(__AVR_ATmega329P__) ++#define LCDMDT 4 ++#endif ++#define LCDDC0 5 ++#define LCDDC1 6 ++#define LCDDC2 7 ++ ++/* Reserved [0xE8..0xEB] */ ++ ++#define LCDDR00 _SFR_MEM8(0XEC) ++#define SEG000 0 ++#define SEG001 1 ++#define SEG002 2 ++#define SEG003 3 ++#define SEG004 4 ++#define SEG005 5 ++#define SEG006 6 ++#define SEG007 7 ++ ++#define LCDDR01 _SFR_MEM8(0XED) ++#define SEG008 0 ++#define SEG009 1 ++#define SEG010 2 ++#define SEG011 3 ++#define SEG012 4 ++#define SEG013 5 ++#define SEG014 6 ++#define SEG015 7 ++ ++#define LCDDR02 _SFR_MEM8(0XEE) ++#define SEG016 0 ++#define SEG017 1 ++#define SEG018 2 ++#define SEG019 3 ++#define SEG020 4 ++#define SEG021 5 ++#define SEG022 6 ++#define SEG023 7 ++ ++#define LCDDR03 _SFR_MEM8(0XEF) ++#define SEG024 0 ++ ++/* Reserved [0xF0] */ ++ ++#define LCDDR05 _SFR_MEM8(0XF1) ++#define SEG100 0 ++#define SEG101 1 ++#define SEG102 2 ++#define SEG103 3 ++#define SEG104 4 ++#define SEG105 5 ++#define SEG106 6 ++#define SEG107 7 ++ ++#define LCDDR06 _SFR_MEM8(0XF2) ++#define SEG108 0 ++#define SEG109 1 ++#define SEG110 2 ++#define SEG111 3 ++#define SEG112 4 ++#define SEG113 5 ++#define SEG114 6 ++#define SEG115 7 ++ ++#define LCDDR07 _SFR_MEM8(0XF3) ++#define SEG116 0 ++#define SEG117 1 ++#define SEG118 2 ++#define SEG119 3 ++#define SEG120 4 ++#define SEG121 5 ++#define SEG122 6 ++#define SEG123 7 ++ ++#define LCDDR08 _SFR_MEM8(0XF4) ++#define SEG124 0 ++ ++/* Reserved [0xF5] */ ++ ++#define LCDDR10 _SFR_MEM8(0XF6) ++#define SEG200 0 ++#define SEG201 1 ++#define SEG202 2 ++#define SEG203 3 ++#define SEG204 4 ++#define SEG205 5 ++#define SEG206 6 ++#define SEG207 7 ++ ++#define LCDDR11 _SFR_MEM8(0XF7) ++#define SEG208 0 ++#define SEG209 1 ++#define SEG210 2 ++#define SEG211 3 ++#define SEG212 4 ++#define SEG213 5 ++#define SEG214 6 ++#define SEG215 7 ++ ++#define LCDDR12 _SFR_MEM8(0XF8) ++#define SEG216 0 ++#define SEG217 1 ++#define SEG218 2 ++#define SEG219 3 ++#define SEG220 4 ++#define SEG221 5 ++#define SEG222 6 ++#define SEG223 7 ++ ++#define LCDDR13 _SFR_MEM8(0XF9) ++#define SEG224 0 ++ ++/* Reserved [0xFA] */ ++ ++#define LCDDR15 _SFR_MEM8(0XFB) ++#define SEG300 0 ++#define SEG301 1 ++#define SEG302 2 ++#define SEG303 3 ++#define SEG304 4 ++#define SEG305 5 ++#define SEG306 6 ++#define SEG307 7 ++ ++#define LCDDR16 _SFR_MEM8(0XFC) ++#define SEG308 0 ++#define SEG309 1 ++#define SEG310 2 ++#define SEG311 3 ++#define SEG312 4 ++#define SEG313 5 ++#define SEG314 6 ++#define SEG315 7 ++ ++#define LCDDR17 _SFR_MEM8(0XFD) ++#define SEG316 0 ++#define SEG217 1 ++#define SEG318 2 ++#define SEG319 3 ++#define SEG320 4 ++#define SEG321 5 ++#define SEG322 6 ++#define SEG323 7 ++ ++#define LCDDR18 _SFR_MEM8(0XFE) ++#define SEG324 0 ++ ++/* Reserved [0xFF] */ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) ++#define SIG_PIN_CHANGE0 _VECTOR(2) ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect_num 3 ++#define PCINT1_vect _VECTOR(3) ++#define SIG_PIN_CHANGE1 _VECTOR(3) ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect_num 4 ++#define TIMER2_COMP_vect _VECTOR(4) ++#define SIG_OUTPUT_COMPARE2 _VECTOR(4) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 5 ++#define TIMER2_OVF_vect _VECTOR(5) ++#define SIG_OVERFLOW2 _VECTOR(5) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 6 ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define SIG_INPUT_CAPTURE1 _VECTOR(6) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 7 ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(7) ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect_num 8 ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(8) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 9 ++#define TIMER1_OVF_vect _VECTOR(9) ++#define SIG_OVERFLOW1 _VECTOR(9) ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect_num 10 ++#define TIMER0_COMP_vect _VECTOR(10) ++#define SIG_OUTPUT_COMPARE0 _VECTOR(10) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 11 ++#define TIMER0_OVF_vect _VECTOR(11) ++#define SIG_OVERFLOW0 _VECTOR(11) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 12 ++#define SPI_STC_vect _VECTOR(12) ++#define SIG_SPI _VECTOR(12) ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect_num 13 ++#define USART0_RX_vect _VECTOR(13) ++#define SIG_UART_RECV _VECTOR(13) ++ ++/* USART0 Data register Empty */ ++#define USART0_UDRE_vect_num 14 ++#define USART0_UDRE_vect _VECTOR(14) ++#define SIG_UART_DATA _VECTOR(14) ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect_num 15 ++#define USART0_TX_vect _VECTOR(15) ++#define SIG_UART_TRANS _VECTOR(15) ++ ++/* USI Start Condition */ ++#define USI_START_vect_num 16 ++#define USI_START_vect _VECTOR(16) ++#define SIG_USI_START _VECTOR(16) ++ ++/* USI Overflow */ ++#define USI_OVERFLOW_vect_num 17 ++#define USI_OVERFLOW_vect _VECTOR(17) ++#define SIG_USI_OVERFLOW _VECTOR(17) ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect_num 18 ++#define ANALOG_COMP_vect _VECTOR(18) ++#define SIG_COMPARATOR _VECTOR(18) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 19 ++#define ADC_vect _VECTOR(19) ++#define SIG_ADC _VECTOR(19) ++ ++/* EEPROM Ready */ ++#define EE_READY_vect_num 20 ++#define EE_READY_vect _VECTOR(20) ++#define SIG_EEPROM_READY _VECTOR(20) ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect_num 21 ++#define SPM_READY_vect _VECTOR(21) ++#define SIG_SPM_READY _VECTOR(21) ++ ++/* LCD Start of Frame */ ++#define LCD_vect_num 22 ++#define LCD_vect _VECTOR(22) ++#define SIG_LCD _VECTOR(22) ++ ++#define _VECTORS_SIZE 92 ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE 128 ++#define RAMSTART 0x100 ++#define RAMEND 0x8FF ++#define XRAMEND RAMEND ++#define E2END 0x3FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x7FFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x03 ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_PIN_CHANGE0 ++#pragma GCC poison SIG_PIN_CHANGE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE2 ++#pragma GCC poison SIG_OVERFLOW2 ++#pragma GCC poison SIG_INPUT_CAPTURE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OUTPUT_COMPARE0 ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_SPI ++#pragma GCC poison SIG_UART_RECV ++#pragma GCC poison SIG_UART_DATA ++#pragma GCC poison SIG_UART_TRANS ++#pragma GCC poison SIG_USI_START ++#pragma GCC poison SIG_USI_OVERFLOW ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_ADC ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_SPM_READY ++#pragma GCC poison SIG_LCD ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++#endif /* _AVR_IOM329_H_ */ +diff --git a/include/avr/iom3290.h b/include/avr/iom3290.h +index d6e0434..aaa2ec9 100644 +--- a/include/avr/iom3290.h ++++ b/include/avr/iom3290.h +@@ -1,1214 +1,1215 @@ +-/* Copyright (c) 2004 Eric B. Weddington +- Copyright (c) 2005, 2006, 2007 Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* avr/iom3290.h - definitions for ATmega3290 and ATmega3290P. */ +- +-#ifndef _AVR_IOM3290_H_ +-#define _AVR_IOM3290_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom3290.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* Registers and associated bit numbers */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-#define PORTA _SFR_IO8(0x02) +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-#define PINB _SFR_IO8(0x03) +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-#define PORTB _SFR_IO8(0x05) +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-#define PORTC _SFR_IO8(0x08) +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-#define PINE _SFR_IO8(0x0C) +-#define PINE7 7 +-#define PINE6 6 +-#define PINE5 5 +-#define PINE4 4 +-#define PINE3 3 +-#define PINE2 2 +-#define PINE1 1 +-#define PINE0 0 +- +-#define DDRE _SFR_IO8(0x0D) +-#define DDE7 7 +-#define DDE6 6 +-#define DDE5 5 +-#define DDE4 4 +-#define DDE3 3 +-#define DDE2 2 +-#define DDE1 1 +-#define DDE0 0 +- +-#define PORTE _SFR_IO8(0x0E) +-#define PE7 7 +-#define PE6 6 +-#define PE5 5 +-#define PE4 4 +-#define PE3 3 +-#define PE2 2 +-#define PE1 1 +-#define PE0 0 +- +-#define PINF _SFR_IO8(0x0F) +-#define PINF7 7 +-#define PINF6 6 +-#define PINF5 5 +-#define PINF4 4 +-#define PINF3 3 +-#define PINF2 2 +-#define PINF1 1 +-#define PINF0 0 +- +-#define DDRF _SFR_IO8(0x10) +-#define DDF7 7 +-#define DDF6 6 +-#define DDF5 5 +-#define DDF4 4 +-#define DDF3 3 +-#define DDF2 2 +-#define DDF1 1 +-#define DDF0 0 +- +-#define PORTF _SFR_IO8(0x11) +-#define PF7 7 +-#define PF6 6 +-#define PF5 5 +-#define PF4 4 +-#define PF3 3 +-#define PF2 2 +-#define PF1 1 +-#define PF0 0 +- +-#define PING _SFR_IO8(0x12) +-#define PING5 5 +-#define PING4 4 +-#define PING3 3 +-#define PING2 2 +-#define PING1 1 +-#define PING0 0 +- +-#define DDRG _SFR_IO8(0x13) +-#define DDG4 4 +-#define DDG3 3 +-#define DDG2 2 +-#define DDG1 1 +-#define DDG0 0 +- +-#define PORTG _SFR_IO8(0x14) +-#define PG4 4 +-#define PG3 3 +-#define PG2 2 +-#define PG1 1 +-#define PG0 0 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define TIFR2 _SFR_IO8(0x17) +-#define TOV2 0 +-#define OCF2A 1 +- +-/* Reserved [0x18..0x1B] */ +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define PCIF0 4 +-#define PCIF1 5 +-#define PCIF2 6 +-#define PCIF3 7 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define PCIE0 4 +-#define PCIE1 5 +-#define PCIE2 6 +-#define PCIE3 7 +- +-#define GPIOR0 _SFR_IO8(0x1E) +- +-#define EECR _SFR_IO8(0x1F) +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-#define EEDR _SFR_IO8(0X20) +- +-/* Combine EEARL and EEARH */ +-#define EEAR _SFR_IO16(0x21) +-#define EEARL _SFR_IO8(0x21) +-#define EEARH _SFR_IO8(0X22) +- +-/* 6-char sequence denoting where to find the EEPROM registers in memory space. +- Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM +- subroutines. +- First two letters: EECR address. +- Second two letters: EEDR address. +- Last two letters: EEAR address. */ +-#define __EEPROM_REG_LOCATIONS__ 1F2021 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSR10 0 +-#define PSR2 1 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM01 3 +-#define COM0A0 4 +-#define COM0A1 5 +-#define WGM00 6 +-#define FOC0A 7 +- +-/* Reserved [0x25] */ +- +-#define TCNT0 _SFR_IO8(0X26) +- +-#define OCR0A _SFR_IO8(0X27) +- +-/* Reserved [0x28..0x29] */ +- +-#define GPIOR1 _SFR_IO8(0x2A) +- +-#define GPIOR2 _SFR_IO8(0x2B) +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0X2E) +- +-/* Reserved [0x2F] */ +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define OCDR _SFR_IO8(0x31) +-#define OCDR0 0 +-#define OCDR1 1 +-#define OCDR2 2 +-#define OCDR3 3 +-#define OCDR4 4 +-#define OCDR5 5 +-#define OCDR6 6 +-#define OCDR7 7 +-#define IDRD 7 +- +-/* Reserved [0x32] */ +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +-#define JTRF 4 +- +-#define MCUCR _SFR_IO8(0X35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#if defined(__AVR_ATmega3290P__) +-#define BODSE 5 +-#define BODS 6 +-#endif +-#define JTD 7 +- +-/* Reserved [0x36] */ +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define RWWSB 6 +-#define SPMIE 7 +- +-/* Reserved [0x38..0x3C] */ +- +-/* SP [0x3D..0x3E] */ +-/* SREG [0x3F] */ +- +-#define WDTCR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-/* Reserved [0x62..0x63] */ +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM1 3 +-#define PRLCD 4 +- +-/* Reserved [0x65] */ +- +-#define OSCCAL _SFR_MEM8(0x66) +- +-/* Reserved [0x67..0x68] */ +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +- +-/* Reserved [0x6A] */ +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-#define PCMSK2 _SFR_MEM8(0x6D) +-#define PCINT16 0 +-#define PCINT17 1 +-#define PCINT18 2 +-#define PCINT19 3 +-#define PCINT20 4 +-#define PCINT21 5 +-#define PCINT22 6 +-#define PCINT23 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define TIMSK2 _SFR_MEM8(0x70) +-#define TOIE2 0 +-#define OCIE2A 1 +- +-/* Reserved [0x71..0x72] */ +- +-#define PCMSK3 _SFR_MEM8(0x73) +-#define PCINT24 0 +-#define PCINT25 1 +-#define PCINT26 2 +-#define PCINT27 3 +-#define PCINT28 4 +-#define PCINT29 5 +-#define PCINT30 6 +- +-/* Reserved [0x74..0x77] */ +- +-/* Combine ADCL and ADCH */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +-#define ADCL _SFR_MEM8(0x78) +-#define ADCH _SFR_MEM8(0x79) +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ACME 6 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-/* Reserved [0x7D] */ +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0X80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0X81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-/* Reserved [0x83] */ +- +-/* Combine TCNT1L and TCNT1H */ +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1H _SFR_MEM8(0x85) +- +-/* Combine ICR1L and ICR1H */ +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1H _SFR_MEM8(0x87) +- +-/* Combine OCR1AL and OCR1AH */ +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AH _SFR_MEM8(0x89) +- +-/* Combine OCR1BL and OCR1BH */ +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BH _SFR_MEM8(0x8B) +- +-/* Reserved [0x8C..0xAF] */ +- +-#define TCCR2A _SFR_MEM8(0xB0) +-#define CS20 0 +-#define CS21 1 +-#define CS22 2 +-#define WGM21 3 +-#define COM2A0 4 +-#define COM2A1 5 +-#define WGM20 6 +-#define FOC2A 7 +- +-/* Reserved [0xB1] */ +- +-#define TCNT2 _SFR_MEM8(0xB2) +- +-#define OCR2A _SFR_MEM8(0xB3) +- +-/* Reserved [0xB4..0xB5] */ +- +-#define ASSR _SFR_MEM8(0xB6) +-#define TCR2UB 0 +-#define OCR2UB 1 +-#define TCN2UB 2 +-#define AS2 3 +-#define EXCLK 4 +- +-/* Reserved [0xB7] */ +- +-#define USICR _SFR_MEM8(0xB8) +-#define USITC 0 +-#define USICLK 1 +-#define USICS0 2 +-#define USICS1 3 +-#define USIWM0 4 +-#define USIWM1 5 +-#define USIOIE 6 +-#define USISIE 7 +- +-#define USISR _SFR_MEM8(0xB9) +-#define USICNT0 0 +-#define USICNT1 1 +-#define USICNT2 2 +-#define USICNT3 3 +-#define USIDC 4 +-#define USIPF 5 +-#define USIOIF 6 +-#define USISIF 7 +- +-#define USIDR _SFR_MEM8(0xBA) +- +-/* Reserved [0xBB..0xBF] */ +- +-#define UCSR0A _SFR_MEM8(0xC0) +-#define MPCM0 0 +-#define U2X0 1 +-#define UPE0 2 +-#define DOR0 3 +-#define FE0 4 +-#define UDRE0 5 +-#define TXC0 6 +-#define RXC0 7 +- +-#define UCSR0B _SFR_MEM8(0XC1) +-#define TXB80 0 +-#define RXB80 1 +-#define UCSZ02 2 +-#define TXEN0 3 +-#define RXEN0 4 +-#define UDRIE0 5 +-#define TXCIE0 6 +-#define RXCIE0 7 +- +-#define UCSR0C _SFR_MEM8(0xC2) +-#define UCPOL0 0 +-#define UCSZ00 1 +-#define UCSZ01 2 +-#define USBS0 3 +-#define UPM00 4 +-#define UPM01 5 +-#define UMSEL0 6 +- +-/* Reserved [0xC3] */ +- +-/* Combine UBRR0L and UBRR0H */ +-#define UBRR0 _SFR_MEM16(0xC4) +- +-#define UBRR0L _SFR_MEM8(0xC4) +-#define UBRR0H _SFR_MEM8(0xC5) +- +-#define UDR0 _SFR_MEM8(0XC6) +- +-/* Reserved [0xC7..0xD7] */ +- +-#define PINH _SFR_MEM8(0xD8) +-#define PINH7 7 +-#define PINH6 6 +-#define PINH5 5 +-#define PINH4 4 +-#define PINH3 3 +-#define PINH2 2 +-#define PINH1 1 +-#define PINH0 0 +- +-#define DDRH _SFR_MEM8(0xD9) +-#define DDH7 7 +-#define DDH6 6 +-#define DDH5 5 +-#define DDH4 4 +-#define DDH3 3 +-#define DDH2 2 +-#define DDH1 1 +-#define DDH0 0 +- +-#define PORTH _SFR_MEM8(0xDA) +-#define PH7 7 +-#define PH6 6 +-#define PH5 5 +-#define PH4 4 +-#define PH3 3 +-#define PH2 2 +-#define PH1 1 +-#define PH0 0 +- +-#define PINJ _SFR_MEM8(0xDB) +-#define PINJ6 6 +-#define PINJ5 5 +-#define PINJ4 4 +-#define PINJ3 3 +-#define PINJ2 2 +-#define PINJ1 1 +-#define PINJ0 0 +- +-#define DDRJ _SFR_MEM8(0xDC) +-#define DDJ6 6 +-#define DDJ5 5 +-#define DDJ4 4 +-#define DDJ3 3 +-#define DDJ2 2 +-#define DDJ1 1 +-#define DDJ0 0 +- +-#define PORTJ _SFR_MEM8(0xDD) +-#define PJ6 6 +-#define PJ5 5 +-#define PJ4 4 +-#define PJ3 3 +-#define PJ2 2 +-#define PJ1 1 +-#define PJ0 0 +- +-/* Reserved [0xDE..0xE3] */ +- +-#define LCDCRA _SFR_MEM8(0XE4) +-#define LCDBL 0 +-#if defined(__AVR_ATmega3290P__) +-#define LCDCCD 1 +-#define LCDBD 2 +-#endif +-#define LCDIE 3 +-#define LCDIF 4 +-#define LCDAB 6 +-#define LCDEN 7 +- +-#define LCDCRB _SFR_MEM8(0XE5) +-#define LCDPM0 0 +-#define LCDPM1 1 +-#define LCDPM2 2 +-#define LCDPM3 3 +-#define LCDMUX0 4 +-#define LCDMUX1 5 +-#define LCD2B 6 +-#define LCDCS 7 +- +-#define LCDFRR _SFR_MEM8(0XE6) +-#define LCDCD0 0 +-#define LCDCD1 1 +-#define LCDCD2 2 +-#define LCDPS0 4 +-#define LCDPS1 5 +-#define LCDPS2 6 +- +-#define LCDCCR _SFR_MEM8(0XE7) +-#define LCDCC0 0 +-#define LCDCC1 1 +-#define LCDCC2 2 +-#define LCDCC3 3 +-#if defined(__AVR_ATmega3290P__) +-#define LCDMDT 4 +-#endif +-#define LCDDC0 5 +-#define LCDDC1 6 +-#define LCDDC2 7 +- +-/* Reserved [0xE8..0xEB] */ +- +-#define LCDDR00 _SFR_MEM8(0XEC) +-#define SEG000 0 +-#define SEG001 1 +-#define SEG002 2 +-#define SEG003 3 +-#define SEG004 4 +-#define SEG005 5 +-#define SEG006 6 +-#define SEG007 7 +- +-#define LCDDR01 _SFR_MEM8(0XED) +-#define SEG008 0 +-#define SEG009 1 +-#define SEG010 2 +-#define SEG011 3 +-#define SEG012 4 +-#define SEG013 5 +-#define SEG014 6 +-#define SEG015 7 +- +-#define LCDDR02 _SFR_MEM8(0XEE) +-#define SEG016 0 +-#define SEG017 1 +-#define SEG018 2 +-#define SEG019 3 +-#define SEG020 4 +-#define SEG021 5 +-#define SEG022 6 +-#define SEG023 7 +- +-#define LCDDR03 _SFR_MEM8(0XEF) +-#define SEG024 0 +-#define SEG025 1 +-#define SEG026 2 +-#define SEG027 3 +-#define SEG028 4 +-#define SEG029 5 +-#define SEG030 6 +-#define SEG031 7 +- +-#define LCDDR04 _SFR_MEM8(0XF0) +-#define SEG032 0 +-#define SEG033 1 +-#define SEG034 2 +-#define SEG035 3 +-#define SEG036 4 +-#define SEG037 5 +-#define SEG038 6 +-#define SEG039 7 +- +-#define LCDDR05 _SFR_MEM8(0XF1) +-#define SEG100 0 +-#define SEG101 1 +-#define SEG102 2 +-#define SEG103 3 +-#define SEG104 4 +-#define SEG105 5 +-#define SEG106 6 +-#define SEG107 7 +- +-#define LCDDR06 _SFR_MEM8(0XF2) +-#define SEG108 0 +-#define SEG109 1 +-#define SEG110 2 +-#define SEG111 3 +-#define SEG112 4 +-#define SEG113 5 +-#define SEG114 6 +-#define SEG115 7 +- +-#define LCDDR07 _SFR_MEM8(0XF3) +-#define SEG116 0 +-#define SEG117 1 +-#define SEG118 2 +-#define SEG119 3 +-#define SEG120 4 +-#define SEG121 5 +-#define SEG122 6 +-#define SEG123 7 +- +-#define LCDDR08 _SFR_MEM8(0XF4) +-#define SEG124 0 +-#define SEG125 1 +-#define SEG126 2 +-#define SEG127 3 +-#define SEG128 4 +-#define SEG129 5 +-#define SEG130 6 +-#define SEG131 7 +- +-#define LCDDR09 _SFR_MEM8(0XF5) +-#define SEG132 0 +-#define SEG133 1 +-#define SEG134 2 +-#define SEG135 3 +-#define SEG136 4 +-#define SEG137 5 +-#define SEG138 6 +-#define SEG139 7 +- +-#define LCDDR10 _SFR_MEM8(0XF6) +-#define SEG200 0 +-#define SEG201 1 +-#define SEG202 2 +-#define SEG203 3 +-#define SEG204 4 +-#define SEG205 5 +-#define SEG206 6 +-#define SEG207 7 +- +-#define LCDDR11 _SFR_MEM8(0XF7) +-#define SEG208 0 +-#define SEG209 1 +-#define SEG210 2 +-#define SEG211 3 +-#define SEG212 4 +-#define SEG213 5 +-#define SEG214 6 +-#define SEG215 7 +- +-#define LCDDR12 _SFR_MEM8(0XF8) +-#define SEG216 0 +-#define SEG217 1 +-#define SEG218 2 +-#define SEG219 3 +-#define SEG220 4 +-#define SEG221 5 +-#define SEG222 6 +-#define SEG223 7 +- +-#define LCDDR13 _SFR_MEM8(0XF9) +-#define SEG224 0 +-#define SEG225 1 +-#define SEG226 2 +-#define SEG227 3 +-#define SEG228 4 +-#define SEG229 5 +-#define SEG230 6 +-#define SEG231 7 +- +-#define LCDDR14 _SFR_MEM8(0XFA) +-#define SEG232 0 +-#define SEG233 1 +-#define SEG234 2 +-#define SEG235 3 +-#define SEG236 4 +-#define SEG237 5 +-#define SEG238 6 +-#define SEG239 7 +- +-#define LCDDR15 _SFR_MEM8(0XFB) +-#define SEG300 0 +-#define SEG301 1 +-#define SEG302 2 +-#define SEG303 3 +-#define SEG304 4 +-#define SEG305 5 +-#define SEG306 6 +-#define SEG307 7 +- +-#define LCDDR16 _SFR_MEM8(0XFC) +-#define SEG308 0 +-#define SEG309 1 +-#define SEG310 2 +-#define SEG311 3 +-#define SEG312 4 +-#define SEG313 5 +-#define SEG314 6 +-#define SEG315 7 +- +-#define LCDDR17 _SFR_MEM8(0XFD) +-#define SEG316 0 +-#define SEG217 1 +-#define SEG318 2 +-#define SEG319 3 +-#define SEG320 4 +-#define SEG321 5 +-#define SEG322 6 +-#define SEG323 7 +- +-#define LCDDR18 _SFR_MEM8(0XFE) +-#define SEG324 0 +-#define SEG325 1 +-#define SEG326 2 +-#define SEG327 3 +-#define SEG328 4 +-#define SEG329 5 +-#define SEG330 6 +-#define SEG331 7 +- +-#define LCDDR19 _SFR_MEM8(0XFF) +-#define SEG332 0 +-#define SEG333 1 +-#define SEG334 2 +-#define SEG335 3 +-#define SEG336 4 +-#define SEG337 5 +-#define SEG338 6 +-#define SEG339 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* Pin Change Interrupt Request 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) +-#define SIG_PIN_CHANGE0 _VECTOR(2) +- +-/* Pin Change Interrupt Request 1 */ +-#define PCINT1_vect_num 3 +-#define PCINT1_vect _VECTOR(3) +-#define SIG_PIN_CHANGE1 _VECTOR(3) +- +-/* Timer/Counter2 Compare Match */ +-#define TIMER2_COMP_vect_num 4 +-#define TIMER2_COMP_vect _VECTOR(4) +-#define SIG_OUTPUT_COMPARE2 _VECTOR(4) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 5 +-#define TIMER2_OVF_vect _VECTOR(5) +-#define SIG_OVERFLOW2 _VECTOR(5) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 6 +-#define TIMER1_CAPT_vect _VECTOR(6) +-#define SIG_INPUT_CAPTURE1 _VECTOR(6) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 7 +-#define TIMER1_COMPA_vect _VECTOR(7) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(7) +- +-/* Timer/Counter Compare Match B */ +-#define TIMER1_COMPB_vect_num 8 +-#define TIMER1_COMPB_vect _VECTOR(8) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(8) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 9 +-#define TIMER1_OVF_vect _VECTOR(9) +-#define SIG_OVERFLOW1 _VECTOR(9) +- +-/* Timer/Counter0 Compare Match */ +-#define TIMER0_COMP_vect_num 10 +-#define TIMER0_COMP_vect _VECTOR(10) +-#define SIG_OUTPUT_COMPARE0 _VECTOR(10) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 11 +-#define TIMER0_OVF_vect _VECTOR(11) +-#define SIG_OVERFLOW0 _VECTOR(11) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 12 +-#define SPI_STC_vect _VECTOR(12) +-#define SIG_SPI _VECTOR(12) +- +-/* USART, Rx Complete */ +-#define USART_RX_vect_num 13 +-#define USART_RX_vect _VECTOR(13) +-#define SIG_UART_RECV _VECTOR(13) +- +-/* USART Data register Empty */ +-#define USART_UDRE_vect_num 14 +-#define USART_UDRE_vect _VECTOR(14) +-#define SIG_UART_DATA _VECTOR(14) +- +-/* USART0, Tx Complete */ +-#define USART0_TX_vect_num 15 +-#define USART0_TX_vect _VECTOR(15) +-#define SIG_UART_TRANS _VECTOR(15) +- +-/* USI Start Condition */ +-#define USI_START_vect_num 16 +-#define USI_START_vect _VECTOR(16) +-#define SIG_USI_START _VECTOR(16) +- +-/* USI Overflow */ +-#define USI_OVERFLOW_vect_num 17 +-#define USI_OVERFLOW_vect _VECTOR(17) +-#define SIG_USI_OVERFLOW _VECTOR(17) +- +-/* Analog Comparator */ +-#define ANALOG_COMP_vect_num 18 +-#define ANALOG_COMP_vect _VECTOR(18) +-#define SIG_COMPARATOR _VECTOR(18) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 19 +-#define ADC_vect _VECTOR(19) +-#define SIG_ADC _VECTOR(19) +- +-/* EEPROM Ready */ +-#define EE_READY_vect_num 20 +-#define EE_READY_vect _VECTOR(20) +-#define SIG_EEPROM_READY _VECTOR(20) +- +-/* Store Program Memory Read */ +-#define SPM_READY_vect_num 21 +-#define SPM_READY_vect _VECTOR(21) +-#define SIG_SPM_READY _VECTOR(21) +- +-/* LCD Start of Frame */ +-#define LCD_vect_num 22 +-#define LCD_vect _VECTOR(22) +-#define SIG_LCD _VECTOR(22) +- +-/* Pin Change Interrupt Request 2 */ +-#define PCINT2_vect_num 23 +-#define PCINT2_vect _VECTOR(23) +-#define SIG_PIN_CHANGE2 _VECTOR(23) +- +-/* Pin Change Interrupt Request 3 */ +-#define PCINT3_vect_num 24 +-#define PCINT3_vect _VECTOR(24) +-#define SIG_PIN_CHANGE3 _VECTOR(24) +- +-#define _VECTORS_SIZE 100 +- +- +-/* Constants */ +-#define SPM_PAGESIZE 128 +-#define RAMEND 0x8FF +-#define XRAMEND RAMEND +-#define E2END 0x3FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x7FFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x95 +-#define SIGNATURE_2 0x04 +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_PIN_CHANGE0 +-#pragma GCC poison SIG_PIN_CHANGE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE2 +-#pragma GCC poison SIG_OVERFLOW2 +-#pragma GCC poison SIG_INPUT_CAPTURE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OUTPUT_COMPARE0 +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_SPI +-#pragma GCC poison SIG_UART_RECV +-#pragma GCC poison SIG_UART_DATA +-#pragma GCC poison SIG_UART_TRANS +-#pragma GCC poison SIG_USI_START +-#pragma GCC poison SIG_USI_OVERFLOW +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_ADC +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_SPM_READY +-#pragma GCC poison SIG_LCD +-#pragma GCC poison SIG_PIN_CHANGE2 +-#pragma GCC poison SIG_PIN_CHANGE3 +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +- +-#endif /* _AVR_IOM3290_H_ */ ++/* Copyright (c) 2004 Eric B. Weddington ++ Copyright (c) 2005, 2006, 2007 Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* avr/iom3290.h - definitions for ATmega3290 and ATmega3290P. */ ++ ++#ifndef _AVR_IOM3290_H_ ++#define _AVR_IOM3290_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom3290.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE7 7 ++#define DDE6 6 ++#define DDE5 5 ++#define DDE4 4 ++#define DDE3 3 ++#define DDE2 2 ++#define DDE1 1 ++#define DDE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PE7 7 ++#define PE6 6 ++#define PE5 5 ++#define PE4 4 ++#define PE3 3 ++#define PE2 2 ++#define PE1 1 ++#define PE0 0 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDF7 7 ++#define DDF6 6 ++#define DDF5 5 ++#define DDF4 4 ++#define DDF3 3 ++#define DDF2 2 ++#define DDF1 1 ++#define DDF0 0 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PF7 7 ++#define PF6 6 ++#define PF5 5 ++#define PF4 4 ++#define PF3 3 ++#define PF2 2 ++#define PF1 1 ++#define PF0 0 ++ ++#define PING _SFR_IO8(0x12) ++#define PING5 5 ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++#define DDRG _SFR_IO8(0x13) ++#define DDG4 4 ++#define DDG3 3 ++#define DDG2 2 ++#define DDG1 1 ++#define DDG0 0 ++ ++#define PORTG _SFR_IO8(0x14) ++#define PG4 4 ++#define PG3 3 ++#define PG2 2 ++#define PG1 1 ++#define PG0 0 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++ ++/* Reserved [0x18..0x1B] */ ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define PCIF0 4 ++#define PCIF1 5 ++#define PCIF2 6 ++#define PCIF3 7 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define PCIE0 4 ++#define PCIE1 5 ++#define PCIE2 6 ++#define PCIE3 7 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++#define EEDR _SFR_IO8(0X20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0X22) ++ ++/* 6-char sequence denoting where to find the EEPROM registers in memory space. ++ Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM ++ subroutines. ++ First two letters: EECR address. ++ Second two letters: EEDR address. ++ Last two letters: EEAR address. */ ++#define __EEPROM_REG_LOCATIONS__ 1F2021 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR10 0 ++#define PSR2 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM01 3 ++#define COM0A0 4 ++#define COM0A1 5 ++#define WGM00 6 ++#define FOC0A 7 ++ ++/* Reserved [0x25] */ ++ ++#define TCNT0 _SFR_IO8(0X26) ++ ++#define OCR0A _SFR_IO8(0X27) ++ ++/* Reserved [0x28..0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0X2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCDR7 7 ++#define IDRD 7 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define JTRF 4 ++ ++#define MCUCR _SFR_IO8(0X35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#if defined(__AVR_ATmega3290P__) ++#define BODSE 5 ++#define BODS 6 ++#endif ++#define JTD 7 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++/* SREG [0x3F] */ ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRLCD 4 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++ ++/* Reserved [0x67..0x68] */ ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++ ++/* Reserved [0x71..0x72] */ ++ ++#define PCMSK3 _SFR_MEM8(0x73) ++#define PCINT24 0 ++#define PCINT25 1 ++#define PCINT26 2 ++#define PCINT27 3 ++#define PCINT28 4 ++#define PCINT29 5 ++#define PCINT30 6 ++ ++/* Reserved [0x74..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0X80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0X81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM21 3 ++#define COM2A0 4 ++#define COM2A1 5 ++#define WGM20 6 ++#define FOC2A 7 ++ ++/* Reserved [0xB1] */ ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++/* Reserved [0xB4..0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2UB 0 ++#define OCR2UB 1 ++#define TCN2UB 2 ++#define AS2 3 ++#define EXCLK 4 ++ ++/* Reserved [0xB7] */ ++ ++#define USICR _SFR_MEM8(0xB8) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_MEM8(0xB9) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_MEM8(0xBA) ++ ++/* Reserved [0xBB..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0XC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL0 6 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0XC6) ++ ++/* Reserved [0xC7..0xD7] */ ++ ++#define PINH _SFR_MEM8(0xD8) ++#define PINH7 7 ++#define PINH6 6 ++#define PINH5 5 ++#define PINH4 4 ++#define PINH3 3 ++#define PINH2 2 ++#define PINH1 1 ++#define PINH0 0 ++ ++#define DDRH _SFR_MEM8(0xD9) ++#define DDH7 7 ++#define DDH6 6 ++#define DDH5 5 ++#define DDH4 4 ++#define DDH3 3 ++#define DDH2 2 ++#define DDH1 1 ++#define DDH0 0 ++ ++#define PORTH _SFR_MEM8(0xDA) ++#define PH7 7 ++#define PH6 6 ++#define PH5 5 ++#define PH4 4 ++#define PH3 3 ++#define PH2 2 ++#define PH1 1 ++#define PH0 0 ++ ++#define PINJ _SFR_MEM8(0xDB) ++#define PINJ6 6 ++#define PINJ5 5 ++#define PINJ4 4 ++#define PINJ3 3 ++#define PINJ2 2 ++#define PINJ1 1 ++#define PINJ0 0 ++ ++#define DDRJ _SFR_MEM8(0xDC) ++#define DDJ6 6 ++#define DDJ5 5 ++#define DDJ4 4 ++#define DDJ3 3 ++#define DDJ2 2 ++#define DDJ1 1 ++#define DDJ0 0 ++ ++#define PORTJ _SFR_MEM8(0xDD) ++#define PJ6 6 ++#define PJ5 5 ++#define PJ4 4 ++#define PJ3 3 ++#define PJ2 2 ++#define PJ1 1 ++#define PJ0 0 ++ ++/* Reserved [0xDE..0xE3] */ ++ ++#define LCDCRA _SFR_MEM8(0XE4) ++#define LCDBL 0 ++#if defined(__AVR_ATmega3290P__) ++#define LCDCCD 1 ++#define LCDBD 2 ++#endif ++#define LCDIE 3 ++#define LCDIF 4 ++#define LCDAB 6 ++#define LCDEN 7 ++ ++#define LCDCRB _SFR_MEM8(0XE5) ++#define LCDPM0 0 ++#define LCDPM1 1 ++#define LCDPM2 2 ++#define LCDPM3 3 ++#define LCDMUX0 4 ++#define LCDMUX1 5 ++#define LCD2B 6 ++#define LCDCS 7 ++ ++#define LCDFRR _SFR_MEM8(0XE6) ++#define LCDCD0 0 ++#define LCDCD1 1 ++#define LCDCD2 2 ++#define LCDPS0 4 ++#define LCDPS1 5 ++#define LCDPS2 6 ++ ++#define LCDCCR _SFR_MEM8(0XE7) ++#define LCDCC0 0 ++#define LCDCC1 1 ++#define LCDCC2 2 ++#define LCDCC3 3 ++#if defined(__AVR_ATmega3290P__) ++#define LCDMDT 4 ++#endif ++#define LCDDC0 5 ++#define LCDDC1 6 ++#define LCDDC2 7 ++ ++/* Reserved [0xE8..0xEB] */ ++ ++#define LCDDR00 _SFR_MEM8(0XEC) ++#define SEG000 0 ++#define SEG001 1 ++#define SEG002 2 ++#define SEG003 3 ++#define SEG004 4 ++#define SEG005 5 ++#define SEG006 6 ++#define SEG007 7 ++ ++#define LCDDR01 _SFR_MEM8(0XED) ++#define SEG008 0 ++#define SEG009 1 ++#define SEG010 2 ++#define SEG011 3 ++#define SEG012 4 ++#define SEG013 5 ++#define SEG014 6 ++#define SEG015 7 ++ ++#define LCDDR02 _SFR_MEM8(0XEE) ++#define SEG016 0 ++#define SEG017 1 ++#define SEG018 2 ++#define SEG019 3 ++#define SEG020 4 ++#define SEG021 5 ++#define SEG022 6 ++#define SEG023 7 ++ ++#define LCDDR03 _SFR_MEM8(0XEF) ++#define SEG024 0 ++#define SEG025 1 ++#define SEG026 2 ++#define SEG027 3 ++#define SEG028 4 ++#define SEG029 5 ++#define SEG030 6 ++#define SEG031 7 ++ ++#define LCDDR04 _SFR_MEM8(0XF0) ++#define SEG032 0 ++#define SEG033 1 ++#define SEG034 2 ++#define SEG035 3 ++#define SEG036 4 ++#define SEG037 5 ++#define SEG038 6 ++#define SEG039 7 ++ ++#define LCDDR05 _SFR_MEM8(0XF1) ++#define SEG100 0 ++#define SEG101 1 ++#define SEG102 2 ++#define SEG103 3 ++#define SEG104 4 ++#define SEG105 5 ++#define SEG106 6 ++#define SEG107 7 ++ ++#define LCDDR06 _SFR_MEM8(0XF2) ++#define SEG108 0 ++#define SEG109 1 ++#define SEG110 2 ++#define SEG111 3 ++#define SEG112 4 ++#define SEG113 5 ++#define SEG114 6 ++#define SEG115 7 ++ ++#define LCDDR07 _SFR_MEM8(0XF3) ++#define SEG116 0 ++#define SEG117 1 ++#define SEG118 2 ++#define SEG119 3 ++#define SEG120 4 ++#define SEG121 5 ++#define SEG122 6 ++#define SEG123 7 ++ ++#define LCDDR08 _SFR_MEM8(0XF4) ++#define SEG124 0 ++#define SEG125 1 ++#define SEG126 2 ++#define SEG127 3 ++#define SEG128 4 ++#define SEG129 5 ++#define SEG130 6 ++#define SEG131 7 ++ ++#define LCDDR09 _SFR_MEM8(0XF5) ++#define SEG132 0 ++#define SEG133 1 ++#define SEG134 2 ++#define SEG135 3 ++#define SEG136 4 ++#define SEG137 5 ++#define SEG138 6 ++#define SEG139 7 ++ ++#define LCDDR10 _SFR_MEM8(0XF6) ++#define SEG200 0 ++#define SEG201 1 ++#define SEG202 2 ++#define SEG203 3 ++#define SEG204 4 ++#define SEG205 5 ++#define SEG206 6 ++#define SEG207 7 ++ ++#define LCDDR11 _SFR_MEM8(0XF7) ++#define SEG208 0 ++#define SEG209 1 ++#define SEG210 2 ++#define SEG211 3 ++#define SEG212 4 ++#define SEG213 5 ++#define SEG214 6 ++#define SEG215 7 ++ ++#define LCDDR12 _SFR_MEM8(0XF8) ++#define SEG216 0 ++#define SEG217 1 ++#define SEG218 2 ++#define SEG219 3 ++#define SEG220 4 ++#define SEG221 5 ++#define SEG222 6 ++#define SEG223 7 ++ ++#define LCDDR13 _SFR_MEM8(0XF9) ++#define SEG224 0 ++#define SEG225 1 ++#define SEG226 2 ++#define SEG227 3 ++#define SEG228 4 ++#define SEG229 5 ++#define SEG230 6 ++#define SEG231 7 ++ ++#define LCDDR14 _SFR_MEM8(0XFA) ++#define SEG232 0 ++#define SEG233 1 ++#define SEG234 2 ++#define SEG235 3 ++#define SEG236 4 ++#define SEG237 5 ++#define SEG238 6 ++#define SEG239 7 ++ ++#define LCDDR15 _SFR_MEM8(0XFB) ++#define SEG300 0 ++#define SEG301 1 ++#define SEG302 2 ++#define SEG303 3 ++#define SEG304 4 ++#define SEG305 5 ++#define SEG306 6 ++#define SEG307 7 ++ ++#define LCDDR16 _SFR_MEM8(0XFC) ++#define SEG308 0 ++#define SEG309 1 ++#define SEG310 2 ++#define SEG311 3 ++#define SEG312 4 ++#define SEG313 5 ++#define SEG314 6 ++#define SEG315 7 ++ ++#define LCDDR17 _SFR_MEM8(0XFD) ++#define SEG316 0 ++#define SEG217 1 ++#define SEG318 2 ++#define SEG319 3 ++#define SEG320 4 ++#define SEG321 5 ++#define SEG322 6 ++#define SEG323 7 ++ ++#define LCDDR18 _SFR_MEM8(0XFE) ++#define SEG324 0 ++#define SEG325 1 ++#define SEG326 2 ++#define SEG327 3 ++#define SEG328 4 ++#define SEG329 5 ++#define SEG330 6 ++#define SEG331 7 ++ ++#define LCDDR19 _SFR_MEM8(0XFF) ++#define SEG332 0 ++#define SEG333 1 ++#define SEG334 2 ++#define SEG335 3 ++#define SEG336 4 ++#define SEG337 5 ++#define SEG338 6 ++#define SEG339 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) ++#define SIG_PIN_CHANGE0 _VECTOR(2) ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect_num 3 ++#define PCINT1_vect _VECTOR(3) ++#define SIG_PIN_CHANGE1 _VECTOR(3) ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect_num 4 ++#define TIMER2_COMP_vect _VECTOR(4) ++#define SIG_OUTPUT_COMPARE2 _VECTOR(4) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 5 ++#define TIMER2_OVF_vect _VECTOR(5) ++#define SIG_OVERFLOW2 _VECTOR(5) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 6 ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define SIG_INPUT_CAPTURE1 _VECTOR(6) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 7 ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(7) ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect_num 8 ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(8) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 9 ++#define TIMER1_OVF_vect _VECTOR(9) ++#define SIG_OVERFLOW1 _VECTOR(9) ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect_num 10 ++#define TIMER0_COMP_vect _VECTOR(10) ++#define SIG_OUTPUT_COMPARE0 _VECTOR(10) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 11 ++#define TIMER0_OVF_vect _VECTOR(11) ++#define SIG_OVERFLOW0 _VECTOR(11) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 12 ++#define SPI_STC_vect _VECTOR(12) ++#define SIG_SPI _VECTOR(12) ++ ++/* USART, Rx Complete */ ++#define USART_RX_vect_num 13 ++#define USART_RX_vect _VECTOR(13) ++#define SIG_UART_RECV _VECTOR(13) ++ ++/* USART Data register Empty */ ++#define USART_UDRE_vect_num 14 ++#define USART_UDRE_vect _VECTOR(14) ++#define SIG_UART_DATA _VECTOR(14) ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect_num 15 ++#define USART0_TX_vect _VECTOR(15) ++#define SIG_UART_TRANS _VECTOR(15) ++ ++/* USI Start Condition */ ++#define USI_START_vect_num 16 ++#define USI_START_vect _VECTOR(16) ++#define SIG_USI_START _VECTOR(16) ++ ++/* USI Overflow */ ++#define USI_OVERFLOW_vect_num 17 ++#define USI_OVERFLOW_vect _VECTOR(17) ++#define SIG_USI_OVERFLOW _VECTOR(17) ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect_num 18 ++#define ANALOG_COMP_vect _VECTOR(18) ++#define SIG_COMPARATOR _VECTOR(18) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 19 ++#define ADC_vect _VECTOR(19) ++#define SIG_ADC _VECTOR(19) ++ ++/* EEPROM Ready */ ++#define EE_READY_vect_num 20 ++#define EE_READY_vect _VECTOR(20) ++#define SIG_EEPROM_READY _VECTOR(20) ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect_num 21 ++#define SPM_READY_vect _VECTOR(21) ++#define SIG_SPM_READY _VECTOR(21) ++ ++/* LCD Start of Frame */ ++#define LCD_vect_num 22 ++#define LCD_vect _VECTOR(22) ++#define SIG_LCD _VECTOR(22) ++ ++/* Pin Change Interrupt Request 2 */ ++#define PCINT2_vect_num 23 ++#define PCINT2_vect _VECTOR(23) ++#define SIG_PIN_CHANGE2 _VECTOR(23) ++ ++/* Pin Change Interrupt Request 3 */ ++#define PCINT3_vect_num 24 ++#define PCINT3_vect _VECTOR(24) ++#define SIG_PIN_CHANGE3 _VECTOR(24) ++ ++#define _VECTORS_SIZE 100 ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE 128 ++#define RAMSTART 0x100 ++#define RAMEND 0x8FF ++#define XRAMEND RAMEND ++#define E2END 0x3FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x7FFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x04 ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_PIN_CHANGE0 ++#pragma GCC poison SIG_PIN_CHANGE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE2 ++#pragma GCC poison SIG_OVERFLOW2 ++#pragma GCC poison SIG_INPUT_CAPTURE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OUTPUT_COMPARE0 ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_SPI ++#pragma GCC poison SIG_UART_RECV ++#pragma GCC poison SIG_UART_DATA ++#pragma GCC poison SIG_UART_TRANS ++#pragma GCC poison SIG_USI_START ++#pragma GCC poison SIG_USI_OVERFLOW ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_ADC ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_SPM_READY ++#pragma GCC poison SIG_LCD ++#pragma GCC poison SIG_PIN_CHANGE2 ++#pragma GCC poison SIG_PIN_CHANGE3 ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++ ++#endif /* _AVR_IOM3290_H_ */ +diff --git a/include/avr/iom3290a.h b/include/avr/iom3290a.h +new file mode 100644 +index 0000000..90dbbf1 +--- /dev/null ++++ b/include/avr/iom3290a.h +@@ -0,0 +1,34 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2011 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++#include "iom3290.h" +diff --git a/include/avr/iom3290p.h b/include/avr/iom3290p.h +new file mode 100644 +index 0000000..90dbbf1 +--- /dev/null ++++ b/include/avr/iom3290p.h +@@ -0,0 +1,34 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2011 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++#include "iom3290.h" +diff --git a/include/avr/iom3290pa.h b/include/avr/iom3290pa.h +new file mode 100644 +index 0000000..0d38242 +--- /dev/null ++++ b/include/avr/iom3290pa.h +@@ -0,0 +1,965 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATMEGA3290PA_H_INCLUDED ++#define _AVR_ATMEGA3290PA_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom3290pa.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDRA7 7 ++#define DDRA6 6 ++#define DDRA5 5 ++#define DDRA4 4 ++#define DDRA3 3 ++#define DDRA2 2 ++#define DDRA1 1 ++#define DDRA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDRC7 7 ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC7 7 ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDRE7 7 ++#define DDRE6 6 ++#define DDRE5 5 ++#define DDRE4 4 ++#define DDRE3 3 ++#define DDRE2 2 ++#define DDRE1 1 ++#define DDRE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE7 7 ++#define PORTE6 6 ++#define PORTE5 5 ++#define PORTE4 4 ++#define PORTE3 3 ++#define PORTE2 2 ++#define PORTE1 1 ++#define PORTE0 0 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDRF7 7 ++#define DDRF6 6 ++#define DDRF5 5 ++#define DDRF4 4 ++#define DDRF3 3 ++#define DDRF2 2 ++#define DDRF1 1 ++#define DDRF0 0 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PORTF7 7 ++#define PORTF6 6 ++#define PORTF5 5 ++#define PORTF4 4 ++#define PORTF3 3 ++#define PORTF2 2 ++#define PORTF1 1 ++#define PORTF0 0 ++ ++#define PING _SFR_IO8(0x12) ++#define PING5 5 ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++#define DDRG _SFR_IO8(0x13) ++#define DDRG4 4 ++#define DDRG3 3 ++#define DDRG2 2 ++#define DDRG1 1 ++#define DDRG0 0 ++ ++#define PORTG _SFR_IO8(0x14) ++#define PORTG4 4 ++#define PORTG3 3 ++#define PORTG2 2 ++#define PORTG1 1 ++#define PORTG0 0 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++ ++/* Reserved [0x18..0x1B] */ ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define PCIF0 4 ++#define PCIF1 5 ++#define PCIF2 6 ++#define PCIF3 7 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define PCIE0 4 ++#define PCIE1 5 ++#define PCIE2 6 ++#define PCIE3 7 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR310 0 ++#define TSM 7 ++#define PSR2 1 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM01 3 ++#define COM0A0 4 ++#define COM0A1 5 ++#define WGM00 6 ++#define FOC0A 7 ++ ++/* Reserved [0x25] */ ++ ++#define TCNT0 _SFR_IO8(0x26) ++ ++#define OCR0A _SFR_IO8(0x27) ++ ++/* Reserved [0x28..0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR7 7 ++#define OCDR6 6 ++#define OCDR5 5 ++#define OCDR4 4 ++#define OCDR3 3 ++#define OCDR2 2 ++#define OCDR1 1 ++#define OCDR0 0 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define JTRF 4 ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define JTD 7 ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRLCD 4 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++/* Reserved [0x67..0x68] */ ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++ ++/* Reserved [0x71..0x72] */ ++ ++#define PCMSK3 _SFR_MEM8(0x73) ++ ++/* Reserved [0x74..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ACME 6 ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM21 3 ++#define COM2A0 4 ++#define COM2A1 5 ++#define WGM20 6 ++#define FOC2A 7 ++ ++/* Reserved [0xB1] */ ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++/* Reserved [0xB4..0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2UB 0 ++#define OCR2UB 1 ++#define TCN2UB 2 ++#define AS2 3 ++#define EXCLK 4 ++ ++/* Reserved [0xB7] */ ++ ++#define USICR _SFR_MEM8(0xB8) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_MEM8(0xB9) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_MEM8(0xBA) ++ ++/* Reserved [0xBB..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL0 6 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0xC6) ++ ++/* Reserved [0xC7..0xD7] */ ++ ++#define PINH _SFR_MEM8(0xD8) ++#define PINH7 7 ++#define PINH6 6 ++#define PINH5 5 ++#define PINH4 4 ++#define PINH3 3 ++#define PINH2 2 ++#define PINH1 1 ++#define PINH0 0 ++ ++#define DDRH _SFR_MEM8(0xD9) ++#define DDRH7 7 ++#define DDRH6 6 ++#define DDRH5 5 ++#define DDRH4 4 ++#define DDRH3 3 ++#define DDRH2 2 ++#define DDRH1 1 ++#define DDRH0 0 ++ ++#define PORTH _SFR_MEM8(0xDA) ++#define PORTH7 7 ++#define PORTH6 6 ++#define PORTH5 5 ++#define PORTH4 4 ++#define PORTH3 3 ++#define PORTH2 2 ++#define PORTH1 1 ++#define PORTH0 0 ++ ++#define PINJ _SFR_MEM8(0xDB) ++#define PINJ6 6 ++#define PINJ5 5 ++#define PINJ4 4 ++#define PINJ3 3 ++#define PINJ2 2 ++#define PINJ1 1 ++#define PINJ0 0 ++ ++#define DDRJ _SFR_MEM8(0xDC) ++#define DDRJ6 6 ++#define DDRJ5 5 ++#define DDRJ4 4 ++#define DDRJ3 3 ++#define DDRJ2 2 ++#define DDRJ1 1 ++#define DDRJ0 0 ++ ++#define PORTJ _SFR_MEM8(0xDD) ++#define PORTJ6 6 ++#define PORTJ5 5 ++#define PORTJ4 4 ++#define PORTJ3 3 ++#define PORTJ2 2 ++#define PORTJ1 1 ++#define PORTJ0 0 ++ ++/* Reserved [0xDE..0xE3] */ ++ ++#define LCDCRA _SFR_MEM8(0xE4) ++#define LCDBL 0 ++#define LCDCCD 1 ++#define LCDBD 2 ++#define LCDIE 3 ++#define LCDIF 4 ++#define LCDAB 6 ++#define LCDEN 7 ++ ++#define LCDCRB _SFR_MEM8(0xE5) ++#define LCDPM0 0 ++#define LCDPM1 1 ++#define LCDPM2 2 ++#define LCDPM3 3 ++#define LCDMUX0 4 ++#define LCDMUX1 5 ++#define LCD2B 6 ++#define LCDCS 7 ++ ++#define LCDFRR _SFR_MEM8(0xE6) ++#define LCDCD0 0 ++#define LCDCD1 1 ++#define LCDCD2 2 ++#define LCDPS0 4 ++#define LCDPS1 5 ++#define LCDPS2 6 ++ ++#define LCDCCR _SFR_MEM8(0xE7) ++#define LCDCC0 0 ++#define LCDCC1 1 ++#define LCDCC2 2 ++#define LCDCC3 3 ++#define LCDMDT 4 ++#define LCDDC0 5 ++#define LCDDC1 6 ++#define LCDDC2 7 ++ ++/* Reserved [0xE8..0xEB] */ ++ ++#define LCDDR0 _SFR_MEM8(0xEC) ++ ++#define LCDDR1 _SFR_MEM8(0xED) ++ ++#define LCDDR2 _SFR_MEM8(0xEE) ++ ++#define LCDDR3 _SFR_MEM8(0xEF) ++ ++#define LCDDR4 _SFR_MEM8(0xF0) ++ ++#define LCDDR5 _SFR_MEM8(0xF1) ++ ++#define LCDDR6 _SFR_MEM8(0xF2) ++ ++#define LCDDR7 _SFR_MEM8(0xF3) ++ ++#define LCDDR8 _SFR_MEM8(0xF4) ++ ++#define LCDDR9 _SFR_MEM8(0xF5) ++ ++#define LCDDR10 _SFR_MEM8(0xF6) ++ ++#define LCDDR11 _SFR_MEM8(0xF7) ++ ++#define LCDDR12 _SFR_MEM8(0xF8) ++ ++#define LCDDR13 _SFR_MEM8(0xF9) ++ ++#define LCDDR14 _SFR_MEM8(0xFA) ++ ++#define LCDDR15 _SFR_MEM8(0xFB) ++ ++#define LCDDR16 _SFR_MEM8(0xFC) ++ ++#define LCDDR17 _SFR_MEM8(0xFD) ++ ++#define LCDDR18 _SFR_MEM8(0xFE) ++ ++#define LCDDR19 _SFR_MEM8(0xFF) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(2) ++#define PCINT0_vect_num 2 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(3) ++#define PCINT1_vect_num 3 ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect _VECTOR(4) ++#define TIMER2_COMP_vect_num 4 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(5) ++#define TIMER2_OVF_vect_num 5 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define TIMER1_CAPT_vect_num 6 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define TIMER1_COMPA_vect_num 7 ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define TIMER1_COMPB_vect_num 8 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(9) ++#define TIMER1_OVF_vect_num 9 ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect _VECTOR(10) ++#define TIMER0_COMP_vect_num 10 ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(11) ++#define TIMER0_OVF_vect_num 11 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(12) ++#define SPI_STC_vect_num 12 ++ ++/* USART, Rx Complete */ ++#define USART_RX_vect _VECTOR(13) ++#define USART_RX_vect_num 13 ++ ++/* USART Data register Empty */ ++#define USART_UDRE_vect _VECTOR(14) ++#define USART_UDRE_vect_num 14 ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect _VECTOR(15) ++#define USART0_TX_vect_num 15 ++ ++/* USI Start Condition */ ++#define USI_START_vect _VECTOR(16) ++#define USI_START_vect_num 16 ++ ++/* USI Overflow */ ++#define USI_OVERFLOW_vect _VECTOR(17) ++#define USI_OVERFLOW_vect_num 17 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(18) ++#define ANALOG_COMP_vect_num 18 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(19) ++#define ADC_vect_num 19 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(20) ++#define EE_READY_vect_num 20 ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect _VECTOR(21) ++#define SPM_READY_vect_num 21 ++ ++/* LCD Start of Frame */ ++#define LCD_vect _VECTOR(22) ++#define LCD_vect_num 22 ++ ++/* Pin Change Interrupt Request 2 */ ++#define PCINT2_vect _VECTOR(23) ++#define PCINT2_vect_num 23 ++ ++/* Pin Change Interrupt Request 3 */ ++#define PCINT3_vect _VECTOR(24) ++#define PCINT3_vect_num 24 ++ ++#define _VECTORS_SIZE 100 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 128 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x7FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 2048 ++#define RAMEND 0x08FF ++#define E2START 0 ++#define E2SIZE 1024 ++#define E2PAGESIZE 4 ++#define E2END 0x03FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x0C ++ ++ ++#endif /* #ifdef _AVR_ATMEGA3290PA_H_INCLUDED */ ++ +diff --git a/include/avr/iom329a.h b/include/avr/iom329a.h +new file mode 100644 +index 0000000..87cbc88 +--- /dev/null ++++ b/include/avr/iom329a.h +@@ -0,0 +1,34 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2011 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++#include "iom329.h" +diff --git a/include/avr/iom329p.h b/include/avr/iom329p.h +new file mode 100644 +index 0000000..2159df9 +--- /dev/null ++++ b/include/avr/iom329p.h +@@ -0,0 +1,1035 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATMEGA329P_H_INCLUDED ++#define _AVR_ATMEGA329P_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom329p.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDRA7 7 ++#define DDRA6 6 ++#define DDRA5 5 ++#define DDRA4 4 ++#define DDRA3 3 ++#define DDRA2 2 ++#define DDRA1 1 ++#define DDRA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDRC7 7 ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC7 7 ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDRE7 7 ++#define DDRE6 6 ++#define DDRE5 5 ++#define DDRE4 4 ++#define DDRE3 3 ++#define DDRE2 2 ++#define DDRE1 1 ++#define DDRE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE7 7 ++#define PORTE6 6 ++#define PORTE5 5 ++#define PORTE4 4 ++#define PORTE3 3 ++#define PORTE2 2 ++#define PORTE1 1 ++#define PORTE0 0 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDRF7 7 ++#define DDRF6 6 ++#define DDRF5 5 ++#define DDRF4 4 ++#define DDRF3 3 ++#define DDRF2 2 ++#define DDRF1 1 ++#define DDRF0 0 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PORTF7 7 ++#define PORTF6 6 ++#define PORTF5 5 ++#define PORTF4 4 ++#define PORTF3 3 ++#define PORTF2 2 ++#define PORTF1 1 ++#define PORTF0 0 ++ ++#define PING _SFR_IO8(0x12) ++#define PING5 5 ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++#define DDRG _SFR_IO8(0x13) ++#define DDRG4 4 ++#define DDRG3 3 ++#define DDRG2 2 ++#define DDRG1 1 ++#define DDRG0 0 ++ ++#define PORTG _SFR_IO8(0x14) ++#define PORTG4 4 ++#define PORTG3 3 ++#define PORTG2 2 ++#define PORTG1 1 ++#define PORTG0 0 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++ ++/* Reserved [0x18..0x1B] */ ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define PCIF0 4 ++#define PCIF1 5 ++#define PCIF2 6 ++#define PCIF3 7 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define PCIE0 4 ++#define PCIE1 5 ++#define PCIE2 6 ++#define PCIE3 7 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR310 0 ++#define TSM 7 ++#define PSR2 1 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM01 3 ++#define COM0A0 4 ++#define COM0A1 5 ++#define WGM00 6 ++#define FOC0A 7 ++ ++/* Reserved [0x25] */ ++ ++#define TCNT0 _SFR_IO8(0x26) ++ ++#define OCR0A _SFR_IO8(0x27) ++ ++/* Reserved [0x28..0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR7 7 ++#define OCDR6 6 ++#define OCDR5 5 ++#define OCDR4 4 ++#define OCDR3 3 ++#define OCDR2 2 ++#define OCDR1 1 ++#define OCDR0 0 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define JTRF 4 ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define JTD 7 ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRLCD 4 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++/* Reserved [0x67..0x68] */ ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++/* Reserved [0x6D] */ ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++ ++/* Reserved [0x71..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ACME 6 ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM21 3 ++#define COM2A0 4 ++#define COM2A1 5 ++#define WGM20 6 ++#define FOC2A 7 ++ ++/* Reserved [0xB1] */ ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++/* Reserved [0xB4..0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2UB 0 ++#define OCR2UB 1 ++#define TCN2UB 2 ++#define AS2 3 ++#define EXCLK 4 ++ ++/* Reserved [0xB7] */ ++ ++#define USICR _SFR_MEM8(0xB8) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_MEM8(0xB9) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_MEM8(0xBA) ++ ++/* Reserved [0xBB..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL0 6 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0xC6) ++ ++/* Reserved [0xC7..0xE3] */ ++ ++#define LCDCRA _SFR_MEM8(0xE4) ++#define LCDBL 0 ++#define LCDCCD 1 ++#define LCDBD 2 ++#define LCDIE 3 ++#define LCDIF 4 ++#define LCDAB 6 ++#define LCDEN 7 ++ ++#define LCDCRB _SFR_MEM8(0xE5) ++#define LCDPM0 0 ++#define LCDPM1 1 ++#define LCDPM2 2 ++#define LCDPM3 3 ++#define LCDMUX0 4 ++#define LCDMUX1 5 ++#define LCD2B 6 ++#define LCDCS 7 ++ ++#define LCDFRR _SFR_MEM8(0xE6) ++#define LCDCD0 0 ++#define LCDCD1 1 ++#define LCDCD2 2 ++#define LCDPS0 4 ++#define LCDPS1 5 ++#define LCDPS2 6 ++ ++#define LCDCCR _SFR_MEM8(0xE7) ++#define LCDCC0 0 ++#define LCDCC1 1 ++#define LCDCC2 2 ++#define LCDCC3 3 ++#define LCDMDT 4 ++#define LCDDC0 5 ++#define LCDDC1 6 ++#define LCDDC2 7 ++ ++/* Reserved [0xE8..0xEB] */ ++ ++#define LCDDR0 _SFR_MEM8(0xEC) ++#define SEG000 0 ++#define SEG001 1 ++#define SEG002 2 ++#define SEG003 3 ++#define SEG004 4 ++#define SEG005 5 ++#define SEG006 6 ++#define SEG007 7 ++ ++#define LCDDR1 _SFR_MEM8(0xED) ++#define SEG008 0 ++#define SEG009 1 ++#define SEG010 2 ++#define SEG011 3 ++#define SEG012 4 ++#define SEG013 5 ++#define SEG014 6 ++#define SEG015 7 ++ ++#define LCDDR2 _SFR_MEM8(0xEE) ++#define SEG016 0 ++#define SEG017 1 ++#define SEG018 2 ++#define SEG019 3 ++#define SEG020 4 ++#define SEG021 5 ++#define SEG022 6 ++#define SEG023 7 ++ ++#define LCDDR3 _SFR_MEM8(0xEF) ++#define SEG024 0 ++#define SEG025 1 ++#define SEG026 2 ++#define SEG027 3 ++#define SEG028 4 ++#define SEG029 5 ++#define SEG030 6 ++#define SEG031 7 ++ ++/* Reserved [0xF0] */ ++ ++#define LCDDR5 _SFR_MEM8(0xF1) ++#define SEG100 0 ++#define SEG101 1 ++#define SEG102 2 ++#define SEG103 3 ++#define SEG104 4 ++#define SEG105 5 ++#define SEG106 6 ++#define SEG107 7 ++ ++#define LCDDR6 _SFR_MEM8(0xF2) ++#define SEG108 0 ++#define SEG109 1 ++#define SEG110 2 ++#define SEG111 3 ++#define SEG112 4 ++#define SEG113 5 ++#define SEG114 6 ++#define SEG115 7 ++ ++#define LCDDR7 _SFR_MEM8(0xF3) ++#define SEG116 0 ++#define SEG117 1 ++#define SEG118 2 ++#define SEG119 3 ++#define SEG120 4 ++#define SEG121 5 ++#define SEG122 6 ++#define SEG123 7 ++ ++#define LCDDR8 _SFR_MEM8(0xF4) ++#define SEG124 0 ++#define SEG125 1 ++#define SEG126 2 ++#define SEG127 3 ++#define SEG128 4 ++#define SEG129 5 ++#define SEG130 6 ++#define SEG131 7 ++ ++/* Reserved [0xF5] */ ++ ++#define LCDDR10 _SFR_MEM8(0xF6) ++#define SEG200 0 ++#define SEG201 1 ++#define SEG202 2 ++#define SEG203 3 ++#define SEG204 4 ++#define SEG205 5 ++#define SEG206 6 ++#define SEG207 7 ++ ++#define LCDDR11 _SFR_MEM8(0xF7) ++#define SEG208 0 ++#define SEG209 1 ++#define SEG210 2 ++#define SEG211 3 ++#define SEG212 4 ++#define SEG213 5 ++#define SEG214 6 ++#define SEG215 7 ++ ++#define LCDDR12 _SFR_MEM8(0xF8) ++#define SEG216 0 ++#define SEG217 1 ++#define SEG218 2 ++#define SEG219 3 ++#define SEG220 4 ++#define SEG221 5 ++#define SEG222 6 ++#define SEG223 7 ++ ++#define LCDDR13 _SFR_MEM8(0xF9) ++#define SEG224 0 ++#define SEG225 1 ++#define SEG226 2 ++#define SEG227 3 ++#define SEG228 4 ++#define SEG229 5 ++#define SEG230 6 ++#define SEG231 7 ++ ++/* Reserved [0xFA] */ ++ ++#define LCDDR15 _SFR_MEM8(0xFB) ++#define SEG300 0 ++#define SEG301 1 ++#define SEG302 2 ++#define SEG304 4 ++#define SEG305 5 ++#define SEG306 6 ++#define SEG307 7 ++ ++#define LCDDR16 _SFR_MEM8(0xFC) ++#define SEG308 0 ++#define SEG309 1 ++#define SEG310 2 ++#define SEG311 3 ++#define SEG312 4 ++#define SEG313 5 ++#define SEG314 6 ++#define SEG315 7 ++ ++#define LCDDR17 _SFR_MEM8(0xFD) ++#define SEG316 0 ++#define SEG317 1 ++#define SEG318 2 ++#define SEG319 3 ++#define SEG320 4 ++#define SEG321 5 ++#define SEG322 6 ++#define SEG323 7 ++ ++#define LCDDR18 _SFR_MEM8(0xFE) ++#define SEG324 0 ++#define SEG325 1 ++#define SEG326 2 ++#define SEG327 3 ++#define SEG328 4 ++#define SEG329 5 ++#define SEG330 6 ++#define SEG331 7 ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(2) ++#define PCINT0_vect_num 2 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(3) ++#define PCINT1_vect_num 3 ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect _VECTOR(4) ++#define TIMER2_COMP_vect_num 4 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(5) ++#define TIMER2_OVF_vect_num 5 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define TIMER1_CAPT_vect_num 6 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define TIMER1_COMPA_vect_num 7 ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define TIMER1_COMPB_vect_num 8 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(9) ++#define TIMER1_OVF_vect_num 9 ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect _VECTOR(10) ++#define TIMER0_COMP_vect_num 10 ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(11) ++#define TIMER0_OVF_vect_num 11 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(12) ++#define SPI_STC_vect_num 12 ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect _VECTOR(13) ++#define USART0_RX_vect_num 13 ++ ++/* USART0 Data register Empty */ ++#define USART0_UDRE_vect _VECTOR(14) ++#define USART0_UDRE_vect_num 14 ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect _VECTOR(15) ++#define USART0_TX_vect_num 15 ++ ++/* USI Start Condition */ ++#define USI_START_vect _VECTOR(16) ++#define USI_START_vect_num 16 ++ ++/* USI Overflow */ ++#define USI_OVERFLOW_vect _VECTOR(17) ++#define USI_OVERFLOW_vect_num 17 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(18) ++#define ANALOG_COMP_vect_num 18 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(19) ++#define ADC_vect_num 19 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(20) ++#define EE_READY_vect_num 20 ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect _VECTOR(21) ++#define SPM_READY_vect_num 21 ++ ++/* LCD Start of Frame */ ++#define LCD_vect _VECTOR(22) ++#define LCD_vect_num 22 ++ ++#define _VECTORS_SIZE 92 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 128 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x7FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 2048 ++#define RAMEND 0x08FF ++#define E2START 0 ++#define E2SIZE 1024 ++#define E2PAGESIZE 4 ++#define E2END 0x03FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x0B ++ ++ ++#endif /* #ifdef _AVR_ATMEGA329P_H_INCLUDED */ ++ +diff --git a/include/avr/iom329pa.h b/include/avr/iom329pa.h +new file mode 100644 +index 0000000..87cbc88 +--- /dev/null ++++ b/include/avr/iom329pa.h +@@ -0,0 +1,34 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2011 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++#include "iom329.h" +diff --git a/include/avr/iom32a.h b/include/avr/iom32a.h +new file mode 100644 +index 0000000..2a303e1 +--- /dev/null ++++ b/include/avr/iom32a.h +@@ -0,0 +1,608 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATMEGA32A_H_INCLUDED ++#define _AVR_ATMEGA32A_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom32a.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define TWBR _SFR_IO8(0x00) ++ ++#define TWSR _SFR_IO8(0x01) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_IO8(0x02) ++ ++#define TWDR _SFR_IO8(0x03) ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCW _SFR_IO16(0x04) ++ ++#define ADCL _SFR_IO8(0x04) ++#define ADCH _SFR_IO8(0x05) ++ ++#define ADCSRA _SFR_IO8(0x06) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADMUX _SFR_IO8(0x07) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define ACSR _SFR_IO8(0x08) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define UBRRL _SFR_IO8(0x09) ++ ++#define UCSRB _SFR_IO8(0x0A) ++#define TXB8 0 ++#define RXB8 1 ++#define UCSZ2 2 ++#define TXEN 3 ++#define RXEN 4 ++#define UDRIE 5 ++#define TXCIE 6 ++#define RXCIE 7 ++ ++#define UCSRA _SFR_IO8(0x0B) ++#define MPCM 0 ++#define U2X 1 ++#define UPE 2 ++#define DOR 3 ++#define FE 4 ++#define UDRE 5 ++#define TXC 6 ++#define RXC 7 ++ ++#define UDR _SFR_IO8(0x0C) ++ ++#define SPCR _SFR_IO8(0x0D) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x0E) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x0F) ++ ++#define PIND _SFR_IO8(0x10) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x11) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x12) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++#define PINC _SFR_IO8(0x13) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x14) ++#define DDRC7 7 ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x15) ++#define PORTC7 7 ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PINB _SFR_IO8(0x16) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x17) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x18) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINA _SFR_IO8(0x19) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x1A) ++#define DDRA7 7 ++#define DDRA6 6 ++#define DDRA5 5 ++#define DDRA4 4 ++#define DDRA3 3 ++#define DDRA2 2 ++#define DDRA1 1 ++#define DDRA0 0 ++ ++#define PORTA _SFR_IO8(0x1B) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define EECR _SFR_IO8(0x1C) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x1E) ++ ++#define EEARL _SFR_IO8(0x1E) ++#define EEARH _SFR_IO8(0x1F) ++ ++#define UCSRC _SFR_IO8(0x20) ++#define UCPOL 0 ++#define UCSZ0 1 ++#define UCSZ1 2 ++#define USBS 3 ++#define UPM0 4 ++#define UPM1 5 ++#define UMSEL 6 ++#define URSEL 7 ++ ++#define UBRRH _SFR_IO8(0x20) ++ ++#define WDTCR _SFR_IO8(0x21) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDTOE 4 ++ ++#define ASSR _SFR_IO8(0x22) ++#define TCR2UB 0 ++#define OCR2UB 1 ++#define TCN2UB 2 ++#define AS2 3 ++ ++#define OCR2 _SFR_IO8(0x23) ++ ++#define TCNT2 _SFR_IO8(0x24) ++ ++#define TCCR2 _SFR_IO8(0x25) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM21 3 ++#define COM20 4 ++#define COM21 5 ++#define WGM20 6 ++#define FOC2 7 ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_IO16(0x26) ++ ++#define ICR1L _SFR_IO8(0x26) ++#define ICR1H _SFR_IO8(0x27) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_IO16(0x28) ++ ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BH _SFR_IO8(0x29) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_IO16(0x2A) ++ ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_IO16(0x2C) ++ ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++ ++#define TCCR1B _SFR_IO8(0x2E) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1A _SFR_IO8(0x2F) ++#define WGM10 0 ++#define WGM11 1 ++#define FOC1B 2 ++#define FOC1A 3 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define SFIOR _SFR_IO8(0x30) ++#define PSR2 0 ++#define PSR10 0 ++#define PUD 2 ++#define ACME 3 ++#define ADTS0 5 ++#define ADTS1 6 ++#define ADTS2 7 ++ ++#define OSCCAL _SFR_IO8(0x31) ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++#define TCNT0 _SFR_IO8(0x32) ++ ++#define TCCR0 _SFR_IO8(0x33) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM01 3 ++#define COM00 4 ++#define COM01 5 ++#define WGM00 6 ++#define FOC0 7 ++ ++#define MCUCSR _SFR_IO8(0x34) ++#define ISC2 6 ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define JTRF 4 ++#define JTD 7 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define SM0 4 ++#define SM1 5 ++#define SM2 6 ++#define SE 7 ++ ++#define TWCR _SFR_IO8(0x36) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define SPMCR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define TIFR _SFR_IO8(0x38) ++#define TOV0 0 ++#define OCF0 1 ++#define TOV2 6 ++#define OCF2 7 ++#define TOV1 2 ++#define OCF1B 3 ++#define OCF1A 4 ++#define ICF1 5 ++ ++#define TIMSK _SFR_IO8(0x39) ++#define TOIE0 0 ++#define OCIE0 1 ++#define TOIE2 6 ++#define OCIE2 7 ++#define TOIE1 2 ++#define OCIE1B 3 ++#define OCIE1A 4 ++#define TICIE1 5 ++ ++#define GIFR _SFR_IO8(0x3A) ++#define INTF2 5 ++#define INTF0 6 ++#define INTF1 7 ++ ++#define GICR _SFR_IO8(0x3B) ++#define IVCE 0 ++#define IVSEL 1 ++#define INT2 5 ++#define INT0 6 ++#define INT1 7 ++ ++#define OCR0 _SFR_IO8(0x3C) ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect _VECTOR(3) ++#define INT2_vect_num 3 ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect _VECTOR(4) ++#define TIMER2_COMP_vect_num 4 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(5) ++#define TIMER2_OVF_vect_num 5 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define TIMER1_CAPT_vect_num 6 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define TIMER1_COMPA_vect_num 7 ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define TIMER1_COMPB_vect_num 8 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(9) ++#define TIMER1_OVF_vect_num 9 ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect _VECTOR(10) ++#define TIMER0_COMP_vect_num 10 ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(11) ++#define TIMER0_OVF_vect_num 11 ++ ++/* Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(12) ++#define SPI_STC_vect_num 12 ++ ++/* USART, Rx Complete */ ++#define USART_RXC_vect _VECTOR(13) ++#define USART_RXC_vect_num 13 ++ ++/* USART Data Register Empty */ ++#define USART_UDRE_vect _VECTOR(14) ++#define USART_UDRE_vect_num 14 ++ ++/* USART, Tx Complete */ ++#define USART_TXC_vect _VECTOR(15) ++#define USART_TXC_vect_num 15 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(16) ++#define ADC_vect_num 16 ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect _VECTOR(17) ++#define EE_RDY_vect_num 17 ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect _VECTOR(18) ++#define ANA_COMP_vect_num 18 ++ ++/* 2-wire Serial Interface */ ++#define TWI_vect _VECTOR(19) ++#define TWI_vect_num 19 ++ ++/* Store Program Memory Ready */ ++#define SPM_RDY_vect _VECTOR(20) ++#define SPM_RDY_vect_num 20 ++ ++#define _VECTORS_SIZE 84 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 128 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x7FFF ++#define RAMSTART 0x0060 ++#define RAMSIZE 2048 ++#define RAMEND 0x085F ++#define E2START 0 ++#define E2SIZE 1024 ++#define E2PAGESIZE 4 ++#define E2END 0x03FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 2 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_BODEN (unsigned char)~_BV(6) ++#define FUSE_BODLEVEL (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_CKOPT (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x02 ++ ++ ++#endif /* #ifdef _AVR_ATMEGA32A_H_INCLUDED */ ++ +diff --git a/include/avr/iom32c1.h b/include/avr/iom32c1.h +index e5df378..69f117e 100644 +--- a/include/avr/iom32c1.h ++++ b/include/avr/iom32c1.h +@@ -1,1306 +1,1306 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom32c1.h 2183 2010-09-21 05:37:46Z aboyapati $ */ +- +-/* avr/iom32c1.h - definitions for ATmega32C1 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom32c1.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATmega32C1_H_ +-#define _AVR_ATmega32C1_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +-#define PINC7 7 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC3 3 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +-#define DDC7 7 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC3 3 +-#define PORTC4 4 +-#define PORTC5 5 +-#define PORTC6 6 +-#define PORTC7 7 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define PINE _SFR_IO8(0x0C) +-#define PINE0 0 +-#define PINE1 1 +-#define PINE2 2 +- +-#define DDRE _SFR_IO8(0x0D) +-#define DDE0 0 +-#define DDE1 1 +-#define DDE2 2 +- +-#define PORTE _SFR_IO8(0x0E) +-#define PORTE0 0 +-#define PORTE1 1 +-#define PORTE2 2 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define GPIOR1 _SFR_IO8(0x19) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x1A) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +-#define PCIF1 1 +-#define PCIF2 2 +-#define PCIF3 3 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +-#define INTF2 2 +-#define INTF3 3 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +-#define INT2 2 +-#define INT3 3 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEWE 1 +-#define EEMWE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +-#define EEAR9 1 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSR10 0 +-#define PSRSYNC 0 +-#define ICPSEL1 6 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define OCR0A _SFR_IO8(0x27) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define OCR0B _SFR_IO8(0x28) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define PLLCSR _SFR_IO8(0x29) +-#define PLOCK 0 +-#define PLLE 1 +-#define PLLF 2 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define ACSR _SFR_IO8(0x30) +-#define AC0O 0 +-#define AC1O 1 +-#define AC2O 2 +-#define AC3O 3 +-#define AC0IF 4 +-#define AC1IF 5 +-#define AC2IF 6 +-#define AC3IF 7 +- +-#define DWDR _SFR_IO8(0x31) +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define SPIPS 7 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define SIGRD 5 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRLIN 1 +-#define PRSPI 2 +-#define PRTIM0 3 +-#define PRTIM1 4 +-#define PRPSC 5 +-#define PRCAN 6 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +-#define PCIE1 1 +-#define PCIE2 2 +-#define PCIE3 3 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define ISC20 4 +-#define ISC21 5 +-#define ISC30 6 +-#define ISC31 7 +- +-#define PCMSK0 _SFR_MEM8(0x6A) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6B) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-#define PCMSK2 _SFR_MEM8(0x6C) +-#define PCINT16 0 +-#define PCINT17 1 +-#define PCINT18 2 +-#define PCINT19 3 +-#define PCINT20 4 +-#define PCINT21 5 +-#define PCINT22 6 +-#define PCINT23 7 +- +-#define PCMSK3 _SFR_MEM8(0x6D) +-#define PCINT24 0 +-#define PCINT25 1 +-#define PCINT26 2 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define AMP0CSR _SFR_MEM8(0x75) +-#define AMP0TS0 0 +-#define AMP0TS1 1 +-#define AMP0TS2 2 +-#define AMPCMP0 3 +-#define AMP0G0 4 +-#define AMP0G1 5 +-#define AMP0IS 6 +-#define AMP0EN 7 +- +-#define AMP1CSR _SFR_MEM8(0x76) +-#define AMP1TS0 0 +-#define AMP1TS1 1 +-#define AMP1TS2 2 +-#define AMPCMP1 3 +-#define AMP1G0 4 +-#define AMP1G1 5 +-#define AMP1IS 6 +-#define AMP1EN 7 +- +-#define AMP2CSR _SFR_MEM8(0x77) +-#define AMP2TS0 0 +-#define AMP2TS1 1 +-#define AMP2TS2 2 +-#define AMPCMP2 3 +-#define AMP2G0 4 +-#define AMP2G1 5 +-#define AMP2IS 6 +-#define AMP2EN 7 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +- +-#define ADCL _SFR_MEM8(0x78) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_MEM8(0x79) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ADTS3 3 +-#define AREFEN 5 +-#define ISRCEN 6 +-#define ADHSM 7 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define ADC8D 0 +-#define ADC9D 1 +-#define ADC10D 2 +-#define AMP0ND 3 +-#define AMP0PD 4 +-#define ACMP0D 5 +-#define AMP2PD 6 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define DACON _SFR_MEM8(0x90) +-#define DAEN 0 +-#define DAOE 1 +-#define DALA 2 +-#define DATS0 4 +-#define DATS1 5 +-#define DATS2 6 +-#define DAATE 7 +- +-#define DAC _SFR_MEM16(0x91) +- +-#define DACL _SFR_MEM8(0x91) +-#define DACL0 0 +-#define DACL1 1 +-#define DACL2 2 +-#define DACL3 3 +-#define DACL4 4 +-#define DACL5 5 +-#define DACL6 6 +-#define DACL7 7 +- +-#define DACH _SFR_MEM8(0x92) +-#define DACH0 0 +-#define DACH1 1 +-#define DACH2 2 +-#define DACH3 3 +-#define DACH4 4 +-#define DACH5 5 +-#define DACH6 6 +-#define DACH7 7 +- +-#define AC0CON _SFR_MEM8(0x94) +-#define AC0M0 0 +-#define AC0M1 1 +-#define AC0M2 2 +-#define ACCKSEL 3 +-#define AC0IS0 4 +-#define AC0IS1 5 +-#define AC0IE 6 +-#define AC0EN 7 +- +-#define AC1CON _SFR_MEM8(0x95) +-#define AC1M0 0 +-#define AC1M1 1 +-#define AC1M2 2 +-#define AC1ICE 3 +-#define AC1IS0 4 +-#define AC1IS1 5 +-#define AC1IE 6 +-#define AC1EN 7 +- +-#define AC2CON _SFR_MEM8(0x96) +-#define AC2M0 0 +-#define AC2M1 1 +-#define AC2M2 2 +-#define AC2IS0 4 +-#define AC2IS1 5 +-#define AC2IE 6 +-#define AC2EN 7 +- +-#define AC3CON _SFR_MEM8(0x97) +-#define AC3M0 0 +-#define AC3M1 1 +-#define AC3M2 2 +-#define AC3IS0 4 +-#define AC3IS1 5 +-#define AC3IE 6 +-#define AC3EN 7 +- +-#define LINCR _SFR_MEM8(0xC8) +-#define LCMD0 0 +-#define LCMD1 1 +-#define LCMD2 2 +-#define LENA 3 +-#define LCONF0 4 +-#define LCONF1 5 +-#define LIN13 6 +-#define LSWRES 7 +- +-#define LINSIR _SFR_MEM8(0xC9) +-#define LRXOK 0 +-#define LTXOK 1 +-#define LIDOK 2 +-#define LERR 3 +-#define LBUSY 4 +-#define LIDST0 5 +-#define LIDST1 6 +-#define LIDST2 7 +- +-#define LINENIR _SFR_MEM8(0xCA) +-#define LENRXOK 0 +-#define LENTXOK 1 +-#define LENIDOK 2 +-#define LENERR 3 +- +-#define LINERR _SFR_MEM8(0xCB) +-#define LBERR 0 +-#define LCERR 1 +-#define LPERR 2 +-#define LSERR 3 +-#define LFERR 4 +-#define LOVERR 5 +-#define LTOERR 6 +-#define LABORT 7 +- +-#define LINBTR _SFR_MEM8(0xCC) +-#define LBT0 0 +-#define LBT1 1 +-#define LBT2 2 +-#define LBT3 3 +-#define LBT4 4 +-#define LBT5 5 +-#define LDISR 7 +- +-#define LINBRR _SFR_MEM16(0xCD) +- +-#define LINBRRL _SFR_MEM8(0xCD) +-#define LDIV0 0 +-#define LDIV1 1 +-#define LDIV2 2 +-#define LDIV3 3 +-#define LDIV4 4 +-#define LDIV5 5 +-#define LDIV6 6 +-#define LDIV7 7 +- +-#define LINBRRH _SFR_MEM8(0xCE) +-#define LDIV8 0 +-#define LDIV9 1 +-#define LDIV10 2 +-#define LDIV11 3 +- +-#define LINDLR _SFR_MEM8(0xCF) +-#define LRXDL0 0 +-#define LRXDL1 1 +-#define LRXDL2 2 +-#define LRXDL3 3 +-#define LTXDL0 4 +-#define LTXDL1 5 +-#define LTXDL2 6 +-#define LTXDL3 7 +- +-#define LINIDR _SFR_MEM8(0xD0) +-#define LID0 0 +-#define LID1 1 +-#define LID2 2 +-#define LID3 3 +-#define LID4 4 +-#define LID5 5 +-#define LP0 6 +-#define LP1 7 +- +-#define LINSEL _SFR_MEM8(0xD1) +-#define LINDX0 0 +-#define LINDX1 1 +-#define LINDX2 2 +-#define LAINC 3 +- +-#define LINDAT _SFR_MEM8(0xD2) +-#define LDATA0 0 +-#define LDATA1 1 +-#define LDATA2 2 +-#define LDATA3 3 +-#define LDATA4 4 +-#define LDATA5 5 +-#define LDATA6 6 +-#define LDATA7 7 +- +-#define CANGCON _SFR_MEM8(0xD8) +-#define SWRES 0 +-#define ENASTB 1 +-#define TEST 2 +-#define LISTEN 3 +-#define SYNTTC 4 +-#define TTC 5 +-#define OVRQ 6 +-#define ABRQ 7 +- +-#define CANGSTA _SFR_MEM8(0xD9) +-#define ERRP 0 +-#define BOFF 1 +-#define ENFG 2 +-#define RXBSY 3 +-#define TXBSY 4 +-#define OVFG 6 +- +-#define CANGIT _SFR_MEM8(0xDA) +-#define AERG 0 +-#define FERG 1 +-#define CERG 2 +-#define SERG 3 +-#define BXOK 4 +-#define OVRTIM 5 +-#define BOFFIT 6 +-#define CANIT 7 +- +-#define CANGIE _SFR_MEM8(0xDB) +-#define ENOVRT 0 +-#define ENERG 1 +-#define ENBX 2 +-#define ENERR 3 +-#define ENTX 4 +-#define ENRX 5 +-#define ENBOFF 6 +-#define ENIT 7 +- +-#define CANEN2 _SFR_MEM8(0xDC) +-#define ENMOB0 0 +-#define ENMOB1 1 +-#define ENMOB2 2 +-#define ENMOB3 3 +-#define ENMOB4 4 +-#define ENMOB5 5 +- +-#define CANEN1 _SFR_MEM8(0xDD) +- +-#define CANIE2 _SFR_MEM8(0xDE) +-#define IEMOB0 0 +-#define IEMOB1 1 +-#define IEMOB2 2 +-#define IEMOB3 3 +-#define IEMOB4 4 +-#define IEMOB5 5 +- +-#define CANIE1 _SFR_MEM8(0xDF) +- +-/* RegDef: CAN Status Interrupt MOb Register*/ +-#define CANSIT _SFR_MEM16(0xE0) +- +-#define CANSIT2 _SFR_MEM8(0xE0) +-#define SIT0 0 +-#define SIT1 1 +-#define SIT2 2 +-#define SIT3 3 +-#define SIT4 4 +-#define SIT5 5 +- +-#define CANSIT1 _SFR_MEM8(0xE1) +- +-#define CANBT1 _SFR_MEM8(0xE2) +-#define BRP0 1 +-#define BRP1 2 +-#define BRP2 3 +-#define BRP3 4 +-#define BRP4 5 +-#define BRP5 6 +- +-#define CANBT2 _SFR_MEM8(0xE3) +-#define PRS0 1 +-#define PRS1 2 +-#define PRS2 3 +-#define SJW0 5 +-#define SJW1 6 +- +-#define CANBT3 _SFR_MEM8(0xE4) +-#define SMP 0 +-#define PHS10 1 +-#define PHS11 2 +-#define PHS12 3 +-#define PHS20 4 +-#define PHS21 5 +-#define PHS22 6 +- +-#define CANTCON _SFR_MEM8(0xE5) +-#define TPRSC0 0 +-#define TPRSC1 1 +-#define TPRSC2 2 +-#define TPRSC3 3 +-#define TPRSC4 4 +-#define TPRSC5 5 +-#define TPRSC6 6 +-#define TPRSC7 7 +- +-#define CANTIM _SFR_MEM16(0xE6) +- +-#define CANTIML _SFR_MEM8(0xE6) +-#define CANTIM0 0 +-#define CANTIM1 1 +-#define CANTIM2 2 +-#define CANTIM3 3 +-#define CANTIM4 4 +-#define CANTIM5 5 +-#define CANTIM6 6 +-#define CANTIM7 7 +- +-#define CANTIMH _SFR_MEM8(0xE7) +-#define CANTIM8 0 +-#define CANTIM9 1 +-#define CANTIM10 2 +-#define CANTIM11 3 +-#define CANTIM12 4 +-#define CANTIM13 5 +-#define CANTIM14 6 +-#define CANTIM15 7 +- +-#define CANTTC _SFR_MEM16(0xE8) +- +-#define CANTTCL _SFR_MEM8(0xE8) +-#define TIMTCC0 0 +-#define TIMTCC1 1 +-#define TIMTCC2 2 +-#define TIMTCC3 3 +-#define TIMTCC4 4 +-#define TIMTCC5 5 +-#define TIMTCC6 6 +-#define TIMTCC7 7 +- +-#define CANTTCH _SFR_MEM8(0xE9) +-#define TIMTCC8 0 +-#define TIMTCC9 1 +-#define TIMTCC10 2 +-#define TIMTCC11 3 +-#define TIMTCC12 4 +-#define TIMTCC13 5 +-#define TIMTCC14 6 +-#define TIMTCC15 7 +- +-#define CANTEC _SFR_MEM8(0xEA) +-#define TEC0 0 +-#define TEC1 1 +-#define TEC2 2 +-#define TEC3 3 +-#define TEC4 4 +-#define TEC5 5 +-#define TEC6 6 +-#define TEC7 7 +- +-#define CANREC _SFR_MEM8(0xEB) +-#define REC0 0 +-#define REC1 1 +-#define REC2 2 +-#define REC3 3 +-#define REC4 4 +-#define REC5 5 +-#define REC6 6 +-#define REC7 7 +- +-#define CANHPMOB _SFR_MEM8(0xEC) +-#define CGP0 0 +-#define CGP1 1 +-#define CGP2 2 +-#define CGP3 3 +-#define HPMOB0 4 +-#define HPMOB1 5 +-#define HPMOB2 6 +-#define HPMOB3 7 +- +-#define CANPAGE _SFR_MEM8(0xED) +-#define INDX0 0 +-#define INDX1 1 +-#define INDX2 2 +-#define AINC 3 +-#define MOBNB0 4 +-#define MOBNB1 5 +-#define MOBNB2 6 +-#define MOBNB3 7 +- +-#define CANSTMOB _SFR_MEM8(0xEE) +-#define AERR 0 +-#define FERR 1 +-#define CERR 2 +-#define SERR 3 +-#define BERR 4 +-#define RXOK 5 +-#define TXOK 6 +-#define DLCW 7 +- +-#define CANCDMOB _SFR_MEM8(0xEF) +-#define DLC0 0 +-#define DLC1 1 +-#define DLC2 2 +-#define DLC3 3 +-#define IDE 4 +-#define RPLV 5 +-#define CONMOB0 6 +-#define CONMOB1 7 +- +-/* RegDef: CAN Identifier Tag Registers*/ +-#define CANIDT _SFR_MEM32(0xF0) +- +-#define CANIDT4 _SFR_MEM8(0xF0) +-#define RB0TAG 0 +-#define RB1TAG 1 +-#define RTRTAG 2 +-#define IDT0 3 +-#define IDT1 4 +-#define IDT2 5 +-#define IDT3 6 +-#define IDT4 7 +- +-#define CANIDT3 _SFR_MEM8(0xF1) +-#define IDT5 0 +-#define IDT6 1 +-#define IDT7 2 +-#define IDT8 3 +-#define IDT9 4 +-#define IDT10 5 +-#define IDT11 6 +-#define IDT12 7 +- +-#define CANIDT2 _SFR_MEM8(0xF2) +-#define IDT13 0 +-#define IDT14 1 +-#define IDT15 2 +-#define IDT16 3 +-#define IDT17 4 +-#define IDT18 5 +-#define IDT19 6 +-#define IDT20 7 +- +-#define CANIDT1 _SFR_MEM8(0xF3) +-#define IDT21 0 +-#define IDT22 1 +-#define IDT23 2 +-#define IDT24 3 +-#define IDT25 4 +-#define IDT26 5 +-#define IDT27 6 +-#define IDT28 7 +- +-/* RegDef: CAN Identifier Mask Registers */ +-#define CANIDM _SFR_MEM32(0xF4) +- +-#define CANIDM4 _SFR_MEM8(0xF4) +-#define IDEMSK 0 +-#define RTRMSK 2 +-#define IDMSK0 3 +-#define IDMSK1 4 +-#define IDMSK2 5 +-#define IDMSK3 6 +-#define IDMSK4 7 +- +-#define CANIDM3 _SFR_MEM8(0xF5) +-#define IDMSK5 0 +-#define IDMSK6 1 +-#define IDMSK7 2 +-#define IDMSK8 3 +-#define IDMSK9 4 +-#define IDMSK10 5 +-#define IDMSK11 6 +-#define IDMSK12 7 +- +-#define CANIDM2 _SFR_MEM8(0xF6) +-#define IDMSK13 0 +-#define IDMSK14 1 +-#define IDMSK15 2 +-#define IDMSK16 3 +-#define IDMSK17 4 +-#define IDMSK18 5 +-#define IDMSK19 6 +-#define IDMSK20 7 +- +-#define CANIDM1 _SFR_MEM8(0xF7) +-#define IDMSK21 0 +-#define IDMSK22 1 +-#define IDMSK23 2 +-#define IDMSK24 3 +-#define IDMSK25 4 +-#define IDMSK26 5 +-#define IDMSK27 6 +-#define IDMSK28 7 +- +-#define CANSTM _SFR_MEM16(0xF8) +- +-#define CANSTML _SFR_MEM8(0xF8) +-#define TIMSTM0 0 +-#define TIMSTM1 1 +-#define TIMSTM2 2 +-#define TIMSTM3 3 +-#define TIMSTM4 4 +-#define TIMSTM5 5 +-#define TIMSTM6 6 +-#define TIMSTM7 7 +- +-#define CANSTMH _SFR_MEM8(0xF9) +-#define TIMSTM8 0 +-#define TIMSTM9 1 +-#define TIMSTM10 2 +-#define TIMSTM11 3 +-#define TIMSTM12 4 +-#define TIMSTM13 5 +-#define TIMSTM14 6 +-#define TIMSTM15 7 +- +-#define CANMSG _SFR_MEM8(0xFA) +-#define MSG0 0 +-#define MSG1 1 +-#define MSG2 2 +-#define MSG3 3 +-#define MSG4 4 +-#define MSG5 5 +-#define MSG6 6 +-#define MSG7 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define ANACOMP0_vect_num 1 +-#define ANACOMP0_vect _VECTOR(1) /* Analog Comparator 0 */ +-#define ANACOMP1_vect_num 2 +-#define ANACOMP1_vect _VECTOR(2) /* Analog Comparator 1 */ +-#define ANACOMP2_vect_num 3 +-#define ANACOMP2_vect _VECTOR(3) /* Analog Comparator 2 */ +-#define ANACOMP3_vect_num 4 +-#define ANACOMP3_vect _VECTOR(4) /* Analog Comparator 3 */ +-#define PSC_FAULT_vect_num 5 +-#define PSC_FAULT_vect _VECTOR(5) /* PSC Fault */ +-#define PSC_EC_vect_num 6 +-#define PSC_EC_vect _VECTOR(6) /* PSC End of Cycle */ +-#define INT0_vect_num 7 +-#define INT0_vect _VECTOR(7) /* External Interrupt Request 0 */ +-#define INT1_vect_num 8 +-#define INT1_vect _VECTOR(8) /* External Interrupt Request 1 */ +-#define INT2_vect_num 9 +-#define INT2_vect _VECTOR(9) /* External Interrupt Request 2 */ +-#define INT3_vect_num 10 +-#define INT3_vect _VECTOR(10) /* External Interrupt Request 3 */ +-#define TIMER1_CAPT_vect_num 11 +-#define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */ +-#define TIMER1_COMPA_vect_num 12 +-#define TIMER1_COMPA_vect _VECTOR(12) /* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPB_vect_num 13 +-#define TIMER1_COMPB_vect _VECTOR(13) /* Timer/Counter1 Compare Match B */ +-#define TIMER1_OVF_vect_num 14 +-#define TIMER1_OVF_vect _VECTOR(14) /* Timer1/Counter1 Overflow */ +-#define TIMER0_COMPA_vect_num 15 +-#define TIMER0_COMPA_vect _VECTOR(15) /* Timer/Counter0 Compare Match A */ +-#define TIMER0_COMPB_vect_num 16 +-#define TIMER0_COMPB_vect _VECTOR(16) /* Timer/Counter0 Compare Match B */ +-#define TIMER0_OVF_vect_num 17 +-#define TIMER0_OVF_vect _VECTOR(17) /* Timer/Counter0 Overflow */ +-#define CAN_INT_vect_num 18 +-#define CAN_INT_vect _VECTOR(18) /* CAN MOB, Burst, General Errors */ +-#define CAN_TOVF_vect_num 19 +-#define CAN_TOVF_vect _VECTOR(19) /* CAN Timer Overflow */ +-#define LIN_TC_vect_num 20 +-#define LIN_TC_vect _VECTOR(20) /* LIN Transfer Complete */ +-#define LIN_ERR_vect_num 21 +-#define LIN_ERR_vect _VECTOR(21) /* LIN Error */ +-#define PCINT0_vect_num 22 +-#define PCINT0_vect _VECTOR(22) /* Pin Change Interrupt Request 0 */ +-#define PCINT1_vect_num 23 +-#define PCINT1_vect _VECTOR(23) /* Pin Change Interrupt Request 1 */ +-#define PCINT2_vect_num 24 +-#define PCINT2_vect _VECTOR(24) /* Pin Change Interrupt Request 2 */ +-#define PCINT3_vect_num 25 +-#define PCINT3_vect _VECTOR(25) /* Pin Change Interrupt Request 3 */ +-#define SPI_STC_vect_num 26 +-#define SPI_STC_vect _VECTOR(26) /* SPI Serial Transfer Complete */ +-#define ADC_vect_num 27 +-#define ADC_vect _VECTOR(27) /* ADC Conversion Complete */ +-#define WDT_vect_num 28 +-#define WDT_vect _VECTOR(28) /* Watchdog Time-Out Interrupt */ +-#define EE_READY_vect_num 29 +-#define EE_READY_vect _VECTOR(29) /* EEPROM Ready */ +-#define SPM_READY_vect_num 30 +-#define SPM_READY_vect _VECTOR(30) /* Store Program Memory Read */ +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (31 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (128) +-#define RAMSTART (0x0100) +-#define RAMSIZE (2048) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (0x0) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x3FF) +-#define E2PAGESIZE (4) +-#define FLASHEND (0x7FFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector Trigger Level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector Trigger Level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector Trigger Level */ +-#define FUSE_PSCRVB (unsigned char)~_BV(3) /* PSC Outputs xB Reset Value */ +-#define FUSE_PSCRVA (unsigned char)~_BV(4) /* PSC Outputs xA Reset Value */ +-#define FUSE_PSCRB (unsigned char)~_BV(5) /* PSC Reset Behavior */ +-#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_BODLEVEL1) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x95 +-#define SIGNATURE_2 0x86 +- +- +-#endif /* _AVR_ATmega32C1_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom32c1.h 2183 2010-09-21 05:37:46Z aboyapati $ */ ++ ++/* avr/iom32c1.h - definitions for ATmega32C1 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom32c1.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATmega32C1_H_ ++#define _AVR_ATmega32C1_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++#define PINC7 7 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++#define DDC7 7 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC3 3 ++#define PORTC4 4 ++#define PORTC5 5 ++#define PORTC6 6 ++#define PORTC7 7 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE0 0 ++#define PINE1 1 ++#define PINE2 2 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE0 0 ++#define DDE1 1 ++#define DDE2 2 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE0 0 ++#define PORTE1 1 ++#define PORTE2 2 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define GPIOR1 _SFR_IO8(0x19) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x1A) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++#define PCIF3 3 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++#define INT3 3 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++#define EEAR9 1 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR10 0 ++#define PSRSYNC 0 ++#define ICPSEL1 6 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define OCR0A _SFR_IO8(0x27) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define OCR0B _SFR_IO8(0x28) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define PLLCSR _SFR_IO8(0x29) ++#define PLOCK 0 ++#define PLLE 1 ++#define PLLF 2 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define ACSR _SFR_IO8(0x30) ++#define AC0O 0 ++#define AC1O 1 ++#define AC2O 2 ++#define AC3O 3 ++#define AC0IF 4 ++#define AC1IF 5 ++#define AC2IF 6 ++#define AC3IF 7 ++ ++#define DWDR _SFR_IO8(0x31) ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define SPIPS 7 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRLIN 1 ++#define PRSPI 2 ++#define PRTIM0 3 ++#define PRTIM1 4 ++#define PRPSC 5 ++#define PRCAN 6 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++#define PCIE3 3 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++#define PCMSK0 _SFR_MEM8(0x6A) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6B) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK2 _SFR_MEM8(0x6C) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define PCMSK3 _SFR_MEM8(0x6D) ++#define PCINT24 0 ++#define PCINT25 1 ++#define PCINT26 2 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define AMP0CSR _SFR_MEM8(0x75) ++#define AMP0TS0 0 ++#define AMP0TS1 1 ++#define AMP0TS2 2 ++#define AMPCMP0 3 ++#define AMP0G0 4 ++#define AMP0G1 5 ++#define AMP0IS 6 ++#define AMP0EN 7 ++ ++#define AMP1CSR _SFR_MEM8(0x76) ++#define AMP1TS0 0 ++#define AMP1TS1 1 ++#define AMP1TS2 2 ++#define AMPCMP1 3 ++#define AMP1G0 4 ++#define AMP1G1 5 ++#define AMP1IS 6 ++#define AMP1EN 7 ++ ++#define AMP2CSR _SFR_MEM8(0x77) ++#define AMP2TS0 0 ++#define AMP2TS1 1 ++#define AMP2TS2 2 ++#define AMPCMP2 3 ++#define AMP2G0 4 ++#define AMP2G1 5 ++#define AMP2IS 6 ++#define AMP2EN 7 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_MEM8(0x79) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ADTS3 3 ++#define AREFEN 5 ++#define ISRCEN 6 ++#define ADHSM 7 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define ADC8D 0 ++#define ADC9D 1 ++#define ADC10D 2 ++#define AMP0ND 3 ++#define AMP0PD 4 ++#define ACMP0D 5 ++#define AMP2PD 6 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define DACON _SFR_MEM8(0x90) ++#define DAEN 0 ++#define DAOE 1 ++#define DALA 2 ++#define DATS0 4 ++#define DATS1 5 ++#define DATS2 6 ++#define DAATE 7 ++ ++#define DAC _SFR_MEM16(0x91) ++ ++#define DACL _SFR_MEM8(0x91) ++#define DACL0 0 ++#define DACL1 1 ++#define DACL2 2 ++#define DACL3 3 ++#define DACL4 4 ++#define DACL5 5 ++#define DACL6 6 ++#define DACL7 7 ++ ++#define DACH _SFR_MEM8(0x92) ++#define DACH0 0 ++#define DACH1 1 ++#define DACH2 2 ++#define DACH3 3 ++#define DACH4 4 ++#define DACH5 5 ++#define DACH6 6 ++#define DACH7 7 ++ ++#define AC0CON _SFR_MEM8(0x94) ++#define AC0M0 0 ++#define AC0M1 1 ++#define AC0M2 2 ++#define ACCKSEL 3 ++#define AC0IS0 4 ++#define AC0IS1 5 ++#define AC0IE 6 ++#define AC0EN 7 ++ ++#define AC1CON _SFR_MEM8(0x95) ++#define AC1M0 0 ++#define AC1M1 1 ++#define AC1M2 2 ++#define AC1ICE 3 ++#define AC1IS0 4 ++#define AC1IS1 5 ++#define AC1IE 6 ++#define AC1EN 7 ++ ++#define AC2CON _SFR_MEM8(0x96) ++#define AC2M0 0 ++#define AC2M1 1 ++#define AC2M2 2 ++#define AC2IS0 4 ++#define AC2IS1 5 ++#define AC2IE 6 ++#define AC2EN 7 ++ ++#define AC3CON _SFR_MEM8(0x97) ++#define AC3M0 0 ++#define AC3M1 1 ++#define AC3M2 2 ++#define AC3IS0 4 ++#define AC3IS1 5 ++#define AC3IE 6 ++#define AC3EN 7 ++ ++#define LINCR _SFR_MEM8(0xC8) ++#define LCMD0 0 ++#define LCMD1 1 ++#define LCMD2 2 ++#define LENA 3 ++#define LCONF0 4 ++#define LCONF1 5 ++#define LIN13 6 ++#define LSWRES 7 ++ ++#define LINSIR _SFR_MEM8(0xC9) ++#define LRXOK 0 ++#define LTXOK 1 ++#define LIDOK 2 ++#define LERR 3 ++#define LBUSY 4 ++#define LIDST0 5 ++#define LIDST1 6 ++#define LIDST2 7 ++ ++#define LINENIR _SFR_MEM8(0xCA) ++#define LENRXOK 0 ++#define LENTXOK 1 ++#define LENIDOK 2 ++#define LENERR 3 ++ ++#define LINERR _SFR_MEM8(0xCB) ++#define LBERR 0 ++#define LCERR 1 ++#define LPERR 2 ++#define LSERR 3 ++#define LFERR 4 ++#define LOVERR 5 ++#define LTOERR 6 ++#define LABORT 7 ++ ++#define LINBTR _SFR_MEM8(0xCC) ++#define LBT0 0 ++#define LBT1 1 ++#define LBT2 2 ++#define LBT3 3 ++#define LBT4 4 ++#define LBT5 5 ++#define LDISR 7 ++ ++#define LINBRR _SFR_MEM16(0xCD) ++ ++#define LINBRRL _SFR_MEM8(0xCD) ++#define LDIV0 0 ++#define LDIV1 1 ++#define LDIV2 2 ++#define LDIV3 3 ++#define LDIV4 4 ++#define LDIV5 5 ++#define LDIV6 6 ++#define LDIV7 7 ++ ++#define LINBRRH _SFR_MEM8(0xCE) ++#define LDIV8 0 ++#define LDIV9 1 ++#define LDIV10 2 ++#define LDIV11 3 ++ ++#define LINDLR _SFR_MEM8(0xCF) ++#define LRXDL0 0 ++#define LRXDL1 1 ++#define LRXDL2 2 ++#define LRXDL3 3 ++#define LTXDL0 4 ++#define LTXDL1 5 ++#define LTXDL2 6 ++#define LTXDL3 7 ++ ++#define LINIDR _SFR_MEM8(0xD0) ++#define LID0 0 ++#define LID1 1 ++#define LID2 2 ++#define LID3 3 ++#define LID4 4 ++#define LID5 5 ++#define LP0 6 ++#define LP1 7 ++ ++#define LINSEL _SFR_MEM8(0xD1) ++#define LINDX0 0 ++#define LINDX1 1 ++#define LINDX2 2 ++#define LAINC 3 ++ ++#define LINDAT _SFR_MEM8(0xD2) ++#define LDATA0 0 ++#define LDATA1 1 ++#define LDATA2 2 ++#define LDATA3 3 ++#define LDATA4 4 ++#define LDATA5 5 ++#define LDATA6 6 ++#define LDATA7 7 ++ ++#define CANGCON _SFR_MEM8(0xD8) ++#define SWRES 0 ++#define ENASTB 1 ++#define TEST 2 ++#define LISTEN 3 ++#define SYNTTC 4 ++#define TTC 5 ++#define OVRQ 6 ++#define ABRQ 7 ++ ++#define CANGSTA _SFR_MEM8(0xD9) ++#define ERRP 0 ++#define BOFF 1 ++#define ENFG 2 ++#define RXBSY 3 ++#define TXBSY 4 ++#define OVFG 6 ++ ++#define CANGIT _SFR_MEM8(0xDA) ++#define AERG 0 ++#define FERG 1 ++#define CERG 2 ++#define SERG 3 ++#define BXOK 4 ++#define OVRTIM 5 ++#define BOFFIT 6 ++#define CANIT 7 ++ ++#define CANGIE _SFR_MEM8(0xDB) ++#define ENOVRT 0 ++#define ENERG 1 ++#define ENBX 2 ++#define ENERR 3 ++#define ENTX 4 ++#define ENRX 5 ++#define ENBOFF 6 ++#define ENIT 7 ++ ++#define CANEN2 _SFR_MEM8(0xDC) ++#define ENMOB0 0 ++#define ENMOB1 1 ++#define ENMOB2 2 ++#define ENMOB3 3 ++#define ENMOB4 4 ++#define ENMOB5 5 ++ ++#define CANEN1 _SFR_MEM8(0xDD) ++ ++#define CANIE2 _SFR_MEM8(0xDE) ++#define IEMOB0 0 ++#define IEMOB1 1 ++#define IEMOB2 2 ++#define IEMOB3 3 ++#define IEMOB4 4 ++#define IEMOB5 5 ++ ++#define CANIE1 _SFR_MEM8(0xDF) ++ ++/* RegDef: CAN Status Interrupt MOb Register*/ ++#define CANSIT _SFR_MEM16(0xE0) ++ ++#define CANSIT2 _SFR_MEM8(0xE0) ++#define SIT0 0 ++#define SIT1 1 ++#define SIT2 2 ++#define SIT3 3 ++#define SIT4 4 ++#define SIT5 5 ++ ++#define CANSIT1 _SFR_MEM8(0xE1) ++ ++#define CANBT1 _SFR_MEM8(0xE2) ++#define BRP0 1 ++#define BRP1 2 ++#define BRP2 3 ++#define BRP3 4 ++#define BRP4 5 ++#define BRP5 6 ++ ++#define CANBT2 _SFR_MEM8(0xE3) ++#define PRS0 1 ++#define PRS1 2 ++#define PRS2 3 ++#define SJW0 5 ++#define SJW1 6 ++ ++#define CANBT3 _SFR_MEM8(0xE4) ++#define SMP 0 ++#define PHS10 1 ++#define PHS11 2 ++#define PHS12 3 ++#define PHS20 4 ++#define PHS21 5 ++#define PHS22 6 ++ ++#define CANTCON _SFR_MEM8(0xE5) ++#define TPRSC0 0 ++#define TPRSC1 1 ++#define TPRSC2 2 ++#define TPRSC3 3 ++#define TPRSC4 4 ++#define TPRSC5 5 ++#define TPRSC6 6 ++#define TPRSC7 7 ++ ++#define CANTIM _SFR_MEM16(0xE6) ++ ++#define CANTIML _SFR_MEM8(0xE6) ++#define CANTIM0 0 ++#define CANTIM1 1 ++#define CANTIM2 2 ++#define CANTIM3 3 ++#define CANTIM4 4 ++#define CANTIM5 5 ++#define CANTIM6 6 ++#define CANTIM7 7 ++ ++#define CANTIMH _SFR_MEM8(0xE7) ++#define CANTIM8 0 ++#define CANTIM9 1 ++#define CANTIM10 2 ++#define CANTIM11 3 ++#define CANTIM12 4 ++#define CANTIM13 5 ++#define CANTIM14 6 ++#define CANTIM15 7 ++ ++#define CANTTC _SFR_MEM16(0xE8) ++ ++#define CANTTCL _SFR_MEM8(0xE8) ++#define TIMTCC0 0 ++#define TIMTCC1 1 ++#define TIMTCC2 2 ++#define TIMTCC3 3 ++#define TIMTCC4 4 ++#define TIMTCC5 5 ++#define TIMTCC6 6 ++#define TIMTCC7 7 ++ ++#define CANTTCH _SFR_MEM8(0xE9) ++#define TIMTCC8 0 ++#define TIMTCC9 1 ++#define TIMTCC10 2 ++#define TIMTCC11 3 ++#define TIMTCC12 4 ++#define TIMTCC13 5 ++#define TIMTCC14 6 ++#define TIMTCC15 7 ++ ++#define CANTEC _SFR_MEM8(0xEA) ++#define TEC0 0 ++#define TEC1 1 ++#define TEC2 2 ++#define TEC3 3 ++#define TEC4 4 ++#define TEC5 5 ++#define TEC6 6 ++#define TEC7 7 ++ ++#define CANREC _SFR_MEM8(0xEB) ++#define REC0 0 ++#define REC1 1 ++#define REC2 2 ++#define REC3 3 ++#define REC4 4 ++#define REC5 5 ++#define REC6 6 ++#define REC7 7 ++ ++#define CANHPMOB _SFR_MEM8(0xEC) ++#define CGP0 0 ++#define CGP1 1 ++#define CGP2 2 ++#define CGP3 3 ++#define HPMOB0 4 ++#define HPMOB1 5 ++#define HPMOB2 6 ++#define HPMOB3 7 ++ ++#define CANPAGE _SFR_MEM8(0xED) ++#define INDX0 0 ++#define INDX1 1 ++#define INDX2 2 ++#define AINC 3 ++#define MOBNB0 4 ++#define MOBNB1 5 ++#define MOBNB2 6 ++#define MOBNB3 7 ++ ++#define CANSTMOB _SFR_MEM8(0xEE) ++#define AERR 0 ++#define FERR 1 ++#define CERR 2 ++#define SERR 3 ++#define BERR 4 ++#define RXOK 5 ++#define TXOK 6 ++#define DLCW 7 ++ ++#define CANCDMOB _SFR_MEM8(0xEF) ++#define DLC0 0 ++#define DLC1 1 ++#define DLC2 2 ++#define DLC3 3 ++#define IDE 4 ++#define RPLV 5 ++#define CONMOB0 6 ++#define CONMOB1 7 ++ ++/* RegDef: CAN Identifier Tag Registers*/ ++#define CANIDT _SFR_MEM32(0xF0) ++ ++#define CANIDT4 _SFR_MEM8(0xF0) ++#define RB0TAG 0 ++#define RB1TAG 1 ++#define RTRTAG 2 ++#define IDT0 3 ++#define IDT1 4 ++#define IDT2 5 ++#define IDT3 6 ++#define IDT4 7 ++ ++#define CANIDT3 _SFR_MEM8(0xF1) ++#define IDT5 0 ++#define IDT6 1 ++#define IDT7 2 ++#define IDT8 3 ++#define IDT9 4 ++#define IDT10 5 ++#define IDT11 6 ++#define IDT12 7 ++ ++#define CANIDT2 _SFR_MEM8(0xF2) ++#define IDT13 0 ++#define IDT14 1 ++#define IDT15 2 ++#define IDT16 3 ++#define IDT17 4 ++#define IDT18 5 ++#define IDT19 6 ++#define IDT20 7 ++ ++#define CANIDT1 _SFR_MEM8(0xF3) ++#define IDT21 0 ++#define IDT22 1 ++#define IDT23 2 ++#define IDT24 3 ++#define IDT25 4 ++#define IDT26 5 ++#define IDT27 6 ++#define IDT28 7 ++ ++/* RegDef: CAN Identifier Mask Registers */ ++#define CANIDM _SFR_MEM32(0xF4) ++ ++#define CANIDM4 _SFR_MEM8(0xF4) ++#define IDEMSK 0 ++#define RTRMSK 2 ++#define IDMSK0 3 ++#define IDMSK1 4 ++#define IDMSK2 5 ++#define IDMSK3 6 ++#define IDMSK4 7 ++ ++#define CANIDM3 _SFR_MEM8(0xF5) ++#define IDMSK5 0 ++#define IDMSK6 1 ++#define IDMSK7 2 ++#define IDMSK8 3 ++#define IDMSK9 4 ++#define IDMSK10 5 ++#define IDMSK11 6 ++#define IDMSK12 7 ++ ++#define CANIDM2 _SFR_MEM8(0xF6) ++#define IDMSK13 0 ++#define IDMSK14 1 ++#define IDMSK15 2 ++#define IDMSK16 3 ++#define IDMSK17 4 ++#define IDMSK18 5 ++#define IDMSK19 6 ++#define IDMSK20 7 ++ ++#define CANIDM1 _SFR_MEM8(0xF7) ++#define IDMSK21 0 ++#define IDMSK22 1 ++#define IDMSK23 2 ++#define IDMSK24 3 ++#define IDMSK25 4 ++#define IDMSK26 5 ++#define IDMSK27 6 ++#define IDMSK28 7 ++ ++#define CANSTM _SFR_MEM16(0xF8) ++ ++#define CANSTML _SFR_MEM8(0xF8) ++#define TIMSTM0 0 ++#define TIMSTM1 1 ++#define TIMSTM2 2 ++#define TIMSTM3 3 ++#define TIMSTM4 4 ++#define TIMSTM5 5 ++#define TIMSTM6 6 ++#define TIMSTM7 7 ++ ++#define CANSTMH _SFR_MEM8(0xF9) ++#define TIMSTM8 0 ++#define TIMSTM9 1 ++#define TIMSTM10 2 ++#define TIMSTM11 3 ++#define TIMSTM12 4 ++#define TIMSTM13 5 ++#define TIMSTM14 6 ++#define TIMSTM15 7 ++ ++#define CANMSG _SFR_MEM8(0xFA) ++#define MSG0 0 ++#define MSG1 1 ++#define MSG2 2 ++#define MSG3 3 ++#define MSG4 4 ++#define MSG5 5 ++#define MSG6 6 ++#define MSG7 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define ANACOMP0_vect_num 1 ++#define ANACOMP0_vect _VECTOR(1) /* Analog Comparator 0 */ ++#define ANACOMP1_vect_num 2 ++#define ANACOMP1_vect _VECTOR(2) /* Analog Comparator 1 */ ++#define ANACOMP2_vect_num 3 ++#define ANACOMP2_vect _VECTOR(3) /* Analog Comparator 2 */ ++#define ANACOMP3_vect_num 4 ++#define ANACOMP3_vect _VECTOR(4) /* Analog Comparator 3 */ ++#define PSC_FAULT_vect_num 5 ++#define PSC_FAULT_vect _VECTOR(5) /* PSC Fault */ ++#define PSC_EC_vect_num 6 ++#define PSC_EC_vect _VECTOR(6) /* PSC End of Cycle */ ++#define INT0_vect_num 7 ++#define INT0_vect _VECTOR(7) /* External Interrupt Request 0 */ ++#define INT1_vect_num 8 ++#define INT1_vect _VECTOR(8) /* External Interrupt Request 1 */ ++#define INT2_vect_num 9 ++#define INT2_vect _VECTOR(9) /* External Interrupt Request 2 */ ++#define INT3_vect_num 10 ++#define INT3_vect _VECTOR(10) /* External Interrupt Request 3 */ ++#define TIMER1_CAPT_vect_num 11 ++#define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */ ++#define TIMER1_COMPA_vect_num 12 ++#define TIMER1_COMPA_vect _VECTOR(12) /* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPB_vect_num 13 ++#define TIMER1_COMPB_vect _VECTOR(13) /* Timer/Counter1 Compare Match B */ ++#define TIMER1_OVF_vect_num 14 ++#define TIMER1_OVF_vect _VECTOR(14) /* Timer1/Counter1 Overflow */ ++#define TIMER0_COMPA_vect_num 15 ++#define TIMER0_COMPA_vect _VECTOR(15) /* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPB_vect_num 16 ++#define TIMER0_COMPB_vect _VECTOR(16) /* Timer/Counter0 Compare Match B */ ++#define TIMER0_OVF_vect_num 17 ++#define TIMER0_OVF_vect _VECTOR(17) /* Timer/Counter0 Overflow */ ++#define CAN_INT_vect_num 18 ++#define CAN_INT_vect _VECTOR(18) /* CAN MOB, Burst, General Errors */ ++#define CAN_TOVF_vect_num 19 ++#define CAN_TOVF_vect _VECTOR(19) /* CAN Timer Overflow */ ++#define LIN_TC_vect_num 20 ++#define LIN_TC_vect _VECTOR(20) /* LIN Transfer Complete */ ++#define LIN_ERR_vect_num 21 ++#define LIN_ERR_vect _VECTOR(21) /* LIN Error */ ++#define PCINT0_vect_num 22 ++#define PCINT0_vect _VECTOR(22) /* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect_num 23 ++#define PCINT1_vect _VECTOR(23) /* Pin Change Interrupt Request 1 */ ++#define PCINT2_vect_num 24 ++#define PCINT2_vect _VECTOR(24) /* Pin Change Interrupt Request 2 */ ++#define PCINT3_vect_num 25 ++#define PCINT3_vect _VECTOR(25) /* Pin Change Interrupt Request 3 */ ++#define SPI_STC_vect_num 26 ++#define SPI_STC_vect _VECTOR(26) /* SPI Serial Transfer Complete */ ++#define ADC_vect_num 27 ++#define ADC_vect _VECTOR(27) /* ADC Conversion Complete */ ++#define WDT_vect_num 28 ++#define WDT_vect _VECTOR(28) /* Watchdog Time-Out Interrupt */ ++#define EE_READY_vect_num 29 ++#define EE_READY_vect _VECTOR(29) /* EEPROM Ready */ ++#define SPM_READY_vect_num 30 ++#define SPM_READY_vect _VECTOR(30) /* Store Program Memory Read */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (31 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (128) ++#define RAMSTART (0x0100) ++#define RAMSIZE (2048) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (0x0) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x3FF) ++#define E2PAGESIZE (4) ++#define FLASHEND (0x7FFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector Trigger Level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector Trigger Level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector Trigger Level */ ++#define FUSE_PSCRVB (unsigned char)~_BV(3) /* PSC Outputs xB Reset Value */ ++#define FUSE_PSCRVA (unsigned char)~_BV(4) /* PSC Outputs xA Reset Value */ ++#define FUSE_PSCRB (unsigned char)~_BV(5) /* PSC Reset Behavior */ ++#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_BODLEVEL1) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x86 ++ ++ ++#endif /* _AVR_ATmega32C1_H_ */ ++ +diff --git a/include/avr/iom32hvb.h b/include/avr/iom32hvb.h +index c63c4f0..1923ae6 100644 +--- a/include/avr/iom32hvb.h ++++ b/include/avr/iom32hvb.h +@@ -1,1039 +1,1039 @@ +-/* Copyright (c) 2011 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom32hvb.h 2211 2011-02-14 14:04:25Z aboyapati $ */ +- +-/* avr/iom32hvb.h - definitions for ATmega32HVB */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom32hvb.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATmega32HVB_H_ +-#define _AVR_ATmega32HVB_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +- +-#define PORTA _SFR_IO8(0x02) +-#define PORTA0 0 +-#define PORTA1 1 +-#define PORTA2 2 +-#define PORTA3 3 +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC3 3 +-#define PORTC4 4 +-#define PORTC5 5 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +-#define ICF0 3 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 3 +- +-#define OSICSR _SFR_IO8(0x17) +-#define OSIEN 0 +-#define OSIST 1 +-#define OSISEL0 4 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +-#define PCIF1 1 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +-#define INTF2 2 +-#define INTF3 3 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +-#define INT2 2 +-#define INT3 3 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +-#define EEAR9 1 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSRSYNC 0 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define ICS0 3 +-#define ICES0 4 +-#define ICNC0 5 +-#define ICEN0 6 +-#define TCW0 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +- +-#define TCNT0 _SFR_IO16(0x26) +- +-#define TCNT0L _SFR_IO8(0x26) +-#define TCNT0L0 0 +-#define TCNT0L1 1 +-#define TCNT0L2 2 +-#define TCNT0L3 3 +-#define TCNT0L4 4 +-#define TCNT0L5 5 +-#define TCNT0L6 6 +-#define TCNT0L7 7 +- +-#define TCNT0H _SFR_IO8(0x27) +-#define TCNT0H0 0 +-#define TCNT0H1 1 +-#define TCNT0H2 2 +-#define TCNT0H3 3 +-#define TCNT0H4 4 +-#define TCNT0H5 5 +-#define TCNT0H6 6 +-#define TCNT0H7 7 +- +-#define OCR0A _SFR_IO8(0x28) +-#define OCR0A0 0 +-#define OCR0A1 1 +-#define OCR0A2 2 +-#define OCR0A3 3 +-#define OCR0A4 4 +-#define OCR0A5 5 +-#define OCR0A6 6 +-#define OCR0A7 7 +- +-#define OCR0B _SFR_IO8(0x29) +-#define OCR0B0 0 +-#define OCR0B1 1 +-#define OCR0B2 2 +-#define OCR0B3 3 +-#define OCR0B4 4 +-#define OCR0B5 5 +-#define OCR0B6 6 +-#define OCR0B7 7 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define DWDR _SFR_IO8(0x31) +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BODRF 2 +-#define WDRF 3 +-#define OCDRF 4 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define CKOE 5 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define LBSET 3 +-#define RWWSRE 4 +-#define SIGRD 5 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPCE 7 +- +-#define PRR0 _SFR_MEM8(0x64) +-#define PRVADC 0 +-#define PRTIM0 1 +-#define PRTIM1 2 +-#define PRSPI 3 +-#define PRVRM 5 +-#define PRTWI 6 +- +-#define FOSCCAL _SFR_MEM8(0x66) +-#define FCAL0 0 +-#define FCAL1 1 +-#define FCAL2 2 +-#define FCAL3 3 +-#define FCAL4 4 +-#define FCAL5 5 +-#define FCAL6 6 +-#define FCAL7 7 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +-#define PCIE1 1 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define ISC20 4 +-#define ISC21 5 +-#define ISC30 6 +-#define ISC31 7 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT4 0 +-#define PCINT5 1 +-#define PCINT6 2 +-#define PCINT7 3 +-#define PCINT8 4 +-#define PCINT9 5 +-#define PCINT10 6 +-#define PCINT11 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +-#define ICIE0 3 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 3 +- +-#define VADC _SFR_MEM16(0x78) +- +-#define VADCL _SFR_MEM8(0x78) +-#define VADC0 0 +-#define VADC1 1 +-#define VADC2 2 +-#define VADC3 3 +-#define VADC4 4 +-#define VADC5 5 +-#define VADC6 6 +-#define VADC7 7 +- +-#define VADCH _SFR_MEM8(0x79) +-#define VADC8 0 +-#define VADC9 1 +-#define VADC10 2 +-#define VADC11 3 +- +-#define VADCSR _SFR_MEM8(0x7A) +-#define VADCCIE 0 +-#define VADCCIF 1 +-#define VADSC 2 +-#define VADEN 3 +- +-#define VADMUX _SFR_MEM8(0x7C) +-#define VADMUX0 0 +-#define VADMUX1 1 +-#define VADMUX2 2 +-#define VADMUX3 3 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define PA0DID 0 +-#define PA1DID 1 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define ICS1 3 +-#define ICES1 4 +-#define ICNC1 5 +-#define ICEN1 6 +-#define TCW1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define OCR1A _SFR_MEM8(0x88) +-#define OCR1A0 0 +-#define OCR1A1 1 +-#define OCR1A2 2 +-#define OCR1A3 3 +-#define OCR1A4 4 +-#define OCR1A5 5 +-#define OCR1A6 6 +-#define OCR1A7 7 +- +-#define OCR1B _SFR_MEM8(0x89) +-#define OCR1B0 0 +-#define OCR1B1 1 +-#define OCR1B2 2 +-#define OCR1B3 3 +-#define OCR1B4 4 +-#define OCR1B5 5 +-#define OCR1B6 6 +-#define OCR1B7 7 +- +-#define TWBR _SFR_MEM8(0xB8) +-#define TWBR0 0 +-#define TWBR1 1 +-#define TWBR2 2 +-#define TWBR3 3 +-#define TWBR4 4 +-#define TWBR5 5 +-#define TWBR6 6 +-#define TWBR7 7 +- +-#define TWSR _SFR_MEM8(0xB9) +-#define TWPS0 0 +-#define TWPS1 1 +-#define TWS3 3 +-#define TWS4 4 +-#define TWS5 5 +-#define TWS6 6 +-#define TWS7 7 +- +-#define TWAR _SFR_MEM8(0xBA) +-#define TWGCE 0 +-#define TWA0 1 +-#define TWA1 2 +-#define TWA2 3 +-#define TWA3 4 +-#define TWA4 5 +-#define TWA5 6 +-#define TWA6 7 +- +-#define TWDR _SFR_MEM8(0xBB) +-#define TWD0 0 +-#define TWD1 1 +-#define TWD2 2 +-#define TWD3 3 +-#define TWD4 4 +-#define TWD5 5 +-#define TWD6 6 +-#define TWD7 7 +- +-#define TWCR _SFR_MEM8(0xBC) +-#define TWIE 0 +-#define TWEN 2 +-#define TWWC 3 +-#define TWSTO 4 +-#define TWSTA 5 +-#define TWEA 6 +-#define TWINT 7 +- +-#define TWAMR _SFR_MEM8(0xBD) +-#define TWAM0 1 +-#define TWAM1 2 +-#define TWAM2 3 +-#define TWAM3 4 +-#define TWAM4 5 +-#define TWAM5 6 +-#define TWAM6 7 +- +-#define TWBCSR _SFR_MEM8(0xBE) +-#define TWBCIP 0 +-#define TWBDT0 1 +-#define TWBDT1 2 +-#define TWBCIE 6 +-#define TWBCIF 7 +- +-#define ROCR _SFR_MEM8(0xC8) +-#define ROCWIE 0 +-#define ROCWIF 1 +-#define ROCD 4 +-#define ROCS 7 +- +-#define BGCCR _SFR_MEM8(0xD0) +-#define BGCC0 0 +-#define BGCC1 1 +-#define BGCC2 2 +-#define BGCC3 3 +-#define BGCC4 4 +-#define BGCC5 5 +- +-#define BGCRR _SFR_MEM8(0xD1) +-#define BGCR0 0 +-#define BGCR1 1 +-#define BGCR2 2 +-#define BGCR3 3 +-#define BGCR4 4 +-#define BGCR5 5 +-#define BGCR6 6 +-#define BGCR7 7 +- +-#define BGCSR _SFR_MEM8(0xD2) +-#define BGSCDIE 0 +-#define BGSCDIF 1 +-#define BGSCDE 4 +-#define BGD 5 +- +-#define CHGDCSR _SFR_MEM8(0xD4) +-#define CHGDIE 0 +-#define CHGDIF 1 +-#define CHGDISC0 2 +-#define CHGDISC1 3 +-#define BATTPVL 4 +- +-#define CADAC0 _SFR_MEM8(0xE0) +-#define CADAC00 0 +-#define CADAC01 1 +-#define CADAC02 2 +-#define CADAC03 3 +-#define CADAC04 4 +-#define CADAC05 5 +-#define CADAC06 6 +-#define CADAC07 7 +- +-#define CADAC1 _SFR_MEM8(0xE1) +-#define CADAC08 0 +-#define CADAC09 1 +-#define CADAC10 2 +-#define CADAC11 3 +-#define CADAC12 4 +-#define CADAC13 5 +-#define CADAC14 6 +-#define CADAC15 7 +- +-#define CADAC2 _SFR_MEM8(0xE2) +-#define CADAC16 0 +-#define CADAC17 1 +-#define CADAC18 2 +-#define CADAC19 3 +-#define CADAC20 4 +-#define CADAC21 5 +-#define CADAC22 6 +-#define CADAC23 7 +- +-#define CADAC3 _SFR_MEM8(0xE3) +-#define CADAC24 0 +-#define CADAC25 1 +-#define CADAC26 2 +-#define CADAC27 3 +-#define CADAC28 4 +-#define CADAC29 5 +-#define CADAC30 6 +-#define CADAC31 7 +- +-#define CADIC _SFR_MEM16(0xE4) +- +-#define CADICL _SFR_MEM8(0xE4) +-#define CADICL0 0 +-#define CADICL1 1 +-#define CADICL2 2 +-#define CADICL3 3 +-#define CADICL4 4 +-#define CADICL5 5 +-#define CADICL6 6 +-#define CADICL7 7 +- +-#define CADICH _SFR_MEM8(0xE5) +-#define CADICH0 0 +-#define CADICH1 1 +-#define CADICH2 2 +-#define CADICH3 3 +-#define CADICH4 4 +-#define CADICH5 5 +-#define CADICH6 6 +-#define CADICH7 7 +- +-#define CADCSRA _SFR_MEM8(0xE6) +-#define CADSE 0 +-#define CADSI0 1 +-#define CADSI1 2 +-#define CADAS0 3 +-#define CADAS1 4 +-#define CADUB 5 +-#define CADPOL 6 +-#define CADEN 7 +- +-#define CADCSRB _SFR_MEM8(0xE7) +-#define CADICIF 0 +-#define CADRCIF 1 +-#define CADACIF 2 +-#define CADICIE 4 +-#define CADRCIE 5 +-#define CADACIE 6 +- +-#define CADCSRC _SFR_MEM8(0xE8) +-#define CADVSE 0 +- +-#define CADRCC _SFR_MEM8(0xE9) +-#define CADRCC0 0 +-#define CADRCC1 1 +-#define CADRCC2 2 +-#define CADRCC3 3 +-#define CADRCC4 4 +-#define CADRCC5 5 +-#define CADRCC6 6 +-#define CADRCC7 7 +- +-#define CADRDC _SFR_MEM8(0xEA) +-#define CADRDC0 0 +-#define CADRDC1 1 +-#define CADRDC2 2 +-#define CADRDC3 3 +-#define CADRDC4 4 +-#define CADRDC5 5 +-#define CADRDC6 6 +-#define CADRDC7 7 +- +-#define FCSR _SFR_MEM8(0xF0) +-#define CFE 0 +-#define DFE 1 +-#define CPS 2 +-#define DUVRD 3 +- +-#define CBCR _SFR_MEM8(0xF1) +-#define CBE1 0 +-#define CBE2 1 +-#define CBE3 2 +-#define CBE4 3 +- +-#define BPIMSK _SFR_MEM8(0xF2) +-#define CHCIE 0 +-#define DHCIE 1 +-#define COCIE 2 +-#define DOCIE 3 +-#define SCIE 4 +- +-#define BPIFR _SFR_MEM8(0xF3) +-#define CHCIF 0 +-#define DHCIF 1 +-#define COCIF 2 +-#define DOCIF 3 +-#define SCIF 4 +- +-#define BPSCD _SFR_MEM8(0xF5) +-#define SCDL0 0 +-#define SCDL1 1 +-#define SCDL2 2 +-#define SCDL3 3 +-#define SCDL4 4 +-#define SCDL5 5 +-#define SCDL6 6 +-#define SCDL7 7 +- +-#define BPDOCD _SFR_MEM8(0xF6) +-#define DOCDL0 0 +-#define DOCDL1 1 +-#define DOCDL2 2 +-#define DOCDL3 3 +-#define DOCDL4 4 +-#define DOCDL5 5 +-#define DOCDL6 6 +-#define DOCDL7 7 +- +-#define BPCOCD _SFR_MEM8(0xF7) +-#define COCDL0 0 +-#define COCDL1 1 +-#define COCDL2 2 +-#define COCDL3 3 +-#define COCDL4 4 +-#define COCDL5 5 +-#define COCDL6 6 +-#define COCDL7 7 +- +-#define BPDHCD _SFR_MEM8(0xF8) +-#define DHCDL0 0 +-#define DHCDL1 1 +-#define DHCDL2 2 +-#define DHCDL3 3 +-#define DHCDL4 4 +-#define DHCDL5 5 +-#define DHCDL6 6 +-#define DHCDL7 7 +- +-#define BPCHCD _SFR_MEM8(0xF9) +-#define CHCDL0 0 +-#define CHCDL1 1 +-#define CHCDL2 2 +-#define CHCDL3 3 +-#define CHCDL4 4 +-#define CHCDL5 5 +-#define CHCDL6 6 +-#define CHCDL7 7 +- +-#define BPSCTR _SFR_MEM8(0xFA) +-#define SCPT0 0 +-#define SCPT1 1 +-#define SCPT2 2 +-#define SCPT3 3 +-#define SCPT4 4 +-#define SCPT5 5 +-#define SCPT6 6 +- +-#define BPOCTR _SFR_MEM8(0xFB) +-#define OCPT0 0 +-#define OCPT1 1 +-#define OCPT2 2 +-#define OCPT3 3 +-#define OCPT4 4 +-#define OCPT5 5 +- +-#define BPHCTR _SFR_MEM8(0xFC) +-#define HCPT0 0 +-#define HCPT1 1 +-#define HCPT2 2 +-#define HCPT3 3 +-#define HCPT4 4 +-#define HCPT5 5 +- +-#define BPCR _SFR_MEM8(0xFD) +-#define CHCD 0 +-#define DHCD 1 +-#define COCD 2 +-#define DOCD 3 +-#define SCD 4 +-#define EPID 5 +- +-#define BPPLR _SFR_MEM8(0xFE) +-#define BPPL 0 +-#define BPPLE 1 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define BPINT_vect_num 1 +-#define BPINT_vect _VECTOR(1) /* Battery Protection Interrupt */ +-#define VREGMON_vect_num 2 +-#define VREGMON_vect _VECTOR(2) /* Voltage regulator monitor interrupt */ +-#define INT0_vect_num 3 +-#define INT0_vect _VECTOR(3) /* External Interrupt Request 0 */ +-#define INT1_vect_num 4 +-#define INT1_vect _VECTOR(4) /* External Interrupt Request 1 */ +-#define INT2_vect_num 5 +-#define INT2_vect _VECTOR(5) /* External Interrupt Request 2 */ +-#define INT3_vect_num 6 +-#define INT3_vect _VECTOR(6) /* External Interrupt Request 3 */ +-#define PCINT0_vect_num 7 +-#define PCINT0_vect _VECTOR(7) /* Pin Change Interrupt 0 */ +-#define PCINT1_vect_num 8 +-#define PCINT1_vect _VECTOR(8) /* Pin Change Interrupt 1 */ +-#define WDT_vect_num 9 +-#define WDT_vect _VECTOR(9) /* Watchdog Timeout Interrupt */ +-#define BGSCD_vect_num 10 +-#define BGSCD_vect _VECTOR(10) /* Bandgap Buffer Short Circuit Detected */ +-#define CHDET_vect_num 11 +-#define CHDET_vect _VECTOR(11) /* Charger Detect */ +-#define TIMER1_IC_vect_num 12 +-#define TIMER1_IC_vect _VECTOR(12) /* Timer 1 Input capture */ +-#define TIMER1_COMPA_vect_num 13 +-#define TIMER1_COMPA_vect _VECTOR(13) /* Timer 1 Compare Match A */ +-#define TIMER1_COMPB_vect_num 14 +-#define TIMER1_COMPB_vect _VECTOR(14) /* Timer 1 Compare Match B */ +-#define TIMER1_OVF_vect_num 15 +-#define TIMER1_OVF_vect _VECTOR(15) /* Timer 1 overflow */ +-#define TIMER0_IC_vect_num 16 +-#define TIMER0_IC_vect _VECTOR(16) /* Timer 0 Input Capture */ +-#define TIMER0_COMPA_vect_num 17 +-#define TIMER0_COMPA_vect _VECTOR(17) /* Timer 0 Comapre Match A */ +-#define TIMER0_COMPB_vect_num 18 +-#define TIMER0_COMPB_vect _VECTOR(18) /* Timer 0 Compare Match B */ +-#define TIMER0_OVF_vect_num 19 +-#define TIMER0_OVF_vect _VECTOR(19) /* Timer 0 Overflow */ +-#define TWIBUSCD_vect_num 20 +-#define TWIBUSCD_vect _VECTOR(20) /* Two-Wire Bus Connect/Disconnect */ +-#define TWI_vect_num 21 +-#define TWI_vect _VECTOR(21) /* Two-Wire Serial Interface */ +-#define SPI_STC_vect_num 22 +-#define SPI_STC_vect _VECTOR(22) /* SPI Serial transfer complete */ +-#define VADC_vect_num 23 +-#define VADC_vect _VECTOR(23) /* Voltage ADC Conversion Complete */ +-#define CCADC_CONV_vect_num 24 +-#define CCADC_CONV_vect _VECTOR(24) /* Coulomb Counter ADC Conversion Complete */ +-#define CCADC_REG_CUR_vect_num 25 +-#define CCADC_REG_CUR_vect _VECTOR(25) /* Coloumb Counter ADC Regular Current */ +-#define CCADC_ACC_vect_num 26 +-#define CCADC_ACC_vect _VECTOR(26) /* Coloumb Counter ADC Accumulator */ +-#define EE_READY_vect_num 27 +-#define EE_READY_vect _VECTOR(27) /* EEPROM Ready */ +-#define SPM_vect_num 28 +-#define SPM_vect _VECTOR(28) /* SPM Ready */ +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (29 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (128) +-#define RAMSTART (0x100) +-#define RAMSIZE (2048) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (NA) +-#define XRAMEND (RAMEND) +-#define E2END (0x3FF) +-#define E2PAGESIZE (4) +-#define FLASHEND (0x7FFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 2 +- +-/* Low Fuse Byte */ +-#define FUSE_OSCSEL0 (unsigned char)~_BV(0) /* Oscillator Select */ +-#define FUSE_OSCSEL1 (unsigned char)~_BV(1) /* Oscillator Select */ +-#define FUSE_SUT0 (unsigned char)~_BV(2) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(3) /* Select start-up time */ +-#define FUSE_SUT2 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_EESAVE (unsigned char)~_BV(6) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(7) /* Watchdog Timer Always On */ +-#define LFUSE_DEFAULT (FUSE_SPIEN & FUSE_OSCSEL0) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_DWEN (unsigned char)~_BV(3) /* Enable debugWire */ +-#define FUSE_CKDIV (unsigned char)~_BV(4) /* CKDIV Register */ +-#define HFUSE_DEFAULT (FUSE_CKDIV & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x95 +-#define SIGNATURE_2 0x10 +- +- +-/* Device Pin Definitions */ +-#define PV2_DDR DDRV +-#define PV2_PORT PORTV +-#define PV2_PIN PINV +-#define PV2_BIT 2 +- +-#define PV1_DDR DDRV +-#define PV1_PORT PORTV +-#define PV1_PIN PINV +-#define PV1_BIT 1 +- +-#define NV_DDR DDRNV +-#define NV_PORT PORTNV +-#define NV_PIN PINNV +-#define NV_BIT NV +- +-#define VFET_DDR DDRVFET +-#define VFET_PORT PORTVFET +-#define VFET_PIN PINVFET +-#define VFET_BIT VFET +- +-#define CF1P_DDR DDRCF1P +-#define CF1P_PORT PORTCF1P +-#define CF1P_PIN PINCF1P +-#define CF1P_BIT CF1P +- +-#define CF1N_DDR DDRCF1N +-#define CF1N_PORT PORTCF1N +-#define CF1N_PIN PINCF1N +-#define CF1N_BIT CF1N +- +-#define CF2P_DDR DDRCF2P +-#define CF2P_PORT PORTCF2P +-#define CF2P_PIN PINCF2P +-#define CF2P_BIT CF2P +- +-#define CF2N_DDR DDRCF2N +-#define CF2N_PORT PORTCF2N +-#define CF2N_PIN PINCF2N +-#define CF2N_BIT CF2N +- +-#define VREG_DDR DDRVREG +-#define VREG_PORT PORTVREG +-#define VREG_PIN PINVREG +-#define VREG_BIT VREG +- +-#define VREF_DDR DDRVREF +-#define VREF_PORT PORTVREF +-#define VREF_PIN PINVREF +-#define VREF_BIT VREF +- +-#define VREF_DDR DDRVREFGND +-#define VREF_PORT PORTVREFGND +-#define VREF_PIN PINVREFGND +-#define VREF_BIT VREFGND +- +-#define PI_DDR DDRI +-#define PI_PORT PORTI +-#define PI_PIN PINI +-#define PI_BIT +- +-#define NI_DDR DDRNI +-#define NI_PORT PORTNI +-#define NI_PIN PINNI +-#define NI_BIT NI +- +-#define PA0_DDR DDRA +-#define PA0_PORT PORTA +-#define PA0_PIN PINA +-#define PA0_BIT 0 +- +-#define PA1_DDR DDRA +-#define PA1_PORT PORTA +-#define PA1_PIN PINA +-#define PA1_BIT 1 +- +-#define PA2_DDR DDRA +-#define PA2_PORT PORTA +-#define PA2_PIN PINA +-#define PA2_BIT 2 +- +-#define PB0_DDR DDRB +-#define PB0_PORT PORTB +-#define PB0_PIN PINB +-#define PB0_BIT 0 +- +-#define PB1_DDR DDRB +-#define PB1_PORT PORTB +-#define PB1_PIN PINB +-#define PB1_BIT 1 +- +-#define PB2_DDR DDRB +-#define PB2_PORT PORTB +-#define PB2_PIN PINB +-#define PB2_BIT 2 +- +-#define PB3_DDR DDRB +-#define PB3_PORT PORTB +-#define PB3_PIN PINB +-#define PB3_BIT 3 +- +-#define PC0_DDR DDRC +-#define PC0_PORT PORTC +-#define PC0_PIN PINC +-#define PC0_BIT 0 +- +-#define BATT_DDR DDRBATT +-#define BATT_PORT PORTBATT +-#define BATT_PIN PINBATT +-#define BATT_BIT BATT +- +-#define OC_DDR DDROC +-#define OC_PORT PORTOC +-#define OC_PIN PINOC +-#define OC_BIT OC +- +-#endif /* _AVR_ATmega32HVB_H_ */ +- ++/* Copyright (c) 2011 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom32hvb.h 2211 2011-02-14 14:04:25Z aboyapati $ */ ++ ++/* avr/iom32hvb.h - definitions for ATmega32HVB */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom32hvb.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATmega32HVB_H_ ++#define _AVR_ATmega32HVB_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA0 0 ++#define PORTA1 1 ++#define PORTA2 2 ++#define PORTA3 3 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC3 3 ++#define PORTC4 4 ++#define PORTC5 5 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++#define ICF0 3 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 3 ++ ++#define OSICSR _SFR_IO8(0x17) ++#define OSIEN 0 ++#define OSIST 1 ++#define OSISEL0 4 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++#define INT3 3 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++#define EEAR9 1 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define ICS0 3 ++#define ICES0 4 ++#define ICNC0 5 ++#define ICEN0 6 ++#define TCW0 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++ ++#define TCNT0 _SFR_IO16(0x26) ++ ++#define TCNT0L _SFR_IO8(0x26) ++#define TCNT0L0 0 ++#define TCNT0L1 1 ++#define TCNT0L2 2 ++#define TCNT0L3 3 ++#define TCNT0L4 4 ++#define TCNT0L5 5 ++#define TCNT0L6 6 ++#define TCNT0L7 7 ++ ++#define TCNT0H _SFR_IO8(0x27) ++#define TCNT0H0 0 ++#define TCNT0H1 1 ++#define TCNT0H2 2 ++#define TCNT0H3 3 ++#define TCNT0H4 4 ++#define TCNT0H5 5 ++#define TCNT0H6 6 ++#define TCNT0H7 7 ++ ++#define OCR0A _SFR_IO8(0x28) ++#define OCR0A0 0 ++#define OCR0A1 1 ++#define OCR0A2 2 ++#define OCR0A3 3 ++#define OCR0A4 4 ++#define OCR0A5 5 ++#define OCR0A6 6 ++#define OCR0A7 7 ++ ++#define OCR0B _SFR_IO8(0x29) ++#define OCR0B0 0 ++#define OCR0B1 1 ++#define OCR0B2 2 ++#define OCR0B3 3 ++#define OCR0B4 4 ++#define OCR0B5 5 ++#define OCR0B6 6 ++#define OCR0B7 7 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define DWDR _SFR_IO8(0x31) ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BODRF 2 ++#define WDRF 3 ++#define OCDRF 4 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define CKOE 5 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define LBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPCE 7 ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRVADC 0 ++#define PRTIM0 1 ++#define PRTIM1 2 ++#define PRSPI 3 ++#define PRVRM 5 ++#define PRTWI 6 ++ ++#define FOSCCAL _SFR_MEM8(0x66) ++#define FCAL0 0 ++#define FCAL1 1 ++#define FCAL2 2 ++#define FCAL3 3 ++#define FCAL4 4 ++#define FCAL5 5 ++#define FCAL6 6 ++#define FCAL7 7 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT4 0 ++#define PCINT5 1 ++#define PCINT6 2 ++#define PCINT7 3 ++#define PCINT8 4 ++#define PCINT9 5 ++#define PCINT10 6 ++#define PCINT11 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++#define ICIE0 3 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 3 ++ ++#define VADC _SFR_MEM16(0x78) ++ ++#define VADCL _SFR_MEM8(0x78) ++#define VADC0 0 ++#define VADC1 1 ++#define VADC2 2 ++#define VADC3 3 ++#define VADC4 4 ++#define VADC5 5 ++#define VADC6 6 ++#define VADC7 7 ++ ++#define VADCH _SFR_MEM8(0x79) ++#define VADC8 0 ++#define VADC9 1 ++#define VADC10 2 ++#define VADC11 3 ++ ++#define VADCSR _SFR_MEM8(0x7A) ++#define VADCCIE 0 ++#define VADCCIF 1 ++#define VADSC 2 ++#define VADEN 3 ++ ++#define VADMUX _SFR_MEM8(0x7C) ++#define VADMUX0 0 ++#define VADMUX1 1 ++#define VADMUX2 2 ++#define VADMUX3 3 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define PA0DID 0 ++#define PA1DID 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define ICS1 3 ++#define ICES1 4 ++#define ICNC1 5 ++#define ICEN1 6 ++#define TCW1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define OCR1A _SFR_MEM8(0x88) ++#define OCR1A0 0 ++#define OCR1A1 1 ++#define OCR1A2 2 ++#define OCR1A3 3 ++#define OCR1A4 4 ++#define OCR1A5 5 ++#define OCR1A6 6 ++#define OCR1A7 7 ++ ++#define OCR1B _SFR_MEM8(0x89) ++#define OCR1B0 0 ++#define OCR1B1 1 ++#define OCR1B2 2 ++#define OCR1B3 3 ++#define OCR1B4 4 ++#define OCR1B5 5 ++#define OCR1B6 6 ++#define OCR1B7 7 ++ ++#define TWBR _SFR_MEM8(0xB8) ++#define TWBR0 0 ++#define TWBR1 1 ++#define TWBR2 2 ++#define TWBR3 3 ++#define TWBR4 4 ++#define TWBR5 5 ++#define TWBR6 6 ++#define TWBR7 7 ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++#define TWD0 0 ++#define TWD1 1 ++#define TWD2 2 ++#define TWD3 3 ++#define TWD4 4 ++#define TWD5 5 ++#define TWD6 6 ++#define TWD7 7 ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++#define TWBCSR _SFR_MEM8(0xBE) ++#define TWBCIP 0 ++#define TWBDT0 1 ++#define TWBDT1 2 ++#define TWBCIE 6 ++#define TWBCIF 7 ++ ++#define ROCR _SFR_MEM8(0xC8) ++#define ROCWIE 0 ++#define ROCWIF 1 ++#define ROCD 4 ++#define ROCS 7 ++ ++#define BGCCR _SFR_MEM8(0xD0) ++#define BGCC0 0 ++#define BGCC1 1 ++#define BGCC2 2 ++#define BGCC3 3 ++#define BGCC4 4 ++#define BGCC5 5 ++ ++#define BGCRR _SFR_MEM8(0xD1) ++#define BGCR0 0 ++#define BGCR1 1 ++#define BGCR2 2 ++#define BGCR3 3 ++#define BGCR4 4 ++#define BGCR5 5 ++#define BGCR6 6 ++#define BGCR7 7 ++ ++#define BGCSR _SFR_MEM8(0xD2) ++#define BGSCDIE 0 ++#define BGSCDIF 1 ++#define BGSCDE 4 ++#define BGD 5 ++ ++#define CHGDCSR _SFR_MEM8(0xD4) ++#define CHGDIE 0 ++#define CHGDIF 1 ++#define CHGDISC0 2 ++#define CHGDISC1 3 ++#define BATTPVL 4 ++ ++#define CADAC0 _SFR_MEM8(0xE0) ++#define CADAC00 0 ++#define CADAC01 1 ++#define CADAC02 2 ++#define CADAC03 3 ++#define CADAC04 4 ++#define CADAC05 5 ++#define CADAC06 6 ++#define CADAC07 7 ++ ++#define CADAC1 _SFR_MEM8(0xE1) ++#define CADAC08 0 ++#define CADAC09 1 ++#define CADAC10 2 ++#define CADAC11 3 ++#define CADAC12 4 ++#define CADAC13 5 ++#define CADAC14 6 ++#define CADAC15 7 ++ ++#define CADAC2 _SFR_MEM8(0xE2) ++#define CADAC16 0 ++#define CADAC17 1 ++#define CADAC18 2 ++#define CADAC19 3 ++#define CADAC20 4 ++#define CADAC21 5 ++#define CADAC22 6 ++#define CADAC23 7 ++ ++#define CADAC3 _SFR_MEM8(0xE3) ++#define CADAC24 0 ++#define CADAC25 1 ++#define CADAC26 2 ++#define CADAC27 3 ++#define CADAC28 4 ++#define CADAC29 5 ++#define CADAC30 6 ++#define CADAC31 7 ++ ++#define CADIC _SFR_MEM16(0xE4) ++ ++#define CADICL _SFR_MEM8(0xE4) ++#define CADICL0 0 ++#define CADICL1 1 ++#define CADICL2 2 ++#define CADICL3 3 ++#define CADICL4 4 ++#define CADICL5 5 ++#define CADICL6 6 ++#define CADICL7 7 ++ ++#define CADICH _SFR_MEM8(0xE5) ++#define CADICH0 0 ++#define CADICH1 1 ++#define CADICH2 2 ++#define CADICH3 3 ++#define CADICH4 4 ++#define CADICH5 5 ++#define CADICH6 6 ++#define CADICH7 7 ++ ++#define CADCSRA _SFR_MEM8(0xE6) ++#define CADSE 0 ++#define CADSI0 1 ++#define CADSI1 2 ++#define CADAS0 3 ++#define CADAS1 4 ++#define CADUB 5 ++#define CADPOL 6 ++#define CADEN 7 ++ ++#define CADCSRB _SFR_MEM8(0xE7) ++#define CADICIF 0 ++#define CADRCIF 1 ++#define CADACIF 2 ++#define CADICIE 4 ++#define CADRCIE 5 ++#define CADACIE 6 ++ ++#define CADCSRC _SFR_MEM8(0xE8) ++#define CADVSE 0 ++ ++#define CADRCC _SFR_MEM8(0xE9) ++#define CADRCC0 0 ++#define CADRCC1 1 ++#define CADRCC2 2 ++#define CADRCC3 3 ++#define CADRCC4 4 ++#define CADRCC5 5 ++#define CADRCC6 6 ++#define CADRCC7 7 ++ ++#define CADRDC _SFR_MEM8(0xEA) ++#define CADRDC0 0 ++#define CADRDC1 1 ++#define CADRDC2 2 ++#define CADRDC3 3 ++#define CADRDC4 4 ++#define CADRDC5 5 ++#define CADRDC6 6 ++#define CADRDC7 7 ++ ++#define FCSR _SFR_MEM8(0xF0) ++#define CFE 0 ++#define DFE 1 ++#define CPS 2 ++#define DUVRD 3 ++ ++#define CBCR _SFR_MEM8(0xF1) ++#define CBE1 0 ++#define CBE2 1 ++#define CBE3 2 ++#define CBE4 3 ++ ++#define BPIMSK _SFR_MEM8(0xF2) ++#define CHCIE 0 ++#define DHCIE 1 ++#define COCIE 2 ++#define DOCIE 3 ++#define SCIE 4 ++ ++#define BPIFR _SFR_MEM8(0xF3) ++#define CHCIF 0 ++#define DHCIF 1 ++#define COCIF 2 ++#define DOCIF 3 ++#define SCIF 4 ++ ++#define BPSCD _SFR_MEM8(0xF5) ++#define SCDL0 0 ++#define SCDL1 1 ++#define SCDL2 2 ++#define SCDL3 3 ++#define SCDL4 4 ++#define SCDL5 5 ++#define SCDL6 6 ++#define SCDL7 7 ++ ++#define BPDOCD _SFR_MEM8(0xF6) ++#define DOCDL0 0 ++#define DOCDL1 1 ++#define DOCDL2 2 ++#define DOCDL3 3 ++#define DOCDL4 4 ++#define DOCDL5 5 ++#define DOCDL6 6 ++#define DOCDL7 7 ++ ++#define BPCOCD _SFR_MEM8(0xF7) ++#define COCDL0 0 ++#define COCDL1 1 ++#define COCDL2 2 ++#define COCDL3 3 ++#define COCDL4 4 ++#define COCDL5 5 ++#define COCDL6 6 ++#define COCDL7 7 ++ ++#define BPDHCD _SFR_MEM8(0xF8) ++#define DHCDL0 0 ++#define DHCDL1 1 ++#define DHCDL2 2 ++#define DHCDL3 3 ++#define DHCDL4 4 ++#define DHCDL5 5 ++#define DHCDL6 6 ++#define DHCDL7 7 ++ ++#define BPCHCD _SFR_MEM8(0xF9) ++#define CHCDL0 0 ++#define CHCDL1 1 ++#define CHCDL2 2 ++#define CHCDL3 3 ++#define CHCDL4 4 ++#define CHCDL5 5 ++#define CHCDL6 6 ++#define CHCDL7 7 ++ ++#define BPSCTR _SFR_MEM8(0xFA) ++#define SCPT0 0 ++#define SCPT1 1 ++#define SCPT2 2 ++#define SCPT3 3 ++#define SCPT4 4 ++#define SCPT5 5 ++#define SCPT6 6 ++ ++#define BPOCTR _SFR_MEM8(0xFB) ++#define OCPT0 0 ++#define OCPT1 1 ++#define OCPT2 2 ++#define OCPT3 3 ++#define OCPT4 4 ++#define OCPT5 5 ++ ++#define BPHCTR _SFR_MEM8(0xFC) ++#define HCPT0 0 ++#define HCPT1 1 ++#define HCPT2 2 ++#define HCPT3 3 ++#define HCPT4 4 ++#define HCPT5 5 ++ ++#define BPCR _SFR_MEM8(0xFD) ++#define CHCD 0 ++#define DHCD 1 ++#define COCD 2 ++#define DOCD 3 ++#define SCD 4 ++#define EPID 5 ++ ++#define BPPLR _SFR_MEM8(0xFE) ++#define BPPL 0 ++#define BPPLE 1 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define BPINT_vect_num 1 ++#define BPINT_vect _VECTOR(1) /* Battery Protection Interrupt */ ++#define VREGMON_vect_num 2 ++#define VREGMON_vect _VECTOR(2) /* Voltage regulator monitor interrupt */ ++#define INT0_vect_num 3 ++#define INT0_vect _VECTOR(3) /* External Interrupt Request 0 */ ++#define INT1_vect_num 4 ++#define INT1_vect _VECTOR(4) /* External Interrupt Request 1 */ ++#define INT2_vect_num 5 ++#define INT2_vect _VECTOR(5) /* External Interrupt Request 2 */ ++#define INT3_vect_num 6 ++#define INT3_vect _VECTOR(6) /* External Interrupt Request 3 */ ++#define PCINT0_vect_num 7 ++#define PCINT0_vect _VECTOR(7) /* Pin Change Interrupt 0 */ ++#define PCINT1_vect_num 8 ++#define PCINT1_vect _VECTOR(8) /* Pin Change Interrupt 1 */ ++#define WDT_vect_num 9 ++#define WDT_vect _VECTOR(9) /* Watchdog Timeout Interrupt */ ++#define BGSCD_vect_num 10 ++#define BGSCD_vect _VECTOR(10) /* Bandgap Buffer Short Circuit Detected */ ++#define CHDET_vect_num 11 ++#define CHDET_vect _VECTOR(11) /* Charger Detect */ ++#define TIMER1_IC_vect_num 12 ++#define TIMER1_IC_vect _VECTOR(12) /* Timer 1 Input capture */ ++#define TIMER1_COMPA_vect_num 13 ++#define TIMER1_COMPA_vect _VECTOR(13) /* Timer 1 Compare Match A */ ++#define TIMER1_COMPB_vect_num 14 ++#define TIMER1_COMPB_vect _VECTOR(14) /* Timer 1 Compare Match B */ ++#define TIMER1_OVF_vect_num 15 ++#define TIMER1_OVF_vect _VECTOR(15) /* Timer 1 overflow */ ++#define TIMER0_IC_vect_num 16 ++#define TIMER0_IC_vect _VECTOR(16) /* Timer 0 Input Capture */ ++#define TIMER0_COMPA_vect_num 17 ++#define TIMER0_COMPA_vect _VECTOR(17) /* Timer 0 Comapre Match A */ ++#define TIMER0_COMPB_vect_num 18 ++#define TIMER0_COMPB_vect _VECTOR(18) /* Timer 0 Compare Match B */ ++#define TIMER0_OVF_vect_num 19 ++#define TIMER0_OVF_vect _VECTOR(19) /* Timer 0 Overflow */ ++#define TWIBUSCD_vect_num 20 ++#define TWIBUSCD_vect _VECTOR(20) /* Two-Wire Bus Connect/Disconnect */ ++#define TWI_vect_num 21 ++#define TWI_vect _VECTOR(21) /* Two-Wire Serial Interface */ ++#define SPI_STC_vect_num 22 ++#define SPI_STC_vect _VECTOR(22) /* SPI Serial transfer complete */ ++#define VADC_vect_num 23 ++#define VADC_vect _VECTOR(23) /* Voltage ADC Conversion Complete */ ++#define CCADC_CONV_vect_num 24 ++#define CCADC_CONV_vect _VECTOR(24) /* Coulomb Counter ADC Conversion Complete */ ++#define CCADC_REG_CUR_vect_num 25 ++#define CCADC_REG_CUR_vect _VECTOR(25) /* Coloumb Counter ADC Regular Current */ ++#define CCADC_ACC_vect_num 26 ++#define CCADC_ACC_vect _VECTOR(26) /* Coloumb Counter ADC Accumulator */ ++#define EE_READY_vect_num 27 ++#define EE_READY_vect _VECTOR(27) /* EEPROM Ready */ ++#define SPM_vect_num 28 ++#define SPM_vect _VECTOR(28) /* SPM Ready */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (29 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (128) ++#define RAMSTART (0x100) ++#define RAMSIZE (2048) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (NA) ++#define XRAMEND (RAMEND) ++#define E2END (0x3FF) ++#define E2PAGESIZE (4) ++#define FLASHEND (0x7FFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 2 ++ ++/* Low Fuse Byte */ ++#define FUSE_OSCSEL0 (unsigned char)~_BV(0) /* Oscillator Select */ ++#define FUSE_OSCSEL1 (unsigned char)~_BV(1) /* Oscillator Select */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Select start-up time */ ++#define FUSE_SUT2 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_EESAVE (unsigned char)~_BV(6) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(7) /* Watchdog Timer Always On */ ++#define LFUSE_DEFAULT (FUSE_SPIEN & FUSE_OSCSEL0) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_DWEN (unsigned char)~_BV(3) /* Enable debugWire */ ++#define FUSE_CKDIV (unsigned char)~_BV(4) /* CKDIV Register */ ++#define HFUSE_DEFAULT (FUSE_CKDIV & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x10 ++ ++ ++/* Device Pin Definitions */ ++#define PV2_DDR DDRV ++#define PV2_PORT PORTV ++#define PV2_PIN PINV ++#define PV2_BIT 2 ++ ++#define PV1_DDR DDRV ++#define PV1_PORT PORTV ++#define PV1_PIN PINV ++#define PV1_BIT 1 ++ ++#define NV_DDR DDRNV ++#define NV_PORT PORTNV ++#define NV_PIN PINNV ++#define NV_BIT NV ++ ++#define VFET_DDR DDRVFET ++#define VFET_PORT PORTVFET ++#define VFET_PIN PINVFET ++#define VFET_BIT VFET ++ ++#define CF1P_DDR DDRCF1P ++#define CF1P_PORT PORTCF1P ++#define CF1P_PIN PINCF1P ++#define CF1P_BIT CF1P ++ ++#define CF1N_DDR DDRCF1N ++#define CF1N_PORT PORTCF1N ++#define CF1N_PIN PINCF1N ++#define CF1N_BIT CF1N ++ ++#define CF2P_DDR DDRCF2P ++#define CF2P_PORT PORTCF2P ++#define CF2P_PIN PINCF2P ++#define CF2P_BIT CF2P ++ ++#define CF2N_DDR DDRCF2N ++#define CF2N_PORT PORTCF2N ++#define CF2N_PIN PINCF2N ++#define CF2N_BIT CF2N ++ ++#define VREG_DDR DDRVREG ++#define VREG_PORT PORTVREG ++#define VREG_PIN PINVREG ++#define VREG_BIT VREG ++ ++#define VREF_DDR DDRVREF ++#define VREF_PORT PORTVREF ++#define VREF_PIN PINVREF ++#define VREF_BIT VREF ++ ++#define VREFGND_DDR DDRVREFGND ++#define VREFGND_PORT PORTVREFGND ++#define VREFGND_PIN PINVREFGND ++#define VREFGND_BIT VREFGND ++ ++#define PI_DDR DDRI ++#define PI_PORT PORTI ++#define PI_PIN PINI ++#define PI_BIT ++ ++#define NI_DDR DDRNI ++#define NI_PORT PORTNI ++#define NI_PIN PINNI ++#define NI_BIT NI ++ ++#define PA0_DDR DDRA ++#define PA0_PORT PORTA ++#define PA0_PIN PINA ++#define PA0_BIT 0 ++ ++#define PA1_DDR DDRA ++#define PA1_PORT PORTA ++#define PA1_PIN PINA ++#define PA1_BIT 1 ++ ++#define PA2_DDR DDRA ++#define PA2_PORT PORTA ++#define PA2_PIN PINA ++#define PA2_BIT 2 ++ ++#define PB0_DDR DDRB ++#define PB0_PORT PORTB ++#define PB0_PIN PINB ++#define PB0_BIT 0 ++ ++#define PB1_DDR DDRB ++#define PB1_PORT PORTB ++#define PB1_PIN PINB ++#define PB1_BIT 1 ++ ++#define PB2_DDR DDRB ++#define PB2_PORT PORTB ++#define PB2_PIN PINB ++#define PB2_BIT 2 ++ ++#define PB3_DDR DDRB ++#define PB3_PORT PORTB ++#define PB3_PIN PINB ++#define PB3_BIT 3 ++ ++#define PC0_DDR DDRC ++#define PC0_PORT PORTC ++#define PC0_PIN PINC ++#define PC0_BIT 0 ++ ++#define BATT_DDR DDRBATT ++#define BATT_PORT PORTBATT ++#define BATT_PIN PINBATT ++#define BATT_BIT BATT ++ ++#define OC_DDR DDROC ++#define OC_PORT PORTOC ++#define OC_PIN PINOC ++#define OC_BIT OC ++ ++#endif /* _AVR_ATmega32HVB_H_ */ ++ +diff --git a/include/avr/iom32hvbrevb.h b/include/avr/iom32hvbrevb.h +index 0978c83..ec62b1d 100755 +--- a/include/avr/iom32hvbrevb.h ++++ b/include/avr/iom32hvbrevb.h +@@ -1,940 +1,941 @@ +-/* Copyright (c) 2007, 2011 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. +-*/ +- +-/* $Id: iom32hvbrevb.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ +- +-/* avr/iom32hvbrevb.h - definitions for ATmega32HVB revision B. */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom32hvbrevb.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_IOM32HVBREVB_H_ +-#define _AVR_IOM32HVBREVB_H_ 1 +- +-/* Registers and associated bit numbers */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +- +-#define PORTA _SFR_IO8(0x02) +-#define PORTA0 0 +-#define PORTA1 1 +-#define PORTA2 2 +-#define PORTA3 3 +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC3 3 +-#define PORTC4 4 +-#define PORTC5 5 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +-#define ICF0 3 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 3 +- +-#define OSICSR _SFR_IO8(0x17) +-#define OSIEN 0 +-#define OSIST 1 +-#define OSISEL0 4 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +-#define PCIF1 1 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +-#define INTF2 2 +-#define INTF3 3 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +-#define INT2 2 +-#define INT3 3 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +-#define EEAR9 1 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSRSYNC 0 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define ICS0 3 +-#define ICES0 4 +-#define ICNC0 5 +-#define ICEN0 6 +-#define TCW0 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +- +-#define TCNT0 _SFR_IO16(0x26) +- +-#define TCNT0L _SFR_IO8(0x26) +-#define TCNT0L0 0 +-#define TCNT0L1 1 +-#define TCNT0L2 2 +-#define TCNT0L3 3 +-#define TCNT0L4 4 +-#define TCNT0L5 5 +-#define TCNT0L6 6 +-#define TCNT0L7 7 +- +-#define TCNT0H _SFR_IO8(0x27) +-#define TCNT0H0 0 +-#define TCNT0H1 1 +-#define TCNT0H2 2 +-#define TCNT0H3 3 +-#define TCNT0H4 4 +-#define TCNT0H5 5 +-#define TCNT0H6 6 +-#define TCNT0H7 7 +- +-#define OCR0A _SFR_IO8(0x28) +-#define OCR0A0 0 +-#define OCR0A1 1 +-#define OCR0A2 2 +-#define OCR0A3 3 +-#define OCR0A4 4 +-#define OCR0A5 5 +-#define OCR0A6 6 +-#define OCR0A7 7 +- +-#define OCR0B _SFR_IO8(0x29) +-#define OCR0B0 0 +-#define OCR0B1 1 +-#define OCR0B2 2 +-#define OCR0B3 3 +-#define OCR0B4 4 +-#define OCR0B5 5 +-#define OCR0B6 6 +-#define OCR0B7 7 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BODRF 2 +-#define WDRF 3 +-#define OCDRF 4 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define CKOE 5 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define LBSET 3 +-#define RWWSRE 4 +-#define SIGRD 5 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPCE 7 +- +-#define PRR0 _SFR_MEM8(0x64) +-#define PRVADC 0 +-#define PRTIM0 1 +-#define PRTIM1 2 +-#define PRSPI 3 +-#define PRVRM 5 +-#define PRTWI 6 +- +-#define FOSCCAL _SFR_MEM8(0x66) +-#define FCAL0 0 +-#define FCAL1 1 +-#define FCAL2 2 +-#define FCAL3 3 +-#define FCAL4 4 +-#define FCAL5 5 +-#define FCAL6 6 +-#define FCAL7 7 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +-#define PCIE1 1 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define ISC20 4 +-#define ISC21 5 +-#define ISC30 6 +-#define ISC31 7 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT4 0 +-#define PCINT5 1 +-#define PCINT6 2 +-#define PCINT7 3 +-#define PCINT8 4 +-#define PCINT9 5 +-#define PCINT10 6 +-#define PCINT11 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +-#define ICIE0 3 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 3 +- +-#define VADC _SFR_MEM16(0x78) +- +-#define VADCL _SFR_MEM8(0x78) +-#define VADC0 0 +-#define VADC1 1 +-#define VADC2 2 +-#define VADC3 3 +-#define VADC4 4 +-#define VADC5 5 +-#define VADC6 6 +-#define VADC7 7 +- +-#define VADCH _SFR_MEM8(0x79) +-#define VADC8 0 +-#define VADC9 1 +-#define VADC10 2 +-#define VADC11 3 +- +-#define VADCSR _SFR_MEM8(0x7A) +-#define VADCCIE 0 +-#define VADCCIF 1 +-#define VADSC 2 +-#define VADEN 3 +- +-#define VADMUX _SFR_MEM8(0x7C) +-#define VADMUX0 0 +-#define VADMUX1 1 +-#define VADMUX2 2 +-#define VADMUX3 3 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define PA0DID 0 +-#define PA1DID 1 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define ICS1 3 +-#define ICES1 4 +-#define ICNC1 5 +-#define ICEN1 6 +-#define TCW1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define OCR1A _SFR_MEM8(0x88) +-#define OCR1A0 0 +-#define OCR1A1 1 +-#define OCR1A2 2 +-#define OCR1A3 3 +-#define OCR1A4 4 +-#define OCR1A5 5 +-#define OCR1A6 6 +-#define OCR1A7 7 +- +-#define OCR1B _SFR_MEM8(0x89) +-#define OCR1B0 0 +-#define OCR1B1 1 +-#define OCR1B2 2 +-#define OCR1B3 3 +-#define OCR1B4 4 +-#define OCR1B5 5 +-#define OCR1B6 6 +-#define OCR1B7 7 +- +-#define TWBR _SFR_MEM8(0xB8) +-#define TWBR0 0 +-#define TWBR1 1 +-#define TWBR2 2 +-#define TWBR3 3 +-#define TWBR4 4 +-#define TWBR5 5 +-#define TWBR6 6 +-#define TWBR7 7 +- +-#define TWSR _SFR_MEM8(0xB9) +-#define TWPS0 0 +-#define TWPS1 1 +-#define TWS3 3 +-#define TWS4 4 +-#define TWS5 5 +-#define TWS6 6 +-#define TWS7 7 +- +-#define TWAR _SFR_MEM8(0xBA) +-#define TWGCE 0 +-#define TWA0 1 +-#define TWA1 2 +-#define TWA2 3 +-#define TWA3 4 +-#define TWA4 5 +-#define TWA5 6 +-#define TWA6 7 +- +-#define TWDR _SFR_MEM8(0xBB) +-#define TWD0 0 +-#define TWD1 1 +-#define TWD2 2 +-#define TWD3 3 +-#define TWD4 4 +-#define TWD5 5 +-#define TWD6 6 +-#define TWD7 7 +- +-#define TWCR _SFR_MEM8(0xBC) +-#define TWIE 0 +-#define TWEN 2 +-#define TWWC 3 +-#define TWSTO 4 +-#define TWSTA 5 +-#define TWEA 6 +-#define TWINT 7 +- +-#define TWAMR _SFR_MEM8(0xBD) +-#define TWAM0 0 +-#define TWAM1 1 +-#define TWAM2 2 +-#define TWAM3 3 +-#define TWAM4 4 +-#define TWAM5 5 +-#define TWAM6 6 +- +-#define TWBCSR _SFR_MEM8(0xBE) +-#define TWBCIP 0 +-#define TWBDT0 1 +-#define TWBDT1 2 +-#define TWBCIE 6 +-#define TWBCIF 7 +- +-#define ROCR _SFR_MEM8(0xC8) +-#define ROCWIE 0 +-#define ROCWIF 1 +-#define ROCD 4 +-#define ROCS 7 +- +-#define BGCCR _SFR_MEM8(0xD0) +-#define BGCC0 0 +-#define BGCC1 1 +-#define BGCC2 2 +-#define BGCC3 3 +-#define BGCC4 4 +-#define BGCC5 5 +- +-#define BGCRR _SFR_MEM8(0xD1) +-#define BGCR0 0 +-#define BGCR1 1 +-#define BGCR2 2 +-#define BGCR3 3 +-#define BGCR4 4 +-#define BGCR5 5 +-#define BGCR6 6 +-#define BGCR7 7 +- +-#define BGCSR _SFR_MEM8(0xD2) +-#define BGSCDIE 0 +-#define BGSCDIF 1 +-#define BGSCDE 4 +-#define BGD 5 +- +-#define CHGDCSR _SFR_MEM8(0xD4) +-#define CHGDIE 0 +-#define CHGDIF 1 +-#define CHGDISC0 2 +-#define CHGDISC1 3 +-#define BATTPVL 4 +- +-#define CADAC _SFR_MEM32(0xE0) +- +-#define CADAC0 _SFR_MEM8(0xE0) +-#define CADAC00 0 +-#define CADAC01 1 +-#define CADAC02 2 +-#define CADAC03 3 +-#define CADAC04 4 +-#define CADAC05 5 +-#define CADAC06 6 +-#define CADAC07 7 +- +-#define CADAC1 _SFR_MEM8(0xE1) +-#define CADAC08 0 +-#define CADAC09 1 +-#define CADAC10 2 +-#define CADAC11 3 +-#define CADAC12 4 +-#define CADAC13 5 +-#define CADAC14 6 +-#define CADAC15 7 +- +-#define CADAC2 _SFR_MEM8(0xE2) +-#define CADAC16 0 +-#define CADAC17 1 +-#define CADAC18 2 +-#define CADAC19 3 +-#define CADAC20 4 +-#define CADAC21 5 +-#define CADAC22 6 +-#define CADAC23 7 +- +-#define CADAC3 _SFR_MEM8(0xE3) +-#define CADAC24 0 +-#define CADAC25 1 +-#define CADAC26 2 +-#define CADAC27 3 +-#define CADAC28 4 +-#define CADAC29 5 +-#define CADAC30 6 +-#define CADAC31 7 +- +-#define CADIC _SFR_MEM16(0xE4) +- +-#define CADICL _SFR_MEM8(0xE4) +-#define CADICL0 0 +-#define CADICL1 1 +-#define CADICL2 2 +-#define CADICL3 3 +-#define CADICL4 4 +-#define CADICL5 5 +-#define CADICL6 6 +-#define CADICL7 7 +- +-#define CADICH _SFR_MEM8(0xE5) +-#define CADICH0 0 +-#define CADICH1 1 +-#define CADICH2 2 +-#define CADICH3 3 +-#define CADICH4 4 +-#define CADICH5 5 +-#define CADICH6 6 +-#define CADICH7 7 +- +-#define CADCSRA _SFR_MEM8(0xE6) +-#define CADSE 0 +-#define CADSI0 1 +-#define CADSI1 2 +-#define CADAS0 3 +-#define CADAS1 4 +-#define CADUB 5 +-#define CADPOL 6 +-#define CADEN 7 +- +-#define CADCSRB _SFR_MEM8(0xE7) +-#define CADICIF 0 +-#define CADRCIF 1 +-#define CADACIF 2 +-#define CADICIE 4 +-#define CADRCIE 5 +-#define CADACIE 6 +- +-#define CADCSRC _SFR_MEM8(0xE8) +-#define CADVSE 0 +- +-#define CADRCC _SFR_MEM8(0xE9) +-#define CADRCC0 0 +-#define CADRCC1 1 +-#define CADRCC2 2 +-#define CADRCC3 3 +-#define CADRCC4 4 +-#define CADRCC5 5 +-#define CADRCC6 6 +-#define CADRCC7 7 +- +-#define CADRDC _SFR_MEM8(0xEA) +-#define CADRDC0 0 +-#define CADRDC1 1 +-#define CADRDC2 2 +-#define CADRDC3 3 +-#define CADRDC4 4 +-#define CADRDC5 5 +-#define CADRDC6 6 +-#define CADRDC7 7 +- +-#define FCSR _SFR_MEM8(0xF0) +-#define CFE 0 +-#define DFE 1 +-#define CPS 2 +-#define DUVRD 3 +- +-#define CBCR _SFR_MEM8(0xF1) +-#define CBE1 0 +-#define CBE2 1 +-#define CBE3 2 +-#define CBE4 3 +- +-#define BPIMSK _SFR_MEM8(0xF2) +-#define CHCIE 0 +-#define DHCIE 1 +-#define COCIE 2 +-#define DOCIE 3 +-#define SCIE 4 +- +-#define BPIFR _SFR_MEM8(0xF3) +-#define CHCIF 0 +-#define DHCIF 1 +-#define COCIF 2 +-#define DOCIF 3 +-#define SCIF 4 +- +-#define BPSCD _SFR_MEM8(0xF5) +-#define SCDL0 0 +-#define SCDL1 1 +-#define SCDL2 2 +-#define SCDL3 3 +-#define SCDL4 4 +-#define SCDL5 5 +-#define SCDL6 6 +-#define SCDL7 7 +- +-#define BPDOCD _SFR_MEM8(0xF6) +-#define DOCDL0 0 +-#define DOCDL1 1 +-#define DOCDL2 2 +-#define DOCDL3 3 +-#define DOCDL4 4 +-#define DOCDL5 5 +-#define DOCDL6 6 +-#define DOCDL7 7 +- +-#define BPCOCD _SFR_MEM8(0xF7) +-#define COCDL0 0 +-#define COCDL1 1 +-#define COCDL2 2 +-#define COCDL3 3 +-#define COCDL4 4 +-#define COCDL5 5 +-#define COCDL6 6 +-#define COCDL7 7 +- +-#define BPDHCD _SFR_MEM8(0xF8) +-#define DHCDL0 0 +-#define DHCDL1 1 +-#define DHCDL2 2 +-#define DHCDL3 3 +-#define DHCDL4 4 +-#define DHCDL5 5 +-#define DHCDL6 6 +-#define DHCDL7 7 +- +-#define BPCHCD _SFR_MEM8(0xF9) +-#define CHCDL0 0 +-#define CHCDL1 1 +-#define CHCDL2 2 +-#define CHCDL3 3 +-#define CHCDL4 4 +-#define CHCDL5 5 +-#define CHCDL6 6 +-#define CHCDL7 7 +- +-#define BPSCTR _SFR_MEM8(0xFA) +-#define SCPT0 0 +-#define SCPT1 1 +-#define SCPT2 2 +-#define SCPT3 3 +-#define SCPT4 4 +-#define SCPT5 5 +-#define SCPT6 6 +- +-#define BPOCTR _SFR_MEM8(0xFB) +-#define OCPT0 0 +-#define OCPT1 1 +-#define OCPT2 2 +-#define OCPT3 3 +-#define OCPT4 4 +-#define OCPT5 5 +- +-#define BPHCTR _SFR_MEM8(0xFC) +-#define HCPT0 0 +-#define HCPT1 1 +-#define HCPT2 2 +-#define HCPT3 3 +-#define HCPT4 4 +-#define HCPT5 5 +- +-#define BPCR _SFR_MEM8(0xFD) +-#define CHCD 0 +-#define DHCD 1 +-#define COCD 2 +-#define DOCD 3 +-#define SCD 4 +-#define EPID 5 +- +-#define BPPLR _SFR_MEM8(0xFE) +-#define BPPL 0 +-#define BPPLE 1 +- +- +- +-/* Interrupt Vectors */ +-/* Interrupt Vector 0 is the reset vector. */ +- +-#define BPINT_vect_num 1 +-#define BPINT_vect _VECTOR(1) /* Battery Protection Interrupt */ +- +-#define VREGMON_vect_num 2 +-#define VREGMON_vect _VECTOR(2) /* Voltage regulator monitor interrupt */ +- +-#define INT0_vect_num 3 +-#define INT0_vect _VECTOR(3) /* External Interrupt Request 0 */ +- +-#define INT1_vect_num 4 +-#define INT1_vect _VECTOR(4) /* External Interrupt Request 1 */ +- +-#define INT2_vect_num 5 +-#define INT2_vect _VECTOR(5) /* External Interrupt Request 2 */ +- +-#define INT3_vect_num 6 +-#define INT3_vect _VECTOR(6) /* External Interrupt Request 3 */ +- +-#define PCINT0_vect_num 7 +-#define PCINT0_vect _VECTOR(7) /* Pin Change Interrupt 0 */ +- +-#define PCINT1_vect_num 8 +-#define PCINT1_vect _VECTOR(8) /* Pin Change Interrupt 1 */ +- +-#define WDT_vect_num 9 +-#define WDT_vect _VECTOR(9) /* Watchdog Timeout Interrupt */ +- +-#define BGSCD_vect_num 10 +-#define BGSCD_vect _VECTOR(10) /* Bandgap Buffer Short Circuit Detected */ +- +-#define CHDET_vect_num 11 +-#define CHDET_vect _VECTOR(11) /* Charger Detect */ +- +-#define TIMER1_IC_vect_num 12 +-#define TIMER1_IC_vect _VECTOR(12) /* Timer 1 Input capture */ +- +-#define TIMER1_COMPA_vect_num 13 +-#define TIMER1_COMPA_vect _VECTOR(13) /* Timer 1 Compare Match A */ +- +-#define TIMER1_COMPB_vect_num 14 +-#define TIMER1_COMPB_vect _VECTOR(14) /* Timer 1 Compare Match B */ +- +-#define TIMER1_OVF_vect_num 15 +-#define TIMER1_OVF_vect _VECTOR(15) /* Timer 1 overflow */ +- +-#define TIMER0_IC_vect_num 16 +-#define TIMER0_IC_vect _VECTOR(16) /* Timer 0 Input Capture */ +- +-#define TIMER0_COMPA_vect_num 17 +-#define TIMER0_COMPA_vect _VECTOR(17) /* Timer 0 Comapre Match A */ +- +-#define TIMER0_COMPB_vect_num 18 +-#define TIMER0_COMPB_vect _VECTOR(18) /* Timer 0 Compare Match B */ +- +-#define TIMER0_OVF_vect_num 19 +-#define TIMER0_OVF_vect _VECTOR(19) /* Timer 0 Overflow */ +- +-#define TWIBUSCD_vect_num 20 +-#define TWIBUSCD_vect _VECTOR(20) /* Two-Wire Bus Connect/Disconnect */ +- +-#define TWI_vect_num 21 +-#define TWI_vect _VECTOR(21) /* Two-Wire Serial Interface */ +- +-#define SPI_STC_vect_num 22 +-#define SPI_STC_vect _VECTOR(22) /* SPI Serial transfer complete */ +- +-#define VADC_vect_num 23 +-#define VADC_vect _VECTOR(23) /* Voltage ADC Conversion Complete */ +- +-#define CCADC_CONV_vect_num 24 +-#define CCADC_CONV_vect _VECTOR(24) /* Coulomb Counter ADC Conversion Complete */ +- +-#define CCADC_REG_CUR_vect_num 25 +-#define CCADC_REG_CUR_vect _VECTOR(25) /* Coloumb Counter ADC Regular Current */ +- +-#define CCADC_ACC_vect_num 26 +-#define CCADC_ACC_vect _VECTOR(26) /* Coloumb Counter ADC Accumulator */ +- +-#define EE_READY_vect_num 27 +-#define EE_READY_vect _VECTOR(27) /* EEPROM Ready */ +- +-#define SPM_vect_num 28 +-#define SPM_vect _VECTOR(28) /* SPM Ready */ +- +-#define _VECTORS_SIZE (29 * 4) +- +- +-/* Constants */ +-#define SPM_PAGESIZE 64 +-#define RAMEND 0x8FF /* Last On-Chip SRAM Location */ +-#define XRAMSIZE 0 +-#define XRAMEND RAMEND +-#define E2END 0x3FF +-#define FLASHEND 0x7FFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 2 +- +-/* Low Fuse Byte */ +-#define FUSE_WDTON (unsigned char)~_BV(7) /* Watchdog Timer Always On */ +-#define FUSE_EESAVE (unsigned char)~_BV(6) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_SUT2 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(3) /* Select start-up time */ +-#define FUSE_SUT0 (unsigned char)~_BV(2) /* Select start-up time */ +-#define FUSE_OSCSEL1 (unsigned char)~_BV(1) /* Oscillator Select */ +-#define FUSE_OSCSEL0 (unsigned char)~_BV(0) /* Oscillator Select */ +-#define LFUSE_DEFAULT (FUSE_OSCSEL0 & FUSE_SPIEN) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_DWEN (unsigned char)~_BV(3) /* Enable debugWire */ +-#define FUSE_DUVRDINIT (unsigned char)~_BV(4) /* Reset Value of DUVRDRegister */ +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_DUVRDINIT) +- +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-#endif /* _AVR_IOM32HVBREVB_H_ */ ++/* Copyright (c) 2007, 2011 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++/* $Id: iom32hvbrevb.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ ++ ++/* avr/iom32hvbrevb.h - definitions for ATmega32HVB revision B. */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom32hvbrevb.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_IOM32HVBREVB_H_ ++#define _AVR_IOM32HVBREVB_H_ 1 ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA0 0 ++#define PORTA1 1 ++#define PORTA2 2 ++#define PORTA3 3 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC3 3 ++#define PORTC4 4 ++#define PORTC5 5 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++#define ICF0 3 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 3 ++ ++#define OSICSR _SFR_IO8(0x17) ++#define OSIEN 0 ++#define OSIST 1 ++#define OSISEL0 4 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++#define INT3 3 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++#define EEAR9 1 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define ICS0 3 ++#define ICES0 4 ++#define ICNC0 5 ++#define ICEN0 6 ++#define TCW0 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++ ++#define TCNT0 _SFR_IO16(0x26) ++ ++#define TCNT0L _SFR_IO8(0x26) ++#define TCNT0L0 0 ++#define TCNT0L1 1 ++#define TCNT0L2 2 ++#define TCNT0L3 3 ++#define TCNT0L4 4 ++#define TCNT0L5 5 ++#define TCNT0L6 6 ++#define TCNT0L7 7 ++ ++#define TCNT0H _SFR_IO8(0x27) ++#define TCNT0H0 0 ++#define TCNT0H1 1 ++#define TCNT0H2 2 ++#define TCNT0H3 3 ++#define TCNT0H4 4 ++#define TCNT0H5 5 ++#define TCNT0H6 6 ++#define TCNT0H7 7 ++ ++#define OCR0A _SFR_IO8(0x28) ++#define OCR0A0 0 ++#define OCR0A1 1 ++#define OCR0A2 2 ++#define OCR0A3 3 ++#define OCR0A4 4 ++#define OCR0A5 5 ++#define OCR0A6 6 ++#define OCR0A7 7 ++ ++#define OCR0B _SFR_IO8(0x29) ++#define OCR0B0 0 ++#define OCR0B1 1 ++#define OCR0B2 2 ++#define OCR0B3 3 ++#define OCR0B4 4 ++#define OCR0B5 5 ++#define OCR0B6 6 ++#define OCR0B7 7 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BODRF 2 ++#define WDRF 3 ++#define OCDRF 4 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define CKOE 5 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define LBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPCE 7 ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRVADC 0 ++#define PRTIM0 1 ++#define PRTIM1 2 ++#define PRSPI 3 ++#define PRVRM 5 ++#define PRTWI 6 ++ ++#define FOSCCAL _SFR_MEM8(0x66) ++#define FCAL0 0 ++#define FCAL1 1 ++#define FCAL2 2 ++#define FCAL3 3 ++#define FCAL4 4 ++#define FCAL5 5 ++#define FCAL6 6 ++#define FCAL7 7 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT4 0 ++#define PCINT5 1 ++#define PCINT6 2 ++#define PCINT7 3 ++#define PCINT8 4 ++#define PCINT9 5 ++#define PCINT10 6 ++#define PCINT11 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++#define ICIE0 3 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 3 ++ ++#define VADC _SFR_MEM16(0x78) ++ ++#define VADCL _SFR_MEM8(0x78) ++#define VADC0 0 ++#define VADC1 1 ++#define VADC2 2 ++#define VADC3 3 ++#define VADC4 4 ++#define VADC5 5 ++#define VADC6 6 ++#define VADC7 7 ++ ++#define VADCH _SFR_MEM8(0x79) ++#define VADC8 0 ++#define VADC9 1 ++#define VADC10 2 ++#define VADC11 3 ++ ++#define VADCSR _SFR_MEM8(0x7A) ++#define VADCCIE 0 ++#define VADCCIF 1 ++#define VADSC 2 ++#define VADEN 3 ++ ++#define VADMUX _SFR_MEM8(0x7C) ++#define VADMUX0 0 ++#define VADMUX1 1 ++#define VADMUX2 2 ++#define VADMUX3 3 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define PA0DID 0 ++#define PA1DID 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define ICS1 3 ++#define ICES1 4 ++#define ICNC1 5 ++#define ICEN1 6 ++#define TCW1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define OCR1A _SFR_MEM8(0x88) ++#define OCR1A0 0 ++#define OCR1A1 1 ++#define OCR1A2 2 ++#define OCR1A3 3 ++#define OCR1A4 4 ++#define OCR1A5 5 ++#define OCR1A6 6 ++#define OCR1A7 7 ++ ++#define OCR1B _SFR_MEM8(0x89) ++#define OCR1B0 0 ++#define OCR1B1 1 ++#define OCR1B2 2 ++#define OCR1B3 3 ++#define OCR1B4 4 ++#define OCR1B5 5 ++#define OCR1B6 6 ++#define OCR1B7 7 ++ ++#define TWBR _SFR_MEM8(0xB8) ++#define TWBR0 0 ++#define TWBR1 1 ++#define TWBR2 2 ++#define TWBR3 3 ++#define TWBR4 4 ++#define TWBR5 5 ++#define TWBR6 6 ++#define TWBR7 7 ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++#define TWD0 0 ++#define TWD1 1 ++#define TWD2 2 ++#define TWD3 3 ++#define TWD4 4 ++#define TWD5 5 ++#define TWD6 6 ++#define TWD7 7 ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 0 ++#define TWAM1 1 ++#define TWAM2 2 ++#define TWAM3 3 ++#define TWAM4 4 ++#define TWAM5 5 ++#define TWAM6 6 ++ ++#define TWBCSR _SFR_MEM8(0xBE) ++#define TWBCIP 0 ++#define TWBDT0 1 ++#define TWBDT1 2 ++#define TWBCIE 6 ++#define TWBCIF 7 ++ ++#define ROCR _SFR_MEM8(0xC8) ++#define ROCWIE 0 ++#define ROCWIF 1 ++#define ROCD 4 ++#define ROCS 7 ++ ++#define BGCCR _SFR_MEM8(0xD0) ++#define BGCC0 0 ++#define BGCC1 1 ++#define BGCC2 2 ++#define BGCC3 3 ++#define BGCC4 4 ++#define BGCC5 5 ++ ++#define BGCRR _SFR_MEM8(0xD1) ++#define BGCR0 0 ++#define BGCR1 1 ++#define BGCR2 2 ++#define BGCR3 3 ++#define BGCR4 4 ++#define BGCR5 5 ++#define BGCR6 6 ++#define BGCR7 7 ++ ++#define BGCSR _SFR_MEM8(0xD2) ++#define BGSCDIE 0 ++#define BGSCDIF 1 ++#define BGSCDE 4 ++#define BGD 5 ++ ++#define CHGDCSR _SFR_MEM8(0xD4) ++#define CHGDIE 0 ++#define CHGDIF 1 ++#define CHGDISC0 2 ++#define CHGDISC1 3 ++#define BATTPVL 4 ++ ++#define CADAC _SFR_MEM32(0xE0) ++ ++#define CADAC0 _SFR_MEM8(0xE0) ++#define CADAC00 0 ++#define CADAC01 1 ++#define CADAC02 2 ++#define CADAC03 3 ++#define CADAC04 4 ++#define CADAC05 5 ++#define CADAC06 6 ++#define CADAC07 7 ++ ++#define CADAC1 _SFR_MEM8(0xE1) ++#define CADAC08 0 ++#define CADAC09 1 ++#define CADAC10 2 ++#define CADAC11 3 ++#define CADAC12 4 ++#define CADAC13 5 ++#define CADAC14 6 ++#define CADAC15 7 ++ ++#define CADAC2 _SFR_MEM8(0xE2) ++#define CADAC16 0 ++#define CADAC17 1 ++#define CADAC18 2 ++#define CADAC19 3 ++#define CADAC20 4 ++#define CADAC21 5 ++#define CADAC22 6 ++#define CADAC23 7 ++ ++#define CADAC3 _SFR_MEM8(0xE3) ++#define CADAC24 0 ++#define CADAC25 1 ++#define CADAC26 2 ++#define CADAC27 3 ++#define CADAC28 4 ++#define CADAC29 5 ++#define CADAC30 6 ++#define CADAC31 7 ++ ++#define CADIC _SFR_MEM16(0xE4) ++ ++#define CADICL _SFR_MEM8(0xE4) ++#define CADICL0 0 ++#define CADICL1 1 ++#define CADICL2 2 ++#define CADICL3 3 ++#define CADICL4 4 ++#define CADICL5 5 ++#define CADICL6 6 ++#define CADICL7 7 ++ ++#define CADICH _SFR_MEM8(0xE5) ++#define CADICH0 0 ++#define CADICH1 1 ++#define CADICH2 2 ++#define CADICH3 3 ++#define CADICH4 4 ++#define CADICH5 5 ++#define CADICH6 6 ++#define CADICH7 7 ++ ++#define CADCSRA _SFR_MEM8(0xE6) ++#define CADSE 0 ++#define CADSI0 1 ++#define CADSI1 2 ++#define CADAS0 3 ++#define CADAS1 4 ++#define CADUB 5 ++#define CADPOL 6 ++#define CADEN 7 ++ ++#define CADCSRB _SFR_MEM8(0xE7) ++#define CADICIF 0 ++#define CADRCIF 1 ++#define CADACIF 2 ++#define CADICIE 4 ++#define CADRCIE 5 ++#define CADACIE 6 ++ ++#define CADCSRC _SFR_MEM8(0xE8) ++#define CADVSE 0 ++ ++#define CADRCC _SFR_MEM8(0xE9) ++#define CADRCC0 0 ++#define CADRCC1 1 ++#define CADRCC2 2 ++#define CADRCC3 3 ++#define CADRCC4 4 ++#define CADRCC5 5 ++#define CADRCC6 6 ++#define CADRCC7 7 ++ ++#define CADRDC _SFR_MEM8(0xEA) ++#define CADRDC0 0 ++#define CADRDC1 1 ++#define CADRDC2 2 ++#define CADRDC3 3 ++#define CADRDC4 4 ++#define CADRDC5 5 ++#define CADRDC6 6 ++#define CADRDC7 7 ++ ++#define FCSR _SFR_MEM8(0xF0) ++#define CFE 0 ++#define DFE 1 ++#define CPS 2 ++#define DUVRD 3 ++ ++#define CBCR _SFR_MEM8(0xF1) ++#define CBE1 0 ++#define CBE2 1 ++#define CBE3 2 ++#define CBE4 3 ++ ++#define BPIMSK _SFR_MEM8(0xF2) ++#define CHCIE 0 ++#define DHCIE 1 ++#define COCIE 2 ++#define DOCIE 3 ++#define SCIE 4 ++ ++#define BPIFR _SFR_MEM8(0xF3) ++#define CHCIF 0 ++#define DHCIF 1 ++#define COCIF 2 ++#define DOCIF 3 ++#define SCIF 4 ++ ++#define BPSCD _SFR_MEM8(0xF5) ++#define SCDL0 0 ++#define SCDL1 1 ++#define SCDL2 2 ++#define SCDL3 3 ++#define SCDL4 4 ++#define SCDL5 5 ++#define SCDL6 6 ++#define SCDL7 7 ++ ++#define BPDOCD _SFR_MEM8(0xF6) ++#define DOCDL0 0 ++#define DOCDL1 1 ++#define DOCDL2 2 ++#define DOCDL3 3 ++#define DOCDL4 4 ++#define DOCDL5 5 ++#define DOCDL6 6 ++#define DOCDL7 7 ++ ++#define BPCOCD _SFR_MEM8(0xF7) ++#define COCDL0 0 ++#define COCDL1 1 ++#define COCDL2 2 ++#define COCDL3 3 ++#define COCDL4 4 ++#define COCDL5 5 ++#define COCDL6 6 ++#define COCDL7 7 ++ ++#define BPDHCD _SFR_MEM8(0xF8) ++#define DHCDL0 0 ++#define DHCDL1 1 ++#define DHCDL2 2 ++#define DHCDL3 3 ++#define DHCDL4 4 ++#define DHCDL5 5 ++#define DHCDL6 6 ++#define DHCDL7 7 ++ ++#define BPCHCD _SFR_MEM8(0xF9) ++#define CHCDL0 0 ++#define CHCDL1 1 ++#define CHCDL2 2 ++#define CHCDL3 3 ++#define CHCDL4 4 ++#define CHCDL5 5 ++#define CHCDL6 6 ++#define CHCDL7 7 ++ ++#define BPSCTR _SFR_MEM8(0xFA) ++#define SCPT0 0 ++#define SCPT1 1 ++#define SCPT2 2 ++#define SCPT3 3 ++#define SCPT4 4 ++#define SCPT5 5 ++#define SCPT6 6 ++ ++#define BPOCTR _SFR_MEM8(0xFB) ++#define OCPT0 0 ++#define OCPT1 1 ++#define OCPT2 2 ++#define OCPT3 3 ++#define OCPT4 4 ++#define OCPT5 5 ++ ++#define BPHCTR _SFR_MEM8(0xFC) ++#define HCPT0 0 ++#define HCPT1 1 ++#define HCPT2 2 ++#define HCPT3 3 ++#define HCPT4 4 ++#define HCPT5 5 ++ ++#define BPCR _SFR_MEM8(0xFD) ++#define CHCD 0 ++#define DHCD 1 ++#define COCD 2 ++#define DOCD 3 ++#define SCD 4 ++#define EPID 5 ++ ++#define BPPLR _SFR_MEM8(0xFE) ++#define BPPL 0 ++#define BPPLE 1 ++ ++ ++ ++/* Interrupt Vectors */ ++/* Interrupt Vector 0 is the reset vector. */ ++ ++#define BPINT_vect_num 1 ++#define BPINT_vect _VECTOR(1) /* Battery Protection Interrupt */ ++ ++#define VREGMON_vect_num 2 ++#define VREGMON_vect _VECTOR(2) /* Voltage regulator monitor interrupt */ ++ ++#define INT0_vect_num 3 ++#define INT0_vect _VECTOR(3) /* External Interrupt Request 0 */ ++ ++#define INT1_vect_num 4 ++#define INT1_vect _VECTOR(4) /* External Interrupt Request 1 */ ++ ++#define INT2_vect_num 5 ++#define INT2_vect _VECTOR(5) /* External Interrupt Request 2 */ ++ ++#define INT3_vect_num 6 ++#define INT3_vect _VECTOR(6) /* External Interrupt Request 3 */ ++ ++#define PCINT0_vect_num 7 ++#define PCINT0_vect _VECTOR(7) /* Pin Change Interrupt 0 */ ++ ++#define PCINT1_vect_num 8 ++#define PCINT1_vect _VECTOR(8) /* Pin Change Interrupt 1 */ ++ ++#define WDT_vect_num 9 ++#define WDT_vect _VECTOR(9) /* Watchdog Timeout Interrupt */ ++ ++#define BGSCD_vect_num 10 ++#define BGSCD_vect _VECTOR(10) /* Bandgap Buffer Short Circuit Detected */ ++ ++#define CHDET_vect_num 11 ++#define CHDET_vect _VECTOR(11) /* Charger Detect */ ++ ++#define TIMER1_IC_vect_num 12 ++#define TIMER1_IC_vect _VECTOR(12) /* Timer 1 Input capture */ ++ ++#define TIMER1_COMPA_vect_num 13 ++#define TIMER1_COMPA_vect _VECTOR(13) /* Timer 1 Compare Match A */ ++ ++#define TIMER1_COMPB_vect_num 14 ++#define TIMER1_COMPB_vect _VECTOR(14) /* Timer 1 Compare Match B */ ++ ++#define TIMER1_OVF_vect_num 15 ++#define TIMER1_OVF_vect _VECTOR(15) /* Timer 1 overflow */ ++ ++#define TIMER0_IC_vect_num 16 ++#define TIMER0_IC_vect _VECTOR(16) /* Timer 0 Input Capture */ ++ ++#define TIMER0_COMPA_vect_num 17 ++#define TIMER0_COMPA_vect _VECTOR(17) /* Timer 0 Comapre Match A */ ++ ++#define TIMER0_COMPB_vect_num 18 ++#define TIMER0_COMPB_vect _VECTOR(18) /* Timer 0 Compare Match B */ ++ ++#define TIMER0_OVF_vect_num 19 ++#define TIMER0_OVF_vect _VECTOR(19) /* Timer 0 Overflow */ ++ ++#define TWIBUSCD_vect_num 20 ++#define TWIBUSCD_vect _VECTOR(20) /* Two-Wire Bus Connect/Disconnect */ ++ ++#define TWI_vect_num 21 ++#define TWI_vect _VECTOR(21) /* Two-Wire Serial Interface */ ++ ++#define SPI_STC_vect_num 22 ++#define SPI_STC_vect _VECTOR(22) /* SPI Serial transfer complete */ ++ ++#define VADC_vect_num 23 ++#define VADC_vect _VECTOR(23) /* Voltage ADC Conversion Complete */ ++ ++#define CCADC_CONV_vect_num 24 ++#define CCADC_CONV_vect _VECTOR(24) /* Coulomb Counter ADC Conversion Complete */ ++ ++#define CCADC_REG_CUR_vect_num 25 ++#define CCADC_REG_CUR_vect _VECTOR(25) /* Coloumb Counter ADC Regular Current */ ++ ++#define CCADC_ACC_vect_num 26 ++#define CCADC_ACC_vect _VECTOR(26) /* Coloumb Counter ADC Accumulator */ ++ ++#define EE_READY_vect_num 27 ++#define EE_READY_vect _VECTOR(27) /* EEPROM Ready */ ++ ++#define SPM_vect_num 28 ++#define SPM_vect _VECTOR(28) /* SPM Ready */ ++ ++#define _VECTORS_SIZE (29 * 4) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE 64 ++#define RAMSTART 0x100 ++#define RAMEND 0x8FF /* Last On-Chip SRAM Location */ ++#define XRAMSIZE 0 ++#define XRAMEND RAMEND ++#define E2END 0x3FF ++#define FLASHEND 0x7FFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 2 ++ ++/* Low Fuse Byte */ ++#define FUSE_WDTON (unsigned char)~_BV(7) /* Watchdog Timer Always On */ ++#define FUSE_EESAVE (unsigned char)~_BV(6) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_SUT2 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Select start-up time */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Select start-up time */ ++#define FUSE_OSCSEL1 (unsigned char)~_BV(1) /* Oscillator Select */ ++#define FUSE_OSCSEL0 (unsigned char)~_BV(0) /* Oscillator Select */ ++#define LFUSE_DEFAULT (FUSE_OSCSEL0 & FUSE_SPIEN) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_DWEN (unsigned char)~_BV(3) /* Enable debugWire */ ++#define FUSE_DUVRDINIT (unsigned char)~_BV(4) /* Reset Value of DUVRDRegister */ ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_DUVRDINIT) ++ ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++#endif /* _AVR_IOM32HVBREVB_H_ */ +diff --git a/include/avr/iom32m1.h b/include/avr/iom32m1.h +index 49469fc..7b5f40a 100644 +--- a/include/avr/iom32m1.h ++++ b/include/avr/iom32m1.h +@@ -1,1611 +1,1611 @@ +-/* Copyright (c) 2008-2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom32m1.h 2235 2011-03-17 04:13:14Z arcanum $ */ +- +-/* avr/iom32m1.h - definitions for ATmega32M1 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom32m1.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATmega32M1_H_ +-#define _AVR_ATmega32M1_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +-#define PINC7 7 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC3 3 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +-#define DDC7 7 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC3 3 +-#define PORTC4 4 +-#define PORTC5 5 +-#define PORTC6 6 +-#define PORTC7 7 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define PINE _SFR_IO8(0x0C) +-#define PINE0 0 +-#define PINE1 1 +-#define PINE2 2 +- +-#define DDRE _SFR_IO8(0x0D) +-#define DDE0 0 +-#define DDE1 1 +-#define DDE2 2 +- +-#define PORTE _SFR_IO8(0x0E) +-#define PORTE0 0 +-#define PORTE1 1 +-#define PORTE2 2 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define GPIOR1 _SFR_IO8(0x19) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x1A) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +-#define PCIF1 1 +-#define PCIF2 2 +-#define PCIF3 3 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +-#define INTF2 2 +-#define INTF3 3 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +-#define INT2 2 +-#define INT3 3 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEWE 1 +-#define EEMWE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +-#define EEAR9 1 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSR10 0 +-#define PSRSYNC 0 +-#define ICPSEL1 6 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define OCR0A _SFR_IO8(0x27) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define OCR0B _SFR_IO8(0x28) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define PLLCSR _SFR_IO8(0x29) +-#define PLOCK 0 +-#define PLLE 1 +-#define PLLF 2 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define ACSR _SFR_IO8(0x30) +-#define AC0O 0 +-#define AC1O 1 +-#define AC2O 2 +-#define AC3O 3 +-#define AC0IF 4 +-#define AC1IF 5 +-#define AC2IF 6 +-#define AC3IF 7 +- +-#define DWDR _SFR_IO8(0x31) +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define SPIPS 7 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define SIGRD 5 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRLIN 1 +-#define PRSPI 2 +-#define PRTIM0 3 +-#define PRTIM1 4 +-#define PRPSC 5 +-#define PRCAN 6 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +-#define PCIE1 1 +-#define PCIE2 2 +-#define PCIE3 3 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define ISC20 4 +-#define ISC21 5 +-#define ISC30 6 +-#define ISC31 7 +- +-#define PCMSK0 _SFR_MEM8(0x6A) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6B) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-#define PCMSK2 _SFR_MEM8(0x6C) +-#define PCINT16 0 +-#define PCINT17 1 +-#define PCINT18 2 +-#define PCINT19 3 +-#define PCINT20 4 +-#define PCINT21 5 +-#define PCINT22 6 +-#define PCINT23 7 +- +-#define PCMSK3 _SFR_MEM8(0x6D) +-#define PCINT24 0 +-#define PCINT25 1 +-#define PCINT26 2 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define AMP0CSR _SFR_MEM8(0x75) +-#define AMP0TS0 0 +-#define AMP0TS1 1 +-#define AMP0TS2 2 +-#define AMPCMP0 3 +-#define AMP0G0 4 +-#define AMP0G1 5 +-#define AMP0IS 6 +-#define AMP0EN 7 +- +-#define AMP1CSR _SFR_MEM8(0x76) +-#define AMP1TS0 0 +-#define AMP1TS1 1 +-#define AMP1TS2 2 +-#define AMPCMP1 3 +-#define AMP1G0 4 +-#define AMP1G1 5 +-#define AMP1IS 6 +-#define AMP1EN 7 +- +-#define AMP2CSR _SFR_MEM8(0x77) +-#define AMP2TS0 0 +-#define AMP2TS1 1 +-#define AMP2TS2 2 +-#define AMPCMP2 3 +-#define AMP2G0 4 +-#define AMP2G1 5 +-#define AMP2IS 6 +-#define AMP2EN 7 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +- +-#define ADCL _SFR_MEM8(0x78) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_MEM8(0x79) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ADTS3 3 +-#define AREFEN 5 +-#define ISRCEN 6 +-#define ADHSM 7 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define ADC8D 0 +-#define ADC9D 1 +-#define ADC10D 2 +-#define AMP0ND 3 +-#define AMP0PD 4 +-#define ACMP0D 5 +-#define AMP2PD 6 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define DACON _SFR_MEM8(0x90) +-#define DAEN 0 +-#define DAOE 1 +-#define DALA 2 +-#define DATS0 4 +-#define DATS1 5 +-#define DATS2 6 +-#define DAATE 7 +- +-#define DAC _SFR_MEM16(0x91) +- +-#define DACL _SFR_MEM8(0x91) +-#define DACL0 0 +-#define DACL1 1 +-#define DACL2 2 +-#define DACL3 3 +-#define DACL4 4 +-#define DACL5 5 +-#define DACL6 6 +-#define DACL7 7 +- +-#define DACH _SFR_MEM8(0x92) +-#define DACH0 0 +-#define DACH1 1 +-#define DACH2 2 +-#define DACH3 3 +-#define DACH4 4 +-#define DACH5 5 +-#define DACH6 6 +-#define DACH7 7 +- +-#define AC0CON _SFR_MEM8(0x94) +-#define AC0M0 0 +-#define AC0M1 1 +-#define AC0M2 2 +-#define ACCKSEL 3 +-#define AC0IS0 4 +-#define AC0IS1 5 +-#define AC0IE 6 +-#define AC0EN 7 +- +-#define AC1CON _SFR_MEM8(0x95) +-#define AC1M0 0 +-#define AC1M1 1 +-#define AC1M2 2 +-#define AC1ICE 3 +-#define AC1IS0 4 +-#define AC1IS1 5 +-#define AC1IE 6 +-#define AC1EN 7 +- +-#define AC2CON _SFR_MEM8(0x96) +-#define AC2M0 0 +-#define AC2M1 1 +-#define AC2M2 2 +-#define AC2IS0 4 +-#define AC2IS1 5 +-#define AC2IE 6 +-#define AC2EN 7 +- +-#define AC3CON _SFR_MEM8(0x97) +-#define AC3M0 0 +-#define AC3M1 1 +-#define AC3M2 2 +-#define AC3IS0 4 +-#define AC3IS1 5 +-#define AC3IE 6 +-#define AC3EN 7 +- +-#define POCR0SA _SFR_MEM16(0xA0) +- +-#define POCR0SAL _SFR_MEM8(0xA0) +-#define POCR0SA_0 0 +-#define POCR0SA_1 1 +-#define POCR0SA_2 2 +-#define POCR0SA_3 3 +-#define POCR0SA_4 4 +-#define POCR0SA_5 5 +-#define POCR0SA_6 6 +-#define POCR0SA_7 7 +- +-#define POCR0SAH _SFR_MEM8(0xA1) +-#define POCR0SA_8 0 +-#define POCR0SA_9 1 +-#define POCR0SA_10 2 +-#define POCR0SA_11 3 +-#define POCR0SA_00 2 /* Deprecated */ +-#define POCR0SA_01 3 /* Deprecated */ +- +-#define POCR0RA _SFR_MEM16(0xA2) +- +-#define POCR0RAL _SFR_MEM8(0xA2) +-#define POCR0RA_0 0 +-#define POCR0RA_1 1 +-#define POCR0RA_2 2 +-#define POCR0RA_3 3 +-#define POCR0RA_4 4 +-#define POCR0RA_5 5 +-#define POCR0RA_6 6 +-#define POCR0RA_7 7 +- +-#define POCR0RAH _SFR_MEM8(0xA3) +-#define POCR0RA_8 0 +-#define POCR0RA_9 1 +-#define POCR0RA_10 2 +-#define POCR0RA_11 3 +-#define POCR0RA_00 2 /* Deprecated */ +-#define POCR0RA_01 3 /* Deprecated */ +- +-#define POCR0SB _SFR_MEM16(0xA4) +- +-#define POCR0SBL _SFR_MEM8(0xA4) +-#define POCR0SB_0 0 +-#define POCR0SB_1 1 +-#define POCR0SB_2 2 +-#define POCR0SB_3 3 +-#define POCR0SB_4 4 +-#define POCR0SB_5 5 +-#define POCR0SB_6 6 +-#define POCR0SB_7 7 +- +-#define POCR0SBH _SFR_MEM8(0xA5) +-#define POCR0SB_8 0 +-#define POCR0SB_9 1 +-#define POCR0SB_10 2 +-#define POCR0SB_11 3 +-#define POCR0SB_00 2 /* Deprecated */ +-#define POCR0SB_01 3 /* Deprecated */ +- +-#define POCR1SA _SFR_MEM16(0xA6) +- +-#define POCR1SAL _SFR_MEM8(0xA6) +-#define POCR1SA_0 0 +-#define POCR1SA_1 1 +-#define POCR1SA_2 2 +-#define POCR1SA_3 3 +-#define POCR1SA_4 4 +-#define POCR1SA_5 5 +-#define POCR1SA_6 6 +-#define POCR1SA_7 7 +- +-#define POCR1SAH _SFR_MEM8(0xA7) +-#define POCR1SA_8 0 +-#define POCR1SA_9 1 +-#define POCR1SA_10 2 +-#define POCR1SA_11 3 +-#define POCR1SA_00 2 /* Deprecated */ +-#define POCR1SA_01 3 /* Deprecated */ +- +-#define POCR1RA _SFR_MEM16(0xA8) +- +-#define POCR1RAL _SFR_MEM8(0xA8) +-#define POCR1RA_0 0 +-#define POCR1RA_1 1 +-#define POCR1RA_2 2 +-#define POCR1RA_3 3 +-#define POCR1RA_4 4 +-#define POCR1RA_5 5 +-#define POCR1RA_6 6 +-#define POCR1RA_7 7 +- +-#define POCR1RAH _SFR_MEM8(0xA9) +-#define POCR1RA_8 0 +-#define POCR1RA_9 1 +-#define POCR1RA_10 2 +-#define POCR1RA_11 3 +-#define POCR1RA_00 2 /* Deprecated */ +- +-#define POCR1SB _SFR_MEM16(0xAA) +- +-#define POCR1SBL _SFR_MEM8(0xAA) +-#define POCR1SB_0 0 +-#define POCR1SB_1 1 +-#define POCR1SB_2 2 +-#define POCR1SB_3 3 +-#define POCR1SB_4 4 +-#define POCR1SB_5 5 +-#define POCR1SB_6 6 +-#define POCR1SB_7 7 +- +-#define POCR1SBH _SFR_MEM8(0xAB) +-#define POCR1SB_8 0 +-#define POCR1SB_9 1 +-#define POCR1SB_10 2 +-#define POCR1SB_11 3 +-#define POCR1SB_00 2 /* Deprecated */ +-#define POCR1SB_01 3 /* Deprecated */ +- +-#define POCR2SA _SFR_MEM16(0xAC) +- +-#define POCR2SAL _SFR_MEM8(0xAC) +-#define POCR2SA_0 0 +-#define POCR2SA_1 1 +-#define POCR2SA_2 2 +-#define POCR2SA_3 3 +-#define POCR2SA_4 4 +-#define POCR2SA_5 5 +-#define POCR2SA_6 6 +-#define POCR2SA_7 7 +- +-#define POCR2SAH _SFR_MEM8(0xAD) +-#define POCR2SA_8 0 +-#define POCR2SA_9 1 +-#define POCR2SA_10 2 +-#define POCR2SA_11 3 +-#define POCR2SA_00 2 /* Deprecated */ +-#define POCR2SA_01 3 /* Deprecated */ +- +-#define POCR2RA _SFR_MEM16(0xAE) +- +-#define POCR2RAL _SFR_MEM8(0xAE) +-#define POCR2RA_0 0 +-#define POCR2RA_1 1 +-#define POCR2RA_2 2 +-#define POCR2RA_3 3 +-#define POCR2RA_4 4 +-#define POCR2RA_5 5 +-#define POCR2RA_6 6 +-#define POCR2RA_7 7 +- +-#define POCR2RAH _SFR_MEM8(0xAF) +-#define POCR2RA_8 0 +-#define POCR2RA_9 1 +-#define POCR2RA_10 2 +-#define POCR2RA_11 3 +-#define POCR2RA_00 2 /* Deprecated */ +-#define POCR2RA_01 3 /* Deprecated */ +- +-#define POCR2SB _SFR_MEM16(0xB0) +- +-#define POCR2SBL _SFR_MEM8(0xB0) +-#define POCR2SB_0 0 +-#define POCR2SB_1 1 +-#define POCR2SB_2 2 +-#define POCR2SB_3 3 +-#define POCR2SB_4 4 +-#define POCR2SB_5 5 +-#define POCR2SB_6 6 +-#define POCR2SB_7 7 +- +-#define POCR2SBH _SFR_MEM8(0xB1) +-#define POCR2SB_8 0 +-#define POCR2SB_9 1 +-#define POCR2SB_10 2 +-#define POCR2SB_11 3 +-#define POCR2SB_00 2 /* Deprecated */ +-#define POCR2SB_01 3 /* Deprecated */ +- +- +-#define POCRxRB _SFR_MEM16(0xB2) /* Deprecated */ +-#define POCR_RB _SFR_MEM16(0xB2) +- +-#define POCRxRBL _SFR_MEM8(0xB2) /* Deprecated */ +-#define POCR_RBL _SFR_MEM8(0xB2) +-#define POCR_RB_0 0 +-#define POCR_RB_1 1 +-#define POCR_RB_2 2 +-#define POCR_RB_3 3 +-#define POCR_RB_4 4 +-#define POCR_RB_5 5 +-#define POCR_RB_6 6 +-#define POCR_RB_7 7 +- +-#define POCRxRBH _SFR_MEM8(0xB3) /* Deprecated */ +-#define POCR_RBH _SFR_MEM8(0xB3) +-#define POCR_RB_8 0 +-#define POCR_RB_9 1 +-#define POCR_RB_10 2 +-#define POCR_RB_11 3 +-#define POCR_RB_00 2 /* Deprecated */ +-#define POCR_RB_01 3 /* Deprecated */ +- +-#define PSYNC _SFR_MEM8(0xB4) +-#define PSYNC00 0 +-#define PSYNC01 1 +-#define PSYNC10 2 +-#define PSYNC11 3 +-#define PSYNC20 4 +-#define PSYNC21 5 +- +-#define PCNF _SFR_MEM8(0xB5) +-#define POPA 2 +-#define POPB 3 +-#define PMODE 4 +-#define PULOCK 5 +- +-#define POC _SFR_MEM8(0xB6) +-#define POEN0A 0 +-#define POEN0B 1 +-#define POEN1A 2 +-#define POEN1B 3 +-#define POEN2A 4 +-#define POEN2B 5 +- +-#define PCTL _SFR_MEM8(0xB7) +-#define PRUN 0 +-#define PCCYC 1 +-#define PCLKSEL 5 +-#define PPRE0 6 +-#define PPRE1 7 +- +-#define PMIC0 _SFR_MEM8(0xB8) +-#define PRFM00 0 +-#define PRFM01 1 +-#define PRFM02 2 +-#define PAOC0 3 +-#define PFLTE0 4 +-#define PELEV0 5 +-#define PISEL0 6 +-#define POVEN0 7 +- +-#define PMIC1 _SFR_MEM8(0xB9) +-#define PRFM10 0 +-#define PRFM11 1 +-#define PRFM12 2 +-#define PAOC1 3 +-#define PFLTE1 4 +-#define PELEV1 5 +-#define PISEL1 6 +-#define POVEN1 7 +- +-#define PMIC2 _SFR_MEM8(0xBA) +-#define PRFM20 0 +-#define PRFM21 1 +-#define PRFM22 2 +-#define PAOC2 3 +-#define PFLTE2 4 +-#define PELEV2 5 +-#define PISEL2 6 +-#define POVEN2 7 +- +-#define PIM _SFR_MEM8(0xBB) +-#define PEOPE 0 +-#define PEVE0 1 +-#define PEVE1 2 +-#define PEVE2 3 +- +-#define PIFR _SFR_MEM8(0xBC) +-#define PEOP 0 +-#define PEV0 1 +-#define PEV1 2 +-#define PEV2 3 +- +-#define LINCR _SFR_MEM8(0xC8) +-#define LCMD0 0 +-#define LCMD1 1 +-#define LCMD2 2 +-#define LENA 3 +-#define LCONF0 4 +-#define LCONF1 5 +-#define LIN13 6 +-#define LSWRES 7 +- +-#define LINSIR _SFR_MEM8(0xC9) +-#define LRXOK 0 +-#define LTXOK 1 +-#define LIDOK 2 +-#define LERR 3 +-#define LBUSY 4 +-#define LIDST0 5 +-#define LIDST1 6 +-#define LIDST2 7 +- +-#define LINENIR _SFR_MEM8(0xCA) +-#define LENRXOK 0 +-#define LENTXOK 1 +-#define LENIDOK 2 +-#define LENERR 3 +- +-#define LINERR _SFR_MEM8(0xCB) +-#define LBERR 0 +-#define LCERR 1 +-#define LPERR 2 +-#define LSERR 3 +-#define LFERR 4 +-#define LOVERR 5 +-#define LTOERR 6 +-#define LABORT 7 +- +-#define LINBTR _SFR_MEM8(0xCC) +-#define LBT0 0 +-#define LBT1 1 +-#define LBT2 2 +-#define LBT3 3 +-#define LBT4 4 +-#define LBT5 5 +-#define LDISR 7 +- +-#define LINBRR _SFR_MEM16(0xCD) +- +-#define LINBRRL _SFR_MEM8(0xCD) +-#define LDIV0 0 +-#define LDIV1 1 +-#define LDIV2 2 +-#define LDIV3 3 +-#define LDIV4 4 +-#define LDIV5 5 +-#define LDIV6 6 +-#define LDIV7 7 +- +-#define LINBRRH _SFR_MEM8(0xCE) +-#define LDIV8 0 +-#define LDIV9 1 +-#define LDIV10 2 +-#define LDIV11 3 +- +-#define LINDLR _SFR_MEM8(0xCF) +-#define LRXDL0 0 +-#define LRXDL1 1 +-#define LRXDL2 2 +-#define LRXDL3 3 +-#define LTXDL0 4 +-#define LTXDL1 5 +-#define LTXDL2 6 +-#define LTXDL3 7 +- +-#define LINIDR _SFR_MEM8(0xD0) +-#define LID0 0 +-#define LID1 1 +-#define LID2 2 +-#define LID3 3 +-#define LID4 4 +-#define LID5 5 +-#define LP0 6 +-#define LP1 7 +- +-#define LINSEL _SFR_MEM8(0xD1) +-#define LINDX0 0 +-#define LINDX1 1 +-#define LINDX2 2 +-#define LAINC 3 +- +-#define LINDAT _SFR_MEM8(0xD2) +-#define LDATA0 0 +-#define LDATA1 1 +-#define LDATA2 2 +-#define LDATA3 3 +-#define LDATA4 4 +-#define LDATA5 5 +-#define LDATA6 6 +-#define LDATA7 7 +- +-#define CANGCON _SFR_MEM8(0xD8) +-#define SWRES 0 +-#define ENASTB 1 +-#define TEST 2 +-#define LISTEN 3 +-#define SYNTTC 4 +-#define TTC 5 +-#define OVRQ 6 +-#define ABRQ 7 +- +-#define CANGSTA _SFR_MEM8(0xD9) +-#define ERRP 0 +-#define BOFF 1 +-#define ENFG 2 +-#define RXBSY 3 +-#define TXBSY 4 +-#define OVFG 6 +- +-#define CANGIT _SFR_MEM8(0xDA) +-#define AERG 0 +-#define FERG 1 +-#define CERG 2 +-#define SERG 3 +-#define BXOK 4 +-#define OVRTIM 5 +-#define BOFFIT 6 +-#define CANIT 7 +- +-#define CANGIE _SFR_MEM8(0xDB) +-#define ENOVRT 0 +-#define ENERG 1 +-#define ENBX 2 +-#define ENERR 3 +-#define ENTX 4 +-#define ENRX 5 +-#define ENBOFF 6 +-#define ENIT 7 +- +-#define CANEN2 _SFR_MEM8(0xDC) +-#define ENMOB0 0 +-#define ENMOB1 1 +-#define ENMOB2 2 +-#define ENMOB3 3 +-#define ENMOB4 4 +-#define ENMOB5 5 +- +-#define CANEN1 _SFR_MEM8(0xDD) +- +-#define CANIE2 _SFR_MEM8(0xDE) +-#define IEMOB0 0 +-#define IEMOB1 1 +-#define IEMOB2 2 +-#define IEMOB3 3 +-#define IEMOB4 4 +-#define IEMOB5 5 +- +-#define CANIE1 _SFR_MEM8(0xDF) +- +-/* RegDef: CAN Status Interrupt MOb Register*/ +-#define CANSIT _SFR_MEM16(0xE0) +- +-#define CANSIT2 _SFR_MEM8(0xE0) +-#define SIT0 0 +-#define SIT1 1 +-#define SIT2 2 +-#define SIT3 3 +-#define SIT4 4 +-#define SIT5 5 +- +-#define CANSIT1 _SFR_MEM8(0xE1) +- +-#define CANBT1 _SFR_MEM8(0xE2) +-#define BRP0 1 +-#define BRP1 2 +-#define BRP2 3 +-#define BRP3 4 +-#define BRP4 5 +-#define BRP5 6 +- +-#define CANBT2 _SFR_MEM8(0xE3) +-#define PRS0 1 +-#define PRS1 2 +-#define PRS2 3 +-#define SJW0 5 +-#define SJW1 6 +- +-#define CANBT3 _SFR_MEM8(0xE4) +-#define SMP 0 +-#define PHS10 1 +-#define PHS11 2 +-#define PHS12 3 +-#define PHS20 4 +-#define PHS21 5 +-#define PHS22 6 +- +-#define CANTCON _SFR_MEM8(0xE5) +-#define TPRSC0 0 +-#define TPRSC1 1 +-#define TPRSC2 2 +-#define TPRSC3 3 +-#define TPRSC4 4 +-#define TPRSC5 5 +-#define TPRSC6 6 +-#define TPRSC7 7 +- +-#define CANTIM _SFR_MEM16(0xE6) +- +-#define CANTIML _SFR_MEM8(0xE6) +-#define CANTIM0 0 +-#define CANTIM1 1 +-#define CANTIM2 2 +-#define CANTIM3 3 +-#define CANTIM4 4 +-#define CANTIM5 5 +-#define CANTIM6 6 +-#define CANTIM7 7 +- +-#define CANTIMH _SFR_MEM8(0xE7) +-#define CANTIM8 0 +-#define CANTIM9 1 +-#define CANTIM10 2 +-#define CANTIM11 3 +-#define CANTIM12 4 +-#define CANTIM13 5 +-#define CANTIM14 6 +-#define CANTIM15 7 +- +-#define CANTTC _SFR_MEM16(0xE8) +- +-#define CANTTCL _SFR_MEM8(0xE8) +-#define TIMTCC0 0 +-#define TIMTCC1 1 +-#define TIMTCC2 2 +-#define TIMTCC3 3 +-#define TIMTCC4 4 +-#define TIMTCC5 5 +-#define TIMTCC6 6 +-#define TIMTCC7 7 +- +-#define CANTTCH _SFR_MEM8(0xE9) +-#define TIMTCC8 0 +-#define TIMTCC9 1 +-#define TIMTCC10 2 +-#define TIMTCC11 3 +-#define TIMTCC12 4 +-#define TIMTCC13 5 +-#define TIMTCC14 6 +-#define TIMTCC15 7 +- +-#define CANTEC _SFR_MEM8(0xEA) +-#define TEC0 0 +-#define TEC1 1 +-#define TEC2 2 +-#define TEC3 3 +-#define TEC4 4 +-#define TEC5 5 +-#define TEC6 6 +-#define TEC7 7 +- +-#define CANREC _SFR_MEM8(0xEB) +-#define REC0 0 +-#define REC1 1 +-#define REC2 2 +-#define REC3 3 +-#define REC4 4 +-#define REC5 5 +-#define REC6 6 +-#define REC7 7 +- +-#define CANHPMOB _SFR_MEM8(0xEC) +-#define CGP0 0 +-#define CGP1 1 +-#define CGP2 2 +-#define CGP3 3 +-#define HPMOB0 4 +-#define HPMOB1 5 +-#define HPMOB2 6 +-#define HPMOB3 7 +- +-#define CANPAGE _SFR_MEM8(0xED) +-#define INDX0 0 +-#define INDX1 1 +-#define INDX2 2 +-#define AINC 3 +-#define MOBNB0 4 +-#define MOBNB1 5 +-#define MOBNB2 6 +-#define MOBNB3 7 +- +-#define CANSTMOB _SFR_MEM8(0xEE) +-#define AERR 0 +-#define FERR 1 +-#define CERR 2 +-#define SERR 3 +-#define BERR 4 +-#define RXOK 5 +-#define TXOK 6 +-#define DLCW 7 +- +-#define CANCDMOB _SFR_MEM8(0xEF) +-#define DLC0 0 +-#define DLC1 1 +-#define DLC2 2 +-#define DLC3 3 +-#define IDE 4 +-#define RPLV 5 +-#define CONMOB0 6 +-#define CONMOB1 7 +- +-/* RegDef: CAN Identifier Tag Registers*/ +-#define CANIDT _SFR_MEM32(0xF0) +- +-#define CANIDT4 _SFR_MEM8(0xF0) +-#define RB0TAG 0 +-#define RB1TAG 1 +-#define RTRTAG 2 +-#define IDT0 3 +-#define IDT1 4 +-#define IDT2 5 +-#define IDT3 6 +-#define IDT4 7 +- +-#define CANIDT3 _SFR_MEM8(0xF1) +-#define IDT5 0 +-#define IDT6 1 +-#define IDT7 2 +-#define IDT8 3 +-#define IDT9 4 +-#define IDT10 5 +-#define IDT11 6 +-#define IDT12 7 +- +-#define CANIDT2 _SFR_MEM8(0xF2) +-#define IDT13 0 +-#define IDT14 1 +-#define IDT15 2 +-#define IDT16 3 +-#define IDT17 4 +-#define IDT18 5 +-#define IDT19 6 +-#define IDT20 7 +- +-#define CANIDT1 _SFR_MEM8(0xF3) +-#define IDT21 0 +-#define IDT22 1 +-#define IDT23 2 +-#define IDT24 3 +-#define IDT25 4 +-#define IDT26 5 +-#define IDT27 6 +-#define IDT28 7 +- +-/* RegDef: CAN Identifier Mask Registers */ +-#define CANIDM _SFR_MEM32(0xF4) +- +-#define CANIDM4 _SFR_MEM8(0xF4) +-#define IDEMSK 0 +-#define RTRMSK 2 +-#define IDMSK0 3 +-#define IDMSK1 4 +-#define IDMSK2 5 +-#define IDMSK3 6 +-#define IDMSK4 7 +- +-#define CANIDM3 _SFR_MEM8(0xF5) +-#define IDMSK5 0 +-#define IDMSK6 1 +-#define IDMSK7 2 +-#define IDMSK8 3 +-#define IDMSK9 4 +-#define IDMSK10 5 +-#define IDMSK11 6 +-#define IDMSK12 7 +- +-#define CANIDM2 _SFR_MEM8(0xF6) +-#define IDMSK13 0 +-#define IDMSK14 1 +-#define IDMSK15 2 +-#define IDMSK16 3 +-#define IDMSK17 4 +-#define IDMSK18 5 +-#define IDMSK19 6 +-#define IDMSK20 7 +- +-#define CANIDM1 _SFR_MEM8(0xF7) +-#define IDMSK21 0 +-#define IDMSK22 1 +-#define IDMSK23 2 +-#define IDMSK24 3 +-#define IDMSK25 4 +-#define IDMSK26 5 +-#define IDMSK27 6 +-#define IDMSK28 7 +- +-#define CANSTM _SFR_MEM16(0xF8) +- +-#define CANSTML _SFR_MEM8(0xF8) +-#define TIMSTM0 0 +-#define TIMSTM1 1 +-#define TIMSTM2 2 +-#define TIMSTM3 3 +-#define TIMSTM4 4 +-#define TIMSTM5 5 +-#define TIMSTM6 6 +-#define TIMSTM7 7 +- +-#define CANSTMH _SFR_MEM8(0xF9) +-#define TIMSTM8 0 +-#define TIMSTM9 1 +-#define TIMSTM10 2 +-#define TIMSTM11 3 +-#define TIMSTM12 4 +-#define TIMSTM13 5 +-#define TIMSTM14 6 +-#define TIMSTM15 7 +- +-#define CANMSG _SFR_MEM8(0xFA) +-#define MSG0 0 +-#define MSG1 1 +-#define MSG2 2 +-#define MSG3 3 +-#define MSG4 4 +-#define MSG5 5 +-#define MSG6 6 +-#define MSG7 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define ANACOMP0_vect_num 1 +-#define ANACOMP0_vect _VECTOR(1) /* Analog Comparator 0 */ +-#define ANACOMP1_vect_num 2 +-#define ANACOMP1_vect _VECTOR(2) /* Analog Comparator 1 */ +-#define ANACOMP2_vect_num 3 +-#define ANACOMP2_vect _VECTOR(3) /* Analog Comparator 2 */ +-#define ANACOMP3_vect_num 4 +-#define ANACOMP3_vect _VECTOR(4) /* Analog Comparator 3 */ +-#define PSC_FAULT_vect_num 5 +-#define PSC_FAULT_vect _VECTOR(5) /* PSC Fault */ +-#define PSC_EC_vect_num 6 +-#define PSC_EC_vect _VECTOR(6) /* PSC End of Cycle */ +-#define INT0_vect_num 7 +-#define INT0_vect _VECTOR(7) /* External Interrupt Request 0 */ +-#define INT1_vect_num 8 +-#define INT1_vect _VECTOR(8) /* External Interrupt Request 1 */ +-#define INT2_vect_num 9 +-#define INT2_vect _VECTOR(9) /* External Interrupt Request 2 */ +-#define INT3_vect_num 10 +-#define INT3_vect _VECTOR(10) /* External Interrupt Request 3 */ +-#define TIMER1_CAPT_vect_num 11 +-#define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */ +-#define TIMER1_COMPA_vect_num 12 +-#define TIMER1_COMPA_vect _VECTOR(12) /* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPB_vect_num 13 +-#define TIMER1_COMPB_vect _VECTOR(13) /* Timer/Counter1 Compare Match B */ +-#define TIMER1_OVF_vect_num 14 +-#define TIMER1_OVF_vect _VECTOR(14) /* Timer1/Counter1 Overflow */ +-#define TIMER0_COMPA_vect_num 15 +-#define TIMER0_COMPA_vect _VECTOR(15) /* Timer/Counter0 Compare Match A */ +-#define TIMER0_COMPB_vect_num 16 +-#define TIMER0_COMPB_vect _VECTOR(16) /* Timer/Counter0 Compare Match B */ +-#define TIMER0_OVF_vect_num 17 +-#define TIMER0_OVF_vect _VECTOR(17) /* Timer/Counter0 Overflow */ +-#define CAN_INT_vect_num 18 +-#define CAN_INT_vect _VECTOR(18) /* CAN MOB, Burst, General Errors */ +-#define CAN_TOVF_vect_num 19 +-#define CAN_TOVF_vect _VECTOR(19) /* CAN Timer Overflow */ +-#define LIN_TC_vect_num 20 +-#define LIN_TC_vect _VECTOR(20) /* LIN Transfer Complete */ +-#define LIN_ERR_vect_num 21 +-#define LIN_ERR_vect _VECTOR(21) /* LIN Error */ +-#define PCINT0_vect_num 22 +-#define PCINT0_vect _VECTOR(22) /* Pin Change Interrupt Request 0 */ +-#define PCINT1_vect_num 23 +-#define PCINT1_vect _VECTOR(23) /* Pin Change Interrupt Request 1 */ +-#define PCINT2_vect_num 24 +-#define PCINT2_vect _VECTOR(24) /* Pin Change Interrupt Request 2 */ +-#define PCINT3_vect_num 25 +-#define PCINT3_vect _VECTOR(25) /* Pin Change Interrupt Request 3 */ +-#define SPI_STC_vect_num 26 +-#define SPI_STC_vect _VECTOR(26) /* SPI Serial Transfer Complete */ +-#define ADC_vect_num 27 +-#define ADC_vect _VECTOR(27) /* ADC Conversion Complete */ +-#define WDT_vect_num 28 +-#define WDT_vect _VECTOR(28) /* Watchdog Time-Out Interrupt */ +-#define EE_READY_vect_num 29 +-#define EE_READY_vect _VECTOR(29) /* EEPROM Ready */ +-#define SPM_READY_vect_num 30 +-#define SPM_READY_vect _VECTOR(30) /* Store Program Memory Read */ +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (31 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (128) +-#define RAMSTART (0x0100) +-#define RAMSIZE (2048) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (0x0) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x3FF) +-#define E2PAGESIZE (4) +-#define FLASHEND (0x7FFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector Trigger Level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector Trigger Level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector Trigger Level */ +-#define FUSE_PSCRVB (unsigned char)~_BV(3) /* PSC Outputs xB Reset Value */ +-#define FUSE_PSCRVA (unsigned char)~_BV(4) /* PSC Outputs xA Reset Value */ +-#define FUSE_PSCRB (unsigned char)~_BV(5) /* PSC Reset Behavior */ +-#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_BODLEVEL1) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x95 +-#define SIGNATURE_2 0x84 +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison POCR0SA_00 +-#pragma GCC poison POCR0SA_01 +-#pragma GCC poison POCR0RA_00 +-#pragma GCC poison POCR0RA_01 +-#pragma GCC poison POCR0SB_00 +-#pragma GCC poison POCR0SB_01 +-#pragma GCC poison POCR1SA_00 +-#pragma GCC poison POCR1SA_01 +-#pragma GCC poison POCR1RA_00 +-#pragma GCC poison POCR1SB_00 +-#pragma GCC poison POCR1SB_01 +-#pragma GCC poison POCR2SA_00 +-#pragma GCC poison POCR2SA_01 +-#pragma GCC poison POCR2RA_00 +-#pragma GCC poison POCR2RA_01 +-#pragma GCC poison POCR2SB_00 +-#pragma GCC poison POCR2SB_01 +-#pragma GCC poison POCRxRB +-#pragma GCC poison POCRxRBL +-#pragma GCC poison POCRxRBH +-#pragma GCC poison POCR_RB_00 +-#pragma GCC poison POCR_RB_01 +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +-#endif /* _AVR_ATmega32M1_H_ */ +- ++/* Copyright (c) 2008-2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom32m1.h 2235 2011-03-17 04:13:14Z arcanum $ */ ++ ++/* avr/iom32m1.h - definitions for ATmega32M1 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom32m1.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATmega32M1_H_ ++#define _AVR_ATmega32M1_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++#define PINC7 7 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++#define DDC7 7 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC3 3 ++#define PORTC4 4 ++#define PORTC5 5 ++#define PORTC6 6 ++#define PORTC7 7 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE0 0 ++#define PINE1 1 ++#define PINE2 2 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE0 0 ++#define DDE1 1 ++#define DDE2 2 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE0 0 ++#define PORTE1 1 ++#define PORTE2 2 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define GPIOR1 _SFR_IO8(0x19) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x1A) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++#define PCIF3 3 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++#define INT3 3 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++#define EEAR9 1 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR10 0 ++#define PSRSYNC 0 ++#define ICPSEL1 6 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define OCR0A _SFR_IO8(0x27) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define OCR0B _SFR_IO8(0x28) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define PLLCSR _SFR_IO8(0x29) ++#define PLOCK 0 ++#define PLLE 1 ++#define PLLF 2 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define ACSR _SFR_IO8(0x30) ++#define AC0O 0 ++#define AC1O 1 ++#define AC2O 2 ++#define AC3O 3 ++#define AC0IF 4 ++#define AC1IF 5 ++#define AC2IF 6 ++#define AC3IF 7 ++ ++#define DWDR _SFR_IO8(0x31) ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define SPIPS 7 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRLIN 1 ++#define PRSPI 2 ++#define PRTIM0 3 ++#define PRTIM1 4 ++#define PRPSC 5 ++#define PRCAN 6 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++#define PCIE3 3 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++#define PCMSK0 _SFR_MEM8(0x6A) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6B) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK2 _SFR_MEM8(0x6C) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define PCMSK3 _SFR_MEM8(0x6D) ++#define PCINT24 0 ++#define PCINT25 1 ++#define PCINT26 2 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define AMP0CSR _SFR_MEM8(0x75) ++#define AMP0TS0 0 ++#define AMP0TS1 1 ++#define AMP0TS2 2 ++#define AMPCMP0 3 ++#define AMP0G0 4 ++#define AMP0G1 5 ++#define AMP0IS 6 ++#define AMP0EN 7 ++ ++#define AMP1CSR _SFR_MEM8(0x76) ++#define AMP1TS0 0 ++#define AMP1TS1 1 ++#define AMP1TS2 2 ++#define AMPCMP1 3 ++#define AMP1G0 4 ++#define AMP1G1 5 ++#define AMP1IS 6 ++#define AMP1EN 7 ++ ++#define AMP2CSR _SFR_MEM8(0x77) ++#define AMP2TS0 0 ++#define AMP2TS1 1 ++#define AMP2TS2 2 ++#define AMPCMP2 3 ++#define AMP2G0 4 ++#define AMP2G1 5 ++#define AMP2IS 6 ++#define AMP2EN 7 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_MEM8(0x79) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ADTS3 3 ++#define AREFEN 5 ++#define ISRCEN 6 ++#define ADHSM 7 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define ADC8D 0 ++#define ADC9D 1 ++#define ADC10D 2 ++#define AMP0ND 3 ++#define AMP0PD 4 ++#define ACMP0D 5 ++#define AMP2PD 6 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define DACON _SFR_MEM8(0x90) ++#define DAEN 0 ++#define DAOE 1 ++#define DALA 2 ++#define DATS0 4 ++#define DATS1 5 ++#define DATS2 6 ++#define DAATE 7 ++ ++#define DAC _SFR_MEM16(0x91) ++ ++#define DACL _SFR_MEM8(0x91) ++#define DACL0 0 ++#define DACL1 1 ++#define DACL2 2 ++#define DACL3 3 ++#define DACL4 4 ++#define DACL5 5 ++#define DACL6 6 ++#define DACL7 7 ++ ++#define DACH _SFR_MEM8(0x92) ++#define DACH0 0 ++#define DACH1 1 ++#define DACH2 2 ++#define DACH3 3 ++#define DACH4 4 ++#define DACH5 5 ++#define DACH6 6 ++#define DACH7 7 ++ ++#define AC0CON _SFR_MEM8(0x94) ++#define AC0M0 0 ++#define AC0M1 1 ++#define AC0M2 2 ++#define ACCKSEL 3 ++#define AC0IS0 4 ++#define AC0IS1 5 ++#define AC0IE 6 ++#define AC0EN 7 ++ ++#define AC1CON _SFR_MEM8(0x95) ++#define AC1M0 0 ++#define AC1M1 1 ++#define AC1M2 2 ++#define AC1ICE 3 ++#define AC1IS0 4 ++#define AC1IS1 5 ++#define AC1IE 6 ++#define AC1EN 7 ++ ++#define AC2CON _SFR_MEM8(0x96) ++#define AC2M0 0 ++#define AC2M1 1 ++#define AC2M2 2 ++#define AC2IS0 4 ++#define AC2IS1 5 ++#define AC2IE 6 ++#define AC2EN 7 ++ ++#define AC3CON _SFR_MEM8(0x97) ++#define AC3M0 0 ++#define AC3M1 1 ++#define AC3M2 2 ++#define AC3IS0 4 ++#define AC3IS1 5 ++#define AC3IE 6 ++#define AC3EN 7 ++ ++#define POCR0SA _SFR_MEM16(0xA0) ++ ++#define POCR0SAL _SFR_MEM8(0xA0) ++#define POCR0SA_0 0 ++#define POCR0SA_1 1 ++#define POCR0SA_2 2 ++#define POCR0SA_3 3 ++#define POCR0SA_4 4 ++#define POCR0SA_5 5 ++#define POCR0SA_6 6 ++#define POCR0SA_7 7 ++ ++#define POCR0SAH _SFR_MEM8(0xA1) ++#define POCR0SA_8 0 ++#define POCR0SA_9 1 ++#define POCR0SA_10 2 ++#define POCR0SA_11 3 ++#define POCR0SA_00 2 /* Deprecated */ ++#define POCR0SA_01 3 /* Deprecated */ ++ ++#define POCR0RA _SFR_MEM16(0xA2) ++ ++#define POCR0RAL _SFR_MEM8(0xA2) ++#define POCR0RA_0 0 ++#define POCR0RA_1 1 ++#define POCR0RA_2 2 ++#define POCR0RA_3 3 ++#define POCR0RA_4 4 ++#define POCR0RA_5 5 ++#define POCR0RA_6 6 ++#define POCR0RA_7 7 ++ ++#define POCR0RAH _SFR_MEM8(0xA3) ++#define POCR0RA_8 0 ++#define POCR0RA_9 1 ++#define POCR0RA_10 2 ++#define POCR0RA_11 3 ++#define POCR0RA_00 2 /* Deprecated */ ++#define POCR0RA_01 3 /* Deprecated */ ++ ++#define POCR0SB _SFR_MEM16(0xA4) ++ ++#define POCR0SBL _SFR_MEM8(0xA4) ++#define POCR0SB_0 0 ++#define POCR0SB_1 1 ++#define POCR0SB_2 2 ++#define POCR0SB_3 3 ++#define POCR0SB_4 4 ++#define POCR0SB_5 5 ++#define POCR0SB_6 6 ++#define POCR0SB_7 7 ++ ++#define POCR0SBH _SFR_MEM8(0xA5) ++#define POCR0SB_8 0 ++#define POCR0SB_9 1 ++#define POCR0SB_10 2 ++#define POCR0SB_11 3 ++#define POCR0SB_00 2 /* Deprecated */ ++#define POCR0SB_01 3 /* Deprecated */ ++ ++#define POCR1SA _SFR_MEM16(0xA6) ++ ++#define POCR1SAL _SFR_MEM8(0xA6) ++#define POCR1SA_0 0 ++#define POCR1SA_1 1 ++#define POCR1SA_2 2 ++#define POCR1SA_3 3 ++#define POCR1SA_4 4 ++#define POCR1SA_5 5 ++#define POCR1SA_6 6 ++#define POCR1SA_7 7 ++ ++#define POCR1SAH _SFR_MEM8(0xA7) ++#define POCR1SA_8 0 ++#define POCR1SA_9 1 ++#define POCR1SA_10 2 ++#define POCR1SA_11 3 ++#define POCR1SA_00 2 /* Deprecated */ ++#define POCR1SA_01 3 /* Deprecated */ ++ ++#define POCR1RA _SFR_MEM16(0xA8) ++ ++#define POCR1RAL _SFR_MEM8(0xA8) ++#define POCR1RA_0 0 ++#define POCR1RA_1 1 ++#define POCR1RA_2 2 ++#define POCR1RA_3 3 ++#define POCR1RA_4 4 ++#define POCR1RA_5 5 ++#define POCR1RA_6 6 ++#define POCR1RA_7 7 ++ ++#define POCR1RAH _SFR_MEM8(0xA9) ++#define POCR1RA_8 0 ++#define POCR1RA_9 1 ++#define POCR1RA_10 2 ++#define POCR1RA_11 3 ++#define POCR1RA_00 2 /* Deprecated */ ++ ++#define POCR1SB _SFR_MEM16(0xAA) ++ ++#define POCR1SBL _SFR_MEM8(0xAA) ++#define POCR1SB_0 0 ++#define POCR1SB_1 1 ++#define POCR1SB_2 2 ++#define POCR1SB_3 3 ++#define POCR1SB_4 4 ++#define POCR1SB_5 5 ++#define POCR1SB_6 6 ++#define POCR1SB_7 7 ++ ++#define POCR1SBH _SFR_MEM8(0xAB) ++#define POCR1SB_8 0 ++#define POCR1SB_9 1 ++#define POCR1SB_10 2 ++#define POCR1SB_11 3 ++#define POCR1SB_00 2 /* Deprecated */ ++#define POCR1SB_01 3 /* Deprecated */ ++ ++#define POCR2SA _SFR_MEM16(0xAC) ++ ++#define POCR2SAL _SFR_MEM8(0xAC) ++#define POCR2SA_0 0 ++#define POCR2SA_1 1 ++#define POCR2SA_2 2 ++#define POCR2SA_3 3 ++#define POCR2SA_4 4 ++#define POCR2SA_5 5 ++#define POCR2SA_6 6 ++#define POCR2SA_7 7 ++ ++#define POCR2SAH _SFR_MEM8(0xAD) ++#define POCR2SA_8 0 ++#define POCR2SA_9 1 ++#define POCR2SA_10 2 ++#define POCR2SA_11 3 ++#define POCR2SA_00 2 /* Deprecated */ ++#define POCR2SA_01 3 /* Deprecated */ ++ ++#define POCR2RA _SFR_MEM16(0xAE) ++ ++#define POCR2RAL _SFR_MEM8(0xAE) ++#define POCR2RA_0 0 ++#define POCR2RA_1 1 ++#define POCR2RA_2 2 ++#define POCR2RA_3 3 ++#define POCR2RA_4 4 ++#define POCR2RA_5 5 ++#define POCR2RA_6 6 ++#define POCR2RA_7 7 ++ ++#define POCR2RAH _SFR_MEM8(0xAF) ++#define POCR2RA_8 0 ++#define POCR2RA_9 1 ++#define POCR2RA_10 2 ++#define POCR2RA_11 3 ++#define POCR2RA_00 2 /* Deprecated */ ++#define POCR2RA_01 3 /* Deprecated */ ++ ++#define POCR2SB _SFR_MEM16(0xB0) ++ ++#define POCR2SBL _SFR_MEM8(0xB0) ++#define POCR2SB_0 0 ++#define POCR2SB_1 1 ++#define POCR2SB_2 2 ++#define POCR2SB_3 3 ++#define POCR2SB_4 4 ++#define POCR2SB_5 5 ++#define POCR2SB_6 6 ++#define POCR2SB_7 7 ++ ++#define POCR2SBH _SFR_MEM8(0xB1) ++#define POCR2SB_8 0 ++#define POCR2SB_9 1 ++#define POCR2SB_10 2 ++#define POCR2SB_11 3 ++#define POCR2SB_00 2 /* Deprecated */ ++#define POCR2SB_01 3 /* Deprecated */ ++ ++ ++#define POCRxRB _SFR_MEM16(0xB2) /* Deprecated */ ++#define POCR_RB _SFR_MEM16(0xB2) ++ ++#define POCRxRBL _SFR_MEM8(0xB2) /* Deprecated */ ++#define POCR_RBL _SFR_MEM8(0xB2) ++#define POCR_RB_0 0 ++#define POCR_RB_1 1 ++#define POCR_RB_2 2 ++#define POCR_RB_3 3 ++#define POCR_RB_4 4 ++#define POCR_RB_5 5 ++#define POCR_RB_6 6 ++#define POCR_RB_7 7 ++ ++#define POCRxRBH _SFR_MEM8(0xB3) /* Deprecated */ ++#define POCR_RBH _SFR_MEM8(0xB3) ++#define POCR_RB_8 0 ++#define POCR_RB_9 1 ++#define POCR_RB_10 2 ++#define POCR_RB_11 3 ++#define POCR_RB_00 2 /* Deprecated */ ++#define POCR_RB_01 3 /* Deprecated */ ++ ++#define PSYNC _SFR_MEM8(0xB4) ++#define PSYNC00 0 ++#define PSYNC01 1 ++#define PSYNC10 2 ++#define PSYNC11 3 ++#define PSYNC20 4 ++#define PSYNC21 5 ++ ++#define PCNF _SFR_MEM8(0xB5) ++#define POPA 2 ++#define POPB 3 ++#define PMODE 4 ++#define PULOCK 5 ++ ++#define POC _SFR_MEM8(0xB6) ++#define POEN0A 0 ++#define POEN0B 1 ++#define POEN1A 2 ++#define POEN1B 3 ++#define POEN2A 4 ++#define POEN2B 5 ++ ++#define PCTL _SFR_MEM8(0xB7) ++#define PRUN 0 ++#define PCCYC 1 ++#define PCLKSEL 5 ++#define PPRE0 6 ++#define PPRE1 7 ++ ++#define PMIC0 _SFR_MEM8(0xB8) ++#define PRFM00 0 ++#define PRFM01 1 ++#define PRFM02 2 ++#define PAOC0 3 ++#define PFLTE0 4 ++#define PELEV0 5 ++#define PISEL0 6 ++#define POVEN0 7 ++ ++#define PMIC1 _SFR_MEM8(0xB9) ++#define PRFM10 0 ++#define PRFM11 1 ++#define PRFM12 2 ++#define PAOC1 3 ++#define PFLTE1 4 ++#define PELEV1 5 ++#define PISEL1 6 ++#define POVEN1 7 ++ ++#define PMIC2 _SFR_MEM8(0xBA) ++#define PRFM20 0 ++#define PRFM21 1 ++#define PRFM22 2 ++#define PAOC2 3 ++#define PFLTE2 4 ++#define PELEV2 5 ++#define PISEL2 6 ++#define POVEN2 7 ++ ++#define PIM _SFR_MEM8(0xBB) ++#define PEOPE 0 ++#define PEVE0 1 ++#define PEVE1 2 ++#define PEVE2 3 ++ ++#define PIFR _SFR_MEM8(0xBC) ++#define PEOP 0 ++#define PEV0 1 ++#define PEV1 2 ++#define PEV2 3 ++ ++#define LINCR _SFR_MEM8(0xC8) ++#define LCMD0 0 ++#define LCMD1 1 ++#define LCMD2 2 ++#define LENA 3 ++#define LCONF0 4 ++#define LCONF1 5 ++#define LIN13 6 ++#define LSWRES 7 ++ ++#define LINSIR _SFR_MEM8(0xC9) ++#define LRXOK 0 ++#define LTXOK 1 ++#define LIDOK 2 ++#define LERR 3 ++#define LBUSY 4 ++#define LIDST0 5 ++#define LIDST1 6 ++#define LIDST2 7 ++ ++#define LINENIR _SFR_MEM8(0xCA) ++#define LENRXOK 0 ++#define LENTXOK 1 ++#define LENIDOK 2 ++#define LENERR 3 ++ ++#define LINERR _SFR_MEM8(0xCB) ++#define LBERR 0 ++#define LCERR 1 ++#define LPERR 2 ++#define LSERR 3 ++#define LFERR 4 ++#define LOVERR 5 ++#define LTOERR 6 ++#define LABORT 7 ++ ++#define LINBTR _SFR_MEM8(0xCC) ++#define LBT0 0 ++#define LBT1 1 ++#define LBT2 2 ++#define LBT3 3 ++#define LBT4 4 ++#define LBT5 5 ++#define LDISR 7 ++ ++#define LINBRR _SFR_MEM16(0xCD) ++ ++#define LINBRRL _SFR_MEM8(0xCD) ++#define LDIV0 0 ++#define LDIV1 1 ++#define LDIV2 2 ++#define LDIV3 3 ++#define LDIV4 4 ++#define LDIV5 5 ++#define LDIV6 6 ++#define LDIV7 7 ++ ++#define LINBRRH _SFR_MEM8(0xCE) ++#define LDIV8 0 ++#define LDIV9 1 ++#define LDIV10 2 ++#define LDIV11 3 ++ ++#define LINDLR _SFR_MEM8(0xCF) ++#define LRXDL0 0 ++#define LRXDL1 1 ++#define LRXDL2 2 ++#define LRXDL3 3 ++#define LTXDL0 4 ++#define LTXDL1 5 ++#define LTXDL2 6 ++#define LTXDL3 7 ++ ++#define LINIDR _SFR_MEM8(0xD0) ++#define LID0 0 ++#define LID1 1 ++#define LID2 2 ++#define LID3 3 ++#define LID4 4 ++#define LID5 5 ++#define LP0 6 ++#define LP1 7 ++ ++#define LINSEL _SFR_MEM8(0xD1) ++#define LINDX0 0 ++#define LINDX1 1 ++#define LINDX2 2 ++#define LAINC 3 ++ ++#define LINDAT _SFR_MEM8(0xD2) ++#define LDATA0 0 ++#define LDATA1 1 ++#define LDATA2 2 ++#define LDATA3 3 ++#define LDATA4 4 ++#define LDATA5 5 ++#define LDATA6 6 ++#define LDATA7 7 ++ ++#define CANGCON _SFR_MEM8(0xD8) ++#define SWRES 0 ++#define ENASTB 1 ++#define TEST 2 ++#define LISTEN 3 ++#define SYNTTC 4 ++#define TTC 5 ++#define OVRQ 6 ++#define ABRQ 7 ++ ++#define CANGSTA _SFR_MEM8(0xD9) ++#define ERRP 0 ++#define BOFF 1 ++#define ENFG 2 ++#define RXBSY 3 ++#define TXBSY 4 ++#define OVFG 6 ++ ++#define CANGIT _SFR_MEM8(0xDA) ++#define AERG 0 ++#define FERG 1 ++#define CERG 2 ++#define SERG 3 ++#define BXOK 4 ++#define OVRTIM 5 ++#define BOFFIT 6 ++#define CANIT 7 ++ ++#define CANGIE _SFR_MEM8(0xDB) ++#define ENOVRT 0 ++#define ENERG 1 ++#define ENBX 2 ++#define ENERR 3 ++#define ENTX 4 ++#define ENRX 5 ++#define ENBOFF 6 ++#define ENIT 7 ++ ++#define CANEN2 _SFR_MEM8(0xDC) ++#define ENMOB0 0 ++#define ENMOB1 1 ++#define ENMOB2 2 ++#define ENMOB3 3 ++#define ENMOB4 4 ++#define ENMOB5 5 ++ ++#define CANEN1 _SFR_MEM8(0xDD) ++ ++#define CANIE2 _SFR_MEM8(0xDE) ++#define IEMOB0 0 ++#define IEMOB1 1 ++#define IEMOB2 2 ++#define IEMOB3 3 ++#define IEMOB4 4 ++#define IEMOB5 5 ++ ++#define CANIE1 _SFR_MEM8(0xDF) ++ ++/* RegDef: CAN Status Interrupt MOb Register*/ ++#define CANSIT _SFR_MEM16(0xE0) ++ ++#define CANSIT2 _SFR_MEM8(0xE0) ++#define SIT0 0 ++#define SIT1 1 ++#define SIT2 2 ++#define SIT3 3 ++#define SIT4 4 ++#define SIT5 5 ++ ++#define CANSIT1 _SFR_MEM8(0xE1) ++ ++#define CANBT1 _SFR_MEM8(0xE2) ++#define BRP0 1 ++#define BRP1 2 ++#define BRP2 3 ++#define BRP3 4 ++#define BRP4 5 ++#define BRP5 6 ++ ++#define CANBT2 _SFR_MEM8(0xE3) ++#define PRS0 1 ++#define PRS1 2 ++#define PRS2 3 ++#define SJW0 5 ++#define SJW1 6 ++ ++#define CANBT3 _SFR_MEM8(0xE4) ++#define SMP 0 ++#define PHS10 1 ++#define PHS11 2 ++#define PHS12 3 ++#define PHS20 4 ++#define PHS21 5 ++#define PHS22 6 ++ ++#define CANTCON _SFR_MEM8(0xE5) ++#define TPRSC0 0 ++#define TPRSC1 1 ++#define TPRSC2 2 ++#define TPRSC3 3 ++#define TPRSC4 4 ++#define TPRSC5 5 ++#define TPRSC6 6 ++#define TPRSC7 7 ++ ++#define CANTIM _SFR_MEM16(0xE6) ++ ++#define CANTIML _SFR_MEM8(0xE6) ++#define CANTIM0 0 ++#define CANTIM1 1 ++#define CANTIM2 2 ++#define CANTIM3 3 ++#define CANTIM4 4 ++#define CANTIM5 5 ++#define CANTIM6 6 ++#define CANTIM7 7 ++ ++#define CANTIMH _SFR_MEM8(0xE7) ++#define CANTIM8 0 ++#define CANTIM9 1 ++#define CANTIM10 2 ++#define CANTIM11 3 ++#define CANTIM12 4 ++#define CANTIM13 5 ++#define CANTIM14 6 ++#define CANTIM15 7 ++ ++#define CANTTC _SFR_MEM16(0xE8) ++ ++#define CANTTCL _SFR_MEM8(0xE8) ++#define TIMTCC0 0 ++#define TIMTCC1 1 ++#define TIMTCC2 2 ++#define TIMTCC3 3 ++#define TIMTCC4 4 ++#define TIMTCC5 5 ++#define TIMTCC6 6 ++#define TIMTCC7 7 ++ ++#define CANTTCH _SFR_MEM8(0xE9) ++#define TIMTCC8 0 ++#define TIMTCC9 1 ++#define TIMTCC10 2 ++#define TIMTCC11 3 ++#define TIMTCC12 4 ++#define TIMTCC13 5 ++#define TIMTCC14 6 ++#define TIMTCC15 7 ++ ++#define CANTEC _SFR_MEM8(0xEA) ++#define TEC0 0 ++#define TEC1 1 ++#define TEC2 2 ++#define TEC3 3 ++#define TEC4 4 ++#define TEC5 5 ++#define TEC6 6 ++#define TEC7 7 ++ ++#define CANREC _SFR_MEM8(0xEB) ++#define REC0 0 ++#define REC1 1 ++#define REC2 2 ++#define REC3 3 ++#define REC4 4 ++#define REC5 5 ++#define REC6 6 ++#define REC7 7 ++ ++#define CANHPMOB _SFR_MEM8(0xEC) ++#define CGP0 0 ++#define CGP1 1 ++#define CGP2 2 ++#define CGP3 3 ++#define HPMOB0 4 ++#define HPMOB1 5 ++#define HPMOB2 6 ++#define HPMOB3 7 ++ ++#define CANPAGE _SFR_MEM8(0xED) ++#define INDX0 0 ++#define INDX1 1 ++#define INDX2 2 ++#define AINC 3 ++#define MOBNB0 4 ++#define MOBNB1 5 ++#define MOBNB2 6 ++#define MOBNB3 7 ++ ++#define CANSTMOB _SFR_MEM8(0xEE) ++#define AERR 0 ++#define FERR 1 ++#define CERR 2 ++#define SERR 3 ++#define BERR 4 ++#define RXOK 5 ++#define TXOK 6 ++#define DLCW 7 ++ ++#define CANCDMOB _SFR_MEM8(0xEF) ++#define DLC0 0 ++#define DLC1 1 ++#define DLC2 2 ++#define DLC3 3 ++#define IDE 4 ++#define RPLV 5 ++#define CONMOB0 6 ++#define CONMOB1 7 ++ ++/* RegDef: CAN Identifier Tag Registers*/ ++#define CANIDT _SFR_MEM32(0xF0) ++ ++#define CANIDT4 _SFR_MEM8(0xF0) ++#define RB0TAG 0 ++#define RB1TAG 1 ++#define RTRTAG 2 ++#define IDT0 3 ++#define IDT1 4 ++#define IDT2 5 ++#define IDT3 6 ++#define IDT4 7 ++ ++#define CANIDT3 _SFR_MEM8(0xF1) ++#define IDT5 0 ++#define IDT6 1 ++#define IDT7 2 ++#define IDT8 3 ++#define IDT9 4 ++#define IDT10 5 ++#define IDT11 6 ++#define IDT12 7 ++ ++#define CANIDT2 _SFR_MEM8(0xF2) ++#define IDT13 0 ++#define IDT14 1 ++#define IDT15 2 ++#define IDT16 3 ++#define IDT17 4 ++#define IDT18 5 ++#define IDT19 6 ++#define IDT20 7 ++ ++#define CANIDT1 _SFR_MEM8(0xF3) ++#define IDT21 0 ++#define IDT22 1 ++#define IDT23 2 ++#define IDT24 3 ++#define IDT25 4 ++#define IDT26 5 ++#define IDT27 6 ++#define IDT28 7 ++ ++/* RegDef: CAN Identifier Mask Registers */ ++#define CANIDM _SFR_MEM32(0xF4) ++ ++#define CANIDM4 _SFR_MEM8(0xF4) ++#define IDEMSK 0 ++#define RTRMSK 2 ++#define IDMSK0 3 ++#define IDMSK1 4 ++#define IDMSK2 5 ++#define IDMSK3 6 ++#define IDMSK4 7 ++ ++#define CANIDM3 _SFR_MEM8(0xF5) ++#define IDMSK5 0 ++#define IDMSK6 1 ++#define IDMSK7 2 ++#define IDMSK8 3 ++#define IDMSK9 4 ++#define IDMSK10 5 ++#define IDMSK11 6 ++#define IDMSK12 7 ++ ++#define CANIDM2 _SFR_MEM8(0xF6) ++#define IDMSK13 0 ++#define IDMSK14 1 ++#define IDMSK15 2 ++#define IDMSK16 3 ++#define IDMSK17 4 ++#define IDMSK18 5 ++#define IDMSK19 6 ++#define IDMSK20 7 ++ ++#define CANIDM1 _SFR_MEM8(0xF7) ++#define IDMSK21 0 ++#define IDMSK22 1 ++#define IDMSK23 2 ++#define IDMSK24 3 ++#define IDMSK25 4 ++#define IDMSK26 5 ++#define IDMSK27 6 ++#define IDMSK28 7 ++ ++#define CANSTM _SFR_MEM16(0xF8) ++ ++#define CANSTML _SFR_MEM8(0xF8) ++#define TIMSTM0 0 ++#define TIMSTM1 1 ++#define TIMSTM2 2 ++#define TIMSTM3 3 ++#define TIMSTM4 4 ++#define TIMSTM5 5 ++#define TIMSTM6 6 ++#define TIMSTM7 7 ++ ++#define CANSTMH _SFR_MEM8(0xF9) ++#define TIMSTM8 0 ++#define TIMSTM9 1 ++#define TIMSTM10 2 ++#define TIMSTM11 3 ++#define TIMSTM12 4 ++#define TIMSTM13 5 ++#define TIMSTM14 6 ++#define TIMSTM15 7 ++ ++#define CANMSG _SFR_MEM8(0xFA) ++#define MSG0 0 ++#define MSG1 1 ++#define MSG2 2 ++#define MSG3 3 ++#define MSG4 4 ++#define MSG5 5 ++#define MSG6 6 ++#define MSG7 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define ANACOMP0_vect_num 1 ++#define ANACOMP0_vect _VECTOR(1) /* Analog Comparator 0 */ ++#define ANACOMP1_vect_num 2 ++#define ANACOMP1_vect _VECTOR(2) /* Analog Comparator 1 */ ++#define ANACOMP2_vect_num 3 ++#define ANACOMP2_vect _VECTOR(3) /* Analog Comparator 2 */ ++#define ANACOMP3_vect_num 4 ++#define ANACOMP3_vect _VECTOR(4) /* Analog Comparator 3 */ ++#define PSC_FAULT_vect_num 5 ++#define PSC_FAULT_vect _VECTOR(5) /* PSC Fault */ ++#define PSC_EC_vect_num 6 ++#define PSC_EC_vect _VECTOR(6) /* PSC End of Cycle */ ++#define INT0_vect_num 7 ++#define INT0_vect _VECTOR(7) /* External Interrupt Request 0 */ ++#define INT1_vect_num 8 ++#define INT1_vect _VECTOR(8) /* External Interrupt Request 1 */ ++#define INT2_vect_num 9 ++#define INT2_vect _VECTOR(9) /* External Interrupt Request 2 */ ++#define INT3_vect_num 10 ++#define INT3_vect _VECTOR(10) /* External Interrupt Request 3 */ ++#define TIMER1_CAPT_vect_num 11 ++#define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */ ++#define TIMER1_COMPA_vect_num 12 ++#define TIMER1_COMPA_vect _VECTOR(12) /* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPB_vect_num 13 ++#define TIMER1_COMPB_vect _VECTOR(13) /* Timer/Counter1 Compare Match B */ ++#define TIMER1_OVF_vect_num 14 ++#define TIMER1_OVF_vect _VECTOR(14) /* Timer1/Counter1 Overflow */ ++#define TIMER0_COMPA_vect_num 15 ++#define TIMER0_COMPA_vect _VECTOR(15) /* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPB_vect_num 16 ++#define TIMER0_COMPB_vect _VECTOR(16) /* Timer/Counter0 Compare Match B */ ++#define TIMER0_OVF_vect_num 17 ++#define TIMER0_OVF_vect _VECTOR(17) /* Timer/Counter0 Overflow */ ++#define CAN_INT_vect_num 18 ++#define CAN_INT_vect _VECTOR(18) /* CAN MOB, Burst, General Errors */ ++#define CAN_TOVF_vect_num 19 ++#define CAN_TOVF_vect _VECTOR(19) /* CAN Timer Overflow */ ++#define LIN_TC_vect_num 20 ++#define LIN_TC_vect _VECTOR(20) /* LIN Transfer Complete */ ++#define LIN_ERR_vect_num 21 ++#define LIN_ERR_vect _VECTOR(21) /* LIN Error */ ++#define PCINT0_vect_num 22 ++#define PCINT0_vect _VECTOR(22) /* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect_num 23 ++#define PCINT1_vect _VECTOR(23) /* Pin Change Interrupt Request 1 */ ++#define PCINT2_vect_num 24 ++#define PCINT2_vect _VECTOR(24) /* Pin Change Interrupt Request 2 */ ++#define PCINT3_vect_num 25 ++#define PCINT3_vect _VECTOR(25) /* Pin Change Interrupt Request 3 */ ++#define SPI_STC_vect_num 26 ++#define SPI_STC_vect _VECTOR(26) /* SPI Serial Transfer Complete */ ++#define ADC_vect_num 27 ++#define ADC_vect _VECTOR(27) /* ADC Conversion Complete */ ++#define WDT_vect_num 28 ++#define WDT_vect _VECTOR(28) /* Watchdog Time-Out Interrupt */ ++#define EE_READY_vect_num 29 ++#define EE_READY_vect _VECTOR(29) /* EEPROM Ready */ ++#define SPM_READY_vect_num 30 ++#define SPM_READY_vect _VECTOR(30) /* Store Program Memory Read */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (31 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (128) ++#define RAMSTART (0x0100) ++#define RAMSIZE (2048) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (0x0) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x3FF) ++#define E2PAGESIZE (4) ++#define FLASHEND (0x7FFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector Trigger Level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector Trigger Level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector Trigger Level */ ++#define FUSE_PSCRVB (unsigned char)~_BV(3) /* PSC Outputs xB Reset Value */ ++#define FUSE_PSCRVA (unsigned char)~_BV(4) /* PSC Outputs xA Reset Value */ ++#define FUSE_PSCRB (unsigned char)~_BV(5) /* PSC Reset Behavior */ ++#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_BODLEVEL1) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x84 ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison POCR0SA_00 ++#pragma GCC poison POCR0SA_01 ++#pragma GCC poison POCR0RA_00 ++#pragma GCC poison POCR0RA_01 ++#pragma GCC poison POCR0SB_00 ++#pragma GCC poison POCR0SB_01 ++#pragma GCC poison POCR1SA_00 ++#pragma GCC poison POCR1SA_01 ++#pragma GCC poison POCR1RA_00 ++#pragma GCC poison POCR1SB_00 ++#pragma GCC poison POCR1SB_01 ++#pragma GCC poison POCR2SA_00 ++#pragma GCC poison POCR2SA_01 ++#pragma GCC poison POCR2RA_00 ++#pragma GCC poison POCR2RA_01 ++#pragma GCC poison POCR2SB_00 ++#pragma GCC poison POCR2SB_01 ++#pragma GCC poison POCRxRB ++#pragma GCC poison POCRxRBL ++#pragma GCC poison POCRxRBH ++#pragma GCC poison POCR_RB_00 ++#pragma GCC poison POCR_RB_01 ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++#endif /* _AVR_ATmega32M1_H_ */ ++ +diff --git a/include/avr/iom32u2.h b/include/avr/iom32u2.h +index 249c3f0..5ab2276 100644 +--- a/include/avr/iom32u2.h ++++ b/include/avr/iom32u2.h +@@ -1,980 +1,986 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom32u2.h 2240 2011-05-09 22:18:18Z arcanum $ */ +- +-/* avr/iom32u2.h - definitions for ATmega32U2 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom32u2.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATmega32U2_H_ +-#define _AVR_ATmega32U2_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +-#define PINC7 7 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +-#define DDC7 7 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC4 4 +-#define PORTC5 5 +-#define PORTC6 6 +-#define PORTC7 7 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define OCF1C 3 +-#define ICF1 5 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +-#define PCIF1 1 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +-#define INTF2 2 +-#define INTF3 3 +-#define INTF4 4 +-#define INTF5 5 +-#define INTF6 6 +-#define INTF7 7 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +-#define INT2 2 +-#define INT3 3 +-#define INT4 4 +-#define INT5 5 +-#define INT6 6 +-#define INT7 7 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +-#define EEAR9 1 +-#define EEAR10 2 +-#define EEAR11 3 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSRSYNC 0 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define OCR0A _SFR_IO8(0x27) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define OCR0B _SFR_IO8(0x28) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define PLLCSR _SFR_IO8(0x29) +-#define PLOCK 0 +-#define PLLE 1 +-#define PLLP0 2 +-#define PLLP1 3 +-#define PLLP2 4 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define DWDR _SFR_IO8(0x31) +-#define DWDR0 0 +-#define DWDR1 1 +-#define DWDR2 2 +-#define DWDR3 3 +-#define DWDR4 4 +-#define DWDR5 5 +-#define DWDR6 6 +-#define DWDR7 7 +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +-#define USBRF 5 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define SIGRD 5 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define EIND _SFR_IO8(0x3C) +-#define EIND0 0 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define WDTCKD _SFR_MEM8(0x62) +-#define WCLKD0 0 +-#define WCLKD1 1 +-#define WDEWIE 2 +-#define WDEWIF 3 +- +-#define REGCR _SFR_MEM8(0x63) +-#define REGDIS 0 +- +-#define PRR0 _SFR_MEM8(0x64) +-#define PRSPI 2 +-#define PRTIM1 3 +-#define PRTIM0 5 +- +-#define PRR1 _SFR_MEM8(0x65) +-#define PRUSART1 0 +-#define PRUSB 7 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +-#define PCIE1 1 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define ISC20 4 +-#define ISC21 5 +-#define ISC30 6 +-#define ISC31 7 +- +-#define EICRB _SFR_MEM8(0x6A) +-#define ISC40 0 +-#define ISC41 1 +-#define ISC50 2 +-#define ISC51 3 +-#define ISC60 4 +-#define ISC61 5 +-#define ISC70 6 +-#define ISC71 7 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define OCIE1C 3 +-#define ICIE1 5 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1C0 2 +-#define COM1C1 3 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1C 5 +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define OCR1C _SFR_MEM16(0x8C) +- +-#define OCR1CL _SFR_MEM8(0x8C) +-#define OCR1CL0 0 +-#define OCR1CL1 1 +-#define OCR1CL2 2 +-#define OCR1CL3 3 +-#define OCR1CL4 4 +-#define OCR1CL5 5 +-#define OCR1CL6 6 +-#define OCR1CL7 7 +- +-#define OCR1CH _SFR_MEM8(0x8D) +-#define OCR1CH0 0 +-#define OCR1CH1 1 +-#define OCR1CH2 2 +-#define OCR1CH3 3 +-#define OCR1CH4 4 +-#define OCR1CH5 5 +-#define OCR1CH6 6 +-#define OCR1CH7 7 +- +-#define UCSR1A _SFR_MEM8(0xC8) +-#define MPCM1 0 +-#define U2X1 1 +-#define UPE1 2 +-#define DOR1 3 +-#define FE1 4 +-#define UDRE1 5 +-#define TXC1 6 +-#define RXC1 7 +- +-#define UCSR1B _SFR_MEM8(0xC9) +-#define TXB81 0 +-#define RXB81 1 +-#define UCSZ12 2 +-#define TXEN1 3 +-#define RXEN1 4 +-#define UDRIE1 5 +-#define TXCIE1 6 +-#define RXCIE1 7 +- +-#define UCSR1C _SFR_MEM8(0xCA) +-#define UCPOL1 0 +-#define UCSZ10 1 +-#define UCSZ11 2 +-#define USBS1 3 +-#define UPM10 4 +-#define UPM11 5 +-#define UMSEL10 6 +-#define UMSEL11 7 +- +-#define UCSR1D _SFR_MEM8(0xCB) +-#define RTSEN 0 +-#define CTSEN 1 +- +-#define UBRR1 _SFR_MEM16(0xCC) +- +-#define UBRR1L _SFR_MEM8(0xCC) +-#define UBRR1_0 0 +-#define UBRR1_1 1 +-#define UBRR1_2 2 +-#define UBRR1_3 3 +-#define UBRR1_4 4 +-#define UBRR1_5 5 +-#define UBRR1_6 6 +-#define UBRR1_7 7 +- +-#define UBRR1H _SFR_MEM8(0xCD) +-#define UBRR1_8 0 +-#define UBRR1_9 1 +-#define UBRR1_10 2 +-#define UBRR1_11 3 +- +-#define UDR1 _SFR_MEM8(0xCE) +-#define UDR1_0 0 +-#define UDR1_1 1 +-#define UDR1_2 2 +-#define UDR1_3 3 +-#define UDR1_4 4 +-#define UDR1_5 5 +-#define UDR1_6 6 +-#define UDR1_7 7 +- +-#define CLKSEL0 _SFR_MEM8(0xD0) +-#define CLKS 0 +-#define EXTE 2 +-#define RCE 3 +-#define EXSUT0 4 +-#define EXSUT1 5 +-#define RCSUT0 6 +-#define RCSUT1 7 +- +-#define CLKSEL1 _SFR_MEM8(0xD1) +-#define EXCKSEL0 0 +-#define EXCKSEL1 1 +-#define EXCKSEL2 2 +-#define EXCKSEL3 3 +-#define RCCKSEL0 4 +-#define RCCKSEL1 5 +-#define RCCKSEL2 6 +-#define RCCKSEL3 7 +- +-#define CLKSTA _SFR_MEM8(0xD2) +-#define EXTON 0 +-#define RCON 1 +- +-#define USBCON _SFR_MEM8(0xD8) +-#define FRZCLK 5 +-#define USBE 7 +- +-#define UDCON _SFR_MEM8(0xE0) +-#define DETACH 0 +-#define RMWKUP 1 +-#define RSTCPU 2 +- +-#define UDINT _SFR_MEM8(0xE1) +-#define SUSPI 0 +-#define SOFI 2 +-#define EORSTI 3 +-#define WAKEUPI 4 +-#define EORSMI 5 +-#define UPRSMI 6 +- +-#define UDIEN _SFR_MEM8(0xE2) +-#define SUSPE 0 +-#define SOFE 2 +-#define EORSTE 3 +-#define WAKEUPE 4 +-#define EORSME 5 +-#define UPRSME 6 +- +-#define UDADDR _SFR_MEM8(0xE3) +-#define UADD0 0 +-#define UADD1 1 +-#define UADD2 2 +-#define UADD3 3 +-#define UADD4 4 +-#define UADD5 5 +-#define UADD6 6 +-#define ADDEN 7 +- +-#define UDFNUM _SFR_MEM16(0xE4) +- +-#define UDFNUML _SFR_MEM8(0xE4) +-#define FNUM0 0 +-#define FNUM1 1 +-#define FNUM2 2 +-#define FNUM3 3 +-#define FNUM4 4 +-#define FNUM5 5 +-#define FNUM6 6 +-#define FNUM7 7 +- +-#define UDFNUMH _SFR_MEM8(0xE5) +-#define FNUM8 0 +-#define FNUM9 1 +-#define FNUM10 2 +- +-#define UDMFN _SFR_MEM8(0xE6) +-#define FNCERR 4 +- +-#define UEINTX _SFR_MEM8(0xE8) +-#define TXINI 0 +-#define STALLEDI 1 +-#define RXOUTI 2 +-#define RXSTPI 3 +-#define NAKOUTI 4 +-#define RWAL 5 +-#define NAKINI 6 +-#define FIFOCON 7 +- +-#define UENUM _SFR_MEM8(0xE9) +-#define EPNUM0 0 +-#define EPNUM1 1 +-#define EPNUM2 2 +- +-#define UERST _SFR_MEM8(0xEA) +-#define EPRST0 0 +-#define EPRST1 1 +-#define EPRST2 2 +-#define EPRST3 3 +-#define EPRST4 4 +- +-#define UECONX _SFR_MEM8(0xEB) +-#define EPEN 0 +-#define RSTDT 3 +-#define STALLRQC 4 +-#define STALLRQ 5 +- +-#define UECFG0X _SFR_MEM8(0xEC) +-#define EPDIR 0 +-#define EPTYPE0 6 +-#define EPTYPE1 7 +- +-#define UECFG1X _SFR_MEM8(0xED) +-#define ALLOC 1 +-#define EPBK0 2 +-#define EPBK1 3 +-#define EPSIZE0 4 +-#define EPSIZE1 5 +-#define EPSIZE2 6 +- +-#define UESTA0X _SFR_MEM8(0xEE) +-#define NBUSYBK0 0 +-#define NBUSYBK1 1 +-#define DTSEQ0 2 +-#define DTSEQ1 3 +-#define UNDERFI 5 +-#define OVERFI 6 +-#define CFGOK 7 +- +-#define UESTA1X _SFR_MEM8(0xEF) +-#define CURRBK0 0 +-#define CURRBK1 1 +-#define CTRLDIR 2 +- +-#define UEIENX _SFR_MEM8(0xF0) +-#define TXINE 0 +-#define STALLEDE 1 +-#define RXOUTE 2 +-#define RXSTPE 3 +-#define NAKOUTE 4 +-#define NAKINE 6 +-#define FLERRE 7 +- +-#define UEDATX _SFR_MEM8(0xF1) +-#define DAT0 0 +-#define DAT1 1 +-#define DAT2 2 +-#define DAT3 3 +-#define DAT4 4 +-#define DAT5 5 +-#define DAT6 6 +-#define DAT7 7 +- +-#define UEBCLX _SFR_MEM8(0xF2) +-#define BYCT0 0 +-#define BYCT1 1 +-#define BYCT2 2 +-#define BYCT3 3 +-#define BYCT4 4 +-#define BYCT5 5 +-#define BYCT6 6 +-#define BYCT7 7 +- +-#define UEINT _SFR_MEM8(0xF4) +-#define EPINT0 0 +-#define EPINT1 1 +-#define EPINT2 2 +-#define EPINT3 3 +-#define EPINT4 4 +- +-#define PS2CON _SFR_MEM8(0xFA) +-#define PS2EN 0 +- +-#define UPOE _SFR_MEM8(0xFB) +-#define DMI 0 +-#define DPI 1 +-#define DATAI 2 +-#define SCKI 3 +-#define UPDRV0 4 +-#define UPDRV1 5 +-#define UPWE0 6 +-#define UPWE1 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ +-#define INT2_vect_num 3 +-#define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ +-#define INT3_vect_num 4 +-#define INT3_vect _VECTOR(4) /* External Interrupt Request 3 */ +-#define INT4_vect_num 5 +-#define INT4_vect _VECTOR(5) /* External Interrupt Request 4 */ +-#define INT5_vect_num 6 +-#define INT5_vect _VECTOR(6) /* External Interrupt Request 5 */ +-#define INT6_vect_num 7 +-#define INT6_vect _VECTOR(7) /* External Interrupt Request 6 */ +-#define INT7_vect_num 8 +-#define INT7_vect _VECTOR(8) /* External Interrupt Request 7 */ +-#define PCINT0_vect_num 9 +-#define PCINT0_vect _VECTOR(9) /* Pin Change Interrupt Request 0 */ +-#define PCINT1_vect_num 10 +-#define PCINT1_vect _VECTOR(10) /* Pin Change Interrupt Request 1 */ +-#define USB_GEN_vect_num 11 +-#define USB_GEN_vect _VECTOR(11) /* USB General Interrupt Request */ +-#define USB_COM_vect_num 12 +-#define USB_COM_vect _VECTOR(12) /* USB Endpoint/Pipe Interrupt Communication Request */ +-#define WDT_vect_num 13 +-#define WDT_vect _VECTOR(13) /* Watchdog Time-out Interrupt */ +-#define TIMER1_CAPT_vect_num 14 +-#define TIMER1_CAPT_vect _VECTOR(14) /* Timer/Counter2 Capture Event */ +-#define TIMER1_COMPA_vect_num 15 +-#define TIMER1_COMPA_vect _VECTOR(15) /* Timer/Counter2 Compare Match B */ +-#define TIMER0_COMPA_vect_num 19 +-#define TIMER0_COMPA_vect _VECTOR(19) /* Timer/Counter0 Compare Match A */ +-#define TIMER0_COMPB_vect_num 20 +-#define TIMER0_COMPB_vect _VECTOR(20) /* Timer/Counter0 Compare Match B */ +-#define TIMER0_OVF_vect_num 21 +-#define TIMER0_OVF_vect _VECTOR(21) /* Timer/Counter0 Overflow */ +-#define SPI_STC_vect_num 22 +-#define SPI_STC_vect _VECTOR(22) /* SPI Serial Transfer Complete */ +-#define USART1_RX_vect_num 23 +-#define USART1_RX_vect _VECTOR(23) /* USART1, Rx Complete */ +-#define USART1_UDRE_vect_num 24 +-#define USART1_UDRE_vect _VECTOR(24) /* USART1 Data register Empty */ +-#define USART1_TX_vect_num 25 +-#define USART1_TX_vect _VECTOR(25) /* USART1, Tx Complete */ +-#define ANALOG_COMP_vect_num 26 +-#define ANALOG_COMP_vect _VECTOR(26) /* Analog Comparator */ +-#define EE_READY_vect_num 27 +-#define EE_READY_vect _VECTOR(27) /* EEPROM Ready */ +-#define SPM_READY_vect_num 28 +-#define SPM_READY_vect _VECTOR(28) /* Store Program Memory Read */ +-#define TIMER1_COMPB_vect_num 16 +-#define TIMER1_COMPB_vect _VECTOR(16) /* Timer/Counter2 Compare Match B */ +-#define TIMER1_COMPC_vect_num 17 +-#define TIMER1_COMPC_vect _VECTOR(17) /* Timer/Counter2 Compare Match C */ +-#define TIMER1_OVF_vect_num 18 +-#define TIMER1_OVF_vect _VECTOR(18) /* Timer/Counter1 Overflow */ +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (29 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (128) +-#define RAMSTART (0x100) +-#define RAMSIZE (1024) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x3FF) +-#define E2PAGESIZE (4) +-#define FLASHEND (0x7FFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(6) /* External Reset Disable */ +-#define FUSE_DWEN (unsigned char)~_BV(7) /* dwbugWIRE Enable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define FUSE_HWBE (unsigned char)~_BV(3) /* Hardware Boot Enable */ +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x95 +-#define SIGNATURE_2 0x8A +- +- +-/* Device Pin Definitions */ +-#endif /* _AVR_ATmega32U2_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom32u2.h 2240 2011-05-09 22:18:18Z arcanum $ */ ++ ++/* avr/iom32u2.h - definitions for ATmega32U2 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom32u2.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATmega32U2_H_ ++#define _AVR_ATmega32U2_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++#define PINC7 7 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++#define DDC7 7 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC4 4 ++#define PORTC5 5 ++#define PORTC6 6 ++#define PORTC7 7 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define OCF1C 3 ++#define ICF1 5 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++#define INTF4 4 ++#define INTF5 5 ++#define INTF6 6 ++#define INTF7 7 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++#define INT3 3 ++#define INT4 4 ++#define INT5 5 ++#define INT6 6 ++#define INT7 7 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++#define EEAR9 1 ++#define EEAR10 2 ++#define EEAR11 3 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define OCR0A _SFR_IO8(0x27) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define OCR0B _SFR_IO8(0x28) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define PLLCSR _SFR_IO8(0x29) ++#define PLOCK 0 ++#define PLLE 1 ++#define PLLP0 2 ++#define PLLP1 3 ++#define PLLP2 4 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define DWDR _SFR_IO8(0x31) ++#define DWDR0 0 ++#define DWDR1 1 ++#define DWDR2 2 ++#define DWDR3 3 ++#define DWDR4 4 ++#define DWDR5 5 ++#define DWDR6 6 ++#define DWDR7 7 ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define USBRF 5 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define EIND _SFR_IO8(0x3C) ++#define EIND0 0 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define WDTCKD _SFR_MEM8(0x62) ++#define WCLKD0 0 ++#define WCLKD1 1 ++#define WDEWIE 2 ++#define WDEWIF 3 ++ ++#define REGCR _SFR_MEM8(0x63) ++#define REGDIS 0 ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRTIM0 5 ++ ++#define PRR1 _SFR_MEM8(0x65) ++#define PRUSART1 0 ++#define PRUSB 7 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++#define EICRB _SFR_MEM8(0x6A) ++#define ISC40 0 ++#define ISC41 1 ++#define ISC50 2 ++#define ISC51 3 ++#define ISC60 4 ++#define ISC61 5 ++#define ISC70 6 ++#define ISC71 7 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define OCIE1C 3 ++#define ICIE1 5 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++#define AIN2D 2 ++#define AIN3D 3 ++#define AIN4D 4 ++#define AIN5D 5 ++#define AIN6D 6 ++#define AIN7D 7 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1C0 2 ++#define COM1C1 3 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1C 5 ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define OCR1C _SFR_MEM16(0x8C) ++ ++#define OCR1CL _SFR_MEM8(0x8C) ++#define OCR1CL0 0 ++#define OCR1CL1 1 ++#define OCR1CL2 2 ++#define OCR1CL3 3 ++#define OCR1CL4 4 ++#define OCR1CL5 5 ++#define OCR1CL6 6 ++#define OCR1CL7 7 ++ ++#define OCR1CH _SFR_MEM8(0x8D) ++#define OCR1CH0 0 ++#define OCR1CH1 1 ++#define OCR1CH2 2 ++#define OCR1CH3 3 ++#define OCR1CH4 4 ++#define OCR1CH5 5 ++#define OCR1CH6 6 ++#define OCR1CH7 7 ++ ++#define UCSR1A _SFR_MEM8(0xC8) ++#define MPCM1 0 ++#define U2X1 1 ++#define UPE1 2 ++#define DOR1 3 ++#define FE1 4 ++#define UDRE1 5 ++#define TXC1 6 ++#define RXC1 7 ++ ++#define UCSR1B _SFR_MEM8(0xC9) ++#define TXB81 0 ++#define RXB81 1 ++#define UCSZ12 2 ++#define TXEN1 3 ++#define RXEN1 4 ++#define UDRIE1 5 ++#define TXCIE1 6 ++#define RXCIE1 7 ++ ++#define UCSR1C _SFR_MEM8(0xCA) ++#define UCPOL1 0 ++#define UCSZ10 1 ++#define UCSZ11 2 ++#define USBS1 3 ++#define UPM10 4 ++#define UPM11 5 ++#define UMSEL10 6 ++#define UMSEL11 7 ++ ++#define UCSR1D _SFR_MEM8(0xCB) ++#define RTSEN 0 ++#define CTSEN 1 ++ ++#define UBRR1 _SFR_MEM16(0xCC) ++ ++#define UBRR1L _SFR_MEM8(0xCC) ++#define UBRR1_0 0 ++#define UBRR1_1 1 ++#define UBRR1_2 2 ++#define UBRR1_3 3 ++#define UBRR1_4 4 ++#define UBRR1_5 5 ++#define UBRR1_6 6 ++#define UBRR1_7 7 ++ ++#define UBRR1H _SFR_MEM8(0xCD) ++#define UBRR1_8 0 ++#define UBRR1_9 1 ++#define UBRR1_10 2 ++#define UBRR1_11 3 ++ ++#define UDR1 _SFR_MEM8(0xCE) ++#define UDR1_0 0 ++#define UDR1_1 1 ++#define UDR1_2 2 ++#define UDR1_3 3 ++#define UDR1_4 4 ++#define UDR1_5 5 ++#define UDR1_6 6 ++#define UDR1_7 7 ++ ++#define CLKSEL0 _SFR_MEM8(0xD0) ++#define CLKS 0 ++#define EXTE 2 ++#define RCE 3 ++#define EXSUT0 4 ++#define EXSUT1 5 ++#define RCSUT0 6 ++#define RCSUT1 7 ++ ++#define CLKSEL1 _SFR_MEM8(0xD1) ++#define EXCKSEL0 0 ++#define EXCKSEL1 1 ++#define EXCKSEL2 2 ++#define EXCKSEL3 3 ++#define RCCKSEL0 4 ++#define RCCKSEL1 5 ++#define RCCKSEL2 6 ++#define RCCKSEL3 7 ++ ++#define CLKSTA _SFR_MEM8(0xD2) ++#define EXTON 0 ++#define RCON 1 ++ ++#define USBCON _SFR_MEM8(0xD8) ++#define FRZCLK 5 ++#define USBE 7 ++ ++#define UDCON _SFR_MEM8(0xE0) ++#define DETACH 0 ++#define RMWKUP 1 ++#define RSTCPU 2 ++ ++#define UDINT _SFR_MEM8(0xE1) ++#define SUSPI 0 ++#define SOFI 2 ++#define EORSTI 3 ++#define WAKEUPI 4 ++#define EORSMI 5 ++#define UPRSMI 6 ++ ++#define UDIEN _SFR_MEM8(0xE2) ++#define SUSPE 0 ++#define SOFE 2 ++#define EORSTE 3 ++#define WAKEUPE 4 ++#define EORSME 5 ++#define UPRSME 6 ++ ++#define UDADDR _SFR_MEM8(0xE3) ++#define UADD0 0 ++#define UADD1 1 ++#define UADD2 2 ++#define UADD3 3 ++#define UADD4 4 ++#define UADD5 5 ++#define UADD6 6 ++#define ADDEN 7 ++ ++#define UDFNUM _SFR_MEM16(0xE4) ++ ++#define UDFNUML _SFR_MEM8(0xE4) ++#define FNUM0 0 ++#define FNUM1 1 ++#define FNUM2 2 ++#define FNUM3 3 ++#define FNUM4 4 ++#define FNUM5 5 ++#define FNUM6 6 ++#define FNUM7 7 ++ ++#define UDFNUMH _SFR_MEM8(0xE5) ++#define FNUM8 0 ++#define FNUM9 1 ++#define FNUM10 2 ++ ++#define UDMFN _SFR_MEM8(0xE6) ++#define FNCERR 4 ++ ++#define UEINTX _SFR_MEM8(0xE8) ++#define TXINI 0 ++#define STALLEDI 1 ++#define RXOUTI 2 ++#define RXSTPI 3 ++#define NAKOUTI 4 ++#define RWAL 5 ++#define NAKINI 6 ++#define FIFOCON 7 ++ ++#define UENUM _SFR_MEM8(0xE9) ++#define EPNUM0 0 ++#define EPNUM1 1 ++#define EPNUM2 2 ++ ++#define UERST _SFR_MEM8(0xEA) ++#define EPRST0 0 ++#define EPRST1 1 ++#define EPRST2 2 ++#define EPRST3 3 ++#define EPRST4 4 ++ ++#define UECONX _SFR_MEM8(0xEB) ++#define EPEN 0 ++#define RSTDT 3 ++#define STALLRQC 4 ++#define STALLRQ 5 ++ ++#define UECFG0X _SFR_MEM8(0xEC) ++#define EPDIR 0 ++#define EPTYPE0 6 ++#define EPTYPE1 7 ++ ++#define UECFG1X _SFR_MEM8(0xED) ++#define ALLOC 1 ++#define EPBK0 2 ++#define EPBK1 3 ++#define EPSIZE0 4 ++#define EPSIZE1 5 ++#define EPSIZE2 6 ++ ++#define UESTA0X _SFR_MEM8(0xEE) ++#define NBUSYBK0 0 ++#define NBUSYBK1 1 ++#define DTSEQ0 2 ++#define DTSEQ1 3 ++#define UNDERFI 5 ++#define OVERFI 6 ++#define CFGOK 7 ++ ++#define UESTA1X _SFR_MEM8(0xEF) ++#define CURRBK0 0 ++#define CURRBK1 1 ++#define CTRLDIR 2 ++ ++#define UEIENX _SFR_MEM8(0xF0) ++#define TXINE 0 ++#define STALLEDE 1 ++#define RXOUTE 2 ++#define RXSTPE 3 ++#define NAKOUTE 4 ++#define NAKINE 6 ++#define FLERRE 7 ++ ++#define UEDATX _SFR_MEM8(0xF1) ++#define DAT0 0 ++#define DAT1 1 ++#define DAT2 2 ++#define DAT3 3 ++#define DAT4 4 ++#define DAT5 5 ++#define DAT6 6 ++#define DAT7 7 ++ ++#define UEBCLX _SFR_MEM8(0xF2) ++#define BYCT0 0 ++#define BYCT1 1 ++#define BYCT2 2 ++#define BYCT3 3 ++#define BYCT4 4 ++#define BYCT5 5 ++#define BYCT6 6 ++#define BYCT7 7 ++ ++#define UEINT _SFR_MEM8(0xF4) ++#define EPINT0 0 ++#define EPINT1 1 ++#define EPINT2 2 ++#define EPINT3 3 ++#define EPINT4 4 ++ ++#define PS2CON _SFR_MEM8(0xFA) ++#define PS2EN 0 ++ ++#define UPOE _SFR_MEM8(0xFB) ++#define DMI 0 ++#define DPI 1 ++#define DATAI 2 ++#define SCKI 3 ++#define UPDRV0 4 ++#define UPDRV1 5 ++#define UPWE0 6 ++#define UPWE1 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ ++#define INT2_vect_num 3 ++#define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ ++#define INT3_vect_num 4 ++#define INT3_vect _VECTOR(4) /* External Interrupt Request 3 */ ++#define INT4_vect_num 5 ++#define INT4_vect _VECTOR(5) /* External Interrupt Request 4 */ ++#define INT5_vect_num 6 ++#define INT5_vect _VECTOR(6) /* External Interrupt Request 5 */ ++#define INT6_vect_num 7 ++#define INT6_vect _VECTOR(7) /* External Interrupt Request 6 */ ++#define INT7_vect_num 8 ++#define INT7_vect _VECTOR(8) /* External Interrupt Request 7 */ ++#define PCINT0_vect_num 9 ++#define PCINT0_vect _VECTOR(9) /* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect_num 10 ++#define PCINT1_vect _VECTOR(10) /* Pin Change Interrupt Request 1 */ ++#define USB_GEN_vect_num 11 ++#define USB_GEN_vect _VECTOR(11) /* USB General Interrupt Request */ ++#define USB_COM_vect_num 12 ++#define USB_COM_vect _VECTOR(12) /* USB Endpoint/Pipe Interrupt Communication Request */ ++#define WDT_vect_num 13 ++#define WDT_vect _VECTOR(13) /* Watchdog Time-out Interrupt */ ++#define TIMER1_CAPT_vect_num 14 ++#define TIMER1_CAPT_vect _VECTOR(14) /* Timer/Counter2 Capture Event */ ++#define TIMER1_COMPA_vect_num 15 ++#define TIMER1_COMPA_vect _VECTOR(15) /* Timer/Counter2 Compare Match B */ ++#define TIMER0_COMPA_vect_num 19 ++#define TIMER0_COMPA_vect _VECTOR(19) /* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPB_vect_num 20 ++#define TIMER0_COMPB_vect _VECTOR(20) /* Timer/Counter0 Compare Match B */ ++#define TIMER0_OVF_vect_num 21 ++#define TIMER0_OVF_vect _VECTOR(21) /* Timer/Counter0 Overflow */ ++#define SPI_STC_vect_num 22 ++#define SPI_STC_vect _VECTOR(22) /* SPI Serial Transfer Complete */ ++#define USART1_RX_vect_num 23 ++#define USART1_RX_vect _VECTOR(23) /* USART1, Rx Complete */ ++#define USART1_UDRE_vect_num 24 ++#define USART1_UDRE_vect _VECTOR(24) /* USART1 Data register Empty */ ++#define USART1_TX_vect_num 25 ++#define USART1_TX_vect _VECTOR(25) /* USART1, Tx Complete */ ++#define ANALOG_COMP_vect_num 26 ++#define ANALOG_COMP_vect _VECTOR(26) /* Analog Comparator */ ++#define EE_READY_vect_num 27 ++#define EE_READY_vect _VECTOR(27) /* EEPROM Ready */ ++#define SPM_READY_vect_num 28 ++#define SPM_READY_vect _VECTOR(28) /* Store Program Memory Read */ ++#define TIMER1_COMPB_vect_num 16 ++#define TIMER1_COMPB_vect _VECTOR(16) /* Timer/Counter2 Compare Match B */ ++#define TIMER1_COMPC_vect_num 17 ++#define TIMER1_COMPC_vect _VECTOR(17) /* Timer/Counter2 Compare Match C */ ++#define TIMER1_OVF_vect_num 18 ++#define TIMER1_OVF_vect _VECTOR(18) /* Timer/Counter1 Overflow */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (29 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (128) ++#define RAMSTART (0x100) ++#define RAMSIZE (1024) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x3FF) ++#define E2PAGESIZE (4) ++#define FLASHEND (0x7FFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(6) /* External Reset Disable */ ++#define FUSE_DWEN (unsigned char)~_BV(7) /* dwbugWIRE Enable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define FUSE_HWBE (unsigned char)~_BV(3) /* Hardware Boot Enable */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x8A ++ ++ ++/* Device Pin Definitions */ ++#endif /* _AVR_ATmega32U2_H_ */ ++ +diff --git a/include/avr/iom32u4.h b/include/avr/iom32u4.h +index b73ccd7..cb91703 100644 +--- a/include/avr/iom32u4.h ++++ b/include/avr/iom32u4.h +@@ -1,1579 +1,1533 @@ +-/* Copyright (c) 2008 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. +-*/ +- +-/* $Id: iom32u4.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* avr/iom32u4.h - definitions for ATmega32U4. */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom32u4.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_IOM32U4_H_ +-#define _AVR_IOM32U4_H_ 1 +- +- +-/* Registers and associated bit numbers */ +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC6 6 +-#define PINC7 7 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC6 6 +-#define DDC7 7 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC6 6 +-#define PORTC7 7 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define PINE _SFR_IO8(0x0C) +-#define PINE2 2 +-#define PINE6 6 +- +-#define DDRE _SFR_IO8(0x0D) +-#define DDE2 2 +-#define DDE6 6 +- +-#define PORTE _SFR_IO8(0x0E) +-#define PORTE2 2 +-#define PORTE6 6 +- +-#define PINF _SFR_IO8(0x0F) +-#define PINF0 0 +-#define PINF1 1 +-#define PINF4 4 +-#define PINF5 5 +-#define PINF6 6 +-#define PINF7 7 +- +-#define DDRF _SFR_IO8(0x10) +-#define DDF0 0 +-#define DDF1 1 +-#define DDF4 4 +-#define DDF5 5 +-#define DDF6 6 +-#define DDF7 7 +- +-#define PORTF _SFR_IO8(0x11) +-#define PORTF0 0 +-#define PORTF1 1 +-#define PORTF4 4 +-#define PORTF5 5 +-#define PORTF6 6 +-#define PORTF7 7 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define OCF1C 3 +-#define ICF1 5 +- +-#define TIFR2 _SFR_IO8(0x17) +-#define TOV2 0 +-#define OCF2A 1 +-#define OCF2B 2 +- +-#define TIFR3 _SFR_IO8(0x18) +-#define TOV3 0 +-#define OCF3A 1 +-#define OCF3B 2 +-#define OCF3C 3 +-#define ICF3 5 +- +-#define TIFR4 _SFR_IO8(0x19) +-#define TOV4 2 +-#define OCF4B 5 +-#define OCF4A 6 +-#define OCF4D 7 +- +-#define TIFR5 _SFR_IO8(0x1A) +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +-#define INTF2 2 +-#define INTF3 3 +-#define INTF4 4 +-#define INTF5 5 +-#define INTF6 6 +-#define INTF7 7 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +-#define INT2 2 +-#define INT3 3 +-#define INT4 4 +-#define INT5 5 +-#define INT6 6 +-#define INT7 7 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +-#define EEAR9 1 +-#define EEAR10 2 +-#define EEAR11 3 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSRSYNC 0 +-#define PSRASY 1 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define OCR0A _SFR_IO8(0x27) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define OCR0B _SFR_IO8(0x28) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define PLLCSR _SFR_IO8(0x29) +-#define PLOCK 0 +-#define PLLE 1 +-#define PINDIV 4 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define OCDR _SFR_IO8(0x31) +-#define OCDR0 0 +-#define OCDR1 1 +-#define OCDR2 2 +-#define OCDR3 3 +-#define OCDR4 4 +-#define OCDR5 5 +-#define OCDR6 6 +-#define OCDR7 7 +- +-#define PLLFRQ _SFR_IO8(0x32) +-#define PDIV0 0 +-#define PDIV1 1 +-#define PDIV2 2 +-#define PDIV3 3 +-#define PLLTM0 4 +-#define PLLTM1 5 +-#define PLLUSB 6 +-#define PINMUX 7 +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +-#define JTRF 4 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define JTD 7 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define SIGRD 5 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define RAMPZ _SFR_IO8(0x3B) +-#define RAMPZ0 0 +- +-#define EIND _SFR_IO8(0x3C) +-#define EIND0 0 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define PRR0 _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM1 3 +-#define PRTIM0 5 +-#define PRTIM2 6 +-#define PRTWI 7 +- +-#define PRR1 _SFR_MEM8(0x65) +-#define PRUSART1 0 +-#define PRTIM3 3 +-#define PRUSB 7 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define RCCTRL _SFR_MEM8(0x67) +-#define RCFREQ 0 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define ISC20 4 +-#define ISC21 5 +-#define ISC30 6 +-#define ISC31 7 +- +-#define EICRB _SFR_MEM8(0x6A) +-#define ISC40 0 +-#define ISC41 1 +-#define ISC50 2 +-#define ISC51 3 +-#define ISC60 4 +-#define ISC61 5 +-#define ISC70 6 +-#define ISC71 7 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +- +-#define PCMSK2 _SFR_MEM8(0x6D) +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define OCIE1C 3 +-#define ICIE1 5 +- +-#define TIMSK2 _SFR_MEM8(0x70) +-#define TOIE2 0 +-#define OCIE2A 1 +-#define OCIE2B 2 +- +-#define TIMSK3 _SFR_MEM8(0x71) +-#define TOIE3 0 +-#define OCIE3A 1 +-#define OCIE3B 2 +-#define OCIE3C 3 +-#define ICIE3 5 +- +-#define TIMSK4 _SFR_MEM8(0x72) +-#define TOIE4 2 +-#define OCIE4B 5 +-#define OCIE4A 6 +-#define OCIE4D 7 +- +-#define TIMSK5 _SFR_MEM8(0x73) +- +-#ifndef _ASSEMBLER_ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +- +-#define ADCL _SFR_MEM8(0x78) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_MEM8(0x79) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ADTS3 3 +-#define MUX5 5 +-#define ACME 6 +-#define ADHSM 7 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define DIDR2 _SFR_MEM8(0x7D) +-#define ADC8D 0 +-#define ADC9D 1 +-#define ADC10D 2 +-#define ADC11D 3 +-#define ADC12D 4 +-#define ADC13D 5 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1C0 2 +-#define COM1C1 3 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1C 5 +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define OCR1C _SFR_MEM16(0x8C) +- +-#define OCR1CL _SFR_MEM8(0x8C) +-#define OCR1CL0 0 +-#define OCR1CL1 1 +-#define OCR1CL2 2 +-#define OCR1CL3 3 +-#define OCR1CL4 4 +-#define OCR1CL5 5 +-#define OCR1CL6 6 +-#define OCR1CL7 7 +- +-#define OCR1CH _SFR_MEM8(0x8D) +-#define OCR1CH0 0 +-#define OCR1CH1 1 +-#define OCR1CH2 2 +-#define OCR1CH3 3 +-#define OCR1CH4 4 +-#define OCR1CH5 5 +-#define OCR1CH6 6 +-#define OCR1CH7 7 +- +-#define TCCR3A _SFR_MEM8(0x90) +-#define WGM30 0 +-#define WGM31 1 +-#define COM3C0 2 +-#define COM3C1 3 +-#define COM3B0 4 +-#define COM3B1 5 +-#define COM3A0 6 +-#define COM3A1 7 +- +-#define TCCR3B _SFR_MEM8(0x91) +-#define CS30 0 +-#define CS31 1 +-#define CS32 2 +-#define WGM32 3 +-#define WGM33 4 +-#define ICES3 6 +-#define ICNC3 7 +- +-#define TCCR3C _SFR_MEM8(0x92) +-#define FOC3C 5 +-#define FOC3B 6 +-#define FOC3A 7 +- +-#define TCNT3 _SFR_MEM16(0x94) +- +-#define TCNT3L _SFR_MEM8(0x94) +-#define TCNT3L0 0 +-#define TCNT3L1 1 +-#define TCNT3L2 2 +-#define TCNT3L3 3 +-#define TCNT3L4 4 +-#define TCNT3L5 5 +-#define TCNT3L6 6 +-#define TCNT3L7 7 +- +-#define TCNT3H _SFR_MEM8(0x95) +-#define TCNT3H0 0 +-#define TCNT3H1 1 +-#define TCNT3H2 2 +-#define TCNT3H3 3 +-#define TCNT3H4 4 +-#define TCNT3H5 5 +-#define TCNT3H6 6 +-#define TCNT3H7 7 +- +-#define ICR3 _SFR_MEM16(0x96) +- +-#define ICR3L _SFR_MEM8(0x96) +-#define ICR3L0 0 +-#define ICR3L1 1 +-#define ICR3L2 2 +-#define ICR3L3 3 +-#define ICR3L4 4 +-#define ICR3L5 5 +-#define ICR3L6 6 +-#define ICR3L7 7 +- +-#define ICR3H _SFR_MEM8(0x97) +-#define ICR3H0 0 +-#define ICR3H1 1 +-#define ICR3H2 2 +-#define ICR3H3 3 +-#define ICR3H4 4 +-#define ICR3H5 5 +-#define ICR3H6 6 +-#define ICR3H7 7 +- +-#define OCR3A _SFR_MEM16(0x98) +- +-#define OCR3AL _SFR_MEM8(0x98) +-#define OCR3AL0 0 +-#define OCR3AL1 1 +-#define OCR3AL2 2 +-#define OCR3AL3 3 +-#define OCR3AL4 4 +-#define OCR3AL5 5 +-#define OCR3AL6 6 +-#define OCR3AL7 7 +- +-#define OCR3AH _SFR_MEM8(0x99) +-#define OCR3AH0 0 +-#define OCR3AH1 1 +-#define OCR3AH2 2 +-#define OCR3AH3 3 +-#define OCR3AH4 4 +-#define OCR3AH5 5 +-#define OCR3AH6 6 +-#define OCR3AH7 7 +- +-#define OCR3B _SFR_MEM16(0x9A) +- +-#define OCR3BL _SFR_MEM8(0x9A) +-#define OCR3BL0 0 +-#define OCR3BL1 1 +-#define OCR3BL2 2 +-#define OCR3BL3 3 +-#define OCR3BL4 4 +-#define OCR3BL5 5 +-#define OCR3BL6 6 +-#define OCR3BL7 7 +- +-#define OCR3BH _SFR_MEM8(0x9B) +-#define OCR3BH0 0 +-#define OCR3BH1 1 +-#define OCR3BH2 2 +-#define OCR3BH3 3 +-#define OCR3BH4 4 +-#define OCR3BH5 5 +-#define OCR3BH6 6 +-#define OCR3BH7 7 +- +-#define OCR3C _SFR_MEM16(0x9C) +- +-#define OCR3CL _SFR_MEM8(0x9C) +-#define OCR3CL0 0 +-#define OCR3CL1 1 +-#define OCR3CL2 2 +-#define OCR3CL3 3 +-#define OCR3CL4 4 +-#define OCR3CL5 5 +-#define OCR3CL6 6 +-#define OCR3CL7 7 +- +-#define OCR3CH _SFR_MEM8(0x9D) +-#define OCR3CH0 0 +-#define OCR3CH1 1 +-#define OCR3CH2 2 +-#define OCR3CH3 3 +-#define OCR3CH4 4 +-#define OCR3CH5 5 +-#define OCR3CH6 6 +-#define OCR3CH7 7 +- +-#define UHCON _SFR_MEM8(0x9E) +- +-#define UHINT _SFR_MEM8(0x9F) +- +-#define UHIEN _SFR_MEM8(0xA0) +- +-#define UHADDR _SFR_MEM8(0xA1) +- +-#define UHFNUM _SFR_MEM16(0xA2) +- +-#define UHFNUML _SFR_MEM8(0xA2) +- +-#define UHFNUMH _SFR_MEM8(0xA3) +- +-#define UHFLEN _SFR_MEM8(0xA4) +- +-#define UPINRQX _SFR_MEM8(0xA5) +- +-#define UPINTX _SFR_MEM8(0xA6) +- +-#define UPNUM _SFR_MEM8(0xA7) +- +-#define UPRST _SFR_MEM8(0xA8) +- +-#define UPCONX _SFR_MEM8(0xA9) +- +-#define UPCFG0X _SFR_MEM8(0xAA) +- +-#define UPCFG1X _SFR_MEM8(0xAB) +- +-#define UPSTAX _SFR_MEM8(0xAC) +- +-#define UPCFG2X _SFR_MEM8(0xAD) +- +-#define UPIENX _SFR_MEM8(0xAE) +- +-#define UPDATX _SFR_MEM8(0xAF) +- +-#define TCCR2A _SFR_MEM8(0xB0) +-#define WGM20 0 +-#define WGM21 1 +-#define COM2B0 4 +-#define COM2B1 5 +-#define COM2A0 6 +-#define COM2A1 7 +- +-#define TCCR2B _SFR_MEM8(0xB1) +-#define CS20 0 +-#define CS21 1 +-#define CS22 2 +-#define WGM22 3 +-#define FOC2B 6 +-#define FOC2A 7 +- +-#define TCNT2 _SFR_MEM8(0xB2) +-#define TCNT2_0 0 +-#define TCNT2_1 1 +-#define TCNT2_2 2 +-#define TCNT2_3 3 +-#define TCNT2_4 4 +-#define TCNT2_5 5 +-#define TCNT2_6 6 +-#define TCNT2_7 7 +- +-#define OCR2A _SFR_MEM8(0xB3) +-#define OCR2_0 0 +-#define OCR2_1 1 +-#define OCR2_2 2 +-#define OCR2_3 3 +-#define OCR2_4 4 +-#define OCR2_5 5 +-#define OCR2_6 6 +-#define OCR2_7 7 +- +-#define OCR2B _SFR_MEM8(0xB4) +-#define OCR2_0 0 +-#define OCR2_1 1 +-#define OCR2_2 2 +-#define OCR2_3 3 +-#define OCR2_4 4 +-#define OCR2_5 5 +-#define OCR2_6 6 +-#define OCR2_7 7 +- +-#define TWBR _SFR_MEM8(0xB8) +-#define TWBR0 0 +-#define TWBR1 1 +-#define TWBR2 2 +-#define TWBR3 3 +-#define TWBR4 4 +-#define TWBR5 5 +-#define TWBR6 6 +-#define TWBR7 7 +- +-#define TWSR _SFR_MEM8(0xB9) +-#define TWPS0 0 +-#define TWPS1 1 +-#define TWS3 3 +-#define TWS4 4 +-#define TWS5 5 +-#define TWS6 6 +-#define TWS7 7 +- +-#define TWAR _SFR_MEM8(0xBA) +-#define TWGCE 0 +-#define TWA0 1 +-#define TWA1 2 +-#define TWA2 3 +-#define TWA3 4 +-#define TWA4 5 +-#define TWA5 6 +-#define TWA6 7 +- +-#define TWDR _SFR_MEM8(0xBB) +-#define TWD0 0 +-#define TWD1 1 +-#define TWD2 2 +-#define TWD3 3 +-#define TWD4 4 +-#define TWD5 5 +-#define TWD6 6 +-#define TWD7 7 +- +-#define TWCR _SFR_MEM8(0xBC) +-#define TWIE 0 +-#define TWEN 2 +-#define TWWC 3 +-#define TWSTO 4 +-#define TWSTA 5 +-#define TWEA 6 +-#define TWINT 7 +- +-#define TWAMR _SFR_MEM8(0xBD) +-#define TWAM0 1 +-#define TWAM1 2 +-#define TWAM2 3 +-#define TWAM3 4 +-#define TWAM4 5 +-#define TWAM5 6 +-#define TWAM6 7 +- +-#define TCNT4 _SFR_MEM16(0xBE) +- +-#define TCNT4L _SFR_MEM8(0xBE) +-#define TC40 0 +-#define TC41 1 +-#define TC42 2 +-#define TC43 3 +-#define TC44 4 +-#define TC45 5 +-#define TC46 6 +-#define TC47 7 +- +-#define TCNT4H _SFR_MEM8(0xBF) /* Alias for naming consistency. */ +-#define TC4H _SFR_MEM8(0xBF) /* Per XML device file. */ +-#define TC48 0 +-#define TC49 1 +-#define TC410 2 +- +-#define TCCR4A _SFR_MEM8(0xC0) +-#define PWM4B 0 +-#define PWM4A 1 +-#define FOC4B 2 +-#define FOC4A 3 +-#define COM4B0 4 +-#define COM4B1 5 +-#define COM4A0 6 +-#define COM4A1 7 +- +-#define TCCR4B _SFR_MEM8(0xC1) +-#define CS40 0 +-#define CS41 1 +-#define CS42 2 +-#define CS43 3 +-#define DTPS40 4 +-#define DTPS41 5 +-#define PSR4 6 +-#define PWM4X 7 +- +-#define TCCR4C _SFR_MEM8(0xC2) +-#define PWM4D 0 +-#define FOC4D 1 +-#define COM4D0 2 +-#define COM4D1 3 +-#define COM4B0S 4 +-#define COM4B1S 5 +-#define COM4A0S 6 +-#define COM4A1S 7 +- +-#define TCCR4D _SFR_MEM8(0xC3) +-#define WGM40 0 +-#define WGM41 1 +-#define FPF4 2 +-#define FPAC4 3 +-#define FPES4 4 +-#define FPNC4 5 +-#define FPEN4 6 +-#define FPIE4 7 +- +-#define TCCR4E _SFR_MEM8(0xC4) +-#define OC4OE0 0 +-#define OC4OE1 1 +-#define OC4OE2 2 +-#define OC4OE3 3 +-#define OC4OE4 4 +-#define OC4OE5 5 +-#define ENHC4 6 +-#define TLOCK4 7 +- +-#define CLKSEL0 _SFR_MEM8(0xC5) +-#define CLKS 0 +-#define EXTE 2 +-#define RCE 3 +-#define EXSUT0 4 +-#define EXSUT1 5 +-#define RCSUT0 6 +-#define RCSUT1 7 +- +-#define CLKSEL1 _SFR_MEM8(0xC6) +-#define EXCKSEL0 0 +-#define EXCKSEL1 1 +-#define EXCKSEL2 2 +-#define EXCKSEL3 3 +-#define RCCKSEL0 4 +-#define RCCKSEL1 5 +-#define RCCKSEL2 6 +-#define RCCKSEL3 7 +- +-#define CLKSTA _SFR_MEM8(0xC7) +-#define EXTON 0 +-#define RCON 1 +- +-#define UCSR1A _SFR_MEM8(0xC8) +-#define MPCM1 0 +-#define U2X1 1 +-#define UPE1 2 +-#define DOR1 3 +-#define FE1 4 +-#define UDRE1 5 +-#define TXC1 6 +-#define RXC1 7 +- +-#define UCSR1B _SFR_MEM8(0xC9) +-#define TXB81 0 +-#define RXB81 1 +-#define UCSZ12 2 +-#define TXEN1 3 +-#define RXEN1 4 +-#define UDRIE1 5 +-#define TXCIE1 6 +-#define RXCIE1 7 +- +-#define UCSR1C _SFR_MEM8(0xCA) +-#define UCPOL1 0 +-#define UCSZ10 1 +-#define UCSZ11 2 +-#define USBS1 3 +-#define UPM10 4 +-#define UPM11 5 +-#define UMSEL10 6 +-#define UMSEL11 7 +- +-#define UBRR1 _SFR_MEM16(0xCC) +- +-#define UBRR1L _SFR_MEM8(0xCC) +- +-#define UBRR1H _SFR_MEM8(0xCD) +- +-#define UDR1 _SFR_MEM8(0xCE) +-#define UDR1_0 0 +-#define UDR1_1 1 +-#define UDR1_2 2 +-#define UDR1_3 3 +-#define UDR1_4 4 +-#define UDR1_5 5 +-#define UDR1_6 6 +-#define UDR1_7 7 +- +-#define OCR4A _SFR_MEM8(0xCF) +-#define OCR4A0 0 +-#define OCR4A1 1 +-#define OCR4A2 2 +-#define OCR4A3 3 +-#define OCR4A4 4 +-#define OCR4A5 5 +-#define OCR4A6 6 +-#define OCR4A7 7 +- +-#define OCR4B _SFR_MEM8(0xD0) +-#define OCR4B0 0 +-#define OCR4B1 1 +-#define OCR4B2 2 +-#define OCR4B3 3 +-#define OCR4B4 4 +-#define OCR4B5 5 +-#define OCR4B6 6 +-#define OCR4B7 7 +- +-#define OCR4C _SFR_MEM8(0xD1) +-#define OCR4C0 0 +-#define OCR4C1 1 +-#define OCR4C2 2 +-#define OCR4C3 3 +-#define OCR4C4 4 +-#define OCR4C5 5 +-#define OCR4C6 6 +-#define OCR4C7 7 +- +-#define OCR4D _SFR_MEM8(0xD2) +-#define OCR4D0 0 +-#define OCR4D1 1 +-#define OCR4D2 2 +-#define OCR4D3 3 +-#define OCR4D4 4 +-#define OCR4D5 5 +-#define OCR4D6 6 +-#define OCR4D7 7 +- +-#define DT4 _SFR_MEM8(0xD4) +-#define DT4L0 0 +-#define DT4L1 1 +-#define DT4L2 2 +-#define DT4L3 3 +-#define DT4L4 4 +-#define DT4L5 5 +-#define DT4L6 6 +-#define DT4L7 7 +- +-#define UHWCON _SFR_MEM8(0xD7) +-#define UVREGE 0 +- +-#define USBCON _SFR_MEM8(0xD8) +-#define VBUSTE 0 +-#define OTGPADE 4 +-#define FRZCLK 5 +-#define USBE 7 +- +-#define USBSTA _SFR_MEM8(0xD9) +-#define VBUS 0 +-#define SPEED 3 +- +-#define USBINT _SFR_MEM8(0xDA) +-#define VBUSTI 0 +- +-#define OTGCON _SFR_MEM8(0xDD) +- +-#define OTGIEN _SFR_MEM8(0xDE) +- +-#define OTGINT _SFR_MEM8(0xDF) +- +-#define UDCON _SFR_MEM8(0xE0) +-#define DETACH 0 +-#define RMWKUP 1 +-#define LSM 2 +-#define RSTCPU 3 +- +-#define UDINT _SFR_MEM8(0xE1) +-#define SUSPI 0 +-#define SOFI 2 +-#define EORSTI 3 +-#define WAKEUPI 4 +-#define EORSMI 5 +-#define UPRSMI 6 +- +-#define UDIEN _SFR_MEM8(0xE2) +-#define SUSPE 0 +-#define SOFE 2 +-#define EORSTE 3 +-#define WAKEUPE 4 +-#define EORSME 5 +-#define UPRSME 6 +- +-#define UDADDR _SFR_MEM8(0xE3) +-#define UADD0 0 +-#define UADD1 1 +-#define UADD2 2 +-#define UADD3 3 +-#define UADD4 4 +-#define UADD5 5 +-#define UADD6 6 +-#define ADDEN 7 +- +-#define UDFNUM _SFR_MEM16(0xE4) +- +-#define UDFNUML _SFR_MEM8(0xE4) +-#define FNUM0 0 +-#define FNUM1 1 +-#define FNUM2 2 +-#define FNUM3 3 +-#define FNUM4 4 +-#define FNUM5 5 +-#define FNUM6 6 +-#define FNUM7 7 +- +-#define UDFNUMH _SFR_MEM8(0xE5) +-#define FNUM8 0 +-#define FNUM9 1 +-#define FNUM10 2 +- +-#define UDMFN _SFR_MEM8(0xE6) +-#define FNCERR 4 +- +-#define UDTST _SFR_MEM8(0xE7) +- +-#define UEINTX _SFR_MEM8(0xE8) +-#define TXINI 0 +-#define STALLEDI 1 +-#define RXOUTI 2 +-#define RXSTPI 3 +-#define NAKOUTI 4 +-#define RWAL 5 +-#define NAKINI 6 +-#define FIFOCON 7 +- +-#define UENUM _SFR_MEM8(0xE9) +-#define UENUM_0 0 +-#define UENUM_1 1 +-#define UENUM_2 2 +- +-#define UERST _SFR_MEM8(0xEA) +-#define EPRST0 0 +-#define EPRST1 1 +-#define EPRST2 2 +-#define EPRST3 3 +-#define EPRST4 4 +-#define EPRST5 5 +-#define EPRST6 6 +- +-#define UECONX _SFR_MEM8(0xEB) +-#define EPEN 0 +-#define RSTDT 3 +-#define STALLRQC 4 +-#define STALLRQ 5 +- +-#define UECFG0X _SFR_MEM8(0xEC) +-#define EPDIR 0 +-#define EPTYPE0 6 +-#define EPTYPE1 7 +- +-#define UECFG1X _SFR_MEM8(0xED) +-#define ALLOC 1 +-#define EPBK0 2 +-#define EPBK1 3 +-#define EPSIZE0 4 +-#define EPSIZE1 5 +-#define EPSIZE2 6 +- +-#define UESTA0X _SFR_MEM8(0xEE) +-#define NBUSYBK0 0 +-#define NBUSYBK1 1 +-#define DTSEQ0 2 +-#define DTSEQ1 3 +-#define UNDERFI 5 +-#define OVERFI 6 +-#define CFGOK 7 +- +-#define UESTA1X _SFR_MEM8(0xEF) +-#define CURRBK0 0 +-#define CURRBK1 1 +-#define CTRLDIR 2 +- +-#define UEIENX _SFR_MEM8(0xF0) +-#define TXINE 0 +-#define STALLEDE 1 +-#define RXOUTE 2 +-#define RXSTPE 3 +-#define NAKOUTE 4 +-#define NAKINE 6 +-#define FLERRE 7 +- +-#define UEDATX _SFR_MEM8(0xF1) +-#define DAT0 0 +-#define DAT1 1 +-#define DAT2 2 +-#define DAT3 3 +-#define DAT4 4 +-#define DAT5 5 +-#define DAT6 6 +-#define DAT7 7 +- +-#define UEBCX _SFR_MEM16(0xF2) +- +-#define UEBCLX _SFR_MEM8(0xF2) +-#define BYCT0 0 +-#define BYCT1 1 +-#define BYCT2 2 +-#define BYCT3 3 +-#define BYCT4 4 +-#define BYCT5 5 +-#define BYCT6 6 +-#define BYCT7 7 +- +-#define UEBCHX _SFR_MEM8(0xF3) +- +-#define UEINT _SFR_MEM8(0xF4) +-#define EPINT0 0 +-#define EPINT1 1 +-#define EPINT2 2 +-#define EPINT3 3 +-#define EPINT4 4 +-#define EPINT5 5 +-#define EPINT6 6 +- +-#define UPERRX _SFR_MEM8(0xF5) +- +-#define UPBCLX _SFR_MEM8(0xF6) +- +-#define UPBCHX _SFR_MEM8(0xF7) +- +-#define UPINT _SFR_MEM8(0xF8) +- +-#define OTGTCON _SFR_MEM8(0xF9) +- +- +- +-/* Interrupt Vectors */ +-/* Interrupt Vector 0 is the reset vector. */ +- +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +- +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ +- +-#define INT2_vect_num 3 +-#define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ +- +-#define INT3_vect_num 4 +-#define INT3_vect _VECTOR(4) /* External Interrupt Request 3 */ +- +-#define INT6_vect_num 7 +-#define INT6_vect _VECTOR(7) /* External Interrupt Request 6 */ +- +-#define PCINT0_vect_num 9 +-#define PCINT0_vect _VECTOR(9) /* Pin Change Interrupt Request 0 */ +- +-#define USB_GEN_vect_num 10 +-#define USB_GEN_vect _VECTOR(10) /* USB General Interrupt Request */ +- +-#define USB_COM_vect_num 11 +-#define USB_COM_vect _VECTOR(11) /* USB Endpoint/Pipe Interrupt Communication Request */ +- +-#define WDT_vect_num 12 +-#define WDT_vect _VECTOR(12) /* Watchdog Time-out Interrupt */ +- +-#define TIMER1_CAPT_vect_num 16 +-#define TIMER1_CAPT_vect _VECTOR(16) /* Timer/Counter1 Capture Event */ +- +-#define TIMER1_COMPA_vect_num 17 +-#define TIMER1_COMPA_vect _VECTOR(17) /* Timer/Counter1 Compare Match A */ +- +-#define TIMER1_COMPB_vect_num 18 +-#define TIMER1_COMPB_vect _VECTOR(18) /* Timer/Counter1 Compare Match B */ +- +-#define TIMER1_COMPC_vect_num 19 +-#define TIMER1_COMPC_vect _VECTOR(19) /* Timer/Counter1 Compare Match C */ +- +-#define TIMER1_OVF_vect_num 20 +-#define TIMER1_OVF_vect _VECTOR(20) /* Timer/Counter1 Overflow */ +- +-#define TIMER0_COMPA_vect_num 21 +-#define TIMER0_COMPA_vect _VECTOR(21) /* Timer/Counter0 Compare Match A */ +- +-#define TIMER0_COMPB_vect_num 22 +-#define TIMER0_COMPB_vect _VECTOR(22) /* Timer/Counter0 Compare Match B */ +- +-#define TIMER0_OVF_vect_num 23 +-#define TIMER0_OVF_vect _VECTOR(23) /* Timer/Counter0 Overflow */ +- +-#define SPI_STC_vect_num 24 +-#define SPI_STC_vect _VECTOR(24) /* SPI Serial Transfer Complete */ +- +-#define USART1_RX_vect_num 25 +-#define USART1_RX_vect _VECTOR(25) /* USART1, Rx Complete */ +- +-#define USART1_UDRE_vect_num 26 +-#define USART1_UDRE_vect _VECTOR(26) /* USART1 Data register Empty */ +- +-#define USART1_TX_vect_num 27 +-#define USART1_TX_vect _VECTOR(27) /* USART1, Tx Complete */ +- +-#define ANALOG_COMP_vect_num 28 +-#define ANALOG_COMP_vect _VECTOR(28) /* Analog Comparator */ +- +-#define ADC_vect_num 29 +-#define ADC_vect _VECTOR(29) /* ADC Conversion Complete */ +- +-#define EE_READY_vect_num 30 +-#define EE_READY_vect _VECTOR(30) /* EEPROM Ready */ +- +-#define TIMER3_CAPT_vect_num 31 +-#define TIMER3_CAPT_vect _VECTOR(31) /* Timer/Counter3 Capture Event */ +- +-#define TIMER3_COMPA_vect_num 32 +-#define TIMER3_COMPA_vect _VECTOR(32) /* Timer/Counter3 Compare Match A */ +- +-#define TIMER3_COMPB_vect_num 33 +-#define TIMER3_COMPB_vect _VECTOR(33) /* Timer/Counter3 Compare Match B */ +- +-#define TIMER3_COMPC_vect_num 34 +-#define TIMER3_COMPC_vect _VECTOR(34) /* Timer/Counter3 Compare Match C */ +- +-#define TIMER3_OVF_vect_num 35 +-#define TIMER3_OVF_vect _VECTOR(35) /* Timer/Counter3 Overflow */ +- +-#define TWI_vect_num 36 +-#define TWI_vect _VECTOR(36) /* 2-wire Serial Interface */ +- +-#define SPM_READY_vect_num 37 +-#define SPM_READY_vect _VECTOR(37) /* Store Program Memory Read */ +- +-#define TIMER4_COMPA_vect_num 38 +-#define TIMER4_COMPA_vect _VECTOR(38) /* Timer/Counter4 Compare Match A */ +- +-#define TIMER4_COMPB_vect_num 39 +-#define TIMER4_COMPB_vect _VECTOR(39) /* Timer/Counter4 Compare Match B */ +- +-#define TIMER4_COMPD_vect_num 40 +-#define TIMER4_COMPD_vect _VECTOR(40) /* Timer/Counter4 Compare Match D */ +- +-#define TIMER4_OVF_vect_num 41 +-#define TIMER4_OVF_vect _VECTOR(41) /* Timer/Counter4 Overflow */ +- +-#define TIMER4_FPF_vect_num 42 +-#define TIMER4_FPF_vect _VECTOR(42) /* Timer/Counter4 Fault Protection Interrupt */ +- +-#define _VECTORS_SIZE (43 * 4) +- +- +- +-/* Constants */ +-#define SPM_PAGESIZE (128) +-#define RAMSTART (0x100) +-#define RAMSIZE (0xA00) +-#define RAMEND (RAMSTART + RAMSIZE - 1) /* Last On-Chip SRAM Location */ +-#define XRAMSTART (0x2200) +-#define XRAMSIZE (0x10000) +-#define XRAMEND (XRAMSIZE - 1) +-#define E2END (0x3FF) +-#define E2PAGESIZE (4) +-#define FLASHEND (0x7FFF) +- +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT1 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ +-#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define FUSE_HWBE (unsigned char)~_BV(3) /* Hardware Boot Enable */ +-#define EFUSE_DEFAULT (0xFF) +- +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x95 +-#define SIGNATURE_2 0x87 +- +- +- +-#endif /* _AVR_IOM32U4_H_ */ ++/* Copyright (c) 2008 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++/* $Id: iom32u4.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* avr/iom32u4.h - definitions for ATmega32U4. */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom32u4.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_IOM32U4_H_ ++#define _AVR_IOM32U4_H_ 1 ++ ++ ++/* Registers and associated bit numbers */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC6 6 ++#define PINC7 7 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC6 6 ++#define DDC7 7 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC6 6 ++#define PORTC7 7 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE2 2 ++#define PINE6 6 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE2 2 ++#define DDE6 6 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE2 2 ++#define PORTE6 6 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF0 0 ++#define PINF1 1 ++#define PINF4 4 ++#define PINF5 5 ++#define PINF6 6 ++#define PINF7 7 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDF0 0 ++#define DDF1 1 ++#define DDF4 4 ++#define DDF5 5 ++#define DDF6 6 ++#define DDF7 7 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PORTF0 0 ++#define PORTF1 1 ++#define PORTF4 4 ++#define PORTF5 5 ++#define PORTF6 6 ++#define PORTF7 7 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define OCF1C 3 ++#define ICF1 5 ++ ++#define TIFR3 _SFR_IO8(0x18) ++#define TOV3 0 ++#define OCF3A 1 ++#define OCF3B 2 ++#define OCF3C 3 ++#define ICF3 5 ++ ++#define TIFR4 _SFR_IO8(0x19) ++#define TOV4 2 ++#define OCF4B 5 ++#define OCF4A 6 ++#define OCF4D 7 ++ ++#define TIFR5 _SFR_IO8(0x1A) ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++#define INTF4 4 ++#define INTF5 5 ++#define INTF6 6 ++#define INTF7 7 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++#define INT3 3 ++#define INT4 4 ++#define INT5 5 ++#define INT6 6 ++#define INT7 7 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++#define EEAR9 1 ++#define EEAR10 2 ++#define EEAR11 3 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define PSRASY 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define OCR0A _SFR_IO8(0x27) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define OCR0B _SFR_IO8(0x28) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define PLLCSR _SFR_IO8(0x29) ++#define PLOCK 0 ++#define PLLE 1 ++#define PINDIV 4 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCDR7 7 ++ ++#define PLLFRQ _SFR_IO8(0x32) ++#define PDIV0 0 ++#define PDIV1 1 ++#define PDIV2 2 ++#define PDIV3 3 ++#define PLLTM0 4 ++#define PLLTM1 5 ++#define PLLUSB 6 ++#define PINMUX 7 ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define JTRF 4 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define JTD 7 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define RAMPZ _SFR_IO8(0x3B) ++#define RAMPZ0 0 ++ ++#define EIND _SFR_IO8(0x3C) ++#define EIND0 0 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++#define PRR1 _SFR_MEM8(0x65) ++#define PRUSART1 0 ++#define PRTIM3 3 ++#define PRUSB 7 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define RCCTRL _SFR_MEM8(0x67) ++#define RCFREQ 0 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++#define EICRB _SFR_MEM8(0x6A) ++#define ISC40 0 ++#define ISC41 1 ++#define ISC50 2 ++#define ISC51 3 ++#define ISC60 4 ++#define ISC61 5 ++#define ISC70 6 ++#define ISC71 7 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define OCIE1C 3 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++#define TIMSK3 _SFR_MEM8(0x71) ++#define TOIE3 0 ++#define OCIE3A 1 ++#define OCIE3B 2 ++#define OCIE3C 3 ++#define ICIE3 5 ++ ++#define TIMSK4 _SFR_MEM8(0x72) ++#define TOIE4 2 ++#define OCIE4B 5 ++#define OCIE4A 6 ++#define OCIE4D 7 ++ ++#define TIMSK5 _SFR_MEM8(0x73) ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_MEM8(0x79) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ADTS3 3 ++#define MUX5 5 ++#define ACME 6 ++#define ADHSM 7 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR2 _SFR_MEM8(0x7D) ++#define ADC8D 0 ++#define ADC9D 1 ++#define ADC10D 2 ++#define ADC11D 3 ++#define ADC12D 4 ++#define ADC13D 5 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1C0 2 ++#define COM1C1 3 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1C 5 ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define OCR1C _SFR_MEM16(0x8C) ++ ++#define OCR1CL _SFR_MEM8(0x8C) ++#define OCR1CL0 0 ++#define OCR1CL1 1 ++#define OCR1CL2 2 ++#define OCR1CL3 3 ++#define OCR1CL4 4 ++#define OCR1CL5 5 ++#define OCR1CL6 6 ++#define OCR1CL7 7 ++ ++#define OCR1CH _SFR_MEM8(0x8D) ++#define OCR1CH0 0 ++#define OCR1CH1 1 ++#define OCR1CH2 2 ++#define OCR1CH3 3 ++#define OCR1CH4 4 ++#define OCR1CH5 5 ++#define OCR1CH6 6 ++#define OCR1CH7 7 ++ ++#define TCCR3A _SFR_MEM8(0x90) ++#define WGM30 0 ++#define WGM31 1 ++#define COM3C0 2 ++#define COM3C1 3 ++#define COM3B0 4 ++#define COM3B1 5 ++#define COM3A0 6 ++#define COM3A1 7 ++ ++#define TCCR3B _SFR_MEM8(0x91) ++#define CS30 0 ++#define CS31 1 ++#define CS32 2 ++#define WGM32 3 ++#define WGM33 4 ++#define ICES3 6 ++#define ICNC3 7 ++ ++#define TCCR3C _SFR_MEM8(0x92) ++#define FOC3C 5 ++#define FOC3B 6 ++#define FOC3A 7 ++ ++#define TCNT3 _SFR_MEM16(0x94) ++ ++#define TCNT3L _SFR_MEM8(0x94) ++#define TCNT3L0 0 ++#define TCNT3L1 1 ++#define TCNT3L2 2 ++#define TCNT3L3 3 ++#define TCNT3L4 4 ++#define TCNT3L5 5 ++#define TCNT3L6 6 ++#define TCNT3L7 7 ++ ++#define TCNT3H _SFR_MEM8(0x95) ++#define TCNT3H0 0 ++#define TCNT3H1 1 ++#define TCNT3H2 2 ++#define TCNT3H3 3 ++#define TCNT3H4 4 ++#define TCNT3H5 5 ++#define TCNT3H6 6 ++#define TCNT3H7 7 ++ ++#define ICR3 _SFR_MEM16(0x96) ++ ++#define ICR3L _SFR_MEM8(0x96) ++#define ICR3L0 0 ++#define ICR3L1 1 ++#define ICR3L2 2 ++#define ICR3L3 3 ++#define ICR3L4 4 ++#define ICR3L5 5 ++#define ICR3L6 6 ++#define ICR3L7 7 ++ ++#define ICR3H _SFR_MEM8(0x97) ++#define ICR3H0 0 ++#define ICR3H1 1 ++#define ICR3H2 2 ++#define ICR3H3 3 ++#define ICR3H4 4 ++#define ICR3H5 5 ++#define ICR3H6 6 ++#define ICR3H7 7 ++ ++#define OCR3A _SFR_MEM16(0x98) ++ ++#define OCR3AL _SFR_MEM8(0x98) ++#define OCR3AL0 0 ++#define OCR3AL1 1 ++#define OCR3AL2 2 ++#define OCR3AL3 3 ++#define OCR3AL4 4 ++#define OCR3AL5 5 ++#define OCR3AL6 6 ++#define OCR3AL7 7 ++ ++#define OCR3AH _SFR_MEM8(0x99) ++#define OCR3AH0 0 ++#define OCR3AH1 1 ++#define OCR3AH2 2 ++#define OCR3AH3 3 ++#define OCR3AH4 4 ++#define OCR3AH5 5 ++#define OCR3AH6 6 ++#define OCR3AH7 7 ++ ++#define OCR3B _SFR_MEM16(0x9A) ++ ++#define OCR3BL _SFR_MEM8(0x9A) ++#define OCR3BL0 0 ++#define OCR3BL1 1 ++#define OCR3BL2 2 ++#define OCR3BL3 3 ++#define OCR3BL4 4 ++#define OCR3BL5 5 ++#define OCR3BL6 6 ++#define OCR3BL7 7 ++ ++#define OCR3BH _SFR_MEM8(0x9B) ++#define OCR3BH0 0 ++#define OCR3BH1 1 ++#define OCR3BH2 2 ++#define OCR3BH3 3 ++#define OCR3BH4 4 ++#define OCR3BH5 5 ++#define OCR3BH6 6 ++#define OCR3BH7 7 ++ ++#define OCR3C _SFR_MEM16(0x9C) ++ ++#define OCR3CL _SFR_MEM8(0x9C) ++#define OCR3CL0 0 ++#define OCR3CL1 1 ++#define OCR3CL2 2 ++#define OCR3CL3 3 ++#define OCR3CL4 4 ++#define OCR3CL5 5 ++#define OCR3CL6 6 ++#define OCR3CL7 7 ++ ++#define OCR3CH _SFR_MEM8(0x9D) ++#define OCR3CH0 0 ++#define OCR3CH1 1 ++#define OCR3CH2 2 ++#define OCR3CH3 3 ++#define OCR3CH4 4 ++#define OCR3CH5 5 ++#define OCR3CH6 6 ++#define OCR3CH7 7 ++ ++#define UHCON _SFR_MEM8(0x9E) ++ ++#define UHINT _SFR_MEM8(0x9F) ++ ++#define UHIEN _SFR_MEM8(0xA0) ++ ++#define UHADDR _SFR_MEM8(0xA1) ++ ++#define UHFNUM _SFR_MEM16(0xA2) ++ ++#define UHFNUML _SFR_MEM8(0xA2) ++ ++#define UHFNUMH _SFR_MEM8(0xA3) ++ ++#define UHFLEN _SFR_MEM8(0xA4) ++ ++#define UPINRQX _SFR_MEM8(0xA5) ++ ++#define UPINTX _SFR_MEM8(0xA6) ++ ++#define UPNUM _SFR_MEM8(0xA7) ++ ++#define UPRST _SFR_MEM8(0xA8) ++ ++#define UPCONX _SFR_MEM8(0xA9) ++ ++#define UPCFG0X _SFR_MEM8(0xAA) ++ ++#define UPCFG1X _SFR_MEM8(0xAB) ++ ++#define UPSTAX _SFR_MEM8(0xAC) ++ ++#define UPCFG2X _SFR_MEM8(0xAD) ++ ++#define UPIENX _SFR_MEM8(0xAE) ++ ++#define UPDATX _SFR_MEM8(0xAF) ++ ++ ++#define TWBR _SFR_MEM8(0xB8) ++#define TWBR0 0 ++#define TWBR1 1 ++#define TWBR2 2 ++#define TWBR3 3 ++#define TWBR4 4 ++#define TWBR5 5 ++#define TWBR6 6 ++#define TWBR7 7 ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++#define TWD0 0 ++#define TWD1 1 ++#define TWD2 2 ++#define TWD3 3 ++#define TWD4 4 ++#define TWD5 5 ++#define TWD6 6 ++#define TWD7 7 ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++#define TCNT4 _SFR_MEM16(0xBE) ++ ++#define TCNT4L _SFR_MEM8(0xBE) ++#define TC40 0 ++#define TC41 1 ++#define TC42 2 ++#define TC43 3 ++#define TC44 4 ++#define TC45 5 ++#define TC46 6 ++#define TC47 7 ++ ++#define TCNT4H _SFR_MEM8(0xBF) /* Alias for naming consistency. */ ++#define TC4H _SFR_MEM8(0xBF) /* Per XML device file. */ ++#define TC48 0 ++#define TC49 1 ++#define TC410 2 ++ ++#define TCCR4A _SFR_MEM8(0xC0) ++#define PWM4B 0 ++#define PWM4A 1 ++#define FOC4B 2 ++#define FOC4A 3 ++#define COM4B0 4 ++#define COM4B1 5 ++#define COM4A0 6 ++#define COM4A1 7 ++ ++#define TCCR4B _SFR_MEM8(0xC1) ++#define CS40 0 ++#define CS41 1 ++#define CS42 2 ++#define CS43 3 ++#define DTPS40 4 ++#define DTPS41 5 ++#define PSR4 6 ++#define PWM4X 7 ++ ++#define TCCR4C _SFR_MEM8(0xC2) ++#define PWM4D 0 ++#define FOC4D 1 ++#define COM4D0 2 ++#define COM4D1 3 ++#define COM4B0S 4 ++#define COM4B1S 5 ++#define COM4A0S 6 ++#define COM4A1S 7 ++ ++#define TCCR4D _SFR_MEM8(0xC3) ++#define WGM40 0 ++#define WGM41 1 ++#define FPF4 2 ++#define FPAC4 3 ++#define FPES4 4 ++#define FPNC4 5 ++#define FPEN4 6 ++#define FPIE4 7 ++ ++#define TCCR4E _SFR_MEM8(0xC4) ++#define OC4OE0 0 ++#define OC4OE1 1 ++#define OC4OE2 2 ++#define OC4OE3 3 ++#define OC4OE4 4 ++#define OC4OE5 5 ++#define ENHC4 6 ++#define TLOCK4 7 ++ ++#define CLKSEL0 _SFR_MEM8(0xC5) ++#define CLKS 0 ++#define EXTE 2 ++#define RCE 3 ++#define EXSUT0 4 ++#define EXSUT1 5 ++#define RCSUT0 6 ++#define RCSUT1 7 ++ ++#define CLKSEL1 _SFR_MEM8(0xC6) ++#define EXCKSEL0 0 ++#define EXCKSEL1 1 ++#define EXCKSEL2 2 ++#define EXCKSEL3 3 ++#define RCCKSEL0 4 ++#define RCCKSEL1 5 ++#define RCCKSEL2 6 ++#define RCCKSEL3 7 ++ ++#define CLKSTA _SFR_MEM8(0xC7) ++#define EXTON 0 ++#define RCON 1 ++ ++#define UCSR1A _SFR_MEM8(0xC8) ++#define MPCM1 0 ++#define U2X1 1 ++#define UPE1 2 ++#define DOR1 3 ++#define FE1 4 ++#define UDRE1 5 ++#define TXC1 6 ++#define RXC1 7 ++ ++#define UCSR1B _SFR_MEM8(0xC9) ++#define TXB81 0 ++#define RXB81 1 ++#define UCSZ12 2 ++#define TXEN1 3 ++#define RXEN1 4 ++#define UDRIE1 5 ++#define TXCIE1 6 ++#define RXCIE1 7 ++ ++#define UCSR1C _SFR_MEM8(0xCA) ++#define UCPOL1 0 ++#define UCSZ10 1 ++#define UCSZ11 2 ++#define USBS1 3 ++#define UPM10 4 ++#define UPM11 5 ++#define UMSEL10 6 ++#define UMSEL11 7 ++ ++#define UCSR1D _SFR_MEM8(0xCB) ++#define RTSEN 0 ++#define CTSEN 1 ++ ++#define UBRR1 _SFR_MEM16(0xCC) ++ ++#define UBRR1L _SFR_MEM8(0xCC) ++ ++#define UBRR1H _SFR_MEM8(0xCD) ++ ++#define UDR1 _SFR_MEM8(0xCE) ++#define UDR1_0 0 ++#define UDR1_1 1 ++#define UDR1_2 2 ++#define UDR1_3 3 ++#define UDR1_4 4 ++#define UDR1_5 5 ++#define UDR1_6 6 ++#define UDR1_7 7 ++ ++#define OCR4A _SFR_MEM8(0xCF) ++#define OCR4A0 0 ++#define OCR4A1 1 ++#define OCR4A2 2 ++#define OCR4A3 3 ++#define OCR4A4 4 ++#define OCR4A5 5 ++#define OCR4A6 6 ++#define OCR4A7 7 ++ ++#define OCR4B _SFR_MEM8(0xD0) ++#define OCR4B0 0 ++#define OCR4B1 1 ++#define OCR4B2 2 ++#define OCR4B3 3 ++#define OCR4B4 4 ++#define OCR4B5 5 ++#define OCR4B6 6 ++#define OCR4B7 7 ++ ++#define OCR4C _SFR_MEM8(0xD1) ++#define OCR4C0 0 ++#define OCR4C1 1 ++#define OCR4C2 2 ++#define OCR4C3 3 ++#define OCR4C4 4 ++#define OCR4C5 5 ++#define OCR4C6 6 ++#define OCR4C7 7 ++ ++#define OCR4D _SFR_MEM8(0xD2) ++#define OCR4D0 0 ++#define OCR4D1 1 ++#define OCR4D2 2 ++#define OCR4D3 3 ++#define OCR4D4 4 ++#define OCR4D5 5 ++#define OCR4D6 6 ++#define OCR4D7 7 ++ ++#define DT4 _SFR_MEM8(0xD4) ++#define DT4L0 0 ++#define DT4L1 1 ++#define DT4L2 2 ++#define DT4L3 3 ++#define DT4L4 4 ++#define DT4L5 5 ++#define DT4L6 6 ++#define DT4L7 7 ++ ++#define UHWCON _SFR_MEM8(0xD7) ++#define UVREGE 0 ++ ++#define USBCON _SFR_MEM8(0xD8) ++#define VBUSTE 0 ++#define OTGPADE 4 ++#define FRZCLK 5 ++#define USBE 7 ++ ++#define USBSTA _SFR_MEM8(0xD9) ++#define VBUS 0 ++#define SPEED 3 ++ ++#define USBINT _SFR_MEM8(0xDA) ++#define VBUSTI 0 ++ ++#define OTGCON _SFR_MEM8(0xDD) ++ ++#define OTGIEN _SFR_MEM8(0xDE) ++ ++#define OTGINT _SFR_MEM8(0xDF) ++ ++#define UDCON _SFR_MEM8(0xE0) ++#define DETACH 0 ++#define RMWKUP 1 ++#define LSM 2 ++#define RSTCPU 3 ++ ++#define UDINT _SFR_MEM8(0xE1) ++#define SUSPI 0 ++#define SOFI 2 ++#define EORSTI 3 ++#define WAKEUPI 4 ++#define EORSMI 5 ++#define UPRSMI 6 ++ ++#define UDIEN _SFR_MEM8(0xE2) ++#define SUSPE 0 ++#define SOFE 2 ++#define EORSTE 3 ++#define WAKEUPE 4 ++#define EORSME 5 ++#define UPRSME 6 ++ ++#define UDADDR _SFR_MEM8(0xE3) ++#define UADD0 0 ++#define UADD1 1 ++#define UADD2 2 ++#define UADD3 3 ++#define UADD4 4 ++#define UADD5 5 ++#define UADD6 6 ++#define ADDEN 7 ++ ++#define UDFNUM _SFR_MEM16(0xE4) ++ ++#define UDFNUML _SFR_MEM8(0xE4) ++#define FNUM0 0 ++#define FNUM1 1 ++#define FNUM2 2 ++#define FNUM3 3 ++#define FNUM4 4 ++#define FNUM5 5 ++#define FNUM6 6 ++#define FNUM7 7 ++ ++#define UDFNUMH _SFR_MEM8(0xE5) ++#define FNUM8 0 ++#define FNUM9 1 ++#define FNUM10 2 ++ ++#define UDMFN _SFR_MEM8(0xE6) ++#define FNCERR 4 ++ ++#define UDTST _SFR_MEM8(0xE7) ++ ++#define UEINTX _SFR_MEM8(0xE8) ++#define TXINI 0 ++#define STALLEDI 1 ++#define RXOUTI 2 ++#define RXSTPI 3 ++#define NAKOUTI 4 ++#define RWAL 5 ++#define NAKINI 6 ++#define FIFOCON 7 ++ ++#define UENUM _SFR_MEM8(0xE9) ++#define UENUM_0 0 ++#define UENUM_1 1 ++#define UENUM_2 2 ++ ++#define UERST _SFR_MEM8(0xEA) ++#define EPRST0 0 ++#define EPRST1 1 ++#define EPRST2 2 ++#define EPRST3 3 ++#define EPRST4 4 ++#define EPRST5 5 ++#define EPRST6 6 ++ ++#define UECONX _SFR_MEM8(0xEB) ++#define EPEN 0 ++#define RSTDT 3 ++#define STALLRQC 4 ++#define STALLRQ 5 ++ ++#define UECFG0X _SFR_MEM8(0xEC) ++#define EPDIR 0 ++#define EPTYPE0 6 ++#define EPTYPE1 7 ++ ++#define UECFG1X _SFR_MEM8(0xED) ++#define ALLOC 1 ++#define EPBK0 2 ++#define EPBK1 3 ++#define EPSIZE0 4 ++#define EPSIZE1 5 ++#define EPSIZE2 6 ++ ++#define UESTA0X _SFR_MEM8(0xEE) ++#define NBUSYBK0 0 ++#define NBUSYBK1 1 ++#define DTSEQ0 2 ++#define DTSEQ1 3 ++#define UNDERFI 5 ++#define OVERFI 6 ++#define CFGOK 7 ++ ++#define UESTA1X _SFR_MEM8(0xEF) ++#define CURRBK0 0 ++#define CURRBK1 1 ++#define CTRLDIR 2 ++ ++#define UEIENX _SFR_MEM8(0xF0) ++#define TXINE 0 ++#define STALLEDE 1 ++#define RXOUTE 2 ++#define RXSTPE 3 ++#define NAKOUTE 4 ++#define NAKINE 6 ++#define FLERRE 7 ++ ++#define UEDATX _SFR_MEM8(0xF1) ++#define DAT0 0 ++#define DAT1 1 ++#define DAT2 2 ++#define DAT3 3 ++#define DAT4 4 ++#define DAT5 5 ++#define DAT6 6 ++#define DAT7 7 ++ ++#define UEBCX _SFR_MEM16(0xF2) ++ ++#define UEBCLX _SFR_MEM8(0xF2) ++#define BYCT0 0 ++#define BYCT1 1 ++#define BYCT2 2 ++#define BYCT3 3 ++#define BYCT4 4 ++#define BYCT5 5 ++#define BYCT6 6 ++#define BYCT7 7 ++ ++#define UEBCHX _SFR_MEM8(0xF3) ++ ++#define UEINT _SFR_MEM8(0xF4) ++#define EPINT0 0 ++#define EPINT1 1 ++#define EPINT2 2 ++#define EPINT3 3 ++#define EPINT4 4 ++#define EPINT5 5 ++#define EPINT6 6 ++ ++#define UPERRX _SFR_MEM8(0xF5) ++ ++#define UPBCLX _SFR_MEM8(0xF6) ++ ++#define UPBCHX _SFR_MEM8(0xF7) ++ ++#define UPINT _SFR_MEM8(0xF8) ++ ++#define OTGTCON _SFR_MEM8(0xF9) ++ ++ ++ ++/* Interrupt Vectors */ ++/* Interrupt Vector 0 is the reset vector. */ ++ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ ++ ++#define INT2_vect_num 3 ++#define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ ++ ++#define INT3_vect_num 4 ++#define INT3_vect _VECTOR(4) /* External Interrupt Request 3 */ ++ ++#define INT6_vect_num 7 ++#define INT6_vect _VECTOR(7) /* External Interrupt Request 6 */ ++ ++#define PCINT0_vect_num 9 ++#define PCINT0_vect _VECTOR(9) /* Pin Change Interrupt Request 0 */ ++ ++#define USB_GEN_vect_num 10 ++#define USB_GEN_vect _VECTOR(10) /* USB General Interrupt Request */ ++ ++#define USB_COM_vect_num 11 ++#define USB_COM_vect _VECTOR(11) /* USB Endpoint/Pipe Interrupt Communication Request */ ++ ++#define WDT_vect_num 12 ++#define WDT_vect _VECTOR(12) /* Watchdog Time-out Interrupt */ ++ ++#define TIMER1_CAPT_vect_num 16 ++#define TIMER1_CAPT_vect _VECTOR(16) /* Timer/Counter1 Capture Event */ ++ ++#define TIMER1_COMPA_vect_num 17 ++#define TIMER1_COMPA_vect _VECTOR(17) /* Timer/Counter1 Compare Match A */ ++ ++#define TIMER1_COMPB_vect_num 18 ++#define TIMER1_COMPB_vect _VECTOR(18) /* Timer/Counter1 Compare Match B */ ++ ++#define TIMER1_COMPC_vect_num 19 ++#define TIMER1_COMPC_vect _VECTOR(19) /* Timer/Counter1 Compare Match C */ ++ ++#define TIMER1_OVF_vect_num 20 ++#define TIMER1_OVF_vect _VECTOR(20) /* Timer/Counter1 Overflow */ ++ ++#define TIMER0_COMPA_vect_num 21 ++#define TIMER0_COMPA_vect _VECTOR(21) /* Timer/Counter0 Compare Match A */ ++ ++#define TIMER0_COMPB_vect_num 22 ++#define TIMER0_COMPB_vect _VECTOR(22) /* Timer/Counter0 Compare Match B */ ++ ++#define TIMER0_OVF_vect_num 23 ++#define TIMER0_OVF_vect _VECTOR(23) /* Timer/Counter0 Overflow */ ++ ++#define SPI_STC_vect_num 24 ++#define SPI_STC_vect _VECTOR(24) /* SPI Serial Transfer Complete */ ++ ++#define USART1_RX_vect_num 25 ++#define USART1_RX_vect _VECTOR(25) /* USART1, Rx Complete */ ++ ++#define USART1_UDRE_vect_num 26 ++#define USART1_UDRE_vect _VECTOR(26) /* USART1 Data register Empty */ ++ ++#define USART1_TX_vect_num 27 ++#define USART1_TX_vect _VECTOR(27) /* USART1, Tx Complete */ ++ ++#define ANALOG_COMP_vect_num 28 ++#define ANALOG_COMP_vect _VECTOR(28) /* Analog Comparator */ ++ ++#define ADC_vect_num 29 ++#define ADC_vect _VECTOR(29) /* ADC Conversion Complete */ ++ ++#define EE_READY_vect_num 30 ++#define EE_READY_vect _VECTOR(30) /* EEPROM Ready */ ++ ++#define TIMER3_CAPT_vect_num 31 ++#define TIMER3_CAPT_vect _VECTOR(31) /* Timer/Counter3 Capture Event */ ++ ++#define TIMER3_COMPA_vect_num 32 ++#define TIMER3_COMPA_vect _VECTOR(32) /* Timer/Counter3 Compare Match A */ ++ ++#define TIMER3_COMPB_vect_num 33 ++#define TIMER3_COMPB_vect _VECTOR(33) /* Timer/Counter3 Compare Match B */ ++ ++#define TIMER3_COMPC_vect_num 34 ++#define TIMER3_COMPC_vect _VECTOR(34) /* Timer/Counter3 Compare Match C */ ++ ++#define TIMER3_OVF_vect_num 35 ++#define TIMER3_OVF_vect _VECTOR(35) /* Timer/Counter3 Overflow */ ++ ++#define TWI_vect_num 36 ++#define TWI_vect _VECTOR(36) /* 2-wire Serial Interface */ ++ ++#define SPM_READY_vect_num 37 ++#define SPM_READY_vect _VECTOR(37) /* Store Program Memory Read */ ++ ++#define TIMER4_COMPA_vect_num 38 ++#define TIMER4_COMPA_vect _VECTOR(38) /* Timer/Counter4 Compare Match A */ ++ ++#define TIMER4_COMPB_vect_num 39 ++#define TIMER4_COMPB_vect _VECTOR(39) /* Timer/Counter4 Compare Match B */ ++ ++#define TIMER4_COMPD_vect_num 40 ++#define TIMER4_COMPD_vect _VECTOR(40) /* Timer/Counter4 Compare Match D */ ++ ++#define TIMER4_OVF_vect_num 41 ++#define TIMER4_OVF_vect _VECTOR(41) /* Timer/Counter4 Overflow */ ++ ++#define TIMER4_FPF_vect_num 42 ++#define TIMER4_FPF_vect _VECTOR(42) /* Timer/Counter4 Fault Protection Interrupt */ ++ ++#define _VECTORS_SIZE (43 * 4) ++ ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (128) ++#define RAMSTART (0x100) ++#define RAMSIZE (0xA00) ++#define RAMEND (RAMSTART + RAMSIZE - 1) /* Last On-Chip SRAM Location */ ++#define XRAMSTART (0x2200) ++#define XRAMSIZE (0x10000) ++#define XRAMEND (XRAMSIZE - 1) ++#define E2END (0x3FF) ++#define E2PAGESIZE (4) ++#define FLASHEND (0x7FFF) ++ ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT1 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ ++#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define FUSE_HWBE (unsigned char)~_BV(3) /* Hardware Boot Enable */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x87 ++ ++ ++ ++#endif /* _AVR_IOM32U4_H_ */ +diff --git a/include/avr/iom32u6.h b/include/avr/iom32u6.h +index 9d5785b..98d9777 100644 +--- a/include/avr/iom32u6.h ++++ b/include/avr/iom32u6.h +@@ -1,1411 +1,1411 @@ +-/* Copyright (c) 2008 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom32u6.h 1873 2009-02-11 17:53:39Z arcanum $ */ +- +-/* avr/iom32u6.h - definitions for ATmega32U6 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom32u6.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATmega32U6_H_ +-#define _AVR_ATmega32U6_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +-#define PINA4 4 +-#define PINA5 5 +-#define PINA6 6 +-#define PINA7 7 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +-#define DDA4 4 +-#define DDA5 5 +-#define DDA6 6 +-#define DDA7 7 +- +-#define PORTA _SFR_IO8(0x02) +-#define PORTA0 0 +-#define PORTA1 1 +-#define PORTA2 2 +-#define PORTA3 3 +-#define PORTA4 4 +-#define PORTA5 5 +-#define PORTA6 6 +-#define PORTA7 7 +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +-#define PINC7 7 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC3 3 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +-#define DDC7 7 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC3 3 +-#define PORTC4 4 +-#define PORTC5 5 +-#define PORTC6 6 +-#define PORTC7 7 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define PINE _SFR_IO8(0x0C) +-#define PINE0 0 +-#define PINE1 1 +-#define PINE2 2 +-#define PINE3 3 +-#define PINE4 4 +-#define PINE5 5 +-#define PINE6 6 +-#define PINE7 7 +- +-#define DDRE _SFR_IO8(0x0D) +-#define DDE0 0 +-#define DDE1 1 +-#define DDE2 2 +-#define DDE3 3 +-#define DDE4 4 +-#define DDE5 5 +-#define DDE6 6 +-#define DDE7 7 +- +-#define PORTE _SFR_IO8(0x0E) +-#define PORTE0 0 +-#define PORTE1 1 +-#define PORTE2 2 +-#define PORTE3 3 +-#define PORTE4 4 +-#define PORTE5 5 +-#define PORTE6 6 +-#define PORTE7 7 +- +-#define PINF _SFR_IO8(0x0F) +-#define PINF0 0 +-#define PINF1 1 +-#define PINF2 2 +-#define PINF3 3 +-#define PINF4 4 +-#define PINF5 5 +-#define PINF6 6 +-#define PINF7 7 +- +-#define DDRF _SFR_IO8(0x10) +-#define DDF0 0 +-#define DDF1 1 +-#define DDF2 2 +-#define DDF3 3 +-#define DDF4 4 +-#define DDF5 5 +-#define DDF6 6 +-#define DDF7 7 +- +-#define PORTF _SFR_IO8(0x11) +-#define PORTF0 0 +-#define PORTF1 1 +-#define PORTF2 2 +-#define PORTF3 3 +-#define PORTF4 4 +-#define PORTF5 5 +-#define PORTF6 6 +-#define PORTF7 7 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define OCF1C 3 +-#define ICF1 5 +- +-#define TIFR2 _SFR_IO8(0x17) +-#define TOV2 0 +-#define OCF2A 1 +-#define OCF2B 2 +- +-#define TIFR3 _SFR_IO8(0x18) +-#define TOV3 0 +-#define OCF3A 1 +-#define OCF3B 2 +-#define OCF3C 3 +-#define ICF3 5 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +-#define INTF2 2 +-#define INTF3 3 +-#define INTF4 4 +-#define INTF5 5 +-#define INTF6 6 +-#define INTF7 7 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +-#define INT2 2 +-#define INT3 3 +-#define INT4 4 +-#define INT5 5 +-#define INT6 6 +-#define INT7 7 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +-#define EEAR9 1 +-#define EEAR10 2 +-#define EEAR11 3 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSRSYNC 0 +-#define PSRASY 1 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define OCR0A _SFR_IO8(0x27) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define OCR0B _SFR_IO8(0x28) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define PLLCSR _SFR_IO8(0x29) +-#define PLOCK 0 +-#define PLLE 1 +-#define PLLP0 2 +-#define PLLP1 3 +-#define PLLP2 4 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define OCDR _SFR_IO8(0x31) +-#define OCDR0 0 +-#define OCDR1 1 +-#define OCDR2 2 +-#define OCDR3 3 +-#define OCDR4 4 +-#define OCDR5 5 +-#define OCDR6 6 +-#define OCDR7 7 +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +-#define JTRF 4 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define JTD 7 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define SIGRD 5 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define PRR0 _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRSPI 2 +-#define PRTIM1 3 +-#define PRTIM0 5 +-#define PRTIM2 6 +-#define PRTWI 7 +- +-#define PRR1 _SFR_MEM8(0x65) +-#define PRUSART1 0 +-#define PRTIM3 3 +-#define PRUSB 7 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define ISC20 4 +-#define ISC21 5 +-#define ISC30 6 +-#define ISC31 7 +- +-#define EICRB _SFR_MEM8(0x6A) +-#define ISC40 0 +-#define ISC41 1 +-#define ISC50 2 +-#define ISC51 3 +-#define ISC60 4 +-#define ISC61 5 +-#define ISC70 6 +-#define ISC71 7 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define OCIE1C 3 +-#define ICIE1 5 +- +-#define TIMSK2 _SFR_MEM8(0x70) +-#define TOIE2 0 +-#define OCIE2A 1 +-#define OCIE2B 2 +- +-#define TIMSK3 _SFR_MEM8(0x71) +-#define TOIE3 0 +-#define OCIE3A 1 +-#define OCIE3B 2 +-#define OCIE3C 3 +-#define ICIE3 5 +- +-#define XMCRA _SFR_MEM8(0x74) +-#define SRW00 0 +-#define SRW01 1 +-#define SRW10 2 +-#define SRW11 3 +-#define SRL0 4 +-#define SRL1 5 +-#define SRL2 6 +-#define SRE 7 +- +-#define XMCRB _SFR_MEM8(0x75) +-#define XMM0 0 +-#define XMM1 1 +-#define XMM2 2 +-#define XMBK 7 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +- +-#define ADCL _SFR_MEM8(0x78) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_MEM8(0x79) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ACME 6 +-#define ADHSM 7 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1C0 2 +-#define COM1C1 3 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1C 5 +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define OCR1C _SFR_MEM16(0x8C) +- +-#define OCR1CL _SFR_MEM8(0x8C) +-#define OCR1CL0 0 +-#define OCR1CL1 1 +-#define OCR1CL2 2 +-#define OCR1CL3 3 +-#define OCR1CL4 4 +-#define OCR1CL5 5 +-#define OCR1CL6 6 +-#define OCR1CL7 7 +- +-#define OCR1CH _SFR_MEM8(0x8D) +-#define OCR1CH0 0 +-#define OCR1CH1 1 +-#define OCR1CH2 2 +-#define OCR1CH3 3 +-#define OCR1CH4 4 +-#define OCR1CH5 5 +-#define OCR1CH6 6 +-#define OCR1CH7 7 +- +-#define TCCR3A _SFR_MEM8(0x90) +-#define WGM30 0 +-#define WGM31 1 +-#define COM3C0 2 +-#define COM3C1 3 +-#define COM3B0 4 +-#define COM3B1 5 +-#define COM3A0 6 +-#define COM3A1 7 +- +-#define TCCR3B _SFR_MEM8(0x91) +-#define CS30 0 +-#define CS31 1 +-#define CS32 2 +-#define WGM32 3 +-#define WGM33 4 +-#define ICES3 6 +-#define ICNC3 7 +- +-#define TCCR3C _SFR_MEM8(0x92) +-#define FOC3C 5 +-#define FOC3B 6 +-#define FOC3A 7 +- +-#define TCNT3 _SFR_MEM16(0x94) +- +-#define TCNT3L _SFR_MEM8(0x94) +-#define TCNT3L0 0 +-#define TCNT3L1 1 +-#define TCNT3L2 2 +-#define TCNT3L3 3 +-#define TCNT3L4 4 +-#define TCNT3L5 5 +-#define TCNT3L6 6 +-#define TCNT3L7 7 +- +-#define TCNT3H _SFR_MEM8(0x95) +-#define TCNT3H0 0 +-#define TCNT3H1 1 +-#define TCNT3H2 2 +-#define TCNT3H3 3 +-#define TCNT3H4 4 +-#define TCNT3H5 5 +-#define TCNT3H6 6 +-#define TCNT3H7 7 +- +-#define ICR3 _SFR_MEM16(0x96) +- +-#define ICR3L _SFR_MEM8(0x96) +-#define ICR3L0 0 +-#define ICR3L1 1 +-#define ICR3L2 2 +-#define ICR3L3 3 +-#define ICR3L4 4 +-#define ICR3L5 5 +-#define ICR3L6 6 +-#define ICR3L7 7 +- +-#define ICR3H _SFR_MEM8(0x97) +-#define ICR3H0 0 +-#define ICR3H1 1 +-#define ICR3H2 2 +-#define ICR3H3 3 +-#define ICR3H4 4 +-#define ICR3H5 5 +-#define ICR3H6 6 +-#define ICR3H7 7 +- +-#define OCR3A _SFR_MEM16(0x98) +- +-#define OCR3AL _SFR_MEM8(0x98) +-#define OCR3AL0 0 +-#define OCR3AL1 1 +-#define OCR3AL2 2 +-#define OCR3AL3 3 +-#define OCR3AL4 4 +-#define OCR3AL5 5 +-#define OCR3AL6 6 +-#define OCR3AL7 7 +- +-#define OCR3AH _SFR_MEM8(0x99) +-#define OCR3AH0 0 +-#define OCR3AH1 1 +-#define OCR3AH2 2 +-#define OCR3AH3 3 +-#define OCR3AH4 4 +-#define OCR3AH5 5 +-#define OCR3AH6 6 +-#define OCR3AH7 7 +- +-#define OCR3B _SFR_MEM16(0x9A) +- +-#define OCR3BL _SFR_MEM8(0x9A) +-#define OCR3BL0 0 +-#define OCR3BL1 1 +-#define OCR3BL2 2 +-#define OCR3BL3 3 +-#define OCR3BL4 4 +-#define OCR3BL5 5 +-#define OCR3BL6 6 +-#define OCR3BL7 7 +- +-#define OCR3BH _SFR_MEM8(0x9B) +-#define OCR3BH0 0 +-#define OCR3BH1 1 +-#define OCR3BH2 2 +-#define OCR3BH3 3 +-#define OCR3BH4 4 +-#define OCR3BH5 5 +-#define OCR3BH6 6 +-#define OCR3BH7 7 +- +-#define OCR3C _SFR_MEM16(0x9C) +- +-#define OCR3CL _SFR_MEM8(0x9C) +-#define OCR3CL0 0 +-#define OCR3CL1 1 +-#define OCR3CL2 2 +-#define OCR3CL3 3 +-#define OCR3CL4 4 +-#define OCR3CL5 5 +-#define OCR3CL6 6 +-#define OCR3CL7 7 +- +-#define OCR3CH _SFR_MEM8(0x9D) +-#define OCR3CH0 0 +-#define OCR3CH1 1 +-#define OCR3CH2 2 +-#define OCR3CH3 3 +-#define OCR3CH4 4 +-#define OCR3CH5 5 +-#define OCR3CH6 6 +-#define OCR3CH7 7 +- +-#define TCCR2A _SFR_MEM8(0xB0) +-#define WGM20 0 +-#define WGM21 1 +-#define COM2B0 4 +-#define COM2B1 5 +-#define COM2A0 6 +-#define COM2A1 7 +- +-#define TCCR2B _SFR_MEM8(0xB1) +-#define CS20 0 +-#define CS21 1 +-#define CS22 2 +-#define WGM22 3 +-#define FOC2B 6 +-#define FOC2A 7 +- +-#define TCNT2 _SFR_MEM8(0xB2) +-#define TCNT2_0 0 +-#define TCNT2_1 1 +-#define TCNT2_2 2 +-#define TCNT2_3 3 +-#define TCNT2_4 4 +-#define TCNT2_5 5 +-#define TCNT2_6 6 +-#define TCNT2_7 7 +- +-#define OCR2A _SFR_MEM8(0xB3) +-#define OCR2A_0 0 +-#define OCR2A_1 1 +-#define OCR2A_2 2 +-#define OCR2A_3 3 +-#define OCR2A_4 4 +-#define OCR2A_5 5 +-#define OCR2A_6 6 +-#define OCR2A_7 7 +- +-#define OCR2B _SFR_MEM8(0xB4) +-#define OCR2B_0 0 +-#define OCR2B_1 1 +-#define OCR2B_2 2 +-#define OCR2B_3 3 +-#define OCR2B_4 4 +-#define OCR2B_5 5 +-#define OCR2B_6 6 +-#define OCR2B_7 7 +- +-#define ASSR _SFR_MEM8(0xB6) +-#define TCR2BUB 0 +-#define TCR2AUB 1 +-#define OCR2BUB 2 +-#define OCR2AUB 3 +-#define TCN2UB 4 +-#define AS2 5 +-#define EXCLK 6 +- +-#define TWBR _SFR_MEM8(0xB8) +-#define TWBR0 0 +-#define TWBR1 1 +-#define TWBR2 2 +-#define TWBR3 3 +-#define TWBR4 4 +-#define TWBR5 5 +-#define TWBR6 6 +-#define TWBR7 7 +- +-#define TWSR _SFR_MEM8(0xB9) +-#define TWPS0 0 +-#define TWPS1 1 +-#define TWS3 3 +-#define TWS4 4 +-#define TWS5 5 +-#define TWS6 6 +-#define TWS7 7 +- +-#define TWAR _SFR_MEM8(0xBA) +-#define TWGCE 0 +-#define TWA0 1 +-#define TWA1 2 +-#define TWA2 3 +-#define TWA3 4 +-#define TWA4 5 +-#define TWA5 6 +-#define TWA6 7 +- +-#define TWDR _SFR_MEM8(0xBB) +-#define TWD0 0 +-#define TWD1 1 +-#define TWD2 2 +-#define TWD3 3 +-#define TWD4 4 +-#define TWD5 5 +-#define TWD6 6 +-#define TWD7 7 +- +-#define TWCR _SFR_MEM8(0xBC) +-#define TWIE 0 +-#define TWEN 2 +-#define TWWC 3 +-#define TWSTO 4 +-#define TWSTA 5 +-#define TWEA 6 +-#define TWINT 7 +- +-#define TWAMR _SFR_MEM8(0xBD) +-#define TWAM0 1 +-#define TWAM1 2 +-#define TWAM2 3 +-#define TWAM3 4 +-#define TWAM4 5 +-#define TWAM5 6 +-#define TWAM6 7 +- +-#define UCSR1A _SFR_MEM8(0xC8) +-#define MPCM1 0 +-#define U2X1 1 +-#define UPE1 2 +-#define DOR1 3 +-#define FE1 4 +-#define UDRE1 5 +-#define TXC1 6 +-#define RXC1 7 +- +-#define UCSR1B _SFR_MEM8(0xC9) +-#define TXB81 0 +-#define RXB81 1 +-#define UCSZ12 2 +-#define TXEN1 3 +-#define RXEN1 4 +-#define UDRIE1 5 +-#define TXCIE1 6 +-#define RXCIE1 7 +- +-#define UCSR1C _SFR_MEM8(0xCA) +-#define UCPOL1 0 +-#define UCSZ10 1 +-#define UCSZ11 2 +-#define USBS1 3 +-#define UPM10 4 +-#define UPM11 5 +-#define UMSEL10 6 +-#define UMSEL11 7 +- +-#define UBRR1 _SFR_MEM16(0xCC) +- +-#define UBRR1L _SFR_MEM8(0xCC) +-#define UBRR_0 0 +-#define UBRR_1 1 +-#define UBRR_2 2 +-#define UBRR_3 3 +-#define UBRR_4 4 +-#define UBRR_5 5 +-#define UBRR_6 6 +-#define UBRR_7 7 +- +-#define UBRR1H _SFR_MEM8(0xCD) +-#define UBRR_8 0 +-#define UBRR_9 1 +-#define UBRR_10 2 +-#define UBRR_11 3 +- +-#define UDR1 _SFR_MEM8(0xCE) +-#define UDR1_0 0 +-#define UDR1_1 1 +-#define UDR1_2 2 +-#define UDR1_3 3 +-#define UDR1_4 4 +-#define UDR1_5 5 +-#define UDR1_6 6 +-#define UDR1_7 7 +- +-#define UHWCON _SFR_MEM8(0xD7) +-#define UVREGE 0 +-#define UVCONE 4 +-#define UIDE 6 +-#define UIMOD 7 +- +-#define USBCON _SFR_MEM8(0xD8) +-#define VBUSTE 0 +-#define IDTE 1 +-#define OTGPADE 4 +-#define FRZCLK 5 +-#define HOST 6 +-#define USBE 7 +- +-#define USBSTA _SFR_MEM8(0xD9) +-#define VBUS 0 +-#define ID 1 +-#define SPEED 3 +- +-#define USBINT _SFR_MEM8(0xDA) +-#define VBUSTI 0 +-#define IDTI 1 +- +-#define UDCON _SFR_MEM8(0xE0) +-#define DETACH 0 +-#define RMWKUP 1 +-#define LSM 2 +- +-#define UDINT _SFR_MEM8(0xE1) +-#define SUSPI 0 +-#define SOFI 2 +-#define EORSTI 3 +-#define WAKEUPI 4 +-#define EORSMI 5 +-#define UPRSMI 6 +- +-#define UDIEN _SFR_MEM8(0xE2) +-#define SUSPE 0 +-#define SOFE 2 +-#define EORSTE 3 +-#define WAKEUPE 4 +-#define EORSME 5 +-#define UPRSME 6 +- +-#define UDADDR _SFR_MEM8(0xE3) +-#define UADD0 0 +-#define UADD1 1 +-#define UADD2 2 +-#define UADD3 3 +-#define UADD4 4 +-#define UADD5 5 +-#define UADD6 6 +-#define ADDEN 7 +- +-#define UDFNUM _SFR_MEM16(0xE4) +- +-#define UDFNUML _SFR_MEM8(0xE4) +-#define UDFNUML_0 0 +-#define UDFNUML_1 1 +-#define UDFNUML_2 2 +-#define UDFNUML_3 3 +-#define UDFNUML_4 4 +-#define UDFNUML_5 5 +-#define UDFNUML_6 6 +-#define UDFNUML_7 7 +- +-#define UDFNUMH _SFR_MEM8(0xE5) +-#define UDFNUMH_0 0 +-#define UDFNUMH_1 1 +-#define UDFNUMH_2 2 +- +-#define UDMFN _SFR_MEM8(0xE6) +-#define FNCERR 4 +- +-#define UEINTX _SFR_MEM8(0xE8) +-#define TXINI 0 +-#define STALLEDI 1 +-#define RXOUTI 2 +-#define RXSTPI 3 +-#define NAKOUTI 4 +-#define RWAL 5 +-#define NAKINI 6 +-#define FIFOCON 7 +- +-#define UENUM _SFR_MEM8(0xE9) +-#define UENUM_0 0 +-#define UENUM_1 1 +-#define UENUM_2 2 +- +-#define UERST _SFR_MEM8(0xEA) +-#define EPRST0 0 +-#define EPRST1 1 +-#define EPRST2 2 +-#define EPRST3 3 +-#define EPRST4 4 +-#define EPRST5 5 +-#define EPRST6 6 +- +-#define UECONX _SFR_MEM8(0xEB) +-#define EPEN 0 +-#define RSTDT 3 +-#define STALLRQC 4 +-#define STALLRQ 5 +- +-#define UECFG0X _SFR_MEM8(0xEC) +-#define EPDIR 0 +-#define EPTYPE0 6 +-#define EPTYPE1 7 +- +-#define UECFG1X _SFR_MEM8(0xED) +-#define ALLOC 1 +-#define EPBK0 2 +-#define EPBK1 3 +-#define EPSIZE0 4 +-#define EPSIZE1 5 +-#define EPSIZE2 6 +- +-#define UESTA0X _SFR_MEM8(0xEE) +-#define NBUSYBK0 0 +-#define NBUSYBK1 1 +-#define DTSEQ0 2 +-#define DTSEQ1 3 +-#define UNDERFI 5 +-#define OVERFI 6 +-#define CFGOK 7 +- +-#define UESTA1X _SFR_MEM8(0xEF) +-#define CURRBK0 0 +-#define CURRBK1 1 +-#define CTRLDIR 2 +- +-#define UEIENX _SFR_MEM8(0xF0) +-#define TXINE 0 +-#define STALLEDE 1 +-#define RXOUTE 2 +-#define RXSTPE 3 +-#define NAKOUTE 4 +-#define NAKINE 6 +-#define FLERRE 7 +- +-#define UEDATX _SFR_MEM8(0xF1) +-#define UEDATX_0 0 +-#define UEDATX_1 1 +-#define UEDATX_2 2 +-#define UEDATX_3 3 +-#define UEDATX_4 4 +-#define UEDATX_5 5 +-#define UEDATX_6 6 +-#define UEDATX_7 7 +- +-#define UEBCLX _SFR_MEM8(0xF2) +-#define UEBCLX_0 0 +-#define UEBCLX_1 1 +-#define UEBCLX_2 2 +-#define UEBCLX_3 3 +-#define UEBCLX_4 4 +-#define UEBCLX_5 5 +-#define UEBCLX_6 6 +-#define UEBCLX_7 7 +- +-#define UEBCHX _SFR_MEM8(0xF3) +-#define UEBCHX_0 0 +-#define UEBCHX_1 1 +-#define UEBCHX_2 2 +- +-#define UEINT _SFR_MEM8(0xF4) +-#define EPINT0 0 +-#define EPINT1 1 +-#define EPINT2 2 +-#define EPINT3 3 +-#define EPINT4 4 +-#define EPINT5 5 +-#define EPINT6 6 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ +-#define INT2_vect_num 3 +-#define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ +-#define INT3_vect_num 4 +-#define INT3_vect _VECTOR(4) /* External Interrupt Request 3 */ +-#define INT4_vect_num 5 +-#define INT4_vect _VECTOR(5) /* External Interrupt Request 4 */ +-#define INT5_vect_num 6 +-#define INT5_vect _VECTOR(6) /* External Interrupt Request 5 */ +-#define INT6_vect_num 7 +-#define INT6_vect _VECTOR(7) /* External Interrupt Request 6 */ +-#define INT7_vect_num 8 +-#define INT7_vect _VECTOR(8) /* External Interrupt Request 7 */ +-#define PCINT0_vect_num 9 +-#define PCINT0_vect _VECTOR(9) /* Pin Change Interrupt Request 0 */ +-#define USB_GEN_vect_num 10 +-#define USB_GEN_vect _VECTOR(10) /* USB General Interrupt Request */ +-#define USB_COM_vect_num 11 +-#define USB_COM_vect _VECTOR(11) /* USB Endpoint/Pipe Interrupt Communication Request */ +-#define WDT_vect_num 12 +-#define WDT_vect _VECTOR(12) /* Watchdog Time-out Interrupt */ +-#define TIMER2_COMPA_vect_num 13 +-#define TIMER2_COMPA_vect _VECTOR(13) /* Timer/Counter2 Compare Match A */ +-#define TIMER2_COMPB_vect_num 14 +-#define TIMER2_COMPB_vect _VECTOR(14) /* Timer/Counter2 Compare Match B */ +-#define TIMER2_OVF_vect_num 15 +-#define TIMER2_OVF_vect _VECTOR(15) /* Timer/Counter2 Overflow */ +-#define TIMER1_CAPT_vect_num 16 +-#define TIMER1_CAPT_vect _VECTOR(16) /* Timer/Counter1 Capture Event */ +-#define TIMER1_COMPA_vect_num 17 +-#define TIMER1_COMPA_vect _VECTOR(17) /* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPB_vect_num 18 +-#define TIMER1_COMPB_vect _VECTOR(18) /* Timer/Counter1 Compare Match B */ +-#define TIMER1_COMPC_vect_num 19 +-#define TIMER1_COMPC_vect _VECTOR(19) /* Timer/Counter1 Compare Match C */ +-#define TIMER1_OVF_vect_num 20 +-#define TIMER1_OVF_vect _VECTOR(20) /* Timer/Counter1 Overflow */ +-#define TIMER0_COMPA_vect_num 21 +-#define TIMER0_COMPA_vect _VECTOR(21) /* Timer/Counter0 Compare Match A */ +-#define TIMER0_COMPB_vect_num 22 +-#define TIMER0_COMPB_vect _VECTOR(22) /* Timer/Counter0 Compare Match B */ +-#define TIMER0_OVF_vect_num 23 +-#define TIMER0_OVF_vect _VECTOR(23) /* Timer/Counter0 Overflow */ +-#define SPI_STC_vect_num 24 +-#define SPI_STC_vect _VECTOR(24) /* SPI Serial Transfer Complete */ +-#define USART1_RX_vect_num 25 +-#define USART1_RX_vect _VECTOR(25) /* USART1, Rx Complete */ +-#define USART1_UDRE_vect_num 26 +-#define USART1_UDRE_vect _VECTOR(26) /* USART1 Data register Empty */ +-#define USART1_TX_vect_num 27 +-#define USART1_TX_vect _VECTOR(27) /* USART1, Tx Complete */ +-#define ANALOG_COMP_vect_num 28 +-#define ANALOG_COMP_vect _VECTOR(28) /* Analog Comparator */ +-#define ADC_vect_num 29 +-#define ADC_vect _VECTOR(29) /* ADC Conversion Complete */ +-#define EE_READY_vect_num 30 +-#define EE_READY_vect _VECTOR(30) /* EEPROM Ready */ +-#define TIMER3_CAPT_vect_num 31 +-#define TIMER3_CAPT_vect _VECTOR(31) /* Timer/Counter3 Capture Event */ +-#define TIMER3_COMPA_vect_num 32 +-#define TIMER3_COMPA_vect _VECTOR(32) /* Timer/Counter3 Compare Match A */ +-#define TIMER3_COMPB_vect_num 33 +-#define TIMER3_COMPB_vect _VECTOR(33) /* Timer/Counter3 Compare Match B */ +-#define TIMER3_COMPC_vect_num 34 +-#define TIMER3_COMPC_vect _VECTOR(34) /* Timer/Counter3 Compare Match C */ +-#define TIMER3_OVF_vect_num 35 +-#define TIMER3_OVF_vect _VECTOR(35) /* Timer/Counter3 Overflow */ +-#define TWI_vect_num 36 +-#define TWI_vect _VECTOR(36) /* 2-wire Serial Interface */ +-#define SPM_READY_vect_num 37 +-#define SPM_READY_vect _VECTOR(37) /* Store Program Memory Read */ +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (38 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (128) +-#define RAMSTART (0x100) +-#define RAMSIZE (2560) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (0x2200) +-#define XRAMSIZE (65536) +-#define XRAMEND (XRAMSIZE - 1) +-#define E2END (0x3FF) +-#define E2PAGESIZE (4) +-#define FLASHEND (0x7FFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ +-#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ +-#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define FUSE_HWBE (unsigned char)~_BV(3) /* Hardware Boot Enable */ +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x95 +-#define SIGNATURE_2 0x88 +- +- +-#endif /* _AVR_ATmega32U6_H_ */ +- ++/* Copyright (c) 2008 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom32u6.h 1873 2009-02-11 17:53:39Z arcanum $ */ ++ ++/* avr/iom32u6.h - definitions for ATmega32U6 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom32u6.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATmega32U6_H_ ++#define _AVR_ATmega32U6_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++#define PINA4 4 ++#define PINA5 5 ++#define PINA6 6 ++#define PINA7 7 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++#define DDA4 4 ++#define DDA5 5 ++#define DDA6 6 ++#define DDA7 7 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA0 0 ++#define PORTA1 1 ++#define PORTA2 2 ++#define PORTA3 3 ++#define PORTA4 4 ++#define PORTA5 5 ++#define PORTA6 6 ++#define PORTA7 7 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++#define PINC7 7 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++#define DDC7 7 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC3 3 ++#define PORTC4 4 ++#define PORTC5 5 ++#define PORTC6 6 ++#define PORTC7 7 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE0 0 ++#define PINE1 1 ++#define PINE2 2 ++#define PINE3 3 ++#define PINE4 4 ++#define PINE5 5 ++#define PINE6 6 ++#define PINE7 7 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE0 0 ++#define DDE1 1 ++#define DDE2 2 ++#define DDE3 3 ++#define DDE4 4 ++#define DDE5 5 ++#define DDE6 6 ++#define DDE7 7 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE0 0 ++#define PORTE1 1 ++#define PORTE2 2 ++#define PORTE3 3 ++#define PORTE4 4 ++#define PORTE5 5 ++#define PORTE6 6 ++#define PORTE7 7 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF0 0 ++#define PINF1 1 ++#define PINF2 2 ++#define PINF3 3 ++#define PINF4 4 ++#define PINF5 5 ++#define PINF6 6 ++#define PINF7 7 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDF0 0 ++#define DDF1 1 ++#define DDF2 2 ++#define DDF3 3 ++#define DDF4 4 ++#define DDF5 5 ++#define DDF6 6 ++#define DDF7 7 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PORTF0 0 ++#define PORTF1 1 ++#define PORTF2 2 ++#define PORTF3 3 ++#define PORTF4 4 ++#define PORTF5 5 ++#define PORTF6 6 ++#define PORTF7 7 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define OCF1C 3 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++#define TIFR3 _SFR_IO8(0x18) ++#define TOV3 0 ++#define OCF3A 1 ++#define OCF3B 2 ++#define OCF3C 3 ++#define ICF3 5 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++#define INTF4 4 ++#define INTF5 5 ++#define INTF6 6 ++#define INTF7 7 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++#define INT3 3 ++#define INT4 4 ++#define INT5 5 ++#define INT6 6 ++#define INT7 7 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++#define EEAR9 1 ++#define EEAR10 2 ++#define EEAR11 3 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define PSRASY 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define OCR0A _SFR_IO8(0x27) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define OCR0B _SFR_IO8(0x28) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define PLLCSR _SFR_IO8(0x29) ++#define PLOCK 0 ++#define PLLE 1 ++#define PLLP0 2 ++#define PLLP1 3 ++#define PLLP2 4 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCDR7 7 ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define JTRF 4 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define JTD 7 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++#define PRR1 _SFR_MEM8(0x65) ++#define PRUSART1 0 ++#define PRTIM3 3 ++#define PRUSB 7 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++#define EICRB _SFR_MEM8(0x6A) ++#define ISC40 0 ++#define ISC41 1 ++#define ISC50 2 ++#define ISC51 3 ++#define ISC60 4 ++#define ISC61 5 ++#define ISC70 6 ++#define ISC71 7 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define OCIE1C 3 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++#define TIMSK3 _SFR_MEM8(0x71) ++#define TOIE3 0 ++#define OCIE3A 1 ++#define OCIE3B 2 ++#define OCIE3C 3 ++#define ICIE3 5 ++ ++#define XMCRA _SFR_MEM8(0x74) ++#define SRW00 0 ++#define SRW01 1 ++#define SRW10 2 ++#define SRW11 3 ++#define SRL0 4 ++#define SRL1 5 ++#define SRL2 6 ++#define SRE 7 ++ ++#define XMCRB _SFR_MEM8(0x75) ++#define XMM0 0 ++#define XMM1 1 ++#define XMM2 2 ++#define XMBK 7 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_MEM8(0x79) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++#define ADHSM 7 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1C0 2 ++#define COM1C1 3 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1C 5 ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define OCR1C _SFR_MEM16(0x8C) ++ ++#define OCR1CL _SFR_MEM8(0x8C) ++#define OCR1CL0 0 ++#define OCR1CL1 1 ++#define OCR1CL2 2 ++#define OCR1CL3 3 ++#define OCR1CL4 4 ++#define OCR1CL5 5 ++#define OCR1CL6 6 ++#define OCR1CL7 7 ++ ++#define OCR1CH _SFR_MEM8(0x8D) ++#define OCR1CH0 0 ++#define OCR1CH1 1 ++#define OCR1CH2 2 ++#define OCR1CH3 3 ++#define OCR1CH4 4 ++#define OCR1CH5 5 ++#define OCR1CH6 6 ++#define OCR1CH7 7 ++ ++#define TCCR3A _SFR_MEM8(0x90) ++#define WGM30 0 ++#define WGM31 1 ++#define COM3C0 2 ++#define COM3C1 3 ++#define COM3B0 4 ++#define COM3B1 5 ++#define COM3A0 6 ++#define COM3A1 7 ++ ++#define TCCR3B _SFR_MEM8(0x91) ++#define CS30 0 ++#define CS31 1 ++#define CS32 2 ++#define WGM32 3 ++#define WGM33 4 ++#define ICES3 6 ++#define ICNC3 7 ++ ++#define TCCR3C _SFR_MEM8(0x92) ++#define FOC3C 5 ++#define FOC3B 6 ++#define FOC3A 7 ++ ++#define TCNT3 _SFR_MEM16(0x94) ++ ++#define TCNT3L _SFR_MEM8(0x94) ++#define TCNT3L0 0 ++#define TCNT3L1 1 ++#define TCNT3L2 2 ++#define TCNT3L3 3 ++#define TCNT3L4 4 ++#define TCNT3L5 5 ++#define TCNT3L6 6 ++#define TCNT3L7 7 ++ ++#define TCNT3H _SFR_MEM8(0x95) ++#define TCNT3H0 0 ++#define TCNT3H1 1 ++#define TCNT3H2 2 ++#define TCNT3H3 3 ++#define TCNT3H4 4 ++#define TCNT3H5 5 ++#define TCNT3H6 6 ++#define TCNT3H7 7 ++ ++#define ICR3 _SFR_MEM16(0x96) ++ ++#define ICR3L _SFR_MEM8(0x96) ++#define ICR3L0 0 ++#define ICR3L1 1 ++#define ICR3L2 2 ++#define ICR3L3 3 ++#define ICR3L4 4 ++#define ICR3L5 5 ++#define ICR3L6 6 ++#define ICR3L7 7 ++ ++#define ICR3H _SFR_MEM8(0x97) ++#define ICR3H0 0 ++#define ICR3H1 1 ++#define ICR3H2 2 ++#define ICR3H3 3 ++#define ICR3H4 4 ++#define ICR3H5 5 ++#define ICR3H6 6 ++#define ICR3H7 7 ++ ++#define OCR3A _SFR_MEM16(0x98) ++ ++#define OCR3AL _SFR_MEM8(0x98) ++#define OCR3AL0 0 ++#define OCR3AL1 1 ++#define OCR3AL2 2 ++#define OCR3AL3 3 ++#define OCR3AL4 4 ++#define OCR3AL5 5 ++#define OCR3AL6 6 ++#define OCR3AL7 7 ++ ++#define OCR3AH _SFR_MEM8(0x99) ++#define OCR3AH0 0 ++#define OCR3AH1 1 ++#define OCR3AH2 2 ++#define OCR3AH3 3 ++#define OCR3AH4 4 ++#define OCR3AH5 5 ++#define OCR3AH6 6 ++#define OCR3AH7 7 ++ ++#define OCR3B _SFR_MEM16(0x9A) ++ ++#define OCR3BL _SFR_MEM8(0x9A) ++#define OCR3BL0 0 ++#define OCR3BL1 1 ++#define OCR3BL2 2 ++#define OCR3BL3 3 ++#define OCR3BL4 4 ++#define OCR3BL5 5 ++#define OCR3BL6 6 ++#define OCR3BL7 7 ++ ++#define OCR3BH _SFR_MEM8(0x9B) ++#define OCR3BH0 0 ++#define OCR3BH1 1 ++#define OCR3BH2 2 ++#define OCR3BH3 3 ++#define OCR3BH4 4 ++#define OCR3BH5 5 ++#define OCR3BH6 6 ++#define OCR3BH7 7 ++ ++#define OCR3C _SFR_MEM16(0x9C) ++ ++#define OCR3CL _SFR_MEM8(0x9C) ++#define OCR3CL0 0 ++#define OCR3CL1 1 ++#define OCR3CL2 2 ++#define OCR3CL3 3 ++#define OCR3CL4 4 ++#define OCR3CL5 5 ++#define OCR3CL6 6 ++#define OCR3CL7 7 ++ ++#define OCR3CH _SFR_MEM8(0x9D) ++#define OCR3CH0 0 ++#define OCR3CH1 1 ++#define OCR3CH2 2 ++#define OCR3CH3 3 ++#define OCR3CH4 4 ++#define OCR3CH5 5 ++#define OCR3CH6 6 ++#define OCR3CH7 7 ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++#define TCNT2_0 0 ++#define TCNT2_1 1 ++#define TCNT2_2 2 ++#define TCNT2_3 3 ++#define TCNT2_4 4 ++#define TCNT2_5 5 ++#define TCNT2_6 6 ++#define TCNT2_7 7 ++ ++#define OCR2A _SFR_MEM8(0xB3) ++#define OCR2A_0 0 ++#define OCR2A_1 1 ++#define OCR2A_2 2 ++#define OCR2A_3 3 ++#define OCR2A_4 4 ++#define OCR2A_5 5 ++#define OCR2A_6 6 ++#define OCR2A_7 7 ++ ++#define OCR2B _SFR_MEM8(0xB4) ++#define OCR2B_0 0 ++#define OCR2B_1 1 ++#define OCR2B_2 2 ++#define OCR2B_3 3 ++#define OCR2B_4 4 ++#define OCR2B_5 5 ++#define OCR2B_6 6 ++#define OCR2B_7 7 ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++ ++#define TWBR _SFR_MEM8(0xB8) ++#define TWBR0 0 ++#define TWBR1 1 ++#define TWBR2 2 ++#define TWBR3 3 ++#define TWBR4 4 ++#define TWBR5 5 ++#define TWBR6 6 ++#define TWBR7 7 ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++#define TWD0 0 ++#define TWD1 1 ++#define TWD2 2 ++#define TWD3 3 ++#define TWD4 4 ++#define TWD5 5 ++#define TWD6 6 ++#define TWD7 7 ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++#define UCSR1A _SFR_MEM8(0xC8) ++#define MPCM1 0 ++#define U2X1 1 ++#define UPE1 2 ++#define DOR1 3 ++#define FE1 4 ++#define UDRE1 5 ++#define TXC1 6 ++#define RXC1 7 ++ ++#define UCSR1B _SFR_MEM8(0xC9) ++#define TXB81 0 ++#define RXB81 1 ++#define UCSZ12 2 ++#define TXEN1 3 ++#define RXEN1 4 ++#define UDRIE1 5 ++#define TXCIE1 6 ++#define RXCIE1 7 ++ ++#define UCSR1C _SFR_MEM8(0xCA) ++#define UCPOL1 0 ++#define UCSZ10 1 ++#define UCSZ11 2 ++#define USBS1 3 ++#define UPM10 4 ++#define UPM11 5 ++#define UMSEL10 6 ++#define UMSEL11 7 ++ ++#define UBRR1 _SFR_MEM16(0xCC) ++ ++#define UBRR1L _SFR_MEM8(0xCC) ++#define UBRR_0 0 ++#define UBRR_1 1 ++#define UBRR_2 2 ++#define UBRR_3 3 ++#define UBRR_4 4 ++#define UBRR_5 5 ++#define UBRR_6 6 ++#define UBRR_7 7 ++ ++#define UBRR1H _SFR_MEM8(0xCD) ++#define UBRR_8 0 ++#define UBRR_9 1 ++#define UBRR_10 2 ++#define UBRR_11 3 ++ ++#define UDR1 _SFR_MEM8(0xCE) ++#define UDR1_0 0 ++#define UDR1_1 1 ++#define UDR1_2 2 ++#define UDR1_3 3 ++#define UDR1_4 4 ++#define UDR1_5 5 ++#define UDR1_6 6 ++#define UDR1_7 7 ++ ++#define UHWCON _SFR_MEM8(0xD7) ++#define UVREGE 0 ++#define UVCONE 4 ++#define UIDE 6 ++#define UIMOD 7 ++ ++#define USBCON _SFR_MEM8(0xD8) ++#define VBUSTE 0 ++#define IDTE 1 ++#define OTGPADE 4 ++#define FRZCLK 5 ++#define HOST 6 ++#define USBE 7 ++ ++#define USBSTA _SFR_MEM8(0xD9) ++#define VBUS 0 ++#define ID 1 ++#define SPEED 3 ++ ++#define USBINT _SFR_MEM8(0xDA) ++#define VBUSTI 0 ++#define IDTI 1 ++ ++#define UDCON _SFR_MEM8(0xE0) ++#define DETACH 0 ++#define RMWKUP 1 ++#define LSM 2 ++ ++#define UDINT _SFR_MEM8(0xE1) ++#define SUSPI 0 ++#define SOFI 2 ++#define EORSTI 3 ++#define WAKEUPI 4 ++#define EORSMI 5 ++#define UPRSMI 6 ++ ++#define UDIEN _SFR_MEM8(0xE2) ++#define SUSPE 0 ++#define SOFE 2 ++#define EORSTE 3 ++#define WAKEUPE 4 ++#define EORSME 5 ++#define UPRSME 6 ++ ++#define UDADDR _SFR_MEM8(0xE3) ++#define UADD0 0 ++#define UADD1 1 ++#define UADD2 2 ++#define UADD3 3 ++#define UADD4 4 ++#define UADD5 5 ++#define UADD6 6 ++#define ADDEN 7 ++ ++#define UDFNUM _SFR_MEM16(0xE4) ++ ++#define UDFNUML _SFR_MEM8(0xE4) ++#define UDFNUML_0 0 ++#define UDFNUML_1 1 ++#define UDFNUML_2 2 ++#define UDFNUML_3 3 ++#define UDFNUML_4 4 ++#define UDFNUML_5 5 ++#define UDFNUML_6 6 ++#define UDFNUML_7 7 ++ ++#define UDFNUMH _SFR_MEM8(0xE5) ++#define UDFNUMH_0 0 ++#define UDFNUMH_1 1 ++#define UDFNUMH_2 2 ++ ++#define UDMFN _SFR_MEM8(0xE6) ++#define FNCERR 4 ++ ++#define UEINTX _SFR_MEM8(0xE8) ++#define TXINI 0 ++#define STALLEDI 1 ++#define RXOUTI 2 ++#define RXSTPI 3 ++#define NAKOUTI 4 ++#define RWAL 5 ++#define NAKINI 6 ++#define FIFOCON 7 ++ ++#define UENUM _SFR_MEM8(0xE9) ++#define UENUM_0 0 ++#define UENUM_1 1 ++#define UENUM_2 2 ++ ++#define UERST _SFR_MEM8(0xEA) ++#define EPRST0 0 ++#define EPRST1 1 ++#define EPRST2 2 ++#define EPRST3 3 ++#define EPRST4 4 ++#define EPRST5 5 ++#define EPRST6 6 ++ ++#define UECONX _SFR_MEM8(0xEB) ++#define EPEN 0 ++#define RSTDT 3 ++#define STALLRQC 4 ++#define STALLRQ 5 ++ ++#define UECFG0X _SFR_MEM8(0xEC) ++#define EPDIR 0 ++#define EPTYPE0 6 ++#define EPTYPE1 7 ++ ++#define UECFG1X _SFR_MEM8(0xED) ++#define ALLOC 1 ++#define EPBK0 2 ++#define EPBK1 3 ++#define EPSIZE0 4 ++#define EPSIZE1 5 ++#define EPSIZE2 6 ++ ++#define UESTA0X _SFR_MEM8(0xEE) ++#define NBUSYBK0 0 ++#define NBUSYBK1 1 ++#define DTSEQ0 2 ++#define DTSEQ1 3 ++#define UNDERFI 5 ++#define OVERFI 6 ++#define CFGOK 7 ++ ++#define UESTA1X _SFR_MEM8(0xEF) ++#define CURRBK0 0 ++#define CURRBK1 1 ++#define CTRLDIR 2 ++ ++#define UEIENX _SFR_MEM8(0xF0) ++#define TXINE 0 ++#define STALLEDE 1 ++#define RXOUTE 2 ++#define RXSTPE 3 ++#define NAKOUTE 4 ++#define NAKINE 6 ++#define FLERRE 7 ++ ++#define UEDATX _SFR_MEM8(0xF1) ++#define UEDATX_0 0 ++#define UEDATX_1 1 ++#define UEDATX_2 2 ++#define UEDATX_3 3 ++#define UEDATX_4 4 ++#define UEDATX_5 5 ++#define UEDATX_6 6 ++#define UEDATX_7 7 ++ ++#define UEBCLX _SFR_MEM8(0xF2) ++#define UEBCLX_0 0 ++#define UEBCLX_1 1 ++#define UEBCLX_2 2 ++#define UEBCLX_3 3 ++#define UEBCLX_4 4 ++#define UEBCLX_5 5 ++#define UEBCLX_6 6 ++#define UEBCLX_7 7 ++ ++#define UEBCHX _SFR_MEM8(0xF3) ++#define UEBCHX_0 0 ++#define UEBCHX_1 1 ++#define UEBCHX_2 2 ++ ++#define UEINT _SFR_MEM8(0xF4) ++#define EPINT0 0 ++#define EPINT1 1 ++#define EPINT2 2 ++#define EPINT3 3 ++#define EPINT4 4 ++#define EPINT5 5 ++#define EPINT6 6 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ ++#define INT2_vect_num 3 ++#define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ ++#define INT3_vect_num 4 ++#define INT3_vect _VECTOR(4) /* External Interrupt Request 3 */ ++#define INT4_vect_num 5 ++#define INT4_vect _VECTOR(5) /* External Interrupt Request 4 */ ++#define INT5_vect_num 6 ++#define INT5_vect _VECTOR(6) /* External Interrupt Request 5 */ ++#define INT6_vect_num 7 ++#define INT6_vect _VECTOR(7) /* External Interrupt Request 6 */ ++#define INT7_vect_num 8 ++#define INT7_vect _VECTOR(8) /* External Interrupt Request 7 */ ++#define PCINT0_vect_num 9 ++#define PCINT0_vect _VECTOR(9) /* Pin Change Interrupt Request 0 */ ++#define USB_GEN_vect_num 10 ++#define USB_GEN_vect _VECTOR(10) /* USB General Interrupt Request */ ++#define USB_COM_vect_num 11 ++#define USB_COM_vect _VECTOR(11) /* USB Endpoint/Pipe Interrupt Communication Request */ ++#define WDT_vect_num 12 ++#define WDT_vect _VECTOR(12) /* Watchdog Time-out Interrupt */ ++#define TIMER2_COMPA_vect_num 13 ++#define TIMER2_COMPA_vect _VECTOR(13) /* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPB_vect_num 14 ++#define TIMER2_COMPB_vect _VECTOR(14) /* Timer/Counter2 Compare Match B */ ++#define TIMER2_OVF_vect_num 15 ++#define TIMER2_OVF_vect _VECTOR(15) /* Timer/Counter2 Overflow */ ++#define TIMER1_CAPT_vect_num 16 ++#define TIMER1_CAPT_vect _VECTOR(16) /* Timer/Counter1 Capture Event */ ++#define TIMER1_COMPA_vect_num 17 ++#define TIMER1_COMPA_vect _VECTOR(17) /* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPB_vect_num 18 ++#define TIMER1_COMPB_vect _VECTOR(18) /* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPC_vect_num 19 ++#define TIMER1_COMPC_vect _VECTOR(19) /* Timer/Counter1 Compare Match C */ ++#define TIMER1_OVF_vect_num 20 ++#define TIMER1_OVF_vect _VECTOR(20) /* Timer/Counter1 Overflow */ ++#define TIMER0_COMPA_vect_num 21 ++#define TIMER0_COMPA_vect _VECTOR(21) /* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPB_vect_num 22 ++#define TIMER0_COMPB_vect _VECTOR(22) /* Timer/Counter0 Compare Match B */ ++#define TIMER0_OVF_vect_num 23 ++#define TIMER0_OVF_vect _VECTOR(23) /* Timer/Counter0 Overflow */ ++#define SPI_STC_vect_num 24 ++#define SPI_STC_vect _VECTOR(24) /* SPI Serial Transfer Complete */ ++#define USART1_RX_vect_num 25 ++#define USART1_RX_vect _VECTOR(25) /* USART1, Rx Complete */ ++#define USART1_UDRE_vect_num 26 ++#define USART1_UDRE_vect _VECTOR(26) /* USART1 Data register Empty */ ++#define USART1_TX_vect_num 27 ++#define USART1_TX_vect _VECTOR(27) /* USART1, Tx Complete */ ++#define ANALOG_COMP_vect_num 28 ++#define ANALOG_COMP_vect _VECTOR(28) /* Analog Comparator */ ++#define ADC_vect_num 29 ++#define ADC_vect _VECTOR(29) /* ADC Conversion Complete */ ++#define EE_READY_vect_num 30 ++#define EE_READY_vect _VECTOR(30) /* EEPROM Ready */ ++#define TIMER3_CAPT_vect_num 31 ++#define TIMER3_CAPT_vect _VECTOR(31) /* Timer/Counter3 Capture Event */ ++#define TIMER3_COMPA_vect_num 32 ++#define TIMER3_COMPA_vect _VECTOR(32) /* Timer/Counter3 Compare Match A */ ++#define TIMER3_COMPB_vect_num 33 ++#define TIMER3_COMPB_vect _VECTOR(33) /* Timer/Counter3 Compare Match B */ ++#define TIMER3_COMPC_vect_num 34 ++#define TIMER3_COMPC_vect _VECTOR(34) /* Timer/Counter3 Compare Match C */ ++#define TIMER3_OVF_vect_num 35 ++#define TIMER3_OVF_vect _VECTOR(35) /* Timer/Counter3 Overflow */ ++#define TWI_vect_num 36 ++#define TWI_vect _VECTOR(36) /* 2-wire Serial Interface */ ++#define SPM_READY_vect_num 37 ++#define SPM_READY_vect _VECTOR(37) /* Store Program Memory Read */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (38 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (128) ++#define RAMSTART (0x100) ++#define RAMSIZE (2560) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (0x2200) ++#define XRAMSIZE (65536) ++#define XRAMEND (XRAMSIZE - 1) ++#define E2END (0x3FF) ++#define E2PAGESIZE (4) ++#define FLASHEND (0x7FFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ ++#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ ++#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define FUSE_HWBE (unsigned char)~_BV(3) /* Hardware Boot Enable */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x88 ++ ++ ++#endif /* _AVR_ATmega32U6_H_ */ ++ +diff --git a/include/avr/iom406.h b/include/avr/iom406.h +index 29c6531..4cd9656 100644 +--- a/include/avr/iom406.h ++++ b/include/avr/iom406.h +@@ -1,771 +1,772 @@ +-/* Copyright (c) 2006, Pieter Conradie +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom406.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* avr/iom406.h - definitions for ATmega406 */ +- +-#ifndef _AVR_IOM406_H_ +-#define _AVR_IOM406_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom406.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-#define PORTA _SFR_IO8(0x02) +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-#define PINB _SFR_IO8(0x03) +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-#define PORTB _SFR_IO8(0x05) +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* Reserved [0x06..0x07] */ +- +-#define PORTC _SFR_IO8(0x08) +-#define PC0 0 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND1 1 +-#define PIND0 0 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD1 1 +-#define DDD0 0 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PD1 1 +-#define PD0 0 +- +-/* Reserved [0x0C..0x14] */ +- +-/* Timer/Counter0 Interrupt Flag Register */ +-#define TIFR0 _SFR_IO8(0x15) +-#define OCF0B 2 +-#define OCF0A 1 +-#define TOV0 0 +- +-/* Timer/Counter1 Interrupt Flag Register */ +-#define TIFR1 _SFR_IO8(0x16) +-#define OCF1A 1 +-#define TOV1 0 +- +-/* Reserved [0x17..0x1A] */ +- +-/* Pin Change Interrupt Control Register */ +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF1 1 +-#define PCIF0 0 +- +-/* External Interrupt Flag Register */ +-#define EIFR _SFR_IO8(0x1C) +-#define INTF3 3 +-#define INTF2 2 +-#define INTF1 1 +-#define INTF0 0 +- +-/* External Interrupt MaSK register */ +-#define EIMSK _SFR_IO8(0x1D) +-#define INT3 3 +-#define INT2 2 +-#define INT1 1 +-#define INT0 0 +- +-/* General Purpose I/O Register 0 */ +-#define GPIOR0 _SFR_IO8(0x1E) +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1F) +-#define EEPM1 5 +-#define EEPM0 4 +-#define EERIE 3 +-#define EEMPE 2 +-#define EEPE 1 +-#define EERE 0 +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x20) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO16(0x21) +-#define EEARL _SFR_IO8(0x21) +-#define EEARH _SFR_IO8(0x22) +- +-/* 6-char sequence denoting where to find the EEPROM registers in memory space. +- Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM +- subroutines. +- First two letters: EECR address. +- Second two letters: EEDR address. +- Last two letters: EEAR address. */ +-#define __EEPROM_REG_LOCATIONS__ 1F2021 +- +-/* General Timer/Counter Control Register */ +-#define GTCCR _SFR_IO8(0x23) +-#define TSM 7 +-#define PSRSYNC 0 +- +-/* Timer/Counter Control Register A */ +-#define TCCR0A _SFR_IO8(0x24) +-#define COM0A1 7 +-#define COM0A0 6 +-#define COM0B1 5 +-#define COM0B0 4 +-#define WGM01 1 +-#define WGM00 0 +- +-/* Timer/Counter Control Register B */ +-#define TCCR0B _SFR_IO8(0x25) +-#define FOC0A 7 +-#define FOC0B 6 +-#define WGM02 3 +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* Timer/Counter 0 */ +-#define TCNT0 _SFR_IO8(0x26) +- +-/* Output Compare Register A */ +-#define OCR0A _SFR_IO8(0x27) +- +-/* Output Compare Register B */ +-#define OCR0B _SFR_IO8(0x28) +- +-/* Reserved [0x29] */ +- +-/* General Purpose I/O Register 1 */ +-#define GPIOR1 _SFR_IO8(0x2A) +- +-/* General Purpose I/O Register 2 */ +-#define GPIOR2 _SFR_IO8(0x2B) +- +-/* Reserved [0x2C..0x30] */ +- +-/* On-chip Debug Register */ +-#define OCDR _SFR_IO8(0x31) +- +-/* Reserved [0x32] */ +- +-/* Sleep Mode Control Register */ +-#define SMCR _SFR_IO8(0x33) +-#define SM2 3 +-#define SM1 2 +-#define SM0 1 +-#define SE 0 +- +-/* MCU Status Register */ +-#define MCUSR _SFR_IO8(0x34) +-#define JTRF 4 +-#define WDRF 3 +-#define BODRF 2 +-#define EXTRF 1 +-#define PORF 0 +- +-/* MCU general Control Register */ +-#define MCUCR _SFR_IO8(0x35) +-#define JTD 7 +-#define PUD 4 +-#define IVSEL 1 +-#define IVCE 0 +- +-/* Reserved [0x36] */ +- +-/* Store Program Memory Control and Status Register */ +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMIE 7 +-#define RWWSB 6 +-#define SIGRD 5 +-#define RWWSRE 4 +-#define BLBSET 3 +-#define PGWRT 2 +-#define PGERS 1 +-#define SPMEN 0 +- +-/* Reserved [0x36..0x3C] */ +- +-/* 0x3D..0x3E SP */ +- +-/* 0x3F SREG */ +- +-/* Extended I/O registers */ +- +-/* Watchdog Timer Control Register */ +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDIF 7 +-#define WDIE 6 +-#define WDP3 5 +-#define WDCE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* Reserved [0x61] */ +- +-/* Wake-up Timer Control and Status Register */ +-#define WUTCSR _SFR_MEM8(0x62) +-#define WUTIF 7 +-#define WUTIE 6 +-#define WUTCF 5 +-#define WUTR 4 +-#define WUTE 3 +-#define WUTP2 2 +-#define WUTP1 1 +-#define WUTP0 0 +- +-/* Reserved [0x63] */ +- +-/* Power Reduction Register 0 */ +-#define PRR0 _SFR_MEM8(0x64) +-#define PRTWI 3 +-#define PRTIM1 2 +-#define PRTIM0 1 +-#define PRVADC 0 +- +-/* Reserved [0x65] */ +- +-/* Fast Oscillator Calibration Register */ +-#define FOSCCAL _SFR_MEM8(0x66) +- +-/* Reserved [0x67] */ +- +-/* Pin Change Interrupt Control Register */ +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE1 1 +-#define PCIE0 0 +- +-/* External Interrupt Control Register A */ +-#define EICRA _SFR_MEM8(0x69) +-#define ISC31 7 +-#define ISC30 6 +-#define ISC21 5 +-#define ISC20 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-/* Reserved [0x6A] */ +- +-/* Pin Change Mask Register 0 */ +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT7 7 +-#define PCINT6 6 +-#define PCINT5 5 +-#define PCINT4 4 +-#define PCINT3 3 +-#define PCINT2 2 +-#define PCINT1 1 +-#define PCINT0 0 +- +-/* Pin Change Mask Register 1 */ +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT15 7 +-#define PCINT14 6 +-#define PCINT13 5 +-#define PCINT12 4 +-#define PCINT11 3 +-#define PCINT10 2 +-#define PCINT9 1 +-#define PCINT8 0 +- +-/* Reserved [0x6D] */ +- +-/* Timer/Counter Interrupt MaSK register 0 */ +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define OCIE0B 2 +-#define OCIE0A 1 +-#define TOIE0 0 +- +-/* Timer/Counter Interrupt MaSK register 1 */ +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define OCIE1A 1 +-#define TOIE1 0 +- +-/* Reserved [0x70..0x77] */ +- +-/* V-ADC Data Register */ +-#define VADC _SFR_MEM16(0x78) +-#define VADCL _SFR_MEM8(0x78) +-#define VADCH _SFR_MEM8(0x79) +- +-/* V-ADC Control and Status Register */ +-#define VADCSR _SFR_MEM8(0x7A) +-#define VADEN 3 +-#define VADSC 2 +-#define VADCCIF 1 +-#define VADCCIE 0 +- +-/* Reserved [0x7B] */ +- +-/* V-ADC Multiplexer Selection Register */ +-#define VADMUX _SFR_MEM8(0x7C) +-#define VADMUX3 3 +-#define VADMUX2 2 +-#define VADMUX1 1 +-#define VADMUX0 0 +- +-/* Reserved [0x7D] */ +- +-/* Digital Input Disable Register 0 */ +-#define DIDR0 _SFR_MEM8(0x7E) +-#define VADC3D 3 +-#define VADC2D 2 +-#define VADC1D 1 +-#define VADC0D 0 +- +-/* Reserved [0x82..0x83] */ +- +-/* Timer/Counter 1 Control and Status Register */ +-#define TCCR1B _SFR_MEM8(0x81) +-#define CTC1 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* Reserved [0x82..0x83] */ +- +-/* Timer/Counter 1 */ +-#define TCNT1 _SFR_MEM16(0x84) +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1H _SFR_MEM8(0x85) +- +-/* Reserved [0x86..0x87] */ +- +-/* Timer/Counter1 Output Compare Register A */ +-#define OCR1A _SFR_MEM16(0x88) +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AH _SFR_MEM8(0x89) +- +-/* Reserved [0x8A..0xB7] */ +- +-/* 2-wire Serial Interface Bit Rate Register */ +-#define TWBR _SFR_MEM8(0xB8) +- +-/* 2-wire Serial Interface Status Register */ +-#define TWSR _SFR_MEM8(0xB9) +-#define TWS7 7 +-#define TWS6 6 +-#define TWS5 5 +-#define TWS4 4 +-#define TWS3 3 +-#define TWPS1 1 +-#define TWPS0 0 +- +-/* 2-wire Serial Interface Address Register */ +-#define TWAR _SFR_MEM8(0xBA) +-#define TWA6 7 +-#define TWA5 6 +-#define TWA4 5 +-#define TWA3 4 +-#define TWA2 3 +-#define TWA1 2 +-#define TWA0 1 +-#define TWGCE 0 +- +-/* 2-wire Serial Interface Data Register */ +-#define TWDR _SFR_MEM8(0xBB) +- +-/* 2-wire Serial Interface Control Register */ +-#define TWCR _SFR_MEM8(0xBC) +-#define TWINT 7 +-#define TWEA 6 +-#define TWSTA 5 +-#define TWSTO 4 +-#define TWWC 3 +-#define TWEN 2 +-#define TWIE 0 +- +-/* 2-wire Serial (Slave) Address Mask Register */ +-#define TWAMR _SFR_MEM8(0xBD) +-#define TWAM6 7 +-#define TWAM5 6 +-#define TWAM4 5 +-#define TWAM3 4 +-#define TWAM2 3 +-#define TWAM1 2 +-#define TWAM0 1 +- +-/* 2-wire Serial Bus Control and Status Register */ +-#define TWBCSR _SFR_MEM8(0xBE) +-#define TWBCIF 7 +-#define TWBCIE 6 +-#define TWBDT1 2 +-#define TWBDT0 1 +-#define TWBCIP 0 +- +-/* Reserved [0xBF] */ +- +-/* Clock Control Status Register */ +-#define CCSR _SFR_MEM8(0xC0) +-#define XOE 1 +-#define ACS 0 +- +-/* Reserved [0xC1..0xCF] */ +- +-/* Bandgap Calibration C Register */ +-#define BGCCR _SFR_MEM8(0xD0) +-#define BGEN 7 +-#define BGCC5 5 +-#define BGCC4 4 +-#define BGCC3 3 +-#define BGCC2 2 +-#define BGCC1 1 +-#define BGCC0 0 +- +-/* Bandgap Calibration R Register */ +-#define BGCRR _SFR_MEM8(0xD1) +-#define BGCR7 7 +-#define BGCR6 6 +-#define BGCR5 5 +-#define BGCR4 4 +-#define BGCR3 3 +-#define BGCR2 2 +-#define BGCR1 1 +-#define BGCR0 0 +- +-/* Reserved [0xD2..0xDF] */ +- +-/* CC-ADC Accumulate Current */ +-/* TODO: Add _SFR_MEM32 */ +-/* #define CADAC _SFR_MEM32(0xE0) */ +-#define CADAC0 _SFR_MEM8(0xE0) +-#define CADAC1 _SFR_MEM8(0xE1) +-#define CADAC2 _SFR_MEM8(0xE2) +-#define CADAC3 _SFR_MEM8(0xE3) +- +-/* CC-ADC Control and Status Register A */ +-#define CADCSRA _SFR_MEM8(0xE4) +-#define CADEN 7 +-#define CADUB 5 +-#define CADAS1 4 +-#define CADAS0 3 +-#define CADSI1 2 +-#define CADSI0 1 +-#define CADSE 0 +- +-/* CC-ADC Control and Status Register B */ +-#define CADCSRB _SFR_MEM8(0xE5) +-#define CADACIE 6 +-#define CADRCIE 5 +-#define CADICIE 4 +-#define CADACIF 2 +-#define CADRCIF 1 +-#define CADICIF 0 +- +-/* CC-ADC Regular Charge Current */ +-#define CADRCC _SFR_MEM8(0xE6) +- +-/* CC-ADC Regular Discharge Current */ +-#define CADRDC _SFR_MEM8(0xE7) +- +-/* CC-ADC Instantaneous Current */ +-#define CADIC _SFR_MEM16(0xE8) +-#define CADICL _SFR_MEM8(0xE8) +-#define CADICH _SFR_MEM8(0xE9) +- +-/* Reserved [0xEA..0xEF] */ +- +-/* FET Control and Status Register */ +-#define FCSR _SFR_MEM8(0xF0) +-#define PWMOC 5 +-#define PWMOPC 4 +-#define CPS 3 +-#define DFE 2 +-#define CFE 1 +-#define PFD 0 +- +-/* Cell Balancing Control Register */ +-#define CBCR _SFR_MEM8(0xF1) +-#define CBE4 3 +-#define CBE3 2 +-#define CBE2 1 +-#define CBE1 0 +- +-/* Battery Protection Interrupt Register */ +-#define BPIR _SFR_MEM8(0xF2) +-#define DUVIF 7 +-#define COCIF 6 +-#define DOCIF 5 +-#define SCIF 4 +-#define DUVIE 3 +-#define COCIE 2 +-#define DOCIE 1 +-#define SCIE 0 +- +-/* Battery Protection Deep Under Voltage Register */ +-#define BPDUV _SFR_MEM8(0xF3) +-#define DUVT1 5 +-#define DUVT0 4 +-#define DUDL3 3 +-#define DUDL2 2 +-#define DUDL1 1 +-#define DUDL0 0 +- +-/* Battery Protection Short-circuit Detection Level Register */ +-#define BPSCD _SFR_MEM8(0xF4) +-#define SCDL3 3 +-#define SCDL2 2 +-#define SCDL1 1 +-#define SCDL0 0 +- +-/* Battery Protection Over-current Detection Level Register */ +-#define BPOCD _SFR_MEM8(0xF5) +-#define DCDL3 7 +-#define DCDL2 6 +-#define DCDL1 5 +-#define DCDL0 4 +-#define CCDL3 3 +-#define CCDL2 2 +-#define CCDL1 1 +-#define CCDL0 0 +- +-/* Current Battery Protection Timing Register */ +-#define CBPTR _SFR_MEM8(0xF6) +-#define SCPT3 7 +-#define SCPT2 6 +-#define SCPT1 5 +-#define SCPT0 4 +-#define OCPT3 3 +-#define OCPT2 2 +-#define OCPT1 1 +-#define OCPT0 0 +- +-/* Battery Protection Control Register */ +-#define BPCR _SFR_MEM8(0xF7) +-#define DUVD 3 +-#define SCD 2 +-#define DCD 1 +-#define CCD 0 +- +-/* Battery Protection Parameter Lock Register */ +-#define BPPLR _SFR_MEM8(0xF8) +-#define BPPLE 1 +-#define BPPL 0 +- +-/* Reserved [0xF9..0xFF] */ +- +-/* Interrupt vectors */ +- +-/* Battery Protection Interrupt */ +-#define BPINT_vect_num 1 +-#define BPINT_vect _VECTOR(1) +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 2 +-#define INT0_vect _VECTOR(2) +- +-/* External Interrupt Request 1 */ +-#define INT1_vect_num 3 +-#define INT1_vect _VECTOR(3) +- +-/* External Interrupt Request 2 */ +-#define INT2_vect_num 4 +-#define INT2_vect _VECTOR(4) +- +-/* External Interrupt Request 3 */ +-#define INT3_vect_num 5 +-#define INT3_vect _VECTOR(5) +- +-/* Pin Change Interrupt 0 */ +-#define PCINT0_vect_num 6 +-#define PCINT0_vect _VECTOR(6) +- +-/* Pin Change Interrupt 1 */ +-#define PCINT1_vect_num 7 +-#define PCINT1_vect _VECTOR(7) +- +-/* Watchdog Timeout Interrupt */ +-#define WDT_vect_num 8 +-#define WDT_vect _VECTOR(8) +- +-/* Wakeup timer overflow */ +-#define WAKE_UP_vect_num 9 +-#define WAKE_UP_vect _VECTOR(9) +- +-/* Timer/Counter 1 Compare Match */ +-#define TIM1_COMP_vect_num 10 +-#define TIM1_COMP_vect _VECTOR(10) +- +-/* Timer/Counter 1 Overflow */ +-#define TIM1_OVF_vect_num 11 +-#define TIM1_OVF_vect _VECTOR(11) +- +-/* Timer/Counter0 Compare A Match */ +-#define TIM0_COMPA_vect_num 12 +-#define TIM0_COMPA_vect _VECTOR(12) +- +-/* Timer/Counter0 Compare B Match */ +-#define TIM0_COMPB_vect_num 13 +-#define TIM0_COMPB_vect _VECTOR(13) +- +-/* Timer/Counter0 Overflow */ +-#define TIM0_OVF_vect_num 14 +-#define TIM0_OVF_vect _VECTOR(14) +- +-/* Two-Wire Bus Connect/Disconnect */ +-#define TWI_BUS_CD_vect_num 15 +-#define TWI_BUS_CD_vect _VECTOR(15) +- +-/* Two-Wire Serial Interface */ +-#define TWI_vect_num 16 +-#define TWI_vect _VECTOR(16) +- +-/* Voltage ADC Conversion Complete */ +-#define VADC_vect_num 17 +-#define VADC_vect _VECTOR(17) +- +-/* Coulomb Counter ADC Conversion Complete */ +-#define CCADC_CONV_vect_num 18 +-#define CCADC_CONV_vect _VECTOR(18) +- +-/* Coloumb Counter ADC Regular Current */ +-#define CCADC_REG_CUR_vect_num 19 +-#define CCADC_REG_CUR_vect _VECTOR(19) +- +-/* Coloumb Counter ADC Accumulator */ +-#define CCADC_ACC_vect_num 20 +-#define CCADC_ACC_vect _VECTOR(20) +- +-/* EEPROM Ready */ +-#define EE_READY_vect_num 21 +-#define EE_READY_vect _VECTOR(21) +- +-/* Store Program Memory Ready */ +-#define SPM_READY_vect_num 22 +-#define SPM_READY_vect _VECTOR(22) +- +-#define _VECTORS_SIZE 92 +- +-/* Constants */ +-#define SPM_PAGESIZE 128 +-#define RAMEND 0x8FF +-#define XRAMEND RAMEND +-#define E2END 0x1FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x9FFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 2 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL (unsigned char)~_BV(0) +-#define FUSE_SUT0 (unsigned char)~_BV(1) +-#define FUSE_SUT1 (unsigned char)~_BV(2) +-#define FUSE_BOOTRST (unsigned char)~_BV(3) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(4) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(5) +-#define FUSE_EESAVE (unsigned char)~_BV(6) +-#define FUSE_WDTON (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_SUT0 & FUSE_BOOTSZ0 & FUSE_BOOTSZ1) +- +-/* High Fuse Byte */ +-#define FUSE_JTAGEN (unsigned char)~_BV(0) +-#define FUSE_OCDEN (unsigned char)~_BV(1) +-#define HFUSE_DEFAULT (FUSE_JTAGEN) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x95 +-#define SIGNATURE_2 0x07 +- +- +-#endif /* _AVR_IOM406_H_ */ ++/* Copyright (c) 2006, Pieter Conradie ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom406.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* avr/iom406.h - definitions for ATmega406 */ ++ ++#ifndef _AVR_IOM406_H_ ++#define _AVR_IOM406_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom406.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* Reserved [0x06..0x07] */ ++ ++#define PORTC _SFR_IO8(0x08) ++#define PC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD1 1 ++#define DDD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PD1 1 ++#define PD0 0 ++ ++/* Reserved [0x0C..0x14] */ ++ ++/* Timer/Counter0 Interrupt Flag Register */ ++#define TIFR0 _SFR_IO8(0x15) ++#define OCF0B 2 ++#define OCF0A 1 ++#define TOV0 0 ++ ++/* Timer/Counter1 Interrupt Flag Register */ ++#define TIFR1 _SFR_IO8(0x16) ++#define OCF1A 1 ++#define TOV1 0 ++ ++/* Reserved [0x17..0x1A] */ ++ ++/* Pin Change Interrupt Control Register */ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF1 1 ++#define PCIF0 0 ++ ++/* External Interrupt Flag Register */ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF3 3 ++#define INTF2 2 ++#define INTF1 1 ++#define INTF0 0 ++ ++/* External Interrupt MaSK register */ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT3 3 ++#define INT2 2 ++#define INT1 1 ++#define INT0 0 ++ ++/* General Purpose I/O Register 0 */ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1F) ++#define EEPM1 5 ++#define EEPM0 4 ++#define EERIE 3 ++#define EEMPE 2 ++#define EEPE 1 ++#define EERE 0 ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x20) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO16(0x21) ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++/* 6-char sequence denoting where to find the EEPROM registers in memory space. ++ Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM ++ subroutines. ++ First two letters: EECR address. ++ Second two letters: EEDR address. ++ Last two letters: EEAR address. */ ++#define __EEPROM_REG_LOCATIONS__ 1F2021 ++ ++/* General Timer/Counter Control Register */ ++#define GTCCR _SFR_IO8(0x23) ++#define TSM 7 ++#define PSRSYNC 0 ++ ++/* Timer/Counter Control Register A */ ++#define TCCR0A _SFR_IO8(0x24) ++#define COM0A1 7 ++#define COM0A0 6 ++#define COM0B1 5 ++#define COM0B0 4 ++#define WGM01 1 ++#define WGM00 0 ++ ++/* Timer/Counter Control Register B */ ++#define TCCR0B _SFR_IO8(0x25) ++#define FOC0A 7 ++#define FOC0B 6 ++#define WGM02 3 ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* Timer/Counter 0 */ ++#define TCNT0 _SFR_IO8(0x26) ++ ++/* Output Compare Register A */ ++#define OCR0A _SFR_IO8(0x27) ++ ++/* Output Compare Register B */ ++#define OCR0B _SFR_IO8(0x28) ++ ++/* Reserved [0x29] */ ++ ++/* General Purpose I/O Register 1 */ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++/* General Purpose I/O Register 2 */ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++/* Reserved [0x2C..0x30] */ ++ ++/* On-chip Debug Register */ ++#define OCDR _SFR_IO8(0x31) ++ ++/* Reserved [0x32] */ ++ ++/* Sleep Mode Control Register */ ++#define SMCR _SFR_IO8(0x33) ++#define SM2 3 ++#define SM1 2 ++#define SM0 1 ++#define SE 0 ++ ++/* MCU Status Register */ ++#define MCUSR _SFR_IO8(0x34) ++#define JTRF 4 ++#define WDRF 3 ++#define BODRF 2 ++#define EXTRF 1 ++#define PORF 0 ++ ++/* MCU general Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++#define JTD 7 ++#define PUD 4 ++#define IVSEL 1 ++#define IVCE 0 ++ ++/* Reserved [0x36] */ ++ ++/* Store Program Memory Control and Status Register */ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMIE 7 ++#define RWWSB 6 ++#define SIGRD 5 ++#define RWWSRE 4 ++#define BLBSET 3 ++#define PGWRT 2 ++#define PGERS 1 ++#define SPMEN 0 ++ ++/* Reserved [0x36..0x3C] */ ++ ++/* 0x3D..0x3E SP */ ++ ++/* 0x3F SREG */ ++ ++/* Extended I/O registers */ ++ ++/* Watchdog Timer Control Register */ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDIF 7 ++#define WDIE 6 ++#define WDP3 5 ++#define WDCE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* Reserved [0x61] */ ++ ++/* Wake-up Timer Control and Status Register */ ++#define WUTCSR _SFR_MEM8(0x62) ++#define WUTIF 7 ++#define WUTIE 6 ++#define WUTCF 5 ++#define WUTR 4 ++#define WUTE 3 ++#define WUTP2 2 ++#define WUTP1 1 ++#define WUTP0 0 ++ ++/* Reserved [0x63] */ ++ ++/* Power Reduction Register 0 */ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRTWI 3 ++#define PRTIM1 2 ++#define PRTIM0 1 ++#define PRVADC 0 ++ ++/* Reserved [0x65] */ ++ ++/* Fast Oscillator Calibration Register */ ++#define FOSCCAL _SFR_MEM8(0x66) ++ ++/* Reserved [0x67] */ ++ ++/* Pin Change Interrupt Control Register */ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE1 1 ++#define PCIE0 0 ++ ++/* External Interrupt Control Register A */ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC31 7 ++#define ISC30 6 ++#define ISC21 5 ++#define ISC20 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* Reserved [0x6A] */ ++ ++/* Pin Change Mask Register 0 */ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT7 7 ++#define PCINT6 6 ++#define PCINT5 5 ++#define PCINT4 4 ++#define PCINT3 3 ++#define PCINT2 2 ++#define PCINT1 1 ++#define PCINT0 0 ++ ++/* Pin Change Mask Register 1 */ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT15 7 ++#define PCINT14 6 ++#define PCINT13 5 ++#define PCINT12 4 ++#define PCINT11 3 ++#define PCINT10 2 ++#define PCINT9 1 ++#define PCINT8 0 ++ ++/* Reserved [0x6D] */ ++ ++/* Timer/Counter Interrupt MaSK register 0 */ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define OCIE0B 2 ++#define OCIE0A 1 ++#define TOIE0 0 ++ ++/* Timer/Counter Interrupt MaSK register 1 */ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define OCIE1A 1 ++#define TOIE1 0 ++ ++/* Reserved [0x70..0x77] */ ++ ++/* V-ADC Data Register */ ++#define VADC _SFR_MEM16(0x78) ++#define VADCL _SFR_MEM8(0x78) ++#define VADCH _SFR_MEM8(0x79) ++ ++/* V-ADC Control and Status Register */ ++#define VADCSR _SFR_MEM8(0x7A) ++#define VADEN 3 ++#define VADSC 2 ++#define VADCCIF 1 ++#define VADCCIE 0 ++ ++/* Reserved [0x7B] */ ++ ++/* V-ADC Multiplexer Selection Register */ ++#define VADMUX _SFR_MEM8(0x7C) ++#define VADMUX3 3 ++#define VADMUX2 2 ++#define VADMUX1 1 ++#define VADMUX0 0 ++ ++/* Reserved [0x7D] */ ++ ++/* Digital Input Disable Register 0 */ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define VADC3D 3 ++#define VADC2D 2 ++#define VADC1D 1 ++#define VADC0D 0 ++ ++/* Reserved [0x82..0x83] */ ++ ++/* Timer/Counter 1 Control and Status Register */ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CTC1 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* Reserved [0x82..0x83] */ ++ ++/* Timer/Counter 1 */ ++#define TCNT1 _SFR_MEM16(0x84) ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Reserved [0x86..0x87] */ ++ ++/* Timer/Counter1 Output Compare Register A */ ++#define OCR1A _SFR_MEM16(0x88) ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Reserved [0x8A..0xB7] */ ++ ++/* 2-wire Serial Interface Bit Rate Register */ ++#define TWBR _SFR_MEM8(0xB8) ++ ++/* 2-wire Serial Interface Status Register */ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWS7 7 ++#define TWS6 6 ++#define TWS5 5 ++#define TWS4 4 ++#define TWS3 3 ++#define TWPS1 1 ++#define TWPS0 0 ++ ++/* 2-wire Serial Interface Address Register */ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWA6 7 ++#define TWA5 6 ++#define TWA4 5 ++#define TWA3 4 ++#define TWA2 3 ++#define TWA1 2 ++#define TWA0 1 ++#define TWGCE 0 ++ ++/* 2-wire Serial Interface Data Register */ ++#define TWDR _SFR_MEM8(0xBB) ++ ++/* 2-wire Serial Interface Control Register */ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWINT 7 ++#define TWEA 6 ++#define TWSTA 5 ++#define TWSTO 4 ++#define TWWC 3 ++#define TWEN 2 ++#define TWIE 0 ++ ++/* 2-wire Serial (Slave) Address Mask Register */ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM6 7 ++#define TWAM5 6 ++#define TWAM4 5 ++#define TWAM3 4 ++#define TWAM2 3 ++#define TWAM1 2 ++#define TWAM0 1 ++ ++/* 2-wire Serial Bus Control and Status Register */ ++#define TWBCSR _SFR_MEM8(0xBE) ++#define TWBCIF 7 ++#define TWBCIE 6 ++#define TWBDT1 2 ++#define TWBDT0 1 ++#define TWBCIP 0 ++ ++/* Reserved [0xBF] */ ++ ++/* Clock Control Status Register */ ++#define CCSR _SFR_MEM8(0xC0) ++#define XOE 1 ++#define ACS 0 ++ ++/* Reserved [0xC1..0xCF] */ ++ ++/* Bandgap Calibration C Register */ ++#define BGCCR _SFR_MEM8(0xD0) ++#define BGEN 7 ++#define BGCC5 5 ++#define BGCC4 4 ++#define BGCC3 3 ++#define BGCC2 2 ++#define BGCC1 1 ++#define BGCC0 0 ++ ++/* Bandgap Calibration R Register */ ++#define BGCRR _SFR_MEM8(0xD1) ++#define BGCR7 7 ++#define BGCR6 6 ++#define BGCR5 5 ++#define BGCR4 4 ++#define BGCR3 3 ++#define BGCR2 2 ++#define BGCR1 1 ++#define BGCR0 0 ++ ++/* Reserved [0xD2..0xDF] */ ++ ++/* CC-ADC Accumulate Current */ ++/* TODO: Add _SFR_MEM32 */ ++/* #define CADAC _SFR_MEM32(0xE0) */ ++#define CADAC0 _SFR_MEM8(0xE0) ++#define CADAC1 _SFR_MEM8(0xE1) ++#define CADAC2 _SFR_MEM8(0xE2) ++#define CADAC3 _SFR_MEM8(0xE3) ++ ++/* CC-ADC Control and Status Register A */ ++#define CADCSRA _SFR_MEM8(0xE4) ++#define CADEN 7 ++#define CADUB 5 ++#define CADAS1 4 ++#define CADAS0 3 ++#define CADSI1 2 ++#define CADSI0 1 ++#define CADSE 0 ++ ++/* CC-ADC Control and Status Register B */ ++#define CADCSRB _SFR_MEM8(0xE5) ++#define CADACIE 6 ++#define CADRCIE 5 ++#define CADICIE 4 ++#define CADACIF 2 ++#define CADRCIF 1 ++#define CADICIF 0 ++ ++/* CC-ADC Regular Charge Current */ ++#define CADRCC _SFR_MEM8(0xE6) ++ ++/* CC-ADC Regular Discharge Current */ ++#define CADRDC _SFR_MEM8(0xE7) ++ ++/* CC-ADC Instantaneous Current */ ++#define CADIC _SFR_MEM16(0xE8) ++#define CADICL _SFR_MEM8(0xE8) ++#define CADICH _SFR_MEM8(0xE9) ++ ++/* Reserved [0xEA..0xEF] */ ++ ++/* FET Control and Status Register */ ++#define FCSR _SFR_MEM8(0xF0) ++#define PWMOC 5 ++#define PWMOPC 4 ++#define CPS 3 ++#define DFE 2 ++#define CFE 1 ++#define PFD 0 ++ ++/* Cell Balancing Control Register */ ++#define CBCR _SFR_MEM8(0xF1) ++#define CBE4 3 ++#define CBE3 2 ++#define CBE2 1 ++#define CBE1 0 ++ ++/* Battery Protection Interrupt Register */ ++#define BPIR _SFR_MEM8(0xF2) ++#define DUVIF 7 ++#define COCIF 6 ++#define DOCIF 5 ++#define SCIF 4 ++#define DUVIE 3 ++#define COCIE 2 ++#define DOCIE 1 ++#define SCIE 0 ++ ++/* Battery Protection Deep Under Voltage Register */ ++#define BPDUV _SFR_MEM8(0xF3) ++#define DUVT1 5 ++#define DUVT0 4 ++#define DUDL3 3 ++#define DUDL2 2 ++#define DUDL1 1 ++#define DUDL0 0 ++ ++/* Battery Protection Short-circuit Detection Level Register */ ++#define BPSCD _SFR_MEM8(0xF4) ++#define SCDL3 3 ++#define SCDL2 2 ++#define SCDL1 1 ++#define SCDL0 0 ++ ++/* Battery Protection Over-current Detection Level Register */ ++#define BPOCD _SFR_MEM8(0xF5) ++#define DCDL3 7 ++#define DCDL2 6 ++#define DCDL1 5 ++#define DCDL0 4 ++#define CCDL3 3 ++#define CCDL2 2 ++#define CCDL1 1 ++#define CCDL0 0 ++ ++/* Current Battery Protection Timing Register */ ++#define CBPTR _SFR_MEM8(0xF6) ++#define SCPT3 7 ++#define SCPT2 6 ++#define SCPT1 5 ++#define SCPT0 4 ++#define OCPT3 3 ++#define OCPT2 2 ++#define OCPT1 1 ++#define OCPT0 0 ++ ++/* Battery Protection Control Register */ ++#define BPCR _SFR_MEM8(0xF7) ++#define DUVD 3 ++#define SCD 2 ++#define DCD 1 ++#define CCD 0 ++ ++/* Battery Protection Parameter Lock Register */ ++#define BPPLR _SFR_MEM8(0xF8) ++#define BPPLE 1 ++#define BPPL 0 ++ ++/* Reserved [0xF9..0xFF] */ ++ ++/* Interrupt vectors */ ++ ++/* Battery Protection Interrupt */ ++#define BPINT_vect_num 1 ++#define BPINT_vect _VECTOR(1) ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 2 ++#define INT0_vect _VECTOR(2) ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect_num 3 ++#define INT1_vect _VECTOR(3) ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect_num 4 ++#define INT2_vect _VECTOR(4) ++ ++/* External Interrupt Request 3 */ ++#define INT3_vect_num 5 ++#define INT3_vect _VECTOR(5) ++ ++/* Pin Change Interrupt 0 */ ++#define PCINT0_vect_num 6 ++#define PCINT0_vect _VECTOR(6) ++ ++/* Pin Change Interrupt 1 */ ++#define PCINT1_vect_num 7 ++#define PCINT1_vect _VECTOR(7) ++ ++/* Watchdog Timeout Interrupt */ ++#define WDT_vect_num 8 ++#define WDT_vect _VECTOR(8) ++ ++/* Wakeup timer overflow */ ++#define WAKE_UP_vect_num 9 ++#define WAKE_UP_vect _VECTOR(9) ++ ++/* Timer/Counter 1 Compare Match */ ++#define TIM1_COMP_vect_num 10 ++#define TIM1_COMP_vect _VECTOR(10) ++ ++/* Timer/Counter 1 Overflow */ ++#define TIM1_OVF_vect_num 11 ++#define TIM1_OVF_vect _VECTOR(11) ++ ++/* Timer/Counter0 Compare A Match */ ++#define TIM0_COMPA_vect_num 12 ++#define TIM0_COMPA_vect _VECTOR(12) ++ ++/* Timer/Counter0 Compare B Match */ ++#define TIM0_COMPB_vect_num 13 ++#define TIM0_COMPB_vect _VECTOR(13) ++ ++/* Timer/Counter0 Overflow */ ++#define TIM0_OVF_vect_num 14 ++#define TIM0_OVF_vect _VECTOR(14) ++ ++/* Two-Wire Bus Connect/Disconnect */ ++#define TWI_BUS_CD_vect_num 15 ++#define TWI_BUS_CD_vect _VECTOR(15) ++ ++/* Two-Wire Serial Interface */ ++#define TWI_vect_num 16 ++#define TWI_vect _VECTOR(16) ++ ++/* Voltage ADC Conversion Complete */ ++#define VADC_vect_num 17 ++#define VADC_vect _VECTOR(17) ++ ++/* Coulomb Counter ADC Conversion Complete */ ++#define CCADC_CONV_vect_num 18 ++#define CCADC_CONV_vect _VECTOR(18) ++ ++/* Coloumb Counter ADC Regular Current */ ++#define CCADC_REG_CUR_vect_num 19 ++#define CCADC_REG_CUR_vect _VECTOR(19) ++ ++/* Coloumb Counter ADC Accumulator */ ++#define CCADC_ACC_vect_num 20 ++#define CCADC_ACC_vect _VECTOR(20) ++ ++/* EEPROM Ready */ ++#define EE_READY_vect_num 21 ++#define EE_READY_vect _VECTOR(21) ++ ++/* Store Program Memory Ready */ ++#define SPM_READY_vect_num 22 ++#define SPM_READY_vect _VECTOR(22) ++ ++#define _VECTORS_SIZE 92 ++ ++/* Constants */ ++#define SPM_PAGESIZE 128 ++#define RAMSTART 0x100 ++#define RAMEND 0x8FF ++#define XRAMEND RAMEND ++#define E2END 0x1FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x9FFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 2 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL (unsigned char)~_BV(0) ++#define FUSE_SUT0 (unsigned char)~_BV(1) ++#define FUSE_SUT1 (unsigned char)~_BV(2) ++#define FUSE_BOOTRST (unsigned char)~_BV(3) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(4) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(5) ++#define FUSE_EESAVE (unsigned char)~_BV(6) ++#define FUSE_WDTON (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_SUT0 & FUSE_BOOTSZ0 & FUSE_BOOTSZ1) ++ ++/* High Fuse Byte */ ++#define FUSE_JTAGEN (unsigned char)~_BV(0) ++#define FUSE_OCDEN (unsigned char)~_BV(1) ++#define HFUSE_DEFAULT (FUSE_JTAGEN) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x07 ++ ++ ++#endif /* _AVR_IOM406_H_ */ +diff --git a/include/avr/iom48.h b/include/avr/iom48.h +index e204388..fe65504 100644 +--- a/include/avr/iom48.h ++++ b/include/avr/iom48.h +@@ -1,88 +1,88 @@ +-/* Copyright (c) 2004, Theodore A. Roth +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom48.h 2115 2010-04-05 23:19:53Z arcanum $ */ +- +-#ifndef _AVR_IOM48_H_ +-#define _AVR_IOM48_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 64 +-#define RAMSTART (0x100) +-#define RAMEND 0x2FF +-#define XRAMEND RAMEND +-#define E2END 0xFF +-#define E2PAGESIZE 4 +-#define FLASHEND 0xFFF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self Programming Enable */ +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x92 +-#define SIGNATURE_2 0x05 +- +- +-#endif /* _AVR_IOM48_H_ */ ++/* Copyright (c) 2004, Theodore A. Roth ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom48.h 2115 2010-04-05 23:19:53Z arcanum $ */ ++ ++#ifndef _AVR_IOM48_H_ ++#define _AVR_IOM48_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 64 ++#define RAMSTART (0x100) ++#define RAMEND 0x2FF ++#define XRAMEND RAMEND ++#define E2END 0xFF ++#define E2PAGESIZE 4 ++#define FLASHEND 0xFFF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self Programming Enable */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x92 ++#define SIGNATURE_2 0x05 ++ ++ ++#endif /* _AVR_IOM48_H_ */ diff --git a/include/avr/iom48a.h b/include/avr/iom48a.h new file mode 100644 -index 0000000..d5284a6 +index 0000000..c0c4a19 --- /dev/null +++ b/include/avr/iom48a.h @@ -0,0 +1,34 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2011 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+#include "iom48.h" ++/***************************************************************************** ++ * ++ * Copyright (C) 2011 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++#include "iom48.h" +diff --git a/include/avr/iom48p.h b/include/avr/iom48p.h +index 8f01df0..9ea0b9f 100644 +--- a/include/avr/iom48p.h ++++ b/include/avr/iom48p.h +@@ -1,919 +1,921 @@ +-/* Copyright (c) 2007 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. +-*/ +- +-/* $Id: iom48p.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* avr/iom48p.h - definitions for ATmega48P. */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom48p.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_IOM48P_H_ +-#define _AVR_IOM48P_H_ 1 +- +-/* Registers and associated bit numbers */ +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC3 3 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC3 3 +-#define PORTC4 4 +-#define PORTC5 5 +-#define PORTC6 6 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define TIFR2 _SFR_IO8(0x17) +-#define TOV2 0 +-#define OCF2A 1 +-#define OCF2B 2 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +-#define PCIF1 1 +-#define PCIF2 2 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-/* Only valid for ATmega88P-168P-328P */ +-/* EEARH _SFR_IO8(0x22) */ +- +-#define EEPROM_REG_LOCATIONS 1F2021 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSRSYNC 0 +-#define PSRASY 1 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define OCR0A _SFR_IO8(0x27) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define OCR0B _SFR_IO8(0x28) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x35) +-#define PUD 4 +-#define BODSE 5 +-#define BODS 6 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SELFPRGEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM1 3 +-#define PRTIM0 5 +-#define PRTIM2 6 +-#define PRTWI 7 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +-#define PCIE1 1 +-#define PCIE2 2 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +- +-#define PCMSK2 _SFR_MEM8(0x6D) +-#define PCINT16 0 +-#define PCINT17 1 +-#define PCINT18 2 +-#define PCINT19 3 +-#define PCINT20 4 +-#define PCINT21 5 +-#define PCINT22 6 +-#define PCINT23 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define TIMSK2 _SFR_MEM8(0x70) +-#define TOIE2 0 +-#define OCIE2A 1 +-#define OCIE2B 2 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +- +-#define ADCL _SFR_MEM8(0x78) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_MEM8(0x79) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ACME 6 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define TCCR2A _SFR_MEM8(0xB0) +-#define WGM20 0 +-#define WGM21 1 +-#define COM2B0 4 +-#define COM2B1 5 +-#define COM2A0 6 +-#define COM2A1 7 +- +-#define TCCR2B _SFR_MEM8(0xB1) +-#define CS20 0 +-#define CS21 1 +-#define CS22 2 +-#define WGM22 3 +-#define FOC2B 6 +-#define FOC2A 7 +- +-#define TCNT2 _SFR_MEM8(0xB2) +-#define TCNT2_0 0 +-#define TCNT2_1 1 +-#define TCNT2_2 2 +-#define TCNT2_3 3 +-#define TCNT2_4 4 +-#define TCNT2_5 5 +-#define TCNT2_6 6 +-#define TCNT2_7 7 +- +-#define OCR2A _SFR_MEM8(0xB3) +-#define OCR2_0 0 +-#define OCR2_1 1 +-#define OCR2_2 2 +-#define OCR2_3 3 +-#define OCR2_4 4 +-#define OCR2_5 5 +-#define OCR2_6 6 +-#define OCR2_7 7 +- +-#define OCR2B _SFR_MEM8(0xB4) +-#define OCR2_0 0 +-#define OCR2_1 1 +-#define OCR2_2 2 +-#define OCR2_3 3 +-#define OCR2_4 4 +-#define OCR2_5 5 +-#define OCR2_6 6 +-#define OCR2_7 7 +- +-#define ASSR _SFR_MEM8(0xB6) +-#define TCR2BUB 0 +-#define TCR2AUB 1 +-#define OCR2BUB 2 +-#define OCR2AUB 3 +-#define TCN2UB 4 +-#define AS2 5 +-#define EXCLK 6 +- +-#define TWBR _SFR_MEM8(0xB8) +-#define TWBR0 0 +-#define TWBR1 1 +-#define TWBR2 2 +-#define TWBR3 3 +-#define TWBR4 4 +-#define TWBR5 5 +-#define TWBR6 6 +-#define TWBR7 7 +- +-#define TWSR _SFR_MEM8(0xB9) +-#define TWPS0 0 +-#define TWPS1 1 +-#define TWS3 3 +-#define TWS4 4 +-#define TWS5 5 +-#define TWS6 6 +-#define TWS7 7 +- +-#define TWAR _SFR_MEM8(0xBA) +-#define TWGCE 0 +-#define TWA0 1 +-#define TWA1 2 +-#define TWA2 3 +-#define TWA3 4 +-#define TWA4 5 +-#define TWA5 6 +-#define TWA6 7 +- +-#define TWDR _SFR_MEM8(0xBB) +-#define TWD0 0 +-#define TWD1 1 +-#define TWD2 2 +-#define TWD3 3 +-#define TWD4 4 +-#define TWD5 5 +-#define TWD6 6 +-#define TWD7 7 +- +-#define TWCR _SFR_MEM8(0xBC) +-#define TWIE 0 +-#define TWEN 2 +-#define TWWC 3 +-#define TWSTO 4 +-#define TWSTA 5 +-#define TWEA 6 +-#define TWINT 7 +- +-#define TWAMR _SFR_MEM8(0xBD) +-#define TWAM0 0 +-#define TWAM1 1 +-#define TWAM2 2 +-#define TWAM3 3 +-#define TWAM4 4 +-#define TWAM5 5 +-#define TWAM6 6 +- +-#define UCSR0A _SFR_MEM8(0xC0) +-#define MPCM0 0 +-#define U2X0 1 +-#define UPE0 2 +-#define DOR0 3 +-#define FE0 4 +-#define UDRE0 5 +-#define TXC0 6 +-#define RXC0 7 +- +-#define UCSR0B _SFR_MEM8(0xC1) +-#define TXB80 0 +-#define RXB80 1 +-#define UCSZ02 2 +-#define TXEN0 3 +-#define RXEN0 4 +-#define UDRIE0 5 +-#define TXCIE0 6 +-#define RXCIE0 7 +- +-#define UCSR0C _SFR_MEM8(0xC2) +-#define UCPOL0 0 +-#define UCSZ00 1 +-#define UCPHA0 1 +-#define UCSZ01 2 +-#define UDORD0 2 +-#define USBS0 3 +-#define UPM00 4 +-#define UPM01 5 +-#define UMSEL00 6 +-#define UMSEL01 7 +- +-#define UBRR0 _SFR_MEM16(0xC4) +- +-#define UBRR0L _SFR_MEM8(0xC4) +-#define UBRR0_0 0 +-#define UBRR0_1 1 +-#define UBRR0_2 2 +-#define UBRR0_3 3 +-#define UBRR0_4 4 +-#define UBRR0_5 5 +-#define UBRR0_6 6 +-#define UBRR0_7 7 +- +-#define UBRR0H _SFR_MEM8(0xC5) +-#define UBRR0_8 0 +-#define UBRR0_9 1 +-#define UBRR0_10 2 +-#define UBRR0_11 3 +- +-#define UDR0 _SFR_MEM8(0xC6) +-#define UDR0_0 0 +-#define UDR0_1 1 +-#define UDR0_2 2 +-#define UDR0_3 3 +-#define UDR0_4 4 +-#define UDR0_5 5 +-#define UDR0_6 6 +-#define UDR0_7 7 +- +- +- +-/* Interrupt Vectors */ +-/* Interrupt Vector 0 is the reset vector. */ +- +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +- +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ +- +-#define PCINT0_vect_num 3 +-#define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ +- +-#define PCINT1_vect_num 4 +-#define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */ +- +-#define PCINT2_vect_num 5 +-#define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */ +- +-#define WDT_vect_num 6 +-#define WDT_vect _VECTOR(6) /* Watchdog Time-out Interrupt */ +- +-#define TIMER2_COMPA_vect_num 7 +-#define TIMER2_COMPA_vect _VECTOR(7) /* Timer/Counter2 Compare Match A */ +- +-#define TIMER2_COMPB_vect_num 8 +-#define TIMER2_COMPB_vect _VECTOR(8) /* Timer/Counter2 Compare Match A */ +- +-#define TIMER2_OVF_vect_num 9 +-#define TIMER2_OVF_vect _VECTOR(9) /* Timer/Counter2 Overflow */ +- +-#define TIMER1_CAPT_vect_num 10 +-#define TIMER1_CAPT_vect _VECTOR(10) /* Timer/Counter1 Capture Event */ +- +-#define TIMER1_COMPA_vect_num 11 +-#define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */ +- +-#define TIMER1_COMPB_vect_num 12 +-#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */ +- +-#define TIMER1_OVF_vect_num 13 +-#define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */ +- +-#define TIMER0_COMPA_vect_num 14 +-#define TIMER0_COMPA_vect _VECTOR(14) /* TimerCounter0 Compare Match A */ +- +-#define TIMER0_COMPB_vect_num 15 +-#define TIMER0_COMPB_vect _VECTOR(15) /* TimerCounter0 Compare Match B */ +- +-#define TIMER0_OVF_vect_num 16 +-#define TIMER0_OVF_vect _VECTOR(16) /* Timer/Couner0 Overflow */ +- +-#define SPI_STC_vect_num 17 +-#define SPI_STC_vect _VECTOR(17) /* SPI Serial Transfer Complete */ +- +-#define USART_RX_vect_num 18 +-#define USART_RX_vect _VECTOR(18) /* USART Rx Complete */ +- +-#define USART_UDRE_vect_num 19 +-#define USART_UDRE_vect _VECTOR(19) /* USART, Data Register Empty */ +- +-#define USART_TX_vect_num 20 +-#define USART_TX_vect _VECTOR(20) /* USART Tx Complete */ +- +-#define ADC_vect_num 21 +-#define ADC_vect _VECTOR(21) /* ADC Conversion Complete */ +- +-#define EE_READY_vect_num 22 +-#define EE_READY_vect _VECTOR(22) /* EEPROM Ready */ +- +-#define ANALOG_COMP_vect_num 23 +-#define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */ +- +-#define TWI_vect_num 24 +-#define TWI_vect _VECTOR(24) /* Two-wire Serial Interface */ +- +-#define SPM_READY_vect_num 25 +-#define SPM_READY_vect _VECTOR(25) /* Store Program Memory Read */ +- +-#define _VECTORS_SIZE (26 * 2) +- +- +- +-/* Constants */ +-#define SPM_PAGESIZE 64 +-#define RAMSTART (0x100) +-#define RAMEND 0x2FF /* Last On-Chip SRAM Location */ +-#define XRAMSIZE 0 +-#define XRAMEND RAMEND +-#define E2END 0xFF +-#define E2PAGESIZE 4 +-#define FLASHEND 0xFFF +- +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self Programming Enable */ +-#define EFUSE_DEFAULT (0xFF) +- +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x92 +-#define SIGNATURE_2 0x0A +- +- +-#endif /* _AVR_IOM48P_H_ */ ++/* Copyright (c) 2007 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++/* $Id: iom48p.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* avr/iom48p.h - definitions for ATmega48P. */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom48p.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_IOM48P_H_ ++#define _AVR_IOM48P_H_ 1 ++ ++/* Registers and associated bit numbers */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC3 3 ++#define PORTC4 4 ++#define PORTC5 5 ++#define PORTC6 6 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++/* Only valid for ATmega88P-168P-328P */ ++/* EEARH _SFR_IO8(0x22) */ ++ ++#define EEPROM_REG_LOCATIONS 1F2021 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define PSRASY 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define OCR0A _SFR_IO8(0x27) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define OCR0B _SFR_IO8(0x28) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SELFPRGEN 0 ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_MEM8(0x79) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++#define TCNT2_0 0 ++#define TCNT2_1 1 ++#define TCNT2_2 2 ++#define TCNT2_3 3 ++#define TCNT2_4 4 ++#define TCNT2_5 5 ++#define TCNT2_6 6 ++#define TCNT2_7 7 ++ ++#define OCR2A _SFR_MEM8(0xB3) ++#define OCR2_0 0 ++#define OCR2_1 1 ++#define OCR2_2 2 ++#define OCR2_3 3 ++#define OCR2_4 4 ++#define OCR2_5 5 ++#define OCR2_6 6 ++#define OCR2_7 7 ++ ++#define OCR2B _SFR_MEM8(0xB4) ++#define OCR2_0 0 ++#define OCR2_1 1 ++#define OCR2_2 2 ++#define OCR2_3 3 ++#define OCR2_4 4 ++#define OCR2_5 5 ++#define OCR2_6 6 ++#define OCR2_7 7 ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++ ++#define TWBR _SFR_MEM8(0xB8) ++#define TWBR0 0 ++#define TWBR1 1 ++#define TWBR2 2 ++#define TWBR3 3 ++#define TWBR4 4 ++#define TWBR5 5 ++#define TWBR6 6 ++#define TWBR7 7 ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++#define TWD0 0 ++#define TWD1 1 ++#define TWD2 2 ++#define TWD3 3 ++#define TWD4 4 ++#define TWD5 5 ++#define TWD6 6 ++#define TWD7 7 ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 0 ++#define TWAM1 1 ++#define TWAM2 2 ++#define TWAM3 3 ++#define TWAM4 4 ++#define TWAM5 5 ++#define TWAM6 6 ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCPHA0 1 ++#define UCSZ01 2 ++#define UDORD0 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0_0 0 ++#define UBRR0_1 1 ++#define UBRR0_2 2 ++#define UBRR0_3 3 ++#define UBRR0_4 4 ++#define UBRR0_5 5 ++#define UBRR0_6 6 ++#define UBRR0_7 7 ++ ++#define UBRR0H _SFR_MEM8(0xC5) ++#define UBRR0_8 0 ++#define UBRR0_9 1 ++#define UBRR0_10 2 ++#define UBRR0_11 3 ++ ++#define UDR0 _SFR_MEM8(0xC6) ++#define UDR0_0 0 ++#define UDR0_1 1 ++#define UDR0_2 2 ++#define UDR0_3 3 ++#define UDR0_4 4 ++#define UDR0_5 5 ++#define UDR0_6 6 ++#define UDR0_7 7 ++ ++ ++ ++/* Interrupt Vectors */ ++/* Interrupt Vector 0 is the reset vector. */ ++ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ ++ ++#define PCINT0_vect_num 3 ++#define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ ++ ++#define PCINT1_vect_num 4 ++#define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */ ++ ++#define PCINT2_vect_num 5 ++#define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */ ++ ++#define WDT_vect_num 6 ++#define WDT_vect _VECTOR(6) /* Watchdog Time-out Interrupt */ ++ ++#define TIMER2_COMPA_vect_num 7 ++#define TIMER2_COMPA_vect _VECTOR(7) /* Timer/Counter2 Compare Match A */ ++ ++#define TIMER2_COMPB_vect_num 8 ++#define TIMER2_COMPB_vect _VECTOR(8) /* Timer/Counter2 Compare Match A */ ++ ++#define TIMER2_OVF_vect_num 9 ++#define TIMER2_OVF_vect _VECTOR(9) /* Timer/Counter2 Overflow */ ++ ++#define TIMER1_CAPT_vect_num 10 ++#define TIMER1_CAPT_vect _VECTOR(10) /* Timer/Counter1 Capture Event */ ++ ++#define TIMER1_COMPA_vect_num 11 ++#define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */ ++ ++#define TIMER1_COMPB_vect_num 12 ++#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */ ++ ++#define TIMER1_OVF_vect_num 13 ++#define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */ ++ ++#define TIMER0_COMPA_vect_num 14 ++#define TIMER0_COMPA_vect _VECTOR(14) /* TimerCounter0 Compare Match A */ ++ ++#define TIMER0_COMPB_vect_num 15 ++#define TIMER0_COMPB_vect _VECTOR(15) /* TimerCounter0 Compare Match B */ ++ ++#define TIMER0_OVF_vect_num 16 ++#define TIMER0_OVF_vect _VECTOR(16) /* Timer/Couner0 Overflow */ ++ ++#define SPI_STC_vect_num 17 ++#define SPI_STC_vect _VECTOR(17) /* SPI Serial Transfer Complete */ ++ ++#define USART_RX_vect_num 18 ++#define USART_RX_vect _VECTOR(18) /* USART Rx Complete */ ++ ++#define USART_UDRE_vect_num 19 ++#define USART_UDRE_vect _VECTOR(19) /* USART, Data Register Empty */ ++ ++#define USART_TX_vect_num 20 ++#define USART_TX_vect _VECTOR(20) /* USART Tx Complete */ ++ ++#define ADC_vect_num 21 ++#define ADC_vect _VECTOR(21) /* ADC Conversion Complete */ ++ ++#define EE_READY_vect_num 22 ++#define EE_READY_vect _VECTOR(22) /* EEPROM Ready */ ++ ++#define ANALOG_COMP_vect_num 23 ++#define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */ ++ ++#define TWI_vect_num 24 ++#define TWI_vect _VECTOR(24) /* Two-wire Serial Interface */ ++ ++#define SPM_READY_vect_num 25 ++#define SPM_READY_vect _VECTOR(25) /* Store Program Memory Read */ ++ ++#define _VECTORS_SIZE (26 * 2) ++ ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE 64 ++#define RAMSTART (0x100) ++#define RAMEND 0x2FF /* Last On-Chip SRAM Location */ ++#define XRAMSIZE 0 ++#define XRAMEND RAMEND ++#define E2END 0xFF ++#define E2PAGESIZE 4 ++#define FLASHEND 0xFFF ++ ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self Programming Enable */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x92 ++#define SIGNATURE_2 0x0A ++ ++ ++#endif /* _AVR_IOM48P_H_ */ diff --git a/include/avr/iom48pa.h b/include/avr/iom48pa.h new file mode 100644 -index 0000000..4506d7b +index 0000000..ddb8f7d --- /dev/null +++ b/include/avr/iom48pa.h @@ -0,0 +1,763 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATMEGA48PA_H_INCLUDED -+#define _AVR_ATMEGA48PA_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iom48pa.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x06) -+#define PINC6 6 -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x07) -+#define DDRC6 6 -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x08) -+#define PORTC6 6 -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PIND _SFR_IO8(0x09) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0A) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x0B) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+/* Reserved [0x0C..0x14] */ -+ -+#define TIFR0 _SFR_IO8(0x15) -+#define TOV0 0 -+#define OCF0A 1 -+#define OCF0B 2 -+ -+#define TIFR1 _SFR_IO8(0x16) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define ICF1 5 -+ -+#define TIFR2 _SFR_IO8(0x17) -+#define TOV2 0 -+#define OCF2A 1 -+#define OCF2B 2 -+ -+/* Reserved [0x18..0x1A] */ -+ -+#define PCIFR _SFR_IO8(0x1B) -+#define PCIF0 0 -+#define PCIF1 1 -+#define PCIF2 2 -+ -+#define EIFR _SFR_IO8(0x1C) -+#define INTF0 0 -+#define INTF1 1 -+ -+#define EIMSK _SFR_IO8(0x1D) -+#define INT0 0 -+#define INT1 1 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEPE 1 -+#define EEMPE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+#define EEARL _SFR_IO8(0x21) -+ -+/* Reserved [0x22] */ -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSRSYNC 0 -+#define TSM 7 -+#define PSRASY 1 -+ -+#define TCCR0A _SFR_IO8(0x24) -+#define WGM00 0 -+#define WGM01 1 -+#define COM0B0 4 -+#define COM0B1 5 -+#define COM0A0 6 -+#define COM0A1 7 -+ -+#define TCCR0B _SFR_IO8(0x25) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define WGM02 3 -+#define FOC0B 6 -+#define FOC0A 7 -+ -+#define TCNT0 _SFR_IO8(0x26) -+ -+#define OCR0A _SFR_IO8(0x27) -+ -+#define OCR0B _SFR_IO8(0x28) -+ -+/* Reserved [0x29] */ -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+/* Reserved [0x2F] */ -+ -+#define ACSR _SFR_IO8(0x30) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACBG 6 -+#define ACD 7 -+ -+/* Reserved [0x31..0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define PUD 4 -+#define BODSE 5 -+#define BODS 6 -+ -+/* Reserved [0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SELFPRGEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+/* Reserved [0x38..0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCSR _SFR_MEM8(0x60) -+#define WDE 3 -+#define WDCE 4 -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDP3 5 -+#define WDIE 6 -+#define WDIF 7 -+ -+#define CLKPR _SFR_MEM8(0x61) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+#define CLKPCE 7 -+ -+/* Reserved [0x62..0x63] */ -+ -+#define PRR _SFR_MEM8(0x64) -+#define PRADC 0 -+#define PRUSART0 1 -+#define PRSPI 2 -+#define PRTIM1 3 -+#define PRTIM0 5 -+#define PRTIM2 6 -+#define PRTWI 7 -+ -+/* Reserved [0x65] */ -+ -+#define OSCCAL _SFR_MEM8(0x66) -+#define OSCCAL0 0 -+#define OSCCAL1 1 -+#define OSCCAL2 2 -+#define OSCCAL3 3 -+#define OSCCAL4 4 -+#define OSCCAL5 5 -+#define OSCCAL6 6 -+#define OSCCAL7 7 -+ -+/* Reserved [0x67] */ -+ -+#define PCICR _SFR_MEM8(0x68) -+#define PCIE0 0 -+#define PCIE1 1 -+#define PCIE2 2 -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+ -+/* Reserved [0x6A] */ -+ -+#define PCMSK0 _SFR_MEM8(0x6B) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6C) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+#define PCINT14 6 -+ -+#define PCMSK2 _SFR_MEM8(0x6D) -+#define PCINT16 0 -+#define PCINT17 1 -+#define PCINT18 2 -+#define PCINT19 3 -+#define PCINT20 4 -+#define PCINT21 5 -+#define PCINT22 6 -+#define PCINT23 7 -+ -+#define TIMSK0 _SFR_MEM8(0x6E) -+#define TOIE0 0 -+#define OCIE0A 1 -+#define OCIE0B 2 -+ -+#define TIMSK1 _SFR_MEM8(0x6F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define ICIE1 5 -+ -+#define TIMSK2 _SFR_MEM8(0x70) -+#define TOIE2 0 -+#define OCIE2A 1 -+#define OCIE2B 2 -+ -+/* Reserved [0x71..0x77] */ -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_MEM16(0x78) -+#endif -+#define ADCW _SFR_MEM16(0x78) -+ -+#define ADCL _SFR_MEM8(0x78) -+#define ADCH _SFR_MEM8(0x79) -+ -+#define ADCSRA _SFR_MEM8(0x7A) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADCSRB _SFR_MEM8(0x7B) -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+#define ACME 6 -+ -+#define ADMUX _SFR_MEM8(0x7C) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+/* Reserved [0x7D] */ -+ -+#define DIDR0 _SFR_MEM8(0x7E) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+ -+#define DIDR1 _SFR_MEM8(0x7F) -+#define AIN0D 0 -+#define AIN1D 1 -+ -+#define TCCR1A _SFR_MEM8(0x80) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR1B _SFR_MEM8(0x81) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1C _SFR_MEM8(0x82) -+#define FOC1B 6 -+#define FOC1A 7 -+ -+/* Reserved [0x83] */ -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x84) -+ -+#define TCNT1L _SFR_MEM8(0x84) -+#define TCNT1H _SFR_MEM8(0x85) -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x86) -+ -+#define ICR1L _SFR_MEM8(0x86) -+#define ICR1H _SFR_MEM8(0x87) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_MEM16(0x88) -+ -+#define OCR1AL _SFR_MEM8(0x88) -+#define OCR1AH _SFR_MEM8(0x89) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_MEM16(0x8A) -+ -+#define OCR1BL _SFR_MEM8(0x8A) -+#define OCR1BH _SFR_MEM8(0x8B) -+ -+/* Reserved [0x8C..0xAF] */ -+ -+#define TCCR2A _SFR_MEM8(0xB0) -+#define WGM20 0 -+#define WGM21 1 -+#define COM2B0 4 -+#define COM2B1 5 -+#define COM2A0 6 -+#define COM2A1 7 -+ -+#define TCCR2B _SFR_MEM8(0xB1) -+#define CS20 0 -+#define CS21 1 -+#define CS22 2 -+#define WGM22 3 -+#define FOC2B 6 -+#define FOC2A 7 -+ -+#define TCNT2 _SFR_MEM8(0xB2) -+ -+#define OCR2A _SFR_MEM8(0xB3) -+ -+#define OCR2B _SFR_MEM8(0xB4) -+ -+/* Reserved [0xB5] */ -+ -+#define ASSR _SFR_MEM8(0xB6) -+#define TCR2BUB 0 -+#define TCR2AUB 1 -+#define OCR2BUB 2 -+#define OCR2AUB 3 -+#define TCN2UB 4 -+#define AS2 5 -+#define EXCLK 6 -+ -+/* Reserved [0xB7] */ -+ -+#define TWBR _SFR_MEM8(0xB8) -+ -+#define TWSR _SFR_MEM8(0xB9) -+#define TWPS0 0 -+#define TWPS1 1 -+#define TWS3 3 -+#define TWS4 4 -+#define TWS5 5 -+#define TWS6 6 -+#define TWS7 7 -+ -+#define TWAR _SFR_MEM8(0xBA) -+#define TWGCE 0 -+#define TWA0 1 -+#define TWA1 2 -+#define TWA2 3 -+#define TWA3 4 -+#define TWA4 5 -+#define TWA5 6 -+#define TWA6 7 -+ -+#define TWDR _SFR_MEM8(0xBB) -+ -+#define TWCR _SFR_MEM8(0xBC) -+#define TWIE 0 -+#define TWEN 2 -+#define TWWC 3 -+#define TWSTO 4 -+#define TWSTA 5 -+#define TWEA 6 -+#define TWINT 7 -+ -+#define TWAMR _SFR_MEM8(0xBD) -+#define TWAM0 1 -+#define TWAM1 2 -+#define TWAM2 3 -+#define TWAM3 4 -+#define TWAM4 5 -+#define TWAM5 6 -+#define TWAM6 7 -+ -+/* Reserved [0xBE..0xBF] */ -+ -+#define UCSR0A _SFR_MEM8(0xC0) -+#define MPCM0 0 -+#define U2X0 1 -+#define UPE0 2 -+#define DOR0 3 -+#define FE0 4 -+#define UDRE0 5 -+#define TXC0 6 -+#define RXC0 7 -+ -+#define UCSR0B _SFR_MEM8(0xC1) -+#define TXB80 0 -+#define RXB80 1 -+#define UCSZ02 2 -+#define TXEN0 3 -+#define RXEN0 4 -+#define UDRIE0 5 -+#define TXCIE0 6 -+#define RXCIE0 7 -+ -+#define UCSR0C _SFR_MEM8(0xC2) -+#define UCPOL0 0 -+#define UCSZ00 1 -+#define UCSZ01 2 -+#define USBS0 3 -+#define UPM00 4 -+#define UPM01 5 -+#define UMSEL00 6 -+#define UMSEL01 7 -+ -+/* Reserved [0xC3] */ -+ -+/* Combine UBRR0L and UBRR0H */ -+#define UBRR0 _SFR_MEM16(0xC4) -+ -+#define UBRR0L _SFR_MEM8(0xC4) -+#define UBRR0H _SFR_MEM8(0xC5) -+ -+#define UDR0 _SFR_MEM8(0xC6) -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(3) -+#define PCINT0_vect_num 3 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT1_vect _VECTOR(4) -+#define PCINT1_vect_num 4 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT2_vect _VECTOR(5) -+#define PCINT2_vect_num 5 -+ -+/* Watchdog Time-out Interrupt */ -+#define WDT_vect _VECTOR(6) -+#define WDT_vect_num 6 -+ -+/* Timer/Counter2 Compare Match A */ -+#define TIMER2_COMPA_vect _VECTOR(7) -+#define TIMER2_COMPA_vect_num 7 -+ -+/* Timer/Counter2 Compare Match A */ -+#define TIMER2_COMPB_vect _VECTOR(8) -+#define TIMER2_COMPB_vect_num 8 -+ -+/* Timer/Counter2 Overflow */ -+#define TIMER2_OVF_vect _VECTOR(9) -+#define TIMER2_OVF_vect_num 9 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(10) -+#define TIMER1_CAPT_vect_num 10 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(11) -+#define TIMER1_COMPA_vect_num 11 -+ -+/* Timer/Counter1 Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(12) -+#define TIMER1_COMPB_vect_num 12 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(13) -+#define TIMER1_OVF_vect_num 13 -+ -+/* TimerCounter0 Compare Match A */ -+#define TIMER0_COMPA_vect _VECTOR(14) -+#define TIMER0_COMPA_vect_num 14 -+ -+/* TimerCounter0 Compare Match B */ -+#define TIMER0_COMPB_vect _VECTOR(15) -+#define TIMER0_COMPB_vect_num 15 -+ -+/* Timer/Couner0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(16) -+#define TIMER0_OVF_vect_num 16 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(17) -+#define SPI_STC_vect_num 17 -+ -+/* USART Rx Complete */ -+#define USART_RX_vect _VECTOR(18) -+#define USART_RX_vect_num 18 -+ -+/* USART, Data Register Empty */ -+#define USART_UDRE_vect _VECTOR(19) -+#define USART_UDRE_vect_num 19 -+ -+/* USART Tx Complete */ -+#define USART_TX_vect _VECTOR(20) -+#define USART_TX_vect_num 20 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(21) -+#define ADC_vect_num 21 -+ -+/* EEPROM Ready */ -+#define EE_READY_vect _VECTOR(22) -+#define EE_READY_vect_num 22 -+ -+/* Analog Comparator */ -+#define ANALOG_COMP_vect _VECTOR(23) -+#define ANALOG_COMP_vect_num 23 -+ -+/* Two-wire Serial Interface */ -+#define TWI_vect _VECTOR(24) -+#define TWI_vect_num 24 -+ -+/* Store Program Memory Read */ -+#define SPM_Ready_vect _VECTOR(25) -+#define SPM_Ready_vect_num 25 -+ -+#define _VECTORS_SIZE 52 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 64 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x0FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 512 -+#define RAMEND 0x02FF -+#define E2START 0 -+#define E2SIZE 256 -+#define E2PAGESIZE 4 -+#define E2END 0x00FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -+#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_DWEN (unsigned char)~_BV(6) -+#define FUSE_RSTDISBL (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_SELFPRGEN (unsigned char)~_BV(0) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x92 -+#define SIGNATURE_2 0x0A -+ -+ -+#endif /* #ifdef _AVR_ATMEGA48PA_H_INCLUDED */ -+ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATMEGA48PA_H_INCLUDED ++#define _AVR_ATMEGA48PA_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom48pa.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++/* Reserved [0x0C..0x14] */ ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++/* Reserved [0x18..0x1A] */ ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++#define EEARL _SFR_IO8(0x21) ++ ++/* Reserved [0x22] */ ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define TSM 7 ++#define PSRASY 1 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++ ++#define OCR0A _SFR_IO8(0x27) ++ ++#define OCR0B _SFR_IO8(0x28) ++ ++/* Reserved [0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++/* Reserved [0x31..0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SELFPRGEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDE 3 ++#define WDCE 4 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++/* Reserved [0x67] */ ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++/* Reserved [0x71..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++#define OCR2B _SFR_MEM8(0xB4) ++ ++/* Reserved [0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++ ++/* Reserved [0xB7] */ ++ ++#define TWBR _SFR_MEM8(0xB8) ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++/* Reserved [0xBE..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0xC6) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(3) ++#define PCINT0_vect_num 3 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect _VECTOR(4) ++#define PCINT1_vect_num 4 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT2_vect _VECTOR(5) ++#define PCINT2_vect_num 5 ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect _VECTOR(6) ++#define WDT_vect_num 6 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPA_vect _VECTOR(7) ++#define TIMER2_COMPA_vect_num 7 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPB_vect _VECTOR(8) ++#define TIMER2_COMPB_vect_num 8 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(9) ++#define TIMER2_OVF_vect_num 9 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(10) ++#define TIMER1_CAPT_vect_num 10 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(11) ++#define TIMER1_COMPA_vect_num 11 ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(12) ++#define TIMER1_COMPB_vect_num 12 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(13) ++#define TIMER1_OVF_vect_num 13 ++ ++/* TimerCounter0 Compare Match A */ ++#define TIMER0_COMPA_vect _VECTOR(14) ++#define TIMER0_COMPA_vect_num 14 ++ ++/* TimerCounter0 Compare Match B */ ++#define TIMER0_COMPB_vect _VECTOR(15) ++#define TIMER0_COMPB_vect_num 15 ++ ++/* Timer/Couner0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(16) ++#define TIMER0_OVF_vect_num 16 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(17) ++#define SPI_STC_vect_num 17 ++ ++/* USART Rx Complete */ ++#define USART_RX_vect _VECTOR(18) ++#define USART_RX_vect_num 18 ++ ++/* USART, Data Register Empty */ ++#define USART_UDRE_vect _VECTOR(19) ++#define USART_UDRE_vect_num 19 ++ ++/* USART Tx Complete */ ++#define USART_TX_vect _VECTOR(20) ++#define USART_TX_vect_num 20 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(21) ++#define ADC_vect_num 21 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(22) ++#define EE_READY_vect_num 22 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(23) ++#define ANALOG_COMP_vect_num 23 ++ ++/* Two-wire Serial Interface */ ++#define TWI_vect _VECTOR(24) ++#define TWI_vect_num 24 ++ ++/* Store Program Memory Read */ ++#define SPM_Ready_vect _VECTOR(25) ++#define SPM_Ready_vect_num 25 ++ ++#define _VECTORS_SIZE 52 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 64 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x0FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 512 ++#define RAMEND 0x02FF ++#define E2START 0 ++#define E2SIZE 256 ++#define E2PAGESIZE 4 ++#define E2END 0x00FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x92 ++#define SIGNATURE_2 0x0A ++ ++ ++#endif /* #ifdef _AVR_ATMEGA48PA_H_INCLUDED */ ++ +diff --git a/include/avr/iom48pb.h b/include/avr/iom48pb.h +new file mode 100644 +index 0000000..966f6d9 +--- /dev/null ++++ b/include/avr/iom48pb.h +@@ -0,0 +1,807 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATMEGA48PB_H_INCLUDED ++#define _AVR_ATMEGA48PB_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom48pb.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDRE3 3 ++#define DDRE2 2 ++#define DDRE1 1 ++#define DDRE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE3 3 ++#define PORTE2 2 ++#define PORTE1 1 ++#define PORTE0 0 ++ ++#define ACSRB _SFR_IO8(0x0F) ++#define ACOE 0 ++ ++/* Reserved [0x10..0x14] */ ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++/* Reserved [0x18..0x1A] */ ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++#define EEARL _SFR_IO8(0x21) ++ ++/* Reserved [0x22] */ ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define TSM 7 ++#define PSRASY 1 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++ ++#define OCR0A _SFR_IO8(0x27) ++ ++#define OCR0B _SFR_IO8(0x28) ++ ++/* Reserved [0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++/* Reserved [0x31..0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SELFPRGEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDE 3 ++#define WDCE 4 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++/* Reserved [0x67] */ ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++/* Reserved [0x71..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++#define OCR2B _SFR_MEM8(0xB4) ++ ++/* Reserved [0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++ ++/* Reserved [0xB7] */ ++ ++#define TWBR _SFR_MEM8(0xB8) ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++/* Reserved [0xBE..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++ ++#define UCSR0D _SFR_MEM8(0xC3) ++#define SFDE 5 ++#define RXS 6 ++#define RXSIE 7 ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0xC6) ++ ++/* Reserved [0xC7..0xEF] */ ++ ++#define DEVID0 _SFR_MEM8(0xF0) ++ ++#define DEVID1 _SFR_MEM8(0xF1) ++ ++#define DEVID2 _SFR_MEM8(0xF2) ++ ++#define DEVID3 _SFR_MEM8(0xF3) ++ ++#define DEVID4 _SFR_MEM8(0xF4) ++ ++#define DEVID5 _SFR_MEM8(0xF5) ++ ++#define DEVID6 _SFR_MEM8(0xF6) ++ ++#define DEVID7 _SFR_MEM8(0xF7) ++ ++#define DEVID8 _SFR_MEM8(0xF8) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(3) ++#define PCINT0_vect_num 3 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect _VECTOR(4) ++#define PCINT1_vect_num 4 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT2_vect _VECTOR(5) ++#define PCINT2_vect_num 5 ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect _VECTOR(6) ++#define WDT_vect_num 6 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPA_vect _VECTOR(7) ++#define TIMER2_COMPA_vect_num 7 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPB_vect _VECTOR(8) ++#define TIMER2_COMPB_vect_num 8 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(9) ++#define TIMER2_OVF_vect_num 9 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(10) ++#define TIMER1_CAPT_vect_num 10 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(11) ++#define TIMER1_COMPA_vect_num 11 ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(12) ++#define TIMER1_COMPB_vect_num 12 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(13) ++#define TIMER1_OVF_vect_num 13 ++ ++/* TimerCounter0 Compare Match A */ ++#define TIMER0_COMPA_vect _VECTOR(14) ++#define TIMER0_COMPA_vect_num 14 ++ ++/* TimerCounter0 Compare Match B */ ++#define TIMER0_COMPB_vect _VECTOR(15) ++#define TIMER0_COMPB_vect_num 15 ++ ++/* Timer/Couner0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(16) ++#define TIMER0_OVF_vect_num 16 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(17) ++#define SPI_STC_vect_num 17 ++ ++/* USART Rx Complete */ ++#define USART_RX_vect _VECTOR(18) ++#define USART_RX_vect_num 18 ++ ++/* USART, Data Register Empty */ ++#define USART_UDRE_vect _VECTOR(19) ++#define USART_UDRE_vect_num 19 ++ ++/* USART Tx Complete */ ++#define USART_TX_vect _VECTOR(20) ++#define USART_TX_vect_num 20 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(21) ++#define ADC_vect_num 21 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(22) ++#define EE_READY_vect_num 22 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(23) ++#define ANALOG_COMP_vect_num 23 ++ ++/* Two-wire Serial Interface */ ++#define TWI_vect _VECTOR(24) ++#define TWI_vect_num 24 ++ ++/* Store Program Memory Read */ ++#define SPM_Ready_vect _VECTOR(25) ++#define SPM_Ready_vect_num 25 ++ ++#define _VECTORS_SIZE 52 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 64 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x0FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 512 ++#define RAMEND 0x02FF ++#define E2START 0 ++#define E2SIZE 256 ++#define E2PAGESIZE 4 ++#define E2END 0x00FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x92 ++#define SIGNATURE_2 0x10 ++ ++ ++#endif /* #ifdef _AVR_ATMEGA48PB_H_INCLUDED */ ++ +diff --git a/include/avr/iom64.h b/include/avr/iom64.h +index fefb83d..7b53431 100644 +--- a/include/avr/iom64.h ++++ b/include/avr/iom64.h +@@ -1,1304 +1,1305 @@ +-/* Copyright (c) 2002, Steinar Haugen +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom64.h 2235 2011-03-17 04:13:14Z arcanum $ */ +- +-/* avr/iom64.h - defines for ATmega64 +- +- As of 2002-11-23: +- - This should be up to date with data sheet Rev. 2490C-AVR-09/02 */ +- +-#ifndef _AVR_IOM64_H_ +-#define _AVR_IOM64_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom64.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* Input Pins, Port F */ +-#define PINF _SFR_IO8(0x00) +- +-/* Input Pins, Port E */ +-#define PINE _SFR_IO8(0x01) +- +-/* Data Direction Register, Port E */ +-#define DDRE _SFR_IO8(0x02) +- +-/* Data Register, Port E */ +-#define PORTE _SFR_IO8(0x03) +- +-/* ADC Data Register */ +-#define ADCW _SFR_IO16(0x04) /* for backwards compatibility */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x04) +-#endif +-#define ADCL _SFR_IO8(0x04) +-#define ADCH _SFR_IO8(0x05) +- +-/* ADC Control and Status Register A */ +-#define ADCSR _SFR_IO8(0x06) /* for backwards compatibility */ +-#define ADCSRA _SFR_IO8(0x06) +- +-/* ADC Multiplexer select */ +-#define ADMUX _SFR_IO8(0x07) +- +-/* Analog Comparator Control and Status Register */ +-#define ACSR _SFR_IO8(0x08) +- +-/* USART0 Baud Rate Register Low */ +-#define UBRR0L _SFR_IO8(0x09) +- +-/* USART0 Control and Status Register B */ +-#define UCSR0B _SFR_IO8(0x0A) +- +-/* USART0 Control and Status Register A */ +-#define UCSR0A _SFR_IO8(0x0B) +- +-/* USART0 I/O Data Register */ +-#define UDR0 _SFR_IO8(0x0C) +- +-/* SPI Control Register */ +-#define SPCR _SFR_IO8(0x0D) +- +-/* SPI Status Register */ +-#define SPSR _SFR_IO8(0x0E) +- +-/* SPI I/O Data Register */ +-#define SPDR _SFR_IO8(0x0F) +- +-/* Input Pins, Port D */ +-#define PIND _SFR_IO8(0x10) +- +-/* Data Direction Register, Port D */ +-#define DDRD _SFR_IO8(0x11) +- +-/* Data Register, Port D */ +-#define PORTD _SFR_IO8(0x12) +- +-/* Input Pins, Port C */ +-#define PINC _SFR_IO8(0x13) +- +-/* Data Direction Register, Port C */ +-#define DDRC _SFR_IO8(0x14) +- +-/* Data Register, Port C */ +-#define PORTC _SFR_IO8(0x15) +- +-/* Input Pins, Port B */ +-#define PINB _SFR_IO8(0x16) +- +-/* Data Direction Register, Port B */ +-#define DDRB _SFR_IO8(0x17) +- +-/* Data Register, Port B */ +-#define PORTB _SFR_IO8(0x18) +- +-/* Input Pins, Port A */ +-#define PINA _SFR_IO8(0x19) +- +-/* Data Direction Register, Port A */ +-#define DDRA _SFR_IO8(0x1A) +- +-/* Data Register, Port A */ +-#define PORTA _SFR_IO8(0x1B) +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO16(0x1E) +-#define EEARL _SFR_IO8(0x1E) +-#define EEARH _SFR_IO8(0x1F) +- +-/* Special Function I/O Register */ +-#define SFIOR _SFR_IO8(0x20) +- +-/* Watchdog Timer Control Register */ +-#define WDTCR _SFR_IO8(0x21) +- +-/* On-chip Debug Register */ +-#define OCDR _SFR_IO8(0x22) +- +-/* Timer2 Output Compare Register */ +-#define OCR2 _SFR_IO8(0x23) +- +-/* Timer/Counter 2 */ +-#define TCNT2 _SFR_IO8(0x24) +- +-/* Timer/Counter 2 Control register */ +-#define TCCR2 _SFR_IO8(0x25) +- +-/* T/C 1 Input Capture Register */ +-#define ICR1 _SFR_IO16(0x26) +-#define ICR1L _SFR_IO8(0x26) +-#define ICR1H _SFR_IO8(0x27) +- +-/* Timer/Counter1 Output Compare Register B */ +-#define OCR1B _SFR_IO16(0x28) +-#define OCR1BL _SFR_IO8(0x28) +-#define OCR1BH _SFR_IO8(0x29) +- +-/* Timer/Counter1 Output Compare Register A */ +-#define OCR1A _SFR_IO16(0x2A) +-#define OCR1AL _SFR_IO8(0x2A) +-#define OCR1AH _SFR_IO8(0x2B) +- +-/* Timer/Counter 1 */ +-#define TCNT1 _SFR_IO16(0x2C) +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1H _SFR_IO8(0x2D) +- +-/* Timer/Counter 1 Control and Status Register */ +-#define TCCR1B _SFR_IO8(0x2E) +- +-/* Timer/Counter 1 Control Register */ +-#define TCCR1A _SFR_IO8(0x2F) +- +-/* Timer/Counter 0 Asynchronous Control & Status Register */ +-#define ASSR _SFR_IO8(0x30) +- +-/* Output Compare Register 0 */ +-#define OCR0 _SFR_IO8(0x31) +- +-/* Timer/Counter 0 */ +-#define TCNT0 _SFR_IO8(0x32) +- +-/* Timer/Counter 0 Control Register */ +-#define TCCR0 _SFR_IO8(0x33) +- +-/* MCU Status Register */ +-#define MCUSR _SFR_IO8(0x34) /* for backwards compatibility */ +-#define MCUCSR _SFR_IO8(0x34) +- +-/* MCU general Control Register */ +-#define MCUCR _SFR_IO8(0x35) +- +-/* Timer/Counter Interrupt Flag Register */ +-#define TIFR _SFR_IO8(0x36) +- +-/* Timer/Counter Interrupt MaSK register */ +-#define TIMSK _SFR_IO8(0x37) +- +-/* External Interrupt Flag Register */ +-#define EIFR _SFR_IO8(0x38) +- +-/* External Interrupt MaSK register */ +-#define EIMSK _SFR_IO8(0x39) +- +-/* External Interrupt Control Register B */ +-#define EICRB _SFR_IO8(0x3A) +- +-/* XDIV Divide control register */ +-#define XDIV _SFR_IO8(0x3C) +- +-/* 0x3D..0x3E SP */ +- +-/* 0x3F SREG */ +- +-/* Extended I/O registers */ +- +-/* Data Direction Register, Port F */ +-#define DDRF _SFR_MEM8(0x61) +- +-/* Data Register, Port F */ +-#define PORTF _SFR_MEM8(0x62) +- +-/* Input Pins, Port G */ +-#define PING _SFR_MEM8(0x63) +- +-/* Data Direction Register, Port G */ +-#define DDRG _SFR_MEM8(0x64) +- +-/* Data Register, Port G */ +-#define PORTG _SFR_MEM8(0x65) +- +-/* Store Program Memory Control and Status Register */ +-#define SPMCR _SFR_MEM8(0x68) +-#define SPMCSR _SFR_MEM8(0x68) /* for backwards compatibility with m128*/ +- +-/* External Interrupt Control Register A */ +-#define EICRA _SFR_MEM8(0x6A) +- +-/* External Memory Control Register B */ +-#define XMCRB _SFR_MEM8(0x6C) +- +-/* External Memory Control Register A */ +-#define XMCRA _SFR_MEM8(0x6D) +- +-/* Oscillator Calibration Register */ +-#define OSCCAL _SFR_MEM8(0x6F) +- +-/* 2-wire Serial Interface Bit Rate Register */ +-#define TWBR _SFR_MEM8(0x70) +- +-/* 2-wire Serial Interface Status Register */ +-#define TWSR _SFR_MEM8(0x71) +- +-/* 2-wire Serial Interface Address Register */ +-#define TWAR _SFR_MEM8(0x72) +- +-/* 2-wire Serial Interface Data Register */ +-#define TWDR _SFR_MEM8(0x73) +- +-/* 2-wire Serial Interface Control Register */ +-#define TWCR _SFR_MEM8(0x74) +- +-/* Time Counter 1 Output Compare Register C */ +-#define OCR1C _SFR_MEM16(0x78) +-#define OCR1CL _SFR_MEM8(0x78) +-#define OCR1CH _SFR_MEM8(0x79) +- +-/* Timer/Counter 1 Control Register C */ +-#define TCCR1C _SFR_MEM8(0x7A) +- +-/* Extended Timer Interrupt Flag Register */ +-#define ETIFR _SFR_MEM8(0x7C) +- +-/* Extended Timer Interrupt Mask Register */ +-#define ETIMSK _SFR_MEM8(0x7D) +- +-/* Timer/Counter 3 Input Capture Register */ +-#define ICR3 _SFR_MEM16(0x80) +-#define ICR3L _SFR_MEM8(0x80) +-#define ICR3H _SFR_MEM8(0x81) +- +-/* Timer/Counter 3 Output Compare Register C */ +-#define OCR3C _SFR_MEM16(0x82) +-#define OCR3CL _SFR_MEM8(0x82) +-#define OCR3CH _SFR_MEM8(0x83) +- +-/* Timer/Counter 3 Output Compare Register B */ +-#define OCR3B _SFR_MEM16(0x84) +-#define OCR3BL _SFR_MEM8(0x84) +-#define OCR3BH _SFR_MEM8(0x85) +- +-/* Timer/Counter 3 Output Compare Register A */ +-#define OCR3A _SFR_MEM16(0x86) +-#define OCR3AL _SFR_MEM8(0x86) +-#define OCR3AH _SFR_MEM8(0x87) +- +-/* Timer/Counter 3 Counter Register */ +-#define TCNT3 _SFR_MEM16(0x88) +-#define TCNT3L _SFR_MEM8(0x88) +-#define TCNT3H _SFR_MEM8(0x89) +- +-/* Timer/Counter 3 Control Register B */ +-#define TCCR3B _SFR_MEM8(0x8A) +- +-/* Timer/Counter 3 Control Register A */ +-#define TCCR3A _SFR_MEM8(0x8B) +- +-/* Timer/Counter 3 Control Register C */ +-#define TCCR3C _SFR_MEM8(0x8C) +- +-/* ADC Control and Status Register B */ +-#define ADCSRB _SFR_MEM8(0x8E) +- +-/* USART0 Baud Rate Register High */ +-#define UBRR0H _SFR_MEM8(0x90) +- +-/* USART0 Control and Status Register C */ +-#define UCSR0C _SFR_MEM8(0x95) +- +-/* USART1 Baud Rate Register High */ +-#define UBRR1H _SFR_MEM8(0x98) +- +-/* USART1 Baud Rate Register Low*/ +-#define UBRR1L _SFR_MEM8(0x99) +- +-/* USART1 Control and Status Register B */ +-#define UCSR1B _SFR_MEM8(0x9A) +- +-/* USART1 Control and Status Register A */ +-#define UCSR1A _SFR_MEM8(0x9B) +- +-/* USART1 I/O Data Register */ +-#define UDR1 _SFR_MEM8(0x9C) +- +-/* USART1 Control and Status Register C */ +-#define UCSR1C _SFR_MEM8(0x9D) +- +-/* Interrupt vectors */ +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt Request 1 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +-#define SIG_INTERRUPT1 _VECTOR(2) +- +-/* External Interrupt Request 2 */ +-#define INT2_vect_num 3 +-#define INT2_vect _VECTOR(3) +-#define SIG_INTERRUPT2 _VECTOR(3) +- +-/* External Interrupt Request 3 */ +-#define INT3_vect_num 4 +-#define INT3_vect _VECTOR(4) +-#define SIG_INTERRUPT3 _VECTOR(4) +- +-/* External Interrupt Request 4 */ +-#define INT4_vect_num 5 +-#define INT4_vect _VECTOR(5) +-#define SIG_INTERRUPT4 _VECTOR(5) +- +-/* External Interrupt Request 5 */ +-#define INT5_vect_num 6 +-#define INT5_vect _VECTOR(6) +-#define SIG_INTERRUPT5 _VECTOR(6) +- +-/* External Interrupt Request 6 */ +-#define INT6_vect_num 7 +-#define INT6_vect _VECTOR(7) +-#define SIG_INTERRUPT6 _VECTOR(7) +- +-/* External Interrupt Request 7 */ +-#define INT7_vect_num 8 +-#define INT7_vect _VECTOR(8) +-#define SIG_INTERRUPT7 _VECTOR(8) +- +-/* Timer/Counter2 Compare Match */ +-#define TIMER2_COMP_vect_num 9 +-#define TIMER2_COMP_vect _VECTOR(9) +-#define SIG_OUTPUT_COMPARE2 _VECTOR(9) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 10 +-#define TIMER2_OVF_vect _VECTOR(10) +-#define SIG_OVERFLOW2 _VECTOR(10) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 11 +-#define TIMER1_CAPT_vect _VECTOR(11) +-#define SIG_INPUT_CAPTURE1 _VECTOR(11) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 12 +-#define TIMER1_COMPA_vect _VECTOR(12) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(12) +- +-/* Timer/Counter Compare Match B */ +-#define TIMER1_COMPB_vect_num 13 +-#define TIMER1_COMPB_vect _VECTOR(13) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(13) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 14 +-#define TIMER1_OVF_vect _VECTOR(14) +-#define SIG_OVERFLOW1 _VECTOR(14) +- +-/* Timer/Counter0 Compare Match */ +-#define TIMER0_COMP_vect_num 15 +-#define TIMER0_COMP_vect _VECTOR(15) +-#define SIG_OUTPUT_COMPARE0 _VECTOR(15) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 16 +-#define TIMER0_OVF_vect _VECTOR(16) +-#define SIG_OVERFLOW0 _VECTOR(16) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 17 +-#define SPI_STC_vect _VECTOR(17) +-#define SIG_SPI _VECTOR(17) +- +-/* USART0, Rx Complete */ +-#define USART0_RX_vect_num 18 +-#define USART0_RX_vect _VECTOR(18) +-#define SIG_UART0_RECV _VECTOR(18) +- +-/* USART0 Data Register Empty */ +-#define USART0_UDRE_vect_num 19 +-#define USART0_UDRE_vect _VECTOR(19) +-#define SIG_UART0_DATA _VECTOR(19) +- +-/* USART0, Tx Complete */ +-#define USART0_TX_vect_num 20 +-#define USART0_TX_vect _VECTOR(20) +-#define SIG_UART0_TRANS _VECTOR(20) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 21 +-#define ADC_vect _VECTOR(21) +-#define SIG_ADC _VECTOR(21) +- +-/* EEPROM Ready */ +-#define EE_READY_vect_num 22 +-#define EE_READY_vect _VECTOR(22) +-#define SIG_EEPROM_READY _VECTOR(22) +- +-/* Analog Comparator */ +-#define ANALOG_COMP_vect_num 23 +-#define ANALOG_COMP_vect _VECTOR(23) +-#define SIG_COMPARATOR _VECTOR(23) +- +-/* Timer/Counter1 Compare Match C */ +-#define TIMER1_COMPC_vect_num 24 +-#define TIMER1_COMPC_vect _VECTOR(24) +-#define SIG_OUTPUT_COMPARE1C _VECTOR(24) +- +-/* Timer/Counter3 Capture Event */ +-#define TIMER3_CAPT_vect_num 25 +-#define TIMER3_CAPT_vect _VECTOR(25) +-#define SIG_INPUT_CAPTURE3 _VECTOR(25) +- +-/* Timer/Counter3 Compare Match A */ +-#define TIMER3_COMPA_vect_num 26 +-#define TIMER3_COMPA_vect _VECTOR(26) +-#define SIG_OUTPUT_COMPARE3A _VECTOR(26) +- +-/* Timer/Counter3 Compare Match B */ +-#define TIMER3_COMPB_vect_num 27 +-#define TIMER3_COMPB_vect _VECTOR(27) +-#define SIG_OUTPUT_COMPARE3B _VECTOR(27) +- +-/* Timer/Counter3 Compare Match C */ +-#define TIMER3_COMPC_vect_num 28 +-#define TIMER3_COMPC_vect _VECTOR(28) +-#define SIG_OUTPUT_COMPARE3C _VECTOR(28) +- +-/* Timer/Counter3 Overflow */ +-#define TIMER3_OVF_vect_num 29 +-#define TIMER3_OVF_vect _VECTOR(29) +-#define SIG_OVERFLOW3 _VECTOR(29) +- +-/* USART1, Rx Complete */ +-#define USART1_RX_vect_num 30 +-#define USART1_RX_vect _VECTOR(30) +-#define SIG_UART1_RECV _VECTOR(30) +- +-/* USART1, Data Register Empty */ +-#define USART1_UDRE_vect_num 31 +-#define USART1_UDRE_vect _VECTOR(31) +-#define SIG_UART1_DATA _VECTOR(31) +- +-/* USART1, Tx Complete */ +-#define USART1_TX_vect_num 32 +-#define USART1_TX_vect _VECTOR(32) +-#define SIG_UART1_TRANS _VECTOR(32) +- +-/* 2-wire Serial Interface */ +-#define TWI_vect_num 33 +-#define TWI_vect _VECTOR(33) +-#define SIG_2WIRE_SERIAL _VECTOR(33) +- +-/* Store Program Memory Read */ +-#define SPM_READY_vect_num 34 +-#define SPM_READY_vect _VECTOR(34) +-#define SIG_SPM_READY _VECTOR(34) +- +-#define _VECTORS_SIZE 140 +- +-/* +- The Register Bit names are represented by their bit number (0-7). +-*/ +- +-/* 2-wire Control Register - TWCR */ +-#define TWINT 7 +-#define TWEA 6 +-#define TWSTA 5 +-#define TWSTO 4 +-#define TWWC 3 +-#define TWEN 2 +-#define TWIE 0 +- +-/* 2-wire Address Register - TWAR */ +-#define TWA6 7 +-#define TWA5 6 +-#define TWA4 5 +-#define TWA3 4 +-#define TWA2 3 +-#define TWA1 2 +-#define TWA0 1 +-#define TWGCE 0 +- +-/* 2-wire Status Register - TWSR */ +-#define TWS7 7 +-#define TWS6 6 +-#define TWS5 5 +-#define TWS4 4 +-#define TWS3 3 +-#define TWPS1 1 +-#define TWPS0 0 +- +-/* External Memory Control Register A - XMCRA */ +-#define SRL2 6 +-#define SRL1 5 +-#define SRL0 4 +-#define SRW01 3 +-#define SRW00 2 +-#define SRW11 1 +- +-/* External Memory Control Register B - XMCRA */ +-#define XMBK 7 +-#define XMM2 2 +-#define XMM1 1 +-#define XMM0 0 +- +-/* XDIV Divide control register - XDIV */ +-#define XDIVEN 7 +-#define XDIV6 6 +-#define XDIV5 5 +-#define XDIV4 4 +-#define XDIV3 3 +-#define XDIV2 2 +-#define XDIV1 1 +-#define XDIV0 0 +- +-/* External Interrupt Control Register A - EICRA */ +-#define ISC31 7 +-#define ISC30 6 +-#define ISC21 5 +-#define ISC20 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-/* External Interrupt Control Register B - EICRB */ +-#define ISC71 7 +-#define ISC70 6 +-#define ISC61 5 +-#define ISC60 4 +-#define ISC51 3 +-#define ISC50 2 +-#define ISC41 1 +-#define ISC40 0 +- +-/* Store Program Memory Control Register - SPMCSR, SPMCR */ +-#define SPMIE 7 +-#define RWWSB 6 +-#define RWWSRE 4 +-#define BLBSET 3 +-#define PGWRT 2 +-#define PGERS 1 +-#define SPMEN 0 +- +-/* External Interrupt MaSK register - EIMSK */ +-#define INT7 7 +-#define INT6 6 +-#define INT5 5 +-#define INT4 4 +-#define INT3 3 +-#define INT2 2 +-#define INT1 1 +-#define INT0 0 +- +-/* External Interrupt Flag Register - EIFR */ +-#define INTF7 7 +-#define INTF6 6 +-#define INTF5 5 +-#define INTF4 4 +-#define INTF3 3 +-#define INTF2 2 +-#define INTF1 1 +-#define INTF0 0 +- +-/* Timer/Counter Interrupt MaSK register - TIMSK */ +-#define OCIE2 7 +-#define TOIE2 6 +-#define TICIE1 5 +-#define OCIE1A 4 +-#define OCIE1B 3 +-#define TOIE1 2 +-#define OCIE0 1 +-#define TOIE0 0 +- +-/* Timer/Counter Interrupt Flag Register - TIFR */ +-#define OCF2 7 +-#define TOV2 6 +-#define ICF1 5 +-#define OCF1A 4 +-#define OCF1B 3 +-#define TOV1 2 +-#define OCF0 1 +-#define TOV0 0 +- +-/* Extended Timer Interrupt MaSK register - ETIMSK */ +-#define TICIE3 5 +-#define OCIE3A 4 +-#define OCIE3B 3 +-#define TOIE3 2 +-#define OCIE3C 1 +-#define OCIE1C 0 +- +-/* Extended Timer Interrupt Flag Register - ETIFR */ +-#define ICF3 5 +-#define OCF3A 4 +-#define OCF3B 3 +-#define TOV3 2 +-#define OCF3C 1 +-#define OCF1C 0 +- +-/* MCU Control Register - MCUCR */ +-#define SRE 7 +-#define SRW10 6 +-#define SE 5 +-#define SM1 4 +-#define SM0 3 +-#define SM2 2 +-#define IVSEL 1 +-#define IVCE 0 +- +-/* MCU Control And Status Register - MCUCSR */ +-#define JTD 7 +-#define JTRF 4 +-#define WDRF 3 +-#define BORF 2 +-#define EXTRF 1 +-#define PORF 0 +- +-/* Timer/Counter Control Register (generic) */ +-#define FOC 7 +-#define WGM0 6 +-#define COM1 5 +-#define COM0 4 +-#define WGM1 3 +-#define CS2 2 +-#define CS1 1 +-#define CS0 0 +- +-/* Timer/Counter 0 Control Register - TCCR0 */ +-#define FOC0 7 +-#define WGM00 6 +-#define COM01 5 +-#define COM00 4 +-#define WGM01 3 +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* Timer/Counter 2 Control Register - TCCR2 */ +-#define FOC2 7 +-#define WGM20 6 +-#define COM21 5 +-#define COM20 4 +-#define WGM21 3 +-#define CS22 2 +-#define CS21 1 +-#define CS20 0 +- +-/* Timer/Counter 0 Asynchronous Control & Status Register - ASSR */ +-#define AS0 3 +-#define TCN0UB 2 +-#define OCR0UB 1 +-#define TCR0UB 0 +- +-/* Timer/Counter Control Register A (generic) */ +-#define COMA1 7 +-#define COMA0 6 +-#define COMB1 5 +-#define COMB0 4 +-#define COMC1 3 +-#define COMC0 2 +-#define WGMA1 1 +-#define WGMA0 0 +- +-/* Timer/Counter 1 Control and Status Register A - TCCR1A */ +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define COM1C1 3 +-#define COM1C0 2 +-#define WGM11 1 +-#define WGM10 0 +- +-/* Timer/Counter 3 Control and Status Register A - TCCR3A */ +-#define COM3A1 7 +-#define COM3A0 6 +-#define COM3B1 5 +-#define COM3B0 4 +-#define COM3C1 3 +-#define COM3C0 2 +-#define WGM31 1 +-#define WGM30 0 +- +-/* Timer/Counter Control and Status Register B (generic) */ +-#define ICNC 7 +-#define ICES 6 +-#define WGMB3 4 +-#define WGMB2 3 +-#define CSB2 2 +-#define CSB1 1 +-#define CSB0 0 +- +-/* Timer/Counter 1 Control and Status Register B - TCCR1B */ +-#define ICNC1 7 +-#define ICES1 6 +-#define WGM13 4 +-#define WGM12 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* Timer/Counter 3 Control and Status Register B - TCCR3B */ +-#define ICNC3 7 +-#define ICES3 6 +-#define WGM33 4 +-#define WGM32 3 +-#define CS32 2 +-#define CS31 1 +-#define CS30 0 +- +-/* Timer/Counter Control Register C (generic) */ +-#define FOCA 7 +-#define FOCB 6 +-#define FOCC 5 +- +-/* Timer/Counter 3 Control Register C - TCCR3C */ +-#define FOC3A 7 +-#define FOC3B 6 +-#define FOC3C 5 +- +-/* Timer/Counter 1 Control Register C - TCCR1C */ +-#define FOC1A 7 +-#define FOC1B 6 +-#define FOC1C 5 +- +-/* On-chip Debug Register - OCDR */ +-#define IDRD 7 +-#define OCDR7 7 +-#define OCDR6 6 +-#define OCDR5 5 +-#define OCDR4 4 +-#define OCDR3 3 +-#define OCDR2 2 +-#define OCDR1 1 +-#define OCDR0 0 +- +-/* Watchdog Timer Control Register - WDTCR */ +-#define WDCE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* +- The ADHSM bit has been removed from all documentation, +- as being not needed at all since the comparator has proven +- to be fast enough even without feeding it more power. +-*/ +- +-/* Special Function I/O Register - SFIOR */ +-#define TSM 7 +-#define ACME 3 +-#define PUD 2 +-#define PSR0 1 +-#define PSR321 0 +- +-/* Port Data Register (generic) */ +-#define PORT7 7 +-#define PORT6 6 +-#define PORT5 5 +-#define PORT4 4 +-#define PORT3 3 +-#define PORT2 2 +-#define PORT1 1 +-#define PORT0 0 +- +-/* Port Data Direction Register (generic) */ +-#define DD7 7 +-#define DD6 6 +-#define DD5 5 +-#define DD4 4 +-#define DD3 3 +-#define DD2 2 +-#define DD1 1 +-#define DD0 0 +- +-/* Port Input Pins (generic) */ +-#define PIN7 7 +-#define PIN6 6 +-#define PIN5 5 +-#define PIN4 4 +-#define PIN3 3 +-#define PIN2 2 +-#define PIN1 1 +-#define PIN0 0 +- +-/* SPI Status Register - SPSR */ +-#define SPIF 7 +-#define WCOL 6 +-#define SPI2X 0 +- +-/* SPI Control Register - SPCR */ +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +-/* USART Register C (generic) */ +-#define UMSEL 6 +-#define UPM1 5 +-#define UPM0 4 +-#define USBS 3 +-#define UCSZ1 2 +-#define UCSZ0 1 +-#define UCPOL 0 +- +-/* USART1 Register C - UCSR1C */ +-#define UMSEL1 6 +-#define UPM11 5 +-#define UPM10 4 +-#define USBS1 3 +-#define UCSZ11 2 +-#define UCSZ10 1 +-#define UCPOL1 0 +- +-/* USART0 Register C - UCSR0C */ +-#define UMSEL0 6 +-#define UPM01 5 +-#define UPM00 4 +-#define USBS0 3 +-#define UCSZ01 2 +-#define UCSZ00 1 +-#define UCPOL0 0 +- +-/* USART Status Register A (generic) */ +-#define RXC 7 +-#define TXC 6 +-#define UDRE 5 +-#define FE 4 +-#define DOR 3 +-#define UPE 2 +-#define U2X 1 +-#define MPCM 0 +- +-/* USART1 Status Register A - UCSR1A */ +-#define RXC1 7 +-#define TXC1 6 +-#define UDRE1 5 +-#define FE1 4 +-#define DOR1 3 +-#define UPE1 2 +-#define U2X1 1 +-#define MPCM1 0 +- +-/* USART0 Status Register A - UCSR0A */ +-#define RXC0 7 +-#define TXC0 6 +-#define UDRE0 5 +-#define FE0 4 +-#define DOR0 3 +-#define UPE0 2 +-#define U2X0 1 +-#define MPCM0 0 +- +-/* USART Control Register B (generic) */ +-#define RXCIE 7 +-#define TXCIE 6 +-#define UDRIE 5 +-#define RXEN 4 +-#define TXEN 3 +-#define UCSZ 2 +-#define UCSZ2 2 /* new name in datasheet (2467E-AVR-05/02) */ +-#define RXB8 1 +-#define TXB8 0 +- +-/* USART1 Control Register B - UCSR1B */ +-#define RXCIE1 7 +-#define TXCIE1 6 +-#define UDRIE1 5 +-#define RXEN1 4 +-#define TXEN1 3 +-#define UCSZ12 2 +-#define RXB81 1 +-#define TXB81 0 +- +-/* USART0 Control Register B - UCSR0B */ +-#define RXCIE0 7 +-#define TXCIE0 6 +-#define UDRIE0 5 +-#define RXEN0 4 +-#define TXEN0 3 +-#define UCSZ02 2 +-#define RXB80 1 +-#define TXB80 0 +- +-/* Analog Comparator Control and Status Register - ACSR */ +-#define ACD 7 +-#define ACBG 6 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +- +-/* ADC Control and Status Register B - ADCSRB */ +-#define ADTS2 2 +-#define ADTS1 1 +-#define ADTS0 0 +- +-/* ADC Control and status Register A - ADCSRA */ +-#define ADEN 7 +-#define ADSC 6 +-#define ADATE 5 +-#define ADIF 4 +-#define ADIE 3 +-#define ADPS2 2 +-#define ADPS1 1 +-#define ADPS0 0 +- +-/* ADC Multiplexer select - ADMUX */ +-#define REFS1 7 +-#define REFS0 6 +-#define ADLAR 5 +-#define MUX4 4 +-#define MUX3 3 +-#define MUX2 2 +-#define MUX1 1 +-#define MUX0 0 +- +-/* Port A Data Register - PORTA */ +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-/* Port A Data Direction Register - DDRA */ +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-/* Port A Input Pins - PINA */ +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-/* Port B Data Register - PORTB */ +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* Port B Data Direction Register - DDRB */ +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* Port B Input Pins - PINB */ +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* Port C Data Register - PORTC */ +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-/* Port C Data Direction Register - DDRC */ +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-/* Port C Input Pins - PINC */ +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-/* Port D Data Register - PORTD */ +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* Port D Data Direction Register - DDRD */ +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-/* Port D Input Pins - PIND */ +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-/* Port E Data Register - PORTE */ +-#define PE7 7 +-#define PE6 6 +-#define PE5 5 +-#define PE4 4 +-#define PE3 3 +-#define PE2 2 +-#define PE1 1 +-#define PE0 0 +- +-/* Port E Data Direction Register - DDRE */ +-#define DDE7 7 +-#define DDE6 6 +-#define DDE5 5 +-#define DDE4 4 +-#define DDE3 3 +-#define DDE2 2 +-#define DDE1 1 +-#define DDE0 0 +- +-/* Port E Input Pins - PINE */ +-#define PINE7 7 +-#define PINE6 6 +-#define PINE5 5 +-#define PINE4 4 +-#define PINE3 3 +-#define PINE2 2 +-#define PINE1 1 +-#define PINE0 0 +- +-/* Port F Data Register - PORTF */ +-#define PF7 7 +-#define PF6 6 +-#define PF5 5 +-#define PF4 4 +-#define PF3 3 +-#define PF2 2 +-#define PF1 1 +-#define PF0 0 +- +-/* Port F Data Direction Register - DDRF */ +-#define DDF7 7 +-#define DDF6 6 +-#define DDF5 5 +-#define DDF4 4 +-#define DDF3 3 +-#define DDF2 2 +-#define DDF1 1 +-#define DDF0 0 +- +-/* Port F Input Pins - PINF */ +-#define PINF7 7 +-#define PINF6 6 +-#define PINF5 5 +-#define PINF4 4 +-#define PINF3 3 +-#define PINF2 2 +-#define PINF1 1 +-#define PINF0 0 +- +-/* Port G Data Register - PORTG */ +-#define PG4 4 +-#define PG3 3 +-#define PG2 2 +-#define PG1 1 +-#define PG0 0 +- +-/* Port G Data Direction Register - DDRG */ +-#define DDG4 4 +-#define DDG3 3 +-#define DDG2 2 +-#define DDG1 1 +-#define DDG0 0 +- +-/* Port G Input Pins - PING */ +-#define PING4 4 +-#define PING3 3 +-#define PING2 2 +-#define PING1 1 +-#define PING0 0 +- +-/* EEPROM Control Register */ +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-/* Constants */ +-#define SPM_PAGESIZE 256 +-#define RAMEND 0x10FF /* Last On-Chip SRAM Location */ +-#define XRAMEND 0xFFFF +-#define E2END 0x07FF +-#define E2PAGESIZE 8 +-#define FLASHEND 0xFFFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_BODEN (unsigned char)~_BV(6) +-#define FUSE_BODLEVEL (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_CKOPT (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_WDTON (unsigned char)~_BV(0) +-#define FUSE_M103C (unsigned char)~_BV(1) +-#define EFUSE_DEFAULT (FUSE_M103C) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x96 +-#define SIGNATURE_2 0x02 +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_INTERRUPT1 +-#pragma GCC poison SIG_INTERRUPT2 +-#pragma GCC poison SIG_INTERRUPT3 +-#pragma GCC poison SIG_INTERRUPT4 +-#pragma GCC poison SIG_INTERRUPT5 +-#pragma GCC poison SIG_INTERRUPT6 +-#pragma GCC poison SIG_INTERRUPT7 +-#pragma GCC poison SIG_OUTPUT_COMPARE2 +-#pragma GCC poison SIG_OVERFLOW2 +-#pragma GCC poison SIG_INPUT_CAPTURE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OUTPUT_COMPARE0 +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_SPI +-#pragma GCC poison SIG_UART0_RECV +-#pragma GCC poison SIG_UART0_DATA +-#pragma GCC poison SIG_UART0_TRANS +-#pragma GCC poison SIG_ADC +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_OUTPUT_COMPARE1C +-#pragma GCC poison SIG_INPUT_CAPTURE3 +-#pragma GCC poison SIG_OUTPUT_COMPARE3A +-#pragma GCC poison SIG_OUTPUT_COMPARE3B +-#pragma GCC poison SIG_OUTPUT_COMPARE3C +-#pragma GCC poison SIG_OVERFLOW3 +-#pragma GCC poison SIG_UART1_RECV +-#pragma GCC poison SIG_UART1_DATA +-#pragma GCC poison SIG_UART1_TRANS +-#pragma GCC poison SIG_2WIRE_SERIAL +-#pragma GCC poison SIG_SPM_READY +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +-#endif /* _AVR_IOM64_H_ */ ++/* Copyright (c) 2002, Steinar Haugen ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom64.h 2235 2011-03-17 04:13:14Z arcanum $ */ ++ ++/* avr/iom64.h - defines for ATmega64 ++ ++ As of 2002-11-23: ++ - This should be up to date with data sheet Rev. 2490C-AVR-09/02 */ ++ ++#ifndef _AVR_IOM64_H_ ++#define _AVR_IOM64_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom64.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* Input Pins, Port F */ ++#define PINF _SFR_IO8(0x00) ++ ++/* Input Pins, Port E */ ++#define PINE _SFR_IO8(0x01) ++ ++/* Data Direction Register, Port E */ ++#define DDRE _SFR_IO8(0x02) ++ ++/* Data Register, Port E */ ++#define PORTE _SFR_IO8(0x03) ++ ++/* ADC Data Register */ ++#define ADCW _SFR_IO16(0x04) /* for backwards compatibility */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCL _SFR_IO8(0x04) ++#define ADCH _SFR_IO8(0x05) ++ ++/* ADC Control and Status Register A */ ++#define ADCSR _SFR_IO8(0x06) /* for backwards compatibility */ ++#define ADCSRA _SFR_IO8(0x06) ++ ++/* ADC Multiplexer select */ ++#define ADMUX _SFR_IO8(0x07) ++ ++/* Analog Comparator Control and Status Register */ ++#define ACSR _SFR_IO8(0x08) ++ ++/* USART0 Baud Rate Register Low */ ++#define UBRR0L _SFR_IO8(0x09) ++ ++/* USART0 Control and Status Register B */ ++#define UCSR0B _SFR_IO8(0x0A) ++ ++/* USART0 Control and Status Register A */ ++#define UCSR0A _SFR_IO8(0x0B) ++ ++/* USART0 I/O Data Register */ ++#define UDR0 _SFR_IO8(0x0C) ++ ++/* SPI Control Register */ ++#define SPCR _SFR_IO8(0x0D) ++ ++/* SPI Status Register */ ++#define SPSR _SFR_IO8(0x0E) ++ ++/* SPI I/O Data Register */ ++#define SPDR _SFR_IO8(0x0F) ++ ++/* Input Pins, Port D */ ++#define PIND _SFR_IO8(0x10) ++ ++/* Data Direction Register, Port D */ ++#define DDRD _SFR_IO8(0x11) ++ ++/* Data Register, Port D */ ++#define PORTD _SFR_IO8(0x12) ++ ++/* Input Pins, Port C */ ++#define PINC _SFR_IO8(0x13) ++ ++/* Data Direction Register, Port C */ ++#define DDRC _SFR_IO8(0x14) ++ ++/* Data Register, Port C */ ++#define PORTC _SFR_IO8(0x15) ++ ++/* Input Pins, Port B */ ++#define PINB _SFR_IO8(0x16) ++ ++/* Data Direction Register, Port B */ ++#define DDRB _SFR_IO8(0x17) ++ ++/* Data Register, Port B */ ++#define PORTB _SFR_IO8(0x18) ++ ++/* Input Pins, Port A */ ++#define PINA _SFR_IO8(0x19) ++ ++/* Data Direction Register, Port A */ ++#define DDRA _SFR_IO8(0x1A) ++ ++/* Data Register, Port A */ ++#define PORTA _SFR_IO8(0x1B) ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO16(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++#define EEARH _SFR_IO8(0x1F) ++ ++/* Special Function I/O Register */ ++#define SFIOR _SFR_IO8(0x20) ++ ++/* Watchdog Timer Control Register */ ++#define WDTCR _SFR_IO8(0x21) ++ ++/* On-chip Debug Register */ ++#define OCDR _SFR_IO8(0x22) ++ ++/* Timer2 Output Compare Register */ ++#define OCR2 _SFR_IO8(0x23) ++ ++/* Timer/Counter 2 */ ++#define TCNT2 _SFR_IO8(0x24) ++ ++/* Timer/Counter 2 Control register */ ++#define TCCR2 _SFR_IO8(0x25) ++ ++/* T/C 1 Input Capture Register */ ++#define ICR1 _SFR_IO16(0x26) ++#define ICR1L _SFR_IO8(0x26) ++#define ICR1H _SFR_IO8(0x27) ++ ++/* Timer/Counter1 Output Compare Register B */ ++#define OCR1B _SFR_IO16(0x28) ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BH _SFR_IO8(0x29) ++ ++/* Timer/Counter1 Output Compare Register A */ ++#define OCR1A _SFR_IO16(0x2A) ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++ ++/* Timer/Counter 1 */ ++#define TCNT1 _SFR_IO16(0x2C) ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++ ++/* Timer/Counter 1 Control and Status Register */ ++#define TCCR1B _SFR_IO8(0x2E) ++ ++/* Timer/Counter 1 Control Register */ ++#define TCCR1A _SFR_IO8(0x2F) ++ ++/* Timer/Counter 0 Asynchronous Control & Status Register */ ++#define ASSR _SFR_IO8(0x30) ++ ++/* Output Compare Register 0 */ ++#define OCR0 _SFR_IO8(0x31) ++ ++/* Timer/Counter 0 */ ++#define TCNT0 _SFR_IO8(0x32) ++ ++/* Timer/Counter 0 Control Register */ ++#define TCCR0 _SFR_IO8(0x33) ++ ++/* MCU Status Register */ ++#define MCUSR _SFR_IO8(0x34) /* for backwards compatibility */ ++#define MCUCSR _SFR_IO8(0x34) ++ ++/* MCU general Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++ ++/* Timer/Counter Interrupt Flag Register */ ++#define TIFR _SFR_IO8(0x36) ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define TIMSK _SFR_IO8(0x37) ++ ++/* External Interrupt Flag Register */ ++#define EIFR _SFR_IO8(0x38) ++ ++/* External Interrupt MaSK register */ ++#define EIMSK _SFR_IO8(0x39) ++ ++/* External Interrupt Control Register B */ ++#define EICRB _SFR_IO8(0x3A) ++ ++/* XDIV Divide control register */ ++#define XDIV _SFR_IO8(0x3C) ++ ++/* 0x3D..0x3E SP */ ++ ++/* 0x3F SREG */ ++ ++/* Extended I/O registers */ ++ ++/* Data Direction Register, Port F */ ++#define DDRF _SFR_MEM8(0x61) ++ ++/* Data Register, Port F */ ++#define PORTF _SFR_MEM8(0x62) ++ ++/* Input Pins, Port G */ ++#define PING _SFR_MEM8(0x63) ++ ++/* Data Direction Register, Port G */ ++#define DDRG _SFR_MEM8(0x64) ++ ++/* Data Register, Port G */ ++#define PORTG _SFR_MEM8(0x65) ++ ++/* Store Program Memory Control and Status Register */ ++#define SPMCR _SFR_MEM8(0x68) ++#define SPMCSR _SFR_MEM8(0x68) /* for backwards compatibility with m128*/ ++ ++/* External Interrupt Control Register A */ ++#define EICRA _SFR_MEM8(0x6A) ++ ++/* External Memory Control Register B */ ++#define XMCRB _SFR_MEM8(0x6C) ++ ++/* External Memory Control Register A */ ++#define XMCRA _SFR_MEM8(0x6D) ++ ++/* Oscillator Calibration Register */ ++#define OSCCAL _SFR_MEM8(0x6F) ++ ++/* 2-wire Serial Interface Bit Rate Register */ ++#define TWBR _SFR_MEM8(0x70) ++ ++/* 2-wire Serial Interface Status Register */ ++#define TWSR _SFR_MEM8(0x71) ++ ++/* 2-wire Serial Interface Address Register */ ++#define TWAR _SFR_MEM8(0x72) ++ ++/* 2-wire Serial Interface Data Register */ ++#define TWDR _SFR_MEM8(0x73) ++ ++/* 2-wire Serial Interface Control Register */ ++#define TWCR _SFR_MEM8(0x74) ++ ++/* Time Counter 1 Output Compare Register C */ ++#define OCR1C _SFR_MEM16(0x78) ++#define OCR1CL _SFR_MEM8(0x78) ++#define OCR1CH _SFR_MEM8(0x79) ++ ++/* Timer/Counter 1 Control Register C */ ++#define TCCR1C _SFR_MEM8(0x7A) ++ ++/* Extended Timer Interrupt Flag Register */ ++#define ETIFR _SFR_MEM8(0x7C) ++ ++/* Extended Timer Interrupt Mask Register */ ++#define ETIMSK _SFR_MEM8(0x7D) ++ ++/* Timer/Counter 3 Input Capture Register */ ++#define ICR3 _SFR_MEM16(0x80) ++#define ICR3L _SFR_MEM8(0x80) ++#define ICR3H _SFR_MEM8(0x81) ++ ++/* Timer/Counter 3 Output Compare Register C */ ++#define OCR3C _SFR_MEM16(0x82) ++#define OCR3CL _SFR_MEM8(0x82) ++#define OCR3CH _SFR_MEM8(0x83) ++ ++/* Timer/Counter 3 Output Compare Register B */ ++#define OCR3B _SFR_MEM16(0x84) ++#define OCR3BL _SFR_MEM8(0x84) ++#define OCR3BH _SFR_MEM8(0x85) ++ ++/* Timer/Counter 3 Output Compare Register A */ ++#define OCR3A _SFR_MEM16(0x86) ++#define OCR3AL _SFR_MEM8(0x86) ++#define OCR3AH _SFR_MEM8(0x87) ++ ++/* Timer/Counter 3 Counter Register */ ++#define TCNT3 _SFR_MEM16(0x88) ++#define TCNT3L _SFR_MEM8(0x88) ++#define TCNT3H _SFR_MEM8(0x89) ++ ++/* Timer/Counter 3 Control Register B */ ++#define TCCR3B _SFR_MEM8(0x8A) ++ ++/* Timer/Counter 3 Control Register A */ ++#define TCCR3A _SFR_MEM8(0x8B) ++ ++/* Timer/Counter 3 Control Register C */ ++#define TCCR3C _SFR_MEM8(0x8C) ++ ++/* ADC Control and Status Register B */ ++#define ADCSRB _SFR_MEM8(0x8E) ++ ++/* USART0 Baud Rate Register High */ ++#define UBRR0H _SFR_MEM8(0x90) ++ ++/* USART0 Control and Status Register C */ ++#define UCSR0C _SFR_MEM8(0x95) ++ ++/* USART1 Baud Rate Register High */ ++#define UBRR1H _SFR_MEM8(0x98) ++ ++/* USART1 Baud Rate Register Low*/ ++#define UBRR1L _SFR_MEM8(0x99) ++ ++/* USART1 Control and Status Register B */ ++#define UCSR1B _SFR_MEM8(0x9A) ++ ++/* USART1 Control and Status Register A */ ++#define UCSR1A _SFR_MEM8(0x9B) ++ ++/* USART1 I/O Data Register */ ++#define UDR1 _SFR_MEM8(0x9C) ++ ++/* USART1 Control and Status Register C */ ++#define UCSR1C _SFR_MEM8(0x9D) ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++#define SIG_INTERRUPT1 _VECTOR(2) ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect_num 3 ++#define INT2_vect _VECTOR(3) ++#define SIG_INTERRUPT2 _VECTOR(3) ++ ++/* External Interrupt Request 3 */ ++#define INT3_vect_num 4 ++#define INT3_vect _VECTOR(4) ++#define SIG_INTERRUPT3 _VECTOR(4) ++ ++/* External Interrupt Request 4 */ ++#define INT4_vect_num 5 ++#define INT4_vect _VECTOR(5) ++#define SIG_INTERRUPT4 _VECTOR(5) ++ ++/* External Interrupt Request 5 */ ++#define INT5_vect_num 6 ++#define INT5_vect _VECTOR(6) ++#define SIG_INTERRUPT5 _VECTOR(6) ++ ++/* External Interrupt Request 6 */ ++#define INT6_vect_num 7 ++#define INT6_vect _VECTOR(7) ++#define SIG_INTERRUPT6 _VECTOR(7) ++ ++/* External Interrupt Request 7 */ ++#define INT7_vect_num 8 ++#define INT7_vect _VECTOR(8) ++#define SIG_INTERRUPT7 _VECTOR(8) ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect_num 9 ++#define TIMER2_COMP_vect _VECTOR(9) ++#define SIG_OUTPUT_COMPARE2 _VECTOR(9) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 10 ++#define TIMER2_OVF_vect _VECTOR(10) ++#define SIG_OVERFLOW2 _VECTOR(10) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 11 ++#define TIMER1_CAPT_vect _VECTOR(11) ++#define SIG_INPUT_CAPTURE1 _VECTOR(11) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 12 ++#define TIMER1_COMPA_vect _VECTOR(12) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(12) ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect_num 13 ++#define TIMER1_COMPB_vect _VECTOR(13) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(13) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 14 ++#define TIMER1_OVF_vect _VECTOR(14) ++#define SIG_OVERFLOW1 _VECTOR(14) ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect_num 15 ++#define TIMER0_COMP_vect _VECTOR(15) ++#define SIG_OUTPUT_COMPARE0 _VECTOR(15) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 16 ++#define TIMER0_OVF_vect _VECTOR(16) ++#define SIG_OVERFLOW0 _VECTOR(16) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 17 ++#define SPI_STC_vect _VECTOR(17) ++#define SIG_SPI _VECTOR(17) ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect_num 18 ++#define USART0_RX_vect _VECTOR(18) ++#define SIG_UART0_RECV _VECTOR(18) ++ ++/* USART0 Data Register Empty */ ++#define USART0_UDRE_vect_num 19 ++#define USART0_UDRE_vect _VECTOR(19) ++#define SIG_UART0_DATA _VECTOR(19) ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect_num 20 ++#define USART0_TX_vect _VECTOR(20) ++#define SIG_UART0_TRANS _VECTOR(20) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 21 ++#define ADC_vect _VECTOR(21) ++#define SIG_ADC _VECTOR(21) ++ ++/* EEPROM Ready */ ++#define EE_READY_vect_num 22 ++#define EE_READY_vect _VECTOR(22) ++#define SIG_EEPROM_READY _VECTOR(22) ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect_num 23 ++#define ANALOG_COMP_vect _VECTOR(23) ++#define SIG_COMPARATOR _VECTOR(23) ++ ++/* Timer/Counter1 Compare Match C */ ++#define TIMER1_COMPC_vect_num 24 ++#define TIMER1_COMPC_vect _VECTOR(24) ++#define SIG_OUTPUT_COMPARE1C _VECTOR(24) ++ ++/* Timer/Counter3 Capture Event */ ++#define TIMER3_CAPT_vect_num 25 ++#define TIMER3_CAPT_vect _VECTOR(25) ++#define SIG_INPUT_CAPTURE3 _VECTOR(25) ++ ++/* Timer/Counter3 Compare Match A */ ++#define TIMER3_COMPA_vect_num 26 ++#define TIMER3_COMPA_vect _VECTOR(26) ++#define SIG_OUTPUT_COMPARE3A _VECTOR(26) ++ ++/* Timer/Counter3 Compare Match B */ ++#define TIMER3_COMPB_vect_num 27 ++#define TIMER3_COMPB_vect _VECTOR(27) ++#define SIG_OUTPUT_COMPARE3B _VECTOR(27) ++ ++/* Timer/Counter3 Compare Match C */ ++#define TIMER3_COMPC_vect_num 28 ++#define TIMER3_COMPC_vect _VECTOR(28) ++#define SIG_OUTPUT_COMPARE3C _VECTOR(28) ++ ++/* Timer/Counter3 Overflow */ ++#define TIMER3_OVF_vect_num 29 ++#define TIMER3_OVF_vect _VECTOR(29) ++#define SIG_OVERFLOW3 _VECTOR(29) ++ ++/* USART1, Rx Complete */ ++#define USART1_RX_vect_num 30 ++#define USART1_RX_vect _VECTOR(30) ++#define SIG_UART1_RECV _VECTOR(30) ++ ++/* USART1, Data Register Empty */ ++#define USART1_UDRE_vect_num 31 ++#define USART1_UDRE_vect _VECTOR(31) ++#define SIG_UART1_DATA _VECTOR(31) ++ ++/* USART1, Tx Complete */ ++#define USART1_TX_vect_num 32 ++#define USART1_TX_vect _VECTOR(32) ++#define SIG_UART1_TRANS _VECTOR(32) ++ ++/* 2-wire Serial Interface */ ++#define TWI_vect_num 33 ++#define TWI_vect _VECTOR(33) ++#define SIG_2WIRE_SERIAL _VECTOR(33) ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect_num 34 ++#define SPM_READY_vect _VECTOR(34) ++#define SIG_SPM_READY _VECTOR(34) ++ ++#define _VECTORS_SIZE 140 ++ ++/* ++ The Register Bit names are represented by their bit number (0-7). ++*/ ++ ++/* 2-wire Control Register - TWCR */ ++#define TWINT 7 ++#define TWEA 6 ++#define TWSTA 5 ++#define TWSTO 4 ++#define TWWC 3 ++#define TWEN 2 ++#define TWIE 0 ++ ++/* 2-wire Address Register - TWAR */ ++#define TWA6 7 ++#define TWA5 6 ++#define TWA4 5 ++#define TWA3 4 ++#define TWA2 3 ++#define TWA1 2 ++#define TWA0 1 ++#define TWGCE 0 ++ ++/* 2-wire Status Register - TWSR */ ++#define TWS7 7 ++#define TWS6 6 ++#define TWS5 5 ++#define TWS4 4 ++#define TWS3 3 ++#define TWPS1 1 ++#define TWPS0 0 ++ ++/* External Memory Control Register A - XMCRA */ ++#define SRL2 6 ++#define SRL1 5 ++#define SRL0 4 ++#define SRW01 3 ++#define SRW00 2 ++#define SRW11 1 ++ ++/* External Memory Control Register B - XMCRA */ ++#define XMBK 7 ++#define XMM2 2 ++#define XMM1 1 ++#define XMM0 0 ++ ++/* XDIV Divide control register - XDIV */ ++#define XDIVEN 7 ++#define XDIV6 6 ++#define XDIV5 5 ++#define XDIV4 4 ++#define XDIV3 3 ++#define XDIV2 2 ++#define XDIV1 1 ++#define XDIV0 0 ++ ++/* External Interrupt Control Register A - EICRA */ ++#define ISC31 7 ++#define ISC30 6 ++#define ISC21 5 ++#define ISC20 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* External Interrupt Control Register B - EICRB */ ++#define ISC71 7 ++#define ISC70 6 ++#define ISC61 5 ++#define ISC60 4 ++#define ISC51 3 ++#define ISC50 2 ++#define ISC41 1 ++#define ISC40 0 ++ ++/* Store Program Memory Control Register - SPMCSR, SPMCR */ ++#define SPMIE 7 ++#define RWWSB 6 ++#define RWWSRE 4 ++#define BLBSET 3 ++#define PGWRT 2 ++#define PGERS 1 ++#define SPMEN 0 ++ ++/* External Interrupt MaSK register - EIMSK */ ++#define INT7 7 ++#define INT6 6 ++#define INT5 5 ++#define INT4 4 ++#define INT3 3 ++#define INT2 2 ++#define INT1 1 ++#define INT0 0 ++ ++/* External Interrupt Flag Register - EIFR */ ++#define INTF7 7 ++#define INTF6 6 ++#define INTF5 5 ++#define INTF4 4 ++#define INTF3 3 ++#define INTF2 2 ++#define INTF1 1 ++#define INTF0 0 ++ ++/* Timer/Counter Interrupt MaSK register - TIMSK */ ++#define OCIE2 7 ++#define TOIE2 6 ++#define TICIE1 5 ++#define OCIE1A 4 ++#define OCIE1B 3 ++#define TOIE1 2 ++#define OCIE0 1 ++#define TOIE0 0 ++ ++/* Timer/Counter Interrupt Flag Register - TIFR */ ++#define OCF2 7 ++#define TOV2 6 ++#define ICF1 5 ++#define OCF1A 4 ++#define OCF1B 3 ++#define TOV1 2 ++#define OCF0 1 ++#define TOV0 0 ++ ++/* Extended Timer Interrupt MaSK register - ETIMSK */ ++#define TICIE3 5 ++#define OCIE3A 4 ++#define OCIE3B 3 ++#define TOIE3 2 ++#define OCIE3C 1 ++#define OCIE1C 0 ++ ++/* Extended Timer Interrupt Flag Register - ETIFR */ ++#define ICF3 5 ++#define OCF3A 4 ++#define OCF3B 3 ++#define TOV3 2 ++#define OCF3C 1 ++#define OCF1C 0 ++ ++/* MCU Control Register - MCUCR */ ++#define SRE 7 ++#define SRW10 6 ++#define SE 5 ++#define SM1 4 ++#define SM0 3 ++#define SM2 2 ++#define IVSEL 1 ++#define IVCE 0 ++ ++/* MCU Control And Status Register - MCUCSR */ ++#define JTD 7 ++#define JTRF 4 ++#define WDRF 3 ++#define BORF 2 ++#define EXTRF 1 ++#define PORF 0 ++ ++/* Timer/Counter Control Register (generic) */ ++#define FOC 7 ++#define WGM0 6 ++#define COM1 5 ++#define COM0 4 ++#define WGM1 3 ++#define CS2 2 ++#define CS1 1 ++#define CS0 0 ++ ++/* Timer/Counter 0 Control Register - TCCR0 */ ++#define FOC0 7 ++#define WGM00 6 ++#define COM01 5 ++#define COM00 4 ++#define WGM01 3 ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* Timer/Counter 2 Control Register - TCCR2 */ ++#define FOC2 7 ++#define WGM20 6 ++#define COM21 5 ++#define COM20 4 ++#define WGM21 3 ++#define CS22 2 ++#define CS21 1 ++#define CS20 0 ++ ++/* Timer/Counter 0 Asynchronous Control & Status Register - ASSR */ ++#define AS0 3 ++#define TCN0UB 2 ++#define OCR0UB 1 ++#define TCR0UB 0 ++ ++/* Timer/Counter Control Register A (generic) */ ++#define COMA1 7 ++#define COMA0 6 ++#define COMB1 5 ++#define COMB0 4 ++#define COMC1 3 ++#define COMC0 2 ++#define WGMA1 1 ++#define WGMA0 0 ++ ++/* Timer/Counter 1 Control and Status Register A - TCCR1A */ ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define COM1C1 3 ++#define COM1C0 2 ++#define WGM11 1 ++#define WGM10 0 ++ ++/* Timer/Counter 3 Control and Status Register A - TCCR3A */ ++#define COM3A1 7 ++#define COM3A0 6 ++#define COM3B1 5 ++#define COM3B0 4 ++#define COM3C1 3 ++#define COM3C0 2 ++#define WGM31 1 ++#define WGM30 0 ++ ++/* Timer/Counter Control and Status Register B (generic) */ ++#define ICNC 7 ++#define ICES 6 ++#define WGMB3 4 ++#define WGMB2 3 ++#define CSB2 2 ++#define CSB1 1 ++#define CSB0 0 ++ ++/* Timer/Counter 1 Control and Status Register B - TCCR1B */ ++#define ICNC1 7 ++#define ICES1 6 ++#define WGM13 4 ++#define WGM12 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* Timer/Counter 3 Control and Status Register B - TCCR3B */ ++#define ICNC3 7 ++#define ICES3 6 ++#define WGM33 4 ++#define WGM32 3 ++#define CS32 2 ++#define CS31 1 ++#define CS30 0 ++ ++/* Timer/Counter Control Register C (generic) */ ++#define FOCA 7 ++#define FOCB 6 ++#define FOCC 5 ++ ++/* Timer/Counter 3 Control Register C - TCCR3C */ ++#define FOC3A 7 ++#define FOC3B 6 ++#define FOC3C 5 ++ ++/* Timer/Counter 1 Control Register C - TCCR1C */ ++#define FOC1A 7 ++#define FOC1B 6 ++#define FOC1C 5 ++ ++/* On-chip Debug Register - OCDR */ ++#define IDRD 7 ++#define OCDR7 7 ++#define OCDR6 6 ++#define OCDR5 5 ++#define OCDR4 4 ++#define OCDR3 3 ++#define OCDR2 2 ++#define OCDR1 1 ++#define OCDR0 0 ++ ++/* Watchdog Timer Control Register - WDTCR */ ++#define WDCE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* ++ The ADHSM bit has been removed from all documentation, ++ as being not needed at all since the comparator has proven ++ to be fast enough even without feeding it more power. ++*/ ++ ++/* Special Function I/O Register - SFIOR */ ++#define TSM 7 ++#define ACME 3 ++#define PUD 2 ++#define PSR0 1 ++#define PSR321 0 ++ ++/* Port Data Register (generic) */ ++#define PORT7 7 ++#define PORT6 6 ++#define PORT5 5 ++#define PORT4 4 ++#define PORT3 3 ++#define PORT2 2 ++#define PORT1 1 ++#define PORT0 0 ++ ++/* Port Data Direction Register (generic) */ ++#define DD7 7 ++#define DD6 6 ++#define DD5 5 ++#define DD4 4 ++#define DD3 3 ++#define DD2 2 ++#define DD1 1 ++#define DD0 0 ++ ++/* Port Input Pins (generic) */ ++#define PIN7 7 ++#define PIN6 6 ++#define PIN5 5 ++#define PIN4 4 ++#define PIN3 3 ++#define PIN2 2 ++#define PIN1 1 ++#define PIN0 0 ++ ++/* SPI Status Register - SPSR */ ++#define SPIF 7 ++#define WCOL 6 ++#define SPI2X 0 ++ ++/* SPI Control Register - SPCR */ ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++/* USART Register C (generic) */ ++#define UMSEL 6 ++#define UPM1 5 ++#define UPM0 4 ++#define USBS 3 ++#define UCSZ1 2 ++#define UCSZ0 1 ++#define UCPOL 0 ++ ++/* USART1 Register C - UCSR1C */ ++#define UMSEL1 6 ++#define UPM11 5 ++#define UPM10 4 ++#define USBS1 3 ++#define UCSZ11 2 ++#define UCSZ10 1 ++#define UCPOL1 0 ++ ++/* USART0 Register C - UCSR0C */ ++#define UMSEL0 6 ++#define UPM01 5 ++#define UPM00 4 ++#define USBS0 3 ++#define UCSZ01 2 ++#define UCSZ00 1 ++#define UCPOL0 0 ++ ++/* USART Status Register A (generic) */ ++#define RXC 7 ++#define TXC 6 ++#define UDRE 5 ++#define FE 4 ++#define DOR 3 ++#define UPE 2 ++#define U2X 1 ++#define MPCM 0 ++ ++/* USART1 Status Register A - UCSR1A */ ++#define RXC1 7 ++#define TXC1 6 ++#define UDRE1 5 ++#define FE1 4 ++#define DOR1 3 ++#define UPE1 2 ++#define U2X1 1 ++#define MPCM1 0 ++ ++/* USART0 Status Register A - UCSR0A */ ++#define RXC0 7 ++#define TXC0 6 ++#define UDRE0 5 ++#define FE0 4 ++#define DOR0 3 ++#define UPE0 2 ++#define U2X0 1 ++#define MPCM0 0 ++ ++/* USART Control Register B (generic) */ ++#define RXCIE 7 ++#define TXCIE 6 ++#define UDRIE 5 ++#define RXEN 4 ++#define TXEN 3 ++#define UCSZ 2 ++#define UCSZ2 2 /* new name in datasheet (2467E-AVR-05/02) */ ++#define RXB8 1 ++#define TXB8 0 ++ ++/* USART1 Control Register B - UCSR1B */ ++#define RXCIE1 7 ++#define TXCIE1 6 ++#define UDRIE1 5 ++#define RXEN1 4 ++#define TXEN1 3 ++#define UCSZ12 2 ++#define RXB81 1 ++#define TXB81 0 ++ ++/* USART0 Control Register B - UCSR0B */ ++#define RXCIE0 7 ++#define TXCIE0 6 ++#define UDRIE0 5 ++#define RXEN0 4 ++#define TXEN0 3 ++#define UCSZ02 2 ++#define RXB80 1 ++#define TXB80 0 ++ ++/* Analog Comparator Control and Status Register - ACSR */ ++#define ACD 7 ++#define ACBG 6 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++/* ADC Control and Status Register B - ADCSRB */ ++#define ADTS2 2 ++#define ADTS1 1 ++#define ADTS0 0 ++ ++/* ADC Control and status Register A - ADCSRA */ ++#define ADEN 7 ++#define ADSC 6 ++#define ADATE 5 ++#define ADIF 4 ++#define ADIE 3 ++#define ADPS2 2 ++#define ADPS1 1 ++#define ADPS0 0 ++ ++/* ADC Multiplexer select - ADMUX */ ++#define REFS1 7 ++#define REFS0 6 ++#define ADLAR 5 ++#define MUX4 4 ++#define MUX3 3 ++#define MUX2 2 ++#define MUX1 1 ++#define MUX0 0 ++ ++/* Port A Data Register - PORTA */ ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++/* Port A Data Direction Register - DDRA */ ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++/* Port A Input Pins - PINA */ ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++/* Port B Data Register - PORTB */ ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* Port B Data Direction Register - DDRB */ ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* Port B Input Pins - PINB */ ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* Port C Data Register - PORTC */ ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++/* Port C Data Direction Register - DDRC */ ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++/* Port C Input Pins - PINC */ ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++/* Port D Data Register - PORTD */ ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* Port D Data Direction Register - DDRD */ ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++/* Port D Input Pins - PIND */ ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++/* Port E Data Register - PORTE */ ++#define PE7 7 ++#define PE6 6 ++#define PE5 5 ++#define PE4 4 ++#define PE3 3 ++#define PE2 2 ++#define PE1 1 ++#define PE0 0 ++ ++/* Port E Data Direction Register - DDRE */ ++#define DDE7 7 ++#define DDE6 6 ++#define DDE5 5 ++#define DDE4 4 ++#define DDE3 3 ++#define DDE2 2 ++#define DDE1 1 ++#define DDE0 0 ++ ++/* Port E Input Pins - PINE */ ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++/* Port F Data Register - PORTF */ ++#define PF7 7 ++#define PF6 6 ++#define PF5 5 ++#define PF4 4 ++#define PF3 3 ++#define PF2 2 ++#define PF1 1 ++#define PF0 0 ++ ++/* Port F Data Direction Register - DDRF */ ++#define DDF7 7 ++#define DDF6 6 ++#define DDF5 5 ++#define DDF4 4 ++#define DDF3 3 ++#define DDF2 2 ++#define DDF1 1 ++#define DDF0 0 ++ ++/* Port F Input Pins - PINF */ ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++/* Port G Data Register - PORTG */ ++#define PG4 4 ++#define PG3 3 ++#define PG2 2 ++#define PG1 1 ++#define PG0 0 ++ ++/* Port G Data Direction Register - DDRG */ ++#define DDG4 4 ++#define DDG3 3 ++#define DDG2 2 ++#define DDG1 1 ++#define DDG0 0 ++ ++/* Port G Input Pins - PING */ ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++/* EEPROM Control Register */ ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++/* Constants */ ++#define SPM_PAGESIZE 256 ++#define RAMSTART 0x100 ++#define RAMEND 0x10FF /* Last On-Chip SRAM Location */ ++#define XRAMEND 0xFFFF ++#define E2END 0x07FF ++#define E2PAGESIZE 8 ++#define FLASHEND 0xFFFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_BODEN (unsigned char)~_BV(6) ++#define FUSE_BODLEVEL (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_CKOPT (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_WDTON (unsigned char)~_BV(0) ++#define FUSE_M103C (unsigned char)~_BV(1) ++#define EFUSE_DEFAULT (FUSE_M103C) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x02 ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_INTERRUPT1 ++#pragma GCC poison SIG_INTERRUPT2 ++#pragma GCC poison SIG_INTERRUPT3 ++#pragma GCC poison SIG_INTERRUPT4 ++#pragma GCC poison SIG_INTERRUPT5 ++#pragma GCC poison SIG_INTERRUPT6 ++#pragma GCC poison SIG_INTERRUPT7 ++#pragma GCC poison SIG_OUTPUT_COMPARE2 ++#pragma GCC poison SIG_OVERFLOW2 ++#pragma GCC poison SIG_INPUT_CAPTURE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OUTPUT_COMPARE0 ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_SPI ++#pragma GCC poison SIG_UART0_RECV ++#pragma GCC poison SIG_UART0_DATA ++#pragma GCC poison SIG_UART0_TRANS ++#pragma GCC poison SIG_ADC ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_OUTPUT_COMPARE1C ++#pragma GCC poison SIG_INPUT_CAPTURE3 ++#pragma GCC poison SIG_OUTPUT_COMPARE3A ++#pragma GCC poison SIG_OUTPUT_COMPARE3B ++#pragma GCC poison SIG_OUTPUT_COMPARE3C ++#pragma GCC poison SIG_OVERFLOW3 ++#pragma GCC poison SIG_UART1_RECV ++#pragma GCC poison SIG_UART1_DATA ++#pragma GCC poison SIG_UART1_TRANS ++#pragma GCC poison SIG_2WIRE_SERIAL ++#pragma GCC poison SIG_SPM_READY ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++#endif /* _AVR_IOM64_H_ */ +diff --git a/include/avr/iom640.h b/include/avr/iom640.h +index 3f8ea62..0f5bf90 100644 +--- a/include/avr/iom640.h ++++ b/include/avr/iom640.h +@@ -1,94 +1,95 @@ +-/* Copyright (c) 2005 Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom640.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ +- +-/* avr/iom640.h - definitions for ATmega640 */ +- +-#ifndef _AVR_IOM640_H_ +-#define _AVR_IOM640_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 256 +-#define RAMEND 0x21FF +-#define XRAMEND 0xFFFF +-#define E2END 0xFFF +-#define E2PAGESIZE 8 +-#define FLASHEND 0xFFFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x96 +-#define SIGNATURE_2 0x08 +- +- +-#endif /* _AVR_IOM640_H_ */ ++/* Copyright (c) 2005 Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom640.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ ++ ++/* avr/iom640.h - definitions for ATmega640 */ ++ ++#ifndef _AVR_IOM640_H_ ++#define _AVR_IOM640_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 256 ++#define RAMSTART 0x200 ++#define RAMEND 0x21FF ++#define XRAMEND 0xFFFF ++#define E2END 0xFFF ++#define E2PAGESIZE 8 ++#define FLASHEND 0xFFFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x08 ++ ++ ++#endif /* _AVR_IOM640_H_ */ +diff --git a/include/avr/iom644.h b/include/avr/iom644.h +index cca3269..e381651 100644 +--- a/include/avr/iom644.h ++++ b/include/avr/iom644.h +@@ -1,95 +1,95 @@ +-/* Copyright (c) 2005 Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* avr/iom644.h - definitions for ATmega644 */ +- +-/* $Id: iom644.h 2115 2010-04-05 23:19:53Z arcanum $ */ +- +-#ifndef _AVR_IOM644_H_ +-#define _AVR_IOM644_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 256 +-#define RAMSTART (0x100) +-#define RAMEND 0x10FF +-#define XRAMEND RAMEND +-#define E2END 0x7FF +-#define E2PAGESIZE 8 +-#define FLASHEND 0xFFFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x96 +-#define SIGNATURE_2 0x09 +- +- +-#endif /* _AVR_IOM644_H_ */ ++/* Copyright (c) 2005 Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* avr/iom644.h - definitions for ATmega644 */ ++ ++/* $Id: iom644.h 2115 2010-04-05 23:19:53Z arcanum $ */ ++ ++#ifndef _AVR_IOM644_H_ ++#define _AVR_IOM644_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 256 ++#define RAMSTART (0x100) ++#define RAMEND 0x10FF ++#define XRAMEND RAMEND ++#define E2END 0x7FF ++#define E2PAGESIZE 8 ++#define FLASHEND 0xFFFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x09 ++ ++ ++#endif /* _AVR_IOM644_H_ */ diff --git a/include/avr/iom644a.h b/include/avr/iom644a.h new file mode 100644 -index 0000000..ca63331 +index 0000000..49d4e3b --- /dev/null +++ b/include/avr/iom644a.h @@ -0,0 +1,34 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2011 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+#include "iom644.h" ++/***************************************************************************** ++ * ++ * Copyright (C) 2011 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++#include "iom644.h" +diff --git a/include/avr/iom644p.h b/include/avr/iom644p.h +index 1480a93..e788c0e 100644 +--- a/include/avr/iom644p.h ++++ b/include/avr/iom644p.h +@@ -1,95 +1,95 @@ +-/* Copyright (c) 2005 Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* avr/iom644p.h - definitions for ATmega644P */ +- +-/* $Id: iom644p.h 2115 2010-04-05 23:19:53Z arcanum $ */ +- +-#ifndef _AVR_IOM644P_H_ +-#define _AVR_IOM644P_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 256 +-#define RAMSTART (0x100) +-#define RAMEND 0x10FF +-#define XRAMEND RAMEND +-#define E2END 0x7FF +-#define E2PAGESIZE 8 +-#define FLASHEND 0xFFFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x96 +-#define SIGNATURE_2 0x0A +- +- +-#endif /* _AVR_IOM644P_H_ */ ++/* Copyright (c) 2005 Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* avr/iom644p.h - definitions for ATmega644P */ ++ ++/* $Id: iom644p.h 2115 2010-04-05 23:19:53Z arcanum $ */ ++ ++#ifndef _AVR_IOM644P_H_ ++#define _AVR_IOM644P_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 256 ++#define RAMSTART (0x100) ++#define RAMEND 0x10FF ++#define XRAMEND RAMEND ++#define E2END 0x7FF ++#define E2PAGESIZE 8 ++#define FLASHEND 0xFFFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x0A ++ ++ ++#endif /* _AVR_IOM644P_H_ */ +diff --git a/include/avr/iom644pa.h b/include/avr/iom644pa.h +index 3d43083..98f4d4f 100644 +--- a/include/avr/iom644pa.h ++++ b/include/avr/iom644pa.h +@@ -1,1370 +1,1370 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom644pa.h 2035 2009-11-02 02:44:17Z arcanum $ */ +- +-/* avr/iom644PA.h - definitions for ATmega644PA */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom644PA.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATmega644PA_H_ +-#define _AVR_ATmega644PA_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +-#define PINA4 4 +-#define PINA5 5 +-#define PINA6 6 +-#define PINA7 7 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +-#define DDA4 4 +-#define DDA5 5 +-#define DDA6 6 +-#define DDA7 7 +- +-#define PORTA _SFR_IO8(0x02) +-#define PORTA0 0 +-#define PORTA1 1 +-#define PORTA2 2 +-#define PORTA3 3 +-#define PORTA4 4 +-#define PORTA5 5 +-#define PORTA6 6 +-#define PORTA7 7 +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +-#define PINC7 7 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC3 3 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +-#define DDC7 7 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC3 3 +-#define PORTC4 4 +-#define PORTC5 5 +-#define PORTC6 6 +-#define PORTC7 7 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define TIFR2 _SFR_IO8(0x17) +-#define TOV2 0 +-#define OCF2A 1 +-#define OCF2B 2 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +-#define PCIF1 1 +-#define PCIF2 2 +-#define PCIF3 3 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +-#define INTF2 2 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +-#define INT2 2 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +-#define EEAR9 1 +-#define EEAR10 2 +-#define EEAR11 3 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSRSYNC 0 +-#define PSRASY 1 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define OCR0A _SFR_IO8(0x27) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define OCR0B _SFR_IO8(0x28) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define OCDR _SFR_IO8(0x31) +-#define OCDR0 0 +-#define OCDR1 1 +-#define OCDR2 2 +-#define OCDR3 3 +-#define OCDR4 4 +-#define OCDR5 5 +-#define OCDR6 6 +-#define OCDR7 7 +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +-#define JTRF 4 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define BODSE 5 +-#define BODS 6 +-#define JTD 7 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define SIGRD 5 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define PRR0 _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM1 3 +-#define PRUSART1 4 +-#define PRTIM0 5 +-#define PRTIM2 6 +-#define PRTWI 7 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +-#define PCIE1 1 +-#define PCIE2 2 +-#define PCIE3 3 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define ISC20 4 +-#define ISC21 5 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-#define PCMSK2 _SFR_MEM8(0x6D) +-#define PCINT16 0 +-#define PCINT17 1 +-#define PCINT18 2 +-#define PCINT19 3 +-#define PCINT20 4 +-#define PCINT21 5 +-#define PCINT22 6 +-#define PCINT23 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define TIMSK2 _SFR_MEM8(0x70) +-#define TOIE2 0 +-#define OCIE2A 1 +-#define OCIE2B 2 +- +-#define PCMSK3 _SFR_MEM8(0x73) +-#define PCINT24 0 +-#define PCINT25 1 +-#define PCINT26 2 +-#define PCINT27 3 +-#define PCINT28 4 +-#define PCINT29 5 +-#define PCINT30 6 +-#define PCINT31 7 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +- +-#define ADCL _SFR_MEM8(0x78) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_MEM8(0x79) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ACME 6 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define TCCR2A _SFR_MEM8(0xB0) +-#define WGM20 0 +-#define WGM21 1 +-#define COM2B0 4 +-#define COM2B1 5 +-#define COM2A0 6 +-#define COM2A1 7 +- +-#define TCCR2B _SFR_MEM8(0xB1) +-#define CS20 0 +-#define CS21 1 +-#define CS22 2 +-#define WGM22 3 +-#define FOC2B 6 +-#define FOC2A 7 +- +-#define TCNT2 _SFR_MEM8(0xB2) +-#define TCNT2_0 0 +-#define TCNT2_1 1 +-#define TCNT2_2 2 +-#define TCNT2_3 3 +-#define TCNT2_4 4 +-#define TCNT2_5 5 +-#define TCNT2_6 6 +-#define TCNT2_7 7 +- +-#define OCR2A _SFR_MEM8(0xB3) +-#define OCR2A_0 0 +-#define OCR2A_1 1 +-#define OCR2A_2 2 +-#define OCR2A_3 3 +-#define OCR2A_4 4 +-#define OCR2A_5 5 +-#define OCR2A_6 6 +-#define OCR2A_7 7 +- +-#define OCR2B _SFR_MEM8(0xB4) +-#define OCR2B_0 0 +-#define OCR2B_1 1 +-#define OCR2B_2 2 +-#define OCR2B_3 3 +-#define OCR2B_4 4 +-#define OCR2B_5 5 +-#define OCR2B_6 6 +-#define OCR2B_7 7 +- +-#define ASSR _SFR_MEM8(0xB6) +-#define TCR2BUB 0 +-#define TCR2AUB 1 +-#define OCR2BUB 2 +-#define OCR2AUB 3 +-#define TCN2UB 4 +-#define AS2 5 +-#define EXCLK 6 +- +-#define TWBR _SFR_MEM8(0xB8) +-#define TWBR0 0 +-#define TWBR1 1 +-#define TWBR2 2 +-#define TWBR3 3 +-#define TWBR4 4 +-#define TWBR5 5 +-#define TWBR6 6 +-#define TWBR7 7 +- +-#define TWSR _SFR_MEM8(0xB9) +-#define TWPS0 0 +-#define TWPS1 1 +-#define TWS3 3 +-#define TWS4 4 +-#define TWS5 5 +-#define TWS6 6 +-#define TWS7 7 +- +-#define TWAR _SFR_MEM8(0xBA) +-#define TWGCE 0 +-#define TWA0 1 +-#define TWA1 2 +-#define TWA2 3 +-#define TWA3 4 +-#define TWA4 5 +-#define TWA5 6 +-#define TWA6 7 +- +-#define TWDR _SFR_MEM8(0xBB) +-#define TWD0 0 +-#define TWD1 1 +-#define TWD2 2 +-#define TWD3 3 +-#define TWD4 4 +-#define TWD5 5 +-#define TWD6 6 +-#define TWD7 7 +- +-#define TWCR _SFR_MEM8(0xBC) +-#define TWIE 0 +-#define TWEN 2 +-#define TWWC 3 +-#define TWSTO 4 +-#define TWSTA 5 +-#define TWEA 6 +-#define TWINT 7 +- +-#define TWAMR _SFR_MEM8(0xBD) +-#define TWAM0 1 +-#define TWAM1 2 +-#define TWAM2 3 +-#define TWAM3 4 +-#define TWAM4 5 +-#define TWAM5 6 +-#define TWAM6 7 +- +-#define UCSR0A _SFR_MEM8(0xC0) +-#define MPCM0 0 +-#define U2X0 1 +-#define UPE0 2 +-#define DOR0 3 +-#define FE0 4 +-#define UDRE0 5 +-#define TXC0 6 +-#define RXC0 7 +- +-#define UCSR0B _SFR_MEM8(0xC1) +-#define TXB80 0 +-#define RXB80 1 +-#define UCSZ02 2 +-#define TXEN0 3 +-#define RXEN0 4 +-#define UDRIE0 5 +-#define TXCIE0 6 +-#define RXCIE0 7 +- +-#define UCSR0C _SFR_MEM8(0xC2) +-#define UCPOL0 0 +-#define UCSZ00 1 +-#define UCSZ01 2 +-#define USBS0 3 +-#define UPM00 4 +-#define UPM01 5 +-#define UMSEL00 6 +-#define UMSEL01 7 +- +-#define UBRR0 _SFR_MEM16(0xC4) +- +-#define UBRR0L _SFR_MEM8(0xC4) +-#define _UBRR0 0 +-#define _UBRR1 1 +-#define UBRR2 2 +-#define UBRR3 3 +-#define UBRR4 4 +-#define UBRR5 5 +-#define UBRR6 6 +-#define UBRR7 7 +- +-#define UBRR0H _SFR_MEM8(0xC5) +-#define UBRR8 0 +-#define UBRR9 1 +-#define UBRR10 2 +-#define UBRR11 3 +- +-#define UDR0 _SFR_MEM8(0xC6) +-#define UDR0_0 0 +-#define UDR0_1 1 +-#define UDR0_2 2 +-#define UDR0_3 3 +-#define UDR0_4 4 +-#define UDR0_5 5 +-#define UDR0_6 6 +-#define UDR0_7 7 +- +-#define UCSR1A _SFR_MEM8(0xC8) +-#define MPCM1 0 +-#define U2X1 1 +-#define UPE1 2 +-#define DOR1 3 +-#define FE1 4 +-#define UDRE1 5 +-#define TXC1 6 +-#define RXC1 7 +- +-#define UCSR1B _SFR_MEM8(0xC9) +-#define TXB81 0 +-#define RXB81 1 +-#define UCSZ12 2 +-#define TXEN1 3 +-#define RXEN1 4 +-#define UDRIE1 5 +-#define TXCIE1 6 +-#define RXCIE1 7 +- +-#define UCSR1C _SFR_MEM8(0xCA) +-#define UCPOL1 0 +-#define UCSZ10 1 +-#define UCSZ11 2 +-#define USBS1 3 +-#define UPM10 4 +-#define UPM11 5 +-#define UMSEL10 6 +-#define UMSEL11 7 +- +-#define UBRR1 _SFR_MEM16(0xCC) +- +-#define UBRR1L _SFR_MEM8(0xCC) +-#define UBRR_0 0 +-#define UBRR_1 1 +-#define UBRR_2 2 +-#define UBRR_3 3 +-#define UBRR_4 4 +-#define UBRR_5 5 +-#define UBRR_6 6 +-#define UBRR_7 7 +- +-#define UBRR1H _SFR_MEM8(0xCD) +-#define UBRR_8 0 +-#define UBRR_9 1 +-#define UBRR_10 2 +-#define UBRR_11 3 +- +-#define UDR1 _SFR_MEM8(0xCE) +-#define UDR1_0 0 +-#define UDR1_1 1 +-#define UDR1_2 2 +-#define UDR1_3 3 +-#define UDR1_4 4 +-#define UDR1_5 5 +-#define UDR1_6 6 +-#define UDR1_7 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ +-#define INT2_vect_num 3 +-#define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ +-#define PCINT0_vect_num 4 +-#define PCINT0_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */ +-#define PCINT1_vect_num 5 +-#define PCINT1_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */ +-#define PCINT2_vect_num 6 +-#define PCINT2_vect _VECTOR(6) /* Pin Change Interrupt Request 2 */ +-#define PCINT3_vect_num 7 +-#define PCINT3_vect _VECTOR(7) /* Pin Change Interrupt Request 3 */ +-#define WDT_vect_num 8 +-#define WDT_vect _VECTOR(8) /* Watchdog Time-out Interrupt */ +-#define TIMER2_COMPA_vect_num 9 +-#define TIMER2_COMPA_vect _VECTOR(9) /* Timer/Counter2 Compare Match A */ +-#define TIMER2_COMPB_vect_num 10 +-#define TIMER2_COMPB_vect _VECTOR(10) /* Timer/Counter2 Compare Match B */ +-#define TIMER2_OVF_vect_num 11 +-#define TIMER2_OVF_vect _VECTOR(11) /* Timer/Counter2 Overflow */ +-#define TIMER1_CAPT_vect_num 12 +-#define TIMER1_CAPT_vect _VECTOR(12) /* Timer/Counter1 Capture Event */ +-#define TIMER1_COMPA_vect_num 13 +-#define TIMER1_COMPA_vect _VECTOR(13) /* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPB_vect_num 14 +-#define TIMER1_COMPB_vect _VECTOR(14) /* Timer/Counter1 Compare Match B */ +-#define TIMER1_OVF_vect_num 15 +-#define TIMER1_OVF_vect _VECTOR(15) /* Timer/Counter1 Overflow */ +-#define TIMER0_COMPA_vect_num 16 +-#define TIMER0_COMPA_vect _VECTOR(16) /* Timer/Counter0 Compare Match A */ +-#define TIMER0_COMPB_vect_num 17 +-#define TIMER0_COMPB_vect _VECTOR(17) /* Timer/Counter0 Compare Match B */ +-#define TIMER0_OVF_vect_num 18 +-#define TIMER0_OVF_vect _VECTOR(18) /* Timer/Counter0 Overflow */ +-#define SPI_STC_vect_num 19 +-#define SPI_STC_vect _VECTOR(19) /* SPI Serial Transfer Complete */ +-#define USART0_RX_vect_num 20 +-#define USART0_RX_vect _VECTOR(20) /* USART0, Rx Complete */ +-#define USART0_UDRE_vect_num 21 +-#define USART0_UDRE_vect _VECTOR(21) /* USART0 Data register Empty */ +-#define USART0_TX_vect_num 22 +-#define USART0_TX_vect _VECTOR(22) /* USART0, Tx Complete */ +-#define ANALOG_COMP_vect_num 23 +-#define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */ +-#define ADC_vect_num 24 +-#define ADC_vect _VECTOR(24) /* ADC Conversion Complete */ +-#define EE_READY_vect_num 25 +-#define EE_READY_vect _VECTOR(25) /* EEPROM Ready */ +-#define TWI_vect_num 26 +-#define TWI_vect _VECTOR(26) /* 2-wire Serial Interface */ +-#define SPM_READY_vect_num 27 +-#define SPM_READY_vect _VECTOR(27) /* Store Program Memory Read */ +-#define USART1_RX_vect_num 28 +-#define USART1_RX_vect _VECTOR(28) /* USART1 RX complete */ +-#define USART1_UDRE_vect_num 29 +-#define USART1_UDRE_vect _VECTOR(29) /* USART1 Data Register Empty */ +-#define USART1_TX_vect_num 30 +-#define USART1_TX_vect _VECTOR(30) /* USART1 TX complete */ +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (31 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (256) +-#define RAMSTART (0x100) +-#define RAMSIZE (4096) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (0x0) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x7FF) +-#define E2PAGESIZE (8) +-#define FLASHEND (0xFFFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ +-#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ +-#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x96 +-#define SIGNATURE_2 0x0A +- +- +-/* Device Pin Definitions */ +-#define MOSI_DDR DDRB +-#define MOSI_PORT PORTB +-#define MOSI_PIN PINB +-#define MOSI_BIT 5 +- +-#define PCINT13_DDR DDRB +-#define PCINT13_PORT PORTB +-#define PCINT13_PIN PINB +-#define PCINT13_BIT 5 +- +-#define MISO_DDR DDRB +-#define MISO_PORT PORTB +-#define MISO_PIN PINB +-#define MISO_BIT 6 +- +-#define PCINT14_DDR DDRB +-#define PCINT14_PORT PORTB +-#define PCINT14_PIN PINB +-#define PCINT14_BIT 6 +- +-#define SCK_DDR DDRB +-#define SCK_PORT PORTB +-#define SCK_PIN PINB +-#define SCK_BIT 7 +- +-#define PCINT15_DDR DDRB +-#define PCINT15_PORT PORTB +-#define PCINT15_PIN PINB +-#define PCINT15_BIT 7 +- +-#define RXD_DDR DDRD +-#define RXD_PORT PORTD +-#define RXD_PIN PIND +-#define RXD_BIT 0 +- +-#define PCINT24_DDR DDRD +-#define PCINT24_PORT PORTD +-#define PCINT24_PIN PIND +-#define PCINT24_BIT 0 +- +-#define TXD_DDR DDRD +-#define TXD_PORT PORTD +-#define TXD_PIN PIND +-#define TXD_BIT 1 +- +-#define PCINT25_DDR DDRD +-#define PCINT25_PORT PORTD +-#define PCINT25_PIN PIND +-#define PCINT25_BIT 1 +- +-#define INT0_DDR DDRD +-#define INT0_PORT PORTD +-#define INT0_PIN PIND +-#define INT0_BIT 2 +- +-#define RDX1_DDR DDRD +-#define RDX1_PORT PORTD +-#define RDX1_PIN PIND +-#define RDX1_BIT 2 +- +-#define PCINT26_DDR DDRD +-#define PCINT26_PORT PORTD +-#define PCINT26_PIN PIND +-#define PCINT26_BIT 2 +- +-#define INT1_DDR DDRD +-#define INT1_PORT PORTD +-#define INT1_PIN PIND +-#define INT1_BIT 3 +- +-#define TXD1_DDR DDRD +-#define TXD1_PORT PORTD +-#define TXD1_PIN PIND +-#define TXD1_BIT 3 +- +-#define PCINT27_DDR DDRD +-#define PCINT27_PORT PORTD +-#define PCINT27_PIN PIND +-#define PCINT27_BIT 3 +- +-#define OC1B_DDR DDRD +-#define OC1B_PORT PORTD +-#define OC1B_PIN PIND +-#define OC1B_BIT 4 +- +-#define XCK1_DDR DDRD +-#define XCK1_PORT PORTD +-#define XCK1_PIN PIND +-#define XCK1_BIT 4 +- +-#define PCINT28_DDR DDRD +-#define PCINT28_PORT PORTD +-#define PCINT28_PIN PIND +-#define PCINT28_BIT 4 +- +-#define OC1A_DDR DDRD +-#define OC1A_PORT PORTD +-#define OC1A_PIN PIND +-#define OC1A_BIT 5 +- +-#define PCINT29_DDR DDRD +-#define PCINT29_PORT PORTD +-#define PCINT29_PIN PIND +-#define PCINT29_BIT 5 +- +-#define ICP_DDR DDRD +-#define ICP_PORT PORTD +-#define ICP_PIN PIND +-#define ICP_BIT 6 +- +-#define OC2B_DDR DDRD +-#define OC2B_PORT PORTD +-#define OC2B_PIN PIND +-#define OC2B_BIT 6 +- +-#define PCINT30_DDR DDRD +-#define PCINT30_PORT PORTD +-#define PCINT30_PIN PIND +-#define PCINT30_BIT 6 +- +-#define OC2A_DDR DDRD +-#define OC2A_PORT PORTD +-#define OC2A_PIN PIND +-#define OC2A_BIT 7 +- +-#define PCINT31_DDR DDRD +-#define PCINT31_PORT PORTD +-#define PCINT31_PIN PIND +-#define PCINT31_BIT 7 +- +-#define SCL_DDR DDRC +-#define SCL_PORT PORTC +-#define SCL_PIN PINC +-#define SCL_BIT 0 +- +-#define PCINT16_DDR DDRC +-#define PCINT16_PORT PORTC +-#define PCINT16_PIN PINC +-#define PCINT16_BIT 0 +- +-#define SDA_DDR DDRC +-#define SDA_PORT PORTC +-#define SDA_PIN PINC +-#define SDA_BIT 1 +- +-#define PCINT17_DDR DDRC +-#define PCINT17_PORT PORTC +-#define PCINT17_PIN PINC +-#define PCINT17_BIT 1 +- +-#define PCINT18_DDR DDRC +-#define PCINT18_PORT PORTC +-#define PCINT18_PIN PINC +-#define PCINT18_BIT 2 +- +-#define PCINT19_DDR DDRC +-#define PCINT19_PORT PORTC +-#define PCINT19_PIN PINC +-#define PCINT19_BIT 3 +- +-#define PCINT20_DDR DDRC +-#define PCINT20_PORT PORTC +-#define PCINT20_PIN PINC +-#define PCINT20_BIT 4 +- +-#define PCINT21_DDR DDRC +-#define PCINT21_PORT PORTC +-#define PCINT21_PIN PINC +-#define PCINT21_BIT 5 +- +-#define PCINT22_DDR DDRC +-#define PCINT22_PORT PORTC +-#define PCINT22_PIN PINC +-#define PCINT22_BIT 6 +- +-#define PCINT23_DDR DDRC +-#define PCINT23_PORT PORTC +-#define PCINT23_PIN PINC +-#define PCINT23_BIT 7 +- +-#define ADC7_DDR DDRA +-#define ADC7_PORT PORTA +-#define ADC7_PIN PINA +-#define ADC7_BIT 7 +- +-#define PCINT7_DDR DDRA +-#define PCINT7_PORT PORTA +-#define PCINT7_PIN PINA +-#define PCINT7_BIT 7 +- +-#define ADC6_DDR DDRA +-#define ADC6_PORT PORTA +-#define ADC6_PIN PINA +-#define ADC6_BIT 6 +- +-#define PCINT6_DDR DDRA +-#define PCINT6_PORT PORTA +-#define PCINT6_PIN PINA +-#define PCINT6_BIT 6 +- +-#define ADC5_DDR DDRA +-#define ADC5_PORT PORTA +-#define ADC5_PIN PINA +-#define ADC5_BIT 5 +- +-#define PCINT5_DDR DDRA +-#define PCINT5_PORT PORTA +-#define PCINT5_PIN PINA +-#define PCINT5_BIT 5 +- +-#define ADC4_DDR DDRA +-#define ADC4_PORT PORTA +-#define ADC4_PIN PINA +-#define ADC4_BIT 4 +- +-#define PCINT4_DDR DDRA +-#define PCINT4_PORT PORTA +-#define PCINT4_PIN PINA +-#define PCINT4_BIT 4 +- +-#define ADC3_DDR DDRA +-#define ADC3_PORT PORTA +-#define ADC3_PIN PINA +-#define ADC3_BIT 3 +- +-#define PCINT3_DDR DDRA +-#define PCINT3_PORT PORTA +-#define PCINT3_PIN PINA +-#define PCINT3_BIT 3 +- +-#define ADC2_DDR DDRA +-#define ADC2_PORT PORTA +-#define ADC2_PIN PINA +-#define ADC2_BIT 2 +- +-#define PCINT2_DDR DDRA +-#define PCINT2_PORT PORTA +-#define PCINT2_PIN PINA +-#define PCINT2_BIT 2 +- +-#define ADC1_DDR DDRA +-#define ADC1_PORT PORTA +-#define ADC1_PIN PINA +-#define ADC1_BIT 1 +- +-#define PCINT1_DDR DDRA +-#define PCINT1_PORT PORTA +-#define PCINT1_PIN PINA +-#define PCINT1_BIT 1 +- +-#define ADC0_DDR DDRA +-#define ADC0_PORT PORTA +-#define ADC0_PIN PINA +-#define ADC0_BIT 0 +- +-#define PCINT0_DDR DDRA +-#define PCINT0_PORT PORTA +-#define PCINT0_PIN PINA +-#define PCINT0_BIT 0 +- +-#define XCK_DDR DDRB +-#define XCK_PORT PORTB +-#define XCK_PIN PINB +-#define XCK_BIT 0 +- +-#define T0_DDR DDRB +-#define T0_PORT PORTB +-#define T0_PIN PINB +-#define T0_BIT 0 +- +-#define PCINT8_DDR DDRB +-#define PCINT8_PORT PORTB +-#define PCINT8_PIN PINB +-#define PCINT8_BIT 0 +- +-#define T1_DDR DDRB +-#define T1_PORT PORTB +-#define T1_PIN PINB +-#define T1_BIT 1 +- +-#define CLKO_DDR DDRB +-#define CLKO_PORT PORTB +-#define CLKO_PIN PINB +-#define CLKO_BIT 1 +- +-#define PCINT9_DDR DDRB +-#define PCINT9_PORT PORTB +-#define PCINT9_PIN PINB +-#define PCINT9_BIT 1 +- +-#define AIN0_DDR DDRB +-#define AIN0_PORT PORTB +-#define AIN0_PIN PINB +-#define AIN0_BIT 2 +- +-#define INT2_DDR DDRB +-#define INT2_PORT PORTB +-#define INT2_PIN PINB +-#define INT2_BIT 2 +- +-#define PCINT10_DDR DDRB +-#define PCINT10_PORT PORTB +-#define PCINT10_PIN PINB +-#define PCINT10_BIT 2 +- +-#define AIN1_DDR DDRB +-#define AIN1_PORT PORTB +-#define AIN1_PIN PINB +-#define AIN1_BIT 3 +- +-#define OC0A_DDR DDRB +-#define OC0A_PORT PORTB +-#define OC0A_PIN PINB +-#define OC0A_BIT 3 +- +-#define PCINT11_DDR DDRB +-#define PCINT11_PORT PORTB +-#define PCINT11_PIN PINB +-#define PCINT11_BIT 3 +- +-#define SS_DDR DDRB +-#define SS_PORT PORTB +-#define SS_PIN PINB +-#define SS_BIT 4 +- +-#define OC0B_DDR DDRB +-#define OC0B_PORT PORTB +-#define OC0B_PIN PINB +-#define OC0B_BIT 4 +- +-#define PCINT12_DDR DDRB +-#define PCINT12_PORT PORTB +-#define PCINT12_PIN PINB +-#define PCINT12_BIT 4 +- +-#endif /* _AVR_ATmega644PA_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom644pa.h 2035 2009-11-02 02:44:17Z arcanum $ */ ++ ++/* avr/iom644PA.h - definitions for ATmega644PA */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom644PA.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATmega644PA_H_ ++#define _AVR_ATmega644PA_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++#define PINA4 4 ++#define PINA5 5 ++#define PINA6 6 ++#define PINA7 7 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++#define DDA4 4 ++#define DDA5 5 ++#define DDA6 6 ++#define DDA7 7 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA0 0 ++#define PORTA1 1 ++#define PORTA2 2 ++#define PORTA3 3 ++#define PORTA4 4 ++#define PORTA5 5 ++#define PORTA6 6 ++#define PORTA7 7 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++#define PINC7 7 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++#define DDC7 7 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC3 3 ++#define PORTC4 4 ++#define PORTC5 5 ++#define PORTC6 6 ++#define PORTC7 7 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++#define PCIF3 3 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++#define EEAR9 1 ++#define EEAR10 2 ++#define EEAR11 3 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define PSRASY 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define OCR0A _SFR_IO8(0x27) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define OCR0B _SFR_IO8(0x28) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCDR7 7 ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define JTRF 4 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++#define JTD 7 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRUSART1 4 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++#define PCIE3 3 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++#define PCMSK3 _SFR_MEM8(0x73) ++#define PCINT24 0 ++#define PCINT25 1 ++#define PCINT26 2 ++#define PCINT27 3 ++#define PCINT28 4 ++#define PCINT29 5 ++#define PCINT30 6 ++#define PCINT31 7 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_MEM8(0x79) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++#define TCNT2_0 0 ++#define TCNT2_1 1 ++#define TCNT2_2 2 ++#define TCNT2_3 3 ++#define TCNT2_4 4 ++#define TCNT2_5 5 ++#define TCNT2_6 6 ++#define TCNT2_7 7 ++ ++#define OCR2A _SFR_MEM8(0xB3) ++#define OCR2A_0 0 ++#define OCR2A_1 1 ++#define OCR2A_2 2 ++#define OCR2A_3 3 ++#define OCR2A_4 4 ++#define OCR2A_5 5 ++#define OCR2A_6 6 ++#define OCR2A_7 7 ++ ++#define OCR2B _SFR_MEM8(0xB4) ++#define OCR2B_0 0 ++#define OCR2B_1 1 ++#define OCR2B_2 2 ++#define OCR2B_3 3 ++#define OCR2B_4 4 ++#define OCR2B_5 5 ++#define OCR2B_6 6 ++#define OCR2B_7 7 ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++ ++#define TWBR _SFR_MEM8(0xB8) ++#define TWBR0 0 ++#define TWBR1 1 ++#define TWBR2 2 ++#define TWBR3 3 ++#define TWBR4 4 ++#define TWBR5 5 ++#define TWBR6 6 ++#define TWBR7 7 ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++#define TWD0 0 ++#define TWD1 1 ++#define TWD2 2 ++#define TWD3 3 ++#define TWD4 4 ++#define TWD5 5 ++#define TWD6 6 ++#define TWD7 7 ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define _UBRR0 0 ++#define _UBRR1 1 ++#define UBRR2 2 ++#define UBRR3 3 ++#define UBRR4 4 ++#define UBRR5 5 ++#define UBRR6 6 ++#define UBRR7 7 ++ ++#define UBRR0H _SFR_MEM8(0xC5) ++#define UBRR8 0 ++#define UBRR9 1 ++#define UBRR10 2 ++#define UBRR11 3 ++ ++#define UDR0 _SFR_MEM8(0xC6) ++#define UDR0_0 0 ++#define UDR0_1 1 ++#define UDR0_2 2 ++#define UDR0_3 3 ++#define UDR0_4 4 ++#define UDR0_5 5 ++#define UDR0_6 6 ++#define UDR0_7 7 ++ ++#define UCSR1A _SFR_MEM8(0xC8) ++#define MPCM1 0 ++#define U2X1 1 ++#define UPE1 2 ++#define DOR1 3 ++#define FE1 4 ++#define UDRE1 5 ++#define TXC1 6 ++#define RXC1 7 ++ ++#define UCSR1B _SFR_MEM8(0xC9) ++#define TXB81 0 ++#define RXB81 1 ++#define UCSZ12 2 ++#define TXEN1 3 ++#define RXEN1 4 ++#define UDRIE1 5 ++#define TXCIE1 6 ++#define RXCIE1 7 ++ ++#define UCSR1C _SFR_MEM8(0xCA) ++#define UCPOL1 0 ++#define UCSZ10 1 ++#define UCSZ11 2 ++#define USBS1 3 ++#define UPM10 4 ++#define UPM11 5 ++#define UMSEL10 6 ++#define UMSEL11 7 ++ ++#define UBRR1 _SFR_MEM16(0xCC) ++ ++#define UBRR1L _SFR_MEM8(0xCC) ++#define UBRR_0 0 ++#define UBRR_1 1 ++#define UBRR_2 2 ++#define UBRR_3 3 ++#define UBRR_4 4 ++#define UBRR_5 5 ++#define UBRR_6 6 ++#define UBRR_7 7 ++ ++#define UBRR1H _SFR_MEM8(0xCD) ++#define UBRR_8 0 ++#define UBRR_9 1 ++#define UBRR_10 2 ++#define UBRR_11 3 ++ ++#define UDR1 _SFR_MEM8(0xCE) ++#define UDR1_0 0 ++#define UDR1_1 1 ++#define UDR1_2 2 ++#define UDR1_3 3 ++#define UDR1_4 4 ++#define UDR1_5 5 ++#define UDR1_6 6 ++#define UDR1_7 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ ++#define INT2_vect_num 3 ++#define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ ++#define PCINT0_vect_num 4 ++#define PCINT0_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect_num 5 ++#define PCINT1_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */ ++#define PCINT2_vect_num 6 ++#define PCINT2_vect _VECTOR(6) /* Pin Change Interrupt Request 2 */ ++#define PCINT3_vect_num 7 ++#define PCINT3_vect _VECTOR(7) /* Pin Change Interrupt Request 3 */ ++#define WDT_vect_num 8 ++#define WDT_vect _VECTOR(8) /* Watchdog Time-out Interrupt */ ++#define TIMER2_COMPA_vect_num 9 ++#define TIMER2_COMPA_vect _VECTOR(9) /* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPB_vect_num 10 ++#define TIMER2_COMPB_vect _VECTOR(10) /* Timer/Counter2 Compare Match B */ ++#define TIMER2_OVF_vect_num 11 ++#define TIMER2_OVF_vect _VECTOR(11) /* Timer/Counter2 Overflow */ ++#define TIMER1_CAPT_vect_num 12 ++#define TIMER1_CAPT_vect _VECTOR(12) /* Timer/Counter1 Capture Event */ ++#define TIMER1_COMPA_vect_num 13 ++#define TIMER1_COMPA_vect _VECTOR(13) /* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPB_vect_num 14 ++#define TIMER1_COMPB_vect _VECTOR(14) /* Timer/Counter1 Compare Match B */ ++#define TIMER1_OVF_vect_num 15 ++#define TIMER1_OVF_vect _VECTOR(15) /* Timer/Counter1 Overflow */ ++#define TIMER0_COMPA_vect_num 16 ++#define TIMER0_COMPA_vect _VECTOR(16) /* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPB_vect_num 17 ++#define TIMER0_COMPB_vect _VECTOR(17) /* Timer/Counter0 Compare Match B */ ++#define TIMER0_OVF_vect_num 18 ++#define TIMER0_OVF_vect _VECTOR(18) /* Timer/Counter0 Overflow */ ++#define SPI_STC_vect_num 19 ++#define SPI_STC_vect _VECTOR(19) /* SPI Serial Transfer Complete */ ++#define USART0_RX_vect_num 20 ++#define USART0_RX_vect _VECTOR(20) /* USART0, Rx Complete */ ++#define USART0_UDRE_vect_num 21 ++#define USART0_UDRE_vect _VECTOR(21) /* USART0 Data register Empty */ ++#define USART0_TX_vect_num 22 ++#define USART0_TX_vect _VECTOR(22) /* USART0, Tx Complete */ ++#define ANALOG_COMP_vect_num 23 ++#define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */ ++#define ADC_vect_num 24 ++#define ADC_vect _VECTOR(24) /* ADC Conversion Complete */ ++#define EE_READY_vect_num 25 ++#define EE_READY_vect _VECTOR(25) /* EEPROM Ready */ ++#define TWI_vect_num 26 ++#define TWI_vect _VECTOR(26) /* 2-wire Serial Interface */ ++#define SPM_READY_vect_num 27 ++#define SPM_READY_vect _VECTOR(27) /* Store Program Memory Read */ ++#define USART1_RX_vect_num 28 ++#define USART1_RX_vect _VECTOR(28) /* USART1 RX complete */ ++#define USART1_UDRE_vect_num 29 ++#define USART1_UDRE_vect _VECTOR(29) /* USART1 Data Register Empty */ ++#define USART1_TX_vect_num 30 ++#define USART1_TX_vect _VECTOR(30) /* USART1 TX complete */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (31 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (256) ++#define RAMSTART (0x100) ++#define RAMSIZE (4096) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (0x0) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x7FF) ++#define E2PAGESIZE (8) ++#define FLASHEND (0xFFFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ ++#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ ++#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x0A ++ ++ ++/* Device Pin Definitions */ ++#define MOSI_DDR DDRB ++#define MOSI_PORT PORTB ++#define MOSI_PIN PINB ++#define MOSI_BIT 5 ++ ++#define PCINT13_DDR DDRB ++#define PCINT13_PORT PORTB ++#define PCINT13_PIN PINB ++#define PCINT13_BIT 5 ++ ++#define MISO_DDR DDRB ++#define MISO_PORT PORTB ++#define MISO_PIN PINB ++#define MISO_BIT 6 ++ ++#define PCINT14_DDR DDRB ++#define PCINT14_PORT PORTB ++#define PCINT14_PIN PINB ++#define PCINT14_BIT 6 ++ ++#define SCK_DDR DDRB ++#define SCK_PORT PORTB ++#define SCK_PIN PINB ++#define SCK_BIT 7 ++ ++#define PCINT15_DDR DDRB ++#define PCINT15_PORT PORTB ++#define PCINT15_PIN PINB ++#define PCINT15_BIT 7 ++ ++#define RXD_DDR DDRD ++#define RXD_PORT PORTD ++#define RXD_PIN PIND ++#define RXD_BIT 0 ++ ++#define PCINT24_DDR DDRD ++#define PCINT24_PORT PORTD ++#define PCINT24_PIN PIND ++#define PCINT24_BIT 0 ++ ++#define TXD_DDR DDRD ++#define TXD_PORT PORTD ++#define TXD_PIN PIND ++#define TXD_BIT 1 ++ ++#define PCINT25_DDR DDRD ++#define PCINT25_PORT PORTD ++#define PCINT25_PIN PIND ++#define PCINT25_BIT 1 ++ ++#define INT0_DDR DDRD ++#define INT0_PORT PORTD ++#define INT0_PIN PIND ++#define INT0_BIT 2 ++ ++#define RDX1_DDR DDRD ++#define RDX1_PORT PORTD ++#define RDX1_PIN PIND ++#define RDX1_BIT 2 ++ ++#define PCINT26_DDR DDRD ++#define PCINT26_PORT PORTD ++#define PCINT26_PIN PIND ++#define PCINT26_BIT 2 ++ ++#define INT1_DDR DDRD ++#define INT1_PORT PORTD ++#define INT1_PIN PIND ++#define INT1_BIT 3 ++ ++#define TXD1_DDR DDRD ++#define TXD1_PORT PORTD ++#define TXD1_PIN PIND ++#define TXD1_BIT 3 ++ ++#define PCINT27_DDR DDRD ++#define PCINT27_PORT PORTD ++#define PCINT27_PIN PIND ++#define PCINT27_BIT 3 ++ ++#define OC1B_DDR DDRD ++#define OC1B_PORT PORTD ++#define OC1B_PIN PIND ++#define OC1B_BIT 4 ++ ++#define XCK1_DDR DDRD ++#define XCK1_PORT PORTD ++#define XCK1_PIN PIND ++#define XCK1_BIT 4 ++ ++#define PCINT28_DDR DDRD ++#define PCINT28_PORT PORTD ++#define PCINT28_PIN PIND ++#define PCINT28_BIT 4 ++ ++#define OC1A_DDR DDRD ++#define OC1A_PORT PORTD ++#define OC1A_PIN PIND ++#define OC1A_BIT 5 ++ ++#define PCINT29_DDR DDRD ++#define PCINT29_PORT PORTD ++#define PCINT29_PIN PIND ++#define PCINT29_BIT 5 ++ ++#define ICP_DDR DDRD ++#define ICP_PORT PORTD ++#define ICP_PIN PIND ++#define ICP_BIT 6 ++ ++#define OC2B_DDR DDRD ++#define OC2B_PORT PORTD ++#define OC2B_PIN PIND ++#define OC2B_BIT 6 ++ ++#define PCINT30_DDR DDRD ++#define PCINT30_PORT PORTD ++#define PCINT30_PIN PIND ++#define PCINT30_BIT 6 ++ ++#define OC2A_DDR DDRD ++#define OC2A_PORT PORTD ++#define OC2A_PIN PIND ++#define OC2A_BIT 7 ++ ++#define PCINT31_DDR DDRD ++#define PCINT31_PORT PORTD ++#define PCINT31_PIN PIND ++#define PCINT31_BIT 7 ++ ++#define SCL_DDR DDRC ++#define SCL_PORT PORTC ++#define SCL_PIN PINC ++#define SCL_BIT 0 ++ ++#define PCINT16_DDR DDRC ++#define PCINT16_PORT PORTC ++#define PCINT16_PIN PINC ++#define PCINT16_BIT 0 ++ ++#define SDA_DDR DDRC ++#define SDA_PORT PORTC ++#define SDA_PIN PINC ++#define SDA_BIT 1 ++ ++#define PCINT17_DDR DDRC ++#define PCINT17_PORT PORTC ++#define PCINT17_PIN PINC ++#define PCINT17_BIT 1 ++ ++#define PCINT18_DDR DDRC ++#define PCINT18_PORT PORTC ++#define PCINT18_PIN PINC ++#define PCINT18_BIT 2 ++ ++#define PCINT19_DDR DDRC ++#define PCINT19_PORT PORTC ++#define PCINT19_PIN PINC ++#define PCINT19_BIT 3 ++ ++#define PCINT20_DDR DDRC ++#define PCINT20_PORT PORTC ++#define PCINT20_PIN PINC ++#define PCINT20_BIT 4 ++ ++#define PCINT21_DDR DDRC ++#define PCINT21_PORT PORTC ++#define PCINT21_PIN PINC ++#define PCINT21_BIT 5 ++ ++#define PCINT22_DDR DDRC ++#define PCINT22_PORT PORTC ++#define PCINT22_PIN PINC ++#define PCINT22_BIT 6 ++ ++#define PCINT23_DDR DDRC ++#define PCINT23_PORT PORTC ++#define PCINT23_PIN PINC ++#define PCINT23_BIT 7 ++ ++#define ADC7_DDR DDRA ++#define ADC7_PORT PORTA ++#define ADC7_PIN PINA ++#define ADC7_BIT 7 ++ ++#define PCINT7_DDR DDRA ++#define PCINT7_PORT PORTA ++#define PCINT7_PIN PINA ++#define PCINT7_BIT 7 ++ ++#define ADC6_DDR DDRA ++#define ADC6_PORT PORTA ++#define ADC6_PIN PINA ++#define ADC6_BIT 6 ++ ++#define PCINT6_DDR DDRA ++#define PCINT6_PORT PORTA ++#define PCINT6_PIN PINA ++#define PCINT6_BIT 6 ++ ++#define ADC5_DDR DDRA ++#define ADC5_PORT PORTA ++#define ADC5_PIN PINA ++#define ADC5_BIT 5 ++ ++#define PCINT5_DDR DDRA ++#define PCINT5_PORT PORTA ++#define PCINT5_PIN PINA ++#define PCINT5_BIT 5 ++ ++#define ADC4_DDR DDRA ++#define ADC4_PORT PORTA ++#define ADC4_PIN PINA ++#define ADC4_BIT 4 ++ ++#define PCINT4_DDR DDRA ++#define PCINT4_PORT PORTA ++#define PCINT4_PIN PINA ++#define PCINT4_BIT 4 ++ ++#define ADC3_DDR DDRA ++#define ADC3_PORT PORTA ++#define ADC3_PIN PINA ++#define ADC3_BIT 3 ++ ++#define PCINT3_DDR DDRA ++#define PCINT3_PORT PORTA ++#define PCINT3_PIN PINA ++#define PCINT3_BIT 3 ++ ++#define ADC2_DDR DDRA ++#define ADC2_PORT PORTA ++#define ADC2_PIN PINA ++#define ADC2_BIT 2 ++ ++#define PCINT2_DDR DDRA ++#define PCINT2_PORT PORTA ++#define PCINT2_PIN PINA ++#define PCINT2_BIT 2 ++ ++#define ADC1_DDR DDRA ++#define ADC1_PORT PORTA ++#define ADC1_PIN PINA ++#define ADC1_BIT 1 ++ ++#define PCINT1_DDR DDRA ++#define PCINT1_PORT PORTA ++#define PCINT1_PIN PINA ++#define PCINT1_BIT 1 ++ ++#define ADC0_DDR DDRA ++#define ADC0_PORT PORTA ++#define ADC0_PIN PINA ++#define ADC0_BIT 0 ++ ++#define PCINT0_DDR DDRA ++#define PCINT0_PORT PORTA ++#define PCINT0_PIN PINA ++#define PCINT0_BIT 0 ++ ++#define XCK_DDR DDRB ++#define XCK_PORT PORTB ++#define XCK_PIN PINB ++#define XCK_BIT 0 ++ ++#define T0_DDR DDRB ++#define T0_PORT PORTB ++#define T0_PIN PINB ++#define T0_BIT 0 ++ ++#define PCINT8_DDR DDRB ++#define PCINT8_PORT PORTB ++#define PCINT8_PIN PINB ++#define PCINT8_BIT 0 ++ ++#define T1_DDR DDRB ++#define T1_PORT PORTB ++#define T1_PIN PINB ++#define T1_BIT 1 ++ ++#define CLKO_DDR DDRB ++#define CLKO_PORT PORTB ++#define CLKO_PIN PINB ++#define CLKO_BIT 1 ++ ++#define PCINT9_DDR DDRB ++#define PCINT9_PORT PORTB ++#define PCINT9_PIN PINB ++#define PCINT9_BIT 1 ++ ++#define AIN0_DDR DDRB ++#define AIN0_PORT PORTB ++#define AIN0_PIN PINB ++#define AIN0_BIT 2 ++ ++#define INT2_DDR DDRB ++#define INT2_PORT PORTB ++#define INT2_PIN PINB ++#define INT2_BIT 2 ++ ++#define PCINT10_DDR DDRB ++#define PCINT10_PORT PORTB ++#define PCINT10_PIN PINB ++#define PCINT10_BIT 2 ++ ++#define AIN1_DDR DDRB ++#define AIN1_PORT PORTB ++#define AIN1_PIN PINB ++#define AIN1_BIT 3 ++ ++#define OC0A_DDR DDRB ++#define OC0A_PORT PORTB ++#define OC0A_PIN PINB ++#define OC0A_BIT 3 ++ ++#define PCINT11_DDR DDRB ++#define PCINT11_PORT PORTB ++#define PCINT11_PIN PINB ++#define PCINT11_BIT 3 ++ ++#define SS_DDR DDRB ++#define SS_PORT PORTB ++#define SS_PIN PINB ++#define SS_BIT 4 ++ ++#define OC0B_DDR DDRB ++#define OC0B_PORT PORTB ++#define OC0B_PIN PINB ++#define OC0B_BIT 4 ++ ++#define PCINT12_DDR DDRB ++#define PCINT12_PORT PORTB ++#define PCINT12_PIN PINB ++#define PCINT12_BIT 4 ++ ++#endif /* _AVR_ATmega644PA_H_ */ ++ diff --git a/include/avr/iom644rfr2.h b/include/avr/iom644rfr2.h new file mode 100644 -index 0000000..86ec3cb +index 0000000..bbb25b9 --- /dev/null +++ b/include/avr/iom644rfr2.h -@@ -0,0 +1,2558 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATMEGA644RFR2_H_INCLUDED -+#define _AVR_ATMEGA644RFR2_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iom644rfr2.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINA _SFR_IO8(0x00) -+#define PINA7 7 -+#define PINA6 6 -+#define PINA5 5 -+#define PINA4 4 -+#define PINA3 3 -+#define PINA2 2 -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x01) -+#define DDRA7 7 -+#define DDRA6 6 -+#define DDRA5 5 -+#define DDRA4 4 -+#define DDRA3 3 -+#define DDRA2 2 -+#define DDRA1 1 -+#define DDRA0 0 -+ -+#define PORTA _SFR_IO8(0x02) -+#define PORTA7 7 -+#define PORTA6 6 -+#define PORTA5 5 -+#define PORTA4 4 -+#define PORTA3 3 -+#define PORTA2 2 -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x06) -+#define PINC7 7 -+#define PINC6 6 -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x07) -+#define DDRC7 7 -+#define DDRC6 6 -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x08) -+#define PORTC7 7 -+#define PORTC6 6 -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PIND _SFR_IO8(0x09) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0A) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x0B) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+#define PINE _SFR_IO8(0x0C) -+#define PINE7 7 -+#define PINE6 6 -+#define PINE5 5 -+#define PINE4 4 -+#define PINE3 3 -+#define PINE2 2 -+#define PINE1 1 -+#define PINE0 0 -+ -+#define DDRE _SFR_IO8(0x0D) -+#define DDRE7 7 -+#define DDRE6 6 -+#define DDRE5 5 -+#define DDRE4 4 -+#define DDRE3 3 -+#define DDRE2 2 -+#define DDRE1 1 -+#define DDRE0 0 -+ -+#define PORTE _SFR_IO8(0x0E) -+#define PORTE7 7 -+#define PORTE6 6 -+#define PORTE5 5 -+#define PORTE4 4 -+#define PORTE3 3 -+#define PORTE2 2 -+#define PORTE1 1 -+#define PORTE0 0 -+ -+#define PINF _SFR_IO8(0x0F) -+#define PINF7 7 -+#define PINF6 6 -+#define PINF5 5 -+#define PINF4 4 -+#define PINF3 3 -+#define PINF2 2 -+#define PINF1 1 -+#define PINF0 0 -+ -+#define DDRF _SFR_IO8(0x10) -+#define DDRF7 7 -+#define DDRF6 6 -+#define DDRF5 5 -+#define DDRF4 4 -+#define DDRF3 3 -+#define DDRF2 2 -+#define DDRF1 1 -+#define DDRF0 0 -+ -+#define PORTF _SFR_IO8(0x11) -+#define PORTF7 7 -+#define PORTF6 6 -+#define PORTF5 5 -+#define PORTF4 4 -+#define PORTF3 3 -+#define PORTF2 2 -+#define PORTF1 1 -+#define PORTF0 0 -+ -+#define PING _SFR_IO8(0x12) -+#define PING7 7 -+#define PING6 6 -+#define PING5 5 -+#define PING4 4 -+#define PING3 3 -+#define PING2 2 -+#define PING1 1 -+#define PING0 0 -+ -+#define DDRG _SFR_IO8(0x13) -+#define DDRG7 7 -+#define DDRG6 6 -+#define DDRG5 5 -+#define DDRG4 4 -+#define DDRG3 3 -+#define DDRG2 2 -+#define DDRG1 1 -+#define DDRG0 0 -+ -+#define PORTG _SFR_IO8(0x14) -+#define PORTG7 7 -+#define PORTG6 6 -+#define PORTG5 5 -+#define PORTG4 4 -+#define PORTG3 3 -+#define PORTG2 2 -+#define PORTG1 1 -+#define PORTG0 0 -+ -+#define TIFR0 _SFR_IO8(0x15) -+#define TOV0 0 -+#define OCF0A 1 -+#define OCF0B 2 -+#define Res0 3 -+#define Res1 4 -+#define Res2 5 -+#define Res3 6 -+#define Res4 7 -+ -+#define TIFR1 _SFR_IO8(0x16) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define OCF1C 3 -+#define ICF1 5 -+ -+#define TIFR2 _SFR_IO8(0x17) -+#define TOV2 0 -+#define OCF2A 1 -+#define OCF2B 2 -+ -+#define TIFR3 _SFR_IO8(0x18) -+#define TOV3 0 -+#define OCF3A 1 -+#define OCF3B 2 -+#define OCF3C 3 -+#define ICF3 5 -+ -+#define TIFR4 _SFR_IO8(0x19) -+#define TOV4 0 -+#define OCF4A 1 -+#define OCF4B 2 -+#define OCF4C 3 -+#define ICF4 5 -+ -+#define TIFR5 _SFR_IO8(0x1A) -+#define TOV5 0 -+#define OCF5A 1 -+#define OCF5B 2 -+#define OCF5C 3 -+#define ICF5 5 -+ -+#define PCIFR _SFR_IO8(0x1B) -+#define PCIF0 0 -+#define PCIF1 1 -+#define PCIF2 2 -+ -+#define EIFR _SFR_IO8(0x1C) -+#define INTF0 0 -+#define INTF1 1 -+#define INTF2 2 -+#define INTF3 3 -+#define INTF4 4 -+#define INTF5 5 -+#define INTF6 6 -+#define INTF7 7 -+ -+#define EIMSK _SFR_IO8(0x1D) -+#define INT0 0 -+#define INT1 1 -+#define INT2 2 -+#define INT3 3 -+#define INT4 4 -+#define INT5 5 -+#define INT6 6 -+#define INT7 7 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+#define GPIOR00 0 -+#define GPIOR01 1 -+#define GPIOR02 2 -+#define GPIOR03 3 -+#define GPIOR04 4 -+#define GPIOR05 5 -+#define GPIOR06 6 -+#define GPIOR07 7 -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEPE 1 -+#define EEMPE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSRSYNC 0 -+#define PSRASY 1 -+#define TSM 7 -+ -+#define TCCR0A _SFR_IO8(0x24) -+#define WGM00 0 -+#define WGM01 1 -+#define COM0B0 4 -+#define COM0B1 5 -+#define COM0A0 6 -+#define COM0A1 7 -+ -+#define TCCR0B _SFR_IO8(0x25) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define WGM02 3 -+#define FOC0B 6 -+#define FOC0A 7 -+ -+#define TCNT0 _SFR_IO8(0x26) -+ -+#define OCR0A _SFR_IO8(0x27) -+ -+#define OCR0B _SFR_IO8(0x28) -+ -+/* Reserved [0x29] */ -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+#define GPIOR10 0 -+#define GPIOR11 1 -+#define GPIOR12 2 -+#define GPIOR13 3 -+#define GPIOR14 4 -+#define GPIOR15 5 -+#define GPIOR16 6 -+#define GPIOR17 7 -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+#define GPIOR20 0 -+#define GPIOR21 1 -+#define GPIOR22 2 -+#define GPIOR23 3 -+#define GPIOR24 4 -+#define GPIOR25 5 -+#define GPIOR26 6 -+#define GPIOR27 7 -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+/* Reserved [0x2F] */ -+ -+#define ACSR _SFR_IO8(0x30) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACBG 6 -+#define ACD 7 -+ -+#define OCDR _SFR_IO8(0x31) -+#define OCDR0 0 -+#define OCDR1 1 -+#define OCDR2 2 -+#define OCDR3 3 -+#define OCDR4 4 -+#define OCDR5 5 -+#define OCDR6 6 -+#define OCDR7 7 -+ -+/* Reserved [0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define JTRF 4 -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define JTD 7 -+#define IVCE 0 -+#define IVSEL 1 -+#define PUD 4 -+ -+/* Reserved [0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define SIGRD 5 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+/* Reserved [0x38..0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCSR _SFR_MEM8(0x60) -+#define WDE 3 -+#define WDCE 4 -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDP3 5 -+#define WDIE 6 -+#define WDIF 7 -+ -+#define CLKPR _SFR_MEM8(0x61) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+#define CLKPCE 7 -+ -+/* Reserved [0x62] */ -+ -+#define PRR2 _SFR_MEM8(0x63) -+#define PRRAM0 0 -+#define PRRAM1 1 -+#define PRRAM2 2 -+#define PRRAM3 3 -+ -+#define PRR0 _SFR_MEM8(0x64) -+#define PRADC 0 -+#define PRUSART0 1 -+#define PRSPI 2 -+#define PRTIM1 3 -+#define PRPGA 4 -+#define PRTIM0 5 -+#define PRTIM2 6 -+#define PRTWI 7 -+ -+#define PRR1 _SFR_MEM8(0x65) -+#define PRUSART1 0 -+#define PRTIM3 3 -+#define PRTIM4 4 -+#define PRTIM5 5 -+#define PRTRX24 6 -+#define Res 7 -+ -+#define OSCCAL _SFR_MEM8(0x66) -+#define CAL0 0 -+#define CAL1 1 -+#define CAL2 2 -+#define CAL3 3 -+#define CAL4 4 -+#define CAL5 5 -+#define CAL6 6 -+#define CAL7 7 -+ -+#define BGCR _SFR_MEM8(0x67) -+#define BGCAL0 0 -+#define BGCAL1 1 -+#define BGCAL2 2 -+#define BGCAL_FINE0 3 -+#define BGCAL_FINE1 4 -+#define BGCAL_FINE2 5 -+#define BGCAL_FINE3 6 -+ -+#define PCICR _SFR_MEM8(0x68) -+#define PCIE0 0 -+#define PCIE1 1 -+#define PCIE2 2 -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+#define ISC20 4 -+#define ISC21 5 -+#define ISC30 6 -+#define ISC31 7 -+ -+#define EICRB _SFR_MEM8(0x6A) -+#define ISC40 0 -+#define ISC41 1 -+#define ISC50 2 -+#define ISC51 3 -+#define ISC60 4 -+#define ISC61 5 -+#define ISC70 6 -+#define ISC71 7 -+ -+#define PCMSK0 _SFR_MEM8(0x6B) -+ -+#define PCMSK1 _SFR_MEM8(0x6C) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+#define PCINT14 6 -+#define PCINT15 7 -+ -+#define PCMSK2 _SFR_MEM8(0x6D) -+#define PCINT16 0 -+#define PCINT17 1 -+#define PCINT18 2 -+#define PCINT19 3 -+#define PCINT20 4 -+#define PCINT21 5 -+#define PCINT22 6 -+#define PCINT23 7 -+ -+#define TIMSK0 _SFR_MEM8(0x6E) -+#define TOIE0 0 -+#define OCIE0A 1 -+#define OCIE0B 2 -+ -+#define TIMSK1 _SFR_MEM8(0x6F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define OCIE1C 3 -+#define ICIE1 5 -+ -+#define TIMSK2 _SFR_MEM8(0x70) -+#define TOIE2 0 -+#define OCIE2A 1 -+#define OCIE2B 2 -+ -+#define TIMSK3 _SFR_MEM8(0x71) -+#define TOIE3 0 -+#define OCIE3A 1 -+#define OCIE3B 2 -+#define OCIE3C 3 -+#define ICIE3 5 -+ -+#define TIMSK4 _SFR_MEM8(0x72) -+#define TOIE4 0 -+#define OCIE4A 1 -+#define OCIE4B 2 -+#define OCIE4C 3 -+#define ICIE4 5 -+ -+#define TIMSK5 _SFR_MEM8(0x73) -+#define TOIE5 0 -+#define OCIE5A 1 -+#define OCIE5B 2 -+#define OCIE5C 3 -+#define ICIE5 5 -+ -+/* Reserved [0x74] */ -+ -+#define NEMCR _SFR_MEM8(0x75) -+#define AEAM0 4 -+#define AEAM1 5 -+#define ENEAM 6 -+ -+/* Reserved [0x76] */ -+ -+#define ADCSRC _SFR_MEM8(0x77) -+#define ADSUT0 0 -+#define ADSUT1 1 -+#define ADSUT2 2 -+#define ADSUT3 3 -+#define ADSUT4 4 -+#define ADTHT0 6 -+#define ADTHT1 7 -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_MEM16(0x78) -+#endif -+#define ADCW _SFR_MEM16(0x78) -+ -+#define ADCL _SFR_MEM8(0x78) -+#define ADCH _SFR_MEM8(0x79) -+ -+#define ADCSRA _SFR_MEM8(0x7A) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADCSRB _SFR_MEM8(0x7B) -+#define ACME 6 -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+#define MUX5 3 -+#define ACCH 4 -+#define REFOK 5 -+#define AVDDOK 7 -+ -+#define ADMUX _SFR_MEM8(0x7C) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define MUX4 4 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+#define DIDR2 _SFR_MEM8(0x7D) -+#define ADC8D 0 -+#define ADC9D 1 -+#define ADC10D 2 -+#define ADC11D 3 -+#define ADC12D 4 -+#define ADC13D 5 -+#define ADC14D 6 -+#define ADC15D 7 -+ -+#define DIDR0 _SFR_MEM8(0x7E) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+#define ADC6D 6 -+#define ADC7D 7 -+ -+#define DIDR1 _SFR_MEM8(0x7F) -+#define AIN0D 0 -+#define AIN1D 1 -+ -+#define TCCR1A _SFR_MEM8(0x80) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1C0 2 -+#define COM1C1 3 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR1B _SFR_MEM8(0x81) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1C _SFR_MEM8(0x82) -+#define FOC1C 5 -+#define FOC1B 6 -+#define FOC1A 7 -+ -+/* Reserved [0x83] */ -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x84) -+ -+#define TCNT1L _SFR_MEM8(0x84) -+#define TCNT1H _SFR_MEM8(0x85) -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x86) -+ -+#define ICR1L _SFR_MEM8(0x86) -+#define ICR1H _SFR_MEM8(0x87) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_MEM16(0x88) -+ -+#define OCR1AL _SFR_MEM8(0x88) -+#define OCR1AH _SFR_MEM8(0x89) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_MEM16(0x8A) -+ -+#define OCR1BL _SFR_MEM8(0x8A) -+#define OCR1BH _SFR_MEM8(0x8B) -+ -+/* Combine OCR1CL and OCR1CH */ -+#define OCR1C _SFR_MEM16(0x8C) -+ -+#define OCR1CL _SFR_MEM8(0x8C) -+#define OCR1CH _SFR_MEM8(0x8D) -+ -+/* Reserved [0x8E..0x8F] */ -+ -+#define TCCR3A _SFR_MEM8(0x90) -+#define WGM30 0 -+#define WGM31 1 -+#define COM3C0 2 -+#define COM3C1 3 -+#define COM3B0 4 -+#define COM3B1 5 -+#define COM3A0 6 -+#define COM3A1 7 -+ -+#define TCCR3B _SFR_MEM8(0x91) -+#define CS30 0 -+#define CS31 1 -+#define CS32 2 -+#define WGM32 3 -+#define WGM33 4 -+#define ICES3 6 -+#define ICNC3 7 -+ -+#define TCCR3C _SFR_MEM8(0x92) -+#define FOC3C 5 -+#define FOC3B 6 -+#define FOC3A 7 -+ -+/* Reserved [0x93] */ -+ -+/* Combine TCNT3L and TCNT3H */ -+#define TCNT3 _SFR_MEM16(0x94) -+ -+#define TCNT3L _SFR_MEM8(0x94) -+#define TCNT3H _SFR_MEM8(0x95) -+ -+/* Combine ICR3L and ICR3H */ -+#define ICR3 _SFR_MEM16(0x96) -+ -+#define ICR3L _SFR_MEM8(0x96) -+#define ICR3H _SFR_MEM8(0x97) -+ -+/* Combine OCR3AL and OCR3AH */ -+#define OCR3A _SFR_MEM16(0x98) -+ -+#define OCR3AL _SFR_MEM8(0x98) -+#define OCR3AH _SFR_MEM8(0x99) -+ -+/* Combine OCR3BL and OCR3BH */ -+#define OCR3B _SFR_MEM16(0x9A) -+ -+#define OCR3BL _SFR_MEM8(0x9A) -+#define OCR3BH _SFR_MEM8(0x9B) -+ -+/* Combine OCR3CL and OCR3CH */ -+#define OCR3C _SFR_MEM16(0x9C) -+ -+#define OCR3CL _SFR_MEM8(0x9C) -+#define OCR3CH _SFR_MEM8(0x9D) -+ -+/* Reserved [0x9E..0x9F] */ -+ -+#define TCCR4A _SFR_MEM8(0xA0) -+#define WGM40 0 -+#define WGM41 1 -+#define COM4C0 2 -+#define COM4C1 3 -+#define COM4B0 4 -+#define COM4B1 5 -+#define COM4A0 6 -+#define COM4A1 7 -+ -+#define TCCR4B _SFR_MEM8(0xA1) -+#define CS40 0 -+#define CS41 1 -+#define CS42 2 -+#define WGM42 3 -+#define WGM43 4 -+#define ICES4 6 -+#define ICNC4 7 -+ -+#define TCCR4C _SFR_MEM8(0xA2) -+#define FOC4C 5 -+#define FOC4B 6 -+#define FOC4A 7 -+ -+/* Reserved [0xA3] */ -+ -+/* Combine TCNT4L and TCNT4H */ -+#define TCNT4 _SFR_MEM16(0xA4) -+ -+#define TCNT4L _SFR_MEM8(0xA4) -+#define TCNT4H _SFR_MEM8(0xA5) -+ -+/* Combine ICR4L and ICR4H */ -+#define ICR4 _SFR_MEM16(0xA6) -+ -+#define ICR4L _SFR_MEM8(0xA6) -+#define ICR4H _SFR_MEM8(0xA7) -+ -+/* Combine OCR4AL and OCR4AH */ -+#define OCR4A _SFR_MEM16(0xA8) -+ -+#define OCR4AL _SFR_MEM8(0xA8) -+#define OCR4AH _SFR_MEM8(0xA9) -+ -+/* Combine OCR4BL and OCR4BH */ -+#define OCR4B _SFR_MEM16(0xAA) -+ -+#define OCR4BL _SFR_MEM8(0xAA) -+#define OCR4BH _SFR_MEM8(0xAB) -+ -+/* Combine OCR4CL and OCR4CH */ -+#define OCR4C _SFR_MEM16(0xAC) -+ -+#define OCR4CL _SFR_MEM8(0xAC) -+#define OCR4CH _SFR_MEM8(0xAD) -+ -+/* Reserved [0xAE..0xAF] */ -+ -+#define TCCR2A _SFR_MEM8(0xB0) -+#define WGM20 0 -+#define WGM21 1 -+#define COM2B0 4 -+#define COM2B1 5 -+#define COM2A0 6 -+#define COM2A1 7 -+ -+#define TCCR2B _SFR_MEM8(0xB1) -+#define CS20 0 -+#define CS21 1 -+#define CS22 2 -+#define WGM22 3 -+#define FOC2B 6 -+#define FOC2A 7 -+ -+#define TCNT2 _SFR_MEM8(0xB2) -+ -+#define OCR2A _SFR_MEM8(0xB3) -+ -+#define OCR2B _SFR_MEM8(0xB4) -+ -+/* Reserved [0xB5] */ -+ -+#define ASSR _SFR_MEM8(0xB6) -+#define TCR2BUB 0 -+#define TCR2AUB 1 -+#define OCR2BUB 2 -+#define OCR2AUB 3 -+#define TCN2UB 4 -+#define AS2 5 -+#define EXCLK 6 -+#define EXCLKAMR 7 -+ -+/* Reserved [0xB7] */ -+ -+#define TWBR _SFR_MEM8(0xB8) -+ -+#define TWSR _SFR_MEM8(0xB9) -+#define TWPS0 0 -+#define TWPS1 1 -+#define TWS3 3 -+#define TWS4 4 -+#define TWS5 5 -+#define TWS6 6 -+#define TWS7 7 -+ -+#define TWAR _SFR_MEM8(0xBA) -+#define TWGCE 0 -+#define TWA0 1 -+#define TWA1 2 -+#define TWA2 3 -+#define TWA3 4 -+#define TWA4 5 -+#define TWA5 6 -+#define TWA6 7 -+ -+#define TWDR _SFR_MEM8(0xBB) -+ -+#define TWCR _SFR_MEM8(0xBC) -+#define TWIE 0 -+#define TWEN 2 -+#define TWWC 3 -+#define TWSTO 4 -+#define TWSTA 5 -+#define TWEA 6 -+#define TWINT 7 -+ -+#define TWAMR _SFR_MEM8(0xBD) -+#define TWAM0 1 -+#define TWAM1 2 -+#define TWAM2 3 -+#define TWAM3 4 -+#define TWAM4 5 -+#define TWAM5 6 -+#define TWAM6 7 -+ -+#define IRQ_MASK1 _SFR_MEM8(0xBE) -+#define TX_START_EN 0 -+#define MAF_0_AMI_EN 1 -+#define MAF_1_AMI_EN 2 -+#define MAF_2_AMI_EN 3 -+#define MAF_3_AMI_EN 4 -+ -+#define IRQ_STATUS1 _SFR_MEM8(0xBF) -+#define TX_START 0 -+#define MAF_0_AMI 1 -+#define MAF_1_AMI 2 -+#define MAF_2_AMI 3 -+#define MAF_3_AMI 4 -+ -+#define UCSR0A _SFR_MEM8(0xC0) -+#define MPCM0 0 -+#define U2X0 1 -+#define UPE0 2 -+#define DOR0 3 -+#define FE0 4 -+#define UDRE0 5 -+#define TXC0 6 -+#define RXC0 7 -+ -+#define UCSR0B _SFR_MEM8(0xC1) -+#define TXB80 0 -+#define RXB80 1 -+#define UCSZ02 2 -+#define TXEN0 3 -+#define RXEN0 4 -+#define UDRIE0 5 -+#define TXCIE0 6 -+#define RXCIE0 7 -+ -+#define UCSR0C _SFR_MEM8(0xC2) -+#define UCPOL0 0 -+#define UCSZ00 1 -+#define UCSZ01 2 -+#define USBS0 3 -+#define UPM00 4 -+#define UPM01 5 -+#define UMSEL00 6 -+#define UMSEL01 7 -+#define UCPHA0 1 -+#define UDORD0 2 -+ -+/* Reserved [0xC3] */ -+ -+/* Combine UBRR0L and UBRR0H */ -+#define UBRR0 _SFR_MEM16(0xC4) -+ -+#define UBRR0L _SFR_MEM8(0xC4) -+#define UBRR0H _SFR_MEM8(0xC5) -+ -+#define UDR0 _SFR_MEM8(0xC6) -+ -+/* Reserved [0xC7] */ -+ -+#define UCSR1A _SFR_MEM8(0xC8) -+#define MPCM1 0 -+#define U2X1 1 -+#define UPE1 2 -+#define DOR1 3 -+#define FE1 4 -+#define UDRE1 5 -+#define TXC1 6 -+#define RXC1 7 -+ -+#define UCSR1B _SFR_MEM8(0xC9) -+#define TXB81 0 -+#define RXB81 1 -+#define UCSZ12 2 -+#define TXEN1 3 -+#define RXEN1 4 -+#define UDRIE1 5 -+#define TXCIE1 6 -+#define RXCIE1 7 -+ -+#define UCSR1C _SFR_MEM8(0xCA) -+#define UCPOL1 0 -+#define UCSZ10 1 -+#define UCSZ11 2 -+#define USBS1 3 -+#define UPM10 4 -+#define UPM11 5 -+#define UMSEL10 6 -+#define UMSEL11 7 -+#define UCPHA1 1 -+#define UDORD1 2 -+ -+/* Reserved [0xCB] */ -+ -+/* Combine UBRR1L and UBRR1H */ -+#define UBRR1 _SFR_MEM16(0xCC) -+ -+#define UBRR1L _SFR_MEM8(0xCC) -+#define UBRR1H _SFR_MEM8(0xCD) -+ -+#define UDR1 _SFR_MEM8(0xCE) -+ -+/* Reserved [0xCF..0xD6] */ -+ -+#define SCRSTRLL _SFR_MEM8(0xD7) -+#define SCRSTRLL0 0 -+#define SCRSTRLL1 1 -+#define SCRSTRLL2 2 -+#define SCRSTRLL3 3 -+#define SCRSTRLL4 4 -+#define SCRSTRLL5 5 -+#define SCRSTRLL6 6 -+#define SCRSTRLL7 7 -+ -+#define SCRSTRLH _SFR_MEM8(0xD8) -+#define SCRSTRLH0 0 -+#define SCRSTRLH1 1 -+#define SCRSTRLH2 2 -+#define SCRSTRLH3 3 -+#define SCRSTRLH4 4 -+#define SCRSTRLH5 5 -+#define SCRSTRLH6 6 -+#define SCRSTRLH7 7 -+ -+#define SCRSTRHL _SFR_MEM8(0xD9) -+#define SCRSTRHL0 0 -+#define SCRSTRHL1 1 -+#define SCRSTRHL2 2 -+#define SCRSTRHL3 3 -+#define SCRSTRHL4 4 -+#define SCRSTRHL5 5 -+#define SCRSTRHL6 6 -+#define SCRSTRHL7 7 -+ -+#define SCRSTRHH _SFR_MEM8(0xDA) -+#define SCRSTRHH0 0 -+#define SCRSTRHH1 1 -+#define SCRSTRHH2 2 -+#define SCRSTRHH3 3 -+#define SCRSTRHH4 4 -+#define SCRSTRHH5 5 -+#define SCRSTRHH6 6 -+#define SCRSTRHH7 7 -+ -+#define SCCSR _SFR_MEM8(0xDB) -+#define SCCS10 0 -+#define SCCS11 1 -+#define SCCS20 2 -+#define SCCS21 3 -+#define SCCS30 4 -+#define SCCS31 5 -+ -+#define SCCR0 _SFR_MEM8(0xDC) -+#define SCCMP1 0 -+#define SCCMP2 1 -+#define SCCMP3 2 -+#define SCTSE 3 -+#define SCCKSEL 4 -+#define SCEN 5 -+#define SCMBTS 6 -+#define SCRES 7 -+ -+#define SCCR1 _SFR_MEM8(0xDD) -+#define SCENBO 0 -+#define SCEECLK 1 -+#define SCCKDIV0 2 -+#define SCCKDIV1 3 -+#define SCCKDIV2 4 -+#define SCBTSM 5 -+#define Res5 6 -+#define Res6 7 -+ -+#define SCSR _SFR_MEM8(0xDE) -+#define SCBSY 0 -+ -+#define SCIRQM _SFR_MEM8(0xDF) -+#define IRQMCP1 0 -+#define IRQMCP2 1 -+#define IRQMCP3 2 -+#define IRQMOF 3 -+#define IRQMBO 4 -+ -+#define SCIRQS _SFR_MEM8(0xE0) -+#define IRQSCP1 0 -+#define IRQSCP2 1 -+#define IRQSCP3 2 -+#define IRQSOF 3 -+#define IRQSBO 4 -+ -+#define SCCNTLL _SFR_MEM8(0xE1) -+#define SCCNTLL0 0 -+#define SCCNTLL1 1 -+#define SCCNTLL2 2 -+#define SCCNTLL3 3 -+#define SCCNTLL4 4 -+#define SCCNTLL5 5 -+#define SCCNTLL6 6 -+#define SCCNTLL7 7 -+ -+#define SCCNTLH _SFR_MEM8(0xE2) -+#define SCCNTLH0 0 -+#define SCCNTLH1 1 -+#define SCCNTLH2 2 -+#define SCCNTLH3 3 -+#define SCCNTLH4 4 -+#define SCCNTLH5 5 -+#define SCCNTLH6 6 -+#define SCCNTLH7 7 -+ -+#define SCCNTHL _SFR_MEM8(0xE3) -+#define SCCNTHL0 0 -+#define SCCNTHL1 1 -+#define SCCNTHL2 2 -+#define SCCNTHL3 3 -+#define SCCNTHL4 4 -+#define SCCNTHL5 5 -+#define SCCNTHL6 6 -+#define SCCNTHL7 7 -+ -+#define SCCNTHH _SFR_MEM8(0xE4) -+#define SCCNTHH0 0 -+#define SCCNTHH1 1 -+#define SCCNTHH2 2 -+#define SCCNTHH3 3 -+#define SCCNTHH4 4 -+#define SCCNTHH5 5 -+#define SCCNTHH6 6 -+#define SCCNTHH7 7 -+ -+#define SCBTSRLL _SFR_MEM8(0xE5) -+#define SCBTSRLL0 0 -+#define SCBTSRLL1 1 -+#define SCBTSRLL2 2 -+#define SCBTSRLL3 3 -+#define SCBTSRLL4 4 -+#define SCBTSRLL5 5 -+#define SCBTSRLL6 6 -+#define SCBTSRLL7 7 -+ -+#define SCBTSRLH _SFR_MEM8(0xE6) -+#define SCBTSRLH0 0 -+#define SCBTSRLH1 1 -+#define SCBTSRLH2 2 -+#define SCBTSRLH3 3 -+#define SCBTSRLH4 4 -+#define SCBTSRLH5 5 -+#define SCBTSRLH6 6 -+#define SCBTSRLH7 7 -+ -+#define SCBTSRHL _SFR_MEM8(0xE7) -+#define SCBTSRHL0 0 -+#define SCBTSRHL1 1 -+#define SCBTSRHL2 2 -+#define SCBTSRHL3 3 -+#define SCBTSRHL4 4 -+#define SCBTSRHL5 5 -+#define SCBTSRHL6 6 -+#define SCBTSRHL7 7 -+ -+#define SCBTSRHH _SFR_MEM8(0xE8) -+#define SCBTSRHH0 0 -+#define SCBTSRHH1 1 -+#define SCBTSRHH2 2 -+#define SCBTSRHH3 3 -+#define SCBTSRHH4 4 -+#define SCBTSRHH5 5 -+#define SCBTSRHH6 6 -+#define SCBTSRHH7 7 -+ -+#define SCTSRLL _SFR_MEM8(0xE9) -+#define SCTSRLL0 0 -+#define SCTSRLL1 1 -+#define SCTSRLL2 2 -+#define SCTSRLL3 3 -+#define SCTSRLL4 4 -+#define SCTSRLL5 5 -+#define SCTSRLL6 6 -+#define SCTSRLL7 7 -+ -+#define SCTSRLH _SFR_MEM8(0xEA) -+#define SCTSRLH0 0 -+#define SCTSRLH1 1 -+#define SCTSRLH2 2 -+#define SCTSRLH3 3 -+#define SCTSRLH4 4 -+#define SCTSRLH5 5 -+#define SCTSRLH6 6 -+#define SCTSRLH7 7 -+ -+#define SCTSRHL _SFR_MEM8(0xEB) -+#define SCTSRHL0 0 -+#define SCTSRHL1 1 -+#define SCTSRHL2 2 -+#define SCTSRHL3 3 -+#define SCTSRHL4 4 -+#define SCTSRHL5 5 -+#define SCTSRHL6 6 -+#define SCTSRHL7 7 -+ -+#define SCTSRHH _SFR_MEM8(0xEC) -+#define SCTSRHH0 0 -+#define SCTSRHH1 1 -+#define SCTSRHH2 2 -+#define SCTSRHH3 3 -+#define SCTSRHH4 4 -+#define SCTSRHH5 5 -+#define SCTSRHH6 6 -+#define SCTSRHH7 7 -+ -+#define SCOCR3LL _SFR_MEM8(0xED) -+#define SCOCR3LL0 0 -+#define SCOCR3LL1 1 -+#define SCOCR3LL2 2 -+#define SCOCR3LL3 3 -+#define SCOCR3LL4 4 -+#define SCOCR3LL5 5 -+#define SCOCR3LL6 6 -+#define SCOCR3LL7 7 -+ -+#define SCOCR3LH _SFR_MEM8(0xEE) -+#define SCOCR3LH0 0 -+#define SCOCR3LH1 1 -+#define SCOCR3LH2 2 -+#define SCOCR3LH3 3 -+#define SCOCR3LH4 4 -+#define SCOCR3LH5 5 -+#define SCOCR3LH6 6 -+#define SCOCR3LH7 7 -+ -+#define SCOCR3HL _SFR_MEM8(0xEF) -+#define SCOCR3HL0 0 -+#define SCOCR3HL1 1 -+#define SCOCR3HL2 2 -+#define SCOCR3HL3 3 -+#define SCOCR3HL4 4 -+#define SCOCR3HL5 5 -+#define SCOCR3HL6 6 -+#define SCOCR3HL7 7 -+ -+#define SCOCR3HH _SFR_MEM8(0xF0) -+#define SCOCR3HH0 0 -+#define SCOCR3HH1 1 -+#define SCOCR3HH2 2 -+#define SCOCR3HH3 3 -+#define SCOCR3HH4 4 -+#define SCOCR3HH5 5 -+#define SCOCR3HH6 6 -+#define SCOCR3HH7 7 -+ -+#define SCOCR2LL _SFR_MEM8(0xF1) -+#define SCOCR2LL0 0 -+#define SCOCR2LL1 1 -+#define SCOCR2LL2 2 -+#define SCOCR2LL3 3 -+#define SCOCR2LL4 4 -+#define SCOCR2LL5 5 -+#define SCOCR2LL6 6 -+#define SCOCR2LL7 7 -+ -+#define SCOCR2LH _SFR_MEM8(0xF2) -+#define SCOCR2LH0 0 -+#define SCOCR2LH1 1 -+#define SCOCR2LH2 2 -+#define SCOCR2LH3 3 -+#define SCOCR2LH4 4 -+#define SCOCR2LH5 5 -+#define SCOCR2LH6 6 -+#define SCOCR2LH7 7 -+ -+#define SCOCR2HL _SFR_MEM8(0xF3) -+#define SCOCR2HL0 0 -+#define SCOCR2HL1 1 -+#define SCOCR2HL2 2 -+#define SCOCR2HL3 3 -+#define SCOCR2HL4 4 -+#define SCOCR2HL5 5 -+#define SCOCR2HL6 6 -+#define SCOCR2HL7 7 -+ -+#define SCOCR2HH _SFR_MEM8(0xF4) -+#define SCOCR2HH0 0 -+#define SCOCR2HH1 1 -+#define SCOCR2HH2 2 -+#define SCOCR2HH3 3 -+#define SCOCR2HH4 4 -+#define SCOCR2HH5 5 -+#define SCOCR2HH6 6 -+#define SCOCR2HH7 7 -+ -+#define SCOCR1LL _SFR_MEM8(0xF5) -+#define SCOCR1LL0 0 -+#define SCOCR1LL1 1 -+#define SCOCR1LL2 2 -+#define SCOCR1LL3 3 -+#define SCOCR1LL4 4 -+#define SCOCR1LL5 5 -+#define SCOCR1LL6 6 -+#define SCOCR1LL7 7 -+ -+#define SCOCR1LH _SFR_MEM8(0xF6) -+#define SCOCR1LH0 0 -+#define SCOCR1LH1 1 -+#define SCOCR1LH2 2 -+#define SCOCR1LH3 3 -+#define SCOCR1LH4 4 -+#define SCOCR1LH5 5 -+#define SCOCR1LH6 6 -+#define SCOCR1LH7 7 -+ -+#define SCOCR1HL _SFR_MEM8(0xF7) -+#define SCOCR1HL0 0 -+#define SCOCR1HL1 1 -+#define SCOCR1HL2 2 -+#define SCOCR1HL3 3 -+#define SCOCR1HL4 4 -+#define SCOCR1HL5 5 -+#define SCOCR1HL6 6 -+#define SCOCR1HL7 7 -+ -+#define SCOCR1HH _SFR_MEM8(0xF8) -+#define SCOCR1HH0 0 -+#define SCOCR1HH1 1 -+#define SCOCR1HH2 2 -+#define SCOCR1HH3 3 -+#define SCOCR1HH4 4 -+#define SCOCR1HH5 5 -+#define SCOCR1HH6 6 -+#define SCOCR1HH7 7 -+ -+#define SCTSTRLL _SFR_MEM8(0xF9) -+#define SCTSTRLL0 0 -+#define SCTSTRLL1 1 -+#define SCTSTRLL2 2 -+#define SCTSTRLL3 3 -+#define SCTSTRLL4 4 -+#define SCTSTRLL5 5 -+#define SCTSTRLL6 6 -+#define SCTSTRLL7 7 -+ -+#define SCTSTRLH _SFR_MEM8(0xFA) -+#define SCTSTRLH0 0 -+#define SCTSTRLH1 1 -+#define SCTSTRLH2 2 -+#define SCTSTRLH3 3 -+#define SCTSTRLH4 4 -+#define SCTSTRLH5 5 -+#define SCTSTRLH6 6 -+#define SCTSTRLH7 7 -+ -+#define SCTSTRHL _SFR_MEM8(0xFB) -+#define SCTSTRHL0 0 -+#define SCTSTRHL1 1 -+#define SCTSTRHL2 2 -+#define SCTSTRHL3 3 -+#define SCTSTRHL4 4 -+#define SCTSTRHL5 5 -+#define SCTSTRHL6 6 -+#define SCTSTRHL7 7 -+ -+#define SCTSTRHH _SFR_MEM8(0xFC) -+#define SCTSTRHH0 0 -+#define SCTSTRHH1 1 -+#define SCTSTRHH2 2 -+#define SCTSTRHH3 3 -+#define SCTSTRHH4 4 -+#define SCTSTRHH5 5 -+#define SCTSTRHH6 6 -+#define SCTSTRHH7 7 -+ -+/* Reserved [0xFD..0x10B] */ -+ -+#define MAFCR0 _SFR_MEM8(0x10C) -+#define MAF0EN 0 -+#define MAF1EN 1 -+#define MAF2EN 2 -+#define MAF3EN 3 -+ -+#define MAFCR1 _SFR_MEM8(0x10D) -+#define AACK_0_I_AM_COORD 0 -+#define AACK_0_SET_PD 1 -+#define AACK_1_I_AM_COORD 2 -+#define AACK_1_SET_PD 3 -+#define AACK_2_I_AM_COORD 4 -+#define AACK_2_SET_PD 5 -+#define AACK_3_I_AM_COORD 6 -+#define AACK_3_SET_PD 7 -+ -+#define MAFSA0L _SFR_MEM8(0x10E) -+#define MAFSA0L0 0 -+#define MAFSA0L1 1 -+#define MAFSA0L2 2 -+#define MAFSA0L3 3 -+#define MAFSA0L4 4 -+#define MAFSA0L5 5 -+#define MAFSA0L6 6 -+#define MAFSA0L7 7 -+ -+#define MAFSA0H _SFR_MEM8(0x10F) -+#define MAFSA0H0 0 -+#define MAFSA0H1 1 -+#define MAFSA0H2 2 -+#define MAFSA0H3 3 -+#define MAFSA0H4 4 -+#define MAFSA0H5 5 -+#define MAFSA0H6 6 -+#define MAFSA0H7 7 -+ -+#define MAFPA0L _SFR_MEM8(0x110) -+#define MAFPA0L0 0 -+#define MAFPA0L1 1 -+#define MAFPA0L2 2 -+#define MAFPA0L3 3 -+#define MAFPA0L4 4 -+#define MAFPA0L5 5 -+#define MAFPA0L6 6 -+#define MAFPA0L7 7 -+ -+#define MAFPA0H _SFR_MEM8(0x111) -+#define MAFPA0H0 0 -+#define MAFPA0H1 1 -+#define MAFPA0H2 2 -+#define MAFPA0H3 3 -+#define MAFPA0H4 4 -+#define MAFPA0H5 5 -+#define MAFPA0H6 6 -+#define MAFPA0H7 7 -+ -+#define MAFSA1L _SFR_MEM8(0x112) -+#define MAFSA1L0 0 -+#define MAFSA1L1 1 -+#define MAFSA1L2 2 -+#define MAFSA1L3 3 -+#define MAFSA1L4 4 -+#define MAFSA1L5 5 -+#define MAFSA1L6 6 -+#define MAFSA1L7 7 -+ -+#define MAFSA1H _SFR_MEM8(0x113) -+#define MAFSA1H0 0 -+#define MAFSA1H1 1 -+#define MAFSA1H2 2 -+#define MAFSA1H3 3 -+#define MAFSA1H4 4 -+#define MAFSA1H5 5 -+#define MAFSA1H6 6 -+#define MAFSA1H7 7 -+ -+#define MAFPA1L _SFR_MEM8(0x114) -+#define MAFPA1L0 0 -+#define MAFPA1L1 1 -+#define MAFPA1L2 2 -+#define MAFPA1L3 3 -+#define MAFPA1L4 4 -+#define MAFPA1L5 5 -+#define MAFPA1L6 6 -+#define MAFPA1L7 7 -+ -+#define MAFPA1H _SFR_MEM8(0x115) -+#define MAFPA1H0 0 -+#define MAFPA1H1 1 -+#define MAFPA1H2 2 -+#define MAFPA1H3 3 -+#define MAFPA1H4 4 -+#define MAFPA1H5 5 -+#define MAFPA1H6 6 -+#define MAFPA1H7 7 -+ -+#define MAFSA2L _SFR_MEM8(0x116) -+#define MAFSA2L0 0 -+#define MAFSA2L1 1 -+#define MAFSA2L2 2 -+#define MAFSA2L3 3 -+#define MAFSA2L4 4 -+#define MAFSA2L5 5 -+#define MAFSA2L6 6 -+#define MAFSA2L7 7 -+ -+#define MAFSA2H _SFR_MEM8(0x117) -+#define MAFSA2H0 0 -+#define MAFSA2H1 1 -+#define MAFSA2H2 2 -+#define MAFSA2H3 3 -+#define MAFSA2H4 4 -+#define MAFSA2H5 5 -+#define MAFSA2H6 6 -+#define MAFSA2H7 7 -+ -+#define MAFPA2L _SFR_MEM8(0x118) -+#define MAFPA2L0 0 -+#define MAFPA2L1 1 -+#define MAFPA2L2 2 -+#define MAFPA2L3 3 -+#define MAFPA2L4 4 -+#define MAFPA2L5 5 -+#define MAFPA2L6 6 -+#define MAFPA2L7 7 -+ -+#define MAFPA2H _SFR_MEM8(0x119) -+#define MAFPA2H0 0 -+#define MAFPA2H1 1 -+#define MAFPA2H2 2 -+#define MAFPA2H3 3 -+#define MAFPA2H4 4 -+#define MAFPA2H5 5 -+#define MAFPA2H6 6 -+#define MAFPA2H7 7 -+ -+#define MAFSA3L _SFR_MEM8(0x11A) -+#define MAFSA3L0 0 -+#define MAFSA3L1 1 -+#define MAFSA3L2 2 -+#define MAFSA3L3 3 -+#define MAFSA3L4 4 -+#define MAFSA3L5 5 -+#define MAFSA3L6 6 -+#define MAFSA3L7 7 -+ -+#define MAFSA3H _SFR_MEM8(0x11B) -+#define MAFSA3H0 0 -+#define MAFSA3H1 1 -+#define MAFSA3H2 2 -+#define MAFSA3H3 3 -+#define MAFSA3H4 4 -+#define MAFSA3H5 5 -+#define MAFSA3H6 6 -+#define MAFSA3H7 7 -+ -+#define MAFPA3L _SFR_MEM8(0x11C) -+#define MAFPA3L0 0 -+#define MAFPA3L1 1 -+#define MAFPA3L2 2 -+#define MAFPA3L3 3 -+#define MAFPA3L4 4 -+#define MAFPA3L5 5 -+#define MAFPA3L6 6 -+#define MAFPA3L7 7 -+ -+#define MAFPA3H _SFR_MEM8(0x11D) -+#define MAFPA3H0 0 -+#define MAFPA3H1 1 -+#define MAFPA3H2 2 -+#define MAFPA3H3 3 -+#define MAFPA3H4 4 -+#define MAFPA3H5 5 -+#define MAFPA3H6 6 -+#define MAFPA3H7 7 -+ -+/* Reserved [0x11E..0x11F] */ -+ -+#define TCCR5A _SFR_MEM8(0x120) -+#define WGM50 0 -+#define WGM51 1 -+#define COM5C0 2 -+#define COM5C1 3 -+#define COM5B0 4 -+#define COM5B1 5 -+#define COM5A0 6 -+#define COM5A1 7 -+ -+#define TCCR5B _SFR_MEM8(0x121) -+#define CS50 0 -+#define CS51 1 -+#define CS52 2 -+#define WGM52 3 -+#define WGM53 4 -+#define ICES5 6 -+#define ICNC5 7 -+ -+#define TCCR5C _SFR_MEM8(0x122) -+#define FOC5C 5 -+#define FOC5B 6 -+#define FOC5A 7 -+ -+/* Reserved [0x123] */ -+ -+/* Combine TCNT5L and TCNT5H */ -+#define TCNT5 _SFR_MEM16(0x124) -+ -+#define TCNT5L _SFR_MEM8(0x124) -+#define TCNT5H _SFR_MEM8(0x125) -+ -+/* Combine ICR5L and ICR5H */ -+#define ICR5 _SFR_MEM16(0x126) -+ -+#define ICR5L _SFR_MEM8(0x126) -+#define ICR5H _SFR_MEM8(0x127) -+ -+/* Combine OCR5AL and OCR5AH */ -+#define OCR5A _SFR_MEM16(0x128) -+ -+#define OCR5AL _SFR_MEM8(0x128) -+#define OCR5AH _SFR_MEM8(0x129) -+ -+/* Combine OCR5BL and OCR5BH */ -+#define OCR5B _SFR_MEM16(0x12A) -+ -+#define OCR5BL _SFR_MEM8(0x12A) -+#define OCR5BH _SFR_MEM8(0x12B) -+ -+/* Combine OCR5CL and OCR5CH */ -+#define OCR5C _SFR_MEM16(0x12C) -+ -+#define OCR5CL _SFR_MEM8(0x12C) -+#define OCR5CH _SFR_MEM8(0x12D) -+ -+/* Reserved [0x12E] */ -+ -+#define LLCR _SFR_MEM8(0x12F) -+#define LLENCAL 0 -+#define LLSHORT 1 -+#define LLTCO 2 -+#define LLCAL 3 -+#define LLCOMP 4 -+#define LLDONE 5 -+ -+#define LLDRL _SFR_MEM8(0x130) -+#define LLDRL0 0 -+#define LLDRL1 1 -+#define LLDRL2 2 -+#define LLDRL3 3 -+ -+#define LLDRH _SFR_MEM8(0x131) -+#define LLDRH0 0 -+#define LLDRH1 1 -+#define LLDRH2 2 -+#define LLDRH3 3 -+#define LLDRH4 4 -+ -+#define DRTRAM3 _SFR_MEM8(0x132) -+#define ENDRT 4 -+#define DRTSWOK 5 -+ -+#define DRTRAM2 _SFR_MEM8(0x133) -+ -+#define DRTRAM1 _SFR_MEM8(0x134) -+ -+#define DRTRAM0 _SFR_MEM8(0x135) -+ -+#define DPDS0 _SFR_MEM8(0x136) -+#define PBDRV0 0 -+#define PBDRV1 1 -+#define PDDRV0 2 -+#define PDDRV1 3 -+#define PEDRV0 4 -+#define PEDRV1 5 -+#define PFDRV0 6 -+#define PFDRV1 7 -+ -+#define DPDS1 _SFR_MEM8(0x137) -+#define PGDRV0 0 -+#define PGDRV1 1 -+ -+#define PARCR _SFR_MEM8(0x138) -+#define PARUFI 0 -+#define PARDFI 1 -+#define PALTU0 2 -+#define PALTU1 3 -+#define PALTU2 4 -+#define PALTD0 5 -+#define PALTD1 6 -+#define PALTD2 7 -+ -+#define TRXPR _SFR_MEM8(0x139) -+#define TRXRST 0 -+#define SLPTR 1 -+ -+/* Reserved [0x13A..0x13B] */ -+ -+#define AES_CTRL _SFR_MEM8(0x13C) -+#define AES_IM 2 -+#define AES_DIR 3 -+#define AES_MODE 5 -+#define AES_REQUEST 7 -+ -+#define AES_STATUS _SFR_MEM8(0x13D) -+#define AES_DONE 0 -+#define AES_ER 7 -+ -+#define AES_STATE _SFR_MEM8(0x13E) -+#define AES_STATE0 0 -+#define AES_STATE1 1 -+#define AES_STATE2 2 -+#define AES_STATE3 3 -+#define AES_STATE4 4 -+#define AES_STATE5 5 -+#define AES_STATE6 6 -+#define AES_STATE7 7 -+ -+#define AES_KEY _SFR_MEM8(0x13F) -+#define AES_KEY0 0 -+#define AES_KEY1 1 -+#define AES_KEY2 2 -+#define AES_KEY3 3 -+#define AES_KEY4 4 -+#define AES_KEY5 5 -+#define AES_KEY6 6 -+#define AES_KEY7 7 -+ -+/* Reserved [0x140] */ -+ -+#define TRX_STATUS _SFR_MEM8(0x141) -+#define TRX_STATUS0 0 -+#define TRX_STATUS1 1 -+#define TRX_STATUS2 2 -+#define TRX_STATUS3 3 -+#define TRX_STATUS4 4 -+#define TST_STATUS 5 -+#define CCA_STATUS 6 -+#define CCA_DONE 7 -+ -+#define TRX_STATE _SFR_MEM8(0x142) -+#define TRX_CMD0 0 -+#define TRX_CMD1 1 -+#define TRX_CMD2 2 -+#define TRX_CMD3 3 -+#define TRX_CMD4 4 -+#define TRAC_STATUS0 5 -+#define TRAC_STATUS1 6 -+#define TRAC_STATUS2 7 -+ -+#define TRX_CTRL_0 _SFR_MEM8(0x143) -+#define PMU_IF_INV 4 -+#define PMU_START 5 -+#define PMU_EN 6 -+#define Res7 7 -+ -+#define TRX_CTRL_1 _SFR_MEM8(0x144) -+#define PLL_TX_FLT 4 -+#define TX_AUTO_CRC_ON 5 -+#define IRQ_2_EXT_EN 6 -+#define PA_EXT_EN 7 -+ -+#define PHY_TX_PWR _SFR_MEM8(0x145) -+#define TX_PWR0 0 -+#define TX_PWR1 1 -+#define TX_PWR2 2 -+#define TX_PWR3 3 -+ -+#define PHY_RSSI _SFR_MEM8(0x146) -+#define RSSI0 0 -+#define RSSI1 1 -+#define RSSI2 2 -+#define RSSI3 3 -+#define RSSI4 4 -+#define RND_VALUE0 5 -+#define RND_VALUE1 6 -+#define RX_CRC_VALID 7 -+ -+#define PHY_ED_LEVEL _SFR_MEM8(0x147) -+#define ED_LEVEL0 0 -+#define ED_LEVEL1 1 -+#define ED_LEVEL2 2 -+#define ED_LEVEL3 3 -+#define ED_LEVEL4 4 -+#define ED_LEVEL5 5 -+#define ED_LEVEL6 6 -+#define ED_LEVEL7 7 -+ -+#define PHY_CC_CCA _SFR_MEM8(0x148) -+#define CHANNEL0 0 -+#define CHANNEL1 1 -+#define CHANNEL2 2 -+#define CHANNEL3 3 -+#define CHANNEL4 4 -+#define CCA_MODE0 5 -+#define CCA_MODE1 6 -+#define CCA_REQUEST 7 -+ -+#define CCA_THRES _SFR_MEM8(0x149) -+#define CCA_ED_THRES0 0 -+#define CCA_ED_THRES1 1 -+#define CCA_ED_THRES2 2 -+#define CCA_ED_THRES3 3 -+#define CCA_CS_THRES0 4 -+#define CCA_CS_THRES1 5 -+#define CCA_CS_THRES2 6 -+#define CCA_CS_THRES3 7 -+ -+#define RX_CTRL _SFR_MEM8(0x14A) -+#define PDT_THRES0 0 -+#define PDT_THRES1 1 -+#define PDT_THRES2 2 -+#define PDT_THRES3 3 -+ -+#define SFD_VALUE _SFR_MEM8(0x14B) -+#define SFD_VALUE0 0 -+#define SFD_VALUE1 1 -+#define SFD_VALUE2 2 -+#define SFD_VALUE3 3 -+#define SFD_VALUE4 4 -+#define SFD_VALUE5 5 -+#define SFD_VALUE6 6 -+#define SFD_VALUE7 7 -+ -+#define TRX_CTRL_2 _SFR_MEM8(0x14C) -+#define OQPSK_DATA_RATE0 0 -+#define OQPSK_DATA_RATE1 1 -+#define RX_SAFE_MODE 7 -+ -+#define ANT_DIV _SFR_MEM8(0x14D) -+#define ANT_CTRL0 0 -+#define ANT_CTRL1 1 -+#define ANT_EXT_SW_EN 2 -+#define ANT_DIV_EN 3 -+#define ANT_SEL 7 -+ -+#define IRQ_MASK _SFR_MEM8(0x14E) -+#define PLL_LOCK_EN 0 -+#define PLL_UNLOCK_EN 1 -+#define RX_START_EN 2 -+#define RX_END_EN 3 -+#define CCA_ED_DONE_EN 4 -+#define AMI_EN 5 -+#define TX_END_EN 6 -+#define AWAKE_EN 7 -+ -+#define IRQ_STATUS _SFR_MEM8(0x14F) -+#define PLL_LOCK 0 -+#define PLL_UNLOCK 1 -+#define RX_START 2 -+#define RX_END 3 -+#define CCA_ED_DONE 4 -+#define AMI 5 -+#define TX_END 6 -+#define AWAKE 7 -+ -+#define VREG_CTRL _SFR_MEM8(0x150) -+#define DVDD_OK 2 -+#define DVREG_EXT 3 -+#define AVDD_OK 6 -+#define AVREG_EXT 7 -+ -+#define BATMON _SFR_MEM8(0x151) -+#define BATMON_VTH0 0 -+#define BATMON_VTH1 1 -+#define BATMON_VTH2 2 -+#define BATMON_VTH3 3 -+#define BATMON_HR 4 -+#define BATMON_OK 5 -+#define BAT_LOW_EN 6 -+#define BAT_LOW 7 -+ -+#define XOSC_CTRL _SFR_MEM8(0x152) -+#define XTAL_TRIM0 0 -+#define XTAL_TRIM1 1 -+#define XTAL_TRIM2 2 -+#define XTAL_TRIM3 3 -+#define XTAL_MODE0 4 -+#define XTAL_MODE1 5 -+#define XTAL_MODE2 6 -+#define XTAL_MODE3 7 -+ -+#define CC_CTRL_0 _SFR_MEM8(0x153) -+#define CC_NUMBER0 0 -+#define CC_NUMBER1 1 -+#define CC_NUMBER2 2 -+#define CC_NUMBER3 3 -+#define CC_NUMBER4 4 -+#define CC_NUMBER5 5 -+#define CC_NUMBER6 6 -+#define CC_NUMBER7 7 -+ -+#define CC_CTRL_1 _SFR_MEM8(0x154) -+#define CC_BAND0 0 -+#define CC_BAND1 1 -+#define CC_BAND2 2 -+#define CC_BAND3 3 -+ -+#define RX_SYN _SFR_MEM8(0x155) -+#define RX_PDT_LEVEL0 0 -+#define RX_PDT_LEVEL1 1 -+#define RX_PDT_LEVEL2 2 -+#define RX_PDT_LEVEL3 3 -+#define RX_OVERRIDE 6 -+#define RX_PDT_DIS 7 -+ -+#define TRX_RPC _SFR_MEM8(0x156) -+#define XAH_RPC_EN 0 -+#define IPAN_RPC_EN 1 -+#define PLL_RPC_EN 3 -+#define PDT_RPC_EN 4 -+#define RX_RPC_EN 5 -+#define RX_RPC_CTRL0 6 -+#define RX_RPC_CTRL1 7 -+ -+#define XAH_CTRL_1 _SFR_MEM8(0x157) -+#define AACK_PROM_MODE 1 -+#define AACK_ACK_TIME 2 -+#define AACK_UPLD_RES_FT 4 -+#define AACK_FLTR_RES_FT 5 -+ -+#define FTN_CTRL _SFR_MEM8(0x158) -+#define FTN_START 7 -+ -+/* Reserved [0x159] */ -+ -+#define PLL_CF _SFR_MEM8(0x15A) -+#define PLL_CF_START 7 -+ -+#define PLL_DCU _SFR_MEM8(0x15B) -+#define PLL_DCU_START 7 -+ -+#define PART_NUM _SFR_MEM8(0x15C) -+#define PART_NUM0 0 -+#define PART_NUM1 1 -+#define PART_NUM2 2 -+#define PART_NUM3 3 -+#define PART_NUM4 4 -+#define PART_NUM5 5 -+#define PART_NUM6 6 -+#define PART_NUM7 7 -+ -+#define VERSION_NUM _SFR_MEM8(0x15D) -+#define VERSION_NUM0 0 -+#define VERSION_NUM1 1 -+#define VERSION_NUM2 2 -+#define VERSION_NUM3 3 -+#define VERSION_NUM4 4 -+#define VERSION_NUM5 5 -+#define VERSION_NUM6 6 -+#define VERSION_NUM7 7 -+ -+#define MAN_ID_0 _SFR_MEM8(0x15E) -+#define MAN_ID_00 0 -+#define MAN_ID_01 1 -+#define MAN_ID_02 2 -+#define MAN_ID_03 3 -+#define MAN_ID_04 4 -+#define MAN_ID_05 5 -+#define MAN_ID_06 6 -+#define MAN_ID_07 7 -+ -+#define MAN_ID_1 _SFR_MEM8(0x15F) -+#define MAN_ID_10 0 -+#define MAN_ID_11 1 -+#define MAN_ID_12 2 -+#define MAN_ID_13 3 -+#define MAN_ID_14 4 -+#define MAN_ID_15 5 -+#define MAN_ID_16 6 -+#define MAN_ID_17 7 -+ -+#define SHORT_ADDR_0 _SFR_MEM8(0x160) -+#define SHORT_ADDR_00 0 -+#define SHORT_ADDR_01 1 -+#define SHORT_ADDR_02 2 -+#define SHORT_ADDR_03 3 -+#define SHORT_ADDR_04 4 -+#define SHORT_ADDR_05 5 -+#define SHORT_ADDR_06 6 -+#define SHORT_ADDR_07 7 -+ -+#define SHORT_ADDR_1 _SFR_MEM8(0x161) -+#define SHORT_ADDR_10 0 -+#define SHORT_ADDR_11 1 -+#define SHORT_ADDR_12 2 -+#define SHORT_ADDR_13 3 -+#define SHORT_ADDR_14 4 -+#define SHORT_ADDR_15 5 -+#define SHORT_ADDR_16 6 -+#define SHORT_ADDR_17 7 -+ -+#define PAN_ID_0 _SFR_MEM8(0x162) -+#define PAN_ID_00 0 -+#define PAN_ID_01 1 -+#define PAN_ID_02 2 -+#define PAN_ID_03 3 -+#define PAN_ID_04 4 -+#define PAN_ID_05 5 -+#define PAN_ID_06 6 -+#define PAN_ID_07 7 -+ -+#define PAN_ID_1 _SFR_MEM8(0x163) -+#define PAN_ID_10 0 -+#define PAN_ID_11 1 -+#define PAN_ID_12 2 -+#define PAN_ID_13 3 -+#define PAN_ID_14 4 -+#define PAN_ID_15 5 -+#define PAN_ID_16 6 -+#define PAN_ID_17 7 -+ -+#define IEEE_ADDR_0 _SFR_MEM8(0x164) -+#define IEEE_ADDR_00 0 -+#define IEEE_ADDR_01 1 -+#define IEEE_ADDR_02 2 -+#define IEEE_ADDR_03 3 -+#define IEEE_ADDR_04 4 -+#define IEEE_ADDR_05 5 -+#define IEEE_ADDR_06 6 -+#define IEEE_ADDR_07 7 -+ -+#define IEEE_ADDR_1 _SFR_MEM8(0x165) -+#define IEEE_ADDR_10 0 -+#define IEEE_ADDR_11 1 -+#define IEEE_ADDR_12 2 -+#define IEEE_ADDR_13 3 -+#define IEEE_ADDR_14 4 -+#define IEEE_ADDR_15 5 -+#define IEEE_ADDR_16 6 -+#define IEEE_ADDR_17 7 -+ -+#define IEEE_ADDR_2 _SFR_MEM8(0x166) -+#define IEEE_ADDR_20 0 -+#define IEEE_ADDR_21 1 -+#define IEEE_ADDR_22 2 -+#define IEEE_ADDR_23 3 -+#define IEEE_ADDR_24 4 -+#define IEEE_ADDR_25 5 -+#define IEEE_ADDR_26 6 -+#define IEEE_ADDR_27 7 -+ -+#define IEEE_ADDR_3 _SFR_MEM8(0x167) -+#define IEEE_ADDR_30 0 -+#define IEEE_ADDR_31 1 -+#define IEEE_ADDR_32 2 -+#define IEEE_ADDR_33 3 -+#define IEEE_ADDR_34 4 -+#define IEEE_ADDR_35 5 -+#define IEEE_ADDR_36 6 -+#define IEEE_ADDR_37 7 -+ -+#define IEEE_ADDR_4 _SFR_MEM8(0x168) -+#define IEEE_ADDR_40 0 -+#define IEEE_ADDR_41 1 -+#define IEEE_ADDR_42 2 -+#define IEEE_ADDR_43 3 -+#define IEEE_ADDR_44 4 -+#define IEEE_ADDR_45 5 -+#define IEEE_ADDR_46 6 -+#define IEEE_ADDR_47 7 -+ -+#define IEEE_ADDR_5 _SFR_MEM8(0x169) -+#define IEEE_ADDR_50 0 -+#define IEEE_ADDR_51 1 -+#define IEEE_ADDR_52 2 -+#define IEEE_ADDR_53 3 -+#define IEEE_ADDR_54 4 -+#define IEEE_ADDR_55 5 -+#define IEEE_ADDR_56 6 -+#define IEEE_ADDR_57 7 -+ -+#define IEEE_ADDR_6 _SFR_MEM8(0x16A) -+#define IEEE_ADDR_60 0 -+#define IEEE_ADDR_61 1 -+#define IEEE_ADDR_62 2 -+#define IEEE_ADDR_63 3 -+#define IEEE_ADDR_64 4 -+#define IEEE_ADDR_65 5 -+#define IEEE_ADDR_66 6 -+#define IEEE_ADDR_67 7 -+ -+#define IEEE_ADDR_7 _SFR_MEM8(0x16B) -+#define IEEE_ADDR_70 0 -+#define IEEE_ADDR_71 1 -+#define IEEE_ADDR_72 2 -+#define IEEE_ADDR_73 3 -+#define IEEE_ADDR_74 4 -+#define IEEE_ADDR_75 5 -+#define IEEE_ADDR_76 6 -+#define IEEE_ADDR_77 7 -+ -+#define XAH_CTRL_0 _SFR_MEM8(0x16C) -+#define SLOTTED_OPERATION 0 -+#define MAX_CSMA_RETRIES0 1 -+#define MAX_CSMA_RETRIES1 2 -+#define MAX_CSMA_RETRIES2 3 -+#define MAX_FRAME_RETRIES0 4 -+#define MAX_FRAME_RETRIES1 5 -+#define MAX_FRAME_RETRIES2 6 -+#define MAX_FRAME_RETRIES3 7 -+ -+#define CSMA_SEED_0 _SFR_MEM8(0x16D) -+#define CSMA_SEED_00 0 -+#define CSMA_SEED_01 1 -+#define CSMA_SEED_02 2 -+#define CSMA_SEED_03 3 -+#define CSMA_SEED_04 4 -+#define CSMA_SEED_05 5 -+#define CSMA_SEED_06 6 -+#define CSMA_SEED_07 7 -+ -+#define CSMA_SEED_1 _SFR_MEM8(0x16E) -+#define CSMA_SEED_10 0 -+#define CSMA_SEED_11 1 -+#define CSMA_SEED_12 2 -+#define AACK_I_AM_COORD 3 -+#define AACK_DIS_ACK 4 -+#define AACK_SET_PD 5 -+#define AACK_FVN_MODE0 6 -+#define AACK_FVN_MODE1 7 -+ -+#define CSMA_BE _SFR_MEM8(0x16F) -+#define MIN_BE0 0 -+#define MIN_BE1 1 -+#define MIN_BE2 2 -+#define MIN_BE3 3 -+#define MAX_BE0 4 -+#define MAX_BE1 5 -+#define MAX_BE2 6 -+#define MAX_BE3 7 -+ -+/* Reserved [0x170..0x175] */ -+ -+#define TST_CTRL_DIGI _SFR_MEM8(0x176) -+#define TST_CTRL_DIG0 0 -+#define TST_CTRL_DIG1 1 -+#define TST_CTRL_DIG2 2 -+#define TST_CTRL_DIG3 3 -+ -+/* Reserved [0x177..0x17A] */ -+ -+#define TST_RX_LENGTH _SFR_MEM8(0x17B) -+#define RX_LENGTH0 0 -+#define RX_LENGTH1 1 -+#define RX_LENGTH2 2 -+#define RX_LENGTH3 3 -+#define RX_LENGTH4 4 -+#define RX_LENGTH5 5 -+#define RX_LENGTH6 6 -+#define RX_LENGTH7 7 -+ -+/* Reserved [0x17C..0x17F] */ -+ -+#define TRXFBST _SFR_MEM8(0x180) -+ -+/* Reserved [0x181..0x1FE] */ -+ -+#define TRXFBEND _SFR_MEM8(0x1FF) -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* External Interrupt Request 2 */ -+#define INT2_vect _VECTOR(3) -+#define INT2_vect_num 3 -+ -+/* External Interrupt Request 3 */ -+#define INT3_vect _VECTOR(4) -+#define INT3_vect_num 4 -+ -+/* External Interrupt Request 4 */ -+#define INT4_vect _VECTOR(5) -+#define INT4_vect_num 5 -+ -+/* External Interrupt Request 5 */ -+#define INT5_vect _VECTOR(6) -+#define INT5_vect_num 6 -+ -+/* External Interrupt Request 6 */ -+#define INT6_vect _VECTOR(7) -+#define INT6_vect_num 7 -+ -+/* External Interrupt Request 7 */ -+#define INT7_vect _VECTOR(8) -+#define INT7_vect_num 8 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(9) -+#define PCINT0_vect_num 9 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(10) -+#define PCINT1_vect_num 10 -+ -+/* Pin Change Interrupt Request 2 */ -+#define PCINT2_vect _VECTOR(11) -+#define PCINT2_vect_num 11 -+ -+/* Watchdog Time-out Interrupt */ -+#define WDT_vect _VECTOR(12) -+#define WDT_vect_num 12 -+ -+/* Timer/Counter2 Compare Match A */ -+#define TIMER2_COMPA_vect _VECTOR(13) -+#define TIMER2_COMPA_vect_num 13 -+ -+/* Timer/Counter2 Compare Match B */ -+#define TIMER2_COMPB_vect _VECTOR(14) -+#define TIMER2_COMPB_vect_num 14 -+ -+/* Timer/Counter2 Overflow */ -+#define TIMER2_OVF_vect _VECTOR(15) -+#define TIMER2_OVF_vect_num 15 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(16) -+#define TIMER1_CAPT_vect_num 16 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(17) -+#define TIMER1_COMPA_vect_num 17 -+ -+/* Timer/Counter1 Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(18) -+#define TIMER1_COMPB_vect_num 18 -+ -+/* Timer/Counter1 Compare Match C */ -+#define TIMER1_COMPC_vect _VECTOR(19) -+#define TIMER1_COMPC_vect_num 19 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(20) -+#define TIMER1_OVF_vect_num 20 -+ -+/* Timer/Counter0 Compare Match A */ -+#define TIMER0_COMPA_vect _VECTOR(21) -+#define TIMER0_COMPA_vect_num 21 -+ -+/* Timer/Counter0 Compare Match B */ -+#define TIMER0_COMPB_vect _VECTOR(22) -+#define TIMER0_COMPB_vect_num 22 -+ -+/* Timer/Counter0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(23) -+#define TIMER0_OVF_vect_num 23 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(24) -+#define SPI_STC_vect_num 24 -+ -+/* USART0, Rx Complete */ -+#define USART0_RX_vect _VECTOR(25) -+#define USART0_RX_vect_num 25 -+ -+/* USART0 Data register Empty */ -+#define USART0_UDRE_vect _VECTOR(26) -+#define USART0_UDRE_vect_num 26 -+ -+/* USART0, Tx Complete */ -+#define USART0_TX_vect _VECTOR(27) -+#define USART0_TX_vect_num 27 -+ -+/* Analog Comparator */ -+#define ANALOG_COMP_vect _VECTOR(28) -+#define ANALOG_COMP_vect_num 28 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(29) -+#define ADC_vect_num 29 -+ -+/* EEPROM Ready */ -+#define EE_READY_vect _VECTOR(30) -+#define EE_READY_vect_num 30 -+ -+/* Timer/Counter3 Capture Event */ -+#define TIMER3_CAPT_vect _VECTOR(31) -+#define TIMER3_CAPT_vect_num 31 -+ -+/* Timer/Counter3 Compare Match A */ -+#define TIMER3_COMPA_vect _VECTOR(32) -+#define TIMER3_COMPA_vect_num 32 -+ -+/* Timer/Counter3 Compare Match B */ -+#define TIMER3_COMPB_vect _VECTOR(33) -+#define TIMER3_COMPB_vect_num 33 -+ -+/* Timer/Counter3 Compare Match C */ -+#define TIMER3_COMPC_vect _VECTOR(34) -+#define TIMER3_COMPC_vect_num 34 -+ -+/* Timer/Counter3 Overflow */ -+#define TIMER3_OVF_vect _VECTOR(35) -+#define TIMER3_OVF_vect_num 35 -+ -+/* USART1, Rx Complete */ -+#define USART1_RX_vect _VECTOR(36) -+#define USART1_RX_vect_num 36 -+ -+/* USART1 Data register Empty */ -+#define USART1_UDRE_vect _VECTOR(37) -+#define USART1_UDRE_vect_num 37 -+ -+/* USART1, Tx Complete */ -+#define USART1_TX_vect _VECTOR(38) -+#define USART1_TX_vect_num 38 -+ -+/* 2-wire Serial Interface */ -+#define TWI_vect _VECTOR(39) -+#define TWI_vect_num 39 -+ -+/* Store Program Memory Read */ -+#define SPM_READY_vect _VECTOR(40) -+#define SPM_READY_vect_num 40 -+ -+/* Timer/Counter4 Capture Event */ -+#define TIMER4_CAPT_vect _VECTOR(41) -+#define TIMER4_CAPT_vect_num 41 -+ -+/* Timer/Counter4 Compare Match A */ -+#define TIMER4_COMPA_vect _VECTOR(42) -+#define TIMER4_COMPA_vect_num 42 -+ -+/* Timer/Counter4 Compare Match B */ -+#define TIMER4_COMPB_vect _VECTOR(43) -+#define TIMER4_COMPB_vect_num 43 -+ -+/* Timer/Counter4 Compare Match C */ -+#define TIMER4_COMPC_vect _VECTOR(44) -+#define TIMER4_COMPC_vect_num 44 -+ -+/* Timer/Counter4 Overflow */ -+#define TIMER4_OVF_vect _VECTOR(45) -+#define TIMER4_OVF_vect_num 45 -+ -+/* Timer/Counter5 Capture Event */ -+#define TIMER5_CAPT_vect _VECTOR(46) -+#define TIMER5_CAPT_vect_num 46 -+ -+/* Timer/Counter5 Compare Match A */ -+#define TIMER5_COMPA_vect _VECTOR(47) -+#define TIMER5_COMPA_vect_num 47 -+ -+/* Timer/Counter5 Compare Match B */ -+#define TIMER5_COMPB_vect _VECTOR(48) -+#define TIMER5_COMPB_vect_num 48 -+ -+/* Timer/Counter5 Compare Match C */ -+#define TIMER5_COMPC_vect _VECTOR(49) -+#define TIMER5_COMPC_vect_num 49 -+ -+/* Timer/Counter5 Overflow */ -+#define TIMER5_OVF_vect _VECTOR(50) -+#define TIMER5_OVF_vect_num 50 -+ -+/* USART2, Rx Complete */ -+#define USART2_RX_vect _VECTOR(51) -+#define USART2_RX_vect_num 51 -+ -+/* USART2 Data register Empty */ -+#define USART2_UDRE_vect _VECTOR(52) -+#define USART2_UDRE_vect_num 52 -+ -+/* USART2, Tx Complete */ -+#define USART2_TX_vect _VECTOR(53) -+#define USART2_TX_vect_num 53 -+ -+/* USART3, Rx Complete */ -+#define USART3_RX_vect _VECTOR(54) -+#define USART3_RX_vect_num 54 -+ -+/* USART3 Data register Empty */ -+#define USART3_UDRE_vect _VECTOR(55) -+#define USART3_UDRE_vect_num 55 -+ -+/* USART3, Tx Complete */ -+#define USART3_TX_vect _VECTOR(56) -+#define USART3_TX_vect_num 56 -+ -+/* TRX24 - PLL lock interrupt */ -+#define TRX24_PLL_LOCK_vect _VECTOR(57) -+#define TRX24_PLL_LOCK_vect_num 57 -+ -+/* TRX24 - PLL unlock interrupt */ -+#define TRX24_PLL_UNLOCK_vect _VECTOR(58) -+#define TRX24_PLL_UNLOCK_vect_num 58 -+ -+/* TRX24 - Receive start interrupt */ -+#define TRX24_RX_START_vect _VECTOR(59) -+#define TRX24_RX_START_vect_num 59 -+ -+/* TRX24 - RX_END interrupt */ -+#define TRX24_RX_END_vect _VECTOR(60) -+#define TRX24_RX_END_vect_num 60 -+ -+/* TRX24 - CCA/ED done interrupt */ -+#define TRX24_CCA_ED_DONE_vect _VECTOR(61) -+#define TRX24_CCA_ED_DONE_vect_num 61 -+ -+/* TRX24 - XAH - AMI */ -+#define TRX24_XAH_AMI_vect _VECTOR(62) -+#define TRX24_XAH_AMI_vect_num 62 -+ -+/* TRX24 - TX_END interrupt */ -+#define TRX24_TX_END_vect _VECTOR(63) -+#define TRX24_TX_END_vect_num 63 -+ -+/* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */ -+#define TRX24_AWAKE_vect _VECTOR(64) -+#define TRX24_AWAKE_vect_num 64 -+ -+/* Symbol counter - compare match 1 interrupt */ -+#define SCNT_CMP1_vect _VECTOR(65) -+#define SCNT_CMP1_vect_num 65 -+ -+/* Symbol counter - compare match 2 interrupt */ -+#define SCNT_CMP2_vect _VECTOR(66) -+#define SCNT_CMP2_vect_num 66 -+ -+/* Symbol counter - compare match 3 interrupt */ -+#define SCNT_CMP3_vect _VECTOR(67) -+#define SCNT_CMP3_vect_num 67 -+ -+/* Symbol counter - overflow interrupt */ -+#define SCNT_OVFL_vect _VECTOR(68) -+#define SCNT_OVFL_vect_num 68 -+ -+/* Symbol counter - backoff interrupt */ -+#define SCNT_BACKOFF_vect _VECTOR(69) -+#define SCNT_BACKOFF_vect_num 69 -+ -+/* AES engine ready interrupt */ -+#define AES_READY_vect _VECTOR(70) -+#define AES_READY_vect_num 70 -+ -+/* Battery monitor indicates supply voltage below threshold */ -+#define BAT_LOW_vect _VECTOR(71) -+#define BAT_LOW_vect_num 71 -+ -+/* TRX24 TX start interrupt */ -+#define TRX24_TX_START_vect _VECTOR(72) -+#define TRX24_TX_START_vect_num 72 -+ -+/* Address match interrupt of address filter 0 */ -+#define TRX24_AMI0_vect _VECTOR(73) -+#define TRX24_AMI0_vect_num 73 -+ -+/* Address match interrupt of address filter 1 */ -+#define TRX24_AMI1_vect _VECTOR(74) -+#define TRX24_AMI1_vect_num 74 -+ -+/* Address match interrupt of address filter 2 */ -+#define TRX24_AMI2_vect _VECTOR(75) -+#define TRX24_AMI2_vect_num 75 -+ -+/* Address match interrupt of address filter 3 */ -+#define TRX24_AMI3_vect _VECTOR(76) -+#define TRX24_AMI3_vect_num 76 -+ -+#define _VECTORS_SIZE 308 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 256 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0xFFFF -+#define RAMSTART 0x0200 -+#define RAMSIZE 8192 -+#define RAMEND 0x21FF -+#define E2START 0 -+#define E2SIZE 2048 -+#define E2PAGESIZE 8 -+#define E2END 0x07FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_CKSEL_SUT0 (unsigned char)~_BV(0) -+#define FUSE_CKSEL_SUT1 (unsigned char)~_BV(1) -+#define FUSE_CKSEL_SUT2 (unsigned char)~_BV(2) -+#define FUSE_CKSEL_SUT3 (unsigned char)~_BV(3) -+#define FUSE_CKSEL_SUT4 (unsigned char)~_BV(4) -+#define FUSE_CKSEL_SUT5 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_JTAGEN (unsigned char)~_BV(6) -+#define FUSE_OCDEN (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0xA6 -+#define SIGNATURE_2 0x03 -+ -+ -+#endif /* #ifdef _AVR_ATMEGA644RFR2_H_INCLUDED */ -+ +@@ -0,0 +1,2534 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATMEGA644RFR2_H_INCLUDED ++#define _AVR_ATMEGA644RFR2_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom644rfr2.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDRA7 7 ++#define DDRA6 6 ++#define DDRA5 5 ++#define DDRA4 4 ++#define DDRA3 3 ++#define DDRA2 2 ++#define DDRA1 1 ++#define DDRA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDRC7 7 ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC7 7 ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDRE7 7 ++#define DDRE6 6 ++#define DDRE5 5 ++#define DDRE4 4 ++#define DDRE3 3 ++#define DDRE2 2 ++#define DDRE1 1 ++#define DDRE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE7 7 ++#define PORTE6 6 ++#define PORTE5 5 ++#define PORTE4 4 ++#define PORTE3 3 ++#define PORTE2 2 ++#define PORTE1 1 ++#define PORTE0 0 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDRF7 7 ++#define DDRF6 6 ++#define DDRF5 5 ++#define DDRF4 4 ++#define DDRF3 3 ++#define DDRF2 2 ++#define DDRF1 1 ++#define DDRF0 0 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PORTF7 7 ++#define PORTF6 6 ++#define PORTF5 5 ++#define PORTF4 4 ++#define PORTF3 3 ++#define PORTF2 2 ++#define PORTF1 1 ++#define PORTF0 0 ++ ++#define PING _SFR_IO8(0x12) ++#define PING7 7 ++#define PING6 6 ++#define PING5 5 ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++#define DDRG _SFR_IO8(0x13) ++#define DDRG7 7 ++#define DDRG6 6 ++#define DDRG5 5 ++#define DDRG4 4 ++#define DDRG3 3 ++#define DDRG2 2 ++#define DDRG1 1 ++#define DDRG0 0 ++ ++#define PORTG _SFR_IO8(0x14) ++#define PORTG7 7 ++#define PORTG6 6 ++#define PORTG5 5 ++#define PORTG4 4 ++#define PORTG3 3 ++#define PORTG2 2 ++#define PORTG1 1 ++#define PORTG0 0 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++#define Res0 3 ++#define Res1 4 ++#define Res2 5 ++#define Res3 6 ++#define Res4 7 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define OCF1C 3 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++#define TIFR3 _SFR_IO8(0x18) ++#define TOV3 0 ++#define OCF3A 1 ++#define OCF3B 2 ++#define OCF3C 3 ++#define ICF3 5 ++ ++#define TIFR4 _SFR_IO8(0x19) ++#define TOV4 0 ++#define OCF4A 1 ++#define OCF4B 2 ++#define OCF4C 3 ++#define ICF4 5 ++ ++#define TIFR5 _SFR_IO8(0x1A) ++#define TOV5 0 ++#define OCF5A 1 ++#define OCF5B 2 ++#define OCF5C 3 ++#define ICF5 5 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++#define INTF4 4 ++#define INTF5 5 ++#define INTF6 6 ++#define INTF7 7 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++#define INT3 3 ++#define INT4 4 ++#define INT5 5 ++#define INT6 6 ++#define INT7 7 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define PSRASY 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++ ++#define OCR0A _SFR_IO8(0x27) ++ ++#define OCR0B _SFR_IO8(0x28) ++ ++/* Reserved [0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCDR7 7 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define JTRF 4 ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define JTD 7 ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDE 3 ++#define WDCE 4 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62] */ ++ ++#define PRR2 _SFR_MEM8(0x63) ++#define PRRAM0 0 ++#define PRRAM1 1 ++#define PRRAM2 2 ++#define PRRAM3 3 ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRPGA 4 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++#define PRR1 _SFR_MEM8(0x65) ++#define PRUSART1 0 ++#define PRTIM3 3 ++#define PRTIM4 4 ++#define PRTIM5 5 ++#define PRTRX24 6 ++#define Res 7 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define BGCR _SFR_MEM8(0x67) ++#define BGCAL0 0 ++#define BGCAL1 1 ++#define BGCAL2 2 ++#define BGCAL_FINE0 3 ++#define BGCAL_FINE1 4 ++#define BGCAL_FINE2 5 ++#define BGCAL_FINE3 6 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++#define EICRB _SFR_MEM8(0x6A) ++#define ISC40 0 ++#define ISC41 1 ++#define ISC50 2 ++#define ISC51 3 ++#define ISC60 4 ++#define ISC61 5 ++#define ISC70 6 ++#define ISC71 7 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define OCIE1C 3 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++#define TIMSK3 _SFR_MEM8(0x71) ++#define TOIE3 0 ++#define OCIE3A 1 ++#define OCIE3B 2 ++#define OCIE3C 3 ++#define ICIE3 5 ++ ++#define TIMSK4 _SFR_MEM8(0x72) ++#define TOIE4 0 ++#define OCIE4A 1 ++#define OCIE4B 2 ++#define OCIE4C 3 ++#define ICIE4 5 ++ ++#define TIMSK5 _SFR_MEM8(0x73) ++#define TOIE5 0 ++#define OCIE5A 1 ++#define OCIE5B 2 ++#define OCIE5C 3 ++#define ICIE5 5 ++ ++/* Reserved [0x74] */ ++ ++#define NEMCR _SFR_MEM8(0x75) ++#define AEAM0 4 ++#define AEAM1 5 ++#define ENEAM 6 ++ ++/* Reserved [0x76] */ ++ ++#define ADCSRC _SFR_MEM8(0x77) ++#define ADSUT0 0 ++#define ADSUT1 1 ++#define ADSUT2 2 ++#define ADSUT3 3 ++#define ADSUT4 4 ++#define ADTHT0 6 ++#define ADTHT1 7 ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ACME 6 ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define MUX5 3 ++#define ACCH 4 ++#define REFOK 5 ++#define AVDDOK 7 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR2 _SFR_MEM8(0x7D) ++#define ADC8D 0 ++#define ADC9D 1 ++#define ADC10D 2 ++#define ADC11D 3 ++#define ADC12D 4 ++#define ADC13D 5 ++#define ADC14D 6 ++#define ADC15D 7 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1C0 2 ++#define COM1C1 3 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1C 5 ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Combine OCR1CL and OCR1CH */ ++#define OCR1C _SFR_MEM16(0x8C) ++ ++#define OCR1CL _SFR_MEM8(0x8C) ++#define OCR1CH _SFR_MEM8(0x8D) ++ ++/* Reserved [0x8E..0x8F] */ ++ ++#define TCCR3A _SFR_MEM8(0x90) ++#define WGM30 0 ++#define WGM31 1 ++#define COM3C0 2 ++#define COM3C1 3 ++#define COM3B0 4 ++#define COM3B1 5 ++#define COM3A0 6 ++#define COM3A1 7 ++ ++#define TCCR3B _SFR_MEM8(0x91) ++#define CS30 0 ++#define CS31 1 ++#define CS32 2 ++#define WGM32 3 ++#define WGM33 4 ++#define ICES3 6 ++#define ICNC3 7 ++ ++#define TCCR3C _SFR_MEM8(0x92) ++#define FOC3C 5 ++#define FOC3B 6 ++#define FOC3A 7 ++ ++/* Reserved [0x93] */ ++ ++/* Combine TCNT3L and TCNT3H */ ++#define TCNT3 _SFR_MEM16(0x94) ++ ++#define TCNT3L _SFR_MEM8(0x94) ++#define TCNT3H _SFR_MEM8(0x95) ++ ++/* Combine ICR3L and ICR3H */ ++#define ICR3 _SFR_MEM16(0x96) ++ ++#define ICR3L _SFR_MEM8(0x96) ++#define ICR3H _SFR_MEM8(0x97) ++ ++/* Combine OCR3AL and OCR3AH */ ++#define OCR3A _SFR_MEM16(0x98) ++ ++#define OCR3AL _SFR_MEM8(0x98) ++#define OCR3AH _SFR_MEM8(0x99) ++ ++/* Combine OCR3BL and OCR3BH */ ++#define OCR3B _SFR_MEM16(0x9A) ++ ++#define OCR3BL _SFR_MEM8(0x9A) ++#define OCR3BH _SFR_MEM8(0x9B) ++ ++/* Combine OCR3CL and OCR3CH */ ++#define OCR3C _SFR_MEM16(0x9C) ++ ++#define OCR3CL _SFR_MEM8(0x9C) ++#define OCR3CH _SFR_MEM8(0x9D) ++ ++/* Reserved [0x9E..0x9F] */ ++ ++#define TCCR4A _SFR_MEM8(0xA0) ++#define WGM40 0 ++#define WGM41 1 ++#define COM4C0 2 ++#define COM4C1 3 ++#define COM4B0 4 ++#define COM4B1 5 ++#define COM4A0 6 ++#define COM4A1 7 ++ ++#define TCCR4B _SFR_MEM8(0xA1) ++#define CS40 0 ++#define CS41 1 ++#define CS42 2 ++#define WGM42 3 ++#define WGM43 4 ++#define ICES4 6 ++#define ICNC4 7 ++ ++#define TCCR4C _SFR_MEM8(0xA2) ++#define FOC4C 5 ++#define FOC4B 6 ++#define FOC4A 7 ++ ++/* Reserved [0xA3] */ ++ ++/* Combine TCNT4L and TCNT4H */ ++#define TCNT4 _SFR_MEM16(0xA4) ++ ++#define TCNT4L _SFR_MEM8(0xA4) ++#define TCNT4H _SFR_MEM8(0xA5) ++ ++/* Combine ICR4L and ICR4H */ ++#define ICR4 _SFR_MEM16(0xA6) ++ ++#define ICR4L _SFR_MEM8(0xA6) ++#define ICR4H _SFR_MEM8(0xA7) ++ ++/* Combine OCR4AL and OCR4AH */ ++#define OCR4A _SFR_MEM16(0xA8) ++ ++#define OCR4AL _SFR_MEM8(0xA8) ++#define OCR4AH _SFR_MEM8(0xA9) ++ ++/* Combine OCR4BL and OCR4BH */ ++#define OCR4B _SFR_MEM16(0xAA) ++ ++#define OCR4BL _SFR_MEM8(0xAA) ++#define OCR4BH _SFR_MEM8(0xAB) ++ ++/* Combine OCR4CL and OCR4CH */ ++#define OCR4C _SFR_MEM16(0xAC) ++ ++#define OCR4CL _SFR_MEM8(0xAC) ++#define OCR4CH _SFR_MEM8(0xAD) ++ ++/* Reserved [0xAE..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++#define OCR2B _SFR_MEM8(0xB4) ++ ++/* Reserved [0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++#define EXCLKAMR 7 ++ ++/* Reserved [0xB7] */ ++ ++#define TWBR _SFR_MEM8(0xB8) ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++#define IRQ_MASK1 _SFR_MEM8(0xBE) ++#define TX_START_EN 0 ++#define MAF_0_AMI_EN 1 ++#define MAF_1_AMI_EN 2 ++#define MAF_2_AMI_EN 3 ++#define MAF_3_AMI_EN 4 ++ ++#define IRQ_STATUS1 _SFR_MEM8(0xBF) ++#define TX_START 0 ++#define MAF_0_AMI 1 ++#define MAF_1_AMI 2 ++#define MAF_2_AMI 3 ++#define MAF_3_AMI 4 ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++#define UCPHA0 1 ++#define UDORD0 2 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0xC6) ++ ++/* Reserved [0xC7] */ ++ ++#define UCSR1A _SFR_MEM8(0xC8) ++#define MPCM1 0 ++#define U2X1 1 ++#define UPE1 2 ++#define DOR1 3 ++#define FE1 4 ++#define UDRE1 5 ++#define TXC1 6 ++#define RXC1 7 ++ ++#define UCSR1B _SFR_MEM8(0xC9) ++#define TXB81 0 ++#define RXB81 1 ++#define UCSZ12 2 ++#define TXEN1 3 ++#define RXEN1 4 ++#define UDRIE1 5 ++#define TXCIE1 6 ++#define RXCIE1 7 ++ ++#define UCSR1C _SFR_MEM8(0xCA) ++#define UCPOL1 0 ++#define UCSZ10 1 ++#define UCSZ11 2 ++#define USBS1 3 ++#define UPM10 4 ++#define UPM11 5 ++#define UMSEL10 6 ++#define UMSEL11 7 ++#define UCPHA1 1 ++#define UDORD1 2 ++ ++/* Reserved [0xCB] */ ++ ++/* Combine UBRR1L and UBRR1H */ ++#define UBRR1 _SFR_MEM16(0xCC) ++ ++#define UBRR1L _SFR_MEM8(0xCC) ++#define UBRR1H _SFR_MEM8(0xCD) ++ ++#define UDR1 _SFR_MEM8(0xCE) ++ ++/* Reserved [0xCF..0xD6] */ ++ ++#define SCRSTRLL _SFR_MEM8(0xD7) ++#define SCRSTRLL0 0 ++#define SCRSTRLL1 1 ++#define SCRSTRLL2 2 ++#define SCRSTRLL3 3 ++#define SCRSTRLL4 4 ++#define SCRSTRLL5 5 ++#define SCRSTRLL6 6 ++#define SCRSTRLL7 7 ++ ++#define SCRSTRLH _SFR_MEM8(0xD8) ++#define SCRSTRLH0 0 ++#define SCRSTRLH1 1 ++#define SCRSTRLH2 2 ++#define SCRSTRLH3 3 ++#define SCRSTRLH4 4 ++#define SCRSTRLH5 5 ++#define SCRSTRLH6 6 ++#define SCRSTRLH7 7 ++ ++#define SCRSTRHL _SFR_MEM8(0xD9) ++#define SCRSTRHL0 0 ++#define SCRSTRHL1 1 ++#define SCRSTRHL2 2 ++#define SCRSTRHL3 3 ++#define SCRSTRHL4 4 ++#define SCRSTRHL5 5 ++#define SCRSTRHL6 6 ++#define SCRSTRHL7 7 ++ ++#define SCRSTRHH _SFR_MEM8(0xDA) ++#define SCRSTRHH0 0 ++#define SCRSTRHH1 1 ++#define SCRSTRHH2 2 ++#define SCRSTRHH3 3 ++#define SCRSTRHH4 4 ++#define SCRSTRHH5 5 ++#define SCRSTRHH6 6 ++#define SCRSTRHH7 7 ++ ++#define SCCSR _SFR_MEM8(0xDB) ++#define SCCS10 0 ++#define SCCS11 1 ++#define SCCS20 2 ++#define SCCS21 3 ++#define SCCS30 4 ++#define SCCS31 5 ++ ++#define SCCR0 _SFR_MEM8(0xDC) ++#define SCCMP1 0 ++#define SCCMP2 1 ++#define SCCMP3 2 ++#define SCTSE 3 ++#define SCCKSEL 4 ++#define SCEN 5 ++#define SCMBTS 6 ++#define SCRES 7 ++ ++#define SCCR1 _SFR_MEM8(0xDD) ++#define SCENBO 0 ++#define SCEECLK 1 ++#define SCCKDIV0 2 ++#define SCCKDIV1 3 ++#define SCCKDIV2 4 ++#define SCBTSM 5 ++#define Res5 6 ++#define Res6 7 ++ ++#define SCSR _SFR_MEM8(0xDE) ++#define SCBSY 0 ++ ++#define SCIRQM _SFR_MEM8(0xDF) ++#define IRQMCP1 0 ++#define IRQMCP2 1 ++#define IRQMCP3 2 ++#define IRQMOF 3 ++#define IRQMBO 4 ++ ++#define SCIRQS _SFR_MEM8(0xE0) ++#define IRQSCP1 0 ++#define IRQSCP2 1 ++#define IRQSCP3 2 ++#define IRQSOF 3 ++#define IRQSBO 4 ++ ++#define SCCNTLL _SFR_MEM8(0xE1) ++#define SCCNTLL0 0 ++#define SCCNTLL1 1 ++#define SCCNTLL2 2 ++#define SCCNTLL3 3 ++#define SCCNTLL4 4 ++#define SCCNTLL5 5 ++#define SCCNTLL6 6 ++#define SCCNTLL7 7 ++ ++#define SCCNTLH _SFR_MEM8(0xE2) ++#define SCCNTLH0 0 ++#define SCCNTLH1 1 ++#define SCCNTLH2 2 ++#define SCCNTLH3 3 ++#define SCCNTLH4 4 ++#define SCCNTLH5 5 ++#define SCCNTLH6 6 ++#define SCCNTLH7 7 ++ ++#define SCCNTHL _SFR_MEM8(0xE3) ++#define SCCNTHL0 0 ++#define SCCNTHL1 1 ++#define SCCNTHL2 2 ++#define SCCNTHL3 3 ++#define SCCNTHL4 4 ++#define SCCNTHL5 5 ++#define SCCNTHL6 6 ++#define SCCNTHL7 7 ++ ++#define SCCNTHH _SFR_MEM8(0xE4) ++#define SCCNTHH0 0 ++#define SCCNTHH1 1 ++#define SCCNTHH2 2 ++#define SCCNTHH3 3 ++#define SCCNTHH4 4 ++#define SCCNTHH5 5 ++#define SCCNTHH6 6 ++#define SCCNTHH7 7 ++ ++#define SCBTSRLL _SFR_MEM8(0xE5) ++#define SCBTSRLL0 0 ++#define SCBTSRLL1 1 ++#define SCBTSRLL2 2 ++#define SCBTSRLL3 3 ++#define SCBTSRLL4 4 ++#define SCBTSRLL5 5 ++#define SCBTSRLL6 6 ++#define SCBTSRLL7 7 ++ ++#define SCBTSRLH _SFR_MEM8(0xE6) ++#define SCBTSRLH0 0 ++#define SCBTSRLH1 1 ++#define SCBTSRLH2 2 ++#define SCBTSRLH3 3 ++#define SCBTSRLH4 4 ++#define SCBTSRLH5 5 ++#define SCBTSRLH6 6 ++#define SCBTSRLH7 7 ++ ++#define SCBTSRHL _SFR_MEM8(0xE7) ++#define SCBTSRHL0 0 ++#define SCBTSRHL1 1 ++#define SCBTSRHL2 2 ++#define SCBTSRHL3 3 ++#define SCBTSRHL4 4 ++#define SCBTSRHL5 5 ++#define SCBTSRHL6 6 ++#define SCBTSRHL7 7 ++ ++#define SCBTSRHH _SFR_MEM8(0xE8) ++#define SCBTSRHH0 0 ++#define SCBTSRHH1 1 ++#define SCBTSRHH2 2 ++#define SCBTSRHH3 3 ++#define SCBTSRHH4 4 ++#define SCBTSRHH5 5 ++#define SCBTSRHH6 6 ++#define SCBTSRHH7 7 ++ ++#define SCTSRLL _SFR_MEM8(0xE9) ++#define SCTSRLL0 0 ++#define SCTSRLL1 1 ++#define SCTSRLL2 2 ++#define SCTSRLL3 3 ++#define SCTSRLL4 4 ++#define SCTSRLL5 5 ++#define SCTSRLL6 6 ++#define SCTSRLL7 7 ++ ++#define SCTSRLH _SFR_MEM8(0xEA) ++#define SCTSRLH0 0 ++#define SCTSRLH1 1 ++#define SCTSRLH2 2 ++#define SCTSRLH3 3 ++#define SCTSRLH4 4 ++#define SCTSRLH5 5 ++#define SCTSRLH6 6 ++#define SCTSRLH7 7 ++ ++#define SCTSRHL _SFR_MEM8(0xEB) ++#define SCTSRHL0 0 ++#define SCTSRHL1 1 ++#define SCTSRHL2 2 ++#define SCTSRHL3 3 ++#define SCTSRHL4 4 ++#define SCTSRHL5 5 ++#define SCTSRHL6 6 ++#define SCTSRHL7 7 ++ ++#define SCTSRHH _SFR_MEM8(0xEC) ++#define SCTSRHH0 0 ++#define SCTSRHH1 1 ++#define SCTSRHH2 2 ++#define SCTSRHH3 3 ++#define SCTSRHH4 4 ++#define SCTSRHH5 5 ++#define SCTSRHH6 6 ++#define SCTSRHH7 7 ++ ++#define SCOCR3LL _SFR_MEM8(0xED) ++#define SCOCR3LL0 0 ++#define SCOCR3LL1 1 ++#define SCOCR3LL2 2 ++#define SCOCR3LL3 3 ++#define SCOCR3LL4 4 ++#define SCOCR3LL5 5 ++#define SCOCR3LL6 6 ++#define SCOCR3LL7 7 ++ ++#define SCOCR3LH _SFR_MEM8(0xEE) ++#define SCOCR3LH0 0 ++#define SCOCR3LH1 1 ++#define SCOCR3LH2 2 ++#define SCOCR3LH3 3 ++#define SCOCR3LH4 4 ++#define SCOCR3LH5 5 ++#define SCOCR3LH6 6 ++#define SCOCR3LH7 7 ++ ++#define SCOCR3HL _SFR_MEM8(0xEF) ++#define SCOCR3HL0 0 ++#define SCOCR3HL1 1 ++#define SCOCR3HL2 2 ++#define SCOCR3HL3 3 ++#define SCOCR3HL4 4 ++#define SCOCR3HL5 5 ++#define SCOCR3HL6 6 ++#define SCOCR3HL7 7 ++ ++#define SCOCR3HH _SFR_MEM8(0xF0) ++#define SCOCR3HH0 0 ++#define SCOCR3HH1 1 ++#define SCOCR3HH2 2 ++#define SCOCR3HH3 3 ++#define SCOCR3HH4 4 ++#define SCOCR3HH5 5 ++#define SCOCR3HH6 6 ++#define SCOCR3HH7 7 ++ ++#define SCOCR2LL _SFR_MEM8(0xF1) ++#define SCOCR2LL0 0 ++#define SCOCR2LL1 1 ++#define SCOCR2LL2 2 ++#define SCOCR2LL3 3 ++#define SCOCR2LL4 4 ++#define SCOCR2LL5 5 ++#define SCOCR2LL6 6 ++#define SCOCR2LL7 7 ++ ++#define SCOCR2LH _SFR_MEM8(0xF2) ++#define SCOCR2LH0 0 ++#define SCOCR2LH1 1 ++#define SCOCR2LH2 2 ++#define SCOCR2LH3 3 ++#define SCOCR2LH4 4 ++#define SCOCR2LH5 5 ++#define SCOCR2LH6 6 ++#define SCOCR2LH7 7 ++ ++#define SCOCR2HL _SFR_MEM8(0xF3) ++#define SCOCR2HL0 0 ++#define SCOCR2HL1 1 ++#define SCOCR2HL2 2 ++#define SCOCR2HL3 3 ++#define SCOCR2HL4 4 ++#define SCOCR2HL5 5 ++#define SCOCR2HL6 6 ++#define SCOCR2HL7 7 ++ ++#define SCOCR2HH _SFR_MEM8(0xF4) ++#define SCOCR2HH0 0 ++#define SCOCR2HH1 1 ++#define SCOCR2HH2 2 ++#define SCOCR2HH3 3 ++#define SCOCR2HH4 4 ++#define SCOCR2HH5 5 ++#define SCOCR2HH6 6 ++#define SCOCR2HH7 7 ++ ++#define SCOCR1LL _SFR_MEM8(0xF5) ++#define SCOCR1LL0 0 ++#define SCOCR1LL1 1 ++#define SCOCR1LL2 2 ++#define SCOCR1LL3 3 ++#define SCOCR1LL4 4 ++#define SCOCR1LL5 5 ++#define SCOCR1LL6 6 ++#define SCOCR1LL7 7 ++ ++#define SCOCR1LH _SFR_MEM8(0xF6) ++#define SCOCR1LH0 0 ++#define SCOCR1LH1 1 ++#define SCOCR1LH2 2 ++#define SCOCR1LH3 3 ++#define SCOCR1LH4 4 ++#define SCOCR1LH5 5 ++#define SCOCR1LH6 6 ++#define SCOCR1LH7 7 ++ ++#define SCOCR1HL _SFR_MEM8(0xF7) ++#define SCOCR1HL0 0 ++#define SCOCR1HL1 1 ++#define SCOCR1HL2 2 ++#define SCOCR1HL3 3 ++#define SCOCR1HL4 4 ++#define SCOCR1HL5 5 ++#define SCOCR1HL6 6 ++#define SCOCR1HL7 7 ++ ++#define SCOCR1HH _SFR_MEM8(0xF8) ++#define SCOCR1HH0 0 ++#define SCOCR1HH1 1 ++#define SCOCR1HH2 2 ++#define SCOCR1HH3 3 ++#define SCOCR1HH4 4 ++#define SCOCR1HH5 5 ++#define SCOCR1HH6 6 ++#define SCOCR1HH7 7 ++ ++#define SCTSTRLL _SFR_MEM8(0xF9) ++#define SCTSTRLL0 0 ++#define SCTSTRLL1 1 ++#define SCTSTRLL2 2 ++#define SCTSTRLL3 3 ++#define SCTSTRLL4 4 ++#define SCTSTRLL5 5 ++#define SCTSTRLL6 6 ++#define SCTSTRLL7 7 ++ ++#define SCTSTRLH _SFR_MEM8(0xFA) ++#define SCTSTRLH0 0 ++#define SCTSTRLH1 1 ++#define SCTSTRLH2 2 ++#define SCTSTRLH3 3 ++#define SCTSTRLH4 4 ++#define SCTSTRLH5 5 ++#define SCTSTRLH6 6 ++#define SCTSTRLH7 7 ++ ++#define SCTSTRHL _SFR_MEM8(0xFB) ++#define SCTSTRHL0 0 ++#define SCTSTRHL1 1 ++#define SCTSTRHL2 2 ++#define SCTSTRHL3 3 ++#define SCTSTRHL4 4 ++#define SCTSTRHL5 5 ++#define SCTSTRHL6 6 ++#define SCTSTRHL7 7 ++ ++#define SCTSTRHH _SFR_MEM8(0xFC) ++#define SCTSTRHH0 0 ++#define SCTSTRHH1 1 ++#define SCTSTRHH2 2 ++#define SCTSTRHH3 3 ++#define SCTSTRHH4 4 ++#define SCTSTRHH5 5 ++#define SCTSTRHH6 6 ++#define SCTSTRHH7 7 ++ ++/* Reserved [0xFD..0x10B] */ ++ ++#define MAFCR0 _SFR_MEM8(0x10C) ++#define MAF0EN 0 ++#define MAF1EN 1 ++#define MAF2EN 2 ++#define MAF3EN 3 ++ ++#define MAFCR1 _SFR_MEM8(0x10D) ++#define AACK_0_I_AM_COORD 0 ++#define AACK_0_SET_PD 1 ++#define AACK_1_I_AM_COORD 2 ++#define AACK_1_SET_PD 3 ++#define AACK_2_I_AM_COORD 4 ++#define AACK_2_SET_PD 5 ++#define AACK_3_I_AM_COORD 6 ++#define AACK_3_SET_PD 7 ++ ++#define MAFSA0L _SFR_MEM8(0x10E) ++#define MAFSA0L0 0 ++#define MAFSA0L1 1 ++#define MAFSA0L2 2 ++#define MAFSA0L3 3 ++#define MAFSA0L4 4 ++#define MAFSA0L5 5 ++#define MAFSA0L6 6 ++#define MAFSA0L7 7 ++ ++#define MAFSA0H _SFR_MEM8(0x10F) ++#define MAFSA0H0 0 ++#define MAFSA0H1 1 ++#define MAFSA0H2 2 ++#define MAFSA0H3 3 ++#define MAFSA0H4 4 ++#define MAFSA0H5 5 ++#define MAFSA0H6 6 ++#define MAFSA0H7 7 ++ ++#define MAFPA0L _SFR_MEM8(0x110) ++#define MAFPA0L0 0 ++#define MAFPA0L1 1 ++#define MAFPA0L2 2 ++#define MAFPA0L3 3 ++#define MAFPA0L4 4 ++#define MAFPA0L5 5 ++#define MAFPA0L6 6 ++#define MAFPA0L7 7 ++ ++#define MAFPA0H _SFR_MEM8(0x111) ++#define MAFPA0H0 0 ++#define MAFPA0H1 1 ++#define MAFPA0H2 2 ++#define MAFPA0H3 3 ++#define MAFPA0H4 4 ++#define MAFPA0H5 5 ++#define MAFPA0H6 6 ++#define MAFPA0H7 7 ++ ++#define MAFSA1L _SFR_MEM8(0x112) ++#define MAFSA1L0 0 ++#define MAFSA1L1 1 ++#define MAFSA1L2 2 ++#define MAFSA1L3 3 ++#define MAFSA1L4 4 ++#define MAFSA1L5 5 ++#define MAFSA1L6 6 ++#define MAFSA1L7 7 ++ ++#define MAFSA1H _SFR_MEM8(0x113) ++#define MAFSA1H0 0 ++#define MAFSA1H1 1 ++#define MAFSA1H2 2 ++#define MAFSA1H3 3 ++#define MAFSA1H4 4 ++#define MAFSA1H5 5 ++#define MAFSA1H6 6 ++#define MAFSA1H7 7 ++ ++#define MAFPA1L _SFR_MEM8(0x114) ++#define MAFPA1L0 0 ++#define MAFPA1L1 1 ++#define MAFPA1L2 2 ++#define MAFPA1L3 3 ++#define MAFPA1L4 4 ++#define MAFPA1L5 5 ++#define MAFPA1L6 6 ++#define MAFPA1L7 7 ++ ++#define MAFPA1H _SFR_MEM8(0x115) ++#define MAFPA1H0 0 ++#define MAFPA1H1 1 ++#define MAFPA1H2 2 ++#define MAFPA1H3 3 ++#define MAFPA1H4 4 ++#define MAFPA1H5 5 ++#define MAFPA1H6 6 ++#define MAFPA1H7 7 ++ ++#define MAFSA2L _SFR_MEM8(0x116) ++#define MAFSA2L0 0 ++#define MAFSA2L1 1 ++#define MAFSA2L2 2 ++#define MAFSA2L3 3 ++#define MAFSA2L4 4 ++#define MAFSA2L5 5 ++#define MAFSA2L6 6 ++#define MAFSA2L7 7 ++ ++#define MAFSA2H _SFR_MEM8(0x117) ++#define MAFSA2H0 0 ++#define MAFSA2H1 1 ++#define MAFSA2H2 2 ++#define MAFSA2H3 3 ++#define MAFSA2H4 4 ++#define MAFSA2H5 5 ++#define MAFSA2H6 6 ++#define MAFSA2H7 7 ++ ++#define MAFPA2L _SFR_MEM8(0x118) ++#define MAFPA2L0 0 ++#define MAFPA2L1 1 ++#define MAFPA2L2 2 ++#define MAFPA2L3 3 ++#define MAFPA2L4 4 ++#define MAFPA2L5 5 ++#define MAFPA2L6 6 ++#define MAFPA2L7 7 ++ ++#define MAFPA2H _SFR_MEM8(0x119) ++#define MAFPA2H0 0 ++#define MAFPA2H1 1 ++#define MAFPA2H2 2 ++#define MAFPA2H3 3 ++#define MAFPA2H4 4 ++#define MAFPA2H5 5 ++#define MAFPA2H6 6 ++#define MAFPA2H7 7 ++ ++#define MAFSA3L _SFR_MEM8(0x11A) ++#define MAFSA3L0 0 ++#define MAFSA3L1 1 ++#define MAFSA3L2 2 ++#define MAFSA3L3 3 ++#define MAFSA3L4 4 ++#define MAFSA3L5 5 ++#define MAFSA3L6 6 ++#define MAFSA3L7 7 ++ ++#define MAFSA3H _SFR_MEM8(0x11B) ++#define MAFSA3H0 0 ++#define MAFSA3H1 1 ++#define MAFSA3H2 2 ++#define MAFSA3H3 3 ++#define MAFSA3H4 4 ++#define MAFSA3H5 5 ++#define MAFSA3H6 6 ++#define MAFSA3H7 7 ++ ++#define MAFPA3L _SFR_MEM8(0x11C) ++#define MAFPA3L0 0 ++#define MAFPA3L1 1 ++#define MAFPA3L2 2 ++#define MAFPA3L3 3 ++#define MAFPA3L4 4 ++#define MAFPA3L5 5 ++#define MAFPA3L6 6 ++#define MAFPA3L7 7 ++ ++#define MAFPA3H _SFR_MEM8(0x11D) ++#define MAFPA3H0 0 ++#define MAFPA3H1 1 ++#define MAFPA3H2 2 ++#define MAFPA3H3 3 ++#define MAFPA3H4 4 ++#define MAFPA3H5 5 ++#define MAFPA3H6 6 ++#define MAFPA3H7 7 ++ ++/* Reserved [0x11E..0x11F] */ ++ ++#define TCCR5A _SFR_MEM8(0x120) ++#define WGM50 0 ++#define WGM51 1 ++#define COM5C0 2 ++#define COM5C1 3 ++#define COM5B0 4 ++#define COM5B1 5 ++#define COM5A0 6 ++#define COM5A1 7 ++ ++#define TCCR5B _SFR_MEM8(0x121) ++#define CS50 0 ++#define CS51 1 ++#define CS52 2 ++#define WGM52 3 ++#define WGM53 4 ++#define ICES5 6 ++#define ICNC5 7 ++ ++#define TCCR5C _SFR_MEM8(0x122) ++#define FOC5C 5 ++#define FOC5B 6 ++#define FOC5A 7 ++ ++/* Reserved [0x123] */ ++ ++/* Combine TCNT5L and TCNT5H */ ++#define TCNT5 _SFR_MEM16(0x124) ++ ++#define TCNT5L _SFR_MEM8(0x124) ++#define TCNT5H _SFR_MEM8(0x125) ++ ++/* Combine ICR5L and ICR5H */ ++#define ICR5 _SFR_MEM16(0x126) ++ ++#define ICR5L _SFR_MEM8(0x126) ++#define ICR5H _SFR_MEM8(0x127) ++ ++/* Combine OCR5AL and OCR5AH */ ++#define OCR5A _SFR_MEM16(0x128) ++ ++#define OCR5AL _SFR_MEM8(0x128) ++#define OCR5AH _SFR_MEM8(0x129) ++ ++/* Combine OCR5BL and OCR5BH */ ++#define OCR5B _SFR_MEM16(0x12A) ++ ++#define OCR5BL _SFR_MEM8(0x12A) ++#define OCR5BH _SFR_MEM8(0x12B) ++ ++/* Combine OCR5CL and OCR5CH */ ++#define OCR5C _SFR_MEM16(0x12C) ++ ++#define OCR5CL _SFR_MEM8(0x12C) ++#define OCR5CH _SFR_MEM8(0x12D) ++ ++/* Reserved [0x12E] */ ++ ++#define LLCR _SFR_MEM8(0x12F) ++#define LLENCAL 0 ++#define LLSHORT 1 ++#define LLTCO 2 ++#define LLCAL 3 ++#define LLCOMP 4 ++#define LLDONE 5 ++ ++#define LLDRL _SFR_MEM8(0x130) ++#define LLDRL0 0 ++#define LLDRL1 1 ++#define LLDRL2 2 ++#define LLDRL3 3 ++ ++#define LLDRH _SFR_MEM8(0x131) ++#define LLDRH0 0 ++#define LLDRH1 1 ++#define LLDRH2 2 ++#define LLDRH3 3 ++#define LLDRH4 4 ++ ++#define DRTRAM3 _SFR_MEM8(0x132) ++#define ENDRT 4 ++#define DRTSWOK 5 ++ ++#define DRTRAM2 _SFR_MEM8(0x133) ++ ++#define DRTRAM1 _SFR_MEM8(0x134) ++ ++#define DRTRAM0 _SFR_MEM8(0x135) ++ ++#define DPDS0 _SFR_MEM8(0x136) ++#define PBDRV0 0 ++#define PBDRV1 1 ++#define PDDRV0 2 ++#define PDDRV1 3 ++#define PEDRV0 4 ++#define PEDRV1 5 ++#define PFDRV0 6 ++#define PFDRV1 7 ++ ++#define DPDS1 _SFR_MEM8(0x137) ++#define PGDRV0 0 ++#define PGDRV1 1 ++ ++#define PARCR _SFR_MEM8(0x138) ++#define PARUFI 0 ++#define PARDFI 1 ++#define PALTU0 2 ++#define PALTU1 3 ++#define PALTU2 4 ++#define PALTD0 5 ++#define PALTD1 6 ++#define PALTD2 7 ++ ++#define TRXPR _SFR_MEM8(0x139) ++#define TRXRST 0 ++#define SLPTR 1 ++ ++/* Reserved [0x13A..0x13B] */ ++ ++#define AES_CTRL _SFR_MEM8(0x13C) ++#define AES_IM 2 ++#define AES_DIR 3 ++#define AES_MODE 5 ++#define AES_REQUEST 7 ++ ++#define AES_STATUS _SFR_MEM8(0x13D) ++#define AES_DONE 0 ++#define AES_ER 7 ++ ++#define AES_STATE _SFR_MEM8(0x13E) ++#define AES_STATE0 0 ++#define AES_STATE1 1 ++#define AES_STATE2 2 ++#define AES_STATE3 3 ++#define AES_STATE4 4 ++#define AES_STATE5 5 ++#define AES_STATE6 6 ++#define AES_STATE7 7 ++ ++#define AES_KEY _SFR_MEM8(0x13F) ++#define AES_KEY0 0 ++#define AES_KEY1 1 ++#define AES_KEY2 2 ++#define AES_KEY3 3 ++#define AES_KEY4 4 ++#define AES_KEY5 5 ++#define AES_KEY6 6 ++#define AES_KEY7 7 ++ ++/* Reserved [0x140] */ ++ ++#define TRX_STATUS _SFR_MEM8(0x141) ++#define TRX_STATUS0 0 ++#define TRX_STATUS1 1 ++#define TRX_STATUS2 2 ++#define TRX_STATUS3 3 ++#define TRX_STATUS4 4 ++#define TST_STATUS 5 ++#define CCA_STATUS 6 ++#define CCA_DONE 7 ++ ++#define TRX_STATE _SFR_MEM8(0x142) ++#define TRX_CMD0 0 ++#define TRX_CMD1 1 ++#define TRX_CMD2 2 ++#define TRX_CMD3 3 ++#define TRX_CMD4 4 ++#define TRAC_STATUS0 5 ++#define TRAC_STATUS1 6 ++#define TRAC_STATUS2 7 ++ ++#define TRX_CTRL_0 _SFR_MEM8(0x143) ++#define PMU_IF_INV 4 ++#define PMU_START 5 ++#define PMU_EN 6 ++#define Res7 7 ++ ++#define TRX_CTRL_1 _SFR_MEM8(0x144) ++#define PLL_TX_FLT 4 ++#define TX_AUTO_CRC_ON 5 ++#define IRQ_2_EXT_EN 6 ++#define PA_EXT_EN 7 ++ ++#define PHY_TX_PWR _SFR_MEM8(0x145) ++#define TX_PWR0 0 ++#define TX_PWR1 1 ++#define TX_PWR2 2 ++#define TX_PWR3 3 ++ ++#define PHY_RSSI _SFR_MEM8(0x146) ++#define RSSI0 0 ++#define RSSI1 1 ++#define RSSI2 2 ++#define RSSI3 3 ++#define RSSI4 4 ++#define RND_VALUE0 5 ++#define RND_VALUE1 6 ++#define RX_CRC_VALID 7 ++ ++#define PHY_ED_LEVEL _SFR_MEM8(0x147) ++#define ED_LEVEL0 0 ++#define ED_LEVEL1 1 ++#define ED_LEVEL2 2 ++#define ED_LEVEL3 3 ++#define ED_LEVEL4 4 ++#define ED_LEVEL5 5 ++#define ED_LEVEL6 6 ++#define ED_LEVEL7 7 ++ ++#define PHY_CC_CCA _SFR_MEM8(0x148) ++#define CHANNEL0 0 ++#define CHANNEL1 1 ++#define CHANNEL2 2 ++#define CHANNEL3 3 ++#define CHANNEL4 4 ++#define CCA_MODE0 5 ++#define CCA_MODE1 6 ++#define CCA_REQUEST 7 ++ ++#define CCA_THRES _SFR_MEM8(0x149) ++#define CCA_ED_THRES0 0 ++#define CCA_ED_THRES1 1 ++#define CCA_ED_THRES2 2 ++#define CCA_ED_THRES3 3 ++#define CCA_CS_THRES0 4 ++#define CCA_CS_THRES1 5 ++#define CCA_CS_THRES2 6 ++#define CCA_CS_THRES3 7 ++ ++#define RX_CTRL _SFR_MEM8(0x14A) ++#define PDT_THRES0 0 ++#define PDT_THRES1 1 ++#define PDT_THRES2 2 ++#define PDT_THRES3 3 ++ ++#define SFD_VALUE _SFR_MEM8(0x14B) ++#define SFD_VALUE0 0 ++#define SFD_VALUE1 1 ++#define SFD_VALUE2 2 ++#define SFD_VALUE3 3 ++#define SFD_VALUE4 4 ++#define SFD_VALUE5 5 ++#define SFD_VALUE6 6 ++#define SFD_VALUE7 7 ++ ++#define TRX_CTRL_2 _SFR_MEM8(0x14C) ++#define OQPSK_DATA_RATE0 0 ++#define OQPSK_DATA_RATE1 1 ++#define RX_SAFE_MODE 7 ++ ++#define ANT_DIV _SFR_MEM8(0x14D) ++#define ANT_CTRL0 0 ++#define ANT_CTRL1 1 ++#define ANT_EXT_SW_EN 2 ++#define ANT_DIV_EN 3 ++#define ANT_SEL 7 ++ ++#define IRQ_MASK _SFR_MEM8(0x14E) ++#define PLL_LOCK_EN 0 ++#define PLL_UNLOCK_EN 1 ++#define RX_START_EN 2 ++#define RX_END_EN 3 ++#define CCA_ED_DONE_EN 4 ++#define AMI_EN 5 ++#define TX_END_EN 6 ++#define AWAKE_EN 7 ++ ++#define IRQ_STATUS _SFR_MEM8(0x14F) ++#define PLL_LOCK 0 ++#define PLL_UNLOCK 1 ++#define RX_START 2 ++#define RX_END 3 ++#define CCA_ED_DONE 4 ++#define AMI 5 ++#define TX_END 6 ++#define AWAKE 7 ++ ++#define VREG_CTRL _SFR_MEM8(0x150) ++#define DVDD_OK 2 ++#define DVREG_EXT 3 ++#define AVDD_OK 6 ++#define AVREG_EXT 7 ++ ++#define BATMON _SFR_MEM8(0x151) ++#define BATMON_VTH0 0 ++#define BATMON_VTH1 1 ++#define BATMON_VTH2 2 ++#define BATMON_VTH3 3 ++#define BATMON_HR 4 ++#define BATMON_OK 5 ++#define BAT_LOW_EN 6 ++#define BAT_LOW 7 ++ ++#define XOSC_CTRL _SFR_MEM8(0x152) ++#define XTAL_TRIM0 0 ++#define XTAL_TRIM1 1 ++#define XTAL_TRIM2 2 ++#define XTAL_TRIM3 3 ++#define XTAL_MODE0 4 ++#define XTAL_MODE1 5 ++#define XTAL_MODE2 6 ++#define XTAL_MODE3 7 ++ ++#define CC_CTRL_0 _SFR_MEM8(0x153) ++#define CC_NUMBER0 0 ++#define CC_NUMBER1 1 ++#define CC_NUMBER2 2 ++#define CC_NUMBER3 3 ++#define CC_NUMBER4 4 ++#define CC_NUMBER5 5 ++#define CC_NUMBER6 6 ++#define CC_NUMBER7 7 ++ ++#define CC_CTRL_1 _SFR_MEM8(0x154) ++#define CC_BAND0 0 ++#define CC_BAND1 1 ++#define CC_BAND2 2 ++#define CC_BAND3 3 ++ ++#define RX_SYN _SFR_MEM8(0x155) ++#define RX_PDT_LEVEL0 0 ++#define RX_PDT_LEVEL1 1 ++#define RX_PDT_LEVEL2 2 ++#define RX_PDT_LEVEL3 3 ++#define RX_OVERRIDE 6 ++#define RX_PDT_DIS 7 ++ ++#define TRX_RPC _SFR_MEM8(0x156) ++#define XAH_RPC_EN 0 ++#define IPAN_RPC_EN 1 ++#define PLL_RPC_EN 3 ++#define PDT_RPC_EN 4 ++#define RX_RPC_EN 5 ++#define RX_RPC_CTRL0 6 ++#define RX_RPC_CTRL1 7 ++ ++#define XAH_CTRL_1 _SFR_MEM8(0x157) ++#define AACK_PROM_MODE 1 ++#define AACK_ACK_TIME 2 ++#define AACK_UPLD_RES_FT 4 ++#define AACK_FLTR_RES_FT 5 ++ ++#define FTN_CTRL _SFR_MEM8(0x158) ++#define FTN_START 7 ++ ++/* Reserved [0x159] */ ++ ++#define PLL_CF _SFR_MEM8(0x15A) ++#define PLL_CF_START 7 ++ ++#define PLL_DCU _SFR_MEM8(0x15B) ++#define PLL_DCU_START 7 ++ ++#define PART_NUM _SFR_MEM8(0x15C) ++#define PART_NUM0 0 ++#define PART_NUM1 1 ++#define PART_NUM2 2 ++#define PART_NUM3 3 ++#define PART_NUM4 4 ++#define PART_NUM5 5 ++#define PART_NUM6 6 ++#define PART_NUM7 7 ++ ++#define VERSION_NUM _SFR_MEM8(0x15D) ++#define VERSION_NUM0 0 ++#define VERSION_NUM1 1 ++#define VERSION_NUM2 2 ++#define VERSION_NUM3 3 ++#define VERSION_NUM4 4 ++#define VERSION_NUM5 5 ++#define VERSION_NUM6 6 ++#define VERSION_NUM7 7 ++ ++#define MAN_ID_0 _SFR_MEM8(0x15E) ++#define MAN_ID_00 0 ++#define MAN_ID_01 1 ++#define MAN_ID_02 2 ++#define MAN_ID_03 3 ++#define MAN_ID_04 4 ++#define MAN_ID_05 5 ++#define MAN_ID_06 6 ++#define MAN_ID_07 7 ++ ++#define MAN_ID_1 _SFR_MEM8(0x15F) ++#define MAN_ID_10 0 ++#define MAN_ID_11 1 ++#define MAN_ID_12 2 ++#define MAN_ID_13 3 ++#define MAN_ID_14 4 ++#define MAN_ID_15 5 ++#define MAN_ID_16 6 ++#define MAN_ID_17 7 ++ ++#define SHORT_ADDR_0 _SFR_MEM8(0x160) ++#define SHORT_ADDR_00 0 ++#define SHORT_ADDR_01 1 ++#define SHORT_ADDR_02 2 ++#define SHORT_ADDR_03 3 ++#define SHORT_ADDR_04 4 ++#define SHORT_ADDR_05 5 ++#define SHORT_ADDR_06 6 ++#define SHORT_ADDR_07 7 ++ ++#define SHORT_ADDR_1 _SFR_MEM8(0x161) ++#define SHORT_ADDR_10 0 ++#define SHORT_ADDR_11 1 ++#define SHORT_ADDR_12 2 ++#define SHORT_ADDR_13 3 ++#define SHORT_ADDR_14 4 ++#define SHORT_ADDR_15 5 ++#define SHORT_ADDR_16 6 ++#define SHORT_ADDR_17 7 ++ ++#define PAN_ID_0 _SFR_MEM8(0x162) ++#define PAN_ID_00 0 ++#define PAN_ID_01 1 ++#define PAN_ID_02 2 ++#define PAN_ID_03 3 ++#define PAN_ID_04 4 ++#define PAN_ID_05 5 ++#define PAN_ID_06 6 ++#define PAN_ID_07 7 ++ ++#define PAN_ID_1 _SFR_MEM8(0x163) ++#define PAN_ID_10 0 ++#define PAN_ID_11 1 ++#define PAN_ID_12 2 ++#define PAN_ID_13 3 ++#define PAN_ID_14 4 ++#define PAN_ID_15 5 ++#define PAN_ID_16 6 ++#define PAN_ID_17 7 ++ ++#define IEEE_ADDR_0 _SFR_MEM8(0x164) ++#define IEEE_ADDR_00 0 ++#define IEEE_ADDR_01 1 ++#define IEEE_ADDR_02 2 ++#define IEEE_ADDR_03 3 ++#define IEEE_ADDR_04 4 ++#define IEEE_ADDR_05 5 ++#define IEEE_ADDR_06 6 ++#define IEEE_ADDR_07 7 ++ ++#define IEEE_ADDR_1 _SFR_MEM8(0x165) ++#define IEEE_ADDR_10 0 ++#define IEEE_ADDR_11 1 ++#define IEEE_ADDR_12 2 ++#define IEEE_ADDR_13 3 ++#define IEEE_ADDR_14 4 ++#define IEEE_ADDR_15 5 ++#define IEEE_ADDR_16 6 ++#define IEEE_ADDR_17 7 ++ ++#define IEEE_ADDR_2 _SFR_MEM8(0x166) ++#define IEEE_ADDR_20 0 ++#define IEEE_ADDR_21 1 ++#define IEEE_ADDR_22 2 ++#define IEEE_ADDR_23 3 ++#define IEEE_ADDR_24 4 ++#define IEEE_ADDR_25 5 ++#define IEEE_ADDR_26 6 ++#define IEEE_ADDR_27 7 ++ ++#define IEEE_ADDR_3 _SFR_MEM8(0x167) ++#define IEEE_ADDR_30 0 ++#define IEEE_ADDR_31 1 ++#define IEEE_ADDR_32 2 ++#define IEEE_ADDR_33 3 ++#define IEEE_ADDR_34 4 ++#define IEEE_ADDR_35 5 ++#define IEEE_ADDR_36 6 ++#define IEEE_ADDR_37 7 ++ ++#define IEEE_ADDR_4 _SFR_MEM8(0x168) ++#define IEEE_ADDR_40 0 ++#define IEEE_ADDR_41 1 ++#define IEEE_ADDR_42 2 ++#define IEEE_ADDR_43 3 ++#define IEEE_ADDR_44 4 ++#define IEEE_ADDR_45 5 ++#define IEEE_ADDR_46 6 ++#define IEEE_ADDR_47 7 ++ ++#define IEEE_ADDR_5 _SFR_MEM8(0x169) ++#define IEEE_ADDR_50 0 ++#define IEEE_ADDR_51 1 ++#define IEEE_ADDR_52 2 ++#define IEEE_ADDR_53 3 ++#define IEEE_ADDR_54 4 ++#define IEEE_ADDR_55 5 ++#define IEEE_ADDR_56 6 ++#define IEEE_ADDR_57 7 ++ ++#define IEEE_ADDR_6 _SFR_MEM8(0x16A) ++#define IEEE_ADDR_60 0 ++#define IEEE_ADDR_61 1 ++#define IEEE_ADDR_62 2 ++#define IEEE_ADDR_63 3 ++#define IEEE_ADDR_64 4 ++#define IEEE_ADDR_65 5 ++#define IEEE_ADDR_66 6 ++#define IEEE_ADDR_67 7 ++ ++#define IEEE_ADDR_7 _SFR_MEM8(0x16B) ++#define IEEE_ADDR_70 0 ++#define IEEE_ADDR_71 1 ++#define IEEE_ADDR_72 2 ++#define IEEE_ADDR_73 3 ++#define IEEE_ADDR_74 4 ++#define IEEE_ADDR_75 5 ++#define IEEE_ADDR_76 6 ++#define IEEE_ADDR_77 7 ++ ++#define XAH_CTRL_0 _SFR_MEM8(0x16C) ++#define SLOTTED_OPERATION 0 ++#define MAX_CSMA_RETRIES0 1 ++#define MAX_CSMA_RETRIES1 2 ++#define MAX_CSMA_RETRIES2 3 ++#define MAX_FRAME_RETRIES0 4 ++#define MAX_FRAME_RETRIES1 5 ++#define MAX_FRAME_RETRIES2 6 ++#define MAX_FRAME_RETRIES3 7 ++ ++#define CSMA_SEED_0 _SFR_MEM8(0x16D) ++#define CSMA_SEED_00 0 ++#define CSMA_SEED_01 1 ++#define CSMA_SEED_02 2 ++#define CSMA_SEED_03 3 ++#define CSMA_SEED_04 4 ++#define CSMA_SEED_05 5 ++#define CSMA_SEED_06 6 ++#define CSMA_SEED_07 7 ++ ++#define CSMA_SEED_1 _SFR_MEM8(0x16E) ++#define CSMA_SEED_10 0 ++#define CSMA_SEED_11 1 ++#define CSMA_SEED_12 2 ++#define AACK_I_AM_COORD 3 ++#define AACK_DIS_ACK 4 ++#define AACK_SET_PD 5 ++#define AACK_FVN_MODE0 6 ++#define AACK_FVN_MODE1 7 ++ ++#define CSMA_BE _SFR_MEM8(0x16F) ++#define MIN_BE0 0 ++#define MIN_BE1 1 ++#define MIN_BE2 2 ++#define MIN_BE3 3 ++#define MAX_BE0 4 ++#define MAX_BE1 5 ++#define MAX_BE2 6 ++#define MAX_BE3 7 ++ ++/* Reserved [0x170..0x175] */ ++ ++#define TST_CTRL_DIGI _SFR_MEM8(0x176) ++#define TST_CTRL_DIG0 0 ++#define TST_CTRL_DIG1 1 ++#define TST_CTRL_DIG2 2 ++#define TST_CTRL_DIG3 3 ++ ++/* Reserved [0x177..0x17A] */ ++ ++#define TST_RX_LENGTH _SFR_MEM8(0x17B) ++#define RX_LENGTH0 0 ++#define RX_LENGTH1 1 ++#define RX_LENGTH2 2 ++#define RX_LENGTH3 3 ++#define RX_LENGTH4 4 ++#define RX_LENGTH5 5 ++#define RX_LENGTH6 6 ++#define RX_LENGTH7 7 ++ ++/* Reserved [0x17C..0x17F] */ ++ ++#define TRXFBST _SFR_MEM8(0x180) ++ ++/* Reserved [0x181..0x1FE] */ ++ ++#define TRXFBEND _SFR_MEM8(0x1FF) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect _VECTOR(3) ++#define INT2_vect_num 3 ++ ++/* External Interrupt Request 3 */ ++#define INT3_vect _VECTOR(4) ++#define INT3_vect_num 4 ++ ++/* External Interrupt Request 4 */ ++#define INT4_vect _VECTOR(5) ++#define INT4_vect_num 5 ++ ++/* External Interrupt Request 5 */ ++#define INT5_vect _VECTOR(6) ++#define INT5_vect_num 6 ++ ++/* External Interrupt Request 6 */ ++#define INT6_vect _VECTOR(7) ++#define INT6_vect_num 7 ++ ++/* External Interrupt Request 7 */ ++#define INT7_vect _VECTOR(8) ++#define INT7_vect_num 8 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(9) ++#define PCINT0_vect_num 9 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(10) ++#define PCINT1_vect_num 10 ++ ++/* Pin Change Interrupt Request 2 */ ++#define PCINT2_vect _VECTOR(11) ++#define PCINT2_vect_num 11 ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect _VECTOR(12) ++#define WDT_vect_num 12 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPA_vect _VECTOR(13) ++#define TIMER2_COMPA_vect_num 13 ++ ++/* Timer/Counter2 Compare Match B */ ++#define TIMER2_COMPB_vect _VECTOR(14) ++#define TIMER2_COMPB_vect_num 14 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(15) ++#define TIMER2_OVF_vect_num 15 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(16) ++#define TIMER1_CAPT_vect_num 16 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(17) ++#define TIMER1_COMPA_vect_num 17 ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(18) ++#define TIMER1_COMPB_vect_num 18 ++ ++/* Timer/Counter1 Compare Match C */ ++#define TIMER1_COMPC_vect _VECTOR(19) ++#define TIMER1_COMPC_vect_num 19 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(20) ++#define TIMER1_OVF_vect_num 20 ++ ++/* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPA_vect _VECTOR(21) ++#define TIMER0_COMPA_vect_num 21 ++ ++/* Timer/Counter0 Compare Match B */ ++#define TIMER0_COMPB_vect _VECTOR(22) ++#define TIMER0_COMPB_vect_num 22 ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(23) ++#define TIMER0_OVF_vect_num 23 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(24) ++#define SPI_STC_vect_num 24 ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect _VECTOR(25) ++#define USART0_RX_vect_num 25 ++ ++/* USART0 Data register Empty */ ++#define USART0_UDRE_vect _VECTOR(26) ++#define USART0_UDRE_vect_num 26 ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect _VECTOR(27) ++#define USART0_TX_vect_num 27 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(28) ++#define ANALOG_COMP_vect_num 28 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(29) ++#define ADC_vect_num 29 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(30) ++#define EE_READY_vect_num 30 ++ ++/* Timer/Counter3 Capture Event */ ++#define TIMER3_CAPT_vect _VECTOR(31) ++#define TIMER3_CAPT_vect_num 31 ++ ++/* Timer/Counter3 Compare Match A */ ++#define TIMER3_COMPA_vect _VECTOR(32) ++#define TIMER3_COMPA_vect_num 32 ++ ++/* Timer/Counter3 Compare Match B */ ++#define TIMER3_COMPB_vect _VECTOR(33) ++#define TIMER3_COMPB_vect_num 33 ++ ++/* Timer/Counter3 Compare Match C */ ++#define TIMER3_COMPC_vect _VECTOR(34) ++#define TIMER3_COMPC_vect_num 34 ++ ++/* Timer/Counter3 Overflow */ ++#define TIMER3_OVF_vect _VECTOR(35) ++#define TIMER3_OVF_vect_num 35 ++ ++/* USART1, Rx Complete */ ++#define USART1_RX_vect _VECTOR(36) ++#define USART1_RX_vect_num 36 ++ ++/* USART1 Data register Empty */ ++#define USART1_UDRE_vect _VECTOR(37) ++#define USART1_UDRE_vect_num 37 ++ ++/* USART1, Tx Complete */ ++#define USART1_TX_vect _VECTOR(38) ++#define USART1_TX_vect_num 38 ++ ++/* 2-wire Serial Interface */ ++#define TWI_vect _VECTOR(39) ++#define TWI_vect_num 39 ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect _VECTOR(40) ++#define SPM_READY_vect_num 40 ++ ++/* Timer/Counter4 Capture Event */ ++#define TIMER4_CAPT_vect _VECTOR(41) ++#define TIMER4_CAPT_vect_num 41 ++ ++/* Timer/Counter4 Compare Match A */ ++#define TIMER4_COMPA_vect _VECTOR(42) ++#define TIMER4_COMPA_vect_num 42 ++ ++/* Timer/Counter4 Compare Match B */ ++#define TIMER4_COMPB_vect _VECTOR(43) ++#define TIMER4_COMPB_vect_num 43 ++ ++/* Timer/Counter4 Compare Match C */ ++#define TIMER4_COMPC_vect _VECTOR(44) ++#define TIMER4_COMPC_vect_num 44 ++ ++/* Timer/Counter4 Overflow */ ++#define TIMER4_OVF_vect _VECTOR(45) ++#define TIMER4_OVF_vect_num 45 ++ ++/* Timer/Counter5 Capture Event */ ++#define TIMER5_CAPT_vect _VECTOR(46) ++#define TIMER5_CAPT_vect_num 46 ++ ++/* Timer/Counter5 Compare Match A */ ++#define TIMER5_COMPA_vect _VECTOR(47) ++#define TIMER5_COMPA_vect_num 47 ++ ++/* Timer/Counter5 Compare Match B */ ++#define TIMER5_COMPB_vect _VECTOR(48) ++#define TIMER5_COMPB_vect_num 48 ++ ++/* Timer/Counter5 Compare Match C */ ++#define TIMER5_COMPC_vect _VECTOR(49) ++#define TIMER5_COMPC_vect_num 49 ++ ++/* Timer/Counter5 Overflow */ ++#define TIMER5_OVF_vect _VECTOR(50) ++#define TIMER5_OVF_vect_num 50 ++ ++/* TRX24 - PLL lock interrupt */ ++#define TRX24_PLL_LOCK_vect _VECTOR(57) ++#define TRX24_PLL_LOCK_vect_num 57 ++ ++/* TRX24 - PLL unlock interrupt */ ++#define TRX24_PLL_UNLOCK_vect _VECTOR(58) ++#define TRX24_PLL_UNLOCK_vect_num 58 ++ ++/* TRX24 - Receive start interrupt */ ++#define TRX24_RX_START_vect _VECTOR(59) ++#define TRX24_RX_START_vect_num 59 ++ ++/* TRX24 - RX_END interrupt */ ++#define TRX24_RX_END_vect _VECTOR(60) ++#define TRX24_RX_END_vect_num 60 ++ ++/* TRX24 - CCA/ED done interrupt */ ++#define TRX24_CCA_ED_DONE_vect _VECTOR(61) ++#define TRX24_CCA_ED_DONE_vect_num 61 ++ ++/* TRX24 - XAH - AMI */ ++#define TRX24_XAH_AMI_vect _VECTOR(62) ++#define TRX24_XAH_AMI_vect_num 62 ++ ++/* TRX24 - TX_END interrupt */ ++#define TRX24_TX_END_vect _VECTOR(63) ++#define TRX24_TX_END_vect_num 63 ++ ++/* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */ ++#define TRX24_AWAKE_vect _VECTOR(64) ++#define TRX24_AWAKE_vect_num 64 ++ ++/* Symbol counter - compare match 1 interrupt */ ++#define SCNT_CMP1_vect _VECTOR(65) ++#define SCNT_CMP1_vect_num 65 ++ ++/* Symbol counter - compare match 2 interrupt */ ++#define SCNT_CMP2_vect _VECTOR(66) ++#define SCNT_CMP2_vect_num 66 ++ ++/* Symbol counter - compare match 3 interrupt */ ++#define SCNT_CMP3_vect _VECTOR(67) ++#define SCNT_CMP3_vect_num 67 ++ ++/* Symbol counter - overflow interrupt */ ++#define SCNT_OVFL_vect _VECTOR(68) ++#define SCNT_OVFL_vect_num 68 ++ ++/* Symbol counter - backoff interrupt */ ++#define SCNT_BACKOFF_vect _VECTOR(69) ++#define SCNT_BACKOFF_vect_num 69 ++ ++/* AES engine ready interrupt */ ++#define AES_READY_vect _VECTOR(70) ++#define AES_READY_vect_num 70 ++ ++/* Battery monitor indicates supply voltage below threshold */ ++#define BAT_LOW_vect _VECTOR(71) ++#define BAT_LOW_vect_num 71 ++ ++/* TRX24 TX start interrupt */ ++#define TRX24_TX_START_vect _VECTOR(72) ++#define TRX24_TX_START_vect_num 72 ++ ++/* Address match interrupt of address filter 0 */ ++#define TRX24_AMI0_vect _VECTOR(73) ++#define TRX24_AMI0_vect_num 73 ++ ++/* Address match interrupt of address filter 1 */ ++#define TRX24_AMI1_vect _VECTOR(74) ++#define TRX24_AMI1_vect_num 74 ++ ++/* Address match interrupt of address filter 2 */ ++#define TRX24_AMI2_vect _VECTOR(75) ++#define TRX24_AMI2_vect_num 75 ++ ++/* Address match interrupt of address filter 3 */ ++#define TRX24_AMI3_vect _VECTOR(76) ++#define TRX24_AMI3_vect_num 76 ++ ++#define _VECTORS_SIZE 308 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 256 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0xFFFF ++#define RAMSTART 0x0200 ++#define RAMSIZE 8192 ++#define RAMEND 0x21FF ++#define E2START 0 ++#define E2SIZE 2048 ++#define E2PAGESIZE 8 ++#define E2END 0x07FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL_SUT0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL_SUT1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL_SUT2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL_SUT3 (unsigned char)~_BV(3) ++#define FUSE_CKSEL_SUT4 (unsigned char)~_BV(4) ++#define FUSE_CKSEL_SUT5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0xA6 ++#define SIGNATURE_2 0x03 ++ ++ ++#endif /* #ifdef _AVR_ATMEGA644RFR2_H_INCLUDED */ ++ +diff --git a/include/avr/iom645.h b/include/avr/iom645.h +index a3dd5f4..ea07f36 100644 +--- a/include/avr/iom645.h ++++ b/include/avr/iom645.h +@@ -1,870 +1,870 @@ +-/* Copyright (c) 2004,2005,2006 Eric B. Weddington +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom645.h 2235 2011-03-17 04:13:14Z arcanum $ */ +- +-/* avr/iom645.h - definitions for ATmega645 */ +- +-#ifndef _AVR_IOM645_H_ +-#define _AVR_IOM645_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom645.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* Registers and associated bit numbers */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-#define PORTA _SFR_IO8(0x02) +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-#define PINB _SFR_IO8(0x03) +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-#define PORTB _SFR_IO8(0x05) +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-#define PORTC _SFR_IO8(0x08) +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-#define PINE _SFR_IO8(0x0C) +-#define PINE7 7 +-#define PINE6 6 +-#define PINE5 5 +-#define PINE4 4 +-#define PINE3 3 +-#define PINE2 2 +-#define PINE1 1 +-#define PINE0 0 +- +-#define DDRE _SFR_IO8(0x0D) +-#define DDE7 7 +-#define DDE6 6 +-#define DDE5 5 +-#define DDE4 4 +-#define DDE3 3 +-#define DDE2 2 +-#define DDE1 1 +-#define DDE0 0 +- +-#define PORTE _SFR_IO8(0x0E) +-#define PE7 7 +-#define PE6 6 +-#define PE5 5 +-#define PE4 4 +-#define PE3 3 +-#define PE2 2 +-#define PE1 1 +-#define PE0 0 +- +-#define PINF _SFR_IO8(0x0F) +-#define PINF7 7 +-#define PINF6 6 +-#define PINF5 5 +-#define PINF4 4 +-#define PINF3 3 +-#define PINF2 2 +-#define PINF1 1 +-#define PINF0 0 +- +-#define DDRF _SFR_IO8(0x10) +-#define DDF7 7 +-#define DDF6 6 +-#define DDF5 5 +-#define DDF4 4 +-#define DDF3 3 +-#define DDF2 2 +-#define DDF1 1 +-#define DDF0 0 +- +-#define PORTF _SFR_IO8(0x11) +-#define PF7 7 +-#define PF6 6 +-#define PF5 5 +-#define PF4 4 +-#define PF3 3 +-#define PF2 2 +-#define PF1 1 +-#define PF0 0 +- +-#define PING _SFR_IO8(0x12) +-#define PING5 5 +-#define PING4 4 +-#define PING3 3 +-#define PING2 2 +-#define PING1 1 +-#define PING0 0 +- +-#define DDRG _SFR_IO8(0x13) +-#define DDG4 4 +-#define DDG3 3 +-#define DDG2 2 +-#define DDG1 1 +-#define DDG0 0 +- +-#define PORTG _SFR_IO8(0x14) +-#define PG4 4 +-#define PG3 3 +-#define PG2 2 +-#define PG1 1 +-#define PG0 0 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define TIFR2 _SFR_IO8(0x17) +-#define TOV2 0 +-#define OCF2A 1 +- +-/* Reserved [0x18..0x1B] */ +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define PCIF0 4 +-#define PCIF1 5 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define PCIE0 4 +-#define PCIE1 5 +- +-#define GPIOR0 _SFR_IO8(0x1E) +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEWE 1 +-#define EEMWE 2 +-#define EERIE 3 +- +-#define EEDR _SFR_IO8(0X20) +- +-/* Combine EEARL and EEARH */ +-#define EEAR _SFR_IO16(0x21) +-#define EEARL _SFR_IO8(0x21) +-#define EEARH _SFR_IO8(0X22) +- +-/* 6-char sequence denoting where to find the EEPROM registers in memory space. +- Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM +- subroutines. +- First two letters: EECR address. +- Second two letters: EEDR address. +- Last two letters: EEAR address. */ +-#define __EEPROM_REG_LOCATIONS__ 1F2021 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSR10 0 +-#define PSR2 1 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM01 3 +-#define COM0A0 4 +-#define COM0A1 5 +-#define WGM00 6 +-#define FOC0A 7 +- +-/* Reserved [0x25] */ +- +-#define TCNT0 _SFR_IO8(0X26) +- +-#define OCR0A _SFR_IO8(0X27) +- +-/* Reserved [0x28..0x29] */ +- +-#define GPIOR1 _SFR_IO8(0x2A) +- +-#define GPIOR2 _SFR_IO8(0x2B) +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0X2E) +- +-/* Reserved [0x2F] */ +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define OCDR _SFR_IO8(0x31) +-#define OCDR0 0 +-#define OCDR1 1 +-#define OCDR2 2 +-#define OCDR3 3 +-#define OCDR4 4 +-#define OCDR5 5 +-#define OCDR6 6 +-#define OCDR7 7 +-#define IDRD 7 +- +-/* Reserved [0x32] */ +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +-#define JTRF 4 +- +-#define MCUCR _SFR_IO8(0X35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define JTD 7 +- +-/* Reserved [0x36] */ +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define RWWSB 6 +-#define SPMIE 7 +- +-/* Reserved [0x38..0x3C] */ +- +-/* SP [0x3D..0x3E] */ +-/* SREG [0x3F] */ +- +-#define WDTCR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-/* Reserved [0x62..0x63] */ +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM1 3 +- +-/* Reserved [0x65] */ +- +-#define OSCCAL _SFR_MEM8(0x66) +- +-/* Reserved [0x67..0x68] */ +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +- +-/* Reserved [0x6A] */ +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-/* Reserved [0x6D] */ +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define TIMSK2 _SFR_MEM8(0x70) +-#define TOIE2 0 +-#define OCIE2A 1 +- +-/* Reserved [0x71..0x77] */ +- +-/* Combine ADCL and ADCH */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +-#define ADCL _SFR_MEM8(0x78) +-#define ADCH _SFR_MEM8(0x79) +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ACME 6 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-/* Reserved [0x7D] */ +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0X80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0X81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-/* Reserved [0x83] */ +- +-/* Combine TCNT1L and TCNT1H */ +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1H _SFR_MEM8(0x85) +- +-/* Combine ICR1L and ICR1H */ +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1H _SFR_MEM8(0x87) +- +-/* Combine OCR1AL and OCR1AH */ +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AH _SFR_MEM8(0x89) +- +-/* Combine OCR1BL and OCR1BH */ +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BH _SFR_MEM8(0x8B) +- +-/* Reserved [0x8C..0xAF] */ +- +-#define TCCR2A _SFR_MEM8(0xB0) +-#define CS20 0 +-#define CS21 1 +-#define CS22 2 +-#define WGM21 3 +-#define COM2A0 4 +-#define COM2A1 5 +-#define WGM20 6 +-#define FOC2A 7 +- +-/* Reserved [0xB1] */ +- +-#define TCNT2 _SFR_MEM8(0xB2) +- +-#define OCR2A _SFR_MEM8(0xB3) +- +-/* Reserved [0xB4..0xB5] */ +- +-#define ASSR _SFR_MEM8(0xB6) +-#define TCR2UB 0 +-#define OCR2UB 1 +-#define TCN2UB 2 +-#define AS2 3 +-#define EXCLK 4 +- +-/* Reserved [0xB7] */ +- +-#define USICR _SFR_MEM8(0xB8) +-#define USITC 0 +-#define USICLK 1 +-#define USICS0 2 +-#define USICS1 3 +-#define USIWM0 4 +-#define USIWM1 5 +-#define USIOIE 6 +-#define USISIE 7 +- +-#define USISR _SFR_MEM8(0xB9) +-#define USICNT0 0 +-#define USICNT1 1 +-#define USICNT2 2 +-#define USICNT3 3 +-#define USIDC 4 +-#define USIPF 5 +-#define USIOIF 6 +-#define USISIF 7 +- +-#define USIDR _SFR_MEM8(0xBA) +- +-/* Reserved [0xBB..0xBF] */ +- +-#define UCSR0A _SFR_MEM8(0xC0) +-#define MPCM0 0 +-#define U2X0 1 +-#define UPE0 2 +-#define DOR0 3 +-#define FE0 4 +-#define UDRE0 5 +-#define TXC0 6 +-#define RXC0 7 +- +-#define UCSR0B _SFR_MEM8(0XC1) +-#define TXB80 0 +-#define RXB80 1 +-#define UCSZ02 2 +-#define TXEN0 3 +-#define RXEN0 4 +-#define UDRIE0 5 +-#define TXCIE0 6 +-#define RXCIE0 7 +- +-#define UCSR0C _SFR_MEM8(0xC2) +-#define UCPOL0 0 +-#define UCSZ00 1 +-#define UCSZ01 2 +-#define USBS0 3 +-#define UPM00 4 +-#define UPM01 5 +-#define UMSEL0 6 +- +-/* Reserved [0xC3] */ +- +-/* Combine UBRR0L and UBRR0H */ +-#define UBRR0 _SFR_MEM16(0xC4) +- +-#define UBRR0L _SFR_MEM8(0xC4) +-#define UBRR0H _SFR_MEM8(0xC5) +- +-#define UDR0 _SFR_MEM8(0XC6) +- +-/* Reserved [0xC7..0xFF] */ +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* Pin Change Interrupt Request 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) +-#define SIG_PIN_CHANGE0 _VECTOR(2) +- +-/* Pin Change Interrupt Request 1 */ +-#define PCINT1_vect_num 3 +-#define PCINT1_vect _VECTOR(3) +-#define SIG_PIN_CHANGE1 _VECTOR(3) +- +-/* Timer/Counter2 Compare Match */ +-#define TIMER2_COMP_vect_num 4 +-#define TIMER2_COMP_vect _VECTOR(4) +-#define SIG_OUTPUT_COMPARE2 _VECTOR(4) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 5 +-#define TIMER2_OVF_vect _VECTOR(5) +-#define SIG_OVERFLOW2 _VECTOR(5) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 6 +-#define TIMER1_CAPT_vect _VECTOR(6) +-#define SIG_INPUT_CAPTURE1 _VECTOR(6) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 7 +-#define TIMER1_COMPA_vect _VECTOR(7) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(7) +- +-/* Timer/Counter Compare Match B */ +-#define TIMER1_COMPB_vect_num 8 +-#define TIMER1_COMPB_vect _VECTOR(8) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(8) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 9 +-#define TIMER1_OVF_vect _VECTOR(9) +-#define SIG_OVERFLOW1 _VECTOR(9) +- +-/* Timer/Counter0 Compare Match */ +-#define TIMER0_COMP_vect_num 10 +-#define TIMER0_COMP_vect _VECTOR(10) +-#define SIG_OUTPUT_COMPARE0 _VECTOR(10) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 11 +-#define TIMER0_OVF_vect _VECTOR(11) +-#define SIG_OVERFLOW0 _VECTOR(11) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 12 +-#define SPI_STC_vect _VECTOR(12) +-#define SIG_SPI _VECTOR(12) +- +-/* USART0, Rx Complete */ +-#define USART0_RX_vect_num 13 +-#define USART0_RX_vect _VECTOR(13) +-#define SIG_UART_RECV _VECTOR(13) +- +-/* USART0 Data register Empty */ +-#define USART0_UDRE_vect_num 14 +-#define USART0_UDRE_vect _VECTOR(14) +-#define SIG_UART_DATA _VECTOR(14) +- +-/* USART0, Tx Complete */ +-#define USART0_TX_vect_num 15 +-#define USART0_TX_vect _VECTOR(15) +-#define SIG_UART_TRANS _VECTOR(15) +- +-/* USI Start Condition */ +-#define USI_START_vect_num 16 +-#define USI_START_vect _VECTOR(16) +-#define SIG_USI_START _VECTOR(16) +- +-/* USI Overflow */ +-#define USI_OVERFLOW_vect_num 17 +-#define USI_OVERFLOW_vect _VECTOR(17) +-#define SIG_USI_OVERFLOW _VECTOR(17) +- +-/* Analog Comparator */ +-#define ANALOG_COMP_vect_num 18 +-#define ANALOG_COMP_vect _VECTOR(18) +-#define SIG_COMPARATOR _VECTOR(18) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 19 +-#define ADC_vect _VECTOR(19) +-#define SIG_ADC _VECTOR(19) +- +-/* EEPROM Ready */ +-#define EE_READY_vect_num 20 +-#define EE_READY_vect _VECTOR(20) +-#define SIG_EEPROM_READY _VECTOR(20) +- +-/* Store Program Memory Read */ +-#define SPM_READY_vect_num 21 +-#define SPM_READY_vect _VECTOR(21) +-#define SIG_SPM_READY _VECTOR(21) +- +-/* Vector 22 is Reserved */ +- +-#define _VECTORS_SIZE 92 +- +- +-/* Constants */ +-#define SPM_PAGESIZE 256 +-#define RAMSTART (0x100) +-#define RAMEND 0x10FF +-#define XRAMEND RAMEND +-#define E2END 0x7FF +-#define E2PAGESIZE 8 +-#define FLASHEND 0xFFFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x96 +-#define SIGNATURE_2 0x05 +- +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_PIN_CHANGE0 +-#pragma GCC poison SIG_PIN_CHANGE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE2 +-#pragma GCC poison SIG_OVERFLOW2 +-#pragma GCC poison SIG_INPUT_CAPTURE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OUTPUT_COMPARE0 +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_SPI +-#pragma GCC poison SIG_UART_RECV +-#pragma GCC poison SIG_UART_DATA +-#pragma GCC poison SIG_UART_TRANS +-#pragma GCC poison SIG_USI_START +-#pragma GCC poison SIG_USI_OVERFLOW +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_ADC +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_SPM_READY +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +- +-#endif /* _AVR_IOM645_H_ */ ++/* Copyright (c) 2004,2005,2006 Eric B. Weddington ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom645.h 2235 2011-03-17 04:13:14Z arcanum $ */ ++ ++/* avr/iom645.h - definitions for ATmega645 */ ++ ++#ifndef _AVR_IOM645_H_ ++#define _AVR_IOM645_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom645.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE7 7 ++#define DDE6 6 ++#define DDE5 5 ++#define DDE4 4 ++#define DDE3 3 ++#define DDE2 2 ++#define DDE1 1 ++#define DDE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PE7 7 ++#define PE6 6 ++#define PE5 5 ++#define PE4 4 ++#define PE3 3 ++#define PE2 2 ++#define PE1 1 ++#define PE0 0 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDF7 7 ++#define DDF6 6 ++#define DDF5 5 ++#define DDF4 4 ++#define DDF3 3 ++#define DDF2 2 ++#define DDF1 1 ++#define DDF0 0 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PF7 7 ++#define PF6 6 ++#define PF5 5 ++#define PF4 4 ++#define PF3 3 ++#define PF2 2 ++#define PF1 1 ++#define PF0 0 ++ ++#define PING _SFR_IO8(0x12) ++#define PING5 5 ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++#define DDRG _SFR_IO8(0x13) ++#define DDG4 4 ++#define DDG3 3 ++#define DDG2 2 ++#define DDG1 1 ++#define DDG0 0 ++ ++#define PORTG _SFR_IO8(0x14) ++#define PG4 4 ++#define PG3 3 ++#define PG2 2 ++#define PG1 1 ++#define PG0 0 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++ ++/* Reserved [0x18..0x1B] */ ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define PCIF0 4 ++#define PCIF1 5 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define PCIE0 4 ++#define PCIE1 5 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++ ++#define EEDR _SFR_IO8(0X20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0X22) ++ ++/* 6-char sequence denoting where to find the EEPROM registers in memory space. ++ Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM ++ subroutines. ++ First two letters: EECR address. ++ Second two letters: EEDR address. ++ Last two letters: EEAR address. */ ++#define __EEPROM_REG_LOCATIONS__ 1F2021 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR10 0 ++#define PSR2 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM01 3 ++#define COM0A0 4 ++#define COM0A1 5 ++#define WGM00 6 ++#define FOC0A 7 ++ ++/* Reserved [0x25] */ ++ ++#define TCNT0 _SFR_IO8(0X26) ++ ++#define OCR0A _SFR_IO8(0X27) ++ ++/* Reserved [0x28..0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0X2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCDR7 7 ++#define IDRD 7 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define JTRF 4 ++ ++#define MCUCR _SFR_IO8(0X35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define JTD 7 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++/* SREG [0x3F] */ ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++ ++/* Reserved [0x67..0x68] */ ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++/* Reserved [0x6D] */ ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++ ++/* Reserved [0x71..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0X80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0X81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM21 3 ++#define COM2A0 4 ++#define COM2A1 5 ++#define WGM20 6 ++#define FOC2A 7 ++ ++/* Reserved [0xB1] */ ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++/* Reserved [0xB4..0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2UB 0 ++#define OCR2UB 1 ++#define TCN2UB 2 ++#define AS2 3 ++#define EXCLK 4 ++ ++/* Reserved [0xB7] */ ++ ++#define USICR _SFR_MEM8(0xB8) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_MEM8(0xB9) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_MEM8(0xBA) ++ ++/* Reserved [0xBB..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0XC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL0 6 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0XC6) ++ ++/* Reserved [0xC7..0xFF] */ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) ++#define SIG_PIN_CHANGE0 _VECTOR(2) ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect_num 3 ++#define PCINT1_vect _VECTOR(3) ++#define SIG_PIN_CHANGE1 _VECTOR(3) ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect_num 4 ++#define TIMER2_COMP_vect _VECTOR(4) ++#define SIG_OUTPUT_COMPARE2 _VECTOR(4) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 5 ++#define TIMER2_OVF_vect _VECTOR(5) ++#define SIG_OVERFLOW2 _VECTOR(5) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 6 ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define SIG_INPUT_CAPTURE1 _VECTOR(6) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 7 ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(7) ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect_num 8 ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(8) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 9 ++#define TIMER1_OVF_vect _VECTOR(9) ++#define SIG_OVERFLOW1 _VECTOR(9) ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect_num 10 ++#define TIMER0_COMP_vect _VECTOR(10) ++#define SIG_OUTPUT_COMPARE0 _VECTOR(10) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 11 ++#define TIMER0_OVF_vect _VECTOR(11) ++#define SIG_OVERFLOW0 _VECTOR(11) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 12 ++#define SPI_STC_vect _VECTOR(12) ++#define SIG_SPI _VECTOR(12) ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect_num 13 ++#define USART0_RX_vect _VECTOR(13) ++#define SIG_UART_RECV _VECTOR(13) ++ ++/* USART0 Data register Empty */ ++#define USART0_UDRE_vect_num 14 ++#define USART0_UDRE_vect _VECTOR(14) ++#define SIG_UART_DATA _VECTOR(14) ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect_num 15 ++#define USART0_TX_vect _VECTOR(15) ++#define SIG_UART_TRANS _VECTOR(15) ++ ++/* USI Start Condition */ ++#define USI_START_vect_num 16 ++#define USI_START_vect _VECTOR(16) ++#define SIG_USI_START _VECTOR(16) ++ ++/* USI Overflow */ ++#define USI_OVERFLOW_vect_num 17 ++#define USI_OVERFLOW_vect _VECTOR(17) ++#define SIG_USI_OVERFLOW _VECTOR(17) ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect_num 18 ++#define ANALOG_COMP_vect _VECTOR(18) ++#define SIG_COMPARATOR _VECTOR(18) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 19 ++#define ADC_vect _VECTOR(19) ++#define SIG_ADC _VECTOR(19) ++ ++/* EEPROM Ready */ ++#define EE_READY_vect_num 20 ++#define EE_READY_vect _VECTOR(20) ++#define SIG_EEPROM_READY _VECTOR(20) ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect_num 21 ++#define SPM_READY_vect _VECTOR(21) ++#define SIG_SPM_READY _VECTOR(21) ++ ++/* Vector 22 is Reserved */ ++ ++#define _VECTORS_SIZE 92 ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE 256 ++#define RAMSTART (0x100) ++#define RAMEND 0x10FF ++#define XRAMEND RAMEND ++#define E2END 0x7FF ++#define E2PAGESIZE 8 ++#define FLASHEND 0xFFFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x05 ++ ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_PIN_CHANGE0 ++#pragma GCC poison SIG_PIN_CHANGE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE2 ++#pragma GCC poison SIG_OVERFLOW2 ++#pragma GCC poison SIG_INPUT_CAPTURE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OUTPUT_COMPARE0 ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_SPI ++#pragma GCC poison SIG_UART_RECV ++#pragma GCC poison SIG_UART_DATA ++#pragma GCC poison SIG_UART_TRANS ++#pragma GCC poison SIG_USI_START ++#pragma GCC poison SIG_USI_OVERFLOW ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_ADC ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_SPM_READY ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++ ++#endif /* _AVR_IOM645_H_ */ +diff --git a/include/avr/iom6450.h b/include/avr/iom6450.h +index 80eab1e..54f3964 100644 +--- a/include/avr/iom6450.h ++++ b/include/avr/iom6450.h +@@ -1,967 +1,967 @@ +-/* Copyright (c) 2004,2005,2006 Eric B. Weddington +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom6450.h 2235 2011-03-17 04:13:14Z arcanum $ */ +- +-/* avr/iom6450.h - definitions for ATmega6450 */ +- +-#ifndef _AVR_IOM6450_H_ +-#define _AVR_IOM6450_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom6450.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* Registers and associated bit numbers */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-#define PORTA _SFR_IO8(0x02) +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-#define PINB _SFR_IO8(0x03) +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-#define PORTB _SFR_IO8(0x05) +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-#define PORTC _SFR_IO8(0x08) +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-#define PINE _SFR_IO8(0x0C) +-#define PINE7 7 +-#define PINE6 6 +-#define PINE5 5 +-#define PINE4 4 +-#define PINE3 3 +-#define PINE2 2 +-#define PINE1 1 +-#define PINE0 0 +- +-#define DDRE _SFR_IO8(0x0D) +-#define DDE7 7 +-#define DDE6 6 +-#define DDE5 5 +-#define DDE4 4 +-#define DDE3 3 +-#define DDE2 2 +-#define DDE1 1 +-#define DDE0 0 +- +-#define PORTE _SFR_IO8(0x0E) +-#define PE7 7 +-#define PE6 6 +-#define PE5 5 +-#define PE4 4 +-#define PE3 3 +-#define PE2 2 +-#define PE1 1 +-#define PE0 0 +- +-#define PINF _SFR_IO8(0x0F) +-#define PINF7 7 +-#define PINF6 6 +-#define PINF5 5 +-#define PINF4 4 +-#define PINF3 3 +-#define PINF2 2 +-#define PINF1 1 +-#define PINF0 0 +- +-#define DDRF _SFR_IO8(0x10) +-#define DDF7 7 +-#define DDF6 6 +-#define DDF5 5 +-#define DDF4 4 +-#define DDF3 3 +-#define DDF2 2 +-#define DDF1 1 +-#define DDF0 0 +- +-#define PORTF _SFR_IO8(0x11) +-#define PF7 7 +-#define PF6 6 +-#define PF5 5 +-#define PF4 4 +-#define PF3 3 +-#define PF2 2 +-#define PF1 1 +-#define PF0 0 +- +-#define PING _SFR_IO8(0x12) +-#define PING5 5 +-#define PING4 4 +-#define PING3 3 +-#define PING2 2 +-#define PING1 1 +-#define PING0 0 +- +-#define DDRG _SFR_IO8(0x13) +-#define DDG4 4 +-#define DDG3 3 +-#define DDG2 2 +-#define DDG1 1 +-#define DDG0 0 +- +-#define PORTG _SFR_IO8(0x14) +-#define PG4 4 +-#define PG3 3 +-#define PG2 2 +-#define PG1 1 +-#define PG0 0 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define TIFR2 _SFR_IO8(0x17) +-#define TOV2 0 +-#define OCF2A 1 +- +-/* Reserved [0x18..0x1B] */ +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define PCIF0 4 +-#define PCIF1 5 +-#define PCIF2 6 +-#define PCIF3 7 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define PCIE0 4 +-#define PCIE1 5 +-#define PCIE2 6 +-#define PCIE3 7 +- +-#define GPIOR0 _SFR_IO8(0x1E) +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEWE 1 +-#define EEMWE 2 +-#define EERIE 3 +- +-#define EEDR _SFR_IO8(0X20) +- +-/* Combine EEARL and EEARH */ +-#define EEAR _SFR_IO16(0x21) +-#define EEARL _SFR_IO8(0x21) +-#define EEARH _SFR_IO8(0X22) +- +-/* 6-char sequence denoting where to find the EEPROM registers in memory space. +- Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM +- subroutines. +- First two letters: EECR address. +- Second two letters: EEDR address. +- Last two letters: EEAR address. */ +-#define __EEPROM_REG_LOCATIONS__ 1F2021 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSR10 0 +-#define PSR2 1 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM01 3 +-#define COM0A0 4 +-#define COM0A1 5 +-#define WGM00 6 +-#define FOC0A 7 +- +-/* Reserved [0x25] */ +- +-#define TCNT0 _SFR_IO8(0X26) +- +-#define OCR0A _SFR_IO8(0X27) +- +-/* Reserved [0x28..0x29] */ +- +-#define GPIOR1 _SFR_IO8(0x2A) +- +-#define GPIOR2 _SFR_IO8(0x2B) +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0X2E) +- +-/* Reserved [0x2F] */ +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define OCDR _SFR_IO8(0x31) +-#define OCDR0 0 +-#define OCDR1 1 +-#define OCDR2 2 +-#define OCDR3 3 +-#define OCDR4 4 +-#define OCDR5 5 +-#define OCDR6 6 +-#define OCDR7 7 +-#define IDRD 7 +- +-/* Reserved [0x32] */ +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +-#define JTRF 4 +- +-#define MCUCR _SFR_IO8(0X35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define JTD 7 +- +-/* Reserved [0x36] */ +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define RWWSB 6 +-#define SPMIE 7 +- +-/* Reserved [0x38..0x3C] */ +- +-/* SP [0x3D..0x3E] */ +-/* SREG [0x3F] */ +- +-#define WDTCR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-/* Reserved [0x62..0x63] */ +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM1 3 +- +-/* Reserved [0x65] */ +- +-#define OSCCAL _SFR_MEM8(0x66) +- +-/* Reserved [0x67..0x68] */ +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +- +-/* Reserved [0x6A] */ +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-#define PCMSK2 _SFR_MEM8(0x6D) +-#define PCINT16 0 +-#define PCINT17 1 +-#define PCINT18 2 +-#define PCINT19 3 +-#define PCINT20 4 +-#define PCINT21 5 +-#define PCINT22 6 +-#define PCINT23 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define TIMSK2 _SFR_MEM8(0x70) +-#define TOIE2 0 +-#define OCIE2A 1 +- +-/* Reserved [0x71..0x72] */ +- +-#define PCMSK3 _SFR_MEM8(0x73) +-#define PCINT24 0 +-#define PCINT25 1 +-#define PCINT26 2 +-#define PCINT27 3 +-#define PCINT28 4 +-#define PCINT29 5 +-#define PCINT30 6 +- +-/* Reserved [0x74..0x77] */ +- +-/* Combine ADCL and ADCH */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +-#define ADCL _SFR_MEM8(0x78) +-#define ADCH _SFR_MEM8(0x79) +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ACME 6 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-/* Reserved [0x7D] */ +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0X80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0X81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-/* Reserved [0x83] */ +- +-/* Combine TCNT1L and TCNT1H */ +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1H _SFR_MEM8(0x85) +- +-/* Combine ICR1L and ICR1H */ +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1H _SFR_MEM8(0x87) +- +-/* Combine OCR1AL and OCR1AH */ +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AH _SFR_MEM8(0x89) +- +-/* Combine OCR1BL and OCR1BH */ +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BH _SFR_MEM8(0x8B) +- +-/* Reserved [0x8C..0xAF] */ +- +-#define TCCR2A _SFR_MEM8(0xB0) +-#define CS20 0 +-#define CS21 1 +-#define CS22 2 +-#define WGM21 3 +-#define COM2A0 4 +-#define COM2A1 5 +-#define WGM20 6 +-#define FOC2A 7 +- +-/* Reserved [0xB1] */ +- +-#define TCNT2 _SFR_MEM8(0xB2) +- +-#define OCR2A _SFR_MEM8(0xB3) +- +-/* Reserved [0xB4..0xB5] */ +- +-#define ASSR _SFR_MEM8(0xB6) +-#define TCR2UB 0 +-#define OCR2UB 1 +-#define TCN2UB 2 +-#define AS2 3 +-#define EXCLK 4 +- +-/* Reserved [0xB7] */ +- +-#define USICR _SFR_MEM8(0xB8) +-#define USITC 0 +-#define USICLK 1 +-#define USICS0 2 +-#define USICS1 3 +-#define USIWM0 4 +-#define USIWM1 5 +-#define USIOIE 6 +-#define USISIE 7 +- +-#define USISR _SFR_MEM8(0xB9) +-#define USICNT0 0 +-#define USICNT1 1 +-#define USICNT2 2 +-#define USICNT3 3 +-#define USIDC 4 +-#define USIPF 5 +-#define USIOIF 6 +-#define USISIF 7 +- +-#define USIDR _SFR_MEM8(0xBA) +- +-/* Reserved [0xBB..0xBF] */ +- +-#define UCSR0A _SFR_MEM8(0xC0) +-#define MPCM0 0 +-#define U2X0 1 +-#define UPE0 2 +-#define DOR0 3 +-#define FE0 4 +-#define UDRE0 5 +-#define TXC0 6 +-#define RXC0 7 +- +-#define UCSR0B _SFR_MEM8(0XC1) +-#define TXB80 0 +-#define RXB80 1 +-#define UCSZ02 2 +-#define TXEN0 3 +-#define RXEN0 4 +-#define UDRIE0 5 +-#define TXCIE0 6 +-#define RXCIE0 7 +- +-#define UCSR0C _SFR_MEM8(0xC2) +-#define UCPOL0 0 +-#define UCSZ00 1 +-#define UCSZ01 2 +-#define USBS0 3 +-#define UPM00 4 +-#define UPM01 5 +-#define UMSEL0 6 +- +-/* Reserved [0xC3] */ +- +-/* Combine UBRR0L and UBRR0H */ +-#define UBRR0 _SFR_MEM16(0xC4) +- +-#define UBRR0L _SFR_MEM8(0xC4) +-#define UBRR0H _SFR_MEM8(0xC5) +- +-#define UDR0 _SFR_MEM8(0XC6) +- +-/* Reserved [0xC7..0xD7] */ +- +-#define PINH _SFR_MEM8(0xD8) +-#define PINH7 7 +-#define PINH6 6 +-#define PINH5 5 +-#define PINH4 4 +-#define PINH3 3 +-#define PINH2 2 +-#define PINH1 1 +-#define PINH0 0 +- +-#define DDRH _SFR_MEM8(0xD9) +-#define DDH7 7 +-#define DDH6 6 +-#define DDH5 5 +-#define DDH4 4 +-#define DDH3 3 +-#define DDH2 2 +-#define DDH1 1 +-#define DDH0 0 +- +-#define PORTH _SFR_MEM8(0xDA) +-#define PH7 7 +-#define PH6 6 +-#define PH5 5 +-#define PH4 4 +-#define PH3 3 +-#define PH2 2 +-#define PH1 1 +-#define PH0 0 +- +-#define PINJ _SFR_MEM8(0xDB) +-#define PINJ6 6 +-#define PINJ5 5 +-#define PINJ4 4 +-#define PINJ3 3 +-#define PINJ2 2 +-#define PINJ1 1 +-#define PINJ0 0 +- +-#define DDRJ _SFR_MEM8(0xDC) +-#define DDJ6 6 +-#define DDJ5 5 +-#define DDJ4 4 +-#define DDJ3 3 +-#define DDJ2 2 +-#define DDJ1 1 +-#define DDJ0 0 +- +-#define PORTJ _SFR_MEM8(0xDD) +-#define PJ6 6 +-#define PJ5 5 +-#define PJ4 4 +-#define PJ3 3 +-#define PJ2 2 +-#define PJ1 1 +-#define PJ0 0 +- +-/* Reserved [0xDE..0xFF] */ +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* Pin Change Interrupt Request 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) +-#define SIG_PIN_CHANGE0 _VECTOR(2) +- +-/* Pin Change Interrupt Request 1 */ +-#define PCINT1_vect_num 3 +-#define PCINT1_vect _VECTOR(3) +-#define SIG_PIN_CHANGE1 _VECTOR(3) +- +-/* Timer/Counter2 Compare Match */ +-#define TIMER2_COMP_vect_num 4 +-#define TIMER2_COMP_vect _VECTOR(4) +-#define SIG_OUTPUT_COMPARE2 _VECTOR(4) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 5 +-#define TIMER2_OVF_vect _VECTOR(5) +-#define SIG_OVERFLOW2 _VECTOR(5) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 6 +-#define TIMER1_CAPT_vect _VECTOR(6) +-#define SIG_INPUT_CAPTURE1 _VECTOR(6) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 7 +-#define TIMER1_COMPA_vect _VECTOR(7) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(7) +- +-/* Timer/Counter Compare Match B */ +-#define TIMER1_COMPB_vect_num 8 +-#define TIMER1_COMPB_vect _VECTOR(8) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(8) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 9 +-#define TIMER1_OVF_vect _VECTOR(9) +-#define SIG_OVERFLOW1 _VECTOR(9) +- +-/* Timer/Counter0 Compare Match */ +-#define TIMER0_COMP_vect_num 10 +-#define TIMER0_COMP_vect _VECTOR(10) +-#define SIG_OUTPUT_COMPARE0 _VECTOR(10) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 11 +-#define TIMER0_OVF_vect _VECTOR(11) +-#define SIG_OVERFLOW0 _VECTOR(11) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 12 +-#define SPI_STC_vect _VECTOR(12) +-#define SIG_SPI _VECTOR(12) +- +-/* USART, Rx Complete */ +-#define USART_RX_vect_num 13 +-#define USART_RX_vect _VECTOR(13) +-#define USART0_RX_vect _VECTOR(13) /* Alias */ +-#define SIG_UART_RECV _VECTOR(13) +- +-/* USART Data register Empty */ +-#define USART_UDRE_vect_num 14 +-#define USART_UDRE_vect _VECTOR(14) +-#define USART0_UDRE_vect _VECTOR(14) /* Alias */ +-#define SIG_UART_DATA _VECTOR(14) +- +-/* USART0, Tx Complete */ +-#define USART0_TX_vect_num 15 +-#define USART0_TX_vect _VECTOR(15) +-#define USART_TX_vect _VECTOR(15) /* Alias */ +-#define SIG_UART_TRANS _VECTOR(15) +- +-/* USI Start Condition */ +-#define USI_START_vect_num 16 +-#define USI_START_vect _VECTOR(16) +-#define SIG_USI_START _VECTOR(16) +- +-/* USI Overflow */ +-#define USI_OVERFLOW_vect_num 17 +-#define USI_OVERFLOW_vect _VECTOR(17) +-#define SIG_USI_OVERFLOW _VECTOR(17) +- +-/* Analog Comparator */ +-#define ANALOG_COMP_vect_num 18 +-#define ANALOG_COMP_vect _VECTOR(18) +-#define SIG_COMPARATOR _VECTOR(18) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 19 +-#define ADC_vect _VECTOR(19) +-#define SIG_ADC _VECTOR(19) +- +-/* EEPROM Ready */ +-#define EE_READY_vect_num 20 +-#define EE_READY_vect _VECTOR(20) +-#define SIG_EEPROM_READY _VECTOR(20) +- +-/* Store Program Memory Read */ +-#define SPM_READY_vect_num 21 +-#define SPM_READY_vect _VECTOR(21) +-#define SIG_SPM_READY _VECTOR(21) +- +-/* Pin Change Interrupt Request 2 */ +-#define PCINT2_vect_num 23 +-#define PCINT2_vect _VECTOR(23) +-#define SIG_PIN_CHANGE2 _VECTOR(23) +- +-/* Pin Change Interrupt Request 3 */ +-#define PCINT3_vect_num 24 +-#define PCINT3_vect _VECTOR(24) +-#define SIG_PIN_CHANGE3 _VECTOR(24) +- +-#define _VECTORS_SIZE 100 +- +- +-/* Constants */ +-#define SPM_PAGESIZE 256 +-#define RAMSTART (0x100) +-#define RAMEND 0x10FF +-#define XRAMEND RAMEND +-#define E2END 0x7FF +-#define E2PAGESIZE 8 +-#define FLASHEND 0xFFFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x96 +-#define SIGNATURE_2 0x06 +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_PIN_CHANGE0 +-#pragma GCC poison SIG_PIN_CHANGE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE2 +-#pragma GCC poison SIG_OVERFLOW2 +-#pragma GCC poison SIG_INPUT_CAPTURE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OUTPUT_COMPARE0 +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_SPI +-#pragma GCC poison USART0_RX_vect +-#pragma GCC poison SIG_UART_RECV +-#pragma GCC poison USART0_UDRE_vect +-#pragma GCC poison SIG_UART_DATA +-#pragma GCC poison USART_TX_vect +-#pragma GCC poison SIG_UART_TRANS +-#pragma GCC poison SIG_USI_START +-#pragma GCC poison SIG_USI_OVERFLOW +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_ADC +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_SPM_READY +-#pragma GCC poison SIG_PIN_CHANGE2 +-#pragma GCC poison SIG_PIN_CHANGE3 +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +-#endif /* _AVR_IOM6450_H_ */ ++/* Copyright (c) 2004,2005,2006 Eric B. Weddington ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom6450.h 2235 2011-03-17 04:13:14Z arcanum $ */ ++ ++/* avr/iom6450.h - definitions for ATmega6450 */ ++ ++#ifndef _AVR_IOM6450_H_ ++#define _AVR_IOM6450_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom6450.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE7 7 ++#define DDE6 6 ++#define DDE5 5 ++#define DDE4 4 ++#define DDE3 3 ++#define DDE2 2 ++#define DDE1 1 ++#define DDE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PE7 7 ++#define PE6 6 ++#define PE5 5 ++#define PE4 4 ++#define PE3 3 ++#define PE2 2 ++#define PE1 1 ++#define PE0 0 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDF7 7 ++#define DDF6 6 ++#define DDF5 5 ++#define DDF4 4 ++#define DDF3 3 ++#define DDF2 2 ++#define DDF1 1 ++#define DDF0 0 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PF7 7 ++#define PF6 6 ++#define PF5 5 ++#define PF4 4 ++#define PF3 3 ++#define PF2 2 ++#define PF1 1 ++#define PF0 0 ++ ++#define PING _SFR_IO8(0x12) ++#define PING5 5 ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++#define DDRG _SFR_IO8(0x13) ++#define DDG4 4 ++#define DDG3 3 ++#define DDG2 2 ++#define DDG1 1 ++#define DDG0 0 ++ ++#define PORTG _SFR_IO8(0x14) ++#define PG4 4 ++#define PG3 3 ++#define PG2 2 ++#define PG1 1 ++#define PG0 0 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++ ++/* Reserved [0x18..0x1B] */ ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define PCIF0 4 ++#define PCIF1 5 ++#define PCIF2 6 ++#define PCIF3 7 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define PCIE0 4 ++#define PCIE1 5 ++#define PCIE2 6 ++#define PCIE3 7 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++ ++#define EEDR _SFR_IO8(0X20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0X22) ++ ++/* 6-char sequence denoting where to find the EEPROM registers in memory space. ++ Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM ++ subroutines. ++ First two letters: EECR address. ++ Second two letters: EEDR address. ++ Last two letters: EEAR address. */ ++#define __EEPROM_REG_LOCATIONS__ 1F2021 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR10 0 ++#define PSR2 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM01 3 ++#define COM0A0 4 ++#define COM0A1 5 ++#define WGM00 6 ++#define FOC0A 7 ++ ++/* Reserved [0x25] */ ++ ++#define TCNT0 _SFR_IO8(0X26) ++ ++#define OCR0A _SFR_IO8(0X27) ++ ++/* Reserved [0x28..0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0X2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCDR7 7 ++#define IDRD 7 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define JTRF 4 ++ ++#define MCUCR _SFR_IO8(0X35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define JTD 7 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++/* SREG [0x3F] */ ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++ ++/* Reserved [0x67..0x68] */ ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++ ++/* Reserved [0x71..0x72] */ ++ ++#define PCMSK3 _SFR_MEM8(0x73) ++#define PCINT24 0 ++#define PCINT25 1 ++#define PCINT26 2 ++#define PCINT27 3 ++#define PCINT28 4 ++#define PCINT29 5 ++#define PCINT30 6 ++ ++/* Reserved [0x74..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0X80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0X81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM21 3 ++#define COM2A0 4 ++#define COM2A1 5 ++#define WGM20 6 ++#define FOC2A 7 ++ ++/* Reserved [0xB1] */ ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++/* Reserved [0xB4..0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2UB 0 ++#define OCR2UB 1 ++#define TCN2UB 2 ++#define AS2 3 ++#define EXCLK 4 ++ ++/* Reserved [0xB7] */ ++ ++#define USICR _SFR_MEM8(0xB8) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_MEM8(0xB9) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_MEM8(0xBA) ++ ++/* Reserved [0xBB..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0XC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL0 6 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0XC6) ++ ++/* Reserved [0xC7..0xD7] */ ++ ++#define PINH _SFR_MEM8(0xD8) ++#define PINH7 7 ++#define PINH6 6 ++#define PINH5 5 ++#define PINH4 4 ++#define PINH3 3 ++#define PINH2 2 ++#define PINH1 1 ++#define PINH0 0 ++ ++#define DDRH _SFR_MEM8(0xD9) ++#define DDH7 7 ++#define DDH6 6 ++#define DDH5 5 ++#define DDH4 4 ++#define DDH3 3 ++#define DDH2 2 ++#define DDH1 1 ++#define DDH0 0 ++ ++#define PORTH _SFR_MEM8(0xDA) ++#define PH7 7 ++#define PH6 6 ++#define PH5 5 ++#define PH4 4 ++#define PH3 3 ++#define PH2 2 ++#define PH1 1 ++#define PH0 0 ++ ++#define PINJ _SFR_MEM8(0xDB) ++#define PINJ6 6 ++#define PINJ5 5 ++#define PINJ4 4 ++#define PINJ3 3 ++#define PINJ2 2 ++#define PINJ1 1 ++#define PINJ0 0 ++ ++#define DDRJ _SFR_MEM8(0xDC) ++#define DDJ6 6 ++#define DDJ5 5 ++#define DDJ4 4 ++#define DDJ3 3 ++#define DDJ2 2 ++#define DDJ1 1 ++#define DDJ0 0 ++ ++#define PORTJ _SFR_MEM8(0xDD) ++#define PJ6 6 ++#define PJ5 5 ++#define PJ4 4 ++#define PJ3 3 ++#define PJ2 2 ++#define PJ1 1 ++#define PJ0 0 ++ ++/* Reserved [0xDE..0xFF] */ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) ++#define SIG_PIN_CHANGE0 _VECTOR(2) ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect_num 3 ++#define PCINT1_vect _VECTOR(3) ++#define SIG_PIN_CHANGE1 _VECTOR(3) ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect_num 4 ++#define TIMER2_COMP_vect _VECTOR(4) ++#define SIG_OUTPUT_COMPARE2 _VECTOR(4) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 5 ++#define TIMER2_OVF_vect _VECTOR(5) ++#define SIG_OVERFLOW2 _VECTOR(5) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 6 ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define SIG_INPUT_CAPTURE1 _VECTOR(6) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 7 ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(7) ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect_num 8 ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(8) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 9 ++#define TIMER1_OVF_vect _VECTOR(9) ++#define SIG_OVERFLOW1 _VECTOR(9) ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect_num 10 ++#define TIMER0_COMP_vect _VECTOR(10) ++#define SIG_OUTPUT_COMPARE0 _VECTOR(10) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 11 ++#define TIMER0_OVF_vect _VECTOR(11) ++#define SIG_OVERFLOW0 _VECTOR(11) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 12 ++#define SPI_STC_vect _VECTOR(12) ++#define SIG_SPI _VECTOR(12) ++ ++/* USART, Rx Complete */ ++#define USART_RX_vect_num 13 ++#define USART_RX_vect _VECTOR(13) ++#define USART0_RX_vect _VECTOR(13) /* Alias */ ++#define SIG_UART_RECV _VECTOR(13) ++ ++/* USART Data register Empty */ ++#define USART_UDRE_vect_num 14 ++#define USART_UDRE_vect _VECTOR(14) ++#define USART0_UDRE_vect _VECTOR(14) /* Alias */ ++#define SIG_UART_DATA _VECTOR(14) ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect_num 15 ++#define USART0_TX_vect _VECTOR(15) ++#define USART_TX_vect _VECTOR(15) /* Alias */ ++#define SIG_UART_TRANS _VECTOR(15) ++ ++/* USI Start Condition */ ++#define USI_START_vect_num 16 ++#define USI_START_vect _VECTOR(16) ++#define SIG_USI_START _VECTOR(16) ++ ++/* USI Overflow */ ++#define USI_OVERFLOW_vect_num 17 ++#define USI_OVERFLOW_vect _VECTOR(17) ++#define SIG_USI_OVERFLOW _VECTOR(17) ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect_num 18 ++#define ANALOG_COMP_vect _VECTOR(18) ++#define SIG_COMPARATOR _VECTOR(18) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 19 ++#define ADC_vect _VECTOR(19) ++#define SIG_ADC _VECTOR(19) ++ ++/* EEPROM Ready */ ++#define EE_READY_vect_num 20 ++#define EE_READY_vect _VECTOR(20) ++#define SIG_EEPROM_READY _VECTOR(20) ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect_num 21 ++#define SPM_READY_vect _VECTOR(21) ++#define SIG_SPM_READY _VECTOR(21) ++ ++/* Pin Change Interrupt Request 2 */ ++#define PCINT2_vect_num 23 ++#define PCINT2_vect _VECTOR(23) ++#define SIG_PIN_CHANGE2 _VECTOR(23) ++ ++/* Pin Change Interrupt Request 3 */ ++#define PCINT3_vect_num 24 ++#define PCINT3_vect _VECTOR(24) ++#define SIG_PIN_CHANGE3 _VECTOR(24) ++ ++#define _VECTORS_SIZE 100 ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE 256 ++#define RAMSTART (0x100) ++#define RAMEND 0x10FF ++#define XRAMEND RAMEND ++#define E2END 0x7FF ++#define E2PAGESIZE 8 ++#define FLASHEND 0xFFFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x06 ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_PIN_CHANGE0 ++#pragma GCC poison SIG_PIN_CHANGE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE2 ++#pragma GCC poison SIG_OVERFLOW2 ++#pragma GCC poison SIG_INPUT_CAPTURE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OUTPUT_COMPARE0 ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_SPI ++#pragma GCC poison USART0_RX_vect ++#pragma GCC poison SIG_UART_RECV ++#pragma GCC poison USART0_UDRE_vect ++#pragma GCC poison SIG_UART_DATA ++#pragma GCC poison USART_TX_vect ++#pragma GCC poison SIG_UART_TRANS ++#pragma GCC poison SIG_USI_START ++#pragma GCC poison SIG_USI_OVERFLOW ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_ADC ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_SPM_READY ++#pragma GCC poison SIG_PIN_CHANGE2 ++#pragma GCC poison SIG_PIN_CHANGE3 ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++#endif /* _AVR_IOM6450_H_ */ diff --git a/include/avr/iom6450a.h b/include/avr/iom6450a.h new file mode 100644 -index 0000000..3e477fc +index 0000000..776f150 --- /dev/null +++ b/include/avr/iom6450a.h @@ -0,0 +1,34 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2011 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+#include "iom6450.h" ++/***************************************************************************** ++ * ++ * Copyright (C) 2011 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++#include "iom6450.h" diff --git a/include/avr/iom6450p.h b/include/avr/iom6450p.h new file mode 100644 -index 0000000..3e477fc +index 0000000..776f150 --- /dev/null +++ b/include/avr/iom6450p.h @@ -0,0 +1,34 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2011 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+#include "iom6450.h" ++/***************************************************************************** ++ * ++ * Copyright (C) 2011 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++#include "iom6450.h" diff --git a/include/avr/iom645a.h b/include/avr/iom645a.h new file mode 100644 -index 0000000..cf01653 +index 0000000..d2e4419 --- /dev/null +++ b/include/avr/iom645a.h @@ -0,0 +1,34 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2011 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+#include "iom645.h" ++/***************************************************************************** ++ * ++ * Copyright (C) 2011 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++#include "iom645.h" diff --git a/include/avr/iom645p.h b/include/avr/iom645p.h new file mode 100644 -index 0000000..cf01653 +index 0000000..d2e4419 --- /dev/null +++ b/include/avr/iom645p.h @@ -0,0 +1,34 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2011 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+#include "iom645.h" ++/***************************************************************************** ++ * ++ * Copyright (C) 2011 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++#include "iom645.h" +diff --git a/include/avr/iom649.h b/include/avr/iom649.h +index 8153ccd..7422159 100644 +--- a/include/avr/iom649.h ++++ b/include/avr/iom649.h +@@ -1,1048 +1,1049 @@ +-/* Copyright (c) 2004 Eric B. Weddington +- Copyright (c) 2005,2006 Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* avr/iom649.h - definitions for ATmega649 */ +- +-#ifndef _AVR_IOM649_H_ +-#define _AVR_IOM649_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom649.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* Registers and associated bit numbers */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-#define PORTA _SFR_IO8(0x02) +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-#define PINB _SFR_IO8(0x03) +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-#define PORTB _SFR_IO8(0x05) +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-#define PORTC _SFR_IO8(0x08) +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-#define PINE _SFR_IO8(0x0C) +-#define PINE7 7 +-#define PINE6 6 +-#define PINE5 5 +-#define PINE4 4 +-#define PINE3 3 +-#define PINE2 2 +-#define PINE1 1 +-#define PINE0 0 +- +-#define DDRE _SFR_IO8(0x0D) +-#define DDE7 7 +-#define DDE6 6 +-#define DDE5 5 +-#define DDE4 4 +-#define DDE3 3 +-#define DDE2 2 +-#define DDE1 1 +-#define DDE0 0 +- +-#define PORTE _SFR_IO8(0x0E) +-#define PE7 7 +-#define PE6 6 +-#define PE5 5 +-#define PE4 4 +-#define PE3 3 +-#define PE2 2 +-#define PE1 1 +-#define PE0 0 +- +-#define PINF _SFR_IO8(0x0F) +-#define PINF7 7 +-#define PINF6 6 +-#define PINF5 5 +-#define PINF4 4 +-#define PINF3 3 +-#define PINF2 2 +-#define PINF1 1 +-#define PINF0 0 +- +-#define DDRF _SFR_IO8(0x10) +-#define DDF7 7 +-#define DDF6 6 +-#define DDF5 5 +-#define DDF4 4 +-#define DDF3 3 +-#define DDF2 2 +-#define DDF1 1 +-#define DDF0 0 +- +-#define PORTF _SFR_IO8(0x11) +-#define PF7 7 +-#define PF6 6 +-#define PF5 5 +-#define PF4 4 +-#define PF3 3 +-#define PF2 2 +-#define PF1 1 +-#define PF0 0 +- +-#define PING _SFR_IO8(0x12) +-#define PING5 5 +-#define PING4 4 +-#define PING3 3 +-#define PING2 2 +-#define PING1 1 +-#define PING0 0 +- +-#define DDRG _SFR_IO8(0x13) +-#define DDG4 4 +-#define DDG3 3 +-#define DDG2 2 +-#define DDG1 1 +-#define DDG0 0 +- +-#define PORTG _SFR_IO8(0x14) +-#define PG4 4 +-#define PG3 3 +-#define PG2 2 +-#define PG1 1 +-#define PG0 0 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define TIFR2 _SFR_IO8(0x17) +-#define TOV2 0 +-#define OCF2A 1 +- +-/* Reserved [0x18..0x1B] */ +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define PCIF0 4 +-#define PCIF1 5 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define PCIE0 4 +-#define PCIE1 5 +- +-#define GPIOR0 _SFR_IO8(0x1E) +- +-#define EECR _SFR_IO8(0x1F) +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-#define EEDR _SFR_IO8(0X20) +- +-/* Combine EEARL and EEARH */ +-#define EEAR _SFR_IO16(0x21) +-#define EEARL _SFR_IO8(0x21) +-#define EEARH _SFR_IO8(0X22) +- +-/* 6-char sequence denoting where to find the EEPROM registers in memory space. +- Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM +- subroutines. +- First two letters: EECR address. +- Second two letters: EEDR address. +- Last two letters: EEAR address. */ +-#define __EEPROM_REG_LOCATIONS__ 1F2021 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSR10 0 +-#define PSR2 1 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM01 3 +-#define COM0A0 4 +-#define COM0A1 5 +-#define WGM00 6 +-#define FOC0A 7 +- +-/* Reserved [0x25] */ +- +-#define TCNT0 _SFR_IO8(0X26) +- +-#define OCR0A _SFR_IO8(0X27) +- +-/* Reserved [0x28..0x29] */ +- +-#define GPIOR1 _SFR_IO8(0x2A) +- +-#define GPIOR2 _SFR_IO8(0x2B) +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0X2E) +- +-/* Reserved [0x2F] */ +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define OCDR _SFR_IO8(0x31) +-#define OCDR0 0 +-#define OCDR1 1 +-#define OCDR2 2 +-#define OCDR3 3 +-#define OCDR4 4 +-#define OCDR5 5 +-#define OCDR6 6 +-#define OCDR7 7 +-#define IDRD 7 +- +-/* Reserved [0x32] */ +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +-#define JTRF 4 +- +-#define MCUCR _SFR_IO8(0X35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define JTD 7 +- +-/* Reserved [0x36] */ +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define RWWSB 6 +-#define SPMIE 7 +- +-/* Reserved [0x38..0x3C] */ +- +-/* SP [0x3D..0x3E] */ +-/* SREG [0x3F] */ +- +-#define WDTCR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-/* Reserved [0x62..0x63] */ +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM1 3 +-#define PRLCD 4 +- +-/* Reserved [0x65] */ +- +-#define OSCCAL _SFR_MEM8(0x66) +- +-/* Reserved [0x67..0x68] */ +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +- +-/* Reserved [0x6A] */ +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-/* Reserved [0x6D] */ +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define TIMSK2 _SFR_MEM8(0x70) +-#define TOIE2 0 +-#define OCIE2A 1 +- +-/* Reserved [0x71..0x77] */ +- +-/* Combine ADCL and ADCH */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +-#define ADCL _SFR_MEM8(0x78) +-#define ADCH _SFR_MEM8(0x79) +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ACME 6 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-/* Reserved [0x7D] */ +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0X80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0X81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-/* Reserved [0x83] */ +- +-/* Combine TCNT1L and TCNT1H */ +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1H _SFR_MEM8(0x85) +- +-/* Combine ICR1L and ICR1H */ +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1H _SFR_MEM8(0x87) +- +-/* Combine OCR1AL and OCR1AH */ +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AH _SFR_MEM8(0x89) +- +-/* Combine OCR1BL and OCR1BH */ +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BH _SFR_MEM8(0x8B) +- +-/* Reserved [0x8C..0xAF] */ +- +-#define TCCR2A _SFR_MEM8(0xB0) +-#define CS20 0 +-#define CS21 1 +-#define CS22 2 +-#define WGM21 3 +-#define COM2A0 4 +-#define COM2A1 5 +-#define WGM20 6 +-#define FOC2A 7 +- +-/* Reserved [0xB1] */ +- +-#define TCNT2 _SFR_MEM8(0xB2) +- +-#define OCR2A _SFR_MEM8(0xB3) +- +-/* Reserved [0xB4..0xB5] */ +- +-#define ASSR _SFR_MEM8(0xB6) +-#define TCR2UB 0 +-#define OCR2UB 1 +-#define TCN2UB 2 +-#define AS2 3 +-#define EXCLK 4 +- +-/* Reserved [0xB7] */ +- +-#define USICR _SFR_MEM8(0xB8) +-#define USITC 0 +-#define USICLK 1 +-#define USICS0 2 +-#define USICS1 3 +-#define USIWM0 4 +-#define USIWM1 5 +-#define USIOIE 6 +-#define USISIE 7 +- +-#define USISR _SFR_MEM8(0xB9) +-#define USICNT0 0 +-#define USICNT1 1 +-#define USICNT2 2 +-#define USICNT3 3 +-#define USIDC 4 +-#define USIPF 5 +-#define USIOIF 6 +-#define USISIF 7 +- +-#define USIDR _SFR_MEM8(0xBA) +- +-/* Reserved [0xBB..0xBF] */ +- +-#define UCSR0A _SFR_MEM8(0xC0) +-#define MPCM0 0 +-#define U2X0 1 +-#define UPE0 2 +-#define DOR0 3 +-#define FE0 4 +-#define UDRE0 5 +-#define TXC0 6 +-#define RXC0 7 +- +-#define UCSR0B _SFR_MEM8(0XC1) +-#define TXB80 0 +-#define RXB80 1 +-#define UCSZ02 2 +-#define TXEN0 3 +-#define RXEN0 4 +-#define UDRIE0 5 +-#define TXCIE0 6 +-#define RXCIE0 7 +- +-#define UCSR0C _SFR_MEM8(0xC2) +-#define UCPOL0 0 +-#define UCSZ00 1 +-#define UCSZ01 2 +-#define USBS0 3 +-#define UPM00 4 +-#define UPM01 5 +-#define UMSEL0 6 +- +-/* Reserved [0xC3] */ +- +-/* Combine UBRR0L and UBRR0H */ +-#define UBRR0 _SFR_MEM16(0xC4) +- +-#define UBRR0L _SFR_MEM8(0xC4) +-#define UBRR0H _SFR_MEM8(0xC5) +- +-#define UDR0 _SFR_MEM8(0XC6) +- +-/* Reserved [0xC7..0xE3] */ +- +-#define LCDCRA _SFR_MEM8(0XE4) +-#define LCDBL 0 +-#define LCDIE 3 +-#define LCDIF 4 +-#define LCDAB 6 +-#define LCDEN 7 +- +-#define LCDCRB _SFR_MEM8(0XE5) +-#define LCDPM0 0 +-#define LCDPM1 1 +-#define LCDPM2 2 +-#define LCDMUX0 4 +-#define LCDMUX1 5 +-#define LCD2B 6 +-#define LCDCS 7 +- +-#define LCDFRR _SFR_MEM8(0XE6) +-#define LCDCD0 0 +-#define LCDCD1 1 +-#define LCDCD2 2 +-#define LCDPS0 4 +-#define LCDPS1 5 +-#define LCDPS2 6 +- +-#define LCDCCR _SFR_MEM8(0XE7) +-#define LCDCC0 0 +-#define LCDCC1 1 +-#define LCDCC2 2 +-#define LCDCC3 3 +-#define LCDDC0 5 +-#define LCDDC1 6 +-#define LCDDC2 7 +- +-/* Reserved [0xE8..0xEB] */ +- +-#define LCDDR00 _SFR_MEM8(0XEC) +-#define SEG000 0 +-#define SEG001 1 +-#define SEG002 2 +-#define SEG003 3 +-#define SEG004 4 +-#define SEG005 5 +-#define SEG006 6 +-#define SEG007 7 +- +-#define LCDDR01 _SFR_MEM8(0XED) +-#define SEG008 0 +-#define SEG009 1 +-#define SEG010 2 +-#define SEG011 3 +-#define SEG012 4 +-#define SEG013 5 +-#define SEG014 6 +-#define SEG015 7 +- +-#define LCDDR02 _SFR_MEM8(0XEE) +-#define SEG016 0 +-#define SEG017 1 +-#define SEG018 2 +-#define SEG019 3 +-#define SEG020 4 +-#define SEG021 5 +-#define SEG022 6 +-#define SEG023 7 +- +-#define LCDDR03 _SFR_MEM8(0XEF) +-#define SEG024 0 +- +-/* Reserved [0xF0] */ +- +-#define LCDDR05 _SFR_MEM8(0XF1) +-#define SEG100 0 +-#define SEG101 1 +-#define SEG102 2 +-#define SEG103 3 +-#define SEG104 4 +-#define SEG105 5 +-#define SEG106 6 +-#define SEG107 7 +- +-#define LCDDR06 _SFR_MEM8(0XF2) +-#define SEG108 0 +-#define SEG109 1 +-#define SEG110 2 +-#define SEG111 3 +-#define SEG112 4 +-#define SEG113 5 +-#define SEG114 6 +-#define SEG115 7 +- +-#define LCDDR07 _SFR_MEM8(0XF3) +-#define SEG116 0 +-#define SEG117 1 +-#define SEG118 2 +-#define SEG119 3 +-#define SEG120 4 +-#define SEG121 5 +-#define SEG122 6 +-#define SEG123 7 +- +-#define LCDDR08 _SFR_MEM8(0XF4) +-#define SEG124 0 +- +-/* Reserved [0xF5] */ +- +-#define LCDDR10 _SFR_MEM8(0XF6) +-#define SEG200 0 +-#define SEG201 1 +-#define SEG202 2 +-#define SEG203 3 +-#define SEG204 4 +-#define SEG205 5 +-#define SEG206 6 +-#define SEG207 7 +- +-#define LCDDR11 _SFR_MEM8(0XF7) +-#define SEG208 0 +-#define SEG209 1 +-#define SEG210 2 +-#define SEG211 3 +-#define SEG212 4 +-#define SEG213 5 +-#define SEG214 6 +-#define SEG215 7 +- +-#define LCDDR12 _SFR_MEM8(0XF8) +-#define SEG216 0 +-#define SEG217 1 +-#define SEG218 2 +-#define SEG219 3 +-#define SEG220 4 +-#define SEG221 5 +-#define SEG222 6 +-#define SEG223 7 +- +-#define LCDDR13 _SFR_MEM8(0XF9) +-#define SEG224 0 +- +-/* Reserved [0xFA] */ +- +-#define LCDDR15 _SFR_MEM8(0XFB) +-#define SEG300 0 +-#define SEG301 1 +-#define SEG302 2 +-#define SEG303 3 +-#define SEG304 4 +-#define SEG305 5 +-#define SEG306 6 +-#define SEG307 7 +- +-#define LCDDR16 _SFR_MEM8(0XFC) +-#define SEG308 0 +-#define SEG309 1 +-#define SEG310 2 +-#define SEG311 3 +-#define SEG312 4 +-#define SEG313 5 +-#define SEG314 6 +-#define SEG315 7 +- +-#define LCDDR17 _SFR_MEM8(0XFD) +-#define SEG316 0 +-#define SEG217 1 +-#define SEG318 2 +-#define SEG319 3 +-#define SEG320 4 +-#define SEG321 5 +-#define SEG322 6 +-#define SEG323 7 +- +-#define LCDDR18 _SFR_MEM8(0XFE) +-#define SEG324 0 +- +-/* Reserved [0xFF] */ +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* Pin Change Interrupt Request 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) +-#define SIG_PIN_CHANGE0 _VECTOR(2) +- +-/* Pin Change Interrupt Request 1 */ +-#define PCINT1_vect_num 3 +-#define PCINT1_vect _VECTOR(3) +-#define SIG_PIN_CHANGE1 _VECTOR(3) +- +-/* Timer/Counter2 Compare Match */ +-#define TIMER2_COMP_vect_num 4 +-#define TIMER2_COMP_vect _VECTOR(4) +-#define SIG_OUTPUT_COMPARE2 _VECTOR(4) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 5 +-#define TIMER2_OVF_vect _VECTOR(5) +-#define SIG_OVERFLOW2 _VECTOR(5) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 6 +-#define TIMER1_CAPT_vect _VECTOR(6) +-#define SIG_INPUT_CAPTURE1 _VECTOR(6) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 7 +-#define TIMER1_COMPA_vect _VECTOR(7) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(7) +- +-/* Timer/Counter Compare Match B */ +-#define TIMER1_COMPB_vect_num 8 +-#define TIMER1_COMPB_vect _VECTOR(8) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(8) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 9 +-#define TIMER1_OVF_vect _VECTOR(9) +-#define SIG_OVERFLOW1 _VECTOR(9) +- +-/* Timer/Counter0 Compare Match */ +-#define TIMER0_COMP_vect_num 10 +-#define TIMER0_COMP_vect _VECTOR(10) +-#define SIG_OUTPUT_COMPARE0 _VECTOR(10) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 11 +-#define TIMER0_OVF_vect _VECTOR(11) +-#define SIG_OVERFLOW0 _VECTOR(11) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 12 +-#define SPI_STC_vect _VECTOR(12) +-#define SIG_SPI _VECTOR(12) +- +-/* USART0, Rx Complete */ +-#define USART0_RX_vect_num 13 +-#define USART0_RX_vect _VECTOR(13) +-#define SIG_UART_RECV _VECTOR(13) +- +-/* USART0 Data register Empty */ +-#define USART0_UDRE_vect_num 14 +-#define USART0_UDRE_vect _VECTOR(14) +-#define SIG_UART_DATA _VECTOR(14) +- +-/* USART0, Tx Complete */ +-#define USART0_TX_vect_num 15 +-#define USART0_TX_vect _VECTOR(15) +-#define SIG_UART_TRANS _VECTOR(15) +- +-/* USI Start Condition */ +-#define USI_START_vect_num 16 +-#define USI_START_vect _VECTOR(16) +-#define SIG_USI_START _VECTOR(16) +- +-/* USI Overflow */ +-#define USI_OVERFLOW_vect_num 17 +-#define USI_OVERFLOW_vect _VECTOR(17) +-#define SIG_USI_OVERFLOW _VECTOR(17) +- +-/* Analog Comparator */ +-#define ANALOG_COMP_vect_num 18 +-#define ANALOG_COMP_vect _VECTOR(18) +-#define SIG_COMPARATOR _VECTOR(18) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 19 +-#define ADC_vect _VECTOR(19) +-#define SIG_ADC _VECTOR(19) +- +-/* EEPROM Ready */ +-#define EE_READY_vect_num 20 +-#define EE_READY_vect _VECTOR(20) +-#define SIG_EEPROM_READY _VECTOR(20) +- +-/* Store Program Memory Read */ +-#define SPM_READY_vect_num 21 +-#define SPM_READY_vect _VECTOR(21) +-#define SIG_SPM_READY _VECTOR(21) +- +-/* LCD Start of Frame */ +-#define LCD_vect_num 22 +-#define LCD_vect _VECTOR(22) +-#define SIG_LCD _VECTOR(22) +- +-#define _VECTORS_SIZE 92 +- +- +-/* Constants */ +-#define SPM_PAGESIZE 256 +-#define RAMEND 0x10FF +-#define XRAMEND RAMEND +-#define E2END 0x7FF +-#define E2PAGESIZE 8 +-#define FLASHEND 0xFFFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x96 +-#define SIGNATURE_2 0x03 +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_PIN_CHANGE0 +-#pragma GCC poison SIG_PIN_CHANGE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE2 +-#pragma GCC poison SIG_OVERFLOW2 +-#pragma GCC poison SIG_INPUT_CAPTURE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OUTPUT_COMPARE0 +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_SPI +-#pragma GCC poison SIG_UART_RECV +-#pragma GCC poison SIG_UART_DATA +-#pragma GCC poison SIG_UART_TRANS +-#pragma GCC poison SIG_USI_START +-#pragma GCC poison SIG_USI_OVERFLOW +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_ADC +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_SPM_READY +-#pragma GCC poison SIG_LCD +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +- +- +-#endif /* _AVR_IOM649_H_ */ ++/* Copyright (c) 2004 Eric B. Weddington ++ Copyright (c) 2005,2006 Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* avr/iom649.h - definitions for ATmega649 */ ++ ++#ifndef _AVR_IOM649_H_ ++#define _AVR_IOM649_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom649.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE7 7 ++#define DDE6 6 ++#define DDE5 5 ++#define DDE4 4 ++#define DDE3 3 ++#define DDE2 2 ++#define DDE1 1 ++#define DDE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PE7 7 ++#define PE6 6 ++#define PE5 5 ++#define PE4 4 ++#define PE3 3 ++#define PE2 2 ++#define PE1 1 ++#define PE0 0 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDF7 7 ++#define DDF6 6 ++#define DDF5 5 ++#define DDF4 4 ++#define DDF3 3 ++#define DDF2 2 ++#define DDF1 1 ++#define DDF0 0 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PF7 7 ++#define PF6 6 ++#define PF5 5 ++#define PF4 4 ++#define PF3 3 ++#define PF2 2 ++#define PF1 1 ++#define PF0 0 ++ ++#define PING _SFR_IO8(0x12) ++#define PING5 5 ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++#define DDRG _SFR_IO8(0x13) ++#define DDG4 4 ++#define DDG3 3 ++#define DDG2 2 ++#define DDG1 1 ++#define DDG0 0 ++ ++#define PORTG _SFR_IO8(0x14) ++#define PG4 4 ++#define PG3 3 ++#define PG2 2 ++#define PG1 1 ++#define PG0 0 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++ ++/* Reserved [0x18..0x1B] */ ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define PCIF0 4 ++#define PCIF1 5 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define PCIE0 4 ++#define PCIE1 5 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++#define EEDR _SFR_IO8(0X20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0X22) ++ ++/* 6-char sequence denoting where to find the EEPROM registers in memory space. ++ Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM ++ subroutines. ++ First two letters: EECR address. ++ Second two letters: EEDR address. ++ Last two letters: EEAR address. */ ++#define __EEPROM_REG_LOCATIONS__ 1F2021 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR10 0 ++#define PSR2 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM01 3 ++#define COM0A0 4 ++#define COM0A1 5 ++#define WGM00 6 ++#define FOC0A 7 ++ ++/* Reserved [0x25] */ ++ ++#define TCNT0 _SFR_IO8(0X26) ++ ++#define OCR0A _SFR_IO8(0X27) ++ ++/* Reserved [0x28..0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0X2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCDR7 7 ++#define IDRD 7 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define JTRF 4 ++ ++#define MCUCR _SFR_IO8(0X35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define JTD 7 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++/* SREG [0x3F] */ ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRLCD 4 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++ ++/* Reserved [0x67..0x68] */ ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++/* Reserved [0x6D] */ ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++ ++/* Reserved [0x71..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0X80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0X81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM21 3 ++#define COM2A0 4 ++#define COM2A1 5 ++#define WGM20 6 ++#define FOC2A 7 ++ ++/* Reserved [0xB1] */ ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++/* Reserved [0xB4..0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2UB 0 ++#define OCR2UB 1 ++#define TCN2UB 2 ++#define AS2 3 ++#define EXCLK 4 ++ ++/* Reserved [0xB7] */ ++ ++#define USICR _SFR_MEM8(0xB8) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_MEM8(0xB9) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_MEM8(0xBA) ++ ++/* Reserved [0xBB..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0XC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL0 6 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0XC6) ++ ++/* Reserved [0xC7..0xE3] */ ++ ++#define LCDCRA _SFR_MEM8(0XE4) ++#define LCDBL 0 ++#define LCDIE 3 ++#define LCDIF 4 ++#define LCDAB 6 ++#define LCDEN 7 ++ ++#define LCDCRB _SFR_MEM8(0XE5) ++#define LCDPM0 0 ++#define LCDPM1 1 ++#define LCDPM2 2 ++#define LCDMUX0 4 ++#define LCDMUX1 5 ++#define LCD2B 6 ++#define LCDCS 7 ++ ++#define LCDFRR _SFR_MEM8(0XE6) ++#define LCDCD0 0 ++#define LCDCD1 1 ++#define LCDCD2 2 ++#define LCDPS0 4 ++#define LCDPS1 5 ++#define LCDPS2 6 ++ ++#define LCDCCR _SFR_MEM8(0XE7) ++#define LCDCC0 0 ++#define LCDCC1 1 ++#define LCDCC2 2 ++#define LCDCC3 3 ++#define LCDDC0 5 ++#define LCDDC1 6 ++#define LCDDC2 7 ++ ++/* Reserved [0xE8..0xEB] */ ++ ++#define LCDDR00 _SFR_MEM8(0XEC) ++#define SEG000 0 ++#define SEG001 1 ++#define SEG002 2 ++#define SEG003 3 ++#define SEG004 4 ++#define SEG005 5 ++#define SEG006 6 ++#define SEG007 7 ++ ++#define LCDDR01 _SFR_MEM8(0XED) ++#define SEG008 0 ++#define SEG009 1 ++#define SEG010 2 ++#define SEG011 3 ++#define SEG012 4 ++#define SEG013 5 ++#define SEG014 6 ++#define SEG015 7 ++ ++#define LCDDR02 _SFR_MEM8(0XEE) ++#define SEG016 0 ++#define SEG017 1 ++#define SEG018 2 ++#define SEG019 3 ++#define SEG020 4 ++#define SEG021 5 ++#define SEG022 6 ++#define SEG023 7 ++ ++#define LCDDR03 _SFR_MEM8(0XEF) ++#define SEG024 0 ++ ++/* Reserved [0xF0] */ ++ ++#define LCDDR05 _SFR_MEM8(0XF1) ++#define SEG100 0 ++#define SEG101 1 ++#define SEG102 2 ++#define SEG103 3 ++#define SEG104 4 ++#define SEG105 5 ++#define SEG106 6 ++#define SEG107 7 ++ ++#define LCDDR06 _SFR_MEM8(0XF2) ++#define SEG108 0 ++#define SEG109 1 ++#define SEG110 2 ++#define SEG111 3 ++#define SEG112 4 ++#define SEG113 5 ++#define SEG114 6 ++#define SEG115 7 ++ ++#define LCDDR07 _SFR_MEM8(0XF3) ++#define SEG116 0 ++#define SEG117 1 ++#define SEG118 2 ++#define SEG119 3 ++#define SEG120 4 ++#define SEG121 5 ++#define SEG122 6 ++#define SEG123 7 ++ ++#define LCDDR08 _SFR_MEM8(0XF4) ++#define SEG124 0 ++ ++/* Reserved [0xF5] */ ++ ++#define LCDDR10 _SFR_MEM8(0XF6) ++#define SEG200 0 ++#define SEG201 1 ++#define SEG202 2 ++#define SEG203 3 ++#define SEG204 4 ++#define SEG205 5 ++#define SEG206 6 ++#define SEG207 7 ++ ++#define LCDDR11 _SFR_MEM8(0XF7) ++#define SEG208 0 ++#define SEG209 1 ++#define SEG210 2 ++#define SEG211 3 ++#define SEG212 4 ++#define SEG213 5 ++#define SEG214 6 ++#define SEG215 7 ++ ++#define LCDDR12 _SFR_MEM8(0XF8) ++#define SEG216 0 ++#define SEG217 1 ++#define SEG218 2 ++#define SEG219 3 ++#define SEG220 4 ++#define SEG221 5 ++#define SEG222 6 ++#define SEG223 7 ++ ++#define LCDDR13 _SFR_MEM8(0XF9) ++#define SEG224 0 ++ ++/* Reserved [0xFA] */ ++ ++#define LCDDR15 _SFR_MEM8(0XFB) ++#define SEG300 0 ++#define SEG301 1 ++#define SEG302 2 ++#define SEG303 3 ++#define SEG304 4 ++#define SEG305 5 ++#define SEG306 6 ++#define SEG307 7 ++ ++#define LCDDR16 _SFR_MEM8(0XFC) ++#define SEG308 0 ++#define SEG309 1 ++#define SEG310 2 ++#define SEG311 3 ++#define SEG312 4 ++#define SEG313 5 ++#define SEG314 6 ++#define SEG315 7 ++ ++#define LCDDR17 _SFR_MEM8(0XFD) ++#define SEG316 0 ++#define SEG217 1 ++#define SEG318 2 ++#define SEG319 3 ++#define SEG320 4 ++#define SEG321 5 ++#define SEG322 6 ++#define SEG323 7 ++ ++#define LCDDR18 _SFR_MEM8(0XFE) ++#define SEG324 0 ++ ++/* Reserved [0xFF] */ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) ++#define SIG_PIN_CHANGE0 _VECTOR(2) ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect_num 3 ++#define PCINT1_vect _VECTOR(3) ++#define SIG_PIN_CHANGE1 _VECTOR(3) ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect_num 4 ++#define TIMER2_COMP_vect _VECTOR(4) ++#define SIG_OUTPUT_COMPARE2 _VECTOR(4) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 5 ++#define TIMER2_OVF_vect _VECTOR(5) ++#define SIG_OVERFLOW2 _VECTOR(5) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 6 ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define SIG_INPUT_CAPTURE1 _VECTOR(6) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 7 ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(7) ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect_num 8 ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(8) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 9 ++#define TIMER1_OVF_vect _VECTOR(9) ++#define SIG_OVERFLOW1 _VECTOR(9) ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect_num 10 ++#define TIMER0_COMP_vect _VECTOR(10) ++#define SIG_OUTPUT_COMPARE0 _VECTOR(10) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 11 ++#define TIMER0_OVF_vect _VECTOR(11) ++#define SIG_OVERFLOW0 _VECTOR(11) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 12 ++#define SPI_STC_vect _VECTOR(12) ++#define SIG_SPI _VECTOR(12) ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect_num 13 ++#define USART0_RX_vect _VECTOR(13) ++#define SIG_UART_RECV _VECTOR(13) ++ ++/* USART0 Data register Empty */ ++#define USART0_UDRE_vect_num 14 ++#define USART0_UDRE_vect _VECTOR(14) ++#define SIG_UART_DATA _VECTOR(14) ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect_num 15 ++#define USART0_TX_vect _VECTOR(15) ++#define SIG_UART_TRANS _VECTOR(15) ++ ++/* USI Start Condition */ ++#define USI_START_vect_num 16 ++#define USI_START_vect _VECTOR(16) ++#define SIG_USI_START _VECTOR(16) ++ ++/* USI Overflow */ ++#define USI_OVERFLOW_vect_num 17 ++#define USI_OVERFLOW_vect _VECTOR(17) ++#define SIG_USI_OVERFLOW _VECTOR(17) ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect_num 18 ++#define ANALOG_COMP_vect _VECTOR(18) ++#define SIG_COMPARATOR _VECTOR(18) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 19 ++#define ADC_vect _VECTOR(19) ++#define SIG_ADC _VECTOR(19) ++ ++/* EEPROM Ready */ ++#define EE_READY_vect_num 20 ++#define EE_READY_vect _VECTOR(20) ++#define SIG_EEPROM_READY _VECTOR(20) ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect_num 21 ++#define SPM_READY_vect _VECTOR(21) ++#define SIG_SPM_READY _VECTOR(21) ++ ++/* LCD Start of Frame */ ++#define LCD_vect_num 22 ++#define LCD_vect _VECTOR(22) ++#define SIG_LCD _VECTOR(22) ++ ++#define _VECTORS_SIZE 92 ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE 256 ++#define RAMSTART 0x100 ++#define RAMEND 0x10FF ++#define XRAMEND RAMEND ++#define E2END 0x7FF ++#define E2PAGESIZE 8 ++#define FLASHEND 0xFFFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x03 ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_PIN_CHANGE0 ++#pragma GCC poison SIG_PIN_CHANGE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE2 ++#pragma GCC poison SIG_OVERFLOW2 ++#pragma GCC poison SIG_INPUT_CAPTURE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OUTPUT_COMPARE0 ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_SPI ++#pragma GCC poison SIG_UART_RECV ++#pragma GCC poison SIG_UART_DATA ++#pragma GCC poison SIG_UART_TRANS ++#pragma GCC poison SIG_USI_START ++#pragma GCC poison SIG_USI_OVERFLOW ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_ADC ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_SPM_READY ++#pragma GCC poison SIG_LCD ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++ ++ ++#endif /* _AVR_IOM649_H_ */ +diff --git a/include/avr/iom6490.h b/include/avr/iom6490.h +index 66dd4b0..bbca146 100644 +--- a/include/avr/iom6490.h ++++ b/include/avr/iom6490.h +@@ -1,1169 +1,1170 @@ +-/* Copyright (c) 2004 Eric B. Weddington +- Copyright (c) 2005,2006 Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* avr/iom6490.h - definitions for ATmega6490 */ +- +-#ifndef _AVR_IOM6490_H_ +-#define _AVR_IOM6490_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom6490.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* Registers and associated bit numbers */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-#define PORTA _SFR_IO8(0x02) +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-#define PINB _SFR_IO8(0x03) +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-#define PORTB _SFR_IO8(0x05) +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-#define PORTC _SFR_IO8(0x08) +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-#define PINE _SFR_IO8(0x0C) +-#define PINE7 7 +-#define PINE6 6 +-#define PINE5 5 +-#define PINE4 4 +-#define PINE3 3 +-#define PINE2 2 +-#define PINE1 1 +-#define PINE0 0 +- +-#define DDRE _SFR_IO8(0x0D) +-#define DDE7 7 +-#define DDE6 6 +-#define DDE5 5 +-#define DDE4 4 +-#define DDE3 3 +-#define DDE2 2 +-#define DDE1 1 +-#define DDE0 0 +- +-#define PORTE _SFR_IO8(0x0E) +-#define PE7 7 +-#define PE6 6 +-#define PE5 5 +-#define PE4 4 +-#define PE3 3 +-#define PE2 2 +-#define PE1 1 +-#define PE0 0 +- +-#define PINF _SFR_IO8(0x0F) +-#define PINF7 7 +-#define PINF6 6 +-#define PINF5 5 +-#define PINF4 4 +-#define PINF3 3 +-#define PINF2 2 +-#define PINF1 1 +-#define PINF0 0 +- +-#define DDRF _SFR_IO8(0x10) +-#define DDF7 7 +-#define DDF6 6 +-#define DDF5 5 +-#define DDF4 4 +-#define DDF3 3 +-#define DDF2 2 +-#define DDF1 1 +-#define DDF0 0 +- +-#define PORTF _SFR_IO8(0x11) +-#define PF7 7 +-#define PF6 6 +-#define PF5 5 +-#define PF4 4 +-#define PF3 3 +-#define PF2 2 +-#define PF1 1 +-#define PF0 0 +- +-#define PING _SFR_IO8(0x12) +-#define PING5 5 +-#define PING4 4 +-#define PING3 3 +-#define PING2 2 +-#define PING1 1 +-#define PING0 0 +- +-#define DDRG _SFR_IO8(0x13) +-#define DDG4 4 +-#define DDG3 3 +-#define DDG2 2 +-#define DDG1 1 +-#define DDG0 0 +- +-#define PORTG _SFR_IO8(0x14) +-#define PG4 4 +-#define PG3 3 +-#define PG2 2 +-#define PG1 1 +-#define PG0 0 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define TIFR2 _SFR_IO8(0x17) +-#define TOV2 0 +-#define OCF2A 1 +- +-/* Reserved [0x18..0x1B] */ +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define PCIF0 4 +-#define PCIF1 5 +-#define PCIF2 6 +-#define PCIF3 7 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define PCIE0 4 +-#define PCIE1 5 +-#define PCIE2 6 +-#define PCIE3 7 +- +-#define GPIOR0 _SFR_IO8(0x1E) +- +-#define EECR _SFR_IO8(0x1F) +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-#define EEDR _SFR_IO8(0X20) +- +-/* Combine EEARL and EEARH */ +-#define EEAR _SFR_IO16(0x21) +-#define EEARL _SFR_IO8(0x21) +-#define EEARH _SFR_IO8(0X22) +- +-/* 6-char sequence denoting where to find the EEPROM registers in memory space. +- Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM +- subroutines. +- First two letters: EECR address. +- Second two letters: EEDR address. +- Last two letters: EEAR address. */ +-#define __EEPROM_REG_LOCATIONS__ 1F2021 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSR10 0 +-#define PSR2 1 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM01 3 +-#define COM0A0 4 +-#define COM0A1 5 +-#define WGM00 6 +-#define FOC0A 7 +- +-/* Reserved [0x25] */ +- +-#define TCNT0 _SFR_IO8(0X26) +- +-#define OCR0A _SFR_IO8(0X27) +- +-/* Reserved [0x28..0x29] */ +- +-#define GPIOR1 _SFR_IO8(0x2A) +- +-#define GPIOR2 _SFR_IO8(0x2B) +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0X2E) +- +-/* Reserved [0x2F] */ +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define OCDR _SFR_IO8(0x31) +-#define OCDR0 0 +-#define OCDR1 1 +-#define OCDR2 2 +-#define OCDR3 3 +-#define OCDR4 4 +-#define OCDR5 5 +-#define OCDR6 6 +-#define OCDR7 7 +-#define IDRD 7 +- +-/* Reserved [0x32] */ +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +-#define JTRF 4 +- +-#define MCUCR _SFR_IO8(0X35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define JTD 7 +- +-/* Reserved [0x36] */ +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define RWWSB 6 +-#define SPMIE 7 +- +-/* Reserved [0x38..0x3C] */ +- +-/* SP [0x3D..0x3E] */ +-/* SREG [0x3F] */ +- +-#define WDTCR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-/* Reserved [0x62..0x63] */ +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM1 3 +-#define PRLCD 4 +- +-/* Reserved [0x65] */ +- +-#define OSCCAL _SFR_MEM8(0x66) +- +-/* Reserved [0x67..0x68] */ +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +- +-/* Reserved [0x6A] */ +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-#define PCMSK2 _SFR_MEM8(0x6D) +-#define PCINT16 0 +-#define PCINT17 1 +-#define PCINT18 2 +-#define PCINT19 3 +-#define PCINT20 4 +-#define PCINT21 5 +-#define PCINT22 6 +-#define PCINT23 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define TIMSK2 _SFR_MEM8(0x70) +-#define TOIE2 0 +-#define OCIE2A 1 +- +-/* Reserved [0x71..0x72] */ +- +-#define PCMSK3 _SFR_MEM8(0x73) +-#define PCINT24 0 +-#define PCINT25 1 +-#define PCINT26 2 +-#define PCINT27 3 +-#define PCINT28 4 +-#define PCINT29 5 +-#define PCINT30 6 +- +-/* Reserved [0x74..0x77] */ +- +-/* Combine ADCL and ADCH */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +-#define ADCL _SFR_MEM8(0x78) +-#define ADCH _SFR_MEM8(0x79) +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ACME 6 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-/* Reserved [0x7D] */ +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0X80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0X81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-/* Reserved [0x83] */ +- +-/* Combine TCNT1L and TCNT1H */ +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1H _SFR_MEM8(0x85) +- +-/* Combine ICR1L and ICR1H */ +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1H _SFR_MEM8(0x87) +- +-/* Combine OCR1AL and OCR1AH */ +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AH _SFR_MEM8(0x89) +- +-/* Combine OCR1BL and OCR1BH */ +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BH _SFR_MEM8(0x8B) +- +-/* Reserved [0x8C..0xAF] */ +- +-#define TCCR2A _SFR_MEM8(0xB0) +-#define CS20 0 +-#define CS21 1 +-#define CS22 2 +-#define WGM21 3 +-#define COM2A0 4 +-#define COM2A1 5 +-#define WGM20 6 +-#define FOC2A 7 +- +-/* Reserved [0xB1] */ +- +-#define TCNT2 _SFR_MEM8(0xB2) +- +-#define OCR2A _SFR_MEM8(0xB3) +- +-/* Reserved [0xB4..0xB5] */ +- +-#define ASSR _SFR_MEM8(0xB6) +-#define TCR2UB 0 +-#define OCR2UB 1 +-#define TCN2UB 2 +-#define AS2 3 +-#define EXCLK 4 +- +-/* Reserved [0xB7] */ +- +-#define USICR _SFR_MEM8(0xB8) +-#define USITC 0 +-#define USICLK 1 +-#define USICS0 2 +-#define USICS1 3 +-#define USIWM0 4 +-#define USIWM1 5 +-#define USIOIE 6 +-#define USISIE 7 +- +-#define USISR _SFR_MEM8(0xB9) +-#define USICNT0 0 +-#define USICNT1 1 +-#define USICNT2 2 +-#define USICNT3 3 +-#define USIDC 4 +-#define USIPF 5 +-#define USIOIF 6 +-#define USISIF 7 +- +-#define USIDR _SFR_MEM8(0xBA) +- +-/* Reserved [0xBB..0xBF] */ +- +-#define UCSR0A _SFR_MEM8(0xC0) +-#define MPCM0 0 +-#define U2X0 1 +-#define UPE0 2 +-#define DOR0 3 +-#define FE0 4 +-#define UDRE0 5 +-#define TXC0 6 +-#define RXC0 7 +- +-#define UCSR0B _SFR_MEM8(0XC1) +-#define TXB80 0 +-#define RXB80 1 +-#define UCSZ02 2 +-#define TXEN0 3 +-#define RXEN0 4 +-#define UDRIE0 5 +-#define TXCIE0 6 +-#define RXCIE0 7 +- +-#define UCSR0C _SFR_MEM8(0xC2) +-#define UCPOL0 0 +-#define UCSZ00 1 +-#define UCSZ01 2 +-#define USBS0 3 +-#define UPM00 4 +-#define UPM01 5 +-#define UMSEL0 6 +- +-/* Reserved [0xC3] */ +- +-/* Combine UBRR0L and UBRR0H */ +-#define UBRR0 _SFR_MEM16(0xC4) +- +-#define UBRR0L _SFR_MEM8(0xC4) +-#define UBRR0H _SFR_MEM8(0xC5) +- +-#define UDR0 _SFR_MEM8(0XC6) +- +-/* Reserved [0xC7..0xD7] */ +- +-#define PINH _SFR_MEM8(0xD8) +-#define PINH7 7 +-#define PINH6 6 +-#define PINH5 5 +-#define PINH4 4 +-#define PINH3 3 +-#define PINH2 2 +-#define PINH1 1 +-#define PINH0 0 +- +-#define DDRH _SFR_MEM8(0xD9) +-#define DDH7 7 +-#define DDH6 6 +-#define DDH5 5 +-#define DDH4 4 +-#define DDH3 3 +-#define DDH2 2 +-#define DDH1 1 +-#define DDH0 0 +- +-#define PORTH _SFR_MEM8(0xDA) +-#define PH7 7 +-#define PH6 6 +-#define PH5 5 +-#define PH4 4 +-#define PH3 3 +-#define PH2 2 +-#define PH1 1 +-#define PH0 0 +- +-#define PINJ _SFR_MEM8(0xDB) +-#define PINJ6 6 +-#define PINJ5 5 +-#define PINJ4 4 +-#define PINJ3 3 +-#define PINJ2 2 +-#define PINJ1 1 +-#define PINJ0 0 +- +-#define DDRJ _SFR_MEM8(0xDC) +-#define DDJ6 6 +-#define DDJ5 5 +-#define DDJ4 4 +-#define DDJ3 3 +-#define DDJ2 2 +-#define DDJ1 1 +-#define DDJ0 0 +- +-#define PORTJ _SFR_MEM8(0xDD) +-#define PJ6 6 +-#define PJ5 5 +-#define PJ4 4 +-#define PJ3 3 +-#define PJ2 2 +-#define PJ1 1 +-#define PJ0 0 +- +-/* Reserved [0xDE..0xE3] */ +- +-#define LCDCRA _SFR_MEM8(0XE4) +-#define LCDBL 0 +-#define LCDIE 3 +-#define LCDIF 4 +-#define LCDAB 6 +-#define LCDEN 7 +- +-#define LCDCRB _SFR_MEM8(0XE5) +-#define LCDPM0 0 +-#define LCDPM1 1 +-#define LCDPM2 2 +-#define LCDPM3 3 +-#define LCDMUX0 4 +-#define LCDMUX1 5 +-#define LCD2B 6 +-#define LCDCS 7 +- +-#define LCDFRR _SFR_MEM8(0XE6) +-#define LCDCD0 0 +-#define LCDCD1 1 +-#define LCDCD2 2 +-#define LCDPS0 4 +-#define LCDPS1 5 +-#define LCDPS2 6 +- +-#define LCDCCR _SFR_MEM8(0XE7) +-#define LCDCC0 0 +-#define LCDCC1 1 +-#define LCDCC2 2 +-#define LCDCC3 3 +-#define LCDDC0 5 +-#define LCDDC1 6 +-#define LCDDC2 7 +- +-/* Reserved [0xE8..0xEB] */ +- +-#define LCDDR00 _SFR_MEM8(0XEC) +-#define SEG000 0 +-#define SEG001 1 +-#define SEG002 2 +-#define SEG003 3 +-#define SEG004 4 +-#define SEG005 5 +-#define SEG006 6 +-#define SEG007 7 +- +-#define LCDDR01 _SFR_MEM8(0XED) +-#define SEG008 0 +-#define SEG009 1 +-#define SEG010 2 +-#define SEG011 3 +-#define SEG012 4 +-#define SEG013 5 +-#define SEG014 6 +-#define SEG015 7 +- +-#define LCDDR02 _SFR_MEM8(0XEE) +-#define SEG016 0 +-#define SEG017 1 +-#define SEG018 2 +-#define SEG019 3 +-#define SEG020 4 +-#define SEG021 5 +-#define SEG022 6 +-#define SEG023 7 +- +-#define LCDDR03 _SFR_MEM8(0XEF) +-#define SEG024 0 +-#define SEG025 1 +-#define SEG026 2 +-#define SEG027 3 +-#define SEG028 4 +-#define SEG029 5 +-#define SEG030 6 +-#define SEG031 7 +- +-#define LCDDR04 _SFR_MEM8(0XF0) +-#define SEG032 0 +-#define SEG033 1 +-#define SEG034 2 +-#define SEG035 3 +-#define SEG036 4 +-#define SEG037 5 +-#define SEG038 6 +-#define SEG039 7 +- +-#define LCDDR05 _SFR_MEM8(0XF1) +-#define SEG100 0 +-#define SEG101 1 +-#define SEG102 2 +-#define SEG103 3 +-#define SEG104 4 +-#define SEG105 5 +-#define SEG106 6 +-#define SEG107 7 +- +-#define LCDDR06 _SFR_MEM8(0XF2) +-#define SEG108 0 +-#define SEG109 1 +-#define SEG110 2 +-#define SEG111 3 +-#define SEG112 4 +-#define SEG113 5 +-#define SEG114 6 +-#define SEG115 7 +- +-#define LCDDR07 _SFR_MEM8(0XF3) +-#define SEG116 0 +-#define SEG117 1 +-#define SEG118 2 +-#define SEG119 3 +-#define SEG120 4 +-#define SEG121 5 +-#define SEG122 6 +-#define SEG123 7 +- +-#define LCDDR08 _SFR_MEM8(0XF4) +-#define SEG124 0 +-#define SEG125 1 +-#define SEG126 2 +-#define SEG127 3 +-#define SEG128 4 +-#define SEG129 5 +-#define SEG130 6 +-#define SEG131 7 +- +-#define LCDDR09 _SFR_MEM8(0XF5) +-#define SEG132 0 +-#define SEG133 1 +-#define SEG134 2 +-#define SEG135 3 +-#define SEG136 4 +-#define SEG137 5 +-#define SEG138 6 +-#define SEG139 7 +- +-#define LCDDR10 _SFR_MEM8(0XF6) +-#define SEG200 0 +-#define SEG201 1 +-#define SEG202 2 +-#define SEG203 3 +-#define SEG204 4 +-#define SEG205 5 +-#define SEG206 6 +-#define SEG207 7 +- +-#define LCDDR11 _SFR_MEM8(0XF7) +-#define SEG208 0 +-#define SEG209 1 +-#define SEG210 2 +-#define SEG211 3 +-#define SEG212 4 +-#define SEG213 5 +-#define SEG214 6 +-#define SEG215 7 +- +-#define LCDDR12 _SFR_MEM8(0XF8) +-#define SEG216 0 +-#define SEG217 1 +-#define SEG218 2 +-#define SEG219 3 +-#define SEG220 4 +-#define SEG221 5 +-#define SEG222 6 +-#define SEG223 7 +- +-#define LCDDR13 _SFR_MEM8(0XF9) +-#define SEG224 0 +-#define SEG225 1 +-#define SEG226 2 +-#define SEG227 3 +-#define SEG228 4 +-#define SEG229 5 +-#define SEG230 6 +-#define SEG231 7 +- +-#define LCDDR14 _SFR_MEM8(0XFA) +-#define SEG232 0 +-#define SEG233 1 +-#define SEG234 2 +-#define SEG235 3 +-#define SEG236 4 +-#define SEG237 5 +-#define SEG238 6 +-#define SEG239 7 +- +-#define LCDDR15 _SFR_MEM8(0XFB) +-#define SEG300 0 +-#define SEG301 1 +-#define SEG302 2 +-#define SEG303 3 +-#define SEG304 4 +-#define SEG305 5 +-#define SEG306 6 +-#define SEG307 7 +- +-#define LCDDR16 _SFR_MEM8(0XFC) +-#define SEG308 0 +-#define SEG309 1 +-#define SEG310 2 +-#define SEG311 3 +-#define SEG312 4 +-#define SEG313 5 +-#define SEG314 6 +-#define SEG315 7 +- +-#define LCDDR17 _SFR_MEM8(0XFD) +-#define SEG316 0 +-#define SEG217 1 +-#define SEG318 2 +-#define SEG319 3 +-#define SEG320 4 +-#define SEG321 5 +-#define SEG322 6 +-#define SEG323 7 +- +-#define LCDDR18 _SFR_MEM8(0XFE) +-#define SEG324 0 +-#define SEG325 1 +-#define SEG326 2 +-#define SEG327 3 +-#define SEG328 4 +-#define SEG329 5 +-#define SEG330 6 +-#define SEG331 7 +- +-#define LCDDR19 _SFR_MEM8(0XFF) +-#define SEG332 0 +-#define SEG333 1 +-#define SEG334 2 +-#define SEG335 3 +-#define SEG336 4 +-#define SEG337 5 +-#define SEG338 6 +-#define SEG339 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* Pin Change Interrupt Request 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) +-#define SIG_PIN_CHANGE0 _VECTOR(2) +- +-/* Pin Change Interrupt Request 1 */ +-#define PCINT1_vect_num 3 +-#define PCINT1_vect _VECTOR(3) +-#define SIG_PIN_CHANGE1 _VECTOR(3) +- +-/* Timer/Counter2 Compare Match */ +-#define TIMER2_COMP_vect_num 4 +-#define TIMER2_COMP_vect _VECTOR(4) +-#define SIG_OUTPUT_COMPARE2 _VECTOR(4) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 5 +-#define TIMER2_OVF_vect _VECTOR(5) +-#define SIG_OVERFLOW2 _VECTOR(5) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 6 +-#define TIMER1_CAPT_vect _VECTOR(6) +-#define SIG_INPUT_CAPTURE1 _VECTOR(6) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 7 +-#define TIMER1_COMPA_vect _VECTOR(7) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(7) +- +-/* Timer/Counter Compare Match B */ +-#define TIMER1_COMPB_vect_num 8 +-#define TIMER1_COMPB_vect _VECTOR(8) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(8) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 9 +-#define TIMER1_OVF_vect _VECTOR(9) +-#define SIG_OVERFLOW1 _VECTOR(9) +- +-/* Timer/Counter0 Compare Match */ +-#define TIMER0_COMP_vect_num 10 +-#define TIMER0_COMP_vect _VECTOR(10) +-#define SIG_OUTPUT_COMPARE0 _VECTOR(10) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 11 +-#define TIMER0_OVF_vect _VECTOR(11) +-#define SIG_OVERFLOW0 _VECTOR(11) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 12 +-#define SPI_STC_vect _VECTOR(12) +-#define SIG_SPI _VECTOR(12) +- +-/* USART, Rx Complete */ +-#define USART_RX_vect_num 13 +-#define USART_RX_vect _VECTOR(13) +-#define SIG_UART_RECV _VECTOR(13) +- +-/* USART Data register Empty */ +-#define USART_UDRE_vect_num 14 +-#define USART_UDRE_vect _VECTOR(14) +-#define SIG_UART_DATA _VECTOR(14) +- +-/* USART0, Tx Complete */ +-#define USART0_TX_vect_num 15 +-#define USART0_TX_vect _VECTOR(15) +-#define SIG_UART_TRANS _VECTOR(15) +- +-/* USI Start Condition */ +-#define USI_START_vect_num 16 +-#define USI_START_vect _VECTOR(16) +-#define SIG_USI_START _VECTOR(16) +- +-/* USI Overflow */ +-#define USI_OVERFLOW_vect_num 17 +-#define USI_OVERFLOW_vect _VECTOR(17) +-#define SIG_USI_OVERFLOW _VECTOR(17) +- +-/* Analog Comparator */ +-#define ANALOG_COMP_vect_num 18 +-#define ANALOG_COMP_vect _VECTOR(18) +-#define SIG_COMPARATOR _VECTOR(18) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 19 +-#define ADC_vect _VECTOR(19) +-#define SIG_ADC _VECTOR(19) +- +-/* EEPROM Ready */ +-#define EE_READY_vect_num 20 +-#define EE_READY_vect _VECTOR(20) +-#define SIG_EEPROM_READY _VECTOR(20) +- +-/* Store Program Memory Read */ +-#define SPM_READY_vect_num 21 +-#define SPM_READY_vect _VECTOR(21) +-#define SIG_SPM_READY _VECTOR(21) +- +-/* LCD Start of Frame */ +-#define LCD_vect_num 22 +-#define LCD_vect _VECTOR(22) +-#define SIG_LCD _VECTOR(22) +- +-/* Pin Change Interrupt Request 2 */ +-#define PCINT2_vect_num 23 +-#define PCINT2_vect _VECTOR(23) +-#define SIG_PIN_CHANGE2 _VECTOR(23) +- +-/* Pin Change Interrupt Request 3 */ +-#define PCINT3_vect_num 24 +-#define PCINT3_vect _VECTOR(24) +-#define SIG_PIN_CHANGE3 _VECTOR(24) +- +-#define _VECTORS_SIZE 100 +- +- +-/* Constants */ +-#define SPM_PAGESIZE 256 +-#define RAMEND 0x10FF +-#define XRAMEND RAMEND +-#define E2END 0x7FF +-#define E2PAGESIZE 8 +-#define FLASHEND 0xFFFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x96 +-#define SIGNATURE_2 0x04 +- +- +-#endif /* _AVR_IOM6490_H_ */ ++/* Copyright (c) 2004 Eric B. Weddington ++ Copyright (c) 2005,2006 Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* avr/iom6490.h - definitions for ATmega6490 */ ++ ++#ifndef _AVR_IOM6490_H_ ++#define _AVR_IOM6490_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom6490.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE7 7 ++#define DDE6 6 ++#define DDE5 5 ++#define DDE4 4 ++#define DDE3 3 ++#define DDE2 2 ++#define DDE1 1 ++#define DDE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PE7 7 ++#define PE6 6 ++#define PE5 5 ++#define PE4 4 ++#define PE3 3 ++#define PE2 2 ++#define PE1 1 ++#define PE0 0 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDF7 7 ++#define DDF6 6 ++#define DDF5 5 ++#define DDF4 4 ++#define DDF3 3 ++#define DDF2 2 ++#define DDF1 1 ++#define DDF0 0 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PF7 7 ++#define PF6 6 ++#define PF5 5 ++#define PF4 4 ++#define PF3 3 ++#define PF2 2 ++#define PF1 1 ++#define PF0 0 ++ ++#define PING _SFR_IO8(0x12) ++#define PING5 5 ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++#define DDRG _SFR_IO8(0x13) ++#define DDG4 4 ++#define DDG3 3 ++#define DDG2 2 ++#define DDG1 1 ++#define DDG0 0 ++ ++#define PORTG _SFR_IO8(0x14) ++#define PG4 4 ++#define PG3 3 ++#define PG2 2 ++#define PG1 1 ++#define PG0 0 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++ ++/* Reserved [0x18..0x1B] */ ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define PCIF0 4 ++#define PCIF1 5 ++#define PCIF2 6 ++#define PCIF3 7 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define PCIE0 4 ++#define PCIE1 5 ++#define PCIE2 6 ++#define PCIE3 7 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++#define EEDR _SFR_IO8(0X20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0X22) ++ ++/* 6-char sequence denoting where to find the EEPROM registers in memory space. ++ Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM ++ subroutines. ++ First two letters: EECR address. ++ Second two letters: EEDR address. ++ Last two letters: EEAR address. */ ++#define __EEPROM_REG_LOCATIONS__ 1F2021 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR10 0 ++#define PSR2 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM01 3 ++#define COM0A0 4 ++#define COM0A1 5 ++#define WGM00 6 ++#define FOC0A 7 ++ ++/* Reserved [0x25] */ ++ ++#define TCNT0 _SFR_IO8(0X26) ++ ++#define OCR0A _SFR_IO8(0X27) ++ ++/* Reserved [0x28..0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0X2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCDR7 7 ++#define IDRD 7 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define JTRF 4 ++ ++#define MCUCR _SFR_IO8(0X35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define JTD 7 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++/* SREG [0x3F] */ ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRLCD 4 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++ ++/* Reserved [0x67..0x68] */ ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++ ++/* Reserved [0x71..0x72] */ ++ ++#define PCMSK3 _SFR_MEM8(0x73) ++#define PCINT24 0 ++#define PCINT25 1 ++#define PCINT26 2 ++#define PCINT27 3 ++#define PCINT28 4 ++#define PCINT29 5 ++#define PCINT30 6 ++ ++/* Reserved [0x74..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0X80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0X81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM21 3 ++#define COM2A0 4 ++#define COM2A1 5 ++#define WGM20 6 ++#define FOC2A 7 ++ ++/* Reserved [0xB1] */ ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++/* Reserved [0xB4..0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2UB 0 ++#define OCR2UB 1 ++#define TCN2UB 2 ++#define AS2 3 ++#define EXCLK 4 ++ ++/* Reserved [0xB7] */ ++ ++#define USICR _SFR_MEM8(0xB8) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_MEM8(0xB9) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_MEM8(0xBA) ++ ++/* Reserved [0xBB..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0XC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL0 6 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0XC6) ++ ++/* Reserved [0xC7..0xD7] */ ++ ++#define PINH _SFR_MEM8(0xD8) ++#define PINH7 7 ++#define PINH6 6 ++#define PINH5 5 ++#define PINH4 4 ++#define PINH3 3 ++#define PINH2 2 ++#define PINH1 1 ++#define PINH0 0 ++ ++#define DDRH _SFR_MEM8(0xD9) ++#define DDH7 7 ++#define DDH6 6 ++#define DDH5 5 ++#define DDH4 4 ++#define DDH3 3 ++#define DDH2 2 ++#define DDH1 1 ++#define DDH0 0 ++ ++#define PORTH _SFR_MEM8(0xDA) ++#define PH7 7 ++#define PH6 6 ++#define PH5 5 ++#define PH4 4 ++#define PH3 3 ++#define PH2 2 ++#define PH1 1 ++#define PH0 0 ++ ++#define PINJ _SFR_MEM8(0xDB) ++#define PINJ6 6 ++#define PINJ5 5 ++#define PINJ4 4 ++#define PINJ3 3 ++#define PINJ2 2 ++#define PINJ1 1 ++#define PINJ0 0 ++ ++#define DDRJ _SFR_MEM8(0xDC) ++#define DDJ6 6 ++#define DDJ5 5 ++#define DDJ4 4 ++#define DDJ3 3 ++#define DDJ2 2 ++#define DDJ1 1 ++#define DDJ0 0 ++ ++#define PORTJ _SFR_MEM8(0xDD) ++#define PJ6 6 ++#define PJ5 5 ++#define PJ4 4 ++#define PJ3 3 ++#define PJ2 2 ++#define PJ1 1 ++#define PJ0 0 ++ ++/* Reserved [0xDE..0xE3] */ ++ ++#define LCDCRA _SFR_MEM8(0XE4) ++#define LCDBL 0 ++#define LCDIE 3 ++#define LCDIF 4 ++#define LCDAB 6 ++#define LCDEN 7 ++ ++#define LCDCRB _SFR_MEM8(0XE5) ++#define LCDPM0 0 ++#define LCDPM1 1 ++#define LCDPM2 2 ++#define LCDPM3 3 ++#define LCDMUX0 4 ++#define LCDMUX1 5 ++#define LCD2B 6 ++#define LCDCS 7 ++ ++#define LCDFRR _SFR_MEM8(0XE6) ++#define LCDCD0 0 ++#define LCDCD1 1 ++#define LCDCD2 2 ++#define LCDPS0 4 ++#define LCDPS1 5 ++#define LCDPS2 6 ++ ++#define LCDCCR _SFR_MEM8(0XE7) ++#define LCDCC0 0 ++#define LCDCC1 1 ++#define LCDCC2 2 ++#define LCDCC3 3 ++#define LCDDC0 5 ++#define LCDDC1 6 ++#define LCDDC2 7 ++ ++/* Reserved [0xE8..0xEB] */ ++ ++#define LCDDR00 _SFR_MEM8(0XEC) ++#define SEG000 0 ++#define SEG001 1 ++#define SEG002 2 ++#define SEG003 3 ++#define SEG004 4 ++#define SEG005 5 ++#define SEG006 6 ++#define SEG007 7 ++ ++#define LCDDR01 _SFR_MEM8(0XED) ++#define SEG008 0 ++#define SEG009 1 ++#define SEG010 2 ++#define SEG011 3 ++#define SEG012 4 ++#define SEG013 5 ++#define SEG014 6 ++#define SEG015 7 ++ ++#define LCDDR02 _SFR_MEM8(0XEE) ++#define SEG016 0 ++#define SEG017 1 ++#define SEG018 2 ++#define SEG019 3 ++#define SEG020 4 ++#define SEG021 5 ++#define SEG022 6 ++#define SEG023 7 ++ ++#define LCDDR03 _SFR_MEM8(0XEF) ++#define SEG024 0 ++#define SEG025 1 ++#define SEG026 2 ++#define SEG027 3 ++#define SEG028 4 ++#define SEG029 5 ++#define SEG030 6 ++#define SEG031 7 ++ ++#define LCDDR04 _SFR_MEM8(0XF0) ++#define SEG032 0 ++#define SEG033 1 ++#define SEG034 2 ++#define SEG035 3 ++#define SEG036 4 ++#define SEG037 5 ++#define SEG038 6 ++#define SEG039 7 ++ ++#define LCDDR05 _SFR_MEM8(0XF1) ++#define SEG100 0 ++#define SEG101 1 ++#define SEG102 2 ++#define SEG103 3 ++#define SEG104 4 ++#define SEG105 5 ++#define SEG106 6 ++#define SEG107 7 ++ ++#define LCDDR06 _SFR_MEM8(0XF2) ++#define SEG108 0 ++#define SEG109 1 ++#define SEG110 2 ++#define SEG111 3 ++#define SEG112 4 ++#define SEG113 5 ++#define SEG114 6 ++#define SEG115 7 ++ ++#define LCDDR07 _SFR_MEM8(0XF3) ++#define SEG116 0 ++#define SEG117 1 ++#define SEG118 2 ++#define SEG119 3 ++#define SEG120 4 ++#define SEG121 5 ++#define SEG122 6 ++#define SEG123 7 ++ ++#define LCDDR08 _SFR_MEM8(0XF4) ++#define SEG124 0 ++#define SEG125 1 ++#define SEG126 2 ++#define SEG127 3 ++#define SEG128 4 ++#define SEG129 5 ++#define SEG130 6 ++#define SEG131 7 ++ ++#define LCDDR09 _SFR_MEM8(0XF5) ++#define SEG132 0 ++#define SEG133 1 ++#define SEG134 2 ++#define SEG135 3 ++#define SEG136 4 ++#define SEG137 5 ++#define SEG138 6 ++#define SEG139 7 ++ ++#define LCDDR10 _SFR_MEM8(0XF6) ++#define SEG200 0 ++#define SEG201 1 ++#define SEG202 2 ++#define SEG203 3 ++#define SEG204 4 ++#define SEG205 5 ++#define SEG206 6 ++#define SEG207 7 ++ ++#define LCDDR11 _SFR_MEM8(0XF7) ++#define SEG208 0 ++#define SEG209 1 ++#define SEG210 2 ++#define SEG211 3 ++#define SEG212 4 ++#define SEG213 5 ++#define SEG214 6 ++#define SEG215 7 ++ ++#define LCDDR12 _SFR_MEM8(0XF8) ++#define SEG216 0 ++#define SEG217 1 ++#define SEG218 2 ++#define SEG219 3 ++#define SEG220 4 ++#define SEG221 5 ++#define SEG222 6 ++#define SEG223 7 ++ ++#define LCDDR13 _SFR_MEM8(0XF9) ++#define SEG224 0 ++#define SEG225 1 ++#define SEG226 2 ++#define SEG227 3 ++#define SEG228 4 ++#define SEG229 5 ++#define SEG230 6 ++#define SEG231 7 ++ ++#define LCDDR14 _SFR_MEM8(0XFA) ++#define SEG232 0 ++#define SEG233 1 ++#define SEG234 2 ++#define SEG235 3 ++#define SEG236 4 ++#define SEG237 5 ++#define SEG238 6 ++#define SEG239 7 ++ ++#define LCDDR15 _SFR_MEM8(0XFB) ++#define SEG300 0 ++#define SEG301 1 ++#define SEG302 2 ++#define SEG303 3 ++#define SEG304 4 ++#define SEG305 5 ++#define SEG306 6 ++#define SEG307 7 ++ ++#define LCDDR16 _SFR_MEM8(0XFC) ++#define SEG308 0 ++#define SEG309 1 ++#define SEG310 2 ++#define SEG311 3 ++#define SEG312 4 ++#define SEG313 5 ++#define SEG314 6 ++#define SEG315 7 ++ ++#define LCDDR17 _SFR_MEM8(0XFD) ++#define SEG316 0 ++#define SEG217 1 ++#define SEG318 2 ++#define SEG319 3 ++#define SEG320 4 ++#define SEG321 5 ++#define SEG322 6 ++#define SEG323 7 ++ ++#define LCDDR18 _SFR_MEM8(0XFE) ++#define SEG324 0 ++#define SEG325 1 ++#define SEG326 2 ++#define SEG327 3 ++#define SEG328 4 ++#define SEG329 5 ++#define SEG330 6 ++#define SEG331 7 ++ ++#define LCDDR19 _SFR_MEM8(0XFF) ++#define SEG332 0 ++#define SEG333 1 ++#define SEG334 2 ++#define SEG335 3 ++#define SEG336 4 ++#define SEG337 5 ++#define SEG338 6 ++#define SEG339 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) ++#define SIG_PIN_CHANGE0 _VECTOR(2) ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect_num 3 ++#define PCINT1_vect _VECTOR(3) ++#define SIG_PIN_CHANGE1 _VECTOR(3) ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect_num 4 ++#define TIMER2_COMP_vect _VECTOR(4) ++#define SIG_OUTPUT_COMPARE2 _VECTOR(4) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 5 ++#define TIMER2_OVF_vect _VECTOR(5) ++#define SIG_OVERFLOW2 _VECTOR(5) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 6 ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define SIG_INPUT_CAPTURE1 _VECTOR(6) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 7 ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(7) ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect_num 8 ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(8) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 9 ++#define TIMER1_OVF_vect _VECTOR(9) ++#define SIG_OVERFLOW1 _VECTOR(9) ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect_num 10 ++#define TIMER0_COMP_vect _VECTOR(10) ++#define SIG_OUTPUT_COMPARE0 _VECTOR(10) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 11 ++#define TIMER0_OVF_vect _VECTOR(11) ++#define SIG_OVERFLOW0 _VECTOR(11) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 12 ++#define SPI_STC_vect _VECTOR(12) ++#define SIG_SPI _VECTOR(12) ++ ++/* USART, Rx Complete */ ++#define USART_RX_vect_num 13 ++#define USART_RX_vect _VECTOR(13) ++#define SIG_UART_RECV _VECTOR(13) ++ ++/* USART Data register Empty */ ++#define USART_UDRE_vect_num 14 ++#define USART_UDRE_vect _VECTOR(14) ++#define SIG_UART_DATA _VECTOR(14) ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect_num 15 ++#define USART0_TX_vect _VECTOR(15) ++#define SIG_UART_TRANS _VECTOR(15) ++ ++/* USI Start Condition */ ++#define USI_START_vect_num 16 ++#define USI_START_vect _VECTOR(16) ++#define SIG_USI_START _VECTOR(16) ++ ++/* USI Overflow */ ++#define USI_OVERFLOW_vect_num 17 ++#define USI_OVERFLOW_vect _VECTOR(17) ++#define SIG_USI_OVERFLOW _VECTOR(17) ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect_num 18 ++#define ANALOG_COMP_vect _VECTOR(18) ++#define SIG_COMPARATOR _VECTOR(18) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 19 ++#define ADC_vect _VECTOR(19) ++#define SIG_ADC _VECTOR(19) ++ ++/* EEPROM Ready */ ++#define EE_READY_vect_num 20 ++#define EE_READY_vect _VECTOR(20) ++#define SIG_EEPROM_READY _VECTOR(20) ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect_num 21 ++#define SPM_READY_vect _VECTOR(21) ++#define SIG_SPM_READY _VECTOR(21) ++ ++/* LCD Start of Frame */ ++#define LCD_vect_num 22 ++#define LCD_vect _VECTOR(22) ++#define SIG_LCD _VECTOR(22) ++ ++/* Pin Change Interrupt Request 2 */ ++#define PCINT2_vect_num 23 ++#define PCINT2_vect _VECTOR(23) ++#define SIG_PIN_CHANGE2 _VECTOR(23) ++ ++/* Pin Change Interrupt Request 3 */ ++#define PCINT3_vect_num 24 ++#define PCINT3_vect _VECTOR(24) ++#define SIG_PIN_CHANGE3 _VECTOR(24) ++ ++#define _VECTORS_SIZE 100 ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE 256 ++#define RAMSTART 0x100 ++#define RAMEND 0x10FF ++#define XRAMEND RAMEND ++#define E2END 0x7FF ++#define E2PAGESIZE 8 ++#define FLASHEND 0xFFFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x04 ++ ++ ++#endif /* _AVR_IOM6490_H_ */ diff --git a/include/avr/iom6490a.h b/include/avr/iom6490a.h new file mode 100644 -index 0000000..76c020b +index 0000000..4cdd7e4 --- /dev/null +++ b/include/avr/iom6490a.h @@ -0,0 +1,34 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2011 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+#include "iom6490.h" ++/***************************************************************************** ++ * ++ * Copyright (C) 2011 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++#include "iom6490.h" diff --git a/include/avr/iom6490p.h b/include/avr/iom6490p.h new file mode 100644 -index 0000000..76c020b +index 0000000..4cdd7e4 --- /dev/null +++ b/include/avr/iom6490p.h @@ -0,0 +1,34 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2011 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+#include "iom6490.h" ++/***************************************************************************** ++ * ++ * Copyright (C) 2011 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++#include "iom6490.h" diff --git a/include/avr/iom649a.h b/include/avr/iom649a.h new file mode 100644 -index 0000000..1e50c4e +index 0000000..544bb90 --- /dev/null +++ b/include/avr/iom649a.h @@ -0,0 +1,34 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2011 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+#include "iom649.h" ++/***************************************************************************** ++ * ++ * Copyright (C) 2011 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++#include "iom649.h" +diff --git a/include/avr/iom649p.h b/include/avr/iom649p.h +index e6226f6..096d95d 100644 +--- a/include/avr/iom649p.h ++++ b/include/avr/iom649p.h +@@ -1,1477 +1,1477 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom649p.h 2146 2010-06-09 06:38:54Z joerg_wunsch $ */ +- +-/* avr/iom649p.h - definitions for ATmega649 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom649p.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATmega649_H_ +-#define _AVR_ATmega649_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +-#define PINA4 4 +-#define PINA5 5 +-#define PINA6 6 +-#define PINA7 7 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +-#define DDA4 4 +-#define DDA5 5 +-#define DDA6 6 +-#define DDA7 7 +- +-#define PORTA _SFR_IO8(0x02) +-#define PORTA0 0 +-#define PORTA1 1 +-#define PORTA2 2 +-#define PORTA3 3 +-#define PORTA4 4 +-#define PORTA5 5 +-#define PORTA6 6 +-#define PORTA7 7 +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +-#define PINC7 7 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC3 3 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +-#define DDC7 7 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC3 3 +-#define PORTC4 4 +-#define PORTC5 5 +-#define PORTC6 6 +-#define PORTC7 7 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define PINE _SFR_IO8(0x0C) +-#define PINE0 0 +-#define PINE1 1 +-#define PINE2 2 +-#define PINE3 3 +-#define PINE4 4 +-#define PINE5 5 +-#define PINE6 6 +-#define PINE7 7 +- +-#define DDRE _SFR_IO8(0x0D) +-#define DDE0 0 +-#define DDE1 1 +-#define DDE2 2 +-#define DDE3 3 +-#define DDE4 4 +-#define DDE5 5 +-#define DDE6 6 +-#define DDE7 7 +- +-#define PORTE _SFR_IO8(0x0E) +-#define PORTE0 0 +-#define PORTE1 1 +-#define PORTE2 2 +-#define PORTE3 3 +-#define PORTE4 4 +-#define PORTE5 5 +-#define PORTE6 6 +-#define PORTE7 7 +- +-#define PINF _SFR_IO8(0x0F) +-#define PINF0 0 +-#define PINF1 1 +-#define PINF2 2 +-#define PINF3 3 +-#define PINF4 4 +-#define PINF5 5 +-#define PINF6 6 +-#define PINF7 7 +- +-#define DDRF _SFR_IO8(0x10) +-#define DDF0 0 +-#define DDF1 1 +-#define DDF2 2 +-#define DDF3 3 +-#define DDF4 4 +-#define DDF5 5 +-#define DDF6 6 +-#define DDF7 7 +- +-#define PORTF _SFR_IO8(0x11) +-#define PORTF0 0 +-#define PORTF1 1 +-#define PORTF2 2 +-#define PORTF3 3 +-#define PORTF4 4 +-#define PORTF5 5 +-#define PORTF6 6 +-#define PORTF7 7 +- +-#define PING _SFR_IO8(0x12) +-#define PING0 0 +-#define PING1 1 +-#define PING2 2 +-#define PING3 3 +-#define PING4 4 +-#define PING5 5 +- +-#define DDRG _SFR_IO8(0x13) +-#define DDG0 0 +-#define DDG1 1 +-#define DDG2 2 +-#define DDG3 3 +-#define DDG4 4 +- +-#define PORTG _SFR_IO8(0x14) +-#define PORTG0 0 +-#define PORTG1 1 +-#define PORTG2 2 +-#define PORTG3 3 +-#define PORTG4 4 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define TIFR2 _SFR_IO8(0x17) +-#define TOV2 0 +-#define OCF2A 1 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define PCIF0 4 +-#define PCIF1 5 +-#define PCIF2 6 +-#define PCIF3 7 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define PCIE0 4 +-#define PCIE1 5 +-#define PCIE2 6 +-#define PCIE3 7 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEWE 1 +-#define EEMWE 2 +-#define EERIE 3 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEARL0 0 +-#define EEARL1 1 +-#define EEARL2 2 +-#define EEARL3 3 +-#define EEARL4 4 +-#define EEARL5 5 +-#define EEARL6 6 +-#define EEARL7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +-#define EEAR9 1 +-#define EEAR10 2 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSR310 0 +-#define PSR2 1 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM01 3 +-#define COM0A0 4 +-#define COM0A1 5 +-#define WGM00 6 +-#define FOC0A 7 +- +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define OCR0A _SFR_IO8(0x27) +-#define OCR0A0 0 +-#define OCR0A1 1 +-#define OCR0A2 2 +-#define OCR0A3 3 +-#define OCR0A4 4 +-#define OCR0A5 5 +-#define OCR0A6 6 +-#define OCR0A7 7 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define OCDR _SFR_IO8(0x31) +-#define OCDR0 0 +-#define OCDR1 1 +-#define OCDR2 2 +-#define OCDR3 3 +-#define OCDR4 4 +-#define OCDR5 5 +-#define OCDR6 6 +-#define OCDR7 7 +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +-#define JTRF 4 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define JTD 7 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define WDTCR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM1 3 +-#define PRLCD 4 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define TIMSK2 _SFR_MEM8(0x70) +-#define TOIE2 0 +-#define OCIE2A 1 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +- +-#define ADCL _SFR_MEM8(0x78) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_MEM8(0x79) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ACME 6 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define TCCR2A _SFR_MEM8(0xB0) +-#define CS20 0 +-#define CS21 1 +-#define CS22 2 +-#define WGM21 3 +-#define COM2A0 4 +-#define COM2A1 5 +-#define WGM20 6 +-#define FOC2A 7 +- +-#define TCNT2 _SFR_MEM8(0xB2) +-#define TCNT2_0 0 +-#define TCNT2_1 1 +-#define TCNT2_2 2 +-#define TCNT2_3 3 +-#define TCNT2_4 4 +-#define TCNT2_5 5 +-#define TCNT2_6 6 +-#define TCNT2_7 7 +- +-#define OCR2A _SFR_MEM8(0xB3) +-#define OCR2A0 0 +-#define OCR2A1 1 +-#define OCR2A2 2 +-#define OCR2A3 3 +-#define OCR2A4 4 +-#define OCR2A5 5 +-#define OCR2A6 6 +-#define OCR2A7 7 +- +-#define ASSR _SFR_MEM8(0xB6) +-#define TCR2UB 0 +-#define OCR2UB 1 +-#define TCN2UB 2 +-#define AS2 3 +-#define EXCLK 4 +- +-#define USICR _SFR_MEM8(0xB8) +-#define USITC 0 +-#define USICLK 1 +-#define USICS0 2 +-#define USICS1 3 +-#define USIWM0 4 +-#define USIWM1 5 +-#define USIOIE 6 +-#define USISIE 7 +- +-#define USISR _SFR_MEM8(0xB9) +-#define USICNT0 0 +-#define USICNT1 1 +-#define USICNT2 2 +-#define USICNT3 3 +-#define USIDC 4 +-#define USIPF 5 +-#define USIOIF 6 +-#define USISIF 7 +- +-#define USIDR _SFR_MEM8(0xBA) +-#define USIDR0 0 +-#define USIDR1 1 +-#define USIDR2 2 +-#define USIDR3 3 +-#define USIDR4 4 +-#define USIDR5 5 +-#define USIDR6 6 +-#define USIDR7 7 +- +-#define UCSR0A _SFR_MEM8(0xC0) +-#define MPCM0 0 +-#define U2X0 1 +-#define UPE0 2 +-#define DOR0 3 +-#define FE0 4 +-#define UDRE0 5 +-#define TXC0 6 +-#define RXC0 7 +- +-#define UCSR0B _SFR_MEM8(0xC1) +-#define TXB80 0 +-#define RXB80 1 +-#define UCSZ02 2 +-#define TXEN0 3 +-#define RXEN0 4 +-#define UDRIE0 5 +-#define TXCIE0 6 +-#define RXCIE0 7 +- +-#define UCSR0C _SFR_MEM8(0xC2) +-#define UCPOL0 0 +-#define UCSZ00 1 +-#define UCSZ01 2 +-#define USBS0 3 +-#define UPM00 4 +-#define UPM01 5 +-#define UMSEL0 6 +- +-#define UBRR0 _SFR_MEM16(0xC4) +- +-#define UBRR0L _SFR_MEM8(0xC4) +-#define UBRR0_0 0 +-#define UBRR0_1 1 +-#define UBRR0_2 2 +-#define UBRR0_3 3 +-#define UBRR0_4 4 +-#define UBRR0_5 5 +-#define UBRR0_6 6 +-#define UBRR0_7 7 +- +-#define UBRR0H _SFR_MEM8(0xC5) +-#define UBRR0_8 0 +-#define UBRR0_9 1 +-#define UBRR0_10 2 +-#define UBRR0_11 3 +- +-#define UDR0 _SFR_MEM8(0xC6) +-#define UDR00 0 +-#define UDR01 1 +-#define UDR02 2 +-#define UDR03 3 +-#define UDR04 4 +-#define UDR05 5 +-#define UDR06 6 +-#define UDR07 7 +- +-#define LCDCRA _SFR_MEM8(0xE4) +-#define LCDBL 0 +-#define LCDIE 3 +-#define LCDIF 4 +-#define LCDAB 6 +-#define LCDEN 7 +- +-#define LCDCRB _SFR_MEM8(0xE5) +-#define LCDPM0 0 +-#define LCDPM1 1 +-#define LCDPM2 2 +-#define LCDPM3 3 +-#define LCDMUX0 4 +-#define LCDMUX1 5 +-#define LCD2B 6 +-#define LCDCS 7 +- +-#define LCDFRR _SFR_MEM8(0xE6) +-#define LCDCD0 0 +-#define LCDCD1 1 +-#define LCDCD2 2 +-#define LCDPS0 4 +-#define LCDPS1 5 +-#define LCDPS2 6 +- +-#define LCDCCR _SFR_MEM8(0xE7) +-#define LCDCC0 0 +-#define LCDCC1 1 +-#define LCDCC2 2 +-#define LCDCC3 3 +-#define LCDDC0 5 +-#define LCDDC1 6 +-#define LCDDC2 7 +- +-#define LCDDR0 _SFR_MEM8(0xEC) +-#define SEG000 0 +-#define SEG001 1 +-#define SEG002 2 +-#define SEG003 3 +-#define SEG004 4 +-#define SEG005 5 +-#define SEG006 6 +-#define SEG007 7 +- +-#define LCDDR1 _SFR_MEM8(0xED) +-#define SEG008 0 +-#define SEG009 1 +-#define SEG010 2 +-#define SEG011 3 +-#define SEG012 4 +-#define SEG013 5 +-#define SEG014 6 +-#define SEG015 7 +- +-#define LCDDR2 _SFR_MEM8(0xEE) +-#define SEG016 0 +-#define SEG017 1 +-#define SEG018 2 +-#define SEG019 3 +-#define SEG020 4 +-#define SEG021 5 +-#define SEG022 6 +-#define SEG023 7 +- +-#define LCDDR3 _SFR_MEM8(0xEF) +-#define SEG024 0 +- +-#define LCDDR4 _SFR_MEM8(0xF0) +- +-#define LCDDR5 _SFR_MEM8(0xF1) +-#define SEG100 0 +-#define SEG101 1 +-#define SEG102 2 +-#define SEG103 3 +-#define SEG104 4 +-#define SEG105 5 +-#define SEG106 6 +-#define SEG107 7 +- +-#define LCDDR6 _SFR_MEM8(0xF2) +-#define SEG108 0 +-#define SEG109 1 +-#define SEG110 2 +-#define SEG111 3 +-#define SEG112 4 +-#define SEG113 5 +-#define SEG114 6 +-#define SEG115 7 +- +-#define LCDDR7 _SFR_MEM8(0xF3) +-#define SEG116 0 +-#define SEG117 1 +-#define SEG118 2 +-#define SEG119 3 +-#define SEG120 4 +-#define SEG121 5 +-#define SEG122 6 +-#define SEG123 7 +- +-#define LCDDR8 _SFR_MEM8(0xF4) +-#define SEG124 0 +- +-#define LCDDR9 _SFR_MEM8(0xF5) +- +-#define LCDDR10 _SFR_MEM8(0xF6) +-#define SEG200 0 +-#define SEG201 1 +-#define SEG202 2 +-#define SEG203 3 +-#define SEG204 4 +-#define SEG205 5 +-#define SEG206 6 +-#define SEG207 7 +- +-#define LCDDR11 _SFR_MEM8(0xF7) +-#define SEG208 0 +-#define SEG209 1 +-#define SEG210 2 +-#define SEG211 3 +-#define SEG212 4 +-#define SEG213 5 +-#define SEG214 6 +-#define SEG215 7 +- +-#define LCDDR12 _SFR_MEM8(0xF8) +-#define SEG216 0 +-#define SEG217 1 +-#define SEG218 2 +-#define SEG219 3 +-#define SEG220 4 +-#define SEG221 5 +-#define SEG222 6 +-#define SEG223 7 +- +-#define LCDDR13 _SFR_MEM8(0xF9) +-#define SEG224 0 +- +-#define LCDDR14 _SFR_MEM8(0xFA) +- +-#define LCDDR15 _SFR_MEM8(0xFB) +-#define SEG300 0 +-#define SEG301 1 +-#define SEG302 2 +-#define SEG303 3 +-#define SEG304 4 +-#define SEG305 5 +-#define SEG306 6 +-#define SEG307 7 +- +-#define LCDDR16 _SFR_MEM8(0xFC) +-#define SEG308 0 +-#define SEG309 1 +-#define SEG310 2 +-#define SEG311 3 +-#define SEG312 4 +-#define SEG313 5 +-#define SEG314 6 +-#define SEG315 7 +- +-#define LCDDR17 _SFR_MEM8(0xFD) +-#define SEG316 0 +-#define SEG317 1 +-#define SEG318 2 +-#define SEG319 3 +-#define SEG320 4 +-#define SEG321 5 +-#define SEG322 6 +-#define SEG323 7 +- +-#define LCDDR18 _SFR_MEM8(0xFE) +-#define SEG324 0 +- +-#define LCDDR19 _SFR_MEM8(0xFF) +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ +-#define PCINT1_vect_num 3 +-#define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */ +-#define TIMER2_COMP_vect_num 4 +-#define TIMER2_COMP_vect _VECTOR(4) /* Timer/Counter2 Compare Match */ +-#define TIMER2_OVF_vect_num 5 +-#define TIMER2_OVF_vect _VECTOR(5) /* Timer/Counter2 Overflow */ +-#define TIMER1_CAPT_vect_num 6 +-#define TIMER1_CAPT_vect _VECTOR(6) /* Timer/Counter1 Capture Event */ +-#define TIMER1_COMPA_vect_num 7 +-#define TIMER1_COMPA_vect _VECTOR(7) /* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPB_vect_num 8 +-#define TIMER1_COMPB_vect _VECTOR(8) /* Timer/Counter Compare Match B */ +-#define TIMER1_OVF_vect_num 9 +-#define TIMER1_OVF_vect _VECTOR(9) /* Timer/Counter1 Overflow */ +-#define TIMER0_COMP_vect_num 10 +-#define TIMER0_COMP_vect _VECTOR(10) /* Timer/Counter0 Compare Match */ +-#define TIMER0_OVF_vect_num 11 +-#define TIMER0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ +-#define SPI_STC_vect_num 12 +-#define SPI_STC_vect _VECTOR(12) /* SPI Serial Transfer Complete */ +-#define USART0_RX_vect_num 13 +-#define USART0_RX_vect _VECTOR(13) /* USART0, Rx Complete */ +-#define USART0_UDRE_vect_num 14 +-#define USART0_UDRE_vect _VECTOR(14) /* USART0 Data register Empty */ +-#define USART0_TX_vect_num 15 +-#define USART0_TX_vect _VECTOR(15) /* USART0, Tx Complete */ +-#define USI_START_vect_num 16 +-#define USI_START_vect _VECTOR(16) /* USI Start Condition */ +-#define USI_OVERFLOW_vect_num 17 +-#define USI_OVERFLOW_vect _VECTOR(17) /* USI Overflow */ +-#define ANALOG_COMP_vect_num 18 +-#define ANALOG_COMP_vect _VECTOR(18) /* Analog Comparator */ +-#define ADC_vect_num 19 +-#define ADC_vect _VECTOR(19) /* ADC Conversion Complete */ +-#define EE_READY_vect_num 20 +-#define EE_READY_vect _VECTOR(20) /* EEPROM Ready */ +-#define SPM_READY_vect_num 21 +-#define SPM_READY_vect _VECTOR(21) /* Store Program Memory Read */ +-#define LCD_vect_num 22 +-#define LCD_vect _VECTOR(22) /* LCD Start of Frame */ +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (23 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (256) +-#define RAMSTART (0x100) +-#define RAMSIZE (4096) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x7FF) +-#define E2PAGESIZE (8) +-#define FLASHEND (0xFFFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ +-#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ +-#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) +- +-/* Extended Fuse Byte */ +-#define FUSE_RESERVED (unsigned char)~_BV(0) /* Reserved fuse bit, do not program */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x96 +-#define SIGNATURE_2 0x0B +- +- +-/* Device Pin Definitions */ +-#define RXD_DDR DDRE +-#define RXD_PORT PORTE +-#define RXD_PIN PINE +-#define RXD_BIT 0 +- +-#define PCINT0_DDR DDRE +-#define PCINT0_PORT PORTE +-#define PCINT0_PIN PINE +-#define PCINT0_BIT 0 +- +-#define TXD_DDR DDRE +-#define TXD_PORT PORTE +-#define TXD_PIN PINE +-#define TXD_BIT 1 +- +-#define PCINT1_DDR DDRE +-#define PCINT1_PORT PORTE +-#define PCINT1_PIN PINE +-#define PCINT1_BIT 1 +- +-#define XCK_DDR DDRE +-#define XCK_PORT PORTE +-#define XCK_PIN PINE +-#define XCK_BIT 2 +- +-#define AIN0_DDR DDRE +-#define AIN0_PORT PORTE +-#define AIN0_PIN PINE +-#define AIN0_BIT 2 +- +-#define PCINT2_DDR DDRE +-#define PCINT2_PORT PORTE +-#define PCINT2_PIN PINE +-#define PCINT2_BIT 2 +- +-#define AIN1_DDR DDRE +-#define AIN1_PORT PORTE +-#define AIN1_PIN PINE +-#define AIN1_BIT 3 +- +-#define PCINT3_DDR DDRE +-#define PCINT3_PORT PORTE +-#define PCINT3_PIN PINE +-#define PCINT3_BIT 3 +- +-#define USCK_DDR DDRE +-#define USCK_PORT PORTE +-#define USCK_PIN PINE +-#define USCK_BIT 4 +- +-#define SCL_DDR DDRE +-#define SCL_PORT PORTE +-#define SCL_PIN PINE +-#define SCL_BIT 4 +- +-#define PCINT4_DDR DDRE +-#define PCINT4_PORT PORTE +-#define PCINT4_PIN PINE +-#define PCINT4_BIT 4 +- +-#define DI_DDR DDRE +-#define DI_PORT PORTE +-#define DI_PIN PINE +-#define DI_BIT 5 +- +-#define SDA_DDR DDRE +-#define SDA_PORT PORTE +-#define SDA_PIN PINE +-#define SDA_BIT 5 +- +-#define PCINT5_DDR DDRE +-#define PCINT5_PORT PORTE +-#define PCINT5_PIN PINE +-#define PCINT5_BIT 5 +- +-#define DO_DDR DDRE +-#define DO_PORT PORTE +-#define DO_PIN PINE +-#define DO_BIT 6 +- +-#define PCINT6_DDR DDRE +-#define PCINT6_PORT PORTE +-#define PCINT6_PIN PINE +-#define PCINT6_BIT 6 +- +-#define PCINT7_DDR DDRE +-#define PCINT7_PORT PORTE +-#define PCINT7_PIN PINE +-#define PCINT7_BIT 7 +- +-#define SS_DDR DDRB +-#define SS_PORT PORTB +-#define SS_PIN PINB +-#define SS_BIT 0 +- +-#define PCINT8_DDR DDRB +-#define PCINT8_PORT PORTB +-#define PCINT8_PIN PINB +-#define PCINT8_BIT 0 +- +-#define SCK_DDR DDRB +-#define SCK_PORT PORTB +-#define SCK_PIN PINB +-#define SCK_BIT 1 +- +-#define PCINT9_DDR DDRB +-#define PCINT9_PORT PORTB +-#define PCINT9_PIN PINB +-#define PCINT9_BIT 1 +- +-#define MOSI_DDR DDRB +-#define MOSI_PORT PORTB +-#define MOSI_PIN PINB +-#define MOSI_BIT 2 +- +-#define PCINT10_DDR DDRB +-#define PCINT10_PORT PORTB +-#define PCINT10_PIN PINB +-#define PCINT10_BIT 2 +- +-#define MISO_DDR DDRB +-#define MISO_PORT PORTB +-#define MISO_PIN PINB +-#define MISO_BIT 3 +- +-#define PCINT11_DDR DDRB +-#define PCINT11_PORT PORTB +-#define PCINT11_PIN PINB +-#define PCINT11_BIT 3 +- +-#define OC0_DDR DDRB +-#define OC0_PORT PORTB +-#define OC0_PIN PINB +-#define OC0_BIT 4 +- +-#define PCINT12_DDR DDRB +-#define PCINT12_PORT PORTB +-#define PCINT12_PIN PINB +-#define PCINT12_BIT 4 +- +-#define OC1A_DDR DDRB +-#define OC1A_PORT PORTB +-#define OC1A_PIN PINB +-#define OC1A_BIT 5 +- +-#define PCINT13_DDR DDRB +-#define PCINT13_PORT PORTB +-#define PCINT13_PIN PINB +-#define PCINT13_BIT 5 +- +-#define OC1B_DDR DDRB +-#define OC1B_PORT PORTB +-#define OC1B_PIN PINB +-#define OC1B_BIT 6 +- +-#define PCINT14_DDR DDRB +-#define PCINT14_PORT PORTB +-#define PCINT14_PIN PINB +-#define PCINT14_BIT 6 +- +-#define OC2_DDR DDRB +-#define OC2_PORT PORTB +-#define OC2_PIN PINB +-#define OC2_BIT 7 +- +-#define PCINT15_DDR DDRB +-#define PCINT15_PORT PORTB +-#define PCINT15_PIN PINB +-#define PCINT15_BIT 7 +- +-#define T1_DDR DDRG +-#define T1_PORT PORTG +-#define T1_PIN PING +-#define T1_BIT 3 +- +-#define SEG24_DDR DDRG +-#define SEG24_PORT PORTG +-#define SEG24_PIN PING +-#define SEG24_BIT 3 +- +-#define T0_DDR DDRG +-#define T0_PORT PORTG +-#define T0_PIN PING +-#define T0_BIT 4 +- +-#define SEG23_DDR DDRG +-#define SEG23_PORT PORTG +-#define SEG23_PIN PING +-#define SEG23_BIT 4 +- +-#define SEG22_DDR DDRD +-#define SEG22_PORT PORTD +-#define SEG22_PIN PIND +-#define SEG22_BIT 0 +- +-#define SEG21_DDR DDRD +-#define SEG21_PORT PORTD +-#define SEG21_PIN PIND +-#define SEG21_BIT 1 +- +-#define SEG20_DDR DDRD +-#define SEG20_PORT PORTD +-#define SEG20_PIN PIND +-#define SEG20_BIT 2 +- +-#define SEG19_DDR DDRD +-#define SEG19_PORT PORTD +-#define SEG19_PIN PIND +-#define SEG19_BIT 3 +- +-#define SEG18_DDR DDRD +-#define SEG18_PORT PORTD +-#define SEG18_PIN PIND +-#define SEG18_BIT 4 +- +-#define SEG17_DDR DDRD +-#define SEG17_PORT PORTD +-#define SEG17_PIN PIND +-#define SEG17_BIT 5 +- +-#define SEG16_DDR DDRD +-#define SEG16_PORT PORTD +-#define SEG16_PIN PIND +-#define SEG16_BIT 6 +- +-#define SEG15_DDR DDRD +-#define SEG15_PORT PORTD +-#define SEG15_PIN PIND +-#define SEG15_BIT 7 +- +-#define SEG14_DDR DDRG +-#define SEG14_PORT PORTG +-#define SEG14_PIN PING +-#define SEG14_BIT 0 +- +-#define SEG13_DDR DDRG +-#define SEG13_PORT PORTG +-#define SEG13_PIN PING +-#define SEG13_BIT 1 +- +-#define SEG12_DDR DDRC +-#define SEG12_PORT PORTC +-#define SEG12_PIN PINC +-#define SEG12_BIT 0 +- +-#define SEG11_DDR DDRC +-#define SEG11_PORT PORTC +-#define SEG11_PIN PINC +-#define SEG11_BIT 1 +- +-#define SEG10_DDR DDRC +-#define SEG10_PORT PORTC +-#define SEG10_PIN PINC +-#define SEG10_BIT 2 +- +-#define SEG9_DDR DDRC +-#define SEG9_PORT PORTC +-#define SEG9_PIN PINC +-#define SEG9_BIT 3 +- +-#define SEG8_DDR DDRC +-#define SEG8_PORT PORTC +-#define SEG8_PIN PINC +-#define SEG8_BIT 4 +- +-#define SEG7_DDR DDRC +-#define SEG7_PORT PORTC +-#define SEG7_PIN PINC +-#define SEG7_BIT 5 +- +-#define SEG6_DDR DDRC +-#define SEG6_PORT PORTC +-#define SEG6_PIN PINC +-#define SEG6_BIT 6 +- +-#define SEG5_DDR DDRC +-#define SEG5_PORT PORTC +-#define SEG5_PIN PINC +-#define SEG5_BIT 7 +- +-#define SEG4_DDR DDRG +-#define SEG4_PORT PORTG +-#define SEG4_PIN PING +-#define SEG4_BIT 2 +- +-#define SEG3_DDR DDRA +-#define SEG3_PORT PORTA +-#define SEG3_PIN PINA +-#define SEG3_BIT 7 +- +-#define SEG2_DDR DDRA +-#define SEG2_PORT PORTA +-#define SEG2_PIN PINA +-#define SEG2_BIT 6 +- +-#define SEG1_DDR DDRA +-#define SEG1_PORT PORTA +-#define SEG1_PIN PINA +-#define SEG1_BIT 5 +- +-#define SEG0_DDR DDRA +-#define SEG0_PORT PORTA +-#define SEG0_PIN PINA +-#define SEG0_BIT 4 +- +-#define COM3_DDR DDRA +-#define COM3_PORT PORTA +-#define COM3_PIN PINA +-#define COM3_BIT 3 +- +-#define COM2_DDR DDRA +-#define COM2_PORT PORTA +-#define COM2_PIN PINA +-#define COM2_BIT 2 +- +-#define COM1_DDR DDRA +-#define COM1_PORT PORTA +-#define COM1_PIN PINA +-#define COM1_BIT 1 +- +-#define COM0_DDR DDRA +-#define COM0_PORT PORTA +-#define COM0_PIN PINA +-#define COM0_BIT 0 +- +-#define ADC7_DDR DDRF +-#define ADC7_PORT PORTF +-#define ADC7_PIN PINF +-#define ADC7_BIT 7 +- +-#define ADC6_DDR DDRF +-#define ADC6_PORT PORTF +-#define ADC6_PIN PINF +-#define ADC6_BIT 6 +- +-#define TD0_DDR DDRF +-#define TD0_PORT PORTF +-#define TD0_PIN PINF +-#define TD0_BIT 6 +- +-#define ADC5_DDR DDRF +-#define ADC5_PORT PORTF +-#define ADC5_PIN PINF +-#define ADC5_BIT 5 +- +-#define ADC4_DDR DDRF +-#define ADC4_PORT PORTF +-#define ADC4_PIN PINF +-#define ADC4_BIT 4 +- +-#define ADC3_DDR DDRF +-#define ADC3_PORT PORTF +-#define ADC3_PIN PINF +-#define ADC3_BIT 3 +- +-#define ADC2_DDR DDRF +-#define ADC2_PORT PORTF +-#define ADC2_PIN PINF +-#define ADC2_BIT 2 +- +-#define ADC1_DDR DDRF +-#define ADC1_PORT PORTF +-#define ADC1_PIN PINF +-#define ADC1_BIT 1 +- +-#define ADC0_DDR DDRF +-#define ADC0_PORT PORTF +-#define ADC0_PIN PINF +-#define ADC0_BIT 0 +- +-#endif /* _AVR_ATmega649_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom649p.h 2146 2010-06-09 06:38:54Z joerg_wunsch $ */ ++ ++/* avr/iom649p.h - definitions for ATmega649 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom649p.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATmega649_H_ ++#define _AVR_ATmega649_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++#define PINA4 4 ++#define PINA5 5 ++#define PINA6 6 ++#define PINA7 7 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++#define DDA4 4 ++#define DDA5 5 ++#define DDA6 6 ++#define DDA7 7 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA0 0 ++#define PORTA1 1 ++#define PORTA2 2 ++#define PORTA3 3 ++#define PORTA4 4 ++#define PORTA5 5 ++#define PORTA6 6 ++#define PORTA7 7 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++#define PINC7 7 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++#define DDC7 7 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC3 3 ++#define PORTC4 4 ++#define PORTC5 5 ++#define PORTC6 6 ++#define PORTC7 7 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE0 0 ++#define PINE1 1 ++#define PINE2 2 ++#define PINE3 3 ++#define PINE4 4 ++#define PINE5 5 ++#define PINE6 6 ++#define PINE7 7 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE0 0 ++#define DDE1 1 ++#define DDE2 2 ++#define DDE3 3 ++#define DDE4 4 ++#define DDE5 5 ++#define DDE6 6 ++#define DDE7 7 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE0 0 ++#define PORTE1 1 ++#define PORTE2 2 ++#define PORTE3 3 ++#define PORTE4 4 ++#define PORTE5 5 ++#define PORTE6 6 ++#define PORTE7 7 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF0 0 ++#define PINF1 1 ++#define PINF2 2 ++#define PINF3 3 ++#define PINF4 4 ++#define PINF5 5 ++#define PINF6 6 ++#define PINF7 7 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDF0 0 ++#define DDF1 1 ++#define DDF2 2 ++#define DDF3 3 ++#define DDF4 4 ++#define DDF5 5 ++#define DDF6 6 ++#define DDF7 7 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PORTF0 0 ++#define PORTF1 1 ++#define PORTF2 2 ++#define PORTF3 3 ++#define PORTF4 4 ++#define PORTF5 5 ++#define PORTF6 6 ++#define PORTF7 7 ++ ++#define PING _SFR_IO8(0x12) ++#define PING0 0 ++#define PING1 1 ++#define PING2 2 ++#define PING3 3 ++#define PING4 4 ++#define PING5 5 ++ ++#define DDRG _SFR_IO8(0x13) ++#define DDG0 0 ++#define DDG1 1 ++#define DDG2 2 ++#define DDG3 3 ++#define DDG4 4 ++ ++#define PORTG _SFR_IO8(0x14) ++#define PORTG0 0 ++#define PORTG1 1 ++#define PORTG2 2 ++#define PORTG3 3 ++#define PORTG4 4 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define PCIF0 4 ++#define PCIF1 5 ++#define PCIF2 6 ++#define PCIF3 7 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define PCIE0 4 ++#define PCIE1 5 ++#define PCIE2 6 ++#define PCIE3 7 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARL0 0 ++#define EEARL1 1 ++#define EEARL2 2 ++#define EEARL3 3 ++#define EEARL4 4 ++#define EEARL5 5 ++#define EEARL6 6 ++#define EEARL7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++#define EEAR9 1 ++#define EEAR10 2 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR310 0 ++#define PSR2 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM01 3 ++#define COM0A0 4 ++#define COM0A1 5 ++#define WGM00 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define OCR0A _SFR_IO8(0x27) ++#define OCR0A0 0 ++#define OCR0A1 1 ++#define OCR0A2 2 ++#define OCR0A3 3 ++#define OCR0A4 4 ++#define OCR0A5 5 ++#define OCR0A6 6 ++#define OCR0A7 7 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCDR7 7 ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define JTRF 4 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define JTD 7 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRLCD 4 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_MEM8(0x79) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM21 3 ++#define COM2A0 4 ++#define COM2A1 5 ++#define WGM20 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++#define TCNT2_0 0 ++#define TCNT2_1 1 ++#define TCNT2_2 2 ++#define TCNT2_3 3 ++#define TCNT2_4 4 ++#define TCNT2_5 5 ++#define TCNT2_6 6 ++#define TCNT2_7 7 ++ ++#define OCR2A _SFR_MEM8(0xB3) ++#define OCR2A0 0 ++#define OCR2A1 1 ++#define OCR2A2 2 ++#define OCR2A3 3 ++#define OCR2A4 4 ++#define OCR2A5 5 ++#define OCR2A6 6 ++#define OCR2A7 7 ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2UB 0 ++#define OCR2UB 1 ++#define TCN2UB 2 ++#define AS2 3 ++#define EXCLK 4 ++ ++#define USICR _SFR_MEM8(0xB8) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_MEM8(0xB9) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_MEM8(0xBA) ++#define USIDR0 0 ++#define USIDR1 1 ++#define USIDR2 2 ++#define USIDR3 3 ++#define USIDR4 4 ++#define USIDR5 5 ++#define USIDR6 6 ++#define USIDR7 7 ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL0 6 ++ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0_0 0 ++#define UBRR0_1 1 ++#define UBRR0_2 2 ++#define UBRR0_3 3 ++#define UBRR0_4 4 ++#define UBRR0_5 5 ++#define UBRR0_6 6 ++#define UBRR0_7 7 ++ ++#define UBRR0H _SFR_MEM8(0xC5) ++#define UBRR0_8 0 ++#define UBRR0_9 1 ++#define UBRR0_10 2 ++#define UBRR0_11 3 ++ ++#define UDR0 _SFR_MEM8(0xC6) ++#define UDR00 0 ++#define UDR01 1 ++#define UDR02 2 ++#define UDR03 3 ++#define UDR04 4 ++#define UDR05 5 ++#define UDR06 6 ++#define UDR07 7 ++ ++#define LCDCRA _SFR_MEM8(0xE4) ++#define LCDBL 0 ++#define LCDIE 3 ++#define LCDIF 4 ++#define LCDAB 6 ++#define LCDEN 7 ++ ++#define LCDCRB _SFR_MEM8(0xE5) ++#define LCDPM0 0 ++#define LCDPM1 1 ++#define LCDPM2 2 ++#define LCDPM3 3 ++#define LCDMUX0 4 ++#define LCDMUX1 5 ++#define LCD2B 6 ++#define LCDCS 7 ++ ++#define LCDFRR _SFR_MEM8(0xE6) ++#define LCDCD0 0 ++#define LCDCD1 1 ++#define LCDCD2 2 ++#define LCDPS0 4 ++#define LCDPS1 5 ++#define LCDPS2 6 ++ ++#define LCDCCR _SFR_MEM8(0xE7) ++#define LCDCC0 0 ++#define LCDCC1 1 ++#define LCDCC2 2 ++#define LCDCC3 3 ++#define LCDDC0 5 ++#define LCDDC1 6 ++#define LCDDC2 7 ++ ++#define LCDDR0 _SFR_MEM8(0xEC) ++#define SEG000 0 ++#define SEG001 1 ++#define SEG002 2 ++#define SEG003 3 ++#define SEG004 4 ++#define SEG005 5 ++#define SEG006 6 ++#define SEG007 7 ++ ++#define LCDDR1 _SFR_MEM8(0xED) ++#define SEG008 0 ++#define SEG009 1 ++#define SEG010 2 ++#define SEG011 3 ++#define SEG012 4 ++#define SEG013 5 ++#define SEG014 6 ++#define SEG015 7 ++ ++#define LCDDR2 _SFR_MEM8(0xEE) ++#define SEG016 0 ++#define SEG017 1 ++#define SEG018 2 ++#define SEG019 3 ++#define SEG020 4 ++#define SEG021 5 ++#define SEG022 6 ++#define SEG023 7 ++ ++#define LCDDR3 _SFR_MEM8(0xEF) ++#define SEG024 0 ++ ++#define LCDDR4 _SFR_MEM8(0xF0) ++ ++#define LCDDR5 _SFR_MEM8(0xF1) ++#define SEG100 0 ++#define SEG101 1 ++#define SEG102 2 ++#define SEG103 3 ++#define SEG104 4 ++#define SEG105 5 ++#define SEG106 6 ++#define SEG107 7 ++ ++#define LCDDR6 _SFR_MEM8(0xF2) ++#define SEG108 0 ++#define SEG109 1 ++#define SEG110 2 ++#define SEG111 3 ++#define SEG112 4 ++#define SEG113 5 ++#define SEG114 6 ++#define SEG115 7 ++ ++#define LCDDR7 _SFR_MEM8(0xF3) ++#define SEG116 0 ++#define SEG117 1 ++#define SEG118 2 ++#define SEG119 3 ++#define SEG120 4 ++#define SEG121 5 ++#define SEG122 6 ++#define SEG123 7 ++ ++#define LCDDR8 _SFR_MEM8(0xF4) ++#define SEG124 0 ++ ++#define LCDDR9 _SFR_MEM8(0xF5) ++ ++#define LCDDR10 _SFR_MEM8(0xF6) ++#define SEG200 0 ++#define SEG201 1 ++#define SEG202 2 ++#define SEG203 3 ++#define SEG204 4 ++#define SEG205 5 ++#define SEG206 6 ++#define SEG207 7 ++ ++#define LCDDR11 _SFR_MEM8(0xF7) ++#define SEG208 0 ++#define SEG209 1 ++#define SEG210 2 ++#define SEG211 3 ++#define SEG212 4 ++#define SEG213 5 ++#define SEG214 6 ++#define SEG215 7 ++ ++#define LCDDR12 _SFR_MEM8(0xF8) ++#define SEG216 0 ++#define SEG217 1 ++#define SEG218 2 ++#define SEG219 3 ++#define SEG220 4 ++#define SEG221 5 ++#define SEG222 6 ++#define SEG223 7 ++ ++#define LCDDR13 _SFR_MEM8(0xF9) ++#define SEG224 0 ++ ++#define LCDDR14 _SFR_MEM8(0xFA) ++ ++#define LCDDR15 _SFR_MEM8(0xFB) ++#define SEG300 0 ++#define SEG301 1 ++#define SEG302 2 ++#define SEG303 3 ++#define SEG304 4 ++#define SEG305 5 ++#define SEG306 6 ++#define SEG307 7 ++ ++#define LCDDR16 _SFR_MEM8(0xFC) ++#define SEG308 0 ++#define SEG309 1 ++#define SEG310 2 ++#define SEG311 3 ++#define SEG312 4 ++#define SEG313 5 ++#define SEG314 6 ++#define SEG315 7 ++ ++#define LCDDR17 _SFR_MEM8(0xFD) ++#define SEG316 0 ++#define SEG317 1 ++#define SEG318 2 ++#define SEG319 3 ++#define SEG320 4 ++#define SEG321 5 ++#define SEG322 6 ++#define SEG323 7 ++ ++#define LCDDR18 _SFR_MEM8(0xFE) ++#define SEG324 0 ++ ++#define LCDDR19 _SFR_MEM8(0xFF) ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect_num 3 ++#define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */ ++#define TIMER2_COMP_vect_num 4 ++#define TIMER2_COMP_vect _VECTOR(4) /* Timer/Counter2 Compare Match */ ++#define TIMER2_OVF_vect_num 5 ++#define TIMER2_OVF_vect _VECTOR(5) /* Timer/Counter2 Overflow */ ++#define TIMER1_CAPT_vect_num 6 ++#define TIMER1_CAPT_vect _VECTOR(6) /* Timer/Counter1 Capture Event */ ++#define TIMER1_COMPA_vect_num 7 ++#define TIMER1_COMPA_vect _VECTOR(7) /* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPB_vect_num 8 ++#define TIMER1_COMPB_vect _VECTOR(8) /* Timer/Counter Compare Match B */ ++#define TIMER1_OVF_vect_num 9 ++#define TIMER1_OVF_vect _VECTOR(9) /* Timer/Counter1 Overflow */ ++#define TIMER0_COMP_vect_num 10 ++#define TIMER0_COMP_vect _VECTOR(10) /* Timer/Counter0 Compare Match */ ++#define TIMER0_OVF_vect_num 11 ++#define TIMER0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ ++#define SPI_STC_vect_num 12 ++#define SPI_STC_vect _VECTOR(12) /* SPI Serial Transfer Complete */ ++#define USART0_RX_vect_num 13 ++#define USART0_RX_vect _VECTOR(13) /* USART0, Rx Complete */ ++#define USART0_UDRE_vect_num 14 ++#define USART0_UDRE_vect _VECTOR(14) /* USART0 Data register Empty */ ++#define USART0_TX_vect_num 15 ++#define USART0_TX_vect _VECTOR(15) /* USART0, Tx Complete */ ++#define USI_START_vect_num 16 ++#define USI_START_vect _VECTOR(16) /* USI Start Condition */ ++#define USI_OVERFLOW_vect_num 17 ++#define USI_OVERFLOW_vect _VECTOR(17) /* USI Overflow */ ++#define ANALOG_COMP_vect_num 18 ++#define ANALOG_COMP_vect _VECTOR(18) /* Analog Comparator */ ++#define ADC_vect_num 19 ++#define ADC_vect _VECTOR(19) /* ADC Conversion Complete */ ++#define EE_READY_vect_num 20 ++#define EE_READY_vect _VECTOR(20) /* EEPROM Ready */ ++#define SPM_READY_vect_num 21 ++#define SPM_READY_vect _VECTOR(21) /* Store Program Memory Read */ ++#define LCD_vect_num 22 ++#define LCD_vect _VECTOR(22) /* LCD Start of Frame */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (23 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (256) ++#define RAMSTART (0x100) ++#define RAMSIZE (4096) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x7FF) ++#define E2PAGESIZE (8) ++#define FLASHEND (0xFFFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_JTAGEN (unsigned char)~_BV(6) /* Enable JTAG */ ++#define FUSE_OCDEN (unsigned char)~_BV(7) /* Enable OCD */ ++#define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) ++ ++/* Extended Fuse Byte */ ++#define FUSE_RESERVED (unsigned char)~_BV(0) /* Reserved fuse bit, do not program */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x0B ++ ++ ++/* Device Pin Definitions */ ++#define RXD_DDR DDRE ++#define RXD_PORT PORTE ++#define RXD_PIN PINE ++#define RXD_BIT 0 ++ ++#define PCINT0_DDR DDRE ++#define PCINT0_PORT PORTE ++#define PCINT0_PIN PINE ++#define PCINT0_BIT 0 ++ ++#define TXD_DDR DDRE ++#define TXD_PORT PORTE ++#define TXD_PIN PINE ++#define TXD_BIT 1 ++ ++#define PCINT1_DDR DDRE ++#define PCINT1_PORT PORTE ++#define PCINT1_PIN PINE ++#define PCINT1_BIT 1 ++ ++#define XCK_DDR DDRE ++#define XCK_PORT PORTE ++#define XCK_PIN PINE ++#define XCK_BIT 2 ++ ++#define AIN0_DDR DDRE ++#define AIN0_PORT PORTE ++#define AIN0_PIN PINE ++#define AIN0_BIT 2 ++ ++#define PCINT2_DDR DDRE ++#define PCINT2_PORT PORTE ++#define PCINT2_PIN PINE ++#define PCINT2_BIT 2 ++ ++#define AIN1_DDR DDRE ++#define AIN1_PORT PORTE ++#define AIN1_PIN PINE ++#define AIN1_BIT 3 ++ ++#define PCINT3_DDR DDRE ++#define PCINT3_PORT PORTE ++#define PCINT3_PIN PINE ++#define PCINT3_BIT 3 ++ ++#define USCK_DDR DDRE ++#define USCK_PORT PORTE ++#define USCK_PIN PINE ++#define USCK_BIT 4 ++ ++#define SCL_DDR DDRE ++#define SCL_PORT PORTE ++#define SCL_PIN PINE ++#define SCL_BIT 4 ++ ++#define PCINT4_DDR DDRE ++#define PCINT4_PORT PORTE ++#define PCINT4_PIN PINE ++#define PCINT4_BIT 4 ++ ++#define DI_DDR DDRE ++#define DI_PORT PORTE ++#define DI_PIN PINE ++#define DI_BIT 5 ++ ++#define SDA_DDR DDRE ++#define SDA_PORT PORTE ++#define SDA_PIN PINE ++#define SDA_BIT 5 ++ ++#define PCINT5_DDR DDRE ++#define PCINT5_PORT PORTE ++#define PCINT5_PIN PINE ++#define PCINT5_BIT 5 ++ ++#define DO_DDR DDRE ++#define DO_PORT PORTE ++#define DO_PIN PINE ++#define DO_BIT 6 ++ ++#define PCINT6_DDR DDRE ++#define PCINT6_PORT PORTE ++#define PCINT6_PIN PINE ++#define PCINT6_BIT 6 ++ ++#define PCINT7_DDR DDRE ++#define PCINT7_PORT PORTE ++#define PCINT7_PIN PINE ++#define PCINT7_BIT 7 ++ ++#define SS_DDR DDRB ++#define SS_PORT PORTB ++#define SS_PIN PINB ++#define SS_BIT 0 ++ ++#define PCINT8_DDR DDRB ++#define PCINT8_PORT PORTB ++#define PCINT8_PIN PINB ++#define PCINT8_BIT 0 ++ ++#define SCK_DDR DDRB ++#define SCK_PORT PORTB ++#define SCK_PIN PINB ++#define SCK_BIT 1 ++ ++#define PCINT9_DDR DDRB ++#define PCINT9_PORT PORTB ++#define PCINT9_PIN PINB ++#define PCINT9_BIT 1 ++ ++#define MOSI_DDR DDRB ++#define MOSI_PORT PORTB ++#define MOSI_PIN PINB ++#define MOSI_BIT 2 ++ ++#define PCINT10_DDR DDRB ++#define PCINT10_PORT PORTB ++#define PCINT10_PIN PINB ++#define PCINT10_BIT 2 ++ ++#define MISO_DDR DDRB ++#define MISO_PORT PORTB ++#define MISO_PIN PINB ++#define MISO_BIT 3 ++ ++#define PCINT11_DDR DDRB ++#define PCINT11_PORT PORTB ++#define PCINT11_PIN PINB ++#define PCINT11_BIT 3 ++ ++#define OC0_DDR DDRB ++#define OC0_PORT PORTB ++#define OC0_PIN PINB ++#define OC0_BIT 4 ++ ++#define PCINT12_DDR DDRB ++#define PCINT12_PORT PORTB ++#define PCINT12_PIN PINB ++#define PCINT12_BIT 4 ++ ++#define OC1A_DDR DDRB ++#define OC1A_PORT PORTB ++#define OC1A_PIN PINB ++#define OC1A_BIT 5 ++ ++#define PCINT13_DDR DDRB ++#define PCINT13_PORT PORTB ++#define PCINT13_PIN PINB ++#define PCINT13_BIT 5 ++ ++#define OC1B_DDR DDRB ++#define OC1B_PORT PORTB ++#define OC1B_PIN PINB ++#define OC1B_BIT 6 ++ ++#define PCINT14_DDR DDRB ++#define PCINT14_PORT PORTB ++#define PCINT14_PIN PINB ++#define PCINT14_BIT 6 ++ ++#define OC2_DDR DDRB ++#define OC2_PORT PORTB ++#define OC2_PIN PINB ++#define OC2_BIT 7 ++ ++#define PCINT15_DDR DDRB ++#define PCINT15_PORT PORTB ++#define PCINT15_PIN PINB ++#define PCINT15_BIT 7 ++ ++#define T1_DDR DDRG ++#define T1_PORT PORTG ++#define T1_PIN PING ++#define T1_BIT 3 ++ ++#define SEG24_DDR DDRG ++#define SEG24_PORT PORTG ++#define SEG24_PIN PING ++#define SEG24_BIT 3 ++ ++#define T0_DDR DDRG ++#define T0_PORT PORTG ++#define T0_PIN PING ++#define T0_BIT 4 ++ ++#define SEG23_DDR DDRG ++#define SEG23_PORT PORTG ++#define SEG23_PIN PING ++#define SEG23_BIT 4 ++ ++#define SEG22_DDR DDRD ++#define SEG22_PORT PORTD ++#define SEG22_PIN PIND ++#define SEG22_BIT 0 ++ ++#define SEG21_DDR DDRD ++#define SEG21_PORT PORTD ++#define SEG21_PIN PIND ++#define SEG21_BIT 1 ++ ++#define SEG20_DDR DDRD ++#define SEG20_PORT PORTD ++#define SEG20_PIN PIND ++#define SEG20_BIT 2 ++ ++#define SEG19_DDR DDRD ++#define SEG19_PORT PORTD ++#define SEG19_PIN PIND ++#define SEG19_BIT 3 ++ ++#define SEG18_DDR DDRD ++#define SEG18_PORT PORTD ++#define SEG18_PIN PIND ++#define SEG18_BIT 4 ++ ++#define SEG17_DDR DDRD ++#define SEG17_PORT PORTD ++#define SEG17_PIN PIND ++#define SEG17_BIT 5 ++ ++#define SEG16_DDR DDRD ++#define SEG16_PORT PORTD ++#define SEG16_PIN PIND ++#define SEG16_BIT 6 ++ ++#define SEG15_DDR DDRD ++#define SEG15_PORT PORTD ++#define SEG15_PIN PIND ++#define SEG15_BIT 7 ++ ++#define SEG14_DDR DDRG ++#define SEG14_PORT PORTG ++#define SEG14_PIN PING ++#define SEG14_BIT 0 ++ ++#define SEG13_DDR DDRG ++#define SEG13_PORT PORTG ++#define SEG13_PIN PING ++#define SEG13_BIT 1 ++ ++#define SEG12_DDR DDRC ++#define SEG12_PORT PORTC ++#define SEG12_PIN PINC ++#define SEG12_BIT 0 ++ ++#define SEG11_DDR DDRC ++#define SEG11_PORT PORTC ++#define SEG11_PIN PINC ++#define SEG11_BIT 1 ++ ++#define SEG10_DDR DDRC ++#define SEG10_PORT PORTC ++#define SEG10_PIN PINC ++#define SEG10_BIT 2 ++ ++#define SEG9_DDR DDRC ++#define SEG9_PORT PORTC ++#define SEG9_PIN PINC ++#define SEG9_BIT 3 ++ ++#define SEG8_DDR DDRC ++#define SEG8_PORT PORTC ++#define SEG8_PIN PINC ++#define SEG8_BIT 4 ++ ++#define SEG7_DDR DDRC ++#define SEG7_PORT PORTC ++#define SEG7_PIN PINC ++#define SEG7_BIT 5 ++ ++#define SEG6_DDR DDRC ++#define SEG6_PORT PORTC ++#define SEG6_PIN PINC ++#define SEG6_BIT 6 ++ ++#define SEG5_DDR DDRC ++#define SEG5_PORT PORTC ++#define SEG5_PIN PINC ++#define SEG5_BIT 7 ++ ++#define SEG4_DDR DDRG ++#define SEG4_PORT PORTG ++#define SEG4_PIN PING ++#define SEG4_BIT 2 ++ ++#define SEG3_DDR DDRA ++#define SEG3_PORT PORTA ++#define SEG3_PIN PINA ++#define SEG3_BIT 7 ++ ++#define SEG2_DDR DDRA ++#define SEG2_PORT PORTA ++#define SEG2_PIN PINA ++#define SEG2_BIT 6 ++ ++#define SEG1_DDR DDRA ++#define SEG1_PORT PORTA ++#define SEG1_PIN PINA ++#define SEG1_BIT 5 ++ ++#define SEG0_DDR DDRA ++#define SEG0_PORT PORTA ++#define SEG0_PIN PINA ++#define SEG0_BIT 4 ++ ++#define COM3_DDR DDRA ++#define COM3_PORT PORTA ++#define COM3_PIN PINA ++#define COM3_BIT 3 ++ ++#define COM2_DDR DDRA ++#define COM2_PORT PORTA ++#define COM2_PIN PINA ++#define COM2_BIT 2 ++ ++#define COM1_DDR DDRA ++#define COM1_PORT PORTA ++#define COM1_PIN PINA ++#define COM1_BIT 1 ++ ++#define COM0_DDR DDRA ++#define COM0_PORT PORTA ++#define COM0_PIN PINA ++#define COM0_BIT 0 ++ ++#define ADC7_DDR DDRF ++#define ADC7_PORT PORTF ++#define ADC7_PIN PINF ++#define ADC7_BIT 7 ++ ++#define ADC6_DDR DDRF ++#define ADC6_PORT PORTF ++#define ADC6_PIN PINF ++#define ADC6_BIT 6 ++ ++#define TD0_DDR DDRF ++#define TD0_PORT PORTF ++#define TD0_PIN PINF ++#define TD0_BIT 6 ++ ++#define ADC5_DDR DDRF ++#define ADC5_PORT PORTF ++#define ADC5_PIN PINF ++#define ADC5_BIT 5 ++ ++#define ADC4_DDR DDRF ++#define ADC4_PORT PORTF ++#define ADC4_PIN PINF ++#define ADC4_BIT 4 ++ ++#define ADC3_DDR DDRF ++#define ADC3_PORT PORTF ++#define ADC3_PIN PINF ++#define ADC3_BIT 3 ++ ++#define ADC2_DDR DDRF ++#define ADC2_PORT PORTF ++#define ADC2_PIN PINF ++#define ADC2_BIT 2 ++ ++#define ADC1_DDR DDRF ++#define ADC1_PORT PORTF ++#define ADC1_PIN PINF ++#define ADC1_BIT 1 ++ ++#define ADC0_DDR DDRF ++#define ADC0_PORT PORTF ++#define ADC0_PIN PINF ++#define ADC0_BIT 0 ++ ++#endif /* _AVR_ATmega649_H_ */ ++ diff --git a/include/avr/iom64a.h b/include/avr/iom64a.h new file mode 100644 -index 0000000..524d31c +index 0000000..5fe0f44 --- /dev/null +++ b/include/avr/iom64a.h @@ -0,0 +1,962 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATMEGA64A_H_INCLUDED -+#define _AVR_ATMEGA64A_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iom64a.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINF _SFR_IO8(0x00) -+#define PINF7 7 -+#define PINF6 6 -+#define PINF5 5 -+#define PINF4 4 -+#define PINF3 3 -+#define PINF2 2 -+#define PINF1 1 -+#define PINF0 0 -+ -+#define PINE _SFR_IO8(0x01) -+#define PINE7 7 -+#define PINE6 6 -+#define PINE5 5 -+#define PINE4 4 -+#define PINE3 3 -+#define PINE2 2 -+#define PINE1 1 -+#define PINE0 0 -+ -+#define DDRE _SFR_IO8(0x02) -+#define DDRE7 7 -+#define DDRE6 6 -+#define DDRE5 5 -+#define DDRE4 4 -+#define DDRE3 3 -+#define DDRE2 2 -+#define DDRE1 1 -+#define DDRE0 0 -+ -+#define PORTE _SFR_IO8(0x03) -+#define PORTE7 7 -+#define PORTE6 6 -+#define PORTE5 5 -+#define PORTE4 4 -+#define PORTE3 3 -+#define PORTE2 2 -+#define PORTE1 1 -+#define PORTE0 0 -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_IO16(0x04) -+#endif -+#define ADCW _SFR_IO16(0x04) -+ -+#define ADCL _SFR_IO8(0x04) -+#define ADCH _SFR_IO8(0x05) -+ -+#define ADCSRA _SFR_IO8(0x06) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADMUX _SFR_IO8(0x07) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define MUX4 4 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+#define ACSR _SFR_IO8(0x08) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACBG 6 -+#define ACD 7 -+ -+#define UBRR0L _SFR_IO8(0x09) -+ -+#define UCSR0B _SFR_IO8(0x0A) -+#define TXB80 0 -+#define RXB80 1 -+#define UCSZ02 2 -+#define TXEN0 3 -+#define RXEN0 4 -+#define UDRIE0 5 -+#define TXCIE0 6 -+#define RXCIE0 7 -+ -+#define UCSR0A _SFR_IO8(0x0B) -+#define MPCM0 0 -+#define U2X0 1 -+#define UPE0 2 -+#define DOR0 3 -+#define FE0 4 -+#define UDRE0 5 -+#define TXC0 6 -+#define RXC0 7 -+ -+#define UDR0 _SFR_IO8(0x0C) -+ -+#define SPCR _SFR_IO8(0x0D) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x0E) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x0F) -+ -+#define PIND _SFR_IO8(0x10) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x11) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x12) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+#define PINC _SFR_IO8(0x13) -+#define PINC7 7 -+#define PINC6 6 -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x14) -+#define DDRC7 7 -+#define DDRC6 6 -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x15) -+#define PORTC7 7 -+#define PORTC6 6 -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PINB _SFR_IO8(0x16) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x17) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x18) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINA _SFR_IO8(0x19) -+#define PINA7 7 -+#define PINA6 6 -+#define PINA5 5 -+#define PINA4 4 -+#define PINA3 3 -+#define PINA2 2 -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x1A) -+#define DDRA7 7 -+#define DDRA6 6 -+#define DDRA5 5 -+#define DDRA4 4 -+#define DDRA3 3 -+#define DDRA2 2 -+#define DDRA1 1 -+#define DDRA0 0 -+ -+#define PORTA _SFR_IO8(0x1B) -+#define PORTA7 7 -+#define PORTA6 6 -+#define PORTA5 5 -+#define PORTA4 4 -+#define PORTA3 3 -+#define PORTA2 2 -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define EECR _SFR_IO8(0x1C) -+#define EERE 0 -+#define EEWE 1 -+#define EEMWE 2 -+#define EERIE 3 -+ -+#define EEDR _SFR_IO8(0x1D) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x1E) -+ -+#define EEARL _SFR_IO8(0x1E) -+#define EEARH _SFR_IO8(0x1F) -+ -+#define SFIOR _SFR_IO8(0x20) -+#define ACME 3 -+#define PSR321 0 -+#define PSR0 1 -+#define PUD 2 -+#define TSM 7 -+ -+#define WDTCR _SFR_IO8(0x21) -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDE 3 -+#define WDCE 4 -+ -+#define OCDR _SFR_IO8(0x22) -+#define OCDR0 0 -+#define OCDR1 1 -+#define OCDR2 2 -+#define OCDR3 3 -+#define OCDR4 4 -+#define OCDR5 5 -+#define OCDR6 6 -+#define OCDR7 7 -+ -+#define OCR2 _SFR_IO8(0x23) -+ -+#define TCNT2 _SFR_IO8(0x24) -+ -+#define TCCR2 _SFR_IO8(0x25) -+#define CS20 0 -+#define CS21 1 -+#define CS22 2 -+#define WGM21 3 -+#define COM20 4 -+#define COM21 5 -+#define WGM20 6 -+#define FOC2 7 -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_IO16(0x26) -+ -+#define ICR1L _SFR_IO8(0x26) -+#define ICR1H _SFR_IO8(0x27) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_IO16(0x28) -+ -+#define OCR1BL _SFR_IO8(0x28) -+#define OCR1BH _SFR_IO8(0x29) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_IO16(0x2A) -+ -+#define OCR1AL _SFR_IO8(0x2A) -+#define OCR1AH _SFR_IO8(0x2B) -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_IO16(0x2C) -+ -+#define TCNT1L _SFR_IO8(0x2C) -+#define TCNT1H _SFR_IO8(0x2D) -+ -+#define TCCR1B _SFR_IO8(0x2E) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1A _SFR_IO8(0x2F) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1C0 2 -+#define COM1C1 3 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define ASSR _SFR_IO8(0x30) -+#define TCR0UB 0 -+#define OCR0UB 1 -+#define TCN0UB 2 -+#define AS0 3 -+ -+#define OCR0 _SFR_IO8(0x31) -+ -+#define TCNT0 _SFR_IO8(0x32) -+ -+#define TCCR0 _SFR_IO8(0x33) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define WGM01 3 -+#define COM00 4 -+#define COM01 5 -+#define WGM00 6 -+#define FOC0 7 -+ -+#define MCUCSR _SFR_IO8(0x34) -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+#define JTRF 4 -+#define JTD 7 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define IVCE 0 -+#define IVSEL 1 -+#define SM2 2 -+#define SM0 3 -+#define SM1 4 -+#define SE 5 -+#define SRW10 6 -+#define SRE 7 -+ -+#define TIFR _SFR_IO8(0x36) -+#define TOV0 0 -+#define OCF0 1 -+#define TOV1 2 -+#define OCF1B 3 -+#define OCF1A 4 -+#define ICF1 5 -+#define TOV2 6 -+#define OCF2 7 -+ -+#define TIMSK _SFR_IO8(0x37) -+#define TOIE0 0 -+#define OCIE0 1 -+#define TOIE1 2 -+#define OCIE1B 3 -+#define OCIE1A 4 -+#define TICIE1 5 -+#define TOIE2 6 -+#define OCIE2 7 -+ -+#define EIFR _SFR_IO8(0x38) -+#define INTF0 0 -+#define INTF1 1 -+#define INTF2 2 -+#define INTF3 3 -+#define INTF4 4 -+#define INTF5 5 -+#define INTF6 6 -+#define INTF7 7 -+ -+#define EIMSK _SFR_IO8(0x39) -+#define INT0 0 -+#define INT1 1 -+#define INT2 2 -+#define INT3 3 -+#define INT4 4 -+#define INT5 5 -+#define INT6 6 -+#define INT7 7 -+ -+#define EICRB _SFR_IO8(0x3A) -+#define ISC40 0 -+#define ISC41 1 -+#define ISC50 2 -+#define ISC51 3 -+#define ISC60 4 -+#define ISC61 5 -+#define ISC70 6 -+#define ISC71 7 -+ -+/* Reserved [0x3B] */ -+ -+#define XDIV _SFR_IO8(0x3C) -+#define XDIV0 0 -+#define XDIV1 1 -+#define XDIV2 2 -+#define XDIV3 3 -+#define XDIV4 4 -+#define XDIV5 5 -+#define XDIV6 6 -+#define XDIVEN 7 -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+/* Reserved [0x40..0x60] */ -+ -+#define DDRF _SFR_MEM8(0x61) -+#define DDRF7 7 -+#define DDRF6 6 -+#define DDRF5 5 -+#define DDRF4 4 -+#define DDRF3 3 -+#define DDRF2 2 -+#define DDRF1 1 -+#define DDRF0 0 -+ -+#define PORTF _SFR_MEM8(0x62) -+#define PORTF7 7 -+#define PORTF6 6 -+#define PORTF5 5 -+#define PORTF4 4 -+#define PORTF3 3 -+#define PORTF2 2 -+#define PORTF1 1 -+#define PORTF0 0 -+ -+#define PING _SFR_MEM8(0x63) -+#define PING4 4 -+#define PING3 3 -+#define PING2 2 -+#define PING1 1 -+#define PING0 0 -+ -+#define DDRG _SFR_MEM8(0x64) -+#define DDRG4 4 -+#define DDRG3 3 -+#define DDRG2 2 -+#define DDRG1 1 -+#define DDRG0 0 -+ -+#define PORTG _SFR_MEM8(0x65) -+#define PORTG4 4 -+#define PORTG3 3 -+#define PORTG2 2 -+#define PORTG1 1 -+#define PORTG0 0 -+ -+/* Reserved [0x66..0x67] */ -+ -+#define SPMCSR _SFR_MEM8(0x68) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+/* Reserved [0x69] */ -+ -+#define EICRA _SFR_MEM8(0x6A) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+#define ISC20 4 -+#define ISC21 5 -+#define ISC30 6 -+#define ISC31 7 -+ -+/* Reserved [0x6B] */ -+ -+#define XMCRB _SFR_MEM8(0x6C) -+#define XMM0 0 -+#define XMM1 1 -+#define XMM2 2 -+#define XMBK 7 -+ -+#define XMCRA _SFR_MEM8(0x6D) -+#define SRW11 1 -+#define SRW00 2 -+#define SRW01 3 -+#define SRL0 4 -+#define SRL1 5 -+#define SRL2 6 -+ -+/* Reserved [0x6E] */ -+ -+#define OSCCAL _SFR_MEM8(0x6F) -+#define OSCCAL0 0 -+#define OSCCAL1 1 -+#define OSCCAL2 2 -+#define OSCCAL3 3 -+#define OSCCAL4 4 -+#define OSCCAL5 5 -+#define OSCCAL6 6 -+#define OSCCAL7 7 -+ -+#define TWBR _SFR_MEM8(0x70) -+ -+#define TWSR _SFR_MEM8(0x71) -+#define TWPS0 0 -+#define TWPS1 1 -+#define TWS3 3 -+#define TWS4 4 -+#define TWS5 5 -+#define TWS6 6 -+#define TWS7 7 -+ -+#define TWAR _SFR_MEM8(0x72) -+#define TWGCE 0 -+#define TWA0 1 -+#define TWA1 2 -+#define TWA2 3 -+#define TWA3 4 -+#define TWA4 5 -+#define TWA5 6 -+#define TWA6 7 -+ -+#define TWDR _SFR_MEM8(0x73) -+ -+#define TWCR _SFR_MEM8(0x74) -+#define TWIE 0 -+#define TWEN 2 -+#define TWWC 3 -+#define TWSTO 4 -+#define TWSTA 5 -+#define TWEA 6 -+#define TWINT 7 -+ -+/* Reserved [0x75..0x77] */ -+ -+/* Combine OCR1CL and OCR1CH */ -+#define OCR1C _SFR_MEM16(0x78) -+ -+#define OCR1CL _SFR_MEM8(0x78) -+#define OCR1CH _SFR_MEM8(0x79) -+ -+#define TCCR1C _SFR_MEM8(0x7A) -+#define FOC1C 5 -+#define FOC1B 6 -+#define FOC1A 7 -+ -+/* Reserved [0x7B] */ -+ -+#define ETIFR _SFR_MEM8(0x7C) -+#define OCF1C 0 -+#define OCF3C 1 -+#define TOV3 2 -+#define OCF3B 3 -+#define OCF3A 4 -+#define ICF3 5 -+ -+#define ETIMSK _SFR_MEM8(0x7D) -+#define OCIE1C 0 -+#define OCIE3C 1 -+#define TOIE3 2 -+#define OCIE3B 3 -+#define OCIE3A 4 -+#define TICIE3 5 -+ -+/* Reserved [0x7E..0x7F] */ -+ -+/* Combine ICR3L and ICR3H */ -+#define ICR3 _SFR_MEM16(0x80) -+ -+#define ICR3L _SFR_MEM8(0x80) -+#define ICR3H _SFR_MEM8(0x81) -+ -+/* Combine OCR3CL and OCR3CH */ -+#define OCR3C _SFR_MEM16(0x82) -+ -+#define OCR3CL _SFR_MEM8(0x82) -+#define OCR3CH _SFR_MEM8(0x83) -+ -+/* Combine OCR3BL and OCR3BH */ -+#define OCR3B _SFR_MEM16(0x84) -+ -+#define OCR3BL _SFR_MEM8(0x84) -+#define OCR3BH _SFR_MEM8(0x85) -+ -+/* Combine OCR3AL and OCR3AH */ -+#define OCR3A _SFR_MEM16(0x86) -+ -+#define OCR3AL _SFR_MEM8(0x86) -+#define OCR3AH _SFR_MEM8(0x87) -+ -+/* Combine TCNT3L and TCNT3H */ -+#define TCNT3 _SFR_MEM16(0x88) -+ -+#define TCNT3L _SFR_MEM8(0x88) -+#define TCNT3H _SFR_MEM8(0x89) -+ -+#define TCCR3B _SFR_MEM8(0x8A) -+#define CS30 0 -+#define CS31 1 -+#define CS32 2 -+#define WGM32 3 -+#define WGM33 4 -+#define ICES3 6 -+#define ICNC3 7 -+ -+#define TCCR3A _SFR_MEM8(0x8B) -+#define WGM30 0 -+#define WGM31 1 -+#define COM3C0 2 -+#define COM3C1 3 -+#define COM3B0 4 -+#define COM3B1 5 -+#define COM3A0 6 -+#define COM3A1 7 -+ -+#define TCCR3C _SFR_MEM8(0x8C) -+#define FOC3C 5 -+#define FOC3B 6 -+#define FOC3A 7 -+ -+/* Reserved [0x8D] */ -+ -+#define ADCSRB _SFR_MEM8(0x8E) -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+ -+/* Reserved [0x8F] */ -+ -+#define UBRR0H _SFR_MEM8(0x90) -+ -+/* Reserved [0x91..0x94] */ -+ -+#define UCSR0C _SFR_MEM8(0x95) -+#define UCPOL0 0 -+#define UCSZ00 1 -+#define UCSZ01 2 -+#define USBS0 3 -+#define UPM00 4 -+#define UPM01 5 -+#define UMSEL0 6 -+ -+/* Reserved [0x96..0x97] */ -+ -+#define UBRR1H _SFR_MEM8(0x98) -+ -+#define UBRR1L _SFR_MEM8(0x99) -+ -+#define UCSR1B _SFR_MEM8(0x9A) -+#define TXB81 0 -+#define RXB81 1 -+#define UCSZ12 2 -+#define TXEN1 3 -+#define RXEN1 4 -+#define UDRIE1 5 -+#define TXCIE1 6 -+#define RXCIE1 7 -+ -+#define UCSR1A _SFR_MEM8(0x9B) -+#define MPCM1 0 -+#define U2X1 1 -+#define UPE1 2 -+#define DOR1 3 -+#define FE1 4 -+#define UDRE1 5 -+#define TXC1 6 -+#define RXC1 7 -+ -+#define UDR1 _SFR_MEM8(0x9C) -+ -+#define UCSR1C _SFR_MEM8(0x9D) -+#define UCPOL1 0 -+#define UCSZ10 1 -+#define UCSZ11 2 -+#define USBS1 3 -+#define UPM10 4 -+#define UPM11 5 -+#define UMSEL1 6 -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* External Interrupt Request 2 */ -+#define INT2_vect _VECTOR(3) -+#define INT2_vect_num 3 -+ -+/* External Interrupt Request 3 */ -+#define INT3_vect _VECTOR(4) -+#define INT3_vect_num 4 -+ -+/* External Interrupt Request 4 */ -+#define INT4_vect _VECTOR(5) -+#define INT4_vect_num 5 -+ -+/* External Interrupt Request 5 */ -+#define INT5_vect _VECTOR(6) -+#define INT5_vect_num 6 -+ -+/* External Interrupt Request 6 */ -+#define INT6_vect _VECTOR(7) -+#define INT6_vect_num 7 -+ -+/* External Interrupt Request 7 */ -+#define INT7_vect _VECTOR(8) -+#define INT7_vect_num 8 -+ -+/* Timer/Counter2 Compare Match */ -+#define TIMER2_COMP_vect _VECTOR(9) -+#define TIMER2_COMP_vect_num 9 -+ -+/* Timer/Counter2 Overflow */ -+#define TIMER2_OVF_vect _VECTOR(10) -+#define TIMER2_OVF_vect_num 10 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(11) -+#define TIMER1_CAPT_vect_num 11 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(12) -+#define TIMER1_COMPA_vect_num 12 -+ -+/* Timer/Counter Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(13) -+#define TIMER1_COMPB_vect_num 13 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(14) -+#define TIMER1_OVF_vect_num 14 -+ -+/* Timer/Counter0 Compare Match */ -+#define TIMER0_COMP_vect _VECTOR(15) -+#define TIMER0_COMP_vect_num 15 -+ -+/* Timer/Counter0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(16) -+#define TIMER0_OVF_vect_num 16 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(17) -+#define SPI_STC_vect_num 17 -+ -+/* USART0, Rx Complete */ -+#define USART0_RX_vect _VECTOR(18) -+#define USART0_RX_vect_num 18 -+ -+/* USART0 Data Register Empty */ -+#define USART0_UDRE_vect _VECTOR(19) -+#define USART0_UDRE_vect_num 19 -+ -+/* USART0, Tx Complete */ -+#define USART0_TX_vect _VECTOR(20) -+#define USART0_TX_vect_num 20 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(21) -+#define ADC_vect_num 21 -+ -+/* EEPROM Ready */ -+#define EE_READY_vect _VECTOR(22) -+#define EE_READY_vect_num 22 -+ -+/* Analog Comparator */ -+#define ANALOG_COMP_vect _VECTOR(23) -+#define ANALOG_COMP_vect_num 23 -+ -+/* Timer/Counter1 Compare Match C */ -+#define TIMER1_COMPC_vect _VECTOR(24) -+#define TIMER1_COMPC_vect_num 24 -+ -+/* Timer/Counter3 Capture Event */ -+#define TIMER3_CAPT_vect _VECTOR(25) -+#define TIMER3_CAPT_vect_num 25 -+ -+/* Timer/Counter3 Compare Match A */ -+#define TIMER3_COMPA_vect _VECTOR(26) -+#define TIMER3_COMPA_vect_num 26 -+ -+/* Timer/Counter3 Compare Match B */ -+#define TIMER3_COMPB_vect _VECTOR(27) -+#define TIMER3_COMPB_vect_num 27 -+ -+/* Timer/Counter3 Compare Match C */ -+#define TIMER3_COMPC_vect _VECTOR(28) -+#define TIMER3_COMPC_vect_num 28 -+ -+/* Timer/Counter3 Overflow */ -+#define TIMER3_OVF_vect _VECTOR(29) -+#define TIMER3_OVF_vect_num 29 -+ -+/* USART1, Rx Complete */ -+#define USART1_RX_vect _VECTOR(30) -+#define USART1_RX_vect_num 30 -+ -+/* USART1, Data Register Empty */ -+#define USART1_UDRE_vect _VECTOR(31) -+#define USART1_UDRE_vect_num 31 -+ -+/* USART1, Tx Complete */ -+#define USART1_TX_vect _VECTOR(32) -+#define USART1_TX_vect_num 32 -+ -+/* 2-wire Serial Interface */ -+#define TWI_vect _VECTOR(33) -+#define TWI_vect_num 33 -+ -+/* Store Program Memory Read */ -+#define SPM_READY_vect _VECTOR(34) -+#define SPM_READY_vect_num 34 -+ -+#define _VECTORS_SIZE 140 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 256 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0xFFFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 4096 -+#define RAMEND 0x10FF -+#define E2START 0 -+#define E2SIZE 2048 -+#define E2PAGESIZE 8 -+#define E2END 0x07FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -+#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -+#define FUSE_BODEN (unsigned char)~_BV(6) -+#define FUSE_BODLEVEL (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_CKOPT (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_JTAGEN (unsigned char)~_BV(6) -+#define FUSE_OCDEN (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_WDTON (unsigned char)~_BV(0) -+#define FUSE_CompMode (unsigned char)~_BV(1) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x96 -+#define SIGNATURE_2 0x02 -+ -+ -+#endif /* #ifdef _AVR_ATMEGA64A_H_INCLUDED */ -+ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATMEGA64A_H_INCLUDED ++#define _AVR_ATMEGA64A_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom64a.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINF _SFR_IO8(0x00) ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++#define PINE _SFR_IO8(0x01) ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x02) ++#define DDRE7 7 ++#define DDRE6 6 ++#define DDRE5 5 ++#define DDRE4 4 ++#define DDRE3 3 ++#define DDRE2 2 ++#define DDRE1 1 ++#define DDRE0 0 ++ ++#define PORTE _SFR_IO8(0x03) ++#define PORTE7 7 ++#define PORTE6 6 ++#define PORTE5 5 ++#define PORTE4 4 ++#define PORTE3 3 ++#define PORTE2 2 ++#define PORTE1 1 ++#define PORTE0 0 ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCW _SFR_IO16(0x04) ++ ++#define ADCL _SFR_IO8(0x04) ++#define ADCH _SFR_IO8(0x05) ++ ++#define ADCSRA _SFR_IO8(0x06) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADMUX _SFR_IO8(0x07) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define ACSR _SFR_IO8(0x08) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define UBRR0L _SFR_IO8(0x09) ++ ++#define UCSR0B _SFR_IO8(0x0A) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0A _SFR_IO8(0x0B) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UDR0 _SFR_IO8(0x0C) ++ ++#define SPCR _SFR_IO8(0x0D) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x0E) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x0F) ++ ++#define PIND _SFR_IO8(0x10) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x11) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x12) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++#define PINC _SFR_IO8(0x13) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x14) ++#define DDRC7 7 ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x15) ++#define PORTC7 7 ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PINB _SFR_IO8(0x16) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x17) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x18) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINA _SFR_IO8(0x19) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x1A) ++#define DDRA7 7 ++#define DDRA6 6 ++#define DDRA5 5 ++#define DDRA4 4 ++#define DDRA3 3 ++#define DDRA2 2 ++#define DDRA1 1 ++#define DDRA0 0 ++ ++#define PORTA _SFR_IO8(0x1B) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define EECR _SFR_IO8(0x1C) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x1E) ++ ++#define EEARL _SFR_IO8(0x1E) ++#define EEARH _SFR_IO8(0x1F) ++ ++#define SFIOR _SFR_IO8(0x20) ++#define ACME 3 ++#define PSR321 0 ++#define PSR0 1 ++#define PUD 2 ++#define TSM 7 ++ ++#define WDTCR _SFR_IO8(0x21) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define OCDR _SFR_IO8(0x22) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCDR7 7 ++ ++#define OCR2 _SFR_IO8(0x23) ++ ++#define TCNT2 _SFR_IO8(0x24) ++ ++#define TCCR2 _SFR_IO8(0x25) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM21 3 ++#define COM20 4 ++#define COM21 5 ++#define WGM20 6 ++#define FOC2 7 ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_IO16(0x26) ++ ++#define ICR1L _SFR_IO8(0x26) ++#define ICR1H _SFR_IO8(0x27) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_IO16(0x28) ++ ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BH _SFR_IO8(0x29) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_IO16(0x2A) ++ ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_IO16(0x2C) ++ ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++ ++#define TCCR1B _SFR_IO8(0x2E) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1A _SFR_IO8(0x2F) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1C0 2 ++#define COM1C1 3 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define ASSR _SFR_IO8(0x30) ++#define TCR0UB 0 ++#define OCR0UB 1 ++#define TCN0UB 2 ++#define AS0 3 ++ ++#define OCR0 _SFR_IO8(0x31) ++ ++#define TCNT0 _SFR_IO8(0x32) ++ ++#define TCCR0 _SFR_IO8(0x33) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM01 3 ++#define COM00 4 ++#define COM01 5 ++#define WGM00 6 ++#define FOC0 7 ++ ++#define MCUCSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define JTRF 4 ++#define JTD 7 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define SM2 2 ++#define SM0 3 ++#define SM1 4 ++#define SE 5 ++#define SRW10 6 ++#define SRE 7 ++ ++#define TIFR _SFR_IO8(0x36) ++#define TOV0 0 ++#define OCF0 1 ++#define TOV1 2 ++#define OCF1B 3 ++#define OCF1A 4 ++#define ICF1 5 ++#define TOV2 6 ++#define OCF2 7 ++ ++#define TIMSK _SFR_IO8(0x37) ++#define TOIE0 0 ++#define OCIE0 1 ++#define TOIE1 2 ++#define OCIE1B 3 ++#define OCIE1A 4 ++#define TICIE1 5 ++#define TOIE2 6 ++#define OCIE2 7 ++ ++#define EIFR _SFR_IO8(0x38) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++#define INTF4 4 ++#define INTF5 5 ++#define INTF6 6 ++#define INTF7 7 ++ ++#define EIMSK _SFR_IO8(0x39) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++#define INT3 3 ++#define INT4 4 ++#define INT5 5 ++#define INT6 6 ++#define INT7 7 ++ ++#define EICRB _SFR_IO8(0x3A) ++#define ISC40 0 ++#define ISC41 1 ++#define ISC50 2 ++#define ISC51 3 ++#define ISC60 4 ++#define ISC61 5 ++#define ISC70 6 ++#define ISC71 7 ++ ++/* Reserved [0x3B] */ ++ ++#define XDIV _SFR_IO8(0x3C) ++#define XDIV0 0 ++#define XDIV1 1 ++#define XDIV2 2 ++#define XDIV3 3 ++#define XDIV4 4 ++#define XDIV5 5 ++#define XDIV6 6 ++#define XDIVEN 7 ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++/* Reserved [0x40..0x60] */ ++ ++#define DDRF _SFR_MEM8(0x61) ++#define DDRF7 7 ++#define DDRF6 6 ++#define DDRF5 5 ++#define DDRF4 4 ++#define DDRF3 3 ++#define DDRF2 2 ++#define DDRF1 1 ++#define DDRF0 0 ++ ++#define PORTF _SFR_MEM8(0x62) ++#define PORTF7 7 ++#define PORTF6 6 ++#define PORTF5 5 ++#define PORTF4 4 ++#define PORTF3 3 ++#define PORTF2 2 ++#define PORTF1 1 ++#define PORTF0 0 ++ ++#define PING _SFR_MEM8(0x63) ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++#define DDRG _SFR_MEM8(0x64) ++#define DDRG4 4 ++#define DDRG3 3 ++#define DDRG2 2 ++#define DDRG1 1 ++#define DDRG0 0 ++ ++#define PORTG _SFR_MEM8(0x65) ++#define PORTG4 4 ++#define PORTG3 3 ++#define PORTG2 2 ++#define PORTG1 1 ++#define PORTG0 0 ++ ++/* Reserved [0x66..0x67] */ ++ ++#define SPMCSR _SFR_MEM8(0x68) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x69] */ ++ ++#define EICRA _SFR_MEM8(0x6A) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++/* Reserved [0x6B] */ ++ ++#define XMCRB _SFR_MEM8(0x6C) ++#define XMM0 0 ++#define XMM1 1 ++#define XMM2 2 ++#define XMBK 7 ++ ++#define XMCRA _SFR_MEM8(0x6D) ++#define SRW11 1 ++#define SRW00 2 ++#define SRW01 3 ++#define SRL0 4 ++#define SRL1 5 ++#define SRL2 6 ++ ++/* Reserved [0x6E] */ ++ ++#define OSCCAL _SFR_MEM8(0x6F) ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++#define TWBR _SFR_MEM8(0x70) ++ ++#define TWSR _SFR_MEM8(0x71) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0x72) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0x73) ++ ++#define TWCR _SFR_MEM8(0x74) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++/* Reserved [0x75..0x77] */ ++ ++/* Combine OCR1CL and OCR1CH */ ++#define OCR1C _SFR_MEM16(0x78) ++ ++#define OCR1CL _SFR_MEM8(0x78) ++#define OCR1CH _SFR_MEM8(0x79) ++ ++#define TCCR1C _SFR_MEM8(0x7A) ++#define FOC1C 5 ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x7B] */ ++ ++#define ETIFR _SFR_MEM8(0x7C) ++#define OCF1C 0 ++#define OCF3C 1 ++#define TOV3 2 ++#define OCF3B 3 ++#define OCF3A 4 ++#define ICF3 5 ++ ++#define ETIMSK _SFR_MEM8(0x7D) ++#define OCIE1C 0 ++#define OCIE3C 1 ++#define TOIE3 2 ++#define OCIE3B 3 ++#define OCIE3A 4 ++#define TICIE3 5 ++ ++/* Reserved [0x7E..0x7F] */ ++ ++/* Combine ICR3L and ICR3H */ ++#define ICR3 _SFR_MEM16(0x80) ++ ++#define ICR3L _SFR_MEM8(0x80) ++#define ICR3H _SFR_MEM8(0x81) ++ ++/* Combine OCR3CL and OCR3CH */ ++#define OCR3C _SFR_MEM16(0x82) ++ ++#define OCR3CL _SFR_MEM8(0x82) ++#define OCR3CH _SFR_MEM8(0x83) ++ ++/* Combine OCR3BL and OCR3BH */ ++#define OCR3B _SFR_MEM16(0x84) ++ ++#define OCR3BL _SFR_MEM8(0x84) ++#define OCR3BH _SFR_MEM8(0x85) ++ ++/* Combine OCR3AL and OCR3AH */ ++#define OCR3A _SFR_MEM16(0x86) ++ ++#define OCR3AL _SFR_MEM8(0x86) ++#define OCR3AH _SFR_MEM8(0x87) ++ ++/* Combine TCNT3L and TCNT3H */ ++#define TCNT3 _SFR_MEM16(0x88) ++ ++#define TCNT3L _SFR_MEM8(0x88) ++#define TCNT3H _SFR_MEM8(0x89) ++ ++#define TCCR3B _SFR_MEM8(0x8A) ++#define CS30 0 ++#define CS31 1 ++#define CS32 2 ++#define WGM32 3 ++#define WGM33 4 ++#define ICES3 6 ++#define ICNC3 7 ++ ++#define TCCR3A _SFR_MEM8(0x8B) ++#define WGM30 0 ++#define WGM31 1 ++#define COM3C0 2 ++#define COM3C1 3 ++#define COM3B0 4 ++#define COM3B1 5 ++#define COM3A0 6 ++#define COM3A1 7 ++ ++#define TCCR3C _SFR_MEM8(0x8C) ++#define FOC3C 5 ++#define FOC3B 6 ++#define FOC3A 7 ++ ++/* Reserved [0x8D] */ ++ ++#define ADCSRB _SFR_MEM8(0x8E) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++ ++/* Reserved [0x8F] */ ++ ++#define UBRR0H _SFR_MEM8(0x90) ++ ++/* Reserved [0x91..0x94] */ ++ ++#define UCSR0C _SFR_MEM8(0x95) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL0 6 ++ ++/* Reserved [0x96..0x97] */ ++ ++#define UBRR1H _SFR_MEM8(0x98) ++ ++#define UBRR1L _SFR_MEM8(0x99) ++ ++#define UCSR1B _SFR_MEM8(0x9A) ++#define TXB81 0 ++#define RXB81 1 ++#define UCSZ12 2 ++#define TXEN1 3 ++#define RXEN1 4 ++#define UDRIE1 5 ++#define TXCIE1 6 ++#define RXCIE1 7 ++ ++#define UCSR1A _SFR_MEM8(0x9B) ++#define MPCM1 0 ++#define U2X1 1 ++#define UPE1 2 ++#define DOR1 3 ++#define FE1 4 ++#define UDRE1 5 ++#define TXC1 6 ++#define RXC1 7 ++ ++#define UDR1 _SFR_MEM8(0x9C) ++ ++#define UCSR1C _SFR_MEM8(0x9D) ++#define UCPOL1 0 ++#define UCSZ10 1 ++#define UCSZ11 2 ++#define USBS1 3 ++#define UPM10 4 ++#define UPM11 5 ++#define UMSEL1 6 ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect _VECTOR(3) ++#define INT2_vect_num 3 ++ ++/* External Interrupt Request 3 */ ++#define INT3_vect _VECTOR(4) ++#define INT3_vect_num 4 ++ ++/* External Interrupt Request 4 */ ++#define INT4_vect _VECTOR(5) ++#define INT4_vect_num 5 ++ ++/* External Interrupt Request 5 */ ++#define INT5_vect _VECTOR(6) ++#define INT5_vect_num 6 ++ ++/* External Interrupt Request 6 */ ++#define INT6_vect _VECTOR(7) ++#define INT6_vect_num 7 ++ ++/* External Interrupt Request 7 */ ++#define INT7_vect _VECTOR(8) ++#define INT7_vect_num 8 ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect _VECTOR(9) ++#define TIMER2_COMP_vect_num 9 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(10) ++#define TIMER2_OVF_vect_num 10 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(11) ++#define TIMER1_CAPT_vect_num 11 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(12) ++#define TIMER1_COMPA_vect_num 12 ++ ++/* Timer/Counter Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(13) ++#define TIMER1_COMPB_vect_num 13 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(14) ++#define TIMER1_OVF_vect_num 14 ++ ++/* Timer/Counter0 Compare Match */ ++#define TIMER0_COMP_vect _VECTOR(15) ++#define TIMER0_COMP_vect_num 15 ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(16) ++#define TIMER0_OVF_vect_num 16 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(17) ++#define SPI_STC_vect_num 17 ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect _VECTOR(18) ++#define USART0_RX_vect_num 18 ++ ++/* USART0 Data Register Empty */ ++#define USART0_UDRE_vect _VECTOR(19) ++#define USART0_UDRE_vect_num 19 ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect _VECTOR(20) ++#define USART0_TX_vect_num 20 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(21) ++#define ADC_vect_num 21 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(22) ++#define EE_READY_vect_num 22 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(23) ++#define ANALOG_COMP_vect_num 23 ++ ++/* Timer/Counter1 Compare Match C */ ++#define TIMER1_COMPC_vect _VECTOR(24) ++#define TIMER1_COMPC_vect_num 24 ++ ++/* Timer/Counter3 Capture Event */ ++#define TIMER3_CAPT_vect _VECTOR(25) ++#define TIMER3_CAPT_vect_num 25 ++ ++/* Timer/Counter3 Compare Match A */ ++#define TIMER3_COMPA_vect _VECTOR(26) ++#define TIMER3_COMPA_vect_num 26 ++ ++/* Timer/Counter3 Compare Match B */ ++#define TIMER3_COMPB_vect _VECTOR(27) ++#define TIMER3_COMPB_vect_num 27 ++ ++/* Timer/Counter3 Compare Match C */ ++#define TIMER3_COMPC_vect _VECTOR(28) ++#define TIMER3_COMPC_vect_num 28 ++ ++/* Timer/Counter3 Overflow */ ++#define TIMER3_OVF_vect _VECTOR(29) ++#define TIMER3_OVF_vect_num 29 ++ ++/* USART1, Rx Complete */ ++#define USART1_RX_vect _VECTOR(30) ++#define USART1_RX_vect_num 30 ++ ++/* USART1, Data Register Empty */ ++#define USART1_UDRE_vect _VECTOR(31) ++#define USART1_UDRE_vect_num 31 ++ ++/* USART1, Tx Complete */ ++#define USART1_TX_vect _VECTOR(32) ++#define USART1_TX_vect_num 32 ++ ++/* 2-wire Serial Interface */ ++#define TWI_vect _VECTOR(33) ++#define TWI_vect_num 33 ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect _VECTOR(34) ++#define SPM_READY_vect_num 34 ++ ++#define _VECTORS_SIZE 140 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 256 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0xFFFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 4096 ++#define RAMEND 0x10FF ++#define E2START 0 ++#define E2SIZE 2048 ++#define E2PAGESIZE 8 ++#define E2END 0x07FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_BODEN (unsigned char)~_BV(6) ++#define FUSE_BODLEVEL (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_CKOPT (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_WDTON (unsigned char)~_BV(0) ++#define FUSE_CompMode (unsigned char)~_BV(1) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x02 ++ ++ ++#endif /* #ifdef _AVR_ATMEGA64A_H_INCLUDED */ ++ +diff --git a/include/avr/iom64c1.h b/include/avr/iom64c1.h +index bf22e44..2c7b597 100644 +--- a/include/avr/iom64c1.h ++++ b/include/avr/iom64c1.h +@@ -1,1307 +1,1307 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom64c1.h 2183 2010-09-21 05:37:46Z aboyapati $ */ +- +-/* avr/iom64c1.h - definitions for ATmega64C1 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom64c1.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATmega64C1_H_ +-#define _AVR_ATmega64C1_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +-#define PINC7 7 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC3 3 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +-#define DDC7 7 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC3 3 +-#define PORTC4 4 +-#define PORTC5 5 +-#define PORTC6 6 +-#define PORTC7 7 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define PINE _SFR_IO8(0x0C) +-#define PINE0 0 +-#define PINE1 1 +-#define PINE2 2 +- +-#define DDRE _SFR_IO8(0x0D) +-#define DDE0 0 +-#define DDE1 1 +-#define DDE2 2 +- +-#define PORTE _SFR_IO8(0x0E) +-#define PORTE0 0 +-#define PORTE1 1 +-#define PORTE2 2 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define GPIOR1 _SFR_IO8(0x19) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x1A) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +-#define PCIF1 1 +-#define PCIF2 2 +-#define PCIF3 3 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +-#define INTF2 2 +-#define INTF3 3 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +-#define INT2 2 +-#define INT3 3 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEWE 1 +-#define EEMWE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +-#define EEAR9 1 +-#define EEAR10 2 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSR10 0 +-#define PSRSYNC 0 +-#define ICPSEL1 6 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define OCR0A _SFR_IO8(0x27) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define OCR0B _SFR_IO8(0x28) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define PLLCSR _SFR_IO8(0x29) +-#define PLOCK 0 +-#define PLLE 1 +-#define PLLF 2 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define ACSR _SFR_IO8(0x30) +-#define AC0O 0 +-#define AC1O 1 +-#define AC2O 2 +-#define AC3O 3 +-#define AC0IF 4 +-#define AC1IF 5 +-#define AC2IF 6 +-#define AC3IF 7 +- +-#define DWDR _SFR_IO8(0x31) +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define SPIPS 7 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define SIGRD 5 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRLIN 1 +-#define PRSPI 2 +-#define PRTIM0 3 +-#define PRTIM1 4 +-#define PRPSC 5 +-#define PRCAN 6 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +-#define PCIE1 1 +-#define PCIE2 2 +-#define PCIE3 3 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define ISC20 4 +-#define ISC21 5 +-#define ISC30 6 +-#define ISC31 7 +- +-#define PCMSK0 _SFR_MEM8(0x6A) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6B) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-#define PCMSK2 _SFR_MEM8(0x6C) +-#define PCINT16 0 +-#define PCINT17 1 +-#define PCINT18 2 +-#define PCINT19 3 +-#define PCINT20 4 +-#define PCINT21 5 +-#define PCINT22 6 +-#define PCINT23 7 +- +-#define PCMSK3 _SFR_MEM8(0x6D) +-#define PCINT24 0 +-#define PCINT25 1 +-#define PCINT26 2 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define AMP0CSR _SFR_MEM8(0x75) +-#define AMP0TS0 0 +-#define AMP0TS1 1 +-#define AMP0TS2 2 +-#define AMPCMP0 3 +-#define AMP0G0 4 +-#define AMP0G1 5 +-#define AMP0IS 6 +-#define AMP0EN 7 +- +-#define AMP1CSR _SFR_MEM8(0x76) +-#define AMP1TS0 0 +-#define AMP1TS1 1 +-#define AMP1TS2 2 +-#define AMPCMP1 3 +-#define AMP1G0 4 +-#define AMP1G1 5 +-#define AMP1IS 6 +-#define AMP1EN 7 +- +-#define AMP2CSR _SFR_MEM8(0x77) +-#define AMP2TS0 0 +-#define AMP2TS1 1 +-#define AMP2TS2 2 +-#define AMPCMP2 3 +-#define AMP2G0 4 +-#define AMP2G1 5 +-#define AMP2IS 6 +-#define AMP2EN 7 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +- +-#define ADCL _SFR_MEM8(0x78) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_MEM8(0x79) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ADTS3 3 +-#define AREFEN 5 +-#define ISRCEN 6 +-#define ADHSM 7 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define ADC8D 0 +-#define ADC9D 1 +-#define ADC10D 2 +-#define AMP0ND 3 +-#define AMP0PD 4 +-#define ACMP0D 5 +-#define AMP2PD 6 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define DACON _SFR_MEM8(0x90) +-#define DAEN 0 +-#define DAOE 1 +-#define DALA 2 +-#define DATS0 4 +-#define DATS1 5 +-#define DATS2 6 +-#define DAATE 7 +- +-#define DAC _SFR_MEM16(0x91) +- +-#define DACL _SFR_MEM8(0x91) +-#define DACL0 0 +-#define DACL1 1 +-#define DACL2 2 +-#define DACL3 3 +-#define DACL4 4 +-#define DACL5 5 +-#define DACL6 6 +-#define DACL7 7 +- +-#define DACH _SFR_MEM8(0x92) +-#define DACH0 0 +-#define DACH1 1 +-#define DACH2 2 +-#define DACH3 3 +-#define DACH4 4 +-#define DACH5 5 +-#define DACH6 6 +-#define DACH7 7 +- +-#define AC0CON _SFR_MEM8(0x94) +-#define AC0M0 0 +-#define AC0M1 1 +-#define AC0M2 2 +-#define ACCKSEL 3 +-#define AC0IS0 4 +-#define AC0IS1 5 +-#define AC0IE 6 +-#define AC0EN 7 +- +-#define AC1CON _SFR_MEM8(0x95) +-#define AC1M0 0 +-#define AC1M1 1 +-#define AC1M2 2 +-#define AC1ICE 3 +-#define AC1IS0 4 +-#define AC1IS1 5 +-#define AC1IE 6 +-#define AC1EN 7 +- +-#define AC2CON _SFR_MEM8(0x96) +-#define AC2M0 0 +-#define AC2M1 1 +-#define AC2M2 2 +-#define AC2IS0 4 +-#define AC2IS1 5 +-#define AC2IE 6 +-#define AC2EN 7 +- +-#define AC3CON _SFR_MEM8(0x97) +-#define AC3M0 0 +-#define AC3M1 1 +-#define AC3M2 2 +-#define AC3IS0 4 +-#define AC3IS1 5 +-#define AC3IE 6 +-#define AC3EN 7 +- +-#define LINCR _SFR_MEM8(0xC8) +-#define LCMD0 0 +-#define LCMD1 1 +-#define LCMD2 2 +-#define LENA 3 +-#define LCONF0 4 +-#define LCONF1 5 +-#define LIN13 6 +-#define LSWRES 7 +- +-#define LINSIR _SFR_MEM8(0xC9) +-#define LRXOK 0 +-#define LTXOK 1 +-#define LIDOK 2 +-#define LERR 3 +-#define LBUSY 4 +-#define LIDST0 5 +-#define LIDST1 6 +-#define LIDST2 7 +- +-#define LINENIR _SFR_MEM8(0xCA) +-#define LENRXOK 0 +-#define LENTXOK 1 +-#define LENIDOK 2 +-#define LENERR 3 +- +-#define LINERR _SFR_MEM8(0xCB) +-#define LBERR 0 +-#define LCERR 1 +-#define LPERR 2 +-#define LSERR 3 +-#define LFERR 4 +-#define LOVERR 5 +-#define LTOERR 6 +-#define LABORT 7 +- +-#define LINBTR _SFR_MEM8(0xCC) +-#define LBT0 0 +-#define LBT1 1 +-#define LBT2 2 +-#define LBT3 3 +-#define LBT4 4 +-#define LBT5 5 +-#define LDISR 7 +- +-#define LINBRR _SFR_MEM16(0xCD) +- +-#define LINBRRL _SFR_MEM8(0xCD) +-#define LDIV0 0 +-#define LDIV1 1 +-#define LDIV2 2 +-#define LDIV3 3 +-#define LDIV4 4 +-#define LDIV5 5 +-#define LDIV6 6 +-#define LDIV7 7 +- +-#define LINBRRH _SFR_MEM8(0xCE) +-#define LDIV8 0 +-#define LDIV9 1 +-#define LDIV10 2 +-#define LDIV11 3 +- +-#define LINDLR _SFR_MEM8(0xCF) +-#define LRXDL0 0 +-#define LRXDL1 1 +-#define LRXDL2 2 +-#define LRXDL3 3 +-#define LTXDL0 4 +-#define LTXDL1 5 +-#define LTXDL2 6 +-#define LTXDL3 7 +- +-#define LINIDR _SFR_MEM8(0xD0) +-#define LID0 0 +-#define LID1 1 +-#define LID2 2 +-#define LID3 3 +-#define LID4 4 +-#define LID5 5 +-#define LP0 6 +-#define LP1 7 +- +-#define LINSEL _SFR_MEM8(0xD1) +-#define LINDX0 0 +-#define LINDX1 1 +-#define LINDX2 2 +-#define LAINC 3 +- +-#define LINDAT _SFR_MEM8(0xD2) +-#define LDATA0 0 +-#define LDATA1 1 +-#define LDATA2 2 +-#define LDATA3 3 +-#define LDATA4 4 +-#define LDATA5 5 +-#define LDATA6 6 +-#define LDATA7 7 +- +-#define CANGCON _SFR_MEM8(0xD8) +-#define SWRES 0 +-#define ENASTB 1 +-#define TEST 2 +-#define LISTEN 3 +-#define SYNTTC 4 +-#define TTC 5 +-#define OVRQ 6 +-#define ABRQ 7 +- +-#define CANGSTA _SFR_MEM8(0xD9) +-#define ERRP 0 +-#define BOFF 1 +-#define ENFG 2 +-#define RXBSY 3 +-#define TXBSY 4 +-#define OVFG 6 +- +-#define CANGIT _SFR_MEM8(0xDA) +-#define AERG 0 +-#define FERG 1 +-#define CERG 2 +-#define SERG 3 +-#define BXOK 4 +-#define OVRTIM 5 +-#define BOFFIT 6 +-#define CANIT 7 +- +-#define CANGIE _SFR_MEM8(0xDB) +-#define ENOVRT 0 +-#define ENERG 1 +-#define ENBX 2 +-#define ENERR 3 +-#define ENTX 4 +-#define ENRX 5 +-#define ENBOFF 6 +-#define ENIT 7 +- +-#define CANEN2 _SFR_MEM8(0xDC) +-#define ENMOB0 0 +-#define ENMOB1 1 +-#define ENMOB2 2 +-#define ENMOB3 3 +-#define ENMOB4 4 +-#define ENMOB5 5 +- +-#define CANEN1 _SFR_MEM8(0xDD) +- +-#define CANIE2 _SFR_MEM8(0xDE) +-#define IEMOB0 0 +-#define IEMOB1 1 +-#define IEMOB2 2 +-#define IEMOB3 3 +-#define IEMOB4 4 +-#define IEMOB5 5 +- +-#define CANIE1 _SFR_MEM8(0xDF) +- +-/* RegDef: CAN Status Interrupt MOb Register*/ +-#define CANSIT _SFR_MEM16(0xE0) +- +-#define CANSIT2 _SFR_MEM8(0xE0) +-#define SIT0 0 +-#define SIT1 1 +-#define SIT2 2 +-#define SIT3 3 +-#define SIT4 4 +-#define SIT5 5 +- +-#define CANSIT1 _SFR_MEM8(0xE1) +- +-#define CANBT1 _SFR_MEM8(0xE2) +-#define BRP0 1 +-#define BRP1 2 +-#define BRP2 3 +-#define BRP3 4 +-#define BRP4 5 +-#define BRP5 6 +- +-#define CANBT2 _SFR_MEM8(0xE3) +-#define PRS0 1 +-#define PRS1 2 +-#define PRS2 3 +-#define SJW0 5 +-#define SJW1 6 +- +-#define CANBT3 _SFR_MEM8(0xE4) +-#define SMP 0 +-#define PHS10 1 +-#define PHS11 2 +-#define PHS12 3 +-#define PHS20 4 +-#define PHS21 5 +-#define PHS22 6 +- +-#define CANTCON _SFR_MEM8(0xE5) +-#define TPRSC0 0 +-#define TPRSC1 1 +-#define TPRSC2 2 +-#define TPRSC3 3 +-#define TPRSC4 4 +-#define TPRSC5 5 +-#define TPRSC6 6 +-#define TPRSC7 7 +- +-#define CANTIM _SFR_MEM16(0xE6) +- +-#define CANTIML _SFR_MEM8(0xE6) +-#define CANTIM0 0 +-#define CANTIM1 1 +-#define CANTIM2 2 +-#define CANTIM3 3 +-#define CANTIM4 4 +-#define CANTIM5 5 +-#define CANTIM6 6 +-#define CANTIM7 7 +- +-#define CANTIMH _SFR_MEM8(0xE7) +-#define CANTIM8 0 +-#define CANTIM9 1 +-#define CANTIM10 2 +-#define CANTIM11 3 +-#define CANTIM12 4 +-#define CANTIM13 5 +-#define CANTIM14 6 +-#define CANTIM15 7 +- +-#define CANTTC _SFR_MEM16(0xE8) +- +-#define CANTTCL _SFR_MEM8(0xE8) +-#define TIMTCC0 0 +-#define TIMTCC1 1 +-#define TIMTCC2 2 +-#define TIMTCC3 3 +-#define TIMTCC4 4 +-#define TIMTCC5 5 +-#define TIMTCC6 6 +-#define TIMTCC7 7 +- +-#define CANTTCH _SFR_MEM8(0xE9) +-#define TIMTCC8 0 +-#define TIMTCC9 1 +-#define TIMTCC10 2 +-#define TIMTCC11 3 +-#define TIMTCC12 4 +-#define TIMTCC13 5 +-#define TIMTCC14 6 +-#define TIMTCC15 7 +- +-#define CANTEC _SFR_MEM8(0xEA) +-#define TEC0 0 +-#define TEC1 1 +-#define TEC2 2 +-#define TEC3 3 +-#define TEC4 4 +-#define TEC5 5 +-#define TEC6 6 +-#define TEC7 7 +- +-#define CANREC _SFR_MEM8(0xEB) +-#define REC0 0 +-#define REC1 1 +-#define REC2 2 +-#define REC3 3 +-#define REC4 4 +-#define REC5 5 +-#define REC6 6 +-#define REC7 7 +- +-#define CANHPMOB _SFR_MEM8(0xEC) +-#define CGP0 0 +-#define CGP1 1 +-#define CGP2 2 +-#define CGP3 3 +-#define HPMOB0 4 +-#define HPMOB1 5 +-#define HPMOB2 6 +-#define HPMOB3 7 +- +-#define CANPAGE _SFR_MEM8(0xED) +-#define INDX0 0 +-#define INDX1 1 +-#define INDX2 2 +-#define AINC 3 +-#define MOBNB0 4 +-#define MOBNB1 5 +-#define MOBNB2 6 +-#define MOBNB3 7 +- +-#define CANSTMOB _SFR_MEM8(0xEE) +-#define AERR 0 +-#define FERR 1 +-#define CERR 2 +-#define SERR 3 +-#define BERR 4 +-#define RXOK 5 +-#define TXOK 6 +-#define DLCW 7 +- +-#define CANCDMOB _SFR_MEM8(0xEF) +-#define DLC0 0 +-#define DLC1 1 +-#define DLC2 2 +-#define DLC3 3 +-#define IDE 4 +-#define RPLV 5 +-#define CONMOB0 6 +-#define CONMOB1 7 +- +-/* RegDef: CAN Identifier Tag Registers*/ +-#define CANIDT _SFR_MEM32(0xF0) +- +-#define CANIDT4 _SFR_MEM8(0xF0) +-#define RB0TAG 0 +-#define RB1TAG 1 +-#define RTRTAG 2 +-#define IDT0 3 +-#define IDT1 4 +-#define IDT2 5 +-#define IDT3 6 +-#define IDT4 7 +- +-#define CANIDT3 _SFR_MEM8(0xF1) +-#define IDT5 0 +-#define IDT6 1 +-#define IDT7 2 +-#define IDT8 3 +-#define IDT9 4 +-#define IDT10 5 +-#define IDT11 6 +-#define IDT12 7 +- +-#define CANIDT2 _SFR_MEM8(0xF2) +-#define IDT13 0 +-#define IDT14 1 +-#define IDT15 2 +-#define IDT16 3 +-#define IDT17 4 +-#define IDT18 5 +-#define IDT19 6 +-#define IDT20 7 +- +-#define CANIDT1 _SFR_MEM8(0xF3) +-#define IDT21 0 +-#define IDT22 1 +-#define IDT23 2 +-#define IDT24 3 +-#define IDT25 4 +-#define IDT26 5 +-#define IDT27 6 +-#define IDT28 7 +- +-/* RegDef: CAN Identifier Mask Registers */ +-#define CANIDM _SFR_MEM32(0xF4) +- +-#define CANIDM4 _SFR_MEM8(0xF4) +-#define IDEMSK 0 +-#define RTRMSK 2 +-#define IDMSK0 3 +-#define IDMSK1 4 +-#define IDMSK2 5 +-#define IDMSK3 6 +-#define IDMSK4 7 +- +-#define CANIDM3 _SFR_MEM8(0xF5) +-#define IDMSK5 0 +-#define IDMSK6 1 +-#define IDMSK7 2 +-#define IDMSK8 3 +-#define IDMSK9 4 +-#define IDMSK10 5 +-#define IDMSK11 6 +-#define IDMSK12 7 +- +-#define CANIDM2 _SFR_MEM8(0xF6) +-#define IDMSK13 0 +-#define IDMSK14 1 +-#define IDMSK15 2 +-#define IDMSK16 3 +-#define IDMSK17 4 +-#define IDMSK18 5 +-#define IDMSK19 6 +-#define IDMSK20 7 +- +-#define CANIDM1 _SFR_MEM8(0xF7) +-#define IDMSK21 0 +-#define IDMSK22 1 +-#define IDMSK23 2 +-#define IDMSK24 3 +-#define IDMSK25 4 +-#define IDMSK26 5 +-#define IDMSK27 6 +-#define IDMSK28 7 +- +-#define CANSTM _SFR_MEM16(0xF8) +- +-#define CANSTML _SFR_MEM8(0xF8) +-#define TIMSTM0 0 +-#define TIMSTM1 1 +-#define TIMSTM2 2 +-#define TIMSTM3 3 +-#define TIMSTM4 4 +-#define TIMSTM5 5 +-#define TIMSTM6 6 +-#define TIMSTM7 7 +- +-#define CANSTMH _SFR_MEM8(0xF9) +-#define TIMSTM8 0 +-#define TIMSTM9 1 +-#define TIMSTM10 2 +-#define TIMSTM11 3 +-#define TIMSTM12 4 +-#define TIMSTM13 5 +-#define TIMSTM14 6 +-#define TIMSTM15 7 +- +-#define CANMSG _SFR_MEM8(0xFA) +-#define MSG0 0 +-#define MSG1 1 +-#define MSG2 2 +-#define MSG3 3 +-#define MSG4 4 +-#define MSG5 5 +-#define MSG6 6 +-#define MSG7 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define ANACOMP0_vect_num 1 +-#define ANACOMP0_vect _VECTOR(1) /* Analog Comparator 0 */ +-#define ANACOMP1_vect_num 2 +-#define ANACOMP1_vect _VECTOR(2) /* Analog Comparator 1 */ +-#define ANACOMP2_vect_num 3 +-#define ANACOMP2_vect _VECTOR(3) /* Analog Comparator 2 */ +-#define ANACOMP3_vect_num 4 +-#define ANACOMP3_vect _VECTOR(4) /* Analog Comparator 3 */ +-#define PSC_FAULT_vect_num 5 +-#define PSC_FAULT_vect _VECTOR(5) /* PSC Fault */ +-#define PSC_EC_vect_num 6 +-#define PSC_EC_vect _VECTOR(6) /* PSC End of Cycle */ +-#define INT0_vect_num 7 +-#define INT0_vect _VECTOR(7) /* External Interrupt Request 0 */ +-#define INT1_vect_num 8 +-#define INT1_vect _VECTOR(8) /* External Interrupt Request 1 */ +-#define INT2_vect_num 9 +-#define INT2_vect _VECTOR(9) /* External Interrupt Request 2 */ +-#define INT3_vect_num 10 +-#define INT3_vect _VECTOR(10) /* External Interrupt Request 3 */ +-#define TIMER1_CAPT_vect_num 11 +-#define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */ +-#define TIMER1_COMPA_vect_num 12 +-#define TIMER1_COMPA_vect _VECTOR(12) /* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPB_vect_num 13 +-#define TIMER1_COMPB_vect _VECTOR(13) /* Timer/Counter1 Compare Match B */ +-#define TIMER1_OVF_vect_num 14 +-#define TIMER1_OVF_vect _VECTOR(14) /* Timer1/Counter1 Overflow */ +-#define TIMER0_COMPA_vect_num 15 +-#define TIMER0_COMPA_vect _VECTOR(15) /* Timer/Counter0 Compare Match A */ +-#define TIMER0_COMPB_vect_num 16 +-#define TIMER0_COMPB_vect _VECTOR(16) /* Timer/Counter0 Compare Match B */ +-#define TIMER0_OVF_vect_num 17 +-#define TIMER0_OVF_vect _VECTOR(17) /* Timer/Counter0 Overflow */ +-#define CAN_INT_vect_num 18 +-#define CAN_INT_vect _VECTOR(18) /* CAN MOB, Burst, General Errors */ +-#define CAN_TOVF_vect_num 19 +-#define CAN_TOVF_vect _VECTOR(19) /* CAN Timer Overflow */ +-#define LIN_TC_vect_num 20 +-#define LIN_TC_vect _VECTOR(20) /* LIN Transfer Complete */ +-#define LIN_ERR_vect_num 21 +-#define LIN_ERR_vect _VECTOR(21) /* LIN Error */ +-#define PCINT0_vect_num 22 +-#define PCINT0_vect _VECTOR(22) /* Pin Change Interrupt Request 0 */ +-#define PCINT1_vect_num 23 +-#define PCINT1_vect _VECTOR(23) /* Pin Change Interrupt Request 1 */ +-#define PCINT2_vect_num 24 +-#define PCINT2_vect _VECTOR(24) /* Pin Change Interrupt Request 2 */ +-#define PCINT3_vect_num 25 +-#define PCINT3_vect _VECTOR(25) /* Pin Change Interrupt Request 3 */ +-#define SPI_STC_vect_num 26 +-#define SPI_STC_vect _VECTOR(26) /* SPI Serial Transfer Complete */ +-#define ADC_vect_num 27 +-#define ADC_vect _VECTOR(27) /* ADC Conversion Complete */ +-#define WDT_vect_num 28 +-#define WDT_vect _VECTOR(28) /* Watchdog Time-Out Interrupt */ +-#define EE_READY_vect_num 29 +-#define EE_READY_vect _VECTOR(29) /* EEPROM Ready */ +-#define SPM_READY_vect_num 30 +-#define SPM_READY_vect _VECTOR(30) /* Store Program Memory Read */ +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (31 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (256) +-#define RAMSTART (0x0100) +-#define RAMSIZE (4096) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (0x0) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x7FF) +-#define E2PAGESIZE (8) +-#define FLASHEND (0xFFFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector Trigger Level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector Trigger Level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector Trigger Level */ +-#define FUSE_PSCRVB (unsigned char)~_BV(3) /* PSC Outputs xB Reset Value */ +-#define FUSE_PSCRVA (unsigned char)~_BV(4) /* PSC Outputs xA Reset Value */ +-#define FUSE_PSCRB (unsigned char)~_BV(5) /* PSC Reset Behavior */ +-#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_BODLEVEL1) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x96 +-#define SIGNATURE_2 0x86 +- +- +-#endif /* _AVR_ATmega64C1_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom64c1.h 2183 2010-09-21 05:37:46Z aboyapati $ */ ++ ++/* avr/iom64c1.h - definitions for ATmega64C1 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom64c1.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATmega64C1_H_ ++#define _AVR_ATmega64C1_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++#define PINC7 7 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++#define DDC7 7 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC3 3 ++#define PORTC4 4 ++#define PORTC5 5 ++#define PORTC6 6 ++#define PORTC7 7 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE0 0 ++#define PINE1 1 ++#define PINE2 2 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE0 0 ++#define DDE1 1 ++#define DDE2 2 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE0 0 ++#define PORTE1 1 ++#define PORTE2 2 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define GPIOR1 _SFR_IO8(0x19) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x1A) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++#define PCIF3 3 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++#define INT3 3 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++#define EEAR9 1 ++#define EEAR10 2 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR10 0 ++#define PSRSYNC 0 ++#define ICPSEL1 6 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define OCR0A _SFR_IO8(0x27) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define OCR0B _SFR_IO8(0x28) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define PLLCSR _SFR_IO8(0x29) ++#define PLOCK 0 ++#define PLLE 1 ++#define PLLF 2 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define ACSR _SFR_IO8(0x30) ++#define AC0O 0 ++#define AC1O 1 ++#define AC2O 2 ++#define AC3O 3 ++#define AC0IF 4 ++#define AC1IF 5 ++#define AC2IF 6 ++#define AC3IF 7 ++ ++#define DWDR _SFR_IO8(0x31) ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define SPIPS 7 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRLIN 1 ++#define PRSPI 2 ++#define PRTIM0 3 ++#define PRTIM1 4 ++#define PRPSC 5 ++#define PRCAN 6 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++#define PCIE3 3 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++#define PCMSK0 _SFR_MEM8(0x6A) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6B) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK2 _SFR_MEM8(0x6C) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define PCMSK3 _SFR_MEM8(0x6D) ++#define PCINT24 0 ++#define PCINT25 1 ++#define PCINT26 2 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define AMP0CSR _SFR_MEM8(0x75) ++#define AMP0TS0 0 ++#define AMP0TS1 1 ++#define AMP0TS2 2 ++#define AMPCMP0 3 ++#define AMP0G0 4 ++#define AMP0G1 5 ++#define AMP0IS 6 ++#define AMP0EN 7 ++ ++#define AMP1CSR _SFR_MEM8(0x76) ++#define AMP1TS0 0 ++#define AMP1TS1 1 ++#define AMP1TS2 2 ++#define AMPCMP1 3 ++#define AMP1G0 4 ++#define AMP1G1 5 ++#define AMP1IS 6 ++#define AMP1EN 7 ++ ++#define AMP2CSR _SFR_MEM8(0x77) ++#define AMP2TS0 0 ++#define AMP2TS1 1 ++#define AMP2TS2 2 ++#define AMPCMP2 3 ++#define AMP2G0 4 ++#define AMP2G1 5 ++#define AMP2IS 6 ++#define AMP2EN 7 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_MEM8(0x79) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ADTS3 3 ++#define AREFEN 5 ++#define ISRCEN 6 ++#define ADHSM 7 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define ADC8D 0 ++#define ADC9D 1 ++#define ADC10D 2 ++#define AMP0ND 3 ++#define AMP0PD 4 ++#define ACMP0D 5 ++#define AMP2PD 6 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define DACON _SFR_MEM8(0x90) ++#define DAEN 0 ++#define DAOE 1 ++#define DALA 2 ++#define DATS0 4 ++#define DATS1 5 ++#define DATS2 6 ++#define DAATE 7 ++ ++#define DAC _SFR_MEM16(0x91) ++ ++#define DACL _SFR_MEM8(0x91) ++#define DACL0 0 ++#define DACL1 1 ++#define DACL2 2 ++#define DACL3 3 ++#define DACL4 4 ++#define DACL5 5 ++#define DACL6 6 ++#define DACL7 7 ++ ++#define DACH _SFR_MEM8(0x92) ++#define DACH0 0 ++#define DACH1 1 ++#define DACH2 2 ++#define DACH3 3 ++#define DACH4 4 ++#define DACH5 5 ++#define DACH6 6 ++#define DACH7 7 ++ ++#define AC0CON _SFR_MEM8(0x94) ++#define AC0M0 0 ++#define AC0M1 1 ++#define AC0M2 2 ++#define ACCKSEL 3 ++#define AC0IS0 4 ++#define AC0IS1 5 ++#define AC0IE 6 ++#define AC0EN 7 ++ ++#define AC1CON _SFR_MEM8(0x95) ++#define AC1M0 0 ++#define AC1M1 1 ++#define AC1M2 2 ++#define AC1ICE 3 ++#define AC1IS0 4 ++#define AC1IS1 5 ++#define AC1IE 6 ++#define AC1EN 7 ++ ++#define AC2CON _SFR_MEM8(0x96) ++#define AC2M0 0 ++#define AC2M1 1 ++#define AC2M2 2 ++#define AC2IS0 4 ++#define AC2IS1 5 ++#define AC2IE 6 ++#define AC2EN 7 ++ ++#define AC3CON _SFR_MEM8(0x97) ++#define AC3M0 0 ++#define AC3M1 1 ++#define AC3M2 2 ++#define AC3IS0 4 ++#define AC3IS1 5 ++#define AC3IE 6 ++#define AC3EN 7 ++ ++#define LINCR _SFR_MEM8(0xC8) ++#define LCMD0 0 ++#define LCMD1 1 ++#define LCMD2 2 ++#define LENA 3 ++#define LCONF0 4 ++#define LCONF1 5 ++#define LIN13 6 ++#define LSWRES 7 ++ ++#define LINSIR _SFR_MEM8(0xC9) ++#define LRXOK 0 ++#define LTXOK 1 ++#define LIDOK 2 ++#define LERR 3 ++#define LBUSY 4 ++#define LIDST0 5 ++#define LIDST1 6 ++#define LIDST2 7 ++ ++#define LINENIR _SFR_MEM8(0xCA) ++#define LENRXOK 0 ++#define LENTXOK 1 ++#define LENIDOK 2 ++#define LENERR 3 ++ ++#define LINERR _SFR_MEM8(0xCB) ++#define LBERR 0 ++#define LCERR 1 ++#define LPERR 2 ++#define LSERR 3 ++#define LFERR 4 ++#define LOVERR 5 ++#define LTOERR 6 ++#define LABORT 7 ++ ++#define LINBTR _SFR_MEM8(0xCC) ++#define LBT0 0 ++#define LBT1 1 ++#define LBT2 2 ++#define LBT3 3 ++#define LBT4 4 ++#define LBT5 5 ++#define LDISR 7 ++ ++#define LINBRR _SFR_MEM16(0xCD) ++ ++#define LINBRRL _SFR_MEM8(0xCD) ++#define LDIV0 0 ++#define LDIV1 1 ++#define LDIV2 2 ++#define LDIV3 3 ++#define LDIV4 4 ++#define LDIV5 5 ++#define LDIV6 6 ++#define LDIV7 7 ++ ++#define LINBRRH _SFR_MEM8(0xCE) ++#define LDIV8 0 ++#define LDIV9 1 ++#define LDIV10 2 ++#define LDIV11 3 ++ ++#define LINDLR _SFR_MEM8(0xCF) ++#define LRXDL0 0 ++#define LRXDL1 1 ++#define LRXDL2 2 ++#define LRXDL3 3 ++#define LTXDL0 4 ++#define LTXDL1 5 ++#define LTXDL2 6 ++#define LTXDL3 7 ++ ++#define LINIDR _SFR_MEM8(0xD0) ++#define LID0 0 ++#define LID1 1 ++#define LID2 2 ++#define LID3 3 ++#define LID4 4 ++#define LID5 5 ++#define LP0 6 ++#define LP1 7 ++ ++#define LINSEL _SFR_MEM8(0xD1) ++#define LINDX0 0 ++#define LINDX1 1 ++#define LINDX2 2 ++#define LAINC 3 ++ ++#define LINDAT _SFR_MEM8(0xD2) ++#define LDATA0 0 ++#define LDATA1 1 ++#define LDATA2 2 ++#define LDATA3 3 ++#define LDATA4 4 ++#define LDATA5 5 ++#define LDATA6 6 ++#define LDATA7 7 ++ ++#define CANGCON _SFR_MEM8(0xD8) ++#define SWRES 0 ++#define ENASTB 1 ++#define TEST 2 ++#define LISTEN 3 ++#define SYNTTC 4 ++#define TTC 5 ++#define OVRQ 6 ++#define ABRQ 7 ++ ++#define CANGSTA _SFR_MEM8(0xD9) ++#define ERRP 0 ++#define BOFF 1 ++#define ENFG 2 ++#define RXBSY 3 ++#define TXBSY 4 ++#define OVFG 6 ++ ++#define CANGIT _SFR_MEM8(0xDA) ++#define AERG 0 ++#define FERG 1 ++#define CERG 2 ++#define SERG 3 ++#define BXOK 4 ++#define OVRTIM 5 ++#define BOFFIT 6 ++#define CANIT 7 ++ ++#define CANGIE _SFR_MEM8(0xDB) ++#define ENOVRT 0 ++#define ENERG 1 ++#define ENBX 2 ++#define ENERR 3 ++#define ENTX 4 ++#define ENRX 5 ++#define ENBOFF 6 ++#define ENIT 7 ++ ++#define CANEN2 _SFR_MEM8(0xDC) ++#define ENMOB0 0 ++#define ENMOB1 1 ++#define ENMOB2 2 ++#define ENMOB3 3 ++#define ENMOB4 4 ++#define ENMOB5 5 ++ ++#define CANEN1 _SFR_MEM8(0xDD) ++ ++#define CANIE2 _SFR_MEM8(0xDE) ++#define IEMOB0 0 ++#define IEMOB1 1 ++#define IEMOB2 2 ++#define IEMOB3 3 ++#define IEMOB4 4 ++#define IEMOB5 5 ++ ++#define CANIE1 _SFR_MEM8(0xDF) ++ ++/* RegDef: CAN Status Interrupt MOb Register*/ ++#define CANSIT _SFR_MEM16(0xE0) ++ ++#define CANSIT2 _SFR_MEM8(0xE0) ++#define SIT0 0 ++#define SIT1 1 ++#define SIT2 2 ++#define SIT3 3 ++#define SIT4 4 ++#define SIT5 5 ++ ++#define CANSIT1 _SFR_MEM8(0xE1) ++ ++#define CANBT1 _SFR_MEM8(0xE2) ++#define BRP0 1 ++#define BRP1 2 ++#define BRP2 3 ++#define BRP3 4 ++#define BRP4 5 ++#define BRP5 6 ++ ++#define CANBT2 _SFR_MEM8(0xE3) ++#define PRS0 1 ++#define PRS1 2 ++#define PRS2 3 ++#define SJW0 5 ++#define SJW1 6 ++ ++#define CANBT3 _SFR_MEM8(0xE4) ++#define SMP 0 ++#define PHS10 1 ++#define PHS11 2 ++#define PHS12 3 ++#define PHS20 4 ++#define PHS21 5 ++#define PHS22 6 ++ ++#define CANTCON _SFR_MEM8(0xE5) ++#define TPRSC0 0 ++#define TPRSC1 1 ++#define TPRSC2 2 ++#define TPRSC3 3 ++#define TPRSC4 4 ++#define TPRSC5 5 ++#define TPRSC6 6 ++#define TPRSC7 7 ++ ++#define CANTIM _SFR_MEM16(0xE6) ++ ++#define CANTIML _SFR_MEM8(0xE6) ++#define CANTIM0 0 ++#define CANTIM1 1 ++#define CANTIM2 2 ++#define CANTIM3 3 ++#define CANTIM4 4 ++#define CANTIM5 5 ++#define CANTIM6 6 ++#define CANTIM7 7 ++ ++#define CANTIMH _SFR_MEM8(0xE7) ++#define CANTIM8 0 ++#define CANTIM9 1 ++#define CANTIM10 2 ++#define CANTIM11 3 ++#define CANTIM12 4 ++#define CANTIM13 5 ++#define CANTIM14 6 ++#define CANTIM15 7 ++ ++#define CANTTC _SFR_MEM16(0xE8) ++ ++#define CANTTCL _SFR_MEM8(0xE8) ++#define TIMTCC0 0 ++#define TIMTCC1 1 ++#define TIMTCC2 2 ++#define TIMTCC3 3 ++#define TIMTCC4 4 ++#define TIMTCC5 5 ++#define TIMTCC6 6 ++#define TIMTCC7 7 ++ ++#define CANTTCH _SFR_MEM8(0xE9) ++#define TIMTCC8 0 ++#define TIMTCC9 1 ++#define TIMTCC10 2 ++#define TIMTCC11 3 ++#define TIMTCC12 4 ++#define TIMTCC13 5 ++#define TIMTCC14 6 ++#define TIMTCC15 7 ++ ++#define CANTEC _SFR_MEM8(0xEA) ++#define TEC0 0 ++#define TEC1 1 ++#define TEC2 2 ++#define TEC3 3 ++#define TEC4 4 ++#define TEC5 5 ++#define TEC6 6 ++#define TEC7 7 ++ ++#define CANREC _SFR_MEM8(0xEB) ++#define REC0 0 ++#define REC1 1 ++#define REC2 2 ++#define REC3 3 ++#define REC4 4 ++#define REC5 5 ++#define REC6 6 ++#define REC7 7 ++ ++#define CANHPMOB _SFR_MEM8(0xEC) ++#define CGP0 0 ++#define CGP1 1 ++#define CGP2 2 ++#define CGP3 3 ++#define HPMOB0 4 ++#define HPMOB1 5 ++#define HPMOB2 6 ++#define HPMOB3 7 ++ ++#define CANPAGE _SFR_MEM8(0xED) ++#define INDX0 0 ++#define INDX1 1 ++#define INDX2 2 ++#define AINC 3 ++#define MOBNB0 4 ++#define MOBNB1 5 ++#define MOBNB2 6 ++#define MOBNB3 7 ++ ++#define CANSTMOB _SFR_MEM8(0xEE) ++#define AERR 0 ++#define FERR 1 ++#define CERR 2 ++#define SERR 3 ++#define BERR 4 ++#define RXOK 5 ++#define TXOK 6 ++#define DLCW 7 ++ ++#define CANCDMOB _SFR_MEM8(0xEF) ++#define DLC0 0 ++#define DLC1 1 ++#define DLC2 2 ++#define DLC3 3 ++#define IDE 4 ++#define RPLV 5 ++#define CONMOB0 6 ++#define CONMOB1 7 ++ ++/* RegDef: CAN Identifier Tag Registers*/ ++#define CANIDT _SFR_MEM32(0xF0) ++ ++#define CANIDT4 _SFR_MEM8(0xF0) ++#define RB0TAG 0 ++#define RB1TAG 1 ++#define RTRTAG 2 ++#define IDT0 3 ++#define IDT1 4 ++#define IDT2 5 ++#define IDT3 6 ++#define IDT4 7 ++ ++#define CANIDT3 _SFR_MEM8(0xF1) ++#define IDT5 0 ++#define IDT6 1 ++#define IDT7 2 ++#define IDT8 3 ++#define IDT9 4 ++#define IDT10 5 ++#define IDT11 6 ++#define IDT12 7 ++ ++#define CANIDT2 _SFR_MEM8(0xF2) ++#define IDT13 0 ++#define IDT14 1 ++#define IDT15 2 ++#define IDT16 3 ++#define IDT17 4 ++#define IDT18 5 ++#define IDT19 6 ++#define IDT20 7 ++ ++#define CANIDT1 _SFR_MEM8(0xF3) ++#define IDT21 0 ++#define IDT22 1 ++#define IDT23 2 ++#define IDT24 3 ++#define IDT25 4 ++#define IDT26 5 ++#define IDT27 6 ++#define IDT28 7 ++ ++/* RegDef: CAN Identifier Mask Registers */ ++#define CANIDM _SFR_MEM32(0xF4) ++ ++#define CANIDM4 _SFR_MEM8(0xF4) ++#define IDEMSK 0 ++#define RTRMSK 2 ++#define IDMSK0 3 ++#define IDMSK1 4 ++#define IDMSK2 5 ++#define IDMSK3 6 ++#define IDMSK4 7 ++ ++#define CANIDM3 _SFR_MEM8(0xF5) ++#define IDMSK5 0 ++#define IDMSK6 1 ++#define IDMSK7 2 ++#define IDMSK8 3 ++#define IDMSK9 4 ++#define IDMSK10 5 ++#define IDMSK11 6 ++#define IDMSK12 7 ++ ++#define CANIDM2 _SFR_MEM8(0xF6) ++#define IDMSK13 0 ++#define IDMSK14 1 ++#define IDMSK15 2 ++#define IDMSK16 3 ++#define IDMSK17 4 ++#define IDMSK18 5 ++#define IDMSK19 6 ++#define IDMSK20 7 ++ ++#define CANIDM1 _SFR_MEM8(0xF7) ++#define IDMSK21 0 ++#define IDMSK22 1 ++#define IDMSK23 2 ++#define IDMSK24 3 ++#define IDMSK25 4 ++#define IDMSK26 5 ++#define IDMSK27 6 ++#define IDMSK28 7 ++ ++#define CANSTM _SFR_MEM16(0xF8) ++ ++#define CANSTML _SFR_MEM8(0xF8) ++#define TIMSTM0 0 ++#define TIMSTM1 1 ++#define TIMSTM2 2 ++#define TIMSTM3 3 ++#define TIMSTM4 4 ++#define TIMSTM5 5 ++#define TIMSTM6 6 ++#define TIMSTM7 7 ++ ++#define CANSTMH _SFR_MEM8(0xF9) ++#define TIMSTM8 0 ++#define TIMSTM9 1 ++#define TIMSTM10 2 ++#define TIMSTM11 3 ++#define TIMSTM12 4 ++#define TIMSTM13 5 ++#define TIMSTM14 6 ++#define TIMSTM15 7 ++ ++#define CANMSG _SFR_MEM8(0xFA) ++#define MSG0 0 ++#define MSG1 1 ++#define MSG2 2 ++#define MSG3 3 ++#define MSG4 4 ++#define MSG5 5 ++#define MSG6 6 ++#define MSG7 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define ANACOMP0_vect_num 1 ++#define ANACOMP0_vect _VECTOR(1) /* Analog Comparator 0 */ ++#define ANACOMP1_vect_num 2 ++#define ANACOMP1_vect _VECTOR(2) /* Analog Comparator 1 */ ++#define ANACOMP2_vect_num 3 ++#define ANACOMP2_vect _VECTOR(3) /* Analog Comparator 2 */ ++#define ANACOMP3_vect_num 4 ++#define ANACOMP3_vect _VECTOR(4) /* Analog Comparator 3 */ ++#define PSC_FAULT_vect_num 5 ++#define PSC_FAULT_vect _VECTOR(5) /* PSC Fault */ ++#define PSC_EC_vect_num 6 ++#define PSC_EC_vect _VECTOR(6) /* PSC End of Cycle */ ++#define INT0_vect_num 7 ++#define INT0_vect _VECTOR(7) /* External Interrupt Request 0 */ ++#define INT1_vect_num 8 ++#define INT1_vect _VECTOR(8) /* External Interrupt Request 1 */ ++#define INT2_vect_num 9 ++#define INT2_vect _VECTOR(9) /* External Interrupt Request 2 */ ++#define INT3_vect_num 10 ++#define INT3_vect _VECTOR(10) /* External Interrupt Request 3 */ ++#define TIMER1_CAPT_vect_num 11 ++#define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */ ++#define TIMER1_COMPA_vect_num 12 ++#define TIMER1_COMPA_vect _VECTOR(12) /* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPB_vect_num 13 ++#define TIMER1_COMPB_vect _VECTOR(13) /* Timer/Counter1 Compare Match B */ ++#define TIMER1_OVF_vect_num 14 ++#define TIMER1_OVF_vect _VECTOR(14) /* Timer1/Counter1 Overflow */ ++#define TIMER0_COMPA_vect_num 15 ++#define TIMER0_COMPA_vect _VECTOR(15) /* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPB_vect_num 16 ++#define TIMER0_COMPB_vect _VECTOR(16) /* Timer/Counter0 Compare Match B */ ++#define TIMER0_OVF_vect_num 17 ++#define TIMER0_OVF_vect _VECTOR(17) /* Timer/Counter0 Overflow */ ++#define CAN_INT_vect_num 18 ++#define CAN_INT_vect _VECTOR(18) /* CAN MOB, Burst, General Errors */ ++#define CAN_TOVF_vect_num 19 ++#define CAN_TOVF_vect _VECTOR(19) /* CAN Timer Overflow */ ++#define LIN_TC_vect_num 20 ++#define LIN_TC_vect _VECTOR(20) /* LIN Transfer Complete */ ++#define LIN_ERR_vect_num 21 ++#define LIN_ERR_vect _VECTOR(21) /* LIN Error */ ++#define PCINT0_vect_num 22 ++#define PCINT0_vect _VECTOR(22) /* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect_num 23 ++#define PCINT1_vect _VECTOR(23) /* Pin Change Interrupt Request 1 */ ++#define PCINT2_vect_num 24 ++#define PCINT2_vect _VECTOR(24) /* Pin Change Interrupt Request 2 */ ++#define PCINT3_vect_num 25 ++#define PCINT3_vect _VECTOR(25) /* Pin Change Interrupt Request 3 */ ++#define SPI_STC_vect_num 26 ++#define SPI_STC_vect _VECTOR(26) /* SPI Serial Transfer Complete */ ++#define ADC_vect_num 27 ++#define ADC_vect _VECTOR(27) /* ADC Conversion Complete */ ++#define WDT_vect_num 28 ++#define WDT_vect _VECTOR(28) /* Watchdog Time-Out Interrupt */ ++#define EE_READY_vect_num 29 ++#define EE_READY_vect _VECTOR(29) /* EEPROM Ready */ ++#define SPM_READY_vect_num 30 ++#define SPM_READY_vect _VECTOR(30) /* Store Program Memory Read */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (31 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (256) ++#define RAMSTART (0x0100) ++#define RAMSIZE (4096) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (0x0) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x7FF) ++#define E2PAGESIZE (8) ++#define FLASHEND (0xFFFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector Trigger Level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector Trigger Level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector Trigger Level */ ++#define FUSE_PSCRVB (unsigned char)~_BV(3) /* PSC Outputs xB Reset Value */ ++#define FUSE_PSCRVA (unsigned char)~_BV(4) /* PSC Outputs xA Reset Value */ ++#define FUSE_PSCRB (unsigned char)~_BV(5) /* PSC Reset Behavior */ ++#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_BODLEVEL1) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x86 ++ ++ ++#endif /* _AVR_ATmega64C1_H_ */ ++ +diff --git a/include/avr/iom64hve.h b/include/avr/iom64hve.h +index a86cd29..80f6a01 100644 +--- a/include/avr/iom64hve.h ++++ b/include/avr/iom64hve.h +@@ -1,1020 +1,1020 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom64hve.h 2086 2009-12-15 03:24:16Z arcanum $ */ +- +-/* avr/iom64hve.h - definitions for ATmega64HVE */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom64hve.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATmega64HVE_H_ +-#define _AVR_ATmega64HVE_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA0 0 +-#define PINA1 1 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA0 0 +-#define DDA1 1 +- +-#define PORTA _SFR_IO8(0x02) +-#define PORTA0 0 +-#define PORTA1 1 +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +-#define ICF0 3 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 3 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +-#define PCIF1 1 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +-#define EEAR9 1 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSRSYNC 0 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define ICS0 3 +-#define ICES0 4 +-#define ICNC0 5 +-#define ICEN0 6 +-#define TCW0 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +- +-#define TCNT0 _SFR_IO16(0x26) +- +-#define TCNT0L _SFR_IO8(0x26) +-#define TCNT0L0 0 +-#define TCNT0L1 1 +-#define TCNT0L2 2 +-#define TCNT0L3 3 +-#define TCNT0L4 4 +-#define TCNT0L5 5 +-#define TCNT0L6 6 +-#define TCNT0L7 7 +- +-#define TCNT0H _SFR_IO8(0x27) +-#define TCNT0H0 0 +-#define TCNT0H1 1 +-#define TCNT0H2 2 +-#define TCNT0H3 3 +-#define TCNT0H4 4 +-#define TCNT0H5 5 +-#define TCNT0H6 6 +-#define TCNT0H7 7 +- +-#define OCR0A _SFR_IO8(0x28) +-#define OCR0A0 0 +-#define OCR0A1 1 +-#define OCR0A2 2 +-#define OCR0A3 3 +-#define OCR0A4 4 +-#define OCR0A5 5 +-#define OCR0A6 6 +-#define OCR0A7 7 +- +-#define OCR0B _SFR_IO8(0x29) +-#define OCR0B0 0 +-#define OCR0B1 1 +-#define OCR0B2 2 +-#define OCR0B3 3 +-#define OCR0B4 4 +-#define OCR0B5 5 +-#define OCR0B6 6 +-#define OCR0B7 7 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define TCCR0C _SFR_IO8(0x2F) +- +-#define OCDR _SFR_IO8(0x31) +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BODRF 2 +-#define WDRF 3 +-#define OCDRF 4 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define CKOE 5 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define LBSET 3 +-#define RWWSRE 4 +-#define SIGRD 5 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPCE 7 +- +-#define WUTCSR _SFR_MEM8(0x62) +-#define WUTP0 0 +-#define WUTP1 1 +-#define WUTP2 2 +-#define WUTE 3 +-#define WUTR 4 +-#define WUTIE 6 +-#define WUTIF 7 +- +-#define WDTCLR _SFR_MEM8(0x63) +-#define WDCLE 0 +-#define WDCL0 1 +-#define WDCL1 2 +- +-#define PRR0 _SFR_MEM8(0x64) +-#define PRTIM0 0 +-#define PRTIM1 1 +-#define PRSPI 2 +-#define PRLIN 3 +- +-#define SOSCCALA _SFR_MEM8(0x66) +-#define SCALA0 0 +-#define SCALA1 1 +-#define SCALA2 2 +-#define SCALA3 3 +-#define SCALA4 4 +-#define SCALA5 5 +-#define SCALA6 6 +-#define SCALA7 7 +- +-#define SOSCCALB _SFR_MEM8(0x67) +-#define SCALB0 0 +-#define SCALB1 1 +-#define SCALB2 2 +-#define SCALB3 3 +-#define SCALB4 4 +-#define SCALB5 5 +-#define SCALB6 6 +-#define SCALB7 7 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +-#define PCIE1 1 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT2 0 +-#define PCINT3 1 +-#define PCINT4 2 +-#define PCINT5 3 +-#define PCINT6 4 +-#define PCINT7 5 +-#define PCINT8 6 +-#define PCINT9 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +-#define ICIE0 3 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 3 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define PA0DID 0 +-#define PA1DID 1 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define ICS1 3 +-#define ICES1 4 +-#define ICNC1 5 +-#define ICEN1 6 +-#define TCW1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +- +-#define TCCR1C _SFR_MEM8(0x82) +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define OCR1A _SFR_MEM8(0x88) +-#define OCR1A0 0 +-#define OCR1A1 1 +-#define OCR1A2 2 +-#define OCR1A3 3 +-#define OCR1A4 4 +-#define OCR1A5 5 +-#define OCR1A6 6 +-#define OCR1A7 7 +- +-#define OCR1B _SFR_MEM8(0x89) +-#define OCR1B0 0 +-#define OCR1B1 1 +-#define OCR1B2 2 +-#define OCR1B3 3 +-#define OCR1B4 4 +-#define OCR1B5 5 +-#define OCR1B6 6 +-#define OCR1B7 7 +- +-#define LINCR _SFR_MEM8(0xC0) +-#define LCMD0 0 +-#define LCMD1 1 +-#define LCMD2 2 +-#define LENA 3 +-#define LCONF0 4 +-#define LCONF1 5 +-#define LIN13 6 +-#define LSWRES 7 +- +-#define LINSIR _SFR_MEM8(0xC1) +-#define LRXOK 0 +-#define LTXOK 1 +-#define LIDOK 2 +-#define LERR 3 +-#define LBUSY 4 +-#define LIDST0 5 +-#define LIDST1 6 +-#define LIDST2 7 +- +-#define LINENIR _SFR_MEM8(0xC2) +-#define LENRXOK 0 +-#define LENTXOK 1 +-#define LENIDOK 2 +-#define LENERR 3 +- +-#define LINERR _SFR_MEM8(0xC3) +-#define LBERR 0 +-#define LCERR 1 +-#define LPERR 2 +-#define LSERR 3 +-#define LFERR 4 +-#define LOVERR 5 +-#define LTOERR 6 +-#define LABORT 7 +- +-#define LINBTR _SFR_MEM8(0xC4) +-#define LBT0 0 +-#define LBT1 1 +-#define LBT2 2 +-#define LBT3 3 +-#define LBT4 4 +-#define LBT5 5 +-#define LDISR 7 +- +-#define LINBRR _SFR_MEM16(0xC5) +- +-#define LINBRRL _SFR_MEM8(0xC5) +-#define LDIV0 0 +-#define LDIV1 1 +-#define LDIV2 2 +-#define LDIV3 3 +-#define LDIV4 4 +-#define LDIV5 5 +-#define LDIV6 6 +-#define LDIV7 7 +- +-#define LINBRRH _SFR_MEM8(0xC6) +-#define LDIV8 0 +-#define LDIV9 1 +-#define LDIV10 2 +-#define LDIV11 3 +- +-#define LINDLR _SFR_MEM8(0xC7) +-#define LRXDL0 0 +-#define LRXDL1 1 +-#define LRXDL2 2 +-#define LRXDL3 3 +-#define LTXDL0 4 +-#define LTXDL1 5 +-#define LTXDL2 6 +-#define LTXDL3 7 +- +-#define LINIDR _SFR_MEM8(0xC8) +-#define LID0 0 +-#define LID1 1 +-#define LID2 2 +-#define LID3 3 +-#define LID4 4 +-#define LID5 5 +-#define LP0 6 +-#define LP1 7 +- +-#define LINSEL _SFR_MEM8(0xC9) +-#define LINDX0 0 +-#define LINDX1 1 +-#define LINDX2 2 +-#define LAINC 3 +- +-#define LINDAT _SFR_MEM8(0xCA) +-#define LDATA0 0 +-#define LDATA1 1 +-#define LDATA2 2 +-#define LDATA3 3 +-#define LDATA4 4 +-#define LDATA5 5 +-#define LDATA6 6 +-#define LDATA7 7 +- +-#define BGCSRA _SFR_MEM8(0xD1) +-#define BGSC0 0 +-#define BGSC1 1 +-#define BGSC2 2 +- +-#define BGCRB _SFR_MEM8(0xD2) +-#define BGCL0 0 +-#define BGCL1 1 +-#define BGCL2 2 +-#define BGCL3 3 +-#define BGCL4 4 +-#define BGCL5 5 +-#define BGCL6 6 +-#define BGCL7 7 +- +-#define BGCRA _SFR_MEM8(0xD3) +-#define BGCN0 0 +-#define BGCN1 1 +-#define BGCN2 2 +-#define BGCN3 3 +-#define BGCN4 4 +-#define BGCN5 5 +-#define BGCN6 6 +-#define BGCN7 7 +- +-#define BGLR _SFR_MEM8(0xD4) +-#define BGPL 0 +-#define BGPLE 1 +- +-#define PLLCSR _SFR_MEM8(0xD8) +-#define PLLCIE 0 +-#define PLLCIF 1 +-#define LOCK 4 +-#define SWEN 5 +- +-#define PBOV _SFR_MEM8(0xDC) +-#define PBOE0 0 +-#define PBOE3 3 +-#define PBOVCE 7 +- +-#define ADSCSRA _SFR_MEM8(0xE0) +-#define SCMD0 0 +-#define SCMD1 1 +-#define SBSY 2 +- +-#define ADSCSRB _SFR_MEM8(0xE1) +-#define CADICRB 0 +-#define CADACRB 1 +-#define CADICPS 2 +-#define VADICRB 4 +-#define VADACRB 5 +-#define VADICPS 6 +- +-#define ADCRA _SFR_MEM8(0xE2) +-#define CKSEL 0 +-#define ADCMS0 1 +-#define ADCMS1 2 +-#define ADPSEL 3 +- +-#define ADCRB _SFR_MEM8(0xE3) +-#define ADADES0 0 +-#define ADADES1 1 +-#define ADADES2 2 +-#define ADIDES0 3 +-#define ADIDES1 4 +- +-#define ADCRC _SFR_MEM8(0xE4) +-#define CADRCT0 0 +-#define CADRCT1 1 +-#define CADRCT2 2 +-#define CADRCT3 3 +-#define CADRCM0 4 +-#define CADRCM1 5 +-#define CADEN 7 +- +-#define ADCRD _SFR_MEM8(0xE5) +-#define CADDSEL 0 +-#define CADPDM0 1 +-#define CADPDM1 2 +-#define CADG0 3 +-#define CADG1 4 +-#define CADG2 5 +- +-#define ADCRE _SFR_MEM8(0xE6) +-#define VADMUX0 0 +-#define VADMUX1 1 +-#define VADMUX2 2 +-#define VADPDM0 3 +-#define VADPDM1 4 +-#define VADREFS 5 +-#define VADEN 7 +- +-#define ADIFR _SFR_MEM8(0xE7) +-#define CADICIF 0 +-#define CADACIF 1 +-#define CADRCIF 2 +-#define VADICIF 4 +-#define VADACIF 5 +- +-#define ADIMR _SFR_MEM8(0xE8) +-#define CADICIE 0 +-#define CADACIE 1 +-#define CADRCIE 2 +-#define VADICIE 4 +-#define VADACIE 5 +- +-#define CADRCL _SFR_MEM16(0xE9) +- +-#define CADRCLL _SFR_MEM8(0xE9) +-#define CADRCL0 0 +-#define CADRCL1 1 +-#define CADRCL2 2 +-#define CADRCL3 3 +-#define CADRCL4 4 +-#define CADRCL5 5 +-#define CADRCL6 6 +-#define CADRCL7 7 +- +-#define CADRCLH _SFR_MEM8(0xEA) +-#define CADRCL8 0 +-#define CADRCL9 1 +-#define CADRCL10 2 +-#define CADRCL11 3 +-#define CADRCL12 4 +-#define CADRCL13 5 +-#define CADRCL14 6 +-#define CADRCL15 7 +- +-#define CADIC _SFR_MEM16(0xEB) +- +-#define CADICL _SFR_MEM8(0xEB) +-#define CADIC0 0 +-#define CADIC1 1 +-#define CADIC2 2 +-#define CADIC3 3 +-#define CADIC4 4 +-#define CADIC5 5 +-#define CADIC6 6 +-#define CADIC7 7 +- +-#define CADICH _SFR_MEM8(0xEC) +-#define CADIC8 0 +-#define CADIC9 1 +-#define CADIC10 2 +-#define CADIC11 3 +-#define CADIC12 4 +-#define CADIC13 5 +-#define CADIC14 6 +-#define CADIC15 7 +- +-#define CADAC0 _SFR_MEM8(0xED) +-#define CADAC00 0 +-#define CADAC01 1 +-#define CADAC02 2 +-#define CADAC03 3 +-#define CADAC04 4 +-#define CADAC05 5 +-#define CADAC06 6 +-#define CADAC07 7 +- +-#define CADAC1 _SFR_MEM8(0xEE) +-#define CADAC08 0 +-#define CADAC09 1 +-#define CADAC10 2 +-#define CADAC11 3 +-#define CADAC12 4 +-#define CADAC13 5 +-#define CADAC14 6 +-#define CADAC15 7 +- +-#define CADAC2 _SFR_MEM8(0xEF) +-#define CADAC16 0 +-#define CADAC17 1 +-#define CADAC18 2 +-#define CADAC19 3 +-#define CADAC20 4 +-#define CADAC21 5 +-#define CADAC22 6 +-#define CADAC23 7 +- +-#define CADAC3 _SFR_MEM8(0xF0) +-#define CADAC24 0 +-#define CADAC25 1 +-#define CADAC26 2 +-#define CADAC27 3 +-#define CADAC28 4 +-#define CADAC29 5 +-#define CADAC30 6 +-#define CADAC31 7 +- +-#define VADIC _SFR_MEM16(0xF1) +- +-#define VADICL _SFR_MEM8(0xF1) +-#define VADIC0 0 +-#define VADIC1 1 +-#define VADIC2 2 +-#define VADIC3 3 +-#define VADIC4 4 +-#define VADIC5 5 +-#define VADIC6 6 +-#define VADIC7 7 +- +-#define VADICH _SFR_MEM8(0xF2) +-#define VADIC8 0 +-#define VADIC9 1 +-#define VADIC10 2 +-#define VADIC11 3 +-#define VADIC12 4 +-#define VADIC13 5 +-#define VADIC14 6 +-#define VADIC15 7 +- +-#define VADAC0 _SFR_MEM8(0xF3) +-#define VADAC00 0 +-#define VADAC01 1 +-#define VADAC02 2 +-#define VADAC03 3 +-#define VADAC04 4 +-#define VADAC05 5 +-#define VADAC06 6 +-#define VADAC07 7 +- +-#define VADAC1 _SFR_MEM8(0xF4) +-#define VADAC08 0 +-#define VADAC09 1 +-#define VADAC10 2 +-#define VADAC11 3 +-#define VADAC12 4 +-#define VADAC13 5 +-#define VADAC14 6 +-#define VADAC15 7 +- +-#define VADAC2 _SFR_MEM8(0xF5) +-#define VADAC16 0 +-#define VADAC17 1 +-#define VADAC18 2 +-#define VADAC19 3 +-#define VADAC20 4 +-#define VADAC21 5 +-#define VADAC22 6 +-#define VADAC23 7 +- +-#define VADAC3 _SFR_MEM8(0xF6) +-#define VADAC24 0 +-#define VADAC25 1 +-#define VADAC26 2 +-#define VADAC27 3 +-#define VADAC28 4 +-#define VADAC29 5 +-#define VADAC30 6 +-#define VADAC31 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt 0 */ +-#define PCINT1_vect_num 3 +-#define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt 1 */ +-#define WDT_vect_num 4 +-#define WDT_vect _VECTOR(4) /* Watchdog Timeout Interrupt */ +-#define WAKEUP_vect_num 5 +-#define WAKEUP_vect _VECTOR(5) /* Wakeup Timer Overflow */ +-#define TIMER1_IC_vect_num 6 +-#define TIMER1_IC_vect _VECTOR(6) /* Timer 1 Input capture */ +-#define TIMER1_COMPA_vect_num 7 +-#define TIMER1_COMPA_vect _VECTOR(7) /* Timer 1 Compare Match A */ +-#define TIMER1_COMPB_vect_num 8 +-#define TIMER1_COMPB_vect _VECTOR(8) /* Timer 1 Compare Match B */ +-#define TIMER1_OVF_vect_num 9 +-#define TIMER1_OVF_vect _VECTOR(9) /* Timer 1 overflow */ +-#define TIMER0_IC_vect_num 10 +-#define TIMER0_IC_vect _VECTOR(10) /* Timer 0 Input Capture */ +-#define TIMER0_COMPA_vect_num 11 +-#define TIMER0_COMPA_vect _VECTOR(11) /* Timer 0 Comapre Match A */ +-#define TIMER0_COMPB_vect_num 12 +-#define TIMER0_COMPB_vect _VECTOR(12) /* Timer 0 Compare Match B */ +-#define TIMER0_OVF_vect_num 13 +-#define TIMER0_OVF_vect _VECTOR(13) /* Timer 0 Overflow */ +-#define LIN_STATUS_vect_num 14 +-#define LIN_STATUS_vect _VECTOR(14) /* LIN Status Interrupt */ +-#define LIN_ERROR_vect_num 15 +-#define LIN_ERROR_vect _VECTOR(15) /* LIN Error Interrupt */ +-#define SPI_STC_vect_num 16 +-#define SPI_STC_vect _VECTOR(16) /* SPI Serial transfer complete */ +-#define VADC_CONV_vect_num 17 +-#define VADC_CONV_vect _VECTOR(17) /* Voltage ADC Instantaneous Conversion Complete */ +-#define VADC_ACC_vect_num 18 +-#define VADC_ACC_vect _VECTOR(18) /* Voltage ADC Accumulated Conversion Complete */ +-#define CADC_CONV_vect_num 19 +-#define CADC_CONV_vect _VECTOR(19) /* C-ADC Instantaneous Conversion Complete */ +-#define CADC_REG_CUR_vect_num 20 +-#define CADC_REG_CUR_vect _VECTOR(20) /* C-ADC Regular Current */ +-#define CADC_ACC_vect_num 21 +-#define CADC_ACC_vect _VECTOR(21) /* C-ADC Accumulated Conversion Complete */ +-#define EE_READY_vect_num 22 +-#define EE_READY_vect _VECTOR(22) /* EEPROM Ready */ +-#define SPM_vect_num 23 +-#define SPM_vect _VECTOR(23) /* SPM Ready */ +-#define PLL_vect_num 24 +-#define PLL_vect _VECTOR(24) /* PLL Lock Change Interrupt */ +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (25 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (128) +-#define RAMSTART (0x100) +-#define RAMSIZE (4096) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (NA) +-#define XRAMEND (RAMEND) +-#define E2END (0x3FF) +-#define E2PAGESIZE (4) +-#define FLASHEND (0xFFFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 2 +- +-/* Low Fuse Byte */ +-#define FUSE_OSCSEL0 (unsigned char)~_BV(0) /* Oscillator Select */ +-#define FUSE_SUT0 (unsigned char)~_BV(1) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(2) /* Select start-up time */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(3) /* Divide clock by 8 */ +-#define FUSE_BODEN (unsigned char)~_BV(4) /* Enable BOD */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_EESAVE (unsigned char)~_BV(6) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(7) /* Watchdog Timer Always On */ +-#define LFUSE_DEFAULT (FUSE_SPIEN & FUSE_CKDIV8 & FUSE_OSCSEL0) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_DWEN (unsigned char)~_BV(3) /* Enable debugWire */ +-#define HFUSE_DEFAULT (FUSE_BOOTSZ1 & FUSE_BOOTSZ0) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x96 +-#define SIGNATURE_2 0x10 +- +- +-/* Device Pin Definitions */ +-#define PV2_DDR DDRV +-#define PV2_PORT PORTV +-#define PV2_PIN PINV +-#define PV2_BIT 2 +- +-#define PV1_DDR DDRV +-#define PV1_PORT PORTV +-#define PV1_PIN PINV +-#define PV1_BIT 1 +- +-#define NV_DDR DDRNV +-#define NV_PORT PORTNV +-#define NV_PIN PINNV +-#define NV_BIT NV +- +-#define VFET_DDR DDRVFET +-#define VFET_PORT PORTVFET +-#define VFET_PIN PINVFET +-#define VFET_BIT VFET +- +-#define CF1P_DDR DDRCF1P +-#define CF1P_PORT PORTCF1P +-#define CF1P_PIN PINCF1P +-#define CF1P_BIT CF1P +- +-#define CF1N_DDR DDRCF1N +-#define CF1N_PORT PORTCF1N +-#define CF1N_PIN PINCF1N +-#define CF1N_BIT CF1N +- +-#define CF2P_DDR DDRCF2P +-#define CF2P_PORT PORTCF2P +-#define CF2P_PIN PINCF2P +-#define CF2P_BIT CF2P +- +-#define CF2N_DDR DDRCF2N +-#define CF2N_PORT PORTCF2N +-#define CF2N_PIN PINCF2N +-#define CF2N_BIT CF2N +- +-#define VREG_DDR DDRVREG +-#define VREG_PORT PORTVREG +-#define VREG_PIN PINVREG +-#define VREG_BIT VREG +- +-#define VREF_DDR DDRVREF +-#define VREF_PORT PORTVREF +-#define VREF_PIN PINVREF +-#define VREF_BIT VREF +- +-#define VREFGND_DDR DDRVREFGND +-#define VREFGND_PORT PORTVREFGND +-#define VREFGND_PIN PINVREFGND +-#define VREFGND_BIT VREFGND +- +-#define PI_DDR DDRI +-#define PI_PORT PORTI +-#define PI_PIN PINI +-#define PI_BIT +- +-#define NI_DDR DDRNI +-#define NI_PORT PORTNI +-#define NI_PIN PINNI +-#define NI_BIT NI +- +-#define PA0_DDR DDRA +-#define PA0_PORT PORTA +-#define PA0_PIN PINA +-#define PA0_BIT 0 +- +-#define PA1_DDR DDRA +-#define PA1_PORT PORTA +-#define PA1_PIN PINA +-#define PA1_BIT 1 +- +-#define PA2_DDR DDRA +-#define PA2_PORT PORTA +-#define PA2_PIN PINA +-#define PA2_BIT 2 +- +-#define PB0_DDR DDRB +-#define PB0_PORT PORTB +-#define PB0_PIN PINB +-#define PB0_BIT 0 +- +-#define PB1_DDR DDRB +-#define PB1_PORT PORTB +-#define PB1_PIN PINB +-#define PB1_BIT 1 +- +-#define PB2_DDR DDRB +-#define PB2_PORT PORTB +-#define PB2_PIN PINB +-#define PB2_BIT 2 +- +-#define PB3_DDR DDRB +-#define PB3_PORT PORTB +-#define PB3_PIN PINB +-#define PB3_BIT 3 +- +-#define PC0_DDR DDRC +-#define PC0_PORT PORTC +-#define PC0_PIN PINC +-#define PC0_BIT 0 +- +-#define BATT_DDR DDRBATT +-#define BATT_PORT PORTBATT +-#define BATT_PIN PINBATT +-#define BATT_BIT BATT +- +-#define OC_DDR DDROC +-#define OC_PORT PORTOC +-#define OC_PIN PINOC +-#define OC_BIT OC +- +-#endif /* _AVR_ATmega64HVE_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom64hve.h 2086 2009-12-15 03:24:16Z arcanum $ */ ++ ++/* avr/iom64hve.h - definitions for ATmega64HVE */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom64hve.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATmega64HVE_H_ ++#define _AVR_ATmega64HVE_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA0 0 ++#define PINA1 1 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA0 0 ++#define DDA1 1 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA0 0 ++#define PORTA1 1 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++#define ICF0 3 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 3 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++#define EEAR9 1 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define ICS0 3 ++#define ICES0 4 ++#define ICNC0 5 ++#define ICEN0 6 ++#define TCW0 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++ ++#define TCNT0 _SFR_IO16(0x26) ++ ++#define TCNT0L _SFR_IO8(0x26) ++#define TCNT0L0 0 ++#define TCNT0L1 1 ++#define TCNT0L2 2 ++#define TCNT0L3 3 ++#define TCNT0L4 4 ++#define TCNT0L5 5 ++#define TCNT0L6 6 ++#define TCNT0L7 7 ++ ++#define TCNT0H _SFR_IO8(0x27) ++#define TCNT0H0 0 ++#define TCNT0H1 1 ++#define TCNT0H2 2 ++#define TCNT0H3 3 ++#define TCNT0H4 4 ++#define TCNT0H5 5 ++#define TCNT0H6 6 ++#define TCNT0H7 7 ++ ++#define OCR0A _SFR_IO8(0x28) ++#define OCR0A0 0 ++#define OCR0A1 1 ++#define OCR0A2 2 ++#define OCR0A3 3 ++#define OCR0A4 4 ++#define OCR0A5 5 ++#define OCR0A6 6 ++#define OCR0A7 7 ++ ++#define OCR0B _SFR_IO8(0x29) ++#define OCR0B0 0 ++#define OCR0B1 1 ++#define OCR0B2 2 ++#define OCR0B3 3 ++#define OCR0B4 4 ++#define OCR0B5 5 ++#define OCR0B6 6 ++#define OCR0B7 7 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define TCCR0C _SFR_IO8(0x2F) ++ ++#define OCDR _SFR_IO8(0x31) ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BODRF 2 ++#define WDRF 3 ++#define OCDRF 4 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define CKOE 5 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define LBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPCE 7 ++ ++#define WUTCSR _SFR_MEM8(0x62) ++#define WUTP0 0 ++#define WUTP1 1 ++#define WUTP2 2 ++#define WUTE 3 ++#define WUTR 4 ++#define WUTIE 6 ++#define WUTIF 7 ++ ++#define WDTCLR _SFR_MEM8(0x63) ++#define WDCLE 0 ++#define WDCL0 1 ++#define WDCL1 2 ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRTIM0 0 ++#define PRTIM1 1 ++#define PRSPI 2 ++#define PRLIN 3 ++ ++#define SOSCCALA _SFR_MEM8(0x66) ++#define SCALA0 0 ++#define SCALA1 1 ++#define SCALA2 2 ++#define SCALA3 3 ++#define SCALA4 4 ++#define SCALA5 5 ++#define SCALA6 6 ++#define SCALA7 7 ++ ++#define SOSCCALB _SFR_MEM8(0x67) ++#define SCALB0 0 ++#define SCALB1 1 ++#define SCALB2 2 ++#define SCALB3 3 ++#define SCALB4 4 ++#define SCALB5 5 ++#define SCALB6 6 ++#define SCALB7 7 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT2 0 ++#define PCINT3 1 ++#define PCINT4 2 ++#define PCINT5 3 ++#define PCINT6 4 ++#define PCINT7 5 ++#define PCINT8 6 ++#define PCINT9 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++#define ICIE0 3 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 3 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define PA0DID 0 ++#define PA1DID 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define ICS1 3 ++#define ICES1 4 ++#define ICNC1 5 ++#define ICEN1 6 ++#define TCW1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define OCR1A _SFR_MEM8(0x88) ++#define OCR1A0 0 ++#define OCR1A1 1 ++#define OCR1A2 2 ++#define OCR1A3 3 ++#define OCR1A4 4 ++#define OCR1A5 5 ++#define OCR1A6 6 ++#define OCR1A7 7 ++ ++#define OCR1B _SFR_MEM8(0x89) ++#define OCR1B0 0 ++#define OCR1B1 1 ++#define OCR1B2 2 ++#define OCR1B3 3 ++#define OCR1B4 4 ++#define OCR1B5 5 ++#define OCR1B6 6 ++#define OCR1B7 7 ++ ++#define LINCR _SFR_MEM8(0xC0) ++#define LCMD0 0 ++#define LCMD1 1 ++#define LCMD2 2 ++#define LENA 3 ++#define LCONF0 4 ++#define LCONF1 5 ++#define LIN13 6 ++#define LSWRES 7 ++ ++#define LINSIR _SFR_MEM8(0xC1) ++#define LRXOK 0 ++#define LTXOK 1 ++#define LIDOK 2 ++#define LERR 3 ++#define LBUSY 4 ++#define LIDST0 5 ++#define LIDST1 6 ++#define LIDST2 7 ++ ++#define LINENIR _SFR_MEM8(0xC2) ++#define LENRXOK 0 ++#define LENTXOK 1 ++#define LENIDOK 2 ++#define LENERR 3 ++ ++#define LINERR _SFR_MEM8(0xC3) ++#define LBERR 0 ++#define LCERR 1 ++#define LPERR 2 ++#define LSERR 3 ++#define LFERR 4 ++#define LOVERR 5 ++#define LTOERR 6 ++#define LABORT 7 ++ ++#define LINBTR _SFR_MEM8(0xC4) ++#define LBT0 0 ++#define LBT1 1 ++#define LBT2 2 ++#define LBT3 3 ++#define LBT4 4 ++#define LBT5 5 ++#define LDISR 7 ++ ++#define LINBRR _SFR_MEM16(0xC5) ++ ++#define LINBRRL _SFR_MEM8(0xC5) ++#define LDIV0 0 ++#define LDIV1 1 ++#define LDIV2 2 ++#define LDIV3 3 ++#define LDIV4 4 ++#define LDIV5 5 ++#define LDIV6 6 ++#define LDIV7 7 ++ ++#define LINBRRH _SFR_MEM8(0xC6) ++#define LDIV8 0 ++#define LDIV9 1 ++#define LDIV10 2 ++#define LDIV11 3 ++ ++#define LINDLR _SFR_MEM8(0xC7) ++#define LRXDL0 0 ++#define LRXDL1 1 ++#define LRXDL2 2 ++#define LRXDL3 3 ++#define LTXDL0 4 ++#define LTXDL1 5 ++#define LTXDL2 6 ++#define LTXDL3 7 ++ ++#define LINIDR _SFR_MEM8(0xC8) ++#define LID0 0 ++#define LID1 1 ++#define LID2 2 ++#define LID3 3 ++#define LID4 4 ++#define LID5 5 ++#define LP0 6 ++#define LP1 7 ++ ++#define LINSEL _SFR_MEM8(0xC9) ++#define LINDX0 0 ++#define LINDX1 1 ++#define LINDX2 2 ++#define LAINC 3 ++ ++#define LINDAT _SFR_MEM8(0xCA) ++#define LDATA0 0 ++#define LDATA1 1 ++#define LDATA2 2 ++#define LDATA3 3 ++#define LDATA4 4 ++#define LDATA5 5 ++#define LDATA6 6 ++#define LDATA7 7 ++ ++#define BGCSRA _SFR_MEM8(0xD1) ++#define BGSC0 0 ++#define BGSC1 1 ++#define BGSC2 2 ++ ++#define BGCRB _SFR_MEM8(0xD2) ++#define BGCL0 0 ++#define BGCL1 1 ++#define BGCL2 2 ++#define BGCL3 3 ++#define BGCL4 4 ++#define BGCL5 5 ++#define BGCL6 6 ++#define BGCL7 7 ++ ++#define BGCRA _SFR_MEM8(0xD3) ++#define BGCN0 0 ++#define BGCN1 1 ++#define BGCN2 2 ++#define BGCN3 3 ++#define BGCN4 4 ++#define BGCN5 5 ++#define BGCN6 6 ++#define BGCN7 7 ++ ++#define BGLR _SFR_MEM8(0xD4) ++#define BGPL 0 ++#define BGPLE 1 ++ ++#define PLLCSR _SFR_MEM8(0xD8) ++#define PLLCIE 0 ++#define PLLCIF 1 ++#define LOCK 4 ++#define SWEN 5 ++ ++#define PBOV _SFR_MEM8(0xDC) ++#define PBOE0 0 ++#define PBOE3 3 ++#define PBOVCE 7 ++ ++#define ADSCSRA _SFR_MEM8(0xE0) ++#define SCMD0 0 ++#define SCMD1 1 ++#define SBSY 2 ++ ++#define ADSCSRB _SFR_MEM8(0xE1) ++#define CADICRB 0 ++#define CADACRB 1 ++#define CADICPS 2 ++#define VADICRB 4 ++#define VADACRB 5 ++#define VADICPS 6 ++ ++#define ADCRA _SFR_MEM8(0xE2) ++#define CKSEL 0 ++#define ADCMS0 1 ++#define ADCMS1 2 ++#define ADPSEL 3 ++ ++#define ADCRB _SFR_MEM8(0xE3) ++#define ADADES0 0 ++#define ADADES1 1 ++#define ADADES2 2 ++#define ADIDES0 3 ++#define ADIDES1 4 ++ ++#define ADCRC _SFR_MEM8(0xE4) ++#define CADRCT0 0 ++#define CADRCT1 1 ++#define CADRCT2 2 ++#define CADRCT3 3 ++#define CADRCM0 4 ++#define CADRCM1 5 ++#define CADEN 7 ++ ++#define ADCRD _SFR_MEM8(0xE5) ++#define CADDSEL 0 ++#define CADPDM0 1 ++#define CADPDM1 2 ++#define CADG0 3 ++#define CADG1 4 ++#define CADG2 5 ++ ++#define ADCRE _SFR_MEM8(0xE6) ++#define VADMUX0 0 ++#define VADMUX1 1 ++#define VADMUX2 2 ++#define VADPDM0 3 ++#define VADPDM1 4 ++#define VADREFS 5 ++#define VADEN 7 ++ ++#define ADIFR _SFR_MEM8(0xE7) ++#define CADICIF 0 ++#define CADACIF 1 ++#define CADRCIF 2 ++#define VADICIF 4 ++#define VADACIF 5 ++ ++#define ADIMR _SFR_MEM8(0xE8) ++#define CADICIE 0 ++#define CADACIE 1 ++#define CADRCIE 2 ++#define VADICIE 4 ++#define VADACIE 5 ++ ++#define CADRCL _SFR_MEM16(0xE9) ++ ++#define CADRCLL _SFR_MEM8(0xE9) ++#define CADRCL0 0 ++#define CADRCL1 1 ++#define CADRCL2 2 ++#define CADRCL3 3 ++#define CADRCL4 4 ++#define CADRCL5 5 ++#define CADRCL6 6 ++#define CADRCL7 7 ++ ++#define CADRCLH _SFR_MEM8(0xEA) ++#define CADRCL8 0 ++#define CADRCL9 1 ++#define CADRCL10 2 ++#define CADRCL11 3 ++#define CADRCL12 4 ++#define CADRCL13 5 ++#define CADRCL14 6 ++#define CADRCL15 7 ++ ++#define CADIC _SFR_MEM16(0xEB) ++ ++#define CADICL _SFR_MEM8(0xEB) ++#define CADIC0 0 ++#define CADIC1 1 ++#define CADIC2 2 ++#define CADIC3 3 ++#define CADIC4 4 ++#define CADIC5 5 ++#define CADIC6 6 ++#define CADIC7 7 ++ ++#define CADICH _SFR_MEM8(0xEC) ++#define CADIC8 0 ++#define CADIC9 1 ++#define CADIC10 2 ++#define CADIC11 3 ++#define CADIC12 4 ++#define CADIC13 5 ++#define CADIC14 6 ++#define CADIC15 7 ++ ++#define CADAC0 _SFR_MEM8(0xED) ++#define CADAC00 0 ++#define CADAC01 1 ++#define CADAC02 2 ++#define CADAC03 3 ++#define CADAC04 4 ++#define CADAC05 5 ++#define CADAC06 6 ++#define CADAC07 7 ++ ++#define CADAC1 _SFR_MEM8(0xEE) ++#define CADAC08 0 ++#define CADAC09 1 ++#define CADAC10 2 ++#define CADAC11 3 ++#define CADAC12 4 ++#define CADAC13 5 ++#define CADAC14 6 ++#define CADAC15 7 ++ ++#define CADAC2 _SFR_MEM8(0xEF) ++#define CADAC16 0 ++#define CADAC17 1 ++#define CADAC18 2 ++#define CADAC19 3 ++#define CADAC20 4 ++#define CADAC21 5 ++#define CADAC22 6 ++#define CADAC23 7 ++ ++#define CADAC3 _SFR_MEM8(0xF0) ++#define CADAC24 0 ++#define CADAC25 1 ++#define CADAC26 2 ++#define CADAC27 3 ++#define CADAC28 4 ++#define CADAC29 5 ++#define CADAC30 6 ++#define CADAC31 7 ++ ++#define VADIC _SFR_MEM16(0xF1) ++ ++#define VADICL _SFR_MEM8(0xF1) ++#define VADIC0 0 ++#define VADIC1 1 ++#define VADIC2 2 ++#define VADIC3 3 ++#define VADIC4 4 ++#define VADIC5 5 ++#define VADIC6 6 ++#define VADIC7 7 ++ ++#define VADICH _SFR_MEM8(0xF2) ++#define VADIC8 0 ++#define VADIC9 1 ++#define VADIC10 2 ++#define VADIC11 3 ++#define VADIC12 4 ++#define VADIC13 5 ++#define VADIC14 6 ++#define VADIC15 7 ++ ++#define VADAC0 _SFR_MEM8(0xF3) ++#define VADAC00 0 ++#define VADAC01 1 ++#define VADAC02 2 ++#define VADAC03 3 ++#define VADAC04 4 ++#define VADAC05 5 ++#define VADAC06 6 ++#define VADAC07 7 ++ ++#define VADAC1 _SFR_MEM8(0xF4) ++#define VADAC08 0 ++#define VADAC09 1 ++#define VADAC10 2 ++#define VADAC11 3 ++#define VADAC12 4 ++#define VADAC13 5 ++#define VADAC14 6 ++#define VADAC15 7 ++ ++#define VADAC2 _SFR_MEM8(0xF5) ++#define VADAC16 0 ++#define VADAC17 1 ++#define VADAC18 2 ++#define VADAC19 3 ++#define VADAC20 4 ++#define VADAC21 5 ++#define VADAC22 6 ++#define VADAC23 7 ++ ++#define VADAC3 _SFR_MEM8(0xF6) ++#define VADAC24 0 ++#define VADAC25 1 ++#define VADAC26 2 ++#define VADAC27 3 ++#define VADAC28 4 ++#define VADAC29 5 ++#define VADAC30 6 ++#define VADAC31 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt 0 */ ++#define PCINT1_vect_num 3 ++#define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt 1 */ ++#define WDT_vect_num 4 ++#define WDT_vect _VECTOR(4) /* Watchdog Timeout Interrupt */ ++#define WAKEUP_vect_num 5 ++#define WAKEUP_vect _VECTOR(5) /* Wakeup Timer Overflow */ ++#define TIMER1_IC_vect_num 6 ++#define TIMER1_IC_vect _VECTOR(6) /* Timer 1 Input capture */ ++#define TIMER1_COMPA_vect_num 7 ++#define TIMER1_COMPA_vect _VECTOR(7) /* Timer 1 Compare Match A */ ++#define TIMER1_COMPB_vect_num 8 ++#define TIMER1_COMPB_vect _VECTOR(8) /* Timer 1 Compare Match B */ ++#define TIMER1_OVF_vect_num 9 ++#define TIMER1_OVF_vect _VECTOR(9) /* Timer 1 overflow */ ++#define TIMER0_IC_vect_num 10 ++#define TIMER0_IC_vect _VECTOR(10) /* Timer 0 Input Capture */ ++#define TIMER0_COMPA_vect_num 11 ++#define TIMER0_COMPA_vect _VECTOR(11) /* Timer 0 Comapre Match A */ ++#define TIMER0_COMPB_vect_num 12 ++#define TIMER0_COMPB_vect _VECTOR(12) /* Timer 0 Compare Match B */ ++#define TIMER0_OVF_vect_num 13 ++#define TIMER0_OVF_vect _VECTOR(13) /* Timer 0 Overflow */ ++#define LIN_STATUS_vect_num 14 ++#define LIN_STATUS_vect _VECTOR(14) /* LIN Status Interrupt */ ++#define LIN_ERROR_vect_num 15 ++#define LIN_ERROR_vect _VECTOR(15) /* LIN Error Interrupt */ ++#define SPI_STC_vect_num 16 ++#define SPI_STC_vect _VECTOR(16) /* SPI Serial transfer complete */ ++#define VADC_CONV_vect_num 17 ++#define VADC_CONV_vect _VECTOR(17) /* Voltage ADC Instantaneous Conversion Complete */ ++#define VADC_ACC_vect_num 18 ++#define VADC_ACC_vect _VECTOR(18) /* Voltage ADC Accumulated Conversion Complete */ ++#define CADC_CONV_vect_num 19 ++#define CADC_CONV_vect _VECTOR(19) /* C-ADC Instantaneous Conversion Complete */ ++#define CADC_REG_CUR_vect_num 20 ++#define CADC_REG_CUR_vect _VECTOR(20) /* C-ADC Regular Current */ ++#define CADC_ACC_vect_num 21 ++#define CADC_ACC_vect _VECTOR(21) /* C-ADC Accumulated Conversion Complete */ ++#define EE_READY_vect_num 22 ++#define EE_READY_vect _VECTOR(22) /* EEPROM Ready */ ++#define SPM_vect_num 23 ++#define SPM_vect _VECTOR(23) /* SPM Ready */ ++#define PLL_vect_num 24 ++#define PLL_vect _VECTOR(24) /* PLL Lock Change Interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (25 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (128) ++#define RAMSTART (0x100) ++#define RAMSIZE (4096) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (NA) ++#define XRAMEND (RAMEND) ++#define E2END (0x3FF) ++#define E2PAGESIZE (4) ++#define FLASHEND (0xFFFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 2 ++ ++/* Low Fuse Byte */ ++#define FUSE_OSCSEL0 (unsigned char)~_BV(0) /* Oscillator Select */ ++#define FUSE_SUT0 (unsigned char)~_BV(1) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(2) /* Select start-up time */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(3) /* Divide clock by 8 */ ++#define FUSE_BODEN (unsigned char)~_BV(4) /* Enable BOD */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_EESAVE (unsigned char)~_BV(6) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(7) /* Watchdog Timer Always On */ ++#define LFUSE_DEFAULT (FUSE_SPIEN & FUSE_CKDIV8 & FUSE_OSCSEL0) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_DWEN (unsigned char)~_BV(3) /* Enable debugWire */ ++#define HFUSE_DEFAULT (FUSE_BOOTSZ1 & FUSE_BOOTSZ0) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x10 ++ ++ ++/* Device Pin Definitions */ ++#define PV2_DDR DDRV ++#define PV2_PORT PORTV ++#define PV2_PIN PINV ++#define PV2_BIT 2 ++ ++#define PV1_DDR DDRV ++#define PV1_PORT PORTV ++#define PV1_PIN PINV ++#define PV1_BIT 1 ++ ++#define NV_DDR DDRNV ++#define NV_PORT PORTNV ++#define NV_PIN PINNV ++#define NV_BIT NV ++ ++#define VFET_DDR DDRVFET ++#define VFET_PORT PORTVFET ++#define VFET_PIN PINVFET ++#define VFET_BIT VFET ++ ++#define CF1P_DDR DDRCF1P ++#define CF1P_PORT PORTCF1P ++#define CF1P_PIN PINCF1P ++#define CF1P_BIT CF1P ++ ++#define CF1N_DDR DDRCF1N ++#define CF1N_PORT PORTCF1N ++#define CF1N_PIN PINCF1N ++#define CF1N_BIT CF1N ++ ++#define CF2P_DDR DDRCF2P ++#define CF2P_PORT PORTCF2P ++#define CF2P_PIN PINCF2P ++#define CF2P_BIT CF2P ++ ++#define CF2N_DDR DDRCF2N ++#define CF2N_PORT PORTCF2N ++#define CF2N_PIN PINCF2N ++#define CF2N_BIT CF2N ++ ++#define VREG_DDR DDRVREG ++#define VREG_PORT PORTVREG ++#define VREG_PIN PINVREG ++#define VREG_BIT VREG ++ ++#define VREF_DDR DDRVREF ++#define VREF_PORT PORTVREF ++#define VREF_PIN PINVREF ++#define VREF_BIT VREF ++ ++#define VREFGND_DDR DDRVREFGND ++#define VREFGND_PORT PORTVREFGND ++#define VREFGND_PIN PINVREFGND ++#define VREFGND_BIT VREFGND ++ ++#define PI_DDR DDRI ++#define PI_PORT PORTI ++#define PI_PIN PINI ++#define PI_BIT ++ ++#define NI_DDR DDRNI ++#define NI_PORT PORTNI ++#define NI_PIN PINNI ++#define NI_BIT NI ++ ++#define PA0_DDR DDRA ++#define PA0_PORT PORTA ++#define PA0_PIN PINA ++#define PA0_BIT 0 ++ ++#define PA1_DDR DDRA ++#define PA1_PORT PORTA ++#define PA1_PIN PINA ++#define PA1_BIT 1 ++ ++#define PA2_DDR DDRA ++#define PA2_PORT PORTA ++#define PA2_PIN PINA ++#define PA2_BIT 2 ++ ++#define PB0_DDR DDRB ++#define PB0_PORT PORTB ++#define PB0_PIN PINB ++#define PB0_BIT 0 ++ ++#define PB1_DDR DDRB ++#define PB1_PORT PORTB ++#define PB1_PIN PINB ++#define PB1_BIT 1 ++ ++#define PB2_DDR DDRB ++#define PB2_PORT PORTB ++#define PB2_PIN PINB ++#define PB2_BIT 2 ++ ++#define PB3_DDR DDRB ++#define PB3_PORT PORTB ++#define PB3_PIN PINB ++#define PB3_BIT 3 ++ ++#define PC0_DDR DDRC ++#define PC0_PORT PORTC ++#define PC0_PIN PINC ++#define PC0_BIT 0 ++ ++#define BATT_DDR DDRBATT ++#define BATT_PORT PORTBATT ++#define BATT_PIN PINBATT ++#define BATT_BIT BATT ++ ++#define OC_DDR DDROC ++#define OC_PORT PORTOC ++#define OC_PIN PINOC ++#define OC_BIT OC ++ ++#endif /* _AVR_ATmega64HVE_H_ */ ++ diff --git a/include/avr/iom64hve2.h b/include/avr/iom64hve2.h new file mode 100644 -index 0000000..01f43c4 +index 0000000..0a0e7f0 --- /dev/null +++ b/include/avr/iom64hve2.h @@ -0,0 +1,727 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATMEGA64HVE2_H_INCLUDED -+#define _AVR_ATMEGA64HVE2_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iom64hve2.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINA _SFR_IO8(0x00) -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x01) -+#define DDRA1 1 -+#define DDRA0 0 -+ -+#define PORTA _SFR_IO8(0x02) -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+/* Reserved [0x06..0x14] */ -+ -+#define TIFR0 _SFR_IO8(0x15) -+#define TOV0 0 -+#define OCF0A 1 -+#define OCF0B 2 -+#define ICF0 3 -+ -+#define TIFR1 _SFR_IO8(0x16) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define ICF1 3 -+ -+/* Reserved [0x17..0x1A] */ -+ -+#define PCIFR _SFR_IO8(0x1B) -+#define PCIF0 0 -+#define PCIF1 1 -+ -+#define EIFR _SFR_IO8(0x1C) -+#define INTF0 0 -+ -+#define EIMSK _SFR_IO8(0x1D) -+#define INT0 0 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEPE 1 -+#define EEMPE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSRSYNC 0 -+#define TSM 7 -+ -+#define TCCR0A _SFR_IO8(0x24) -+#define WGM00 0 -+#define ICS0 3 -+#define ICES0 4 -+#define ICNC0 5 -+#define ICEN0 6 -+#define TCW0 7 -+ -+#define TCCR0B _SFR_IO8(0x25) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+ -+/* Combine TCNT0L and TCNT0H */ -+#define TCNT0 _SFR_IO16(0x26) -+ -+#define TCNT0L _SFR_IO8(0x26) -+#define TCNT0H _SFR_IO8(0x27) -+ -+#define OCR0A _SFR_IO8(0x28) -+ -+#define OCR0B _SFR_IO8(0x29) -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+/* Reserved [0x2F..0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define PORF 0 -+#define EXTRF 1 -+#define BODRF 2 -+#define WDRF 3 -+#define OCDRF 4 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define IVCE 0 -+#define IVSEL 1 -+#define PUD 4 -+#define CKOE 5 -+ -+/* Reserved [0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define LBSET 3 -+#define RWWSRE 4 -+#define SIGRD 5 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+/* Reserved [0x38..0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCSR _SFR_MEM8(0x60) -+#define WDE 3 -+#define WDCE 4 -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDP3 5 -+#define WDIE 6 -+#define WDIF 7 -+ -+#define CLKPR _SFR_MEM8(0x61) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPCE 7 -+ -+#define WUTCSR _SFR_MEM8(0x62) -+#define WUTP0 0 -+#define WUTP1 1 -+#define WUTP2 2 -+#define WUTE 3 -+#define WUTR 4 -+#define WUTIE 6 -+#define WUTIF 7 -+ -+#define WDTCLR _SFR_MEM8(0x63) -+#define WDCLE 0 -+#define WDCL0 1 -+#define WDCL1 2 -+ -+#define PRR0 _SFR_MEM8(0x64) -+#define PRTIM0 0 -+#define PRTIM1 1 -+#define PRSPI 2 -+#define PRLIN 3 -+ -+/* Reserved [0x65] */ -+ -+#define SOSCCALA _SFR_MEM8(0x66) -+ -+#define SOSCCALB _SFR_MEM8(0x67) -+ -+#define PCICR _SFR_MEM8(0x68) -+#define PCIE0 0 -+#define PCIE1 1 -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+ -+/* Reserved [0x6A] */ -+ -+#define PCMSK0 _SFR_MEM8(0x6B) -+ -+#define PCMSK1 _SFR_MEM8(0x6C) -+ -+/* Reserved [0x6D] */ -+ -+#define TIMSK0 _SFR_MEM8(0x6E) -+#define TOIE0 0 -+#define OCIE0A 1 -+#define OCIE0B 2 -+#define ICIE0 3 -+ -+#define TIMSK1 _SFR_MEM8(0x6F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define ICIE1 3 -+ -+/* Reserved [0x70..0x7D] */ -+ -+#define DIDR0 _SFR_MEM8(0x7E) -+#define PA0DID 0 -+#define PA1DID 1 -+ -+/* Reserved [0x7F] */ -+ -+#define TCCR1A _SFR_MEM8(0x80) -+#define WGM10 0 -+#define ICS1 3 -+#define ICES1 4 -+#define ICNC1 5 -+#define ICEN1 6 -+#define TCW1 7 -+ -+#define TCCR1B _SFR_MEM8(0x81) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+ -+/* Reserved [0x82..0x83] */ -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x84) -+ -+#define TCNT1L _SFR_MEM8(0x84) -+#define TCNT1H _SFR_MEM8(0x85) -+ -+/* Reserved [0x86..0x87] */ -+ -+#define OCR1A _SFR_MEM8(0x88) -+ -+#define OCR1B _SFR_MEM8(0x89) -+ -+/* Reserved [0x8A..0xBF] */ -+ -+#define LINCR _SFR_MEM8(0xC0) -+#define LCMD0 0 -+#define LCMD1 1 -+#define LCMD2 2 -+#define LENA 3 -+#define LCONF0 4 -+#define LCONF1 5 -+#define LIN13 6 -+#define LSWRES 7 -+ -+#define LINSIR _SFR_MEM8(0xC1) -+#define LRXOK 0 -+#define LTXOK 1 -+#define LIDOK 2 -+#define LERR 3 -+#define LBUSY 4 -+#define LIDST0 5 -+#define LIDST1 6 -+#define LIDST2 7 -+ -+#define LINENIR _SFR_MEM8(0xC2) -+#define LENRXOK 0 -+#define LENTXOK 1 -+#define LENIDOK 2 -+#define LENERR 3 -+ -+#define LINERR _SFR_MEM8(0xC3) -+#define LBERR 0 -+#define LCERR 1 -+#define LPERR 2 -+#define LSERR 3 -+#define LFERR 4 -+#define LOVERR 5 -+#define LTOERR 6 -+#define LABORT 7 -+ -+#define LINBTR _SFR_MEM8(0xC4) -+#define LBT0 0 -+#define LBT1 1 -+#define LBT2 2 -+#define LBT3 3 -+#define LBT4 4 -+#define LBT5 5 -+#define LDISR 7 -+ -+#define LINBRRL _SFR_MEM8(0xC5) -+#define LDIV0 0 -+#define LDIV1 1 -+#define LDIV2 2 -+#define LDIV3 3 -+#define LDIV4 4 -+#define LDIV5 5 -+#define LDIV6 6 -+#define LDIV7 7 -+ -+#define LINBRRH _SFR_MEM8(0xC6) -+#define LDIV8 0 -+#define LDIV9 1 -+#define LDIV10 2 -+#define LDIV11 3 -+ -+#define LINDLR _SFR_MEM8(0xC7) -+#define LRXDL0 0 -+#define LRXDL1 1 -+#define LRXDL2 2 -+#define LRXDL3 3 -+#define LTXDL0 4 -+#define LTXDL1 5 -+#define LTXDL2 6 -+#define LTXDL3 7 -+ -+#define LINIDR _SFR_MEM8(0xC8) -+#define LID0 0 -+#define LID1 1 -+#define LID2 2 -+#define LID3 3 -+#define LID4 4 -+#define LID5 5 -+#define LP0 6 -+#define LP1 7 -+ -+#define LINSEL _SFR_MEM8(0xC9) -+#define LINDX0 0 -+#define LINDX1 1 -+#define LINDX2 2 -+#define LAINC 3 -+ -+#define LINDAT _SFR_MEM8(0xCA) -+#define LDATA0 0 -+#define LDATA1 1 -+#define LDATA2 2 -+#define LDATA3 3 -+#define LDATA4 4 -+#define LDATA5 5 -+#define LDATA6 6 -+#define LDATA7 7 -+ -+/* Reserved [0xCB..0xD0] */ -+ -+#define BGCSRA _SFR_MEM8(0xD1) -+#define BGSC0 0 -+#define BGSC1 1 -+#define BGSC2 2 -+ -+#define BGCRB _SFR_MEM8(0xD2) -+#define BGCL0 0 -+#define BGCL1 1 -+#define BGCL2 2 -+#define BGCL3 3 -+#define BGCL4 4 -+#define BGCL5 5 -+#define BGCL6 6 -+#define BGCL7 7 -+ -+#define BGCRA _SFR_MEM8(0xD3) -+#define BGCN0 0 -+#define BGCN1 1 -+#define BGCN2 2 -+#define BGCN3 3 -+#define BGCN4 4 -+#define BGCN5 5 -+#define BGCN6 6 -+#define BGCN7 7 -+ -+#define BGLR _SFR_MEM8(0xD4) -+#define BGPL 0 -+#define BGPLE 1 -+ -+/* Reserved [0xD5..0xD7] */ -+ -+#define PLLCSR _SFR_MEM8(0xD8) -+#define PLLCIE 0 -+#define PLLCIF 1 -+#define LOCK 4 -+#define SWEN 5 -+ -+/* Reserved [0xD9..0xDB] */ -+ -+#define PBOV _SFR_MEM8(0xDC) -+#define PBOE0 0 -+#define PBOE3 3 -+#define PBOVCE 7 -+ -+/* Reserved [0xDD..0xDF] */ -+ -+#define ADSCSRA _SFR_MEM8(0xE0) -+#define SCMD0 0 -+#define SCMD1 1 -+#define SBSY 2 -+ -+#define ADSCSRB _SFR_MEM8(0xE1) -+#define CADICRB 0 -+#define CADACRB 1 -+#define CADICPS 2 -+#define VADICRB 4 -+#define VADACRB 5 -+#define VADICPS 6 -+ -+#define ADCRA _SFR_MEM8(0xE2) -+#define CKSEL 0 -+#define ADCMS0 1 -+#define ADCMS1 2 -+#define ADPSEL 3 -+ -+#define ADCRB _SFR_MEM8(0xE3) -+#define ADADES0 0 -+#define ADADES1 1 -+#define ADADES2 2 -+#define ADIDES0 3 -+#define ADIDES1 4 -+ -+#define ADCRC _SFR_MEM8(0xE4) -+#define CADRCT0 0 -+#define CADRCT1 1 -+#define CADRCT2 2 -+#define CADRCT3 3 -+#define CADRCM0 4 -+#define CADRCM1 5 -+#define CADEN 7 -+ -+#define ADCRD _SFR_MEM8(0xE5) -+#define CADDSEL 0 -+#define CADPDM0 1 -+#define CADPDM1 2 -+#define CADG0 3 -+#define CADG1 4 -+#define CADG2 5 -+ -+#define ADCRE _SFR_MEM8(0xE6) -+#define VADMUX0 0 -+#define VADMUX1 1 -+#define VADMUX2 2 -+#define VADPDM0 3 -+#define VADPDM1 4 -+#define VADREFS 5 -+#define VADEN 7 -+ -+#define ADIFR _SFR_MEM8(0xE7) -+#define CADICIF 0 -+#define CADACIF 1 -+#define CADRCIF 2 -+#define VADICIF 4 -+#define VADACIF 5 -+ -+#define ADIMR _SFR_MEM8(0xE8) -+#define CADICIE 0 -+#define CADACIE 1 -+#define CADRCIE 2 -+#define VADICIE 4 -+#define VADACIE 5 -+ -+/* Combine CADRCLL and CADRCLH */ -+#define CADRCL _SFR_MEM16(0xE9) -+ -+#define CADRCLL _SFR_MEM8(0xE9) -+#define CADRCLH _SFR_MEM8(0xEA) -+ -+/* Combine CADICL and CADICH */ -+#define CADIC _SFR_MEM16(0xEB) -+ -+#define CADICL _SFR_MEM8(0xEB) -+#define CADICH _SFR_MEM8(0xEC) -+ -+#define CADAC0 _SFR_MEM8(0xED) -+ -+#define CADAC1 _SFR_MEM8(0xEE) -+ -+#define CADAC2 _SFR_MEM8(0xEF) -+ -+#define CADAC3 _SFR_MEM8(0xF0) -+ -+/* Combine VADICL and VADICH */ -+#define VADIC _SFR_MEM16(0xF1) -+ -+#define VADICL _SFR_MEM8(0xF1) -+#define VADICH _SFR_MEM8(0xF2) -+ -+#define VADAC0 _SFR_MEM8(0xF3) -+ -+#define VADAC1 _SFR_MEM8(0xF4) -+ -+#define VADAC2 _SFR_MEM8(0xF5) -+ -+#define VADAC3 _SFR_MEM8(0xF6) -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* Pin Change Interrupt 0 */ -+#define PCINT0_vect _VECTOR(2) -+#define PCINT0_vect_num 2 -+ -+/* Pin Change Interrupt 1 */ -+#define PCINT1_vect _VECTOR(3) -+#define PCINT1_vect_num 3 -+ -+/* Watchdog Timeout Interrupt */ -+#define WDT_vect _VECTOR(4) -+#define WDT_vect_num 4 -+ -+/* Wakeup Timer Overflow */ -+#define WAKEUP_vect _VECTOR(5) -+#define WAKEUP_vect_num 5 -+ -+/* Timer 1 Input capture */ -+#define TIMER1_IC_vect _VECTOR(6) -+#define TIMER1_IC_vect_num 6 -+ -+/* Timer 1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(7) -+#define TIMER1_COMPA_vect_num 7 -+ -+/* Timer 1 Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(8) -+#define TIMER1_COMPB_vect_num 8 -+ -+/* Timer 1 overflow */ -+#define TIMER1_OVF_vect _VECTOR(9) -+#define TIMER1_OVF_vect_num 9 -+ -+/* Timer 0 Input Capture */ -+#define TIMER0_IC_vect _VECTOR(10) -+#define TIMER0_IC_vect_num 10 -+ -+/* Timer 0 Comapre Match A */ -+#define TIMER0_COMPA_vect _VECTOR(11) -+#define TIMER0_COMPA_vect_num 11 -+ -+/* Timer 0 Compare Match B */ -+#define TIMER0_COMPB_vect _VECTOR(12) -+#define TIMER0_COMPB_vect_num 12 -+ -+/* Timer 0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(13) -+#define TIMER0_OVF_vect_num 13 -+ -+/* LIN Status Interrupt */ -+#define LIN_STATUS_vect _VECTOR(14) -+#define LIN_STATUS_vect_num 14 -+ -+/* LIN Error Interrupt */ -+#define LIN_ERROR_vect _VECTOR(15) -+#define LIN_ERROR_vect_num 15 -+ -+/* SPI Serial transfer complete */ -+#define SPI_STC_vect _VECTOR(16) -+#define SPI_STC_vect_num 16 -+ -+/* Voltage ADC Instantaneous Conversion Complete */ -+#define VADC_CONV_vect _VECTOR(17) -+#define VADC_CONV_vect_num 17 -+ -+/* Voltage ADC Accumulated Conversion Complete */ -+#define VADC_ACC_vect _VECTOR(18) -+#define VADC_ACC_vect_num 18 -+ -+/* C-ADC Instantaneous Conversion Complete */ -+#define CADC_CONV_vect _VECTOR(19) -+#define CADC_CONV_vect_num 19 -+ -+/* C-ADC Regular Current */ -+#define CADC_REG_CUR_vect _VECTOR(20) -+#define CADC_REG_CUR_vect_num 20 -+ -+/* C-ADC Accumulated Conversion Complete */ -+#define CADC_ACC_vect _VECTOR(21) -+#define CADC_ACC_vect_num 21 -+ -+/* EEPROM Ready */ -+#define EE_READY_vect _VECTOR(22) -+#define EE_READY_vect_num 22 -+ -+/* SPM Ready */ -+#define SPM_vect _VECTOR(23) -+#define SPM_vect_num 23 -+ -+/* PLL Lock Change Interrupt */ -+#define PLL_vect _VECTOR(24) -+#define PLL_vect_num 24 -+ -+#define _VECTORS_SIZE 100 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 128 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0xFFFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 4096 -+#define RAMEND 0x10FF -+#define E2START 0 -+#define E2SIZE 1024 -+#define E2PAGESIZE 4 -+#define E2END 0x03FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 2 -+ -+/* Low Fuse Byte */ -+#define FUSE_OSCSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT0 (unsigned char)~_BV(1) -+#define FUSE_SUT1 (unsigned char)~_BV(2) -+#define FUSE_CKDIV8 (unsigned char)~_BV(3) -+#define FUSE_BODEN (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_EESAVE (unsigned char)~_BV(6) -+#define FUSE_WDTON (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+#define FUSE_DWEN (unsigned char)~_BV(3) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x96 -+#define SIGNATURE_2 0x10 -+ -+ -+#endif /* #ifdef _AVR_ATMEGA64HVE2_H_INCLUDED */ -+ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATMEGA64HVE2_H_INCLUDED ++#define _AVR_ATMEGA64HVE2_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom64hve2.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDRA1 1 ++#define DDRA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++/* Reserved [0x06..0x14] */ ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++#define ICF0 3 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 3 ++ ++/* Reserved [0x17..0x1A] */ ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define ICS0 3 ++#define ICES0 4 ++#define ICNC0 5 ++#define ICEN0 6 ++#define TCW0 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++ ++/* Combine TCNT0L and TCNT0H */ ++#define TCNT0 _SFR_IO16(0x26) ++ ++#define TCNT0L _SFR_IO8(0x26) ++#define TCNT0H _SFR_IO8(0x27) ++ ++#define OCR0A _SFR_IO8(0x28) ++ ++#define OCR0B _SFR_IO8(0x29) ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F..0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BODRF 2 ++#define WDRF 3 ++#define OCDRF 4 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define CKOE 5 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define LBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDE 3 ++#define WDCE 4 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPCE 7 ++ ++#define WUTCSR _SFR_MEM8(0x62) ++#define WUTP0 0 ++#define WUTP1 1 ++#define WUTP2 2 ++#define WUTE 3 ++#define WUTR 4 ++#define WUTIE 6 ++#define WUTIF 7 ++ ++#define WDTCLR _SFR_MEM8(0x63) ++#define WDCLE 0 ++#define WDCL0 1 ++#define WDCL1 2 ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRTIM0 0 ++#define PRTIM1 1 ++#define PRSPI 2 ++#define PRLIN 3 ++ ++/* Reserved [0x65] */ ++ ++#define SOSCCALA _SFR_MEM8(0x66) ++ ++#define SOSCCALB _SFR_MEM8(0x67) ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++ ++/* Reserved [0x6D] */ ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++#define ICIE0 3 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 3 ++ ++/* Reserved [0x70..0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define PA0DID 0 ++#define PA1DID 1 ++ ++/* Reserved [0x7F] */ ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define ICS1 3 ++#define ICES1 4 ++#define ICNC1 5 ++#define ICEN1 6 ++#define TCW1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++ ++/* Reserved [0x82..0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Reserved [0x86..0x87] */ ++ ++#define OCR1A _SFR_MEM8(0x88) ++ ++#define OCR1B _SFR_MEM8(0x89) ++ ++/* Reserved [0x8A..0xBF] */ ++ ++#define LINCR _SFR_MEM8(0xC0) ++#define LCMD0 0 ++#define LCMD1 1 ++#define LCMD2 2 ++#define LENA 3 ++#define LCONF0 4 ++#define LCONF1 5 ++#define LIN13 6 ++#define LSWRES 7 ++ ++#define LINSIR _SFR_MEM8(0xC1) ++#define LRXOK 0 ++#define LTXOK 1 ++#define LIDOK 2 ++#define LERR 3 ++#define LBUSY 4 ++#define LIDST0 5 ++#define LIDST1 6 ++#define LIDST2 7 ++ ++#define LINENIR _SFR_MEM8(0xC2) ++#define LENRXOK 0 ++#define LENTXOK 1 ++#define LENIDOK 2 ++#define LENERR 3 ++ ++#define LINERR _SFR_MEM8(0xC3) ++#define LBERR 0 ++#define LCERR 1 ++#define LPERR 2 ++#define LSERR 3 ++#define LFERR 4 ++#define LOVERR 5 ++#define LTOERR 6 ++#define LABORT 7 ++ ++#define LINBTR _SFR_MEM8(0xC4) ++#define LBT0 0 ++#define LBT1 1 ++#define LBT2 2 ++#define LBT3 3 ++#define LBT4 4 ++#define LBT5 5 ++#define LDISR 7 ++ ++#define LINBRRL _SFR_MEM8(0xC5) ++#define LDIV0 0 ++#define LDIV1 1 ++#define LDIV2 2 ++#define LDIV3 3 ++#define LDIV4 4 ++#define LDIV5 5 ++#define LDIV6 6 ++#define LDIV7 7 ++ ++#define LINBRRH _SFR_MEM8(0xC6) ++#define LDIV8 0 ++#define LDIV9 1 ++#define LDIV10 2 ++#define LDIV11 3 ++ ++#define LINDLR _SFR_MEM8(0xC7) ++#define LRXDL0 0 ++#define LRXDL1 1 ++#define LRXDL2 2 ++#define LRXDL3 3 ++#define LTXDL0 4 ++#define LTXDL1 5 ++#define LTXDL2 6 ++#define LTXDL3 7 ++ ++#define LINIDR _SFR_MEM8(0xC8) ++#define LID0 0 ++#define LID1 1 ++#define LID2 2 ++#define LID3 3 ++#define LID4 4 ++#define LID5 5 ++#define LP0 6 ++#define LP1 7 ++ ++#define LINSEL _SFR_MEM8(0xC9) ++#define LINDX0 0 ++#define LINDX1 1 ++#define LINDX2 2 ++#define LAINC 3 ++ ++#define LINDAT _SFR_MEM8(0xCA) ++#define LDATA0 0 ++#define LDATA1 1 ++#define LDATA2 2 ++#define LDATA3 3 ++#define LDATA4 4 ++#define LDATA5 5 ++#define LDATA6 6 ++#define LDATA7 7 ++ ++/* Reserved [0xCB..0xD0] */ ++ ++#define BGCSRA _SFR_MEM8(0xD1) ++#define BGSC0 0 ++#define BGSC1 1 ++#define BGSC2 2 ++ ++#define BGCRB _SFR_MEM8(0xD2) ++#define BGCL0 0 ++#define BGCL1 1 ++#define BGCL2 2 ++#define BGCL3 3 ++#define BGCL4 4 ++#define BGCL5 5 ++#define BGCL6 6 ++#define BGCL7 7 ++ ++#define BGCRA _SFR_MEM8(0xD3) ++#define BGCN0 0 ++#define BGCN1 1 ++#define BGCN2 2 ++#define BGCN3 3 ++#define BGCN4 4 ++#define BGCN5 5 ++#define BGCN6 6 ++#define BGCN7 7 ++ ++#define BGLR _SFR_MEM8(0xD4) ++#define BGPL 0 ++#define BGPLE 1 ++ ++/* Reserved [0xD5..0xD7] */ ++ ++#define PLLCSR _SFR_MEM8(0xD8) ++#define PLLCIE 0 ++#define PLLCIF 1 ++#define LOCK 4 ++#define SWEN 5 ++ ++/* Reserved [0xD9..0xDB] */ ++ ++#define PBOV _SFR_MEM8(0xDC) ++#define PBOE0 0 ++#define PBOE3 3 ++#define PBOVCE 7 ++ ++/* Reserved [0xDD..0xDF] */ ++ ++#define ADSCSRA _SFR_MEM8(0xE0) ++#define SCMD0 0 ++#define SCMD1 1 ++#define SBSY 2 ++ ++#define ADSCSRB _SFR_MEM8(0xE1) ++#define CADICRB 0 ++#define CADACRB 1 ++#define CADICPS 2 ++#define VADICRB 4 ++#define VADACRB 5 ++#define VADICPS 6 ++ ++#define ADCRA _SFR_MEM8(0xE2) ++#define CKSEL 0 ++#define ADCMS0 1 ++#define ADCMS1 2 ++#define ADPSEL 3 ++ ++#define ADCRB _SFR_MEM8(0xE3) ++#define ADADES0 0 ++#define ADADES1 1 ++#define ADADES2 2 ++#define ADIDES0 3 ++#define ADIDES1 4 ++ ++#define ADCRC _SFR_MEM8(0xE4) ++#define CADRCT0 0 ++#define CADRCT1 1 ++#define CADRCT2 2 ++#define CADRCT3 3 ++#define CADRCM0 4 ++#define CADRCM1 5 ++#define CADEN 7 ++ ++#define ADCRD _SFR_MEM8(0xE5) ++#define CADDSEL 0 ++#define CADPDM0 1 ++#define CADPDM1 2 ++#define CADG0 3 ++#define CADG1 4 ++#define CADG2 5 ++ ++#define ADCRE _SFR_MEM8(0xE6) ++#define VADMUX0 0 ++#define VADMUX1 1 ++#define VADMUX2 2 ++#define VADPDM0 3 ++#define VADPDM1 4 ++#define VADREFS 5 ++#define VADEN 7 ++ ++#define ADIFR _SFR_MEM8(0xE7) ++#define CADICIF 0 ++#define CADACIF 1 ++#define CADRCIF 2 ++#define VADICIF 4 ++#define VADACIF 5 ++ ++#define ADIMR _SFR_MEM8(0xE8) ++#define CADICIE 0 ++#define CADACIE 1 ++#define CADRCIE 2 ++#define VADICIE 4 ++#define VADACIE 5 ++ ++/* Combine CADRCLL and CADRCLH */ ++#define CADRCL _SFR_MEM16(0xE9) ++ ++#define CADRCLL _SFR_MEM8(0xE9) ++#define CADRCLH _SFR_MEM8(0xEA) ++ ++/* Combine CADICL and CADICH */ ++#define CADIC _SFR_MEM16(0xEB) ++ ++#define CADICL _SFR_MEM8(0xEB) ++#define CADICH _SFR_MEM8(0xEC) ++ ++#define CADAC0 _SFR_MEM8(0xED) ++ ++#define CADAC1 _SFR_MEM8(0xEE) ++ ++#define CADAC2 _SFR_MEM8(0xEF) ++ ++#define CADAC3 _SFR_MEM8(0xF0) ++ ++/* Combine VADICL and VADICH */ ++#define VADIC _SFR_MEM16(0xF1) ++ ++#define VADICL _SFR_MEM8(0xF1) ++#define VADICH _SFR_MEM8(0xF2) ++ ++#define VADAC0 _SFR_MEM8(0xF3) ++ ++#define VADAC1 _SFR_MEM8(0xF4) ++ ++#define VADAC2 _SFR_MEM8(0xF5) ++ ++#define VADAC3 _SFR_MEM8(0xF6) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* Pin Change Interrupt 0 */ ++#define PCINT0_vect _VECTOR(2) ++#define PCINT0_vect_num 2 ++ ++/* Pin Change Interrupt 1 */ ++#define PCINT1_vect _VECTOR(3) ++#define PCINT1_vect_num 3 ++ ++/* Watchdog Timeout Interrupt */ ++#define WDT_vect _VECTOR(4) ++#define WDT_vect_num 4 ++ ++/* Wakeup Timer Overflow */ ++#define WAKEUP_vect _VECTOR(5) ++#define WAKEUP_vect_num 5 ++ ++/* Timer 1 Input capture */ ++#define TIMER1_IC_vect _VECTOR(6) ++#define TIMER1_IC_vect_num 6 ++ ++/* Timer 1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define TIMER1_COMPA_vect_num 7 ++ ++/* Timer 1 Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define TIMER1_COMPB_vect_num 8 ++ ++/* Timer 1 overflow */ ++#define TIMER1_OVF_vect _VECTOR(9) ++#define TIMER1_OVF_vect_num 9 ++ ++/* Timer 0 Input Capture */ ++#define TIMER0_IC_vect _VECTOR(10) ++#define TIMER0_IC_vect_num 10 ++ ++/* Timer 0 Comapre Match A */ ++#define TIMER0_COMPA_vect _VECTOR(11) ++#define TIMER0_COMPA_vect_num 11 ++ ++/* Timer 0 Compare Match B */ ++#define TIMER0_COMPB_vect _VECTOR(12) ++#define TIMER0_COMPB_vect_num 12 ++ ++/* Timer 0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(13) ++#define TIMER0_OVF_vect_num 13 ++ ++/* LIN Status Interrupt */ ++#define LIN_STATUS_vect _VECTOR(14) ++#define LIN_STATUS_vect_num 14 ++ ++/* LIN Error Interrupt */ ++#define LIN_ERROR_vect _VECTOR(15) ++#define LIN_ERROR_vect_num 15 ++ ++/* SPI Serial transfer complete */ ++#define SPI_STC_vect _VECTOR(16) ++#define SPI_STC_vect_num 16 ++ ++/* Voltage ADC Instantaneous Conversion Complete */ ++#define VADC_CONV_vect _VECTOR(17) ++#define VADC_CONV_vect_num 17 ++ ++/* Voltage ADC Accumulated Conversion Complete */ ++#define VADC_ACC_vect _VECTOR(18) ++#define VADC_ACC_vect_num 18 ++ ++/* C-ADC Instantaneous Conversion Complete */ ++#define CADC_CONV_vect _VECTOR(19) ++#define CADC_CONV_vect_num 19 ++ ++/* C-ADC Regular Current */ ++#define CADC_REG_CUR_vect _VECTOR(20) ++#define CADC_REG_CUR_vect_num 20 ++ ++/* C-ADC Accumulated Conversion Complete */ ++#define CADC_ACC_vect _VECTOR(21) ++#define CADC_ACC_vect_num 21 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(22) ++#define EE_READY_vect_num 22 ++ ++/* SPM Ready */ ++#define SPM_vect _VECTOR(23) ++#define SPM_vect_num 23 ++ ++/* PLL Lock Change Interrupt */ ++#define PLL_vect _VECTOR(24) ++#define PLL_vect_num 24 ++ ++#define _VECTORS_SIZE 100 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 128 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0xFFFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 4096 ++#define RAMEND 0x10FF ++#define E2START 0 ++#define E2SIZE 1024 ++#define E2PAGESIZE 4 ++#define E2END 0x03FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 2 ++ ++/* Low Fuse Byte */ ++#define FUSE_OSCSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT0 (unsigned char)~_BV(1) ++#define FUSE_SUT1 (unsigned char)~_BV(2) ++#define FUSE_CKDIV8 (unsigned char)~_BV(3) ++#define FUSE_BODEN (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_EESAVE (unsigned char)~_BV(6) ++#define FUSE_WDTON (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_DWEN (unsigned char)~_BV(3) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x10 ++ ++ ++#endif /* #ifdef _AVR_ATMEGA64HVE2_H_INCLUDED */ ++ +diff --git a/include/avr/iom64m1.h b/include/avr/iom64m1.h +index 4164532..44e31a9 100644 +--- a/include/avr/iom64m1.h ++++ b/include/avr/iom64m1.h +@@ -1,1558 +1,1558 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom64m1.h 2183 2010-09-21 05:37:46Z aboyapati $ */ +- +-/* avr/iom64m1.h - definitions for ATmega64M1 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom64m1.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATmega64M1_H_ +-#define _AVR_ATmega64M1_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +-#define PINC7 7 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC3 3 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +-#define DDC7 7 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC3 3 +-#define PORTC4 4 +-#define PORTC5 5 +-#define PORTC6 6 +-#define PORTC7 7 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define PINE _SFR_IO8(0x0C) +-#define PINE0 0 +-#define PINE1 1 +-#define PINE2 2 +- +-#define DDRE _SFR_IO8(0x0D) +-#define DDE0 0 +-#define DDE1 1 +-#define DDE2 2 +- +-#define PORTE _SFR_IO8(0x0E) +-#define PORTE0 0 +-#define PORTE1 1 +-#define PORTE2 2 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define GPIOR1 _SFR_IO8(0x19) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x1A) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +-#define PCIF1 1 +-#define PCIF2 2 +-#define PCIF3 3 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +-#define INTF2 2 +-#define INTF3 3 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +-#define INT2 2 +-#define INT3 3 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEWE 1 +-#define EEMWE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +-#define EEAR9 1 +-#define EEAR10 2 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSR10 0 +-#define PSRSYNC 0 +-#define ICPSEL1 6 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define OCR0A _SFR_IO8(0x27) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define OCR0B _SFR_IO8(0x28) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define PLLCSR _SFR_IO8(0x29) +-#define PLOCK 0 +-#define PLLE 1 +-#define PLLF 2 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define ACSR _SFR_IO8(0x30) +-#define AC0O 0 +-#define AC1O 1 +-#define AC2O 2 +-#define AC3O 3 +-#define AC0IF 4 +-#define AC1IF 5 +-#define AC2IF 6 +-#define AC3IF 7 +- +-#define DWDR _SFR_IO8(0x31) +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define SPIPS 7 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define SIGRD 5 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRLIN 1 +-#define PRSPI 2 +-#define PRTIM0 3 +-#define PRTIM1 4 +-#define PRPSC 5 +-#define PRCAN 6 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +-#define PCIE1 1 +-#define PCIE2 2 +-#define PCIE3 3 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define ISC20 4 +-#define ISC21 5 +-#define ISC30 6 +-#define ISC31 7 +- +-#define PCMSK0 _SFR_MEM8(0x6A) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6B) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-#define PCMSK2 _SFR_MEM8(0x6C) +-#define PCINT16 0 +-#define PCINT17 1 +-#define PCINT18 2 +-#define PCINT19 3 +-#define PCINT20 4 +-#define PCINT21 5 +-#define PCINT22 6 +-#define PCINT23 7 +- +-#define PCMSK3 _SFR_MEM8(0x6D) +-#define PCINT24 0 +-#define PCINT25 1 +-#define PCINT26 2 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define AMP0CSR _SFR_MEM8(0x75) +-#define AMP0TS0 0 +-#define AMP0TS1 1 +-#define AMP0TS2 2 +-#define AMPCMP0 3 +-#define AMP0G0 4 +-#define AMP0G1 5 +-#define AMP0IS 6 +-#define AMP0EN 7 +- +-#define AMP1CSR _SFR_MEM8(0x76) +-#define AMP1TS0 0 +-#define AMP1TS1 1 +-#define AMP1TS2 2 +-#define AMPCMP1 3 +-#define AMP1G0 4 +-#define AMP1G1 5 +-#define AMP1IS 6 +-#define AMP1EN 7 +- +-#define AMP2CSR _SFR_MEM8(0x77) +-#define AMP2TS0 0 +-#define AMP2TS1 1 +-#define AMP2TS2 2 +-#define AMPCMP2 3 +-#define AMP2G0 4 +-#define AMP2G1 5 +-#define AMP2IS 6 +-#define AMP2EN 7 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +- +-#define ADCL _SFR_MEM8(0x78) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_MEM8(0x79) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ADTS3 3 +-#define AREFEN 5 +-#define ISRCEN 6 +-#define ADHSM 7 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define ADC8D 0 +-#define ADC9D 1 +-#define ADC10D 2 +-#define AMP0ND 3 +-#define AMP0PD 4 +-#define ACMP0D 5 +-#define AMP2PD 6 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define DACON _SFR_MEM8(0x90) +-#define DAEN 0 +-#define DAOE 1 +-#define DALA 2 +-#define DATS0 4 +-#define DATS1 5 +-#define DATS2 6 +-#define DAATE 7 +- +-#define DAC _SFR_MEM16(0x91) +- +-#define DACL _SFR_MEM8(0x91) +-#define DACL0 0 +-#define DACL1 1 +-#define DACL2 2 +-#define DACL3 3 +-#define DACL4 4 +-#define DACL5 5 +-#define DACL6 6 +-#define DACL7 7 +- +-#define DACH _SFR_MEM8(0x92) +-#define DACH0 0 +-#define DACH1 1 +-#define DACH2 2 +-#define DACH3 3 +-#define DACH4 4 +-#define DACH5 5 +-#define DACH6 6 +-#define DACH7 7 +- +-#define AC0CON _SFR_MEM8(0x94) +-#define AC0M0 0 +-#define AC0M1 1 +-#define AC0M2 2 +-#define ACCKSEL 3 +-#define AC0IS0 4 +-#define AC0IS1 5 +-#define AC0IE 6 +-#define AC0EN 7 +- +-#define AC1CON _SFR_MEM8(0x95) +-#define AC1M0 0 +-#define AC1M1 1 +-#define AC1M2 2 +-#define AC1ICE 3 +-#define AC1IS0 4 +-#define AC1IS1 5 +-#define AC1IE 6 +-#define AC1EN 7 +- +-#define AC2CON _SFR_MEM8(0x96) +-#define AC2M0 0 +-#define AC2M1 1 +-#define AC2M2 2 +-#define AC2IS0 4 +-#define AC2IS1 5 +-#define AC2IE 6 +-#define AC2EN 7 +- +-#define AC3CON _SFR_MEM8(0x97) +-#define AC3M0 0 +-#define AC3M1 1 +-#define AC3M2 2 +-#define AC3IS0 4 +-#define AC3IS1 5 +-#define AC3IE 6 +-#define AC3EN 7 +- +-#define POCR0SA _SFR_MEM16(0xA0) +- +-#define POCR0SAL _SFR_MEM8(0xA0) +-#define POCR0SA_0 0 +-#define POCR0SA_1 1 +-#define POCR0SA_2 2 +-#define POCR0SA_3 3 +-#define POCR0SA_4 4 +-#define POCR0SA_5 5 +-#define POCR0SA_6 6 +-#define POCR0SA_7 7 +- +-#define POCR0SAH _SFR_MEM8(0xA1) +-#define POCR0SA_8 0 +-#define POCR0SA_9 1 +-#define POCR0SA_10 2 +-#define POCR0SA_11 3 +- +-#define POCR0RA _SFR_MEM16(0xA2) +- +-#define POCR0RAL _SFR_MEM8(0xA2) +-#define POCR0RA_0 0 +-#define POCR0RA_1 1 +-#define POCR0RA_2 2 +-#define POCR0RA_3 3 +-#define POCR0RA_4 4 +-#define POCR0RA_5 5 +-#define POCR0RA_6 6 +-#define POCR0RA_7 7 +- +-#define POCR0RAH _SFR_MEM8(0xA3) +-#define POCR0RA_8 0 +-#define POCR0RA_9 1 +-#define POCR0RA_10 2 +-#define POCR0RA_11 3 +- +-#define POCR0SB _SFR_MEM16(0xA4) +- +-#define POCR0SBL _SFR_MEM8(0xA4) +-#define POCR0SB_0 0 +-#define POCR0SB_1 1 +-#define POCR0SB_2 2 +-#define POCR0SB_3 3 +-#define POCR0SB_4 4 +-#define POCR0SB_5 5 +-#define POCR0SB_6 6 +-#define POCR0SB_7 7 +- +-#define POCR0SBH _SFR_MEM8(0xA5) +-#define POCR0SB_8 0 +-#define POCR0SB_9 1 +-#define POCR0SB_10 2 +-#define POCR0SB_11 3 +- +-#define POCR1SA _SFR_MEM16(0xA6) +- +-#define POCR1SAL _SFR_MEM8(0xA6) +-#define POCR1SA_0 0 +-#define POCR1SA_1 1 +-#define POCR1SA_2 2 +-#define POCR1SA_3 3 +-#define POCR1SA_4 4 +-#define POCR1SA_5 5 +-#define POCR1SA_6 6 +-#define POCR1SA_7 7 +- +-#define POCR1SAH _SFR_MEM8(0xA7) +-#define POCR1SA_8 0 +-#define POCR1SA_9 1 +-#define POCR1SA_10 2 +-#define POCR1SA_11 3 +- +-#define POCR1RA _SFR_MEM16(0xA8) +- +-#define POCR1RAL _SFR_MEM8(0xA8) +-#define POCR1RA_0 0 +-#define POCR1RA_1 1 +-#define POCR1RA_2 2 +-#define POCR1RA_3 3 +-#define POCR1RA_4 4 +-#define POCR1RA_5 5 +-#define POCR1RA_6 6 +-#define POCR1RA_7 7 +- +-#define POCR1RAH _SFR_MEM8(0xA9) +-#define POCR1RA_8 0 +-#define POCR1RA_9 1 +-#define POCR1RA_10 2 +-#define POCR1RA_11 3 +- +-#define POCR1SB _SFR_MEM16(0xAA) +- +-#define POCR1SBL _SFR_MEM8(0xAA) +-#define POCR1SB_0 0 +-#define POCR1SB_1 1 +-#define POCR1SB_2 2 +-#define POCR1SB_3 3 +-#define POCR1SB_4 4 +-#define POCR1SB_5 5 +-#define POCR1SB_6 6 +-#define POCR1SB_7 7 +- +-#define POCR1SBH _SFR_MEM8(0xAB) +-#define POCR1SB_8 0 +-#define POCR1SB_9 1 +-#define POCR1SB_10 2 +-#define POCR1SB_11 3 +- +-#define POCR2SA _SFR_MEM16(0xAC) +- +-#define POCR2SAL _SFR_MEM8(0xAC) +-#define POCR2SA_0 0 +-#define POCR2SA_1 1 +-#define POCR2SA_2 2 +-#define POCR2SA_3 3 +-#define POCR2SA_4 4 +-#define POCR2SA_5 5 +-#define POCR2SA_6 6 +-#define POCR2SA_7 7 +- +-#define POCR2SAH _SFR_MEM8(0xAD) +-#define POCR2SA_8 0 +-#define POCR2SA_9 1 +-#define POCR2SA_10 2 +-#define POCR2SA_11 3 +- +-#define POCR2RA _SFR_MEM16(0xAE) +- +-#define POCR2RAL _SFR_MEM8(0xAE) +-#define POCR2RA_0 0 +-#define POCR2RA_1 1 +-#define POCR2RA_2 2 +-#define POCR2RA_3 3 +-#define POCR2RA_4 4 +-#define POCR2RA_5 5 +-#define POCR2RA_6 6 +-#define POCR2RA_7 7 +- +-#define POCR2RAH _SFR_MEM8(0xAF) +-#define POCR2RA_8 0 +-#define POCR2RA_9 1 +-#define POCR2RA_10 2 +-#define POCR2RA_11 3 +- +-#define POCR2SB _SFR_MEM16(0xB0) +- +-#define POCR2SBL _SFR_MEM8(0xB0) +-#define POCR2SB_0 0 +-#define POCR2SB_1 1 +-#define POCR2SB_2 2 +-#define POCR2SB_3 3 +-#define POCR2SB_4 4 +-#define POCR2SB_5 5 +-#define POCR2SB_6 6 +-#define POCR2SB_7 7 +- +-#define POCR2SBH _SFR_MEM8(0xB1) +-#define POCR2SB_8 0 +-#define POCR2SB_9 1 +-#define POCR2SB_10 2 +-#define POCR2SB_11 3 +- +-#define POCR_RB _SFR_MEM16(0xB2) +- +-#define POCR_RBL _SFR_MEM8(0xB2) +-#define POCR_RB_0 0 +-#define POCR_RB_1 1 +-#define POCR_RB_2 2 +-#define POCR_RB_3 3 +-#define POCR_RB_4 4 +-#define POCR_RB_5 5 +-#define POCR_RB_6 6 +-#define POCR_RB_7 7 +- +-#define POCR_RBH _SFR_MEM8(0xB3) +-#define POCR_RB_8 0 +-#define POCR_RB_9 1 +-#define POCR_RB_10 2 +-#define POCR_RB_11 3 +- +-#define PSYNC _SFR_MEM8(0xB4) +-#define PSYNC00 0 +-#define PSYNC01 1 +-#define PSYNC10 2 +-#define PSYNC11 3 +-#define PSYNC20 4 +-#define PSYNC21 5 +- +-#define PCNF _SFR_MEM8(0xB5) +-#define POPA 2 +-#define POPB 3 +-#define PMODE 4 +-#define PULOCK 5 +- +-#define POC _SFR_MEM8(0xB6) +-#define POEN0A 0 +-#define POEN0B 1 +-#define POEN1A 2 +-#define POEN1B 3 +-#define POEN2A 4 +-#define POEN2B 5 +- +-#define PCTL _SFR_MEM8(0xB7) +-#define PRUN 0 +-#define PCCYC 1 +-#define PCLKSEL 5 +-#define PPRE0 6 +-#define PPRE1 7 +- +-#define PMIC0 _SFR_MEM8(0xB8) +-#define PRFM00 0 +-#define PRFM01 1 +-#define PRFM02 2 +-#define PAOC0 3 +-#define PFLTE0 4 +-#define PELEV0 5 +-#define PISEL0 6 +-#define POVEN0 7 +- +-#define PMIC1 _SFR_MEM8(0xB9) +-#define PRFM10 0 +-#define PRFM11 1 +-#define PRFM12 2 +-#define PAOC1 3 +-#define PFLTE1 4 +-#define PELEV1 5 +-#define PISEL1 6 +-#define POVEN1 7 +- +-#define PMIC2 _SFR_MEM8(0xBA) +-#define PRFM20 0 +-#define PRFM21 1 +-#define PRFM22 2 +-#define PAOC2 3 +-#define PFLTE2 4 +-#define PELEV2 5 +-#define PISEL2 6 +-#define POVEN2 7 +- +-#define PIM _SFR_MEM8(0xBB) +-#define PEOPE 0 +-#define PEVE0 1 +-#define PEVE1 2 +-#define PEVE2 3 +- +-#define PIFR _SFR_MEM8(0xBC) +-#define PEOP 0 +-#define PEV0 1 +-#define PEV1 2 +-#define PEV2 3 +- +-#define LINCR _SFR_MEM8(0xC8) +-#define LCMD0 0 +-#define LCMD1 1 +-#define LCMD2 2 +-#define LENA 3 +-#define LCONF0 4 +-#define LCONF1 5 +-#define LIN13 6 +-#define LSWRES 7 +- +-#define LINSIR _SFR_MEM8(0xC9) +-#define LRXOK 0 +-#define LTXOK 1 +-#define LIDOK 2 +-#define LERR 3 +-#define LBUSY 4 +-#define LIDST0 5 +-#define LIDST1 6 +-#define LIDST2 7 +- +-#define LINENIR _SFR_MEM8(0xCA) +-#define LENRXOK 0 +-#define LENTXOK 1 +-#define LENIDOK 2 +-#define LENERR 3 +- +-#define LINERR _SFR_MEM8(0xCB) +-#define LBERR 0 +-#define LCERR 1 +-#define LPERR 2 +-#define LSERR 3 +-#define LFERR 4 +-#define LOVERR 5 +-#define LTOERR 6 +-#define LABORT 7 +- +-#define LINBTR _SFR_MEM8(0xCC) +-#define LBT0 0 +-#define LBT1 1 +-#define LBT2 2 +-#define LBT3 3 +-#define LBT4 4 +-#define LBT5 5 +-#define LDISR 7 +- +-#define LINBRR _SFR_MEM16(0xCD) +- +-#define LINBRRL _SFR_MEM8(0xCD) +-#define LDIV0 0 +-#define LDIV1 1 +-#define LDIV2 2 +-#define LDIV3 3 +-#define LDIV4 4 +-#define LDIV5 5 +-#define LDIV6 6 +-#define LDIV7 7 +- +-#define LINBRRH _SFR_MEM8(0xCE) +-#define LDIV8 0 +-#define LDIV9 1 +-#define LDIV10 2 +-#define LDIV11 3 +- +-#define LINDLR _SFR_MEM8(0xCF) +-#define LRXDL0 0 +-#define LRXDL1 1 +-#define LRXDL2 2 +-#define LRXDL3 3 +-#define LTXDL0 4 +-#define LTXDL1 5 +-#define LTXDL2 6 +-#define LTXDL3 7 +- +-#define LINIDR _SFR_MEM8(0xD0) +-#define LID0 0 +-#define LID1 1 +-#define LID2 2 +-#define LID3 3 +-#define LID4 4 +-#define LID5 5 +-#define LP0 6 +-#define LP1 7 +- +-#define LINSEL _SFR_MEM8(0xD1) +-#define LINDX0 0 +-#define LINDX1 1 +-#define LINDX2 2 +-#define LAINC 3 +- +-#define LINDAT _SFR_MEM8(0xD2) +-#define LDATA0 0 +-#define LDATA1 1 +-#define LDATA2 2 +-#define LDATA3 3 +-#define LDATA4 4 +-#define LDATA5 5 +-#define LDATA6 6 +-#define LDATA7 7 +- +-#define CANGCON _SFR_MEM8(0xD8) +-#define SWRES 0 +-#define ENASTB 1 +-#define TEST 2 +-#define LISTEN 3 +-#define SYNTTC 4 +-#define TTC 5 +-#define OVRQ 6 +-#define ABRQ 7 +- +-#define CANGSTA _SFR_MEM8(0xD9) +-#define ERRP 0 +-#define BOFF 1 +-#define ENFG 2 +-#define RXBSY 3 +-#define TXBSY 4 +-#define OVFG 6 +- +-#define CANGIT _SFR_MEM8(0xDA) +-#define AERG 0 +-#define FERG 1 +-#define CERG 2 +-#define SERG 3 +-#define BXOK 4 +-#define OVRTIM 5 +-#define BOFFIT 6 +-#define CANIT 7 +- +-#define CANGIE _SFR_MEM8(0xDB) +-#define ENOVRT 0 +-#define ENERG 1 +-#define ENBX 2 +-#define ENERR 3 +-#define ENTX 4 +-#define ENRX 5 +-#define ENBOFF 6 +-#define ENIT 7 +- +-#define CANEN2 _SFR_MEM8(0xDC) +-#define ENMOB0 0 +-#define ENMOB1 1 +-#define ENMOB2 2 +-#define ENMOB3 3 +-#define ENMOB4 4 +-#define ENMOB5 5 +- +-#define CANEN1 _SFR_MEM8(0xDD) +- +-#define CANIE2 _SFR_MEM8(0xDE) +-#define IEMOB0 0 +-#define IEMOB1 1 +-#define IEMOB2 2 +-#define IEMOB3 3 +-#define IEMOB4 4 +-#define IEMOB5 5 +- +-#define CANIE1 _SFR_MEM8(0xDF) +- +-/* RegDef: CAN Status Interrupt MOb Register*/ +-#define CANSIT _SFR_MEM16(0xE0) +- +-#define CANSIT2 _SFR_MEM8(0xE0) +-#define SIT0 0 +-#define SIT1 1 +-#define SIT2 2 +-#define SIT3 3 +-#define SIT4 4 +-#define SIT5 5 +- +-#define CANSIT1 _SFR_MEM8(0xE1) +- +-#define CANBT1 _SFR_MEM8(0xE2) +-#define BRP0 1 +-#define BRP1 2 +-#define BRP2 3 +-#define BRP3 4 +-#define BRP4 5 +-#define BRP5 6 +- +-#define CANBT2 _SFR_MEM8(0xE3) +-#define PRS0 1 +-#define PRS1 2 +-#define PRS2 3 +-#define SJW0 5 +-#define SJW1 6 +- +-#define CANBT3 _SFR_MEM8(0xE4) +-#define SMP 0 +-#define PHS10 1 +-#define PHS11 2 +-#define PHS12 3 +-#define PHS20 4 +-#define PHS21 5 +-#define PHS22 6 +- +-#define CANTCON _SFR_MEM8(0xE5) +-#define TPRSC0 0 +-#define TPRSC1 1 +-#define TPRSC2 2 +-#define TPRSC3 3 +-#define TPRSC4 4 +-#define TPRSC5 5 +-#define TPRSC6 6 +-#define TPRSC7 7 +- +-#define CANTIM _SFR_MEM16(0xE6) +- +-#define CANTIML _SFR_MEM8(0xE6) +-#define CANTIM0 0 +-#define CANTIM1 1 +-#define CANTIM2 2 +-#define CANTIM3 3 +-#define CANTIM4 4 +-#define CANTIM5 5 +-#define CANTIM6 6 +-#define CANTIM7 7 +- +-#define CANTIMH _SFR_MEM8(0xE7) +-#define CANTIM8 0 +-#define CANTIM9 1 +-#define CANTIM10 2 +-#define CANTIM11 3 +-#define CANTIM12 4 +-#define CANTIM13 5 +-#define CANTIM14 6 +-#define CANTIM15 7 +- +-#define CANTTC _SFR_MEM16(0xE8) +- +-#define CANTTCL _SFR_MEM8(0xE8) +-#define TIMTCC0 0 +-#define TIMTCC1 1 +-#define TIMTCC2 2 +-#define TIMTCC3 3 +-#define TIMTCC4 4 +-#define TIMTCC5 5 +-#define TIMTCC6 6 +-#define TIMTCC7 7 +- +-#define CANTTCH _SFR_MEM8(0xE9) +-#define TIMTCC8 0 +-#define TIMTCC9 1 +-#define TIMTCC10 2 +-#define TIMTCC11 3 +-#define TIMTCC12 4 +-#define TIMTCC13 5 +-#define TIMTCC14 6 +-#define TIMTCC15 7 +- +-#define CANTEC _SFR_MEM8(0xEA) +-#define TEC0 0 +-#define TEC1 1 +-#define TEC2 2 +-#define TEC3 3 +-#define TEC4 4 +-#define TEC5 5 +-#define TEC6 6 +-#define TEC7 7 +- +-#define CANREC _SFR_MEM8(0xEB) +-#define REC0 0 +-#define REC1 1 +-#define REC2 2 +-#define REC3 3 +-#define REC4 4 +-#define REC5 5 +-#define REC6 6 +-#define REC7 7 +- +-#define CANHPMOB _SFR_MEM8(0xEC) +-#define CGP0 0 +-#define CGP1 1 +-#define CGP2 2 +-#define CGP3 3 +-#define HPMOB0 4 +-#define HPMOB1 5 +-#define HPMOB2 6 +-#define HPMOB3 7 +- +-#define CANPAGE _SFR_MEM8(0xED) +-#define INDX0 0 +-#define INDX1 1 +-#define INDX2 2 +-#define AINC 3 +-#define MOBNB0 4 +-#define MOBNB1 5 +-#define MOBNB2 6 +-#define MOBNB3 7 +- +-#define CANSTMOB _SFR_MEM8(0xEE) +-#define AERR 0 +-#define FERR 1 +-#define CERR 2 +-#define SERR 3 +-#define BERR 4 +-#define RXOK 5 +-#define TXOK 6 +-#define DLCW 7 +- +-#define CANCDMOB _SFR_MEM8(0xEF) +-#define DLC0 0 +-#define DLC1 1 +-#define DLC2 2 +-#define DLC3 3 +-#define IDE 4 +-#define RPLV 5 +-#define CONMOB0 6 +-#define CONMOB1 7 +- +-/* RegDef: CAN Identifier Tag Registers*/ +-#define CANIDT _SFR_MEM32(0xF0) +- +-#define CANIDT4 _SFR_MEM8(0xF0) +-#define RB0TAG 0 +-#define RB1TAG 1 +-#define RTRTAG 2 +-#define IDT0 3 +-#define IDT1 4 +-#define IDT2 5 +-#define IDT3 6 +-#define IDT4 7 +- +-#define CANIDT3 _SFR_MEM8(0xF1) +-#define IDT5 0 +-#define IDT6 1 +-#define IDT7 2 +-#define IDT8 3 +-#define IDT9 4 +-#define IDT10 5 +-#define IDT11 6 +-#define IDT12 7 +- +-#define CANIDT2 _SFR_MEM8(0xF2) +-#define IDT13 0 +-#define IDT14 1 +-#define IDT15 2 +-#define IDT16 3 +-#define IDT17 4 +-#define IDT18 5 +-#define IDT19 6 +-#define IDT20 7 +- +-#define CANIDT1 _SFR_MEM8(0xF3) +-#define IDT21 0 +-#define IDT22 1 +-#define IDT23 2 +-#define IDT24 3 +-#define IDT25 4 +-#define IDT26 5 +-#define IDT27 6 +-#define IDT28 7 +- +-/* RegDef: CAN Identifier Mask Registers */ +-#define CANIDM _SFR_MEM32(0xF4) +- +-#define CANIDM4 _SFR_MEM8(0xF4) +-#define IDEMSK 0 +-#define RTRMSK 2 +-#define IDMSK0 3 +-#define IDMSK1 4 +-#define IDMSK2 5 +-#define IDMSK3 6 +-#define IDMSK4 7 +- +-#define CANIDM3 _SFR_MEM8(0xF5) +-#define IDMSK5 0 +-#define IDMSK6 1 +-#define IDMSK7 2 +-#define IDMSK8 3 +-#define IDMSK9 4 +-#define IDMSK10 5 +-#define IDMSK11 6 +-#define IDMSK12 7 +- +-#define CANIDM2 _SFR_MEM8(0xF6) +-#define IDMSK13 0 +-#define IDMSK14 1 +-#define IDMSK15 2 +-#define IDMSK16 3 +-#define IDMSK17 4 +-#define IDMSK18 5 +-#define IDMSK19 6 +-#define IDMSK20 7 +- +-#define CANIDM1 _SFR_MEM8(0xF7) +-#define IDMSK21 0 +-#define IDMSK22 1 +-#define IDMSK23 2 +-#define IDMSK24 3 +-#define IDMSK25 4 +-#define IDMSK26 5 +-#define IDMSK27 6 +-#define IDMSK28 7 +- +-#define CANSTM _SFR_MEM16(0xF8) +- +-#define CANSTML _SFR_MEM8(0xF8) +-#define TIMSTM0 0 +-#define TIMSTM1 1 +-#define TIMSTM2 2 +-#define TIMSTM3 3 +-#define TIMSTM4 4 +-#define TIMSTM5 5 +-#define TIMSTM6 6 +-#define TIMSTM7 7 +- +-#define CANSTMH _SFR_MEM8(0xF9) +-#define TIMSTM8 0 +-#define TIMSTM9 1 +-#define TIMSTM10 2 +-#define TIMSTM11 3 +-#define TIMSTM12 4 +-#define TIMSTM13 5 +-#define TIMSTM14 6 +-#define TIMSTM15 7 +- +-#define CANMSG _SFR_MEM8(0xFA) +-#define MSG0 0 +-#define MSG1 1 +-#define MSG2 2 +-#define MSG3 3 +-#define MSG4 4 +-#define MSG5 5 +-#define MSG6 6 +-#define MSG7 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define ANACOMP0_vect_num 1 +-#define ANACOMP0_vect _VECTOR(1) /* Analog Comparator 0 */ +-#define ANACOMP1_vect_num 2 +-#define ANACOMP1_vect _VECTOR(2) /* Analog Comparator 1 */ +-#define ANACOMP2_vect_num 3 +-#define ANACOMP2_vect _VECTOR(3) /* Analog Comparator 2 */ +-#define ANACOMP3_vect_num 4 +-#define ANACOMP3_vect _VECTOR(4) /* Analog Comparator 3 */ +-#define PSC_FAULT_vect_num 5 +-#define PSC_FAULT_vect _VECTOR(5) /* PSC Fault */ +-#define PSC_EC_vect_num 6 +-#define PSC_EC_vect _VECTOR(6) /* PSC End of Cycle */ +-#define INT0_vect_num 7 +-#define INT0_vect _VECTOR(7) /* External Interrupt Request 0 */ +-#define INT1_vect_num 8 +-#define INT1_vect _VECTOR(8) /* External Interrupt Request 1 */ +-#define INT2_vect_num 9 +-#define INT2_vect _VECTOR(9) /* External Interrupt Request 2 */ +-#define INT3_vect_num 10 +-#define INT3_vect _VECTOR(10) /* External Interrupt Request 3 */ +-#define TIMER1_CAPT_vect_num 11 +-#define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */ +-#define TIMER1_COMPA_vect_num 12 +-#define TIMER1_COMPA_vect _VECTOR(12) /* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPB_vect_num 13 +-#define TIMER1_COMPB_vect _VECTOR(13) /* Timer/Counter1 Compare Match B */ +-#define TIMER1_OVF_vect_num 14 +-#define TIMER1_OVF_vect _VECTOR(14) /* Timer1/Counter1 Overflow */ +-#define TIMER0_COMPA_vect_num 15 +-#define TIMER0_COMPA_vect _VECTOR(15) /* Timer/Counter0 Compare Match A */ +-#define TIMER0_COMPB_vect_num 16 +-#define TIMER0_COMPB_vect _VECTOR(16) /* Timer/Counter0 Compare Match B */ +-#define TIMER0_OVF_vect_num 17 +-#define TIMER0_OVF_vect _VECTOR(17) /* Timer/Counter0 Overflow */ +-#define CAN_INT_vect_num 18 +-#define CAN_INT_vect _VECTOR(18) /* CAN MOB, Burst, General Errors */ +-#define CAN_TOVF_vect_num 19 +-#define CAN_TOVF_vect _VECTOR(19) /* CAN Timer Overflow */ +-#define LIN_TC_vect_num 20 +-#define LIN_TC_vect _VECTOR(20) /* LIN Transfer Complete */ +-#define LIN_ERR_vect_num 21 +-#define LIN_ERR_vect _VECTOR(21) /* LIN Error */ +-#define PCINT0_vect_num 22 +-#define PCINT0_vect _VECTOR(22) /* Pin Change Interrupt Request 0 */ +-#define PCINT1_vect_num 23 +-#define PCINT1_vect _VECTOR(23) /* Pin Change Interrupt Request 1 */ +-#define PCINT2_vect_num 24 +-#define PCINT2_vect _VECTOR(24) /* Pin Change Interrupt Request 2 */ +-#define PCINT3_vect_num 25 +-#define PCINT3_vect _VECTOR(25) /* Pin Change Interrupt Request 3 */ +-#define SPI_STC_vect_num 26 +-#define SPI_STC_vect _VECTOR(26) /* SPI Serial Transfer Complete */ +-#define ADC_vect_num 27 +-#define ADC_vect _VECTOR(27) /* ADC Conversion Complete */ +-#define WDT_vect_num 28 +-#define WDT_vect _VECTOR(28) /* Watchdog Time-Out Interrupt */ +-#define EE_READY_vect_num 29 +-#define EE_READY_vect _VECTOR(29) /* EEPROM Ready */ +-#define SPM_READY_vect_num 30 +-#define SPM_READY_vect _VECTOR(30) /* Store Program Memory Read */ +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (31 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (256) +-#define RAMSTART (0x0100) +-#define RAMSIZE (4096) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (0x0) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x7FF) +-#define E2PAGESIZE (8) +-#define FLASHEND (0xFFFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector Trigger Level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector Trigger Level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector Trigger Level */ +-#define FUSE_PSCRVB (unsigned char)~_BV(3) /* PSC Outputs xB Reset Value */ +-#define FUSE_PSCRVA (unsigned char)~_BV(4) /* PSC Outputs xA Reset Value */ +-#define FUSE_PSCRB (unsigned char)~_BV(5) /* PSC Reset Behavior */ +-#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_BODLEVEL1) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x96 +-#define SIGNATURE_2 0x84 +- +- +-#endif /* _AVR_ATmega64M1_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom64m1.h 2183 2010-09-21 05:37:46Z aboyapati $ */ ++ ++/* avr/iom64m1.h - definitions for ATmega64M1 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom64m1.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATmega64M1_H_ ++#define _AVR_ATmega64M1_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++#define PINC7 7 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++#define DDC7 7 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC3 3 ++#define PORTC4 4 ++#define PORTC5 5 ++#define PORTC6 6 ++#define PORTC7 7 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE0 0 ++#define PINE1 1 ++#define PINE2 2 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE0 0 ++#define DDE1 1 ++#define DDE2 2 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE0 0 ++#define PORTE1 1 ++#define PORTE2 2 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define GPIOR1 _SFR_IO8(0x19) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x1A) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++#define PCIF3 3 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++#define INT3 3 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++#define EEAR9 1 ++#define EEAR10 2 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR10 0 ++#define PSRSYNC 0 ++#define ICPSEL1 6 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define OCR0A _SFR_IO8(0x27) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define OCR0B _SFR_IO8(0x28) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define PLLCSR _SFR_IO8(0x29) ++#define PLOCK 0 ++#define PLLE 1 ++#define PLLF 2 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define ACSR _SFR_IO8(0x30) ++#define AC0O 0 ++#define AC1O 1 ++#define AC2O 2 ++#define AC3O 3 ++#define AC0IF 4 ++#define AC1IF 5 ++#define AC2IF 6 ++#define AC3IF 7 ++ ++#define DWDR _SFR_IO8(0x31) ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define SPIPS 7 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRLIN 1 ++#define PRSPI 2 ++#define PRTIM0 3 ++#define PRTIM1 4 ++#define PRPSC 5 ++#define PRCAN 6 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++#define PCIE3 3 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++#define PCMSK0 _SFR_MEM8(0x6A) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6B) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK2 _SFR_MEM8(0x6C) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define PCMSK3 _SFR_MEM8(0x6D) ++#define PCINT24 0 ++#define PCINT25 1 ++#define PCINT26 2 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define AMP0CSR _SFR_MEM8(0x75) ++#define AMP0TS0 0 ++#define AMP0TS1 1 ++#define AMP0TS2 2 ++#define AMPCMP0 3 ++#define AMP0G0 4 ++#define AMP0G1 5 ++#define AMP0IS 6 ++#define AMP0EN 7 ++ ++#define AMP1CSR _SFR_MEM8(0x76) ++#define AMP1TS0 0 ++#define AMP1TS1 1 ++#define AMP1TS2 2 ++#define AMPCMP1 3 ++#define AMP1G0 4 ++#define AMP1G1 5 ++#define AMP1IS 6 ++#define AMP1EN 7 ++ ++#define AMP2CSR _SFR_MEM8(0x77) ++#define AMP2TS0 0 ++#define AMP2TS1 1 ++#define AMP2TS2 2 ++#define AMPCMP2 3 ++#define AMP2G0 4 ++#define AMP2G1 5 ++#define AMP2IS 6 ++#define AMP2EN 7 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_MEM8(0x79) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ADTS3 3 ++#define AREFEN 5 ++#define ISRCEN 6 ++#define ADHSM 7 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define ADC8D 0 ++#define ADC9D 1 ++#define ADC10D 2 ++#define AMP0ND 3 ++#define AMP0PD 4 ++#define ACMP0D 5 ++#define AMP2PD 6 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define DACON _SFR_MEM8(0x90) ++#define DAEN 0 ++#define DAOE 1 ++#define DALA 2 ++#define DATS0 4 ++#define DATS1 5 ++#define DATS2 6 ++#define DAATE 7 ++ ++#define DAC _SFR_MEM16(0x91) ++ ++#define DACL _SFR_MEM8(0x91) ++#define DACL0 0 ++#define DACL1 1 ++#define DACL2 2 ++#define DACL3 3 ++#define DACL4 4 ++#define DACL5 5 ++#define DACL6 6 ++#define DACL7 7 ++ ++#define DACH _SFR_MEM8(0x92) ++#define DACH0 0 ++#define DACH1 1 ++#define DACH2 2 ++#define DACH3 3 ++#define DACH4 4 ++#define DACH5 5 ++#define DACH6 6 ++#define DACH7 7 ++ ++#define AC0CON _SFR_MEM8(0x94) ++#define AC0M0 0 ++#define AC0M1 1 ++#define AC0M2 2 ++#define ACCKSEL 3 ++#define AC0IS0 4 ++#define AC0IS1 5 ++#define AC0IE 6 ++#define AC0EN 7 ++ ++#define AC1CON _SFR_MEM8(0x95) ++#define AC1M0 0 ++#define AC1M1 1 ++#define AC1M2 2 ++#define AC1ICE 3 ++#define AC1IS0 4 ++#define AC1IS1 5 ++#define AC1IE 6 ++#define AC1EN 7 ++ ++#define AC2CON _SFR_MEM8(0x96) ++#define AC2M0 0 ++#define AC2M1 1 ++#define AC2M2 2 ++#define AC2IS0 4 ++#define AC2IS1 5 ++#define AC2IE 6 ++#define AC2EN 7 ++ ++#define AC3CON _SFR_MEM8(0x97) ++#define AC3M0 0 ++#define AC3M1 1 ++#define AC3M2 2 ++#define AC3IS0 4 ++#define AC3IS1 5 ++#define AC3IE 6 ++#define AC3EN 7 ++ ++#define POCR0SA _SFR_MEM16(0xA0) ++ ++#define POCR0SAL _SFR_MEM8(0xA0) ++#define POCR0SA_0 0 ++#define POCR0SA_1 1 ++#define POCR0SA_2 2 ++#define POCR0SA_3 3 ++#define POCR0SA_4 4 ++#define POCR0SA_5 5 ++#define POCR0SA_6 6 ++#define POCR0SA_7 7 ++ ++#define POCR0SAH _SFR_MEM8(0xA1) ++#define POCR0SA_8 0 ++#define POCR0SA_9 1 ++#define POCR0SA_10 2 ++#define POCR0SA_11 3 ++ ++#define POCR0RA _SFR_MEM16(0xA2) ++ ++#define POCR0RAL _SFR_MEM8(0xA2) ++#define POCR0RA_0 0 ++#define POCR0RA_1 1 ++#define POCR0RA_2 2 ++#define POCR0RA_3 3 ++#define POCR0RA_4 4 ++#define POCR0RA_5 5 ++#define POCR0RA_6 6 ++#define POCR0RA_7 7 ++ ++#define POCR0RAH _SFR_MEM8(0xA3) ++#define POCR0RA_8 0 ++#define POCR0RA_9 1 ++#define POCR0RA_10 2 ++#define POCR0RA_11 3 ++ ++#define POCR0SB _SFR_MEM16(0xA4) ++ ++#define POCR0SBL _SFR_MEM8(0xA4) ++#define POCR0SB_0 0 ++#define POCR0SB_1 1 ++#define POCR0SB_2 2 ++#define POCR0SB_3 3 ++#define POCR0SB_4 4 ++#define POCR0SB_5 5 ++#define POCR0SB_6 6 ++#define POCR0SB_7 7 ++ ++#define POCR0SBH _SFR_MEM8(0xA5) ++#define POCR0SB_8 0 ++#define POCR0SB_9 1 ++#define POCR0SB_10 2 ++#define POCR0SB_11 3 ++ ++#define POCR1SA _SFR_MEM16(0xA6) ++ ++#define POCR1SAL _SFR_MEM8(0xA6) ++#define POCR1SA_0 0 ++#define POCR1SA_1 1 ++#define POCR1SA_2 2 ++#define POCR1SA_3 3 ++#define POCR1SA_4 4 ++#define POCR1SA_5 5 ++#define POCR1SA_6 6 ++#define POCR1SA_7 7 ++ ++#define POCR1SAH _SFR_MEM8(0xA7) ++#define POCR1SA_8 0 ++#define POCR1SA_9 1 ++#define POCR1SA_10 2 ++#define POCR1SA_11 3 ++ ++#define POCR1RA _SFR_MEM16(0xA8) ++ ++#define POCR1RAL _SFR_MEM8(0xA8) ++#define POCR1RA_0 0 ++#define POCR1RA_1 1 ++#define POCR1RA_2 2 ++#define POCR1RA_3 3 ++#define POCR1RA_4 4 ++#define POCR1RA_5 5 ++#define POCR1RA_6 6 ++#define POCR1RA_7 7 ++ ++#define POCR1RAH _SFR_MEM8(0xA9) ++#define POCR1RA_8 0 ++#define POCR1RA_9 1 ++#define POCR1RA_10 2 ++#define POCR1RA_11 3 ++ ++#define POCR1SB _SFR_MEM16(0xAA) ++ ++#define POCR1SBL _SFR_MEM8(0xAA) ++#define POCR1SB_0 0 ++#define POCR1SB_1 1 ++#define POCR1SB_2 2 ++#define POCR1SB_3 3 ++#define POCR1SB_4 4 ++#define POCR1SB_5 5 ++#define POCR1SB_6 6 ++#define POCR1SB_7 7 ++ ++#define POCR1SBH _SFR_MEM8(0xAB) ++#define POCR1SB_8 0 ++#define POCR1SB_9 1 ++#define POCR1SB_10 2 ++#define POCR1SB_11 3 ++ ++#define POCR2SA _SFR_MEM16(0xAC) ++ ++#define POCR2SAL _SFR_MEM8(0xAC) ++#define POCR2SA_0 0 ++#define POCR2SA_1 1 ++#define POCR2SA_2 2 ++#define POCR2SA_3 3 ++#define POCR2SA_4 4 ++#define POCR2SA_5 5 ++#define POCR2SA_6 6 ++#define POCR2SA_7 7 ++ ++#define POCR2SAH _SFR_MEM8(0xAD) ++#define POCR2SA_8 0 ++#define POCR2SA_9 1 ++#define POCR2SA_10 2 ++#define POCR2SA_11 3 ++ ++#define POCR2RA _SFR_MEM16(0xAE) ++ ++#define POCR2RAL _SFR_MEM8(0xAE) ++#define POCR2RA_0 0 ++#define POCR2RA_1 1 ++#define POCR2RA_2 2 ++#define POCR2RA_3 3 ++#define POCR2RA_4 4 ++#define POCR2RA_5 5 ++#define POCR2RA_6 6 ++#define POCR2RA_7 7 ++ ++#define POCR2RAH _SFR_MEM8(0xAF) ++#define POCR2RA_8 0 ++#define POCR2RA_9 1 ++#define POCR2RA_10 2 ++#define POCR2RA_11 3 ++ ++#define POCR2SB _SFR_MEM16(0xB0) ++ ++#define POCR2SBL _SFR_MEM8(0xB0) ++#define POCR2SB_0 0 ++#define POCR2SB_1 1 ++#define POCR2SB_2 2 ++#define POCR2SB_3 3 ++#define POCR2SB_4 4 ++#define POCR2SB_5 5 ++#define POCR2SB_6 6 ++#define POCR2SB_7 7 ++ ++#define POCR2SBH _SFR_MEM8(0xB1) ++#define POCR2SB_8 0 ++#define POCR2SB_9 1 ++#define POCR2SB_10 2 ++#define POCR2SB_11 3 ++ ++#define POCR_RB _SFR_MEM16(0xB2) ++ ++#define POCR_RBL _SFR_MEM8(0xB2) ++#define POCR_RB_0 0 ++#define POCR_RB_1 1 ++#define POCR_RB_2 2 ++#define POCR_RB_3 3 ++#define POCR_RB_4 4 ++#define POCR_RB_5 5 ++#define POCR_RB_6 6 ++#define POCR_RB_7 7 ++ ++#define POCR_RBH _SFR_MEM8(0xB3) ++#define POCR_RB_8 0 ++#define POCR_RB_9 1 ++#define POCR_RB_10 2 ++#define POCR_RB_11 3 ++ ++#define PSYNC _SFR_MEM8(0xB4) ++#define PSYNC00 0 ++#define PSYNC01 1 ++#define PSYNC10 2 ++#define PSYNC11 3 ++#define PSYNC20 4 ++#define PSYNC21 5 ++ ++#define PCNF _SFR_MEM8(0xB5) ++#define POPA 2 ++#define POPB 3 ++#define PMODE 4 ++#define PULOCK 5 ++ ++#define POC _SFR_MEM8(0xB6) ++#define POEN0A 0 ++#define POEN0B 1 ++#define POEN1A 2 ++#define POEN1B 3 ++#define POEN2A 4 ++#define POEN2B 5 ++ ++#define PCTL _SFR_MEM8(0xB7) ++#define PRUN 0 ++#define PCCYC 1 ++#define PCLKSEL 5 ++#define PPRE0 6 ++#define PPRE1 7 ++ ++#define PMIC0 _SFR_MEM8(0xB8) ++#define PRFM00 0 ++#define PRFM01 1 ++#define PRFM02 2 ++#define PAOC0 3 ++#define PFLTE0 4 ++#define PELEV0 5 ++#define PISEL0 6 ++#define POVEN0 7 ++ ++#define PMIC1 _SFR_MEM8(0xB9) ++#define PRFM10 0 ++#define PRFM11 1 ++#define PRFM12 2 ++#define PAOC1 3 ++#define PFLTE1 4 ++#define PELEV1 5 ++#define PISEL1 6 ++#define POVEN1 7 ++ ++#define PMIC2 _SFR_MEM8(0xBA) ++#define PRFM20 0 ++#define PRFM21 1 ++#define PRFM22 2 ++#define PAOC2 3 ++#define PFLTE2 4 ++#define PELEV2 5 ++#define PISEL2 6 ++#define POVEN2 7 ++ ++#define PIM _SFR_MEM8(0xBB) ++#define PEOPE 0 ++#define PEVE0 1 ++#define PEVE1 2 ++#define PEVE2 3 ++ ++#define PIFR _SFR_MEM8(0xBC) ++#define PEOP 0 ++#define PEV0 1 ++#define PEV1 2 ++#define PEV2 3 ++ ++#define LINCR _SFR_MEM8(0xC8) ++#define LCMD0 0 ++#define LCMD1 1 ++#define LCMD2 2 ++#define LENA 3 ++#define LCONF0 4 ++#define LCONF1 5 ++#define LIN13 6 ++#define LSWRES 7 ++ ++#define LINSIR _SFR_MEM8(0xC9) ++#define LRXOK 0 ++#define LTXOK 1 ++#define LIDOK 2 ++#define LERR 3 ++#define LBUSY 4 ++#define LIDST0 5 ++#define LIDST1 6 ++#define LIDST2 7 ++ ++#define LINENIR _SFR_MEM8(0xCA) ++#define LENRXOK 0 ++#define LENTXOK 1 ++#define LENIDOK 2 ++#define LENERR 3 ++ ++#define LINERR _SFR_MEM8(0xCB) ++#define LBERR 0 ++#define LCERR 1 ++#define LPERR 2 ++#define LSERR 3 ++#define LFERR 4 ++#define LOVERR 5 ++#define LTOERR 6 ++#define LABORT 7 ++ ++#define LINBTR _SFR_MEM8(0xCC) ++#define LBT0 0 ++#define LBT1 1 ++#define LBT2 2 ++#define LBT3 3 ++#define LBT4 4 ++#define LBT5 5 ++#define LDISR 7 ++ ++#define LINBRR _SFR_MEM16(0xCD) ++ ++#define LINBRRL _SFR_MEM8(0xCD) ++#define LDIV0 0 ++#define LDIV1 1 ++#define LDIV2 2 ++#define LDIV3 3 ++#define LDIV4 4 ++#define LDIV5 5 ++#define LDIV6 6 ++#define LDIV7 7 ++ ++#define LINBRRH _SFR_MEM8(0xCE) ++#define LDIV8 0 ++#define LDIV9 1 ++#define LDIV10 2 ++#define LDIV11 3 ++ ++#define LINDLR _SFR_MEM8(0xCF) ++#define LRXDL0 0 ++#define LRXDL1 1 ++#define LRXDL2 2 ++#define LRXDL3 3 ++#define LTXDL0 4 ++#define LTXDL1 5 ++#define LTXDL2 6 ++#define LTXDL3 7 ++ ++#define LINIDR _SFR_MEM8(0xD0) ++#define LID0 0 ++#define LID1 1 ++#define LID2 2 ++#define LID3 3 ++#define LID4 4 ++#define LID5 5 ++#define LP0 6 ++#define LP1 7 ++ ++#define LINSEL _SFR_MEM8(0xD1) ++#define LINDX0 0 ++#define LINDX1 1 ++#define LINDX2 2 ++#define LAINC 3 ++ ++#define LINDAT _SFR_MEM8(0xD2) ++#define LDATA0 0 ++#define LDATA1 1 ++#define LDATA2 2 ++#define LDATA3 3 ++#define LDATA4 4 ++#define LDATA5 5 ++#define LDATA6 6 ++#define LDATA7 7 ++ ++#define CANGCON _SFR_MEM8(0xD8) ++#define SWRES 0 ++#define ENASTB 1 ++#define TEST 2 ++#define LISTEN 3 ++#define SYNTTC 4 ++#define TTC 5 ++#define OVRQ 6 ++#define ABRQ 7 ++ ++#define CANGSTA _SFR_MEM8(0xD9) ++#define ERRP 0 ++#define BOFF 1 ++#define ENFG 2 ++#define RXBSY 3 ++#define TXBSY 4 ++#define OVFG 6 ++ ++#define CANGIT _SFR_MEM8(0xDA) ++#define AERG 0 ++#define FERG 1 ++#define CERG 2 ++#define SERG 3 ++#define BXOK 4 ++#define OVRTIM 5 ++#define BOFFIT 6 ++#define CANIT 7 ++ ++#define CANGIE _SFR_MEM8(0xDB) ++#define ENOVRT 0 ++#define ENERG 1 ++#define ENBX 2 ++#define ENERR 3 ++#define ENTX 4 ++#define ENRX 5 ++#define ENBOFF 6 ++#define ENIT 7 ++ ++#define CANEN2 _SFR_MEM8(0xDC) ++#define ENMOB0 0 ++#define ENMOB1 1 ++#define ENMOB2 2 ++#define ENMOB3 3 ++#define ENMOB4 4 ++#define ENMOB5 5 ++ ++#define CANEN1 _SFR_MEM8(0xDD) ++ ++#define CANIE2 _SFR_MEM8(0xDE) ++#define IEMOB0 0 ++#define IEMOB1 1 ++#define IEMOB2 2 ++#define IEMOB3 3 ++#define IEMOB4 4 ++#define IEMOB5 5 ++ ++#define CANIE1 _SFR_MEM8(0xDF) ++ ++/* RegDef: CAN Status Interrupt MOb Register*/ ++#define CANSIT _SFR_MEM16(0xE0) ++ ++#define CANSIT2 _SFR_MEM8(0xE0) ++#define SIT0 0 ++#define SIT1 1 ++#define SIT2 2 ++#define SIT3 3 ++#define SIT4 4 ++#define SIT5 5 ++ ++#define CANSIT1 _SFR_MEM8(0xE1) ++ ++#define CANBT1 _SFR_MEM8(0xE2) ++#define BRP0 1 ++#define BRP1 2 ++#define BRP2 3 ++#define BRP3 4 ++#define BRP4 5 ++#define BRP5 6 ++ ++#define CANBT2 _SFR_MEM8(0xE3) ++#define PRS0 1 ++#define PRS1 2 ++#define PRS2 3 ++#define SJW0 5 ++#define SJW1 6 ++ ++#define CANBT3 _SFR_MEM8(0xE4) ++#define SMP 0 ++#define PHS10 1 ++#define PHS11 2 ++#define PHS12 3 ++#define PHS20 4 ++#define PHS21 5 ++#define PHS22 6 ++ ++#define CANTCON _SFR_MEM8(0xE5) ++#define TPRSC0 0 ++#define TPRSC1 1 ++#define TPRSC2 2 ++#define TPRSC3 3 ++#define TPRSC4 4 ++#define TPRSC5 5 ++#define TPRSC6 6 ++#define TPRSC7 7 ++ ++#define CANTIM _SFR_MEM16(0xE6) ++ ++#define CANTIML _SFR_MEM8(0xE6) ++#define CANTIM0 0 ++#define CANTIM1 1 ++#define CANTIM2 2 ++#define CANTIM3 3 ++#define CANTIM4 4 ++#define CANTIM5 5 ++#define CANTIM6 6 ++#define CANTIM7 7 ++ ++#define CANTIMH _SFR_MEM8(0xE7) ++#define CANTIM8 0 ++#define CANTIM9 1 ++#define CANTIM10 2 ++#define CANTIM11 3 ++#define CANTIM12 4 ++#define CANTIM13 5 ++#define CANTIM14 6 ++#define CANTIM15 7 ++ ++#define CANTTC _SFR_MEM16(0xE8) ++ ++#define CANTTCL _SFR_MEM8(0xE8) ++#define TIMTCC0 0 ++#define TIMTCC1 1 ++#define TIMTCC2 2 ++#define TIMTCC3 3 ++#define TIMTCC4 4 ++#define TIMTCC5 5 ++#define TIMTCC6 6 ++#define TIMTCC7 7 ++ ++#define CANTTCH _SFR_MEM8(0xE9) ++#define TIMTCC8 0 ++#define TIMTCC9 1 ++#define TIMTCC10 2 ++#define TIMTCC11 3 ++#define TIMTCC12 4 ++#define TIMTCC13 5 ++#define TIMTCC14 6 ++#define TIMTCC15 7 ++ ++#define CANTEC _SFR_MEM8(0xEA) ++#define TEC0 0 ++#define TEC1 1 ++#define TEC2 2 ++#define TEC3 3 ++#define TEC4 4 ++#define TEC5 5 ++#define TEC6 6 ++#define TEC7 7 ++ ++#define CANREC _SFR_MEM8(0xEB) ++#define REC0 0 ++#define REC1 1 ++#define REC2 2 ++#define REC3 3 ++#define REC4 4 ++#define REC5 5 ++#define REC6 6 ++#define REC7 7 ++ ++#define CANHPMOB _SFR_MEM8(0xEC) ++#define CGP0 0 ++#define CGP1 1 ++#define CGP2 2 ++#define CGP3 3 ++#define HPMOB0 4 ++#define HPMOB1 5 ++#define HPMOB2 6 ++#define HPMOB3 7 ++ ++#define CANPAGE _SFR_MEM8(0xED) ++#define INDX0 0 ++#define INDX1 1 ++#define INDX2 2 ++#define AINC 3 ++#define MOBNB0 4 ++#define MOBNB1 5 ++#define MOBNB2 6 ++#define MOBNB3 7 ++ ++#define CANSTMOB _SFR_MEM8(0xEE) ++#define AERR 0 ++#define FERR 1 ++#define CERR 2 ++#define SERR 3 ++#define BERR 4 ++#define RXOK 5 ++#define TXOK 6 ++#define DLCW 7 ++ ++#define CANCDMOB _SFR_MEM8(0xEF) ++#define DLC0 0 ++#define DLC1 1 ++#define DLC2 2 ++#define DLC3 3 ++#define IDE 4 ++#define RPLV 5 ++#define CONMOB0 6 ++#define CONMOB1 7 ++ ++/* RegDef: CAN Identifier Tag Registers*/ ++#define CANIDT _SFR_MEM32(0xF0) ++ ++#define CANIDT4 _SFR_MEM8(0xF0) ++#define RB0TAG 0 ++#define RB1TAG 1 ++#define RTRTAG 2 ++#define IDT0 3 ++#define IDT1 4 ++#define IDT2 5 ++#define IDT3 6 ++#define IDT4 7 ++ ++#define CANIDT3 _SFR_MEM8(0xF1) ++#define IDT5 0 ++#define IDT6 1 ++#define IDT7 2 ++#define IDT8 3 ++#define IDT9 4 ++#define IDT10 5 ++#define IDT11 6 ++#define IDT12 7 ++ ++#define CANIDT2 _SFR_MEM8(0xF2) ++#define IDT13 0 ++#define IDT14 1 ++#define IDT15 2 ++#define IDT16 3 ++#define IDT17 4 ++#define IDT18 5 ++#define IDT19 6 ++#define IDT20 7 ++ ++#define CANIDT1 _SFR_MEM8(0xF3) ++#define IDT21 0 ++#define IDT22 1 ++#define IDT23 2 ++#define IDT24 3 ++#define IDT25 4 ++#define IDT26 5 ++#define IDT27 6 ++#define IDT28 7 ++ ++/* RegDef: CAN Identifier Mask Registers */ ++#define CANIDM _SFR_MEM32(0xF4) ++ ++#define CANIDM4 _SFR_MEM8(0xF4) ++#define IDEMSK 0 ++#define RTRMSK 2 ++#define IDMSK0 3 ++#define IDMSK1 4 ++#define IDMSK2 5 ++#define IDMSK3 6 ++#define IDMSK4 7 ++ ++#define CANIDM3 _SFR_MEM8(0xF5) ++#define IDMSK5 0 ++#define IDMSK6 1 ++#define IDMSK7 2 ++#define IDMSK8 3 ++#define IDMSK9 4 ++#define IDMSK10 5 ++#define IDMSK11 6 ++#define IDMSK12 7 ++ ++#define CANIDM2 _SFR_MEM8(0xF6) ++#define IDMSK13 0 ++#define IDMSK14 1 ++#define IDMSK15 2 ++#define IDMSK16 3 ++#define IDMSK17 4 ++#define IDMSK18 5 ++#define IDMSK19 6 ++#define IDMSK20 7 ++ ++#define CANIDM1 _SFR_MEM8(0xF7) ++#define IDMSK21 0 ++#define IDMSK22 1 ++#define IDMSK23 2 ++#define IDMSK24 3 ++#define IDMSK25 4 ++#define IDMSK26 5 ++#define IDMSK27 6 ++#define IDMSK28 7 ++ ++#define CANSTM _SFR_MEM16(0xF8) ++ ++#define CANSTML _SFR_MEM8(0xF8) ++#define TIMSTM0 0 ++#define TIMSTM1 1 ++#define TIMSTM2 2 ++#define TIMSTM3 3 ++#define TIMSTM4 4 ++#define TIMSTM5 5 ++#define TIMSTM6 6 ++#define TIMSTM7 7 ++ ++#define CANSTMH _SFR_MEM8(0xF9) ++#define TIMSTM8 0 ++#define TIMSTM9 1 ++#define TIMSTM10 2 ++#define TIMSTM11 3 ++#define TIMSTM12 4 ++#define TIMSTM13 5 ++#define TIMSTM14 6 ++#define TIMSTM15 7 ++ ++#define CANMSG _SFR_MEM8(0xFA) ++#define MSG0 0 ++#define MSG1 1 ++#define MSG2 2 ++#define MSG3 3 ++#define MSG4 4 ++#define MSG5 5 ++#define MSG6 6 ++#define MSG7 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define ANACOMP0_vect_num 1 ++#define ANACOMP0_vect _VECTOR(1) /* Analog Comparator 0 */ ++#define ANACOMP1_vect_num 2 ++#define ANACOMP1_vect _VECTOR(2) /* Analog Comparator 1 */ ++#define ANACOMP2_vect_num 3 ++#define ANACOMP2_vect _VECTOR(3) /* Analog Comparator 2 */ ++#define ANACOMP3_vect_num 4 ++#define ANACOMP3_vect _VECTOR(4) /* Analog Comparator 3 */ ++#define PSC_FAULT_vect_num 5 ++#define PSC_FAULT_vect _VECTOR(5) /* PSC Fault */ ++#define PSC_EC_vect_num 6 ++#define PSC_EC_vect _VECTOR(6) /* PSC End of Cycle */ ++#define INT0_vect_num 7 ++#define INT0_vect _VECTOR(7) /* External Interrupt Request 0 */ ++#define INT1_vect_num 8 ++#define INT1_vect _VECTOR(8) /* External Interrupt Request 1 */ ++#define INT2_vect_num 9 ++#define INT2_vect _VECTOR(9) /* External Interrupt Request 2 */ ++#define INT3_vect_num 10 ++#define INT3_vect _VECTOR(10) /* External Interrupt Request 3 */ ++#define TIMER1_CAPT_vect_num 11 ++#define TIMER1_CAPT_vect _VECTOR(11) /* Timer/Counter1 Capture Event */ ++#define TIMER1_COMPA_vect_num 12 ++#define TIMER1_COMPA_vect _VECTOR(12) /* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPB_vect_num 13 ++#define TIMER1_COMPB_vect _VECTOR(13) /* Timer/Counter1 Compare Match B */ ++#define TIMER1_OVF_vect_num 14 ++#define TIMER1_OVF_vect _VECTOR(14) /* Timer1/Counter1 Overflow */ ++#define TIMER0_COMPA_vect_num 15 ++#define TIMER0_COMPA_vect _VECTOR(15) /* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPB_vect_num 16 ++#define TIMER0_COMPB_vect _VECTOR(16) /* Timer/Counter0 Compare Match B */ ++#define TIMER0_OVF_vect_num 17 ++#define TIMER0_OVF_vect _VECTOR(17) /* Timer/Counter0 Overflow */ ++#define CAN_INT_vect_num 18 ++#define CAN_INT_vect _VECTOR(18) /* CAN MOB, Burst, General Errors */ ++#define CAN_TOVF_vect_num 19 ++#define CAN_TOVF_vect _VECTOR(19) /* CAN Timer Overflow */ ++#define LIN_TC_vect_num 20 ++#define LIN_TC_vect _VECTOR(20) /* LIN Transfer Complete */ ++#define LIN_ERR_vect_num 21 ++#define LIN_ERR_vect _VECTOR(21) /* LIN Error */ ++#define PCINT0_vect_num 22 ++#define PCINT0_vect _VECTOR(22) /* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect_num 23 ++#define PCINT1_vect _VECTOR(23) /* Pin Change Interrupt Request 1 */ ++#define PCINT2_vect_num 24 ++#define PCINT2_vect _VECTOR(24) /* Pin Change Interrupt Request 2 */ ++#define PCINT3_vect_num 25 ++#define PCINT3_vect _VECTOR(25) /* Pin Change Interrupt Request 3 */ ++#define SPI_STC_vect_num 26 ++#define SPI_STC_vect _VECTOR(26) /* SPI Serial Transfer Complete */ ++#define ADC_vect_num 27 ++#define ADC_vect _VECTOR(27) /* ADC Conversion Complete */ ++#define WDT_vect_num 28 ++#define WDT_vect _VECTOR(28) /* Watchdog Time-Out Interrupt */ ++#define EE_READY_vect_num 29 ++#define EE_READY_vect _VECTOR(29) /* EEPROM Ready */ ++#define SPM_READY_vect_num 30 ++#define SPM_READY_vect _VECTOR(30) /* Store Program Memory Read */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (31 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (256) ++#define RAMSTART (0x0100) ++#define RAMSIZE (4096) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (0x0) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x7FF) ++#define E2PAGESIZE (8) ++#define FLASHEND (0xFFFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator output option */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset Disable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector Trigger Level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector Trigger Level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector Trigger Level */ ++#define FUSE_PSCRVB (unsigned char)~_BV(3) /* PSC Outputs xB Reset Value */ ++#define FUSE_PSCRVA (unsigned char)~_BV(4) /* PSC Outputs xA Reset Value */ ++#define FUSE_PSCRB (unsigned char)~_BV(5) /* PSC Reset Behavior */ ++#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_BODLEVEL1) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x84 ++ ++ ++#endif /* _AVR_ATmega64M1_H_ */ ++ diff --git a/include/avr/iom64rfr2.h b/include/avr/iom64rfr2.h new file mode 100644 -index 0000000..321721e +index 0000000..2c9309f --- /dev/null +++ b/include/avr/iom64rfr2.h -@@ -0,0 +1,2574 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATMEGA64RFR2_H_INCLUDED -+#define _AVR_ATMEGA64RFR2_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iom64rfr2.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINA _SFR_IO8(0x00) -+#define PINA7 7 -+#define PINA6 6 -+#define PINA5 5 -+#define PINA4 4 -+#define PINA3 3 -+#define PINA2 2 -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x01) -+#define DDRA7 7 -+#define DDRA6 6 -+#define DDRA5 5 -+#define DDRA4 4 -+#define DDRA3 3 -+#define DDRA2 2 -+#define DDRA1 1 -+#define DDRA0 0 -+ -+#define PORTA _SFR_IO8(0x02) -+#define PORTA7 7 -+#define PORTA6 6 -+#define PORTA5 5 -+#define PORTA4 4 -+#define PORTA3 3 -+#define PORTA2 2 -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define PINB _SFR_IO8(0x03) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x04) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x05) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINC _SFR_IO8(0x06) -+#define PINC7 7 -+#define PINC6 6 -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x07) -+#define DDRC7 7 -+#define DDRC6 6 -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x08) -+#define PORTC7 7 -+#define PORTC6 6 -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PIND _SFR_IO8(0x09) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0A) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x0B) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+#define PINE _SFR_IO8(0x0C) -+#define PINE7 7 -+#define PINE6 6 -+#define PINE5 5 -+#define PINE4 4 -+#define PINE3 3 -+#define PINE2 2 -+#define PINE1 1 -+#define PINE0 0 -+ -+#define DDRE _SFR_IO8(0x0D) -+#define DDRE7 7 -+#define DDRE6 6 -+#define DDRE5 5 -+#define DDRE4 4 -+#define DDRE3 3 -+#define DDRE2 2 -+#define DDRE1 1 -+#define DDRE0 0 -+ -+#define PORTE _SFR_IO8(0x0E) -+#define PORTE7 7 -+#define PORTE6 6 -+#define PORTE5 5 -+#define PORTE4 4 -+#define PORTE3 3 -+#define PORTE2 2 -+#define PORTE1 1 -+#define PORTE0 0 -+ -+#define PINF _SFR_IO8(0x0F) -+#define PINF7 7 -+#define PINF6 6 -+#define PINF5 5 -+#define PINF4 4 -+#define PINF3 3 -+#define PINF2 2 -+#define PINF1 1 -+#define PINF0 0 -+ -+#define DDRF _SFR_IO8(0x10) -+#define DDRF7 7 -+#define DDRF6 6 -+#define DDRF5 5 -+#define DDRF4 4 -+#define DDRF3 3 -+#define DDRF2 2 -+#define DDRF1 1 -+#define DDRF0 0 -+ -+#define PORTF _SFR_IO8(0x11) -+#define PORTF7 7 -+#define PORTF6 6 -+#define PORTF5 5 -+#define PORTF4 4 -+#define PORTF3 3 -+#define PORTF2 2 -+#define PORTF1 1 -+#define PORTF0 0 -+ -+#define PING _SFR_IO8(0x12) -+#define PING7 7 -+#define PING6 6 -+#define PING5 5 -+#define PING4 4 -+#define PING3 3 -+#define PING2 2 -+#define PING1 1 -+#define PING0 0 -+ -+#define DDRG _SFR_IO8(0x13) -+#define DDRG7 7 -+#define DDRG6 6 -+#define DDRG5 5 -+#define DDRG4 4 -+#define DDRG3 3 -+#define DDRG2 2 -+#define DDRG1 1 -+#define DDRG0 0 -+ -+#define PORTG _SFR_IO8(0x14) -+#define PORTG7 7 -+#define PORTG6 6 -+#define PORTG5 5 -+#define PORTG4 4 -+#define PORTG3 3 -+#define PORTG2 2 -+#define PORTG1 1 -+#define PORTG0 0 -+ -+#define TIFR0 _SFR_IO8(0x15) -+#define TOV0 0 -+#define OCF0A 1 -+#define OCF0B 2 -+#define Res0 3 -+#define Res1 4 -+#define Res2 5 -+#define Res3 6 -+#define Res4 7 -+ -+#define TIFR1 _SFR_IO8(0x16) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define OCF1C 3 -+#define ICF1 5 -+ -+#define TIFR2 _SFR_IO8(0x17) -+#define TOV2 0 -+#define OCF2A 1 -+#define OCF2B 2 -+ -+#define TIFR3 _SFR_IO8(0x18) -+#define TOV3 0 -+#define OCF3A 1 -+#define OCF3B 2 -+#define OCF3C 3 -+#define ICF3 5 -+ -+#define TIFR4 _SFR_IO8(0x19) -+#define TOV4 0 -+#define OCF4A 1 -+#define OCF4B 2 -+#define OCF4C 3 -+#define ICF4 5 -+ -+#define TIFR5 _SFR_IO8(0x1A) -+#define TOV5 0 -+#define OCF5A 1 -+#define OCF5B 2 -+#define OCF5C 3 -+#define ICF5 5 -+ -+#define PCIFR _SFR_IO8(0x1B) -+#define PCIF0 0 -+#define PCIF1 1 -+#define PCIF2 2 -+ -+#define EIFR _SFR_IO8(0x1C) -+#define INTF0 0 -+#define INTF1 1 -+#define INTF2 2 -+#define INTF3 3 -+#define INTF4 4 -+#define INTF5 5 -+#define INTF6 6 -+#define INTF7 7 -+ -+#define EIMSK _SFR_IO8(0x1D) -+#define INT0 0 -+#define INT1 1 -+#define INT2 2 -+#define INT3 3 -+#define INT4 4 -+#define INT5 5 -+#define INT6 6 -+#define INT7 7 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+#define GPIOR00 0 -+#define GPIOR01 1 -+#define GPIOR02 2 -+#define GPIOR03 3 -+#define GPIOR04 4 -+#define GPIOR05 5 -+#define GPIOR06 6 -+#define GPIOR07 7 -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEPE 1 -+#define EEMPE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x21) -+ -+#define EEARL _SFR_IO8(0x21) -+#define EEARH _SFR_IO8(0x22) -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSRSYNC 0 -+#define PSRASY 1 -+#define TSM 7 -+ -+#define TCCR0A _SFR_IO8(0x24) -+#define WGM00 0 -+#define WGM01 1 -+#define COM0B0 4 -+#define COM0B1 5 -+#define COM0A0 6 -+#define COM0A1 7 -+ -+#define TCCR0B _SFR_IO8(0x25) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define WGM02 3 -+#define FOC0B 6 -+#define FOC0A 7 -+ -+#define TCNT0 _SFR_IO8(0x26) -+ -+#define OCR0A _SFR_IO8(0x27) -+ -+#define OCR0B _SFR_IO8(0x28) -+ -+/* Reserved [0x29] */ -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+#define GPIOR10 0 -+#define GPIOR11 1 -+#define GPIOR12 2 -+#define GPIOR13 3 -+#define GPIOR14 4 -+#define GPIOR15 5 -+#define GPIOR16 6 -+#define GPIOR17 7 -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+#define GPIOR20 0 -+#define GPIOR21 1 -+#define GPIOR22 2 -+#define GPIOR23 3 -+#define GPIOR24 4 -+#define GPIOR25 5 -+#define GPIOR26 6 -+#define GPIOR27 7 -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+/* Reserved [0x2F] */ -+ -+#define ACSR _SFR_IO8(0x30) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACBG 6 -+#define ACD 7 -+ -+#define OCDR _SFR_IO8(0x31) -+#define OCDR0 0 -+#define OCDR1 1 -+#define OCDR2 2 -+#define OCDR3 3 -+#define OCDR4 4 -+#define OCDR5 5 -+#define OCDR6 6 -+#define OCDR7 7 -+ -+/* Reserved [0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+#define SM2 3 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define JTRF 4 -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define JTD 7 -+#define IVCE 0 -+#define IVSEL 1 -+#define PUD 4 -+ -+/* Reserved [0x36] */ -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define SIGRD 5 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+/* Reserved [0x38..0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCSR _SFR_MEM8(0x60) -+#define WDE 3 -+#define WDCE 4 -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDP3 5 -+#define WDIE 6 -+#define WDIF 7 -+ -+#define CLKPR _SFR_MEM8(0x61) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+#define CLKPCE 7 -+ -+/* Reserved [0x62] */ -+ -+#define PRR2 _SFR_MEM8(0x63) -+#define PRRAM0 0 -+#define PRRAM1 1 -+#define PRRAM2 2 -+#define PRRAM3 3 -+ -+#define PRR0 _SFR_MEM8(0x64) -+#define PRADC 0 -+#define PRUSART0 1 -+#define PRSPI 2 -+#define PRTIM1 3 -+#define PRPGA 4 -+#define PRTIM0 5 -+#define PRTIM2 6 -+#define PRTWI 7 -+ -+#define PRR1 _SFR_MEM8(0x65) -+#define PRUSART1 0 -+#define PRTIM3 3 -+#define PRTIM4 4 -+#define PRTIM5 5 -+#define PRTRX24 6 -+#define Res 7 -+ -+#define OSCCAL _SFR_MEM8(0x66) -+#define CAL0 0 -+#define CAL1 1 -+#define CAL2 2 -+#define CAL3 3 -+#define CAL4 4 -+#define CAL5 5 -+#define CAL6 6 -+#define CAL7 7 -+#define OSCCAL0 0 -+#define OSCCAL1 1 -+#define OSCCAL2 2 -+#define OSCCAL3 3 -+#define OSCCAL4 4 -+#define OSCCAL5 5 -+#define OSCCAL6 6 -+#define OSCCAL7 7 -+ -+#define BGCR _SFR_MEM8(0x67) -+#define BGCAL0 0 -+#define BGCAL1 1 -+#define BGCAL2 2 -+#define BGCAL_FINE0 3 -+#define BGCAL_FINE1 4 -+#define BGCAL_FINE2 5 -+#define BGCAL_FINE3 6 -+ -+#define PCICR _SFR_MEM8(0x68) -+#define PCIE0 0 -+#define PCIE1 1 -+#define PCIE2 2 -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+#define ISC20 4 -+#define ISC21 5 -+#define ISC30 6 -+#define ISC31 7 -+ -+#define EICRB _SFR_MEM8(0x6A) -+#define ISC40 0 -+#define ISC41 1 -+#define ISC50 2 -+#define ISC51 3 -+#define ISC60 4 -+#define ISC61 5 -+#define ISC70 6 -+#define ISC71 7 -+ -+#define PCMSK0 _SFR_MEM8(0x6B) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6C) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+#define PCINT14 6 -+#define PCINT15 7 -+ -+#define PCMSK2 _SFR_MEM8(0x6D) -+#define PCINT16 0 -+#define PCINT17 1 -+#define PCINT18 2 -+#define PCINT19 3 -+#define PCINT20 4 -+#define PCINT21 5 -+#define PCINT22 6 -+#define PCINT23 7 -+ -+#define TIMSK0 _SFR_MEM8(0x6E) -+#define TOIE0 0 -+#define OCIE0A 1 -+#define OCIE0B 2 -+ -+#define TIMSK1 _SFR_MEM8(0x6F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define OCIE1C 3 -+#define ICIE1 5 -+ -+#define TIMSK2 _SFR_MEM8(0x70) -+#define TOIE2 0 -+#define OCIE2A 1 -+#define OCIE2B 2 -+ -+#define TIMSK3 _SFR_MEM8(0x71) -+#define TOIE3 0 -+#define OCIE3A 1 -+#define OCIE3B 2 -+#define OCIE3C 3 -+#define ICIE3 5 -+ -+#define TIMSK4 _SFR_MEM8(0x72) -+#define TOIE4 0 -+#define OCIE4A 1 -+#define OCIE4B 2 -+#define OCIE4C 3 -+#define ICIE4 5 -+ -+#define TIMSK5 _SFR_MEM8(0x73) -+#define TOIE5 0 -+#define OCIE5A 1 -+#define OCIE5B 2 -+#define OCIE5C 3 -+#define ICIE5 5 -+ -+/* Reserved [0x74] */ -+ -+#define NEMCR _SFR_MEM8(0x75) -+#define AEAM0 4 -+#define AEAM1 5 -+#define ENEAM 6 -+ -+/* Reserved [0x76] */ -+ -+#define ADCSRC _SFR_MEM8(0x77) -+#define ADSUT0 0 -+#define ADSUT1 1 -+#define ADSUT2 2 -+#define ADSUT3 3 -+#define ADSUT4 4 -+#define ADTHT0 6 -+#define ADTHT1 7 -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_MEM16(0x78) -+#endif -+#define ADCW _SFR_MEM16(0x78) -+ -+#define ADCL _SFR_MEM8(0x78) -+#define ADCH _SFR_MEM8(0x79) -+ -+#define ADCSRA _SFR_MEM8(0x7A) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADCSRB _SFR_MEM8(0x7B) -+#define ACME 6 -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+#define MUX5 3 -+#define ACCH 4 -+#define REFOK 5 -+#define AVDDOK 7 -+ -+#define ADMUX _SFR_MEM8(0x7C) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define MUX4 4 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+#define DIDR2 _SFR_MEM8(0x7D) -+#define ADC8D 0 -+#define ADC9D 1 -+#define ADC10D 2 -+#define ADC11D 3 -+#define ADC12D 4 -+#define ADC13D 5 -+#define ADC14D 6 -+#define ADC15D 7 -+ -+#define DIDR0 _SFR_MEM8(0x7E) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+#define ADC6D 6 -+#define ADC7D 7 -+ -+#define DIDR1 _SFR_MEM8(0x7F) -+#define AIN0D 0 -+#define AIN1D 1 -+ -+#define TCCR1A _SFR_MEM8(0x80) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1C0 2 -+#define COM1C1 3 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR1B _SFR_MEM8(0x81) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1C _SFR_MEM8(0x82) -+#define FOC1C 5 -+#define FOC1B 6 -+#define FOC1A 7 -+ -+/* Reserved [0x83] */ -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x84) -+ -+#define TCNT1L _SFR_MEM8(0x84) -+#define TCNT1H _SFR_MEM8(0x85) -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x86) -+ -+#define ICR1L _SFR_MEM8(0x86) -+#define ICR1H _SFR_MEM8(0x87) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_MEM16(0x88) -+ -+#define OCR1AL _SFR_MEM8(0x88) -+#define OCR1AH _SFR_MEM8(0x89) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_MEM16(0x8A) -+ -+#define OCR1BL _SFR_MEM8(0x8A) -+#define OCR1BH _SFR_MEM8(0x8B) -+ -+/* Combine OCR1CL and OCR1CH */ -+#define OCR1C _SFR_MEM16(0x8C) -+ -+#define OCR1CL _SFR_MEM8(0x8C) -+#define OCR1CH _SFR_MEM8(0x8D) -+ -+/* Reserved [0x8E..0x8F] */ -+ -+#define TCCR3A _SFR_MEM8(0x90) -+#define WGM30 0 -+#define WGM31 1 -+#define COM3C0 2 -+#define COM3C1 3 -+#define COM3B0 4 -+#define COM3B1 5 -+#define COM3A0 6 -+#define COM3A1 7 -+ -+#define TCCR3B _SFR_MEM8(0x91) -+#define CS30 0 -+#define CS31 1 -+#define CS32 2 -+#define WGM32 3 -+#define WGM33 4 -+#define ICES3 6 -+#define ICNC3 7 -+ -+#define TCCR3C _SFR_MEM8(0x92) -+#define FOC3C 5 -+#define FOC3B 6 -+#define FOC3A 7 -+ -+/* Reserved [0x93] */ -+ -+/* Combine TCNT3L and TCNT3H */ -+#define TCNT3 _SFR_MEM16(0x94) -+ -+#define TCNT3L _SFR_MEM8(0x94) -+#define TCNT3H _SFR_MEM8(0x95) -+ -+/* Combine ICR3L and ICR3H */ -+#define ICR3 _SFR_MEM16(0x96) -+ -+#define ICR3L _SFR_MEM8(0x96) -+#define ICR3H _SFR_MEM8(0x97) -+ -+/* Combine OCR3AL and OCR3AH */ -+#define OCR3A _SFR_MEM16(0x98) -+ -+#define OCR3AL _SFR_MEM8(0x98) -+#define OCR3AH _SFR_MEM8(0x99) -+ -+/* Combine OCR3BL and OCR3BH */ -+#define OCR3B _SFR_MEM16(0x9A) -+ -+#define OCR3BL _SFR_MEM8(0x9A) -+#define OCR3BH _SFR_MEM8(0x9B) -+ -+/* Combine OCR3CL and OCR3CH */ -+#define OCR3C _SFR_MEM16(0x9C) -+ -+#define OCR3CL _SFR_MEM8(0x9C) -+#define OCR3CH _SFR_MEM8(0x9D) -+ -+/* Reserved [0x9E..0x9F] */ -+ -+#define TCCR4A _SFR_MEM8(0xA0) -+#define WGM40 0 -+#define WGM41 1 -+#define COM4C0 2 -+#define COM4C1 3 -+#define COM4B0 4 -+#define COM4B1 5 -+#define COM4A0 6 -+#define COM4A1 7 -+ -+#define TCCR4B _SFR_MEM8(0xA1) -+#define CS40 0 -+#define CS41 1 -+#define CS42 2 -+#define WGM42 3 -+#define WGM43 4 -+#define ICES4 6 -+#define ICNC4 7 -+ -+#define TCCR4C _SFR_MEM8(0xA2) -+#define FOC4C 5 -+#define FOC4B 6 -+#define FOC4A 7 -+ -+/* Reserved [0xA3] */ -+ -+/* Combine TCNT4L and TCNT4H */ -+#define TCNT4 _SFR_MEM16(0xA4) -+ -+#define TCNT4L _SFR_MEM8(0xA4) -+#define TCNT4H _SFR_MEM8(0xA5) -+ -+/* Combine ICR4L and ICR4H */ -+#define ICR4 _SFR_MEM16(0xA6) -+ -+#define ICR4L _SFR_MEM8(0xA6) -+#define ICR4H _SFR_MEM8(0xA7) -+ -+/* Combine OCR4AL and OCR4AH */ -+#define OCR4A _SFR_MEM16(0xA8) -+ -+#define OCR4AL _SFR_MEM8(0xA8) -+#define OCR4AH _SFR_MEM8(0xA9) -+ -+/* Combine OCR4BL and OCR4BH */ -+#define OCR4B _SFR_MEM16(0xAA) -+ -+#define OCR4BL _SFR_MEM8(0xAA) -+#define OCR4BH _SFR_MEM8(0xAB) -+ -+/* Combine OCR4CL and OCR4CH */ -+#define OCR4C _SFR_MEM16(0xAC) -+ -+#define OCR4CL _SFR_MEM8(0xAC) -+#define OCR4CH _SFR_MEM8(0xAD) -+ -+/* Reserved [0xAE..0xAF] */ -+ -+#define TCCR2A _SFR_MEM8(0xB0) -+#define WGM20 0 -+#define WGM21 1 -+#define COM2B0 4 -+#define COM2B1 5 -+#define COM2A0 6 -+#define COM2A1 7 -+ -+#define TCCR2B _SFR_MEM8(0xB1) -+#define CS20 0 -+#define CS21 1 -+#define CS22 2 -+#define WGM22 3 -+#define FOC2B 6 -+#define FOC2A 7 -+ -+#define TCNT2 _SFR_MEM8(0xB2) -+ -+#define OCR2A _SFR_MEM8(0xB3) -+ -+#define OCR2B _SFR_MEM8(0xB4) -+ -+/* Reserved [0xB5] */ -+ -+#define ASSR _SFR_MEM8(0xB6) -+#define TCR2BUB 0 -+#define TCR2AUB 1 -+#define OCR2BUB 2 -+#define OCR2AUB 3 -+#define TCN2UB 4 -+#define AS2 5 -+#define EXCLK 6 -+#define EXCLKAMR 7 -+ -+/* Reserved [0xB7] */ -+ -+#define TWBR _SFR_MEM8(0xB8) -+ -+#define TWSR _SFR_MEM8(0xB9) -+#define TWPS0 0 -+#define TWPS1 1 -+#define TWS3 3 -+#define TWS4 4 -+#define TWS5 5 -+#define TWS6 6 -+#define TWS7 7 -+ -+#define TWAR _SFR_MEM8(0xBA) -+#define TWGCE 0 -+#define TWA0 1 -+#define TWA1 2 -+#define TWA2 3 -+#define TWA3 4 -+#define TWA4 5 -+#define TWA5 6 -+#define TWA6 7 -+ -+#define TWDR _SFR_MEM8(0xBB) -+ -+#define TWCR _SFR_MEM8(0xBC) -+#define TWIE 0 -+#define TWEN 2 -+#define TWWC 3 -+#define TWSTO 4 -+#define TWSTA 5 -+#define TWEA 6 -+#define TWINT 7 -+ -+#define TWAMR _SFR_MEM8(0xBD) -+#define TWAM0 1 -+#define TWAM1 2 -+#define TWAM2 3 -+#define TWAM3 4 -+#define TWAM4 5 -+#define TWAM5 6 -+#define TWAM6 7 -+ -+#define IRQ_MASK1 _SFR_MEM8(0xBE) -+#define TX_START_EN 0 -+#define MAF_0_AMI_EN 1 -+#define MAF_1_AMI_EN 2 -+#define MAF_2_AMI_EN 3 -+#define MAF_3_AMI_EN 4 -+ -+#define IRQ_STATUS1 _SFR_MEM8(0xBF) -+#define TX_START 0 -+#define MAF_0_AMI 1 -+#define MAF_1_AMI 2 -+#define MAF_2_AMI 3 -+#define MAF_3_AMI 4 -+ -+#define UCSR0A _SFR_MEM8(0xC0) -+#define MPCM0 0 -+#define U2X0 1 -+#define UPE0 2 -+#define DOR0 3 -+#define FE0 4 -+#define UDRE0 5 -+#define TXC0 6 -+#define RXC0 7 -+ -+#define UCSR0B _SFR_MEM8(0xC1) -+#define TXB80 0 -+#define RXB80 1 -+#define UCSZ02 2 -+#define TXEN0 3 -+#define RXEN0 4 -+#define UDRIE0 5 -+#define TXCIE0 6 -+#define RXCIE0 7 -+ -+#define UCSR0C _SFR_MEM8(0xC2) -+#define UCPOL0 0 -+#define UCSZ00 1 -+#define UCSZ01 2 -+#define USBS0 3 -+#define UPM00 4 -+#define UPM01 5 -+#define UMSEL00 6 -+#define UMSEL01 7 -+#define UCPHA0 1 -+#define UDORD0 2 -+ -+/* Reserved [0xC3] */ -+ -+/* Combine UBRR0L and UBRR0H */ -+#define UBRR0 _SFR_MEM16(0xC4) -+ -+#define UBRR0L _SFR_MEM8(0xC4) -+#define UBRR0H _SFR_MEM8(0xC5) -+ -+#define UDR0 _SFR_MEM8(0xC6) -+ -+/* Reserved [0xC7] */ -+ -+#define UCSR1A _SFR_MEM8(0xC8) -+#define MPCM1 0 -+#define U2X1 1 -+#define UPE1 2 -+#define DOR1 3 -+#define FE1 4 -+#define UDRE1 5 -+#define TXC1 6 -+#define RXC1 7 -+ -+#define UCSR1B _SFR_MEM8(0xC9) -+#define TXB81 0 -+#define RXB81 1 -+#define UCSZ12 2 -+#define TXEN1 3 -+#define RXEN1 4 -+#define UDRIE1 5 -+#define TXCIE1 6 -+#define RXCIE1 7 -+ -+#define UCSR1C _SFR_MEM8(0xCA) -+#define UCPOL1 0 -+#define UCSZ10 1 -+#define UCSZ11 2 -+#define USBS1 3 -+#define UPM10 4 -+#define UPM11 5 -+#define UMSEL10 6 -+#define UMSEL11 7 -+#define UCPHA1 1 -+#define UDORD1 2 -+ -+/* Reserved [0xCB] */ -+ -+/* Combine UBRR1L and UBRR1H */ -+#define UBRR1 _SFR_MEM16(0xCC) -+ -+#define UBRR1L _SFR_MEM8(0xCC) -+#define UBRR1H _SFR_MEM8(0xCD) -+ -+#define UDR1 _SFR_MEM8(0xCE) -+ -+/* Reserved [0xCF..0xD6] */ -+ -+#define SCRSTRLL _SFR_MEM8(0xD7) -+#define SCRSTRLL0 0 -+#define SCRSTRLL1 1 -+#define SCRSTRLL2 2 -+#define SCRSTRLL3 3 -+#define SCRSTRLL4 4 -+#define SCRSTRLL5 5 -+#define SCRSTRLL6 6 -+#define SCRSTRLL7 7 -+ -+#define SCRSTRLH _SFR_MEM8(0xD8) -+#define SCRSTRLH0 0 -+#define SCRSTRLH1 1 -+#define SCRSTRLH2 2 -+#define SCRSTRLH3 3 -+#define SCRSTRLH4 4 -+#define SCRSTRLH5 5 -+#define SCRSTRLH6 6 -+#define SCRSTRLH7 7 -+ -+#define SCRSTRHL _SFR_MEM8(0xD9) -+#define SCRSTRHL0 0 -+#define SCRSTRHL1 1 -+#define SCRSTRHL2 2 -+#define SCRSTRHL3 3 -+#define SCRSTRHL4 4 -+#define SCRSTRHL5 5 -+#define SCRSTRHL6 6 -+#define SCRSTRHL7 7 -+ -+#define SCRSTRHH _SFR_MEM8(0xDA) -+#define SCRSTRHH0 0 -+#define SCRSTRHH1 1 -+#define SCRSTRHH2 2 -+#define SCRSTRHH3 3 -+#define SCRSTRHH4 4 -+#define SCRSTRHH5 5 -+#define SCRSTRHH6 6 -+#define SCRSTRHH7 7 -+ -+#define SCCSR _SFR_MEM8(0xDB) -+#define SCCS10 0 -+#define SCCS11 1 -+#define SCCS20 2 -+#define SCCS21 3 -+#define SCCS30 4 -+#define SCCS31 5 -+ -+#define SCCR0 _SFR_MEM8(0xDC) -+#define SCCMP1 0 -+#define SCCMP2 1 -+#define SCCMP3 2 -+#define SCTSE 3 -+#define SCCKSEL 4 -+#define SCEN 5 -+#define SCMBTS 6 -+#define SCRES 7 -+ -+#define SCCR1 _SFR_MEM8(0xDD) -+#define SCENBO 0 -+#define SCEECLK 1 -+#define SCCKDIV0 2 -+#define SCCKDIV1 3 -+#define SCCKDIV2 4 -+#define SCBTSM 5 -+#define Res5 6 -+#define Res6 7 -+ -+#define SCSR _SFR_MEM8(0xDE) -+#define SCBSY 0 -+ -+#define SCIRQM _SFR_MEM8(0xDF) -+#define IRQMCP1 0 -+#define IRQMCP2 1 -+#define IRQMCP3 2 -+#define IRQMOF 3 -+#define IRQMBO 4 -+ -+#define SCIRQS _SFR_MEM8(0xE0) -+#define IRQSCP1 0 -+#define IRQSCP2 1 -+#define IRQSCP3 2 -+#define IRQSOF 3 -+#define IRQSBO 4 -+ -+#define SCCNTLL _SFR_MEM8(0xE1) -+#define SCCNTLL0 0 -+#define SCCNTLL1 1 -+#define SCCNTLL2 2 -+#define SCCNTLL3 3 -+#define SCCNTLL4 4 -+#define SCCNTLL5 5 -+#define SCCNTLL6 6 -+#define SCCNTLL7 7 -+ -+#define SCCNTLH _SFR_MEM8(0xE2) -+#define SCCNTLH0 0 -+#define SCCNTLH1 1 -+#define SCCNTLH2 2 -+#define SCCNTLH3 3 -+#define SCCNTLH4 4 -+#define SCCNTLH5 5 -+#define SCCNTLH6 6 -+#define SCCNTLH7 7 -+ -+#define SCCNTHL _SFR_MEM8(0xE3) -+#define SCCNTHL0 0 -+#define SCCNTHL1 1 -+#define SCCNTHL2 2 -+#define SCCNTHL3 3 -+#define SCCNTHL4 4 -+#define SCCNTHL5 5 -+#define SCCNTHL6 6 -+#define SCCNTHL7 7 -+ -+#define SCCNTHH _SFR_MEM8(0xE4) -+#define SCCNTHH0 0 -+#define SCCNTHH1 1 -+#define SCCNTHH2 2 -+#define SCCNTHH3 3 -+#define SCCNTHH4 4 -+#define SCCNTHH5 5 -+#define SCCNTHH6 6 -+#define SCCNTHH7 7 -+ -+#define SCBTSRLL _SFR_MEM8(0xE5) -+#define SCBTSRLL0 0 -+#define SCBTSRLL1 1 -+#define SCBTSRLL2 2 -+#define SCBTSRLL3 3 -+#define SCBTSRLL4 4 -+#define SCBTSRLL5 5 -+#define SCBTSRLL6 6 -+#define SCBTSRLL7 7 -+ -+#define SCBTSRLH _SFR_MEM8(0xE6) -+#define SCBTSRLH0 0 -+#define SCBTSRLH1 1 -+#define SCBTSRLH2 2 -+#define SCBTSRLH3 3 -+#define SCBTSRLH4 4 -+#define SCBTSRLH5 5 -+#define SCBTSRLH6 6 -+#define SCBTSRLH7 7 -+ -+#define SCBTSRHL _SFR_MEM8(0xE7) -+#define SCBTSRHL0 0 -+#define SCBTSRHL1 1 -+#define SCBTSRHL2 2 -+#define SCBTSRHL3 3 -+#define SCBTSRHL4 4 -+#define SCBTSRHL5 5 -+#define SCBTSRHL6 6 -+#define SCBTSRHL7 7 -+ -+#define SCBTSRHH _SFR_MEM8(0xE8) -+#define SCBTSRHH0 0 -+#define SCBTSRHH1 1 -+#define SCBTSRHH2 2 -+#define SCBTSRHH3 3 -+#define SCBTSRHH4 4 -+#define SCBTSRHH5 5 -+#define SCBTSRHH6 6 -+#define SCBTSRHH7 7 -+ -+#define SCTSRLL _SFR_MEM8(0xE9) -+#define SCTSRLL0 0 -+#define SCTSRLL1 1 -+#define SCTSRLL2 2 -+#define SCTSRLL3 3 -+#define SCTSRLL4 4 -+#define SCTSRLL5 5 -+#define SCTSRLL6 6 -+#define SCTSRLL7 7 -+ -+#define SCTSRLH _SFR_MEM8(0xEA) -+#define SCTSRLH0 0 -+#define SCTSRLH1 1 -+#define SCTSRLH2 2 -+#define SCTSRLH3 3 -+#define SCTSRLH4 4 -+#define SCTSRLH5 5 -+#define SCTSRLH6 6 -+#define SCTSRLH7 7 -+ -+#define SCTSRHL _SFR_MEM8(0xEB) -+#define SCTSRHL0 0 -+#define SCTSRHL1 1 -+#define SCTSRHL2 2 -+#define SCTSRHL3 3 -+#define SCTSRHL4 4 -+#define SCTSRHL5 5 -+#define SCTSRHL6 6 -+#define SCTSRHL7 7 -+ -+#define SCTSRHH _SFR_MEM8(0xEC) -+#define SCTSRHH0 0 -+#define SCTSRHH1 1 -+#define SCTSRHH2 2 -+#define SCTSRHH3 3 -+#define SCTSRHH4 4 -+#define SCTSRHH5 5 -+#define SCTSRHH6 6 -+#define SCTSRHH7 7 -+ -+#define SCOCR3LL _SFR_MEM8(0xED) -+#define SCOCR3LL0 0 -+#define SCOCR3LL1 1 -+#define SCOCR3LL2 2 -+#define SCOCR3LL3 3 -+#define SCOCR3LL4 4 -+#define SCOCR3LL5 5 -+#define SCOCR3LL6 6 -+#define SCOCR3LL7 7 -+ -+#define SCOCR3LH _SFR_MEM8(0xEE) -+#define SCOCR3LH0 0 -+#define SCOCR3LH1 1 -+#define SCOCR3LH2 2 -+#define SCOCR3LH3 3 -+#define SCOCR3LH4 4 -+#define SCOCR3LH5 5 -+#define SCOCR3LH6 6 -+#define SCOCR3LH7 7 -+ -+#define SCOCR3HL _SFR_MEM8(0xEF) -+#define SCOCR3HL0 0 -+#define SCOCR3HL1 1 -+#define SCOCR3HL2 2 -+#define SCOCR3HL3 3 -+#define SCOCR3HL4 4 -+#define SCOCR3HL5 5 -+#define SCOCR3HL6 6 -+#define SCOCR3HL7 7 -+ -+#define SCOCR3HH _SFR_MEM8(0xF0) -+#define SCOCR3HH0 0 -+#define SCOCR3HH1 1 -+#define SCOCR3HH2 2 -+#define SCOCR3HH3 3 -+#define SCOCR3HH4 4 -+#define SCOCR3HH5 5 -+#define SCOCR3HH6 6 -+#define SCOCR3HH7 7 -+ -+#define SCOCR2LL _SFR_MEM8(0xF1) -+#define SCOCR2LL0 0 -+#define SCOCR2LL1 1 -+#define SCOCR2LL2 2 -+#define SCOCR2LL3 3 -+#define SCOCR2LL4 4 -+#define SCOCR2LL5 5 -+#define SCOCR2LL6 6 -+#define SCOCR2LL7 7 -+ -+#define SCOCR2LH _SFR_MEM8(0xF2) -+#define SCOCR2LH0 0 -+#define SCOCR2LH1 1 -+#define SCOCR2LH2 2 -+#define SCOCR2LH3 3 -+#define SCOCR2LH4 4 -+#define SCOCR2LH5 5 -+#define SCOCR2LH6 6 -+#define SCOCR2LH7 7 -+ -+#define SCOCR2HL _SFR_MEM8(0xF3) -+#define SCOCR2HL0 0 -+#define SCOCR2HL1 1 -+#define SCOCR2HL2 2 -+#define SCOCR2HL3 3 -+#define SCOCR2HL4 4 -+#define SCOCR2HL5 5 -+#define SCOCR2HL6 6 -+#define SCOCR2HL7 7 -+ -+#define SCOCR2HH _SFR_MEM8(0xF4) -+#define SCOCR2HH0 0 -+#define SCOCR2HH1 1 -+#define SCOCR2HH2 2 -+#define SCOCR2HH3 3 -+#define SCOCR2HH4 4 -+#define SCOCR2HH5 5 -+#define SCOCR2HH6 6 -+#define SCOCR2HH7 7 -+ -+#define SCOCR1LL _SFR_MEM8(0xF5) -+#define SCOCR1LL0 0 -+#define SCOCR1LL1 1 -+#define SCOCR1LL2 2 -+#define SCOCR1LL3 3 -+#define SCOCR1LL4 4 -+#define SCOCR1LL5 5 -+#define SCOCR1LL6 6 -+#define SCOCR1LL7 7 -+ -+#define SCOCR1LH _SFR_MEM8(0xF6) -+#define SCOCR1LH0 0 -+#define SCOCR1LH1 1 -+#define SCOCR1LH2 2 -+#define SCOCR1LH3 3 -+#define SCOCR1LH4 4 -+#define SCOCR1LH5 5 -+#define SCOCR1LH6 6 -+#define SCOCR1LH7 7 -+ -+#define SCOCR1HL _SFR_MEM8(0xF7) -+#define SCOCR1HL0 0 -+#define SCOCR1HL1 1 -+#define SCOCR1HL2 2 -+#define SCOCR1HL3 3 -+#define SCOCR1HL4 4 -+#define SCOCR1HL5 5 -+#define SCOCR1HL6 6 -+#define SCOCR1HL7 7 -+ -+#define SCOCR1HH _SFR_MEM8(0xF8) -+#define SCOCR1HH0 0 -+#define SCOCR1HH1 1 -+#define SCOCR1HH2 2 -+#define SCOCR1HH3 3 -+#define SCOCR1HH4 4 -+#define SCOCR1HH5 5 -+#define SCOCR1HH6 6 -+#define SCOCR1HH7 7 -+ -+#define SCTSTRLL _SFR_MEM8(0xF9) -+#define SCTSTRLL0 0 -+#define SCTSTRLL1 1 -+#define SCTSTRLL2 2 -+#define SCTSTRLL3 3 -+#define SCTSTRLL4 4 -+#define SCTSTRLL5 5 -+#define SCTSTRLL6 6 -+#define SCTSTRLL7 7 -+ -+#define SCTSTRLH _SFR_MEM8(0xFA) -+#define SCTSTRLH0 0 -+#define SCTSTRLH1 1 -+#define SCTSTRLH2 2 -+#define SCTSTRLH3 3 -+#define SCTSTRLH4 4 -+#define SCTSTRLH5 5 -+#define SCTSTRLH6 6 -+#define SCTSTRLH7 7 -+ -+#define SCTSTRHL _SFR_MEM8(0xFB) -+#define SCTSTRHL0 0 -+#define SCTSTRHL1 1 -+#define SCTSTRHL2 2 -+#define SCTSTRHL3 3 -+#define SCTSTRHL4 4 -+#define SCTSTRHL5 5 -+#define SCTSTRHL6 6 -+#define SCTSTRHL7 7 -+ -+#define SCTSTRHH _SFR_MEM8(0xFC) -+#define SCTSTRHH0 0 -+#define SCTSTRHH1 1 -+#define SCTSTRHH2 2 -+#define SCTSTRHH3 3 -+#define SCTSTRHH4 4 -+#define SCTSTRHH5 5 -+#define SCTSTRHH6 6 -+#define SCTSTRHH7 7 -+ -+/* Reserved [0xFD..0x10B] */ -+ -+#define MAFCR0 _SFR_MEM8(0x10C) -+#define MAF0EN 0 -+#define MAF1EN 1 -+#define MAF2EN 2 -+#define MAF3EN 3 -+ -+#define MAFCR1 _SFR_MEM8(0x10D) -+#define AACK_0_I_AM_COORD 0 -+#define AACK_0_SET_PD 1 -+#define AACK_1_I_AM_COORD 2 -+#define AACK_1_SET_PD 3 -+#define AACK_2_I_AM_COORD 4 -+#define AACK_2_SET_PD 5 -+#define AACK_3_I_AM_COORD 6 -+#define AACK_3_SET_PD 7 -+ -+#define MAFSA0L _SFR_MEM8(0x10E) -+#define MAFSA0L0 0 -+#define MAFSA0L1 1 -+#define MAFSA0L2 2 -+#define MAFSA0L3 3 -+#define MAFSA0L4 4 -+#define MAFSA0L5 5 -+#define MAFSA0L6 6 -+#define MAFSA0L7 7 -+ -+#define MAFSA0H _SFR_MEM8(0x10F) -+#define MAFSA0H0 0 -+#define MAFSA0H1 1 -+#define MAFSA0H2 2 -+#define MAFSA0H3 3 -+#define MAFSA0H4 4 -+#define MAFSA0H5 5 -+#define MAFSA0H6 6 -+#define MAFSA0H7 7 -+ -+#define MAFPA0L _SFR_MEM8(0x110) -+#define MAFPA0L0 0 -+#define MAFPA0L1 1 -+#define MAFPA0L2 2 -+#define MAFPA0L3 3 -+#define MAFPA0L4 4 -+#define MAFPA0L5 5 -+#define MAFPA0L6 6 -+#define MAFPA0L7 7 -+ -+#define MAFPA0H _SFR_MEM8(0x111) -+#define MAFPA0H0 0 -+#define MAFPA0H1 1 -+#define MAFPA0H2 2 -+#define MAFPA0H3 3 -+#define MAFPA0H4 4 -+#define MAFPA0H5 5 -+#define MAFPA0H6 6 -+#define MAFPA0H7 7 -+ -+#define MAFSA1L _SFR_MEM8(0x112) -+#define MAFSA1L0 0 -+#define MAFSA1L1 1 -+#define MAFSA1L2 2 -+#define MAFSA1L3 3 -+#define MAFSA1L4 4 -+#define MAFSA1L5 5 -+#define MAFSA1L6 6 -+#define MAFSA1L7 7 -+ -+#define MAFSA1H _SFR_MEM8(0x113) -+#define MAFSA1H0 0 -+#define MAFSA1H1 1 -+#define MAFSA1H2 2 -+#define MAFSA1H3 3 -+#define MAFSA1H4 4 -+#define MAFSA1H5 5 -+#define MAFSA1H6 6 -+#define MAFSA1H7 7 -+ -+#define MAFPA1L _SFR_MEM8(0x114) -+#define MAFPA1L0 0 -+#define MAFPA1L1 1 -+#define MAFPA1L2 2 -+#define MAFPA1L3 3 -+#define MAFPA1L4 4 -+#define MAFPA1L5 5 -+#define MAFPA1L6 6 -+#define MAFPA1L7 7 -+ -+#define MAFPA1H _SFR_MEM8(0x115) -+#define MAFPA1H0 0 -+#define MAFPA1H1 1 -+#define MAFPA1H2 2 -+#define MAFPA1H3 3 -+#define MAFPA1H4 4 -+#define MAFPA1H5 5 -+#define MAFPA1H6 6 -+#define MAFPA1H7 7 -+ -+#define MAFSA2L _SFR_MEM8(0x116) -+#define MAFSA2L0 0 -+#define MAFSA2L1 1 -+#define MAFSA2L2 2 -+#define MAFSA2L3 3 -+#define MAFSA2L4 4 -+#define MAFSA2L5 5 -+#define MAFSA2L6 6 -+#define MAFSA2L7 7 -+ -+#define MAFSA2H _SFR_MEM8(0x117) -+#define MAFSA2H0 0 -+#define MAFSA2H1 1 -+#define MAFSA2H2 2 -+#define MAFSA2H3 3 -+#define MAFSA2H4 4 -+#define MAFSA2H5 5 -+#define MAFSA2H6 6 -+#define MAFSA2H7 7 -+ -+#define MAFPA2L _SFR_MEM8(0x118) -+#define MAFPA2L0 0 -+#define MAFPA2L1 1 -+#define MAFPA2L2 2 -+#define MAFPA2L3 3 -+#define MAFPA2L4 4 -+#define MAFPA2L5 5 -+#define MAFPA2L6 6 -+#define MAFPA2L7 7 -+ -+#define MAFPA2H _SFR_MEM8(0x119) -+#define MAFPA2H0 0 -+#define MAFPA2H1 1 -+#define MAFPA2H2 2 -+#define MAFPA2H3 3 -+#define MAFPA2H4 4 -+#define MAFPA2H5 5 -+#define MAFPA2H6 6 -+#define MAFPA2H7 7 -+ -+#define MAFSA3L _SFR_MEM8(0x11A) -+#define MAFSA3L0 0 -+#define MAFSA3L1 1 -+#define MAFSA3L2 2 -+#define MAFSA3L3 3 -+#define MAFSA3L4 4 -+#define MAFSA3L5 5 -+#define MAFSA3L6 6 -+#define MAFSA3L7 7 -+ -+#define MAFSA3H _SFR_MEM8(0x11B) -+#define MAFSA3H0 0 -+#define MAFSA3H1 1 -+#define MAFSA3H2 2 -+#define MAFSA3H3 3 -+#define MAFSA3H4 4 -+#define MAFSA3H5 5 -+#define MAFSA3H6 6 -+#define MAFSA3H7 7 -+ -+#define MAFPA3L _SFR_MEM8(0x11C) -+#define MAFPA3L0 0 -+#define MAFPA3L1 1 -+#define MAFPA3L2 2 -+#define MAFPA3L3 3 -+#define MAFPA3L4 4 -+#define MAFPA3L5 5 -+#define MAFPA3L6 6 -+#define MAFPA3L7 7 -+ -+#define MAFPA3H _SFR_MEM8(0x11D) -+#define MAFPA3H0 0 -+#define MAFPA3H1 1 -+#define MAFPA3H2 2 -+#define MAFPA3H3 3 -+#define MAFPA3H4 4 -+#define MAFPA3H5 5 -+#define MAFPA3H6 6 -+#define MAFPA3H7 7 -+ -+/* Reserved [0x11E..0x11F] */ -+ -+#define TCCR5A _SFR_MEM8(0x120) -+#define WGM50 0 -+#define WGM51 1 -+#define COM5C0 2 -+#define COM5C1 3 -+#define COM5B0 4 -+#define COM5B1 5 -+#define COM5A0 6 -+#define COM5A1 7 -+ -+#define TCCR5B _SFR_MEM8(0x121) -+#define CS50 0 -+#define CS51 1 -+#define CS52 2 -+#define WGM52 3 -+#define WGM53 4 -+#define ICES5 6 -+#define ICNC5 7 -+ -+#define TCCR5C _SFR_MEM8(0x122) -+#define FOC5C 5 -+#define FOC5B 6 -+#define FOC5A 7 -+ -+/* Reserved [0x123] */ -+ -+/* Combine TCNT5L and TCNT5H */ -+#define TCNT5 _SFR_MEM16(0x124) -+ -+#define TCNT5L _SFR_MEM8(0x124) -+#define TCNT5H _SFR_MEM8(0x125) -+ -+/* Combine ICR5L and ICR5H */ -+#define ICR5 _SFR_MEM16(0x126) -+ -+#define ICR5L _SFR_MEM8(0x126) -+#define ICR5H _SFR_MEM8(0x127) -+ -+/* Combine OCR5AL and OCR5AH */ -+#define OCR5A _SFR_MEM16(0x128) -+ -+#define OCR5AL _SFR_MEM8(0x128) -+#define OCR5AH _SFR_MEM8(0x129) -+ -+/* Combine OCR5BL and OCR5BH */ -+#define OCR5B _SFR_MEM16(0x12A) -+ -+#define OCR5BL _SFR_MEM8(0x12A) -+#define OCR5BH _SFR_MEM8(0x12B) -+ -+/* Combine OCR5CL and OCR5CH */ -+#define OCR5C _SFR_MEM16(0x12C) -+ -+#define OCR5CL _SFR_MEM8(0x12C) -+#define OCR5CH _SFR_MEM8(0x12D) -+ -+/* Reserved [0x12E] */ -+ -+#define LLCR _SFR_MEM8(0x12F) -+#define LLENCAL 0 -+#define LLSHORT 1 -+#define LLTCO 2 -+#define LLCAL 3 -+#define LLCOMP 4 -+#define LLDONE 5 -+ -+#define LLDRL _SFR_MEM8(0x130) -+#define LLDRL0 0 -+#define LLDRL1 1 -+#define LLDRL2 2 -+#define LLDRL3 3 -+ -+#define LLDRH _SFR_MEM8(0x131) -+#define LLDRH0 0 -+#define LLDRH1 1 -+#define LLDRH2 2 -+#define LLDRH3 3 -+#define LLDRH4 4 -+ -+#define DRTRAM3 _SFR_MEM8(0x132) -+#define ENDRT 4 -+#define DRTSWOK 5 -+ -+#define DRTRAM2 _SFR_MEM8(0x133) -+ -+#define DRTRAM1 _SFR_MEM8(0x134) -+ -+#define DRTRAM0 _SFR_MEM8(0x135) -+ -+#define DPDS0 _SFR_MEM8(0x136) -+#define PBDRV0 0 -+#define PBDRV1 1 -+#define PDDRV0 2 -+#define PDDRV1 3 -+#define PEDRV0 4 -+#define PEDRV1 5 -+#define PFDRV0 6 -+#define PFDRV1 7 -+ -+#define DPDS1 _SFR_MEM8(0x137) -+#define PGDRV0 0 -+#define PGDRV1 1 -+ -+#define PARCR _SFR_MEM8(0x138) -+#define PARUFI 0 -+#define PARDFI 1 -+#define PALTU0 2 -+#define PALTU1 3 -+#define PALTU2 4 -+#define PALTD0 5 -+#define PALTD1 6 -+#define PALTD2 7 -+ -+#define TRXPR _SFR_MEM8(0x139) -+#define TRXRST 0 -+#define SLPTR 1 -+ -+/* Reserved [0x13A..0x13B] */ -+ -+#define AES_CTRL _SFR_MEM8(0x13C) -+#define AES_IM 2 -+#define AES_DIR 3 -+#define AES_MODE 5 -+#define AES_REQUEST 7 -+ -+#define AES_STATUS _SFR_MEM8(0x13D) -+#define AES_DONE 0 -+#define AES_ER 7 -+ -+#define AES_STATE _SFR_MEM8(0x13E) -+#define AES_STATE0 0 -+#define AES_STATE1 1 -+#define AES_STATE2 2 -+#define AES_STATE3 3 -+#define AES_STATE4 4 -+#define AES_STATE5 5 -+#define AES_STATE6 6 -+#define AES_STATE7 7 -+ -+#define AES_KEY _SFR_MEM8(0x13F) -+#define AES_KEY0 0 -+#define AES_KEY1 1 -+#define AES_KEY2 2 -+#define AES_KEY3 3 -+#define AES_KEY4 4 -+#define AES_KEY5 5 -+#define AES_KEY6 6 -+#define AES_KEY7 7 -+ -+/* Reserved [0x140] */ -+ -+#define TRX_STATUS _SFR_MEM8(0x141) -+#define TRX_STATUS0 0 -+#define TRX_STATUS1 1 -+#define TRX_STATUS2 2 -+#define TRX_STATUS3 3 -+#define TRX_STATUS4 4 -+#define TST_STATUS 5 -+#define CCA_STATUS 6 -+#define CCA_DONE 7 -+ -+#define TRX_STATE _SFR_MEM8(0x142) -+#define TRX_CMD0 0 -+#define TRX_CMD1 1 -+#define TRX_CMD2 2 -+#define TRX_CMD3 3 -+#define TRX_CMD4 4 -+#define TRAC_STATUS0 5 -+#define TRAC_STATUS1 6 -+#define TRAC_STATUS2 7 -+ -+#define TRX_CTRL_0 _SFR_MEM8(0x143) -+#define PMU_IF_INV 4 -+#define PMU_START 5 -+#define PMU_EN 6 -+#define Res7 7 -+ -+#define TRX_CTRL_1 _SFR_MEM8(0x144) -+#define PLL_TX_FLT 4 -+#define TX_AUTO_CRC_ON 5 -+#define IRQ_2_EXT_EN 6 -+#define PA_EXT_EN 7 -+ -+#define PHY_TX_PWR _SFR_MEM8(0x145) -+#define TX_PWR0 0 -+#define TX_PWR1 1 -+#define TX_PWR2 2 -+#define TX_PWR3 3 -+ -+#define PHY_RSSI _SFR_MEM8(0x146) -+#define RSSI0 0 -+#define RSSI1 1 -+#define RSSI2 2 -+#define RSSI3 3 -+#define RSSI4 4 -+#define RND_VALUE0 5 -+#define RND_VALUE1 6 -+#define RX_CRC_VALID 7 -+ -+#define PHY_ED_LEVEL _SFR_MEM8(0x147) -+#define ED_LEVEL0 0 -+#define ED_LEVEL1 1 -+#define ED_LEVEL2 2 -+#define ED_LEVEL3 3 -+#define ED_LEVEL4 4 -+#define ED_LEVEL5 5 -+#define ED_LEVEL6 6 -+#define ED_LEVEL7 7 -+ -+#define PHY_CC_CCA _SFR_MEM8(0x148) -+#define CHANNEL0 0 -+#define CHANNEL1 1 -+#define CHANNEL2 2 -+#define CHANNEL3 3 -+#define CHANNEL4 4 -+#define CCA_MODE0 5 -+#define CCA_MODE1 6 -+#define CCA_REQUEST 7 -+ -+#define CCA_THRES _SFR_MEM8(0x149) -+#define CCA_ED_THRES0 0 -+#define CCA_ED_THRES1 1 -+#define CCA_ED_THRES2 2 -+#define CCA_ED_THRES3 3 -+#define CCA_CS_THRES0 4 -+#define CCA_CS_THRES1 5 -+#define CCA_CS_THRES2 6 -+#define CCA_CS_THRES3 7 -+ -+#define RX_CTRL _SFR_MEM8(0x14A) -+#define PDT_THRES0 0 -+#define PDT_THRES1 1 -+#define PDT_THRES2 2 -+#define PDT_THRES3 3 -+ -+#define SFD_VALUE _SFR_MEM8(0x14B) -+#define SFD_VALUE0 0 -+#define SFD_VALUE1 1 -+#define SFD_VALUE2 2 -+#define SFD_VALUE3 3 -+#define SFD_VALUE4 4 -+#define SFD_VALUE5 5 -+#define SFD_VALUE6 6 -+#define SFD_VALUE7 7 -+ -+#define TRX_CTRL_2 _SFR_MEM8(0x14C) -+#define OQPSK_DATA_RATE0 0 -+#define OQPSK_DATA_RATE1 1 -+#define RX_SAFE_MODE 7 -+ -+#define ANT_DIV _SFR_MEM8(0x14D) -+#define ANT_CTRL0 0 -+#define ANT_CTRL1 1 -+#define ANT_EXT_SW_EN 2 -+#define ANT_DIV_EN 3 -+#define ANT_SEL 7 -+ -+#define IRQ_MASK _SFR_MEM8(0x14E) -+#define PLL_LOCK_EN 0 -+#define PLL_UNLOCK_EN 1 -+#define RX_START_EN 2 -+#define RX_END_EN 3 -+#define CCA_ED_DONE_EN 4 -+#define AMI_EN 5 -+#define TX_END_EN 6 -+#define AWAKE_EN 7 -+ -+#define IRQ_STATUS _SFR_MEM8(0x14F) -+#define PLL_LOCK 0 -+#define PLL_UNLOCK 1 -+#define RX_START 2 -+#define RX_END 3 -+#define CCA_ED_DONE 4 -+#define AMI 5 -+#define TX_END 6 -+#define AWAKE 7 -+ -+#define VREG_CTRL _SFR_MEM8(0x150) -+#define DVDD_OK 2 -+#define DVREG_EXT 3 -+#define AVDD_OK 6 -+#define AVREG_EXT 7 -+ -+#define BATMON _SFR_MEM8(0x151) -+#define BATMON_VTH0 0 -+#define BATMON_VTH1 1 -+#define BATMON_VTH2 2 -+#define BATMON_VTH3 3 -+#define BATMON_HR 4 -+#define BATMON_OK 5 -+#define BAT_LOW_EN 6 -+#define BAT_LOW 7 -+ -+#define XOSC_CTRL _SFR_MEM8(0x152) -+#define XTAL_TRIM0 0 -+#define XTAL_TRIM1 1 -+#define XTAL_TRIM2 2 -+#define XTAL_TRIM3 3 -+#define XTAL_MODE0 4 -+#define XTAL_MODE1 5 -+#define XTAL_MODE2 6 -+#define XTAL_MODE3 7 -+ -+#define CC_CTRL_0 _SFR_MEM8(0x153) -+#define CC_NUMBER0 0 -+#define CC_NUMBER1 1 -+#define CC_NUMBER2 2 -+#define CC_NUMBER3 3 -+#define CC_NUMBER4 4 -+#define CC_NUMBER5 5 -+#define CC_NUMBER6 6 -+#define CC_NUMBER7 7 -+ -+#define CC_CTRL_1 _SFR_MEM8(0x154) -+#define CC_BAND0 0 -+#define CC_BAND1 1 -+#define CC_BAND2 2 -+#define CC_BAND3 3 -+ -+#define RX_SYN _SFR_MEM8(0x155) -+#define RX_PDT_LEVEL0 0 -+#define RX_PDT_LEVEL1 1 -+#define RX_PDT_LEVEL2 2 -+#define RX_PDT_LEVEL3 3 -+#define RX_OVERRIDE 6 -+#define RX_PDT_DIS 7 -+ -+#define TRX_RPC _SFR_MEM8(0x156) -+#define XAH_RPC_EN 0 -+#define IPAN_RPC_EN 1 -+#define PLL_RPC_EN 3 -+#define PDT_RPC_EN 4 -+#define RX_RPC_EN 5 -+#define RX_RPC_CTRL0 6 -+#define RX_RPC_CTRL1 7 -+ -+#define XAH_CTRL_1 _SFR_MEM8(0x157) -+#define AACK_PROM_MODE 1 -+#define AACK_ACK_TIME 2 -+#define AACK_UPLD_RES_FT 4 -+#define AACK_FLTR_RES_FT 5 -+ -+#define FTN_CTRL _SFR_MEM8(0x158) -+#define FTN_START 7 -+ -+/* Reserved [0x159] */ -+ -+#define PLL_CF _SFR_MEM8(0x15A) -+#define PLL_CF_START 7 -+ -+#define PLL_DCU _SFR_MEM8(0x15B) -+#define PLL_DCU_START 7 -+ -+#define PART_NUM _SFR_MEM8(0x15C) -+#define PART_NUM0 0 -+#define PART_NUM1 1 -+#define PART_NUM2 2 -+#define PART_NUM3 3 -+#define PART_NUM4 4 -+#define PART_NUM5 5 -+#define PART_NUM6 6 -+#define PART_NUM7 7 -+ -+#define VERSION_NUM _SFR_MEM8(0x15D) -+#define VERSION_NUM0 0 -+#define VERSION_NUM1 1 -+#define VERSION_NUM2 2 -+#define VERSION_NUM3 3 -+#define VERSION_NUM4 4 -+#define VERSION_NUM5 5 -+#define VERSION_NUM6 6 -+#define VERSION_NUM7 7 -+ -+#define MAN_ID_0 _SFR_MEM8(0x15E) -+#define MAN_ID_00 0 -+#define MAN_ID_01 1 -+#define MAN_ID_02 2 -+#define MAN_ID_03 3 -+#define MAN_ID_04 4 -+#define MAN_ID_05 5 -+#define MAN_ID_06 6 -+#define MAN_ID_07 7 -+ -+#define MAN_ID_1 _SFR_MEM8(0x15F) -+#define MAN_ID_10 0 -+#define MAN_ID_11 1 -+#define MAN_ID_12 2 -+#define MAN_ID_13 3 -+#define MAN_ID_14 4 -+#define MAN_ID_15 5 -+#define MAN_ID_16 6 -+#define MAN_ID_17 7 -+ -+#define SHORT_ADDR_0 _SFR_MEM8(0x160) -+#define SHORT_ADDR_00 0 -+#define SHORT_ADDR_01 1 -+#define SHORT_ADDR_02 2 -+#define SHORT_ADDR_03 3 -+#define SHORT_ADDR_04 4 -+#define SHORT_ADDR_05 5 -+#define SHORT_ADDR_06 6 -+#define SHORT_ADDR_07 7 -+ -+#define SHORT_ADDR_1 _SFR_MEM8(0x161) -+#define SHORT_ADDR_10 0 -+#define SHORT_ADDR_11 1 -+#define SHORT_ADDR_12 2 -+#define SHORT_ADDR_13 3 -+#define SHORT_ADDR_14 4 -+#define SHORT_ADDR_15 5 -+#define SHORT_ADDR_16 6 -+#define SHORT_ADDR_17 7 -+ -+#define PAN_ID_0 _SFR_MEM8(0x162) -+#define PAN_ID_00 0 -+#define PAN_ID_01 1 -+#define PAN_ID_02 2 -+#define PAN_ID_03 3 -+#define PAN_ID_04 4 -+#define PAN_ID_05 5 -+#define PAN_ID_06 6 -+#define PAN_ID_07 7 -+ -+#define PAN_ID_1 _SFR_MEM8(0x163) -+#define PAN_ID_10 0 -+#define PAN_ID_11 1 -+#define PAN_ID_12 2 -+#define PAN_ID_13 3 -+#define PAN_ID_14 4 -+#define PAN_ID_15 5 -+#define PAN_ID_16 6 -+#define PAN_ID_17 7 -+ -+#define IEEE_ADDR_0 _SFR_MEM8(0x164) -+#define IEEE_ADDR_00 0 -+#define IEEE_ADDR_01 1 -+#define IEEE_ADDR_02 2 -+#define IEEE_ADDR_03 3 -+#define IEEE_ADDR_04 4 -+#define IEEE_ADDR_05 5 -+#define IEEE_ADDR_06 6 -+#define IEEE_ADDR_07 7 -+ -+#define IEEE_ADDR_1 _SFR_MEM8(0x165) -+#define IEEE_ADDR_10 0 -+#define IEEE_ADDR_11 1 -+#define IEEE_ADDR_12 2 -+#define IEEE_ADDR_13 3 -+#define IEEE_ADDR_14 4 -+#define IEEE_ADDR_15 5 -+#define IEEE_ADDR_16 6 -+#define IEEE_ADDR_17 7 -+ -+#define IEEE_ADDR_2 _SFR_MEM8(0x166) -+#define IEEE_ADDR_20 0 -+#define IEEE_ADDR_21 1 -+#define IEEE_ADDR_22 2 -+#define IEEE_ADDR_23 3 -+#define IEEE_ADDR_24 4 -+#define IEEE_ADDR_25 5 -+#define IEEE_ADDR_26 6 -+#define IEEE_ADDR_27 7 -+ -+#define IEEE_ADDR_3 _SFR_MEM8(0x167) -+#define IEEE_ADDR_30 0 -+#define IEEE_ADDR_31 1 -+#define IEEE_ADDR_32 2 -+#define IEEE_ADDR_33 3 -+#define IEEE_ADDR_34 4 -+#define IEEE_ADDR_35 5 -+#define IEEE_ADDR_36 6 -+#define IEEE_ADDR_37 7 -+ -+#define IEEE_ADDR_4 _SFR_MEM8(0x168) -+#define IEEE_ADDR_40 0 -+#define IEEE_ADDR_41 1 -+#define IEEE_ADDR_42 2 -+#define IEEE_ADDR_43 3 -+#define IEEE_ADDR_44 4 -+#define IEEE_ADDR_45 5 -+#define IEEE_ADDR_46 6 -+#define IEEE_ADDR_47 7 -+ -+#define IEEE_ADDR_5 _SFR_MEM8(0x169) -+#define IEEE_ADDR_50 0 -+#define IEEE_ADDR_51 1 -+#define IEEE_ADDR_52 2 -+#define IEEE_ADDR_53 3 -+#define IEEE_ADDR_54 4 -+#define IEEE_ADDR_55 5 -+#define IEEE_ADDR_56 6 -+#define IEEE_ADDR_57 7 -+ -+#define IEEE_ADDR_6 _SFR_MEM8(0x16A) -+#define IEEE_ADDR_60 0 -+#define IEEE_ADDR_61 1 -+#define IEEE_ADDR_62 2 -+#define IEEE_ADDR_63 3 -+#define IEEE_ADDR_64 4 -+#define IEEE_ADDR_65 5 -+#define IEEE_ADDR_66 6 -+#define IEEE_ADDR_67 7 -+ -+#define IEEE_ADDR_7 _SFR_MEM8(0x16B) -+#define IEEE_ADDR_70 0 -+#define IEEE_ADDR_71 1 -+#define IEEE_ADDR_72 2 -+#define IEEE_ADDR_73 3 -+#define IEEE_ADDR_74 4 -+#define IEEE_ADDR_75 5 -+#define IEEE_ADDR_76 6 -+#define IEEE_ADDR_77 7 -+ -+#define XAH_CTRL_0 _SFR_MEM8(0x16C) -+#define SLOTTED_OPERATION 0 -+#define MAX_CSMA_RETRIES0 1 -+#define MAX_CSMA_RETRIES1 2 -+#define MAX_CSMA_RETRIES2 3 -+#define MAX_FRAME_RETRIES0 4 -+#define MAX_FRAME_RETRIES1 5 -+#define MAX_FRAME_RETRIES2 6 -+#define MAX_FRAME_RETRIES3 7 -+ -+#define CSMA_SEED_0 _SFR_MEM8(0x16D) -+#define CSMA_SEED_00 0 -+#define CSMA_SEED_01 1 -+#define CSMA_SEED_02 2 -+#define CSMA_SEED_03 3 -+#define CSMA_SEED_04 4 -+#define CSMA_SEED_05 5 -+#define CSMA_SEED_06 6 -+#define CSMA_SEED_07 7 -+ -+#define CSMA_SEED_1 _SFR_MEM8(0x16E) -+#define CSMA_SEED_10 0 -+#define CSMA_SEED_11 1 -+#define CSMA_SEED_12 2 -+#define AACK_I_AM_COORD 3 -+#define AACK_DIS_ACK 4 -+#define AACK_SET_PD 5 -+#define AACK_FVN_MODE0 6 -+#define AACK_FVN_MODE1 7 -+ -+#define CSMA_BE _SFR_MEM8(0x16F) -+#define MIN_BE0 0 -+#define MIN_BE1 1 -+#define MIN_BE2 2 -+#define MIN_BE3 3 -+#define MAX_BE0 4 -+#define MAX_BE1 5 -+#define MAX_BE2 6 -+#define MAX_BE3 7 -+ -+/* Reserved [0x170..0x175] */ -+ -+#define TST_CTRL_DIGI _SFR_MEM8(0x176) -+#define TST_CTRL_DIG0 0 -+#define TST_CTRL_DIG1 1 -+#define TST_CTRL_DIG2 2 -+#define TST_CTRL_DIG3 3 -+ -+/* Reserved [0x177..0x17A] */ -+ -+#define TST_RX_LENGTH _SFR_MEM8(0x17B) -+#define RX_LENGTH0 0 -+#define RX_LENGTH1 1 -+#define RX_LENGTH2 2 -+#define RX_LENGTH3 3 -+#define RX_LENGTH4 4 -+#define RX_LENGTH5 5 -+#define RX_LENGTH6 6 -+#define RX_LENGTH7 7 -+ -+/* Reserved [0x17C..0x17F] */ -+ -+#define TRXFBST _SFR_MEM8(0x180) -+ -+/* Reserved [0x181..0x1FE] */ -+ -+#define TRXFBEND _SFR_MEM8(0x1FF) -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* External Interrupt Request 2 */ -+#define INT2_vect _VECTOR(3) -+#define INT2_vect_num 3 -+ -+/* External Interrupt Request 3 */ -+#define INT3_vect _VECTOR(4) -+#define INT3_vect_num 4 -+ -+/* External Interrupt Request 4 */ -+#define INT4_vect _VECTOR(5) -+#define INT4_vect_num 5 -+ -+/* External Interrupt Request 5 */ -+#define INT5_vect _VECTOR(6) -+#define INT5_vect_num 6 -+ -+/* External Interrupt Request 6 */ -+#define INT6_vect _VECTOR(7) -+#define INT6_vect_num 7 -+ -+/* External Interrupt Request 7 */ -+#define INT7_vect _VECTOR(8) -+#define INT7_vect_num 8 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(9) -+#define PCINT0_vect_num 9 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(10) -+#define PCINT1_vect_num 10 -+ -+/* Pin Change Interrupt Request 2 */ -+#define PCINT2_vect _VECTOR(11) -+#define PCINT2_vect_num 11 -+ -+/* Watchdog Time-out Interrupt */ -+#define WDT_vect _VECTOR(12) -+#define WDT_vect_num 12 -+ -+/* Timer/Counter2 Compare Match A */ -+#define TIMER2_COMPA_vect _VECTOR(13) -+#define TIMER2_COMPA_vect_num 13 -+ -+/* Timer/Counter2 Compare Match B */ -+#define TIMER2_COMPB_vect _VECTOR(14) -+#define TIMER2_COMPB_vect_num 14 -+ -+/* Timer/Counter2 Overflow */ -+#define TIMER2_OVF_vect _VECTOR(15) -+#define TIMER2_OVF_vect_num 15 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(16) -+#define TIMER1_CAPT_vect_num 16 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(17) -+#define TIMER1_COMPA_vect_num 17 -+ -+/* Timer/Counter1 Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(18) -+#define TIMER1_COMPB_vect_num 18 -+ -+/* Timer/Counter1 Compare Match C */ -+#define TIMER1_COMPC_vect _VECTOR(19) -+#define TIMER1_COMPC_vect_num 19 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(20) -+#define TIMER1_OVF_vect_num 20 -+ -+/* Timer/Counter0 Compare Match A */ -+#define TIMER0_COMPA_vect _VECTOR(21) -+#define TIMER0_COMPA_vect_num 21 -+ -+/* Timer/Counter0 Compare Match B */ -+#define TIMER0_COMPB_vect _VECTOR(22) -+#define TIMER0_COMPB_vect_num 22 -+ -+/* Timer/Counter0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(23) -+#define TIMER0_OVF_vect_num 23 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(24) -+#define SPI_STC_vect_num 24 -+ -+/* USART0, Rx Complete */ -+#define USART0_RX_vect _VECTOR(25) -+#define USART0_RX_vect_num 25 -+ -+/* USART0 Data register Empty */ -+#define USART0_UDRE_vect _VECTOR(26) -+#define USART0_UDRE_vect_num 26 -+ -+/* USART0, Tx Complete */ -+#define USART0_TX_vect _VECTOR(27) -+#define USART0_TX_vect_num 27 -+ -+/* Analog Comparator */ -+#define ANALOG_COMP_vect _VECTOR(28) -+#define ANALOG_COMP_vect_num 28 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(29) -+#define ADC_vect_num 29 -+ -+/* EEPROM Ready */ -+#define EE_READY_vect _VECTOR(30) -+#define EE_READY_vect_num 30 -+ -+/* Timer/Counter3 Capture Event */ -+#define TIMER3_CAPT_vect _VECTOR(31) -+#define TIMER3_CAPT_vect_num 31 -+ -+/* Timer/Counter3 Compare Match A */ -+#define TIMER3_COMPA_vect _VECTOR(32) -+#define TIMER3_COMPA_vect_num 32 -+ -+/* Timer/Counter3 Compare Match B */ -+#define TIMER3_COMPB_vect _VECTOR(33) -+#define TIMER3_COMPB_vect_num 33 -+ -+/* Timer/Counter3 Compare Match C */ -+#define TIMER3_COMPC_vect _VECTOR(34) -+#define TIMER3_COMPC_vect_num 34 -+ -+/* Timer/Counter3 Overflow */ -+#define TIMER3_OVF_vect _VECTOR(35) -+#define TIMER3_OVF_vect_num 35 -+ -+/* USART1, Rx Complete */ -+#define USART1_RX_vect _VECTOR(36) -+#define USART1_RX_vect_num 36 -+ -+/* USART1 Data register Empty */ -+#define USART1_UDRE_vect _VECTOR(37) -+#define USART1_UDRE_vect_num 37 -+ -+/* USART1, Tx Complete */ -+#define USART1_TX_vect _VECTOR(38) -+#define USART1_TX_vect_num 38 -+ -+/* 2-wire Serial Interface */ -+#define TWI_vect _VECTOR(39) -+#define TWI_vect_num 39 -+ -+/* Store Program Memory Read */ -+#define SPM_READY_vect _VECTOR(40) -+#define SPM_READY_vect_num 40 -+ -+/* Timer/Counter4 Capture Event */ -+#define TIMER4_CAPT_vect _VECTOR(41) -+#define TIMER4_CAPT_vect_num 41 -+ -+/* Timer/Counter4 Compare Match A */ -+#define TIMER4_COMPA_vect _VECTOR(42) -+#define TIMER4_COMPA_vect_num 42 -+ -+/* Timer/Counter4 Compare Match B */ -+#define TIMER4_COMPB_vect _VECTOR(43) -+#define TIMER4_COMPB_vect_num 43 -+ -+/* Timer/Counter4 Compare Match C */ -+#define TIMER4_COMPC_vect _VECTOR(44) -+#define TIMER4_COMPC_vect_num 44 -+ -+/* Timer/Counter4 Overflow */ -+#define TIMER4_OVF_vect _VECTOR(45) -+#define TIMER4_OVF_vect_num 45 -+ -+/* Timer/Counter5 Capture Event */ -+#define TIMER5_CAPT_vect _VECTOR(46) -+#define TIMER5_CAPT_vect_num 46 -+ -+/* Timer/Counter5 Compare Match A */ -+#define TIMER5_COMPA_vect _VECTOR(47) -+#define TIMER5_COMPA_vect_num 47 -+ -+/* Timer/Counter5 Compare Match B */ -+#define TIMER5_COMPB_vect _VECTOR(48) -+#define TIMER5_COMPB_vect_num 48 -+ -+/* Timer/Counter5 Compare Match C */ -+#define TIMER5_COMPC_vect _VECTOR(49) -+#define TIMER5_COMPC_vect_num 49 -+ -+/* Timer/Counter5 Overflow */ -+#define TIMER5_OVF_vect _VECTOR(50) -+#define TIMER5_OVF_vect_num 50 -+ -+/* USART2, Rx Complete */ -+#define USART2_RX_vect _VECTOR(51) -+#define USART2_RX_vect_num 51 -+ -+/* USART2 Data register Empty */ -+#define USART2_UDRE_vect _VECTOR(52) -+#define USART2_UDRE_vect_num 52 -+ -+/* USART2, Tx Complete */ -+#define USART2_TX_vect _VECTOR(53) -+#define USART2_TX_vect_num 53 -+ -+/* USART3, Rx Complete */ -+#define USART3_RX_vect _VECTOR(54) -+#define USART3_RX_vect_num 54 -+ -+/* USART3 Data register Empty */ -+#define USART3_UDRE_vect _VECTOR(55) -+#define USART3_UDRE_vect_num 55 -+ -+/* USART3, Tx Complete */ -+#define USART3_TX_vect _VECTOR(56) -+#define USART3_TX_vect_num 56 -+ -+/* TRX24 - PLL lock interrupt */ -+#define TRX24_PLL_LOCK_vect _VECTOR(57) -+#define TRX24_PLL_LOCK_vect_num 57 -+ -+/* TRX24 - PLL unlock interrupt */ -+#define TRX24_PLL_UNLOCK_vect _VECTOR(58) -+#define TRX24_PLL_UNLOCK_vect_num 58 -+ -+/* TRX24 - Receive start interrupt */ -+#define TRX24_RX_START_vect _VECTOR(59) -+#define TRX24_RX_START_vect_num 59 -+ -+/* TRX24 - RX_END interrupt */ -+#define TRX24_RX_END_vect _VECTOR(60) -+#define TRX24_RX_END_vect_num 60 -+ -+/* TRX24 - CCA/ED done interrupt */ -+#define TRX24_CCA_ED_DONE_vect _VECTOR(61) -+#define TRX24_CCA_ED_DONE_vect_num 61 -+ -+/* TRX24 - XAH - AMI */ -+#define TRX24_XAH_AMI_vect _VECTOR(62) -+#define TRX24_XAH_AMI_vect_num 62 -+ -+/* TRX24 - TX_END interrupt */ -+#define TRX24_TX_END_vect _VECTOR(63) -+#define TRX24_TX_END_vect_num 63 -+ -+/* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */ -+#define TRX24_AWAKE_vect _VECTOR(64) -+#define TRX24_AWAKE_vect_num 64 -+ -+/* Symbol counter - compare match 1 interrupt */ -+#define SCNT_CMP1_vect _VECTOR(65) -+#define SCNT_CMP1_vect_num 65 -+ -+/* Symbol counter - compare match 2 interrupt */ -+#define SCNT_CMP2_vect _VECTOR(66) -+#define SCNT_CMP2_vect_num 66 -+ -+/* Symbol counter - compare match 3 interrupt */ -+#define SCNT_CMP3_vect _VECTOR(67) -+#define SCNT_CMP3_vect_num 67 -+ -+/* Symbol counter - overflow interrupt */ -+#define SCNT_OVFL_vect _VECTOR(68) -+#define SCNT_OVFL_vect_num 68 -+ -+/* Symbol counter - backoff interrupt */ -+#define SCNT_BACKOFF_vect _VECTOR(69) -+#define SCNT_BACKOFF_vect_num 69 -+ -+/* AES engine ready interrupt */ -+#define AES_READY_vect _VECTOR(70) -+#define AES_READY_vect_num 70 -+ -+/* Battery monitor indicates supply voltage below threshold */ -+#define BAT_LOW_vect _VECTOR(71) -+#define BAT_LOW_vect_num 71 -+ -+/* TRX24 TX start interrupt */ -+#define TRX24_TX_START_vect _VECTOR(72) -+#define TRX24_TX_START_vect_num 72 -+ -+/* Address match interrupt of address filter 0 */ -+#define TRX24_AMI0_vect _VECTOR(73) -+#define TRX24_AMI0_vect_num 73 -+ -+/* Address match interrupt of address filter 1 */ -+#define TRX24_AMI1_vect _VECTOR(74) -+#define TRX24_AMI1_vect_num 74 -+ -+/* Address match interrupt of address filter 2 */ -+#define TRX24_AMI2_vect _VECTOR(75) -+#define TRX24_AMI2_vect_num 75 -+ -+/* Address match interrupt of address filter 3 */ -+#define TRX24_AMI3_vect _VECTOR(76) -+#define TRX24_AMI3_vect_num 76 -+ -+#define _VECTORS_SIZE 308 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 256 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0xFFFF -+#define RAMSTART 0x0200 -+#define RAMSIZE 8192 -+#define RAMEND 0x21FF -+#define E2START 0 -+#define E2SIZE 2048 -+#define E2PAGESIZE 8 -+#define E2END 0x07FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_CKSEL_SUT0 (unsigned char)~_BV(0) -+#define FUSE_CKSEL_SUT1 (unsigned char)~_BV(1) -+#define FUSE_CKSEL_SUT2 (unsigned char)~_BV(2) -+#define FUSE_CKSEL_SUT3 (unsigned char)~_BV(3) -+#define FUSE_CKSEL_SUT4 (unsigned char)~_BV(4) -+#define FUSE_CKSEL_SUT5 (unsigned char)~_BV(5) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_JTAGEN (unsigned char)~_BV(6) -+#define FUSE_OCDEN (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0xA6 -+#define SIGNATURE_2 0x02 -+ -+ -+#endif /* #ifdef _AVR_ATMEGA64RFR2_H_INCLUDED */ -+ +@@ -0,0 +1,2550 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATMEGA64RFR2_H_INCLUDED ++#define _AVR_ATMEGA64RFR2_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom64rfr2.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDRA7 7 ++#define DDRA6 6 ++#define DDRA5 5 ++#define DDRA4 4 ++#define DDRA3 3 ++#define DDRA2 2 ++#define DDRA1 1 ++#define DDRA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDRC7 7 ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC7 7 ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDRE7 7 ++#define DDRE6 6 ++#define DDRE5 5 ++#define DDRE4 4 ++#define DDRE3 3 ++#define DDRE2 2 ++#define DDRE1 1 ++#define DDRE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE7 7 ++#define PORTE6 6 ++#define PORTE5 5 ++#define PORTE4 4 ++#define PORTE3 3 ++#define PORTE2 2 ++#define PORTE1 1 ++#define PORTE0 0 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDRF7 7 ++#define DDRF6 6 ++#define DDRF5 5 ++#define DDRF4 4 ++#define DDRF3 3 ++#define DDRF2 2 ++#define DDRF1 1 ++#define DDRF0 0 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PORTF7 7 ++#define PORTF6 6 ++#define PORTF5 5 ++#define PORTF4 4 ++#define PORTF3 3 ++#define PORTF2 2 ++#define PORTF1 1 ++#define PORTF0 0 ++ ++#define PING _SFR_IO8(0x12) ++#define PING7 7 ++#define PING6 6 ++#define PING5 5 ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++#define DDRG _SFR_IO8(0x13) ++#define DDRG7 7 ++#define DDRG6 6 ++#define DDRG5 5 ++#define DDRG4 4 ++#define DDRG3 3 ++#define DDRG2 2 ++#define DDRG1 1 ++#define DDRG0 0 ++ ++#define PORTG _SFR_IO8(0x14) ++#define PORTG7 7 ++#define PORTG6 6 ++#define PORTG5 5 ++#define PORTG4 4 ++#define PORTG3 3 ++#define PORTG2 2 ++#define PORTG1 1 ++#define PORTG0 0 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++#define Res0 3 ++#define Res1 4 ++#define Res2 5 ++#define Res3 6 ++#define Res4 7 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define OCF1C 3 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++#define TIFR3 _SFR_IO8(0x18) ++#define TOV3 0 ++#define OCF3A 1 ++#define OCF3B 2 ++#define OCF3C 3 ++#define ICF3 5 ++ ++#define TIFR4 _SFR_IO8(0x19) ++#define TOV4 0 ++#define OCF4A 1 ++#define OCF4B 2 ++#define OCF4C 3 ++#define ICF4 5 ++ ++#define TIFR5 _SFR_IO8(0x1A) ++#define TOV5 0 ++#define OCF5A 1 ++#define OCF5B 2 ++#define OCF5C 3 ++#define ICF5 5 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++#define INTF4 4 ++#define INTF5 5 ++#define INTF6 6 ++#define INTF7 7 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++#define INT3 3 ++#define INT4 4 ++#define INT5 5 ++#define INT6 6 ++#define INT7 7 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define PSRASY 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++ ++#define OCR0A _SFR_IO8(0x27) ++ ++#define OCR0B _SFR_IO8(0x28) ++ ++/* Reserved [0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCDR _SFR_IO8(0x31) ++#define OCDR0 0 ++#define OCDR1 1 ++#define OCDR2 2 ++#define OCDR3 3 ++#define OCDR4 4 ++#define OCDR5 5 ++#define OCDR6 6 ++#define OCDR7 7 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define JTRF 4 ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define JTD 7 ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDE 3 ++#define WDCE 4 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62] */ ++ ++#define PRR2 _SFR_MEM8(0x63) ++#define PRRAM0 0 ++#define PRRAM1 1 ++#define PRRAM2 2 ++#define PRRAM3 3 ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRPGA 4 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++#define PRR1 _SFR_MEM8(0x65) ++#define PRUSART1 0 ++#define PRTIM3 3 ++#define PRTIM4 4 ++#define PRTIM5 5 ++#define PRTRX24 6 ++#define Res 7 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++#define BGCR _SFR_MEM8(0x67) ++#define BGCAL0 0 ++#define BGCAL1 1 ++#define BGCAL2 2 ++#define BGCAL_FINE0 3 ++#define BGCAL_FINE1 4 ++#define BGCAL_FINE2 5 ++#define BGCAL_FINE3 6 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++#define EICRB _SFR_MEM8(0x6A) ++#define ISC40 0 ++#define ISC41 1 ++#define ISC50 2 ++#define ISC51 3 ++#define ISC60 4 ++#define ISC61 5 ++#define ISC70 6 ++#define ISC71 7 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define OCIE1C 3 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++#define TIMSK3 _SFR_MEM8(0x71) ++#define TOIE3 0 ++#define OCIE3A 1 ++#define OCIE3B 2 ++#define OCIE3C 3 ++#define ICIE3 5 ++ ++#define TIMSK4 _SFR_MEM8(0x72) ++#define TOIE4 0 ++#define OCIE4A 1 ++#define OCIE4B 2 ++#define OCIE4C 3 ++#define ICIE4 5 ++ ++#define TIMSK5 _SFR_MEM8(0x73) ++#define TOIE5 0 ++#define OCIE5A 1 ++#define OCIE5B 2 ++#define OCIE5C 3 ++#define ICIE5 5 ++ ++/* Reserved [0x74] */ ++ ++#define NEMCR _SFR_MEM8(0x75) ++#define AEAM0 4 ++#define AEAM1 5 ++#define ENEAM 6 ++ ++/* Reserved [0x76] */ ++ ++#define ADCSRC _SFR_MEM8(0x77) ++#define ADSUT0 0 ++#define ADSUT1 1 ++#define ADSUT2 2 ++#define ADSUT3 3 ++#define ADSUT4 4 ++#define ADTHT0 6 ++#define ADTHT1 7 ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ACME 6 ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define MUX5 3 ++#define ACCH 4 ++#define REFOK 5 ++#define AVDDOK 7 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR2 _SFR_MEM8(0x7D) ++#define ADC8D 0 ++#define ADC9D 1 ++#define ADC10D 2 ++#define ADC11D 3 ++#define ADC12D 4 ++#define ADC13D 5 ++#define ADC14D 6 ++#define ADC15D 7 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1C0 2 ++#define COM1C1 3 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1C 5 ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Combine OCR1CL and OCR1CH */ ++#define OCR1C _SFR_MEM16(0x8C) ++ ++#define OCR1CL _SFR_MEM8(0x8C) ++#define OCR1CH _SFR_MEM8(0x8D) ++ ++/* Reserved [0x8E..0x8F] */ ++ ++#define TCCR3A _SFR_MEM8(0x90) ++#define WGM30 0 ++#define WGM31 1 ++#define COM3C0 2 ++#define COM3C1 3 ++#define COM3B0 4 ++#define COM3B1 5 ++#define COM3A0 6 ++#define COM3A1 7 ++ ++#define TCCR3B _SFR_MEM8(0x91) ++#define CS30 0 ++#define CS31 1 ++#define CS32 2 ++#define WGM32 3 ++#define WGM33 4 ++#define ICES3 6 ++#define ICNC3 7 ++ ++#define TCCR3C _SFR_MEM8(0x92) ++#define FOC3C 5 ++#define FOC3B 6 ++#define FOC3A 7 ++ ++/* Reserved [0x93] */ ++ ++/* Combine TCNT3L and TCNT3H */ ++#define TCNT3 _SFR_MEM16(0x94) ++ ++#define TCNT3L _SFR_MEM8(0x94) ++#define TCNT3H _SFR_MEM8(0x95) ++ ++/* Combine ICR3L and ICR3H */ ++#define ICR3 _SFR_MEM16(0x96) ++ ++#define ICR3L _SFR_MEM8(0x96) ++#define ICR3H _SFR_MEM8(0x97) ++ ++/* Combine OCR3AL and OCR3AH */ ++#define OCR3A _SFR_MEM16(0x98) ++ ++#define OCR3AL _SFR_MEM8(0x98) ++#define OCR3AH _SFR_MEM8(0x99) ++ ++/* Combine OCR3BL and OCR3BH */ ++#define OCR3B _SFR_MEM16(0x9A) ++ ++#define OCR3BL _SFR_MEM8(0x9A) ++#define OCR3BH _SFR_MEM8(0x9B) ++ ++/* Combine OCR3CL and OCR3CH */ ++#define OCR3C _SFR_MEM16(0x9C) ++ ++#define OCR3CL _SFR_MEM8(0x9C) ++#define OCR3CH _SFR_MEM8(0x9D) ++ ++/* Reserved [0x9E..0x9F] */ ++ ++#define TCCR4A _SFR_MEM8(0xA0) ++#define WGM40 0 ++#define WGM41 1 ++#define COM4C0 2 ++#define COM4C1 3 ++#define COM4B0 4 ++#define COM4B1 5 ++#define COM4A0 6 ++#define COM4A1 7 ++ ++#define TCCR4B _SFR_MEM8(0xA1) ++#define CS40 0 ++#define CS41 1 ++#define CS42 2 ++#define WGM42 3 ++#define WGM43 4 ++#define ICES4 6 ++#define ICNC4 7 ++ ++#define TCCR4C _SFR_MEM8(0xA2) ++#define FOC4C 5 ++#define FOC4B 6 ++#define FOC4A 7 ++ ++/* Reserved [0xA3] */ ++ ++/* Combine TCNT4L and TCNT4H */ ++#define TCNT4 _SFR_MEM16(0xA4) ++ ++#define TCNT4L _SFR_MEM8(0xA4) ++#define TCNT4H _SFR_MEM8(0xA5) ++ ++/* Combine ICR4L and ICR4H */ ++#define ICR4 _SFR_MEM16(0xA6) ++ ++#define ICR4L _SFR_MEM8(0xA6) ++#define ICR4H _SFR_MEM8(0xA7) ++ ++/* Combine OCR4AL and OCR4AH */ ++#define OCR4A _SFR_MEM16(0xA8) ++ ++#define OCR4AL _SFR_MEM8(0xA8) ++#define OCR4AH _SFR_MEM8(0xA9) ++ ++/* Combine OCR4BL and OCR4BH */ ++#define OCR4B _SFR_MEM16(0xAA) ++ ++#define OCR4BL _SFR_MEM8(0xAA) ++#define OCR4BH _SFR_MEM8(0xAB) ++ ++/* Combine OCR4CL and OCR4CH */ ++#define OCR4C _SFR_MEM16(0xAC) ++ ++#define OCR4CL _SFR_MEM8(0xAC) ++#define OCR4CH _SFR_MEM8(0xAD) ++ ++/* Reserved [0xAE..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++#define OCR2B _SFR_MEM8(0xB4) ++ ++/* Reserved [0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++#define EXCLKAMR 7 ++ ++/* Reserved [0xB7] */ ++ ++#define TWBR _SFR_MEM8(0xB8) ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++#define IRQ_MASK1 _SFR_MEM8(0xBE) ++#define TX_START_EN 0 ++#define MAF_0_AMI_EN 1 ++#define MAF_1_AMI_EN 2 ++#define MAF_2_AMI_EN 3 ++#define MAF_3_AMI_EN 4 ++ ++#define IRQ_STATUS1 _SFR_MEM8(0xBF) ++#define TX_START 0 ++#define MAF_0_AMI 1 ++#define MAF_1_AMI 2 ++#define MAF_2_AMI 3 ++#define MAF_3_AMI 4 ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++#define UCPHA0 1 ++#define UDORD0 2 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0xC6) ++ ++/* Reserved [0xC7] */ ++ ++#define UCSR1A _SFR_MEM8(0xC8) ++#define MPCM1 0 ++#define U2X1 1 ++#define UPE1 2 ++#define DOR1 3 ++#define FE1 4 ++#define UDRE1 5 ++#define TXC1 6 ++#define RXC1 7 ++ ++#define UCSR1B _SFR_MEM8(0xC9) ++#define TXB81 0 ++#define RXB81 1 ++#define UCSZ12 2 ++#define TXEN1 3 ++#define RXEN1 4 ++#define UDRIE1 5 ++#define TXCIE1 6 ++#define RXCIE1 7 ++ ++#define UCSR1C _SFR_MEM8(0xCA) ++#define UCPOL1 0 ++#define UCSZ10 1 ++#define UCSZ11 2 ++#define USBS1 3 ++#define UPM10 4 ++#define UPM11 5 ++#define UMSEL10 6 ++#define UMSEL11 7 ++#define UCPHA1 1 ++#define UDORD1 2 ++ ++/* Reserved [0xCB] */ ++ ++/* Combine UBRR1L and UBRR1H */ ++#define UBRR1 _SFR_MEM16(0xCC) ++ ++#define UBRR1L _SFR_MEM8(0xCC) ++#define UBRR1H _SFR_MEM8(0xCD) ++ ++#define UDR1 _SFR_MEM8(0xCE) ++ ++/* Reserved [0xCF..0xD6] */ ++ ++#define SCRSTRLL _SFR_MEM8(0xD7) ++#define SCRSTRLL0 0 ++#define SCRSTRLL1 1 ++#define SCRSTRLL2 2 ++#define SCRSTRLL3 3 ++#define SCRSTRLL4 4 ++#define SCRSTRLL5 5 ++#define SCRSTRLL6 6 ++#define SCRSTRLL7 7 ++ ++#define SCRSTRLH _SFR_MEM8(0xD8) ++#define SCRSTRLH0 0 ++#define SCRSTRLH1 1 ++#define SCRSTRLH2 2 ++#define SCRSTRLH3 3 ++#define SCRSTRLH4 4 ++#define SCRSTRLH5 5 ++#define SCRSTRLH6 6 ++#define SCRSTRLH7 7 ++ ++#define SCRSTRHL _SFR_MEM8(0xD9) ++#define SCRSTRHL0 0 ++#define SCRSTRHL1 1 ++#define SCRSTRHL2 2 ++#define SCRSTRHL3 3 ++#define SCRSTRHL4 4 ++#define SCRSTRHL5 5 ++#define SCRSTRHL6 6 ++#define SCRSTRHL7 7 ++ ++#define SCRSTRHH _SFR_MEM8(0xDA) ++#define SCRSTRHH0 0 ++#define SCRSTRHH1 1 ++#define SCRSTRHH2 2 ++#define SCRSTRHH3 3 ++#define SCRSTRHH4 4 ++#define SCRSTRHH5 5 ++#define SCRSTRHH6 6 ++#define SCRSTRHH7 7 ++ ++#define SCCSR _SFR_MEM8(0xDB) ++#define SCCS10 0 ++#define SCCS11 1 ++#define SCCS20 2 ++#define SCCS21 3 ++#define SCCS30 4 ++#define SCCS31 5 ++ ++#define SCCR0 _SFR_MEM8(0xDC) ++#define SCCMP1 0 ++#define SCCMP2 1 ++#define SCCMP3 2 ++#define SCTSE 3 ++#define SCCKSEL 4 ++#define SCEN 5 ++#define SCMBTS 6 ++#define SCRES 7 ++ ++#define SCCR1 _SFR_MEM8(0xDD) ++#define SCENBO 0 ++#define SCEECLK 1 ++#define SCCKDIV0 2 ++#define SCCKDIV1 3 ++#define SCCKDIV2 4 ++#define SCBTSM 5 ++#define Res5 6 ++#define Res6 7 ++ ++#define SCSR _SFR_MEM8(0xDE) ++#define SCBSY 0 ++ ++#define SCIRQM _SFR_MEM8(0xDF) ++#define IRQMCP1 0 ++#define IRQMCP2 1 ++#define IRQMCP3 2 ++#define IRQMOF 3 ++#define IRQMBO 4 ++ ++#define SCIRQS _SFR_MEM8(0xE0) ++#define IRQSCP1 0 ++#define IRQSCP2 1 ++#define IRQSCP3 2 ++#define IRQSOF 3 ++#define IRQSBO 4 ++ ++#define SCCNTLL _SFR_MEM8(0xE1) ++#define SCCNTLL0 0 ++#define SCCNTLL1 1 ++#define SCCNTLL2 2 ++#define SCCNTLL3 3 ++#define SCCNTLL4 4 ++#define SCCNTLL5 5 ++#define SCCNTLL6 6 ++#define SCCNTLL7 7 ++ ++#define SCCNTLH _SFR_MEM8(0xE2) ++#define SCCNTLH0 0 ++#define SCCNTLH1 1 ++#define SCCNTLH2 2 ++#define SCCNTLH3 3 ++#define SCCNTLH4 4 ++#define SCCNTLH5 5 ++#define SCCNTLH6 6 ++#define SCCNTLH7 7 ++ ++#define SCCNTHL _SFR_MEM8(0xE3) ++#define SCCNTHL0 0 ++#define SCCNTHL1 1 ++#define SCCNTHL2 2 ++#define SCCNTHL3 3 ++#define SCCNTHL4 4 ++#define SCCNTHL5 5 ++#define SCCNTHL6 6 ++#define SCCNTHL7 7 ++ ++#define SCCNTHH _SFR_MEM8(0xE4) ++#define SCCNTHH0 0 ++#define SCCNTHH1 1 ++#define SCCNTHH2 2 ++#define SCCNTHH3 3 ++#define SCCNTHH4 4 ++#define SCCNTHH5 5 ++#define SCCNTHH6 6 ++#define SCCNTHH7 7 ++ ++#define SCBTSRLL _SFR_MEM8(0xE5) ++#define SCBTSRLL0 0 ++#define SCBTSRLL1 1 ++#define SCBTSRLL2 2 ++#define SCBTSRLL3 3 ++#define SCBTSRLL4 4 ++#define SCBTSRLL5 5 ++#define SCBTSRLL6 6 ++#define SCBTSRLL7 7 ++ ++#define SCBTSRLH _SFR_MEM8(0xE6) ++#define SCBTSRLH0 0 ++#define SCBTSRLH1 1 ++#define SCBTSRLH2 2 ++#define SCBTSRLH3 3 ++#define SCBTSRLH4 4 ++#define SCBTSRLH5 5 ++#define SCBTSRLH6 6 ++#define SCBTSRLH7 7 ++ ++#define SCBTSRHL _SFR_MEM8(0xE7) ++#define SCBTSRHL0 0 ++#define SCBTSRHL1 1 ++#define SCBTSRHL2 2 ++#define SCBTSRHL3 3 ++#define SCBTSRHL4 4 ++#define SCBTSRHL5 5 ++#define SCBTSRHL6 6 ++#define SCBTSRHL7 7 ++ ++#define SCBTSRHH _SFR_MEM8(0xE8) ++#define SCBTSRHH0 0 ++#define SCBTSRHH1 1 ++#define SCBTSRHH2 2 ++#define SCBTSRHH3 3 ++#define SCBTSRHH4 4 ++#define SCBTSRHH5 5 ++#define SCBTSRHH6 6 ++#define SCBTSRHH7 7 ++ ++#define SCTSRLL _SFR_MEM8(0xE9) ++#define SCTSRLL0 0 ++#define SCTSRLL1 1 ++#define SCTSRLL2 2 ++#define SCTSRLL3 3 ++#define SCTSRLL4 4 ++#define SCTSRLL5 5 ++#define SCTSRLL6 6 ++#define SCTSRLL7 7 ++ ++#define SCTSRLH _SFR_MEM8(0xEA) ++#define SCTSRLH0 0 ++#define SCTSRLH1 1 ++#define SCTSRLH2 2 ++#define SCTSRLH3 3 ++#define SCTSRLH4 4 ++#define SCTSRLH5 5 ++#define SCTSRLH6 6 ++#define SCTSRLH7 7 ++ ++#define SCTSRHL _SFR_MEM8(0xEB) ++#define SCTSRHL0 0 ++#define SCTSRHL1 1 ++#define SCTSRHL2 2 ++#define SCTSRHL3 3 ++#define SCTSRHL4 4 ++#define SCTSRHL5 5 ++#define SCTSRHL6 6 ++#define SCTSRHL7 7 ++ ++#define SCTSRHH _SFR_MEM8(0xEC) ++#define SCTSRHH0 0 ++#define SCTSRHH1 1 ++#define SCTSRHH2 2 ++#define SCTSRHH3 3 ++#define SCTSRHH4 4 ++#define SCTSRHH5 5 ++#define SCTSRHH6 6 ++#define SCTSRHH7 7 ++ ++#define SCOCR3LL _SFR_MEM8(0xED) ++#define SCOCR3LL0 0 ++#define SCOCR3LL1 1 ++#define SCOCR3LL2 2 ++#define SCOCR3LL3 3 ++#define SCOCR3LL4 4 ++#define SCOCR3LL5 5 ++#define SCOCR3LL6 6 ++#define SCOCR3LL7 7 ++ ++#define SCOCR3LH _SFR_MEM8(0xEE) ++#define SCOCR3LH0 0 ++#define SCOCR3LH1 1 ++#define SCOCR3LH2 2 ++#define SCOCR3LH3 3 ++#define SCOCR3LH4 4 ++#define SCOCR3LH5 5 ++#define SCOCR3LH6 6 ++#define SCOCR3LH7 7 ++ ++#define SCOCR3HL _SFR_MEM8(0xEF) ++#define SCOCR3HL0 0 ++#define SCOCR3HL1 1 ++#define SCOCR3HL2 2 ++#define SCOCR3HL3 3 ++#define SCOCR3HL4 4 ++#define SCOCR3HL5 5 ++#define SCOCR3HL6 6 ++#define SCOCR3HL7 7 ++ ++#define SCOCR3HH _SFR_MEM8(0xF0) ++#define SCOCR3HH0 0 ++#define SCOCR3HH1 1 ++#define SCOCR3HH2 2 ++#define SCOCR3HH3 3 ++#define SCOCR3HH4 4 ++#define SCOCR3HH5 5 ++#define SCOCR3HH6 6 ++#define SCOCR3HH7 7 ++ ++#define SCOCR2LL _SFR_MEM8(0xF1) ++#define SCOCR2LL0 0 ++#define SCOCR2LL1 1 ++#define SCOCR2LL2 2 ++#define SCOCR2LL3 3 ++#define SCOCR2LL4 4 ++#define SCOCR2LL5 5 ++#define SCOCR2LL6 6 ++#define SCOCR2LL7 7 ++ ++#define SCOCR2LH _SFR_MEM8(0xF2) ++#define SCOCR2LH0 0 ++#define SCOCR2LH1 1 ++#define SCOCR2LH2 2 ++#define SCOCR2LH3 3 ++#define SCOCR2LH4 4 ++#define SCOCR2LH5 5 ++#define SCOCR2LH6 6 ++#define SCOCR2LH7 7 ++ ++#define SCOCR2HL _SFR_MEM8(0xF3) ++#define SCOCR2HL0 0 ++#define SCOCR2HL1 1 ++#define SCOCR2HL2 2 ++#define SCOCR2HL3 3 ++#define SCOCR2HL4 4 ++#define SCOCR2HL5 5 ++#define SCOCR2HL6 6 ++#define SCOCR2HL7 7 ++ ++#define SCOCR2HH _SFR_MEM8(0xF4) ++#define SCOCR2HH0 0 ++#define SCOCR2HH1 1 ++#define SCOCR2HH2 2 ++#define SCOCR2HH3 3 ++#define SCOCR2HH4 4 ++#define SCOCR2HH5 5 ++#define SCOCR2HH6 6 ++#define SCOCR2HH7 7 ++ ++#define SCOCR1LL _SFR_MEM8(0xF5) ++#define SCOCR1LL0 0 ++#define SCOCR1LL1 1 ++#define SCOCR1LL2 2 ++#define SCOCR1LL3 3 ++#define SCOCR1LL4 4 ++#define SCOCR1LL5 5 ++#define SCOCR1LL6 6 ++#define SCOCR1LL7 7 ++ ++#define SCOCR1LH _SFR_MEM8(0xF6) ++#define SCOCR1LH0 0 ++#define SCOCR1LH1 1 ++#define SCOCR1LH2 2 ++#define SCOCR1LH3 3 ++#define SCOCR1LH4 4 ++#define SCOCR1LH5 5 ++#define SCOCR1LH6 6 ++#define SCOCR1LH7 7 ++ ++#define SCOCR1HL _SFR_MEM8(0xF7) ++#define SCOCR1HL0 0 ++#define SCOCR1HL1 1 ++#define SCOCR1HL2 2 ++#define SCOCR1HL3 3 ++#define SCOCR1HL4 4 ++#define SCOCR1HL5 5 ++#define SCOCR1HL6 6 ++#define SCOCR1HL7 7 ++ ++#define SCOCR1HH _SFR_MEM8(0xF8) ++#define SCOCR1HH0 0 ++#define SCOCR1HH1 1 ++#define SCOCR1HH2 2 ++#define SCOCR1HH3 3 ++#define SCOCR1HH4 4 ++#define SCOCR1HH5 5 ++#define SCOCR1HH6 6 ++#define SCOCR1HH7 7 ++ ++#define SCTSTRLL _SFR_MEM8(0xF9) ++#define SCTSTRLL0 0 ++#define SCTSTRLL1 1 ++#define SCTSTRLL2 2 ++#define SCTSTRLL3 3 ++#define SCTSTRLL4 4 ++#define SCTSTRLL5 5 ++#define SCTSTRLL6 6 ++#define SCTSTRLL7 7 ++ ++#define SCTSTRLH _SFR_MEM8(0xFA) ++#define SCTSTRLH0 0 ++#define SCTSTRLH1 1 ++#define SCTSTRLH2 2 ++#define SCTSTRLH3 3 ++#define SCTSTRLH4 4 ++#define SCTSTRLH5 5 ++#define SCTSTRLH6 6 ++#define SCTSTRLH7 7 ++ ++#define SCTSTRHL _SFR_MEM8(0xFB) ++#define SCTSTRHL0 0 ++#define SCTSTRHL1 1 ++#define SCTSTRHL2 2 ++#define SCTSTRHL3 3 ++#define SCTSTRHL4 4 ++#define SCTSTRHL5 5 ++#define SCTSTRHL6 6 ++#define SCTSTRHL7 7 ++ ++#define SCTSTRHH _SFR_MEM8(0xFC) ++#define SCTSTRHH0 0 ++#define SCTSTRHH1 1 ++#define SCTSTRHH2 2 ++#define SCTSTRHH3 3 ++#define SCTSTRHH4 4 ++#define SCTSTRHH5 5 ++#define SCTSTRHH6 6 ++#define SCTSTRHH7 7 ++ ++/* Reserved [0xFD..0x10B] */ ++ ++#define MAFCR0 _SFR_MEM8(0x10C) ++#define MAF0EN 0 ++#define MAF1EN 1 ++#define MAF2EN 2 ++#define MAF3EN 3 ++ ++#define MAFCR1 _SFR_MEM8(0x10D) ++#define AACK_0_I_AM_COORD 0 ++#define AACK_0_SET_PD 1 ++#define AACK_1_I_AM_COORD 2 ++#define AACK_1_SET_PD 3 ++#define AACK_2_I_AM_COORD 4 ++#define AACK_2_SET_PD 5 ++#define AACK_3_I_AM_COORD 6 ++#define AACK_3_SET_PD 7 ++ ++#define MAFSA0L _SFR_MEM8(0x10E) ++#define MAFSA0L0 0 ++#define MAFSA0L1 1 ++#define MAFSA0L2 2 ++#define MAFSA0L3 3 ++#define MAFSA0L4 4 ++#define MAFSA0L5 5 ++#define MAFSA0L6 6 ++#define MAFSA0L7 7 ++ ++#define MAFSA0H _SFR_MEM8(0x10F) ++#define MAFSA0H0 0 ++#define MAFSA0H1 1 ++#define MAFSA0H2 2 ++#define MAFSA0H3 3 ++#define MAFSA0H4 4 ++#define MAFSA0H5 5 ++#define MAFSA0H6 6 ++#define MAFSA0H7 7 ++ ++#define MAFPA0L _SFR_MEM8(0x110) ++#define MAFPA0L0 0 ++#define MAFPA0L1 1 ++#define MAFPA0L2 2 ++#define MAFPA0L3 3 ++#define MAFPA0L4 4 ++#define MAFPA0L5 5 ++#define MAFPA0L6 6 ++#define MAFPA0L7 7 ++ ++#define MAFPA0H _SFR_MEM8(0x111) ++#define MAFPA0H0 0 ++#define MAFPA0H1 1 ++#define MAFPA0H2 2 ++#define MAFPA0H3 3 ++#define MAFPA0H4 4 ++#define MAFPA0H5 5 ++#define MAFPA0H6 6 ++#define MAFPA0H7 7 ++ ++#define MAFSA1L _SFR_MEM8(0x112) ++#define MAFSA1L0 0 ++#define MAFSA1L1 1 ++#define MAFSA1L2 2 ++#define MAFSA1L3 3 ++#define MAFSA1L4 4 ++#define MAFSA1L5 5 ++#define MAFSA1L6 6 ++#define MAFSA1L7 7 ++ ++#define MAFSA1H _SFR_MEM8(0x113) ++#define MAFSA1H0 0 ++#define MAFSA1H1 1 ++#define MAFSA1H2 2 ++#define MAFSA1H3 3 ++#define MAFSA1H4 4 ++#define MAFSA1H5 5 ++#define MAFSA1H6 6 ++#define MAFSA1H7 7 ++ ++#define MAFPA1L _SFR_MEM8(0x114) ++#define MAFPA1L0 0 ++#define MAFPA1L1 1 ++#define MAFPA1L2 2 ++#define MAFPA1L3 3 ++#define MAFPA1L4 4 ++#define MAFPA1L5 5 ++#define MAFPA1L6 6 ++#define MAFPA1L7 7 ++ ++#define MAFPA1H _SFR_MEM8(0x115) ++#define MAFPA1H0 0 ++#define MAFPA1H1 1 ++#define MAFPA1H2 2 ++#define MAFPA1H3 3 ++#define MAFPA1H4 4 ++#define MAFPA1H5 5 ++#define MAFPA1H6 6 ++#define MAFPA1H7 7 ++ ++#define MAFSA2L _SFR_MEM8(0x116) ++#define MAFSA2L0 0 ++#define MAFSA2L1 1 ++#define MAFSA2L2 2 ++#define MAFSA2L3 3 ++#define MAFSA2L4 4 ++#define MAFSA2L5 5 ++#define MAFSA2L6 6 ++#define MAFSA2L7 7 ++ ++#define MAFSA2H _SFR_MEM8(0x117) ++#define MAFSA2H0 0 ++#define MAFSA2H1 1 ++#define MAFSA2H2 2 ++#define MAFSA2H3 3 ++#define MAFSA2H4 4 ++#define MAFSA2H5 5 ++#define MAFSA2H6 6 ++#define MAFSA2H7 7 ++ ++#define MAFPA2L _SFR_MEM8(0x118) ++#define MAFPA2L0 0 ++#define MAFPA2L1 1 ++#define MAFPA2L2 2 ++#define MAFPA2L3 3 ++#define MAFPA2L4 4 ++#define MAFPA2L5 5 ++#define MAFPA2L6 6 ++#define MAFPA2L7 7 ++ ++#define MAFPA2H _SFR_MEM8(0x119) ++#define MAFPA2H0 0 ++#define MAFPA2H1 1 ++#define MAFPA2H2 2 ++#define MAFPA2H3 3 ++#define MAFPA2H4 4 ++#define MAFPA2H5 5 ++#define MAFPA2H6 6 ++#define MAFPA2H7 7 ++ ++#define MAFSA3L _SFR_MEM8(0x11A) ++#define MAFSA3L0 0 ++#define MAFSA3L1 1 ++#define MAFSA3L2 2 ++#define MAFSA3L3 3 ++#define MAFSA3L4 4 ++#define MAFSA3L5 5 ++#define MAFSA3L6 6 ++#define MAFSA3L7 7 ++ ++#define MAFSA3H _SFR_MEM8(0x11B) ++#define MAFSA3H0 0 ++#define MAFSA3H1 1 ++#define MAFSA3H2 2 ++#define MAFSA3H3 3 ++#define MAFSA3H4 4 ++#define MAFSA3H5 5 ++#define MAFSA3H6 6 ++#define MAFSA3H7 7 ++ ++#define MAFPA3L _SFR_MEM8(0x11C) ++#define MAFPA3L0 0 ++#define MAFPA3L1 1 ++#define MAFPA3L2 2 ++#define MAFPA3L3 3 ++#define MAFPA3L4 4 ++#define MAFPA3L5 5 ++#define MAFPA3L6 6 ++#define MAFPA3L7 7 ++ ++#define MAFPA3H _SFR_MEM8(0x11D) ++#define MAFPA3H0 0 ++#define MAFPA3H1 1 ++#define MAFPA3H2 2 ++#define MAFPA3H3 3 ++#define MAFPA3H4 4 ++#define MAFPA3H5 5 ++#define MAFPA3H6 6 ++#define MAFPA3H7 7 ++ ++/* Reserved [0x11E..0x11F] */ ++ ++#define TCCR5A _SFR_MEM8(0x120) ++#define WGM50 0 ++#define WGM51 1 ++#define COM5C0 2 ++#define COM5C1 3 ++#define COM5B0 4 ++#define COM5B1 5 ++#define COM5A0 6 ++#define COM5A1 7 ++ ++#define TCCR5B _SFR_MEM8(0x121) ++#define CS50 0 ++#define CS51 1 ++#define CS52 2 ++#define WGM52 3 ++#define WGM53 4 ++#define ICES5 6 ++#define ICNC5 7 ++ ++#define TCCR5C _SFR_MEM8(0x122) ++#define FOC5C 5 ++#define FOC5B 6 ++#define FOC5A 7 ++ ++/* Reserved [0x123] */ ++ ++/* Combine TCNT5L and TCNT5H */ ++#define TCNT5 _SFR_MEM16(0x124) ++ ++#define TCNT5L _SFR_MEM8(0x124) ++#define TCNT5H _SFR_MEM8(0x125) ++ ++/* Combine ICR5L and ICR5H */ ++#define ICR5 _SFR_MEM16(0x126) ++ ++#define ICR5L _SFR_MEM8(0x126) ++#define ICR5H _SFR_MEM8(0x127) ++ ++/* Combine OCR5AL and OCR5AH */ ++#define OCR5A _SFR_MEM16(0x128) ++ ++#define OCR5AL _SFR_MEM8(0x128) ++#define OCR5AH _SFR_MEM8(0x129) ++ ++/* Combine OCR5BL and OCR5BH */ ++#define OCR5B _SFR_MEM16(0x12A) ++ ++#define OCR5BL _SFR_MEM8(0x12A) ++#define OCR5BH _SFR_MEM8(0x12B) ++ ++/* Combine OCR5CL and OCR5CH */ ++#define OCR5C _SFR_MEM16(0x12C) ++ ++#define OCR5CL _SFR_MEM8(0x12C) ++#define OCR5CH _SFR_MEM8(0x12D) ++ ++/* Reserved [0x12E] */ ++ ++#define LLCR _SFR_MEM8(0x12F) ++#define LLENCAL 0 ++#define LLSHORT 1 ++#define LLTCO 2 ++#define LLCAL 3 ++#define LLCOMP 4 ++#define LLDONE 5 ++ ++#define LLDRL _SFR_MEM8(0x130) ++#define LLDRL0 0 ++#define LLDRL1 1 ++#define LLDRL2 2 ++#define LLDRL3 3 ++ ++#define LLDRH _SFR_MEM8(0x131) ++#define LLDRH0 0 ++#define LLDRH1 1 ++#define LLDRH2 2 ++#define LLDRH3 3 ++#define LLDRH4 4 ++ ++#define DRTRAM3 _SFR_MEM8(0x132) ++#define ENDRT 4 ++#define DRTSWOK 5 ++ ++#define DRTRAM2 _SFR_MEM8(0x133) ++ ++#define DRTRAM1 _SFR_MEM8(0x134) ++ ++#define DRTRAM0 _SFR_MEM8(0x135) ++ ++#define DPDS0 _SFR_MEM8(0x136) ++#define PBDRV0 0 ++#define PBDRV1 1 ++#define PDDRV0 2 ++#define PDDRV1 3 ++#define PEDRV0 4 ++#define PEDRV1 5 ++#define PFDRV0 6 ++#define PFDRV1 7 ++ ++#define DPDS1 _SFR_MEM8(0x137) ++#define PGDRV0 0 ++#define PGDRV1 1 ++ ++#define PARCR _SFR_MEM8(0x138) ++#define PARUFI 0 ++#define PARDFI 1 ++#define PALTU0 2 ++#define PALTU1 3 ++#define PALTU2 4 ++#define PALTD0 5 ++#define PALTD1 6 ++#define PALTD2 7 ++ ++#define TRXPR _SFR_MEM8(0x139) ++#define TRXRST 0 ++#define SLPTR 1 ++ ++/* Reserved [0x13A..0x13B] */ ++ ++#define AES_CTRL _SFR_MEM8(0x13C) ++#define AES_IM 2 ++#define AES_DIR 3 ++#define AES_MODE 5 ++#define AES_REQUEST 7 ++ ++#define AES_STATUS _SFR_MEM8(0x13D) ++#define AES_DONE 0 ++#define AES_ER 7 ++ ++#define AES_STATE _SFR_MEM8(0x13E) ++#define AES_STATE0 0 ++#define AES_STATE1 1 ++#define AES_STATE2 2 ++#define AES_STATE3 3 ++#define AES_STATE4 4 ++#define AES_STATE5 5 ++#define AES_STATE6 6 ++#define AES_STATE7 7 ++ ++#define AES_KEY _SFR_MEM8(0x13F) ++#define AES_KEY0 0 ++#define AES_KEY1 1 ++#define AES_KEY2 2 ++#define AES_KEY3 3 ++#define AES_KEY4 4 ++#define AES_KEY5 5 ++#define AES_KEY6 6 ++#define AES_KEY7 7 ++ ++/* Reserved [0x140] */ ++ ++#define TRX_STATUS _SFR_MEM8(0x141) ++#define TRX_STATUS0 0 ++#define TRX_STATUS1 1 ++#define TRX_STATUS2 2 ++#define TRX_STATUS3 3 ++#define TRX_STATUS4 4 ++#define TST_STATUS 5 ++#define CCA_STATUS 6 ++#define CCA_DONE 7 ++ ++#define TRX_STATE _SFR_MEM8(0x142) ++#define TRX_CMD0 0 ++#define TRX_CMD1 1 ++#define TRX_CMD2 2 ++#define TRX_CMD3 3 ++#define TRX_CMD4 4 ++#define TRAC_STATUS0 5 ++#define TRAC_STATUS1 6 ++#define TRAC_STATUS2 7 ++ ++#define TRX_CTRL_0 _SFR_MEM8(0x143) ++#define PMU_IF_INV 4 ++#define PMU_START 5 ++#define PMU_EN 6 ++#define Res7 7 ++ ++#define TRX_CTRL_1 _SFR_MEM8(0x144) ++#define PLL_TX_FLT 4 ++#define TX_AUTO_CRC_ON 5 ++#define IRQ_2_EXT_EN 6 ++#define PA_EXT_EN 7 ++ ++#define PHY_TX_PWR _SFR_MEM8(0x145) ++#define TX_PWR0 0 ++#define TX_PWR1 1 ++#define TX_PWR2 2 ++#define TX_PWR3 3 ++ ++#define PHY_RSSI _SFR_MEM8(0x146) ++#define RSSI0 0 ++#define RSSI1 1 ++#define RSSI2 2 ++#define RSSI3 3 ++#define RSSI4 4 ++#define RND_VALUE0 5 ++#define RND_VALUE1 6 ++#define RX_CRC_VALID 7 ++ ++#define PHY_ED_LEVEL _SFR_MEM8(0x147) ++#define ED_LEVEL0 0 ++#define ED_LEVEL1 1 ++#define ED_LEVEL2 2 ++#define ED_LEVEL3 3 ++#define ED_LEVEL4 4 ++#define ED_LEVEL5 5 ++#define ED_LEVEL6 6 ++#define ED_LEVEL7 7 ++ ++#define PHY_CC_CCA _SFR_MEM8(0x148) ++#define CHANNEL0 0 ++#define CHANNEL1 1 ++#define CHANNEL2 2 ++#define CHANNEL3 3 ++#define CHANNEL4 4 ++#define CCA_MODE0 5 ++#define CCA_MODE1 6 ++#define CCA_REQUEST 7 ++ ++#define CCA_THRES _SFR_MEM8(0x149) ++#define CCA_ED_THRES0 0 ++#define CCA_ED_THRES1 1 ++#define CCA_ED_THRES2 2 ++#define CCA_ED_THRES3 3 ++#define CCA_CS_THRES0 4 ++#define CCA_CS_THRES1 5 ++#define CCA_CS_THRES2 6 ++#define CCA_CS_THRES3 7 ++ ++#define RX_CTRL _SFR_MEM8(0x14A) ++#define PDT_THRES0 0 ++#define PDT_THRES1 1 ++#define PDT_THRES2 2 ++#define PDT_THRES3 3 ++ ++#define SFD_VALUE _SFR_MEM8(0x14B) ++#define SFD_VALUE0 0 ++#define SFD_VALUE1 1 ++#define SFD_VALUE2 2 ++#define SFD_VALUE3 3 ++#define SFD_VALUE4 4 ++#define SFD_VALUE5 5 ++#define SFD_VALUE6 6 ++#define SFD_VALUE7 7 ++ ++#define TRX_CTRL_2 _SFR_MEM8(0x14C) ++#define OQPSK_DATA_RATE0 0 ++#define OQPSK_DATA_RATE1 1 ++#define RX_SAFE_MODE 7 ++ ++#define ANT_DIV _SFR_MEM8(0x14D) ++#define ANT_CTRL0 0 ++#define ANT_CTRL1 1 ++#define ANT_EXT_SW_EN 2 ++#define ANT_DIV_EN 3 ++#define ANT_SEL 7 ++ ++#define IRQ_MASK _SFR_MEM8(0x14E) ++#define PLL_LOCK_EN 0 ++#define PLL_UNLOCK_EN 1 ++#define RX_START_EN 2 ++#define RX_END_EN 3 ++#define CCA_ED_DONE_EN 4 ++#define AMI_EN 5 ++#define TX_END_EN 6 ++#define AWAKE_EN 7 ++ ++#define IRQ_STATUS _SFR_MEM8(0x14F) ++#define PLL_LOCK 0 ++#define PLL_UNLOCK 1 ++#define RX_START 2 ++#define RX_END 3 ++#define CCA_ED_DONE 4 ++#define AMI 5 ++#define TX_END 6 ++#define AWAKE 7 ++ ++#define VREG_CTRL _SFR_MEM8(0x150) ++#define DVDD_OK 2 ++#define DVREG_EXT 3 ++#define AVDD_OK 6 ++#define AVREG_EXT 7 ++ ++#define BATMON _SFR_MEM8(0x151) ++#define BATMON_VTH0 0 ++#define BATMON_VTH1 1 ++#define BATMON_VTH2 2 ++#define BATMON_VTH3 3 ++#define BATMON_HR 4 ++#define BATMON_OK 5 ++#define BAT_LOW_EN 6 ++#define BAT_LOW 7 ++ ++#define XOSC_CTRL _SFR_MEM8(0x152) ++#define XTAL_TRIM0 0 ++#define XTAL_TRIM1 1 ++#define XTAL_TRIM2 2 ++#define XTAL_TRIM3 3 ++#define XTAL_MODE0 4 ++#define XTAL_MODE1 5 ++#define XTAL_MODE2 6 ++#define XTAL_MODE3 7 ++ ++#define CC_CTRL_0 _SFR_MEM8(0x153) ++#define CC_NUMBER0 0 ++#define CC_NUMBER1 1 ++#define CC_NUMBER2 2 ++#define CC_NUMBER3 3 ++#define CC_NUMBER4 4 ++#define CC_NUMBER5 5 ++#define CC_NUMBER6 6 ++#define CC_NUMBER7 7 ++ ++#define CC_CTRL_1 _SFR_MEM8(0x154) ++#define CC_BAND0 0 ++#define CC_BAND1 1 ++#define CC_BAND2 2 ++#define CC_BAND3 3 ++ ++#define RX_SYN _SFR_MEM8(0x155) ++#define RX_PDT_LEVEL0 0 ++#define RX_PDT_LEVEL1 1 ++#define RX_PDT_LEVEL2 2 ++#define RX_PDT_LEVEL3 3 ++#define RX_OVERRIDE 6 ++#define RX_PDT_DIS 7 ++ ++#define TRX_RPC _SFR_MEM8(0x156) ++#define XAH_RPC_EN 0 ++#define IPAN_RPC_EN 1 ++#define PLL_RPC_EN 3 ++#define PDT_RPC_EN 4 ++#define RX_RPC_EN 5 ++#define RX_RPC_CTRL0 6 ++#define RX_RPC_CTRL1 7 ++ ++#define XAH_CTRL_1 _SFR_MEM8(0x157) ++#define AACK_PROM_MODE 1 ++#define AACK_ACK_TIME 2 ++#define AACK_UPLD_RES_FT 4 ++#define AACK_FLTR_RES_FT 5 ++ ++#define FTN_CTRL _SFR_MEM8(0x158) ++#define FTN_START 7 ++ ++/* Reserved [0x159] */ ++ ++#define PLL_CF _SFR_MEM8(0x15A) ++#define PLL_CF_START 7 ++ ++#define PLL_DCU _SFR_MEM8(0x15B) ++#define PLL_DCU_START 7 ++ ++#define PART_NUM _SFR_MEM8(0x15C) ++#define PART_NUM0 0 ++#define PART_NUM1 1 ++#define PART_NUM2 2 ++#define PART_NUM3 3 ++#define PART_NUM4 4 ++#define PART_NUM5 5 ++#define PART_NUM6 6 ++#define PART_NUM7 7 ++ ++#define VERSION_NUM _SFR_MEM8(0x15D) ++#define VERSION_NUM0 0 ++#define VERSION_NUM1 1 ++#define VERSION_NUM2 2 ++#define VERSION_NUM3 3 ++#define VERSION_NUM4 4 ++#define VERSION_NUM5 5 ++#define VERSION_NUM6 6 ++#define VERSION_NUM7 7 ++ ++#define MAN_ID_0 _SFR_MEM8(0x15E) ++#define MAN_ID_00 0 ++#define MAN_ID_01 1 ++#define MAN_ID_02 2 ++#define MAN_ID_03 3 ++#define MAN_ID_04 4 ++#define MAN_ID_05 5 ++#define MAN_ID_06 6 ++#define MAN_ID_07 7 ++ ++#define MAN_ID_1 _SFR_MEM8(0x15F) ++#define MAN_ID_10 0 ++#define MAN_ID_11 1 ++#define MAN_ID_12 2 ++#define MAN_ID_13 3 ++#define MAN_ID_14 4 ++#define MAN_ID_15 5 ++#define MAN_ID_16 6 ++#define MAN_ID_17 7 ++ ++#define SHORT_ADDR_0 _SFR_MEM8(0x160) ++#define SHORT_ADDR_00 0 ++#define SHORT_ADDR_01 1 ++#define SHORT_ADDR_02 2 ++#define SHORT_ADDR_03 3 ++#define SHORT_ADDR_04 4 ++#define SHORT_ADDR_05 5 ++#define SHORT_ADDR_06 6 ++#define SHORT_ADDR_07 7 ++ ++#define SHORT_ADDR_1 _SFR_MEM8(0x161) ++#define SHORT_ADDR_10 0 ++#define SHORT_ADDR_11 1 ++#define SHORT_ADDR_12 2 ++#define SHORT_ADDR_13 3 ++#define SHORT_ADDR_14 4 ++#define SHORT_ADDR_15 5 ++#define SHORT_ADDR_16 6 ++#define SHORT_ADDR_17 7 ++ ++#define PAN_ID_0 _SFR_MEM8(0x162) ++#define PAN_ID_00 0 ++#define PAN_ID_01 1 ++#define PAN_ID_02 2 ++#define PAN_ID_03 3 ++#define PAN_ID_04 4 ++#define PAN_ID_05 5 ++#define PAN_ID_06 6 ++#define PAN_ID_07 7 ++ ++#define PAN_ID_1 _SFR_MEM8(0x163) ++#define PAN_ID_10 0 ++#define PAN_ID_11 1 ++#define PAN_ID_12 2 ++#define PAN_ID_13 3 ++#define PAN_ID_14 4 ++#define PAN_ID_15 5 ++#define PAN_ID_16 6 ++#define PAN_ID_17 7 ++ ++#define IEEE_ADDR_0 _SFR_MEM8(0x164) ++#define IEEE_ADDR_00 0 ++#define IEEE_ADDR_01 1 ++#define IEEE_ADDR_02 2 ++#define IEEE_ADDR_03 3 ++#define IEEE_ADDR_04 4 ++#define IEEE_ADDR_05 5 ++#define IEEE_ADDR_06 6 ++#define IEEE_ADDR_07 7 ++ ++#define IEEE_ADDR_1 _SFR_MEM8(0x165) ++#define IEEE_ADDR_10 0 ++#define IEEE_ADDR_11 1 ++#define IEEE_ADDR_12 2 ++#define IEEE_ADDR_13 3 ++#define IEEE_ADDR_14 4 ++#define IEEE_ADDR_15 5 ++#define IEEE_ADDR_16 6 ++#define IEEE_ADDR_17 7 ++ ++#define IEEE_ADDR_2 _SFR_MEM8(0x166) ++#define IEEE_ADDR_20 0 ++#define IEEE_ADDR_21 1 ++#define IEEE_ADDR_22 2 ++#define IEEE_ADDR_23 3 ++#define IEEE_ADDR_24 4 ++#define IEEE_ADDR_25 5 ++#define IEEE_ADDR_26 6 ++#define IEEE_ADDR_27 7 ++ ++#define IEEE_ADDR_3 _SFR_MEM8(0x167) ++#define IEEE_ADDR_30 0 ++#define IEEE_ADDR_31 1 ++#define IEEE_ADDR_32 2 ++#define IEEE_ADDR_33 3 ++#define IEEE_ADDR_34 4 ++#define IEEE_ADDR_35 5 ++#define IEEE_ADDR_36 6 ++#define IEEE_ADDR_37 7 ++ ++#define IEEE_ADDR_4 _SFR_MEM8(0x168) ++#define IEEE_ADDR_40 0 ++#define IEEE_ADDR_41 1 ++#define IEEE_ADDR_42 2 ++#define IEEE_ADDR_43 3 ++#define IEEE_ADDR_44 4 ++#define IEEE_ADDR_45 5 ++#define IEEE_ADDR_46 6 ++#define IEEE_ADDR_47 7 ++ ++#define IEEE_ADDR_5 _SFR_MEM8(0x169) ++#define IEEE_ADDR_50 0 ++#define IEEE_ADDR_51 1 ++#define IEEE_ADDR_52 2 ++#define IEEE_ADDR_53 3 ++#define IEEE_ADDR_54 4 ++#define IEEE_ADDR_55 5 ++#define IEEE_ADDR_56 6 ++#define IEEE_ADDR_57 7 ++ ++#define IEEE_ADDR_6 _SFR_MEM8(0x16A) ++#define IEEE_ADDR_60 0 ++#define IEEE_ADDR_61 1 ++#define IEEE_ADDR_62 2 ++#define IEEE_ADDR_63 3 ++#define IEEE_ADDR_64 4 ++#define IEEE_ADDR_65 5 ++#define IEEE_ADDR_66 6 ++#define IEEE_ADDR_67 7 ++ ++#define IEEE_ADDR_7 _SFR_MEM8(0x16B) ++#define IEEE_ADDR_70 0 ++#define IEEE_ADDR_71 1 ++#define IEEE_ADDR_72 2 ++#define IEEE_ADDR_73 3 ++#define IEEE_ADDR_74 4 ++#define IEEE_ADDR_75 5 ++#define IEEE_ADDR_76 6 ++#define IEEE_ADDR_77 7 ++ ++#define XAH_CTRL_0 _SFR_MEM8(0x16C) ++#define SLOTTED_OPERATION 0 ++#define MAX_CSMA_RETRIES0 1 ++#define MAX_CSMA_RETRIES1 2 ++#define MAX_CSMA_RETRIES2 3 ++#define MAX_FRAME_RETRIES0 4 ++#define MAX_FRAME_RETRIES1 5 ++#define MAX_FRAME_RETRIES2 6 ++#define MAX_FRAME_RETRIES3 7 ++ ++#define CSMA_SEED_0 _SFR_MEM8(0x16D) ++#define CSMA_SEED_00 0 ++#define CSMA_SEED_01 1 ++#define CSMA_SEED_02 2 ++#define CSMA_SEED_03 3 ++#define CSMA_SEED_04 4 ++#define CSMA_SEED_05 5 ++#define CSMA_SEED_06 6 ++#define CSMA_SEED_07 7 ++ ++#define CSMA_SEED_1 _SFR_MEM8(0x16E) ++#define CSMA_SEED_10 0 ++#define CSMA_SEED_11 1 ++#define CSMA_SEED_12 2 ++#define AACK_I_AM_COORD 3 ++#define AACK_DIS_ACK 4 ++#define AACK_SET_PD 5 ++#define AACK_FVN_MODE0 6 ++#define AACK_FVN_MODE1 7 ++ ++#define CSMA_BE _SFR_MEM8(0x16F) ++#define MIN_BE0 0 ++#define MIN_BE1 1 ++#define MIN_BE2 2 ++#define MIN_BE3 3 ++#define MAX_BE0 4 ++#define MAX_BE1 5 ++#define MAX_BE2 6 ++#define MAX_BE3 7 ++ ++/* Reserved [0x170..0x175] */ ++ ++#define TST_CTRL_DIGI _SFR_MEM8(0x176) ++#define TST_CTRL_DIG0 0 ++#define TST_CTRL_DIG1 1 ++#define TST_CTRL_DIG2 2 ++#define TST_CTRL_DIG3 3 ++ ++/* Reserved [0x177..0x17A] */ ++ ++#define TST_RX_LENGTH _SFR_MEM8(0x17B) ++#define RX_LENGTH0 0 ++#define RX_LENGTH1 1 ++#define RX_LENGTH2 2 ++#define RX_LENGTH3 3 ++#define RX_LENGTH4 4 ++#define RX_LENGTH5 5 ++#define RX_LENGTH6 6 ++#define RX_LENGTH7 7 ++ ++/* Reserved [0x17C..0x17F] */ ++ ++#define TRXFBST _SFR_MEM8(0x180) ++ ++/* Reserved [0x181..0x1FE] */ ++ ++#define TRXFBEND _SFR_MEM8(0x1FF) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect _VECTOR(3) ++#define INT2_vect_num 3 ++ ++/* External Interrupt Request 3 */ ++#define INT3_vect _VECTOR(4) ++#define INT3_vect_num 4 ++ ++/* External Interrupt Request 4 */ ++#define INT4_vect _VECTOR(5) ++#define INT4_vect_num 5 ++ ++/* External Interrupt Request 5 */ ++#define INT5_vect _VECTOR(6) ++#define INT5_vect_num 6 ++ ++/* External Interrupt Request 6 */ ++#define INT6_vect _VECTOR(7) ++#define INT6_vect_num 7 ++ ++/* External Interrupt Request 7 */ ++#define INT7_vect _VECTOR(8) ++#define INT7_vect_num 8 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(9) ++#define PCINT0_vect_num 9 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(10) ++#define PCINT1_vect_num 10 ++ ++/* Pin Change Interrupt Request 2 */ ++#define PCINT2_vect _VECTOR(11) ++#define PCINT2_vect_num 11 ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect _VECTOR(12) ++#define WDT_vect_num 12 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPA_vect _VECTOR(13) ++#define TIMER2_COMPA_vect_num 13 ++ ++/* Timer/Counter2 Compare Match B */ ++#define TIMER2_COMPB_vect _VECTOR(14) ++#define TIMER2_COMPB_vect_num 14 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(15) ++#define TIMER2_OVF_vect_num 15 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(16) ++#define TIMER1_CAPT_vect_num 16 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(17) ++#define TIMER1_COMPA_vect_num 17 ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(18) ++#define TIMER1_COMPB_vect_num 18 ++ ++/* Timer/Counter1 Compare Match C */ ++#define TIMER1_COMPC_vect _VECTOR(19) ++#define TIMER1_COMPC_vect_num 19 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(20) ++#define TIMER1_OVF_vect_num 20 ++ ++/* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPA_vect _VECTOR(21) ++#define TIMER0_COMPA_vect_num 21 ++ ++/* Timer/Counter0 Compare Match B */ ++#define TIMER0_COMPB_vect _VECTOR(22) ++#define TIMER0_COMPB_vect_num 22 ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(23) ++#define TIMER0_OVF_vect_num 23 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(24) ++#define SPI_STC_vect_num 24 ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect _VECTOR(25) ++#define USART0_RX_vect_num 25 ++ ++/* USART0 Data register Empty */ ++#define USART0_UDRE_vect _VECTOR(26) ++#define USART0_UDRE_vect_num 26 ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect _VECTOR(27) ++#define USART0_TX_vect_num 27 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(28) ++#define ANALOG_COMP_vect_num 28 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(29) ++#define ADC_vect_num 29 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(30) ++#define EE_READY_vect_num 30 ++ ++/* Timer/Counter3 Capture Event */ ++#define TIMER3_CAPT_vect _VECTOR(31) ++#define TIMER3_CAPT_vect_num 31 ++ ++/* Timer/Counter3 Compare Match A */ ++#define TIMER3_COMPA_vect _VECTOR(32) ++#define TIMER3_COMPA_vect_num 32 ++ ++/* Timer/Counter3 Compare Match B */ ++#define TIMER3_COMPB_vect _VECTOR(33) ++#define TIMER3_COMPB_vect_num 33 ++ ++/* Timer/Counter3 Compare Match C */ ++#define TIMER3_COMPC_vect _VECTOR(34) ++#define TIMER3_COMPC_vect_num 34 ++ ++/* Timer/Counter3 Overflow */ ++#define TIMER3_OVF_vect _VECTOR(35) ++#define TIMER3_OVF_vect_num 35 ++ ++/* USART1, Rx Complete */ ++#define USART1_RX_vect _VECTOR(36) ++#define USART1_RX_vect_num 36 ++ ++/* USART1 Data register Empty */ ++#define USART1_UDRE_vect _VECTOR(37) ++#define USART1_UDRE_vect_num 37 ++ ++/* USART1, Tx Complete */ ++#define USART1_TX_vect _VECTOR(38) ++#define USART1_TX_vect_num 38 ++ ++/* 2-wire Serial Interface */ ++#define TWI_vect _VECTOR(39) ++#define TWI_vect_num 39 ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect _VECTOR(40) ++#define SPM_READY_vect_num 40 ++ ++/* Timer/Counter4 Capture Event */ ++#define TIMER4_CAPT_vect _VECTOR(41) ++#define TIMER4_CAPT_vect_num 41 ++ ++/* Timer/Counter4 Compare Match A */ ++#define TIMER4_COMPA_vect _VECTOR(42) ++#define TIMER4_COMPA_vect_num 42 ++ ++/* Timer/Counter4 Compare Match B */ ++#define TIMER4_COMPB_vect _VECTOR(43) ++#define TIMER4_COMPB_vect_num 43 ++ ++/* Timer/Counter4 Compare Match C */ ++#define TIMER4_COMPC_vect _VECTOR(44) ++#define TIMER4_COMPC_vect_num 44 ++ ++/* Timer/Counter4 Overflow */ ++#define TIMER4_OVF_vect _VECTOR(45) ++#define TIMER4_OVF_vect_num 45 ++ ++/* Timer/Counter5 Capture Event */ ++#define TIMER5_CAPT_vect _VECTOR(46) ++#define TIMER5_CAPT_vect_num 46 ++ ++/* Timer/Counter5 Compare Match A */ ++#define TIMER5_COMPA_vect _VECTOR(47) ++#define TIMER5_COMPA_vect_num 47 ++ ++/* Timer/Counter5 Compare Match B */ ++#define TIMER5_COMPB_vect _VECTOR(48) ++#define TIMER5_COMPB_vect_num 48 ++ ++/* Timer/Counter5 Compare Match C */ ++#define TIMER5_COMPC_vect _VECTOR(49) ++#define TIMER5_COMPC_vect_num 49 ++ ++/* Timer/Counter5 Overflow */ ++#define TIMER5_OVF_vect _VECTOR(50) ++#define TIMER5_OVF_vect_num 50 ++ ++/* TRX24 - PLL lock interrupt */ ++#define TRX24_PLL_LOCK_vect _VECTOR(57) ++#define TRX24_PLL_LOCK_vect_num 57 ++ ++/* TRX24 - PLL unlock interrupt */ ++#define TRX24_PLL_UNLOCK_vect _VECTOR(58) ++#define TRX24_PLL_UNLOCK_vect_num 58 ++ ++/* TRX24 - Receive start interrupt */ ++#define TRX24_RX_START_vect _VECTOR(59) ++#define TRX24_RX_START_vect_num 59 ++ ++/* TRX24 - RX_END interrupt */ ++#define TRX24_RX_END_vect _VECTOR(60) ++#define TRX24_RX_END_vect_num 60 ++ ++/* TRX24 - CCA/ED done interrupt */ ++#define TRX24_CCA_ED_DONE_vect _VECTOR(61) ++#define TRX24_CCA_ED_DONE_vect_num 61 ++ ++/* TRX24 - XAH - AMI */ ++#define TRX24_XAH_AMI_vect _VECTOR(62) ++#define TRX24_XAH_AMI_vect_num 62 ++ ++/* TRX24 - TX_END interrupt */ ++#define TRX24_TX_END_vect _VECTOR(63) ++#define TRX24_TX_END_vect_num 63 ++ ++/* TRX24 AWAKE - tranceiver is reaching state TRX_OFF */ ++#define TRX24_AWAKE_vect _VECTOR(64) ++#define TRX24_AWAKE_vect_num 64 ++ ++/* Symbol counter - compare match 1 interrupt */ ++#define SCNT_CMP1_vect _VECTOR(65) ++#define SCNT_CMP1_vect_num 65 ++ ++/* Symbol counter - compare match 2 interrupt */ ++#define SCNT_CMP2_vect _VECTOR(66) ++#define SCNT_CMP2_vect_num 66 ++ ++/* Symbol counter - compare match 3 interrupt */ ++#define SCNT_CMP3_vect _VECTOR(67) ++#define SCNT_CMP3_vect_num 67 ++ ++/* Symbol counter - overflow interrupt */ ++#define SCNT_OVFL_vect _VECTOR(68) ++#define SCNT_OVFL_vect_num 68 ++ ++/* Symbol counter - backoff interrupt */ ++#define SCNT_BACKOFF_vect _VECTOR(69) ++#define SCNT_BACKOFF_vect_num 69 ++ ++/* AES engine ready interrupt */ ++#define AES_READY_vect _VECTOR(70) ++#define AES_READY_vect_num 70 ++ ++/* Battery monitor indicates supply voltage below threshold */ ++#define BAT_LOW_vect _VECTOR(71) ++#define BAT_LOW_vect_num 71 ++ ++/* TRX24 TX start interrupt */ ++#define TRX24_TX_START_vect _VECTOR(72) ++#define TRX24_TX_START_vect_num 72 ++ ++/* Address match interrupt of address filter 0 */ ++#define TRX24_AMI0_vect _VECTOR(73) ++#define TRX24_AMI0_vect_num 73 ++ ++/* Address match interrupt of address filter 1 */ ++#define TRX24_AMI1_vect _VECTOR(74) ++#define TRX24_AMI1_vect_num 74 ++ ++/* Address match interrupt of address filter 2 */ ++#define TRX24_AMI2_vect _VECTOR(75) ++#define TRX24_AMI2_vect_num 75 ++ ++/* Address match interrupt of address filter 3 */ ++#define TRX24_AMI3_vect _VECTOR(76) ++#define TRX24_AMI3_vect_num 76 ++ ++#define _VECTORS_SIZE 308 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 256 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0xFFFF ++#define RAMSTART 0x0200 ++#define RAMSIZE 8192 ++#define RAMEND 0x21FF ++#define E2START 0 ++#define E2SIZE 2048 ++#define E2PAGESIZE 8 ++#define E2END 0x07FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL_SUT0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL_SUT1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL_SUT2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL_SUT3 (unsigned char)~_BV(3) ++#define FUSE_CKSEL_SUT4 (unsigned char)~_BV(4) ++#define FUSE_CKSEL_SUT5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0xA6 ++#define SIGNATURE_2 0x02 ++ ++ ++#endif /* #ifdef _AVR_ATMEGA64RFR2_H_INCLUDED */ ++ +diff --git a/include/avr/iom8.h b/include/avr/iom8.h +index 5e68ba2..332dabb 100644 +--- a/include/avr/iom8.h ++++ b/include/avr/iom8.h +@@ -1,660 +1,660 @@ +-/* Copyright (c) 2002, Marek Michalkiewicz +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom8.h 2235 2011-03-17 04:13:14Z arcanum $ */ +- +-/* avr/iom8.h - definitions for ATmega8 */ +- +-#ifndef _AVR_IOM8_H_ +-#define _AVR_IOM8_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom8.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ +-#define TWBR _SFR_IO8(0x00) +-#define TWSR _SFR_IO8(0x01) +-#define TWAR _SFR_IO8(0x02) +-#define TWDR _SFR_IO8(0x03) +- +-/* ADC */ +-#define ADCW _SFR_IO16(0x04) +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x04) +-#endif +-#define ADCL _SFR_IO8(0x04) +-#define ADCH _SFR_IO8(0x05) +-#define ADCSR _SFR_IO8(0x06) +-#define ADCSRA _SFR_IO8(0x06) /* Changed in 2486H-AVR-09/02 */ +-#define ADMUX _SFR_IO8(0x07) +- +-/* analog comparator */ +-#define ACSR _SFR_IO8(0x08) +- +-/* USART */ +-#define UBRRL _SFR_IO8(0x09) +-#define UCSRB _SFR_IO8(0x0A) +-#define UCSRA _SFR_IO8(0x0B) +-#define UDR _SFR_IO8(0x0C) +- +-/* SPI */ +-#define SPCR _SFR_IO8(0x0D) +-#define SPSR _SFR_IO8(0x0E) +-#define SPDR _SFR_IO8(0x0F) +- +-/* Port D */ +-#define PIND _SFR_IO8(0x10) +-#define DDRD _SFR_IO8(0x11) +-#define PORTD _SFR_IO8(0x12) +- +-/* Port C */ +-#define PINC _SFR_IO8(0x13) +-#define DDRC _SFR_IO8(0x14) +-#define PORTC _SFR_IO8(0x15) +- +-/* Port B */ +-#define PINB _SFR_IO8(0x16) +-#define DDRB _SFR_IO8(0x17) +-#define PORTB _SFR_IO8(0x18) +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO16(0x1E) +-#define EEARL _SFR_IO8(0x1E) +-#define EEARH _SFR_IO8(0x1F) +- +-#define UCSRC _SFR_IO8(0x20) +-#define UBRRH _SFR_IO8(0x20) +- +-#define WDTCR _SFR_IO8(0x21) +-#define ASSR _SFR_IO8(0x22) +- +-/* Timer 2 */ +-#define OCR2 _SFR_IO8(0x23) +-#define TCNT2 _SFR_IO8(0x24) +-#define TCCR2 _SFR_IO8(0x25) +- +-/* Timer 1 */ +-#define ICR1 _SFR_IO16(0x26) +-#define ICR1L _SFR_IO8(0x26) +-#define ICR1H _SFR_IO8(0x27) +-#define OCR1B _SFR_IO16(0x28) +-#define OCR1BL _SFR_IO8(0x28) +-#define OCR1BH _SFR_IO8(0x29) +-#define OCR1A _SFR_IO16(0x2A) +-#define OCR1AL _SFR_IO8(0x2A) +-#define OCR1AH _SFR_IO8(0x2B) +-#define TCNT1 _SFR_IO16(0x2C) +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1H _SFR_IO8(0x2D) +-#define TCCR1B _SFR_IO8(0x2E) +-#define TCCR1A _SFR_IO8(0x2F) +- +-#define SFIOR _SFR_IO8(0x30) +- +-#define OSCCAL _SFR_IO8(0x31) +- +-/* Timer 0 */ +-#define TCNT0 _SFR_IO8(0x32) +-#define TCCR0 _SFR_IO8(0x33) +- +-#define MCUCSR _SFR_IO8(0x34) +-#define MCUSR _SFR_IO8(0x34) /* Defined as an alias for MCUCSR. */ +- +-#define MCUCR _SFR_IO8(0x35) +- +-#define TWCR _SFR_IO8(0x36) +- +-#define SPMCR _SFR_IO8(0x37) +- +-#define TIFR _SFR_IO8(0x38) +-#define TIMSK _SFR_IO8(0x39) +- +-#define GIFR _SFR_IO8(0x3A) +-#define GIMSK _SFR_IO8(0x3B) +-#define GICR _SFR_IO8(0x3B) /* Changed in 2486H-AVR-09/02 */ +- +-/* 0x3C reserved (OCR0?) */ +- +-/* 0x3D..0x3E SP */ +- +-/* 0x3F SREG */ +- +-/* Interrupt vectors */ +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt Request 1 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +-#define SIG_INTERRUPT1 _VECTOR(2) +- +-/* Timer/Counter2 Compare Match */ +-#define TIMER2_COMP_vect_num 3 +-#define TIMER2_COMP_vect _VECTOR(3) +-#define SIG_OUTPUT_COMPARE2 _VECTOR(3) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 4 +-#define TIMER2_OVF_vect _VECTOR(4) +-#define SIG_OVERFLOW2 _VECTOR(4) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 5 +-#define TIMER1_CAPT_vect _VECTOR(5) +-#define SIG_INPUT_CAPTURE1 _VECTOR(5) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 6 +-#define TIMER1_COMPA_vect _VECTOR(6) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(6) +- +-/* Timer/Counter1 Compare Match B */ +-#define TIMER1_COMPB_vect_num 7 +-#define TIMER1_COMPB_vect _VECTOR(7) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(7) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 8 +-#define TIMER1_OVF_vect _VECTOR(8) +-#define SIG_OVERFLOW1 _VECTOR(8) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 9 +-#define TIMER0_OVF_vect _VECTOR(9) +-#define SIG_OVERFLOW0 _VECTOR(9) +- +-/* Serial Transfer Complete */ +-#define SPI_STC_vect_num 10 +-#define SPI_STC_vect _VECTOR(10) +-#define SIG_SPI _VECTOR(10) +- +-/* USART, Rx Complete */ +-#define USART_RXC_vect_num 11 +-#define USART_RXC_vect _VECTOR(11) +-#define SIG_UART_RECV _VECTOR(11) +- +-/* USART Data Register Empty */ +-#define USART_UDRE_vect_num 12 +-#define USART_UDRE_vect _VECTOR(12) +-#define SIG_UART_DATA _VECTOR(12) +- +-/* USART, Tx Complete */ +-#define USART_TXC_vect_num 13 +-#define USART_TXC_vect _VECTOR(13) +-#define SIG_UART_TRANS _VECTOR(13) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 14 +-#define ADC_vect _VECTOR(14) +-#define SIG_ADC _VECTOR(14) +- +-/* EEPROM Ready */ +-#define EE_RDY_vect_num 15 +-#define EE_RDY_vect _VECTOR(15) +-#define SIG_EEPROM_READY _VECTOR(15) +- +-/* Analog Comparator */ +-#define ANA_COMP_vect_num 16 +-#define ANA_COMP_vect _VECTOR(16) +-#define SIG_COMPARATOR _VECTOR(16) +- +-/* 2-wire Serial Interface */ +-#define TWI_vect_num 17 +-#define TWI_vect _VECTOR(17) +-#define SIG_2WIRE_SERIAL _VECTOR(17) +- +-/* Store Program Memory Ready */ +-#define SPM_RDY_vect_num 18 +-#define SPM_RDY_vect _VECTOR(18) +-#define SIG_SPM_READY _VECTOR(18) +- +-#define _VECTORS_SIZE 38 +- +-/* Bit numbers */ +- +-/* GIMSK / GICR */ +-#define INT1 7 +-#define INT0 6 +-#define IVSEL 1 +-#define IVCE 0 +- +-/* GIFR */ +-#define INTF1 7 +-#define INTF0 6 +- +-/* TIMSK */ +-#define OCIE2 7 +-#define TOIE2 6 +-#define TICIE1 5 +-#define OCIE1A 4 +-#define OCIE1B 3 +-#define TOIE1 2 +-/* bit 1 reserved (OCIE0?) */ +-#define TOIE0 0 +- +-/* TIFR */ +-#define OCF2 7 +-#define TOV2 6 +-#define ICF1 5 +-#define OCF1A 4 +-#define OCF1B 3 +-#define TOV1 2 +-/* bit 1 reserved (OCF0?) */ +-#define TOV0 0 +- +-/* SPMCR */ +-#define SPMIE 7 +-#define RWWSB 6 +-/* bit 5 reserved */ +-#define RWWSRE 4 +-#define BLBSET 3 +-#define PGWRT 2 +-#define PGERS 1 +-#define SPMEN 0 +- +-/* TWCR */ +-#define TWINT 7 +-#define TWEA 6 +-#define TWSTA 5 +-#define TWSTO 4 +-#define TWWC 3 +-#define TWEN 2 +-/* bit 1 reserved (TWI_TST?) */ +-#define TWIE 0 +- +-/* TWAR */ +-#define TWA6 7 +-#define TWA5 6 +-#define TWA4 5 +-#define TWA3 4 +-#define TWA2 3 +-#define TWA1 2 +-#define TWA0 1 +-#define TWGCE 0 +- +-/* TWSR */ +-#define TWS7 7 +-#define TWS6 6 +-#define TWS5 5 +-#define TWS4 4 +-#define TWS3 3 +-/* bit 2 reserved */ +-#define TWPS1 1 +-#define TWPS0 0 +- +-/* MCUCR */ +-#define SE 7 +-#define SM2 6 +-#define SM1 5 +-#define SM0 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-/* MCUCSR */ +-/* bits 7-4 reserved */ +-#define WDRF 3 +-#define BORF 2 +-#define EXTRF 1 +-#define PORF 0 +- +-/* +- The ADHSM bit has been removed from all documentation, +- as being not needed at all since the comparator has proven +- to be fast enough even without feeding it more power. +-*/ +- +-/* SFIOR */ +-/* bits 7-5 reserved */ +-#define ACME 3 +-#define PUD 2 +-#define PSR2 1 +-#define PSR10 0 +- +-/* TCCR0 */ +-/* bits 7-3 reserved */ +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* TCCR2 */ +-#define FOC2 7 +-#define WGM20 6 +-#define COM21 5 +-#define COM20 4 +-#define WGM21 3 +-#define CS22 2 +-#define CS21 1 +-#define CS20 0 +- +-/* ASSR */ +-/* bits 7-4 reserved */ +-#define AS2 3 +-#define TCN2UB 2 +-#define OCR2UB 1 +-#define TCR2UB 0 +- +-/* TCCR1A */ +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define FOC1A 3 +-#define FOC1B 2 +-#define WGM11 1 +-#define WGM10 0 +- +-/* TCCR1B */ +-#define ICNC1 7 +-#define ICES1 6 +-/* bit 5 reserved */ +-#define WGM13 4 +-#define WGM12 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* WDTCR */ +-/* bits 7-5 reserved */ +-#define WDCE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* UBRRH */ +-#define URSEL 7 +- +-/* UCSRC */ +-#define URSEL 7 +-#define UMSEL 6 +-#define UPM1 5 +-#define UPM0 4 +-#define USBS 3 +-#define UCSZ1 2 +-#define UCSZ0 1 +-#define UCPOL 0 +- +-/* PORTB */ +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* DDRB */ +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* PINB */ +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* PORTC */ +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-/* DDRC */ +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-/* PINC */ +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-/* PORTD */ +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* DDRD */ +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-/* PIND */ +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-/* SPSR */ +-#define SPIF 7 +-#define WCOL 6 +-#define SPI2X 0 +- +-/* SPCR */ +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +-/* UCSRA */ +-#define RXC 7 +-#define TXC 6 +-#define UDRE 5 +-#define FE 4 +-#define DOR 3 +-#define PE 2 +-#define U2X 1 +-#define MPCM 0 +- +-/* UCSRB */ +-#define RXCIE 7 +-#define TXCIE 6 +-#define UDRIE 5 +-#define RXEN 4 +-#define TXEN 3 +-#define UCSZ2 2 +-#define RXB8 1 +-#define TXB8 0 +- +-/* ACSR */ +-#define ACD 7 +-#define ACBG 6 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +- +-/* ADCSR / ADCSRA */ +-#define ADEN 7 +-#define ADSC 6 +-#define ADFR 5 +-#define ADIF 4 +-#define ADIE 3 +-#define ADPS2 2 +-#define ADPS1 1 +-#define ADPS0 0 +- +-/* ADMUX */ +-#define REFS1 7 +-#define REFS0 6 +-#define ADLAR 5 +-/* bit 4 reserved */ +-#define MUX3 3 +-#define MUX2 2 +-#define MUX1 1 +-#define MUX0 0 +- +-/* EEPROM Control Register */ +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-/* Constants */ +-#define SPM_PAGESIZE 64 +-#define RAMSTART (0x60) +-#define RAMEND 0x45F +-#define XRAMEND RAMEND +-#define E2END 0x1FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x1FFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 2 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_BODEN (unsigned char)~_BV(6) +-#define FUSE_BODLEVEL (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_CKOPT (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_WDTON (unsigned char)~_BV(6) +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x93 +-#define SIGNATURE_2 0x07 +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_INTERRUPT1 +-#pragma GCC poison SIG_OUTPUT_COMPARE2 +-#pragma GCC poison SIG_OVERFLOW2 +-#pragma GCC poison SIG_INPUT_CAPTURE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_SPI +-#pragma GCC poison SIG_UART_RECV +-#pragma GCC poison SIG_UART_DATA +-#pragma GCC poison SIG_UART_TRANS +-#pragma GCC poison SIG_ADC +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_2WIRE_SERIAL +-#pragma GCC poison SIG_SPM_READY +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +-#endif /* _AVR_IOM8_H_ */ ++/* Copyright (c) 2002, Marek Michalkiewicz ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom8.h 2235 2011-03-17 04:13:14Z arcanum $ */ ++ ++/* avr/iom8.h - definitions for ATmega8 */ ++ ++#ifndef _AVR_IOM8_H_ ++#define _AVR_IOM8_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom8.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ ++#define TWBR _SFR_IO8(0x00) ++#define TWSR _SFR_IO8(0x01) ++#define TWAR _SFR_IO8(0x02) ++#define TWDR _SFR_IO8(0x03) ++ ++/* ADC */ ++#define ADCW _SFR_IO16(0x04) ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCL _SFR_IO8(0x04) ++#define ADCH _SFR_IO8(0x05) ++#define ADCSR _SFR_IO8(0x06) ++#define ADCSRA _SFR_IO8(0x06) /* Changed in 2486H-AVR-09/02 */ ++#define ADMUX _SFR_IO8(0x07) ++ ++/* analog comparator */ ++#define ACSR _SFR_IO8(0x08) ++ ++/* USART */ ++#define UBRRL _SFR_IO8(0x09) ++#define UCSRB _SFR_IO8(0x0A) ++#define UCSRA _SFR_IO8(0x0B) ++#define UDR _SFR_IO8(0x0C) ++ ++/* SPI */ ++#define SPCR _SFR_IO8(0x0D) ++#define SPSR _SFR_IO8(0x0E) ++#define SPDR _SFR_IO8(0x0F) ++ ++/* Port D */ ++#define PIND _SFR_IO8(0x10) ++#define DDRD _SFR_IO8(0x11) ++#define PORTD _SFR_IO8(0x12) ++ ++/* Port C */ ++#define PINC _SFR_IO8(0x13) ++#define DDRC _SFR_IO8(0x14) ++#define PORTC _SFR_IO8(0x15) ++ ++/* Port B */ ++#define PINB _SFR_IO8(0x16) ++#define DDRB _SFR_IO8(0x17) ++#define PORTB _SFR_IO8(0x18) ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO16(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++#define EEARH _SFR_IO8(0x1F) ++ ++#define UCSRC _SFR_IO8(0x20) ++#define UBRRH _SFR_IO8(0x20) ++ ++#define WDTCR _SFR_IO8(0x21) ++#define ASSR _SFR_IO8(0x22) ++ ++/* Timer 2 */ ++#define OCR2 _SFR_IO8(0x23) ++#define TCNT2 _SFR_IO8(0x24) ++#define TCCR2 _SFR_IO8(0x25) ++ ++/* Timer 1 */ ++#define ICR1 _SFR_IO16(0x26) ++#define ICR1L _SFR_IO8(0x26) ++#define ICR1H _SFR_IO8(0x27) ++#define OCR1B _SFR_IO16(0x28) ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BH _SFR_IO8(0x29) ++#define OCR1A _SFR_IO16(0x2A) ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++#define TCNT1 _SFR_IO16(0x2C) ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++#define TCCR1B _SFR_IO8(0x2E) ++#define TCCR1A _SFR_IO8(0x2F) ++ ++#define SFIOR _SFR_IO8(0x30) ++ ++#define OSCCAL _SFR_IO8(0x31) ++ ++/* Timer 0 */ ++#define TCNT0 _SFR_IO8(0x32) ++#define TCCR0 _SFR_IO8(0x33) ++ ++#define MCUCSR _SFR_IO8(0x34) ++#define MCUSR _SFR_IO8(0x34) /* Defined as an alias for MCUCSR. */ ++ ++#define MCUCR _SFR_IO8(0x35) ++ ++#define TWCR _SFR_IO8(0x36) ++ ++#define SPMCR _SFR_IO8(0x37) ++ ++#define TIFR _SFR_IO8(0x38) ++#define TIMSK _SFR_IO8(0x39) ++ ++#define GIFR _SFR_IO8(0x3A) ++#define GIMSK _SFR_IO8(0x3B) ++#define GICR _SFR_IO8(0x3B) /* Changed in 2486H-AVR-09/02 */ ++ ++/* 0x3C reserved (OCR0?) */ ++ ++/* 0x3D..0x3E SP */ ++ ++/* 0x3F SREG */ ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++#define SIG_INTERRUPT1 _VECTOR(2) ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect_num 3 ++#define TIMER2_COMP_vect _VECTOR(3) ++#define SIG_OUTPUT_COMPARE2 _VECTOR(3) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 4 ++#define TIMER2_OVF_vect _VECTOR(4) ++#define SIG_OVERFLOW2 _VECTOR(4) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 5 ++#define TIMER1_CAPT_vect _VECTOR(5) ++#define SIG_INPUT_CAPTURE1 _VECTOR(5) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 6 ++#define TIMER1_COMPA_vect _VECTOR(6) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(6) ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect_num 7 ++#define TIMER1_COMPB_vect _VECTOR(7) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(7) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 8 ++#define TIMER1_OVF_vect _VECTOR(8) ++#define SIG_OVERFLOW1 _VECTOR(8) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 9 ++#define TIMER0_OVF_vect _VECTOR(9) ++#define SIG_OVERFLOW0 _VECTOR(9) ++ ++/* Serial Transfer Complete */ ++#define SPI_STC_vect_num 10 ++#define SPI_STC_vect _VECTOR(10) ++#define SIG_SPI _VECTOR(10) ++ ++/* USART, Rx Complete */ ++#define USART_RXC_vect_num 11 ++#define USART_RXC_vect _VECTOR(11) ++#define SIG_UART_RECV _VECTOR(11) ++ ++/* USART Data Register Empty */ ++#define USART_UDRE_vect_num 12 ++#define USART_UDRE_vect _VECTOR(12) ++#define SIG_UART_DATA _VECTOR(12) ++ ++/* USART, Tx Complete */ ++#define USART_TXC_vect_num 13 ++#define USART_TXC_vect _VECTOR(13) ++#define SIG_UART_TRANS _VECTOR(13) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 14 ++#define ADC_vect _VECTOR(14) ++#define SIG_ADC _VECTOR(14) ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect_num 15 ++#define EE_RDY_vect _VECTOR(15) ++#define SIG_EEPROM_READY _VECTOR(15) ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect_num 16 ++#define ANA_COMP_vect _VECTOR(16) ++#define SIG_COMPARATOR _VECTOR(16) ++ ++/* 2-wire Serial Interface */ ++#define TWI_vect_num 17 ++#define TWI_vect _VECTOR(17) ++#define SIG_2WIRE_SERIAL _VECTOR(17) ++ ++/* Store Program Memory Ready */ ++#define SPM_RDY_vect_num 18 ++#define SPM_RDY_vect _VECTOR(18) ++#define SIG_SPM_READY _VECTOR(18) ++ ++#define _VECTORS_SIZE 38 ++ ++/* Bit numbers */ ++ ++/* GIMSK / GICR */ ++#define INT1 7 ++#define INT0 6 ++#define IVSEL 1 ++#define IVCE 0 ++ ++/* GIFR */ ++#define INTF1 7 ++#define INTF0 6 ++ ++/* TIMSK */ ++#define OCIE2 7 ++#define TOIE2 6 ++#define TICIE1 5 ++#define OCIE1A 4 ++#define OCIE1B 3 ++#define TOIE1 2 ++/* bit 1 reserved (OCIE0?) */ ++#define TOIE0 0 ++ ++/* TIFR */ ++#define OCF2 7 ++#define TOV2 6 ++#define ICF1 5 ++#define OCF1A 4 ++#define OCF1B 3 ++#define TOV1 2 ++/* bit 1 reserved (OCF0?) */ ++#define TOV0 0 ++ ++/* SPMCR */ ++#define SPMIE 7 ++#define RWWSB 6 ++/* bit 5 reserved */ ++#define RWWSRE 4 ++#define BLBSET 3 ++#define PGWRT 2 ++#define PGERS 1 ++#define SPMEN 0 ++ ++/* TWCR */ ++#define TWINT 7 ++#define TWEA 6 ++#define TWSTA 5 ++#define TWSTO 4 ++#define TWWC 3 ++#define TWEN 2 ++/* bit 1 reserved (TWI_TST?) */ ++#define TWIE 0 ++ ++/* TWAR */ ++#define TWA6 7 ++#define TWA5 6 ++#define TWA4 5 ++#define TWA3 4 ++#define TWA2 3 ++#define TWA1 2 ++#define TWA0 1 ++#define TWGCE 0 ++ ++/* TWSR */ ++#define TWS7 7 ++#define TWS6 6 ++#define TWS5 5 ++#define TWS4 4 ++#define TWS3 3 ++/* bit 2 reserved */ ++#define TWPS1 1 ++#define TWPS0 0 ++ ++/* MCUCR */ ++#define SE 7 ++#define SM2 6 ++#define SM1 5 ++#define SM0 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* MCUCSR */ ++/* bits 7-4 reserved */ ++#define WDRF 3 ++#define BORF 2 ++#define EXTRF 1 ++#define PORF 0 ++ ++/* ++ The ADHSM bit has been removed from all documentation, ++ as being not needed at all since the comparator has proven ++ to be fast enough even without feeding it more power. ++*/ ++ ++/* SFIOR */ ++/* bits 7-5 reserved */ ++#define ACME 3 ++#define PUD 2 ++#define PSR2 1 ++#define PSR10 0 ++ ++/* TCCR0 */ ++/* bits 7-3 reserved */ ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* TCCR2 */ ++#define FOC2 7 ++#define WGM20 6 ++#define COM21 5 ++#define COM20 4 ++#define WGM21 3 ++#define CS22 2 ++#define CS21 1 ++#define CS20 0 ++ ++/* ASSR */ ++/* bits 7-4 reserved */ ++#define AS2 3 ++#define TCN2UB 2 ++#define OCR2UB 1 ++#define TCR2UB 0 ++ ++/* TCCR1A */ ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define FOC1A 3 ++#define FOC1B 2 ++#define WGM11 1 ++#define WGM10 0 ++ ++/* TCCR1B */ ++#define ICNC1 7 ++#define ICES1 6 ++/* bit 5 reserved */ ++#define WGM13 4 ++#define WGM12 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* WDTCR */ ++/* bits 7-5 reserved */ ++#define WDCE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* UBRRH */ ++#define URSEL 7 ++ ++/* UCSRC */ ++#define URSEL 7 ++#define UMSEL 6 ++#define UPM1 5 ++#define UPM0 4 ++#define USBS 3 ++#define UCSZ1 2 ++#define UCSZ0 1 ++#define UCPOL 0 ++ ++/* PORTB */ ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* DDRB */ ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* PINB */ ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* PORTC */ ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++/* DDRC */ ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++/* PINC */ ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++/* PORTD */ ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* DDRD */ ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++/* PIND */ ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++/* SPSR */ ++#define SPIF 7 ++#define WCOL 6 ++#define SPI2X 0 ++ ++/* SPCR */ ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++/* UCSRA */ ++#define RXC 7 ++#define TXC 6 ++#define UDRE 5 ++#define FE 4 ++#define DOR 3 ++#define PE 2 ++#define U2X 1 ++#define MPCM 0 ++ ++/* UCSRB */ ++#define RXCIE 7 ++#define TXCIE 6 ++#define UDRIE 5 ++#define RXEN 4 ++#define TXEN 3 ++#define UCSZ2 2 ++#define RXB8 1 ++#define TXB8 0 ++ ++/* ACSR */ ++#define ACD 7 ++#define ACBG 6 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++/* ADCSR / ADCSRA */ ++#define ADEN 7 ++#define ADSC 6 ++#define ADFR 5 ++#define ADIF 4 ++#define ADIE 3 ++#define ADPS2 2 ++#define ADPS1 1 ++#define ADPS0 0 ++ ++/* ADMUX */ ++#define REFS1 7 ++#define REFS0 6 ++#define ADLAR 5 ++/* bit 4 reserved */ ++#define MUX3 3 ++#define MUX2 2 ++#define MUX1 1 ++#define MUX0 0 ++ ++/* EEPROM Control Register */ ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++/* Constants */ ++#define SPM_PAGESIZE 64 ++#define RAMSTART (0x60) ++#define RAMEND 0x45F ++#define XRAMEND RAMEND ++#define E2END 0x1FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x1FFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 2 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_BODEN (unsigned char)~_BV(6) ++#define FUSE_BODLEVEL (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_CKOPT (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_WDTON (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x07 ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_INTERRUPT1 ++#pragma GCC poison SIG_OUTPUT_COMPARE2 ++#pragma GCC poison SIG_OVERFLOW2 ++#pragma GCC poison SIG_INPUT_CAPTURE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_SPI ++#pragma GCC poison SIG_UART_RECV ++#pragma GCC poison SIG_UART_DATA ++#pragma GCC poison SIG_UART_TRANS ++#pragma GCC poison SIG_ADC ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_2WIRE_SERIAL ++#pragma GCC poison SIG_SPM_READY ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++#endif /* _AVR_IOM8_H_ */ +diff --git a/include/avr/iom8515.h b/include/avr/iom8515.h +index 9a11838..3a08421 100644 +--- a/include/avr/iom8515.h ++++ b/include/avr/iom8515.h +@@ -1,681 +1,681 @@ +-/* Copyright (c) 2002, Steinar Haugen +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom8515.h 2235 2011-03-17 04:13:14Z arcanum $ */ +- +-/* avr/iom8515.h - definitions for ATmega8515 */ +- +-#ifndef _AVR_IOM8515_H_ +-#define _AVR_IOM8515_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom8515.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* Oscillator Calibration Register */ +-#define OSCCAL _SFR_IO8(0x04) +- +-/* Input Pins, Port E */ +-#define PINE _SFR_IO8(0x05) +- +-/* Data Direction Register, Port E */ +-#define DDRE _SFR_IO8(0x06) +- +-/* Data Register, Port E */ +-#define PORTE _SFR_IO8(0x07) +- +-/* Analog Comparator Control and Status Register */ +-#define ACSR _SFR_IO8(0x08) +- +-/* USART Baud Rate Register */ +-#define UBRRL _SFR_IO8(0x09) +- +-/* USART Control and Status Register B */ +-#define UCSRB _SFR_IO8(0x0A) +- +-/* USART Control and Status Register A */ +-#define UCSRA _SFR_IO8(0x0B) +- +-/* USART I/O Data Register */ +-#define UDR _SFR_IO8(0x0C) +- +-/* SPI Control Register */ +-#define SPCR _SFR_IO8(0x0D) +- +-/* SPI Status Register */ +-#define SPSR _SFR_IO8(0x0E) +- +-/* SPI I/O Data Register */ +-#define SPDR _SFR_IO8(0x0F) +- +-/* Input Pins, Port D */ +-#define PIND _SFR_IO8(0x10) +- +-/* Data Direction Register, Port D */ +-#define DDRD _SFR_IO8(0x11) +- +-/* Data Register, Port D */ +-#define PORTD _SFR_IO8(0x12) +- +-/* Input Pins, Port C */ +-#define PINC _SFR_IO8(0x13) +- +-/* Data Direction Register, Port C */ +-#define DDRC _SFR_IO8(0x14) +- +-/* Data Register, Port C */ +-#define PORTC _SFR_IO8(0x15) +- +-/* Input Pins, Port B */ +-#define PINB _SFR_IO8(0x16) +- +-/* Data Direction Register, Port B */ +-#define DDRB _SFR_IO8(0x17) +- +-/* Data Register, Port B */ +-#define PORTB _SFR_IO8(0x18) +- +-/* Input Pins, Port A */ +-#define PINA _SFR_IO8(0x19) +- +-/* Data Direction Register, Port A */ +-#define DDRA _SFR_IO8(0x1A) +- +-/* Data Register, Port A */ +-#define PORTA _SFR_IO8(0x1B) +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO16(0x1E) +-#define EEARL _SFR_IO8(0x1E) +-#define EEARH _SFR_IO8(0x1F) +- +-/* USART Baud Rate Register HI */ +-/* USART Control and Status Register C */ +-#define UBRRH _SFR_IO8(0x20) +-#define UCSRC UBRRH +- +-/* Watchdog Timer Control Register */ +-#define WDTCR _SFR_IO8(0x21) +- +-/* T/C 1 Input Capture Register */ +-#define ICR1 _SFR_IO16(0x24) +-#define ICR1L _SFR_IO8(0x24) +-#define ICR1H _SFR_IO8(0x25) +- +-/* Timer/Counter1 Output Compare Register B */ +-#define OCR1B _SFR_IO16(0x28) +-#define OCR1BL _SFR_IO8(0x28) +-#define OCR1BH _SFR_IO8(0x29) +- +-/* Timer/Counter1 Output Compare Register A */ +-#define OCR1A _SFR_IO16(0x2A) +-#define OCR1AL _SFR_IO8(0x2A) +-#define OCR1AH _SFR_IO8(0x2B) +- +-/* Timer/Counter 1 */ +-#define TCNT1 _SFR_IO16(0x2C) +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1H _SFR_IO8(0x2D) +- +-/* Timer/Counter 1 Control and Status Register */ +-#define TCCR1B _SFR_IO8(0x2E) +- +-/* Timer/Counter 1 Control Register */ +-#define TCCR1A _SFR_IO8(0x2F) +- +-/* Special Function IO Register */ +-#define SFIOR _SFR_IO8(0x30) +- +-/* Timer/Counter 0 Output Compare Register */ +-#define OCR0 _SFR_IO8(0x31) +- +-/* Timer/Counter 0 */ +-#define TCNT0 _SFR_IO8(0x32) +- +-/* Timer/Counter 0 Control Register */ +-#define TCCR0 _SFR_IO8(0x33) +- +-/* MCU Control and Status Register */ +-#define MCUCSR _SFR_IO8(0x34) +- +-/* MCU Control Register */ +-#define MCUCR _SFR_IO8(0x35) +- +-/* Extended MCU Control Register */ +-#define EMCUCR _SFR_IO8(0x36) +- +-/* Store Program Memory Control Register */ +-#define SPMCR _SFR_IO8(0x37) +- +-/* Timer/Counter Interrupt Flag register */ +-#define TIFR _SFR_IO8(0x38) +- +-/* Timer/Counter Interrupt MaSK register */ +-#define TIMSK _SFR_IO8(0x39) +- +-/* General Interrupt Flag Register */ +-#define GIFR _SFR_IO8(0x3A) +- +-/* General Interrupt Control Register */ +-#define GICR _SFR_IO8(0x3B) +- +-/* 0x3D..0x3E SP */ +- +-/* 0x3F SREG */ +- +-/* Interrupt vectors */ +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt Request 1 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +-#define SIG_INTERRUPT1 _VECTOR(2) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 3 +-#define TIMER1_CAPT_vect _VECTOR(3) +-#define SIG_INPUT_CAPTURE1 _VECTOR(3) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 4 +-#define TIMER1_COMPA_vect _VECTOR(4) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(4) +- +-/* Timer/Counter1 Compare MatchB */ +-#define TIMER1_COMPB_vect_num 5 +-#define TIMER1_COMPB_vect _VECTOR(5) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(5) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 6 +-#define TIMER1_OVF_vect _VECTOR(6) +-#define SIG_OVERFLOW1 _VECTOR(6) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 7 +-#define TIMER0_OVF_vect _VECTOR(7) +-#define SIG_OVERFLOW0 _VECTOR(7) +- +-/* Serial Transfer Complete */ +-#define SPI_STC_vect_num 8 +-#define SPI_STC_vect _VECTOR(8) +-#define SIG_SPI _VECTOR(8) +- +-/* UART, Rx Complete */ +-#define USART_RX_vect_num 9 +-#define USART_RX_vect _VECTOR(9) +-#define UART_RX_vect _VECTOR(9) /* For compatability only */ +-#define SIG_UART_RECV _VECTOR(9) /* For compatability only */ +- +-/* UART Data Register Empty */ +-#define USART_UDRE_vect_num 10 +-#define USART_UDRE_vect _VECTOR(10) +-#define UART_UDRE_vect _VECTOR(10) /* For compatability only */ +-#define SIG_UART_DATA _VECTOR(10) /* For compatability only */ +- +-/* UART, Tx Complete */ +-#define USART_TX_vect_num 11 +-#define USART_TX_vect _VECTOR(11) +-#define UART_TX_vect _VECTOR(11) /* For compatability only */ +-#define SIG_UART_TRANS _VECTOR(11) /* For compatability only */ +- +-/* Analog Comparator */ +-#define ANA_COMP_vect_num 12 +-#define ANA_COMP_vect _VECTOR(12) +-#define SIG_COMPARATOR _VECTOR(12) +- +-/* External Interrupt Request 2 */ +-#define INT2_vect_num 13 +-#define INT2_vect _VECTOR(13) +-#define SIG_INTERRUPT2 _VECTOR(13) +- +-/* Timer 0 Compare Match */ +-#define TIMER0_COMP_vect_num 14 +-#define TIMER0_COMP_vect _VECTOR(14) +-#define SIG_OUTPUT_COMPARE0 _VECTOR(14) +- +-/* EEPROM Ready */ +-#define EE_RDY_vect_num 15 +-#define EE_RDY_vect _VECTOR(15) +-#define SIG_EEPROM_READY _VECTOR(15) +- +-/* Store Program Memory Ready */ +-#define SPM_RDY_vect_num 16 +-#define SPM_RDY_vect _VECTOR(16) +-#define SIG_SPM_READY _VECTOR(16) +- +-#define _VECTORS_SIZE 34 +- +-/* +- The Register Bit names are represented by their bit number (0-7). +-*/ +- +-/* General Interrupt Control Register */ +-#define INT1 7 +-#define INT0 6 +-#define INT2 5 +-#define IVSEL 1 +-#define IVCE 0 +- +-/* General Interrupt Flag Register */ +-#define INTF1 7 +-#define INTF0 6 +-#define INTF2 5 +- +-/* Timer/Counter Interrupt MaSK Register */ +-#define TOIE1 7 +-#define OCIE1A 6 +-#define OCIE1B 5 +-#define TICIE1 3 +-#define TOIE0 1 +-#define OCIE0 0 +- +-/* Timer/Counter Interrupt Flag Register */ +-#define TOV1 7 +-#define OCF1A 6 +-#define OCF1B 5 +-#define ICF1 3 +-#define TOV0 1 +-#define OCF0 0 +- +-/* Store Program Memory Control Register */ +-#define SPMIE 7 +-#define RWWSB 6 +-#define RWWSRE 4 +-#define BLBSET 3 +-#define PGWRT 2 +-#define PGERS 1 +-#define SPMEN 0 +- +-/* Extended MCU Control Register */ +-#define SM0 7 +-#define SRL2 6 +-#define SRL1 5 +-#define SRL0 4 +-#define SRW01 3 +-#define SRW00 2 +-#define SRW11 1 +-#define ISC2 0 +- +-/* MCU Control Register */ +-#define SRE 7 +-#define SRW10 6 +-#define SE 5 +-#define SM1 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-/* MCU Control and Status Register */ +-#define SM2 5 +-#define WDRF 3 +-#define BORF 2 +-#define EXTRF 1 +-#define PORF 0 +- +-/* Timer/Counter 0 Control Register */ +-#define FOC0 7 +-#define WGM00 6 +-#define COM01 5 +-#define COM00 4 +-#define WGM01 3 +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* Special Function IO Register */ +-#define XMBK 6 +-#define XMM2 5 +-#define XMM1 4 +-#define XMM0 3 +-#define PUD 2 +-#define PSR10 0 +- +-/* Timer/Counter 1 Control Register */ +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define FOC1A 3 +-#define FOC1B 2 +-#define WGM11 1 +-#define WGM10 0 +- +-/* Timer/Counter 1 Control and Status Register */ +-#define ICNC1 7 +-#define ICES1 6 +-#define WGM13 4 +-#define WGM12 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* Watchdog Timer Control Register */ +-#define WDCE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* USART Control and Status Register C */ +-#define URSEL 7 +-#define UMSEL 6 +-#define UPM1 5 +-#define UPM0 4 +-#define USBS 3 +-#define UCSZ1 2 +-#define UCSZ0 1 +-#define UCPOL 0 +- +-/* Data Register, Port A */ +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-/* Data Direction Register, Port A */ +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-/* Input Pins, Port A */ +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-/* Data Register, Port B */ +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* Data Direction Register, Port B */ +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* Input Pins, Port B */ +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* Data Register, Port C */ +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-/* Data Direction Register, Port C */ +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-/* Input Pins, Port C */ +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-/* Data Register, Port D */ +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* Data Direction Register, Port D */ +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-/* Input Pins, Port D */ +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-/* SPI Status Register */ +-#define SPIF 7 +-#define WCOL 6 +-#define SPI2X 0 +- +-/* SPI Control Register */ +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +-/* USART Control and Status Register A */ +-#define RXC 7 +-#define TXC 6 +-#define UDRE 5 +-#define FE 4 +-#define DOR 3 +-#define PE 2 +-#define U2X 1 +-#define MPCM 0 +- +-/* USART Control and Status Register B */ +-#define RXCIE 7 +-#define TXCIE 6 +-#define UDRIE 5 +-#define RXEN 4 +-#define TXEN 3 +-#define UCSZ2 2 +-#define RXB8 1 +-#define TXB8 0 +- +-/* Analog Comparator Control and Status Register */ +-#define ACD 7 +-#define ACBG 6 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +- +-/* Data Register, Port E */ +-#define PE2 2 +-#define PE1 1 +-#define PE0 0 +- +-/* Data Direction Register, Port E */ +-#define DDE2 2 +-#define DDE1 1 +-#define DDE0 0 +- +-/* Input Pins, Port E */ +-#define PINE2 2 +-#define PINE1 1 +-#define PINE0 0 +- +-/* EEPROM Control Register */ +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-/* Constants */ +-#define SPM_PAGESIZE 64 +-#define RAMSTART (0x60) +-#define RAMEND 0x25F /* Last On-Chip SRAM Location */ +-#define XRAMEND 0xFFFF +-#define E2END 0x1FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x1FFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 2 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_BODEN (unsigned char)~_BV(6) +-#define FUSE_BODLEVEL (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_CKOPT (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_WDTON (unsigned char)~_BV(6) +-#define FUSE_S8515C (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x93 +-#define SIGNATURE_2 0x06 +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_INTERRUPT1 +-#pragma GCC poison SIG_INPUT_CAPTURE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_SPI +-#pragma GCC poison UART_RX_vect +-#pragma GCC poison SIG_UART_RECV +-#pragma GCC poison UART_UDRE_vect +-#pragma GCC poison SIG_UART_DATA +-#pragma GCC poison UART_TX_vect +-#pragma GCC poison SIG_UART_TRANS +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_INTERRUPT2 +-#pragma GCC poison SIG_OUTPUT_COMPARE0 +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_SPM_READY +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +-#endif /* _AVR_IOM8515_H_ */ ++/* Copyright (c) 2002, Steinar Haugen ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom8515.h 2235 2011-03-17 04:13:14Z arcanum $ */ ++ ++/* avr/iom8515.h - definitions for ATmega8515 */ ++ ++#ifndef _AVR_IOM8515_H_ ++#define _AVR_IOM8515_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom8515.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* Oscillator Calibration Register */ ++#define OSCCAL _SFR_IO8(0x04) ++ ++/* Input Pins, Port E */ ++#define PINE _SFR_IO8(0x05) ++ ++/* Data Direction Register, Port E */ ++#define DDRE _SFR_IO8(0x06) ++ ++/* Data Register, Port E */ ++#define PORTE _SFR_IO8(0x07) ++ ++/* Analog Comparator Control and Status Register */ ++#define ACSR _SFR_IO8(0x08) ++ ++/* USART Baud Rate Register */ ++#define UBRRL _SFR_IO8(0x09) ++ ++/* USART Control and Status Register B */ ++#define UCSRB _SFR_IO8(0x0A) ++ ++/* USART Control and Status Register A */ ++#define UCSRA _SFR_IO8(0x0B) ++ ++/* USART I/O Data Register */ ++#define UDR _SFR_IO8(0x0C) ++ ++/* SPI Control Register */ ++#define SPCR _SFR_IO8(0x0D) ++ ++/* SPI Status Register */ ++#define SPSR _SFR_IO8(0x0E) ++ ++/* SPI I/O Data Register */ ++#define SPDR _SFR_IO8(0x0F) ++ ++/* Input Pins, Port D */ ++#define PIND _SFR_IO8(0x10) ++ ++/* Data Direction Register, Port D */ ++#define DDRD _SFR_IO8(0x11) ++ ++/* Data Register, Port D */ ++#define PORTD _SFR_IO8(0x12) ++ ++/* Input Pins, Port C */ ++#define PINC _SFR_IO8(0x13) ++ ++/* Data Direction Register, Port C */ ++#define DDRC _SFR_IO8(0x14) ++ ++/* Data Register, Port C */ ++#define PORTC _SFR_IO8(0x15) ++ ++/* Input Pins, Port B */ ++#define PINB _SFR_IO8(0x16) ++ ++/* Data Direction Register, Port B */ ++#define DDRB _SFR_IO8(0x17) ++ ++/* Data Register, Port B */ ++#define PORTB _SFR_IO8(0x18) ++ ++/* Input Pins, Port A */ ++#define PINA _SFR_IO8(0x19) ++ ++/* Data Direction Register, Port A */ ++#define DDRA _SFR_IO8(0x1A) ++ ++/* Data Register, Port A */ ++#define PORTA _SFR_IO8(0x1B) ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO16(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++#define EEARH _SFR_IO8(0x1F) ++ ++/* USART Baud Rate Register HI */ ++/* USART Control and Status Register C */ ++#define UBRRH _SFR_IO8(0x20) ++#define UCSRC UBRRH ++ ++/* Watchdog Timer Control Register */ ++#define WDTCR _SFR_IO8(0x21) ++ ++/* T/C 1 Input Capture Register */ ++#define ICR1 _SFR_IO16(0x24) ++#define ICR1L _SFR_IO8(0x24) ++#define ICR1H _SFR_IO8(0x25) ++ ++/* Timer/Counter1 Output Compare Register B */ ++#define OCR1B _SFR_IO16(0x28) ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BH _SFR_IO8(0x29) ++ ++/* Timer/Counter1 Output Compare Register A */ ++#define OCR1A _SFR_IO16(0x2A) ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++ ++/* Timer/Counter 1 */ ++#define TCNT1 _SFR_IO16(0x2C) ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++ ++/* Timer/Counter 1 Control and Status Register */ ++#define TCCR1B _SFR_IO8(0x2E) ++ ++/* Timer/Counter 1 Control Register */ ++#define TCCR1A _SFR_IO8(0x2F) ++ ++/* Special Function IO Register */ ++#define SFIOR _SFR_IO8(0x30) ++ ++/* Timer/Counter 0 Output Compare Register */ ++#define OCR0 _SFR_IO8(0x31) ++ ++/* Timer/Counter 0 */ ++#define TCNT0 _SFR_IO8(0x32) ++ ++/* Timer/Counter 0 Control Register */ ++#define TCCR0 _SFR_IO8(0x33) ++ ++/* MCU Control and Status Register */ ++#define MCUCSR _SFR_IO8(0x34) ++ ++/* MCU Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++ ++/* Extended MCU Control Register */ ++#define EMCUCR _SFR_IO8(0x36) ++ ++/* Store Program Memory Control Register */ ++#define SPMCR _SFR_IO8(0x37) ++ ++/* Timer/Counter Interrupt Flag register */ ++#define TIFR _SFR_IO8(0x38) ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define TIMSK _SFR_IO8(0x39) ++ ++/* General Interrupt Flag Register */ ++#define GIFR _SFR_IO8(0x3A) ++ ++/* General Interrupt Control Register */ ++#define GICR _SFR_IO8(0x3B) ++ ++/* 0x3D..0x3E SP */ ++ ++/* 0x3F SREG */ ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++#define SIG_INTERRUPT1 _VECTOR(2) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 3 ++#define TIMER1_CAPT_vect _VECTOR(3) ++#define SIG_INPUT_CAPTURE1 _VECTOR(3) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 4 ++#define TIMER1_COMPA_vect _VECTOR(4) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(4) ++ ++/* Timer/Counter1 Compare MatchB */ ++#define TIMER1_COMPB_vect_num 5 ++#define TIMER1_COMPB_vect _VECTOR(5) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(5) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 6 ++#define TIMER1_OVF_vect _VECTOR(6) ++#define SIG_OVERFLOW1 _VECTOR(6) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 7 ++#define TIMER0_OVF_vect _VECTOR(7) ++#define SIG_OVERFLOW0 _VECTOR(7) ++ ++/* Serial Transfer Complete */ ++#define SPI_STC_vect_num 8 ++#define SPI_STC_vect _VECTOR(8) ++#define SIG_SPI _VECTOR(8) ++ ++/* UART, Rx Complete */ ++#define USART_RX_vect_num 9 ++#define USART_RX_vect _VECTOR(9) ++#define UART_RX_vect _VECTOR(9) /* For compatability only */ ++#define SIG_UART_RECV _VECTOR(9) /* For compatability only */ ++ ++/* UART Data Register Empty */ ++#define USART_UDRE_vect_num 10 ++#define USART_UDRE_vect _VECTOR(10) ++#define UART_UDRE_vect _VECTOR(10) /* For compatability only */ ++#define SIG_UART_DATA _VECTOR(10) /* For compatability only */ ++ ++/* UART, Tx Complete */ ++#define USART_TX_vect_num 11 ++#define USART_TX_vect _VECTOR(11) ++#define UART_TX_vect _VECTOR(11) /* For compatability only */ ++#define SIG_UART_TRANS _VECTOR(11) /* For compatability only */ ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect_num 12 ++#define ANA_COMP_vect _VECTOR(12) ++#define SIG_COMPARATOR _VECTOR(12) ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect_num 13 ++#define INT2_vect _VECTOR(13) ++#define SIG_INTERRUPT2 _VECTOR(13) ++ ++/* Timer 0 Compare Match */ ++#define TIMER0_COMP_vect_num 14 ++#define TIMER0_COMP_vect _VECTOR(14) ++#define SIG_OUTPUT_COMPARE0 _VECTOR(14) ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect_num 15 ++#define EE_RDY_vect _VECTOR(15) ++#define SIG_EEPROM_READY _VECTOR(15) ++ ++/* Store Program Memory Ready */ ++#define SPM_RDY_vect_num 16 ++#define SPM_RDY_vect _VECTOR(16) ++#define SIG_SPM_READY _VECTOR(16) ++ ++#define _VECTORS_SIZE 34 ++ ++/* ++ The Register Bit names are represented by their bit number (0-7). ++*/ ++ ++/* General Interrupt Control Register */ ++#define INT1 7 ++#define INT0 6 ++#define INT2 5 ++#define IVSEL 1 ++#define IVCE 0 ++ ++/* General Interrupt Flag Register */ ++#define INTF1 7 ++#define INTF0 6 ++#define INTF2 5 ++ ++/* Timer/Counter Interrupt MaSK Register */ ++#define TOIE1 7 ++#define OCIE1A 6 ++#define OCIE1B 5 ++#define TICIE1 3 ++#define TOIE0 1 ++#define OCIE0 0 ++ ++/* Timer/Counter Interrupt Flag Register */ ++#define TOV1 7 ++#define OCF1A 6 ++#define OCF1B 5 ++#define ICF1 3 ++#define TOV0 1 ++#define OCF0 0 ++ ++/* Store Program Memory Control Register */ ++#define SPMIE 7 ++#define RWWSB 6 ++#define RWWSRE 4 ++#define BLBSET 3 ++#define PGWRT 2 ++#define PGERS 1 ++#define SPMEN 0 ++ ++/* Extended MCU Control Register */ ++#define SM0 7 ++#define SRL2 6 ++#define SRL1 5 ++#define SRL0 4 ++#define SRW01 3 ++#define SRW00 2 ++#define SRW11 1 ++#define ISC2 0 ++ ++/* MCU Control Register */ ++#define SRE 7 ++#define SRW10 6 ++#define SE 5 ++#define SM1 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* MCU Control and Status Register */ ++#define SM2 5 ++#define WDRF 3 ++#define BORF 2 ++#define EXTRF 1 ++#define PORF 0 ++ ++/* Timer/Counter 0 Control Register */ ++#define FOC0 7 ++#define WGM00 6 ++#define COM01 5 ++#define COM00 4 ++#define WGM01 3 ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* Special Function IO Register */ ++#define XMBK 6 ++#define XMM2 5 ++#define XMM1 4 ++#define XMM0 3 ++#define PUD 2 ++#define PSR10 0 ++ ++/* Timer/Counter 1 Control Register */ ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define FOC1A 3 ++#define FOC1B 2 ++#define WGM11 1 ++#define WGM10 0 ++ ++/* Timer/Counter 1 Control and Status Register */ ++#define ICNC1 7 ++#define ICES1 6 ++#define WGM13 4 ++#define WGM12 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* Watchdog Timer Control Register */ ++#define WDCE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* USART Control and Status Register C */ ++#define URSEL 7 ++#define UMSEL 6 ++#define UPM1 5 ++#define UPM0 4 ++#define USBS 3 ++#define UCSZ1 2 ++#define UCSZ0 1 ++#define UCPOL 0 ++ ++/* Data Register, Port A */ ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++/* Data Direction Register, Port A */ ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++/* Input Pins, Port A */ ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++/* Data Register, Port B */ ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* Data Direction Register, Port B */ ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* Input Pins, Port B */ ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* Data Register, Port C */ ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++/* Data Direction Register, Port C */ ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++/* Input Pins, Port C */ ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++/* Data Register, Port D */ ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* Data Direction Register, Port D */ ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++/* Input Pins, Port D */ ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++/* SPI Status Register */ ++#define SPIF 7 ++#define WCOL 6 ++#define SPI2X 0 ++ ++/* SPI Control Register */ ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++/* USART Control and Status Register A */ ++#define RXC 7 ++#define TXC 6 ++#define UDRE 5 ++#define FE 4 ++#define DOR 3 ++#define PE 2 ++#define U2X 1 ++#define MPCM 0 ++ ++/* USART Control and Status Register B */ ++#define RXCIE 7 ++#define TXCIE 6 ++#define UDRIE 5 ++#define RXEN 4 ++#define TXEN 3 ++#define UCSZ2 2 ++#define RXB8 1 ++#define TXB8 0 ++ ++/* Analog Comparator Control and Status Register */ ++#define ACD 7 ++#define ACBG 6 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++/* Data Register, Port E */ ++#define PE2 2 ++#define PE1 1 ++#define PE0 0 ++ ++/* Data Direction Register, Port E */ ++#define DDE2 2 ++#define DDE1 1 ++#define DDE0 0 ++ ++/* Input Pins, Port E */ ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++/* EEPROM Control Register */ ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++/* Constants */ ++#define SPM_PAGESIZE 64 ++#define RAMSTART (0x60) ++#define RAMEND 0x25F /* Last On-Chip SRAM Location */ ++#define XRAMEND 0xFFFF ++#define E2END 0x1FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x1FFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 2 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_BODEN (unsigned char)~_BV(6) ++#define FUSE_BODLEVEL (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_CKOPT (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_WDTON (unsigned char)~_BV(6) ++#define FUSE_S8515C (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x06 ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_INTERRUPT1 ++#pragma GCC poison SIG_INPUT_CAPTURE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_SPI ++#pragma GCC poison UART_RX_vect ++#pragma GCC poison SIG_UART_RECV ++#pragma GCC poison UART_UDRE_vect ++#pragma GCC poison SIG_UART_DATA ++#pragma GCC poison UART_TX_vect ++#pragma GCC poison SIG_UART_TRANS ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_INTERRUPT2 ++#pragma GCC poison SIG_OUTPUT_COMPARE0 ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_SPM_READY ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++#endif /* _AVR_IOM8515_H_ */ +diff --git a/include/avr/iom8535.h b/include/avr/iom8535.h +index b14129d..c961846 100644 +--- a/include/avr/iom8535.h ++++ b/include/avr/iom8535.h +@@ -1,766 +1,766 @@ +-/* Copyright (c) 2002, Steinar Haugen +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom8535.h 2235 2011-03-17 04:13:14Z arcanum $ */ +- +-/* avr/iom8535.h - definitions for ATmega8535 */ +- +-#ifndef _AVR_IOM8535_H_ +-#define _AVR_IOM8535_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom8535.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ +-#define TWBR _SFR_IO8(0x00) +-#define TWSR _SFR_IO8(0x01) +-#define TWAR _SFR_IO8(0x02) +-#define TWDR _SFR_IO8(0x03) +- +-/* ADC Data register */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x04) +-#endif +-#define ADCW _SFR_IO16(0x04) +-#define ADCL _SFR_IO8(0x04) +-#define ADCH _SFR_IO8(0x05) +- +-/* ADC Control and Status Register */ +-#define ADCSRA _SFR_IO8(0x06) +- +-/* ADC MUX */ +-#define ADMUX _SFR_IO8(0x07) +- +-/* Analog Comparator Control and Status Register */ +-#define ACSR _SFR_IO8(0x08) +- +-/* USART Baud Rate Register */ +-#define UBRRL _SFR_IO8(0x09) +- +-/* USART Control and Status Register B */ +-#define UCSRB _SFR_IO8(0x0A) +- +-/* USART Control and Status Register A */ +-#define UCSRA _SFR_IO8(0x0B) +- +-/* USART I/O Data Register */ +-#define UDR _SFR_IO8(0x0C) +- +-/* SPI Control Register */ +-#define SPCR _SFR_IO8(0x0D) +- +-/* SPI Status Register */ +-#define SPSR _SFR_IO8(0x0E) +- +-/* SPI I/O Data Register */ +-#define SPDR _SFR_IO8(0x0F) +- +-/* Input Pins, Port D */ +-#define PIND _SFR_IO8(0x10) +- +-/* Data Direction Register, Port D */ +-#define DDRD _SFR_IO8(0x11) +- +-/* Data Register, Port D */ +-#define PORTD _SFR_IO8(0x12) +- +-/* Input Pins, Port C */ +-#define PINC _SFR_IO8(0x13) +- +-/* Data Direction Register, Port C */ +-#define DDRC _SFR_IO8(0x14) +- +-/* Data Register, Port C */ +-#define PORTC _SFR_IO8(0x15) +- +-/* Input Pins, Port B */ +-#define PINB _SFR_IO8(0x16) +- +-/* Data Direction Register, Port B */ +-#define DDRB _SFR_IO8(0x17) +- +-/* Data Register, Port B */ +-#define PORTB _SFR_IO8(0x18) +- +-/* Input Pins, Port A */ +-#define PINA _SFR_IO8(0x19) +- +-/* Data Direction Register, Port A */ +-#define DDRA _SFR_IO8(0x1A) +- +-/* Data Register, Port A */ +-#define PORTA _SFR_IO8(0x1B) +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO16(0x1E) +-#define EEARL _SFR_IO8(0x1E) +-#define EEARH _SFR_IO8(0x1F) +- +-/* USART Baud Rate Register HI */ +-/* USART Control and Status Register C */ +-#define UBRRH _SFR_IO8(0x20) +-#define UCSRC UBRRH +- +-/* Watchdog Timer Control Register */ +-#define WDTCR _SFR_IO8(0x21) +- +-/* Asynchronous mode Status Register */ +-#define ASSR _SFR_IO8(0x22) +- +-/* Timer/Counter2 Output Compare Register */ +-#define OCR2 _SFR_IO8(0x23) +- +-/* Timer/Counter 2 */ +-#define TCNT2 _SFR_IO8(0x24) +- +-/* Timer/Counter 2 Control Register */ +-#define TCCR2 _SFR_IO8(0x25) +- +-/* T/C 1 Input Capture Register */ +-#define ICR1 _SFR_IO16(0x26) +-#define ICR1L _SFR_IO8(0x26) +-#define ICR1H _SFR_IO8(0x27) +- +-/* Timer/Counter1 Output Compare Register B */ +-#define OCR1B _SFR_IO16(0x28) +-#define OCR1BL _SFR_IO8(0x28) +-#define OCR1BH _SFR_IO8(0x29) +- +-/* Timer/Counter1 Output Compare Register A */ +-#define OCR1A _SFR_IO16(0x2A) +-#define OCR1AL _SFR_IO8(0x2A) +-#define OCR1AH _SFR_IO8(0x2B) +- +-/* Timer/Counter 1 */ +-#define TCNT1 _SFR_IO16(0x2C) +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1H _SFR_IO8(0x2D) +- +-/* Timer/Counter 1 Control and Status Register */ +-#define TCCR1B _SFR_IO8(0x2E) +- +-/* Timer/Counter 1 Control Register */ +-#define TCCR1A _SFR_IO8(0x2F) +- +-/* Special Function IO Register */ +-#define SFIOR _SFR_IO8(0x30) +- +-/* Oscillator Calibration Register */ +-#define OSCCAL _SFR_IO8(0x31) +- +-/* Timer/Counter 0 */ +-#define TCNT0 _SFR_IO8(0x32) +- +-/* Timer/Counter 0 Control Register */ +-#define TCCR0 _SFR_IO8(0x33) +- +-/* MCU Control and Status Register */ +-#define MCUCSR _SFR_IO8(0x34) +- +-/* MCU Control Register */ +-#define MCUCR _SFR_IO8(0x35) +- +-/* TWI Control Register */ +-#define TWCR _SFR_IO8(0x36) +- +-/* Store Program Memory Control Register */ +-#define SPMCR _SFR_IO8(0x37) +- +-/* Timer/Counter Interrupt Flag register */ +-#define TIFR _SFR_IO8(0x38) +- +-/* Timer/Counter Interrupt MaSK register */ +-#define TIMSK _SFR_IO8(0x39) +- +-/* General Interrupt Flag Register */ +-#define GIFR _SFR_IO8(0x3A) +- +-/* General Interrupt MaSK register */ +-#define GICR _SFR_IO8(0x3B) +- +-/* Timer/Counter 0 Output Compare Register */ +-#define OCR0 _SFR_IO8(0x3C) +- +-/* 0x3D..0x3E SP */ +- +-/* 0x3F SREG */ +- +-/* Interrupt vectors */ +- +-/* External Interrupt 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt 1 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +-#define SIG_INTERRUPT1 _VECTOR(2) +- +-/* Timer/Counter2 Compare Match */ +-#define TIMER2_COMP_vect_num 3 +-#define TIMER2_COMP_vect _VECTOR(3) +-#define SIG_OUTPUT_COMPARE2 _VECTOR(3) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 4 +-#define TIMER2_OVF_vect _VECTOR(4) +-#define SIG_OVERFLOW2 _VECTOR(4) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 5 +-#define TIMER1_CAPT_vect _VECTOR(5) +-#define SIG_INPUT_CAPTURE1 _VECTOR(5) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 6 +-#define TIMER1_COMPA_vect _VECTOR(6) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(6) +- +-/* Timer/Counter1 Compare Match B */ +-#define TIMER1_COMPB_vect_num 7 +-#define TIMER1_COMPB_vect _VECTOR(7) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(7) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 8 +-#define TIMER1_OVF_vect _VECTOR(8) +-#define SIG_OVERFLOW1 _VECTOR(8) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 9 +-#define TIMER0_OVF_vect _VECTOR(9) +-#define SIG_OVERFLOW0 _VECTOR(9) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 10 +-#define SPI_STC_vect _VECTOR(10) +-#define SIG_SPI _VECTOR(10) +- +-/* USART, RX Complete */ +-#define USART_RX_vect_num 11 +-#define USART_RX_vect _VECTOR(11) +-#define SIG_UART_RECV _VECTOR(11) +- +-/* USART Data Register Empty */ +-#define USART_UDRE_vect_num 12 +-#define USART_UDRE_vect _VECTOR(12) +-#define SIG_UART_DATA _VECTOR(12) +- +-/* USART, TX Complete */ +-#define USART_TX_vect_num 13 +-#define USART_TX_vect _VECTOR(13) +-#define SIG_UART_TRANS _VECTOR(13) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 14 +-#define ADC_vect _VECTOR(14) +-#define SIG_ADC _VECTOR(14) +- +-/* EEPROM Ready */ +-#define EE_RDY_vect_num 15 +-#define EE_RDY_vect _VECTOR(15) +-#define SIG_EEPROM_READY _VECTOR(15) +- +-/* Analog Comparator */ +-#define ANA_COMP_vect_num 16 +-#define ANA_COMP_vect _VECTOR(16) +-#define SIG_COMPARATOR _VECTOR(16) +- +-/* Two-wire Serial Interface */ +-#define TWI_vect_num 17 +-#define TWI_vect _VECTOR(17) +-#define SIG_2WIRE_SERIAL _VECTOR(17) +- +-/* External Interrupt Request 2 */ +-#define INT2_vect_num 18 +-#define INT2_vect _VECTOR(18) +-#define SIG_INTERRUPT2 _VECTOR(18) +- +-/* TimerCounter0 Compare Match */ +-#define TIMER0_COMP_vect_num 19 +-#define TIMER0_COMP_vect _VECTOR(19) +-#define SIG_OUTPUT_COMPARE0 _VECTOR(19) +- +-/* Store Program Memory Read */ +-#define SPM_RDY_vect_num 20 +-#define SPM_RDY_vect _VECTOR(20) +-#define SIG_SPM_READY _VECTOR(20) +- +-#define _VECTORS_SIZE 42 +- +-/* +- The Register Bit names are represented by their bit number (0-7). +-*/ +- +-/* General Interrupt Control Register */ +-#define INT1 7 +-#define INT0 6 +-#define INT2 5 +-#define IVSEL 1 +-#define IVCE 0 +- +-/* General Interrupt Flag Register */ +-#define INTF1 7 +-#define INTF0 6 +-#define INTF2 5 +- +-/* Timer/Counter Interrupt MaSK register */ +-#define OCIE2 7 +-#define TOIE2 6 +-#define TICIE1 5 +-#define OCIE1A 4 +-#define OCIE1B 3 +-#define TOIE1 2 +-#define OCIE0 1 +-#define TOIE0 0 +- +-/* Timer/Counter Interrupt Flag register */ +-#define OCF2 7 +-#define TOV2 6 +-#define ICF1 5 +-#define OCF1A 4 +-#define OCF1B 3 +-#define TOV1 2 +-#define OCF0 1 +-#define TOV0 0 +- +-/* Store Program Memory Control Register */ +-#define SPMIE 7 +-#define RWWSB 6 +-#define RWWSRE 4 +-#define BLBSET 3 +-#define PGWRT 2 +-#define PGERS 1 +-#define SPMEN 0 +- +-/* TWI Control Register */ +-#define TWINT 7 +-#define TWEA 6 +-#define TWSTA 5 +-#define TWSTO 4 +-#define TWWC 3 +-#define TWEN 2 +-#define TWIE 0 +- +-/* MCU Control Register */ +-#define SM2 7 +-#define SE 6 +-#define SM1 5 +-#define SM0 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-/* MCU Control and Status Register */ +-#define ISC2 6 +-#define WDRF 3 +-#define BORF 2 +-#define EXTRF 1 +-#define PORF 0 +- +-/* Timer/Counter 0 Control Register */ +-#define FOC0 7 +-#define WGM00 6 +-#define COM01 5 +-#define COM00 4 +-#define WGM01 3 +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* +- The ADHSM bit has been removed from all documentation, +- as being not needed at all since the comparator has proven +- to be fast enough even without feeding it more power. +-*/ +- +-/* Special Function IO Register */ +-#define ADTS2 7 +-#define ADTS1 6 +-#define ADTS0 5 +-#define ACME 3 +-#define PUD 2 +-#define PSR2 1 +-#define PSR10 0 +- +-/* Timer/Counter 1 Control Register */ +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define FOC1A 3 +-#define FOC1B 2 +-#define WGM11 1 +-#define WGM10 0 +- +-/* Timer/Counter 1 Control and Status Register */ +-#define ICNC1 7 +-#define ICES1 6 +-#define WGM13 4 +-#define WGM12 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* Timer/Counter 2 Control Register */ +-#define FOC2 7 +-#define WGM20 6 +-#define COM21 5 +-#define COM20 4 +-#define WGM21 3 +-#define CS22 2 +-#define CS21 1 +-#define CS20 0 +- +-/* Asynchronous mode Status Register */ +-#define AS2 3 +-#define TCN2UB 2 +-#define OCR2UB 1 +-#define TCR2UB 0 +- +-/* Watchdog Timer Control Register */ +-#define WDCE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* USART Control and Status Register C */ +-#define URSEL 7 +-#define UMSEL 6 +-#define UPM1 5 +-#define UPM0 4 +-#define USBS 3 +-#define UCSZ1 2 +-#define UCSZ0 1 +-#define UCPOL 0 +- +-/* Data Register, Port A */ +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-/* Data Direction Register, Port A */ +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-/* Input Pins, Port A */ +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-/* Data Register, Port B */ +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* Data Direction Register, Port B */ +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* Input Pins, Port B */ +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* Data Register, Port C */ +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-/* Data Direction Register, Port C */ +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-/* Input Pins, Port C */ +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-/* Data Register, Port D */ +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* Data Direction Register, Port D */ +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-/* Input Pins, Port D */ +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-/* SPI Status Register */ +-#define SPIF 7 +-#define WCOL 6 +-#define SPI2X 0 +- +-/* SPI Control Register */ +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +-/* USART Control and Status Register A */ +-#define RXC 7 +-#define TXC 6 +-#define UDRE 5 +-#define FE 4 +-#define DOR 3 +-#define PE 2 +-#define U2X 1 +-#define MPCM 0 +- +-/* USART Control and Status Register B */ +-#define RXCIE 7 +-#define TXCIE 6 +-#define UDRIE 5 +-#define RXEN 4 +-#define TXEN 3 +-#define UCSZ2 2 +-#define RXB8 1 +-#define TXB8 0 +- +-/* Analog Comparator Control and Status Register */ +-#define ACD 7 +-#define ACBG 6 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +- +-/* ADC Multiplexer Selection Register */ +-#define REFS1 7 +-#define REFS0 6 +-#define ADLAR 5 +-#define MUX4 4 +-#define MUX3 3 +-#define MUX2 2 +-#define MUX1 1 +-#define MUX0 0 +- +-/* ADC Control and Status Register */ +-#define ADEN 7 +-#define ADSC 6 +-#define ADATE 5 +-#define ADIF 4 +-#define ADIE 3 +-#define ADPS2 2 +-#define ADPS1 1 +-#define ADPS0 0 +- +-/* TWI (Slave) Address Register */ +-#define TWGCE 0 +- +-/* TWI Status Register */ +-#define TWS7 7 +-#define TWS6 6 +-#define TWS5 5 +-#define TWS4 4 +-#define TWS3 3 +-#define TWPS1 1 +-#define TWPS0 0 +- +-/* EEPROM Control Register */ +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-/* Constants */ +-#define SPM_PAGESIZE 64 +-#define RAMSTART (0x60) +-#define RAMEND 0x25F /* Last On-Chip SRAM Location */ +-#define XRAMEND RAMEND +-#define E2END 0x1FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x1FFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 2 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_BODEN (unsigned char)~_BV(6) +-#define FUSE_BODLEVEL (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_CKOPT (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_WDTON (unsigned char)~_BV(6) +-#define FUSE_S8535C (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x93 +-#define SIGNATURE_2 0x08 +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_INTERRUPT1 +-#pragma GCC poison SIG_OUTPUT_COMPARE2 +-#pragma GCC poison SIG_OVERFLOW2 +-#pragma GCC poison SIG_INPUT_CAPTURE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_SPI +-#pragma GCC poison SIG_UART_RECV +-#pragma GCC poison SIG_UART_DATA +-#pragma GCC poison SIG_UART_TRANS +-#pragma GCC poison SIG_ADC +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_2WIRE_SERIAL +-#pragma GCC poison SIG_INTERRUPT2 +-#pragma GCC poison SIG_OUTPUT_COMPARE0 +-#pragma GCC poison SIG_SPM_READY +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +- +-#endif /* _AVR_IOM8535_H_ */ ++/* Copyright (c) 2002, Steinar Haugen ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom8535.h 2235 2011-03-17 04:13:14Z arcanum $ */ ++ ++/* avr/iom8535.h - definitions for ATmega8535 */ ++ ++#ifndef _AVR_IOM8535_H_ ++#define _AVR_IOM8535_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom8535.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */ ++#define TWBR _SFR_IO8(0x00) ++#define TWSR _SFR_IO8(0x01) ++#define TWAR _SFR_IO8(0x02) ++#define TWDR _SFR_IO8(0x03) ++ ++/* ADC Data register */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCW _SFR_IO16(0x04) ++#define ADCL _SFR_IO8(0x04) ++#define ADCH _SFR_IO8(0x05) ++ ++/* ADC Control and Status Register */ ++#define ADCSRA _SFR_IO8(0x06) ++ ++/* ADC MUX */ ++#define ADMUX _SFR_IO8(0x07) ++ ++/* Analog Comparator Control and Status Register */ ++#define ACSR _SFR_IO8(0x08) ++ ++/* USART Baud Rate Register */ ++#define UBRRL _SFR_IO8(0x09) ++ ++/* USART Control and Status Register B */ ++#define UCSRB _SFR_IO8(0x0A) ++ ++/* USART Control and Status Register A */ ++#define UCSRA _SFR_IO8(0x0B) ++ ++/* USART I/O Data Register */ ++#define UDR _SFR_IO8(0x0C) ++ ++/* SPI Control Register */ ++#define SPCR _SFR_IO8(0x0D) ++ ++/* SPI Status Register */ ++#define SPSR _SFR_IO8(0x0E) ++ ++/* SPI I/O Data Register */ ++#define SPDR _SFR_IO8(0x0F) ++ ++/* Input Pins, Port D */ ++#define PIND _SFR_IO8(0x10) ++ ++/* Data Direction Register, Port D */ ++#define DDRD _SFR_IO8(0x11) ++ ++/* Data Register, Port D */ ++#define PORTD _SFR_IO8(0x12) ++ ++/* Input Pins, Port C */ ++#define PINC _SFR_IO8(0x13) ++ ++/* Data Direction Register, Port C */ ++#define DDRC _SFR_IO8(0x14) ++ ++/* Data Register, Port C */ ++#define PORTC _SFR_IO8(0x15) ++ ++/* Input Pins, Port B */ ++#define PINB _SFR_IO8(0x16) ++ ++/* Data Direction Register, Port B */ ++#define DDRB _SFR_IO8(0x17) ++ ++/* Data Register, Port B */ ++#define PORTB _SFR_IO8(0x18) ++ ++/* Input Pins, Port A */ ++#define PINA _SFR_IO8(0x19) ++ ++/* Data Direction Register, Port A */ ++#define DDRA _SFR_IO8(0x1A) ++ ++/* Data Register, Port A */ ++#define PORTA _SFR_IO8(0x1B) ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO16(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++#define EEARH _SFR_IO8(0x1F) ++ ++/* USART Baud Rate Register HI */ ++/* USART Control and Status Register C */ ++#define UBRRH _SFR_IO8(0x20) ++#define UCSRC UBRRH ++ ++/* Watchdog Timer Control Register */ ++#define WDTCR _SFR_IO8(0x21) ++ ++/* Asynchronous mode Status Register */ ++#define ASSR _SFR_IO8(0x22) ++ ++/* Timer/Counter2 Output Compare Register */ ++#define OCR2 _SFR_IO8(0x23) ++ ++/* Timer/Counter 2 */ ++#define TCNT2 _SFR_IO8(0x24) ++ ++/* Timer/Counter 2 Control Register */ ++#define TCCR2 _SFR_IO8(0x25) ++ ++/* T/C 1 Input Capture Register */ ++#define ICR1 _SFR_IO16(0x26) ++#define ICR1L _SFR_IO8(0x26) ++#define ICR1H _SFR_IO8(0x27) ++ ++/* Timer/Counter1 Output Compare Register B */ ++#define OCR1B _SFR_IO16(0x28) ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BH _SFR_IO8(0x29) ++ ++/* Timer/Counter1 Output Compare Register A */ ++#define OCR1A _SFR_IO16(0x2A) ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++ ++/* Timer/Counter 1 */ ++#define TCNT1 _SFR_IO16(0x2C) ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++ ++/* Timer/Counter 1 Control and Status Register */ ++#define TCCR1B _SFR_IO8(0x2E) ++ ++/* Timer/Counter 1 Control Register */ ++#define TCCR1A _SFR_IO8(0x2F) ++ ++/* Special Function IO Register */ ++#define SFIOR _SFR_IO8(0x30) ++ ++/* Oscillator Calibration Register */ ++#define OSCCAL _SFR_IO8(0x31) ++ ++/* Timer/Counter 0 */ ++#define TCNT0 _SFR_IO8(0x32) ++ ++/* Timer/Counter 0 Control Register */ ++#define TCCR0 _SFR_IO8(0x33) ++ ++/* MCU Control and Status Register */ ++#define MCUCSR _SFR_IO8(0x34) ++ ++/* MCU Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++ ++/* TWI Control Register */ ++#define TWCR _SFR_IO8(0x36) ++ ++/* Store Program Memory Control Register */ ++#define SPMCR _SFR_IO8(0x37) ++ ++/* Timer/Counter Interrupt Flag register */ ++#define TIFR _SFR_IO8(0x38) ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define TIMSK _SFR_IO8(0x39) ++ ++/* General Interrupt Flag Register */ ++#define GIFR _SFR_IO8(0x3A) ++ ++/* General Interrupt MaSK register */ ++#define GICR _SFR_IO8(0x3B) ++ ++/* Timer/Counter 0 Output Compare Register */ ++#define OCR0 _SFR_IO8(0x3C) ++ ++/* 0x3D..0x3E SP */ ++ ++/* 0x3F SREG */ ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt 1 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++#define SIG_INTERRUPT1 _VECTOR(2) ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect_num 3 ++#define TIMER2_COMP_vect _VECTOR(3) ++#define SIG_OUTPUT_COMPARE2 _VECTOR(3) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 4 ++#define TIMER2_OVF_vect _VECTOR(4) ++#define SIG_OVERFLOW2 _VECTOR(4) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 5 ++#define TIMER1_CAPT_vect _VECTOR(5) ++#define SIG_INPUT_CAPTURE1 _VECTOR(5) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 6 ++#define TIMER1_COMPA_vect _VECTOR(6) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(6) ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect_num 7 ++#define TIMER1_COMPB_vect _VECTOR(7) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(7) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 8 ++#define TIMER1_OVF_vect _VECTOR(8) ++#define SIG_OVERFLOW1 _VECTOR(8) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 9 ++#define TIMER0_OVF_vect _VECTOR(9) ++#define SIG_OVERFLOW0 _VECTOR(9) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 10 ++#define SPI_STC_vect _VECTOR(10) ++#define SIG_SPI _VECTOR(10) ++ ++/* USART, RX Complete */ ++#define USART_RX_vect_num 11 ++#define USART_RX_vect _VECTOR(11) ++#define SIG_UART_RECV _VECTOR(11) ++ ++/* USART Data Register Empty */ ++#define USART_UDRE_vect_num 12 ++#define USART_UDRE_vect _VECTOR(12) ++#define SIG_UART_DATA _VECTOR(12) ++ ++/* USART, TX Complete */ ++#define USART_TX_vect_num 13 ++#define USART_TX_vect _VECTOR(13) ++#define SIG_UART_TRANS _VECTOR(13) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 14 ++#define ADC_vect _VECTOR(14) ++#define SIG_ADC _VECTOR(14) ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect_num 15 ++#define EE_RDY_vect _VECTOR(15) ++#define SIG_EEPROM_READY _VECTOR(15) ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect_num 16 ++#define ANA_COMP_vect _VECTOR(16) ++#define SIG_COMPARATOR _VECTOR(16) ++ ++/* Two-wire Serial Interface */ ++#define TWI_vect_num 17 ++#define TWI_vect _VECTOR(17) ++#define SIG_2WIRE_SERIAL _VECTOR(17) ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect_num 18 ++#define INT2_vect _VECTOR(18) ++#define SIG_INTERRUPT2 _VECTOR(18) ++ ++/* TimerCounter0 Compare Match */ ++#define TIMER0_COMP_vect_num 19 ++#define TIMER0_COMP_vect _VECTOR(19) ++#define SIG_OUTPUT_COMPARE0 _VECTOR(19) ++ ++/* Store Program Memory Read */ ++#define SPM_RDY_vect_num 20 ++#define SPM_RDY_vect _VECTOR(20) ++#define SIG_SPM_READY _VECTOR(20) ++ ++#define _VECTORS_SIZE 42 ++ ++/* ++ The Register Bit names are represented by their bit number (0-7). ++*/ ++ ++/* General Interrupt Control Register */ ++#define INT1 7 ++#define INT0 6 ++#define INT2 5 ++#define IVSEL 1 ++#define IVCE 0 ++ ++/* General Interrupt Flag Register */ ++#define INTF1 7 ++#define INTF0 6 ++#define INTF2 5 ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define OCIE2 7 ++#define TOIE2 6 ++#define TICIE1 5 ++#define OCIE1A 4 ++#define OCIE1B 3 ++#define TOIE1 2 ++#define OCIE0 1 ++#define TOIE0 0 ++ ++/* Timer/Counter Interrupt Flag register */ ++#define OCF2 7 ++#define TOV2 6 ++#define ICF1 5 ++#define OCF1A 4 ++#define OCF1B 3 ++#define TOV1 2 ++#define OCF0 1 ++#define TOV0 0 ++ ++/* Store Program Memory Control Register */ ++#define SPMIE 7 ++#define RWWSB 6 ++#define RWWSRE 4 ++#define BLBSET 3 ++#define PGWRT 2 ++#define PGERS 1 ++#define SPMEN 0 ++ ++/* TWI Control Register */ ++#define TWINT 7 ++#define TWEA 6 ++#define TWSTA 5 ++#define TWSTO 4 ++#define TWWC 3 ++#define TWEN 2 ++#define TWIE 0 ++ ++/* MCU Control Register */ ++#define SM2 7 ++#define SE 6 ++#define SM1 5 ++#define SM0 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* MCU Control and Status Register */ ++#define ISC2 6 ++#define WDRF 3 ++#define BORF 2 ++#define EXTRF 1 ++#define PORF 0 ++ ++/* Timer/Counter 0 Control Register */ ++#define FOC0 7 ++#define WGM00 6 ++#define COM01 5 ++#define COM00 4 ++#define WGM01 3 ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* ++ The ADHSM bit has been removed from all documentation, ++ as being not needed at all since the comparator has proven ++ to be fast enough even without feeding it more power. ++*/ ++ ++/* Special Function IO Register */ ++#define ADTS2 7 ++#define ADTS1 6 ++#define ADTS0 5 ++#define ACME 3 ++#define PUD 2 ++#define PSR2 1 ++#define PSR10 0 ++ ++/* Timer/Counter 1 Control Register */ ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define FOC1A 3 ++#define FOC1B 2 ++#define WGM11 1 ++#define WGM10 0 ++ ++/* Timer/Counter 1 Control and Status Register */ ++#define ICNC1 7 ++#define ICES1 6 ++#define WGM13 4 ++#define WGM12 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* Timer/Counter 2 Control Register */ ++#define FOC2 7 ++#define WGM20 6 ++#define COM21 5 ++#define COM20 4 ++#define WGM21 3 ++#define CS22 2 ++#define CS21 1 ++#define CS20 0 ++ ++/* Asynchronous mode Status Register */ ++#define AS2 3 ++#define TCN2UB 2 ++#define OCR2UB 1 ++#define TCR2UB 0 ++ ++/* Watchdog Timer Control Register */ ++#define WDCE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* USART Control and Status Register C */ ++#define URSEL 7 ++#define UMSEL 6 ++#define UPM1 5 ++#define UPM0 4 ++#define USBS 3 ++#define UCSZ1 2 ++#define UCSZ0 1 ++#define UCPOL 0 ++ ++/* Data Register, Port A */ ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++/* Data Direction Register, Port A */ ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++/* Input Pins, Port A */ ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++/* Data Register, Port B */ ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* Data Direction Register, Port B */ ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* Input Pins, Port B */ ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* Data Register, Port C */ ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++/* Data Direction Register, Port C */ ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++/* Input Pins, Port C */ ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++/* Data Register, Port D */ ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* Data Direction Register, Port D */ ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++/* Input Pins, Port D */ ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++/* SPI Status Register */ ++#define SPIF 7 ++#define WCOL 6 ++#define SPI2X 0 ++ ++/* SPI Control Register */ ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++/* USART Control and Status Register A */ ++#define RXC 7 ++#define TXC 6 ++#define UDRE 5 ++#define FE 4 ++#define DOR 3 ++#define PE 2 ++#define U2X 1 ++#define MPCM 0 ++ ++/* USART Control and Status Register B */ ++#define RXCIE 7 ++#define TXCIE 6 ++#define UDRIE 5 ++#define RXEN 4 ++#define TXEN 3 ++#define UCSZ2 2 ++#define RXB8 1 ++#define TXB8 0 ++ ++/* Analog Comparator Control and Status Register */ ++#define ACD 7 ++#define ACBG 6 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++/* ADC Multiplexer Selection Register */ ++#define REFS1 7 ++#define REFS0 6 ++#define ADLAR 5 ++#define MUX4 4 ++#define MUX3 3 ++#define MUX2 2 ++#define MUX1 1 ++#define MUX0 0 ++ ++/* ADC Control and Status Register */ ++#define ADEN 7 ++#define ADSC 6 ++#define ADATE 5 ++#define ADIF 4 ++#define ADIE 3 ++#define ADPS2 2 ++#define ADPS1 1 ++#define ADPS0 0 ++ ++/* TWI (Slave) Address Register */ ++#define TWGCE 0 ++ ++/* TWI Status Register */ ++#define TWS7 7 ++#define TWS6 6 ++#define TWS5 5 ++#define TWS4 4 ++#define TWS3 3 ++#define TWPS1 1 ++#define TWPS0 0 ++ ++/* EEPROM Control Register */ ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++/* Constants */ ++#define SPM_PAGESIZE 64 ++#define RAMSTART (0x60) ++#define RAMEND 0x25F /* Last On-Chip SRAM Location */ ++#define XRAMEND RAMEND ++#define E2END 0x1FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x1FFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 2 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_BODEN (unsigned char)~_BV(6) ++#define FUSE_BODLEVEL (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_CKOPT (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_WDTON (unsigned char)~_BV(6) ++#define FUSE_S8535C (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x08 ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_INTERRUPT1 ++#pragma GCC poison SIG_OUTPUT_COMPARE2 ++#pragma GCC poison SIG_OVERFLOW2 ++#pragma GCC poison SIG_INPUT_CAPTURE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_SPI ++#pragma GCC poison SIG_UART_RECV ++#pragma GCC poison SIG_UART_DATA ++#pragma GCC poison SIG_UART_TRANS ++#pragma GCC poison SIG_ADC ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_2WIRE_SERIAL ++#pragma GCC poison SIG_INTERRUPT2 ++#pragma GCC poison SIG_OUTPUT_COMPARE0 ++#pragma GCC poison SIG_SPM_READY ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++ ++#endif /* _AVR_IOM8535_H_ */ +diff --git a/include/avr/iom88.h b/include/avr/iom88.h +index b9704c5..2d48d40 100644 +--- a/include/avr/iom88.h ++++ b/include/avr/iom88.h +@@ -1,92 +1,92 @@ +-/* Copyright (c) 2004, Theodore A. Roth +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom88.h 2115 2010-04-05 23:19:53Z arcanum $ */ +- +-#ifndef _AVR_IOM88_H_ +-#define _AVR_IOM88_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 64 +-#define RAMSTART (0x100) +-#define RAMEND 0x4FF +-#define XRAMEND RAMEND +-#define E2END 0x1FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x1FFF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x93 +-#define SIGNATURE_2 0x0A +- +- +-#endif /* _AVR_IOM88_H_ */ ++/* Copyright (c) 2004, Theodore A. Roth ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom88.h 2115 2010-04-05 23:19:53Z arcanum $ */ ++ ++#ifndef _AVR_IOM88_H_ ++#define _AVR_IOM88_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 64 ++#define RAMSTART (0x100) ++#define RAMEND 0x4FF ++#define XRAMEND RAMEND ++#define E2END 0x1FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x1FFF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x0A ++ ++ ++#endif /* _AVR_IOM88_H_ */ diff --git a/include/avr/iom88a.h b/include/avr/iom88a.h new file mode 100644 -index 0000000..a564ddd +index 0000000..d2ff981 --- /dev/null +++ b/include/avr/iom88a.h @@ -0,0 +1,34 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2011 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+#include "iom88.h" -diff --git a/include/avr/iom8a.h b/include/avr/iom8a.h -new file mode 100644 -index 0000000..7b55820 ---- /dev/null -+++ b/include/avr/iom8a.h -@@ -0,0 +1,562 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATMEGA8A_H_INCLUDED -+#define _AVR_ATMEGA8A_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iom8a.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define TWBR _SFR_IO8(0x00) -+ -+#define TWSR _SFR_IO8(0x01) -+#define TWPS0 0 -+#define TWPS1 1 -+#define TWS3 3 -+#define TWS4 4 -+#define TWS5 5 -+#define TWS6 6 -+#define TWS7 7 -+ -+#define TWAR _SFR_IO8(0x02) -+#define TWGCE 0 -+#define TWA0 1 -+#define TWA1 2 -+#define TWA2 3 -+#define TWA3 4 -+#define TWA4 5 -+#define TWA5 6 -+#define TWA6 7 -+ -+#define TWDR _SFR_IO8(0x03) -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_IO16(0x04) -+#endif -+#define ADCW _SFR_IO16(0x04) -+ -+#define ADCL _SFR_IO8(0x04) -+#define ADCH _SFR_IO8(0x05) -+ -+#define ADCSRA _SFR_IO8(0x06) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADFR 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADMUX _SFR_IO8(0x07) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define ADLAR 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+#define ACSR _SFR_IO8(0x08) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACBG 6 -+#define ACD 7 -+ -+#define UBRRL _SFR_IO8(0x09) -+ -+#define UCSRB _SFR_IO8(0x0A) -+#define TXB8 0 -+#define RXB8 1 -+#define UCSZ2 2 -+#define TXEN 3 -+#define RXEN 4 -+#define UDRIE 5 -+#define TXCIE 6 -+#define RXCIE 7 -+ -+#define UCSRA _SFR_IO8(0x0B) -+#define MPCM 0 -+#define U2X 1 -+#define UPE 2 -+#define DOR 3 -+#define FE 4 -+#define UDRE 5 -+#define TXC 6 -+#define RXC 7 -+ -+#define UDR _SFR_IO8(0x0C) -+ -+#define SPCR _SFR_IO8(0x0D) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x0E) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x0F) -+ -+#define PIND _SFR_IO8(0x10) -+#define PIND7 7 -+#define PIND6 6 -+#define PIND5 5 -+#define PIND4 4 -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x11) -+#define DDRD7 7 -+#define DDRD6 6 -+#define DDRD5 5 -+#define DDRD4 4 -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x12) -+#define PORTD7 7 -+#define PORTD6 6 -+#define PORTD5 5 -+#define PORTD4 4 -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+#define PINC _SFR_IO8(0x13) -+#define PINC6 6 -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x14) -+#define DDRC6 6 -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x15) -+#define PORTC6 6 -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PINB _SFR_IO8(0x16) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x17) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x18) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+/* Reserved [0x19..0x1B] */ -+ -+#define EECR _SFR_IO8(0x1C) -+#define EERE 0 -+#define EEWE 1 -+#define EEMWE 2 -+#define EERIE 3 -+ -+#define EEDR _SFR_IO8(0x1D) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x1E) -+ -+#define EEARL _SFR_IO8(0x1E) -+#define EEARH _SFR_IO8(0x1F) -+ -+#define UCSRC _SFR_IO8(0x20) -+#define UCPOL 0 -+#define UCSZ0 1 -+#define UCSZ1 2 -+#define USBS 3 -+#define UPM0 4 -+#define UPM1 5 -+#define UMSEL 6 -+#define URSEL 7 -+ -+#define UBRRH _SFR_IO8(0x20) -+ -+#define WDTCR _SFR_IO8(0x21) -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDE 3 -+#define WDCE 4 -+ -+#define ASSR _SFR_IO8(0x22) -+#define TCR2UB 0 -+#define OCR2UB 1 -+#define TCN2UB 2 -+#define AS2 3 -+ -+#define OCR2 _SFR_IO8(0x23) -+ -+#define TCNT2 _SFR_IO8(0x24) -+ -+#define TCCR2 _SFR_IO8(0x25) -+#define CS20 0 -+#define CS21 1 -+#define CS22 2 -+#define WGM21 3 -+#define COM20 4 -+#define COM21 5 -+#define WGM20 6 -+#define FOC2 7 -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_IO16(0x26) -+ -+#define ICR1L _SFR_IO8(0x26) -+#define ICR1H _SFR_IO8(0x27) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_IO16(0x28) -+ -+#define OCR1BL _SFR_IO8(0x28) -+#define OCR1BH _SFR_IO8(0x29) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_IO16(0x2A) -+ -+#define OCR1AL _SFR_IO8(0x2A) -+#define OCR1AH _SFR_IO8(0x2B) -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_IO16(0x2C) -+ -+#define TCNT1L _SFR_IO8(0x2C) -+#define TCNT1H _SFR_IO8(0x2D) -+ -+#define TCCR1B _SFR_IO8(0x2E) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1A _SFR_IO8(0x2F) -+#define WGM10 0 -+#define WGM11 1 -+#define FOC1B 2 -+#define FOC1A 3 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define SFIOR _SFR_IO8(0x30) -+#define ACME 3 -+#define PSR2 1 -+#define PSR10 0 -+#define PUD 2 -+#define ADHSM 4 -+ -+#define OSCCAL _SFR_IO8(0x31) -+#define OSCCAL0 0 -+#define OSCCAL1 1 -+#define OSCCAL2 2 -+#define OSCCAL3 3 -+#define OSCCAL4 4 -+#define OSCCAL5 5 -+#define OSCCAL6 6 -+#define OSCCAL7 7 -+ -+#define TCNT0 _SFR_IO8(0x32) -+ -+#define TCCR0 _SFR_IO8(0x33) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+ -+#define MCUCSR _SFR_IO8(0x34) -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+#define SM0 4 -+#define SM1 5 -+#define SM2 6 -+#define SE 7 -+ -+#define TWCR _SFR_IO8(0x36) -+#define TWIE 0 -+#define TWEN 2 -+#define TWWC 3 -+#define TWSTO 4 -+#define TWSTA 5 -+#define TWEA 6 -+#define TWINT 7 -+ -+#define SPMCR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define BLBSET 3 -+#define RWWSRE 4 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+#define TIFR _SFR_IO8(0x38) -+#define TOV0 0 -+#define TOV1 2 -+#define OCF1B 3 -+#define OCF1A 4 -+#define ICF1 5 -+#define TOV2 6 -+#define OCF2 7 -+ -+#define TIMSK _SFR_IO8(0x39) -+#define TOIE0 0 -+#define TOIE1 2 -+#define OCIE1B 3 -+#define OCIE1A 4 -+#define TICIE1 5 -+#define TOIE2 6 -+#define OCIE2 7 -+ -+#define GIFR _SFR_IO8(0x3A) -+#define INTF0 6 -+#define INTF1 7 -+ -+#define GICR _SFR_IO8(0x3B) -+#define IVCE 0 -+#define IVSEL 1 -+#define INT0 6 -+#define INT1 7 -+ -+/* Reserved [0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* Timer/Counter2 Compare Match */ -+#define TIMER2_COMP_vect _VECTOR(3) -+#define TIMER2_COMP_vect_num 3 -+ -+/* Timer/Counter2 Overflow */ -+#define TIMER2_OVF_vect _VECTOR(4) -+#define TIMER2_OVF_vect_num 4 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(5) -+#define TIMER1_CAPT_vect_num 5 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(6) -+#define TIMER1_COMPA_vect_num 6 -+ -+/* Timer/Counter1 Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(7) -+#define TIMER1_COMPB_vect_num 7 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(8) -+#define TIMER1_OVF_vect_num 8 -+ -+/* Timer/Counter0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(9) -+#define TIMER0_OVF_vect_num 9 -+ -+/* Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(10) -+#define SPI_STC_vect_num 10 -+ -+/* USART, Rx Complete */ -+#define USART_RXC_vect _VECTOR(11) -+#define USART_RXC_vect_num 11 -+ -+/* USART Data Register Empty */ -+#define USART_UDRE_vect _VECTOR(12) -+#define USART_UDRE_vect_num 12 -+ -+/* USART, Tx Complete */ -+#define USART_TXC_vect _VECTOR(13) -+#define USART_TXC_vect_num 13 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(14) -+#define ADC_vect_num 14 -+ -+/* EEPROM Ready */ -+#define EE_RDY_vect _VECTOR(15) -+#define EE_RDY_vect_num 15 -+ -+/* Analog Comparator */ -+#define ANA_COMP_vect _VECTOR(16) -+#define ANA_COMP_vect_num 16 -+ -+/* 2-wire Serial Interface */ -+#define TWI_vect _VECTOR(17) -+#define TWI_vect_num 17 -+ -+/* Store Program Memory Ready */ -+#define SPM_RDY_vect _VECTOR(18) -+#define SPM_RDY_vect_num 18 -+ -+#define _VECTORS_SIZE 38 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 64 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x1FFF -+#define RAMSTART 0x0060 -+#define RAMSIZE 1024 -+#define RAMEND 0x045F -+#define E2START 0 -+#define E2SIZE 512 -+#define E2PAGESIZE 4 -+#define E2END 0x01FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 2 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -+#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) -+#define FUSE_BODEN (unsigned char)~_BV(6) -+#define FUSE_BODLEVEL (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_CKOPT (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_WTDON (unsigned char)~_BV(6) -+#define FUSE_RSTDISBL (unsigned char)~_BV(7) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x93 -+#define SIGNATURE_2 0x07 -+ -+ -+#endif /* #ifdef _AVR_ATMEGA8A_H_INCLUDED */ -+ -diff --git a/include/avr/iom8u2.h b/include/avr/iom8u2.h -index dacd768..680bf0f 100644 ---- a/include/avr/iom8u2.h -+++ b/include/avr/iom8u2.h -@@ -474,6 +474,12 @@ - #define DIDR1 _SFR_MEM8(0x7F) - #define AIN0D 0 - #define AIN1D 1 -+#define AIN2D 2 -+#define AIN3D 3 -+#define AIN4D 4 -+#define AIN5D 5 -+#define AIN6D 6 -+#define AIN7D 7 - - #define TCCR1A _SFR_MEM8(0x80) - #define WGM10 0 -diff --git a/include/avr/iomx8.h b/include/avr/iomx8.h -index 99ab37a..c7c1fda 100644 ---- a/include/avr/iomx8.h -+++ b/include/avr/iomx8.h -@@ -305,10 +305,13 @@ must be defined for the mega48. - #define SPMCSR _SFR_IO8 (0x37) - /* SPMCSR */ - #define SPMIE 7 --#if defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__) -+#if defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__) || (__AVR_ATmega88P__) || defined (__AVR_ATmega168P__) || (__AVR_ATmega88A__) || defined (__AVR_ATmega168A__) || (__AVR_ATmega88PA__) || defined (__AVR_ATmega168PA__) - # define RWWSB 6 - # define RWWSRE 4 - #endif -+#if defined(__AVR_ATmega48A) || defined(__AVR_ATmega48PA) || defined(__AVR_ATmega88A) || defined(__AVR_ATmega88PA) || defined(__AVR_ATmega168A) || defined(__AVR_ATmega168PA) -+ #define SIGRD 5 -+#endif - #define BLBSET 3 - #define PGWRT 2 - #define PGERS 1 -diff --git a/include/avr/iomxx4.h b/include/avr/iomxx4.h -index 9795cb1..25fccdf 100644 ---- a/include/avr/iomxx4.h -+++ b/include/avr/iomxx4.h -@@ -366,8 +366,8 @@ - - /* Reserved [0x62..0x63] */ - --#define PRR _SFR_MEM8(0x64) /* Datasheets: ATmega164P/324P/644P 8011D–AVR–02/07 -- and ATmega644 2593L–AVR–02/07. */ -+#define PRR _SFR_MEM8(0x64) /* Datasheets: ATmega164P/324P/644P 8011D�AVR�02/07 -+ and ATmega644 2593L�AVR�02/07. */ - #define PRR0 _SFR_MEM8(0x64) /* AVR Studio 4.13, build 524. */ - #define PRTWI 7 - #define PRTIM2 6 -diff --git a/include/avr/iotn13a.h b/include/avr/iotn13a.h -index 7c9c5f9..3560bba 100644 ---- a/include/avr/iotn13a.h -+++ b/include/avr/iotn13a.h -@@ -229,8 +229,8 @@ - #define COM0A1 7 - - #define BODCR _SFR_IO8(0x30) --#define BPDSE 0 --#define BPDS 1 -+#define BODSE 0 -+#define BODS 1 - - #define OSCCAL _SFR_IO8(0x31) - #define CAL0 0 -diff --git a/include/avr/iotn1634.h b/include/avr/iotn1634.h -new file mode 100644 -index 0000000..3fd91f0 ---- /dev/null -+++ b/include/avr/iotn1634.h -@@ -0,0 +1,855 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATTINY1634_H_INCLUDED -+#define _AVR_ATTINY1634_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iotn1634.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_IO16(0x00) -+#endif -+#define ADCW _SFR_IO16(0x00) -+ -+#define ADCL _SFR_IO8(0x00) -+#define ADCH _SFR_IO8(0x01) -+ -+#define ADCSRB _SFR_IO8(0x02) -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+#define ADLAR 3 -+#define VDPD 6 -+#define VDEN 7 -+ -+#define ADCSRA _SFR_IO8(0x03) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADMUX _SFR_IO8(0x04) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define ADC0EN 4 -+#define REFEN 5 -+#define REFS0 6 -+#define REFS1 7 -+ -+#define ACSRB _SFR_IO8(0x05) -+#define ACIRS0 0 -+#define ACIRS1 1 -+#define ACME 2 -+#define ACCE 3 -+#define ACLP 5 -+#define HLEV 6 -+#define HSEL 7 -+ -+#define ACSRA _SFR_IO8(0x06) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACBG 6 -+#define ACD 7 -+ -+#define PINC _SFR_IO8(0x07) -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x08) -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x09) -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PUEC _SFR_IO8(0x0A) -+#define PUEC0 0 -+#define PUEC1 1 -+#define PUEC2 2 -+#define PUEC3 3 -+#define PUEC4 4 -+#define PUEC5 5 -+ -+#define PINB _SFR_IO8(0x0B) -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x0C) -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x0D) -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PUEB _SFR_IO8(0x0E) -+#define PUEB0 0 -+#define PUEB1 1 -+#define PUEB2 2 -+#define PUEB3 3 -+ -+#define PINA _SFR_IO8(0x0F) -+#define PINA7 7 -+#define PINA6 6 -+#define PINA5 5 -+#define PINA4 4 -+#define PINA3 3 -+#define PINA2 2 -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x10) -+#define DDRA7 7 -+#define DDRA6 6 -+#define DDRA5 5 -+#define DDRA4 4 -+#define DDRA3 3 -+#define DDRA2 2 -+#define DDRA1 1 -+#define DDRA0 0 -+ -+#define PORTA _SFR_IO8(0x11) -+#define PORTA7 7 -+#define PORTA6 6 -+#define PORTA5 5 -+#define PORTA4 4 -+#define PORTA3 3 -+#define PORTA2 2 -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define PUEA _SFR_IO8(0x12) -+#define PUEA0 0 -+#define PUEA1 1 -+#define PUEA2 2 -+#define PUEA3 3 -+#define PUEA4 4 -+#define PUEA5 5 -+#define PUEA6 6 -+#define PUEA7 7 -+ -+#define PORTCR _SFR_IO8(0x13) -+#define BBMB 1 -+#define BBMC 2 -+#define BBMA 0 -+ -+#define GPIOR0 _SFR_IO8(0x14) -+ -+#define GPIOR1 _SFR_IO8(0x15) -+ -+#define GPIOR2 _SFR_IO8(0x16) -+ -+#define OCR0B _SFR_IO8(0x17) -+ -+#define OCR0A _SFR_IO8(0x18) -+ -+#define TCNT0 _SFR_IO8(0x19) -+ -+#define TCCR0B _SFR_IO8(0x1A) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define WGM02 3 -+#define FOC0B 6 -+#define FOC0A 7 -+ -+#define TCCR0A _SFR_IO8(0x1B) -+#define WGM00 0 -+#define WGM01 1 -+#define COM0B0 4 -+#define COM0B1 5 -+#define COM0A0 6 -+#define COM0A1 7 -+ -+#define EECR _SFR_IO8(0x1C) -+#define EERE 0 -+#define EEPE 1 -+#define EEMPE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+ -+#define EEDR _SFR_IO8(0x1D) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x1E) -+ -+#define EEARL _SFR_IO8(0x1E) -+#define EEARH _SFR_IO8(0x1F) -+ -+#define UDR0 _SFR_IO8(0x20) -+ -+/* Combine UBRR0L and UBRR0H */ -+#define UBRR0 _SFR_IO16(0x21) -+ -+#define UBRR0L _SFR_IO8(0x21) -+#define UBRR0H _SFR_IO8(0x22) -+ -+#define UCSR0D _SFR_IO8(0x23) -+#define SFDE0 5 -+#define RXS0 6 -+#define RXSIE0 7 -+ -+#define UCSR0C _SFR_IO8(0x24) -+#define UCPOL0 0 -+#define UCSZ00 1 -+#define UCSZ01 2 -+#define USBS0 3 -+#define UPM00 4 -+#define UPM01 5 -+#define UMSEL00 6 -+#define UMSEL01 7 -+ -+#define UCSR0B _SFR_IO8(0x25) -+#define TXB80 0 -+#define RXB80 1 -+#define UCSZ02 2 -+#define TXEN0 3 -+#define RXEN0 4 -+#define UDRIE0 5 -+#define TXCIE0 6 -+#define RXCIE0 7 -+ -+#define UCSR0A _SFR_IO8(0x26) -+#define MPCM0 0 -+#define U2X0 1 -+#define UPE0 2 -+#define DOR0 3 -+#define FE0 4 -+#define UDRE0 5 -+#define TXC0 6 -+#define RXC0 7 -+ -+#define PCMSK0 _SFR_IO8(0x27) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_IO8(0x28) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+ -+#define PCMSK2 _SFR_IO8(0x29) -+#define PCINT12 0 -+#define PCINT13 1 -+#define PCINT14 2 -+#define PCINT15 3 -+#define PCINT16 4 -+#define PCINT17 5 -+ -+#define USICR _SFR_IO8(0x2A) -+#define USITC 0 -+#define USICLK 1 -+#define USICS0 2 -+#define USICS1 3 -+#define USIWM0 4 -+#define USIWM1 5 -+#define USIOIE 6 -+#define USISIE 7 -+ -+#define USISR _SFR_IO8(0x2B) -+#define USICNT0 0 -+#define USICNT1 1 -+#define USICNT2 2 -+#define USICNT3 3 -+#define USIDC 4 -+#define USIPF 5 -+#define USIOIF 6 -+#define USISIF 7 -+ -+#define USIDR _SFR_IO8(0x2C) -+ -+#define USIBR _SFR_IO8(0x2D) -+ -+/* Reserved [0x2E] */ -+ -+#define CCP _SFR_IO8(0x2F) -+ -+#define WDTCSR _SFR_IO8(0x30) -+#define WDE 3 -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDP3 5 -+#define WDIE 6 -+#define WDIF 7 -+ -+/* Reserved [0x31] */ -+ -+#define CLKSR _SFR_IO8(0x32) -+#define CKSEL0 0 -+#define CKSEL1 1 -+#define CKSEL2 2 -+#define CKSEL3 3 -+#define SUT 4 -+#define CKOUT_IO 5 -+#define CSTR 6 -+#define OSCRDY 7 -+ -+#define CLKPR _SFR_IO8(0x33) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+ -+#define PRR _SFR_IO8(0x34) -+#define PRADC 0 -+#define PRUSART0 1 -+#define PRUSART1 2 -+#define PRUSI 3 -+#define PRTIM0 4 -+#define PRTIM1 5 -+#define PRTWI 6 -+ -+#define MCUSR _SFR_IO8(0x35) -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x36) -+#define ISC00 0 -+#define ISC01 1 -+#define SE 4 -+#define SM0 5 -+#define SM1 6 -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define RFLB 3 -+#define CTPB 4 -+#define RSIG 5 -+ -+/* Reserved [0x38] */ -+ -+#define TIFR _SFR_IO8(0x39) -+#define ICF1 3 -+#define OCF1B 5 -+#define OCF1A 6 -+#define TOV1 7 -+#define OCF0A 0 -+#define TOV0 1 -+#define OCF0B 2 -+ -+#define TIMSK _SFR_IO8(0x3A) -+#define ICIE1 3 -+#define OCIE1B 5 -+#define OCIE1A 6 -+#define TOIE1 7 -+#define OCIE0A 0 -+#define TOIE0 1 -+#define OCIE0B 2 -+ -+#define GIFR _SFR_IO8(0x3B) -+#define PCIF0 3 -+#define PCIF1 4 -+#define PCIF2 5 -+#define INTF0 6 -+ -+#define GIMSK _SFR_IO8(0x3C) -+#define PCIE0 3 -+#define PCIE1 4 -+#define PCIE2 5 -+#define INT0 6 -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define DIDR0 _SFR_MEM8(0x60) -+#define AREFD 0 -+#define AIN0D 1 -+#define AIN1D 2 -+#define ADC0D 3 -+#define ADC1D 4 -+#define ADC2D 5 -+#define ADC3D 6 -+#define ADC4D 7 -+ -+#define DIDR1 _SFR_MEM8(0x61) -+#define ADC5D 0 -+#define ADC6D 1 -+#define ADC7D 2 -+#define ADC8D 3 -+ -+#define DIDR2 _SFR_MEM8(0x62) -+#define ADC9D 0 -+#define ADC10D 1 -+#define ADC11D 2 -+ -+#define OSCCAL0 _SFR_MEM8(0x63) -+ -+#define OSCTCAL0A _SFR_MEM8(0x64) -+ -+#define OSCTCAL0B _SFR_MEM8(0x65) -+ -+#define OSCCAL1 _SFR_MEM8(0x66) -+ -+#define GTCCR _SFR_MEM8(0x67) -+#define PSR10 0 -+#define TSM 7 -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x68) -+ -+#define ICR1L _SFR_MEM8(0x68) -+#define ICR1H _SFR_MEM8(0x69) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_MEM16(0x6A) -+ -+#define OCR1BL _SFR_MEM8(0x6A) -+#define OCR1BH _SFR_MEM8(0x6B) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_MEM16(0x6C) -+ -+#define OCR1AL _SFR_MEM8(0x6C) -+#define OCR1AH _SFR_MEM8(0x6D) -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x6E) -+ -+#define TCNT1L _SFR_MEM8(0x6E) -+#define TCNT1H _SFR_MEM8(0x6F) -+ -+#define TCCR1C _SFR_MEM8(0x70) -+#define FOC1B 6 -+#define FOC1A 7 -+ -+#define TCCR1B _SFR_MEM8(0x71) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1A _SFR_MEM8(0x72) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define UDR1 _SFR_MEM8(0x73) -+ -+/* Combine UBRR1L and UBRR1H */ -+#define UBRR1 _SFR_MEM16(0x74) -+ -+#define UBRR1L _SFR_MEM8(0x74) -+#define UBRR1H _SFR_MEM8(0x75) -+ -+#define UCSR1D _SFR_MEM8(0x76) -+#define SFDE1 5 -+#define RXS1 6 -+#define RXSIE1 7 -+ -+#define UCSR1C _SFR_MEM8(0x77) -+#define UCPOL1 0 -+#define UCSZ10 1 -+#define UCSZ11 2 -+#define USBS1 3 -+#define UPM10 4 -+#define UPM11 5 -+#define UMSEL10 6 -+#define UMSEL11 7 -+ -+#define UCSR1B _SFR_MEM8(0x78) -+#define TXB81 0 -+#define RXB81 1 -+#define UCSZ12 2 -+#define TXEN1 3 -+#define RXEN1 4 -+#define UDRIE1 5 -+#define TXCIE1 6 -+#define RXCIE1 7 -+ -+#define UCSR1A _SFR_MEM8(0x79) -+#define MPCM1 0 -+#define U2X1 1 -+#define UPE1 2 -+#define DOR1 3 -+#define FE1 4 -+#define UDRE1 5 -+#define TXC1 6 -+#define RXC1 7 -+ -+#define TWSD _SFR_MEM8(0x7A) -+#define TWSD0 0 -+#define TWSD1 1 -+#define TWSD2 2 -+#define TWSD3 3 -+#define TWSD4 4 -+#define TWSD5 5 -+#define TWSD6 6 -+#define TWSD7 7 -+ -+#define TWSAM _SFR_MEM8(0x7B) -+ -+#define TWSA _SFR_MEM8(0x7C) -+#define TWSA0 0 -+#define TWSA1 1 -+#define TWSA2 2 -+#define TWSA3 3 -+#define TWSA4 4 -+#define TWSA5 5 -+#define TWSA6 6 -+#define TWSA7 7 -+ -+#define TWSSRA _SFR_MEM8(0x7D) -+#define TWAS 0 -+#define TWDIR 1 -+#define TWBE 2 -+#define TWC 3 -+#define TWRA 4 -+#define TWCH 5 -+#define TWASIF 6 -+#define TWDIF 7 -+ -+#define TWSCRB _SFR_MEM8(0x7E) -+#define TWCMD0 0 -+#define TWCMD1 1 -+#define TWAA 2 -+ -+#define TWSCRA _SFR_MEM8(0x7F) -+#define TWSME 0 -+#define TWPME 1 -+#define TWSIE 2 -+#define TWEN 3 -+#define TWASIE 4 -+#define TWDIE 5 -+#define TWSHE 7 -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(2) -+#define PCINT0_vect_num 2 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(3) -+#define PCINT1_vect_num 3 -+ -+/* Pin Change Interrupt Request 2 */ -+#define PCINT2_vect _VECTOR(4) -+#define PCINT2_vect_num 4 -+ -+/* Watchdog Time-out Interrupt */ -+#define WDT_vect _VECTOR(5) -+#define WDT_vect_num 5 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(6) -+#define TIMER1_CAPT_vect_num 6 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIM1_CAPT_vect _VECTOR(6) -+#define TIM1_CAPT_vect_num 6 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(7) -+#define TIMER1_COMPA_vect_num 7 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIM1_COMPA_vect _VECTOR(7) -+#define TIM1_COMPA_vect_num 7 -+ -+/* Timer/Counter1 Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(8) -+#define TIMER1_COMPB_vect_num 8 -+ -+/* Timer/Counter1 Compare Match B */ -+#define TIM1_COMPB_vect _VECTOR(8) -+#define TIM1_COMPB_vect_num 8 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(9) -+#define TIMER1_OVF_vect_num 9 -+ -+/* Timer/Counter1 Overflow */ -+#define TIM1_OVF_vect _VECTOR(9) -+#define TIM1_OVF_vect_num 9 -+ -+/* TimerCounter0 Compare Match A */ -+#define TIMER0_COMPA_vect _VECTOR(10) -+#define TIMER0_COMPA_vect_num 10 -+ -+/* TimerCounter0 Compare Match A */ -+#define TIM0_COMPA_vect _VECTOR(10) -+#define TIM0_COMPA_vect_num 10 -+ -+/* TimerCounter0 Compare Match B */ -+#define TIMER0_COMPB_vect _VECTOR(11) -+#define TIMER0_COMPB_vect_num 11 -+ -+/* TimerCounter0 Compare Match B */ -+#define TIM0_COMPB_vect _VECTOR(11) -+#define TIM0_COMPB_vect_num 11 -+ -+/* Timer/Couner0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(12) -+#define TIMER0_OVF_vect_num 12 -+ -+/* Timer/Couner0 Overflow */ -+#define TIM0_OVF_vect _VECTOR(12) -+#define TIM0_OVF_vect_num 12 -+ -+/* Analog Comparator */ -+#define ANA_COMP_vect _VECTOR(13) -+#define ANA_COMP_vect_num 13 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(14) -+#define ADC_vect_num 14 -+ -+/* ADC Conversion Complete */ -+#define ADC_READY_vect _VECTOR(14) -+#define ADC_READY_vect_num 14 -+ -+/* USART0, Start */ -+#define USART0_START_vect _VECTOR(15) -+#define USART0_START_vect_num 15 -+ -+/* USART0, Start */ -+#define USART0_RXS_vect _VECTOR(15) -+#define USART0_RXS_vect_num 15 -+ -+/* USART0, Rx Complete */ -+#define USART0_RX_vect _VECTOR(16) -+#define USART0_RX_vect_num 16 -+ -+/* USART0, Rx Complete */ -+#define USART0_RXC_vect _VECTOR(16) -+#define USART0_RXC_vect_num 16 -+ -+/* USART0 Data Register Empty */ -+#define USART0_UDRE_vect _VECTOR(17) -+#define USART0_UDRE_vect_num 17 -+ -+/* USART0 Data Register Empty */ -+#define USART0_DRE_vect _VECTOR(17) -+#define USART0_DRE_vect_num 17 -+ -+/* USART0, Tx Complete */ -+#define USART0_TX_vect _VECTOR(18) -+#define USART0_TX_vect_num 18 -+ -+/* USART0, Tx Complete */ -+#define USART0_TXC_vect _VECTOR(18) -+#define USART0_TXC_vect_num 18 -+ -+/* USART1, Start */ -+#define USART1_START_vect _VECTOR(19) -+#define USART1_START_vect_num 19 -+ -+/* USART1, Start */ -+#define USART1_RXS_vect _VECTOR(19) -+#define USART1_RXS_vect_num 19 -+ -+/* USART1, Rx Complete */ -+#define USART1_RX_vect _VECTOR(20) -+#define USART1_RX_vect_num 20 -+ -+/* USART1, Rx Complete */ -+#define USART1_RXC_vect _VECTOR(20) -+#define USART1_RXC_vect_num 20 -+ -+/* USART1 Data Register Empty */ -+#define USART1_UDRE_vect _VECTOR(21) -+#define USART1_UDRE_vect_num 21 -+ -+/* USART1 Data Register Empty */ -+#define USART1_DRE_vect _VECTOR(21) -+#define USART1_DRE_vect_num 21 -+ -+/* USART1, Tx Complete */ -+#define USART1_TX_vect _VECTOR(22) -+#define USART1_TX_vect_num 22 -+ -+/* USART1, Tx Complete */ -+#define USART1_TXC_vect _VECTOR(22) -+#define USART1_TXC_vect_num 22 -+ -+/* USI Start Condition */ -+#define USI_START_vect _VECTOR(23) -+#define USI_START_vect_num 23 -+ -+/* USI Start Condition */ -+#define USI_STR_vect _VECTOR(23) -+#define USI_STR_vect_num 23 -+ -+/* USI Overflow */ -+#define USI_OVERFLOW_vect _VECTOR(24) -+#define USI_OVERFLOW_vect_num 24 -+ -+/* USI Overflow */ -+#define USI_OVF_vect _VECTOR(24) -+#define USI_OVF_vect_num 24 -+ -+/* Two-wire Serial Interface */ -+#define TWI_SLAVE_vect _VECTOR(25) -+#define TWI_SLAVE_vect_num 25 -+ -+/* Two-wire Serial Interface */ -+#define TWI_vect _VECTOR(25) -+#define TWI_vect_num 25 -+ -+/* EEPROM Ready */ -+#define EE_RDY_vect _VECTOR(26) -+#define EE_RDY_vect_num 26 -+ -+/* Touch Sensing */ -+#define QTRIP_vect _VECTOR(27) -+#define QTRIP_vect_num 27 -+ -+#define _VECTORS_SIZE 112 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 32 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x3FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 1024 -+#define RAMEND 0x04FF -+#define E2START 0 -+#define E2SIZE 256 -+#define E2PAGESIZE 4 -+#define E2END 0x00FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_DWEN (unsigned char)~_BV(6) -+#define FUSE_RSTDISBL (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_SELFPRGEN (unsigned char)~_BV(0) -+#define FUSE_BODACT0 (unsigned char)~_BV(1) -+#define FUSE_BODACT1 (unsigned char)~_BV(2) -+#define FUSE_BODPD0 (unsigned char)~_BV(3) -+#define FUSE_BODPD1 (unsigned char)~_BV(4) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x94 -+#define SIGNATURE_2 0x12 -+ -+ -+#endif /* #ifdef _AVR_ATTINY1634_H_INCLUDED */ -+ -diff --git a/include/avr/iotn167.h b/include/avr/iotn167.h -index 04ee489..fdd5f33 100644 ---- a/include/avr/iotn167.h -+++ b/include/avr/iotn167.h -@@ -114,7 +114,7 @@ - - #define PORTCR _SFR_IO8(0x12) - #define PUDA 0 --#define PUDB 2 -+#define PUDB 1 - #define BBMA 4 - #define BBMB 5 - -diff --git a/include/avr/iotn2313a.h b/include/avr/iotn2313a.h -index 6c6db60..c5da4c7 100644 ---- a/include/avr/iotn2313a.h -+++ b/include/avr/iotn2313a.h -@@ -68,7 +68,12 @@ - #define USBS 3 - #define UPM0 4 - #define UPM1 5 --#define UMSEL 6 -+#define UMSEL0 6 -+#define UMSEL1 7 -+ -+/* When in MSPIM mode*/ -+#define UCPHA 1 -+#define UDORD 2 - - #define PCMSK1 _SFR_IO8(0x004) - #define PCINT8 0 -@@ -303,7 +308,7 @@ - #define EEAR5 5 - #define EEAR6 6 - --#define PCMSK _SFR_IO8(0x020) -+#define PCMSK0 _SFR_IO8(0x020) - #define PCINT0 0 - #define PCINT1 1 - #define PCINT2 2 -@@ -528,13 +533,17 @@ - #define OCIE1A 6 - #define TOIE1 7 - --#define EIFR _SFR_IO8(0x03A) --#define PCIF 5 -+#define GIFR _SFR_IO8(0x03A) -+#define PCIF0 5 -+#define PCIF2 4 -+#define PCIF1 3 - #define INTF0 6 - #define INTF1 7 - - #define GIMSK _SFR_IO8(0x03B) --#define PCIE 5 -+#define PCIE1 3 -+#define PCIE2 4 -+#define PCIE0 5 - #define INT0 6 - #define INT1 7 - -@@ -563,16 +572,16 @@ - #define TIMER1_OVF_vect _VECTOR(5) /* Timer/Counter1 Overflow */ - #define TIMER0_OVF_vect_num 6 - #define TIMER0_OVF_vect _VECTOR(6) /* Timer/Counter0 Overflow */ --#define USART_RX_vect_num 7 --#define USART_RX_vect _VECTOR(7) /* USART, Rx Complete */ --#define USART_UDRE_vect_num 8 --#define USART_UDRE_vect _VECTOR(8) /* USART Data Register Empty */ --#define USART_TX_vect_num 9 --#define USART_TX_vect _VECTOR(9) /* USART, Tx Complete */ -+#define USART0_RX_vect_num 7 -+#define USART0_RX_vect _VECTOR(7) /* USART, Rx Complete */ -+#define USART0_UDRE_vect_num 8 -+#define USART0_UDRE_vect _VECTOR(8) /* USART Data Register Empty */ -+#define USART0_TX_vect_num 9 -+#define USART0_TX_vect _VECTOR(9) /* USART, Tx Complete */ - #define ANA_COMP_vect_num 10 - #define ANA_COMP_vect _VECTOR(10) /* Analog Comparator */ --#define PCINT_B_vect_num 11 --#define PCINT_B_vect _VECTOR(11) /* Pin Change Interrupt Request B */ -+#define PCINT0_vect_num 11 -+#define PCINT0_vect _VECTOR(11) /* Pin Change Interrupt Request 0 */ - #define TIMER1_COMPB_vect_num 12 - #define TIMER1_COMPB_vect _VECTOR(12) /* */ - #define TIMER0_COMPA_vect_num 13 -@@ -583,14 +592,14 @@ - #define USI_START_vect _VECTOR(15) /* USI Start Condition */ - #define USI_OVERFLOW_vect_num 16 - #define USI_OVERFLOW_vect _VECTOR(16) /* USI Overflow */ -+#define EEPROM_Ready_vect_num 17 -+#define EEPROM_Ready_vect _VECTOR(17) /* EEPROM Ready */ - #define WDT_OVERFLOW_vect_num 18 - #define WDT_OVERFLOW_vect _VECTOR(18) /* Watchdog Timer Overflow */ --#define PCINT_D_vect_num 20 --#define PCINT_D_vect _VECTOR(20) /* Pin Change Interrupt Request D */ --#define EEPROM_Ready_vect_num 17 --#define EEPROM_Ready_vect _VECTOR(17) /* */ --#define PCINT_A_vect_num 19 --#define PCINT_A_vect _VECTOR(19) /* Pin Change Interrupt Request A */ -+#define PCINT1_vect_num 19 -+#define PCINT1_vect _VECTOR(19) /* Pin Change Interrupt Request 1 */ -+#define PCINT2_vect_num 20 -+#define PCINT2_vect _VECTOR(20) /* Pin Change Interrupt Request 2 */ - - #define _VECTOR_SIZE 2 /* Size of individual vector. */ - #define _VECTORS_SIZE (21 * _VECTOR_SIZE) -@@ -624,14 +633,14 @@ - #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) - - /* High Fuse Byte */ ++/***************************************************************************** ++ * ++ * Copyright (C) 2011 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++#include "iom88.h" +diff --git a/include/avr/iom88p.h b/include/avr/iom88p.h +index b51c7de..6498ab1 100644 +--- a/include/avr/iom88p.h ++++ b/include/avr/iom88p.h +@@ -1,924 +1,926 @@ +-/* Copyright (c) 2007 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. +-*/ +- +-/* $Id: iom88p.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* avr/iom88p.h - definitions for ATmega88P. */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom88p.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_IOM88P_H_ +-#define _AVR_IOM88P_H_ 1 +- +-/* Registers and associated bit numbers */ +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC3 3 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC3 3 +-#define PORTC4 4 +-#define PORTC5 5 +-#define PORTC6 6 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define TIFR2 _SFR_IO8(0x17) +-#define TOV2 0 +-#define OCF2A 1 +-#define OCF2B 2 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +-#define PCIF1 1 +-#define PCIF2 2 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +- +-#define EEPROM_REG_LOCATIONS 1F2021 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSRSYNC 0 +-#define PSRASY 1 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define OCR0A _SFR_IO8(0x27) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define OCR0B _SFR_IO8(0x28) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define BODSE 5 +-#define BODS 6 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SELFPRGEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM1 3 +-#define PRTIM0 5 +-#define PRTIM2 6 +-#define PRTWI 7 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +-#define PCIE1 1 +-#define PCIE2 2 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +- +-#define PCMSK2 _SFR_MEM8(0x6D) +-#define PCINT16 0 +-#define PCINT17 1 +-#define PCINT18 2 +-#define PCINT19 3 +-#define PCINT20 4 +-#define PCINT21 5 +-#define PCINT22 6 +-#define PCINT23 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define TIMSK2 _SFR_MEM8(0x70) +-#define TOIE2 0 +-#define OCIE2A 1 +-#define OCIE2B 2 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +- +-#define ADCL _SFR_MEM8(0x78) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_MEM8(0x79) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ACME 6 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define TCCR2A _SFR_MEM8(0xB0) +-#define WGM20 0 +-#define WGM21 1 +-#define COM2B0 4 +-#define COM2B1 5 +-#define COM2A0 6 +-#define COM2A1 7 +- +-#define TCCR2B _SFR_MEM8(0xB1) +-#define CS20 0 +-#define CS21 1 +-#define CS22 2 +-#define WGM22 3 +-#define FOC2B 6 +-#define FOC2A 7 +- +-#define TCNT2 _SFR_MEM8(0xB2) +-#define TCNT2_0 0 +-#define TCNT2_1 1 +-#define TCNT2_2 2 +-#define TCNT2_3 3 +-#define TCNT2_4 4 +-#define TCNT2_5 5 +-#define TCNT2_6 6 +-#define TCNT2_7 7 +- +-#define OCR2A _SFR_MEM8(0xB3) +-#define OCR2_0 0 +-#define OCR2_1 1 +-#define OCR2_2 2 +-#define OCR2_3 3 +-#define OCR2_4 4 +-#define OCR2_5 5 +-#define OCR2_6 6 +-#define OCR2_7 7 +- +-#define OCR2B _SFR_MEM8(0xB4) +-#define OCR2_0 0 +-#define OCR2_1 1 +-#define OCR2_2 2 +-#define OCR2_3 3 +-#define OCR2_4 4 +-#define OCR2_5 5 +-#define OCR2_6 6 +-#define OCR2_7 7 +- +-#define ASSR _SFR_MEM8(0xB6) +-#define TCR2BUB 0 +-#define TCR2AUB 1 +-#define OCR2BUB 2 +-#define OCR2AUB 3 +-#define TCN2UB 4 +-#define AS2 5 +-#define EXCLK 6 +- +-#define TWBR _SFR_MEM8(0xB8) +-#define TWBR0 0 +-#define TWBR1 1 +-#define TWBR2 2 +-#define TWBR3 3 +-#define TWBR4 4 +-#define TWBR5 5 +-#define TWBR6 6 +-#define TWBR7 7 +- +-#define TWSR _SFR_MEM8(0xB9) +-#define TWPS0 0 +-#define TWPS1 1 +-#define TWS3 3 +-#define TWS4 4 +-#define TWS5 5 +-#define TWS6 6 +-#define TWS7 7 +- +-#define TWAR _SFR_MEM8(0xBA) +-#define TWGCE 0 +-#define TWA0 1 +-#define TWA1 2 +-#define TWA2 3 +-#define TWA3 4 +-#define TWA4 5 +-#define TWA5 6 +-#define TWA6 7 +- +-#define TWDR _SFR_MEM8(0xBB) +-#define TWD0 0 +-#define TWD1 1 +-#define TWD2 2 +-#define TWD3 3 +-#define TWD4 4 +-#define TWD5 5 +-#define TWD6 6 +-#define TWD7 7 +- +-#define TWCR _SFR_MEM8(0xBC) +-#define TWIE 0 +-#define TWEN 2 +-#define TWWC 3 +-#define TWSTO 4 +-#define TWSTA 5 +-#define TWEA 6 +-#define TWINT 7 +- +-#define TWAMR _SFR_MEM8(0xBD) +-#define TWAM0 0 +-#define TWAM1 1 +-#define TWAM2 2 +-#define TWAM3 3 +-#define TWAM4 4 +-#define TWAM5 5 +-#define TWAM6 6 +- +-#define UCSR0A _SFR_MEM8(0xC0) +-#define MPCM0 0 +-#define U2X0 1 +-#define UPE0 2 +-#define DOR0 3 +-#define FE0 4 +-#define UDRE0 5 +-#define TXC0 6 +-#define RXC0 7 +- +-#define UCSR0B _SFR_MEM8(0xC1) +-#define TXB80 0 +-#define RXB80 1 +-#define UCSZ02 2 +-#define TXEN0 3 +-#define RXEN0 4 +-#define UDRIE0 5 +-#define TXCIE0 6 +-#define RXCIE0 7 +- +-#define UCSR0C _SFR_MEM8(0xC2) +-#define UCPOL0 0 +-#define UCSZ00 1 +-#define UCPHA0 1 +-#define UCSZ01 2 +-#define UDORD0 2 +-#define USBS0 3 +-#define UPM00 4 +-#define UPM01 5 +-#define UMSEL00 6 +-#define UMSEL01 7 +- +-#define UBRR0 _SFR_MEM16(0xC4) +- +-#define UBRR0L _SFR_MEM8(0xC4) +-#define UBRR0_0 0 +-#define UBRR0_1 1 +-#define UBRR0_2 2 +-#define UBRR0_3 3 +-#define UBRR0_4 4 +-#define UBRR0_5 5 +-#define UBRR0_6 6 +-#define UBRR0_7 7 +- +-#define UBRR0H _SFR_MEM8(0xC5) +-#define UBRR0_8 0 +-#define UBRR0_9 1 +-#define UBRR0_10 2 +-#define UBRR0_11 3 +- +-#define UDR0 _SFR_MEM8(0xC6) +-#define UDR0_0 0 +-#define UDR0_1 1 +-#define UDR0_2 2 +-#define UDR0_3 3 +-#define UDR0_4 4 +-#define UDR0_5 5 +-#define UDR0_6 6 +-#define UDR0_7 7 +- +- +- +-/* Interrupt Vectors */ +-/* Interrupt Vector 0 is the reset vector. */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +- +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ +- +-#define PCINT0_vect_num 3 +-#define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ +- +-#define PCINT1_vect_num 4 +-#define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */ +- +-#define PCINT2_vect_num 5 +-#define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */ +- +-#define WDT_vect_num 6 +-#define WDT_vect _VECTOR(6) /* Watchdog Time-out Interrupt */ +- +-#define TIMER2_COMPA_vect_num 7 +-#define TIMER2_COMPA_vect _VECTOR(7) /* Timer/Counter2 Compare Match A */ +- +-#define TIMER2_COMPB_vect_num 8 +-#define TIMER2_COMPB_vect _VECTOR(8) /* Timer/Counter2 Compare Match A */ +- +-#define TIMER2_OVF_vect_num 9 +-#define TIMER2_OVF_vect _VECTOR(9) /* Timer/Counter2 Overflow */ +- +-#define TIMER1_CAPT_vect_num 10 +-#define TIMER1_CAPT_vect _VECTOR(10) /* Timer/Counter1 Capture Event */ +- +-#define TIMER1_COMPA_vect_num 11 +-#define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */ +- +-#define TIMER1_COMPB_vect_num 12 +-#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */ +- +-#define TIMER1_OVF_vect_num 13 +-#define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */ +- +-#define TIMER0_COMPA_vect_num 14 +-#define TIMER0_COMPA_vect _VECTOR(14) /* TimerCounter0 Compare Match A */ +- +-#define TIMER0_COMPB_vect_num 15 +-#define TIMER0_COMPB_vect _VECTOR(15) /* TimerCounter0 Compare Match B */ +- +-#define TIMER0_OVF_vect_num 16 +-#define TIMER0_OVF_vect _VECTOR(16) /* Timer/Couner0 Overflow */ +- +-#define SPI_STC_vect_num 17 +-#define SPI_STC_vect _VECTOR(17) /* SPI Serial Transfer Complete */ +- +-#define USART_RX_vect_num 18 +-#define USART_RX_vect _VECTOR(18) /* USART Rx Complete */ +- +-#define USART_UDRE_vect_num 19 +-#define USART_UDRE_vect _VECTOR(19) /* USART, Data Register Empty */ +- +-#define USART_TX_vect_num 20 +-#define USART_TX_vect _VECTOR(20) /* USART Tx Complete */ +- +-#define ADC_vect_num 21 +-#define ADC_vect _VECTOR(21) /* ADC Conversion Complete */ +- +-#define EE_READY_vect_num 22 +-#define EE_READY_vect _VECTOR(22) /* EEPROM Ready */ +- +-#define ANALOG_COMP_vect_num 23 +-#define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */ +- +-#define TWI_vect_num 24 +-#define TWI_vect _VECTOR(24) /* Two-wire Serial Interface */ +- +-#define SPM_READY_vect_num 25 +-#define SPM_READY_vect _VECTOR(25) /* Store Program Memory Read */ +- +-#define _VECTORS_SIZE (26 * 2) +- +- +- +-/* Constants */ +-#define SPM_PAGESIZE 64 +-#define RAMSTART (0x100) +-#define RAMEND 0x4FF /* Last On-Chip SRAM Location */ +-#define XRAMSIZE 0 +-#define XRAMEND RAMEND +-#define E2END 0x1FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x1FFF +- +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) +- +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x93 +-#define SIGNATURE_2 0x0F +- +- +-#endif /* _AVR_IOM88P_H_ */ ++/* Copyright (c) 2007 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++/* $Id: iom88p.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* avr/iom88p.h - definitions for ATmega88P. */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom88p.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_IOM88P_H_ ++#define _AVR_IOM88P_H_ 1 ++ ++/* Registers and associated bit numbers */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC3 3 ++#define PORTC4 4 ++#define PORTC5 5 ++#define PORTC6 6 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++ ++#define EEPROM_REG_LOCATIONS 1F2021 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define PSRASY 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define OCR0A _SFR_IO8(0x27) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define OCR0B _SFR_IO8(0x28) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SELFPRGEN 0 ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_MEM8(0x79) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++#define TCNT2_0 0 ++#define TCNT2_1 1 ++#define TCNT2_2 2 ++#define TCNT2_3 3 ++#define TCNT2_4 4 ++#define TCNT2_5 5 ++#define TCNT2_6 6 ++#define TCNT2_7 7 ++ ++#define OCR2A _SFR_MEM8(0xB3) ++#define OCR2_0 0 ++#define OCR2_1 1 ++#define OCR2_2 2 ++#define OCR2_3 3 ++#define OCR2_4 4 ++#define OCR2_5 5 ++#define OCR2_6 6 ++#define OCR2_7 7 ++ ++#define OCR2B _SFR_MEM8(0xB4) ++#define OCR2_0 0 ++#define OCR2_1 1 ++#define OCR2_2 2 ++#define OCR2_3 3 ++#define OCR2_4 4 ++#define OCR2_5 5 ++#define OCR2_6 6 ++#define OCR2_7 7 ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++ ++#define TWBR _SFR_MEM8(0xB8) ++#define TWBR0 0 ++#define TWBR1 1 ++#define TWBR2 2 ++#define TWBR3 3 ++#define TWBR4 4 ++#define TWBR5 5 ++#define TWBR6 6 ++#define TWBR7 7 ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++#define TWD0 0 ++#define TWD1 1 ++#define TWD2 2 ++#define TWD3 3 ++#define TWD4 4 ++#define TWD5 5 ++#define TWD6 6 ++#define TWD7 7 ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 0 ++#define TWAM1 1 ++#define TWAM2 2 ++#define TWAM3 3 ++#define TWAM4 4 ++#define TWAM5 5 ++#define TWAM6 6 ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCPHA0 1 ++#define UCSZ01 2 ++#define UDORD0 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0_0 0 ++#define UBRR0_1 1 ++#define UBRR0_2 2 ++#define UBRR0_3 3 ++#define UBRR0_4 4 ++#define UBRR0_5 5 ++#define UBRR0_6 6 ++#define UBRR0_7 7 ++ ++#define UBRR0H _SFR_MEM8(0xC5) ++#define UBRR0_8 0 ++#define UBRR0_9 1 ++#define UBRR0_10 2 ++#define UBRR0_11 3 ++ ++#define UDR0 _SFR_MEM8(0xC6) ++#define UDR0_0 0 ++#define UDR0_1 1 ++#define UDR0_2 2 ++#define UDR0_3 3 ++#define UDR0_4 4 ++#define UDR0_5 5 ++#define UDR0_6 6 ++#define UDR0_7 7 ++ ++ ++ ++/* Interrupt Vectors */ ++/* Interrupt Vector 0 is the reset vector. */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ ++ ++#define PCINT0_vect_num 3 ++#define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ ++ ++#define PCINT1_vect_num 4 ++#define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */ ++ ++#define PCINT2_vect_num 5 ++#define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */ ++ ++#define WDT_vect_num 6 ++#define WDT_vect _VECTOR(6) /* Watchdog Time-out Interrupt */ ++ ++#define TIMER2_COMPA_vect_num 7 ++#define TIMER2_COMPA_vect _VECTOR(7) /* Timer/Counter2 Compare Match A */ ++ ++#define TIMER2_COMPB_vect_num 8 ++#define TIMER2_COMPB_vect _VECTOR(8) /* Timer/Counter2 Compare Match A */ ++ ++#define TIMER2_OVF_vect_num 9 ++#define TIMER2_OVF_vect _VECTOR(9) /* Timer/Counter2 Overflow */ ++ ++#define TIMER1_CAPT_vect_num 10 ++#define TIMER1_CAPT_vect _VECTOR(10) /* Timer/Counter1 Capture Event */ ++ ++#define TIMER1_COMPA_vect_num 11 ++#define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */ ++ ++#define TIMER1_COMPB_vect_num 12 ++#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */ ++ ++#define TIMER1_OVF_vect_num 13 ++#define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */ ++ ++#define TIMER0_COMPA_vect_num 14 ++#define TIMER0_COMPA_vect _VECTOR(14) /* TimerCounter0 Compare Match A */ ++ ++#define TIMER0_COMPB_vect_num 15 ++#define TIMER0_COMPB_vect _VECTOR(15) /* TimerCounter0 Compare Match B */ ++ ++#define TIMER0_OVF_vect_num 16 ++#define TIMER0_OVF_vect _VECTOR(16) /* Timer/Couner0 Overflow */ ++ ++#define SPI_STC_vect_num 17 ++#define SPI_STC_vect _VECTOR(17) /* SPI Serial Transfer Complete */ ++ ++#define USART_RX_vect_num 18 ++#define USART_RX_vect _VECTOR(18) /* USART Rx Complete */ ++ ++#define USART_UDRE_vect_num 19 ++#define USART_UDRE_vect _VECTOR(19) /* USART, Data Register Empty */ ++ ++#define USART_TX_vect_num 20 ++#define USART_TX_vect _VECTOR(20) /* USART Tx Complete */ ++ ++#define ADC_vect_num 21 ++#define ADC_vect _VECTOR(21) /* ADC Conversion Complete */ ++ ++#define EE_READY_vect_num 22 ++#define EE_READY_vect _VECTOR(22) /* EEPROM Ready */ ++ ++#define ANALOG_COMP_vect_num 23 ++#define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */ ++ ++#define TWI_vect_num 24 ++#define TWI_vect _VECTOR(24) /* Two-wire Serial Interface */ ++ ++#define SPM_READY_vect_num 25 ++#define SPM_READY_vect _VECTOR(25) /* Store Program Memory Read */ ++ ++#define _VECTORS_SIZE (26 * 2) ++ ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE 64 ++#define RAMSTART (0x100) ++#define RAMEND 0x4FF /* Last On-Chip SRAM Location */ ++#define XRAMSIZE 0 ++#define XRAMEND RAMEND ++#define E2END 0x1FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x1FFF ++ ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define EFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1) ++ ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x0F ++ ++ ++#endif /* _AVR_IOM88P_H_ */ +diff --git a/include/avr/iom88pa.h b/include/avr/iom88pa.h +index 62efee3..0b7522e 100644 +--- a/include/avr/iom88pa.h ++++ b/include/avr/iom88pa.h +@@ -1,1167 +1,1169 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom88pa.h 2035 2009-11-02 02:44:17Z arcanum $ */ +- +-/* avr/iom88pa.h - definitions for ATmega88PA */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom88pa.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATmega88PA_H_ +-#define _AVR_ATmega88PA_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC3 3 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC3 3 +-#define PORTC4 4 +-#define PORTC5 5 +-#define PORTC6 6 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define TIFR2 _SFR_IO8(0x17) +-#define TOV2 0 +-#define OCF2A 1 +-#define OCF2B 2 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +-#define PCIF1 1 +-#define PCIF2 2 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSRSYNC 0 +-#define PSRASY 1 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define OCR0A _SFR_IO8(0x27) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define OCR0B _SFR_IO8(0x28) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +-#define BODSE 5 +-#define BODS 6 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SELFPRGEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSART0 1 +-#define PRSPI 2 +-#define PRTIM1 3 +-#define PRTIM0 5 +-#define PRTIM2 6 +-#define PRTWI 7 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +-#define PCIE1 1 +-#define PCIE2 2 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +- +-#define PCMSK2 _SFR_MEM8(0x6D) +-#define PCINT16 0 +-#define PCINT17 1 +-#define PCINT18 2 +-#define PCINT19 3 +-#define PCINT20 4 +-#define PCINT21 5 +-#define PCINT22 6 +-#define PCINT23 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define TIMSK2 _SFR_MEM8(0x70) +-#define TOIE2 0 +-#define OCIE2A 1 +-#define OCIE2B 2 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +- +-#define ADCL _SFR_MEM8(0x78) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_MEM8(0x79) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ACME 6 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define TCCR2A _SFR_MEM8(0xB0) +-#define WGM20 0 +-#define WGM21 1 +-#define COM2B0 4 +-#define COM2B1 5 +-#define COM2A0 6 +-#define COM2A1 7 +- +-#define TCCR2B _SFR_MEM8(0xB1) +-#define CS20 0 +-#define CS21 1 +-#define CS22 2 +-#define WGM22 3 +-#define FOC2B 6 +-#define FOC2A 7 +- +-#define TCNT2 _SFR_MEM8(0xB2) +-#define TCNT2_0 0 +-#define TCNT2_1 1 +-#define TCNT2_2 2 +-#define TCNT2_3 3 +-#define TCNT2_4 4 +-#define TCNT2_5 5 +-#define TCNT2_6 6 +-#define TCNT2_7 7 +- +-#define OCR2A _SFR_MEM8(0xB3) +-#define OCR2A_0 0 +-#define OCR2A_1 1 +-#define OCR2A_2 2 +-#define OCR2A_3 3 +-#define OCR2A_4 4 +-#define OCR2A_5 5 +-#define OCR2A_6 6 +-#define OCR2A_7 7 +- +-#define OCR2B _SFR_MEM8(0xB4) +-#define OCR2B_0 0 +-#define OCR2B_1 1 +-#define OCR2B_2 2 +-#define OCR2B_3 3 +-#define OCR2B_4 4 +-#define OCR2B_5 5 +-#define OCR2B_6 6 +-#define OCR2B_7 7 +- +-#define ASSR _SFR_MEM8(0xB6) +-#define TCR2BUB 0 +-#define TCR2AUB 1 +-#define OCR2BUB 2 +-#define OCR2AUB 3 +-#define TCN2UB 4 +-#define AS2 5 +-#define EXCLK 6 +- +-#define TWBR _SFR_MEM8(0xB8) +-#define TWBR0 0 +-#define TWBR1 1 +-#define TWBR2 2 +-#define TWBR3 3 +-#define TWBR4 4 +-#define TWBR5 5 +-#define TWBR6 6 +-#define TWBR7 7 +- +-#define TWSR _SFR_MEM8(0xB9) +-#define TWPS0 0 +-#define TWPS1 1 +-#define TWS3 3 +-#define TWS4 4 +-#define TWS5 5 +-#define TWS6 6 +-#define TWS7 7 +- +-#define TWAR _SFR_MEM8(0xBA) +-#define TWGCE 0 +-#define TWA0 1 +-#define TWA1 2 +-#define TWA2 3 +-#define TWA3 4 +-#define TWA4 5 +-#define TWA5 6 +-#define TWA6 7 +- +-#define TWDR _SFR_MEM8(0xBB) +-#define TWD0 0 +-#define TWD1 1 +-#define TWD2 2 +-#define TWD3 3 +-#define TWD4 4 +-#define TWD5 5 +-#define TWD6 6 +-#define TWD7 7 +- +-#define TWCR _SFR_MEM8(0xBC) +-#define TWIE 0 +-#define TWEN 2 +-#define TWWC 3 +-#define TWSTO 4 +-#define TWSTA 5 +-#define TWEA 6 +-#define TWINT 7 +- +-#define TWAMR _SFR_MEM8(0xBD) +-#define TWAM0 1 +-#define TWAM1 2 +-#define TWAM2 3 +-#define TWAM3 4 +-#define TWAM4 5 +-#define TWAM5 6 +-#define TWAM6 7 +- +-#define UCSR0A _SFR_MEM8(0xC0) +-#define MPCM0 0 +-#define U2X0 1 +-#define UPE0 2 +-#define DOR0 3 +-#define FE0 4 +-#define UDRE0 5 +-#define TXC0 6 +-#define RXC0 7 +- +-#define UCSR0B _SFR_MEM8(0xC1) +-#define TXB80 0 +-#define RXB80 1 +-#define UCSZ02 2 +-#define TXEN0 3 +-#define RXEN0 4 +-#define UDRIE0 5 +-#define TXCIE0 6 +-#define RXCIE0 7 +- +-#define UCSR0C _SFR_MEM8(0xC2) +-#define UCPOL0 0 +-#define UCSZ00 1 +-#define UCSZ01 2 +-#define USBS0 3 +-#define UPM00 4 +-#define UPM01 5 +-#define UMSEL00 6 +-#define UMSEL01 7 +- +-#define UBRR0 _SFR_MEM16(0xC4) +- +-#define UBRR0L _SFR_MEM8(0xC4) +-#define _UBRR0 0 +-#define _UBRR1 1 +-#define UBRR2 2 +-#define UBRR3 3 +-#define UBRR4 4 +-#define UBRR5 5 +-#define UBRR6 6 +-#define UBRR7 7 +- +-#define UBRR0H _SFR_MEM8(0xC5) +-#define UBRR8 0 +-#define UBRR9 1 +-#define UBRR10 2 +-#define UBRR11 3 +- +-#define UDR0 _SFR_MEM8(0xC6) +-#define UDR0_0 0 +-#define UDR0_1 1 +-#define UDR0_2 2 +-#define UDR0_3 3 +-#define UDR0_4 4 +-#define UDR0_5 5 +-#define UDR0_6 6 +-#define UDR0_7 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ +-#define PCINT0_vect_num 3 +-#define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ +-#define PCINT1_vect_num 4 +-#define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */ +-#define PCINT2_vect_num 5 +-#define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */ +-#define WDT_vect_num 6 +-#define WDT_vect _VECTOR(6) /* Watchdog Time-out Interrupt */ +-#define TIMER2_COMPA_vect_num 7 +-#define TIMER2_COMPA_vect _VECTOR(7) /* Timer/Counter2 Compare Match A */ +-#define TIMER2_COMPB_vect_num 8 +-#define TIMER2_COMPB_vect _VECTOR(8) /* Timer/Counter2 Compare Match A */ +-#define TIMER2_OVF_vect_num 9 +-#define TIMER2_OVF_vect _VECTOR(9) /* Timer/Counter2 Overflow */ +-#define TIMER1_CAPT_vect_num 10 +-#define TIMER1_CAPT_vect _VECTOR(10) /* Timer/Counter1 Capture Event */ +-#define TIMER1_COMPA_vect_num 11 +-#define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPB_vect_num 12 +-#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */ +-#define TIMER1_OVF_vect_num 13 +-#define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */ +-#define TIMER0_COMPA_vect_num 14 +-#define TIMER0_COMPA_vect _VECTOR(14) /* TimerCounter0 Compare Match A */ +-#define TIMER0_COMPB_vect_num 15 +-#define TIMER0_COMPB_vect _VECTOR(15) /* TimerCounter0 Compare Match B */ +-#define TIMER0_OVF_vect_num 16 +-#define TIMER0_OVF_vect _VECTOR(16) /* Timer/Couner0 Overflow */ +-#define SPI_STC_vect_num 17 +-#define SPI_STC_vect _VECTOR(17) /* SPI Serial Transfer Complete */ +-#define USART_RX_vect_num 18 +-#define USART_RX_vect _VECTOR(18) /* USART Rx Complete */ +-#define USART_UDRE_vect_num 19 +-#define USART_UDRE_vect _VECTOR(19) /* USART, Data Register Empty */ +-#define USART_TX_vect_num 20 +-#define USART_TX_vect _VECTOR(20) /* USART Tx Complete */ +-#define ADC_vect_num 21 +-#define ADC_vect _VECTOR(21) /* ADC Conversion Complete */ +-#define EE_READY_vect_num 22 +-#define EE_READY_vect _VECTOR(22) /* EEPROM Ready */ +-#define ANALOG_COMP_vect_num 23 +-#define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */ +-#define TWI_vect_num 24 +-#define TWI_vect _VECTOR(24) /* Two-wire Serial Interface */ +-#define SPM_Ready_vect_num 25 +-#define SPM_Ready_vect _VECTOR(25) /* Store Program Memory Read */ +- +-#define _VECTOR_SIZE 2 /* Size of individual vector. */ +-#define _VECTORS_SIZE (26 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (64) +-#define RAMSTART (0x100) +-#define RAMSIZE (1024) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x1FF) +-#define E2PAGESIZE (4) +-#define FLASHEND (0x1FFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) +- +-/* High Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(0) /* External reset disable */ -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) /* Brown-out Detector trigger level */ - #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ - #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ -#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ -#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ -+#define FUSE_EESAVE (unsigned char)~_BV(6) /* EEPROM memory is preserved through chip erase */ -+#define FUSE_DWEN (unsigned char)~_BV(7) /* debugWIRE Enable */ - #define HFUSE_DEFAULT (FUSE_SPIEN) - - /* Extended Fuse Byte */ -diff --git a/include/avr/iotn24a.h b/include/avr/iotn24a.h -index f260215..7bb871d 100644 ---- a/include/avr/iotn24a.h -+++ b/include/avr/iotn24a.h -@@ -486,10 +486,12 @@ - #define MCUCR _SFR_IO8(0x35) - #define ISC00 0 - #define ISC01 1 -+#define BODSE 2 - #define SM0 3 - #define SM1 4 - #define SE 5 - #define PUD 6 -+#define BODS 7 - - #define OCR0A _SFR_IO8(0x36) - #define OCR0A_0 0 -@@ -547,8 +549,8 @@ - #define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ - #define PCINT1_vect_num 3 - #define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */ --#define WATCHDOG_vect_num 4 --#define WATCHDOG_vect _VECTOR(4) /* Watchdog Time-out */ -+#define WDT_vect_num 4 -+#define WDT_vect _VECTOR(4) /* Watchdog Time-out */ - #define TIM1_CAPT_vect_num 5 - #define TIM1_CAPT_vect _VECTOR(5) /* Timer/Counter1 Capture Event */ - #define TIM1_COMPA_vect_num 6 -diff --git a/include/avr/iotn40.h b/include/avr/iotn40.h -index 01c8531..315f422 100644 ---- a/include/avr/iotn40.h -+++ b/include/avr/iotn40.h -@@ -545,32 +545,34 @@ - #define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ - #define PCINT1_vect_num 3 - #define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */ +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select reset vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select boot size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select boot size */ +-#define EFUSE_DEFAULT (FUSE_BOOTSZ1 & FUSE_BOOTSZ0) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x93 +-#define SIGNATURE_2 0x0F +- +- +-/* Device Pin Definitions */ +-#define PCINT19_DDR DDRD +-#define PCINT19_PORT PORTD +-#define PCINT19_PIN PIND +-#define PCINT19_BIT 3 +- +-#define OC2B_DDR DDRD +-#define OC2B_PORT PORTD +-#define OC2B_PIN PIND +-#define OC2B_BIT 3 +- +-#define INT1_DDR DDRD +-#define INT1_PORT PORTD +-#define INT1_PIN PIND +-#define INT1_BIT 3 +- +-#define XCK_DDR DDRD +-#define XCK_PORT PORTD +-#define XCK_PIN PIND +-#define XCK_BIT 4 +- +-#define T0_DDR DDRD +-#define T0_PORT PORTD +-#define T0_PIN PIND +-#define T0_BIT 4 +- +-#define PCINT20_DDR DDRD +-#define PCINT20_PORT PORTD +-#define PCINT20_PIN PIND +-#define PCINT20_BIT 4 +- +-#define PCINT6_DDR DDRB +-#define PCINT6_PORT PORTB +-#define PCINT6_PIN PINB +-#define PCINT6_BIT 6 +- +-#define PCINT7_DDR DDRB +-#define PCINT7_PORT PORTB +-#define PCINT7_PIN PINB +-#define PCINT7_BIT 7 +- +-#define T1_DDR DDRD +-#define T1_PORT PORTD +-#define T1_PIN PIND +-#define T1_BIT 5 +- +-#define OC0B_DDR DDRD +-#define OC0B_PORT PORTD +-#define OC0B_PIN PIND +-#define OC0B_BIT 5 +- +-#define PCINT21_DDR DDRD +-#define PCINT21_PORT PORTD +-#define PCINT21_PIN PIND +-#define PCINT21_BIT 5 +- +-#define AIN0_DDR DDRD +-#define AIN0_PORT PORTD +-#define AIN0_PIN PIND +-#define AIN0_BIT 6 +- +-#define OC0A_DDR DDRD +-#define OC0A_PORT PORTD +-#define OC0A_PIN PIND +-#define OC0A_BIT 6 +- +-#define PCINT22_DDR DDRD +-#define PCINT22_PORT PORTD +-#define PCINT22_PIN PIND +-#define PCINT22_BIT 6 +- +-#define AIN1_DDR DDRD +-#define AIN1_PORT PORTD +-#define AIN1_PIN PIND +-#define AIN1_BIT 7 +- +-#define PCINT23_DDR DDRD +-#define PCINT23_PORT PORTD +-#define PCINT23_PIN PIND +-#define PCINT23_BIT 7 +- +-#define ICP1_DDR DDRB +-#define ICP1_PORT PORTB +-#define ICP1_PIN PINB +-#define ICP1_BIT 0 +- +-#define CLKO_DDR DDRB +-#define CLKO_PORT PORTB +-#define CLKO_PIN PINB +-#define CLKO_BIT 0 +- +-#define PCINT0_DDR DDRB +-#define PCINT0_PORT PORTB +-#define PCINT0_PIN PINB +-#define PCINT0_BIT 0 +- +-#define OC1A_DDR DDRB +-#define OC1A_PORT PORTB +-#define OC1A_PIN PINB +-#define OC1A_BIT 1 +- +-#define PCINT1_DDR DDRB +-#define PCINT1_PORT PORTB +-#define PCINT1_PIN PINB +-#define PCINT1_BIT 1 +- +-#define SS_DDR DDRB +-#define SS_PORT PORTB +-#define SS_PIN PINB +-#define SS_BIT 2 +- +-#define OC1B_DDR DDRB +-#define OC1B_PORT PORTB +-#define OC1B_PIN PINB +-#define OC1B_BIT 2 +- +-#define PCINT2_DDR DDRB +-#define PCINT2_PORT PORTB +-#define PCINT2_PIN PINB +-#define PCINT2_BIT 2 +- +-#define MOSI_DDR DDRB +-#define MOSI_PORT PORTB +-#define MOSI_PIN PINB +-#define MOSI_BIT 3 +- +-#define OC2A_DDR DDRB +-#define OC2A_PORT PORTB +-#define OC2A_PIN PINB +-#define OC2A_BIT 3 +- +-#define PCINT3_DDR DDRB +-#define PCINT3_PORT PORTB +-#define PCINT3_PIN PINB +-#define PCINT3_BIT 3 +- +-#define MISO_DDR DDRB +-#define MISO_PORT PORTB +-#define MISO_PIN PINB +-#define MISO_BIT 4 +- +-#define PCINT4_DDR DDRB +-#define PCINT4_PORT PORTB +-#define PCINT4_PIN PINB +-#define PCINT4_BIT 4 +- +-#define SCK_DDR DDRB +-#define SCK_PORT PORTB +-#define SCK_PIN PINB +-#define SCK_BIT 5 +- +-#define PCINT5_DDR DDRB +-#define PCINT5_PORT PORTB +-#define PCINT5_PIN PINB +-#define PCINT5_BIT 5 +- +-#define ADC6_DDR DDRADC +-#define ADC6_PORT PORTADC +-#define ADC6_PIN PINADC +-#define ADC6_BIT ADC6 +- +-#define ADC7_DDR DDRADC +-#define ADC7_PORT PORTADC +-#define ADC7_PIN PINADC +-#define ADC7_BIT ADC7 +- +-#define ADC0_DDR DDRC +-#define ADC0_PORT PORTC +-#define ADC0_PIN PINC +-#define ADC0_BIT 0 +- +-#define PCINT8_DDR DDRC +-#define PCINT8_PORT PORTC +-#define PCINT8_PIN PINC +-#define PCINT8_BIT 0 +- +-#define ADC1_DDR DDRC +-#define ADC1_PORT PORTC +-#define ADC1_PIN PINC +-#define ADC1_BIT 1 +- +-#define PCINT9_DDR DDRC +-#define PCINT9_PORT PORTC +-#define PCINT9_PIN PINC +-#define PCINT9_BIT 1 +- +-#define ADC2_DDR DDRC +-#define ADC2_PORT PORTC +-#define ADC2_PIN PINC +-#define ADC2_BIT 2 +- +-#define PCINT10_DDR DDRC +-#define PCINT10_PORT PORTC +-#define PCINT10_PIN PINC +-#define PCINT10_BIT 2 +- +-#define ADC3_DDR DDRC +-#define ADC3_PORT PORTC +-#define ADC3_PIN PINC +-#define ADC3_BIT 3 +- +-#define PCINT11_DDR DDRC +-#define PCINT11_PORT PORTC +-#define PCINT11_PIN PINC +-#define PCINT11_BIT 3 +- +-#define ADC4_DDR DDRC +-#define ADC4_PORT PORTC +-#define ADC4_PIN PINC +-#define ADC4_BIT 4 +- +-#define SDA_DDR DDRC +-#define SDA_PORT PORTC +-#define SDA_PIN PINC +-#define SDA_BIT 4 +- +-#define PCINT12_DDR DDRC +-#define PCINT12_PORT PORTC +-#define PCINT12_PIN PINC +-#define PCINT12_BIT 4 +- +-#define ADC5_DDR DDRC +-#define ADC5_PORT PORTC +-#define ADC5_PIN PINC +-#define ADC5_BIT 5 +- +-#define SCL_DDR DDRC +-#define SCL_PORT PORTC +-#define SCL_PIN PINC +-#define SCL_BIT 5 +- +-#define PCINT13_DDR DDRC +-#define PCINT13_PORT PORTC +-#define PCINT13_PIN PINC +-#define PCINT13_BIT 5 +- +-#define PCINT14_DDR DDRC +-#define PCINT14_PORT PORTC +-#define PCINT14_PIN PINC +-#define PCINT14_BIT 6 +- +-#define RXD_DDR DDRD +-#define RXD_PORT PORTD +-#define RXD_PIN PIND +-#define RXD_BIT 0 +- +-#define PCINT16_DDR DDRD +-#define PCINT16_PORT PORTD +-#define PCINT16_PIN PIND +-#define PCINT16_BIT 0 +- +-#define TXD_DDR DDRD +-#define TXD_PORT PORTD +-#define TXD_PIN PIND +-#define TXD_BIT 1 +- +-#define PCINT17_DDR DDRD +-#define PCINT17_PORT PORTD +-#define PCINT17_PIN PIND +-#define PCINT17_BIT 1 +- +-#define INT0_DDR DDRD +-#define INT0_PORT PORTD +-#define INT0_PIN PIND +-#define INT0_BIT 2 +- +-#define PCINT18_DDR DDRD +-#define PCINT18_PORT PORTD +-#define PCINT18_PIN PIND +-#define PCINT18_BIT 2 +- +-#endif /* _AVR_ATmega88PA_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom88pa.h 2035 2009-11-02 02:44:17Z arcanum $ */ ++ ++/* avr/iom88pa.h - definitions for ATmega88PA */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom88pa.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATmega88PA_H_ ++#define _AVR_ATmega88PA_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC3 3 ++#define PORTC4 4 ++#define PORTC5 5 ++#define PORTC6 6 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define PSRASY 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define OCR0A _SFR_IO8(0x27) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define OCR0B _SFR_IO8(0x28) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SELFPRGEN 0 ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_MEM8(0x79) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++#define TCNT2_0 0 ++#define TCNT2_1 1 ++#define TCNT2_2 2 ++#define TCNT2_3 3 ++#define TCNT2_4 4 ++#define TCNT2_5 5 ++#define TCNT2_6 6 ++#define TCNT2_7 7 ++ ++#define OCR2A _SFR_MEM8(0xB3) ++#define OCR2A_0 0 ++#define OCR2A_1 1 ++#define OCR2A_2 2 ++#define OCR2A_3 3 ++#define OCR2A_4 4 ++#define OCR2A_5 5 ++#define OCR2A_6 6 ++#define OCR2A_7 7 ++ ++#define OCR2B _SFR_MEM8(0xB4) ++#define OCR2B_0 0 ++#define OCR2B_1 1 ++#define OCR2B_2 2 ++#define OCR2B_3 3 ++#define OCR2B_4 4 ++#define OCR2B_5 5 ++#define OCR2B_6 6 ++#define OCR2B_7 7 ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++ ++#define TWBR _SFR_MEM8(0xB8) ++#define TWBR0 0 ++#define TWBR1 1 ++#define TWBR2 2 ++#define TWBR3 3 ++#define TWBR4 4 ++#define TWBR5 5 ++#define TWBR6 6 ++#define TWBR7 7 ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++#define TWD0 0 ++#define TWD1 1 ++#define TWD2 2 ++#define TWD3 3 ++#define TWD4 4 ++#define TWD5 5 ++#define TWD6 6 ++#define TWD7 7 ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define _UBRR0 0 ++#define _UBRR1 1 ++#define UBRR2 2 ++#define UBRR3 3 ++#define UBRR4 4 ++#define UBRR5 5 ++#define UBRR6 6 ++#define UBRR7 7 ++ ++#define UBRR0H _SFR_MEM8(0xC5) ++#define UBRR8 0 ++#define UBRR9 1 ++#define UBRR10 2 ++#define UBRR11 3 ++ ++#define UDR0 _SFR_MEM8(0xC6) ++#define UDR0_0 0 ++#define UDR0_1 1 ++#define UDR0_2 2 ++#define UDR0_3 3 ++#define UDR0_4 4 ++#define UDR0_5 5 ++#define UDR0_6 6 ++#define UDR0_7 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ ++#define PCINT0_vect_num 3 ++#define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect_num 4 ++#define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 0 */ ++#define PCINT2_vect_num 5 ++#define PCINT2_vect _VECTOR(5) /* Pin Change Interrupt Request 1 */ ++#define WDT_vect_num 6 ++#define WDT_vect _VECTOR(6) /* Watchdog Time-out Interrupt */ ++#define TIMER2_COMPA_vect_num 7 ++#define TIMER2_COMPA_vect _VECTOR(7) /* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPB_vect_num 8 ++#define TIMER2_COMPB_vect _VECTOR(8) /* Timer/Counter2 Compare Match A */ ++#define TIMER2_OVF_vect_num 9 ++#define TIMER2_OVF_vect _VECTOR(9) /* Timer/Counter2 Overflow */ ++#define TIMER1_CAPT_vect_num 10 ++#define TIMER1_CAPT_vect _VECTOR(10) /* Timer/Counter1 Capture Event */ ++#define TIMER1_COMPA_vect_num 11 ++#define TIMER1_COMPA_vect _VECTOR(11) /* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPB_vect_num 12 ++#define TIMER1_COMPB_vect _VECTOR(12) /* Timer/Counter1 Compare Match B */ ++#define TIMER1_OVF_vect_num 13 ++#define TIMER1_OVF_vect _VECTOR(13) /* Timer/Counter1 Overflow */ ++#define TIMER0_COMPA_vect_num 14 ++#define TIMER0_COMPA_vect _VECTOR(14) /* TimerCounter0 Compare Match A */ ++#define TIMER0_COMPB_vect_num 15 ++#define TIMER0_COMPB_vect _VECTOR(15) /* TimerCounter0 Compare Match B */ ++#define TIMER0_OVF_vect_num 16 ++#define TIMER0_OVF_vect _VECTOR(16) /* Timer/Couner0 Overflow */ ++#define SPI_STC_vect_num 17 ++#define SPI_STC_vect _VECTOR(17) /* SPI Serial Transfer Complete */ ++#define USART_RX_vect_num 18 ++#define USART_RX_vect _VECTOR(18) /* USART Rx Complete */ ++#define USART_UDRE_vect_num 19 ++#define USART_UDRE_vect _VECTOR(19) /* USART, Data Register Empty */ ++#define USART_TX_vect_num 20 ++#define USART_TX_vect _VECTOR(20) /* USART Tx Complete */ ++#define ADC_vect_num 21 ++#define ADC_vect _VECTOR(21) /* ADC Conversion Complete */ ++#define EE_READY_vect_num 22 ++#define EE_READY_vect _VECTOR(22) /* EEPROM Ready */ ++#define ANALOG_COMP_vect_num 23 ++#define ANALOG_COMP_vect _VECTOR(23) /* Analog Comparator */ ++#define TWI_vect_num 24 ++#define TWI_vect _VECTOR(24) /* Two-wire Serial Interface */ ++#define SPM_Ready_vect_num 25 ++#define SPM_Ready_vect _VECTOR(25) /* Store Program Memory Read */ ++ ++#define _VECTOR_SIZE 2 /* Size of individual vector. */ ++#define _VECTORS_SIZE (26 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (64) ++#define RAMSTART (0x100) ++#define RAMSIZE (1024) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x1FF) ++#define E2PAGESIZE (4) ++#define FLASHEND (0x1FFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select reset vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select boot size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select boot size */ ++#define EFUSE_DEFAULT (FUSE_BOOTSZ1 & FUSE_BOOTSZ0) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x0F ++ ++ ++/* Device Pin Definitions */ ++#define PCINT19_DDR DDRD ++#define PCINT19_PORT PORTD ++#define PCINT19_PIN PIND ++#define PCINT19_BIT 3 ++ ++#define OC2B_DDR DDRD ++#define OC2B_PORT PORTD ++#define OC2B_PIN PIND ++#define OC2B_BIT 3 ++ ++#define INT1_DDR DDRD ++#define INT1_PORT PORTD ++#define INT1_PIN PIND ++#define INT1_BIT 3 ++ ++#define XCK_DDR DDRD ++#define XCK_PORT PORTD ++#define XCK_PIN PIND ++#define XCK_BIT 4 ++ ++#define T0_DDR DDRD ++#define T0_PORT PORTD ++#define T0_PIN PIND ++#define T0_BIT 4 ++ ++#define PCINT20_DDR DDRD ++#define PCINT20_PORT PORTD ++#define PCINT20_PIN PIND ++#define PCINT20_BIT 4 ++ ++#define PCINT6_DDR DDRB ++#define PCINT6_PORT PORTB ++#define PCINT6_PIN PINB ++#define PCINT6_BIT 6 ++ ++#define PCINT7_DDR DDRB ++#define PCINT7_PORT PORTB ++#define PCINT7_PIN PINB ++#define PCINT7_BIT 7 ++ ++#define T1_DDR DDRD ++#define T1_PORT PORTD ++#define T1_PIN PIND ++#define T1_BIT 5 ++ ++#define OC0B_DDR DDRD ++#define OC0B_PORT PORTD ++#define OC0B_PIN PIND ++#define OC0B_BIT 5 ++ ++#define PCINT21_DDR DDRD ++#define PCINT21_PORT PORTD ++#define PCINT21_PIN PIND ++#define PCINT21_BIT 5 ++ ++#define AIN0_DDR DDRD ++#define AIN0_PORT PORTD ++#define AIN0_PIN PIND ++#define AIN0_BIT 6 ++ ++#define OC0A_DDR DDRD ++#define OC0A_PORT PORTD ++#define OC0A_PIN PIND ++#define OC0A_BIT 6 ++ ++#define PCINT22_DDR DDRD ++#define PCINT22_PORT PORTD ++#define PCINT22_PIN PIND ++#define PCINT22_BIT 6 ++ ++#define AIN1_DDR DDRD ++#define AIN1_PORT PORTD ++#define AIN1_PIN PIND ++#define AIN1_BIT 7 ++ ++#define PCINT23_DDR DDRD ++#define PCINT23_PORT PORTD ++#define PCINT23_PIN PIND ++#define PCINT23_BIT 7 ++ ++#define ICP1_DDR DDRB ++#define ICP1_PORT PORTB ++#define ICP1_PIN PINB ++#define ICP1_BIT 0 ++ ++#define CLKO_DDR DDRB ++#define CLKO_PORT PORTB ++#define CLKO_PIN PINB ++#define CLKO_BIT 0 ++ ++#define PCINT0_DDR DDRB ++#define PCINT0_PORT PORTB ++#define PCINT0_PIN PINB ++#define PCINT0_BIT 0 ++ ++#define OC1A_DDR DDRB ++#define OC1A_PORT PORTB ++#define OC1A_PIN PINB ++#define OC1A_BIT 1 ++ ++#define PCINT1_DDR DDRB ++#define PCINT1_PORT PORTB ++#define PCINT1_PIN PINB ++#define PCINT1_BIT 1 ++ ++#define SS_DDR DDRB ++#define SS_PORT PORTB ++#define SS_PIN PINB ++#define SS_BIT 2 ++ ++#define OC1B_DDR DDRB ++#define OC1B_PORT PORTB ++#define OC1B_PIN PINB ++#define OC1B_BIT 2 ++ ++#define PCINT2_DDR DDRB ++#define PCINT2_PORT PORTB ++#define PCINT2_PIN PINB ++#define PCINT2_BIT 2 ++ ++#define MOSI_DDR DDRB ++#define MOSI_PORT PORTB ++#define MOSI_PIN PINB ++#define MOSI_BIT 3 ++ ++#define OC2A_DDR DDRB ++#define OC2A_PORT PORTB ++#define OC2A_PIN PINB ++#define OC2A_BIT 3 ++ ++#define PCINT3_DDR DDRB ++#define PCINT3_PORT PORTB ++#define PCINT3_PIN PINB ++#define PCINT3_BIT 3 ++ ++#define MISO_DDR DDRB ++#define MISO_PORT PORTB ++#define MISO_PIN PINB ++#define MISO_BIT 4 ++ ++#define PCINT4_DDR DDRB ++#define PCINT4_PORT PORTB ++#define PCINT4_PIN PINB ++#define PCINT4_BIT 4 ++ ++#define SCK_DDR DDRB ++#define SCK_PORT PORTB ++#define SCK_PIN PINB ++#define SCK_BIT 5 ++ ++#define PCINT5_DDR DDRB ++#define PCINT5_PORT PORTB ++#define PCINT5_PIN PINB ++#define PCINT5_BIT 5 ++ ++#define ADC6_DDR DDRADC ++#define ADC6_PORT PORTADC ++#define ADC6_PIN PINADC ++#define ADC6_BIT ADC6 ++ ++#define ADC7_DDR DDRADC ++#define ADC7_PORT PORTADC ++#define ADC7_PIN PINADC ++#define ADC7_BIT ADC7 ++ ++#define ADC0_DDR DDRC ++#define ADC0_PORT PORTC ++#define ADC0_PIN PINC ++#define ADC0_BIT 0 ++ ++#define PCINT8_DDR DDRC ++#define PCINT8_PORT PORTC ++#define PCINT8_PIN PINC ++#define PCINT8_BIT 0 ++ ++#define ADC1_DDR DDRC ++#define ADC1_PORT PORTC ++#define ADC1_PIN PINC ++#define ADC1_BIT 1 ++ ++#define PCINT9_DDR DDRC ++#define PCINT9_PORT PORTC ++#define PCINT9_PIN PINC ++#define PCINT9_BIT 1 ++ ++#define ADC2_DDR DDRC ++#define ADC2_PORT PORTC ++#define ADC2_PIN PINC ++#define ADC2_BIT 2 ++ ++#define PCINT10_DDR DDRC ++#define PCINT10_PORT PORTC ++#define PCINT10_PIN PINC ++#define PCINT10_BIT 2 ++ ++#define ADC3_DDR DDRC ++#define ADC3_PORT PORTC ++#define ADC3_PIN PINC ++#define ADC3_BIT 3 ++ ++#define PCINT11_DDR DDRC ++#define PCINT11_PORT PORTC ++#define PCINT11_PIN PINC ++#define PCINT11_BIT 3 ++ ++#define ADC4_DDR DDRC ++#define ADC4_PORT PORTC ++#define ADC4_PIN PINC ++#define ADC4_BIT 4 ++ ++#define SDA_DDR DDRC ++#define SDA_PORT PORTC ++#define SDA_PIN PINC ++#define SDA_BIT 4 ++ ++#define PCINT12_DDR DDRC ++#define PCINT12_PORT PORTC ++#define PCINT12_PIN PINC ++#define PCINT12_BIT 4 ++ ++#define ADC5_DDR DDRC ++#define ADC5_PORT PORTC ++#define ADC5_PIN PINC ++#define ADC5_BIT 5 ++ ++#define SCL_DDR DDRC ++#define SCL_PORT PORTC ++#define SCL_PIN PINC ++#define SCL_BIT 5 ++ ++#define PCINT13_DDR DDRC ++#define PCINT13_PORT PORTC ++#define PCINT13_PIN PINC ++#define PCINT13_BIT 5 ++ ++#define PCINT14_DDR DDRC ++#define PCINT14_PORT PORTC ++#define PCINT14_PIN PINC ++#define PCINT14_BIT 6 ++ ++#define RXD_DDR DDRD ++#define RXD_PORT PORTD ++#define RXD_PIN PIND ++#define RXD_BIT 0 ++ ++#define PCINT16_DDR DDRD ++#define PCINT16_PORT PORTD ++#define PCINT16_PIN PIND ++#define PCINT16_BIT 0 ++ ++#define TXD_DDR DDRD ++#define TXD_PORT PORTD ++#define TXD_PIN PIND ++#define TXD_BIT 1 ++ ++#define PCINT17_DDR DDRD ++#define PCINT17_PORT PORTD ++#define PCINT17_PIN PIND ++#define PCINT17_BIT 1 ++ ++#define INT0_DDR DDRD ++#define INT0_PORT PORTD ++#define INT0_PIN PIND ++#define INT0_BIT 2 ++ ++#define PCINT18_DDR DDRD ++#define PCINT18_PORT PORTD ++#define PCINT18_PIN PIND ++#define PCINT18_BIT 2 ++ ++#endif /* _AVR_ATmega88PA_H_ */ ++ +diff --git a/include/avr/iom88pb.h b/include/avr/iom88pb.h +new file mode 100644 +index 0000000..7107bd4 +--- /dev/null ++++ b/include/avr/iom88pb.h +@@ -0,0 +1,815 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATMEGA88PB_H_INCLUDED ++#define _AVR_ATMEGA88PB_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom88pb.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDRE3 3 ++#define DDRE2 2 ++#define DDRE1 1 ++#define DDRE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PORTE3 3 ++#define PORTE2 2 ++#define PORTE1 1 ++#define PORTE0 0 ++ ++#define ACSRB _SFR_IO8(0x0F) ++#define ACOE 0 ++ ++/* Reserved [0x10..0x14] */ ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++ ++/* Reserved [0x18..0x1A] */ ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define TSM 7 ++#define PSRASY 1 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++ ++#define OCR0A _SFR_IO8(0x27) ++ ++#define OCR0B _SFR_IO8(0x28) ++ ++/* Reserved [0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++/* Reserved [0x31..0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SELFPRGEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDE 3 ++#define WDCE 4 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRTIM0 5 ++#define PRTIM2 6 ++#define PRTWI 7 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++/* Reserved [0x67] */ ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++ ++/* Reserved [0x71..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++#define OCR2B _SFR_MEM8(0xB4) ++ ++/* Reserved [0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR2BUB 0 ++#define TCR2AUB 1 ++#define OCR2BUB 2 ++#define OCR2AUB 3 ++#define TCN2UB 4 ++#define AS2 5 ++#define EXCLK 6 ++ ++/* Reserved [0xB7] */ ++ ++#define TWBR _SFR_MEM8(0xB8) ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++/* Reserved [0xBE..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define UCSR0B _SFR_MEM8(0xC1) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++ ++#define UCSR0D _SFR_MEM8(0xC3) ++#define SFDE 5 ++#define RXS 6 ++#define RXSIE 7 ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0xC6) ++ ++/* Reserved [0xC7..0xEF] */ ++ ++#define DEVID0 _SFR_MEM8(0xF0) ++ ++#define DEVID1 _SFR_MEM8(0xF1) ++ ++#define DEVID2 _SFR_MEM8(0xF2) ++ ++#define DEVID3 _SFR_MEM8(0xF3) ++ ++#define DEVID4 _SFR_MEM8(0xF4) ++ ++#define DEVID5 _SFR_MEM8(0xF5) ++ ++#define DEVID6 _SFR_MEM8(0xF6) ++ ++#define DEVID7 _SFR_MEM8(0xF7) ++ ++#define DEVID8 _SFR_MEM8(0xF8) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(3) ++#define PCINT0_vect_num 3 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect _VECTOR(4) ++#define PCINT1_vect_num 4 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT2_vect _VECTOR(5) ++#define PCINT2_vect_num 5 ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect _VECTOR(6) ++#define WDT_vect_num 6 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPA_vect _VECTOR(7) ++#define TIMER2_COMPA_vect_num 7 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPB_vect _VECTOR(8) ++#define TIMER2_COMPB_vect_num 8 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(9) ++#define TIMER2_OVF_vect_num 9 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(10) ++#define TIMER1_CAPT_vect_num 10 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(11) ++#define TIMER1_COMPA_vect_num 11 ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(12) ++#define TIMER1_COMPB_vect_num 12 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(13) ++#define TIMER1_OVF_vect_num 13 ++ ++/* TimerCounter0 Compare Match A */ ++#define TIMER0_COMPA_vect _VECTOR(14) ++#define TIMER0_COMPA_vect_num 14 ++ ++/* TimerCounter0 Compare Match B */ ++#define TIMER0_COMPB_vect _VECTOR(15) ++#define TIMER0_COMPB_vect_num 15 ++ ++/* Timer/Couner0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(16) ++#define TIMER0_OVF_vect_num 16 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(17) ++#define SPI_STC_vect_num 17 ++ ++/* USART Rx Complete */ ++#define USART_RX_vect _VECTOR(18) ++#define USART_RX_vect_num 18 ++ ++/* USART, Data Register Empty */ ++#define USART_UDRE_vect _VECTOR(19) ++#define USART_UDRE_vect_num 19 ++ ++/* USART Tx Complete */ ++#define USART_TX_vect _VECTOR(20) ++#define USART_TX_vect_num 20 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(21) ++#define ADC_vect_num 21 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(22) ++#define EE_READY_vect_num 22 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(23) ++#define ANALOG_COMP_vect_num 23 ++ ++/* Two-wire Serial Interface */ ++#define TWI_vect _VECTOR(24) ++#define TWI_vect_num 24 ++ ++/* Store Program Memory Read */ ++#define SPM_Ready_vect _VECTOR(25) ++#define SPM_Ready_vect_num 25 ++ ++#define _VECTORS_SIZE 52 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 64 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x1FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 1024 ++#define RAMEND 0x04FF ++#define E2START 0 ++#define E2SIZE 512 ++#define E2PAGESIZE 4 ++#define E2END 0x01FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x16 ++ ++ ++#endif /* #ifdef _AVR_ATMEGA88PB_H_INCLUDED */ ++ +diff --git a/include/avr/iom8a.h b/include/avr/iom8a.h +new file mode 100644 +index 0000000..48e1dbc +--- /dev/null ++++ b/include/avr/iom8a.h +@@ -0,0 +1,562 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATMEGA8A_H_INCLUDED ++#define _AVR_ATMEGA8A_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom8a.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define TWBR _SFR_IO8(0x00) ++ ++#define TWSR _SFR_IO8(0x01) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_IO8(0x02) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_IO8(0x03) ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCW _SFR_IO16(0x04) ++ ++#define ADCL _SFR_IO8(0x04) ++#define ADCH _SFR_IO8(0x05) ++ ++#define ADCSRA _SFR_IO8(0x06) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADFR 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADMUX _SFR_IO8(0x07) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define ACSR _SFR_IO8(0x08) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define UBRRL _SFR_IO8(0x09) ++ ++#define UCSRB _SFR_IO8(0x0A) ++#define TXB8 0 ++#define RXB8 1 ++#define UCSZ2 2 ++#define TXEN 3 ++#define RXEN 4 ++#define UDRIE 5 ++#define TXCIE 6 ++#define RXCIE 7 ++ ++#define UCSRA _SFR_IO8(0x0B) ++#define MPCM 0 ++#define U2X 1 ++#define UPE 2 ++#define DOR 3 ++#define FE 4 ++#define UDRE 5 ++#define TXC 6 ++#define RXC 7 ++ ++#define UDR _SFR_IO8(0x0C) ++ ++#define SPCR _SFR_IO8(0x0D) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x0E) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x0F) ++ ++#define PIND _SFR_IO8(0x10) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x11) ++#define DDRD7 7 ++#define DDRD6 6 ++#define DDRD5 5 ++#define DDRD4 4 ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x12) ++#define PORTD7 7 ++#define PORTD6 6 ++#define PORTD5 5 ++#define PORTD4 4 ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++#define PINC _SFR_IO8(0x13) ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x14) ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x15) ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PINB _SFR_IO8(0x16) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x17) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x18) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++/* Reserved [0x19..0x1B] */ ++ ++#define EECR _SFR_IO8(0x1C) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x1E) ++ ++#define EEARL _SFR_IO8(0x1E) ++#define EEARH _SFR_IO8(0x1F) ++ ++#define UCSRC _SFR_IO8(0x20) ++#define UCPOL 0 ++#define UCSZ0 1 ++#define UCSZ1 2 ++#define USBS 3 ++#define UPM0 4 ++#define UPM1 5 ++#define UMSEL 6 ++#define URSEL 7 ++ ++#define UBRRH _SFR_IO8(0x20) ++ ++#define WDTCR _SFR_IO8(0x21) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++#define ASSR _SFR_IO8(0x22) ++#define TCR2UB 0 ++#define OCR2UB 1 ++#define TCN2UB 2 ++#define AS2 3 ++ ++#define OCR2 _SFR_IO8(0x23) ++ ++#define TCNT2 _SFR_IO8(0x24) ++ ++#define TCCR2 _SFR_IO8(0x25) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM21 3 ++#define COM20 4 ++#define COM21 5 ++#define WGM20 6 ++#define FOC2 7 ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_IO16(0x26) ++ ++#define ICR1L _SFR_IO8(0x26) ++#define ICR1H _SFR_IO8(0x27) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_IO16(0x28) ++ ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BH _SFR_IO8(0x29) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_IO16(0x2A) ++ ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_IO16(0x2C) ++ ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++ ++#define TCCR1B _SFR_IO8(0x2E) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1A _SFR_IO8(0x2F) ++#define WGM10 0 ++#define WGM11 1 ++#define FOC1B 2 ++#define FOC1A 3 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define SFIOR _SFR_IO8(0x30) ++#define ACME 3 ++#define PSR2 1 ++#define PSR10 0 ++#define PUD 2 ++#define ADHSM 4 ++ ++#define OSCCAL _SFR_IO8(0x31) ++#define OSCCAL0 0 ++#define OSCCAL1 1 ++#define OSCCAL2 2 ++#define OSCCAL3 3 ++#define OSCCAL4 4 ++#define OSCCAL5 5 ++#define OSCCAL6 6 ++#define OSCCAL7 7 ++ ++#define TCNT0 _SFR_IO8(0x32) ++ ++#define TCCR0 _SFR_IO8(0x33) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++ ++#define MCUCSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define SM0 4 ++#define SM1 5 ++#define SM2 6 ++#define SE 7 ++ ++#define TWCR _SFR_IO8(0x36) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define SPMCR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define TIFR _SFR_IO8(0x38) ++#define TOV0 0 ++#define TOV1 2 ++#define OCF1B 3 ++#define OCF1A 4 ++#define ICF1 5 ++#define TOV2 6 ++#define OCF2 7 ++ ++#define TIMSK _SFR_IO8(0x39) ++#define TOIE0 0 ++#define TOIE1 2 ++#define OCIE1B 3 ++#define OCIE1A 4 ++#define TICIE1 5 ++#define TOIE2 6 ++#define OCIE2 7 ++ ++#define GIFR _SFR_IO8(0x3A) ++#define INTF0 6 ++#define INTF1 7 ++ ++#define GICR _SFR_IO8(0x3B) ++#define IVCE 0 ++#define IVSEL 1 ++#define INT0 6 ++#define INT1 7 ++ ++/* Reserved [0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* Timer/Counter2 Compare Match */ ++#define TIMER2_COMP_vect _VECTOR(3) ++#define TIMER2_COMP_vect_num 3 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(4) ++#define TIMER2_OVF_vect_num 4 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(5) ++#define TIMER1_CAPT_vect_num 5 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(6) ++#define TIMER1_COMPA_vect_num 6 ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(7) ++#define TIMER1_COMPB_vect_num 7 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(8) ++#define TIMER1_OVF_vect_num 8 ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(9) ++#define TIMER0_OVF_vect_num 9 ++ ++/* Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(10) ++#define SPI_STC_vect_num 10 ++ ++/* USART, Rx Complete */ ++#define USART_RXC_vect _VECTOR(11) ++#define USART_RXC_vect_num 11 ++ ++/* USART Data Register Empty */ ++#define USART_UDRE_vect _VECTOR(12) ++#define USART_UDRE_vect_num 12 ++ ++/* USART, Tx Complete */ ++#define USART_TXC_vect _VECTOR(13) ++#define USART_TXC_vect_num 13 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(14) ++#define ADC_vect_num 14 ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect _VECTOR(15) ++#define EE_RDY_vect_num 15 ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect _VECTOR(16) ++#define ANA_COMP_vect_num 16 ++ ++/* 2-wire Serial Interface */ ++#define TWI_vect _VECTOR(17) ++#define TWI_vect_num 17 ++ ++/* Store Program Memory Ready */ ++#define SPM_RDY_vect _VECTOR(18) ++#define SPM_RDY_vect_num 18 ++ ++#define _VECTORS_SIZE 38 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 64 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x1FFF ++#define RAMSTART 0x0060 ++#define RAMSIZE 1024 ++#define RAMEND 0x045F ++#define E2START 0 ++#define E2SIZE 512 ++#define E2PAGESIZE 4 ++#define E2END 0x01FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 2 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_SUT_CKSEL5 (unsigned char)~_BV(5) ++#define FUSE_BODEN (unsigned char)~_BV(6) ++#define FUSE_BODLEVEL (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_CKOPT (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_WTDON (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x07 ++ ++ ++#endif /* #ifdef _AVR_ATMEGA8A_H_INCLUDED */ ++ +diff --git a/include/avr/iom8hva.h b/include/avr/iom8hva.h +index 8885c56..8631de5 100644 +--- a/include/avr/iom8hva.h ++++ b/include/avr/iom8hva.h +@@ -1,70 +1,71 @@ +-/* Copyright (c) 2007, Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom8hva.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ +- +-/* iom8hva.h - definitions for ATmega8HVA. */ +- +-#ifndef _AVR_IOM8HVA_H_ +-#define _AVR_IOM8HVA_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 128 +-#define RAMEND 0x2FF +-#define XRAMEND RAMEND +-#define E2END 0xFF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x1FFF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 1 +- +-/* Low Fuse Byte */ +-#define FUSE_SUT0 (unsigned char)~_BV(0) +-#define FUSE_SUT1 (unsigned char)~_BV(1) +-#define FUSE_SUT2 (unsigned char)~_BV(2) +-#define FUSE_SELFPRGEN (unsigned char)~_BV(3) +-#define FUSE_DWEN (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_EESAVE (unsigned char)~_BV(6) +-#define FUSE_WDTON (unsigned char)~_BV(7) +-#define FUSE_DEFAULT (FUSE_SPIEN) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-#endif /* _AVR_IOM8HVA_H_ */ +- ++/* Copyright (c) 2007, Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom8hva.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ ++ ++/* iom8hva.h - definitions for ATmega8HVA. */ ++ ++#ifndef _AVR_IOM8HVA_H_ ++#define _AVR_IOM8HVA_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 128 ++#define RAMSTART 0x100 ++#define RAMEND 0x2FF ++#define XRAMEND RAMEND ++#define E2END 0xFF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x1FFF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT0 (unsigned char)~_BV(0) ++#define FUSE_SUT1 (unsigned char)~_BV(1) ++#define FUSE_SUT2 (unsigned char)~_BV(2) ++#define FUSE_SELFPRGEN (unsigned char)~_BV(3) ++#define FUSE_DWEN (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_EESAVE (unsigned char)~_BV(6) ++#define FUSE_WDTON (unsigned char)~_BV(7) ++#define FUSE_DEFAULT (FUSE_SPIEN) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++#endif /* _AVR_IOM8HVA_H_ */ ++ +diff --git a/include/avr/iom8u2.h b/include/avr/iom8u2.h +index dacd768..557bdda 100644 +--- a/include/avr/iom8u2.h ++++ b/include/avr/iom8u2.h +@@ -1,977 +1,983 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iom8u2.h 2245 2011-05-12 22:42:21Z arcanum $ */ +- +-/* avr/iom8u2.h - definitions for ATmega8U2 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom8u2.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATmega8U2_H_ +-#define _AVR_ATmega8U2_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +-#define PINC7 7 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +-#define DDC7 7 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC4 4 +-#define PORTC5 5 +-#define PORTC6 6 +-#define PORTC7 7 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define OCF1C 3 +-#define ICF1 5 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +-#define PCIF1 1 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +-#define INTF2 2 +-#define INTF3 3 +-#define INTF4 4 +-#define INTF5 5 +-#define INTF6 6 +-#define INTF7 7 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +-#define INT2 2 +-#define INT3 3 +-#define INT4 4 +-#define INT5 5 +-#define INT6 6 +-#define INT7 7 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +-#define EEAR9 1 +-#define EEAR10 2 +-#define EEAR11 3 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSRSYNC 0 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define OCR0A _SFR_IO8(0x27) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define OCR0B _SFR_IO8(0x28) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define PLLCSR _SFR_IO8(0x29) +-#define PLOCK 0 +-#define PLLE 1 +-#define PLLP0 2 +-#define PLLP1 3 +-#define PLLP2 4 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define DWDR _SFR_IO8(0x31) +-#define DWDR0 0 +-#define DWDR1 1 +-#define DWDR2 2 +-#define DWDR3 3 +-#define DWDR4 4 +-#define DWDR5 5 +-#define DWDR6 6 +-#define DWDR7 7 +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +-#define USBRF 5 +- +-#define MCUCR _SFR_IO8(0x35) +-#define IVCE 0 +-#define IVSEL 1 +-#define PUD 4 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define BLBSET 3 +-#define RWWSRE 4 +-#define SIGRD 5 +-#define RWWSB 6 +-#define SPMIE 7 +- +-#define EIND _SFR_IO8(0x3C) +-#define EIND0 0 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define WDTCKD _SFR_MEM8(0x62) +-#define WCLKD0 0 +-#define WCLKD1 1 +-#define WDEWIE 2 +-#define WDEWIF 3 +- +-#define REGCR _SFR_MEM8(0x63) +-#define REGDIS 0 +- +-#define PRR0 _SFR_MEM8(0x64) +-#define PRSPI 2 +-#define PRTIM1 3 +-#define PRTIM0 5 +- +-#define PRR1 _SFR_MEM8(0x65) +-#define PRUSART1 0 +-#define PRUSB 7 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +-#define PCIE1 1 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define ISC20 4 +-#define ISC21 5 +-#define ISC30 6 +-#define ISC31 7 +- +-#define EICRB _SFR_MEM8(0x6A) +-#define ISC40 0 +-#define ISC41 1 +-#define ISC50 2 +-#define ISC51 3 +-#define ISC60 4 +-#define ISC61 5 +-#define ISC70 6 +-#define ISC71 7 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define OCIE1C 3 +-#define ICIE1 5 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1C0 2 +-#define COM1C1 3 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1C 5 +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define OCR1C _SFR_MEM16(0x8C) +- +-#define OCR1CL _SFR_MEM8(0x8C) +-#define OCR1CL0 0 +-#define OCR1CL1 1 +-#define OCR1CL2 2 +-#define OCR1CL3 3 +-#define OCR1CL4 4 +-#define OCR1CL5 5 +-#define OCR1CL6 6 +-#define OCR1CL7 7 +- +-#define OCR1CH _SFR_MEM8(0x8D) +-#define OCR1CH0 0 +-#define OCR1CH1 1 +-#define OCR1CH2 2 +-#define OCR1CH3 3 +-#define OCR1CH4 4 +-#define OCR1CH5 5 +-#define OCR1CH6 6 +-#define OCR1CH7 7 +- +-#define UCSR1A _SFR_MEM8(0xC8) +-#define MPCM1 0 +-#define U2X1 1 +-#define UPE1 2 +-#define DOR1 3 +-#define FE1 4 +-#define UDRE1 5 +-#define TXC1 6 +-#define RXC1 7 +- +-#define UCSR1B _SFR_MEM8(0xC9) +-#define TXB81 0 +-#define RXB81 1 +-#define UCSZ12 2 +-#define TXEN1 3 +-#define RXEN1 4 +-#define UDRIE1 5 +-#define TXCIE1 6 +-#define RXCIE1 7 +- +-#define UCSR1C _SFR_MEM8(0xCA) +-#define UCPOL1 0 +-#define UCSZ10 1 +-#define UCSZ11 2 +-#define USBS1 3 +-#define UPM10 4 +-#define UPM11 5 +-#define UMSEL10 6 +-#define UMSEL11 7 +- +-#define UCSR1D _SFR_MEM8(0xCB) +-#define RTSEN 0 +-#define CTSEN 1 +- +-#define UBRR1 _SFR_MEM16(0xCC) +- +-#define UBRR1L _SFR_MEM8(0xCC) +-#define UBRR1_0 0 +-#define UBRR1_1 1 +-#define UBRR1_2 2 +-#define UBRR1_3 3 +-#define UBRR1_4 4 +-#define UBRR1_5 5 +-#define UBRR1_6 6 +-#define UBRR1_7 7 +- +-#define UBRR1H _SFR_MEM8(0xCD) +-#define UBRR1_8 0 +-#define UBRR1_9 1 +-#define UBRR1_10 2 +-#define UBRR1_11 3 +- +-#define UDR1 _SFR_MEM8(0xCE) +-#define UDR1_0 0 +-#define UDR1_1 1 +-#define UDR1_2 2 +-#define UDR1_3 3 +-#define UDR1_4 4 +-#define UDR1_5 5 +-#define UDR1_6 6 +-#define UDR1_7 7 +- +-#define CLKSEL0 _SFR_MEM8(0xD0) +-#define CLKS 0 +-#define EXTE 2 +-#define RCE 3 +-#define EXSUT0 4 +-#define EXSUT1 5 +-#define RCSUT0 6 +-#define RCSUT1 7 +- +-#define CLKSEL1 _SFR_MEM8(0xD1) +-#define EXCKSEL0 0 +-#define EXCKSEL1 1 +-#define EXCKSEL2 2 +-#define EXCKSEL3 3 +-#define RCCKSEL0 4 +-#define RCCKSEL1 5 +-#define RCCKSEL2 6 +-#define RCCKSEL3 7 +- +-#define CLKSTA _SFR_MEM8(0xD2) +-#define EXTON 0 +-#define RCON 1 +- +-#define USBCON _SFR_MEM8(0xD8) +-#define FRZCLK 5 +-#define USBE 7 +- +-#define UDCON _SFR_MEM8(0xE0) +-#define DETACH 0 +-#define RMWKUP 1 +-#define RSTCPU 2 +- +-#define UDINT _SFR_MEM8(0xE1) +-#define SUSPI 0 +-#define SOFI 2 +-#define EORSTI 3 +-#define WAKEUPI 4 +-#define EORSMI 5 +-#define UPRSMI 6 +- +-#define UDIEN _SFR_MEM8(0xE2) +-#define SUSPE 0 +-#define SOFE 2 +-#define EORSTE 3 +-#define WAKEUPE 4 +-#define EORSME 5 +-#define UPRSME 6 +- +-#define UDADDR _SFR_MEM8(0xE3) +-#define UADD0 0 +-#define UADD1 1 +-#define UADD2 2 +-#define UADD3 3 +-#define UADD4 4 +-#define UADD5 5 +-#define UADD6 6 +-#define ADDEN 7 +- +-#define UDFNUM _SFR_MEM16(0xE4) +- +-#define UDFNUML _SFR_MEM8(0xE4) +-#define FNUM0 0 +-#define FNUM1 1 +-#define FNUM2 2 +-#define FNUM3 3 +-#define FNUM4 4 +-#define FNUM5 5 +-#define FNUM6 6 +-#define FNUM7 7 +- +-#define UDFNUMH _SFR_MEM8(0xE5) +-#define FNUM8 0 +-#define FNUM9 1 +-#define FNUM10 2 +- +-#define UDMFN _SFR_MEM8(0xE6) +-#define FNCERR 4 +- +-#define UEINTX _SFR_MEM8(0xE8) +-#define TXINI 0 +-#define STALLEDI 1 +-#define RXOUTI 2 +-#define RXSTPI 3 +-#define NAKOUTI 4 +-#define RWAL 5 +-#define NAKINI 6 +-#define FIFOCON 7 +- +-#define UENUM _SFR_MEM8(0xE9) +-#define EPNUM0 0 +-#define EPNUM1 1 +-#define EPNUM2 2 +- +-#define UERST _SFR_MEM8(0xEA) +-#define EPRST0 0 +-#define EPRST1 1 +-#define EPRST2 2 +-#define EPRST3 3 +-#define EPRST4 4 +- +-#define UECONX _SFR_MEM8(0xEB) +-#define EPEN 0 +-#define RSTDT 3 +-#define STALLRQC 4 +-#define STALLRQ 5 +- +-#define UECFG0X _SFR_MEM8(0xEC) +-#define EPDIR 0 +-#define EPTYPE0 6 +-#define EPTYPE1 7 +- +-#define UECFG1X _SFR_MEM8(0xED) +-#define ALLOC 1 +-#define EPBK0 2 +-#define EPBK1 3 +-#define EPSIZE0 4 +-#define EPSIZE1 5 +-#define EPSIZE2 6 +- +-#define UESTA0X _SFR_MEM8(0xEE) +-#define NBUSYBK0 0 +-#define NBUSYBK1 1 +-#define DTSEQ0 2 +-#define DTSEQ1 3 +-#define UNDERFI 5 +-#define OVERFI 6 +-#define CFGOK 7 +- +-#define UESTA1X _SFR_MEM8(0xEF) +-#define CURRBK0 0 +-#define CURRBK1 1 +-#define CTRLDIR 2 +- +-#define UEIENX _SFR_MEM8(0xF0) +-#define TXINE 0 +-#define STALLEDE 1 +-#define RXOUTE 2 +-#define RXSTPE 3 +-#define NAKOUTE 4 +-#define NAKINE 6 +-#define FLERRE 7 +- +-#define UEDATX _SFR_MEM8(0xF1) +-#define DAT0 0 +-#define DAT1 1 +-#define DAT2 2 +-#define DAT3 3 +-#define DAT4 4 +-#define DAT5 5 +-#define DAT6 6 +-#define DAT7 7 +- +-#define UEBCLX _SFR_MEM8(0xF2) +-#define BYCT0 0 +-#define BYCT1 1 +-#define BYCT2 2 +-#define BYCT3 3 +-#define BYCT4 4 +-#define BYCT5 5 +-#define BYCT6 6 +-#define BYCT7 7 +- +-#define UEINT _SFR_MEM8(0xF4) +-#define EPINT0 0 +-#define EPINT1 1 +-#define EPINT2 2 +-#define EPINT3 3 +-#define EPINT4 4 +- +-#define UPOE _SFR_MEM8(0XFB) +-#define UPWE1 7 +-#define UPWE0 6 +-#define UPDRV1 5 +-#define UPDRV0 4 +-#define SCKI 3 +-#define DATAI 2 +-#define DPI 1 +-#define DMI 0 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ +-#define INT2_vect_num 3 +-#define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ +-#define INT3_vect_num 4 +-#define INT3_vect _VECTOR(4) /* External Interrupt Request 3 */ +-#define INT4_vect_num 5 +-#define INT4_vect _VECTOR(5) /* External Interrupt Request 4 */ +-#define INT5_vect_num 6 +-#define INT5_vect _VECTOR(6) /* External Interrupt Request 5 */ +-#define INT6_vect_num 7 +-#define INT6_vect _VECTOR(7) /* External Interrupt Request 6 */ +-#define INT7_vect_num 8 +-#define INT7_vect _VECTOR(8) /* External Interrupt Request 7 */ +-#define PCINT0_vect_num 9 +-#define PCINT0_vect _VECTOR(9) /* Pin Change Interrupt Request 0 */ +-#define PCINT1_vect_num 10 +-#define PCINT1_vect _VECTOR(10) /* Pin Change Interrupt Request 1 */ +-#define USB_GEN_vect_num 11 +-#define USB_GEN_vect _VECTOR(11) /* USB General Interrupt Request */ +-#define USB_COM_vect_num 12 +-#define USB_COM_vect _VECTOR(12) /* USB Endpoint/Pipe Interrupt Communication Request */ +-#define WDT_vect_num 13 +-#define WDT_vect _VECTOR(13) /* Watchdog Time-out Interrupt */ +-#define TIMER1_CAPT_vect_num 14 +-#define TIMER1_CAPT_vect _VECTOR(14) /* Timer/Counter2 Capture Event */ +-#define TIMER1_COMPA_vect_num 15 +-#define TIMER1_COMPA_vect _VECTOR(15) /* Timer/Counter2 Compare Match B */ +-#define TIMER0_COMPA_vect_num 19 +-#define TIMER0_COMPA_vect _VECTOR(19) /* Timer/Counter0 Compare Match A */ +-#define TIMER0_COMPB_vect_num 20 +-#define TIMER0_COMPB_vect _VECTOR(20) /* Timer/Counter0 Compare Match B */ +-#define TIMER0_OVF_vect_num 21 +-#define TIMER0_OVF_vect _VECTOR(21) /* Timer/Counter0 Overflow */ +-#define SPI_STC_vect_num 22 +-#define SPI_STC_vect _VECTOR(22) /* SPI Serial Transfer Complete */ +-#define USART1_RX_vect_num 23 +-#define USART1_RX_vect _VECTOR(23) /* USART1, Rx Complete */ +-#define USART1_UDRE_vect_num 24 +-#define USART1_UDRE_vect _VECTOR(24) /* USART1 Data register Empty */ +-#define USART1_TX_vect_num 25 +-#define USART1_TX_vect _VECTOR(25) /* USART1, Tx Complete */ +-#define ANALOG_COMP_vect_num 26 +-#define ANALOG_COMP_vect _VECTOR(26) /* Analog Comparator */ +-#define EE_READY_vect_num 27 +-#define EE_READY_vect _VECTOR(27) /* EEPROM Ready */ +-#define SPM_READY_vect_num 28 +-#define SPM_READY_vect _VECTOR(28) /* Store Program Memory Read */ +-#define TIMER1_COMPB_vect_num 16 +-#define TIMER1_COMPB_vect _VECTOR(16) /* Timer/Counter2 Compare Match B */ +-#define TIMER1_COMPC_vect_num 17 +-#define TIMER1_COMPC_vect _VECTOR(17) /* Timer/Counter2 Compare Match C */ +-#define TIMER1_OVF_vect_num 18 +-#define TIMER1_OVF_vect _VECTOR(18) /* Timer/Counter1 Overflow */ +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (29 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (128) +-#define RAMSTART (0x100) +-#define RAMSIZE (512) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x1FF) +-#define E2PAGESIZE (4) +-#define FLASHEND (0x1FFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(6) /* External Reset Disable */ +-#define FUSE_DWEN (unsigned char)~_BV(7) /* dwbugWIRE Enable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define FUSE_HWBE (unsigned char)~_BV(3) /* Hardware Boot Enable */ +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x93 +-#define SIGNATURE_2 0x89 +- +- +-/* Device Pin Definitions */ +-#endif /* _AVR_ATmega8U2_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iom8u2.h 2245 2011-05-12 22:42:21Z arcanum $ */ ++ ++/* avr/iom8u2.h - definitions for ATmega8U2 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom8u2.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATmega8U2_H_ ++#define _AVR_ATmega8U2_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++#define PINC7 7 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++#define DDC7 7 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC4 4 ++#define PORTC5 5 ++#define PORTC6 6 ++#define PORTC7 7 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define OCF1C 3 ++#define ICF1 5 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++#define INTF2 2 ++#define INTF3 3 ++#define INTF4 4 ++#define INTF5 5 ++#define INTF6 6 ++#define INTF7 7 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++#define INT2 2 ++#define INT3 3 ++#define INT4 4 ++#define INT5 5 ++#define INT6 6 ++#define INT7 7 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++#define EEAR9 1 ++#define EEAR10 2 ++#define EEAR11 3 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define OCR0A _SFR_IO8(0x27) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define OCR0B _SFR_IO8(0x28) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define PLLCSR _SFR_IO8(0x29) ++#define PLOCK 0 ++#define PLLE 1 ++#define PLLP0 2 ++#define PLLP1 3 ++#define PLLP2 4 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define DWDR _SFR_IO8(0x31) ++#define DWDR0 0 ++#define DWDR1 1 ++#define DWDR2 2 ++#define DWDR3 3 ++#define DWDR4 4 ++#define DWDR5 5 ++#define DWDR6 6 ++#define DWDR7 7 ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++#define USBRF 5 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVCE 0 ++#define IVSEL 1 ++#define PUD 4 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define BLBSET 3 ++#define RWWSRE 4 ++#define SIGRD 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++#define EIND _SFR_IO8(0x3C) ++#define EIND0 0 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define WDTCKD _SFR_MEM8(0x62) ++#define WCLKD0 0 ++#define WCLKD1 1 ++#define WDEWIE 2 ++#define WDEWIF 3 ++ ++#define REGCR _SFR_MEM8(0x63) ++#define REGDIS 0 ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRTIM0 5 ++ ++#define PRR1 _SFR_MEM8(0x65) ++#define PRUSART1 0 ++#define PRUSB 7 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define ISC20 4 ++#define ISC21 5 ++#define ISC30 6 ++#define ISC31 7 ++ ++#define EICRB _SFR_MEM8(0x6A) ++#define ISC40 0 ++#define ISC41 1 ++#define ISC50 2 ++#define ISC51 3 ++#define ISC60 4 ++#define ISC61 5 ++#define ISC70 6 ++#define ISC71 7 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define OCIE1C 3 ++#define ICIE1 5 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++#define AIN2D 2 ++#define AIN3D 3 ++#define AIN4D 4 ++#define AIN5D 5 ++#define AIN6D 6 ++#define AIN7D 7 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1C0 2 ++#define COM1C1 3 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1C 5 ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define OCR1C _SFR_MEM16(0x8C) ++ ++#define OCR1CL _SFR_MEM8(0x8C) ++#define OCR1CL0 0 ++#define OCR1CL1 1 ++#define OCR1CL2 2 ++#define OCR1CL3 3 ++#define OCR1CL4 4 ++#define OCR1CL5 5 ++#define OCR1CL6 6 ++#define OCR1CL7 7 ++ ++#define OCR1CH _SFR_MEM8(0x8D) ++#define OCR1CH0 0 ++#define OCR1CH1 1 ++#define OCR1CH2 2 ++#define OCR1CH3 3 ++#define OCR1CH4 4 ++#define OCR1CH5 5 ++#define OCR1CH6 6 ++#define OCR1CH7 7 ++ ++#define UCSR1A _SFR_MEM8(0xC8) ++#define MPCM1 0 ++#define U2X1 1 ++#define UPE1 2 ++#define DOR1 3 ++#define FE1 4 ++#define UDRE1 5 ++#define TXC1 6 ++#define RXC1 7 ++ ++#define UCSR1B _SFR_MEM8(0xC9) ++#define TXB81 0 ++#define RXB81 1 ++#define UCSZ12 2 ++#define TXEN1 3 ++#define RXEN1 4 ++#define UDRIE1 5 ++#define TXCIE1 6 ++#define RXCIE1 7 ++ ++#define UCSR1C _SFR_MEM8(0xCA) ++#define UCPOL1 0 ++#define UCSZ10 1 ++#define UCSZ11 2 ++#define USBS1 3 ++#define UPM10 4 ++#define UPM11 5 ++#define UMSEL10 6 ++#define UMSEL11 7 ++ ++#define UCSR1D _SFR_MEM8(0xCB) ++#define RTSEN 0 ++#define CTSEN 1 ++ ++#define UBRR1 _SFR_MEM16(0xCC) ++ ++#define UBRR1L _SFR_MEM8(0xCC) ++#define UBRR1_0 0 ++#define UBRR1_1 1 ++#define UBRR1_2 2 ++#define UBRR1_3 3 ++#define UBRR1_4 4 ++#define UBRR1_5 5 ++#define UBRR1_6 6 ++#define UBRR1_7 7 ++ ++#define UBRR1H _SFR_MEM8(0xCD) ++#define UBRR1_8 0 ++#define UBRR1_9 1 ++#define UBRR1_10 2 ++#define UBRR1_11 3 ++ ++#define UDR1 _SFR_MEM8(0xCE) ++#define UDR1_0 0 ++#define UDR1_1 1 ++#define UDR1_2 2 ++#define UDR1_3 3 ++#define UDR1_4 4 ++#define UDR1_5 5 ++#define UDR1_6 6 ++#define UDR1_7 7 ++ ++#define CLKSEL0 _SFR_MEM8(0xD0) ++#define CLKS 0 ++#define EXTE 2 ++#define RCE 3 ++#define EXSUT0 4 ++#define EXSUT1 5 ++#define RCSUT0 6 ++#define RCSUT1 7 ++ ++#define CLKSEL1 _SFR_MEM8(0xD1) ++#define EXCKSEL0 0 ++#define EXCKSEL1 1 ++#define EXCKSEL2 2 ++#define EXCKSEL3 3 ++#define RCCKSEL0 4 ++#define RCCKSEL1 5 ++#define RCCKSEL2 6 ++#define RCCKSEL3 7 ++ ++#define CLKSTA _SFR_MEM8(0xD2) ++#define EXTON 0 ++#define RCON 1 ++ ++#define USBCON _SFR_MEM8(0xD8) ++#define FRZCLK 5 ++#define USBE 7 ++ ++#define UDCON _SFR_MEM8(0xE0) ++#define DETACH 0 ++#define RMWKUP 1 ++#define RSTCPU 2 ++ ++#define UDINT _SFR_MEM8(0xE1) ++#define SUSPI 0 ++#define SOFI 2 ++#define EORSTI 3 ++#define WAKEUPI 4 ++#define EORSMI 5 ++#define UPRSMI 6 ++ ++#define UDIEN _SFR_MEM8(0xE2) ++#define SUSPE 0 ++#define SOFE 2 ++#define EORSTE 3 ++#define WAKEUPE 4 ++#define EORSME 5 ++#define UPRSME 6 ++ ++#define UDADDR _SFR_MEM8(0xE3) ++#define UADD0 0 ++#define UADD1 1 ++#define UADD2 2 ++#define UADD3 3 ++#define UADD4 4 ++#define UADD5 5 ++#define UADD6 6 ++#define ADDEN 7 ++ ++#define UDFNUM _SFR_MEM16(0xE4) ++ ++#define UDFNUML _SFR_MEM8(0xE4) ++#define FNUM0 0 ++#define FNUM1 1 ++#define FNUM2 2 ++#define FNUM3 3 ++#define FNUM4 4 ++#define FNUM5 5 ++#define FNUM6 6 ++#define FNUM7 7 ++ ++#define UDFNUMH _SFR_MEM8(0xE5) ++#define FNUM8 0 ++#define FNUM9 1 ++#define FNUM10 2 ++ ++#define UDMFN _SFR_MEM8(0xE6) ++#define FNCERR 4 ++ ++#define UEINTX _SFR_MEM8(0xE8) ++#define TXINI 0 ++#define STALLEDI 1 ++#define RXOUTI 2 ++#define RXSTPI 3 ++#define NAKOUTI 4 ++#define RWAL 5 ++#define NAKINI 6 ++#define FIFOCON 7 ++ ++#define UENUM _SFR_MEM8(0xE9) ++#define EPNUM0 0 ++#define EPNUM1 1 ++#define EPNUM2 2 ++ ++#define UERST _SFR_MEM8(0xEA) ++#define EPRST0 0 ++#define EPRST1 1 ++#define EPRST2 2 ++#define EPRST3 3 ++#define EPRST4 4 ++ ++#define UECONX _SFR_MEM8(0xEB) ++#define EPEN 0 ++#define RSTDT 3 ++#define STALLRQC 4 ++#define STALLRQ 5 ++ ++#define UECFG0X _SFR_MEM8(0xEC) ++#define EPDIR 0 ++#define EPTYPE0 6 ++#define EPTYPE1 7 ++ ++#define UECFG1X _SFR_MEM8(0xED) ++#define ALLOC 1 ++#define EPBK0 2 ++#define EPBK1 3 ++#define EPSIZE0 4 ++#define EPSIZE1 5 ++#define EPSIZE2 6 ++ ++#define UESTA0X _SFR_MEM8(0xEE) ++#define NBUSYBK0 0 ++#define NBUSYBK1 1 ++#define DTSEQ0 2 ++#define DTSEQ1 3 ++#define UNDERFI 5 ++#define OVERFI 6 ++#define CFGOK 7 ++ ++#define UESTA1X _SFR_MEM8(0xEF) ++#define CURRBK0 0 ++#define CURRBK1 1 ++#define CTRLDIR 2 ++ ++#define UEIENX _SFR_MEM8(0xF0) ++#define TXINE 0 ++#define STALLEDE 1 ++#define RXOUTE 2 ++#define RXSTPE 3 ++#define NAKOUTE 4 ++#define NAKINE 6 ++#define FLERRE 7 ++ ++#define UEDATX _SFR_MEM8(0xF1) ++#define DAT0 0 ++#define DAT1 1 ++#define DAT2 2 ++#define DAT3 3 ++#define DAT4 4 ++#define DAT5 5 ++#define DAT6 6 ++#define DAT7 7 ++ ++#define UEBCLX _SFR_MEM8(0xF2) ++#define BYCT0 0 ++#define BYCT1 1 ++#define BYCT2 2 ++#define BYCT3 3 ++#define BYCT4 4 ++#define BYCT5 5 ++#define BYCT6 6 ++#define BYCT7 7 ++ ++#define UEINT _SFR_MEM8(0xF4) ++#define EPINT0 0 ++#define EPINT1 1 ++#define EPINT2 2 ++#define EPINT3 3 ++#define EPINT4 4 ++ ++#define UPOE _SFR_MEM8(0XFB) ++#define UPWE1 7 ++#define UPWE0 6 ++#define UPDRV1 5 ++#define UPDRV0 4 ++#define SCKI 3 ++#define DATAI 2 ++#define DPI 1 ++#define DMI 0 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ ++#define INT2_vect_num 3 ++#define INT2_vect _VECTOR(3) /* External Interrupt Request 2 */ ++#define INT3_vect_num 4 ++#define INT3_vect _VECTOR(4) /* External Interrupt Request 3 */ ++#define INT4_vect_num 5 ++#define INT4_vect _VECTOR(5) /* External Interrupt Request 4 */ ++#define INT5_vect_num 6 ++#define INT5_vect _VECTOR(6) /* External Interrupt Request 5 */ ++#define INT6_vect_num 7 ++#define INT6_vect _VECTOR(7) /* External Interrupt Request 6 */ ++#define INT7_vect_num 8 ++#define INT7_vect _VECTOR(8) /* External Interrupt Request 7 */ ++#define PCINT0_vect_num 9 ++#define PCINT0_vect _VECTOR(9) /* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect_num 10 ++#define PCINT1_vect _VECTOR(10) /* Pin Change Interrupt Request 1 */ ++#define USB_GEN_vect_num 11 ++#define USB_GEN_vect _VECTOR(11) /* USB General Interrupt Request */ ++#define USB_COM_vect_num 12 ++#define USB_COM_vect _VECTOR(12) /* USB Endpoint/Pipe Interrupt Communication Request */ ++#define WDT_vect_num 13 ++#define WDT_vect _VECTOR(13) /* Watchdog Time-out Interrupt */ ++#define TIMER1_CAPT_vect_num 14 ++#define TIMER1_CAPT_vect _VECTOR(14) /* Timer/Counter2 Capture Event */ ++#define TIMER1_COMPA_vect_num 15 ++#define TIMER1_COMPA_vect _VECTOR(15) /* Timer/Counter2 Compare Match B */ ++#define TIMER0_COMPA_vect_num 19 ++#define TIMER0_COMPA_vect _VECTOR(19) /* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPB_vect_num 20 ++#define TIMER0_COMPB_vect _VECTOR(20) /* Timer/Counter0 Compare Match B */ ++#define TIMER0_OVF_vect_num 21 ++#define TIMER0_OVF_vect _VECTOR(21) /* Timer/Counter0 Overflow */ ++#define SPI_STC_vect_num 22 ++#define SPI_STC_vect _VECTOR(22) /* SPI Serial Transfer Complete */ ++#define USART1_RX_vect_num 23 ++#define USART1_RX_vect _VECTOR(23) /* USART1, Rx Complete */ ++#define USART1_UDRE_vect_num 24 ++#define USART1_UDRE_vect _VECTOR(24) /* USART1 Data register Empty */ ++#define USART1_TX_vect_num 25 ++#define USART1_TX_vect _VECTOR(25) /* USART1, Tx Complete */ ++#define ANALOG_COMP_vect_num 26 ++#define ANALOG_COMP_vect _VECTOR(26) /* Analog Comparator */ ++#define EE_READY_vect_num 27 ++#define EE_READY_vect _VECTOR(27) /* EEPROM Ready */ ++#define SPM_READY_vect_num 28 ++#define SPM_READY_vect _VECTOR(28) /* Store Program Memory Read */ ++#define TIMER1_COMPB_vect_num 16 ++#define TIMER1_COMPB_vect _VECTOR(16) /* Timer/Counter2 Compare Match B */ ++#define TIMER1_COMPC_vect_num 17 ++#define TIMER1_COMPC_vect _VECTOR(17) /* Timer/Counter2 Compare Match C */ ++#define TIMER1_OVF_vect_num 18 ++#define TIMER1_OVF_vect _VECTOR(18) /* Timer/Counter1 Overflow */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (29 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (128) ++#define RAMSTART (0x100) ++#define RAMSIZE (512) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x1FF) ++#define E2PAGESIZE (4) ++#define FLASHEND (0x1FFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Oscillator options */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) /* Select Reset Vector */ ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) /* Select Boot Size */ ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) /* Select Boot Size */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(6) /* External Reset Disable */ ++#define FUSE_DWEN (unsigned char)~_BV(7) /* dwbugWIRE Enable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define FUSE_HWBE (unsigned char)~_BV(3) /* Hardware Boot Enable */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x89 ++ ++ ++/* Device Pin Definitions */ ++#endif /* _AVR_ATmega8U2_H_ */ ++ +diff --git a/include/avr/iomx8.h b/include/avr/iomx8.h +index 99ab37a..088e959 100644 +--- a/include/avr/iomx8.h ++++ b/include/avr/iomx8.h +@@ -1,796 +1,799 @@ +-/* Copyright (c) 2004,2005, Theodore A. Roth +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iomx8.h 2235 2011-03-17 04:13:14Z arcanum $ */ +- +-/* avr/iomx8.h - definitions for ATmega48, ATmega88 and ATmega168 */ +- +-#ifndef _AVR_IOMX8_H_ +-#define _AVR_IOMX8_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iomx8.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* Port B */ +- +-#define PINB _SFR_IO8 (0x03) +-/* PINB */ +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-#define DDRB _SFR_IO8 (0x04) +-/* DDRB */ +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-#define PORTB _SFR_IO8 (0x05) +-/* PORTB */ +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* Port C */ +- +-#define PINC _SFR_IO8 (0x06) +-/* PINC */ +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-#define DDRC _SFR_IO8 (0x07) +-/* DDRC */ +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-#define PORTC _SFR_IO8 (0x08) +-/* PORTC */ +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-/* Port D */ +- +-#define PIND _SFR_IO8 (0x09) +-/* PIND */ +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-#define DDRD _SFR_IO8 (0x0A) +-/* DDRD */ +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-#define PORTD _SFR_IO8 (0x0B) +-/* PORTD */ +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-#define TIFR0 _SFR_IO8 (0x15) +-/* TIFR0 */ +-#define OCF0B 2 +-#define OCF0A 1 +-#define TOV0 0 +- +-#define TIFR1 _SFR_IO8 (0x16) +-/* TIFR1 */ +-#define ICF1 5 +-#define OCF1B 2 +-#define OCF1A 1 +-#define TOV1 0 +- +-#define TIFR2 _SFR_IO8 (0x17) +-/* TIFR2 */ +-#define OCF2B 2 +-#define OCF2A 1 +-#define TOV2 0 +- +-#define PCIFR _SFR_IO8 (0x1B) +-/* PCIFR */ +-#define PCIF2 2 +-#define PCIF1 1 +-#define PCIF0 0 +- +-#define EIFR _SFR_IO8 (0x1C) +-/* EIFR */ +-#define INTF1 1 +-#define INTF0 0 +- +-#define EIMSK _SFR_IO8 (0x1D) +-/* EIMSK */ +-#define INT1 1 +-#define INT0 0 +- +-#define GPIOR0 _SFR_IO8 (0x1E) +- +-#define EECR _SFR_IO8(0x1F) +-/* EECT - EEPROM Control Register */ +-#define EEPM1 5 +-#define EEPM0 4 +-#define EERIE 3 +-#define EEMPE 2 +-#define EEPE 1 +-#define EERE 0 +- +-#define EEDR _SFR_IO8(0X20) +- +-/* Combine EEARL and EEARH */ +-#define EEAR _SFR_IO16(0x21) +-#define EEARL _SFR_IO8(0x21) +-#define EEARH _SFR_IO8(0X22) +-/* +-Even though EEARH is not used by the mega48, the EEAR8 bit in the register +-must be written to 0, according to the datasheet, hence the EEARH register +-must be defined for the mega48. +-*/ +-/* 6-char sequence denoting where to find the EEPROM registers in memory space. +- Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM +- subroutines. +- First two letters: EECR address. +- Second two letters: EEDR address. +- Last two letters: EEAR address. */ +-#define __EEPROM_REG_LOCATIONS__ 1F2021 +- +- +-#define GTCCR _SFR_IO8 (0x23) +-/* GTCCR */ +-#define TSM 7 +-#define PSRASY 1 +-#define PSRSYNC 0 +- +-#define TCCR0A _SFR_IO8 (0x24) +-/* TCCR0A */ +-#define COM0A1 7 +-#define COM0A0 6 +-#define COM0B1 5 +-#define COM0B0 4 +-#define WGM01 1 +-#define WGM00 0 +- +-#define TCCR0B _SFR_IO8 (0x25) +-/* TCCR0A */ +-#define FOC0A 7 +-#define FOC0B 6 +-#define WGM02 3 +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-#define TCNT0 _SFR_IO8 (0x26) +-#define OCR0A _SFR_IO8 (0x27) +-#define OCR0B _SFR_IO8 (0x28) +- +-#define GPIOR1 _SFR_IO8 (0x2A) +-#define GPIOR2 _SFR_IO8 (0x2B) +- +-#define SPCR _SFR_IO8 (0x2C) +-/* SPCR */ +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +-#define SPSR _SFR_IO8 (0x2D) +-/* SPSR */ +-#define SPIF 7 +-#define WCOL 6 +-#define SPI2X 0 +- +-#define SPDR _SFR_IO8 (0x2E) +- +-#define ACSR _SFR_IO8 (0x30) +-/* ACSR */ +-#define ACD 7 +-#define ACBG 6 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +- +-#define MONDR _SFR_IO8 (0x31) +- +-#define SMCR _SFR_IO8 (0x33) +-/* SMCR */ +-#define SM2 3 +-#define SM1 2 +-#define SM0 1 +-#define SE 0 +- +-#define MCUSR _SFR_IO8 (0x34) +-/* MCUSR */ +-#define WDRF 3 +-#define BORF 2 +-#define EXTRF 1 +-#define PORF 0 +- +-#define MCUCR _SFR_IO8 (0x35) +-/* MCUCR */ +-#define PUD 4 +-#if defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__) +-#define IVSEL 1 +-#define IVCE 0 +-#endif +- +-#define SPMCSR _SFR_IO8 (0x37) +-/* SPMCSR */ +-#define SPMIE 7 +-#if defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__) +-# define RWWSB 6 +-# define RWWSRE 4 +-#endif +-#define BLBSET 3 +-#define PGWRT 2 +-#define PGERS 1 +-#define SELFPRGEN 0 +-#define SPMEN 0 +- +-/* 0x3D..0x3E SP [defined in ] */ +-/* 0x3F SREG [defined in ] */ +- +-#define WDTCSR _SFR_MEM8 (0x60) +-/* WDTCSR */ +-#define WDIF 7 +-#define WDIE 6 +-#define WDP3 5 +-#define WDCE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-#define CLKPR _SFR_MEM8 (0x61) +-/* CLKPR */ +-#define CLKPCE 7 +-#define CLKPS3 3 +-#define CLKPS2 2 +-#define CLKPS1 1 +-#define CLKPS0 0 +- +-#define PRR _SFR_MEM8 (0x64) +-/* PRR */ +-#define PRTWI 7 +-#define PRTIM2 6 +-#define PRTIM0 5 +-#define PRTIM1 3 +-#define PRSPI 2 +-#define PRUSART0 1 +-#define PRADC 0 +- +-#define OSCCAL _SFR_MEM8 (0x66) +- +-#define PCICR _SFR_MEM8 (0x68) +-/* PCICR */ +-#define PCIE2 2 +-#define PCIE1 1 +-#define PCIE0 0 +- +-#define EICRA _SFR_MEM8 (0x69) +-/* EICRA */ +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-#define PCMSK0 _SFR_MEM8 (0x6B) +-/* PCMSK0 */ +-#define PCINT7 7 +-#define PCINT6 6 +-#define PCINT5 5 +-#define PCINT4 4 +-#define PCINT3 3 +-#define PCINT2 2 +-#define PCINT1 1 +-#define PCINT0 0 +- +-#define PCMSK1 _SFR_MEM8 (0x6C) +-/* PCMSK1 */ +-#define PCINT14 6 +-#define PCINT13 5 +-#define PCINT12 4 +-#define PCINT11 3 +-#define PCINT10 2 +-#define PCINT9 1 +-#define PCINT8 0 +- +-#define PCMSK2 _SFR_MEM8 (0x6D) +-/* PCMSK2 */ +-#define PCINT23 7 +-#define PCINT22 6 +-#define PCINT21 5 +-#define PCINT20 4 +-#define PCINT19 3 +-#define PCINT18 2 +-#define PCINT17 1 +-#define PCINT16 0 +- +-#define TIMSK0 _SFR_MEM8 (0x6E) +-/* TIMSK0 */ +-#define OCIE0B 2 +-#define OCIE0A 1 +-#define TOIE0 0 +- +-#define TIMSK1 _SFR_MEM8 (0x6F) +-/* TIMSK1 */ +-#define ICIE1 5 +-#define OCIE1B 2 +-#define OCIE1A 1 +-#define TOIE1 0 +- +-#define TIMSK2 _SFR_MEM8 (0x70) +-/* TIMSK2 */ +-#define OCIE2B 2 +-#define OCIE2A 1 +-#define TOIE2 0 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16 (0x78) +-#endif +-#define ADCW _SFR_MEM16 (0x78) +-#define ADCL _SFR_MEM8 (0x78) +-#define ADCH _SFR_MEM8 (0x79) +- +-#define ADCSRA _SFR_MEM8 (0x7A) +-/* ADCSRA */ +-#define ADEN 7 +-#define ADSC 6 +-#define ADATE 5 +-#define ADIF 4 +-#define ADIE 3 +-#define ADPS2 2 +-#define ADPS1 1 +-#define ADPS0 0 +- +-#define ADCSRB _SFR_MEM8 (0x7B) +-/* ADCSRB */ +-#define ACME 6 +-#define ADTS2 2 +-#define ADTS1 1 +-#define ADTS0 0 +- +-#define ADMUX _SFR_MEM8 (0x7C) +-/* ADMUX */ +-#define REFS1 7 +-#define REFS0 6 +-#define ADLAR 5 +-#define MUX3 3 +-#define MUX2 2 +-#define MUX1 1 +-#define MUX0 0 +- +-#define DIDR0 _SFR_MEM8 (0x7E) +-/* DIDR0 */ +-#define ADC5D 5 +-#define ADC4D 4 +-#define ADC3D 3 +-#define ADC2D 2 +-#define ADC1D 1 +-#define ADC0D 0 +- +-#define DIDR1 _SFR_MEM8 (0x7F) +-/* DIDR1 */ +-#define AIN1D 1 +-#define AIN0D 0 +- +-#define TCCR1A _SFR_MEM8 (0x80) +-/* TCCR1A */ +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define WGM11 1 +-#define WGM10 0 +- +-#define TCCR1B _SFR_MEM8 (0x81) +-/* TCCR1B */ +-#define ICNC1 7 +-#define ICES1 6 +-#define WGM13 4 +-#define WGM12 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-#define TCCR1C _SFR_MEM8 (0x82) +-/* TCCR1C */ +-#define FOC1A 7 +-#define FOC1B 6 +- +-#define TCNT1 _SFR_MEM16 (0x84) +-#define TCNT1L _SFR_MEM8 (0x84) +-#define TCNT1H _SFR_MEM8 (0x85) +- +-#define ICR1 _SFR_MEM16 (0x86) +-#define ICR1L _SFR_MEM8 (0x86) +-#define ICR1H _SFR_MEM8 (0x87) +- +-#define OCR1A _SFR_MEM16 (0x88) +-#define OCR1AL _SFR_MEM8 (0x88) +-#define OCR1AH _SFR_MEM8 (0x89) +- +-#define OCR1B _SFR_MEM16 (0x8A) +-#define OCR1BL _SFR_MEM8 (0x8A) +-#define OCR1BH _SFR_MEM8 (0x8B) +- +-#define TCCR2A _SFR_MEM8 (0xB0) +-/* TCCR2A */ +-#define COM2A1 7 +-#define COM2A0 6 +-#define COM2B1 5 +-#define COM2B0 4 +-#define WGM21 1 +-#define WGM20 0 +- +-#define TCCR2B _SFR_MEM8 (0xB1) +-/* TCCR2B */ +-#define FOC2A 7 +-#define FOC2B 6 +-#define WGM22 3 +-#define CS22 2 +-#define CS21 1 +-#define CS20 0 +- +-#define TCNT2 _SFR_MEM8 (0xB2) +-#define OCR2A _SFR_MEM8 (0xB3) +-#define OCR2B _SFR_MEM8 (0xB4) +- +-#define ASSR _SFR_MEM8 (0xB6) +-/* ASSR */ +-#define EXCLK 6 +-#define AS2 5 +-#define TCN2UB 4 +-#define OCR2AUB 3 +-#define OCR2BUB 2 +-#define TCR2AUB 1 +-#define TCR2BUB 0 +- +-#define TWBR _SFR_MEM8 (0xB8) +- +-#define TWSR _SFR_MEM8 (0xB9) +-/* TWSR */ +-#define TWS7 7 +-#define TWS6 6 +-#define TWS5 5 +-#define TWS4 4 +-#define TWS3 3 +-#define TWPS1 1 +-#define TWPS0 0 +- +-#define TWAR _SFR_MEM8 (0xBA) +-/* TWAR */ +-#define TWA6 7 +-#define TWA5 6 +-#define TWA4 5 +-#define TWA3 4 +-#define TWA2 3 +-#define TWA1 2 +-#define TWA0 1 +-#define TWGCE 0 +- +-#define TWDR _SFR_MEM8 (0xBB) +- +-#define TWCR _SFR_MEM8 (0xBC) +-/* TWCR */ +-#define TWINT 7 +-#define TWEA 6 +-#define TWSTA 5 +-#define TWSTO 4 +-#define TWWC 3 +-#define TWEN 2 +-#define TWIE 0 +- +-#define TWAMR _SFR_MEM8 (0xBD) +-/* TWAMR */ +-#define TWAM6 7 +-#define TWAM5 6 +-#define TWAM4 5 +-#define TWAM3 4 +-#define TWAM2 3 +-#define TWAM1 2 +-#define TWAM0 1 +- +-#define UCSR0A _SFR_MEM8 (0xC0) +-/* UCSR0A */ +-#define RXC0 7 +-#define TXC0 6 +-#define UDRE0 5 +-#define FE0 4 +-#define DOR0 3 +-#define UPE0 2 +-#define U2X0 1 +-#define MPCM0 0 +- +-#define UCSR0B _SFR_MEM8 (0xC1) +-/* UCSR0B */ +-#define RXCIE0 7 +-#define TXCIE0 6 +-#define UDRIE0 5 +-#define RXEN0 4 +-#define TXEN0 3 +-#define UCSZ02 2 +-#define RXB80 1 +-#define TXB80 0 +- +-#define UCSR0C _SFR_MEM8 (0xC2) +-/* UCSR0C */ +-#define UMSEL01 7 +-#define UMSEL00 6 +-#define UPM01 5 +-#define UPM00 4 +-#define USBS0 3 +-#define UCSZ01 2 +-#define UDORD0 2 +-#define UCSZ00 1 +-#define UCPHA0 1 +-#define UCPOL0 0 +- +-#define UBRR0 _SFR_MEM16 (0xC4) +-#define UBRR0L _SFR_MEM8 (0xC4) +-#define UBRR0H _SFR_MEM8 (0xC5) +-#define UDR0 _SFR_MEM8 (0xC6) +- +-/* Interrupt vectors */ +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt Request 1 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +-#define SIG_INTERRUPT1 _VECTOR(2) +- +-/* Pin Change Interrupt Request 0 */ +-#define PCINT0_vect_num 3 +-#define PCINT0_vect _VECTOR(3) +-#define SIG_PIN_CHANGE0 _VECTOR(3) +- +-/* Pin Change Interrupt Request 0 */ +-#define PCINT1_vect_num 4 +-#define PCINT1_vect _VECTOR(4) +-#define SIG_PIN_CHANGE1 _VECTOR(4) +- +-/* Pin Change Interrupt Request 1 */ +-#define PCINT2_vect_num 5 +-#define PCINT2_vect _VECTOR(5) +-#define SIG_PIN_CHANGE2 _VECTOR(5) +- +-/* Watchdog Time-out Interrupt */ +-#define WDT_vect_num 6 +-#define WDT_vect _VECTOR(6) +-#define SIG_WATCHDOG_TIMEOUT _VECTOR(6) +- +-/* Timer/Counter2 Compare Match A */ +-#define TIMER2_COMPA_vect_num 7 +-#define TIMER2_COMPA_vect _VECTOR(7) +-#define SIG_OUTPUT_COMPARE2A _VECTOR(7) +- +-/* Timer/Counter2 Compare Match A */ +-#define TIMER2_COMPB_vect_num 8 +-#define TIMER2_COMPB_vect _VECTOR(8) +-#define SIG_OUTPUT_COMPARE2B _VECTOR(8) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 9 +-#define TIMER2_OVF_vect _VECTOR(9) +-#define SIG_OVERFLOW2 _VECTOR(9) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 10 +-#define TIMER1_CAPT_vect _VECTOR(10) +-#define SIG_INPUT_CAPTURE1 _VECTOR(10) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 11 +-#define TIMER1_COMPA_vect _VECTOR(11) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(11) +- +-/* Timer/Counter1 Compare Match B */ +-#define TIMER1_COMPB_vect_num 12 +-#define TIMER1_COMPB_vect _VECTOR(12) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(12) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 13 +-#define TIMER1_OVF_vect _VECTOR(13) +-#define SIG_OVERFLOW1 _VECTOR(13) +- +-/* TimerCounter0 Compare Match A */ +-#define TIMER0_COMPA_vect_num 14 +-#define TIMER0_COMPA_vect _VECTOR(14) +-#define SIG_OUTPUT_COMPARE0A _VECTOR(14) +- +-/* TimerCounter0 Compare Match B */ +-#define TIMER0_COMPB_vect_num 15 +-#define TIMER0_COMPB_vect _VECTOR(15) +-#define SIG_OUTPUT_COMPARE0B _VECTOR(15) +- +-/* Timer/Couner0 Overflow */ +-#define TIMER0_OVF_vect_num 16 +-#define TIMER0_OVF_vect _VECTOR(16) +-#define SIG_OVERFLOW0 _VECTOR(16) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 17 +-#define SPI_STC_vect _VECTOR(17) +-#define SIG_SPI _VECTOR(17) +- +-/* USART Rx Complete */ +-#define USART_RX_vect_num 18 +-#define USART_RX_vect _VECTOR(18) +-#define SIG_USART_RECV _VECTOR(18) +- +-/* USART, Data Register Empty */ +-#define USART_UDRE_vect_num 19 +-#define USART_UDRE_vect _VECTOR(19) +-#define SIG_USART_DATA _VECTOR(19) +- +-/* USART Tx Complete */ +-#define USART_TX_vect_num 20 +-#define USART_TX_vect _VECTOR(20) +-#define SIG_USART_TRANS _VECTOR(20) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 21 +-#define ADC_vect _VECTOR(21) +-#define SIG_ADC _VECTOR(21) +- +-/* EEPROM Ready */ +-#define EE_READY_vect_num 22 +-#define EE_READY_vect _VECTOR(22) +-#define SIG_EEPROM_READY _VECTOR(22) +- +-/* Analog Comparator */ +-#define ANALOG_COMP_vect_num 23 +-#define ANALOG_COMP_vect _VECTOR(23) +-#define SIG_COMPARATOR _VECTOR(23) +- +-/* Two-wire Serial Interface */ +-#define TWI_vect_num 24 +-#define TWI_vect _VECTOR(24) +-#define SIG_TWI _VECTOR(24) +-#define SIG_2WIRE_SERIAL _VECTOR(24) +- +-/* Store Program Memory Read */ +-#define SPM_READY_vect_num 25 +-#define SPM_READY_vect _VECTOR(25) +-#define SIG_SPM_READY _VECTOR(25) +- +-/* The mega48 and mega88 vector tables are single instruction entries (16 bits +- per entry for an RJMP) while the mega168 table has double instruction +- entries (32 bits per entry for a JMP). */ +- +-#if defined (__AVR_ATmega168__) || defined (__AVR_ATmega168A__) +-# define _VECTORS_SIZE 104 +-#else +-# define _VECTORS_SIZE 52 +-#endif +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_INTERRUPT1 +-#pragma GCC poison SIG_PIN_CHANGE0 +-#pragma GCC poison SIG_PIN_CHANGE1 +-#pragma GCC poison SIG_PIN_CHANGE2 +-#pragma GCC poison SIG_WATCHDOG_TIMEOUT +-#pragma GCC poison SIG_OUTPUT_COMPARE2A +-#pragma GCC poison SIG_OUTPUT_COMPARE2B +-#pragma GCC poison SIG_OVERFLOW2 +-#pragma GCC poison SIG_INPUT_CAPTURE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OUTPUT_COMPARE0A +-#pragma GCC poison SIG_OUTPUT_COMPARE0B +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_SPI +-#pragma GCC poison SIG_USART_RECV +-#pragma GCC poison SIG_USART_DATA +-#pragma GCC poison SIG_USART_TRANS +-#pragma GCC poison SIG_ADC +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_TWI +-#pragma GCC poison SIG_2WIRE_SERIAL +-#pragma GCC poison SIG_SPM_READY +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +-#endif /* _AVR_IOM8_H_ */ ++/* Copyright (c) 2004,2005, Theodore A. Roth ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iomx8.h 2235 2011-03-17 04:13:14Z arcanum $ */ ++ ++/* avr/iomx8.h - definitions for ATmega48, ATmega88 and ATmega168 */ ++ ++#ifndef _AVR_IOMX8_H_ ++#define _AVR_IOMX8_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iomx8.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* Port B */ ++ ++#define PINB _SFR_IO8 (0x03) ++/* PINB */ ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8 (0x04) ++/* DDRB */ ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++#define PORTB _SFR_IO8 (0x05) ++/* PORTB */ ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* Port C */ ++ ++#define PINC _SFR_IO8 (0x06) ++/* PINC */ ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8 (0x07) ++/* DDRC */ ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++#define PORTC _SFR_IO8 (0x08) ++/* PORTC */ ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++/* Port D */ ++ ++#define PIND _SFR_IO8 (0x09) ++/* PIND */ ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8 (0x0A) ++/* DDRD */ ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++#define PORTD _SFR_IO8 (0x0B) ++/* PORTD */ ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++#define TIFR0 _SFR_IO8 (0x15) ++/* TIFR0 */ ++#define OCF0B 2 ++#define OCF0A 1 ++#define TOV0 0 ++ ++#define TIFR1 _SFR_IO8 (0x16) ++/* TIFR1 */ ++#define ICF1 5 ++#define OCF1B 2 ++#define OCF1A 1 ++#define TOV1 0 ++ ++#define TIFR2 _SFR_IO8 (0x17) ++/* TIFR2 */ ++#define OCF2B 2 ++#define OCF2A 1 ++#define TOV2 0 ++ ++#define PCIFR _SFR_IO8 (0x1B) ++/* PCIFR */ ++#define PCIF2 2 ++#define PCIF1 1 ++#define PCIF0 0 ++ ++#define EIFR _SFR_IO8 (0x1C) ++/* EIFR */ ++#define INTF1 1 ++#define INTF0 0 ++ ++#define EIMSK _SFR_IO8 (0x1D) ++/* EIMSK */ ++#define INT1 1 ++#define INT0 0 ++ ++#define GPIOR0 _SFR_IO8 (0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++/* EECT - EEPROM Control Register */ ++#define EEPM1 5 ++#define EEPM0 4 ++#define EERIE 3 ++#define EEMPE 2 ++#define EEPE 1 ++#define EERE 0 ++ ++#define EEDR _SFR_IO8(0X20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0X22) ++/* ++Even though EEARH is not used by the mega48, the EEAR8 bit in the register ++must be written to 0, according to the datasheet, hence the EEARH register ++must be defined for the mega48. ++*/ ++/* 6-char sequence denoting where to find the EEPROM registers in memory space. ++ Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM ++ subroutines. ++ First two letters: EECR address. ++ Second two letters: EEDR address. ++ Last two letters: EEAR address. */ ++#define __EEPROM_REG_LOCATIONS__ 1F2021 ++ ++ ++#define GTCCR _SFR_IO8 (0x23) ++/* GTCCR */ ++#define TSM 7 ++#define PSRASY 1 ++#define PSRSYNC 0 ++ ++#define TCCR0A _SFR_IO8 (0x24) ++/* TCCR0A */ ++#define COM0A1 7 ++#define COM0A0 6 ++#define COM0B1 5 ++#define COM0B0 4 ++#define WGM01 1 ++#define WGM00 0 ++ ++#define TCCR0B _SFR_IO8 (0x25) ++/* TCCR0A */ ++#define FOC0A 7 ++#define FOC0B 6 ++#define WGM02 3 ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++#define TCNT0 _SFR_IO8 (0x26) ++#define OCR0A _SFR_IO8 (0x27) ++#define OCR0B _SFR_IO8 (0x28) ++ ++#define GPIOR1 _SFR_IO8 (0x2A) ++#define GPIOR2 _SFR_IO8 (0x2B) ++ ++#define SPCR _SFR_IO8 (0x2C) ++/* SPCR */ ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++#define SPSR _SFR_IO8 (0x2D) ++/* SPSR */ ++#define SPIF 7 ++#define WCOL 6 ++#define SPI2X 0 ++ ++#define SPDR _SFR_IO8 (0x2E) ++ ++#define ACSR _SFR_IO8 (0x30) ++/* ACSR */ ++#define ACD 7 ++#define ACBG 6 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++#define MONDR _SFR_IO8 (0x31) ++ ++#define SMCR _SFR_IO8 (0x33) ++/* SMCR */ ++#define SM2 3 ++#define SM1 2 ++#define SM0 1 ++#define SE 0 ++ ++#define MCUSR _SFR_IO8 (0x34) ++/* MCUSR */ ++#define WDRF 3 ++#define BORF 2 ++#define EXTRF 1 ++#define PORF 0 ++ ++#define MCUCR _SFR_IO8 (0x35) ++/* MCUCR */ ++#define PUD 4 ++#if defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__) ++#define IVSEL 1 ++#define IVCE 0 ++#endif ++ ++#define SPMCSR _SFR_IO8 (0x37) ++/* SPMCSR */ ++#define SPMIE 7 ++#if defined (__AVR_ATmega88__) || defined (__AVR_ATmega168__) || (__AVR_ATmega88P__) || defined (__AVR_ATmega168P__) || (__AVR_ATmega88A__) || defined (__AVR_ATmega168A__) || (__AVR_ATmega88PA__) || defined (__AVR_ATmega168PA__) ++# define RWWSB 6 ++# define RWWSRE 4 ++#endif ++#if defined(__AVR_ATmega48A) || defined(__AVR_ATmega48PA) || defined(__AVR_ATmega88A) || defined(__AVR_ATmega88PA) || defined(__AVR_ATmega168A) || defined(__AVR_ATmega168PA) ++ #define SIGRD 5 ++#endif ++#define BLBSET 3 ++#define PGWRT 2 ++#define PGERS 1 ++#define SELFPRGEN 0 ++#define SPMEN 0 ++ ++/* 0x3D..0x3E SP [defined in ] */ ++/* 0x3F SREG [defined in ] */ ++ ++#define WDTCSR _SFR_MEM8 (0x60) ++/* WDTCSR */ ++#define WDIF 7 ++#define WDIE 6 ++#define WDP3 5 ++#define WDCE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++#define CLKPR _SFR_MEM8 (0x61) ++/* CLKPR */ ++#define CLKPCE 7 ++#define CLKPS3 3 ++#define CLKPS2 2 ++#define CLKPS1 1 ++#define CLKPS0 0 ++ ++#define PRR _SFR_MEM8 (0x64) ++/* PRR */ ++#define PRTWI 7 ++#define PRTIM2 6 ++#define PRTIM0 5 ++#define PRTIM1 3 ++#define PRSPI 2 ++#define PRUSART0 1 ++#define PRADC 0 ++ ++#define OSCCAL _SFR_MEM8 (0x66) ++ ++#define PCICR _SFR_MEM8 (0x68) ++/* PCICR */ ++#define PCIE2 2 ++#define PCIE1 1 ++#define PCIE0 0 ++ ++#define EICRA _SFR_MEM8 (0x69) ++/* EICRA */ ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++#define PCMSK0 _SFR_MEM8 (0x6B) ++/* PCMSK0 */ ++#define PCINT7 7 ++#define PCINT6 6 ++#define PCINT5 5 ++#define PCINT4 4 ++#define PCINT3 3 ++#define PCINT2 2 ++#define PCINT1 1 ++#define PCINT0 0 ++ ++#define PCMSK1 _SFR_MEM8 (0x6C) ++/* PCMSK1 */ ++#define PCINT14 6 ++#define PCINT13 5 ++#define PCINT12 4 ++#define PCINT11 3 ++#define PCINT10 2 ++#define PCINT9 1 ++#define PCINT8 0 ++ ++#define PCMSK2 _SFR_MEM8 (0x6D) ++/* PCMSK2 */ ++#define PCINT23 7 ++#define PCINT22 6 ++#define PCINT21 5 ++#define PCINT20 4 ++#define PCINT19 3 ++#define PCINT18 2 ++#define PCINT17 1 ++#define PCINT16 0 ++ ++#define TIMSK0 _SFR_MEM8 (0x6E) ++/* TIMSK0 */ ++#define OCIE0B 2 ++#define OCIE0A 1 ++#define TOIE0 0 ++ ++#define TIMSK1 _SFR_MEM8 (0x6F) ++/* TIMSK1 */ ++#define ICIE1 5 ++#define OCIE1B 2 ++#define OCIE1A 1 ++#define TOIE1 0 ++ ++#define TIMSK2 _SFR_MEM8 (0x70) ++/* TIMSK2 */ ++#define OCIE2B 2 ++#define OCIE2A 1 ++#define TOIE2 0 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16 (0x78) ++#endif ++#define ADCW _SFR_MEM16 (0x78) ++#define ADCL _SFR_MEM8 (0x78) ++#define ADCH _SFR_MEM8 (0x79) ++ ++#define ADCSRA _SFR_MEM8 (0x7A) ++/* ADCSRA */ ++#define ADEN 7 ++#define ADSC 6 ++#define ADATE 5 ++#define ADIF 4 ++#define ADIE 3 ++#define ADPS2 2 ++#define ADPS1 1 ++#define ADPS0 0 ++ ++#define ADCSRB _SFR_MEM8 (0x7B) ++/* ADCSRB */ ++#define ACME 6 ++#define ADTS2 2 ++#define ADTS1 1 ++#define ADTS0 0 ++ ++#define ADMUX _SFR_MEM8 (0x7C) ++/* ADMUX */ ++#define REFS1 7 ++#define REFS0 6 ++#define ADLAR 5 ++#define MUX3 3 ++#define MUX2 2 ++#define MUX1 1 ++#define MUX0 0 ++ ++#define DIDR0 _SFR_MEM8 (0x7E) ++/* DIDR0 */ ++#define ADC5D 5 ++#define ADC4D 4 ++#define ADC3D 3 ++#define ADC2D 2 ++#define ADC1D 1 ++#define ADC0D 0 ++ ++#define DIDR1 _SFR_MEM8 (0x7F) ++/* DIDR1 */ ++#define AIN1D 1 ++#define AIN0D 0 ++ ++#define TCCR1A _SFR_MEM8 (0x80) ++/* TCCR1A */ ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define WGM11 1 ++#define WGM10 0 ++ ++#define TCCR1B _SFR_MEM8 (0x81) ++/* TCCR1B */ ++#define ICNC1 7 ++#define ICES1 6 ++#define WGM13 4 ++#define WGM12 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++#define TCCR1C _SFR_MEM8 (0x82) ++/* TCCR1C */ ++#define FOC1A 7 ++#define FOC1B 6 ++ ++#define TCNT1 _SFR_MEM16 (0x84) ++#define TCNT1L _SFR_MEM8 (0x84) ++#define TCNT1H _SFR_MEM8 (0x85) ++ ++#define ICR1 _SFR_MEM16 (0x86) ++#define ICR1L _SFR_MEM8 (0x86) ++#define ICR1H _SFR_MEM8 (0x87) ++ ++#define OCR1A _SFR_MEM16 (0x88) ++#define OCR1AL _SFR_MEM8 (0x88) ++#define OCR1AH _SFR_MEM8 (0x89) ++ ++#define OCR1B _SFR_MEM16 (0x8A) ++#define OCR1BL _SFR_MEM8 (0x8A) ++#define OCR1BH _SFR_MEM8 (0x8B) ++ ++#define TCCR2A _SFR_MEM8 (0xB0) ++/* TCCR2A */ ++#define COM2A1 7 ++#define COM2A0 6 ++#define COM2B1 5 ++#define COM2B0 4 ++#define WGM21 1 ++#define WGM20 0 ++ ++#define TCCR2B _SFR_MEM8 (0xB1) ++/* TCCR2B */ ++#define FOC2A 7 ++#define FOC2B 6 ++#define WGM22 3 ++#define CS22 2 ++#define CS21 1 ++#define CS20 0 ++ ++#define TCNT2 _SFR_MEM8 (0xB2) ++#define OCR2A _SFR_MEM8 (0xB3) ++#define OCR2B _SFR_MEM8 (0xB4) ++ ++#define ASSR _SFR_MEM8 (0xB6) ++/* ASSR */ ++#define EXCLK 6 ++#define AS2 5 ++#define TCN2UB 4 ++#define OCR2AUB 3 ++#define OCR2BUB 2 ++#define TCR2AUB 1 ++#define TCR2BUB 0 ++ ++#define TWBR _SFR_MEM8 (0xB8) ++ ++#define TWSR _SFR_MEM8 (0xB9) ++/* TWSR */ ++#define TWS7 7 ++#define TWS6 6 ++#define TWS5 5 ++#define TWS4 4 ++#define TWS3 3 ++#define TWPS1 1 ++#define TWPS0 0 ++ ++#define TWAR _SFR_MEM8 (0xBA) ++/* TWAR */ ++#define TWA6 7 ++#define TWA5 6 ++#define TWA4 5 ++#define TWA3 4 ++#define TWA2 3 ++#define TWA1 2 ++#define TWA0 1 ++#define TWGCE 0 ++ ++#define TWDR _SFR_MEM8 (0xBB) ++ ++#define TWCR _SFR_MEM8 (0xBC) ++/* TWCR */ ++#define TWINT 7 ++#define TWEA 6 ++#define TWSTA 5 ++#define TWSTO 4 ++#define TWWC 3 ++#define TWEN 2 ++#define TWIE 0 ++ ++#define TWAMR _SFR_MEM8 (0xBD) ++/* TWAMR */ ++#define TWAM6 7 ++#define TWAM5 6 ++#define TWAM4 5 ++#define TWAM3 4 ++#define TWAM2 3 ++#define TWAM1 2 ++#define TWAM0 1 ++ ++#define UCSR0A _SFR_MEM8 (0xC0) ++/* UCSR0A */ ++#define RXC0 7 ++#define TXC0 6 ++#define UDRE0 5 ++#define FE0 4 ++#define DOR0 3 ++#define UPE0 2 ++#define U2X0 1 ++#define MPCM0 0 ++ ++#define UCSR0B _SFR_MEM8 (0xC1) ++/* UCSR0B */ ++#define RXCIE0 7 ++#define TXCIE0 6 ++#define UDRIE0 5 ++#define RXEN0 4 ++#define TXEN0 3 ++#define UCSZ02 2 ++#define RXB80 1 ++#define TXB80 0 ++ ++#define UCSR0C _SFR_MEM8 (0xC2) ++/* UCSR0C */ ++#define UMSEL01 7 ++#define UMSEL00 6 ++#define UPM01 5 ++#define UPM00 4 ++#define USBS0 3 ++#define UCSZ01 2 ++#define UDORD0 2 ++#define UCSZ00 1 ++#define UCPHA0 1 ++#define UCPOL0 0 ++ ++#define UBRR0 _SFR_MEM16 (0xC4) ++#define UBRR0L _SFR_MEM8 (0xC4) ++#define UBRR0H _SFR_MEM8 (0xC5) ++#define UDR0 _SFR_MEM8 (0xC6) ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++#define SIG_INTERRUPT1 _VECTOR(2) ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect_num 3 ++#define PCINT0_vect _VECTOR(3) ++#define SIG_PIN_CHANGE0 _VECTOR(3) ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect_num 4 ++#define PCINT1_vect _VECTOR(4) ++#define SIG_PIN_CHANGE1 _VECTOR(4) ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT2_vect_num 5 ++#define PCINT2_vect _VECTOR(5) ++#define SIG_PIN_CHANGE2 _VECTOR(5) ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect_num 6 ++#define WDT_vect _VECTOR(6) ++#define SIG_WATCHDOG_TIMEOUT _VECTOR(6) ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPA_vect_num 7 ++#define TIMER2_COMPA_vect _VECTOR(7) ++#define SIG_OUTPUT_COMPARE2A _VECTOR(7) ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPB_vect_num 8 ++#define TIMER2_COMPB_vect _VECTOR(8) ++#define SIG_OUTPUT_COMPARE2B _VECTOR(8) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 9 ++#define TIMER2_OVF_vect _VECTOR(9) ++#define SIG_OVERFLOW2 _VECTOR(9) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 10 ++#define TIMER1_CAPT_vect _VECTOR(10) ++#define SIG_INPUT_CAPTURE1 _VECTOR(10) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 11 ++#define TIMER1_COMPA_vect _VECTOR(11) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(11) ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect_num 12 ++#define TIMER1_COMPB_vect _VECTOR(12) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(12) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 13 ++#define TIMER1_OVF_vect _VECTOR(13) ++#define SIG_OVERFLOW1 _VECTOR(13) ++ ++/* TimerCounter0 Compare Match A */ ++#define TIMER0_COMPA_vect_num 14 ++#define TIMER0_COMPA_vect _VECTOR(14) ++#define SIG_OUTPUT_COMPARE0A _VECTOR(14) ++ ++/* TimerCounter0 Compare Match B */ ++#define TIMER0_COMPB_vect_num 15 ++#define TIMER0_COMPB_vect _VECTOR(15) ++#define SIG_OUTPUT_COMPARE0B _VECTOR(15) ++ ++/* Timer/Couner0 Overflow */ ++#define TIMER0_OVF_vect_num 16 ++#define TIMER0_OVF_vect _VECTOR(16) ++#define SIG_OVERFLOW0 _VECTOR(16) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 17 ++#define SPI_STC_vect _VECTOR(17) ++#define SIG_SPI _VECTOR(17) ++ ++/* USART Rx Complete */ ++#define USART_RX_vect_num 18 ++#define USART_RX_vect _VECTOR(18) ++#define SIG_USART_RECV _VECTOR(18) ++ ++/* USART, Data Register Empty */ ++#define USART_UDRE_vect_num 19 ++#define USART_UDRE_vect _VECTOR(19) ++#define SIG_USART_DATA _VECTOR(19) ++ ++/* USART Tx Complete */ ++#define USART_TX_vect_num 20 ++#define USART_TX_vect _VECTOR(20) ++#define SIG_USART_TRANS _VECTOR(20) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 21 ++#define ADC_vect _VECTOR(21) ++#define SIG_ADC _VECTOR(21) ++ ++/* EEPROM Ready */ ++#define EE_READY_vect_num 22 ++#define EE_READY_vect _VECTOR(22) ++#define SIG_EEPROM_READY _VECTOR(22) ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect_num 23 ++#define ANALOG_COMP_vect _VECTOR(23) ++#define SIG_COMPARATOR _VECTOR(23) ++ ++/* Two-wire Serial Interface */ ++#define TWI_vect_num 24 ++#define TWI_vect _VECTOR(24) ++#define SIG_TWI _VECTOR(24) ++#define SIG_2WIRE_SERIAL _VECTOR(24) ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect_num 25 ++#define SPM_READY_vect _VECTOR(25) ++#define SIG_SPM_READY _VECTOR(25) ++ ++/* The mega48 and mega88 vector tables are single instruction entries (16 bits ++ per entry for an RJMP) while the mega168 table has double instruction ++ entries (32 bits per entry for a JMP). */ ++ ++#if defined (__AVR_ATmega168__) || defined (__AVR_ATmega168A__) ++# define _VECTORS_SIZE 104 ++#else ++# define _VECTORS_SIZE 52 ++#endif ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_INTERRUPT1 ++#pragma GCC poison SIG_PIN_CHANGE0 ++#pragma GCC poison SIG_PIN_CHANGE1 ++#pragma GCC poison SIG_PIN_CHANGE2 ++#pragma GCC poison SIG_WATCHDOG_TIMEOUT ++#pragma GCC poison SIG_OUTPUT_COMPARE2A ++#pragma GCC poison SIG_OUTPUT_COMPARE2B ++#pragma GCC poison SIG_OVERFLOW2 ++#pragma GCC poison SIG_INPUT_CAPTURE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OUTPUT_COMPARE0A ++#pragma GCC poison SIG_OUTPUT_COMPARE0B ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_SPI ++#pragma GCC poison SIG_USART_RECV ++#pragma GCC poison SIG_USART_DATA ++#pragma GCC poison SIG_USART_TRANS ++#pragma GCC poison SIG_ADC ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_TWI ++#pragma GCC poison SIG_2WIRE_SERIAL ++#pragma GCC poison SIG_SPM_READY ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++#endif /* _AVR_IOM8_H_ */ +diff --git a/include/avr/iomxx0_1.h b/include/avr/iomxx0_1.h +index 74e807d..ff39d3b 100644 +--- a/include/avr/iomxx0_1.h ++++ b/include/avr/iomxx0_1.h +@@ -1,1675 +1,1675 @@ +-/* Copyright (c) 2005 Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iomxx0_1.h 2235 2011-03-17 04:13:14Z arcanum $ */ +- +-/* avr/iomxx0_1.h - definitions for ATmega640, Atmega1280, ATmega1281, +- ATmega2560 and ATmega2561. */ +- +-#ifndef _AVR_IOMXX0_1_H_ +-#define _AVR_IOMXX0_1_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iomxx0_1.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-#if defined(__AVR_ATmega640__) || defined(__AVR_ATmega1280__) || defined(__AVR_ATmega2560__) +-# define __ATmegaxx0__ +-#elif defined(__AVR_ATmega1281__) || defined(__AVR_ATmega2561__) +-# define __ATmegaxx1__ +-#endif +- +-/* Registers and associated bit numbers */ +- +-#define PINA _SFR_IO8(0X00) +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-#define DDRA _SFR_IO8(0X01) +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-#define PORTA _SFR_IO8(0X02) +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-#define PINB _SFR_IO8(0X03) +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-#define PORTB _SFR_IO8(0x05) +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-#define PORTC _SFR_IO8(0x08) +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-#define PINE _SFR_IO8(0x0C) +-#define PINE7 7 +-#define PINE6 6 +-#define PINE5 5 +-#define PINE4 4 +-#define PINE3 3 +-#define PINE2 2 +-#define PINE1 1 +-#define PINE0 0 +- +-#define DDRE _SFR_IO8(0x0D) +-#define DDE7 7 +-#define DDE6 6 +-#define DDE5 5 +-#define DDE4 4 +-#define DDE3 3 +-#define DDE2 2 +-#define DDE1 1 +-#define DDE0 0 +- +-#define PORTE _SFR_IO8(0x0E) +-#define PE7 7 +-#define PE6 6 +-#define PE5 5 +-#define PE4 4 +-#define PE3 3 +-#define PE2 2 +-#define PE1 1 +-#define PE0 0 +- +-#define PINF _SFR_IO8(0x0F) +-#define PINF7 7 +-#define PINF6 6 +-#define PINF5 5 +-#define PINF4 4 +-#define PINF3 3 +-#define PINF2 2 +-#define PINF1 1 +-#define PINF0 0 +- +-#define DDRF _SFR_IO8(0x10) +-#define DDF7 7 +-#define DDF6 6 +-#define DDF5 5 +-#define DDF4 4 +-#define DDF3 3 +-#define DDF2 2 +-#define DDF1 1 +-#define DDF0 0 +- +-#define PORTF _SFR_IO8(0x11) +-#define PF7 7 +-#define PF6 6 +-#define PF5 5 +-#define PF4 4 +-#define PF3 3 +-#define PF2 2 +-#define PF1 1 +-#define PF0 0 +- +-#define PING _SFR_IO8(0x12) +-#define PING5 5 +-#define PING4 4 +-#define PING3 3 +-#define PING2 2 +-#define PING1 1 +-#define PING0 0 +- +-#define DDRG _SFR_IO8(0x13) +-#define DDG5 5 +-#define DDG4 4 +-#define DDG3 3 +-#define DDG2 2 +-#define DDG1 1 +-#define DDG0 0 +- +-#define PORTG _SFR_IO8(0x14) +-#define PG5 5 +-#define PG4 4 +-#define PG3 3 +-#define PG2 2 +-#define PG1 1 +-#define PG0 0 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define OCF0B 2 +-#define OCF0A 1 +-#define TOV0 0 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define ICF1 5 +-#define OCF1C 3 +-#define OCF1B 2 +-#define OCF1A 1 +-#define TOV1 0 +- +-#define TIFR2 _SFR_IO8(0x17) +-#define OCF2B 2 +-#define OCF2A 1 +-#define TOV2 0 +- +-#define TIFR3 _SFR_IO8(0x18) +-#define ICF3 5 +-#define OCF3C 3 +-#define OCF3B 2 +-#define OCF3A 1 +-#define TOV3 0 +- +-#define TIFR4 _SFR_IO8(0x19) +-#define ICF4 5 +-#define OCF4C 3 +-#define OCF4B 2 +-#define OCF4A 1 +-#define TOV4 0 +- +-#define TIFR5 _SFR_IO8(0x1A) +-#define ICF5 5 +-#define OCF5C 3 +-#define OCF5B 2 +-#define OCF5A 1 +-#define TOV5 0 +- +-#define PCIFR _SFR_IO8(0x1B) +-#if defined(__ATmegaxx0__) +-# define PCIF2 2 +-#endif /* __ATmegaxx0__ */ +-#define PCIF1 1 +-#define PCIF0 0 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF7 7 +-#define INTF6 6 +-#define INTF5 5 +-#define INTF4 4 +-#define INTF3 3 +-#define INTF2 2 +-#define INTF1 1 +-#define INTF0 0 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT7 7 +-#define INT6 6 +-#define INT5 5 +-#define INT4 4 +-#define INT3 3 +-#define INT2 2 +-#define INT1 1 +-#define INT0 0 +- +-#define GPIOR0 _SFR_IO8(0x1E) +- +-#define EECR _SFR_IO8(0x1F) +-#define EEPM1 5 +-#define EEPM0 4 +-#define EERIE 3 +-#define EEMPE 2 +-#define EEPE 1 +-#define EERE 0 +- +-#define EEDR _SFR_IO8(0X20) +- +-/* Combine EEARL and EEARH */ +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEARH _SFR_IO8(0X22) +- +-/* 6-char sequence denoting where to find the EEPROM registers in memory space. +- Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM +- subroutines. +- First two letters: EECR address. +- Second two letters: EEDR address. +- Last two letters: EEAR address. */ +-#define __EEPROM_REG_LOCATIONS__ 1F2021 +- +-#define GTCCR _SFR_IO8(0x23) +-#define TSM 7 +-#define PSRASY 1 +-#define PSRSYNC 0 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define COM0A1 7 +-#define COM0A0 6 +-#define COM0B1 5 +-#define COM0B0 4 +-#define WGM01 1 +-#define WGM00 0 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define FOC0A 7 +-#define FOC0B 6 +-#define WGM02 3 +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-#define TCNT0 _SFR_IO8(0X26) +- +-#define OCR0A _SFR_IO8(0X27) +- +-#define OCR0B _SFR_IO8(0X28) +- +-/* Reserved [0x29] */ +- +-#define GPIOR1 _SFR_IO8(0x2A) +- +-#define GPIOR2 _SFR_IO8(0x2B) +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPIF 7 +-#define WCOL 6 +-#define SPI2X 0 +- +-#define SPDR _SFR_IO8(0X2E) +- +-/* Reserved [0x2F] */ +- +-#define ACSR _SFR_IO8(0x30) +-#define ACD 7 +-#define ACBG 6 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +- +-#define MONDR _SFR_IO8(0x31) +-#define OCDR _SFR_IO8(0x31) +-#define IDRD 7 +-#define OCDR7 7 +-#define OCDR6 6 +-#define OCDR5 5 +-#define OCDR4 4 +-#define OCDR3 3 +-#define OCDR2 2 +-#define OCDR1 1 +-#define OCDR0 0 +- +-/* Reserved [0x32] */ +- +-#define SMCR _SFR_IO8(0x33) +-#define SM2 3 +-#define SM1 2 +-#define SM0 1 +-#define SE 0 +- +-#define MCUSR _SFR_IO8(0x34) +-#define JTRF 4 +-#define WDRF 3 +-#define BORF 2 +-#define EXTRF 1 +-#define PORF 0 +- +-#define MCUCR _SFR_IO8(0X35) +-#define JTD 7 +-#define PUD 4 +-#define IVSEL 1 +-#define IVCE 0 +- +-/* Reserved [0x36] */ +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMIE 7 +-#define RWWSB 6 +-#define SIGRD 5 +-#define RWWSRE 4 +-#define BLBSET 3 +-#define PGWRT 2 +-#define PGERS 1 +-#define SPMEN 0 +- +-/* Reserved [0x38..0x3A] */ +- +-#define RAMPZ _SFR_IO8(0X3B) +-#define RAMPZ0 0 +- +-#define EIND _SFR_IO8(0X3C) +-#define EIND0 0 +- +-/* SP [0x3D..0x3E] */ +-/* SREG [0x3F] */ +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDIF 7 +-#define WDIE 6 +-#define WDP3 5 +-#define WDCE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPCE 7 +-#define CLKPS3 3 +-#define CLKPS2 2 +-#define CLKPS1 1 +-#define CLKPS0 0 +- +-/* Reserved [0x62..0x63] */ +- +-#define PRR0 _SFR_MEM8(0x64) +-#define PRTWI 7 +-#define PRTIM2 6 +-#define PRTIM0 5 +-#define PRTIM1 3 +-#define PRSPI 2 +-#define PRUSART0 1 +-#define PRADC 0 +- +-#define PRR1 _SFR_MEM8(0x65) +-#define PRTIM5 5 +-#define PRTIM4 4 +-#define PRTIM3 3 +-#define PRUSART3 2 +-#define PRUSART2 1 +-#define PRUSART1 0 +- +-#define OSCCAL _SFR_MEM8(0x66) +- +-/* Reserved [0x67] */ +- +-#define PCICR _SFR_MEM8(0x68) +-#if defined(__ATmegaxx0__) +-# define PCIE2 2 +-#endif /* __ATmegaxx0__ */ +-#define PCIE1 1 +-#define PCIE0 0 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC31 7 +-#define ISC30 6 +-#define ISC21 5 +-#define ISC20 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-#define EICRB _SFR_MEM8(0x6A) +-#define ISC71 7 +-#define ISC70 6 +-#define ISC61 5 +-#define ISC60 4 +-#define ISC51 3 +-#define ISC50 2 +-#define ISC41 1 +-#define ISC40 0 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT7 7 +-#define PCINT6 6 +-#define PCINT5 5 +-#define PCINT4 4 +-#define PCINT3 3 +-#define PCINT2 2 +-#define PCINT1 1 +-#define PCINT0 0 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT15 7 +-#define PCINT14 6 +-#define PCINT13 5 +-#define PCINT12 4 +-#define PCINT11 3 +-#define PCINT10 2 +-#define PCINT9 1 +-#define PCINT8 0 +- +-#if defined(__ATmegaxx0__) +-# define PCMSK2 _SFR_MEM8(0x6D) +-# define PCINT23 7 +-# define PCINT22 6 +-# define PCINT21 5 +-# define PCINT20 4 +-# define PCINT19 3 +-# define PCINT18 2 +-# define PCINT17 1 +-# define PCINT16 0 +-#endif /* __ATmegaxx0__ */ +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define OCIE0B 2 +-#define OCIE0A 1 +-#define TOIE0 0 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define ICIE1 5 +-#define OCIE1C 3 +-#define OCIE1B 2 +-#define OCIE1A 1 +-#define TOIE1 0 +- +-#define TIMSK2 _SFR_MEM8(0x70) +-#define OCIE2B 2 +-#define OCIE2A 1 +-#define TOIE2 0 +- +-#define TIMSK3 _SFR_MEM8(0x71) +-#define ICIE3 5 +-#define OCIE3C 3 +-#define OCIE3B 2 +-#define OCIE3A 1 +-#define TOIE3 0 +- +-#define TIMSK4 _SFR_MEM8(0x72) +-#define ICIE4 5 +-#define OCIE4C 3 +-#define OCIE4B 2 +-#define OCIE4A 1 +-#define TOIE4 0 +- +-#define TIMSK5 _SFR_MEM8(0x73) +-#define ICIE5 5 +-#define OCIE5C 3 +-#define OCIE5B 2 +-#define OCIE5A 1 +-#define TOIE5 0 +- +-#define XMCRA _SFR_MEM8(0x74) +-#define SRE 7 +-#define SRL2 6 +-#define SRL1 5 +-#define SRL0 4 +-#define SRW11 3 +-#define SRW10 2 +-#define SRW01 1 +-#define SRW00 0 +- +-#define XMCRB _SFR_MEM8(0x75) +-#define XMBK 7 +-#define XMM2 2 +-#define XMM1 1 +-#define XMM0 0 +- +-/* Reserved [0x76..0x77] */ +- +-/* Combine ADCL and ADCH */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +-#define ADCL _SFR_MEM8(0x78) +-#define ADCH _SFR_MEM8(0x79) +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADEN 7 +-#define ADSC 6 +-#define ADATE 5 +-#define ADIF 4 +-#define ADIE 3 +-#define ADPS2 2 +-#define ADPS1 1 +-#define ADPS0 0 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ACME 6 +-#if defined(__ATmegaxx0__) +-# define MUX5 3 +-#endif /* __ATmegaxx0__ */ +-#define ADTS2 2 +-#define ADTS1 1 +-#define ADTS0 0 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define REFS1 7 +-#define REFS0 6 +-#define ADLAR 5 +-#define MUX4 4 +-#define MUX3 3 +-#define MUX2 2 +-#define MUX1 1 +-#define MUX0 0 +- +-#define DIDR2 _SFR_MEM8(0x7D) +-#define ADC15D 7 +-#define ADC14D 6 +-#define ADC13D 5 +-#define ADC12D 4 +-#define ADC11D 3 +-#define ADC10D 2 +-#define ADC9D 1 +-#define ADC8D 0 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC7D 7 +-#define ADC6D 6 +-#define ADC5D 5 +-#define ADC4D 4 +-#define ADC3D 3 +-#define ADC2D 2 +-#define ADC1D 1 +-#define ADC0D 0 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN1D 1 +-#define AIN0D 0 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define COM1C1 3 +-#define COM1C0 2 +-#define WGM11 1 +-#define WGM10 0 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define ICNC1 7 +-#define ICES1 6 +-#define WGM13 4 +-#define WGM12 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1A 7 +-#define FOC1B 6 +-#define FOC1C 5 +- +-/* Reserved [0x83] */ +- +-/* Combine TCNT1L and TCNT1H */ +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1H _SFR_MEM8(0x85) +- +-/* Combine ICR1L and ICR1H */ +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1H _SFR_MEM8(0x87) +- +-/* Combine OCR1AL and OCR1AH */ +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AH _SFR_MEM8(0x89) +- +-/* Combine OCR1BL and OCR1BH */ +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BH _SFR_MEM8(0x8B) +- +-/* Combine OCR1CL and OCR1CH */ +-#define OCR1C _SFR_MEM16(0x8C) +- +-#define OCR1CL _SFR_MEM8(0x8C) +-#define OCR1CH _SFR_MEM8(0x8D) +- +-/* Reserved [0x8E..0x8F] */ +- +-#define TCCR3A _SFR_MEM8(0x90) +-#define COM3A1 7 +-#define COM3A0 6 +-#define COM3B1 5 +-#define COM3B0 4 +-#define COM3C1 3 +-#define COM3C0 2 +-#define WGM31 1 +-#define WGM30 0 +- +-#define TCCR3B _SFR_MEM8(0x91) +-#define ICNC3 7 +-#define ICES3 6 +-#define WGM33 4 +-#define WGM32 3 +-#define CS32 2 +-#define CS31 1 +-#define CS30 0 +- +-#define TCCR3C _SFR_MEM8(0x92) +-#define FOC3A 7 +-#define FOC3B 6 +-#define FOC3C 5 +- +-/* Reserved [0x93] */ +- +-/* Combine TCNT3L and TCNT3H */ +-#define TCNT3 _SFR_MEM16(0x94) +- +-#define TCNT3L _SFR_MEM8(0x94) +-#define TCNT3H _SFR_MEM8(0x95) +- +-/* Combine ICR3L and ICR3H */ +-#define ICR3 _SFR_MEM16(0x96) +- +-#define ICR3L _SFR_MEM8(0x96) +-#define ICR3H _SFR_MEM8(0x97) +- +-/* Combine OCR3AL and OCR3AH */ +-#define OCR3A _SFR_MEM16(0x98) +- +-#define OCR3AL _SFR_MEM8(0x98) +-#define OCR3AH _SFR_MEM8(0x99) +- +-/* Combine OCR3BL and OCR3BH */ +-#define OCR3B _SFR_MEM16(0x9A) +- +-#define OCR3BL _SFR_MEM8(0x9A) +-#define OCR3BH _SFR_MEM8(0x9B) +- +-/* Combine OCR3CL and OCR3CH */ +-#define OCR3C _SFR_MEM16(0x9C) +- +-#define OCR3CL _SFR_MEM8(0x9C) +-#define OCR3CH _SFR_MEM8(0x9D) +- +-/* Reserved [0x9E..0x9F] */ +- +-#define TCCR4A _SFR_MEM8(0xA0) +-#define COM4A1 7 +-#define COM4A0 6 +-#define COM4B1 5 +-#define COM4B0 4 +-#define COM4C1 3 +-#define COM4C0 2 +-#define WGM41 1 +-#define WGM40 0 +- +-#define TCCR4B _SFR_MEM8(0xA1) +-#define ICNC4 7 +-#define ICES4 6 +-#define WGM43 4 +-#define WGM42 3 +-#define CS42 2 +-#define CS41 1 +-#define CS40 0 +- +-#define TCCR4C _SFR_MEM8(0xA2) +-#define FOC4A 7 +-#define FOC4B 6 +-#define FOC4C 5 +- +-/* Reserved [0xA3] */ +- +-/* Combine TCNT4L and TCNT4H */ +-#define TCNT4 _SFR_MEM16(0xA4) +- +-#define TCNT4L _SFR_MEM8(0xA4) +-#define TCNT4H _SFR_MEM8(0xA5) +- +-/* Combine ICR4L and ICR4H */ +-#define ICR4 _SFR_MEM16(0xA6) +- +-#define ICR4L _SFR_MEM8(0xA6) +-#define ICR4H _SFR_MEM8(0xA7) +- +-/* Combine OCR4AL and OCR4AH */ +-#define OCR4A _SFR_MEM16(0xA8) +- +-#define OCR4AL _SFR_MEM8(0xA8) +-#define OCR4AH _SFR_MEM8(0xA9) +- +-/* Combine OCR4BL and OCR4BH */ +-#define OCR4B _SFR_MEM16(0xAA) +- +-#define OCR4BL _SFR_MEM8(0xAA) +-#define OCR4BH _SFR_MEM8(0xAB) +- +-/* Combine OCR4CL and OCR4CH */ +-#define OCR4C _SFR_MEM16(0xAC) +- +-#define OCR4CL _SFR_MEM8(0xAC) +-#define OCR4CH _SFR_MEM8(0xAD) +- +-/* Reserved [0xAE..0xAF] */ +- +-#define TCCR2A _SFR_MEM8(0xB0) +-#define COM2A1 7 +-#define COM2A0 6 +-#define COM2B1 5 +-#define COM2B0 4 +-#define WGM21 1 +-#define WGM20 0 +- +-#define TCCR2B _SFR_MEM8(0xB1) +-#define FOC2A 7 +-#define FOC2B 6 +-#define WGM22 3 +-#define CS22 2 +-#define CS21 1 +-#define CS20 0 +- +-#define TCNT2 _SFR_MEM8(0xB2) +- +-#define OCR2A _SFR_MEM8(0xB3) +- +-#define OCR2B _SFR_MEM8(0xB4) +- +-/* Reserved [0xB5] */ +- +-#define ASSR _SFR_MEM8(0xB6) +-#define EXCLK 6 +-#define AS2 5 +-#define TCN2UB 4 +-#define OCR2AUB 3 +-#define OCR2BUB 2 +-#define TCR2AUB 1 +-#define TCR2BUB 0 +- +-/* Reserved [0xB7] */ +- +-#define TWBR _SFR_MEM8(0xB8) +- +-#define TWSR _SFR_MEM8(0xB9) +-#define TWS7 7 +-#define TWS6 6 +-#define TWS5 5 +-#define TWS4 4 +-#define TWS3 3 +-#define TWPS1 1 +-#define TWPS0 0 +- +-#define TWAR _SFR_MEM8(0xBA) +-#define TWA6 7 +-#define TWA5 6 +-#define TWA4 5 +-#define TWA3 4 +-#define TWA2 3 +-#define TWA1 2 +-#define TWA0 1 +-#define TWGCE 0 +- +-#define TWDR _SFR_MEM8(0xBB) +- +-#define TWCR _SFR_MEM8(0xBC) +-#define TWINT 7 +-#define TWEA 6 +-#define TWSTA 5 +-#define TWSTO 4 +-#define TWWC 3 +-#define TWEN 2 +-#define TWIE 0 +- +-#define TWAMR _SFR_MEM8(0xBD) +-#define TWAM6 7 +-#define TWAM5 6 +-#define TWAM4 5 +-#define TWAM3 4 +-#define TWAM2 3 +-#define TWAM1 2 +-#define TWAM0 1 +- +-/* Reserved [0xBE..0xBF] */ +- +-#define UCSR0A _SFR_MEM8(0xC0) +-#define RXC0 7 +-#define TXC0 6 +-#define UDRE0 5 +-#define FE0 4 +-#define DOR0 3 +-#define UPE0 2 +-#define U2X0 1 +-#define MPCM0 0 +- +-#define UCSR0B _SFR_MEM8(0XC1) +-#define RXCIE0 7 +-#define TXCIE0 6 +-#define UDRIE0 5 +-#define RXEN0 4 +-#define TXEN0 3 +-#define UCSZ02 2 +-#define RXB80 1 +-#define TXB80 0 +- +-#define UCSR0C _SFR_MEM8(0xC2) +-#define UMSEL01 7 +-#define UMSEL00 6 +-#define UPM01 5 +-#define UPM00 4 +-#define USBS0 3 +-#define UCSZ01 2 +-#define UCSZ00 1 +-#define UCPOL0 0 +- +-/* Reserved [0xC3] */ +- +-/* Combine UBRR0L and UBRR0H */ +-#define UBRR0 _SFR_MEM16(0xC4) +- +-#define UBRR0L _SFR_MEM8(0xC4) +-#define UBRR0H _SFR_MEM8(0xC5) +- +-#define UDR0 _SFR_MEM8(0XC6) +- +-/* Reserved [0xC7] */ +- +-#define UCSR1A _SFR_MEM8(0xC8) +-#define RXC1 7 +-#define TXC1 6 +-#define UDRE1 5 +-#define FE1 4 +-#define DOR1 3 +-#define UPE1 2 +-#define U2X1 1 +-#define MPCM1 0 +- +-#define UCSR1B _SFR_MEM8(0XC9) +-#define RXCIE1 7 +-#define TXCIE1 6 +-#define UDRIE1 5 +-#define RXEN1 4 +-#define TXEN1 3 +-#define UCSZ12 2 +-#define RXB81 1 +-#define TXB81 0 +- +-#define UCSR1C _SFR_MEM8(0xCA) +-#define UMSEL11 7 +-#define UMSEL10 6 +-#define UPM11 5 +-#define UPM10 4 +-#define USBS1 3 +-#define UCSZ11 2 +-#define UCSZ10 1 +-#define UCPOL1 0 +- +-/* Reserved [0xCB] */ +- +-/* Combine UBRR1L and UBRR1H */ +-#define UBRR1 _SFR_MEM16(0xCC) +- +-#define UBRR1L _SFR_MEM8(0xCC) +-#define UBRR1H _SFR_MEM8(0xCD) +- +-#define UDR1 _SFR_MEM8(0XCE) +- +-/* Reserved [0xCF] */ +- +-#if defined(__ATmegaxx0__) +- +-# define UCSR2A _SFR_MEM8(0xD0) +-# define RXC2 7 +-# define TXC2 6 +-# define UDRE2 5 +-# define FE2 4 +-# define DOR2 3 +-# define UPE2 2 +-# define U2X2 1 +-# define MPCM2 0 +- +-# define UCSR2B _SFR_MEM8(0XD1) +-# define RXCIE2 7 +-# define TXCIE2 6 +-# define UDRIE2 5 +-# define RXEN2 4 +-# define TXEN2 3 +-# define UCSZ22 2 +-# define RXB82 1 +-# define TXB82 0 +- +-# define UCSR2C _SFR_MEM8(0xD2) +-# define UMSEL21 7 +-# define UMSEL20 6 +-# define UPM21 5 +-# define UPM20 4 +-# define USBS2 3 +-# define UCSZ21 2 +-# define UCSZ20 1 +-# define UCPOL2 0 +- +-/* Reserved [0xD3] */ +- +-/* Combine UBRR2L and UBRR2H */ +-# define UBRR2 _SFR_MEM16(0xD4) +- +-# define UBRR2L _SFR_MEM8(0xD4) +-# define UBRR2H _SFR_MEM8(0xD5) +- +-# define UDR2 _SFR_MEM8(0XD6) +- +-#endif /* __ATmegaxx0__ */ +- +-/* Reserved [0xD7..0xFF] */ +- +-#if defined(__ATmegaxx0__) +- +-# define PINH _SFR_MEM8(0x100) +-# define PINH7 7 +-# define PINH6 6 +-# define PINH5 5 +-# define PINH4 4 +-# define PINH3 3 +-# define PINH2 2 +-# define PINH1 1 +-# define PINH0 0 +- +-# define DDRH _SFR_MEM8(0x101) +-# define DDH7 7 +-# define DDH6 6 +-# define DDH5 5 +-# define DDH4 4 +-# define DDH3 3 +-# define DDH2 2 +-# define DDH1 1 +-# define DDH0 0 +- +-# define PORTH _SFR_MEM8(0x102) +-# define PH7 7 +-# define PH6 6 +-# define PH5 5 +-# define PH4 4 +-# define PH3 3 +-# define PH2 2 +-# define PH1 1 +-# define PH0 0 +- +-# define PINJ _SFR_MEM8(0x103) +-# define PINJ7 7 +-# define PINJ6 6 +-# define PINJ5 5 +-# define PINJ4 4 +-# define PINJ3 3 +-# define PINJ2 2 +-# define PINJ1 1 +-# define PINJ0 0 +- +-# define DDRJ _SFR_MEM8(0x104) +-# define DDJ7 7 +-# define DDJ6 6 +-# define DDJ5 5 +-# define DDJ4 4 +-# define DDJ3 3 +-# define DDJ2 2 +-# define DDJ1 1 +-# define DDJ0 0 +- +-# define PORTJ _SFR_MEM8(0x105) +-# define PJ7 7 +-# define PJ6 6 +-# define PJ5 5 +-# define PJ4 4 +-# define PJ3 3 +-# define PJ2 2 +-# define PJ1 1 +-# define PJ0 0 +- +-# define PINK _SFR_MEM8(0x106) +-# define PINK7 7 +-# define PINK6 6 +-# define PINK5 5 +-# define PINK4 4 +-# define PINK3 3 +-# define PINK2 2 +-# define PINK1 1 +-# define PINK0 0 +- +-# define DDRK _SFR_MEM8(0x107) +-# define DDK7 7 +-# define DDK6 6 +-# define DDK5 5 +-# define DDK4 4 +-# define DDK3 3 +-# define DDK2 2 +-# define DDK1 1 +-# define DDK0 0 +- +-# define PORTK _SFR_MEM8(0x108) +-# define PK7 7 +-# define PK6 6 +-# define PK5 5 +-# define PK4 4 +-# define PK3 3 +-# define PK2 2 +-# define PK1 1 +-# define PK0 0 +- +-# define PINL _SFR_MEM8(0x109) +-# define PINL7 7 +-# define PINL6 6 +-# define PINL5 5 +-# define PINL4 4 +-# define PINL3 3 +-# define PINL2 2 +-# define PINL1 1 +-# define PINL0 0 +- +-# define DDRL _SFR_MEM8(0x10A) +-# define DDL7 7 +-# define DDL6 6 +-# define DDL5 5 +-# define DDL4 4 +-# define DDL3 3 +-# define DDL2 2 +-# define DDL1 1 +-# define DDL0 0 +- +-# define PORTL _SFR_MEM8(0x10B) +-# define PL7 7 +-# define PL6 6 +-# define PL5 5 +-# define PL4 4 +-# define PL3 3 +-# define PL2 2 +-# define PL1 1 +-# define PL0 0 +- +-#endif /* __ATmegaxx0__ */ +- +-/* Reserved [0x10C..0x11F] */ +- +-#define TCCR5A _SFR_MEM8(0x120) +-#define COM5A1 7 +-#define COM5A0 6 +-#define COM5B1 5 +-#define COM5B0 4 +-#define COM5C1 3 +-#define COM5C0 2 +-#define WGM51 1 +-#define WGM50 0 +- +-#define TCCR5B _SFR_MEM8(0x121) +-#define ICNC5 7 +-#define ICES5 6 +-#define WGM53 4 +-#define WGM52 3 +-#define CS52 2 +-#define CS51 1 +-#define CS50 0 +- +-#define TCCR5C _SFR_MEM8(0x122) +-#define FOC5A 7 +-#define FOC5B 6 +-#define FOC5C 5 +- +-/* Reserved [0x123] */ +- +-/* Combine TCNT5L and TCNT5H */ +-#define TCNT5 _SFR_MEM16(0x124) +- +-#define TCNT5L _SFR_MEM8(0x124) +-#define TCNT5H _SFR_MEM8(0x125) +- +-/* Combine ICR5L and ICR5H */ +-#define ICR5 _SFR_MEM16(0x126) +- +-#define ICR5L _SFR_MEM8(0x126) +-#define ICR5H _SFR_MEM8(0x127) +- +-/* Combine OCR5AL and OCR5AH */ +-#define OCR5A _SFR_MEM16(0x128) +- +-#define OCR5AL _SFR_MEM8(0x128) +-#define OCR5AH _SFR_MEM8(0x129) +- +-/* Combine OCR5BL and OCR5BH */ +-#define OCR5B _SFR_MEM16(0x12A) +- +-#define OCR5BL _SFR_MEM8(0x12A) +-#define OCR5BH _SFR_MEM8(0x12B) +- +-/* Combine OCR5CL and OCR5CH */ +-#define OCR5C _SFR_MEM16(0x12C) +- +-#define OCR5CL _SFR_MEM8(0x12C) +-#define OCR5CH _SFR_MEM8(0x12D) +- +-/* Reserved [0x12E..0x12F] */ +- +-#if defined(__ATmegaxx0__) +- +-# define UCSR3A _SFR_MEM8(0x130) +-# define RXC3 7 +-# define TXC3 6 +-# define UDRE3 5 +-# define FE3 4 +-# define DOR3 3 +-# define UPE3 2 +-# define U2X3 1 +-# define MPCM3 0 +- +-# define UCSR3B _SFR_MEM8(0X131) +-# define RXCIE3 7 +-# define TXCIE3 6 +-# define UDRIE3 5 +-# define RXEN3 4 +-# define TXEN3 3 +-# define UCSZ32 2 +-# define RXB83 1 +-# define TXB83 0 +- +-# define UCSR3C _SFR_MEM8(0x132) +-# define UMSEL31 7 +-# define UMSEL30 6 +-# define UPM31 5 +-# define UPM30 4 +-# define USBS3 3 +-# define UCSZ31 2 +-# define UCSZ30 1 +-# define UCPOL3 0 +- +-/* Reserved [0x133] */ +- +-/* Combine UBRR3L and UBRR3H */ +-# define UBRR3 _SFR_MEM16(0x134) +- +-# define UBRR3L _SFR_MEM8(0x134) +-# define UBRR3H _SFR_MEM8(0x135) +- +-# define UDR3 _SFR_MEM8(0X136) +- +-#endif /* __ATmegaxx0__ */ +- +-/* Reserved [0x137..1FF] */ +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt Request 1 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +-#define SIG_INTERRUPT1 _VECTOR(2) +- +-/* External Interrupt Request 2 */ +-#define INT2_vect_num 3 +-#define INT2_vect _VECTOR(3) +-#define SIG_INTERRUPT2 _VECTOR(3) +- +-/* External Interrupt Request 3 */ +-#define INT3_vect_num 4 +-#define INT3_vect _VECTOR(4) +-#define SIG_INTERRUPT3 _VECTOR(4) +- +-/* External Interrupt Request 4 */ +-#define INT4_vect_num 5 +-#define INT4_vect _VECTOR(5) +-#define SIG_INTERRUPT4 _VECTOR(5) +- +-/* External Interrupt Request 5 */ +-#define INT5_vect_num 6 +-#define INT5_vect _VECTOR(6) +-#define SIG_INTERRUPT5 _VECTOR(6) +- +-/* External Interrupt Request 6 */ +-#define INT6_vect_num 7 +-#define INT6_vect _VECTOR(7) +-#define SIG_INTERRUPT6 _VECTOR(7) +- +-/* External Interrupt Request 7 */ +-#define INT7_vect_num 8 +-#define INT7_vect _VECTOR(8) +-#define SIG_INTERRUPT7 _VECTOR(8) +- +-/* Pin Change Interrupt Request 0 */ +-#define PCINT0_vect_num 9 +-#define PCINT0_vect _VECTOR(9) +-#define SIG_PIN_CHANGE0 _VECTOR(9) +- +-/* Pin Change Interrupt Request 1 */ +-#define PCINT1_vect_num 10 +-#define PCINT1_vect _VECTOR(10) +-#define SIG_PIN_CHANGE1 _VECTOR(10) +- +-#if defined(__ATmegaxx0__) +-/* Pin Change Interrupt Request 2 */ +-#define PCINT2_vect_num 11 +-#define PCINT2_vect _VECTOR(11) +-#define SIG_PIN_CHANGE2 _VECTOR(11) +- +-#endif /* __ATmegaxx0__ */ +- +-/* Watchdog Time-out Interrupt */ +-#define WDT_vect_num 12 +-#define WDT_vect _VECTOR(12) +-#define SIG_WATCHDOG_TIMEOUT _VECTOR(12) +- +-/* Timer/Counter2 Compare Match A */ +-#define TIMER2_COMPA_vect_num 13 +-#define TIMER2_COMPA_vect _VECTOR(13) +-#define SIG_OUTPUT_COMPARE2A _VECTOR(13) +- +-/* Timer/Counter2 Compare Match B */ +-#define TIMER2_COMPB_vect_num 14 +-#define TIMER2_COMPB_vect _VECTOR(14) +-#define SIG_OUTPUT_COMPARE2B _VECTOR(14) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 15 +-#define TIMER2_OVF_vect _VECTOR(15) +-#define SIG_OVERFLOW2 _VECTOR(15) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 16 +-#define TIMER1_CAPT_vect _VECTOR(16) +-#define SIG_INPUT_CAPTURE1 _VECTOR(16) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 17 +-#define TIMER1_COMPA_vect _VECTOR(17) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(17) +- +-/* Timer/Counter1 Compare Match B */ +-#define TIMER1_COMPB_vect_num 18 +-#define TIMER1_COMPB_vect _VECTOR(18) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(18) +- +-/* Timer/Counter1 Compare Match C */ +-#define TIMER1_COMPC_vect_num 19 +-#define TIMER1_COMPC_vect _VECTOR(19) +-#define SIG_OUTPUT_COMPARE1C _VECTOR(19) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 20 +-#define TIMER1_OVF_vect _VECTOR(20) +-#define SIG_OVERFLOW1 _VECTOR(20) +- +-/* Timer/Counter0 Compare Match A */ +-#define TIMER0_COMPA_vect_num 21 +-#define TIMER0_COMPA_vect _VECTOR(21) +-#define SIG_OUTPUT_COMPARE0A _VECTOR(21) +- +-/* Timer/Counter0 Compare Match B */ +-#define TIMER0_COMPB_vect_num 22 +-#define TIMER0_COMPB_vect _VECTOR(22) +-#define SIG_OUTPUT_COMPARE0B _VECTOR(22) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 23 +-#define TIMER0_OVF_vect _VECTOR(23) +-#define SIG_OVERFLOW0 _VECTOR(23) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 24 +-#define SPI_STC_vect _VECTOR(24) +-#define SIG_SPI _VECTOR(24) +- +-/* USART0, Rx Complete */ +-#define USART0_RX_vect_num 25 +-#define USART0_RX_vect _VECTOR(25) +-#define SIG_USART0_RECV _VECTOR(25) +- +-/* USART0 Data register Empty */ +-#define USART0_UDRE_vect_num 26 +-#define USART0_UDRE_vect _VECTOR(26) +-#define SIG_USART0_DATA _VECTOR(26) +- +-/* USART0, Tx Complete */ +-#define USART0_TX_vect_num 27 +-#define USART0_TX_vect _VECTOR(27) +-#define SIG_USART0_TRANS _VECTOR(27) +- +-/* Analog Comparator */ +-#define ANALOG_COMP_vect_num 28 +-#define ANALOG_COMP_vect _VECTOR(28) +-#define SIG_COMPARATOR _VECTOR(28) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 29 +-#define ADC_vect _VECTOR(29) +-#define SIG_ADC _VECTOR(29) +- +-/* EEPROM Ready */ +-#define EE_READY_vect_num 30 +-#define EE_READY_vect _VECTOR(30) +-#define SIG_EEPROM_READY _VECTOR(30) +- +-/* Timer/Counter3 Capture Event */ +-#define TIMER3_CAPT_vect_num 31 +-#define TIMER3_CAPT_vect _VECTOR(31) +-#define SIG_INPUT_CAPTURE3 _VECTOR(31) +- +-/* Timer/Counter3 Compare Match A */ +-#define TIMER3_COMPA_vect_num 32 +-#define TIMER3_COMPA_vect _VECTOR(32) +-#define SIG_OUTPUT_COMPARE3A _VECTOR(32) +- +-/* Timer/Counter3 Compare Match B */ +-#define TIMER3_COMPB_vect_num 33 +-#define TIMER3_COMPB_vect _VECTOR(33) +-#define SIG_OUTPUT_COMPARE3B _VECTOR(33) +- +-/* Timer/Counter3 Compare Match C */ +-#define TIMER3_COMPC_vect_num 34 +-#define TIMER3_COMPC_vect _VECTOR(34) +-#define SIG_OUTPUT_COMPARE3C _VECTOR(34) +- +-/* Timer/Counter3 Overflow */ +-#define TIMER3_OVF_vect_num 35 +-#define TIMER3_OVF_vect _VECTOR(35) +-#define SIG_OVERFLOW3 _VECTOR(35) +- +-/* USART1, Rx Complete */ +-#define USART1_RX_vect_num 36 +-#define USART1_RX_vect _VECTOR(36) +-#define SIG_USART1_RECV _VECTOR(36) +- +-/* USART1 Data register Empty */ +-#define USART1_UDRE_vect_num 37 +-#define USART1_UDRE_vect _VECTOR(37) +-#define SIG_USART1_DATA _VECTOR(37) +- +-/* USART1, Tx Complete */ +-#define USART1_TX_vect_num 38 +-#define USART1_TX_vect _VECTOR(38) +-#define SIG_USART1_TRANS _VECTOR(38) +- +-/* 2-wire Serial Interface */ +-#define TWI_vect_num 39 +-#define TWI_vect _VECTOR(39) +-#define SIG_2WIRE_SERIAL _VECTOR(39) +- +-/* Store Program Memory Read */ +-#define SPM_READY_vect_num 40 +-#define SPM_READY_vect _VECTOR(40) +-#define SIG_SPM_READY _VECTOR(40) +- +-#if defined(__ATmegaxx0__) +-/* Timer/Counter4 Capture Event */ +-#define TIMER4_CAPT_vect_num 41 +-#define TIMER4_CAPT_vect _VECTOR(41) +-#define SIG_INPUT_CAPTURE4 _VECTOR(41) +- +-#endif /* __ATmegaxx0__ */ +- +-/* Timer/Counter4 Compare Match A */ +-#define TIMER4_COMPA_vect_num 42 +-#define TIMER4_COMPA_vect _VECTOR(42) +-#define SIG_OUTPUT_COMPARE4A _VECTOR(42) +- +-/* Timer/Counter4 Compare Match B */ +-#define TIMER4_COMPB_vect_num 43 +-#define TIMER4_COMPB_vect _VECTOR(43) +-#define SIG_OUTPUT_COMPARE4B _VECTOR(43) +- +-/* Timer/Counter4 Compare Match C */ +-#define TIMER4_COMPC_vect_num 44 +-#define TIMER4_COMPC_vect _VECTOR(44) +-#define SIG_OUTPUT_COMPARE4C _VECTOR(44) +- +-/* Timer/Counter4 Overflow */ +-#define TIMER4_OVF_vect_num 45 +-#define TIMER4_OVF_vect _VECTOR(45) +-#define SIG_OVERFLOW4 _VECTOR(45) +- +-#if defined(__ATmegaxx0__) +-/* Timer/Counter5 Capture Event */ +-#define TIMER5_CAPT_vect_num 46 +-#define TIMER5_CAPT_vect _VECTOR(46) +-#define SIG_INPUT_CAPTURE5 _VECTOR(46) +- +-#endif /* __ATmegaxx0__ */ +- +-/* Timer/Counter5 Compare Match A */ +-#define TIMER5_COMPA_vect_num 47 +-#define TIMER5_COMPA_vect _VECTOR(47) +-#define SIG_OUTPUT_COMPARE5A _VECTOR(47) +- +-/* Timer/Counter5 Compare Match B */ +-#define TIMER5_COMPB_vect_num 48 +-#define TIMER5_COMPB_vect _VECTOR(48) +-#define SIG_OUTPUT_COMPARE5B _VECTOR(48) +- +-/* Timer/Counter5 Compare Match C */ +-#define TIMER5_COMPC_vect_num 49 +-#define TIMER5_COMPC_vect _VECTOR(49) +-#define SIG_OUTPUT_COMPARE5C _VECTOR(49) +- +-/* Timer/Counter5 Overflow */ +-#define TIMER5_OVF_vect_num 50 +-#define TIMER5_OVF_vect _VECTOR(50) +-#define SIG_OVERFLOW5 _VECTOR(50) +- +-#if defined(__ATmegaxx1__) +- +-# define _VECTORS_SIZE 204 +- +-#else +- +-/* USART2, Rx Complete */ +-#define USART2_RX_vect_num 51 +-#define USART2_RX_vect _VECTOR(51) +-#define SIG_USART2_RECV _VECTOR(51) +- +-/* USART2 Data register Empty */ +-#define USART2_UDRE_vect_num 52 +-#define USART2_UDRE_vect _VECTOR(52) +-#define SIG_USART2_DATA _VECTOR(52) +- +-/* USART2, Tx Complete */ +-#define USART2_TX_vect_num 53 +-#define USART2_TX_vect _VECTOR(53) +-#define SIG_USART2_TRANS _VECTOR(53) +- +-/* USART3, Rx Complete */ +-#define USART3_RX_vect_num 54 +-#define USART3_RX_vect _VECTOR(54) +-#define SIG_USART3_RECV _VECTOR(54) +- +-/* USART3 Data register Empty */ +-#define USART3_UDRE_vect_num 55 +-#define USART3_UDRE_vect _VECTOR(55) +-#define SIG_USART3_DATA _VECTOR(55) +- +-/* USART3, Tx Complete */ +-#define USART3_TX_vect_num 56 +-#define USART3_TX_vect _VECTOR(56) +-#define SIG_USART3_TRANS _VECTOR(56) +- +-# define _VECTORS_SIZE 228 +- +-#endif /* __ATmegaxx1__ */ +- +-#if defined(__ATmegaxx0__) +-# undef __ATmegaxx0__ +-#endif +- +-#if defined(__ATmegaxx1__) +-# undef __ATmegaxx1__ +-#endif +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_INTERRUPT1 +-#pragma GCC poison SIG_INTERRUPT2 +-#pragma GCC poison SIG_INTERRUPT3 +-#pragma GCC poison SIG_INTERRUPT4 +-#pragma GCC poison SIG_INTERRUPT5 +-#pragma GCC poison SIG_INTERRUPT6 +-#pragma GCC poison SIG_INTERRUPT7 +-#pragma GCC poison SIG_PIN_CHANGE0 +-#pragma GCC poison SIG_PIN_CHANGE1 +-#pragma GCC poison SIG_PIN_CHANGE2 +-#pragma GCC poison SIG_WATCHDOG_TIMEOUT +-#pragma GCC poison SIG_OUTPUT_COMPARE2A +-#pragma GCC poison SIG_OUTPUT_COMPARE2B +-#pragma GCC poison SIG_OVERFLOW2 +-#pragma GCC poison SIG_INPUT_CAPTURE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_OUTPUT_COMPARE1C +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OUTPUT_COMPARE0A +-#pragma GCC poison SIG_OUTPUT_COMPARE0B +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_SPI +-#pragma GCC poison SIG_USART0_RECV +-#pragma GCC poison SIG_USART0_DATA +-#pragma GCC poison SIG_USART0_TRANS +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_ADC +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_INPUT_CAPTURE3 +-#pragma GCC poison SIG_OUTPUT_COMPARE3A +-#pragma GCC poison SIG_OUTPUT_COMPARE3B +-#pragma GCC poison SIG_OUTPUT_COMPARE3C +-#pragma GCC poison SIG_OVERFLOW3 +-#pragma GCC poison SIG_USART1_RECV +-#pragma GCC poison SIG_USART1_DATA +-#pragma GCC poison SIG_USART1_TRANS +-#pragma GCC poison SIG_2WIRE_SERIAL +-#pragma GCC poison SIG_SPM_READY +-#pragma GCC poison SIG_INPUT_CAPTURE4 +-#pragma GCC poison SIG_OUTPUT_COMPARE4A +-#pragma GCC poison SIG_OUTPUT_COMPARE4B +-#pragma GCC poison SIG_OUTPUT_COMPARE4C +-#pragma GCC poison SIG_OVERFLOW4 +-#pragma GCC poison SIG_INPUT_CAPTURE5 +-#pragma GCC poison SIG_OUTPUT_COMPARE5A +-#pragma GCC poison SIG_OUTPUT_COMPARE5B +-#pragma GCC poison SIG_OUTPUT_COMPARE5C +-#pragma GCC poison SIG_OVERFLOW5 +-#pragma GCC poison SIG_USART2_RECV +-#pragma GCC poison SIG_USART2_DATA +-#pragma GCC poison SIG_USART2_TRANS +-#pragma GCC poison SIG_USART3_RECV +-#pragma GCC poison SIG_USART3_DATA +-#pragma GCC poison SIG_USART3_TRANS +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +-#endif /* _AVR_IOMXX0_1_H_ */ ++/* Copyright (c) 2005 Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iomxx0_1.h 2235 2011-03-17 04:13:14Z arcanum $ */ ++ ++/* avr/iomxx0_1.h - definitions for ATmega640, Atmega1280, ATmega1281, ++ ATmega2560 and ATmega2561. */ ++ ++#ifndef _AVR_IOMXX0_1_H_ ++#define _AVR_IOMXX0_1_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iomxx0_1.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#if defined(__AVR_ATmega640__) || defined(__AVR_ATmega1280__) || defined(__AVR_ATmega2560__) ++# define __ATmegaxx0__ ++#elif defined(__AVR_ATmega1281__) || defined(__AVR_ATmega2561__) ++# define __ATmegaxx1__ ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0X00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0X01) ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++#define PORTA _SFR_IO8(0X02) ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++#define PINB _SFR_IO8(0X03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE7 7 ++#define DDE6 6 ++#define DDE5 5 ++#define DDE4 4 ++#define DDE3 3 ++#define DDE2 2 ++#define DDE1 1 ++#define DDE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PE7 7 ++#define PE6 6 ++#define PE5 5 ++#define PE4 4 ++#define PE3 3 ++#define PE2 2 ++#define PE1 1 ++#define PE0 0 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDF7 7 ++#define DDF6 6 ++#define DDF5 5 ++#define DDF4 4 ++#define DDF3 3 ++#define DDF2 2 ++#define DDF1 1 ++#define DDF0 0 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PF7 7 ++#define PF6 6 ++#define PF5 5 ++#define PF4 4 ++#define PF3 3 ++#define PF2 2 ++#define PF1 1 ++#define PF0 0 ++ ++#define PING _SFR_IO8(0x12) ++#define PING5 5 ++#define PING4 4 ++#define PING3 3 ++#define PING2 2 ++#define PING1 1 ++#define PING0 0 ++ ++#define DDRG _SFR_IO8(0x13) ++#define DDG5 5 ++#define DDG4 4 ++#define DDG3 3 ++#define DDG2 2 ++#define DDG1 1 ++#define DDG0 0 ++ ++#define PORTG _SFR_IO8(0x14) ++#define PG5 5 ++#define PG4 4 ++#define PG3 3 ++#define PG2 2 ++#define PG1 1 ++#define PG0 0 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define OCF0B 2 ++#define OCF0A 1 ++#define TOV0 0 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define ICF1 5 ++#define OCF1C 3 ++#define OCF1B 2 ++#define OCF1A 1 ++#define TOV1 0 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define OCF2B 2 ++#define OCF2A 1 ++#define TOV2 0 ++ ++#define TIFR3 _SFR_IO8(0x18) ++#define ICF3 5 ++#define OCF3C 3 ++#define OCF3B 2 ++#define OCF3A 1 ++#define TOV3 0 ++ ++#define TIFR4 _SFR_IO8(0x19) ++#define ICF4 5 ++#define OCF4C 3 ++#define OCF4B 2 ++#define OCF4A 1 ++#define TOV4 0 ++ ++#define TIFR5 _SFR_IO8(0x1A) ++#define ICF5 5 ++#define OCF5C 3 ++#define OCF5B 2 ++#define OCF5A 1 ++#define TOV5 0 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#if defined(__ATmegaxx0__) ++# define PCIF2 2 ++#endif /* __ATmegaxx0__ */ ++#define PCIF1 1 ++#define PCIF0 0 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF7 7 ++#define INTF6 6 ++#define INTF5 5 ++#define INTF4 4 ++#define INTF3 3 ++#define INTF2 2 ++#define INTF1 1 ++#define INTF0 0 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT7 7 ++#define INT6 6 ++#define INT5 5 ++#define INT4 4 ++#define INT3 3 ++#define INT2 2 ++#define INT1 1 ++#define INT0 0 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EEPM1 5 ++#define EEPM0 4 ++#define EERIE 3 ++#define EEMPE 2 ++#define EEPE 1 ++#define EERE 0 ++ ++#define EEDR _SFR_IO8(0X20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0X22) ++ ++/* 6-char sequence denoting where to find the EEPROM registers in memory space. ++ Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM ++ subroutines. ++ First two letters: EECR address. ++ Second two letters: EEDR address. ++ Last two letters: EEAR address. */ ++#define __EEPROM_REG_LOCATIONS__ 1F2021 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define TSM 7 ++#define PSRASY 1 ++#define PSRSYNC 0 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define COM0A1 7 ++#define COM0A0 6 ++#define COM0B1 5 ++#define COM0B0 4 ++#define WGM01 1 ++#define WGM00 0 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define FOC0A 7 ++#define FOC0B 6 ++#define WGM02 3 ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++#define TCNT0 _SFR_IO8(0X26) ++ ++#define OCR0A _SFR_IO8(0X27) ++ ++#define OCR0B _SFR_IO8(0X28) ++ ++/* Reserved [0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPIF 7 ++#define WCOL 6 ++#define SPI2X 0 ++ ++#define SPDR _SFR_IO8(0X2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACD 7 ++#define ACBG 6 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++#define MONDR _SFR_IO8(0x31) ++#define OCDR _SFR_IO8(0x31) ++#define IDRD 7 ++#define OCDR7 7 ++#define OCDR6 6 ++#define OCDR5 5 ++#define OCDR4 4 ++#define OCDR3 3 ++#define OCDR2 2 ++#define OCDR1 1 ++#define OCDR0 0 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SM2 3 ++#define SM1 2 ++#define SM0 1 ++#define SE 0 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define JTRF 4 ++#define WDRF 3 ++#define BORF 2 ++#define EXTRF 1 ++#define PORF 0 ++ ++#define MCUCR _SFR_IO8(0X35) ++#define JTD 7 ++#define PUD 4 ++#define IVSEL 1 ++#define IVCE 0 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMIE 7 ++#define RWWSB 6 ++#define SIGRD 5 ++#define RWWSRE 4 ++#define BLBSET 3 ++#define PGWRT 2 ++#define PGERS 1 ++#define SPMEN 0 ++ ++/* Reserved [0x38..0x3A] */ ++ ++#define RAMPZ _SFR_IO8(0X3B) ++#define RAMPZ0 0 ++ ++#define EIND _SFR_IO8(0X3C) ++#define EIND0 0 ++ ++/* SP [0x3D..0x3E] */ ++/* SREG [0x3F] */ ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDIF 7 ++#define WDIE 6 ++#define WDP3 5 ++#define WDCE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPCE 7 ++#define CLKPS3 3 ++#define CLKPS2 2 ++#define CLKPS1 1 ++#define CLKPS0 0 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRTWI 7 ++#define PRTIM2 6 ++#define PRTIM0 5 ++#define PRTIM1 3 ++#define PRSPI 2 ++#define PRUSART0 1 ++#define PRADC 0 ++ ++#define PRR1 _SFR_MEM8(0x65) ++#define PRTIM5 5 ++#define PRTIM4 4 ++#define PRTIM3 3 ++#define PRUSART3 2 ++#define PRUSART2 1 ++#define PRUSART1 0 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++ ++/* Reserved [0x67] */ ++ ++#define PCICR _SFR_MEM8(0x68) ++#if defined(__ATmegaxx0__) ++# define PCIE2 2 ++#endif /* __ATmegaxx0__ */ ++#define PCIE1 1 ++#define PCIE0 0 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC31 7 ++#define ISC30 6 ++#define ISC21 5 ++#define ISC20 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++#define EICRB _SFR_MEM8(0x6A) ++#define ISC71 7 ++#define ISC70 6 ++#define ISC61 5 ++#define ISC60 4 ++#define ISC51 3 ++#define ISC50 2 ++#define ISC41 1 ++#define ISC40 0 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT7 7 ++#define PCINT6 6 ++#define PCINT5 5 ++#define PCINT4 4 ++#define PCINT3 3 ++#define PCINT2 2 ++#define PCINT1 1 ++#define PCINT0 0 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT15 7 ++#define PCINT14 6 ++#define PCINT13 5 ++#define PCINT12 4 ++#define PCINT11 3 ++#define PCINT10 2 ++#define PCINT9 1 ++#define PCINT8 0 ++ ++#if defined(__ATmegaxx0__) ++# define PCMSK2 _SFR_MEM8(0x6D) ++# define PCINT23 7 ++# define PCINT22 6 ++# define PCINT21 5 ++# define PCINT20 4 ++# define PCINT19 3 ++# define PCINT18 2 ++# define PCINT17 1 ++# define PCINT16 0 ++#endif /* __ATmegaxx0__ */ ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define OCIE0B 2 ++#define OCIE0A 1 ++#define TOIE0 0 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define ICIE1 5 ++#define OCIE1C 3 ++#define OCIE1B 2 ++#define OCIE1A 1 ++#define TOIE1 0 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define OCIE2B 2 ++#define OCIE2A 1 ++#define TOIE2 0 ++ ++#define TIMSK3 _SFR_MEM8(0x71) ++#define ICIE3 5 ++#define OCIE3C 3 ++#define OCIE3B 2 ++#define OCIE3A 1 ++#define TOIE3 0 ++ ++#define TIMSK4 _SFR_MEM8(0x72) ++#define ICIE4 5 ++#define OCIE4C 3 ++#define OCIE4B 2 ++#define OCIE4A 1 ++#define TOIE4 0 ++ ++#define TIMSK5 _SFR_MEM8(0x73) ++#define ICIE5 5 ++#define OCIE5C 3 ++#define OCIE5B 2 ++#define OCIE5A 1 ++#define TOIE5 0 ++ ++#define XMCRA _SFR_MEM8(0x74) ++#define SRE 7 ++#define SRL2 6 ++#define SRL1 5 ++#define SRL0 4 ++#define SRW11 3 ++#define SRW10 2 ++#define SRW01 1 ++#define SRW00 0 ++ ++#define XMCRB _SFR_MEM8(0x75) ++#define XMBK 7 ++#define XMM2 2 ++#define XMM1 1 ++#define XMM0 0 ++ ++/* Reserved [0x76..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADEN 7 ++#define ADSC 6 ++#define ADATE 5 ++#define ADIF 4 ++#define ADIE 3 ++#define ADPS2 2 ++#define ADPS1 1 ++#define ADPS0 0 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ACME 6 ++#if defined(__ATmegaxx0__) ++# define MUX5 3 ++#endif /* __ATmegaxx0__ */ ++#define ADTS2 2 ++#define ADTS1 1 ++#define ADTS0 0 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define REFS1 7 ++#define REFS0 6 ++#define ADLAR 5 ++#define MUX4 4 ++#define MUX3 3 ++#define MUX2 2 ++#define MUX1 1 ++#define MUX0 0 ++ ++#define DIDR2 _SFR_MEM8(0x7D) ++#define ADC15D 7 ++#define ADC14D 6 ++#define ADC13D 5 ++#define ADC12D 4 ++#define ADC11D 3 ++#define ADC10D 2 ++#define ADC9D 1 ++#define ADC8D 0 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC7D 7 ++#define ADC6D 6 ++#define ADC5D 5 ++#define ADC4D 4 ++#define ADC3D 3 ++#define ADC2D 2 ++#define ADC1D 1 ++#define ADC0D 0 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN1D 1 ++#define AIN0D 0 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define COM1C1 3 ++#define COM1C0 2 ++#define WGM11 1 ++#define WGM10 0 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define ICNC1 7 ++#define ICES1 6 ++#define WGM13 4 ++#define WGM12 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1A 7 ++#define FOC1B 6 ++#define FOC1C 5 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Combine OCR1CL and OCR1CH */ ++#define OCR1C _SFR_MEM16(0x8C) ++ ++#define OCR1CL _SFR_MEM8(0x8C) ++#define OCR1CH _SFR_MEM8(0x8D) ++ ++/* Reserved [0x8E..0x8F] */ ++ ++#define TCCR3A _SFR_MEM8(0x90) ++#define COM3A1 7 ++#define COM3A0 6 ++#define COM3B1 5 ++#define COM3B0 4 ++#define COM3C1 3 ++#define COM3C0 2 ++#define WGM31 1 ++#define WGM30 0 ++ ++#define TCCR3B _SFR_MEM8(0x91) ++#define ICNC3 7 ++#define ICES3 6 ++#define WGM33 4 ++#define WGM32 3 ++#define CS32 2 ++#define CS31 1 ++#define CS30 0 ++ ++#define TCCR3C _SFR_MEM8(0x92) ++#define FOC3A 7 ++#define FOC3B 6 ++#define FOC3C 5 ++ ++/* Reserved [0x93] */ ++ ++/* Combine TCNT3L and TCNT3H */ ++#define TCNT3 _SFR_MEM16(0x94) ++ ++#define TCNT3L _SFR_MEM8(0x94) ++#define TCNT3H _SFR_MEM8(0x95) ++ ++/* Combine ICR3L and ICR3H */ ++#define ICR3 _SFR_MEM16(0x96) ++ ++#define ICR3L _SFR_MEM8(0x96) ++#define ICR3H _SFR_MEM8(0x97) ++ ++/* Combine OCR3AL and OCR3AH */ ++#define OCR3A _SFR_MEM16(0x98) ++ ++#define OCR3AL _SFR_MEM8(0x98) ++#define OCR3AH _SFR_MEM8(0x99) ++ ++/* Combine OCR3BL and OCR3BH */ ++#define OCR3B _SFR_MEM16(0x9A) ++ ++#define OCR3BL _SFR_MEM8(0x9A) ++#define OCR3BH _SFR_MEM8(0x9B) ++ ++/* Combine OCR3CL and OCR3CH */ ++#define OCR3C _SFR_MEM16(0x9C) ++ ++#define OCR3CL _SFR_MEM8(0x9C) ++#define OCR3CH _SFR_MEM8(0x9D) ++ ++/* Reserved [0x9E..0x9F] */ ++ ++#define TCCR4A _SFR_MEM8(0xA0) ++#define COM4A1 7 ++#define COM4A0 6 ++#define COM4B1 5 ++#define COM4B0 4 ++#define COM4C1 3 ++#define COM4C0 2 ++#define WGM41 1 ++#define WGM40 0 ++ ++#define TCCR4B _SFR_MEM8(0xA1) ++#define ICNC4 7 ++#define ICES4 6 ++#define WGM43 4 ++#define WGM42 3 ++#define CS42 2 ++#define CS41 1 ++#define CS40 0 ++ ++#define TCCR4C _SFR_MEM8(0xA2) ++#define FOC4A 7 ++#define FOC4B 6 ++#define FOC4C 5 ++ ++/* Reserved [0xA3] */ ++ ++/* Combine TCNT4L and TCNT4H */ ++#define TCNT4 _SFR_MEM16(0xA4) ++ ++#define TCNT4L _SFR_MEM8(0xA4) ++#define TCNT4H _SFR_MEM8(0xA5) ++ ++/* Combine ICR4L and ICR4H */ ++#define ICR4 _SFR_MEM16(0xA6) ++ ++#define ICR4L _SFR_MEM8(0xA6) ++#define ICR4H _SFR_MEM8(0xA7) ++ ++/* Combine OCR4AL and OCR4AH */ ++#define OCR4A _SFR_MEM16(0xA8) ++ ++#define OCR4AL _SFR_MEM8(0xA8) ++#define OCR4AH _SFR_MEM8(0xA9) ++ ++/* Combine OCR4BL and OCR4BH */ ++#define OCR4B _SFR_MEM16(0xAA) ++ ++#define OCR4BL _SFR_MEM8(0xAA) ++#define OCR4BH _SFR_MEM8(0xAB) ++ ++/* Combine OCR4CL and OCR4CH */ ++#define OCR4C _SFR_MEM16(0xAC) ++ ++#define OCR4CL _SFR_MEM8(0xAC) ++#define OCR4CH _SFR_MEM8(0xAD) ++ ++/* Reserved [0xAE..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define COM2A1 7 ++#define COM2A0 6 ++#define COM2B1 5 ++#define COM2B0 4 ++#define WGM21 1 ++#define WGM20 0 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define FOC2A 7 ++#define FOC2B 6 ++#define WGM22 3 ++#define CS22 2 ++#define CS21 1 ++#define CS20 0 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++#define OCR2B _SFR_MEM8(0xB4) ++ ++/* Reserved [0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define EXCLK 6 ++#define AS2 5 ++#define TCN2UB 4 ++#define OCR2AUB 3 ++#define OCR2BUB 2 ++#define TCR2AUB 1 ++#define TCR2BUB 0 ++ ++/* Reserved [0xB7] */ ++ ++#define TWBR _SFR_MEM8(0xB8) ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWS7 7 ++#define TWS6 6 ++#define TWS5 5 ++#define TWS4 4 ++#define TWS3 3 ++#define TWPS1 1 ++#define TWPS0 0 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWA6 7 ++#define TWA5 6 ++#define TWA4 5 ++#define TWA3 4 ++#define TWA2 3 ++#define TWA1 2 ++#define TWA0 1 ++#define TWGCE 0 ++ ++#define TWDR _SFR_MEM8(0xBB) ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWINT 7 ++#define TWEA 6 ++#define TWSTA 5 ++#define TWSTO 4 ++#define TWWC 3 ++#define TWEN 2 ++#define TWIE 0 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM6 7 ++#define TWAM5 6 ++#define TWAM4 5 ++#define TWAM3 4 ++#define TWAM2 3 ++#define TWAM1 2 ++#define TWAM0 1 ++ ++/* Reserved [0xBE..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define RXC0 7 ++#define TXC0 6 ++#define UDRE0 5 ++#define FE0 4 ++#define DOR0 3 ++#define UPE0 2 ++#define U2X0 1 ++#define MPCM0 0 ++ ++#define UCSR0B _SFR_MEM8(0XC1) ++#define RXCIE0 7 ++#define TXCIE0 6 ++#define UDRIE0 5 ++#define RXEN0 4 ++#define TXEN0 3 ++#define UCSZ02 2 ++#define RXB80 1 ++#define TXB80 0 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UMSEL01 7 ++#define UMSEL00 6 ++#define UPM01 5 ++#define UPM00 4 ++#define USBS0 3 ++#define UCSZ01 2 ++#define UCSZ00 1 ++#define UCPOL0 0 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0XC6) ++ ++/* Reserved [0xC7] */ ++ ++#define UCSR1A _SFR_MEM8(0xC8) ++#define RXC1 7 ++#define TXC1 6 ++#define UDRE1 5 ++#define FE1 4 ++#define DOR1 3 ++#define UPE1 2 ++#define U2X1 1 ++#define MPCM1 0 ++ ++#define UCSR1B _SFR_MEM8(0XC9) ++#define RXCIE1 7 ++#define TXCIE1 6 ++#define UDRIE1 5 ++#define RXEN1 4 ++#define TXEN1 3 ++#define UCSZ12 2 ++#define RXB81 1 ++#define TXB81 0 ++ ++#define UCSR1C _SFR_MEM8(0xCA) ++#define UMSEL11 7 ++#define UMSEL10 6 ++#define UPM11 5 ++#define UPM10 4 ++#define USBS1 3 ++#define UCSZ11 2 ++#define UCSZ10 1 ++#define UCPOL1 0 ++ ++/* Reserved [0xCB] */ ++ ++/* Combine UBRR1L and UBRR1H */ ++#define UBRR1 _SFR_MEM16(0xCC) ++ ++#define UBRR1L _SFR_MEM8(0xCC) ++#define UBRR1H _SFR_MEM8(0xCD) ++ ++#define UDR1 _SFR_MEM8(0XCE) ++ ++/* Reserved [0xCF] */ ++ ++#if defined(__ATmegaxx0__) ++ ++# define UCSR2A _SFR_MEM8(0xD0) ++# define RXC2 7 ++# define TXC2 6 ++# define UDRE2 5 ++# define FE2 4 ++# define DOR2 3 ++# define UPE2 2 ++# define U2X2 1 ++# define MPCM2 0 ++ ++# define UCSR2B _SFR_MEM8(0XD1) ++# define RXCIE2 7 ++# define TXCIE2 6 ++# define UDRIE2 5 ++# define RXEN2 4 ++# define TXEN2 3 ++# define UCSZ22 2 ++# define RXB82 1 ++# define TXB82 0 ++ ++# define UCSR2C _SFR_MEM8(0xD2) ++# define UMSEL21 7 ++# define UMSEL20 6 ++# define UPM21 5 ++# define UPM20 4 ++# define USBS2 3 ++# define UCSZ21 2 ++# define UCSZ20 1 ++# define UCPOL2 0 ++ ++/* Reserved [0xD3] */ ++ ++/* Combine UBRR2L and UBRR2H */ ++# define UBRR2 _SFR_MEM16(0xD4) ++ ++# define UBRR2L _SFR_MEM8(0xD4) ++# define UBRR2H _SFR_MEM8(0xD5) ++ ++# define UDR2 _SFR_MEM8(0XD6) ++ ++#endif /* __ATmegaxx0__ */ ++ ++/* Reserved [0xD7..0xFF] */ ++ ++#if defined(__ATmegaxx0__) ++ ++# define PINH _SFR_MEM8(0x100) ++# define PINH7 7 ++# define PINH6 6 ++# define PINH5 5 ++# define PINH4 4 ++# define PINH3 3 ++# define PINH2 2 ++# define PINH1 1 ++# define PINH0 0 ++ ++# define DDRH _SFR_MEM8(0x101) ++# define DDH7 7 ++# define DDH6 6 ++# define DDH5 5 ++# define DDH4 4 ++# define DDH3 3 ++# define DDH2 2 ++# define DDH1 1 ++# define DDH0 0 ++ ++# define PORTH _SFR_MEM8(0x102) ++# define PH7 7 ++# define PH6 6 ++# define PH5 5 ++# define PH4 4 ++# define PH3 3 ++# define PH2 2 ++# define PH1 1 ++# define PH0 0 ++ ++# define PINJ _SFR_MEM8(0x103) ++# define PINJ7 7 ++# define PINJ6 6 ++# define PINJ5 5 ++# define PINJ4 4 ++# define PINJ3 3 ++# define PINJ2 2 ++# define PINJ1 1 ++# define PINJ0 0 ++ ++# define DDRJ _SFR_MEM8(0x104) ++# define DDJ7 7 ++# define DDJ6 6 ++# define DDJ5 5 ++# define DDJ4 4 ++# define DDJ3 3 ++# define DDJ2 2 ++# define DDJ1 1 ++# define DDJ0 0 ++ ++# define PORTJ _SFR_MEM8(0x105) ++# define PJ7 7 ++# define PJ6 6 ++# define PJ5 5 ++# define PJ4 4 ++# define PJ3 3 ++# define PJ2 2 ++# define PJ1 1 ++# define PJ0 0 ++ ++# define PINK _SFR_MEM8(0x106) ++# define PINK7 7 ++# define PINK6 6 ++# define PINK5 5 ++# define PINK4 4 ++# define PINK3 3 ++# define PINK2 2 ++# define PINK1 1 ++# define PINK0 0 ++ ++# define DDRK _SFR_MEM8(0x107) ++# define DDK7 7 ++# define DDK6 6 ++# define DDK5 5 ++# define DDK4 4 ++# define DDK3 3 ++# define DDK2 2 ++# define DDK1 1 ++# define DDK0 0 ++ ++# define PORTK _SFR_MEM8(0x108) ++# define PK7 7 ++# define PK6 6 ++# define PK5 5 ++# define PK4 4 ++# define PK3 3 ++# define PK2 2 ++# define PK1 1 ++# define PK0 0 ++ ++# define PINL _SFR_MEM8(0x109) ++# define PINL7 7 ++# define PINL6 6 ++# define PINL5 5 ++# define PINL4 4 ++# define PINL3 3 ++# define PINL2 2 ++# define PINL1 1 ++# define PINL0 0 ++ ++# define DDRL _SFR_MEM8(0x10A) ++# define DDL7 7 ++# define DDL6 6 ++# define DDL5 5 ++# define DDL4 4 ++# define DDL3 3 ++# define DDL2 2 ++# define DDL1 1 ++# define DDL0 0 ++ ++# define PORTL _SFR_MEM8(0x10B) ++# define PL7 7 ++# define PL6 6 ++# define PL5 5 ++# define PL4 4 ++# define PL3 3 ++# define PL2 2 ++# define PL1 1 ++# define PL0 0 ++ ++#endif /* __ATmegaxx0__ */ ++ ++/* Reserved [0x10C..0x11F] */ ++ ++#define TCCR5A _SFR_MEM8(0x120) ++#define COM5A1 7 ++#define COM5A0 6 ++#define COM5B1 5 ++#define COM5B0 4 ++#define COM5C1 3 ++#define COM5C0 2 ++#define WGM51 1 ++#define WGM50 0 ++ ++#define TCCR5B _SFR_MEM8(0x121) ++#define ICNC5 7 ++#define ICES5 6 ++#define WGM53 4 ++#define WGM52 3 ++#define CS52 2 ++#define CS51 1 ++#define CS50 0 ++ ++#define TCCR5C _SFR_MEM8(0x122) ++#define FOC5A 7 ++#define FOC5B 6 ++#define FOC5C 5 ++ ++/* Reserved [0x123] */ ++ ++/* Combine TCNT5L and TCNT5H */ ++#define TCNT5 _SFR_MEM16(0x124) ++ ++#define TCNT5L _SFR_MEM8(0x124) ++#define TCNT5H _SFR_MEM8(0x125) ++ ++/* Combine ICR5L and ICR5H */ ++#define ICR5 _SFR_MEM16(0x126) ++ ++#define ICR5L _SFR_MEM8(0x126) ++#define ICR5H _SFR_MEM8(0x127) ++ ++/* Combine OCR5AL and OCR5AH */ ++#define OCR5A _SFR_MEM16(0x128) ++ ++#define OCR5AL _SFR_MEM8(0x128) ++#define OCR5AH _SFR_MEM8(0x129) ++ ++/* Combine OCR5BL and OCR5BH */ ++#define OCR5B _SFR_MEM16(0x12A) ++ ++#define OCR5BL _SFR_MEM8(0x12A) ++#define OCR5BH _SFR_MEM8(0x12B) ++ ++/* Combine OCR5CL and OCR5CH */ ++#define OCR5C _SFR_MEM16(0x12C) ++ ++#define OCR5CL _SFR_MEM8(0x12C) ++#define OCR5CH _SFR_MEM8(0x12D) ++ ++/* Reserved [0x12E..0x12F] */ ++ ++#if defined(__ATmegaxx0__) ++ ++# define UCSR3A _SFR_MEM8(0x130) ++# define RXC3 7 ++# define TXC3 6 ++# define UDRE3 5 ++# define FE3 4 ++# define DOR3 3 ++# define UPE3 2 ++# define U2X3 1 ++# define MPCM3 0 ++ ++# define UCSR3B _SFR_MEM8(0X131) ++# define RXCIE3 7 ++# define TXCIE3 6 ++# define UDRIE3 5 ++# define RXEN3 4 ++# define TXEN3 3 ++# define UCSZ32 2 ++# define RXB83 1 ++# define TXB83 0 ++ ++# define UCSR3C _SFR_MEM8(0x132) ++# define UMSEL31 7 ++# define UMSEL30 6 ++# define UPM31 5 ++# define UPM30 4 ++# define USBS3 3 ++# define UCSZ31 2 ++# define UCSZ30 1 ++# define UCPOL3 0 ++ ++/* Reserved [0x133] */ ++ ++/* Combine UBRR3L and UBRR3H */ ++# define UBRR3 _SFR_MEM16(0x134) ++ ++# define UBRR3L _SFR_MEM8(0x134) ++# define UBRR3H _SFR_MEM8(0x135) ++ ++# define UDR3 _SFR_MEM8(0X136) ++ ++#endif /* __ATmegaxx0__ */ ++ ++/* Reserved [0x137..1FF] */ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++#define SIG_INTERRUPT1 _VECTOR(2) ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect_num 3 ++#define INT2_vect _VECTOR(3) ++#define SIG_INTERRUPT2 _VECTOR(3) ++ ++/* External Interrupt Request 3 */ ++#define INT3_vect_num 4 ++#define INT3_vect _VECTOR(4) ++#define SIG_INTERRUPT3 _VECTOR(4) ++ ++/* External Interrupt Request 4 */ ++#define INT4_vect_num 5 ++#define INT4_vect _VECTOR(5) ++#define SIG_INTERRUPT4 _VECTOR(5) ++ ++/* External Interrupt Request 5 */ ++#define INT5_vect_num 6 ++#define INT5_vect _VECTOR(6) ++#define SIG_INTERRUPT5 _VECTOR(6) ++ ++/* External Interrupt Request 6 */ ++#define INT6_vect_num 7 ++#define INT6_vect _VECTOR(7) ++#define SIG_INTERRUPT6 _VECTOR(7) ++ ++/* External Interrupt Request 7 */ ++#define INT7_vect_num 8 ++#define INT7_vect _VECTOR(8) ++#define SIG_INTERRUPT7 _VECTOR(8) ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect_num 9 ++#define PCINT0_vect _VECTOR(9) ++#define SIG_PIN_CHANGE0 _VECTOR(9) ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect_num 10 ++#define PCINT1_vect _VECTOR(10) ++#define SIG_PIN_CHANGE1 _VECTOR(10) ++ ++#if defined(__ATmegaxx0__) ++/* Pin Change Interrupt Request 2 */ ++#define PCINT2_vect_num 11 ++#define PCINT2_vect _VECTOR(11) ++#define SIG_PIN_CHANGE2 _VECTOR(11) ++ ++#endif /* __ATmegaxx0__ */ ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect_num 12 ++#define WDT_vect _VECTOR(12) ++#define SIG_WATCHDOG_TIMEOUT _VECTOR(12) ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPA_vect_num 13 ++#define TIMER2_COMPA_vect _VECTOR(13) ++#define SIG_OUTPUT_COMPARE2A _VECTOR(13) ++ ++/* Timer/Counter2 Compare Match B */ ++#define TIMER2_COMPB_vect_num 14 ++#define TIMER2_COMPB_vect _VECTOR(14) ++#define SIG_OUTPUT_COMPARE2B _VECTOR(14) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 15 ++#define TIMER2_OVF_vect _VECTOR(15) ++#define SIG_OVERFLOW2 _VECTOR(15) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 16 ++#define TIMER1_CAPT_vect _VECTOR(16) ++#define SIG_INPUT_CAPTURE1 _VECTOR(16) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 17 ++#define TIMER1_COMPA_vect _VECTOR(17) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(17) ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect_num 18 ++#define TIMER1_COMPB_vect _VECTOR(18) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(18) ++ ++/* Timer/Counter1 Compare Match C */ ++#define TIMER1_COMPC_vect_num 19 ++#define TIMER1_COMPC_vect _VECTOR(19) ++#define SIG_OUTPUT_COMPARE1C _VECTOR(19) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 20 ++#define TIMER1_OVF_vect _VECTOR(20) ++#define SIG_OVERFLOW1 _VECTOR(20) ++ ++/* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPA_vect_num 21 ++#define TIMER0_COMPA_vect _VECTOR(21) ++#define SIG_OUTPUT_COMPARE0A _VECTOR(21) ++ ++/* Timer/Counter0 Compare Match B */ ++#define TIMER0_COMPB_vect_num 22 ++#define TIMER0_COMPB_vect _VECTOR(22) ++#define SIG_OUTPUT_COMPARE0B _VECTOR(22) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 23 ++#define TIMER0_OVF_vect _VECTOR(23) ++#define SIG_OVERFLOW0 _VECTOR(23) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 24 ++#define SPI_STC_vect _VECTOR(24) ++#define SIG_SPI _VECTOR(24) ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect_num 25 ++#define USART0_RX_vect _VECTOR(25) ++#define SIG_USART0_RECV _VECTOR(25) ++ ++/* USART0 Data register Empty */ ++#define USART0_UDRE_vect_num 26 ++#define USART0_UDRE_vect _VECTOR(26) ++#define SIG_USART0_DATA _VECTOR(26) ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect_num 27 ++#define USART0_TX_vect _VECTOR(27) ++#define SIG_USART0_TRANS _VECTOR(27) ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect_num 28 ++#define ANALOG_COMP_vect _VECTOR(28) ++#define SIG_COMPARATOR _VECTOR(28) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 29 ++#define ADC_vect _VECTOR(29) ++#define SIG_ADC _VECTOR(29) ++ ++/* EEPROM Ready */ ++#define EE_READY_vect_num 30 ++#define EE_READY_vect _VECTOR(30) ++#define SIG_EEPROM_READY _VECTOR(30) ++ ++/* Timer/Counter3 Capture Event */ ++#define TIMER3_CAPT_vect_num 31 ++#define TIMER3_CAPT_vect _VECTOR(31) ++#define SIG_INPUT_CAPTURE3 _VECTOR(31) ++ ++/* Timer/Counter3 Compare Match A */ ++#define TIMER3_COMPA_vect_num 32 ++#define TIMER3_COMPA_vect _VECTOR(32) ++#define SIG_OUTPUT_COMPARE3A _VECTOR(32) ++ ++/* Timer/Counter3 Compare Match B */ ++#define TIMER3_COMPB_vect_num 33 ++#define TIMER3_COMPB_vect _VECTOR(33) ++#define SIG_OUTPUT_COMPARE3B _VECTOR(33) ++ ++/* Timer/Counter3 Compare Match C */ ++#define TIMER3_COMPC_vect_num 34 ++#define TIMER3_COMPC_vect _VECTOR(34) ++#define SIG_OUTPUT_COMPARE3C _VECTOR(34) ++ ++/* Timer/Counter3 Overflow */ ++#define TIMER3_OVF_vect_num 35 ++#define TIMER3_OVF_vect _VECTOR(35) ++#define SIG_OVERFLOW3 _VECTOR(35) ++ ++/* USART1, Rx Complete */ ++#define USART1_RX_vect_num 36 ++#define USART1_RX_vect _VECTOR(36) ++#define SIG_USART1_RECV _VECTOR(36) ++ ++/* USART1 Data register Empty */ ++#define USART1_UDRE_vect_num 37 ++#define USART1_UDRE_vect _VECTOR(37) ++#define SIG_USART1_DATA _VECTOR(37) ++ ++/* USART1, Tx Complete */ ++#define USART1_TX_vect_num 38 ++#define USART1_TX_vect _VECTOR(38) ++#define SIG_USART1_TRANS _VECTOR(38) ++ ++/* 2-wire Serial Interface */ ++#define TWI_vect_num 39 ++#define TWI_vect _VECTOR(39) ++#define SIG_2WIRE_SERIAL _VECTOR(39) ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect_num 40 ++#define SPM_READY_vect _VECTOR(40) ++#define SIG_SPM_READY _VECTOR(40) ++ ++#if defined(__ATmegaxx0__) ++/* Timer/Counter4 Capture Event */ ++#define TIMER4_CAPT_vect_num 41 ++#define TIMER4_CAPT_vect _VECTOR(41) ++#define SIG_INPUT_CAPTURE4 _VECTOR(41) ++ ++#endif /* __ATmegaxx0__ */ ++ ++/* Timer/Counter4 Compare Match A */ ++#define TIMER4_COMPA_vect_num 42 ++#define TIMER4_COMPA_vect _VECTOR(42) ++#define SIG_OUTPUT_COMPARE4A _VECTOR(42) ++ ++/* Timer/Counter4 Compare Match B */ ++#define TIMER4_COMPB_vect_num 43 ++#define TIMER4_COMPB_vect _VECTOR(43) ++#define SIG_OUTPUT_COMPARE4B _VECTOR(43) ++ ++/* Timer/Counter4 Compare Match C */ ++#define TIMER4_COMPC_vect_num 44 ++#define TIMER4_COMPC_vect _VECTOR(44) ++#define SIG_OUTPUT_COMPARE4C _VECTOR(44) ++ ++/* Timer/Counter4 Overflow */ ++#define TIMER4_OVF_vect_num 45 ++#define TIMER4_OVF_vect _VECTOR(45) ++#define SIG_OVERFLOW4 _VECTOR(45) ++ ++#if defined(__ATmegaxx0__) ++/* Timer/Counter5 Capture Event */ ++#define TIMER5_CAPT_vect_num 46 ++#define TIMER5_CAPT_vect _VECTOR(46) ++#define SIG_INPUT_CAPTURE5 _VECTOR(46) ++ ++#endif /* __ATmegaxx0__ */ ++ ++/* Timer/Counter5 Compare Match A */ ++#define TIMER5_COMPA_vect_num 47 ++#define TIMER5_COMPA_vect _VECTOR(47) ++#define SIG_OUTPUT_COMPARE5A _VECTOR(47) ++ ++/* Timer/Counter5 Compare Match B */ ++#define TIMER5_COMPB_vect_num 48 ++#define TIMER5_COMPB_vect _VECTOR(48) ++#define SIG_OUTPUT_COMPARE5B _VECTOR(48) ++ ++/* Timer/Counter5 Compare Match C */ ++#define TIMER5_COMPC_vect_num 49 ++#define TIMER5_COMPC_vect _VECTOR(49) ++#define SIG_OUTPUT_COMPARE5C _VECTOR(49) ++ ++/* Timer/Counter5 Overflow */ ++#define TIMER5_OVF_vect_num 50 ++#define TIMER5_OVF_vect _VECTOR(50) ++#define SIG_OVERFLOW5 _VECTOR(50) ++ ++#if defined(__ATmegaxx1__) ++ ++# define _VECTORS_SIZE 204 ++ ++#else ++ ++/* USART2, Rx Complete */ ++#define USART2_RX_vect_num 51 ++#define USART2_RX_vect _VECTOR(51) ++#define SIG_USART2_RECV _VECTOR(51) ++ ++/* USART2 Data register Empty */ ++#define USART2_UDRE_vect_num 52 ++#define USART2_UDRE_vect _VECTOR(52) ++#define SIG_USART2_DATA _VECTOR(52) ++ ++/* USART2, Tx Complete */ ++#define USART2_TX_vect_num 53 ++#define USART2_TX_vect _VECTOR(53) ++#define SIG_USART2_TRANS _VECTOR(53) ++ ++/* USART3, Rx Complete */ ++#define USART3_RX_vect_num 54 ++#define USART3_RX_vect _VECTOR(54) ++#define SIG_USART3_RECV _VECTOR(54) ++ ++/* USART3 Data register Empty */ ++#define USART3_UDRE_vect_num 55 ++#define USART3_UDRE_vect _VECTOR(55) ++#define SIG_USART3_DATA _VECTOR(55) ++ ++/* USART3, Tx Complete */ ++#define USART3_TX_vect_num 56 ++#define USART3_TX_vect _VECTOR(56) ++#define SIG_USART3_TRANS _VECTOR(56) ++ ++# define _VECTORS_SIZE 228 ++ ++#endif /* __ATmegaxx1__ */ ++ ++#if defined(__ATmegaxx0__) ++# undef __ATmegaxx0__ ++#endif ++ ++#if defined(__ATmegaxx1__) ++# undef __ATmegaxx1__ ++#endif ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_INTERRUPT1 ++#pragma GCC poison SIG_INTERRUPT2 ++#pragma GCC poison SIG_INTERRUPT3 ++#pragma GCC poison SIG_INTERRUPT4 ++#pragma GCC poison SIG_INTERRUPT5 ++#pragma GCC poison SIG_INTERRUPT6 ++#pragma GCC poison SIG_INTERRUPT7 ++#pragma GCC poison SIG_PIN_CHANGE0 ++#pragma GCC poison SIG_PIN_CHANGE1 ++#pragma GCC poison SIG_PIN_CHANGE2 ++#pragma GCC poison SIG_WATCHDOG_TIMEOUT ++#pragma GCC poison SIG_OUTPUT_COMPARE2A ++#pragma GCC poison SIG_OUTPUT_COMPARE2B ++#pragma GCC poison SIG_OVERFLOW2 ++#pragma GCC poison SIG_INPUT_CAPTURE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_OUTPUT_COMPARE1C ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OUTPUT_COMPARE0A ++#pragma GCC poison SIG_OUTPUT_COMPARE0B ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_SPI ++#pragma GCC poison SIG_USART0_RECV ++#pragma GCC poison SIG_USART0_DATA ++#pragma GCC poison SIG_USART0_TRANS ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_ADC ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_INPUT_CAPTURE3 ++#pragma GCC poison SIG_OUTPUT_COMPARE3A ++#pragma GCC poison SIG_OUTPUT_COMPARE3B ++#pragma GCC poison SIG_OUTPUT_COMPARE3C ++#pragma GCC poison SIG_OVERFLOW3 ++#pragma GCC poison SIG_USART1_RECV ++#pragma GCC poison SIG_USART1_DATA ++#pragma GCC poison SIG_USART1_TRANS ++#pragma GCC poison SIG_2WIRE_SERIAL ++#pragma GCC poison SIG_SPM_READY ++#pragma GCC poison SIG_INPUT_CAPTURE4 ++#pragma GCC poison SIG_OUTPUT_COMPARE4A ++#pragma GCC poison SIG_OUTPUT_COMPARE4B ++#pragma GCC poison SIG_OUTPUT_COMPARE4C ++#pragma GCC poison SIG_OVERFLOW4 ++#pragma GCC poison SIG_INPUT_CAPTURE5 ++#pragma GCC poison SIG_OUTPUT_COMPARE5A ++#pragma GCC poison SIG_OUTPUT_COMPARE5B ++#pragma GCC poison SIG_OUTPUT_COMPARE5C ++#pragma GCC poison SIG_OVERFLOW5 ++#pragma GCC poison SIG_USART2_RECV ++#pragma GCC poison SIG_USART2_DATA ++#pragma GCC poison SIG_USART2_TRANS ++#pragma GCC poison SIG_USART3_RECV ++#pragma GCC poison SIG_USART3_DATA ++#pragma GCC poison SIG_USART3_TRANS ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++#endif /* _AVR_IOMXX0_1_H_ */ +diff --git a/include/avr/iomxx4.h b/include/avr/iomxx4.h +index 9795cb1..9003039 100644 +--- a/include/avr/iomxx4.h ++++ b/include/avr/iomxx4.h +@@ -1,938 +1,938 @@ +-/* Copyright (c) 2005, 2006, 2007 Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* avr/iomXX4.h - definitions for ATmega164P/324P/644P and ATmega644 */ +- +-/* $Id: iomxx4.h 2235 2011-03-17 04:13:14Z arcanum $ */ +- +-#ifndef _AVR_IOMXX4_H_ +-#define _AVR_IOMXX4_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iom164.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* Registers and associated bit numbers */ +- +-#define PINA _SFR_IO8(0X00) +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-#define DDRA _SFR_IO8(0X01) +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-#define PORTA _SFR_IO8(0X02) +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-#define PINB _SFR_IO8(0X03) +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-#define PORTB _SFR_IO8(0x05) +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-#define PORTC _SFR_IO8(0x08) +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* Reserved [0x0C..0x14] */ +- +-#define TIFR0 _SFR_IO8(0x15) +-#define OCF0B 2 +-#define OCF0A 1 +-#define TOV0 0 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define ICF1 5 +-#define OCF1B 2 +-#define OCF1A 1 +-#define TOV1 0 +- +-#define TIFR2 _SFR_IO8(0x17) +-#define OCF2B 2 +-#define OCF2A 1 +-#define TOV2 0 +- +-/* Reserved [0x18..0x1A] */ +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF3 3 +-#define PCIF2 2 +-#define PCIF1 1 +-#define PCIF0 0 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF2 2 +-#define INTF1 1 +-#define INTF0 0 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT2 2 +-#define INT1 1 +-#define INT0 0 +- +-#define GPIOR0 _SFR_IO8(0x1E) +- +-#define EECR _SFR_IO8(0x1F) +-/* EECR - EEPROM Control Register */ +-#define EEPM1 5 +-#define EEPM0 4 +-#define EERIE 3 +-#define EEMPE 2 +-#define EEPE 1 +-#define EERE 0 +- +-#define EEDR _SFR_IO8(0X20) +- +-/* Combine EEARL and EEARH */ +-#define EEAR _SFR_IO16(0x21) +-#define EEARL _SFR_IO8(0x21) +-#define EEARH _SFR_IO8(0X22) +- +-/* 6-char sequence denoting where to find the EEPROM registers in memory space. +- Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM +- subroutines. +- First two letters: EECR address. +- Second two letters: EEDR address. +- Last two letters: EEAR address. */ +-#define __EEPROM_REG_LOCATIONS__ 1F2021 +- +-#define GTCCR _SFR_IO8(0x23) +-#define TSM 7 +-#define PSRASY 1 +-#define PSRSYNC 0 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define COM0A1 7 +-#define COM0A0 6 +-#define COM0B1 5 +-#define COM0B0 4 +-#define WGM01 1 +-#define WGM00 0 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define FOC0A 7 +-#define FOC0B 6 +-#define WGM02 3 +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-#define TCNT0 _SFR_IO8(0X26) +- +-#define OCR0A _SFR_IO8(0X27) +- +-#define OCR0B _SFR_IO8(0X28) +- +-/* Reserved [0x29] */ +- +-#define GPIOR1 _SFR_IO8(0x2A) +- +-#define GPIOR2 _SFR_IO8(0x2B) +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPIF 7 +-#define WCOL 6 +-#define SPI2X 0 +- +-#define SPDR _SFR_IO8(0x2E) +- +-/* Reserved [0x2F] */ +- +-#define ACSR _SFR_IO8(0x30) +-#define ACD 7 +-#define ACBG 6 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +- +-#define MONDR _SFR_IO8(0x31) +-#define OCDR _SFR_IO8(0x31) +-#define IDRD 7 +-#define OCDR7 7 +-#define OCDR6 6 +-#define OCDR5 5 +-#define OCDR4 4 +-#define OCDR3 3 +-#define OCDR2 2 +-#define OCDR1 1 +-#define OCDR0 0 +- +-/* Reserved [0x32] */ +- +-#define SMCR _SFR_IO8(0x33) +-#define SM2 3 +-#define SM1 2 +-#define SM0 1 +-#define SE 0 +- +-#define MCUSR _SFR_IO8(0x34) +-#define JTRF 4 +-#define WDRF 3 +-#define BORF 2 +-#define EXTRF 1 +-#define PORF 0 +- +-#define MCUCR _SFR_IO8(0X35) +-#define JTD 7 +-#if !defined(__AVR_ATmega644__) +-#define BODS 6 +-#define BODSE 5 +-#endif +-#define PUD 4 +-#define IVSEL 1 +-#define IVCE 0 +- +-/* Reserved [0x36] */ +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMIE 7 +-#define RWWSB 6 +-#define SIGRD 5 +-#define RWWSRE 4 +-#define BLBSET 3 +-#define PGWRT 2 +-#define PGERS 1 +-#define SPMEN 0 +- +-/* Reserved [0x38..0x3C] */ +- +-/* SP [0x3D..0x3E] */ +-/* SREG [0x3F] */ +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDIF 7 +-#define WDIE 6 +-#define WDP3 5 +-#define WDCE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPCE 7 +-#define CLKPS3 3 +-#define CLKPS2 2 +-#define CLKPS1 1 +-#define CLKPS0 0 +- +-/* Reserved [0x62..0x63] */ +- +-#define PRR _SFR_MEM8(0x64) /* Datasheets: ATmega164P/324P/644P 8011D–AVR–02/07 +- and ATmega644 2593L–AVR–02/07. */ +-#define PRR0 _SFR_MEM8(0x64) /* AVR Studio 4.13, build 524. */ +-#define PRTWI 7 +-#define PRTIM2 6 +-#define PRTIM0 5 +-#if !defined(__AVR_ATmega644__) +-# define PRUSART1 4 +-#endif +-#define PRTIM1 3 +-#define PRSPI 2 +-#define PRUSART0 1 +-#define PRADC 0 +- +-/* Reserved [0x65] */ +- +-#define OSCCAL _SFR_MEM8(0x66) +- +-/* Reserved [0x67] */ +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE3 3 +-#define PCIE2 2 +-#define PCIE1 1 +-#define PCIE0 0 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC21 5 +-#define ISC20 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-/* Reserved [0x6A] */ +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT7 7 +-#define PCINT6 6 +-#define PCINT5 5 +-#define PCINT4 4 +-#define PCINT3 3 +-#define PCINT2 2 +-#define PCINT1 1 +-#define PCINT0 0 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT15 7 +-#define PCINT14 6 +-#define PCINT13 5 +-#define PCINT12 4 +-#define PCINT11 3 +-#define PCINT10 2 +-#define PCINT9 1 +-#define PCINT8 0 +- +-#define PCMSK2 _SFR_MEM8(0x6D) +-#define PCINT23 7 +-#define PCINT22 6 +-#define PCINT21 5 +-#define PCINT20 4 +-#define PCINT19 3 +-#define PCINT18 2 +-#define PCINT17 1 +-#define PCINT16 0 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define OCIE0B 2 +-#define OCIE0A 1 +-#define TOIE0 0 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define ICIE1 5 +-#define OCIE1B 2 +-#define OCIE1A 1 +-#define TOIE1 0 +- +-#define TIMSK2 _SFR_MEM8(0x70) +-#define OCIE2B 2 +-#define OCIE2A 1 +-#define TOIE2 0 +- +-/* Reserved [0x71..0x72] */ +- +-#define PCMSK3 _SFR_MEM8(0x73) +-#define PCINT31 7 +-#define PCINT30 6 +-#define PCINT29 5 +-#define PCINT28 4 +-#define PCINT27 3 +-#define PCINT26 2 +-#define PCINT25 1 +-#define PCINT24 0 +- +-/* Reserved [0x74..0x77] */ +- +-/* Combine ADCL and ADCH */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +-#define ADCL _SFR_MEM8(0x78) +-#define ADCH _SFR_MEM8(0x79) +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADEN 7 +-#define ADSC 6 +-#define ADATE 5 +-#define ADIF 4 +-#define ADIE 3 +-#define ADPS2 2 +-#define ADPS1 1 +-#define ADPS0 0 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ACME 6 +-#define ADTS2 2 +-#define ADTS1 1 +-#define ADTS0 0 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define REFS1 7 +-#define REFS0 6 +-#define ADLAR 5 +-#define MUX4 4 +-#define MUX3 3 +-#define MUX2 2 +-#define MUX1 1 +-#define MUX0 0 +- +-/* Reserved [0x7D] */ +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC7D 7 +-#define ADC6D 6 +-#define ADC5D 5 +-#define ADC4D 4 +-#define ADC3D 3 +-#define ADC2D 2 +-#define ADC1D 1 +-#define ADC0D 0 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN1D 1 +-#define AIN0D 0 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define WGM11 1 +-#define WGM10 0 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define ICNC1 7 +-#define ICES1 6 +-#define WGM13 4 +-#define WGM12 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1A 7 +-#define FOC1B 6 +- +-/* Reserved [0x83] */ +- +-/* Combine TCNT1L and TCNT1H */ +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1H _SFR_MEM8(0x85) +- +-/* Combine ICR1L and ICR1H */ +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1H _SFR_MEM8(0x87) +- +-/* Combine OCR1AL and OCR1AH */ +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AH _SFR_MEM8(0x89) +- +-/* Combine OCR1BL and OCR1BH */ +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BH _SFR_MEM8(0x8B) +- +-/* Reserved [0x8C..0xAF] */ +- +-#define TCCR2A _SFR_MEM8(0xB0) +-#define COM2A1 7 +-#define COM2A0 6 +-#define COM2B1 5 +-#define COM2B0 4 +-#define WGM21 1 +-#define WGM20 0 +- +-#define TCCR2B _SFR_MEM8(0xB1) +-#define FOC2A 7 +-#define FOC2B 6 +-#define WGM22 3 +-#define CS22 2 +-#define CS21 1 +-#define CS20 0 +- +-#define TCNT2 _SFR_MEM8(0xB2) +- +-#define OCR2A _SFR_MEM8(0xB3) +- +-#define OCR2B _SFR_MEM8(0xB4) +- +-/* Reserved [0xB5] */ +- +-#define ASSR _SFR_MEM8(0xB6) +-#define EXCLK 6 +-#define AS2 5 +-#define TCN2UB 4 +-#define OCR2AUB 3 +-#define OCR2BUB 2 +-#define TCR2AUB 1 +-#define TCR2BUB 0 +- +-/* Reserved [0xB7] */ +- +-#define TWBR _SFR_MEM8(0xB8) +- +-#define TWSR _SFR_MEM8(0xB9) +-#define TWS7 7 +-#define TWS6 6 +-#define TWS5 5 +-#define TWS4 4 +-#define TWS3 3 +-#define TWPS1 1 +-#define TWPS0 0 +- +-#define TWAR _SFR_MEM8(0xBA) +-#define TWA6 7 +-#define TWA5 6 +-#define TWA4 5 +-#define TWA3 4 +-#define TWA2 3 +-#define TWA1 2 +-#define TWA0 1 +-#define TWGCE 0 +- +-#define TWDR _SFR_MEM8(0xBB) +- +-#define TWCR _SFR_MEM8(0xBC) +-#define TWINT 7 +-#define TWEA 6 +-#define TWSTA 5 +-#define TWSTO 4 +-#define TWWC 3 +-#define TWEN 2 +-#define TWIE 0 +- +-#define TWAMR _SFR_MEM8(0xBD) +-#define TWAM6 7 +-#define TWAM5 6 +-#define TWAM4 5 +-#define TWAM3 4 +-#define TWAM2 3 +-#define TWAM1 2 +-#define TWAM0 1 +- +-/* Reserved [0xBE..0xBF] */ +- +-#define UCSR0A _SFR_MEM8(0xC0) +-#define RXC0 7 +-#define TXC0 6 +-#define UDRE0 5 +-#define FE0 4 +-#define DOR0 3 +-#define UPE0 2 +-#define U2X0 1 +-#define MPCM0 0 +- +-#define UCSR0B _SFR_MEM8(0XC1) +-#define RXCIE0 7 +-#define TXCIE0 6 +-#define UDRIE0 5 +-#define RXEN0 4 +-#define TXEN0 3 +-#define UCSZ02 2 +-#define RXB80 1 +-#define TXB80 0 +- +-#define UCSR0C _SFR_MEM8(0xC2) +-#define UMSEL01 7 +-#define UMSEL00 6 +-#define UPM01 5 +-#define UPM00 4 +-#define USBS0 3 +-#define UCSZ01 2 +-#define UCSZ00 1 +-#define UCPHA0 1 +-#define UCPOL0 0 +- +-/* Reserved [0xC3] */ +- +-/* Combine UBRR0L and UBRR0H */ +-#define UBRR0 _SFR_MEM16(0xC4) +- +-#define UBRR0L _SFR_MEM8(0xC4) +-#define UBRR0H _SFR_MEM8(0xC5) +- +-#define UDR0 _SFR_MEM8(0XC6) +- +-#if !defined(__AVR_ATmega644__) +-/* +- * Only ATmega164P/324P/644P have a second USART. +- */ +-/* Reserved [0xC7] */ +- +-#define UCSR1A _SFR_MEM8(0xC8) +-#define RXC1 7 +-#define TXC1 6 +-#define UDRE1 5 +-#define FE1 4 +-#define DOR1 3 +-#define UPE1 2 +-#define U2X1 1 +-#define MPCM1 0 +- +-#define UCSR1B _SFR_MEM8(0XC9) +-#define RXCIE1 7 +-#define TXCIE1 6 +-#define UDRIE1 5 +-#define RXEN1 4 +-#define TXEN1 3 +-#define UCSZ12 2 +-#define RXB81 1 +-#define TXB81 0 +- +-#define UCSR1C _SFR_MEM8(0xCA) +-#define UMSEL11 7 +-#define UMSEL10 6 +-#define UPM11 5 +-#define UPM10 4 +-#define USBS1 3 +-#define UCSZ11 2 +-#define UCSZ10 1 +-#define UCPHA1 1 +-#define UCPOL1 0 +- +-/* Reserved [0xCB] */ +- +-/* Combine UBRR1L and UBRR1H */ +-#define UBRR1 _SFR_MEM16(0xCC) +- +-#define UBRR1L _SFR_MEM8(0xCC) +-#define UBRR1H _SFR_MEM8(0xCD) +- +-#define UDR1 _SFR_MEM8(0XCE) +-#endif /* !defined(__AVR_ATmega644) */ +- +-/* Reserved [0xCF..0xFF] */ +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt Request 1 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +-#define SIG_INTERRUPT1 _VECTOR(2) +- +-/* External Interrupt Request 2 */ +-#define INT2_vect_num 3 +-#define INT2_vect _VECTOR(3) +-#define SIG_INTERRUPT2 _VECTOR(3) +- +-/* Pin Change Interrupt Request 0 */ +-#define PCINT0_vect_num 4 +-#define PCINT0_vect _VECTOR(4) +-#define SIG_PIN_CHANGE0 _VECTOR(4) +- +-/* Pin Change Interrupt Request 1 */ +-#define PCINT1_vect_num 5 +-#define PCINT1_vect _VECTOR(5) +-#define SIG_PIN_CHANGE1 _VECTOR(5) +- +-/* Pin Change Interrupt Request 2 */ +-#define PCINT2_vect_num 6 +-#define PCINT2_vect _VECTOR(6) +-#define SIG_PIN_CHANGE2 _VECTOR(6) +- +-/* Pin Change Interrupt Request 3 */ +-#define PCINT3_vect_num 7 +-#define PCINT3_vect _VECTOR(7) +-#define SIG_PIN_CHANGE3 _VECTOR(7) +- +-/* Watchdog Time-out Interrupt */ +-#define WDT_vect_num 8 +-#define WDT_vect _VECTOR(8) +-#define SIG_WATCHDOG_TIMEOUT _VECTOR(8) +- +-/* Timer/Counter2 Compare Match A */ +-#define TIMER2_COMPA_vect_num 9 +-#define TIMER2_COMPA_vect _VECTOR(9) +-#define SIG_OUTPUT_COMPARE2A _VECTOR(9) +- +-/* Timer/Counter2 Compare Match B */ +-#define TIMER2_COMPB_vect_num 10 +-#define TIMER2_COMPB_vect _VECTOR(10) +-#define SIG_OUTPUT_COMPARE2B _VECTOR(10) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 11 +-#define TIMER2_OVF_vect _VECTOR(11) +-#define SIG_OVERFLOW2 _VECTOR(11) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 12 +-#define TIMER1_CAPT_vect _VECTOR(12) +-#define SIG_INPUT_CAPTURE1 _VECTOR(12) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 13 +-#define TIMER1_COMPA_vect _VECTOR(13) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(13) +- +-/* Timer/Counter1 Compare Match B */ +-#define TIMER1_COMPB_vect_num 14 +-#define TIMER1_COMPB_vect _VECTOR(14) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(14) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 15 +-#define TIMER1_OVF_vect _VECTOR(15) +-#define SIG_OVERFLOW1 _VECTOR(15) +- +-/* Timer/Counter0 Compare Match A */ +-#define TIMER0_COMPA_vect_num 16 +-#define TIMER0_COMPA_vect _VECTOR(16) +-#define SIG_OUTPUT_COMPARE0A _VECTOR(16) +- +-/* Timer/Counter0 Compare Match B */ +-#define TIMER0_COMPB_vect_num 17 +-#define TIMER0_COMPB_vect _VECTOR(17) +-#define SIG_OUTPUT_COMPARE0B _VECTOR(17) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 18 +-#define TIMER0_OVF_vect _VECTOR(18) +-#define SIG_OVERFLOW0 _VECTOR(18) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 19 +-#define SPI_STC_vect _VECTOR(19) +-#define SIG_SPI _VECTOR(19) +- +-/* USART0, Rx Complete */ +-#define USART0_RX_vect_num 20 +-#define USART0_RX_vect _VECTOR(20) +-#define SIG_USART_RECV _VECTOR(20) +- +-/* USART0 Data register Empty */ +-#define USART0_UDRE_vect_num 21 +-#define USART0_UDRE_vect _VECTOR(21) +-#define SIG_USART_DATA _VECTOR(21) +- +-/* USART0, Tx Complete */ +-#define USART0_TX_vect_num 22 +-#define USART0_TX_vect _VECTOR(22) +-#define SIG_USART_TRANS _VECTOR(22) +- +-/* Analog Comparator */ +-#define ANALOG_COMP_vect_num 23 +-#define ANALOG_COMP_vect _VECTOR(23) +-#define SIG_COMPARATOR _VECTOR(23) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 24 +-#define ADC_vect _VECTOR(24) +-#define SIG_ADC _VECTOR(24) +- +-/* EEPROM Ready */ +-#define EE_READY_vect_num 25 +-#define EE_READY_vect _VECTOR(25) +-#define SIG_EEPROM_READY _VECTOR(25) +- +-/* 2-wire Serial Interface */ +-#define TWI_vect_num 26 +-#define TWI_vect _VECTOR(26) +-#define SIG_2WIRE_SERIAL _VECTOR(26) +- +-/* Store Program Memory Read */ +-#define SPM_READY_vect_num 27 +-#define SPM_READY_vect _VECTOR(27) +-#define SIG_SPM_READY _VECTOR(27) +- +-#if defined(__AVR_ATmega644__) +- +-# define _VECTORS_SIZE 112 +- +-#else /* !defined(__AVR_ATmega644__) */ +- +-/* USART1, Rx Complete */ +-/* USART1 RX complete */ +-#define USART1_RX_vect_num 28 +-#define USART1_RX_vect _VECTOR(28) +-#define SIG_USART1_RECV _VECTOR(28) +- +-/* USART1 Data register Empty */ +-/* USART1 Data Register Empty */ +-#define USART1_UDRE_vect_num 29 +-#define USART1_UDRE_vect _VECTOR(29) +-#define SIG_USART1_DATA _VECTOR(29) +- +-/* USART1, Tx Complete */ +-/* USART1 TX complete */ +-#define USART1_TX_vect_num 30 +-#define USART1_TX_vect _VECTOR(30) +-#define SIG_USART1_TRANS _VECTOR(30) +- +-# define _VECTORS_SIZE 124 +- +-#endif /* defined(__AVR_ATmega644__) */ +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_INTERRUPT1 +-#pragma GCC poison SIG_INTERRUPT2 +-#pragma GCC poison SIG_PIN_CHANGE0 +-#pragma GCC poison SIG_PIN_CHANGE1 +-#pragma GCC poison SIG_PIN_CHANGE2 +-#pragma GCC poison SIG_PIN_CHANGE3 +-#pragma GCC poison SIG_WATCHDOG_TIMEOUT +-#pragma GCC poison SIG_OUTPUT_COMPARE2A +-#pragma GCC poison SIG_OUTPUT_COMPARE2B +-#pragma GCC poison SIG_OVERFLOW2 +-#pragma GCC poison SIG_INPUT_CAPTURE1 +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OUTPUT_COMPARE0A +-#pragma GCC poison SIG_OUTPUT_COMPARE0B +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_SPI +-#pragma GCC poison SIG_USART_RECV +-#pragma GCC poison SIG_USART_DATA +-#pragma GCC poison SIG_USART_TRANS +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_ADC +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_2WIRE_SERIAL +-#pragma GCC poison SIG_SPM_READY +-#pragma GCC poison SIG_USART1_RECV +-#pragma GCC poison SIG_USART1_DATA +-#pragma GCC poison SIG_USART1_TRANS +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +-#endif /* _AVR_IOMXX4_H_ */ ++/* Copyright (c) 2005, 2006, 2007 Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* avr/iomXX4.h - definitions for ATmega164P/324P/644P and ATmega644 */ ++ ++/* $Id: iomxx4.h 2235 2011-03-17 04:13:14Z arcanum $ */ ++ ++#ifndef _AVR_IOMXX4_H_ ++#define _AVR_IOMXX4_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iom164.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0X00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0X01) ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++#define PORTA _SFR_IO8(0X02) ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++#define PINB _SFR_IO8(0X03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* Reserved [0x0C..0x14] */ ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define OCF0B 2 ++#define OCF0A 1 ++#define TOV0 0 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define ICF1 5 ++#define OCF1B 2 ++#define OCF1A 1 ++#define TOV1 0 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define OCF2B 2 ++#define OCF2A 1 ++#define TOV2 0 ++ ++/* Reserved [0x18..0x1A] */ ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF3 3 ++#define PCIF2 2 ++#define PCIF1 1 ++#define PCIF0 0 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF2 2 ++#define INTF1 1 ++#define INTF0 0 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT2 2 ++#define INT1 1 ++#define INT0 0 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++/* EECR - EEPROM Control Register */ ++#define EEPM1 5 ++#define EEPM0 4 ++#define EERIE 3 ++#define EEMPE 2 ++#define EEPE 1 ++#define EERE 0 ++ ++#define EEDR _SFR_IO8(0X20) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x21) ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0X22) ++ ++/* 6-char sequence denoting where to find the EEPROM registers in memory space. ++ Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM ++ subroutines. ++ First two letters: EECR address. ++ Second two letters: EEDR address. ++ Last two letters: EEAR address. */ ++#define __EEPROM_REG_LOCATIONS__ 1F2021 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define TSM 7 ++#define PSRASY 1 ++#define PSRSYNC 0 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define COM0A1 7 ++#define COM0A0 6 ++#define COM0B1 5 ++#define COM0B0 4 ++#define WGM01 1 ++#define WGM00 0 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define FOC0A 7 ++#define FOC0B 6 ++#define WGM02 3 ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++#define TCNT0 _SFR_IO8(0X26) ++ ++#define OCR0A _SFR_IO8(0X27) ++ ++#define OCR0B _SFR_IO8(0X28) ++ ++/* Reserved [0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPIF 7 ++#define WCOL 6 ++#define SPI2X 0 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACD 7 ++#define ACBG 6 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++#define MONDR _SFR_IO8(0x31) ++#define OCDR _SFR_IO8(0x31) ++#define IDRD 7 ++#define OCDR7 7 ++#define OCDR6 6 ++#define OCDR5 5 ++#define OCDR4 4 ++#define OCDR3 3 ++#define OCDR2 2 ++#define OCDR1 1 ++#define OCDR0 0 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SM2 3 ++#define SM1 2 ++#define SM0 1 ++#define SE 0 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define JTRF 4 ++#define WDRF 3 ++#define BORF 2 ++#define EXTRF 1 ++#define PORF 0 ++ ++#define MCUCR _SFR_IO8(0X35) ++#define JTD 7 ++#if !defined(__AVR_ATmega644__) ++#define BODS 6 ++#define BODSE 5 ++#endif ++#define PUD 4 ++#define IVSEL 1 ++#define IVCE 0 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMIE 7 ++#define RWWSB 6 ++#define SIGRD 5 ++#define RWWSRE 4 ++#define BLBSET 3 ++#define PGWRT 2 ++#define PGERS 1 ++#define SPMEN 0 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++/* SREG [0x3F] */ ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDIF 7 ++#define WDIE 6 ++#define WDP3 5 ++#define WDCE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPCE 7 ++#define CLKPS3 3 ++#define CLKPS2 2 ++#define CLKPS1 1 ++#define CLKPS0 0 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR _SFR_MEM8(0x64) /* Datasheets: ATmega164P/324P/644P 8011D�AVR�02/07 ++ and ATmega644 2593L�AVR�02/07. */ ++#define PRR0 _SFR_MEM8(0x64) /* AVR Studio 4.13, build 524. */ ++#define PRTWI 7 ++#define PRTIM2 6 ++#define PRTIM0 5 ++#if !defined(__AVR_ATmega644__) ++# define PRUSART1 4 ++#endif ++#define PRTIM1 3 ++#define PRSPI 2 ++#define PRUSART0 1 ++#define PRADC 0 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL _SFR_MEM8(0x66) ++ ++/* Reserved [0x67] */ ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE3 3 ++#define PCIE2 2 ++#define PCIE1 1 ++#define PCIE0 0 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC21 5 ++#define ISC20 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT7 7 ++#define PCINT6 6 ++#define PCINT5 5 ++#define PCINT4 4 ++#define PCINT3 3 ++#define PCINT2 2 ++#define PCINT1 1 ++#define PCINT0 0 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT15 7 ++#define PCINT14 6 ++#define PCINT13 5 ++#define PCINT12 4 ++#define PCINT11 3 ++#define PCINT10 2 ++#define PCINT9 1 ++#define PCINT8 0 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT23 7 ++#define PCINT22 6 ++#define PCINT21 5 ++#define PCINT20 4 ++#define PCINT19 3 ++#define PCINT18 2 ++#define PCINT17 1 ++#define PCINT16 0 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define OCIE0B 2 ++#define OCIE0A 1 ++#define TOIE0 0 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define ICIE1 5 ++#define OCIE1B 2 ++#define OCIE1A 1 ++#define TOIE1 0 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define OCIE2B 2 ++#define OCIE2A 1 ++#define TOIE2 0 ++ ++/* Reserved [0x71..0x72] */ ++ ++#define PCMSK3 _SFR_MEM8(0x73) ++#define PCINT31 7 ++#define PCINT30 6 ++#define PCINT29 5 ++#define PCINT28 4 ++#define PCINT27 3 ++#define PCINT26 2 ++#define PCINT25 1 ++#define PCINT24 0 ++ ++/* Reserved [0x74..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADEN 7 ++#define ADSC 6 ++#define ADATE 5 ++#define ADIF 4 ++#define ADIE 3 ++#define ADPS2 2 ++#define ADPS1 1 ++#define ADPS0 0 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ACME 6 ++#define ADTS2 2 ++#define ADTS1 1 ++#define ADTS0 0 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define REFS1 7 ++#define REFS0 6 ++#define ADLAR 5 ++#define MUX4 4 ++#define MUX3 3 ++#define MUX2 2 ++#define MUX1 1 ++#define MUX0 0 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC7D 7 ++#define ADC6D 6 ++#define ADC5D 5 ++#define ADC4D 4 ++#define ADC3D 3 ++#define ADC2D 2 ++#define ADC1D 1 ++#define ADC0D 0 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN1D 1 ++#define AIN0D 0 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define WGM11 1 ++#define WGM10 0 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define ICNC1 7 ++#define ICES1 6 ++#define WGM13 4 ++#define WGM12 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1A 7 ++#define FOC1B 6 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xAF] */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define COM2A1 7 ++#define COM2A0 6 ++#define COM2B1 5 ++#define COM2B0 4 ++#define WGM21 1 ++#define WGM20 0 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define FOC2A 7 ++#define FOC2B 6 ++#define WGM22 3 ++#define CS22 2 ++#define CS21 1 ++#define CS20 0 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++#define OCR2B _SFR_MEM8(0xB4) ++ ++/* Reserved [0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define EXCLK 6 ++#define AS2 5 ++#define TCN2UB 4 ++#define OCR2AUB 3 ++#define OCR2BUB 2 ++#define TCR2AUB 1 ++#define TCR2BUB 0 ++ ++/* Reserved [0xB7] */ ++ ++#define TWBR _SFR_MEM8(0xB8) ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWS7 7 ++#define TWS6 6 ++#define TWS5 5 ++#define TWS4 4 ++#define TWS3 3 ++#define TWPS1 1 ++#define TWPS0 0 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWA6 7 ++#define TWA5 6 ++#define TWA4 5 ++#define TWA3 4 ++#define TWA2 3 ++#define TWA1 2 ++#define TWA0 1 ++#define TWGCE 0 ++ ++#define TWDR _SFR_MEM8(0xBB) ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWINT 7 ++#define TWEA 6 ++#define TWSTA 5 ++#define TWSTO 4 ++#define TWWC 3 ++#define TWEN 2 ++#define TWIE 0 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM6 7 ++#define TWAM5 6 ++#define TWAM4 5 ++#define TWAM3 4 ++#define TWAM2 3 ++#define TWAM1 2 ++#define TWAM0 1 ++ ++/* Reserved [0xBE..0xBF] */ ++ ++#define UCSR0A _SFR_MEM8(0xC0) ++#define RXC0 7 ++#define TXC0 6 ++#define UDRE0 5 ++#define FE0 4 ++#define DOR0 3 ++#define UPE0 2 ++#define U2X0 1 ++#define MPCM0 0 ++ ++#define UCSR0B _SFR_MEM8(0XC1) ++#define RXCIE0 7 ++#define TXCIE0 6 ++#define UDRIE0 5 ++#define RXEN0 4 ++#define TXEN0 3 ++#define UCSZ02 2 ++#define RXB80 1 ++#define TXB80 0 ++ ++#define UCSR0C _SFR_MEM8(0xC2) ++#define UMSEL01 7 ++#define UMSEL00 6 ++#define UPM01 5 ++#define UPM00 4 ++#define USBS0 3 ++#define UCSZ01 2 ++#define UCSZ00 1 ++#define UCPHA0 1 ++#define UCPOL0 0 ++ ++/* Reserved [0xC3] */ ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0xC4) ++ ++#define UBRR0L _SFR_MEM8(0xC4) ++#define UBRR0H _SFR_MEM8(0xC5) ++ ++#define UDR0 _SFR_MEM8(0XC6) ++ ++#if !defined(__AVR_ATmega644__) ++/* ++ * Only ATmega164P/324P/644P have a second USART. ++ */ ++/* Reserved [0xC7] */ ++ ++#define UCSR1A _SFR_MEM8(0xC8) ++#define RXC1 7 ++#define TXC1 6 ++#define UDRE1 5 ++#define FE1 4 ++#define DOR1 3 ++#define UPE1 2 ++#define U2X1 1 ++#define MPCM1 0 ++ ++#define UCSR1B _SFR_MEM8(0XC9) ++#define RXCIE1 7 ++#define TXCIE1 6 ++#define UDRIE1 5 ++#define RXEN1 4 ++#define TXEN1 3 ++#define UCSZ12 2 ++#define RXB81 1 ++#define TXB81 0 ++ ++#define UCSR1C _SFR_MEM8(0xCA) ++#define UMSEL11 7 ++#define UMSEL10 6 ++#define UPM11 5 ++#define UPM10 4 ++#define USBS1 3 ++#define UCSZ11 2 ++#define UCSZ10 1 ++#define UCPHA1 1 ++#define UCPOL1 0 ++ ++/* Reserved [0xCB] */ ++ ++/* Combine UBRR1L and UBRR1H */ ++#define UBRR1 _SFR_MEM16(0xCC) ++ ++#define UBRR1L _SFR_MEM8(0xCC) ++#define UBRR1H _SFR_MEM8(0xCD) ++ ++#define UDR1 _SFR_MEM8(0XCE) ++#endif /* !defined(__AVR_ATmega644) */ ++ ++/* Reserved [0xCF..0xFF] */ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++#define SIG_INTERRUPT1 _VECTOR(2) ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect_num 3 ++#define INT2_vect _VECTOR(3) ++#define SIG_INTERRUPT2 _VECTOR(3) ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect_num 4 ++#define PCINT0_vect _VECTOR(4) ++#define SIG_PIN_CHANGE0 _VECTOR(4) ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect_num 5 ++#define PCINT1_vect _VECTOR(5) ++#define SIG_PIN_CHANGE1 _VECTOR(5) ++ ++/* Pin Change Interrupt Request 2 */ ++#define PCINT2_vect_num 6 ++#define PCINT2_vect _VECTOR(6) ++#define SIG_PIN_CHANGE2 _VECTOR(6) ++ ++/* Pin Change Interrupt Request 3 */ ++#define PCINT3_vect_num 7 ++#define PCINT3_vect _VECTOR(7) ++#define SIG_PIN_CHANGE3 _VECTOR(7) ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect_num 8 ++#define WDT_vect _VECTOR(8) ++#define SIG_WATCHDOG_TIMEOUT _VECTOR(8) ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPA_vect_num 9 ++#define TIMER2_COMPA_vect _VECTOR(9) ++#define SIG_OUTPUT_COMPARE2A _VECTOR(9) ++ ++/* Timer/Counter2 Compare Match B */ ++#define TIMER2_COMPB_vect_num 10 ++#define TIMER2_COMPB_vect _VECTOR(10) ++#define SIG_OUTPUT_COMPARE2B _VECTOR(10) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 11 ++#define TIMER2_OVF_vect _VECTOR(11) ++#define SIG_OVERFLOW2 _VECTOR(11) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 12 ++#define TIMER1_CAPT_vect _VECTOR(12) ++#define SIG_INPUT_CAPTURE1 _VECTOR(12) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 13 ++#define TIMER1_COMPA_vect _VECTOR(13) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(13) ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect_num 14 ++#define TIMER1_COMPB_vect _VECTOR(14) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(14) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 15 ++#define TIMER1_OVF_vect _VECTOR(15) ++#define SIG_OVERFLOW1 _VECTOR(15) ++ ++/* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPA_vect_num 16 ++#define TIMER0_COMPA_vect _VECTOR(16) ++#define SIG_OUTPUT_COMPARE0A _VECTOR(16) ++ ++/* Timer/Counter0 Compare Match B */ ++#define TIMER0_COMPB_vect_num 17 ++#define TIMER0_COMPB_vect _VECTOR(17) ++#define SIG_OUTPUT_COMPARE0B _VECTOR(17) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 18 ++#define TIMER0_OVF_vect _VECTOR(18) ++#define SIG_OVERFLOW0 _VECTOR(18) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 19 ++#define SPI_STC_vect _VECTOR(19) ++#define SIG_SPI _VECTOR(19) ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect_num 20 ++#define USART0_RX_vect _VECTOR(20) ++#define SIG_USART_RECV _VECTOR(20) ++ ++/* USART0 Data register Empty */ ++#define USART0_UDRE_vect_num 21 ++#define USART0_UDRE_vect _VECTOR(21) ++#define SIG_USART_DATA _VECTOR(21) ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect_num 22 ++#define USART0_TX_vect _VECTOR(22) ++#define SIG_USART_TRANS _VECTOR(22) ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect_num 23 ++#define ANALOG_COMP_vect _VECTOR(23) ++#define SIG_COMPARATOR _VECTOR(23) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 24 ++#define ADC_vect _VECTOR(24) ++#define SIG_ADC _VECTOR(24) ++ ++/* EEPROM Ready */ ++#define EE_READY_vect_num 25 ++#define EE_READY_vect _VECTOR(25) ++#define SIG_EEPROM_READY _VECTOR(25) ++ ++/* 2-wire Serial Interface */ ++#define TWI_vect_num 26 ++#define TWI_vect _VECTOR(26) ++#define SIG_2WIRE_SERIAL _VECTOR(26) ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect_num 27 ++#define SPM_READY_vect _VECTOR(27) ++#define SIG_SPM_READY _VECTOR(27) ++ ++#if defined(__AVR_ATmega644__) ++ ++# define _VECTORS_SIZE 112 ++ ++#else /* !defined(__AVR_ATmega644__) */ ++ ++/* USART1, Rx Complete */ ++/* USART1 RX complete */ ++#define USART1_RX_vect_num 28 ++#define USART1_RX_vect _VECTOR(28) ++#define SIG_USART1_RECV _VECTOR(28) ++ ++/* USART1 Data register Empty */ ++/* USART1 Data Register Empty */ ++#define USART1_UDRE_vect_num 29 ++#define USART1_UDRE_vect _VECTOR(29) ++#define SIG_USART1_DATA _VECTOR(29) ++ ++/* USART1, Tx Complete */ ++/* USART1 TX complete */ ++#define USART1_TX_vect_num 30 ++#define USART1_TX_vect _VECTOR(30) ++#define SIG_USART1_TRANS _VECTOR(30) ++ ++# define _VECTORS_SIZE 124 ++ ++#endif /* defined(__AVR_ATmega644__) */ ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_INTERRUPT1 ++#pragma GCC poison SIG_INTERRUPT2 ++#pragma GCC poison SIG_PIN_CHANGE0 ++#pragma GCC poison SIG_PIN_CHANGE1 ++#pragma GCC poison SIG_PIN_CHANGE2 ++#pragma GCC poison SIG_PIN_CHANGE3 ++#pragma GCC poison SIG_WATCHDOG_TIMEOUT ++#pragma GCC poison SIG_OUTPUT_COMPARE2A ++#pragma GCC poison SIG_OUTPUT_COMPARE2B ++#pragma GCC poison SIG_OVERFLOW2 ++#pragma GCC poison SIG_INPUT_CAPTURE1 ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OUTPUT_COMPARE0A ++#pragma GCC poison SIG_OUTPUT_COMPARE0B ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_SPI ++#pragma GCC poison SIG_USART_RECV ++#pragma GCC poison SIG_USART_DATA ++#pragma GCC poison SIG_USART_TRANS ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_ADC ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_2WIRE_SERIAL ++#pragma GCC poison SIG_SPM_READY ++#pragma GCC poison SIG_USART1_RECV ++#pragma GCC poison SIG_USART1_DATA ++#pragma GCC poison SIG_USART1_TRANS ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++#endif /* _AVR_IOMXX4_H_ */ +diff --git a/include/avr/iomxxhva.h b/include/avr/iomxxhva.h +index 82b0981..b0bd342 100644 +--- a/include/avr/iomxxhva.h ++++ b/include/avr/iomxxhva.h +@@ -1,543 +1,543 @@ +-/* Copyright (c) 2007, Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iomxxhva.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* iomxxhva.h - definitions for ATmega8HVA and ATmega16HVA. */ +- +-#ifndef _AVR_IOMXXHVA_H_ +-#define _AVR_IOMXXHVA_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iomxxhva.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* Registers and associated bit numbers */ +- +-#define PINA _SFR_IO8(0X00) +-#define PINA1 1 +-#define PINA0 0 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA1 1 +-#define DDA0 0 +- +-#define PORTA _SFR_IO8(0x02) +-#define PA1 1 +-#define PA0 0 +- +-#define PINB _SFR_IO8(0X03) +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-#define PORTB _SFR_IO8(0x05) +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +- +-/* Reserved [0x7] */ +- +-#define PORTC _SFR_IO8(0x08) +-#define PC0 0 +- +-/* Reserved [0x9..0x14] */ +- +-#define TIFR0 _SFR_IO8(0x15) +-#define ICF0 3 +-#define OCF0B 2 +-#define OCF0A 1 +-#define TOV0 0 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define ICF1 3 +-#define OCF1B 2 +-#define OCF1A 1 +-#define TOV1 0 +- +-#define OSICSR _SFR_IO8(0x17) +-#define OSISEL0 4 +-#define OSIST 1 +-#define OSIEN 0 +- +-/* Reserved [0x18..0x1B] */ +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF2 2 +-#define INTF1 1 +-#define INTF0 0 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT2 2 +-#define INT1 1 +-#define INT0 0 +- +-#define GPIOR0 _SFR_IO8(0x1E) +- +-#define EECR _SFR_IO8(0x1F) +-#define EEPM1 5 +-#define EEPM0 4 +-#define EERIE 3 +-#define EEMPE 2 +-#define EEPE 1 +-#define EERE 0 +- +-#define EEDR _SFR_IO8(0x20) +- +-#define EEAR _SFR_IO8(0x21) +-#define EEARL _SFR_IO8(0x21) +- +-/* 6-char sequence denoting where to find the EEPROM registers in memory space. +- Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM +- subroutines. +- First two letters: EECR address. +- Second two letters: EEDR address. +- Last two letters: EEAR address. */ +-#define __EEPROM_REG_LOCATIONS__ 1F2021 +- +-/* Reserved [0x22] */ +- +-#define GTCCR _SFR_IO8(0x23) +-#define TSM 7 +-#define PSRSYNC 0 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define TCW0 7 +-#define ICEN0 6 +-#define ICNC0 5 +-#define ICES0 4 +-#define ICS0 3 +-#define WGM00 0 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-#define TCNT0 _SFR_IO16(0X26) +-#define TCNT0L _SFR_IO8(0X26) +-#define TCNT0H _SFR_IO8(0X27) +- +-#define OCR0A _SFR_IO8(0x28) +- +-#define OCR0B _SFR_IO8(0X29) +- +-#define GPIOR1 _SFR_IO8(0x2A) +- +-#define GPIOR2 _SFR_IO8(0x2B) +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPIF 7 +-#define WCOL 6 +-#define SPI2X 0 +- +-#define SPDR _SFR_IO8(0x2E) +- +-/* Reserved [0x2F..0x30] */ +- +-#define DWDR _SFR_IO8(0x31) +-#define IDRD 7 +- +-/* Reserved [0x32] */ +- +-#define SMCR _SFR_IO8(0x33) +-#define SM2 3 +-#define SM1 2 +-#define SM0 1 +-#define SE 0 +- +-#define MCUSR _SFR_IO8(0x34) +-#define OCDRF 4 +-#define WDRF 3 +-#define BORF 2 +-#define EXTRF 1 +-#define PORF 0 +- +-#define MCUCR _SFR_IO8(0x35) +-#define CKOE 5 +-#define PUD 4 +- +-/* Reserved [0x36] */ +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SIGRD 5 +-#define CTPB 4 +-#define RFLB 3 +-#define PGWRT 2 +-#define PGERS 1 +-#define SPMEN 0 +- +-/* Reserved [0x38..0x3C] */ +- +-/* SP [0x3D..0x3E] */ +-/* SREG [0x3F] */ +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDIF 7 +-#define WDIE 6 +-#define WDP3 5 +-#define WDCE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPCE 7 +-#define CLKPS1 1 +-#define CLKPS0 0 +- +-/* Reserved [0x62..0x63] */ +- +-#define PRR0 _SFR_MEM8(0x64) +-#define PRVRM 5 +-#define PRSPI 3 +-#define PRTIM1 2 +-#define PRTIM0 1 +-#define PRVADC 0 +- +-/* Reserved [0x65] */ +- +-#define FOSCCAL _SFR_MEM8(0x66) +- +-/* Reserved [0x67..0x68] */ +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC21 5 +-#define ISC20 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-/* Reserved [0x6A..0x6D] */ +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define ICIE0 3 +-#define OCIE0B 2 +-#define OCIE0A 1 +-#define TOIE0 0 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define ICIE1 3 +-#define OCIE1B 2 +-#define OCIE1A 1 +-#define TOIE1 0 +- +-/* Reserved [0x70..0x77] */ +- +-#define VADC _SFR_MEM16(0x78) +-#define VADCL _SFR_MEM8(0x78) +-#define VADCH _SFR_MEM8(0x79) +- +-#define VADCSR _SFR_MEM8(0x7A) +-#define VADEN 3 +-#define VADSC 2 +-#define VADCCIF 1 +-#define VADCCIE 0 +- +-/* Reserved [0x7B] */ +- +-#define VADMUX _SFR_MEM8(0x7C) +-#define VADMUX3 3 +-#define VADMUX2 2 +-#define VADMUX1 1 +-#define VADMUX0 0 +- +-/* Reserved [0x7D] */ +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define PA1DID 1 +-#define PA0DID 0 +- +-/* Reserved [0x7F] */ +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define TCW1 7 +-#define ICEN1 6 +-#define ICNC1 5 +-#define ICES1 4 +-#define ICS1 3 +-#define WGM10 0 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* Reserved [0x82..0x83] */ +- +-#define TCNT1 _SFR_MEM16(0x84) +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1H _SFR_MEM8(0x85) +- +-/* Reserved [0x86..0x87] */ +- +-#define OCR1A _SFR_MEM8(0x88) +- +-#define OCR1B _SFR_MEM8(0x89) +- +-/* Reserved [0x8A..0xC7] */ +- +-#define ROCR _SFR_MEM8(0xC8) +-#define ROCS 7 +-#define ROCWIF 1 +-#define ROCWIE 0 +- +-/* Reserved [0xC9..0xCF] */ +- +-#define BGCCR _SFR_MEM8(0xD0) +-#define BGD 7 +-#define BGCC5 5 +-#define BGCC4 4 +-#define BGCC3 3 +-#define BGCC2 2 +-#define BGCC1 1 +-#define BGCC0 0 +- +-#define BGCRR _SFR_MEM8(0xD1) +-#define BGCR7 7 +-#define BGCR6 6 +-#define BGCR5 5 +-#define BGCR4 4 +-#define BGCR3 3 +-#define BGCR2 2 +-#define BGCR1 1 +-#define BGCR0 0 +- +-/* Reserved [0xD2..0xDF] */ +- +-/* CC-ADC Accumulate Current */ +-/* TODO: Add _SFR_MEM32 */ +-/* #define CADAC _SFR_MEM32(0xE0) */ +-#define CADAC0 _SFR_MEM8(0xE0) +-#define CADAC1 _SFR_MEM8(0xE1) +-#define CADAC2 _SFR_MEM8(0xE2) +-#define CADAC3 _SFR_MEM8(0xE3) +- +-#define CADCSRA _SFR_MEM8(0xE4) +-#define CADEN 7 +-#define CADPOL 6 +-#define CADUB 5 +-#define CADAS1 4 +-#define CADAS0 3 +-#define CADSI1 2 +-#define CADSI0 1 +-#define CADSE 0 +- +-#define CADCSRB _SFR_MEM8(0xE5) +-#define CADACIE 6 +-#define CADRCIE 5 +-#define CADICIE 4 +-#define CADACIF 2 +-#define CADRCIF 1 +-#define CADICIF 0 +- +-#define CADRC _SFR_MEM8(0xE6) +- +-/* Reserved [0xE7] */ +- +-#define CADIC _SFR_MEM16(0xE8) +-#define CADICL _SFR_MEM8(0xE8) +-#define CADICH _SFR_MEM8(0xE9) +- +-/* Reserved [0xEA..0xEF] */ +- +-#define FCSR _SFR_MEM8(0xF0) +-#define DUVRD 3 +-#define CPS 2 +-#define DFE 1 +-#define CFE 0 +- +-/* Reserved [0xF1] */ +- +-#define BPIMSK _SFR_MEM8(0xF2) +-#define SCIE 4 +-#define DOCIE 3 +-#define COCIE 2 +-#define DHCIE 1 +-#define CHCIE 0 +- +-#define BPIFR _SFR_MEM8(0xF3) +-#define SCIF 4 +-#define DOCIF 3 +-#define COCIF 2 +-#define DHCIF 1 +-#define CHCIF 0 +- +-/* Reserved [0xF4] */ +- +-#define BPSCD _SFR_MEM8(0xF5) +- +-#define BPDOCD _SFR_MEM8(0xF6) +- +-#define BPCOCD _SFR_MEM8(0xF7) +- +-#define BPDHCD _SFR_MEM8(0xF8) +- +-#define BPCHCD _SFR_MEM8(0xF9) +- +-#define BPSCTR _SFR_MEM8(0xFA) +- +-#define BPOCTR _SFR_MEM8(0xFB) +- +-#define BPHCTR _SFR_MEM8(0xFC) +- +-#define BPCR _SFR_MEM8(0xFD) +-#define SCD 4 +-#define DOCD 3 +-#define COCD 2 +-#define DHCD 1 +-#define CHCD 0 +- +-#define BPPLR _SFR_MEM8(0xFE) +-#define BPPLE 1 +-#define BPPL 0 +- +-/* Reserved [0xFF] */ +- +-/* Interrupt vectors */ +-/* Battery Protection Interrupt */ +-#define BPINT_vect_num 1 +-#define BPINT_vect _VECTOR(1) +- +-/* Voltage Regulator Monitor Interrupt */ +-#define VREGMON_vect_num 2 +-#define VREGMON_vect _VECTOR(2) +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 3 +-#define INT0_vect _VECTOR(3) +- +-/* External Interrupt Request 1 */ +-#define INT1_vect_num 4 +-#define INT1_vect _VECTOR(4) +- +-/* External Interrupt Request 2 */ +-#define INT2_vect_num 5 +-#define INT2_vect _VECTOR(5) +- +-/* Watchdog Timeout Interrupt */ +-#define WDT_vect_num 6 +-#define WDT_vect _VECTOR(6) +- +-/* Timer/Counter 1 Input Capture */ +-#define TIMER1_IC_vect_num 7 +-#define TIMER1_IC_vect _VECTOR(7) +- +-/* Timer/Counter 1 Compare A Match */ +-#define TIMER1_COMPA_vect_num 8 +-#define TIMER1_COMPA_vect _VECTOR(8) +- +-/* Timer/Counter 1 Compare B Match */ +-#define TIMER1_COMPB_vect_num 9 +-#define TIMER1_COMPB_vect _VECTOR(9) +- +-/* Timer/Counter 1 Overflow */ +-#define TIMER1_OVF_vect_num 10 +-#define TIMER1_OVF_vect _VECTOR(10) +- +-/* Timer/Counter 0 Input Capture */ +-#define TIMER0_IC_vect_num 11 +-#define TIMER0_IC_vect _VECTOR(11) +- +-/* Timer/Counter0 Compare A Match */ +-#define TIMER0_COMPA_vect_num 12 +-#define TIMER0_COMPA_vect _VECTOR(12) +- +-/* Timer/Counter0 Compare B Match */ +-#define TIMER0_COMPB_vect_num 13 +-#define TIMER0_COMPB_vect _VECTOR(13) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 14 +-#define TIMER0_OVF_vect _VECTOR(14) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 15 +-#define SPI_STC_vect _VECTOR(15) +- +-/* Voltage ADC Conversion Complete */ +-#define VADC_vect_num 16 +-#define VADC_vect _VECTOR(16) +- +-/* Coulomb Counter ADC Conversion Complete */ +-#define CCADC_CONV_vect_num 17 +-#define CCADC_CONV_vect _VECTOR(17) +- +-/* Coloumb Counter ADC Regular Current */ +-#define CCADC_REG_CUR_vect_num 18 +-#define CCADC_REG_CUR_vect _VECTOR(18) +- +-/* Coloumb Counter ADC Accumulator */ +-#define CCADC_ACC_vect_num 19 +-#define CCADC_ACC_vect _VECTOR(19) +- +-/* EEPROM Ready */ +-#define EE_READY_vect_num 20 +-#define EE_READY_vect _VECTOR(20) +- +-#if defined (__AVR_ATmega16HVA__) +-# define _VECTORS_SIZE 84 +-#else +-# define _VECTORS_SIZE 42 +-#endif +- +- +-#endif /* _AVR_IOMXXHVA_H_ */ ++/* Copyright (c) 2007, Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iomxxhva.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* iomxxhva.h - definitions for ATmega8HVA and ATmega16HVA. */ ++ ++#ifndef _AVR_IOMXXHVA_H_ ++#define _AVR_IOMXXHVA_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iomxxhva.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0X00) ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA1 1 ++#define DDA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PA1 1 ++#define PA0 0 ++ ++#define PINB _SFR_IO8(0X03) ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++ ++/* Reserved [0x7] */ ++ ++#define PORTC _SFR_IO8(0x08) ++#define PC0 0 ++ ++/* Reserved [0x9..0x14] */ ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define ICF0 3 ++#define OCF0B 2 ++#define OCF0A 1 ++#define TOV0 0 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define ICF1 3 ++#define OCF1B 2 ++#define OCF1A 1 ++#define TOV1 0 ++ ++#define OSICSR _SFR_IO8(0x17) ++#define OSISEL0 4 ++#define OSIST 1 ++#define OSIEN 0 ++ ++/* Reserved [0x18..0x1B] */ ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF2 2 ++#define INTF1 1 ++#define INTF0 0 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT2 2 ++#define INT1 1 ++#define INT0 0 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EEPM1 5 ++#define EEPM0 4 ++#define EERIE 3 ++#define EEMPE 2 ++#define EEPE 1 ++#define EERE 0 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++#define EEAR _SFR_IO8(0x21) ++#define EEARL _SFR_IO8(0x21) ++ ++/* 6-char sequence denoting where to find the EEPROM registers in memory space. ++ Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM ++ subroutines. ++ First two letters: EECR address. ++ Second two letters: EEDR address. ++ Last two letters: EEAR address. */ ++#define __EEPROM_REG_LOCATIONS__ 1F2021 ++ ++/* Reserved [0x22] */ ++ ++#define GTCCR _SFR_IO8(0x23) ++#define TSM 7 ++#define PSRSYNC 0 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define TCW0 7 ++#define ICEN0 6 ++#define ICNC0 5 ++#define ICES0 4 ++#define ICS0 3 ++#define WGM00 0 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++#define TCNT0 _SFR_IO16(0X26) ++#define TCNT0L _SFR_IO8(0X26) ++#define TCNT0H _SFR_IO8(0X27) ++ ++#define OCR0A _SFR_IO8(0x28) ++ ++#define OCR0B _SFR_IO8(0X29) ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPIF 7 ++#define WCOL 6 ++#define SPI2X 0 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F..0x30] */ ++ ++#define DWDR _SFR_IO8(0x31) ++#define IDRD 7 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SM2 3 ++#define SM1 2 ++#define SM0 1 ++#define SE 0 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define OCDRF 4 ++#define WDRF 3 ++#define BORF 2 ++#define EXTRF 1 ++#define PORF 0 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define CKOE 5 ++#define PUD 4 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SIGRD 5 ++#define CTPB 4 ++#define RFLB 3 ++#define PGWRT 2 ++#define PGERS 1 ++#define SPMEN 0 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++/* SREG [0x3F] */ ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDIF 7 ++#define WDIE 6 ++#define WDP3 5 ++#define WDCE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPCE 7 ++#define CLKPS1 1 ++#define CLKPS0 0 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRVRM 5 ++#define PRSPI 3 ++#define PRTIM1 2 ++#define PRTIM0 1 ++#define PRVADC 0 ++ ++/* Reserved [0x65] */ ++ ++#define FOSCCAL _SFR_MEM8(0x66) ++ ++/* Reserved [0x67..0x68] */ ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC21 5 ++#define ISC20 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* Reserved [0x6A..0x6D] */ ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define ICIE0 3 ++#define OCIE0B 2 ++#define OCIE0A 1 ++#define TOIE0 0 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define ICIE1 3 ++#define OCIE1B 2 ++#define OCIE1A 1 ++#define TOIE1 0 ++ ++/* Reserved [0x70..0x77] */ ++ ++#define VADC _SFR_MEM16(0x78) ++#define VADCL _SFR_MEM8(0x78) ++#define VADCH _SFR_MEM8(0x79) ++ ++#define VADCSR _SFR_MEM8(0x7A) ++#define VADEN 3 ++#define VADSC 2 ++#define VADCCIF 1 ++#define VADCCIE 0 ++ ++/* Reserved [0x7B] */ ++ ++#define VADMUX _SFR_MEM8(0x7C) ++#define VADMUX3 3 ++#define VADMUX2 2 ++#define VADMUX1 1 ++#define VADMUX0 0 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define PA1DID 1 ++#define PA0DID 0 ++ ++/* Reserved [0x7F] */ ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define TCW1 7 ++#define ICEN1 6 ++#define ICNC1 5 ++#define ICES1 4 ++#define ICS1 3 ++#define WGM10 0 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* Reserved [0x82..0x83] */ ++ ++#define TCNT1 _SFR_MEM16(0x84) ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Reserved [0x86..0x87] */ ++ ++#define OCR1A _SFR_MEM8(0x88) ++ ++#define OCR1B _SFR_MEM8(0x89) ++ ++/* Reserved [0x8A..0xC7] */ ++ ++#define ROCR _SFR_MEM8(0xC8) ++#define ROCS 7 ++#define ROCWIF 1 ++#define ROCWIE 0 ++ ++/* Reserved [0xC9..0xCF] */ ++ ++#define BGCCR _SFR_MEM8(0xD0) ++#define BGD 7 ++#define BGCC5 5 ++#define BGCC4 4 ++#define BGCC3 3 ++#define BGCC2 2 ++#define BGCC1 1 ++#define BGCC0 0 ++ ++#define BGCRR _SFR_MEM8(0xD1) ++#define BGCR7 7 ++#define BGCR6 6 ++#define BGCR5 5 ++#define BGCR4 4 ++#define BGCR3 3 ++#define BGCR2 2 ++#define BGCR1 1 ++#define BGCR0 0 ++ ++/* Reserved [0xD2..0xDF] */ ++ ++/* CC-ADC Accumulate Current */ ++/* TODO: Add _SFR_MEM32 */ ++/* #define CADAC _SFR_MEM32(0xE0) */ ++#define CADAC0 _SFR_MEM8(0xE0) ++#define CADAC1 _SFR_MEM8(0xE1) ++#define CADAC2 _SFR_MEM8(0xE2) ++#define CADAC3 _SFR_MEM8(0xE3) ++ ++#define CADCSRA _SFR_MEM8(0xE4) ++#define CADEN 7 ++#define CADPOL 6 ++#define CADUB 5 ++#define CADAS1 4 ++#define CADAS0 3 ++#define CADSI1 2 ++#define CADSI0 1 ++#define CADSE 0 ++ ++#define CADCSRB _SFR_MEM8(0xE5) ++#define CADACIE 6 ++#define CADRCIE 5 ++#define CADICIE 4 ++#define CADACIF 2 ++#define CADRCIF 1 ++#define CADICIF 0 ++ ++#define CADRC _SFR_MEM8(0xE6) ++ ++/* Reserved [0xE7] */ ++ ++#define CADIC _SFR_MEM16(0xE8) ++#define CADICL _SFR_MEM8(0xE8) ++#define CADICH _SFR_MEM8(0xE9) ++ ++/* Reserved [0xEA..0xEF] */ ++ ++#define FCSR _SFR_MEM8(0xF0) ++#define DUVRD 3 ++#define CPS 2 ++#define DFE 1 ++#define CFE 0 ++ ++/* Reserved [0xF1] */ ++ ++#define BPIMSK _SFR_MEM8(0xF2) ++#define SCIE 4 ++#define DOCIE 3 ++#define COCIE 2 ++#define DHCIE 1 ++#define CHCIE 0 ++ ++#define BPIFR _SFR_MEM8(0xF3) ++#define SCIF 4 ++#define DOCIF 3 ++#define COCIF 2 ++#define DHCIF 1 ++#define CHCIF 0 ++ ++/* Reserved [0xF4] */ ++ ++#define BPSCD _SFR_MEM8(0xF5) ++ ++#define BPDOCD _SFR_MEM8(0xF6) ++ ++#define BPCOCD _SFR_MEM8(0xF7) ++ ++#define BPDHCD _SFR_MEM8(0xF8) ++ ++#define BPCHCD _SFR_MEM8(0xF9) ++ ++#define BPSCTR _SFR_MEM8(0xFA) ++ ++#define BPOCTR _SFR_MEM8(0xFB) ++ ++#define BPHCTR _SFR_MEM8(0xFC) ++ ++#define BPCR _SFR_MEM8(0xFD) ++#define SCD 4 ++#define DOCD 3 ++#define COCD 2 ++#define DHCD 1 ++#define CHCD 0 ++ ++#define BPPLR _SFR_MEM8(0xFE) ++#define BPPLE 1 ++#define BPPL 0 ++ ++/* Reserved [0xFF] */ ++ ++/* Interrupt vectors */ ++/* Battery Protection Interrupt */ ++#define BPINT_vect_num 1 ++#define BPINT_vect _VECTOR(1) ++ ++/* Voltage Regulator Monitor Interrupt */ ++#define VREGMON_vect_num 2 ++#define VREGMON_vect _VECTOR(2) ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 3 ++#define INT0_vect _VECTOR(3) ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect_num 4 ++#define INT1_vect _VECTOR(4) ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect_num 5 ++#define INT2_vect _VECTOR(5) ++ ++/* Watchdog Timeout Interrupt */ ++#define WDT_vect_num 6 ++#define WDT_vect _VECTOR(6) ++ ++/* Timer/Counter 1 Input Capture */ ++#define TIMER1_IC_vect_num 7 ++#define TIMER1_IC_vect _VECTOR(7) ++ ++/* Timer/Counter 1 Compare A Match */ ++#define TIMER1_COMPA_vect_num 8 ++#define TIMER1_COMPA_vect _VECTOR(8) ++ ++/* Timer/Counter 1 Compare B Match */ ++#define TIMER1_COMPB_vect_num 9 ++#define TIMER1_COMPB_vect _VECTOR(9) ++ ++/* Timer/Counter 1 Overflow */ ++#define TIMER1_OVF_vect_num 10 ++#define TIMER1_OVF_vect _VECTOR(10) ++ ++/* Timer/Counter 0 Input Capture */ ++#define TIMER0_IC_vect_num 11 ++#define TIMER0_IC_vect _VECTOR(11) ++ ++/* Timer/Counter0 Compare A Match */ ++#define TIMER0_COMPA_vect_num 12 ++#define TIMER0_COMPA_vect _VECTOR(12) ++ ++/* Timer/Counter0 Compare B Match */ ++#define TIMER0_COMPB_vect_num 13 ++#define TIMER0_COMPB_vect _VECTOR(13) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 14 ++#define TIMER0_OVF_vect _VECTOR(14) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 15 ++#define SPI_STC_vect _VECTOR(15) ++ ++/* Voltage ADC Conversion Complete */ ++#define VADC_vect_num 16 ++#define VADC_vect _VECTOR(16) ++ ++/* Coulomb Counter ADC Conversion Complete */ ++#define CCADC_CONV_vect_num 17 ++#define CCADC_CONV_vect _VECTOR(17) ++ ++/* Coloumb Counter ADC Regular Current */ ++#define CCADC_REG_CUR_vect_num 18 ++#define CCADC_REG_CUR_vect _VECTOR(18) ++ ++/* Coloumb Counter ADC Accumulator */ ++#define CCADC_ACC_vect_num 19 ++#define CCADC_ACC_vect _VECTOR(19) ++ ++/* EEPROM Ready */ ++#define EE_READY_vect_num 20 ++#define EE_READY_vect _VECTOR(20) ++ ++#if defined (__AVR_ATmega16HVA__) ++# define _VECTORS_SIZE 84 ++#else ++# define _VECTORS_SIZE 42 ++#endif ++ ++ ++#endif /* _AVR_IOMXXHVA_H_ */ +diff --git a/include/avr/iotn10.h b/include/avr/iotn10.h +index 6c85f42..6cf838b 100644 +--- a/include/avr/iotn10.h ++++ b/include/avr/iotn10.h +@@ -1,503 +1,503 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn10.h 2063 2009-11-18 22:06:28Z arcanum $ */ +- +-/* avr/iotn10.h - definitions for ATtiny10 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn10.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATtiny10_H_ +-#define _AVR_ATtiny10_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINB _SFR_IO8(0x00) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +- +-#define DDRB _SFR_IO8(0x01) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +- +-#define PORTB _SFR_IO8(0x02) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +- +-#define PUEB _SFR_IO8(0x03) +-#define PUEB0 0 +-#define PUEB1 1 +-#define PUEB2 2 +-#define PUEB3 3 +- +-#define PORTCR _SFR_IO8(0x0C) +-#define BBMB 1 +- +-#define PCMSK _SFR_IO8(0x10) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +- +-#define PCIFR _SFR_IO8(0x11) +-#define PCIF0 0 +- +-#define PCICR _SFR_IO8(0x12) +-#define PCIE0 0 +- +-#define EIMSK _SFR_IO8(0x13) +-#define INT0 0 +- +-#define EIFR _SFR_IO8(0x14) +-#define INTF0 0 +- +-#define EICRA _SFR_IO8(0x15) +-#define ISC00 0 +-#define ISC01 1 +- +-#define DIDR0 _SFR_IO8(0x17) +-#define ADC0D 0 +-#define AIN0D 0 +-#define ADC1D 1 +-#define AIN1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +- +-#define ADCL _SFR_IO8(0x19) +-#define ADC0 0 +-#define ADC1 1 +-#define ADC2 2 +-#define ADC3 3 +-#define ADC4 4 +-#define ADC5 5 +-#define ADC6 6 +-#define ADC7 7 +- +-#define ADMUX _SFR_IO8(0x1B) +-#define MUX0 0 +-#define MUX1 1 +- +-#define ADCSRB _SFR_IO8(0x1C) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +- +-#define ADCSRA _SFR_IO8(0x1D) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ACSR _SFR_IO8(0x1F) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACD 7 +- +-#define ICR0 _SFR_IO16(0x22) +- +-#define ICR0L _SFR_IO8(0x22) +-#define ICR0_0 0 +-#define ICR0_1 1 +-#define ICR0_2 2 +-#define ICR0_3 3 +-#define ICR0_4 4 +-#define ICR0_5 5 +-#define ICR0_6 6 +-#define ICR0_7 7 +- +-#define ICR0H _SFR_IO8(0x23) +-#define ICR0_8 0 +-#define ICR0_9 1 +-#define ICR0_10 2 +-#define ICR0_11 3 +-#define ICR0_12 4 +-#define ICR0_13 5 +-#define ICR0_14 6 +-#define ICR0_15 7 +- +-#define OCR0B _SFR_IO16(0x24) +- +-#define OCR0BL _SFR_IO8(0x24) +-#define OCR0B0 0 +-#define OCR0B1 1 +-#define OCR0B2 2 +-#define OCR0B3 3 +-#define OCR0B4 4 +-#define OCR0B5 5 +-#define OCR0B6 6 +-#define OCR0B7 7 +- +-#define OCR0BH _SFR_IO8(0x25) +-#define OCR0B8 0 +-#define OCR0B9 1 +-#define OCR0B10 2 +-#define OCR0B11 3 +-#define OCR0B12 4 +-#define OCR0B13 5 +-#define OCR0B14 6 +-#define OCR0B15 7 +- +-#define OCR0A _SFR_IO16(0x26) +- +-#define OCR0AL _SFR_IO8(0x26) +-#define OCR0A0 0 +-#define OCR0A1 1 +-#define OCR0A2 2 +-#define OCR0A3 3 +-#define OCR0A4 4 +-#define OCR0A5 5 +-#define OCR0A6 6 +-#define OCR0A7 7 +- +-#define OCR0AH _SFR_IO8(0x27) +-#define OCR0A8 0 +-#define OCR0A9 1 +-#define OCR0A10 2 +-#define OCR0A11 3 +-#define OCR0A12 4 +-#define OCR0A13 5 +-#define OCR0A14 6 +-#define OCR0A15 7 +- +-#define TCNT0 _SFR_IO16(0x28) +- +-#define TCNT0L _SFR_IO8(0x28) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define TCNT0H _SFR_IO8(0x29) +-#define TCNT0_8 0 +-#define TCNT0_9 1 +-#define TCNT0_10 2 +-#define TCNT0_11 3 +-#define TCNT0_12 4 +-#define TCNT0_13 5 +-#define TCNT0_14 6 +-#define TCNT0_15 7 +- +-#define TIFR0 _SFR_IO8(0x2A) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +-#define ICF0 5 +- +-#define TIMSK0 _SFR_IO8(0x2B) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +-#define ICIE0 5 +- +-#define TCCR0C _SFR_IO8(0x2C) +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCCR0B _SFR_IO8(0x2D) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define WGM03 4 +-#define ICES0 6 +-#define ICNC0 7 +- +-#define TCCR0A _SFR_IO8(0x2E) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define GTCCR _SFR_IO8(0x2F) +-#define PSR 0 +-#define TSM 7 +- +-#define WDTCSR _SFR_IO8(0x31) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define NVMCSR _SFR_IO8(0x32) +-#define NVMBSY 7 +- +-#define NVMCMD _SFR_IO8(0x33) +-#define NVMCMD0 0 +-#define NVMCMD1 1 +-#define NVMCMD2 2 +-#define NVMCMD3 3 +-#define NVMCMD4 4 +-#define NVMCMD5 5 +- +-#define VLMCSR _SFR_IO8(0x34) +-#define VLM0 0 +-#define VLM1 1 +-#define VLM2 2 +-#define VLMIE 6 +-#define VLMF 7 +- +-#define PRR _SFR_IO8(0x35) +-#define PRTIM0 0 +-#define PRADC 1 +- +-#define CLKPSR _SFR_IO8(0x36) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +- +-#define CLKMSR _SFR_IO8(0x37) +-#define CLKMS0 0 +-#define CLKMS1 1 +- +-#define OSCCAL _SFR_IO8(0x39) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define SMCR _SFR_IO8(0x3A) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define RSTFLR _SFR_IO8(0x3B) +-#define PORF 0 +-#define EXTRF 1 +-#define WDRF 3 +- +-#define CCP _SFR_IO8(0x3C) +-#define CCP0 0 +-#define CCP1 1 +-#define CCP2 2 +-#define CCP3 3 +-#define CCP4 4 +-#define CCP5 5 +-#define CCP6 6 +-#define CCP7 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ +-#define TIM0_CAPT_vect_num 3 +-#define TIM0_CAPT_vect _VECTOR(3) /* Timer/Counter0 Input Capture */ +-#define TIM0_OVF_vect_num 4 +-#define TIM0_OVF_vect _VECTOR(4) /* Timer/Counter0 Overflow */ +-#define TIM0_COMPA_vect_num 5 +-#define TIM0_COMPA_vect _VECTOR(5) /* Timer/Counter Compare Match A */ +-#define TIM0_COMPB_vect_num 6 +-#define TIM0_COMPB_vect _VECTOR(6) /* Timer/Counter Compare Match B */ +-#define ANA_COMP_vect_num 7 +-#define ANA_COMP_vect _VECTOR(7) /* Analog Comparator */ +-#define WDT_vect_num 8 +-#define WDT_vect _VECTOR(8) /* Watchdog Time-out */ +-#define VLM_vect_num 9 +-#define VLM_vect _VECTOR(9) /* Vcc Voltage Level Monitor */ +-#define ADC_vect_num 10 +-#define ADC_vect _VECTOR(10) /* ADC Conversion Complete */ +- +-#define _VECTOR_SIZE 2 /* Size of individual vector. */ +-#define _VECTORS_SIZE (11 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (32) +-#define RAMSTART (0x40) +-#define RAMSIZE (32) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x0) +-#define E2PAGESIZE (0) +-#define FLASHEND (0x3FF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 0 +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x90 +-#define SIGNATURE_2 0x03 +- +- +-/* Device Pin Definitions */ +-#define SPDATA_DDR DDRCINT +-#define SPDATA_PORT PORTCINT +-#define SPDATA_PIN PINCINT +-#define SPDATA_BIT INT0 +- +-#define OC0A_DDR DDRCINT +-#define OC0A_PORT PORTCINT +-#define OC0A_PIN PINCINT +-#define OC0A_BIT INT0 +- +-#define ADC0_DDR DDRCINT +-#define ADC0_PORT PORTCINT +-#define ADC0_PIN PINCINT +-#define ADC0_BIT INT0 +- +-#define AIN0_DDR DDRCINT +-#define AIN0_PORT PORTCINT +-#define AIN0_PIN PINCINT +-#define AIN0_BIT INT0 +- +-#define PB0_DDR DDRCINT +-#define PB0_PORT PORTCINT +-#define PB0_PIN PINCINT +-#define PB0_BIT INT0 +- +-#define SPCLK_DDR DDRCINT +-#define SPCLK_PORT PORTCINT +-#define SPCLK_PIN PINCINT +-#define SPCLK_BIT INT1 +- +-#define CLKI_DDR DDRCINT +-#define CLKI_PORT PORTCINT +-#define CLKI_PIN PINCINT +-#define CLKI_BIT INT1 +- +-#define ICP0_DDR DDRCINT +-#define ICP0_PORT PORTCINT +-#define ICP0_PIN PINCINT +-#define ICP0_BIT INT1 +- +-#define OC0B_DDR DDRCINT +-#define OC0B_PORT PORTCINT +-#define OC0B_PIN PINCINT +-#define OC0B_BIT INT1 +- +-#define ADC1_DDR DDRCINT +-#define ADC1_PORT PORTCINT +-#define ADC1_PIN PINCINT +-#define ADC1_BIT INT1 +- +-#define AIN1_DDR DDRCINT +-#define AIN1_PORT PORTCINT +-#define AIN1_PIN PINCINT +-#define AIN1_BIT INT1 +- +-#define PB1_DDR DDRCINT +-#define PB1_PORT PORTCINT +-#define PB1_PIN PINCINT +-#define PB1_BIT INT1 +- +-#define CLKO_DDR DDRT +-#define CLKO_PORT PORTT +-#define CLKO_PIN PINT +-#define CLKO_BIT T0 +- +-#define PCINT2_DDR DDRT +-#define PCINT2_PORT PORTT +-#define PCINT2_PIN PINT +-#define PCINT2_BIT T0 +- +-#define INT0_DDR DDRT +-#define INT0_PORT PORTT +-#define INT0_PIN PINT +-#define INT0_BIT T0 +- +-#define ADC2_DDR DDRT +-#define ADC2_PORT PORTT +-#define ADC2_PIN PINT +-#define ADC2_BIT T0 +- +-#define PB2_DDR DDRT +-#define PB2_PORT PORTT +-#define PB2_PIN PINT +-#define PB2_BIT T0 +- +-#define PCINT3_DDR DDRRESET +-#define PCINT3_PORT PORTRESET +-#define PCINT3_PIN PINRESET +-#define PCINT3_BIT RESET +- +-#define ADC3_DDR DDRRESET +-#define ADC3_PORT PORTRESET +-#define ADC3_PIN PINRESET +-#define ADC3_BIT RESET +- +-#define PB3_DDR DDRRESET +-#define PB3_PORT PORTRESET +-#define PB3_PIN PINRESET +-#define PB3_BIT RESET +- +-#endif /* _AVR_ATtiny10_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn10.h 2063 2009-11-18 22:06:28Z arcanum $ */ ++ ++/* avr/iotn10.h - definitions for ATtiny10 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn10.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATtiny10_H_ ++#define _AVR_ATtiny10_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINB _SFR_IO8(0x00) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++ ++#define DDRB _SFR_IO8(0x01) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++ ++#define PORTB _SFR_IO8(0x02) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++ ++#define PUEB _SFR_IO8(0x03) ++#define PUEB0 0 ++#define PUEB1 1 ++#define PUEB2 2 ++#define PUEB3 3 ++ ++#define PORTCR _SFR_IO8(0x0C) ++#define BBMB 1 ++ ++#define PCMSK _SFR_IO8(0x10) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++ ++#define PCIFR _SFR_IO8(0x11) ++#define PCIF0 0 ++ ++#define PCICR _SFR_IO8(0x12) ++#define PCIE0 0 ++ ++#define EIMSK _SFR_IO8(0x13) ++#define INT0 0 ++ ++#define EIFR _SFR_IO8(0x14) ++#define INTF0 0 ++ ++#define EICRA _SFR_IO8(0x15) ++#define ISC00 0 ++#define ISC01 1 ++ ++#define DIDR0 _SFR_IO8(0x17) ++#define ADC0D 0 ++#define AIN0D 0 ++#define ADC1D 1 ++#define AIN1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++ ++#define ADCL _SFR_IO8(0x19) ++#define ADC0 0 ++#define ADC1 1 ++#define ADC2 2 ++#define ADC3 3 ++#define ADC4 4 ++#define ADC5 5 ++#define ADC6 6 ++#define ADC7 7 ++ ++#define ADMUX _SFR_IO8(0x1B) ++#define MUX0 0 ++#define MUX1 1 ++ ++#define ADCSRB _SFR_IO8(0x1C) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++ ++#define ADCSRA _SFR_IO8(0x1D) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ACSR _SFR_IO8(0x1F) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACD 7 ++ ++#define ICR0 _SFR_IO16(0x22) ++ ++#define ICR0L _SFR_IO8(0x22) ++#define ICR0_0 0 ++#define ICR0_1 1 ++#define ICR0_2 2 ++#define ICR0_3 3 ++#define ICR0_4 4 ++#define ICR0_5 5 ++#define ICR0_6 6 ++#define ICR0_7 7 ++ ++#define ICR0H _SFR_IO8(0x23) ++#define ICR0_8 0 ++#define ICR0_9 1 ++#define ICR0_10 2 ++#define ICR0_11 3 ++#define ICR0_12 4 ++#define ICR0_13 5 ++#define ICR0_14 6 ++#define ICR0_15 7 ++ ++#define OCR0B _SFR_IO16(0x24) ++ ++#define OCR0BL _SFR_IO8(0x24) ++#define OCR0B0 0 ++#define OCR0B1 1 ++#define OCR0B2 2 ++#define OCR0B3 3 ++#define OCR0B4 4 ++#define OCR0B5 5 ++#define OCR0B6 6 ++#define OCR0B7 7 ++ ++#define OCR0BH _SFR_IO8(0x25) ++#define OCR0B8 0 ++#define OCR0B9 1 ++#define OCR0B10 2 ++#define OCR0B11 3 ++#define OCR0B12 4 ++#define OCR0B13 5 ++#define OCR0B14 6 ++#define OCR0B15 7 ++ ++#define OCR0A _SFR_IO16(0x26) ++ ++#define OCR0AL _SFR_IO8(0x26) ++#define OCR0A0 0 ++#define OCR0A1 1 ++#define OCR0A2 2 ++#define OCR0A3 3 ++#define OCR0A4 4 ++#define OCR0A5 5 ++#define OCR0A6 6 ++#define OCR0A7 7 ++ ++#define OCR0AH _SFR_IO8(0x27) ++#define OCR0A8 0 ++#define OCR0A9 1 ++#define OCR0A10 2 ++#define OCR0A11 3 ++#define OCR0A12 4 ++#define OCR0A13 5 ++#define OCR0A14 6 ++#define OCR0A15 7 ++ ++#define TCNT0 _SFR_IO16(0x28) ++ ++#define TCNT0L _SFR_IO8(0x28) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define TCNT0H _SFR_IO8(0x29) ++#define TCNT0_8 0 ++#define TCNT0_9 1 ++#define TCNT0_10 2 ++#define TCNT0_11 3 ++#define TCNT0_12 4 ++#define TCNT0_13 5 ++#define TCNT0_14 6 ++#define TCNT0_15 7 ++ ++#define TIFR0 _SFR_IO8(0x2A) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++#define ICF0 5 ++ ++#define TIMSK0 _SFR_IO8(0x2B) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++#define ICIE0 5 ++ ++#define TCCR0C _SFR_IO8(0x2C) ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCCR0B _SFR_IO8(0x2D) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define WGM03 4 ++#define ICES0 6 ++#define ICNC0 7 ++ ++#define TCCR0A _SFR_IO8(0x2E) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define GTCCR _SFR_IO8(0x2F) ++#define PSR 0 ++#define TSM 7 ++ ++#define WDTCSR _SFR_IO8(0x31) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define NVMCSR _SFR_IO8(0x32) ++#define NVMBSY 7 ++ ++#define NVMCMD _SFR_IO8(0x33) ++#define NVMCMD0 0 ++#define NVMCMD1 1 ++#define NVMCMD2 2 ++#define NVMCMD3 3 ++#define NVMCMD4 4 ++#define NVMCMD5 5 ++ ++#define VLMCSR _SFR_IO8(0x34) ++#define VLM0 0 ++#define VLM1 1 ++#define VLM2 2 ++#define VLMIE 6 ++#define VLMF 7 ++ ++#define PRR _SFR_IO8(0x35) ++#define PRTIM0 0 ++#define PRADC 1 ++ ++#define CLKPSR _SFR_IO8(0x36) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++ ++#define CLKMSR _SFR_IO8(0x37) ++#define CLKMS0 0 ++#define CLKMS1 1 ++ ++#define OSCCAL _SFR_IO8(0x39) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define SMCR _SFR_IO8(0x3A) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define RSTFLR _SFR_IO8(0x3B) ++#define PORF 0 ++#define EXTRF 1 ++#define WDRF 3 ++ ++#define CCP _SFR_IO8(0x3C) ++#define CCP0 0 ++#define CCP1 1 ++#define CCP2 2 ++#define CCP3 3 ++#define CCP4 4 ++#define CCP5 5 ++#define CCP6 6 ++#define CCP7 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ ++#define TIM0_CAPT_vect_num 3 ++#define TIM0_CAPT_vect _VECTOR(3) /* Timer/Counter0 Input Capture */ ++#define TIM0_OVF_vect_num 4 ++#define TIM0_OVF_vect _VECTOR(4) /* Timer/Counter0 Overflow */ ++#define TIM0_COMPA_vect_num 5 ++#define TIM0_COMPA_vect _VECTOR(5) /* Timer/Counter Compare Match A */ ++#define TIM0_COMPB_vect_num 6 ++#define TIM0_COMPB_vect _VECTOR(6) /* Timer/Counter Compare Match B */ ++#define ANA_COMP_vect_num 7 ++#define ANA_COMP_vect _VECTOR(7) /* Analog Comparator */ ++#define WDT_vect_num 8 ++#define WDT_vect _VECTOR(8) /* Watchdog Time-out */ ++#define VLM_vect_num 9 ++#define VLM_vect _VECTOR(9) /* Vcc Voltage Level Monitor */ ++#define ADC_vect_num 10 ++#define ADC_vect _VECTOR(10) /* ADC Conversion Complete */ ++ ++#define _VECTOR_SIZE 2 /* Size of individual vector. */ ++#define _VECTORS_SIZE (11 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (32) ++#define RAMSTART (0x40) ++#define RAMSIZE (32) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x0) ++#define E2PAGESIZE (0) ++#define FLASHEND (0x3FF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 0 ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x90 ++#define SIGNATURE_2 0x03 ++ ++ ++/* Device Pin Definitions */ ++#define SPDATA_DDR DDRCINT ++#define SPDATA_PORT PORTCINT ++#define SPDATA_PIN PINCINT ++#define SPDATA_BIT INT0 ++ ++#define OC0A_DDR DDRCINT ++#define OC0A_PORT PORTCINT ++#define OC0A_PIN PINCINT ++#define OC0A_BIT INT0 ++ ++#define ADC0_DDR DDRCINT ++#define ADC0_PORT PORTCINT ++#define ADC0_PIN PINCINT ++#define ADC0_BIT INT0 ++ ++#define AIN0_DDR DDRCINT ++#define AIN0_PORT PORTCINT ++#define AIN0_PIN PINCINT ++#define AIN0_BIT INT0 ++ ++#define PB0_DDR DDRCINT ++#define PB0_PORT PORTCINT ++#define PB0_PIN PINCINT ++#define PB0_BIT INT0 ++ ++#define SPCLK_DDR DDRCINT ++#define SPCLK_PORT PORTCINT ++#define SPCLK_PIN PINCINT ++#define SPCLK_BIT INT1 ++ ++#define CLKI_DDR DDRCINT ++#define CLKI_PORT PORTCINT ++#define CLKI_PIN PINCINT ++#define CLKI_BIT INT1 ++ ++#define ICP0_DDR DDRCINT ++#define ICP0_PORT PORTCINT ++#define ICP0_PIN PINCINT ++#define ICP0_BIT INT1 ++ ++#define OC0B_DDR DDRCINT ++#define OC0B_PORT PORTCINT ++#define OC0B_PIN PINCINT ++#define OC0B_BIT INT1 ++ ++#define ADC1_DDR DDRCINT ++#define ADC1_PORT PORTCINT ++#define ADC1_PIN PINCINT ++#define ADC1_BIT INT1 ++ ++#define AIN1_DDR DDRCINT ++#define AIN1_PORT PORTCINT ++#define AIN1_PIN PINCINT ++#define AIN1_BIT INT1 ++ ++#define PB1_DDR DDRCINT ++#define PB1_PORT PORTCINT ++#define PB1_PIN PINCINT ++#define PB1_BIT INT1 ++ ++#define CLKO_DDR DDRT ++#define CLKO_PORT PORTT ++#define CLKO_PIN PINT ++#define CLKO_BIT T0 ++ ++#define PCINT2_DDR DDRT ++#define PCINT2_PORT PORTT ++#define PCINT2_PIN PINT ++#define PCINT2_BIT T0 ++ ++#define INT0_DDR DDRT ++#define INT0_PORT PORTT ++#define INT0_PIN PINT ++#define INT0_BIT T0 ++ ++#define ADC2_DDR DDRT ++#define ADC2_PORT PORTT ++#define ADC2_PIN PINT ++#define ADC2_BIT T0 ++ ++#define PB2_DDR DDRT ++#define PB2_PORT PORTT ++#define PB2_PIN PINT ++#define PB2_BIT T0 ++ ++#define PCINT3_DDR DDRRESET ++#define PCINT3_PORT PORTRESET ++#define PCINT3_PIN PINRESET ++#define PCINT3_BIT RESET ++ ++#define ADC3_DDR DDRRESET ++#define ADC3_PORT PORTRESET ++#define ADC3_PIN PINRESET ++#define ADC3_BIT RESET ++ ++#define PB3_DDR DDRRESET ++#define PB3_PORT PORTRESET ++#define PB3_PIN PINRESET ++#define PB3_BIT RESET ++ ++#endif /* _AVR_ATtiny10_H_ */ ++ +diff --git a/include/avr/iotn11.h b/include/avr/iotn11.h +index 42f8b1b..8f08db6 100644 +--- a/include/avr/iotn11.h ++++ b/include/avr/iotn11.h +@@ -1,252 +1,253 @@ +-/* Copyright (c) 2002,2005 Marek Michalkiewicz +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn11.h 2236 2011-03-17 21:53:39Z arcanum $ */ +- +-/* avr/iotn11.h - definitions for ATtiny10/11 */ +- +-#ifndef _AVR_IOTN11_H_ +-#define _AVR_IOTN11_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn11.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-#ifndef __ASSEMBLER__ +-# warning "MCU not supported by the C compiler" +-#endif +- +-/* I/O registers */ +- +-/* 0x00..0x07 reserved */ +- +-/* Analog Comparator Control and Status Register */ +-#define ACSR _SFR_IO8(0x08) +- +-/* 0x09..0x15 reserved */ +- +-/* Input Pins, Port B */ +-#define PINB _SFR_IO8(0x16) +- +-/* Data Direction Register, Port B */ +-#define DDRB _SFR_IO8(0x17) +- +-/* Data Register, Port B */ +-#define PORTB _SFR_IO8(0x18) +- +-/* 0x19..0x20 reserved */ +- +-/* Watchdog Timer Control Register */ +-#define WDTCR _SFR_IO8(0x21) +- +-/* 0x22..0x31 reserved */ +- +-/* Timer/Counter0 (8-bit) */ +-#define TCNT0 _SFR_IO8(0x32) +- +-/* Timer/Counter0 Control Register */ +-#define TCCR0 _SFR_IO8(0x33) +- +-/* MCU general Status Register */ +-#define MCUSR _SFR_IO8(0x34) +- +-/* MCU general Control Register */ +-#define MCUCR _SFR_IO8(0x35) +- +-/* 0x36..0x37 reserved */ +- +-/* Timer/Counter Interrupt Flag Register */ +-#define TIFR _SFR_IO8(0x38) +- +-/* Timer/Counter Interrupt MaSK Register */ +-#define TIMSK _SFR_IO8(0x39) +- +-/* General Interrupt Flag Register */ +-#define GIFR _SFR_IO8(0x3A) +- +-/* General Interrupt MaSK register */ +-#define GIMSK _SFR_IO8(0x3B) +- +-/* 0x3C..0x3E reserved */ +- +-/* 0x3F SREG */ +- +-/* Interrupt vectors */ +- +-/* External Interrupt 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt Request 0 */ +-#define IO_PINS_vect_num 2 +-#define IO_PINS_vect _VECTOR(2) +-#define SIG_PIN _VECTOR(2) +-#define SIG_PIN_CHANGE _VECTOR(2) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 3 +-#define TIMER0_OVF_vect _VECTOR(3) +-#define SIG_OVERFLOW0 _VECTOR(3) +- +-/* Analog Comparator */ +-#define ANA_COMP_vect_num 4 +-#define ANA_COMP_vect _VECTOR(4) +-#define SIG_COMPARATOR _VECTOR(4) +- +-#define _VECTORS_SIZE 10 +- +-/* Bit numbers */ +- +-/* GIMSK */ +-#define INT0 6 +-#define PCIE 5 +- +-/* GIFR */ +-#define INTF0 6 +-#define PCIF 5 +- +-/* TIMSK */ +-#define TOIE0 1 +- +-/* TIFR */ +-#define TOV0 1 +- +-/* MCUCR */ +-#define SE 5 +-#define SM 4 +-#define ISC01 1 +-#define ISC00 0 +- +-/* TCCR0 */ +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* WDTCR */ +-#define WDTOE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* +- PB5 = RESET# +- PB4 = XTAL2 +- PB3 = XTAL1 +- PB2 = T0 +- PB1 = INT0 / AIN1 +- PB0 = AIN0 +- */ +- +-/* PORTB */ +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* DDRB */ +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* PINB */ +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* ACSR */ +-#define ACD 7 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIS1 1 +-#define ACIS0 0 +- +-/* Last memory addresses */ +-#define RAMEND 0x1F +-#define XRAMEND 0x0 +-#define E2END 0x0 +-#define E2PAGESIZE 2 +-#define FLASHEND 0x3FF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 1 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_RSTDISBL (unsigned char)~_BV(3) +-#define FUSE_FSTRT (unsigned char)~_BV(4) +-#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL1) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x90 +-#define SIGNATURE_2 0x04 +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_PIN +-#pragma GCC poison SIG_PIN_CHANGE +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_COMPARATOR +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +-#endif /* _AVR_IOTN11_H_ */ ++/* Copyright (c) 2002,2005 Marek Michalkiewicz ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn11.h 2236 2011-03-17 21:53:39Z arcanum $ */ ++ ++/* avr/iotn11.h - definitions for ATtiny10/11 */ ++ ++#ifndef _AVR_IOTN11_H_ ++#define _AVR_IOTN11_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn11.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef __ASSEMBLER__ ++# warning "MCU not supported by the C compiler" ++#endif ++ ++/* I/O registers */ ++ ++/* 0x00..0x07 reserved */ ++ ++/* Analog Comparator Control and Status Register */ ++#define ACSR _SFR_IO8(0x08) ++ ++/* 0x09..0x15 reserved */ ++ ++/* Input Pins, Port B */ ++#define PINB _SFR_IO8(0x16) ++ ++/* Data Direction Register, Port B */ ++#define DDRB _SFR_IO8(0x17) ++ ++/* Data Register, Port B */ ++#define PORTB _SFR_IO8(0x18) ++ ++/* 0x19..0x20 reserved */ ++ ++/* Watchdog Timer Control Register */ ++#define WDTCR _SFR_IO8(0x21) ++ ++/* 0x22..0x31 reserved */ ++ ++/* Timer/Counter0 (8-bit) */ ++#define TCNT0 _SFR_IO8(0x32) ++ ++/* Timer/Counter0 Control Register */ ++#define TCCR0 _SFR_IO8(0x33) ++ ++/* MCU general Status Register */ ++#define MCUSR _SFR_IO8(0x34) ++ ++/* MCU general Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++ ++/* 0x36..0x37 reserved */ ++ ++/* Timer/Counter Interrupt Flag Register */ ++#define TIFR _SFR_IO8(0x38) ++ ++/* Timer/Counter Interrupt MaSK Register */ ++#define TIMSK _SFR_IO8(0x39) ++ ++/* General Interrupt Flag Register */ ++#define GIFR _SFR_IO8(0x3A) ++ ++/* General Interrupt MaSK register */ ++#define GIMSK _SFR_IO8(0x3B) ++ ++/* 0x3C..0x3E reserved */ ++ ++/* 0x3F SREG */ ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt Request 0 */ ++#define IO_PINS_vect_num 2 ++#define IO_PINS_vect _VECTOR(2) ++#define SIG_PIN _VECTOR(2) ++#define SIG_PIN_CHANGE _VECTOR(2) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 3 ++#define TIMER0_OVF_vect _VECTOR(3) ++#define SIG_OVERFLOW0 _VECTOR(3) ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect_num 4 ++#define ANA_COMP_vect _VECTOR(4) ++#define SIG_COMPARATOR _VECTOR(4) ++ ++#define _VECTORS_SIZE 10 ++ ++/* Bit numbers */ ++ ++/* GIMSK */ ++#define INT0 6 ++#define PCIE 5 ++ ++/* GIFR */ ++#define INTF0 6 ++#define PCIF 5 ++ ++/* TIMSK */ ++#define TOIE0 1 ++ ++/* TIFR */ ++#define TOV0 1 ++ ++/* MCUCR */ ++#define SE 5 ++#define SM 4 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* TCCR0 */ ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* WDTCR */ ++#define WDTOE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* ++ PB5 = RESET# ++ PB4 = XTAL2 ++ PB3 = XTAL1 ++ PB2 = T0 ++ PB1 = INT0 / AIN1 ++ PB0 = AIN0 ++ */ ++ ++/* PORTB */ ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* DDRB */ ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* PINB */ ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* ACSR */ ++#define ACD 7 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++#define RAMSTART 0x60 ++/* Last memory addresses */ ++#define RAMEND 0x1F ++#define XRAMEND 0x0 ++#define E2END 0x0 ++#define E2PAGESIZE 2 ++#define FLASHEND 0x3FF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_RSTDISBL (unsigned char)~_BV(3) ++#define FUSE_FSTRT (unsigned char)~_BV(4) ++#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL1) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x90 ++#define SIGNATURE_2 0x04 ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_PIN ++#pragma GCC poison SIG_PIN_CHANGE ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_COMPARATOR ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++#endif /* _AVR_IOTN11_H_ */ +diff --git a/include/avr/iotn12.h b/include/avr/iotn12.h +index 2b051b2..6373c71 100644 +--- a/include/avr/iotn12.h ++++ b/include/avr/iotn12.h +@@ -1,285 +1,286 @@ +-/* Copyright (c) 2002,2005 Marek Michalkiewicz +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn12.h 2236 2011-03-17 21:53:39Z arcanum $ */ +- +-/* avr/iotn12.h - definitions for ATtiny12 */ +- +-#ifndef _AVR_IOTN12_H_ +-#define _AVR_IOTN12_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn12.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-#ifndef __ASSEMBLER__ +-# warning "MCU not supported by the C compiler" +-#endif +- +-/* I/O registers */ +- +-/* 0x00..0x07 reserved */ +- +-/* Analog Comparator Control and Status Register */ +-#define ACSR _SFR_IO8(0x08) +- +-/* 0x09..0x15 reserved */ +- +-/* Input Pins, Port B */ +-#define PINB _SFR_IO8(0x16) +- +-/* Data Direction Register, Port B */ +-#define DDRB _SFR_IO8(0x17) +- +-/* Data Register, Port B */ +-#define PORTB _SFR_IO8(0x18) +- +-/* 0x19..0x1B reserved */ +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO8(0x1E) +-#define EEARL _SFR_IO8(0x1E) +- +-/* 0x1F..0x20 reserved */ +- +-/* Watchdog Timer Control Register */ +-#define WDTCR _SFR_IO8(0x21) +- +-/* 0x22..0x30 reserved */ +- +-/* Oscillator Calibration Register */ +-#define OSCCAL _SFR_IO8(0x31) +- +-/* Timer/Counter0 (8-bit) */ +-#define TCNT0 _SFR_IO8(0x32) +- +-/* Timer/Counter0 Control Register */ +-#define TCCR0 _SFR_IO8(0x33) +- +-/* MCU general Status Register */ +-#define MCUSR _SFR_IO8(0x34) +- +-/* MCU general Control Register */ +-#define MCUCR _SFR_IO8(0x35) +- +-/* 0x36..0x37 reserved */ +- +-/* Timer/Counter Interrupt Flag Register */ +-#define TIFR _SFR_IO8(0x38) +- +-/* Timer/Counter Interrupt MaSK Register */ +-#define TIMSK _SFR_IO8(0x39) +- +-/* General Interrupt Flag Register */ +-#define GIFR _SFR_IO8(0x3A) +- +-/* General Interrupt MaSK register */ +-#define GIMSK _SFR_IO8(0x3B) +- +-/* 0x3C..0x3E reserved */ +- +-/* 0x3F SREG */ +- +-/* Interrupt vectors */ +- +-/* External Interrupt 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt Request 0 */ +-#define IO_PINS_vect_num 2 +-#define IO_PINS_vect _VECTOR(2) +-#define SIG_PIN _VECTOR(2) +-#define SIG_PIN_CHANGE _VECTOR(2) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 3 +-#define TIMER0_OVF_vect _VECTOR(3) +-#define SIG_OVERFLOW0 _VECTOR(3) +- +-/* EEPROM Ready */ +-#define EE_RDY_vect_num 4 +-#define EE_RDY_vect _VECTOR(4) +-#define SIG_EEPROM_READY _VECTOR(4) +- +-/* Analog Comparator */ +-#define ANA_COMP_vect_num 5 +-#define ANA_COMP_vect _VECTOR(5) +-#define SIG_COMPARATOR _VECTOR(5) +- +-#define _VECTORS_SIZE 12 +- +-/* Bit numbers */ +- +-/* GIMSK */ +-#define INT0 6 +-#define PCIE 5 +- +-/* GIFR */ +-#define INTF0 6 +-#define PCIF 5 +- +-/* TIMSK */ +-#define TOIE0 1 +- +-/* TIFR */ +-#define TOV0 1 +- +-/* MCUCR */ +-#define PUD 6 +-#define SE 5 +-#define SM 4 +-#define ISC01 1 +-#define ISC00 0 +- +-/* TCCR0 */ +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* WDTCR */ +-#define WDTOE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* +- PB5 = RESET# +- PB4 = XTAL2 +- PB3 = XTAL1 +- PB2 = T0 / SCK +- PB1 = INT0 / AIN1 / MISO +- PB0 = AIN0 / MOSI +- */ +- +-/* PORTB */ +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* DDRB */ +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* PINB */ +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* ACSR */ +-#define ACD 7 +-#define AINBG 6 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIS1 1 +-#define ACIS0 0 +- +-/* EEPROM Control Register */ +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-/* Last memory addresses */ +-#define RAMEND 0x1F +-#define XRAMEND 0x0 +-#define E2END 0x3F +-#define E2PAGESIZE 2 +-#define FLASHEND 0x3FF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 1 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_RSTDISBL (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_BODEN (unsigned char)~_BV(6) +-#define FUSE_BODLEVEL (unsigned char)~_BV(7) +-#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SPIEN & FUSE_BODLEVEL) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x90 +-#define SIGNATURE_2 0x05 +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_PIN +-#pragma GCC poison SIG_PIN_CHANGE +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_COMPARATOR +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +-#endif /* _AVR_IOTN12_H_ */ ++/* Copyright (c) 2002,2005 Marek Michalkiewicz ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn12.h 2236 2011-03-17 21:53:39Z arcanum $ */ ++ ++/* avr/iotn12.h - definitions for ATtiny12 */ ++ ++#ifndef _AVR_IOTN12_H_ ++#define _AVR_IOTN12_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn12.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef __ASSEMBLER__ ++# warning "MCU not supported by the C compiler" ++#endif ++ ++/* I/O registers */ ++ ++/* 0x00..0x07 reserved */ ++ ++/* Analog Comparator Control and Status Register */ ++#define ACSR _SFR_IO8(0x08) ++ ++/* 0x09..0x15 reserved */ ++ ++/* Input Pins, Port B */ ++#define PINB _SFR_IO8(0x16) ++ ++/* Data Direction Register, Port B */ ++#define DDRB _SFR_IO8(0x17) ++ ++/* Data Register, Port B */ ++#define PORTB _SFR_IO8(0x18) ++ ++/* 0x19..0x1B reserved */ ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO8(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++ ++/* 0x1F..0x20 reserved */ ++ ++/* Watchdog Timer Control Register */ ++#define WDTCR _SFR_IO8(0x21) ++ ++/* 0x22..0x30 reserved */ ++ ++/* Oscillator Calibration Register */ ++#define OSCCAL _SFR_IO8(0x31) ++ ++/* Timer/Counter0 (8-bit) */ ++#define TCNT0 _SFR_IO8(0x32) ++ ++/* Timer/Counter0 Control Register */ ++#define TCCR0 _SFR_IO8(0x33) ++ ++/* MCU general Status Register */ ++#define MCUSR _SFR_IO8(0x34) ++ ++/* MCU general Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++ ++/* 0x36..0x37 reserved */ ++ ++/* Timer/Counter Interrupt Flag Register */ ++#define TIFR _SFR_IO8(0x38) ++ ++/* Timer/Counter Interrupt MaSK Register */ ++#define TIMSK _SFR_IO8(0x39) ++ ++/* General Interrupt Flag Register */ ++#define GIFR _SFR_IO8(0x3A) ++ ++/* General Interrupt MaSK register */ ++#define GIMSK _SFR_IO8(0x3B) ++ ++/* 0x3C..0x3E reserved */ ++ ++/* 0x3F SREG */ ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt Request 0 */ ++#define IO_PINS_vect_num 2 ++#define IO_PINS_vect _VECTOR(2) ++#define SIG_PIN _VECTOR(2) ++#define SIG_PIN_CHANGE _VECTOR(2) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 3 ++#define TIMER0_OVF_vect _VECTOR(3) ++#define SIG_OVERFLOW0 _VECTOR(3) ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect_num 4 ++#define EE_RDY_vect _VECTOR(4) ++#define SIG_EEPROM_READY _VECTOR(4) ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect_num 5 ++#define ANA_COMP_vect _VECTOR(5) ++#define SIG_COMPARATOR _VECTOR(5) ++ ++#define _VECTORS_SIZE 12 ++ ++/* Bit numbers */ ++ ++/* GIMSK */ ++#define INT0 6 ++#define PCIE 5 ++ ++/* GIFR */ ++#define INTF0 6 ++#define PCIF 5 ++ ++/* TIMSK */ ++#define TOIE0 1 ++ ++/* TIFR */ ++#define TOV0 1 ++ ++/* MCUCR */ ++#define PUD 6 ++#define SE 5 ++#define SM 4 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* TCCR0 */ ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* WDTCR */ ++#define WDTOE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* ++ PB5 = RESET# ++ PB4 = XTAL2 ++ PB3 = XTAL1 ++ PB2 = T0 / SCK ++ PB1 = INT0 / AIN1 / MISO ++ PB0 = AIN0 / MOSI ++ */ ++ ++/* PORTB */ ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* DDRB */ ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* PINB */ ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* ACSR */ ++#define ACD 7 ++#define AINBG 6 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++/* EEPROM Control Register */ ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++#define RAMSTART 0x60 ++/* Last memory addresses */ ++#define RAMEND 0x1F ++#define XRAMEND 0x0 ++#define E2END 0x3F ++#define E2PAGESIZE 2 ++#define FLASHEND 0x3FF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_BODEN (unsigned char)~_BV(6) ++#define FUSE_BODLEVEL (unsigned char)~_BV(7) ++#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SPIEN & FUSE_BODLEVEL) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x90 ++#define SIGNATURE_2 0x05 ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_PIN ++#pragma GCC poison SIG_PIN_CHANGE ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_COMPARATOR ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++#endif /* _AVR_IOTN12_H_ */ +diff --git a/include/avr/iotn13.h b/include/avr/iotn13.h +index aba7ffe..3211823 100644 +--- a/include/avr/iotn13.h ++++ b/include/avr/iotn13.h +@@ -1,392 +1,392 @@ +-/* Copyright (c) 2004, Theodore A. Roth +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn13.h 2236 2011-03-17 21:53:39Z arcanum $ */ +- +-/* avr/iotn13.h - definitions for ATtiny13 */ +- +-/* Verified 5/20/04 by Bruce Graham */ +- +-#ifndef _AVR_IOTN13_H_ +-#define _AVR_IOTN13_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn13.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers and bit names */ +- +-/* ADC Control and Status Register B */ +-#define ADCSRB _SFR_IO8(0x03) +-# define ACME 6 +-# define ADTS2 2 +-# define ADTS1 1 +-# define ADTS0 0 +- +-/* ADC Data Register */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16 (0x04) +-#endif +-#define ADCW _SFR_IO16 (0x04) +-#define ADCL _SFR_IO8(0x04) +-#define ADCH _SFR_IO8(0x05) +- +-/* ADC Control and Status Register A */ +-#define ADCSRA _SFR_IO8(0x06) +-# define ADEN 7 +-# define ADSC 6 +-# define ADATE 5 +-# define ADIF 4 +-# define ADIE 3 +-# define ADPS2 2 +-# define ADPS1 1 +-# define ADPS0 0 +- +-/* ADC Multiplex Selection Register */ +-#define ADMUX _SFR_IO8(0x07) +-# define REFS0 6 +-# define ADLAR 5 +-# define MUX1 1 +-# define MUX0 0 +- +-/* Analog Comparator Control and Status Register */ +-#define ACSR _SFR_IO8(0x08) +-# define ACD 7 +-# define ACBG 6 +-# define ACO 5 +-# define ACI 4 +-# define ACIE 3 +-# define ACIS1 1 +-# define ACIS0 0 +- +-/* Digital Input Disable Register 0 */ +-#define DIDR0 _SFR_IO8(0x14) +-# define ADC0D 5 +-# define ADC2D 4 +-# define ADC3D 3 +-# define ADC1D 2 +-# define AIN1D 1 +-# define AIN0D 0 +- +-/* PIN Change Mask Register */ +-#define PCMSK _SFR_IO8(0x15) +-# define PCINT5 5 +-# define PCINT4 4 +-# define PCINT3 3 +-# define PCINT2 2 +-# define PCINT1 1 +-# define PCINT0 0 +- +-/* Port B Pin Utilization [2535D-AVR-04/04] +- - PORTB5 = PCINT5/RESET#/ADC0/dW +- - PORTB4 = PCINT4/ADC2 +- - PORTB3 = PCINT3/CLKI/ADC3 +- - PORTB2 = SCK/ADC1/T0/PCINT2 +- - PORTB1 = MISO/AIN1/OC0B/INT0/PCINT1 +- - PORTB0 = MOSI/AIN0/OC0A/PCINT0 */ +- +-/* Input Pins, Port B */ +-#define PINB _SFR_IO8(0x16) +-# define PINB5 5 +-# define PINB4 4 +-# define PINB3 3 +-# define PINB2 2 +-# define PINB1 1 +-# define PINB0 0 +- +-/* Data Direction Register, Port B */ +-#define DDRB _SFR_IO8(0x17) +-# define DDB5 5 +-# define DDB4 4 +-# define DDB3 3 +-# define DDB2 2 +-# define DDB1 1 +-# define DDB0 0 +- +-/* Data Register, Port B */ +-#define PORTB _SFR_IO8(0x18) +-# define PB5 5 +-# define PB4 4 +-# define PB3 3 +-# define PB2 2 +-# define PB1 1 +-# define PB0 0 +- +-/* ATtiny EEPROM Control Register EECR */ +-#define EECR _SFR_IO8(0x1C) +-#define EEPM1 5 +-#define EEPM0 4 +-#define EERIE 3 +-#define EEMPE 2 +-#define EEPE 1 +-#define EERE 0 +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* The EEPROM Address Register EEAR[6:0] */ +-#define EEAR _SFR_IO8(0x1E) +-#define EEARL _SFR_IO8(0x1E) +- +-/* Watchdog Timer Control Register */ +-#define WDTCR _SFR_IO8(0x21) +-# define WDTIF 7 +-# define WDTIE 6 +-# define WDP3 5 +-# define WDCE 4 +-# define WDE 3 +-# define WDP2 2 +-# define WDP1 1 +-# define WDP0 0 +- +-/* Clock Prescale Register */ +-#define CLKPR _SFR_IO8(0x26) +-# define CLKPCE 7 +-# define CLKPS3 3 +-# define CLKPS2 2 +-# define CLKPS1 1 +-# define CLKPS0 0 +- +-/* General Timer/Counter Control Register */ +-#define GTCCR _SFR_IO8(0x28) +-# define TSM 7 +-# define PSR10 0 +- +-/* Output Compare 0 Register B */ +-#define OCR0B _SFR_IO8(0x29) +- +-/* debugWIRE Data Register */ +-#define DWDR _SFR_IO8(0x2e) +- +-/* Timer/Counter 0 Control Register A */ +-#define TCCR0A _SFR_IO8(0x2f) +-# define COM0A1 7 +-# define COM0A0 6 +-# define COM0B1 5 +-# define COM0B0 4 +-# define WGM01 1 +-# define WGM00 0 +- +-/* Oscillator Calibration Register */ +-#define OSCCAL _SFR_IO8(0x31) +- +-/* Timer/Counter0 (8-bit) */ +-#define TCNT0 _SFR_IO8(0x32) +- +-/* Timer/Counter 0 Control Register B */ +-#define TCCR0B _SFR_IO8(0x33) +-# define FOC0A 7 +-# define FOC0B 6 +-# define WGM02 3 +-# define CS02 2 +-# define CS01 1 +-# define CS00 0 +- +-/* MCU General Status Register */ +-#define MCUSR _SFR_IO8(0x34) +-# define WDRF 3 +-# define BORF 2 +-# define EXTRF 1 +-# define PORF 0 +- +-/* MCU General Control Register */ +-#define MCUCR _SFR_IO8(0x35) +-# define PUD 6 +-# define SE 5 +-# define SM1 4 +-# define SM0 3 +-# define ISC01 1 +-# define ISC00 0 +- +-/* Output Compare 0 REgister A */ +-#define OCR0A _SFR_IO8(0x36) +- +-/* Store Program Memory Control and Status Register */ +-#define SPMCSR _SFR_IO8(0x37) +-# define CTPB 4 +-# define RFLB 3 +-# define PGWRT 2 +-# define PGERS 1 +-# define SPMEN 0 +-# define SELFPRGEN 0 +- +-/* Timer/Counter 0 Interrupt Flag Register */ +-#define TIFR0 _SFR_IO8(0x38) +-# define OCF0B 3 +-# define OCF0A 2 +-# define TOV0 1 +- +-/* Timer/Counter 0 Interrupt MaSK Register */ +-#define TIMSK0 _SFR_IO8(0x39) +-# define OCIE0B 3 +-# define OCIE0A 2 +-# define TOIE0 1 +- +-/* General Interrupt Flag Register */ +-#define GIFR _SFR_IO8(0x3a) +-# define INTF0 6 +-# define PCIF 5 +- +-/* General Interrupt MaSK register */ +-#define GIMSK _SFR_IO8(0x3b) +-# define INT0 6 +-# define PCIE 5 +- +-/* SPL and SREG are defined in */ +- +-/* From the datasheet: +- 1 0x0000 RESET External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset +- 2 0x0001 INT0 External Interrupt Request 0 +- 3 0x0002 PCINT0 Pin Change Interrupt Request 0 +- 4 0x0003 TIM0_OVF Timer/Counter Overflow +- 5 0x0004 EE_RDY EEPROM Ready +- 6 0x0005 ANA_COMP Analog Comparator +- 7 0x0006 TIM0_COMPA Timer/Counter Compare Match A +- 8 0x0007 TIM0_COMPB Timer/Counter Compare Match B +- 9 0x0008 WDT Watchdog Time-out +- 10 0x0009 ADC ADC Conversion Complete */ +- +-/* External Interrupt 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt Request 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) +-#define SIG_PIN_CHANGE0 _VECTOR(2) +- +-/* Timer/Counter0 Overflow */ +-#define TIM0_OVF_vect_num 3 +-#define TIM0_OVF_vect _VECTOR(3) +-#define SIG_OVERFLOW0 _VECTOR(3) +- +-/* EEPROM Ready */ +-#define EE_RDY_vect_num 4 +-#define EE_RDY_vect _VECTOR(4) +-#define SIG_EEPROM_READY _VECTOR(4) +- +-/* Analog Comparator */ +-#define ANA_COMP_vect_num 5 +-#define ANA_COMP_vect _VECTOR(5) +-#define SIG_COMPARATOR _VECTOR(5) +- +-/* Timer/Counter Compare Match A */ +-#define TIM0_COMPA_vect_num 6 +-#define TIM0_COMPA_vect _VECTOR(6) +-#define SIG_OUTPUT_COMPARE0A _VECTOR(6) +- +-/* Timer/Counter Compare Match B */ +-#define TIM0_COMPB_vect_num 7 +-#define TIM0_COMPB_vect _VECTOR(7) +-#define SIG_OUTPUT_COMPARE0B _VECTOR(7) +- +-/* Watchdog Time-out */ +-#define WDT_vect_num 8 +-#define WDT_vect _VECTOR(8) +-#define SIG_WATCHDOG_TIMEOUT _VECTOR(8) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 9 +-#define ADC_vect _VECTOR(9) +-#define SIG_ADC _VECTOR(9) +- +-#define _VECTORS_SIZE 20 +- +-#define SPM_PAGESIZE 32 +-#define RAMSTART (0x60) +-#define RAMEND 0x9F +-#define XRAMEND RAMEND +-#define E2END 0x3F +-#define E2PAGESIZE 4 +-#define FLASHEND 0x3FF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 2 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_SUT0 (unsigned char)~_BV(2) +-#define FUSE_SUT1 (unsigned char)~_BV(3) +-#define FUSE_CKDIV8 (unsigned char)~_BV(4) +-#define FUSE_WDTON (unsigned char)~_BV(5) +-#define FUSE_EESAVE (unsigned char)~_BV(6) +-#define FUSE_SPIEN (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_SUT0 & FUSE_CKDIV8 & FUSE_SPIEN) +- +-/* High Fuse Byte */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) +-#define FUSE_DWEN (unsigned char)~_BV(3) +-#define FUSE_SPMEN (unsigned char)~_BV(4) +-#define HFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x90 +-#define SIGNATURE_2 0x07 +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_PIN_CHANGE0 +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_OUTPUT_COMPARE0A +-#pragma GCC poison SIG_OUTPUT_COMPARE0B +-#pragma GCC poison SIG_WATCHDOG_TIMEOUT +-#pragma GCC poison SIG_ADC +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +-#endif /* _AVR_IOTN13_H_*/ ++/* Copyright (c) 2004, Theodore A. Roth ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn13.h 2236 2011-03-17 21:53:39Z arcanum $ */ ++ ++/* avr/iotn13.h - definitions for ATtiny13 */ ++ ++/* Verified 5/20/04 by Bruce Graham */ ++ ++#ifndef _AVR_IOTN13_H_ ++#define _AVR_IOTN13_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn13.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers and bit names */ ++ ++/* ADC Control and Status Register B */ ++#define ADCSRB _SFR_IO8(0x03) ++# define ACME 6 ++# define ADTS2 2 ++# define ADTS1 1 ++# define ADTS0 0 ++ ++/* ADC Data Register */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16 (0x04) ++#endif ++#define ADCW _SFR_IO16 (0x04) ++#define ADCL _SFR_IO8(0x04) ++#define ADCH _SFR_IO8(0x05) ++ ++/* ADC Control and Status Register A */ ++#define ADCSRA _SFR_IO8(0x06) ++# define ADEN 7 ++# define ADSC 6 ++# define ADATE 5 ++# define ADIF 4 ++# define ADIE 3 ++# define ADPS2 2 ++# define ADPS1 1 ++# define ADPS0 0 ++ ++/* ADC Multiplex Selection Register */ ++#define ADMUX _SFR_IO8(0x07) ++# define REFS0 6 ++# define ADLAR 5 ++# define MUX1 1 ++# define MUX0 0 ++ ++/* Analog Comparator Control and Status Register */ ++#define ACSR _SFR_IO8(0x08) ++# define ACD 7 ++# define ACBG 6 ++# define ACO 5 ++# define ACI 4 ++# define ACIE 3 ++# define ACIS1 1 ++# define ACIS0 0 ++ ++/* Digital Input Disable Register 0 */ ++#define DIDR0 _SFR_IO8(0x14) ++# define ADC0D 5 ++# define ADC2D 4 ++# define ADC3D 3 ++# define ADC1D 2 ++# define AIN1D 1 ++# define AIN0D 0 ++ ++/* PIN Change Mask Register */ ++#define PCMSK _SFR_IO8(0x15) ++# define PCINT5 5 ++# define PCINT4 4 ++# define PCINT3 3 ++# define PCINT2 2 ++# define PCINT1 1 ++# define PCINT0 0 ++ ++/* Port B Pin Utilization [2535D-AVR-04/04] ++ - PORTB5 = PCINT5/RESET#/ADC0/dW ++ - PORTB4 = PCINT4/ADC2 ++ - PORTB3 = PCINT3/CLKI/ADC3 ++ - PORTB2 = SCK/ADC1/T0/PCINT2 ++ - PORTB1 = MISO/AIN1/OC0B/INT0/PCINT1 ++ - PORTB0 = MOSI/AIN0/OC0A/PCINT0 */ ++ ++/* Input Pins, Port B */ ++#define PINB _SFR_IO8(0x16) ++# define PINB5 5 ++# define PINB4 4 ++# define PINB3 3 ++# define PINB2 2 ++# define PINB1 1 ++# define PINB0 0 ++ ++/* Data Direction Register, Port B */ ++#define DDRB _SFR_IO8(0x17) ++# define DDB5 5 ++# define DDB4 4 ++# define DDB3 3 ++# define DDB2 2 ++# define DDB1 1 ++# define DDB0 0 ++ ++/* Data Register, Port B */ ++#define PORTB _SFR_IO8(0x18) ++# define PB5 5 ++# define PB4 4 ++# define PB3 3 ++# define PB2 2 ++# define PB1 1 ++# define PB0 0 ++ ++/* ATtiny EEPROM Control Register EECR */ ++#define EECR _SFR_IO8(0x1C) ++#define EEPM1 5 ++#define EEPM0 4 ++#define EERIE 3 ++#define EEMPE 2 ++#define EEPE 1 ++#define EERE 0 ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* The EEPROM Address Register EEAR[6:0] */ ++#define EEAR _SFR_IO8(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++ ++/* Watchdog Timer Control Register */ ++#define WDTCR _SFR_IO8(0x21) ++# define WDTIF 7 ++# define WDTIE 6 ++# define WDP3 5 ++# define WDCE 4 ++# define WDE 3 ++# define WDP2 2 ++# define WDP1 1 ++# define WDP0 0 ++ ++/* Clock Prescale Register */ ++#define CLKPR _SFR_IO8(0x26) ++# define CLKPCE 7 ++# define CLKPS3 3 ++# define CLKPS2 2 ++# define CLKPS1 1 ++# define CLKPS0 0 ++ ++/* General Timer/Counter Control Register */ ++#define GTCCR _SFR_IO8(0x28) ++# define TSM 7 ++# define PSR10 0 ++ ++/* Output Compare 0 Register B */ ++#define OCR0B _SFR_IO8(0x29) ++ ++/* debugWIRE Data Register */ ++#define DWDR _SFR_IO8(0x2e) ++ ++/* Timer/Counter 0 Control Register A */ ++#define TCCR0A _SFR_IO8(0x2f) ++# define COM0A1 7 ++# define COM0A0 6 ++# define COM0B1 5 ++# define COM0B0 4 ++# define WGM01 1 ++# define WGM00 0 ++ ++/* Oscillator Calibration Register */ ++#define OSCCAL _SFR_IO8(0x31) ++ ++/* Timer/Counter0 (8-bit) */ ++#define TCNT0 _SFR_IO8(0x32) ++ ++/* Timer/Counter 0 Control Register B */ ++#define TCCR0B _SFR_IO8(0x33) ++# define FOC0A 7 ++# define FOC0B 6 ++# define WGM02 3 ++# define CS02 2 ++# define CS01 1 ++# define CS00 0 ++ ++/* MCU General Status Register */ ++#define MCUSR _SFR_IO8(0x34) ++# define WDRF 3 ++# define BORF 2 ++# define EXTRF 1 ++# define PORF 0 ++ ++/* MCU General Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++# define PUD 6 ++# define SE 5 ++# define SM1 4 ++# define SM0 3 ++# define ISC01 1 ++# define ISC00 0 ++ ++/* Output Compare 0 REgister A */ ++#define OCR0A _SFR_IO8(0x36) ++ ++/* Store Program Memory Control and Status Register */ ++#define SPMCSR _SFR_IO8(0x37) ++# define CTPB 4 ++# define RFLB 3 ++# define PGWRT 2 ++# define PGERS 1 ++# define SPMEN 0 ++# define SELFPRGEN 0 ++ ++/* Timer/Counter 0 Interrupt Flag Register */ ++#define TIFR0 _SFR_IO8(0x38) ++# define OCF0B 3 ++# define OCF0A 2 ++# define TOV0 1 ++ ++/* Timer/Counter 0 Interrupt MaSK Register */ ++#define TIMSK0 _SFR_IO8(0x39) ++# define OCIE0B 3 ++# define OCIE0A 2 ++# define TOIE0 1 ++ ++/* General Interrupt Flag Register */ ++#define GIFR _SFR_IO8(0x3a) ++# define INTF0 6 ++# define PCIF 5 ++ ++/* General Interrupt MaSK register */ ++#define GIMSK _SFR_IO8(0x3b) ++# define INT0 6 ++# define PCIE 5 ++ ++/* SPL and SREG are defined in */ ++ ++/* From the datasheet: ++ 1 0x0000 RESET External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset ++ 2 0x0001 INT0 External Interrupt Request 0 ++ 3 0x0002 PCINT0 Pin Change Interrupt Request 0 ++ 4 0x0003 TIM0_OVF Timer/Counter Overflow ++ 5 0x0004 EE_RDY EEPROM Ready ++ 6 0x0005 ANA_COMP Analog Comparator ++ 7 0x0006 TIM0_COMPA Timer/Counter Compare Match A ++ 8 0x0007 TIM0_COMPB Timer/Counter Compare Match B ++ 9 0x0008 WDT Watchdog Time-out ++ 10 0x0009 ADC ADC Conversion Complete */ ++ ++/* External Interrupt 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt Request 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) ++#define SIG_PIN_CHANGE0 _VECTOR(2) ++ ++/* Timer/Counter0 Overflow */ ++#define TIM0_OVF_vect_num 3 ++#define TIM0_OVF_vect _VECTOR(3) ++#define SIG_OVERFLOW0 _VECTOR(3) ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect_num 4 ++#define EE_RDY_vect _VECTOR(4) ++#define SIG_EEPROM_READY _VECTOR(4) ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect_num 5 ++#define ANA_COMP_vect _VECTOR(5) ++#define SIG_COMPARATOR _VECTOR(5) ++ ++/* Timer/Counter Compare Match A */ ++#define TIM0_COMPA_vect_num 6 ++#define TIM0_COMPA_vect _VECTOR(6) ++#define SIG_OUTPUT_COMPARE0A _VECTOR(6) ++ ++/* Timer/Counter Compare Match B */ ++#define TIM0_COMPB_vect_num 7 ++#define TIM0_COMPB_vect _VECTOR(7) ++#define SIG_OUTPUT_COMPARE0B _VECTOR(7) ++ ++/* Watchdog Time-out */ ++#define WDT_vect_num 8 ++#define WDT_vect _VECTOR(8) ++#define SIG_WATCHDOG_TIMEOUT _VECTOR(8) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 9 ++#define ADC_vect _VECTOR(9) ++#define SIG_ADC _VECTOR(9) ++ ++#define _VECTORS_SIZE 20 ++ ++#define SPM_PAGESIZE 32 ++#define RAMSTART (0x60) ++#define RAMEND 0x9F ++#define XRAMEND RAMEND ++#define E2END 0x3F ++#define E2PAGESIZE 4 ++#define FLASHEND 0x3FF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 2 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT0 (unsigned char)~_BV(2) ++#define FUSE_SUT1 (unsigned char)~_BV(3) ++#define FUSE_CKDIV8 (unsigned char)~_BV(4) ++#define FUSE_WDTON (unsigned char)~_BV(5) ++#define FUSE_EESAVE (unsigned char)~_BV(6) ++#define FUSE_SPIEN (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_SUT0 & FUSE_CKDIV8 & FUSE_SPIEN) ++ ++/* High Fuse Byte */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) ++#define FUSE_DWEN (unsigned char)~_BV(3) ++#define FUSE_SPMEN (unsigned char)~_BV(4) ++#define HFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x90 ++#define SIGNATURE_2 0x07 ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_PIN_CHANGE0 ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_OUTPUT_COMPARE0A ++#pragma GCC poison SIG_OUTPUT_COMPARE0B ++#pragma GCC poison SIG_WATCHDOG_TIMEOUT ++#pragma GCC poison SIG_ADC ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++#endif /* _AVR_IOTN13_H_*/ +diff --git a/include/avr/iotn13a.h b/include/avr/iotn13a.h +index 7c9c5f9..936a052 100644 +--- a/include/avr/iotn13a.h ++++ b/include/avr/iotn13a.h +@@ -1,384 +1,384 @@ +-/* Copyright (c) 2008 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn13a.h 1955 2009-04-28 08:51:16Z arcanum $ */ +- +-/* avr/iotn13a.h - definitions for ATtiny13 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn13a.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATTINY13A_H_ +-#define _AVR_ATTINY13A_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define ADCSRB _SFR_IO8(0x03) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ACME 6 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x04) +-#endif +-#define ADCW _SFR_IO16(0x04) +- +-#define ADCL _SFR_IO8(0x04) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_IO8(0x05) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_IO8(0x06) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADMUX _SFR_IO8(0x07) +-#define MUX0 0 +-#define MUX1 1 +-#define ADLAR 5 +-#define REFS0 6 +- +-#define ACSR _SFR_IO8(0x08) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define DIDR0 _SFR_IO8(0x14) +-#define AIN0D 0 +-#define AIN1D 1 +-#define ADC1D 2 +-#define ADC3D 3 +-#define ADC2D 4 +-#define ADC0D 5 +- +-#define PCMSK _SFR_IO8(0x15) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +- +-#define PINB _SFR_IO8(0x16) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +- +-#define DDRB _SFR_IO8(0x17) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +- +-#define PORTB _SFR_IO8(0x18) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +- +-#define EECR _SFR_IO8(0x1C) +-#define EERE 0 +-#define EEWE 1 +-#define EEMWE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x1D) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEARL _SFR_IO8(0x1E) +- +-#define EEAR _SFR_IO8(0x1E) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +- +-#define WDTCR _SFR_IO8(0x21) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDTIE 6 +-#define WDTIF 7 +- +-#define PRR _SFR_IO8(0x25) +-#define PRADC 0 +-#define PRTIM0 1 +- +-#define CLKPR _SFR_IO8(0x26) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define GTCCR _SFR_IO8(0x28) +-#define PSR10 0 +-#define TSM 7 +- +-#define OCR0B _SFR_IO8(0x29) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define DWDR _SFR_IO8(0x2E) +-#define DWDR0 0 +-#define DWDR1 1 +-#define DWDR2 2 +-#define DWDR3 3 +-#define DWDR4 4 +-#define DWDR5 5 +-#define DWDR6 6 +-#define DWDR7 7 +- +-#define TCCR0A _SFR_IO8(0x2F) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define BODCR _SFR_IO8(0x30) +-#define BPDSE 0 +-#define BPDS 1 +- +-#define OSCCAL _SFR_IO8(0x31) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +- +-#define TCNT0 _SFR_IO8(0x32) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define TCCR0B _SFR_IO8(0x33) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x35) +-#define ISC00 0 +-#define ISC01 1 +-#define SM0 3 +-#define SM1 4 +-#define SE 5 +-#define PUD 6 +- +-#define OCR0A _SFR_IO8(0x36) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define RFLB 3 +-#define CTPB 4 +- +-#define TIFR0 _SFR_IO8(0x38) +-#define TOV0 1 +-#define OCF0A 2 +-#define OCF0B 3 +- +-#define TIMSK0 _SFR_IO8(0x39) +-#define TOIE0 1 +-#define OCIE0A 2 +-#define OCIE0B 3 +- +-#define GIFR _SFR_IO8(0x3A) +-#define PCIF 5 +-#define INTF0 6 +- +-#define GIMSK _SFR_IO8(0x3B) +-#define PCIE 5 +-#define INT0 6 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) /* External Interrupt Request 0 */ +-#define TIM0_OVF_vect_num 3 +-#define TIM0_OVF_vect _VECTOR(3) /* Timer/Counter0 Overflow */ +-#define EE_RDY_vect_num 4 +-#define EE_RDY_vect _VECTOR(4) /* EEPROM Ready */ +-#define ANA_COMP_vect_num 5 +-#define ANA_COMP_vect _VECTOR(5) /* Analog Comparator */ +-#define TIM0_COMPA_vect_num 6 +-#define TIM0_COMPA_vect _VECTOR(6) /* Timer/Counter Compare Match A */ +-#define TIM0_COMPB_vect_num 7 +-#define TIM0_COMPB_vect _VECTOR(7) /* Timer/Counter Compare Match B */ +-#define WDT_vect_num 8 +-#define WDT_vect _VECTOR(8) /* Watchdog Time-out */ +-#define ADC_vect_num 9 +-#define ADC_vect _VECTOR(9) /* ADC Conversion Complete */ +- +-#define _VECTOR_SIZE 2 /* Size of individual vector. */ +-#define _VECTORS_SIZE (10 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (32) +-#define RAMSTART (0x60) +-#define RAMSIZE (64) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (0) +-#define XRAMEND RAMEND +-#define E2END (64 - 1) +-#define E2PAGESIZE (4) +-#define FLASHEND (1024 - 1) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 2 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(2) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(3) /* Select start-up time */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(4) /* Start up with system clock divided by 8 */ +-#define FUSE_WDTON (unsigned char)~_BV(5) /* Watch dog timer always on */ +-#define FUSE_EESAVE (unsigned char)~_BV(6) /* Keep EEprom contents during chip erase */ +-#define FUSE_SPIEN (unsigned char)~_BV(7) /* SPI programming enable */ +-#define LFUSE_DEFAULT (FUSE_SPIEN & FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL0) +- +-/* High Fuse Byte */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(0) /* Disable external reset */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) /* Enable BOD and select level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) /* Enable BOD and select level */ +-#define FUSE_DWEN (unsigned char)~_BV(3) /* DebugWire Enable */ +-#define FUSE_SELFPRGEN (unsigned char)~_BV(4) /* Self Programming Enable */ +-#define HFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x90 +-#define SIGNATURE_2 0x07 +- +- +-#endif /* _AVR_ATTINY13A_H_ */ +- ++/* Copyright (c) 2008 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn13a.h 1955 2009-04-28 08:51:16Z arcanum $ */ ++ ++/* avr/iotn13a.h - definitions for ATtiny13 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn13a.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATTINY13A_H_ ++#define _AVR_ATTINY13A_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define ADCSRB _SFR_IO8(0x03) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCW _SFR_IO16(0x04) ++ ++#define ADCL _SFR_IO8(0x04) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_IO8(0x05) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_IO8(0x06) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADMUX _SFR_IO8(0x07) ++#define MUX0 0 ++#define MUX1 1 ++#define ADLAR 5 ++#define REFS0 6 ++ ++#define ACSR _SFR_IO8(0x08) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define DIDR0 _SFR_IO8(0x14) ++#define AIN0D 0 ++#define AIN1D 1 ++#define ADC1D 2 ++#define ADC3D 3 ++#define ADC2D 4 ++#define ADC0D 5 ++ ++#define PCMSK _SFR_IO8(0x15) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++ ++#define PINB _SFR_IO8(0x16) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++ ++#define DDRB _SFR_IO8(0x17) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++ ++#define PORTB _SFR_IO8(0x18) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++ ++#define EECR _SFR_IO8(0x1C) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x1D) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEARL _SFR_IO8(0x1E) ++ ++#define EEAR _SFR_IO8(0x1E) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++ ++#define WDTCR _SFR_IO8(0x21) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDTIE 6 ++#define WDTIF 7 ++ ++#define PRR _SFR_IO8(0x25) ++#define PRADC 0 ++#define PRTIM0 1 ++ ++#define CLKPR _SFR_IO8(0x26) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define GTCCR _SFR_IO8(0x28) ++#define PSR10 0 ++#define TSM 7 ++ ++#define OCR0B _SFR_IO8(0x29) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define DWDR _SFR_IO8(0x2E) ++#define DWDR0 0 ++#define DWDR1 1 ++#define DWDR2 2 ++#define DWDR3 3 ++#define DWDR4 4 ++#define DWDR5 5 ++#define DWDR6 6 ++#define DWDR7 7 ++ ++#define TCCR0A _SFR_IO8(0x2F) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define BODCR _SFR_IO8(0x30) ++#define BODSE 0 ++#define BODS 1 ++ ++#define OSCCAL _SFR_IO8(0x31) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++ ++#define TCNT0 _SFR_IO8(0x32) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define TCCR0B _SFR_IO8(0x33) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define ISC00 0 ++#define ISC01 1 ++#define SM0 3 ++#define SM1 4 ++#define SE 5 ++#define PUD 6 ++ ++#define OCR0A _SFR_IO8(0x36) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define RFLB 3 ++#define CTPB 4 ++ ++#define TIFR0 _SFR_IO8(0x38) ++#define TOV0 1 ++#define OCF0A 2 ++#define OCF0B 3 ++ ++#define TIMSK0 _SFR_IO8(0x39) ++#define TOIE0 1 ++#define OCIE0A 2 ++#define OCIE0B 3 ++ ++#define GIFR _SFR_IO8(0x3A) ++#define PCIF 5 ++#define INTF0 6 ++ ++#define GIMSK _SFR_IO8(0x3B) ++#define PCIE 5 ++#define INT0 6 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) /* External Interrupt Request 0 */ ++#define TIM0_OVF_vect_num 3 ++#define TIM0_OVF_vect _VECTOR(3) /* Timer/Counter0 Overflow */ ++#define EE_RDY_vect_num 4 ++#define EE_RDY_vect _VECTOR(4) /* EEPROM Ready */ ++#define ANA_COMP_vect_num 5 ++#define ANA_COMP_vect _VECTOR(5) /* Analog Comparator */ ++#define TIM0_COMPA_vect_num 6 ++#define TIM0_COMPA_vect _VECTOR(6) /* Timer/Counter Compare Match A */ ++#define TIM0_COMPB_vect_num 7 ++#define TIM0_COMPB_vect _VECTOR(7) /* Timer/Counter Compare Match B */ ++#define WDT_vect_num 8 ++#define WDT_vect _VECTOR(8) /* Watchdog Time-out */ ++#define ADC_vect_num 9 ++#define ADC_vect _VECTOR(9) /* ADC Conversion Complete */ ++ ++#define _VECTOR_SIZE 2 /* Size of individual vector. */ ++#define _VECTORS_SIZE (10 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (32) ++#define RAMSTART (0x60) ++#define RAMSIZE (64) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (0) ++#define XRAMEND RAMEND ++#define E2END (64 - 1) ++#define E2PAGESIZE (4) ++#define FLASHEND (1024 - 1) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 2 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Select start-up time */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(4) /* Start up with system clock divided by 8 */ ++#define FUSE_WDTON (unsigned char)~_BV(5) /* Watch dog timer always on */ ++#define FUSE_EESAVE (unsigned char)~_BV(6) /* Keep EEprom contents during chip erase */ ++#define FUSE_SPIEN (unsigned char)~_BV(7) /* SPI programming enable */ ++#define LFUSE_DEFAULT (FUSE_SPIEN & FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL0) ++ ++/* High Fuse Byte */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(0) /* Disable external reset */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) /* Enable BOD and select level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) /* Enable BOD and select level */ ++#define FUSE_DWEN (unsigned char)~_BV(3) /* DebugWire Enable */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(4) /* Self Programming Enable */ ++#define HFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x90 ++#define SIGNATURE_2 0x07 ++ ++ ++#endif /* _AVR_ATTINY13A_H_ */ ++ +diff --git a/include/avr/iotn15.h b/include/avr/iotn15.h +index 1a12541..3903179 100644 +--- a/include/avr/iotn15.h ++++ b/include/avr/iotn15.h +@@ -1,359 +1,360 @@ +-/* Copyright (c) 2002,2005 Marek Michalkiewicz +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn15.h 2236 2011-03-17 21:53:39Z arcanum $ */ +- +-/* avr/iotn15.h - definitions for ATtiny15 */ +- +-#ifndef _AVR_IOTN15_H_ +-#define _AVR_IOTN15_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn15.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-#ifndef __ASSEMBLER__ +-# warning "MCU not supported by the C compiler" +-#endif +- +-/* I/O registers */ +- +-/* 0x00..0x03 reserved */ +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16 (0x04) +-#endif +-#define ADCW _SFR_IO16(0x04) +-#define ADCL _SFR_IO8(0x04) +-#define ADCH _SFR_IO8(0x05) +-#define ADCSR _SFR_IO8(0x06) +-#define ADMUX _SFR_IO8(0x07) +- +-/* Analog Comparator Control and Status Register */ +-#define ACSR _SFR_IO8(0x08) +- +-/* 0x09..0x15 reserved */ +- +-/* Input Pins, Port B */ +-#define PINB _SFR_IO8(0x16) +- +-/* Data Direction Register, Port B */ +-#define DDRB _SFR_IO8(0x17) +- +-/* Data Register, Port B */ +-#define PORTB _SFR_IO8(0x18) +- +-/* 0x19..0x1B reserved */ +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO8(0x1E) +-#define EEARL _SFR_IO8(0x1E) +- +-/* 0x1F..0x20 reserved */ +- +-/* Watchdog Timer Control Register */ +-#define WDTCR _SFR_IO8(0x21) +- +-/* 0x22..0x2B reserved */ +-#define SFIOR _SFR_IO8(0x2C) +- +-#define OCR1B _SFR_IO8(0x2D) +-#define OCR1A _SFR_IO8(0x2E) +-#define TCNT1 _SFR_IO8(0x2F) +-#define TCCR1 _SFR_IO8(0x30) +- +-/* Oscillator Calibration Register */ +-#define OSCCAL _SFR_IO8(0x31) +- +-/* Timer/Counter0 (8-bit) */ +-#define TCNT0 _SFR_IO8(0x32) +- +-/* Timer/Counter0 Control Register */ +-#define TCCR0 _SFR_IO8(0x33) +- +-/* MCU general Status Register */ +-#define MCUSR _SFR_IO8(0x34) +- +-/* MCU general Control Register */ +-#define MCUCR _SFR_IO8(0x35) +- +-/* 0x36..0x37 reserved */ +- +-/* Timer/Counter Interrupt Flag Register */ +-#define TIFR _SFR_IO8(0x38) +- +-/* Timer/Counter Interrupt MaSK Register */ +-#define TIMSK _SFR_IO8(0x39) +- +-/* General Interrupt Flag Register */ +-#define GIFR _SFR_IO8(0x3A) +- +-/* General Interrupt MaSK register */ +-#define GIMSK _SFR_IO8(0x3B) +- +-/* 0x3C..0x3E reserved */ +- +-/* 0x3F SREG */ +- +-/* Interrupt vectors */ +- +-/* External Interrupt 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt Request 0 */ +-#define IO_PINS_vect_num 2 +-#define IO_PINS_vect _VECTOR(2) +-#define SIG_PIN _VECTOR(2) +-#define SIG_PIN_CHANGE _VECTOR(2) +- +-/* Timer/Counter1 Compare Match */ +-#define TIMER1_COMP_vect_num 3 +-#define TIMER1_COMP_vect _VECTOR(3) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(3) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 4 +-#define TIMER1_OVF_vect _VECTOR(4) +-#define SIG_OVERFLOW1 _VECTOR(4) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 5 +-#define TIMER0_OVF_vect _VECTOR(5) +-#define SIG_OVERFLOW0 _VECTOR(5) +- +-/* EEPROM Ready */ +-#define EE_RDY_vect_num 6 +-#define EE_RDY_vect _VECTOR(6) +-#define SIG_EEPROM_READY _VECTOR(6) +- +-/* Analog Comparator */ +-#define ANA_COMP_vect_num 7 +-#define ANA_COMP_vect _VECTOR(7) +-#define SIG_COMPARATOR _VECTOR(7) +- +-/* ADC Conversion Ready */ +-#define ADC_vect_num 8 +-#define ADC_vect _VECTOR(8) +-#define SIG_ADC _VECTOR(8) +- +-#define _VECTORS_SIZE 18 +- +-/* Bit numbers */ +- +-/* GIMSK */ +-#define INT0 6 +-#define PCIE 5 +- +-/* GIFR */ +-#define INTF0 6 +-#define PCIF 5 +- +-/* TIMSK */ +-#define OCIE1 6 +-#define TOIE1 2 +-#define TOIE0 1 +- +-/* TIFR */ +-#define OCF1 6 +-#define TOV1 2 +-#define TOV0 1 +- +-/* MCUCR */ +-#define PUD 6 +-#define SE 5 +-#define SM1 4 +-#define SM0 3 +-#define ISC01 1 +-#define ISC00 0 +- +-/* MCUSR */ +-#define WDRF 3 +-#define BORF 2 +-#define EXTRF 1 +-#define PORF 0 +- +-/* TCCR0 */ +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* TCCR1 */ +-#define CTC1 7 +-#define PWM1 6 +-#define COM1A1 5 +-#define COM1A0 4 +-#define CS13 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* SFIOR */ +-#define FOC1A 2 +-#define PSR1 1 +-#define PSR0 0 +- +-/* WDTCR */ +-#define WDTOE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* +- PB5 = RESET# / ADC0 +- PB4 = ADC3 +- PB3 = ADC2 +- PB2 = SCK / ADC1 / T0 / INT0 +- PB1 = MISO / AIN1 / OCP +- PB0 = MOSI / AIN0 / AREF +- */ +- +-/* PORTB */ +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* DDRB */ +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* PINB */ +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* ACSR */ +-#define ACD 7 +-#define GREF 6 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIS1 1 +-#define ACIS0 0 +- +-/* ADMUX */ +-#define REFS1 7 +-#define REFS0 6 +-#define ADLAR 5 +-#define MUX2 2 +-#define MUX1 1 +-#define MUX0 0 +- +-/* ADCSR */ +-#define ADEN 7 +-#define ADSC 6 +-#define ADFR 5 +-#define ADIF 4 +-#define ADIE 3 +-#define ADPS2 2 +-#define ADPS1 1 +-#define ADPS0 0 +- +-/* EEPROM Control Register */ +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-/* Last memory addresses */ +-#define RAMEND 0x1F +-#define XRAMEND 0x0 +-#define E2END 0x3F +-#define E2PAGESIZE 2 +-#define FLASHEND 0x3FF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 1 +- +-/* Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_RSTDISBL (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_BODEN (unsigned char)~_BV(6) +-#define FUSE_BODLEVEL (unsigned char)~_BV(7) +-#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL1 & FUSE_SPIEN) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x90 +-#define SIGNATURE_2 0x06 +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_PIN +-#pragma GCC poison SIG_PIN_CHANGE +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_ADC +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +-#endif /* _AVR_IOTN15_H_ */ ++/* Copyright (c) 2002,2005 Marek Michalkiewicz ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn15.h 2236 2011-03-17 21:53:39Z arcanum $ */ ++ ++/* avr/iotn15.h - definitions for ATtiny15 */ ++ ++#ifndef _AVR_IOTN15_H_ ++#define _AVR_IOTN15_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn15.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef __ASSEMBLER__ ++# warning "MCU not supported by the C compiler" ++#endif ++ ++/* I/O registers */ ++ ++/* 0x00..0x03 reserved */ ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16 (0x04) ++#endif ++#define ADCW _SFR_IO16(0x04) ++#define ADCL _SFR_IO8(0x04) ++#define ADCH _SFR_IO8(0x05) ++#define ADCSR _SFR_IO8(0x06) ++#define ADMUX _SFR_IO8(0x07) ++ ++/* Analog Comparator Control and Status Register */ ++#define ACSR _SFR_IO8(0x08) ++ ++/* 0x09..0x15 reserved */ ++ ++/* Input Pins, Port B */ ++#define PINB _SFR_IO8(0x16) ++ ++/* Data Direction Register, Port B */ ++#define DDRB _SFR_IO8(0x17) ++ ++/* Data Register, Port B */ ++#define PORTB _SFR_IO8(0x18) ++ ++/* 0x19..0x1B reserved */ ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO8(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++ ++/* 0x1F..0x20 reserved */ ++ ++/* Watchdog Timer Control Register */ ++#define WDTCR _SFR_IO8(0x21) ++ ++/* 0x22..0x2B reserved */ ++#define SFIOR _SFR_IO8(0x2C) ++ ++#define OCR1B _SFR_IO8(0x2D) ++#define OCR1A _SFR_IO8(0x2E) ++#define TCNT1 _SFR_IO8(0x2F) ++#define TCCR1 _SFR_IO8(0x30) ++ ++/* Oscillator Calibration Register */ ++#define OSCCAL _SFR_IO8(0x31) ++ ++/* Timer/Counter0 (8-bit) */ ++#define TCNT0 _SFR_IO8(0x32) ++ ++/* Timer/Counter0 Control Register */ ++#define TCCR0 _SFR_IO8(0x33) ++ ++/* MCU general Status Register */ ++#define MCUSR _SFR_IO8(0x34) ++ ++/* MCU general Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++ ++/* 0x36..0x37 reserved */ ++ ++/* Timer/Counter Interrupt Flag Register */ ++#define TIFR _SFR_IO8(0x38) ++ ++/* Timer/Counter Interrupt MaSK Register */ ++#define TIMSK _SFR_IO8(0x39) ++ ++/* General Interrupt Flag Register */ ++#define GIFR _SFR_IO8(0x3A) ++ ++/* General Interrupt MaSK register */ ++#define GIMSK _SFR_IO8(0x3B) ++ ++/* 0x3C..0x3E reserved */ ++ ++/* 0x3F SREG */ ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt Request 0 */ ++#define IO_PINS_vect_num 2 ++#define IO_PINS_vect _VECTOR(2) ++#define SIG_PIN _VECTOR(2) ++#define SIG_PIN_CHANGE _VECTOR(2) ++ ++/* Timer/Counter1 Compare Match */ ++#define TIMER1_COMP_vect_num 3 ++#define TIMER1_COMP_vect _VECTOR(3) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(3) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 4 ++#define TIMER1_OVF_vect _VECTOR(4) ++#define SIG_OVERFLOW1 _VECTOR(4) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 5 ++#define TIMER0_OVF_vect _VECTOR(5) ++#define SIG_OVERFLOW0 _VECTOR(5) ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect_num 6 ++#define EE_RDY_vect _VECTOR(6) ++#define SIG_EEPROM_READY _VECTOR(6) ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect_num 7 ++#define ANA_COMP_vect _VECTOR(7) ++#define SIG_COMPARATOR _VECTOR(7) ++ ++/* ADC Conversion Ready */ ++#define ADC_vect_num 8 ++#define ADC_vect _VECTOR(8) ++#define SIG_ADC _VECTOR(8) ++ ++#define _VECTORS_SIZE 18 ++ ++/* Bit numbers */ ++ ++/* GIMSK */ ++#define INT0 6 ++#define PCIE 5 ++ ++/* GIFR */ ++#define INTF0 6 ++#define PCIF 5 ++ ++/* TIMSK */ ++#define OCIE1 6 ++#define TOIE1 2 ++#define TOIE0 1 ++ ++/* TIFR */ ++#define OCF1 6 ++#define TOV1 2 ++#define TOV0 1 ++ ++/* MCUCR */ ++#define PUD 6 ++#define SE 5 ++#define SM1 4 ++#define SM0 3 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* MCUSR */ ++#define WDRF 3 ++#define BORF 2 ++#define EXTRF 1 ++#define PORF 0 ++ ++/* TCCR0 */ ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* TCCR1 */ ++#define CTC1 7 ++#define PWM1 6 ++#define COM1A1 5 ++#define COM1A0 4 ++#define CS13 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* SFIOR */ ++#define FOC1A 2 ++#define PSR1 1 ++#define PSR0 0 ++ ++/* WDTCR */ ++#define WDTOE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* ++ PB5 = RESET# / ADC0 ++ PB4 = ADC3 ++ PB3 = ADC2 ++ PB2 = SCK / ADC1 / T0 / INT0 ++ PB1 = MISO / AIN1 / OCP ++ PB0 = MOSI / AIN0 / AREF ++ */ ++ ++/* PORTB */ ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* DDRB */ ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* PINB */ ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* ACSR */ ++#define ACD 7 ++#define GREF 6 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++/* ADMUX */ ++#define REFS1 7 ++#define REFS0 6 ++#define ADLAR 5 ++#define MUX2 2 ++#define MUX1 1 ++#define MUX0 0 ++ ++/* ADCSR */ ++#define ADEN 7 ++#define ADSC 6 ++#define ADFR 5 ++#define ADIF 4 ++#define ADIE 3 ++#define ADPS2 2 ++#define ADPS1 1 ++#define ADPS0 0 ++ ++/* EEPROM Control Register */ ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++#define RAMSTART 0x60 ++/* Last memory addresses */ ++#define RAMEND 0x1F ++#define XRAMEND 0x0 ++#define E2END 0x3F ++#define E2PAGESIZE 2 ++#define FLASHEND 0x3FF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_BODEN (unsigned char)~_BV(6) ++#define FUSE_BODLEVEL (unsigned char)~_BV(7) ++#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL1 & FUSE_SPIEN) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x90 ++#define SIGNATURE_2 0x06 ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_PIN ++#pragma GCC poison SIG_PIN_CHANGE ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_ADC ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++#endif /* _AVR_IOTN15_H_ */ +diff --git a/include/avr/iotn1634.h b/include/avr/iotn1634.h +new file mode 100644 +index 0000000..36e6ab5 +--- /dev/null ++++ b/include/avr/iotn1634.h +@@ -0,0 +1,855 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATTINY1634_H_INCLUDED ++#define _AVR_ATTINY1634_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn1634.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x00) ++#endif ++#define ADCW _SFR_IO16(0x00) ++ ++#define ADCL _SFR_IO8(0x00) ++#define ADCH _SFR_IO8(0x01) ++ ++#define ADCSRB _SFR_IO8(0x02) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ADLAR 3 ++#define VDPD 6 ++#define VDEN 7 ++ ++#define ADCSRA _SFR_IO8(0x03) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADMUX _SFR_IO8(0x04) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define ADC0EN 4 ++#define REFEN 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define ACSRB _SFR_IO8(0x05) ++#define ACIRS0 0 ++#define ACIRS1 1 ++#define ACME 2 ++#define ACCE 3 ++#define ACLP 5 ++#define HLEV 6 ++#define HSEL 7 ++ ++#define ACSRA _SFR_IO8(0x06) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define PINC _SFR_IO8(0x07) ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x08) ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x09) ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PUEC _SFR_IO8(0x0A) ++#define PUEC0 0 ++#define PUEC1 1 ++#define PUEC2 2 ++#define PUEC3 3 ++#define PUEC4 4 ++#define PUEC5 5 ++ ++#define PINB _SFR_IO8(0x0B) ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x0C) ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x0D) ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PUEB _SFR_IO8(0x0E) ++#define PUEB0 0 ++#define PUEB1 1 ++#define PUEB2 2 ++#define PUEB3 3 ++ ++#define PINA _SFR_IO8(0x0F) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x10) ++#define DDRA7 7 ++#define DDRA6 6 ++#define DDRA5 5 ++#define DDRA4 4 ++#define DDRA3 3 ++#define DDRA2 2 ++#define DDRA1 1 ++#define DDRA0 0 ++ ++#define PORTA _SFR_IO8(0x11) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define PUEA _SFR_IO8(0x12) ++#define PUEA0 0 ++#define PUEA1 1 ++#define PUEA2 2 ++#define PUEA3 3 ++#define PUEA4 4 ++#define PUEA5 5 ++#define PUEA6 6 ++#define PUEA7 7 ++ ++#define PORTCR _SFR_IO8(0x13) ++#define BBMB 1 ++#define BBMC 2 ++#define BBMA 0 ++ ++#define GPIOR0 _SFR_IO8(0x14) ++ ++#define GPIOR1 _SFR_IO8(0x15) ++ ++#define GPIOR2 _SFR_IO8(0x16) ++ ++#define OCR0B _SFR_IO8(0x17) ++ ++#define OCR0A _SFR_IO8(0x18) ++ ++#define TCNT0 _SFR_IO8(0x19) ++ ++#define TCCR0B _SFR_IO8(0x1A) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCCR0A _SFR_IO8(0x1B) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define EECR _SFR_IO8(0x1C) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x1E) ++ ++#define EEARL _SFR_IO8(0x1E) ++#define EEARH _SFR_IO8(0x1F) ++ ++#define UDR0 _SFR_IO8(0x20) ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_IO16(0x21) ++ ++#define UBRR0L _SFR_IO8(0x21) ++#define UBRR0H _SFR_IO8(0x22) ++ ++#define UCSR0D _SFR_IO8(0x23) ++#define SFDE0 5 ++#define RXS0 6 ++#define RXSIE0 7 ++ ++#define UCSR0C _SFR_IO8(0x24) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++ ++#define UCSR0B _SFR_IO8(0x25) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0A _SFR_IO8(0x26) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++#define PCMSK0 _SFR_IO8(0x27) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_IO8(0x28) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++ ++#define PCMSK2 _SFR_IO8(0x29) ++#define PCINT12 0 ++#define PCINT13 1 ++#define PCINT14 2 ++#define PCINT15 3 ++#define PCINT16 4 ++#define PCINT17 5 ++ ++#define USICR _SFR_IO8(0x2A) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_IO8(0x2B) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_IO8(0x2C) ++ ++#define USIBR _SFR_IO8(0x2D) ++ ++/* Reserved [0x2E] */ ++ ++#define CCP _SFR_IO8(0x2F) ++ ++#define WDTCSR _SFR_IO8(0x30) ++#define WDE 3 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++/* Reserved [0x31] */ ++ ++#define CLKSR _SFR_IO8(0x32) ++#define CKSEL0 0 ++#define CKSEL1 1 ++#define CKSEL2 2 ++#define CKSEL3 3 ++#define SUT 4 ++#define CKOUT_IO 5 ++#define CSTR 6 ++#define OSCRDY 7 ++ ++#define CLKPR _SFR_IO8(0x33) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++ ++#define PRR _SFR_IO8(0x34) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRUSART1 2 ++#define PRUSI 3 ++#define PRTIM0 4 ++#define PRTIM1 5 ++#define PRTWI 6 ++ ++#define MCUSR _SFR_IO8(0x35) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x36) ++#define ISC00 0 ++#define ISC01 1 ++#define SE 4 ++#define SM0 5 ++#define SM1 6 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define RFLB 3 ++#define CTPB 4 ++#define RSIG 5 ++ ++/* Reserved [0x38] */ ++ ++#define TIFR _SFR_IO8(0x39) ++#define ICF1 3 ++#define OCF1B 5 ++#define OCF1A 6 ++#define TOV1 7 ++#define OCF0A 0 ++#define TOV0 1 ++#define OCF0B 2 ++ ++#define TIMSK _SFR_IO8(0x3A) ++#define ICIE1 3 ++#define OCIE1B 5 ++#define OCIE1A 6 ++#define TOIE1 7 ++#define OCIE0A 0 ++#define TOIE0 1 ++#define OCIE0B 2 ++ ++#define GIFR _SFR_IO8(0x3B) ++#define PCIF0 3 ++#define PCIF1 4 ++#define PCIF2 5 ++#define INTF0 6 ++ ++#define GIMSK _SFR_IO8(0x3C) ++#define PCIE0 3 ++#define PCIE1 4 ++#define PCIE2 5 ++#define INT0 6 ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define DIDR0 _SFR_MEM8(0x60) ++#define AREFD 0 ++#define AIN0D 1 ++#define AIN1D 2 ++#define ADC0D 3 ++#define ADC1D 4 ++#define ADC2D 5 ++#define ADC3D 6 ++#define ADC4D 7 ++ ++#define DIDR1 _SFR_MEM8(0x61) ++#define ADC5D 0 ++#define ADC6D 1 ++#define ADC7D 2 ++#define ADC8D 3 ++ ++#define DIDR2 _SFR_MEM8(0x62) ++#define ADC9D 0 ++#define ADC10D 1 ++#define ADC11D 2 ++ ++#define OSCCAL0 _SFR_MEM8(0x63) ++ ++#define OSCTCAL0A _SFR_MEM8(0x64) ++ ++#define OSCTCAL0B _SFR_MEM8(0x65) ++ ++#define OSCCAL1 _SFR_MEM8(0x66) ++ ++#define GTCCR _SFR_MEM8(0x67) ++#define PSR10 0 ++#define TSM 7 ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x68) ++ ++#define ICR1L _SFR_MEM8(0x68) ++#define ICR1H _SFR_MEM8(0x69) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x6A) ++ ++#define OCR1BL _SFR_MEM8(0x6A) ++#define OCR1BH _SFR_MEM8(0x6B) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x6C) ++ ++#define OCR1AL _SFR_MEM8(0x6C) ++#define OCR1AH _SFR_MEM8(0x6D) ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x6E) ++ ++#define TCNT1L _SFR_MEM8(0x6E) ++#define TCNT1H _SFR_MEM8(0x6F) ++ ++#define TCCR1C _SFR_MEM8(0x70) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCCR1B _SFR_MEM8(0x71) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1A _SFR_MEM8(0x72) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define UDR1 _SFR_MEM8(0x73) ++ ++/* Combine UBRR1L and UBRR1H */ ++#define UBRR1 _SFR_MEM16(0x74) ++ ++#define UBRR1L _SFR_MEM8(0x74) ++#define UBRR1H _SFR_MEM8(0x75) ++ ++#define UCSR1D _SFR_MEM8(0x76) ++#define SFDE1 5 ++#define RXS1 6 ++#define RXSIE1 7 ++ ++#define UCSR1C _SFR_MEM8(0x77) ++#define UCPOL1 0 ++#define UCSZ10 1 ++#define UCSZ11 2 ++#define USBS1 3 ++#define UPM10 4 ++#define UPM11 5 ++#define UMSEL10 6 ++#define UMSEL11 7 ++ ++#define UCSR1B _SFR_MEM8(0x78) ++#define TXB81 0 ++#define RXB81 1 ++#define UCSZ12 2 ++#define TXEN1 3 ++#define RXEN1 4 ++#define UDRIE1 5 ++#define TXCIE1 6 ++#define RXCIE1 7 ++ ++#define UCSR1A _SFR_MEM8(0x79) ++#define MPCM1 0 ++#define U2X1 1 ++#define UPE1 2 ++#define DOR1 3 ++#define FE1 4 ++#define UDRE1 5 ++#define TXC1 6 ++#define RXC1 7 ++ ++#define TWSD _SFR_MEM8(0x7A) ++#define TWSD0 0 ++#define TWSD1 1 ++#define TWSD2 2 ++#define TWSD3 3 ++#define TWSD4 4 ++#define TWSD5 5 ++#define TWSD6 6 ++#define TWSD7 7 ++ ++#define TWSAM _SFR_MEM8(0x7B) ++ ++#define TWSA _SFR_MEM8(0x7C) ++#define TWSA0 0 ++#define TWSA1 1 ++#define TWSA2 2 ++#define TWSA3 3 ++#define TWSA4 4 ++#define TWSA5 5 ++#define TWSA6 6 ++#define TWSA7 7 ++ ++#define TWSSRA _SFR_MEM8(0x7D) ++#define TWAS 0 ++#define TWDIR 1 ++#define TWBE 2 ++#define TWC 3 ++#define TWRA 4 ++#define TWCH 5 ++#define TWASIF 6 ++#define TWDIF 7 ++ ++#define TWSCRB _SFR_MEM8(0x7E) ++#define TWCMD0 0 ++#define TWCMD1 1 ++#define TWAA 2 ++ ++#define TWSCRA _SFR_MEM8(0x7F) ++#define TWSME 0 ++#define TWPME 1 ++#define TWSIE 2 ++#define TWEN 3 ++#define TWASIE 4 ++#define TWDIE 5 ++#define TWSHE 7 ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(2) ++#define PCINT0_vect_num 2 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(3) ++#define PCINT1_vect_num 3 ++ ++/* Pin Change Interrupt Request 2 */ ++#define PCINT2_vect _VECTOR(4) ++#define PCINT2_vect_num 4 ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect _VECTOR(5) ++#define WDT_vect_num 5 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(6) ++#define TIMER1_CAPT_vect_num 6 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIM1_CAPT_vect _VECTOR(6) ++#define TIM1_CAPT_vect_num 6 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(7) ++#define TIMER1_COMPA_vect_num 7 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIM1_COMPA_vect _VECTOR(7) ++#define TIM1_COMPA_vect_num 7 ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(8) ++#define TIMER1_COMPB_vect_num 8 ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIM1_COMPB_vect _VECTOR(8) ++#define TIM1_COMPB_vect_num 8 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(9) ++#define TIMER1_OVF_vect_num 9 ++ ++/* Timer/Counter1 Overflow */ ++#define TIM1_OVF_vect _VECTOR(9) ++#define TIM1_OVF_vect_num 9 ++ ++/* TimerCounter0 Compare Match A */ ++#define TIMER0_COMPA_vect _VECTOR(10) ++#define TIMER0_COMPA_vect_num 10 ++ ++/* TimerCounter0 Compare Match A */ ++#define TIM0_COMPA_vect _VECTOR(10) ++#define TIM0_COMPA_vect_num 10 ++ ++/* TimerCounter0 Compare Match B */ ++#define TIMER0_COMPB_vect _VECTOR(11) ++#define TIMER0_COMPB_vect_num 11 ++ ++/* TimerCounter0 Compare Match B */ ++#define TIM0_COMPB_vect _VECTOR(11) ++#define TIM0_COMPB_vect_num 11 ++ ++/* Timer/Couner0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(12) ++#define TIMER0_OVF_vect_num 12 ++ ++/* Timer/Couner0 Overflow */ ++#define TIM0_OVF_vect _VECTOR(12) ++#define TIM0_OVF_vect_num 12 ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect _VECTOR(13) ++#define ANA_COMP_vect_num 13 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(14) ++#define ADC_vect_num 14 ++ ++/* ADC Conversion Complete */ ++#define ADC_READY_vect _VECTOR(14) ++#define ADC_READY_vect_num 14 ++ ++/* USART0, Start */ ++#define USART0_START_vect _VECTOR(15) ++#define USART0_START_vect_num 15 ++ ++/* USART0, Start */ ++#define USART0_RXS_vect _VECTOR(15) ++#define USART0_RXS_vect_num 15 ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect _VECTOR(16) ++#define USART0_RX_vect_num 16 ++ ++/* USART0, Rx Complete */ ++#define USART0_RXC_vect _VECTOR(16) ++#define USART0_RXC_vect_num 16 ++ ++/* USART0 Data Register Empty */ ++#define USART0_UDRE_vect _VECTOR(17) ++#define USART0_UDRE_vect_num 17 ++ ++/* USART0 Data Register Empty */ ++#define USART0_DRE_vect _VECTOR(17) ++#define USART0_DRE_vect_num 17 ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect _VECTOR(18) ++#define USART0_TX_vect_num 18 ++ ++/* USART0, Tx Complete */ ++#define USART0_TXC_vect _VECTOR(18) ++#define USART0_TXC_vect_num 18 ++ ++/* USART1, Start */ ++#define USART1_START_vect _VECTOR(19) ++#define USART1_START_vect_num 19 ++ ++/* USART1, Start */ ++#define USART1_RXS_vect _VECTOR(19) ++#define USART1_RXS_vect_num 19 ++ ++/* USART1, Rx Complete */ ++#define USART1_RX_vect _VECTOR(20) ++#define USART1_RX_vect_num 20 ++ ++/* USART1, Rx Complete */ ++#define USART1_RXC_vect _VECTOR(20) ++#define USART1_RXC_vect_num 20 ++ ++/* USART1 Data Register Empty */ ++#define USART1_UDRE_vect _VECTOR(21) ++#define USART1_UDRE_vect_num 21 ++ ++/* USART1 Data Register Empty */ ++#define USART1_DRE_vect _VECTOR(21) ++#define USART1_DRE_vect_num 21 ++ ++/* USART1, Tx Complete */ ++#define USART1_TX_vect _VECTOR(22) ++#define USART1_TX_vect_num 22 ++ ++/* USART1, Tx Complete */ ++#define USART1_TXC_vect _VECTOR(22) ++#define USART1_TXC_vect_num 22 ++ ++/* USI Start Condition */ ++#define USI_START_vect _VECTOR(23) ++#define USI_START_vect_num 23 ++ ++/* USI Start Condition */ ++#define USI_STR_vect _VECTOR(23) ++#define USI_STR_vect_num 23 ++ ++/* USI Overflow */ ++#define USI_OVERFLOW_vect _VECTOR(24) ++#define USI_OVERFLOW_vect_num 24 ++ ++/* USI Overflow */ ++#define USI_OVF_vect _VECTOR(24) ++#define USI_OVF_vect_num 24 ++ ++/* Two-wire Serial Interface */ ++#define TWI_SLAVE_vect _VECTOR(25) ++#define TWI_SLAVE_vect_num 25 ++ ++/* Two-wire Serial Interface */ ++#define TWI_vect _VECTOR(25) ++#define TWI_vect_num 25 ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect _VECTOR(26) ++#define EE_RDY_vect_num 26 ++ ++/* Touch Sensing */ ++#define QTRIP_vect _VECTOR(27) ++#define QTRIP_vect_num 27 ++ ++#define _VECTORS_SIZE 112 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 32 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x3FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 1024 ++#define RAMEND 0x04FF ++#define E2START 0 ++#define E2SIZE 256 ++#define E2PAGESIZE 4 ++#define E2END 0x00FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) ++#define FUSE_BODACT0 (unsigned char)~_BV(1) ++#define FUSE_BODACT1 (unsigned char)~_BV(2) ++#define FUSE_BODPD0 (unsigned char)~_BV(3) ++#define FUSE_BODPD1 (unsigned char)~_BV(4) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x12 ++ ++ ++#endif /* #ifdef _AVR_ATTINY1634_H_INCLUDED */ ++ +diff --git a/include/avr/iotn167.h b/include/avr/iotn167.h +index 04ee489..76202a9 100644 +--- a/include/avr/iotn167.h ++++ b/include/avr/iotn167.h +@@ -1,869 +1,869 @@ +-/* Copyright (c) 2008-2010 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. +-*/ +- +-/* $Id: iotn167.h 2253 2011-09-26 14:53:41Z arcanum $ */ +- +-/* avr/iotn167.h - definitions for ATtiny167. */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn167.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_IOTN167_H_ +-#define _AVR_IOTN167_H_ 1 +- +- +-/* Registers and associated bit numbers */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +-#define PINA4 4 +-#define PINA5 5 +-#define PINA6 6 +-#define PINA7 7 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +-#define DDA4 4 +-#define DDA5 5 +-#define DDA6 6 +-#define DDA7 7 +- +-#define PORTA _SFR_IO8(0x02) +-#define PORTA0 0 +-#define PORTA1 1 +-#define PORTA2 2 +-#define PORTA3 3 +-#define PORTA4 4 +-#define PORTA5 5 +-#define PORTA6 6 +-#define PORTA7 7 +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PORTCR _SFR_IO8(0x12) +-#define PUDA 0 +-#define PUDB 2 +-#define BBMA 4 +-#define BBMB 5 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +-#define PCIF1 1 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSR1 0 +-#define PSR0 1 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x25) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define TCCR0B _SFR_IO8(0x26) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define FOC0A 7 +- +-#define TCNT0 _SFR_IO8(0x27) +-#define TCNT00 0 +-#define TCNT01 1 +-#define TCNT02 2 +-#define TCNT03 3 +-#define TCNT04 4 +-#define TCNT05 5 +-#define TCNT06 6 +-#define TCNT07 7 +- +-#define OCR0A _SFR_IO8(0x28) +-#define OCR00 0 +-#define OCR01 1 +-#define OCR02 2 +-#define OCR03 3 +-#define OCR04 4 +-#define OCR05 5 +-#define OCR06 6 +-#define OCR07 7 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACIRS 6 +-#define ACD 7 +- +-#define DWDR _SFR_IO8(0x31) +-#define DWDR0 0 +-#define DWDR1 1 +-#define DWDR2 2 +-#define DWDR3 3 +-#define DWDR4 4 +-#define DWDR5 5 +-#define DWDR6 6 +-#define DWDR7 7 +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x35) +-#define PUD 4 +-#define BODSE 5 +-#define BODS 6 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define RFLB 3 +-#define CTPB 4 +-#define SIGRD 5 +-#define RWWSB 6 +- +-#define WDTCR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define CLKCSR _SFR_MEM8(0x62) +-#define CLKC0 0 +-#define CLKC1 1 +-#define CLKC2 2 +-#define CLKC3 3 +-#define CLKRDY 4 +-#define CLKCCE 7 +- +-#define CLKSELR _SFR_MEM8(0x63) +-#define CSEL0 0 +-#define CSEL1 1 +-#define CSEL2 2 +-#define CSEL3 3 +-#define CSUT0 4 +-#define CSUT1 5 +-#define COUT 6 +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSI 1 +-#define PRTIM0 2 +-#define PRTIM1 3 +-#define PRSPI 4 +-#define PRLIN 5 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +-#define PCIE1 1 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define AMISCR _SFR_MEM8(0x77) +-#define ISRCEN 0 +-#define XREFEN 1 +-#define AREFEN 2 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +- +-#define ADCL _SFR_MEM8(0x78) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_MEM8(0x79) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ACIR0 4 +-#define ACIR1 5 +-#define ACME 6 +-#define BIN 7 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define ADC8D 0 +-#define ADC9D 1 +-#define ADC10D 2 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCCR1D _SFR_MEM8(0x83) +-#define OC1AU 0 +-#define OC1AV 1 +-#define OC1AW 2 +-#define OC1AX 3 +-#define OC1BU 4 +-#define OC1BV 5 +-#define OC1BW 6 +-#define OC1BX 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define ASSR _SFR_MEM8(0xB6) +-#define TCR0BUB 0 +-#define TCR0AUB 1 +-#define OCR0AUB 3 +-#define TCN0UB 4 +-#define AS0 5 +-#define EXCLK 6 +- +-#define USICR _SFR_MEM8(0xB8) +-#define USITC 0 +-#define USICLK 1 +-#define USICS0 2 +-#define USICS1 3 +-#define USIWM0 4 +-#define USIWM1 5 +-#define USIOIE 6 +-#define USISIE 7 +- +-#define USISR _SFR_MEM8(0xB9) +-#define USICNT0 0 +-#define USICNT1 1 +-#define USICNT2 2 +-#define USICNT3 3 +-#define USIDC 4 +-#define USIPF 5 +-#define USIOIF 6 +-#define USISIF 7 +- +-#define USIDR _SFR_MEM8(0xBA) +-#define USIDR0 0 +-#define USIDR1 1 +-#define USIDR2 2 +-#define USIDR3 3 +-#define USIDR4 4 +-#define USIDR5 5 +-#define USIDR6 6 +-#define USIDR7 7 +- +-#define USIBR _SFR_MEM8(0xBB) +-#define USIBR0 0 +-#define USIBR1 1 +-#define USIBR2 2 +-#define USIBR3 3 +-#define USIBR4 4 +-#define USIBR5 5 +-#define USIBR6 6 +-#define USIBR7 7 +- +-#define USIPP _SFR_MEM8(0xBC) +-#define USIPOS 0 +- +-#define LINCR _SFR_MEM8(0xC8) +-#define LCMD0 0 +-#define LCMD1 1 +-#define LCMD2 2 +-#define LENA 3 +-#define LCONF0 4 +-#define LCONF1 5 +-#define LIN13 6 +-#define LSWRES 7 +- +-#define LINSIR _SFR_MEM8(0xC9) +-#define LRXOK 0 +-#define LTXOK 1 +-#define LIDOK 2 +-#define LERR 3 +-#define LBUSY 4 +-#define LIDST0 5 +-#define LIDST1 6 +-#define LIDST2 7 +- +-#define LINENIR _SFR_MEM8(0xCA) +-#define LENRXOK 0 +-#define LENTXOK 1 +-#define LENIDOK 2 +-#define LENERR 3 +- +-#define LINERR _SFR_MEM8(0xCB) +-#define LBERR 0 +-#define LCERR 1 +-#define LPERR 2 +-#define LSERR 3 +-#define LFERR 4 +-#define LOVERR 5 +-#define LTOERR 6 +-#define LABORT 7 +- +-#define LINBTR _SFR_MEM8(0xCC) +-#define LBT0 0 +-#define LBT1 1 +-#define LBT2 2 +-#define LBT3 3 +-#define LBT4 4 +-#define LBT5 5 +-#define LDISR 7 +- +-#define LINBRR _SFR_MEM16(0xCD) +- +-#define LINBRRL _SFR_MEM8(0xCD) +-#define LDIV0 0 +-#define LDIV1 1 +-#define LDIV2 2 +-#define LDIV3 3 +-#define LDIV4 4 +-#define LDIV5 5 +-#define LDIV6 6 +-#define LDIV7 7 +- +-#define LINBRRH _SFR_MEM8(0xCE) +-#define LDIV8 0 +-#define LDIV9 1 +-#define LDIV10 2 +-#define LDIV11 3 +- +-#define LINDLR _SFR_MEM8(0xCF) +-#define LRXDL0 0 +-#define LRXDL1 1 +-#define LRXDL2 2 +-#define LRXDL3 3 +-#define LTXDL0 4 +-#define LTXDL1 5 +-#define LTXDL2 6 +-#define LTXDL3 7 +- +-#define LINIDR _SFR_MEM8(0xD0) +-#define LID0 0 +-#define LID1 1 +-#define LID2 2 +-#define LID3 3 +-#define LID4 4 +-#define LID5 5 +-#define LP0 6 +-#define LP1 7 +- +-#define LINSEL _SFR_MEM8(0xD1) +-#define LINDX0 0 +-#define LINDX1 1 +-#define LINDX2 2 +-#define LAINC 3 +- +-#define LINDAT _SFR_MEM8(0xD2) +-#define LDATA0 0 +-#define LDATA1 1 +-#define LDATA2 2 +-#define LDATA3 3 +-#define LDATA4 4 +-#define LDATA5 5 +-#define LDATA6 6 +-#define LDATA7 7 +- +- +- +-/* Interrupt Vectors */ +-/* Interrupt Vector 0 is the reset vector. */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +- +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ +- +-#define PCINT0_vect_num 3 +-#define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ +- +-#define PCINT1_vect_num 4 +-#define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 1 */ +- +-#define WDT_vect_num 5 +-#define WDT_vect _VECTOR(5) /* Watchdog Time-Out Interrupt */ +- +-#define TIMER1_CAPT_vect_num 6 +-#define TIMER1_CAPT_vect _VECTOR(6) /* Timer/Counter1 Capture Event */ +- +-#define TIMER1_COMPA_vect_num 7 +-#define TIMER1_COMPA_vect _VECTOR(7) /* Timer/Counter1 Compare Match 1A */ +- +-#define TIMER1_COMPB_vect_num 8 +-#define TIMER1_COMPB_vect _VECTOR(8) /* Timer/Counter1 Compare Match 1B */ +- +-#define TIMER1_OVF_vect_num 9 +-#define TIMER1_OVF_vect _VECTOR(9) /* Timer/Counter1 Overflow */ +- +-#define TIMER0_COMPA_vect_num 10 +-#define TIMER0_COMPA_vect _VECTOR(10) /* Timer/Counter0 Compare Match 0A */ +- +-#define TIMER0_OVF_vect_num 11 +-#define TIMER0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ +- +-#define LIN_TC_vect_num 12 +-#define LIN_TC_vect _VECTOR(12) /* LIN Transfer Complete */ +- +-#define LIN_ERR_vect_num 13 +-#define LIN_ERR_vect _VECTOR(13) /* LIN Error */ +- +-#define SPI_STC_vect_num 14 +-#define SPI_STC_vect _VECTOR(14) /* SPI Serial Transfer Complete */ +- +-#define ADC_vect_num 15 +-#define ADC_vect _VECTOR(15) /* ADC Conversion Complete */ +- +-#define EE_RDY_vect_num 16 +-#define EE_RDY_vect _VECTOR(16) /* EEPROM Ready */ +- +-#define ANA_COMP_vect_num 17 +-#define ANA_COMP_vect _VECTOR(17) /* Analog Comparator */ +- +-#define USI_START_vect_num 18 +-#define USI_START_vect _VECTOR(18) /* USI Start */ +- +-#define USI_OVF_vect_num 19 +-#define USI_OVF_vect _VECTOR(19) /* USI Overflow */ +- +-#define _VECTORS_SIZE (20 * 4) +- +- +- +-/* Constants */ +-#define SPM_PAGESIZE (128) +-#define RAMSTART (0x100) +-#define RAMSIZE (0x1FF) +-#define RAMEND (RAMSTART + RAMSIZE - 1) /* Last On-Chip SRAM Location */ +-#define XRAMSIZE (0) +-#define XRAMEND RAMEND +-#define E2END (0x1FF) +-#define E2PAGESIZE (4) +-#define FLASHEND (0x3FFF) +- +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always ON */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ +-#define EFUSE_DEFAULT (0xFF) +- +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x94 +-#define SIGNATURE_2 0x87 +- +- +- +-#endif /* _AVR_IOTN167_H_ */ ++/* Copyright (c) 2008-2010 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++/* $Id: iotn167.h 2253 2011-09-26 14:53:41Z arcanum $ */ ++ ++/* avr/iotn167.h - definitions for ATtiny167. */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn167.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_IOTN167_H_ ++#define _AVR_IOTN167_H_ 1 ++ ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++#define PINA4 4 ++#define PINA5 5 ++#define PINA6 6 ++#define PINA7 7 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++#define DDA4 4 ++#define DDA5 5 ++#define DDA6 6 ++#define DDA7 7 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA0 0 ++#define PORTA1 1 ++#define PORTA2 2 ++#define PORTA3 3 ++#define PORTA4 4 ++#define PORTA5 5 ++#define PORTA6 6 ++#define PORTA7 7 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PORTCR _SFR_IO8(0x12) ++#define PUDA 0 ++#define PUDB 1 ++#define BBMA 4 ++#define BBMB 5 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR1 0 ++#define PSR0 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x25) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x26) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x27) ++#define TCNT00 0 ++#define TCNT01 1 ++#define TCNT02 2 ++#define TCNT03 3 ++#define TCNT04 4 ++#define TCNT05 5 ++#define TCNT06 6 ++#define TCNT07 7 ++ ++#define OCR0A _SFR_IO8(0x28) ++#define OCR00 0 ++#define OCR01 1 ++#define OCR02 2 ++#define OCR03 3 ++#define OCR04 4 ++#define OCR05 5 ++#define OCR06 6 ++#define OCR07 7 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACIRS 6 ++#define ACD 7 ++ ++#define DWDR _SFR_IO8(0x31) ++#define DWDR0 0 ++#define DWDR1 1 ++#define DWDR2 2 ++#define DWDR3 3 ++#define DWDR4 4 ++#define DWDR5 5 ++#define DWDR6 6 ++#define DWDR7 7 ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define RFLB 3 ++#define CTPB 4 ++#define SIGRD 5 ++#define RWWSB 6 ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define CLKCSR _SFR_MEM8(0x62) ++#define CLKC0 0 ++#define CLKC1 1 ++#define CLKC2 2 ++#define CLKC3 3 ++#define CLKRDY 4 ++#define CLKCCE 7 ++ ++#define CLKSELR _SFR_MEM8(0x63) ++#define CSEL0 0 ++#define CSEL1 1 ++#define CSEL2 2 ++#define CSEL3 3 ++#define CSUT0 4 ++#define CSUT1 5 ++#define COUT 6 ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSI 1 ++#define PRTIM0 2 ++#define PRTIM1 3 ++#define PRSPI 4 ++#define PRLIN 5 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define AMISCR _SFR_MEM8(0x77) ++#define ISRCEN 0 ++#define XREFEN 1 ++#define AREFEN 2 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_MEM8(0x79) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACIR0 4 ++#define ACIR1 5 ++#define ACME 6 ++#define BIN 7 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define ADC8D 4 ++#define ADC9D 5 ++#define ADC10D 6 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCCR1D _SFR_MEM8(0x83) ++#define OC1AU 0 ++#define OC1AV 1 ++#define OC1AW 2 ++#define OC1AX 3 ++#define OC1BU 4 ++#define OC1BV 5 ++#define OC1BW 6 ++#define OC1BX 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR0BUB 0 ++#define TCR0AUB 1 ++#define OCR0AUB 3 ++#define TCN0UB 4 ++#define AS0 5 ++#define EXCLK 6 ++ ++#define USICR _SFR_MEM8(0xB8) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_MEM8(0xB9) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_MEM8(0xBA) ++#define USIDR0 0 ++#define USIDR1 1 ++#define USIDR2 2 ++#define USIDR3 3 ++#define USIDR4 4 ++#define USIDR5 5 ++#define USIDR6 6 ++#define USIDR7 7 ++ ++#define USIBR _SFR_MEM8(0xBB) ++#define USIBR0 0 ++#define USIBR1 1 ++#define USIBR2 2 ++#define USIBR3 3 ++#define USIBR4 4 ++#define USIBR5 5 ++#define USIBR6 6 ++#define USIBR7 7 ++ ++#define USIPP _SFR_MEM8(0xBC) ++#define USIPOS 0 ++ ++#define LINCR _SFR_MEM8(0xC8) ++#define LCMD0 0 ++#define LCMD1 1 ++#define LCMD2 2 ++#define LENA 3 ++#define LCONF0 4 ++#define LCONF1 5 ++#define LIN13 6 ++#define LSWRES 7 ++ ++#define LINSIR _SFR_MEM8(0xC9) ++#define LRXOK 0 ++#define LTXOK 1 ++#define LIDOK 2 ++#define LERR 3 ++#define LBUSY 4 ++#define LIDST0 5 ++#define LIDST1 6 ++#define LIDST2 7 ++ ++#define LINENIR _SFR_MEM8(0xCA) ++#define LENRXOK 0 ++#define LENTXOK 1 ++#define LENIDOK 2 ++#define LENERR 3 ++ ++#define LINERR _SFR_MEM8(0xCB) ++#define LBERR 0 ++#define LCERR 1 ++#define LPERR 2 ++#define LSERR 3 ++#define LFERR 4 ++#define LOVERR 5 ++#define LTOERR 6 ++#define LABORT 7 ++ ++#define LINBTR _SFR_MEM8(0xCC) ++#define LBT0 0 ++#define LBT1 1 ++#define LBT2 2 ++#define LBT3 3 ++#define LBT4 4 ++#define LBT5 5 ++#define LDISR 7 ++ ++#define LINBRR _SFR_MEM16(0xCD) ++ ++#define LINBRRL _SFR_MEM8(0xCD) ++#define LDIV0 0 ++#define LDIV1 1 ++#define LDIV2 2 ++#define LDIV3 3 ++#define LDIV4 4 ++#define LDIV5 5 ++#define LDIV6 6 ++#define LDIV7 7 ++ ++#define LINBRRH _SFR_MEM8(0xCE) ++#define LDIV8 0 ++#define LDIV9 1 ++#define LDIV10 2 ++#define LDIV11 3 ++ ++#define LINDLR _SFR_MEM8(0xCF) ++#define LRXDL0 0 ++#define LRXDL1 1 ++#define LRXDL2 2 ++#define LRXDL3 3 ++#define LTXDL0 4 ++#define LTXDL1 5 ++#define LTXDL2 6 ++#define LTXDL3 7 ++ ++#define LINIDR _SFR_MEM8(0xD0) ++#define LID0 0 ++#define LID1 1 ++#define LID2 2 ++#define LID3 3 ++#define LID4 4 ++#define LID5 5 ++#define LP0 6 ++#define LP1 7 ++ ++#define LINSEL _SFR_MEM8(0xD1) ++#define LINDX0 0 ++#define LINDX1 1 ++#define LINDX2 2 ++#define LAINC 3 ++ ++#define LINDAT _SFR_MEM8(0xD2) ++#define LDATA0 0 ++#define LDATA1 1 ++#define LDATA2 2 ++#define LDATA3 3 ++#define LDATA4 4 ++#define LDATA5 5 ++#define LDATA6 6 ++#define LDATA7 7 ++ ++ ++ ++/* Interrupt Vectors */ ++/* Interrupt Vector 0 is the reset vector. */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ ++ ++#define PCINT0_vect_num 3 ++#define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ ++ ++#define PCINT1_vect_num 4 ++#define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 1 */ ++ ++#define WDT_vect_num 5 ++#define WDT_vect _VECTOR(5) /* Watchdog Time-Out Interrupt */ ++ ++#define TIMER1_CAPT_vect_num 6 ++#define TIMER1_CAPT_vect _VECTOR(6) /* Timer/Counter1 Capture Event */ ++ ++#define TIMER1_COMPA_vect_num 7 ++#define TIMER1_COMPA_vect _VECTOR(7) /* Timer/Counter1 Compare Match 1A */ ++ ++#define TIMER1_COMPB_vect_num 8 ++#define TIMER1_COMPB_vect _VECTOR(8) /* Timer/Counter1 Compare Match 1B */ ++ ++#define TIMER1_OVF_vect_num 9 ++#define TIMER1_OVF_vect _VECTOR(9) /* Timer/Counter1 Overflow */ ++ ++#define TIMER0_COMPA_vect_num 10 ++#define TIMER0_COMPA_vect _VECTOR(10) /* Timer/Counter0 Compare Match 0A */ ++ ++#define TIMER0_OVF_vect_num 11 ++#define TIMER0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ ++ ++#define LIN_TC_vect_num 12 ++#define LIN_TC_vect _VECTOR(12) /* LIN Transfer Complete */ ++ ++#define LIN_ERR_vect_num 13 ++#define LIN_ERR_vect _VECTOR(13) /* LIN Error */ ++ ++#define SPI_STC_vect_num 14 ++#define SPI_STC_vect _VECTOR(14) /* SPI Serial Transfer Complete */ ++ ++#define ADC_vect_num 15 ++#define ADC_vect _VECTOR(15) /* ADC Conversion Complete */ ++ ++#define EE_RDY_vect_num 16 ++#define EE_RDY_vect _VECTOR(16) /* EEPROM Ready */ ++ ++#define ANA_COMP_vect_num 17 ++#define ANA_COMP_vect _VECTOR(17) /* Analog Comparator */ ++ ++#define USI_START_vect_num 18 ++#define USI_START_vect _VECTOR(18) /* USI Start */ ++ ++#define USI_OVF_vect_num 19 ++#define USI_OVF_vect _VECTOR(19) /* USI Overflow */ ++ ++#define _VECTORS_SIZE (20 * 4) ++ ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (128) ++#define RAMSTART (0x100) ++#define RAMSIZE (0x200) ++#define RAMEND (RAMSTART + RAMSIZE - 1) /* Last On-Chip SRAM Location */ ++#define XRAMSIZE (0) ++#define XRAMEND RAMEND ++#define E2END (0x1FF) ++#define E2PAGESIZE (4) ++#define FLASHEND (0x3FFF) ++ ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always ON */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x87 ++ ++ ++ ++#endif /* _AVR_IOTN167_H_ */ +diff --git a/include/avr/iotn20.h b/include/avr/iotn20.h +index c0a0831..88b7752 100644 +--- a/include/avr/iotn20.h ++++ b/include/avr/iotn20.h +@@ -1,764 +1,764 @@ +-/* Copyright (c) 2010 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id$ */ +- +-/* avr/iotn20.h - definitions for ATtiny20 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn20.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATtiny20_H_ +-#define _AVR_ATtiny20_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +-#define PINA4 4 +-#define PINA5 5 +-#define PINA6 6 +-#define PINA7 7 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +-#define DDA4 4 +-#define DDA5 5 +-#define DDA6 6 +-#define DDA7 7 +- +-#define PORTA _SFR_IO8(0x02) +-#define PORTA0 0 +-#define PORTA1 1 +-#define PORTA2 2 +-#define PORTA3 3 +-#define PORTA4 4 +-#define PORTA5 5 +-#define PORTA6 6 +-#define PORTA7 7 +- +-#define PUEA _SFR_IO8(0x03) +-#define PUEA0 0 +-#define PUEA1 1 +-#define PUEA2 2 +-#define PUEA3 3 +-#define PUEA4 4 +-#define PUEA5 5 +-#define PUEA6 6 +-#define PUEA7 7 +- +-#define PINB _SFR_IO8(0x04) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +- +-#define DDRB _SFR_IO8(0x05) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +- +-#define PORTB _SFR_IO8(0x06) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +- +-#define PUEB _SFR_IO8(0x07) +-#define PUEB0 0 +-#define PUEB1 1 +-#define PUEB2 2 +-#define PUEB3 3 +- +-#define PORTCR _SFR_IO8(0x08) +-#define BBMA 0 +-#define BBMB 1 +- +-#define PCMSK0 _SFR_IO8(0x09) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_IO8(0x0A) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +- +-#define GIFR _SFR_IO8(0x0B) +-#define INTF0 0 +-#define PCIF0 4 +-#define PCIF1 5 +- +-#define GIMSK _SFR_IO8(0x0C) +-#define INT0 0 +-#define PCIE0 4 +-#define PCIE1 5 +- +-#define DIDR0 _SFR_IO8(0x0D) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x0E) +-#endif +-#define ADCW _SFR_IO16(0x0E) +- +-#define ADCL _SFR_IO8(0x0E) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_IO8(0x0F) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADMUX _SFR_IO8(0x10) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define REFS 6 +- +-#define ADCSRB _SFR_IO8(0x11) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ADLAR 3 +- +-#define ADCSRA _SFR_IO8(0x12) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ACSRB _SFR_IO8(0x13) +-#define ACME 2 +-#define HLEV 6 +-#define HSEL 7 +- +-#define ACSRA _SFR_IO8(0x14) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define OCR0B _SFR_IO8(0x15) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define OCR0A _SFR_IO8(0x16) +-#define OCR0_0 0 +-#define OCR0_1 1 +-#define OCR0_2 2 +-#define OCR0_3 3 +-#define OCR0_4 4 +-#define OCR0_5 5 +-#define OCR0_6 6 +-#define OCR0_7 7 +- +-#define TCNT0 _SFR_IO8(0x17) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define TCCR0B _SFR_IO8(0x18) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCCR0A _SFR_IO8(0x19) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define ICR1 _SFR_IO16(0x1A) +- +-#define ICR1L _SFR_IO8(0x1A) +-#define ICR1_0 0 +-#define ICR1_1 1 +-#define ICR1_2 2 +-#define ICR1_3 3 +-#define ICR1_4 4 +-#define ICR1_5 5 +-#define ICR1_6 6 +-#define ICR1_7 7 +- +-#define ICR1H _SFR_IO8(0x1B) +-#define ICR1_8 0 +-#define ICR1_9 1 +-#define ICR1_10 2 +-#define ICR1_11 3 +-#define ICR1_12 4 +-#define ICR1_13 5 +-#define ICR1_14 6 +-#define ICR1_15 7 +- +-#define OCR1B _SFR_IO16(0x1C) +- +-#define OCR1BL _SFR_IO8(0x1C) +-#define OCR1B0 0 +-#define OCR1B1 1 +-#define OCR1B2 2 +-#define OCR1B3 3 +-#define OCR1B4 4 +-#define OCR1B5 5 +-#define OCR1B6 6 +-#define OCR1B7 7 +- +-#define OCR1BH _SFR_IO8(0x1D) +-#define OCR1B8 0 +-#define OCR1B9 1 +-#define OCR1B10 2 +-#define OCR1B11 3 +-#define OCR1B12 4 +-#define OCR1B13 5 +-#define OCR1B14 6 +-#define OCR1B15 7 +- +-#define OCR1A _SFR_IO16(0x1E) +- +-#define OCR1AL _SFR_IO8(0x1E) +-#define OCR1A0 0 +-#define OCR1A1 1 +-#define OCR1A2 2 +-#define OCR1A3 3 +-#define OCR1A4 4 +-#define OCR1A5 5 +-#define OCR1A6 6 +-#define OCR1A7 7 +- +-#define OCR1AH _SFR_IO8(0x1F) +-#define OCR1A8 0 +-#define OCR1A9 1 +-#define OCR1A10 2 +-#define OCR1A11 3 +-#define OCR1A12 4 +-#define OCR1A13 5 +-#define OCR1A14 6 +-#define OCR1A15 7 +- +-#define TCNT1 _SFR_IO16(0x20) +- +-#define TCNT1L _SFR_IO8(0x20) +-#define TCNT1_0 0 +-#define TCNT1_1 1 +-#define TCNT1_2 2 +-#define TCNT1_3 3 +-#define TCNT1_4 4 +-#define TCNT1_5 5 +-#define TCNT1_6 6 +-#define TCNT1_7 7 +- +-#define TCNT1H _SFR_IO8(0x21) +-#define TCNT1_8 0 +-#define TCNT1_9 1 +-#define TCNT1_10 2 +-#define TCNT1_11 3 +-#define TCNT1_12 4 +-#define TCNT1_13 5 +-#define TCNT1_14 6 +-#define TCNT1_15 7 +- +-#define TCCR1C _SFR_IO8(0x22) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCCR1B _SFR_IO8(0x23) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1A _SFR_IO8(0x24) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TIFR _SFR_IO8(0x25) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +-#define TOV1 3 +-#define OCF1A 4 +-#define OCF1B 5 +-#define ICF1 7 +- +-#define TIMSK _SFR_IO8(0x26) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +-#define TOIE1 3 +-#define OCIE1A 4 +-#define OCIE1B 5 +-#define ICIE1 7 +- +-#define GTCCR _SFR_IO8(0x27) +-#define PSR 0 +-#define TSM 7 +- +-#define TWSD _SFR_IO8(0x28) +-#define TWSD0 0 +-#define TWSD1 1 +-#define TWSD2 2 +-#define TWSD3 3 +-#define TWSD4 4 +-#define TWSD5 5 +-#define TWSD6 6 +-#define TWSD7 7 +- +-#define TWSAM _SFR_IO8(0x29) +-#define TWAE 0 +-#define TWSAM1 1 +-#define TWSAM2 2 +-#define TWSAM3 3 +-#define TWSAM4 4 +-#define TWSAM5 5 +-#define TWSAM6 6 +-#define TWSAM7 7 +- +-#define TWSA _SFR_IO8(0x2A) +-#define TWSA0 0 +-#define TWSA1 1 +-#define TWSA2 2 +-#define TWSA3 3 +-#define TWSA4 4 +-#define TWSA5 5 +-#define TWSA6 6 +-#define TWSA7 7 +- +-#define TWSSRA _SFR_IO8(0x2B) +-#define TWAS 0 +-#define TWDIR 1 +-#define TWBE 2 +-#define TWC 3 +-#define TWRA 4 +-#define TWCH 5 +-#define TWASIF 6 +-#define TWDIF 7 +- +-#define TWSCRB _SFR_IO8(0x2C) +-#define TWCMD0 0 +-#define TWCMD1 1 +-#define TWAA 2 +- +-#define TWSCRA _SFR_IO8(0x2D) +-#define TWSME 0 +-#define TWPME 1 +-#define TWSIE 2 +-#define TWEN 3 +-#define TWASIE 4 +-#define TWDIE 5 +-#define TWSHE 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define SPSR _SFR_IO8(0x2F) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPCR _SFR_IO8(0x30) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define WDTCSR _SFR_IO8(0x31) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define NVMCSR _SFR_IO8(0x32) +-#define NVMBSY 7 +- +-#define NVMCMD _SFR_IO8(0x33) +-#define NVMCMD0 0 +-#define NVMCMD1 1 +-#define NVMCMD2 2 +-#define NVMCMD3 3 +-#define NVMCMD4 4 +-#define NVMCMD5 5 +- +-#define QTCSR _SFR_IO8(0x34) +- +-#define PRR _SFR_IO8(0x35) +-#define PRADC 0 +-#define PRTIM0 1 +-#define PRTIM1 2 +-#define PRSPI 3 +-#define PRTWI 4 +- +-#define CLKPSR _SFR_IO8(0x36) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +- +-#define CLKMSR _SFR_IO8(0x37) +-#define CLKMS0 0 +-#define CLKMS1 1 +- +-#define OSCCAL _SFR_IO8(0x39) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define MCUCR _SFR_IO8(0x3A) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +-#define BODS 4 +-#define ISC00 6 +-#define ISC01 7 +- +-#define RSTFLR _SFR_IO8(0x3B) +-#define PORF 0 +-#define EXTRF 1 +-#define WDRF 3 +- +-#define CCP _SFR_IO8(0x3C) +-#define CCP0 0 +-#define CCP1 1 +-#define CCP2 2 +-#define CCP3 3 +-#define CCP4 4 +-#define CCP5 5 +-#define CCP6 6 +-#define CCP7 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ +-#define PCINT1_vect_num 3 +-#define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */ -#define WDT_vect_num 4 -#define WDT_vect _VECTOR(4) /* Watchdog Time-out */ -#define TIM1_CAPT_vect_num 5 @@ -62316,2760 +246999,5156 @@ index 01c8531..315f422 100644 -#define SPI_vect _VECTOR(15) /* Serial Peripheral Interface */ -#define QTRIP_vect_num 16 -#define QTRIP_vect _VECTOR(16) /* Touch Sensing */ -+#define PCINT2_vect_num 4 -+#define PCINT2_vect _VECTOR(4) /* Pin Change Interrupt Request 2 */ -+#define WDT_vect_num 5 -+#define WDT_vect _VECTOR(5) /* Watchdog Time-out */ -+#define TIM1_CAPT_vect_num 6 -+#define TIM1_CAPT_vect _VECTOR(6) /* Timer/Counter1 Input Capture */ -+#define TIM1_COMPA_vect_num 7 -+#define TIM1_COMPA_vect _VECTOR(7) /* Timer/Counter1 Compare Match A */ -+#define TIM1_COMPB_vect_num 8 -+#define TIM1_COMPB_vect _VECTOR(8) /* Timer/Counter1 Compare Match B */ -+#define TIM1_OVF_vect_num 9 -+#define TIM1_OVF_vect _VECTOR(9) /* Timer/Counter1 Overflow */ -+#define TIM0_COMPA_vect_num 10 -+#define TIM0_COMPA_vect _VECTOR(10) /* Timer/Counter0 Compare Match A */ -+#define TIM0_COMPB_vect_num 11 -+#define TIM0_COMPB_vect _VECTOR(11) /* Timer/Counter0 Compare Match B */ -+#define TIM0_OVF_vect_num 12 -+#define TIM0_OVF_vect _VECTOR(12) /* Timer/Counter0 Overflow */ -+#define ANA_COMP_vect_num 13 -+#define ANA_COMP_vect _VECTOR(13) /* Analog Comparator */ -+#define ADC_ADC_vect_num 14 -+#define ADC_ADC_vect _VECTOR(14) /* Conversion Complete */ -+#define TWI_SLAVE_vect_num 15 -+#define TWI_SLAVE_vect _VECTOR(15) /* Two-Wire Interface */ -+#define SPI_vect_num 16 -+#define SPI_vect _VECTOR(16) /* Serial Peripheral Interface */ -+#define QTRIP_vect_num 17 -+#define QTRIP_vect _VECTOR(17) /* Touch Sensing */ - - #define _VECTOR_SIZE 2 /* Size of individual vector. */ - #define _VECTORS_SIZE (17 * _VECTOR_SIZE) -diff --git a/include/avr/iotn4313.h b/include/avr/iotn4313.h -index bdef413..e67c59a 100644 ---- a/include/avr/iotn4313.h -+++ b/include/avr/iotn4313.h -@@ -68,7 +68,12 @@ - #define USBS 3 - #define UPM0 4 - #define UPM1 5 +- +-#define _VECTOR_SIZE 2 /* Size of individual vector. */ +-#define _VECTORS_SIZE (17 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (64) +-#define RAMSTART (0x40) +-#define RAMSIZE (128) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x0) +-#define E2PAGESIZE (0) +-#define FLASHEND (0x7FF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 0 +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x91 +-#define SIGNATURE_2 0x0F +- +- +-/* Device Pin Definitions */ +-#define ADC4_DDR DDRCINT +-#define ADC4_PORT PORTCINT +-#define ADC4_PIN PINCINT +-#define ADC4_BIT INT4 +- +-#define ADC3_DDR DDRCINT +-#define ADC3_PORT PORTCINT +-#define ADC3_PIN PINCINT +-#define ADC3_BIT INT3 +- +-#define AIN1_DDR DDRCINT +-#define AIN1_PORT PORTCINT +-#define AIN1_PIN PINCINT +-#define AIN1_BIT INT2 +- +-#define ADC2_DDR DDRCINT +-#define ADC2_PORT PORTCINT +-#define ADC2_PIN PINCINT +-#define ADC2_BIT INT2 +- +-#define AIN0_DDR DDRCINT +-#define AIN0_PORT PORTCINT +-#define AIN0_PIN PINCINT +-#define AIN0_BIT INT1 +- +-#define ADC1_DDR DDRCINT +-#define ADC1_PORT PORTCINT +-#define ADC1_PIN PINCINT +-#define ADC1_BIT INT1 +- +-#define ADC0_DDR DDRCINT +-#define ADC0_PORT PORTCINT +-#define ADC0_PIN PINCINT +-#define ADC0_BIT INT0 +- +-#define T0_DDR DDRCLKI +-#define T0_PORT PORTCLKI +-#define T0_PIN PINCLKI +-#define T0_BIT CLKI +- +-#define TPICLK_DDR DDRCLKI +-#define TPICLK_PORT PORTCLKI +-#define TPICLK_PIN PINCLKI +-#define TPICLK_BIT CLKI +- +-#define PCINT8_DDR DDRCLKI +-#define PCINT8_PORT PORTCLKI +-#define PCINT8_PIN PINCLKI +-#define PCINT8_BIT CLKI +- +-#define SDA_DDR DDROC1A +-#define SDA_PORT PORTOC1A +-#define SDA_PIN PINOC1A +-#define SDA_BIT OC1A +- +-#define MOSI_DDR DDROC1A +-#define MOSI_PORT PORTOC1A +-#define MOSI_PIN PINOC1A +-#define MOSI_BIT OC1A +- +-#define TPIDATA_DDR DDROC1A +-#define TPIDATA_PORT PORTOC1A +-#define TPIDATA_PIN PINOC1A +-#define TPIDATA_BIT OC1A +- +-#define PCINT9_DDR DDROC1A +-#define PCINT9_PORT PORTOC1A +-#define PCINT9_PIN PINOC1A +-#define PCINT9_BIT OC1A +- +-#define PCINT11_DDR DDRRESET +-#define PCINT11_PORT PORTRESET +-#define PCINT11_PIN PINRESET +-#define PCINT11_BIT RESET +- +-#define OC0A_DDR DDRCKOUT +-#define OC0A_PORT PORTCKOUT +-#define OC0A_PIN PINCKOUT +-#define OC0A_BIT CKOUT +- +-#define OC1B_DDR DDRCKOUT +-#define OC1B_PORT PORTCKOUT +-#define OC1B_PIN PINCKOUT +-#define OC1B_BIT CKOUT +- +-#define MISO_DDR DDRCKOUT +-#define MISO_PORT PORTCKOUT +-#define MISO_PIN PINCKOUT +-#define MISO_BIT CKOUT +- +-#define INT0_DDR DDRCKOUT +-#define INT0_PORT PORTCKOUT +-#define INT0_PIN PINCKOUT +-#define INT0_BIT CKOUT +- +-#define PCINT10_DDR DDRCKOUT +-#define PCINT10_PORT PORTCKOUT +-#define PCINT10_PIN PINCKOUT +-#define PCINT10_BIT CKOUT +- +-#define OC0B_DDR DDR(ADC +-#define OC0B_PORT PORT(ADC +-#define OC0B_PIN PIN(ADC +-#define OC0B_BIT (ADC7 +- +-#define ICP1_DDR DDR(ADC +-#define ICP1_PORT PORT(ADC +-#define ICP1_PIN PIN(ADC +-#define ICP1_BIT (ADC7 +- +-#define T1_DDR DDR(ADC +-#define T1_PORT PORT(ADC +-#define T1_PIN PIN(ADC +-#define T1_BIT (ADC7 +- +-#define SCL_DDR DDR(ADC +-#define SCL_PORT PORT(ADC +-#define SCL_PIN PIN(ADC +-#define SCL_BIT (ADC7 +- +-#define SCK_DDR DDR(ADC +-#define SCK_PORT PORT(ADC +-#define SCK_PIN PIN(ADC +-#define SCK_BIT (ADC7 +- +-#define PCINT7_DDR DDR(ADC +-#define PCINT7_PORT PORT(ADC +-#define PCINT7_PIN PIN(ADC +-#define PCINT7_BIT (ADC7 +- +-#define SS_DDR DDRADC +-#define SS_PORT PORTADC +-#define SS_PIN PINADC +-#define SS_BIT ADC6 +- +-#define PCINT6_DDR DDRADC +-#define PCINT6_PORT PORTADC +-#define PCINT6_PIN PINADC +-#define PCINT6_BIT ADC6 +- +-#define PCINT5_DDR DDRADC +-#define PCINT5_PORT PORTADC +-#define PCINT5_PIN PINADC +-#define PCINT5_BIT ADC5 +- +-#endif /* _AVR_ATtiny20_H_ */ +- ++/* Copyright (c) 2010 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id$ */ ++ ++/* avr/iotn20.h - definitions for ATtiny20 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn20.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATtiny20_H_ ++#define _AVR_ATtiny20_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++#define PINA4 4 ++#define PINA5 5 ++#define PINA6 6 ++#define PINA7 7 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++#define DDA4 4 ++#define DDA5 5 ++#define DDA6 6 ++#define DDA7 7 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA0 0 ++#define PORTA1 1 ++#define PORTA2 2 ++#define PORTA3 3 ++#define PORTA4 4 ++#define PORTA5 5 ++#define PORTA6 6 ++#define PORTA7 7 ++ ++#define PUEA _SFR_IO8(0x03) ++#define PUEA0 0 ++#define PUEA1 1 ++#define PUEA2 2 ++#define PUEA3 3 ++#define PUEA4 4 ++#define PUEA5 5 ++#define PUEA6 6 ++#define PUEA7 7 ++ ++#define PINB _SFR_IO8(0x04) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++ ++#define DDRB _SFR_IO8(0x05) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++ ++#define PORTB _SFR_IO8(0x06) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++ ++#define PUEB _SFR_IO8(0x07) ++#define PUEB0 0 ++#define PUEB1 1 ++#define PUEB2 2 ++#define PUEB3 3 ++ ++#define PORTCR _SFR_IO8(0x08) ++#define BBMA 0 ++#define BBMB 1 ++ ++#define PCMSK0 _SFR_IO8(0x09) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_IO8(0x0A) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++ ++#define GIFR _SFR_IO8(0x0B) ++#define INTF0 0 ++#define PCIF0 4 ++#define PCIF1 5 ++ ++#define GIMSK _SFR_IO8(0x0C) ++#define INT0 0 ++#define PCIE0 4 ++#define PCIE1 5 ++ ++#define DIDR0 _SFR_IO8(0x0D) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x0E) ++#endif ++#define ADCW _SFR_IO16(0x0E) ++ ++#define ADCL _SFR_IO8(0x0E) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_IO8(0x0F) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADMUX _SFR_IO8(0x10) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define REFS 6 ++ ++#define ADCSRB _SFR_IO8(0x11) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ADLAR 3 ++ ++#define ADCSRA _SFR_IO8(0x12) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ACSRB _SFR_IO8(0x13) ++#define ACME 2 ++#define HLEV 6 ++#define HSEL 7 ++ ++#define ACSRA _SFR_IO8(0x14) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCR0B _SFR_IO8(0x15) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define OCR0A _SFR_IO8(0x16) ++#define OCR0_0 0 ++#define OCR0_1 1 ++#define OCR0_2 2 ++#define OCR0_3 3 ++#define OCR0_4 4 ++#define OCR0_5 5 ++#define OCR0_6 6 ++#define OCR0_7 7 ++ ++#define TCNT0 _SFR_IO8(0x17) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define TCCR0B _SFR_IO8(0x18) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCCR0A _SFR_IO8(0x19) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define ICR1 _SFR_IO16(0x1A) ++ ++#define ICR1L _SFR_IO8(0x1A) ++#define ICR1_0 0 ++#define ICR1_1 1 ++#define ICR1_2 2 ++#define ICR1_3 3 ++#define ICR1_4 4 ++#define ICR1_5 5 ++#define ICR1_6 6 ++#define ICR1_7 7 ++ ++#define ICR1H _SFR_IO8(0x1B) ++#define ICR1_8 0 ++#define ICR1_9 1 ++#define ICR1_10 2 ++#define ICR1_11 3 ++#define ICR1_12 4 ++#define ICR1_13 5 ++#define ICR1_14 6 ++#define ICR1_15 7 ++ ++#define OCR1B _SFR_IO16(0x1C) ++ ++#define OCR1BL _SFR_IO8(0x1C) ++#define OCR1B0 0 ++#define OCR1B1 1 ++#define OCR1B2 2 ++#define OCR1B3 3 ++#define OCR1B4 4 ++#define OCR1B5 5 ++#define OCR1B6 6 ++#define OCR1B7 7 ++ ++#define OCR1BH _SFR_IO8(0x1D) ++#define OCR1B8 0 ++#define OCR1B9 1 ++#define OCR1B10 2 ++#define OCR1B11 3 ++#define OCR1B12 4 ++#define OCR1B13 5 ++#define OCR1B14 6 ++#define OCR1B15 7 ++ ++#define OCR1A _SFR_IO16(0x1E) ++ ++#define OCR1AL _SFR_IO8(0x1E) ++#define OCR1A0 0 ++#define OCR1A1 1 ++#define OCR1A2 2 ++#define OCR1A3 3 ++#define OCR1A4 4 ++#define OCR1A5 5 ++#define OCR1A6 6 ++#define OCR1A7 7 ++ ++#define OCR1AH _SFR_IO8(0x1F) ++#define OCR1A8 0 ++#define OCR1A9 1 ++#define OCR1A10 2 ++#define OCR1A11 3 ++#define OCR1A12 4 ++#define OCR1A13 5 ++#define OCR1A14 6 ++#define OCR1A15 7 ++ ++#define TCNT1 _SFR_IO16(0x20) ++ ++#define TCNT1L _SFR_IO8(0x20) ++#define TCNT1_0 0 ++#define TCNT1_1 1 ++#define TCNT1_2 2 ++#define TCNT1_3 3 ++#define TCNT1_4 4 ++#define TCNT1_5 5 ++#define TCNT1_6 6 ++#define TCNT1_7 7 ++ ++#define TCNT1H _SFR_IO8(0x21) ++#define TCNT1_8 0 ++#define TCNT1_9 1 ++#define TCNT1_10 2 ++#define TCNT1_11 3 ++#define TCNT1_12 4 ++#define TCNT1_13 5 ++#define TCNT1_14 6 ++#define TCNT1_15 7 ++ ++#define TCCR1C _SFR_IO8(0x22) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCCR1B _SFR_IO8(0x23) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1A _SFR_IO8(0x24) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TIFR _SFR_IO8(0x25) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++#define TOV1 3 ++#define OCF1A 4 ++#define OCF1B 5 ++#define ICF1 7 ++ ++#define TIMSK _SFR_IO8(0x26) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++#define TOIE1 3 ++#define OCIE1A 4 ++#define OCIE1B 5 ++#define ICIE1 7 ++ ++#define GTCCR _SFR_IO8(0x27) ++#define PSR 0 ++#define TSM 7 ++ ++#define TWSD _SFR_IO8(0x28) ++#define TWSD0 0 ++#define TWSD1 1 ++#define TWSD2 2 ++#define TWSD3 3 ++#define TWSD4 4 ++#define TWSD5 5 ++#define TWSD6 6 ++#define TWSD7 7 ++ ++#define TWSAM _SFR_IO8(0x29) ++#define TWAE 0 ++#define TWSAM1 1 ++#define TWSAM2 2 ++#define TWSAM3 3 ++#define TWSAM4 4 ++#define TWSAM5 5 ++#define TWSAM6 6 ++#define TWSAM7 7 ++ ++#define TWSA _SFR_IO8(0x2A) ++#define TWSA0 0 ++#define TWSA1 1 ++#define TWSA2 2 ++#define TWSA3 3 ++#define TWSA4 4 ++#define TWSA5 5 ++#define TWSA6 6 ++#define TWSA7 7 ++ ++#define TWSSRA _SFR_IO8(0x2B) ++#define TWAS 0 ++#define TWDIR 1 ++#define TWBE 2 ++#define TWC 3 ++#define TWRA 4 ++#define TWCH 5 ++#define TWASIF 6 ++#define TWDIF 7 ++ ++#define TWSCRB _SFR_IO8(0x2C) ++#define TWCMD0 0 ++#define TWCMD1 1 ++#define TWAA 2 ++ ++#define TWSCRA _SFR_IO8(0x2D) ++#define TWSME 0 ++#define TWPME 1 ++#define TWSIE 2 ++#define TWEN 3 ++#define TWASIE 4 ++#define TWDIE 5 ++#define TWSHE 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define SPSR _SFR_IO8(0x2F) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPCR _SFR_IO8(0x30) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define WDTCSR _SFR_IO8(0x31) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define NVMCSR _SFR_IO8(0x32) ++#define NVMBSY 7 ++ ++#define NVMCMD _SFR_IO8(0x33) ++#define NVMCMD0 0 ++#define NVMCMD1 1 ++#define NVMCMD2 2 ++#define NVMCMD3 3 ++#define NVMCMD4 4 ++#define NVMCMD5 5 ++ ++#define QTCSR _SFR_IO8(0x34) ++ ++#define PRR _SFR_IO8(0x35) ++#define PRADC 0 ++#define PRTIM0 1 ++#define PRTIM1 2 ++#define PRSPI 3 ++#define PRTWI 4 ++ ++#define CLKPSR _SFR_IO8(0x36) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++ ++#define CLKMSR _SFR_IO8(0x37) ++#define CLKMS0 0 ++#define CLKMS1 1 ++ ++#define OSCCAL _SFR_IO8(0x39) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define MCUCR _SFR_IO8(0x3A) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++#define BODS 4 ++#define ISC00 6 ++#define ISC01 7 ++ ++#define RSTFLR _SFR_IO8(0x3B) ++#define PORF 0 ++#define EXTRF 1 ++#define WDRF 3 ++ ++#define CCP _SFR_IO8(0x3C) ++#define CCP0 0 ++#define CCP1 1 ++#define CCP2 2 ++#define CCP3 3 ++#define CCP4 4 ++#define CCP5 5 ++#define CCP6 6 ++#define CCP7 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect_num 3 ++#define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */ ++#define WDT_vect_num 4 ++#define WDT_vect _VECTOR(4) /* Watchdog Time-out */ ++#define TIM1_CAPT_vect_num 5 ++#define TIM1_CAPT_vect _VECTOR(5) /* Timer/Counter1 Input Capture */ ++#define TIM1_COMPA_vect_num 6 ++#define TIM1_COMPA_vect _VECTOR(6) /* Timer/Counter1 Compare Match A */ ++#define TIM1_COMPB_vect_num 7 ++#define TIM1_COMPB_vect _VECTOR(7) /* Timer/Counter1 Compare Match B */ ++#define TIM1_OVF_vect_num 8 ++#define TIM1_OVF_vect _VECTOR(8) /* Timer/Counter1 Overflow */ ++#define TIM0_COMPA_vect_num 9 ++#define TIM0_COMPA_vect _VECTOR(9) /* Timer/Counter0 Compare Match A */ ++#define TIM0_COMPB_vect_num 10 ++#define TIM0_COMPB_vect _VECTOR(10) /* Timer/Counter0 Compare Match B */ ++#define TIM0_OVF_vect_num 11 ++#define TIM0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ ++#define ANA_COMP_vect_num 12 ++#define ANA_COMP_vect _VECTOR(12) /* Analog Comparator */ ++#define ADC_ADC_vect_num 13 ++#define ADC_ADC_vect _VECTOR(13) /* Conversion Complete */ ++#define TWI_SLAVE_vect_num 14 ++#define TWI_SLAVE_vect _VECTOR(14) /* Two-Wire Interface */ ++#define SPI_vect_num 15 ++#define SPI_vect _VECTOR(15) /* Serial Peripheral Interface */ ++#define QTRIP_vect_num 16 ++#define QTRIP_vect _VECTOR(16) /* Touch Sensing */ ++ ++#define _VECTOR_SIZE 2 /* Size of individual vector. */ ++#define _VECTORS_SIZE (17 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (64) ++#define RAMSTART (0x40) ++#define RAMSIZE (128) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x0) ++#define E2PAGESIZE (0) ++#define FLASHEND (0x7FF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 0 ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x91 ++#define SIGNATURE_2 0x0F ++ ++ ++/* Device Pin Definitions */ ++#define ADC4_DDR DDRCINT ++#define ADC4_PORT PORTCINT ++#define ADC4_PIN PINCINT ++#define ADC4_BIT INT4 ++ ++#define ADC3_DDR DDRCINT ++#define ADC3_PORT PORTCINT ++#define ADC3_PIN PINCINT ++#define ADC3_BIT INT3 ++ ++#define AIN1_DDR DDRCINT ++#define AIN1_PORT PORTCINT ++#define AIN1_PIN PINCINT ++#define AIN1_BIT INT2 ++ ++#define ADC2_DDR DDRCINT ++#define ADC2_PORT PORTCINT ++#define ADC2_PIN PINCINT ++#define ADC2_BIT INT2 ++ ++#define AIN0_DDR DDRCINT ++#define AIN0_PORT PORTCINT ++#define AIN0_PIN PINCINT ++#define AIN0_BIT INT1 ++ ++#define ADC1_DDR DDRCINT ++#define ADC1_PORT PORTCINT ++#define ADC1_PIN PINCINT ++#define ADC1_BIT INT1 ++ ++#define ADC0_DDR DDRCINT ++#define ADC0_PORT PORTCINT ++#define ADC0_PIN PINCINT ++#define ADC0_BIT INT0 ++ ++#define T0_DDR DDRCLKI ++#define T0_PORT PORTCLKI ++#define T0_PIN PINCLKI ++#define T0_BIT CLKI ++ ++#define TPICLK_DDR DDRCLKI ++#define TPICLK_PORT PORTCLKI ++#define TPICLK_PIN PINCLKI ++#define TPICLK_BIT CLKI ++ ++#define PCINT8_DDR DDRCLKI ++#define PCINT8_PORT PORTCLKI ++#define PCINT8_PIN PINCLKI ++#define PCINT8_BIT CLKI ++ ++#define SDA_DDR DDROC1A ++#define SDA_PORT PORTOC1A ++#define SDA_PIN PINOC1A ++#define SDA_BIT OC1A ++ ++#define MOSI_DDR DDROC1A ++#define MOSI_PORT PORTOC1A ++#define MOSI_PIN PINOC1A ++#define MOSI_BIT OC1A ++ ++#define TPIDATA_DDR DDROC1A ++#define TPIDATA_PORT PORTOC1A ++#define TPIDATA_PIN PINOC1A ++#define TPIDATA_BIT OC1A ++ ++#define PCINT9_DDR DDROC1A ++#define PCINT9_PORT PORTOC1A ++#define PCINT9_PIN PINOC1A ++#define PCINT9_BIT OC1A ++ ++#define PCINT11_DDR DDRRESET ++#define PCINT11_PORT PORTRESET ++#define PCINT11_PIN PINRESET ++#define PCINT11_BIT RESET ++ ++#define OC0A_DDR DDRCKOUT ++#define OC0A_PORT PORTCKOUT ++#define OC0A_PIN PINCKOUT ++#define OC0A_BIT CKOUT ++ ++#define OC1B_DDR DDRCKOUT ++#define OC1B_PORT PORTCKOUT ++#define OC1B_PIN PINCKOUT ++#define OC1B_BIT CKOUT ++ ++#define MISO_DDR DDRCKOUT ++#define MISO_PORT PORTCKOUT ++#define MISO_PIN PINCKOUT ++#define MISO_BIT CKOUT ++ ++#define INT0_DDR DDRCKOUT ++#define INT0_PORT PORTCKOUT ++#define INT0_PIN PINCKOUT ++#define INT0_BIT CKOUT ++ ++#define PCINT10_DDR DDRCKOUT ++#define PCINT10_PORT PORTCKOUT ++#define PCINT10_PIN PINCKOUT ++#define PCINT10_BIT CKOUT ++ ++#define OC0B_DDR DDR(ADC ++#define OC0B_PORT PORT(ADC ++#define OC0B_PIN PIN(ADC ++#define OC0B_BIT (ADC7 ++ ++#define ICP1_DDR DDR(ADC ++#define ICP1_PORT PORT(ADC ++#define ICP1_PIN PIN(ADC ++#define ICP1_BIT (ADC7 ++ ++#define T1_DDR DDR(ADC ++#define T1_PORT PORT(ADC ++#define T1_PIN PIN(ADC ++#define T1_BIT (ADC7 ++ ++#define SCL_DDR DDR(ADC ++#define SCL_PORT PORT(ADC ++#define SCL_PIN PIN(ADC ++#define SCL_BIT (ADC7 ++ ++#define SCK_DDR DDR(ADC ++#define SCK_PORT PORT(ADC ++#define SCK_PIN PIN(ADC ++#define SCK_BIT (ADC7 ++ ++#define PCINT7_DDR DDR(ADC ++#define PCINT7_PORT PORT(ADC ++#define PCINT7_PIN PIN(ADC ++#define PCINT7_BIT (ADC7 ++ ++#define SS_DDR DDRADC ++#define SS_PORT PORTADC ++#define SS_PIN PINADC ++#define SS_BIT ADC6 ++ ++#define PCINT6_DDR DDRADC ++#define PCINT6_PORT PORTADC ++#define PCINT6_PIN PINADC ++#define PCINT6_BIT ADC6 ++ ++#define PCINT5_DDR DDRADC ++#define PCINT5_PORT PORTADC ++#define PCINT5_PIN PINADC ++#define PCINT5_BIT ADC5 ++ ++#endif /* _AVR_ATtiny20_H_ */ ++ +diff --git a/include/avr/iotn22.h b/include/avr/iotn22.h +index c7e8c38..d8f35d2 100644 +--- a/include/avr/iotn22.h ++++ b/include/avr/iotn22.h +@@ -1,218 +1,219 @@ +-/* Copyright (c) 2002, Marek Michalkiewicz +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn22.h 2236 2011-03-17 21:53:39Z arcanum $ */ +- +-/* avr/iotn22.h - definitions for ATtiny22 */ +- +-#ifndef _AVR_IOTN22_H_ +-#define _AVR_IOTN22_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn22.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* Input Pins, Port B */ +-#define PINB _SFR_IO8(0x16) +- +-/* Data Direction Register, Port B */ +-#define DDRB _SFR_IO8(0x17) +- +-/* Data Register, Port B */ +-#define PORTB _SFR_IO8(0x18) +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO8(0x1E) +-#define EEARL _SFR_IO8(0x1E) +- +-/* Watchdog Timer Control Register */ +-#define WDTCR _SFR_IO8(0x21) +- +-/* Timer/Counter 0 */ +-#define TCNT0 _SFR_IO8(0x32) +- +-/* Timer/Counter 0 Control Register */ +-#define TCCR0 _SFR_IO8(0x33) +- +-/* MCU Status Register */ +-#define MCUSR _SFR_IO8(0x34) +- +-/* MCU general Control Register */ +-#define MCUCR _SFR_IO8(0x35) +- +-/* Timer/Counter Interrupt Flag register */ +-#define TIFR _SFR_IO8(0x38) +- +-/* Timer/Counter Interrupt MaSK register */ +-#define TIMSK _SFR_IO8(0x39) +- +-/* General Interrupt Flag register */ +-#define GIFR _SFR_IO8(0x3A) +- +-/* General Interrupt MaSK register */ +-#define GIMSK _SFR_IO8(0x3B) +- +-/* 0x3D SP */ +- +-/* 0x3F SREG */ +- +-/* Interrupt vectors */ +- +-/* External Interrupt 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF0_vect_num 2 +-#define TIMER0_OVF0_vect _VECTOR(2) +-#define SIG_OVERFLOW0 _VECTOR(2) +- +-#define _VECTORS_SIZE 6 +- +-/* +- The Register Bit names are represented by their bit number (0-7). +- */ +- +-/* General Interrupt MaSK register */ +-#define INT0 6 +-#define INTF0 6 +- +-/* General Interrupt Flag Register */ +-#define TOIE0 1 +-#define TOV0 1 +- +-/* MCU general Control Register */ +-#define SE 5 +-#define SM 4 +-#define ISC01 1 +-#define ISC00 0 +- +-/* Timer/Counter 0 Control Register */ +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* Watchdog Timer Control Register */ +-#define WDTOE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* +- PB2 = SCK/T0 +- PB1 = MISO/INT0 +- PB0 = MOSI +- */ +- +-/* Data Register, Port B */ +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* Data Direction Register, Port B */ +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* Input Pins, Port B */ +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* EEPROM Control Register */ +-#define EERIE 3 +-#define EEMWE 2 +-#define EEWE 1 +-#define EERE 0 +- +-/* Constants */ +-#define RAMEND 0xDF +-#define XRAMEND RAMEND +-#define E2END 0x7F +-#define E2PAGESIZE 0 +-#define FLASHEND 0x07FF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 1 +- +-/* Fuse Byte */ +-#define FUSE_CKSEL (unsigned char)~_BV(0) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_DEFAULT (FUSE_SPIEN) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x91 +-#define SIGNATURE_2 0x06 +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_OVERFLOW0 +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +-#endif /* _AVR_IOTN22_H_ */ ++/* Copyright (c) 2002, Marek Michalkiewicz ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn22.h 2236 2011-03-17 21:53:39Z arcanum $ */ ++ ++/* avr/iotn22.h - definitions for ATtiny22 */ ++ ++#ifndef _AVR_IOTN22_H_ ++#define _AVR_IOTN22_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn22.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* Input Pins, Port B */ ++#define PINB _SFR_IO8(0x16) ++ ++/* Data Direction Register, Port B */ ++#define DDRB _SFR_IO8(0x17) ++ ++/* Data Register, Port B */ ++#define PORTB _SFR_IO8(0x18) ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO8(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++ ++/* Watchdog Timer Control Register */ ++#define WDTCR _SFR_IO8(0x21) ++ ++/* Timer/Counter 0 */ ++#define TCNT0 _SFR_IO8(0x32) ++ ++/* Timer/Counter 0 Control Register */ ++#define TCCR0 _SFR_IO8(0x33) ++ ++/* MCU Status Register */ ++#define MCUSR _SFR_IO8(0x34) ++ ++/* MCU general Control Register */ ++#define MCUCR _SFR_IO8(0x35) ++ ++/* Timer/Counter Interrupt Flag register */ ++#define TIFR _SFR_IO8(0x38) ++ ++/* Timer/Counter Interrupt MaSK register */ ++#define TIMSK _SFR_IO8(0x39) ++ ++/* General Interrupt Flag register */ ++#define GIFR _SFR_IO8(0x3A) ++ ++/* General Interrupt MaSK register */ ++#define GIMSK _SFR_IO8(0x3B) ++ ++/* 0x3D SP */ ++ ++/* 0x3F SREG */ ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF0_vect_num 2 ++#define TIMER0_OVF0_vect _VECTOR(2) ++#define SIG_OVERFLOW0 _VECTOR(2) ++ ++#define _VECTORS_SIZE 6 ++ ++/* ++ The Register Bit names are represented by their bit number (0-7). ++ */ ++ ++/* General Interrupt MaSK register */ ++#define INT0 6 ++#define INTF0 6 ++ ++/* General Interrupt Flag Register */ ++#define TOIE0 1 ++#define TOV0 1 ++ ++/* MCU general Control Register */ ++#define SE 5 ++#define SM 4 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* Timer/Counter 0 Control Register */ ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* Watchdog Timer Control Register */ ++#define WDTOE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* ++ PB2 = SCK/T0 ++ PB1 = MISO/INT0 ++ PB0 = MOSI ++ */ ++ ++/* Data Register, Port B */ ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* Data Direction Register, Port B */ ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* Input Pins, Port B */ ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* EEPROM Control Register */ ++#define EERIE 3 ++#define EEMWE 2 ++#define EEWE 1 ++#define EERE 0 ++ ++/* Constants */ ++#define RAMSTART 0x60 ++#define RAMEND 0xDF ++#define XRAMEND RAMEND ++#define E2END 0x7F ++#define E2PAGESIZE 0 ++#define FLASHEND 0x07FF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Fuse Byte */ ++#define FUSE_CKSEL (unsigned char)~_BV(0) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DEFAULT (FUSE_SPIEN) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x91 ++#define SIGNATURE_2 0x06 ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_OVERFLOW0 ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++#endif /* _AVR_IOTN22_H_ */ +diff --git a/include/avr/iotn2313.h b/include/avr/iotn2313.h +index 6d7aa50..0504c9c 100644 +--- a/include/avr/iotn2313.h ++++ b/include/avr/iotn2313.h +@@ -1,698 +1,698 @@ +-/* Copyright (c) 2004, 2005, 2006 Bob Paddock +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn2313.h 2236 2011-03-17 21:53:39Z arcanum $ */ +- +-/* iotn2313.h derived from io2313.h by Bob Paddock. +- +- The changes between the AT90S2313 and the ATtiny2313 are extensive. +- +- Atmel has renamed several registers, and bits. See Atmel application note +- AVR091, as well as the errata at the end of the current ATtiny2313 data +- sheet. Some of the names have changed more than once during the sampling +- period of the ATtiny2313. +- +- Where there is no conflict the new and old names are both supported. +- +- In the case of a new feature in a register, only the new name is used. +- This intentionally breaks old code, so that there are no silent bugs. The +- source code must be updated to the new name in this case. +- +- The hardware interrupt vector table has changed from that of the AT90S2313. +- +- ATtiny2313 programs in page mode rather than the byte mode of the +- AT90S2313. Beware of programming the ATtiny2313 as a AT90S2313 device, +- when programming the Flash. +- +- ATtiny2313 has Signature Bytes: 0x1E 0x91 0x0A. +- +- Changes and/or additions are noted by "ATtiny" in the comments below. */ +- +-/* avr/iotn2313.h - definitions for ATtiny2313 */ +- +-#ifndef _AVR_IOTN2313_H_ +-#define _AVR_IOTN2313_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn2313.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* +- * The Register Bit names are represented by their bit number (0-7). +- * Example: PORTB |= _BV(PORTB7); Set MSB of PORTB. +- */ +- +-/* 0x00 Reserved */ +- +-/* ATtiny Digital Input Disable Register DIDR */ +-#define DIDR _SFR_IO8(0x01) +- +-#define AIN1D 1 +-#define AIN0D 0 +- +-/* ATtiny USART Baud Rate Register High UBBRH[11:8] */ +-#define UBRRH _SFR_IO8(0x02) +- +-/* ATtiny USART Control and Status Register C UCSRC */ +-#define UCSRC _SFR_IO8(0x03) +- +-#define UMSEL 6 +-#define UPM1 5 +-#define UPM0 4 +-#define USBS 3 +-#define UCSZ1 2 +-#define UCSZ0 1 +-#define UCPOL 0 +- +-/* 0x04 -> 0x07 Reserved */ +- +-/* ATtiny Analog Comparator Control and Status Register ACSR */ +-#define ACSR _SFR_IO8(0x08) +- +-#define ACD 7 +-#define ACBG 6 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +- +-/* USART Baud Rate Register Low UBBRL[7:0] */ +-#define UBRRL _SFR_IO8(0x09) +- +-/* ATtiny USART Control Register UCSRB */ +-#define UCSRB _SFR_IO8(0x0A) +- +-#define RXCIE 7 +-#define TXCIE 6 +-#define UDRIE 5 +-#define RXEN 4 +-#define TXEN 3 +-#define UCSZ2 2 +-#define RXB8 1 +-#define TXB8 0 +- +-/* ATtiny USART Status Register UCSRA */ +-#define UCSRA _SFR_IO8(0x0B) +- +-#define RXC 7 +-#define TXC 6 +-#define UDRE 5 +-#define FE 4 +-#define DOR 3 +-#define UPE 2 +-#define U2X 1 +-#define MPCM 0 +- +-/* USART I/O Data Register UBR or RXB[7:0], TXB[7:0] */ +-#define UDR _SFR_IO8(0x0C) +-#define RXB _SFR_IO8(0x0C) +-#define TXB _SFR_IO8(0x0C) +- +-/* ATtiny USI Control Register USICR */ +-#define USICR _SFR_IO8(0x0D) +- +-#define USISIE 7 +-#define USIOIE 6 +-#define USIWM1 5 +-#define USIWM0 4 +-#define USICS1 3 +-#define USICS0 2 +-#define USICLK 1 +-#define USITC 0 +- +-/* ATtiny USI Status Register USISR */ +-#define USISR _SFR_IO8(0x0E) +- +-#define USISIF 7 +-#define USIOIF 6 +-#define USIPF 5 +-#define USIDC 4 +-#define USICNT3 3 +-#define USICNT2 2 +-#define USICNT1 1 +-#define USICNT0 0 +- +-/* ATtiny USI Data Register USIDR[7:0] */ +-#define USIDR _SFR_IO8(0x0F) +- +-/* Input Pins, Port D PIND[6:0] */ +-#define PIND _SFR_IO8(0x10) +- +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-/* Data Direction Register, Port D DDRD[6:0] */ +-#define DDRD _SFR_IO8(0x11) +- +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-/* Data Register, Port D PORTD[6:0] */ +-#define PORTD _SFR_IO8(0x12) +- +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* ATtiny General Purpose I/O Register Zero GPIOR0[7:0] */ +-#define GPIOR0 _SFR_IO8(0x13) +- +-/* ATtiny General Purpose I/O Register One GPIOR1[7:0] */ +-#define GPIOR1 _SFR_IO8(0x14) +- +-/* ATtiny General Purpose I/O Register Two One GPIOR2[7:0] */ +-#define GPIOR2 _SFR_IO8(0x15) +- +-/* Input Pins, Port B PORTB[7:0] */ +-#define PINB _SFR_IO8(0x16) +- +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* Data Direction Register, Port B PORTB[7:0] */ +-#define DDRB _SFR_IO8(0x17) +- +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-/* Data Register, Port B PORTB[7:0] */ +-#define PORTB _SFR_IO8(0x18) +- +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* Port A Input Pins Address PINA[2:0] */ +-#define PINA _SFR_IO8(0x19) +- +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-/* Port A Data Direction Register DDRA[2:0] */ +-#define DDRA _SFR_IO8(0x1A) +- +-#define DDRA2 2 +-#define DDRA1 1 +-#define DDRA0 0 +- +-/* Port A Data Register PORTA[2:0] */ +-#define PORTA _SFR_IO8(0x1B) +- +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-/* ATtiny EEPROM Control Register EECR */ +-#define EECR _SFR_IO8(0x1C) +-#define EEPM1 5 +-#define EEPM0 4 +-#define EERIE 3 +-#define EEMPE 2 +-#define EEPE 1 +-#define EERE 0 +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* The EEPROM Address Register EEAR[6:0] */ +-#define EEAR _SFR_IO8(0x1E) +-#define EEARL _SFR_IO8(0x1E) +-#define EEAR6 6 +-#define EEAR5 5 +-#define EEAR4 4 +-#define EEAR3 3 +-#define EEAR2 2 +-#define EEAR1 1 +-#define EEAR0 0 +- +-/* 0x1F Reserved */ +- +-/* ATtiny Pin Change Mask Register PCMSK PCINT[7:0] */ +-#define PCMSK _SFR_IO8(0x20) +- +-#define PCINT7 7 +-#define PCINT6 6 +-#define PCINT5 5 +-#define PCINT4 4 +-#define PCINT3 3 +-#define PCINT2 2 +-#define PCINT1 1 +-#define PCINT0 0 +- +-/* ATtiny Watchdog Timer Control Register WDTCSR */ +-#define WDTCSR _SFR_IO8(0x21) +- +-#define WDIF 7 +-#define WDIE 6 +-#define WDP3 5 +-#define WDCE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* ATtiny Timer/Counter1 Control Register C TCCR1C */ +-#define TCCR1C _SFR_IO8(0x22) +- +-#define FOC1A 7 +-#define FOC1B 6 +- +-/* General Timer/Counter Control Register GTCCR */ +-#define GTCCR _SFR_IO8(0x23) +- +-#define PSR10 0 +- +-/* T/C 1 Input Capture Register ICR1[15:0] */ +-#define ICR1 _SFR_IO16(0x24) +-#define ICR1L _SFR_IO8(0x24) +-#define ICR1H _SFR_IO8(0x25) +- +-/* ATtiny Clock Prescale Register */ +-#define CLKPR _SFR_IO8(0x26) +- +-#define CLKPCE 7 +-#define CLKPS3 3 +-#define CLKPS2 2 +-#define CLKPS1 1 +-#define CLKPS0 0 +- +-/* 0x27 Reserved */ +- +-/* ATtiny Output Compare Register 1 B OCR1B[15:0] */ +-#define OCR1B _SFR_IO16(0x28) +-#define OCR1BL _SFR_IO8(0x28) +-#define OCR1BH _SFR_IO8(0x29) +- +-/* Output Compare Register 1 OCR1A[15:0] */ +-#define OCR1 _SFR_IO16(0x2A) +-#define OCR1L _SFR_IO8(0x2A) +-#define OCR1H _SFR_IO8(0x2B) +-#define OCR1A _SFR_IO16(0x2A) +-#define OCR1AL _SFR_IO8(0x2A) +-#define OCR1AH _SFR_IO8(0x2B) +- +-/* Timer/Counter 1 TCNT1[15:0] */ +-#define TCNT1 _SFR_IO16(0x2C) +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1H _SFR_IO8(0x2D) +- +-/* ATtiny Timer/Counter 1 Control and Status Register TCCR1B */ +-#define TCCR1B _SFR_IO8(0x2E) +- +-#define ICNC1 7 +-#define ICES1 6 +-#define WGM13 4 +-#define WGM12 3 /* Was CTC1 in AT90S2313 */ +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-/* ATtiny Timer/Counter 1 Control Register TCCR1A */ +-#define TCCR1A _SFR_IO8(0x2F) +- +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define WGM11 1 /* Was PWM11 in AT90S2313 */ +-#define WGM10 0 /* Was PWM10 in AT90S2313 */ +- +-/* ATtiny Timer/Counter Control Register A TCCR0A */ +-#define TCCR0A _SFR_IO8(0x30) +- +-#define COM0A1 7 +-#define COM0A0 6 +-#define COM0B1 5 +-#define COM0B0 4 +-#define WGM01 1 +-#define WGM00 0 +- +-/* ATtiny Oscillator Calibration Register OSCCAL[6:0] */ +-#define OSCCAL _SFR_IO8(0x31) +- +-#define CAL6 6 +-#define CAL5 5 +-#define CAL4 4 +-#define CAL3 3 +-#define CAL2 2 +-#define CAL1 1 +-#define CAL0 0 +- +-/* Timer/Counter 0 TCNT0[7:0] */ +-#define TCNT0 _SFR_IO8(0x32) +- +-/* ATtiny Timer/Counter 0 Control Register TCCR0B */ +-#define TCCR0B _SFR_IO8(0x33) +- +-#define FOC0A 7 +-#define FOC0B 6 +-#define WGM02 3 +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* ATtiny MCU Status Register MCUSR */ +-#define MCUSR _SFR_IO8(0x34) +- +-#define WDRF 3 +-#define BORF 2 +-#define EXTRF 1 +-#define PORF 0 +- +-/* ATtiny MCU general Control Register MCUCR */ +-#define MCUCR _SFR_IO8(0x35) +- +-#define PUD 7 +-#define SM1 6 +-#define SE 5 +-#define SM0 4 /* Some preliminary ATtiny2313 data sheets incorrectly refer +- to this bit as SMD; was SM in AT90S2313. */ +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-/* ATtiny Output Compare Register A OCR0A[7:0] */ +-#define OCR0A _SFR_IO8(0x36) +- +-/* ATtiny Store Program Memory Control and Status Register SPMCSR */ +-#define SPMCSR _SFR_IO8(0x37) +- +-#define CTPB 4 +-#define RFLB 3 +-#define PGWRT 2 +-#define PGERS 1 +-#define SPMEN 0 /* The name is used in ATtiny2313.xml file. */ +-#define SELFPRGEN 0 /* The name is used in datasheet. */ +-#define SELFPRGE 0 /* The name is left for compatibility. */ +- +-/* ATtiny Timer/Counter Interrupt Flag register TIFR */ +-#define TIFR _SFR_IO8(0x38) +- +-#define TOV1 7 +-#define OCF1A 6 +-#define OCF1B 5 +-#define ICF1 3 +-#define OCF0B 2 +-#define TOV0 1 +-#define OCF0A 0 +- +-/* ATtiny Timer/Counter Interrupt MaSK register TIMSK */ +-#define TIMSK _SFR_IO8(0x39) +- +-#define TOIE1 7 +-#define OCIE1A 6 +-#define OCIE1B 5 +-#define ICIE1 3 +-#define OCIE0B 2 +-#define TOIE0 1 +-#define OCIE0A 0 +- +-/* ATtiny External Interrupt Flag Register EIFR, was GIFR */ +-#define EIFR _SFR_IO8(0x3A) +- +-#define INTF1 7 +-#define INTF0 6 +-#define PCIF 5 +- +-/* ATtiny General Interrupt MaSK register GIMSK */ +-#define GIMSK _SFR_IO8(0x3B) +- +-#define INT1 7 +-#define INT0 6 +-#define PCIE 5 +- +-/* ATtiny Output Compare Register B OCR0B[7:0] */ +-#define OCR0B _SFR_IO8(0x3C) +- +-/* Interrupt vectors: */ +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +-#define SIG_INT0 _VECTOR(1) +- +-/* External Interrupt Request 1 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +-#define SIG_INTERRUPT1 _VECTOR(2) +-#define SIG_INT1 _VECTOR(2) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 3 +-#define TIMER1_CAPT_vect _VECTOR(3) +-#define SIG_INPUT_CAPTURE1 _VECTOR(3) +-#define SIG_TIMER1_CAPT _VECTOR(3) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 4 +-#define TIMER1_COMPA_vect _VECTOR(4) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(4) +-#define SIG_TIMER1_COMPA _VECTOR(4) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 5 +-#define TIMER1_OVF_vect _VECTOR(5) +-#define SIG_OVERFLOW1 _VECTOR(5) +-#define SIG_TIMER1_OVF _VECTOR(5) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 6 +-#define TIMER0_OVF_vect _VECTOR(6) +-#define SIG_OVERFLOW0 _VECTOR(6) +-#define SIG_TIMER0_OVF _VECTOR(6) +- +-/* USART, Rx Complete */ +-#define USART_RX_vect_num 7 +-#define USART_RX_vect _VECTOR(7) +-#define SIG_USART0_RECV _VECTOR(7) +-#define SIG_USART0_RX _VECTOR(7) +- +-/* USART Data Register Empty */ +-#define USART_UDRE_vect_num 8 +-#define USART_UDRE_vect _VECTOR(8) +-#define SIG_USART0_DATA _VECTOR(8) +-#define SIG_USART0_UDRE _VECTOR(8) +- +-/* USART, Tx Complete */ +-#define USART_TX_vect_num 9 +-#define USART_TX_vect _VECTOR(9) +-#define SIG_USART0_TRANS _VECTOR(9) +-#define SIG_USART0_TX _VECTOR(9) +- +-/* Analog Comparator */ +-#define ANA_COMP_vect_num 10 +-#define ANA_COMP_vect _VECTOR(10) +-#define SIG_COMPARATOR _VECTOR(10) +-#define SIG_ANALOG_COMP _VECTOR(10) +- +-#define PCINT_vect_num 11 +-#define PCINT_vect _VECTOR(11) +-#define SIG_PIN_CHANGE _VECTOR(11) +-#define SIG_PCINT _VECTOR(11) +- +-#define TIMER1_COMPB_vect_num 12 +-#define TIMER1_COMPB_vect _VECTOR(12) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(12) +-#define SIG_TIMER1_COMPB _VECTOR(12) +- +-#define TIMER0_COMPA_vect_num 13 +-#define TIMER0_COMPA_vect _VECTOR(13) +-#define SIG_OUTPUT_COMPARE0A _VECTOR(13) +-#define SIG_TIMER0_COMPA _VECTOR(13) +- +-#define TIMER0_COMPB_vect_num 14 +-#define TIMER0_COMPB_vect _VECTOR(14) +-#define SIG_OUTPUT_COMPARE0B _VECTOR(14) +-#define SIG_TIMER0_COMPB _VECTOR(14) +- +-/* USI Start Condition */ +-#define USI_START_vect_num 15 +-#define USI_START_vect _VECTOR(15) +-#define SIG_USI_START _VECTOR(15) +- +-/* USI Overflow */ +-#define USI_OVERFLOW_vect_num 16 +-#define USI_OVERFLOW_vect _VECTOR(16) +-#define SIG_USI_OVERFLOW _VECTOR(16) +- +-#define EEPROM_READY_vect_num 17 +-#define EEPROM_READY_vect _VECTOR(17) +-#define SIG_EEPROM_READY _VECTOR(17) +-#define SIG_EE_READY _VECTOR(17) +- +-/* Watchdog Timer Overflow */ +-#define WDT_OVERFLOW_vect_num 18 +-#define WDT_OVERFLOW_vect _VECTOR(18) +-#define SIG_WATCHDOG_TIMEOUT _VECTOR(18) +-#define SIG_WDT_OVERFLOW _VECTOR(18) +- +-/* 38 = (18*2)+2: Number of vectors times two, plus the reset vector */ +-#define _VECTORS_SIZE 38 +- +-/* Constants */ +-#define SPM_PAGESIZE 32 +-#define RAMSTART (0x60) +-#define RAMEND 0xDF +-#define XRAMEND RAMEND +-#define E2END 0x7F +-#define E2PAGESIZE 4 +-#define FLASHEND 0x07FF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL1 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_EESAVE (unsigned char)~_BV(6) +-#define FUSE_DWEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_SELFPRGEN (unsigned char)~_BV(0) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x91 +-#define SIGNATURE_2 0x0A +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_INT0 +-#pragma GCC poison SIG_INTERRUPT1 +-#pragma GCC poison SIG_INT1 +-#pragma GCC poison SIG_INPUT_CAPTURE1 +-#pragma GCC poison SIG_TIMER1_CAPT +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_TIMER1_COMPA +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_TIMER1_OVF +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_TIMER0_OVF +-#pragma GCC poison SIG_USART0_RECV +-#pragma GCC poison SIG_USART0_RX +-#pragma GCC poison SIG_USART0_DATA +-#pragma GCC poison SIG_USART0_UDRE +-#pragma GCC poison SIG_USART0_TRANS +-#pragma GCC poison SIG_USART0_TX +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_ANALOG_COMP +-#pragma GCC poison SIG_PIN_CHANGE +-#pragma GCC poison SIG_PCINT +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_TIMER1_COMPB +-#pragma GCC poison SIG_OUTPUT_COMPARE0A +-#pragma GCC poison SIG_TIMER0_COMPA +-#pragma GCC poison SIG_OUTPUT_COMPARE0B +-#pragma GCC poison SIG_TIMER0_COMPB +-#pragma GCC poison SIG_USI_START +-#pragma GCC poison SIG_USI_OVERFLOW +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_EE_READY +-#pragma GCC poison SIG_WATCHDOG_TIMEOUT +-#pragma GCC poison SIG_WDT_OVERFLOW +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +-#endif /* _AVR_IOTN2313_H_ */ ++/* Copyright (c) 2004, 2005, 2006 Bob Paddock ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn2313.h 2236 2011-03-17 21:53:39Z arcanum $ */ ++ ++/* iotn2313.h derived from io2313.h by Bob Paddock. ++ ++ The changes between the AT90S2313 and the ATtiny2313 are extensive. ++ ++ Atmel has renamed several registers, and bits. See Atmel application note ++ AVR091, as well as the errata at the end of the current ATtiny2313 data ++ sheet. Some of the names have changed more than once during the sampling ++ period of the ATtiny2313. ++ ++ Where there is no conflict the new and old names are both supported. ++ ++ In the case of a new feature in a register, only the new name is used. ++ This intentionally breaks old code, so that there are no silent bugs. The ++ source code must be updated to the new name in this case. ++ ++ The hardware interrupt vector table has changed from that of the AT90S2313. ++ ++ ATtiny2313 programs in page mode rather than the byte mode of the ++ AT90S2313. Beware of programming the ATtiny2313 as a AT90S2313 device, ++ when programming the Flash. ++ ++ ATtiny2313 has Signature Bytes: 0x1E 0x91 0x0A. ++ ++ Changes and/or additions are noted by "ATtiny" in the comments below. */ ++ ++/* avr/iotn2313.h - definitions for ATtiny2313 */ ++ ++#ifndef _AVR_IOTN2313_H_ ++#define _AVR_IOTN2313_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn2313.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* ++ * The Register Bit names are represented by their bit number (0-7). ++ * Example: PORTB |= _BV(PORTB7); Set MSB of PORTB. ++ */ ++ ++/* 0x00 Reserved */ ++ ++/* ATtiny Digital Input Disable Register DIDR */ ++#define DIDR _SFR_IO8(0x01) ++ ++#define AIN1D 1 ++#define AIN0D 0 ++ ++/* ATtiny USART Baud Rate Register High UBBRH[11:8] */ ++#define UBRRH _SFR_IO8(0x02) ++ ++/* ATtiny USART Control and Status Register C UCSRC */ ++#define UCSRC _SFR_IO8(0x03) ++ ++#define UMSEL 6 ++#define UPM1 5 ++#define UPM0 4 ++#define USBS 3 ++#define UCSZ1 2 ++#define UCSZ0 1 ++#define UCPOL 0 ++ ++/* 0x04 -> 0x07 Reserved */ ++ ++/* ATtiny Analog Comparator Control and Status Register ACSR */ ++#define ACSR _SFR_IO8(0x08) ++ ++#define ACD 7 ++#define ACBG 6 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++/* USART Baud Rate Register Low UBBRL[7:0] */ ++#define UBRRL _SFR_IO8(0x09) ++ ++/* ATtiny USART Control Register UCSRB */ ++#define UCSRB _SFR_IO8(0x0A) ++ ++#define RXCIE 7 ++#define TXCIE 6 ++#define UDRIE 5 ++#define RXEN 4 ++#define TXEN 3 ++#define UCSZ2 2 ++#define RXB8 1 ++#define TXB8 0 ++ ++/* ATtiny USART Status Register UCSRA */ ++#define UCSRA _SFR_IO8(0x0B) ++ ++#define RXC 7 ++#define TXC 6 ++#define UDRE 5 ++#define FE 4 ++#define DOR 3 ++#define UPE 2 ++#define U2X 1 ++#define MPCM 0 ++ ++/* USART I/O Data Register UBR or RXB[7:0], TXB[7:0] */ ++#define UDR _SFR_IO8(0x0C) ++#define RXB _SFR_IO8(0x0C) ++#define TXB _SFR_IO8(0x0C) ++ ++/* ATtiny USI Control Register USICR */ ++#define USICR _SFR_IO8(0x0D) ++ ++#define USISIE 7 ++#define USIOIE 6 ++#define USIWM1 5 ++#define USIWM0 4 ++#define USICS1 3 ++#define USICS0 2 ++#define USICLK 1 ++#define USITC 0 ++ ++/* ATtiny USI Status Register USISR */ ++#define USISR _SFR_IO8(0x0E) ++ ++#define USISIF 7 ++#define USIOIF 6 ++#define USIPF 5 ++#define USIDC 4 ++#define USICNT3 3 ++#define USICNT2 2 ++#define USICNT1 1 ++#define USICNT0 0 ++ ++/* ATtiny USI Data Register USIDR[7:0] */ ++#define USIDR _SFR_IO8(0x0F) ++ ++/* Input Pins, Port D PIND[6:0] */ ++#define PIND _SFR_IO8(0x10) ++ ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++/* Data Direction Register, Port D DDRD[6:0] */ ++#define DDRD _SFR_IO8(0x11) ++ ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++/* Data Register, Port D PORTD[6:0] */ ++#define PORTD _SFR_IO8(0x12) ++ ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* ATtiny General Purpose I/O Register Zero GPIOR0[7:0] */ ++#define GPIOR0 _SFR_IO8(0x13) ++ ++/* ATtiny General Purpose I/O Register One GPIOR1[7:0] */ ++#define GPIOR1 _SFR_IO8(0x14) ++ ++/* ATtiny General Purpose I/O Register Two One GPIOR2[7:0] */ ++#define GPIOR2 _SFR_IO8(0x15) ++ ++/* Input Pins, Port B PORTB[7:0] */ ++#define PINB _SFR_IO8(0x16) ++ ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* Data Direction Register, Port B PORTB[7:0] */ ++#define DDRB _SFR_IO8(0x17) ++ ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++/* Data Register, Port B PORTB[7:0] */ ++#define PORTB _SFR_IO8(0x18) ++ ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* Port A Input Pins Address PINA[2:0] */ ++#define PINA _SFR_IO8(0x19) ++ ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++/* Port A Data Direction Register DDRA[2:0] */ ++#define DDRA _SFR_IO8(0x1A) ++ ++#define DDRA2 2 ++#define DDRA1 1 ++#define DDRA0 0 ++ ++/* Port A Data Register PORTA[2:0] */ ++#define PORTA _SFR_IO8(0x1B) ++ ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++/* ATtiny EEPROM Control Register EECR */ ++#define EECR _SFR_IO8(0x1C) ++#define EEPM1 5 ++#define EEPM0 4 ++#define EERIE 3 ++#define EEMPE 2 ++#define EEPE 1 ++#define EERE 0 ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* The EEPROM Address Register EEAR[6:0] */ ++#define EEAR _SFR_IO8(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++#define EEAR6 6 ++#define EEAR5 5 ++#define EEAR4 4 ++#define EEAR3 3 ++#define EEAR2 2 ++#define EEAR1 1 ++#define EEAR0 0 ++ ++/* 0x1F Reserved */ ++ ++/* ATtiny Pin Change Mask Register PCMSK PCINT[7:0] */ ++#define PCMSK _SFR_IO8(0x20) ++ ++#define PCINT7 7 ++#define PCINT6 6 ++#define PCINT5 5 ++#define PCINT4 4 ++#define PCINT3 3 ++#define PCINT2 2 ++#define PCINT1 1 ++#define PCINT0 0 ++ ++/* ATtiny Watchdog Timer Control Register WDTCSR */ ++#define WDTCSR _SFR_IO8(0x21) ++ ++#define WDIF 7 ++#define WDIE 6 ++#define WDP3 5 ++#define WDCE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* ATtiny Timer/Counter1 Control Register C TCCR1C */ ++#define TCCR1C _SFR_IO8(0x22) ++ ++#define FOC1A 7 ++#define FOC1B 6 ++ ++/* General Timer/Counter Control Register GTCCR */ ++#define GTCCR _SFR_IO8(0x23) ++ ++#define PSR10 0 ++ ++/* T/C 1 Input Capture Register ICR1[15:0] */ ++#define ICR1 _SFR_IO16(0x24) ++#define ICR1L _SFR_IO8(0x24) ++#define ICR1H _SFR_IO8(0x25) ++ ++/* ATtiny Clock Prescale Register */ ++#define CLKPR _SFR_IO8(0x26) ++ ++#define CLKPCE 7 ++#define CLKPS3 3 ++#define CLKPS2 2 ++#define CLKPS1 1 ++#define CLKPS0 0 ++ ++/* 0x27 Reserved */ ++ ++/* ATtiny Output Compare Register 1 B OCR1B[15:0] */ ++#define OCR1B _SFR_IO16(0x28) ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BH _SFR_IO8(0x29) ++ ++/* Output Compare Register 1 OCR1A[15:0] */ ++#define OCR1 _SFR_IO16(0x2A) ++#define OCR1L _SFR_IO8(0x2A) ++#define OCR1H _SFR_IO8(0x2B) ++#define OCR1A _SFR_IO16(0x2A) ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++ ++/* Timer/Counter 1 TCNT1[15:0] */ ++#define TCNT1 _SFR_IO16(0x2C) ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++ ++/* ATtiny Timer/Counter 1 Control and Status Register TCCR1B */ ++#define TCCR1B _SFR_IO8(0x2E) ++ ++#define ICNC1 7 ++#define ICES1 6 ++#define WGM13 4 ++#define WGM12 3 /* Was CTC1 in AT90S2313 */ ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++/* ATtiny Timer/Counter 1 Control Register TCCR1A */ ++#define TCCR1A _SFR_IO8(0x2F) ++ ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define WGM11 1 /* Was PWM11 in AT90S2313 */ ++#define WGM10 0 /* Was PWM10 in AT90S2313 */ ++ ++/* ATtiny Timer/Counter Control Register A TCCR0A */ ++#define TCCR0A _SFR_IO8(0x30) ++ ++#define COM0A1 7 ++#define COM0A0 6 ++#define COM0B1 5 ++#define COM0B0 4 ++#define WGM01 1 ++#define WGM00 0 ++ ++/* ATtiny Oscillator Calibration Register OSCCAL[6:0] */ ++#define OSCCAL _SFR_IO8(0x31) ++ ++#define CAL6 6 ++#define CAL5 5 ++#define CAL4 4 ++#define CAL3 3 ++#define CAL2 2 ++#define CAL1 1 ++#define CAL0 0 ++ ++/* Timer/Counter 0 TCNT0[7:0] */ ++#define TCNT0 _SFR_IO8(0x32) ++ ++/* ATtiny Timer/Counter 0 Control Register TCCR0B */ ++#define TCCR0B _SFR_IO8(0x33) ++ ++#define FOC0A 7 ++#define FOC0B 6 ++#define WGM02 3 ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* ATtiny MCU Status Register MCUSR */ ++#define MCUSR _SFR_IO8(0x34) ++ ++#define WDRF 3 ++#define BORF 2 ++#define EXTRF 1 ++#define PORF 0 ++ ++/* ATtiny MCU general Control Register MCUCR */ ++#define MCUCR _SFR_IO8(0x35) ++ ++#define PUD 7 ++#define SM1 6 ++#define SE 5 ++#define SM0 4 /* Some preliminary ATtiny2313 data sheets incorrectly refer ++ to this bit as SMD; was SM in AT90S2313. */ ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* ATtiny Output Compare Register A OCR0A[7:0] */ ++#define OCR0A _SFR_IO8(0x36) ++ ++/* ATtiny Store Program Memory Control and Status Register SPMCSR */ ++#define SPMCSR _SFR_IO8(0x37) ++ ++#define CTPB 4 ++#define RFLB 3 ++#define PGWRT 2 ++#define PGERS 1 ++#define SPMEN 0 /* The name is used in ATtiny2313.xml file. */ ++#define SELFPRGEN 0 /* The name is used in datasheet. */ ++#define SELFPRGE 0 /* The name is left for compatibility. */ ++ ++/* ATtiny Timer/Counter Interrupt Flag register TIFR */ ++#define TIFR _SFR_IO8(0x38) ++ ++#define TOV1 7 ++#define OCF1A 6 ++#define OCF1B 5 ++#define ICF1 3 ++#define OCF0B 2 ++#define TOV0 1 ++#define OCF0A 0 ++ ++/* ATtiny Timer/Counter Interrupt MaSK register TIMSK */ ++#define TIMSK _SFR_IO8(0x39) ++ ++#define TOIE1 7 ++#define OCIE1A 6 ++#define OCIE1B 5 ++#define ICIE1 3 ++#define OCIE0B 2 ++#define TOIE0 1 ++#define OCIE0A 0 ++ ++/* ATtiny External Interrupt Flag Register EIFR, was GIFR */ ++#define EIFR _SFR_IO8(0x3A) ++ ++#define INTF1 7 ++#define INTF0 6 ++#define PCIF 5 ++ ++/* ATtiny General Interrupt MaSK register GIMSK */ ++#define GIMSK _SFR_IO8(0x3B) ++ ++#define INT1 7 ++#define INT0 6 ++#define PCIE 5 ++ ++/* ATtiny Output Compare Register B OCR0B[7:0] */ ++#define OCR0B _SFR_IO8(0x3C) ++ ++/* Interrupt vectors: */ ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++#define SIG_INT0 _VECTOR(1) ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++#define SIG_INTERRUPT1 _VECTOR(2) ++#define SIG_INT1 _VECTOR(2) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 3 ++#define TIMER1_CAPT_vect _VECTOR(3) ++#define SIG_INPUT_CAPTURE1 _VECTOR(3) ++#define SIG_TIMER1_CAPT _VECTOR(3) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 4 ++#define TIMER1_COMPA_vect _VECTOR(4) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(4) ++#define SIG_TIMER1_COMPA _VECTOR(4) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 5 ++#define TIMER1_OVF_vect _VECTOR(5) ++#define SIG_OVERFLOW1 _VECTOR(5) ++#define SIG_TIMER1_OVF _VECTOR(5) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 6 ++#define TIMER0_OVF_vect _VECTOR(6) ++#define SIG_OVERFLOW0 _VECTOR(6) ++#define SIG_TIMER0_OVF _VECTOR(6) ++ ++/* USART, Rx Complete */ ++#define USART_RX_vect_num 7 ++#define USART_RX_vect _VECTOR(7) ++#define SIG_USART0_RECV _VECTOR(7) ++#define SIG_USART0_RX _VECTOR(7) ++ ++/* USART Data Register Empty */ ++#define USART_UDRE_vect_num 8 ++#define USART_UDRE_vect _VECTOR(8) ++#define SIG_USART0_DATA _VECTOR(8) ++#define SIG_USART0_UDRE _VECTOR(8) ++ ++/* USART, Tx Complete */ ++#define USART_TX_vect_num 9 ++#define USART_TX_vect _VECTOR(9) ++#define SIG_USART0_TRANS _VECTOR(9) ++#define SIG_USART0_TX _VECTOR(9) ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect_num 10 ++#define ANA_COMP_vect _VECTOR(10) ++#define SIG_COMPARATOR _VECTOR(10) ++#define SIG_ANALOG_COMP _VECTOR(10) ++ ++#define PCINT_vect_num 11 ++#define PCINT_vect _VECTOR(11) ++#define SIG_PIN_CHANGE _VECTOR(11) ++#define SIG_PCINT _VECTOR(11) ++ ++#define TIMER1_COMPB_vect_num 12 ++#define TIMER1_COMPB_vect _VECTOR(12) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(12) ++#define SIG_TIMER1_COMPB _VECTOR(12) ++ ++#define TIMER0_COMPA_vect_num 13 ++#define TIMER0_COMPA_vect _VECTOR(13) ++#define SIG_OUTPUT_COMPARE0A _VECTOR(13) ++#define SIG_TIMER0_COMPA _VECTOR(13) ++ ++#define TIMER0_COMPB_vect_num 14 ++#define TIMER0_COMPB_vect _VECTOR(14) ++#define SIG_OUTPUT_COMPARE0B _VECTOR(14) ++#define SIG_TIMER0_COMPB _VECTOR(14) ++ ++/* USI Start Condition */ ++#define USI_START_vect_num 15 ++#define USI_START_vect _VECTOR(15) ++#define SIG_USI_START _VECTOR(15) ++ ++/* USI Overflow */ ++#define USI_OVERFLOW_vect_num 16 ++#define USI_OVERFLOW_vect _VECTOR(16) ++#define SIG_USI_OVERFLOW _VECTOR(16) ++ ++#define EEPROM_READY_vect_num 17 ++#define EEPROM_READY_vect _VECTOR(17) ++#define SIG_EEPROM_READY _VECTOR(17) ++#define SIG_EE_READY _VECTOR(17) ++ ++/* Watchdog Timer Overflow */ ++#define WDT_OVERFLOW_vect_num 18 ++#define WDT_OVERFLOW_vect _VECTOR(18) ++#define SIG_WATCHDOG_TIMEOUT _VECTOR(18) ++#define SIG_WDT_OVERFLOW _VECTOR(18) ++ ++/* 38 = (18*2)+2: Number of vectors times two, plus the reset vector */ ++#define _VECTORS_SIZE 38 ++ ++/* Constants */ ++#define SPM_PAGESIZE 32 ++#define RAMSTART (0x60) ++#define RAMEND 0xDF ++#define XRAMEND RAMEND ++#define E2END 0x7F ++#define E2PAGESIZE 4 ++#define FLASHEND 0x07FF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL1 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_EESAVE (unsigned char)~_BV(6) ++#define FUSE_DWEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x91 ++#define SIGNATURE_2 0x0A ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_INT0 ++#pragma GCC poison SIG_INTERRUPT1 ++#pragma GCC poison SIG_INT1 ++#pragma GCC poison SIG_INPUT_CAPTURE1 ++#pragma GCC poison SIG_TIMER1_CAPT ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_TIMER1_COMPA ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_TIMER1_OVF ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_TIMER0_OVF ++#pragma GCC poison SIG_USART0_RECV ++#pragma GCC poison SIG_USART0_RX ++#pragma GCC poison SIG_USART0_DATA ++#pragma GCC poison SIG_USART0_UDRE ++#pragma GCC poison SIG_USART0_TRANS ++#pragma GCC poison SIG_USART0_TX ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_ANALOG_COMP ++#pragma GCC poison SIG_PIN_CHANGE ++#pragma GCC poison SIG_PCINT ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_TIMER1_COMPB ++#pragma GCC poison SIG_OUTPUT_COMPARE0A ++#pragma GCC poison SIG_TIMER0_COMPA ++#pragma GCC poison SIG_OUTPUT_COMPARE0B ++#pragma GCC poison SIG_TIMER0_COMPB ++#pragma GCC poison SIG_USI_START ++#pragma GCC poison SIG_USI_OVERFLOW ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_EE_READY ++#pragma GCC poison SIG_WATCHDOG_TIMEOUT ++#pragma GCC poison SIG_WDT_OVERFLOW ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++#endif /* _AVR_IOTN2313_H_ */ +diff --git a/include/avr/iotn2313a.h b/include/avr/iotn2313a.h +index 6c6db60..26b98d6 100644 +--- a/include/avr/iotn2313a.h ++++ b/include/avr/iotn2313a.h +@@ -1,769 +1,802 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn2313a.h 2035 2009-11-02 02:44:17Z arcanum $ */ +- +-/* avr/iotn2313a.h - definitions for ATtiny2313A */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn2313a.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATtiny2313A_H_ +-#define _AVR_ATtiny2313A_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define DIDR _SFR_IO8(0x001) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define UBRRH _SFR_IO8(0x002) +-#define UBRR8 0 +-#define UBRR9 1 +-#define UBRR10 2 +-#define UBRR11 3 +- +-#define UCSRC _SFR_IO8(0x003) +-#define UCPOL 0 +-#define UCSZ0 1 +-#define UCSZ1 2 +-#define USBS 3 +-#define UPM0 4 +-#define UPM1 5 -#define UMSEL 6 -+#define UMSEL0 6 -+#define UMSEL1 7 -+ -+/* When in MSPIM mode*/ -+#define UCPHA 1 -+#define UDORD 2 - - #define PCMSK1 _SFR_IO8(0x004) - #define PCINT8 0 -@@ -509,6 +514,7 @@ - #define PGWRT 2 - #define RFLB 3 - #define CTPB 4 -+#define RSIG 5 - - #define TIFR _SFR_IO8(0x038) - #define OCF0A 0 -@@ -528,13 +534,17 @@ - #define OCIE1A 6 - #define TOIE1 7 - +- +-#define PCMSK1 _SFR_IO8(0x004) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +- +-#define PCMSK2 _SFR_IO8(0x005) +-#define PCINT11 0 +-#define PCINT12 1 +-#define PCINT13 2 +-#define PCINT14 3 +-#define PCINT15 4 +-#define PCINT16 5 +-#define PCINT17 6 +- +-#define PRR _SFR_IO8(0x006) +-#define PRUSART 0 +-#define PRUSI 1 +-#define PRTIM0 2 +-#define PRTIM1 3 +- +-#define BODCR _SFR_IO8(0x007) +-#define BPDSE 0 +-#define BPDS 1 +- +-#define ACSR _SFR_IO8(0x008) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define UBRRL _SFR_IO8(0x009) +-#define UBRR0 0 +-#define UBRR1 1 +-#define UBRR2 2 +-#define UBRR3 3 +-#define UBRR4 4 +-#define UBRR5 5 +-#define UBRR6 6 +-#define UBRR7 7 +- +-#define UCSRB _SFR_IO8(0x00A) +-#define TXB8 0 +-#define RXB8 1 +-#define UCSZ2 2 +-#define TXEN 3 +-#define RXEN 4 +-#define UDRIE 5 +-#define TXCIE 6 +-#define RXCIE 7 +- +-#define UCSRA _SFR_IO8(0x00B) +-#define MPCM 0 +-#define U2X 1 +-#define UPE 2 +-#define DOR 3 +-#define FE 4 +-#define UDRE 5 +-#define TXC 6 +-#define RXC 7 +- +-#define UDR _SFR_IO8(0x00C) +-#define UDR0 0 +-#define UDR1 1 +-#define UDR2 2 +-#define UDR3 3 +-#define UDR4 4 +-#define UDR5 5 +-#define UDR6 6 +-#define UDR7 7 +- +-#define USICR _SFR_IO8(0x00D) +-#define USITC 0 +-#define USICLK 1 +-#define USICS0 2 +-#define USICS1 3 +-#define USIWM0 4 +-#define USIWM1 5 +-#define USIOIE 6 +-#define USISIE 7 +- +-#define USISR _SFR_IO8(0x00E) +-#define USICNT0 0 +-#define USICNT1 1 +-#define USICNT2 2 +-#define USICNT3 3 +-#define USIDC 4 +-#define USIPF 5 +-#define USIOIF 6 +-#define USISIF 7 +- +-#define USIDR _SFR_IO8(0x00F) +-#define USIDR0 0 +-#define USIDR1 1 +-#define USIDR2 2 +-#define USIDR3 3 +-#define USIDR4 4 +-#define USIDR5 5 +-#define USIDR6 6 +-#define USIDR7 7 +- +-#define PIND _SFR_IO8(0x010) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +- +-#define DDRD _SFR_IO8(0x011) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +- +-#define PORTD _SFR_IO8(0x012) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +- +-#define GPIOR0 _SFR_IO8(0x013) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define GPIOR1 _SFR_IO8(0x014) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x015) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define PINB _SFR_IO8(0x016) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x017) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x018) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINA _SFR_IO8(0x019) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +- +-#define DDRA _SFR_IO8(0x01A) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +- +-#define PORTA _SFR_IO8(0x01B) +-#define PORTA0 0 +-#define PORTA1 1 +-#define PORTA2 2 +- +-#define EECR _SFR_IO8(0x01C) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x01D) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO8(0x01E) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +- +-#define PCMSK _SFR_IO8(0x020) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define WDTCR _SFR_IO8(0x021) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define TCCR1C _SFR_IO8(0x022) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define GTCCR _SFR_IO8(0x023) +-#define PSR10 0 +- +-#define ICR1 _SFR_IO16(0x024) +- +-#define ICR1L _SFR_IO8(0x024) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_IO8(0x025) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define CLKPR _SFR_IO8(0x026) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define OCR1B _SFR_IO16(0x028) +- +-#define OCR1BL _SFR_IO8(0x028) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_IO8(0x029) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define OCR1A _SFR_IO16(0x02A) +- +-#define OCR1AL _SFR_IO8(0x02A) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_IO8(0x02B) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define TCNT1 _SFR_IO16(0x02C) +- +-#define TCNT1L _SFR_IO8(0x02C) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_IO8(0x02D) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define TCCR1B _SFR_IO8(0x02E) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1A _SFR_IO8(0x02F) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR0A _SFR_IO8(0x030) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define OSCCAL _SFR_IO8(0x031) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +- +-#define TCNT0 _SFR_IO8(0x032) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define TCCR0B _SFR_IO8(0x033) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define MCUSR _SFR_IO8(0x034) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x035) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define SM0 4 +-#define SE 5 +-#define SM1 6 +-#define PUD 7 +- +-#define OCR0A _SFR_IO8(0x036) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define SPMCSR _SFR_IO8(0x037) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define RFLB 3 +-#define CTPB 4 +- +-#define TIFR _SFR_IO8(0x038) +-#define OCF0A 0 +-#define TOV0 1 +-#define OCF0B 2 +-#define ICF1 3 +-#define OCF1B 5 +-#define OCF1A 6 +-#define TOV1 7 +- +-#define TIMSK _SFR_IO8(0x039) +-#define OCIE0A 0 +-#define TOIE0 1 +-#define OCIE0B 2 +-#define ICIE1 3 +-#define OCIE1B 5 +-#define OCIE1A 6 +-#define TOIE1 7 +- -#define EIFR _SFR_IO8(0x03A) -#define PCIF 5 -+#define GIFR _SFR_IO8(0x03A) -+#define PCIF0 5 -+#define PCIF2 4 -+#define PCIF1 3 - #define INTF0 6 - #define INTF1 7 - - #define GIMSK _SFR_IO8(0x03B) +-#define INTF0 6 +-#define INTF1 7 +- +-#define GIMSK _SFR_IO8(0x03B) -#define PCIE 5 -+#define PCIE1 3 -+#define PCIE2 4 -+#define PCIE0 5 - #define INT0 6 - #define INT1 7 - -@@ -563,16 +573,16 @@ - #define TIMER1_OVF_vect _VECTOR(5) /* Timer/Counter1 Overflow */ - #define TIMER0_OVF_vect_num 6 - #define TIMER0_OVF_vect _VECTOR(6) /* Timer/Counter0 Overflow */ +-#define INT0 6 +-#define INT1 7 +- +-#define OCR0B _SFR_IO8(0x03C) +-#define OCR0_0 0 +-#define OCR0_1 1 +-#define OCR0_2 2 +-#define OCR0_3 3 +-#define OCR0_4 4 +-#define OCR0_5 5 +-#define OCR0_6 6 +-#define OCR0_7 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ +-#define TIMER1_CAPT_vect_num 3 +-#define TIMER1_CAPT_vect _VECTOR(3) /* Timer/Counter1 Capture Event */ +-#define TIMER1_COMPA_vect_num 4 +-#define TIMER1_COMPA_vect _VECTOR(4) /* Timer/Counter1 Compare Match A */ +-#define TIMER1_OVF_vect_num 5 +-#define TIMER1_OVF_vect _VECTOR(5) /* Timer/Counter1 Overflow */ +-#define TIMER0_OVF_vect_num 6 +-#define TIMER0_OVF_vect _VECTOR(6) /* Timer/Counter0 Overflow */ -#define USART_RX_vect_num 7 -#define USART_RX_vect _VECTOR(7) /* USART, Rx Complete */ -#define USART_UDRE_vect_num 8 -#define USART_UDRE_vect _VECTOR(8) /* USART Data Register Empty */ -#define USART_TX_vect_num 9 -#define USART_TX_vect _VECTOR(9) /* USART, Tx Complete */ -+#define USART0_RX_vect_num 7 -+#define USART0_RX_vect _VECTOR(7) /* USART, Rx Complete */ -+#define USART0_UDRE_vect_num 8 -+#define USART0_UDRE_vect _VECTOR(8) /* USART Data Register Empty */ -+#define USART0_TX_vect_num 9 -+#define USART0_TX_vect _VECTOR(9) /* USART, Tx Complete */ - #define ANA_COMP_vect_num 10 - #define ANA_COMP_vect _VECTOR(10) /* Analog Comparator */ +-#define ANA_COMP_vect_num 10 +-#define ANA_COMP_vect _VECTOR(10) /* Analog Comparator */ -#define PCINT_B_vect_num 11 -#define PCINT_B_vect _VECTOR(11) /* Pin Change Interrupt Request B */ -+#define PCINT0_vect_num 11 -+#define PCINT0_vect _VECTOR(11) /* Pin Change Interrupt Request 0 */ - #define TIMER1_COMPB_vect_num 12 - #define TIMER1_COMPB_vect _VECTOR(12) /* */ - #define TIMER0_COMPA_vect_num 13 -@@ -583,14 +593,14 @@ - #define USI_START_vect _VECTOR(15) /* USI Start Condition */ - #define USI_OVERFLOW_vect_num 16 - #define USI_OVERFLOW_vect _VECTOR(16) /* USI Overflow */ -+#define EEPROM_Ready_vect_num 17 -+#define EEPROM_Ready_vect _VECTOR(17) /* EEPROM Ready */ - #define WDT_OVERFLOW_vect_num 18 - #define WDT_OVERFLOW_vect _VECTOR(18) /* Watchdog Timer Overflow */ +-#define TIMER1_COMPB_vect_num 12 +-#define TIMER1_COMPB_vect _VECTOR(12) /* */ +-#define TIMER0_COMPA_vect_num 13 +-#define TIMER0_COMPA_vect _VECTOR(13) /* */ +-#define TIMER0_COMPB_vect_num 14 +-#define TIMER0_COMPB_vect _VECTOR(14) /* */ +-#define USI_START_vect_num 15 +-#define USI_START_vect _VECTOR(15) /* USI Start Condition */ +-#define USI_OVERFLOW_vect_num 16 +-#define USI_OVERFLOW_vect _VECTOR(16) /* USI Overflow */ +-#define WDT_OVERFLOW_vect_num 18 +-#define WDT_OVERFLOW_vect _VECTOR(18) /* Watchdog Timer Overflow */ -#define PCINT_D_vect_num 20 -#define PCINT_D_vect _VECTOR(20) /* Pin Change Interrupt Request D */ -#define EEPROM_Ready_vect_num 17 -#define EEPROM_Ready_vect _VECTOR(17) /* */ -#define PCINT_A_vect_num 19 -#define PCINT_A_vect _VECTOR(19) /* Pin Change Interrupt Request A */ -+#define PCINT1_vect_num 19 -+#define PCINT1_vect _VECTOR(19) /* Pin Change Interrupt Request 1 */ -+#define PCINT2_vect_num 20 -+#define PCINT2_vect _VECTOR(20) /* Pin Change Interrupt Request 2 */ - - #define _VECTOR_SIZE 2 /* Size of individual vector. */ - #define _VECTORS_SIZE (21 * _VECTOR_SIZE) -@@ -624,14 +634,14 @@ - #define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) - - /* High Fuse Byte */ +- +-#define _VECTOR_SIZE 2 /* Size of individual vector. */ +-#define _VECTORS_SIZE (21 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (32) +-#define RAMSTART (0x60) +-#define RAMSIZE (128) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x7F) +-#define E2PAGESIZE (4) +-#define FLASHEND (0x7FF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) +- +-/* High Fuse Byte */ -#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ -#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ -#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(0) /* External reset disable */ -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) /* Brown-out Detector trigger level */ - #define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ - #define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ -#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ -#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ -+#define FUSE_EESAVE (unsigned char)~_BV(6) /* EEPROM memory is preserved through chip erase */ -+#define FUSE_DWEN (unsigned char)~_BV(7) /* debugWIRE Enable */ - #define HFUSE_DEFAULT (FUSE_SPIEN) - - /* Extended Fuse Byte */ -diff --git a/include/avr/iotn441.h b/include/avr/iotn441.h -new file mode 100644 -index 0000000..d987fce ---- /dev/null -+++ b/include/avr/iotn441.h -@@ -0,0 +1,843 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATTINY441_H_INCLUDED -+#define _AVR_ATTINY441_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iotn441.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define ADCSRB _SFR_IO8(0x04) -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+#define ADLAR 3 -+ -+#define ADCSRA _SFR_IO8(0x05) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_IO16(0x06) -+#endif -+#define ADCW _SFR_IO16(0x06) -+ -+#define ADCL _SFR_IO8(0x06) -+#define ADCH _SFR_IO8(0x07) -+ -+#define ADMUXB _SFR_IO8(0x08) -+#define GSEL0 0 -+#define GSEL1 1 -+#define REFS0 5 -+#define REFS1 6 -+#define REFS2 7 -+ -+#define ADMUXA _SFR_IO8(0x09) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define MUX4 4 -+#define MUX5 5 -+ -+#define ACSR0A _SFR_IO8(0x0A) -+#define ACIS00 0 -+#define ACIS01 1 -+#define ACIC0 2 -+#define ACIE0 3 -+#define ACI0 4 -+#define ACO0 5 -+#define ACPMUX2 6 -+#define ACD0 7 -+ -+#define ACSR0B _SFR_IO8(0x0B) -+#define ACPMUX0 0 -+#define ACPMUX1 1 -+#define ACNMUX0 2 -+#define ACNMUX1 3 -+#define ACOE0 4 -+#define HLEV0 6 -+#define HSEL0 7 -+ -+#define ACSR1A _SFR_IO8(0x0C) -+#define ACIS10 0 -+#define ACIS11 1 -+#define ACIC1 2 -+#define ACIE1 3 -+#define ACI1 4 -+#define ACO1 5 -+#define ACBG1 6 -+#define ACD1 7 -+ -+#define ACSR1B _SFR_IO8(0x0D) -+#define ACME1 2 -+#define ACOE1 4 -+#define HLEV1 6 -+#define HSEL1 7 -+ -+#define TIFR1 _SFR_IO8(0x0E) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define ICF1 5 -+ -+#define TIMSK1 _SFR_IO8(0x0F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define ICIE1 5 -+ -+#define TIFR2 _SFR_IO8(0x10) -+#define TOV2 0 -+#define OCF2A 1 -+#define OCF2B 2 -+#define ICF2 5 -+ -+#define TIMSK2 _SFR_IO8(0x11) -+#define TOIE2 0 -+#define OCIE2A 1 -+#define OCIE2B 2 -+#define ICIE2 5 -+ -+#define PCMSK0 _SFR_IO8(0x12) -+ -+#define GPIOR0 _SFR_IO8(0x13) -+ -+#define GPIOR1 _SFR_IO8(0x14) -+ -+#define GPIOR2 _SFR_IO8(0x15) -+ -+#define PINB _SFR_IO8(0x16) -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x17) -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x18) -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINA _SFR_IO8(0x19) -+#define PINA7 7 -+#define PINA6 6 -+#define PINA5 5 -+#define PINA4 4 -+#define PINA3 3 -+#define PINA2 2 -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x1A) -+#define DDRA7 7 -+#define DDRA6 6 -+#define DDRA5 5 -+#define DDRA4 4 -+#define DDRA3 3 -+#define DDRA2 2 -+#define DDRA1 1 -+#define DDRA0 0 -+ -+#define PORTA _SFR_IO8(0x1B) -+#define PORTA7 7 -+#define PORTA6 6 -+#define PORTA5 5 -+#define PORTA4 4 -+#define PORTA3 3 -+#define PORTA2 2 -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define EECR _SFR_IO8(0x1C) -+#define EERE 0 -+#define EEPE 1 -+#define EEMPE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+ -+#define EEDR _SFR_IO8(0x1D) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x1E) -+ -+#define EEARL _SFR_IO8(0x1E) -+#define EEARH _SFR_IO8(0x1F) -+ -+#define PCMSK1 _SFR_IO8(0x20) -+ -+#define WDTCSR _SFR_IO8(0x21) -+#define WDE 3 -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDP3 5 -+#define WDIE 6 -+#define WDIF 7 -+ -+#define TCCR1C _SFR_IO8(0x22) -+#define FOC1B 6 -+#define FOC1A 7 -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSR 0 -+#define TSM 7 -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_IO16(0x24) -+ -+#define ICR1L _SFR_IO8(0x24) -+#define ICR1H _SFR_IO8(0x25) -+ -+/* Reserved [0x26..0x27] */ -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_IO16(0x28) -+ -+#define OCR1BL _SFR_IO8(0x28) -+#define OCR1BH _SFR_IO8(0x29) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_IO16(0x2A) -+ -+#define OCR1AL _SFR_IO8(0x2A) -+#define OCR1AH _SFR_IO8(0x2B) -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_IO16(0x2C) -+ -+#define TCNT1L _SFR_IO8(0x2C) -+#define TCNT1H _SFR_IO8(0x2D) -+ -+#define TCCR1B _SFR_IO8(0x2E) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1A _SFR_IO8(0x2F) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR0A _SFR_IO8(0x30) -+#define WGM00 0 -+#define WGM01 1 -+#define COM0B0 4 -+#define COM0B1 5 -+#define COM0A0 6 -+#define COM0A1 7 -+ -+/* Reserved [0x31] */ -+ -+#define TCNT0 _SFR_IO8(0x32) -+ -+#define TCCR0B _SFR_IO8(0x33) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define WGM02 3 -+#define FOC0B 6 -+#define FOC0A 7 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define ISC00 0 -+#define ISC01 1 -+#define SM0 3 -+#define SM1 4 -+#define SE 5 -+ -+#define OCR0A _SFR_IO8(0x36) -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define RFLB 3 -+#define CTPB 4 -+#define RSIG 5 -+ -+#define TIFR0 _SFR_IO8(0x38) -+#define TOV0 0 -+#define OCF0A 1 -+#define OCF0B 2 -+ -+#define TIMSK0 _SFR_IO8(0x39) -+#define TOIE0 0 -+#define OCIE0A 1 -+#define OCIE0B 2 -+ -+#define GIFR _SFR_IO8(0x3A) -+#define PCIF0 4 -+#define PCIF1 5 -+#define INTF0 6 -+ -+#define GIMSK _SFR_IO8(0x3B) -+#define PCIE0 4 -+#define PCIE1 5 -+#define INT0 6 -+ -+#define OCR0B _SFR_IO8(0x3C) -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define DIDR0 _SFR_MEM8(0x60) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+#define ADC6D 6 -+#define ADC7D 7 -+ -+#define DIDR1 _SFR_MEM8(0x61) -+#define ADC11D 0 -+#define ADC10D 1 -+#define ADC8D 2 -+#define ADC9D 3 -+ -+#define PUEB _SFR_MEM8(0x62) -+ -+#define PUEA _SFR_MEM8(0x63) -+ -+#define PORTCR _SFR_MEM8(0x64) -+#define BBMB 1 -+#define BBMA 0 -+ -+#define REMAP _SFR_MEM8(0x65) -+#define U0MAP 0 -+#define SPIMAP 1 -+ -+#define TOCPMCOE _SFR_MEM8(0x66) -+#define TOCC0OE 0 -+#define TOCC1OE 1 -+#define TOCC2OE 2 -+#define TOCC3OE 3 -+#define TOCC4OE 4 -+#define TOCC5OE 5 -+#define TOCC6OE 6 -+#define TOCC7OE 7 -+ -+#define TOCPMSA0 _SFR_MEM8(0x67) -+#define TOCC0S0 0 -+#define TOCC0S1 1 -+#define TOCC1S0 2 -+#define TOCC1S1 3 -+#define TOCC2S0 4 -+#define TOCC2S1 5 -+#define TOCC3S0 6 -+#define TOCC3S1 7 -+ -+#define TOCPMSA1 _SFR_MEM8(0x68) -+#define TOCC4S0 0 -+#define TOCC4S1 1 -+#define TOCC5S0 2 -+#define TOCC5S1 3 -+#define TOCC6S0 4 -+#define TOCC6S1 5 -+#define TOCC7S0 6 -+#define TOCC7S1 7 -+ -+/* Reserved [0x69] */ -+ -+#define PHDE _SFR_MEM8(0x6A) -+#define PHDEA0 0 -+#define PHDEA1 1 -+ -+/* Reserved [0x6B..0x6F] */ -+ -+#define PRR _SFR_MEM8(0x70) -+#define PRADC 0 -+#define PRTIM0 1 -+#define PRTIM1 2 -+#define PRTIM2 3 -+#define PRSPI 4 -+#define PRUSART0 5 -+#define PRUSART1 6 -+#define PRTWI 7 -+ -+#define CCP _SFR_MEM8(0x71) -+ -+#define CLKCR _SFR_MEM8(0x72) -+#define CKSEL0 0 -+#define CKSEL1 1 -+#define CKSEL2 2 -+#define CKSEL3 3 -+#define SUT 4 -+#define CKOUTC 5 -+#define CSTR 6 -+#define OSCRDY 7 -+ -+#define CLKPR _SFR_MEM8(0x73) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+ -+#define OSCCAL0 _SFR_MEM8(0x74) -+ -+#define OSCTCAL0A _SFR_MEM8(0x75) -+ -+#define OSCTCAL0B _SFR_MEM8(0x76) -+ -+#define OSCCAL1 _SFR_MEM8(0x77) -+ -+/* Reserved [0x78..0x7F] */ -+ -+#define UDR0 _SFR_MEM8(0x80) -+ -+/* Combine UBRR0L and UBRR0H */ -+#define UBRR0 _SFR_MEM16(0x81) -+ -+#define UBRR0L _SFR_MEM8(0x81) -+#define UBRR0H _SFR_MEM8(0x82) -+ -+#define UCSR0D _SFR_MEM8(0x83) -+#define SFDE0 5 -+#define RXS0 6 -+#define RXSIE0 7 -+ -+#define UCSR0C _SFR_MEM8(0x84) -+#define UCPOL0 0 -+#define UCSZ00 1 -+#define UCSZ01 2 -+#define USBS0 3 -+#define UPM00 4 -+#define UPM01 5 -+#define UMSEL00 6 -+#define UMSEL01 7 -+ -+#define UCSR0B _SFR_MEM8(0x85) -+#define TXB80 0 -+#define RXB80 1 -+#define UCSZ02 2 -+#define TXEN0 3 -+#define RXEN0 4 -+#define UDRIE0 5 -+#define TXCIE0 6 -+#define RXCIE0 7 -+ -+#define UCSR0A _SFR_MEM8(0x86) -+#define MPCM0 0 -+#define U2X0 1 -+#define UPE0 2 -+#define DOR0 3 -+#define FE0 4 -+#define UDRE0 5 -+#define TXC0 6 -+#define RXC0 7 -+ -+/* Reserved [0x87..0x8F] */ -+ -+#define UDR1 _SFR_MEM8(0x90) -+ -+/* Combine UBRR1L and UBRR1H */ -+#define UBRR1 _SFR_MEM16(0x91) -+ -+#define UBRR1L _SFR_MEM8(0x91) -+#define UBRR1H _SFR_MEM8(0x92) -+ -+#define UCSR1D _SFR_MEM8(0x93) -+#define SFDE1 5 -+#define RXS1 6 -+#define RXSIE1 7 -+ -+#define UCSR1C _SFR_MEM8(0x94) -+#define UCPOL1 0 -+#define UCSZ10 1 -+#define UCSZ11 2 -+#define USBS1 3 -+#define UPM10 4 -+#define UPM11 5 -+#define UMSEL10 6 -+#define UMSEL11 7 -+ -+#define UCSR1B _SFR_MEM8(0x95) -+#define TXB81 0 -+#define RXB81 1 -+#define UCSZ12 2 -+#define TXEN1 3 -+#define RXEN1 4 -+#define UDRIE1 5 -+#define TXCIE1 6 -+#define RXCIE1 7 -+ -+#define UCSR1A _SFR_MEM8(0x96) -+#define MPCM1 0 -+#define U2X1 1 -+#define UPE1 2 -+#define DOR1 3 -+#define FE1 4 -+#define UDRE1 5 -+#define TXC1 6 -+#define RXC1 7 -+ -+/* Reserved [0x97..0x9F] */ -+ -+#define TWSD _SFR_MEM8(0xA0) -+#define TWSD0 0 -+#define TWSD1 1 -+#define TWSD2 2 -+#define TWSD3 3 -+#define TWSD4 4 -+#define TWSD5 5 -+#define TWSD6 6 -+#define TWSD7 7 -+ -+#define TWSAM _SFR_MEM8(0xA1) -+#define TWAE 0 -+#define TWSAM1 1 -+#define TWSAM2 2 -+#define TWSAM3 3 -+#define TWSAM4 4 -+#define TWSAM5 5 -+#define TWSAM6 6 -+#define TWSAM7 7 -+ -+#define TWSA _SFR_MEM8(0xA2) -+ -+#define TWSSRA _SFR_MEM8(0xA3) -+#define TWAS 0 -+#define TWDIR 1 -+#define TWBE 2 -+#define TWC 3 -+#define TWRA 4 -+#define TWCH 5 -+#define TWASIF 6 -+#define TWDIF 7 -+ -+#define TWSCRB _SFR_MEM8(0xA4) -+#define TWCMD0 0 -+#define TWCMD1 1 -+#define TWAA 2 -+#define TWHNM 3 -+ -+#define TWSCRA _SFR_MEM8(0xA5) -+#define TWSME 0 -+#define TWPME 1 -+#define TWSIE 2 -+#define TWEN 3 -+#define TWASIE 4 -+#define TWDIE 5 -+#define TWSHE 7 -+ -+/* Reserved [0xA6..0xAF] */ -+ -+#define SPDR _SFR_MEM8(0xB0) -+ -+#define SPSR _SFR_MEM8(0xB1) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPCR _SFR_MEM8(0xB2) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+/* Reserved [0xB3..0xBF] */ -+ -+/* Combine ICR2L and ICR2H */ -+#define ICR2 _SFR_MEM16(0xC0) -+ -+#define ICR2L _SFR_MEM8(0xC0) -+#define ICR2H _SFR_MEM8(0xC1) -+ -+/* Combine OCR2BL and OCR2BH */ -+#define OCR2B _SFR_MEM16(0xC2) -+ -+#define OCR2BL _SFR_MEM8(0xC2) -+#define OCR2BH _SFR_MEM8(0xC3) -+ -+/* Combine OCR2AL and OCR2AH */ -+#define OCR2A _SFR_MEM16(0xC4) -+ -+#define OCR2AL _SFR_MEM8(0xC4) -+#define OCR2AH _SFR_MEM8(0xC5) -+ -+/* Combine TCNT2L and TCNT2H */ -+#define TCNT2 _SFR_MEM16(0xC6) -+ -+#define TCNT2L _SFR_MEM8(0xC6) -+#define TCNT2H _SFR_MEM8(0xC7) -+ -+#define TCCR2C _SFR_MEM8(0xC8) -+#define FOC2B 6 -+#define FOC2A 7 -+ -+#define TCCR2B _SFR_MEM8(0xC9) -+#define CS20 0 -+#define CS21 1 -+#define CS22 2 -+#define WGM22 3 -+#define WGM23 4 -+#define ICES2 6 -+#define ICNC2 7 -+ -+#define TCCR2A _SFR_MEM8(0xCA) -+#define WGM20 0 -+#define WGM21 1 -+#define COM2B0 4 -+#define COM2B1 5 -+#define COM2A0 6 -+#define COM2A1 7 -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(2) -+#define PCINT0_vect_num 2 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(3) -+#define PCINT1_vect_num 3 -+ -+/* Watchdog Time-out Interrupt */ -+#define WDT_vect _VECTOR(4) -+#define WDT_vect_num 4 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(5) -+#define TIMER1_CAPT_vect_num 5 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(6) -+#define TIMER1_COMPA_vect_num 6 -+ -+/* Timer/Counter1 Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(7) -+#define TIMER1_COMPB_vect_num 7 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(8) -+#define TIMER1_OVF_vect_num 8 -+ -+/* TimerCounter0 Compare Match A */ -+#define TIMER0_COMPA_vect _VECTOR(9) -+#define TIMER0_COMPA_vect_num 9 -+ -+/* TimerCounter0 Compare Match B */ -+#define TIMER0_COMPB_vect _VECTOR(10) -+#define TIMER0_COMPB_vect_num 10 -+ -+/* Timer/Couner0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(11) -+#define TIMER0_OVF_vect_num 11 -+ -+/* Analog Comparator 0 */ -+#define ANA_COMP0_vect _VECTOR(12) -+#define ANA_COMP0_vect_num 12 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(13) -+#define ADC_vect_num 13 -+ -+/* EEPROM Ready */ -+#define EE_RDY_vect _VECTOR(14) -+#define EE_RDY_vect_num 14 -+ -+/* Analog Comparator 1 */ -+#define ANA_COMP1_vect _VECTOR(15) -+#define ANA_COMP1_vect_num 15 -+ -+/* Timer/Counter2 Capture Event */ -+#define TIMER2_CAPT_vect _VECTOR(16) -+#define TIMER2_CAPT_vect_num 16 -+ -+/* Timer/Counter2 Compare Match A */ -+#define TIMER2_COMPA_vect _VECTOR(17) -+#define TIMER2_COMPA_vect_num 17 -+ -+/* Timer/Counter2 Compare Match B */ -+#define TIMER2_COMPB_vect _VECTOR(18) -+#define TIMER2_COMPB_vect_num 18 -+ -+/* Timer/Counter2 Overflow */ -+#define TIMER2_OVF_vect _VECTOR(19) -+#define TIMER2_OVF_vect_num 19 -+ -+/* Serial Peripheral Interface */ -+#define SPI_vect _VECTOR(20) -+#define SPI_vect_num 20 -+ -+/* USART0, Start */ -+#define USART0_START_vect _VECTOR(21) -+#define USART0_START_vect_num 21 -+ -+/* USART0, Rx Complete */ -+#define USART0_RX_vect _VECTOR(22) -+#define USART0_RX_vect_num 22 -+ -+/* USART0 Data Register Empty */ -+#define USART0_UDRE_vect _VECTOR(23) -+#define USART0_UDRE_vect_num 23 -+ -+/* USART0, Tx Complete */ -+#define USART0_TX_vect _VECTOR(24) -+#define USART0_TX_vect_num 24 -+ -+/* USART1, Start */ -+#define USART1_START_vect _VECTOR(25) -+#define USART1_START_vect_num 25 -+ -+/* USART1, Rx Complete */ -+#define USART1_RX_vect _VECTOR(26) -+#define USART1_RX_vect_num 26 -+ -+/* USART1 Data Register Empty */ -+#define USART1_UDRE_vect _VECTOR(27) -+#define USART1_UDRE_vect_num 27 -+ -+/* USART1, Tx Complete */ -+#define USART1_TX_vect _VECTOR(28) -+#define USART1_TX_vect_num 28 -+ -+/* Two-wire Serial Interface */ -+#define TWI_SLAVE_vect _VECTOR(29) -+#define TWI_SLAVE_vect_num 29 -+ -+#define _VECTORS_SIZE 60 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 16 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x0FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 256 -+#define RAMEND 0x01FF -+#define E2START 0 -+#define E2SIZE 256 -+#define E2PAGESIZE 4 -+#define E2END 0x00FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_DWEN (unsigned char)~_BV(6) -+#define FUSE_RSTDISBL (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_SELFPRGEN (unsigned char)~_BV(0) -+#define FUSE_BODACT0 (unsigned char)~_BV(1) -+#define FUSE_BODACT1 (unsigned char)~_BV(2) -+#define FUSE_BODPD0 (unsigned char)~_BV(3) -+#define FUSE_BODPD1 (unsigned char)~_BV(4) -+#define FUSE_ULPOSCSEL0 (unsigned char)~_BV(5) -+#define FUSE_ULPOSCSEL1 (unsigned char)~_BV(6) -+#define FUSE_ULPOSCSEL2 (unsigned char)~_BV(7) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x92 -+#define SIGNATURE_2 0x15 -+ -+ -+#endif /* #ifdef _AVR_ATTINY441_H_INCLUDED */ -+ -diff --git a/include/avr/iotn44a.h b/include/avr/iotn44a.h -index cca6515..ee027e0 100644 ---- a/include/avr/iotn44a.h -+++ b/include/avr/iotn44a.h -@@ -486,10 +486,12 @@ - #define MCUCR _SFR_IO8(0x35) - #define ISC00 0 - #define ISC01 1 -+#define BODSE 2 - #define SM0 3 - #define SM1 4 - #define SE 5 - #define PUD 6 -+#define BODS 7 - - #define OCR0A _SFR_IO8(0x36) - #define OCR0A_0 0 -diff --git a/include/avr/iotn48.h b/include/avr/iotn48.h -index 616cbf4..463ee99 100644 ---- a/include/avr/iotn48.h -+++ b/include/avr/iotn48.h -@@ -742,7 +742,7 @@ - - - /* Constants */ +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self Programming Enable */ +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x91 +-#define SIGNATURE_2 0x0A +- +- +-/* Device Pin Definitions */ +-#define RXD_DDR DDRD +-#define RXD_PORT PORTD +-#define RXD_PIN PIND +-#define RXD_BIT 0 +- +-#define TXD_DDR DDRD +-#define TXD_PORT PORTD +-#define TXD_PIN PIND +-#define TXD_BIT 1 +- +-#define PA1_DDR DDRXTAL +-#define PA1_PORT PORTXTAL +-#define PA1_PIN PINXTAL +-#define PA1_BIT XTAL2 +- +-#define PA0_DDR DDRXTAL +-#define PA0_PORT PORTXTAL +-#define PA0_PIN PINXTAL +-#define PA0_BIT XTAL1 +- +-#define INT0_DDR DDRD +-#define INT0_PORT PORTD +-#define INT0_PIN PIND +-#define INT0_BIT 2 +- +-#define XCK_DDR DDRD +-#define XCK_PORT PORTD +-#define XCK_PIN PIND +-#define XCK_BIT 2 +- +-#define CKOUT_DDR DDRD +-#define CKOUT_PORT PORTD +-#define CKOUT_PIN PIND +-#define CKOUT_BIT 2 +- +-#define INT1_DDR DDRD +-#define INT1_PORT PORTD +-#define INT1_PIN PIND +-#define INT1_BIT 3 +- +-#define T0_DDR DDRD +-#define T0_PORT PORTD +-#define T0_PIN PIND +-#define T0_BIT 4 +- +-#define T1_DDR DDRD +-#define T1_PORT PORTD +-#define T1_PIN PIND +-#define T1_BIT 5 +- +-#define OC0B_DDR DDRD +-#define OC0B_PORT PORTD +-#define OC0B_PIN PIND +-#define OC0B_BIT 5 +- +-#define ICP_DDR DDRD +-#define ICP_PORT PORTD +-#define ICP_PIN PIND +-#define ICP_BIT 6 +- +-#define AIN0_DDR DDRB +-#define AIN0_PORT PORTB +-#define AIN0_PIN PINB +-#define AIN0_BIT 0 +- +-#define AIN1_DDR DDRB +-#define AIN1_PORT PORTB +-#define AIN1_PIN PINB +-#define AIN1_BIT 1 +- +-#define OC0A_DDR DDRB +-#define OC0A_PORT PORTB +-#define OC0A_PIN PINB +-#define OC0A_BIT 2 +- +-#define OC1A_DDR DDRB +-#define OC1A_PORT PORTB +-#define OC1A_PIN PINB +-#define OC1A_BIT 3 +- +-#define OC1B_DDR DDRB +-#define OC1B_PORT PORTB +-#define OC1B_PIN PINB +-#define OC1B_BIT 4 +- +-#define MOSI_DDR DDRB +-#define MOSI_PORT PORTB +-#define MOSI_PIN PINB +-#define MOSI_BIT 5 +- +-#define DI_DDR DDRB +-#define DI_PORT PORTB +-#define DI_PIN PINB +-#define DI_BIT 5 +- +-#define MISO_DDR DDRB +-#define MISO_PORT PORTB +-#define MISO_PIN PINB +-#define MISO_BIT 6 +- +-#define DO_DDR DDRB +-#define DO_PORT PORTB +-#define DO_PIN PINB +-#define DO_BIT 6 +- +-#define SCK_DDR DDRB +-#define SCK_PORT PORTB +-#define SCK_PIN PINB +-#define SCK_BIT 7 +- +-#define SCL_DDR DDRB +-#define SCL_PORT PORTB +-#define SCL_PIN PINB +-#define SCL_BIT 7 +- +-#endif /* _AVR_ATtiny2313A_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn2313a.h 2412 2014-03-20 11:21:20Z pitchumani $ */ ++ ++/* avr/iotn2313a.h - definitions for ATtiny2313A */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn2313a.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATtiny2313A_H_ ++#define _AVR_ATtiny2313A_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define USIBR _SFR_IO8(0x000) ++#define USIBR0 0 ++#define USIBR1 1 ++#define USIBR2 2 ++#define USIBR3 3 ++#define USIBR4 4 ++#define USIBR5 5 ++#define USIBR6 6 ++#define USIBR7 7 ++ ++#define DIDR _SFR_IO8(0x001) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define UBRRH _SFR_IO8(0x002) ++#define UBRR8 0 ++#define UBRR9 1 ++#define UBRR10 2 ++#define UBRR11 3 ++ ++#define UCSRC _SFR_IO8(0x003) ++#define UCPOL 0 ++#define UCSZ0 1 ++#define UCSZ1 2 ++#define USBS 3 ++#define UPM0 4 ++#define UPM1 5 ++#define UMSEL0 6 ++#define UMSEL1 7 ++ ++/* When in MSPIM mode */ ++#define UCPHA 1 ++#define UDORD 2 ++ ++#define PCMSK1 _SFR_IO8(0x004) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++ ++#define PCMSK2 _SFR_IO8(0x005) ++#define PCINT11 0 ++#define PCINT12 1 ++#define PCINT13 2 ++#define PCINT14 3 ++#define PCINT15 4 ++#define PCINT16 5 ++#define PCINT17 6 ++ ++#define PRR _SFR_IO8(0x006) ++#define PRUSART 0 ++#define PRUSI 1 ++#define PRTIM0 2 ++#define PRTIM1 3 ++ ++#define BODCR _SFR_IO8(0x007) ++#define BPDSE 0 ++#define BPDS 1 ++ ++#define ACSR _SFR_IO8(0x008) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define UBRRL _SFR_IO8(0x009) ++#define UBRR0 0 ++#define UBRR1 1 ++#define UBRR2 2 ++#define UBRR3 3 ++#define UBRR4 4 ++#define UBRR5 5 ++#define UBRR6 6 ++#define UBRR7 7 ++ ++#define UCSRB _SFR_IO8(0x00A) ++#define TXB8 0 ++#define RXB8 1 ++#define UCSZ2 2 ++#define TXEN 3 ++#define RXEN 4 ++#define UDRIE 5 ++#define TXCIE 6 ++#define RXCIE 7 ++ ++#define UCSRA _SFR_IO8(0x00B) ++#define MPCM 0 ++#define U2X 1 ++#define UPE 2 ++#define DOR 3 ++#define FE 4 ++#define UDRE 5 ++#define TXC 6 ++#define RXC 7 ++ ++#define UDR _SFR_IO8(0x00C) ++#define UDR0 0 ++#define UDR1 1 ++#define UDR2 2 ++#define UDR3 3 ++#define UDR4 4 ++#define UDR5 5 ++#define UDR6 6 ++#define UDR7 7 ++ ++#define USICR _SFR_IO8(0x00D) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_IO8(0x00E) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_IO8(0x00F) ++#define USIDR0 0 ++#define USIDR1 1 ++#define USIDR2 2 ++#define USIDR3 3 ++#define USIDR4 4 ++#define USIDR5 5 ++#define USIDR6 6 ++#define USIDR7 7 ++ ++#define PIND _SFR_IO8(0x010) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++ ++#define DDRD _SFR_IO8(0x011) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++ ++#define PORTD _SFR_IO8(0x012) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++ ++#define GPIOR0 _SFR_IO8(0x013) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define GPIOR1 _SFR_IO8(0x014) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x015) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define PINB _SFR_IO8(0x016) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x017) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x018) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINA _SFR_IO8(0x019) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++ ++#define DDRA _SFR_IO8(0x01A) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++ ++#define PORTA _SFR_IO8(0x01B) ++#define PORTA0 0 ++#define PORTA1 1 ++#define PORTA2 2 ++ ++#define EECR _SFR_IO8(0x01C) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x01D) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO8(0x01E) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++ ++#define PCMSK _SFR_IO8(0x020) ++#define PCMSK0 _SFR_IO8(0x020) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define WDTCR _SFR_IO8(0x021) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define TCCR1C _SFR_IO8(0x022) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define GTCCR _SFR_IO8(0x023) ++#define PSR10 0 ++ ++#define ICR1 _SFR_IO16(0x024) ++ ++#define ICR1L _SFR_IO8(0x024) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_IO8(0x025) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define CLKPR _SFR_IO8(0x026) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define OCR1B _SFR_IO16(0x028) ++ ++#define OCR1BL _SFR_IO8(0x028) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_IO8(0x029) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define OCR1A _SFR_IO16(0x02A) ++ ++#define OCR1AL _SFR_IO8(0x02A) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_IO8(0x02B) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define TCNT1 _SFR_IO16(0x02C) ++ ++#define TCNT1L _SFR_IO8(0x02C) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_IO8(0x02D) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define TCCR1B _SFR_IO8(0x02E) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1A _SFR_IO8(0x02F) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR0A _SFR_IO8(0x030) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define OSCCAL _SFR_IO8(0x031) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++ ++#define TCNT0 _SFR_IO8(0x032) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define TCCR0B _SFR_IO8(0x033) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define MCUSR _SFR_IO8(0x034) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x035) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define SM0 4 ++#define SE 5 ++#define SM1 6 ++#define PUD 7 ++ ++#define OCR0A _SFR_IO8(0x036) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define SPMCSR _SFR_IO8(0x037) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define RFLB 3 ++#define CTPB 4 ++ ++#define TIFR _SFR_IO8(0x038) ++#define OCF0A 0 ++#define TOV0 1 ++#define OCF0B 2 ++#define ICF1 3 ++#define OCF1B 5 ++#define OCF1A 6 ++#define TOV1 7 ++ ++#define TIMSK _SFR_IO8(0x039) ++#define OCIE0A 0 ++#define TOIE0 1 ++#define OCIE0B 2 ++#define ICIE1 3 ++#define OCIE1B 5 ++#define OCIE1A 6 ++#define TOIE1 7 ++ ++#define EIFR _SFR_IO8(0x03A) ++#define GIFR _SFR_IO8(0x03A) ++#define PCIF1 3 ++#define PCIF2 4 ++#define PCIF0 5 ++#define INTF0 6 ++#define INTF1 7 ++ ++#define GIMSK _SFR_IO8(0x03B) ++#define PCIE1 3 ++#define PCIE2 4 ++#define PCIE0 5 ++#define INT0 6 ++#define INT1 7 ++ ++#define OCR0B _SFR_IO8(0x03C) ++#define OCR0_0 0 ++#define OCR0_1 1 ++#define OCR0_2 2 ++#define OCR0_3 3 ++#define OCR0_4 4 ++#define OCR0_5 5 ++#define OCR0_6 6 ++#define OCR0_7 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ ++#define TIMER1_CAPT_vect_num 3 ++#define TIMER1_CAPT_vect _VECTOR(3) /* Timer/Counter1 Capture Event */ ++#define TIMER1_COMPA_vect_num 4 ++#define TIMER1_COMPA_vect _VECTOR(4) /* Timer/Counter1 Compare Match A */ ++#define TIMER1_OVF_vect_num 5 ++#define TIMER1_OVF_vect _VECTOR(5) /* Timer/Counter1 Overflow */ ++#define TIMER0_OVF_vect_num 6 ++#define TIMER0_OVF_vect _VECTOR(6) /* Timer/Counter0 Overflow */ ++#define USART0_RX_vect_num 7 ++#define USART0_RX_vect _VECTOR(7) /* USART, Rx Complete */ ++#define USART_RX_vect_num 7 ++#define USART_RX_vect _VECTOR(7) /* alias */ ++#define USART0_UDRE_vect_num 8 ++#define USART0_UDRE_vect _VECTOR(8) /* USART Data Register Empty */ ++#define USART_UDRE_vect_num 8 ++#define USART_UDRE_vect _VECTOR(8) /* alias */ ++#define USART0_TX_vect_num 9 ++#define USART0_TX_vect _VECTOR(9) /* USART, Tx Complete */ ++#define USART_TX_vect_num 9 ++#define USART_TX_vect _VECTOR(9) /* alias */ ++#define ANA_COMP_vect_num 10 ++#define ANA_COMP_vect _VECTOR(10) /* Analog Comparator */ ++#define PCINT0_vect_num 11 ++#define PCINT0_vect _VECTOR(11) /* Pin Change Interrupt Request 0 */ ++#define PCINT_B_vect_num 11 ++#define PCINT_B_vect _VECTOR(11) /* alias */ ++#define TIMER1_COMPB_vect_num 12 ++#define TIMER1_COMPB_vect _VECTOR(12) /* */ ++#define TIMER0_COMPA_vect_num 13 ++#define TIMER0_COMPA_vect _VECTOR(13) /* */ ++#define TIMER0_COMPB_vect_num 14 ++#define TIMER0_COMPB_vect _VECTOR(14) /* */ ++#define USI_START_vect_num 15 ++#define USI_START_vect _VECTOR(15) /* USI Start Condition */ ++#define USI_OVERFLOW_vect_num 16 ++#define USI_OVERFLOW_vect _VECTOR(16) /* USI Overflow */ ++#define EEPROM_Ready_vect_num 17 ++#define EEPROM_Ready_vect _VECTOR(17) /* EEPROM Ready */ ++#define WDT_OVERFLOW_vect_num 18 ++#define WDT_OVERFLOW_vect _VECTOR(18) /* Watchdog Timer Overflow */ ++#define PCINT1_vect_num 19 ++#define PCINT1_vect _VECTOR(19) /* Pin Change Interrupt Request 1 */ ++#define PCINT_A_vect_num 19 ++#define PCINT_A_vect _VECTOR(19) /* alias */ ++#define PCINT2_vect_num 20 ++#define PCINT2_vect _VECTOR(20) /* Pin Change Interrupt Request 2 */ ++#define PCINT_D_vect_num 20 ++#define PCINT_D_vect _VECTOR(20) /* alias */ ++ ++#define _VECTOR_SIZE 2 /* Size of individual vector. */ ++#define _VECTORS_SIZE (21 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (32) ++#define RAMSTART (0x60) ++#define RAMSIZE (128) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x7F) ++#define E2PAGESIZE (4) ++#define FLASHEND (0x7FF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) ++ ++/* High Fuse Byte */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(0) /* External reset disable */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) /* Brown-out Detector trigger level */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_EESAVE (unsigned char)~_BV(6) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_DWEN (unsigned char)~_BV(7) /* debugWIRE Enable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self Programming Enable */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x91 ++#define SIGNATURE_2 0x0A ++ ++ ++/* Device Pin Definitions */ ++#define RXD_DDR DDRD ++#define RXD_PORT PORTD ++#define RXD_PIN PIND ++#define RXD_BIT 0 ++ ++#define TXD_DDR DDRD ++#define TXD_PORT PORTD ++#define TXD_PIN PIND ++#define TXD_BIT 1 ++ ++#define PA1_DDR DDRXTAL ++#define PA1_PORT PORTXTAL ++#define PA1_PIN PINXTAL ++#define PA1_BIT XTAL2 ++ ++#define PA0_DDR DDRXTAL ++#define PA0_PORT PORTXTAL ++#define PA0_PIN PINXTAL ++#define PA0_BIT XTAL1 ++ ++#define INT0_DDR DDRD ++#define INT0_PORT PORTD ++#define INT0_PIN PIND ++#define INT0_BIT 2 ++ ++#define XCK_DDR DDRD ++#define XCK_PORT PORTD ++#define XCK_PIN PIND ++#define XCK_BIT 2 ++ ++#define CKOUT_DDR DDRD ++#define CKOUT_PORT PORTD ++#define CKOUT_PIN PIND ++#define CKOUT_BIT 2 ++ ++#define INT1_DDR DDRD ++#define INT1_PORT PORTD ++#define INT1_PIN PIND ++#define INT1_BIT 3 ++ ++#define T0_DDR DDRD ++#define T0_PORT PORTD ++#define T0_PIN PIND ++#define T0_BIT 4 ++ ++#define T1_DDR DDRD ++#define T1_PORT PORTD ++#define T1_PIN PIND ++#define T1_BIT 5 ++ ++#define OC0B_DDR DDRD ++#define OC0B_PORT PORTD ++#define OC0B_PIN PIND ++#define OC0B_BIT 5 ++ ++#define ICP_DDR DDRD ++#define ICP_PORT PORTD ++#define ICP_PIN PIND ++#define ICP_BIT 6 ++ ++#define AIN0_DDR DDRB ++#define AIN0_PORT PORTB ++#define AIN0_PIN PINB ++#define AIN0_BIT 0 ++ ++#define AIN1_DDR DDRB ++#define AIN1_PORT PORTB ++#define AIN1_PIN PINB ++#define AIN1_BIT 1 ++ ++#define OC0A_DDR DDRB ++#define OC0A_PORT PORTB ++#define OC0A_PIN PINB ++#define OC0A_BIT 2 ++ ++#define OC1A_DDR DDRB ++#define OC1A_PORT PORTB ++#define OC1A_PIN PINB ++#define OC1A_BIT 3 ++ ++#define OC1B_DDR DDRB ++#define OC1B_PORT PORTB ++#define OC1B_PIN PINB ++#define OC1B_BIT 4 ++ ++#define MOSI_DDR DDRB ++#define MOSI_PORT PORTB ++#define MOSI_PIN PINB ++#define MOSI_BIT 5 ++ ++#define DI_DDR DDRB ++#define DI_PORT PORTB ++#define DI_PIN PINB ++#define DI_BIT 5 ++ ++#define MISO_DDR DDRB ++#define MISO_PORT PORTB ++#define MISO_PIN PINB ++#define MISO_BIT 6 ++ ++#define DO_DDR DDRB ++#define DO_PORT PORTB ++#define DO_PIN PINB ++#define DO_BIT 6 ++ ++#define SCK_DDR DDRB ++#define SCK_PORT PORTB ++#define SCK_PIN PINB ++#define SCK_BIT 7 ++ ++#define SCL_DDR DDRB ++#define SCL_PORT PORTB ++#define SCL_PIN PINB ++#define SCL_BIT 7 ++ ++#endif /* _AVR_ATtiny2313A_H_ */ ++ +diff --git a/include/avr/iotn24.h b/include/avr/iotn24.h +index e877e7b..2c7052a 100644 +--- a/include/avr/iotn24.h ++++ b/include/avr/iotn24.h +@@ -1,90 +1,90 @@ +-/* Copyright (c) 2005, Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn24.h 2115 2010-04-05 23:19:53Z arcanum $ */ +- +-/* avr/iotn24.h - definitions for ATtiny24 */ +- +-#ifndef _AVR_IOTN24_H_ +-#define _AVR_IOTN24_H_ 1 +- +-#include +- -#define SPM_PAGESIZE 32 -+#define SPM_PAGESIZE 64 - #define RAMSTART (0x100) - #define RAMEND 0x1FF - #define XRAMSIZE 0 -diff --git a/include/avr/iotn828.h b/include/avr/iotn828.h -new file mode 100644 -index 0000000..337c6f7 ---- /dev/null -+++ b/include/avr/iotn828.h -@@ -0,0 +1,832 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATTINY828_H_INCLUDED -+#define _AVR_ATTINY828_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iotn828.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define PINA _SFR_IO8(0x00) -+#define PINA7 7 -+#define PINA6 6 -+#define PINA5 5 -+#define PINA4 4 -+#define PINA3 3 -+#define PINA2 2 -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x01) -+#define DDRA7 7 -+#define DDRA6 6 -+#define DDRA5 5 -+#define DDRA4 4 -+#define DDRA3 3 -+#define DDRA2 2 -+#define DDRA1 1 -+#define DDRA0 0 -+ -+#define PORTA _SFR_IO8(0x02) -+#define PORTA7 7 -+#define PORTA6 6 -+#define PORTA5 5 -+#define PORTA4 4 -+#define PORTA3 3 -+#define PORTA2 2 -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define PUEA _SFR_IO8(0x03) -+ -+#define PINB _SFR_IO8(0x04) -+#define PINB7 7 -+#define PINB6 6 -+#define PINB5 5 -+#define PINB4 4 -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x05) -+#define DDRB7 7 -+#define DDRB6 6 -+#define DDRB5 5 -+#define DDRB4 4 -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x06) -+#define PORTB7 7 -+#define PORTB6 6 -+#define PORTB5 5 -+#define PORTB4 4 -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PUEB _SFR_IO8(0x07) -+ -+#define PINC _SFR_IO8(0x08) -+#define PINC7 7 -+#define PINC6 6 -+#define PINC5 5 -+#define PINC4 4 -+#define PINC3 3 -+#define PINC2 2 -+#define PINC1 1 -+#define PINC0 0 -+ -+#define DDRC _SFR_IO8(0x09) -+#define DDRC7 7 -+#define DDRC6 6 -+#define DDRC5 5 -+#define DDRC4 4 -+#define DDRC3 3 -+#define DDRC2 2 -+#define DDRC1 1 -+#define DDRC0 0 -+ -+#define PORTC _SFR_IO8(0x0A) -+#define PORTC7 7 -+#define PORTC6 6 -+#define PORTC5 5 -+#define PORTC4 4 -+#define PORTC3 3 -+#define PORTC2 2 -+#define PORTC1 1 -+#define PORTC0 0 -+ -+#define PUEC _SFR_IO8(0x0B) -+ -+#define PIND _SFR_IO8(0x0C) -+#define PIND3 3 -+#define PIND2 2 -+#define PIND1 1 -+#define PIND0 0 -+ -+#define DDRD _SFR_IO8(0x0D) -+#define DDRD3 3 -+#define DDRD2 2 -+#define DDRD1 1 -+#define DDRD0 0 -+ -+#define PORTD _SFR_IO8(0x0E) -+#define PORTD3 3 -+#define PORTD2 2 -+#define PORTD1 1 -+#define PORTD0 0 -+ -+#define PUED _SFR_IO8(0x0F) -+ -+/* Reserved [0x10..0x13] */ -+ -+#define PHDE _SFR_IO8(0x14) -+#define PHDEC 2 -+ -+#define TIFR0 _SFR_IO8(0x15) -+#define TOV0 0 -+#define OCF0A 1 -+#define OCF0B 2 -+ -+#define TIFR1 _SFR_IO8(0x16) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define ICF1 5 -+ -+/* Reserved [0x17..0x1A] */ -+ -+#define PCIFR _SFR_IO8(0x1B) -+#define PCIF0 0 -+#define PCIF1 1 -+#define PCIF2 2 -+#define PCIF3 3 -+ -+#define EIFR _SFR_IO8(0x1C) -+#define INTF0 0 -+#define INTF1 1 -+ -+#define EIMSK _SFR_IO8(0x1D) -+#define INT0 0 -+#define INT1 1 -+ -+#define GPIOR0 _SFR_IO8(0x1E) -+ -+#define EECR _SFR_IO8(0x1F) -+#define EERE 0 -+#define EEPE 1 -+#define EEMPE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+ -+#define EEDR _SFR_IO8(0x20) -+ -+#define EEAR _SFR_IO8(0x21) -+ -+/* Reserved [0x22] */ -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSRSYNC 0 -+#define TSM 7 -+ -+#define TCCR0A _SFR_IO8(0x24) -+#define WGM00 0 -+#define WGM01 1 -+#define COM0B0 4 -+#define COM0B1 5 -+#define COM0A0 6 -+#define COM0A1 7 -+ -+#define TCCR0B _SFR_IO8(0x25) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define WGM02 3 -+#define FOC0B 6 -+#define FOC0A 7 -+ -+#define TCNT0 _SFR_IO8(0x26) -+ -+#define OCR0A _SFR_IO8(0x27) -+ -+#define OCR0B _SFR_IO8(0x28) -+ -+/* Reserved [0x29] */ -+ -+#define GPIOR1 _SFR_IO8(0x2A) -+ -+#define GPIOR2 _SFR_IO8(0x2B) -+ -+#define SPCR _SFR_IO8(0x2C) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+#define SPSR _SFR_IO8(0x2D) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPDR _SFR_IO8(0x2E) -+ -+#define ACSRB _SFR_IO8(0x2F) -+#define ACPMUX0 0 -+#define ACPMUX1 1 -+#define ACNMUX0 2 -+#define ACNMUX1 3 -+#define HLEV 6 -+#define HSEL 7 -+ -+#define ACSRA _SFR_IO8(0x30) -+#define ACIS0 0 -+#define ACIS1 1 -+#define ACIC 2 -+#define ACIE 3 -+#define ACI 4 -+#define ACO 5 -+#define ACPMUX2 6 -+#define ACD 7 -+ -+/* Reserved [0x31..0x32] */ -+ -+#define SMCR _SFR_IO8(0x33) -+#define SE 0 -+#define SM0 1 -+#define SM1 2 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define IVSEL 1 -+ -+#define CCP _SFR_IO8(0x36) -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define RWFLB 3 -+#define RWWSRE 4 -+#define RSIG 5 -+#define RWWSB 6 -+#define SPMIE 7 -+ -+/* Reserved [0x38..0x3C] */ -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define WDTCSR _SFR_MEM8(0x60) -+#define WDE 3 -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDP3 5 -+#define WDIE 6 -+#define WDIF 7 -+ -+#define CLKPR _SFR_MEM8(0x61) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+ -+/* Reserved [0x62..0x63] */ -+ -+#define PRR _SFR_MEM8(0x64) -+#define PRADC 0 -+#define PRUSART0 1 -+#define PRSPI 2 -+#define PRTIM1 3 -+#define PRTIM0 5 -+#define PRTWI 7 -+ -+/* Reserved [0x65] */ -+ -+#define OSCCAL0 _SFR_MEM8(0x66) -+ -+#define OSCCAL1 _SFR_MEM8(0x67) -+ -+#define PCICR _SFR_MEM8(0x68) -+#define PCIE0 0 -+#define PCIE1 1 -+#define PCIE2 2 -+#define PCIE3 3 -+ -+#define EICRA _SFR_MEM8(0x69) -+#define ISC00 0 -+#define ISC01 1 -+#define ISC10 2 -+#define ISC11 3 -+ -+/* Reserved [0x6A] */ -+ -+#define PCMSK0 _SFR_MEM8(0x6B) -+#define PCINT0 0 -+#define PCINT1 1 -+#define PCINT2 2 -+#define PCINT3 3 -+#define PCINT4 4 -+#define PCINT5 5 -+#define PCINT6 6 -+#define PCINT7 7 -+ -+#define PCMSK1 _SFR_MEM8(0x6C) -+#define PCINT8 0 -+#define PCINT9 1 -+#define PCINT10 2 -+#define PCINT11 3 -+#define PCINT12 4 -+#define PCINT13 5 -+#define PCINT14 6 -+#define PCINT15 7 -+ -+#define PCMSK2 _SFR_MEM8(0x6D) -+#define PCINT16 0 -+#define PCINT17 1 -+#define PCINT18 2 -+#define PCINT19 3 -+#define PCINT20 4 -+#define PCINT21 5 -+#define PCINT22 6 -+#define PCINT23 7 -+ -+#define TIMSK0 _SFR_MEM8(0x6E) -+#define TOIE0 0 -+#define OCIE0A 1 -+#define OCIE0B 2 -+ -+#define TIMSK1 _SFR_MEM8(0x6F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define ICIE1 5 -+ -+/* Reserved [0x70..0x72] */ -+ -+#define PCMSK3 _SFR_MEM8(0x73) -+#define PCINT24 0 -+#define PCINT25 1 -+#define PCINT26 2 -+#define PCINT27 3 -+ -+/* Reserved [0x74..0x77] */ -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_MEM16(0x78) -+#endif -+#define ADCW _SFR_MEM16(0x78) -+ -+#define ADCL _SFR_MEM8(0x78) -+#define ADCH _SFR_MEM8(0x79) -+ -+#define ADCSRA _SFR_MEM8(0x7A) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+#define ADCSRB _SFR_MEM8(0x7B) -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+#define ADLAR 3 -+ -+#define ADMUXA _SFR_MEM8(0x7C) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define MUX4 4 -+ -+#define ADMUXB _SFR_MEM8(0x7D) -+#define MUX5 0 -+#define REFS 5 -+ -+#define DIDR0 _SFR_MEM8(0x7E) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+#define ADC6D 6 -+#define ADC7D 7 -+ -+#define DIDR1 _SFR_MEM8(0x7F) -+#define ADC8D 0 -+#define ADC9D 1 -+#define ADC10D 2 -+#define ADC11D 3 -+#define ADC12D 4 -+#define ADC13D 5 -+#define ADC14D 6 -+#define ADC15D 7 -+ -+#define TCCR1A _SFR_MEM8(0x80) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR1B _SFR_MEM8(0x81) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1C _SFR_MEM8(0x82) -+#define FOC1B 6 -+#define FOC1A 7 -+ -+/* Reserved [0x83] */ -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_MEM16(0x84) -+ -+#define TCNT1L _SFR_MEM8(0x84) -+#define TCNT1H _SFR_MEM8(0x85) -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_MEM16(0x86) -+ -+#define ICR1L _SFR_MEM8(0x86) -+#define ICR1H _SFR_MEM8(0x87) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_MEM16(0x88) -+ -+#define OCR1AL _SFR_MEM8(0x88) -+#define OCR1AH _SFR_MEM8(0x89) -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_MEM16(0x8A) -+ -+#define OCR1BL _SFR_MEM8(0x8A) -+#define OCR1BH _SFR_MEM8(0x8B) -+ -+/* Reserved [0x8C..0xB7] */ -+ -+#define TWSCRA _SFR_MEM8(0xB8) -+#define TWSME 0 -+#define TWPME 1 -+#define TWSIE 2 -+#define TWEN 3 -+#define TWASIE 4 -+#define TWDIE 5 -+#define TWSHE 7 -+ -+#define TWSCRB _SFR_MEM8(0xB9) -+#define TWCMD0 0 -+#define TWCMD1 1 -+#define TWAA 2 -+#define TWHNM 3 -+ -+#define TWSSRA _SFR_MEM8(0xBA) -+#define TWAS 0 -+#define TWDIR 1 -+#define TWBE 2 -+#define TWC 3 -+#define TWRA 4 -+#define TWCH 5 -+#define TWASIF 6 -+#define TWDIF 7 -+ -+#define TWSAM _SFR_MEM8(0xBB) -+#define TWAE 0 -+#define TWSAM1 1 -+#define TWSAM2 2 -+#define TWSAM3 3 -+#define TWSAM4 4 -+#define TWSAM5 5 -+#define TWSAM6 6 -+#define TWSAM7 7 -+ -+#define TWSA _SFR_MEM8(0xBC) -+ -+#define TWSD _SFR_MEM8(0xBD) -+#define TWSD0 0 -+#define TWSD1 1 -+#define TWSD2 2 -+#define TWSD3 3 -+#define TWSD4 4 -+#define TWSD5 5 -+#define TWSD6 6 -+#define TWSD7 7 -+ -+/* Reserved [0xBE..0xBF] */ -+ -+#define UCSRA _SFR_MEM8(0xC0) -+#define MPCM 0 -+#define U2X 1 -+#define UPE 2 -+#define DOR 3 -+#define FE 4 -+#define UDRE 5 -+#define TXC 6 -+#define RXC 7 -+ -+#define UCSRB _SFR_MEM8(0xC1) -+#define TXB8 0 -+#define RXB8 1 -+#define UCSZ2 2 -+#define TXEN 3 -+#define RXEN 4 -+#define UDRIE 5 -+#define TXCIE 6 -+#define RXCIE 7 -+ -+#define UCSRC _SFR_MEM8(0xC2) -+#define UCPOL 0 -+#define UCSZ0 1 -+#define UCSZ1 2 -+#define USBS 3 -+#define UPM0 4 -+#define UPM1 5 -+#define UMSEL0 6 -+#define UMSEL1 7 -+ -+#define UCSRD _SFR_MEM8(0xC3) -+#define SFDE 5 -+#define RXS 6 -+#define RXSIE 7 -+ -+/* Combine UBRRL and UBRRH */ -+#define UBRR _SFR_MEM16(0xC4) -+ -+#define UBRRL _SFR_MEM8(0xC4) -+#define UBRRH _SFR_MEM8(0xC5) -+ -+#define UDR _SFR_MEM8(0xC6) -+ -+/* Reserved [0xC7..0xDD] */ -+ -+#define DIDR2 _SFR_MEM8(0xDE) -+#define ADC16D 0 -+#define ADC17D 1 -+#define ADC18D 2 -+#define ADC19D 3 -+#define ADC20D 4 -+#define ADC21D 5 -+#define ADC22D 6 -+#define ADC23D 7 -+ -+#define DIDR3 _SFR_MEM8(0xDF) -+#define ADC24D 0 -+#define ADC25D 1 -+#define ADC26D 2 -+#define ADC27D 3 -+ -+/* Reserved [0xE0..0xE1] */ -+ -+#define TOCPMCOE _SFR_MEM8(0xE2) -+#define TOCC0OE 0 -+#define TOCC1OE 1 -+#define TOCC2OE 2 -+#define TOCC3OE 3 -+#define TOCC4OE 4 -+#define TOCC5OE 5 -+#define TOCC6OE 6 -+#define TOCC7OE 7 -+ -+/* Reserved [0xE3..0xE7] */ -+ -+#define TOCPMSA0 _SFR_MEM8(0xE8) -+#define TOCC0S0 0 -+#define TOCC0S1 1 -+#define TOCC1S0 2 -+#define TOCC1S1 3 -+#define TOCC2S0 4 -+#define TOCC2S1 5 -+#define TOCC3S0 6 -+#define TOCC3S1 7 -+ -+#define TOCPMSA1 _SFR_MEM8(0xE9) -+#define TOCC4S0 0 -+#define TOCC4S1 1 -+#define TOCC5S0 2 -+#define TOCC5S1 3 -+#define TOCC6S0 4 -+#define TOCC6S1 5 -+#define TOCC7S0 6 -+#define TOCC7S1 7 -+ -+/* Reserved [0xEA..0xEF] */ -+ -+#define OSCTCAL0A _SFR_MEM8(0xF0) -+ -+#define OSCTCAL0B _SFR_MEM8(0xF1) -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* External Interrupt Request 1 */ -+#define INT1_vect _VECTOR(2) -+#define INT1_vect_num 2 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(3) -+#define PCINT0_vect_num 3 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(4) -+#define PCINT1_vect_num 4 -+ -+/* Pin Change Interrupt Request 2 */ -+#define PCINT2_vect _VECTOR(5) -+#define PCINT2_vect_num 5 -+ -+/* Pin Change Interrupt Request 3 */ -+#define PCINT3_vect _VECTOR(6) -+#define PCINT3_vect_num 6 -+ -+/* Watchdog Time-out Interrupt */ -+#define WDT_vect _VECTOR(7) -+#define WDT_vect_num 7 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(8) -+#define TIMER1_CAPT_vect_num 8 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(9) -+#define TIMER1_COMPA_vect_num 9 -+ -+/* Timer/Counter1 Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(10) -+#define TIMER1_COMPB_vect_num 10 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(11) -+#define TIMER1_OVF_vect_num 11 -+ -+/* Timer/Counter0 Compare Match A */ -+#define TIMER0_COMPA_vect _VECTOR(12) -+#define TIMER0_COMPA_vect_num 12 -+ -+/* Timer/Counter0 Compare Match B */ -+#define TIMER0_COMPB_vect _VECTOR(13) -+#define TIMER0_COMPB_vect_num 13 -+ -+/* Timer/Counter0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(14) -+#define TIMER0_OVF_vect_num 14 -+ -+/* SPI Serial Transfer Complete */ -+#define SPI_STC_vect _VECTOR(15) -+#define SPI_STC_vect_num 15 -+ -+/* USART, Start */ -+#define USART_START_vect _VECTOR(16) -+#define USART_START_vect_num 16 -+ -+/* USART Rx Complete */ -+#define USART_RX_vect _VECTOR(17) -+#define USART_RX_vect_num 17 -+ -+/* USART, Data Register Empty */ -+#define USART_UDRE_vect _VECTOR(18) -+#define USART_UDRE_vect_num 18 -+ -+/* USART Tx Complete */ -+#define USART_TX_vect _VECTOR(19) -+#define USART_TX_vect_num 19 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(20) -+#define ADC_vect_num 20 -+ -+/* EEPROM Ready */ -+#define EE_READY_vect _VECTOR(21) -+#define EE_READY_vect_num 21 -+ -+/* Analog Comparator */ -+#define ANALOG_COMP_vect _VECTOR(22) -+#define ANALOG_COMP_vect_num 22 -+ -+/* Two-wire Serial Interface */ -+#define TWI_SLAVE_vect _VECTOR(23) -+#define TWI_SLAVE_vect_num 23 -+ -+/* Store Program Memory Read */ -+#define SPM_Ready_vect _VECTOR(24) -+#define SPM_Ready_vect_num 24 -+ -+/* Touch Sensing */ -+#define QTRIP_vect _VECTOR(25) -+#define QTRIP_vect_num 25 -+ -+#define _VECTORS_SIZE 52 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 64 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x1FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 512 -+#define RAMEND 0x02FF -+#define E2START 0 -+#define E2SIZE 256 -+#define E2PAGESIZE 4 -+#define E2END 0x00FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_DWEN (unsigned char)~_BV(6) -+#define FUSE_RSTDISBL (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_BOOTRST (unsigned char)~_BV(0) -+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) -+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) -+#define FUSE_BODACT0 (unsigned char)~_BV(4) -+#define FUSE_BODACT1 (unsigned char)~_BV(5) -+#define FUSE_BODPD0 (unsigned char)~_BV(6) -+#define FUSE_BODPD1 (unsigned char)~_BV(7) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_BITS_0_EXIST -+#define __BOOT_LOCK_BITS_1_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x93 -+#define SIGNATURE_2 0x14 -+ -+ -+#endif /* #ifdef _AVR_ATTINY828_H_INCLUDED */ -+ -diff --git a/include/avr/iotn84.h b/include/avr/iotn84.h -index 47a867f..6f3cf9c 100644 ---- a/include/avr/iotn84.h -+++ b/include/avr/iotn84.h -@@ -59,7 +59,7 @@ - #define FUSE_SUT1 (unsigned char)~_BV(5) - #define FUSE_CKOUT (unsigned char)~_BV(6) - #define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define RAMSTART (0x60) +-#define RAMEND 0xDF +-#define XRAMEND RAMEND +-#define E2END 0x7F +-#define E2PAGESIZE 4 +-#define FLASHEND 0x7FF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) -+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - - /* High Fuse Byte */ - #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -@@ -70,7 +70,7 @@ - #define FUSE_SPIEN (unsigned char)~_BV(5) - #define FUSE_DWEN (unsigned char)~_BV(6) - #define FUSE_RSTDISBL (unsigned char)~_BV(7) --#define FUSE_HFUSE_DEFAULT (FUSE_SPIEN) -+#define HFUSE_DEFAULT (FUSE_SPIEN) - - /* Extended Fuse Byte */ - #define FUSE_SELFPRGEN (unsigned char)~_BV(0) -diff --git a/include/avr/iotn841.h b/include/avr/iotn841.h -new file mode 100644 -index 0000000..1142faa ---- /dev/null -+++ b/include/avr/iotn841.h -@@ -0,0 +1,843 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_ATTINY841_H_INCLUDED -+#define _AVR_ATTINY841_H_INCLUDED -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iotn841.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+/* Registers and associated bit numbers */ -+ -+#define ADCSRB _SFR_IO8(0x04) -+#define ADTS0 0 -+#define ADTS1 1 -+#define ADTS2 2 -+#define ADLAR 3 -+ -+#define ADCSRA _SFR_IO8(0x05) -+#define ADPS0 0 -+#define ADPS1 1 -+#define ADPS2 2 -+#define ADIE 3 -+#define ADIF 4 -+#define ADATE 5 -+#define ADSC 6 -+#define ADEN 7 -+ -+/* Combine ADCL and ADCH */ -+#ifndef __ASSEMBLER__ -+#define ADC _SFR_IO16(0x06) -+#endif -+#define ADCW _SFR_IO16(0x06) -+ -+#define ADCL _SFR_IO8(0x06) -+#define ADCH _SFR_IO8(0x07) -+ -+#define ADMUXB _SFR_IO8(0x08) -+#define GSEL0 0 -+#define GSEL1 1 -+#define REFS0 5 -+#define REFS1 6 -+#define REFS2 7 -+ -+#define ADMUXA _SFR_IO8(0x09) -+#define MUX0 0 -+#define MUX1 1 -+#define MUX2 2 -+#define MUX3 3 -+#define MUX4 4 -+#define MUX5 5 -+ -+#define ACSR0A _SFR_IO8(0x0A) -+#define ACIS00 0 -+#define ACIS01 1 -+#define ACIC0 2 -+#define ACIE0 3 -+#define ACI0 4 -+#define ACO0 5 -+#define ACPMUX2 6 -+#define ACD0 7 -+ -+#define ACSR0B _SFR_IO8(0x0B) -+#define ACPMUX0 0 -+#define ACPMUX1 1 -+#define ACNMUX0 2 -+#define ACNMUX1 3 -+#define ACOE0 4 -+#define HLEV0 6 -+#define HSEL0 7 -+ -+#define ACSR1A _SFR_IO8(0x0C) -+#define ACIS10 0 -+#define ACIS11 1 -+#define ACIC1 2 -+#define ACIE1 3 -+#define ACI1 4 -+#define ACO1 5 -+#define ACBG1 6 -+#define ACD1 7 -+ -+#define ACSR1B _SFR_IO8(0x0D) -+#define ACME1 2 -+#define ACOE1 4 -+#define HLEV1 6 -+#define HSEL1 7 -+ -+#define TIFR1 _SFR_IO8(0x0E) -+#define TOV1 0 -+#define OCF1A 1 -+#define OCF1B 2 -+#define ICF1 5 -+ -+#define TIMSK1 _SFR_IO8(0x0F) -+#define TOIE1 0 -+#define OCIE1A 1 -+#define OCIE1B 2 -+#define ICIE1 5 -+ -+#define TIFR2 _SFR_IO8(0x10) -+#define TOV2 0 -+#define OCF2A 1 -+#define OCF2B 2 -+#define ICF2 5 -+ -+#define TIMSK2 _SFR_IO8(0x11) -+#define TOIE2 0 -+#define OCIE2A 1 -+#define OCIE2B 2 -+#define ICIE2 5 -+ -+#define PCMSK0 _SFR_IO8(0x12) -+ -+#define GPIOR0 _SFR_IO8(0x13) -+ -+#define GPIOR1 _SFR_IO8(0x14) -+ -+#define GPIOR2 _SFR_IO8(0x15) -+ -+#define PINB _SFR_IO8(0x16) -+#define PINB3 3 -+#define PINB2 2 -+#define PINB1 1 -+#define PINB0 0 -+ -+#define DDRB _SFR_IO8(0x17) -+#define DDRB3 3 -+#define DDRB2 2 -+#define DDRB1 1 -+#define DDRB0 0 -+ -+#define PORTB _SFR_IO8(0x18) -+#define PORTB3 3 -+#define PORTB2 2 -+#define PORTB1 1 -+#define PORTB0 0 -+ -+#define PINA _SFR_IO8(0x19) -+#define PINA7 7 -+#define PINA6 6 -+#define PINA5 5 -+#define PINA4 4 -+#define PINA3 3 -+#define PINA2 2 -+#define PINA1 1 -+#define PINA0 0 -+ -+#define DDRA _SFR_IO8(0x1A) -+#define DDRA7 7 -+#define DDRA6 6 -+#define DDRA5 5 -+#define DDRA4 4 -+#define DDRA3 3 -+#define DDRA2 2 -+#define DDRA1 1 -+#define DDRA0 0 -+ -+#define PORTA _SFR_IO8(0x1B) -+#define PORTA7 7 -+#define PORTA6 6 -+#define PORTA5 5 -+#define PORTA4 4 -+#define PORTA3 3 -+#define PORTA2 2 -+#define PORTA1 1 -+#define PORTA0 0 -+ -+#define EECR _SFR_IO8(0x1C) -+#define EERE 0 -+#define EEPE 1 -+#define EEMPE 2 -+#define EERIE 3 -+#define EEPM0 4 -+#define EEPM1 5 -+ -+#define EEDR _SFR_IO8(0x1D) -+ -+/* Combine EEARL and EEARH */ -+#define EEAR _SFR_IO16(0x1E) -+ -+#define EEARL _SFR_IO8(0x1E) -+#define EEARH _SFR_IO8(0x1F) -+ -+#define PCMSK1 _SFR_IO8(0x20) -+ -+#define WDTCSR _SFR_IO8(0x21) -+#define WDE 3 -+#define WDP0 0 -+#define WDP1 1 -+#define WDP2 2 -+#define WDP3 5 -+#define WDIE 6 -+#define WDIF 7 -+ -+#define TCCR1C _SFR_IO8(0x22) -+#define FOC1B 6 -+#define FOC1A 7 -+ -+#define GTCCR _SFR_IO8(0x23) -+#define PSR 0 -+#define TSM 7 -+ -+/* Combine ICR1L and ICR1H */ -+#define ICR1 _SFR_IO16(0x24) -+ -+#define ICR1L _SFR_IO8(0x24) -+#define ICR1H _SFR_IO8(0x25) -+ -+/* Reserved [0x26..0x27] */ -+ -+/* Combine OCR1BL and OCR1BH */ -+#define OCR1B _SFR_IO16(0x28) -+ -+#define OCR1BL _SFR_IO8(0x28) -+#define OCR1BH _SFR_IO8(0x29) -+ -+/* Combine OCR1AL and OCR1AH */ -+#define OCR1A _SFR_IO16(0x2A) -+ -+#define OCR1AL _SFR_IO8(0x2A) -+#define OCR1AH _SFR_IO8(0x2B) -+ -+/* Combine TCNT1L and TCNT1H */ -+#define TCNT1 _SFR_IO16(0x2C) -+ -+#define TCNT1L _SFR_IO8(0x2C) -+#define TCNT1H _SFR_IO8(0x2D) -+ -+#define TCCR1B _SFR_IO8(0x2E) -+#define CS10 0 -+#define CS11 1 -+#define CS12 2 -+#define WGM12 3 -+#define WGM13 4 -+#define ICES1 6 -+#define ICNC1 7 -+ -+#define TCCR1A _SFR_IO8(0x2F) -+#define WGM10 0 -+#define WGM11 1 -+#define COM1B0 4 -+#define COM1B1 5 -+#define COM1A0 6 -+#define COM1A1 7 -+ -+#define TCCR0A _SFR_IO8(0x30) -+#define WGM00 0 -+#define WGM01 1 -+#define COM0B0 4 -+#define COM0B1 5 -+#define COM0A0 6 -+#define COM0A1 7 -+ -+/* Reserved [0x31] */ -+ -+#define TCNT0 _SFR_IO8(0x32) -+ -+#define TCCR0B _SFR_IO8(0x33) -+#define CS00 0 -+#define CS01 1 -+#define CS02 2 -+#define WGM02 3 -+#define FOC0B 6 -+#define FOC0A 7 -+ -+#define MCUSR _SFR_IO8(0x34) -+#define PORF 0 -+#define EXTRF 1 -+#define BORF 2 -+#define WDRF 3 -+ -+#define MCUCR _SFR_IO8(0x35) -+#define ISC00 0 -+#define ISC01 1 -+#define SM0 3 -+#define SM1 4 -+#define SE 5 -+ -+#define OCR0A _SFR_IO8(0x36) -+ -+#define SPMCSR _SFR_IO8(0x37) -+#define SPMEN 0 -+#define PGERS 1 -+#define PGWRT 2 -+#define RFLB 3 -+#define CTPB 4 -+#define RSIG 5 -+ -+#define TIFR0 _SFR_IO8(0x38) -+#define TOV0 0 -+#define OCF0A 1 -+#define OCF0B 2 -+ -+#define TIMSK0 _SFR_IO8(0x39) -+#define TOIE0 0 -+#define OCIE0A 1 -+#define OCIE0B 2 -+ -+#define GIFR _SFR_IO8(0x3A) -+#define PCIF0 4 -+#define PCIF1 5 -+#define INTF0 6 -+ -+#define GIMSK _SFR_IO8(0x3B) -+#define PCIE0 4 -+#define PCIE1 5 -+#define INT0 6 -+ -+#define OCR0B _SFR_IO8(0x3C) -+ -+/* SP [0x3D..0x3E] */ -+ -+/* SREG [0x3F] */ -+ -+#define DIDR0 _SFR_MEM8(0x60) -+#define ADC0D 0 -+#define ADC1D 1 -+#define ADC2D 2 -+#define ADC3D 3 -+#define ADC4D 4 -+#define ADC5D 5 -+#define ADC6D 6 -+#define ADC7D 7 -+ -+#define DIDR1 _SFR_MEM8(0x61) -+#define ADC11D 0 -+#define ADC10D 1 -+#define ADC8D 2 -+#define ADC9D 3 -+ -+#define PUEB _SFR_MEM8(0x62) -+ -+#define PUEA _SFR_MEM8(0x63) -+ -+#define PORTCR _SFR_MEM8(0x64) -+#define BBMB 1 -+#define BBMA 0 -+ -+#define REMAP _SFR_MEM8(0x65) -+#define U0MAP 0 -+#define SPIMAP 1 -+ -+#define TOCPMCOE _SFR_MEM8(0x66) -+#define TOCC0OE 0 -+#define TOCC1OE 1 -+#define TOCC2OE 2 -+#define TOCC3OE 3 -+#define TOCC4OE 4 -+#define TOCC5OE 5 -+#define TOCC6OE 6 -+#define TOCC7OE 7 -+ -+#define TOCPMSA0 _SFR_MEM8(0x67) -+#define TOCC0S0 0 -+#define TOCC0S1 1 -+#define TOCC1S0 2 -+#define TOCC1S1 3 -+#define TOCC2S0 4 -+#define TOCC2S1 5 -+#define TOCC3S0 6 -+#define TOCC3S1 7 -+ -+#define TOCPMSA1 _SFR_MEM8(0x68) -+#define TOCC4S0 0 -+#define TOCC4S1 1 -+#define TOCC5S0 2 -+#define TOCC5S1 3 -+#define TOCC6S0 4 -+#define TOCC6S1 5 -+#define TOCC7S0 6 -+#define TOCC7S1 7 -+ -+/* Reserved [0x69] */ -+ -+#define PHDE _SFR_MEM8(0x6A) -+#define PHDEA0 0 -+#define PHDEA1 1 -+ -+/* Reserved [0x6B..0x6F] */ -+ -+#define PRR _SFR_MEM8(0x70) -+#define PRADC 0 -+#define PRTIM0 1 -+#define PRTIM1 2 -+#define PRTIM2 3 -+#define PRSPI 4 -+#define PRUSART0 5 -+#define PRUSART1 6 -+#define PRTWI 7 -+ -+#define CCP _SFR_MEM8(0x71) -+ -+#define CLKCR _SFR_MEM8(0x72) -+#define CKSEL0 0 -+#define CKSEL1 1 -+#define CKSEL2 2 -+#define CKSEL3 3 -+#define SUT 4 -+#define CKOUTC 5 -+#define CSTR 6 -+#define OSCRDY 7 -+ -+#define CLKPR _SFR_MEM8(0x73) -+#define CLKPS0 0 -+#define CLKPS1 1 -+#define CLKPS2 2 -+#define CLKPS3 3 -+ -+#define OSCCAL0 _SFR_MEM8(0x74) -+ -+#define OSCTCAL0A _SFR_MEM8(0x75) -+ -+#define OSCTCAL0B _SFR_MEM8(0x76) -+ -+#define OSCCAL1 _SFR_MEM8(0x77) -+ -+/* Reserved [0x78..0x7F] */ -+ -+#define UDR0 _SFR_MEM8(0x80) -+ -+/* Combine UBRR0L and UBRR0H */ -+#define UBRR0 _SFR_MEM16(0x81) -+ -+#define UBRR0L _SFR_MEM8(0x81) -+#define UBRR0H _SFR_MEM8(0x82) -+ -+#define UCSR0D _SFR_MEM8(0x83) -+#define SFDE0 5 -+#define RXS0 6 -+#define RXSIE0 7 -+ -+#define UCSR0C _SFR_MEM8(0x84) -+#define UCPOL0 0 -+#define UCSZ00 1 -+#define UCSZ01 2 -+#define USBS0 3 -+#define UPM00 4 -+#define UPM01 5 -+#define UMSEL00 6 -+#define UMSEL01 7 -+ -+#define UCSR0B _SFR_MEM8(0x85) -+#define TXB80 0 -+#define RXB80 1 -+#define UCSZ02 2 -+#define TXEN0 3 -+#define RXEN0 4 -+#define UDRIE0 5 -+#define TXCIE0 6 -+#define RXCIE0 7 -+ -+#define UCSR0A _SFR_MEM8(0x86) -+#define MPCM0 0 -+#define U2X0 1 -+#define UPE0 2 -+#define DOR0 3 -+#define FE0 4 -+#define UDRE0 5 -+#define TXC0 6 -+#define RXC0 7 -+ -+/* Reserved [0x87..0x8F] */ -+ -+#define UDR1 _SFR_MEM8(0x90) -+ -+/* Combine UBRR1L and UBRR1H */ -+#define UBRR1 _SFR_MEM16(0x91) -+ -+#define UBRR1L _SFR_MEM8(0x91) -+#define UBRR1H _SFR_MEM8(0x92) -+ -+#define UCSR1D _SFR_MEM8(0x93) -+#define SFDE1 5 -+#define RXS1 6 -+#define RXSIE1 7 -+ -+#define UCSR1C _SFR_MEM8(0x94) -+#define UCPOL1 0 -+#define UCSZ10 1 -+#define UCSZ11 2 -+#define USBS1 3 -+#define UPM10 4 -+#define UPM11 5 -+#define UMSEL10 6 -+#define UMSEL11 7 -+ -+#define UCSR1B _SFR_MEM8(0x95) -+#define TXB81 0 -+#define RXB81 1 -+#define UCSZ12 2 -+#define TXEN1 3 -+#define RXEN1 4 -+#define UDRIE1 5 -+#define TXCIE1 6 -+#define RXCIE1 7 -+ -+#define UCSR1A _SFR_MEM8(0x96) -+#define MPCM1 0 -+#define U2X1 1 -+#define UPE1 2 -+#define DOR1 3 -+#define FE1 4 -+#define UDRE1 5 -+#define TXC1 6 -+#define RXC1 7 -+ -+/* Reserved [0x97..0x9F] */ -+ -+#define TWSD _SFR_MEM8(0xA0) -+#define TWSD0 0 -+#define TWSD1 1 -+#define TWSD2 2 -+#define TWSD3 3 -+#define TWSD4 4 -+#define TWSD5 5 -+#define TWSD6 6 -+#define TWSD7 7 -+ -+#define TWSAM _SFR_MEM8(0xA1) -+#define TWAE 0 -+#define TWSAM1 1 -+#define TWSAM2 2 -+#define TWSAM3 3 -+#define TWSAM4 4 -+#define TWSAM5 5 -+#define TWSAM6 6 -+#define TWSAM7 7 -+ -+#define TWSA _SFR_MEM8(0xA2) -+ -+#define TWSSRA _SFR_MEM8(0xA3) -+#define TWAS 0 -+#define TWDIR 1 -+#define TWBE 2 -+#define TWC 3 -+#define TWRA 4 -+#define TWCH 5 -+#define TWASIF 6 -+#define TWDIF 7 -+ -+#define TWSCRB _SFR_MEM8(0xA4) -+#define TWCMD0 0 -+#define TWCMD1 1 -+#define TWAA 2 -+#define TWHNM 3 -+ -+#define TWSCRA _SFR_MEM8(0xA5) -+#define TWSME 0 -+#define TWPME 1 -+#define TWSIE 2 -+#define TWEN 3 -+#define TWASIE 4 -+#define TWDIE 5 -+#define TWSHE 7 -+ -+/* Reserved [0xA6..0xAF] */ -+ -+#define SPDR _SFR_MEM8(0xB0) -+ -+#define SPSR _SFR_MEM8(0xB1) -+#define SPI2X 0 -+#define WCOL 6 -+#define SPIF 7 -+ -+#define SPCR _SFR_MEM8(0xB2) -+#define SPR0 0 -+#define SPR1 1 -+#define CPHA 2 -+#define CPOL 3 -+#define MSTR 4 -+#define DORD 5 -+#define SPE 6 -+#define SPIE 7 -+ -+/* Reserved [0xB3..0xBF] */ -+ -+/* Combine ICR2L and ICR2H */ -+#define ICR2 _SFR_MEM16(0xC0) -+ -+#define ICR2L _SFR_MEM8(0xC0) -+#define ICR2H _SFR_MEM8(0xC1) -+ -+/* Combine OCR2BL and OCR2BH */ -+#define OCR2B _SFR_MEM16(0xC2) -+ -+#define OCR2BL _SFR_MEM8(0xC2) -+#define OCR2BH _SFR_MEM8(0xC3) -+ -+/* Combine OCR2AL and OCR2AH */ -+#define OCR2A _SFR_MEM16(0xC4) -+ -+#define OCR2AL _SFR_MEM8(0xC4) -+#define OCR2AH _SFR_MEM8(0xC5) -+ -+/* Combine TCNT2L and TCNT2H */ -+#define TCNT2 _SFR_MEM16(0xC6) -+ -+#define TCNT2L _SFR_MEM8(0xC6) -+#define TCNT2H _SFR_MEM8(0xC7) -+ -+#define TCCR2C _SFR_MEM8(0xC8) -+#define FOC2B 6 -+#define FOC2A 7 -+ -+#define TCCR2B _SFR_MEM8(0xC9) -+#define CS20 0 -+#define CS21 1 -+#define CS22 2 -+#define WGM22 3 -+#define WGM23 4 -+#define ICES2 6 -+#define ICNC2 7 -+ -+#define TCCR2A _SFR_MEM8(0xCA) -+#define WGM20 0 -+#define WGM21 1 -+#define COM2B0 4 -+#define COM2B1 5 -+#define COM2A0 6 -+#define COM2A1 7 -+ -+ -+ -+/* Interrupt vectors */ -+/* Vector 0 is the reset vector */ -+/* External Interrupt Request 0 */ -+#define INT0_vect _VECTOR(1) -+#define INT0_vect_num 1 -+ -+/* Pin Change Interrupt Request 0 */ -+#define PCINT0_vect _VECTOR(2) -+#define PCINT0_vect_num 2 -+ -+/* Pin Change Interrupt Request 1 */ -+#define PCINT1_vect _VECTOR(3) -+#define PCINT1_vect_num 3 -+ -+/* Watchdog Time-out Interrupt */ -+#define WDT_vect _VECTOR(4) -+#define WDT_vect_num 4 -+ -+/* Timer/Counter1 Capture Event */ -+#define TIMER1_CAPT_vect _VECTOR(5) -+#define TIMER1_CAPT_vect_num 5 -+ -+/* Timer/Counter1 Compare Match A */ -+#define TIMER1_COMPA_vect _VECTOR(6) -+#define TIMER1_COMPA_vect_num 6 -+ -+/* Timer/Counter1 Compare Match B */ -+#define TIMER1_COMPB_vect _VECTOR(7) -+#define TIMER1_COMPB_vect_num 7 -+ -+/* Timer/Counter1 Overflow */ -+#define TIMER1_OVF_vect _VECTOR(8) -+#define TIMER1_OVF_vect_num 8 -+ -+/* TimerCounter0 Compare Match A */ -+#define TIMER0_COMPA_vect _VECTOR(9) -+#define TIMER0_COMPA_vect_num 9 -+ -+/* TimerCounter0 Compare Match B */ -+#define TIMER0_COMPB_vect _VECTOR(10) -+#define TIMER0_COMPB_vect_num 10 -+ -+/* Timer/Couner0 Overflow */ -+#define TIMER0_OVF_vect _VECTOR(11) -+#define TIMER0_OVF_vect_num 11 -+ -+/* Analog Comparator 0 */ -+#define ANA_COMP0_vect _VECTOR(12) -+#define ANA_COMP0_vect_num 12 -+ -+/* ADC Conversion Complete */ -+#define ADC_vect _VECTOR(13) -+#define ADC_vect_num 13 -+ -+/* EEPROM Ready */ -+#define EE_RDY_vect _VECTOR(14) -+#define EE_RDY_vect_num 14 -+ -+/* Analog Comparator 1 */ -+#define ANA_COMP1_vect _VECTOR(15) -+#define ANA_COMP1_vect_num 15 -+ -+/* Timer/Counter2 Capture Event */ -+#define TIMER2_CAPT_vect _VECTOR(16) -+#define TIMER2_CAPT_vect_num 16 -+ -+/* Timer/Counter2 Compare Match A */ -+#define TIMER2_COMPA_vect _VECTOR(17) -+#define TIMER2_COMPA_vect_num 17 -+ -+/* Timer/Counter2 Compare Match B */ -+#define TIMER2_COMPB_vect _VECTOR(18) -+#define TIMER2_COMPB_vect_num 18 -+ -+/* Timer/Counter2 Overflow */ -+#define TIMER2_OVF_vect _VECTOR(19) -+#define TIMER2_OVF_vect_num 19 -+ -+/* Serial Peripheral Interface */ -+#define SPI_vect _VECTOR(20) -+#define SPI_vect_num 20 -+ -+/* USART0, Start */ -+#define USART0_START_vect _VECTOR(21) -+#define USART0_START_vect_num 21 -+ -+/* USART0, Rx Complete */ -+#define USART0_RX_vect _VECTOR(22) -+#define USART0_RX_vect_num 22 -+ -+/* USART0 Data Register Empty */ -+#define USART0_UDRE_vect _VECTOR(23) -+#define USART0_UDRE_vect_num 23 -+ -+/* USART0, Tx Complete */ -+#define USART0_TX_vect _VECTOR(24) -+#define USART0_TX_vect_num 24 -+ -+/* USART1, Start */ -+#define USART1_START_vect _VECTOR(25) -+#define USART1_START_vect_num 25 -+ -+/* USART1, Rx Complete */ -+#define USART1_RX_vect _VECTOR(26) -+#define USART1_RX_vect_num 26 -+ -+/* USART1 Data Register Empty */ -+#define USART1_UDRE_vect _VECTOR(27) -+#define USART1_UDRE_vect_num 27 -+ -+/* USART1, Tx Complete */ -+#define USART1_TX_vect _VECTOR(28) -+#define USART1_TX_vect_num 28 -+ -+/* Two-wire Serial Interface */ -+#define TWI_SLAVE_vect _VECTOR(29) -+#define TWI_SLAVE_vect_num 29 -+ -+#define _VECTORS_SIZE 60 -+ -+ -+/* Constants */ -+ -+#define SPM_PAGESIZE 16 -+#define FLASHSTART 0x0000 -+#define FLASHEND 0x1FFF -+#define RAMSTART 0x0100 -+#define RAMSIZE 512 -+#define RAMEND 0x02FF -+#define E2START 0 -+#define E2SIZE 512 -+#define E2PAGESIZE 4 -+#define E2END 0x01FF -+#define XRAMEND RAMEND -+ -+ -+/* Fuses */ -+ -+#define FUSE_MEMORY_SIZE 3 -+ -+/* Low Fuse Byte */ -+#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) -+#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) -+#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) -+#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) -+#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) -+#define FUSE_CKOUT (unsigned char)~_BV(6) -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) -+ -+/* High Fuse Byte */ -+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) -+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) -+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) -+#define FUSE_EESAVE (unsigned char)~_BV(3) -+#define FUSE_WDTON (unsigned char)~_BV(4) -+#define FUSE_SPIEN (unsigned char)~_BV(5) -+#define FUSE_DWEN (unsigned char)~_BV(6) -+#define FUSE_RSTDISBL (unsigned char)~_BV(7) -+ -+/* Extended Fuse Byte */ -+#define FUSE_SELFPRGEN (unsigned char)~_BV(0) -+#define FUSE_BODACT0 (unsigned char)~_BV(1) -+#define FUSE_BODACT1 (unsigned char)~_BV(2) -+#define FUSE_BODPD0 (unsigned char)~_BV(3) -+#define FUSE_BODPD1 (unsigned char)~_BV(4) -+#define FUSE_ULPOSCSEL0 (unsigned char)~_BV(5) -+#define FUSE_ULPOSCSEL1 (unsigned char)~_BV(6) -+#define FUSE_ULPOSCSEL2 (unsigned char)~_BV(7) -+ -+ -+/* Lock Bits */ -+#define __LOCK_BITS_EXIST -+ -+ -+/* Signature */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x93 -+#define SIGNATURE_2 0x15 -+ -+ -+#endif /* #ifdef _AVR_ATTINY841_H_INCLUDED */ -+ -diff --git a/include/avr/iotn84a.h b/include/avr/iotn84a.h -index 2099df6..f452a4b 100755 ---- a/include/avr/iotn84a.h -+++ b/include/avr/iotn84a.h -@@ -486,10 +486,12 @@ - #define MCUCR _SFR_IO8(0x35) - #define ISC00 0 - #define ISC01 1 -+#define BODSE 2 - #define SM0 3 - #define SM1 4 - #define SE 5 - #define PUD 6 -+#define BODS 7 - - #define OCR0A _SFR_IO8(0x36) - #define OCR0A_0 0 -@@ -595,26 +597,26 @@ - #define FUSE_MEMORY_SIZE 3 - - /* Low Fuse Byte */ +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_DWEN (unsigned char)~_BV(6) +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_SELFPRGEN (unsigned char)~_BV(0) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x91 +-#define SIGNATURE_2 0x0B +- +- +-#endif /* _AVR_IOTN24_H_ */ ++/* Copyright (c) 2005, Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn24.h 2115 2010-04-05 23:19:53Z arcanum $ */ ++ ++/* avr/iotn24.h - definitions for ATtiny24 */ ++ ++#ifndef _AVR_IOTN24_H_ ++#define _AVR_IOTN24_H_ 1 ++ ++#include ++ ++#define SPM_PAGESIZE 32 ++#define RAMSTART (0x60) ++#define RAMEND 0xDF ++#define XRAMEND RAMEND ++#define E2END 0x7F ++#define E2PAGESIZE 4 ++#define FLASHEND 0x7FF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x91 ++#define SIGNATURE_2 0x0B ++ ++ ++#endif /* _AVR_IOTN24_H_ */ +diff --git a/include/avr/iotn24a.h b/include/avr/iotn24a.h +index f260215..6f1d352 100644 +--- a/include/avr/iotn24a.h ++++ b/include/avr/iotn24a.h +@@ -1,831 +1,835 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn24a.h 2035 2009-11-02 02:44:17Z arcanum $ */ +- +-/* avr/iotn24a.h - definitions for ATtiny24A */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn24a.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATtiny24A_H_ +-#define _AVR_ATtiny24A_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PRR _SFR_IO8(0x00) +-#define PRADC 0 +-#define PRUSI 1 +-#define PRTIM0 2 +-#define PRTIM1 3 +- +-#define DIDR0 _SFR_IO8(0x01) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define ADCSRB _SFR_IO8(0x03) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ADLAR 4 +-#define ACME 6 +-#define BIN 7 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x04) +-#endif +-#define ADCW _SFR_IO16(0x04) +- +-#define ADCL _SFR_IO8(0x04) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_IO8(0x05) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_IO8(0x06) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADMUX _SFR_IO8(0x07) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define MUX5 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define ACSR _SFR_IO8(0x08) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define TIFR1 _SFR_IO8(0x0B) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define TIMSK1 _SFR_IO8(0x0C) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define USICR _SFR_IO8(0x0D) +-#define USITC 0 +-#define USICLK 1 +-#define USICS0 2 +-#define USICS1 3 +-#define USIWM0 4 +-#define USIWM1 5 +-#define USIOIE 6 +-#define USISIE 7 +- +-#define USISR _SFR_IO8(0x0E) +-#define USICNT0 0 +-#define USICNT1 1 +-#define USICNT2 2 +-#define USICNT3 3 +-#define USIDC 4 +-#define USIPF 5 +-#define USIOIF 6 +-#define USISIF 7 +- +-#define USIDR _SFR_IO8(0x0F) +-#define USIDR0 0 +-#define USIDR1 1 +-#define USIDR2 2 +-#define USIDR3 3 +-#define USIDR4 4 +-#define USIDR5 5 +-#define USIDR6 6 +-#define USIDR7 7 +- +-#define USIBR _SFR_IO8(0x10) +-#define USIBR0 0 +-#define USIBR1 1 +-#define USIBR2 2 +-#define USIBR3 3 +-#define USIBR4 4 +-#define USIBR5 5 +-#define USIBR6 6 +-#define USIBR7 7 +- +-#define PCMSK0 _SFR_IO8(0x12) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define GPIOR0 _SFR_IO8(0x13) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define GPIOR1 _SFR_IO8(0x14) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x15) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define PINB _SFR_IO8(0x16) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +- +-#define DDRB _SFR_IO8(0x17) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +- +-#define PORTB _SFR_IO8(0x18) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +- +-#define PINA _SFR_IO8(0x19) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +-#define PINA4 4 +-#define PINA5 5 +-#define PINA6 6 +-#define PINA7 7 +- +-#define DDRA _SFR_IO8(0x1A) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +-#define DDA4 4 +-#define DDA5 5 +-#define DDA6 6 +-#define DDA7 7 +- +-#define PORTA _SFR_IO8(0x1B) +-#define PORTA0 0 +-#define PORTA1 1 +-#define PORTA2 2 +-#define PORTA3 3 +-#define PORTA4 4 +-#define PORTA5 5 +-#define PORTA6 6 +-#define PORTA7 7 +- +-#define EECR _SFR_IO8(0x1C) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x1D) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x1E) +- +-#define EEARL _SFR_IO8(0x1E) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x1F) +-#define EEAR8 0 +- +-#define PCMSK1 _SFR_IO8(0x20) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +- +-#define WDTCSR _SFR_IO8(0x21) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define TCCR1C _SFR_IO8(0x22) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSR10 0 +-#define TSM 7 +- +-#define ICR1 _SFR_IO16(0x24) +- +-#define ICR1L _SFR_IO8(0x24) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_IO8(0x25) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define CLKPR _SFR_IO8(0x26) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define DWDR _SFR_IO8(0x27) +- +-#define OCR1B _SFR_IO16(0x28) +- +-#define OCR1BL _SFR_IO8(0x28) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_IO8(0x29) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define OCR1A _SFR_IO16(0x2A) +- +-#define OCR1AL _SFR_IO8(0x2A) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_IO8(0x2B) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define TCNT1 _SFR_IO16(0x2C) +- +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_IO8(0x2D) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define TCCR1B _SFR_IO8(0x2E) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1A _SFR_IO8(0x2F) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR0A _SFR_IO8(0x30) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define OSCCAL _SFR_IO8(0x31) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define TCNT0 _SFR_IO8(0x32) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define TCCR0B _SFR_IO8(0x33) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x35) +-#define ISC00 0 +-#define ISC01 1 +-#define SM0 3 +-#define SM1 4 +-#define SE 5 +-#define PUD 6 +- +-#define OCR0A _SFR_IO8(0x36) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define RFLB 3 +-#define CTPB 4 +- +-#define TIFR0 _SFR_IO8(0x38) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIMSK0 _SFR_IO8(0x39) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define GIFR _SFR_IO8(0x3A) +-#define PCIF0 4 +-#define PCIF1 5 +-#define INTF0 6 +- +-#define GIMSK _SFR_IO8(0x3B) +-#define PCIE0 4 +-#define PCIE1 5 +-#define INT0 6 +- +-#define OCR0B _SFR_IO8(0x3C) +-#define OCR0_0 0 +-#define OCR0_1 1 +-#define OCR0_2 2 +-#define OCR0_3 3 +-#define OCR0_4 4 +-#define OCR0_5 5 +-#define OCR0_6 6 +-#define OCR0_7 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define EXT_INT0_vect_num 1 +-#define EXT_INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ +-#define PCINT1_vect_num 3 +-#define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */ +-#define WATCHDOG_vect_num 4 +-#define WATCHDOG_vect _VECTOR(4) /* Watchdog Time-out */ +-#define TIM1_CAPT_vect_num 5 +-#define TIM1_CAPT_vect _VECTOR(5) /* Timer/Counter1 Capture Event */ +-#define TIM1_COMPA_vect_num 6 +-#define TIM1_COMPA_vect _VECTOR(6) /* Timer/Counter1 Compare Match A */ +-#define TIM1_COMPB_vect_num 7 +-#define TIM1_COMPB_vect _VECTOR(7) /* Timer/Counter1 Compare Match B */ +-#define TIM1_OVF_vect_num 8 +-#define TIM1_OVF_vect _VECTOR(8) /* Timer/Counter1 Overflow */ +-#define TIM0_COMPA_vect_num 9 +-#define TIM0_COMPA_vect _VECTOR(9) /* Timer/Counter0 Compare Match A */ +-#define TIM0_COMPB_vect_num 10 +-#define TIM0_COMPB_vect _VECTOR(10) /* Timer/Counter0 Compare Match B */ +-#define TIM0_OVF_vect_num 11 +-#define TIM0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ +-#define ANA_COMP_vect_num 12 +-#define ANA_COMP_vect _VECTOR(12) /* Analog Comparator */ +-#define ADC_vect_num 13 +-#define ADC_vect _VECTOR(13) /* ADC Conversion Complete */ +-#define EE_RDY_vect_num 14 +-#define EE_RDY_vect _VECTOR(14) /* EEPROM Ready */ +-#define USI_STR_vect_num 15 +-#define USI_STR_vect _VECTOR(15) /* USI START */ +-#define USI_OVF_vect_num 16 +-#define USI_OVF_vect _VECTOR(16) /* USI Overflow */ +- +-#define _VECTOR_SIZE 2 /* Size of individual vector. */ +-#define _VECTORS_SIZE (17 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (32) +-#define RAMSTART (0x60) +-#define RAMSIZE (128) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x7F) +-#define E2PAGESIZE (4) +-#define FLASHEND (0x7FF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ -#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ -#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ -#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ @@ -65079,88 +252158,50452 @@ index 2099df6..f452a4b 100755 -#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ -#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ -#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_SUT0 & FUSE_CKDIV8) -+#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ -+#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ -+#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ -+#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */ -+#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ -+#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ -+#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ -+#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ -+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) - - /* High Fuse Byte */ - #define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ - #define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ - #define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ -#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ -#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always on */ -#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ -#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ -#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ -#define HFUSE_DEFAULT (FUSE_SPIEN) -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ -+#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always on */ -+#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ -+#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ -+#define HFUSE_DEFAULT (FUSE_SPIEN) - - /* Extended Fuse Byte */ - #define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ -diff --git a/include/avr/iotn88.h b/include/avr/iotn88.h -index 8213a53..43db0b4 100644 ---- a/include/avr/iotn88.h -+++ b/include/avr/iotn88.h -@@ -749,7 +749,7 @@ - #define E2END 0x3F - #define E2PAGESIZE 4 - #define FLASHEND 0x1FFF +- +-/* Extended Fuse Byte */ +-#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x91 +-#define SIGNATURE_2 0x0B +- +- +-/* Device Pin Definitions */ +-#define ADC4_DDR DDRA +-#define ADC4_PORT PORTA +-#define ADC4_PIN PINA +-#define ADC4_BIT 4 +- +-#define USCK_DDR DDRA +-#define USCK_PORT PORTA +-#define USCK_PIN PINA +-#define USCK_BIT 4 +- +-#define SCL_DDR DDRA +-#define SCL_PORT PORTA +-#define SCL_PIN PINA +-#define SCL_BIT 4 +- +-#define T1_DDR DDRA +-#define T1_PORT PORTA +-#define T1_PIN PINA +-#define T1_BIT 4 +- +-#define PCINT4_DDR DDRA +-#define PCINT4_PORT PORTA +-#define PCINT4_PIN PINA +-#define PCINT4_BIT 4 +- +-#define ADC3_DDR DDRA +-#define ADC3_PORT PORTA +-#define ADC3_PIN PINA +-#define ADC3_BIT 3 +- +-#define T0_DDR DDRA +-#define T0_PORT PORTA +-#define T0_PIN PINA +-#define T0_BIT 3 +- +-#define PCINT3_DDR DDRA +-#define PCINT3_PORT PORTA +-#define PCINT3_PIN PINA +-#define PCINT3_BIT 3 +- +-#define ADC2_DDR DDRA +-#define ADC2_PORT PORTA +-#define ADC2_PIN PINA +-#define ADC2_BIT 2 +- +-#define AIN1_DDR DDRA +-#define AIN1_PORT PORTA +-#define AIN1_PIN PINA +-#define AIN1_BIT 2 +- +-#define PCINT2_DDR DDRA +-#define PCINT2_PORT PORTA +-#define PCINT2_PIN PINA +-#define PCINT2_BIT 2 +- +-#define ADC1_DDR DDRA +-#define ADC1_PORT PORTA +-#define ADC1_PIN PINA +-#define ADC1_BIT 1 +- +-#define AIN0_DDR DDRA +-#define AIN0_PORT PORTA +-#define AIN0_PIN PINA +-#define AIN0_BIT 1 +- +-#define PCINT1_DDR DDRA +-#define PCINT1_PORT PORTA +-#define PCINT1_PIN PINA +-#define PCINT1_BIT 1 +- +-#define ADC0_DDR DDRA +-#define ADC0_PORT PORTA +-#define ADC0_PIN PINA +-#define ADC0_BIT 0 +- +-#define PCINT0_DDR DDRA +-#define PCINT0_PORT PORTA +-#define PCINT0_PIN PINA +-#define PCINT0_BIT 0 +- +-#define PCINT8_DDR DDRB +-#define PCINT8_PORT PORTB +-#define PCINT8_PIN PINB +-#define PCINT8_BIT 0 +- +-#define PCINT9_DDR DDRB +-#define PCINT9_PORT PORTB +-#define PCINT9_PIN PINB +-#define PCINT9_BIT 1 +- +-#define PCINT11_DDR DDRB +-#define PCINT11_PORT PORTB +-#define PCINT11_PIN PINB +-#define PCINT11_BIT 3 +- +-#define dW_DDR DDRB +-#define dW_PORT PORTB +-#define dW_PIN PINB +-#define dW_BIT 3 +- +-#define PCINT10_DDR DDRB +-#define PCINT10_PORT PORTB +-#define PCINT10_PIN PINB +-#define PCINT10_BIT 2 +- +-#define INT0_DDR DDRB +-#define INT0_PORT PORTB +-#define INT0_PIN PINB +-#define INT0_BIT 2 +- +-#define OC0A_DDR DDRB +-#define OC0A_PORT PORTB +-#define OC0A_PIN PINB +-#define OC0A_BIT 2 +- +-#define CKOUT_DDR DDRB +-#define CKOUT_PORT PORTB +-#define CKOUT_PIN PINB +-#define CKOUT_BIT 2 +- +-#define PCINT7_DDR DDRA +-#define PCINT7_PORT PORTA +-#define PCINT7_PIN PINA +-#define PCINT7_BIT 7 +- +-#define ICP1_DDR DDRA +-#define ICP1_PORT PORTA +-#define ICP1_PIN PINA +-#define ICP1_BIT 7 +- +-#define OC0B_DDR DDRA +-#define OC0B_PORT PORTA +-#define OC0B_PIN PINA +-#define OC0B_BIT 7 +- +-#define ADC7_DDR DDRA +-#define ADC7_PORT PORTA +-#define ADC7_PIN PINA +-#define ADC7_BIT 7 +- +-#define PCINT6_DDR DDRA +-#define PCINT6_PORT PORTA +-#define PCINT6_PIN PINA +-#define PCINT6_BIT 6 +- +-#define OC1A_DDR DDRA +-#define OC1A_PORT PORTA +-#define OC1A_PIN PINA +-#define OC1A_BIT 6 +- +-#define DI_DDR DDRA +-#define DI_PORT PORTA +-#define DI_PIN PINA +-#define DI_BIT 6 +- +-#define SDA_DDR DDRA +-#define SDA_PORT PORTA +-#define SDA_PIN PINA +-#define SDA_BIT 6 +- +-#define MOSI_DDR DDRA +-#define MOSI_PORT PORTA +-#define MOSI_PIN PINA +-#define MOSI_BIT 6 +- +-#define ADC6_DDR DDRA +-#define ADC6_PORT PORTA +-#define ADC6_PIN PINA +-#define ADC6_BIT 6 +- +-#define ADC5_DDR DDRA +-#define ADC5_PORT PORTA +-#define ADC5_PIN PINA +-#define ADC5_BIT 5 +- +-#define DO_DDR DDRA +-#define DO_PORT PORTA +-#define DO_PIN PINA +-#define DO_BIT 5 +- +-#define MISO_DDR DDRA +-#define MISO_PORT PORTA +-#define MISO_PIN PINA +-#define MISO_BIT 5 +- +-#define OC1B_DDR DDRA +-#define OC1B_PORT PORTA +-#define OC1B_PIN PINA +-#define OC1B_BIT 5 +- +-#define PCINT5_DDR DDRA +-#define PCINT5_PORT PORTA +-#define PCINT5_PIN PINA +-#define PCINT5_BIT 5 +- +-#endif /* _AVR_ATtiny24A_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn24a.h 2414 2014-03-21 16:04:00Z pitchumani $ */ ++ ++/* avr/iotn24a.h - definitions for ATtiny24A */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn24a.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATtiny24A_H_ ++#define _AVR_ATtiny24A_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PRR _SFR_IO8(0x00) ++#define PRADC 0 ++#define PRUSI 1 ++#define PRTIM0 2 ++#define PRTIM1 3 ++ ++#define DIDR0 _SFR_IO8(0x01) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define ADCSRB _SFR_IO8(0x03) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ADLAR 4 ++#define ACME 6 ++#define BIN 7 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCW _SFR_IO16(0x04) ++ ++#define ADCL _SFR_IO8(0x04) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_IO8(0x05) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_IO8(0x06) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADMUX _SFR_IO8(0x07) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define MUX5 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define ACSR _SFR_IO8(0x08) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define TIFR1 _SFR_IO8(0x0B) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIMSK1 _SFR_IO8(0x0C) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define USICR _SFR_IO8(0x0D) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_IO8(0x0E) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_IO8(0x0F) ++#define USIDR0 0 ++#define USIDR1 1 ++#define USIDR2 2 ++#define USIDR3 3 ++#define USIDR4 4 ++#define USIDR5 5 ++#define USIDR6 6 ++#define USIDR7 7 ++ ++#define USIBR _SFR_IO8(0x10) ++#define USIBR0 0 ++#define USIBR1 1 ++#define USIBR2 2 ++#define USIBR3 3 ++#define USIBR4 4 ++#define USIBR5 5 ++#define USIBR6 6 ++#define USIBR7 7 ++ ++#define PCMSK0 _SFR_IO8(0x12) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define GPIOR0 _SFR_IO8(0x13) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define GPIOR1 _SFR_IO8(0x14) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x15) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define PINB _SFR_IO8(0x16) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++ ++#define DDRB _SFR_IO8(0x17) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++ ++#define PORTB _SFR_IO8(0x18) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++ ++#define PINA _SFR_IO8(0x19) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++#define PINA4 4 ++#define PINA5 5 ++#define PINA6 6 ++#define PINA7 7 ++ ++#define DDRA _SFR_IO8(0x1A) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++#define DDA4 4 ++#define DDA5 5 ++#define DDA6 6 ++#define DDA7 7 ++ ++#define PORTA _SFR_IO8(0x1B) ++#define PORTA0 0 ++#define PORTA1 1 ++#define PORTA2 2 ++#define PORTA3 3 ++#define PORTA4 4 ++#define PORTA5 5 ++#define PORTA6 6 ++#define PORTA7 7 ++ ++#define EECR _SFR_IO8(0x1C) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x1D) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x1E) ++ ++#define EEARL _SFR_IO8(0x1E) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x1F) ++#define EEAR8 0 ++ ++#define PCMSK1 _SFR_IO8(0x20) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++ ++#define WDTCSR _SFR_IO8(0x21) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define TCCR1C _SFR_IO8(0x22) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR10 0 ++#define TSM 7 ++ ++#define ICR1 _SFR_IO16(0x24) ++ ++#define ICR1L _SFR_IO8(0x24) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_IO8(0x25) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define CLKPR _SFR_IO8(0x26) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define DWDR _SFR_IO8(0x27) ++ ++#define OCR1B _SFR_IO16(0x28) ++ ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_IO8(0x29) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define OCR1A _SFR_IO16(0x2A) ++ ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_IO8(0x2B) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define TCNT1 _SFR_IO16(0x2C) ++ ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_IO8(0x2D) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define TCCR1B _SFR_IO8(0x2E) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1A _SFR_IO8(0x2F) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR0A _SFR_IO8(0x30) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define OSCCAL _SFR_IO8(0x31) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define TCNT0 _SFR_IO8(0x32) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define TCCR0B _SFR_IO8(0x33) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define ISC00 0 ++#define ISC01 1 ++#define BODSE 2 ++#define SM0 3 ++#define SM1 4 ++#define SE 5 ++#define PUD 6 ++#define BODS 7 ++ ++#define OCR0A _SFR_IO8(0x36) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define RFLB 3 ++#define CTPB 4 ++ ++#define TIFR0 _SFR_IO8(0x38) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIMSK0 _SFR_IO8(0x39) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define GIFR _SFR_IO8(0x3A) ++#define PCIF0 4 ++#define PCIF1 5 ++#define INTF0 6 ++ ++#define GIMSK _SFR_IO8(0x3B) ++#define PCIE0 4 ++#define PCIE1 5 ++#define INT0 6 ++ ++#define OCR0B _SFR_IO8(0x3C) ++#define OCR0_0 0 ++#define OCR0_1 1 ++#define OCR0_2 2 ++#define OCR0_3 3 ++#define OCR0_4 4 ++#define OCR0_5 5 ++#define OCR0_6 6 ++#define OCR0_7 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define EXT_INT0_vect_num 1 ++#define EXT_INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect_num 3 ++#define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */ ++#define WDT_vect_num 4 ++#define WDT_vect _VECTOR(4) /* Watchdog Time-out */ ++#define WATCHDOG_vect_num 4 ++#define WATCHDOG_vect _VECTOR(4) /* alias */ ++#define TIM1_CAPT_vect_num 5 ++#define TIM1_CAPT_vect _VECTOR(5) /* Timer/Counter1 Capture Event */ ++#define TIM1_COMPA_vect_num 6 ++#define TIM1_COMPA_vect _VECTOR(6) /* Timer/Counter1 Compare Match A */ ++#define TIM1_COMPB_vect_num 7 ++#define TIM1_COMPB_vect _VECTOR(7) /* Timer/Counter1 Compare Match B */ ++#define TIM1_OVF_vect_num 8 ++#define TIM1_OVF_vect _VECTOR(8) /* Timer/Counter1 Overflow */ ++#define TIM0_COMPA_vect_num 9 ++#define TIM0_COMPA_vect _VECTOR(9) /* Timer/Counter0 Compare Match A */ ++#define TIM0_COMPB_vect_num 10 ++#define TIM0_COMPB_vect _VECTOR(10) /* Timer/Counter0 Compare Match B */ ++#define TIM0_OVF_vect_num 11 ++#define TIM0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ ++#define ANA_COMP_vect_num 12 ++#define ANA_COMP_vect _VECTOR(12) /* Analog Comparator */ ++#define ADC_vect_num 13 ++#define ADC_vect _VECTOR(13) /* ADC Conversion Complete */ ++#define EE_RDY_vect_num 14 ++#define EE_RDY_vect _VECTOR(14) /* EEPROM Ready */ ++#define USI_STR_vect_num 15 ++#define USI_STR_vect _VECTOR(15) /* USI START */ ++#define USI_OVF_vect_num 16 ++#define USI_OVF_vect _VECTOR(16) /* USI Overflow */ ++ ++#define _VECTOR_SIZE 2 /* Size of individual vector. */ ++#define _VECTORS_SIZE (17 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (32) ++#define RAMSTART (0x60) ++#define RAMSIZE (128) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x7F) ++#define E2PAGESIZE (4) ++#define FLASHEND (0x7FF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x91 ++#define SIGNATURE_2 0x0B ++ ++ ++/* Device Pin Definitions */ ++#define ADC4_DDR DDRA ++#define ADC4_PORT PORTA ++#define ADC4_PIN PINA ++#define ADC4_BIT 4 ++ ++#define USCK_DDR DDRA ++#define USCK_PORT PORTA ++#define USCK_PIN PINA ++#define USCK_BIT 4 ++ ++#define SCL_DDR DDRA ++#define SCL_PORT PORTA ++#define SCL_PIN PINA ++#define SCL_BIT 4 ++ ++#define T1_DDR DDRA ++#define T1_PORT PORTA ++#define T1_PIN PINA ++#define T1_BIT 4 ++ ++#define PCINT4_DDR DDRA ++#define PCINT4_PORT PORTA ++#define PCINT4_PIN PINA ++#define PCINT4_BIT 4 ++ ++#define ADC3_DDR DDRA ++#define ADC3_PORT PORTA ++#define ADC3_PIN PINA ++#define ADC3_BIT 3 ++ ++#define T0_DDR DDRA ++#define T0_PORT PORTA ++#define T0_PIN PINA ++#define T0_BIT 3 ++ ++#define PCINT3_DDR DDRA ++#define PCINT3_PORT PORTA ++#define PCINT3_PIN PINA ++#define PCINT3_BIT 3 ++ ++#define ADC2_DDR DDRA ++#define ADC2_PORT PORTA ++#define ADC2_PIN PINA ++#define ADC2_BIT 2 ++ ++#define AIN1_DDR DDRA ++#define AIN1_PORT PORTA ++#define AIN1_PIN PINA ++#define AIN1_BIT 2 ++ ++#define PCINT2_DDR DDRA ++#define PCINT2_PORT PORTA ++#define PCINT2_PIN PINA ++#define PCINT2_BIT 2 ++ ++#define ADC1_DDR DDRA ++#define ADC1_PORT PORTA ++#define ADC1_PIN PINA ++#define ADC1_BIT 1 ++ ++#define AIN0_DDR DDRA ++#define AIN0_PORT PORTA ++#define AIN0_PIN PINA ++#define AIN0_BIT 1 ++ ++#define PCINT1_DDR DDRA ++#define PCINT1_PORT PORTA ++#define PCINT1_PIN PINA ++#define PCINT1_BIT 1 ++ ++#define ADC0_DDR DDRA ++#define ADC0_PORT PORTA ++#define ADC0_PIN PINA ++#define ADC0_BIT 0 ++ ++#define PCINT0_DDR DDRA ++#define PCINT0_PORT PORTA ++#define PCINT0_PIN PINA ++#define PCINT0_BIT 0 ++ ++#define PCINT8_DDR DDRB ++#define PCINT8_PORT PORTB ++#define PCINT8_PIN PINB ++#define PCINT8_BIT 0 ++ ++#define PCINT9_DDR DDRB ++#define PCINT9_PORT PORTB ++#define PCINT9_PIN PINB ++#define PCINT9_BIT 1 ++ ++#define PCINT11_DDR DDRB ++#define PCINT11_PORT PORTB ++#define PCINT11_PIN PINB ++#define PCINT11_BIT 3 ++ ++#define dW_DDR DDRB ++#define dW_PORT PORTB ++#define dW_PIN PINB ++#define dW_BIT 3 ++ ++#define PCINT10_DDR DDRB ++#define PCINT10_PORT PORTB ++#define PCINT10_PIN PINB ++#define PCINT10_BIT 2 ++ ++#define INT0_DDR DDRB ++#define INT0_PORT PORTB ++#define INT0_PIN PINB ++#define INT0_BIT 2 ++ ++#define OC0A_DDR DDRB ++#define OC0A_PORT PORTB ++#define OC0A_PIN PINB ++#define OC0A_BIT 2 ++ ++#define CKOUT_DDR DDRB ++#define CKOUT_PORT PORTB ++#define CKOUT_PIN PINB ++#define CKOUT_BIT 2 ++ ++#define PCINT7_DDR DDRA ++#define PCINT7_PORT PORTA ++#define PCINT7_PIN PINA ++#define PCINT7_BIT 7 ++ ++#define ICP1_DDR DDRA ++#define ICP1_PORT PORTA ++#define ICP1_PIN PINA ++#define ICP1_BIT 7 ++ ++#define OC0B_DDR DDRA ++#define OC0B_PORT PORTA ++#define OC0B_PIN PINA ++#define OC0B_BIT 7 ++ ++#define ADC7_DDR DDRA ++#define ADC7_PORT PORTA ++#define ADC7_PIN PINA ++#define ADC7_BIT 7 ++ ++#define PCINT6_DDR DDRA ++#define PCINT6_PORT PORTA ++#define PCINT6_PIN PINA ++#define PCINT6_BIT 6 ++ ++#define OC1A_DDR DDRA ++#define OC1A_PORT PORTA ++#define OC1A_PIN PINA ++#define OC1A_BIT 6 ++ ++#define DI_DDR DDRA ++#define DI_PORT PORTA ++#define DI_PIN PINA ++#define DI_BIT 6 ++ ++#define SDA_DDR DDRA ++#define SDA_PORT PORTA ++#define SDA_PIN PINA ++#define SDA_BIT 6 ++ ++#define MOSI_DDR DDRA ++#define MOSI_PORT PORTA ++#define MOSI_PIN PINA ++#define MOSI_BIT 6 ++ ++#define ADC6_DDR DDRA ++#define ADC6_PORT PORTA ++#define ADC6_PIN PINA ++#define ADC6_BIT 6 ++ ++#define ADC5_DDR DDRA ++#define ADC5_PORT PORTA ++#define ADC5_PIN PINA ++#define ADC5_BIT 5 ++ ++#define DO_DDR DDRA ++#define DO_PORT PORTA ++#define DO_PIN PINA ++#define DO_BIT 5 ++ ++#define MISO_DDR DDRA ++#define MISO_PORT PORTA ++#define MISO_PIN PINA ++#define MISO_BIT 5 ++ ++#define OC1B_DDR DDRA ++#define OC1B_PORT PORTA ++#define OC1B_PIN PINA ++#define OC1B_BIT 5 ++ ++#define PCINT5_DDR DDRA ++#define PCINT5_PORT PORTA ++#define PCINT5_PIN PINA ++#define PCINT5_BIT 5 ++ ++#endif /* _AVR_ATtiny24A_H_ */ ++ +diff --git a/include/avr/iotn25.h b/include/avr/iotn25.h +index b2a7bfd..f8b5e9a 100644 +--- a/include/avr/iotn25.h ++++ b/include/avr/iotn25.h +@@ -1,90 +1,90 @@ +-/* Copyright (c) 2005, Joerg Wunsch +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn25.h 2115 2010-04-05 23:19:53Z arcanum $ */ +- +-/* avr/iotn25.h - definitions for ATtiny25 */ +- +-#ifndef _AVR_IOTN25_H_ +-#define _AVR_IOTN25_H_ 1 +- +-#include +- -#define SPM_PAGESIZE 32 -+#define SPM_PAGESIZE 64 - - - /* Fuse Information */ -diff --git a/include/avr/iox128a1u.h b/include/avr/iox128a1u.h -index e8f4163..0b61d9e 100644 ---- a/include/avr/iox128a1u.h -+++ b/include/avr/iox128a1u.h -@@ -1,38 +1,36 @@ +-#define RAMSTART (0x60) +-#define RAMEND 0xDF +-#define XRAMEND RAMEND +-#define E2END 0x7F +-#define E2PAGESIZE 4 +-#define FLASHEND 0x7FF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_DWEN (unsigned char)~_BV(6) +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_SELFPRGEN (unsigned char)~_BV(0) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x91 +-#define SIGNATURE_2 0x08 +- +- +-#endif /* _AVR_IOTN25_H_ */ ++/* Copyright (c) 2005, Joerg Wunsch ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn25.h 2115 2010-04-05 23:19:53Z arcanum $ */ ++ ++/* avr/iotn25.h - definitions for ATtiny25 */ ++ ++#ifndef _AVR_IOTN25_H_ ++#define _AVR_IOTN25_H_ 1 ++ ++#include ++ ++#define SPM_PAGESIZE 32 ++#define RAMSTART (0x60) ++#define RAMEND 0xDF ++#define XRAMEND RAMEND ++#define E2END 0x7F ++#define E2PAGESIZE 4 ++#define FLASHEND 0x7FF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x91 ++#define SIGNATURE_2 0x08 ++ ++ ++#endif /* _AVR_IOTN25_H_ */ +diff --git a/include/avr/iotn26.h b/include/avr/iotn26.h +index d348431..069218f 100644 +--- a/include/avr/iotn26.h ++++ b/include/avr/iotn26.h +@@ -1,417 +1,418 @@ +-/* Copyright (c) 2004,2005 Eric B. Weddington +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn26.h 2236 2011-03-17 21:53:39Z arcanum $ */ +- +-/* avr/iotn26.h - definitions for ATtiny26 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn26.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-#ifndef _AVR_IOTN26_H_ +-#define _AVR_IOTN26_H_ 1 +- +-/* Registers and associated bit numbers */ +- +-/* Reserved [0x00..0x03] */ +- +-#define ADCW _SFR_IO16(0x04) +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x04) +-#endif +- +-#define ADCL _SFR_IO8(0x04) +-#define ADCH _SFR_IO8(0x05) +- +-#define ADCSR _SFR_IO8(0x06) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADFR 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADMUX _SFR_IO8(0x07) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define ACSR _SFR_IO8(0x08) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACME 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-/* Reserved [0x09..0x0C] */ +- +-#define USICR _SFR_IO8(0x0D) +-#define USITC 0 +-#define USICLK 1 +-#define USICS0 2 +-#define USICS1 3 +-#define USIWM0 4 +-#define USIWM1 5 +-#define USIOIE 6 +-#define USISIE 7 +- +-#define USISR _SFR_IO8(0x0E) +-#define USICNT0 0 +-#define USICNT1 1 +-#define USICNT2 2 +-#define USICNT3 3 +-#define USIDC 4 +-#define USIPF 5 +-#define USIOIF 6 +-#define USISIF 7 +- +-#define USIDR _SFR_IO8(0x0F) +- +-/* Reserved [0x10..0x15] */ +- +- +-#define PINB _SFR_IO8(0x16) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x17) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x18) +-#define PB0 0 +-#define PB1 1 +-#define PB2 2 +-#define PB3 3 +-#define PB4 4 +-#define PB5 5 +-#define PB6 6 +-#define PB7 7 +- +-#define PINA _SFR_IO8(0x19) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +-#define PINA4 4 +-#define PINA5 5 +-#define PINA6 6 +-#define PINA7 7 +- +-#define DDRA _SFR_IO8(0x1A) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +-#define DDA4 4 +-#define DDA5 5 +-#define DDA6 6 +-#define DDA7 7 +- +-#define PORTA _SFR_IO8(0x1B) +-#define PA0 0 +-#define PA1 1 +-#define PA2 2 +-#define PA3 3 +-#define PA4 4 +-#define PA5 5 +-#define PA6 6 +-#define PA7 7 +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +-#define EERE 0 +-#define EEWE 1 +-#define EEMWE 2 +-#define EERIE 3 +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO8(0x1E) +-#define EEARL _SFR_IO8(0x1E) +- +-/* Reserved [0x1F..0x20] */ +- +-#define WDTCR _SFR_IO8(0x21) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +- +-/* Reserved [0x22..0x28] */ +- +-#define PLLCSR _SFR_IO8(0x29) +-#define PLOCK 0 +-#define PLLE 1 +-#define PCKE 2 +- +-/* Reserved [0x2A] */ +- +-#define OCR1C _SFR_IO8(0x2B) +- +-#define OCR1B _SFR_IO8(0x2C) +- +-#define OCR1A _SFR_IO8(0x2D) +- +-#define TCNT1 _SFR_IO8(0x2E) +- +-#define TCCR1B _SFR_IO8(0x2F) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define CS13 3 +-#define PSR1 6 +-#define CTC1 7 +- +-#define TCCR1A _SFR_IO8(0x30) +-#define PWM1B 0 +-#define PWM1A 1 +-#define FOC1B 2 +-#define FOC1A 3 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define OSCCAL _SFR_IO8(0x31) +- +-#define TCNT0 _SFR_IO8(0x32) +- +-#define TCCR0 _SFR_IO8(0x33) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define PSR0 3 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x35) +-#define ISC00 0 +-#define ISC01 1 +-#define SM0 3 +-#define SM1 4 +-#define SE 5 +-#define PUD 6 +- +-/* Reserved [0x36..0x37] */ +- +-#define TIFR _SFR_IO8(0x38) +-#define TOV0 1 +-#define TOV1 2 +-#define OCF1B 5 +-#define OCF1A 6 +- +-#define TIMSK _SFR_IO8(0x39) +-#define TOIE0 1 +-#define TOIE1 2 +-#define OCIE1B 5 +-#define OCIE1A 6 +- +-#define GIFR _SFR_IO8(0x3A) +-#define PCIF 5 +-#define INTF0 6 +- +-#define GIMSK _SFR_IO8(0x3B) +-#define PCIE0 4 +-#define PCIE1 5 +-#define INT0 6 +- +-/* Reserved [0x3C] */ +- +-/* SP [0x3D] */ +- +-/* Reserved [0x3E] */ +- +-/* SREG [0x3F] */ +- +- +-/* Interrupt vectors */ +-/* Interrupt vector 0 is the reset vector. */ +-/* External Interrupt 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt Request 0 */ +-#define IO_PINS_vect_num 2 +-#define IO_PINS_vect _VECTOR(2) +-#define SIG_PIN_CHANGE _VECTOR(2) +- +-/* Timer/Counter1 Compare Match 1A */ +-#define TIMER1_CMPA_vect_num 3 +-#define TIMER1_CMPA_vect _VECTOR(3) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(3) +- +-/* Timer/Counter1 Compare Match 1B */ +-#define TIMER1_CMPB_vect_num 4 +-#define TIMER1_CMPB_vect _VECTOR(4) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(4) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF1_vect_num 5 +-#define TIMER1_OVF1_vect _VECTOR(5) +-#define SIG_OVERFLOW1 _VECTOR(5) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF0_vect_num 6 +-#define TIMER0_OVF0_vect _VECTOR(6) +-#define SIG_OVERFLOW0 _VECTOR(6) +- +-/* USI Start */ +-#define USI_STRT_vect_num 7 +-#define USI_STRT_vect _VECTOR(7) +-#define SIG_USI_START _VECTOR(7) +- +-/* USI Overflow */ +-#define USI_OVF_vect_num 8 +-#define USI_OVF_vect _VECTOR(8) +-#define SIG_USI_OVERFLOW _VECTOR(8) +- +-/* EEPROM Ready */ +-#define EE_RDY_vect_num 9 +-#define EE_RDY_vect _VECTOR(9) +-#define SIG_EEPROM_READY _VECTOR(9) +- +-/* Analog Comparator */ +-#define ANA_COMP_vect_num 10 +-#define ANA_COMP_vect _VECTOR(10) +-#define SIG_ANA_COMP _VECTOR(10) +-#define SIG_COMPARATOR _VECTOR(10) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 11 +-#define ADC_vect _VECTOR(11) +-#define SIG_ADC _VECTOR(11) +- +-#define _VECTORS_SIZE 24 +- +- +-/* Constants */ +-#define RAMEND 0xDF +-#define XRAMEND RAMEND +-#define E2END 0x7F +-#define E2PAGESIZE 4 +-#define FLASHEND 0x07FF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 2 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOPT (unsigned char)~_BV(6) +-#define FUSE_PLLCK (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) +- +-/* High Fuse Byte */ +-#define FUSE_BODEN (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL (unsigned char)~_BV(1) +-#define FUSE_EESAVE (unsigned char)~_BV(2) +-#define FUSE_SPIEN (unsigned char)~_BV(3) +-#define FUSE_RSTDISBL (unsigned char)~_BV(4) +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x91 +-#define SIGNATURE_2 0x09 +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_PIN_CHANGE +-#pragma GCC poison SIG_OUTPUT_COMPARE1A +-#pragma GCC poison SIG_OUTPUT_COMPARE1B +-#pragma GCC poison SIG_OVERFLOW1 +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_USI_START +-#pragma GCC poison SIG_USI_OVERFLOW +-#pragma GCC poison SIG_EEPROM_READY +-#pragma GCC poison SIG_ANA_COMP +-#pragma GCC poison SIG_COMPARATOR +-#pragma GCC poison SIG_ADC +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +-#endif /* _AVR_IOTN26_H_ */ ++/* Copyright (c) 2004,2005 Eric B. Weddington ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn26.h 2236 2011-03-17 21:53:39Z arcanum $ */ ++ ++/* avr/iotn26.h - definitions for ATtiny26 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn26.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_IOTN26_H_ ++#define _AVR_IOTN26_H_ 1 ++ ++/* Registers and associated bit numbers */ ++ ++/* Reserved [0x00..0x03] */ ++ ++#define ADCW _SFR_IO16(0x04) ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++ ++#define ADCL _SFR_IO8(0x04) ++#define ADCH _SFR_IO8(0x05) ++ ++#define ADCSR _SFR_IO8(0x06) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADFR 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADMUX _SFR_IO8(0x07) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define ACSR _SFR_IO8(0x08) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACME 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++/* Reserved [0x09..0x0C] */ ++ ++#define USICR _SFR_IO8(0x0D) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_IO8(0x0E) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_IO8(0x0F) ++ ++/* Reserved [0x10..0x15] */ ++ ++ ++#define PINB _SFR_IO8(0x16) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x17) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x18) ++#define PB0 0 ++#define PB1 1 ++#define PB2 2 ++#define PB3 3 ++#define PB4 4 ++#define PB5 5 ++#define PB6 6 ++#define PB7 7 ++ ++#define PINA _SFR_IO8(0x19) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++#define PINA4 4 ++#define PINA5 5 ++#define PINA6 6 ++#define PINA7 7 ++ ++#define DDRA _SFR_IO8(0x1A) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++#define DDA4 4 ++#define DDA5 5 ++#define DDA6 6 ++#define DDA7 7 ++ ++#define PORTA _SFR_IO8(0x1B) ++#define PA0 0 ++#define PA1 1 ++#define PA2 2 ++#define PA3 3 ++#define PA4 4 ++#define PA5 5 ++#define PA6 6 ++#define PA7 7 ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++#define EERE 0 ++#define EEWE 1 ++#define EEMWE 2 ++#define EERIE 3 ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO8(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++ ++/* Reserved [0x1F..0x20] */ ++ ++#define WDTCR _SFR_IO8(0x21) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++ ++/* Reserved [0x22..0x28] */ ++ ++#define PLLCSR _SFR_IO8(0x29) ++#define PLOCK 0 ++#define PLLE 1 ++#define PCKE 2 ++ ++/* Reserved [0x2A] */ ++ ++#define OCR1C _SFR_IO8(0x2B) ++ ++#define OCR1B _SFR_IO8(0x2C) ++ ++#define OCR1A _SFR_IO8(0x2D) ++ ++#define TCNT1 _SFR_IO8(0x2E) ++ ++#define TCCR1B _SFR_IO8(0x2F) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define CS13 3 ++#define PSR1 6 ++#define CTC1 7 ++ ++#define TCCR1A _SFR_IO8(0x30) ++#define PWM1B 0 ++#define PWM1A 1 ++#define FOC1B 2 ++#define FOC1A 3 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define OSCCAL _SFR_IO8(0x31) ++ ++#define TCNT0 _SFR_IO8(0x32) ++ ++#define TCCR0 _SFR_IO8(0x33) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define PSR0 3 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define ISC00 0 ++#define ISC01 1 ++#define SM0 3 ++#define SM1 4 ++#define SE 5 ++#define PUD 6 ++ ++/* Reserved [0x36..0x37] */ ++ ++#define TIFR _SFR_IO8(0x38) ++#define TOV0 1 ++#define TOV1 2 ++#define OCF1B 5 ++#define OCF1A 6 ++ ++#define TIMSK _SFR_IO8(0x39) ++#define TOIE0 1 ++#define TOIE1 2 ++#define OCIE1B 5 ++#define OCIE1A 6 ++ ++#define GIFR _SFR_IO8(0x3A) ++#define PCIF 5 ++#define INTF0 6 ++ ++#define GIMSK _SFR_IO8(0x3B) ++#define PCIE0 4 ++#define PCIE1 5 ++#define INT0 6 ++ ++/* Reserved [0x3C] */ ++ ++/* SP [0x3D] */ ++ ++/* Reserved [0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++ ++/* Interrupt vectors */ ++/* Interrupt vector 0 is the reset vector. */ ++/* External Interrupt 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt Request 0 */ ++#define IO_PINS_vect_num 2 ++#define IO_PINS_vect _VECTOR(2) ++#define SIG_PIN_CHANGE _VECTOR(2) ++ ++/* Timer/Counter1 Compare Match 1A */ ++#define TIMER1_CMPA_vect_num 3 ++#define TIMER1_CMPA_vect _VECTOR(3) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(3) ++ ++/* Timer/Counter1 Compare Match 1B */ ++#define TIMER1_CMPB_vect_num 4 ++#define TIMER1_CMPB_vect _VECTOR(4) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(4) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF1_vect_num 5 ++#define TIMER1_OVF1_vect _VECTOR(5) ++#define SIG_OVERFLOW1 _VECTOR(5) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF0_vect_num 6 ++#define TIMER0_OVF0_vect _VECTOR(6) ++#define SIG_OVERFLOW0 _VECTOR(6) ++ ++/* USI Start */ ++#define USI_STRT_vect_num 7 ++#define USI_STRT_vect _VECTOR(7) ++#define SIG_USI_START _VECTOR(7) ++ ++/* USI Overflow */ ++#define USI_OVF_vect_num 8 ++#define USI_OVF_vect _VECTOR(8) ++#define SIG_USI_OVERFLOW _VECTOR(8) ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect_num 9 ++#define EE_RDY_vect _VECTOR(9) ++#define SIG_EEPROM_READY _VECTOR(9) ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect_num 10 ++#define ANA_COMP_vect _VECTOR(10) ++#define SIG_ANA_COMP _VECTOR(10) ++#define SIG_COMPARATOR _VECTOR(10) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 11 ++#define ADC_vect _VECTOR(11) ++#define SIG_ADC _VECTOR(11) ++ ++#define _VECTORS_SIZE 24 ++ ++ ++/* Constants */ ++#define RAMSTART 0x60 ++#define RAMEND 0xDF ++#define XRAMEND RAMEND ++#define E2END 0x7F ++#define E2PAGESIZE 4 ++#define FLASHEND 0x07FF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 2 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOPT (unsigned char)~_BV(6) ++#define FUSE_PLLCK (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0) ++ ++/* High Fuse Byte */ ++#define FUSE_BODEN (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL (unsigned char)~_BV(1) ++#define FUSE_EESAVE (unsigned char)~_BV(2) ++#define FUSE_SPIEN (unsigned char)~_BV(3) ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x91 ++#define SIGNATURE_2 0x09 ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_PIN_CHANGE ++#pragma GCC poison SIG_OUTPUT_COMPARE1A ++#pragma GCC poison SIG_OUTPUT_COMPARE1B ++#pragma GCC poison SIG_OVERFLOW1 ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_USI_START ++#pragma GCC poison SIG_USI_OVERFLOW ++#pragma GCC poison SIG_EEPROM_READY ++#pragma GCC poison SIG_ANA_COMP ++#pragma GCC poison SIG_COMPARATOR ++#pragma GCC poison SIG_ADC ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++#endif /* _AVR_IOTN26_H_ */ +diff --git a/include/avr/iotn261.h b/include/avr/iotn261.h +index c19ef39..b6e8a4c 100644 +--- a/include/avr/iotn261.h ++++ b/include/avr/iotn261.h +@@ -1,89 +1,89 @@ +-/* Copyright (c) 2006, Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn261.h 2115 2010-04-05 23:19:53Z arcanum $ */ +- +-/* avr/iotn261.h - definitions for ATtiny261 */ +- +-#ifndef _AVR_IOTN261_H_ +-#define _AVR_IOTN261_H_ 1 +- +-#include +- +-#define SPM_PAGESIZE 32 +-#define RAMSTART (0x60) +-#define RAMEND 0xDF +-#define XRAMEND RAMEND +-#define E2END 0x7F +-#define E2PAGESIZE 4 +-#define FLASHEND 0x7FF +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_DWEN (unsigned char)~_BV(6) +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_SELFPRGEN (unsigned char)~_BV(0) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x91 +-#define SIGNATURE_2 0x0C +- +- +-#endif /* _AVR_IOTN261_H_ */ ++/* Copyright (c) 2006, Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn261.h 2115 2010-04-05 23:19:53Z arcanum $ */ ++ ++/* avr/iotn261.h - definitions for ATtiny261 */ ++ ++#ifndef _AVR_IOTN261_H_ ++#define _AVR_IOTN261_H_ 1 ++ ++#include ++ ++#define SPM_PAGESIZE 32 ++#define RAMSTART (0x60) ++#define RAMEND 0xDF ++#define XRAMEND RAMEND ++#define E2END 0x7F ++#define E2PAGESIZE 4 ++#define FLASHEND 0x7FF ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x91 ++#define SIGNATURE_2 0x0C ++ ++ ++#endif /* _AVR_IOTN261_H_ */ +diff --git a/include/avr/iotn261a.h b/include/avr/iotn261a.h +index 2246264..9805519 100644 +--- a/include/avr/iotn261a.h ++++ b/include/avr/iotn261a.h +@@ -1,976 +1,976 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn261a.h 2063 2009-11-18 22:06:28Z arcanum $ */ +- +-/* avr/iotn261a.h - definitions for ATtiny261A */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn261a.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATtiny261A_H_ +-#define _AVR_ATtiny261A_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define TCCR1E _SFR_IO8(0x00) +-#define OC1OE0 0 +-#define OC1OE1 1 +-#define OC1OE2 2 +-#define OC1OE3 3 +-#define OC1OE4 4 +-#define OC1OE5 5 +- +-#define DIDR0 _SFR_IO8(0x01) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define AREFD 3 +-#define ADC3D 4 +-#define ADC4D 5 +-#define ADC5D 6 +-#define ADC6D 7 +- +-#define DIDR1 _SFR_IO8(0x02) +-#define ADC7D 4 +-#define ADC8D 5 +-#define ADC9D 6 +-#define ADC10D 7 +- +-#define ADCSRB _SFR_IO8(0x03) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define MUX5 3 +-#define REFS2 4 +-#define IPR 5 +-#define GSEL 6 +-#define BIN 7 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x04) +-#endif +-#define ADCW _SFR_IO16(0x04) +- +-#define ADCL _SFR_IO8(0x04) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_IO8(0x05) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_IO8(0x06) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADMUX _SFR_IO8(0x07) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define ACSRA _SFR_IO8(0x08) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACME 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define ACSRB _SFR_IO8(0x09) +-#define ACM0 0 +-#define ACM1 1 +-#define ACM2 2 +-#define HLEV 6 +-#define HSEL 7 +- +-#define GPIOR0 _SFR_IO8(0x0A) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define GPIOR1 _SFR_IO8(0x0B) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x0C) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define USICR _SFR_IO8(0x0D) +-#define USITC 0 +-#define USICLK 1 +-#define USICS0 2 +-#define USICS1 3 +-#define USIWM0 4 +-#define USIWM1 5 +-#define USIOIE 6 +-#define USISIE 7 +- +-#define USISR _SFR_IO8(0x0E) +-#define USICNT0 0 +-#define USICNT1 1 +-#define USICNT2 2 +-#define USICNT3 3 +-#define USIDC 4 +-#define USIPF 5 +-#define USIOIF 6 +-#define USISIF 7 +- +-#define USIDR _SFR_IO8(0x0F) +-#define USIDR0 0 +-#define USIDR1 1 +-#define USIDR2 2 +-#define USIDR3 3 +-#define USIDR4 4 +-#define USIDR5 5 +-#define USIDR6 6 +-#define USIDR7 7 +- +-#define USIBR _SFR_IO8(0x10) +-#define USIBR0 0 +-#define USIBR1 1 +-#define USIBR2 2 +-#define USIBR3 3 +-#define USIBR4 4 +-#define USIBR5 5 +-#define USIBR6 6 +-#define USIBR7 7 +- +-#define USIPP _SFR_IO8(0x11) +-#define USIPOS 0 +- +-#define OCR0B _SFR_IO8(0x12) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define OCR0A _SFR_IO8(0x13) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define TCNT0H _SFR_IO8(0x14) +-#define TCNT0H_0 0 +-#define TCNT0H_1 1 +-#define TCNT0H_2 2 +-#define TCNT0H_3 3 +-#define TCNT0H_4 4 +-#define TCNT0H_5 5 +-#define TCNT0H_6 6 +-#define TCNT0H_7 7 +- +-#define TCCR0A _SFR_IO8(0x15) +-#define WGM00 0 +-#define ACIC0 3 +-#define ICES0 4 +-#define ICNC0 5 +-#define ICEN0 6 +-#define TCW0 7 +- +-#define PINB _SFR_IO8(0x16) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x17) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x18) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINA _SFR_IO8(0x19) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +-#define PINA4 4 +-#define PINA5 5 +-#define PINA6 6 +-#define PINA7 7 +- +-#define DDRA _SFR_IO8(0x1A) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +-#define DDA4 4 +-#define DDA5 5 +-#define DDA6 6 +-#define DDA7 7 +- +-#define PORTA _SFR_IO8(0x1B) +-#define PORTA0 0 +-#define PORTA1 1 +-#define PORTA2 2 +-#define PORTA3 3 +-#define PORTA4 4 +-#define PORTA5 5 +-#define PORTA6 6 +-#define PORTA7 7 +- +-#define EECR _SFR_IO8(0x1C) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x1D) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x1E) +- +-#define EEARL _SFR_IO8(0x1E) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x1F) +-#define EEAR8 0 +- +-#define DWDR _SFR_IO8(0x20) +-#define DWDR0 0 +-#define DWDR1 1 +-#define DWDR2 2 +-#define DWDR3 3 +-#define DWDR4 4 +-#define DWDR5 5 +-#define DWDR6 6 +-#define DWDR7 7 +- +-#define WDTCR _SFR_IO8(0x21) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define PCMSK1 _SFR_IO8(0x22) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-#define PCMSK0 _SFR_IO8(0x23) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define DT1 _SFR_IO8(0x24) +-#define DT1L0 0 +-#define DT1L1 1 +-#define DT1L2 2 +-#define DT1L3 3 +-#define DT1H0 4 +-#define DT1H1 5 +-#define DT1H2 6 +-#define DT1H3 7 +- +-#define TC1H _SFR_IO8(0x25) +-#define TC18 0 +-#define TC19 1 +- +-#define TCCR1D _SFR_IO8(0x26) +-#define WGM10 0 +-#define WGM11 1 +-#define FPF1 2 +-#define FPAC1 3 +-#define FPES1 4 +-#define FPNC1 5 +-#define FPEN1 6 +-#define FPIE1 7 +- +-#define TCCR1C _SFR_IO8(0x27) +-#define PWM1D 0 +-#define FOC1D 1 +-#define COM1D0 2 +-#define COM1D1 3 +-#define COM1B0S 4 +-#define COM1B1S 5 +-#define COM1A0S 6 +-#define COM1A1S 7 +- +-#define CLKPR _SFR_IO8(0x28) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define PLLCSR _SFR_IO8(0x29) +-#define PLOCK 0 +-#define PLLE 1 +-#define PCKE 2 +-#define LSM 7 +- +-#define OCR1D _SFR_IO8(0x2A) +-#define OCR1D0 0 +-#define OCR1D1 1 +-#define OCR1D2 2 +-#define OCR1D3 3 +-#define OCR1D4 4 +-#define OCR1D5 5 +-#define OCR1D6 6 +-#define OCR1D7 7 +- +-#define OCR1C _SFR_IO8(0x2B) +-#define OCR1C0 0 +-#define OCR1C1 1 +-#define OCR1C2 2 +-#define OCR1C3 3 +-#define OCR1C4 4 +-#define OCR1C5 5 +-#define OCR1C6 6 +-#define OCR1C7 7 +- +-#define OCR1B _SFR_IO8(0x2C) +-#define OCR1B0 0 +-#define OCR1B1 1 +-#define OCR1B2 2 +-#define OCR1B3 3 +-#define OCR1B4 4 +-#define OCR1B5 5 +-#define OCR1B6 6 +-#define OCR1B7 7 +- +-#define OCR1A _SFR_IO8(0x2D) +-#define OCR1A0 0 +-#define OCR1A1 1 +-#define OCR1A2 2 +-#define OCR1A3 3 +-#define OCR1A4 4 +-#define OCR1A5 5 +-#define OCR1A6 6 +-#define OCR1A7 7 +- +-#define TCNT1 _SFR_IO8(0x2E) +-#define TC1H_0 0 +-#define TC1H_1 1 +-#define TC1H_2 2 +-#define TC1H_3 3 +-#define TC1H_4 4 +-#define TC1H_5 5 +-#define TC1H_6 6 +-#define TC1H_7 7 +- +-#define TCCR1B _SFR_IO8(0x2F) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define CS13 3 +-#define DTPS10 4 +-#define DTPS11 5 +-#define PSR1 6 +- +-#define TCCR1A _SFR_IO8(0x30) +-#define PWM1B 0 +-#define PWM1A 1 +-#define FOC1B 2 +-#define FOC1A 3 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define OSCCAL _SFR_IO8(0x31) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define TCNT0L _SFR_IO8(0x32) +-#define TCNT0L_0 0 +-#define TCNT0L_1 1 +-#define TCNT0L_2 2 +-#define TCNT0L_3 3 +-#define TCNT0L_4 4 +-#define TCNT0L_5 5 +-#define TCNT0L_6 6 +-#define TCNT0L_7 7 +- +-#define TCCR0B _SFR_IO8(0x33) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define PSR0 3 +-#define TSM 4 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x35) +-#define ISC00 0 +-#define ISC01 1 +-#define BODSE 2 +-#define SM0 3 +-#define SM1 4 +-#define SE 5 +-#define PUD 6 +-#define BODS 7 +- +-#define PRR _SFR_IO8(0x36) +-#define PRADC 0 +-#define PRUSI 1 +-#define PRTIM0 2 +-#define PRTIM1 3 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define RFLB 3 +-#define CTPB 4 +- +-#define TIFR _SFR_IO8(0x38) +-#define ICF0 0 +-#define TOV0 1 +-#define TOV1 2 +-#define OCF0B 3 +-#define OCF0A 4 +-#define OCF1B 5 +-#define OCF1A 6 +-#define OCF1D 7 +- +-#define TIMSK _SFR_IO8(0x39) +-#define TICIE0 0 +-#define TOIE0 1 +-#define TOIE1 2 +-#define OCIE0B 3 +-#define OCIE0A 4 +-#define OCIE1B 5 +-#define OCIE1A 6 +-#define OCIE1D 7 +- +-#define GIFR _SFR_IO8(0x3A) +-#define PCIF 5 +-#define INTF0 6 +-#define INTF1 7 +- +-#define GIMSK _SFR_IO8(0x3B) +-#define PCIE0 4 +-#define PCIE1 5 +-#define INT0 6 +-#define INT1 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt 0 */ +-#define PCINT_vect_num 2 +-#define PCINT_vect _VECTOR(2) /* Pin Change Interrupt */ +-#define TIMER1_COMPA_vect_num 3 +-#define TIMER1_COMPA_vect _VECTOR(3) /* Timer/Counter1 Compare Match 1A */ +-#define TIMER1_COMPB_vect_num 4 +-#define TIMER1_COMPB_vect _VECTOR(4) /* Timer/Counter1 Compare Match 1B */ +-#define TIMER1_OVF_vect_num 5 +-#define TIMER1_OVF_vect _VECTOR(5) /* Timer/Counter1 Overflow */ +-#define TIMER0_OVF_vect_num 6 +-#define TIMER0_OVF_vect _VECTOR(6) /* Timer/Counter0 Overflow */ +-#define USI_START_vect_num 7 +-#define USI_START_vect _VECTOR(7) /* USI Start */ +-#define USI_OVF_vect_num 8 +-#define USI_OVF_vect _VECTOR(8) /* USI Overflow */ +-#define EE_RDY_vect_num 9 +-#define EE_RDY_vect _VECTOR(9) /* EEPROM Ready */ +-#define ANA_COMP_vect_num 10 +-#define ANA_COMP_vect _VECTOR(10) /* Analog Comparator */ +-#define ADC_vect_num 11 +-#define ADC_vect _VECTOR(11) /* ADC Conversion Complete */ +-#define WDT_vect_num 12 +-#define WDT_vect _VECTOR(12) /* Watchdog Time-Out */ +-#define INT1_vect_num 13 +-#define INT1_vect _VECTOR(13) /* External Interrupt 1 */ +-#define TIMER0_COMPA_vect_num 14 +-#define TIMER0_COMPA_vect _VECTOR(14) /* Timer/Counter0 Compare Match A */ +-#define TIMER0_COMPB_vect_num 15 +-#define TIMER0_COMPB_vect _VECTOR(15) /* Timer/Counter0 Compare Match B */ +-#define TIMER0_CAPT_vect_num 16 +-#define TIMER0_CAPT_vect _VECTOR(16) /* ADC Conversion Complete */ +-#define TIMER1_COMPD_vect_num 17 +-#define TIMER1_COMPD_vect _VECTOR(17) /* Timer/Counter1 Compare Match D */ +-#define FAULT_PROTECTION_vect_num 18 +-#define FAULT_PROTECTION_vect _VECTOR(18) /* Timer/Counter1 Fault Protection */ +- +-#define _VECTOR_SIZE 2 /* Size of individual vector. */ +-#define _VECTORS_SIZE (19 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (32) +-#define RAMSTART (0x60) +-#define RAMSIZE (128) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x7F) +-#define E2PAGESIZE (4) +-#define FLASHEND (0x7FF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x91 +-#define SIGNATURE_2 0x0C +- +- +-/* Device Pin Definitions */ +-#define DI_B_DDR DDRMOSI +-#define DI_B_PORT PORTMOSI +-#define DI_B_PIN PINMOSI +-#define DI_B_BIT MOSI +- +-#define SDA_B_DDR DDRMOSI +-#define SDA_B_PORT PORTMOSI +-#define SDA_B_PIN PINMOSI +-#define SDA_B_BIT MOSI +- +-#define _OC1A_DDR DDRMOSI +-#define _OC1A_PORT PORTMOSI +-#define _OC1A_PIN PINMOSI +-#define _OC1A_BIT MOSI +- +-#define PCINT8_DDR DDRMOSI +-#define PCINT8_PORT PORTMOSI +-#define PCINT8_PIN PINMOSI +-#define PCINT8_BIT MOSI +- +-#define PB0_DDR DDRMOSI +-#define PB0_PORT PORTMOSI +-#define PB0_PIN PINMOSI +-#define PB0_BIT MOSI +- +-#define DO_B_DDR DDRMISO +-#define DO_B_PORT PORTMISO +-#define DO_B_PIN PINMISO +-#define DO_B_BIT MISO +- +-#define OC1A_DDR DDRMISO +-#define OC1A_PORT PORTMISO +-#define OC1A_PIN PINMISO +-#define OC1A_BIT MISO +- +-#define PCINT9_DDR DDRMISO +-#define PCINT9_PORT PORTMISO +-#define PCINT9_PIN PINMISO +-#define PCINT9_BIT MISO +- +-#define PB1_DDR DDRMISO +-#define PB1_PORT PORTMISO +-#define PB1_PIN PINMISO +-#define PB1_BIT MISO +- +-#define USCK_B_DDR DDRSCK +-#define USCK_B_PORT PORTSCK +-#define USCK_B_PIN PINSCK +-#define USCK_B_BIT SCK +- +-#define SCL_B_DDR DDRSCK +-#define SCL_B_PORT PORTSCK +-#define SCL_B_PIN PINSCK +-#define SCL_B_BIT SCK +- +-#define OC1B_DDR DDRSCK +-#define OC1B_PORT PORTSCK +-#define OC1B_PIN PINSCK +-#define OC1B_BIT SCK +- +-#define PCINT10_DDR DDRSCK +-#define PCINT10_PORT PORTSCK +-#define PCINT10_PIN PINSCK +-#define PCINT10_BIT SCK +- +-#define PB2_DDR DDRSCK +-#define PB2_PORT PORTSCK +-#define PB2_PIN PINSCK +-#define PB2_BIT SCK +- +-#define PCINT11_DDR DDROC1B +-#define PCINT11_PORT PORTOC1B +-#define PCINT11_PIN PINOC1B +-#define PCINT11_BIT OC1B +- +-#define PB3_DDR DDROC1B +-#define PB3_PORT PORTOC1B +-#define PB3_PIN PINOC1B +-#define PB3_BIT OC1B +- +-#define PCINT12_DDR DDRADC +-#define PCINT12_PORT PORTADC +-#define PCINT12_PIN PINADC +-#define PCINT12_BIT ADC7 +- +-#define _OC1D_DDR DDRADC +-#define _OC1D_PORT PORTADC +-#define _OC1D_PIN PINADC +-#define _OC1D_BIT ADC7 +- +-#define CLKI_DDR DDRADC +-#define CLKI_PORT PORTADC +-#define CLKI_PIN PINADC +-#define CLKI_BIT ADC7 +- +-#define PB4_DDR DDRADC +-#define PB4_PORT PORTADC +-#define PB4_PIN PINADC +-#define PB4_BIT ADC7 +- +-#define PCINT13_DDR DDRADC +-#define PCINT13_PORT PORTADC +-#define PCINT13_PIN PINADC +-#define PCINT13_BIT ADC8 +- +-#define OC1D_DDR DDRADC +-#define OC1D_PORT PORTADC +-#define OC1D_PIN PINADC +-#define OC1D_BIT ADC8 +- +-#define CKLO_DDR DDRADC +-#define CKLO_PORT PORTADC +-#define CKLO_PIN PINADC +-#define CKLO_BIT ADC8 +- +-#define PB5_DDR DDRADC +-#define PB5_PORT PORTADC +-#define PB5_PIN PINADC +-#define PB5_BIT ADC8 +- +-#define INT0_DDR DDRADC +-#define INT0_PORT PORTADC +-#define INT0_PIN PINADC +-#define INT0_BIT ADC9 +- +-#define T0_DDR DDRADC +-#define T0_PORT PORTADC +-#define T0_PIN PINADC +-#define T0_BIT ADC9 +- +-#define PCINT14_DDR DDRADC +-#define PCINT14_PORT PORTADC +-#define PCINT14_PIN PINADC +-#define PCINT14_BIT ADC9 +- +-#define PB6_DDR DDRADC +-#define PB6_PORT PORTADC +-#define PB6_PIN PINADC +-#define PB6_BIT ADC9 +- +-#define PCINT15_DDR DDRADC1 +-#define PCINT15_PORT PORTADC1 +-#define PCINT15_PIN PINADC1 +-#define PCINT15_BIT ADC10 +- +-#define PB7_DDR DDRADC1 +-#define PB7_PORT PORTADC1 +-#define PB7_PIN PINADC1 +-#define PB7_BIT ADC10 +- +-#define AIN1_DDR DDRADC +-#define AIN1_PORT PORTADC +-#define AIN1_PIN PINADC +-#define AIN1_BIT ADC6 +- +-#define PCINT7_DDR DDRADC +-#define PCINT7_PORT PORTADC +-#define PCINT7_PIN PINADC +-#define PCINT7_BIT ADC6 +- +-#define PA7_DDR DDRADC +-#define PA7_PORT PORTADC +-#define PA7_PIN PINADC +-#define PA7_BIT ADC6 +- +-#define AIN0_DDR DDRADC +-#define AIN0_PORT PORTADC +-#define AIN0_PIN PINADC +-#define AIN0_BIT ADC5 +- +-#define PCINT6_DDR DDRADC +-#define PCINT6_PORT PORTADC +-#define PCINT6_PIN PINADC +-#define PCINT6_BIT ADC5 +- +-#define PA6_DDR DDRADC +-#define PA6_PORT PORTADC +-#define PA6_PIN PINADC +-#define PA6_BIT ADC5 +- +-#define AIN2_DDR DDRADC +-#define AIN2_PORT PORTADC +-#define AIN2_PIN PINADC +-#define AIN2_BIT ADC4 +- +-#define PCINT5_DDR DDRADC +-#define PCINT5_PORT PORTADC +-#define PCINT5_PIN PINADC +-#define PCINT5_BIT ADC4 +- +-#define PA5_DDR DDRADC +-#define PA5_PORT PORTADC +-#define PA5_PIN PINADC +-#define PA5_BIT ADC4 +- +-#define ICP0_DDR DDRADC +-#define ICP0_PORT PORTADC +-#define ICP0_PIN PINADC +-#define ICP0_BIT ADC3 +- +-#define PCINT4_DDR DDRADC +-#define PCINT4_PORT PORTADC +-#define PCINT4_PIN PINADC +-#define PCINT4_BIT ADC3 +- +-#define PA4_DDR DDRADC +-#define PA4_PORT PORTADC +-#define PA4_PIN PINADC +-#define PA4_BIT ADC3 +- +-#define PCINT3_DDR DDRAREF +-#define PCINT3_PORT PORTAREF +-#define PCINT3_PIN PINAREF +-#define PCINT3_BIT AREF +- +-#define PA3_DDR DDRAREF +-#define PA3_PORT PORTAREF +-#define PA3_PIN PINAREF +-#define PA3_BIT AREF +- +-#define INT1_DDR DDRADC +-#define INT1_PORT PORTADC +-#define INT1_PIN PINADC +-#define INT1_BIT ADC2 +- +-#define USCK_A_DDR DDRADC +-#define USCK_A_PORT PORTADC +-#define USCK_A_PIN PINADC +-#define USCK_A_BIT ADC2 +- +-#define SCL_A_DDR DDRADC +-#define SCL_A_PORT PORTADC +-#define SCL_A_PIN PINADC +-#define SCL_A_BIT ADC2 +- +-#define PCINT2_DDR DDRADC +-#define PCINT2_PORT PORTADC +-#define PCINT2_PIN PINADC +-#define PCINT2_BIT ADC2 +- +-#define PA2_DDR DDRADC +-#define PA2_PORT PORTADC +-#define PA2_PIN PINADC +-#define PA2_BIT ADC2 +- +-#define DO_A_DDR DDRADC +-#define DO_A_PORT PORTADC +-#define DO_A_PIN PINADC +-#define DO_A_BIT ADC1 +- +-#define PCINT1_DDR DDRADC +-#define PCINT1_PORT PORTADC +-#define PCINT1_PIN PINADC +-#define PCINT1_BIT ADC1 +- +-#define PA1_DDR DDRADC +-#define PA1_PORT PORTADC +-#define PA1_PIN PINADC +-#define PA1_BIT ADC1 +- +-#define DI_A_DDR DDRADC +-#define DI_A_PORT PORTADC +-#define DI_A_PIN PINADC +-#define DI_A_BIT ADC0 +- +-#define SDA_A_DDR DDRADC +-#define SDA_A_PORT PORTADC +-#define SDA_A_PIN PINADC +-#define SDA_A_BIT ADC0 +- +-#define PCINT0_DDR DDRADC +-#define PCINT0_PORT PORTADC +-#define PCINT0_PIN PINADC +-#define PCINT0_BIT ADC0 +- +-#define PA0_DDR DDRADC +-#define PA0_PORT PORTADC +-#define PA0_PIN PINADC +-#define PA0_BIT ADC0 +- +-#endif /* _AVR_ATtiny261A_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn261a.h 2063 2009-11-18 22:06:28Z arcanum $ */ ++ ++/* avr/iotn261a.h - definitions for ATtiny261A */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn261a.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATtiny261A_H_ ++#define _AVR_ATtiny261A_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define TCCR1E _SFR_IO8(0x00) ++#define OC1OE0 0 ++#define OC1OE1 1 ++#define OC1OE2 2 ++#define OC1OE3 3 ++#define OC1OE4 4 ++#define OC1OE5 5 ++ ++#define DIDR0 _SFR_IO8(0x01) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define AREFD 3 ++#define ADC3D 4 ++#define ADC4D 5 ++#define ADC5D 6 ++#define ADC6D 7 ++ ++#define DIDR1 _SFR_IO8(0x02) ++#define ADC7D 4 ++#define ADC8D 5 ++#define ADC9D 6 ++#define ADC10D 7 ++ ++#define ADCSRB _SFR_IO8(0x03) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define MUX5 3 ++#define REFS2 4 ++#define IPR 5 ++#define GSEL 6 ++#define BIN 7 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCW _SFR_IO16(0x04) ++ ++#define ADCL _SFR_IO8(0x04) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_IO8(0x05) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_IO8(0x06) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADMUX _SFR_IO8(0x07) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define ACSRA _SFR_IO8(0x08) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACME 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define ACSRB _SFR_IO8(0x09) ++#define ACM0 0 ++#define ACM1 1 ++#define ACM2 2 ++#define HLEV 6 ++#define HSEL 7 ++ ++#define GPIOR0 _SFR_IO8(0x0A) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define GPIOR1 _SFR_IO8(0x0B) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x0C) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define USICR _SFR_IO8(0x0D) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_IO8(0x0E) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_IO8(0x0F) ++#define USIDR0 0 ++#define USIDR1 1 ++#define USIDR2 2 ++#define USIDR3 3 ++#define USIDR4 4 ++#define USIDR5 5 ++#define USIDR6 6 ++#define USIDR7 7 ++ ++#define USIBR _SFR_IO8(0x10) ++#define USIBR0 0 ++#define USIBR1 1 ++#define USIBR2 2 ++#define USIBR3 3 ++#define USIBR4 4 ++#define USIBR5 5 ++#define USIBR6 6 ++#define USIBR7 7 ++ ++#define USIPP _SFR_IO8(0x11) ++#define USIPOS 0 ++ ++#define OCR0B _SFR_IO8(0x12) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define OCR0A _SFR_IO8(0x13) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define TCNT0H _SFR_IO8(0x14) ++#define TCNT0H_0 0 ++#define TCNT0H_1 1 ++#define TCNT0H_2 2 ++#define TCNT0H_3 3 ++#define TCNT0H_4 4 ++#define TCNT0H_5 5 ++#define TCNT0H_6 6 ++#define TCNT0H_7 7 ++ ++#define TCCR0A _SFR_IO8(0x15) ++#define WGM00 0 ++#define ACIC0 3 ++#define ICES0 4 ++#define ICNC0 5 ++#define ICEN0 6 ++#define TCW0 7 ++ ++#define PINB _SFR_IO8(0x16) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x17) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x18) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINA _SFR_IO8(0x19) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++#define PINA4 4 ++#define PINA5 5 ++#define PINA6 6 ++#define PINA7 7 ++ ++#define DDRA _SFR_IO8(0x1A) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++#define DDA4 4 ++#define DDA5 5 ++#define DDA6 6 ++#define DDA7 7 ++ ++#define PORTA _SFR_IO8(0x1B) ++#define PORTA0 0 ++#define PORTA1 1 ++#define PORTA2 2 ++#define PORTA3 3 ++#define PORTA4 4 ++#define PORTA5 5 ++#define PORTA6 6 ++#define PORTA7 7 ++ ++#define EECR _SFR_IO8(0x1C) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x1D) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x1E) ++ ++#define EEARL _SFR_IO8(0x1E) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x1F) ++#define EEAR8 0 ++ ++#define DWDR _SFR_IO8(0x20) ++#define DWDR0 0 ++#define DWDR1 1 ++#define DWDR2 2 ++#define DWDR3 3 ++#define DWDR4 4 ++#define DWDR5 5 ++#define DWDR6 6 ++#define DWDR7 7 ++ ++#define WDTCR _SFR_IO8(0x21) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define PCMSK1 _SFR_IO8(0x22) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK0 _SFR_IO8(0x23) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define DT1 _SFR_IO8(0x24) ++#define DT1L0 0 ++#define DT1L1 1 ++#define DT1L2 2 ++#define DT1L3 3 ++#define DT1H0 4 ++#define DT1H1 5 ++#define DT1H2 6 ++#define DT1H3 7 ++ ++#define TC1H _SFR_IO8(0x25) ++#define TC18 0 ++#define TC19 1 ++ ++#define TCCR1D _SFR_IO8(0x26) ++#define WGM10 0 ++#define WGM11 1 ++#define FPF1 2 ++#define FPAC1 3 ++#define FPES1 4 ++#define FPNC1 5 ++#define FPEN1 6 ++#define FPIE1 7 ++ ++#define TCCR1C _SFR_IO8(0x27) ++#define PWM1D 0 ++#define FOC1D 1 ++#define COM1D0 2 ++#define COM1D1 3 ++#define COM1B0S 4 ++#define COM1B1S 5 ++#define COM1A0S 6 ++#define COM1A1S 7 ++ ++#define CLKPR _SFR_IO8(0x28) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define PLLCSR _SFR_IO8(0x29) ++#define PLOCK 0 ++#define PLLE 1 ++#define PCKE 2 ++#define LSM 7 ++ ++#define OCR1D _SFR_IO8(0x2A) ++#define OCR1D0 0 ++#define OCR1D1 1 ++#define OCR1D2 2 ++#define OCR1D3 3 ++#define OCR1D4 4 ++#define OCR1D5 5 ++#define OCR1D6 6 ++#define OCR1D7 7 ++ ++#define OCR1C _SFR_IO8(0x2B) ++#define OCR1C0 0 ++#define OCR1C1 1 ++#define OCR1C2 2 ++#define OCR1C3 3 ++#define OCR1C4 4 ++#define OCR1C5 5 ++#define OCR1C6 6 ++#define OCR1C7 7 ++ ++#define OCR1B _SFR_IO8(0x2C) ++#define OCR1B0 0 ++#define OCR1B1 1 ++#define OCR1B2 2 ++#define OCR1B3 3 ++#define OCR1B4 4 ++#define OCR1B5 5 ++#define OCR1B6 6 ++#define OCR1B7 7 ++ ++#define OCR1A _SFR_IO8(0x2D) ++#define OCR1A0 0 ++#define OCR1A1 1 ++#define OCR1A2 2 ++#define OCR1A3 3 ++#define OCR1A4 4 ++#define OCR1A5 5 ++#define OCR1A6 6 ++#define OCR1A7 7 ++ ++#define TCNT1 _SFR_IO8(0x2E) ++#define TC1H_0 0 ++#define TC1H_1 1 ++#define TC1H_2 2 ++#define TC1H_3 3 ++#define TC1H_4 4 ++#define TC1H_5 5 ++#define TC1H_6 6 ++#define TC1H_7 7 ++ ++#define TCCR1B _SFR_IO8(0x2F) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define CS13 3 ++#define DTPS10 4 ++#define DTPS11 5 ++#define PSR1 6 ++ ++#define TCCR1A _SFR_IO8(0x30) ++#define PWM1B 0 ++#define PWM1A 1 ++#define FOC1B 2 ++#define FOC1A 3 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define OSCCAL _SFR_IO8(0x31) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define TCNT0L _SFR_IO8(0x32) ++#define TCNT0L_0 0 ++#define TCNT0L_1 1 ++#define TCNT0L_2 2 ++#define TCNT0L_3 3 ++#define TCNT0L_4 4 ++#define TCNT0L_5 5 ++#define TCNT0L_6 6 ++#define TCNT0L_7 7 ++ ++#define TCCR0B _SFR_IO8(0x33) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define PSR0 3 ++#define TSM 4 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define ISC00 0 ++#define ISC01 1 ++#define BODSE 2 ++#define SM0 3 ++#define SM1 4 ++#define SE 5 ++#define PUD 6 ++#define BODS 7 ++ ++#define PRR _SFR_IO8(0x36) ++#define PRADC 0 ++#define PRUSI 1 ++#define PRTIM0 2 ++#define PRTIM1 3 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define RFLB 3 ++#define CTPB 4 ++ ++#define TIFR _SFR_IO8(0x38) ++#define ICF0 0 ++#define TOV0 1 ++#define TOV1 2 ++#define OCF0B 3 ++#define OCF0A 4 ++#define OCF1B 5 ++#define OCF1A 6 ++#define OCF1D 7 ++ ++#define TIMSK _SFR_IO8(0x39) ++#define TICIE0 0 ++#define TOIE0 1 ++#define TOIE1 2 ++#define OCIE0B 3 ++#define OCIE0A 4 ++#define OCIE1B 5 ++#define OCIE1A 6 ++#define OCIE1D 7 ++ ++#define GIFR _SFR_IO8(0x3A) ++#define PCIF 5 ++#define INTF0 6 ++#define INTF1 7 ++ ++#define GIMSK _SFR_IO8(0x3B) ++#define PCIE0 4 ++#define PCIE1 5 ++#define INT0 6 ++#define INT1 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt 0 */ ++#define PCINT_vect_num 2 ++#define PCINT_vect _VECTOR(2) /* Pin Change Interrupt */ ++#define TIMER1_COMPA_vect_num 3 ++#define TIMER1_COMPA_vect _VECTOR(3) /* Timer/Counter1 Compare Match 1A */ ++#define TIMER1_COMPB_vect_num 4 ++#define TIMER1_COMPB_vect _VECTOR(4) /* Timer/Counter1 Compare Match 1B */ ++#define TIMER1_OVF_vect_num 5 ++#define TIMER1_OVF_vect _VECTOR(5) /* Timer/Counter1 Overflow */ ++#define TIMER0_OVF_vect_num 6 ++#define TIMER0_OVF_vect _VECTOR(6) /* Timer/Counter0 Overflow */ ++#define USI_START_vect_num 7 ++#define USI_START_vect _VECTOR(7) /* USI Start */ ++#define USI_OVF_vect_num 8 ++#define USI_OVF_vect _VECTOR(8) /* USI Overflow */ ++#define EE_RDY_vect_num 9 ++#define EE_RDY_vect _VECTOR(9) /* EEPROM Ready */ ++#define ANA_COMP_vect_num 10 ++#define ANA_COMP_vect _VECTOR(10) /* Analog Comparator */ ++#define ADC_vect_num 11 ++#define ADC_vect _VECTOR(11) /* ADC Conversion Complete */ ++#define WDT_vect_num 12 ++#define WDT_vect _VECTOR(12) /* Watchdog Time-Out */ ++#define INT1_vect_num 13 ++#define INT1_vect _VECTOR(13) /* External Interrupt 1 */ ++#define TIMER0_COMPA_vect_num 14 ++#define TIMER0_COMPA_vect _VECTOR(14) /* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPB_vect_num 15 ++#define TIMER0_COMPB_vect _VECTOR(15) /* Timer/Counter0 Compare Match B */ ++#define TIMER0_CAPT_vect_num 16 ++#define TIMER0_CAPT_vect _VECTOR(16) /* ADC Conversion Complete */ ++#define TIMER1_COMPD_vect_num 17 ++#define TIMER1_COMPD_vect _VECTOR(17) /* Timer/Counter1 Compare Match D */ ++#define FAULT_PROTECTION_vect_num 18 ++#define FAULT_PROTECTION_vect _VECTOR(18) /* Timer/Counter1 Fault Protection */ ++ ++#define _VECTOR_SIZE 2 /* Size of individual vector. */ ++#define _VECTORS_SIZE (19 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (32) ++#define RAMSTART (0x60) ++#define RAMSIZE (128) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x7F) ++#define E2PAGESIZE (4) ++#define FLASHEND (0x7FF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x91 ++#define SIGNATURE_2 0x0C ++ ++ ++/* Device Pin Definitions */ ++#define DI_B_DDR DDRMOSI ++#define DI_B_PORT PORTMOSI ++#define DI_B_PIN PINMOSI ++#define DI_B_BIT MOSI ++ ++#define SDA_B_DDR DDRMOSI ++#define SDA_B_PORT PORTMOSI ++#define SDA_B_PIN PINMOSI ++#define SDA_B_BIT MOSI ++ ++#define _OC1A_DDR DDRMOSI ++#define _OC1A_PORT PORTMOSI ++#define _OC1A_PIN PINMOSI ++#define _OC1A_BIT MOSI ++ ++#define PCINT8_DDR DDRMOSI ++#define PCINT8_PORT PORTMOSI ++#define PCINT8_PIN PINMOSI ++#define PCINT8_BIT MOSI ++ ++#define PB0_DDR DDRMOSI ++#define PB0_PORT PORTMOSI ++#define PB0_PIN PINMOSI ++#define PB0_BIT MOSI ++ ++#define DO_B_DDR DDRMISO ++#define DO_B_PORT PORTMISO ++#define DO_B_PIN PINMISO ++#define DO_B_BIT MISO ++ ++#define OC1A_DDR DDRMISO ++#define OC1A_PORT PORTMISO ++#define OC1A_PIN PINMISO ++#define OC1A_BIT MISO ++ ++#define PCINT9_DDR DDRMISO ++#define PCINT9_PORT PORTMISO ++#define PCINT9_PIN PINMISO ++#define PCINT9_BIT MISO ++ ++#define PB1_DDR DDRMISO ++#define PB1_PORT PORTMISO ++#define PB1_PIN PINMISO ++#define PB1_BIT MISO ++ ++#define USCK_B_DDR DDRSCK ++#define USCK_B_PORT PORTSCK ++#define USCK_B_PIN PINSCK ++#define USCK_B_BIT SCK ++ ++#define SCL_B_DDR DDRSCK ++#define SCL_B_PORT PORTSCK ++#define SCL_B_PIN PINSCK ++#define SCL_B_BIT SCK ++ ++#define OC1B_DDR DDRSCK ++#define OC1B_PORT PORTSCK ++#define OC1B_PIN PINSCK ++#define OC1B_BIT SCK ++ ++#define PCINT10_DDR DDRSCK ++#define PCINT10_PORT PORTSCK ++#define PCINT10_PIN PINSCK ++#define PCINT10_BIT SCK ++ ++#define PB2_DDR DDRSCK ++#define PB2_PORT PORTSCK ++#define PB2_PIN PINSCK ++#define PB2_BIT SCK ++ ++#define PCINT11_DDR DDROC1B ++#define PCINT11_PORT PORTOC1B ++#define PCINT11_PIN PINOC1B ++#define PCINT11_BIT OC1B ++ ++#define PB3_DDR DDROC1B ++#define PB3_PORT PORTOC1B ++#define PB3_PIN PINOC1B ++#define PB3_BIT OC1B ++ ++#define PCINT12_DDR DDRADC ++#define PCINT12_PORT PORTADC ++#define PCINT12_PIN PINADC ++#define PCINT12_BIT ADC7 ++ ++#define _OC1D_DDR DDRADC ++#define _OC1D_PORT PORTADC ++#define _OC1D_PIN PINADC ++#define _OC1D_BIT ADC7 ++ ++#define CLKI_DDR DDRADC ++#define CLKI_PORT PORTADC ++#define CLKI_PIN PINADC ++#define CLKI_BIT ADC7 ++ ++#define PB4_DDR DDRADC ++#define PB4_PORT PORTADC ++#define PB4_PIN PINADC ++#define PB4_BIT ADC7 ++ ++#define PCINT13_DDR DDRADC ++#define PCINT13_PORT PORTADC ++#define PCINT13_PIN PINADC ++#define PCINT13_BIT ADC8 ++ ++#define OC1D_DDR DDRADC ++#define OC1D_PORT PORTADC ++#define OC1D_PIN PINADC ++#define OC1D_BIT ADC8 ++ ++#define CKLO_DDR DDRADC ++#define CKLO_PORT PORTADC ++#define CKLO_PIN PINADC ++#define CKLO_BIT ADC8 ++ ++#define PB5_DDR DDRADC ++#define PB5_PORT PORTADC ++#define PB5_PIN PINADC ++#define PB5_BIT ADC8 ++ ++#define INT0_DDR DDRADC ++#define INT0_PORT PORTADC ++#define INT0_PIN PINADC ++#define INT0_BIT ADC9 ++ ++#define T0_DDR DDRADC ++#define T0_PORT PORTADC ++#define T0_PIN PINADC ++#define T0_BIT ADC9 ++ ++#define PCINT14_DDR DDRADC ++#define PCINT14_PORT PORTADC ++#define PCINT14_PIN PINADC ++#define PCINT14_BIT ADC9 ++ ++#define PB6_DDR DDRADC ++#define PB6_PORT PORTADC ++#define PB6_PIN PINADC ++#define PB6_BIT ADC9 ++ ++#define PCINT15_DDR DDRADC1 ++#define PCINT15_PORT PORTADC1 ++#define PCINT15_PIN PINADC1 ++#define PCINT15_BIT ADC10 ++ ++#define PB7_DDR DDRADC1 ++#define PB7_PORT PORTADC1 ++#define PB7_PIN PINADC1 ++#define PB7_BIT ADC10 ++ ++#define AIN1_DDR DDRADC ++#define AIN1_PORT PORTADC ++#define AIN1_PIN PINADC ++#define AIN1_BIT ADC6 ++ ++#define PCINT7_DDR DDRADC ++#define PCINT7_PORT PORTADC ++#define PCINT7_PIN PINADC ++#define PCINT7_BIT ADC6 ++ ++#define PA7_DDR DDRADC ++#define PA7_PORT PORTADC ++#define PA7_PIN PINADC ++#define PA7_BIT ADC6 ++ ++#define AIN0_DDR DDRADC ++#define AIN0_PORT PORTADC ++#define AIN0_PIN PINADC ++#define AIN0_BIT ADC5 ++ ++#define PCINT6_DDR DDRADC ++#define PCINT6_PORT PORTADC ++#define PCINT6_PIN PINADC ++#define PCINT6_BIT ADC5 ++ ++#define PA6_DDR DDRADC ++#define PA6_PORT PORTADC ++#define PA6_PIN PINADC ++#define PA6_BIT ADC5 ++ ++#define AIN2_DDR DDRADC ++#define AIN2_PORT PORTADC ++#define AIN2_PIN PINADC ++#define AIN2_BIT ADC4 ++ ++#define PCINT5_DDR DDRADC ++#define PCINT5_PORT PORTADC ++#define PCINT5_PIN PINADC ++#define PCINT5_BIT ADC4 ++ ++#define PA5_DDR DDRADC ++#define PA5_PORT PORTADC ++#define PA5_PIN PINADC ++#define PA5_BIT ADC4 ++ ++#define ICP0_DDR DDRADC ++#define ICP0_PORT PORTADC ++#define ICP0_PIN PINADC ++#define ICP0_BIT ADC3 ++ ++#define PCINT4_DDR DDRADC ++#define PCINT4_PORT PORTADC ++#define PCINT4_PIN PINADC ++#define PCINT4_BIT ADC3 ++ ++#define PA4_DDR DDRADC ++#define PA4_PORT PORTADC ++#define PA4_PIN PINADC ++#define PA4_BIT ADC3 ++ ++#define PCINT3_DDR DDRAREF ++#define PCINT3_PORT PORTAREF ++#define PCINT3_PIN PINAREF ++#define PCINT3_BIT AREF ++ ++#define PA3_DDR DDRAREF ++#define PA3_PORT PORTAREF ++#define PA3_PIN PINAREF ++#define PA3_BIT AREF ++ ++#define INT1_DDR DDRADC ++#define INT1_PORT PORTADC ++#define INT1_PIN PINADC ++#define INT1_BIT ADC2 ++ ++#define USCK_A_DDR DDRADC ++#define USCK_A_PORT PORTADC ++#define USCK_A_PIN PINADC ++#define USCK_A_BIT ADC2 ++ ++#define SCL_A_DDR DDRADC ++#define SCL_A_PORT PORTADC ++#define SCL_A_PIN PINADC ++#define SCL_A_BIT ADC2 ++ ++#define PCINT2_DDR DDRADC ++#define PCINT2_PORT PORTADC ++#define PCINT2_PIN PINADC ++#define PCINT2_BIT ADC2 ++ ++#define PA2_DDR DDRADC ++#define PA2_PORT PORTADC ++#define PA2_PIN PINADC ++#define PA2_BIT ADC2 ++ ++#define DO_A_DDR DDRADC ++#define DO_A_PORT PORTADC ++#define DO_A_PIN PINADC ++#define DO_A_BIT ADC1 ++ ++#define PCINT1_DDR DDRADC ++#define PCINT1_PORT PORTADC ++#define PCINT1_PIN PINADC ++#define PCINT1_BIT ADC1 ++ ++#define PA1_DDR DDRADC ++#define PA1_PORT PORTADC ++#define PA1_PIN PINADC ++#define PA1_BIT ADC1 ++ ++#define DI_A_DDR DDRADC ++#define DI_A_PORT PORTADC ++#define DI_A_PIN PINADC ++#define DI_A_BIT ADC0 ++ ++#define SDA_A_DDR DDRADC ++#define SDA_A_PORT PORTADC ++#define SDA_A_PIN PINADC ++#define SDA_A_BIT ADC0 ++ ++#define PCINT0_DDR DDRADC ++#define PCINT0_PORT PORTADC ++#define PCINT0_PIN PINADC ++#define PCINT0_BIT ADC0 ++ ++#define PA0_DDR DDRADC ++#define PA0_PORT PORTADC ++#define PA0_PIN PINADC ++#define PA0_BIT ADC0 ++ ++#endif /* _AVR_ATtiny261A_H_ */ ++ +diff --git a/include/avr/iotn28.h b/include/avr/iotn28.h +index 3f6eb05..ce36c85 100644 +--- a/include/avr/iotn28.h ++++ b/include/avr/iotn28.h +@@ -1,294 +1,295 @@ +-/* Copyright (c) 2002, Marek Michalkiewicz +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn28.h 2236 2011-03-17 21:53:39Z arcanum $ */ +- +-/* avr/iotn28.h - definitions for ATtiny28 */ +- +-#ifndef _AVR_IOTN28_H_ +-#define _AVR_IOTN28_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn28.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-#ifndef __ASSEMBLER__ +-# warning "MCU not supported by the C compiler" +-#endif +- +-/* I/O registers */ +- +-#define OSCCAL _SFR_IO8(0x00) +- +-#define WDTCR _SFR_IO8(0x01) +- +-#define MODCR _SFR_IO8(0x02) +- +-#define TCNT0 _SFR_IO8(0x03) +-#define TCCR0 _SFR_IO8(0x04) +- +-#define IFR _SFR_IO8(0x05) +-#define ICR _SFR_IO8(0x06) +- +-#define MCUCS _SFR_IO8(0x07) +- +-#define ACSR _SFR_IO8(0x08) +- +-/* 0x09..0x0F reserved */ +- +-#define PIND _SFR_IO8(0x10) +-#define DDRD _SFR_IO8(0x11) +-#define PORTD _SFR_IO8(0x12) +- +-/* 0x13..0x15 reserved */ +- +-#define PINB _SFR_IO8(0x16) +- +-/* 0x17..0x18 reserved */ +- +-#define PINA _SFR_IO8(0x19) +-#define PACR _SFR_IO8(0x1A) +-#define PORTA _SFR_IO8(0x1B) +- +-/* 0x1C..0x3E reserved */ +- +-/* 0x3F SREG */ +- +-/* Interrupt vectors */ +- +-/* External Interrupt 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* External Interrupt 1 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +-#define SIG_INTERRUPT1 _VECTOR(2) +- +-/* Low-level Input on Port B */ +-#define LOWLEVEL_IO_PINS_vect_num 3 +-#define LOWLEVEL_IO_PINS_vect _VECTOR(3) +-#define SIG_PIN _VECTOR(3) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 4 +-#define TIMER0_OVF_vect _VECTOR(4) +-#define SIG_OVERFLOW0 _VECTOR(4) +- +-/* Analog Comparator */ +-#define ANA_COMP_vect_num 5 +-#define ANA_COMP_vect _VECTOR(5) +-#define SIG_COMPARATOR _VECTOR(5) +- +-#define _VECTORS_SIZE 12 +- +- +-/* Bit numbers */ +- +-/* ICR */ +-#define INT1 7 +-#define INT0 6 +-#define LLIE 5 +-#define TOIE0 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 +- +-/* IFR */ +-#define INTF1 7 +-#define INTF0 6 +-#define TOV0 4 +- +-/* MCUCS */ +-#define PLUPB 7 +-#define SE 5 +-#define SM 4 +-#define WDRF 3 +-#define EXTRF 1 +-#define PORF 0 +- +-/* TCCR0 */ +-#define FOV0 7 +-#define OOM01 4 +-#define OOM00 3 +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-/* MODCR */ +-#define ONTIM4 7 +-#define ONTIM3 6 +-#define ONTIM2 5 +-#define ONTIM1 4 +-#define ONTIM0 3 +-#define MCONF2 2 +-#define MCONF1 1 +-#define MCONF0 0 +- +-/* WDTCR */ +-#define WDTOE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-/* +- PA2 = IR +- */ +- +-/* PORTA */ +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-/* PACR */ +-#define DDA3 3 +-#define PA2HC 2 +-#define DDA1 1 +-#define DDA0 0 +- +-/* PINA */ +-#define PINA3 3 +-#define PINA1 1 +-#define PINA0 0 +- +-/* +- PB4 = INT1 +- PB3 = INT0 +- PB2 = T0 +- PB1 = AIN1 +- PB0 = AIN0 +- */ +- +-/* PINB */ +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-/* PORTD */ +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* DDRD */ +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-/* PIND */ +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-/* ACSR */ +-#define ACD 7 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIS1 1 +-#define ACIS0 0 +- +-/* Last memory addresses */ +-#define RAMEND 0x1F +-#define XRAMEND 0x0 +-#define E2END 0x0 +-#define E2PAGESIZE 0 +-#define FLASHEND 0x7FF +- +- +-/* Fuses */ +- +-#define FUSE_MEMORY_SIZE 1 +- +-/* Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_INTCAP (unsigned char)~_BV(4) +-#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x91 +-#define SIGNATURE_2 0x07 +- +- +-/* Deprecated items */ +-#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) +- +-#pragma GCC system_header +- +-#pragma GCC poison SIG_INTERRUPT0 +-#pragma GCC poison SIG_INTERRUPT1 +-#pragma GCC poison SIG_PIN +-#pragma GCC poison SIG_OVERFLOW0 +-#pragma GCC poison SIG_COMPARATOR +- +-#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ +- +- +-#endif /* _AVR_IOTN28_H_ */ ++/* Copyright (c) 2002, Marek Michalkiewicz ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn28.h 2236 2011-03-17 21:53:39Z arcanum $ */ ++ ++/* avr/iotn28.h - definitions for ATtiny28 */ ++ ++#ifndef _AVR_IOTN28_H_ ++#define _AVR_IOTN28_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn28.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef __ASSEMBLER__ ++# warning "MCU not supported by the C compiler" ++#endif ++ ++/* I/O registers */ ++ ++#define OSCCAL _SFR_IO8(0x00) ++ ++#define WDTCR _SFR_IO8(0x01) ++ ++#define MODCR _SFR_IO8(0x02) ++ ++#define TCNT0 _SFR_IO8(0x03) ++#define TCCR0 _SFR_IO8(0x04) ++ ++#define IFR _SFR_IO8(0x05) ++#define ICR _SFR_IO8(0x06) ++ ++#define MCUCS _SFR_IO8(0x07) ++ ++#define ACSR _SFR_IO8(0x08) ++ ++/* 0x09..0x0F reserved */ ++ ++#define PIND _SFR_IO8(0x10) ++#define DDRD _SFR_IO8(0x11) ++#define PORTD _SFR_IO8(0x12) ++ ++/* 0x13..0x15 reserved */ ++ ++#define PINB _SFR_IO8(0x16) ++ ++/* 0x17..0x18 reserved */ ++ ++#define PINA _SFR_IO8(0x19) ++#define PACR _SFR_IO8(0x1A) ++#define PORTA _SFR_IO8(0x1B) ++ ++/* 0x1C..0x3E reserved */ ++ ++/* 0x3F SREG */ ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* External Interrupt 1 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++#define SIG_INTERRUPT1 _VECTOR(2) ++ ++/* Low-level Input on Port B */ ++#define LOWLEVEL_IO_PINS_vect_num 3 ++#define LOWLEVEL_IO_PINS_vect _VECTOR(3) ++#define SIG_PIN _VECTOR(3) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 4 ++#define TIMER0_OVF_vect _VECTOR(4) ++#define SIG_OVERFLOW0 _VECTOR(4) ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect_num 5 ++#define ANA_COMP_vect _VECTOR(5) ++#define SIG_COMPARATOR _VECTOR(5) ++ ++#define _VECTORS_SIZE 12 ++ ++ ++/* Bit numbers */ ++ ++/* ICR */ ++#define INT1 7 ++#define INT0 6 ++#define LLIE 5 ++#define TOIE0 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 ++ ++/* IFR */ ++#define INTF1 7 ++#define INTF0 6 ++#define TOV0 4 ++ ++/* MCUCS */ ++#define PLUPB 7 ++#define SE 5 ++#define SM 4 ++#define WDRF 3 ++#define EXTRF 1 ++#define PORF 0 ++ ++/* TCCR0 */ ++#define FOV0 7 ++#define OOM01 4 ++#define OOM00 3 ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++/* MODCR */ ++#define ONTIM4 7 ++#define ONTIM3 6 ++#define ONTIM2 5 ++#define ONTIM1 4 ++#define ONTIM0 3 ++#define MCONF2 2 ++#define MCONF1 1 ++#define MCONF0 0 ++ ++/* WDTCR */ ++#define WDTOE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++/* ++ PA2 = IR ++ */ ++ ++/* PORTA */ ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++/* PACR */ ++#define DDA3 3 ++#define PA2HC 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++/* PINA */ ++#define PINA3 3 ++#define PINA1 1 ++#define PINA0 0 ++ ++/* ++ PB4 = INT1 ++ PB3 = INT0 ++ PB2 = T0 ++ PB1 = AIN1 ++ PB0 = AIN0 ++ */ ++ ++/* PINB */ ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++/* PORTD */ ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* DDRD */ ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++/* PIND */ ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++/* ACSR */ ++#define ACD 7 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++#define RAMSTART 0x60 ++/* Last memory addresses */ ++#define RAMEND 0x1F ++#define XRAMEND 0x0 ++#define E2END 0x0 ++#define E2PAGESIZE 0 ++#define FLASHEND 0x7FF ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 1 ++ ++/* Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_INTCAP (unsigned char)~_BV(4) ++#define FUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x91 ++#define SIGNATURE_2 0x07 ++ ++ ++/* Deprecated items */ ++#if !defined(__AVR_LIBC_DEPRECATED_ENABLE__) ++ ++#pragma GCC system_header ++ ++#pragma GCC poison SIG_INTERRUPT0 ++#pragma GCC poison SIG_INTERRUPT1 ++#pragma GCC poison SIG_PIN ++#pragma GCC poison SIG_OVERFLOW0 ++#pragma GCC poison SIG_COMPARATOR ++ ++#endif /* !defined(__AVR_LIBC_DEPRECATED_ENABLE__) */ ++ ++ ++#endif /* _AVR_IOTN28_H_ */ +diff --git a/include/avr/iotn4.h b/include/avr/iotn4.h +index fe7e724..addd83d 100644 +--- a/include/avr/iotn4.h ++++ b/include/avr/iotn4.h +@@ -1,468 +1,468 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn4.h 2063 2009-11-18 22:06:28Z arcanum $ */ +- +-/* avr/iotn4.h - definitions for ATtiny4 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn4.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATtiny4_H_ +-#define _AVR_ATtiny4_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINB _SFR_IO8(0x00) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +- +-#define DDRB _SFR_IO8(0x01) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +- +-#define PORTB _SFR_IO8(0x02) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +- +-#define PUEB _SFR_IO8(0x03) +-#define PUEB0 0 +-#define PUEB1 1 +-#define PUEB2 2 +-#define PUEB3 3 +- +-#define PORTCR _SFR_IO8(0x0C) +-#define BBMB 1 +- +-#define PCMSK _SFR_IO8(0x10) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +- +-#define PCIFR _SFR_IO8(0x11) +-#define PCIF0 0 +- +-#define PCICR _SFR_IO8(0x12) +-#define PCIE0 0 +- +-#define EIMSK _SFR_IO8(0x13) +-#define INT0 0 +- +-#define EIFR _SFR_IO8(0x14) +-#define INTF0 0 +- +-#define EICRA _SFR_IO8(0x15) +-#define ISC00 0 +-#define ISC01 1 +- +-#define DIDR0 _SFR_IO8(0x17) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define ACSR _SFR_IO8(0x1F) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACD 7 +- +-#define ICR0 _SFR_IO16(0x22) +- +-#define ICR0L _SFR_IO8(0x22) +-#define ICR0_0 0 +-#define ICR0_1 1 +-#define ICR0_2 2 +-#define ICR0_3 3 +-#define ICR0_4 4 +-#define ICR0_5 5 +-#define ICR0_6 6 +-#define ICR0_7 7 +- +-#define ICR0H _SFR_IO8(0x23) +-#define ICR0_8 0 +-#define ICR0_9 1 +-#define ICR0_10 2 +-#define ICR0_11 3 +-#define ICR0_12 4 +-#define ICR0_13 5 +-#define ICR0_14 6 +-#define ICR0_15 7 +- +-#define OCR0B _SFR_IO16(0x24) +- +-#define OCR0BL _SFR_IO8(0x24) +-#define OCR0B0 0 +-#define OCR0B1 1 +-#define OCR0B2 2 +-#define OCR0B3 3 +-#define OCR0B4 4 +-#define OCR0B5 5 +-#define OCR0B6 6 +-#define OCR0B7 7 +- +-#define OCR0BH _SFR_IO8(0x25) +-#define OCR0B8 0 +-#define OCR0B9 1 +-#define OCR0B10 2 +-#define OCR0B11 3 +-#define OCR0B12 4 +-#define OCR0B13 5 +-#define OCR0B14 6 +-#define OCR0B15 7 +- +-#define OCR0A _SFR_IO16(0x26) +- +-#define OCR0AL _SFR_IO8(0x26) +-#define OCR0A0 0 +-#define OCR0A1 1 +-#define OCR0A2 2 +-#define OCR0A3 3 +-#define OCR0A4 4 +-#define OCR0A5 5 +-#define OCR0A6 6 +-#define OCR0A7 7 +- +-#define OCR0AH _SFR_IO8(0x27) +-#define OCR0A8 0 +-#define OCR0A9 1 +-#define OCR0A10 2 +-#define OCR0A11 3 +-#define OCR0A12 4 +-#define OCR0A13 5 +-#define OCR0A14 6 +-#define OCR0A15 7 +- +-#define TCNT0 _SFR_IO16(0x28) +- +-#define TCNT0L _SFR_IO8(0x28) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define TCNT0H _SFR_IO8(0x29) +-#define TCNT0_8 0 +-#define TCNT0_9 1 +-#define TCNT0_10 2 +-#define TCNT0_11 3 +-#define TCNT0_12 4 +-#define TCNT0_13 5 +-#define TCNT0_14 6 +-#define TCNT0_15 7 +- +-#define TIFR0 _SFR_IO8(0x2A) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +-#define ICF0 5 +- +-#define TIMSK0 _SFR_IO8(0x2B) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +-#define ICIE0 5 +- +-#define TCCR0C _SFR_IO8(0x2C) +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCCR0B _SFR_IO8(0x2D) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define WGM03 4 +-#define ICES0 6 +-#define ICNC0 7 +- +-#define TCCR0A _SFR_IO8(0x2E) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define GTCCR _SFR_IO8(0x2F) +-#define PSR 0 +-#define TSM 7 +- +-#define WDTCSR _SFR_IO8(0x31) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define NVMCSR _SFR_IO8(0x32) +-#define NVMBSY 7 +- +-#define NVMCMD _SFR_IO8(0x33) +-#define NVMCMD0 0 +-#define NVMCMD1 1 +-#define NVMCMD2 2 +-#define NVMCMD3 3 +-#define NVMCMD4 4 +-#define NVMCMD5 5 +- +-#define VLMCSR _SFR_IO8(0x34) +-#define VLM0 0 +-#define VLM1 1 +-#define VLM2 2 +-#define VLMIE 6 +-#define VLMF 7 +- +-#define PRR _SFR_IO8(0x35) +-#define PRTIM0 0 +-#define PRADC 1 +- +-#define CLKPSR _SFR_IO8(0x36) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +- +-#define CLKMSR _SFR_IO8(0x37) +-#define CLKMS0 0 +-#define CLKMS1 1 +- +-#define OSCCAL _SFR_IO8(0x39) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define SMCR _SFR_IO8(0x3A) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define RSTFLR _SFR_IO8(0x3B) +-#define PORF 0 +-#define EXTRF 1 +-#define WDRF 3 +- +-#define CCP _SFR_IO8(0x3C) +-#define CCP0 0 +-#define CCP1 1 +-#define CCP2 2 +-#define CCP3 3 +-#define CCP4 4 +-#define CCP5 5 +-#define CCP6 6 +-#define CCP7 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ +-#define TIM0_CAPT_vect_num 3 +-#define TIM0_CAPT_vect _VECTOR(3) /* Timer/Counter0 Input Capture */ +-#define TIM0_OVF_vect_num 4 +-#define TIM0_OVF_vect _VECTOR(4) /* Timer/Counter0 Overflow */ +-#define TIM0_COMPA_vect_num 5 +-#define TIM0_COMPA_vect _VECTOR(5) /* Timer/Counter Compare Match A */ +-#define TIM0_COMPB_vect_num 6 +-#define TIM0_COMPB_vect _VECTOR(6) /* Timer/Counter Compare Match B */ +-#define ANA_COMP_vect_num 7 +-#define ANA_COMP_vect _VECTOR(7) /* Analog Comparator */ +-#define WDT_vect_num 8 +-#define WDT_vect _VECTOR(8) /* Watchdog Time-out */ +-#define VLM_vect_num 9 +-#define VLM_vect _VECTOR(9) /* Vcc Voltage Level Monitor */ +- +-#define _VECTOR_SIZE 2 /* Size of individual vector. */ +-#define _VECTORS_SIZE (10 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (32) +-#define RAMSTART (0x40) +-#define RAMSIZE (32) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x0) +-#define E2PAGESIZE (0) +-#define FLASHEND (0x1FF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 0 +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x90 +-#define SIGNATURE_2 0x0A +- +- +-/* Device Pin Definitions */ +-#define SPDATA_DDR DDRCINT +-#define SPDATA_PORT PORTCINT +-#define SPDATA_PIN PINCINT +-#define SPDATA_BIT INT0 +- +-#define OC0A_DDR DDRCINT +-#define OC0A_PORT PORTCINT +-#define OC0A_PIN PINCINT +-#define OC0A_BIT INT0 +- +-#define ADC0_DDR DDRCINT +-#define ADC0_PORT PORTCINT +-#define ADC0_PIN PINCINT +-#define ADC0_BIT INT0 +- +-#define AIN0_DDR DDRCINT +-#define AIN0_PORT PORTCINT +-#define AIN0_PIN PINCINT +-#define AIN0_BIT INT0 +- +-#define PB0_DDR DDRCINT +-#define PB0_PORT PORTCINT +-#define PB0_PIN PINCINT +-#define PB0_BIT INT0 +- +-#define SPCLK_DDR DDRCINT +-#define SPCLK_PORT PORTCINT +-#define SPCLK_PIN PINCINT +-#define SPCLK_BIT INT1 +- +-#define CLKI_DDR DDRCINT +-#define CLKI_PORT PORTCINT +-#define CLKI_PIN PINCINT +-#define CLKI_BIT INT1 +- +-#define ICP0_DDR DDRCINT +-#define ICP0_PORT PORTCINT +-#define ICP0_PIN PINCINT +-#define ICP0_BIT INT1 +- +-#define OC0B_DDR DDRCINT +-#define OC0B_PORT PORTCINT +-#define OC0B_PIN PINCINT +-#define OC0B_BIT INT1 +- +-#define ADC1_DDR DDRCINT +-#define ADC1_PORT PORTCINT +-#define ADC1_PIN PINCINT +-#define ADC1_BIT INT1 +- +-#define AIN1_DDR DDRCINT +-#define AIN1_PORT PORTCINT +-#define AIN1_PIN PINCINT +-#define AIN1_BIT INT1 +- +-#define PB1_DDR DDRCINT +-#define PB1_PORT PORTCINT +-#define PB1_PIN PINCINT +-#define PB1_BIT INT1 +- +-#define CLKO_DDR DDRT +-#define CLKO_PORT PORTT +-#define CLKO_PIN PINT +-#define CLKO_BIT T0 +- +-#define PCINT2_DDR DDRT +-#define PCINT2_PORT PORTT +-#define PCINT2_PIN PINT +-#define PCINT2_BIT T0 +- +-#define INT0_DDR DDRT +-#define INT0_PORT PORTT +-#define INT0_PIN PINT +-#define INT0_BIT T0 +- +-#define ADC2_DDR DDRT +-#define ADC2_PORT PORTT +-#define ADC2_PIN PINT +-#define ADC2_BIT T0 +- +-#define PB2_DDR DDRT +-#define PB2_PORT PORTT +-#define PB2_PIN PINT +-#define PB2_BIT T0 +- +-#define PCINT3_DDR DDRRESET +-#define PCINT3_PORT PORTRESET +-#define PCINT3_PIN PINRESET +-#define PCINT3_BIT RESET +- +-#define ADC3_DDR DDRRESET +-#define ADC3_PORT PORTRESET +-#define ADC3_PIN PINRESET +-#define ADC3_BIT RESET +- +-#define PB3_DDR DDRRESET +-#define PB3_PORT PORTRESET +-#define PB3_PIN PINRESET +-#define PB3_BIT RESET +- +-#endif /* _AVR_ATtiny4_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn4.h 2063 2009-11-18 22:06:28Z arcanum $ */ ++ ++/* avr/iotn4.h - definitions for ATtiny4 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn4.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATtiny4_H_ ++#define _AVR_ATtiny4_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINB _SFR_IO8(0x00) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++ ++#define DDRB _SFR_IO8(0x01) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++ ++#define PORTB _SFR_IO8(0x02) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++ ++#define PUEB _SFR_IO8(0x03) ++#define PUEB0 0 ++#define PUEB1 1 ++#define PUEB2 2 ++#define PUEB3 3 ++ ++#define PORTCR _SFR_IO8(0x0C) ++#define BBMB 1 ++ ++#define PCMSK _SFR_IO8(0x10) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++ ++#define PCIFR _SFR_IO8(0x11) ++#define PCIF0 0 ++ ++#define PCICR _SFR_IO8(0x12) ++#define PCIE0 0 ++ ++#define EIMSK _SFR_IO8(0x13) ++#define INT0 0 ++ ++#define EIFR _SFR_IO8(0x14) ++#define INTF0 0 ++ ++#define EICRA _SFR_IO8(0x15) ++#define ISC00 0 ++#define ISC01 1 ++ ++#define DIDR0 _SFR_IO8(0x17) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define ACSR _SFR_IO8(0x1F) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACD 7 ++ ++#define ICR0 _SFR_IO16(0x22) ++ ++#define ICR0L _SFR_IO8(0x22) ++#define ICR0_0 0 ++#define ICR0_1 1 ++#define ICR0_2 2 ++#define ICR0_3 3 ++#define ICR0_4 4 ++#define ICR0_5 5 ++#define ICR0_6 6 ++#define ICR0_7 7 ++ ++#define ICR0H _SFR_IO8(0x23) ++#define ICR0_8 0 ++#define ICR0_9 1 ++#define ICR0_10 2 ++#define ICR0_11 3 ++#define ICR0_12 4 ++#define ICR0_13 5 ++#define ICR0_14 6 ++#define ICR0_15 7 ++ ++#define OCR0B _SFR_IO16(0x24) ++ ++#define OCR0BL _SFR_IO8(0x24) ++#define OCR0B0 0 ++#define OCR0B1 1 ++#define OCR0B2 2 ++#define OCR0B3 3 ++#define OCR0B4 4 ++#define OCR0B5 5 ++#define OCR0B6 6 ++#define OCR0B7 7 ++ ++#define OCR0BH _SFR_IO8(0x25) ++#define OCR0B8 0 ++#define OCR0B9 1 ++#define OCR0B10 2 ++#define OCR0B11 3 ++#define OCR0B12 4 ++#define OCR0B13 5 ++#define OCR0B14 6 ++#define OCR0B15 7 ++ ++#define OCR0A _SFR_IO16(0x26) ++ ++#define OCR0AL _SFR_IO8(0x26) ++#define OCR0A0 0 ++#define OCR0A1 1 ++#define OCR0A2 2 ++#define OCR0A3 3 ++#define OCR0A4 4 ++#define OCR0A5 5 ++#define OCR0A6 6 ++#define OCR0A7 7 ++ ++#define OCR0AH _SFR_IO8(0x27) ++#define OCR0A8 0 ++#define OCR0A9 1 ++#define OCR0A10 2 ++#define OCR0A11 3 ++#define OCR0A12 4 ++#define OCR0A13 5 ++#define OCR0A14 6 ++#define OCR0A15 7 ++ ++#define TCNT0 _SFR_IO16(0x28) ++ ++#define TCNT0L _SFR_IO8(0x28) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define TCNT0H _SFR_IO8(0x29) ++#define TCNT0_8 0 ++#define TCNT0_9 1 ++#define TCNT0_10 2 ++#define TCNT0_11 3 ++#define TCNT0_12 4 ++#define TCNT0_13 5 ++#define TCNT0_14 6 ++#define TCNT0_15 7 ++ ++#define TIFR0 _SFR_IO8(0x2A) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++#define ICF0 5 ++ ++#define TIMSK0 _SFR_IO8(0x2B) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++#define ICIE0 5 ++ ++#define TCCR0C _SFR_IO8(0x2C) ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCCR0B _SFR_IO8(0x2D) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define WGM03 4 ++#define ICES0 6 ++#define ICNC0 7 ++ ++#define TCCR0A _SFR_IO8(0x2E) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define GTCCR _SFR_IO8(0x2F) ++#define PSR 0 ++#define TSM 7 ++ ++#define WDTCSR _SFR_IO8(0x31) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define NVMCSR _SFR_IO8(0x32) ++#define NVMBSY 7 ++ ++#define NVMCMD _SFR_IO8(0x33) ++#define NVMCMD0 0 ++#define NVMCMD1 1 ++#define NVMCMD2 2 ++#define NVMCMD3 3 ++#define NVMCMD4 4 ++#define NVMCMD5 5 ++ ++#define VLMCSR _SFR_IO8(0x34) ++#define VLM0 0 ++#define VLM1 1 ++#define VLM2 2 ++#define VLMIE 6 ++#define VLMF 7 ++ ++#define PRR _SFR_IO8(0x35) ++#define PRTIM0 0 ++#define PRADC 1 ++ ++#define CLKPSR _SFR_IO8(0x36) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++ ++#define CLKMSR _SFR_IO8(0x37) ++#define CLKMS0 0 ++#define CLKMS1 1 ++ ++#define OSCCAL _SFR_IO8(0x39) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define SMCR _SFR_IO8(0x3A) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define RSTFLR _SFR_IO8(0x3B) ++#define PORF 0 ++#define EXTRF 1 ++#define WDRF 3 ++ ++#define CCP _SFR_IO8(0x3C) ++#define CCP0 0 ++#define CCP1 1 ++#define CCP2 2 ++#define CCP3 3 ++#define CCP4 4 ++#define CCP5 5 ++#define CCP6 6 ++#define CCP7 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ ++#define TIM0_CAPT_vect_num 3 ++#define TIM0_CAPT_vect _VECTOR(3) /* Timer/Counter0 Input Capture */ ++#define TIM0_OVF_vect_num 4 ++#define TIM0_OVF_vect _VECTOR(4) /* Timer/Counter0 Overflow */ ++#define TIM0_COMPA_vect_num 5 ++#define TIM0_COMPA_vect _VECTOR(5) /* Timer/Counter Compare Match A */ ++#define TIM0_COMPB_vect_num 6 ++#define TIM0_COMPB_vect _VECTOR(6) /* Timer/Counter Compare Match B */ ++#define ANA_COMP_vect_num 7 ++#define ANA_COMP_vect _VECTOR(7) /* Analog Comparator */ ++#define WDT_vect_num 8 ++#define WDT_vect _VECTOR(8) /* Watchdog Time-out */ ++#define VLM_vect_num 9 ++#define VLM_vect _VECTOR(9) /* Vcc Voltage Level Monitor */ ++ ++#define _VECTOR_SIZE 2 /* Size of individual vector. */ ++#define _VECTORS_SIZE (10 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (32) ++#define RAMSTART (0x40) ++#define RAMSIZE (32) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x0) ++#define E2PAGESIZE (0) ++#define FLASHEND (0x1FF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 0 ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x90 ++#define SIGNATURE_2 0x0A ++ ++ ++/* Device Pin Definitions */ ++#define SPDATA_DDR DDRCINT ++#define SPDATA_PORT PORTCINT ++#define SPDATA_PIN PINCINT ++#define SPDATA_BIT INT0 ++ ++#define OC0A_DDR DDRCINT ++#define OC0A_PORT PORTCINT ++#define OC0A_PIN PINCINT ++#define OC0A_BIT INT0 ++ ++#define ADC0_DDR DDRCINT ++#define ADC0_PORT PORTCINT ++#define ADC0_PIN PINCINT ++#define ADC0_BIT INT0 ++ ++#define AIN0_DDR DDRCINT ++#define AIN0_PORT PORTCINT ++#define AIN0_PIN PINCINT ++#define AIN0_BIT INT0 ++ ++#define PB0_DDR DDRCINT ++#define PB0_PORT PORTCINT ++#define PB0_PIN PINCINT ++#define PB0_BIT INT0 ++ ++#define SPCLK_DDR DDRCINT ++#define SPCLK_PORT PORTCINT ++#define SPCLK_PIN PINCINT ++#define SPCLK_BIT INT1 ++ ++#define CLKI_DDR DDRCINT ++#define CLKI_PORT PORTCINT ++#define CLKI_PIN PINCINT ++#define CLKI_BIT INT1 ++ ++#define ICP0_DDR DDRCINT ++#define ICP0_PORT PORTCINT ++#define ICP0_PIN PINCINT ++#define ICP0_BIT INT1 ++ ++#define OC0B_DDR DDRCINT ++#define OC0B_PORT PORTCINT ++#define OC0B_PIN PINCINT ++#define OC0B_BIT INT1 ++ ++#define ADC1_DDR DDRCINT ++#define ADC1_PORT PORTCINT ++#define ADC1_PIN PINCINT ++#define ADC1_BIT INT1 ++ ++#define AIN1_DDR DDRCINT ++#define AIN1_PORT PORTCINT ++#define AIN1_PIN PINCINT ++#define AIN1_BIT INT1 ++ ++#define PB1_DDR DDRCINT ++#define PB1_PORT PORTCINT ++#define PB1_PIN PINCINT ++#define PB1_BIT INT1 ++ ++#define CLKO_DDR DDRT ++#define CLKO_PORT PORTT ++#define CLKO_PIN PINT ++#define CLKO_BIT T0 ++ ++#define PCINT2_DDR DDRT ++#define PCINT2_PORT PORTT ++#define PCINT2_PIN PINT ++#define PCINT2_BIT T0 ++ ++#define INT0_DDR DDRT ++#define INT0_PORT PORTT ++#define INT0_PIN PINT ++#define INT0_BIT T0 ++ ++#define ADC2_DDR DDRT ++#define ADC2_PORT PORTT ++#define ADC2_PIN PINT ++#define ADC2_BIT T0 ++ ++#define PB2_DDR DDRT ++#define PB2_PORT PORTT ++#define PB2_PIN PINT ++#define PB2_BIT T0 ++ ++#define PCINT3_DDR DDRRESET ++#define PCINT3_PORT PORTRESET ++#define PCINT3_PIN PINRESET ++#define PCINT3_BIT RESET ++ ++#define ADC3_DDR DDRRESET ++#define ADC3_PORT PORTRESET ++#define ADC3_PIN PINRESET ++#define ADC3_BIT RESET ++ ++#define PB3_DDR DDRRESET ++#define PB3_PORT PORTRESET ++#define PB3_PIN PINRESET ++#define PB3_BIT RESET ++ ++#endif /* _AVR_ATtiny4_H_ */ ++ +diff --git a/include/avr/iotn40.h b/include/avr/iotn40.h +index 01c8531..a938bb1 100644 +--- a/include/avr/iotn40.h ++++ b/include/avr/iotn40.h +@@ -1,753 +1,755 @@ -/* Copyright (c) 2010 Atmel Corporation - All rights reserved. -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ - +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id$ */ +- +-/* avr/iotn40.h - definitions for ATtiny40 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn40.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATtiny40_H_ +-#define _AVR_ATtiny40_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +-#define PINA4 4 +-#define PINA5 5 +-#define PINA6 6 +-#define PINA7 7 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +-#define DDA4 4 +-#define DDA5 5 +-#define DDA6 6 +-#define DDA7 7 +- +-#define PORTA _SFR_IO8(0x02) +-#define PORTA0 0 +-#define PORTA1 1 +-#define PORTA2 2 +-#define PORTA3 3 +-#define PORTA4 4 +-#define PORTA5 5 +-#define PORTA6 6 +-#define PORTA7 7 +- +-#define PUEA _SFR_IO8(0x03) +-#define PUEA0 0 +-#define PUEA1 1 +-#define PUEA2 2 +-#define PUEA3 3 +-#define PUEA4 4 +-#define PUEA5 5 +-#define PUEA6 6 +-#define PUEA7 7 +- +-#define PINB _SFR_IO8(0x04) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +- +-#define DDRB _SFR_IO8(0x05) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +- +-#define PORTB _SFR_IO8(0x06) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +- +-#define PUEB _SFR_IO8(0x07) +-#define PUEB0 0 +-#define PUEB1 1 +-#define PUEB2 2 +-#define PUEB3 3 +- +-#define PORTCR _SFR_IO8(0x08) +-#define BBMA 0 +-#define BBMB 1 +-#define BBMC 2 +-#define ADC8D 4 +-#define ADC9D 5 +-#define ADC10D 6 +-#define ADC11D 7 +- +-#define PCMSK0 _SFR_IO8(0x09) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_IO8(0x0A) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +- +-#define GIFR _SFR_IO8(0x0B) +-#define INTF0 0 +-#define PCIF0 4 +-#define PCIF1 5 +-#define PCIF2 6 +- +-#define GIMSK _SFR_IO8(0x0C) +-#define INT0 0 +-#define PCIE0 4 +-#define PCIE1 5 +-#define PCIE2 6 +- +-#define DIDR0 _SFR_IO8(0x0D) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x0E) +-#endif +-#define ADCW _SFR_IO16(0x0E) +- +-#define ADCL _SFR_IO8(0x0E) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_IO8(0x0F) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADMUX _SFR_IO8(0x10) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define REFS 6 +- +-#define ADCSRB _SFR_IO8(0x11) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ADLAR 3 +- +-#define ADCSRA _SFR_IO8(0x12) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ACSRB _SFR_IO8(0x13) +-#define ACME 2 +-#define HLEV 6 +-#define HSEL 7 +- +-#define ACSRA _SFR_IO8(0x14) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define OCR0B _SFR_IO8(0x15) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define OCR0A _SFR_IO8(0x16) +-#define OCR0_0 0 +-#define OCR0_1 1 +-#define OCR0_2 2 +-#define OCR0_3 3 +-#define OCR0_4 4 +-#define OCR0_5 5 +-#define OCR0_6 6 +-#define OCR0_7 7 +- +-#define TCNT0 _SFR_IO8(0x17) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define TCCR0B _SFR_IO8(0x18) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define PSR 4 +-#define TSM 5 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCCR0A _SFR_IO8(0x19) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define PCMSK2 _SFR_IO8(0x1A) +-#define PCINT12 0 +-#define PCINT13 1 +-#define PCINT14 2 +-#define PCINT15 3 +-#define PCINT16 4 +-#define PCINT17 5 +- +-#define PINC _SFR_IO8(0x1B) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +-#define PINC5 5 +- +-#define DDRC _SFR_IO8(0x1C) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC3 3 +-#define DDC4 4 +-#define DDC5 5 +- +-#define PORTC _SFR_IO8(0x1D) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC3 3 +-#define PORTC4 4 +-#define PORTC5 5 +- +-#define PUEC _SFR_IO8(0x1E) +-#define PUEC0 0 +-#define PUEC1 1 +-#define PUEC2 2 +-#define PUEC3 3 +-#define PUEC4 4 +-#define PUEC5 5 +- +-#define RAMDR _SFR_IO8(0x1F) +-#define RAMDR0 0 +-#define RAMDR1 1 +-#define RAMDR2 2 +-#define RAMDR3 3 +-#define RAMDR4 4 +-#define RAMDR5 5 +-#define RAMDR6 6 +-#define RAMDR7 7 +- +-#define RAMAR _SFR_IO8(0x20) +-#define RAMAR0 0 +-#define RAMAR1 1 +-#define RAMAR2 2 +-#define RAMAR3 3 +-#define RAMAR4 4 +-#define RAMAR5 5 +-#define RAMAR6 6 +-#define RAMAR7 7 +- +-#define OCR1B _SFR_IO8(0x21) +-#define OCR1B0 0 +-#define OCR1B1 1 +-#define OCR1B2 2 +-#define OCR1B3 3 +-#define OCR1B4 4 +-#define OCR1B5 5 +-#define OCR1B6 6 +-#define OCR1B7 7 +- +-#define OCR1A _SFR_IO8(0x22) +-#define OCR1A0 0 +-#define OCR1A1 1 +-#define OCR1A2 2 +-#define OCR1A3 3 +-#define OCR1A4 4 +-#define OCR1A5 5 +-#define OCR1A6 6 +-#define OCR1A7 7 +- +-#define TCNT1L _SFR_IO8(0x23) +-#define TCNT1_0 0 +-#define TCNT1_1 1 +-#define TCNT1_2 2 +-#define TCNT1_3 3 +-#define TCNT1_4 4 +-#define TCNT1_5 5 +-#define TCNT1_6 6 +-#define TCNT1_7 7 +- +-#define TCCR1A _SFR_IO8(0x24) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define CTC1 3 +-#define ICES1 4 +-#define ICNC1 5 +-#define ICEN1 6 +-#define TCW1 7 +- +-#define TIFR _SFR_IO8(0x25) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +-#define TOV1 3 +-#define OCF1A 4 +-#define OCF1B 5 +-#define ICF1 7 +- +-#define TIMSK _SFR_IO8(0x26) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +-#define TOIE1 3 +-#define OCIE1A 4 +-#define OCIE1B 5 +-#define ICIE1 7 +- +-#define TCNT1H _SFR_IO8(0x27) +-#define TCNT1_8 0 +-#define TCNT1_9 1 +-#define TCNT1_10 2 +-#define TCNT1_11 3 +-#define TCNT1_12 4 +-#define TCNT1_13 5 +-#define TCNT1_14 6 +-#define TCNT1_15 7 +- +-#define TWSD _SFR_IO8(0x28) +-#define TWSD0 0 +-#define TWSD1 1 +-#define TWSD2 2 +-#define TWSD3 3 +-#define TWSD4 4 +-#define TWSD5 5 +-#define TWSD6 6 +-#define TWSD7 7 +- +-#define TWSAM _SFR_IO8(0x29) +-#define TWAE 0 +-#define TWSAM1 1 +-#define TWSAM2 2 +-#define TWSAM3 3 +-#define TWSAM4 4 +-#define TWSAM5 5 +-#define TWSAM6 6 +-#define TWSAM7 7 +- +-#define TWSA _SFR_IO8(0x2A) +-#define TWSA0 0 +-#define TWSA1 1 +-#define TWSA2 2 +-#define TWSA3 3 +-#define TWSA4 4 +-#define TWSA5 5 +-#define TWSA6 6 +-#define TWSA7 7 +- +-#define TWSSRA _SFR_IO8(0x2B) +-#define TWAS 0 +-#define TWDIR 1 +-#define TWBE 2 +-#define TWC 3 +-#define TWRA 4 +-#define TWCH 5 +-#define TWASIF 6 +-#define TWDIF 7 +- +-#define TWSCRB _SFR_IO8(0x2C) +-#define TWCMD0 0 +-#define TWCMD1 1 +-#define TWAA 2 +- +-#define TWSCRA _SFR_IO8(0x2D) +-#define TWSME 0 +-#define TWPME 1 +-#define TWSIE 2 +-#define TWEN 3 +-#define TWASIE 4 +-#define TWDIE 5 +-#define TWSHE 7 +- +-#define SPDR _SFR_IO8(0x2E) +- +-#define SPSR _SFR_IO8(0x2F) +- +-#define SPCR _SFR_IO8(0x30) +- +-#define WDTCSR _SFR_IO8(0x31) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define NVMCSR _SFR_IO8(0x32) +-#define NVMBSY 7 +- +-#define NVMCMD _SFR_IO8(0x33) +-#define NVMCMD0 0 +-#define NVMCMD1 1 +-#define NVMCMD2 2 +-#define NVMCMD3 3 +-#define NVMCMD4 4 +-#define NVMCMD5 5 +- +-#define QTCSR _SFR_IO8(0x34) +- +-#define PRR _SFR_IO8(0x35) +-#define PRADC 0 +-#define PRTIM0 1 +-#define PRTIM1 2 +-#define PRSPI 3 +-#define PRTWI 4 +- +-#define CLKPSR _SFR_IO8(0x36) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +- +-#define CLKMSR _SFR_IO8(0x37) +-#define CLKMS0 0 +-#define CLKMS1 1 +- +-#define DWDR _SFR_IO8(0x38) +- +-#define OSCCAL _SFR_IO8(0x39) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define MCUCR _SFR_IO8(0x3A) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +-#define BODS 4 +-#define ISC00 6 +-#define ISC01 7 +- +-#define RSTFLR _SFR_IO8(0x3B) +-#define PORF 0 +-#define EXTRF 1 +-#define WDRF 3 +- +-#define CCP _SFR_IO8(0x3C) +-#define CCP0 0 +-#define CCP1 1 +-#define CCP2 2 +-#define CCP3 3 +-#define CCP4 4 +-#define CCP5 5 +-#define CCP6 6 +-#define CCP7 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ +-#define PCINT1_vect_num 3 +-#define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */ +-#define WDT_vect_num 4 +-#define WDT_vect _VECTOR(4) /* Watchdog Time-out */ +-#define TIM1_CAPT_vect_num 5 +-#define TIM1_CAPT_vect _VECTOR(5) /* Timer/Counter1 Input Capture */ +-#define TIM1_COMPA_vect_num 6 +-#define TIM1_COMPA_vect _VECTOR(6) /* Timer/Counter1 Compare Match A */ +-#define TIM1_COMPB_vect_num 7 +-#define TIM1_COMPB_vect _VECTOR(7) /* Timer/Counter1 Compare Match B */ +-#define TIM1_OVF_vect_num 8 +-#define TIM1_OVF_vect _VECTOR(8) /* Timer/Counter1 Overflow */ +-#define TIM0_COMPA_vect_num 9 +-#define TIM0_COMPA_vect _VECTOR(9) /* Timer/Counter0 Compare Match A */ +-#define TIM0_COMPB_vect_num 10 +-#define TIM0_COMPB_vect _VECTOR(10) /* Timer/Counter0 Compare Match B */ +-#define TIM0_OVF_vect_num 11 +-#define TIM0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ +-#define ANA_COMP_vect_num 12 +-#define ANA_COMP_vect _VECTOR(12) /* Analog Comparator */ +-#define ADC_ADC_vect_num 13 +-#define ADC_ADC_vect _VECTOR(13) /* Conversion Complete */ +-#define TWI_SLAVE_vect_num 14 +-#define TWI_SLAVE_vect _VECTOR(14) /* Two-Wire Interface */ +-#define SPI_vect_num 15 +-#define SPI_vect _VECTOR(15) /* Serial Peripheral Interface */ +-#define QTRIP_vect_num 16 +-#define QTRIP_vect _VECTOR(16) /* Touch Sensing */ +- +-#define _VECTOR_SIZE 2 /* Size of individual vector. */ +-#define _VECTORS_SIZE (17 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (64) +-#define RAMSTART (0x40) +-#define RAMSIZE (256) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x0) +-#define E2PAGESIZE (0) +-#define FLASHEND (0xFFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 0 +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x92 +-#define SIGNATURE_2 0x0E +- +- +-/* Device Pin Definitions */ +-#define ADC6_DDR DDRCINT +-#define ADC6_PORT PORTCINT +-#define ADC6_PIN PINCINT +-#define ADC6_BIT INT6 +- +-#define ADC5_DDR DDRCINT +-#define ADC5_PORT PORTCINT +-#define ADC5_PIN PINCINT +-#define ADC5_BIT INT5 +- +-#define OC0B_DDR DDRCINT +-#define OC0B_PORT PORTCINT +-#define OC0B_PIN PINCINT +-#define OC0B_BIT INT5 +- +-#define ADC4_DDR DDRCINT +-#define ADC4_PORT PORTCINT +-#define ADC4_PIN PINCINT +-#define ADC4_BIT INT4 +- +-#define T0_DDR DDRCINT +-#define T0_PORT PORTCINT +-#define T0_PIN PINCINT +-#define T0_BIT INT4 +- +-#define ADC3_DDR DDRPCINT +-#define ADC3_PORT PORTPCINT +-#define ADC3_PIN PINPCINT +-#define ADC3_BIT PCINT3 +- +-#define ADC2_DDR DDRPCINT +-#define ADC2_PORT PORTPCINT +-#define ADC2_PIN PINPCINT +-#define ADC2_BIT PCINT2 +- +-#define AIN1_DDR DDRPCINT +-#define AIN1_PORT PORTPCINT +-#define AIN1_PIN PINPCINT +-#define AIN1_BIT PCINT2 +- +-#define ADC1_DDR DDRCINT +-#define ADC1_PORT PORTCINT +-#define ADC1_PIN PINCINT +-#define ADC1_BIT INT1 +- +-#define AIN0_DDR DDRCINT +-#define AIN0_PORT PORTCINT +-#define AIN0_PIN PINCINT +-#define AIN0_BIT INT1 +- +-#define ADC0_DDR DDRCINT +-#define ADC0_PORT PORTCINT +-#define ADC0_PIN PINCINT +-#define ADC0_BIT INT0 +- +-#define CLKI_DDR DDRCINT1 +-#define CLKI_PORT PORTCINT1 +-#define CLKI_PIN PINCINT1 +-#define CLKI_BIT INT17 +- +-#define SDA_DDR DDRMOSI +-#define SDA_PORT PORTMOSI +-#define SDA_PIN PINMOSI +-#define SDA_BIT MOSI +- +-#define PCINT16_DDR DDRMOSI +-#define PCINT16_PORT PORTMOSI +-#define PCINT16_PIN PINMOSI +-#define PCINT16_BIT MOSI +- +-#define PCINT15_DDR DDRRESET +-#define PCINT15_PORT PORTRESET +-#define PCINT15_PIN PINRESET +-#define PCINT15_BIT RESET +- +-#define CLKO_DDR DDRINT +-#define CLKO_PORT PORTINT +-#define CLKO_PIN PININT +-#define CLKO_BIT INT0 +- +-#define MISO_DDR DDRINT +-#define MISO_PORT PORTINT +-#define MISO_PIN PININT +-#define MISO_BIT INT0 +- +-#define PCINT14_DDR DDRINT +-#define PCINT14_PORT PORTINT +-#define PCINT14_PIN PININT +-#define PCINT14_BIT INT0 +- +-#define SCL_DDR DDRSCK +-#define SCL_PORT PORTSCK +-#define SCL_PIN PINSCK +-#define SCL_BIT SCK +- +-#define ICP1_DDR DDRSCK +-#define ICP1_PORT PORTSCK +-#define ICP1_PIN PINSCK +-#define ICP1_BIT SCK +- +-#define T1_DDR DDRSCK +-#define T1_PORT PORTSCK +-#define T1_PIN PINSCK +-#define T1_BIT SCK +- +-#define PCINT13_DDR DDRSCK +-#define PCINT13_PORT PORTSCK +-#define PCINT13_PIN PINSCK +-#define PCINT13_BIT SCK +- +-#define SS_DDR DDROC0A +-#define SS_PORT PORTOC0A +-#define SS_PIN PINOC0A +-#define SS_BIT OC0A +- +-#define PCINT12_DDR DDROC0A +-#define PCINT12_PORT PORTOC0A +-#define PCINT12_PIN PINOC0A +-#define PCINT12_BIT OC0A +- +-#define PCINT11_DDR DDRADC1 +-#define PCINT11_PORT PORTADC1 +-#define PCINT11_PIN PINADC1 +-#define PCINT11_BIT ADC11 +- +-#define PCINT10_DDR DDRADC1 +-#define PCINT10_PORT PORTADC1 +-#define PCINT10_PIN PINADC1 +-#define PCINT10_BIT ADC10 +- +-#define PCINT9_DDR DDRADC9 +-#define PCINT9_PORT PORTADC9 +-#define PCINT9_PIN PINADC9 +-#define PCINT9_BIT ADC9 +- +-#define PCINT8_DDR DDRADC +-#define PCINT8_PORT PORTADC +-#define PCINT8_PIN PINADC +-#define PCINT8_BIT ADC8 +- +-#define PCINT7_DDR DDRADC +-#define PCINT7_PORT PORTADC +-#define PCINT7_PIN PINADC +-#define PCINT7_BIT ADC7 +- +-#endif /* _AVR_ATtiny40_H_ */ +- ++/* Copyright (c) 2010 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn40.h 2435 2014-08-11 10:31:52Z joerg_wunsch $ */ ++ ++/* avr/iotn40.h - definitions for ATtiny40 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn40.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATtiny40_H_ ++#define _AVR_ATtiny40_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++#define PINA4 4 ++#define PINA5 5 ++#define PINA6 6 ++#define PINA7 7 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++#define DDA4 4 ++#define DDA5 5 ++#define DDA6 6 ++#define DDA7 7 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA0 0 ++#define PORTA1 1 ++#define PORTA2 2 ++#define PORTA3 3 ++#define PORTA4 4 ++#define PORTA5 5 ++#define PORTA6 6 ++#define PORTA7 7 ++ ++#define PUEA _SFR_IO8(0x03) ++#define PUEA0 0 ++#define PUEA1 1 ++#define PUEA2 2 ++#define PUEA3 3 ++#define PUEA4 4 ++#define PUEA5 5 ++#define PUEA6 6 ++#define PUEA7 7 ++ ++#define PINB _SFR_IO8(0x04) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++ ++#define DDRB _SFR_IO8(0x05) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++ ++#define PORTB _SFR_IO8(0x06) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++ ++#define PUEB _SFR_IO8(0x07) ++#define PUEB0 0 ++#define PUEB1 1 ++#define PUEB2 2 ++#define PUEB3 3 ++ ++#define PORTCR _SFR_IO8(0x08) ++#define BBMA 0 ++#define BBMB 1 ++#define BBMC 2 ++#define ADC8D 4 ++#define ADC9D 5 ++#define ADC10D 6 ++#define ADC11D 7 ++ ++#define PCMSK0 _SFR_IO8(0x09) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_IO8(0x0A) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++ ++#define GIFR _SFR_IO8(0x0B) ++#define INTF0 0 ++#define PCIF0 4 ++#define PCIF1 5 ++#define PCIF2 6 ++ ++#define GIMSK _SFR_IO8(0x0C) ++#define INT0 0 ++#define PCIE0 4 ++#define PCIE1 5 ++#define PCIE2 6 ++ ++#define DIDR0 _SFR_IO8(0x0D) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x0E) ++#endif ++#define ADCW _SFR_IO16(0x0E) ++ ++#define ADCL _SFR_IO8(0x0E) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_IO8(0x0F) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADMUX _SFR_IO8(0x10) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define REFS 6 ++ ++#define ADCSRB _SFR_IO8(0x11) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ADLAR 3 ++ ++#define ADCSRA _SFR_IO8(0x12) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ACSRB _SFR_IO8(0x13) ++#define ACME 2 ++#define HLEV 6 ++#define HSEL 7 ++ ++#define ACSRA _SFR_IO8(0x14) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define OCR0B _SFR_IO8(0x15) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define OCR0A _SFR_IO8(0x16) ++#define OCR0_0 0 ++#define OCR0_1 1 ++#define OCR0_2 2 ++#define OCR0_3 3 ++#define OCR0_4 4 ++#define OCR0_5 5 ++#define OCR0_6 6 ++#define OCR0_7 7 ++ ++#define TCNT0 _SFR_IO8(0x17) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define TCCR0B _SFR_IO8(0x18) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define PSR 4 ++#define TSM 5 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCCR0A _SFR_IO8(0x19) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define PCMSK2 _SFR_IO8(0x1A) ++#define PCINT12 0 ++#define PCINT13 1 ++#define PCINT14 2 ++#define PCINT15 3 ++#define PCINT16 4 ++#define PCINT17 5 ++ ++#define PINC _SFR_IO8(0x1B) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++#define PINC5 5 ++ ++#define DDRC _SFR_IO8(0x1C) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++ ++#define PORTC _SFR_IO8(0x1D) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC3 3 ++#define PORTC4 4 ++#define PORTC5 5 ++ ++#define PUEC _SFR_IO8(0x1E) ++#define PUEC0 0 ++#define PUEC1 1 ++#define PUEC2 2 ++#define PUEC3 3 ++#define PUEC4 4 ++#define PUEC5 5 ++ ++#define RAMDR _SFR_IO8(0x1F) ++#define RAMDR0 0 ++#define RAMDR1 1 ++#define RAMDR2 2 ++#define RAMDR3 3 ++#define RAMDR4 4 ++#define RAMDR5 5 ++#define RAMDR6 6 ++#define RAMDR7 7 ++ ++#define RAMAR _SFR_IO8(0x20) ++#define RAMAR0 0 ++#define RAMAR1 1 ++#define RAMAR2 2 ++#define RAMAR3 3 ++#define RAMAR4 4 ++#define RAMAR5 5 ++#define RAMAR6 6 ++#define RAMAR7 7 ++ ++#define OCR1B _SFR_IO8(0x21) ++#define OCR1B0 0 ++#define OCR1B1 1 ++#define OCR1B2 2 ++#define OCR1B3 3 ++#define OCR1B4 4 ++#define OCR1B5 5 ++#define OCR1B6 6 ++#define OCR1B7 7 ++ ++#define OCR1A _SFR_IO8(0x22) ++#define OCR1A0 0 ++#define OCR1A1 1 ++#define OCR1A2 2 ++#define OCR1A3 3 ++#define OCR1A4 4 ++#define OCR1A5 5 ++#define OCR1A6 6 ++#define OCR1A7 7 ++ ++#define TCNT1L _SFR_IO8(0x23) ++#define TCNT1_0 0 ++#define TCNT1_1 1 ++#define TCNT1_2 2 ++#define TCNT1_3 3 ++#define TCNT1_4 4 ++#define TCNT1_5 5 ++#define TCNT1_6 6 ++#define TCNT1_7 7 ++ ++#define TCCR1A _SFR_IO8(0x24) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define CTC1 3 ++#define ICES1 4 ++#define ICNC1 5 ++#define ICEN1 6 ++#define TCW1 7 ++ ++#define TIFR _SFR_IO8(0x25) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++#define TOV1 3 ++#define OCF1A 4 ++#define OCF1B 5 ++#define ICF1 7 ++ ++#define TIMSK _SFR_IO8(0x26) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++#define TOIE1 3 ++#define OCIE1A 4 ++#define OCIE1B 5 ++#define ICIE1 7 ++ ++#define TCNT1H _SFR_IO8(0x27) ++#define TCNT1_8 0 ++#define TCNT1_9 1 ++#define TCNT1_10 2 ++#define TCNT1_11 3 ++#define TCNT1_12 4 ++#define TCNT1_13 5 ++#define TCNT1_14 6 ++#define TCNT1_15 7 ++ ++#define TWSD _SFR_IO8(0x28) ++#define TWSD0 0 ++#define TWSD1 1 ++#define TWSD2 2 ++#define TWSD3 3 ++#define TWSD4 4 ++#define TWSD5 5 ++#define TWSD6 6 ++#define TWSD7 7 ++ ++#define TWSAM _SFR_IO8(0x29) ++#define TWAE 0 ++#define TWSAM1 1 ++#define TWSAM2 2 ++#define TWSAM3 3 ++#define TWSAM4 4 ++#define TWSAM5 5 ++#define TWSAM6 6 ++#define TWSAM7 7 ++ ++#define TWSA _SFR_IO8(0x2A) ++#define TWSA0 0 ++#define TWSA1 1 ++#define TWSA2 2 ++#define TWSA3 3 ++#define TWSA4 4 ++#define TWSA5 5 ++#define TWSA6 6 ++#define TWSA7 7 ++ ++#define TWSSRA _SFR_IO8(0x2B) ++#define TWAS 0 ++#define TWDIR 1 ++#define TWBE 2 ++#define TWC 3 ++#define TWRA 4 ++#define TWCH 5 ++#define TWASIF 6 ++#define TWDIF 7 ++ ++#define TWSCRB _SFR_IO8(0x2C) ++#define TWCMD0 0 ++#define TWCMD1 1 ++#define TWAA 2 ++ ++#define TWSCRA _SFR_IO8(0x2D) ++#define TWSME 0 ++#define TWPME 1 ++#define TWSIE 2 ++#define TWEN 3 ++#define TWASIE 4 ++#define TWDIE 5 ++#define TWSHE 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++#define SPSR _SFR_IO8(0x2F) ++ ++#define SPCR _SFR_IO8(0x30) ++ ++#define WDTCSR _SFR_IO8(0x31) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define NVMCSR _SFR_IO8(0x32) ++#define NVMBSY 7 ++ ++#define NVMCMD _SFR_IO8(0x33) ++#define NVMCMD0 0 ++#define NVMCMD1 1 ++#define NVMCMD2 2 ++#define NVMCMD3 3 ++#define NVMCMD4 4 ++#define NVMCMD5 5 ++ ++#define QTCSR _SFR_IO8(0x34) ++ ++#define PRR _SFR_IO8(0x35) ++#define PRADC 0 ++#define PRTIM0 1 ++#define PRTIM1 2 ++#define PRSPI 3 ++#define PRTWI 4 ++ ++#define CLKPSR _SFR_IO8(0x36) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++ ++#define CLKMSR _SFR_IO8(0x37) ++#define CLKMS0 0 ++#define CLKMS1 1 ++ ++#define DWDR _SFR_IO8(0x38) ++ ++#define OSCCAL _SFR_IO8(0x39) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define MCUCR _SFR_IO8(0x3A) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++#define BODS 4 ++#define ISC00 6 ++#define ISC01 7 ++ ++#define RSTFLR _SFR_IO8(0x3B) ++#define PORF 0 ++#define EXTRF 1 ++#define WDRF 3 ++ ++#define CCP _SFR_IO8(0x3C) ++#define CCP0 0 ++#define CCP1 1 ++#define CCP2 2 ++#define CCP3 3 ++#define CCP4 4 ++#define CCP5 5 ++#define CCP6 6 ++#define CCP7 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect_num 3 ++#define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */ ++#define PCINT2_vect_num 4 ++#define PCINT2_vect _VECTOR(4) /* Pin Change Interrupt Request 2 */ ++#define WDT_vect_num 5 ++#define WDT_vect _VECTOR(5) /* Watchdog Time-out */ ++#define TIM1_CAPT_vect_num 6 ++#define TIM1_CAPT_vect _VECTOR(6) /* Timer/Counter1 Input Capture */ ++#define TIM1_COMPA_vect_num 7 ++#define TIM1_COMPA_vect _VECTOR(7) /* Timer/Counter1 Compare Match A */ ++#define TIM1_COMPB_vect_num 8 ++#define TIM1_COMPB_vect _VECTOR(8) /* Timer/Counter1 Compare Match B */ ++#define TIM1_OVF_vect_num 9 ++#define TIM1_OVF_vect _VECTOR(9) /* Timer/Counter1 Overflow */ ++#define TIM0_COMPA_vect_num 10 ++#define TIM0_COMPA_vect _VECTOR(10) /* Timer/Counter0 Compare Match A */ ++#define TIM0_COMPB_vect_num 11 ++#define TIM0_COMPB_vect _VECTOR(11) /* Timer/Counter0 Compare Match B */ ++#define TIM0_OVF_vect_num 12 ++#define TIM0_OVF_vect _VECTOR(12) /* Timer/Counter0 Overflow */ ++#define ANA_COMP_vect_num 13 ++#define ANA_COMP_vect _VECTOR(13) /* Analog Comparator */ ++#define ADC_vect_num 14 ++#define ADC_vect _VECTOR(14) /* Conversion Complete */ ++#define TWI_SLAVE_vect_num 15 ++#define TWI_SLAVE_vect _VECTOR(15) /* Two-Wire Interface */ ++#define SPI_vect_num 16 ++#define SPI_vect _VECTOR(16) /* Serial Peripheral Interface */ ++#define QTRIP_vect_num 17 ++#define QTRIP_vect _VECTOR(17) /* Touch Sensing */ ++ ++#define _VECTOR_SIZE 2 /* Size of individual vector. */ ++#define _VECTORS_SIZE (18 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (64) ++#define RAMSTART (0x40) ++#define RAMSIZE (256) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x0) ++#define E2PAGESIZE (0) ++#define FLASHEND (0xFFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 0 ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x92 ++#define SIGNATURE_2 0x0E ++ ++ ++/* Device Pin Definitions */ ++#define ADC6_DDR DDRCINT ++#define ADC6_PORT PORTCINT ++#define ADC6_PIN PINCINT ++#define ADC6_BIT INT6 ++ ++#define ADC5_DDR DDRCINT ++#define ADC5_PORT PORTCINT ++#define ADC5_PIN PINCINT ++#define ADC5_BIT INT5 ++ ++#define OC0B_DDR DDRCINT ++#define OC0B_PORT PORTCINT ++#define OC0B_PIN PINCINT ++#define OC0B_BIT INT5 ++ ++#define ADC4_DDR DDRCINT ++#define ADC4_PORT PORTCINT ++#define ADC4_PIN PINCINT ++#define ADC4_BIT INT4 ++ ++#define T0_DDR DDRCINT ++#define T0_PORT PORTCINT ++#define T0_PIN PINCINT ++#define T0_BIT INT4 ++ ++#define ADC3_DDR DDRPCINT ++#define ADC3_PORT PORTPCINT ++#define ADC3_PIN PINPCINT ++#define ADC3_BIT PCINT3 ++ ++#define ADC2_DDR DDRPCINT ++#define ADC2_PORT PORTPCINT ++#define ADC2_PIN PINPCINT ++#define ADC2_BIT PCINT2 ++ ++#define AIN1_DDR DDRPCINT ++#define AIN1_PORT PORTPCINT ++#define AIN1_PIN PINPCINT ++#define AIN1_BIT PCINT2 ++ ++#define ADC1_DDR DDRCINT ++#define ADC1_PORT PORTCINT ++#define ADC1_PIN PINCINT ++#define ADC1_BIT INT1 ++ ++#define AIN0_DDR DDRCINT ++#define AIN0_PORT PORTCINT ++#define AIN0_PIN PINCINT ++#define AIN0_BIT INT1 ++ ++#define ADC0_DDR DDRCINT ++#define ADC0_PORT PORTCINT ++#define ADC0_PIN PINCINT ++#define ADC0_BIT INT0 ++ ++#define CLKI_DDR DDRCINT1 ++#define CLKI_PORT PORTCINT1 ++#define CLKI_PIN PINCINT1 ++#define CLKI_BIT INT17 ++ ++#define SDA_DDR DDRMOSI ++#define SDA_PORT PORTMOSI ++#define SDA_PIN PINMOSI ++#define SDA_BIT MOSI ++ ++#define PCINT16_DDR DDRMOSI ++#define PCINT16_PORT PORTMOSI ++#define PCINT16_PIN PINMOSI ++#define PCINT16_BIT MOSI ++ ++#define PCINT15_DDR DDRRESET ++#define PCINT15_PORT PORTRESET ++#define PCINT15_PIN PINRESET ++#define PCINT15_BIT RESET ++ ++#define CLKO_DDR DDRINT ++#define CLKO_PORT PORTINT ++#define CLKO_PIN PININT ++#define CLKO_BIT INT0 ++ ++#define MISO_DDR DDRINT ++#define MISO_PORT PORTINT ++#define MISO_PIN PININT ++#define MISO_BIT INT0 ++ ++#define PCINT14_DDR DDRINT ++#define PCINT14_PORT PORTINT ++#define PCINT14_PIN PININT ++#define PCINT14_BIT INT0 ++ ++#define SCL_DDR DDRSCK ++#define SCL_PORT PORTSCK ++#define SCL_PIN PINSCK ++#define SCL_BIT SCK ++ ++#define ICP1_DDR DDRSCK ++#define ICP1_PORT PORTSCK ++#define ICP1_PIN PINSCK ++#define ICP1_BIT SCK ++ ++#define T1_DDR DDRSCK ++#define T1_PORT PORTSCK ++#define T1_PIN PINSCK ++#define T1_BIT SCK ++ ++#define PCINT13_DDR DDRSCK ++#define PCINT13_PORT PORTSCK ++#define PCINT13_PIN PINSCK ++#define PCINT13_BIT SCK ++ ++#define SS_DDR DDROC0A ++#define SS_PORT PORTOC0A ++#define SS_PIN PINOC0A ++#define SS_BIT OC0A ++ ++#define PCINT12_DDR DDROC0A ++#define PCINT12_PORT PORTOC0A ++#define PCINT12_PIN PINOC0A ++#define PCINT12_BIT OC0A ++ ++#define PCINT11_DDR DDRADC1 ++#define PCINT11_PORT PORTADC1 ++#define PCINT11_PIN PINADC1 ++#define PCINT11_BIT ADC11 ++ ++#define PCINT10_DDR DDRADC1 ++#define PCINT10_PORT PORTADC1 ++#define PCINT10_PIN PINADC1 ++#define PCINT10_BIT ADC10 ++ ++#define PCINT9_DDR DDRADC9 ++#define PCINT9_PORT PORTADC9 ++#define PCINT9_PIN PINADC9 ++#define PCINT9_BIT ADC9 ++ ++#define PCINT8_DDR DDRADC ++#define PCINT8_PORT PORTADC ++#define PCINT8_PIN PINADC ++#define PCINT8_BIT ADC8 ++ ++#define PCINT7_DDR DDRADC ++#define PCINT7_PORT PORTADC ++#define PCINT7_PIN PINADC ++#define PCINT7_BIT ADC7 ++ ++#endif /* _AVR_ATtiny40_H_ */ ++ +diff --git a/include/avr/iotn4313.h b/include/avr/iotn4313.h +index bdef413..cdc8b5e 100644 +--- a/include/avr/iotn4313.h ++++ b/include/avr/iotn4313.h +@@ -1,769 +1,802 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn4313.h 2035 2009-11-02 02:44:17Z arcanum $ */ +- +-/* avr/iotn4313.h - definitions for ATtiny4313 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn4313.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATtiny4313_H_ +-#define _AVR_ATtiny4313_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define DIDR _SFR_IO8(0x001) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define UBRRH _SFR_IO8(0x002) +-#define UBRR8 0 +-#define UBRR9 1 +-#define UBRR10 2 +-#define UBRR11 3 +- +-#define UCSRC _SFR_IO8(0x003) +-#define UCPOL 0 +-#define UCSZ0 1 +-#define UCSZ1 2 +-#define USBS 3 +-#define UPM0 4 +-#define UPM1 5 +-#define UMSEL 6 +- +-#define PCMSK1 _SFR_IO8(0x004) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +- +-#define PCMSK2 _SFR_IO8(0x005) +-#define PCINT11 0 +-#define PCINT12 1 +-#define PCINT13 2 +-#define PCINT14 3 +-#define PCINT15 4 +-#define PCINT16 5 +-#define PCINT17 6 +- +-#define PRR _SFR_IO8(0x006) +-#define PRUSART 0 +-#define PRUSI 1 +-#define PRTIM0 2 +-#define PRTIM1 3 +- +-#define BODCR _SFR_IO8(0x007) +-#define BPDSE 0 +-#define BPDS 1 +- +-#define ACSR _SFR_IO8(0x008) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define UBRRL _SFR_IO8(0x009) +-#define UBRR0 0 +-#define UBRR1 1 +-#define UBRR2 2 +-#define UBRR3 3 +-#define UBRR4 4 +-#define UBRR5 5 +-#define UBRR6 6 +-#define UBRR7 7 +- +-#define UCSRB _SFR_IO8(0x00A) +-#define TXB8 0 +-#define RXB8 1 +-#define UCSZ2 2 +-#define TXEN 3 +-#define RXEN 4 +-#define UDRIE 5 +-#define TXCIE 6 +-#define RXCIE 7 +- +-#define UCSRA _SFR_IO8(0x00B) +-#define MPCM 0 +-#define U2X 1 +-#define UPE 2 +-#define DOR 3 +-#define FE 4 +-#define UDRE 5 +-#define TXC 6 +-#define RXC 7 +- +-#define UDR _SFR_IO8(0x00C) +-#define UDR0 0 +-#define UDR1 1 +-#define UDR2 2 +-#define UDR3 3 +-#define UDR4 4 +-#define UDR5 5 +-#define UDR6 6 +-#define UDR7 7 +- +-#define USICR _SFR_IO8(0x00D) +-#define USITC 0 +-#define USICLK 1 +-#define USICS0 2 +-#define USICS1 3 +-#define USIWM0 4 +-#define USIWM1 5 +-#define USIOIE 6 +-#define USISIE 7 +- +-#define USISR _SFR_IO8(0x00E) +-#define USICNT0 0 +-#define USICNT1 1 +-#define USICNT2 2 +-#define USICNT3 3 +-#define USIDC 4 +-#define USIPF 5 +-#define USIOIF 6 +-#define USISIF 7 +- +-#define USIDR _SFR_IO8(0x00F) +-#define USIDR0 0 +-#define USIDR1 1 +-#define USIDR2 2 +-#define USIDR3 3 +-#define USIDR4 4 +-#define USIDR5 5 +-#define USIDR6 6 +-#define USIDR7 7 +- +-#define PIND _SFR_IO8(0x010) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +- +-#define DDRD _SFR_IO8(0x011) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +- +-#define PORTD _SFR_IO8(0x012) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +- +-#define GPIOR0 _SFR_IO8(0x013) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define GPIOR1 _SFR_IO8(0x014) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x015) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define PINB _SFR_IO8(0x016) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x017) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x018) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINA _SFR_IO8(0x019) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +- +-#define DDRA _SFR_IO8(0x01A) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +- +-#define PORTA _SFR_IO8(0x01B) +-#define PORTA0 0 +-#define PORTA1 1 +-#define PORTA2 2 +- +-#define EECR _SFR_IO8(0x01C) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x01D) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO8(0x01E) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +- +-#define PCMSK _SFR_IO8(0x020) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define WDTCR _SFR_IO8(0x021) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define TCCR1C _SFR_IO8(0x022) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define GTCCR _SFR_IO8(0x023) +-#define PSR10 0 +- +-#define ICR1 _SFR_IO16(0x024) +- +-#define ICR1L _SFR_IO8(0x024) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_IO8(0x025) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define CLKPR _SFR_IO8(0x026) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define OCR1B _SFR_IO16(0x028) +- +-#define OCR1BL _SFR_IO8(0x028) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_IO8(0x029) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define OCR1A _SFR_IO16(0x02A) +- +-#define OCR1AL _SFR_IO8(0x02A) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_IO8(0x02B) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define TCNT1 _SFR_IO16(0x02C) +- +-#define TCNT1L _SFR_IO8(0x02C) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_IO8(0x02D) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define TCCR1B _SFR_IO8(0x02E) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1A _SFR_IO8(0x02F) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR0A _SFR_IO8(0x030) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define OSCCAL _SFR_IO8(0x031) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +- +-#define TCNT0 _SFR_IO8(0x032) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define TCCR0B _SFR_IO8(0x033) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define MCUSR _SFR_IO8(0x034) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x035) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +-#define SM0 4 +-#define SE 5 +-#define SM1 6 +-#define PUD 7 +- +-#define OCR0A _SFR_IO8(0x036) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define SPMCSR _SFR_IO8(0x037) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define RFLB 3 +-#define CTPB 4 +- +-#define TIFR _SFR_IO8(0x038) +-#define OCF0A 0 +-#define TOV0 1 +-#define OCF0B 2 +-#define ICF1 3 +-#define OCF1B 5 +-#define OCF1A 6 +-#define TOV1 7 +- +-#define TIMSK _SFR_IO8(0x039) +-#define OCIE0A 0 +-#define TOIE0 1 +-#define OCIE0B 2 +-#define ICIE1 3 +-#define OCIE1B 5 +-#define OCIE1A 6 +-#define TOIE1 7 +- +-#define EIFR _SFR_IO8(0x03A) +-#define PCIF 5 +-#define INTF0 6 +-#define INTF1 7 +- +-#define GIMSK _SFR_IO8(0x03B) +-#define PCIE 5 +-#define INT0 6 +-#define INT1 7 +- +-#define OCR0B _SFR_IO8(0x03C) +-#define OCR0_0 0 +-#define OCR0_1 1 +-#define OCR0_2 2 +-#define OCR0_3 3 +-#define OCR0_4 4 +-#define OCR0_5 5 +-#define OCR0_6 6 +-#define OCR0_7 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ +-#define TIMER1_CAPT_vect_num 3 +-#define TIMER1_CAPT_vect _VECTOR(3) /* Timer/Counter1 Capture Event */ +-#define TIMER1_COMPA_vect_num 4 +-#define TIMER1_COMPA_vect _VECTOR(4) /* Timer/Counter1 Compare Match A */ +-#define TIMER1_OVF_vect_num 5 +-#define TIMER1_OVF_vect _VECTOR(5) /* Timer/Counter1 Overflow */ +-#define TIMER0_OVF_vect_num 6 +-#define TIMER0_OVF_vect _VECTOR(6) /* Timer/Counter0 Overflow */ +-#define USART_RX_vect_num 7 +-#define USART_RX_vect _VECTOR(7) /* USART, Rx Complete */ +-#define USART_UDRE_vect_num 8 +-#define USART_UDRE_vect _VECTOR(8) /* USART Data Register Empty */ +-#define USART_TX_vect_num 9 +-#define USART_TX_vect _VECTOR(9) /* USART, Tx Complete */ +-#define ANA_COMP_vect_num 10 +-#define ANA_COMP_vect _VECTOR(10) /* Analog Comparator */ +-#define PCINT_B_vect_num 11 +-#define PCINT_B_vect _VECTOR(11) /* Pin Change Interrupt Request B */ +-#define TIMER1_COMPB_vect_num 12 +-#define TIMER1_COMPB_vect _VECTOR(12) /* */ +-#define TIMER0_COMPA_vect_num 13 +-#define TIMER0_COMPA_vect _VECTOR(13) /* */ +-#define TIMER0_COMPB_vect_num 14 +-#define TIMER0_COMPB_vect _VECTOR(14) /* */ +-#define USI_START_vect_num 15 +-#define USI_START_vect _VECTOR(15) /* USI Start Condition */ +-#define USI_OVERFLOW_vect_num 16 +-#define USI_OVERFLOW_vect _VECTOR(16) /* USI Overflow */ +-#define WDT_OVERFLOW_vect_num 18 +-#define WDT_OVERFLOW_vect _VECTOR(18) /* Watchdog Timer Overflow */ +-#define PCINT_D_vect_num 20 +-#define PCINT_D_vect _VECTOR(20) /* Pin Change Interrupt Request D */ +-#define EEPROM_Ready_vect_num 17 +-#define EEPROM_Ready_vect _VECTOR(17) /* */ +-#define PCINT_A_vect_num 19 +-#define PCINT_A_vect _VECTOR(19) /* Pin Change Interrupt Request A */ +- +-#define _VECTOR_SIZE 2 /* Size of individual vector. */ +-#define _VECTORS_SIZE (21 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (64) +-#define RAMSTART (0x60) +-#define RAMSIZE (256) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0xFF) +-#define E2PAGESIZE (4) +-#define FLASHEND (0xFFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self Programming Enable */ +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x92 +-#define SIGNATURE_2 0x0D +- +- +-/* Device Pin Definitions */ +-#define RXD_DDR DDRD +-#define RXD_PORT PORTD +-#define RXD_PIN PIND +-#define RXD_BIT 0 +- +-#define TXD_DDR DDRD +-#define TXD_PORT PORTD +-#define TXD_PIN PIND +-#define TXD_BIT 1 +- +-#define PA1_DDR DDRXTAL +-#define PA1_PORT PORTXTAL +-#define PA1_PIN PINXTAL +-#define PA1_BIT XTAL2 +- +-#define PA0_DDR DDRXTAL +-#define PA0_PORT PORTXTAL +-#define PA0_PIN PINXTAL +-#define PA0_BIT XTAL1 +- +-#define INT0_DDR DDRD +-#define INT0_PORT PORTD +-#define INT0_PIN PIND +-#define INT0_BIT 2 +- +-#define XCK_DDR DDRD +-#define XCK_PORT PORTD +-#define XCK_PIN PIND +-#define XCK_BIT 2 +- +-#define CKOUT_DDR DDRD +-#define CKOUT_PORT PORTD +-#define CKOUT_PIN PIND +-#define CKOUT_BIT 2 +- +-#define INT1_DDR DDRD +-#define INT1_PORT PORTD +-#define INT1_PIN PIND +-#define INT1_BIT 3 +- +-#define T0_DDR DDRD +-#define T0_PORT PORTD +-#define T0_PIN PIND +-#define T0_BIT 4 +- +-#define T1_DDR DDRD +-#define T1_PORT PORTD +-#define T1_PIN PIND +-#define T1_BIT 5 +- +-#define OC0B_DDR DDRD +-#define OC0B_PORT PORTD +-#define OC0B_PIN PIND +-#define OC0B_BIT 5 +- +-#define ICP_DDR DDRD +-#define ICP_PORT PORTD +-#define ICP_PIN PIND +-#define ICP_BIT 6 +- +-#define AIN0_DDR DDRB +-#define AIN0_PORT PORTB +-#define AIN0_PIN PINB +-#define AIN0_BIT 0 +- +-#define AIN1_DDR DDRB +-#define AIN1_PORT PORTB +-#define AIN1_PIN PINB +-#define AIN1_BIT 1 +- +-#define OC0A_DDR DDRB +-#define OC0A_PORT PORTB +-#define OC0A_PIN PINB +-#define OC0A_BIT 2 +- +-#define OC1A_DDR DDRB +-#define OC1A_PORT PORTB +-#define OC1A_PIN PINB +-#define OC1A_BIT 3 +- +-#define OC1B_DDR DDRB +-#define OC1B_PORT PORTB +-#define OC1B_PIN PINB +-#define OC1B_BIT 4 +- +-#define MOSI_DDR DDRB +-#define MOSI_PORT PORTB +-#define MOSI_PIN PINB +-#define MOSI_BIT 5 +- +-#define DI_DDR DDRB +-#define DI_PORT PORTB +-#define DI_PIN PINB +-#define DI_BIT 5 +- +-#define MISO_DDR DDRB +-#define MISO_PORT PORTB +-#define MISO_PIN PINB +-#define MISO_BIT 6 +- +-#define DO_DDR DDRB +-#define DO_PORT PORTB +-#define DO_PIN PINB +-#define DO_BIT 6 +- +-#define SCK_DDR DDRB +-#define SCK_PORT PORTB +-#define SCK_PIN PINB +-#define SCK_BIT 7 +- +-#define SCL_DDR DDRB +-#define SCL_PORT PORTB +-#define SCL_PIN PINB +-#define SCL_BIT 7 +- +-#endif /* _AVR_ATtiny4313_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn4313.h 2412 2014-03-20 11:21:20Z pitchumani $ */ ++ ++/* avr/iotn4313.h - definitions for ATtiny4313 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn4313.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATtiny4313_H_ ++#define _AVR_ATtiny4313_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define USIBR _SFR_IO8(0x000) ++#define USIBR0 0 ++#define USIBR1 1 ++#define USIBR2 2 ++#define USIBR3 3 ++#define USIBR4 4 ++#define USIBR5 5 ++#define USIBR6 6 ++#define USIBR7 7 ++ ++#define DIDR _SFR_IO8(0x001) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define UBRRH _SFR_IO8(0x002) ++#define UBRR8 0 ++#define UBRR9 1 ++#define UBRR10 2 ++#define UBRR11 3 ++ ++#define UCSRC _SFR_IO8(0x003) ++#define UCPOL 0 ++#define UCSZ0 1 ++#define UCSZ1 2 ++#define USBS 3 ++#define UPM0 4 ++#define UPM1 5 ++#define UMSEL0 6 ++#define UMSEL1 7 ++ ++/* When in MSPIM mode */ ++#define UCPHA 1 ++#define UDORD 2 ++ ++#define PCMSK1 _SFR_IO8(0x004) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++ ++#define PCMSK2 _SFR_IO8(0x005) ++#define PCINT11 0 ++#define PCINT12 1 ++#define PCINT13 2 ++#define PCINT14 3 ++#define PCINT15 4 ++#define PCINT16 5 ++#define PCINT17 6 ++ ++#define PRR _SFR_IO8(0x006) ++#define PRUSART 0 ++#define PRUSI 1 ++#define PRTIM0 2 ++#define PRTIM1 3 ++ ++#define BODCR _SFR_IO8(0x007) ++#define BPDSE 0 ++#define BPDS 1 ++ ++#define ACSR _SFR_IO8(0x008) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define UBRRL _SFR_IO8(0x009) ++#define UBRR0 0 ++#define UBRR1 1 ++#define UBRR2 2 ++#define UBRR3 3 ++#define UBRR4 4 ++#define UBRR5 5 ++#define UBRR6 6 ++#define UBRR7 7 ++ ++#define UCSRB _SFR_IO8(0x00A) ++#define TXB8 0 ++#define RXB8 1 ++#define UCSZ2 2 ++#define TXEN 3 ++#define RXEN 4 ++#define UDRIE 5 ++#define TXCIE 6 ++#define RXCIE 7 ++ ++#define UCSRA _SFR_IO8(0x00B) ++#define MPCM 0 ++#define U2X 1 ++#define UPE 2 ++#define DOR 3 ++#define FE 4 ++#define UDRE 5 ++#define TXC 6 ++#define RXC 7 ++ ++#define UDR _SFR_IO8(0x00C) ++#define UDR0 0 ++#define UDR1 1 ++#define UDR2 2 ++#define UDR3 3 ++#define UDR4 4 ++#define UDR5 5 ++#define UDR6 6 ++#define UDR7 7 ++ ++#define USICR _SFR_IO8(0x00D) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_IO8(0x00E) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_IO8(0x00F) ++#define USIDR0 0 ++#define USIDR1 1 ++#define USIDR2 2 ++#define USIDR3 3 ++#define USIDR4 4 ++#define USIDR5 5 ++#define USIDR6 6 ++#define USIDR7 7 ++ ++#define PIND _SFR_IO8(0x010) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++ ++#define DDRD _SFR_IO8(0x011) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++ ++#define PORTD _SFR_IO8(0x012) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++ ++#define GPIOR0 _SFR_IO8(0x013) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define GPIOR1 _SFR_IO8(0x014) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x015) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define PINB _SFR_IO8(0x016) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x017) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x018) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINA _SFR_IO8(0x019) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++ ++#define DDRA _SFR_IO8(0x01A) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++ ++#define PORTA _SFR_IO8(0x01B) ++#define PORTA0 0 ++#define PORTA1 1 ++#define PORTA2 2 ++ ++#define EECR _SFR_IO8(0x01C) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x01D) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO8(0x01E) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++ ++#define PCMSK _SFR_IO8(0x020) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define WDTCR _SFR_IO8(0x021) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define TCCR1C _SFR_IO8(0x022) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define GTCCR _SFR_IO8(0x023) ++#define PSR10 0 ++ ++#define ICR1 _SFR_IO16(0x024) ++ ++#define ICR1L _SFR_IO8(0x024) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_IO8(0x025) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define CLKPR _SFR_IO8(0x026) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define OCR1B _SFR_IO16(0x028) ++ ++#define OCR1BL _SFR_IO8(0x028) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_IO8(0x029) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define OCR1A _SFR_IO16(0x02A) ++ ++#define OCR1AL _SFR_IO8(0x02A) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_IO8(0x02B) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define TCNT1 _SFR_IO16(0x02C) ++ ++#define TCNT1L _SFR_IO8(0x02C) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_IO8(0x02D) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define TCCR1B _SFR_IO8(0x02E) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1A _SFR_IO8(0x02F) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR0A _SFR_IO8(0x030) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define OSCCAL _SFR_IO8(0x031) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++ ++#define TCNT0 _SFR_IO8(0x032) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define TCCR0B _SFR_IO8(0x033) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define MCUSR _SFR_IO8(0x034) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x035) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++#define SM0 4 ++#define SE 5 ++#define SM1 6 ++#define PUD 7 ++ ++#define OCR0A _SFR_IO8(0x036) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define SPMCSR _SFR_IO8(0x037) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define RFLB 3 ++#define CTPB 4 ++#define RSIG 5 ++ ++#define TIFR _SFR_IO8(0x038) ++#define OCF0A 0 ++#define TOV0 1 ++#define OCF0B 2 ++#define ICF1 3 ++#define OCF1B 5 ++#define OCF1A 6 ++#define TOV1 7 ++ ++#define TIMSK _SFR_IO8(0x039) ++#define OCIE0A 0 ++#define TOIE0 1 ++#define OCIE0B 2 ++#define ICIE1 3 ++#define OCIE1B 5 ++#define OCIE1A 6 ++#define TOIE1 7 ++ ++#define EIFR _SFR_IO8(0x03A) ++#define GIFR _SFR_IO8(0x03A) ++#define PCIF1 3 ++#define PCIF2 4 ++#define PCIF0 5 ++#define INTF0 6 ++#define INTF1 7 ++ ++#define GIMSK _SFR_IO8(0x03B) ++#define PCIE1 3 ++#define PCIE2 4 ++#define PCIE0 5 ++#define INT0 6 ++#define INT1 7 ++ ++#define OCR0B _SFR_IO8(0x03C) ++#define OCR0_0 0 ++#define OCR0_1 1 ++#define OCR0_2 2 ++#define OCR0_3 3 ++#define OCR0_4 4 ++#define OCR0_5 5 ++#define OCR0_6 6 ++#define OCR0_7 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ ++#define TIMER1_CAPT_vect_num 3 ++#define TIMER1_CAPT_vect _VECTOR(3) /* Timer/Counter1 Capture Event */ ++#define TIMER1_COMPA_vect_num 4 ++#define TIMER1_COMPA_vect _VECTOR(4) /* Timer/Counter1 Compare Match A */ ++#define TIMER1_OVF_vect_num 5 ++#define TIMER1_OVF_vect _VECTOR(5) /* Timer/Counter1 Overflow */ ++#define TIMER0_OVF_vect_num 6 ++#define TIMER0_OVF_vect _VECTOR(6) /* Timer/Counter0 Overflow */ ++#define USART0_RX_vect_num 7 ++#define USART0_RX_vect _VECTOR(7) /* USART, Rx Complete */ ++#define USART_RX_vect_num 7 ++#define USART_RX_vect _VECTOR(7) /* alias */ ++#define USART0_UDRE_vect_num 8 ++#define USART0_UDRE_vect _VECTOR(8) /* USART Data Register Empty */ ++#define USART_UDRE_vect_num 8 ++#define USART_UDRE_vect _VECTOR(8) /* alias */ ++#define USART0_TX_vect_num 9 ++#define USART0_TX_vect _VECTOR(9) /* USART, Tx Complete */ ++#define USART_TX_vect_num 9 ++#define USART_TX_vect _VECTOR(9) /* alias */ ++#define ANA_COMP_vect_num 10 ++#define ANA_COMP_vect _VECTOR(10) /* Analog Comparator */ ++#define PCINT0_vect_num 11 ++#define PCINT0_vect _VECTOR(11) /* Pin Change Interrupt Request 0 */ ++#define PCINT_B_vect_num 11 ++#define PCINT_B_vect _VECTOR(11) /* alias */ ++#define TIMER1_COMPB_vect_num 12 ++#define TIMER1_COMPB_vect _VECTOR(12) /* */ ++#define TIMER0_COMPA_vect_num 13 ++#define TIMER0_COMPA_vect _VECTOR(13) /* */ ++#define TIMER0_COMPB_vect_num 14 ++#define TIMER0_COMPB_vect _VECTOR(14) /* */ ++#define USI_START_vect_num 15 ++#define USI_START_vect _VECTOR(15) /* USI Start Condition */ ++#define USI_OVERFLOW_vect_num 16 ++#define USI_OVERFLOW_vect _VECTOR(16) /* USI Overflow */ ++#define EEPROM_Ready_vect_num 17 ++#define EEPROM_Ready_vect _VECTOR(17) /* EEPROM Ready */ ++#define WDT_OVERFLOW_vect_num 18 ++#define WDT_OVERFLOW_vect _VECTOR(18) /* Watchdog Timer Overflow */ ++#define PCINT1_vect_num 19 ++#define PCINT1_vect _VECTOR(19) /* Pin Change Interrupt Request 1 */ ++#define PCINT_A_vect_num 19 ++#define PCINT_A_vect _VECTOR(19) /* alias */ ++#define PCINT2_vect_num 20 ++#define PCINT2_vect _VECTOR(20) /* Pin Change Interrupt Request 2 */ ++#define PCINT_D_vect_num 20 ++#define PCINT_D_vect _VECTOR(20) /* alias */ ++ ++#define _VECTOR_SIZE 2 /* Size of individual vector. */ ++#define _VECTORS_SIZE (21 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (64) ++#define RAMSTART (0x60) ++#define RAMSIZE (256) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0xFF) ++#define E2PAGESIZE (4) ++#define FLASHEND (0xFFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL0) ++ ++/* High Fuse Byte */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(0) /* External reset disable */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(3) /* Brown-out Detector trigger level */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_EESAVE (unsigned char)~_BV(6) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_DWEN (unsigned char)~_BV(7) /* debugWIRE Enable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self Programming Enable */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x92 ++#define SIGNATURE_2 0x0D ++ ++ ++/* Device Pin Definitions */ ++#define RXD_DDR DDRD ++#define RXD_PORT PORTD ++#define RXD_PIN PIND ++#define RXD_BIT 0 ++ ++#define TXD_DDR DDRD ++#define TXD_PORT PORTD ++#define TXD_PIN PIND ++#define TXD_BIT 1 ++ ++#define PA1_DDR DDRXTAL ++#define PA1_PORT PORTXTAL ++#define PA1_PIN PINXTAL ++#define PA1_BIT XTAL2 ++ ++#define PA0_DDR DDRXTAL ++#define PA0_PORT PORTXTAL ++#define PA0_PIN PINXTAL ++#define PA0_BIT XTAL1 ++ ++#define INT0_DDR DDRD ++#define INT0_PORT PORTD ++#define INT0_PIN PIND ++#define INT0_BIT 2 ++ ++#define XCK_DDR DDRD ++#define XCK_PORT PORTD ++#define XCK_PIN PIND ++#define XCK_BIT 2 ++ ++#define CKOUT_DDR DDRD ++#define CKOUT_PORT PORTD ++#define CKOUT_PIN PIND ++#define CKOUT_BIT 2 ++ ++#define INT1_DDR DDRD ++#define INT1_PORT PORTD ++#define INT1_PIN PIND ++#define INT1_BIT 3 ++ ++#define T0_DDR DDRD ++#define T0_PORT PORTD ++#define T0_PIN PIND ++#define T0_BIT 4 ++ ++#define T1_DDR DDRD ++#define T1_PORT PORTD ++#define T1_PIN PIND ++#define T1_BIT 5 ++ ++#define OC0B_DDR DDRD ++#define OC0B_PORT PORTD ++#define OC0B_PIN PIND ++#define OC0B_BIT 5 ++ ++#define ICP_DDR DDRD ++#define ICP_PORT PORTD ++#define ICP_PIN PIND ++#define ICP_BIT 6 ++ ++#define AIN0_DDR DDRB ++#define AIN0_PORT PORTB ++#define AIN0_PIN PINB ++#define AIN0_BIT 0 ++ ++#define AIN1_DDR DDRB ++#define AIN1_PORT PORTB ++#define AIN1_PIN PINB ++#define AIN1_BIT 1 ++ ++#define OC0A_DDR DDRB ++#define OC0A_PORT PORTB ++#define OC0A_PIN PINB ++#define OC0A_BIT 2 ++ ++#define OC1A_DDR DDRB ++#define OC1A_PORT PORTB ++#define OC1A_PIN PINB ++#define OC1A_BIT 3 ++ ++#define OC1B_DDR DDRB ++#define OC1B_PORT PORTB ++#define OC1B_PIN PINB ++#define OC1B_BIT 4 ++ ++#define MOSI_DDR DDRB ++#define MOSI_PORT PORTB ++#define MOSI_PIN PINB ++#define MOSI_BIT 5 ++ ++#define DI_DDR DDRB ++#define DI_PORT PORTB ++#define DI_PIN PINB ++#define DI_BIT 5 ++ ++#define MISO_DDR DDRB ++#define MISO_PORT PORTB ++#define MISO_PIN PINB ++#define MISO_BIT 6 ++ ++#define DO_DDR DDRB ++#define DO_PORT PORTB ++#define DO_PIN PINB ++#define DO_BIT 6 ++ ++#define SCK_DDR DDRB ++#define SCK_PORT PORTB ++#define SCK_PIN PINB ++#define SCK_BIT 7 ++ ++#define SCL_DDR DDRB ++#define SCL_PORT PORTB ++#define SCL_PIN PINB ++#define SCL_BIT 7 ++ ++#endif /* _AVR_ATtiny4313_H_ */ ++ +diff --git a/include/avr/iotn43u.h b/include/avr/iotn43u.h +index 42f00cb..ed4a343 100644 +--- a/include/avr/iotn43u.h ++++ b/include/avr/iotn43u.h +@@ -1,593 +1,594 @@ +-/* Copyright (c) 2007 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. +-*/ +- +-/* $Id: iotn43u.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* avr/iotn43u.h - definitions for ATtiny43U */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn43u.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_IOTN43U_H_ +-#define _AVR_IOTN43U_H_ 1 +- +-/* Registers and associated bit numbers */ +- +-#define PRR _SFR_IO8(0x00) +-#define PRADC 0 +-#define PRUSI 1 +-#define PRTIM0 2 +-#define PRTIM1 3 +- +-#define DIDR0 _SFR_IO8(0x01) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define AIN0D 4 +-#define AIN1D 5 +- +-/* Reserved [0x02] */ +- +-#define ADCSRB _SFR_IO8(0x03) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ADLAR 4 +-#define ACME 6 +- +-#ifndef _ASSEMBLER_ +-#define ADC _SFR_IO16(0x04) +-#endif +-#define ADCW _SFR_IO16(0x04) +- +-#define ADCL _SFR_IO8(0x04) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_IO8(0x05) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_IO8(0x06) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADMUX _SFR_IO8(0x07) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define REFS0 6 +- +-#define ACSR _SFR_IO8(0x08) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-/* Reserved [0x09], [0x0A] */ +- +-#define TIFR1 _SFR_IO8(0x0B) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +- +-#define TIMSK1 _SFR_IO8(0x0C) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +- +-#define USICR _SFR_IO8(0x0D) +-#define USITC 0 +-#define USICLK 1 +-#define USICS0 2 +-#define USICS1 3 +-#define USIWM0 4 +-#define USIWM1 5 +-#define USIOIE 6 +-#define USISIE 7 +- +-#define USISR _SFR_IO8(0x0E) +-#define USICNT0 0 +-#define USICNT1 1 +-#define USICNT2 2 +-#define USICNT3 3 +-#define USIDC 4 +-#define USIPF 5 +-#define USIOIF 6 +-#define USISIF 7 +- +-#define USIDR _SFR_IO8(0x0F) +-#define USIDR0 0 +-#define USIDR1 1 +-#define USIDR2 2 +-#define USIDR3 3 +-#define USIDR4 4 +-#define USIDR5 5 +-#define USIDR6 6 +-#define USIDR7 7 +- +-#define USIBR _SFR_IO8(0x10) +-#define USIBR0 0 +-#define USIBR1 1 +-#define USIBR2 2 +-#define USIBR3 3 +-#define USIBR4 4 +-#define USIBR5 5 +-#define USIBR6 6 +-#define USIBR7 7 +- +-/* Reserved [0x11] */ +- +-#define PCMSK0 _SFR_IO8(0x12) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define GPIOR0 _SFR_IO8(0x13) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define GPIOR1 _SFR_IO8(0x14) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x15) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define PINB _SFR_IO8(0x16) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x17) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x18) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINA _SFR_IO8(0x19) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +-#define PINA4 4 +-#define PINA5 5 +-#define PINA6 6 +-#define PINA7 7 +- +-#define DDRA _SFR_IO8(0x1A) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +-#define DDA4 4 +-#define DDA5 5 +-#define DDA6 6 +-#define DDA7 7 +- +-#define PORTA _SFR_IO8(0x1B) +-#define PORTA0 0 +-#define PORTA1 1 +-#define PORTA2 2 +-#define PORTA3 3 +-#define PORTA4 4 +-#define PORTA5 5 +-#define PORTA6 6 +-#define PORTA7 7 +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEARL _SFR_IO8(0x1E) +- +-/* Reserved [0x1F] */ +- +-#define PCMSK1 _SFR_IO8(0x20) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +- +-#define WDTCSR _SFR_IO8(0x21) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-/* Reserved [0x22] */ +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSR10 0 +-#define TSM 7 +- +-/* Reserved [0x24], [0x25] */ +- +-#define CLKPR _SFR_IO8(0x26) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-/* Reserved [0x27],[0x28],[0x29],[0x2A] */ +- +-#define OCR1B _SFR_IO8(0x2B) +-#define OCR1B_0 0 +-#define OCR1B_1 1 +-#define OCR1B_2 2 +-#define OCR1B_3 3 +-#define OCR1B_4 4 +-#define OCR1B_5 5 +-#define OCR1B_6 6 +-#define OCR1B_7 7 +- +-#define OCR1A _SFR_IO8(0x2C) +-#define OCR1A_0 0 +-#define OCR1A_1 1 +-#define OCRA1_2 2 +-#define OCRA1_3 3 +-#define OCRA1_4 4 +-#define OCRA1_5 5 +-#define OCRA1_6 6 +-#define OCRA1_7 7 +- +-#define TCNT1 _SFR_IO8(0x2D) +-#define TCNT1_0 0 +-#define TCNT1_1 1 +-#define TCNT1_2 2 +-#define TCNT1_3 3 +-#define TCNT1_4 4 +-#define TCNT1_5 5 +-#define TCNT1_6 6 +-#define TCNT1_7 7 +- +-#define TCCR1B _SFR_IO8(0x2E) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCCR1A _SFR_IO8(0x2F) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR0A _SFR_IO8(0x30) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define OSCCAL _SFR_IO8(0x31) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define TCNT0 _SFR_IO8(0x32) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define TCCR0B _SFR_IO8(0x33) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x35) +-#define ISC00 0 +-#define ISC01 1 +-#define BODSE 2 +-#define SM0 3 +-#define SM1 4 +-#define SE 5 +-#define PUD 6 +-#define BODS 7 +- +-#define OCR0A _SFR_IO8(0x36) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define RFLB 3 +-#define CTPB 4 +- +-#define TIFR0 _SFR_IO8(0x38) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIMSK0 _SFR_IO8(0x39) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define GIFR _SFR_IO8(0x3A) +-#define PCIF0 4 +-#define PCIF1 5 +-#define INTF0 6 +- +-#define GIMSK _SFR_IO8(0x3B) +-#define PCIE0 4 +-#define PCIE1 5 +-#define INT0 6 +- +-#define OCR0B _SFR_IO8(0x3C) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +- +- +-/* Interrupt Vectors */ +-/* Interrupt vector 0 is the reset vector. */ +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +- +-/* Pin Change Interrupt Request 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) +- +-/* Pin Change Interrupt Request 1 */ +-#define PCINT1_vect_num 3 +-#define PCINT1_vect _VECTOR(3) +- +-/* Watchdog Time-out */ +-#define WDT_vect_num 4 +-#define WDT_vect _VECTOR(4) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIM1_COMPA_vect_num 5 +-#define TIM1_COMPA_vect _VECTOR(5) +- +-/* Timer/Counter1 Compare Match B */ +-#define TIM1_COMPB_vect_num 6 +-#define TIM1_COMPB_vect _VECTOR(6) +- +-/* Timer/Counter1 Overflow */ +-#define TIM1_OVF_vect_num 7 +-#define TIM1_OVF_vect _VECTOR(7) +- +-/* Timer/Counter0 Compare Match A */ +-#define TIM0_COMPA_vect_num 8 +-#define TIM0_COMPA_vect _VECTOR(8) +- +-/* Timer/Counter0 Compare Match B */ +-#define TIM0_COMPB_vect_num 9 +-#define TIM0_COMPB_vect _VECTOR(9) +- +-/* Timer/Counter0 Overflow */ +-#define TIM0_OVF_vect_num 10 +-#define TIM0_OVF_vect _VECTOR(10) +- +-/* Analog Comparator */ +-#define ANA_COMP_vect_num 11 +-#define ANA_COMP_vect _VECTOR(11) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 12 +-#define ADC_vect _VECTOR(12) +- +-/* EEPROM Ready */ +-#define EE_RDY_vect_num 13 +-#define EE_RDY_vect _VECTOR(13) +- +-/* USI START */ +-#define USI_START_vect_num 14 +-#define USI_START_vect _VECTOR(14) +- +-/* USI Overflow */ +-#define USI_OVF_vect_num 15 +-#define USI_OVF_vect _VECTOR(15) +- +-#define _VECTORS_SIZE 32 +- +- +-/* Constants */ +-#define SPM_PAGESIZE 64 +-#define RAMEND 0x15F +-#define XRAMEND RAMEND +-#define E2END 0x3F +-#define E2PAGESIZE 4 +-#define FLASHEND 0xFFF +- +- +-/* Fuse Information */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_DWEN (unsigned char)~_BV(6) +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_SELFPRGEN (unsigned char)~_BV(0) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x92 +-#define SIGNATURE_2 0x0C +- +- +-#endif /* _AVR_IOTN43U_H_ */ ++/* Copyright (c) 2007 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++/* $Id: iotn43u.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* avr/iotn43u.h - definitions for ATtiny43U */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn43u.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_IOTN43U_H_ ++#define _AVR_IOTN43U_H_ 1 ++ ++/* Registers and associated bit numbers */ ++ ++#define PRR _SFR_IO8(0x00) ++#define PRADC 0 ++#define PRUSI 1 ++#define PRTIM0 2 ++#define PRTIM1 3 ++ ++#define DIDR0 _SFR_IO8(0x01) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define AIN0D 4 ++#define AIN1D 5 ++ ++/* Reserved [0x02] */ ++ ++#define ADCSRB _SFR_IO8(0x03) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ADLAR 4 ++#define ACME 6 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCW _SFR_IO16(0x04) ++ ++#define ADCL _SFR_IO8(0x04) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_IO8(0x05) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_IO8(0x06) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADMUX _SFR_IO8(0x07) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define REFS0 6 ++ ++#define ACSR _SFR_IO8(0x08) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++/* Reserved [0x09], [0x0A] */ ++ ++#define TIFR1 _SFR_IO8(0x0B) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++ ++#define TIMSK1 _SFR_IO8(0x0C) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++ ++#define USICR _SFR_IO8(0x0D) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_IO8(0x0E) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_IO8(0x0F) ++#define USIDR0 0 ++#define USIDR1 1 ++#define USIDR2 2 ++#define USIDR3 3 ++#define USIDR4 4 ++#define USIDR5 5 ++#define USIDR6 6 ++#define USIDR7 7 ++ ++#define USIBR _SFR_IO8(0x10) ++#define USIBR0 0 ++#define USIBR1 1 ++#define USIBR2 2 ++#define USIBR3 3 ++#define USIBR4 4 ++#define USIBR5 5 ++#define USIBR6 6 ++#define USIBR7 7 ++ ++/* Reserved [0x11] */ ++ ++#define PCMSK0 _SFR_IO8(0x12) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define GPIOR0 _SFR_IO8(0x13) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define GPIOR1 _SFR_IO8(0x14) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x15) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define PINB _SFR_IO8(0x16) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x17) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x18) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINA _SFR_IO8(0x19) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++#define PINA4 4 ++#define PINA5 5 ++#define PINA6 6 ++#define PINA7 7 ++ ++#define DDRA _SFR_IO8(0x1A) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++#define DDA4 4 ++#define DDA5 5 ++#define DDA6 6 ++#define DDA7 7 ++ ++#define PORTA _SFR_IO8(0x1B) ++#define PORTA0 0 ++#define PORTA1 1 ++#define PORTA2 2 ++#define PORTA3 3 ++#define PORTA4 4 ++#define PORTA5 5 ++#define PORTA6 6 ++#define PORTA7 7 ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEARL _SFR_IO8(0x1E) ++ ++/* Reserved [0x1F] */ ++ ++#define PCMSK1 _SFR_IO8(0x20) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++ ++#define WDTCSR _SFR_IO8(0x21) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++/* Reserved [0x22] */ ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR10 0 ++#define TSM 7 ++ ++/* Reserved [0x24], [0x25] */ ++ ++#define CLKPR _SFR_IO8(0x26) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++/* Reserved [0x27],[0x28],[0x29],[0x2A] */ ++ ++#define OCR1B _SFR_IO8(0x2B) ++#define OCR1B_0 0 ++#define OCR1B_1 1 ++#define OCR1B_2 2 ++#define OCR1B_3 3 ++#define OCR1B_4 4 ++#define OCR1B_5 5 ++#define OCR1B_6 6 ++#define OCR1B_7 7 ++ ++#define OCR1A _SFR_IO8(0x2C) ++#define OCR1A_0 0 ++#define OCR1A_1 1 ++#define OCRA1_2 2 ++#define OCRA1_3 3 ++#define OCRA1_4 4 ++#define OCRA1_5 5 ++#define OCRA1_6 6 ++#define OCRA1_7 7 ++ ++#define TCNT1 _SFR_IO8(0x2D) ++#define TCNT1_0 0 ++#define TCNT1_1 1 ++#define TCNT1_2 2 ++#define TCNT1_3 3 ++#define TCNT1_4 4 ++#define TCNT1_5 5 ++#define TCNT1_6 6 ++#define TCNT1_7 7 ++ ++#define TCCR1B _SFR_IO8(0x2E) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCCR1A _SFR_IO8(0x2F) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR0A _SFR_IO8(0x30) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define OSCCAL _SFR_IO8(0x31) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define TCNT0 _SFR_IO8(0x32) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define TCCR0B _SFR_IO8(0x33) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define ISC00 0 ++#define ISC01 1 ++#define BODSE 2 ++#define SM0 3 ++#define SM1 4 ++#define SE 5 ++#define PUD 6 ++#define BODS 7 ++ ++#define OCR0A _SFR_IO8(0x36) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define RFLB 3 ++#define CTPB 4 ++ ++#define TIFR0 _SFR_IO8(0x38) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIMSK0 _SFR_IO8(0x39) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define GIFR _SFR_IO8(0x3A) ++#define PCIF0 4 ++#define PCIF1 5 ++#define INTF0 6 ++ ++#define GIMSK _SFR_IO8(0x3B) ++#define PCIE0 4 ++#define PCIE1 5 ++#define INT0 6 ++ ++#define OCR0B _SFR_IO8(0x3C) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++ ++ ++/* Interrupt Vectors */ ++/* Interrupt vector 0 is the reset vector. */ ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect_num 3 ++#define PCINT1_vect _VECTOR(3) ++ ++/* Watchdog Time-out */ ++#define WDT_vect_num 4 ++#define WDT_vect _VECTOR(4) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIM1_COMPA_vect_num 5 ++#define TIM1_COMPA_vect _VECTOR(5) ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIM1_COMPB_vect_num 6 ++#define TIM1_COMPB_vect _VECTOR(6) ++ ++/* Timer/Counter1 Overflow */ ++#define TIM1_OVF_vect_num 7 ++#define TIM1_OVF_vect _VECTOR(7) ++ ++/* Timer/Counter0 Compare Match A */ ++#define TIM0_COMPA_vect_num 8 ++#define TIM0_COMPA_vect _VECTOR(8) ++ ++/* Timer/Counter0 Compare Match B */ ++#define TIM0_COMPB_vect_num 9 ++#define TIM0_COMPB_vect _VECTOR(9) ++ ++/* Timer/Counter0 Overflow */ ++#define TIM0_OVF_vect_num 10 ++#define TIM0_OVF_vect _VECTOR(10) ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect_num 11 ++#define ANA_COMP_vect _VECTOR(11) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 12 ++#define ADC_vect _VECTOR(12) ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect_num 13 ++#define EE_RDY_vect _VECTOR(13) ++ ++/* USI START */ ++#define USI_START_vect_num 14 ++#define USI_START_vect _VECTOR(14) ++ ++/* USI Overflow */ ++#define USI_OVF_vect_num 15 ++#define USI_OVF_vect _VECTOR(15) ++ ++#define _VECTORS_SIZE 32 ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE 64 ++#define RAMSTART 0x60 ++#define RAMEND 0x15F ++#define XRAMEND RAMEND ++#define E2END 0x3F ++#define E2PAGESIZE 4 ++#define FLASHEND 0xFFF ++ ++ ++/* Fuse Information */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x92 ++#define SIGNATURE_2 0x0C ++ ++ ++#endif /* _AVR_IOTN43U_H_ */ +diff --git a/include/avr/iotn44.h b/include/avr/iotn44.h +index 1fc3a8e..124f895 100644 +--- a/include/avr/iotn44.h ++++ b/include/avr/iotn44.h +@@ -1,90 +1,90 @@ +-/* Copyright (c) 2005, Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn44.h 2115 2010-04-05 23:19:53Z arcanum $ */ +- +-/* avr/iotn44.h - definitions for ATtiny44 */ +- +-#ifndef _AVR_IOTN44_H_ +-#define _AVR_IOTN44_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 64 +-#define RAMSTART (0x60) +-#define RAMEND 0x15F +-#define XRAMEND RAMEND +-#define E2END 0xFF +-#define E2PAGESIZE 4 +-#define FLASHEND 0xFFF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_DWEN (unsigned char)~_BV(6) +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_SELFPRGEN (unsigned char)~_BV(0) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x92 +-#define SIGNATURE_2 0x07 +- +- +-#endif /* _AVR_IOTN44_H_ */ ++/* Copyright (c) 2005, Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn44.h 2115 2010-04-05 23:19:53Z arcanum $ */ ++ ++/* avr/iotn44.h - definitions for ATtiny44 */ ++ ++#ifndef _AVR_IOTN44_H_ ++#define _AVR_IOTN44_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 64 ++#define RAMSTART (0x60) ++#define RAMEND 0x15F ++#define XRAMEND RAMEND ++#define E2END 0xFF ++#define E2PAGESIZE 4 ++#define FLASHEND 0xFFF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x92 ++#define SIGNATURE_2 0x07 ++ ++ ++#endif /* _AVR_IOTN44_H_ */ +diff --git a/include/avr/iotn441.h b/include/avr/iotn441.h +new file mode 100644 +index 0000000..c393ada +--- /dev/null ++++ b/include/avr/iotn441.h +@@ -0,0 +1,843 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATTINY441_H_INCLUDED ++#define _AVR_ATTINY441_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn441.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define ADCSRB _SFR_IO8(0x04) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ADLAR 3 ++ ++#define ADCSRA _SFR_IO8(0x05) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x06) ++#endif ++#define ADCW _SFR_IO16(0x06) ++ ++#define ADCL _SFR_IO8(0x06) ++#define ADCH _SFR_IO8(0x07) ++ ++#define ADMUXB _SFR_IO8(0x08) ++#define GSEL0 0 ++#define GSEL1 1 ++#define REFS0 5 ++#define REFS1 6 ++#define REFS2 7 ++ ++#define ADMUXA _SFR_IO8(0x09) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define MUX5 5 ++ ++#define ACSR0A _SFR_IO8(0x0A) ++#define ACIS00 0 ++#define ACIS01 1 ++#define ACIC0 2 ++#define ACIE0 3 ++#define ACI0 4 ++#define ACO0 5 ++#define ACPMUX2 6 ++#define ACD0 7 ++ ++#define ACSR0B _SFR_IO8(0x0B) ++#define ACPMUX0 0 ++#define ACPMUX1 1 ++#define ACNMUX0 2 ++#define ACNMUX1 3 ++#define ACOE0 4 ++#define HLEV0 6 ++#define HSEL0 7 ++ ++#define ACSR1A _SFR_IO8(0x0C) ++#define ACIS10 0 ++#define ACIS11 1 ++#define ACIC1 2 ++#define ACIE1 3 ++#define ACI1 4 ++#define ACO1 5 ++#define ACBG1 6 ++#define ACD1 7 ++ ++#define ACSR1B _SFR_IO8(0x0D) ++#define ACME1 2 ++#define ACOE1 4 ++#define HLEV1 6 ++#define HSEL1 7 ++ ++#define TIFR1 _SFR_IO8(0x0E) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIMSK1 _SFR_IO8(0x0F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIFR2 _SFR_IO8(0x10) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++#define ICF2 5 ++ ++#define TIMSK2 _SFR_IO8(0x11) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++#define ICIE2 5 ++ ++#define PCMSK0 _SFR_IO8(0x12) ++ ++#define GPIOR0 _SFR_IO8(0x13) ++ ++#define GPIOR1 _SFR_IO8(0x14) ++ ++#define GPIOR2 _SFR_IO8(0x15) ++ ++#define PINB _SFR_IO8(0x16) ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x17) ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x18) ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINA _SFR_IO8(0x19) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x1A) ++#define DDRA7 7 ++#define DDRA6 6 ++#define DDRA5 5 ++#define DDRA4 4 ++#define DDRA3 3 ++#define DDRA2 2 ++#define DDRA1 1 ++#define DDRA0 0 ++ ++#define PORTA _SFR_IO8(0x1B) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define EECR _SFR_IO8(0x1C) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x1E) ++ ++#define EEARL _SFR_IO8(0x1E) ++#define EEARH _SFR_IO8(0x1F) ++ ++#define PCMSK1 _SFR_IO8(0x20) ++ ++#define WDTCSR _SFR_IO8(0x21) ++#define WDE 3 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define TCCR1C _SFR_IO8(0x22) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR 0 ++#define TSM 7 ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_IO16(0x24) ++ ++#define ICR1L _SFR_IO8(0x24) ++#define ICR1H _SFR_IO8(0x25) ++ ++/* Reserved [0x26..0x27] */ ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_IO16(0x28) ++ ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BH _SFR_IO8(0x29) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_IO16(0x2A) ++ ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_IO16(0x2C) ++ ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++ ++#define TCCR1B _SFR_IO8(0x2E) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1A _SFR_IO8(0x2F) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR0A _SFR_IO8(0x30) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++/* Reserved [0x31] */ ++ ++#define TCNT0 _SFR_IO8(0x32) ++ ++#define TCCR0B _SFR_IO8(0x33) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define ISC00 0 ++#define ISC01 1 ++#define SM0 3 ++#define SM1 4 ++#define SE 5 ++ ++#define OCR0A _SFR_IO8(0x36) ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define RFLB 3 ++#define CTPB 4 ++#define RSIG 5 ++ ++#define TIFR0 _SFR_IO8(0x38) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIMSK0 _SFR_IO8(0x39) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define GIFR _SFR_IO8(0x3A) ++#define PCIF0 4 ++#define PCIF1 5 ++#define INTF0 6 ++ ++#define GIMSK _SFR_IO8(0x3B) ++#define PCIE0 4 ++#define PCIE1 5 ++#define INT0 6 ++ ++#define OCR0B _SFR_IO8(0x3C) ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define DIDR0 _SFR_MEM8(0x60) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x61) ++#define ADC11D 0 ++#define ADC10D 1 ++#define ADC8D 2 ++#define ADC9D 3 ++ ++#define PUEB _SFR_MEM8(0x62) ++ ++#define PUEA _SFR_MEM8(0x63) ++ ++#define PORTCR _SFR_MEM8(0x64) ++#define BBMB 1 ++#define BBMA 0 ++ ++#define REMAP _SFR_MEM8(0x65) ++#define U0MAP 0 ++#define SPIMAP 1 ++ ++#define TOCPMCOE _SFR_MEM8(0x66) ++#define TOCC0OE 0 ++#define TOCC1OE 1 ++#define TOCC2OE 2 ++#define TOCC3OE 3 ++#define TOCC4OE 4 ++#define TOCC5OE 5 ++#define TOCC6OE 6 ++#define TOCC7OE 7 ++ ++#define TOCPMSA0 _SFR_MEM8(0x67) ++#define TOCC0S0 0 ++#define TOCC0S1 1 ++#define TOCC1S0 2 ++#define TOCC1S1 3 ++#define TOCC2S0 4 ++#define TOCC2S1 5 ++#define TOCC3S0 6 ++#define TOCC3S1 7 ++ ++#define TOCPMSA1 _SFR_MEM8(0x68) ++#define TOCC4S0 0 ++#define TOCC4S1 1 ++#define TOCC5S0 2 ++#define TOCC5S1 3 ++#define TOCC6S0 4 ++#define TOCC6S1 5 ++#define TOCC7S0 6 ++#define TOCC7S1 7 ++ ++/* Reserved [0x69] */ ++ ++#define PHDE _SFR_MEM8(0x6A) ++#define PHDEA0 0 ++#define PHDEA1 1 ++ ++/* Reserved [0x6B..0x6F] */ ++ ++#define PRR _SFR_MEM8(0x70) ++#define PRADC 0 ++#define PRTIM0 1 ++#define PRTIM1 2 ++#define PRTIM2 3 ++#define PRSPI 4 ++#define PRUSART0 5 ++#define PRUSART1 6 ++#define PRTWI 7 ++ ++#define CCP _SFR_MEM8(0x71) ++ ++#define CLKCR _SFR_MEM8(0x72) ++#define CKSEL0 0 ++#define CKSEL1 1 ++#define CKSEL2 2 ++#define CKSEL3 3 ++#define SUT 4 ++#define CKOUTC 5 ++#define CSTR 6 ++#define OSCRDY 7 ++ ++#define CLKPR _SFR_MEM8(0x73) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++ ++#define OSCCAL0 _SFR_MEM8(0x74) ++ ++#define OSCTCAL0A _SFR_MEM8(0x75) ++ ++#define OSCTCAL0B _SFR_MEM8(0x76) ++ ++#define OSCCAL1 _SFR_MEM8(0x77) ++ ++/* Reserved [0x78..0x7F] */ ++ ++#define UDR0 _SFR_MEM8(0x80) ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0x81) ++ ++#define UBRR0L _SFR_MEM8(0x81) ++#define UBRR0H _SFR_MEM8(0x82) ++ ++#define UCSR0D _SFR_MEM8(0x83) ++#define SFDE0 5 ++#define RXS0 6 ++#define RXSIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0x84) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++ ++#define UCSR0B _SFR_MEM8(0x85) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0A _SFR_MEM8(0x86) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++/* Reserved [0x87..0x8F] */ ++ ++#define UDR1 _SFR_MEM8(0x90) ++ ++/* Combine UBRR1L and UBRR1H */ ++#define UBRR1 _SFR_MEM16(0x91) ++ ++#define UBRR1L _SFR_MEM8(0x91) ++#define UBRR1H _SFR_MEM8(0x92) ++ ++#define UCSR1D _SFR_MEM8(0x93) ++#define SFDE1 5 ++#define RXS1 6 ++#define RXSIE1 7 ++ ++#define UCSR1C _SFR_MEM8(0x94) ++#define UCPOL1 0 ++#define UCSZ10 1 ++#define UCSZ11 2 ++#define USBS1 3 ++#define UPM10 4 ++#define UPM11 5 ++#define UMSEL10 6 ++#define UMSEL11 7 ++ ++#define UCSR1B _SFR_MEM8(0x95) ++#define TXB81 0 ++#define RXB81 1 ++#define UCSZ12 2 ++#define TXEN1 3 ++#define RXEN1 4 ++#define UDRIE1 5 ++#define TXCIE1 6 ++#define RXCIE1 7 ++ ++#define UCSR1A _SFR_MEM8(0x96) ++#define MPCM1 0 ++#define U2X1 1 ++#define UPE1 2 ++#define DOR1 3 ++#define FE1 4 ++#define UDRE1 5 ++#define TXC1 6 ++#define RXC1 7 ++ ++/* Reserved [0x97..0x9F] */ ++ ++#define TWSD _SFR_MEM8(0xA0) ++#define TWSD0 0 ++#define TWSD1 1 ++#define TWSD2 2 ++#define TWSD3 3 ++#define TWSD4 4 ++#define TWSD5 5 ++#define TWSD6 6 ++#define TWSD7 7 ++ ++#define TWSAM _SFR_MEM8(0xA1) ++#define TWAE 0 ++#define TWSAM1 1 ++#define TWSAM2 2 ++#define TWSAM3 3 ++#define TWSAM4 4 ++#define TWSAM5 5 ++#define TWSAM6 6 ++#define TWSAM7 7 ++ ++#define TWSA _SFR_MEM8(0xA2) ++ ++#define TWSSRA _SFR_MEM8(0xA3) ++#define TWAS 0 ++#define TWDIR 1 ++#define TWBE 2 ++#define TWC 3 ++#define TWRA 4 ++#define TWCH 5 ++#define TWASIF 6 ++#define TWDIF 7 ++ ++#define TWSCRB _SFR_MEM8(0xA4) ++#define TWCMD0 0 ++#define TWCMD1 1 ++#define TWAA 2 ++#define TWHNM 3 ++ ++#define TWSCRA _SFR_MEM8(0xA5) ++#define TWSME 0 ++#define TWPME 1 ++#define TWSIE 2 ++#define TWEN 3 ++#define TWASIE 4 ++#define TWDIE 5 ++#define TWSHE 7 ++ ++/* Reserved [0xA6..0xAF] */ ++ ++#define SPDR _SFR_MEM8(0xB0) ++ ++#define SPSR _SFR_MEM8(0xB1) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPCR _SFR_MEM8(0xB2) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++/* Reserved [0xB3..0xBF] */ ++ ++/* Combine ICR2L and ICR2H */ ++#define ICR2 _SFR_MEM16(0xC0) ++ ++#define ICR2L _SFR_MEM8(0xC0) ++#define ICR2H _SFR_MEM8(0xC1) ++ ++/* Combine OCR2BL and OCR2BH */ ++#define OCR2B _SFR_MEM16(0xC2) ++ ++#define OCR2BL _SFR_MEM8(0xC2) ++#define OCR2BH _SFR_MEM8(0xC3) ++ ++/* Combine OCR2AL and OCR2AH */ ++#define OCR2A _SFR_MEM16(0xC4) ++ ++#define OCR2AL _SFR_MEM8(0xC4) ++#define OCR2AH _SFR_MEM8(0xC5) ++ ++/* Combine TCNT2L and TCNT2H */ ++#define TCNT2 _SFR_MEM16(0xC6) ++ ++#define TCNT2L _SFR_MEM8(0xC6) ++#define TCNT2H _SFR_MEM8(0xC7) ++ ++#define TCCR2C _SFR_MEM8(0xC8) ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCCR2B _SFR_MEM8(0xC9) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define WGM23 4 ++#define ICES2 6 ++#define ICNC2 7 ++ ++#define TCCR2A _SFR_MEM8(0xCA) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(2) ++#define PCINT0_vect_num 2 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(3) ++#define PCINT1_vect_num 3 ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect _VECTOR(4) ++#define WDT_vect_num 4 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(5) ++#define TIMER1_CAPT_vect_num 5 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(6) ++#define TIMER1_COMPA_vect_num 6 ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(7) ++#define TIMER1_COMPB_vect_num 7 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(8) ++#define TIMER1_OVF_vect_num 8 ++ ++/* TimerCounter0 Compare Match A */ ++#define TIMER0_COMPA_vect _VECTOR(9) ++#define TIMER0_COMPA_vect_num 9 ++ ++/* TimerCounter0 Compare Match B */ ++#define TIMER0_COMPB_vect _VECTOR(10) ++#define TIMER0_COMPB_vect_num 10 ++ ++/* Timer/Couner0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(11) ++#define TIMER0_OVF_vect_num 11 ++ ++/* Analog Comparator 0 */ ++#define ANA_COMP0_vect _VECTOR(12) ++#define ANA_COMP0_vect_num 12 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(13) ++#define ADC_vect_num 13 ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect _VECTOR(14) ++#define EE_RDY_vect_num 14 ++ ++/* Analog Comparator 1 */ ++#define ANA_COMP1_vect _VECTOR(15) ++#define ANA_COMP1_vect_num 15 ++ ++/* Timer/Counter2 Capture Event */ ++#define TIMER2_CAPT_vect _VECTOR(16) ++#define TIMER2_CAPT_vect_num 16 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPA_vect _VECTOR(17) ++#define TIMER2_COMPA_vect_num 17 ++ ++/* Timer/Counter2 Compare Match B */ ++#define TIMER2_COMPB_vect _VECTOR(18) ++#define TIMER2_COMPB_vect_num 18 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(19) ++#define TIMER2_OVF_vect_num 19 ++ ++/* Serial Peripheral Interface */ ++#define SPI_vect _VECTOR(20) ++#define SPI_vect_num 20 ++ ++/* USART0, Start */ ++#define USART0_START_vect _VECTOR(21) ++#define USART0_START_vect_num 21 ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect _VECTOR(22) ++#define USART0_RX_vect_num 22 ++ ++/* USART0 Data Register Empty */ ++#define USART0_UDRE_vect _VECTOR(23) ++#define USART0_UDRE_vect_num 23 ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect _VECTOR(24) ++#define USART0_TX_vect_num 24 ++ ++/* USART1, Start */ ++#define USART1_START_vect _VECTOR(25) ++#define USART1_START_vect_num 25 ++ ++/* USART1, Rx Complete */ ++#define USART1_RX_vect _VECTOR(26) ++#define USART1_RX_vect_num 26 ++ ++/* USART1 Data Register Empty */ ++#define USART1_UDRE_vect _VECTOR(27) ++#define USART1_UDRE_vect_num 27 ++ ++/* USART1, Tx Complete */ ++#define USART1_TX_vect _VECTOR(28) ++#define USART1_TX_vect_num 28 ++ ++/* Two-wire Serial Interface */ ++#define TWI_SLAVE_vect _VECTOR(29) ++#define TWI_SLAVE_vect_num 29 ++ ++#define _VECTORS_SIZE 60 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 16 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x0FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 256 ++#define RAMEND 0x01FF ++#define E2START 0 ++#define E2SIZE 256 ++#define E2PAGESIZE 4 ++#define E2END 0x00FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) ++#define FUSE_BODACT0 (unsigned char)~_BV(1) ++#define FUSE_BODACT1 (unsigned char)~_BV(2) ++#define FUSE_BODPD0 (unsigned char)~_BV(3) ++#define FUSE_BODPD1 (unsigned char)~_BV(4) ++#define FUSE_ULPOSCSEL0 (unsigned char)~_BV(5) ++#define FUSE_ULPOSCSEL1 (unsigned char)~_BV(6) ++#define FUSE_ULPOSCSEL2 (unsigned char)~_BV(7) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x92 ++#define SIGNATURE_2 0x15 ++ ++ ++#endif /* #ifdef _AVR_ATTINY441_H_INCLUDED */ ++ +diff --git a/include/avr/iotn44a.h b/include/avr/iotn44a.h +index cca6515..0173892 100644 +--- a/include/avr/iotn44a.h ++++ b/include/avr/iotn44a.h +@@ -1,831 +1,833 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn44a.h 2035 2009-11-02 02:44:17Z arcanum $ */ +- +-/* avr/iotn44a.h - definitions for ATtiny44A */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn44a.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATtiny44A_H_ +-#define _AVR_ATtiny44A_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PRR _SFR_IO8(0x00) +-#define PRADC 0 +-#define PRUSI 1 +-#define PRTIM0 2 +-#define PRTIM1 3 +- +-#define DIDR0 _SFR_IO8(0x01) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define ADCSRB _SFR_IO8(0x03) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ADLAR 4 +-#define ACME 6 +-#define BIN 7 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x04) +-#endif +-#define ADCW _SFR_IO16(0x04) +- +-#define ADCL _SFR_IO8(0x04) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_IO8(0x05) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_IO8(0x06) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADMUX _SFR_IO8(0x07) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define MUX5 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define ACSR _SFR_IO8(0x08) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define TIFR1 _SFR_IO8(0x0B) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define TIMSK1 _SFR_IO8(0x0C) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define USICR _SFR_IO8(0x0D) +-#define USITC 0 +-#define USICLK 1 +-#define USICS0 2 +-#define USICS1 3 +-#define USIWM0 4 +-#define USIWM1 5 +-#define USIOIE 6 +-#define USISIE 7 +- +-#define USISR _SFR_IO8(0x0E) +-#define USICNT0 0 +-#define USICNT1 1 +-#define USICNT2 2 +-#define USICNT3 3 +-#define USIDC 4 +-#define USIPF 5 +-#define USIOIF 6 +-#define USISIF 7 +- +-#define USIDR _SFR_IO8(0x0F) +-#define USIDR0 0 +-#define USIDR1 1 +-#define USIDR2 2 +-#define USIDR3 3 +-#define USIDR4 4 +-#define USIDR5 5 +-#define USIDR6 6 +-#define USIDR7 7 +- +-#define USIBR _SFR_IO8(0x10) +-#define USIBR0 0 +-#define USIBR1 1 +-#define USIBR2 2 +-#define USIBR3 3 +-#define USIBR4 4 +-#define USIBR5 5 +-#define USIBR6 6 +-#define USIBR7 7 +- +-#define PCMSK0 _SFR_IO8(0x12) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define GPIOR0 _SFR_IO8(0x13) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define GPIOR1 _SFR_IO8(0x14) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x15) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define PINB _SFR_IO8(0x16) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +- +-#define DDRB _SFR_IO8(0x17) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +- +-#define PORTB _SFR_IO8(0x18) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +- +-#define PINA _SFR_IO8(0x19) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +-#define PINA4 4 +-#define PINA5 5 +-#define PINA6 6 +-#define PINA7 7 +- +-#define DDRA _SFR_IO8(0x1A) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +-#define DDA4 4 +-#define DDA5 5 +-#define DDA6 6 +-#define DDA7 7 +- +-#define PORTA _SFR_IO8(0x1B) +-#define PORTA0 0 +-#define PORTA1 1 +-#define PORTA2 2 +-#define PORTA3 3 +-#define PORTA4 4 +-#define PORTA5 5 +-#define PORTA6 6 +-#define PORTA7 7 +- +-#define EECR _SFR_IO8(0x1C) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x1D) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x1E) +- +-#define EEARL _SFR_IO8(0x1E) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x1F) +-#define EEAR8 0 +- +-#define PCMSK1 _SFR_IO8(0x20) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +- +-#define WDTCSR _SFR_IO8(0x21) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define TCCR1C _SFR_IO8(0x22) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSR10 0 +-#define TSM 7 +- +-#define ICR1 _SFR_IO16(0x24) +- +-#define ICR1L _SFR_IO8(0x24) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_IO8(0x25) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define CLKPR _SFR_IO8(0x26) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define DWDR _SFR_IO8(0x27) +- +-#define OCR1B _SFR_IO16(0x28) +- +-#define OCR1BL _SFR_IO8(0x28) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_IO8(0x29) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define OCR1A _SFR_IO16(0x2A) +- +-#define OCR1AL _SFR_IO8(0x2A) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_IO8(0x2B) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define TCNT1 _SFR_IO16(0x2C) +- +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_IO8(0x2D) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define TCCR1B _SFR_IO8(0x2E) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1A _SFR_IO8(0x2F) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR0A _SFR_IO8(0x30) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define OSCCAL _SFR_IO8(0x31) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define TCNT0 _SFR_IO8(0x32) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define TCCR0B _SFR_IO8(0x33) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x35) +-#define ISC00 0 +-#define ISC01 1 +-#define SM0 3 +-#define SM1 4 +-#define SE 5 +-#define PUD 6 +- +-#define OCR0A _SFR_IO8(0x36) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define RFLB 3 +-#define CTPB 4 +- +-#define TIFR0 _SFR_IO8(0x38) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIMSK0 _SFR_IO8(0x39) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define GIFR _SFR_IO8(0x3A) +-#define PCIF0 4 +-#define PCIF1 5 +-#define INTF0 6 +- +-#define GIMSK _SFR_IO8(0x3B) +-#define PCIE0 4 +-#define PCIE1 5 +-#define INT0 6 +- +-#define OCR0B _SFR_IO8(0x3C) +-#define OCR0_0 0 +-#define OCR0_1 1 +-#define OCR0_2 2 +-#define OCR0_3 3 +-#define OCR0_4 4 +-#define OCR0_5 5 +-#define OCR0_6 6 +-#define OCR0_7 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define EXT_INT0_vect_num 1 +-#define EXT_INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ +-#define PCINT1_vect_num 3 +-#define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */ +-#define WATCHDOG_vect_num 4 +-#define WATCHDOG_vect _VECTOR(4) /* Watchdog Time-out */ +-#define TIM1_CAPT_vect_num 5 +-#define TIM1_CAPT_vect _VECTOR(5) /* Timer/Counter1 Capture Event */ +-#define TIM1_COMPA_vect_num 6 +-#define TIM1_COMPA_vect _VECTOR(6) /* Timer/Counter1 Compare Match A */ +-#define TIM1_COMPB_vect_num 7 +-#define TIM1_COMPB_vect _VECTOR(7) /* Timer/Counter1 Compare Match B */ +-#define TIM1_OVF_vect_num 8 +-#define TIM1_OVF_vect _VECTOR(8) /* Timer/Counter1 Overflow */ +-#define TIM0_COMPA_vect_num 9 +-#define TIM0_COMPA_vect _VECTOR(9) /* Timer/Counter0 Compare Match A */ +-#define TIM0_COMPB_vect_num 10 +-#define TIM0_COMPB_vect _VECTOR(10) /* Timer/Counter0 Compare Match B */ +-#define TIM0_OVF_vect_num 11 +-#define TIM0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ +-#define ANA_COMP_vect_num 12 +-#define ANA_COMP_vect _VECTOR(12) /* Analog Comparator */ +-#define ADC_vect_num 13 +-#define ADC_vect _VECTOR(13) /* ADC Conversion Complete */ +-#define EE_RDY_vect_num 14 +-#define EE_RDY_vect _VECTOR(14) /* EEPROM Ready */ +-#define USI_STR_vect_num 15 +-#define USI_STR_vect _VECTOR(15) /* USI START */ +-#define USI_OVF_vect_num 16 +-#define USI_OVF_vect _VECTOR(16) /* USI Overflow */ +- +-#define _VECTOR_SIZE 2 /* Size of individual vector. */ +-#define _VECTORS_SIZE (17 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (64) +-#define RAMSTART (0x60) +-#define RAMSIZE (256) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0xFF) +-#define E2PAGESIZE (4) +-#define FLASHEND (0xFFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x92 +-#define SIGNATURE_2 0x07 +- +- +-/* Device Pin Definitions */ +-#define ADC4_DDR DDRA +-#define ADC4_PORT PORTA +-#define ADC4_PIN PINA +-#define ADC4_BIT 4 +- +-#define USCK_DDR DDRA +-#define USCK_PORT PORTA +-#define USCK_PIN PINA +-#define USCK_BIT 4 +- +-#define SCL_DDR DDRA +-#define SCL_PORT PORTA +-#define SCL_PIN PINA +-#define SCL_BIT 4 +- +-#define T1_DDR DDRA +-#define T1_PORT PORTA +-#define T1_PIN PINA +-#define T1_BIT 4 +- +-#define PCINT4_DDR DDRA +-#define PCINT4_PORT PORTA +-#define PCINT4_PIN PINA +-#define PCINT4_BIT 4 +- +-#define ADC3_DDR DDRA +-#define ADC3_PORT PORTA +-#define ADC3_PIN PINA +-#define ADC3_BIT 3 +- +-#define T0_DDR DDRA +-#define T0_PORT PORTA +-#define T0_PIN PINA +-#define T0_BIT 3 +- +-#define PCINT3_DDR DDRA +-#define PCINT3_PORT PORTA +-#define PCINT3_PIN PINA +-#define PCINT3_BIT 3 +- +-#define ADC2_DDR DDRA +-#define ADC2_PORT PORTA +-#define ADC2_PIN PINA +-#define ADC2_BIT 2 +- +-#define AIN1_DDR DDRA +-#define AIN1_PORT PORTA +-#define AIN1_PIN PINA +-#define AIN1_BIT 2 +- +-#define PCINT2_DDR DDRA +-#define PCINT2_PORT PORTA +-#define PCINT2_PIN PINA +-#define PCINT2_BIT 2 +- +-#define ADC1_DDR DDRA +-#define ADC1_PORT PORTA +-#define ADC1_PIN PINA +-#define ADC1_BIT 1 +- +-#define AIN0_DDR DDRA +-#define AIN0_PORT PORTA +-#define AIN0_PIN PINA +-#define AIN0_BIT 1 +- +-#define PCINT1_DDR DDRA +-#define PCINT1_PORT PORTA +-#define PCINT1_PIN PINA +-#define PCINT1_BIT 1 +- +-#define ADC0_DDR DDRA +-#define ADC0_PORT PORTA +-#define ADC0_PIN PINA +-#define ADC0_BIT 0 +- +-#define PCINT0_DDR DDRA +-#define PCINT0_PORT PORTA +-#define PCINT0_PIN PINA +-#define PCINT0_BIT 0 +- +-#define PCINT8_DDR DDRB +-#define PCINT8_PORT PORTB +-#define PCINT8_PIN PINB +-#define PCINT8_BIT 0 +- +-#define PCINT9_DDR DDRB +-#define PCINT9_PORT PORTB +-#define PCINT9_PIN PINB +-#define PCINT9_BIT 1 +- +-#define PCINT11_DDR DDRB +-#define PCINT11_PORT PORTB +-#define PCINT11_PIN PINB +-#define PCINT11_BIT 3 +- +-#define dW_DDR DDRB +-#define dW_PORT PORTB +-#define dW_PIN PINB +-#define dW_BIT 3 +- +-#define PCINT10_DDR DDRB +-#define PCINT10_PORT PORTB +-#define PCINT10_PIN PINB +-#define PCINT10_BIT 2 +- +-#define INT0_DDR DDRB +-#define INT0_PORT PORTB +-#define INT0_PIN PINB +-#define INT0_BIT 2 +- +-#define OC0A_DDR DDRB +-#define OC0A_PORT PORTB +-#define OC0A_PIN PINB +-#define OC0A_BIT 2 +- +-#define CKOUT_DDR DDRB +-#define CKOUT_PORT PORTB +-#define CKOUT_PIN PINB +-#define CKOUT_BIT 2 +- +-#define PCINT7_DDR DDRA +-#define PCINT7_PORT PORTA +-#define PCINT7_PIN PINA +-#define PCINT7_BIT 7 +- +-#define ICP1_DDR DDRA +-#define ICP1_PORT PORTA +-#define ICP1_PIN PINA +-#define ICP1_BIT 7 +- +-#define OC0B_DDR DDRA +-#define OC0B_PORT PORTA +-#define OC0B_PIN PINA +-#define OC0B_BIT 7 +- +-#define ADC7_DDR DDRA +-#define ADC7_PORT PORTA +-#define ADC7_PIN PINA +-#define ADC7_BIT 7 +- +-#define PCINT6_DDR DDRA +-#define PCINT6_PORT PORTA +-#define PCINT6_PIN PINA +-#define PCINT6_BIT 6 +- +-#define OC1A_DDR DDRA +-#define OC1A_PORT PORTA +-#define OC1A_PIN PINA +-#define OC1A_BIT 6 +- +-#define DI_DDR DDRA +-#define DI_PORT PORTA +-#define DI_PIN PINA +-#define DI_BIT 6 +- +-#define SDA_DDR DDRA +-#define SDA_PORT PORTA +-#define SDA_PIN PINA +-#define SDA_BIT 6 +- +-#define MOSI_DDR DDRA +-#define MOSI_PORT PORTA +-#define MOSI_PIN PINA +-#define MOSI_BIT 6 +- +-#define ADC6_DDR DDRA +-#define ADC6_PORT PORTA +-#define ADC6_PIN PINA +-#define ADC6_BIT 6 +- +-#define ADC5_DDR DDRA +-#define ADC5_PORT PORTA +-#define ADC5_PIN PINA +-#define ADC5_BIT 5 +- +-#define DO_DDR DDRA +-#define DO_PORT PORTA +-#define DO_PIN PINA +-#define DO_BIT 5 +- +-#define MISO_DDR DDRA +-#define MISO_PORT PORTA +-#define MISO_PIN PINA +-#define MISO_BIT 5 +- +-#define OC1B_DDR DDRA +-#define OC1B_PORT PORTA +-#define OC1B_PIN PINA +-#define OC1B_BIT 5 +- +-#define PCINT5_DDR DDRA +-#define PCINT5_PORT PORTA +-#define PCINT5_PIN PINA +-#define PCINT5_BIT 5 +- +-#endif /* _AVR_ATtiny44A_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn44a.h 2035 2009-11-02 02:44:17Z arcanum $ */ ++ ++/* avr/iotn44a.h - definitions for ATtiny44A */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn44a.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATtiny44A_H_ ++#define _AVR_ATtiny44A_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PRR _SFR_IO8(0x00) ++#define PRADC 0 ++#define PRUSI 1 ++#define PRTIM0 2 ++#define PRTIM1 3 ++ ++#define DIDR0 _SFR_IO8(0x01) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define ADCSRB _SFR_IO8(0x03) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ADLAR 4 ++#define ACME 6 ++#define BIN 7 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCW _SFR_IO16(0x04) ++ ++#define ADCL _SFR_IO8(0x04) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_IO8(0x05) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_IO8(0x06) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADMUX _SFR_IO8(0x07) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define MUX5 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define ACSR _SFR_IO8(0x08) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define TIFR1 _SFR_IO8(0x0B) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIMSK1 _SFR_IO8(0x0C) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define USICR _SFR_IO8(0x0D) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_IO8(0x0E) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_IO8(0x0F) ++#define USIDR0 0 ++#define USIDR1 1 ++#define USIDR2 2 ++#define USIDR3 3 ++#define USIDR4 4 ++#define USIDR5 5 ++#define USIDR6 6 ++#define USIDR7 7 ++ ++#define USIBR _SFR_IO8(0x10) ++#define USIBR0 0 ++#define USIBR1 1 ++#define USIBR2 2 ++#define USIBR3 3 ++#define USIBR4 4 ++#define USIBR5 5 ++#define USIBR6 6 ++#define USIBR7 7 ++ ++#define PCMSK0 _SFR_IO8(0x12) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define GPIOR0 _SFR_IO8(0x13) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define GPIOR1 _SFR_IO8(0x14) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x15) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define PINB _SFR_IO8(0x16) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++ ++#define DDRB _SFR_IO8(0x17) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++ ++#define PORTB _SFR_IO8(0x18) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++ ++#define PINA _SFR_IO8(0x19) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++#define PINA4 4 ++#define PINA5 5 ++#define PINA6 6 ++#define PINA7 7 ++ ++#define DDRA _SFR_IO8(0x1A) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++#define DDA4 4 ++#define DDA5 5 ++#define DDA6 6 ++#define DDA7 7 ++ ++#define PORTA _SFR_IO8(0x1B) ++#define PORTA0 0 ++#define PORTA1 1 ++#define PORTA2 2 ++#define PORTA3 3 ++#define PORTA4 4 ++#define PORTA5 5 ++#define PORTA6 6 ++#define PORTA7 7 ++ ++#define EECR _SFR_IO8(0x1C) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x1D) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x1E) ++ ++#define EEARL _SFR_IO8(0x1E) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x1F) ++#define EEAR8 0 ++ ++#define PCMSK1 _SFR_IO8(0x20) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++ ++#define WDTCSR _SFR_IO8(0x21) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define TCCR1C _SFR_IO8(0x22) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR10 0 ++#define TSM 7 ++ ++#define ICR1 _SFR_IO16(0x24) ++ ++#define ICR1L _SFR_IO8(0x24) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_IO8(0x25) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define CLKPR _SFR_IO8(0x26) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define DWDR _SFR_IO8(0x27) ++ ++#define OCR1B _SFR_IO16(0x28) ++ ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_IO8(0x29) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define OCR1A _SFR_IO16(0x2A) ++ ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_IO8(0x2B) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define TCNT1 _SFR_IO16(0x2C) ++ ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_IO8(0x2D) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define TCCR1B _SFR_IO8(0x2E) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1A _SFR_IO8(0x2F) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR0A _SFR_IO8(0x30) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define OSCCAL _SFR_IO8(0x31) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define TCNT0 _SFR_IO8(0x32) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define TCCR0B _SFR_IO8(0x33) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define ISC00 0 ++#define ISC01 1 ++#define BODSE 2 ++#define SM0 3 ++#define SM1 4 ++#define SE 5 ++#define PUD 6 ++#define BODS 7 ++ ++#define OCR0A _SFR_IO8(0x36) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define RFLB 3 ++#define CTPB 4 ++ ++#define TIFR0 _SFR_IO8(0x38) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIMSK0 _SFR_IO8(0x39) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define GIFR _SFR_IO8(0x3A) ++#define PCIF0 4 ++#define PCIF1 5 ++#define INTF0 6 ++ ++#define GIMSK _SFR_IO8(0x3B) ++#define PCIE0 4 ++#define PCIE1 5 ++#define INT0 6 ++ ++#define OCR0B _SFR_IO8(0x3C) ++#define OCR0_0 0 ++#define OCR0_1 1 ++#define OCR0_2 2 ++#define OCR0_3 3 ++#define OCR0_4 4 ++#define OCR0_5 5 ++#define OCR0_6 6 ++#define OCR0_7 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define EXT_INT0_vect_num 1 ++#define EXT_INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect_num 3 ++#define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */ ++#define WATCHDOG_vect_num 4 ++#define WATCHDOG_vect _VECTOR(4) /* Watchdog Time-out */ ++#define TIM1_CAPT_vect_num 5 ++#define TIM1_CAPT_vect _VECTOR(5) /* Timer/Counter1 Capture Event */ ++#define TIM1_COMPA_vect_num 6 ++#define TIM1_COMPA_vect _VECTOR(6) /* Timer/Counter1 Compare Match A */ ++#define TIM1_COMPB_vect_num 7 ++#define TIM1_COMPB_vect _VECTOR(7) /* Timer/Counter1 Compare Match B */ ++#define TIM1_OVF_vect_num 8 ++#define TIM1_OVF_vect _VECTOR(8) /* Timer/Counter1 Overflow */ ++#define TIM0_COMPA_vect_num 9 ++#define TIM0_COMPA_vect _VECTOR(9) /* Timer/Counter0 Compare Match A */ ++#define TIM0_COMPB_vect_num 10 ++#define TIM0_COMPB_vect _VECTOR(10) /* Timer/Counter0 Compare Match B */ ++#define TIM0_OVF_vect_num 11 ++#define TIM0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ ++#define ANA_COMP_vect_num 12 ++#define ANA_COMP_vect _VECTOR(12) /* Analog Comparator */ ++#define ADC_vect_num 13 ++#define ADC_vect _VECTOR(13) /* ADC Conversion Complete */ ++#define EE_RDY_vect_num 14 ++#define EE_RDY_vect _VECTOR(14) /* EEPROM Ready */ ++#define USI_STR_vect_num 15 ++#define USI_STR_vect _VECTOR(15) /* USI START */ ++#define USI_OVF_vect_num 16 ++#define USI_OVF_vect _VECTOR(16) /* USI Overflow */ ++ ++#define _VECTOR_SIZE 2 /* Size of individual vector. */ ++#define _VECTORS_SIZE (17 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (64) ++#define RAMSTART (0x60) ++#define RAMSIZE (256) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0xFF) ++#define E2PAGESIZE (4) ++#define FLASHEND (0xFFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x92 ++#define SIGNATURE_2 0x07 ++ ++ ++/* Device Pin Definitions */ ++#define ADC4_DDR DDRA ++#define ADC4_PORT PORTA ++#define ADC4_PIN PINA ++#define ADC4_BIT 4 ++ ++#define USCK_DDR DDRA ++#define USCK_PORT PORTA ++#define USCK_PIN PINA ++#define USCK_BIT 4 ++ ++#define SCL_DDR DDRA ++#define SCL_PORT PORTA ++#define SCL_PIN PINA ++#define SCL_BIT 4 ++ ++#define T1_DDR DDRA ++#define T1_PORT PORTA ++#define T1_PIN PINA ++#define T1_BIT 4 ++ ++#define PCINT4_DDR DDRA ++#define PCINT4_PORT PORTA ++#define PCINT4_PIN PINA ++#define PCINT4_BIT 4 ++ ++#define ADC3_DDR DDRA ++#define ADC3_PORT PORTA ++#define ADC3_PIN PINA ++#define ADC3_BIT 3 ++ ++#define T0_DDR DDRA ++#define T0_PORT PORTA ++#define T0_PIN PINA ++#define T0_BIT 3 ++ ++#define PCINT3_DDR DDRA ++#define PCINT3_PORT PORTA ++#define PCINT3_PIN PINA ++#define PCINT3_BIT 3 ++ ++#define ADC2_DDR DDRA ++#define ADC2_PORT PORTA ++#define ADC2_PIN PINA ++#define ADC2_BIT 2 ++ ++#define AIN1_DDR DDRA ++#define AIN1_PORT PORTA ++#define AIN1_PIN PINA ++#define AIN1_BIT 2 ++ ++#define PCINT2_DDR DDRA ++#define PCINT2_PORT PORTA ++#define PCINT2_PIN PINA ++#define PCINT2_BIT 2 ++ ++#define ADC1_DDR DDRA ++#define ADC1_PORT PORTA ++#define ADC1_PIN PINA ++#define ADC1_BIT 1 ++ ++#define AIN0_DDR DDRA ++#define AIN0_PORT PORTA ++#define AIN0_PIN PINA ++#define AIN0_BIT 1 ++ ++#define PCINT1_DDR DDRA ++#define PCINT1_PORT PORTA ++#define PCINT1_PIN PINA ++#define PCINT1_BIT 1 ++ ++#define ADC0_DDR DDRA ++#define ADC0_PORT PORTA ++#define ADC0_PIN PINA ++#define ADC0_BIT 0 ++ ++#define PCINT0_DDR DDRA ++#define PCINT0_PORT PORTA ++#define PCINT0_PIN PINA ++#define PCINT0_BIT 0 ++ ++#define PCINT8_DDR DDRB ++#define PCINT8_PORT PORTB ++#define PCINT8_PIN PINB ++#define PCINT8_BIT 0 ++ ++#define PCINT9_DDR DDRB ++#define PCINT9_PORT PORTB ++#define PCINT9_PIN PINB ++#define PCINT9_BIT 1 ++ ++#define PCINT11_DDR DDRB ++#define PCINT11_PORT PORTB ++#define PCINT11_PIN PINB ++#define PCINT11_BIT 3 ++ ++#define dW_DDR DDRB ++#define dW_PORT PORTB ++#define dW_PIN PINB ++#define dW_BIT 3 ++ ++#define PCINT10_DDR DDRB ++#define PCINT10_PORT PORTB ++#define PCINT10_PIN PINB ++#define PCINT10_BIT 2 ++ ++#define INT0_DDR DDRB ++#define INT0_PORT PORTB ++#define INT0_PIN PINB ++#define INT0_BIT 2 ++ ++#define OC0A_DDR DDRB ++#define OC0A_PORT PORTB ++#define OC0A_PIN PINB ++#define OC0A_BIT 2 ++ ++#define CKOUT_DDR DDRB ++#define CKOUT_PORT PORTB ++#define CKOUT_PIN PINB ++#define CKOUT_BIT 2 ++ ++#define PCINT7_DDR DDRA ++#define PCINT7_PORT PORTA ++#define PCINT7_PIN PINA ++#define PCINT7_BIT 7 ++ ++#define ICP1_DDR DDRA ++#define ICP1_PORT PORTA ++#define ICP1_PIN PINA ++#define ICP1_BIT 7 ++ ++#define OC0B_DDR DDRA ++#define OC0B_PORT PORTA ++#define OC0B_PIN PINA ++#define OC0B_BIT 7 ++ ++#define ADC7_DDR DDRA ++#define ADC7_PORT PORTA ++#define ADC7_PIN PINA ++#define ADC7_BIT 7 ++ ++#define PCINT6_DDR DDRA ++#define PCINT6_PORT PORTA ++#define PCINT6_PIN PINA ++#define PCINT6_BIT 6 ++ ++#define OC1A_DDR DDRA ++#define OC1A_PORT PORTA ++#define OC1A_PIN PINA ++#define OC1A_BIT 6 ++ ++#define DI_DDR DDRA ++#define DI_PORT PORTA ++#define DI_PIN PINA ++#define DI_BIT 6 ++ ++#define SDA_DDR DDRA ++#define SDA_PORT PORTA ++#define SDA_PIN PINA ++#define SDA_BIT 6 ++ ++#define MOSI_DDR DDRA ++#define MOSI_PORT PORTA ++#define MOSI_PIN PINA ++#define MOSI_BIT 6 ++ ++#define ADC6_DDR DDRA ++#define ADC6_PORT PORTA ++#define ADC6_PIN PINA ++#define ADC6_BIT 6 ++ ++#define ADC5_DDR DDRA ++#define ADC5_PORT PORTA ++#define ADC5_PIN PINA ++#define ADC5_BIT 5 ++ ++#define DO_DDR DDRA ++#define DO_PORT PORTA ++#define DO_PIN PINA ++#define DO_BIT 5 ++ ++#define MISO_DDR DDRA ++#define MISO_PORT PORTA ++#define MISO_PIN PINA ++#define MISO_BIT 5 ++ ++#define OC1B_DDR DDRA ++#define OC1B_PORT PORTA ++#define OC1B_PIN PINA ++#define OC1B_BIT 5 ++ ++#define PCINT5_DDR DDRA ++#define PCINT5_PORT PORTA ++#define PCINT5_PIN PINA ++#define PCINT5_BIT 5 ++ ++#endif /* _AVR_ATtiny44A_H_ */ ++ +diff --git a/include/avr/iotn45.h b/include/avr/iotn45.h +index 66f4062..9b5f3b9 100644 +--- a/include/avr/iotn45.h ++++ b/include/avr/iotn45.h +@@ -1,90 +1,90 @@ +-/* Copyright (c) 2005, Joerg Wunsch +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn45.h 2115 2010-04-05 23:19:53Z arcanum $ */ +- +-/* avr/iotn45.h - definitions for ATtiny45 */ +- +-#ifndef _AVR_IOTN45_H_ +-#define _AVR_IOTN45_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 64 +-#define RAMSTART (0x60) +-#define RAMEND 0x15F +-#define XRAMEND RAMEND +-#define E2END 0xFF +-#define E2PAGESIZE 4 +-#define FLASHEND 0xFFF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_DWEN (unsigned char)~_BV(6) +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_SELFPRGEN (unsigned char)~_BV(0) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x92 +-#define SIGNATURE_2 0x06 +- +- +-#endif /* _AVR_IOTN45_H_ */ ++/* Copyright (c) 2005, Joerg Wunsch ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn45.h 2115 2010-04-05 23:19:53Z arcanum $ */ ++ ++/* avr/iotn45.h - definitions for ATtiny45 */ ++ ++#ifndef _AVR_IOTN45_H_ ++#define _AVR_IOTN45_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 64 ++#define RAMSTART (0x60) ++#define RAMEND 0x15F ++#define XRAMEND RAMEND ++#define E2END 0xFF ++#define E2PAGESIZE 4 ++#define FLASHEND 0xFFF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x92 ++#define SIGNATURE_2 0x06 ++ ++ ++#endif /* _AVR_IOTN45_H_ */ +diff --git a/include/avr/iotn461.h b/include/avr/iotn461.h +index 0e48c9c..d1554c5 100644 +--- a/include/avr/iotn461.h ++++ b/include/avr/iotn461.h +@@ -1,90 +1,90 @@ +-/* Copyright (c) 2006, Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn461.h 2115 2010-04-05 23:19:53Z arcanum $ */ +- +-/* avr/iotn461.h - definitions for ATtiny461 */ +- +-#ifndef _AVR_IOTN461_H_ +-#define _AVR_IOTN461_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 64 +-#define RAMSTART (0x60) +-#define RAMEND 0x15F +-#define XRAMEND RAMEND +-#define E2END 0xFF +-#define E2PAGESIZE 4 +-#define FLASHEND 0xFFF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_DWEN (unsigned char)~_BV(6) +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_SELFPRGEN (unsigned char)~_BV(0) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x92 +-#define SIGNATURE_2 0x08 +- +- +-#endif /* _AVR_IOTN461_H_ */ ++/* Copyright (c) 2006, Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn461.h 2115 2010-04-05 23:19:53Z arcanum $ */ ++ ++/* avr/iotn461.h - definitions for ATtiny461 */ ++ ++#ifndef _AVR_IOTN461_H_ ++#define _AVR_IOTN461_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 64 ++#define RAMSTART (0x60) ++#define RAMEND 0x15F ++#define XRAMEND RAMEND ++#define E2END 0xFF ++#define E2PAGESIZE 4 ++#define FLASHEND 0xFFF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x92 ++#define SIGNATURE_2 0x08 ++ ++ ++#endif /* _AVR_IOTN461_H_ */ +diff --git a/include/avr/iotn461a.h b/include/avr/iotn461a.h +index aadb2c2..59f15e0 100644 +--- a/include/avr/iotn461a.h ++++ b/include/avr/iotn461a.h +@@ -1,976 +1,976 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn461a.h 2063 2009-11-18 22:06:28Z arcanum $ */ +- +-/* avr/iotn461a.h - definitions for ATtiny461A */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn461a.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATtiny461A_H_ +-#define _AVR_ATtiny461A_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define TCCR1E _SFR_IO8(0x00) +-#define OC1OE0 0 +-#define OC1OE1 1 +-#define OC1OE2 2 +-#define OC1OE3 3 +-#define OC1OE4 4 +-#define OC1OE5 5 +- +-#define DIDR0 _SFR_IO8(0x01) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define AREFD 3 +-#define ADC3D 4 +-#define ADC4D 5 +-#define ADC5D 6 +-#define ADC6D 7 +- +-#define DIDR1 _SFR_IO8(0x02) +-#define ADC7D 4 +-#define ADC8D 5 +-#define ADC9D 6 +-#define ADC10D 7 +- +-#define ADCSRB _SFR_IO8(0x03) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define MUX5 3 +-#define REFS2 4 +-#define IPR 5 +-#define GSEL 6 +-#define BIN 7 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x04) +-#endif +-#define ADCW _SFR_IO16(0x04) +- +-#define ADCL _SFR_IO8(0x04) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_IO8(0x05) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_IO8(0x06) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADMUX _SFR_IO8(0x07) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define ACSRA _SFR_IO8(0x08) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACME 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define ACSRB _SFR_IO8(0x09) +-#define ACM0 0 +-#define ACM1 1 +-#define ACM2 2 +-#define HLEV 6 +-#define HSEL 7 +- +-#define GPIOR0 _SFR_IO8(0x0A) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define GPIOR1 _SFR_IO8(0x0B) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x0C) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define USICR _SFR_IO8(0x0D) +-#define USITC 0 +-#define USICLK 1 +-#define USICS0 2 +-#define USICS1 3 +-#define USIWM0 4 +-#define USIWM1 5 +-#define USIOIE 6 +-#define USISIE 7 +- +-#define USISR _SFR_IO8(0x0E) +-#define USICNT0 0 +-#define USICNT1 1 +-#define USICNT2 2 +-#define USICNT3 3 +-#define USIDC 4 +-#define USIPF 5 +-#define USIOIF 6 +-#define USISIF 7 +- +-#define USIDR _SFR_IO8(0x0F) +-#define USIDR0 0 +-#define USIDR1 1 +-#define USIDR2 2 +-#define USIDR3 3 +-#define USIDR4 4 +-#define USIDR5 5 +-#define USIDR6 6 +-#define USIDR7 7 +- +-#define USIBR _SFR_IO8(0x10) +-#define USIBR0 0 +-#define USIBR1 1 +-#define USIBR2 2 +-#define USIBR3 3 +-#define USIBR4 4 +-#define USIBR5 5 +-#define USIBR6 6 +-#define USIBR7 7 +- +-#define USIPP _SFR_IO8(0x11) +-#define USIPOS 0 +- +-#define OCR0B _SFR_IO8(0x12) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define OCR0A _SFR_IO8(0x13) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define TCNT0H _SFR_IO8(0x14) +-#define TCNT0H_0 0 +-#define TCNT0H_1 1 +-#define TCNT0H_2 2 +-#define TCNT0H_3 3 +-#define TCNT0H_4 4 +-#define TCNT0H_5 5 +-#define TCNT0H_6 6 +-#define TCNT0H_7 7 +- +-#define TCCR0A _SFR_IO8(0x15) +-#define WGM00 0 +-#define ACIC0 3 +-#define ICES0 4 +-#define ICNC0 5 +-#define ICEN0 6 +-#define TCW0 7 +- +-#define PINB _SFR_IO8(0x16) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x17) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x18) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINA _SFR_IO8(0x19) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +-#define PINA4 4 +-#define PINA5 5 +-#define PINA6 6 +-#define PINA7 7 +- +-#define DDRA _SFR_IO8(0x1A) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +-#define DDA4 4 +-#define DDA5 5 +-#define DDA6 6 +-#define DDA7 7 +- +-#define PORTA _SFR_IO8(0x1B) +-#define PORTA0 0 +-#define PORTA1 1 +-#define PORTA2 2 +-#define PORTA3 3 +-#define PORTA4 4 +-#define PORTA5 5 +-#define PORTA6 6 +-#define PORTA7 7 +- +-#define EECR _SFR_IO8(0x1C) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x1D) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x1E) +- +-#define EEARL _SFR_IO8(0x1E) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x1F) +-#define EEAR8 0 +- +-#define DWDR _SFR_IO8(0x20) +-#define DWDR0 0 +-#define DWDR1 1 +-#define DWDR2 2 +-#define DWDR3 3 +-#define DWDR4 4 +-#define DWDR5 5 +-#define DWDR6 6 +-#define DWDR7 7 +- +-#define WDTCR _SFR_IO8(0x21) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define PCMSK1 _SFR_IO8(0x22) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-#define PCMSK0 _SFR_IO8(0x23) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define DT1 _SFR_IO8(0x24) +-#define DT1L0 0 +-#define DT1L1 1 +-#define DT1L2 2 +-#define DT1L3 3 +-#define DT1H0 4 +-#define DT1H1 5 +-#define DT1H2 6 +-#define DT1H3 7 +- +-#define TC1H _SFR_IO8(0x25) +-#define TC18 0 +-#define TC19 1 +- +-#define TCCR1D _SFR_IO8(0x26) +-#define WGM10 0 +-#define WGM11 1 +-#define FPF1 2 +-#define FPAC1 3 +-#define FPES1 4 +-#define FPNC1 5 +-#define FPEN1 6 +-#define FPIE1 7 +- +-#define TCCR1C _SFR_IO8(0x27) +-#define PWM1D 0 +-#define FOC1D 1 +-#define COM1D0 2 +-#define COM1D1 3 +-#define COM1B0S 4 +-#define COM1B1S 5 +-#define COM1A0S 6 +-#define COM1A1S 7 +- +-#define CLKPR _SFR_IO8(0x28) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define PLLCSR _SFR_IO8(0x29) +-#define PLOCK 0 +-#define PLLE 1 +-#define PCKE 2 +-#define LSM 7 +- +-#define OCR1D _SFR_IO8(0x2A) +-#define OCR1D0 0 +-#define OCR1D1 1 +-#define OCR1D2 2 +-#define OCR1D3 3 +-#define OCR1D4 4 +-#define OCR1D5 5 +-#define OCR1D6 6 +-#define OCR1D7 7 +- +-#define OCR1C _SFR_IO8(0x2B) +-#define OCR1C0 0 +-#define OCR1C1 1 +-#define OCR1C2 2 +-#define OCR1C3 3 +-#define OCR1C4 4 +-#define OCR1C5 5 +-#define OCR1C6 6 +-#define OCR1C7 7 +- +-#define OCR1B _SFR_IO8(0x2C) +-#define OCR1B0 0 +-#define OCR1B1 1 +-#define OCR1B2 2 +-#define OCR1B3 3 +-#define OCR1B4 4 +-#define OCR1B5 5 +-#define OCR1B6 6 +-#define OCR1B7 7 +- +-#define OCR1A _SFR_IO8(0x2D) +-#define OCR1A0 0 +-#define OCR1A1 1 +-#define OCR1A2 2 +-#define OCR1A3 3 +-#define OCR1A4 4 +-#define OCR1A5 5 +-#define OCR1A6 6 +-#define OCR1A7 7 +- +-#define TCNT1 _SFR_IO8(0x2E) +-#define TC1H_0 0 +-#define TC1H_1 1 +-#define TC1H_2 2 +-#define TC1H_3 3 +-#define TC1H_4 4 +-#define TC1H_5 5 +-#define TC1H_6 6 +-#define TC1H_7 7 +- +-#define TCCR1B _SFR_IO8(0x2F) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define CS13 3 +-#define DTPS10 4 +-#define DTPS11 5 +-#define PSR1 6 +- +-#define TCCR1A _SFR_IO8(0x30) +-#define PWM1B 0 +-#define PWM1A 1 +-#define FOC1B 2 +-#define FOC1A 3 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define OSCCAL _SFR_IO8(0x31) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define TCNT0L _SFR_IO8(0x32) +-#define TCNT0L_0 0 +-#define TCNT0L_1 1 +-#define TCNT0L_2 2 +-#define TCNT0L_3 3 +-#define TCNT0L_4 4 +-#define TCNT0L_5 5 +-#define TCNT0L_6 6 +-#define TCNT0L_7 7 +- +-#define TCCR0B _SFR_IO8(0x33) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define PSR0 3 +-#define TSM 4 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x35) +-#define ISC00 0 +-#define ISC01 1 +-#define BODSE 2 +-#define SM0 3 +-#define SM1 4 +-#define SE 5 +-#define PUD 6 +-#define BODS 7 +- +-#define PRR _SFR_IO8(0x36) +-#define PRADC 0 +-#define PRUSI 1 +-#define PRTIM0 2 +-#define PRTIM1 3 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define RFLB 3 +-#define CTPB 4 +- +-#define TIFR _SFR_IO8(0x38) +-#define ICF0 0 +-#define TOV0 1 +-#define TOV1 2 +-#define OCF0B 3 +-#define OCF0A 4 +-#define OCF1B 5 +-#define OCF1A 6 +-#define OCF1D 7 +- +-#define TIMSK _SFR_IO8(0x39) +-#define TICIE0 0 +-#define TOIE0 1 +-#define TOIE1 2 +-#define OCIE0B 3 +-#define OCIE0A 4 +-#define OCIE1B 5 +-#define OCIE1A 6 +-#define OCIE1D 7 +- +-#define GIFR _SFR_IO8(0x3A) +-#define PCIF 5 +-#define INTF0 6 +-#define INTF1 7 +- +-#define GIMSK _SFR_IO8(0x3B) +-#define PCIE0 4 +-#define PCIE1 5 +-#define INT0 6 +-#define INT1 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt 0 */ +-#define PCINT_vect_num 2 +-#define PCINT_vect _VECTOR(2) /* Pin Change Interrupt */ +-#define TIMER1_COMPA_vect_num 3 +-#define TIMER1_COMPA_vect _VECTOR(3) /* Timer/Counter1 Compare Match 1A */ +-#define TIMER1_COMPB_vect_num 4 +-#define TIMER1_COMPB_vect _VECTOR(4) /* Timer/Counter1 Compare Match 1B */ +-#define TIMER1_OVF_vect_num 5 +-#define TIMER1_OVF_vect _VECTOR(5) /* Timer/Counter1 Overflow */ +-#define TIMER0_OVF_vect_num 6 +-#define TIMER0_OVF_vect _VECTOR(6) /* Timer/Counter0 Overflow */ +-#define USI_START_vect_num 7 +-#define USI_START_vect _VECTOR(7) /* USI Start */ +-#define USI_OVF_vect_num 8 +-#define USI_OVF_vect _VECTOR(8) /* USI Overflow */ +-#define EE_RDY_vect_num 9 +-#define EE_RDY_vect _VECTOR(9) /* EEPROM Ready */ +-#define ANA_COMP_vect_num 10 +-#define ANA_COMP_vect _VECTOR(10) /* Analog Comparator */ +-#define ADC_vect_num 11 +-#define ADC_vect _VECTOR(11) /* ADC Conversion Complete */ +-#define WDT_vect_num 12 +-#define WDT_vect _VECTOR(12) /* Watchdog Time-Out */ +-#define INT1_vect_num 13 +-#define INT1_vect _VECTOR(13) /* External Interrupt 1 */ +-#define TIMER0_COMPA_vect_num 14 +-#define TIMER0_COMPA_vect _VECTOR(14) /* Timer/Counter0 Compare Match A */ +-#define TIMER0_COMPB_vect_num 15 +-#define TIMER0_COMPB_vect _VECTOR(15) /* Timer/Counter0 Compare Match B */ +-#define TIMER0_CAPT_vect_num 16 +-#define TIMER0_CAPT_vect _VECTOR(16) /* ADC Conversion Complete */ +-#define TIMER1_COMPD_vect_num 17 +-#define TIMER1_COMPD_vect _VECTOR(17) /* Timer/Counter1 Compare Match D */ +-#define FAULT_PROTECTION_vect_num 18 +-#define FAULT_PROTECTION_vect _VECTOR(18) /* Timer/Counter1 Fault Protection */ +- +-#define _VECTOR_SIZE 2 /* Size of individual vector. */ +-#define _VECTORS_SIZE (19 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (64) +-#define RAMSTART (0x60) +-#define RAMSIZE (256) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0xFF) +-#define E2PAGESIZE (4) +-#define FLASHEND (0xFFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x92 +-#define SIGNATURE_2 0x08 +- +- +-/* Device Pin Definitions */ +-#define DI_B_DDR DDRMOSI +-#define DI_B_PORT PORTMOSI +-#define DI_B_PIN PINMOSI +-#define DI_B_BIT MOSI +- +-#define SDA_B_DDR DDRMOSI +-#define SDA_B_PORT PORTMOSI +-#define SDA_B_PIN PINMOSI +-#define SDA_B_BIT MOSI +- +-#define _OC1A_DDR DDRMOSI +-#define _OC1A_PORT PORTMOSI +-#define _OC1A_PIN PINMOSI +-#define _OC1A_BIT MOSI +- +-#define PCINT8_DDR DDRMOSI +-#define PCINT8_PORT PORTMOSI +-#define PCINT8_PIN PINMOSI +-#define PCINT8_BIT MOSI +- +-#define PB0_DDR DDRMOSI +-#define PB0_PORT PORTMOSI +-#define PB0_PIN PINMOSI +-#define PB0_BIT MOSI +- +-#define DO_B_DDR DDRMISO +-#define DO_B_PORT PORTMISO +-#define DO_B_PIN PINMISO +-#define DO_B_BIT MISO +- +-#define OC1A_DDR DDRMISO +-#define OC1A_PORT PORTMISO +-#define OC1A_PIN PINMISO +-#define OC1A_BIT MISO +- +-#define PCINT9_DDR DDRMISO +-#define PCINT9_PORT PORTMISO +-#define PCINT9_PIN PINMISO +-#define PCINT9_BIT MISO +- +-#define PB1_DDR DDRMISO +-#define PB1_PORT PORTMISO +-#define PB1_PIN PINMISO +-#define PB1_BIT MISO +- +-#define USCK_B_DDR DDRSCK +-#define USCK_B_PORT PORTSCK +-#define USCK_B_PIN PINSCK +-#define USCK_B_BIT SCK +- +-#define SCL_B_DDR DDRSCK +-#define SCL_B_PORT PORTSCK +-#define SCL_B_PIN PINSCK +-#define SCL_B_BIT SCK +- +-#define OC1B_DDR DDRSCK +-#define OC1B_PORT PORTSCK +-#define OC1B_PIN PINSCK +-#define OC1B_BIT SCK +- +-#define PCINT10_DDR DDRSCK +-#define PCINT10_PORT PORTSCK +-#define PCINT10_PIN PINSCK +-#define PCINT10_BIT SCK +- +-#define PB2_DDR DDRSCK +-#define PB2_PORT PORTSCK +-#define PB2_PIN PINSCK +-#define PB2_BIT SCK +- +-#define PCINT11_DDR DDROC1B +-#define PCINT11_PORT PORTOC1B +-#define PCINT11_PIN PINOC1B +-#define PCINT11_BIT OC1B +- +-#define PB3_DDR DDROC1B +-#define PB3_PORT PORTOC1B +-#define PB3_PIN PINOC1B +-#define PB3_BIT OC1B +- +-#define PCINT12_DDR DDRADC +-#define PCINT12_PORT PORTADC +-#define PCINT12_PIN PINADC +-#define PCINT12_BIT ADC7 +- +-#define _OC1D_DDR DDRADC +-#define _OC1D_PORT PORTADC +-#define _OC1D_PIN PINADC +-#define _OC1D_BIT ADC7 +- +-#define CLKI_DDR DDRADC +-#define CLKI_PORT PORTADC +-#define CLKI_PIN PINADC +-#define CLKI_BIT ADC7 +- +-#define PB4_DDR DDRADC +-#define PB4_PORT PORTADC +-#define PB4_PIN PINADC +-#define PB4_BIT ADC7 +- +-#define PCINT13_DDR DDRADC +-#define PCINT13_PORT PORTADC +-#define PCINT13_PIN PINADC +-#define PCINT13_BIT ADC8 +- +-#define OC1D_DDR DDRADC +-#define OC1D_PORT PORTADC +-#define OC1D_PIN PINADC +-#define OC1D_BIT ADC8 +- +-#define CKLO_DDR DDRADC +-#define CKLO_PORT PORTADC +-#define CKLO_PIN PINADC +-#define CKLO_BIT ADC8 +- +-#define PB5_DDR DDRADC +-#define PB5_PORT PORTADC +-#define PB5_PIN PINADC +-#define PB5_BIT ADC8 +- +-#define INT0_DDR DDRADC +-#define INT0_PORT PORTADC +-#define INT0_PIN PINADC +-#define INT0_BIT ADC9 +- +-#define T0_DDR DDRADC +-#define T0_PORT PORTADC +-#define T0_PIN PINADC +-#define T0_BIT ADC9 +- +-#define PCINT14_DDR DDRADC +-#define PCINT14_PORT PORTADC +-#define PCINT14_PIN PINADC +-#define PCINT14_BIT ADC9 +- +-#define PB6_DDR DDRADC +-#define PB6_PORT PORTADC +-#define PB6_PIN PINADC +-#define PB6_BIT ADC9 +- +-#define PCINT15_DDR DDRADC1 +-#define PCINT15_PORT PORTADC1 +-#define PCINT15_PIN PINADC1 +-#define PCINT15_BIT ADC10 +- +-#define PB7_DDR DDRADC1 +-#define PB7_PORT PORTADC1 +-#define PB7_PIN PINADC1 +-#define PB7_BIT ADC10 +- +-#define AIN1_DDR DDRADC +-#define AIN1_PORT PORTADC +-#define AIN1_PIN PINADC +-#define AIN1_BIT ADC6 +- +-#define PCINT7_DDR DDRADC +-#define PCINT7_PORT PORTADC +-#define PCINT7_PIN PINADC +-#define PCINT7_BIT ADC6 +- +-#define PA7_DDR DDRADC +-#define PA7_PORT PORTADC +-#define PA7_PIN PINADC +-#define PA7_BIT ADC6 +- +-#define AIN0_DDR DDRADC +-#define AIN0_PORT PORTADC +-#define AIN0_PIN PINADC +-#define AIN0_BIT ADC5 +- +-#define PCINT6_DDR DDRADC +-#define PCINT6_PORT PORTADC +-#define PCINT6_PIN PINADC +-#define PCINT6_BIT ADC5 +- +-#define PA6_DDR DDRADC +-#define PA6_PORT PORTADC +-#define PA6_PIN PINADC +-#define PA6_BIT ADC5 +- +-#define AIN2_DDR DDRADC +-#define AIN2_PORT PORTADC +-#define AIN2_PIN PINADC +-#define AIN2_BIT ADC4 +- +-#define PCINT5_DDR DDRADC +-#define PCINT5_PORT PORTADC +-#define PCINT5_PIN PINADC +-#define PCINT5_BIT ADC4 +- +-#define PA5_DDR DDRADC +-#define PA5_PORT PORTADC +-#define PA5_PIN PINADC +-#define PA5_BIT ADC4 +- +-#define ICP0_DDR DDRADC +-#define ICP0_PORT PORTADC +-#define ICP0_PIN PINADC +-#define ICP0_BIT ADC3 +- +-#define PCINT4_DDR DDRADC +-#define PCINT4_PORT PORTADC +-#define PCINT4_PIN PINADC +-#define PCINT4_BIT ADC3 +- +-#define PA4_DDR DDRADC +-#define PA4_PORT PORTADC +-#define PA4_PIN PINADC +-#define PA4_BIT ADC3 +- +-#define PCINT3_DDR DDRAREF +-#define PCINT3_PORT PORTAREF +-#define PCINT3_PIN PINAREF +-#define PCINT3_BIT AREF +- +-#define PA3_DDR DDRAREF +-#define PA3_PORT PORTAREF +-#define PA3_PIN PINAREF +-#define PA3_BIT AREF +- +-#define INT1_DDR DDRADC +-#define INT1_PORT PORTADC +-#define INT1_PIN PINADC +-#define INT1_BIT ADC2 +- +-#define USCK_A_DDR DDRADC +-#define USCK_A_PORT PORTADC +-#define USCK_A_PIN PINADC +-#define USCK_A_BIT ADC2 +- +-#define SCL_A_DDR DDRADC +-#define SCL_A_PORT PORTADC +-#define SCL_A_PIN PINADC +-#define SCL_A_BIT ADC2 +- +-#define PCINT2_DDR DDRADC +-#define PCINT2_PORT PORTADC +-#define PCINT2_PIN PINADC +-#define PCINT2_BIT ADC2 +- +-#define PA2_DDR DDRADC +-#define PA2_PORT PORTADC +-#define PA2_PIN PINADC +-#define PA2_BIT ADC2 +- +-#define DO_A_DDR DDRADC +-#define DO_A_PORT PORTADC +-#define DO_A_PIN PINADC +-#define DO_A_BIT ADC1 +- +-#define PCINT1_DDR DDRADC +-#define PCINT1_PORT PORTADC +-#define PCINT1_PIN PINADC +-#define PCINT1_BIT ADC1 +- +-#define PA1_DDR DDRADC +-#define PA1_PORT PORTADC +-#define PA1_PIN PINADC +-#define PA1_BIT ADC1 +- +-#define DI_A_DDR DDRADC +-#define DI_A_PORT PORTADC +-#define DI_A_PIN PINADC +-#define DI_A_BIT ADC0 +- +-#define SDA_A_DDR DDRADC +-#define SDA_A_PORT PORTADC +-#define SDA_A_PIN PINADC +-#define SDA_A_BIT ADC0 +- +-#define PCINT0_DDR DDRADC +-#define PCINT0_PORT PORTADC +-#define PCINT0_PIN PINADC +-#define PCINT0_BIT ADC0 +- +-#define PA0_DDR DDRADC +-#define PA0_PORT PORTADC +-#define PA0_PIN PINADC +-#define PA0_BIT ADC0 +- +-#endif /* _AVR_ATtiny461A_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn461a.h 2063 2009-11-18 22:06:28Z arcanum $ */ ++ ++/* avr/iotn461a.h - definitions for ATtiny461A */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn461a.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATtiny461A_H_ ++#define _AVR_ATtiny461A_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define TCCR1E _SFR_IO8(0x00) ++#define OC1OE0 0 ++#define OC1OE1 1 ++#define OC1OE2 2 ++#define OC1OE3 3 ++#define OC1OE4 4 ++#define OC1OE5 5 ++ ++#define DIDR0 _SFR_IO8(0x01) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define AREFD 3 ++#define ADC3D 4 ++#define ADC4D 5 ++#define ADC5D 6 ++#define ADC6D 7 ++ ++#define DIDR1 _SFR_IO8(0x02) ++#define ADC7D 4 ++#define ADC8D 5 ++#define ADC9D 6 ++#define ADC10D 7 ++ ++#define ADCSRB _SFR_IO8(0x03) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define MUX5 3 ++#define REFS2 4 ++#define IPR 5 ++#define GSEL 6 ++#define BIN 7 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCW _SFR_IO16(0x04) ++ ++#define ADCL _SFR_IO8(0x04) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_IO8(0x05) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_IO8(0x06) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADMUX _SFR_IO8(0x07) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define ACSRA _SFR_IO8(0x08) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACME 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define ACSRB _SFR_IO8(0x09) ++#define ACM0 0 ++#define ACM1 1 ++#define ACM2 2 ++#define HLEV 6 ++#define HSEL 7 ++ ++#define GPIOR0 _SFR_IO8(0x0A) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define GPIOR1 _SFR_IO8(0x0B) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x0C) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define USICR _SFR_IO8(0x0D) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_IO8(0x0E) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_IO8(0x0F) ++#define USIDR0 0 ++#define USIDR1 1 ++#define USIDR2 2 ++#define USIDR3 3 ++#define USIDR4 4 ++#define USIDR5 5 ++#define USIDR6 6 ++#define USIDR7 7 ++ ++#define USIBR _SFR_IO8(0x10) ++#define USIBR0 0 ++#define USIBR1 1 ++#define USIBR2 2 ++#define USIBR3 3 ++#define USIBR4 4 ++#define USIBR5 5 ++#define USIBR6 6 ++#define USIBR7 7 ++ ++#define USIPP _SFR_IO8(0x11) ++#define USIPOS 0 ++ ++#define OCR0B _SFR_IO8(0x12) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define OCR0A _SFR_IO8(0x13) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define TCNT0H _SFR_IO8(0x14) ++#define TCNT0H_0 0 ++#define TCNT0H_1 1 ++#define TCNT0H_2 2 ++#define TCNT0H_3 3 ++#define TCNT0H_4 4 ++#define TCNT0H_5 5 ++#define TCNT0H_6 6 ++#define TCNT0H_7 7 ++ ++#define TCCR0A _SFR_IO8(0x15) ++#define WGM00 0 ++#define ACIC0 3 ++#define ICES0 4 ++#define ICNC0 5 ++#define ICEN0 6 ++#define TCW0 7 ++ ++#define PINB _SFR_IO8(0x16) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x17) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x18) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINA _SFR_IO8(0x19) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++#define PINA4 4 ++#define PINA5 5 ++#define PINA6 6 ++#define PINA7 7 ++ ++#define DDRA _SFR_IO8(0x1A) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++#define DDA4 4 ++#define DDA5 5 ++#define DDA6 6 ++#define DDA7 7 ++ ++#define PORTA _SFR_IO8(0x1B) ++#define PORTA0 0 ++#define PORTA1 1 ++#define PORTA2 2 ++#define PORTA3 3 ++#define PORTA4 4 ++#define PORTA5 5 ++#define PORTA6 6 ++#define PORTA7 7 ++ ++#define EECR _SFR_IO8(0x1C) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x1D) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x1E) ++ ++#define EEARL _SFR_IO8(0x1E) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x1F) ++#define EEAR8 0 ++ ++#define DWDR _SFR_IO8(0x20) ++#define DWDR0 0 ++#define DWDR1 1 ++#define DWDR2 2 ++#define DWDR3 3 ++#define DWDR4 4 ++#define DWDR5 5 ++#define DWDR6 6 ++#define DWDR7 7 ++ ++#define WDTCR _SFR_IO8(0x21) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define PCMSK1 _SFR_IO8(0x22) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK0 _SFR_IO8(0x23) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define DT1 _SFR_IO8(0x24) ++#define DT1L0 0 ++#define DT1L1 1 ++#define DT1L2 2 ++#define DT1L3 3 ++#define DT1H0 4 ++#define DT1H1 5 ++#define DT1H2 6 ++#define DT1H3 7 ++ ++#define TC1H _SFR_IO8(0x25) ++#define TC18 0 ++#define TC19 1 ++ ++#define TCCR1D _SFR_IO8(0x26) ++#define WGM10 0 ++#define WGM11 1 ++#define FPF1 2 ++#define FPAC1 3 ++#define FPES1 4 ++#define FPNC1 5 ++#define FPEN1 6 ++#define FPIE1 7 ++ ++#define TCCR1C _SFR_IO8(0x27) ++#define PWM1D 0 ++#define FOC1D 1 ++#define COM1D0 2 ++#define COM1D1 3 ++#define COM1B0S 4 ++#define COM1B1S 5 ++#define COM1A0S 6 ++#define COM1A1S 7 ++ ++#define CLKPR _SFR_IO8(0x28) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define PLLCSR _SFR_IO8(0x29) ++#define PLOCK 0 ++#define PLLE 1 ++#define PCKE 2 ++#define LSM 7 ++ ++#define OCR1D _SFR_IO8(0x2A) ++#define OCR1D0 0 ++#define OCR1D1 1 ++#define OCR1D2 2 ++#define OCR1D3 3 ++#define OCR1D4 4 ++#define OCR1D5 5 ++#define OCR1D6 6 ++#define OCR1D7 7 ++ ++#define OCR1C _SFR_IO8(0x2B) ++#define OCR1C0 0 ++#define OCR1C1 1 ++#define OCR1C2 2 ++#define OCR1C3 3 ++#define OCR1C4 4 ++#define OCR1C5 5 ++#define OCR1C6 6 ++#define OCR1C7 7 ++ ++#define OCR1B _SFR_IO8(0x2C) ++#define OCR1B0 0 ++#define OCR1B1 1 ++#define OCR1B2 2 ++#define OCR1B3 3 ++#define OCR1B4 4 ++#define OCR1B5 5 ++#define OCR1B6 6 ++#define OCR1B7 7 ++ ++#define OCR1A _SFR_IO8(0x2D) ++#define OCR1A0 0 ++#define OCR1A1 1 ++#define OCR1A2 2 ++#define OCR1A3 3 ++#define OCR1A4 4 ++#define OCR1A5 5 ++#define OCR1A6 6 ++#define OCR1A7 7 ++ ++#define TCNT1 _SFR_IO8(0x2E) ++#define TC1H_0 0 ++#define TC1H_1 1 ++#define TC1H_2 2 ++#define TC1H_3 3 ++#define TC1H_4 4 ++#define TC1H_5 5 ++#define TC1H_6 6 ++#define TC1H_7 7 ++ ++#define TCCR1B _SFR_IO8(0x2F) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define CS13 3 ++#define DTPS10 4 ++#define DTPS11 5 ++#define PSR1 6 ++ ++#define TCCR1A _SFR_IO8(0x30) ++#define PWM1B 0 ++#define PWM1A 1 ++#define FOC1B 2 ++#define FOC1A 3 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define OSCCAL _SFR_IO8(0x31) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define TCNT0L _SFR_IO8(0x32) ++#define TCNT0L_0 0 ++#define TCNT0L_1 1 ++#define TCNT0L_2 2 ++#define TCNT0L_3 3 ++#define TCNT0L_4 4 ++#define TCNT0L_5 5 ++#define TCNT0L_6 6 ++#define TCNT0L_7 7 ++ ++#define TCCR0B _SFR_IO8(0x33) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define PSR0 3 ++#define TSM 4 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define ISC00 0 ++#define ISC01 1 ++#define BODSE 2 ++#define SM0 3 ++#define SM1 4 ++#define SE 5 ++#define PUD 6 ++#define BODS 7 ++ ++#define PRR _SFR_IO8(0x36) ++#define PRADC 0 ++#define PRUSI 1 ++#define PRTIM0 2 ++#define PRTIM1 3 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define RFLB 3 ++#define CTPB 4 ++ ++#define TIFR _SFR_IO8(0x38) ++#define ICF0 0 ++#define TOV0 1 ++#define TOV1 2 ++#define OCF0B 3 ++#define OCF0A 4 ++#define OCF1B 5 ++#define OCF1A 6 ++#define OCF1D 7 ++ ++#define TIMSK _SFR_IO8(0x39) ++#define TICIE0 0 ++#define TOIE0 1 ++#define TOIE1 2 ++#define OCIE0B 3 ++#define OCIE0A 4 ++#define OCIE1B 5 ++#define OCIE1A 6 ++#define OCIE1D 7 ++ ++#define GIFR _SFR_IO8(0x3A) ++#define PCIF 5 ++#define INTF0 6 ++#define INTF1 7 ++ ++#define GIMSK _SFR_IO8(0x3B) ++#define PCIE0 4 ++#define PCIE1 5 ++#define INT0 6 ++#define INT1 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt 0 */ ++#define PCINT_vect_num 2 ++#define PCINT_vect _VECTOR(2) /* Pin Change Interrupt */ ++#define TIMER1_COMPA_vect_num 3 ++#define TIMER1_COMPA_vect _VECTOR(3) /* Timer/Counter1 Compare Match 1A */ ++#define TIMER1_COMPB_vect_num 4 ++#define TIMER1_COMPB_vect _VECTOR(4) /* Timer/Counter1 Compare Match 1B */ ++#define TIMER1_OVF_vect_num 5 ++#define TIMER1_OVF_vect _VECTOR(5) /* Timer/Counter1 Overflow */ ++#define TIMER0_OVF_vect_num 6 ++#define TIMER0_OVF_vect _VECTOR(6) /* Timer/Counter0 Overflow */ ++#define USI_START_vect_num 7 ++#define USI_START_vect _VECTOR(7) /* USI Start */ ++#define USI_OVF_vect_num 8 ++#define USI_OVF_vect _VECTOR(8) /* USI Overflow */ ++#define EE_RDY_vect_num 9 ++#define EE_RDY_vect _VECTOR(9) /* EEPROM Ready */ ++#define ANA_COMP_vect_num 10 ++#define ANA_COMP_vect _VECTOR(10) /* Analog Comparator */ ++#define ADC_vect_num 11 ++#define ADC_vect _VECTOR(11) /* ADC Conversion Complete */ ++#define WDT_vect_num 12 ++#define WDT_vect _VECTOR(12) /* Watchdog Time-Out */ ++#define INT1_vect_num 13 ++#define INT1_vect _VECTOR(13) /* External Interrupt 1 */ ++#define TIMER0_COMPA_vect_num 14 ++#define TIMER0_COMPA_vect _VECTOR(14) /* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPB_vect_num 15 ++#define TIMER0_COMPB_vect _VECTOR(15) /* Timer/Counter0 Compare Match B */ ++#define TIMER0_CAPT_vect_num 16 ++#define TIMER0_CAPT_vect _VECTOR(16) /* ADC Conversion Complete */ ++#define TIMER1_COMPD_vect_num 17 ++#define TIMER1_COMPD_vect _VECTOR(17) /* Timer/Counter1 Compare Match D */ ++#define FAULT_PROTECTION_vect_num 18 ++#define FAULT_PROTECTION_vect _VECTOR(18) /* Timer/Counter1 Fault Protection */ ++ ++#define _VECTOR_SIZE 2 /* Size of individual vector. */ ++#define _VECTORS_SIZE (19 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (64) ++#define RAMSTART (0x60) ++#define RAMSIZE (256) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0xFF) ++#define E2PAGESIZE (4) ++#define FLASHEND (0xFFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x92 ++#define SIGNATURE_2 0x08 ++ ++ ++/* Device Pin Definitions */ ++#define DI_B_DDR DDRMOSI ++#define DI_B_PORT PORTMOSI ++#define DI_B_PIN PINMOSI ++#define DI_B_BIT MOSI ++ ++#define SDA_B_DDR DDRMOSI ++#define SDA_B_PORT PORTMOSI ++#define SDA_B_PIN PINMOSI ++#define SDA_B_BIT MOSI ++ ++#define _OC1A_DDR DDRMOSI ++#define _OC1A_PORT PORTMOSI ++#define _OC1A_PIN PINMOSI ++#define _OC1A_BIT MOSI ++ ++#define PCINT8_DDR DDRMOSI ++#define PCINT8_PORT PORTMOSI ++#define PCINT8_PIN PINMOSI ++#define PCINT8_BIT MOSI ++ ++#define PB0_DDR DDRMOSI ++#define PB0_PORT PORTMOSI ++#define PB0_PIN PINMOSI ++#define PB0_BIT MOSI ++ ++#define DO_B_DDR DDRMISO ++#define DO_B_PORT PORTMISO ++#define DO_B_PIN PINMISO ++#define DO_B_BIT MISO ++ ++#define OC1A_DDR DDRMISO ++#define OC1A_PORT PORTMISO ++#define OC1A_PIN PINMISO ++#define OC1A_BIT MISO ++ ++#define PCINT9_DDR DDRMISO ++#define PCINT9_PORT PORTMISO ++#define PCINT9_PIN PINMISO ++#define PCINT9_BIT MISO ++ ++#define PB1_DDR DDRMISO ++#define PB1_PORT PORTMISO ++#define PB1_PIN PINMISO ++#define PB1_BIT MISO ++ ++#define USCK_B_DDR DDRSCK ++#define USCK_B_PORT PORTSCK ++#define USCK_B_PIN PINSCK ++#define USCK_B_BIT SCK ++ ++#define SCL_B_DDR DDRSCK ++#define SCL_B_PORT PORTSCK ++#define SCL_B_PIN PINSCK ++#define SCL_B_BIT SCK ++ ++#define OC1B_DDR DDRSCK ++#define OC1B_PORT PORTSCK ++#define OC1B_PIN PINSCK ++#define OC1B_BIT SCK ++ ++#define PCINT10_DDR DDRSCK ++#define PCINT10_PORT PORTSCK ++#define PCINT10_PIN PINSCK ++#define PCINT10_BIT SCK ++ ++#define PB2_DDR DDRSCK ++#define PB2_PORT PORTSCK ++#define PB2_PIN PINSCK ++#define PB2_BIT SCK ++ ++#define PCINT11_DDR DDROC1B ++#define PCINT11_PORT PORTOC1B ++#define PCINT11_PIN PINOC1B ++#define PCINT11_BIT OC1B ++ ++#define PB3_DDR DDROC1B ++#define PB3_PORT PORTOC1B ++#define PB3_PIN PINOC1B ++#define PB3_BIT OC1B ++ ++#define PCINT12_DDR DDRADC ++#define PCINT12_PORT PORTADC ++#define PCINT12_PIN PINADC ++#define PCINT12_BIT ADC7 ++ ++#define _OC1D_DDR DDRADC ++#define _OC1D_PORT PORTADC ++#define _OC1D_PIN PINADC ++#define _OC1D_BIT ADC7 ++ ++#define CLKI_DDR DDRADC ++#define CLKI_PORT PORTADC ++#define CLKI_PIN PINADC ++#define CLKI_BIT ADC7 ++ ++#define PB4_DDR DDRADC ++#define PB4_PORT PORTADC ++#define PB4_PIN PINADC ++#define PB4_BIT ADC7 ++ ++#define PCINT13_DDR DDRADC ++#define PCINT13_PORT PORTADC ++#define PCINT13_PIN PINADC ++#define PCINT13_BIT ADC8 ++ ++#define OC1D_DDR DDRADC ++#define OC1D_PORT PORTADC ++#define OC1D_PIN PINADC ++#define OC1D_BIT ADC8 ++ ++#define CKLO_DDR DDRADC ++#define CKLO_PORT PORTADC ++#define CKLO_PIN PINADC ++#define CKLO_BIT ADC8 ++ ++#define PB5_DDR DDRADC ++#define PB5_PORT PORTADC ++#define PB5_PIN PINADC ++#define PB5_BIT ADC8 ++ ++#define INT0_DDR DDRADC ++#define INT0_PORT PORTADC ++#define INT0_PIN PINADC ++#define INT0_BIT ADC9 ++ ++#define T0_DDR DDRADC ++#define T0_PORT PORTADC ++#define T0_PIN PINADC ++#define T0_BIT ADC9 ++ ++#define PCINT14_DDR DDRADC ++#define PCINT14_PORT PORTADC ++#define PCINT14_PIN PINADC ++#define PCINT14_BIT ADC9 ++ ++#define PB6_DDR DDRADC ++#define PB6_PORT PORTADC ++#define PB6_PIN PINADC ++#define PB6_BIT ADC9 ++ ++#define PCINT15_DDR DDRADC1 ++#define PCINT15_PORT PORTADC1 ++#define PCINT15_PIN PINADC1 ++#define PCINT15_BIT ADC10 ++ ++#define PB7_DDR DDRADC1 ++#define PB7_PORT PORTADC1 ++#define PB7_PIN PINADC1 ++#define PB7_BIT ADC10 ++ ++#define AIN1_DDR DDRADC ++#define AIN1_PORT PORTADC ++#define AIN1_PIN PINADC ++#define AIN1_BIT ADC6 ++ ++#define PCINT7_DDR DDRADC ++#define PCINT7_PORT PORTADC ++#define PCINT7_PIN PINADC ++#define PCINT7_BIT ADC6 ++ ++#define PA7_DDR DDRADC ++#define PA7_PORT PORTADC ++#define PA7_PIN PINADC ++#define PA7_BIT ADC6 ++ ++#define AIN0_DDR DDRADC ++#define AIN0_PORT PORTADC ++#define AIN0_PIN PINADC ++#define AIN0_BIT ADC5 ++ ++#define PCINT6_DDR DDRADC ++#define PCINT6_PORT PORTADC ++#define PCINT6_PIN PINADC ++#define PCINT6_BIT ADC5 ++ ++#define PA6_DDR DDRADC ++#define PA6_PORT PORTADC ++#define PA6_PIN PINADC ++#define PA6_BIT ADC5 ++ ++#define AIN2_DDR DDRADC ++#define AIN2_PORT PORTADC ++#define AIN2_PIN PINADC ++#define AIN2_BIT ADC4 ++ ++#define PCINT5_DDR DDRADC ++#define PCINT5_PORT PORTADC ++#define PCINT5_PIN PINADC ++#define PCINT5_BIT ADC4 ++ ++#define PA5_DDR DDRADC ++#define PA5_PORT PORTADC ++#define PA5_PIN PINADC ++#define PA5_BIT ADC4 ++ ++#define ICP0_DDR DDRADC ++#define ICP0_PORT PORTADC ++#define ICP0_PIN PINADC ++#define ICP0_BIT ADC3 ++ ++#define PCINT4_DDR DDRADC ++#define PCINT4_PORT PORTADC ++#define PCINT4_PIN PINADC ++#define PCINT4_BIT ADC3 ++ ++#define PA4_DDR DDRADC ++#define PA4_PORT PORTADC ++#define PA4_PIN PINADC ++#define PA4_BIT ADC3 ++ ++#define PCINT3_DDR DDRAREF ++#define PCINT3_PORT PORTAREF ++#define PCINT3_PIN PINAREF ++#define PCINT3_BIT AREF ++ ++#define PA3_DDR DDRAREF ++#define PA3_PORT PORTAREF ++#define PA3_PIN PINAREF ++#define PA3_BIT AREF ++ ++#define INT1_DDR DDRADC ++#define INT1_PORT PORTADC ++#define INT1_PIN PINADC ++#define INT1_BIT ADC2 ++ ++#define USCK_A_DDR DDRADC ++#define USCK_A_PORT PORTADC ++#define USCK_A_PIN PINADC ++#define USCK_A_BIT ADC2 ++ ++#define SCL_A_DDR DDRADC ++#define SCL_A_PORT PORTADC ++#define SCL_A_PIN PINADC ++#define SCL_A_BIT ADC2 ++ ++#define PCINT2_DDR DDRADC ++#define PCINT2_PORT PORTADC ++#define PCINT2_PIN PINADC ++#define PCINT2_BIT ADC2 ++ ++#define PA2_DDR DDRADC ++#define PA2_PORT PORTADC ++#define PA2_PIN PINADC ++#define PA2_BIT ADC2 ++ ++#define DO_A_DDR DDRADC ++#define DO_A_PORT PORTADC ++#define DO_A_PIN PINADC ++#define DO_A_BIT ADC1 ++ ++#define PCINT1_DDR DDRADC ++#define PCINT1_PORT PORTADC ++#define PCINT1_PIN PINADC ++#define PCINT1_BIT ADC1 ++ ++#define PA1_DDR DDRADC ++#define PA1_PORT PORTADC ++#define PA1_PIN PINADC ++#define PA1_BIT ADC1 ++ ++#define DI_A_DDR DDRADC ++#define DI_A_PORT PORTADC ++#define DI_A_PIN PINADC ++#define DI_A_BIT ADC0 ++ ++#define SDA_A_DDR DDRADC ++#define SDA_A_PORT PORTADC ++#define SDA_A_PIN PINADC ++#define SDA_A_BIT ADC0 ++ ++#define PCINT0_DDR DDRADC ++#define PCINT0_PORT PORTADC ++#define PCINT0_PIN PINADC ++#define PCINT0_BIT ADC0 ++ ++#define PA0_DDR DDRADC ++#define PA0_PORT PORTADC ++#define PA0_PIN PINADC ++#define PA0_BIT ADC0 ++ ++#endif /* _AVR_ATtiny461A_H_ */ ++ +diff --git a/include/avr/iotn48.h b/include/avr/iotn48.h +index 616cbf4..68777e5 100644 +--- a/include/avr/iotn48.h ++++ b/include/avr/iotn48.h +@@ -1,795 +1,795 @@ +-/* Copyright (c) 2007-2010 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. +-*/ +- +-/* $Id: iotn48.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* avr/iotn48.h - definitions for ATtiny48 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn48.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_IOTN48_H_ +-#define _AVR_IOTN48_H_ 1 +- +-/* Registers and associated bit numbers */ +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +-#define PINC7 7 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC3 3 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +-#define DDC7 7 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC3 3 +-#define PORTC4 4 +-#define PORTC5 5 +-#define PORTC6 6 +-#define PORTC7 7 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define PINA _SFR_IO8(0x0C) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +- +-#define DDRA _SFR_IO8(0x0D) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +- +-#define PORTA _SFR_IO8(0x0E) +-#define PORTA0 0 +-#define PORTA1 1 +-#define PORTA2 2 +-#define PORTA3 3 +- +-#define PORTCR _SFR_IO8(0x12) +-#define PUDA 0 +-#define PUDB 1 +-#define PUDC 2 +-#define PUDD 3 +-#define BBMA 4 +-#define BBMB 5 +-#define BBMC 6 +-#define BBMD 7 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +-#define PCIF1 1 +-#define PCIF2 2 +-#define PCIF3 3 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSRSYNC 0 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define CTC0 3 +- +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define OCR0A _SFR_IO8(0x27) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define OCR0B _SFR_IO8(0x28) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x35) +-#define PUD 4 +-#define BODSE 5 +-#define BODS 6 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SELFPRGEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define RFLB 3 +-#define CTPB 4 +-#define RWWSB 6 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRSPI 2 +-#define PRTIM1 3 +-#define PRTIM0 5 +-#define PRTWI 7 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +-#define PCIE1 1 +-#define PCIE2 2 +-#define PCIE3 3 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +- +-#define PCMSK3 _SFR_MEM8(0x6A) +-#define PCINT24 0 +-#define PCINT25 1 +-#define PCINT26 2 +-#define PCINT27 3 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-#define PCMSK2 _SFR_MEM8(0x6D) +-#define PCINT16 0 +-#define PCINT17 1 +-#define PCINT18 2 +-#define PCINT19 3 +-#define PCINT20 4 +-#define PCINT21 5 +-#define PCINT22 6 +-#define PCINT23 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +- +-#define ADCL _SFR_MEM8(0x78) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_MEM8(0x79) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ACME 6 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define ADLAR 5 +-#define REFS0 6 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define TWBR _SFR_MEM8(0xB8) +-#define TWBR0 0 +-#define TWBR1 1 +-#define TWBR2 2 +-#define TWBR3 3 +-#define TWBR4 4 +-#define TWBR5 5 +-#define TWBR6 6 +-#define TWBR7 7 +- +-#define TWSR _SFR_MEM8(0xB9) +-#define TWPS0 0 +-#define TWPS1 1 +-#define TWS3 3 +-#define TWS4 4 +-#define TWS5 5 +-#define TWS6 6 +-#define TWS7 7 +- +-#define TWAR _SFR_MEM8(0xBA) +-#define TWGCE 0 +-#define TWA0 1 +-#define TWA1 2 +-#define TWA2 3 +-#define TWA3 4 +-#define TWA4 5 +-#define TWA5 6 +-#define TWA6 7 +- +-#define TWDR _SFR_MEM8(0xBB) +-#define TWD0 0 +-#define TWD1 1 +-#define TWD2 2 +-#define TWD3 3 +-#define TWD4 4 +-#define TWD5 5 +-#define TWD6 6 +-#define TWD7 7 +- +-#define TWCR _SFR_MEM8(0xBC) +-#define TWIE 0 +-#define TWEN 2 +-#define TWWC 3 +-#define TWSTO 4 +-#define TWSTA 5 +-#define TWEA 6 +-#define TWINT 7 +- +-#define TWAMR _SFR_MEM8(0xBD) +-#define TWAM0 1 +-#define TWAM1 2 +-#define TWAM2 3 +-#define TWAM3 4 +-#define TWAM4 5 +-#define TWAM5 6 +-#define TWAM6 7 +- +-#define TWIHSR _SFR_MEM8(0xBE) /* Deprecated */ +-#define TWHSR _SFR_MEM8(0xBE) +-#define TWIHS 0 +- +- +-/* Interrupt Vectors */ +-/* Interrupt vector 0 is the reset vector. */ +- +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +- +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +- +-#define PCINT0_vect_num 3 +-#define PCINT0_vect _VECTOR(3) +- +-#define PCINT1_vect_num 4 +-#define PCINT1_vect _VECTOR(4) +- +-#define PCINT2_vect_num 5 +-#define PCINT2_vect _VECTOR(5) +- +-#define PCINT3_vect_num 6 +-#define PCINT3_vect _VECTOR(6) +- +-#define WDT_vect_num 7 +-#define WDT_vect _VECTOR(7) +- +-#define TIMER1_CAPT_vect_num 8 +-#define TIMER1_CAPT_vect _VECTOR(8) +- +-#define TIMER1_COMPA_vect_num 9 +-#define TIMER1_COMPA_vect _VECTOR(9) +- +-#define TIMER1_COMPB_vect_num 10 +-#define TIMER1_COMPB_vect _VECTOR(10) +- +-#define TIMER1_OVF_vect_num 11 +-#define TIMER1_OVF_vect _VECTOR(11) +- +-#define TIMER0_COMPA_vect_num 12 +-#define TIMER0_COMPA_vect _VECTOR(12) +- +-#define TIMER0_COMPB_vect_num 13 +-#define TIMER0_COMPB_vect _VECTOR(13) +- +-#define TIMER0_OVF_vect_num 14 +-#define TIMER0_OVF_vect _VECTOR(14) +- +-#define SPI_STC_vect_num 15 +-#define SPI_STC_vect _VECTOR(15) +- +-#define ADC_vect_num 16 +-#define ADC_vect _VECTOR(16) +- +-#define EE_READY_vect_num 17 +-#define EE_READY_vect _VECTOR(17) +- +-#define ANALOG_COMP_vect_num 18 +-#define ANALOG_COMP_vect _VECTOR(18) +- +-#define TWI_vect_num 19 +-#define TWI_vect _VECTOR(19) +- +-#define _VECTORS_SIZE 40 +- +- +-/* Constants */ +-#define SPM_PAGESIZE 32 +-#define RAMSTART (0x100) +-#define RAMEND 0x1FF +-#define XRAMSIZE 0 +-#define XRAMEND RAMEND +-#define E2END 0x3F +-#define E2PAGESIZE 4 +-#define FLASHEND 0xFFF +- +- +-/* Fuse Information */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self Programming Enable */ +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x92 +-#define SIGNATURE_2 0x09 +- +- +-#endif /* _AVR_IOTN48_H_ */ ++/* Copyright (c) 2007-2010 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++/* $Id: iotn48.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* avr/iotn48.h - definitions for ATtiny48 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn48.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_IOTN48_H_ ++#define _AVR_IOTN48_H_ 1 ++ ++/* Registers and associated bit numbers */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++#define PINC7 7 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++#define DDC7 7 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC3 3 ++#define PORTC4 4 ++#define PORTC5 5 ++#define PORTC6 6 ++#define PORTC7 7 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define PINA _SFR_IO8(0x0C) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++ ++#define DDRA _SFR_IO8(0x0D) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++ ++#define PORTA _SFR_IO8(0x0E) ++#define PORTA0 0 ++#define PORTA1 1 ++#define PORTA2 2 ++#define PORTA3 3 ++ ++#define PORTCR _SFR_IO8(0x12) ++#define PUDA 0 ++#define PUDB 1 ++#define PUDC 2 ++#define PUDD 3 ++#define BBMA 4 ++#define BBMB 5 ++#define BBMC 6 ++#define BBMD 7 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++#define PCIF3 3 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define CTC0 3 ++ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define OCR0A _SFR_IO8(0x27) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define OCR0B _SFR_IO8(0x28) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SELFPRGEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define RFLB 3 ++#define CTPB 4 ++#define RWWSB 6 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRTIM0 5 ++#define PRTWI 7 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++#define PCIE3 3 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++#define PCMSK3 _SFR_MEM8(0x6A) ++#define PCINT24 0 ++#define PCINT25 1 ++#define PCINT26 2 ++#define PCINT27 3 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_MEM8(0x79) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define ADLAR 5 ++#define REFS0 6 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define TWBR _SFR_MEM8(0xB8) ++#define TWBR0 0 ++#define TWBR1 1 ++#define TWBR2 2 ++#define TWBR3 3 ++#define TWBR4 4 ++#define TWBR5 5 ++#define TWBR6 6 ++#define TWBR7 7 ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++#define TWD0 0 ++#define TWD1 1 ++#define TWD2 2 ++#define TWD3 3 ++#define TWD4 4 ++#define TWD5 5 ++#define TWD6 6 ++#define TWD7 7 ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++#define TWIHSR _SFR_MEM8(0xBE) /* Deprecated */ ++#define TWHSR _SFR_MEM8(0xBE) ++#define TWIHS 0 ++ ++ ++/* Interrupt Vectors */ ++/* Interrupt vector 0 is the reset vector. */ ++ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++ ++#define PCINT0_vect_num 3 ++#define PCINT0_vect _VECTOR(3) ++ ++#define PCINT1_vect_num 4 ++#define PCINT1_vect _VECTOR(4) ++ ++#define PCINT2_vect_num 5 ++#define PCINT2_vect _VECTOR(5) ++ ++#define PCINT3_vect_num 6 ++#define PCINT3_vect _VECTOR(6) ++ ++#define WDT_vect_num 7 ++#define WDT_vect _VECTOR(7) ++ ++#define TIMER1_CAPT_vect_num 8 ++#define TIMER1_CAPT_vect _VECTOR(8) ++ ++#define TIMER1_COMPA_vect_num 9 ++#define TIMER1_COMPA_vect _VECTOR(9) ++ ++#define TIMER1_COMPB_vect_num 10 ++#define TIMER1_COMPB_vect _VECTOR(10) ++ ++#define TIMER1_OVF_vect_num 11 ++#define TIMER1_OVF_vect _VECTOR(11) ++ ++#define TIMER0_COMPA_vect_num 12 ++#define TIMER0_COMPA_vect _VECTOR(12) ++ ++#define TIMER0_COMPB_vect_num 13 ++#define TIMER0_COMPB_vect _VECTOR(13) ++ ++#define TIMER0_OVF_vect_num 14 ++#define TIMER0_OVF_vect _VECTOR(14) ++ ++#define SPI_STC_vect_num 15 ++#define SPI_STC_vect _VECTOR(15) ++ ++#define ADC_vect_num 16 ++#define ADC_vect _VECTOR(16) ++ ++#define EE_READY_vect_num 17 ++#define EE_READY_vect _VECTOR(17) ++ ++#define ANALOG_COMP_vect_num 18 ++#define ANALOG_COMP_vect _VECTOR(18) ++ ++#define TWI_vect_num 19 ++#define TWI_vect _VECTOR(19) ++ ++#define _VECTORS_SIZE 40 ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE 64 ++#define RAMSTART (0x100) ++#define RAMEND 0x1FF ++#define XRAMSIZE 0 ++#define XRAMEND RAMEND ++#define E2END 0x3F ++#define E2PAGESIZE 4 ++#define FLASHEND 0xFFF ++ ++ ++/* Fuse Information */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self Programming Enable */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x92 ++#define SIGNATURE_2 0x09 ++ ++ ++#endif /* _AVR_IOTN48_H_ */ +diff --git a/include/avr/iotn5.h b/include/avr/iotn5.h +index cd99654..2078b28 100644 +--- a/include/avr/iotn5.h ++++ b/include/avr/iotn5.h +@@ -1,503 +1,503 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn5.h 2063 2009-11-18 22:06:28Z arcanum $ */ +- +-/* avr/iotn5.h - definitions for ATtiny5 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn5.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATtiny5_H_ +-#define _AVR_ATtiny5_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINB _SFR_IO8(0x00) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +- +-#define DDRB _SFR_IO8(0x01) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +- +-#define PORTB _SFR_IO8(0x02) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +- +-#define PUEB _SFR_IO8(0x03) +-#define PUEB0 0 +-#define PUEB1 1 +-#define PUEB2 2 +-#define PUEB3 3 +- +-#define PORTCR _SFR_IO8(0x0C) +-#define BBMB 1 +- +-#define PCMSK _SFR_IO8(0x10) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +- +-#define PCIFR _SFR_IO8(0x11) +-#define PCIF0 0 +- +-#define PCICR _SFR_IO8(0x12) +-#define PCIE0 0 +- +-#define EIMSK _SFR_IO8(0x13) +-#define INT0 0 +- +-#define EIFR _SFR_IO8(0x14) +-#define INTF0 0 +- +-#define EICRA _SFR_IO8(0x15) +-#define ISC00 0 +-#define ISC01 1 +- +-#define DIDR0 _SFR_IO8(0x17) +-#define ADC0D 0 +-#define AIN0D 0 +-#define ADC1D 1 +-#define AIN1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +- +-#define ADCL _SFR_IO8(0x19) +-#define ADC0 0 +-#define ADC1 1 +-#define ADC2 2 +-#define ADC3 3 +-#define ADC4 4 +-#define ADC5 5 +-#define ADC6 6 +-#define ADC7 7 +- +-#define ADMUX _SFR_IO8(0x1B) +-#define MUX0 0 +-#define MUX1 1 +- +-#define ADCSRB _SFR_IO8(0x1C) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +- +-#define ADCSRA _SFR_IO8(0x1D) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ACSR _SFR_IO8(0x1F) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACD 7 +- +-#define ICR0 _SFR_IO16(0x22) +- +-#define ICR0L _SFR_IO8(0x22) +-#define ICR0_0 0 +-#define ICR0_1 1 +-#define ICR0_2 2 +-#define ICR0_3 3 +-#define ICR0_4 4 +-#define ICR0_5 5 +-#define ICR0_6 6 +-#define ICR0_7 7 +- +-#define ICR0H _SFR_IO8(0x23) +-#define ICR0_8 0 +-#define ICR0_9 1 +-#define ICR0_10 2 +-#define ICR0_11 3 +-#define ICR0_12 4 +-#define ICR0_13 5 +-#define ICR0_14 6 +-#define ICR0_15 7 +- +-#define OCR0B _SFR_IO16(0x24) +- +-#define OCR0BL _SFR_IO8(0x24) +-#define OCR0B0 0 +-#define OCR0B1 1 +-#define OCR0B2 2 +-#define OCR0B3 3 +-#define OCR0B4 4 +-#define OCR0B5 5 +-#define OCR0B6 6 +-#define OCR0B7 7 +- +-#define OCR0BH _SFR_IO8(0x25) +-#define OCR0B8 0 +-#define OCR0B9 1 +-#define OCR0B10 2 +-#define OCR0B11 3 +-#define OCR0B12 4 +-#define OCR0B13 5 +-#define OCR0B14 6 +-#define OCR0B15 7 +- +-#define OCR0A _SFR_IO16(0x26) +- +-#define OCR0AL _SFR_IO8(0x26) +-#define OCR0A0 0 +-#define OCR0A1 1 +-#define OCR0A2 2 +-#define OCR0A3 3 +-#define OCR0A4 4 +-#define OCR0A5 5 +-#define OCR0A6 6 +-#define OCR0A7 7 +- +-#define OCR0AH _SFR_IO8(0x27) +-#define OCR0A8 0 +-#define OCR0A9 1 +-#define OCR0A10 2 +-#define OCR0A11 3 +-#define OCR0A12 4 +-#define OCR0A13 5 +-#define OCR0A14 6 +-#define OCR0A15 7 +- +-#define TCNT0 _SFR_IO16(0x28) +- +-#define TCNT0L _SFR_IO8(0x28) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define TCNT0H _SFR_IO8(0x29) +-#define TCNT0_8 0 +-#define TCNT0_9 1 +-#define TCNT0_10 2 +-#define TCNT0_11 3 +-#define TCNT0_12 4 +-#define TCNT0_13 5 +-#define TCNT0_14 6 +-#define TCNT0_15 7 +- +-#define TIFR0 _SFR_IO8(0x2A) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +-#define ICF0 5 +- +-#define TIMSK0 _SFR_IO8(0x2B) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +-#define ICIE0 5 +- +-#define TCCR0C _SFR_IO8(0x2C) +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCCR0B _SFR_IO8(0x2D) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define WGM03 4 +-#define ICES0 6 +-#define ICNC0 7 +- +-#define TCCR0A _SFR_IO8(0x2E) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define GTCCR _SFR_IO8(0x2F) +-#define PSR 0 +-#define TSM 7 +- +-#define WDTCSR _SFR_IO8(0x31) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define NVMCSR _SFR_IO8(0x32) +-#define NVMBSY 7 +- +-#define NVMCMD _SFR_IO8(0x33) +-#define NVMCMD0 0 +-#define NVMCMD1 1 +-#define NVMCMD2 2 +-#define NVMCMD3 3 +-#define NVMCMD4 4 +-#define NVMCMD5 5 +- +-#define VLMCSR _SFR_IO8(0x34) +-#define VLM0 0 +-#define VLM1 1 +-#define VLM2 2 +-#define VLMIE 6 +-#define VLMF 7 +- +-#define PRR _SFR_IO8(0x35) +-#define PRTIM0 0 +-#define PRADC 1 +- +-#define CLKPSR _SFR_IO8(0x36) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +- +-#define CLKMSR _SFR_IO8(0x37) +-#define CLKMS0 0 +-#define CLKMS1 1 +- +-#define OSCCAL _SFR_IO8(0x39) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define SMCR _SFR_IO8(0x3A) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define RSTFLR _SFR_IO8(0x3B) +-#define PORF 0 +-#define EXTRF 1 +-#define WDRF 3 +- +-#define CCP _SFR_IO8(0x3C) +-#define CCP0 0 +-#define CCP1 1 +-#define CCP2 2 +-#define CCP3 3 +-#define CCP4 4 +-#define CCP5 5 +-#define CCP6 6 +-#define CCP7 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ +-#define TIM0_CAPT_vect_num 3 +-#define TIM0_CAPT_vect _VECTOR(3) /* Timer/Counter0 Input Capture */ +-#define TIM0_OVF_vect_num 4 +-#define TIM0_OVF_vect _VECTOR(4) /* Timer/Counter0 Overflow */ +-#define TIM0_COMPA_vect_num 5 +-#define TIM0_COMPA_vect _VECTOR(5) /* Timer/Counter Compare Match A */ +-#define TIM0_COMPB_vect_num 6 +-#define TIM0_COMPB_vect _VECTOR(6) /* Timer/Counter Compare Match B */ +-#define ANA_COMP_vect_num 7 +-#define ANA_COMP_vect _VECTOR(7) /* Analog Comparator */ +-#define WDT_vect_num 8 +-#define WDT_vect _VECTOR(8) /* Watchdog Time-out */ +-#define VLM_vect_num 9 +-#define VLM_vect _VECTOR(9) /* Vcc Voltage Level Monitor */ +-#define ADC_vect_num 10 +-#define ADC_vect _VECTOR(10) /* ADC Conversion Complete */ +- +-#define _VECTOR_SIZE 2 /* Size of individual vector. */ +-#define _VECTORS_SIZE (11 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (32) +-#define RAMSTART (0x40) +-#define RAMSIZE (32) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x0) +-#define E2PAGESIZE (0) +-#define FLASHEND (0x1FF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 0 +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x90 +-#define SIGNATURE_2 0x09 +- +- +-/* Device Pin Definitions */ +-#define SPDATA_DDR DDRCINT +-#define SPDATA_PORT PORTCINT +-#define SPDATA_PIN PINCINT +-#define SPDATA_BIT INT0 +- +-#define OC0A_DDR DDRCINT +-#define OC0A_PORT PORTCINT +-#define OC0A_PIN PINCINT +-#define OC0A_BIT INT0 +- +-#define ADC0_DDR DDRCINT +-#define ADC0_PORT PORTCINT +-#define ADC0_PIN PINCINT +-#define ADC0_BIT INT0 +- +-#define AIN0_DDR DDRCINT +-#define AIN0_PORT PORTCINT +-#define AIN0_PIN PINCINT +-#define AIN0_BIT INT0 +- +-#define PB0_DDR DDRCINT +-#define PB0_PORT PORTCINT +-#define PB0_PIN PINCINT +-#define PB0_BIT INT0 +- +-#define SPCLK_DDR DDRCINT +-#define SPCLK_PORT PORTCINT +-#define SPCLK_PIN PINCINT +-#define SPCLK_BIT INT1 +- +-#define CLKI_DDR DDRCINT +-#define CLKI_PORT PORTCINT +-#define CLKI_PIN PINCINT +-#define CLKI_BIT INT1 +- +-#define ICP0_DDR DDRCINT +-#define ICP0_PORT PORTCINT +-#define ICP0_PIN PINCINT +-#define ICP0_BIT INT1 +- +-#define OC0B_DDR DDRCINT +-#define OC0B_PORT PORTCINT +-#define OC0B_PIN PINCINT +-#define OC0B_BIT INT1 +- +-#define ADC1_DDR DDRCINT +-#define ADC1_PORT PORTCINT +-#define ADC1_PIN PINCINT +-#define ADC1_BIT INT1 +- +-#define AIN1_DDR DDRCINT +-#define AIN1_PORT PORTCINT +-#define AIN1_PIN PINCINT +-#define AIN1_BIT INT1 +- +-#define PB1_DDR DDRCINT +-#define PB1_PORT PORTCINT +-#define PB1_PIN PINCINT +-#define PB1_BIT INT1 +- +-#define CLKO_DDR DDRT +-#define CLKO_PORT PORTT +-#define CLKO_PIN PINT +-#define CLKO_BIT T0 +- +-#define PCINT2_DDR DDRT +-#define PCINT2_PORT PORTT +-#define PCINT2_PIN PINT +-#define PCINT2_BIT T0 +- +-#define INT0_DDR DDRT +-#define INT0_PORT PORTT +-#define INT0_PIN PINT +-#define INT0_BIT T0 +- +-#define ADC2_DDR DDRT +-#define ADC2_PORT PORTT +-#define ADC2_PIN PINT +-#define ADC2_BIT T0 +- +-#define PB2_DDR DDRT +-#define PB2_PORT PORTT +-#define PB2_PIN PINT +-#define PB2_BIT T0 +- +-#define PCINT3_DDR DDRRESET +-#define PCINT3_PORT PORTRESET +-#define PCINT3_PIN PINRESET +-#define PCINT3_BIT RESET +- +-#define ADC3_DDR DDRRESET +-#define ADC3_PORT PORTRESET +-#define ADC3_PIN PINRESET +-#define ADC3_BIT RESET +- +-#define PB3_DDR DDRRESET +-#define PB3_PORT PORTRESET +-#define PB3_PIN PINRESET +-#define PB3_BIT RESET +- +-#endif /* _AVR_ATtiny5_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn5.h 2063 2009-11-18 22:06:28Z arcanum $ */ ++ ++/* avr/iotn5.h - definitions for ATtiny5 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn5.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATtiny5_H_ ++#define _AVR_ATtiny5_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINB _SFR_IO8(0x00) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++ ++#define DDRB _SFR_IO8(0x01) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++ ++#define PORTB _SFR_IO8(0x02) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++ ++#define PUEB _SFR_IO8(0x03) ++#define PUEB0 0 ++#define PUEB1 1 ++#define PUEB2 2 ++#define PUEB3 3 ++ ++#define PORTCR _SFR_IO8(0x0C) ++#define BBMB 1 ++ ++#define PCMSK _SFR_IO8(0x10) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++ ++#define PCIFR _SFR_IO8(0x11) ++#define PCIF0 0 ++ ++#define PCICR _SFR_IO8(0x12) ++#define PCIE0 0 ++ ++#define EIMSK _SFR_IO8(0x13) ++#define INT0 0 ++ ++#define EIFR _SFR_IO8(0x14) ++#define INTF0 0 ++ ++#define EICRA _SFR_IO8(0x15) ++#define ISC00 0 ++#define ISC01 1 ++ ++#define DIDR0 _SFR_IO8(0x17) ++#define ADC0D 0 ++#define AIN0D 0 ++#define ADC1D 1 ++#define AIN1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++ ++#define ADCL _SFR_IO8(0x19) ++#define ADC0 0 ++#define ADC1 1 ++#define ADC2 2 ++#define ADC3 3 ++#define ADC4 4 ++#define ADC5 5 ++#define ADC6 6 ++#define ADC7 7 ++ ++#define ADMUX _SFR_IO8(0x1B) ++#define MUX0 0 ++#define MUX1 1 ++ ++#define ADCSRB _SFR_IO8(0x1C) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++ ++#define ADCSRA _SFR_IO8(0x1D) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ACSR _SFR_IO8(0x1F) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACD 7 ++ ++#define ICR0 _SFR_IO16(0x22) ++ ++#define ICR0L _SFR_IO8(0x22) ++#define ICR0_0 0 ++#define ICR0_1 1 ++#define ICR0_2 2 ++#define ICR0_3 3 ++#define ICR0_4 4 ++#define ICR0_5 5 ++#define ICR0_6 6 ++#define ICR0_7 7 ++ ++#define ICR0H _SFR_IO8(0x23) ++#define ICR0_8 0 ++#define ICR0_9 1 ++#define ICR0_10 2 ++#define ICR0_11 3 ++#define ICR0_12 4 ++#define ICR0_13 5 ++#define ICR0_14 6 ++#define ICR0_15 7 ++ ++#define OCR0B _SFR_IO16(0x24) ++ ++#define OCR0BL _SFR_IO8(0x24) ++#define OCR0B0 0 ++#define OCR0B1 1 ++#define OCR0B2 2 ++#define OCR0B3 3 ++#define OCR0B4 4 ++#define OCR0B5 5 ++#define OCR0B6 6 ++#define OCR0B7 7 ++ ++#define OCR0BH _SFR_IO8(0x25) ++#define OCR0B8 0 ++#define OCR0B9 1 ++#define OCR0B10 2 ++#define OCR0B11 3 ++#define OCR0B12 4 ++#define OCR0B13 5 ++#define OCR0B14 6 ++#define OCR0B15 7 ++ ++#define OCR0A _SFR_IO16(0x26) ++ ++#define OCR0AL _SFR_IO8(0x26) ++#define OCR0A0 0 ++#define OCR0A1 1 ++#define OCR0A2 2 ++#define OCR0A3 3 ++#define OCR0A4 4 ++#define OCR0A5 5 ++#define OCR0A6 6 ++#define OCR0A7 7 ++ ++#define OCR0AH _SFR_IO8(0x27) ++#define OCR0A8 0 ++#define OCR0A9 1 ++#define OCR0A10 2 ++#define OCR0A11 3 ++#define OCR0A12 4 ++#define OCR0A13 5 ++#define OCR0A14 6 ++#define OCR0A15 7 ++ ++#define TCNT0 _SFR_IO16(0x28) ++ ++#define TCNT0L _SFR_IO8(0x28) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define TCNT0H _SFR_IO8(0x29) ++#define TCNT0_8 0 ++#define TCNT0_9 1 ++#define TCNT0_10 2 ++#define TCNT0_11 3 ++#define TCNT0_12 4 ++#define TCNT0_13 5 ++#define TCNT0_14 6 ++#define TCNT0_15 7 ++ ++#define TIFR0 _SFR_IO8(0x2A) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++#define ICF0 5 ++ ++#define TIMSK0 _SFR_IO8(0x2B) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++#define ICIE0 5 ++ ++#define TCCR0C _SFR_IO8(0x2C) ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCCR0B _SFR_IO8(0x2D) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define WGM03 4 ++#define ICES0 6 ++#define ICNC0 7 ++ ++#define TCCR0A _SFR_IO8(0x2E) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define GTCCR _SFR_IO8(0x2F) ++#define PSR 0 ++#define TSM 7 ++ ++#define WDTCSR _SFR_IO8(0x31) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define NVMCSR _SFR_IO8(0x32) ++#define NVMBSY 7 ++ ++#define NVMCMD _SFR_IO8(0x33) ++#define NVMCMD0 0 ++#define NVMCMD1 1 ++#define NVMCMD2 2 ++#define NVMCMD3 3 ++#define NVMCMD4 4 ++#define NVMCMD5 5 ++ ++#define VLMCSR _SFR_IO8(0x34) ++#define VLM0 0 ++#define VLM1 1 ++#define VLM2 2 ++#define VLMIE 6 ++#define VLMF 7 ++ ++#define PRR _SFR_IO8(0x35) ++#define PRTIM0 0 ++#define PRADC 1 ++ ++#define CLKPSR _SFR_IO8(0x36) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++ ++#define CLKMSR _SFR_IO8(0x37) ++#define CLKMS0 0 ++#define CLKMS1 1 ++ ++#define OSCCAL _SFR_IO8(0x39) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define SMCR _SFR_IO8(0x3A) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define RSTFLR _SFR_IO8(0x3B) ++#define PORF 0 ++#define EXTRF 1 ++#define WDRF 3 ++ ++#define CCP _SFR_IO8(0x3C) ++#define CCP0 0 ++#define CCP1 1 ++#define CCP2 2 ++#define CCP3 3 ++#define CCP4 4 ++#define CCP5 5 ++#define CCP6 6 ++#define CCP7 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ ++#define TIM0_CAPT_vect_num 3 ++#define TIM0_CAPT_vect _VECTOR(3) /* Timer/Counter0 Input Capture */ ++#define TIM0_OVF_vect_num 4 ++#define TIM0_OVF_vect _VECTOR(4) /* Timer/Counter0 Overflow */ ++#define TIM0_COMPA_vect_num 5 ++#define TIM0_COMPA_vect _VECTOR(5) /* Timer/Counter Compare Match A */ ++#define TIM0_COMPB_vect_num 6 ++#define TIM0_COMPB_vect _VECTOR(6) /* Timer/Counter Compare Match B */ ++#define ANA_COMP_vect_num 7 ++#define ANA_COMP_vect _VECTOR(7) /* Analog Comparator */ ++#define WDT_vect_num 8 ++#define WDT_vect _VECTOR(8) /* Watchdog Time-out */ ++#define VLM_vect_num 9 ++#define VLM_vect _VECTOR(9) /* Vcc Voltage Level Monitor */ ++#define ADC_vect_num 10 ++#define ADC_vect _VECTOR(10) /* ADC Conversion Complete */ ++ ++#define _VECTOR_SIZE 2 /* Size of individual vector. */ ++#define _VECTORS_SIZE (11 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (32) ++#define RAMSTART (0x40) ++#define RAMSIZE (32) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x0) ++#define E2PAGESIZE (0) ++#define FLASHEND (0x1FF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 0 ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x90 ++#define SIGNATURE_2 0x09 ++ ++ ++/* Device Pin Definitions */ ++#define SPDATA_DDR DDRCINT ++#define SPDATA_PORT PORTCINT ++#define SPDATA_PIN PINCINT ++#define SPDATA_BIT INT0 ++ ++#define OC0A_DDR DDRCINT ++#define OC0A_PORT PORTCINT ++#define OC0A_PIN PINCINT ++#define OC0A_BIT INT0 ++ ++#define ADC0_DDR DDRCINT ++#define ADC0_PORT PORTCINT ++#define ADC0_PIN PINCINT ++#define ADC0_BIT INT0 ++ ++#define AIN0_DDR DDRCINT ++#define AIN0_PORT PORTCINT ++#define AIN0_PIN PINCINT ++#define AIN0_BIT INT0 ++ ++#define PB0_DDR DDRCINT ++#define PB0_PORT PORTCINT ++#define PB0_PIN PINCINT ++#define PB0_BIT INT0 ++ ++#define SPCLK_DDR DDRCINT ++#define SPCLK_PORT PORTCINT ++#define SPCLK_PIN PINCINT ++#define SPCLK_BIT INT1 ++ ++#define CLKI_DDR DDRCINT ++#define CLKI_PORT PORTCINT ++#define CLKI_PIN PINCINT ++#define CLKI_BIT INT1 ++ ++#define ICP0_DDR DDRCINT ++#define ICP0_PORT PORTCINT ++#define ICP0_PIN PINCINT ++#define ICP0_BIT INT1 ++ ++#define OC0B_DDR DDRCINT ++#define OC0B_PORT PORTCINT ++#define OC0B_PIN PINCINT ++#define OC0B_BIT INT1 ++ ++#define ADC1_DDR DDRCINT ++#define ADC1_PORT PORTCINT ++#define ADC1_PIN PINCINT ++#define ADC1_BIT INT1 ++ ++#define AIN1_DDR DDRCINT ++#define AIN1_PORT PORTCINT ++#define AIN1_PIN PINCINT ++#define AIN1_BIT INT1 ++ ++#define PB1_DDR DDRCINT ++#define PB1_PORT PORTCINT ++#define PB1_PIN PINCINT ++#define PB1_BIT INT1 ++ ++#define CLKO_DDR DDRT ++#define CLKO_PORT PORTT ++#define CLKO_PIN PINT ++#define CLKO_BIT T0 ++ ++#define PCINT2_DDR DDRT ++#define PCINT2_PORT PORTT ++#define PCINT2_PIN PINT ++#define PCINT2_BIT T0 ++ ++#define INT0_DDR DDRT ++#define INT0_PORT PORTT ++#define INT0_PIN PINT ++#define INT0_BIT T0 ++ ++#define ADC2_DDR DDRT ++#define ADC2_PORT PORTT ++#define ADC2_PIN PINT ++#define ADC2_BIT T0 ++ ++#define PB2_DDR DDRT ++#define PB2_PORT PORTT ++#define PB2_PIN PINT ++#define PB2_BIT T0 ++ ++#define PCINT3_DDR DDRRESET ++#define PCINT3_PORT PORTRESET ++#define PCINT3_PIN PINRESET ++#define PCINT3_BIT RESET ++ ++#define ADC3_DDR DDRRESET ++#define ADC3_PORT PORTRESET ++#define ADC3_PIN PINRESET ++#define ADC3_BIT RESET ++ ++#define PB3_DDR DDRRESET ++#define PB3_PORT PORTRESET ++#define PB3_PIN PINRESET ++#define PB3_BIT RESET ++ ++#endif /* _AVR_ATtiny5_H_ */ ++ +diff --git a/include/avr/iotn828.h b/include/avr/iotn828.h +new file mode 100644 +index 0000000..9cc09ea +--- /dev/null ++++ b/include/avr/iotn828.h +@@ -0,0 +1,832 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATTINY828_H_INCLUDED ++#define _AVR_ATTINY828_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn828.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDRA7 7 ++#define DDRA6 6 ++#define DDRA5 5 ++#define DDRA4 4 ++#define DDRA3 3 ++#define DDRA2 2 ++#define DDRA1 1 ++#define DDRA0 0 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define PUEA _SFR_IO8(0x03) ++ ++#define PINB _SFR_IO8(0x04) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x05) ++#define DDRB7 7 ++#define DDRB6 6 ++#define DDRB5 5 ++#define DDRB4 4 ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x06) ++#define PORTB7 7 ++#define PORTB6 6 ++#define PORTB5 5 ++#define PORTB4 4 ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PUEB _SFR_IO8(0x07) ++ ++#define PINC _SFR_IO8(0x08) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x09) ++#define DDRC7 7 ++#define DDRC6 6 ++#define DDRC5 5 ++#define DDRC4 4 ++#define DDRC3 3 ++#define DDRC2 2 ++#define DDRC1 1 ++#define DDRC0 0 ++ ++#define PORTC _SFR_IO8(0x0A) ++#define PORTC7 7 ++#define PORTC6 6 ++#define PORTC5 5 ++#define PORTC4 4 ++#define PORTC3 3 ++#define PORTC2 2 ++#define PORTC1 1 ++#define PORTC0 0 ++ ++#define PUEC _SFR_IO8(0x0B) ++ ++#define PIND _SFR_IO8(0x0C) ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0D) ++#define DDRD3 3 ++#define DDRD2 2 ++#define DDRD1 1 ++#define DDRD0 0 ++ ++#define PORTD _SFR_IO8(0x0E) ++#define PORTD3 3 ++#define PORTD2 2 ++#define PORTD1 1 ++#define PORTD0 0 ++ ++#define PUED _SFR_IO8(0x0F) ++ ++/* Reserved [0x10..0x13] */ ++ ++#define PHDE _SFR_IO8(0x14) ++#define PHDEC 2 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++/* Reserved [0x17..0x1A] */ ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++#define PCIF3 3 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++#define EEAR _SFR_IO8(0x21) ++ ++/* Reserved [0x22] */ ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x26) ++ ++#define OCR0A _SFR_IO8(0x27) ++ ++#define OCR0B _SFR_IO8(0x28) ++ ++/* Reserved [0x29] */ ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++#define ACSRB _SFR_IO8(0x2F) ++#define ACPMUX0 0 ++#define ACPMUX1 1 ++#define ACNMUX0 2 ++#define ACNMUX1 3 ++#define HLEV 6 ++#define HSEL 7 ++ ++#define ACSRA _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACPMUX2 6 ++#define ACD 7 ++ ++/* Reserved [0x31..0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define IVSEL 1 ++ ++#define CCP _SFR_IO8(0x36) ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define RWFLB 3 ++#define RWWSRE 4 ++#define RSIG 5 ++#define RWWSB 6 ++#define SPMIE 7 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDE 3 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSART0 1 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRTIM0 5 ++#define PRTWI 7 ++ ++/* Reserved [0x65] */ ++ ++#define OSCCAL0 _SFR_MEM8(0x66) ++ ++#define OSCCAL1 _SFR_MEM8(0x67) ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++#define PCIE3 3 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++/* Reserved [0x6A] */ ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++/* Reserved [0x70..0x72] */ ++ ++#define PCMSK3 _SFR_MEM8(0x73) ++#define PCINT24 0 ++#define PCINT25 1 ++#define PCINT26 2 ++#define PCINT27 3 ++ ++/* Reserved [0x74..0x77] */ ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ADLAR 3 ++ ++#define ADMUXA _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++ ++#define ADMUXB _SFR_MEM8(0x7D) ++#define MUX5 0 ++#define REFS 5 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define ADC8D 0 ++#define ADC9D 1 ++#define ADC10D 2 ++#define ADC11D 3 ++#define ADC12D 4 ++#define ADC13D 5 ++#define ADC14D 6 ++#define ADC15D 7 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Reserved [0x8C..0xB7] */ ++ ++#define TWSCRA _SFR_MEM8(0xB8) ++#define TWSME 0 ++#define TWPME 1 ++#define TWSIE 2 ++#define TWEN 3 ++#define TWASIE 4 ++#define TWDIE 5 ++#define TWSHE 7 ++ ++#define TWSCRB _SFR_MEM8(0xB9) ++#define TWCMD0 0 ++#define TWCMD1 1 ++#define TWAA 2 ++#define TWHNM 3 ++ ++#define TWSSRA _SFR_MEM8(0xBA) ++#define TWAS 0 ++#define TWDIR 1 ++#define TWBE 2 ++#define TWC 3 ++#define TWRA 4 ++#define TWCH 5 ++#define TWASIF 6 ++#define TWDIF 7 ++ ++#define TWSAM _SFR_MEM8(0xBB) ++#define TWAE 0 ++#define TWSAM1 1 ++#define TWSAM2 2 ++#define TWSAM3 3 ++#define TWSAM4 4 ++#define TWSAM5 5 ++#define TWSAM6 6 ++#define TWSAM7 7 ++ ++#define TWSA _SFR_MEM8(0xBC) ++ ++#define TWSD _SFR_MEM8(0xBD) ++#define TWSD0 0 ++#define TWSD1 1 ++#define TWSD2 2 ++#define TWSD3 3 ++#define TWSD4 4 ++#define TWSD5 5 ++#define TWSD6 6 ++#define TWSD7 7 ++ ++/* Reserved [0xBE..0xBF] */ ++ ++#define UCSRA _SFR_MEM8(0xC0) ++#define MPCM 0 ++#define U2X 1 ++#define UPE 2 ++#define DOR 3 ++#define FE 4 ++#define UDRE 5 ++#define TXC 6 ++#define RXC 7 ++ ++#define UCSRB _SFR_MEM8(0xC1) ++#define TXB8 0 ++#define RXB8 1 ++#define UCSZ2 2 ++#define TXEN 3 ++#define RXEN 4 ++#define UDRIE 5 ++#define TXCIE 6 ++#define RXCIE 7 ++ ++#define UCSRC _SFR_MEM8(0xC2) ++#define UCPOL 0 ++#define UCSZ0 1 ++#define UCSZ1 2 ++#define USBS 3 ++#define UPM0 4 ++#define UPM1 5 ++#define UMSEL0 6 ++#define UMSEL1 7 ++ ++#define UCSRD _SFR_MEM8(0xC3) ++#define SFDE 5 ++#define RXS 6 ++#define RXSIE 7 ++ ++/* Combine UBRRL and UBRRH */ ++#define UBRR _SFR_MEM16(0xC4) ++ ++#define UBRRL _SFR_MEM8(0xC4) ++#define UBRRH _SFR_MEM8(0xC5) ++ ++#define UDR _SFR_MEM8(0xC6) ++ ++/* Reserved [0xC7..0xDD] */ ++ ++#define DIDR2 _SFR_MEM8(0xDE) ++#define ADC16D 0 ++#define ADC17D 1 ++#define ADC18D 2 ++#define ADC19D 3 ++#define ADC20D 4 ++#define ADC21D 5 ++#define ADC22D 6 ++#define ADC23D 7 ++ ++#define DIDR3 _SFR_MEM8(0xDF) ++#define ADC24D 0 ++#define ADC25D 1 ++#define ADC26D 2 ++#define ADC27D 3 ++ ++/* Reserved [0xE0..0xE1] */ ++ ++#define TOCPMCOE _SFR_MEM8(0xE2) ++#define TOCC0OE 0 ++#define TOCC1OE 1 ++#define TOCC2OE 2 ++#define TOCC3OE 3 ++#define TOCC4OE 4 ++#define TOCC5OE 5 ++#define TOCC6OE 6 ++#define TOCC7OE 7 ++ ++/* Reserved [0xE3..0xE7] */ ++ ++#define TOCPMSA0 _SFR_MEM8(0xE8) ++#define TOCC0S0 0 ++#define TOCC0S1 1 ++#define TOCC1S0 2 ++#define TOCC1S1 3 ++#define TOCC2S0 4 ++#define TOCC2S1 5 ++#define TOCC3S0 6 ++#define TOCC3S1 7 ++ ++#define TOCPMSA1 _SFR_MEM8(0xE9) ++#define TOCC4S0 0 ++#define TOCC4S1 1 ++#define TOCC5S0 2 ++#define TOCC5S1 3 ++#define TOCC6S0 4 ++#define TOCC6S1 5 ++#define TOCC7S0 6 ++#define TOCC7S1 7 ++ ++/* Reserved [0xEA..0xEF] */ ++ ++#define OSCTCAL0A _SFR_MEM8(0xF0) ++ ++#define OSCTCAL0B _SFR_MEM8(0xF1) ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect _VECTOR(2) ++#define INT1_vect_num 2 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(3) ++#define PCINT0_vect_num 3 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(4) ++#define PCINT1_vect_num 4 ++ ++/* Pin Change Interrupt Request 2 */ ++#define PCINT2_vect _VECTOR(5) ++#define PCINT2_vect_num 5 ++ ++/* Pin Change Interrupt Request 3 */ ++#define PCINT3_vect _VECTOR(6) ++#define PCINT3_vect_num 6 ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect _VECTOR(7) ++#define WDT_vect_num 7 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(8) ++#define TIMER1_CAPT_vect_num 8 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(9) ++#define TIMER1_COMPA_vect_num 9 ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(10) ++#define TIMER1_COMPB_vect_num 10 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(11) ++#define TIMER1_OVF_vect_num 11 ++ ++/* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPA_vect _VECTOR(12) ++#define TIMER0_COMPA_vect_num 12 ++ ++/* Timer/Counter0 Compare Match B */ ++#define TIMER0_COMPB_vect _VECTOR(13) ++#define TIMER0_COMPB_vect_num 13 ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(14) ++#define TIMER0_OVF_vect_num 14 ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect _VECTOR(15) ++#define SPI_STC_vect_num 15 ++ ++/* USART, Start */ ++#define USART_START_vect _VECTOR(16) ++#define USART_START_vect_num 16 ++ ++/* USART Rx Complete */ ++#define USART_RX_vect _VECTOR(17) ++#define USART_RX_vect_num 17 ++ ++/* USART, Data Register Empty */ ++#define USART_UDRE_vect _VECTOR(18) ++#define USART_UDRE_vect_num 18 ++ ++/* USART Tx Complete */ ++#define USART_TX_vect _VECTOR(19) ++#define USART_TX_vect_num 19 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(20) ++#define ADC_vect_num 20 ++ ++/* EEPROM Ready */ ++#define EE_READY_vect _VECTOR(21) ++#define EE_READY_vect_num 21 ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect _VECTOR(22) ++#define ANALOG_COMP_vect_num 22 ++ ++/* Two-wire Serial Interface */ ++#define TWI_SLAVE_vect _VECTOR(23) ++#define TWI_SLAVE_vect_num 23 ++ ++/* Store Program Memory Read */ ++#define SPM_Ready_vect _VECTOR(24) ++#define SPM_Ready_vect_num 24 ++ ++/* Touch Sensing */ ++#define QTRIP_vect _VECTOR(25) ++#define QTRIP_vect_num 25 ++ ++#define _VECTORS_SIZE 52 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 64 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x1FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 512 ++#define RAMEND 0x02FF ++#define E2START 0 ++#define E2SIZE 256 ++#define E2PAGESIZE 4 ++#define E2END 0x00FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_BODACT0 (unsigned char)~_BV(4) ++#define FUSE_BODACT1 (unsigned char)~_BV(5) ++#define FUSE_BODPD0 (unsigned char)~_BV(6) ++#define FUSE_BODPD1 (unsigned char)~_BV(7) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x14 ++ ++ ++#endif /* #ifdef _AVR_ATTINY828_H_INCLUDED */ ++ +diff --git a/include/avr/iotn84.h b/include/avr/iotn84.h +index 47a867f..1912c1e 100644 +--- a/include/avr/iotn84.h ++++ b/include/avr/iotn84.h +@@ -1,90 +1,90 @@ +-/* Copyright (c) 2005, Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn84.h 2115 2010-04-05 23:19:53Z arcanum $ */ +- +-/* avr/iotn84.h - definitions for ATtiny84 */ +- +-#ifndef _AVR_IOTN84_H_ +-#define _AVR_IOTN84_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 64 +-#define RAMSTART (0x60) +-#define RAMEND 0x25F +-#define XRAMEND RAMEND +-#define E2END 0x1FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x1FFF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_DWEN (unsigned char)~_BV(6) +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) +-#define FUSE_HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_SELFPRGEN (unsigned char)~_BV(0) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x93 +-#define SIGNATURE_2 0x0C +- +- +-#endif /* _AVR_IOTN84_H_ */ ++/* Copyright (c) 2005, Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn84.h 2417 2014-04-16 11:34:47Z pitchumani $ */ ++ ++/* avr/iotn84.h - definitions for ATtiny84 */ ++ ++#ifndef _AVR_IOTN84_H_ ++#define _AVR_IOTN84_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 64 ++#define RAMSTART (0x60) ++#define RAMEND 0x25F ++#define XRAMEND RAMEND ++#define E2END 0x1FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x1FFF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x0C ++ ++ ++#endif /* _AVR_IOTN84_H_ */ +diff --git a/include/avr/iotn841.h b/include/avr/iotn841.h +new file mode 100644 +index 0000000..031bd9d +--- /dev/null ++++ b/include/avr/iotn841.h +@@ -0,0 +1,843 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_ATTINY841_H_INCLUDED ++#define _AVR_ATTINY841_H_INCLUDED ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn841.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define ADCSRB _SFR_IO8(0x04) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ADLAR 3 ++ ++#define ADCSRA _SFR_IO8(0x05) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++/* Combine ADCL and ADCH */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x06) ++#endif ++#define ADCW _SFR_IO16(0x06) ++ ++#define ADCL _SFR_IO8(0x06) ++#define ADCH _SFR_IO8(0x07) ++ ++#define ADMUXB _SFR_IO8(0x08) ++#define GSEL0 0 ++#define GSEL1 1 ++#define REFS0 5 ++#define REFS1 6 ++#define REFS2 7 ++ ++#define ADMUXA _SFR_IO8(0x09) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define MUX5 5 ++ ++#define ACSR0A _SFR_IO8(0x0A) ++#define ACIS00 0 ++#define ACIS01 1 ++#define ACIC0 2 ++#define ACIE0 3 ++#define ACI0 4 ++#define ACO0 5 ++#define ACPMUX2 6 ++#define ACD0 7 ++ ++#define ACSR0B _SFR_IO8(0x0B) ++#define ACPMUX0 0 ++#define ACPMUX1 1 ++#define ACNMUX0 2 ++#define ACNMUX1 3 ++#define ACOE0 4 ++#define HLEV0 6 ++#define HSEL0 7 ++ ++#define ACSR1A _SFR_IO8(0x0C) ++#define ACIS10 0 ++#define ACIS11 1 ++#define ACIC1 2 ++#define ACIE1 3 ++#define ACI1 4 ++#define ACO1 5 ++#define ACBG1 6 ++#define ACD1 7 ++ ++#define ACSR1B _SFR_IO8(0x0D) ++#define ACME1 2 ++#define ACOE1 4 ++#define HLEV1 6 ++#define HSEL1 7 ++ ++#define TIFR1 _SFR_IO8(0x0E) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIMSK1 _SFR_IO8(0x0F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define TIFR2 _SFR_IO8(0x10) ++#define TOV2 0 ++#define OCF2A 1 ++#define OCF2B 2 ++#define ICF2 5 ++ ++#define TIMSK2 _SFR_IO8(0x11) ++#define TOIE2 0 ++#define OCIE2A 1 ++#define OCIE2B 2 ++#define ICIE2 5 ++ ++#define PCMSK0 _SFR_IO8(0x12) ++ ++#define GPIOR0 _SFR_IO8(0x13) ++ ++#define GPIOR1 _SFR_IO8(0x14) ++ ++#define GPIOR2 _SFR_IO8(0x15) ++ ++#define PINB _SFR_IO8(0x16) ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x17) ++#define DDRB3 3 ++#define DDRB2 2 ++#define DDRB1 1 ++#define DDRB0 0 ++ ++#define PORTB _SFR_IO8(0x18) ++#define PORTB3 3 ++#define PORTB2 2 ++#define PORTB1 1 ++#define PORTB0 0 ++ ++#define PINA _SFR_IO8(0x19) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x1A) ++#define DDRA7 7 ++#define DDRA6 6 ++#define DDRA5 5 ++#define DDRA4 4 ++#define DDRA3 3 ++#define DDRA2 2 ++#define DDRA1 1 ++#define DDRA0 0 ++ ++#define PORTA _SFR_IO8(0x1B) ++#define PORTA7 7 ++#define PORTA6 6 ++#define PORTA5 5 ++#define PORTA4 4 ++#define PORTA3 3 ++#define PORTA2 2 ++#define PORTA1 1 ++#define PORTA0 0 ++ ++#define EECR _SFR_IO8(0x1C) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* Combine EEARL and EEARH */ ++#define EEAR _SFR_IO16(0x1E) ++ ++#define EEARL _SFR_IO8(0x1E) ++#define EEARH _SFR_IO8(0x1F) ++ ++#define PCMSK1 _SFR_IO8(0x20) ++ ++#define WDTCSR _SFR_IO8(0x21) ++#define WDE 3 ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define TCCR1C _SFR_IO8(0x22) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR 0 ++#define TSM 7 ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_IO16(0x24) ++ ++#define ICR1L _SFR_IO8(0x24) ++#define ICR1H _SFR_IO8(0x25) ++ ++/* Reserved [0x26..0x27] */ ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_IO16(0x28) ++ ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BH _SFR_IO8(0x29) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_IO16(0x2A) ++ ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_IO16(0x2C) ++ ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++ ++#define TCCR1B _SFR_IO8(0x2E) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1A _SFR_IO8(0x2F) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR0A _SFR_IO8(0x30) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++/* Reserved [0x31] */ ++ ++#define TCNT0 _SFR_IO8(0x32) ++ ++#define TCCR0B _SFR_IO8(0x33) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define ISC00 0 ++#define ISC01 1 ++#define SM0 3 ++#define SM1 4 ++#define SE 5 ++ ++#define OCR0A _SFR_IO8(0x36) ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define RFLB 3 ++#define CTPB 4 ++#define RSIG 5 ++ ++#define TIFR0 _SFR_IO8(0x38) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIMSK0 _SFR_IO8(0x39) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define GIFR _SFR_IO8(0x3A) ++#define PCIF0 4 ++#define PCIF1 5 ++#define INTF0 6 ++ ++#define GIMSK _SFR_IO8(0x3B) ++#define PCIE0 4 ++#define PCIE1 5 ++#define INT0 6 ++ ++#define OCR0B _SFR_IO8(0x3C) ++ ++/* SP [0x3D..0x3E] */ ++ ++/* SREG [0x3F] */ ++ ++#define DIDR0 _SFR_MEM8(0x60) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x61) ++#define ADC11D 0 ++#define ADC10D 1 ++#define ADC8D 2 ++#define ADC9D 3 ++ ++#define PUEB _SFR_MEM8(0x62) ++ ++#define PUEA _SFR_MEM8(0x63) ++ ++#define PORTCR _SFR_MEM8(0x64) ++#define BBMB 1 ++#define BBMA 0 ++ ++#define REMAP _SFR_MEM8(0x65) ++#define U0MAP 0 ++#define SPIMAP 1 ++ ++#define TOCPMCOE _SFR_MEM8(0x66) ++#define TOCC0OE 0 ++#define TOCC1OE 1 ++#define TOCC2OE 2 ++#define TOCC3OE 3 ++#define TOCC4OE 4 ++#define TOCC5OE 5 ++#define TOCC6OE 6 ++#define TOCC7OE 7 ++ ++#define TOCPMSA0 _SFR_MEM8(0x67) ++#define TOCC0S0 0 ++#define TOCC0S1 1 ++#define TOCC1S0 2 ++#define TOCC1S1 3 ++#define TOCC2S0 4 ++#define TOCC2S1 5 ++#define TOCC3S0 6 ++#define TOCC3S1 7 ++ ++#define TOCPMSA1 _SFR_MEM8(0x68) ++#define TOCC4S0 0 ++#define TOCC4S1 1 ++#define TOCC5S0 2 ++#define TOCC5S1 3 ++#define TOCC6S0 4 ++#define TOCC6S1 5 ++#define TOCC7S0 6 ++#define TOCC7S1 7 ++ ++/* Reserved [0x69] */ ++ ++#define PHDE _SFR_MEM8(0x6A) ++#define PHDEA0 0 ++#define PHDEA1 1 ++ ++/* Reserved [0x6B..0x6F] */ ++ ++#define PRR _SFR_MEM8(0x70) ++#define PRADC 0 ++#define PRTIM0 1 ++#define PRTIM1 2 ++#define PRTIM2 3 ++#define PRSPI 4 ++#define PRUSART0 5 ++#define PRUSART1 6 ++#define PRTWI 7 ++ ++#define CCP _SFR_MEM8(0x71) ++ ++#define CLKCR _SFR_MEM8(0x72) ++#define CKSEL0 0 ++#define CKSEL1 1 ++#define CKSEL2 2 ++#define CKSEL3 3 ++#define SUT 4 ++#define CKOUTC 5 ++#define CSTR 6 ++#define OSCRDY 7 ++ ++#define CLKPR _SFR_MEM8(0x73) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++ ++#define OSCCAL0 _SFR_MEM8(0x74) ++ ++#define OSCTCAL0A _SFR_MEM8(0x75) ++ ++#define OSCTCAL0B _SFR_MEM8(0x76) ++ ++#define OSCCAL1 _SFR_MEM8(0x77) ++ ++/* Reserved [0x78..0x7F] */ ++ ++#define UDR0 _SFR_MEM8(0x80) ++ ++/* Combine UBRR0L and UBRR0H */ ++#define UBRR0 _SFR_MEM16(0x81) ++ ++#define UBRR0L _SFR_MEM8(0x81) ++#define UBRR0H _SFR_MEM8(0x82) ++ ++#define UCSR0D _SFR_MEM8(0x83) ++#define SFDE0 5 ++#define RXS0 6 ++#define RXSIE0 7 ++ ++#define UCSR0C _SFR_MEM8(0x84) ++#define UCPOL0 0 ++#define UCSZ00 1 ++#define UCSZ01 2 ++#define USBS0 3 ++#define UPM00 4 ++#define UPM01 5 ++#define UMSEL00 6 ++#define UMSEL01 7 ++ ++#define UCSR0B _SFR_MEM8(0x85) ++#define TXB80 0 ++#define RXB80 1 ++#define UCSZ02 2 ++#define TXEN0 3 ++#define RXEN0 4 ++#define UDRIE0 5 ++#define TXCIE0 6 ++#define RXCIE0 7 ++ ++#define UCSR0A _SFR_MEM8(0x86) ++#define MPCM0 0 ++#define U2X0 1 ++#define UPE0 2 ++#define DOR0 3 ++#define FE0 4 ++#define UDRE0 5 ++#define TXC0 6 ++#define RXC0 7 ++ ++/* Reserved [0x87..0x8F] */ ++ ++#define UDR1 _SFR_MEM8(0x90) ++ ++/* Combine UBRR1L and UBRR1H */ ++#define UBRR1 _SFR_MEM16(0x91) ++ ++#define UBRR1L _SFR_MEM8(0x91) ++#define UBRR1H _SFR_MEM8(0x92) ++ ++#define UCSR1D _SFR_MEM8(0x93) ++#define SFDE1 5 ++#define RXS1 6 ++#define RXSIE1 7 ++ ++#define UCSR1C _SFR_MEM8(0x94) ++#define UCPOL1 0 ++#define UCSZ10 1 ++#define UCSZ11 2 ++#define USBS1 3 ++#define UPM10 4 ++#define UPM11 5 ++#define UMSEL10 6 ++#define UMSEL11 7 ++ ++#define UCSR1B _SFR_MEM8(0x95) ++#define TXB81 0 ++#define RXB81 1 ++#define UCSZ12 2 ++#define TXEN1 3 ++#define RXEN1 4 ++#define UDRIE1 5 ++#define TXCIE1 6 ++#define RXCIE1 7 ++ ++#define UCSR1A _SFR_MEM8(0x96) ++#define MPCM1 0 ++#define U2X1 1 ++#define UPE1 2 ++#define DOR1 3 ++#define FE1 4 ++#define UDRE1 5 ++#define TXC1 6 ++#define RXC1 7 ++ ++/* Reserved [0x97..0x9F] */ ++ ++#define TWSD _SFR_MEM8(0xA0) ++#define TWSD0 0 ++#define TWSD1 1 ++#define TWSD2 2 ++#define TWSD3 3 ++#define TWSD4 4 ++#define TWSD5 5 ++#define TWSD6 6 ++#define TWSD7 7 ++ ++#define TWSAM _SFR_MEM8(0xA1) ++#define TWAE 0 ++#define TWSAM1 1 ++#define TWSAM2 2 ++#define TWSAM3 3 ++#define TWSAM4 4 ++#define TWSAM5 5 ++#define TWSAM6 6 ++#define TWSAM7 7 ++ ++#define TWSA _SFR_MEM8(0xA2) ++ ++#define TWSSRA _SFR_MEM8(0xA3) ++#define TWAS 0 ++#define TWDIR 1 ++#define TWBE 2 ++#define TWC 3 ++#define TWRA 4 ++#define TWCH 5 ++#define TWASIF 6 ++#define TWDIF 7 ++ ++#define TWSCRB _SFR_MEM8(0xA4) ++#define TWCMD0 0 ++#define TWCMD1 1 ++#define TWAA 2 ++#define TWHNM 3 ++ ++#define TWSCRA _SFR_MEM8(0xA5) ++#define TWSME 0 ++#define TWPME 1 ++#define TWSIE 2 ++#define TWEN 3 ++#define TWASIE 4 ++#define TWDIE 5 ++#define TWSHE 7 ++ ++/* Reserved [0xA6..0xAF] */ ++ ++#define SPDR _SFR_MEM8(0xB0) ++ ++#define SPSR _SFR_MEM8(0xB1) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPCR _SFR_MEM8(0xB2) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++/* Reserved [0xB3..0xBF] */ ++ ++/* Combine ICR2L and ICR2H */ ++#define ICR2 _SFR_MEM16(0xC0) ++ ++#define ICR2L _SFR_MEM8(0xC0) ++#define ICR2H _SFR_MEM8(0xC1) ++ ++/* Combine OCR2BL and OCR2BH */ ++#define OCR2B _SFR_MEM16(0xC2) ++ ++#define OCR2BL _SFR_MEM8(0xC2) ++#define OCR2BH _SFR_MEM8(0xC3) ++ ++/* Combine OCR2AL and OCR2AH */ ++#define OCR2A _SFR_MEM16(0xC4) ++ ++#define OCR2AL _SFR_MEM8(0xC4) ++#define OCR2AH _SFR_MEM8(0xC5) ++ ++/* Combine TCNT2L and TCNT2H */ ++#define TCNT2 _SFR_MEM16(0xC6) ++ ++#define TCNT2L _SFR_MEM8(0xC6) ++#define TCNT2H _SFR_MEM8(0xC7) ++ ++#define TCCR2C _SFR_MEM8(0xC8) ++#define FOC2B 6 ++#define FOC2A 7 ++ ++#define TCCR2B _SFR_MEM8(0xC9) ++#define CS20 0 ++#define CS21 1 ++#define CS22 2 ++#define WGM22 3 ++#define WGM23 4 ++#define ICES2 6 ++#define ICNC2 7 ++ ++#define TCCR2A _SFR_MEM8(0xCA) ++#define WGM20 0 ++#define WGM21 1 ++#define COM2B0 4 ++#define COM2B1 5 ++#define COM2A0 6 ++#define COM2A1 7 ++ ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++/* External Interrupt Request 0 */ ++#define INT0_vect _VECTOR(1) ++#define INT0_vect_num 1 ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect _VECTOR(2) ++#define PCINT0_vect_num 2 ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect _VECTOR(3) ++#define PCINT1_vect_num 3 ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect _VECTOR(4) ++#define WDT_vect_num 4 ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect _VECTOR(5) ++#define TIMER1_CAPT_vect_num 5 ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect _VECTOR(6) ++#define TIMER1_COMPA_vect_num 6 ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect _VECTOR(7) ++#define TIMER1_COMPB_vect_num 7 ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect _VECTOR(8) ++#define TIMER1_OVF_vect_num 8 ++ ++/* TimerCounter0 Compare Match A */ ++#define TIMER0_COMPA_vect _VECTOR(9) ++#define TIMER0_COMPA_vect_num 9 ++ ++/* TimerCounter0 Compare Match B */ ++#define TIMER0_COMPB_vect _VECTOR(10) ++#define TIMER0_COMPB_vect_num 10 ++ ++/* Timer/Couner0 Overflow */ ++#define TIMER0_OVF_vect _VECTOR(11) ++#define TIMER0_OVF_vect_num 11 ++ ++/* Analog Comparator 0 */ ++#define ANA_COMP0_vect _VECTOR(12) ++#define ANA_COMP0_vect_num 12 ++ ++/* ADC Conversion Complete */ ++#define ADC_vect _VECTOR(13) ++#define ADC_vect_num 13 ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect _VECTOR(14) ++#define EE_RDY_vect_num 14 ++ ++/* Analog Comparator 1 */ ++#define ANA_COMP1_vect _VECTOR(15) ++#define ANA_COMP1_vect_num 15 ++ ++/* Timer/Counter2 Capture Event */ ++#define TIMER2_CAPT_vect _VECTOR(16) ++#define TIMER2_CAPT_vect_num 16 ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPA_vect _VECTOR(17) ++#define TIMER2_COMPA_vect_num 17 ++ ++/* Timer/Counter2 Compare Match B */ ++#define TIMER2_COMPB_vect _VECTOR(18) ++#define TIMER2_COMPB_vect_num 18 ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect _VECTOR(19) ++#define TIMER2_OVF_vect_num 19 ++ ++/* Serial Peripheral Interface */ ++#define SPI_vect _VECTOR(20) ++#define SPI_vect_num 20 ++ ++/* USART0, Start */ ++#define USART0_START_vect _VECTOR(21) ++#define USART0_START_vect_num 21 ++ ++/* USART0, Rx Complete */ ++#define USART0_RX_vect _VECTOR(22) ++#define USART0_RX_vect_num 22 ++ ++/* USART0 Data Register Empty */ ++#define USART0_UDRE_vect _VECTOR(23) ++#define USART0_UDRE_vect_num 23 ++ ++/* USART0, Tx Complete */ ++#define USART0_TX_vect _VECTOR(24) ++#define USART0_TX_vect_num 24 ++ ++/* USART1, Start */ ++#define USART1_START_vect _VECTOR(25) ++#define USART1_START_vect_num 25 ++ ++/* USART1, Rx Complete */ ++#define USART1_RX_vect _VECTOR(26) ++#define USART1_RX_vect_num 26 ++ ++/* USART1 Data Register Empty */ ++#define USART1_UDRE_vect _VECTOR(27) ++#define USART1_UDRE_vect_num 27 ++ ++/* USART1, Tx Complete */ ++#define USART1_TX_vect _VECTOR(28) ++#define USART1_TX_vect_num 28 ++ ++/* Two-wire Serial Interface */ ++#define TWI_SLAVE_vect _VECTOR(29) ++#define TWI_SLAVE_vect_num 29 ++ ++#define _VECTORS_SIZE 60 ++ ++ ++/* Constants */ ++ ++#define SPM_PAGESIZE 16 ++#define FLASHSTART 0x0000 ++#define FLASHEND 0x1FFF ++#define RAMSTART 0x0100 ++#define RAMSIZE 512 ++#define RAMEND 0x02FF ++#define E2START 0 ++#define E2SIZE 512 ++#define E2PAGESIZE 4 ++#define E2END 0x01FF ++#define XRAMEND RAMEND ++ ++ ++/* Fuses */ ++ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_SUT_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_SUT_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_SUT_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_SUT_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT_CKSEL4 (unsigned char)~_BV(4) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) ++#define FUSE_BODACT0 (unsigned char)~_BV(1) ++#define FUSE_BODACT1 (unsigned char)~_BV(2) ++#define FUSE_BODPD0 (unsigned char)~_BV(3) ++#define FUSE_BODPD1 (unsigned char)~_BV(4) ++#define FUSE_ULPOSCSEL0 (unsigned char)~_BV(5) ++#define FUSE_ULPOSCSEL1 (unsigned char)~_BV(6) ++#define FUSE_ULPOSCSEL2 (unsigned char)~_BV(7) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x15 ++ ++ ++#endif /* #ifdef _AVR_ATTINY841_H_INCLUDED */ ++ +diff --git a/include/avr/iotn84a.h b/include/avr/iotn84a.h +index 2099df6..7811055 100755 +--- a/include/avr/iotn84a.h ++++ b/include/avr/iotn84a.h +@@ -1,831 +1,833 @@ +-/* Copyright (c) 2010 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id$ */ +- +-/* avr/iotn84a.h - definitions for ATtiny84A */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn84a.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATtiny84A_H_ +-#define _AVR_ATtiny84A_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PRR _SFR_IO8(0x00) +-#define PRADC 0 +-#define PRUSI 1 +-#define PRTIM0 2 +-#define PRTIM1 3 +- +-#define DIDR0 _SFR_IO8(0x01) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define ADCSRB _SFR_IO8(0x03) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ADLAR 4 +-#define ACME 6 +-#define BIN 7 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x04) +-#endif +-#define ADCW _SFR_IO16(0x04) +- +-#define ADCL _SFR_IO8(0x04) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_IO8(0x05) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_IO8(0x06) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADMUX _SFR_IO8(0x07) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define MUX5 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define ACSR _SFR_IO8(0x08) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define TIFR1 _SFR_IO8(0x0B) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define TIMSK1 _SFR_IO8(0x0C) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define USICR _SFR_IO8(0x0D) +-#define USITC 0 +-#define USICLK 1 +-#define USICS0 2 +-#define USICS1 3 +-#define USIWM0 4 +-#define USIWM1 5 +-#define USIOIE 6 +-#define USISIE 7 +- +-#define USISR _SFR_IO8(0x0E) +-#define USICNT0 0 +-#define USICNT1 1 +-#define USICNT2 2 +-#define USICNT3 3 +-#define USIDC 4 +-#define USIPF 5 +-#define USIOIF 6 +-#define USISIF 7 +- +-#define USIDR _SFR_IO8(0x0F) +-#define USIDR0 0 +-#define USIDR1 1 +-#define USIDR2 2 +-#define USIDR3 3 +-#define USIDR4 4 +-#define USIDR5 5 +-#define USIDR6 6 +-#define USIDR7 7 +- +-#define USIBR _SFR_IO8(0x10) +-#define USIBR0 0 +-#define USIBR1 1 +-#define USIBR2 2 +-#define USIBR3 3 +-#define USIBR4 4 +-#define USIBR5 5 +-#define USIBR6 6 +-#define USIBR7 7 +- +-#define PCMSK0 _SFR_IO8(0x12) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define GPIOR0 _SFR_IO8(0x13) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define GPIOR1 _SFR_IO8(0x14) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x15) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define PINB _SFR_IO8(0x16) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +- +-#define DDRB _SFR_IO8(0x17) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +- +-#define PORTB _SFR_IO8(0x18) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +- +-#define PINA _SFR_IO8(0x19) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +-#define PINA4 4 +-#define PINA5 5 +-#define PINA6 6 +-#define PINA7 7 +- +-#define DDRA _SFR_IO8(0x1A) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +-#define DDA4 4 +-#define DDA5 5 +-#define DDA6 6 +-#define DDA7 7 +- +-#define PORTA _SFR_IO8(0x1B) +-#define PORTA0 0 +-#define PORTA1 1 +-#define PORTA2 2 +-#define PORTA3 3 +-#define PORTA4 4 +-#define PORTA5 5 +-#define PORTA6 6 +-#define PORTA7 7 +- +-#define EECR _SFR_IO8(0x1C) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x1D) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x1E) +- +-#define EEARL _SFR_IO8(0x1E) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x1F) +-#define EEAR8 0 +- +-#define PCMSK1 _SFR_IO8(0x20) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +- +-#define WDTCSR _SFR_IO8(0x21) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define TCCR1C _SFR_IO8(0x22) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSR10 0 +-#define TSM 7 +- +-#define ICR1 _SFR_IO16(0x24) +- +-#define ICR1L _SFR_IO8(0x24) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_IO8(0x25) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define CLKPR _SFR_IO8(0x26) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define DWDR _SFR_IO8(0x27) +- +-#define OCR1B _SFR_IO16(0x28) +- +-#define OCR1BL _SFR_IO8(0x28) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_IO8(0x29) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define OCR1A _SFR_IO16(0x2A) +- +-#define OCR1AL _SFR_IO8(0x2A) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_IO8(0x2B) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define TCNT1 _SFR_IO16(0x2C) +- +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_IO8(0x2D) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define TCCR1B _SFR_IO8(0x2E) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1A _SFR_IO8(0x2F) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR0A _SFR_IO8(0x30) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define OSCCAL _SFR_IO8(0x31) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define TCNT0 _SFR_IO8(0x32) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define TCCR0B _SFR_IO8(0x33) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x35) +-#define ISC00 0 +-#define ISC01 1 +-#define SM0 3 +-#define SM1 4 +-#define SE 5 +-#define PUD 6 +- +-#define OCR0A _SFR_IO8(0x36) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define RFLB 3 +-#define CTPB 4 +- +-#define TIFR0 _SFR_IO8(0x38) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIMSK0 _SFR_IO8(0x39) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define GIFR _SFR_IO8(0x3A) +-#define PCIF0 4 +-#define PCIF1 5 +-#define INTF0 6 +- +-#define GIMSK _SFR_IO8(0x3B) +-#define PCIE0 4 +-#define PCIE1 5 +-#define INT0 6 +- +-#define OCR0B _SFR_IO8(0x3C) +-#define OCR0_0 0 +-#define OCR0_1 1 +-#define OCR0_2 2 +-#define OCR0_3 3 +-#define OCR0_4 4 +-#define OCR0_5 5 +-#define OCR0_6 6 +-#define OCR0_7 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define EXT_INT0_vect_num 1 +-#define EXT_INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ +-#define PCINT1_vect_num 3 +-#define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */ +-#define WATCHDOG_vect_num 4 +-#define WATCHDOG_vect _VECTOR(4) /* Watchdog Time-out */ +-#define TIM1_CAPT_vect_num 5 +-#define TIM1_CAPT_vect _VECTOR(5) /* Timer/Counter1 Capture Event */ +-#define TIM1_COMPA_vect_num 6 +-#define TIM1_COMPA_vect _VECTOR(6) /* Timer/Counter1 Compare Match A */ +-#define TIM1_COMPB_vect_num 7 +-#define TIM1_COMPB_vect _VECTOR(7) /* Timer/Counter1 Compare Match B */ +-#define TIM1_OVF_vect_num 8 +-#define TIM1_OVF_vect _VECTOR(8) /* Timer/Counter1 Overflow */ +-#define TIM0_COMPA_vect_num 9 +-#define TIM0_COMPA_vect _VECTOR(9) /* Timer/Counter0 Compare Match A */ +-#define TIM0_COMPB_vect_num 10 +-#define TIM0_COMPB_vect _VECTOR(10) /* Timer/Counter0 Compare Match B */ +-#define TIM0_OVF_vect_num 11 +-#define TIM0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ +-#define ANA_COMP_vect_num 12 +-#define ANA_COMP_vect _VECTOR(12) /* Analog Comparator */ +-#define ADC_vect_num 13 +-#define ADC_vect _VECTOR(13) /* ADC Conversion Complete */ +-#define EE_RDY_vect_num 14 +-#define EE_RDY_vect _VECTOR(14) /* EEPROM Ready */ +-#define USI_STR_vect_num 15 +-#define USI_STR_vect _VECTOR(15) /* USI START */ +-#define USI_OVF_vect_num 16 +-#define USI_OVF_vect _VECTOR(16) /* USI Overflow */ +- +-#define _VECTOR_SIZE 2 /* Size of individual vector. */ +-#define _VECTORS_SIZE (17 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (64) +-#define RAMSTART (0x60) +-#define RAMSIZE (512) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x1FF) +-#define E2PAGESIZE (4) +-#define FLASHEND (0x1FFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x93 +-#define SIGNATURE_2 0x0C +- +- +-/* Device Pin Definitions */ +-#define ADC4_DDR DDRA +-#define ADC4_PORT PORTA +-#define ADC4_PIN PINA +-#define ADC4_BIT 4 +- +-#define USCK_DDR DDRA +-#define USCK_PORT PORTA +-#define USCK_PIN PINA +-#define USCK_BIT 4 +- +-#define SCL_DDR DDRA +-#define SCL_PORT PORTA +-#define SCL_PIN PINA +-#define SCL_BIT 4 +- +-#define T1_DDR DDRA +-#define T1_PORT PORTA +-#define T1_PIN PINA +-#define T1_BIT 4 +- +-#define PCINT4_DDR DDRA +-#define PCINT4_PORT PORTA +-#define PCINT4_PIN PINA +-#define PCINT4_BIT 4 +- +-#define ADC3_DDR DDRA +-#define ADC3_PORT PORTA +-#define ADC3_PIN PINA +-#define ADC3_BIT 3 +- +-#define T0_DDR DDRA +-#define T0_PORT PORTA +-#define T0_PIN PINA +-#define T0_BIT 3 +- +-#define PCINT3_DDR DDRA +-#define PCINT3_PORT PORTA +-#define PCINT3_PIN PINA +-#define PCINT3_BIT 3 +- +-#define ADC2_DDR DDRA +-#define ADC2_PORT PORTA +-#define ADC2_PIN PINA +-#define ADC2_BIT 2 +- +-#define AIN1_DDR DDRA +-#define AIN1_PORT PORTA +-#define AIN1_PIN PINA +-#define AIN1_BIT 2 +- +-#define PCINT2_DDR DDRA +-#define PCINT2_PORT PORTA +-#define PCINT2_PIN PINA +-#define PCINT2_BIT 2 +- +-#define ADC1_DDR DDRA +-#define ADC1_PORT PORTA +-#define ADC1_PIN PINA +-#define ADC1_BIT 1 +- +-#define AIN0_DDR DDRA +-#define AIN0_PORT PORTA +-#define AIN0_PIN PINA +-#define AIN0_BIT 1 +- +-#define PCINT1_DDR DDRA +-#define PCINT1_PORT PORTA +-#define PCINT1_PIN PINA +-#define PCINT1_BIT 1 +- +-#define ADC0_DDR DDRA +-#define ADC0_PORT PORTA +-#define ADC0_PIN PINA +-#define ADC0_BIT 0 +- +-#define PCINT0_DDR DDRA +-#define PCINT0_PORT PORTA +-#define PCINT0_PIN PINA +-#define PCINT0_BIT 0 +- +-#define PCINT8_DDR DDRB +-#define PCINT8_PORT PORTB +-#define PCINT8_PIN PINB +-#define PCINT8_BIT 0 +- +-#define PCINT9_DDR DDRB +-#define PCINT9_PORT PORTB +-#define PCINT9_PIN PINB +-#define PCINT9_BIT 1 +- +-#define PCINT11_DDR DDRB +-#define PCINT11_PORT PORTB +-#define PCINT11_PIN PINB +-#define PCINT11_BIT 3 +- +-#define dW_DDR DDRB +-#define dW_PORT PORTB +-#define dW_PIN PINB +-#define dW_BIT 3 +- +-#define PCINT10_DDR DDRB +-#define PCINT10_PORT PORTB +-#define PCINT10_PIN PINB +-#define PCINT10_BIT 2 +- +-#define INT0_DDR DDRB +-#define INT0_PORT PORTB +-#define INT0_PIN PINB +-#define INT0_BIT 2 +- +-#define OC0A_DDR DDRB +-#define OC0A_PORT PORTB +-#define OC0A_PIN PINB +-#define OC0A_BIT 2 +- +-#define CKOUT_DDR DDRB +-#define CKOUT_PORT PORTB +-#define CKOUT_PIN PINB +-#define CKOUT_BIT 2 +- +-#define PCINT7_DDR DDRA +-#define PCINT7_PORT PORTA +-#define PCINT7_PIN PINA +-#define PCINT7_BIT 7 +- +-#define ICP1_DDR DDRA +-#define ICP1_PORT PORTA +-#define ICP1_PIN PINA +-#define ICP1_BIT 7 +- +-#define OC0B_DDR DDRA +-#define OC0B_PORT PORTA +-#define OC0B_PIN PINA +-#define OC0B_BIT 7 +- +-#define ADC7_DDR DDRA +-#define ADC7_PORT PORTA +-#define ADC7_PIN PINA +-#define ADC7_BIT 7 +- +-#define PCINT6_DDR DDRA +-#define PCINT6_PORT PORTA +-#define PCINT6_PIN PINA +-#define PCINT6_BIT 6 +- +-#define OC1A_DDR DDRA +-#define OC1A_PORT PORTA +-#define OC1A_PIN PINA +-#define OC1A_BIT 6 +- +-#define DI_DDR DDRA +-#define DI_PORT PORTA +-#define DI_PIN PINA +-#define DI_BIT 6 +- +-#define SDA_DDR DDRA +-#define SDA_PORT PORTA +-#define SDA_PIN PINA +-#define SDA_BIT 6 +- +-#define MOSI_DDR DDRA +-#define MOSI_PORT PORTA +-#define MOSI_PIN PINA +-#define MOSI_BIT 6 +- +-#define ADC6_DDR DDRA +-#define ADC6_PORT PORTA +-#define ADC6_PIN PINA +-#define ADC6_BIT 6 +- +-#define ADC5_DDR DDRA +-#define ADC5_PORT PORTA +-#define ADC5_PIN PINA +-#define ADC5_BIT 5 +- +-#define DO_DDR DDRA +-#define DO_PORT PORTA +-#define DO_PIN PINA +-#define DO_BIT 5 +- +-#define MISO_DDR DDRA +-#define MISO_PORT PORTA +-#define MISO_PIN PINA +-#define MISO_BIT 5 +- +-#define OC1B_DDR DDRA +-#define OC1B_PORT PORTA +-#define OC1B_PIN PINA +-#define OC1B_BIT 5 +- +-#define PCINT5_DDR DDRA +-#define PCINT5_PORT PORTA +-#define PCINT5_PIN PINA +-#define PCINT5_BIT 5 +- +-#endif /* _AVR_ATtiny84A_H_ */ +- ++/* Copyright (c) 2010 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn84a.h 2435 2014-08-11 10:31:52Z joerg_wunsch $ */ ++ ++/* avr/iotn84a.h - definitions for ATtiny84A */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn84a.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATtiny84A_H_ ++#define _AVR_ATtiny84A_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PRR _SFR_IO8(0x00) ++#define PRADC 0 ++#define PRUSI 1 ++#define PRTIM0 2 ++#define PRTIM1 3 ++ ++#define DIDR0 _SFR_IO8(0x01) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define ADCSRB _SFR_IO8(0x03) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ADLAR 4 ++#define ACME 6 ++#define BIN 7 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCW _SFR_IO16(0x04) ++ ++#define ADCL _SFR_IO8(0x04) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_IO8(0x05) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_IO8(0x06) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADMUX _SFR_IO8(0x07) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define MUX5 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define ACSR _SFR_IO8(0x08) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define TIFR1 _SFR_IO8(0x0B) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define TIMSK1 _SFR_IO8(0x0C) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define USICR _SFR_IO8(0x0D) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_IO8(0x0E) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_IO8(0x0F) ++#define USIDR0 0 ++#define USIDR1 1 ++#define USIDR2 2 ++#define USIDR3 3 ++#define USIDR4 4 ++#define USIDR5 5 ++#define USIDR6 6 ++#define USIDR7 7 ++ ++#define USIBR _SFR_IO8(0x10) ++#define USIBR0 0 ++#define USIBR1 1 ++#define USIBR2 2 ++#define USIBR3 3 ++#define USIBR4 4 ++#define USIBR5 5 ++#define USIBR6 6 ++#define USIBR7 7 ++ ++#define PCMSK0 _SFR_IO8(0x12) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define GPIOR0 _SFR_IO8(0x13) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define GPIOR1 _SFR_IO8(0x14) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x15) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define PINB _SFR_IO8(0x16) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++ ++#define DDRB _SFR_IO8(0x17) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++ ++#define PORTB _SFR_IO8(0x18) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++ ++#define PINA _SFR_IO8(0x19) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++#define PINA4 4 ++#define PINA5 5 ++#define PINA6 6 ++#define PINA7 7 ++ ++#define DDRA _SFR_IO8(0x1A) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++#define DDA4 4 ++#define DDA5 5 ++#define DDA6 6 ++#define DDA7 7 ++ ++#define PORTA _SFR_IO8(0x1B) ++#define PORTA0 0 ++#define PORTA1 1 ++#define PORTA2 2 ++#define PORTA3 3 ++#define PORTA4 4 ++#define PORTA5 5 ++#define PORTA6 6 ++#define PORTA7 7 ++ ++#define EECR _SFR_IO8(0x1C) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x1D) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x1E) ++ ++#define EEARL _SFR_IO8(0x1E) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x1F) ++#define EEAR8 0 ++ ++#define PCMSK1 _SFR_IO8(0x20) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++ ++#define WDTCSR _SFR_IO8(0x21) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define TCCR1C _SFR_IO8(0x22) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR10 0 ++#define TSM 7 ++ ++#define ICR1 _SFR_IO16(0x24) ++ ++#define ICR1L _SFR_IO8(0x24) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_IO8(0x25) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define CLKPR _SFR_IO8(0x26) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define DWDR _SFR_IO8(0x27) ++ ++#define OCR1B _SFR_IO16(0x28) ++ ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_IO8(0x29) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define OCR1A _SFR_IO16(0x2A) ++ ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_IO8(0x2B) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define TCNT1 _SFR_IO16(0x2C) ++ ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_IO8(0x2D) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define TCCR1B _SFR_IO8(0x2E) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1A _SFR_IO8(0x2F) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR0A _SFR_IO8(0x30) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define OSCCAL _SFR_IO8(0x31) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define TCNT0 _SFR_IO8(0x32) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define TCCR0B _SFR_IO8(0x33) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define ISC00 0 ++#define ISC01 1 ++#define BODSE 2 ++#define SM0 3 ++#define SM1 4 ++#define SE 5 ++#define PUD 6 ++#define BODS 7 ++ ++#define OCR0A _SFR_IO8(0x36) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define RFLB 3 ++#define CTPB 4 ++ ++#define TIFR0 _SFR_IO8(0x38) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIMSK0 _SFR_IO8(0x39) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define GIFR _SFR_IO8(0x3A) ++#define PCIF0 4 ++#define PCIF1 5 ++#define INTF0 6 ++ ++#define GIMSK _SFR_IO8(0x3B) ++#define PCIE0 4 ++#define PCIE1 5 ++#define INT0 6 ++ ++#define OCR0B _SFR_IO8(0x3C) ++#define OCR0_0 0 ++#define OCR0_1 1 ++#define OCR0_2 2 ++#define OCR0_3 3 ++#define OCR0_4 4 ++#define OCR0_5 5 ++#define OCR0_6 6 ++#define OCR0_7 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define EXT_INT0_vect_num 1 ++#define EXT_INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect_num 3 ++#define PCINT1_vect _VECTOR(3) /* Pin Change Interrupt Request 1 */ ++#define WATCHDOG_vect_num 4 ++#define WATCHDOG_vect _VECTOR(4) /* Watchdog Time-out */ ++#define TIM1_CAPT_vect_num 5 ++#define TIM1_CAPT_vect _VECTOR(5) /* Timer/Counter1 Capture Event */ ++#define TIM1_COMPA_vect_num 6 ++#define TIM1_COMPA_vect _VECTOR(6) /* Timer/Counter1 Compare Match A */ ++#define TIM1_COMPB_vect_num 7 ++#define TIM1_COMPB_vect _VECTOR(7) /* Timer/Counter1 Compare Match B */ ++#define TIM1_OVF_vect_num 8 ++#define TIM1_OVF_vect _VECTOR(8) /* Timer/Counter1 Overflow */ ++#define TIM0_COMPA_vect_num 9 ++#define TIM0_COMPA_vect _VECTOR(9) /* Timer/Counter0 Compare Match A */ ++#define TIM0_COMPB_vect_num 10 ++#define TIM0_COMPB_vect _VECTOR(10) /* Timer/Counter0 Compare Match B */ ++#define TIM0_OVF_vect_num 11 ++#define TIM0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ ++#define ANA_COMP_vect_num 12 ++#define ANA_COMP_vect _VECTOR(12) /* Analog Comparator */ ++#define ADC_vect_num 13 ++#define ADC_vect _VECTOR(13) /* ADC Conversion Complete */ ++#define EE_RDY_vect_num 14 ++#define EE_RDY_vect _VECTOR(14) /* EEPROM Ready */ ++#define USI_STR_vect_num 15 ++#define USI_STR_vect _VECTOR(15) /* USI START */ ++#define USI_OVF_vect_num 16 ++#define USI_OVF_vect _VECTOR(16) /* USI Overflow */ ++ ++#define _VECTOR_SIZE 2 /* Size of individual vector. */ ++#define _VECTORS_SIZE (17 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (64) ++#define RAMSTART (0x60) ++#define RAMSIZE (512) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x1FF) ++#define E2PAGESIZE (4) ++#define FLASHEND (0x1FFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x0C ++ ++ ++/* Device Pin Definitions */ ++#define ADC4_DDR DDRA ++#define ADC4_PORT PORTA ++#define ADC4_PIN PINA ++#define ADC4_BIT 4 ++ ++#define USCK_DDR DDRA ++#define USCK_PORT PORTA ++#define USCK_PIN PINA ++#define USCK_BIT 4 ++ ++#define SCL_DDR DDRA ++#define SCL_PORT PORTA ++#define SCL_PIN PINA ++#define SCL_BIT 4 ++ ++#define T1_DDR DDRA ++#define T1_PORT PORTA ++#define T1_PIN PINA ++#define T1_BIT 4 ++ ++#define PCINT4_DDR DDRA ++#define PCINT4_PORT PORTA ++#define PCINT4_PIN PINA ++#define PCINT4_BIT 4 ++ ++#define ADC3_DDR DDRA ++#define ADC3_PORT PORTA ++#define ADC3_PIN PINA ++#define ADC3_BIT 3 ++ ++#define T0_DDR DDRA ++#define T0_PORT PORTA ++#define T0_PIN PINA ++#define T0_BIT 3 ++ ++#define PCINT3_DDR DDRA ++#define PCINT3_PORT PORTA ++#define PCINT3_PIN PINA ++#define PCINT3_BIT 3 ++ ++#define ADC2_DDR DDRA ++#define ADC2_PORT PORTA ++#define ADC2_PIN PINA ++#define ADC2_BIT 2 ++ ++#define AIN1_DDR DDRA ++#define AIN1_PORT PORTA ++#define AIN1_PIN PINA ++#define AIN1_BIT 2 ++ ++#define PCINT2_DDR DDRA ++#define PCINT2_PORT PORTA ++#define PCINT2_PIN PINA ++#define PCINT2_BIT 2 ++ ++#define ADC1_DDR DDRA ++#define ADC1_PORT PORTA ++#define ADC1_PIN PINA ++#define ADC1_BIT 1 ++ ++#define AIN0_DDR DDRA ++#define AIN0_PORT PORTA ++#define AIN0_PIN PINA ++#define AIN0_BIT 1 ++ ++#define PCINT1_DDR DDRA ++#define PCINT1_PORT PORTA ++#define PCINT1_PIN PINA ++#define PCINT1_BIT 1 ++ ++#define ADC0_DDR DDRA ++#define ADC0_PORT PORTA ++#define ADC0_PIN PINA ++#define ADC0_BIT 0 ++ ++#define PCINT0_DDR DDRA ++#define PCINT0_PORT PORTA ++#define PCINT0_PIN PINA ++#define PCINT0_BIT 0 ++ ++#define PCINT8_DDR DDRB ++#define PCINT8_PORT PORTB ++#define PCINT8_PIN PINB ++#define PCINT8_BIT 0 ++ ++#define PCINT9_DDR DDRB ++#define PCINT9_PORT PORTB ++#define PCINT9_PIN PINB ++#define PCINT9_BIT 1 ++ ++#define PCINT11_DDR DDRB ++#define PCINT11_PORT PORTB ++#define PCINT11_PIN PINB ++#define PCINT11_BIT 3 ++ ++#define dW_DDR DDRB ++#define dW_PORT PORTB ++#define dW_PIN PINB ++#define dW_BIT 3 ++ ++#define PCINT10_DDR DDRB ++#define PCINT10_PORT PORTB ++#define PCINT10_PIN PINB ++#define PCINT10_BIT 2 ++ ++#define INT0_DDR DDRB ++#define INT0_PORT PORTB ++#define INT0_PIN PINB ++#define INT0_BIT 2 ++ ++#define OC0A_DDR DDRB ++#define OC0A_PORT PORTB ++#define OC0A_PIN PINB ++#define OC0A_BIT 2 ++ ++#define CKOUT_DDR DDRB ++#define CKOUT_PORT PORTB ++#define CKOUT_PIN PINB ++#define CKOUT_BIT 2 ++ ++#define PCINT7_DDR DDRA ++#define PCINT7_PORT PORTA ++#define PCINT7_PIN PINA ++#define PCINT7_BIT 7 ++ ++#define ICP1_DDR DDRA ++#define ICP1_PORT PORTA ++#define ICP1_PIN PINA ++#define ICP1_BIT 7 ++ ++#define OC0B_DDR DDRA ++#define OC0B_PORT PORTA ++#define OC0B_PIN PINA ++#define OC0B_BIT 7 ++ ++#define ADC7_DDR DDRA ++#define ADC7_PORT PORTA ++#define ADC7_PIN PINA ++#define ADC7_BIT 7 ++ ++#define PCINT6_DDR DDRA ++#define PCINT6_PORT PORTA ++#define PCINT6_PIN PINA ++#define PCINT6_BIT 6 ++ ++#define OC1A_DDR DDRA ++#define OC1A_PORT PORTA ++#define OC1A_PIN PINA ++#define OC1A_BIT 6 ++ ++#define DI_DDR DDRA ++#define DI_PORT PORTA ++#define DI_PIN PINA ++#define DI_BIT 6 ++ ++#define SDA_DDR DDRA ++#define SDA_PORT PORTA ++#define SDA_PIN PINA ++#define SDA_BIT 6 ++ ++#define MOSI_DDR DDRA ++#define MOSI_PORT PORTA ++#define MOSI_PIN PINA ++#define MOSI_BIT 6 ++ ++#define ADC6_DDR DDRA ++#define ADC6_PORT PORTA ++#define ADC6_PIN PINA ++#define ADC6_BIT 6 ++ ++#define ADC5_DDR DDRA ++#define ADC5_PORT PORTA ++#define ADC5_PIN PINA ++#define ADC5_BIT 5 ++ ++#define DO_DDR DDRA ++#define DO_PORT PORTA ++#define DO_PIN PINA ++#define DO_BIT 5 ++ ++#define MISO_DDR DDRA ++#define MISO_PORT PORTA ++#define MISO_PIN PINA ++#define MISO_BIT 5 ++ ++#define OC1B_DDR DDRA ++#define OC1B_PORT PORTA ++#define OC1B_PIN PINA ++#define OC1B_BIT 5 ++ ++#define PCINT5_DDR DDRA ++#define PCINT5_PORT PORTA ++#define PCINT5_PIN PINA ++#define PCINT5_BIT 5 ++ ++#endif /* _AVR_ATtiny84A_H_ */ ++ +diff --git a/include/avr/iotn85.h b/include/avr/iotn85.h +index afc675d..62f15ad 100644 +--- a/include/avr/iotn85.h ++++ b/include/avr/iotn85.h +@@ -1,90 +1,90 @@ +-/* Copyright (c) 2005, Joerg Wunsch +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn85.h 2115 2010-04-05 23:19:53Z arcanum $ */ +- +-/* avr/iotn85.h - definitions for ATtiny85 */ +- +-#ifndef _AVR_IOTN85_H_ +-#define _AVR_IOTN85_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 64 +-#define RAMSTART (0x60) +-#define RAMEND 0x25F +-#define XRAMEND RAMEND +-#define E2END 0x1FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x1FFF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_DWEN (unsigned char)~_BV(6) +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_SELFPRGEN (unsigned char)~_BV(0) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x93 +-#define SIGNATURE_2 0x0B +- +- +-#endif /* _AVR_IOTN85_H_ */ ++/* Copyright (c) 2005, Joerg Wunsch ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn85.h 2115 2010-04-05 23:19:53Z arcanum $ */ ++ ++/* avr/iotn85.h - definitions for ATtiny85 */ ++ ++#ifndef _AVR_IOTN85_H_ ++#define _AVR_IOTN85_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 64 ++#define RAMSTART (0x60) ++#define RAMEND 0x25F ++#define XRAMEND RAMEND ++#define E2END 0x1FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x1FFF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x0B ++ ++ ++#endif /* _AVR_IOTN85_H_ */ +diff --git a/include/avr/iotn861.h b/include/avr/iotn861.h +index b7337a0..95bb74f 100644 +--- a/include/avr/iotn861.h ++++ b/include/avr/iotn861.h +@@ -1,90 +1,90 @@ +-/* Copyright (c) 2006, Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn861.h 2115 2010-04-05 23:19:53Z arcanum $ */ +- +-/* avr/iotn861.h - definitions for ATtiny861 */ +- +-#ifndef _AVR_IOTN861_H_ +-#define _AVR_IOTN861_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 64 +-#define RAMSTART (0x60) +-#define RAMEND 0x25F +-#define XRAMEND RAMEND +-#define E2END 0x1FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x1FFF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_DWEN (unsigned char)~_BV(6) +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_SELFPRGEN (unsigned char)~_BV(0) +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x93 +-#define SIGNATURE_2 0x0D +- +- +-#endif /* _AVR_IOTN861_H_ */ ++/* Copyright (c) 2006, Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn861.h 2115 2010-04-05 23:19:53Z arcanum $ */ ++ ++/* avr/iotn861.h - definitions for ATtiny861 */ ++ ++#ifndef _AVR_IOTN861_H_ ++#define _AVR_IOTN861_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 64 ++#define RAMSTART (0x60) ++#define RAMEND 0x25F ++#define XRAMEND RAMEND ++#define E2END 0x1FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x1FFF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_DWEN (unsigned char)~_BV(6) ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x0D ++ ++ ++#endif /* _AVR_IOTN861_H_ */ +diff --git a/include/avr/iotn861a.h b/include/avr/iotn861a.h +index a629612..c21933a 100644 +--- a/include/avr/iotn861a.h ++++ b/include/avr/iotn861a.h +@@ -1,976 +1,976 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn861a.h 2063 2009-11-18 22:06:28Z arcanum $ */ +- +-/* avr/iotn861a.h - definitions for ATtiny861A */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn861a.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATtiny861A_H_ +-#define _AVR_ATtiny861A_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define TCCR1E _SFR_IO8(0x00) +-#define OC1OE0 0 +-#define OC1OE1 1 +-#define OC1OE2 2 +-#define OC1OE3 3 +-#define OC1OE4 4 +-#define OC1OE5 5 +- +-#define DIDR0 _SFR_IO8(0x01) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define AREFD 3 +-#define ADC3D 4 +-#define ADC4D 5 +-#define ADC5D 6 +-#define ADC6D 7 +- +-#define DIDR1 _SFR_IO8(0x02) +-#define ADC7D 4 +-#define ADC8D 5 +-#define ADC9D 6 +-#define ADC10D 7 +- +-#define ADCSRB _SFR_IO8(0x03) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define MUX5 3 +-#define REFS2 4 +-#define IPR 5 +-#define GSEL 6 +-#define BIN 7 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x04) +-#endif +-#define ADCW _SFR_IO16(0x04) +- +-#define ADCL _SFR_IO8(0x04) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_IO8(0x05) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_IO8(0x06) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADMUX _SFR_IO8(0x07) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define ACSRA _SFR_IO8(0x08) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACME 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define ACSRB _SFR_IO8(0x09) +-#define ACM0 0 +-#define ACM1 1 +-#define ACM2 2 +-#define HLEV 6 +-#define HSEL 7 +- +-#define GPIOR0 _SFR_IO8(0x0A) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define GPIOR1 _SFR_IO8(0x0B) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x0C) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define USICR _SFR_IO8(0x0D) +-#define USITC 0 +-#define USICLK 1 +-#define USICS0 2 +-#define USICS1 3 +-#define USIWM0 4 +-#define USIWM1 5 +-#define USIOIE 6 +-#define USISIE 7 +- +-#define USISR _SFR_IO8(0x0E) +-#define USICNT0 0 +-#define USICNT1 1 +-#define USICNT2 2 +-#define USICNT3 3 +-#define USIDC 4 +-#define USIPF 5 +-#define USIOIF 6 +-#define USISIF 7 +- +-#define USIDR _SFR_IO8(0x0F) +-#define USIDR0 0 +-#define USIDR1 1 +-#define USIDR2 2 +-#define USIDR3 3 +-#define USIDR4 4 +-#define USIDR5 5 +-#define USIDR6 6 +-#define USIDR7 7 +- +-#define USIBR _SFR_IO8(0x10) +-#define USIBR0 0 +-#define USIBR1 1 +-#define USIBR2 2 +-#define USIBR3 3 +-#define USIBR4 4 +-#define USIBR5 5 +-#define USIBR6 6 +-#define USIBR7 7 +- +-#define USIPP _SFR_IO8(0x11) +-#define USIPOS 0 +- +-#define OCR0B _SFR_IO8(0x12) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define OCR0A _SFR_IO8(0x13) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define TCNT0H _SFR_IO8(0x14) +-#define TCNT0H_0 0 +-#define TCNT0H_1 1 +-#define TCNT0H_2 2 +-#define TCNT0H_3 3 +-#define TCNT0H_4 4 +-#define TCNT0H_5 5 +-#define TCNT0H_6 6 +-#define TCNT0H_7 7 +- +-#define TCCR0A _SFR_IO8(0x15) +-#define WGM00 0 +-#define ACIC0 3 +-#define ICES0 4 +-#define ICNC0 5 +-#define ICEN0 6 +-#define TCW0 7 +- +-#define PINB _SFR_IO8(0x16) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x17) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x18) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINA _SFR_IO8(0x19) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +-#define PINA4 4 +-#define PINA5 5 +-#define PINA6 6 +-#define PINA7 7 +- +-#define DDRA _SFR_IO8(0x1A) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +-#define DDA4 4 +-#define DDA5 5 +-#define DDA6 6 +-#define DDA7 7 +- +-#define PORTA _SFR_IO8(0x1B) +-#define PORTA0 0 +-#define PORTA1 1 +-#define PORTA2 2 +-#define PORTA3 3 +-#define PORTA4 4 +-#define PORTA5 5 +-#define PORTA6 6 +-#define PORTA7 7 +- +-#define EECR _SFR_IO8(0x1C) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x1D) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x1E) +- +-#define EEARL _SFR_IO8(0x1E) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x1F) +-#define EEAR8 0 +- +-#define DWDR _SFR_IO8(0x20) +-#define DWDR0 0 +-#define DWDR1 1 +-#define DWDR2 2 +-#define DWDR3 3 +-#define DWDR4 4 +-#define DWDR5 5 +-#define DWDR6 6 +-#define DWDR7 7 +- +-#define WDTCR _SFR_IO8(0x21) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define PCMSK1 _SFR_IO8(0x22) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-#define PCMSK0 _SFR_IO8(0x23) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define DT1 _SFR_IO8(0x24) +-#define DT1L0 0 +-#define DT1L1 1 +-#define DT1L2 2 +-#define DT1L3 3 +-#define DT1H0 4 +-#define DT1H1 5 +-#define DT1H2 6 +-#define DT1H3 7 +- +-#define TC1H _SFR_IO8(0x25) +-#define TC18 0 +-#define TC19 1 +- +-#define TCCR1D _SFR_IO8(0x26) +-#define WGM10 0 +-#define WGM11 1 +-#define FPF1 2 +-#define FPAC1 3 +-#define FPES1 4 +-#define FPNC1 5 +-#define FPEN1 6 +-#define FPIE1 7 +- +-#define TCCR1C _SFR_IO8(0x27) +-#define PWM1D 0 +-#define FOC1D 1 +-#define COM1D0 2 +-#define COM1D1 3 +-#define COM1B0S 4 +-#define COM1B1S 5 +-#define COM1A0S 6 +-#define COM1A1S 7 +- +-#define CLKPR _SFR_IO8(0x28) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define PLLCSR _SFR_IO8(0x29) +-#define PLOCK 0 +-#define PLLE 1 +-#define PCKE 2 +-#define LSM 7 +- +-#define OCR1D _SFR_IO8(0x2A) +-#define OCR1D0 0 +-#define OCR1D1 1 +-#define OCR1D2 2 +-#define OCR1D3 3 +-#define OCR1D4 4 +-#define OCR1D5 5 +-#define OCR1D6 6 +-#define OCR1D7 7 +- +-#define OCR1C _SFR_IO8(0x2B) +-#define OCR1C0 0 +-#define OCR1C1 1 +-#define OCR1C2 2 +-#define OCR1C3 3 +-#define OCR1C4 4 +-#define OCR1C5 5 +-#define OCR1C6 6 +-#define OCR1C7 7 +- +-#define OCR1B _SFR_IO8(0x2C) +-#define OCR1B0 0 +-#define OCR1B1 1 +-#define OCR1B2 2 +-#define OCR1B3 3 +-#define OCR1B4 4 +-#define OCR1B5 5 +-#define OCR1B6 6 +-#define OCR1B7 7 +- +-#define OCR1A _SFR_IO8(0x2D) +-#define OCR1A0 0 +-#define OCR1A1 1 +-#define OCR1A2 2 +-#define OCR1A3 3 +-#define OCR1A4 4 +-#define OCR1A5 5 +-#define OCR1A6 6 +-#define OCR1A7 7 +- +-#define TCNT1 _SFR_IO8(0x2E) +-#define TC1H_0 0 +-#define TC1H_1 1 +-#define TC1H_2 2 +-#define TC1H_3 3 +-#define TC1H_4 4 +-#define TC1H_5 5 +-#define TC1H_6 6 +-#define TC1H_7 7 +- +-#define TCCR1B _SFR_IO8(0x2F) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define CS13 3 +-#define DTPS10 4 +-#define DTPS11 5 +-#define PSR1 6 +- +-#define TCCR1A _SFR_IO8(0x30) +-#define PWM1B 0 +-#define PWM1A 1 +-#define FOC1B 2 +-#define FOC1A 3 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define OSCCAL _SFR_IO8(0x31) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define TCNT0L _SFR_IO8(0x32) +-#define TCNT0L_0 0 +-#define TCNT0L_1 1 +-#define TCNT0L_2 2 +-#define TCNT0L_3 3 +-#define TCNT0L_4 4 +-#define TCNT0L_5 5 +-#define TCNT0L_6 6 +-#define TCNT0L_7 7 +- +-#define TCCR0B _SFR_IO8(0x33) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define PSR0 3 +-#define TSM 4 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x35) +-#define ISC00 0 +-#define ISC01 1 +-#define BODSE 2 +-#define SM0 3 +-#define SM1 4 +-#define SE 5 +-#define PUD 6 +-#define BODS 7 +- +-#define PRR _SFR_IO8(0x36) +-#define PRADC 0 +-#define PRUSI 1 +-#define PRTIM0 2 +-#define PRTIM1 3 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define RFLB 3 +-#define CTPB 4 +- +-#define TIFR _SFR_IO8(0x38) +-#define ICF0 0 +-#define TOV0 1 +-#define TOV1 2 +-#define OCF0B 3 +-#define OCF0A 4 +-#define OCF1B 5 +-#define OCF1A 6 +-#define OCF1D 7 +- +-#define TIMSK _SFR_IO8(0x39) +-#define TICIE0 0 +-#define TOIE0 1 +-#define TOIE1 2 +-#define OCIE0B 3 +-#define OCIE0A 4 +-#define OCIE1B 5 +-#define OCIE1A 6 +-#define OCIE1D 7 +- +-#define GIFR _SFR_IO8(0x3A) +-#define PCIF 5 +-#define INTF0 6 +-#define INTF1 7 +- +-#define GIMSK _SFR_IO8(0x3B) +-#define PCIE0 4 +-#define PCIE1 5 +-#define INT0 6 +-#define INT1 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt 0 */ +-#define PCINT_vect_num 2 +-#define PCINT_vect _VECTOR(2) /* Pin Change Interrupt */ +-#define TIMER1_COMPA_vect_num 3 +-#define TIMER1_COMPA_vect _VECTOR(3) /* Timer/Counter1 Compare Match 1A */ +-#define TIMER1_COMPB_vect_num 4 +-#define TIMER1_COMPB_vect _VECTOR(4) /* Timer/Counter1 Compare Match 1B */ +-#define TIMER1_OVF_vect_num 5 +-#define TIMER1_OVF_vect _VECTOR(5) /* Timer/Counter1 Overflow */ +-#define TIMER0_OVF_vect_num 6 +-#define TIMER0_OVF_vect _VECTOR(6) /* Timer/Counter0 Overflow */ +-#define USI_START_vect_num 7 +-#define USI_START_vect _VECTOR(7) /* USI Start */ +-#define USI_OVF_vect_num 8 +-#define USI_OVF_vect _VECTOR(8) /* USI Overflow */ +-#define EE_RDY_vect_num 9 +-#define EE_RDY_vect _VECTOR(9) /* EEPROM Ready */ +-#define ANA_COMP_vect_num 10 +-#define ANA_COMP_vect _VECTOR(10) /* Analog Comparator */ +-#define ADC_vect_num 11 +-#define ADC_vect _VECTOR(11) /* ADC Conversion Complete */ +-#define WDT_vect_num 12 +-#define WDT_vect _VECTOR(12) /* Watchdog Time-Out */ +-#define INT1_vect_num 13 +-#define INT1_vect _VECTOR(13) /* External Interrupt 1 */ +-#define TIMER0_COMPA_vect_num 14 +-#define TIMER0_COMPA_vect _VECTOR(14) /* Timer/Counter0 Compare Match A */ +-#define TIMER0_COMPB_vect_num 15 +-#define TIMER0_COMPB_vect _VECTOR(15) /* Timer/Counter0 Compare Match B */ +-#define TIMER0_CAPT_vect_num 16 +-#define TIMER0_CAPT_vect _VECTOR(16) /* ADC Conversion Complete */ +-#define TIMER1_COMPD_vect_num 17 +-#define TIMER1_COMPD_vect _VECTOR(17) /* Timer/Counter1 Compare Match D */ +-#define FAULT_PROTECTION_vect_num 18 +-#define FAULT_PROTECTION_vect _VECTOR(18) /* Timer/Counter1 Fault Protection */ +- +-#define _VECTOR_SIZE 2 /* Size of individual vector. */ +-#define _VECTORS_SIZE (19 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (64) +-#define RAMSTART (0x60) +-#define RAMSIZE (512) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x1FF) +-#define E2PAGESIZE (4) +-#define FLASHEND (0x1FFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always on */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x93 +-#define SIGNATURE_2 0x0D +- +- +-/* Device Pin Definitions */ +-#define DI_B_DDR DDRMOSI +-#define DI_B_PORT PORTMOSI +-#define DI_B_PIN PINMOSI +-#define DI_B_BIT MOSI +- +-#define SDA_B_DDR DDRMOSI +-#define SDA_B_PORT PORTMOSI +-#define SDA_B_PIN PINMOSI +-#define SDA_B_BIT MOSI +- +-#define _OC1A_DDR DDRMOSI +-#define _OC1A_PORT PORTMOSI +-#define _OC1A_PIN PINMOSI +-#define _OC1A_BIT MOSI +- +-#define PCINT8_DDR DDRMOSI +-#define PCINT8_PORT PORTMOSI +-#define PCINT8_PIN PINMOSI +-#define PCINT8_BIT MOSI +- +-#define PB0_DDR DDRMOSI +-#define PB0_PORT PORTMOSI +-#define PB0_PIN PINMOSI +-#define PB0_BIT MOSI +- +-#define DO_B_DDR DDRMISO +-#define DO_B_PORT PORTMISO +-#define DO_B_PIN PINMISO +-#define DO_B_BIT MISO +- +-#define OC1A_DDR DDRMISO +-#define OC1A_PORT PORTMISO +-#define OC1A_PIN PINMISO +-#define OC1A_BIT MISO +- +-#define PCINT9_DDR DDRMISO +-#define PCINT9_PORT PORTMISO +-#define PCINT9_PIN PINMISO +-#define PCINT9_BIT MISO +- +-#define PB1_DDR DDRMISO +-#define PB1_PORT PORTMISO +-#define PB1_PIN PINMISO +-#define PB1_BIT MISO +- +-#define USCK_B_DDR DDRSCK +-#define USCK_B_PORT PORTSCK +-#define USCK_B_PIN PINSCK +-#define USCK_B_BIT SCK +- +-#define SCL_B_DDR DDRSCK +-#define SCL_B_PORT PORTSCK +-#define SCL_B_PIN PINSCK +-#define SCL_B_BIT SCK +- +-#define OC1B_DDR DDRSCK +-#define OC1B_PORT PORTSCK +-#define OC1B_PIN PINSCK +-#define OC1B_BIT SCK +- +-#define PCINT10_DDR DDRSCK +-#define PCINT10_PORT PORTSCK +-#define PCINT10_PIN PINSCK +-#define PCINT10_BIT SCK +- +-#define PB2_DDR DDRSCK +-#define PB2_PORT PORTSCK +-#define PB2_PIN PINSCK +-#define PB2_BIT SCK +- +-#define PCINT11_DDR DDROC1B +-#define PCINT11_PORT PORTOC1B +-#define PCINT11_PIN PINOC1B +-#define PCINT11_BIT OC1B +- +-#define PB3_DDR DDROC1B +-#define PB3_PORT PORTOC1B +-#define PB3_PIN PINOC1B +-#define PB3_BIT OC1B +- +-#define PCINT12_DDR DDRADC +-#define PCINT12_PORT PORTADC +-#define PCINT12_PIN PINADC +-#define PCINT12_BIT ADC7 +- +-#define _OC1D_DDR DDRADC +-#define _OC1D_PORT PORTADC +-#define _OC1D_PIN PINADC +-#define _OC1D_BIT ADC7 +- +-#define CLKI_DDR DDRADC +-#define CLKI_PORT PORTADC +-#define CLKI_PIN PINADC +-#define CLKI_BIT ADC7 +- +-#define PB4_DDR DDRADC +-#define PB4_PORT PORTADC +-#define PB4_PIN PINADC +-#define PB4_BIT ADC7 +- +-#define PCINT13_DDR DDRADC +-#define PCINT13_PORT PORTADC +-#define PCINT13_PIN PINADC +-#define PCINT13_BIT ADC8 +- +-#define OC1D_DDR DDRADC +-#define OC1D_PORT PORTADC +-#define OC1D_PIN PINADC +-#define OC1D_BIT ADC8 +- +-#define CKLO_DDR DDRADC +-#define CKLO_PORT PORTADC +-#define CKLO_PIN PINADC +-#define CKLO_BIT ADC8 +- +-#define PB5_DDR DDRADC +-#define PB5_PORT PORTADC +-#define PB5_PIN PINADC +-#define PB5_BIT ADC8 +- +-#define INT0_DDR DDRADC +-#define INT0_PORT PORTADC +-#define INT0_PIN PINADC +-#define INT0_BIT ADC9 +- +-#define T0_DDR DDRADC +-#define T0_PORT PORTADC +-#define T0_PIN PINADC +-#define T0_BIT ADC9 +- +-#define PCINT14_DDR DDRADC +-#define PCINT14_PORT PORTADC +-#define PCINT14_PIN PINADC +-#define PCINT14_BIT ADC9 +- +-#define PB6_DDR DDRADC +-#define PB6_PORT PORTADC +-#define PB6_PIN PINADC +-#define PB6_BIT ADC9 +- +-#define PCINT15_DDR DDRADC1 +-#define PCINT15_PORT PORTADC1 +-#define PCINT15_PIN PINADC1 +-#define PCINT15_BIT ADC10 +- +-#define PB7_DDR DDRADC1 +-#define PB7_PORT PORTADC1 +-#define PB7_PIN PINADC1 +-#define PB7_BIT ADC10 +- +-#define AIN1_DDR DDRADC +-#define AIN1_PORT PORTADC +-#define AIN1_PIN PINADC +-#define AIN1_BIT ADC6 +- +-#define PCINT7_DDR DDRADC +-#define PCINT7_PORT PORTADC +-#define PCINT7_PIN PINADC +-#define PCINT7_BIT ADC6 +- +-#define PA7_DDR DDRADC +-#define PA7_PORT PORTADC +-#define PA7_PIN PINADC +-#define PA7_BIT ADC6 +- +-#define AIN0_DDR DDRADC +-#define AIN0_PORT PORTADC +-#define AIN0_PIN PINADC +-#define AIN0_BIT ADC5 +- +-#define PCINT6_DDR DDRADC +-#define PCINT6_PORT PORTADC +-#define PCINT6_PIN PINADC +-#define PCINT6_BIT ADC5 +- +-#define PA6_DDR DDRADC +-#define PA6_PORT PORTADC +-#define PA6_PIN PINADC +-#define PA6_BIT ADC5 +- +-#define AIN2_DDR DDRADC +-#define AIN2_PORT PORTADC +-#define AIN2_PIN PINADC +-#define AIN2_BIT ADC4 +- +-#define PCINT5_DDR DDRADC +-#define PCINT5_PORT PORTADC +-#define PCINT5_PIN PINADC +-#define PCINT5_BIT ADC4 +- +-#define PA5_DDR DDRADC +-#define PA5_PORT PORTADC +-#define PA5_PIN PINADC +-#define PA5_BIT ADC4 +- +-#define ICP0_DDR DDRADC +-#define ICP0_PORT PORTADC +-#define ICP0_PIN PINADC +-#define ICP0_BIT ADC3 +- +-#define PCINT4_DDR DDRADC +-#define PCINT4_PORT PORTADC +-#define PCINT4_PIN PINADC +-#define PCINT4_BIT ADC3 +- +-#define PA4_DDR DDRADC +-#define PA4_PORT PORTADC +-#define PA4_PIN PINADC +-#define PA4_BIT ADC3 +- +-#define PCINT3_DDR DDRAREF +-#define PCINT3_PORT PORTAREF +-#define PCINT3_PIN PINAREF +-#define PCINT3_BIT AREF +- +-#define PA3_DDR DDRAREF +-#define PA3_PORT PORTAREF +-#define PA3_PIN PINAREF +-#define PA3_BIT AREF +- +-#define INT1_DDR DDRADC +-#define INT1_PORT PORTADC +-#define INT1_PIN PINADC +-#define INT1_BIT ADC2 +- +-#define USCK_A_DDR DDRADC +-#define USCK_A_PORT PORTADC +-#define USCK_A_PIN PINADC +-#define USCK_A_BIT ADC2 +- +-#define SCL_A_DDR DDRADC +-#define SCL_A_PORT PORTADC +-#define SCL_A_PIN PINADC +-#define SCL_A_BIT ADC2 +- +-#define PCINT2_DDR DDRADC +-#define PCINT2_PORT PORTADC +-#define PCINT2_PIN PINADC +-#define PCINT2_BIT ADC2 +- +-#define PA2_DDR DDRADC +-#define PA2_PORT PORTADC +-#define PA2_PIN PINADC +-#define PA2_BIT ADC2 +- +-#define DO_A_DDR DDRADC +-#define DO_A_PORT PORTADC +-#define DO_A_PIN PINADC +-#define DO_A_BIT ADC1 +- +-#define PCINT1_DDR DDRADC +-#define PCINT1_PORT PORTADC +-#define PCINT1_PIN PINADC +-#define PCINT1_BIT ADC1 +- +-#define PA1_DDR DDRADC +-#define PA1_PORT PORTADC +-#define PA1_PIN PINADC +-#define PA1_BIT ADC1 +- +-#define DI_A_DDR DDRADC +-#define DI_A_PORT PORTADC +-#define DI_A_PIN PINADC +-#define DI_A_BIT ADC0 +- +-#define SDA_A_DDR DDRADC +-#define SDA_A_PORT PORTADC +-#define SDA_A_PIN PINADC +-#define SDA_A_BIT ADC0 +- +-#define PCINT0_DDR DDRADC +-#define PCINT0_PORT PORTADC +-#define PCINT0_PIN PINADC +-#define PCINT0_BIT ADC0 +- +-#define PA0_DDR DDRADC +-#define PA0_PORT PORTADC +-#define PA0_PIN PINADC +-#define PA0_BIT ADC0 +- +-#endif /* _AVR_ATtiny861A_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn861a.h 2063 2009-11-18 22:06:28Z arcanum $ */ ++ ++/* avr/iotn861a.h - definitions for ATtiny861A */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn861a.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATtiny861A_H_ ++#define _AVR_ATtiny861A_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define TCCR1E _SFR_IO8(0x00) ++#define OC1OE0 0 ++#define OC1OE1 1 ++#define OC1OE2 2 ++#define OC1OE3 3 ++#define OC1OE4 4 ++#define OC1OE5 5 ++ ++#define DIDR0 _SFR_IO8(0x01) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define AREFD 3 ++#define ADC3D 4 ++#define ADC4D 5 ++#define ADC5D 6 ++#define ADC6D 7 ++ ++#define DIDR1 _SFR_IO8(0x02) ++#define ADC7D 4 ++#define ADC8D 5 ++#define ADC9D 6 ++#define ADC10D 7 ++ ++#define ADCSRB _SFR_IO8(0x03) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define MUX5 3 ++#define REFS2 4 ++#define IPR 5 ++#define GSEL 6 ++#define BIN 7 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCW _SFR_IO16(0x04) ++ ++#define ADCL _SFR_IO8(0x04) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_IO8(0x05) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_IO8(0x06) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADMUX _SFR_IO8(0x07) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define ACSRA _SFR_IO8(0x08) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACME 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define ACSRB _SFR_IO8(0x09) ++#define ACM0 0 ++#define ACM1 1 ++#define ACM2 2 ++#define HLEV 6 ++#define HSEL 7 ++ ++#define GPIOR0 _SFR_IO8(0x0A) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define GPIOR1 _SFR_IO8(0x0B) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x0C) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define USICR _SFR_IO8(0x0D) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_IO8(0x0E) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_IO8(0x0F) ++#define USIDR0 0 ++#define USIDR1 1 ++#define USIDR2 2 ++#define USIDR3 3 ++#define USIDR4 4 ++#define USIDR5 5 ++#define USIDR6 6 ++#define USIDR7 7 ++ ++#define USIBR _SFR_IO8(0x10) ++#define USIBR0 0 ++#define USIBR1 1 ++#define USIBR2 2 ++#define USIBR3 3 ++#define USIBR4 4 ++#define USIBR5 5 ++#define USIBR6 6 ++#define USIBR7 7 ++ ++#define USIPP _SFR_IO8(0x11) ++#define USIPOS 0 ++ ++#define OCR0B _SFR_IO8(0x12) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define OCR0A _SFR_IO8(0x13) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define TCNT0H _SFR_IO8(0x14) ++#define TCNT0H_0 0 ++#define TCNT0H_1 1 ++#define TCNT0H_2 2 ++#define TCNT0H_3 3 ++#define TCNT0H_4 4 ++#define TCNT0H_5 5 ++#define TCNT0H_6 6 ++#define TCNT0H_7 7 ++ ++#define TCCR0A _SFR_IO8(0x15) ++#define WGM00 0 ++#define ACIC0 3 ++#define ICES0 4 ++#define ICNC0 5 ++#define ICEN0 6 ++#define TCW0 7 ++ ++#define PINB _SFR_IO8(0x16) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x17) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x18) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINA _SFR_IO8(0x19) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++#define PINA4 4 ++#define PINA5 5 ++#define PINA6 6 ++#define PINA7 7 ++ ++#define DDRA _SFR_IO8(0x1A) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++#define DDA4 4 ++#define DDA5 5 ++#define DDA6 6 ++#define DDA7 7 ++ ++#define PORTA _SFR_IO8(0x1B) ++#define PORTA0 0 ++#define PORTA1 1 ++#define PORTA2 2 ++#define PORTA3 3 ++#define PORTA4 4 ++#define PORTA5 5 ++#define PORTA6 6 ++#define PORTA7 7 ++ ++#define EECR _SFR_IO8(0x1C) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x1D) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x1E) ++ ++#define EEARL _SFR_IO8(0x1E) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x1F) ++#define EEAR8 0 ++ ++#define DWDR _SFR_IO8(0x20) ++#define DWDR0 0 ++#define DWDR1 1 ++#define DWDR2 2 ++#define DWDR3 3 ++#define DWDR4 4 ++#define DWDR5 5 ++#define DWDR6 6 ++#define DWDR7 7 ++ ++#define WDTCR _SFR_IO8(0x21) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define PCMSK1 _SFR_IO8(0x22) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK0 _SFR_IO8(0x23) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define DT1 _SFR_IO8(0x24) ++#define DT1L0 0 ++#define DT1L1 1 ++#define DT1L2 2 ++#define DT1L3 3 ++#define DT1H0 4 ++#define DT1H1 5 ++#define DT1H2 6 ++#define DT1H3 7 ++ ++#define TC1H _SFR_IO8(0x25) ++#define TC18 0 ++#define TC19 1 ++ ++#define TCCR1D _SFR_IO8(0x26) ++#define WGM10 0 ++#define WGM11 1 ++#define FPF1 2 ++#define FPAC1 3 ++#define FPES1 4 ++#define FPNC1 5 ++#define FPEN1 6 ++#define FPIE1 7 ++ ++#define TCCR1C _SFR_IO8(0x27) ++#define PWM1D 0 ++#define FOC1D 1 ++#define COM1D0 2 ++#define COM1D1 3 ++#define COM1B0S 4 ++#define COM1B1S 5 ++#define COM1A0S 6 ++#define COM1A1S 7 ++ ++#define CLKPR _SFR_IO8(0x28) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define PLLCSR _SFR_IO8(0x29) ++#define PLOCK 0 ++#define PLLE 1 ++#define PCKE 2 ++#define LSM 7 ++ ++#define OCR1D _SFR_IO8(0x2A) ++#define OCR1D0 0 ++#define OCR1D1 1 ++#define OCR1D2 2 ++#define OCR1D3 3 ++#define OCR1D4 4 ++#define OCR1D5 5 ++#define OCR1D6 6 ++#define OCR1D7 7 ++ ++#define OCR1C _SFR_IO8(0x2B) ++#define OCR1C0 0 ++#define OCR1C1 1 ++#define OCR1C2 2 ++#define OCR1C3 3 ++#define OCR1C4 4 ++#define OCR1C5 5 ++#define OCR1C6 6 ++#define OCR1C7 7 ++ ++#define OCR1B _SFR_IO8(0x2C) ++#define OCR1B0 0 ++#define OCR1B1 1 ++#define OCR1B2 2 ++#define OCR1B3 3 ++#define OCR1B4 4 ++#define OCR1B5 5 ++#define OCR1B6 6 ++#define OCR1B7 7 ++ ++#define OCR1A _SFR_IO8(0x2D) ++#define OCR1A0 0 ++#define OCR1A1 1 ++#define OCR1A2 2 ++#define OCR1A3 3 ++#define OCR1A4 4 ++#define OCR1A5 5 ++#define OCR1A6 6 ++#define OCR1A7 7 ++ ++#define TCNT1 _SFR_IO8(0x2E) ++#define TC1H_0 0 ++#define TC1H_1 1 ++#define TC1H_2 2 ++#define TC1H_3 3 ++#define TC1H_4 4 ++#define TC1H_5 5 ++#define TC1H_6 6 ++#define TC1H_7 7 ++ ++#define TCCR1B _SFR_IO8(0x2F) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define CS13 3 ++#define DTPS10 4 ++#define DTPS11 5 ++#define PSR1 6 ++ ++#define TCCR1A _SFR_IO8(0x30) ++#define PWM1B 0 ++#define PWM1A 1 ++#define FOC1B 2 ++#define FOC1A 3 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define OSCCAL _SFR_IO8(0x31) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define TCNT0L _SFR_IO8(0x32) ++#define TCNT0L_0 0 ++#define TCNT0L_1 1 ++#define TCNT0L_2 2 ++#define TCNT0L_3 3 ++#define TCNT0L_4 4 ++#define TCNT0L_5 5 ++#define TCNT0L_6 6 ++#define TCNT0L_7 7 ++ ++#define TCCR0B _SFR_IO8(0x33) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define PSR0 3 ++#define TSM 4 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define ISC00 0 ++#define ISC01 1 ++#define BODSE 2 ++#define SM0 3 ++#define SM1 4 ++#define SE 5 ++#define PUD 6 ++#define BODS 7 ++ ++#define PRR _SFR_IO8(0x36) ++#define PRADC 0 ++#define PRUSI 1 ++#define PRTIM0 2 ++#define PRTIM1 3 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define RFLB 3 ++#define CTPB 4 ++ ++#define TIFR _SFR_IO8(0x38) ++#define ICF0 0 ++#define TOV0 1 ++#define TOV1 2 ++#define OCF0B 3 ++#define OCF0A 4 ++#define OCF1B 5 ++#define OCF1A 6 ++#define OCF1D 7 ++ ++#define TIMSK _SFR_IO8(0x39) ++#define TICIE0 0 ++#define TOIE0 1 ++#define TOIE1 2 ++#define OCIE0B 3 ++#define OCIE0A 4 ++#define OCIE1B 5 ++#define OCIE1A 6 ++#define OCIE1D 7 ++ ++#define GIFR _SFR_IO8(0x3A) ++#define PCIF 5 ++#define INTF0 6 ++#define INTF1 7 ++ ++#define GIMSK _SFR_IO8(0x3B) ++#define PCIE0 4 ++#define PCIE1 5 ++#define INT0 6 ++#define INT1 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt 0 */ ++#define PCINT_vect_num 2 ++#define PCINT_vect _VECTOR(2) /* Pin Change Interrupt */ ++#define TIMER1_COMPA_vect_num 3 ++#define TIMER1_COMPA_vect _VECTOR(3) /* Timer/Counter1 Compare Match 1A */ ++#define TIMER1_COMPB_vect_num 4 ++#define TIMER1_COMPB_vect _VECTOR(4) /* Timer/Counter1 Compare Match 1B */ ++#define TIMER1_OVF_vect_num 5 ++#define TIMER1_OVF_vect _VECTOR(5) /* Timer/Counter1 Overflow */ ++#define TIMER0_OVF_vect_num 6 ++#define TIMER0_OVF_vect _VECTOR(6) /* Timer/Counter0 Overflow */ ++#define USI_START_vect_num 7 ++#define USI_START_vect _VECTOR(7) /* USI Start */ ++#define USI_OVF_vect_num 8 ++#define USI_OVF_vect _VECTOR(8) /* USI Overflow */ ++#define EE_RDY_vect_num 9 ++#define EE_RDY_vect _VECTOR(9) /* EEPROM Ready */ ++#define ANA_COMP_vect_num 10 ++#define ANA_COMP_vect _VECTOR(10) /* Analog Comparator */ ++#define ADC_vect_num 11 ++#define ADC_vect _VECTOR(11) /* ADC Conversion Complete */ ++#define WDT_vect_num 12 ++#define WDT_vect _VECTOR(12) /* Watchdog Time-Out */ ++#define INT1_vect_num 13 ++#define INT1_vect _VECTOR(13) /* External Interrupt 1 */ ++#define TIMER0_COMPA_vect_num 14 ++#define TIMER0_COMPA_vect _VECTOR(14) /* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPB_vect_num 15 ++#define TIMER0_COMPB_vect _VECTOR(15) /* Timer/Counter0 Compare Match B */ ++#define TIMER0_CAPT_vect_num 16 ++#define TIMER0_CAPT_vect _VECTOR(16) /* ADC Conversion Complete */ ++#define TIMER1_COMPD_vect_num 17 ++#define TIMER1_COMPD_vect _VECTOR(17) /* Timer/Counter1 Compare Match D */ ++#define FAULT_PROTECTION_vect_num 18 ++#define FAULT_PROTECTION_vect _VECTOR(18) /* Timer/Counter1 Fault Protection */ ++ ++#define _VECTOR_SIZE 2 /* Size of individual vector. */ ++#define _VECTORS_SIZE (19 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (64) ++#define RAMSTART (0x60) ++#define RAMSIZE (512) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x1FF) ++#define E2PAGESIZE (4) ++#define FLASHEND (0x1FFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always on */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x0D ++ ++ ++/* Device Pin Definitions */ ++#define DI_B_DDR DDRMOSI ++#define DI_B_PORT PORTMOSI ++#define DI_B_PIN PINMOSI ++#define DI_B_BIT MOSI ++ ++#define SDA_B_DDR DDRMOSI ++#define SDA_B_PORT PORTMOSI ++#define SDA_B_PIN PINMOSI ++#define SDA_B_BIT MOSI ++ ++#define _OC1A_DDR DDRMOSI ++#define _OC1A_PORT PORTMOSI ++#define _OC1A_PIN PINMOSI ++#define _OC1A_BIT MOSI ++ ++#define PCINT8_DDR DDRMOSI ++#define PCINT8_PORT PORTMOSI ++#define PCINT8_PIN PINMOSI ++#define PCINT8_BIT MOSI ++ ++#define PB0_DDR DDRMOSI ++#define PB0_PORT PORTMOSI ++#define PB0_PIN PINMOSI ++#define PB0_BIT MOSI ++ ++#define DO_B_DDR DDRMISO ++#define DO_B_PORT PORTMISO ++#define DO_B_PIN PINMISO ++#define DO_B_BIT MISO ++ ++#define OC1A_DDR DDRMISO ++#define OC1A_PORT PORTMISO ++#define OC1A_PIN PINMISO ++#define OC1A_BIT MISO ++ ++#define PCINT9_DDR DDRMISO ++#define PCINT9_PORT PORTMISO ++#define PCINT9_PIN PINMISO ++#define PCINT9_BIT MISO ++ ++#define PB1_DDR DDRMISO ++#define PB1_PORT PORTMISO ++#define PB1_PIN PINMISO ++#define PB1_BIT MISO ++ ++#define USCK_B_DDR DDRSCK ++#define USCK_B_PORT PORTSCK ++#define USCK_B_PIN PINSCK ++#define USCK_B_BIT SCK ++ ++#define SCL_B_DDR DDRSCK ++#define SCL_B_PORT PORTSCK ++#define SCL_B_PIN PINSCK ++#define SCL_B_BIT SCK ++ ++#define OC1B_DDR DDRSCK ++#define OC1B_PORT PORTSCK ++#define OC1B_PIN PINSCK ++#define OC1B_BIT SCK ++ ++#define PCINT10_DDR DDRSCK ++#define PCINT10_PORT PORTSCK ++#define PCINT10_PIN PINSCK ++#define PCINT10_BIT SCK ++ ++#define PB2_DDR DDRSCK ++#define PB2_PORT PORTSCK ++#define PB2_PIN PINSCK ++#define PB2_BIT SCK ++ ++#define PCINT11_DDR DDROC1B ++#define PCINT11_PORT PORTOC1B ++#define PCINT11_PIN PINOC1B ++#define PCINT11_BIT OC1B ++ ++#define PB3_DDR DDROC1B ++#define PB3_PORT PORTOC1B ++#define PB3_PIN PINOC1B ++#define PB3_BIT OC1B ++ ++#define PCINT12_DDR DDRADC ++#define PCINT12_PORT PORTADC ++#define PCINT12_PIN PINADC ++#define PCINT12_BIT ADC7 ++ ++#define _OC1D_DDR DDRADC ++#define _OC1D_PORT PORTADC ++#define _OC1D_PIN PINADC ++#define _OC1D_BIT ADC7 ++ ++#define CLKI_DDR DDRADC ++#define CLKI_PORT PORTADC ++#define CLKI_PIN PINADC ++#define CLKI_BIT ADC7 ++ ++#define PB4_DDR DDRADC ++#define PB4_PORT PORTADC ++#define PB4_PIN PINADC ++#define PB4_BIT ADC7 ++ ++#define PCINT13_DDR DDRADC ++#define PCINT13_PORT PORTADC ++#define PCINT13_PIN PINADC ++#define PCINT13_BIT ADC8 ++ ++#define OC1D_DDR DDRADC ++#define OC1D_PORT PORTADC ++#define OC1D_PIN PINADC ++#define OC1D_BIT ADC8 ++ ++#define CKLO_DDR DDRADC ++#define CKLO_PORT PORTADC ++#define CKLO_PIN PINADC ++#define CKLO_BIT ADC8 ++ ++#define PB5_DDR DDRADC ++#define PB5_PORT PORTADC ++#define PB5_PIN PINADC ++#define PB5_BIT ADC8 ++ ++#define INT0_DDR DDRADC ++#define INT0_PORT PORTADC ++#define INT0_PIN PINADC ++#define INT0_BIT ADC9 ++ ++#define T0_DDR DDRADC ++#define T0_PORT PORTADC ++#define T0_PIN PINADC ++#define T0_BIT ADC9 ++ ++#define PCINT14_DDR DDRADC ++#define PCINT14_PORT PORTADC ++#define PCINT14_PIN PINADC ++#define PCINT14_BIT ADC9 ++ ++#define PB6_DDR DDRADC ++#define PB6_PORT PORTADC ++#define PB6_PIN PINADC ++#define PB6_BIT ADC9 ++ ++#define PCINT15_DDR DDRADC1 ++#define PCINT15_PORT PORTADC1 ++#define PCINT15_PIN PINADC1 ++#define PCINT15_BIT ADC10 ++ ++#define PB7_DDR DDRADC1 ++#define PB7_PORT PORTADC1 ++#define PB7_PIN PINADC1 ++#define PB7_BIT ADC10 ++ ++#define AIN1_DDR DDRADC ++#define AIN1_PORT PORTADC ++#define AIN1_PIN PINADC ++#define AIN1_BIT ADC6 ++ ++#define PCINT7_DDR DDRADC ++#define PCINT7_PORT PORTADC ++#define PCINT7_PIN PINADC ++#define PCINT7_BIT ADC6 ++ ++#define PA7_DDR DDRADC ++#define PA7_PORT PORTADC ++#define PA7_PIN PINADC ++#define PA7_BIT ADC6 ++ ++#define AIN0_DDR DDRADC ++#define AIN0_PORT PORTADC ++#define AIN0_PIN PINADC ++#define AIN0_BIT ADC5 ++ ++#define PCINT6_DDR DDRADC ++#define PCINT6_PORT PORTADC ++#define PCINT6_PIN PINADC ++#define PCINT6_BIT ADC5 ++ ++#define PA6_DDR DDRADC ++#define PA6_PORT PORTADC ++#define PA6_PIN PINADC ++#define PA6_BIT ADC5 ++ ++#define AIN2_DDR DDRADC ++#define AIN2_PORT PORTADC ++#define AIN2_PIN PINADC ++#define AIN2_BIT ADC4 ++ ++#define PCINT5_DDR DDRADC ++#define PCINT5_PORT PORTADC ++#define PCINT5_PIN PINADC ++#define PCINT5_BIT ADC4 ++ ++#define PA5_DDR DDRADC ++#define PA5_PORT PORTADC ++#define PA5_PIN PINADC ++#define PA5_BIT ADC4 ++ ++#define ICP0_DDR DDRADC ++#define ICP0_PORT PORTADC ++#define ICP0_PIN PINADC ++#define ICP0_BIT ADC3 ++ ++#define PCINT4_DDR DDRADC ++#define PCINT4_PORT PORTADC ++#define PCINT4_PIN PINADC ++#define PCINT4_BIT ADC3 ++ ++#define PA4_DDR DDRADC ++#define PA4_PORT PORTADC ++#define PA4_PIN PINADC ++#define PA4_BIT ADC3 ++ ++#define PCINT3_DDR DDRAREF ++#define PCINT3_PORT PORTAREF ++#define PCINT3_PIN PINAREF ++#define PCINT3_BIT AREF ++ ++#define PA3_DDR DDRAREF ++#define PA3_PORT PORTAREF ++#define PA3_PIN PINAREF ++#define PA3_BIT AREF ++ ++#define INT1_DDR DDRADC ++#define INT1_PORT PORTADC ++#define INT1_PIN PINADC ++#define INT1_BIT ADC2 ++ ++#define USCK_A_DDR DDRADC ++#define USCK_A_PORT PORTADC ++#define USCK_A_PIN PINADC ++#define USCK_A_BIT ADC2 ++ ++#define SCL_A_DDR DDRADC ++#define SCL_A_PORT PORTADC ++#define SCL_A_PIN PINADC ++#define SCL_A_BIT ADC2 ++ ++#define PCINT2_DDR DDRADC ++#define PCINT2_PORT PORTADC ++#define PCINT2_PIN PINADC ++#define PCINT2_BIT ADC2 ++ ++#define PA2_DDR DDRADC ++#define PA2_PORT PORTADC ++#define PA2_PIN PINADC ++#define PA2_BIT ADC2 ++ ++#define DO_A_DDR DDRADC ++#define DO_A_PORT PORTADC ++#define DO_A_PIN PINADC ++#define DO_A_BIT ADC1 ++ ++#define PCINT1_DDR DDRADC ++#define PCINT1_PORT PORTADC ++#define PCINT1_PIN PINADC ++#define PCINT1_BIT ADC1 ++ ++#define PA1_DDR DDRADC ++#define PA1_PORT PORTADC ++#define PA1_PIN PINADC ++#define PA1_BIT ADC1 ++ ++#define DI_A_DDR DDRADC ++#define DI_A_PORT PORTADC ++#define DI_A_PIN PINADC ++#define DI_A_BIT ADC0 ++ ++#define SDA_A_DDR DDRADC ++#define SDA_A_PORT PORTADC ++#define SDA_A_PIN PINADC ++#define SDA_A_BIT ADC0 ++ ++#define PCINT0_DDR DDRADC ++#define PCINT0_PORT PORTADC ++#define PCINT0_PIN PINADC ++#define PCINT0_BIT ADC0 ++ ++#define PA0_DDR DDRADC ++#define PA0_PORT PORTADC ++#define PA0_PIN PINADC ++#define PA0_BIT ADC0 ++ ++#endif /* _AVR_ATtiny861A_H_ */ ++ +diff --git a/include/avr/iotn87.h b/include/avr/iotn87.h +index 7681ec8..1d14d59 100644 +--- a/include/avr/iotn87.h ++++ b/include/avr/iotn87.h +@@ -1,847 +1,847 @@ +-/* Copyright (c) 2009-2010 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn87.h 2181 2010-08-23 03:46:23Z arcanum $ */ +- +-/* avr/iotn87.h - definitions for ATtiny87 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn87.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATtiny87_H_ +-#define _AVR_ATtiny87_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINA _SFR_IO8(0x00) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +-#define PINA4 4 +-#define PINA5 5 +-#define PINA6 6 +-#define PINA7 7 +- +-#define DDRA _SFR_IO8(0x01) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +-#define DDA4 4 +-#define DDA5 5 +-#define DDA6 6 +-#define DDA7 7 +- +-#define PORTA _SFR_IO8(0x02) +-#define PORTA0 0 +-#define PORTA1 1 +-#define PORTA2 2 +-#define PORTA3 3 +-#define PORTA4 4 +-#define PORTA5 5 +-#define PORTA6 6 +-#define PORTA7 7 +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PORTCR _SFR_IO8(0x12) +-#define PUDA 0 +-#define PUDB 2 +-#define BBMA 4 +-#define BBMB 5 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +-#define PCIF1 1 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEAR _SFR_IO16(0x21) +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define EEARH _SFR_IO8(0x22) +-#define EEAR8 0 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSR1 0 +-#define PSR0 1 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x25) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define TCCR0B _SFR_IO8(0x26) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define FOC0A 7 +- +-#define TCNT0 _SFR_IO8(0x27) +-#define TCNT00 0 +-#define TCNT01 1 +-#define TCNT02 2 +-#define TCNT03 3 +-#define TCNT04 4 +-#define TCNT05 5 +-#define TCNT06 6 +-#define TCNT07 7 +- +-#define OCR0A _SFR_IO8(0x28) +-#define OCR00 0 +-#define OCR01 1 +-#define OCR02 2 +-#define OCR03 3 +-#define OCR04 4 +-#define OCR05 5 +-#define OCR06 6 +-#define OCR07 7 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACIRS 6 +-#define ACD 7 +- +-#define DWDR _SFR_IO8(0x31) +-#define DWDR0 0 +-#define DWDR1 1 +-#define DWDR2 2 +-#define DWDR3 3 +-#define DWDR4 4 +-#define DWDR5 5 +-#define DWDR6 6 +-#define DWDR7 7 +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x35) +-#define PUD 4 +-#define BODSE 5 +-#define BODS 6 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define RFLB 3 +-#define CTPB 4 +-#define SIGRD 5 +-#define RWWSB 6 +- +-#define WDTCR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define CLKCSR _SFR_MEM8(0x62) +-#define CLKC0 0 +-#define CLKC1 1 +-#define CLKC2 2 +-#define CLKC3 3 +-#define CLKRDY 4 +-#define CLKCCE 7 +- +-#define CLKSELR _SFR_MEM8(0x63) +-#define CSEL0 0 +-#define CSEL1 1 +-#define CSEL2 2 +-#define CSEL3 3 +-#define CSUT0 4 +-#define CSUT1 5 +-#define COUT 6 +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRUSI 1 +-#define PRTIM0 2 +-#define PRTIM1 3 +-#define PRSPI 4 +-#define PRLIN 5 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +-#define PCIE1 1 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#define AMISCR _SFR_MEM8(0x77) +-#define ISRCEN 0 +-#define XREFEN 1 +-#define AREFEN 2 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +- +-#define ADCL _SFR_MEM8(0x78) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_MEM8(0x79) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ACIR0 4 +-#define ACIR1 5 +-#define ACME 6 +-#define BIN 7 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define ADC8D 0 +-#define ADC9D 1 +-#define ADC10D 2 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCCR1D _SFR_MEM8(0x83) +-#define OC1AU 0 +-#define OC1AV 1 +-#define OC1AW 2 +-#define OC1AX 3 +-#define OC1BU 4 +-#define OC1BV 5 +-#define OC1BW 6 +-#define OC1BX 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define ASSR _SFR_MEM8(0xB6) +-#define TCR0BUB 0 +-#define TCR0AUB 1 +-#define OCR0AUB 3 +-#define TCN0UB 4 +-#define AS0 5 +-#define EXCLK 6 +- +-#define USICR _SFR_MEM8(0xB8) +-#define USITC 0 +-#define USICLK 1 +-#define USICS0 2 +-#define USICS1 3 +-#define USIWM0 4 +-#define USIWM1 5 +-#define USIOIE 6 +-#define USISIE 7 +- +-#define USISR _SFR_MEM8(0xB9) +-#define USICNT0 0 +-#define USICNT1 1 +-#define USICNT2 2 +-#define USICNT3 3 +-#define USIDC 4 +-#define USIPF 5 +-#define USIOIF 6 +-#define USISIF 7 +- +-#define USIDR _SFR_MEM8(0xBA) +-#define USIDR0 0 +-#define USIDR1 1 +-#define USIDR2 2 +-#define USIDR3 3 +-#define USIDR4 4 +-#define USIDR5 5 +-#define USIDR6 6 +-#define USIDR7 7 +- +-#define USIBR _SFR_MEM8(0xBB) +-#define USIBR0 0 +-#define USIBR1 1 +-#define USIBR2 2 +-#define USIBR3 3 +-#define USIBR4 4 +-#define USIBR5 5 +-#define USIBR6 6 +-#define USIBR7 7 +- +-#define USIPP _SFR_MEM8(0xBC) +-#define USIPOS 0 +- +-#define LINCR _SFR_MEM8(0xC8) +-#define LCMD0 0 +-#define LCMD1 1 +-#define LCMD2 2 +-#define LENA 3 +-#define LCONF0 4 +-#define LCONF1 5 +-#define LIN13 6 +-#define LSWRES 7 +- +-#define LINSIR _SFR_MEM8(0xC9) +-#define LRXOK 0 +-#define LTXOK 1 +-#define LIDOK 2 +-#define LERR 3 +-#define LBUSY 4 +-#define LIDST0 5 +-#define LIDST1 6 +-#define LIDST2 7 +- +-#define LINENIR _SFR_MEM8(0xCA) +-#define LENRXOK 0 +-#define LENTXOK 1 +-#define LENIDOK 2 +-#define LENERR 3 +- +-#define LINERR _SFR_MEM8(0xCB) +-#define LBERR 0 +-#define LCERR 1 +-#define LPERR 2 +-#define LSERR 3 +-#define LFERR 4 +-#define LOVERR 5 +-#define LTOERR 6 +-#define LABORT 7 +- +-#define LINBTR _SFR_MEM8(0xCC) +-#define LBT0 0 +-#define LBT1 1 +-#define LBT2 2 +-#define LBT3 3 +-#define LBT4 4 +-#define LBT5 5 +-#define LDISR 7 +- +-#define LINBRR _SFR_MEM16(0xCD) +- +-#define LINBRRL _SFR_MEM8(0xCD) +-#define LDIV0 0 +-#define LDIV1 1 +-#define LDIV2 2 +-#define LDIV3 3 +-#define LDIV4 4 +-#define LDIV5 5 +-#define LDIV6 6 +-#define LDIV7 7 +- +-#define LINBRRH _SFR_MEM8(0xCE) +-#define LDIV8 0 +-#define LDIV9 1 +-#define LDIV10 2 +-#define LDIV11 3 +- +-#define LINDLR _SFR_MEM8(0xCF) +-#define LRXDL0 0 +-#define LRXDL1 1 +-#define LRXDL2 2 +-#define LRXDL3 3 +-#define LTXDL0 4 +-#define LTXDL1 5 +-#define LTXDL2 6 +-#define LTXDL3 7 +- +-#define LINIDR _SFR_MEM8(0xD0) +-#define LID0 0 +-#define LID1 1 +-#define LID2 2 +-#define LID3 3 +-#define LID4 4 +-#define LID5 5 +-#define LP0 6 +-#define LP1 7 +- +-#define LINSEL _SFR_MEM8(0xD1) +-#define LINDX0 0 +-#define LINDX1 1 +-#define LINDX2 2 +-#define LAINC 3 +- +-#define LINDAT _SFR_MEM8(0xD2) +-#define LDATA0 0 +-#define LDATA1 1 +-#define LDATA2 2 +-#define LDATA3 3 +-#define LDATA4 4 +-#define LDATA5 5 +-#define LDATA6 6 +-#define LDATA7 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +-#define USI_OVF_vect_num 19 +-#define USI_OVF_vect _VECTOR(19) /* USI Overflow */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ +-#define PCINT0_vect_num 3 +-#define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ +-#define PCINT1_vect_num 4 +-#define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 1 */ +-#define WDT_vect_num 5 +-#define WDT_vect _VECTOR(5) /* Watchdog Time-Out Interrupt */ +-#define TIMER1_CAPT_vect_num 6 +-#define TIMER1_CAPT_vect _VECTOR(6) /* Timer/Counter1 Capture Event */ +-#define TIMER1_COMPA_vect_num 7 +-#define TIMER1_COMPA_vect _VECTOR(7) /* Timer/Counter1 Compare Match 1A */ +-#define TIMER1_COMPB_vect_num 8 +-#define TIMER1_COMPB_vect _VECTOR(8) /* Timer/Counter1 Compare Match 1B */ +-#define TIMER1_OVF_vect_num 9 +-#define TIMER1_OVF_vect _VECTOR(9) /* Timer/Counter1 Overflow */ +-#define TIMER0_COMPA_vect_num 10 +-#define TIMER0_COMPA_vect _VECTOR(10) /* Timer/Counter0 Compare Match 0A */ +-#define TIMER0_OVF_vect_num 11 +-#define TIMER0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ +-#define LIN_TC_vect_num 12 +-#define LIN_TC_vect _VECTOR(12) /* LIN Transfer Complete */ +-#define LIN_ERR_vect_num 13 +-#define LIN_ERR_vect _VECTOR(13) /* LIN Error */ +-#define SPI_STC_vect_num 14 +-#define SPI_STC_vect _VECTOR(14) /* SPI Serial Transfer Complete */ +-#define ADC_vect_num 15 +-#define ADC_vect _VECTOR(15) /* ADC Conversion Complete */ +-#define EE_RDY_vect_num 16 +-#define EE_RDY_vect _VECTOR(16) /* EEPROM Ready */ +-#define ANA_COMP_vect_num 17 +-#define ANA_COMP_vect _VECTOR(17) /* Analog Comparator */ +-#define USI_START_vect_num 18 +-#define USI_START_vect _VECTOR(18) /* USI Start */ +- +-#define _VECTOR_SIZE 2 /* Size of individual vector. */ +-#define _VECTORS_SIZE (20 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (128) +-#define RAMSTART (0x0100) +-#define RAMSIZE (512) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x1FF) +-#define E2PAGESIZE (4) +-#define FLASHEND (0x1FFF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always ON */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x93 +-#define SIGNATURE_2 0x87 +- +- +-#endif /* _AVR_ATtiny87_H_ */ +- ++/* Copyright (c) 2009-2010 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn87.h 2181 2010-08-23 03:46:23Z arcanum $ */ ++ ++/* avr/iotn87.h - definitions for ATtiny87 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn87.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATtiny87_H_ ++#define _AVR_ATtiny87_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINA _SFR_IO8(0x00) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++#define PINA4 4 ++#define PINA5 5 ++#define PINA6 6 ++#define PINA7 7 ++ ++#define DDRA _SFR_IO8(0x01) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++#define DDA4 4 ++#define DDA5 5 ++#define DDA6 6 ++#define DDA7 7 ++ ++#define PORTA _SFR_IO8(0x02) ++#define PORTA0 0 ++#define PORTA1 1 ++#define PORTA2 2 ++#define PORTA3 3 ++#define PORTA4 4 ++#define PORTA5 5 ++#define PORTA6 6 ++#define PORTA7 7 ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PORTCR _SFR_IO8(0x12) ++#define PUDA 0 ++#define PUDB 2 ++#define BBMA 4 ++#define BBMB 5 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEAR _SFR_IO16(0x21) ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define EEARH _SFR_IO8(0x22) ++#define EEAR8 0 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSR1 0 ++#define PSR0 1 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x25) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define TCCR0B _SFR_IO8(0x26) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define FOC0A 7 ++ ++#define TCNT0 _SFR_IO8(0x27) ++#define TCNT00 0 ++#define TCNT01 1 ++#define TCNT02 2 ++#define TCNT03 3 ++#define TCNT04 4 ++#define TCNT05 5 ++#define TCNT06 6 ++#define TCNT07 7 ++ ++#define OCR0A _SFR_IO8(0x28) ++#define OCR00 0 ++#define OCR01 1 ++#define OCR02 2 ++#define OCR03 3 ++#define OCR04 4 ++#define OCR05 5 ++#define OCR06 6 ++#define OCR07 7 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACIRS 6 ++#define ACD 7 ++ ++#define DWDR _SFR_IO8(0x31) ++#define DWDR0 0 ++#define DWDR1 1 ++#define DWDR2 2 ++#define DWDR3 3 ++#define DWDR4 4 ++#define DWDR5 5 ++#define DWDR6 6 ++#define DWDR7 7 ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define RFLB 3 ++#define CTPB 4 ++#define SIGRD 5 ++#define RWWSB 6 ++ ++#define WDTCR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define CLKCSR _SFR_MEM8(0x62) ++#define CLKC0 0 ++#define CLKC1 1 ++#define CLKC2 2 ++#define CLKC3 3 ++#define CLKRDY 4 ++#define CLKCCE 7 ++ ++#define CLKSELR _SFR_MEM8(0x63) ++#define CSEL0 0 ++#define CSEL1 1 ++#define CSEL2 2 ++#define CSEL3 3 ++#define CSUT0 4 ++#define CSUT1 5 ++#define COUT 6 ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRUSI 1 ++#define PRTIM0 2 ++#define PRTIM1 3 ++#define PRSPI 4 ++#define PRLIN 5 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#define AMISCR _SFR_MEM8(0x77) ++#define ISRCEN 0 ++#define XREFEN 1 ++#define AREFEN 2 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_MEM8(0x79) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACIR0 4 ++#define ACIR1 5 ++#define ACME 6 ++#define BIN 7 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define ADC8D 4 ++#define ADC9D 5 ++#define ADC10D 6 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCCR1D _SFR_MEM8(0x83) ++#define OC1AU 0 ++#define OC1AV 1 ++#define OC1AW 2 ++#define OC1AX 3 ++#define OC1BU 4 ++#define OC1BV 5 ++#define OC1BW 6 ++#define OC1BX 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define TCR0BUB 0 ++#define TCR0AUB 1 ++#define OCR0AUB 3 ++#define TCN0UB 4 ++#define AS0 5 ++#define EXCLK 6 ++ ++#define USICR _SFR_MEM8(0xB8) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_MEM8(0xB9) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_MEM8(0xBA) ++#define USIDR0 0 ++#define USIDR1 1 ++#define USIDR2 2 ++#define USIDR3 3 ++#define USIDR4 4 ++#define USIDR5 5 ++#define USIDR6 6 ++#define USIDR7 7 ++ ++#define USIBR _SFR_MEM8(0xBB) ++#define USIBR0 0 ++#define USIBR1 1 ++#define USIBR2 2 ++#define USIBR3 3 ++#define USIBR4 4 ++#define USIBR5 5 ++#define USIBR6 6 ++#define USIBR7 7 ++ ++#define USIPP _SFR_MEM8(0xBC) ++#define USIPOS 0 ++ ++#define LINCR _SFR_MEM8(0xC8) ++#define LCMD0 0 ++#define LCMD1 1 ++#define LCMD2 2 ++#define LENA 3 ++#define LCONF0 4 ++#define LCONF1 5 ++#define LIN13 6 ++#define LSWRES 7 ++ ++#define LINSIR _SFR_MEM8(0xC9) ++#define LRXOK 0 ++#define LTXOK 1 ++#define LIDOK 2 ++#define LERR 3 ++#define LBUSY 4 ++#define LIDST0 5 ++#define LIDST1 6 ++#define LIDST2 7 ++ ++#define LINENIR _SFR_MEM8(0xCA) ++#define LENRXOK 0 ++#define LENTXOK 1 ++#define LENIDOK 2 ++#define LENERR 3 ++ ++#define LINERR _SFR_MEM8(0xCB) ++#define LBERR 0 ++#define LCERR 1 ++#define LPERR 2 ++#define LSERR 3 ++#define LFERR 4 ++#define LOVERR 5 ++#define LTOERR 6 ++#define LABORT 7 ++ ++#define LINBTR _SFR_MEM8(0xCC) ++#define LBT0 0 ++#define LBT1 1 ++#define LBT2 2 ++#define LBT3 3 ++#define LBT4 4 ++#define LBT5 5 ++#define LDISR 7 ++ ++#define LINBRR _SFR_MEM16(0xCD) ++ ++#define LINBRRL _SFR_MEM8(0xCD) ++#define LDIV0 0 ++#define LDIV1 1 ++#define LDIV2 2 ++#define LDIV3 3 ++#define LDIV4 4 ++#define LDIV5 5 ++#define LDIV6 6 ++#define LDIV7 7 ++ ++#define LINBRRH _SFR_MEM8(0xCE) ++#define LDIV8 0 ++#define LDIV9 1 ++#define LDIV10 2 ++#define LDIV11 3 ++ ++#define LINDLR _SFR_MEM8(0xCF) ++#define LRXDL0 0 ++#define LRXDL1 1 ++#define LRXDL2 2 ++#define LRXDL3 3 ++#define LTXDL0 4 ++#define LTXDL1 5 ++#define LTXDL2 6 ++#define LTXDL3 7 ++ ++#define LINIDR _SFR_MEM8(0xD0) ++#define LID0 0 ++#define LID1 1 ++#define LID2 2 ++#define LID3 3 ++#define LID4 4 ++#define LID5 5 ++#define LP0 6 ++#define LP1 7 ++ ++#define LINSEL _SFR_MEM8(0xD1) ++#define LINDX0 0 ++#define LINDX1 1 ++#define LINDX2 2 ++#define LAINC 3 ++ ++#define LINDAT _SFR_MEM8(0xD2) ++#define LDATA0 0 ++#define LDATA1 1 ++#define LDATA2 2 ++#define LDATA3 3 ++#define LDATA4 4 ++#define LDATA5 5 ++#define LDATA6 6 ++#define LDATA7 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++#define USI_OVF_vect_num 19 ++#define USI_OVF_vect _VECTOR(19) /* USI Overflow */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) /* External Interrupt Request 1 */ ++#define PCINT0_vect_num 3 ++#define PCINT0_vect _VECTOR(3) /* Pin Change Interrupt Request 0 */ ++#define PCINT1_vect_num 4 ++#define PCINT1_vect _VECTOR(4) /* Pin Change Interrupt Request 1 */ ++#define WDT_vect_num 5 ++#define WDT_vect _VECTOR(5) /* Watchdog Time-Out Interrupt */ ++#define TIMER1_CAPT_vect_num 6 ++#define TIMER1_CAPT_vect _VECTOR(6) /* Timer/Counter1 Capture Event */ ++#define TIMER1_COMPA_vect_num 7 ++#define TIMER1_COMPA_vect _VECTOR(7) /* Timer/Counter1 Compare Match 1A */ ++#define TIMER1_COMPB_vect_num 8 ++#define TIMER1_COMPB_vect _VECTOR(8) /* Timer/Counter1 Compare Match 1B */ ++#define TIMER1_OVF_vect_num 9 ++#define TIMER1_OVF_vect _VECTOR(9) /* Timer/Counter1 Overflow */ ++#define TIMER0_COMPA_vect_num 10 ++#define TIMER0_COMPA_vect _VECTOR(10) /* Timer/Counter0 Compare Match 0A */ ++#define TIMER0_OVF_vect_num 11 ++#define TIMER0_OVF_vect _VECTOR(11) /* Timer/Counter0 Overflow */ ++#define LIN_TC_vect_num 12 ++#define LIN_TC_vect _VECTOR(12) /* LIN Transfer Complete */ ++#define LIN_ERR_vect_num 13 ++#define LIN_ERR_vect _VECTOR(13) /* LIN Error */ ++#define SPI_STC_vect_num 14 ++#define SPI_STC_vect _VECTOR(14) /* SPI Serial Transfer Complete */ ++#define ADC_vect_num 15 ++#define ADC_vect _VECTOR(15) /* ADC Conversion Complete */ ++#define EE_RDY_vect_num 16 ++#define EE_RDY_vect _VECTOR(16) /* EEPROM Ready */ ++#define ANA_COMP_vect_num 17 ++#define ANA_COMP_vect _VECTOR(17) /* Analog Comparator */ ++#define USI_START_vect_num 18 ++#define USI_START_vect _VECTOR(18) /* USI Start */ ++ ++#define _VECTOR_SIZE 2 /* Size of individual vector. */ ++#define _VECTORS_SIZE (20 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (128) ++#define RAMSTART (0x0100) ++#define RAMSIZE (512) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x1FF) ++#define E2PAGESIZE (4) ++#define FLASHEND (0x1FFF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock Output Enable */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through the Chip Erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer always ON */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial Program and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* DebugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External Reset disable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN (unsigned char)~_BV(0) /* Self-Programming Enable */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x87 ++ ++ ++#endif /* _AVR_ATtiny87_H_ */ ++ +diff --git a/include/avr/iotn88.h b/include/avr/iotn88.h +index 8213a53..55e4148 100644 +--- a/include/avr/iotn88.h ++++ b/include/avr/iotn88.h +@@ -1,795 +1,795 @@ +-/* Copyright (c) 2007 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. +-*/ +- +-/* $Id: iotn88.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* avr/iotn88.h - definitions for ATtiny88 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn88.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_IOTN88_H_ +-#define _AVR_IOTN88_H_ 1 +- +-/* Registers and associated bit numbers */ +- +-#define PINB _SFR_IO8(0x03) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x05) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +-#define PORTB4 4 +-#define PORTB5 5 +-#define PORTB6 6 +-#define PORTB7 7 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC0 0 +-#define PINC1 1 +-#define PINC2 2 +-#define PINC3 3 +-#define PINC4 4 +-#define PINC5 5 +-#define PINC6 6 +-#define PINC7 7 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC0 0 +-#define DDC1 1 +-#define DDC2 2 +-#define DDC3 3 +-#define DDC4 4 +-#define DDC5 5 +-#define DDC6 6 +-#define DDC7 7 +- +-#define PORTC _SFR_IO8(0x08) +-#define PORTC0 0 +-#define PORTC1 1 +-#define PORTC2 2 +-#define PORTC3 3 +-#define PORTC4 4 +-#define PORTC5 5 +-#define PORTC6 6 +-#define PORTC7 7 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND0 0 +-#define PIND1 1 +-#define PIND2 2 +-#define PIND3 3 +-#define PIND4 4 +-#define PIND5 5 +-#define PIND6 6 +-#define PIND7 7 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD0 0 +-#define DDD1 1 +-#define DDD2 2 +-#define DDD3 3 +-#define DDD4 4 +-#define DDD5 5 +-#define DDD6 6 +-#define DDD7 7 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PORTD0 0 +-#define PORTD1 1 +-#define PORTD2 2 +-#define PORTD3 3 +-#define PORTD4 4 +-#define PORTD5 5 +-#define PORTD6 6 +-#define PORTD7 7 +- +-#define PINA _SFR_IO8(0x0C) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +- +-#define DDRA _SFR_IO8(0x0D) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +- +-#define PORTA _SFR_IO8(0x0E) +-#define PORTA0 0 +-#define PORTA1 1 +-#define PORTA2 2 +-#define PORTA3 3 +- +-#define PORTCR _SFR_IO8(0x12) +-#define PUDA 0 +-#define PUDB 1 +-#define PUDC 2 +-#define PUDD 3 +-#define BBMA 4 +-#define BBMB 5 +-#define BBMC 6 +-#define BBMD 7 +- +-#define TIFR0 _SFR_IO8(0x15) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define TOV1 0 +-#define OCF1A 1 +-#define OCF1B 2 +-#define ICF1 5 +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +-#define PCIF1 1 +-#define PCIF2 2 +-#define PCIF3 3 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF0 0 +-#define INTF1 1 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT0 0 +-#define INT1 1 +- +-#define GPIOR0 _SFR_IO8(0x1E) +-#define GPIOR00 0 +-#define GPIOR01 1 +-#define GPIOR02 2 +-#define GPIOR03 3 +-#define GPIOR04 4 +-#define GPIOR05 5 +-#define GPIOR06 6 +-#define GPIOR07 7 +- +-#define EECR _SFR_IO8(0x1F) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-#define EEDR _SFR_IO8(0x20) +-#define EEDR0 0 +-#define EEDR1 1 +-#define EEDR2 2 +-#define EEDR3 3 +-#define EEDR4 4 +-#define EEDR5 5 +-#define EEDR6 6 +-#define EEDR7 7 +- +-#define EEARL _SFR_IO8(0x21) +-#define EEAR0 0 +-#define EEAR1 1 +-#define EEAR2 2 +-#define EEAR3 3 +-#define EEAR4 4 +-#define EEAR5 5 +-#define EEAR6 6 +-#define EEAR7 7 +- +-#define GTCCR _SFR_IO8(0x23) +-#define PSRSYNC 0 +-#define TSM 7 +- +-#define TCCR0A _SFR_IO8(0x25) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define CTC0 3 +- +-#define TCNT0 _SFR_IO8(0x26) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define OCR0A _SFR_IO8(0x27) +-#define OCR0A_0 0 +-#define OCR0A_1 1 +-#define OCR0A_2 2 +-#define OCR0A_3 3 +-#define OCR0A_4 4 +-#define OCR0A_5 5 +-#define OCR0A_6 6 +-#define OCR0A_7 7 +- +-#define OCR0B _SFR_IO8(0x28) +-#define OCR0B_0 0 +-#define OCR0B_1 1 +-#define OCR0B_2 2 +-#define OCR0B_3 3 +-#define OCR0B_4 4 +-#define OCR0B_5 5 +-#define OCR0B_6 6 +-#define OCR0B_7 7 +- +-#define GPIOR1 _SFR_IO8(0x2A) +-#define GPIOR10 0 +-#define GPIOR11 1 +-#define GPIOR12 2 +-#define GPIOR13 3 +-#define GPIOR14 4 +-#define GPIOR15 5 +-#define GPIOR16 6 +-#define GPIOR17 7 +- +-#define GPIOR2 _SFR_IO8(0x2B) +-#define GPIOR20 0 +-#define GPIOR21 1 +-#define GPIOR22 2 +-#define GPIOR23 3 +-#define GPIOR24 4 +-#define GPIOR25 5 +-#define GPIOR26 6 +-#define GPIOR27 7 +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPR0 0 +-#define SPR1 1 +-#define CPHA 2 +-#define CPOL 3 +-#define MSTR 4 +-#define DORD 5 +-#define SPE 6 +-#define SPIE 7 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPI2X 0 +-#define WCOL 6 +-#define SPIF 7 +- +-#define SPDR _SFR_IO8(0x2E) +-#define SPDR0 0 +-#define SPDR1 1 +-#define SPDR2 2 +-#define SPDR3 3 +-#define SPDR4 4 +-#define SPDR5 5 +-#define SPDR6 6 +-#define SPDR7 7 +- +-#define ACSR _SFR_IO8(0x30) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define SMCR _SFR_IO8(0x33) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x35) +-#define PUD 4 +-#define BODSE 5 +-#define BODS 6 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SELFPRGEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define RFLB 3 +-#define CTPB 4 +-#define RWWSB 6 +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define PRR _SFR_MEM8(0x64) +-#define PRADC 0 +-#define PRSPI 2 +-#define PRTIM1 3 +-#define PRTIM0 5 +-#define PRTWI 7 +- +-#define OSCCAL _SFR_MEM8(0x66) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +-#define PCIE1 1 +-#define PCIE2 2 +-#define PCIE3 3 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC00 0 +-#define ISC01 1 +-#define ISC10 2 +-#define ISC11 3 +- +-#define PCMSK3 _SFR_MEM8(0x6A) +-#define PCINT24 0 +-#define PCINT25 1 +-#define PCINT26 2 +-#define PCINT27 3 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-#define PCMSK2 _SFR_MEM8(0x6D) +-#define PCINT16 0 +-#define PCINT17 1 +-#define PCINT18 2 +-#define PCINT19 3 +-#define PCINT20 4 +-#define PCINT21 5 +-#define PCINT22 6 +-#define PCINT23 7 +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define TOIE1 0 +-#define OCIE1A 1 +-#define OCIE1B 2 +-#define ICIE1 5 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +- +-#define ADCL _SFR_MEM8(0x78) +-#define ADCL0 0 +-#define ADCL1 1 +-#define ADCL2 2 +-#define ADCL3 3 +-#define ADCL4 4 +-#define ADCL5 5 +-#define ADCL6 6 +-#define ADCL7 7 +- +-#define ADCH _SFR_MEM8(0x79) +-#define ADCH0 0 +-#define ADCH1 1 +-#define ADCH2 2 +-#define ADCH3 3 +-#define ADCH4 4 +-#define ADCH5 5 +-#define ADCH6 6 +-#define ADCH7 7 +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define ACME 6 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define ADLAR 5 +-#define REFS0 6 +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define ADC3D 3 +-#define ADC4D 4 +-#define ADC5D 5 +-#define ADC6D 6 +-#define ADC7D 7 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define WGM10 0 +-#define WGM11 1 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define WGM12 3 +-#define WGM13 4 +-#define ICES1 6 +-#define ICNC1 7 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1B 6 +-#define FOC1A 7 +- +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1L0 0 +-#define TCNT1L1 1 +-#define TCNT1L2 2 +-#define TCNT1L3 3 +-#define TCNT1L4 4 +-#define TCNT1L5 5 +-#define TCNT1L6 6 +-#define TCNT1L7 7 +- +-#define TCNT1H _SFR_MEM8(0x85) +-#define TCNT1H0 0 +-#define TCNT1H1 1 +-#define TCNT1H2 2 +-#define TCNT1H3 3 +-#define TCNT1H4 4 +-#define TCNT1H5 5 +-#define TCNT1H6 6 +-#define TCNT1H7 7 +- +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1L0 0 +-#define ICR1L1 1 +-#define ICR1L2 2 +-#define ICR1L3 3 +-#define ICR1L4 4 +-#define ICR1L5 5 +-#define ICR1L6 6 +-#define ICR1L7 7 +- +-#define ICR1H _SFR_MEM8(0x87) +-#define ICR1H0 0 +-#define ICR1H1 1 +-#define ICR1H2 2 +-#define ICR1H3 3 +-#define ICR1H4 4 +-#define ICR1H5 5 +-#define ICR1H6 6 +-#define ICR1H7 7 +- +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AL0 0 +-#define OCR1AL1 1 +-#define OCR1AL2 2 +-#define OCR1AL3 3 +-#define OCR1AL4 4 +-#define OCR1AL5 5 +-#define OCR1AL6 6 +-#define OCR1AL7 7 +- +-#define OCR1AH _SFR_MEM8(0x89) +-#define OCR1AH0 0 +-#define OCR1AH1 1 +-#define OCR1AH2 2 +-#define OCR1AH3 3 +-#define OCR1AH4 4 +-#define OCR1AH5 5 +-#define OCR1AH6 6 +-#define OCR1AH7 7 +- +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BL0 0 +-#define OCR1BL1 1 +-#define OCR1BL2 2 +-#define OCR1BL3 3 +-#define OCR1BL4 4 +-#define OCR1BL5 5 +-#define OCR1BL6 6 +-#define OCR1BL7 7 +- +-#define OCR1BH _SFR_MEM8(0x8B) +-#define OCR1BH0 0 +-#define OCR1BH1 1 +-#define OCR1BH2 2 +-#define OCR1BH3 3 +-#define OCR1BH4 4 +-#define OCR1BH5 5 +-#define OCR1BH6 6 +-#define OCR1BH7 7 +- +-#define TWBR _SFR_MEM8(0xB8) +-#define TWBR0 0 +-#define TWBR1 1 +-#define TWBR2 2 +-#define TWBR3 3 +-#define TWBR4 4 +-#define TWBR5 5 +-#define TWBR6 6 +-#define TWBR7 7 +- +-#define TWSR _SFR_MEM8(0xB9) +-#define TWPS0 0 +-#define TWPS1 1 +-#define TWS3 3 +-#define TWS4 4 +-#define TWS5 5 +-#define TWS6 6 +-#define TWS7 7 +- +-#define TWAR _SFR_MEM8(0xBA) +-#define TWGCE 0 +-#define TWA0 1 +-#define TWA1 2 +-#define TWA2 3 +-#define TWA3 4 +-#define TWA4 5 +-#define TWA5 6 +-#define TWA6 7 +- +-#define TWDR _SFR_MEM8(0xBB) +-#define TWD0 0 +-#define TWD1 1 +-#define TWD2 2 +-#define TWD3 3 +-#define TWD4 4 +-#define TWD5 5 +-#define TWD6 6 +-#define TWD7 7 +- +-#define TWCR _SFR_MEM8(0xBC) +-#define TWIE 0 +-#define TWEN 2 +-#define TWWC 3 +-#define TWSTO 4 +-#define TWSTA 5 +-#define TWEA 6 +-#define TWINT 7 +- +-#define TWAMR _SFR_MEM8(0xBD) +-#define TWAM0 1 +-#define TWAM1 2 +-#define TWAM2 3 +-#define TWAM3 4 +-#define TWAM4 5 +-#define TWAM5 6 +-#define TWAM6 7 +- +-#define TWHSR _SFR_MEM8(0xBE) +-#define TWIHS 0 +- +- +- +-/* Interrupt Vectors */ +-/* Interrupt vector 0 is the reset vector. */ +- +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +- +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +- +-#define PCINT0_vect_num 3 +-#define PCINT0_vect _VECTOR(3) +- +-#define PCINT1_vect_num 4 +-#define PCINT1_vect _VECTOR(4) +- +-#define PCINT2_vect_num 5 +-#define PCINT2_vect _VECTOR(5) +- +-#define PCINT3_vect_num 6 +-#define PCINT3_vect _VECTOR(6) +- +-#define WDT_vect_num 7 +-#define WDT_vect _VECTOR(7) +- +-#define TIMER1_CAPT_vect_num 8 +-#define TIMER1_CAPT_vect _VECTOR(8) +- +-#define TIMER1_COMPA_vect_num 9 +-#define TIMER1_COMPA_vect _VECTOR(9) +- +-#define TIMER1_COMPB_vect_num 10 +-#define TIMER1_COMPB_vect _VECTOR(10) +- +-#define TIMER1_OVF_vect_num 11 +-#define TIMER1_OVF_vect _VECTOR(11) +- +-#define TIMER0_COMPA_vect_num 12 +-#define TIMER0_COMPA_vect _VECTOR(12) +- +-#define TIMER0_COMPB_vect_num 13 +-#define TIMER0_COMPB_vect _VECTOR(13) +- +-#define TIMER0_OVF_vect_num 14 +-#define TIMER0_OVF_vect _VECTOR(14) +- +-#define SPI_STC_vect_num 15 +-#define SPI_STC_vect _VECTOR(15) +- +-#define ADC_vect_num 16 +-#define ADC_vect _VECTOR(16) +- +-#define EE_READY_vect_num 17 +-#define EE_READY_vect _VECTOR(17) +- +-#define ANALOG_COMP_vect_num 18 +-#define ANALOG_COMP_vect _VECTOR(18) +- +-#define TWI_vect_num 19 +-#define TWI_vect _VECTOR(19) +- +-#define _VECTORS_SIZE 40 +- +- +-/* Constants */ +-#define RAMEND 0x2FF +-#define RAMSTART (0x100) +-#define XRAMSIZE 0 +-#define XRAMEND RAMEND +-#define E2END 0x3F +-#define E2PAGESIZE 4 +-#define FLASHEND 0x1FFF +-#define SPM_PAGESIZE 32 +- +- +-/* Fuse Information */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ +-#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ +-#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ +-#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ +-#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ +-#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ +-#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ +-#define HFUSE_DEFAULT (FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_SELFPRGEN ~_BV(0) /* Self Programming Enable */ +-#define EFUSE_DEFAULT (0xFF) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x93 +-#define SIGNATURE_2 0x11 +- +- +-#endif /* _AVR_IOTN88_H_ */ ++/* Copyright (c) 2007 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. ++*/ ++ ++/* $Id: iotn88.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* avr/iotn88.h - definitions for ATtiny88 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn88.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_IOTN88_H_ ++#define _AVR_IOTN88_H_ 1 ++ ++/* Registers and associated bit numbers */ ++ ++#define PINB _SFR_IO8(0x03) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++#define PORTB4 4 ++#define PORTB5 5 ++#define PORTB6 6 ++#define PORTB7 7 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC0 0 ++#define PINC1 1 ++#define PINC2 2 ++#define PINC3 3 ++#define PINC4 4 ++#define PINC5 5 ++#define PINC6 6 ++#define PINC7 7 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC0 0 ++#define DDC1 1 ++#define DDC2 2 ++#define DDC3 3 ++#define DDC4 4 ++#define DDC5 5 ++#define DDC6 6 ++#define DDC7 7 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PORTC0 0 ++#define PORTC1 1 ++#define PORTC2 2 ++#define PORTC3 3 ++#define PORTC4 4 ++#define PORTC5 5 ++#define PORTC6 6 ++#define PORTC7 7 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND0 0 ++#define PIND1 1 ++#define PIND2 2 ++#define PIND3 3 ++#define PIND4 4 ++#define PIND5 5 ++#define PIND6 6 ++#define PIND7 7 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD0 0 ++#define DDD1 1 ++#define DDD2 2 ++#define DDD3 3 ++#define DDD4 4 ++#define DDD5 5 ++#define DDD6 6 ++#define DDD7 7 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PORTD0 0 ++#define PORTD1 1 ++#define PORTD2 2 ++#define PORTD3 3 ++#define PORTD4 4 ++#define PORTD5 5 ++#define PORTD6 6 ++#define PORTD7 7 ++ ++#define PINA _SFR_IO8(0x0C) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++ ++#define DDRA _SFR_IO8(0x0D) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++ ++#define PORTA _SFR_IO8(0x0E) ++#define PORTA0 0 ++#define PORTA1 1 ++#define PORTA2 2 ++#define PORTA3 3 ++ ++#define PORTCR _SFR_IO8(0x12) ++#define PUDA 0 ++#define PUDB 1 ++#define PUDC 2 ++#define PUDD 3 ++#define BBMA 4 ++#define BBMB 5 ++#define BBMC 6 ++#define BBMD 7 ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define TOV1 0 ++#define OCF1A 1 ++#define OCF1B 2 ++#define ICF1 5 ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++#define PCIF1 1 ++#define PCIF2 2 ++#define PCIF3 3 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF0 0 ++#define INTF1 1 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT0 0 ++#define INT1 1 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++#define GPIOR00 0 ++#define GPIOR01 1 ++#define GPIOR02 2 ++#define GPIOR03 3 ++#define GPIOR04 4 ++#define GPIOR05 5 ++#define GPIOR06 6 ++#define GPIOR07 7 ++ ++#define EECR _SFR_IO8(0x1F) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++#define EEDR _SFR_IO8(0x20) ++#define EEDR0 0 ++#define EEDR1 1 ++#define EEDR2 2 ++#define EEDR3 3 ++#define EEDR4 4 ++#define EEDR5 5 ++#define EEDR6 6 ++#define EEDR7 7 ++ ++#define EEARL _SFR_IO8(0x21) ++#define EEAR0 0 ++#define EEAR1 1 ++#define EEAR2 2 ++#define EEAR3 3 ++#define EEAR4 4 ++#define EEAR5 5 ++#define EEAR6 6 ++#define EEAR7 7 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define PSRSYNC 0 ++#define TSM 7 ++ ++#define TCCR0A _SFR_IO8(0x25) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define CTC0 3 ++ ++#define TCNT0 _SFR_IO8(0x26) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define OCR0A _SFR_IO8(0x27) ++#define OCR0A_0 0 ++#define OCR0A_1 1 ++#define OCR0A_2 2 ++#define OCR0A_3 3 ++#define OCR0A_4 4 ++#define OCR0A_5 5 ++#define OCR0A_6 6 ++#define OCR0A_7 7 ++ ++#define OCR0B _SFR_IO8(0x28) ++#define OCR0B_0 0 ++#define OCR0B_1 1 ++#define OCR0B_2 2 ++#define OCR0B_3 3 ++#define OCR0B_4 4 ++#define OCR0B_5 5 ++#define OCR0B_6 6 ++#define OCR0B_7 7 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++#define GPIOR10 0 ++#define GPIOR11 1 ++#define GPIOR12 2 ++#define GPIOR13 3 ++#define GPIOR14 4 ++#define GPIOR15 5 ++#define GPIOR16 6 ++#define GPIOR17 7 ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++#define GPIOR20 0 ++#define GPIOR21 1 ++#define GPIOR22 2 ++#define GPIOR23 3 ++#define GPIOR24 4 ++#define GPIOR25 5 ++#define GPIOR26 6 ++#define GPIOR27 7 ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPR0 0 ++#define SPR1 1 ++#define CPHA 2 ++#define CPOL 3 ++#define MSTR 4 ++#define DORD 5 ++#define SPE 6 ++#define SPIE 7 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPI2X 0 ++#define WCOL 6 ++#define SPIF 7 ++ ++#define SPDR _SFR_IO8(0x2E) ++#define SPDR0 0 ++#define SPDR1 1 ++#define SPDR2 2 ++#define SPDR3 3 ++#define SPDR4 4 ++#define SPDR5 5 ++#define SPDR6 6 ++#define SPDR7 7 ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define SMCR _SFR_IO8(0x33) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define PUD 4 ++#define BODSE 5 ++#define BODS 6 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SELFPRGEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define RFLB 3 ++#define CTPB 4 ++#define RWWSB 6 ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define PRR _SFR_MEM8(0x64) ++#define PRADC 0 ++#define PRSPI 2 ++#define PRTIM1 3 ++#define PRTIM0 5 ++#define PRTWI 7 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++#define PCIE1 1 ++#define PCIE2 2 ++#define PCIE3 3 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC00 0 ++#define ISC01 1 ++#define ISC10 2 ++#define ISC11 3 ++ ++#define PCMSK3 _SFR_MEM8(0x6A) ++#define PCINT24 0 ++#define PCINT25 1 ++#define PCINT26 2 ++#define PCINT27 3 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK2 _SFR_MEM8(0x6D) ++#define PCINT16 0 ++#define PCINT17 1 ++#define PCINT18 2 ++#define PCINT19 3 ++#define PCINT20 4 ++#define PCINT21 5 ++#define PCINT22 6 ++#define PCINT23 7 ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define TOIE1 0 ++#define OCIE1A 1 ++#define OCIE1B 2 ++#define ICIE1 5 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++ ++#define ADCL _SFR_MEM8(0x78) ++#define ADCL0 0 ++#define ADCL1 1 ++#define ADCL2 2 ++#define ADCL3 3 ++#define ADCL4 4 ++#define ADCL5 5 ++#define ADCL6 6 ++#define ADCL7 7 ++ ++#define ADCH _SFR_MEM8(0x79) ++#define ADCH0 0 ++#define ADCH1 1 ++#define ADCH2 2 ++#define ADCH3 3 ++#define ADCH4 4 ++#define ADCH5 5 ++#define ADCH6 6 ++#define ADCH7 7 ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define ACME 6 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define ADLAR 5 ++#define REFS0 6 ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define ADC3D 3 ++#define ADC4D 4 ++#define ADC5D 5 ++#define ADC6D 6 ++#define ADC7D 7 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define WGM10 0 ++#define WGM11 1 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define WGM12 3 ++#define WGM13 4 ++#define ICES1 6 ++#define ICNC1 7 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1B 6 ++#define FOC1A 7 ++ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1L0 0 ++#define TCNT1L1 1 ++#define TCNT1L2 2 ++#define TCNT1L3 3 ++#define TCNT1L4 4 ++#define TCNT1L5 5 ++#define TCNT1L6 6 ++#define TCNT1L7 7 ++ ++#define TCNT1H _SFR_MEM8(0x85) ++#define TCNT1H0 0 ++#define TCNT1H1 1 ++#define TCNT1H2 2 ++#define TCNT1H3 3 ++#define TCNT1H4 4 ++#define TCNT1H5 5 ++#define TCNT1H6 6 ++#define TCNT1H7 7 ++ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1L0 0 ++#define ICR1L1 1 ++#define ICR1L2 2 ++#define ICR1L3 3 ++#define ICR1L4 4 ++#define ICR1L5 5 ++#define ICR1L6 6 ++#define ICR1L7 7 ++ ++#define ICR1H _SFR_MEM8(0x87) ++#define ICR1H0 0 ++#define ICR1H1 1 ++#define ICR1H2 2 ++#define ICR1H3 3 ++#define ICR1H4 4 ++#define ICR1H5 5 ++#define ICR1H6 6 ++#define ICR1H7 7 ++ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AL0 0 ++#define OCR1AL1 1 ++#define OCR1AL2 2 ++#define OCR1AL3 3 ++#define OCR1AL4 4 ++#define OCR1AL5 5 ++#define OCR1AL6 6 ++#define OCR1AL7 7 ++ ++#define OCR1AH _SFR_MEM8(0x89) ++#define OCR1AH0 0 ++#define OCR1AH1 1 ++#define OCR1AH2 2 ++#define OCR1AH3 3 ++#define OCR1AH4 4 ++#define OCR1AH5 5 ++#define OCR1AH6 6 ++#define OCR1AH7 7 ++ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BL0 0 ++#define OCR1BL1 1 ++#define OCR1BL2 2 ++#define OCR1BL3 3 ++#define OCR1BL4 4 ++#define OCR1BL5 5 ++#define OCR1BL6 6 ++#define OCR1BL7 7 ++ ++#define OCR1BH _SFR_MEM8(0x8B) ++#define OCR1BH0 0 ++#define OCR1BH1 1 ++#define OCR1BH2 2 ++#define OCR1BH3 3 ++#define OCR1BH4 4 ++#define OCR1BH5 5 ++#define OCR1BH6 6 ++#define OCR1BH7 7 ++ ++#define TWBR _SFR_MEM8(0xB8) ++#define TWBR0 0 ++#define TWBR1 1 ++#define TWBR2 2 ++#define TWBR3 3 ++#define TWBR4 4 ++#define TWBR5 5 ++#define TWBR6 6 ++#define TWBR7 7 ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWPS0 0 ++#define TWPS1 1 ++#define TWS3 3 ++#define TWS4 4 ++#define TWS5 5 ++#define TWS6 6 ++#define TWS7 7 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWGCE 0 ++#define TWA0 1 ++#define TWA1 2 ++#define TWA2 3 ++#define TWA3 4 ++#define TWA4 5 ++#define TWA5 6 ++#define TWA6 7 ++ ++#define TWDR _SFR_MEM8(0xBB) ++#define TWD0 0 ++#define TWD1 1 ++#define TWD2 2 ++#define TWD3 3 ++#define TWD4 4 ++#define TWD5 5 ++#define TWD6 6 ++#define TWD7 7 ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWIE 0 ++#define TWEN 2 ++#define TWWC 3 ++#define TWSTO 4 ++#define TWSTA 5 ++#define TWEA 6 ++#define TWINT 7 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM0 1 ++#define TWAM1 2 ++#define TWAM2 3 ++#define TWAM3 4 ++#define TWAM4 5 ++#define TWAM5 6 ++#define TWAM6 7 ++ ++#define TWHSR _SFR_MEM8(0xBE) ++#define TWIHS 0 ++ ++ ++ ++/* Interrupt Vectors */ ++/* Interrupt vector 0 is the reset vector. */ ++ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++ ++#define PCINT0_vect_num 3 ++#define PCINT0_vect _VECTOR(3) ++ ++#define PCINT1_vect_num 4 ++#define PCINT1_vect _VECTOR(4) ++ ++#define PCINT2_vect_num 5 ++#define PCINT2_vect _VECTOR(5) ++ ++#define PCINT3_vect_num 6 ++#define PCINT3_vect _VECTOR(6) ++ ++#define WDT_vect_num 7 ++#define WDT_vect _VECTOR(7) ++ ++#define TIMER1_CAPT_vect_num 8 ++#define TIMER1_CAPT_vect _VECTOR(8) ++ ++#define TIMER1_COMPA_vect_num 9 ++#define TIMER1_COMPA_vect _VECTOR(9) ++ ++#define TIMER1_COMPB_vect_num 10 ++#define TIMER1_COMPB_vect _VECTOR(10) ++ ++#define TIMER1_OVF_vect_num 11 ++#define TIMER1_OVF_vect _VECTOR(11) ++ ++#define TIMER0_COMPA_vect_num 12 ++#define TIMER0_COMPA_vect _VECTOR(12) ++ ++#define TIMER0_COMPB_vect_num 13 ++#define TIMER0_COMPB_vect _VECTOR(13) ++ ++#define TIMER0_OVF_vect_num 14 ++#define TIMER0_OVF_vect _VECTOR(14) ++ ++#define SPI_STC_vect_num 15 ++#define SPI_STC_vect _VECTOR(15) ++ ++#define ADC_vect_num 16 ++#define ADC_vect _VECTOR(16) ++ ++#define EE_READY_vect_num 17 ++#define EE_READY_vect _VECTOR(17) ++ ++#define ANALOG_COMP_vect_num 18 ++#define ANALOG_COMP_vect _VECTOR(18) ++ ++#define TWI_vect_num 19 ++#define TWI_vect _VECTOR(19) ++ ++#define _VECTORS_SIZE 40 ++ ++ ++/* Constants */ ++#define RAMEND 0x2FF ++#define RAMSTART (0x100) ++#define XRAMSIZE 0 ++#define XRAMEND RAMEND ++#define E2END 0x3F ++#define E2PAGESIZE 4 ++#define FLASHEND 0x1FFF ++#define SPM_PAGESIZE 64 ++ ++ ++/* Fuse Information */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) /* Select Clock Source */ ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) /* Select Clock Source */ ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) /* Select Clock Source */ ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) /* Select Clock Source */ ++#define FUSE_SUT0 (unsigned char)~_BV(4) /* Select start-up time */ ++#define FUSE_SUT1 (unsigned char)~_BV(5) /* Select start-up time */ ++#define FUSE_CKOUT (unsigned char)~_BV(6) /* Clock output */ ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) /* Divide clock by 8 */ ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) /* Brown-out Detector trigger level */ ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) /* Brown-out Detector trigger level */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* EEPROM memory is preserved through chip erase */ ++#define FUSE_WDTON (unsigned char)~_BV(4) /* Watchdog Timer Always On */ ++#define FUSE_SPIEN (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */ ++#define FUSE_DWEN (unsigned char)~_BV(6) /* debugWIRE Enable */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(7) /* External reset disable */ ++#define HFUSE_DEFAULT (FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_SELFPRGEN ~_BV(0) /* Self Programming Enable */ ++#define EFUSE_DEFAULT (0xFF) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x11 ++ ++ ++#endif /* _AVR_IOTN88_H_ */ +diff --git a/include/avr/iotn9.h b/include/avr/iotn9.h +index 16dc4dc..240a31e 100644 +--- a/include/avr/iotn9.h ++++ b/include/avr/iotn9.h +@@ -1,468 +1,468 @@ +-/* Copyright (c) 2009 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotn9.h 2063 2009-11-18 22:06:28Z arcanum $ */ +- +-/* avr/iotn9.h - definitions for ATtiny9 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotn9.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATtiny9_H_ +-#define _AVR_ATtiny9_H_ 1 +- +- +-/* Registers and associated bit numbers. */ +- +-#define PINB _SFR_IO8(0x00) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +- +-#define DDRB _SFR_IO8(0x01) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +- +-#define PORTB _SFR_IO8(0x02) +-#define PORTB0 0 +-#define PORTB1 1 +-#define PORTB2 2 +-#define PORTB3 3 +- +-#define PUEB _SFR_IO8(0x03) +-#define PUEB0 0 +-#define PUEB1 1 +-#define PUEB2 2 +-#define PUEB3 3 +- +-#define PORTCR _SFR_IO8(0x0C) +-#define BBMB 1 +- +-#define PCMSK _SFR_IO8(0x10) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +- +-#define PCIFR _SFR_IO8(0x11) +-#define PCIF0 0 +- +-#define PCICR _SFR_IO8(0x12) +-#define PCIE0 0 +- +-#define EIMSK _SFR_IO8(0x13) +-#define INT0 0 +- +-#define EIFR _SFR_IO8(0x14) +-#define INTF0 0 +- +-#define EICRA _SFR_IO8(0x15) +-#define ISC00 0 +-#define ISC01 1 +- +-#define DIDR0 _SFR_IO8(0x17) +-#define AIN0D 0 +-#define AIN1D 1 +- +-#define ACSR _SFR_IO8(0x1F) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACIC 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACD 7 +- +-#define ICR0 _SFR_IO16(0x22) +- +-#define ICR0L _SFR_IO8(0x22) +-#define ICR0_0 0 +-#define ICR0_1 1 +-#define ICR0_2 2 +-#define ICR0_3 3 +-#define ICR0_4 4 +-#define ICR0_5 5 +-#define ICR0_6 6 +-#define ICR0_7 7 +- +-#define ICR0H _SFR_IO8(0x23) +-#define ICR0_8 0 +-#define ICR0_9 1 +-#define ICR0_10 2 +-#define ICR0_11 3 +-#define ICR0_12 4 +-#define ICR0_13 5 +-#define ICR0_14 6 +-#define ICR0_15 7 +- +-#define OCR0B _SFR_IO16(0x24) +- +-#define OCR0BL _SFR_IO8(0x24) +-#define OCR0B0 0 +-#define OCR0B1 1 +-#define OCR0B2 2 +-#define OCR0B3 3 +-#define OCR0B4 4 +-#define OCR0B5 5 +-#define OCR0B6 6 +-#define OCR0B7 7 +- +-#define OCR0BH _SFR_IO8(0x25) +-#define OCR0B8 0 +-#define OCR0B9 1 +-#define OCR0B10 2 +-#define OCR0B11 3 +-#define OCR0B12 4 +-#define OCR0B13 5 +-#define OCR0B14 6 +-#define OCR0B15 7 +- +-#define OCR0A _SFR_IO16(0x26) +- +-#define OCR0AL _SFR_IO8(0x26) +-#define OCR0A0 0 +-#define OCR0A1 1 +-#define OCR0A2 2 +-#define OCR0A3 3 +-#define OCR0A4 4 +-#define OCR0A5 5 +-#define OCR0A6 6 +-#define OCR0A7 7 +- +-#define OCR0AH _SFR_IO8(0x27) +-#define OCR0A8 0 +-#define OCR0A9 1 +-#define OCR0A10 2 +-#define OCR0A11 3 +-#define OCR0A12 4 +-#define OCR0A13 5 +-#define OCR0A14 6 +-#define OCR0A15 7 +- +-#define TCNT0 _SFR_IO16(0x28) +- +-#define TCNT0L _SFR_IO8(0x28) +-#define TCNT0_0 0 +-#define TCNT0_1 1 +-#define TCNT0_2 2 +-#define TCNT0_3 3 +-#define TCNT0_4 4 +-#define TCNT0_5 5 +-#define TCNT0_6 6 +-#define TCNT0_7 7 +- +-#define TCNT0H _SFR_IO8(0x29) +-#define TCNT0_8 0 +-#define TCNT0_9 1 +-#define TCNT0_10 2 +-#define TCNT0_11 3 +-#define TCNT0_12 4 +-#define TCNT0_13 5 +-#define TCNT0_14 6 +-#define TCNT0_15 7 +- +-#define TIFR0 _SFR_IO8(0x2A) +-#define TOV0 0 +-#define OCF0A 1 +-#define OCF0B 2 +-#define ICF0 5 +- +-#define TIMSK0 _SFR_IO8(0x2B) +-#define TOIE0 0 +-#define OCIE0A 1 +-#define OCIE0B 2 +-#define ICIE0 5 +- +-#define TCCR0C _SFR_IO8(0x2C) +-#define FOC0B 6 +-#define FOC0A 7 +- +-#define TCCR0B _SFR_IO8(0x2D) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define WGM02 3 +-#define WGM03 4 +-#define ICES0 6 +-#define ICNC0 7 +- +-#define TCCR0A _SFR_IO8(0x2E) +-#define WGM00 0 +-#define WGM01 1 +-#define COM0B0 4 +-#define COM0B1 5 +-#define COM0A0 6 +-#define COM0A1 7 +- +-#define GTCCR _SFR_IO8(0x2F) +-#define PSR 0 +-#define TSM 7 +- +-#define WDTCSR _SFR_IO8(0x31) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define NVMCSR _SFR_IO8(0x32) +-#define NVMBSY 7 +- +-#define NVMCMD _SFR_IO8(0x33) +-#define NVMCMD0 0 +-#define NVMCMD1 1 +-#define NVMCMD2 2 +-#define NVMCMD3 3 +-#define NVMCMD4 4 +-#define NVMCMD5 5 +- +-#define VLMCSR _SFR_IO8(0x34) +-#define VLM0 0 +-#define VLM1 1 +-#define VLM2 2 +-#define VLMIE 6 +-#define VLMF 7 +- +-#define PRR _SFR_IO8(0x35) +-#define PRTIM0 0 +-#define PRADC 1 +- +-#define CLKPSR _SFR_IO8(0x36) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +- +-#define CLKMSR _SFR_IO8(0x37) +-#define CLKMS0 0 +-#define CLKMS1 1 +- +-#define OSCCAL _SFR_IO8(0x39) +-#define CAL0 0 +-#define CAL1 1 +-#define CAL2 2 +-#define CAL3 3 +-#define CAL4 4 +-#define CAL5 5 +-#define CAL6 6 +-#define CAL7 7 +- +-#define SMCR _SFR_IO8(0x3A) +-#define SE 0 +-#define SM0 1 +-#define SM1 2 +-#define SM2 3 +- +-#define RSTFLR _SFR_IO8(0x3B) +-#define PORF 0 +-#define EXTRF 1 +-#define WDRF 3 +- +-#define CCP _SFR_IO8(0x3C) +-#define CCP0 0 +-#define CCP1 1 +-#define CCP2 2 +-#define CCP3 3 +-#define CCP4 4 +-#define CCP5 5 +-#define CCP6 6 +-#define CCP7 7 +- +- +-/* Interrupt vectors */ +-/* Vector 0 is the reset vector */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ +-#define TIM0_CAPT_vect_num 3 +-#define TIM0_CAPT_vect _VECTOR(3) /* Timer/Counter0 Input Capture */ +-#define TIM0_OVF_vect_num 4 +-#define TIM0_OVF_vect _VECTOR(4) /* Timer/Counter0 Overflow */ +-#define TIM0_COMPA_vect_num 5 +-#define TIM0_COMPA_vect _VECTOR(5) /* Timer/Counter Compare Match A */ +-#define TIM0_COMPB_vect_num 6 +-#define TIM0_COMPB_vect _VECTOR(6) /* Timer/Counter Compare Match B */ +-#define ANA_COMP_vect_num 7 +-#define ANA_COMP_vect _VECTOR(7) /* Analog Comparator */ +-#define WDT_vect_num 8 +-#define WDT_vect _VECTOR(8) /* Watchdog Time-out */ +-#define VLM_vect_num 9 +-#define VLM_vect _VECTOR(9) /* Vcc Voltage Level Monitor */ +- +-#define _VECTOR_SIZE 2 /* Size of individual vector. */ +-#define _VECTORS_SIZE (10 * _VECTOR_SIZE) +- +- +-/* Constants */ +-#define SPM_PAGESIZE (32) +-#define RAMSTART (0x40) +-#define RAMSIZE (32) +-#define RAMEND (RAMSTART + RAMSIZE - 1) +-#define XRAMSTART (NA) +-#define XRAMSIZE (0) +-#define XRAMEND (RAMEND) +-#define E2END (0x0) +-#define E2PAGESIZE (0) +-#define FLASHEND (0x3FF) +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 0 +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x90 +-#define SIGNATURE_2 0x08 +- +- +-/* Device Pin Definitions */ +-#define SPDATA_DDR DDRCINT +-#define SPDATA_PORT PORTCINT +-#define SPDATA_PIN PINCINT +-#define SPDATA_BIT INT0 +- +-#define OC0A_DDR DDRCINT +-#define OC0A_PORT PORTCINT +-#define OC0A_PIN PINCINT +-#define OC0A_BIT INT0 +- +-#define ADC0_DDR DDRCINT +-#define ADC0_PORT PORTCINT +-#define ADC0_PIN PINCINT +-#define ADC0_BIT INT0 +- +-#define AIN0_DDR DDRCINT +-#define AIN0_PORT PORTCINT +-#define AIN0_PIN PINCINT +-#define AIN0_BIT INT0 +- +-#define PB0_DDR DDRCINT +-#define PB0_PORT PORTCINT +-#define PB0_PIN PINCINT +-#define PB0_BIT INT0 +- +-#define SPCLK_DDR DDRCINT +-#define SPCLK_PORT PORTCINT +-#define SPCLK_PIN PINCINT +-#define SPCLK_BIT INT1 +- +-#define CLKI_DDR DDRCINT +-#define CLKI_PORT PORTCINT +-#define CLKI_PIN PINCINT +-#define CLKI_BIT INT1 +- +-#define ICP0_DDR DDRCINT +-#define ICP0_PORT PORTCINT +-#define ICP0_PIN PINCINT +-#define ICP0_BIT INT1 +- +-#define OC0B_DDR DDRCINT +-#define OC0B_PORT PORTCINT +-#define OC0B_PIN PINCINT +-#define OC0B_BIT INT1 +- +-#define ADC1_DDR DDRCINT +-#define ADC1_PORT PORTCINT +-#define ADC1_PIN PINCINT +-#define ADC1_BIT INT1 +- +-#define AIN1_DDR DDRCINT +-#define AIN1_PORT PORTCINT +-#define AIN1_PIN PINCINT +-#define AIN1_BIT INT1 +- +-#define PB1_DDR DDRCINT +-#define PB1_PORT PORTCINT +-#define PB1_PIN PINCINT +-#define PB1_BIT INT1 +- +-#define CLKO_DDR DDRT +-#define CLKO_PORT PORTT +-#define CLKO_PIN PINT +-#define CLKO_BIT T0 +- +-#define PCINT2_DDR DDRT +-#define PCINT2_PORT PORTT +-#define PCINT2_PIN PINT +-#define PCINT2_BIT T0 +- +-#define INT0_DDR DDRT +-#define INT0_PORT PORTT +-#define INT0_PIN PINT +-#define INT0_BIT T0 +- +-#define ADC2_DDR DDRT +-#define ADC2_PORT PORTT +-#define ADC2_PIN PINT +-#define ADC2_BIT T0 +- +-#define PB2_DDR DDRT +-#define PB2_PORT PORTT +-#define PB2_PIN PINT +-#define PB2_BIT T0 +- +-#define PCINT3_DDR DDRRESET +-#define PCINT3_PORT PORTRESET +-#define PCINT3_PIN PINRESET +-#define PCINT3_BIT RESET +- +-#define ADC3_DDR DDRRESET +-#define ADC3_PORT PORTRESET +-#define ADC3_PIN PINRESET +-#define ADC3_BIT RESET +- +-#define PB3_DDR DDRRESET +-#define PB3_PORT PORTRESET +-#define PB3_PIN PINRESET +-#define PB3_BIT RESET +- +-#endif /* _AVR_ATtiny9_H_ */ +- ++/* Copyright (c) 2009 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotn9.h 2063 2009-11-18 22:06:28Z arcanum $ */ ++ ++/* avr/iotn9.h - definitions for ATtiny9 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotn9.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATtiny9_H_ ++#define _AVR_ATtiny9_H_ 1 ++ ++ ++/* Registers and associated bit numbers. */ ++ ++#define PINB _SFR_IO8(0x00) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++ ++#define DDRB _SFR_IO8(0x01) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++ ++#define PORTB _SFR_IO8(0x02) ++#define PORTB0 0 ++#define PORTB1 1 ++#define PORTB2 2 ++#define PORTB3 3 ++ ++#define PUEB _SFR_IO8(0x03) ++#define PUEB0 0 ++#define PUEB1 1 ++#define PUEB2 2 ++#define PUEB3 3 ++ ++#define PORTCR _SFR_IO8(0x0C) ++#define BBMB 1 ++ ++#define PCMSK _SFR_IO8(0x10) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++ ++#define PCIFR _SFR_IO8(0x11) ++#define PCIF0 0 ++ ++#define PCICR _SFR_IO8(0x12) ++#define PCIE0 0 ++ ++#define EIMSK _SFR_IO8(0x13) ++#define INT0 0 ++ ++#define EIFR _SFR_IO8(0x14) ++#define INTF0 0 ++ ++#define EICRA _SFR_IO8(0x15) ++#define ISC00 0 ++#define ISC01 1 ++ ++#define DIDR0 _SFR_IO8(0x17) ++#define AIN0D 0 ++#define AIN1D 1 ++ ++#define ACSR _SFR_IO8(0x1F) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACIC 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACD 7 ++ ++#define ICR0 _SFR_IO16(0x22) ++ ++#define ICR0L _SFR_IO8(0x22) ++#define ICR0_0 0 ++#define ICR0_1 1 ++#define ICR0_2 2 ++#define ICR0_3 3 ++#define ICR0_4 4 ++#define ICR0_5 5 ++#define ICR0_6 6 ++#define ICR0_7 7 ++ ++#define ICR0H _SFR_IO8(0x23) ++#define ICR0_8 0 ++#define ICR0_9 1 ++#define ICR0_10 2 ++#define ICR0_11 3 ++#define ICR0_12 4 ++#define ICR0_13 5 ++#define ICR0_14 6 ++#define ICR0_15 7 ++ ++#define OCR0B _SFR_IO16(0x24) ++ ++#define OCR0BL _SFR_IO8(0x24) ++#define OCR0B0 0 ++#define OCR0B1 1 ++#define OCR0B2 2 ++#define OCR0B3 3 ++#define OCR0B4 4 ++#define OCR0B5 5 ++#define OCR0B6 6 ++#define OCR0B7 7 ++ ++#define OCR0BH _SFR_IO8(0x25) ++#define OCR0B8 0 ++#define OCR0B9 1 ++#define OCR0B10 2 ++#define OCR0B11 3 ++#define OCR0B12 4 ++#define OCR0B13 5 ++#define OCR0B14 6 ++#define OCR0B15 7 ++ ++#define OCR0A _SFR_IO16(0x26) ++ ++#define OCR0AL _SFR_IO8(0x26) ++#define OCR0A0 0 ++#define OCR0A1 1 ++#define OCR0A2 2 ++#define OCR0A3 3 ++#define OCR0A4 4 ++#define OCR0A5 5 ++#define OCR0A6 6 ++#define OCR0A7 7 ++ ++#define OCR0AH _SFR_IO8(0x27) ++#define OCR0A8 0 ++#define OCR0A9 1 ++#define OCR0A10 2 ++#define OCR0A11 3 ++#define OCR0A12 4 ++#define OCR0A13 5 ++#define OCR0A14 6 ++#define OCR0A15 7 ++ ++#define TCNT0 _SFR_IO16(0x28) ++ ++#define TCNT0L _SFR_IO8(0x28) ++#define TCNT0_0 0 ++#define TCNT0_1 1 ++#define TCNT0_2 2 ++#define TCNT0_3 3 ++#define TCNT0_4 4 ++#define TCNT0_5 5 ++#define TCNT0_6 6 ++#define TCNT0_7 7 ++ ++#define TCNT0H _SFR_IO8(0x29) ++#define TCNT0_8 0 ++#define TCNT0_9 1 ++#define TCNT0_10 2 ++#define TCNT0_11 3 ++#define TCNT0_12 4 ++#define TCNT0_13 5 ++#define TCNT0_14 6 ++#define TCNT0_15 7 ++ ++#define TIFR0 _SFR_IO8(0x2A) ++#define TOV0 0 ++#define OCF0A 1 ++#define OCF0B 2 ++#define ICF0 5 ++ ++#define TIMSK0 _SFR_IO8(0x2B) ++#define TOIE0 0 ++#define OCIE0A 1 ++#define OCIE0B 2 ++#define ICIE0 5 ++ ++#define TCCR0C _SFR_IO8(0x2C) ++#define FOC0B 6 ++#define FOC0A 7 ++ ++#define TCCR0B _SFR_IO8(0x2D) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define WGM02 3 ++#define WGM03 4 ++#define ICES0 6 ++#define ICNC0 7 ++ ++#define TCCR0A _SFR_IO8(0x2E) ++#define WGM00 0 ++#define WGM01 1 ++#define COM0B0 4 ++#define COM0B1 5 ++#define COM0A0 6 ++#define COM0A1 7 ++ ++#define GTCCR _SFR_IO8(0x2F) ++#define PSR 0 ++#define TSM 7 ++ ++#define WDTCSR _SFR_IO8(0x31) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define NVMCSR _SFR_IO8(0x32) ++#define NVMBSY 7 ++ ++#define NVMCMD _SFR_IO8(0x33) ++#define NVMCMD0 0 ++#define NVMCMD1 1 ++#define NVMCMD2 2 ++#define NVMCMD3 3 ++#define NVMCMD4 4 ++#define NVMCMD5 5 ++ ++#define VLMCSR _SFR_IO8(0x34) ++#define VLM0 0 ++#define VLM1 1 ++#define VLM2 2 ++#define VLMIE 6 ++#define VLMF 7 ++ ++#define PRR _SFR_IO8(0x35) ++#define PRTIM0 0 ++#define PRADC 1 ++ ++#define CLKPSR _SFR_IO8(0x36) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++ ++#define CLKMSR _SFR_IO8(0x37) ++#define CLKMS0 0 ++#define CLKMS1 1 ++ ++#define OSCCAL _SFR_IO8(0x39) ++#define CAL0 0 ++#define CAL1 1 ++#define CAL2 2 ++#define CAL3 3 ++#define CAL4 4 ++#define CAL5 5 ++#define CAL6 6 ++#define CAL7 7 ++ ++#define SMCR _SFR_IO8(0x3A) ++#define SE 0 ++#define SM0 1 ++#define SM1 2 ++#define SM2 3 ++ ++#define RSTFLR _SFR_IO8(0x3B) ++#define PORF 0 ++#define EXTRF 1 ++#define WDRF 3 ++ ++#define CCP _SFR_IO8(0x3C) ++#define CCP0 0 ++#define CCP1 1 ++#define CCP2 2 ++#define CCP3 3 ++#define CCP4 4 ++#define CCP5 5 ++#define CCP6 6 ++#define CCP7 7 ++ ++ ++/* Interrupt vectors */ ++/* Vector 0 is the reset vector */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) /* External Interrupt Request 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) /* Pin Change Interrupt Request 0 */ ++#define TIM0_CAPT_vect_num 3 ++#define TIM0_CAPT_vect _VECTOR(3) /* Timer/Counter0 Input Capture */ ++#define TIM0_OVF_vect_num 4 ++#define TIM0_OVF_vect _VECTOR(4) /* Timer/Counter0 Overflow */ ++#define TIM0_COMPA_vect_num 5 ++#define TIM0_COMPA_vect _VECTOR(5) /* Timer/Counter Compare Match A */ ++#define TIM0_COMPB_vect_num 6 ++#define TIM0_COMPB_vect _VECTOR(6) /* Timer/Counter Compare Match B */ ++#define ANA_COMP_vect_num 7 ++#define ANA_COMP_vect _VECTOR(7) /* Analog Comparator */ ++#define WDT_vect_num 8 ++#define WDT_vect _VECTOR(8) /* Watchdog Time-out */ ++#define VLM_vect_num 9 ++#define VLM_vect _VECTOR(9) /* Vcc Voltage Level Monitor */ ++ ++#define _VECTOR_SIZE 2 /* Size of individual vector. */ ++#define _VECTORS_SIZE (10 * _VECTOR_SIZE) ++ ++ ++/* Constants */ ++#define SPM_PAGESIZE (32) ++#define RAMSTART (0x40) ++#define RAMSIZE (32) ++#define RAMEND (RAMSTART + RAMSIZE - 1) ++#define XRAMSTART (NA) ++#define XRAMSIZE (0) ++#define XRAMEND (RAMEND) ++#define E2END (0x0) ++#define E2PAGESIZE (0) ++#define FLASHEND (0x3FF) ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 0 ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x90 ++#define SIGNATURE_2 0x08 ++ ++ ++/* Device Pin Definitions */ ++#define SPDATA_DDR DDRCINT ++#define SPDATA_PORT PORTCINT ++#define SPDATA_PIN PINCINT ++#define SPDATA_BIT INT0 ++ ++#define OC0A_DDR DDRCINT ++#define OC0A_PORT PORTCINT ++#define OC0A_PIN PINCINT ++#define OC0A_BIT INT0 ++ ++#define ADC0_DDR DDRCINT ++#define ADC0_PORT PORTCINT ++#define ADC0_PIN PINCINT ++#define ADC0_BIT INT0 ++ ++#define AIN0_DDR DDRCINT ++#define AIN0_PORT PORTCINT ++#define AIN0_PIN PINCINT ++#define AIN0_BIT INT0 ++ ++#define PB0_DDR DDRCINT ++#define PB0_PORT PORTCINT ++#define PB0_PIN PINCINT ++#define PB0_BIT INT0 ++ ++#define SPCLK_DDR DDRCINT ++#define SPCLK_PORT PORTCINT ++#define SPCLK_PIN PINCINT ++#define SPCLK_BIT INT1 ++ ++#define CLKI_DDR DDRCINT ++#define CLKI_PORT PORTCINT ++#define CLKI_PIN PINCINT ++#define CLKI_BIT INT1 ++ ++#define ICP0_DDR DDRCINT ++#define ICP0_PORT PORTCINT ++#define ICP0_PIN PINCINT ++#define ICP0_BIT INT1 ++ ++#define OC0B_DDR DDRCINT ++#define OC0B_PORT PORTCINT ++#define OC0B_PIN PINCINT ++#define OC0B_BIT INT1 ++ ++#define ADC1_DDR DDRCINT ++#define ADC1_PORT PORTCINT ++#define ADC1_PIN PINCINT ++#define ADC1_BIT INT1 ++ ++#define AIN1_DDR DDRCINT ++#define AIN1_PORT PORTCINT ++#define AIN1_PIN PINCINT ++#define AIN1_BIT INT1 ++ ++#define PB1_DDR DDRCINT ++#define PB1_PORT PORTCINT ++#define PB1_PIN PINCINT ++#define PB1_BIT INT1 ++ ++#define CLKO_DDR DDRT ++#define CLKO_PORT PORTT ++#define CLKO_PIN PINT ++#define CLKO_BIT T0 ++ ++#define PCINT2_DDR DDRT ++#define PCINT2_PORT PORTT ++#define PCINT2_PIN PINT ++#define PCINT2_BIT T0 ++ ++#define INT0_DDR DDRT ++#define INT0_PORT PORTT ++#define INT0_PIN PINT ++#define INT0_BIT T0 ++ ++#define ADC2_DDR DDRT ++#define ADC2_PORT PORTT ++#define ADC2_PIN PINT ++#define ADC2_BIT T0 ++ ++#define PB2_DDR DDRT ++#define PB2_PORT PORTT ++#define PB2_PIN PINT ++#define PB2_BIT T0 ++ ++#define PCINT3_DDR DDRRESET ++#define PCINT3_PORT PORTRESET ++#define PCINT3_PIN PINRESET ++#define PCINT3_BIT RESET ++ ++#define ADC3_DDR DDRRESET ++#define ADC3_PORT PORTRESET ++#define ADC3_PIN PINRESET ++#define ADC3_BIT RESET ++ ++#define PB3_DDR DDRRESET ++#define PB3_PORT PORTRESET ++#define PB3_PIN PINRESET ++#define PB3_BIT RESET ++ ++#endif /* _AVR_ATtiny9_H_ */ ++ +diff --git a/include/avr/iotnx4.h b/include/avr/iotnx4.h +index ddcadae..584a925 100644 +--- a/include/avr/iotnx4.h ++++ b/include/avr/iotnx4.h +@@ -1,476 +1,476 @@ +-/* Copyright (c) 2005,2007 Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotnx4.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* avr/iotnx4.h - definitions for ATtiny24, ATtiny44 and ATtiny84 */ +- +-#ifndef _AVR_IOTNX4_H_ +-#define _AVR_IOTNX4_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotnx4.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-#define PRR _SFR_IO8 (0x00) +-#define PRTIM1 3 +-#define PRTIM0 2 +-#define PRUSI 1 +-#define PRADC 0 +- +-#define DIDR0 _SFR_IO8(0x01) +-#define ADC7D 7 +-#define ADC6D 6 +-#define ADC5D 5 +-#define ADC4D 4 +-#define ADC3D 3 +-#define ADC2D 2 +-#define ADC1D 1 +-#define ADC0D 0 +- +-/* Reserved [0x02] */ +- +-#define ADCSRB _SFR_IO8 (0x03) +-#define BIN 7 +-#define ACME 6 +-#define ADLAR 4 +-#define ADTS2 2 +-#define ADTS1 1 +-#define ADTS0 0 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x04) +-#endif +-#define ADCW _SFR_IO16(0x04) +-#define ADCL _SFR_IO8(0x04) +-#define ADCH _SFR_IO8(0x05) +- +-#define ADCSRA _SFR_IO8 (0x06) +-#define ADEN 7 +-#define ADSC 6 +-#define ADATE 5 +-#define ADIF 4 +-#define ADIE 3 +-#define ADPS2 2 +-#define ADPS1 1 +-#define ADPS0 0 +- +-#define ADMUX _SFR_IO8(0x07) +-#define REFS1 7 +-#define REFS0 6 +-#define MUX5 5 +-#define MUX4 4 +-#define MUX3 3 +-#define MUX2 2 +-#define MUX1 1 +-#define MUX0 0 +- +-#define ACSR _SFR_IO8(0x08) +-#define ACD 7 +-#define ACBG 6 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +- +-/* Reserved [0x09..0x0A] */ +- +-#define TIFR1 _SFR_IO8(0x0B) +-#define ICF1 5 +-#define OCF1B 2 +-#define OCF1A 1 +-#define TOV1 0 +- +-#define TIMSK1 _SFR_IO8(0x0C) +-#define ICIE1 5 +-#define OCIE1B 2 +-#define OCIE1A 1 +-#define TOIE1 0 +- +-#define USICR _SFR_IO8(0x0D) +-#define USISIE 7 +-#define USIOIE 6 +-#define USIWM1 5 +-#define USIWM0 4 +-#define USICS1 3 +-#define USICS0 2 +-#define USICLK 1 +-#define USITC 0 +- +-#define USISR _SFR_IO8(0x0E) +-#define USISIF 7 +-#define USIOIF 6 +-#define USIPF 5 +-#define USIDC 4 +-#define USICNT3 3 +-#define USICNT2 2 +-#define USICNT1 1 +-#define USICNT0 0 +- +-#define USIDR _SFR_IO8(0x0F) +- +-#define USIBR _SFR_IO8(0x10) +- +-/* Reserved [0x11] */ +- +-#define PCMSK0 _SFR_IO8(0x12) +-#define PCINT7 7 +-#define PCINT6 6 +-#define PCINT5 5 +-#define PCINT4 4 +-#define PCINT3 3 +-#define PCINT2 2 +-#define PCINT1 1 +-#define PCINT0 0 +- +-#define GPIOR0 _SFR_IO8(0x13) +- +-#define GPIOR1 _SFR_IO8(0x14) +- +-#define GPIOR2 _SFR_IO8(0x15) +- +-#define PINB _SFR_IO8(0x16) +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-#define DDRB _SFR_IO8(0x17) +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-#define PORTB _SFR_IO8(0x18) +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-#define PINA _SFR_IO8(0x19) +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-#define DDRA _SFR_IO8(0x1A) +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-#define PORTA _SFR_IO8(0x1B) +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-/* EEPROM Control Register EECR */ +-#define EECR _SFR_IO8(0x1C) +-#define EEPM1 5 +-#define EEPM0 4 +-#define EERIE 3 +-#define EEMPE 2 +-#define EEPE 1 +-#define EERE 0 +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO16(0x1E) +-#define EEARL _SFR_IO8(0x1E) +-#define EEARH _SFR_IO8(0x1F) +- +-#define PCMSK1 _SFR_IO8(0x20) +-#define PCINT11 3 +-#define PCINT10 2 +-#define PCINT9 1 +-#define PCINT8 0 +- +-#define WDTCSR _SFR_IO8(0x21) +-#define WDIF 7 +-#define WDIE 6 +-#define WDP3 5 +-#define WDCE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-#define TCCR1C _SFR_IO8(0x22) +-#define FOC1A 7 +-#define FOC1B 6 +- +-#define GTCCR _SFR_IO8(0x23) +-#define TSM 7 +-#define PSR10 0 +- +-#define ICR1 _SFR_IO16(0x24) +-#define ICR1L _SFR_IO8(0x24) +-#define ICR1H _SFR_IO8(0x25) +- +-#define CLKPR _SFR_IO8(0x26) +-#define CLKPCE 7 +-#define CLKPS3 3 +-#define CLKPS2 2 +-#define CLKPS1 1 +-#define CLKPS0 0 +- +-#define DWDR _SFR_IO8(0x27) +- +-#define OCR1B _SFR_IO16(0x28) +-#define OCR1BL _SFR_IO8(0x28) +-#define OCR1BH _SFR_IO8(0x29) +- +-#define OCR1A _SFR_IO16(0x2A) +-#define OCR1AL _SFR_IO8(0x2A) +-#define OCR1AH _SFR_IO8(0x2B) +- +-/* keep misspelled names from avr-libc 1.4.[0..1] for compatibility */ +-#define OCRB1 _SFR_IO16(0x28) +-#define OCRB1L _SFR_IO8(0x28) +-#define OCRB1H _SFR_IO8(0x29) +- +-#define OCRA1 _SFR_IO16(0x2A) +-#define OCRA1L _SFR_IO8(0x2A) +-#define OCRA1H _SFR_IO8(0x2B) +- +-#define TCNT1 _SFR_IO16(0x2C) +-#define TCNT1L _SFR_IO8(0x2C) +-#define TCNT1H _SFR_IO8(0x2D) +- +-#define TCCR1B _SFR_IO8(0x2E) +-#define ICNC1 7 +-#define ICES1 6 +-#define WGM13 4 +-#define WGM12 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-#define TCCR1A _SFR_IO8(0x2F) +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define WGM11 1 +-#define WGM10 0 +- +-#define TCCR0A _SFR_IO8(0x30) +-#define COM0A1 7 +-#define COM0A0 6 +-#define COM0B1 5 +-#define COM0B0 4 +-#define WGM01 1 +-#define WGM00 0 +- +-#define OSCCAL _SFR_IO8(0x31) +- +-#define TCNT0 _SFR_IO8(0x32) +- +-#define TCCR0B _SFR_IO8(0x33) +-#define FOC0A 7 +-#define FOC0B 6 +-#define WGM02 3 +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-#define MCUSR _SFR_IO8(0x34) +-#define WDRF 3 +-#define BORF 2 +-#define EXTRF 1 +-#define PORF 0 +- +-#define MCUCR _SFR_IO8(0x35) +-#define BODS 7 +-#define PUD 6 +-#define SE 5 +-#define SM1 4 +-#define SM0 3 +-#define BODSE 2 +-#define ISC01 1 +-#define ISC00 0 +- +-#define OCR0A _SFR_IO8(0x36) +- +-#define SPMCSR _SFR_IO8(0x37) +-#define RSIG 5 +-#define CTPB 4 +-#define RFLB 3 +-#define PGWRT 2 +-#define PGERS 1 +-#define SPMEN 0 +- +-#define TIFR0 _SFR_IO8(0x38) +-#define OCF0B 2 +-#define OCF0A 1 +-#define TOV0 0 +- +-#define TIMSK0 _SFR_IO8(0x39) +-#define OCIE0B 2 +-#define OCIE0A 1 +-#define TOIE0 0 +- +-#define GIFR _SFR_IO8(0x3A) +-#define INTF0 6 +-#define PCIF1 5 +-#define PCIF0 4 +- +-#define GIMSK _SFR_IO8(0x3B) +-#define INT0 6 +-#define PCIE1 5 +-#define PCIE0 4 +- +-#define OCR0B _SFR_IO8(0x3C) +- +-/* 0x3D..0x3E SP [defined in ] */ +-/* 0x3F SREG [defined in ] */ +- +-///--- +- +-/* Interrupt vectors */ +-/* Interrupt vector 0 is the reset vector. */ +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define EXT_INT0_vect_num 1 +-#define EXT_INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* Pin Change Interrupt Request 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) +-#define SIG_PIN_CHANGE0 _VECTOR(2) +- +-/* Pin Change Interrupt Request 1 */ +-#define PCINT1_vect_num 3 +-#define PCINT1_vect _VECTOR(3) +-#define SIG_PIN_CHANGE1 _VECTOR(3) +- +-/* Watchdog Time-out */ +-#define WDT_vect_num 4 +-#define WDT_vect _VECTOR(4) +-#define WATCHDOG_vect_num 4 +-#define WATCHDOG_vect _VECTOR(4) +-#define SIG_WATCHDOG_TIMEOUT _VECTOR(4) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 5 +-#define TIMER1_CAPT_vect _VECTOR(5) +-#define TIM1_CAPT_vect_num 5 +-#define TIM1_CAPT_vect _VECTOR(5) +-#define SIG_INPUT_CAPTURE1 _VECTOR(5) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIM1_COMPA_vect_num 6 +-#define TIM1_COMPA_vect _VECTOR(6) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(6) +- +-/* Timer/Counter1 Compare Match B */ +-#define TIM1_COMPB_vect_num 7 +-#define TIM1_COMPB_vect _VECTOR(7) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(7) +- +-/* Timer/Counter1 Overflow */ +-#define TIM1_OVF_vect_num 8 +-#define TIM1_OVF_vect _VECTOR(8) +-#define SIG_OVERFLOW1 _VECTOR(8) +- +-/* Timer/Counter0 Compare Match A */ +-#define TIM0_COMPA_vect_num 9 +-#define TIM0_COMPA_vect _VECTOR(9) +-#define SIG_OUTPUT_COMPARE0A _VECTOR(9) +- +-/* Timer/Counter0 Compare Match B */ +-#define TIM0_COMPB_vect_num 10 +-#define TIM0_COMPB_vect _VECTOR(10) +-#define SIG_OUTPUT_COMPARE0B _VECTOR(10) +- +-/* Timer/Counter0 Overflow */ +-#define TIM0_OVF_vect_num 11 +-#define TIM0_OVF_vect _VECTOR(11) +-#define SIG_OVERFLOW0 _VECTOR(11) +- +-/* Analog Comparator */ +-#define ANA_COMP_vect_num 12 +-#define ANA_COMP_vect _VECTOR(12) +-#define SIG_COMPARATOR _VECTOR(12) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 13 +-#define ADC_vect _VECTOR(13) +-#define SIG_ADC _VECTOR(13) +- +-/* EEPROM Ready */ +-#define EE_RDY_vect_num 14 +-#define EE_RDY_vect _VECTOR(14) +-#define SIG_EEPROM_READY _VECTOR(14) +- +-/* USI START */ +-#define USI_START_vect_num 15 +-#define USI_START_vect _VECTOR(15) +-#define USI_STR_vect_num 15 +-#define USI_STR_vect _VECTOR(15) +-#define SIG_USI_START _VECTOR(15) +- +-/* USI Overflow */ +-#define USI_OVF_vect_num 16 +-#define USI_OVF_vect _VECTOR(16) +-#define SIG_USI_OVERFLOW _VECTOR(16) +- +-#define _VECTORS_SIZE 34 +- +-#endif /* _AVR_IOTNX4_H_ */ ++/* Copyright (c) 2005,2007 Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotnx4.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* avr/iotnx4.h - definitions for ATtiny24, ATtiny44 and ATtiny84 */ ++ ++#ifndef _AVR_IOTNX4_H_ ++#define _AVR_IOTNX4_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotnx4.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++#define PRR _SFR_IO8 (0x00) ++#define PRTIM1 3 ++#define PRTIM0 2 ++#define PRUSI 1 ++#define PRADC 0 ++ ++#define DIDR0 _SFR_IO8(0x01) ++#define ADC7D 7 ++#define ADC6D 6 ++#define ADC5D 5 ++#define ADC4D 4 ++#define ADC3D 3 ++#define ADC2D 2 ++#define ADC1D 1 ++#define ADC0D 0 ++ ++/* Reserved [0x02] */ ++ ++#define ADCSRB _SFR_IO8 (0x03) ++#define BIN 7 ++#define ACME 6 ++#define ADLAR 4 ++#define ADTS2 2 ++#define ADTS1 1 ++#define ADTS0 0 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCW _SFR_IO16(0x04) ++#define ADCL _SFR_IO8(0x04) ++#define ADCH _SFR_IO8(0x05) ++ ++#define ADCSRA _SFR_IO8 (0x06) ++#define ADEN 7 ++#define ADSC 6 ++#define ADATE 5 ++#define ADIF 4 ++#define ADIE 3 ++#define ADPS2 2 ++#define ADPS1 1 ++#define ADPS0 0 ++ ++#define ADMUX _SFR_IO8(0x07) ++#define REFS1 7 ++#define REFS0 6 ++#define MUX5 5 ++#define MUX4 4 ++#define MUX3 3 ++#define MUX2 2 ++#define MUX1 1 ++#define MUX0 0 ++ ++#define ACSR _SFR_IO8(0x08) ++#define ACD 7 ++#define ACBG 6 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++/* Reserved [0x09..0x0A] */ ++ ++#define TIFR1 _SFR_IO8(0x0B) ++#define ICF1 5 ++#define OCF1B 2 ++#define OCF1A 1 ++#define TOV1 0 ++ ++#define TIMSK1 _SFR_IO8(0x0C) ++#define ICIE1 5 ++#define OCIE1B 2 ++#define OCIE1A 1 ++#define TOIE1 0 ++ ++#define USICR _SFR_IO8(0x0D) ++#define USISIE 7 ++#define USIOIE 6 ++#define USIWM1 5 ++#define USIWM0 4 ++#define USICS1 3 ++#define USICS0 2 ++#define USICLK 1 ++#define USITC 0 ++ ++#define USISR _SFR_IO8(0x0E) ++#define USISIF 7 ++#define USIOIF 6 ++#define USIPF 5 ++#define USIDC 4 ++#define USICNT3 3 ++#define USICNT2 2 ++#define USICNT1 1 ++#define USICNT0 0 ++ ++#define USIDR _SFR_IO8(0x0F) ++ ++#define USIBR _SFR_IO8(0x10) ++ ++/* Reserved [0x11] */ ++ ++#define PCMSK0 _SFR_IO8(0x12) ++#define PCINT7 7 ++#define PCINT6 6 ++#define PCINT5 5 ++#define PCINT4 4 ++#define PCINT3 3 ++#define PCINT2 2 ++#define PCINT1 1 ++#define PCINT0 0 ++ ++#define GPIOR0 _SFR_IO8(0x13) ++ ++#define GPIOR1 _SFR_IO8(0x14) ++ ++#define GPIOR2 _SFR_IO8(0x15) ++ ++#define PINB _SFR_IO8(0x16) ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x17) ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++#define PORTB _SFR_IO8(0x18) ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++#define PINA _SFR_IO8(0x19) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0x1A) ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++#define PORTA _SFR_IO8(0x1B) ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++/* EEPROM Control Register EECR */ ++#define EECR _SFR_IO8(0x1C) ++#define EEPM1 5 ++#define EEPM0 4 ++#define EERIE 3 ++#define EEMPE 2 ++#define EEPE 1 ++#define EERE 0 ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO16(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++#define EEARH _SFR_IO8(0x1F) ++ ++#define PCMSK1 _SFR_IO8(0x20) ++#define PCINT11 3 ++#define PCINT10 2 ++#define PCINT9 1 ++#define PCINT8 0 ++ ++#define WDTCSR _SFR_IO8(0x21) ++#define WDIF 7 ++#define WDIE 6 ++#define WDP3 5 ++#define WDCE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++#define TCCR1C _SFR_IO8(0x22) ++#define FOC1A 7 ++#define FOC1B 6 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define TSM 7 ++#define PSR10 0 ++ ++#define ICR1 _SFR_IO16(0x24) ++#define ICR1L _SFR_IO8(0x24) ++#define ICR1H _SFR_IO8(0x25) ++ ++#define CLKPR _SFR_IO8(0x26) ++#define CLKPCE 7 ++#define CLKPS3 3 ++#define CLKPS2 2 ++#define CLKPS1 1 ++#define CLKPS0 0 ++ ++#define DWDR _SFR_IO8(0x27) ++ ++#define OCR1B _SFR_IO16(0x28) ++#define OCR1BL _SFR_IO8(0x28) ++#define OCR1BH _SFR_IO8(0x29) ++ ++#define OCR1A _SFR_IO16(0x2A) ++#define OCR1AL _SFR_IO8(0x2A) ++#define OCR1AH _SFR_IO8(0x2B) ++ ++/* keep misspelled names from avr-libc 1.4.[0..1] for compatibility */ ++#define OCRB1 _SFR_IO16(0x28) ++#define OCRB1L _SFR_IO8(0x28) ++#define OCRB1H _SFR_IO8(0x29) ++ ++#define OCRA1 _SFR_IO16(0x2A) ++#define OCRA1L _SFR_IO8(0x2A) ++#define OCRA1H _SFR_IO8(0x2B) ++ ++#define TCNT1 _SFR_IO16(0x2C) ++#define TCNT1L _SFR_IO8(0x2C) ++#define TCNT1H _SFR_IO8(0x2D) ++ ++#define TCCR1B _SFR_IO8(0x2E) ++#define ICNC1 7 ++#define ICES1 6 ++#define WGM13 4 ++#define WGM12 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++#define TCCR1A _SFR_IO8(0x2F) ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define WGM11 1 ++#define WGM10 0 ++ ++#define TCCR0A _SFR_IO8(0x30) ++#define COM0A1 7 ++#define COM0A0 6 ++#define COM0B1 5 ++#define COM0B0 4 ++#define WGM01 1 ++#define WGM00 0 ++ ++#define OSCCAL _SFR_IO8(0x31) ++ ++#define TCNT0 _SFR_IO8(0x32) ++ ++#define TCCR0B _SFR_IO8(0x33) ++#define FOC0A 7 ++#define FOC0B 6 ++#define WGM02 3 ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define WDRF 3 ++#define BORF 2 ++#define EXTRF 1 ++#define PORF 0 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define BODS 7 ++#define PUD 6 ++#define SE 5 ++#define SM1 4 ++#define SM0 3 ++#define BODSE 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++#define OCR0A _SFR_IO8(0x36) ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define RSIG 5 ++#define CTPB 4 ++#define RFLB 3 ++#define PGWRT 2 ++#define PGERS 1 ++#define SPMEN 0 ++ ++#define TIFR0 _SFR_IO8(0x38) ++#define OCF0B 2 ++#define OCF0A 1 ++#define TOV0 0 ++ ++#define TIMSK0 _SFR_IO8(0x39) ++#define OCIE0B 2 ++#define OCIE0A 1 ++#define TOIE0 0 ++ ++#define GIFR _SFR_IO8(0x3A) ++#define INTF0 6 ++#define PCIF1 5 ++#define PCIF0 4 ++ ++#define GIMSK _SFR_IO8(0x3B) ++#define INT0 6 ++#define PCIE1 5 ++#define PCIE0 4 ++ ++#define OCR0B _SFR_IO8(0x3C) ++ ++/* 0x3D..0x3E SP [defined in ] */ ++/* 0x3F SREG [defined in ] */ ++ ++///--- ++ ++/* Interrupt vectors */ ++/* Interrupt vector 0 is the reset vector. */ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define EXT_INT0_vect_num 1 ++#define EXT_INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) ++#define SIG_PIN_CHANGE0 _VECTOR(2) ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect_num 3 ++#define PCINT1_vect _VECTOR(3) ++#define SIG_PIN_CHANGE1 _VECTOR(3) ++ ++/* Watchdog Time-out */ ++#define WDT_vect_num 4 ++#define WDT_vect _VECTOR(4) ++#define WATCHDOG_vect_num 4 ++#define WATCHDOG_vect _VECTOR(4) ++#define SIG_WATCHDOG_TIMEOUT _VECTOR(4) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 5 ++#define TIMER1_CAPT_vect _VECTOR(5) ++#define TIM1_CAPT_vect_num 5 ++#define TIM1_CAPT_vect _VECTOR(5) ++#define SIG_INPUT_CAPTURE1 _VECTOR(5) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIM1_COMPA_vect_num 6 ++#define TIM1_COMPA_vect _VECTOR(6) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(6) ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIM1_COMPB_vect_num 7 ++#define TIM1_COMPB_vect _VECTOR(7) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(7) ++ ++/* Timer/Counter1 Overflow */ ++#define TIM1_OVF_vect_num 8 ++#define TIM1_OVF_vect _VECTOR(8) ++#define SIG_OVERFLOW1 _VECTOR(8) ++ ++/* Timer/Counter0 Compare Match A */ ++#define TIM0_COMPA_vect_num 9 ++#define TIM0_COMPA_vect _VECTOR(9) ++#define SIG_OUTPUT_COMPARE0A _VECTOR(9) ++ ++/* Timer/Counter0 Compare Match B */ ++#define TIM0_COMPB_vect_num 10 ++#define TIM0_COMPB_vect _VECTOR(10) ++#define SIG_OUTPUT_COMPARE0B _VECTOR(10) ++ ++/* Timer/Counter0 Overflow */ ++#define TIM0_OVF_vect_num 11 ++#define TIM0_OVF_vect _VECTOR(11) ++#define SIG_OVERFLOW0 _VECTOR(11) ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect_num 12 ++#define ANA_COMP_vect _VECTOR(12) ++#define SIG_COMPARATOR _VECTOR(12) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 13 ++#define ADC_vect _VECTOR(13) ++#define SIG_ADC _VECTOR(13) ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect_num 14 ++#define EE_RDY_vect _VECTOR(14) ++#define SIG_EEPROM_READY _VECTOR(14) ++ ++/* USI START */ ++#define USI_START_vect_num 15 ++#define USI_START_vect _VECTOR(15) ++#define USI_STR_vect_num 15 ++#define USI_STR_vect _VECTOR(15) ++#define SIG_USI_START _VECTOR(15) ++ ++/* USI Overflow */ ++#define USI_OVF_vect_num 16 ++#define USI_OVF_vect _VECTOR(16) ++#define SIG_USI_OVERFLOW _VECTOR(16) ++ ++#define _VECTORS_SIZE 34 ++ ++#endif /* _AVR_IOTNX4_H_ */ +diff --git a/include/avr/iotnx5.h b/include/avr/iotnx5.h +index 49ec56b..9af2984 100644 +--- a/include/avr/iotnx5.h ++++ b/include/avr/iotnx5.h +@@ -1,436 +1,436 @@ +-/* Copyright (c) 2005,2007 Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotnx5.h 2269 2011-12-29 08:07:25Z joerg_wunsch $ */ +- +-/* avr/iotnx5.h - definitions for ATtiny25, ATtiny45 and ATtiny85 */ +- +-#ifndef _AVR_IOTNX5_H_ +-#define _AVR_IOTNX5_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotnx5.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* I/O registers */ +- +-/* Reserved [0x00..0x02] */ +- +-#define ADCSRB _SFR_IO8 (0x03) +-#define BIN 7 +-#define ACME 6 +-#define IPR 5 +-#define ADTS2 2 +-#define ADTS1 1 +-#define ADTS0 0 +- +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x04) +-#endif +-#define ADCW _SFR_IO16(0x04) +-#define ADCL _SFR_IO8(0x04) +-#define ADCH _SFR_IO8(0x05) +- +-#define ADCSRA _SFR_IO8 (0x06) +-#define ADEN 7 +-#define ADSC 6 +-#define ADATE 5 +-#define ADIF 4 +-#define ADIE 3 +-#define ADPS2 2 +-#define ADPS1 1 +-#define ADPS0 0 +- +-#define ADMUX _SFR_IO8(0x07) +-#define REFS1 7 +-#define REFS0 6 +-#define ADLAR 5 +-#define REFS2 4 +-#define MUX3 3 +-#define MUX2 2 +-#define MUX1 1 +-#define MUX0 0 +- +-#define ACSR _SFR_IO8(0x08) +-#define ACD 7 +-#define ACBG 6 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIS1 1 +-#define ACIS0 0 +- +-/* Reserved [0x09..0x0C] */ +- +-#define USICR _SFR_IO8(0x0D) +-#define USISIE 7 +-#define USIOIE 6 +-#define USIWM1 5 +-#define USIWM0 4 +-#define USICS1 3 +-#define USICS0 2 +-#define USICLK 1 +-#define USITC 0 +- +-#define USISR _SFR_IO8(0x0E) +-#define USISIF 7 +-#define USIOIF 6 +-#define USIPF 5 +-#define USIDC 4 +-#define USICNT3 3 +-#define USICNT2 2 +-#define USICNT1 1 +-#define USICNT0 0 +- +-#define USIDR _SFR_IO8(0x0F) +-#define USIBR _SFR_IO8(0x10) +- +-#define GPIOR0 _SFR_IO8(0x11) +-#define GPIOR1 _SFR_IO8(0x12) +-#define GPIOR2 _SFR_IO8(0x13) +- +-#define DIDR0 _SFR_IO8(0x14) +-#define ADC0D 5 +-#define ADC2D 4 +-#define ADC3D 3 +-#define ADC1D 2 +-#define AIN1D 1 +-#define AIN0D 0 +- +-#define PCMSK _SFR_IO8(0x15) +-#define PCINT5 5 +-#define PCINT4 4 +-#define PCINT3 3 +-#define PCINT2 2 +-#define PCINT1 1 +-#define PCINT0 0 +- +-#define PINB _SFR_IO8(0x16) +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-#define DDRB _SFR_IO8(0x17) +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-#define PORTB _SFR_IO8(0x18) +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-/* Reserved [0x19..0x1B] */ +- +-/* EEPROM Control Register EECR */ +-#define EECR _SFR_IO8(0x1C) +-#define EEPM1 5 +-#define EEPM0 4 +-#define EERIE 3 +-#define EEMPE 2 +-#define EEPE 1 +-#define EERE 0 +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO16(0x1E) +-#define EEARL _SFR_IO8(0x1E) +-#define EEARH _SFR_IO8(0x1F) +- +-#define PRR _SFR_IO8(0x20) +-#define PRTIM1 3 +-#define PRTIM0 2 +-#define PRUSI 1 +-#define PRADC 0 +- +-#define WDTCR _SFR_IO8(0x21) +-#define WDIF 7 +-#define WDIE 6 +-#define WDP3 5 +-#define WDCE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-#define DWDR _SFR_IO8(0x22) +- +-#define DTPS1 _SFR_IO8(0x23) +-#define DTPS11 1 +-#define DTPS10 0 +- +-#define DT1B _SFR_IO8(0x24) +-#define DT1BH3 7 +-#define DT1BH2 6 +-#define DT1BH1 5 +-#define DT1BH0 4 +-#define DT1BL3 3 +-#define DT1BL2 2 +-#define DT1BL1 1 +-#define DT1BL0 0 +- +-#define DT1A _SFR_IO8(0x25) +-#define DT1AH3 7 +-#define DT1AH2 6 +-#define DT1AH1 5 +-#define DT1AH0 4 +-#define DT1AL3 3 +-#define DT1AL2 2 +-#define DT1AL1 1 +-#define DT1AL0 0 +- +-#define CLKPR _SFR_IO8(0x26) +-#define CLKPCE 7 +-#define CLKPS3 3 +-#define CLKPS2 2 +-#define CLKPS1 1 +-#define CLKPS0 0 +- +-#define PLLCSR _SFR_IO8(0x27) +-#define LSM 7 +-#define PCKE 2 +-#define PLLE 1 +-#define PLOCK 0 +- +-#define OCR0B _SFR_IO8(0x28) +- +-#define OCR0A _SFR_IO8(0x29) +- +-#define TCCR0A _SFR_IO8(0x2A) +-#define COM0A1 7 +-#define COM0A0 6 +-#define COM0B1 5 +-#define COM0B0 4 +-#define WGM01 1 +-#define WGM00 0 +- +-#define OCR1B _SFR_IO8(0x2B) +- +-#define GTCCR _SFR_IO8(0x2C) +-#define TSM 7 +-#define PWM1B 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define FOC1B 3 +-#define FOC1A 2 +-#define PSR1 1 +-#define PSR0 0 +- +-#define OCR1C _SFR_IO8(0x2D) +- +-#define OCR1A _SFR_IO8(0x2E) +- +-#define TCNT1 _SFR_IO8(0x2F) +- +-#define TCCR1 _SFR_IO8(0x30) +-#define CTC1 7 +-#define PWM1A 6 +-#define COM1A1 5 +-#define COM1A0 4 +-#define CS13 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-#define OSCCAL _SFR_IO8(0x31) +- +-#define TCNT0 _SFR_IO8(0x32) +- +-#define TCCR0B _SFR_IO8(0x33) +-#define FOC0A 7 +-#define FOC0B 6 +-#define WGM02 3 +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-#define MCUSR _SFR_IO8(0x34) +-#define WDRF 3 +-#define BORF 2 +-#define EXTRF 1 +-#define PORF 0 +- +-#define MCUCR _SFR_IO8(0x35) +-#define BODS 7 +-#define PUD 6 +-#define SE 5 +-#define SM1 4 +-#define SM0 3 +-#define BODSE 2 +-#define ISC01 1 +-#define ISC00 0 +- +-/* Reserved [0x36] */ +- +-#define SPMCSR _SFR_IO8(0x37) +-#define RSIG 5 +-#define CTPB 4 +-#define RFLB 3 +-#define PGWRT 2 +-#define PGERS 1 +-#define SPMEN 0 +- +-#define TIFR _SFR_IO8(0x38) +-#define OCF1A 6 +-#define OCF1B 5 +-#define OCF0A 4 +-#define OCF0B 3 +-#define TOV1 2 +-#define TOV0 1 +- +-#define TIMSK _SFR_IO8(0x39) +-#define OCIE1A 6 +-#define OCIE1B 5 +-#define OCIE0A 4 +-#define OCIE0B 3 +-#define TOIE1 2 +-#define TOIE0 1 +- +-#define GIFR _SFR_IO8(0x3A) +-#define INTF0 6 +-#define PCIF 5 +- +-#define GIMSK _SFR_IO8(0x3B) +-#define INT0 6 +-#define PCIE 5 +- +-/* Reserved [0x3C] */ +- +-/* 0x3D..0x3E SP [defined in ] */ +-/* 0x3F SREG [defined in ] */ +- +-///--- +- +-/* Interrupt vectors */ +-/* Interrupt vector 0 is the reset vector. */ +-/* External Interrupt 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* Pin change Interrupt Request 0 */ +-#define PCINT0_vect_num 2 +-#define PCINT0_vect _VECTOR(2) +-#define SIG_PIN_CHANGE _VECTOR(2) +- +-/* Timer/Counter1 Compare Match 1A */ +-#define TIM1_COMPA_vect_num 3 +-#define TIM1_COMPA_vect _VECTOR(3) +-#define TIMER1_COMPA_vect_num 3 +-#define TIMER1_COMPA_vect _VECTOR(3) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(3) +- +-/* Timer/Counter1 Overflow */ +-#define TIM1_OVF_vect_num 4 +-#define TIM1_OVF_vect _VECTOR(4) +-#define TIMER1_OVF_vect_num 4 +-#define TIMER1_OVF_vect _VECTOR(4) +-#define SIG_OVERFLOW1 _VECTOR(4) +- +-/* Timer/Counter0 Overflow */ +-#define TIM0_OVF_vect_num 5 +-#define TIM0_OVF_vect _VECTOR(5) +-#define TIMER0_OVF_vect_num 5 +-#define TIMER0_OVF_vect _VECTOR(5) +-#define SIG_OVERFLOW0 _VECTOR(5) +- +-/* EEPROM Ready */ +-#define EE_RDY_vect_num 6 +-#define EE_RDY_vect _VECTOR(6) +-#define SIG_EEPROM_READY _VECTOR(6) +- +-/* Analog comparator */ +-#define ANA_COMP_vect_num 7 +-#define ANA_COMP_vect _VECTOR(7) +-#define SIG_COMPARATOR _VECTOR(7) +- +-/* ADC Conversion ready */ +-#define ADC_vect_num 8 +-#define ADC_vect _VECTOR(8) +-#define SIG_ADC _VECTOR(8) +- +-/* Timer/Counter1 Compare Match B */ +-#define TIM1_COMPB_vect_num 9 +-#define TIM1_COMPB_vect _VECTOR(9) +-#define TIMER1_COMPB_vect_num 9 +-#define TIMER1_COMPB_vect _VECTOR(9) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(9) +- +-/* Timer/Counter0 Compare Match A */ +-#define TIM0_COMPA_vect_num 10 +-#define TIM0_COMPA_vect _VECTOR(10) +-#define TIMER0_COMPA_vect_num 10 +-#define TIMER0_COMPA_vect _VECTOR(10) +-#define SIG_OUTPUT_COMPARE0A _VECTOR(10) +- +-/* Timer/Counter0 Compare Match B */ +-#define TIM0_COMPB_vect_num 11 +-#define TIM0_COMPB_vect _VECTOR(11) +-#define TIMER0_COMPB_vect_num 11 +-#define TIMER0_COMPB_vect _VECTOR(11) +-#define SIG_OUTPUT_COMPARE0B _VECTOR(11) +- +-/* Watchdog Time-out */ +-#define WDT_vect_num 12 +-#define WDT_vect _VECTOR(12) +-#define SIG_WATCHDOG_TIMEOUT _VECTOR(12) +- +-/* USI START */ +-#define USI_START_vect_num 13 +-#define USI_START_vect _VECTOR(13) +-#define SIG_USI_START _VECTOR(13) +- +-/* USI Overflow */ +-#define USI_OVF_vect_num 14 +-#define USI_OVF_vect _VECTOR(14) +-#define SIG_USI_OVERFLOW _VECTOR(14) +- +-#define _VECTORS_SIZE 30 +- +-#endif /* _AVR_IOTNX5_H_ */ ++/* Copyright (c) 2005,2007 Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotnx5.h 2269 2011-12-29 08:07:25Z joerg_wunsch $ */ ++ ++/* avr/iotnx5.h - definitions for ATtiny25, ATtiny45 and ATtiny85 */ ++ ++#ifndef _AVR_IOTNX5_H_ ++#define _AVR_IOTNX5_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotnx5.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* I/O registers */ ++ ++/* Reserved [0x00..0x02] */ ++ ++#define ADCSRB _SFR_IO8 (0x03) ++#define BIN 7 ++#define ACME 6 ++#define IPR 5 ++#define ADTS2 2 ++#define ADTS1 1 ++#define ADTS0 0 ++ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++#define ADCW _SFR_IO16(0x04) ++#define ADCL _SFR_IO8(0x04) ++#define ADCH _SFR_IO8(0x05) ++ ++#define ADCSRA _SFR_IO8 (0x06) ++#define ADEN 7 ++#define ADSC 6 ++#define ADATE 5 ++#define ADIF 4 ++#define ADIE 3 ++#define ADPS2 2 ++#define ADPS1 1 ++#define ADPS0 0 ++ ++#define ADMUX _SFR_IO8(0x07) ++#define REFS1 7 ++#define REFS0 6 ++#define ADLAR 5 ++#define REFS2 4 ++#define MUX3 3 ++#define MUX2 2 ++#define MUX1 1 ++#define MUX0 0 ++ ++#define ACSR _SFR_IO8(0x08) ++#define ACD 7 ++#define ACBG 6 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++/* Reserved [0x09..0x0C] */ ++ ++#define USICR _SFR_IO8(0x0D) ++#define USISIE 7 ++#define USIOIE 6 ++#define USIWM1 5 ++#define USIWM0 4 ++#define USICS1 3 ++#define USICS0 2 ++#define USICLK 1 ++#define USITC 0 ++ ++#define USISR _SFR_IO8(0x0E) ++#define USISIF 7 ++#define USIOIF 6 ++#define USIPF 5 ++#define USIDC 4 ++#define USICNT3 3 ++#define USICNT2 2 ++#define USICNT1 1 ++#define USICNT0 0 ++ ++#define USIDR _SFR_IO8(0x0F) ++#define USIBR _SFR_IO8(0x10) ++ ++#define GPIOR0 _SFR_IO8(0x11) ++#define GPIOR1 _SFR_IO8(0x12) ++#define GPIOR2 _SFR_IO8(0x13) ++ ++#define DIDR0 _SFR_IO8(0x14) ++#define ADC0D 5 ++#define ADC2D 4 ++#define ADC3D 3 ++#define ADC1D 2 ++#define AIN1D 1 ++#define AIN0D 0 ++ ++#define PCMSK _SFR_IO8(0x15) ++#define PCINT5 5 ++#define PCINT4 4 ++#define PCINT3 3 ++#define PCINT2 2 ++#define PCINT1 1 ++#define PCINT0 0 ++ ++#define PINB _SFR_IO8(0x16) ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x17) ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++#define PORTB _SFR_IO8(0x18) ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++/* Reserved [0x19..0x1B] */ ++ ++/* EEPROM Control Register EECR */ ++#define EECR _SFR_IO8(0x1C) ++#define EEPM1 5 ++#define EEPM0 4 ++#define EERIE 3 ++#define EEMPE 2 ++#define EEPE 1 ++#define EERE 0 ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO16(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++#define EEARH _SFR_IO8(0x1F) ++ ++#define PRR _SFR_IO8(0x20) ++#define PRTIM1 3 ++#define PRTIM0 2 ++#define PRUSI 1 ++#define PRADC 0 ++ ++#define WDTCR _SFR_IO8(0x21) ++#define WDIF 7 ++#define WDIE 6 ++#define WDP3 5 ++#define WDCE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++#define DWDR _SFR_IO8(0x22) ++ ++#define DTPS1 _SFR_IO8(0x23) ++#define DTPS11 1 ++#define DTPS10 0 ++ ++#define DT1B _SFR_IO8(0x24) ++#define DT1BH3 7 ++#define DT1BH2 6 ++#define DT1BH1 5 ++#define DT1BH0 4 ++#define DT1BL3 3 ++#define DT1BL2 2 ++#define DT1BL1 1 ++#define DT1BL0 0 ++ ++#define DT1A _SFR_IO8(0x25) ++#define DT1AH3 7 ++#define DT1AH2 6 ++#define DT1AH1 5 ++#define DT1AH0 4 ++#define DT1AL3 3 ++#define DT1AL2 2 ++#define DT1AL1 1 ++#define DT1AL0 0 ++ ++#define CLKPR _SFR_IO8(0x26) ++#define CLKPCE 7 ++#define CLKPS3 3 ++#define CLKPS2 2 ++#define CLKPS1 1 ++#define CLKPS0 0 ++ ++#define PLLCSR _SFR_IO8(0x27) ++#define LSM 7 ++#define PCKE 2 ++#define PLLE 1 ++#define PLOCK 0 ++ ++#define OCR0B _SFR_IO8(0x28) ++ ++#define OCR0A _SFR_IO8(0x29) ++ ++#define TCCR0A _SFR_IO8(0x2A) ++#define COM0A1 7 ++#define COM0A0 6 ++#define COM0B1 5 ++#define COM0B0 4 ++#define WGM01 1 ++#define WGM00 0 ++ ++#define OCR1B _SFR_IO8(0x2B) ++ ++#define GTCCR _SFR_IO8(0x2C) ++#define TSM 7 ++#define PWM1B 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define FOC1B 3 ++#define FOC1A 2 ++#define PSR1 1 ++#define PSR0 0 ++ ++#define OCR1C _SFR_IO8(0x2D) ++ ++#define OCR1A _SFR_IO8(0x2E) ++ ++#define TCNT1 _SFR_IO8(0x2F) ++ ++#define TCCR1 _SFR_IO8(0x30) ++#define CTC1 7 ++#define PWM1A 6 ++#define COM1A1 5 ++#define COM1A0 4 ++#define CS13 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++#define OSCCAL _SFR_IO8(0x31) ++ ++#define TCNT0 _SFR_IO8(0x32) ++ ++#define TCCR0B _SFR_IO8(0x33) ++#define FOC0A 7 ++#define FOC0B 6 ++#define WGM02 3 ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define WDRF 3 ++#define BORF 2 ++#define EXTRF 1 ++#define PORF 0 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define BODS 7 ++#define PUD 6 ++#define SE 5 ++#define SM1 4 ++#define SM0 3 ++#define BODSE 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define RSIG 5 ++#define CTPB 4 ++#define RFLB 3 ++#define PGWRT 2 ++#define PGERS 1 ++#define SPMEN 0 ++ ++#define TIFR _SFR_IO8(0x38) ++#define OCF1A 6 ++#define OCF1B 5 ++#define OCF0A 4 ++#define OCF0B 3 ++#define TOV1 2 ++#define TOV0 1 ++ ++#define TIMSK _SFR_IO8(0x39) ++#define OCIE1A 6 ++#define OCIE1B 5 ++#define OCIE0A 4 ++#define OCIE0B 3 ++#define TOIE1 2 ++#define TOIE0 1 ++ ++#define GIFR _SFR_IO8(0x3A) ++#define INTF0 6 ++#define PCIF 5 ++ ++#define GIMSK _SFR_IO8(0x3B) ++#define INT0 6 ++#define PCIE 5 ++ ++/* Reserved [0x3C] */ ++ ++/* 0x3D..0x3E SP [defined in ] */ ++/* 0x3F SREG [defined in ] */ ++ ++///--- ++ ++/* Interrupt vectors */ ++/* Interrupt vector 0 is the reset vector. */ ++/* External Interrupt 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* Pin change Interrupt Request 0 */ ++#define PCINT0_vect_num 2 ++#define PCINT0_vect _VECTOR(2) ++#define SIG_PIN_CHANGE _VECTOR(2) ++ ++/* Timer/Counter1 Compare Match 1A */ ++#define TIM1_COMPA_vect_num 3 ++#define TIM1_COMPA_vect _VECTOR(3) ++#define TIMER1_COMPA_vect_num 3 ++#define TIMER1_COMPA_vect _VECTOR(3) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(3) ++ ++/* Timer/Counter1 Overflow */ ++#define TIM1_OVF_vect_num 4 ++#define TIM1_OVF_vect _VECTOR(4) ++#define TIMER1_OVF_vect_num 4 ++#define TIMER1_OVF_vect _VECTOR(4) ++#define SIG_OVERFLOW1 _VECTOR(4) ++ ++/* Timer/Counter0 Overflow */ ++#define TIM0_OVF_vect_num 5 ++#define TIM0_OVF_vect _VECTOR(5) ++#define TIMER0_OVF_vect_num 5 ++#define TIMER0_OVF_vect _VECTOR(5) ++#define SIG_OVERFLOW0 _VECTOR(5) ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect_num 6 ++#define EE_RDY_vect _VECTOR(6) ++#define SIG_EEPROM_READY _VECTOR(6) ++ ++/* Analog comparator */ ++#define ANA_COMP_vect_num 7 ++#define ANA_COMP_vect _VECTOR(7) ++#define SIG_COMPARATOR _VECTOR(7) ++ ++/* ADC Conversion ready */ ++#define ADC_vect_num 8 ++#define ADC_vect _VECTOR(8) ++#define SIG_ADC _VECTOR(8) ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIM1_COMPB_vect_num 9 ++#define TIM1_COMPB_vect _VECTOR(9) ++#define TIMER1_COMPB_vect_num 9 ++#define TIMER1_COMPB_vect _VECTOR(9) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(9) ++ ++/* Timer/Counter0 Compare Match A */ ++#define TIM0_COMPA_vect_num 10 ++#define TIM0_COMPA_vect _VECTOR(10) ++#define TIMER0_COMPA_vect_num 10 ++#define TIMER0_COMPA_vect _VECTOR(10) ++#define SIG_OUTPUT_COMPARE0A _VECTOR(10) ++ ++/* Timer/Counter0 Compare Match B */ ++#define TIM0_COMPB_vect_num 11 ++#define TIM0_COMPB_vect _VECTOR(11) ++#define TIMER0_COMPB_vect_num 11 ++#define TIMER0_COMPB_vect _VECTOR(11) ++#define SIG_OUTPUT_COMPARE0B _VECTOR(11) ++ ++/* Watchdog Time-out */ ++#define WDT_vect_num 12 ++#define WDT_vect _VECTOR(12) ++#define SIG_WATCHDOG_TIMEOUT _VECTOR(12) ++ ++/* USI START */ ++#define USI_START_vect_num 13 ++#define USI_START_vect _VECTOR(13) ++#define SIG_USI_START _VECTOR(13) ++ ++/* USI Overflow */ ++#define USI_OVF_vect_num 14 ++#define USI_OVF_vect _VECTOR(14) ++#define SIG_USI_OVERFLOW _VECTOR(14) ++ ++#define _VECTORS_SIZE 30 ++ ++#endif /* _AVR_IOTNX5_H_ */ +diff --git a/include/avr/iotnx61.h b/include/avr/iotnx61.h +index 630a8bd..156db42 100644 +--- a/include/avr/iotnx61.h ++++ b/include/avr/iotnx61.h +@@ -1,535 +1,535 @@ +-/* Copyright (c) 2006, 2007 Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iotnx61.h 2247 2011-05-23 19:39:56Z joerg_wunsch $ */ +- +-/* avr/iotnx61.h - definitions for ATtiny261, ATtiny461 and ATtiny861 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iotnx61.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-#ifndef _AVR_IOTNx61_H_ +-#define _AVR_IOTNx61_H_ 1 +- +-/* Registers and associated bit numbers */ +- +-#define TCCR1E _SFR_IO8(0x00) +-#define OC1OE0 0 +-#define OC1OE1 1 +-#define OC1OE2 2 +-#define OC1OE3 3 +-#define OC1OE4 4 +-#define OC1OE5 5 +- +-#define DIDR0 _SFR_IO8(0x01) +-#define ADC0D 0 +-#define ADC1D 1 +-#define ADC2D 2 +-#define AREFD 3 +-#define ADC3D 4 +-#define ADC4D 5 +-#define ADC5D 6 +-#define ADC6D 7 +- +-#define DIDR1 _SFR_IO8(0x02) +-#define ADC7D 4 +-#define ADC8D 5 +-#define ADC9D 6 +-#define ADC10D 7 +- +-#define ADCSRB _SFR_IO8(0x03) +-#define ADTS0 0 +-#define ADTS1 1 +-#define ADTS2 2 +-#define MUX5 3 +-#define REFS2 4 +-#define IRP 5 +-#define GSEL 6 +-#define BIN 7 +- +-#define ADCW _SFR_IO16(0x04) +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_IO16(0x04) +-#endif +- +-#define ADCL _SFR_IO8(0x04) +-#define ADCH _SFR_IO8(0x05) +- +-#define ADCSRA _SFR_IO8(0x06) +-#define ADPS0 0 +-#define ADPS1 1 +-#define ADPS2 2 +-#define ADIE 3 +-#define ADIF 4 +-#define ADATE 5 +-#define ADSC 6 +-#define ADEN 7 +- +-#define ADMUX _SFR_IO8(0x07) +-#define MUX0 0 +-#define MUX1 1 +-#define MUX2 2 +-#define MUX3 3 +-#define MUX4 4 +-#define ADLAR 5 +-#define REFS0 6 +-#define REFS1 7 +- +-#define ACSRA _SFR_IO8(0x08) +-#define ACIS0 0 +-#define ACIS1 1 +-#define ACME 2 +-#define ACIE 3 +-#define ACI 4 +-#define ACO 5 +-#define ACBG 6 +-#define ACD 7 +- +-#define ACSRB _SFR_IO8(0x09) +-#define ACM0 0 +-#define ACM1 1 +-#define ACM2 2 +-#define HLEV 6 +-#define HSEL 7 +- +-#define GPIOR0 _SFR_IO8(0x0A) +- +-#define GPIOR1 _SFR_IO8(0x0B) +- +-#define GPIOR2 _SFR_IO8(0x0C) +- +-#define USICR _SFR_IO8(0x0D) +-#define USITC 0 +-#define USICLK 1 +-#define USICS0 2 +-#define USICS1 3 +-#define USIWM0 4 +-#define USIWM1 5 +-#define USIOIE 6 +-#define USISIE 7 +- +-#define USISR _SFR_IO8(0x0E) +-#define USICNT0 0 +-#define USICNT1 1 +-#define USICNT2 2 +-#define USICNT3 3 +-#define USIDC 4 +-#define USIPF 5 +-#define USIOIF 6 +-#define USISIF 7 +- +-#define USIDR _SFR_IO8(0x0F) +- +-#define USIBR _SFR_IO8(0x10) +- +-#define USIPP _SFR_IO8(0x11) +-#define USIPOS 0 +- +-#define OCR0B _SFR_IO8(0x12) +- +-#define OCR0A _SFR_IO8(0x13) +- +-#define TCNT0H _SFR_IO8(0x14) +- +-#define TCCR0A _SFR_IO8(0x15) +-#define WGM00 0 /* up to at least datasheet rev. B */ +-#define CTC0 0 /* newer revisions; change not mentioned +- * in revision history */ +-#define ACIC0 3 +-#define ICES0 4 +-#define ICNC0 5 +-#define ICEN0 6 +-#define TCW0 7 +- +-#define PINB _SFR_IO8(0x16) +-#define PINB0 0 +-#define PINB1 1 +-#define PINB2 2 +-#define PINB3 3 +-#define PINB4 4 +-#define PINB5 5 +-#define PINB6 6 +-#define PINB7 7 +- +-#define DDRB _SFR_IO8(0x17) +-#define DDB0 0 +-#define DDB1 1 +-#define DDB2 2 +-#define DDB3 3 +-#define DDB4 4 +-#define DDB5 5 +-#define DDB6 6 +-#define DDB7 7 +- +-#define PORTB _SFR_IO8(0x18) +-#define PB0 0 +-#define PB1 1 +-#define PB2 2 +-#define PB3 3 +-#define PB4 4 +-#define PB5 5 +-#define PB6 6 +-#define PB7 7 +- +-#define PINA _SFR_IO8(0x19) +-#define PINA0 0 +-#define PINA1 1 +-#define PINA2 2 +-#define PINA3 3 +-#define PINA4 4 +-#define PINA5 5 +-#define PINA6 6 +-#define PINA7 7 +- +-#define DDRA _SFR_IO8(0x1A) +-#define DDA0 0 +-#define DDA1 1 +-#define DDA2 2 +-#define DDA3 3 +-#define DDA4 4 +-#define DDA5 5 +-#define DDA6 6 +-#define DDA7 7 +- +-#define PORTA _SFR_IO8(0x1B) +-#define PA0 0 +-#define PA1 1 +-#define PA2 2 +-#define PA3 3 +-#define PA4 4 +-#define PA5 5 +-#define PA6 6 +-#define PA7 7 +- +-/* EEPROM Control Register */ +-#define EECR _SFR_IO8(0x1C) +-#define EERE 0 +-#define EEPE 1 +-#define EEMPE 2 +-#define EERIE 3 +-#define EEPM0 4 +-#define EEPM1 5 +- +-/* EEPROM Data Register */ +-#define EEDR _SFR_IO8(0x1D) +- +-/* EEPROM Address Register */ +-#define EEAR _SFR_IO16(0x1E) +-#define EEARL _SFR_IO8(0x1E) +-#define EEARH _SFR_IO8(0x1F) +- +-#define DWDR _SFR_IO8(0x20) +- +-#define WDTCR _SFR_IO8(0x21) +-#define WDP0 0 +-#define WDP1 1 +-#define WDP2 2 +-#define WDE 3 +-#define WDCE 4 +-#define WDP3 5 +-#define WDIE 6 +-#define WDIF 7 +- +-#define PCMSK1 _SFR_IO8(0x22) +-#define PCINT8 0 +-#define PCINT9 1 +-#define PCINT10 2 +-#define PCINT11 3 +-#define PCINT12 4 +-#define PCINT13 5 +-#define PCINT14 6 +-#define PCINT15 7 +- +-#define PCMSK0 _SFR_IO8(0x23) +-#define PCINT0 0 +-#define PCINT1 1 +-#define PCINT2 2 +-#define PCINT3 3 +-#define PCINT4 4 +-#define PCINT5 5 +-#define PCINT6 6 +-#define PCINT7 7 +- +-#define DT1 _SFR_IO8(0x24) +-#define DT1L0 0 +-#define DT1L1 1 +-#define DT1L2 2 +-#define DT1L3 3 +-#define DT1H0 4 +-#define DT1H1 5 +-#define DT1H2 6 +-#define DT1H3 7 +- +-#define TC1H _SFR_IO8(0x25) +-#define TC18 0 +-#define TC19 1 +- +-#define TCCR1D _SFR_IO8(0x26) +-#define WGM10 0 +-#define WGM11 1 +-#define FPF1 2 +-#define FPAC1 3 +-#define FPES1 4 +-#define FPNC1 5 +-#define FPEN1 6 +-#define FPIE1 7 +- +-#define TCCR1C _SFR_IO8(0x27) +-#define PWM1D 0 +-#define FOC1D 1 +-#define COM1D0 2 +-#define COM1D1 3 +-#define COM1B0S 4 +-#define COM1B1S 5 +-#define COM1A0S 6 +-#define COM1A1S 7 +- +-#define CLKPR _SFR_IO8(0x28) +-#define CLKPS0 0 +-#define CLKPS1 1 +-#define CLKPS2 2 +-#define CLKPS3 3 +-#define CLKPCE 7 +- +-#define PLLCSR _SFR_IO8(0x29) +-#define PLOCK 0 +-#define PLLE 1 +-#define PCKE 2 +-#define LSM 7 +- +-#define OCR1D _SFR_IO8(0x2A) +- +-#define OCR1C _SFR_IO8(0x2B) +- +-#define OCR1B _SFR_IO8(0x2C) +- +-#define OCR1A _SFR_IO8(0x2D) +- +-#define TCNT1 _SFR_IO8(0x2E) +- +-#define TCCR1B _SFR_IO8(0x2F) +-#define CS10 0 +-#define CS11 1 +-#define CS12 2 +-#define CS13 3 +-#define DTPS10 4 +-#define DTPS11 5 +-#define PSR1 6 +-#define PWM1X 7 +- +-#define TCCR1A _SFR_IO8(0x30) +-#define PWM1B 0 +-#define PWM1A 1 +-#define FOC1B 2 +-#define FOC1A 3 +-#define COM1B0 4 +-#define COM1B1 5 +-#define COM1A0 6 +-#define COM1A1 7 +- +-#define OSCCAL _SFR_IO8(0x31) +- +-#define TCNT0L _SFR_IO8(0x32) +- +-#define TCCR0B _SFR_IO8(0x33) +-#define CS00 0 +-#define CS01 1 +-#define CS02 2 +-#define PSR0 3 +-#define TSM 4 +- +-#define MCUSR _SFR_IO8(0x34) +-#define PORF 0 +-#define EXTRF 1 +-#define BORF 2 +-#define WDRF 3 +- +-#define MCUCR _SFR_IO8(0x35) +-#define ISC00 0 +-#define ISC01 1 +-#define SM0 3 +-#define SM1 4 +-#define SE 5 +-#define PUD 6 +- +-#define PRR _SFR_IO8(0x36) +-#define PRADC 0 +-#define PRUSI 1 +-#define PRTIM0 2 +-#define PRTIM1 3 +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMEN 0 +-#define PGERS 1 +-#define PGWRT 2 +-#define RFLB 3 +-#define CTPB 4 +- +-#define TIFR _SFR_IO8(0x38) +-#define ICF0 0 +-#define TOV0 1 +-#define TOV1 2 +-#define OCF0B 3 +-#define OCF0A 4 +-#define OCF1B 5 +-#define OCF1A 6 +-#define OCF1D 7 +- +-#define TIMSK _SFR_IO8(0x39) +-#define TICIE0 0 +-#define TOIE0 1 +-#define TOIE1 2 +-#define OCIE0B 3 +-#define OCIE0A 4 +-#define OCIE1B 5 +-#define OCIE1A 6 +-#define OCIE1D 7 +- +-#define GIFR _SFR_IO8(0x3A) +-#define PCIF 5 +-#define INTF0 6 +-#define INTF1 7 +- +-#define GIMSK _SFR_IO8(0x3B) +-#define PCIE0 4 +-#define PCIE1 5 +-#define INT0 6 +-#define INT1 7 +- +-/* Reserved [0x3C] */ +- +-/* 0x3D..0x3E SP [defined in ] */ +-/* 0x3F SREG [defined in ] */ +- +- +-/* Interrupt vectors */ +-/* Interrupt vector 0 is the reset vector. */ +-/* External Interrupt 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +-#define SIG_INTERRUPT0 _VECTOR(1) +- +-/* Pin Change Interrupt */ +-#define PCINT_vect_num 2 +-#define PCINT_vect _VECTOR(2) +-#define SIG_PIN_CHANGE _VECTOR(2) +- +-/* Timer/Counter1 Compare Match 1A */ +-#define TIMER1_COMPA_vect_num 3 +-#define TIMER1_COMPA_vect _VECTOR(3) +-#define SIG_OUTPUT_COMPARE1A _VECTOR(3) +- +-/* Timer/Counter1 Compare Match 1B */ +-#define TIMER1_COMPB_vect_num 4 +-#define TIMER1_COMPB_vect _VECTOR(4) +-#define SIG_OUTPUT_COMPARE1B _VECTOR(4) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 5 +-#define TIMER1_OVF_vect _VECTOR(5) +-#define SIG_OVERFLOW1 _VECTOR(5) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 6 +-#define TIMER0_OVF_vect _VECTOR(6) +-#define SIG_OVERFLOW0 _VECTOR(6) +- +-/* USI Start */ +-#define USI_START_vect_num 7 +-#define USI_START_vect _VECTOR(7) +-#define SIG_USI_START _VECTOR(7) +- +-/* USI Overflow */ +-#define USI_OVF_vect_num 8 +-#define USI_OVF_vect _VECTOR(8) +-#define SIG_USI_OVERFLOW _VECTOR(8) +- +-/* EEPROM Ready */ +-#define EE_RDY_vect_num 9 +-#define EE_RDY_vect _VECTOR(9) +-#define SIG_EEPROM_READY _VECTOR(9) +- +-/* Analog Comparator */ +-#define ANA_COMP_vect_num 10 +-#define ANA_COMP_vect _VECTOR(10) +-#define SIG_ANA_COMP _VECTOR(10) +-#define SIG_COMPARATOR _VECTOR(10) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 11 +-#define ADC_vect _VECTOR(11) +-#define SIG_ADC _VECTOR(11) +- +-/* Watchdog Time-Out */ +-#define WDT_vect_num 12 +-#define WDT_vect _VECTOR(12) +-#define SIG_WDT _VECTOR(12) +- +-/* External Interrupt 1 */ +-#define INT1_vect_num 13 +-#define INT1_vect _VECTOR(13) +-#define SIG_INTERRUPT1 _VECTOR(13) +- +-/* Timer/Counter0 Compare Match A */ +-#define TIMER0_COMPA_vect_num 14 +-#define TIMER0_COMPA_vect _VECTOR(14) +-#define SIG_OUTPUT_COMPARE0A _VECTOR(14) +- +-/* Timer/Counter0 Compare Match B */ +-#define TIMER0_COMPB_vect_num 15 +-#define TIMER0_COMPB_vect _VECTOR(15) +-#define SIG_OUTPUT_COMPARE0B _VECTOR(15) +- +-/* ADC Conversion Complete */ +-#define TIMER0_CAPT_vect_num 16 +-#define TIMER0_CAPT_vect _VECTOR(16) +-#define SIG_INPUT_CAPTURE0 _VECTOR(16) +- +-/* Timer/Counter1 Compare Match D */ +-#define TIMER1_COMPD_vect_num 17 +-#define TIMER1_COMPD_vect _VECTOR(17) +-#define SIG_OUTPUT_COMPARE0D _VECTOR(17) +- +-/* Timer/Counter1 Fault Protection */ +-#define FAULT_PROTECTION_vect_num 18 +-#define FAULT_PROTECTION_vect _VECTOR(18) +- +-#define _VECTORS_SIZE 38 +- +-#endif /* _AVR_IOTNx61_H_ */ ++/* Copyright (c) 2006, 2007 Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iotnx61.h 2247 2011-05-23 19:39:56Z joerg_wunsch $ */ ++ ++/* avr/iotnx61.h - definitions for ATtiny261, ATtiny461 and ATtiny861 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iotnx61.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_IOTNx61_H_ ++#define _AVR_IOTNx61_H_ 1 ++ ++/* Registers and associated bit numbers */ ++ ++#define TCCR1E _SFR_IO8(0x00) ++#define OC1OE0 0 ++#define OC1OE1 1 ++#define OC1OE2 2 ++#define OC1OE3 3 ++#define OC1OE4 4 ++#define OC1OE5 5 ++ ++#define DIDR0 _SFR_IO8(0x01) ++#define ADC0D 0 ++#define ADC1D 1 ++#define ADC2D 2 ++#define AREFD 3 ++#define ADC3D 4 ++#define ADC4D 5 ++#define ADC5D 6 ++#define ADC6D 7 ++ ++#define DIDR1 _SFR_IO8(0x02) ++#define ADC7D 4 ++#define ADC8D 5 ++#define ADC9D 6 ++#define ADC10D 7 ++ ++#define ADCSRB _SFR_IO8(0x03) ++#define ADTS0 0 ++#define ADTS1 1 ++#define ADTS2 2 ++#define MUX5 3 ++#define REFS2 4 ++#define IRP 5 ++#define GSEL 6 ++#define BIN 7 ++ ++#define ADCW _SFR_IO16(0x04) ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_IO16(0x04) ++#endif ++ ++#define ADCL _SFR_IO8(0x04) ++#define ADCH _SFR_IO8(0x05) ++ ++#define ADCSRA _SFR_IO8(0x06) ++#define ADPS0 0 ++#define ADPS1 1 ++#define ADPS2 2 ++#define ADIE 3 ++#define ADIF 4 ++#define ADATE 5 ++#define ADSC 6 ++#define ADEN 7 ++ ++#define ADMUX _SFR_IO8(0x07) ++#define MUX0 0 ++#define MUX1 1 ++#define MUX2 2 ++#define MUX3 3 ++#define MUX4 4 ++#define ADLAR 5 ++#define REFS0 6 ++#define REFS1 7 ++ ++#define ACSRA _SFR_IO8(0x08) ++#define ACIS0 0 ++#define ACIS1 1 ++#define ACME 2 ++#define ACIE 3 ++#define ACI 4 ++#define ACO 5 ++#define ACBG 6 ++#define ACD 7 ++ ++#define ACSRB _SFR_IO8(0x09) ++#define ACM0 0 ++#define ACM1 1 ++#define ACM2 2 ++#define HLEV 6 ++#define HSEL 7 ++ ++#define GPIOR0 _SFR_IO8(0x0A) ++ ++#define GPIOR1 _SFR_IO8(0x0B) ++ ++#define GPIOR2 _SFR_IO8(0x0C) ++ ++#define USICR _SFR_IO8(0x0D) ++#define USITC 0 ++#define USICLK 1 ++#define USICS0 2 ++#define USICS1 3 ++#define USIWM0 4 ++#define USIWM1 5 ++#define USIOIE 6 ++#define USISIE 7 ++ ++#define USISR _SFR_IO8(0x0E) ++#define USICNT0 0 ++#define USICNT1 1 ++#define USICNT2 2 ++#define USICNT3 3 ++#define USIDC 4 ++#define USIPF 5 ++#define USIOIF 6 ++#define USISIF 7 ++ ++#define USIDR _SFR_IO8(0x0F) ++ ++#define USIBR _SFR_IO8(0x10) ++ ++#define USIPP _SFR_IO8(0x11) ++#define USIPOS 0 ++ ++#define OCR0B _SFR_IO8(0x12) ++ ++#define OCR0A _SFR_IO8(0x13) ++ ++#define TCNT0H _SFR_IO8(0x14) ++ ++#define TCCR0A _SFR_IO8(0x15) ++#define WGM00 0 /* up to at least datasheet rev. B */ ++#define CTC0 0 /* newer revisions; change not mentioned ++ * in revision history */ ++#define ACIC0 3 ++#define ICES0 4 ++#define ICNC0 5 ++#define ICEN0 6 ++#define TCW0 7 ++ ++#define PINB _SFR_IO8(0x16) ++#define PINB0 0 ++#define PINB1 1 ++#define PINB2 2 ++#define PINB3 3 ++#define PINB4 4 ++#define PINB5 5 ++#define PINB6 6 ++#define PINB7 7 ++ ++#define DDRB _SFR_IO8(0x17) ++#define DDB0 0 ++#define DDB1 1 ++#define DDB2 2 ++#define DDB3 3 ++#define DDB4 4 ++#define DDB5 5 ++#define DDB6 6 ++#define DDB7 7 ++ ++#define PORTB _SFR_IO8(0x18) ++#define PB0 0 ++#define PB1 1 ++#define PB2 2 ++#define PB3 3 ++#define PB4 4 ++#define PB5 5 ++#define PB6 6 ++#define PB7 7 ++ ++#define PINA _SFR_IO8(0x19) ++#define PINA0 0 ++#define PINA1 1 ++#define PINA2 2 ++#define PINA3 3 ++#define PINA4 4 ++#define PINA5 5 ++#define PINA6 6 ++#define PINA7 7 ++ ++#define DDRA _SFR_IO8(0x1A) ++#define DDA0 0 ++#define DDA1 1 ++#define DDA2 2 ++#define DDA3 3 ++#define DDA4 4 ++#define DDA5 5 ++#define DDA6 6 ++#define DDA7 7 ++ ++#define PORTA _SFR_IO8(0x1B) ++#define PA0 0 ++#define PA1 1 ++#define PA2 2 ++#define PA3 3 ++#define PA4 4 ++#define PA5 5 ++#define PA6 6 ++#define PA7 7 ++ ++/* EEPROM Control Register */ ++#define EECR _SFR_IO8(0x1C) ++#define EERE 0 ++#define EEPE 1 ++#define EEMPE 2 ++#define EERIE 3 ++#define EEPM0 4 ++#define EEPM1 5 ++ ++/* EEPROM Data Register */ ++#define EEDR _SFR_IO8(0x1D) ++ ++/* EEPROM Address Register */ ++#define EEAR _SFR_IO16(0x1E) ++#define EEARL _SFR_IO8(0x1E) ++#define EEARH _SFR_IO8(0x1F) ++ ++#define DWDR _SFR_IO8(0x20) ++ ++#define WDTCR _SFR_IO8(0x21) ++#define WDP0 0 ++#define WDP1 1 ++#define WDP2 2 ++#define WDE 3 ++#define WDCE 4 ++#define WDP3 5 ++#define WDIE 6 ++#define WDIF 7 ++ ++#define PCMSK1 _SFR_IO8(0x22) ++#define PCINT8 0 ++#define PCINT9 1 ++#define PCINT10 2 ++#define PCINT11 3 ++#define PCINT12 4 ++#define PCINT13 5 ++#define PCINT14 6 ++#define PCINT15 7 ++ ++#define PCMSK0 _SFR_IO8(0x23) ++#define PCINT0 0 ++#define PCINT1 1 ++#define PCINT2 2 ++#define PCINT3 3 ++#define PCINT4 4 ++#define PCINT5 5 ++#define PCINT6 6 ++#define PCINT7 7 ++ ++#define DT1 _SFR_IO8(0x24) ++#define DT1L0 0 ++#define DT1L1 1 ++#define DT1L2 2 ++#define DT1L3 3 ++#define DT1H0 4 ++#define DT1H1 5 ++#define DT1H2 6 ++#define DT1H3 7 ++ ++#define TC1H _SFR_IO8(0x25) ++#define TC18 0 ++#define TC19 1 ++ ++#define TCCR1D _SFR_IO8(0x26) ++#define WGM10 0 ++#define WGM11 1 ++#define FPF1 2 ++#define FPAC1 3 ++#define FPES1 4 ++#define FPNC1 5 ++#define FPEN1 6 ++#define FPIE1 7 ++ ++#define TCCR1C _SFR_IO8(0x27) ++#define PWM1D 0 ++#define FOC1D 1 ++#define COM1D0 2 ++#define COM1D1 3 ++#define COM1B0S 4 ++#define COM1B1S 5 ++#define COM1A0S 6 ++#define COM1A1S 7 ++ ++#define CLKPR _SFR_IO8(0x28) ++#define CLKPS0 0 ++#define CLKPS1 1 ++#define CLKPS2 2 ++#define CLKPS3 3 ++#define CLKPCE 7 ++ ++#define PLLCSR _SFR_IO8(0x29) ++#define PLOCK 0 ++#define PLLE 1 ++#define PCKE 2 ++#define LSM 7 ++ ++#define OCR1D _SFR_IO8(0x2A) ++ ++#define OCR1C _SFR_IO8(0x2B) ++ ++#define OCR1B _SFR_IO8(0x2C) ++ ++#define OCR1A _SFR_IO8(0x2D) ++ ++#define TCNT1 _SFR_IO8(0x2E) ++ ++#define TCCR1B _SFR_IO8(0x2F) ++#define CS10 0 ++#define CS11 1 ++#define CS12 2 ++#define CS13 3 ++#define DTPS10 4 ++#define DTPS11 5 ++#define PSR1 6 ++#define PWM1X 7 ++ ++#define TCCR1A _SFR_IO8(0x30) ++#define PWM1B 0 ++#define PWM1A 1 ++#define FOC1B 2 ++#define FOC1A 3 ++#define COM1B0 4 ++#define COM1B1 5 ++#define COM1A0 6 ++#define COM1A1 7 ++ ++#define OSCCAL _SFR_IO8(0x31) ++ ++#define TCNT0L _SFR_IO8(0x32) ++ ++#define TCCR0B _SFR_IO8(0x33) ++#define CS00 0 ++#define CS01 1 ++#define CS02 2 ++#define PSR0 3 ++#define TSM 4 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define PORF 0 ++#define EXTRF 1 ++#define BORF 2 ++#define WDRF 3 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define ISC00 0 ++#define ISC01 1 ++#define SM0 3 ++#define SM1 4 ++#define SE 5 ++#define PUD 6 ++ ++#define PRR _SFR_IO8(0x36) ++#define PRADC 0 ++#define PRUSI 1 ++#define PRTIM0 2 ++#define PRTIM1 3 ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMEN 0 ++#define PGERS 1 ++#define PGWRT 2 ++#define RFLB 3 ++#define CTPB 4 ++ ++#define TIFR _SFR_IO8(0x38) ++#define ICF0 0 ++#define TOV0 1 ++#define TOV1 2 ++#define OCF0B 3 ++#define OCF0A 4 ++#define OCF1B 5 ++#define OCF1A 6 ++#define OCF1D 7 ++ ++#define TIMSK _SFR_IO8(0x39) ++#define TICIE0 0 ++#define TOIE0 1 ++#define TOIE1 2 ++#define OCIE0B 3 ++#define OCIE0A 4 ++#define OCIE1B 5 ++#define OCIE1A 6 ++#define OCIE1D 7 ++ ++#define GIFR _SFR_IO8(0x3A) ++#define PCIF 5 ++#define INTF0 6 ++#define INTF1 7 ++ ++#define GIMSK _SFR_IO8(0x3B) ++#define PCIE0 4 ++#define PCIE1 5 ++#define INT0 6 ++#define INT1 7 ++ ++/* Reserved [0x3C] */ ++ ++/* 0x3D..0x3E SP [defined in ] */ ++/* 0x3F SREG [defined in ] */ ++ ++ ++/* Interrupt vectors */ ++/* Interrupt vector 0 is the reset vector. */ ++/* External Interrupt 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++#define SIG_INTERRUPT0 _VECTOR(1) ++ ++/* Pin Change Interrupt */ ++#define PCINT_vect_num 2 ++#define PCINT_vect _VECTOR(2) ++#define SIG_PIN_CHANGE _VECTOR(2) ++ ++/* Timer/Counter1 Compare Match 1A */ ++#define TIMER1_COMPA_vect_num 3 ++#define TIMER1_COMPA_vect _VECTOR(3) ++#define SIG_OUTPUT_COMPARE1A _VECTOR(3) ++ ++/* Timer/Counter1 Compare Match 1B */ ++#define TIMER1_COMPB_vect_num 4 ++#define TIMER1_COMPB_vect _VECTOR(4) ++#define SIG_OUTPUT_COMPARE1B _VECTOR(4) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 5 ++#define TIMER1_OVF_vect _VECTOR(5) ++#define SIG_OVERFLOW1 _VECTOR(5) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 6 ++#define TIMER0_OVF_vect _VECTOR(6) ++#define SIG_OVERFLOW0 _VECTOR(6) ++ ++/* USI Start */ ++#define USI_START_vect_num 7 ++#define USI_START_vect _VECTOR(7) ++#define SIG_USI_START _VECTOR(7) ++ ++/* USI Overflow */ ++#define USI_OVF_vect_num 8 ++#define USI_OVF_vect _VECTOR(8) ++#define SIG_USI_OVERFLOW _VECTOR(8) ++ ++/* EEPROM Ready */ ++#define EE_RDY_vect_num 9 ++#define EE_RDY_vect _VECTOR(9) ++#define SIG_EEPROM_READY _VECTOR(9) ++ ++/* Analog Comparator */ ++#define ANA_COMP_vect_num 10 ++#define ANA_COMP_vect _VECTOR(10) ++#define SIG_ANA_COMP _VECTOR(10) ++#define SIG_COMPARATOR _VECTOR(10) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 11 ++#define ADC_vect _VECTOR(11) ++#define SIG_ADC _VECTOR(11) ++ ++/* Watchdog Time-Out */ ++#define WDT_vect_num 12 ++#define WDT_vect _VECTOR(12) ++#define SIG_WDT _VECTOR(12) ++ ++/* External Interrupt 1 */ ++#define INT1_vect_num 13 ++#define INT1_vect _VECTOR(13) ++#define SIG_INTERRUPT1 _VECTOR(13) ++ ++/* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPA_vect_num 14 ++#define TIMER0_COMPA_vect _VECTOR(14) ++#define SIG_OUTPUT_COMPARE0A _VECTOR(14) ++ ++/* Timer/Counter0 Compare Match B */ ++#define TIMER0_COMPB_vect_num 15 ++#define TIMER0_COMPB_vect _VECTOR(15) ++#define SIG_OUTPUT_COMPARE0B _VECTOR(15) ++ ++/* ADC Conversion Complete */ ++#define TIMER0_CAPT_vect_num 16 ++#define TIMER0_CAPT_vect _VECTOR(16) ++#define SIG_INPUT_CAPTURE0 _VECTOR(16) ++ ++/* Timer/Counter1 Compare Match D */ ++#define TIMER1_COMPD_vect_num 17 ++#define TIMER1_COMPD_vect _VECTOR(17) ++#define SIG_OUTPUT_COMPARE0D _VECTOR(17) ++ ++/* Timer/Counter1 Fault Protection */ ++#define FAULT_PROTECTION_vect_num 18 ++#define FAULT_PROTECTION_vect _VECTOR(18) ++ ++#define _VECTORS_SIZE 38 ++ ++#endif /* _AVR_IOTNx61_H_ */ +diff --git a/include/avr/iousb1286.h b/include/avr/iousb1286.h +index 7d3d4ec..9f25510 100644 +--- a/include/avr/iousb1286.h ++++ b/include/avr/iousb1286.h +@@ -1,94 +1,95 @@ +-/* Copyright (c) 2006 Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iousb1286.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ +- +-/* avr/iousb1286.h - definitions for AT90USB1286 */ +- +-#ifndef _AVR_AT90USB1286_H_ +-#define _AVR_AT90USB1286_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 256 +-#define RAMEND 0x20FF +-#define XRAMEND 0xFFFF +-#define E2END 0xFFF +-#define E2PAGESIZE 8 +-#define FLASHEND 0x1FFFF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define FUSE_HWBE (unsigned char)~_BV(3) +-#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_HWBE) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x97 +-#define SIGNATURE_2 0x82 +- +- +-#endif /* _AVR_AT90USB1286_H_ */ ++/* Copyright (c) 2006 Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iousb1286.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ ++ ++/* avr/iousb1286.h - definitions for AT90USB1286 */ ++ ++#ifndef _AVR_AT90USB1286_H_ ++#define _AVR_AT90USB1286_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 256 ++#define RAMSTART 0x100 ++#define RAMEND 0x20FF ++#define XRAMEND 0xFFFF ++#define E2END 0xFFF ++#define E2PAGESIZE 8 ++#define FLASHEND 0x1FFFF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_HWBE (unsigned char)~_BV(3) ++#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_HWBE) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x97 ++#define SIGNATURE_2 0x82 ++ ++ ++#endif /* _AVR_AT90USB1286_H_ */ +diff --git a/include/avr/iousb1287.h b/include/avr/iousb1287.h +index 1fe45e1..8ed89a8 100644 +--- a/include/avr/iousb1287.h ++++ b/include/avr/iousb1287.h +@@ -1,94 +1,95 @@ +-/* Copyright (c) 2006 Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iousb1287.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ +- +-/* avr/iousb1287.h - definitions for AT90USB1287 */ +- +-#ifndef _AVR_AT90USB1287_H_ +-#define _AVR_AT90USB1287_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 256 +-#define RAMEND 0x20FF +-#define XRAMEND 0xFFFF +-#define E2END 0xFFF +-#define E2PAGESIZE 8 +-#define FLASHEND 0x1FFFF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define FUSE_HWBE (unsigned char)~_BV(3) +-#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_HWBE) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x97 +-#define SIGNATURE_2 0x82 +- +- +-#endif /* _AVR_AT90USB1287_H_ */ ++/* Copyright (c) 2006 Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iousb1287.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ ++ ++/* avr/iousb1287.h - definitions for AT90USB1287 */ ++ ++#ifndef _AVR_AT90USB1287_H_ ++#define _AVR_AT90USB1287_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 256 ++#define RAMSTART 0x100 ++#define RAMEND 0x20FF ++#define XRAMEND 0xFFFF ++#define E2END 0xFFF ++#define E2PAGESIZE 8 ++#define FLASHEND 0x1FFFF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_HWBE (unsigned char)~_BV(3) ++#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_HWBE) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x97 ++#define SIGNATURE_2 0x82 ++ ++ ++#endif /* _AVR_AT90USB1287_H_ */ +diff --git a/include/avr/iousb162.h b/include/avr/iousb162.h +index e0648bf..d206044 100644 +--- a/include/avr/iousb162.h ++++ b/include/avr/iousb162.h +@@ -1,95 +1,96 @@ +-/* Copyright (c) 2007 Anatoly Sokolov +- Copyright (c) 2010 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iousb162.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ +- +-/* avr/iousb162.h - definitions for AT90USB162 */ +- +-#ifndef _AVR_AT90USB162_H_ +-#define _AVR_AT90USB162_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 128 +-#define RAMEND 0x2FF +-#define XRAMEND RAMEND +-#define E2END 0x1FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x3FFF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_SUT1 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_RSTDSBL (unsigned char)~_BV(6) +-#define FUSE_DWEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define FUSE_HWBE (unsigned char)~_BV(3) +-#define EFUSE_DEFAULT (FUSE_BODLEVEL0 & FUSE_BODLEVEL1 & FUSE_HWBE) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x94 +-#define SIGNATURE_2 0x82 +- +- +-#endif /* _AVR_AT90USB162_H_ */ ++/* Copyright (c) 2007 Anatoly Sokolov ++ Copyright (c) 2010 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iousb162.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ ++ ++/* avr/iousb162.h - definitions for AT90USB162 */ ++ ++#ifndef _AVR_AT90USB162_H_ ++#define _AVR_AT90USB162_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 128 ++#define RAMSTART 0x100 ++#define RAMEND 0x2FF ++#define XRAMEND RAMEND ++#define E2END 0x1FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x3FFF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_SUT1 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_RSTDSBL (unsigned char)~_BV(6) ++#define FUSE_DWEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_HWBE (unsigned char)~_BV(3) ++#define EFUSE_DEFAULT (FUSE_BODLEVEL0 & FUSE_BODLEVEL1 & FUSE_HWBE) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x82 ++ ++ ++#endif /* _AVR_AT90USB162_H_ */ +diff --git a/include/avr/iousb646.h b/include/avr/iousb646.h +index 1dea508..6ca6926 100644 +--- a/include/avr/iousb646.h ++++ b/include/avr/iousb646.h +@@ -1,95 +1,96 @@ +-/* Copyright (c) 2006 Anatoly Sokolov +- Copyright (c) 2010 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iousb646.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ +- +-/* avr/iousb646.h - definitions for AT90USB646 */ +- +-#ifndef _AVR_AT90USB646_H_ +-#define _AVR_AT90USB646_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 256 +-#define RAMEND 0x10FF +-#define XRAMEND 0xFFFF +-#define E2END 0x7FF +-#define E2PAGESIZE 8 +-#define FLASHEND 0xFFFF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define FUSE_HWBE (unsigned char)~_BV(3) +-#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_HWBE) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x96 +-#define SIGNATURE_2 0x82 +- +- +-#endif /* _AVR_AT90USB646_H_ */ ++/* Copyright (c) 2006 Anatoly Sokolov ++ Copyright (c) 2010 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iousb646.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ ++ ++/* avr/iousb646.h - definitions for AT90USB646 */ ++ ++#ifndef _AVR_AT90USB646_H_ ++#define _AVR_AT90USB646_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 256 ++#define RAMSTART 0x100 ++#define RAMEND 0x10FF ++#define XRAMEND 0xFFFF ++#define E2END 0x7FF ++#define E2PAGESIZE 8 ++#define FLASHEND 0xFFFF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_HWBE (unsigned char)~_BV(3) ++#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_HWBE) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x82 ++ ++ ++#endif /* _AVR_AT90USB646_H_ */ +diff --git a/include/avr/iousb647.h b/include/avr/iousb647.h +index d0dba09..da2c0b3 100644 +--- a/include/avr/iousb647.h ++++ b/include/avr/iousb647.h +@@ -1,95 +1,96 @@ +-/* Copyright (c) 2006 Anatoly Sokolov +- Copyright (c) 2010 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iousb647.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ +- +-/* avr/iousb647.h - definitions for AT90USB647 */ +- +-#ifndef _AVR_AT90USB647_H_ +-#define _AVR_AT90USB647_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 256 +-#define RAMEND 0x10FF +-#define XRAMEND 0xFFFF +-#define E2END 0x7FF +-#define E2PAGESIZE 8 +-#define FLASHEND 0xFFFF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_JTAGEN (unsigned char)~_BV(6) +-#define FUSE_OCDEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define FUSE_HWBE (unsigned char)~_BV(3) +-#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_HWBE) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-/* Signature */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x96 +-#define SIGNATURE_2 0x82 +- +- +-#endif /* _AVR_AT90USB647_H_ */ ++/* Copyright (c) 2006 Anatoly Sokolov ++ Copyright (c) 2010 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iousb647.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ ++ ++/* avr/iousb647.h - definitions for AT90USB647 */ ++ ++#ifndef _AVR_AT90USB647_H_ ++#define _AVR_AT90USB647_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 256 ++#define RAMSTART 0x100 ++#define RAMEND 0x10FF ++#define XRAMEND 0xFFFF ++#define E2END 0x7FF ++#define E2PAGESIZE 8 ++#define FLASHEND 0xFFFF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_JTAGEN (unsigned char)~_BV(6) ++#define FUSE_OCDEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_HWBE (unsigned char)~_BV(3) ++#define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_HWBE) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++/* Signature */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x82 ++ ++ ++#endif /* _AVR_AT90USB647_H_ */ +diff --git a/include/avr/iousb82.h b/include/avr/iousb82.h +index 53b0686..178ff68 100644 +--- a/include/avr/iousb82.h ++++ b/include/avr/iousb82.h +@@ -1,89 +1,90 @@ +-/* Copyright (c) 2007 Anatoly Sokolov +- Copyright (c) 2010 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iousb82.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ +- +-/* avr/iousb82.h - definitions for AT90USB82 */ +- +-#ifndef _AVR_AT90USB82_H_ +-#define _AVR_AT90USB82_H_ 1 +- +-#include +- +-/* Constants */ +-#define SPM_PAGESIZE 128 +-#define RAMEND 0x2FF +-#define XRAMEND RAMEND +-#define E2END 0x1FF +-#define E2PAGESIZE 4 +-#define FLASHEND 0x1FFF +- +- +-/* Fuses */ +-#define FUSE_MEMORY_SIZE 3 +- +-/* Low Fuse Byte */ +-#define FUSE_CKSEL0 (unsigned char)~_BV(0) +-#define FUSE_CKSEL1 (unsigned char)~_BV(1) +-#define FUSE_CKSEL2 (unsigned char)~_BV(2) +-#define FUSE_CKSEL3 (unsigned char)~_BV(3) +-#define FUSE_SUT0 (unsigned char)~_BV(4) +-#define FUSE_SUT1 (unsigned char)~_BV(5) +-#define FUSE_CKOUT (unsigned char)~_BV(6) +-#define FUSE_CKDIV8 (unsigned char)~_BV(7) +-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_SUT1 & FUSE_CKDIV8) +- +-/* High Fuse Byte */ +-#define FUSE_BOOTRST (unsigned char)~_BV(0) +-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) +-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) +-#define FUSE_EESAVE (unsigned char)~_BV(3) +-#define FUSE_WDTON (unsigned char)~_BV(4) +-#define FUSE_SPIEN (unsigned char)~_BV(5) +-#define FUSE_RSTDSBL (unsigned char)~_BV(6) +-#define FUSE_DWEN (unsigned char)~_BV(7) +-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) +- +-/* Extended Fuse Byte */ +-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) +-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) +-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) +-#define FUSE_HWBE (unsigned char)~_BV(3) +-#define EFUSE_DEFAULT (FUSE_BODLEVEL0 & FUSE_BODLEVEL1 & FUSE_HWBE) +- +- +-/* Lock Bits */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_BITS_0_EXIST +-#define __BOOT_LOCK_BITS_1_EXIST +- +- +-#endif /* _AVR_AT90USB82_H_ */ ++/* Copyright (c) 2007 Anatoly Sokolov ++ Copyright (c) 2010 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iousb82.h 2102 2010-03-16 22:52:39Z joerg_wunsch $ */ ++ ++/* avr/iousb82.h - definitions for AT90USB82 */ ++ ++#ifndef _AVR_AT90USB82_H_ ++#define _AVR_AT90USB82_H_ 1 ++ ++#include ++ ++/* Constants */ ++#define SPM_PAGESIZE 128 ++#define RAMSTART 0x100 ++#define RAMEND 0x2FF ++#define XRAMEND RAMEND ++#define E2END 0x1FF ++#define E2PAGESIZE 4 ++#define FLASHEND 0x1FFF ++ ++ ++/* Fuses */ ++#define FUSE_MEMORY_SIZE 3 ++ ++/* Low Fuse Byte */ ++#define FUSE_CKSEL0 (unsigned char)~_BV(0) ++#define FUSE_CKSEL1 (unsigned char)~_BV(1) ++#define FUSE_CKSEL2 (unsigned char)~_BV(2) ++#define FUSE_CKSEL3 (unsigned char)~_BV(3) ++#define FUSE_SUT0 (unsigned char)~_BV(4) ++#define FUSE_SUT1 (unsigned char)~_BV(5) ++#define FUSE_CKOUT (unsigned char)~_BV(6) ++#define FUSE_CKDIV8 (unsigned char)~_BV(7) ++#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_SUT1 & FUSE_CKDIV8) ++ ++/* High Fuse Byte */ ++#define FUSE_BOOTRST (unsigned char)~_BV(0) ++#define FUSE_BOOTSZ0 (unsigned char)~_BV(1) ++#define FUSE_BOOTSZ1 (unsigned char)~_BV(2) ++#define FUSE_EESAVE (unsigned char)~_BV(3) ++#define FUSE_WDTON (unsigned char)~_BV(4) ++#define FUSE_SPIEN (unsigned char)~_BV(5) ++#define FUSE_RSTDSBL (unsigned char)~_BV(6) ++#define FUSE_DWEN (unsigned char)~_BV(7) ++#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN) ++ ++/* Extended Fuse Byte */ ++#define FUSE_BODLEVEL0 (unsigned char)~_BV(0) ++#define FUSE_BODLEVEL1 (unsigned char)~_BV(1) ++#define FUSE_BODLEVEL2 (unsigned char)~_BV(2) ++#define FUSE_HWBE (unsigned char)~_BV(3) ++#define EFUSE_DEFAULT (FUSE_BODLEVEL0 & FUSE_BODLEVEL1 & FUSE_HWBE) ++ ++ ++/* Lock Bits */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_BITS_0_EXIST ++#define __BOOT_LOCK_BITS_1_EXIST ++ ++ ++#endif /* _AVR_AT90USB82_H_ */ +diff --git a/include/avr/iousbxx2.h b/include/avr/iousbxx2.h +index 2961de0..3579fe5 100644 +--- a/include/avr/iousbxx2.h ++++ b/include/avr/iousbxx2.h +@@ -1,798 +1,798 @@ +-/* Copyright (c) 2007 Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iousbxx2.h 2246 2011-05-14 20:02:02Z joerg_wunsch $ */ +- +-/* iousbxx2.h - definitions for AT90USB82 and AT90USB162. */ +- +-#ifndef _AVR_IOUSBXX2_H_ +-#define _AVR_IOUSBXX2_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iousbxx2.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-/* Registers and associated bit numbers */ +- +-/* Reserved [0x00..0x02] */ +- +-#define PINB _SFR_IO8(0X03) +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-#define PORTB _SFR_IO8(0x05) +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-#define PORTC _SFR_IO8(0x08) +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-/* Reserved [0xC..0x14] */ +- +-#define TIFR0 _SFR_IO8(0x15) +-#define OCF0B 2 +-#define OCF0A 1 +-#define TOV0 0 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define ICF1 5 +-#define OCF1C 3 +-#define OCF1B 2 +-#define OCF1A 1 +-#define TOV1 0 +- +-/* Reserved [0x17..0x1A] */ +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF1 1 +-#define PCIF0 0 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF7 7 +-#define INTF6 6 +-#define INTF5 5 +-#define INTF4 4 +-#define INTF3 3 +-#define INTF2 2 +-#define INTF1 1 +-#define INTF0 0 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT7 7 +-#define INT6 6 +-#define INT5 5 +-#define INT4 4 +-#define INT3 3 +-#define INT2 2 +-#define INT1 1 +-#define INT0 0 +- +-#define GPIOR0 _SFR_IO8(0x1E) +- +-#define EECR _SFR_IO8(0x1F) +-#define EEPM1 5 +-#define EEPM0 4 +-#define EERIE 3 +-#define EEMPE 2 +-#define EEPE 1 +-#define EERE 0 +- +-#define EEDR _SFR_IO8(0x20) +- +-#define EEAR _SFR_IO16(0x21) +-#define EEARL _SFR_IO8(0x21) +-#define EEARH _SFR_IO8(0x22) +- +-/* 6-char sequence denoting where to find the EEPROM registers in memory space. +- Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM +- subroutines. +- First two letters: EECR address. +- Second two letters: EEDR address. +- Last two letters: EEAR address. */ +-#define __EEPROM_REG_LOCATIONS__ 1F2021 +- +-#define GTCCR _SFR_IO8(0x23) +-#define TSM 7 +-#define PSRASY 1 +-#define PSRSYNC 0 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define COM0A1 7 +-#define COM0A0 6 +-#define COM0B1 5 +-#define COM0B0 4 +-#define WGM01 1 +-#define WGM00 0 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define FOC0A 7 +-#define FOC0B 6 +-#define WGM02 3 +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-#define TCNT0 _SFR_IO8(0X26) +- +-#define OCR0A _SFR_IO8(0x27) +- +-#define OCR0B _SFR_IO8(0X28) +- +-#define PLLCSR _SFR_IO8(0x29) +-#define PLLP2 4 +-#define PLLP1 3 +-#define PLLP0 2 +-#define PLLE 1 +-#define PLOCK 0 +- +-#define GPIOR1 _SFR_IO8(0x2A) +- +-#define GPIOR2 _SFR_IO8(0x2B) +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPIF 7 +-#define WCOL 6 +-#define SPI2X 0 +- +-#define SPDR _SFR_IO8(0x2E) +- +-/* Reserved [0x2F] */ +- +-#define ACSR _SFR_IO8(0x30) +-#define ACD 7 +-#define ACBG 6 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +- +-#define DWDR _SFR_IO8(0x31) +-#define IDRD 7 +- +-/* Reserved [0x32] */ +- +-#define SMCR _SFR_IO8(0x33) +-#define SM2 3 +-#define SM1 2 +-#define SM0 1 +-#define SE 0 +- +-#define MCUSR _SFR_IO8(0x34) +-#define USBRF 5 +-#define WDRF 3 +-#define BORF 2 +-#define EXTRF 1 +-#define PORF 0 +- +-#define MCUCR _SFR_IO8(0x35) +-#define PUD 4 +-#define IVSEL 1 +-#define IVCE 0 +- +-/* Reserved [0x36] */ +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMIE 7 +-#define RWWSB 6 +-#define SIGRD 5 +-#define RWWSRE 4 +-#define BLBSET 3 +-#define PGWRT 2 +-#define PGERS 1 +-#define SPMEN 0 +- +-/* Reserved [0x38..0x3C] */ +- +-/* SP [0x3D..0x3E] */ +-/* SREG [0x3F] */ +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDIF 7 +-#define WDIE 6 +-#define WDP3 5 +-#define WDCE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPCE 7 +-#define CLKPS3 3 +-#define CLKPS2 2 +-#define CLKPS1 1 +-#define CLKPS0 0 +- +-#define WDTCKD _SFR_MEM8(0x62) +-#define WDEWIF 3 +-#define WDEWIE 2 +-#define WCLKD1 1 +-#define WCLKD0 0 +- +-#define REGCR _SFR_MEM8(0x63) +-#define REGDIS 0 +- +-#define PRR0 _SFR_MEM8(0x64) +-#define PRTIM0 5 +-#define PRTIM1 3 +-#define PRSPI 2 +- +-#define PRR1 _SFR_MEM8(0x65) +-#define PRUSB 7 +-#define PRUSART1 0 +- +-#define OSCCAL _SFR_MEM8(0x66) +- +-/* Reserved [0x67] */ +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE1 1 +-#define PCIE0 0 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC31 7 +-#define ISC30 6 +-#define ISC21 5 +-#define ISC20 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-#define EICRB _SFR_MEM8(0x6A) +-#define ISC71 7 +-#define ISC70 6 +-#define ISC61 5 +-#define ISC60 4 +-#define ISC51 3 +-#define ISC50 2 +-#define ISC41 1 +-#define ISC40 0 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT7 7 +-#define PCINT6 6 +-#define PCINT5 5 +-#define PCINT4 4 +-#define PCINT3 3 +-#define PCINT2 2 +-#define PCINT1 1 +-#define PCINT0 0 +- +-#define PCMSK1 _SFR_MEM8(0x6C) +-#define PCINT12 4 +-#define PCINT11 3 +-#define PCINT10 2 +-#define PCINT9 1 +-#define PCINT8 0 +- +-/* Reserved [0x6D] */ +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define OCIE0B 2 +-#define OCIE0A 1 +-#define TOIE0 0 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define ICIE1 5 +-#define OCIE1C 3 +-#define OCIE1B 2 +-#define OCIE1A 1 +-#define TOIE1 0 +- +-/* Reserved [0x70..0x7F] */ +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define COM1C1 3 +-#define COM1C0 2 +-#define WGM11 1 +-#define WGM10 0 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define ICNC1 7 +-#define ICES1 6 +-#define WGM13 4 +-#define WGM12 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1A 7 +-#define FOC1B 6 +-#define FOC1C 5 +- +-/* Reserved [0x83] */ +- +-/* Combine TCNT1L and TCNT1H */ +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1H _SFR_MEM8(0x85) +- +-/* Combine ICR1L and ICR1H */ +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1H _SFR_MEM8(0x87) +- +-/* Combine OCR1AL and OCR1AH */ +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AH _SFR_MEM8(0x89) +- +-/* Combine OCR1BL and OCR1BH */ +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BH _SFR_MEM8(0x8B) +- +-/* Combine OCR1CL and OCR1CH */ +-#define OCR1C _SFR_MEM16(0x8C) +- +-#define OCR1CL _SFR_MEM8(0x8C) +-#define OCR1CH _SFR_MEM8(0x8D) +- +-/* Reserved [0x8E..0xC7] */ +- +-#define UCSR1A _SFR_MEM8(0xC8) +-#define RXC1 7 +-#define TXC1 6 +-#define UDRE1 5 +-#define FE1 4 +-#define DOR1 3 +-#define UPE1 2 +-#define U2X1 1 +-#define MPCM1 0 +- +-#define UCSR1B _SFR_MEM8(0XC9) +-#define RXCIE1 7 +-#define TXCIE1 6 +-#define UDRIE1 5 +-#define RXEN1 4 +-#define TXEN1 3 +-#define UCSZ12 2 +-#define RXB81 1 +-#define TXB81 0 +- +-#define UCSR1C _SFR_MEM8(0xCA) +-#define UMSEL11 7 +-#define UMSEL10 6 +-#define UPM11 5 +-#define UPM10 4 +-#define USBS1 3 +-#define UCSZ11 2 +-#define UCSZ10 1 +-#define UCPOL1 0 +- +-#define UCSR1D _SFR_MEM8(0xCB) +-#define CTSEN 1 +-#define RTSEN 0 +- +-/* Combine UBRR1L and UBRR1H */ +-#define UBRR1 _SFR_MEM16(0xCC) +- +-#define UBRR1L _SFR_MEM8(0xCC) +-#define UBRR1H _SFR_MEM8(0xCD) +- +-#define UDR1 _SFR_MEM8(0XCE) +- +-/* Reserved [0xCF] */ +- +-#define CKSEL0 _SFR_MEM8(0XD0) /* old name; up to AVR Studio v 4.13 */ +-#define CLKSEL0 _SFR_MEM8(0XD0) /* since AVR Studio v 4.14 */ +-#define RCSUT1 7 +-#define RCSUT0 6 +-#define EXSUT1 5 +-#define EXSUT0 4 +-#define RCE 3 +-#define EXTE 2 +-#define CLKS 0 +- +-#define CKSEL1 _SFR_MEM8(0XD1) /* old name */ +-#define CLKSEL1 _SFR_MEM8(0XD1) +-#define RCCKSEL3 7 +-#define RCCKSEL2 6 +-#define RCCKSEL1 5 +-#define RCCKSEL0 4 +-#define EXCKSEL3 3 +-#define EXCKSEL2 2 +-#define EXCKSEL1 1 +-#define EXCKSEL0 0 +- +-#define CKSTA _SFR_MEM8(0XD2) /* old name */ +-#define CLKSTA _SFR_MEM8(0XD2) +-#define RCON 1 +-#define EXTON 0 +- +-/* Reserved [0xD3..0xD7] */ +- +-#define USBCON _SFR_MEM8(0XD8) +-#define USBE 7 +-#define FRZCLK 5 +- +-/* Reserved [0xD9..0xDA] */ +- +-/* Combine UDPADDL and UDPADDH */ +-#define UDPADD _SFR_MEM16(0xDB) +- +-#define UDPADDL _SFR_MEM8(0xDB) +-#define UDPADDH _SFR_MEM8(0xDC) +-#define DPACC 7 +- +-/* Reserved [0xDD..0xDF] */ +- +-#define UDCON _SFR_MEM8(0XE0) +-#define RSTCPU 2 +-#define RMWKUP 1 +-#define DETACH 0 +- +-#define UDINT _SFR_MEM8(0XE1) +-#define UPRSMI 6 +-#define EORSMI 5 +-#define WAKEUPI 4 +-#define EORSTI 3 +-#define SOFI 2 +-#define SUSPI 0 +- +-#define UDIEN _SFR_MEM8(0XE2) +-#define UPRSME 6 +-#define EORSME 5 +-#define WAKEUPE 4 +-#define EORSTE 3 +-#define SOFE 2 +-#define SUSPE 0 +- +-#define UDADDR _SFR_MEM8(0XE3) +-#define ADDEN 7 +- +-/* Combine UDFNUML and UDFNUMH */ +-#define UDFNUM _SFR_MEM16(0xE4) +- +-#define UDFNUML _SFR_MEM8(0xE4) +-#define UDFNUMH _SFR_MEM8(0xE5) +- +-#define UDMFN _SFR_MEM8(0XE6) +-#define FNCERR 4 +- +-/* Reserved [0xE7] */ +- +-#define UEINTX _SFR_MEM8(0XE8) +-#define FIFOCON 7 +-#define NAKINI 6 +-#define RWAL 5 +-#define NAKOUTI 4 +-#define RXSTPI 3 +-#define RXOUTI 2 +-#define STALLEDI 1 +-#define TXINI 0 +- +-#define UENUM _SFR_MEM8(0XE9) +-#define EPNUM2 2 +-#define EPNUM1 1 +-#define EPNUM0 0 +- +-#define UERST _SFR_MEM8(0XEA) +-#define EPRST4 4 +-#define EPRST3 3 +-#define EPRST2 2 +-#define EPRST1 1 +-#define EPRST0 0 +- +-#define UECONX _SFR_MEM8(0XEB) +-#define STALLRQ 5 +-#define STALLRQC 4 +-#define RSTDT 3 +-#define EPEN 0 +- +-#define UECFG0X _SFR_MEM8(0XEC) +-#define EPTYPE1 7 +-#define EPTYPE0 6 +-#define EPDIR 0 +- +-#define UECFG1X _SFR_MEM8(0XED) +-#define EPSIZE2 6 +-#define EPSIZE1 5 +-#define EPSIZE0 4 +-#define EPBK1 3 +-#define EPBK0 2 +-#define ALLOC 1 +- +-#define UESTA0X _SFR_MEM8(0XEE) +-#define CFGOK 7 +-#define OVERFI 6 +-#define UNDERFI 5 +-#define DTSEQ1 3 +-#define DTSEQ0 2 +-#define NBUSYBK1 1 +-#define NBUSYBK0 0 +- +-#define UESTA1X _SFR_MEM8(0XEF) +-#define CTRLDIR 2 +-#define CURRBK1 1 +-#define CURRBK0 0 +- +-#define UEIENX _SFR_MEM8(0XF0) +-#define FLERRE 7 +-#define NAKINE 6 +-#define NAKOUTE 4 +-#define RXSTPE 3 +-#define RXOUTE 2 +-#define STALLEDE 1 +-#define TXINE 0 +- +-#define UEDATX _SFR_MEM8(0XF1) +- +-#define UEBCLX _SFR_MEM8(0xF2) +- +-/* Reserved [0xF3] */ +- +-#define UEINT _SFR_MEM8(0XF4) +-#define EPINT4 4 +-#define EPINT3 3 +-#define EPINT2 2 +-#define EPINT1 1 +-#define EPINT0 0 +- +-/* Reserved [0xF5..0xF9] */ +- +-#define PS2CON _SFR_MEM8(0XFA) +-#define PS2EN 0 +- +-#define UPOE _SFR_MEM8(0XFB) +-#define UPWE1 7 +-#define UPWE0 6 +-#define UPDRV1 5 +-#define UPDRV0 4 +-#define SCKI 3 +-#define DATAI 2 +-#define DPI 1 +-#define DMI 0 +- +-/* Reserved [0xFC..0xFF] */ +- +-/* Interrupt vectors */ +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +- +-/* External Interrupt Request 1 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +- +-/* External Interrupt Request 2 */ +-#define INT2_vect_num 3 +-#define INT2_vect _VECTOR(3) +- +-/* External Interrupt Request 3 */ +-#define INT3_vect_num 4 +-#define INT3_vect _VECTOR(4) +- +-/* External Interrupt Request 4 */ +-#define INT4_vect_num 5 +-#define INT4_vect _VECTOR(5) +- +-/* External Interrupt Request 5 */ +-#define INT5_vect_num 6 +-#define INT5_vect _VECTOR(6) +- +-/* External Interrupt Request 6 */ +-#define INT6_vect_num 7 +-#define INT6_vect _VECTOR(7) +- +-/* External Interrupt Request 7 */ +-#define INT7_vect_num 8 +-#define INT7_vect _VECTOR(8) +- +-/* Pin Change Interrupt Request 0 */ +-#define PCINT0_vect_num 9 +-#define PCINT0_vect _VECTOR(9) +- +-/* Pin Change Interrupt Request 1 */ +-#define PCINT1_vect_num 10 +-#define PCINT1_vect _VECTOR(10) +- +-/* USB General Interrupt Request */ +-#define USB_GEN_vect_num 11 +-#define USB_GEN_vect _VECTOR(11) +- +-/* USB Endpoint/Pipe Interrupt Communication Request */ +-#define USB_COM_vect_num 12 +-#define USB_COM_vect _VECTOR(12) +- +-/* Watchdog Time-out Interrupt */ +-#define WDT_vect_num 13 +-#define WDT_vect _VECTOR(13) +- +-/* Timer/Counter2 Capture Event */ +-#define TIMER1_CAPT_vect_num 14 +-#define TIMER1_CAPT_vect _VECTOR(14) +- +-/* Timer/Counter2 Compare Match B */ +-#define TIMER1_COMPA_vect_num 15 +-#define TIMER1_COMPA_vect _VECTOR(15) +- +-/* Timer/Counter2 Compare Match B */ +-#define TIMER1_COMPB_vect_num 16 +-#define TIMER1_COMPB_vect _VECTOR(16) +- +-/* Timer/Counter2 Compare Match C */ +-#define TIMER1_COMPC_vect_num 17 +-#define TIMER1_COMPC_vect _VECTOR(17) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 18 +-#define TIMER1_OVF_vect _VECTOR(18) +- +-/* Timer/Counter0 Compare Match A */ +-#define TIMER0_COMPA_vect_num 19 +-#define TIMER0_COMPA_vect _VECTOR(19) +- +-/* Timer/Counter0 Compare Match B */ +-#define TIMER0_COMPB_vect_num 20 +-#define TIMER0_COMPB_vect _VECTOR(20) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 21 +-#define TIMER0_OVF_vect _VECTOR(21) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 22 +-#define SPI_STC_vect _VECTOR(22) +- +-/* USART1, Rx Complete */ +-#define USART1_RX_vect_num 23 +-#define USART1_RX_vect _VECTOR(23) +- +-/* USART1 Data register Empty */ +-#define USART1_UDRE_vect_num 24 +-#define USART1_UDRE_vect _VECTOR(24) +- +-/* USART1, Tx Complete */ +-#define USART1_TX_vect_num 25 +-#define USART1_TX_vect _VECTOR(25) +- +-/* Analog Comparator */ +-#define ANALOG_COMP_vect_num 26 +-#define ANALOG_COMP_vect _VECTOR(26) +- +-/* EEPROM Ready */ +-#define EE_READY_vect_num 27 +-#define EE_READY_vect _VECTOR(27) +- +-/* Store Program Memory Read */ +-#define SPM_READY_vect_num 28 +-#define SPM_READY_vect _VECTOR(28) +- +-#define _VECTORS_SIZE 116 +- +-#endif /* _AVR_IOUSBXX2_H_ */ ++/* Copyright (c) 2007 Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iousbxx2.h 2246 2011-05-14 20:02:02Z joerg_wunsch $ */ ++ ++/* iousbxx2.h - definitions for AT90USB82 and AT90USB162. */ ++ ++#ifndef _AVR_IOUSBXX2_H_ ++#define _AVR_IOUSBXX2_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iousbxx2.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++/* Reserved [0x00..0x02] */ ++ ++#define PINB _SFR_IO8(0X03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++/* Reserved [0xC..0x14] */ ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define OCF0B 2 ++#define OCF0A 1 ++#define TOV0 0 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define ICF1 5 ++#define OCF1C 3 ++#define OCF1B 2 ++#define OCF1A 1 ++#define TOV1 0 ++ ++/* Reserved [0x17..0x1A] */ ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF1 1 ++#define PCIF0 0 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF7 7 ++#define INTF6 6 ++#define INTF5 5 ++#define INTF4 4 ++#define INTF3 3 ++#define INTF2 2 ++#define INTF1 1 ++#define INTF0 0 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT7 7 ++#define INT6 6 ++#define INT5 5 ++#define INT4 4 ++#define INT3 3 ++#define INT2 2 ++#define INT1 1 ++#define INT0 0 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EEPM1 5 ++#define EEPM0 4 ++#define EERIE 3 ++#define EEMPE 2 ++#define EEPE 1 ++#define EERE 0 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++#define EEAR _SFR_IO16(0x21) ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++/* 6-char sequence denoting where to find the EEPROM registers in memory space. ++ Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM ++ subroutines. ++ First two letters: EECR address. ++ Second two letters: EEDR address. ++ Last two letters: EEAR address. */ ++#define __EEPROM_REG_LOCATIONS__ 1F2021 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define TSM 7 ++#define PSRASY 1 ++#define PSRSYNC 0 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define COM0A1 7 ++#define COM0A0 6 ++#define COM0B1 5 ++#define COM0B0 4 ++#define WGM01 1 ++#define WGM00 0 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define FOC0A 7 ++#define FOC0B 6 ++#define WGM02 3 ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++#define TCNT0 _SFR_IO8(0X26) ++ ++#define OCR0A _SFR_IO8(0x27) ++ ++#define OCR0B _SFR_IO8(0X28) ++ ++#define PLLCSR _SFR_IO8(0x29) ++#define PLLP2 4 ++#define PLLP1 3 ++#define PLLP0 2 ++#define PLLE 1 ++#define PLOCK 0 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPIF 7 ++#define WCOL 6 ++#define SPI2X 0 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACD 7 ++#define ACBG 6 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++#define DWDR _SFR_IO8(0x31) ++#define IDRD 7 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SM2 3 ++#define SM1 2 ++#define SM0 1 ++#define SE 0 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define USBRF 5 ++#define WDRF 3 ++#define BORF 2 ++#define EXTRF 1 ++#define PORF 0 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define PUD 4 ++#define IVSEL 1 ++#define IVCE 0 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMIE 7 ++#define RWWSB 6 ++#define SIGRD 5 ++#define RWWSRE 4 ++#define BLBSET 3 ++#define PGWRT 2 ++#define PGERS 1 ++#define SPMEN 0 ++ ++/* Reserved [0x38..0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++/* SREG [0x3F] */ ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDIF 7 ++#define WDIE 6 ++#define WDP3 5 ++#define WDCE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPCE 7 ++#define CLKPS3 3 ++#define CLKPS2 2 ++#define CLKPS1 1 ++#define CLKPS0 0 ++ ++#define WDTCKD _SFR_MEM8(0x62) ++#define WDEWIF 3 ++#define WDEWIE 2 ++#define WCLKD1 1 ++#define WCLKD0 0 ++ ++#define REGCR _SFR_MEM8(0x63) ++#define REGDIS 0 ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRTIM0 5 ++#define PRTIM1 3 ++#define PRSPI 2 ++ ++#define PRR1 _SFR_MEM8(0x65) ++#define PRUSB 7 ++#define PRUSART1 0 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++ ++/* Reserved [0x67] */ ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE1 1 ++#define PCIE0 0 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC31 7 ++#define ISC30 6 ++#define ISC21 5 ++#define ISC20 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++#define EICRB _SFR_MEM8(0x6A) ++#define ISC71 7 ++#define ISC70 6 ++#define ISC61 5 ++#define ISC60 4 ++#define ISC51 3 ++#define ISC50 2 ++#define ISC41 1 ++#define ISC40 0 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT7 7 ++#define PCINT6 6 ++#define PCINT5 5 ++#define PCINT4 4 ++#define PCINT3 3 ++#define PCINT2 2 ++#define PCINT1 1 ++#define PCINT0 0 ++ ++#define PCMSK1 _SFR_MEM8(0x6C) ++#define PCINT12 4 ++#define PCINT11 3 ++#define PCINT10 2 ++#define PCINT9 1 ++#define PCINT8 0 ++ ++/* Reserved [0x6D] */ ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define OCIE0B 2 ++#define OCIE0A 1 ++#define TOIE0 0 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define ICIE1 5 ++#define OCIE1C 3 ++#define OCIE1B 2 ++#define OCIE1A 1 ++#define TOIE1 0 ++ ++/* Reserved [0x70..0x7F] */ ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define COM1C1 3 ++#define COM1C0 2 ++#define WGM11 1 ++#define WGM10 0 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define ICNC1 7 ++#define ICES1 6 ++#define WGM13 4 ++#define WGM12 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1A 7 ++#define FOC1B 6 ++#define FOC1C 5 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Combine OCR1CL and OCR1CH */ ++#define OCR1C _SFR_MEM16(0x8C) ++ ++#define OCR1CL _SFR_MEM8(0x8C) ++#define OCR1CH _SFR_MEM8(0x8D) ++ ++/* Reserved [0x8E..0xC7] */ ++ ++#define UCSR1A _SFR_MEM8(0xC8) ++#define RXC1 7 ++#define TXC1 6 ++#define UDRE1 5 ++#define FE1 4 ++#define DOR1 3 ++#define UPE1 2 ++#define U2X1 1 ++#define MPCM1 0 ++ ++#define UCSR1B _SFR_MEM8(0XC9) ++#define RXCIE1 7 ++#define TXCIE1 6 ++#define UDRIE1 5 ++#define RXEN1 4 ++#define TXEN1 3 ++#define UCSZ12 2 ++#define RXB81 1 ++#define TXB81 0 ++ ++#define UCSR1C _SFR_MEM8(0xCA) ++#define UMSEL11 7 ++#define UMSEL10 6 ++#define UPM11 5 ++#define UPM10 4 ++#define USBS1 3 ++#define UCSZ11 2 ++#define UCSZ10 1 ++#define UCPOL1 0 ++ ++#define UCSR1D _SFR_MEM8(0xCB) ++#define CTSEN 1 ++#define RTSEN 0 ++ ++/* Combine UBRR1L and UBRR1H */ ++#define UBRR1 _SFR_MEM16(0xCC) ++ ++#define UBRR1L _SFR_MEM8(0xCC) ++#define UBRR1H _SFR_MEM8(0xCD) ++ ++#define UDR1 _SFR_MEM8(0XCE) ++ ++/* Reserved [0xCF] */ ++ ++#define CKSEL0 _SFR_MEM8(0XD0) /* old name; up to AVR Studio v 4.13 */ ++#define CLKSEL0 _SFR_MEM8(0XD0) /* since AVR Studio v 4.14 */ ++#define RCSUT1 7 ++#define RCSUT0 6 ++#define EXSUT1 5 ++#define EXSUT0 4 ++#define RCE 3 ++#define EXTE 2 ++#define CLKS 0 ++ ++#define CKSEL1 _SFR_MEM8(0XD1) /* old name */ ++#define CLKSEL1 _SFR_MEM8(0XD1) ++#define RCCKSEL3 7 ++#define RCCKSEL2 6 ++#define RCCKSEL1 5 ++#define RCCKSEL0 4 ++#define EXCKSEL3 3 ++#define EXCKSEL2 2 ++#define EXCKSEL1 1 ++#define EXCKSEL0 0 ++ ++#define CKSTA _SFR_MEM8(0XD2) /* old name */ ++#define CLKSTA _SFR_MEM8(0XD2) ++#define RCON 1 ++#define EXTON 0 ++ ++/* Reserved [0xD3..0xD7] */ ++ ++#define USBCON _SFR_MEM8(0XD8) ++#define USBE 7 ++#define FRZCLK 5 ++ ++/* Reserved [0xD9..0xDA] */ ++ ++/* Combine UDPADDL and UDPADDH */ ++#define UDPADD _SFR_MEM16(0xDB) ++ ++#define UDPADDL _SFR_MEM8(0xDB) ++#define UDPADDH _SFR_MEM8(0xDC) ++#define DPACC 7 ++ ++/* Reserved [0xDD..0xDF] */ ++ ++#define UDCON _SFR_MEM8(0XE0) ++#define RSTCPU 2 ++#define RMWKUP 1 ++#define DETACH 0 ++ ++#define UDINT _SFR_MEM8(0XE1) ++#define UPRSMI 6 ++#define EORSMI 5 ++#define WAKEUPI 4 ++#define EORSTI 3 ++#define SOFI 2 ++#define SUSPI 0 ++ ++#define UDIEN _SFR_MEM8(0XE2) ++#define UPRSME 6 ++#define EORSME 5 ++#define WAKEUPE 4 ++#define EORSTE 3 ++#define SOFE 2 ++#define SUSPE 0 ++ ++#define UDADDR _SFR_MEM8(0XE3) ++#define ADDEN 7 ++ ++/* Combine UDFNUML and UDFNUMH */ ++#define UDFNUM _SFR_MEM16(0xE4) ++ ++#define UDFNUML _SFR_MEM8(0xE4) ++#define UDFNUMH _SFR_MEM8(0xE5) ++ ++#define UDMFN _SFR_MEM8(0XE6) ++#define FNCERR 4 ++ ++/* Reserved [0xE7] */ ++ ++#define UEINTX _SFR_MEM8(0XE8) ++#define FIFOCON 7 ++#define NAKINI 6 ++#define RWAL 5 ++#define NAKOUTI 4 ++#define RXSTPI 3 ++#define RXOUTI 2 ++#define STALLEDI 1 ++#define TXINI 0 ++ ++#define UENUM _SFR_MEM8(0XE9) ++#define EPNUM2 2 ++#define EPNUM1 1 ++#define EPNUM0 0 ++ ++#define UERST _SFR_MEM8(0XEA) ++#define EPRST4 4 ++#define EPRST3 3 ++#define EPRST2 2 ++#define EPRST1 1 ++#define EPRST0 0 ++ ++#define UECONX _SFR_MEM8(0XEB) ++#define STALLRQ 5 ++#define STALLRQC 4 ++#define RSTDT 3 ++#define EPEN 0 ++ ++#define UECFG0X _SFR_MEM8(0XEC) ++#define EPTYPE1 7 ++#define EPTYPE0 6 ++#define EPDIR 0 ++ ++#define UECFG1X _SFR_MEM8(0XED) ++#define EPSIZE2 6 ++#define EPSIZE1 5 ++#define EPSIZE0 4 ++#define EPBK1 3 ++#define EPBK0 2 ++#define ALLOC 1 ++ ++#define UESTA0X _SFR_MEM8(0XEE) ++#define CFGOK 7 ++#define OVERFI 6 ++#define UNDERFI 5 ++#define DTSEQ1 3 ++#define DTSEQ0 2 ++#define NBUSYBK1 1 ++#define NBUSYBK0 0 ++ ++#define UESTA1X _SFR_MEM8(0XEF) ++#define CTRLDIR 2 ++#define CURRBK1 1 ++#define CURRBK0 0 ++ ++#define UEIENX _SFR_MEM8(0XF0) ++#define FLERRE 7 ++#define NAKINE 6 ++#define NAKOUTE 4 ++#define RXSTPE 3 ++#define RXOUTE 2 ++#define STALLEDE 1 ++#define TXINE 0 ++ ++#define UEDATX _SFR_MEM8(0XF1) ++ ++#define UEBCLX _SFR_MEM8(0xF2) ++ ++/* Reserved [0xF3] */ ++ ++#define UEINT _SFR_MEM8(0XF4) ++#define EPINT4 4 ++#define EPINT3 3 ++#define EPINT2 2 ++#define EPINT1 1 ++#define EPINT0 0 ++ ++/* Reserved [0xF5..0xF9] */ ++ ++#define PS2CON _SFR_MEM8(0XFA) ++#define PS2EN 0 ++ ++#define UPOE _SFR_MEM8(0XFB) ++#define UPWE1 7 ++#define UPWE0 6 ++#define UPDRV1 5 ++#define UPDRV0 4 ++#define SCKI 3 ++#define DATAI 2 ++#define DPI 1 ++#define DMI 0 ++ ++/* Reserved [0xFC..0xFF] */ ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect_num 3 ++#define INT2_vect _VECTOR(3) ++ ++/* External Interrupt Request 3 */ ++#define INT3_vect_num 4 ++#define INT3_vect _VECTOR(4) ++ ++/* External Interrupt Request 4 */ ++#define INT4_vect_num 5 ++#define INT4_vect _VECTOR(5) ++ ++/* External Interrupt Request 5 */ ++#define INT5_vect_num 6 ++#define INT5_vect _VECTOR(6) ++ ++/* External Interrupt Request 6 */ ++#define INT6_vect_num 7 ++#define INT6_vect _VECTOR(7) ++ ++/* External Interrupt Request 7 */ ++#define INT7_vect_num 8 ++#define INT7_vect _VECTOR(8) ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect_num 9 ++#define PCINT0_vect _VECTOR(9) ++ ++/* Pin Change Interrupt Request 1 */ ++#define PCINT1_vect_num 10 ++#define PCINT1_vect _VECTOR(10) ++ ++/* USB General Interrupt Request */ ++#define USB_GEN_vect_num 11 ++#define USB_GEN_vect _VECTOR(11) ++ ++/* USB Endpoint/Pipe Interrupt Communication Request */ ++#define USB_COM_vect_num 12 ++#define USB_COM_vect _VECTOR(12) ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect_num 13 ++#define WDT_vect _VECTOR(13) ++ ++/* Timer/Counter2 Capture Event */ ++#define TIMER1_CAPT_vect_num 14 ++#define TIMER1_CAPT_vect _VECTOR(14) ++ ++/* Timer/Counter2 Compare Match B */ ++#define TIMER1_COMPA_vect_num 15 ++#define TIMER1_COMPA_vect _VECTOR(15) ++ ++/* Timer/Counter2 Compare Match B */ ++#define TIMER1_COMPB_vect_num 16 ++#define TIMER1_COMPB_vect _VECTOR(16) ++ ++/* Timer/Counter2 Compare Match C */ ++#define TIMER1_COMPC_vect_num 17 ++#define TIMER1_COMPC_vect _VECTOR(17) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 18 ++#define TIMER1_OVF_vect _VECTOR(18) ++ ++/* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPA_vect_num 19 ++#define TIMER0_COMPA_vect _VECTOR(19) ++ ++/* Timer/Counter0 Compare Match B */ ++#define TIMER0_COMPB_vect_num 20 ++#define TIMER0_COMPB_vect _VECTOR(20) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 21 ++#define TIMER0_OVF_vect _VECTOR(21) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 22 ++#define SPI_STC_vect _VECTOR(22) ++ ++/* USART1, Rx Complete */ ++#define USART1_RX_vect_num 23 ++#define USART1_RX_vect _VECTOR(23) ++ ++/* USART1 Data register Empty */ ++#define USART1_UDRE_vect_num 24 ++#define USART1_UDRE_vect _VECTOR(24) ++ ++/* USART1, Tx Complete */ ++#define USART1_TX_vect_num 25 ++#define USART1_TX_vect _VECTOR(25) ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect_num 26 ++#define ANALOG_COMP_vect _VECTOR(26) ++ ++/* EEPROM Ready */ ++#define EE_READY_vect_num 27 ++#define EE_READY_vect _VECTOR(27) ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect_num 28 ++#define SPM_READY_vect _VECTOR(28) ++ ++#define _VECTORS_SIZE 116 ++ ++#endif /* _AVR_IOUSBXX2_H_ */ +diff --git a/include/avr/iousbxx6_7.h b/include/avr/iousbxx6_7.h +index 30af678..7c7ae4e 100644 +--- a/include/avr/iousbxx6_7.h ++++ b/include/avr/iousbxx6_7.h +@@ -1,1322 +1,1322 @@ +-/* Copyright (c) 2006, Anatoly Sokolov +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iousbxx6_7.h 2225 2011-03-02 16:27:26Z arcanum $ */ +- +-/* iousbxx6_7.h - definitions for AT90USB646, AT90USB647, AT90USB1286 +- and AT90USB1287 */ +- +-#ifndef _AVR_IOUSBXX6_7_H_ +-#define _AVR_IOUSBXX6_7_H_ 1 +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iousbxx6_7.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +-#if defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__) +-# define __AT90USBxx6__ 1 +-#elif defined(__AVR_AT90USB647__) || defined(__AVR_AT90USB1287__) +-# define __AT90USBxx7__ 1 +-#endif +- +-/* Registers and associated bit numbers */ +- +-#define PINA _SFR_IO8(0X00) +-#define PINA7 7 +-#define PINA6 6 +-#define PINA5 5 +-#define PINA4 4 +-#define PINA3 3 +-#define PINA2 2 +-#define PINA1 1 +-#define PINA0 0 +- +-#define DDRA _SFR_IO8(0X01) +-#define DDA7 7 +-#define DDA6 6 +-#define DDA5 5 +-#define DDA4 4 +-#define DDA3 3 +-#define DDA2 2 +-#define DDA1 1 +-#define DDA0 0 +- +-#define PORTA _SFR_IO8(0X02) +-#define PA7 7 +-#define PA6 6 +-#define PA5 5 +-#define PA4 4 +-#define PA3 3 +-#define PA2 2 +-#define PA1 1 +-#define PA0 0 +- +-#define PINB _SFR_IO8(0X03) +-#define PINB7 7 +-#define PINB6 6 +-#define PINB5 5 +-#define PINB4 4 +-#define PINB3 3 +-#define PINB2 2 +-#define PINB1 1 +-#define PINB0 0 +- +-#define DDRB _SFR_IO8(0x04) +-#define DDB7 7 +-#define DDB6 6 +-#define DDB5 5 +-#define DDB4 4 +-#define DDB3 3 +-#define DDB2 2 +-#define DDB1 1 +-#define DDB0 0 +- +-#define PORTB _SFR_IO8(0x05) +-#define PB7 7 +-#define PB6 6 +-#define PB5 5 +-#define PB4 4 +-#define PB3 3 +-#define PB2 2 +-#define PB1 1 +-#define PB0 0 +- +-#define PINC _SFR_IO8(0x06) +-#define PINC7 7 +-#define PINC6 6 +-#define PINC5 5 +-#define PINC4 4 +-#define PINC3 3 +-#define PINC2 2 +-#define PINC1 1 +-#define PINC0 0 +- +-#define DDRC _SFR_IO8(0x07) +-#define DDC7 7 +-#define DDC6 6 +-#define DDC5 5 +-#define DDC4 4 +-#define DDC3 3 +-#define DDC2 2 +-#define DDC1 1 +-#define DDC0 0 +- +-#define PORTC _SFR_IO8(0x08) +-#define PC7 7 +-#define PC6 6 +-#define PC5 5 +-#define PC4 4 +-#define PC3 3 +-#define PC2 2 +-#define PC1 1 +-#define PC0 0 +- +-#define PIND _SFR_IO8(0x09) +-#define PIND7 7 +-#define PIND6 6 +-#define PIND5 5 +-#define PIND4 4 +-#define PIND3 3 +-#define PIND2 2 +-#define PIND1 1 +-#define PIND0 0 +- +-#define DDRD _SFR_IO8(0x0A) +-#define DDD7 7 +-#define DDD6 6 +-#define DDD5 5 +-#define DDD4 4 +-#define DDD3 3 +-#define DDD2 2 +-#define DDD1 1 +-#define DDD0 0 +- +-#define PORTD _SFR_IO8(0x0B) +-#define PD7 7 +-#define PD6 6 +-#define PD5 5 +-#define PD4 4 +-#define PD3 3 +-#define PD2 2 +-#define PD1 1 +-#define PD0 0 +- +-#define PINE _SFR_IO8(0x0C) +-#define PINE7 7 +-#define PINE6 6 +-#define PINE5 5 +-#define PINE4 4 +-#define PINE3 3 +-#define PINE2 2 +-#define PINE1 1 +-#define PINE0 0 +- +-#define DDRE _SFR_IO8(0x0D) +-#define DDE7 7 +-#define DDE6 6 +-#define DDE5 5 +-#define DDE4 4 +-#define DDE3 3 +-#define DDE2 2 +-#define DDE1 1 +-#define DDE0 0 +- +-#define PORTE _SFR_IO8(0x0E) +-#define PE7 7 +-#define PE6 6 +-#define PE5 5 +-#define PE4 4 +-#define PE3 3 +-#define PE2 2 +-#define PE1 1 +-#define PE0 0 +- +-#define PINF _SFR_IO8(0x0F) +-#define PINF7 7 +-#define PINF6 6 +-#define PINF5 5 +-#define PINF4 4 +-#define PINF3 3 +-#define PINF2 2 +-#define PINF1 1 +-#define PINF0 0 +- +-#define DDRF _SFR_IO8(0x10) +-#define DDF7 7 +-#define DDF6 6 +-#define DDF5 5 +-#define DDF4 4 +-#define DDF3 3 +-#define DDF2 2 +-#define DDF1 1 +-#define DDF0 0 +- +-#define PORTF _SFR_IO8(0x11) +-#define PF7 7 +-#define PF6 6 +-#define PF5 5 +-#define PF4 4 +-#define PF3 3 +-#define PF2 2 +-#define PF1 1 +-#define PF0 0 +- +-/* Reserved [0x12..0x14] */ +- +-#define TIFR0 _SFR_IO8(0x15) +-#define OCF0B 2 +-#define OCF0A 1 +-#define TOV0 0 +- +-#define TIFR1 _SFR_IO8(0x16) +-#define ICF1 5 +-#define OCF1C 3 +-#define OCF1B 2 +-#define OCF1A 1 +-#define TOV1 0 +- +-#define TIFR2 _SFR_IO8(0x17) +-#define OCF2B 2 +-#define OCF2A 1 +-#define TOV2 0 +- +-#define TIFR3 _SFR_IO8(0x18) +-#define ICF3 5 +-#define OCF3C 3 +-#define OCF3B 2 +-#define OCF3A 1 +-#define TOV3 0 +- +-/* Reserved [0x19..0x1A] */ +- +-#define PCIFR _SFR_IO8(0x1B) +-#define PCIF0 0 +- +-#define EIFR _SFR_IO8(0x1C) +-#define INTF7 7 +-#define INTF6 6 +-#define INTF5 5 +-#define INTF4 4 +-#define INTF3 3 +-#define INTF2 2 +-#define INTF1 1 +-#define INTF0 0 +- +-#define EIMSK _SFR_IO8(0x1D) +-#define INT7 7 +-#define INT6 6 +-#define INT5 5 +-#define INT4 4 +-#define INT3 3 +-#define INT2 2 +-#define INT1 1 +-#define INT0 0 +- +-#define GPIOR0 _SFR_IO8(0x1E) +- +-#define EECR _SFR_IO8(0x1F) +-#define EEPM1 5 +-#define EEPM0 4 +-#define EERIE 3 +-#define EEMPE 2 +-#define EEPE 1 +-#define EERE 0 +- +-#define EEDR _SFR_IO8(0x20) +- +-#define EEAR _SFR_IO16(0x21) +-#define EEARL _SFR_IO8(0x21) +-#define EEARH _SFR_IO8(0x22) +- +-/* 6-char sequence denoting where to find the EEPROM registers in memory space. +- Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM +- subroutines. +- First two letters: EECR address. +- Second two letters: EEDR address. +- Last two letters: EEAR address. */ +-#define __EEPROM_REG_LOCATIONS__ 1F2021 +- +-#define GTCCR _SFR_IO8(0x23) +-#define TSM 7 +-#define PSRASY 1 +-#define PSRSYNC 0 +- +-#define TCCR0A _SFR_IO8(0x24) +-#define COM0A1 7 +-#define COM0A0 6 +-#define COM0B1 5 +-#define COM0B0 4 +-#define WGM01 1 +-#define WGM00 0 +- +-#define TCCR0B _SFR_IO8(0x25) +-#define FOC0A 7 +-#define FOC0B 6 +-#define WGM02 3 +-#define CS02 2 +-#define CS01 1 +-#define CS00 0 +- +-#define TCNT0 _SFR_IO8(0X26) +- +-#define OCR0A _SFR_IO8(0x27) +- +-#define OCR0B _SFR_IO8(0X28) +- +-#define PLLCSR _SFR_IO8(0x29) +-#define PLLP2 4 +-#define PLLP1 3 +-#define PLLP0 2 +-#define PLLE 1 +-#define PLOCK 0 +- +-#define GPIOR1 _SFR_IO8(0x2A) +- +-#define GPIOR2 _SFR_IO8(0x2B) +- +-#define SPCR _SFR_IO8(0x2C) +-#define SPIE 7 +-#define SPE 6 +-#define DORD 5 +-#define MSTR 4 +-#define CPOL 3 +-#define CPHA 2 +-#define SPR1 1 +-#define SPR0 0 +- +-#define SPSR _SFR_IO8(0x2D) +-#define SPIF 7 +-#define WCOL 6 +-#define SPI2X 0 +- +-#define SPDR _SFR_IO8(0x2E) +- +-/* Reserved [0x2F] */ +- +-#define ACSR _SFR_IO8(0x30) +-#define ACD 7 +-#define ACBG 6 +-#define ACO 5 +-#define ACI 4 +-#define ACIE 3 +-#define ACIC 2 +-#define ACIS1 1 +-#define ACIS0 0 +- +-#define MONDR _SFR_IO8(0x31) +-#define OCDR _SFR_IO8(0x31) +-#define IDRD 7 +-#define OCDR7 7 +-#define OCDR6 6 +-#define OCDR5 5 +-#define OCDR4 4 +-#define OCDR3 3 +-#define OCDR2 2 +-#define OCDR1 1 +-#define OCDR0 0 +- +-/* Reserved [0x32] */ +- +-#define SMCR _SFR_IO8(0x33) +-#define SM2 3 +-#define SM1 2 +-#define SM0 1 +-#define SE 0 +- +-#define MCUSR _SFR_IO8(0x34) +-#define JTRF 4 +-#define WDRF 3 +-#define BORF 2 +-#define EXTRF 1 +-#define PORF 0 +- +-#define MCUCR _SFR_IO8(0x35) +-#define JTD 7 +-#define PUD 4 +-#define IVSEL 1 +-#define IVCE 0 +- +-/* Reserved [0x36] */ +- +-#define SPMCSR _SFR_IO8(0x37) +-#define SPMIE 7 +-#define RWWSB 6 +-#define SIGRD 5 +-#define RWWSRE 4 +-#define BLBSET 3 +-#define PGWRT 2 +-#define PGERS 1 +-#define SPMEN 0 +- +-/* Reserved [0x38..0x3A] */ +- +-#if defined(__AVR_AT90USB1286__) || defined(__AVR_AT90USB1287__) +-#define RAMPZ _SFR_IO8(0x3B) +-#endif +- +-/* Reserved [0x3C] */ +- +-/* SP [0x3D..0x3E] */ +-/* SREG [0x3F] */ +- +-#define WDTCSR _SFR_MEM8(0x60) +-#define WDIF 7 +-#define WDIE 6 +-#define WDP3 5 +-#define WDCE 4 +-#define WDE 3 +-#define WDP2 2 +-#define WDP1 1 +-#define WDP0 0 +- +-#define CLKPR _SFR_MEM8(0x61) +-#define CLKPCE 7 +-#define CLKPS3 3 +-#define CLKPS2 2 +-#define CLKPS1 1 +-#define CLKPS0 0 +- +-/* Reserved [0x62..0x63] */ +- +-#define PRR0 _SFR_MEM8(0x64) +-#define PRTWI 7 +-#define PRTIM2 6 +-#define PRTIM0 5 +-#define PRTIM1 3 +-#define PRSPI 2 +-#define PRADC 0 +- +-#define PRR1 _SFR_MEM8(0x65) +-#define PRUSB 7 +-#define PRTIM3 3 +-#define PRUSART1 0 +- +-#define OSCCAL _SFR_MEM8(0x66) +- +-/* Reserved [0x67] */ +- +-#define PCICR _SFR_MEM8(0x68) +-#define PCIE0 0 +- +-#define EICRA _SFR_MEM8(0x69) +-#define ISC31 7 +-#define ISC30 6 +-#define ISC21 5 +-#define ISC20 4 +-#define ISC11 3 +-#define ISC10 2 +-#define ISC01 1 +-#define ISC00 0 +- +-#define EICRB _SFR_MEM8(0x6A) +-#define ISC71 7 +-#define ISC70 6 +-#define ISC61 5 +-#define ISC60 4 +-#define ISC51 3 +-#define ISC50 2 +-#define ISC41 1 +-#define ISC40 0 +- +-#define PCMSK0 _SFR_MEM8(0x6B) +-#define PCINT7 7 +-#define PCINT6 6 +-#define PCINT5 5 +-#define PCINT4 4 +-#define PCINT3 3 +-#define PCINT2 2 +-#define PCINT1 1 +-#define PCINT0 0 +- +-/* Reserved [0x6C..0x6D] */ +- +-#define TIMSK0 _SFR_MEM8(0x6E) +-#define OCIE0B 2 +-#define OCIE0A 1 +-#define TOIE0 0 +- +-#define TIMSK1 _SFR_MEM8(0x6F) +-#define ICIE1 5 +-#define OCIE1C 3 +-#define OCIE1B 2 +-#define OCIE1A 1 +-#define TOIE1 0 +- +-#define TIMSK2 _SFR_MEM8(0x70) +-#define OCIE2B 2 +-#define OCIE2A 1 +-#define TOIE2 0 +- +-#define TIMSK3 _SFR_MEM8(0x71) +-#define ICIE3 5 +-#define OCIE3C 3 +-#define OCIE3B 2 +-#define OCIE3A 1 +-#define TOIE3 0 +- +-/* Reserved [0x72..0x73] */ +- +-#define XMCRA _SFR_MEM8(0x74) +-#define SRE 7 +-#define SRL2 6 +-#define SRL1 5 +-#define SRL0 4 +-#define SRW11 3 +-#define SRW10 2 +-#define SRW01 1 +-#define SRW00 0 +- +-#define XMCRB _SFR_MEM8(0x75) +-#define XMBK 7 +-#define XMM2 2 +-#define XMM1 1 +-#define XMM0 0 +- +-/* Reserved [0x76..0x77] */ +- +-/* RegDef: ADC Data Register */ +-#ifndef __ASSEMBLER__ +-#define ADC _SFR_MEM16(0x78) +-#endif +-#define ADCW _SFR_MEM16(0x78) +-#define ADCL _SFR_MEM8(0x78) +-#define ADCH _SFR_MEM8(0x79) +- +-#define ADCSRA _SFR_MEM8(0x7A) +-#define ADEN 7 +-#define ADSC 6 +-#define ADATE 5 +-#define ADIF 4 +-#define ADIE 3 +-#define ADPS2 2 +-#define ADPS1 1 +-#define ADPS0 0 +- +-#define ADCSRB _SFR_MEM8(0x7B) +-#define ACME 6 +-#define ADTS2 2 +-#define ADTS1 1 +-#define ADTS0 0 +- +-#define ADMUX _SFR_MEM8(0x7C) +-#define REFS1 7 +-#define REFS0 6 +-#define ADLAR 5 +-#define MUX4 4 +-#define MUX3 3 +-#define MUX2 2 +-#define MUX1 1 +-#define MUX0 0 +- +-/* Reserved [0x7D] */ +- +-#define DIDR0 _SFR_MEM8(0x7E) +-#define ADC7D 7 +-#define ADC6D 6 +-#define ADC5D 5 +-#define ADC4D 4 +-#define ADC3D 3 +-#define ADC2D 2 +-#define ADC1D 1 +-#define ADC0D 0 +- +-#define DIDR1 _SFR_MEM8(0x7F) +-#define AIN1D 1 +-#define AIN0D 0 +- +-#define TCCR1A _SFR_MEM8(0x80) +-#define COM1A1 7 +-#define COM1A0 6 +-#define COM1B1 5 +-#define COM1B0 4 +-#define COM1C1 3 +-#define COM1C0 2 +-#define WGM11 1 +-#define WGM10 0 +- +-#define TCCR1B _SFR_MEM8(0x81) +-#define ICNC1 7 +-#define ICES1 6 +-#define WGM13 4 +-#define WGM12 3 +-#define CS12 2 +-#define CS11 1 +-#define CS10 0 +- +-#define TCCR1C _SFR_MEM8(0x82) +-#define FOC1A 7 +-#define FOC1B 6 +-#define FOC1C 5 +- +-/* Reserved [0x83] */ +- +-/* Combine TCNT1L and TCNT1H */ +-#define TCNT1 _SFR_MEM16(0x84) +- +-#define TCNT1L _SFR_MEM8(0x84) +-#define TCNT1H _SFR_MEM8(0x85) +- +-/* Combine ICR1L and ICR1H */ +-#define ICR1 _SFR_MEM16(0x86) +- +-#define ICR1L _SFR_MEM8(0x86) +-#define ICR1H _SFR_MEM8(0x87) +- +-/* Combine OCR1AL and OCR1AH */ +-#define OCR1A _SFR_MEM16(0x88) +- +-#define OCR1AL _SFR_MEM8(0x88) +-#define OCR1AH _SFR_MEM8(0x89) +- +-/* Combine OCR1BL and OCR1BH */ +-#define OCR1B _SFR_MEM16(0x8A) +- +-#define OCR1BL _SFR_MEM8(0x8A) +-#define OCR1BH _SFR_MEM8(0x8B) +- +-/* Combine OCR1CL and OCR1CH */ +-#define OCR1C _SFR_MEM16(0x8C) +- +-#define OCR1CL _SFR_MEM8(0x8C) +-#define OCR1CH _SFR_MEM8(0x8D) +- +-/* Reserved [0x8E..0x8F] */ +- +-#define TCCR3A _SFR_MEM8(0x90) +-#define COM3A1 7 +-#define COM3A0 6 +-#define COM3B1 5 +-#define COM3B0 4 +-#define COM3C1 3 +-#define COM3C0 2 +-#define WGM31 1 +-#define WGM30 0 +- +-#define TCCR3B _SFR_MEM8(0x91) +-#define ICNC3 7 +-#define ICES3 6 +-#define WGM33 4 +-#define WGM32 3 +-#define CS32 2 +-#define CS31 1 +-#define CS30 0 +- +-#define TCCR3C _SFR_MEM8(0x92) +-#define FOC3A 7 +-#define FOC3B 6 +-#define FOC3C 5 +- +-/* Reserved [0x93] */ +- +-/* Combine TCNT3L and TCNT3H */ +-#define TCNT3 _SFR_MEM16(0x94) +- +-#define TCNT3L _SFR_MEM8(0x94) +-#define TCNT3H _SFR_MEM8(0x95) +- +-/* Combine ICR3L and ICR3H */ +-#define ICR3 _SFR_MEM16(0x96) +- +-#define ICR3L _SFR_MEM8(0x96) +-#define ICR3H _SFR_MEM8(0x97) +- +-/* Combine OCR3AL and OCR3AH */ +-#define OCR3A _SFR_MEM16(0x98) +- +-#define OCR3AL _SFR_MEM8(0x98) +-#define OCR3AH _SFR_MEM8(0x99) +- +-/* Combine OCR3BL and OCR3BH */ +-#define OCR3B _SFR_MEM16(0x9A) +- +-#define OCR3BL _SFR_MEM8(0x9A) +-#define OCR3BH _SFR_MEM8(0x9B) +- +-/* Combine OCR3CL and OCR3CH */ +-#define OCR3C _SFR_MEM16(0x9C) +- +-#define OCR3CL _SFR_MEM8(0x9C) +-#define OCR3CH _SFR_MEM8(0x9D) +- +-#if defined(__AT90USBxx7__) +- +-#define UHCON _SFR_MEM8(0x9E) +-#define RESUME 2 +-#define RESET 1 +-#define SOFEN 0 +- +-#define UHINT _SFR_MEM8(0x9F) +-#define HWUPI 6 +-#define HSOFI 5 +-#define RXRSMI 4 +-#define RSMEDI 3 +-#define RSTI 2 +-#define DDISCI 1 +-#define DCONNI 0 +- +-#define UHIEN _SFR_MEM8(0xA0) +-#define HWUPE 6 +-#define HSOFE 5 +-#define RXRSME 4 +-#define RSMEDE 3 +-#define RSTE 2 +-#define DDISCE 1 +-#define DCONNE 0 +- +-#define UHADDR _SFR_MEM8(0xA1) +- +-/* Combine UHFNUML and UHFNUMH */ +-#define UHFNUM _SFR_MEM16(0xA2) +- +-#define UHFNUML _SFR_MEM8(0xA2) +-#define UHFNUMH _SFR_MEM8(0xA3) +- +-#define UHFLEN _SFR_MEM8(0xA4) +- +-#define UPINRQX _SFR_MEM8(0xA5) +- +-#define UPINTX _SFR_MEM8(0xA6) +-#define FIFOCON 7 +-#define NAKEDI 6 +-#define RWAL 5 +-#define PERRI 4 +-#define TXSTPI 3 +-#define TXOUTI 2 +-#define RXSTALLI 1 +-#define RXINI 0 +- +-#define UPNUM _SFR_MEM8(0xA7) +- +-#define UPRST _SFR_MEM8(0xA8) +-#define PRST6 6 +-#define PRST5 5 +-#define PRST4 4 +-#define PRST3 3 +-#define PRST2 2 +-#define PRST1 1 +-#define PRST0 0 +- +-#define UPCONX _SFR_MEM8(0xA9) +-#define PFREEZE 6 +-#define INMODE 5 +-/* #define AUTOSW 4 */ /* Reserved */ +-#define RSTDT 3 +-#define PEN 0 +- +-#define UPCFG0X _SFR_MEM8(0XAA) +-#define PTYPE1 7 +-#define PTYPE0 6 +-#define PTOKEN1 5 +-#define PTOKEN0 4 +-#define PEPNUM3 3 +-#define PEPNUM2 2 +-#define PEPNUM1 1 +-#define PEPNUM0 0 +- +-#define UPCFG1X _SFR_MEM8(0XAB) +-#define PSIZE2 6 +-#define PSIZE1 5 +-#define PSIZE0 4 +-#define PBK1 3 +-#define PBK0 2 +-#define ALLOC 1 +- +-#define UPSTAX _SFR_MEM8(0XAC) +-#define CFGOK 7 +-#define OVERFI 6 +-#define UNDERFI 5 +-#define DTSEQ1 3 +-#define DTSEQ0 2 +-#define NBUSYBK1 1 +-#define NBUSYBK0 0 +- +-#define UPCFG2X _SFR_MEM8(0XAD) +- +-#define UPIENX _SFR_MEM8(0XAE) +-#define FLERRE 7 +-#define NAKEDE 6 +-#define PERRE 4 +-#define TXSTPE 3 +-#define TXOUTE 2 +-#define RXSTALLE 1 +-#define RXINE 0 +- +-#define UPDATX _SFR_MEM8(0XAF) +- +-#endif /* __AT90USBxx7__ */ +- +-#define TCCR2A _SFR_MEM8(0xB0) +-#define COM2A1 7 +-#define COM2A0 6 +-#define COM2B1 5 +-#define COM2B0 4 +-#define WGM21 1 +-#define WGM20 0 +- +-#define TCCR2B _SFR_MEM8(0xB1) +-#define FOC2A 7 +-#define FOC2B 6 +-#define WGM22 3 +-#define CS22 2 +-#define CS21 1 +-#define CS20 0 +- +-#define TCNT2 _SFR_MEM8(0xB2) +- +-#define OCR2A _SFR_MEM8(0xB3) +- +-#define OCR2B _SFR_MEM8(0xB4) +- +-/* Reserved [0xB5] */ +- +-#define ASSR _SFR_MEM8(0xB6) +-#define EXCLK 6 +-#define AS2 5 +-#define TCN2UB 4 +-#define OCR2AUB 3 +-#define OCR2BUB 2 +-#define TCR2AUB 1 +-#define TCR2BUB 0 +- +-/* Reserved [0xB7] */ +- +-#define TWBR _SFR_MEM8(0xB8) +- +-#define TWSR _SFR_MEM8(0xB9) +-#define TWS7 7 +-#define TWS6 6 +-#define TWS5 5 +-#define TWS4 4 +-#define TWS3 3 +-#define TWPS1 1 +-#define TWPS0 0 +- +-#define TWAR _SFR_MEM8(0xBA) +-#define TWA6 7 +-#define TWA5 6 +-#define TWA4 5 +-#define TWA3 4 +-#define TWA2 3 +-#define TWA1 2 +-#define TWA0 1 +-#define TWGCE 0 +- +-#define TWDR _SFR_MEM8(0xBB) +- +-#define TWCR _SFR_MEM8(0xBC) +-#define TWINT 7 +-#define TWEA 6 +-#define TWSTA 5 +-#define TWSTO 4 +-#define TWWC 3 +-#define TWEN 2 +-#define TWIE 0 +- +-#define TWAMR _SFR_MEM8(0xBD) +-#define TWAM6 7 +-#define TWAM5 6 +-#define TWAM4 5 +-#define TWAM3 4 +-#define TWAM2 3 +-#define TWAM1 2 +-#define TWAM0 1 +- +-/* Reserved [0xBE..0xC7] */ +- +-#define UCSR1A _SFR_MEM8(0xC8) +-#define RXC1 7 +-#define TXC1 6 +-#define UDRE1 5 +-#define FE1 4 +-#define DOR1 3 +-#define UPE1 2 +-#define U2X1 1 +-#define MPCM1 0 +- +-#define UCSR1B _SFR_MEM8(0XC9) +-#define RXCIE1 7 +-#define TXCIE1 6 +-#define UDRIE1 5 +-#define RXEN1 4 +-#define TXEN1 3 +-#define UCSZ12 2 +-#define RXB81 1 +-#define TXB81 0 +- +-#define UCSR1C _SFR_MEM8(0xCA) +-#define UMSEL11 7 +-#define UMSEL10 6 +-#define UPM11 5 +-#define UPM10 4 +-#define USBS1 3 +-#define UCSZ11 2 +-#define UCSZ10 1 +-#define UCPOL1 0 +- +-/* Reserved [0xCB] */ +- +-/* Combine UBRR1L and UBRR1H */ +-#define UBRR1 _SFR_MEM16(0xCC) +- +-#define UBRR1L _SFR_MEM8(0xCC) +-#define UBRR1H _SFR_MEM8(0xCD) +- +-#define UDR1 _SFR_MEM8(0XCE) +- +-/* Reserved [0xCF..0xD6] */ +- +-#define UHWCON _SFR_MEM8(0XD7) +-#define UIMOD 7 +-#define UIDE 6 +-#define UVCONE 4 +-#define UVREGE 0 +- +-#define USBCON _SFR_MEM8(0XD8) +-#define USBE 7 +-#define HOST 6 +-#define FRZCLK 5 +-#define OTGPADE 4 +-#define IDTE 1 +-#define VBUSTE 0 +- +-#define USBSTA _SFR_MEM8(0XD9) +-#define SPEED 3 +-#define ID 1 +-#define VBUS 0 +- +-#define USBINT _SFR_MEM8(0XDA) +-#define IDTI 1 +-#define VBUSTI 0 +- +-/* Combine UDPADDL and UDPADDH */ +-#define UDPADD _SFR_MEM16(0xDB) +- +-#define UDPADDL _SFR_MEM8(0xDB) +-#define UDPADDH _SFR_MEM8(0xDC) +-#define DPACC 7 +- +-#if defined(__AT90USBxx7__) +- +-#define OTGCON _SFR_MEM8(0XDD) +-#define HNPREQ 5 +-#define SRPREQ 4 +-#define SRPSEL 3 +-#define VBUSHWC 2 +-#define VBUSREQ 1 +-#define VBUSRQC 0 +- +-#define OTGIEN _SFR_MEM8(0XDE) +-#define STOE 5 +-#define HNPERRE 4 +-#define ROLEEXE 3 +-#define BCERRE 2 +-#define VBERRE 1 +-#define SRPE 0 +- +-#define OTGINT _SFR_MEM8(0XDF) +-#define STOI 5 +-#define HNPERRI 4 +-#define ROLEEXI 3 +-#define BCERRI 2 +-#define VBERRI 1 +-#define SRPI 0 +- +-#endif /* __AT90USBxx7__ */ +- +-#define UDCON _SFR_MEM8(0XE0) +-#define LSM 2 +-#define RMWKUP 1 +-#define DETACH 0 +- +-#define UDINT _SFR_MEM8(0XE1) +-#define UPRSMI 6 +-#define EORSMI 5 +-#define WAKEUPI 4 +-#define EORSTI 3 +-#define SOFI 2 +-/* #define MSOFI 1 */ /* Reserved */ +-#define SUSPI 0 +- +-#define UDIEN _SFR_MEM8(0XE2) +-#define UPRSME 6 +-#define EORSME 5 +-#define WAKEUPE 4 +-#define EORSTE 3 +-#define SOFE 2 +-/* #define MSOFE 1 */ /* Reserved */ +-#define SUSPE 0 +- +-#define UDADDR _SFR_MEM8(0XE3) +-#define ADDEN 7 +- +-/* Combine UDFNUML and UDFNUMH */ +-#define UDFNUM _SFR_MEM16(0xE4) +- +-#define UDFNUML _SFR_MEM8(0xE4) +-#define UDFNUMH _SFR_MEM8(0xE5) +- +-#define UDMFN _SFR_MEM8(0XE6) +-#define FNCERR 4 +- +-#define UDTST _SFR_MEM8(0XE7) +-#define OPMODE2 5 +-#define TSTPCKT 4 +-#define TSTK 3 +-#define TSTJ 2 +- +-#define UEINTX _SFR_MEM8(0XE8) +-#define FIFOCON 7 +-#define NAKINI 6 +-#define RWAL 5 +-#define NAKOUTI 4 +-#define RXSTPI 3 +-#define RXOUTI 2 +-#define STALLEDI 1 +-#define TXINI 0 +- +-#define UENUM _SFR_MEM8(0XE9) +- +-#define UERST _SFR_MEM8(0XEA) +-#define EPRST6 6 +-#define EPRST5 5 +-#define EPRST4 4 +-#define EPRST3 3 +-#define EPRST2 2 +-#define EPRST1 1 +-#define EPRST0 0 +- +-#define UECONX _SFR_MEM8(0XEB) +-#define STALLRQ 5 +-#define STALLRQC 4 +-#define RSTDT 3 +-#define EPEN 0 +- +-#define UECFG0X _SFR_MEM8(0XEC) +-#define EPTYPE1 7 +-#define EPTYPE0 6 +-/* #define ISOSW 3 */ /* Reserved */ +-/* #define AUTOSW 2 */ /* Reserved */ +-/* #define NYETSDIS 1 */ /* Reserved */ +-#define EPDIR 0 +- +-#define UECFG1X _SFR_MEM8(0XED) +-#define EPSIZE2 6 +-#define EPSIZE1 5 +-#define EPSIZE0 4 +-#define EPBK1 3 +-#define EPBK0 2 +-#define ALLOC 1 +- +-#define UESTA0X _SFR_MEM8(0XEE) +-#define CFGOK 7 +-#define OVERFI 6 +-#define UNDERFI 5 +-#define ZLPSEEN 4 +-#define DTSEQ1 3 +-#define DTSEQ0 2 +-#define NBUSYBK1 1 +-#define NBUSYBK0 0 +- +-#define UESTA1X _SFR_MEM8(0XEF) +-#define CTRLDIR 2 +-#define CURRBK1 1 +-#define CURRBK0 0 +- +-#define UEIENX _SFR_MEM8(0XF0) +-#define FLERRE 7 +-#define NAKINE 6 +-#define NAKOUTE 4 +-#define RXSTPE 3 +-#define RXOUTE 2 +-#define STALLEDE 1 +-#define TXINE 0 +- +-#define UEDATX _SFR_MEM8(0XF1) +- +-/* Combine UEBCLX and UEBCHX */ +-#define UEBCX _SFR_MEM16(0xF2) +- +-#define UEBCLX _SFR_MEM8(0xF2) +-#define UEBCHX _SFR_MEM8(0xF3) +- +-#define UEINT _SFR_MEM8(0XF4) +-#define EPINT6 6 +-#define EPINT5 5 +-#define EPINT4 4 +-#define EPINT3 3 +-#define EPINT2 2 +-#define EPINT1 1 +-#define EPINT0 0 +- +-#if defined(__AT90USBxx7__) +- +-#define UPERRX _SFR_MEM8(0XF5) +-#define COUNTER1 6 +-#define COUNTER0 5 +-#define CRC16 4 +-#define TIMEOUT 3 +-#define PID 2 +-#define DATAPID 1 +-#define DATATGL 0 +- +-/* Combine UPBCLX and UPBCHX */ +-#define UPBCX _SFR_MEM16(0xF6) +- +-#define UPBCLX _SFR_MEM8(0xF6) +-#define UPBCHX _SFR_MEM8(0xF7) +- +-#define UPINT _SFR_MEM8(0XF8) +-#define PINT6 6 +-#define PINT5 5 +-#define PINT4 4 +-#define PINT3 3 +-#define PINT2 2 +-#define PINT1 1 +-#define PINT0 0 +- +-#define OTGTCON _SFR_MEM8(0XF9) +-#define PAGE1 6 +-#define PAGE0 5 +-#define VALUE1 1 +-#define VALUE0 0 +- +-#endif /* __AT90USBxx7__ */ +- +-/* Reserved [0xFA..0xFF] */ +- +-/* Interrupt vectors */ +- +-/* External Interrupt Request 0 */ +-#define INT0_vect_num 1 +-#define INT0_vect _VECTOR(1) +- +-/* External Interrupt Request 1 */ +-#define INT1_vect_num 2 +-#define INT1_vect _VECTOR(2) +- +-/* External Interrupt Request 2 */ +-#define INT2_vect_num 3 +-#define INT2_vect _VECTOR(3) +- +-/* External Interrupt Request 3 */ +-#define INT3_vect_num 4 +-#define INT3_vect _VECTOR(4) +- +-/* External Interrupt Request 4 */ +-#define INT4_vect_num 5 +-#define INT4_vect _VECTOR(5) +- +-/* External Interrupt Request 5 */ +-#define INT5_vect_num 6 +-#define INT5_vect _VECTOR(6) +- +-/* External Interrupt Request 6 */ +-#define INT6_vect_num 7 +-#define INT6_vect _VECTOR(7) +- +-/* External Interrupt Request 7 */ +-#define INT7_vect_num 8 +-#define INT7_vect _VECTOR(8) +- +-/* Pin Change Interrupt Request 0 */ +-#define PCINT0_vect_num 9 +-#define PCINT0_vect _VECTOR(9) +- +-/* USB General Interrupt Request */ +-#define USB_GEN_vect_num 10 +-#define USB_GEN_vect _VECTOR(10) +- +-/* USB Endpoint/Pipe Interrupt Communication Request */ +-#define USB_COM_vect_num 11 +-#define USB_COM_vect _VECTOR(11) +- +-/* Watchdog Time-out Interrupt */ +-#define WDT_vect_num 12 +-#define WDT_vect _VECTOR(12) +- +-/* Timer/Counter2 Compare Match A */ +-#define TIMER2_COMPA_vect_num 13 +-#define TIMER2_COMPA_vect _VECTOR(13) +- +-/* Timer/Counter2 Compare Match B */ +-#define TIMER2_COMPB_vect_num 14 +-#define TIMER2_COMPB_vect _VECTOR(14) +- +-/* Timer/Counter2 Overflow */ +-#define TIMER2_OVF_vect_num 15 +-#define TIMER2_OVF_vect _VECTOR(15) +- +-/* Timer/Counter1 Capture Event */ +-#define TIMER1_CAPT_vect_num 16 +-#define TIMER1_CAPT_vect _VECTOR(16) +- +-/* Timer/Counter1 Compare Match A */ +-#define TIMER1_COMPA_vect_num 17 +-#define TIMER1_COMPA_vect _VECTOR(17) +- +-/* Timer/Counter1 Compare Match B */ +-#define TIMER1_COMPB_vect_num 18 +-#define TIMER1_COMPB_vect _VECTOR(18) +- +-/* Timer/Counter1 Compare Match C */ +-#define TIMER1_COMPC_vect_num 19 +-#define TIMER1_COMPC_vect _VECTOR(19) +- +-/* Timer/Counter1 Overflow */ +-#define TIMER1_OVF_vect_num 20 +-#define TIMER1_OVF_vect _VECTOR(20) +- +-/* Timer/Counter0 Compare Match A */ +-#define TIMER0_COMPA_vect_num 21 +-#define TIMER0_COMPA_vect _VECTOR(21) +- +-/* Timer/Counter0 Compare Match B */ +-#define TIMER0_COMPB_vect_num 22 +-#define TIMER0_COMPB_vect _VECTOR(22) +- +-/* Timer/Counter0 Overflow */ +-#define TIMER0_OVF_vect_num 23 +-#define TIMER0_OVF_vect _VECTOR(23) +- +-/* SPI Serial Transfer Complete */ +-#define SPI_STC_vect_num 24 +-#define SPI_STC_vect _VECTOR(24) +- +-/* USART1, Rx Complete */ +-#define USART1_RX_vect_num 25 +-#define USART1_RX_vect _VECTOR(25) +- +-/* USART1 Data register Empty */ +-#define USART1_UDRE_vect_num 26 +-#define USART1_UDRE_vect _VECTOR(26) +- +-/* USART1, Tx Complete */ +-#define USART1_TX_vect_num 27 +-#define USART1_TX_vect _VECTOR(27) +- +-/* Analog Comparator */ +-#define ANALOG_COMP_vect_num 28 +-#define ANALOG_COMP_vect _VECTOR(28) +- +-/* ADC Conversion Complete */ +-#define ADC_vect_num 29 +-#define ADC_vect _VECTOR(29) +- +-/* EEPROM Ready */ +-#define EE_READY_vect_num 30 +-#define EE_READY_vect _VECTOR(30) +- +-/* Timer/Counter3 Capture Event */ +-#define TIMER3_CAPT_vect_num 31 +-#define TIMER3_CAPT_vect _VECTOR(31) +- +-/* Timer/Counter3 Compare Match A */ +-#define TIMER3_COMPA_vect_num 32 +-#define TIMER3_COMPA_vect _VECTOR(32) +- +-/* Timer/Counter3 Compare Match B */ +-#define TIMER3_COMPB_vect_num 33 +-#define TIMER3_COMPB_vect _VECTOR(33) +- +-/* Timer/Counter3 Compare Match C */ +-#define TIMER3_COMPC_vect_num 34 +-#define TIMER3_COMPC_vect _VECTOR(34) +- +-/* Timer/Counter3 Overflow */ +-#define TIMER3_OVF_vect_num 35 +-#define TIMER3_OVF_vect _VECTOR(35) +- +-/* 2-wire Serial Interface */ +-#define TWI_vect_num _VECTOR(36) +-#define TWI_vect _VECTOR(36) +- +-/* Store Program Memory Read */ +-#define SPM_READY_vect_num 37 +-#define SPM_READY_vect _VECTOR(37) +- +-#define _VECTORS_SIZE 152 +- +-#if defined(__AT90USBxx6__) +-# undef __AT90USBxx6__ +-#endif /* __AT90USBxx6__ */ +- +-#if defined(__AT90USBxx7__) +-# undef __AT90USBxx7__ +-#endif /* __AT90USBxx7__ */ +- +-#endif /* _AVR_IOUSBXX6_7_H_ */ ++/* Copyright (c) 2006, Anatoly Sokolov ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iousbxx6_7.h 2225 2011-03-02 16:27:26Z arcanum $ */ ++ ++/* iousbxx6_7.h - definitions for AT90USB646, AT90USB647, AT90USB1286 ++ and AT90USB1287 */ ++ ++#ifndef _AVR_IOUSBXX6_7_H_ ++#define _AVR_IOUSBXX6_7_H_ 1 ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iousbxx6_7.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#if defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__) ++# define __AT90USBxx6__ 1 ++#elif defined(__AVR_AT90USB647__) || defined(__AVR_AT90USB1287__) ++# define __AT90USBxx7__ 1 ++#endif ++ ++/* Registers and associated bit numbers */ ++ ++#define PINA _SFR_IO8(0X00) ++#define PINA7 7 ++#define PINA6 6 ++#define PINA5 5 ++#define PINA4 4 ++#define PINA3 3 ++#define PINA2 2 ++#define PINA1 1 ++#define PINA0 0 ++ ++#define DDRA _SFR_IO8(0X01) ++#define DDA7 7 ++#define DDA6 6 ++#define DDA5 5 ++#define DDA4 4 ++#define DDA3 3 ++#define DDA2 2 ++#define DDA1 1 ++#define DDA0 0 ++ ++#define PORTA _SFR_IO8(0X02) ++#define PA7 7 ++#define PA6 6 ++#define PA5 5 ++#define PA4 4 ++#define PA3 3 ++#define PA2 2 ++#define PA1 1 ++#define PA0 0 ++ ++#define PINB _SFR_IO8(0X03) ++#define PINB7 7 ++#define PINB6 6 ++#define PINB5 5 ++#define PINB4 4 ++#define PINB3 3 ++#define PINB2 2 ++#define PINB1 1 ++#define PINB0 0 ++ ++#define DDRB _SFR_IO8(0x04) ++#define DDB7 7 ++#define DDB6 6 ++#define DDB5 5 ++#define DDB4 4 ++#define DDB3 3 ++#define DDB2 2 ++#define DDB1 1 ++#define DDB0 0 ++ ++#define PORTB _SFR_IO8(0x05) ++#define PB7 7 ++#define PB6 6 ++#define PB5 5 ++#define PB4 4 ++#define PB3 3 ++#define PB2 2 ++#define PB1 1 ++#define PB0 0 ++ ++#define PINC _SFR_IO8(0x06) ++#define PINC7 7 ++#define PINC6 6 ++#define PINC5 5 ++#define PINC4 4 ++#define PINC3 3 ++#define PINC2 2 ++#define PINC1 1 ++#define PINC0 0 ++ ++#define DDRC _SFR_IO8(0x07) ++#define DDC7 7 ++#define DDC6 6 ++#define DDC5 5 ++#define DDC4 4 ++#define DDC3 3 ++#define DDC2 2 ++#define DDC1 1 ++#define DDC0 0 ++ ++#define PORTC _SFR_IO8(0x08) ++#define PC7 7 ++#define PC6 6 ++#define PC5 5 ++#define PC4 4 ++#define PC3 3 ++#define PC2 2 ++#define PC1 1 ++#define PC0 0 ++ ++#define PIND _SFR_IO8(0x09) ++#define PIND7 7 ++#define PIND6 6 ++#define PIND5 5 ++#define PIND4 4 ++#define PIND3 3 ++#define PIND2 2 ++#define PIND1 1 ++#define PIND0 0 ++ ++#define DDRD _SFR_IO8(0x0A) ++#define DDD7 7 ++#define DDD6 6 ++#define DDD5 5 ++#define DDD4 4 ++#define DDD3 3 ++#define DDD2 2 ++#define DDD1 1 ++#define DDD0 0 ++ ++#define PORTD _SFR_IO8(0x0B) ++#define PD7 7 ++#define PD6 6 ++#define PD5 5 ++#define PD4 4 ++#define PD3 3 ++#define PD2 2 ++#define PD1 1 ++#define PD0 0 ++ ++#define PINE _SFR_IO8(0x0C) ++#define PINE7 7 ++#define PINE6 6 ++#define PINE5 5 ++#define PINE4 4 ++#define PINE3 3 ++#define PINE2 2 ++#define PINE1 1 ++#define PINE0 0 ++ ++#define DDRE _SFR_IO8(0x0D) ++#define DDE7 7 ++#define DDE6 6 ++#define DDE5 5 ++#define DDE4 4 ++#define DDE3 3 ++#define DDE2 2 ++#define DDE1 1 ++#define DDE0 0 ++ ++#define PORTE _SFR_IO8(0x0E) ++#define PE7 7 ++#define PE6 6 ++#define PE5 5 ++#define PE4 4 ++#define PE3 3 ++#define PE2 2 ++#define PE1 1 ++#define PE0 0 ++ ++#define PINF _SFR_IO8(0x0F) ++#define PINF7 7 ++#define PINF6 6 ++#define PINF5 5 ++#define PINF4 4 ++#define PINF3 3 ++#define PINF2 2 ++#define PINF1 1 ++#define PINF0 0 ++ ++#define DDRF _SFR_IO8(0x10) ++#define DDF7 7 ++#define DDF6 6 ++#define DDF5 5 ++#define DDF4 4 ++#define DDF3 3 ++#define DDF2 2 ++#define DDF1 1 ++#define DDF0 0 ++ ++#define PORTF _SFR_IO8(0x11) ++#define PF7 7 ++#define PF6 6 ++#define PF5 5 ++#define PF4 4 ++#define PF3 3 ++#define PF2 2 ++#define PF1 1 ++#define PF0 0 ++ ++/* Reserved [0x12..0x14] */ ++ ++#define TIFR0 _SFR_IO8(0x15) ++#define OCF0B 2 ++#define OCF0A 1 ++#define TOV0 0 ++ ++#define TIFR1 _SFR_IO8(0x16) ++#define ICF1 5 ++#define OCF1C 3 ++#define OCF1B 2 ++#define OCF1A 1 ++#define TOV1 0 ++ ++#define TIFR2 _SFR_IO8(0x17) ++#define OCF2B 2 ++#define OCF2A 1 ++#define TOV2 0 ++ ++#define TIFR3 _SFR_IO8(0x18) ++#define ICF3 5 ++#define OCF3C 3 ++#define OCF3B 2 ++#define OCF3A 1 ++#define TOV3 0 ++ ++/* Reserved [0x19..0x1A] */ ++ ++#define PCIFR _SFR_IO8(0x1B) ++#define PCIF0 0 ++ ++#define EIFR _SFR_IO8(0x1C) ++#define INTF7 7 ++#define INTF6 6 ++#define INTF5 5 ++#define INTF4 4 ++#define INTF3 3 ++#define INTF2 2 ++#define INTF1 1 ++#define INTF0 0 ++ ++#define EIMSK _SFR_IO8(0x1D) ++#define INT7 7 ++#define INT6 6 ++#define INT5 5 ++#define INT4 4 ++#define INT3 3 ++#define INT2 2 ++#define INT1 1 ++#define INT0 0 ++ ++#define GPIOR0 _SFR_IO8(0x1E) ++ ++#define EECR _SFR_IO8(0x1F) ++#define EEPM1 5 ++#define EEPM0 4 ++#define EERIE 3 ++#define EEMPE 2 ++#define EEPE 1 ++#define EERE 0 ++ ++#define EEDR _SFR_IO8(0x20) ++ ++#define EEAR _SFR_IO16(0x21) ++#define EEARL _SFR_IO8(0x21) ++#define EEARH _SFR_IO8(0x22) ++ ++/* 6-char sequence denoting where to find the EEPROM registers in memory space. ++ Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM ++ subroutines. ++ First two letters: EECR address. ++ Second two letters: EEDR address. ++ Last two letters: EEAR address. */ ++#define __EEPROM_REG_LOCATIONS__ 1F2021 ++ ++#define GTCCR _SFR_IO8(0x23) ++#define TSM 7 ++#define PSRASY 1 ++#define PSRSYNC 0 ++ ++#define TCCR0A _SFR_IO8(0x24) ++#define COM0A1 7 ++#define COM0A0 6 ++#define COM0B1 5 ++#define COM0B0 4 ++#define WGM01 1 ++#define WGM00 0 ++ ++#define TCCR0B _SFR_IO8(0x25) ++#define FOC0A 7 ++#define FOC0B 6 ++#define WGM02 3 ++#define CS02 2 ++#define CS01 1 ++#define CS00 0 ++ ++#define TCNT0 _SFR_IO8(0X26) ++ ++#define OCR0A _SFR_IO8(0x27) ++ ++#define OCR0B _SFR_IO8(0X28) ++ ++#define PLLCSR _SFR_IO8(0x29) ++#define PLLP2 4 ++#define PLLP1 3 ++#define PLLP0 2 ++#define PLLE 1 ++#define PLOCK 0 ++ ++#define GPIOR1 _SFR_IO8(0x2A) ++ ++#define GPIOR2 _SFR_IO8(0x2B) ++ ++#define SPCR _SFR_IO8(0x2C) ++#define SPIE 7 ++#define SPE 6 ++#define DORD 5 ++#define MSTR 4 ++#define CPOL 3 ++#define CPHA 2 ++#define SPR1 1 ++#define SPR0 0 ++ ++#define SPSR _SFR_IO8(0x2D) ++#define SPIF 7 ++#define WCOL 6 ++#define SPI2X 0 ++ ++#define SPDR _SFR_IO8(0x2E) ++ ++/* Reserved [0x2F] */ ++ ++#define ACSR _SFR_IO8(0x30) ++#define ACD 7 ++#define ACBG 6 ++#define ACO 5 ++#define ACI 4 ++#define ACIE 3 ++#define ACIC 2 ++#define ACIS1 1 ++#define ACIS0 0 ++ ++#define MONDR _SFR_IO8(0x31) ++#define OCDR _SFR_IO8(0x31) ++#define IDRD 7 ++#define OCDR7 7 ++#define OCDR6 6 ++#define OCDR5 5 ++#define OCDR4 4 ++#define OCDR3 3 ++#define OCDR2 2 ++#define OCDR1 1 ++#define OCDR0 0 ++ ++/* Reserved [0x32] */ ++ ++#define SMCR _SFR_IO8(0x33) ++#define SM2 3 ++#define SM1 2 ++#define SM0 1 ++#define SE 0 ++ ++#define MCUSR _SFR_IO8(0x34) ++#define JTRF 4 ++#define WDRF 3 ++#define BORF 2 ++#define EXTRF 1 ++#define PORF 0 ++ ++#define MCUCR _SFR_IO8(0x35) ++#define JTD 7 ++#define PUD 4 ++#define IVSEL 1 ++#define IVCE 0 ++ ++/* Reserved [0x36] */ ++ ++#define SPMCSR _SFR_IO8(0x37) ++#define SPMIE 7 ++#define RWWSB 6 ++#define SIGRD 5 ++#define RWWSRE 4 ++#define BLBSET 3 ++#define PGWRT 2 ++#define PGERS 1 ++#define SPMEN 0 ++ ++/* Reserved [0x38..0x3A] */ ++ ++#if defined(__AVR_AT90USB1286__) || defined(__AVR_AT90USB1287__) ++#define RAMPZ _SFR_IO8(0x3B) ++#endif ++ ++/* Reserved [0x3C] */ ++ ++/* SP [0x3D..0x3E] */ ++/* SREG [0x3F] */ ++ ++#define WDTCSR _SFR_MEM8(0x60) ++#define WDIF 7 ++#define WDIE 6 ++#define WDP3 5 ++#define WDCE 4 ++#define WDE 3 ++#define WDP2 2 ++#define WDP1 1 ++#define WDP0 0 ++ ++#define CLKPR _SFR_MEM8(0x61) ++#define CLKPCE 7 ++#define CLKPS3 3 ++#define CLKPS2 2 ++#define CLKPS1 1 ++#define CLKPS0 0 ++ ++/* Reserved [0x62..0x63] */ ++ ++#define PRR0 _SFR_MEM8(0x64) ++#define PRTWI 7 ++#define PRTIM2 6 ++#define PRTIM0 5 ++#define PRTIM1 3 ++#define PRSPI 2 ++#define PRADC 0 ++ ++#define PRR1 _SFR_MEM8(0x65) ++#define PRUSB 7 ++#define PRTIM3 3 ++#define PRUSART1 0 ++ ++#define OSCCAL _SFR_MEM8(0x66) ++ ++/* Reserved [0x67] */ ++ ++#define PCICR _SFR_MEM8(0x68) ++#define PCIE0 0 ++ ++#define EICRA _SFR_MEM8(0x69) ++#define ISC31 7 ++#define ISC30 6 ++#define ISC21 5 ++#define ISC20 4 ++#define ISC11 3 ++#define ISC10 2 ++#define ISC01 1 ++#define ISC00 0 ++ ++#define EICRB _SFR_MEM8(0x6A) ++#define ISC71 7 ++#define ISC70 6 ++#define ISC61 5 ++#define ISC60 4 ++#define ISC51 3 ++#define ISC50 2 ++#define ISC41 1 ++#define ISC40 0 ++ ++#define PCMSK0 _SFR_MEM8(0x6B) ++#define PCINT7 7 ++#define PCINT6 6 ++#define PCINT5 5 ++#define PCINT4 4 ++#define PCINT3 3 ++#define PCINT2 2 ++#define PCINT1 1 ++#define PCINT0 0 ++ ++/* Reserved [0x6C..0x6D] */ ++ ++#define TIMSK0 _SFR_MEM8(0x6E) ++#define OCIE0B 2 ++#define OCIE0A 1 ++#define TOIE0 0 ++ ++#define TIMSK1 _SFR_MEM8(0x6F) ++#define ICIE1 5 ++#define OCIE1C 3 ++#define OCIE1B 2 ++#define OCIE1A 1 ++#define TOIE1 0 ++ ++#define TIMSK2 _SFR_MEM8(0x70) ++#define OCIE2B 2 ++#define OCIE2A 1 ++#define TOIE2 0 ++ ++#define TIMSK3 _SFR_MEM8(0x71) ++#define ICIE3 5 ++#define OCIE3C 3 ++#define OCIE3B 2 ++#define OCIE3A 1 ++#define TOIE3 0 ++ ++/* Reserved [0x72..0x73] */ ++ ++#define XMCRA _SFR_MEM8(0x74) ++#define SRE 7 ++#define SRL2 6 ++#define SRL1 5 ++#define SRL0 4 ++#define SRW11 3 ++#define SRW10 2 ++#define SRW01 1 ++#define SRW00 0 ++ ++#define XMCRB _SFR_MEM8(0x75) ++#define XMBK 7 ++#define XMM2 2 ++#define XMM1 1 ++#define XMM0 0 ++ ++/* Reserved [0x76..0x77] */ ++ ++/* RegDef: ADC Data Register */ ++#ifndef __ASSEMBLER__ ++#define ADC _SFR_MEM16(0x78) ++#endif ++#define ADCW _SFR_MEM16(0x78) ++#define ADCL _SFR_MEM8(0x78) ++#define ADCH _SFR_MEM8(0x79) ++ ++#define ADCSRA _SFR_MEM8(0x7A) ++#define ADEN 7 ++#define ADSC 6 ++#define ADATE 5 ++#define ADIF 4 ++#define ADIE 3 ++#define ADPS2 2 ++#define ADPS1 1 ++#define ADPS0 0 ++ ++#define ADCSRB _SFR_MEM8(0x7B) ++#define ACME 6 ++#define ADTS2 2 ++#define ADTS1 1 ++#define ADTS0 0 ++ ++#define ADMUX _SFR_MEM8(0x7C) ++#define REFS1 7 ++#define REFS0 6 ++#define ADLAR 5 ++#define MUX4 4 ++#define MUX3 3 ++#define MUX2 2 ++#define MUX1 1 ++#define MUX0 0 ++ ++/* Reserved [0x7D] */ ++ ++#define DIDR0 _SFR_MEM8(0x7E) ++#define ADC7D 7 ++#define ADC6D 6 ++#define ADC5D 5 ++#define ADC4D 4 ++#define ADC3D 3 ++#define ADC2D 2 ++#define ADC1D 1 ++#define ADC0D 0 ++ ++#define DIDR1 _SFR_MEM8(0x7F) ++#define AIN1D 1 ++#define AIN0D 0 ++ ++#define TCCR1A _SFR_MEM8(0x80) ++#define COM1A1 7 ++#define COM1A0 6 ++#define COM1B1 5 ++#define COM1B0 4 ++#define COM1C1 3 ++#define COM1C0 2 ++#define WGM11 1 ++#define WGM10 0 ++ ++#define TCCR1B _SFR_MEM8(0x81) ++#define ICNC1 7 ++#define ICES1 6 ++#define WGM13 4 ++#define WGM12 3 ++#define CS12 2 ++#define CS11 1 ++#define CS10 0 ++ ++#define TCCR1C _SFR_MEM8(0x82) ++#define FOC1A 7 ++#define FOC1B 6 ++#define FOC1C 5 ++ ++/* Reserved [0x83] */ ++ ++/* Combine TCNT1L and TCNT1H */ ++#define TCNT1 _SFR_MEM16(0x84) ++ ++#define TCNT1L _SFR_MEM8(0x84) ++#define TCNT1H _SFR_MEM8(0x85) ++ ++/* Combine ICR1L and ICR1H */ ++#define ICR1 _SFR_MEM16(0x86) ++ ++#define ICR1L _SFR_MEM8(0x86) ++#define ICR1H _SFR_MEM8(0x87) ++ ++/* Combine OCR1AL and OCR1AH */ ++#define OCR1A _SFR_MEM16(0x88) ++ ++#define OCR1AL _SFR_MEM8(0x88) ++#define OCR1AH _SFR_MEM8(0x89) ++ ++/* Combine OCR1BL and OCR1BH */ ++#define OCR1B _SFR_MEM16(0x8A) ++ ++#define OCR1BL _SFR_MEM8(0x8A) ++#define OCR1BH _SFR_MEM8(0x8B) ++ ++/* Combine OCR1CL and OCR1CH */ ++#define OCR1C _SFR_MEM16(0x8C) ++ ++#define OCR1CL _SFR_MEM8(0x8C) ++#define OCR1CH _SFR_MEM8(0x8D) ++ ++/* Reserved [0x8E..0x8F] */ ++ ++#define TCCR3A _SFR_MEM8(0x90) ++#define COM3A1 7 ++#define COM3A0 6 ++#define COM3B1 5 ++#define COM3B0 4 ++#define COM3C1 3 ++#define COM3C0 2 ++#define WGM31 1 ++#define WGM30 0 ++ ++#define TCCR3B _SFR_MEM8(0x91) ++#define ICNC3 7 ++#define ICES3 6 ++#define WGM33 4 ++#define WGM32 3 ++#define CS32 2 ++#define CS31 1 ++#define CS30 0 ++ ++#define TCCR3C _SFR_MEM8(0x92) ++#define FOC3A 7 ++#define FOC3B 6 ++#define FOC3C 5 ++ ++/* Reserved [0x93] */ ++ ++/* Combine TCNT3L and TCNT3H */ ++#define TCNT3 _SFR_MEM16(0x94) ++ ++#define TCNT3L _SFR_MEM8(0x94) ++#define TCNT3H _SFR_MEM8(0x95) ++ ++/* Combine ICR3L and ICR3H */ ++#define ICR3 _SFR_MEM16(0x96) ++ ++#define ICR3L _SFR_MEM8(0x96) ++#define ICR3H _SFR_MEM8(0x97) ++ ++/* Combine OCR3AL and OCR3AH */ ++#define OCR3A _SFR_MEM16(0x98) ++ ++#define OCR3AL _SFR_MEM8(0x98) ++#define OCR3AH _SFR_MEM8(0x99) ++ ++/* Combine OCR3BL and OCR3BH */ ++#define OCR3B _SFR_MEM16(0x9A) ++ ++#define OCR3BL _SFR_MEM8(0x9A) ++#define OCR3BH _SFR_MEM8(0x9B) ++ ++/* Combine OCR3CL and OCR3CH */ ++#define OCR3C _SFR_MEM16(0x9C) ++ ++#define OCR3CL _SFR_MEM8(0x9C) ++#define OCR3CH _SFR_MEM8(0x9D) ++ ++#if defined(__AT90USBxx7__) ++ ++#define UHCON _SFR_MEM8(0x9E) ++#define RESUME 2 ++#define RESET 1 ++#define SOFEN 0 ++ ++#define UHINT _SFR_MEM8(0x9F) ++#define HWUPI 6 ++#define HSOFI 5 ++#define RXRSMI 4 ++#define RSMEDI 3 ++#define RSTI 2 ++#define DDISCI 1 ++#define DCONNI 0 ++ ++#define UHIEN _SFR_MEM8(0xA0) ++#define HWUPE 6 ++#define HSOFE 5 ++#define RXRSME 4 ++#define RSMEDE 3 ++#define RSTE 2 ++#define DDISCE 1 ++#define DCONNE 0 ++ ++#define UHADDR _SFR_MEM8(0xA1) ++ ++/* Combine UHFNUML and UHFNUMH */ ++#define UHFNUM _SFR_MEM16(0xA2) ++ ++#define UHFNUML _SFR_MEM8(0xA2) ++#define UHFNUMH _SFR_MEM8(0xA3) ++ ++#define UHFLEN _SFR_MEM8(0xA4) ++ ++#define UPINRQX _SFR_MEM8(0xA5) ++ ++#define UPINTX _SFR_MEM8(0xA6) ++#define FIFOCON 7 ++#define NAKEDI 6 ++#define RWAL 5 ++#define PERRI 4 ++#define TXSTPI 3 ++#define TXOUTI 2 ++#define RXSTALLI 1 ++#define RXINI 0 ++ ++#define UPNUM _SFR_MEM8(0xA7) ++ ++#define UPRST _SFR_MEM8(0xA8) ++#define PRST6 6 ++#define PRST5 5 ++#define PRST4 4 ++#define PRST3 3 ++#define PRST2 2 ++#define PRST1 1 ++#define PRST0 0 ++ ++#define UPCONX _SFR_MEM8(0xA9) ++#define PFREEZE 6 ++#define INMODE 5 ++/* #define AUTOSW 4 */ /* Reserved */ ++#define RSTDT 3 ++#define PEN 0 ++ ++#define UPCFG0X _SFR_MEM8(0XAA) ++#define PTYPE1 7 ++#define PTYPE0 6 ++#define PTOKEN1 5 ++#define PTOKEN0 4 ++#define PEPNUM3 3 ++#define PEPNUM2 2 ++#define PEPNUM1 1 ++#define PEPNUM0 0 ++ ++#define UPCFG1X _SFR_MEM8(0XAB) ++#define PSIZE2 6 ++#define PSIZE1 5 ++#define PSIZE0 4 ++#define PBK1 3 ++#define PBK0 2 ++#define ALLOC 1 ++ ++#define UPSTAX _SFR_MEM8(0XAC) ++#define CFGOK 7 ++#define OVERFI 6 ++#define UNDERFI 5 ++#define DTSEQ1 3 ++#define DTSEQ0 2 ++#define NBUSYBK1 1 ++#define NBUSYBK0 0 ++ ++#define UPCFG2X _SFR_MEM8(0XAD) ++ ++#define UPIENX _SFR_MEM8(0XAE) ++#define FLERRE 7 ++#define NAKEDE 6 ++#define PERRE 4 ++#define TXSTPE 3 ++#define TXOUTE 2 ++#define RXSTALLE 1 ++#define RXINE 0 ++ ++#define UPDATX _SFR_MEM8(0XAF) ++ ++#endif /* __AT90USBxx7__ */ ++ ++#define TCCR2A _SFR_MEM8(0xB0) ++#define COM2A1 7 ++#define COM2A0 6 ++#define COM2B1 5 ++#define COM2B0 4 ++#define WGM21 1 ++#define WGM20 0 ++ ++#define TCCR2B _SFR_MEM8(0xB1) ++#define FOC2A 7 ++#define FOC2B 6 ++#define WGM22 3 ++#define CS22 2 ++#define CS21 1 ++#define CS20 0 ++ ++#define TCNT2 _SFR_MEM8(0xB2) ++ ++#define OCR2A _SFR_MEM8(0xB3) ++ ++#define OCR2B _SFR_MEM8(0xB4) ++ ++/* Reserved [0xB5] */ ++ ++#define ASSR _SFR_MEM8(0xB6) ++#define EXCLK 6 ++#define AS2 5 ++#define TCN2UB 4 ++#define OCR2AUB 3 ++#define OCR2BUB 2 ++#define TCR2AUB 1 ++#define TCR2BUB 0 ++ ++/* Reserved [0xB7] */ ++ ++#define TWBR _SFR_MEM8(0xB8) ++ ++#define TWSR _SFR_MEM8(0xB9) ++#define TWS7 7 ++#define TWS6 6 ++#define TWS5 5 ++#define TWS4 4 ++#define TWS3 3 ++#define TWPS1 1 ++#define TWPS0 0 ++ ++#define TWAR _SFR_MEM8(0xBA) ++#define TWA6 7 ++#define TWA5 6 ++#define TWA4 5 ++#define TWA3 4 ++#define TWA2 3 ++#define TWA1 2 ++#define TWA0 1 ++#define TWGCE 0 ++ ++#define TWDR _SFR_MEM8(0xBB) ++ ++#define TWCR _SFR_MEM8(0xBC) ++#define TWINT 7 ++#define TWEA 6 ++#define TWSTA 5 ++#define TWSTO 4 ++#define TWWC 3 ++#define TWEN 2 ++#define TWIE 0 ++ ++#define TWAMR _SFR_MEM8(0xBD) ++#define TWAM6 7 ++#define TWAM5 6 ++#define TWAM4 5 ++#define TWAM3 4 ++#define TWAM2 3 ++#define TWAM1 2 ++#define TWAM0 1 ++ ++/* Reserved [0xBE..0xC7] */ ++ ++#define UCSR1A _SFR_MEM8(0xC8) ++#define RXC1 7 ++#define TXC1 6 ++#define UDRE1 5 ++#define FE1 4 ++#define DOR1 3 ++#define UPE1 2 ++#define U2X1 1 ++#define MPCM1 0 ++ ++#define UCSR1B _SFR_MEM8(0XC9) ++#define RXCIE1 7 ++#define TXCIE1 6 ++#define UDRIE1 5 ++#define RXEN1 4 ++#define TXEN1 3 ++#define UCSZ12 2 ++#define RXB81 1 ++#define TXB81 0 ++ ++#define UCSR1C _SFR_MEM8(0xCA) ++#define UMSEL11 7 ++#define UMSEL10 6 ++#define UPM11 5 ++#define UPM10 4 ++#define USBS1 3 ++#define UCSZ11 2 ++#define UCSZ10 1 ++#define UCPOL1 0 ++ ++/* Reserved [0xCB] */ ++ ++/* Combine UBRR1L and UBRR1H */ ++#define UBRR1 _SFR_MEM16(0xCC) ++ ++#define UBRR1L _SFR_MEM8(0xCC) ++#define UBRR1H _SFR_MEM8(0xCD) ++ ++#define UDR1 _SFR_MEM8(0XCE) ++ ++/* Reserved [0xCF..0xD6] */ ++ ++#define UHWCON _SFR_MEM8(0XD7) ++#define UIMOD 7 ++#define UIDE 6 ++#define UVCONE 4 ++#define UVREGE 0 ++ ++#define USBCON _SFR_MEM8(0XD8) ++#define USBE 7 ++#define HOST 6 ++#define FRZCLK 5 ++#define OTGPADE 4 ++#define IDTE 1 ++#define VBUSTE 0 ++ ++#define USBSTA _SFR_MEM8(0XD9) ++#define SPEED 3 ++#define ID 1 ++#define VBUS 0 ++ ++#define USBINT _SFR_MEM8(0XDA) ++#define IDTI 1 ++#define VBUSTI 0 ++ ++/* Combine UDPADDL and UDPADDH */ ++#define UDPADD _SFR_MEM16(0xDB) ++ ++#define UDPADDL _SFR_MEM8(0xDB) ++#define UDPADDH _SFR_MEM8(0xDC) ++#define DPACC 7 ++ ++#if defined(__AT90USBxx7__) ++ ++#define OTGCON _SFR_MEM8(0XDD) ++#define HNPREQ 5 ++#define SRPREQ 4 ++#define SRPSEL 3 ++#define VBUSHWC 2 ++#define VBUSREQ 1 ++#define VBUSRQC 0 ++ ++#define OTGIEN _SFR_MEM8(0XDE) ++#define STOE 5 ++#define HNPERRE 4 ++#define ROLEEXE 3 ++#define BCERRE 2 ++#define VBERRE 1 ++#define SRPE 0 ++ ++#define OTGINT _SFR_MEM8(0XDF) ++#define STOI 5 ++#define HNPERRI 4 ++#define ROLEEXI 3 ++#define BCERRI 2 ++#define VBERRI 1 ++#define SRPI 0 ++ ++#endif /* __AT90USBxx7__ */ ++ ++#define UDCON _SFR_MEM8(0XE0) ++#define LSM 2 ++#define RMWKUP 1 ++#define DETACH 0 ++ ++#define UDINT _SFR_MEM8(0XE1) ++#define UPRSMI 6 ++#define EORSMI 5 ++#define WAKEUPI 4 ++#define EORSTI 3 ++#define SOFI 2 ++/* #define MSOFI 1 */ /* Reserved */ ++#define SUSPI 0 ++ ++#define UDIEN _SFR_MEM8(0XE2) ++#define UPRSME 6 ++#define EORSME 5 ++#define WAKEUPE 4 ++#define EORSTE 3 ++#define SOFE 2 ++/* #define MSOFE 1 */ /* Reserved */ ++#define SUSPE 0 ++ ++#define UDADDR _SFR_MEM8(0XE3) ++#define ADDEN 7 ++ ++/* Combine UDFNUML and UDFNUMH */ ++#define UDFNUM _SFR_MEM16(0xE4) ++ ++#define UDFNUML _SFR_MEM8(0xE4) ++#define UDFNUMH _SFR_MEM8(0xE5) ++ ++#define UDMFN _SFR_MEM8(0XE6) ++#define FNCERR 4 ++ ++#define UDTST _SFR_MEM8(0XE7) ++#define OPMODE2 5 ++#define TSTPCKT 4 ++#define TSTK 3 ++#define TSTJ 2 ++ ++#define UEINTX _SFR_MEM8(0XE8) ++#define FIFOCON 7 ++#define NAKINI 6 ++#define RWAL 5 ++#define NAKOUTI 4 ++#define RXSTPI 3 ++#define RXOUTI 2 ++#define STALLEDI 1 ++#define TXINI 0 ++ ++#define UENUM _SFR_MEM8(0XE9) ++ ++#define UERST _SFR_MEM8(0XEA) ++#define EPRST6 6 ++#define EPRST5 5 ++#define EPRST4 4 ++#define EPRST3 3 ++#define EPRST2 2 ++#define EPRST1 1 ++#define EPRST0 0 ++ ++#define UECONX _SFR_MEM8(0XEB) ++#define STALLRQ 5 ++#define STALLRQC 4 ++#define RSTDT 3 ++#define EPEN 0 ++ ++#define UECFG0X _SFR_MEM8(0XEC) ++#define EPTYPE1 7 ++#define EPTYPE0 6 ++/* #define ISOSW 3 */ /* Reserved */ ++/* #define AUTOSW 2 */ /* Reserved */ ++/* #define NYETSDIS 1 */ /* Reserved */ ++#define EPDIR 0 ++ ++#define UECFG1X _SFR_MEM8(0XED) ++#define EPSIZE2 6 ++#define EPSIZE1 5 ++#define EPSIZE0 4 ++#define EPBK1 3 ++#define EPBK0 2 ++#define ALLOC 1 ++ ++#define UESTA0X _SFR_MEM8(0XEE) ++#define CFGOK 7 ++#define OVERFI 6 ++#define UNDERFI 5 ++#define ZLPSEEN 4 ++#define DTSEQ1 3 ++#define DTSEQ0 2 ++#define NBUSYBK1 1 ++#define NBUSYBK0 0 ++ ++#define UESTA1X _SFR_MEM8(0XEF) ++#define CTRLDIR 2 ++#define CURRBK1 1 ++#define CURRBK0 0 ++ ++#define UEIENX _SFR_MEM8(0XF0) ++#define FLERRE 7 ++#define NAKINE 6 ++#define NAKOUTE 4 ++#define RXSTPE 3 ++#define RXOUTE 2 ++#define STALLEDE 1 ++#define TXINE 0 ++ ++#define UEDATX _SFR_MEM8(0XF1) ++ ++/* Combine UEBCLX and UEBCHX */ ++#define UEBCX _SFR_MEM16(0xF2) ++ ++#define UEBCLX _SFR_MEM8(0xF2) ++#define UEBCHX _SFR_MEM8(0xF3) ++ ++#define UEINT _SFR_MEM8(0XF4) ++#define EPINT6 6 ++#define EPINT5 5 ++#define EPINT4 4 ++#define EPINT3 3 ++#define EPINT2 2 ++#define EPINT1 1 ++#define EPINT0 0 ++ ++#if defined(__AT90USBxx7__) ++ ++#define UPERRX _SFR_MEM8(0XF5) ++#define COUNTER1 6 ++#define COUNTER0 5 ++#define CRC16 4 ++#define TIMEOUT 3 ++#define PID 2 ++#define DATAPID 1 ++#define DATATGL 0 ++ ++/* Combine UPBCLX and UPBCHX */ ++#define UPBCX _SFR_MEM16(0xF6) ++ ++#define UPBCLX _SFR_MEM8(0xF6) ++#define UPBCHX _SFR_MEM8(0xF7) ++ ++#define UPINT _SFR_MEM8(0XF8) ++#define PINT6 6 ++#define PINT5 5 ++#define PINT4 4 ++#define PINT3 3 ++#define PINT2 2 ++#define PINT1 1 ++#define PINT0 0 ++ ++#define OTGTCON _SFR_MEM8(0XF9) ++#define PAGE1 6 ++#define PAGE0 5 ++#define VALUE1 1 ++#define VALUE0 0 ++ ++#endif /* __AT90USBxx7__ */ ++ ++/* Reserved [0xFA..0xFF] */ ++ ++/* Interrupt vectors */ ++ ++/* External Interrupt Request 0 */ ++#define INT0_vect_num 1 ++#define INT0_vect _VECTOR(1) ++ ++/* External Interrupt Request 1 */ ++#define INT1_vect_num 2 ++#define INT1_vect _VECTOR(2) ++ ++/* External Interrupt Request 2 */ ++#define INT2_vect_num 3 ++#define INT2_vect _VECTOR(3) ++ ++/* External Interrupt Request 3 */ ++#define INT3_vect_num 4 ++#define INT3_vect _VECTOR(4) ++ ++/* External Interrupt Request 4 */ ++#define INT4_vect_num 5 ++#define INT4_vect _VECTOR(5) ++ ++/* External Interrupt Request 5 */ ++#define INT5_vect_num 6 ++#define INT5_vect _VECTOR(6) ++ ++/* External Interrupt Request 6 */ ++#define INT6_vect_num 7 ++#define INT6_vect _VECTOR(7) ++ ++/* External Interrupt Request 7 */ ++#define INT7_vect_num 8 ++#define INT7_vect _VECTOR(8) ++ ++/* Pin Change Interrupt Request 0 */ ++#define PCINT0_vect_num 9 ++#define PCINT0_vect _VECTOR(9) ++ ++/* USB General Interrupt Request */ ++#define USB_GEN_vect_num 10 ++#define USB_GEN_vect _VECTOR(10) ++ ++/* USB Endpoint/Pipe Interrupt Communication Request */ ++#define USB_COM_vect_num 11 ++#define USB_COM_vect _VECTOR(11) ++ ++/* Watchdog Time-out Interrupt */ ++#define WDT_vect_num 12 ++#define WDT_vect _VECTOR(12) ++ ++/* Timer/Counter2 Compare Match A */ ++#define TIMER2_COMPA_vect_num 13 ++#define TIMER2_COMPA_vect _VECTOR(13) ++ ++/* Timer/Counter2 Compare Match B */ ++#define TIMER2_COMPB_vect_num 14 ++#define TIMER2_COMPB_vect _VECTOR(14) ++ ++/* Timer/Counter2 Overflow */ ++#define TIMER2_OVF_vect_num 15 ++#define TIMER2_OVF_vect _VECTOR(15) ++ ++/* Timer/Counter1 Capture Event */ ++#define TIMER1_CAPT_vect_num 16 ++#define TIMER1_CAPT_vect _VECTOR(16) ++ ++/* Timer/Counter1 Compare Match A */ ++#define TIMER1_COMPA_vect_num 17 ++#define TIMER1_COMPA_vect _VECTOR(17) ++ ++/* Timer/Counter1 Compare Match B */ ++#define TIMER1_COMPB_vect_num 18 ++#define TIMER1_COMPB_vect _VECTOR(18) ++ ++/* Timer/Counter1 Compare Match C */ ++#define TIMER1_COMPC_vect_num 19 ++#define TIMER1_COMPC_vect _VECTOR(19) ++ ++/* Timer/Counter1 Overflow */ ++#define TIMER1_OVF_vect_num 20 ++#define TIMER1_OVF_vect _VECTOR(20) ++ ++/* Timer/Counter0 Compare Match A */ ++#define TIMER0_COMPA_vect_num 21 ++#define TIMER0_COMPA_vect _VECTOR(21) ++ ++/* Timer/Counter0 Compare Match B */ ++#define TIMER0_COMPB_vect_num 22 ++#define TIMER0_COMPB_vect _VECTOR(22) ++ ++/* Timer/Counter0 Overflow */ ++#define TIMER0_OVF_vect_num 23 ++#define TIMER0_OVF_vect _VECTOR(23) ++ ++/* SPI Serial Transfer Complete */ ++#define SPI_STC_vect_num 24 ++#define SPI_STC_vect _VECTOR(24) ++ ++/* USART1, Rx Complete */ ++#define USART1_RX_vect_num 25 ++#define USART1_RX_vect _VECTOR(25) ++ ++/* USART1 Data register Empty */ ++#define USART1_UDRE_vect_num 26 ++#define USART1_UDRE_vect _VECTOR(26) ++ ++/* USART1, Tx Complete */ ++#define USART1_TX_vect_num 27 ++#define USART1_TX_vect _VECTOR(27) ++ ++/* Analog Comparator */ ++#define ANALOG_COMP_vect_num 28 ++#define ANALOG_COMP_vect _VECTOR(28) ++ ++/* ADC Conversion Complete */ ++#define ADC_vect_num 29 ++#define ADC_vect _VECTOR(29) ++ ++/* EEPROM Ready */ ++#define EE_READY_vect_num 30 ++#define EE_READY_vect _VECTOR(30) ++ ++/* Timer/Counter3 Capture Event */ ++#define TIMER3_CAPT_vect_num 31 ++#define TIMER3_CAPT_vect _VECTOR(31) ++ ++/* Timer/Counter3 Compare Match A */ ++#define TIMER3_COMPA_vect_num 32 ++#define TIMER3_COMPA_vect _VECTOR(32) ++ ++/* Timer/Counter3 Compare Match B */ ++#define TIMER3_COMPB_vect_num 33 ++#define TIMER3_COMPB_vect _VECTOR(33) ++ ++/* Timer/Counter3 Compare Match C */ ++#define TIMER3_COMPC_vect_num 34 ++#define TIMER3_COMPC_vect _VECTOR(34) ++ ++/* Timer/Counter3 Overflow */ ++#define TIMER3_OVF_vect_num 35 ++#define TIMER3_OVF_vect _VECTOR(35) ++ ++/* 2-wire Serial Interface */ ++#define TWI_vect_num 36 ++#define TWI_vect _VECTOR(36) ++ ++/* Store Program Memory Read */ ++#define SPM_READY_vect_num 37 ++#define SPM_READY_vect _VECTOR(37) ++ ++#define _VECTORS_SIZE 152 ++ ++#if defined(__AT90USBxx6__) ++# undef __AT90USBxx6__ ++#endif /* __AT90USBxx6__ */ ++ ++#if defined(__AT90USBxx7__) ++# undef __AT90USBxx7__ ++#endif /* __AT90USBxx7__ */ ++ ++#endif /* _AVR_IOUSBXX6_7_H_ */ +diff --git a/include/avr/iox128a1.h b/include/avr/iox128a1.h +index fff87ab..da5ad6e 100644 +--- a/include/avr/iox128a1.h ++++ b/include/avr/iox128a1.h +@@ -1,7167 +1,7167 @@ +-/* Copyright (c) 2009-2010 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iox128a1.h 2200 2010-12-14 04:24:24Z arcanum $ */ +- +-/* avr/iox128a1.h - definitions for ATxmega128A1 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iox128a1.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATxmega128A1_H_ +-#define _AVR_ATxmega128A1_H_ 1 +- +- +-/* Ungrouped common registers */ +-#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +-#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +-#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +-#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +-#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +-#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +-#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +-#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +-#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +-#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +-#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +-#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +-#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +-#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +-#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +-#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +- +-/* Deprecated */ +-#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +-#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +-#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +-#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +-#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +-#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +-#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +-#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +-#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +-#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +-#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +-#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +-#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +-#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +-#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +-#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +- +-#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +-#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +-#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +-#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +-#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +-#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +-#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +-#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +-#define SREG _SFR_MEM8(0x003F) /* Status Register */ +- +- +-/* C Language Only */ +-#if !defined (__ASSEMBLER__) +- +-#include +- +-typedef volatile uint8_t register8_t; +-typedef volatile uint16_t register16_t; +-typedef volatile uint32_t register32_t; +- +- +-#ifdef _WORDREGISTER +-#undef _WORDREGISTER +-#endif +-#define _WORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register16_t regname; \ +- struct \ +- { \ +- register8_t regname ## L; \ +- register8_t regname ## H; \ +- }; \ +- } +- +-#ifdef _DWORDREGISTER +-#undef _DWORDREGISTER +-#endif +-#define _DWORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register32_t regname; \ +- struct \ +- { \ +- register8_t regname ## 0; \ +- register8_t regname ## 1; \ +- register8_t regname ## 2; \ +- register8_t regname ## 3; \ +- }; \ +- } +- +- +-/* +-========================================================================== +-IO Module Structures +-========================================================================== +-*/ +- +- +-/* +--------------------------------------------------------------------------- +-XOCD - On-Chip Debug System +--------------------------------------------------------------------------- +-*/ +- +-/* On-Chip Debug System */ +-typedef struct OCD_struct +-{ +- register8_t OCDR0; /* OCD Register 0 */ +- register8_t OCDR1; /* OCD Register 1 */ +-} OCD_t; +- +- +-/* CCP signatures */ +-typedef enum CCP_enum +-{ +- CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ +- CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +-} CCP_t; +- +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Clock System */ +-typedef struct CLK_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t PSCTRL; /* Prescaler Control Register */ +- register8_t LOCK; /* Lock register */ +- register8_t RTCCTRL; /* RTC Control Register */ +-} CLK_t; +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Power Reduction */ +-typedef struct PR_struct +-{ +- register8_t PRGEN; /* General Power Reduction */ +- register8_t PRPA; /* Power Reduction Port A */ +- register8_t PRPB; /* Power Reduction Port B */ +- register8_t PRPC; /* Power Reduction Port C */ +- register8_t PRPD; /* Power Reduction Port D */ +- register8_t PRPE; /* Power Reduction Port E */ +- register8_t PRPF; /* Power Reduction Port F */ +-} PR_t; +- +-/* System Clock Selection */ +-typedef enum CLK_SCLKSEL_enum +-{ +- CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ +- CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ +- CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ +- CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ +- CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +-} CLK_SCLKSEL_t; +- +-/* Prescaler A Division Factor */ +-typedef enum CLK_PSADIV_enum +-{ +- CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ +- CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ +- CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ +- CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ +- CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ +- CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ +- CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ +- CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ +- CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ +- CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +-} CLK_PSADIV_t; +- +-/* Prescaler B and C Division Factor */ +-typedef enum CLK_PSBCDIV_enum +-{ +- CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ +- CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ +- CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ +- CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +-} CLK_PSBCDIV_t; +- +-/* RTC Clock Source */ +-typedef enum CLK_RTCSRC_enum +-{ +- CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ +- CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ +- CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ +- CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +-} CLK_RTCSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-SLEEP - Sleep Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Sleep Controller */ +-typedef struct SLEEP_struct +-{ +- register8_t CTRL; /* Control Register */ +-} SLEEP_t; +- +-/* Sleep Mode */ +-typedef enum SLEEP_SMODE_enum +-{ +- SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ +- SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +- SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ +- SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ +- SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +-} SLEEP_SMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-OSC - Oscillator +--------------------------------------------------------------------------- +-*/ +- +-/* Oscillator */ +-typedef struct OSC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t XOSCCTRL; /* External Oscillator Control Register */ +- register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ +- register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ +- register8_t PLLCTRL; /* PLL Control REgister */ +- register8_t DFLLCTRL; /* DFLL Control Register */ +-} OSC_t; +- +-/* Oscillator Frequency Range */ +-typedef enum OSC_FRQRANGE_enum +-{ +- OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ +- OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ +- OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ +- OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +-} OSC_FRQRANGE_t; +- +-/* External Oscillator Selection and Startup Time */ +-typedef enum OSC_XOSCSEL_enum +-{ +- OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ +- OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ +- OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ +- OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ +- OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +-} OSC_XOSCSEL_t; +- +-/* PLL Clock Source */ +-typedef enum OSC_PLLSRC_enum +-{ +- OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ +- OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ +- OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +-} OSC_PLLSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-DFLL - DFLL +--------------------------------------------------------------------------- +-*/ +- +-/* DFLL */ +-typedef struct DFLL_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t CALA; /* Calibration Register A */ +- register8_t CALB; /* Calibration Register B */ +- register8_t COMP0; /* Oscillator Compare Register 0 */ +- register8_t COMP1; /* Oscillator Compare Register 1 */ +- register8_t COMP2; /* Oscillator Compare Register 2 */ +- register8_t reserved_0x07; +-} DFLL_t; +- +- +-/* +--------------------------------------------------------------------------- +-RST - Reset +--------------------------------------------------------------------------- +-*/ +- +-/* Reset */ +-typedef struct RST_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t CTRL; /* Control Register */ +-} RST_t; +- +- +-/* +--------------------------------------------------------------------------- +-WDT - Watch-Dog Timer +--------------------------------------------------------------------------- +-*/ +- +-/* Watch-Dog Timer */ +-typedef struct WDT_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t WINCTRL; /* Windowed Mode Control */ +- register8_t STATUS; /* Status */ +-} WDT_t; +- +-/* Period setting */ +-typedef enum WDT_PER_enum +-{ +- WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ +- WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ +- WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ +- WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_PER_t; +- +-/* Closed window period */ +-typedef enum WDT_WPER_enum +-{ +- WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ +- WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ +- WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ +- WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_WPER_t; +- +- +-/* +--------------------------------------------------------------------------- +-MCU - MCU Control +--------------------------------------------------------------------------- +-*/ +- +-/* MCU Control */ +-typedef struct MCU_struct +-{ +- register8_t DEVID0; /* Device ID byte 0 */ +- register8_t DEVID1; /* Device ID byte 1 */ +- register8_t DEVID2; /* Device ID byte 2 */ +- register8_t REVID; /* Revision ID */ +- register8_t JTAGUID; /* JTAG User ID */ +- register8_t reserved_0x05; +- register8_t MCUCR; /* MCU Control */ +- register8_t reserved_0x07; +- register8_t EVSYSLOCK; /* Event System Lock */ +- register8_t AWEXLOCK; /* AWEX Lock */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +-} MCU_t; +- +- +-/* +--------------------------------------------------------------------------- +-PMIC - Programmable Multi-level Interrupt Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Programmable Multi-level Interrupt Controller */ +-typedef struct PMIC_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t INTPRI; /* Interrupt Priority */ +- register8_t CTRL; /* Control Register */ +-} PMIC_t; +- +- +-/* +--------------------------------------------------------------------------- +-DMA - DMA Controller +--------------------------------------------------------------------------- +-*/ +- +-/* DMA Channel */ +-typedef struct DMA_CH_struct +-{ +- register8_t CTRLA; /* Channel Control */ +- register8_t CTRLB; /* Channel Control */ +- register8_t ADDRCTRL; /* Address Control */ +- register8_t TRIGSRC; /* Channel Trigger Source */ +- _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ +- register8_t REPCNT; /* Channel Repeat Count */ +- register8_t reserved_0x07; +- register8_t SRCADDR0; /* Channel Source Address 0 */ +- register8_t SRCADDR1; /* Channel Source Address 1 */ +- register8_t SRCADDR2; /* Channel Source Address 2 */ +- register8_t reserved_0x0B; +- register8_t DESTADDR0; /* Channel Destination Address 0 */ +- register8_t DESTADDR1; /* Channel Destination Address 1 */ +- register8_t DESTADDR2; /* Channel Destination Address 2 */ +- register8_t reserved_0x0F; +-} DMA_CH_t; +- +-/* +--------------------------------------------------------------------------- +-DMA - DMA Controller +--------------------------------------------------------------------------- +-*/ +- +-/* DMA Controller */ +-typedef struct DMA_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t reserved_0x01; +- register8_t reserved_0x02; +- register8_t INTFLAGS; /* Transfer Interrupt Status */ +- register8_t STATUS; /* Status */ +- register8_t reserved_0x05; +- _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- DMA_CH_t CH0; /* DMA Channel 0 */ +- DMA_CH_t CH1; /* DMA Channel 1 */ +- DMA_CH_t CH2; /* DMA Channel 2 */ +- DMA_CH_t CH3; /* DMA Channel 3 */ +-} DMA_t; +- +-/* Burst mode */ +-typedef enum DMA_CH_BURSTLEN_enum +-{ +- DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ +- DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ +- DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ +- DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +-} DMA_CH_BURSTLEN_t; +- +-/* Source address reload mode */ +-typedef enum DMA_CH_SRCRELOAD_enum +-{ +- DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ +- DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ +- DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ +- DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +-} DMA_CH_SRCRELOAD_t; +- +-/* Source addressing mode */ +-typedef enum DMA_CH_SRCDIR_enum +-{ +- DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ +- DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ +- DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +-} DMA_CH_SRCDIR_t; +- +-/* Destination adress reload mode */ +-typedef enum DMA_CH_DESTRELOAD_enum +-{ +- DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ +- DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ +- DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ +- DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +-} DMA_CH_DESTRELOAD_t; +- +-/* Destination adressing mode */ +-typedef enum DMA_CH_DESTDIR_enum +-{ +- DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ +- DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ +- DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +-} DMA_CH_DESTDIR_t; +- +-/* Transfer trigger source */ +-typedef enum DMA_CH_TRIGSRC_enum +-{ +- DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ +- DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ +- DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ +- DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ +- DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ +- DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ +- DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ +- DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ +- DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ +- DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ +- DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ +- DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ +- DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ +- DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ +- DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ +- DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ +- DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ +- DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ +- DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ +- DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ +- DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ +- DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ +- DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ +- DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ +- DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ +- DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ +- DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ +- DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ +- DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ +- DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ +- DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ +- DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ +- DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ +- DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ +- DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ +- DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ +- DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ +- DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ +- DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +-} DMA_CH_TRIGSRC_t; +- +-/* Double buffering mode */ +-typedef enum DMA_DBUFMODE_enum +-{ +- DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ +- DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ +- DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ +- DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +-} DMA_DBUFMODE_t; +- +-/* Priority mode */ +-typedef enum DMA_PRIMODE_enum +-{ +- DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ +- DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ +- DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ +- DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +-} DMA_PRIMODE_t; +- +-/* Interrupt level */ +-typedef enum DMA_CH_ERRINTLVL_enum +-{ +- DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ +- DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ +- DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +-} DMA_CH_ERRINTLVL_t; +- +-/* Interrupt level */ +-typedef enum DMA_CH_TRNINTLVL_enum +-{ +- DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ +- DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ +- DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +-} DMA_CH_TRNINTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-EVSYS - Event System +--------------------------------------------------------------------------- +-*/ +- +-/* Event System */ +-typedef struct EVSYS_struct +-{ +- register8_t CH0MUX; /* Event Channel 0 Multiplexer */ +- register8_t CH1MUX; /* Event Channel 1 Multiplexer */ +- register8_t CH2MUX; /* Event Channel 2 Multiplexer */ +- register8_t CH3MUX; /* Event Channel 3 Multiplexer */ +- register8_t CH4MUX; /* Event Channel 4 Multiplexer */ +- register8_t CH5MUX; /* Event Channel 5 Multiplexer */ +- register8_t CH6MUX; /* Event Channel 6 Multiplexer */ +- register8_t CH7MUX; /* Event Channel 7 Multiplexer */ +- register8_t CH0CTRL; /* Channel 0 Control Register */ +- register8_t CH1CTRL; /* Channel 1 Control Register */ +- register8_t CH2CTRL; /* Channel 2 Control Register */ +- register8_t CH3CTRL; /* Channel 3 Control Register */ +- register8_t CH4CTRL; /* Channel 4 Control Register */ +- register8_t CH5CTRL; /* Channel 5 Control Register */ +- register8_t CH6CTRL; /* Channel 6 Control Register */ +- register8_t CH7CTRL; /* Channel 7 Control Register */ +- register8_t STROBE; /* Event Strobe */ +- register8_t DATA; /* Event Data */ +-} EVSYS_t; +- +-/* Quadrature Decoder Index Recognition Mode */ +-typedef enum EVSYS_QDIRM_enum +-{ +- EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ +- EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ +- EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ +- EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +-} EVSYS_QDIRM_t; +- +-/* Digital filter coefficient */ +-typedef enum EVSYS_DIGFILT_enum +-{ +- EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ +- EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ +- EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ +- EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ +- EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ +- EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ +- EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ +- EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +-} EVSYS_DIGFILT_t; +- +-/* Event Channel multiplexer input selection */ +-typedef enum EVSYS_CHMUX_enum +-{ +- EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ +- EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ +- EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ +- EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ +- EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ +- EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ +- EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ +- EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ +- EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ +- EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ +- EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ +- EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ +- EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ +- EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ +- EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ +- EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ +- EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ +- EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ +- EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ +- EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ +- EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ +- EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ +- EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ +- EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ +- EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ +- EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ +- EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ +- EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ +- EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ +- EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ +- EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ +- EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ +- EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ +- EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ +- EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ +- EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ +- EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ +- EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ +- EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ +- EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ +- EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ +- EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ +- EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ +- EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ +- EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ +- EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ +- EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ +- EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ +- EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ +- EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ +- EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ +- EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ +- EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ +- EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ +- EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ +- EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ +- EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ +- EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ +- EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ +- EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ +- EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ +- EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ +- EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ +- EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ +- EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ +- EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ +- EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ +- EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ +- EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ +- EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ +- EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ +- EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ +- EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ +- EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ +- EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ +- EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ +- EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ +- EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ +- EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ +- EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ +- EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ +- EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ +- EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ +- EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ +- EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ +- EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ +- EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ +- EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ +- EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ +- EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ +- EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ +- EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ +- EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ +- EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ +- EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ +- EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ +- EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ +- EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ +- EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ +- EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ +- EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ +- EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ +- EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ +- EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ +- EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ +- EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ +- EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ +- EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ +- EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ +- EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ +- EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +- EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ +- EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ +- EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ +- EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +-} EVSYS_CHMUX_t; +- +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Non-volatile Memory Controller */ +-typedef struct NVM_struct +-{ +- register8_t ADDR0; /* Address Register 0 */ +- register8_t ADDR1; /* Address Register 1 */ +- register8_t ADDR2; /* Address Register 2 */ +- register8_t reserved_0x03; +- register8_t DATA0; /* Data Register 0 */ +- register8_t DATA1; /* Data Register 1 */ +- register8_t DATA2; /* Data Register 2 */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t CMD; /* Command */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t INTCTRL; /* Interrupt Control */ +- register8_t reserved_0x0E; +- register8_t STATUS; /* Status */ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Lock Bits */ +-typedef struct NVM_LOCKBITS_struct +-{ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_LOCKBITS_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Fuses */ +-typedef struct NVM_FUSES_struct +-{ +- register8_t FUSEBYTE0; /* JTAG User ID */ +- register8_t FUSEBYTE1; /* Watchdog Configuration */ +- register8_t FUSEBYTE2; /* Reset Configuration */ +- register8_t reserved_0x03; +- register8_t FUSEBYTE4; /* Start-up Configuration */ +- register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +-} NVM_FUSES_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Production Signatures */ +-typedef struct NVM_PROD_SIGNATURES_struct +-{ +- register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ +- register8_t reserved_0x01; +- register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ +- register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ +- register8_t reserved_0x04; +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ +- register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ +- register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ +- register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ +- register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ +- register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t WAFNUM; /* Wafer Number */ +- register8_t reserved_0x11; +- register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ +- register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ +- register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ +- register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ +- register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ +- register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ +- register8_t reserved_0x26; +- register8_t reserved_0x27; +- register8_t reserved_0x28; +- register8_t reserved_0x29; +- register8_t reserved_0x2A; +- register8_t reserved_0x2B; +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ +- register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ +- register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ +- register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ +- register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ +- register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- register8_t reserved_0x36; +- register8_t reserved_0x37; +- register8_t reserved_0x38; +- register8_t reserved_0x39; +- register8_t reserved_0x3A; +- register8_t reserved_0x3B; +- register8_t reserved_0x3C; +- register8_t reserved_0x3D; +- register8_t reserved_0x3E; +-} NVM_PROD_SIGNATURES_t; +- +-/* NVM Command */ +-typedef enum NVM_CMD_enum +-{ +- NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ +- NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ +- NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ +- NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ +- NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ +- NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ +- NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ +- NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ +- NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ +- NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ +- NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ +- NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ +- NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ +- NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ +- NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ +- NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ +- NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ +- NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ +- NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ +- NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ +- NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ +- NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ +- NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ +- NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ +- NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ +- NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +-} NVM_CMD_t; +- +-/* SPM ready interrupt level */ +-typedef enum NVM_SPMLVL_enum +-{ +- NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ +- NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ +- NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +-} NVM_SPMLVL_t; +- +-/* EEPROM ready interrupt level */ +-typedef enum NVM_EELVL_enum +-{ +- NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ +- NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ +- NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +-} NVM_EELVL_t; +- +-/* Boot lock bits - boot setcion */ +-typedef enum NVM_BLBB_enum +-{ +- NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +- NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ +- NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ +- NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +-} NVM_BLBB_t; +- +-/* Boot lock bits - application section */ +-typedef enum NVM_BLBA_enum +-{ +- NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +- NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ +- NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ +- NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +-} NVM_BLBA_t; +- +-/* Boot lock bits - application table section */ +-typedef enum NVM_BLBAT_enum +-{ +- NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +- NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ +- NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ +- NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +-} NVM_BLBAT_t; +- +-/* Lock bits */ +-typedef enum NVM_LB_enum +-{ +- NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +- NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ +- NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +-} NVM_LB_t; +- +-/* Boot Loader Section Reset Vector */ +-typedef enum BOOTRST_enum +-{ +- BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ +- BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +-} BOOTRST_t; +- +-/* BOD operation */ +-typedef enum BOD_enum +-{ +- BOD_INSAMPLEDMODE_gc = (0x01<<2), /* BOD enabled in sampled mode */ +- BOD_CONTINOUSLY_gc = (0x02<<2), /* BOD enabled continuously */ +- BOD_DISABLED_gc = (0x03<<2), /* BOD Disabled */ +-} BOD_t; +- +-/* Watchdog (Window) Timeout Period */ +-typedef enum WD_enum +-{ +- WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ +- WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ +- WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ +- WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ +- WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ +- WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ +- WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ +- WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ +- WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ +- WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ +- WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +-} WD_t; +- +-/* Start-up Time */ +-typedef enum SUT_enum +-{ +- SUT_0MS_gc = (0x03<<2), /* 0 ms */ +- SUT_4MS_gc = (0x01<<2), /* 4 ms */ +- SUT_64MS_gc = (0x00<<2), /* 64 ms */ +-} SUT_t; +- +-/* Brown Out Detection Voltage Level */ +-typedef enum BODLVL_enum +-{ +- BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ +- BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ +- BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ +- BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ +- BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ +- BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ +- BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ +-} BODLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-AC - Analog Comparator +--------------------------------------------------------------------------- +-*/ +- +-/* Analog Comparator */ +-typedef struct AC_struct +-{ +- register8_t AC0CTRL; /* Comparator 0 Control */ +- register8_t AC1CTRL; /* Comparator 1 Control */ +- register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ +- register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t WINCTRL; /* Window Mode Control */ +- register8_t STATUS; /* Status */ +-} AC_t; +- +-/* Interrupt mode */ +-typedef enum AC_INTMODE_enum +-{ +- AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ +- AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ +- AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +-} AC_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum AC_INTLVL_enum +-{ +- AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ +- AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ +- AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ +- AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +-} AC_INTLVL_t; +- +-/* Hysteresis mode selection */ +-typedef enum AC_HYSMODE_enum +-{ +- AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ +- AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ +- AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +-} AC_HYSMODE_t; +- +-/* Positive input multiplexer selection */ +-typedef enum AC_MUXPOS_enum +-{ +- AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ +- AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ +- AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ +- AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ +- AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ +- AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ +- AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +- AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +-} AC_MUXPOS_t; +- +-/* Negative input multiplexer selection */ +-typedef enum AC_MUXNEG_enum +-{ +- AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ +- AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ +- AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ +- AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ +- AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ +- AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ +- AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ +- AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +-} AC_MUXNEG_t; +- +-/* Windows interrupt mode */ +-typedef enum AC_WINTMODE_enum +-{ +- AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ +- AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ +- AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ +- AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +-} AC_WINTMODE_t; +- +-/* Window interrupt level */ +-typedef enum AC_WINTLVL_enum +-{ +- AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ +- AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ +- AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +-} AC_WINTLVL_t; +- +-/* Window mode state */ +-typedef enum AC_WSTATE_enum +-{ +- AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ +- AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ +- AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +-} AC_WSTATE_t; +- +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* ADC Channel */ +-typedef struct ADC_CH_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t MUXCTRL; /* MUX Control */ +- register8_t INTCTRL; /* Channel Interrupt Control */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- _WORDREGISTER(RES); /* Channel Result */ +- register8_t reserved_0x6; +- register8_t reserved_0x7; +-} ADC_CH_t; +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Analog-to-Digital Converter */ +-typedef struct ADC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t REFCTRL; /* Reference Control */ +- register8_t EVCTRL; /* Event Control */ +- register8_t PRESCALER; /* Clock Prescaler */ +- register8_t reserved_0x05; +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- _WORDREGISTER(CAL); /* Calibration Value */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- _WORDREGISTER(CH0RES); /* Channel 0 Result */ +- _WORDREGISTER(CH1RES); /* Channel 1 Result */ +- _WORDREGISTER(CH2RES); /* Channel 2 Result */ +- _WORDREGISTER(CH3RES); /* Channel 3 Result */ +- _WORDREGISTER(CMP); /* Compare Value */ +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- ADC_CH_t CH0; /* ADC Channel 0 */ +- ADC_CH_t CH1; /* ADC Channel 1 */ +- ADC_CH_t CH2; /* ADC Channel 2 */ +- ADC_CH_t CH3; /* ADC Channel 3 */ +-} ADC_t; +- +-/* Positive input multiplexer selection */ +-typedef enum ADC_CH_MUXPOS_enum +-{ +- ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ +- ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ +- ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ +- ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ +- ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ +- ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ +- ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ +- ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +-} ADC_CH_MUXPOS_t; +- +-/* Internal input multiplexer selections */ +-typedef enum ADC_CH_MUXINT_enum +-{ +- ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ +- ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ +- ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +- ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +-} ADC_CH_MUXINT_t; +- +-/* Negative input multiplexer selection */ +-typedef enum ADC_CH_MUXNEG_enum +-{ +- ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ +- ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ +- ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ +- ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ +- ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ +- ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ +- ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ +- ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +-} ADC_CH_MUXNEG_t; +- +-/* Input mode */ +-typedef enum ADC_CH_INPUTMODE_enum +-{ +- ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ +- ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ +- ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ +- ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +-} ADC_CH_INPUTMODE_t; +- +-/* Gain factor */ +-typedef enum ADC_CH_GAIN_enum +-{ +- ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ +- ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ +- ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ +- ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ +- ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ +- ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ +- ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ +-} ADC_CH_GAIN_t; +- +-/* Conversion result resolution */ +-typedef enum ADC_RESOLUTION_enum +-{ +- ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ +- ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ +- ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +-} ADC_RESOLUTION_t; +- +-/* Voltage reference selection */ +-typedef enum ADC_REFSEL_enum +-{ +- ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ +- ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ +- ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ +- ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +-} ADC_REFSEL_t; +- +-/* Channel sweep selection */ +-typedef enum ADC_SWEEP_enum +-{ +- ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ +- ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ +- ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ +- ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +-} ADC_SWEEP_t; +- +-/* Event channel input selection */ +-typedef enum ADC_EVSEL_enum +-{ +- ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ +- ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ +- ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ +- ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ +- ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ +- ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ +- ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ +- ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +-} ADC_EVSEL_t; +- +-/* Event action selection */ +-typedef enum ADC_EVACT_enum +-{ +- ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ +- ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ +- ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ +- ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ +- ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ +- ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ +- ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ +-} ADC_EVACT_t; +- +-/* Interupt mode */ +-typedef enum ADC_CH_INTMODE_enum +-{ +- ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ +- ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ +- ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +-} ADC_CH_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum ADC_CH_INTLVL_enum +-{ +- ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ +- ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ +- ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +-} ADC_CH_INTLVL_t; +- +-/* DMA request selection */ +-typedef enum ADC_DMASEL_enum +-{ +- ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ +- ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ +- ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ +- ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +-} ADC_DMASEL_t; +- +-/* Clock prescaler */ +-typedef enum ADC_PRESCALER_enum +-{ +- ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ +- ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ +- ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ +- ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ +- ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ +- ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ +- ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ +- ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +-} ADC_PRESCALER_t; +- +- +-/* +--------------------------------------------------------------------------- +-DAC - Digital/Analog Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Digital-to-Analog Converter */ +-typedef struct DAC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t EVCTRL; /* Event Input Control */ +- register8_t TIMCTRL; /* Timing Control */ +- register8_t STATUS; /* Status */ +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t GAINCAL; /* Gain Calibration */ +- register8_t OFFSETCAL; /* Offset Calibration */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- _WORDREGISTER(CH0DATA); /* Channel 0 Data */ +- _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +-} DAC_t; +- +-/* Output channel selection */ +-typedef enum DAC_CHSEL_enum +-{ +- DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ +- DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ +-} DAC_CHSEL_t; +- +-/* Reference voltage selection */ +-typedef enum DAC_REFSEL_enum +-{ +- DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ +- DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ +- DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ +- DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +-} DAC_REFSEL_t; +- +-/* Event channel selection */ +-typedef enum DAC_EVSEL_enum +-{ +- DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ +- DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ +- DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ +- DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ +- DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ +- DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ +- DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ +- DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +-} DAC_EVSEL_t; +- +-/* Conversion interval */ +-typedef enum DAC_CONINTVAL_enum +-{ +- DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ +- DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ +- DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ +- DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ +- DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ +- DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ +- DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ +- DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ +-} DAC_CONINTVAL_t; +- +-/* Refresh rate */ +-typedef enum DAC_REFRESH_enum +-{ +- DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ +- DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ +- DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ +- DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ +- DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ +- DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ +- DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ +- DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ +- DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ +- DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ +- DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ +- DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ +- DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ +- DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ +-} DAC_REFRESH_t; +- +- +-/* +--------------------------------------------------------------------------- +-RTC - Real-Time Clounter +--------------------------------------------------------------------------- +-*/ +- +-/* Real-Time Counter */ +-typedef struct RTC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t TEMP; /* Temporary register */ +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- _WORDREGISTER(CNT); /* Count Register */ +- _WORDREGISTER(PER); /* Period Register */ +- _WORDREGISTER(COMP); /* Compare Register */ +-} RTC_t; +- +-/* Prescaler Factor */ +-typedef enum RTC_PRESCALER_enum +-{ +- RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ +- RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ +- RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ +- RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ +- RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ +- RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ +- RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ +- RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +-} RTC_PRESCALER_t; +- +-/* Compare Interrupt level */ +-typedef enum RTC_COMPINTLVL_enum +-{ +- RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} RTC_COMPINTLVL_t; +- +-/* Overflow Interrupt level */ +-typedef enum RTC_OVFINTLVL_enum +-{ +- RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} RTC_OVFINTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* EBI Chip Select Module */ +-typedef struct EBI_CS_struct +-{ +- register8_t CTRLA; /* Chip Select Control Register A */ +- register8_t CTRLB; /* Chip Select Control Register B */ +- _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +-} EBI_CS_t; +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* External Bus Interface */ +-typedef struct EBI_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t SDRAMCTRLA; /* SDRAM Control Register A */ +- register8_t reserved_0x02; +- register8_t reserved_0x03; +- _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ +- _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ +- register8_t SDRAMCTRLB; /* SDRAM Control Register B */ +- register8_t SDRAMCTRLC; /* SDRAM Control Register C */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- EBI_CS_t CS0; /* Chip Select 0 */ +- EBI_CS_t CS1; /* Chip Select 1 */ +- EBI_CS_t CS2; /* Chip Select 2 */ +- EBI_CS_t CS3; /* Chip Select 3 */ +-} EBI_t; +- +-/* Chip Select adress space */ +-typedef enum EBI_CS_ASIZE_enum +-{ +- EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ +- EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ +- EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ +- EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ +- EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ +- EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ +- EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ +- EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ +- EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ +- EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ +- EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ +- EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ +- EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ +- EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ +- EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ +- EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ +- EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +-} EBI_CS_ASIZE_t; +- +-/* */ +-typedef enum EBI_CS_SRWS_enum +-{ +- EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_CS_SRWS_t; +- +-/* Chip Select address mode */ +-typedef enum EBI_CS_MODE_enum +-{ +- EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ +- EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ +- EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ +- EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +-} EBI_CS_MODE_t; +- +-/* Chip Select SDRAM mode */ +-typedef enum EBI_CS_SDMODE_enum +-{ +- EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ +- EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +-} EBI_CS_SDMODE_t; +- +-/* */ +-typedef enum EBI_SDDATAW_enum +-{ +- EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ +- EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +-} EBI_SDDATAW_t; +- +-/* */ +-typedef enum EBI_LPCMODE_enum +-{ +- EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ +- EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +-} EBI_LPCMODE_t; +- +-/* */ +-typedef enum EBI_SRMODE_enum +-{ +- EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ +- EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ +- EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ +- EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +-} EBI_SRMODE_t; +- +-/* */ +-typedef enum EBI_IFMODE_enum +-{ +- EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ +- EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ +- EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ +- EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +-} EBI_IFMODE_t; +- +-/* */ +-typedef enum EBI_SDCOL_enum +-{ +- EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ +- EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ +- EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ +- EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +-} EBI_SDCOL_t; +- +-/* */ +-typedef enum EBI_MRDLY_enum +-{ +- EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_MRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCYCDLY_enum +-{ +- EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ROWCYCDLY_t; +- +-/* */ +-typedef enum EBI_RPDLY_enum +-{ +- EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_RPDLY_t; +- +-/* */ +-typedef enum EBI_WRDLY_enum +-{ +- EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_WRDLY_t; +- +-/* */ +-typedef enum EBI_ESRDLY_enum +-{ +- EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ESRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCOLDLY_enum +-{ +- EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_ROWCOLDLY_t; +- +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_MASTER_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t STATUS; /* Status Register */ +- register8_t BAUD; /* Baurd Rate Control Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +-} TWI_MASTER_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_SLAVE_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t STATUS; /* Status Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +- register8_t ADDRMASK; /* Address Mask Register */ +-} TWI_SLAVE_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Two-Wire Interface */ +-typedef struct TWI_struct +-{ +- register8_t CTRL; /* TWI Common Control Register */ +- TWI_MASTER_t MASTER; /* TWI master module */ +- TWI_SLAVE_t SLAVE; /* TWI slave module */ +-} TWI_t; +- +-/* Master Interrupt Level */ +-typedef enum TWI_MASTER_INTLVL_enum +-{ +- TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_MASTER_INTLVL_t; +- +-/* Inactive Timeout */ +-typedef enum TWI_MASTER_TIMEOUT_enum +-{ +- TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ +- TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ +- TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ +- TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +-} TWI_MASTER_TIMEOUT_t; +- +-/* Master Command */ +-typedef enum TWI_MASTER_CMD_enum +-{ +- TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ +- TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ +- TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +-} TWI_MASTER_CMD_t; +- +-/* Master Bus State */ +-typedef enum TWI_MASTER_BUSSTATE_enum +-{ +- TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ +- TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ +- TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ +- TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +-} TWI_MASTER_BUSSTATE_t; +- +-/* Slave Interrupt Level */ +-typedef enum TWI_SLAVE_INTLVL_enum +-{ +- TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_SLAVE_INTLVL_t; +- +-/* Slave Command */ +-typedef enum TWI_SLAVE_CMD_enum +-{ +- TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ +- TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +-} TWI_SLAVE_CMD_t; +- +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O port Configuration */ +-typedef struct PORTCFG_struct +-{ +- register8_t MPCMASK; /* Multi-pin Configuration Mask */ +- register8_t reserved_0x01; +- register8_t VPCTRLA; /* Virtual Port Control Register A */ +- register8_t VPCTRLB; /* Virtual Port Control Register B */ +- register8_t CLKEVOUT; /* Clock and Event Out Register */ +-} PORTCFG_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* Virtual Port */ +-typedef struct VPORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t OUT; /* I/O Port Output */ +- register8_t IN; /* I/O Port Input */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +-} VPORT_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O Ports */ +-typedef struct PORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t DIRSET; /* I/O Port Data Direction Set */ +- register8_t DIRCLR; /* I/O Port Data Direction Clear */ +- register8_t DIRTGL; /* I/O Port Data Direction Toggle */ +- register8_t OUT; /* I/O Port Output */ +- register8_t OUTSET; /* I/O Port Output Set */ +- register8_t OUTCLR; /* I/O Port Output Clear */ +- register8_t OUTTGL; /* I/O Port Output Toggle */ +- register8_t IN; /* I/O port Input */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INT0MASK; /* Port Interrupt 0 Mask */ +- register8_t INT1MASK; /* Port Interrupt 1 Mask */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t PIN0CTRL; /* Pin 0 Control Register */ +- register8_t PIN1CTRL; /* Pin 1 Control Register */ +- register8_t PIN2CTRL; /* Pin 2 Control Register */ +- register8_t PIN3CTRL; /* Pin 3 Control Register */ +- register8_t PIN4CTRL; /* Pin 4 Control Register */ +- register8_t PIN5CTRL; /* Pin 5 Control Register */ +- register8_t PIN6CTRL; /* Pin 6 Control Register */ +- register8_t PIN7CTRL; /* Pin 7 Control Register */ +-} PORT_t; +- +-/* Virtual Port 0 Mapping */ +-typedef enum PORTCFG_VP0MAP_enum +-{ +- PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP0MAP_t; +- +-/* Virtual Port 1 Mapping */ +-typedef enum PORTCFG_VP1MAP_enum +-{ +- PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP1MAP_t; +- +-/* Virtual Port 2 Mapping */ +-typedef enum PORTCFG_VP2MAP_enum +-{ +- PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP2MAP_t; +- +-/* Virtual Port 3 Mapping */ +-typedef enum PORTCFG_VP3MAP_enum +-{ +- PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP3MAP_t; +- +-/* Clock Output Port */ +-typedef enum PORTCFG_CLKOUT_enum +-{ +- PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ +- PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ +- PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ +- PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +-} PORTCFG_CLKOUT_t; +- +-/* Event Output Port */ +-typedef enum PORTCFG_EVOUT_enum +-{ +- PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ +- PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ +- PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ +- PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +-} PORTCFG_EVOUT_t; +- +-/* Port Interrupt 0 Level */ +-typedef enum PORT_INT0LVL_enum +-{ +- PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ +- PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ +- PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +-} PORT_INT0LVL_t; +- +-/* Port Interrupt 1 Level */ +-typedef enum PORT_INT1LVL_enum +-{ +- PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ +- PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ +- PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +-} PORT_INT1LVL_t; +- +-/* Output/Pull Configuration */ +-typedef enum PORT_OPC_enum +-{ +- PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ +- PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ +- PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ +- PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ +- PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ +- PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ +- PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ +- PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +-} PORT_OPC_t; +- +-/* Input/Sense Configuration */ +-typedef enum PORT_ISC_enum +-{ +- PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ +- PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ +- PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ +- PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ +- PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +-} PORT_ISC_t; +- +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 0 */ +-typedef struct TC0_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- _WORDREGISTER(CCC); /* Compare or Capture C */ +- _WORDREGISTER(CCD); /* Compare or Capture D */ +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +- _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ +- _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +-} TC0_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 1 */ +-typedef struct TC1_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t reserved_0x2E; +- register8_t reserved_0x2F; +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +-} TC1_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* Advanced Waveform Extension */ +-typedef struct AWEX_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t FDEMASK; /* Fault Detection Event Mask */ +- register8_t FDCTRL; /* Fault Detection Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x05; +- register8_t DTBOTH; /* Dead Time Both Sides */ +- register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ +- register8_t DTLS; /* Dead Time Low Side */ +- register8_t DTHS; /* Dead Time High Side */ +- register8_t DTLSBUF; /* Dead Time Low Side Buffer */ +- register8_t DTHSBUF; /* Dead Time High Side Buffer */ +- register8_t OUTOVEN; /* Output Override Enable */ +-} AWEX_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* High-Resolution Extension */ +-typedef struct HIRES_struct +-{ +- register8_t CTRLA; /* Control Register A */ +-} HIRES_t; +- +-/* Clock Selection */ +-typedef enum TC_CLKSEL_enum +-{ +- TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ +- TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ +- TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ +- TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ +- TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ +- TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ +- TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ +- TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ +- TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_CLKSEL_t; +- +-/* Waveform Generation Mode */ +-typedef enum TC_WGMODE_enum +-{ +- TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ +- TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ +- TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ +- TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ +- TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ +- TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +-} TC_WGMODE_t; +- +-/* Event Action */ +-typedef enum TC_EVACT_enum +-{ +- TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ +- TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ +- TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ +- TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ +- TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ +- TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ +- TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +-} TC_EVACT_t; +- +-/* Event Selection */ +-typedef enum TC_EVSEL_enum +-{ +- TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_EVSEL_t; +- +-/* Error Interrupt Level */ +-typedef enum TC_ERRINTLVL_enum +-{ +- TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_ERRINTLVL_t; +- +-/* Overflow Interrupt Level */ +-typedef enum TC_OVFINTLVL_enum +-{ +- TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_OVFINTLVL_t; +- +-/* Compare or Capture D Interrupt Level */ +-typedef enum TC_CCDINTLVL_enum +-{ +- TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TC_CCDINTLVL_t; +- +-/* Compare or Capture C Interrupt Level */ +-typedef enum TC_CCCINTLVL_enum +-{ +- TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} TC_CCCINTLVL_t; +- +-/* Compare or Capture B Interrupt Level */ +-typedef enum TC_CCBINTLVL_enum +-{ +- TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_CCBINTLVL_t; +- +-/* Compare or Capture A Interrupt Level */ +-typedef enum TC_CCAINTLVL_enum +-{ +- TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_CCAINTLVL_t; +- +-/* Timer/Counter Command */ +-typedef enum TC_CMD_enum +-{ +- TC_CMD_NONE_gc = (0x00<<2), /* No Command */ +- TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ +- TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ +- TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +-} TC_CMD_t; +- +-/* Fault Detect Action */ +-typedef enum AWEX_FDACT_enum +-{ +- AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ +- AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ +- AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +-} AWEX_FDACT_t; +- +-/* High Resolution Enable */ +-typedef enum HIRES_HREN_enum +-{ +- HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ +- HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ +- HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ +- HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +-} HIRES_HREN_t; +- +- +-/* +--------------------------------------------------------------------------- +-USART - Universal Asynchronous Receiver-Transmitter +--------------------------------------------------------------------------- +-*/ +- +-/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +-typedef struct USART_struct +-{ +- register8_t DATA; /* Data Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x02; +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t BAUDCTRLA; /* Baud Rate Control Register A */ +- register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +-} USART_t; +- +-/* Receive Complete Interrupt level */ +-typedef enum USART_RXCINTLVL_enum +-{ +- USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} USART_RXCINTLVL_t; +- +-/* Transmit Complete Interrupt level */ +-typedef enum USART_TXCINTLVL_enum +-{ +- USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} USART_TXCINTLVL_t; +- +-/* Data Register Empty Interrupt level */ +-typedef enum USART_DREINTLVL_enum +-{ +- USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} USART_DREINTLVL_t; +- +-/* Character Size */ +-typedef enum USART_CHSIZE_enum +-{ +- USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ +- USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ +- USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ +- USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ +- USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +-} USART_CHSIZE_t; +- +-/* Communication Mode */ +-typedef enum USART_CMODE_enum +-{ +- USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ +- USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ +- USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ +- USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +-} USART_CMODE_t; +- +-/* Parity Mode */ +-typedef enum USART_PMODE_enum +-{ +- USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ +- USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ +- USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +-} USART_PMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-SPI - Serial Peripheral Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Serial Peripheral Interface */ +-typedef struct SPI_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t DATA; /* Data Register */ +-} SPI_t; +- +-/* SPI Mode */ +-typedef enum SPI_MODE_enum +-{ +- SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ +- SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ +- SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ +- SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +-} SPI_MODE_t; +- +-/* Prescaler setting */ +-typedef enum SPI_PRESCALER_enum +-{ +- SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ +- SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ +- SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ +- SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +-} SPI_PRESCALER_t; +- +-/* Interrupt level */ +-typedef enum SPI_INTLVL_enum +-{ +- SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} SPI_INTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-IRCOM - IR Communication Module +--------------------------------------------------------------------------- +-*/ +- +-/* IR Communication Module */ +-typedef struct IRCOM_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ +- register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +-} IRCOM_t; +- +-/* Event channel selection */ +-typedef enum IRDA_EVSEL_enum +-{ +- IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ +- IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ +- IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ +- IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +- IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ +- IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ +- IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ +- IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +-} IRDA_EVSEL_t; +- +- +-/* +--------------------------------------------------------------------------- +-AES - AES Module +--------------------------------------------------------------------------- +-*/ +- +-/* AES Module */ +-typedef struct AES_struct +-{ +- register8_t CTRL; /* AES Control Register */ +- register8_t STATUS; /* AES Status Register */ +- register8_t STATE; /* AES State Register */ +- register8_t KEY; /* AES Key Register */ +- register8_t INTCTRL; /* AES Interrupt Control Register */ +-} AES_t; +- +-/* Interrupt level */ +-typedef enum AES_INTLVL_enum +-{ +- AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} AES_INTLVL_t; +- +- +- +-/* +-========================================================================== +-IO Module Instances. Mapped to memory. +-========================================================================== +-*/ +- +-#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +-#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +-#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +-#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +-#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +-#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +-#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +-#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +-#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +-#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +-#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +-#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +-#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +-#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +-#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +-#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +-#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ +-#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +-#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +-#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +-#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +-#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ +-#define DACA (*(DAC_t *) 0x0300) /* Digital to Analog Converter A */ +-#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ +-#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +-#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ +-#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +-#define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */ +-#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +-#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface D */ +-#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ +-#define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface F */ +-#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +-#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +-#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +-#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +-#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +-#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ +-#define PORTH (*(PORT_t *) 0x06E0) /* Port H */ +-#define PORTJ (*(PORT_t *) 0x0700) /* Port J */ +-#define PORTK (*(PORT_t *) 0x0720) /* Port K */ +-#define PORTQ (*(PORT_t *) 0x07C0) /* Port Q */ +-#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +-#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +-#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +-#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +-#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +-#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +-#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ +-#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +-#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +-#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +-#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ +-#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ +-#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +-#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ +-#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +-#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +-#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ +-#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ +-#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ +-#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ +-#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ +-#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ +-#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ +-#define TCF1 (*(TC1_t *) 0x0B40) /* Timer/Counter F1 */ +-#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ +-#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ +-#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ +-#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ +- +- +-#endif /* !defined (__ASSEMBLER__) */ +- +- +-/* ========== Flattened fully qualified IO register names ========== */ +- +-/* GPIO - General Purpose IO Registers */ +-#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +-#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +-#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +-#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +-#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +-#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +-#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +-#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +-#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +-#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +-#define GPIO_GPIORA _SFR_MEM8(0x000A) +-#define GPIO_GPIORB _SFR_MEM8(0x000B) +-#define GPIO_GPIORC _SFR_MEM8(0x000C) +-#define GPIO_GPIORD _SFR_MEM8(0x000D) +-#define GPIO_GPIORE _SFR_MEM8(0x000E) +-#define GPIO_GPIORF _SFR_MEM8(0x000F) +- +-/* Deprecated */ +-#define GPIO_GPIO0 _SFR_MEM8(0x0000) +-#define GPIO_GPIO1 _SFR_MEM8(0x0001) +-#define GPIO_GPIO2 _SFR_MEM8(0x0002) +-#define GPIO_GPIO3 _SFR_MEM8(0x0003) +-#define GPIO_GPIO4 _SFR_MEM8(0x0004) +-#define GPIO_GPIO5 _SFR_MEM8(0x0005) +-#define GPIO_GPIO6 _SFR_MEM8(0x0006) +-#define GPIO_GPIO7 _SFR_MEM8(0x0007) +-#define GPIO_GPIO8 _SFR_MEM8(0x0008) +-#define GPIO_GPIO9 _SFR_MEM8(0x0009) +-#define GPIO_GPIOA _SFR_MEM8(0x000A) +-#define GPIO_GPIOB _SFR_MEM8(0x000B) +-#define GPIO_GPIOC _SFR_MEM8(0x000C) +-#define GPIO_GPIOD _SFR_MEM8(0x000D) +-#define GPIO_GPIOE _SFR_MEM8(0x000E) +-#define GPIO_GPIOF _SFR_MEM8(0x000F) +- +-/* VPORT0 - Virtual Port 0 */ +-#define VPORT0_DIR _SFR_MEM8(0x0010) +-#define VPORT0_OUT _SFR_MEM8(0x0011) +-#define VPORT0_IN _SFR_MEM8(0x0012) +-#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) +- +-/* VPORT1 - Virtual Port 1 */ +-#define VPORT1_DIR _SFR_MEM8(0x0014) +-#define VPORT1_OUT _SFR_MEM8(0x0015) +-#define VPORT1_IN _SFR_MEM8(0x0016) +-#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) +- +-/* VPORT2 - Virtual Port 2 */ +-#define VPORT2_DIR _SFR_MEM8(0x0018) +-#define VPORT2_OUT _SFR_MEM8(0x0019) +-#define VPORT2_IN _SFR_MEM8(0x001A) +-#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) +- +-/* VPORT3 - Virtual Port 3 */ +-#define VPORT3_DIR _SFR_MEM8(0x001C) +-#define VPORT3_OUT _SFR_MEM8(0x001D) +-#define VPORT3_IN _SFR_MEM8(0x001E) +-#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) +- +-/* OCD - On-Chip Debug System */ +-#define OCD_OCDR0 _SFR_MEM8(0x002E) +-#define OCD_OCDR1 _SFR_MEM8(0x002F) +- +-/* CPU - CPU Registers */ +-#define CPU_CCP _SFR_MEM8(0x0034) +-#define CPU_RAMPD _SFR_MEM8(0x0038) +-#define CPU_RAMPX _SFR_MEM8(0x0039) +-#define CPU_RAMPY _SFR_MEM8(0x003A) +-#define CPU_RAMPZ _SFR_MEM8(0x003B) +-#define CPU_EIND _SFR_MEM8(0x003C) +-#define CPU_SPL _SFR_MEM8(0x003D) +-#define CPU_SPH _SFR_MEM8(0x003E) +-#define CPU_SREG _SFR_MEM8(0x003F) +- +-/* CLK - Clock System */ +-#define CLK_CTRL _SFR_MEM8(0x0040) +-#define CLK_PSCTRL _SFR_MEM8(0x0041) +-#define CLK_LOCK _SFR_MEM8(0x0042) +-#define CLK_RTCCTRL _SFR_MEM8(0x0043) +- +-/* SLEEP - Sleep Controller */ +-#define SLEEP_CTRL _SFR_MEM8(0x0048) +- +-/* OSC - Oscillator Control */ +-#define OSC_CTRL _SFR_MEM8(0x0050) +-#define OSC_STATUS _SFR_MEM8(0x0051) +-#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +-#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +-#define OSC_RC32KCAL _SFR_MEM8(0x0054) +-#define OSC_PLLCTRL _SFR_MEM8(0x0055) +-#define OSC_DFLLCTRL _SFR_MEM8(0x0056) +- +-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +-#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +-#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +-#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +-#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +-#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +-#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) +- +-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +-#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +-#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +-#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +-#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +-#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +-#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) +- +-/* PR - Power Reduction */ +-#define PR_PRGEN _SFR_MEM8(0x0070) +-#define PR_PRPA _SFR_MEM8(0x0071) +-#define PR_PRPB _SFR_MEM8(0x0072) +-#define PR_PRPC _SFR_MEM8(0x0073) +-#define PR_PRPD _SFR_MEM8(0x0074) +-#define PR_PRPE _SFR_MEM8(0x0075) +-#define PR_PRPF _SFR_MEM8(0x0076) +- +-/* RST - Reset Controller */ +-#define RST_STATUS _SFR_MEM8(0x0078) +-#define RST_CTRL _SFR_MEM8(0x0079) +- +-/* WDT - Watch-Dog Timer */ +-#define WDT_CTRL _SFR_MEM8(0x0080) +-#define WDT_WINCTRL _SFR_MEM8(0x0081) +-#define WDT_STATUS _SFR_MEM8(0x0082) +- +-/* MCU - MCU Control */ +-#define MCU_DEVID0 _SFR_MEM8(0x0090) +-#define MCU_DEVID1 _SFR_MEM8(0x0091) +-#define MCU_DEVID2 _SFR_MEM8(0x0092) +-#define MCU_REVID _SFR_MEM8(0x0093) +-#define MCU_JTAGUID _SFR_MEM8(0x0094) +-#define MCU_MCUCR _SFR_MEM8(0x0096) +-#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +-#define MCU_AWEXLOCK _SFR_MEM8(0x0099) +- +-/* PMIC - Programmable Interrupt Controller */ +-#define PMIC_STATUS _SFR_MEM8(0x00A0) +-#define PMIC_INTPRI _SFR_MEM8(0x00A1) +-#define PMIC_CTRL _SFR_MEM8(0x00A2) +- +-/* PORTCFG - Port Configuration */ +-#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +-#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +-#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +-#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +- +-/* AES - AES Crypto Module */ +-#define AES_CTRL _SFR_MEM8(0x00C0) +-#define AES_STATUS _SFR_MEM8(0x00C1) +-#define AES_STATE _SFR_MEM8(0x00C2) +-#define AES_KEY _SFR_MEM8(0x00C3) +-#define AES_INTCTRL _SFR_MEM8(0x00C4) +- +-/* DMA - DMA Controller */ +-#define DMA_CTRL _SFR_MEM8(0x0100) +-#define DMA_INTFLAGS _SFR_MEM8(0x0103) +-#define DMA_STATUS _SFR_MEM8(0x0104) +-#define DMA_TEMP _SFR_MEM16(0x0106) +-#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +-#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +-#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +-#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +-#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +-#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +-#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +-#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +-#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +-#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +-#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +-#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +-#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +-#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +-#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +-#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +-#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +-#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +-#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +-#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +-#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +-#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +-#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +-#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +-#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +-#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +-#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +-#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +-#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +-#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +-#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +-#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +-#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +-#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +-#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +-#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +-#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +-#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +-#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +-#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +-#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +-#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +-#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +-#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +-#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +-#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +-#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +-#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) +- +-/* EVSYS - Event System */ +-#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +-#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +-#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +-#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +-#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +-#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +-#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +-#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +-#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +-#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +-#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +-#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +-#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +-#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +-#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +-#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +-#define EVSYS_STROBE _SFR_MEM8(0x0190) +-#define EVSYS_DATA _SFR_MEM8(0x0191) +- +-/* NVM - Non Volatile Memory Controller */ +-#define NVM_ADDR0 _SFR_MEM8(0x01C0) +-#define NVM_ADDR1 _SFR_MEM8(0x01C1) +-#define NVM_ADDR2 _SFR_MEM8(0x01C2) +-#define NVM_DATA0 _SFR_MEM8(0x01C4) +-#define NVM_DATA1 _SFR_MEM8(0x01C5) +-#define NVM_DATA2 _SFR_MEM8(0x01C6) +-#define NVM_CMD _SFR_MEM8(0x01CA) +-#define NVM_CTRLA _SFR_MEM8(0x01CB) +-#define NVM_CTRLB _SFR_MEM8(0x01CC) +-#define NVM_INTCTRL _SFR_MEM8(0x01CD) +-#define NVM_STATUS _SFR_MEM8(0x01CF) +-#define NVM_LOCKBITS _SFR_MEM8(0x01D0) +- +-/* ADCA - Analog to Digital Converter A */ +-#define ADCA_CTRLA _SFR_MEM8(0x0200) +-#define ADCA_CTRLB _SFR_MEM8(0x0201) +-#define ADCA_REFCTRL _SFR_MEM8(0x0202) +-#define ADCA_EVCTRL _SFR_MEM8(0x0203) +-#define ADCA_PRESCALER _SFR_MEM8(0x0204) +-#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +-#define ADCA_CAL _SFR_MEM16(0x020C) +-#define ADCA_CH0RES _SFR_MEM16(0x0210) +-#define ADCA_CH1RES _SFR_MEM16(0x0212) +-#define ADCA_CH2RES _SFR_MEM16(0x0214) +-#define ADCA_CH3RES _SFR_MEM16(0x0216) +-#define ADCA_CMP _SFR_MEM16(0x0218) +-#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +-#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +-#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +-#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +-#define ADCA_CH0_RES _SFR_MEM16(0x0224) +-#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +-#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +-#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +-#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +-#define ADCA_CH1_RES _SFR_MEM16(0x022C) +-#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +-#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +-#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +-#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +-#define ADCA_CH2_RES _SFR_MEM16(0x0234) +-#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +-#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +-#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +-#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +-#define ADCA_CH3_RES _SFR_MEM16(0x023C) +- +-/* ADCB - Analog to Digital Converter B */ +-#define ADCB_CTRLA _SFR_MEM8(0x0240) +-#define ADCB_CTRLB _SFR_MEM8(0x0241) +-#define ADCB_REFCTRL _SFR_MEM8(0x0242) +-#define ADCB_EVCTRL _SFR_MEM8(0x0243) +-#define ADCB_PRESCALER _SFR_MEM8(0x0244) +-#define ADCB_INTFLAGS _SFR_MEM8(0x0246) +-#define ADCB_CAL _SFR_MEM16(0x024C) +-#define ADCB_CH0RES _SFR_MEM16(0x0250) +-#define ADCB_CH1RES _SFR_MEM16(0x0252) +-#define ADCB_CH2RES _SFR_MEM16(0x0254) +-#define ADCB_CH3RES _SFR_MEM16(0x0256) +-#define ADCB_CMP _SFR_MEM16(0x0258) +-#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) +-#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) +-#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) +-#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) +-#define ADCB_CH0_RES _SFR_MEM16(0x0264) +-#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) +-#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) +-#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) +-#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) +-#define ADCB_CH1_RES _SFR_MEM16(0x026C) +-#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) +-#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) +-#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) +-#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) +-#define ADCB_CH2_RES _SFR_MEM16(0x0274) +-#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) +-#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) +-#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) +-#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) +-#define ADCB_CH3_RES _SFR_MEM16(0x027C) +- +-/* DACA - Digital to Analog Converter A */ +-#define DACA_CTRLA _SFR_MEM8(0x0300) +-#define DACA_CTRLB _SFR_MEM8(0x0301) +-#define DACA_CTRLC _SFR_MEM8(0x0302) +-#define DACA_EVCTRL _SFR_MEM8(0x0303) +-#define DACA_TIMCTRL _SFR_MEM8(0x0304) +-#define DACA_STATUS _SFR_MEM8(0x0305) +-#define DACA_GAINCAL _SFR_MEM8(0x0308) +-#define DACA_OFFSETCAL _SFR_MEM8(0x0309) +-#define DACA_CH0DATA _SFR_MEM16(0x0318) +-#define DACA_CH1DATA _SFR_MEM16(0x031A) +- +-/* DACB - Digital to Analog Converter B */ +-#define DACB_CTRLA _SFR_MEM8(0x0320) +-#define DACB_CTRLB _SFR_MEM8(0x0321) +-#define DACB_CTRLC _SFR_MEM8(0x0322) +-#define DACB_EVCTRL _SFR_MEM8(0x0323) +-#define DACB_TIMCTRL _SFR_MEM8(0x0324) +-#define DACB_STATUS _SFR_MEM8(0x0325) +-#define DACB_GAINCAL _SFR_MEM8(0x0328) +-#define DACB_OFFSETCAL _SFR_MEM8(0x0329) +-#define DACB_CH0DATA _SFR_MEM16(0x0338) +-#define DACB_CH1DATA _SFR_MEM16(0x033A) +- +-/* ACA - Analog Comparator A */ +-#define ACA_AC0CTRL _SFR_MEM8(0x0380) +-#define ACA_AC1CTRL _SFR_MEM8(0x0381) +-#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +-#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +-#define ACA_CTRLA _SFR_MEM8(0x0384) +-#define ACA_CTRLB _SFR_MEM8(0x0385) +-#define ACA_WINCTRL _SFR_MEM8(0x0386) +-#define ACA_STATUS _SFR_MEM8(0x0387) +- +-/* ACB - Analog Comparator B */ +-#define ACB_AC0CTRL _SFR_MEM8(0x0390) +-#define ACB_AC1CTRL _SFR_MEM8(0x0391) +-#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +-#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +-#define ACB_CTRLA _SFR_MEM8(0x0394) +-#define ACB_CTRLB _SFR_MEM8(0x0395) +-#define ACB_WINCTRL _SFR_MEM8(0x0396) +-#define ACB_STATUS _SFR_MEM8(0x0397) +- +-/* RTC - Real-Time Counter */ +-#define RTC_CTRL _SFR_MEM8(0x0400) +-#define RTC_STATUS _SFR_MEM8(0x0401) +-#define RTC_INTCTRL _SFR_MEM8(0x0402) +-#define RTC_INTFLAGS _SFR_MEM8(0x0403) +-#define RTC_TEMP _SFR_MEM8(0x0404) +-#define RTC_CNT _SFR_MEM16(0x0408) +-#define RTC_PER _SFR_MEM16(0x040A) +-#define RTC_COMP _SFR_MEM16(0x040C) +- +-/* EBI - External Bus Interface */ +-#define EBI_CTRL _SFR_MEM8(0x0440) +-#define EBI_SDRAMCTRLA _SFR_MEM8(0x0441) +-#define EBI_REFRESH _SFR_MEM16(0x0444) +-#define EBI_INITDLY _SFR_MEM16(0x0446) +-#define EBI_SDRAMCTRLB _SFR_MEM8(0x0448) +-#define EBI_SDRAMCTRLC _SFR_MEM8(0x0449) +-#define EBI_CS0_CTRLA _SFR_MEM8(0x0450) +-#define EBI_CS0_CTRLB _SFR_MEM8(0x0451) +-#define EBI_CS0_BASEADDR _SFR_MEM16(0x0452) +-#define EBI_CS1_CTRLA _SFR_MEM8(0x0454) +-#define EBI_CS1_CTRLB _SFR_MEM8(0x0455) +-#define EBI_CS1_BASEADDR _SFR_MEM16(0x0456) +-#define EBI_CS2_CTRLA _SFR_MEM8(0x0458) +-#define EBI_CS2_CTRLB _SFR_MEM8(0x0459) +-#define EBI_CS2_BASEADDR _SFR_MEM16(0x045A) +-#define EBI_CS3_CTRLA _SFR_MEM8(0x045C) +-#define EBI_CS3_CTRLB _SFR_MEM8(0x045D) +-#define EBI_CS3_BASEADDR _SFR_MEM16(0x045E) +- +-/* TWIC - Two-Wire Interface C */ +-#define TWIC_CTRL _SFR_MEM8(0x0480) +-#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +-#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +-#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +-#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +-#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +-#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +-#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +-#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +-#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +-#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +-#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +-#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +-#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) +- +-/* TWID - Two-Wire Interface D */ +-#define TWID_CTRL _SFR_MEM8(0x0490) +-#define TWID_MASTER_CTRLA _SFR_MEM8(0x0491) +-#define TWID_MASTER_CTRLB _SFR_MEM8(0x0492) +-#define TWID_MASTER_CTRLC _SFR_MEM8(0x0493) +-#define TWID_MASTER_STATUS _SFR_MEM8(0x0494) +-#define TWID_MASTER_BAUD _SFR_MEM8(0x0495) +-#define TWID_MASTER_ADDR _SFR_MEM8(0x0496) +-#define TWID_MASTER_DATA _SFR_MEM8(0x0497) +-#define TWID_SLAVE_CTRLA _SFR_MEM8(0x0498) +-#define TWID_SLAVE_CTRLB _SFR_MEM8(0x0499) +-#define TWID_SLAVE_STATUS _SFR_MEM8(0x049A) +-#define TWID_SLAVE_ADDR _SFR_MEM8(0x049B) +-#define TWID_SLAVE_DATA _SFR_MEM8(0x049C) +-#define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D) +- +-/* TWIE - Two-Wire Interface E */ +-#define TWIE_CTRL _SFR_MEM8(0x04A0) +-#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +-#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +-#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +-#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +-#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +-#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +-#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +-#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +-#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +-#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +-#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +-#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +-#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) +- +-/* TWIF - Two-Wire Interface F */ +-#define TWIF_CTRL _SFR_MEM8(0x04B0) +-#define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1) +-#define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2) +-#define TWIF_MASTER_CTRLC _SFR_MEM8(0x04B3) +-#define TWIF_MASTER_STATUS _SFR_MEM8(0x04B4) +-#define TWIF_MASTER_BAUD _SFR_MEM8(0x04B5) +-#define TWIF_MASTER_ADDR _SFR_MEM8(0x04B6) +-#define TWIF_MASTER_DATA _SFR_MEM8(0x04B7) +-#define TWIF_SLAVE_CTRLA _SFR_MEM8(0x04B8) +-#define TWIF_SLAVE_CTRLB _SFR_MEM8(0x04B9) +-#define TWIF_SLAVE_STATUS _SFR_MEM8(0x04BA) +-#define TWIF_SLAVE_ADDR _SFR_MEM8(0x04BB) +-#define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC) +-#define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD) +- +-/* PORTA - Port A */ +-#define PORTA_DIR _SFR_MEM8(0x0600) +-#define PORTA_DIRSET _SFR_MEM8(0x0601) +-#define PORTA_DIRCLR _SFR_MEM8(0x0602) +-#define PORTA_DIRTGL _SFR_MEM8(0x0603) +-#define PORTA_OUT _SFR_MEM8(0x0604) +-#define PORTA_OUTSET _SFR_MEM8(0x0605) +-#define PORTA_OUTCLR _SFR_MEM8(0x0606) +-#define PORTA_OUTTGL _SFR_MEM8(0x0607) +-#define PORTA_IN _SFR_MEM8(0x0608) +-#define PORTA_INTCTRL _SFR_MEM8(0x0609) +-#define PORTA_INT0MASK _SFR_MEM8(0x060A) +-#define PORTA_INT1MASK _SFR_MEM8(0x060B) +-#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +-#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +-#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +-#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +-#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +-#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +-#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +-#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +-#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) +- +-/* PORTB - Port B */ +-#define PORTB_DIR _SFR_MEM8(0x0620) +-#define PORTB_DIRSET _SFR_MEM8(0x0621) +-#define PORTB_DIRCLR _SFR_MEM8(0x0622) +-#define PORTB_DIRTGL _SFR_MEM8(0x0623) +-#define PORTB_OUT _SFR_MEM8(0x0624) +-#define PORTB_OUTSET _SFR_MEM8(0x0625) +-#define PORTB_OUTCLR _SFR_MEM8(0x0626) +-#define PORTB_OUTTGL _SFR_MEM8(0x0627) +-#define PORTB_IN _SFR_MEM8(0x0628) +-#define PORTB_INTCTRL _SFR_MEM8(0x0629) +-#define PORTB_INT0MASK _SFR_MEM8(0x062A) +-#define PORTB_INT1MASK _SFR_MEM8(0x062B) +-#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +-#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +-#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +-#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +-#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +-#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +-#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +-#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +-#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) +- +-/* PORTC - Port C */ +-#define PORTC_DIR _SFR_MEM8(0x0640) +-#define PORTC_DIRSET _SFR_MEM8(0x0641) +-#define PORTC_DIRCLR _SFR_MEM8(0x0642) +-#define PORTC_DIRTGL _SFR_MEM8(0x0643) +-#define PORTC_OUT _SFR_MEM8(0x0644) +-#define PORTC_OUTSET _SFR_MEM8(0x0645) +-#define PORTC_OUTCLR _SFR_MEM8(0x0646) +-#define PORTC_OUTTGL _SFR_MEM8(0x0647) +-#define PORTC_IN _SFR_MEM8(0x0648) +-#define PORTC_INTCTRL _SFR_MEM8(0x0649) +-#define PORTC_INT0MASK _SFR_MEM8(0x064A) +-#define PORTC_INT1MASK _SFR_MEM8(0x064B) +-#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +-#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +-#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +-#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +-#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +-#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +-#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +-#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +-#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) +- +-/* PORTD - Port D */ +-#define PORTD_DIR _SFR_MEM8(0x0660) +-#define PORTD_DIRSET _SFR_MEM8(0x0661) +-#define PORTD_DIRCLR _SFR_MEM8(0x0662) +-#define PORTD_DIRTGL _SFR_MEM8(0x0663) +-#define PORTD_OUT _SFR_MEM8(0x0664) +-#define PORTD_OUTSET _SFR_MEM8(0x0665) +-#define PORTD_OUTCLR _SFR_MEM8(0x0666) +-#define PORTD_OUTTGL _SFR_MEM8(0x0667) +-#define PORTD_IN _SFR_MEM8(0x0668) +-#define PORTD_INTCTRL _SFR_MEM8(0x0669) +-#define PORTD_INT0MASK _SFR_MEM8(0x066A) +-#define PORTD_INT1MASK _SFR_MEM8(0x066B) +-#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +-#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +-#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +-#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +-#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +-#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +-#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +-#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +-#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) +- +-/* PORTE - Port E */ +-#define PORTE_DIR _SFR_MEM8(0x0680) +-#define PORTE_DIRSET _SFR_MEM8(0x0681) +-#define PORTE_DIRCLR _SFR_MEM8(0x0682) +-#define PORTE_DIRTGL _SFR_MEM8(0x0683) +-#define PORTE_OUT _SFR_MEM8(0x0684) +-#define PORTE_OUTSET _SFR_MEM8(0x0685) +-#define PORTE_OUTCLR _SFR_MEM8(0x0686) +-#define PORTE_OUTTGL _SFR_MEM8(0x0687) +-#define PORTE_IN _SFR_MEM8(0x0688) +-#define PORTE_INTCTRL _SFR_MEM8(0x0689) +-#define PORTE_INT0MASK _SFR_MEM8(0x068A) +-#define PORTE_INT1MASK _SFR_MEM8(0x068B) +-#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +-#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +-#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +-#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +-#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +-#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +-#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +-#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +-#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) +- +-/* PORTF - Port F */ +-#define PORTF_DIR _SFR_MEM8(0x06A0) +-#define PORTF_DIRSET _SFR_MEM8(0x06A1) +-#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +-#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +-#define PORTF_OUT _SFR_MEM8(0x06A4) +-#define PORTF_OUTSET _SFR_MEM8(0x06A5) +-#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +-#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +-#define PORTF_IN _SFR_MEM8(0x06A8) +-#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +-#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +-#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +-#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +-#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +-#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +-#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +-#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +-#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +-#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +-#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +-#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) +- +-/* PORTH - Port H */ +-#define PORTH_DIR _SFR_MEM8(0x06E0) +-#define PORTH_DIRSET _SFR_MEM8(0x06E1) +-#define PORTH_DIRCLR _SFR_MEM8(0x06E2) +-#define PORTH_DIRTGL _SFR_MEM8(0x06E3) +-#define PORTH_OUT _SFR_MEM8(0x06E4) +-#define PORTH_OUTSET _SFR_MEM8(0x06E5) +-#define PORTH_OUTCLR _SFR_MEM8(0x06E6) +-#define PORTH_OUTTGL _SFR_MEM8(0x06E7) +-#define PORTH_IN _SFR_MEM8(0x06E8) +-#define PORTH_INTCTRL _SFR_MEM8(0x06E9) +-#define PORTH_INT0MASK _SFR_MEM8(0x06EA) +-#define PORTH_INT1MASK _SFR_MEM8(0x06EB) +-#define PORTH_INTFLAGS _SFR_MEM8(0x06EC) +-#define PORTH_PIN0CTRL _SFR_MEM8(0x06F0) +-#define PORTH_PIN1CTRL _SFR_MEM8(0x06F1) +-#define PORTH_PIN2CTRL _SFR_MEM8(0x06F2) +-#define PORTH_PIN3CTRL _SFR_MEM8(0x06F3) +-#define PORTH_PIN4CTRL _SFR_MEM8(0x06F4) +-#define PORTH_PIN5CTRL _SFR_MEM8(0x06F5) +-#define PORTH_PIN6CTRL _SFR_MEM8(0x06F6) +-#define PORTH_PIN7CTRL _SFR_MEM8(0x06F7) +- +-/* PORTJ - Port J */ +-#define PORTJ_DIR _SFR_MEM8(0x0700) +-#define PORTJ_DIRSET _SFR_MEM8(0x0701) +-#define PORTJ_DIRCLR _SFR_MEM8(0x0702) +-#define PORTJ_DIRTGL _SFR_MEM8(0x0703) +-#define PORTJ_OUT _SFR_MEM8(0x0704) +-#define PORTJ_OUTSET _SFR_MEM8(0x0705) +-#define PORTJ_OUTCLR _SFR_MEM8(0x0706) +-#define PORTJ_OUTTGL _SFR_MEM8(0x0707) +-#define PORTJ_IN _SFR_MEM8(0x0708) +-#define PORTJ_INTCTRL _SFR_MEM8(0x0709) +-#define PORTJ_INT0MASK _SFR_MEM8(0x070A) +-#define PORTJ_INT1MASK _SFR_MEM8(0x070B) +-#define PORTJ_INTFLAGS _SFR_MEM8(0x070C) +-#define PORTJ_PIN0CTRL _SFR_MEM8(0x0710) +-#define PORTJ_PIN1CTRL _SFR_MEM8(0x0711) +-#define PORTJ_PIN2CTRL _SFR_MEM8(0x0712) +-#define PORTJ_PIN3CTRL _SFR_MEM8(0x0713) +-#define PORTJ_PIN4CTRL _SFR_MEM8(0x0714) +-#define PORTJ_PIN5CTRL _SFR_MEM8(0x0715) +-#define PORTJ_PIN6CTRL _SFR_MEM8(0x0716) +-#define PORTJ_PIN7CTRL _SFR_MEM8(0x0717) +- +-/* PORTK - Port K */ +-#define PORTK_DIR _SFR_MEM8(0x0720) +-#define PORTK_DIRSET _SFR_MEM8(0x0721) +-#define PORTK_DIRCLR _SFR_MEM8(0x0722) +-#define PORTK_DIRTGL _SFR_MEM8(0x0723) +-#define PORTK_OUT _SFR_MEM8(0x0724) +-#define PORTK_OUTSET _SFR_MEM8(0x0725) +-#define PORTK_OUTCLR _SFR_MEM8(0x0726) +-#define PORTK_OUTTGL _SFR_MEM8(0x0727) +-#define PORTK_IN _SFR_MEM8(0x0728) +-#define PORTK_INTCTRL _SFR_MEM8(0x0729) +-#define PORTK_INT0MASK _SFR_MEM8(0x072A) +-#define PORTK_INT1MASK _SFR_MEM8(0x072B) +-#define PORTK_INTFLAGS _SFR_MEM8(0x072C) +-#define PORTK_PIN0CTRL _SFR_MEM8(0x0730) +-#define PORTK_PIN1CTRL _SFR_MEM8(0x0731) +-#define PORTK_PIN2CTRL _SFR_MEM8(0x0732) +-#define PORTK_PIN3CTRL _SFR_MEM8(0x0733) +-#define PORTK_PIN4CTRL _SFR_MEM8(0x0734) +-#define PORTK_PIN5CTRL _SFR_MEM8(0x0735) +-#define PORTK_PIN6CTRL _SFR_MEM8(0x0736) +-#define PORTK_PIN7CTRL _SFR_MEM8(0x0737) +- +-/* PORTQ - Port Q */ +-#define PORTQ_DIR _SFR_MEM8(0x07C0) +-#define PORTQ_DIRSET _SFR_MEM8(0x07C1) +-#define PORTQ_DIRCLR _SFR_MEM8(0x07C2) +-#define PORTQ_DIRTGL _SFR_MEM8(0x07C3) +-#define PORTQ_OUT _SFR_MEM8(0x07C4) +-#define PORTQ_OUTSET _SFR_MEM8(0x07C5) +-#define PORTQ_OUTCLR _SFR_MEM8(0x07C6) +-#define PORTQ_OUTTGL _SFR_MEM8(0x07C7) +-#define PORTQ_IN _SFR_MEM8(0x07C8) +-#define PORTQ_INTCTRL _SFR_MEM8(0x07C9) +-#define PORTQ_INT0MASK _SFR_MEM8(0x07CA) +-#define PORTQ_INT1MASK _SFR_MEM8(0x07CB) +-#define PORTQ_INTFLAGS _SFR_MEM8(0x07CC) +-#define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0) +-#define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1) +-#define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2) +-#define PORTQ_PIN3CTRL _SFR_MEM8(0x07D3) +-#define PORTQ_PIN4CTRL _SFR_MEM8(0x07D4) +-#define PORTQ_PIN5CTRL _SFR_MEM8(0x07D5) +-#define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6) +-#define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7) +- +-/* PORTR - Port R */ +-#define PORTR_DIR _SFR_MEM8(0x07E0) +-#define PORTR_DIRSET _SFR_MEM8(0x07E1) +-#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +-#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +-#define PORTR_OUT _SFR_MEM8(0x07E4) +-#define PORTR_OUTSET _SFR_MEM8(0x07E5) +-#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +-#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +-#define PORTR_IN _SFR_MEM8(0x07E8) +-#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +-#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +-#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +-#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +-#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +-#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +-#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +-#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +-#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +-#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +-#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +-#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) +- +-/* TCC0 - Timer/Counter C0 */ +-#define TCC0_CTRLA _SFR_MEM8(0x0800) +-#define TCC0_CTRLB _SFR_MEM8(0x0801) +-#define TCC0_CTRLC _SFR_MEM8(0x0802) +-#define TCC0_CTRLD _SFR_MEM8(0x0803) +-#define TCC0_CTRLE _SFR_MEM8(0x0804) +-#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +-#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +-#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +-#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +-#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +-#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +-#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +-#define TCC0_TEMP _SFR_MEM8(0x080F) +-#define TCC0_CNT _SFR_MEM16(0x0820) +-#define TCC0_PER _SFR_MEM16(0x0826) +-#define TCC0_CCA _SFR_MEM16(0x0828) +-#define TCC0_CCB _SFR_MEM16(0x082A) +-#define TCC0_CCC _SFR_MEM16(0x082C) +-#define TCC0_CCD _SFR_MEM16(0x082E) +-#define TCC0_PERBUF _SFR_MEM16(0x0836) +-#define TCC0_CCABUF _SFR_MEM16(0x0838) +-#define TCC0_CCBBUF _SFR_MEM16(0x083A) +-#define TCC0_CCCBUF _SFR_MEM16(0x083C) +-#define TCC0_CCDBUF _SFR_MEM16(0x083E) +- +-/* TCC1 - Timer/Counter C1 */ +-#define TCC1_CTRLA _SFR_MEM8(0x0840) +-#define TCC1_CTRLB _SFR_MEM8(0x0841) +-#define TCC1_CTRLC _SFR_MEM8(0x0842) +-#define TCC1_CTRLD _SFR_MEM8(0x0843) +-#define TCC1_CTRLE _SFR_MEM8(0x0844) +-#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +-#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +-#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +-#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +-#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +-#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +-#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +-#define TCC1_TEMP _SFR_MEM8(0x084F) +-#define TCC1_CNT _SFR_MEM16(0x0860) +-#define TCC1_PER _SFR_MEM16(0x0866) +-#define TCC1_CCA _SFR_MEM16(0x0868) +-#define TCC1_CCB _SFR_MEM16(0x086A) +-#define TCC1_PERBUF _SFR_MEM16(0x0876) +-#define TCC1_CCABUF _SFR_MEM16(0x0878) +-#define TCC1_CCBBUF _SFR_MEM16(0x087A) +- +-/* AWEXC - Advanced Waveform Extension C */ +-#define AWEXC_CTRL _SFR_MEM8(0x0880) +-#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +-#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +-#define AWEXC_STATUS _SFR_MEM8(0x0884) +-#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +-#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +-#define AWEXC_DTLS _SFR_MEM8(0x0888) +-#define AWEXC_DTHS _SFR_MEM8(0x0889) +-#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +-#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +-#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) +- +-/* HIRESC - High-Resolution Extension C */ +-#define HIRESC_CTRLA _SFR_MEM8(0x0890) +- +-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +-#define USARTC0_DATA _SFR_MEM8(0x08A0) +-#define USARTC0_STATUS _SFR_MEM8(0x08A1) +-#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +-#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +-#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +-#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +-#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) +- +-/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ +-#define USARTC1_DATA _SFR_MEM8(0x08B0) +-#define USARTC1_STATUS _SFR_MEM8(0x08B1) +-#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +-#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +-#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +-#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +-#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) +- +-/* SPIC - Serial Peripheral Interface C */ +-#define SPIC_CTRL _SFR_MEM8(0x08C0) +-#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +-#define SPIC_STATUS _SFR_MEM8(0x08C2) +-#define SPIC_DATA _SFR_MEM8(0x08C3) +- +-/* IRCOM - IR Communication Module */ +-#define IRCOM_CTRL _SFR_MEM8(0x08F8) +-#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +-#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) +- +-/* TCD0 - Timer/Counter D0 */ +-#define TCD0_CTRLA _SFR_MEM8(0x0900) +-#define TCD0_CTRLB _SFR_MEM8(0x0901) +-#define TCD0_CTRLC _SFR_MEM8(0x0902) +-#define TCD0_CTRLD _SFR_MEM8(0x0903) +-#define TCD0_CTRLE _SFR_MEM8(0x0904) +-#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +-#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +-#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +-#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +-#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +-#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +-#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +-#define TCD0_TEMP _SFR_MEM8(0x090F) +-#define TCD0_CNT _SFR_MEM16(0x0920) +-#define TCD0_PER _SFR_MEM16(0x0926) +-#define TCD0_CCA _SFR_MEM16(0x0928) +-#define TCD0_CCB _SFR_MEM16(0x092A) +-#define TCD0_CCC _SFR_MEM16(0x092C) +-#define TCD0_CCD _SFR_MEM16(0x092E) +-#define TCD0_PERBUF _SFR_MEM16(0x0936) +-#define TCD0_CCABUF _SFR_MEM16(0x0938) +-#define TCD0_CCBBUF _SFR_MEM16(0x093A) +-#define TCD0_CCCBUF _SFR_MEM16(0x093C) +-#define TCD0_CCDBUF _SFR_MEM16(0x093E) +- +-/* TCD1 - Timer/Counter D1 */ +-#define TCD1_CTRLA _SFR_MEM8(0x0940) +-#define TCD1_CTRLB _SFR_MEM8(0x0941) +-#define TCD1_CTRLC _SFR_MEM8(0x0942) +-#define TCD1_CTRLD _SFR_MEM8(0x0943) +-#define TCD1_CTRLE _SFR_MEM8(0x0944) +-#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +-#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +-#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +-#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +-#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +-#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +-#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +-#define TCD1_TEMP _SFR_MEM8(0x094F) +-#define TCD1_CNT _SFR_MEM16(0x0960) +-#define TCD1_PER _SFR_MEM16(0x0966) +-#define TCD1_CCA _SFR_MEM16(0x0968) +-#define TCD1_CCB _SFR_MEM16(0x096A) +-#define TCD1_PERBUF _SFR_MEM16(0x0976) +-#define TCD1_CCABUF _SFR_MEM16(0x0978) +-#define TCD1_CCBBUF _SFR_MEM16(0x097A) +- +-/* HIRESD - High-Resolution Extension D */ +-#define HIRESD_CTRLA _SFR_MEM8(0x0990) +- +-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +-#define USARTD0_DATA _SFR_MEM8(0x09A0) +-#define USARTD0_STATUS _SFR_MEM8(0x09A1) +-#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +-#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +-#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +-#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +-#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) +- +-/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ +-#define USARTD1_DATA _SFR_MEM8(0x09B0) +-#define USARTD1_STATUS _SFR_MEM8(0x09B1) +-#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +-#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +-#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +-#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +-#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) +- +-/* SPID - Serial Peripheral Interface D */ +-#define SPID_CTRL _SFR_MEM8(0x09C0) +-#define SPID_INTCTRL _SFR_MEM8(0x09C1) +-#define SPID_STATUS _SFR_MEM8(0x09C2) +-#define SPID_DATA _SFR_MEM8(0x09C3) +- +-/* TCE0 - Timer/Counter E0 */ +-#define TCE0_CTRLA _SFR_MEM8(0x0A00) +-#define TCE0_CTRLB _SFR_MEM8(0x0A01) +-#define TCE0_CTRLC _SFR_MEM8(0x0A02) +-#define TCE0_CTRLD _SFR_MEM8(0x0A03) +-#define TCE0_CTRLE _SFR_MEM8(0x0A04) +-#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +-#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +-#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +-#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +-#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +-#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +-#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +-#define TCE0_TEMP _SFR_MEM8(0x0A0F) +-#define TCE0_CNT _SFR_MEM16(0x0A20) +-#define TCE0_PER _SFR_MEM16(0x0A26) +-#define TCE0_CCA _SFR_MEM16(0x0A28) +-#define TCE0_CCB _SFR_MEM16(0x0A2A) +-#define TCE0_CCC _SFR_MEM16(0x0A2C) +-#define TCE0_CCD _SFR_MEM16(0x0A2E) +-#define TCE0_PERBUF _SFR_MEM16(0x0A36) +-#define TCE0_CCABUF _SFR_MEM16(0x0A38) +-#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +-#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +-#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) +- +-/* TCE1 - Timer/Counter E1 */ +-#define TCE1_CTRLA _SFR_MEM8(0x0A40) +-#define TCE1_CTRLB _SFR_MEM8(0x0A41) +-#define TCE1_CTRLC _SFR_MEM8(0x0A42) +-#define TCE1_CTRLD _SFR_MEM8(0x0A43) +-#define TCE1_CTRLE _SFR_MEM8(0x0A44) +-#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) +-#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) +-#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) +-#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) +-#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) +-#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) +-#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) +-#define TCE1_TEMP _SFR_MEM8(0x0A4F) +-#define TCE1_CNT _SFR_MEM16(0x0A60) +-#define TCE1_PER _SFR_MEM16(0x0A66) +-#define TCE1_CCA _SFR_MEM16(0x0A68) +-#define TCE1_CCB _SFR_MEM16(0x0A6A) +-#define TCE1_PERBUF _SFR_MEM16(0x0A76) +-#define TCE1_CCABUF _SFR_MEM16(0x0A78) +-#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) +- +-/* AWEXE - Advanced Waveform Extension E */ +-#define AWEXE_CTRL _SFR_MEM8(0x0A80) +-#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +-#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +-#define AWEXE_STATUS _SFR_MEM8(0x0A84) +-#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +-#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +-#define AWEXE_DTLS _SFR_MEM8(0x0A88) +-#define AWEXE_DTHS _SFR_MEM8(0x0A89) +-#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +-#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +-#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) +- +-/* HIRESE - High-Resolution Extension E */ +-#define HIRESE_CTRLA _SFR_MEM8(0x0A90) +- +-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +-#define USARTE0_DATA _SFR_MEM8(0x0AA0) +-#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +-#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +-#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +-#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +-#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +-#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) +- +-/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ +-#define USARTE1_DATA _SFR_MEM8(0x0AB0) +-#define USARTE1_STATUS _SFR_MEM8(0x0AB1) +-#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) +-#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) +-#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) +-#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) +-#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) +- +-/* SPIE - Serial Peripheral Interface E */ +-#define SPIE_CTRL _SFR_MEM8(0x0AC0) +-#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +-#define SPIE_STATUS _SFR_MEM8(0x0AC2) +-#define SPIE_DATA _SFR_MEM8(0x0AC3) +- +-/* TCF0 - Timer/Counter F0 */ +-#define TCF0_CTRLA _SFR_MEM8(0x0B00) +-#define TCF0_CTRLB _SFR_MEM8(0x0B01) +-#define TCF0_CTRLC _SFR_MEM8(0x0B02) +-#define TCF0_CTRLD _SFR_MEM8(0x0B03) +-#define TCF0_CTRLE _SFR_MEM8(0x0B04) +-#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +-#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +-#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +-#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +-#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +-#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +-#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +-#define TCF0_TEMP _SFR_MEM8(0x0B0F) +-#define TCF0_CNT _SFR_MEM16(0x0B20) +-#define TCF0_PER _SFR_MEM16(0x0B26) +-#define TCF0_CCA _SFR_MEM16(0x0B28) +-#define TCF0_CCB _SFR_MEM16(0x0B2A) +-#define TCF0_CCC _SFR_MEM16(0x0B2C) +-#define TCF0_CCD _SFR_MEM16(0x0B2E) +-#define TCF0_PERBUF _SFR_MEM16(0x0B36) +-#define TCF0_CCABUF _SFR_MEM16(0x0B38) +-#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +-#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +-#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) +- +-/* TCF1 - Timer/Counter F1 */ +-#define TCF1_CTRLA _SFR_MEM8(0x0B40) +-#define TCF1_CTRLB _SFR_MEM8(0x0B41) +-#define TCF1_CTRLC _SFR_MEM8(0x0B42) +-#define TCF1_CTRLD _SFR_MEM8(0x0B43) +-#define TCF1_CTRLE _SFR_MEM8(0x0B44) +-#define TCF1_INTCTRLA _SFR_MEM8(0x0B46) +-#define TCF1_INTCTRLB _SFR_MEM8(0x0B47) +-#define TCF1_CTRLFCLR _SFR_MEM8(0x0B48) +-#define TCF1_CTRLFSET _SFR_MEM8(0x0B49) +-#define TCF1_CTRLGCLR _SFR_MEM8(0x0B4A) +-#define TCF1_CTRLGSET _SFR_MEM8(0x0B4B) +-#define TCF1_INTFLAGS _SFR_MEM8(0x0B4C) +-#define TCF1_TEMP _SFR_MEM8(0x0B4F) +-#define TCF1_CNT _SFR_MEM16(0x0B60) +-#define TCF1_PER _SFR_MEM16(0x0B66) +-#define TCF1_CCA _SFR_MEM16(0x0B68) +-#define TCF1_CCB _SFR_MEM16(0x0B6A) +-#define TCF1_PERBUF _SFR_MEM16(0x0B76) +-#define TCF1_CCABUF _SFR_MEM16(0x0B78) +-#define TCF1_CCBBUF _SFR_MEM16(0x0B7A) +- +-/* HIRESF - High-Resolution Extension F */ +-#define HIRESF_CTRLA _SFR_MEM8(0x0B90) +- +-/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ +-#define USARTF0_DATA _SFR_MEM8(0x0BA0) +-#define USARTF0_STATUS _SFR_MEM8(0x0BA1) +-#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) +-#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) +-#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) +-#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) +-#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) +- +-/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ +-#define USARTF1_DATA _SFR_MEM8(0x0BB0) +-#define USARTF1_STATUS _SFR_MEM8(0x0BB1) +-#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) +-#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) +-#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) +-#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) +-#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) +- +-/* SPIF - Serial Peripheral Interface F */ +-#define SPIF_CTRL _SFR_MEM8(0x0BC0) +-#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) +-#define SPIF_STATUS _SFR_MEM8(0x0BC2) +-#define SPIF_DATA _SFR_MEM8(0x0BC3) +- +- +- +-/*================== Bitfield Definitions ================== */ +- +-/* XOCD - On-Chip Debug System */ +-/* OCD.OCDR1 bit masks and bit positions */ +-#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +-#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ +- +- +-/* CPU - CPU */ +-/* CPU.CCP bit masks and bit positions */ +-#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +-#define CPU_CCP_gp 0 /* CCP signature group position. */ +-#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +-#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +-#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +-#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +-#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +-#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +-#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +-#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +-#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +-#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +-#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +-#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +-#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +-#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +-#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +-#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ +- +- +-/* CPU.SREG bit masks and bit positions */ +-#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +-#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ +- +-#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +-#define CPU_T_bp 6 /* Transfer Bit bit position. */ +- +-#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +-#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +- +-#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +-#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +- +-#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +-#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +- +-#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +-#define CPU_N_bp 2 /* Negative Flag bit position. */ +- +-#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +-#define CPU_Z_bp 1 /* Zero Flag bit position. */ +- +-#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +-#define CPU_C_bp 0 /* Carry Flag bit position. */ +- +- +-/* CLK - Clock System */ +-/* CLK.CTRL bit masks and bit positions */ +-#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +-#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +-#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +-#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +-#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +-#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +-#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +-#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ +- +- +-/* CLK.PSCTRL bit masks and bit positions */ +-#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +-#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +-#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +-#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +-#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +-#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +-#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +-#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +-#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +-#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +-#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +-#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ +- +-#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +-#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +-#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +-#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +-#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +-#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ +- +- +-/* CLK.LOCK bit masks and bit positions */ +-#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +-#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ +- +- +-/* CLK.RTCCTRL bit masks and bit positions */ +-#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +-#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +-#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +-#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +-#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +-#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +-#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +-#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ +- +-#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +-#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ +- +- +-/* PR.PRGEN bit masks and bit positions */ +-#define PR_AES_bm 0x10 /* AES bit mask. */ +-#define PR_AES_bp 4 /* AES bit position. */ +- +-#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +-#define PR_EBI_bp 3 /* External Bus Interface bit position. */ +- +-#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +-#define PR_RTC_bp 2 /* Real-time Counter bit position. */ +- +-#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +-#define PR_EVSYS_bp 1 /* Event System bit position. */ +- +-#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +-#define PR_DMA_bp 0 /* DMA-Controller bit position. */ +- +- +-/* PR.PRPA bit masks and bit positions */ +-#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +-#define PR_DAC_bp 2 /* Port A DAC bit position. */ +- +-#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +-#define PR_ADC_bp 1 /* Port A ADC bit position. */ +- +-#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +-#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ +- +- +-/* PR.PRPB bit masks and bit positions */ +-/* PR_DAC_bm Predefined. */ +-/* PR_DAC_bp Predefined. */ +- +-/* PR_ADC_bm Predefined. */ +-/* PR_ADC_bp Predefined. */ +- +-/* PR_AC_bm Predefined. */ +-/* PR_AC_bp Predefined. */ +- +- +-/* PR.PRPC bit masks and bit positions */ +-#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +-#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ +- +-#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +-#define PR_USART1_bp 5 /* Port C USART1 bit position. */ +- +-#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +-#define PR_USART0_bp 4 /* Port C USART0 bit position. */ +- +-#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +-#define PR_SPI_bp 3 /* Port C SPI bit position. */ +- +-#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +-#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ +- +-#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +-#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ +- +-#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +-#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ +- +- +-/* PR.PRPD bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* PR.PRPE bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* PR.PRPF bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* SLEEP - Sleep Controller */ +-/* SLEEP.CTRL bit masks and bit positions */ +-#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +-#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +-#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +-#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +-#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +-#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +-#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +-#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ +- +-#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +-#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ +- +- +-/* OSC - Oscillator */ +-/* OSC.CTRL bit masks and bit positions */ +-#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +-#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ +- +-#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +-#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ +- +-#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ +- +- +-/* OSC.STATUS bit masks and bit positions */ +-#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +-#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ +- +-#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +-#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ +- +-#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ +- +- +-/* OSC.XOSCCTRL bit masks and bit positions */ +-#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +-#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +-#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +-#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +-#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +-#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ +- +-#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +-#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ +- +-#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +-#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +-#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +-#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +-#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +-#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +-#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +-#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +-#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +-#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +- +- +-/* OSC.XOSCFAIL bit masks and bit positions */ +-#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +-#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ +- +-#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +-#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ +- +- +-/* OSC.PLLCTRL bit masks and bit positions */ +-#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +-#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +-#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +-#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +-#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +-#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ +- +-#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +-#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +-#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +-#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +-#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +-#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +-#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +-#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +-#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +-#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +-#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +-#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ +- +- +-/* OSC.DFLLCTRL bit masks and bit positions */ +-#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +-#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ +- +-#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +-#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ +- +- +-/* DFLL - DFLL */ +-/* DFLL.CTRL bit masks and bit positions */ +-#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +-#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ +- +- +-/* DFLL.CALA bit masks and bit positions */ +-#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +-#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +-#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +-#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +-#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +-#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +-#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +-#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +-#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +-#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +-#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +-#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +-#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +-#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +-#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +-#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ +- +- +-/* DFLL.CALB bit masks and bit positions */ +-#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +-#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +-#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +-#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +-#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +-#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +-#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +-#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +-#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +-#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +-#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +-#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +-#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +-#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ +- +- +-/* RST - Reset */ +-/* RST.STATUS bit masks and bit positions */ +-#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +-#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ +- +-#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +-#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ +- +-#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +-#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ +- +-#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +-#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ +- +-#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +-#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ +- +-#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +-#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ +- +-#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +-#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ +- +- +-/* RST.CTRL bit masks and bit positions */ +-#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +-#define RST_SWRST_bp 0 /* Software Reset bit position. */ +- +- +-/* WDT - Watch-Dog Timer */ +-/* WDT.CTRL bit masks and bit positions */ +-#define WDT_PER_gm 0x3C /* Period group mask. */ +-#define WDT_PER_gp 2 /* Period group position. */ +-#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +-#define WDT_PER0_bp 2 /* Period bit 0 position. */ +-#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +-#define WDT_PER1_bp 3 /* Period bit 1 position. */ +-#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +-#define WDT_PER2_bp 4 /* Period bit 2 position. */ +-#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +-#define WDT_PER3_bp 5 /* Period bit 3 position. */ +- +-#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +-#define WDT_ENABLE_bp 1 /* Enable bit position. */ +- +-#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +-#define WDT_CEN_bp 0 /* Change Enable bit position. */ +- +- +-/* WDT.WINCTRL bit masks and bit positions */ +-#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +-#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +-#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +-#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +-#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +-#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +-#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +-#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +-#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +-#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ +- +-#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +-#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ +- +-#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +-#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ +- +- +-/* WDT.STATUS bit masks and bit positions */ +-#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +-#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +- +- +-/* MCU - MCU Control */ +-/* MCU.MCUCR bit masks and bit positions */ +-#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +-#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ +- +- +-/* MCU.EVSYSLOCK bit masks and bit positions */ +-#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +-#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ +- +-#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +-#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ +- +- +-/* MCU.AWEXLOCK bit masks and bit positions */ +-#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +-#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ +- +-#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +-#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ +- +- +-/* PMIC - Programmable Multi-level Interrupt Controller */ +-/* PMIC.STATUS bit masks and bit positions */ +-#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +-#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ +- +-#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +-#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ +- +-#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +-#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ +- +-#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +-#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ +- +- +-/* PMIC.CTRL bit masks and bit positions */ +-#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +-#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ +- +-#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +-#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ +- +-#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +-#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ +- +-#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +-#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ +- +-#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +-#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ +- +- +-/* DMA - DMA Controller */ +-/* DMA_CH.CTRLA bit masks and bit positions */ +-#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +-#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ +- +-#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +-#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ +- +-#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +-#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ +- +-#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +-#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ +- +-#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +-#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ +- +-#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +-#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +-#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +-#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +-#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +-#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ +- +- +-/* DMA_CH.CTRLB bit masks and bit positions */ +-#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +-#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ +- +-#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +-#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ +- +-#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +-#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ +- +-#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +-#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +-#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +-#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +-#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +-#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ +- +-#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +-#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +-#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +-#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +-#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +-#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ +- +- +-/* DMA_CH.ADDRCTRL bit masks and bit positions */ +-#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +-#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +-#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +-#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +-#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +-#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ +- +-#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +-#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +-#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +-#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +-#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +-#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ +- +-#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +-#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +-#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +-#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +-#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +-#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ +- +-#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +-#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +-#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +-#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +-#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +-#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ +- +- +-/* DMA_CH.TRIGSRC bit masks and bit positions */ +-#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +-#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +-#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +-#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +-#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +-#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +-#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +-#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +-#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +-#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +-#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +-#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +-#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +-#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +-#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +-#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +-#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +-#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ +- +- +-/* DMA.CTRL bit masks and bit positions */ +-#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +-#define DMA_ENABLE_bp 7 /* Enable bit position. */ +- +-#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +-#define DMA_RESET_bp 6 /* Software Reset bit position. */ +- +-#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +-#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +-#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +-#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +-#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +-#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ +- +-#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +-#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +-#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +-#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +-#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +-#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ +- +- +-/* DMA.INTFLAGS bit masks and bit positions */ +-#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ +- +- +-/* DMA.STATUS bit masks and bit positions */ +-#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +-#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ +- +-#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +-#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ +- +-#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +-#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ +- +-#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +-#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ +- +-#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +-#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ +- +-#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +-#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ +- +-#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +-#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ +- +-#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +-#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ +- +- +-/* EVSYS - Event System */ +-/* EVSYS.CH0MUX bit masks and bit positions */ +-#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +-#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +-#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +-#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +-#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +-#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +-#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +-#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +-#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +-#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +-#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +-#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +-#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +-#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +-#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +-#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +-#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +-#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ +- +- +-/* EVSYS.CH1MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH2MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH3MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH4MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH5MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH6MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH7MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH0CTRL bit masks and bit positions */ +-#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +-#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +-#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +-#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +-#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +-#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ +- +-#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +-#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ +- +-#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +-#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ +- +-#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +-#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +-#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +-#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +-#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +-#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +-#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +-#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ +- +- +-/* EVSYS.CH1CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH2CTRL bit masks and bit positions */ +-/* EVSYS_QDIRM_gm Predefined. */ +-/* EVSYS_QDIRM_gp Predefined. */ +-/* EVSYS_QDIRM0_bm Predefined. */ +-/* EVSYS_QDIRM0_bp Predefined. */ +-/* EVSYS_QDIRM1_bm Predefined. */ +-/* EVSYS_QDIRM1_bp Predefined. */ +- +-/* EVSYS_QDIEN_bm Predefined. */ +-/* EVSYS_QDIEN_bp Predefined. */ +- +-/* EVSYS_QDEN_bm Predefined. */ +-/* EVSYS_QDEN_bp Predefined. */ +- +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH3CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH4CTRL bit masks and bit positions */ +-/* EVSYS_QDIRM_gm Predefined. */ +-/* EVSYS_QDIRM_gp Predefined. */ +-/* EVSYS_QDIRM0_bm Predefined. */ +-/* EVSYS_QDIRM0_bp Predefined. */ +-/* EVSYS_QDIRM1_bm Predefined. */ +-/* EVSYS_QDIRM1_bp Predefined. */ +- +-/* EVSYS_QDIEN_bm Predefined. */ +-/* EVSYS_QDIEN_bp Predefined. */ +- +-/* EVSYS_QDEN_bm Predefined. */ +-/* EVSYS_QDEN_bp Predefined. */ +- +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH5CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH6CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH7CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* NVM - Non Volatile Memory Controller */ +-/* NVM.CMD bit masks and bit positions */ +-#define NVM_CMD_gm 0xFF /* Command group mask. */ +-#define NVM_CMD_gp 0 /* Command group position. */ +-#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +-#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +-#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +-#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +-#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +-#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +-#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +-#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +-#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +-#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +-#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +-#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +-#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +-#define NVM_CMD7_bp 7 /* Command bit 7 position. */ +- +- +-/* NVM.CTRLA bit masks and bit positions */ +-#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +-#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ +- +- +-/* NVM.CTRLB bit masks and bit positions */ +-#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +-#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ +- +-#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +-#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ +- +-#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +-#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ +- +-#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +-#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ +- +- +-/* NVM.INTCTRL bit masks and bit positions */ +-#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +-#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +-#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +-#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +-#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +-#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ +- +-#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +-#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +-#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +-#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +-#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +-#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ +- +- +-/* NVM.STATUS bit masks and bit positions */ +-#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +-#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ +- +-#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +-#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ +- +-#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +-#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ +- +-#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +-#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ +- +- +-/* NVM.LOCKBITS bit masks and bit positions */ +-#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +-#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +-#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ +-#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ +-#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ +-#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ +-#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ +-#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ +-#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ +-#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ +-#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ +-#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ +-#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ +-#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ +-#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ +-#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ +-#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ +-#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ +-#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ +-#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +-#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +-#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +-#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ +- +-#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +-#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +-#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +-#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +-#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ +- +-#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +-#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ +- +-#define NVM_FUSES_BODACT_gm 0x0C /* BOD Operation in Active Mode group mask. */ +-#define NVM_FUSES_BODACT_gp 2 /* BOD Operation in Active Mode group position. */ +-#define NVM_FUSES_BODACT0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +-#define NVM_FUSES_BODACT0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +-#define NVM_FUSES_BODACT1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +-#define NVM_FUSES_BODACT1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +- +-#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +-#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +-#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +-#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +-#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +-#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +-#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +-#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +-#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +-#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +-#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +-#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ +- +-#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +-#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ +- +-#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ +-#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ +- +- +-/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +-#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +-#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ +- +-#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +-#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +-#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +-#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +-#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +-#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +-#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +-#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +- +- +-/* AC - Analog Comparator */ +-/* AC.AC0CTRL bit masks and bit positions */ +-#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +-#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +-#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +-#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +-#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +-#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ +- +-#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +-#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +-#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +-#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +-#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +-#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ +- +-#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +-#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ +- +-#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +-#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +-#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +-#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +-#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +-#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +- +-#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define AC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* AC.AC1CTRL bit masks and bit positions */ +-/* AC_INTMODE_gm Predefined. */ +-/* AC_INTMODE_gp Predefined. */ +-/* AC_INTMODE0_bm Predefined. */ +-/* AC_INTMODE0_bp Predefined. */ +-/* AC_INTMODE1_bm Predefined. */ +-/* AC_INTMODE1_bp Predefined. */ +- +-/* AC_INTLVL_gm Predefined. */ +-/* AC_INTLVL_gp Predefined. */ +-/* AC_INTLVL0_bm Predefined. */ +-/* AC_INTLVL0_bp Predefined. */ +-/* AC_INTLVL1_bm Predefined. */ +-/* AC_INTLVL1_bp Predefined. */ +- +-/* AC_HSMODE_bm Predefined. */ +-/* AC_HSMODE_bp Predefined. */ +- +-/* AC_HYSMODE_gm Predefined. */ +-/* AC_HYSMODE_gp Predefined. */ +-/* AC_HYSMODE0_bm Predefined. */ +-/* AC_HYSMODE0_bp Predefined. */ +-/* AC_HYSMODE1_bm Predefined. */ +-/* AC_HYSMODE1_bp Predefined. */ +- +-/* AC_ENABLE_bm Predefined. */ +-/* AC_ENABLE_bp Predefined. */ +- +- +-/* AC.AC0MUXCTRL bit masks and bit positions */ +-#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +-#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +-#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +-#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +-#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +-#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +-#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +-#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ +- +-#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +-#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +-#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +-#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +-#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +-#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +-#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +-#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ +- +- +-/* AC.AC1MUXCTRL bit masks and bit positions */ +-/* AC_MUXPOS_gm Predefined. */ +-/* AC_MUXPOS_gp Predefined. */ +-/* AC_MUXPOS0_bm Predefined. */ +-/* AC_MUXPOS0_bp Predefined. */ +-/* AC_MUXPOS1_bm Predefined. */ +-/* AC_MUXPOS1_bp Predefined. */ +-/* AC_MUXPOS2_bm Predefined. */ +-/* AC_MUXPOS2_bp Predefined. */ +- +-/* AC_MUXNEG_gm Predefined. */ +-/* AC_MUXNEG_gp Predefined. */ +-/* AC_MUXNEG0_bm Predefined. */ +-/* AC_MUXNEG0_bp Predefined. */ +-/* AC_MUXNEG1_bm Predefined. */ +-/* AC_MUXNEG1_bp Predefined. */ +-/* AC_MUXNEG2_bm Predefined. */ +-/* AC_MUXNEG2_bp Predefined. */ +- +- +-/* AC.CTRLA bit masks and bit positions */ +-#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +-#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ +- +- +-/* AC.CTRLB bit masks and bit positions */ +-#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +-#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +-#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +-#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +-#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +-#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +-#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +-#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +-#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +-#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +-#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +-#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +-#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +-#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ +- +- +-/* AC.WINCTRL bit masks and bit positions */ +-#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +-#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ +- +-#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +-#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +-#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +-#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +-#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +-#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ +- +-#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +-#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +-#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +-#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +-#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +-#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ +- +- +-/* AC.STATUS bit masks and bit positions */ +-#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +-#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +-#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +-#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +-#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +-#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ +- +-#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +-#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ +- +-#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +-#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ +- +-#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +-#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ +- +-#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +-#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ +- +-#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +-#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ +- +- +-/* ADC - Analog/Digital Converter */ +-/* ADC_CH.CTRL bit masks and bit positions */ +-#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +-#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ +- +-#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +-#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +-#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +-#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +-#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +-#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +-#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +-#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ +- +-#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +-#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +-#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +-#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +-#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +-#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ +- +- +-/* ADC_CH.MUXCTRL bit masks and bit positions */ +-#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +-#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +-#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +-#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +-#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +-#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +-#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +-#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +-#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +-#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ +- +-#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +-#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +-#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +-#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +-#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +-#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +-#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +-#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +-#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +-#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ +- +-#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +-#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +-#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +-#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +-#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +-#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ +- +- +-/* ADC_CH.INTCTRL bit masks and bit positions */ +-#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +-#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +-#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +-#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +-#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +-#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ +- +-#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +-#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +-#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +-#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +-#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +-#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ +- +- +-/* ADC_CH.INTFLAGS bit masks and bit positions */ +-#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +-#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ +- +- +-/* ADC.CTRLA bit masks and bit positions */ +-#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +-#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +-#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +-#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +-#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +-#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ +- +-#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +-#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ +- +-#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +-#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ +- +-#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +-#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ +- +-#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +-#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ +- +-#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +-#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ +- +-#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +-#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ +- +- +-/* ADC.CTRLB bit masks and bit positions */ +-#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +-#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ +- +-#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +-#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ +- +-#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +-#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +-#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +-#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +-#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +-#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ +- +- +-/* ADC.REFCTRL bit masks and bit positions */ +-#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +-#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +-#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +-#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +-#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +-#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +- +-#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +-#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ +- +-#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +-#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ +- +- +-/* ADC.EVCTRL bit masks and bit positions */ +-#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +-#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +-#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +-#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +-#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +-#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ +- +-#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +-#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +-#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +-#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +-#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +-#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +-#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +-#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ +- +-#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +-#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +-#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +-#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +-#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +-#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +-#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +-#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ +- +- +-/* ADC.PRESCALER bit masks and bit positions */ +-#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +-#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +-#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +-#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +-#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +-#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +-#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +-#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ +- +- +-/* ADC.INTFLAGS bit masks and bit positions */ +-#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +-#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ +- +-#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +-#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ +- +-#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +-#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ +- +-#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +-#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ +- +- +-/* DAC - Digital/Analog Converter */ +-/* DAC.CTRLA bit masks and bit positions */ +-#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +-#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ +- +-#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +-#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ +- +-#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +-#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ +- +-#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +-#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ +- +-#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define DAC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* DAC.CTRLB bit masks and bit positions */ +-#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +-#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +-#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +-#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +-#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +-#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ +- +-#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +-#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ +- +-#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +-#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ +- +- +-/* DAC.CTRLC bit masks and bit positions */ +-#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +-#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +-#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +-#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +-#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +-#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ +- +-#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +-#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ +- +- +-/* DAC.EVCTRL bit masks and bit positions */ +-#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +-#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +-#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +-#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +-#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +-#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +-#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +-#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ +- +- +-/* DAC.TIMCTRL bit masks and bit positions */ +-#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ +-#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ +-#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ +-#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ +-#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ +-#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ +-#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ +-#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ +- +-#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ +-#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ +-#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ +-#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ +-#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ +-#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ +-#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ +-#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ +-#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ +-#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ +- +- +-/* DAC.STATUS bit masks and bit positions */ +-#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +-#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ +- +-#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +-#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ +- +- +-/* RTC - Real-Time Clounter */ +-/* RTC.CTRL bit masks and bit positions */ +-#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +-#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +-#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +-#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +-#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +-#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +-#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +-#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ +- +- +-/* RTC.STATUS bit masks and bit positions */ +-#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +-#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ +- +- +-/* RTC.INTCTRL bit masks and bit positions */ +-#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +-#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +-#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +-#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +-#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +-#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ +- +-#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +-#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +-#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +-#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +-#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +-#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ +- +- +-/* RTC.INTFLAGS bit masks and bit positions */ +-#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +-#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ +- +-#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* EBI - External Bus Interface */ +-/* EBI_CS.CTRLA bit masks and bit positions */ +-#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +-#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +-#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +-#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +-#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +-#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +-#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +-#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +-#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +-#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +-#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +-#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ +- +-#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +-#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +-#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +-#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +-#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +-#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ +- +- +-/* EBI_CS.CTRLB bit masks and bit positions */ +-#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +-#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +-#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +-#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +-#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +-#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +-#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +-#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ +- +-#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +-#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ +- +-#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +-#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ +- +-#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +-#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +-#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +-#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +-#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +-#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ +- +- +-/* EBI.CTRL bit masks and bit positions */ +-#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +-#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +-#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +-#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +-#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +-#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ +- +-#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +-#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +-#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +-#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +-#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +-#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ +- +-#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +-#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +-#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +-#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +-#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +-#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ +- +-#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +-#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +-#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +-#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +-#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +-#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLA bit masks and bit positions */ +-#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +-#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ +- +-#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +-#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ +- +-#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +-#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +-#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +-#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +-#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +-#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLB bit masks and bit positions */ +-#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +-#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +-#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +-#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +-#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +-#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ +- +-#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +-#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +-#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +-#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +-#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +-#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +-#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +-#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ +- +-#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +-#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +-#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +-#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +-#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +-#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +-#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +-#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ +- +- +-/* EBI.SDRAMCTRLC bit masks and bit positions */ +-#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +-#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +-#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +-#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +-#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +-#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ +- +-#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +-#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +-#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +-#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +-#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +-#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +-#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +-#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ +- +-#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +-#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +-#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +-#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +-#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +-#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +-#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +-#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ +- +- +-/* TWI - Two-Wire Interface */ +-/* TWI_MASTER.CTRLA bit masks and bit positions */ +-#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +-#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ +- +-#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +-#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ +- +-#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +-#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ +- +- +-/* TWI_MASTER.CTRLB bit masks and bit positions */ +-#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +-#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +-#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +-#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +-#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +-#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +- +-#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +-#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ +- +-#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_MASTER.CTRLC bit masks and bit positions */ +-#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +-#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_MASTER.STATUS bit masks and bit positions */ +-#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +-#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ +- +-#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +-#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ +- +-#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +-#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +- +-#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +-#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +-#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +-#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +-#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +-#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +- +- +-/* TWI_SLAVE.CTRLA bit masks and bit positions */ +-#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +-#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +-#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ +- +-#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +-#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ +- +-#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_SLAVE.CTRLB bit masks and bit positions */ +-#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +-#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_SLAVE.STATUS bit masks and bit positions */ +-#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +-#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +-#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +-#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ +- +-#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +-#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ +- +-#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +-#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ +- +- +-/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +-#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +-#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +-#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +-#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +-#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +-#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +-#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +-#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +-#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +-#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +-#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +-#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +-#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +-#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +-#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +-#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ +- +-#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +-#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ +- +- +-/* TWI.CTRL bit masks and bit positions */ +-#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +-#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ +- +-#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +-#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ +- +- +-/* PORT - Port Configuration */ +-/* PORTCFG.VPCTRLA bit masks and bit positions */ +-#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +-#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +-#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +-#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +-#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +-#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +-#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +-#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +-#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +-#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ +- +-#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +-#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +-#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +-#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +-#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +-#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +-#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +-#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +-#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +-#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ +- +- +-/* PORTCFG.VPCTRLB bit masks and bit positions */ +-#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +-#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +-#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +-#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +-#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +-#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +-#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +-#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +-#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +-#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ +- +-#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +-#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +-#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +-#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +-#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +-#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +-#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +-#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +-#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +-#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ +- +- +-/* PORTCFG.CLKEVOUT bit masks and bit positions */ +-#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +-#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +-#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +-#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +-#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +-#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ +- +-#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +-#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +-#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +-#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +-#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +-#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ +- +- +-/* VPORT.INTFLAGS bit masks and bit positions */ +-#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.INTCTRL bit masks and bit positions */ +-#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +-#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +-#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +-#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +-#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +-#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ +- +-#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +-#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +-#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +-#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +-#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +-#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ +- +- +-/* PORT.INTFLAGS bit masks and bit positions */ +-#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.PIN0CTRL bit masks and bit positions */ +-#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +-#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ +- +-#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +-#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ +- +-#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +-#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +-#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +-#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +-#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +-#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +-#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +-#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ +- +-#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +-#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +-#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +-#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +-#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +-#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +-#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +-#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +- +- +-/* PORT.PIN1CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN2CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN3CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN4CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN5CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN6CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN7CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* TC - 16-bit Timer/Counter With PWM */ +-/* TC0.CTRLA bit masks and bit positions */ +-#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC0.CTRLB bit masks and bit positions */ +-#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +-#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ +- +-#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +-#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ +- +-#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC0.CTRLC bit masks and bit positions */ +-#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +-#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ +- +-#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +-#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ +- +-#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC0.CTRLD bit masks and bit positions */ +-#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC0_EVACT_gp 5 /* Event Action group position. */ +-#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC0.CTRLE bit masks and bit positions */ +-#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +-#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ +- +-#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC0.INTCTRLA bit masks and bit positions */ +-#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC0.INTCTRLB bit masks and bit positions */ +-#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +-#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +-#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +-#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +-#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +-#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ +- +-#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +-#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +-#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +-#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +-#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +-#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ +- +-#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC0.CTRLFCLR bit masks and bit positions */ +-#define TC0_CMD_gm 0x0C /* Command group mask. */ +-#define TC0_CMD_gp 2 /* Command group position. */ +-#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC0_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC0_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC0_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC0.CTRLFSET bit masks and bit positions */ +-/* TC0_CMD_gm Predefined. */ +-/* TC0_CMD_gp Predefined. */ +-/* TC0_CMD0_bm Predefined. */ +-/* TC0_CMD0_bp Predefined. */ +-/* TC0_CMD1_bm Predefined. */ +-/* TC0_CMD1_bp Predefined. */ +- +-/* TC0_LUPD_bm Predefined. */ +-/* TC0_LUPD_bp Predefined. */ +- +-/* TC0_DIR_bm Predefined. */ +-/* TC0_DIR_bp Predefined. */ +- +- +-/* TC0.CTRLGCLR bit masks and bit positions */ +-#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +-#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ +- +-#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +-#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ +- +-#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC0.CTRLGSET bit masks and bit positions */ +-/* TC0_CCDBV_bm Predefined. */ +-/* TC0_CCDBV_bp Predefined. */ +- +-/* TC0_CCCBV_bm Predefined. */ +-/* TC0_CCCBV_bp Predefined. */ +- +-/* TC0_CCBBV_bm Predefined. */ +-/* TC0_CCBBV_bp Predefined. */ +- +-/* TC0_CCABV_bm Predefined. */ +-/* TC0_CCABV_bp Predefined. */ +- +-/* TC0_PERBV_bm Predefined. */ +-/* TC0_PERBV_bp Predefined. */ +- +- +-/* TC0.INTFLAGS bit masks and bit positions */ +-#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +-#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ +- +-#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +-#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ +- +-#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* TC1.CTRLA bit masks and bit positions */ +-#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC1.CTRLB bit masks and bit positions */ +-#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC1.CTRLC bit masks and bit positions */ +-#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC1.CTRLD bit masks and bit positions */ +-#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC1_EVACT_gp 5 /* Event Action group position. */ +-#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC1.CTRLE bit masks and bit positions */ +-#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +-#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ +- +-#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC1.INTCTRLA bit masks and bit positions */ +-#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC1.INTCTRLB bit masks and bit positions */ +-#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC1.CTRLFCLR bit masks and bit positions */ +-#define TC1_CMD_gm 0x0C /* Command group mask. */ +-#define TC1_CMD_gp 2 /* Command group position. */ +-#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC1_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC1_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC1_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC1.CTRLFSET bit masks and bit positions */ +-/* TC1_CMD_gm Predefined. */ +-/* TC1_CMD_gp Predefined. */ +-/* TC1_CMD0_bm Predefined. */ +-/* TC1_CMD0_bp Predefined. */ +-/* TC1_CMD1_bm Predefined. */ +-/* TC1_CMD1_bp Predefined. */ +- +-/* TC1_LUPD_bm Predefined. */ +-/* TC1_LUPD_bp Predefined. */ +- +-/* TC1_DIR_bm Predefined. */ +-/* TC1_DIR_bp Predefined. */ +- +- +-/* TC1.CTRLGCLR bit masks and bit positions */ +-#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC1.CTRLGSET bit masks and bit positions */ +-/* TC1_CCBBV_bm Predefined. */ +-/* TC1_CCBBV_bp Predefined. */ +- +-/* TC1_CCABV_bm Predefined. */ +-/* TC1_CCABV_bp Predefined. */ +- +-/* TC1_PERBV_bm Predefined. */ +-/* TC1_PERBV_bp Predefined. */ +- +- +-/* TC1.INTFLAGS bit masks and bit positions */ +-#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* AWEX.CTRL bit masks and bit positions */ +-#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +-#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ +- +-#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +-#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ +- +-#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +-#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ +- +-#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +-#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ +- +-#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +-#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ +- +-#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +-#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ +- +- +-/* AWEX.FDCTRL bit masks and bit positions */ +-#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +-#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ +- +-#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +-#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ +- +-#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +-#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +-#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +-#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +-#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +-#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ +- +- +-/* AWEX.STATUS bit masks and bit positions */ +-#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +-#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ +- +-#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +-#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ +- +-#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +-#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ +- +- +-/* HIRES.CTRLA bit masks and bit positions */ +-#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +-#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +-#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +-#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +-#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +-#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ +- +- +-/* USART - Universal Asynchronous Receiver-Transmitter */ +-/* USART.STATUS bit masks and bit positions */ +-#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +-#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ +- +-#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +-#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +- +-#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +-#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +- +-#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +-#define USART_FERR_bp 4 /* Frame Error bit position. */ +- +-#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +-#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ +- +-#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +-#define USART_PERR_bp 2 /* Parity Error bit position. */ +- +-#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +-#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ +- +- +-/* USART.CTRLA bit masks and bit positions */ +-#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +-#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +-#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +-#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +-#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +-#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ +- +-#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +-#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +-#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +-#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +-#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +-#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ +- +-#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +-#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +-#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +-#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +-#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +-#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ +- +- +-/* USART.CTRLB bit masks and bit positions */ +-#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +-#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ +- +-#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +-#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ +- +-#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +-#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ +- +-#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +-#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ +- +-#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +-#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ +- +- +-/* USART.CTRLC bit masks and bit positions */ +-#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +-#define USART_CMODE_gp 6 /* Communication Mode group position. */ +-#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +-#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +-#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +-#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ +- +-#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +-#define USART_PMODE_gp 4 /* Parity Mode group position. */ +-#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +-#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +-#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +-#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +- +-#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +-#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +- +-#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +-#define USART_CHSIZE_gp 0 /* Character Size group position. */ +-#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +-#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +-#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +-#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +-#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +-#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +- +- +-/* USART.BAUDCTRLA bit masks and bit positions */ +-#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +-#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +-#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +-#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +-#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +-#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +-#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +-#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +-#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +-#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +-#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +-#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +-#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +-#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +-#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +-#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +-#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +-#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ +- +- +-/* USART.BAUDCTRLB bit masks and bit positions */ +-#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +-#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +-#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +-#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +-#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +-#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +-#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +-#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +-#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +-#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ +- +-/* USART_BSEL_gm Predefined. */ +-/* USART_BSEL_gp Predefined. */ +-/* USART_BSEL0_bm Predefined. */ +-/* USART_BSEL0_bp Predefined. */ +-/* USART_BSEL1_bm Predefined. */ +-/* USART_BSEL1_bp Predefined. */ +-/* USART_BSEL2_bm Predefined. */ +-/* USART_BSEL2_bp Predefined. */ +-/* USART_BSEL3_bm Predefined. */ +-/* USART_BSEL3_bp Predefined. */ +- +- +-/* SPI - Serial Peripheral Interface */ +-/* SPI.CTRL bit masks and bit positions */ +-#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +-#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ +- +-#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +-#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ +- +-#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +-#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ +- +-#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +-#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ +- +-#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +-#define SPI_MODE_gp 2 /* SPI Mode group position. */ +-#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +-#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +-#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +-#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ +- +-#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +-#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +-#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +-#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +-#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +-#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ +- +- +-/* SPI.INTCTRL bit masks and bit positions */ +-#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +-#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +-/* SPI.STATUS bit masks and bit positions */ +-#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +-#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ +- +-#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +-#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +- +- +-/* IRCOM - IR Communication Module */ +-/* IRCOM.CTRL bit masks and bit positions */ +-#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +-#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +-#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +-#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +-#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +-#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +-#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +-#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +-#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +-#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ +- +- +-/* AES - AES Module */ +-/* AES.CTRL bit masks and bit positions */ +-#define AES_START_bm 0x80 /* Start/Run bit mask. */ +-#define AES_START_bp 7 /* Start/Run bit position. */ +- +-#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +-#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ +- +-#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +-#define AES_RESET_bp 5 /* AES Software Reset bit position. */ +- +-#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +-#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ +- +-#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +-#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ +- +- +-/* AES.STATUS bit masks and bit positions */ +-#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +-#define AES_ERROR_bp 7 /* AES Error bit position. */ +- +-#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +-#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ +- +- +-/* AES.INTCTRL bit masks and bit positions */ +-#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +-#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +- +-// Generic Port Pins +- +-#define PIN0_bm 0x01 +-#define PIN0_bp 0 +-#define PIN1_bm 0x02 +-#define PIN1_bp 1 +-#define PIN2_bm 0x04 +-#define PIN2_bp 2 +-#define PIN3_bm 0x08 +-#define PIN3_bp 3 +-#define PIN4_bm 0x10 +-#define PIN4_bp 4 +-#define PIN5_bm 0x20 +-#define PIN5_bp 5 +-#define PIN6_bm 0x40 +-#define PIN6_bp 6 +-#define PIN7_bm 0x80 +-#define PIN7_bp 7 +- +- +-/* ========== Interrupt Vector Definitions ========== */ +-/* Vector 0 is the reset vector */ +- +-/* OSC interrupt vectors */ +-#define OSC_XOSCF_vect_num 1 +-#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ +- +-/* PORTC interrupt vectors */ +-#define PORTC_INT0_vect_num 2 +-#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +-#define PORTC_INT1_vect_num 3 +-#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ +- +-/* PORTR interrupt vectors */ +-#define PORTR_INT0_vect_num 4 +-#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +-#define PORTR_INT1_vect_num 5 +-#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ +- +-/* DMA interrupt vectors */ +-#define DMA_CH0_vect_num 6 +-#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +-#define DMA_CH1_vect_num 7 +-#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +-#define DMA_CH2_vect_num 8 +-#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +-#define DMA_CH3_vect_num 9 +-#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ +- +-/* RTC interrupt vectors */ +-#define RTC_OVF_vect_num 10 +-#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +-#define RTC_COMP_vect_num 11 +-#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ +- +-/* TWIC interrupt vectors */ +-#define TWIC_TWIS_vect_num 12 +-#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +-#define TWIC_TWIM_vect_num 13 +-#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ +- +-/* TCC0 interrupt vectors */ +-#define TCC0_OVF_vect_num 14 +-#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +-#define TCC0_ERR_vect_num 15 +-#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +-#define TCC0_CCA_vect_num 16 +-#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +-#define TCC0_CCB_vect_num 17 +-#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +-#define TCC0_CCC_vect_num 18 +-#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +-#define TCC0_CCD_vect_num 19 +-#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ +- +-/* TCC1 interrupt vectors */ +-#define TCC1_OVF_vect_num 20 +-#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +-#define TCC1_ERR_vect_num 21 +-#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +-#define TCC1_CCA_vect_num 22 +-#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +-#define TCC1_CCB_vect_num 23 +-#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ +- +-/* SPIC interrupt vectors */ +-#define SPIC_INT_vect_num 24 +-#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ +- +-/* USARTC0 interrupt vectors */ +-#define USARTC0_RXC_vect_num 25 +-#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +-#define USARTC0_DRE_vect_num 26 +-#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +-#define USARTC0_TXC_vect_num 27 +-#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ +- +-/* USARTC1 interrupt vectors */ +-#define USARTC1_RXC_vect_num 28 +-#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +-#define USARTC1_DRE_vect_num 29 +-#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +-#define USARTC1_TXC_vect_num 30 +-#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ +- +-/* AES interrupt vectors */ +-#define AES_INT_vect_num 31 +-#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ +- +-/* NVM interrupt vectors */ +-#define NVM_EE_vect_num 32 +-#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +-#define NVM_SPM_vect_num 33 +-#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ +- +-/* PORTB interrupt vectors */ +-#define PORTB_INT0_vect_num 34 +-#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +-#define PORTB_INT1_vect_num 35 +-#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ +- +-/* ACB interrupt vectors */ +-#define ACB_AC0_vect_num 36 +-#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ +-#define ACB_AC1_vect_num 37 +-#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ +-#define ACB_ACW_vect_num 38 +-#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ +- +-/* ADCB interrupt vectors */ +-#define ADCB_CH0_vect_num 39 +-#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ +-#define ADCB_CH1_vect_num 40 +-#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ +-#define ADCB_CH2_vect_num 41 +-#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ +-#define ADCB_CH3_vect_num 42 +-#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ +- +-/* PORTE interrupt vectors */ +-#define PORTE_INT0_vect_num 43 +-#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +-#define PORTE_INT1_vect_num 44 +-#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ +- +-/* TWIE interrupt vectors */ +-#define TWIE_TWIS_vect_num 45 +-#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +-#define TWIE_TWIM_vect_num 46 +-#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ +- +-/* TCE0 interrupt vectors */ +-#define TCE0_OVF_vect_num 47 +-#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +-#define TCE0_ERR_vect_num 48 +-#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +-#define TCE0_CCA_vect_num 49 +-#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +-#define TCE0_CCB_vect_num 50 +-#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +-#define TCE0_CCC_vect_num 51 +-#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +-#define TCE0_CCD_vect_num 52 +-#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ +- +-/* TCE1 interrupt vectors */ +-#define TCE1_OVF_vect_num 53 +-#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ +-#define TCE1_ERR_vect_num 54 +-#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ +-#define TCE1_CCA_vect_num 55 +-#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ +-#define TCE1_CCB_vect_num 56 +-#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ +- +-/* SPIE interrupt vectors */ +-#define SPIE_INT_vect_num 57 +-#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ +- +-/* USARTE0 interrupt vectors */ +-#define USARTE0_RXC_vect_num 58 +-#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +-#define USARTE0_DRE_vect_num 59 +-#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +-#define USARTE0_TXC_vect_num 60 +-#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ +- +-/* USARTE1 interrupt vectors */ +-#define USARTE1_RXC_vect_num 61 +-#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ +-#define USARTE1_DRE_vect_num 62 +-#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ +-#define USARTE1_TXC_vect_num 63 +-#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ +- +-/* PORTD interrupt vectors */ +-#define PORTD_INT0_vect_num 64 +-#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +-#define PORTD_INT1_vect_num 65 +-#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ +- +-/* PORTA interrupt vectors */ +-#define PORTA_INT0_vect_num 66 +-#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +-#define PORTA_INT1_vect_num 67 +-#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ +- +-/* ACA interrupt vectors */ +-#define ACA_AC0_vect_num 68 +-#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +-#define ACA_AC1_vect_num 69 +-#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +-#define ACA_ACW_vect_num 70 +-#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ +- +-/* ADCA interrupt vectors */ +-#define ADCA_CH0_vect_num 71 +-#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +-#define ADCA_CH1_vect_num 72 +-#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +-#define ADCA_CH2_vect_num 73 +-#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +-#define ADCA_CH3_vect_num 74 +-#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ +- +-/* TWID interrupt vectors */ +-#define TWID_TWIS_vect_num 75 +-#define TWID_TWIS_vect _VECTOR(75) /* TWI Slave Interrupt */ +-#define TWID_TWIM_vect_num 76 +-#define TWID_TWIM_vect _VECTOR(76) /* TWI Master Interrupt */ +- +-/* TCD0 interrupt vectors */ +-#define TCD0_OVF_vect_num 77 +-#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +-#define TCD0_ERR_vect_num 78 +-#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +-#define TCD0_CCA_vect_num 79 +-#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +-#define TCD0_CCB_vect_num 80 +-#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +-#define TCD0_CCC_vect_num 81 +-#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +-#define TCD0_CCD_vect_num 82 +-#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ +- +-/* TCD1 interrupt vectors */ +-#define TCD1_OVF_vect_num 83 +-#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +-#define TCD1_ERR_vect_num 84 +-#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +-#define TCD1_CCA_vect_num 85 +-#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +-#define TCD1_CCB_vect_num 86 +-#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ +- +-/* SPID interrupt vectors */ +-#define SPID_INT_vect_num 87 +-#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ +- +-/* USARTD0 interrupt vectors */ +-#define USARTD0_RXC_vect_num 88 +-#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +-#define USARTD0_DRE_vect_num 89 +-#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +-#define USARTD0_TXC_vect_num 90 +-#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ +- +-/* USARTD1 interrupt vectors */ +-#define USARTD1_RXC_vect_num 91 +-#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +-#define USARTD1_DRE_vect_num 92 +-#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +-#define USARTD1_TXC_vect_num 93 +-#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ +- +-/* PORTQ interrupt vectors */ +-#define PORTQ_INT0_vect_num 94 +-#define PORTQ_INT0_vect _VECTOR(94) /* External Interrupt 0 */ +-#define PORTQ_INT1_vect_num 95 +-#define PORTQ_INT1_vect _VECTOR(95) /* External Interrupt 1 */ +- +-/* PORTH interrupt vectors */ +-#define PORTH_INT0_vect_num 96 +-#define PORTH_INT0_vect _VECTOR(96) /* External Interrupt 0 */ +-#define PORTH_INT1_vect_num 97 +-#define PORTH_INT1_vect _VECTOR(97) /* External Interrupt 1 */ +- +-/* PORTJ interrupt vectors */ +-#define PORTJ_INT0_vect_num 98 +-#define PORTJ_INT0_vect _VECTOR(98) /* External Interrupt 0 */ +-#define PORTJ_INT1_vect_num 99 +-#define PORTJ_INT1_vect _VECTOR(99) /* External Interrupt 1 */ +- +-/* PORTK interrupt vectors */ +-#define PORTK_INT0_vect_num 100 +-#define PORTK_INT0_vect _VECTOR(100) /* External Interrupt 0 */ +-#define PORTK_INT1_vect_num 101 +-#define PORTK_INT1_vect _VECTOR(101) /* External Interrupt 1 */ +- +-/* PORTF interrupt vectors */ +-#define PORTF_INT0_vect_num 104 +-#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +-#define PORTF_INT1_vect_num 105 +-#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ +- +-/* TWIF interrupt vectors */ +-#define TWIF_TWIS_vect_num 106 +-#define TWIF_TWIS_vect _VECTOR(106) /* TWI Slave Interrupt */ +-#define TWIF_TWIM_vect_num 107 +-#define TWIF_TWIM_vect _VECTOR(107) /* TWI Master Interrupt */ +- +-/* TCF0 interrupt vectors */ +-#define TCF0_OVF_vect_num 108 +-#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ +-#define TCF0_ERR_vect_num 109 +-#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ +-#define TCF0_CCA_vect_num 110 +-#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ +-#define TCF0_CCB_vect_num 111 +-#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ +-#define TCF0_CCC_vect_num 112 +-#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ +-#define TCF0_CCD_vect_num 113 +-#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ +- +-/* TCF1 interrupt vectors */ +-#define TCF1_OVF_vect_num 114 +-#define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */ +-#define TCF1_ERR_vect_num 115 +-#define TCF1_ERR_vect _VECTOR(115) /* Error Interrupt */ +-#define TCF1_CCA_vect_num 116 +-#define TCF1_CCA_vect _VECTOR(116) /* Compare or Capture A Interrupt */ +-#define TCF1_CCB_vect_num 117 +-#define TCF1_CCB_vect _VECTOR(117) /* Compare or Capture B Interrupt */ +- +-/* SPIF interrupt vectors */ +-#define SPIF_INT_vect_num 118 +-#define SPIF_INT_vect _VECTOR(118) /* SPI Interrupt */ +- +-/* USARTF0 interrupt vectors */ +-#define USARTF0_RXC_vect_num 119 +-#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ +-#define USARTF0_DRE_vect_num 120 +-#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ +-#define USARTF0_TXC_vect_num 121 +-#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ +- +-/* USARTF1 interrupt vectors */ +-#define USARTF1_RXC_vect_num 122 +-#define USARTF1_RXC_vect _VECTOR(122) /* Reception Complete Interrupt */ +-#define USARTF1_DRE_vect_num 123 +-#define USARTF1_DRE_vect _VECTOR(123) /* Data Register Empty Interrupt */ +-#define USARTF1_TXC_vect_num 124 +-#define USARTF1_TXC_vect _VECTOR(124) /* Transmission Complete Interrupt */ +- +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (125 * _VECTOR_SIZE) +- +- +-/* ========== Constants ========== */ +- +-#define PROGMEM_START (0x0000) +-#define PROGMEM_SIZE (139264) +-#define PROGMEM_PAGE_SIZE (512) +-#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) +- +-#define APP_SECTION_START (0x0000) +-#define APP_SECTION_SIZE (131072) +-#define APP_SECTION_PAGE_SIZE (512) +-#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) +- +-#define APPTABLE_SECTION_START (0x1E000) +-#define APPTABLE_SECTION_SIZE (8192) +-#define APPTABLE_SECTION_PAGE_SIZE (512) +-#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) +- +-#define BOOT_SECTION_START (0x20000) +-#define BOOT_SECTION_SIZE (8192) +-#define BOOT_SECTION_PAGE_SIZE (512) +-#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) +- +-#define DATAMEM_START (0x0000) +-#define DATAMEM_SIZE (16777216) +-#define DATAMEM_PAGE_SIZE (0) +-#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) +- +-#define IO_START (0x0000) +-#define IO_SIZE (4096) +-#define IO_PAGE_SIZE (0) +-#define IO_END (IO_START + IO_SIZE - 1) +- +-#define MAPPED_EEPROM_START (0x1000) +-#define MAPPED_EEPROM_SIZE (2048) +-#define MAPPED_EEPROM_PAGE_SIZE (0) +-#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) +- +-#define INTERNAL_SRAM_START (0x2000) +-#define INTERNAL_SRAM_SIZE (8192) +-#define INTERNAL_SRAM_PAGE_SIZE (0) +-#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) +- +-#define EXTERNAL_SRAM_START (0x4000) +-#define EXTERNAL_SRAM_SIZE (16760832) +-#define EXTERNAL_SRAM_PAGE_SIZE (0) +-#define EXTERNAL_SRAM_END (EXTERNAL_SRAM_START + EXTERNAL_SRAM_SIZE - 1) +- +-#define EEPROM_START (0x0000) +-#define EEPROM_SIZE (2048) +-#define EEPROM_PAGE_SIZE (32) +-#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) +- +-#define FUSE_START (0x0000) +-#define FUSE_SIZE (6) +-#define FUSE_PAGE_SIZE (0) +-#define FUSE_END (FUSE_START + FUSE_SIZE - 1) +- +-#define LOCKBIT_START (0x0000) +-#define LOCKBIT_SIZE (1) +-#define LOCKBIT_PAGE_SIZE (0) +-#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) +- +-#define SIGNATURES_START (0x0000) +-#define SIGNATURES_SIZE (3) +-#define SIGNATURES_PAGE_SIZE (0) +-#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) +- +-#define USER_SIGNATURES_START (0x0000) +-#define USER_SIGNATURES_SIZE (512) +-#define USER_SIGNATURES_PAGE_SIZE (0) +-#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) +- +-#define PROD_SIGNATURES_START (0x0000) +-#define PROD_SIGNATURES_SIZE (52) +-#define PROD_SIGNATURES_PAGE_SIZE (0) +-#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) +- +-#define FLASHEND PROGMEM_END +-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +-#define RAMSTART INTERNAL_SRAM_START +-#define RAMSIZE INTERNAL_SRAM_SIZE +-#define RAMEND INTERNAL_SRAM_END +-#define XRAMSTART EXTERNAL_SRAM_START +-#define XRAMSIZE EXTERNAL_SRAM_SIZE +-#define XRAMEND EXTERNAL_SRAM_END +-#define E2END EEPROM_END +-#define E2PAGESIZE EEPROM_PAGE_SIZE +- +- +-/* ========== Fuses ========== */ +-#define FUSE_MEMORY_SIZE 6 +- +-/* Fuse Byte 0 */ +-#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ +-#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ +-#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ +-#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ +-#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ +-#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ +-#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ +-#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ +-#define FUSE0_DEFAULT (0xFF) +- +-/* Fuse Byte 1 */ +-#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +-#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +-#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +-#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +-#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +-#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +-#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +-#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +-#define FUSE1_DEFAULT (0xFF) +- +-/* Fuse Byte 2 */ +-#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +-#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +-#define FUSE_BODACT0 (unsigned char)~_BV(2) /* BOD Operation in Active Mode Bit 0 */ +-#define FUSE_BODACT1 (unsigned char)~_BV(3) /* BOD Operation in Active Mode Bit 1 */ +-#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +-#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +-#define FUSE2_DEFAULT (0xFF) +- +-/* Fuse Byte 3 Reserved */ +- +-/* Fuse Byte 4 */ +-#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ +-#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +-#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +-#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +-#define FUSE4_DEFAULT (0xFF) +- +-/* Fuse Byte 5 */ +-#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +-#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +-#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +-#define FUSE5_DEFAULT (0xFF) +- +- +-/* ========== Lock Bits ========== */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_BITS_EXIST +-#define __BOOT_LOCK_BOOT_BITS_EXIST +- +- +-/* ========== Signature ========== */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x97 +-#define SIGNATURE_2 0x4C +- +- +-#endif /* _AVR_ATxmega128A1_H_ */ +- ++/* Copyright (c) 2009-2010 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iox128a1.h 2200 2010-12-14 04:24:24Z arcanum $ */ ++ ++/* avr/iox128a1.h - definitions for ATxmega128A1 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox128a1.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATxmega128A1_H_ ++#define _AVR_ATxmega128A1_H_ 1 ++ ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++} CLK_t; ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t PRPB; /* Power Reduction Port B */ ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ ++} CLK_RTCSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control REgister */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t reserved_0x07; ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Channel */ ++typedef struct DMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Address Control */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ ++ register8_t REPCNT; /* Channel Repeat Count */ ++ register8_t reserved_0x07; ++ register8_t SRCADDR0; /* Channel Source Address 0 */ ++ register8_t SRCADDR1; /* Channel Source Address 1 */ ++ register8_t SRCADDR2; /* Channel Source Address 2 */ ++ register8_t reserved_0x0B; ++ register8_t DESTADDR0; /* Channel Destination Address 0 */ ++ register8_t DESTADDR1; /* Channel Destination Address 1 */ ++ register8_t DESTADDR2; /* Channel Destination Address 2 */ ++ register8_t reserved_0x0F; ++} DMA_CH_t; ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Controller */ ++typedef struct DMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ DMA_CH_t CH0; /* DMA Channel 0 */ ++ DMA_CH_t CH1; /* DMA Channel 1 */ ++ DMA_CH_t CH2; /* DMA Channel 2 */ ++ DMA_CH_t CH3; /* DMA Channel 3 */ ++} DMA_t; ++ ++/* Burst mode */ ++typedef enum DMA_CH_BURSTLEN_enum ++{ ++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ ++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ ++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ ++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ ++} DMA_CH_BURSTLEN_t; ++ ++/* Source address reload mode */ ++typedef enum DMA_CH_SRCRELOAD_enum ++{ ++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ ++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ ++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ ++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ ++} DMA_CH_SRCRELOAD_t; ++ ++/* Source addressing mode */ ++typedef enum DMA_CH_SRCDIR_enum ++{ ++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ ++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ ++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ ++} DMA_CH_SRCDIR_t; ++ ++/* Destination adress reload mode */ ++typedef enum DMA_CH_DESTRELOAD_enum ++{ ++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ ++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ ++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ ++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ ++} DMA_CH_DESTRELOAD_t; ++ ++/* Destination adressing mode */ ++typedef enum DMA_CH_DESTDIR_enum ++{ ++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ ++} DMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum DMA_CH_TRIGSRC_enum ++{ ++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ ++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ ++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ ++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ ++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ ++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ ++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ ++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ ++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ ++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ ++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ ++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ ++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ ++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ ++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ ++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ ++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ ++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ ++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ ++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ ++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ ++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ ++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ ++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ ++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ ++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ ++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ ++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ ++} DMA_CH_TRIGSRC_t; ++ ++/* Double buffering mode */ ++typedef enum DMA_DBUFMODE_enum ++{ ++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ ++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ ++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ ++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ ++} DMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum DMA_PRIMODE_enum ++{ ++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ ++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ ++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ ++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ ++} DMA_PRIMODE_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_ERRINTLVL_enum ++{ ++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ ++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ ++} DMA_CH_ERRINTLVL_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_TRNINTLVL_enum ++{ ++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ ++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ ++} DMA_CH_TRNINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ ++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ ++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ ++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t CH4CTRL; /* Channel 4 Control Register */ ++ register8_t CH5CTRL; /* Channel 5 Control Register */ ++ register8_t CH6CTRL; /* Channel 6 Control Register */ ++ register8_t CH7CTRL; /* Channel 7 Control Register */ ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ ++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ ++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ ++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ ++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ ++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ ++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ ++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ ++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ ++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ ++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ ++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ ++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ ++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ ++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ ++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ ++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ ++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t FUSEBYTE0; /* JTAG User ID */ ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ ++ register8_t reserved_0x01; ++ register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ ++ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ ++ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ ++ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++} NVM_PROD_SIGNATURES_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++} NVM_LB_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_INSAMPLEDMODE_gc = (0x01<<2), /* BOD enabled in sampled mode */ ++ BOD_CONTINOUSLY_gc = (0x02<<2), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<2), /* BOD Disabled */ ++} BOD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brown Out Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ ++ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Comparator 0 Control */ ++ register8_t AC1CTRL; /* Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t reserved_0x6; ++ register8_t reserved_0x7; ++} ADC_CH_t; ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ _WORDREGISTER(CH1RES); /* Channel 1 Result */ ++ _WORDREGISTER(CH2RES); /* Channel 2 Result */ ++ _WORDREGISTER(CH3RES); /* Channel 3 Result */ ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++ ADC_CH_t CH1; /* ADC Channel 1 */ ++ ADC_CH_t CH2; /* ADC Channel 2 */ ++ ADC_CH_t CH3; /* ADC Channel 3 */ ++} ADC_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++} ADC_REFSEL_t; ++ ++/* Channel sweep selection */ ++typedef enum ADC_SWEEP_enum ++{ ++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ ++} ADC_SWEEP_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ++ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* DMA request selection */ ++typedef enum ADC_DMASEL_enum ++{ ++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ ++} ADC_DMASEL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DAC - Digital/Analog Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Digital-to-Analog Converter */ ++typedef struct DAC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t EVCTRL; /* Event Input Control */ ++ register8_t TIMCTRL; /* Timing Control */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t GAINCAL; /* Gain Calibration */ ++ register8_t OFFSETCAL; /* Offset Calibration */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ ++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ ++} DAC_t; ++ ++/* Output channel selection */ ++typedef enum DAC_CHSEL_enum ++{ ++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ ++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ ++} DAC_CHSEL_t; ++ ++/* Reference voltage selection */ ++typedef enum DAC_REFSEL_enum ++{ ++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ ++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ ++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ ++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ ++} DAC_REFSEL_t; ++ ++/* Event channel selection */ ++typedef enum DAC_EVSEL_enum ++{ ++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ ++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ ++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ ++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ ++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ ++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ ++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ ++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ ++} DAC_EVSEL_t; ++ ++/* Conversion interval */ ++typedef enum DAC_CONINTVAL_enum ++{ ++ DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ ++ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ ++ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ ++ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ ++ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ ++ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ ++ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ ++ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ ++} DAC_CONINTVAL_t; ++ ++/* Refresh rate */ ++typedef enum DAC_REFRESH_enum ++{ ++ DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ ++ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ ++ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ ++ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ ++ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ ++ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ ++ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ ++ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ ++ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ ++ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ ++ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ ++ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ ++ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ ++ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ ++} DAC_REFRESH_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Clounter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* EBI Chip Select Module */ ++typedef struct EBI_CS_struct ++{ ++ register8_t CTRLA; /* Chip Select Control Register A */ ++ register8_t CTRLB; /* Chip Select Control Register B */ ++ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ ++} EBI_CS_t; ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* External Bus Interface */ ++typedef struct EBI_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ ++ register8_t reserved_0x02; ++ register8_t reserved_0x03; ++ _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ ++ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ ++ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ ++ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ EBI_CS_t CS0; /* Chip Select 0 */ ++ EBI_CS_t CS1; /* Chip Select 1 */ ++ EBI_CS_t CS2; /* Chip Select 2 */ ++ EBI_CS_t CS3; /* Chip Select 3 */ ++} EBI_t; ++ ++/* Chip Select adress space */ ++typedef enum EBI_CS_ASIZE_enum ++{ ++ EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ ++ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ ++ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ ++ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ ++ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ ++ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ ++ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ ++ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ ++ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ ++ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ ++ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ ++ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ ++ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ ++ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ ++ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ ++ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ ++ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ ++} EBI_CS_ASIZE_t; ++ ++/* */ ++typedef enum EBI_CS_SRWS_enum ++{ ++ EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_CS_SRWS_t; ++ ++/* Chip Select address mode */ ++typedef enum EBI_CS_MODE_enum ++{ ++ EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ ++ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ ++ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ ++ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ ++} EBI_CS_MODE_t; ++ ++/* Chip Select SDRAM mode */ ++typedef enum EBI_CS_SDMODE_enum ++{ ++ EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ ++ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ ++} EBI_CS_SDMODE_t; ++ ++/* */ ++typedef enum EBI_SDDATAW_enum ++{ ++ EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ ++ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ ++} EBI_SDDATAW_t; ++ ++/* */ ++typedef enum EBI_LPCMODE_enum ++{ ++ EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ ++ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ ++} EBI_LPCMODE_t; ++ ++/* */ ++typedef enum EBI_SRMODE_enum ++{ ++ EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ ++ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ ++ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ ++ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ ++} EBI_SRMODE_t; ++ ++/* */ ++typedef enum EBI_IFMODE_enum ++{ ++ EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ ++ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ ++ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ ++ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ ++} EBI_IFMODE_t; ++ ++/* */ ++typedef enum EBI_SDCOL_enum ++{ ++ EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ ++ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ ++ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ ++ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ ++} EBI_SDCOL_t; ++ ++/* */ ++typedef enum EBI_MRDLY_enum ++{ ++ EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_MRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCYCDLY_enum ++{ ++ EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ROWCYCDLY_t; ++ ++/* */ ++typedef enum EBI_RPDLY_enum ++{ ++ EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_RPDLY_t; ++ ++/* */ ++typedef enum EBI_WRDLY_enum ++{ ++ EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_WRDLY_t; ++ ++/* */ ++typedef enum EBI_ESRDLY_enum ++{ ++ EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ESRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCOLDLY_enum ++{ ++ EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_ROWCOLDLY_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++} PORTCFG_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Virtual Port 0 Mapping */ ++typedef enum PORTCFG_VP0MAP_enum ++{ ++ PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP0MAP_t; ++ ++/* Virtual Port 1 Mapping */ ++typedef enum PORTCFG_VP1MAP_enum ++{ ++ PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP1MAP_t; ++ ++/* Virtual Port 2 Mapping */ ++typedef enum PORTCFG_VP2MAP_enum ++{ ++ PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP2MAP_t; ++ ++/* Virtual Port 3 Mapping */ ++typedef enum PORTCFG_VP3MAP_enum ++{ ++ PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP3MAP_t; ++ ++/* Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x05; ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++} HIRES_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AES - AES Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* AES Module */ ++typedef struct AES_struct ++{ ++ register8_t CTRL; /* AES Control Register */ ++ register8_t STATUS; /* AES Status Register */ ++ register8_t STATE; /* AES State Register */ ++ register8_t KEY; /* AES Key Register */ ++ register8_t INTCTRL; /* AES Interrupt Control Register */ ++} AES_t; ++ ++/* Interrupt level */ ++typedef enum AES_INTLVL_enum ++{ ++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} AES_INTLVL_t; ++ ++ ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset Controller */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ ++#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ ++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ ++#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ ++#define DACA (*(DAC_t *) 0x0300) /* Digital to Analog Converter A */ ++#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ ++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ ++#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface D */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ ++#define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface F */ ++#define PORTA (*(PORT_t *) 0x0600) /* Port A */ ++#define PORTB (*(PORT_t *) 0x0620) /* Port B */ ++#define PORTC (*(PORT_t *) 0x0640) /* Port C */ ++#define PORTD (*(PORT_t *) 0x0660) /* Port D */ ++#define PORTE (*(PORT_t *) 0x0680) /* Port E */ ++#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ ++#define PORTH (*(PORT_t *) 0x06E0) /* Port H */ ++#define PORTJ (*(PORT_t *) 0x0700) /* Port J */ ++#define PORTK (*(PORT_t *) 0x0720) /* Port K */ ++#define PORTQ (*(PORT_t *) 0x07C0) /* Port Q */ ++#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ ++#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ ++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ ++#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ ++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ ++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ ++#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ ++#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ ++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ ++#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ ++#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ ++#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ ++#define TCF1 (*(TC1_t *) 0x0B40) /* Timer/Counter F1 */ ++#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ ++#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ ++#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ ++#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++#define GPIO_GPIOR4 _SFR_MEM8(0x0004) ++#define GPIO_GPIOR5 _SFR_MEM8(0x0005) ++#define GPIO_GPIOR6 _SFR_MEM8(0x0006) ++#define GPIO_GPIOR7 _SFR_MEM8(0x0007) ++#define GPIO_GPIOR8 _SFR_MEM8(0x0008) ++#define GPIO_GPIOR9 _SFR_MEM8(0x0009) ++#define GPIO_GPIORA _SFR_MEM8(0x000A) ++#define GPIO_GPIORB _SFR_MEM8(0x000B) ++#define GPIO_GPIORC _SFR_MEM8(0x000C) ++#define GPIO_GPIORD _SFR_MEM8(0x000D) ++#define GPIO_GPIORE _SFR_MEM8(0x000E) ++#define GPIO_GPIORF _SFR_MEM8(0x000F) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++#define GPIO_GPIO4 _SFR_MEM8(0x0004) ++#define GPIO_GPIO5 _SFR_MEM8(0x0005) ++#define GPIO_GPIO6 _SFR_MEM8(0x0006) ++#define GPIO_GPIO7 _SFR_MEM8(0x0007) ++#define GPIO_GPIO8 _SFR_MEM8(0x0008) ++#define GPIO_GPIO9 _SFR_MEM8(0x0009) ++#define GPIO_GPIOA _SFR_MEM8(0x000A) ++#define GPIO_GPIOB _SFR_MEM8(0x000B) ++#define GPIO_GPIOC _SFR_MEM8(0x000C) ++#define GPIO_GPIOD _SFR_MEM8(0x000D) ++#define GPIO_GPIOE _SFR_MEM8(0x000E) ++#define GPIO_GPIOF _SFR_MEM8(0x000F) ++ ++/* VPORT0 - Virtual Port 0 */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT1 - Virtual Port 1 */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT2 - Virtual Port 2 */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT3 - Virtual Port 3 */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU Registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator Control */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPB _SFR_MEM8(0x0072) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset Controller */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - Port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++ ++/* AES - AES Crypto Module */ ++#define AES_CTRL _SFR_MEM8(0x00C0) ++#define AES_STATUS _SFR_MEM8(0x00C1) ++#define AES_STATE _SFR_MEM8(0x00C2) ++#define AES_KEY _SFR_MEM8(0x00C3) ++#define AES_INTCTRL _SFR_MEM8(0x00C4) ++ ++/* DMA - DMA Controller */ ++#define DMA_CTRL _SFR_MEM8(0x0100) ++#define DMA_INTFLAGS _SFR_MEM8(0x0103) ++#define DMA_STATUS _SFR_MEM8(0x0104) ++#define DMA_TEMP _SFR_MEM16(0x0106) ++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) ++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) ++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) ++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) ++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) ++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) ++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) ++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) ++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) ++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) ++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) ++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) ++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) ++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) ++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) ++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) ++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) ++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) ++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) ++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) ++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) ++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) ++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) ++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) ++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) ++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) ++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) ++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) ++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) ++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) ++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) ++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) ++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) ++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) ++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) ++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) ++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) ++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) ++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) ++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) ++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) ++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH4MUX _SFR_MEM8(0x0184) ++#define EVSYS_CH5MUX _SFR_MEM8(0x0185) ++#define EVSYS_CH6MUX _SFR_MEM8(0x0186) ++#define EVSYS_CH7MUX _SFR_MEM8(0x0187) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) ++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) ++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) ++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non Volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADCA - Analog to Digital Converter A */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CH1RES _SFR_MEM16(0x0212) ++#define ADCA_CH2RES _SFR_MEM16(0x0214) ++#define ADCA_CH3RES _SFR_MEM16(0x0216) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) ++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) ++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) ++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) ++#define ADCA_CH1_RES _SFR_MEM16(0x022C) ++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) ++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) ++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) ++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) ++#define ADCA_CH2_RES _SFR_MEM16(0x0234) ++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) ++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) ++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) ++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) ++#define ADCA_CH3_RES _SFR_MEM16(0x023C) ++ ++/* ADCB - Analog to Digital Converter B */ ++#define ADCB_CTRLA _SFR_MEM8(0x0240) ++#define ADCB_CTRLB _SFR_MEM8(0x0241) ++#define ADCB_REFCTRL _SFR_MEM8(0x0242) ++#define ADCB_EVCTRL _SFR_MEM8(0x0243) ++#define ADCB_PRESCALER _SFR_MEM8(0x0244) ++#define ADCB_INTFLAGS _SFR_MEM8(0x0246) ++#define ADCB_CAL _SFR_MEM16(0x024C) ++#define ADCB_CH0RES _SFR_MEM16(0x0250) ++#define ADCB_CH1RES _SFR_MEM16(0x0252) ++#define ADCB_CH2RES _SFR_MEM16(0x0254) ++#define ADCB_CH3RES _SFR_MEM16(0x0256) ++#define ADCB_CMP _SFR_MEM16(0x0258) ++#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) ++#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) ++#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) ++#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) ++#define ADCB_CH0_RES _SFR_MEM16(0x0264) ++#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) ++#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) ++#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) ++#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) ++#define ADCB_CH1_RES _SFR_MEM16(0x026C) ++#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) ++#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) ++#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) ++#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) ++#define ADCB_CH2_RES _SFR_MEM16(0x0274) ++#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) ++#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) ++#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) ++#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) ++#define ADCB_CH3_RES _SFR_MEM16(0x027C) ++ ++/* DACA - Digital to Analog Converter A */ ++#define DACA_CTRLA _SFR_MEM8(0x0300) ++#define DACA_CTRLB _SFR_MEM8(0x0301) ++#define DACA_CTRLC _SFR_MEM8(0x0302) ++#define DACA_EVCTRL _SFR_MEM8(0x0303) ++#define DACA_TIMCTRL _SFR_MEM8(0x0304) ++#define DACA_STATUS _SFR_MEM8(0x0305) ++#define DACA_GAINCAL _SFR_MEM8(0x0308) ++#define DACA_OFFSETCAL _SFR_MEM8(0x0309) ++#define DACA_CH0DATA _SFR_MEM16(0x0318) ++#define DACA_CH1DATA _SFR_MEM16(0x031A) ++ ++/* DACB - Digital to Analog Converter B */ ++#define DACB_CTRLA _SFR_MEM8(0x0320) ++#define DACB_CTRLB _SFR_MEM8(0x0321) ++#define DACB_CTRLC _SFR_MEM8(0x0322) ++#define DACB_EVCTRL _SFR_MEM8(0x0323) ++#define DACB_TIMCTRL _SFR_MEM8(0x0324) ++#define DACB_STATUS _SFR_MEM8(0x0325) ++#define DACB_GAINCAL _SFR_MEM8(0x0328) ++#define DACB_OFFSETCAL _SFR_MEM8(0x0329) ++#define DACB_CH0DATA _SFR_MEM16(0x0338) ++#define DACB_CH1DATA _SFR_MEM16(0x033A) ++ ++/* ACA - Analog Comparator A */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* ACB - Analog Comparator B */ ++#define ACB_AC0CTRL _SFR_MEM8(0x0390) ++#define ACB_AC1CTRL _SFR_MEM8(0x0391) ++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) ++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) ++#define ACB_CTRLA _SFR_MEM8(0x0394) ++#define ACB_CTRLB _SFR_MEM8(0x0395) ++#define ACB_WINCTRL _SFR_MEM8(0x0396) ++#define ACB_STATUS _SFR_MEM8(0x0397) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* EBI - External Bus Interface */ ++#define EBI_CTRL _SFR_MEM8(0x0440) ++#define EBI_SDRAMCTRLA _SFR_MEM8(0x0441) ++#define EBI_REFRESH _SFR_MEM16(0x0444) ++#define EBI_INITDLY _SFR_MEM16(0x0446) ++#define EBI_SDRAMCTRLB _SFR_MEM8(0x0448) ++#define EBI_SDRAMCTRLC _SFR_MEM8(0x0449) ++#define EBI_CS0_CTRLA _SFR_MEM8(0x0450) ++#define EBI_CS0_CTRLB _SFR_MEM8(0x0451) ++#define EBI_CS0_BASEADDR _SFR_MEM16(0x0452) ++#define EBI_CS1_CTRLA _SFR_MEM8(0x0454) ++#define EBI_CS1_CTRLB _SFR_MEM8(0x0455) ++#define EBI_CS1_BASEADDR _SFR_MEM16(0x0456) ++#define EBI_CS2_CTRLA _SFR_MEM8(0x0458) ++#define EBI_CS2_CTRLB _SFR_MEM8(0x0459) ++#define EBI_CS2_BASEADDR _SFR_MEM16(0x045A) ++#define EBI_CS3_CTRLA _SFR_MEM8(0x045C) ++#define EBI_CS3_CTRLB _SFR_MEM8(0x045D) ++#define EBI_CS3_BASEADDR _SFR_MEM16(0x045E) ++ ++/* TWIC - Two-Wire Interface C */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWID - Two-Wire Interface D */ ++#define TWID_CTRL _SFR_MEM8(0x0490) ++#define TWID_MASTER_CTRLA _SFR_MEM8(0x0491) ++#define TWID_MASTER_CTRLB _SFR_MEM8(0x0492) ++#define TWID_MASTER_CTRLC _SFR_MEM8(0x0493) ++#define TWID_MASTER_STATUS _SFR_MEM8(0x0494) ++#define TWID_MASTER_BAUD _SFR_MEM8(0x0495) ++#define TWID_MASTER_ADDR _SFR_MEM8(0x0496) ++#define TWID_MASTER_DATA _SFR_MEM8(0x0497) ++#define TWID_SLAVE_CTRLA _SFR_MEM8(0x0498) ++#define TWID_SLAVE_CTRLB _SFR_MEM8(0x0499) ++#define TWID_SLAVE_STATUS _SFR_MEM8(0x049A) ++#define TWID_SLAVE_ADDR _SFR_MEM8(0x049B) ++#define TWID_SLAVE_DATA _SFR_MEM8(0x049C) ++#define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D) ++ ++/* TWIE - Two-Wire Interface E */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* TWIF - Two-Wire Interface F */ ++#define TWIF_CTRL _SFR_MEM8(0x04B0) ++#define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1) ++#define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2) ++#define TWIF_MASTER_CTRLC _SFR_MEM8(0x04B3) ++#define TWIF_MASTER_STATUS _SFR_MEM8(0x04B4) ++#define TWIF_MASTER_BAUD _SFR_MEM8(0x04B5) ++#define TWIF_MASTER_ADDR _SFR_MEM8(0x04B6) ++#define TWIF_MASTER_DATA _SFR_MEM8(0x04B7) ++#define TWIF_SLAVE_CTRLA _SFR_MEM8(0x04B8) ++#define TWIF_SLAVE_CTRLB _SFR_MEM8(0x04B9) ++#define TWIF_SLAVE_STATUS _SFR_MEM8(0x04BA) ++#define TWIF_SLAVE_ADDR _SFR_MEM8(0x04BB) ++#define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC) ++#define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD) ++ ++/* PORTA - Port A */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORTB - Port B */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORTC - Port C */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORTD - Port D */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORTE - Port E */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORTF - Port F */ ++#define PORTF_DIR _SFR_MEM8(0x06A0) ++#define PORTF_DIRSET _SFR_MEM8(0x06A1) ++#define PORTF_DIRCLR _SFR_MEM8(0x06A2) ++#define PORTF_DIRTGL _SFR_MEM8(0x06A3) ++#define PORTF_OUT _SFR_MEM8(0x06A4) ++#define PORTF_OUTSET _SFR_MEM8(0x06A5) ++#define PORTF_OUTCLR _SFR_MEM8(0x06A6) ++#define PORTF_OUTTGL _SFR_MEM8(0x06A7) ++#define PORTF_IN _SFR_MEM8(0x06A8) ++#define PORTF_INTCTRL _SFR_MEM8(0x06A9) ++#define PORTF_INT0MASK _SFR_MEM8(0x06AA) ++#define PORTF_INT1MASK _SFR_MEM8(0x06AB) ++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) ++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) ++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) ++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) ++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) ++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) ++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) ++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) ++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) ++ ++/* PORTH - Port H */ ++#define PORTH_DIR _SFR_MEM8(0x06E0) ++#define PORTH_DIRSET _SFR_MEM8(0x06E1) ++#define PORTH_DIRCLR _SFR_MEM8(0x06E2) ++#define PORTH_DIRTGL _SFR_MEM8(0x06E3) ++#define PORTH_OUT _SFR_MEM8(0x06E4) ++#define PORTH_OUTSET _SFR_MEM8(0x06E5) ++#define PORTH_OUTCLR _SFR_MEM8(0x06E6) ++#define PORTH_OUTTGL _SFR_MEM8(0x06E7) ++#define PORTH_IN _SFR_MEM8(0x06E8) ++#define PORTH_INTCTRL _SFR_MEM8(0x06E9) ++#define PORTH_INT0MASK _SFR_MEM8(0x06EA) ++#define PORTH_INT1MASK _SFR_MEM8(0x06EB) ++#define PORTH_INTFLAGS _SFR_MEM8(0x06EC) ++#define PORTH_PIN0CTRL _SFR_MEM8(0x06F0) ++#define PORTH_PIN1CTRL _SFR_MEM8(0x06F1) ++#define PORTH_PIN2CTRL _SFR_MEM8(0x06F2) ++#define PORTH_PIN3CTRL _SFR_MEM8(0x06F3) ++#define PORTH_PIN4CTRL _SFR_MEM8(0x06F4) ++#define PORTH_PIN5CTRL _SFR_MEM8(0x06F5) ++#define PORTH_PIN6CTRL _SFR_MEM8(0x06F6) ++#define PORTH_PIN7CTRL _SFR_MEM8(0x06F7) ++ ++/* PORTJ - Port J */ ++#define PORTJ_DIR _SFR_MEM8(0x0700) ++#define PORTJ_DIRSET _SFR_MEM8(0x0701) ++#define PORTJ_DIRCLR _SFR_MEM8(0x0702) ++#define PORTJ_DIRTGL _SFR_MEM8(0x0703) ++#define PORTJ_OUT _SFR_MEM8(0x0704) ++#define PORTJ_OUTSET _SFR_MEM8(0x0705) ++#define PORTJ_OUTCLR _SFR_MEM8(0x0706) ++#define PORTJ_OUTTGL _SFR_MEM8(0x0707) ++#define PORTJ_IN _SFR_MEM8(0x0708) ++#define PORTJ_INTCTRL _SFR_MEM8(0x0709) ++#define PORTJ_INT0MASK _SFR_MEM8(0x070A) ++#define PORTJ_INT1MASK _SFR_MEM8(0x070B) ++#define PORTJ_INTFLAGS _SFR_MEM8(0x070C) ++#define PORTJ_PIN0CTRL _SFR_MEM8(0x0710) ++#define PORTJ_PIN1CTRL _SFR_MEM8(0x0711) ++#define PORTJ_PIN2CTRL _SFR_MEM8(0x0712) ++#define PORTJ_PIN3CTRL _SFR_MEM8(0x0713) ++#define PORTJ_PIN4CTRL _SFR_MEM8(0x0714) ++#define PORTJ_PIN5CTRL _SFR_MEM8(0x0715) ++#define PORTJ_PIN6CTRL _SFR_MEM8(0x0716) ++#define PORTJ_PIN7CTRL _SFR_MEM8(0x0717) ++ ++/* PORTK - Port K */ ++#define PORTK_DIR _SFR_MEM8(0x0720) ++#define PORTK_DIRSET _SFR_MEM8(0x0721) ++#define PORTK_DIRCLR _SFR_MEM8(0x0722) ++#define PORTK_DIRTGL _SFR_MEM8(0x0723) ++#define PORTK_OUT _SFR_MEM8(0x0724) ++#define PORTK_OUTSET _SFR_MEM8(0x0725) ++#define PORTK_OUTCLR _SFR_MEM8(0x0726) ++#define PORTK_OUTTGL _SFR_MEM8(0x0727) ++#define PORTK_IN _SFR_MEM8(0x0728) ++#define PORTK_INTCTRL _SFR_MEM8(0x0729) ++#define PORTK_INT0MASK _SFR_MEM8(0x072A) ++#define PORTK_INT1MASK _SFR_MEM8(0x072B) ++#define PORTK_INTFLAGS _SFR_MEM8(0x072C) ++#define PORTK_PIN0CTRL _SFR_MEM8(0x0730) ++#define PORTK_PIN1CTRL _SFR_MEM8(0x0731) ++#define PORTK_PIN2CTRL _SFR_MEM8(0x0732) ++#define PORTK_PIN3CTRL _SFR_MEM8(0x0733) ++#define PORTK_PIN4CTRL _SFR_MEM8(0x0734) ++#define PORTK_PIN5CTRL _SFR_MEM8(0x0735) ++#define PORTK_PIN6CTRL _SFR_MEM8(0x0736) ++#define PORTK_PIN7CTRL _SFR_MEM8(0x0737) ++ ++/* PORTQ - Port Q */ ++#define PORTQ_DIR _SFR_MEM8(0x07C0) ++#define PORTQ_DIRSET _SFR_MEM8(0x07C1) ++#define PORTQ_DIRCLR _SFR_MEM8(0x07C2) ++#define PORTQ_DIRTGL _SFR_MEM8(0x07C3) ++#define PORTQ_OUT _SFR_MEM8(0x07C4) ++#define PORTQ_OUTSET _SFR_MEM8(0x07C5) ++#define PORTQ_OUTCLR _SFR_MEM8(0x07C6) ++#define PORTQ_OUTTGL _SFR_MEM8(0x07C7) ++#define PORTQ_IN _SFR_MEM8(0x07C8) ++#define PORTQ_INTCTRL _SFR_MEM8(0x07C9) ++#define PORTQ_INT0MASK _SFR_MEM8(0x07CA) ++#define PORTQ_INT1MASK _SFR_MEM8(0x07CB) ++#define PORTQ_INTFLAGS _SFR_MEM8(0x07CC) ++#define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0) ++#define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1) ++#define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2) ++#define PORTQ_PIN3CTRL _SFR_MEM8(0x07D3) ++#define PORTQ_PIN4CTRL _SFR_MEM8(0x07D4) ++#define PORTQ_PIN5CTRL _SFR_MEM8(0x07D5) ++#define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6) ++#define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7) ++ ++/* PORTR - Port R */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TCC0 - Timer/Counter C0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TCC1 - Timer/Counter C1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEXC - Advanced Waveform Extension C */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRESC - High-Resolution Extension C */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ ++#define USARTC1_DATA _SFR_MEM8(0x08B0) ++#define USARTC1_STATUS _SFR_MEM8(0x08B1) ++#define USARTC1_CTRLA _SFR_MEM8(0x08B3) ++#define USARTC1_CTRLB _SFR_MEM8(0x08B4) ++#define USARTC1_CTRLC _SFR_MEM8(0x08B5) ++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) ++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) ++ ++/* SPIC - Serial Peripheral Interface C */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TCD0 - Timer/Counter D0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TCD1 - Timer/Counter D1 */ ++#define TCD1_CTRLA _SFR_MEM8(0x0940) ++#define TCD1_CTRLB _SFR_MEM8(0x0941) ++#define TCD1_CTRLC _SFR_MEM8(0x0942) ++#define TCD1_CTRLD _SFR_MEM8(0x0943) ++#define TCD1_CTRLE _SFR_MEM8(0x0944) ++#define TCD1_INTCTRLA _SFR_MEM8(0x0946) ++#define TCD1_INTCTRLB _SFR_MEM8(0x0947) ++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) ++#define TCD1_CTRLFSET _SFR_MEM8(0x0949) ++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) ++#define TCD1_CTRLGSET _SFR_MEM8(0x094B) ++#define TCD1_INTFLAGS _SFR_MEM8(0x094C) ++#define TCD1_TEMP _SFR_MEM8(0x094F) ++#define TCD1_CNT _SFR_MEM16(0x0960) ++#define TCD1_PER _SFR_MEM16(0x0966) ++#define TCD1_CCA _SFR_MEM16(0x0968) ++#define TCD1_CCB _SFR_MEM16(0x096A) ++#define TCD1_PERBUF _SFR_MEM16(0x0976) ++#define TCD1_CCABUF _SFR_MEM16(0x0978) ++#define TCD1_CCBBUF _SFR_MEM16(0x097A) ++ ++/* HIRESD - High-Resolution Extension D */ ++#define HIRESD_CTRLA _SFR_MEM8(0x0990) ++ ++/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ ++#define USARTD1_DATA _SFR_MEM8(0x09B0) ++#define USARTD1_STATUS _SFR_MEM8(0x09B1) ++#define USARTD1_CTRLA _SFR_MEM8(0x09B3) ++#define USARTD1_CTRLB _SFR_MEM8(0x09B4) ++#define USARTD1_CTRLC _SFR_MEM8(0x09B5) ++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) ++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) ++ ++/* SPID - Serial Peripheral Interface D */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TCE0 - Timer/Counter E0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* TCE1 - Timer/Counter E1 */ ++#define TCE1_CTRLA _SFR_MEM8(0x0A40) ++#define TCE1_CTRLB _SFR_MEM8(0x0A41) ++#define TCE1_CTRLC _SFR_MEM8(0x0A42) ++#define TCE1_CTRLD _SFR_MEM8(0x0A43) ++#define TCE1_CTRLE _SFR_MEM8(0x0A44) ++#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) ++#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) ++#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) ++#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) ++#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) ++#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) ++#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) ++#define TCE1_TEMP _SFR_MEM8(0x0A4F) ++#define TCE1_CNT _SFR_MEM16(0x0A60) ++#define TCE1_PER _SFR_MEM16(0x0A66) ++#define TCE1_CCA _SFR_MEM16(0x0A68) ++#define TCE1_CCB _SFR_MEM16(0x0A6A) ++#define TCE1_PERBUF _SFR_MEM16(0x0A76) ++#define TCE1_CCABUF _SFR_MEM16(0x0A78) ++#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) ++ ++/* AWEXE - Advanced Waveform Extension E */ ++#define AWEXE_CTRL _SFR_MEM8(0x0A80) ++#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) ++#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) ++#define AWEXE_STATUS _SFR_MEM8(0x0A84) ++#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) ++#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) ++#define AWEXE_DTLS _SFR_MEM8(0x0A88) ++#define AWEXE_DTHS _SFR_MEM8(0x0A89) ++#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) ++#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) ++#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) ++ ++/* HIRESE - High-Resolution Extension E */ ++#define HIRESE_CTRLA _SFR_MEM8(0x0A90) ++ ++/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ ++#define USARTE1_DATA _SFR_MEM8(0x0AB0) ++#define USARTE1_STATUS _SFR_MEM8(0x0AB1) ++#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) ++#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) ++#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) ++#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) ++#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) ++ ++/* SPIE - Serial Peripheral Interface E */ ++#define SPIE_CTRL _SFR_MEM8(0x0AC0) ++#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) ++#define SPIE_STATUS _SFR_MEM8(0x0AC2) ++#define SPIE_DATA _SFR_MEM8(0x0AC3) ++ ++/* TCF0 - Timer/Counter F0 */ ++#define TCF0_CTRLA _SFR_MEM8(0x0B00) ++#define TCF0_CTRLB _SFR_MEM8(0x0B01) ++#define TCF0_CTRLC _SFR_MEM8(0x0B02) ++#define TCF0_CTRLD _SFR_MEM8(0x0B03) ++#define TCF0_CTRLE _SFR_MEM8(0x0B04) ++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) ++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) ++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) ++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) ++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF0_TEMP _SFR_MEM8(0x0B0F) ++#define TCF0_CNT _SFR_MEM16(0x0B20) ++#define TCF0_PER _SFR_MEM16(0x0B26) ++#define TCF0_CCA _SFR_MEM16(0x0B28) ++#define TCF0_CCB _SFR_MEM16(0x0B2A) ++#define TCF0_CCC _SFR_MEM16(0x0B2C) ++#define TCF0_CCD _SFR_MEM16(0x0B2E) ++#define TCF0_PERBUF _SFR_MEM16(0x0B36) ++#define TCF0_CCABUF _SFR_MEM16(0x0B38) ++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) ++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) ++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) ++ ++/* TCF1 - Timer/Counter F1 */ ++#define TCF1_CTRLA _SFR_MEM8(0x0B40) ++#define TCF1_CTRLB _SFR_MEM8(0x0B41) ++#define TCF1_CTRLC _SFR_MEM8(0x0B42) ++#define TCF1_CTRLD _SFR_MEM8(0x0B43) ++#define TCF1_CTRLE _SFR_MEM8(0x0B44) ++#define TCF1_INTCTRLA _SFR_MEM8(0x0B46) ++#define TCF1_INTCTRLB _SFR_MEM8(0x0B47) ++#define TCF1_CTRLFCLR _SFR_MEM8(0x0B48) ++#define TCF1_CTRLFSET _SFR_MEM8(0x0B49) ++#define TCF1_CTRLGCLR _SFR_MEM8(0x0B4A) ++#define TCF1_CTRLGSET _SFR_MEM8(0x0B4B) ++#define TCF1_INTFLAGS _SFR_MEM8(0x0B4C) ++#define TCF1_TEMP _SFR_MEM8(0x0B4F) ++#define TCF1_CNT _SFR_MEM16(0x0B60) ++#define TCF1_PER _SFR_MEM16(0x0B66) ++#define TCF1_CCA _SFR_MEM16(0x0B68) ++#define TCF1_CCB _SFR_MEM16(0x0B6A) ++#define TCF1_PERBUF _SFR_MEM16(0x0B76) ++#define TCF1_CCABUF _SFR_MEM16(0x0B78) ++#define TCF1_CCBBUF _SFR_MEM16(0x0B7A) ++ ++/* HIRESF - High-Resolution Extension F */ ++#define HIRESF_CTRLA _SFR_MEM8(0x0B90) ++ ++/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ ++#define USARTF0_DATA _SFR_MEM8(0x0BA0) ++#define USARTF0_STATUS _SFR_MEM8(0x0BA1) ++#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) ++#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) ++#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) ++#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) ++#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) ++ ++/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ ++#define USARTF1_DATA _SFR_MEM8(0x0BB0) ++#define USARTF1_STATUS _SFR_MEM8(0x0BB1) ++#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) ++#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) ++#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) ++#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) ++#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) ++ ++/* SPIF - Serial Peripheral Interface F */ ++#define SPIF_CTRL _SFR_MEM8(0x0BC0) ++#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) ++#define SPIF_STATUS _SFR_MEM8(0x0BC2) ++#define SPIF_DATA _SFR_MEM8(0x0BC3) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR1 bit masks and bit positions */ ++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ ++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ ++ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ ++ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ ++#define PR_EBI_bp 3 /* External Bus Interface bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ ++#define PR_DAC_bp 2 /* Port A DAC bit position. */ ++ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++ ++/* PR.PRPB bit masks and bit positions */ ++/* PR_DAC_bm Predefined. */ ++/* PR_DAC_bp Predefined. */ ++ ++/* PR_ADC_bm Predefined. */ ++/* PR_ADC_bp Predefined. */ ++ ++/* PR_AC_bm Predefined. */ ++/* PR_AC_bp Predefined. */ ++ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ ++ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ ++ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ ++ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ ++#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ ++ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ ++ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ ++ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ ++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ ++ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++ ++/* DMA - DMA Controller */ ++/* DMA_CH.CTRLA bit masks and bit positions */ ++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ ++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ ++ ++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ ++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ ++ ++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ ++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ ++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ ++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ ++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ ++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ ++ ++ ++/* DMA_CH.CTRLB bit masks and bit positions */ ++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ ++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ ++ ++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ ++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ ++ ++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ ++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ ++ ++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ ++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ ++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ ++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ ++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ ++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ ++ ++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ ++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ ++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ ++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ ++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ ++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ ++ ++ ++/* DMA_CH.ADDRCTRL bit masks and bit positions */ ++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ ++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ ++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ ++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ ++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ ++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ ++ ++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ ++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ ++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ ++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ ++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ ++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ ++ ++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ ++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ ++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ ++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ ++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ ++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ ++ ++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ ++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ ++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ ++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ ++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ ++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ ++ ++ ++/* DMA_CH.TRIGSRC bit masks and bit positions */ ++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++ ++/* DMA.CTRL bit masks and bit positions */ ++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define DMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define DMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ ++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ ++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ ++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ ++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ ++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ ++ ++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ ++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ ++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ ++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ ++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ ++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ ++ ++ ++/* DMA.INTFLAGS bit masks and bit positions */ ++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++ ++/* DMA.STATUS bit masks and bit positions */ ++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ ++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ ++ ++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ ++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ ++ ++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ ++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ ++ ++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ ++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ ++ ++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ ++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ ++ ++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ ++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ ++ ++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ ++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ ++ ++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ ++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ ++ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH4MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH5MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH6MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH7MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM_gm Predefined. */ ++/* EVSYS_QDIRM_gp Predefined. */ ++/* EVSYS_QDIRM0_bm Predefined. */ ++/* EVSYS_QDIRM0_bp Predefined. */ ++/* EVSYS_QDIRM1_bm Predefined. */ ++/* EVSYS_QDIRM1_bp Predefined. */ ++ ++/* EVSYS_QDIEN_bm Predefined. */ ++/* EVSYS_QDIEN_bp Predefined. */ ++ ++/* EVSYS_QDEN_bm Predefined. */ ++/* EVSYS_QDEN_bp Predefined. */ ++ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH4CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM_gm Predefined. */ ++/* EVSYS_QDIRM_gp Predefined. */ ++/* EVSYS_QDIRM0_bm Predefined. */ ++/* EVSYS_QDIRM0_bp Predefined. */ ++/* EVSYS_QDIRM1_bm Predefined. */ ++/* EVSYS_QDIRM1_bp Predefined. */ ++ ++/* EVSYS_QDIEN_bm Predefined. */ ++/* EVSYS_QDIEN_bp Predefined. */ ++ ++/* EVSYS_QDEN_bm Predefined. */ ++/* EVSYS_QDEN_bp Predefined. */ ++ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH5CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH6CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH7CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0xFF /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ ++#define NVM_CMD7_bp 7 /* Command bit 7 position. */ ++ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ ++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ ++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ ++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ ++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ ++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ ++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ ++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ ++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ ++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ ++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ ++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ ++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ ++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ ++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ ++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ ++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ ++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ ++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ ++#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ ++ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_BODACT_gm 0x0C /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 2 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ ++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ ++ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ ++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE_gm Predefined. */ ++/* AC_INTMODE_gp Predefined. */ ++/* AC_INTMODE0_bm Predefined. */ ++/* AC_INTMODE0_bp Predefined. */ ++/* AC_INTMODE1_bm Predefined. */ ++/* AC_INTMODE1_bp Predefined. */ ++ ++/* AC_INTLVL_gm Predefined. */ ++/* AC_INTLVL_gp Predefined. */ ++/* AC_INTLVL0_bm Predefined. */ ++/* AC_INTLVL0_bp Predefined. */ ++/* AC_INTLVL1_bm Predefined. */ ++/* AC_INTLVL1_bp Predefined. */ ++ ++/* AC_HSMODE_bm Predefined. */ ++/* AC_HSMODE_bp Predefined. */ ++ ++/* AC_HYSMODE_gm Predefined. */ ++/* AC_HYSMODE_gp Predefined. */ ++/* AC_HYSMODE0_bm Predefined. */ ++/* AC_HYSMODE0_bp Predefined. */ ++/* AC_HYSMODE1_bm Predefined. */ ++/* AC_HYSMODE1_bp Predefined. */ ++ ++/* AC_ENABLE_bm Predefined. */ ++/* AC_ENABLE_bp Predefined. */ ++ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS_gm Predefined. */ ++/* AC_MUXPOS_gp Predefined. */ ++/* AC_MUXPOS0_bm Predefined. */ ++/* AC_MUXPOS0_bp Predefined. */ ++/* AC_MUXPOS1_bm Predefined. */ ++/* AC_MUXPOS1_bp Predefined. */ ++/* AC_MUXPOS2_bm Predefined. */ ++/* AC_MUXPOS2_bp Predefined. */ ++ ++/* AC_MUXNEG_gm Predefined. */ ++/* AC_MUXNEG_gp Predefined. */ ++/* AC_MUXNEG0_bm Predefined. */ ++/* AC_MUXNEG0_bp Predefined. */ ++/* AC_MUXNEG1_bm Predefined. */ ++/* AC_MUXNEG1_bp Predefined. */ ++/* AC_MUXNEG2_bm Predefined. */ ++/* AC_MUXNEG2_bp Predefined. */ ++ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ ++ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ ++ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ ++ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ ++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ ++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ ++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ ++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ ++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ ++ ++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ ++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ ++ ++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ ++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ ++ ++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ ++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ ++ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ ++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ ++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ ++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ ++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ ++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ ++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ ++ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ ++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ ++ ++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ ++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ ++ ++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ ++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ ++ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++ ++/* DAC - Digital/Analog Converter */ ++/* DAC.CTRLA bit masks and bit positions */ ++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ ++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ ++ ++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ ++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ ++ ++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ ++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ ++ ++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ ++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ ++ ++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define DAC_ENABLE_bp 0 /* Enable bit position. */ ++ ++ ++/* DAC.CTRLB bit masks and bit positions */ ++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ ++#define DAC_CHSEL_gp 5 /* Channel Select group position. */ ++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ ++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ ++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ ++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ ++ ++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ ++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ ++ ++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ ++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ ++ ++ ++/* DAC.CTRLC bit masks and bit positions */ ++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ ++#define DAC_REFSEL_gp 3 /* Reference Select group position. */ ++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ ++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ ++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ ++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ ++ ++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ ++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ ++ ++ ++/* DAC.EVCTRL bit masks and bit positions */ ++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ ++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ ++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ ++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ ++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ ++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ ++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ ++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ ++ ++ ++/* DAC.TIMCTRL bit masks and bit positions */ ++#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ ++#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ ++#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ ++#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ ++#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ ++#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ ++#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ ++#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ ++ ++#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ ++#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ ++#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ ++#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ ++#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ ++#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ ++#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ ++#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ ++#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ ++#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ ++ ++ ++/* DAC.STATUS bit masks and bit positions */ ++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ ++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ ++ ++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ ++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ ++ ++ ++/* RTC - Real-Time Clounter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* EBI - External Bus Interface */ ++/* EBI_CS.CTRLA bit masks and bit positions */ ++#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ ++#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ ++#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ ++#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ ++#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ ++#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ ++#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ ++#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ ++#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ ++#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ ++#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ ++#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ ++ ++#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ ++#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ ++#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ ++#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ ++#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ ++#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ ++ ++ ++/* EBI_CS.CTRLB bit masks and bit positions */ ++#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ ++#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ ++#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ ++#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ ++#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ ++#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ ++#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ ++#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ ++ ++#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ ++#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ ++ ++#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ ++#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ ++ ++#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ ++#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ ++#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ ++#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ ++#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ ++#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ ++ ++ ++/* EBI.CTRL bit masks and bit positions */ ++#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ ++#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ ++#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ ++#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ ++#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ ++#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ ++ ++#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ ++#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ ++#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ ++#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ ++#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ ++#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ ++ ++#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ ++#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ ++#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ ++#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ ++#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ ++#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ ++ ++#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ ++#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ ++#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ ++#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ ++#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ ++#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLA bit masks and bit positions */ ++#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ ++#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ ++ ++#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ ++#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ ++ ++#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ ++#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ ++#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ ++#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ ++#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ ++#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLB bit masks and bit positions */ ++#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ ++#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ ++#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ ++#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ ++#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ ++#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ ++ ++#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ ++#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ ++#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ ++#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ ++#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ ++#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ ++#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ ++#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ ++ ++#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ ++#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ ++#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ ++#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ ++#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ ++#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ ++#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ ++#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ ++ ++ ++/* EBI.SDRAMCTRLC bit masks and bit positions */ ++#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ ++#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ ++#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ ++#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ ++#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ ++#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ ++ ++#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ ++#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ ++#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ ++#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ ++#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ ++#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ ++#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ ++#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ ++ ++#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ ++#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ ++#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ ++#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ ++#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ ++#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ ++#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ ++#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ ++ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ ++#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++ ++/* PORT - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ ++#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ ++ ++#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD_gm Predefined. */ ++/* TC0_CMD_gp Predefined. */ ++/* TC0_CMD0_bm Predefined. */ ++/* TC0_CMD0_bp Predefined. */ ++/* TC0_CMD1_bm Predefined. */ ++/* TC0_CMD1_bp Predefined. */ ++ ++/* TC0_LUPD_bm Predefined. */ ++/* TC0_LUPD_bp Predefined. */ ++ ++/* TC0_DIR_bm Predefined. */ ++/* TC0_DIR_bp Predefined. */ ++ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV_bm Predefined. */ ++/* TC0_CCDBV_bp Predefined. */ ++ ++/* TC0_CCCBV_bm Predefined. */ ++/* TC0_CCCBV_bp Predefined. */ ++ ++/* TC0_CCBBV_bm Predefined. */ ++/* TC0_CCBBV_bp Predefined. */ ++ ++/* TC0_CCABV_bm Predefined. */ ++/* TC0_CCABV_bp Predefined. */ ++ ++/* TC0_PERBV_bm Predefined. */ ++/* TC0_PERBV_bp Predefined. */ ++ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ ++#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ ++ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD_gm Predefined. */ ++/* TC1_CMD_gp Predefined. */ ++/* TC1_CMD0_bm Predefined. */ ++/* TC1_CMD0_bp Predefined. */ ++/* TC1_CMD1_bm Predefined. */ ++/* TC1_CMD1_bp Predefined. */ ++ ++/* TC1_LUPD_bm Predefined. */ ++/* TC1_LUPD_bp Predefined. */ ++ ++/* TC1_DIR_bm Predefined. */ ++/* TC1_DIR_bp Predefined. */ ++ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV_bm Predefined. */ ++/* TC1_CCBBV_bp Predefined. */ ++ ++/* TC1_CCABV_bm Predefined. */ ++/* TC1_CCABV_bp Predefined. */ ++ ++/* TC1_PERBV_bm Predefined. */ ++/* TC1_PERBV_bp Predefined. */ ++ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL_gm Predefined. */ ++/* USART_BSEL_gp Predefined. */ ++/* USART_BSEL0_bm Predefined. */ ++/* USART_BSEL0_bp Predefined. */ ++/* USART_BSEL1_bm Predefined. */ ++/* USART_BSEL1_bp Predefined. */ ++/* USART_BSEL2_bm Predefined. */ ++/* USART_BSEL2_bp Predefined. */ ++/* USART_BSEL3_bm Predefined. */ ++/* USART_BSEL3_bp Predefined. */ ++ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++ ++/* AES - AES Module */ ++/* AES.CTRL bit masks and bit positions */ ++#define AES_START_bm 0x80 /* Start/Run bit mask. */ ++#define AES_START_bp 7 /* Start/Run bit position. */ ++ ++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ ++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ ++ ++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ ++#define AES_RESET_bp 5 /* AES Software Reset bit position. */ ++ ++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ ++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ ++ ++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ ++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ ++ ++ ++/* AES.STATUS bit masks and bit positions */ ++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ ++#define AES_ERROR_bp 7 /* AES Error bit position. */ ++ ++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ ++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ ++ ++ ++/* AES.INTCTRL bit masks and bit positions */ ++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define AES_INTLVL_gp 0 /* Interrupt level group position. */ ++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_XOSCF_vect_num 1 ++#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* DMA interrupt vectors */ ++#define DMA_CH0_vect_num 6 ++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ ++#define DMA_CH1_vect_num 7 ++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ ++#define DMA_CH2_vect_num 8 ++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ ++#define DMA_CH3_vect_num 9 ++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* USARTC1 interrupt vectors */ ++#define USARTC1_RXC_vect_num 28 ++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ ++#define USARTC1_DRE_vect_num 29 ++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ ++#define USARTC1_TXC_vect_num 30 ++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ ++ ++/* AES interrupt vectors */ ++#define AES_INT_vect_num 31 ++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* ACB interrupt vectors */ ++#define ACB_AC0_vect_num 36 ++#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ ++#define ACB_AC1_vect_num 37 ++#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ ++#define ACB_ACW_vect_num 38 ++#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ ++ ++/* ADCB interrupt vectors */ ++#define ADCB_CH0_vect_num 39 ++#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ ++#define ADCB_CH1_vect_num 40 ++#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ ++#define ADCB_CH2_vect_num 41 ++#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ ++#define ADCB_CH3_vect_num 42 ++#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* TCE1 interrupt vectors */ ++#define TCE1_OVF_vect_num 53 ++#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ ++#define TCE1_ERR_vect_num 54 ++#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ ++#define TCE1_CCA_vect_num 55 ++#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ ++#define TCE1_CCB_vect_num 56 ++#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ ++ ++/* SPIE interrupt vectors */ ++#define SPIE_INT_vect_num 57 ++#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* USARTE1 interrupt vectors */ ++#define USARTE1_RXC_vect_num 61 ++#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ ++#define USARTE1_DRE_vect_num 62 ++#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ ++#define USARTE1_TXC_vect_num 63 ++#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++#define ADCA_CH1_vect_num 72 ++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ ++#define ADCA_CH2_vect_num 73 ++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ ++#define ADCA_CH3_vect_num 74 ++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ ++ ++/* TWID interrupt vectors */ ++#define TWID_TWIS_vect_num 75 ++#define TWID_TWIS_vect _VECTOR(75) /* TWI Slave Interrupt */ ++#define TWID_TWIM_vect_num 76 ++#define TWID_TWIM_vect _VECTOR(76) /* TWI Master Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD1 interrupt vectors */ ++#define TCD1_OVF_vect_num 83 ++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ ++#define TCD1_ERR_vect_num 84 ++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ ++#define TCD1_CCA_vect_num 85 ++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ ++#define TCD1_CCB_vect_num 86 ++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* USARTD1 interrupt vectors */ ++#define USARTD1_RXC_vect_num 91 ++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ ++#define USARTD1_DRE_vect_num 92 ++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ ++#define USARTD1_TXC_vect_num 93 ++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ ++ ++/* PORTQ interrupt vectors */ ++#define PORTQ_INT0_vect_num 94 ++#define PORTQ_INT0_vect _VECTOR(94) /* External Interrupt 0 */ ++#define PORTQ_INT1_vect_num 95 ++#define PORTQ_INT1_vect _VECTOR(95) /* External Interrupt 1 */ ++ ++/* PORTH interrupt vectors */ ++#define PORTH_INT0_vect_num 96 ++#define PORTH_INT0_vect _VECTOR(96) /* External Interrupt 0 */ ++#define PORTH_INT1_vect_num 97 ++#define PORTH_INT1_vect _VECTOR(97) /* External Interrupt 1 */ ++ ++/* PORTJ interrupt vectors */ ++#define PORTJ_INT0_vect_num 98 ++#define PORTJ_INT0_vect _VECTOR(98) /* External Interrupt 0 */ ++#define PORTJ_INT1_vect_num 99 ++#define PORTJ_INT1_vect _VECTOR(99) /* External Interrupt 1 */ ++ ++/* PORTK interrupt vectors */ ++#define PORTK_INT0_vect_num 100 ++#define PORTK_INT0_vect _VECTOR(100) /* External Interrupt 0 */ ++#define PORTK_INT1_vect_num 101 ++#define PORTK_INT1_vect _VECTOR(101) /* External Interrupt 1 */ ++ ++/* PORTF interrupt vectors */ ++#define PORTF_INT0_vect_num 104 ++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ ++#define PORTF_INT1_vect_num 105 ++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ ++ ++/* TWIF interrupt vectors */ ++#define TWIF_TWIS_vect_num 106 ++#define TWIF_TWIS_vect _VECTOR(106) /* TWI Slave Interrupt */ ++#define TWIF_TWIM_vect_num 107 ++#define TWIF_TWIM_vect _VECTOR(107) /* TWI Master Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_OVF_vect_num 108 ++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ ++#define TCF0_ERR_vect_num 109 ++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ ++#define TCF0_CCA_vect_num 110 ++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ ++#define TCF0_CCB_vect_num 111 ++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ ++#define TCF0_CCC_vect_num 112 ++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ ++#define TCF0_CCD_vect_num 113 ++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ ++ ++/* TCF1 interrupt vectors */ ++#define TCF1_OVF_vect_num 114 ++#define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */ ++#define TCF1_ERR_vect_num 115 ++#define TCF1_ERR_vect _VECTOR(115) /* Error Interrupt */ ++#define TCF1_CCA_vect_num 116 ++#define TCF1_CCA_vect _VECTOR(116) /* Compare or Capture A Interrupt */ ++#define TCF1_CCB_vect_num 117 ++#define TCF1_CCB_vect _VECTOR(117) /* Compare or Capture B Interrupt */ ++ ++/* SPIF interrupt vectors */ ++#define SPIF_INT_vect_num 118 ++#define SPIF_INT_vect _VECTOR(118) /* SPI Interrupt */ ++ ++/* USARTF0 interrupt vectors */ ++#define USARTF0_RXC_vect_num 119 ++#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ ++#define USARTF0_DRE_vect_num 120 ++#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ ++#define USARTF0_TXC_vect_num 121 ++#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ ++ ++/* USARTF1 interrupt vectors */ ++#define USARTF1_RXC_vect_num 122 ++#define USARTF1_RXC_vect _VECTOR(122) /* Reception Complete Interrupt */ ++#define USARTF1_DRE_vect_num 123 ++#define USARTF1_DRE_vect _VECTOR(123) /* Data Register Empty Interrupt */ ++#define USARTF1_TXC_vect_num 124 ++#define USARTF1_TXC_vect _VECTOR(124) /* Transmission Complete Interrupt */ ++ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (125 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (139264) ++#define PROGMEM_PAGE_SIZE (512) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (131072) ++#define APP_SECTION_PAGE_SIZE (512) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x1E000) ++#define APPTABLE_SECTION_SIZE (8192) ++#define APPTABLE_SECTION_PAGE_SIZE (512) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x20000) ++#define BOOT_SECTION_SIZE (8192) ++#define BOOT_SECTION_PAGE_SIZE (512) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (16777216) ++#define DATAMEM_PAGE_SIZE (0) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (2048) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (8192) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EXTERNAL_SRAM_START (0x4000) ++#define EXTERNAL_SRAM_SIZE (16760832) ++#define EXTERNAL_SRAM_PAGE_SIZE (0) ++#define EXTERNAL_SRAM_END (EXTERNAL_SRAM_START + EXTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (2048) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define FUSE_START (0x0000) ++#define FUSE_SIZE (6) ++#define FUSE_PAGE_SIZE (0) ++#define FUSE_END (FUSE_START + FUSE_SIZE - 1) ++ ++#define LOCKBIT_START (0x0000) ++#define LOCKBIT_SIZE (1) ++#define LOCKBIT_PAGE_SIZE (0) ++#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (512) ++#define USER_SIGNATURES_PAGE_SIZE (0) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (0) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE PROGMEM_PAGE_SIZE ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define XRAMSTART EXTERNAL_SRAM_START ++#define XRAMSIZE EXTERNAL_SRAM_SIZE ++#define XRAMEND EXTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 */ ++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ ++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ ++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ ++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ ++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ ++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ ++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ ++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ ++#define FUSE0_DEFAULT (0xFF) ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_BODACT0 (unsigned char)~_BV(2) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(3) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE5_DEFAULT (0xFF) ++ ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x97 ++#define SIGNATURE_2 0x4C ++ ++ ++#endif /* _AVR_ATxmega128A1_H_ */ ++ +diff --git a/include/avr/iox128a1u.h b/include/avr/iox128a1u.h +index e8f4163..2068a2b 100644 +--- a/include/avr/iox128a1u.h ++++ b/include/avr/iox128a1u.h +@@ -1,7810 +1,8236 @@ +-/* Copyright (c) 2010 Atmel Corporation +- All rights reserved. +- - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - @@ -65193,226 +302636,550 @@ index e8f4163..0b61d9e 100644 -/* avr/iox128a1u.h - definitions for ATxmega128A1U */ - -/* This file should only be included from , never directly. */ - - #ifndef _AVR_IO_H_ - # error "Include instead of this file." -@@ -42,12 +40,10 @@ - # define _AVR_IOXXX_H_ "iox128a1u.h" - #else - # error "Attempt to include more than one file." +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iox128a1u.h" +-#else +-# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATxmega128A1U_H_ -#define _AVR_ATxmega128A1U_H_ 1 -+#endif - -+#ifndef _AVR_ATXMEGA128A1U_H_INCLUDED -+#define _AVR_ATXMEGA128A1U_H_INCLUDED - - /* Ungrouped common registers */ - #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -@@ -67,6 +63,24 @@ - #define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ - #define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -+#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -+#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -+#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -+#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -+#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -+#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -+#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -+#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -+#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -+#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -+#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ -+ - #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ - #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ - #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -@@ -77,7 +91,6 @@ - #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ - #define SREG _SFR_MEM8(0x003F) /* Status Register */ - - - /* C Language Only */ - #if !defined (__ASSEMBLER__) - -@@ -156,6 +169,12 @@ typedef struct OCD_struct - } OCD_t; - - -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ - /* CCP signatures */ - typedef enum CCP_enum - { -@@ -180,11 +199,6 @@ typedef struct CLK_struct - register8_t USBCTRL; /* USB Control Register */ - } CLK_t; - +- +-/* Ungrouped common registers */ +-#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +-#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +-#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +-#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +-#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +-#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +-#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +-#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +-#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +-#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +-#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +-#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +-#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +-#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +-#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +-#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +- +-#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +-#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +-#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +-#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +-#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +-#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +-#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +-#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +-#define SREG _SFR_MEM8(0x003F) /* Status Register */ +- +- +-/* C Language Only */ +-#if !defined (__ASSEMBLER__) +- +-#include +- +-typedef volatile uint8_t register8_t; +-typedef volatile uint16_t register16_t; +-typedef volatile uint32_t register32_t; +- +- +-#ifdef _WORDREGISTER +-#undef _WORDREGISTER +-#endif +-#define _WORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register16_t regname; \ +- struct \ +- { \ +- register8_t regname ## L; \ +- register8_t regname ## H; \ +- }; \ +- } +- +-#ifdef _DWORDREGISTER +-#undef _DWORDREGISTER +-#endif +-#define _DWORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register32_t regname; \ +- struct \ +- { \ +- register8_t regname ## 0; \ +- register8_t regname ## 1; \ +- register8_t regname ## 2; \ +- register8_t regname ## 3; \ +- }; \ +- } +- +- +-/* +-========================================================================== +-IO Module Structures +-========================================================================== +-*/ +- +- +-/* +--------------------------------------------------------------------------- +-VPORT - Virtual Ports +--------------------------------------------------------------------------- +-*/ +- +-/* Virtual Port */ +-typedef struct VPORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t OUT; /* I/O Port Output */ +- register8_t IN; /* I/O Port Input */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +-} VPORT_t; +- +- +-/* +--------------------------------------------------------------------------- +-XOCD - On-Chip Debug System +--------------------------------------------------------------------------- +-*/ +- +-/* On-Chip Debug System */ +-typedef struct OCD_struct +-{ +- register8_t OCDR0; /* OCD Register 0 */ +- register8_t OCDR1; /* OCD Register 1 */ +-} OCD_t; +- +- +-/* CCP signatures */ +-typedef enum CCP_enum +-{ +- CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ +- CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +-} CCP_t; +- +- -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - - /* Power Reduction */ - typedef struct PR_struct -@@ -258,6 +272,7 @@ typedef enum CLK_USBPSDIV_enum - typedef enum CLK_USBSRC_enum - { - CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ -+ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ - } CLK_USBSRC_t; - - -@@ -298,7 +313,7 @@ typedef struct OSC_struct - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ +- +-/* Clock System */ +-typedef struct CLK_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t PSCTRL; /* Prescaler Control Register */ +- register8_t LOCK; /* Lock register */ +- register8_t RTCCTRL; /* RTC Control Register */ +- register8_t USBCTRL; /* USB Control Register */ +-} CLK_t; +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Power Reduction */ +-typedef struct PR_struct +-{ +- register8_t PRGEN; /* General Power Reduction */ +- register8_t PRPA; /* Power Reduction Port A */ +- register8_t PRPB; /* Power Reduction Port B */ +- register8_t PRPC; /* Power Reduction Port C */ +- register8_t PRPD; /* Power Reduction Port D */ +- register8_t PRPE; /* Power Reduction Port E */ +- register8_t PRPF; /* Power Reduction Port F */ +-} PR_t; +- +-/* System Clock Selection */ +-typedef enum CLK_SCLKSEL_enum +-{ +- CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ +- CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ +- CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ +- CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ +- CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +-} CLK_SCLKSEL_t; +- +-/* Prescaler A Division Factor */ +-typedef enum CLK_PSADIV_enum +-{ +- CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ +- CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ +- CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ +- CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ +- CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ +- CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ +- CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ +- CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ +- CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ +- CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +-} CLK_PSADIV_t; +- +-/* Prescaler B and C Division Factor */ +-typedef enum CLK_PSBCDIV_enum +-{ +- CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ +- CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ +- CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ +- CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +-} CLK_PSBCDIV_t; +- +-/* RTC Clock Source */ +-typedef enum CLK_RTCSRC_enum +-{ +- CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ +- CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ +- CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ +- CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ +- CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ +- CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +-} CLK_RTCSRC_t; +- +-/* USB Prescaler Division Factor */ +-typedef enum CLK_USBPSDIV_enum +-{ +- CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ +- CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ +- CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ +- CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ +- CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ +- CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ +-} CLK_USBPSDIV_t; +- +-/* USB Clock Source */ +-typedef enum CLK_USBSRC_enum +-{ +- CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ +-} CLK_USBSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-SLEEP - Sleep Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Sleep Controller */ +-typedef struct SLEEP_struct +-{ +- register8_t CTRL; /* Control Register */ +-} SLEEP_t; +- +-/* Sleep Mode */ +-typedef enum SLEEP_SMODE_enum +-{ +- SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ +- SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +- SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ +- SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ +- SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +-} SLEEP_SMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-OSC - Oscillator +--------------------------------------------------------------------------- +-*/ +- +-/* Oscillator */ +-typedef struct OSC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t XOSCCTRL; /* External Oscillator Control Register */ +- register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ +- register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control REgister */ -+ register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ - } OSC_t; - -@@ -329,11 +344,19 @@ typedef enum OSC_PLLSRC_enum - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ - } OSC_PLLSRC_t; - +- register8_t DFLLCTRL; /* DFLL Control Register */ +-} OSC_t; +- +-/* Oscillator Frequency Range */ +-typedef enum OSC_FRQRANGE_enum +-{ +- OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ +- OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ +- OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ +- OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +-} OSC_FRQRANGE_t; +- +-/* External Oscillator Selection and Startup Time */ +-typedef enum OSC_XOSCSEL_enum +-{ +- OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ +- OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ +- OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ +- OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ +- OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ +-} OSC_XOSCSEL_t; +- +-/* PLL Clock Source */ +-typedef enum OSC_PLLSRC_enum +-{ +- OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ +- OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ +- OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +-} OSC_PLLSRC_t; +- -/* 32 MHz Calibration Reference */ -+/* 2 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC2MCREF_enum -+{ -+ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC2MCREF_t; -+ -+/* 32 MHz DFLL Calibration Reference */ - typedef enum OSC_RC32MCREF_enum - { - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ +-typedef enum OSC_RC32MCREF_enum +-{ +- OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ - } OSC_RC32MCREF_t; - - -@@ -392,9 +415,9 @@ typedef enum WDT_PER_enum - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +-} OSC_RC32MCREF_t; +- +- +-/* +--------------------------------------------------------------------------- +-DFLL - DFLL +--------------------------------------------------------------------------- +-*/ +- +-/* DFLL */ +-typedef struct DFLL_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t CALA; /* Calibration Register A */ +- register8_t CALB; /* Calibration Register B */ +- register8_t COMP0; /* Oscillator Compare Register 0 */ +- register8_t COMP1; /* Oscillator Compare Register 1 */ +- register8_t COMP2; /* Oscillator Compare Register 2 */ +- register8_t reserved_0x07; +-} DFLL_t; +- +- +-/* +--------------------------------------------------------------------------- +-RST - Reset +--------------------------------------------------------------------------- +-*/ +- +-/* Reset */ +-typedef struct RST_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t CTRL; /* Control Register */ +-} RST_t; +- +- +-/* +--------------------------------------------------------------------------- +-WDT - Watch-Dog Timer +--------------------------------------------------------------------------- +-*/ +- +-/* Watch-Dog Timer */ +-typedef struct WDT_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t WINCTRL; /* Windowed Mode Control */ +- register8_t STATUS; /* Status */ +-} WDT_t; +- +-/* Period setting */ +-typedef enum WDT_PER_enum +-{ +- WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ - WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ - WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -@@ -408,9 +431,9 @@ typedef enum WDT_WPER_enum - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_PER_t; +- +-/* Closed window period */ +-typedef enum WDT_WPER_enum +-{ +- WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ - WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ - WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -@@ -454,6 +477,19 @@ typedef struct PMIC_struct - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; - } PMIC_t; - - -@@ -471,6 +507,8 @@ typedef struct PORTCFG_struct - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ -+ register8_t EBIOUT; /* EBI Output register */ -+ register8_t EVOUTSEL; /* Event Output Select */ - } PORTCFG_t; - - /* Virtual Port Mapping */ -@@ -541,6 +579,44 @@ typedef enum PORTCFG_EVOUT_enum - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ - } PORTCFG_EVOUT_t; - -+/* Clock and Event Output Port */ -+typedef enum PORTCFG_CLKEVPIN_enum -+{ -+ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ -+ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -+} PORTCFG_CLKEVPIN_t; -+ -+/* EBI Address Output Port */ -+typedef enum PORTCFG_EBIADROUT_enum -+{ -+ PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ -+ PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ -+ PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ -+ PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ -+} PORTCFG_EBIADROUT_t; -+ -+/* EBI Chip Select Output Port */ -+typedef enum PORTCFG_EBICSOUT_enum -+{ -+ PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ -+} PORTCFG_EBICSOUT_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -+ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ -+ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ -+ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ -+ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ - - /* - -------------------------------------------------------------------------- -@@ -577,16 +653,17 @@ CRC - Cyclic Redundancy Checker - /* Cyclic Redundancy Checker */ - typedef struct CRC_struct - { +- WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_WPER_t; +- +- +-/* +--------------------------------------------------------------------------- +-MCU - MCU Control +--------------------------------------------------------------------------- +-*/ +- +-/* MCU Control */ +-typedef struct MCU_struct +-{ +- register8_t DEVID0; /* Device ID byte 0 */ +- register8_t DEVID1; /* Device ID byte 1 */ +- register8_t DEVID2; /* Device ID byte 2 */ +- register8_t REVID; /* Revision ID */ +- register8_t JTAGUID; /* JTAG User ID */ +- register8_t reserved_0x05; +- register8_t MCUCR; /* MCU Control */ +- register8_t ANAINIT; /* Analog Startup Delay */ +- register8_t EVSYSLOCK; /* Event System Lock */ +- register8_t AWEXLOCK; /* AWEX Lock */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +-} MCU_t; +- +- +-/* +--------------------------------------------------------------------------- +-PMIC - Programmable Multi-level Interrupt Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Programmable Multi-level Interrupt Controller */ +-typedef struct PMIC_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t INTPRI; /* Interrupt Priority */ +- register8_t CTRL; /* Control Register */ +-} PMIC_t; +- +- +-/* +--------------------------------------------------------------------------- +-PORTCFG - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O port Configuration */ +-typedef struct PORTCFG_struct +-{ +- register8_t MPCMASK; /* Multi-pin Configuration Mask */ +- register8_t reserved_0x01; +- register8_t VPCTRLA; /* Virtual Port Control Register A */ +- register8_t VPCTRLB; /* Virtual Port Control Register B */ +- register8_t CLKEVOUT; /* Clock and Event Out Register */ +-} PORTCFG_t; +- +-/* Virtual Port Mapping */ +-typedef enum PORTCFG_VP02MAP_enum +-{ +- PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP02MAP_t; +- +-/* Virtual Port Mapping */ +-typedef enum PORTCFG_VP13MAP_enum +-{ +- PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP13MAP_t; +- +-/* System Clock Output Port */ +-typedef enum PORTCFG_CLKOUT_enum +-{ +- PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ +- PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ +- PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ +- PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ +-} PORTCFG_CLKOUT_t; +- +-/* Peripheral Clock Output Select */ +-typedef enum PORTCFG_CLKOUTSEL_enum +-{ +- PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ +- PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ +- PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +-} PORTCFG_CLKOUTSEL_t; +- +-/* Event Output Port */ +-typedef enum PORTCFG_EVOUT_enum +-{ +- PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ +- PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ +- PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ +- PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +-} PORTCFG_EVOUT_t; +- +- +-/* +--------------------------------------------------------------------------- +-AES - AES Module +--------------------------------------------------------------------------- +-*/ +- +-/* AES Module */ +-typedef struct AES_struct +-{ +- register8_t CTRL; /* AES Control Register */ +- register8_t STATUS; /* AES Status Register */ +- register8_t STATE; /* AES State Register */ +- register8_t KEY; /* AES Key Register */ +- register8_t INTCTRL; /* AES Interrupt Control Register */ +-} AES_t; +- +-/* Interrupt level */ +-typedef enum AES_INTLVL_enum +-{ +- AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} AES_INTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-CRC - Cyclic Redundancy Checker +--------------------------------------------------------------------------- +-*/ +- +-/* Cyclic Redundancy Checker */ +-typedef struct CRC_struct +-{ - register8_t CTRL; /* CRC Control Register */ - register8_t STATUS; /* CRC Status Register */ - register8_t DATAIN; /* CRC Data Input */ @@ -65420,225 +303187,838 @@ index e8f4163..0b61d9e 100644 - register8_t CHECKSUM1; /* CRC Checksum byte 1 */ - register8_t CHECKSUM2; /* CRC Checksum byte 2 */ - register8_t CHECKSUM3; /* CRC Checksum byte 3 */ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ - } CRC_t; - +-} CRC_t; +- -/* CRC Reset */ -+/* Reset */ - typedef enum CRC_RESET_enum - { - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -@@ -594,10 +671,10 @@ typedef enum CRC_RESET_enum - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ - } CRC_RESET_t; - +-typedef enum CRC_RESET_enum +-{ +- CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ +- CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ +- CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +-} CRC_RESET_t; +- -/* CRC Input Source */ -+/* Input Source */ - typedef enum CRC_SOURCE_enum - { +-typedef enum CRC_SOURCE_enum +-{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* CRC Disabled */ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ -@@ -633,11 +710,6 @@ typedef struct DMA_CH_struct - register8_t reserved_0x0F; - } DMA_CH_t; - +- CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ +- CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ +- CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ +- CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ +- CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ +- CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ +-} CRC_SOURCE_t; +- +- -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - - /* DMA Controller */ - typedef struct DMA_struct -@@ -1037,8 +1109,8 @@ typedef struct NVM_struct - typedef enum NVM_CMD_enum - { - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ +- +-/* DMA Channel */ +-typedef struct DMA_CH_struct +-{ +- register8_t CTRLA; /* Channel Control */ +- register8_t CTRLB; /* Channel Control */ +- register8_t ADDRCTRL; /* Address Control */ +- register8_t TRIGSRC; /* Channel Trigger Source */ +- _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ +- register8_t REPCNT; /* Channel Repeat Count */ +- register8_t reserved_0x07; +- register8_t SRCADDR0; /* Channel Source Address 0 */ +- register8_t SRCADDR1; /* Channel Source Address 1 */ +- register8_t SRCADDR2; /* Channel Source Address 2 */ +- register8_t reserved_0x0B; +- register8_t DESTADDR0; /* Channel Destination Address 0 */ +- register8_t DESTADDR1; /* Channel Destination Address 1 */ +- register8_t DESTADDR2; /* Channel Destination Address 2 */ +- register8_t reserved_0x0F; +-} DMA_CH_t; +- +-/* +--------------------------------------------------------------------------- +-DMA - DMA Controller +--------------------------------------------------------------------------- +-*/ +- +-/* DMA Controller */ +-typedef struct DMA_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t reserved_0x01; +- register8_t reserved_0x02; +- register8_t INTFLAGS; /* Transfer Interrupt Status */ +- register8_t STATUS; /* Status */ +- register8_t reserved_0x05; +- _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- DMA_CH_t CH0; /* DMA Channel 0 */ +- DMA_CH_t CH1; /* DMA Channel 1 */ +- DMA_CH_t CH2; /* DMA Channel 2 */ +- DMA_CH_t CH3; /* DMA Channel 3 */ +-} DMA_t; +- +-/* Burst mode */ +-typedef enum DMA_CH_BURSTLEN_enum +-{ +- DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ +- DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ +- DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ +- DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +-} DMA_CH_BURSTLEN_t; +- +-/* Source address reload mode */ +-typedef enum DMA_CH_SRCRELOAD_enum +-{ +- DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ +- DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ +- DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ +- DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +-} DMA_CH_SRCRELOAD_t; +- +-/* Source addressing mode */ +-typedef enum DMA_CH_SRCDIR_enum +-{ +- DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ +- DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ +- DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +-} DMA_CH_SRCDIR_t; +- +-/* Destination adress reload mode */ +-typedef enum DMA_CH_DESTRELOAD_enum +-{ +- DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ +- DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ +- DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ +- DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +-} DMA_CH_DESTRELOAD_t; +- +-/* Destination adressing mode */ +-typedef enum DMA_CH_DESTDIR_enum +-{ +- DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ +- DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ +- DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +-} DMA_CH_DESTDIR_t; +- +-/* Transfer trigger source */ +-typedef enum DMA_CH_TRIGSRC_enum +-{ +- DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ +- DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ +- DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ +- DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ +- DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ +- DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ +- DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ +- DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ +- DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ +- DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ +- DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ +- DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ +- DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ +- DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ +- DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ +- DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ +- DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ +- DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ +- DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ +- DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ +- DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ +- DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ +- DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ +- DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ +- DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ +- DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ +- DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ +- DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ +- DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ +- DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ +- DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ +- DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ +- DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ +- DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ +- DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ +- DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ +- DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ +- DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ +- DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +-} DMA_CH_TRIGSRC_t; +- +-/* Double buffering mode */ +-typedef enum DMA_DBUFMODE_enum +-{ +- DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ +- DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ +- DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ +- DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +-} DMA_DBUFMODE_t; +- +-/* Priority mode */ +-typedef enum DMA_PRIMODE_enum +-{ +- DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ +- DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ +- DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ +- DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +-} DMA_PRIMODE_t; +- +-/* Interrupt level */ +-typedef enum DMA_CH_ERRINTLVL_enum +-{ +- DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ +- DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ +- DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +-} DMA_CH_ERRINTLVL_t; +- +-/* Interrupt level */ +-typedef enum DMA_CH_TRNINTLVL_enum +-{ +- DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ +- DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ +- DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +-} DMA_CH_TRNINTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-EVSYS - Event System +--------------------------------------------------------------------------- +-*/ +- +-/* Event System */ +-typedef struct EVSYS_struct +-{ +- register8_t CH0MUX; /* Event Channel 0 Multiplexer */ +- register8_t CH1MUX; /* Event Channel 1 Multiplexer */ +- register8_t CH2MUX; /* Event Channel 2 Multiplexer */ +- register8_t CH3MUX; /* Event Channel 3 Multiplexer */ +- register8_t CH4MUX; /* Event Channel 4 Multiplexer */ +- register8_t CH5MUX; /* Event Channel 5 Multiplexer */ +- register8_t CH6MUX; /* Event Channel 6 Multiplexer */ +- register8_t CH7MUX; /* Event Channel 7 Multiplexer */ +- register8_t CH0CTRL; /* Channel 0 Control Register */ +- register8_t CH1CTRL; /* Channel 1 Control Register */ +- register8_t CH2CTRL; /* Channel 2 Control Register */ +- register8_t CH3CTRL; /* Channel 3 Control Register */ +- register8_t CH4CTRL; /* Channel 4 Control Register */ +- register8_t CH5CTRL; /* Channel 5 Control Register */ +- register8_t CH6CTRL; /* Channel 6 Control Register */ +- register8_t CH7CTRL; /* Channel 7 Control Register */ +- register8_t STROBE; /* Event Strobe */ +- register8_t DATA; /* Event Data */ +-} EVSYS_t; +- +-/* Quadrature Decoder Index Recognition Mode */ +-typedef enum EVSYS_QDIRM_enum +-{ +- EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ +- EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ +- EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ +- EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +-} EVSYS_QDIRM_t; +- +-/* Digital filter coefficient */ +-typedef enum EVSYS_DIGFILT_enum +-{ +- EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ +- EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ +- EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ +- EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ +- EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ +- EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ +- EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ +- EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +-} EVSYS_DIGFILT_t; +- +-/* Event Channel multiplexer input selection */ +-typedef enum EVSYS_CHMUX_enum +-{ +- EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ +- EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ +- EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ +- EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ +- EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ +- EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ +- EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ +- EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ +- EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ +- EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ +- EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ +- EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ +- EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ +- EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ +- EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ +- EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ +- EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ +- EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ +- EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ +- EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ +- EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ +- EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ +- EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ +- EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ +- EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ +- EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ +- EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ +- EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ +- EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ +- EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ +- EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ +- EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ +- EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ +- EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ +- EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ +- EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ +- EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ +- EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ +- EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ +- EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ +- EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ +- EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ +- EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ +- EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ +- EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ +- EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ +- EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ +- EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ +- EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ +- EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ +- EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ +- EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ +- EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ +- EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ +- EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ +- EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ +- EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ +- EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ +- EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ +- EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ +- EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ +- EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ +- EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ +- EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ +- EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ +- EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ +- EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ +- EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ +- EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ +- EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ +- EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ +- EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ +- EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ +- EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ +- EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ +- EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ +- EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ +- EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ +- EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ +- EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ +- EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ +- EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ +- EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ +- EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ +- EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ +- EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ +- EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ +- EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ +- EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ +- EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ +- EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ +- EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ +- EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ +- EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ +- EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ +- EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ +- EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ +- EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ +- EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ +- EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ +- EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ +- EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ +- EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ +- EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ +- EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ +- EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ +- EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ +- EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ +- EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ +- EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ +- EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ +- EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +- EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ +- EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ +- EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ +- EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +-} EVSYS_CHMUX_t; +- +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Non-volatile Memory Controller */ +-typedef struct NVM_struct +-{ +- register8_t ADDR0; /* Address Register 0 */ +- register8_t ADDR1; /* Address Register 1 */ +- register8_t ADDR2; /* Address Register 2 */ +- register8_t reserved_0x03; +- register8_t DATA0; /* Data Register 0 */ +- register8_t DATA1; /* Data Register 1 */ +- register8_t DATA2; /* Data Register 2 */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t CMD; /* Command */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t INTCTRL; /* Interrupt Control */ +- register8_t reserved_0x0E; +- register8_t STATUS; /* Status */ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_t; +- +-/* NVM Command */ +-typedef enum NVM_CMD_enum +-{ +- NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ +- NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x03<<0), /* Read user signature row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -@@ -1062,13 +1134,14 @@ typedef enum NVM_CMD_enum - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ +- NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ +- NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ +- NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ +- NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ +- NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ +- NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ +- NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ +- NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ +- NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ +- NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ +- NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ +- NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ +- NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ +- NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ +- NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ +- NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ +- NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ +- NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ +- NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ +- NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ +- NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ +- NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ +- NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ +- NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ +- NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ +- NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ +- NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x78<<0), /* Generate Flash Range CRC */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ - } NVM_CMD_t; - - /* SPM ready interrupt level */ -@@ -1092,36 +1165,36 @@ typedef enum NVM_EELVL_enum - /* Boot lock bits - boot setcion */ - typedef enum NVM_BLBB_enum - { +-} NVM_CMD_t; +- +-/* SPM ready interrupt level */ +-typedef enum NVM_SPMLVL_enum +-{ +- NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ +- NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ +- NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +-} NVM_SPMLVL_t; +- +-/* EEPROM ready interrupt level */ +-typedef enum NVM_EELVL_enum +-{ +- NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ +- NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ +- NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +-} NVM_EELVL_t; +- +-/* Boot lock bits - boot setcion */ +-typedef enum NVM_BLBB_enum +-{ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ - } NVM_BLBB_t; - - /* Boot lock bits - application section */ - typedef enum NVM_BLBA_enum - { +- NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +-} NVM_BLBB_t; +- +-/* Boot lock bits - application section */ +-typedef enum NVM_BLBA_enum +-{ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ - } NVM_BLBA_t; - - /* Boot lock bits - application table section */ - typedef enum NVM_BLBAT_enum - { +- NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +-} NVM_BLBA_t; +- +-/* Boot lock bits - application table section */ +-typedef enum NVM_BLBAT_enum +-{ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ - } NVM_BLBAT_t; - - /* Lock bits */ - typedef enum NVM_LB_enum - { +- NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +-} NVM_BLBAT_t; +- +-/* Lock bits */ +-typedef enum NVM_LB_enum +-{ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ - } NVM_LB_t; - - -@@ -1136,17 +1209,13 @@ typedef struct ADC_CH_struct - { - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ -- register8_t INTCTRL; /* Channel Interrupt Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ -- register8_t reserved_0x7; -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t reserved_0x07; - } ADC_CH_t; - +- NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +-} NVM_LB_t; +- +- -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - - /* Analog-to-Digital Converter */ - typedef struct ADC_struct -@@ -1158,7 +1227,7 @@ typedef struct ADC_struct - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ +- +-/* ADC Channel */ +-typedef struct ADC_CH_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t MUXCTRL; /* MUX Control */ +- register8_t INTCTRL; /* Channel Interrupt Control */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- _WORDREGISTER(RES); /* Channel Result */ +- register8_t reserved_0x7; +-} ADC_CH_t; +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Analog-to-Digital Converter */ +-typedef struct ADC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t REFCTRL; /* Reference Control */ +- register8_t EVCTRL; /* Event Control */ +- register8_t PRESCALER; /* Clock Prescaler */ +- register8_t reserved_0x05; +- register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ -+ register8_t TEMP; /* Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; -@@ -1224,6 +1293,10 @@ typedef enum ADC_CH_MUXNEG_enum - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+ ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 3) */ -+ ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Groud (Input Mode = 3) */ -+ ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Groud (Input Mode = 4) */ -+ ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 4) */ - } ADC_CH_MUXNEG_t; - - /* Input mode */ -@@ -1245,7 +1318,7 @@ typedef enum ADC_CH_GAIN_enum - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- _WORDREGISTER(CAL); /* Calibration Value */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- _WORDREGISTER(CH0RES); /* Channel 0 Result */ +- _WORDREGISTER(CH1RES); /* Channel 1 Result */ +- _WORDREGISTER(CH2RES); /* Channel 2 Result */ +- _WORDREGISTER(CH3RES); /* Channel 3 Result */ +- _WORDREGISTER(CMP); /* Compare Value */ +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- ADC_CH_t CH0; /* ADC Channel 0 */ +- ADC_CH_t CH1; /* ADC Channel 1 */ +- ADC_CH_t CH2; /* ADC Channel 2 */ +- ADC_CH_t CH3; /* ADC Channel 3 */ +-} ADC_t; +- +-/* Positive input multiplexer selection */ +-typedef enum ADC_CH_MUXPOS_enum +-{ +- ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ +- ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ +- ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ +- ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ +- ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ +- ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ +- ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ +- ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +- ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ +- ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ +- ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ +- ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ +- ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ +- ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ +- ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ +- ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +-} ADC_CH_MUXPOS_t; +- +-/* Internal input multiplexer selections */ +-typedef enum ADC_CH_MUXINT_enum +-{ +- ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ +- ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ +- ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +- ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +-} ADC_CH_MUXINT_t; +- +-/* Negative input multiplexer selection */ +-typedef enum ADC_CH_MUXNEG_enum +-{ +- ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ +- ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ +- ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ +- ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ +- ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ +- ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ +- ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ +- ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ +-} ADC_CH_MUXNEG_t; +- +-/* Input mode */ +-typedef enum ADC_CH_INPUTMODE_enum +-{ +- ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ +- ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ +- ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ +- ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +-} ADC_CH_INPUTMODE_t; +- +-/* Gain factor */ +-typedef enum ADC_CH_GAIN_enum +-{ +- ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ +- ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ +- ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ +- ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ +- ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ +- ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ +- ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_128X_gc = (0x07<<2), /* 128x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ - } ADC_CH_GAIN_t; - - /* Conversion result resolution */ -@@ -1257,22 +1330,22 @@ typedef enum ADC_RESOLUTION_enum - } ADC_RESOLUTION_t; - - /* Current Limitation Mode */ +-} ADC_CH_GAIN_t; +- +-/* Conversion result resolution */ +-typedef enum ADC_RESOLUTION_enum +-{ +- ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ +- ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ +- ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +-} ADC_RESOLUTION_t; +- +-/* Current Limitation Mode */ -typedef enum ADC_CURRENT_enum -+typedef enum ADC_CURRLIMIT_enum - { +-{ - ADC_CURRENT_NO_gc = (0x00<<5), /* No Current Reduction */ - ADC_CURRENT_SMALL_gc = (0x01<<5), /* 10% current reduction */ - ADC_CURRENT_MEDIUM_gc = (0x02<<5), /* 20% current reduction */ - ADC_CURRENT_LARGE_gc = (0x03<<5), /* 30% current reduction */ -} ADC_CURRENT_t; -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ -+} ADC_CURRLIMIT_t; - - /* Voltage reference selection */ - typedef enum ADC_REFSEL_enum - { - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ +- +-/* Voltage reference selection */ +-typedef enum ADC_REFSEL_enum +-{ +- ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +- ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ +- ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ - } ADC_REFSEL_t; - - /* Channel sweep selection */ -@@ -1306,7 +1379,7 @@ typedef enum ADC_EVACT_enum - ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ - ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ - ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ +-} ADC_REFSEL_t; +- +-/* Channel sweep selection */ +-typedef enum ADC_SWEEP_enum +-{ +- ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ +- ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ +- ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ +- ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +-} ADC_SWEEP_t; +- +-/* Event channel input selection */ +-typedef enum ADC_EVSEL_enum +-{ +- ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ +- ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ +- ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ +- ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ +- ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ +- ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ +- ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ +- ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +-} ADC_EVSEL_t; +- +-/* Event action selection */ +-typedef enum ADC_EVACT_enum +-{ +- ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ +- ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ +- ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ +- ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ +- ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ +- ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ - ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ - } ADC_EVACT_t; - - /* Interupt mode */ -@@ -1362,7 +1435,7 @@ typedef struct DAC_struct - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ +-} ADC_EVACT_t; +- +-/* Interupt mode */ +-typedef enum ADC_CH_INTMODE_enum +-{ +- ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ +- ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ +- ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +-} ADC_CH_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum ADC_CH_INTLVL_enum +-{ +- ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ +- ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ +- ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +-} ADC_CH_INTLVL_t; +- +-/* DMA request selection */ +-typedef enum ADC_DMASEL_enum +-{ +- ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ +- ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ +- ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ +- ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +-} ADC_DMASEL_t; +- +-/* Clock prescaler */ +-typedef enum ADC_PRESCALER_enum +-{ +- ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ +- ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ +- ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ +- ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ +- ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ +- ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ +- ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ +- ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +-} ADC_PRESCALER_t; +- +- +-/* +--------------------------------------------------------------------------- +-DAC - Digital/Analog Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Digital-to-Analog Converter */ +-typedef struct DAC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t EVCTRL; /* Event Input Control */ - register8_t TIMCTRL; /* Timing Control */ -+ register8_t reserved_0x04; - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; -@@ -1416,38 +1489,6 @@ typedef enum DAC_EVSEL_enum - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ - } DAC_EVSEL_t; - +- register8_t STATUS; /* Status */ +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t CH0GAINCAL; /* Gain Calibration */ +- register8_t CH0OFFSETCAL; /* Offset Calibration */ +- register8_t CH1GAINCAL; /* Gain Calibration */ +- register8_t CH1OFFSETCAL; /* Offset Calibration */ +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- _WORDREGISTER(CH0DATA); /* Channel 0 Data */ +- _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +-} DAC_t; +- +-/* Output channel selection */ +-typedef enum DAC_CHSEL_enum +-{ +- DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ +- DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ +- DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ +-} DAC_CHSEL_t; +- +-/* Reference voltage selection */ +-typedef enum DAC_REFSEL_enum +-{ +- DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ +- DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ +- DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ +- DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +-} DAC_REFSEL_t; +- +-/* Event channel selection */ +-typedef enum DAC_EVSEL_enum +-{ +- DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ +- DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ +- DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ +- DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ +- DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ +- DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ +- DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ +- DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +-} DAC_EVSEL_t; +- -/* Conversion interval */ -typedef enum DAC_CONINTVAL_enum -{ @@ -65671,34 +304051,202 @@ index e8f4163..0b61d9e 100644 - DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ -} DAC_REFRESH_t; - - - /* - -------------------------------------------------------------------------- -@@ -1548,7 +1589,7 @@ typedef enum AC_WSTATE_enum - - /* - -------------------------------------------------------------------------- +- +-/* +--------------------------------------------------------------------------- +-AC - Analog Comparator +--------------------------------------------------------------------------- +-*/ +- +-/* Analog Comparator */ +-typedef struct AC_struct +-{ +- register8_t AC0CTRL; /* Analog Comparator 0 Control */ +- register8_t AC1CTRL; /* Analog Comparator 1 Control */ +- register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ +- register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t WINCTRL; /* Window Mode Control */ +- register8_t STATUS; /* Status */ +-} AC_t; +- +-/* Interrupt mode */ +-typedef enum AC_INTMODE_enum +-{ +- AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ +- AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ +- AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +-} AC_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum AC_INTLVL_enum +-{ +- AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ +- AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ +- AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ +- AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +-} AC_INTLVL_t; +- +-/* Hysteresis mode selection */ +-typedef enum AC_HYSMODE_enum +-{ +- AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ +- AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ +- AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +-} AC_HYSMODE_t; +- +-/* Positive input multiplexer selection */ +-typedef enum AC_MUXPOS_enum +-{ +- AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ +- AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ +- AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ +- AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ +- AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ +- AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ +- AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +- AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +-} AC_MUXPOS_t; +- +-/* Negative input multiplexer selection */ +-typedef enum AC_MUXNEG_enum +-{ +- AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ +- AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ +- AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ +- AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ +- AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ +- AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ +- AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ +- AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +-} AC_MUXNEG_t; +- +-/* Windows interrupt mode */ +-typedef enum AC_WINTMODE_enum +-{ +- AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ +- AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ +- AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ +- AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +-} AC_WINTMODE_t; +- +-/* Window interrupt level */ +-typedef enum AC_WINTLVL_enum +-{ +- AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ +- AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ +- AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +-} AC_WINTLVL_t; +- +-/* Window mode state */ +-typedef enum AC_WSTATE_enum +-{ +- AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ +- AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ +- AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +-} AC_WSTATE_t; +- +- +-/* +--------------------------------------------------------------------------- -RTC - Real-Time Clounter -+RTC - Real-Time Counter - -------------------------------------------------------------------------- - */ - -@@ -1614,11 +1655,6 @@ typedef struct EBI_CS_struct - _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ - } EBI_CS_t; - +--------------------------------------------------------------------------- +-*/ +- +-/* Real-Time Counter */ +-typedef struct RTC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t TEMP; /* Temporary register */ +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- _WORDREGISTER(CNT); /* Count Register */ +- _WORDREGISTER(PER); /* Period Register */ +- _WORDREGISTER(COMP); /* Compare Register */ +-} RTC_t; +- +-/* Prescaler Factor */ +-typedef enum RTC_PRESCALER_enum +-{ +- RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ +- RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ +- RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ +- RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ +- RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ +- RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ +- RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ +- RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +-} RTC_PRESCALER_t; +- +-/* Compare Interrupt level */ +-typedef enum RTC_COMPINTLVL_enum +-{ +- RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} RTC_COMPINTLVL_t; +- +-/* Overflow Interrupt level */ +-typedef enum RTC_OVFINTLVL_enum +-{ +- RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} RTC_OVFINTLVL_t; +- +- -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - - /* External Bus Interface */ - typedef struct EBI_struct -@@ -1644,28 +1680,28 @@ typedef struct EBI_struct - } EBI_t; - - /* Chip Select adress space */ +- +-/* EBI Chip Select Module */ +-typedef struct EBI_CS_struct +-{ +- register8_t CTRLA; /* Chip Select Control Register A */ +- register8_t CTRLB; /* Chip Select Control Register B */ +- _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +-} EBI_CS_t; +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* External Bus Interface */ +-typedef struct EBI_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t SDRAMCTRLA; /* SDRAM Control Register A */ +- register8_t reserved_0x02; +- register8_t reserved_0x03; +- _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ +- _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ +- register8_t SDRAMCTRLB; /* SDRAM Control Register B */ +- register8_t SDRAMCTRLC; /* SDRAM Control Register C */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- EBI_CS_t CS0; /* Chip Select 0 */ +- EBI_CS_t CS1; /* Chip Select 1 */ +- EBI_CS_t CS2; /* Chip Select 2 */ +- EBI_CS_t CS3; /* Chip Select 3 */ +-} EBI_t; +- +-/* Chip Select adress space */ -typedef enum EBI_CS_ASIZE_enum -{ - EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ @@ -65721,187 +304269,274 @@ index e8f4163..0b61d9e 100644 -} EBI_CS_ASIZE_t; - -/* */ -+typedef enum EBI_CS_ASPACE_enum -+{ -+ EBI_CS_ASPACE_256B_gc = (0x00<<2), /* 256 bytes */ -+ EBI_CS_ASPACE_512B_gc = (0x01<<2), /* 512 bytes */ -+ EBI_CS_ASPACE_1KB_gc = (0x02<<2), /* 1K bytes */ -+ EBI_CS_ASPACE_2KB_gc = (0x03<<2), /* 2K bytes */ -+ EBI_CS_ASPACE_4KB_gc = (0x04<<2), /* 4K bytes */ -+ EBI_CS_ASPACE_8KB_gc = (0x05<<2), /* 8K bytes */ -+ EBI_CS_ASPACE_16KB_gc = (0x06<<2), /* 16K bytes */ -+ EBI_CS_ASPACE_32KB_gc = (0x07<<2), /* 32K bytes */ -+ EBI_CS_ASPACE_64KB_gc = (0x08<<2), /* 64K bytes */ -+ EBI_CS_ASPACE_128KB_gc = (0x09<<2), /* 128K bytes */ -+ EBI_CS_ASPACE_256KB_gc = (0x0A<<2), /* 256K bytes */ -+ EBI_CS_ASPACE_512KB_gc = (0x0B<<2), /* 512K bytes */ -+ EBI_CS_ASPACE_1MB_gc = (0x0C<<2), /* 1M bytes */ -+ EBI_CS_ASPACE_2MB_gc = (0x0D<<2), /* 2M bytes */ -+ EBI_CS_ASPACE_4MB_gc = (0x0E<<2), /* 4M bytes */ -+ EBI_CS_ASPACE_8MB_gc = (0x0F<<2), /* 8M bytes */ -+ EBI_CS_ASPACE_16M_gc = (0x10<<2), /* 16M bytes */ -+} EBI_CS_ASPACE_t; -+ -+/* SRAM Wait State Selection */ - typedef enum EBI_CS_SRWS_enum - { - EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ -@@ -1673,7 +1709,7 @@ typedef enum EBI_CS_SRWS_enum - EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ +-typedef enum EBI_CS_SRWS_enum +-{ +- EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ -+ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycles */ - EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ - } EBI_CS_SRWS_t; -@@ -1735,7 +1771,7 @@ typedef enum EBI_SDCOL_enum - EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ - } EBI_SDCOL_t; - +- EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_CS_SRWS_t; +- +-/* Chip Select address mode */ +-typedef enum EBI_CS_MODE_enum +-{ +- EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ +- EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ +- EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ +- EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +-} EBI_CS_MODE_t; +- +-/* Chip Select SDRAM mode */ +-typedef enum EBI_CS_SDMODE_enum +-{ +- EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ +- EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +-} EBI_CS_SDMODE_t; +- -/* */ -+/* SDRAM Load Mode to Active delay */ - typedef enum EBI_MRDLY_enum - { - EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ -@@ -1744,7 +1780,7 @@ typedef enum EBI_MRDLY_enum - EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ - } EBI_MRDLY_t; - +-typedef enum EBI_SDDATAW_enum +-{ +- EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ +- EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +-} EBI_SDDATAW_t; +- -/* */ -+/* SDRAM Row Cycle Delay */ - typedef enum EBI_ROWCYCDLY_enum - { - EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ -@@ -1752,12 +1788,12 @@ typedef enum EBI_ROWCYCDLY_enum - EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +-typedef enum EBI_LPCMODE_enum +-{ +- EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ +- EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +-} EBI_LPCMODE_t; +- +-/* */ +-typedef enum EBI_SRMODE_enum +-{ +- EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ +- EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ +- EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ +- EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +-} EBI_SRMODE_t; +- +-/* */ +-typedef enum EBI_IFMODE_enum +-{ +- EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ +- EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ +- EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ +- EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +-} EBI_IFMODE_t; +- +-/* */ +-typedef enum EBI_SDCOL_enum +-{ +- EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ +- EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ +- EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ +- EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +-} EBI_SDCOL_t; +- +-/* */ +-typedef enum EBI_MRDLY_enum +-{ +- EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_MRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCYCDLY_enum +-{ +- EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ -+ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycles */ - EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ - } EBI_ROWCYCDLY_t; - +- EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ROWCYCDLY_t; +- -/* */ -+/* SDRAM Row to Precharge Delay */ - typedef enum EBI_RPDLY_enum - { - EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ -@@ -1765,12 +1801,12 @@ typedef enum EBI_RPDLY_enum - EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +-typedef enum EBI_RPDLY_enum +-{ +- EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ -+ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycles */ - EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ - } EBI_RPDLY_t; - +- EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_RPDLY_t; +- -/* */ -+/* SDRAM Write Recovery Delay */ - typedef enum EBI_WRDLY_enum - { - EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ -@@ -1779,7 +1815,7 @@ typedef enum EBI_WRDLY_enum - EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ - } EBI_WRDLY_t; - +-typedef enum EBI_WRDLY_enum +-{ +- EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_WRDLY_t; +- -/* */ -+/* SDRAM Exit Self Refresh to Active Delay */ - typedef enum EBI_ESRDLY_enum - { - EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ -@@ -1787,12 +1823,12 @@ typedef enum EBI_ESRDLY_enum - EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +-typedef enum EBI_ESRDLY_enum +-{ +- EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ -+ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycles */ - EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ - } EBI_ESRDLY_t; - +- EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ESRDLY_t; +- -/* */ -+/* SDRAM Row to Column Delay */ - typedef enum EBI_ROWCOLDLY_enum - { - EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ -@@ -1800,7 +1836,7 @@ typedef enum EBI_ROWCOLDLY_enum - EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +-typedef enum EBI_ROWCOLDLY_enum +-{ +- EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ -+ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycles */ - EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ - } EBI_ROWCOLDLY_t; -@@ -1824,11 +1860,6 @@ typedef struct TWI_MASTER_struct - register8_t DATA; /* Data Register */ - } TWI_MASTER_t; - +- EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_ROWCOLDLY_t; +- +- -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - - /* */ - typedef struct TWI_SLAVE_struct -@@ -1841,11 +1872,6 @@ typedef struct TWI_SLAVE_struct - register8_t ADDRMASK; /* Address Mask Register */ - } TWI_SLAVE_t; - +- +-/* */ +-typedef struct TWI_MASTER_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t STATUS; /* Status Register */ +- register8_t BAUD; /* Baurd Rate Control Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +-} TWI_MASTER_t; +- -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - - /* Two-Wire Interface */ - typedef struct TWI_struct -@@ -1908,10 +1934,19 @@ typedef enum TWI_SLAVE_CMD_enum - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ - } TWI_SLAVE_CMD_t; - -+/* SDA hold time */ -+typedef enum SDA_HOLD_TIME_enum -+{ -+ SDA_HOLD_TIME_OFF_gc = (0x00<<1), /* SDA hold time off */ -+ SDA_HOLD_TIME_50NS_gc = (0x01<<1), /* Typical 50ns hold time */ -+ SDA_HOLD_TIME_300NS_gc = (0x02<<1), /* Typical 300ns hold time */ -+ SDA_HOLD_TIME_400NS_gc = (0x03<<1), /* Typical 400ns hold time */ -+} SDA_HOLD_TIME_t; -+ - - /* - -------------------------------------------------------------------------- +- +-/* */ +-typedef struct TWI_SLAVE_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t STATUS; /* Status Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +- register8_t ADDRMASK; /* Address Mask Register */ +-} TWI_SLAVE_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Two-Wire Interface */ +-typedef struct TWI_struct +-{ +- register8_t CTRL; /* TWI Common Control Register */ +- TWI_MASTER_t MASTER; /* TWI master module */ +- TWI_SLAVE_t SLAVE; /* TWI slave module */ +-} TWI_t; +- +-/* Master Interrupt Level */ +-typedef enum TWI_MASTER_INTLVL_enum +-{ +- TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_MASTER_INTLVL_t; +- +-/* Inactive Timeout */ +-typedef enum TWI_MASTER_TIMEOUT_enum +-{ +- TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ +- TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ +- TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ +- TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +-} TWI_MASTER_TIMEOUT_t; +- +-/* Master Command */ +-typedef enum TWI_MASTER_CMD_enum +-{ +- TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ +- TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ +- TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +-} TWI_MASTER_CMD_t; +- +-/* Master Bus State */ +-typedef enum TWI_MASTER_BUSSTATE_enum +-{ +- TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ +- TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ +- TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ +- TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +-} TWI_MASTER_BUSSTATE_t; +- +-/* Slave Interrupt Level */ +-typedef enum TWI_SLAVE_INTLVL_enum +-{ +- TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_SLAVE_INTLVL_t; +- +-/* Slave Command */ +-typedef enum TWI_SLAVE_CMD_enum +-{ +- TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ +- TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +-} TWI_SLAVE_CMD_t; +- +- +-/* +--------------------------------------------------------------------------- -USB - USB Module -+USB - USB - -------------------------------------------------------------------------- - */ - -@@ -1920,66 +1955,13 @@ typedef struct USB_EP_struct - { - register8_t STATUS; /* Endpoint Status */ - register8_t CTRL; /* Endpoint Control */ +--------------------------------------------------------------------------- +-*/ +- +-/* USB Endpoint */ +-typedef struct USB_EP_struct +-{ +- register8_t STATUS; /* Endpoint Status */ +- register8_t CTRL; /* Endpoint Control */ - register8_t CNTL; /* USB Endpoint Counter Low Byte */ - register8_t CNTH; /* USB Endpoint Counter High Byte */ - register8_t DATAPTRL; /* Data Pointer Low Byte */ - register8_t DATAPTRH; /* Data Pointer High Byte */ - register8_t AUXDATAL; /* Auxiliary Data Low Byte */ - register8_t AUXDATAH; /* Auxiliary Data High Byte */ -+ _WORDREGISTER(CNT); /* USB Endpoint Counter */ -+ _WORDREGISTER(DATAPTR); /* Data Pointer */ -+ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ - } USB_EP_t; - +-} USB_EP_t; +- -/* --------------------------------------------------------------------------- -USB - USB Module --------------------------------------------------------------------------- -*/ - +- -/* USB Endpoint table */ -typedef struct USB_EP_TABLE_struct -{ @@ -65948,91 +304583,81 @@ index e8f4163..0b61d9e 100644 -*/ - -/* USB Module */ -+/* Universal Serial Bus */ - typedef struct USB_struct - { - register8_t CTRLA; /* Control Register A */ -@@ -2043,6 +2025,71 @@ typedef struct USB_struct - register8_t CAL1; /* Calibration Byte 1 */ - } USB_t; - -+ -+/* USB Endpoint Table */ -+typedef struct USB_EP_TABLE_struct -+{ -+ USB_EP_t EP0OUT; /* Endpoint 0 */ -+ USB_EP_t EP0IN; /* Endpoint 0 */ -+ USB_EP_t EP1OUT; /* Endpoint 1 */ -+ USB_EP_t EP1IN; /* Endpoint 1 */ -+ USB_EP_t EP2OUT; /* Endpoint 2 */ -+ USB_EP_t EP2IN; /* Endpoint 2 */ -+ USB_EP_t EP3OUT; /* Endpoint 3 */ -+ USB_EP_t EP3IN; /* Endpoint 3 */ -+ USB_EP_t EP4OUT; /* Endpoint 4 */ -+ USB_EP_t EP4IN; /* Endpoint 4 */ -+ USB_EP_t EP5OUT; /* Endpoint 5 */ -+ USB_EP_t EP5IN; /* Endpoint 5 */ -+ USB_EP_t EP6OUT; /* Endpoint 6 */ -+ USB_EP_t EP6IN; /* Endpoint 6 */ -+ USB_EP_t EP7OUT; /* Endpoint 7 */ -+ USB_EP_t EP7IN; /* Endpoint 7 */ -+ USB_EP_t EP8OUT; /* Endpoint 8 */ -+ USB_EP_t EP8IN; /* Endpoint 8 */ -+ USB_EP_t EP9OUT; /* Endpoint 9 */ -+ USB_EP_t EP9IN; /* Endpoint 9 */ -+ USB_EP_t EP10OUT; /* Endpoint 10 */ -+ USB_EP_t EP10IN; /* Endpoint 10 */ -+ USB_EP_t EP11OUT; /* Endpoint 11 */ -+ USB_EP_t EP11IN; /* Endpoint 11 */ -+ USB_EP_t EP12OUT; /* Endpoint 12 */ -+ USB_EP_t EP12IN; /* Endpoint 12 */ -+ USB_EP_t EP13OUT; /* Endpoint 13 */ -+ USB_EP_t EP13IN; /* Endpoint 13 */ -+ USB_EP_t EP14OUT; /* Endpoint 14 */ -+ USB_EP_t EP14IN; /* Endpoint 14 */ -+ USB_EP_t EP15OUT; /* Endpoint 15 */ -+ USB_EP_t EP15IN; /* Endpoint 15 */ -+ register8_t reserved_0x100; -+ register8_t reserved_0x101; -+ register8_t reserved_0x102; -+ register8_t reserved_0x103; -+ register8_t reserved_0x104; -+ register8_t reserved_0x105; -+ register8_t reserved_0x106; -+ register8_t reserved_0x107; -+ register8_t reserved_0x108; -+ register8_t reserved_0x109; -+ register8_t reserved_0x10A; -+ register8_t reserved_0x10B; -+ register8_t reserved_0x10C; -+ register8_t reserved_0x10D; -+ register8_t reserved_0x10E; -+ register8_t reserved_0x10F; -+ register8_t FRAMENUML; /* Frame Number Low Byte */ -+ register8_t FRAMENUMH; /* Frame Number High Byte */ -+} USB_EP_TABLE_t; -+ -+/* Interrupt level */ -+typedef enum USB_INTLVL_enum -+{ -+ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} USB_INTLVL_t; -+ - /* USB Endpoint Type */ - typedef enum USB_EP_TYPE_enum - { -@@ -2052,27 +2099,18 @@ typedef enum USB_EP_TYPE_enum - USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ - } USB_EP_TYPE_t; - +-typedef struct USB_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t STATUS; /* Status Register */ +- register8_t ADDR; /* Address Register */ +- register8_t FIFOWP; /* FIFO Write Pointer Register */ +- register8_t FIFORP; /* FIFO Read Pointer Register */ +- _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ +- register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ +- register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ +- register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- register8_t reserved_0x20; +- register8_t reserved_0x21; +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- register8_t reserved_0x26; +- register8_t reserved_0x27; +- register8_t reserved_0x28; +- register8_t reserved_0x29; +- register8_t reserved_0x2A; +- register8_t reserved_0x2B; +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t reserved_0x2E; +- register8_t reserved_0x2F; +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- register8_t reserved_0x36; +- register8_t reserved_0x37; +- register8_t reserved_0x38; +- register8_t reserved_0x39; +- register8_t CAL0; /* Calibration Byte 0 */ +- register8_t CAL1; /* Calibration Byte 1 */ +-} USB_t; +- +-/* USB Endpoint Type */ +-typedef enum USB_EP_TYPE_enum +-{ +- USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ +- USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ +- USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ +- USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ +-} USB_EP_TYPE_t; +- -/* USB Endpoint Buffer Size */ -typedef enum USB_EP_SIZE_enum -+/* USB Endpoint Buffersize */ -+typedef enum USB_EP_BUFSIZE_enum - { +-{ - USB_EP_SIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_SIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_SIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ @@ -66051,517 +304676,576 @@ index e8f4163..0b61d9e 100644 - USB_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} USB_INTLVL_t; -+ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ -+ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ -+ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ -+ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ -+ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ -+ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ -+ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ -+ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -+} USB_EP_BUFSIZE_t; - - - /* -@@ -2098,6 +2136,7 @@ typedef struct PORT_struct - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; -+ register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ -@@ -2215,11 +2254,6 @@ typedef struct TC0_struct - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ - } TC0_t; - +- +- +-/* +--------------------------------------------------------------------------- +-PORT - I/O Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O Ports */ +-typedef struct PORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t DIRSET; /* I/O Port Data Direction Set */ +- register8_t DIRCLR; /* I/O Port Data Direction Clear */ +- register8_t DIRTGL; /* I/O Port Data Direction Toggle */ +- register8_t OUT; /* I/O Port Output */ +- register8_t OUTSET; /* I/O Port Output Set */ +- register8_t OUTCLR; /* I/O Port Output Clear */ +- register8_t OUTTGL; /* I/O Port Output Toggle */ +- register8_t IN; /* I/O port Input */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INT0MASK; /* Port Interrupt 0 Mask */ +- register8_t INT1MASK; /* Port Interrupt 1 Mask */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0F; +- register8_t PIN0CTRL; /* Pin 0 Control Register */ +- register8_t PIN1CTRL; /* Pin 1 Control Register */ +- register8_t PIN2CTRL; /* Pin 2 Control Register */ +- register8_t PIN3CTRL; /* Pin 3 Control Register */ +- register8_t PIN4CTRL; /* Pin 4 Control Register */ +- register8_t PIN5CTRL; /* Pin 5 Control Register */ +- register8_t PIN6CTRL; /* Pin 6 Control Register */ +- register8_t PIN7CTRL; /* Pin 7 Control Register */ +-} PORT_t; +- +-/* Port Interrupt 0 Level */ +-typedef enum PORT_INT0LVL_enum +-{ +- PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ +- PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ +- PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +-} PORT_INT0LVL_t; +- +-/* Port Interrupt 1 Level */ +-typedef enum PORT_INT1LVL_enum +-{ +- PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ +- PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ +- PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +-} PORT_INT1LVL_t; +- +-/* Output/Pull Configuration */ +-typedef enum PORT_OPC_enum +-{ +- PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ +- PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ +- PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ +- PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ +- PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ +- PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ +- PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ +- PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +-} PORT_OPC_t; +- +-/* Input/Sense Configuration */ +-typedef enum PORT_ISC_enum +-{ +- PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ +- PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ +- PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ +- PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ +- PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +-} PORT_ISC_t; +- +- -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - - /* 16-bit Timer/Counter 1 */ - typedef struct TC1_struct -@@ -2305,12 +2339,24 @@ typedef enum TC_WGMODE_enum - { - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -- TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ -+ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - } TC_WGMODE_t; - -+/* Byte Mode */ -+typedef enum TC_BYTEM_enum -+{ -+ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ -+ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -+} TC_BYTEM_t; -+ - /* Event Action */ - typedef enum TC_EVACT_enum - { -@@ -2403,6 +2449,165 @@ typedef enum TC_CMD_enum - - /* - -------------------------------------------------------------------------- -+TC2 - 16-bit Timer/Counter type 2 -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter type 2 */ -+typedef struct TC2_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t reserved_0x03; -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t reserved_0x08; -+ register8_t CTRLF; /* Control Register F */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t LCNT; /* Low Byte Count */ -+ register8_t HCNT; /* High Byte Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t LPER; /* Low Byte Period */ -+ register8_t HPER; /* High Byte Period */ -+ register8_t LCMPA; /* Low Byte Compare A */ -+ register8_t HCMPA; /* High Byte Compare A */ -+ register8_t LCMPB; /* Low Byte Compare B */ -+ register8_t HCMPB; /* High Byte Compare B */ -+ register8_t LCMPC; /* Low Byte Compare C */ -+ register8_t HCMPC; /* High Byte Compare C */ -+ register8_t LCMPD; /* Low Byte Compare D */ -+ register8_t HCMPD; /* High Byte Compare D */ -+} TC2_t; -+ -+/* Clock Selection */ -+typedef enum TC2_CLKSEL_enum -+{ -+ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC2_CLKSEL_t; -+ -+/* Byte Mode */ -+typedef enum TC2_BYTEM_enum -+{ -+ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ -+ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -+} TC2_BYTEM_t; -+ -+/* High Byte Underflow Interrupt Level */ -+typedef enum TC2_HUNFINTLVL_enum -+{ -+ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_HUNFINTLVL_t; -+ -+/* Low Byte Underflow Interrupt Level */ -+typedef enum TC2_LUNFINTLVL_enum -+{ -+ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LUNFINTLVL_t; -+ -+/* Low Byte Compare D Interrupt Level */ -+typedef enum TC2_LCMPDINTLVL_enum -+{ -+ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC2_LCMPDINTLVL_t; -+ -+/* Low Byte Compare C Interrupt Level */ -+typedef enum TC2_LCMPCINTLVL_enum -+{ -+ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC2_LCMPCINTLVL_t; -+ -+/* Low Byte Compare B Interrupt Level */ -+typedef enum TC2_LCMPBINTLVL_enum -+{ -+ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_LCMPBINTLVL_t; -+ -+/* Low Byte Compare A Interrupt Level */ -+typedef enum TC2_LCMPAINTLVL_enum -+{ -+ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LCMPAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMD_enum -+{ -+ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC2_CMD_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMDEN_enum -+{ -+ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ -+ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ -+ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -+} TC2_CMDEN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- - AWEX - Timer/Counter Advanced Waveform Extension - -------------------------------------------------------------------------- - */ -@@ -2415,7 +2620,7 @@ typedef struct AWEX_struct - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ +- +-/* 16-bit Timer/Counter 0 */ +-typedef struct TC0_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; -+ register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ -@@ -2604,97 +2809,318 @@ typedef enum IRDA_EVSEL_enum - - /* - -------------------------------------------------------------------------- +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- _WORDREGISTER(CCC); /* Compare or Capture C */ +- _WORDREGISTER(CCD); /* Compare or Capture D */ +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +- _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ +- _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +-} TC0_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 1 */ +-typedef struct TC1_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t reserved_0x2E; +- register8_t reserved_0x2F; +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +-} TC1_t; +- +-/* Clock Selection */ +-typedef enum TC_CLKSEL_enum +-{ +- TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ +- TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ +- TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ +- TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ +- TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ +- TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ +- TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ +- TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ +- TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_CLKSEL_t; +- +-/* Waveform Generation Mode */ +-typedef enum TC_WGMODE_enum +-{ +- TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ +- TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ +- TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ +- TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ +- TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ +- TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +-} TC_WGMODE_t; +- +-/* Event Action */ +-typedef enum TC_EVACT_enum +-{ +- TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ +- TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ +- TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ +- TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ +- TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ +- TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ +- TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +-} TC_EVACT_t; +- +-/* Event Selection */ +-typedef enum TC_EVSEL_enum +-{ +- TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_EVSEL_t; +- +-/* Error Interrupt Level */ +-typedef enum TC_ERRINTLVL_enum +-{ +- TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_ERRINTLVL_t; +- +-/* Overflow Interrupt Level */ +-typedef enum TC_OVFINTLVL_enum +-{ +- TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_OVFINTLVL_t; +- +-/* Compare or Capture D Interrupt Level */ +-typedef enum TC_CCDINTLVL_enum +-{ +- TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TC_CCDINTLVL_t; +- +-/* Compare or Capture C Interrupt Level */ +-typedef enum TC_CCCINTLVL_enum +-{ +- TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} TC_CCCINTLVL_t; +- +-/* Compare or Capture B Interrupt Level */ +-typedef enum TC_CCBINTLVL_enum +-{ +- TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_CCBINTLVL_t; +- +-/* Compare or Capture A Interrupt Level */ +-typedef enum TC_CCAINTLVL_enum +-{ +- TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_CCAINTLVL_t; +- +-/* Timer/Counter Command */ +-typedef enum TC_CMD_enum +-{ +- TC_CMD_NONE_gc = (0x00<<2), /* No Command */ +- TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ +- TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ +- TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +-} TC_CMD_t; +- +- +-/* +--------------------------------------------------------------------------- +-AWEX - Timer/Counter Advanced Waveform Extension +--------------------------------------------------------------------------- +-*/ +- +-/* Advanced Waveform Extension */ +-typedef struct AWEX_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t FDEMASK; /* Fault Detection Event Mask */ +- register8_t FDCTRL; /* Fault Detection Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x05; +- register8_t DTBOTH; /* Dead Time Both Sides */ +- register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ +- register8_t DTLS; /* Dead Time Low Side */ +- register8_t DTHS; /* Dead Time High Side */ +- register8_t DTLSBUF; /* Dead Time Low Side Buffer */ +- register8_t DTHSBUF; /* Dead Time High Side Buffer */ +- register8_t OUTOVEN; /* Output Override Enable */ +-} AWEX_t; +- +-/* Fault Detect Action */ +-typedef enum AWEX_FDACT_enum +-{ +- AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ +- AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ +- AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +-} AWEX_FDACT_t; +- +- +-/* +--------------------------------------------------------------------------- +-HIRES - Timer/Counter High-Resolution Extension +--------------------------------------------------------------------------- +-*/ +- +-/* High-Resolution Extension */ +-typedef struct HIRES_struct +-{ +- register8_t CTRLA; /* Control Register */ +-} HIRES_t; +- +-/* High Resolution Enable */ +-typedef enum HIRES_HREN_enum +-{ +- HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ +- HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ +- HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ +- HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +-} HIRES_HREN_t; +- +- +-/* +--------------------------------------------------------------------------- +-USART - Universal Asynchronous Receiver-Transmitter +--------------------------------------------------------------------------- +-*/ +- +-/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +-typedef struct USART_struct +-{ +- register8_t DATA; /* Data Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x02; +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t BAUDCTRLA; /* Baud Rate Control Register A */ +- register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +-} USART_t; +- +-/* Receive Complete Interrupt level */ +-typedef enum USART_RXCINTLVL_enum +-{ +- USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} USART_RXCINTLVL_t; +- +-/* Transmit Complete Interrupt level */ +-typedef enum USART_TXCINTLVL_enum +-{ +- USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} USART_TXCINTLVL_t; +- +-/* Data Register Empty Interrupt level */ +-typedef enum USART_DREINTLVL_enum +-{ +- USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} USART_DREINTLVL_t; +- +-/* Character Size */ +-typedef enum USART_CHSIZE_enum +-{ +- USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ +- USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ +- USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ +- USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ +- USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +-} USART_CHSIZE_t; +- +-/* Communication Mode */ +-typedef enum USART_CMODE_enum +-{ +- USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ +- USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ +- USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ +- USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +-} USART_CMODE_t; +- +-/* Parity Mode */ +-typedef enum USART_PMODE_enum +-{ +- USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ +- USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ +- USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +-} USART_PMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-SPI - Serial Peripheral Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Serial Peripheral Interface */ +-typedef struct SPI_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t DATA; /* Data Register */ +-} SPI_t; +- +-/* SPI Mode */ +-typedef enum SPI_MODE_enum +-{ +- SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ +- SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ +- SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ +- SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +-} SPI_MODE_t; +- +-/* Prescaler setting */ +-typedef enum SPI_PRESCALER_enum +-{ +- SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ +- SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ +- SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ +- SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +-} SPI_PRESCALER_t; +- +-/* Interrupt level */ +-typedef enum SPI_INTLVL_enum +-{ +- SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} SPI_INTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-IRCOM - IR Communication Module +--------------------------------------------------------------------------- +-*/ +- +-/* IR Communication Module */ +-typedef struct IRCOM_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ +- register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +-} IRCOM_t; +- +-/* Event channel selection */ +-typedef enum IRDA_EVSEL_enum +-{ +- IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ +- IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ +- IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ +- IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +- IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ +- IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ +- IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ +- IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +-} IRDA_EVSEL_t; +- +- +-/* +--------------------------------------------------------------------------- -PRESC - Prescaler -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t FUSEBYTE0; /* JTAG User ID */ -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+} NVM_FUSES_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* Timer Oscillator pin location */ -+typedef enum TOSCSEL_enum -+{ -+ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ -+ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -+} TOSCSEL_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -+} BOD_t; -+ -+/* BOD operation */ -+typedef enum BODACT_enum -+{ -+ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BODACT_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WDP_enum -+{ -+ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ -+ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ -+ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ -+ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ -+ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ -+ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ -+ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ -+ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ -+ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ -+ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ -+ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -+} WDP_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LOCKBIT - Fuses and Lockbits - -------------------------------------------------------------------------- - */ - +--------------------------------------------------------------------------- +-*/ +- -/* Prescaler */ -typedef struct PRESC_struct -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum - { +-{ - register8_t PRESCALER; /* Control Register */ -} PRESC_t; -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; - -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; - - - /* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ -+ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t USBCAL0; /* USB Calibration Byte 0 */ -+ register8_t USBCAL1; /* USB Calibration Byte 1 */ -+ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ -+ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ -+ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ -+ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ -+ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ -+ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ -+ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ -+ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ -+ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ -+ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+ register8_t reserved_0x40; -+ register8_t reserved_0x41; -+ register8_t reserved_0x42; -+ register8_t reserved_0x43; -+ register8_t reserved_0x44; -+ register8_t reserved_0x45; -+ register8_t reserved_0x46; -+ register8_t reserved_0x47; -+} NVM_PROD_SIGNATURES_t; -+ -+/* - ========================================================================== - IO Module Instances. Mapped to memory. - ========================================================================== - */ - +- +- +- +-/* +-========================================================================== +-IO Module Instances. Mapped to memory. +-========================================================================== +-*/ +- -#define USB_EP_TABLE (*(USB_EP_TABLE_t *) ) /* Universal Serial Bus Module */ -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ - #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ - #define CLK (*(CLK_t *) 0x0040) /* Clock System */ - #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +-#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +-#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +-#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ - #define PR (*(PR_t *) 0x0070) /* Power Reduction */ +-#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset Controller */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ - #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ - #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +-#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +-#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ -#define CRC (*(CRC_t *) 0x00D0) /* CRC Module */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define AES (*(AES_t *) 0x00C0) /* AES Module */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ - #define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ - #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +-#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +-#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ -#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ @@ -66569,15 +305253,8 @@ index e8f4163..0b61d9e 100644 -#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ -#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ -+#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ -+#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ - #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ - #define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */ +-#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +-#define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ -#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface D */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ @@ -66601,31 +305278,7 @@ index e8f4163..0b61d9e 100644 -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -+#define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface */ -+#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -+#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -+#define PORTH (*(PORT_t *) 0x06E0) /* I/O Ports */ -+#define PORTJ (*(PORT_t *) 0x0700) /* I/O Ports */ -+#define PORTK (*(PORT_t *) 0x0720) /* I/O Ports */ -+#define PORTQ (*(PORT_t *) 0x07C0) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -+#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -+#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ - #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +-#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ -#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ -#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ @@ -66645,35 +305298,13 @@ index e8f4163..0b61d9e 100644 -#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ -#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ -#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ -+#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -+#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -+#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ -+#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ -+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -+#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -+#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -+#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ -+#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ -+#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ -+#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ -+#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -+#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ -+#define TCF1 (*(TC1_t *) 0x0B40) /* 16-bit Timer/Counter 1 */ -+#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ -+#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface */ - - - #endif /* !defined (__ASSEMBLER__) */ -@@ -2702,266 +3128,6 @@ IO Module Instances. Mapped to memory. - - /* ========== Flattened fully qualified IO register names ========== */ - +- +- +-#endif /* !defined (__ASSEMBLER__) */ +- +- +-/* ========== Flattened fully qualified IO register names ========== */ +- -/* USB_EP_TABLE - Universal Serial Bus Module */ -#define USB_EP_TABLE_EP0OUT_STATUS _SFR_MEM8(0x0000) -#define USB_EP_TABLE_EP0OUT_CTRL _SFR_MEM8(0x0001) @@ -66934,1143 +305565,1440 @@ index e8f4163..0b61d9e 100644 -#define USB_EP_TABLE_FRAMENUML _SFR_MEM8(0x0110) -#define USB_EP_TABLE_FRAMENUMH _SFR_MEM8(0x0111) - - /* GPIO - General Purpose IO Registers */ - #define GPIO_GPIOR0 _SFR_MEM8(0x0000) - #define GPIO_GPIOR1 _SFR_MEM8(0x0001) -@@ -2980,25 +3146,89 @@ IO Module Instances. Mapped to memory. - #define GPIO_GPIORE _SFR_MEM8(0x000E) - #define GPIO_GPIORF _SFR_MEM8(0x000F) - --/* VPORT0 - Virtual Port 0 */ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+#define GPIO_GPIO4 _SFR_MEM8(0x0004) -+#define GPIO_GPIO5 _SFR_MEM8(0x0005) -+#define GPIO_GPIO6 _SFR_MEM8(0x0006) -+#define GPIO_GPIO7 _SFR_MEM8(0x0007) -+#define GPIO_GPIO8 _SFR_MEM8(0x0008) -+#define GPIO_GPIO9 _SFR_MEM8(0x0009) -+#define GPIO_GPIOA _SFR_MEM8(0x000A) -+#define GPIO_GPIOB _SFR_MEM8(0x000B) -+#define GPIO_GPIOC _SFR_MEM8(0x000C) -+#define GPIO_GPIOD _SFR_MEM8(0x000D) -+#define GPIO_GPIOE _SFR_MEM8(0x000E) -+#define GPIO_GPIOF _SFR_MEM8(0x000F) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -+#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -+#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -+#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -+#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -+#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -+#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) -+#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) -+#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -+#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) -+#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) -+#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) -+ -+/* VPORT - Virtual Port */ - #define VPORT0_DIR _SFR_MEM8(0x0010) - #define VPORT0_OUT _SFR_MEM8(0x0011) - #define VPORT0_IN _SFR_MEM8(0x0012) - #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - --/* VPORT1 - Virtual Port 1 */ -+/* VPORT - Virtual Port */ - #define VPORT1_DIR _SFR_MEM8(0x0014) - #define VPORT1_OUT _SFR_MEM8(0x0015) - #define VPORT1_IN _SFR_MEM8(0x0016) - #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - --/* VPORT2 - Virtual Port 2 */ -+/* VPORT - Virtual Port */ - #define VPORT2_DIR _SFR_MEM8(0x0018) - #define VPORT2_OUT _SFR_MEM8(0x0019) - #define VPORT2_IN _SFR_MEM8(0x001A) - #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - --/* VPORT3 - Virtual Port 3 */ -+/* VPORT - Virtual Port */ - #define VPORT3_DIR _SFR_MEM8(0x001C) - #define VPORT3_OUT _SFR_MEM8(0x001D) - #define VPORT3_IN _SFR_MEM8(0x001E) -@@ -3008,7 +3238,7 @@ IO Module Instances. Mapped to memory. - #define OCD_OCDR0 _SFR_MEM8(0x002E) - #define OCD_OCDR1 _SFR_MEM8(0x002F) - --/* CPU - CPU Registers */ -+/* CPU - CPU registers */ - #define CPU_CCP _SFR_MEM8(0x0034) - #define CPU_RAMPD _SFR_MEM8(0x0038) - #define CPU_RAMPX _SFR_MEM8(0x0039) -@@ -3029,16 +3259,16 @@ IO Module Instances. Mapped to memory. - /* SLEEP - Sleep Controller */ - #define SLEEP_CTRL _SFR_MEM8(0x0048) - --/* OSC - Oscillator Control */ -+/* OSC - Oscillator */ - #define OSC_CTRL _SFR_MEM8(0x0050) - #define OSC_STATUS _SFR_MEM8(0x0051) - #define OSC_XOSCCTRL _SFR_MEM8(0x0052) --#define OSC_XOSCFAIL _SFR_MEM8(0x005F) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) - #define OSC_RC32KCAL _SFR_MEM8(0x0054) - #define OSC_PLLCTRL _SFR_MEM8(0x0055) - #define OSC_DFLLCTRL _SFR_MEM8(0x0056) - --/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ -+/* DFLL - DFLL */ - #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) - #define DFLLRC32M_CALA _SFR_MEM8(0x0062) - #define DFLLRC32M_CALB _SFR_MEM8(0x0063) -@@ -3046,7 +3276,7 @@ IO Module Instances. Mapped to memory. - #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) - #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - --/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ -+/* DFLL - DFLL */ - #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) - #define DFLLRC2M_CALA _SFR_MEM8(0x006A) - #define DFLLRC2M_CALB _SFR_MEM8(0x006B) -@@ -3063,7 +3293,7 @@ IO Module Instances. Mapped to memory. - #define PR_PRPE _SFR_MEM8(0x0075) - #define PR_PRPF _SFR_MEM8(0x0076) - --/* RST - Reset Controller */ -+/* RST - Reset */ - #define RST_STATUS _SFR_MEM8(0x0078) - #define RST_CTRL _SFR_MEM8(0x0079) - -@@ -3083,25 +3313,27 @@ IO Module Instances. Mapped to memory. - #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) - #define MCU_AWEXLOCK _SFR_MEM8(0x0099) - --/* PMIC - Programmable Interrupt Controller */ -+/* PMIC - Programmable Multi-level Interrupt Controller */ - #define PMIC_STATUS _SFR_MEM8(0x00A0) - #define PMIC_INTPRI _SFR_MEM8(0x00A1) - #define PMIC_CTRL _SFR_MEM8(0x00A2) - --/* PORTCFG - Port Configuration */ -+/* PORTCFG - I/O port Configuration */ - #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) - #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) - #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) - #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) -+#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - --/* AES - AES Crypto Module */ -+/* AES - AES Module */ - #define AES_CTRL _SFR_MEM8(0x00C0) - #define AES_STATUS _SFR_MEM8(0x00C1) - #define AES_STATE _SFR_MEM8(0x00C2) - #define AES_KEY _SFR_MEM8(0x00C3) - #define AES_INTCTRL _SFR_MEM8(0x00C4) - --/* CRC - CRC Module */ -+/* CRC - Cyclic Redundancy Checker */ - #define CRC_CTRL _SFR_MEM8(0x00D0) - #define CRC_STATUS _SFR_MEM8(0x00D1) - #define CRC_DATAIN _SFR_MEM8(0x00D3) -@@ -3184,7 +3416,7 @@ IO Module Instances. Mapped to memory. - #define EVSYS_STROBE _SFR_MEM8(0x0190) - #define EVSYS_DATA _SFR_MEM8(0x0191) - --/* NVM - Non Volatile Memory Controller */ -+/* NVM - Non-volatile Memory Controller */ - #define NVM_ADDR0 _SFR_MEM8(0x01C0) - #define NVM_ADDR1 _SFR_MEM8(0x01C1) - #define NVM_ADDR2 _SFR_MEM8(0x01C2) -@@ -3198,7 +3430,7 @@ IO Module Instances. Mapped to memory. - #define NVM_STATUS _SFR_MEM8(0x01CF) - #define NVM_LOCKBITS _SFR_MEM8(0x01D0) - --/* ADCA - Analog to Digital Converter A */ -+/* ADC - Analog-to-Digital Converter */ - #define ADCA_CTRLA _SFR_MEM8(0x0200) - #define ADCA_CTRLB _SFR_MEM8(0x0201) - #define ADCA_REFCTRL _SFR_MEM8(0x0202) -@@ -3217,23 +3449,27 @@ IO Module Instances. Mapped to memory. - #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) - #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) - #define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) - #define ADCA_CH1_CTRL _SFR_MEM8(0x0228) - #define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) - #define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) - #define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) - #define ADCA_CH1_RES _SFR_MEM16(0x022C) -+#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) - #define ADCA_CH2_CTRL _SFR_MEM8(0x0230) - #define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) - #define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) - #define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) - #define ADCA_CH2_RES _SFR_MEM16(0x0234) -+#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) - #define ADCA_CH3_CTRL _SFR_MEM8(0x0238) - #define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) - #define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) - #define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) - #define ADCA_CH3_RES _SFR_MEM16(0x023C) -+#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) - --/* ADCB - Analog to Digital Converter B */ -+/* ADC - Analog-to-Digital Converter */ - #define ADCB_CTRLA _SFR_MEM8(0x0240) - #define ADCB_CTRLB _SFR_MEM8(0x0241) - #define ADCB_REFCTRL _SFR_MEM8(0x0242) -@@ -3252,28 +3488,31 @@ IO Module Instances. Mapped to memory. - #define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) - #define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) - #define ADCB_CH0_RES _SFR_MEM16(0x0264) -+#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) - #define ADCB_CH1_CTRL _SFR_MEM8(0x0268) - #define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) - #define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) - #define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) - #define ADCB_CH1_RES _SFR_MEM16(0x026C) -+#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) - #define ADCB_CH2_CTRL _SFR_MEM8(0x0270) - #define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) - #define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) - #define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) - #define ADCB_CH2_RES _SFR_MEM16(0x0274) -+#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) - #define ADCB_CH3_CTRL _SFR_MEM8(0x0278) - #define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) - #define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) - #define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) - #define ADCB_CH3_RES _SFR_MEM16(0x027C) -+#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) - --/* DACA - Digital to Analog Converter A */ -+/* DAC - Digital-to-Analog Converter */ - #define DACA_CTRLA _SFR_MEM8(0x0300) - #define DACA_CTRLB _SFR_MEM8(0x0301) - #define DACA_CTRLC _SFR_MEM8(0x0302) - #define DACA_EVCTRL _SFR_MEM8(0x0303) --#define DACA_TIMCTRL _SFR_MEM8(0x0304) - #define DACA_STATUS _SFR_MEM8(0x0305) - #define DACA_CH0GAINCAL _SFR_MEM8(0x0308) - #define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) -@@ -3282,12 +3521,11 @@ IO Module Instances. Mapped to memory. - #define DACA_CH0DATA _SFR_MEM16(0x0318) - #define DACA_CH1DATA _SFR_MEM16(0x031A) - --/* DACB - Digital to Analog Converter B */ -+/* DAC - Digital-to-Analog Converter */ - #define DACB_CTRLA _SFR_MEM8(0x0320) - #define DACB_CTRLB _SFR_MEM8(0x0321) - #define DACB_CTRLC _SFR_MEM8(0x0322) - #define DACB_EVCTRL _SFR_MEM8(0x0323) --#define DACB_TIMCTRL _SFR_MEM8(0x0324) - #define DACB_STATUS _SFR_MEM8(0x0325) - #define DACB_CH0GAINCAL _SFR_MEM8(0x0328) - #define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) -@@ -3296,7 +3534,7 @@ IO Module Instances. Mapped to memory. - #define DACB_CH0DATA _SFR_MEM16(0x0338) - #define DACB_CH1DATA _SFR_MEM16(0x033A) - --/* ACA - Analog Comparator A */ -+/* AC - Analog Comparator */ - #define ACA_AC0CTRL _SFR_MEM8(0x0380) - #define ACA_AC1CTRL _SFR_MEM8(0x0381) - #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -@@ -3306,7 +3544,7 @@ IO Module Instances. Mapped to memory. - #define ACA_WINCTRL _SFR_MEM8(0x0386) - #define ACA_STATUS _SFR_MEM8(0x0387) - --/* ACB - Analog Comparator B */ -+/* AC - Analog Comparator */ - #define ACB_AC0CTRL _SFR_MEM8(0x0390) - #define ACB_AC1CTRL _SFR_MEM8(0x0391) - #define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -@@ -3346,7 +3584,7 @@ IO Module Instances. Mapped to memory. - #define EBI_CS3_CTRLB _SFR_MEM8(0x045D) - #define EBI_CS3_BASEADDR _SFR_MEM16(0x045E) - --/* TWIC - Two-Wire Interface C */ -+/* TWI - Two-Wire Interface */ - #define TWIC_CTRL _SFR_MEM8(0x0480) - #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) - #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -@@ -3362,7 +3600,7 @@ IO Module Instances. Mapped to memory. - #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) - #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - --/* TWID - Two-Wire Interface D */ -+/* TWI - Two-Wire Interface */ - #define TWID_CTRL _SFR_MEM8(0x0490) - #define TWID_MASTER_CTRLA _SFR_MEM8(0x0491) - #define TWID_MASTER_CTRLB _SFR_MEM8(0x0492) -@@ -3378,7 +3616,7 @@ IO Module Instances. Mapped to memory. - #define TWID_SLAVE_DATA _SFR_MEM8(0x049C) - #define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D) - --/* TWIE - Two-Wire Interface E */ -+/* TWI - Two-Wire Interface */ - #define TWIE_CTRL _SFR_MEM8(0x04A0) - #define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) - #define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -@@ -3394,7 +3632,7 @@ IO Module Instances. Mapped to memory. - #define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) - #define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - --/* TWIF - Two-Wire Interface F */ -+/* TWI - Two-Wire Interface */ - #define TWIF_CTRL _SFR_MEM8(0x04B0) - #define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1) - #define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2) -@@ -3410,7 +3648,7 @@ IO Module Instances. Mapped to memory. - #define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC) - #define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD) - --/* USB - Universal Serial Bus Module */ -+/* USB - Universal Serial Bus */ - #define USB_CTRLA _SFR_MEM8(0x04C0) - #define USB_CTRLB _SFR_MEM8(0x04C1) - #define USB_STATUS _SFR_MEM8(0x04C2) -@@ -3427,7 +3665,7 @@ IO Module Instances. Mapped to memory. - #define USB_CAL0 _SFR_MEM8(0x04FA) - #define USB_CAL1 _SFR_MEM8(0x04FB) - --/* PORTA - Port A */ -+/* PORT - I/O Ports */ - #define PORTA_DIR _SFR_MEM8(0x0600) - #define PORTA_DIRSET _SFR_MEM8(0x0601) - #define PORTA_DIRCLR _SFR_MEM8(0x0602) -@@ -3441,6 +3679,7 @@ IO Module Instances. Mapped to memory. - #define PORTA_INT0MASK _SFR_MEM8(0x060A) - #define PORTA_INT1MASK _SFR_MEM8(0x060B) - #define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_REMAP _SFR_MEM8(0x060E) - #define PORTA_PIN0CTRL _SFR_MEM8(0x0610) - #define PORTA_PIN1CTRL _SFR_MEM8(0x0611) - #define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -@@ -3450,7 +3689,7 @@ IO Module Instances. Mapped to memory. - #define PORTA_PIN6CTRL _SFR_MEM8(0x0616) - #define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - --/* PORTB - Port B */ -+/* PORT - I/O Ports */ - #define PORTB_DIR _SFR_MEM8(0x0620) - #define PORTB_DIRSET _SFR_MEM8(0x0621) - #define PORTB_DIRCLR _SFR_MEM8(0x0622) -@@ -3464,6 +3703,7 @@ IO Module Instances. Mapped to memory. - #define PORTB_INT0MASK _SFR_MEM8(0x062A) - #define PORTB_INT1MASK _SFR_MEM8(0x062B) - #define PORTB_INTFLAGS _SFR_MEM8(0x062C) -+#define PORTB_REMAP _SFR_MEM8(0x062E) - #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) - #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) - #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -@@ -3473,7 +3713,7 @@ IO Module Instances. Mapped to memory. - #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) - #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - --/* PORTC - Port C */ -+/* PORT - I/O Ports */ - #define PORTC_DIR _SFR_MEM8(0x0640) - #define PORTC_DIRSET _SFR_MEM8(0x0641) - #define PORTC_DIRCLR _SFR_MEM8(0x0642) -@@ -3487,6 +3727,7 @@ IO Module Instances. Mapped to memory. - #define PORTC_INT0MASK _SFR_MEM8(0x064A) - #define PORTC_INT1MASK _SFR_MEM8(0x064B) - #define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) - #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) - #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) - #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -@@ -3496,7 +3737,7 @@ IO Module Instances. Mapped to memory. - #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) - #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - --/* PORTD - Port D */ -+/* PORT - I/O Ports */ - #define PORTD_DIR _SFR_MEM8(0x0660) - #define PORTD_DIRSET _SFR_MEM8(0x0661) - #define PORTD_DIRCLR _SFR_MEM8(0x0662) -@@ -3510,6 +3751,7 @@ IO Module Instances. Mapped to memory. - #define PORTD_INT0MASK _SFR_MEM8(0x066A) - #define PORTD_INT1MASK _SFR_MEM8(0x066B) - #define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) - #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) - #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) - #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -@@ -3519,7 +3761,7 @@ IO Module Instances. Mapped to memory. - #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) - #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - --/* PORTE - Port E */ -+/* PORT - I/O Ports */ - #define PORTE_DIR _SFR_MEM8(0x0680) - #define PORTE_DIRSET _SFR_MEM8(0x0681) - #define PORTE_DIRCLR _SFR_MEM8(0x0682) -@@ -3533,6 +3775,7 @@ IO Module Instances. Mapped to memory. - #define PORTE_INT0MASK _SFR_MEM8(0x068A) - #define PORTE_INT1MASK _SFR_MEM8(0x068B) - #define PORTE_INTFLAGS _SFR_MEM8(0x068C) -+#define PORTE_REMAP _SFR_MEM8(0x068E) - #define PORTE_PIN0CTRL _SFR_MEM8(0x0690) - #define PORTE_PIN1CTRL _SFR_MEM8(0x0691) - #define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -@@ -3542,7 +3785,7 @@ IO Module Instances. Mapped to memory. - #define PORTE_PIN6CTRL _SFR_MEM8(0x0696) - #define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - --/* PORTF - Port F */ -+/* PORT - I/O Ports */ - #define PORTF_DIR _SFR_MEM8(0x06A0) - #define PORTF_DIRSET _SFR_MEM8(0x06A1) - #define PORTF_DIRCLR _SFR_MEM8(0x06A2) -@@ -3556,6 +3799,7 @@ IO Module Instances. Mapped to memory. - #define PORTF_INT0MASK _SFR_MEM8(0x06AA) - #define PORTF_INT1MASK _SFR_MEM8(0x06AB) - #define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -+#define PORTF_REMAP _SFR_MEM8(0x06AE) - #define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) - #define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) - #define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -@@ -3565,7 +3809,7 @@ IO Module Instances. Mapped to memory. - #define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) - #define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - --/* PORTH - Port H */ -+/* PORT - I/O Ports */ - #define PORTH_DIR _SFR_MEM8(0x06E0) - #define PORTH_DIRSET _SFR_MEM8(0x06E1) - #define PORTH_DIRCLR _SFR_MEM8(0x06E2) -@@ -3579,6 +3823,7 @@ IO Module Instances. Mapped to memory. - #define PORTH_INT0MASK _SFR_MEM8(0x06EA) - #define PORTH_INT1MASK _SFR_MEM8(0x06EB) - #define PORTH_INTFLAGS _SFR_MEM8(0x06EC) -+#define PORTH_REMAP _SFR_MEM8(0x06EE) - #define PORTH_PIN0CTRL _SFR_MEM8(0x06F0) - #define PORTH_PIN1CTRL _SFR_MEM8(0x06F1) - #define PORTH_PIN2CTRL _SFR_MEM8(0x06F2) -@@ -3588,7 +3833,7 @@ IO Module Instances. Mapped to memory. - #define PORTH_PIN6CTRL _SFR_MEM8(0x06F6) - #define PORTH_PIN7CTRL _SFR_MEM8(0x06F7) - --/* PORTJ - Port J */ -+/* PORT - I/O Ports */ - #define PORTJ_DIR _SFR_MEM8(0x0700) - #define PORTJ_DIRSET _SFR_MEM8(0x0701) - #define PORTJ_DIRCLR _SFR_MEM8(0x0702) -@@ -3602,6 +3847,7 @@ IO Module Instances. Mapped to memory. - #define PORTJ_INT0MASK _SFR_MEM8(0x070A) - #define PORTJ_INT1MASK _SFR_MEM8(0x070B) - #define PORTJ_INTFLAGS _SFR_MEM8(0x070C) -+#define PORTJ_REMAP _SFR_MEM8(0x070E) - #define PORTJ_PIN0CTRL _SFR_MEM8(0x0710) - #define PORTJ_PIN1CTRL _SFR_MEM8(0x0711) - #define PORTJ_PIN2CTRL _SFR_MEM8(0x0712) -@@ -3611,7 +3857,7 @@ IO Module Instances. Mapped to memory. - #define PORTJ_PIN6CTRL _SFR_MEM8(0x0716) - #define PORTJ_PIN7CTRL _SFR_MEM8(0x0717) - --/* PORTK - Port K */ -+/* PORT - I/O Ports */ - #define PORTK_DIR _SFR_MEM8(0x0720) - #define PORTK_DIRSET _SFR_MEM8(0x0721) - #define PORTK_DIRCLR _SFR_MEM8(0x0722) -@@ -3625,6 +3871,7 @@ IO Module Instances. Mapped to memory. - #define PORTK_INT0MASK _SFR_MEM8(0x072A) - #define PORTK_INT1MASK _SFR_MEM8(0x072B) - #define PORTK_INTFLAGS _SFR_MEM8(0x072C) -+#define PORTK_REMAP _SFR_MEM8(0x072E) - #define PORTK_PIN0CTRL _SFR_MEM8(0x0730) - #define PORTK_PIN1CTRL _SFR_MEM8(0x0731) - #define PORTK_PIN2CTRL _SFR_MEM8(0x0732) -@@ -3634,7 +3881,7 @@ IO Module Instances. Mapped to memory. - #define PORTK_PIN6CTRL _SFR_MEM8(0x0736) - #define PORTK_PIN7CTRL _SFR_MEM8(0x0737) - --/* PORTQ - Port Q */ -+/* PORT - I/O Ports */ - #define PORTQ_DIR _SFR_MEM8(0x07C0) - #define PORTQ_DIRSET _SFR_MEM8(0x07C1) - #define PORTQ_DIRCLR _SFR_MEM8(0x07C2) -@@ -3648,6 +3895,7 @@ IO Module Instances. Mapped to memory. - #define PORTQ_INT0MASK _SFR_MEM8(0x07CA) - #define PORTQ_INT1MASK _SFR_MEM8(0x07CB) - #define PORTQ_INTFLAGS _SFR_MEM8(0x07CC) -+#define PORTQ_REMAP _SFR_MEM8(0x07CE) - #define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0) - #define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1) - #define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2) -@@ -3657,7 +3905,7 @@ IO Module Instances. Mapped to memory. - #define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6) - #define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7) - --/* PORTR - Port R */ -+/* PORT - I/O Ports */ - #define PORTR_DIR _SFR_MEM8(0x07E0) - #define PORTR_DIRSET _SFR_MEM8(0x07E1) - #define PORTR_DIRCLR _SFR_MEM8(0x07E2) -@@ -3671,6 +3919,7 @@ IO Module Instances. Mapped to memory. - #define PORTR_INT0MASK _SFR_MEM8(0x07EA) - #define PORTR_INT1MASK _SFR_MEM8(0x07EB) - #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) - #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) - #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) - #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -@@ -3680,7 +3929,7 @@ IO Module Instances. Mapped to memory. - #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) - #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - --/* TCC0 - Timer/Counter C0 */ -+/* TC0 - 16-bit Timer/Counter 0 */ - #define TCC0_CTRLA _SFR_MEM8(0x0800) - #define TCC0_CTRLB _SFR_MEM8(0x0801) - #define TCC0_CTRLC _SFR_MEM8(0x0802) -@@ -3706,7 +3955,29 @@ IO Module Instances. Mapped to memory. - #define TCC0_CCCBUF _SFR_MEM16(0x083C) - #define TCC0_CCDBUF _SFR_MEM16(0x083E) - --/* TCC1 - Timer/Counter C1 */ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCC2_CTRLA _SFR_MEM8(0x0800) -+#define TCC2_CTRLB _SFR_MEM8(0x0801) -+#define TCC2_CTRLC _SFR_MEM8(0x0802) -+#define TCC2_CTRLE _SFR_MEM8(0x0804) -+#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC2_CTRLF _SFR_MEM8(0x0809) -+#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC2_LCNT _SFR_MEM8(0x0820) -+#define TCC2_HCNT _SFR_MEM8(0x0821) -+#define TCC2_LPER _SFR_MEM8(0x0826) -+#define TCC2_HPER _SFR_MEM8(0x0827) -+#define TCC2_LCMPA _SFR_MEM8(0x0828) -+#define TCC2_HCMPA _SFR_MEM8(0x0829) -+#define TCC2_LCMPB _SFR_MEM8(0x082A) -+#define TCC2_HCMPB _SFR_MEM8(0x082B) -+#define TCC2_LCMPC _SFR_MEM8(0x082C) -+#define TCC2_HCMPC _SFR_MEM8(0x082D) -+#define TCC2_LCMPD _SFR_MEM8(0x082E) -+#define TCC2_HCMPD _SFR_MEM8(0x082F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ - #define TCC1_CTRLA _SFR_MEM8(0x0840) - #define TCC1_CTRLB _SFR_MEM8(0x0841) - #define TCC1_CTRLC _SFR_MEM8(0x0842) -@@ -3728,11 +3999,12 @@ IO Module Instances. Mapped to memory. - #define TCC1_CCABUF _SFR_MEM16(0x0878) - #define TCC1_CCBBUF _SFR_MEM16(0x087A) - --/* AWEXC - Advanced Waveform Extension C */ -+/* AWEX - Advanced Waveform Extension */ - #define AWEXC_CTRL _SFR_MEM8(0x0880) - #define AWEXC_FDEMASK _SFR_MEM8(0x0882) - #define AWEXC_FDCTRL _SFR_MEM8(0x0883) - #define AWEXC_STATUS _SFR_MEM8(0x0884) -+#define AWEXC_STATUSSET _SFR_MEM8(0x0885) - #define AWEXC_DTBOTH _SFR_MEM8(0x0886) - #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) - #define AWEXC_DTLS _SFR_MEM8(0x0888) -@@ -3741,10 +4013,10 @@ IO Module Instances. Mapped to memory. - #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) - #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - --/* HIRESC - High-Resolution Extension C */ -+/* HIRES - High-Resolution Extension */ - #define HIRESC_CTRLA _SFR_MEM8(0x0890) - --/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ - #define USARTC0_DATA _SFR_MEM8(0x08A0) - #define USARTC0_STATUS _SFR_MEM8(0x08A1) - #define USARTC0_CTRLA _SFR_MEM8(0x08A3) -@@ -3753,7 +4025,7 @@ IO Module Instances. Mapped to memory. - #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) - #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - --/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ - #define USARTC1_DATA _SFR_MEM8(0x08B0) - #define USARTC1_STATUS _SFR_MEM8(0x08B1) - #define USARTC1_CTRLA _SFR_MEM8(0x08B3) -@@ -3762,7 +4034,7 @@ IO Module Instances. Mapped to memory. - #define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) - #define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) - --/* SPIC - Serial Peripheral Interface C */ -+/* SPI - Serial Peripheral Interface */ - #define SPIC_CTRL _SFR_MEM8(0x08C0) - #define SPIC_INTCTRL _SFR_MEM8(0x08C1) - #define SPIC_STATUS _SFR_MEM8(0x08C2) -@@ -3773,7 +4045,7 @@ IO Module Instances. Mapped to memory. - #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) - #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - --/* TCD0 - Timer/Counter D0 */ -+/* TC0 - 16-bit Timer/Counter 0 */ - #define TCD0_CTRLA _SFR_MEM8(0x0900) - #define TCD0_CTRLB _SFR_MEM8(0x0901) - #define TCD0_CTRLC _SFR_MEM8(0x0902) -@@ -3799,7 +4071,29 @@ IO Module Instances. Mapped to memory. - #define TCD0_CCCBUF _SFR_MEM16(0x093C) - #define TCD0_CCDBUF _SFR_MEM16(0x093E) - --/* TCD1 - Timer/Counter D1 */ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCD2_CTRLA _SFR_MEM8(0x0900) -+#define TCD2_CTRLB _SFR_MEM8(0x0901) -+#define TCD2_CTRLC _SFR_MEM8(0x0902) -+#define TCD2_CTRLE _SFR_MEM8(0x0904) -+#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD2_CTRLF _SFR_MEM8(0x0909) -+#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD2_LCNT _SFR_MEM8(0x0920) -+#define TCD2_HCNT _SFR_MEM8(0x0921) -+#define TCD2_LPER _SFR_MEM8(0x0926) -+#define TCD2_HPER _SFR_MEM8(0x0927) -+#define TCD2_LCMPA _SFR_MEM8(0x0928) -+#define TCD2_HCMPA _SFR_MEM8(0x0929) -+#define TCD2_LCMPB _SFR_MEM8(0x092A) -+#define TCD2_HCMPB _SFR_MEM8(0x092B) -+#define TCD2_LCMPC _SFR_MEM8(0x092C) -+#define TCD2_HCMPC _SFR_MEM8(0x092D) -+#define TCD2_LCMPD _SFR_MEM8(0x092E) -+#define TCD2_HCMPD _SFR_MEM8(0x092F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ - #define TCD1_CTRLA _SFR_MEM8(0x0940) - #define TCD1_CTRLB _SFR_MEM8(0x0941) - #define TCD1_CTRLC _SFR_MEM8(0x0942) -@@ -3821,10 +4115,10 @@ IO Module Instances. Mapped to memory. - #define TCD1_CCABUF _SFR_MEM16(0x0978) - #define TCD1_CCBBUF _SFR_MEM16(0x097A) - --/* HIRESD - High-Resolution Extension D */ -+/* HIRES - High-Resolution Extension */ - #define HIRESD_CTRLA _SFR_MEM8(0x0990) - --/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ - #define USARTD0_DATA _SFR_MEM8(0x09A0) - #define USARTD0_STATUS _SFR_MEM8(0x09A1) - #define USARTD0_CTRLA _SFR_MEM8(0x09A3) -@@ -3833,7 +4127,7 @@ IO Module Instances. Mapped to memory. - #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) - #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - --/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ - #define USARTD1_DATA _SFR_MEM8(0x09B0) - #define USARTD1_STATUS _SFR_MEM8(0x09B1) - #define USARTD1_CTRLA _SFR_MEM8(0x09B3) -@@ -3842,13 +4136,13 @@ IO Module Instances. Mapped to memory. - #define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) - #define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) - --/* SPID - Serial Peripheral Interface D */ -+/* SPI - Serial Peripheral Interface */ - #define SPID_CTRL _SFR_MEM8(0x09C0) - #define SPID_INTCTRL _SFR_MEM8(0x09C1) - #define SPID_STATUS _SFR_MEM8(0x09C2) - #define SPID_DATA _SFR_MEM8(0x09C3) - --/* TCE0 - Timer/Counter E0 */ -+/* TC0 - 16-bit Timer/Counter 0 */ - #define TCE0_CTRLA _SFR_MEM8(0x0A00) - #define TCE0_CTRLB _SFR_MEM8(0x0A01) - #define TCE0_CTRLC _SFR_MEM8(0x0A02) -@@ -3874,7 +4168,29 @@ IO Module Instances. Mapped to memory. - #define TCE0_CCCBUF _SFR_MEM16(0x0A3C) - #define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - --/* TCE1 - Timer/Counter E1 */ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCE2_CTRLA _SFR_MEM8(0x0A00) -+#define TCE2_CTRLB _SFR_MEM8(0x0A01) -+#define TCE2_CTRLC _SFR_MEM8(0x0A02) -+#define TCE2_CTRLE _SFR_MEM8(0x0A04) -+#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE2_CTRLF _SFR_MEM8(0x0A09) -+#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE2_LCNT _SFR_MEM8(0x0A20) -+#define TCE2_HCNT _SFR_MEM8(0x0A21) -+#define TCE2_LPER _SFR_MEM8(0x0A26) -+#define TCE2_HPER _SFR_MEM8(0x0A27) -+#define TCE2_LCMPA _SFR_MEM8(0x0A28) -+#define TCE2_HCMPA _SFR_MEM8(0x0A29) -+#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -+#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -+#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -+#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -+#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -+#define TCE2_HCMPD _SFR_MEM8(0x0A2F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ - #define TCE1_CTRLA _SFR_MEM8(0x0A40) - #define TCE1_CTRLB _SFR_MEM8(0x0A41) - #define TCE1_CTRLC _SFR_MEM8(0x0A42) -@@ -3896,11 +4212,12 @@ IO Module Instances. Mapped to memory. - #define TCE1_CCABUF _SFR_MEM16(0x0A78) - #define TCE1_CCBBUF _SFR_MEM16(0x0A7A) - --/* AWEXE - Advanced Waveform Extension E */ -+/* AWEX - Advanced Waveform Extension */ - #define AWEXE_CTRL _SFR_MEM8(0x0A80) - #define AWEXE_FDEMASK _SFR_MEM8(0x0A82) - #define AWEXE_FDCTRL _SFR_MEM8(0x0A83) - #define AWEXE_STATUS _SFR_MEM8(0x0A84) -+#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) - #define AWEXE_DTBOTH _SFR_MEM8(0x0A86) - #define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) - #define AWEXE_DTLS _SFR_MEM8(0x0A88) -@@ -3909,10 +4226,10 @@ IO Module Instances. Mapped to memory. - #define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) - #define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) - --/* HIRESE - High-Resolution Extension E */ -+/* HIRES - High-Resolution Extension */ - #define HIRESE_CTRLA _SFR_MEM8(0x0A90) - --/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ - #define USARTE0_DATA _SFR_MEM8(0x0AA0) - #define USARTE0_STATUS _SFR_MEM8(0x0AA1) - #define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -@@ -3921,7 +4238,7 @@ IO Module Instances. Mapped to memory. - #define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) - #define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - --/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ - #define USARTE1_DATA _SFR_MEM8(0x0AB0) - #define USARTE1_STATUS _SFR_MEM8(0x0AB1) - #define USARTE1_CTRLA _SFR_MEM8(0x0AB3) -@@ -3930,13 +4247,13 @@ IO Module Instances. Mapped to memory. - #define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) - #define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) - --/* SPIE - Serial Peripheral Interface E */ -+/* SPI - Serial Peripheral Interface */ - #define SPIE_CTRL _SFR_MEM8(0x0AC0) - #define SPIE_INTCTRL _SFR_MEM8(0x0AC1) - #define SPIE_STATUS _SFR_MEM8(0x0AC2) - #define SPIE_DATA _SFR_MEM8(0x0AC3) - --/* TCF0 - Timer/Counter F0 */ -+/* TC0 - 16-bit Timer/Counter 0 */ - #define TCF0_CTRLA _SFR_MEM8(0x0B00) - #define TCF0_CTRLB _SFR_MEM8(0x0B01) - #define TCF0_CTRLC _SFR_MEM8(0x0B02) -@@ -3962,7 +4279,29 @@ IO Module Instances. Mapped to memory. - #define TCF0_CCCBUF _SFR_MEM16(0x0B3C) - #define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - --/* TCF1 - Timer/Counter F1 */ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCF2_CTRLA _SFR_MEM8(0x0B00) -+#define TCF2_CTRLB _SFR_MEM8(0x0B01) -+#define TCF2_CTRLC _SFR_MEM8(0x0B02) -+#define TCF2_CTRLE _SFR_MEM8(0x0B04) -+#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -+#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -+#define TCF2_CTRLF _SFR_MEM8(0x0B09) -+#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -+#define TCF2_LCNT _SFR_MEM8(0x0B20) -+#define TCF2_HCNT _SFR_MEM8(0x0B21) -+#define TCF2_LPER _SFR_MEM8(0x0B26) -+#define TCF2_HPER _SFR_MEM8(0x0B27) -+#define TCF2_LCMPA _SFR_MEM8(0x0B28) -+#define TCF2_HCMPA _SFR_MEM8(0x0B29) -+#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -+#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -+#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -+#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -+#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -+#define TCF2_HCMPD _SFR_MEM8(0x0B2F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ - #define TCF1_CTRLA _SFR_MEM8(0x0B40) - #define TCF1_CTRLB _SFR_MEM8(0x0B41) - #define TCF1_CTRLC _SFR_MEM8(0x0B42) -@@ -3984,10 +4323,10 @@ IO Module Instances. Mapped to memory. - #define TCF1_CCABUF _SFR_MEM16(0x0B78) - #define TCF1_CCBBUF _SFR_MEM16(0x0B7A) - --/* HIRESF - High-Resolution Extension F */ -+/* HIRES - High-Resolution Extension */ - #define HIRESF_CTRLA _SFR_MEM8(0x0B90) - --/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ - #define USARTF0_DATA _SFR_MEM8(0x0BA0) - #define USARTF0_STATUS _SFR_MEM8(0x0BA1) - #define USARTF0_CTRLA _SFR_MEM8(0x0BA3) -@@ -3996,7 +4335,7 @@ IO Module Instances. Mapped to memory. - #define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) - #define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) - --/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ - #define USARTF1_DATA _SFR_MEM8(0x0BB0) - #define USARTF1_STATUS _SFR_MEM8(0x0BB1) - #define USARTF1_CTRLA _SFR_MEM8(0x0BB3) -@@ -4005,7 +4344,7 @@ IO Module Instances. Mapped to memory. - #define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) - #define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) - --/* SPIF - Serial Peripheral Interface F */ -+/* SPI - Serial Peripheral Interface */ - #define SPIF_CTRL _SFR_MEM8(0x0BC0) - #define SPIF_INTCTRL _SFR_MEM8(0x0BC1) - #define SPIF_STATUS _SFR_MEM8(0x0BC2) -@@ -4023,12 +4362,30 @@ IO Module Instances. Mapped to memory. - #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ - #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - +-/* GPIO - General Purpose IO Registers */ +-#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +-#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +-#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +-#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +-#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +-#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +-#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +-#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +-#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +-#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +-#define GPIO_GPIORA _SFR_MEM8(0x000A) +-#define GPIO_GPIORB _SFR_MEM8(0x000B) +-#define GPIO_GPIORC _SFR_MEM8(0x000C) +-#define GPIO_GPIORD _SFR_MEM8(0x000D) +-#define GPIO_GPIORE _SFR_MEM8(0x000E) +-#define GPIO_GPIORF _SFR_MEM8(0x000F) - - /* XOCD - On-Chip Debug System */ +-/* VPORT0 - Virtual Port 0 */ +-#define VPORT0_DIR _SFR_MEM8(0x0010) +-#define VPORT0_OUT _SFR_MEM8(0x0011) +-#define VPORT0_IN _SFR_MEM8(0x0012) +-#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) +- +-/* VPORT1 - Virtual Port 1 */ +-#define VPORT1_DIR _SFR_MEM8(0x0014) +-#define VPORT1_OUT _SFR_MEM8(0x0015) +-#define VPORT1_IN _SFR_MEM8(0x0016) +-#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) +- +-/* VPORT2 - Virtual Port 2 */ +-#define VPORT2_DIR _SFR_MEM8(0x0018) +-#define VPORT2_OUT _SFR_MEM8(0x0019) +-#define VPORT2_IN _SFR_MEM8(0x001A) +-#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) +- +-/* VPORT3 - Virtual Port 3 */ +-#define VPORT3_DIR _SFR_MEM8(0x001C) +-#define VPORT3_OUT _SFR_MEM8(0x001D) +-#define VPORT3_IN _SFR_MEM8(0x001E) +-#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) +- +-/* OCD - On-Chip Debug System */ +-#define OCD_OCDR0 _SFR_MEM8(0x002E) +-#define OCD_OCDR1 _SFR_MEM8(0x002F) +- +-/* CPU - CPU Registers */ +-#define CPU_CCP _SFR_MEM8(0x0034) +-#define CPU_RAMPD _SFR_MEM8(0x0038) +-#define CPU_RAMPX _SFR_MEM8(0x0039) +-#define CPU_RAMPY _SFR_MEM8(0x003A) +-#define CPU_RAMPZ _SFR_MEM8(0x003B) +-#define CPU_EIND _SFR_MEM8(0x003C) +-#define CPU_SPL _SFR_MEM8(0x003D) +-#define CPU_SPH _SFR_MEM8(0x003E) +-#define CPU_SREG _SFR_MEM8(0x003F) +- +-/* CLK - Clock System */ +-#define CLK_CTRL _SFR_MEM8(0x0040) +-#define CLK_PSCTRL _SFR_MEM8(0x0041) +-#define CLK_LOCK _SFR_MEM8(0x0042) +-#define CLK_RTCCTRL _SFR_MEM8(0x0043) +-#define CLK_USBCTRL _SFR_MEM8(0x0044) +- +-/* SLEEP - Sleep Controller */ +-#define SLEEP_CTRL _SFR_MEM8(0x0048) +- +-/* OSC - Oscillator Control */ +-#define OSC_CTRL _SFR_MEM8(0x0050) +-#define OSC_STATUS _SFR_MEM8(0x0051) +-#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +-#define OSC_XOSCFAIL _SFR_MEM8(0x005F) +-#define OSC_RC32KCAL _SFR_MEM8(0x0054) +-#define OSC_PLLCTRL _SFR_MEM8(0x0055) +-#define OSC_DFLLCTRL _SFR_MEM8(0x0056) +- +-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +-#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +-#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +-#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +-#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +-#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +-#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) +- +-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +-#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +-#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +-#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +-#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +-#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +-#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) +- +-/* PR - Power Reduction */ +-#define PR_PRGEN _SFR_MEM8(0x0070) +-#define PR_PRPA _SFR_MEM8(0x0071) +-#define PR_PRPB _SFR_MEM8(0x0072) +-#define PR_PRPC _SFR_MEM8(0x0073) +-#define PR_PRPD _SFR_MEM8(0x0074) +-#define PR_PRPE _SFR_MEM8(0x0075) +-#define PR_PRPF _SFR_MEM8(0x0076) +- +-/* RST - Reset Controller */ +-#define RST_STATUS _SFR_MEM8(0x0078) +-#define RST_CTRL _SFR_MEM8(0x0079) +- +-/* WDT - Watch-Dog Timer */ +-#define WDT_CTRL _SFR_MEM8(0x0080) +-#define WDT_WINCTRL _SFR_MEM8(0x0081) +-#define WDT_STATUS _SFR_MEM8(0x0082) +- +-/* MCU - MCU Control */ +-#define MCU_DEVID0 _SFR_MEM8(0x0090) +-#define MCU_DEVID1 _SFR_MEM8(0x0091) +-#define MCU_DEVID2 _SFR_MEM8(0x0092) +-#define MCU_REVID _SFR_MEM8(0x0093) +-#define MCU_JTAGUID _SFR_MEM8(0x0094) +-#define MCU_MCUCR _SFR_MEM8(0x0096) +-#define MCU_ANAINIT _SFR_MEM8(0x0097) +-#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +-#define MCU_AWEXLOCK _SFR_MEM8(0x0099) +- +-/* PMIC - Programmable Interrupt Controller */ +-#define PMIC_STATUS _SFR_MEM8(0x00A0) +-#define PMIC_INTPRI _SFR_MEM8(0x00A1) +-#define PMIC_CTRL _SFR_MEM8(0x00A2) +- +-/* PORTCFG - Port Configuration */ +-#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +-#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +-#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +-#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +- +-/* AES - AES Crypto Module */ +-#define AES_CTRL _SFR_MEM8(0x00C0) +-#define AES_STATUS _SFR_MEM8(0x00C1) +-#define AES_STATE _SFR_MEM8(0x00C2) +-#define AES_KEY _SFR_MEM8(0x00C3) +-#define AES_INTCTRL _SFR_MEM8(0x00C4) +- +-/* CRC - CRC Module */ +-#define CRC_CTRL _SFR_MEM8(0x00D0) +-#define CRC_STATUS _SFR_MEM8(0x00D1) +-#define CRC_DATAIN _SFR_MEM8(0x00D3) +-#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +-#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +-#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +-#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) +- +-/* DMA - DMA Controller */ +-#define DMA_CTRL _SFR_MEM8(0x0100) +-#define DMA_INTFLAGS _SFR_MEM8(0x0103) +-#define DMA_STATUS _SFR_MEM8(0x0104) +-#define DMA_TEMP _SFR_MEM16(0x0106) +-#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +-#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +-#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +-#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +-#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +-#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +-#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +-#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +-#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +-#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +-#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +-#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +-#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +-#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +-#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +-#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +-#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +-#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +-#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +-#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +-#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +-#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +-#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +-#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +-#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +-#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +-#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +-#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +-#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +-#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +-#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +-#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +-#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +-#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +-#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +-#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +-#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +-#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +-#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +-#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +-#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +-#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +-#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +-#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +-#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +-#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +-#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +-#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) +- +-/* EVSYS - Event System */ +-#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +-#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +-#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +-#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +-#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +-#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +-#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +-#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +-#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +-#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +-#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +-#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +-#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +-#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +-#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +-#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +-#define EVSYS_STROBE _SFR_MEM8(0x0190) +-#define EVSYS_DATA _SFR_MEM8(0x0191) +- +-/* NVM - Non Volatile Memory Controller */ +-#define NVM_ADDR0 _SFR_MEM8(0x01C0) +-#define NVM_ADDR1 _SFR_MEM8(0x01C1) +-#define NVM_ADDR2 _SFR_MEM8(0x01C2) +-#define NVM_DATA0 _SFR_MEM8(0x01C4) +-#define NVM_DATA1 _SFR_MEM8(0x01C5) +-#define NVM_DATA2 _SFR_MEM8(0x01C6) +-#define NVM_CMD _SFR_MEM8(0x01CA) +-#define NVM_CTRLA _SFR_MEM8(0x01CB) +-#define NVM_CTRLB _SFR_MEM8(0x01CC) +-#define NVM_INTCTRL _SFR_MEM8(0x01CD) +-#define NVM_STATUS _SFR_MEM8(0x01CF) +-#define NVM_LOCKBITS _SFR_MEM8(0x01D0) +- +-/* ADCA - Analog to Digital Converter A */ +-#define ADCA_CTRLA _SFR_MEM8(0x0200) +-#define ADCA_CTRLB _SFR_MEM8(0x0201) +-#define ADCA_REFCTRL _SFR_MEM8(0x0202) +-#define ADCA_EVCTRL _SFR_MEM8(0x0203) +-#define ADCA_PRESCALER _SFR_MEM8(0x0204) +-#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +-#define ADCA_TEMP _SFR_MEM8(0x0207) +-#define ADCA_CAL _SFR_MEM16(0x020C) +-#define ADCA_CH0RES _SFR_MEM16(0x0210) +-#define ADCA_CH1RES _SFR_MEM16(0x0212) +-#define ADCA_CH2RES _SFR_MEM16(0x0214) +-#define ADCA_CH3RES _SFR_MEM16(0x0216) +-#define ADCA_CMP _SFR_MEM16(0x0218) +-#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +-#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +-#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +-#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +-#define ADCA_CH0_RES _SFR_MEM16(0x0224) +-#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +-#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +-#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +-#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +-#define ADCA_CH1_RES _SFR_MEM16(0x022C) +-#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +-#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +-#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +-#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +-#define ADCA_CH2_RES _SFR_MEM16(0x0234) +-#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +-#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +-#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +-#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +-#define ADCA_CH3_RES _SFR_MEM16(0x023C) +- +-/* ADCB - Analog to Digital Converter B */ +-#define ADCB_CTRLA _SFR_MEM8(0x0240) +-#define ADCB_CTRLB _SFR_MEM8(0x0241) +-#define ADCB_REFCTRL _SFR_MEM8(0x0242) +-#define ADCB_EVCTRL _SFR_MEM8(0x0243) +-#define ADCB_PRESCALER _SFR_MEM8(0x0244) +-#define ADCB_INTFLAGS _SFR_MEM8(0x0246) +-#define ADCB_TEMP _SFR_MEM8(0x0247) +-#define ADCB_CAL _SFR_MEM16(0x024C) +-#define ADCB_CH0RES _SFR_MEM16(0x0250) +-#define ADCB_CH1RES _SFR_MEM16(0x0252) +-#define ADCB_CH2RES _SFR_MEM16(0x0254) +-#define ADCB_CH3RES _SFR_MEM16(0x0256) +-#define ADCB_CMP _SFR_MEM16(0x0258) +-#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) +-#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) +-#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) +-#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) +-#define ADCB_CH0_RES _SFR_MEM16(0x0264) +-#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) +-#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) +-#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) +-#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) +-#define ADCB_CH1_RES _SFR_MEM16(0x026C) +-#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) +-#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) +-#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) +-#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) +-#define ADCB_CH2_RES _SFR_MEM16(0x0274) +-#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) +-#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) +-#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) +-#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) +-#define ADCB_CH3_RES _SFR_MEM16(0x027C) +- +-/* DACA - Digital to Analog Converter A */ +-#define DACA_CTRLA _SFR_MEM8(0x0300) +-#define DACA_CTRLB _SFR_MEM8(0x0301) +-#define DACA_CTRLC _SFR_MEM8(0x0302) +-#define DACA_EVCTRL _SFR_MEM8(0x0303) +-#define DACA_TIMCTRL _SFR_MEM8(0x0304) +-#define DACA_STATUS _SFR_MEM8(0x0305) +-#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) +-#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) +-#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) +-#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) +-#define DACA_CH0DATA _SFR_MEM16(0x0318) +-#define DACA_CH1DATA _SFR_MEM16(0x031A) +- +-/* DACB - Digital to Analog Converter B */ +-#define DACB_CTRLA _SFR_MEM8(0x0320) +-#define DACB_CTRLB _SFR_MEM8(0x0321) +-#define DACB_CTRLC _SFR_MEM8(0x0322) +-#define DACB_EVCTRL _SFR_MEM8(0x0323) +-#define DACB_TIMCTRL _SFR_MEM8(0x0324) +-#define DACB_STATUS _SFR_MEM8(0x0325) +-#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) +-#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) +-#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) +-#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) +-#define DACB_CH0DATA _SFR_MEM16(0x0338) +-#define DACB_CH1DATA _SFR_MEM16(0x033A) +- +-/* ACA - Analog Comparator A */ +-#define ACA_AC0CTRL _SFR_MEM8(0x0380) +-#define ACA_AC1CTRL _SFR_MEM8(0x0381) +-#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +-#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +-#define ACA_CTRLA _SFR_MEM8(0x0384) +-#define ACA_CTRLB _SFR_MEM8(0x0385) +-#define ACA_WINCTRL _SFR_MEM8(0x0386) +-#define ACA_STATUS _SFR_MEM8(0x0387) +- +-/* ACB - Analog Comparator B */ +-#define ACB_AC0CTRL _SFR_MEM8(0x0390) +-#define ACB_AC1CTRL _SFR_MEM8(0x0391) +-#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +-#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +-#define ACB_CTRLA _SFR_MEM8(0x0394) +-#define ACB_CTRLB _SFR_MEM8(0x0395) +-#define ACB_WINCTRL _SFR_MEM8(0x0396) +-#define ACB_STATUS _SFR_MEM8(0x0397) +- +-/* RTC - Real-Time Counter */ +-#define RTC_CTRL _SFR_MEM8(0x0400) +-#define RTC_STATUS _SFR_MEM8(0x0401) +-#define RTC_INTCTRL _SFR_MEM8(0x0402) +-#define RTC_INTFLAGS _SFR_MEM8(0x0403) +-#define RTC_TEMP _SFR_MEM8(0x0404) +-#define RTC_CNT _SFR_MEM16(0x0408) +-#define RTC_PER _SFR_MEM16(0x040A) +-#define RTC_COMP _SFR_MEM16(0x040C) +- +-/* EBI - External Bus Interface */ +-#define EBI_CTRL _SFR_MEM8(0x0440) +-#define EBI_SDRAMCTRLA _SFR_MEM8(0x0441) +-#define EBI_REFRESH _SFR_MEM16(0x0444) +-#define EBI_INITDLY _SFR_MEM16(0x0446) +-#define EBI_SDRAMCTRLB _SFR_MEM8(0x0448) +-#define EBI_SDRAMCTRLC _SFR_MEM8(0x0449) +-#define EBI_CS0_CTRLA _SFR_MEM8(0x0450) +-#define EBI_CS0_CTRLB _SFR_MEM8(0x0451) +-#define EBI_CS0_BASEADDR _SFR_MEM16(0x0452) +-#define EBI_CS1_CTRLA _SFR_MEM8(0x0454) +-#define EBI_CS1_CTRLB _SFR_MEM8(0x0455) +-#define EBI_CS1_BASEADDR _SFR_MEM16(0x0456) +-#define EBI_CS2_CTRLA _SFR_MEM8(0x0458) +-#define EBI_CS2_CTRLB _SFR_MEM8(0x0459) +-#define EBI_CS2_BASEADDR _SFR_MEM16(0x045A) +-#define EBI_CS3_CTRLA _SFR_MEM8(0x045C) +-#define EBI_CS3_CTRLB _SFR_MEM8(0x045D) +-#define EBI_CS3_BASEADDR _SFR_MEM16(0x045E) +- +-/* TWIC - Two-Wire Interface C */ +-#define TWIC_CTRL _SFR_MEM8(0x0480) +-#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +-#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +-#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +-#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +-#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +-#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +-#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +-#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +-#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +-#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +-#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +-#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +-#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) +- +-/* TWID - Two-Wire Interface D */ +-#define TWID_CTRL _SFR_MEM8(0x0490) +-#define TWID_MASTER_CTRLA _SFR_MEM8(0x0491) +-#define TWID_MASTER_CTRLB _SFR_MEM8(0x0492) +-#define TWID_MASTER_CTRLC _SFR_MEM8(0x0493) +-#define TWID_MASTER_STATUS _SFR_MEM8(0x0494) +-#define TWID_MASTER_BAUD _SFR_MEM8(0x0495) +-#define TWID_MASTER_ADDR _SFR_MEM8(0x0496) +-#define TWID_MASTER_DATA _SFR_MEM8(0x0497) +-#define TWID_SLAVE_CTRLA _SFR_MEM8(0x0498) +-#define TWID_SLAVE_CTRLB _SFR_MEM8(0x0499) +-#define TWID_SLAVE_STATUS _SFR_MEM8(0x049A) +-#define TWID_SLAVE_ADDR _SFR_MEM8(0x049B) +-#define TWID_SLAVE_DATA _SFR_MEM8(0x049C) +-#define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D) +- +-/* TWIE - Two-Wire Interface E */ +-#define TWIE_CTRL _SFR_MEM8(0x04A0) +-#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +-#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +-#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +-#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +-#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +-#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +-#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +-#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +-#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +-#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +-#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +-#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +-#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) +- +-/* TWIF - Two-Wire Interface F */ +-#define TWIF_CTRL _SFR_MEM8(0x04B0) +-#define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1) +-#define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2) +-#define TWIF_MASTER_CTRLC _SFR_MEM8(0x04B3) +-#define TWIF_MASTER_STATUS _SFR_MEM8(0x04B4) +-#define TWIF_MASTER_BAUD _SFR_MEM8(0x04B5) +-#define TWIF_MASTER_ADDR _SFR_MEM8(0x04B6) +-#define TWIF_MASTER_DATA _SFR_MEM8(0x04B7) +-#define TWIF_SLAVE_CTRLA _SFR_MEM8(0x04B8) +-#define TWIF_SLAVE_CTRLB _SFR_MEM8(0x04B9) +-#define TWIF_SLAVE_STATUS _SFR_MEM8(0x04BA) +-#define TWIF_SLAVE_ADDR _SFR_MEM8(0x04BB) +-#define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC) +-#define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD) +- +-/* USB - Universal Serial Bus Module */ +-#define USB_CTRLA _SFR_MEM8(0x04C0) +-#define USB_CTRLB _SFR_MEM8(0x04C1) +-#define USB_STATUS _SFR_MEM8(0x04C2) +-#define USB_ADDR _SFR_MEM8(0x04C3) +-#define USB_FIFOWP _SFR_MEM8(0x04C4) +-#define USB_FIFORP _SFR_MEM8(0x04C5) +-#define USB_EPPTR _SFR_MEM16(0x04C6) +-#define USB_INTCTRLA _SFR_MEM8(0x04C8) +-#define USB_INTCTRLB _SFR_MEM8(0x04C9) +-#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) +-#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) +-#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) +-#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) +-#define USB_CAL0 _SFR_MEM8(0x04FA) +-#define USB_CAL1 _SFR_MEM8(0x04FB) +- +-/* PORTA - Port A */ +-#define PORTA_DIR _SFR_MEM8(0x0600) +-#define PORTA_DIRSET _SFR_MEM8(0x0601) +-#define PORTA_DIRCLR _SFR_MEM8(0x0602) +-#define PORTA_DIRTGL _SFR_MEM8(0x0603) +-#define PORTA_OUT _SFR_MEM8(0x0604) +-#define PORTA_OUTSET _SFR_MEM8(0x0605) +-#define PORTA_OUTCLR _SFR_MEM8(0x0606) +-#define PORTA_OUTTGL _SFR_MEM8(0x0607) +-#define PORTA_IN _SFR_MEM8(0x0608) +-#define PORTA_INTCTRL _SFR_MEM8(0x0609) +-#define PORTA_INT0MASK _SFR_MEM8(0x060A) +-#define PORTA_INT1MASK _SFR_MEM8(0x060B) +-#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +-#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +-#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +-#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +-#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +-#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +-#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +-#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +-#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) +- +-/* PORTB - Port B */ +-#define PORTB_DIR _SFR_MEM8(0x0620) +-#define PORTB_DIRSET _SFR_MEM8(0x0621) +-#define PORTB_DIRCLR _SFR_MEM8(0x0622) +-#define PORTB_DIRTGL _SFR_MEM8(0x0623) +-#define PORTB_OUT _SFR_MEM8(0x0624) +-#define PORTB_OUTSET _SFR_MEM8(0x0625) +-#define PORTB_OUTCLR _SFR_MEM8(0x0626) +-#define PORTB_OUTTGL _SFR_MEM8(0x0627) +-#define PORTB_IN _SFR_MEM8(0x0628) +-#define PORTB_INTCTRL _SFR_MEM8(0x0629) +-#define PORTB_INT0MASK _SFR_MEM8(0x062A) +-#define PORTB_INT1MASK _SFR_MEM8(0x062B) +-#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +-#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +-#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +-#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +-#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +-#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +-#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +-#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +-#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) +- +-/* PORTC - Port C */ +-#define PORTC_DIR _SFR_MEM8(0x0640) +-#define PORTC_DIRSET _SFR_MEM8(0x0641) +-#define PORTC_DIRCLR _SFR_MEM8(0x0642) +-#define PORTC_DIRTGL _SFR_MEM8(0x0643) +-#define PORTC_OUT _SFR_MEM8(0x0644) +-#define PORTC_OUTSET _SFR_MEM8(0x0645) +-#define PORTC_OUTCLR _SFR_MEM8(0x0646) +-#define PORTC_OUTTGL _SFR_MEM8(0x0647) +-#define PORTC_IN _SFR_MEM8(0x0648) +-#define PORTC_INTCTRL _SFR_MEM8(0x0649) +-#define PORTC_INT0MASK _SFR_MEM8(0x064A) +-#define PORTC_INT1MASK _SFR_MEM8(0x064B) +-#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +-#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +-#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +-#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +-#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +-#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +-#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +-#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +-#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) +- +-/* PORTD - Port D */ +-#define PORTD_DIR _SFR_MEM8(0x0660) +-#define PORTD_DIRSET _SFR_MEM8(0x0661) +-#define PORTD_DIRCLR _SFR_MEM8(0x0662) +-#define PORTD_DIRTGL _SFR_MEM8(0x0663) +-#define PORTD_OUT _SFR_MEM8(0x0664) +-#define PORTD_OUTSET _SFR_MEM8(0x0665) +-#define PORTD_OUTCLR _SFR_MEM8(0x0666) +-#define PORTD_OUTTGL _SFR_MEM8(0x0667) +-#define PORTD_IN _SFR_MEM8(0x0668) +-#define PORTD_INTCTRL _SFR_MEM8(0x0669) +-#define PORTD_INT0MASK _SFR_MEM8(0x066A) +-#define PORTD_INT1MASK _SFR_MEM8(0x066B) +-#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +-#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +-#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +-#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +-#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +-#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +-#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +-#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +-#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) +- +-/* PORTE - Port E */ +-#define PORTE_DIR _SFR_MEM8(0x0680) +-#define PORTE_DIRSET _SFR_MEM8(0x0681) +-#define PORTE_DIRCLR _SFR_MEM8(0x0682) +-#define PORTE_DIRTGL _SFR_MEM8(0x0683) +-#define PORTE_OUT _SFR_MEM8(0x0684) +-#define PORTE_OUTSET _SFR_MEM8(0x0685) +-#define PORTE_OUTCLR _SFR_MEM8(0x0686) +-#define PORTE_OUTTGL _SFR_MEM8(0x0687) +-#define PORTE_IN _SFR_MEM8(0x0688) +-#define PORTE_INTCTRL _SFR_MEM8(0x0689) +-#define PORTE_INT0MASK _SFR_MEM8(0x068A) +-#define PORTE_INT1MASK _SFR_MEM8(0x068B) +-#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +-#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +-#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +-#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +-#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +-#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +-#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +-#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +-#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) +- +-/* PORTF - Port F */ +-#define PORTF_DIR _SFR_MEM8(0x06A0) +-#define PORTF_DIRSET _SFR_MEM8(0x06A1) +-#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +-#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +-#define PORTF_OUT _SFR_MEM8(0x06A4) +-#define PORTF_OUTSET _SFR_MEM8(0x06A5) +-#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +-#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +-#define PORTF_IN _SFR_MEM8(0x06A8) +-#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +-#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +-#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +-#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +-#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +-#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +-#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +-#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +-#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +-#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +-#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +-#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) +- +-/* PORTH - Port H */ +-#define PORTH_DIR _SFR_MEM8(0x06E0) +-#define PORTH_DIRSET _SFR_MEM8(0x06E1) +-#define PORTH_DIRCLR _SFR_MEM8(0x06E2) +-#define PORTH_DIRTGL _SFR_MEM8(0x06E3) +-#define PORTH_OUT _SFR_MEM8(0x06E4) +-#define PORTH_OUTSET _SFR_MEM8(0x06E5) +-#define PORTH_OUTCLR _SFR_MEM8(0x06E6) +-#define PORTH_OUTTGL _SFR_MEM8(0x06E7) +-#define PORTH_IN _SFR_MEM8(0x06E8) +-#define PORTH_INTCTRL _SFR_MEM8(0x06E9) +-#define PORTH_INT0MASK _SFR_MEM8(0x06EA) +-#define PORTH_INT1MASK _SFR_MEM8(0x06EB) +-#define PORTH_INTFLAGS _SFR_MEM8(0x06EC) +-#define PORTH_PIN0CTRL _SFR_MEM8(0x06F0) +-#define PORTH_PIN1CTRL _SFR_MEM8(0x06F1) +-#define PORTH_PIN2CTRL _SFR_MEM8(0x06F2) +-#define PORTH_PIN3CTRL _SFR_MEM8(0x06F3) +-#define PORTH_PIN4CTRL _SFR_MEM8(0x06F4) +-#define PORTH_PIN5CTRL _SFR_MEM8(0x06F5) +-#define PORTH_PIN6CTRL _SFR_MEM8(0x06F6) +-#define PORTH_PIN7CTRL _SFR_MEM8(0x06F7) +- +-/* PORTJ - Port J */ +-#define PORTJ_DIR _SFR_MEM8(0x0700) +-#define PORTJ_DIRSET _SFR_MEM8(0x0701) +-#define PORTJ_DIRCLR _SFR_MEM8(0x0702) +-#define PORTJ_DIRTGL _SFR_MEM8(0x0703) +-#define PORTJ_OUT _SFR_MEM8(0x0704) +-#define PORTJ_OUTSET _SFR_MEM8(0x0705) +-#define PORTJ_OUTCLR _SFR_MEM8(0x0706) +-#define PORTJ_OUTTGL _SFR_MEM8(0x0707) +-#define PORTJ_IN _SFR_MEM8(0x0708) +-#define PORTJ_INTCTRL _SFR_MEM8(0x0709) +-#define PORTJ_INT0MASK _SFR_MEM8(0x070A) +-#define PORTJ_INT1MASK _SFR_MEM8(0x070B) +-#define PORTJ_INTFLAGS _SFR_MEM8(0x070C) +-#define PORTJ_PIN0CTRL _SFR_MEM8(0x0710) +-#define PORTJ_PIN1CTRL _SFR_MEM8(0x0711) +-#define PORTJ_PIN2CTRL _SFR_MEM8(0x0712) +-#define PORTJ_PIN3CTRL _SFR_MEM8(0x0713) +-#define PORTJ_PIN4CTRL _SFR_MEM8(0x0714) +-#define PORTJ_PIN5CTRL _SFR_MEM8(0x0715) +-#define PORTJ_PIN6CTRL _SFR_MEM8(0x0716) +-#define PORTJ_PIN7CTRL _SFR_MEM8(0x0717) +- +-/* PORTK - Port K */ +-#define PORTK_DIR _SFR_MEM8(0x0720) +-#define PORTK_DIRSET _SFR_MEM8(0x0721) +-#define PORTK_DIRCLR _SFR_MEM8(0x0722) +-#define PORTK_DIRTGL _SFR_MEM8(0x0723) +-#define PORTK_OUT _SFR_MEM8(0x0724) +-#define PORTK_OUTSET _SFR_MEM8(0x0725) +-#define PORTK_OUTCLR _SFR_MEM8(0x0726) +-#define PORTK_OUTTGL _SFR_MEM8(0x0727) +-#define PORTK_IN _SFR_MEM8(0x0728) +-#define PORTK_INTCTRL _SFR_MEM8(0x0729) +-#define PORTK_INT0MASK _SFR_MEM8(0x072A) +-#define PORTK_INT1MASK _SFR_MEM8(0x072B) +-#define PORTK_INTFLAGS _SFR_MEM8(0x072C) +-#define PORTK_PIN0CTRL _SFR_MEM8(0x0730) +-#define PORTK_PIN1CTRL _SFR_MEM8(0x0731) +-#define PORTK_PIN2CTRL _SFR_MEM8(0x0732) +-#define PORTK_PIN3CTRL _SFR_MEM8(0x0733) +-#define PORTK_PIN4CTRL _SFR_MEM8(0x0734) +-#define PORTK_PIN5CTRL _SFR_MEM8(0x0735) +-#define PORTK_PIN6CTRL _SFR_MEM8(0x0736) +-#define PORTK_PIN7CTRL _SFR_MEM8(0x0737) +- +-/* PORTQ - Port Q */ +-#define PORTQ_DIR _SFR_MEM8(0x07C0) +-#define PORTQ_DIRSET _SFR_MEM8(0x07C1) +-#define PORTQ_DIRCLR _SFR_MEM8(0x07C2) +-#define PORTQ_DIRTGL _SFR_MEM8(0x07C3) +-#define PORTQ_OUT _SFR_MEM8(0x07C4) +-#define PORTQ_OUTSET _SFR_MEM8(0x07C5) +-#define PORTQ_OUTCLR _SFR_MEM8(0x07C6) +-#define PORTQ_OUTTGL _SFR_MEM8(0x07C7) +-#define PORTQ_IN _SFR_MEM8(0x07C8) +-#define PORTQ_INTCTRL _SFR_MEM8(0x07C9) +-#define PORTQ_INT0MASK _SFR_MEM8(0x07CA) +-#define PORTQ_INT1MASK _SFR_MEM8(0x07CB) +-#define PORTQ_INTFLAGS _SFR_MEM8(0x07CC) +-#define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0) +-#define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1) +-#define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2) +-#define PORTQ_PIN3CTRL _SFR_MEM8(0x07D3) +-#define PORTQ_PIN4CTRL _SFR_MEM8(0x07D4) +-#define PORTQ_PIN5CTRL _SFR_MEM8(0x07D5) +-#define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6) +-#define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7) +- +-/* PORTR - Port R */ +-#define PORTR_DIR _SFR_MEM8(0x07E0) +-#define PORTR_DIRSET _SFR_MEM8(0x07E1) +-#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +-#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +-#define PORTR_OUT _SFR_MEM8(0x07E4) +-#define PORTR_OUTSET _SFR_MEM8(0x07E5) +-#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +-#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +-#define PORTR_IN _SFR_MEM8(0x07E8) +-#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +-#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +-#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +-#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +-#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +-#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +-#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +-#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +-#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +-#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +-#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +-#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) +- +-/* TCC0 - Timer/Counter C0 */ +-#define TCC0_CTRLA _SFR_MEM8(0x0800) +-#define TCC0_CTRLB _SFR_MEM8(0x0801) +-#define TCC0_CTRLC _SFR_MEM8(0x0802) +-#define TCC0_CTRLD _SFR_MEM8(0x0803) +-#define TCC0_CTRLE _SFR_MEM8(0x0804) +-#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +-#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +-#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +-#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +-#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +-#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +-#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +-#define TCC0_TEMP _SFR_MEM8(0x080F) +-#define TCC0_CNT _SFR_MEM16(0x0820) +-#define TCC0_PER _SFR_MEM16(0x0826) +-#define TCC0_CCA _SFR_MEM16(0x0828) +-#define TCC0_CCB _SFR_MEM16(0x082A) +-#define TCC0_CCC _SFR_MEM16(0x082C) +-#define TCC0_CCD _SFR_MEM16(0x082E) +-#define TCC0_PERBUF _SFR_MEM16(0x0836) +-#define TCC0_CCABUF _SFR_MEM16(0x0838) +-#define TCC0_CCBBUF _SFR_MEM16(0x083A) +-#define TCC0_CCCBUF _SFR_MEM16(0x083C) +-#define TCC0_CCDBUF _SFR_MEM16(0x083E) +- +-/* TCC1 - Timer/Counter C1 */ +-#define TCC1_CTRLA _SFR_MEM8(0x0840) +-#define TCC1_CTRLB _SFR_MEM8(0x0841) +-#define TCC1_CTRLC _SFR_MEM8(0x0842) +-#define TCC1_CTRLD _SFR_MEM8(0x0843) +-#define TCC1_CTRLE _SFR_MEM8(0x0844) +-#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +-#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +-#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +-#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +-#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +-#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +-#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +-#define TCC1_TEMP _SFR_MEM8(0x084F) +-#define TCC1_CNT _SFR_MEM16(0x0860) +-#define TCC1_PER _SFR_MEM16(0x0866) +-#define TCC1_CCA _SFR_MEM16(0x0868) +-#define TCC1_CCB _SFR_MEM16(0x086A) +-#define TCC1_PERBUF _SFR_MEM16(0x0876) +-#define TCC1_CCABUF _SFR_MEM16(0x0878) +-#define TCC1_CCBBUF _SFR_MEM16(0x087A) +- +-/* AWEXC - Advanced Waveform Extension C */ +-#define AWEXC_CTRL _SFR_MEM8(0x0880) +-#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +-#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +-#define AWEXC_STATUS _SFR_MEM8(0x0884) +-#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +-#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +-#define AWEXC_DTLS _SFR_MEM8(0x0888) +-#define AWEXC_DTHS _SFR_MEM8(0x0889) +-#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +-#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +-#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) +- +-/* HIRESC - High-Resolution Extension C */ +-#define HIRESC_CTRLA _SFR_MEM8(0x0890) +- +-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +-#define USARTC0_DATA _SFR_MEM8(0x08A0) +-#define USARTC0_STATUS _SFR_MEM8(0x08A1) +-#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +-#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +-#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +-#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +-#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) +- +-/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ +-#define USARTC1_DATA _SFR_MEM8(0x08B0) +-#define USARTC1_STATUS _SFR_MEM8(0x08B1) +-#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +-#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +-#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +-#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +-#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) +- +-/* SPIC - Serial Peripheral Interface C */ +-#define SPIC_CTRL _SFR_MEM8(0x08C0) +-#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +-#define SPIC_STATUS _SFR_MEM8(0x08C2) +-#define SPIC_DATA _SFR_MEM8(0x08C3) +- +-/* IRCOM - IR Communication Module */ +-#define IRCOM_CTRL _SFR_MEM8(0x08F8) +-#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +-#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) +- +-/* TCD0 - Timer/Counter D0 */ +-#define TCD0_CTRLA _SFR_MEM8(0x0900) +-#define TCD0_CTRLB _SFR_MEM8(0x0901) +-#define TCD0_CTRLC _SFR_MEM8(0x0902) +-#define TCD0_CTRLD _SFR_MEM8(0x0903) +-#define TCD0_CTRLE _SFR_MEM8(0x0904) +-#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +-#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +-#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +-#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +-#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +-#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +-#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +-#define TCD0_TEMP _SFR_MEM8(0x090F) +-#define TCD0_CNT _SFR_MEM16(0x0920) +-#define TCD0_PER _SFR_MEM16(0x0926) +-#define TCD0_CCA _SFR_MEM16(0x0928) +-#define TCD0_CCB _SFR_MEM16(0x092A) +-#define TCD0_CCC _SFR_MEM16(0x092C) +-#define TCD0_CCD _SFR_MEM16(0x092E) +-#define TCD0_PERBUF _SFR_MEM16(0x0936) +-#define TCD0_CCABUF _SFR_MEM16(0x0938) +-#define TCD0_CCBBUF _SFR_MEM16(0x093A) +-#define TCD0_CCCBUF _SFR_MEM16(0x093C) +-#define TCD0_CCDBUF _SFR_MEM16(0x093E) +- +-/* TCD1 - Timer/Counter D1 */ +-#define TCD1_CTRLA _SFR_MEM8(0x0940) +-#define TCD1_CTRLB _SFR_MEM8(0x0941) +-#define TCD1_CTRLC _SFR_MEM8(0x0942) +-#define TCD1_CTRLD _SFR_MEM8(0x0943) +-#define TCD1_CTRLE _SFR_MEM8(0x0944) +-#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +-#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +-#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +-#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +-#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +-#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +-#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +-#define TCD1_TEMP _SFR_MEM8(0x094F) +-#define TCD1_CNT _SFR_MEM16(0x0960) +-#define TCD1_PER _SFR_MEM16(0x0966) +-#define TCD1_CCA _SFR_MEM16(0x0968) +-#define TCD1_CCB _SFR_MEM16(0x096A) +-#define TCD1_PERBUF _SFR_MEM16(0x0976) +-#define TCD1_CCABUF _SFR_MEM16(0x0978) +-#define TCD1_CCBBUF _SFR_MEM16(0x097A) +- +-/* HIRESD - High-Resolution Extension D */ +-#define HIRESD_CTRLA _SFR_MEM8(0x0990) +- +-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +-#define USARTD0_DATA _SFR_MEM8(0x09A0) +-#define USARTD0_STATUS _SFR_MEM8(0x09A1) +-#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +-#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +-#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +-#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +-#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) +- +-/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ +-#define USARTD1_DATA _SFR_MEM8(0x09B0) +-#define USARTD1_STATUS _SFR_MEM8(0x09B1) +-#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +-#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +-#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +-#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +-#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) +- +-/* SPID - Serial Peripheral Interface D */ +-#define SPID_CTRL _SFR_MEM8(0x09C0) +-#define SPID_INTCTRL _SFR_MEM8(0x09C1) +-#define SPID_STATUS _SFR_MEM8(0x09C2) +-#define SPID_DATA _SFR_MEM8(0x09C3) +- +-/* TCE0 - Timer/Counter E0 */ +-#define TCE0_CTRLA _SFR_MEM8(0x0A00) +-#define TCE0_CTRLB _SFR_MEM8(0x0A01) +-#define TCE0_CTRLC _SFR_MEM8(0x0A02) +-#define TCE0_CTRLD _SFR_MEM8(0x0A03) +-#define TCE0_CTRLE _SFR_MEM8(0x0A04) +-#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +-#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +-#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +-#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +-#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +-#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +-#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +-#define TCE0_TEMP _SFR_MEM8(0x0A0F) +-#define TCE0_CNT _SFR_MEM16(0x0A20) +-#define TCE0_PER _SFR_MEM16(0x0A26) +-#define TCE0_CCA _SFR_MEM16(0x0A28) +-#define TCE0_CCB _SFR_MEM16(0x0A2A) +-#define TCE0_CCC _SFR_MEM16(0x0A2C) +-#define TCE0_CCD _SFR_MEM16(0x0A2E) +-#define TCE0_PERBUF _SFR_MEM16(0x0A36) +-#define TCE0_CCABUF _SFR_MEM16(0x0A38) +-#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +-#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +-#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) +- +-/* TCE1 - Timer/Counter E1 */ +-#define TCE1_CTRLA _SFR_MEM8(0x0A40) +-#define TCE1_CTRLB _SFR_MEM8(0x0A41) +-#define TCE1_CTRLC _SFR_MEM8(0x0A42) +-#define TCE1_CTRLD _SFR_MEM8(0x0A43) +-#define TCE1_CTRLE _SFR_MEM8(0x0A44) +-#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) +-#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) +-#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) +-#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) +-#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) +-#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) +-#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) +-#define TCE1_TEMP _SFR_MEM8(0x0A4F) +-#define TCE1_CNT _SFR_MEM16(0x0A60) +-#define TCE1_PER _SFR_MEM16(0x0A66) +-#define TCE1_CCA _SFR_MEM16(0x0A68) +-#define TCE1_CCB _SFR_MEM16(0x0A6A) +-#define TCE1_PERBUF _SFR_MEM16(0x0A76) +-#define TCE1_CCABUF _SFR_MEM16(0x0A78) +-#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) +- +-/* AWEXE - Advanced Waveform Extension E */ +-#define AWEXE_CTRL _SFR_MEM8(0x0A80) +-#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +-#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +-#define AWEXE_STATUS _SFR_MEM8(0x0A84) +-#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +-#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +-#define AWEXE_DTLS _SFR_MEM8(0x0A88) +-#define AWEXE_DTHS _SFR_MEM8(0x0A89) +-#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +-#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +-#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) +- +-/* HIRESE - High-Resolution Extension E */ +-#define HIRESE_CTRLA _SFR_MEM8(0x0A90) +- +-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +-#define USARTE0_DATA _SFR_MEM8(0x0AA0) +-#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +-#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +-#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +-#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +-#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +-#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) +- +-/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ +-#define USARTE1_DATA _SFR_MEM8(0x0AB0) +-#define USARTE1_STATUS _SFR_MEM8(0x0AB1) +-#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) +-#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) +-#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) +-#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) +-#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) +- +-/* SPIE - Serial Peripheral Interface E */ +-#define SPIE_CTRL _SFR_MEM8(0x0AC0) +-#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +-#define SPIE_STATUS _SFR_MEM8(0x0AC2) +-#define SPIE_DATA _SFR_MEM8(0x0AC3) +- +-/* TCF0 - Timer/Counter F0 */ +-#define TCF0_CTRLA _SFR_MEM8(0x0B00) +-#define TCF0_CTRLB _SFR_MEM8(0x0B01) +-#define TCF0_CTRLC _SFR_MEM8(0x0B02) +-#define TCF0_CTRLD _SFR_MEM8(0x0B03) +-#define TCF0_CTRLE _SFR_MEM8(0x0B04) +-#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +-#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +-#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +-#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +-#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +-#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +-#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +-#define TCF0_TEMP _SFR_MEM8(0x0B0F) +-#define TCF0_CNT _SFR_MEM16(0x0B20) +-#define TCF0_PER _SFR_MEM16(0x0B26) +-#define TCF0_CCA _SFR_MEM16(0x0B28) +-#define TCF0_CCB _SFR_MEM16(0x0B2A) +-#define TCF0_CCC _SFR_MEM16(0x0B2C) +-#define TCF0_CCD _SFR_MEM16(0x0B2E) +-#define TCF0_PERBUF _SFR_MEM16(0x0B36) +-#define TCF0_CCABUF _SFR_MEM16(0x0B38) +-#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +-#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +-#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) +- +-/* TCF1 - Timer/Counter F1 */ +-#define TCF1_CTRLA _SFR_MEM8(0x0B40) +-#define TCF1_CTRLB _SFR_MEM8(0x0B41) +-#define TCF1_CTRLC _SFR_MEM8(0x0B42) +-#define TCF1_CTRLD _SFR_MEM8(0x0B43) +-#define TCF1_CTRLE _SFR_MEM8(0x0B44) +-#define TCF1_INTCTRLA _SFR_MEM8(0x0B46) +-#define TCF1_INTCTRLB _SFR_MEM8(0x0B47) +-#define TCF1_CTRLFCLR _SFR_MEM8(0x0B48) +-#define TCF1_CTRLFSET _SFR_MEM8(0x0B49) +-#define TCF1_CTRLGCLR _SFR_MEM8(0x0B4A) +-#define TCF1_CTRLGSET _SFR_MEM8(0x0B4B) +-#define TCF1_INTFLAGS _SFR_MEM8(0x0B4C) +-#define TCF1_TEMP _SFR_MEM8(0x0B4F) +-#define TCF1_CNT _SFR_MEM16(0x0B60) +-#define TCF1_PER _SFR_MEM16(0x0B66) +-#define TCF1_CCA _SFR_MEM16(0x0B68) +-#define TCF1_CCB _SFR_MEM16(0x0B6A) +-#define TCF1_PERBUF _SFR_MEM16(0x0B76) +-#define TCF1_CCABUF _SFR_MEM16(0x0B78) +-#define TCF1_CCBBUF _SFR_MEM16(0x0B7A) +- +-/* HIRESF - High-Resolution Extension F */ +-#define HIRESF_CTRLA _SFR_MEM8(0x0B90) +- +-/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ +-#define USARTF0_DATA _SFR_MEM8(0x0BA0) +-#define USARTF0_STATUS _SFR_MEM8(0x0BA1) +-#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) +-#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) +-#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) +-#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) +-#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) +- +-/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ +-#define USARTF1_DATA _SFR_MEM8(0x0BB0) +-#define USARTF1_STATUS _SFR_MEM8(0x0BB1) +-#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) +-#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) +-#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) +-#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) +-#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) +- +-/* SPIF - Serial Peripheral Interface F */ +-#define SPIF_CTRL _SFR_MEM8(0x0BC0) +-#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) +-#define SPIF_STATUS _SFR_MEM8(0x0BC2) +-#define SPIF_DATA _SFR_MEM8(0x0BC3) +- +- +- +-/*================== Bitfield Definitions ================== */ +- +-/* VPORT - Virtual Ports */ +-/* VPORT.INTFLAGS bit masks and bit positions */ +-#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* XOCD - On-Chip Debug System */ -/* OCD.OCDR1 bit masks and bit positions */ -#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ -#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ - - /* CPU - CPU */ - /* CPU.CCP bit masks and bit positions */ -@@ -4051,7 +4408,6 @@ IO Module Instances. Mapped to memory. - #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ - #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - - - /* CPU.SREG bit masks and bit positions */ - #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ - #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -@@ -4077,7 +4433,6 @@ IO Module Instances. Mapped to memory. - #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ - #define CPU_C_bp 0 /* Carry Flag bit position. */ - - - /* CLK - Clock System */ - /* CLK.CTRL bit masks and bit positions */ - #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -@@ -4089,7 +4444,6 @@ IO Module Instances. Mapped to memory. - #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ - #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - +-/* CPU - CPU */ +-/* CPU.CCP bit masks and bit positions */ +-#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +-#define CPU_CCP_gp 0 /* CCP signature group position. */ +-#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +-#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +-#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +-#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +-#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +-#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +-#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +-#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +-#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +-#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +-#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +-#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +-#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +-#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +-#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +-#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - - /* CLK.PSCTRL bit masks and bit positions */ - #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ - #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -@@ -4111,12 +4465,10 @@ IO Module Instances. Mapped to memory. - #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ - #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - - - /* CLK.LOCK bit masks and bit positions */ - #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ - #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - +-/* CPU.SREG bit masks and bit positions */ +-#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +-#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - - /* CLK.RTCCTRL bit masks and bit positions */ - #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ - #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -@@ -4130,7 +4482,6 @@ IO Module Instances. Mapped to memory. - #define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ - #define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - +-#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +-#define CPU_T_bp 6 /* Transfer Bit bit position. */ +- +-#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +-#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +- +-#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +-#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +- +-#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +-#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +- +-#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +-#define CPU_N_bp 2 /* Negative Flag bit position. */ +- +-#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +-#define CPU_Z_bp 1 /* Zero Flag bit position. */ +- +-#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +-#define CPU_C_bp 0 /* Carry Flag bit position. */ +- +- +-/* CLK - Clock System */ +-/* CLK.CTRL bit masks and bit positions */ +-#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +-#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +-#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +-#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +-#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +-#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +-#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +-#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ +- +- +-/* CLK.PSCTRL bit masks and bit positions */ +-#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +-#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +-#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +-#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +-#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +-#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +-#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +-#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +-#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +-#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +-#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +-#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ +- +-#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +-#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +-#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +-#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +-#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +-#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ +- +- +-/* CLK.LOCK bit masks and bit positions */ +-#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +-#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ +- +- +-/* CLK.RTCCTRL bit masks and bit positions */ +-#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +-#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +-#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +-#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +-#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +-#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +-#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +-#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ +- +-#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +-#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ +- +- +-/* CLK.USBCTRL bit masks and bit positions */ +-#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ +-#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ +-#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ +-#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ +-#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ +-#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ +-#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ +-#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ +- +-#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ +-#define CLK_USBSRC_gp 1 /* Clock Source group position. */ +-#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +-#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ +-#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +-#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - - /* CLK.USBCTRL bit masks and bit positions */ - #define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ - #define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -@@ -4148,9 +4499,8 @@ IO Module Instances. Mapped to memory. - #define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ - #define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - -#define CLK_USBEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBEN_bp 0 /* Clock Source Enable bit position. */ - -+#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ - - /* PR.PRGEN bit masks and bit positions */ - #define PR_USB_bm 0x40 /* USB bit mask. */ -@@ -4171,7 +4521,6 @@ IO Module Instances. Mapped to memory. - #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ - #define PR_DMA_bp 0 /* DMA-Controller bit position. */ - - - /* PR.PRPA bit masks and bit positions */ - #define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ - #define PR_DAC_bp 2 /* Port A DAC bit position. */ -@@ -4182,17 +4531,15 @@ IO Module Instances. Mapped to memory. - #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ - #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - +-/* PR.PRGEN bit masks and bit positions */ +-#define PR_USB_bm 0x40 /* USB bit mask. */ +-#define PR_USB_bp 6 /* USB bit position. */ - - /* PR.PRPB bit masks and bit positions */ +-#define PR_AES_bm 0x10 /* AES bit mask. */ +-#define PR_AES_bp 4 /* AES bit position. */ +- +-#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +-#define PR_EBI_bp 3 /* External Bus Interface bit position. */ +- +-#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +-#define PR_RTC_bp 2 /* Real-time Counter bit position. */ +- +-#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +-#define PR_EVSYS_bp 1 /* Event System bit position. */ +- +-#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +-#define PR_DMA_bp 0 /* DMA-Controller bit position. */ +- +- +-/* PR.PRPA bit masks and bit positions */ +-#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +-#define PR_DAC_bp 2 /* Port A DAC bit position. */ +- +-#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +-#define PR_ADC_bp 1 /* Port A ADC bit position. */ +- +-#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +-#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ +- +- +-/* PR.PRPB bit masks and bit positions */ -/* PR_DAC_bm Predefined. */ -/* PR_DAC_bp Predefined. */ - -/* PR_ADC_bm Predefined. */ -/* PR_ADC_bp Predefined. */ -+/* PR_DAC Predefined. */ -+/* PR_DAC Predefined. */ - +- -/* PR_AC_bm Predefined. */ -/* PR_AC_bp Predefined. */ -+/* PR_ADC Predefined. */ -+/* PR_ADC Predefined. */ - -+/* PR_AC Predefined. */ -+/* PR_AC Predefined. */ - - /* PR.PRPC bit masks and bit positions */ - #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -@@ -4216,75 +4563,71 @@ IO Module Instances. Mapped to memory. - #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ - #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - - - /* PR.PRPD bit masks and bit positions */ --/* PR_TWI_bm Predefined. */ --/* PR_TWI_bp Predefined. */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ - --/* PR_USART1_bm Predefined. */ --/* PR_USART1_bp Predefined. */ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ - --/* PR_USART0_bm Predefined. */ --/* PR_USART0_bp Predefined. */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ - --/* PR_SPI_bm Predefined. */ --/* PR_SPI_bp Predefined. */ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ - --/* PR_HIRES_bm Predefined. */ --/* PR_HIRES_bp Predefined. */ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ - --/* PR_TC1_bm Predefined. */ --/* PR_TC1_bp Predefined. */ - --/* PR_TC0_bm Predefined. */ --/* PR_TC0_bp Predefined. */ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ - -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ - - /* PR.PRPE bit masks and bit positions */ +-/* PR.PRPC bit masks and bit positions */ +-#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +-#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ +- +-#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +-#define PR_USART1_bp 5 /* Port C USART1 bit position. */ +- +-#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +-#define PR_USART0_bp 4 /* Port C USART0 bit position. */ +- +-#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +-#define PR_SPI_bp 3 /* Port C SPI bit position. */ +- +-#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +-#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ +- +-#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +-#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ +- +-#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +-#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ +- +- +-/* PR.PRPD bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ - +- -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ - +- -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ - +- -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ - +- -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ - +- -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ - -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ - - /* PR.PRPF bit masks and bit positions */ +- +- +-/* PR.PRPE bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ - +- -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ - +- -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ - +- -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ - +- -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ - +- -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ - -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ - - /* SLEEP - Sleep Controller */ - /* SLEEP.CTRL bit masks and bit positions */ -@@ -4300,7 +4643,6 @@ IO Module Instances. Mapped to memory. - #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ - #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - - - /* OSC - Oscillator */ - /* OSC.CTRL bit masks and bit positions */ - #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -@@ -4318,7 +4660,6 @@ IO Module Instances. Mapped to memory. - #define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ - #define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - - - /* OSC.STATUS bit masks and bit positions */ - #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ - #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -@@ -4335,7 +4676,6 @@ IO Module Instances. Mapped to memory. - #define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ - #define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - +-/* PR.PRPF bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ - - /* OSC.XOSCCTRL bit masks and bit positions */ - #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ - #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -@@ -4347,6 +4687,9 @@ IO Module Instances. Mapped to memory. - #define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ - #define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ - #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ - #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ - #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -@@ -4358,7 +4701,6 @@ IO Module Instances. Mapped to memory. - #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ - #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ - - /* OSC.XOSCFAIL bit masks and bit positions */ - #define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ - #define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -@@ -4372,7 +4714,6 @@ IO Module Instances. Mapped to memory. - #define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ - #define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ - - /* OSC.PLLCTRL bit masks and bit positions */ - #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ - #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -@@ -4381,6 +4722,9 @@ IO Module Instances. Mapped to memory. - #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ - #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ - #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ - #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ - #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -@@ -4394,25 +4738,22 @@ IO Module Instances. Mapped to memory. - #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ - #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ - - /* OSC.DFLLCTRL bit masks and bit positions */ +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* SLEEP - Sleep Controller */ +-/* SLEEP.CTRL bit masks and bit positions */ +-#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +-#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +-#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +-#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +-#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +-#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +-#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +-#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ +- +-#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +-#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ +- +- +-/* OSC - Oscillator */ +-/* OSC.CTRL bit masks and bit positions */ +-#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +-#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ +- +-#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +-#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ +- +-#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ +- +- +-/* OSC.STATUS bit masks and bit positions */ +-#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +-#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ +- +-#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +-#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ +- +-#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ +- +- +-/* OSC.XOSCCTRL bit masks and bit positions */ +-#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +-#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +-#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +-#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +-#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +-#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ +- +-#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +-#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ +- +-#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +-#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +-#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +-#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +-#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +-#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +-#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +-#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +-#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +-#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +- +- +-/* OSC.XOSCFAIL bit masks and bit positions */ +-#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +-#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ +- +-#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +-#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ +- +-#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +-#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ +- +-#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +-#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ +- +- +-/* OSC.PLLCTRL bit masks and bit positions */ +-#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +-#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +-#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +-#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +-#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +-#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ +- +-#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +-#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +-#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +-#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +-#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +-#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +-#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +-#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +-#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +-#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +-#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +-#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ +- +- +-/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz Calibration Reference bit 0 mask. */ @@ -68080,79 +307008,130 @@ index e8f4163..0b61d9e 100644 - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz Calibration Reference bit position. */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -+#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -+#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - - /* DFLL - DFLL */ - /* DFLL.CTRL bit masks and bit positions */ - #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ - #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - - - /* DFLL.CALA bit masks and bit positions */ - #define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ - #define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -@@ -4431,7 +4772,6 @@ IO Module Instances. Mapped to memory. - #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ - #define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - - - /* DFLL.CALB bit masks and bit positions */ - #define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ - #define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -@@ -4448,7 +4788,6 @@ IO Module Instances. Mapped to memory. - #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ - #define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - +-/* DFLL - DFLL */ +-/* DFLL.CTRL bit masks and bit positions */ +-#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +-#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - - /* RST - Reset */ - /* RST.STATUS bit masks and bit positions */ - #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -@@ -4472,12 +4811,10 @@ IO Module Instances. Mapped to memory. - #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ - #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - - - /* RST.CTRL bit masks and bit positions */ - #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ - #define RST_SWRST_bp 0 /* Software Reset bit position. */ - +-/* DFLL.CALA bit masks and bit positions */ +-#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +-#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +-#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +-#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +-#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +-#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +-#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +-#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +-#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +-#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +-#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +-#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +-#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +-#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +-#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +-#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - - /* WDT - Watch-Dog Timer */ - /* WDT.CTRL bit masks and bit positions */ - #define WDT_PER_gm 0x3C /* Period group mask. */ -@@ -4497,7 +4834,6 @@ IO Module Instances. Mapped to memory. - #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ - #define WDT_CEN_bp 0 /* Change Enable bit position. */ - - - /* WDT.WINCTRL bit masks and bit positions */ - #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ - #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -@@ -4516,33 +4852,29 @@ IO Module Instances. Mapped to memory. - #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ - #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - +-/* DFLL.CALB bit masks and bit positions */ +-#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +-#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +-#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +-#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +-#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +-#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +-#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +-#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +-#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +-#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +-#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +-#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +-#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +-#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - - /* WDT.STATUS bit masks and bit positions */ - #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ - #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - - - /* MCU - MCU Control */ - /* MCU.MCUCR bit masks and bit positions */ - #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ - #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - +-/* RST - Reset */ +-/* RST.STATUS bit masks and bit positions */ +-#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +-#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - - /* MCU.ANAINIT bit masks and bit positions */ +-#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +-#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ +- +-#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +-#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ +- +-#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +-#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ +- +-#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +-#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ +- +-#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +-#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ +- +-#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +-#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ +- +- +-/* RST.CTRL bit masks and bit positions */ +-#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +-#define RST_SWRST_bp 0 /* Software Reset bit position. */ +- +- +-/* WDT - Watch-Dog Timer */ +-/* WDT.CTRL bit masks and bit positions */ +-#define WDT_PER_gm 0x3C /* Period group mask. */ +-#define WDT_PER_gp 2 /* Period group position. */ +-#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +-#define WDT_PER0_bp 2 /* Period bit 0 position. */ +-#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +-#define WDT_PER1_bp 3 /* Period bit 1 position. */ +-#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +-#define WDT_PER2_bp 4 /* Period bit 2 position. */ +-#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +-#define WDT_PER3_bp 5 /* Period bit 3 position. */ +- +-#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +-#define WDT_ENABLE_bp 1 /* Enable bit position. */ +- +-#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +-#define WDT_CEN_bp 0 /* Change Enable bit position. */ +- +- +-/* WDT.WINCTRL bit masks and bit positions */ +-#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +-#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +-#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +-#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +-#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +-#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +-#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +-#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +-#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +-#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ +- +-#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +-#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ +- +-#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +-#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ +- +- +-/* WDT.STATUS bit masks and bit positions */ +-#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +-#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +- +- +-/* MCU - MCU Control */ +-/* MCU.MCUCR bit masks and bit positions */ +-#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +-#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ +- +- +-/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port A bit 0 mask. */ @@ -68167,164 +307146,180 @@ index e8f4163..0b61d9e 100644 -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port B bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port B bit 1 position. */ - -+#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -+#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -+#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -+#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -+#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -+#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ -+ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - - /* MCU.EVSYSLOCK bit masks and bit positions */ - #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -@@ -4551,15 +4883,19 @@ IO Module Instances. Mapped to memory. - #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ - #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - - - /* MCU.AWEXLOCK bit masks and bit positions */ -+#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ -+#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ -+ - #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ - #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -+#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ -+#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ -+ - #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ - #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - +-/* MCU.EVSYSLOCK bit masks and bit positions */ +-#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +-#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - - /* PMIC - Programmable Multi-level Interrupt Controller */ - /* PMIC.STATUS bit masks and bit positions */ - #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -@@ -4574,6 +4910,25 @@ IO Module Instances. Mapped to memory. - #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ - #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - - /* PMIC.CTRL bit masks and bit positions */ - #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -@@ -4591,7 +4946,6 @@ IO Module Instances. Mapped to memory. - #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ - #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - +-#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +-#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - - /* PORTCFG - Port Configuration */ - /* PORTCFG.VPCTRLA bit masks and bit positions */ - #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -@@ -4616,7 +4970,6 @@ IO Module Instances. Mapped to memory. - #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ - #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - - - /* PORTCFG.VPCTRLB bit masks and bit positions */ - #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ - #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -@@ -4640,7 +4993,6 @@ IO Module Instances. Mapped to memory. - #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ - #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - +-/* MCU.AWEXLOCK bit masks and bit positions */ +-#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +-#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - - /* PORTCFG.CLKEVOUT bit masks and bit positions */ - #define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ - #define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -@@ -4669,6 +5021,30 @@ IO Module Instances. Mapped to memory. - #define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ - #define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -+/* PORTCFG.EBIOUT bit masks and bit positions */ -+#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ -+#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ -+#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ -+#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ -+#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ -+#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ -+ -+#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ -+#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ -+#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ -+#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ -+#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ -+#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ -+ -+/* PORTCFG.EVOUTSEL bit masks and bit positions */ -+#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -+#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -+#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -+#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -+#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -+#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -+#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -+#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ - - /* AES - AES Module */ - /* AES.CTRL bit masks and bit positions */ -@@ -4687,7 +5063,6 @@ IO Module Instances. Mapped to memory. - #define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ - #define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - +-#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +-#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - - /* AES.STATUS bit masks and bit positions */ - #define AES_ERROR_bm 0x80 /* AES Error bit mask. */ - #define AES_ERROR_bp 7 /* AES Error bit position. */ -@@ -4695,7 +5070,6 @@ IO Module Instances. Mapped to memory. - #define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ - #define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - - - /* AES.INTCTRL bit masks and bit positions */ - #define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ - #define AES_INTLVL_gp 0 /* Interrupt level group position. */ -@@ -4704,38 +5078,35 @@ IO Module Instances. Mapped to memory. - #define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ - #define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - +-/* PMIC - Programmable Multi-level Interrupt Controller */ +-/* PMIC.STATUS bit masks and bit positions */ +-#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +-#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - - /* CRC - Cyclic Redundancy Checker */ - /* CRC.CTRL bit masks and bit positions */ +-#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +-#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ +- +-#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +-#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ +- +-#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +-#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ +- +- +-/* PMIC.CTRL bit masks and bit positions */ +-#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +-#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ +- +-#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +-#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ +- +-#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +-#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ +- +-#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +-#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ +- +-#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +-#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ +- +- +-/* PORTCFG - Port Configuration */ +-/* PORTCFG.VPCTRLA bit masks and bit positions */ +-#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +-#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +-#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +-#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +-#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +-#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +-#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +-#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +-#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +-#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ +- +-#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +-#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +-#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +-#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +-#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +-#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +-#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +-#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +-#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +-#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ +- +- +-/* PORTCFG.VPCTRLB bit masks and bit positions */ +-#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +-#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +-#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +-#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +-#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +-#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +-#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +-#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +-#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +-#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ +- +-#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +-#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +-#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +-#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +-#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +-#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +-#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +-#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +-#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +-#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ +- +- +-/* PORTCFG.CLKEVOUT bit masks and bit positions */ +-#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +-#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +-#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +-#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +-#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +-#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ +- +-#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +-#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +-#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +-#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +-#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +-#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ +- +-#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +-#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +-#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +-#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +-#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +-#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ +- +-#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +-#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ +- +-#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +-#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ +- +- +-/* AES - AES Module */ +-/* AES.CTRL bit masks and bit positions */ +-#define AES_START_bm 0x80 /* Start/Run bit mask. */ +-#define AES_START_bp 7 /* Start/Run bit position. */ +- +-#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +-#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ +- +-#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +-#define AES_RESET_bp 5 /* AES Software Reset bit position. */ +- +-#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +-#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ +- +-#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +-#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ +- +- +-/* AES.STATUS bit masks and bit positions */ +-#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +-#define AES_ERROR_bp 7 /* AES Error bit position. */ +- +-#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +-#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ +- +- +-/* AES.INTCTRL bit masks and bit positions */ +-#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +-#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +-/* CRC - Cyclic Redundancy Checker */ +-/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* CRC Reset group mask. */ -#define CRC_RESET_gp 6 /* CRC Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* CRC Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* CRC Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* CRC Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* CRC Reset bit 1 position. */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - - #define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ - #define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - +- +-#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +-#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ +- -#define CRC_SOURCE_gm 0x0F /* CRC Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* CRC Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* CRC Input Source bit 0 mask. */ @@ -68336,93 +307331,216 @@ index e8f4163..0b61d9e 100644 -#define CRC_SOURCE3_bm (1<<3) /* CRC Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* CRC Input Source bit 3 position. */ - -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - - /* CRC.STATUS bit masks and bit positions */ +- +-/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero CRC detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero CRC detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Enable bit mask. */ -#define CRC_BUSY_bp 0 /* Enable bit position. */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ - - /* DMA - DMA Controller */ - /* DMA_CH.CTRLA bit masks and bit positions */ -@@ -4761,7 +5132,6 @@ IO Module Instances. Mapped to memory. - #define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ - #define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - - - /* DMA_CH.CTRLB bit masks and bit positions */ - #define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ - #define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ -@@ -4789,7 +5159,6 @@ IO Module Instances. Mapped to memory. - #define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ - #define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - - - /* DMA_CH.ADDRCTRL bit masks and bit positions */ - #define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ - #define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -@@ -4819,7 +5188,6 @@ IO Module Instances. Mapped to memory. - #define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ - #define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - +-/* DMA - DMA Controller */ +-/* DMA_CH.CTRLA bit masks and bit positions */ +-#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +-#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - - /* DMA_CH.TRIGSRC bit masks and bit positions */ - #define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ - #define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -@@ -4840,7 +5208,6 @@ IO Module Instances. Mapped to memory. - #define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ - #define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - +-#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +-#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - - /* DMA.CTRL bit masks and bit positions */ - #define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ - #define DMA_ENABLE_bp 7 /* Enable bit position. */ -@@ -4862,7 +5229,6 @@ IO Module Instances. Mapped to memory. - #define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ - #define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ - +-#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +-#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - - /* DMA.INTFLAGS bit masks and bit positions */ - #define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ - #define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ -@@ -4888,7 +5254,6 @@ IO Module Instances. Mapped to memory. - #define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ - #define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - +-#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +-#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - - /* DMA.STATUS bit masks and bit positions */ - #define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ - #define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ -@@ -4914,7 +5279,6 @@ IO Module Instances. Mapped to memory. - #define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ - #define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - +-#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +-#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - - /* EVSYS - Event System */ - /* EVSYS.CH0MUX bit masks and bit positions */ - #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -@@ -4936,153 +5300,33 @@ IO Module Instances. Mapped to memory. - #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ - #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - +-#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +-#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +-#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +-#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +-#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +-#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - - /* EVSYS.CH1MUX bit masks and bit positions */ +- +-/* DMA_CH.CTRLB bit masks and bit positions */ +-#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +-#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ +- +-#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +-#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ +- +-#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +-#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ +- +-#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +-#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +-#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +-#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +-#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +-#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ +- +-#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +-#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +-#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +-#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +-#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +-#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ +- +- +-/* DMA_CH.ADDRCTRL bit masks and bit positions */ +-#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +-#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +-#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +-#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +-#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +-#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ +- +-#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +-#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +-#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +-#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +-#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +-#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ +- +-#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +-#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +-#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +-#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +-#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +-#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ +- +-#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +-#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +-#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +-#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +-#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +-#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ +- +- +-/* DMA_CH.TRIGSRC bit masks and bit positions */ +-#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +-#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +-#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +-#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +-#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +-#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +-#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +-#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +-#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +-#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +-#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +-#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +-#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +-#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +-#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +-#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +-#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +-#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ +- +- +-/* DMA.CTRL bit masks and bit positions */ +-#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +-#define DMA_ENABLE_bp 7 /* Enable bit position. */ +- +-#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +-#define DMA_RESET_bp 6 /* Software Reset bit position. */ +- +-#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +-#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +-#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +-#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +-#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +-#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ +- +-#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +-#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +-#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +-#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +-#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +-#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ +- +- +-/* DMA.INTFLAGS bit masks and bit positions */ +-#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ +- +- +-/* DMA.STATUS bit masks and bit positions */ +-#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +-#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ +- +-#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +-#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ +- +-#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +-#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ +- +-#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +-#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ +- +-#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +-#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ +- +-#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +-#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ +- +-#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +-#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ +- +-#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +-#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ +- +- +-/* EVSYS - Event System */ +-/* EVSYS.CH0MUX bit masks and bit positions */ +-#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +-#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +-#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +-#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +-#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +-#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +-#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +-#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +-#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +-#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +-#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +-#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +-#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +-#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +-#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +-#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +-#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +-#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ +- +- +-/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ @@ -68442,10 +307560,8 @@ index e8f4163..0b61d9e 100644 -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ - - /* EVSYS.CH2MUX bit masks and bit positions */ +- +-/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ @@ -68465,10 +307581,8 @@ index e8f4163..0b61d9e 100644 -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ - - /* EVSYS.CH3MUX bit masks and bit positions */ +- +-/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ @@ -68488,10 +307602,8 @@ index e8f4163..0b61d9e 100644 -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ - - /* EVSYS.CH4MUX bit masks and bit positions */ +- +-/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ @@ -68511,10 +307623,8 @@ index e8f4163..0b61d9e 100644 -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ - - /* EVSYS.CH5MUX bit masks and bit positions */ +- +-/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ @@ -68534,10 +307644,8 @@ index e8f4163..0b61d9e 100644 -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ - - /* EVSYS.CH6MUX bit masks and bit positions */ +- +-/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ @@ -68557,10 +307665,8 @@ index e8f4163..0b61d9e 100644 -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ - - /* EVSYS.CH7MUX bit masks and bit positions */ +- +-/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ @@ -68580,17 +307686,32 @@ index e8f4163..0b61d9e 100644 -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ - - /* EVSYS.CH0CTRL bit masks and bit positions */ - #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -@@ -5107,109 +5351,51 @@ IO Module Instances. Mapped to memory. - #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ - #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - - - /* EVSYS.CH1CTRL bit masks and bit positions */ +-/* EVSYS.CH0CTRL bit masks and bit positions */ +-#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +-#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +-#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +-#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +-#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +-#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ +- +-#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +-#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ +- +-#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +-#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ +- +-#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +-#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +-#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +-#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +-#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +-#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +-#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +-#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ +- +- +-/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ @@ -68600,10 +307721,8 @@ index e8f4163..0b61d9e 100644 -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ - - /* EVSYS.CH2CTRL bit masks and bit positions */ +- +-/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ @@ -68613,29 +307732,10 @@ index e8f4163..0b61d9e 100644 - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ -+/* EVSYS_QDIRM Predefined. */ -+/* EVSYS_QDIRM Predefined. */ - +- -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ -+/* EVSYS_QDIEN Predefined. */ -+/* EVSYS_QDIEN Predefined. */ - --/* EVSYS_DIGFILT_gm Predefined. */ --/* EVSYS_DIGFILT_gp Predefined. */ --/* EVSYS_DIGFILT0_bm Predefined. */ --/* EVSYS_DIGFILT0_bp Predefined. */ --/* EVSYS_DIGFILT1_bm Predefined. */ --/* EVSYS_DIGFILT1_bp Predefined. */ --/* EVSYS_DIGFILT2_bm Predefined. */ --/* EVSYS_DIGFILT2_bp Predefined. */ -+/* EVSYS_QDEN Predefined. */ -+/* EVSYS_QDEN Predefined. */ - -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ - - /* EVSYS.CH3CTRL bit masks and bit positions */ +- -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ @@ -68645,10 +307745,19 @@ index e8f4163..0b61d9e 100644 -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ - - /* EVSYS.CH4CTRL bit masks and bit positions */ +- +-/* EVSYS.CH3CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ @@ -68658,29 +307767,10 @@ index e8f4163..0b61d9e 100644 - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ -+/* EVSYS_QDIRM Predefined. */ -+/* EVSYS_QDIRM Predefined. */ - +- -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ -+/* EVSYS_QDIEN Predefined. */ -+/* EVSYS_QDIEN Predefined. */ - --/* EVSYS_DIGFILT_gm Predefined. */ --/* EVSYS_DIGFILT_gp Predefined. */ --/* EVSYS_DIGFILT0_bm Predefined. */ --/* EVSYS_DIGFILT0_bp Predefined. */ --/* EVSYS_DIGFILT1_bm Predefined. */ --/* EVSYS_DIGFILT1_bp Predefined. */ --/* EVSYS_DIGFILT2_bm Predefined. */ --/* EVSYS_DIGFILT2_bp Predefined. */ -+/* EVSYS_QDEN Predefined. */ -+/* EVSYS_QDEN Predefined. */ - -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ - - /* EVSYS.CH5CTRL bit masks and bit positions */ +- -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ @@ -68690,10 +307780,8 @@ index e8f4163..0b61d9e 100644 -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ - - /* EVSYS.CH6CTRL bit masks and bit positions */ +- +-/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ @@ -68703,10 +307791,8 @@ index e8f4163..0b61d9e 100644 -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ - - /* EVSYS.CH7CTRL bit masks and bit positions */ +- +-/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ @@ -68716,207 +307802,370 @@ index e8f4163..0b61d9e 100644 -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ - - /* NVM - Non Volatile Memory Controller */ - /* NVM.CMD bit masks and bit positions */ -@@ -5230,12 +5416,10 @@ IO Module Instances. Mapped to memory. - #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ - #define NVM_CMD6_bp 6 /* Command bit 6 position. */ - - - /* NVM.CTRLA bit masks and bit positions */ - #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ - #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - +-/* EVSYS.CH7CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ - - /* NVM.CTRLB bit masks and bit positions */ - #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ - #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ -@@ -5249,7 +5433,6 @@ IO Module Instances. Mapped to memory. - #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ - #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - - - /* NVM.INTCTRL bit masks and bit positions */ - #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ - #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -@@ -5265,7 +5448,6 @@ IO Module Instances. Mapped to memory. - #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ - #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - +-/* NVM - Non Volatile Memory Controller */ +-/* NVM.CMD bit masks and bit positions */ +-#define NVM_CMD_gm 0x7F /* Command group mask. */ +-#define NVM_CMD_gp 0 /* Command group position. */ +-#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +-#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +-#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +-#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +-#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +-#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +-#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +-#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +-#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +-#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +-#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +-#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - - /* NVM.STATUS bit masks and bit positions */ - #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ - #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -@@ -5279,7 +5461,6 @@ IO Module Instances. Mapped to memory. - #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ - #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - - - /* NVM.LOCKBITS bit masks and bit positions */ - #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ - #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -@@ -5309,7 +5490,6 @@ IO Module Instances. Mapped to memory. - #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ - #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - +-/* NVM.CTRLA bit masks and bit positions */ +-#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +-#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - - /* ADC - Analog/Digital Converter */ - /* ADC_CH.CTRL bit masks and bit positions */ - #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -@@ -5331,7 +5511,6 @@ IO Module Instances. Mapped to memory. - #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ - #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - - - /* ADC_CH.MUXCTRL bit masks and bit positions */ - #define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ - #define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -@@ -5355,13 +5534,14 @@ IO Module Instances. Mapped to memory. - #define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ - #define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - +-/* NVM.CTRLB bit masks and bit positions */ +-#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +-#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ +- +-#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +-#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ +- +-#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +-#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ +- +-#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +-#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ +- +- +-/* NVM.INTCTRL bit masks and bit positions */ +-#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +-#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +-#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +-#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +-#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +-#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ +- +-#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +-#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +-#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +-#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +-#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +-#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ +- +- +-/* NVM.STATUS bit masks and bit positions */ +-#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +-#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ +- +-#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +-#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ +- +-#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +-#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ +- +-#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +-#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ +- +- +-/* NVM.LOCKBITS bit masks and bit positions */ +-#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* ADC - Analog/Digital Converter */ +-/* ADC_CH.CTRL bit masks and bit positions */ +-#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +-#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ +- +-#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +-#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +-#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +-#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +-#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +-#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +-#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +-#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ +- +-#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +-#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +-#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +-#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +-#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +-#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ +- +- +-/* ADC_CH.MUXCTRL bit masks and bit positions */ +-#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +-#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +-#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +-#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +-#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +-#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +-#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +-#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +-#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +-#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ +- +-#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +-#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +-#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +-#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +-#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +-#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +-#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +-#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +-#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +-#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ +- -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -+#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ - #define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ - #define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ - #define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ - #define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ - #define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ +-#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +-#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +-#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +-#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +-#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ - -+#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ -+#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ - - /* ADC_CH.INTCTRL bit masks and bit positions */ - #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -@@ -5378,11 +5558,32 @@ IO Module Instances. Mapped to memory. - #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ - #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - - - /* ADC_CH.INTFLAGS bit masks and bit positions */ - #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ - #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -+#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -+#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -+#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -+#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -+#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -+#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -+#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -+#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -+#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ -+ -+#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -+#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -+#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -+#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -+#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -+#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -+#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -+#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -+#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -+#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ - - /* ADC.CTRLA bit masks and bit positions */ - #define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -@@ -5410,17 +5611,16 @@ IO Module Instances. Mapped to memory. - #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ - #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - +-/* ADC_CH.INTCTRL bit masks and bit positions */ +-#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +-#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +-#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +-#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +-#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +-#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ +- +-#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +-#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +-#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +-#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +-#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +-#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ +- +- +-/* ADC_CH.INTFLAGS bit masks and bit positions */ +-#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +-#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ +- +- +-/* ADC.CTRLA bit masks and bit positions */ +-#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +-#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +-#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +-#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +-#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +-#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ +- +-#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +-#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ +- +-#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +-#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ +- +-#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +-#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ +- +-#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +-#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ +- +-#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +-#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ +- +-#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +-#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ +- +- +-/* ADC.CTRLB bit masks and bit positions */ +-#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ +-#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ - - /* ADC.CTRLB bit masks and bit positions */ - #define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ - #define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ - -#define ADC_CURRENT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRENT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRENT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRENT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRENT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRENT1_bp 6 /* Current Limitation bit 1 position. */ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - - #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ - #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -@@ -5435,7 +5635,6 @@ IO Module Instances. Mapped to memory. - #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ - #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - - - /* ADC.REFCTRL bit masks and bit positions */ - #define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ - #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -@@ -5452,7 +5651,6 @@ IO Module Instances. Mapped to memory. - #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ - #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - +-#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +-#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - - /* ADC.EVCTRL bit masks and bit positions */ - #define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ - #define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -@@ -5479,7 +5677,6 @@ IO Module Instances. Mapped to memory. - #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ - #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - +-#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +-#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - - /* ADC.PRESCALER bit masks and bit positions */ - #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ - #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -@@ -5490,7 +5687,6 @@ IO Module Instances. Mapped to memory. - #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ - #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - +-#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +-#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +-#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +-#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +-#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +-#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - - /* ADC.INTFLAGS bit masks and bit positions */ - #define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ - #define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ -@@ -5504,7 +5700,6 @@ IO Module Instances. Mapped to memory. - #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ - #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - - - /* DAC - Digital/Analog Converter */ - /* DAC.CTRLA bit masks and bit positions */ - #define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -@@ -5522,7 +5717,6 @@ IO Module Instances. Mapped to memory. - #define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ - #define DAC_ENABLE_bp 0 /* Enable bit position. */ - +-/* ADC.REFCTRL bit masks and bit positions */ +-#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +-#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +-#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +-#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +-#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +-#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +-#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +-#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - - /* DAC.CTRLB bit masks and bit positions */ - #define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ - #define DAC_CHSEL_gp 5 /* Channel Select group position. */ -@@ -5537,7 +5731,6 @@ IO Module Instances. Mapped to memory. - #define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ - #define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - +-#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +-#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - - /* DAC.CTRLC bit masks and bit positions */ - #define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ - #define DAC_REFSEL_gp 3 /* Reference Select group position. */ -@@ -5549,7 +5742,6 @@ IO Module Instances. Mapped to memory. - #define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ - #define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - +-#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +-#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ +- +- +-/* ADC.EVCTRL bit masks and bit positions */ +-#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +-#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +-#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +-#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +-#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +-#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ +- +-#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +-#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +-#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +-#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +-#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +-#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +-#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +-#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ +- +-#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +-#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +-#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +-#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +-#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +-#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +-#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +-#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ +- +- +-/* ADC.PRESCALER bit masks and bit positions */ +-#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +-#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +-#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +-#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +-#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +-#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +-#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +-#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ +- +- +-/* ADC.INTFLAGS bit masks and bit positions */ +-#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +-#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ +- +-#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +-#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ +- +-#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +-#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ +- +-#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +-#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ +- +- +-/* DAC - Digital/Analog Converter */ +-/* DAC.CTRLA bit masks and bit positions */ +-#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +-#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ +- +-#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +-#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ +- +-#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +-#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ +- +-#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +-#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ +- +-#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define DAC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* DAC.CTRLB bit masks and bit positions */ +-#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +-#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +-#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +-#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +-#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +-#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ +- +-#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +-#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ +- +-#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +-#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ +- +- +-/* DAC.CTRLC bit masks and bit positions */ +-#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +-#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +-#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +-#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +-#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +-#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ +- +-#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +-#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ +- +- +-/* DAC.EVCTRL bit masks and bit positions */ +-#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ +-#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ +- +-#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +-#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +-#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +-#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +-#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +-#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +-#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +-#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - - /* DAC.EVCTRL bit masks and bit positions */ - #define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ - #define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ -@@ -5563,29 +5755,6 @@ IO Module Instances. Mapped to memory. - #define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ - #define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - - -/* DAC.TIMCTRL bit masks and bit positions */ -#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ @@ -68940,55 +308189,121 @@ index e8f4163..0b61d9e 100644 -#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ - - - /* DAC.STATUS bit masks and bit positions */ - #define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ - #define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ -@@ -5593,7 +5762,6 @@ IO Module Instances. Mapped to memory. - #define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ - #define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - +-/* DAC.STATUS bit masks and bit positions */ +-#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +-#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - - /* DAC.CH0GAINCAL bit masks and bit positions */ - #define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ - #define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -@@ -5612,7 +5780,6 @@ IO Module Instances. Mapped to memory. - #define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ - #define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - +-#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +-#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - - /* DAC.CH0OFFSETCAL bit masks and bit positions */ - #define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ - #define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -@@ -5631,7 +5798,6 @@ IO Module Instances. Mapped to memory. - #define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ - #define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - - - /* DAC.CH1GAINCAL bit masks and bit positions */ - #define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ - #define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -@@ -5650,7 +5816,6 @@ IO Module Instances. Mapped to memory. - #define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ - #define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - +-/* DAC.CH0GAINCAL bit masks and bit positions */ +-#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +-#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ +-#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +-#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +-#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +-#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +-#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +-#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +-#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +-#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +-#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +-#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +-#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +-#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +-#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +-#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - - /* DAC.CH1OFFSETCAL bit masks and bit positions */ - #define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ - #define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -@@ -5669,7 +5834,6 @@ IO Module Instances. Mapped to memory. - #define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ - #define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - - - /* AC - Analog Comparator */ - /* AC.AC0CTRL bit masks and bit positions */ - #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -@@ -5699,35 +5863,21 @@ IO Module Instances. Mapped to memory. - #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ - #define AC_ENABLE_bp 0 /* Enable bit position. */ - +-/* DAC.CH0OFFSETCAL bit masks and bit positions */ +-#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +-#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ +-#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +-#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +-#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +-#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +-#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +-#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +-#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +-#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +-#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +-#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +-#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +-#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +-#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +-#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - - /* AC.AC1CTRL bit masks and bit positions */ +- +-/* DAC.CH1GAINCAL bit masks and bit positions */ +-#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +-#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ +-#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +-#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +-#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +-#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +-#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +-#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +-#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +-#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +-#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +-#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +-#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +-#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +-#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +-#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ +- +- +-/* DAC.CH1OFFSETCAL bit masks and bit positions */ +-#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +-#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ +-#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +-#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +-#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +-#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +-#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +-#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +-#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +-#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +-#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +-#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +-#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +-#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +-#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +-#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ +- +- +-/* AC - Analog Comparator */ +-/* AC.AC0CTRL bit masks and bit positions */ +-#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +-#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +-#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +-#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +-#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +-#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ +- +-#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +-#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +-#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +-#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +-#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +-#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ +- +-#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +-#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ +- +-#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +-#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +-#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +-#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +-#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +-#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +- +-#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define AC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE_gm Predefined. */ -/* AC_INTMODE_gp Predefined. */ -/* AC_INTMODE0_bm Predefined. */ @@ -69015,29 +308330,29 @@ index e8f4163..0b61d9e 100644 - -/* AC_ENABLE_bm Predefined. */ -/* AC_ENABLE_bp Predefined. */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HSMODE Predefined. */ -+/* AC_HSMODE Predefined. */ - -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ - - /* AC.AC0MUXCTRL bit masks and bit positions */ - #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -@@ -5748,32 +5898,20 @@ IO Module Instances. Mapped to memory. - #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ - #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - - - /* AC.AC1MUXCTRL bit masks and bit positions */ +- +-/* AC.AC0MUXCTRL bit masks and bit positions */ +-#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +-#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +-#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +-#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +-#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +-#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +-#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +-#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ +- +-#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +-#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +-#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +-#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +-#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +-#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +-#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +-#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ +- +- +-/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS_gm Predefined. */ -/* AC_MUXPOS_gp Predefined. */ -/* AC_MUXPOS0_bm Predefined. */ @@ -69055,77 +308370,116 @@ index e8f4163..0b61d9e 100644 -/* AC_MUXNEG1_bp Predefined. */ -/* AC_MUXNEG2_bm Predefined. */ -/* AC_MUXNEG2_bp Predefined. */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ - -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ - - /* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ - #define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ - #define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - - - /* AC.CTRLB bit masks and bit positions */ - #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ - #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -@@ -5790,7 +5928,6 @@ IO Module Instances. Mapped to memory. - #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ - #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - - - /* AC.WINCTRL bit masks and bit positions */ - #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ - #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -@@ -5809,7 +5946,6 @@ IO Module Instances. Mapped to memory. - #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ - #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - +-/* AC.CTRLA bit masks and bit positions */ +-#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +-#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ +- +- +-/* AC.CTRLB bit masks and bit positions */ +-#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +-#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +-#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +-#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +-#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +-#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +-#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +-#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +-#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +-#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +-#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +-#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +-#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +-#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ +- +- +-/* AC.WINCTRL bit masks and bit positions */ +-#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +-#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ +- +-#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +-#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +-#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +-#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +-#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +-#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ +- +-#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +-#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +-#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +-#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +-#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +-#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ +- +- +-/* AC.STATUS bit masks and bit positions */ +-#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +-#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +-#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +-#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +-#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +-#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ +- +-#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +-#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ +- +-#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +-#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ +- +-#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +-#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ +- +-#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +-#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ +- +-#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +-#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - - /* AC.STATUS bit masks and bit positions */ - #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ - #define AC_WSTATE_gp 6 /* Window Mode State group position. */ -@@ -5833,8 +5969,7 @@ IO Module Instances. Mapped to memory. - #define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ - #define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - - -/* RTC - Real-Time Clounter */ -+/* RTC - Real-Time Counter */ - /* RTC.CTRL bit masks and bit positions */ - #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ - #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -@@ -5845,12 +5980,10 @@ IO Module Instances. Mapped to memory. - #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ - #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - +-/* RTC.CTRL bit masks and bit positions */ +-#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +-#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +-#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +-#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +-#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +-#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +-#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +-#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - - /* RTC.STATUS bit masks and bit positions */ - #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ - #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - - - /* RTC.INTCTRL bit masks and bit positions */ - #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ - #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -@@ -5866,7 +5999,6 @@ IO Module Instances. Mapped to memory. - #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ - #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - +-/* RTC.STATUS bit masks and bit positions */ +-#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +-#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - - /* RTC.INTFLAGS bit masks and bit positions */ - #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ - #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -@@ -5874,21 +6006,20 @@ IO Module Instances. Mapped to memory. - #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ - #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - - /* EBI - External Bus Interface */ - /* EBI_CS.CTRLA bit masks and bit positions */ +-/* RTC.INTCTRL bit masks and bit positions */ +-#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +-#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +-#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +-#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +-#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +-#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ +- +-#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +-#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +-#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +-#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +-#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +-#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ +- +- +-/* RTC.INTFLAGS bit masks and bit positions */ +-#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +-#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ +- +-#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* EBI - External Bus Interface */ +-/* EBI_CS.CTRLA bit masks and bit positions */ -#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ -#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ -#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ @@ -69138,202 +308492,356 @@ index e8f4163..0b61d9e 100644 -#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ -#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ -#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ -+#define EBI_CS_ASPACE_gm 0x7C /* Address Space group mask. */ -+#define EBI_CS_ASPACE_gp 2 /* Address Space group position. */ -+#define EBI_CS_ASPACE0_bm (1<<2) /* Address Space bit 0 mask. */ -+#define EBI_CS_ASPACE0_bp 2 /* Address Space bit 0 position. */ -+#define EBI_CS_ASPACE1_bm (1<<3) /* Address Space bit 1 mask. */ -+#define EBI_CS_ASPACE1_bp 3 /* Address Space bit 1 position. */ -+#define EBI_CS_ASPACE2_bm (1<<4) /* Address Space bit 2 mask. */ -+#define EBI_CS_ASPACE2_bp 4 /* Address Space bit 2 position. */ -+#define EBI_CS_ASPACE3_bm (1<<5) /* Address Space bit 3 mask. */ -+#define EBI_CS_ASPACE3_bp 5 /* Address Space bit 3 position. */ -+#define EBI_CS_ASPACE4_bm (1<<6) /* Address Space bit 4 mask. */ -+#define EBI_CS_ASPACE4_bp 6 /* Address Space bit 4 position. */ - - #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ - #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ -@@ -5897,7 +6028,6 @@ IO Module Instances. Mapped to memory. - #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ - #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ - - - /* EBI_CS.CTRLB bit masks and bit positions */ - #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ - #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ -@@ -5921,7 +6051,6 @@ IO Module Instances. Mapped to memory. - #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ - #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ - +-#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +-#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +-#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +-#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +-#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +-#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ - - /* EBI.CTRL bit masks and bit positions */ - #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ - #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ -@@ -5951,7 +6080,6 @@ IO Module Instances. Mapped to memory. - #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ - #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ - - - /* EBI.SDRAMCTRLA bit masks and bit positions */ - #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ - #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ -@@ -5966,7 +6094,6 @@ IO Module Instances. Mapped to memory. - #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ - #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ - +-/* EBI_CS.CTRLB bit masks and bit positions */ +-#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +-#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +-#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +-#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +-#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +-#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +-#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +-#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ - - /* EBI.SDRAMCTRLB bit masks and bit positions */ - #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ - #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ -@@ -5993,7 +6120,6 @@ IO Module Instances. Mapped to memory. - #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ - #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ - +-#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +-#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ - - /* EBI.SDRAMCTRLC bit masks and bit positions */ - #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ - #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ -@@ -6020,7 +6146,6 @@ IO Module Instances. Mapped to memory. - #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ - #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ - +-#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +-#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ - - /* TWI - Two-Wire Interface */ - /* TWI_MASTER.CTRLA bit masks and bit positions */ - #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -@@ -6039,14 +6164,13 @@ IO Module Instances. Mapped to memory. - #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ - #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - +-#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +-#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +-#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +-#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +-#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +-#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ - - /* TWI_MASTER.CTRLB bit masks and bit positions */ +- +-/* EBI.CTRL bit masks and bit positions */ +-#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +-#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +-#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +-#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +-#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +-#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ +- +-#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +-#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +-#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +-#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +-#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +-#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ +- +-#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +-#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +-#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +-#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +-#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +-#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ +- +-#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +-#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +-#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +-#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +-#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +-#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLA bit masks and bit positions */ +-#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +-#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ +- +-#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +-#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ +- +-#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +-#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +-#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +-#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +-#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +-#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLB bit masks and bit positions */ +-#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +-#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +-#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +-#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +-#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +-#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ +- +-#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +-#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +-#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +-#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +-#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +-#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +-#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +-#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ +- +-#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +-#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +-#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +-#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +-#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +-#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +-#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +-#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ +- +- +-/* EBI.SDRAMCTRLC bit masks and bit positions */ +-#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +-#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +-#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +-#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +-#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +-#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ +- +-#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +-#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +-#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +-#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +-#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +-#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +-#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +-#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ +- +-#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +-#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +-#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +-#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +-#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +-#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +-#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +-#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ +- +- +-/* TWI - Two-Wire Interface */ +-/* TWI_MASTER.CTRLA bit masks and bit positions */ +-#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +-#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ +- +-#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +-#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ +- +-#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +-#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ +- +- +-/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Tisdahmeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Tisdahmeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Tisdahmeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Tisdahmeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Tisdahmeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Tisdahmeout bit 1 position. */ - - #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ - #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -@@ -6054,7 +6178,6 @@ IO Module Instances. Mapped to memory. - #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ - #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - - /* TWI_MASTER.CTRLC bit masks and bit positions */ - #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ - #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -@@ -6066,7 +6189,6 @@ IO Module Instances. Mapped to memory. - #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ - #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - +-#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +-#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - - /* TWI_MASTER.STATUS bit masks and bit positions */ - #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ - #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -@@ -6093,7 +6215,6 @@ IO Module Instances. Mapped to memory. - #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ - #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - +-#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - /* TWI_SLAVE.CTRLA bit masks and bit positions */ - #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ - #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -@@ -6120,7 +6241,6 @@ IO Module Instances. Mapped to memory. - #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ - #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - - /* TWI_SLAVE.CTRLB bit masks and bit positions */ - #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ - #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -@@ -6132,7 +6252,6 @@ IO Module Instances. Mapped to memory. - #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ - #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - +-/* TWI_MASTER.CTRLC bit masks and bit positions */ +-#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - - /* TWI_SLAVE.STATUS bit masks and bit positions */ - #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ - #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -@@ -6158,7 +6277,6 @@ IO Module Instances. Mapped to memory. - #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ - #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - +-#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +-#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - - /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ - #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ - #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -@@ -6180,31 +6298,36 @@ IO Module Instances. Mapped to memory. - #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ - #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - - - /* TWI.CTRL bit masks and bit positions */ +-/* TWI_MASTER.STATUS bit masks and bit positions */ +-#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +-#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ +- +-#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +-#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ +- +-#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +-#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +- +-#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +-#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +-#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +-#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +-#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +-#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +- +- +-/* TWI_SLAVE.CTRLA bit masks and bit positions */ +-#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +-#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +-#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ +- +-#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +-#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ +- +-#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_SLAVE.CTRLB bit masks and bit positions */ +-#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +-#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_SLAVE.STATUS bit masks and bit positions */ +-#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +-#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +-#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +-#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ +- +-#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +-#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ +- +-#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +-#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ +- +- +-/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +-#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +-#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +-#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +-#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +-#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +-#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +-#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +-#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +-#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +-#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +-#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +-#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +-#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +-#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +-#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +-#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ +- +-#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +-#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ +- +- +-/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ -#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - - #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ - #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - +- +-#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +-#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ +- - -/* USB - USB Module */ -+/* USB - USB */ - /* USB_EP.STATUS bit masks and bit positions */ +-/* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALL_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALL_bp 7 /* Endpoint Stall Flag bit position. */ -+#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -+#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ -+ -+#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -+#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ - +- -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag for Isochronous Out Endpoints bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag for Isochronous Out Endpoints bit position. */ -+#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -+#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ - +- -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint Flag for Input Endpoints bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint Flag for Input Endpoints bit position. */ -+#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -+#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ - +- -#define USB_EP_OVF_bm 0x40 /* Underflow/Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Underflow/Overflow Enpoint Flag for Output Endpoints bit position. */ -+#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -+#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ - +- -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete Flag bit position. */ -+#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -+#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ - - #define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ - #define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ -@@ -6221,7 +6344,6 @@ IO Module Instances. Mapped to memory. - #define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ - #define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - - - /* USB_EP.CTRL bit masks and bit positions */ - #define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ - #define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -@@ -6239,30 +6361,21 @@ IO Module Instances. Mapped to memory. - #define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ - #define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ - +-#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ +-#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ +- +-#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ +-#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ +- +-#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ +-#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ +- +-#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ +-#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ +- +-#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ +-#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ +- +- +-/* USB_EP.CTRL bit masks and bit positions */ +-#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ +-#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ +-#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ +-#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ +-#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ +-#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ +- +-#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ +-#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ +- +-#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ +-#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ +- +-#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ +-#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ +- -/* USB_EP_STALL_bm Predefined. */ -/* USB_EP_STALL_bp Predefined. */ - @@ -69350,201 +308858,266 @@ index e8f4163..0b61d9e 100644 -/* USB_EP.CNTH bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x80 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 7 /* Zero Length Packet bit position. */ -+#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -+#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ - +- -#define USB_EP_CNT_gm 0x03 /* Endpoint Byte Counter group mask. */ -#define USB_EP_CNT_gp 0 /* Endpoint Byte Counter group position. */ -#define USB_EP_CNT0_bm (1<<0) /* Endpoint Byte Counter bit 0 mask. */ -#define USB_EP_CNT0_bp 0 /* Endpoint Byte Counter bit 0 position. */ -#define USB_EP_CNT1_bm (1<<1) /* Endpoint Byte Counter bit 1 mask. */ -#define USB_EP_CNT1_bp 1 /* Endpoint Byte Counter bit 1 position. */ -+#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -+#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -+#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -+#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -+#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -+#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -+#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -+#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - -+/* USB_EP.CNT bit masks and bit positions */ -+#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -+#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ - - /* USB.CTRLA bit masks and bit positions */ - #define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -@@ -6288,7 +6401,6 @@ IO Module Instances. Mapped to memory. - #define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ - #define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - - - /* USB.CTRLB bit masks and bit positions */ - #define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ - #define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ -@@ -6302,7 +6414,6 @@ IO Module Instances. Mapped to memory. - #define USB_ATTACH_bm 0x01 /* Attach bit mask. */ - #define USB_ATTACH_bp 0 /* Attach bit position. */ - - - /* USB.STATUS bit masks and bit positions */ - #define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ - #define USB_URESUME_bp 3 /* Upstream Resume bit position. */ -@@ -6316,7 +6427,6 @@ IO Module Instances. Mapped to memory. - #define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ - #define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - +-/* USB.CTRLA bit masks and bit positions */ +-#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ +-#define USB_ENABLE_bp 7 /* USB Enable bit position. */ - - /* USB.ADDR bit masks and bit positions */ - #define USB_ADDR_gm 0x7F /* Device Address group mask. */ - #define USB_ADDR_gp 0 /* Device Address group position. */ -@@ -6335,7 +6445,6 @@ IO Module Instances. Mapped to memory. - #define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ - #define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - +-#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ +-#define USB_SPEED_bp 6 /* Speed Select bit position. */ - - /* USB.FIFOWP bit masks and bit positions */ - #define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ - #define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -@@ -6350,7 +6459,6 @@ IO Module Instances. Mapped to memory. - #define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ - #define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - +-#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ +-#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ - - /* USB.FIFORP bit masks and bit positions */ - #define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ - #define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -@@ -6365,7 +6473,6 @@ IO Module Instances. Mapped to memory. - #define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ - #define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - +-#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ +-#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ - - /* USB.INTCTRLA bit masks and bit positions */ - #define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ - #define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ -@@ -6386,7 +6493,6 @@ IO Module Instances. Mapped to memory. - #define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ - #define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - +-#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ +-#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ +-#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ +-#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ +-#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ +-#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ +-#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ +-#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ +-#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ +-#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - - /* USB.INTCTRLB bit masks and bit positions */ - #define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ - #define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ -@@ -6394,7 +6500,6 @@ IO Module Instances. Mapped to memory. - #define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ - #define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - - - /* USB.INTFLAGSACLR bit masks and bit positions */ - #define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ - #define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ -@@ -6420,32 +6525,30 @@ IO Module Instances. Mapped to memory. - #define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ - #define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - +-/* USB.CTRLB bit masks and bit positions */ +-#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ +-#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ - - /* USB.INTFLAGSASET bit masks and bit positions */ +-#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ +-#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ +- +-#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ +-#define USB_GNACK_bp 1 /* Global NACK bit position. */ +- +-#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ +-#define USB_ATTACH_bp 0 /* Attach bit position. */ +- +- +-/* USB.STATUS bit masks and bit positions */ +-#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ +-#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ +- +-#define USB_RESUME_bm 0x04 /* Resume bit mask. */ +-#define USB_RESUME_bp 2 /* Resume bit position. */ +- +-#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ +-#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ +- +-#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ +-#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ +- +- +-/* USB.ADDR bit masks and bit positions */ +-#define USB_ADDR_gm 0x7F /* Device Address group mask. */ +-#define USB_ADDR_gp 0 /* Device Address group position. */ +-#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ +-#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ +-#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ +-#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ +-#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ +-#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ +-#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ +-#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ +-#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ +-#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ +-#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ +-#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ +-#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ +-#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ +- +- +-/* USB.FIFOWP bit masks and bit positions */ +-#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ +-#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ +-#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ +-#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ +-#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ +-#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ +-#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ +-#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ +-#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ +-#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ +-#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ +-#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ +- +- +-/* USB.FIFORP bit masks and bit positions */ +-#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ +-#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ +-#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ +-#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ +-#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ +-#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ +-#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ +-#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ +-#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ +-#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ +-#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ +-#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ +- +- +-/* USB.INTCTRLA bit masks and bit positions */ +-#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ +-#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ +- +-#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ +-#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ +- +-#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ +-#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ +- +-#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ +-#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ +- +-#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +-#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ +-#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +-#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +-#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +-#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ +- +- +-/* USB.INTCTRLB bit masks and bit positions */ +-#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ +-#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ +- +-#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ +-#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ +- +- +-/* USB.INTFLAGSACLR bit masks and bit positions */ +-#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ +-#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ +- +-#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ +-#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ +- +-#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ +-#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ +- +-#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ +-#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ +- +-#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ +-#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ +- +-#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ +-#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ +- +-#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ +-#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ +- +-#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ +-#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ +- +- +-/* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF_bm Predefined. */ -/* USB_SOFIF_bp Predefined. */ - -/* USB_SUSPENDIF_bm Predefined. */ -/* USB_SUSPENDIF_bp Predefined. */ -+/* USB_SOFIF Predefined. */ -+/* USB_SOFIF Predefined. */ - +- -/* USB_RESUMEIF_bm Predefined. */ -/* USB_RESUMEIF_bp Predefined. */ -+/* USB_SUSPENDIF Predefined. */ -+/* USB_SUSPENDIF Predefined. */ - +- -/* USB_RSTIF_bm Predefined. */ -/* USB_RSTIF_bp Predefined. */ -+/* USB_RESUMEIF Predefined. */ -+/* USB_RESUMEIF Predefined. */ - +- -/* USB_CRCIF_bm Predefined. */ -/* USB_CRCIF_bp Predefined. */ -+/* USB_RSTIF Predefined. */ -+/* USB_RSTIF Predefined. */ - +- -/* USB_UNFIF_bm Predefined. */ -/* USB_UNFIF_bp Predefined. */ -+/* USB_CRCIF Predefined. */ -+/* USB_CRCIF Predefined. */ - +- -/* USB_OVFIF_bm Predefined. */ -/* USB_OVFIF_bp Predefined. */ -+/* USB_UNFIF Predefined. */ -+/* USB_UNFIF Predefined. */ - +- -/* USB_STALLIF_bm Predefined. */ -/* USB_STALLIF_bp Predefined. */ -+/* USB_OVFIF Predefined. */ -+/* USB_OVFIF Predefined. */ - -+/* USB_STALLIF Predefined. */ -+/* USB_STALLIF Predefined. */ - - /* USB.INTFLAGSBCLR bit masks and bit positions */ - #define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -@@ -6454,14 +6557,12 @@ IO Module Instances. Mapped to memory. - #define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ - #define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - - - /* USB.INTFLAGSBSET bit masks and bit positions */ +- +-/* USB.INTFLAGSBCLR bit masks and bit positions */ +-#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ +-#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ +- +-#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ +-#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ +- +- +-/* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF_bm Predefined. */ -/* USB_TRNIF_bp Predefined. */ - -/* USB_SETUPIF_bm Predefined. */ -/* USB_SETUPIF_bp Predefined. */ -+/* USB_TRNIF Predefined. */ -+/* USB_TRNIF Predefined. */ - -+/* USB_SETUPIF Predefined. */ -+/* USB_SETUPIF Predefined. */ - - /* PORT - I/O Port Configuration */ - /* PORT.INTCTRL bit masks and bit positions */ -@@ -6479,7 +6580,6 @@ IO Module Instances. Mapped to memory. - #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ - #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - - - /* PORT.INTFLAGS bit masks and bit positions */ - #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ - #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -@@ -6487,6 +6587,24 @@ IO Module Instances. Mapped to memory. - #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ - #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -+#define PORT_SPI_bp 5 /* SPI bit position. */ -+ -+#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -+#define PORT_USART0_bp 4 /* USART0 bit position. */ -+ -+#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -+#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ -+ -+#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -+#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ -+ -+#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -+#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ -+ -+#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -+#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - - /* PORT.PIN0CTRL bit masks and bit positions */ - #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -@@ -6513,188 +6631,96 @@ IO Module Instances. Mapped to memory. - #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ - #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - - - /* PORT.PIN1CTRL bit masks and bit positions */ +-/* PORT - I/O Port Configuration */ +-/* PORT.INTCTRL bit masks and bit positions */ +-#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +-#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +-#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +-#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +-#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +-#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ +- +-#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +-#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +-#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +-#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +-#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +-#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ +- +- +-/* PORT.INTFLAGS bit masks and bit positions */ +-#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.PIN0CTRL bit masks and bit positions */ +-#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +-#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ +- +-#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +-#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ +- +-#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +-#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +-#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +-#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +-#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +-#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +-#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +-#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ +- +-#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +-#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +-#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +-#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +-#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +-#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +-#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +-#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +- +- +-/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - @@ -69568,19 +309141,9 @@ index e8f4163..0b61d9e 100644 -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ - -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ - - /* PORT.PIN2CTRL bit masks and bit positions */ +- +- +-/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - @@ -69604,19 +309167,9 @@ index e8f4163..0b61d9e 100644 -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ - -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ - - /* PORT.PIN3CTRL bit masks and bit positions */ +- +- +-/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - @@ -69640,19 +309193,9 @@ index e8f4163..0b61d9e 100644 -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ - -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ - - /* PORT.PIN4CTRL bit masks and bit positions */ +- +- +-/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - @@ -69676,19 +309219,9 @@ index e8f4163..0b61d9e 100644 -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ - -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ - - /* PORT.PIN5CTRL bit masks and bit positions */ +- +- +-/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - @@ -69712,19 +309245,9 @@ index e8f4163..0b61d9e 100644 -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ - -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ - - /* PORT.PIN6CTRL bit masks and bit positions */ +- +- +-/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - @@ -69748,19 +309271,9 @@ index e8f4163..0b61d9e 100644 -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ - -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ - - /* PORT.PIN7CTRL bit masks and bit positions */ +- +- +-/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - @@ -69784,84 +309297,151 @@ index e8f4163..0b61d9e 100644 -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ - -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ - - /* TC - 16-bit Timer/Counter With PWM */ - /* TC0.CTRLA bit masks and bit positions */ -@@ -6709,7 +6735,6 @@ IO Module Instances. Mapped to memory. - #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ - #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - - /* TC0.CTRLB bit masks and bit positions */ - #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ - #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ -@@ -6732,7 +6757,6 @@ IO Module Instances. Mapped to memory. - #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ - #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - - /* TC0.CTRLC bit masks and bit positions */ - #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ - #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ -@@ -6746,7 +6770,6 @@ IO Module Instances. Mapped to memory. - #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ - #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - +-/* TC - 16-bit Timer/Counter With PWM */ +-/* TC0.CTRLA bit masks and bit positions */ +-#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - /* TC0.CTRLD bit masks and bit positions */ - #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ - #define TC0_EVACT_gp 5 /* Event Action group position. */ -@@ -6771,11 +6794,13 @@ IO Module Instances. Mapped to memory. - #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ - #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - - /* TC0.CTRLE bit masks and bit positions */ +-/* TC0.CTRLB bit masks and bit positions */ +-#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +-#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ +- +-#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +-#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ +- +-#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC0.CTRLC bit masks and bit positions */ +-#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +-#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ +- +-#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +-#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ +- +-#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC0.CTRLD bit masks and bit positions */ +-#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC0_EVACT_gp 5 /* Event Action group position. */ +-#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ - -+#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - - /* TC0.INTCTRLA bit masks and bit positions */ - #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -@@ -6792,7 +6817,6 @@ IO Module Instances. Mapped to memory. - #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ - #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - - /* TC0.INTCTRLB bit masks and bit positions */ - #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ - #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -@@ -6822,7 +6846,6 @@ IO Module Instances. Mapped to memory. - #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ - #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - +-/* TC0.INTCTRLA bit masks and bit positions */ +-#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - - /* TC0.CTRLFCLR bit masks and bit positions */ - #define TC0_CMD_gm 0x0C /* Command group mask. */ - #define TC0_CMD_gp 2 /* Command group position. */ -@@ -6837,21 +6860,15 @@ IO Module Instances. Mapped to memory. - #define TC0_DIR_bm 0x01 /* Direction bit mask. */ - #define TC0_DIR_bp 0 /* Direction bit position. */ - +-#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - /* TC0.CTRLFSET bit masks and bit positions */ +- +-/* TC0.INTCTRLB bit masks and bit positions */ +-#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +-#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +-#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +-#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +-#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +-#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ +- +-#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +-#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +-#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +-#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +-#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +-#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ +- +-#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC0.CTRLFCLR bit masks and bit positions */ +-#define TC0_CMD_gm 0x0C /* Command group mask. */ +-#define TC0_CMD_gp 2 /* Command group position. */ +-#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC0_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC0_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC0_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD_gm Predefined. */ -/* TC0_CMD_gp Predefined. */ -/* TC0_CMD0_bm Predefined. */ @@ -69871,120 +309451,181 @@ index e8f4163..0b61d9e 100644 - -/* TC0_LUPD_bm Predefined. */ -/* TC0_LUPD_bp Predefined. */ -+/* TC0_CMD Predefined. */ -+/* TC0_CMD Predefined. */ - +- -/* TC0_DIR_bm Predefined. */ -/* TC0_DIR_bp Predefined. */ -+/* TC0_LUPD Predefined. */ -+/* TC0_LUPD Predefined. */ - -+/* TC0_DIR Predefined. */ -+/* TC0_DIR Predefined. */ - - /* TC0.CTRLGCLR bit masks and bit positions */ - #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -@@ -6869,23 +6886,21 @@ IO Module Instances. Mapped to memory. - #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ - #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - - /* TC0.CTRLGSET bit masks and bit positions */ +- +-/* TC0.CTRLGCLR bit masks and bit positions */ +-#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +-#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ +- +-#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +-#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ +- +-#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV_bm Predefined. */ -/* TC0_CCDBV_bp Predefined. */ - -/* TC0_CCCBV_bm Predefined. */ -/* TC0_CCCBV_bp Predefined. */ -+/* TC0_CCDBV Predefined. */ -+/* TC0_CCDBV Predefined. */ - +- -/* TC0_CCBBV_bm Predefined. */ -/* TC0_CCBBV_bp Predefined. */ -+/* TC0_CCCBV Predefined. */ -+/* TC0_CCCBV Predefined. */ - +- -/* TC0_CCABV_bm Predefined. */ -/* TC0_CCABV_bp Predefined. */ -+/* TC0_CCBBV Predefined. */ -+/* TC0_CCBBV Predefined. */ - +- -/* TC0_PERBV_bm Predefined. */ -/* TC0_PERBV_bp Predefined. */ -+/* TC0_CCABV Predefined. */ -+/* TC0_CCABV Predefined. */ - -+/* TC0_PERBV Predefined. */ -+/* TC0_PERBV Predefined. */ - - /* TC0.INTFLAGS bit masks and bit positions */ - #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -@@ -6906,7 +6921,6 @@ IO Module Instances. Mapped to memory. - #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ - #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - - /* TC1.CTRLA bit masks and bit positions */ - #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ - #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -@@ -6919,7 +6933,6 @@ IO Module Instances. Mapped to memory. - #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ - #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - - /* TC1.CTRLB bit masks and bit positions */ - #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ - #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -@@ -6936,7 +6949,6 @@ IO Module Instances. Mapped to memory. - #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ - #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - +-/* TC0.INTFLAGS bit masks and bit positions */ +-#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +-#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - - /* TC1.CTRLC bit masks and bit positions */ - #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ - #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ -@@ -6944,7 +6956,6 @@ IO Module Instances. Mapped to memory. - #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ - #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - +-#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +-#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - - /* TC1.CTRLD bit masks and bit positions */ - #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ - #define TC1_EVACT_gp 5 /* Event Action group position. */ -@@ -6969,12 +6980,10 @@ IO Module Instances. Mapped to memory. - #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ - #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - +-#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - - /* TC1.CTRLE bit masks and bit positions */ - #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ - #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - +-#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - - /* TC1.INTCTRLA bit masks and bit positions */ - #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ - #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -@@ -6990,7 +6999,6 @@ IO Module Instances. Mapped to memory. - #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ - #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - +-#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - - /* TC1.INTCTRLB bit masks and bit positions */ - #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ - #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -@@ -7006,7 +7014,6 @@ IO Module Instances. Mapped to memory. - #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ - #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - +-#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - /* TC1.CTRLFCLR bit masks and bit positions */ - #define TC1_CMD_gm 0x0C /* Command group mask. */ - #define TC1_CMD_gp 2 /* Command group position. */ -@@ -7021,21 +7028,15 @@ IO Module Instances. Mapped to memory. - #define TC1_DIR_bm 0x01 /* Direction bit mask. */ - #define TC1_DIR_bp 0 /* Direction bit position. */ - - - /* TC1.CTRLFSET bit masks and bit positions */ +-/* TC1.CTRLA bit masks and bit positions */ +-#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC1.CTRLB bit masks and bit positions */ +-#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC1.CTRLC bit masks and bit positions */ +-#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC1.CTRLD bit masks and bit positions */ +-#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC1_EVACT_gp 5 /* Event Action group position. */ +-#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC1.CTRLE bit masks and bit positions */ +-#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC1.INTCTRLA bit masks and bit positions */ +-#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC1.INTCTRLB bit masks and bit positions */ +-#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC1.CTRLFCLR bit masks and bit positions */ +-#define TC1_CMD_gm 0x0C /* Command group mask. */ +-#define TC1_CMD_gp 2 /* Command group position. */ +-#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC1_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC1_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC1_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD_gm Predefined. */ -/* TC1_CMD_gp Predefined. */ -/* TC1_CMD0_bm Predefined. */ @@ -69994,282 +309635,229 @@ index e8f4163..0b61d9e 100644 - -/* TC1_LUPD_bm Predefined. */ -/* TC1_LUPD_bp Predefined. */ -+/* TC1_CMD Predefined. */ -+/* TC1_CMD Predefined. */ - +- -/* TC1_DIR_bm Predefined. */ -/* TC1_DIR_bp Predefined. */ -+/* TC1_LUPD Predefined. */ -+/* TC1_LUPD Predefined. */ - -+/* TC1_DIR Predefined. */ -+/* TC1_DIR Predefined. */ - - /* TC1.CTRLGCLR bit masks and bit positions */ - #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -@@ -7047,17 +7048,15 @@ IO Module Instances. Mapped to memory. - #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ - #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - - /* TC1.CTRLGSET bit masks and bit positions */ +- +-/* TC1.CTRLGCLR bit masks and bit positions */ +-#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV_bm Predefined. */ -/* TC1_CCBBV_bp Predefined. */ - -/* TC1_CCABV_bm Predefined. */ -/* TC1_CCABV_bp Predefined. */ -+/* TC1_CCBBV Predefined. */ -+/* TC1_CCBBV Predefined. */ - +- -/* TC1_PERBV_bm Predefined. */ -/* TC1_PERBV_bp Predefined. */ -+/* TC1_CCABV Predefined. */ -+/* TC1_CCABV Predefined. */ - -+/* TC1_PERBV Predefined. */ -+/* TC1_PERBV Predefined. */ - - /* TC1.INTFLAGS bit masks and bit positions */ - #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -@@ -7072,6 +7071,154 @@ IO Module Instances. Mapped to memory. - #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ - #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -+/* TC2 - 16-bit Timer/Counter type 2 */ -+/* TC2.CTRLA bit masks and bit positions */ -+#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC2.CTRLB bit masks and bit positions */ -+#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -+#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ -+ -+#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -+#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ -+ -+#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -+#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ -+ -+#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -+#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ -+ -+#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -+#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ -+ -+#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -+#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ -+ -+#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -+#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ -+ -+#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -+#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ -+ -+/* TC2.CTRLC bit masks and bit positions */ -+#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -+#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ -+ -+#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -+#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ -+ -+#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -+#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ -+ -+#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -+#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ -+ -+#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -+#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ -+ -+#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -+#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ -+ -+#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -+#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ -+ -+#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -+#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ -+ -+/* TC2.CTRLE bit masks and bit positions */ -+#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC2.INTCTRLA bit masks and bit positions */ -+#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -+#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -+#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -+#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -+#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -+#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ -+ -+#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -+#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -+#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -+#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -+#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -+#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ -+ -+/* TC2.INTCTRLB bit masks and bit positions */ -+#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -+#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -+#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -+#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -+#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -+#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -+#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -+#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -+#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -+#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -+#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -+#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -+#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -+#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -+#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -+#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -+#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -+#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -+#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -+#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -+#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ -+ -+/* TC2.CTRLF bit masks and bit positions */ -+#define TC2_CMD_gm 0x0C /* Command group mask. */ -+#define TC2_CMD_gp 2 /* Command group position. */ -+#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC2_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -+#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -+#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -+#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -+#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -+#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ -+ -+/* TC2.INTFLAGS bit masks and bit positions */ -+#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -+#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ -+ -+#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -+#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ -+ -+#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -+#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ -+ -+#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -+#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ -+ -+#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ -+ -+#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ - - /* AWEX - Timer/Counter Advanced Waveform Extension */ - /* AWEX.CTRL bit masks and bit positions */ -@@ -7093,7 +7240,6 @@ IO Module Instances. Mapped to memory. - #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ - #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - - - /* AWEX.FDCTRL bit masks and bit positions */ - #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ - #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ -@@ -7108,7 +7254,6 @@ IO Module Instances. Mapped to memory. - #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ - #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - - - /* AWEX.STATUS bit masks and bit positions */ - #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ - #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ -@@ -7119,6 +7264,15 @@ IO Module Instances. Mapped to memory. - #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ - #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -+/* AWEX.STATUSSET bit masks and bit positions */ -+/* AWEX_FDF Predefined. */ -+/* AWEX_FDF Predefined. */ -+ -+/* AWEX_DTHSBUFV Predefined. */ -+/* AWEX_DTHSBUFV Predefined. */ -+ -+/* AWEX_DTLSBUFV Predefined. */ -+/* AWEX_DTLSBUFV Predefined. */ - - /* HIRES - Timer/Counter High-Resolution Extension */ - /* HIRES.CTRLA bit masks and bit positions */ -@@ -7129,7 +7283,6 @@ IO Module Instances. Mapped to memory. - #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ - #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - +-/* TC1.INTFLAGS bit masks and bit positions */ +-#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - - /* USART - Universal Asynchronous Receiver-Transmitter */ - /* USART.STATUS bit masks and bit positions */ - #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -@@ -7153,7 +7306,6 @@ IO Module Instances. Mapped to memory. - #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ - #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - +-#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - - /* USART.CTRLA bit masks and bit positions */ - #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ - #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -@@ -7176,7 +7328,6 @@ IO Module Instances. Mapped to memory. - #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ - #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - +-#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - - /* USART.CTRLB bit masks and bit positions */ - #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ - #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -@@ -7193,7 +7344,6 @@ IO Module Instances. Mapped to memory. - #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ - #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - +-#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - /* USART.CTRLC bit masks and bit positions */ - #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ - #define USART_CMODE_gp 6 /* Communication Mode group position. */ -@@ -7221,7 +7371,6 @@ IO Module Instances. Mapped to memory. - #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ - #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - - - /* USART.BAUDCTRLA bit masks and bit positions */ - #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ - #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -@@ -7242,7 +7391,6 @@ IO Module Instances. Mapped to memory. - #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ - #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - +-/* AWEX - Timer/Counter Advanced Waveform Extension */ +-/* AWEX.CTRL bit masks and bit positions */ +-#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +-#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ +- +-#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +-#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ +- +-#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +-#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ +- +-#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +-#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ +- +-#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +-#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ +- +-#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +-#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ +- +- +-/* AWEX.FDCTRL bit masks and bit positions */ +-#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +-#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ +- +-#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +-#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ +- +-#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +-#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +-#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +-#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +-#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +-#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ +- +- +-/* AWEX.STATUS bit masks and bit positions */ +-#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +-#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ +- +-#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +-#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ +- +-#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +-#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ +- +- +-/* HIRES - Timer/Counter High-Resolution Extension */ +-/* HIRES.CTRLA bit masks and bit positions */ +-#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +-#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +-#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +-#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +-#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +-#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ +- +- +-/* USART - Universal Asynchronous Receiver-Transmitter */ +-/* USART.STATUS bit masks and bit positions */ +-#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +-#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ +- +-#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +-#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +- +-#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +-#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +- +-#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +-#define USART_FERR_bp 4 /* Frame Error bit position. */ +- +-#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +-#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ +- +-#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +-#define USART_PERR_bp 2 /* Parity Error bit position. */ +- +-#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +-#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ +- +- +-/* USART.CTRLA bit masks and bit positions */ +-#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +-#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +-#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +-#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +-#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +-#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ +- +-#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +-#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +-#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +-#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +-#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +-#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ +- +-#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +-#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +-#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +-#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +-#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +-#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ +- +- +-/* USART.CTRLB bit masks and bit positions */ +-#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +-#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ +- +-#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +-#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ +- +-#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +-#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ +- +-#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +-#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ +- +-#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +-#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ +- +- +-/* USART.CTRLC bit masks and bit positions */ +-#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +-#define USART_CMODE_gp 6 /* Communication Mode group position. */ +-#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +-#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +-#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +-#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ +- +-#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +-#define USART_PMODE_gp 4 /* Parity Mode group position. */ +-#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +-#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +-#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +-#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +- +-#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +-#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +- +-#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +-#define USART_CHSIZE_gp 0 /* Character Size group position. */ +-#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +-#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +-#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +-#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +-#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +-#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +- +- +-/* USART.BAUDCTRLA bit masks and bit positions */ +-#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +-#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +-#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +-#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +-#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +-#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +-#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +-#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +-#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +-#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +-#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +-#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +-#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +-#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +-#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +-#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +-#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +-#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ +- +- +-/* USART.BAUDCTRLB bit masks and bit positions */ +-#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +-#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +-#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +-#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +-#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +-#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +-#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +-#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +-#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +-#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - - /* USART.BAUDCTRLB bit masks and bit positions */ - #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ - #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -@@ -7255,17 +7403,8 @@ IO Module Instances. Mapped to memory. - #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ - #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL_gm Predefined. */ -/* USART_BSEL_gp Predefined. */ -/* USART_BSEL0_bm Predefined. */ @@ -70281,473 +309869,487 @@ index e8f4163..0b61d9e 100644 -/* USART_BSEL3_bm Predefined. */ -/* USART_BSEL3_bp Predefined. */ - -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ - - /* SPI - Serial Peripheral Interface */ - /* SPI.CTRL bit masks and bit positions */ -@@ -7295,7 +7434,6 @@ IO Module Instances. Mapped to memory. - #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ - #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - - - /* SPI.INTCTRL bit masks and bit positions */ - #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ - #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -@@ -7304,7 +7442,6 @@ IO Module Instances. Mapped to memory. - #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ - #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - +-/* SPI - Serial Peripheral Interface */ +-/* SPI.CTRL bit masks and bit positions */ +-#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +-#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - - /* SPI.STATUS bit masks and bit positions */ - #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ - #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ -@@ -7312,7 +7449,6 @@ IO Module Instances. Mapped to memory. - #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ - #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - +-#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +-#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ +- +-#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +-#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ +- +-#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +-#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ +- +-#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +-#define SPI_MODE_gp 2 /* SPI Mode group position. */ +-#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +-#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +-#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +-#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ +- +-#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +-#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +-#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +-#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +-#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +-#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ +- +- +-/* SPI.INTCTRL bit masks and bit positions */ +-#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +-#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +-/* SPI.STATUS bit masks and bit positions */ +-#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +-#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ +- +-#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +-#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +- +- +-/* IRCOM - IR Communication Module */ +-/* IRCOM.CTRL bit masks and bit positions */ +-#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +-#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +-#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +-#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +-#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +-#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +-#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +-#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +-#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +-#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - - /* IRCOM - IR Communication Module */ - /* IRCOM.CTRL bit masks and bit positions */ - #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -@@ -7326,34 +7462,152 @@ IO Module Instances. Mapped to memory. - #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ - #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - - -/* PRESC - Prescaler */ -/* PRESC.PRESCALER bit masks and bit positions */ -#define PRESC_RESET_bm 0x01 /* Reset bit mask. */ -#define PRESC_RESET_bp 0 /* Reset bit position. */ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -+#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -+#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -+#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -+#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -+#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -+#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -+#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -+#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -+#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -+#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -+#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -+#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -+#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -+#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -+#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -+#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -+#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -+#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ -+ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -+#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -+#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* LOCKBIT - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - - // Generic Port Pins - --#define PIN0_bm 0x01 -+#define PIN0_bm 0x01 - #define PIN0_bp 0 - #define PIN1_bm 0x02 - #define PIN1_bp 1 --#define PIN2_bm 0x04 -+#define PIN2_bm 0x04 - #define PIN2_bp 2 --#define PIN3_bm 0x08 -+#define PIN3_bm 0x08 - #define PIN3_bp 3 --#define PIN4_bm 0x10 -+#define PIN4_bm 0x10 - #define PIN4_bp 4 --#define PIN5_bm 0x20 -+#define PIN5_bm 0x20 - #define PIN5_bp 5 --#define PIN6_bm 0x40 -+#define PIN6_bm 0x40 - #define PIN6_bp 6 --#define PIN7_bm 0x80 -+#define PIN7_bm 0x80 - #define PIN7_bp 7 - - - /* ========== Interrupt Vector Definitions ========== */ - /* Vector 0 is the reset vector */ - -@@ -7398,17 +7652,51 @@ IO Module Instances. Mapped to memory. - /* TCC0 interrupt vectors */ - #define TCC0_OVF_vect_num 14 - #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LUNF_vect_num 14 -+#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ - #define TCC0_ERR_vect_num 15 - #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_HUNF_vect_num 15 -+#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ - #define TCC0_CCA_vect_num 16 - #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPA_vect_num 16 -+#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ -+ -+/* TCC0 interrupt vectors */ - #define TCC0_CCB_vect_num 17 - #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPB_vect_num 17 -+#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ -+ -+/* TCC0 interrupt vectors */ - #define TCC0_CCC_vect_num 18 - #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPC_vect_num 18 -+#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ -+ -+/* TCC0 interrupt vectors */ - #define TCC0_CCD_vect_num 19 - #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPD_vect_num 19 -+#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ -+ - /* TCC1 interrupt vectors */ - #define TCC1_OVF_vect_num 20 - #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -@@ -7444,10 +7732,10 @@ IO Module Instances. Mapped to memory. - #define AES_INT_vect _VECTOR(31) /* AES Interrupt */ - - /* NVM interrupt vectors */ +- +- +-// Generic Port Pins +- +-#define PIN0_bm 0x01 +-#define PIN0_bp 0 +-#define PIN1_bm 0x02 +-#define PIN1_bp 1 +-#define PIN2_bm 0x04 +-#define PIN2_bp 2 +-#define PIN3_bm 0x08 +-#define PIN3_bp 3 +-#define PIN4_bm 0x10 +-#define PIN4_bp 4 +-#define PIN5_bm 0x20 +-#define PIN5_bp 5 +-#define PIN6_bm 0x40 +-#define PIN6_bp 6 +-#define PIN7_bm 0x80 +-#define PIN7_bp 7 +- +- +-/* ========== Interrupt Vector Definitions ========== */ +-/* Vector 0 is the reset vector */ +- +-/* OSC interrupt vectors */ +-#define OSC_OSCF_vect_num 1 +-#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ +- +-/* PORTC interrupt vectors */ +-#define PORTC_INT0_vect_num 2 +-#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +-#define PORTC_INT1_vect_num 3 +-#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ +- +-/* PORTR interrupt vectors */ +-#define PORTR_INT0_vect_num 4 +-#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +-#define PORTR_INT1_vect_num 5 +-#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ +- +-/* DMA interrupt vectors */ +-#define DMA_CH0_vect_num 6 +-#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +-#define DMA_CH1_vect_num 7 +-#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +-#define DMA_CH2_vect_num 8 +-#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +-#define DMA_CH3_vect_num 9 +-#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ +- +-/* RTC interrupt vectors */ +-#define RTC_OVF_vect_num 10 +-#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +-#define RTC_COMP_vect_num 11 +-#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ +- +-/* TWIC interrupt vectors */ +-#define TWIC_TWIS_vect_num 12 +-#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +-#define TWIC_TWIM_vect_num 13 +-#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ +- +-/* TCC0 interrupt vectors */ +-#define TCC0_OVF_vect_num 14 +-#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +-#define TCC0_ERR_vect_num 15 +-#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +-#define TCC0_CCA_vect_num 16 +-#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +-#define TCC0_CCB_vect_num 17 +-#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +-#define TCC0_CCC_vect_num 18 +-#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +-#define TCC0_CCD_vect_num 19 +-#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ +- +-/* TCC1 interrupt vectors */ +-#define TCC1_OVF_vect_num 20 +-#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +-#define TCC1_ERR_vect_num 21 +-#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +-#define TCC1_CCA_vect_num 22 +-#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +-#define TCC1_CCB_vect_num 23 +-#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ +- +-/* SPIC interrupt vectors */ +-#define SPIC_INT_vect_num 24 +-#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ +- +-/* USARTC0 interrupt vectors */ +-#define USARTC0_RXC_vect_num 25 +-#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +-#define USARTC0_DRE_vect_num 26 +-#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +-#define USARTC0_TXC_vect_num 27 +-#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ +- +-/* USARTC1 interrupt vectors */ +-#define USARTC1_RXC_vect_num 28 +-#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +-#define USARTC1_DRE_vect_num 29 +-#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +-#define USARTC1_TXC_vect_num 30 +-#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ +- +-/* AES interrupt vectors */ +-#define AES_INT_vect_num 31 +-#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ +- +-/* NVM interrupt vectors */ -#define NVM_SPM_vect_num 32 -#define NVM_SPM_vect _VECTOR(32) /* SPM Interrupt */ -#define NVM_EE_vect_num 33 -#define NVM_EE_vect _VECTOR(33) /* EE Interrupt */ -+#define NVM_EE_vect_num 32 -+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -+#define NVM_SPM_vect_num 33 -+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - - /* PORTB interrupt vectors */ - #define PORTB_INT0_vect_num 34 -@@ -7488,17 +7776,51 @@ IO Module Instances. Mapped to memory. - /* TCE0 interrupt vectors */ - #define TCE0_OVF_vect_num 47 - #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LUNF_vect_num 47 -+#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ - #define TCE0_ERR_vect_num 48 - #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_HUNF_vect_num 48 -+#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ - #define TCE0_CCA_vect_num 49 - #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPA_vect_num 49 -+#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ -+ -+/* TCE0 interrupt vectors */ - #define TCE0_CCB_vect_num 50 - #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPB_vect_num 50 -+#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ -+ -+/* TCE0 interrupt vectors */ - #define TCE0_CCC_vect_num 51 - #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPC_vect_num 51 -+#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ -+ -+/* TCE0 interrupt vectors */ - #define TCE0_CCD_vect_num 52 - #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPD_vect_num 52 -+#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ -+ - /* TCE1 interrupt vectors */ - #define TCE1_OVF_vect_num 53 - #define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ -@@ -7568,17 +7890,51 @@ IO Module Instances. Mapped to memory. - /* TCD0 interrupt vectors */ - #define TCD0_OVF_vect_num 77 - #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LUNF_vect_num 77 -+#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ - #define TCD0_ERR_vect_num 78 - #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_HUNF_vect_num 78 -+#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ - #define TCD0_CCA_vect_num 79 - #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPA_vect_num 79 -+#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ -+ -+/* TCD0 interrupt vectors */ - #define TCD0_CCB_vect_num 80 - #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPB_vect_num 80 -+#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ -+ -+/* TCD0 interrupt vectors */ - #define TCD0_CCC_vect_num 81 - #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPC_vect_num 81 -+#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ -+ -+/* TCD0 interrupt vectors */ - #define TCD0_CCD_vect_num 82 - #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPD_vect_num 82 -+#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ -+ - /* TCD1 interrupt vectors */ - #define TCD1_OVF_vect_num 83 - #define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -@@ -7648,17 +8004,51 @@ IO Module Instances. Mapped to memory. - /* TCF0 interrupt vectors */ - #define TCF0_OVF_vect_num 108 - #define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LUNF_vect_num 108 -+#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ - #define TCF0_ERR_vect_num 109 - #define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_HUNF_vect_num 109 -+#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ - #define TCF0_CCA_vect_num 110 - #define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPA_vect_num 110 -+#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ -+ -+/* TCF0 interrupt vectors */ - #define TCF0_CCB_vect_num 111 - #define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPB_vect_num 111 -+#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ -+ -+/* TCF0 interrupt vectors */ - #define TCF0_CCC_vect_num 112 - #define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPC_vect_num 112 -+#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ -+ -+/* TCF0 interrupt vectors */ - #define TCF0_CCD_vect_num 113 - #define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPD_vect_num 113 -+#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ -+ - /* TCF1 interrupt vectors */ - #define TCF1_OVF_vect_num 114 - #define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */ -@@ -7691,23 +8081,21 @@ IO Module Instances. Mapped to memory. - - /* USB interrupt vectors */ - #define USB_BUSEVENT_vect_num 125 +- +-/* PORTB interrupt vectors */ +-#define PORTB_INT0_vect_num 34 +-#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +-#define PORTB_INT1_vect_num 35 +-#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ +- +-/* ACB interrupt vectors */ +-#define ACB_AC0_vect_num 36 +-#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ +-#define ACB_AC1_vect_num 37 +-#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ +-#define ACB_ACW_vect_num 38 +-#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ +- +-/* ADCB interrupt vectors */ +-#define ADCB_CH0_vect_num 39 +-#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ +-#define ADCB_CH1_vect_num 40 +-#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ +-#define ADCB_CH2_vect_num 41 +-#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ +-#define ADCB_CH3_vect_num 42 +-#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ +- +-/* PORTE interrupt vectors */ +-#define PORTE_INT0_vect_num 43 +-#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +-#define PORTE_INT1_vect_num 44 +-#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ +- +-/* TWIE interrupt vectors */ +-#define TWIE_TWIS_vect_num 45 +-#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +-#define TWIE_TWIM_vect_num 46 +-#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ +- +-/* TCE0 interrupt vectors */ +-#define TCE0_OVF_vect_num 47 +-#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +-#define TCE0_ERR_vect_num 48 +-#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +-#define TCE0_CCA_vect_num 49 +-#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +-#define TCE0_CCB_vect_num 50 +-#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +-#define TCE0_CCC_vect_num 51 +-#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +-#define TCE0_CCD_vect_num 52 +-#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ +- +-/* TCE1 interrupt vectors */ +-#define TCE1_OVF_vect_num 53 +-#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ +-#define TCE1_ERR_vect_num 54 +-#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ +-#define TCE1_CCA_vect_num 55 +-#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ +-#define TCE1_CCB_vect_num 56 +-#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ +- +-/* SPIE interrupt vectors */ +-#define SPIE_INT_vect_num 57 +-#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ +- +-/* USARTE0 interrupt vectors */ +-#define USARTE0_RXC_vect_num 58 +-#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +-#define USARTE0_DRE_vect_num 59 +-#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +-#define USARTE0_TXC_vect_num 60 +-#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ +- +-/* USARTE1 interrupt vectors */ +-#define USARTE1_RXC_vect_num 61 +-#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ +-#define USARTE1_DRE_vect_num 62 +-#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ +-#define USARTE1_TXC_vect_num 63 +-#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ +- +-/* PORTD interrupt vectors */ +-#define PORTD_INT0_vect_num 64 +-#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +-#define PORTD_INT1_vect_num 65 +-#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ +- +-/* PORTA interrupt vectors */ +-#define PORTA_INT0_vect_num 66 +-#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +-#define PORTA_INT1_vect_num 67 +-#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ +- +-/* ACA interrupt vectors */ +-#define ACA_AC0_vect_num 68 +-#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +-#define ACA_AC1_vect_num 69 +-#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +-#define ACA_ACW_vect_num 70 +-#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ +- +-/* ADCA interrupt vectors */ +-#define ADCA_CH0_vect_num 71 +-#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +-#define ADCA_CH1_vect_num 72 +-#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +-#define ADCA_CH2_vect_num 73 +-#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +-#define ADCA_CH3_vect_num 74 +-#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ +- +-/* TWID interrupt vectors */ +-#define TWID_TWIS_vect_num 75 +-#define TWID_TWIS_vect _VECTOR(75) /* TWI Slave Interrupt */ +-#define TWID_TWIM_vect_num 76 +-#define TWID_TWIM_vect _VECTOR(76) /* TWI Master Interrupt */ +- +-/* TCD0 interrupt vectors */ +-#define TCD0_OVF_vect_num 77 +-#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +-#define TCD0_ERR_vect_num 78 +-#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +-#define TCD0_CCA_vect_num 79 +-#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +-#define TCD0_CCB_vect_num 80 +-#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +-#define TCD0_CCC_vect_num 81 +-#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +-#define TCD0_CCD_vect_num 82 +-#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ +- +-/* TCD1 interrupt vectors */ +-#define TCD1_OVF_vect_num 83 +-#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +-#define TCD1_ERR_vect_num 84 +-#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +-#define TCD1_CCA_vect_num 85 +-#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +-#define TCD1_CCB_vect_num 86 +-#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ +- +-/* SPID interrupt vectors */ +-#define SPID_INT_vect_num 87 +-#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ +- +-/* USARTD0 interrupt vectors */ +-#define USARTD0_RXC_vect_num 88 +-#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +-#define USARTD0_DRE_vect_num 89 +-#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +-#define USARTD0_TXC_vect_num 90 +-#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ +- +-/* USARTD1 interrupt vectors */ +-#define USARTD1_RXC_vect_num 91 +-#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +-#define USARTD1_DRE_vect_num 92 +-#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +-#define USARTD1_TXC_vect_num 93 +-#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ +- +-/* PORTQ interrupt vectors */ +-#define PORTQ_INT0_vect_num 94 +-#define PORTQ_INT0_vect _VECTOR(94) /* External Interrupt 0 */ +-#define PORTQ_INT1_vect_num 95 +-#define PORTQ_INT1_vect _VECTOR(95) /* External Interrupt 1 */ +- +-/* PORTH interrupt vectors */ +-#define PORTH_INT0_vect_num 96 +-#define PORTH_INT0_vect _VECTOR(96) /* External Interrupt 0 */ +-#define PORTH_INT1_vect_num 97 +-#define PORTH_INT1_vect _VECTOR(97) /* External Interrupt 1 */ +- +-/* PORTJ interrupt vectors */ +-#define PORTJ_INT0_vect_num 98 +-#define PORTJ_INT0_vect _VECTOR(98) /* External Interrupt 0 */ +-#define PORTJ_INT1_vect_num 99 +-#define PORTJ_INT1_vect _VECTOR(99) /* External Interrupt 1 */ +- +-/* PORTK interrupt vectors */ +-#define PORTK_INT0_vect_num 100 +-#define PORTK_INT0_vect _VECTOR(100) /* External Interrupt 0 */ +-#define PORTK_INT1_vect_num 101 +-#define PORTK_INT1_vect _VECTOR(101) /* External Interrupt 1 */ +- +-/* PORTF interrupt vectors */ +-#define PORTF_INT0_vect_num 104 +-#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +-#define PORTF_INT1_vect_num 105 +-#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ +- +-/* TWIF interrupt vectors */ +-#define TWIF_TWIS_vect_num 106 +-#define TWIF_TWIS_vect _VECTOR(106) /* TWI Slave Interrupt */ +-#define TWIF_TWIM_vect_num 107 +-#define TWIF_TWIM_vect _VECTOR(107) /* TWI Master Interrupt */ +- +-/* TCF0 interrupt vectors */ +-#define TCF0_OVF_vect_num 108 +-#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ +-#define TCF0_ERR_vect_num 109 +-#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ +-#define TCF0_CCA_vect_num 110 +-#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ +-#define TCF0_CCB_vect_num 111 +-#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ +-#define TCF0_CCC_vect_num 112 +-#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ +-#define TCF0_CCD_vect_num 113 +-#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ +- +-/* TCF1 interrupt vectors */ +-#define TCF1_OVF_vect_num 114 +-#define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */ +-#define TCF1_ERR_vect_num 115 +-#define TCF1_ERR_vect _VECTOR(115) /* Error Interrupt */ +-#define TCF1_CCA_vect_num 116 +-#define TCF1_CCA_vect _VECTOR(116) /* Compare or Capture A Interrupt */ +-#define TCF1_CCB_vect_num 117 +-#define TCF1_CCB_vect _VECTOR(117) /* Compare or Capture B Interrupt */ +- +-/* SPIF interrupt vectors */ +-#define SPIF_INT_vect_num 118 +-#define SPIF_INT_vect _VECTOR(118) /* SPI Interrupt */ +- +-/* USARTF0 interrupt vectors */ +-#define USARTF0_RXC_vect_num 119 +-#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ +-#define USARTF0_DRE_vect_num 120 +-#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ +-#define USARTF0_TXC_vect_num 121 +-#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ +- +-/* USARTF1 interrupt vectors */ +-#define USARTF1_RXC_vect_num 122 +-#define USARTF1_RXC_vect _VECTOR(122) /* Reception Complete Interrupt */ +-#define USARTF1_DRE_vect_num 123 +-#define USARTF1_DRE_vect _VECTOR(123) /* Data Register Empty Interrupt */ +-#define USARTF1_TXC_vect_num 124 +-#define USARTF1_TXC_vect _VECTOR(124) /* Transmission Complete Interrupt */ +- +-/* USB interrupt vectors */ +-#define USB_BUSEVENT_vect_num 125 -#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts and crc, underflow, overflow and stall error interrupts */ -#define USB_TRNCOMPL_vect_num 127 -#define USB_TRNCOMPL_vect _VECTOR(127) /* Transaction complete interrupt */ - -+#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -+#define USB_TRNCOMPL_vect_num 126 -+#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ - - #define _VECTOR_SIZE 4 /* Size of individual vector. */ +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (128 * _VECTOR_SIZE) -+#define _VECTORS_SIZE (127 * _VECTOR_SIZE) - - - /* ========== Constants ========== */ - +- +- +-/* ========== Constants ========== */ +- -#define PROGMEM_START (0x00000) -+#define PROGMEM_START (0x0000) - #define PROGMEM_SIZE (139264) +-#define PROGMEM_SIZE (139264) -#define PROGMEM_PAGE_SIZE (512) - #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - +-#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) +- -#define APP_SECTION_START (0x00000) -+#define APP_SECTION_START (0x0000) - #define APP_SECTION_SIZE (131072) - #define APP_SECTION_PAGE_SIZE (512) - #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -@@ -7722,14 +8110,8 @@ IO Module Instances. Mapped to memory. - #define BOOT_SECTION_PAGE_SIZE (512) - #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - +-#define APP_SECTION_SIZE (131072) +-#define APP_SECTION_PAGE_SIZE (512) +-#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) +- +-#define APPTABLE_SECTION_START (0x1E000) +-#define APPTABLE_SECTION_SIZE (8192) +-#define APPTABLE_SECTION_PAGE_SIZE (512) +-#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) +- +-#define BOOT_SECTION_START (0x20000) +-#define BOOT_SECTION_SIZE (8192) +-#define BOOT_SECTION_PAGE_SIZE (512) +-#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) +- -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - - #define DATAMEM_START (0x0000) - #define DATAMEM_SIZE (16777216) +-#define DATAMEM_START (0x0000) +-#define DATAMEM_SIZE (16777216) -#define DATAMEM_PAGE_SIZE (0) - #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - - #define IO_START (0x0000) -@@ -7747,51 +8129,96 @@ IO Module Instances. Mapped to memory. - #define INTERNAL_SRAM_PAGE_SIZE (0) - #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - +-#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) +- +-#define IO_START (0x0000) +-#define IO_SIZE (4096) +-#define IO_PAGE_SIZE (0) +-#define IO_END (IO_START + IO_SIZE - 1) +- +-#define MAPPED_EEPROM_START (0x1000) +-#define MAPPED_EEPROM_SIZE (2048) +-#define MAPPED_EEPROM_PAGE_SIZE (0) +-#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) +- +-#define INTERNAL_SRAM_START (0x2000) +-#define INTERNAL_SRAM_SIZE (8192) +-#define INTERNAL_SRAM_PAGE_SIZE (0) +-#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) +- -#define EXTERNAL_SRAM_START (0x4000) -#define EXTERNAL_SRAM_SIZE (16760832) -#define EXTERNAL_SRAM_PAGE_SIZE (0) @@ -70762,75513 +310364,11757 @@ index e8f4163..0b61d9e 100644 -#define LOCKBIT_SIZE (1) -#define LOCKBIT_PAGE_SIZE (0) -#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (2048) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - - #define SIGNATURES_START (0x0000) - #define SIGNATURES_SIZE (3) - #define SIGNATURES_PAGE_SIZE (0) - #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (6) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ - #define USER_SIGNATURES_START (0x0000) - #define USER_SIGNATURES_SIZE (512) +- +-#define SIGNATURES_START (0x0000) +-#define SIGNATURES_SIZE (3) +-#define SIGNATURES_PAGE_SIZE (0) +-#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) +- +-#define USER_SIGNATURES_START (0x0000) +-#define USER_SIGNATURES_SIZE (512) -#define USER_SIGNATURES_PAGE_SIZE (0) -+#define USER_SIGNATURES_PAGE_SIZE (512) - #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - - #define PROD_SIGNATURES_START (0x0000) +-#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) +- +-#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (0) -+#define PROD_SIGNATURES_SIZE (64) -+#define PROD_SIGNATURES_PAGE_SIZE (512) - #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -+#define FLASHSTART PROGMEM_START - #define FLASHEND PROGMEM_END +-#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) +- +-#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE PROGMEM_PAGE_SIZE -+#define SPM_PAGESIZE 512 - #define RAMSTART INTERNAL_SRAM_START - #define RAMSIZE INTERNAL_SRAM_SIZE - #define RAMEND INTERNAL_SRAM_END +-#define RAMSTART INTERNAL_SRAM_START +-#define RAMSIZE INTERNAL_SRAM_SIZE +-#define RAMEND INTERNAL_SRAM_END -#define XRAMSTART EXTERNAL_SRAM_START -#define XRAMSIZE EXTERNAL_SRAM_SIZE -#define XRAMEND EXTERNAL_SRAM_END - #define E2END EEPROM_END - #define E2PAGESIZE EEPROM_PAGE_SIZE - - - /* ========== Fuses ========== */ +-#define E2END EEPROM_END +-#define E2PAGESIZE EEPROM_PAGE_SIZE +- +- +-/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 0 - -+#define FUSE_MEMORY_SIZE 6 -+ -+/* Fuse Byte 0 */ -+#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -+#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -+#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -+#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -+#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -+#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -+#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -+#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -+#define FUSE0_DEFAULT (0xFF) -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) - - /* ========== Lock Bits ========== */ - #define __LOCK_BITS_EXIST -@@ -7799,12 +8226,11 @@ IO Module Instances. Mapped to memory. - #define __BOOT_LOCK_APPLICATION_BITS_EXIST - #define __BOOT_LOCK_BOOT_BITS_EXIST - - - /* ========== Signature ========== */ - #define SIGNATURE_0 0x1E - #define SIGNATURE_1 0x97 - #define SIGNATURE_2 0x4C - - +-/* ========== Lock Bits ========== */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_BITS_EXIST +-#define __BOOT_LOCK_BOOT_BITS_EXIST +- +- +-/* ========== Signature ========== */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x97 +-#define SIGNATURE_2 0x4C +- +- -#endif /* _AVR_ATxmega128A1U_H_ */ -+#endif /* #ifdef _AVR_ATXMEGA128A1U_H_INCLUDED */ - -diff --git a/include/avr/iox128a3u.h b/include/avr/iox128a3u.h -new file mode 100644 -index 0000000..b6f16be ---- /dev/null -+++ b/include/avr/iox128a3u.h -@@ -0,0 +1,7628 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox128a3u.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA128A3U_H_INCLUDED -+#define _AVR_ATXMEGA128A3U_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -+#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -+#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -+#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -+#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -+#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -+#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -+#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -+#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -+#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -+#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -+#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -+#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -+#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -+#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -+#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -+#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -+#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -+#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -+#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -+#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -+#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -+#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+VPORT - Virtual Ports -+-------------------------------------------------------------------------- -+*/ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t USBCTRL; /* USB Control Register */ -+} CLK_t; -+ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t PRPB; /* Power Reduction Port B */ -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t PRPD; /* Power Reduction Port D */ -+ register8_t PRPE; /* Power Reduction Port E */ -+ register8_t PRPF; /* Power Reduction Port F */ -+} PR_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+/* USB Prescaler Division Factor */ -+typedef enum CLK_USBPSDIV_enum -+{ -+ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ -+ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ -+ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ -+ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ -+ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ -+ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -+} CLK_USBPSDIV_t; -+ -+/* USB Clock Source */ -+typedef enum CLK_USBSRC_enum -+{ -+ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ -+ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -+} CLK_USBSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control Register */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+/* 2 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC2MCREF_enum -+{ -+ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC2MCREF_t; -+ -+/* 32 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC32MCREF_enum -+{ -+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -+} OSC_RC32MCREF_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t JTAGUID; /* JTAG User ID */ -+ register8_t reserved_0x05; -+ register8_t MCUCR; /* MCU Control */ -+ register8_t ANAINIT; /* Analog Startup Delay */ -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t AWEXLOCK; /* AWEX Lock */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORTCFG - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t VPCTRLA; /* Virtual Port Control Register A */ -+ register8_t VPCTRLB; /* Virtual Port Control Register B */ -+ register8_t CLKEVOUT; /* Clock and Event Out Register */ -+ register8_t EBIOUT; /* EBI Output register */ -+ register8_t EVOUTSEL; /* Event Output Select */ -+} PORTCFG_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP02MAP_enum -+{ -+ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ -+ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ -+ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ -+ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ -+ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ -+ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ -+ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ -+ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ -+ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ -+ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ -+ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ -+ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ -+ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ -+ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ -+ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ -+ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -+} PORTCFG_VP02MAP_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP13MAP_enum -+{ -+ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ -+ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ -+ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ -+ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ -+ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ -+ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ -+ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ -+ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ -+ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ -+ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ -+ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ -+ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ -+ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ -+ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ -+ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ -+ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -+} PORTCFG_VP13MAP_t; -+ -+/* System Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ -+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ -+ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -+} PORTCFG_CLKOUT_t; -+ -+/* Peripheral Clock Output Select */ -+typedef enum PORTCFG_CLKOUTSEL_enum -+{ -+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -+} PORTCFG_CLKOUTSEL_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ -+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ -+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -+} PORTCFG_EVOUT_t; -+ -+/* Clock and Event Output Port */ -+typedef enum PORTCFG_CLKEVPIN_enum -+{ -+ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ -+ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -+} PORTCFG_CLKEVPIN_t; -+ -+/* EBI Address Output Port */ -+typedef enum PORTCFG_EBIADROUT_enum -+{ -+ PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ -+ PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ -+ PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ -+ PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ -+} PORTCFG_EBIADROUT_t; -+ -+/* EBI Chip Select Output Port */ -+typedef enum PORTCFG_EBICSOUT_enum -+{ -+ PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ -+} PORTCFG_EBICSOUT_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -+ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ -+ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ -+ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ -+ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AES - AES Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* AES Module */ -+typedef struct AES_struct -+{ -+ register8_t CTRL; /* AES Control Register */ -+ register8_t STATUS; /* AES Status Register */ -+ register8_t STATE; /* AES State Register */ -+ register8_t KEY; /* AES Key Register */ -+ register8_t INTCTRL; /* AES Interrupt Control Register */ -+} AES_t; -+ -+/* Interrupt level */ -+typedef enum AES_INTLVL_enum -+{ -+ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} AES_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ -+ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ -+ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ -+ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DMA - DMA Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* DMA Channel */ -+typedef struct DMA_CH_struct -+{ -+ register8_t CTRLA; /* Channel Control */ -+ register8_t CTRLB; /* Channel Control */ -+ register8_t ADDRCTRL; /* Address Control */ -+ register8_t TRIGSRC; /* Channel Trigger Source */ -+ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ -+ register8_t REPCNT; /* Channel Repeat Count */ -+ register8_t reserved_0x07; -+ register8_t SRCADDR0; /* Channel Source Address 0 */ -+ register8_t SRCADDR1; /* Channel Source Address 1 */ -+ register8_t SRCADDR2; /* Channel Source Address 2 */ -+ register8_t reserved_0x0B; -+ register8_t DESTADDR0; /* Channel Destination Address 0 */ -+ register8_t DESTADDR1; /* Channel Destination Address 1 */ -+ register8_t DESTADDR2; /* Channel Destination Address 2 */ -+ register8_t reserved_0x0F; -+} DMA_CH_t; -+ -+ -+/* DMA Controller */ -+typedef struct DMA_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t reserved_0x01; -+ register8_t reserved_0x02; -+ register8_t INTFLAGS; /* Transfer Interrupt Status */ -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x05; -+ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ DMA_CH_t CH0; /* DMA Channel 0 */ -+ DMA_CH_t CH1; /* DMA Channel 1 */ -+ DMA_CH_t CH2; /* DMA Channel 2 */ -+ DMA_CH_t CH3; /* DMA Channel 3 */ -+} DMA_t; -+ -+/* Burst mode */ -+typedef enum DMA_CH_BURSTLEN_enum -+{ -+ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ -+ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ -+ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ -+ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -+} DMA_CH_BURSTLEN_t; -+ -+/* Source address reload mode */ -+typedef enum DMA_CH_SRCRELOAD_enum -+{ -+ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ -+ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ -+ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ -+ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -+} DMA_CH_SRCRELOAD_t; -+ -+/* Source addressing mode */ -+typedef enum DMA_CH_SRCDIR_enum -+{ -+ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ -+ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ -+ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -+} DMA_CH_SRCDIR_t; -+ -+/* Destination adress reload mode */ -+typedef enum DMA_CH_DESTRELOAD_enum -+{ -+ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ -+ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ -+ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ -+ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -+} DMA_CH_DESTRELOAD_t; -+ -+/* Destination adressing mode */ -+typedef enum DMA_CH_DESTDIR_enum -+{ -+ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ -+ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ -+ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -+} DMA_CH_DESTDIR_t; -+ -+/* Transfer trigger source */ -+typedef enum DMA_CH_TRIGSRC_enum -+{ -+ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ -+ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ -+ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ -+ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ -+ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ -+ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ -+ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ -+ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ -+ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ -+ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ -+ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ -+ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ -+ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ -+ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ -+ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ -+ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ -+ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ -+ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ -+ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ -+ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ -+ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ -+ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ -+ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ -+ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ -+ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ -+ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ -+ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ -+ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ -+ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ -+ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ -+ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ -+ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ -+ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ -+ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ -+ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -+} DMA_CH_TRIGSRC_t; -+ -+/* Double buffering mode */ -+typedef enum DMA_DBUFMODE_enum -+{ -+ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ -+ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ -+ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ -+ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -+} DMA_DBUFMODE_t; -+ -+/* Priority mode */ -+typedef enum DMA_PRIMODE_enum -+{ -+ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ -+ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ -+ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ -+ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -+} DMA_PRIMODE_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_ERRINTLVL_enum -+{ -+ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ -+ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ -+ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -+} DMA_CH_ERRINTLVL_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_TRNINTLVL_enum -+{ -+ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ -+ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -+} DMA_CH_TRNINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ -+ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ -+ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ -+ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t CH4CTRL; /* Channel 4 Control Register */ -+ register8_t CH5CTRL; /* Channel 5 Control Register */ -+ register8_t CH6CTRL; /* Channel 6 Control Register */ -+ register8_t CH7CTRL; /* Channel 7 Control Register */ -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+} EVSYS_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ -+ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ -+ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ -+ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ -+ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ -+ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ -+ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ -+ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ -+ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ -+ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ -+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ -+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ -+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ -+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ -+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ -+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ -+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ -+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ -+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ -+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ -+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ -+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ -+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ -+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ -+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ -+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ -+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ -+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ -+ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ -+ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ -+ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ -+ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ -+ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ -+ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ -+ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ -+ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ -+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ -+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ -+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ -+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ -+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ -+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ -+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ -+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ -+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ -+ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ -+ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ -+ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ -+ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ -+ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ -+ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ -+ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ -+ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ -+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ -+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ -+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ -+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -+ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ -+ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ -+ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ -+ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ -+ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ -+ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ -+ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ -+ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -+ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ -+ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ -+ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ -+ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -+} EVSYS_CHMUX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ -+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ -+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ -+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ -+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} NVM_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t reserved_0x07; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ _WORDREGISTER(CH1RES); /* Channel 1 Result */ -+ _WORDREGISTER(CH2RES); /* Channel 2 Result */ -+ _WORDREGISTER(CH3RES); /* Channel 3 Result */ -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+ ADC_CH_t CH1; /* ADC Channel 1 */ -+ ADC_CH_t CH2; /* ADC Channel 2 */ -+ ADC_CH_t CH3; /* ADC Channel 3 */ -+} ADC_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -+ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+ ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 3) */ -+ ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Groud (Input Mode = 3) */ -+ ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Groud (Input Mode = 4) */ -+ ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 4) */ -+} ADC_CH_MUXNEG_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Current Limitation Mode */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ -+} ADC_CURRLIMIT_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Channel sweep selection */ -+typedef enum ADC_SWEEP_enum -+{ -+ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ -+ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ -+ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ -+ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -+} ADC_SWEEP_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ -+ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ -+ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ -+ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ -+ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ -+ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ -+ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ -+ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -+ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ -+ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ -+ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ -+ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* DMA request selection */ -+typedef enum ADC_DMASEL_enum -+{ -+ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ -+ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ -+ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ -+ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -+} ADC_DMASEL_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DAC - Digital/Analog Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Digital-to-Analog Converter */ -+typedef struct DAC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t EVCTRL; /* Event Input Control */ -+ register8_t reserved_0x04; -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0GAINCAL; /* Gain Calibration */ -+ register8_t CH0OFFSETCAL; /* Offset Calibration */ -+ register8_t CH1GAINCAL; /* Gain Calibration */ -+ register8_t CH1OFFSETCAL; /* Offset Calibration */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ -+ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -+} DAC_t; -+ -+/* Output channel selection */ -+typedef enum DAC_CHSEL_enum -+{ -+ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ -+ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ -+ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -+} DAC_CHSEL_t; -+ -+/* Reference voltage selection */ -+typedef enum DAC_REFSEL_enum -+{ -+ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ -+ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ -+ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ -+ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -+} DAC_REFSEL_t; -+ -+/* Event channel selection */ -+typedef enum DAC_EVSEL_enum -+{ -+ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ -+ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ -+ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ -+ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ -+ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ -+ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ -+ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ -+ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -+} DAC_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC - Real-Time Counter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Real-Time Counter */ -+typedef struct RTC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary register */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ _WORDREGISTER(CNT); /* Count Register */ -+ _WORDREGISTER(PER); /* Period Register */ -+ _WORDREGISTER(COMP); /* Compare Register */ -+} RTC_t; -+ -+/* Prescaler Factor */ -+typedef enum RTC_PRESCALER_enum -+{ -+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ -+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ -+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ -+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ -+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ -+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ -+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ -+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -+} RTC_PRESCALER_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC_COMPINTLVL_enum -+{ -+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC_OVFINTLVL_enum -+{ -+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+} TWI_t; -+ -+/* SDA Hold Time */ -+typedef enum TWI_SDAHOLD_enum -+{ -+ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ -+ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ -+ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ -+ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -+} TWI_SDAHOLD_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USB - USB -+-------------------------------------------------------------------------- -+*/ -+ -+/* USB Endpoint */ -+typedef struct USB_EP_struct -+{ -+ register8_t STATUS; /* Endpoint Status */ -+ register8_t CTRL; /* Endpoint Control */ -+ _WORDREGISTER(CNT); /* USB Endpoint Counter */ -+ _WORDREGISTER(DATAPTR); /* Data Pointer */ -+ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -+} USB_EP_t; -+ -+ -+/* Universal Serial Bus */ -+typedef struct USB_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t FIFOWP; /* FIFO Write Pointer Register */ -+ register8_t FIFORP; /* FIFO Read Pointer Register */ -+ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ -+ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ -+ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ -+ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t reserved_0x20; -+ register8_t reserved_0x21; -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t CAL0; /* Calibration Byte 0 */ -+ register8_t CAL1; /* Calibration Byte 1 */ -+} USB_t; -+ -+ -+/* USB Endpoint Table */ -+typedef struct USB_EP_TABLE_struct -+{ -+ USB_EP_t EP0OUT; /* Endpoint 0 */ -+ USB_EP_t EP0IN; /* Endpoint 0 */ -+ USB_EP_t EP1OUT; /* Endpoint 1 */ -+ USB_EP_t EP1IN; /* Endpoint 1 */ -+ USB_EP_t EP2OUT; /* Endpoint 2 */ -+ USB_EP_t EP2IN; /* Endpoint 2 */ -+ USB_EP_t EP3OUT; /* Endpoint 3 */ -+ USB_EP_t EP3IN; /* Endpoint 3 */ -+ USB_EP_t EP4OUT; /* Endpoint 4 */ -+ USB_EP_t EP4IN; /* Endpoint 4 */ -+ USB_EP_t EP5OUT; /* Endpoint 5 */ -+ USB_EP_t EP5IN; /* Endpoint 5 */ -+ USB_EP_t EP6OUT; /* Endpoint 6 */ -+ USB_EP_t EP6IN; /* Endpoint 6 */ -+ USB_EP_t EP7OUT; /* Endpoint 7 */ -+ USB_EP_t EP7IN; /* Endpoint 7 */ -+ USB_EP_t EP8OUT; /* Endpoint 8 */ -+ USB_EP_t EP8IN; /* Endpoint 8 */ -+ USB_EP_t EP9OUT; /* Endpoint 9 */ -+ USB_EP_t EP9IN; /* Endpoint 9 */ -+ USB_EP_t EP10OUT; /* Endpoint 10 */ -+ USB_EP_t EP10IN; /* Endpoint 10 */ -+ USB_EP_t EP11OUT; /* Endpoint 11 */ -+ USB_EP_t EP11IN; /* Endpoint 11 */ -+ USB_EP_t EP12OUT; /* Endpoint 12 */ -+ USB_EP_t EP12IN; /* Endpoint 12 */ -+ USB_EP_t EP13OUT; /* Endpoint 13 */ -+ USB_EP_t EP13IN; /* Endpoint 13 */ -+ USB_EP_t EP14OUT; /* Endpoint 14 */ -+ USB_EP_t EP14IN; /* Endpoint 14 */ -+ USB_EP_t EP15OUT; /* Endpoint 15 */ -+ USB_EP_t EP15IN; /* Endpoint 15 */ -+ register8_t reserved_0x100; -+ register8_t reserved_0x101; -+ register8_t reserved_0x102; -+ register8_t reserved_0x103; -+ register8_t reserved_0x104; -+ register8_t reserved_0x105; -+ register8_t reserved_0x106; -+ register8_t reserved_0x107; -+ register8_t reserved_0x108; -+ register8_t reserved_0x109; -+ register8_t reserved_0x10A; -+ register8_t reserved_0x10B; -+ register8_t reserved_0x10C; -+ register8_t reserved_0x10D; -+ register8_t reserved_0x10E; -+ register8_t reserved_0x10F; -+ register8_t FRAMENUML; /* Frame Number Low Byte */ -+ register8_t FRAMENUMH; /* Frame Number High Byte */ -+} USB_EP_TABLE_t; -+ -+/* Interrupt level */ -+typedef enum USB_INTLVL_enum -+{ -+ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} USB_INTLVL_t; -+ -+/* USB Endpoint Type */ -+typedef enum USB_EP_TYPE_enum -+{ -+ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ -+ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ -+ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ -+ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -+} USB_EP_TYPE_t; -+ -+/* USB Endpoint Buffersize */ -+typedef enum USB_EP_BUFSIZE_enum -+{ -+ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ -+ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ -+ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ -+ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ -+ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ -+ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ -+ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ -+ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -+} USB_EP_BUFSIZE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - I/O Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INT0MASK; /* Port Interrupt 0 Mask */ -+ register8_t INT1MASK; /* Port Interrupt 1 Mask */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t REMAP; /* I/O Port Pin Remap Register */ -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Port Interrupt 0 Level */ -+typedef enum PORT_INT0LVL_enum -+{ -+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INT0LVL_t; -+ -+/* Port Interrupt 1 Level */ -+typedef enum PORT_INT1LVL_enum -+{ -+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ -+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ -+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -+} PORT_INT1LVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 0 */ -+typedef struct TC0_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC0_t; -+ -+ -+/* 16-bit Timer/Counter 1 */ -+typedef struct TC1_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+} TC1_t; -+ -+/* Clock Selection */ -+typedef enum TC_CLKSEL_enum -+{ -+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC_CLKSEL_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC_WGMODE_enum -+{ -+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC_WGMODE_t; -+ -+/* Byte Mode */ -+typedef enum TC_BYTEM_enum -+{ -+ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ -+ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -+} TC_BYTEM_t; -+ -+/* Event Action */ -+typedef enum TC_EVACT_enum -+{ -+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ -+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ -+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ -+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ -+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ -+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC_EVSEL_enum -+{ -+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC_EVSEL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC_ERRINTLVL_enum -+{ -+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC_OVFINTLVL_enum -+{ -+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_OVFINTLVL_t; -+ -+/* Compare or Capture D Interrupt Level */ -+typedef enum TC_CCDINTLVL_enum -+{ -+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC_CCDINTLVL_t; -+ -+/* Compare or Capture C Interrupt Level */ -+typedef enum TC_CCCINTLVL_enum -+{ -+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC_CCCINTLVL_t; -+ -+/* Compare or Capture B Interrupt Level */ -+typedef enum TC_CCBINTLVL_enum -+{ -+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_CCBINTLVL_t; -+ -+/* Compare or Capture A Interrupt Level */ -+typedef enum TC_CCAINTLVL_enum -+{ -+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_CCAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC_CMD_enum -+{ -+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC2 - 16-bit Timer/Counter type 2 -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter type 2 */ -+typedef struct TC2_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t reserved_0x03; -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t reserved_0x08; -+ register8_t CTRLF; /* Control Register F */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t LCNT; /* Low Byte Count */ -+ register8_t HCNT; /* High Byte Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t LPER; /* Low Byte Period */ -+ register8_t HPER; /* High Byte Period */ -+ register8_t LCMPA; /* Low Byte Compare A */ -+ register8_t HCMPA; /* High Byte Compare A */ -+ register8_t LCMPB; /* Low Byte Compare B */ -+ register8_t HCMPB; /* High Byte Compare B */ -+ register8_t LCMPC; /* Low Byte Compare C */ -+ register8_t HCMPC; /* High Byte Compare C */ -+ register8_t LCMPD; /* Low Byte Compare D */ -+ register8_t HCMPD; /* High Byte Compare D */ -+} TC2_t; -+ -+/* Clock Selection */ -+typedef enum TC2_CLKSEL_enum -+{ -+ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC2_CLKSEL_t; -+ -+/* Byte Mode */ -+typedef enum TC2_BYTEM_enum -+{ -+ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ -+ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -+} TC2_BYTEM_t; -+ -+/* High Byte Underflow Interrupt Level */ -+typedef enum TC2_HUNFINTLVL_enum -+{ -+ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_HUNFINTLVL_t; -+ -+/* Low Byte Underflow Interrupt Level */ -+typedef enum TC2_LUNFINTLVL_enum -+{ -+ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LUNFINTLVL_t; -+ -+/* Low Byte Compare D Interrupt Level */ -+typedef enum TC2_LCMPDINTLVL_enum -+{ -+ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC2_LCMPDINTLVL_t; -+ -+/* Low Byte Compare C Interrupt Level */ -+typedef enum TC2_LCMPCINTLVL_enum -+{ -+ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC2_LCMPCINTLVL_t; -+ -+/* Low Byte Compare B Interrupt Level */ -+typedef enum TC2_LCMPBINTLVL_enum -+{ -+ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_LCMPBINTLVL_t; -+ -+/* Low Byte Compare A Interrupt Level */ -+typedef enum TC2_LCMPAINTLVL_enum -+{ -+ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LCMPAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMD_enum -+{ -+ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC2_CMD_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMDEN_enum -+{ -+ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ -+ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ -+ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -+} TC2_CMDEN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AWEX - Timer/Counter Advanced Waveform Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Advanced Waveform Extension */ -+typedef struct AWEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t FDEMASK; /* Fault Detection Event Mask */ -+ register8_t FDCTRL; /* Fault Detection Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t STATUSSET; /* Status Set Register */ -+ register8_t DTBOTH; /* Dead Time Both Sides */ -+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ -+ register8_t DTLS; /* Dead Time Low Side */ -+ register8_t DTHS; /* Dead Time High Side */ -+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ -+ register8_t DTHSBUF; /* Dead Time High Side Buffer */ -+ register8_t OUTOVEN; /* Output Override Enable */ -+} AWEX_t; -+ -+/* Fault Detect Action */ -+typedef enum AWEX_FDACT_enum -+{ -+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ -+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -+} AWEX_FDACT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+HIRES - Timer/Counter High-Resolution Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register */ -+} HIRES_t; -+ -+/* High Resolution Enable */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ -+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ -+ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ -+ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ -+ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -+} IRDA_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t FUSEBYTE0; /* JTAG User ID */ -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+} NVM_FUSES_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* Timer Oscillator pin location */ -+typedef enum TOSCSEL_enum -+{ -+ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ -+ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -+} TOSCSEL_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -+} BOD_t; -+ -+/* BOD operation */ -+typedef enum BODACT_enum -+{ -+ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BODACT_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WDP_enum -+{ -+ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ -+ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ -+ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ -+ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ -+ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ -+ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ -+ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ -+ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ -+ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ -+ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ -+ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -+} WDP_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LOCKBIT - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ -+ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t USBCAL0; /* USB Calibration Byte 0 */ -+ register8_t USBCAL1; /* USB Calibration Byte 1 */ -+ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ -+ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ -+ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ -+ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ -+ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ -+ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ -+ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ -+ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ -+ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ -+ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+ register8_t reserved_0x40; -+ register8_t reserved_0x41; -+ register8_t reserved_0x42; -+ register8_t reserved_0x43; -+ register8_t reserved_0x44; -+ register8_t reserved_0x45; -+ register8_t reserved_0x46; -+ register8_t reserved_0x47; -+} NVM_PROD_SIGNATURES_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define AES (*(AES_t *) 0x00C0) /* AES Module */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ -+#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ -+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -+#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -+#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -+#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -+#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -+#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -+#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ -+#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ -+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -+#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -+#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -+#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ -+#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ -+#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ -+#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ -+#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -+#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ -+#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ -+#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -+#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -+#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -+#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -+#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -+#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -+#define GPIO_GPIORA _SFR_MEM8(0x000A) -+#define GPIO_GPIORB _SFR_MEM8(0x000B) -+#define GPIO_GPIORC _SFR_MEM8(0x000C) -+#define GPIO_GPIORD _SFR_MEM8(0x000D) -+#define GPIO_GPIORE _SFR_MEM8(0x000E) -+#define GPIO_GPIORF _SFR_MEM8(0x000F) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+#define GPIO_GPIO4 _SFR_MEM8(0x0004) -+#define GPIO_GPIO5 _SFR_MEM8(0x0005) -+#define GPIO_GPIO6 _SFR_MEM8(0x0006) -+#define GPIO_GPIO7 _SFR_MEM8(0x0007) -+#define GPIO_GPIO8 _SFR_MEM8(0x0008) -+#define GPIO_GPIO9 _SFR_MEM8(0x0009) -+#define GPIO_GPIOA _SFR_MEM8(0x000A) -+#define GPIO_GPIOB _SFR_MEM8(0x000B) -+#define GPIO_GPIOC _SFR_MEM8(0x000C) -+#define GPIO_GPIOD _SFR_MEM8(0x000D) -+#define GPIO_GPIOE _SFR_MEM8(0x000E) -+#define GPIO_GPIOF _SFR_MEM8(0x000F) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -+#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -+#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -+#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -+#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -+#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -+#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) -+#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) -+#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -+#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) -+#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) -+#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+#define CLK_USBCTRL _SFR_MEM8(0x0044) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* DFLL - DFLL */ -+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -+#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -+#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPB _SFR_MEM8(0x0072) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPD _SFR_MEM8(0x0074) -+#define PR_PRPE _SFR_MEM8(0x0075) -+#define PR_PRPF _SFR_MEM8(0x0076) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_JTAGUID _SFR_MEM8(0x0094) -+#define MCU_MCUCR _SFR_MEM8(0x0096) -+#define MCU_ANAINIT _SFR_MEM8(0x0097) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_AWEXLOCK _SFR_MEM8(0x0099) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) -+#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) -+ -+/* AES - AES Module */ -+#define AES_CTRL _SFR_MEM8(0x00C0) -+#define AES_STATUS _SFR_MEM8(0x00C1) -+#define AES_STATE _SFR_MEM8(0x00C2) -+#define AES_KEY _SFR_MEM8(0x00C3) -+#define AES_INTCTRL _SFR_MEM8(0x00C4) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* DMA - DMA Controller */ -+#define DMA_CTRL _SFR_MEM8(0x0100) -+#define DMA_INTFLAGS _SFR_MEM8(0x0103) -+#define DMA_STATUS _SFR_MEM8(0x0104) -+#define DMA_TEMP _SFR_MEM16(0x0106) -+#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -+#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -+#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -+#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -+#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -+#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -+#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -+#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -+#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -+#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -+#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -+#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -+#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -+#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -+#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -+#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -+#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -+#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -+#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -+#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -+#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -+#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -+#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -+#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -+#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -+#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -+#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -+#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -+#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -+#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -+#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -+#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -+#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -+#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -+#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -+#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -+#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -+#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -+#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -+#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -+#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -+#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -+#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -+#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -+#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -+#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -+#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -+#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -+#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -+#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -+#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -+#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -+#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -+#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCA_CTRLA _SFR_MEM8(0x0200) -+#define ADCA_CTRLB _SFR_MEM8(0x0201) -+#define ADCA_REFCTRL _SFR_MEM8(0x0202) -+#define ADCA_EVCTRL _SFR_MEM8(0x0203) -+#define ADCA_PRESCALER _SFR_MEM8(0x0204) -+#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -+#define ADCA_TEMP _SFR_MEM8(0x0207) -+#define ADCA_CAL _SFR_MEM16(0x020C) -+#define ADCA_CH0RES _SFR_MEM16(0x0210) -+#define ADCA_CH1RES _SFR_MEM16(0x0212) -+#define ADCA_CH2RES _SFR_MEM16(0x0214) -+#define ADCA_CH3RES _SFR_MEM16(0x0216) -+#define ADCA_CMP _SFR_MEM16(0x0218) -+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -+#define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -+#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -+#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -+#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -+#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -+#define ADCA_CH1_RES _SFR_MEM16(0x022C) -+#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) -+#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -+#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -+#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -+#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -+#define ADCA_CH2_RES _SFR_MEM16(0x0234) -+#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) -+#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -+#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -+#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -+#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -+#define ADCA_CH3_RES _SFR_MEM16(0x023C) -+#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCB_CTRLA _SFR_MEM8(0x0240) -+#define ADCB_CTRLB _SFR_MEM8(0x0241) -+#define ADCB_REFCTRL _SFR_MEM8(0x0242) -+#define ADCB_EVCTRL _SFR_MEM8(0x0243) -+#define ADCB_PRESCALER _SFR_MEM8(0x0244) -+#define ADCB_INTFLAGS _SFR_MEM8(0x0246) -+#define ADCB_TEMP _SFR_MEM8(0x0247) -+#define ADCB_CAL _SFR_MEM16(0x024C) -+#define ADCB_CH0RES _SFR_MEM16(0x0250) -+#define ADCB_CH1RES _SFR_MEM16(0x0252) -+#define ADCB_CH2RES _SFR_MEM16(0x0254) -+#define ADCB_CH3RES _SFR_MEM16(0x0256) -+#define ADCB_CMP _SFR_MEM16(0x0258) -+#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) -+#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) -+#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) -+#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) -+#define ADCB_CH0_RES _SFR_MEM16(0x0264) -+#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) -+#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) -+#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) -+#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) -+#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) -+#define ADCB_CH1_RES _SFR_MEM16(0x026C) -+#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) -+#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) -+#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) -+#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) -+#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) -+#define ADCB_CH2_RES _SFR_MEM16(0x0274) -+#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) -+#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) -+#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) -+#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) -+#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) -+#define ADCB_CH3_RES _SFR_MEM16(0x027C) -+#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) -+ -+/* DAC - Digital-to-Analog Converter */ -+#define DACB_CTRLA _SFR_MEM8(0x0320) -+#define DACB_CTRLB _SFR_MEM8(0x0321) -+#define DACB_CTRLC _SFR_MEM8(0x0322) -+#define DACB_EVCTRL _SFR_MEM8(0x0323) -+#define DACB_STATUS _SFR_MEM8(0x0325) -+#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) -+#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) -+#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) -+#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) -+#define DACB_CH0DATA _SFR_MEM16(0x0338) -+#define DACB_CH1DATA _SFR_MEM16(0x033A) -+ -+/* AC - Analog Comparator */ -+#define ACA_AC0CTRL _SFR_MEM8(0x0380) -+#define ACA_AC1CTRL _SFR_MEM8(0x0381) -+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -+#define ACA_CTRLA _SFR_MEM8(0x0384) -+#define ACA_CTRLB _SFR_MEM8(0x0385) -+#define ACA_WINCTRL _SFR_MEM8(0x0386) -+#define ACA_STATUS _SFR_MEM8(0x0387) -+ -+/* AC - Analog Comparator */ -+#define ACB_AC0CTRL _SFR_MEM8(0x0390) -+#define ACB_AC1CTRL _SFR_MEM8(0x0391) -+#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -+#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -+#define ACB_CTRLA _SFR_MEM8(0x0394) -+#define ACB_CTRLB _SFR_MEM8(0x0395) -+#define ACB_WINCTRL _SFR_MEM8(0x0396) -+#define ACB_STATUS _SFR_MEM8(0x0397) -+ -+/* RTC - Real-Time Counter */ -+#define RTC_CTRL _SFR_MEM8(0x0400) -+#define RTC_STATUS _SFR_MEM8(0x0401) -+#define RTC_INTCTRL _SFR_MEM8(0x0402) -+#define RTC_INTFLAGS _SFR_MEM8(0x0403) -+#define RTC_TEMP _SFR_MEM8(0x0404) -+#define RTC_CNT _SFR_MEM16(0x0408) -+#define RTC_PER _SFR_MEM16(0x040A) -+#define RTC_COMP _SFR_MEM16(0x040C) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIE_CTRL _SFR_MEM8(0x04A0) -+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -+ -+/* USB - Universal Serial Bus */ -+#define USB_CTRLA _SFR_MEM8(0x04C0) -+#define USB_CTRLB _SFR_MEM8(0x04C1) -+#define USB_STATUS _SFR_MEM8(0x04C2) -+#define USB_ADDR _SFR_MEM8(0x04C3) -+#define USB_FIFOWP _SFR_MEM8(0x04C4) -+#define USB_FIFORP _SFR_MEM8(0x04C5) -+#define USB_EPPTR _SFR_MEM16(0x04C6) -+#define USB_INTCTRLA _SFR_MEM8(0x04C8) -+#define USB_INTCTRLB _SFR_MEM8(0x04C9) -+#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -+#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -+#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -+#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -+#define USB_CAL0 _SFR_MEM8(0x04FA) -+#define USB_CAL1 _SFR_MEM8(0x04FB) -+ -+/* PORT - I/O Ports */ -+#define PORTA_DIR _SFR_MEM8(0x0600) -+#define PORTA_DIRSET _SFR_MEM8(0x0601) -+#define PORTA_DIRCLR _SFR_MEM8(0x0602) -+#define PORTA_DIRTGL _SFR_MEM8(0x0603) -+#define PORTA_OUT _SFR_MEM8(0x0604) -+#define PORTA_OUTSET _SFR_MEM8(0x0605) -+#define PORTA_OUTCLR _SFR_MEM8(0x0606) -+#define PORTA_OUTTGL _SFR_MEM8(0x0607) -+#define PORTA_IN _SFR_MEM8(0x0608) -+#define PORTA_INTCTRL _SFR_MEM8(0x0609) -+#define PORTA_INT0MASK _SFR_MEM8(0x060A) -+#define PORTA_INT1MASK _SFR_MEM8(0x060B) -+#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_REMAP _SFR_MEM8(0x060E) -+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -+ -+/* PORT - I/O Ports */ -+#define PORTB_DIR _SFR_MEM8(0x0620) -+#define PORTB_DIRSET _SFR_MEM8(0x0621) -+#define PORTB_DIRCLR _SFR_MEM8(0x0622) -+#define PORTB_DIRTGL _SFR_MEM8(0x0623) -+#define PORTB_OUT _SFR_MEM8(0x0624) -+#define PORTB_OUTSET _SFR_MEM8(0x0625) -+#define PORTB_OUTCLR _SFR_MEM8(0x0626) -+#define PORTB_OUTTGL _SFR_MEM8(0x0627) -+#define PORTB_IN _SFR_MEM8(0x0628) -+#define PORTB_INTCTRL _SFR_MEM8(0x0629) -+#define PORTB_INT0MASK _SFR_MEM8(0x062A) -+#define PORTB_INT1MASK _SFR_MEM8(0x062B) -+#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -+#define PORTB_REMAP _SFR_MEM8(0x062E) -+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INT0MASK _SFR_MEM8(0x064A) -+#define PORTC_INT1MASK _SFR_MEM8(0x064B) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INT0MASK _SFR_MEM8(0x066A) -+#define PORTD_INT1MASK _SFR_MEM8(0x066B) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTE_DIR _SFR_MEM8(0x0680) -+#define PORTE_DIRSET _SFR_MEM8(0x0681) -+#define PORTE_DIRCLR _SFR_MEM8(0x0682) -+#define PORTE_DIRTGL _SFR_MEM8(0x0683) -+#define PORTE_OUT _SFR_MEM8(0x0684) -+#define PORTE_OUTSET _SFR_MEM8(0x0685) -+#define PORTE_OUTCLR _SFR_MEM8(0x0686) -+#define PORTE_OUTTGL _SFR_MEM8(0x0687) -+#define PORTE_IN _SFR_MEM8(0x0688) -+#define PORTE_INTCTRL _SFR_MEM8(0x0689) -+#define PORTE_INT0MASK _SFR_MEM8(0x068A) -+#define PORTE_INT1MASK _SFR_MEM8(0x068B) -+#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -+#define PORTE_REMAP _SFR_MEM8(0x068E) -+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) -+ -+/* PORT - I/O Ports */ -+#define PORTF_DIR _SFR_MEM8(0x06A0) -+#define PORTF_DIRSET _SFR_MEM8(0x06A1) -+#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -+#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -+#define PORTF_OUT _SFR_MEM8(0x06A4) -+#define PORTF_OUTSET _SFR_MEM8(0x06A5) -+#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -+#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -+#define PORTF_IN _SFR_MEM8(0x06A8) -+#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -+#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -+#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -+#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -+#define PORTF_REMAP _SFR_MEM8(0x06AE) -+#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -+#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -+#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -+#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -+#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -+#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -+#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -+#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -+#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCC0_CTRLA _SFR_MEM8(0x0800) -+#define TCC0_CTRLB _SFR_MEM8(0x0801) -+#define TCC0_CTRLC _SFR_MEM8(0x0802) -+#define TCC0_CTRLD _SFR_MEM8(0x0803) -+#define TCC0_CTRLE _SFR_MEM8(0x0804) -+#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -+#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -+#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -+#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC0_TEMP _SFR_MEM8(0x080F) -+#define TCC0_CNT _SFR_MEM16(0x0820) -+#define TCC0_PER _SFR_MEM16(0x0826) -+#define TCC0_CCA _SFR_MEM16(0x0828) -+#define TCC0_CCB _SFR_MEM16(0x082A) -+#define TCC0_CCC _SFR_MEM16(0x082C) -+#define TCC0_CCD _SFR_MEM16(0x082E) -+#define TCC0_PERBUF _SFR_MEM16(0x0836) -+#define TCC0_CCABUF _SFR_MEM16(0x0838) -+#define TCC0_CCBBUF _SFR_MEM16(0x083A) -+#define TCC0_CCCBUF _SFR_MEM16(0x083C) -+#define TCC0_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCC2_CTRLA _SFR_MEM8(0x0800) -+#define TCC2_CTRLB _SFR_MEM8(0x0801) -+#define TCC2_CTRLC _SFR_MEM8(0x0802) -+#define TCC2_CTRLE _SFR_MEM8(0x0804) -+#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC2_CTRLF _SFR_MEM8(0x0809) -+#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC2_LCNT _SFR_MEM8(0x0820) -+#define TCC2_HCNT _SFR_MEM8(0x0821) -+#define TCC2_LPER _SFR_MEM8(0x0826) -+#define TCC2_HPER _SFR_MEM8(0x0827) -+#define TCC2_LCMPA _SFR_MEM8(0x0828) -+#define TCC2_HCMPA _SFR_MEM8(0x0829) -+#define TCC2_LCMPB _SFR_MEM8(0x082A) -+#define TCC2_HCMPB _SFR_MEM8(0x082B) -+#define TCC2_LCMPC _SFR_MEM8(0x082C) -+#define TCC2_HCMPC _SFR_MEM8(0x082D) -+#define TCC2_LCMPD _SFR_MEM8(0x082E) -+#define TCC2_HCMPD _SFR_MEM8(0x082F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCC1_CTRLA _SFR_MEM8(0x0840) -+#define TCC1_CTRLB _SFR_MEM8(0x0841) -+#define TCC1_CTRLC _SFR_MEM8(0x0842) -+#define TCC1_CTRLD _SFR_MEM8(0x0843) -+#define TCC1_CTRLE _SFR_MEM8(0x0844) -+#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -+#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -+#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -+#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC1_TEMP _SFR_MEM8(0x084F) -+#define TCC1_CNT _SFR_MEM16(0x0860) -+#define TCC1_PER _SFR_MEM16(0x0866) -+#define TCC1_CCA _SFR_MEM16(0x0868) -+#define TCC1_CCB _SFR_MEM16(0x086A) -+#define TCC1_PERBUF _SFR_MEM16(0x0876) -+#define TCC1_CCABUF _SFR_MEM16(0x0878) -+#define TCC1_CCBBUF _SFR_MEM16(0x087A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXC_CTRL _SFR_MEM8(0x0880) -+#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -+#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -+#define AWEXC_STATUS _SFR_MEM8(0x0884) -+#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -+#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -+#define AWEXC_DTLS _SFR_MEM8(0x0888) -+#define AWEXC_DTHS _SFR_MEM8(0x0889) -+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x0890) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08A0) -+#define USARTC0_STATUS _SFR_MEM8(0x08A1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -+#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -+#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC1_DATA _SFR_MEM8(0x08B0) -+#define USARTC1_STATUS _SFR_MEM8(0x08B1) -+#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -+#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -+#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -+#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -+#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIC_CTRL _SFR_MEM8(0x08C0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -+#define SPIC_STATUS _SFR_MEM8(0x08C2) -+#define SPIC_DATA _SFR_MEM8(0x08C3) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCD0_CTRLA _SFR_MEM8(0x0900) -+#define TCD0_CTRLB _SFR_MEM8(0x0901) -+#define TCD0_CTRLC _SFR_MEM8(0x0902) -+#define TCD0_CTRLD _SFR_MEM8(0x0903) -+#define TCD0_CTRLE _SFR_MEM8(0x0904) -+#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -+#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -+#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -+#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -+#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD0_TEMP _SFR_MEM8(0x090F) -+#define TCD0_CNT _SFR_MEM16(0x0920) -+#define TCD0_PER _SFR_MEM16(0x0926) -+#define TCD0_CCA _SFR_MEM16(0x0928) -+#define TCD0_CCB _SFR_MEM16(0x092A) -+#define TCD0_CCC _SFR_MEM16(0x092C) -+#define TCD0_CCD _SFR_MEM16(0x092E) -+#define TCD0_PERBUF _SFR_MEM16(0x0936) -+#define TCD0_CCABUF _SFR_MEM16(0x0938) -+#define TCD0_CCBBUF _SFR_MEM16(0x093A) -+#define TCD0_CCCBUF _SFR_MEM16(0x093C) -+#define TCD0_CCDBUF _SFR_MEM16(0x093E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCD2_CTRLA _SFR_MEM8(0x0900) -+#define TCD2_CTRLB _SFR_MEM8(0x0901) -+#define TCD2_CTRLC _SFR_MEM8(0x0902) -+#define TCD2_CTRLE _SFR_MEM8(0x0904) -+#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD2_CTRLF _SFR_MEM8(0x0909) -+#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD2_LCNT _SFR_MEM8(0x0920) -+#define TCD2_HCNT _SFR_MEM8(0x0921) -+#define TCD2_LPER _SFR_MEM8(0x0926) -+#define TCD2_HPER _SFR_MEM8(0x0927) -+#define TCD2_LCMPA _SFR_MEM8(0x0928) -+#define TCD2_HCMPA _SFR_MEM8(0x0929) -+#define TCD2_LCMPB _SFR_MEM8(0x092A) -+#define TCD2_HCMPB _SFR_MEM8(0x092B) -+#define TCD2_LCMPC _SFR_MEM8(0x092C) -+#define TCD2_HCMPC _SFR_MEM8(0x092D) -+#define TCD2_LCMPD _SFR_MEM8(0x092E) -+#define TCD2_HCMPD _SFR_MEM8(0x092F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCD1_CTRLA _SFR_MEM8(0x0940) -+#define TCD1_CTRLB _SFR_MEM8(0x0941) -+#define TCD1_CTRLC _SFR_MEM8(0x0942) -+#define TCD1_CTRLD _SFR_MEM8(0x0943) -+#define TCD1_CTRLE _SFR_MEM8(0x0944) -+#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -+#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -+#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -+#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -+#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -+#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -+#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -+#define TCD1_TEMP _SFR_MEM8(0x094F) -+#define TCD1_CNT _SFR_MEM16(0x0960) -+#define TCD1_PER _SFR_MEM16(0x0966) -+#define TCD1_CCA _SFR_MEM16(0x0968) -+#define TCD1_CCB _SFR_MEM16(0x096A) -+#define TCD1_PERBUF _SFR_MEM16(0x0976) -+#define TCD1_CCABUF _SFR_MEM16(0x0978) -+#define TCD1_CCBBUF _SFR_MEM16(0x097A) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESD_CTRLA _SFR_MEM8(0x0990) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD0_DATA _SFR_MEM8(0x09A0) -+#define USARTD0_STATUS _SFR_MEM8(0x09A1) -+#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -+#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -+#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD1_DATA _SFR_MEM8(0x09B0) -+#define USARTD1_STATUS _SFR_MEM8(0x09B1) -+#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -+#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -+#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -+#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -+#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPID_CTRL _SFR_MEM8(0x09C0) -+#define SPID_INTCTRL _SFR_MEM8(0x09C1) -+#define SPID_STATUS _SFR_MEM8(0x09C2) -+#define SPID_DATA _SFR_MEM8(0x09C3) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCE0_CTRLA _SFR_MEM8(0x0A00) -+#define TCE0_CTRLB _SFR_MEM8(0x0A01) -+#define TCE0_CTRLC _SFR_MEM8(0x0A02) -+#define TCE0_CTRLD _SFR_MEM8(0x0A03) -+#define TCE0_CTRLE _SFR_MEM8(0x0A04) -+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE0_TEMP _SFR_MEM8(0x0A0F) -+#define TCE0_CNT _SFR_MEM16(0x0A20) -+#define TCE0_PER _SFR_MEM16(0x0A26) -+#define TCE0_CCA _SFR_MEM16(0x0A28) -+#define TCE0_CCB _SFR_MEM16(0x0A2A) -+#define TCE0_CCC _SFR_MEM16(0x0A2C) -+#define TCE0_CCD _SFR_MEM16(0x0A2E) -+#define TCE0_PERBUF _SFR_MEM16(0x0A36) -+#define TCE0_CCABUF _SFR_MEM16(0x0A38) -+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCE2_CTRLA _SFR_MEM8(0x0A00) -+#define TCE2_CTRLB _SFR_MEM8(0x0A01) -+#define TCE2_CTRLC _SFR_MEM8(0x0A02) -+#define TCE2_CTRLE _SFR_MEM8(0x0A04) -+#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE2_CTRLF _SFR_MEM8(0x0A09) -+#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE2_LCNT _SFR_MEM8(0x0A20) -+#define TCE2_HCNT _SFR_MEM8(0x0A21) -+#define TCE2_LPER _SFR_MEM8(0x0A26) -+#define TCE2_HPER _SFR_MEM8(0x0A27) -+#define TCE2_LCMPA _SFR_MEM8(0x0A28) -+#define TCE2_HCMPA _SFR_MEM8(0x0A29) -+#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -+#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -+#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -+#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -+#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -+#define TCE2_HCMPD _SFR_MEM8(0x0A2F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCE1_CTRLA _SFR_MEM8(0x0A40) -+#define TCE1_CTRLB _SFR_MEM8(0x0A41) -+#define TCE1_CTRLC _SFR_MEM8(0x0A42) -+#define TCE1_CTRLD _SFR_MEM8(0x0A43) -+#define TCE1_CTRLE _SFR_MEM8(0x0A44) -+#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) -+#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) -+#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) -+#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) -+#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) -+#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) -+#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) -+#define TCE1_TEMP _SFR_MEM8(0x0A4F) -+#define TCE1_CNT _SFR_MEM16(0x0A60) -+#define TCE1_PER _SFR_MEM16(0x0A66) -+#define TCE1_CCA _SFR_MEM16(0x0A68) -+#define TCE1_CCB _SFR_MEM16(0x0A6A) -+#define TCE1_PERBUF _SFR_MEM16(0x0A76) -+#define TCE1_CCABUF _SFR_MEM16(0x0A78) -+#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXE_CTRL _SFR_MEM8(0x0A80) -+#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) -+#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) -+#define AWEXE_STATUS _SFR_MEM8(0x0A84) -+#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) -+#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) -+#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) -+#define AWEXE_DTLS _SFR_MEM8(0x0A88) -+#define AWEXE_DTHS _SFR_MEM8(0x0A89) -+#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) -+#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) -+#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESE_CTRLA _SFR_MEM8(0x0A90) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE0_DATA _SFR_MEM8(0x0AA0) -+#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -+#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -+#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -+#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -+#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -+#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE1_DATA _SFR_MEM8(0x0AB0) -+#define USARTE1_STATUS _SFR_MEM8(0x0AB1) -+#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) -+#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) -+#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) -+#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) -+#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIE_CTRL _SFR_MEM8(0x0AC0) -+#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) -+#define SPIE_STATUS _SFR_MEM8(0x0AC2) -+#define SPIE_DATA _SFR_MEM8(0x0AC3) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCF0_CTRLA _SFR_MEM8(0x0B00) -+#define TCF0_CTRLB _SFR_MEM8(0x0B01) -+#define TCF0_CTRLC _SFR_MEM8(0x0B02) -+#define TCF0_CTRLD _SFR_MEM8(0x0B03) -+#define TCF0_CTRLE _SFR_MEM8(0x0B04) -+#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -+#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -+#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -+#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -+#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -+#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -+#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -+#define TCF0_TEMP _SFR_MEM8(0x0B0F) -+#define TCF0_CNT _SFR_MEM16(0x0B20) -+#define TCF0_PER _SFR_MEM16(0x0B26) -+#define TCF0_CCA _SFR_MEM16(0x0B28) -+#define TCF0_CCB _SFR_MEM16(0x0B2A) -+#define TCF0_CCC _SFR_MEM16(0x0B2C) -+#define TCF0_CCD _SFR_MEM16(0x0B2E) -+#define TCF0_PERBUF _SFR_MEM16(0x0B36) -+#define TCF0_CCABUF _SFR_MEM16(0x0B38) -+#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -+#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -+#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCF2_CTRLA _SFR_MEM8(0x0B00) -+#define TCF2_CTRLB _SFR_MEM8(0x0B01) -+#define TCF2_CTRLC _SFR_MEM8(0x0B02) -+#define TCF2_CTRLE _SFR_MEM8(0x0B04) -+#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -+#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -+#define TCF2_CTRLF _SFR_MEM8(0x0B09) -+#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -+#define TCF2_LCNT _SFR_MEM8(0x0B20) -+#define TCF2_HCNT _SFR_MEM8(0x0B21) -+#define TCF2_LPER _SFR_MEM8(0x0B26) -+#define TCF2_HPER _SFR_MEM8(0x0B27) -+#define TCF2_LCMPA _SFR_MEM8(0x0B28) -+#define TCF2_HCMPA _SFR_MEM8(0x0B29) -+#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -+#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -+#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -+#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -+#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -+#define TCF2_HCMPD _SFR_MEM8(0x0B2F) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESF_CTRLA _SFR_MEM8(0x0B90) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTF0_DATA _SFR_MEM8(0x0BA0) -+#define USARTF0_STATUS _SFR_MEM8(0x0BA1) -+#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) -+#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) -+#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) -+#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) -+#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* VPORT - Virtual Ports */ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* CLK.USBCTRL bit masks and bit positions */ -+#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -+#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -+#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -+#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -+#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -+#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -+#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -+#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ -+ -+#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -+#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -+#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ -+ -+#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_USB_bm 0x40 /* USB bit mask. */ -+#define PR_USB_bp 6 /* USB bit position. */ -+ -+#define PR_AES_bm 0x10 /* AES bit mask. */ -+#define PR_AES_bp 4 /* AES bit position. */ -+ -+#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -+#define PR_EBI_bp 3 /* External Bus Interface bit position. */ -+ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -+#define PR_DMA_bp 0 /* DMA-Controller bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -+#define PR_DAC_bp 2 /* Port A DAC bit position. */ -+ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPB bit masks and bit positions */ -+/* PR_DAC Predefined. */ -+/* PR_DAC Predefined. */ -+ -+/* PR_ADC Predefined. */ -+/* PR_ADC Predefined. */ -+ -+/* PR_AC Predefined. */ -+/* PR_AC Predefined. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -+#define PR_USART1_bp 5 /* Port C USART1 bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -+#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ -+ -+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -+ -+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ -+ -+/* PR.PRPD bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPE bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPF bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -+#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -+#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ -+ -+#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ -+ -+#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -+#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.MCUCR bit masks and bit positions */ -+#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -+#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ -+ -+/* MCU.ANAINIT bit masks and bit positions */ -+#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -+#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -+#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -+#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -+#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -+#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ -+ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -+#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ -+ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.AWEXLOCK bit masks and bit positions */ -+#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ -+#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ -+ -+#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -+#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ -+ -+#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ -+#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ -+ -+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* PORTCFG - Port Configuration */ -+/* PORTCFG.VPCTRLA bit masks and bit positions */ -+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ -+ -+/* PORTCFG.VPCTRLB bit masks and bit positions */ -+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ -+ -+/* PORTCFG.CLKEVOUT bit masks and bit positions */ -+#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ -+ -+#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -+#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -+#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -+#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -+#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -+#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ -+ -+#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -+#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ -+ -+#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -+#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ -+ -+/* PORTCFG.EBIOUT bit masks and bit positions */ -+#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ -+#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ -+#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ -+#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ -+#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ -+#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ -+ -+#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ -+#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ -+#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ -+#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ -+#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ -+#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ -+ -+/* PORTCFG.EVOUTSEL bit masks and bit positions */ -+#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -+#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -+#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -+#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -+#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -+#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -+#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -+#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ -+ -+/* AES - AES Module */ -+/* AES.CTRL bit masks and bit positions */ -+#define AES_START_bm 0x80 /* Start/Run bit mask. */ -+#define AES_START_bp 7 /* Start/Run bit position. */ -+ -+#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -+#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ -+ -+#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -+#define AES_RESET_bp 5 /* AES Software Reset bit position. */ -+ -+#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -+#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ -+ -+#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -+#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ -+ -+/* AES.STATUS bit masks and bit positions */ -+#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -+#define AES_ERROR_bp 7 /* AES Error bit position. */ -+ -+#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -+#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ -+ -+/* AES.INTCTRL bit masks and bit positions */ -+#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -+#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* DMA - DMA Controller */ -+/* DMA_CH.CTRLA bit masks and bit positions */ -+#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -+#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ -+ -+#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -+#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ -+ -+#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -+#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ -+ -+#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -+#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ -+ -+#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -+#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ -+ -+#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -+#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -+#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -+#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -+#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -+#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ -+ -+/* DMA_CH.CTRLB bit masks and bit positions */ -+#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -+#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ -+ -+#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -+#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ -+ -+#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -+#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ -+ -+#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -+#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -+#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -+#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -+#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -+#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ -+ -+#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -+#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -+#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -+#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -+#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -+#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ -+ -+/* DMA_CH.ADDRCTRL bit masks and bit positions */ -+#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -+#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -+#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -+#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -+#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -+#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ -+ -+#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -+#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -+#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -+#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -+#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -+#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ -+ -+#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -+#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -+#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -+#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -+#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -+#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ -+ -+#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -+#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -+#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -+#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -+#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -+#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ -+ -+/* DMA_CH.TRIGSRC bit masks and bit positions */ -+#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -+#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -+#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -+#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -+#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -+#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -+#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -+#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -+#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -+#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -+#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -+#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -+#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -+#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -+#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -+#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -+#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -+#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ -+ -+/* DMA.CTRL bit masks and bit positions */ -+#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -+#define DMA_ENABLE_bp 7 /* Enable bit position. */ -+ -+#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -+#define DMA_RESET_bp 6 /* Software Reset bit position. */ -+ -+#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -+#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -+#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -+#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -+#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -+#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ -+ -+#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -+#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -+#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -+#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -+#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -+#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ -+ -+/* DMA.INTFLAGS bit masks and bit positions */ -+#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ -+ -+/* DMA.STATUS bit masks and bit positions */ -+#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -+#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ -+ -+#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -+#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ -+ -+#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -+#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ -+ -+#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -+#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ -+ -+#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -+#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ -+ -+#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -+#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ -+ -+#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -+#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ -+ -+#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -+#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH4MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH5MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH6MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH7MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_QDIRM Predefined. */ -+/* EVSYS_QDIRM Predefined. */ -+ -+/* EVSYS_QDIEN Predefined. */ -+/* EVSYS_QDIEN Predefined. */ -+ -+/* EVSYS_QDEN Predefined. */ -+/* EVSYS_QDEN Predefined. */ -+ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH4CTRL bit masks and bit positions */ -+/* EVSYS_QDIRM Predefined. */ -+/* EVSYS_QDIRM Predefined. */ -+ -+/* EVSYS_QDIEN Predefined. */ -+/* EVSYS_QDIEN Predefined. */ -+ -+/* EVSYS_QDEN Predefined. */ -+/* EVSYS_QDEN Predefined. */ -+ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH5CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH6CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH7CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0x7F /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ -+ -+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ -+ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -+#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ -+#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -+#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -+#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -+#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -+#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -+#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -+#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -+#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -+#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -+#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ -+ -+#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -+#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -+#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -+#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -+#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -+#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -+#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -+#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -+#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -+#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -+#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -+#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -+#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -+#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -+#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ -+ -+#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -+#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ -+ -+#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -+#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ -+ -+#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -+#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ -+ -+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -+#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ -+#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ -+ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -+#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -+#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -+#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -+#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -+#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ -+ -+#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -+#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -+#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ -+ -+#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -+#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ -+ -+#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -+#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ -+ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* DAC - Digital/Analog Converter */ -+/* DAC.CTRLA bit masks and bit positions */ -+#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -+#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ -+ -+#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -+#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ -+ -+#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -+#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ -+ -+#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -+#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ -+ -+#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define DAC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* DAC.CTRLB bit masks and bit positions */ -+#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -+#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -+#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -+#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -+#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -+#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ -+ -+#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -+#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ -+ -+#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -+#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ -+ -+/* DAC.CTRLC bit masks and bit positions */ -+#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -+#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -+#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -+#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -+#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -+#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ -+ -+#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -+#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ -+ -+/* DAC.EVCTRL bit masks and bit positions */ -+#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -+#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ -+ -+#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -+#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -+#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -+#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -+#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -+#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -+#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -+#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ -+ -+/* DAC.STATUS bit masks and bit positions */ -+#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -+#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ -+ -+#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -+#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ -+ -+/* DAC.CH0GAINCAL bit masks and bit positions */ -+#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -+#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -+#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -+#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -+#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -+#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -+#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -+#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -+#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -+#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -+#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -+#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -+#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -+#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -+#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -+#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ -+ -+/* DAC.CH0OFFSETCAL bit masks and bit positions */ -+#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -+#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -+#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -+#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -+#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -+#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -+#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -+#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -+#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -+#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -+#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -+#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -+#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -+#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -+#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -+#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ -+ -+/* DAC.CH1GAINCAL bit masks and bit positions */ -+#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -+#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -+#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -+#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -+#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -+#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -+#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -+#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -+#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -+#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -+#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -+#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -+#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -+#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -+#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -+#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ -+ -+/* DAC.CH1OFFSETCAL bit masks and bit positions */ -+#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -+#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -+#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -+#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -+#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -+#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -+#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -+#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -+#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -+#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -+#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -+#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -+#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -+#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -+#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -+#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -+#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HSMODE Predefined. */ -+/* AC_HSMODE Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* RTC - Real-Time Counter */ -+/* RTC.CTRL bit masks and bit positions */ -+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ -+ -+/* RTC.STATUS bit masks and bit positions */ -+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC.INTCTRL bit masks and bit positions */ -+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC.INTFLAGS bit masks and bit positions */ -+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* USB - USB */ -+/* USB_EP.STATUS bit masks and bit positions */ -+#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -+#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ -+ -+#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -+#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ -+ -+#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -+#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ -+ -+#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -+#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ -+ -+#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -+#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ -+ -+#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -+#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ -+ -+#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -+#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ -+ -+#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -+#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ -+ -+#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ -+ -+#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ -+ -+#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -+#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ -+ -+/* USB_EP.CTRL bit masks and bit positions */ -+#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -+#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -+#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -+#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -+#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -+#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ -+ -+#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -+#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ -+ -+#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -+#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ -+ -+#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -+#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ -+ -+#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -+#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ -+ -+#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -+#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -+#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -+#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -+#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -+#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -+#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -+#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ -+ -+/* USB_EP.CNT bit masks and bit positions */ -+#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -+#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ -+ -+/* USB.CTRLA bit masks and bit positions */ -+#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -+#define USB_ENABLE_bp 7 /* USB Enable bit position. */ -+ -+#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -+#define USB_SPEED_bp 6 /* Speed Select bit position. */ -+ -+#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -+#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ -+ -+#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -+#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ -+ -+#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -+#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -+#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -+#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -+#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -+#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -+#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -+#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -+#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -+#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ -+ -+/* USB.CTRLB bit masks and bit positions */ -+#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -+#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ -+ -+#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -+#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ -+ -+#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -+#define USB_GNACK_bp 1 /* Global NACK bit position. */ -+ -+#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -+#define USB_ATTACH_bp 0 /* Attach bit position. */ -+ -+/* USB.STATUS bit masks and bit positions */ -+#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -+#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ -+ -+#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -+#define USB_RESUME_bp 2 /* Resume bit position. */ -+ -+#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -+#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ -+ -+#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -+#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ -+ -+/* USB.ADDR bit masks and bit positions */ -+#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -+#define USB_ADDR_gp 0 /* Device Address group position. */ -+#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -+#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -+#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -+#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -+#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -+#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -+#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -+#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -+#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -+#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -+#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -+#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -+#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -+#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ -+ -+/* USB.FIFOWP bit masks and bit positions */ -+#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -+#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -+#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -+#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -+#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -+#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -+#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -+#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -+#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -+#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -+#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -+#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ -+ -+/* USB.FIFORP bit masks and bit positions */ -+#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -+#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -+#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -+#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -+#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -+#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -+#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -+#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -+#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -+#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -+#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -+#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ -+ -+/* USB.INTCTRLA bit masks and bit positions */ -+#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -+#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ -+ -+#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -+#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ -+ -+#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -+#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ -+ -+#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -+#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ -+ -+#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* USB.INTCTRLB bit masks and bit positions */ -+#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -+#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ -+ -+#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -+#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ -+ -+/* USB.INTFLAGSACLR bit masks and bit positions */ -+#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -+#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ -+ -+#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -+#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ -+ -+#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -+#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ -+ -+#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -+#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ -+ -+#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -+#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ -+ -+#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -+#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ -+ -+#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -+#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ -+ -+#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -+#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSASET bit masks and bit positions */ -+/* USB_SOFIF Predefined. */ -+/* USB_SOFIF Predefined. */ -+ -+/* USB_SUSPENDIF Predefined. */ -+/* USB_SUSPENDIF Predefined. */ -+ -+/* USB_RESUMEIF Predefined. */ -+/* USB_RESUMEIF Predefined. */ -+ -+/* USB_RSTIF Predefined. */ -+/* USB_RSTIF Predefined. */ -+ -+/* USB_CRCIF Predefined. */ -+/* USB_CRCIF Predefined. */ -+ -+/* USB_UNFIF Predefined. */ -+/* USB_UNFIF Predefined. */ -+ -+/* USB_OVFIF Predefined. */ -+/* USB_OVFIF Predefined. */ -+ -+/* USB_STALLIF Predefined. */ -+/* USB_STALLIF Predefined. */ -+ -+/* USB.INTFLAGSBCLR bit masks and bit positions */ -+#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -+#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ -+ -+#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -+#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSBSET bit masks and bit positions */ -+/* USB_TRNIF Predefined. */ -+/* USB_TRNIF Predefined. */ -+ -+/* USB_SETUPIF Predefined. */ -+/* USB_SETUPIF Predefined. */ -+ -+/* PORT - I/O Port Configuration */ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ -+ -+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -+#define PORT_SPI_bp 5 /* SPI bit position. */ -+ -+#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -+#define PORT_USART0_bp 4 /* USART0 bit position. */ -+ -+#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -+#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ -+ -+#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -+#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ -+ -+#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -+#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ -+ -+#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -+#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ -+ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC0.CTRLA bit masks and bit positions */ -+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC0.CTRLB bit masks and bit positions */ -+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ -+ -+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ -+ -+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC0.CTRLC bit masks and bit positions */ -+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ -+ -+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ -+ -+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC0.CTRLD bit masks and bit positions */ -+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC0_EVACT_gp 5 /* Event Action group position. */ -+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC0.CTRLE bit masks and bit positions */ -+#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC0.INTCTRLA bit masks and bit positions */ -+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC0.INTCTRLB bit masks and bit positions */ -+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ -+ -+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ -+ -+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC0.CTRLFCLR bit masks and bit positions */ -+#define TC0_CMD_gm 0x0C /* Command group mask. */ -+#define TC0_CMD_gp 2 /* Command group position. */ -+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC0_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC0_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC0_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC0.CTRLFSET bit masks and bit positions */ -+/* TC0_CMD Predefined. */ -+/* TC0_CMD Predefined. */ -+ -+/* TC0_LUPD Predefined. */ -+/* TC0_LUPD Predefined. */ -+ -+/* TC0_DIR Predefined. */ -+/* TC0_DIR Predefined. */ -+ -+/* TC0.CTRLGCLR bit masks and bit positions */ -+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ -+ -+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ -+ -+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC0.CTRLGSET bit masks and bit positions */ -+/* TC0_CCDBV Predefined. */ -+/* TC0_CCDBV Predefined. */ -+ -+/* TC0_CCCBV Predefined. */ -+/* TC0_CCCBV Predefined. */ -+ -+/* TC0_CCBBV Predefined. */ -+/* TC0_CCBBV Predefined. */ -+ -+/* TC0_CCABV Predefined. */ -+/* TC0_CCABV Predefined. */ -+ -+/* TC0_PERBV Predefined. */ -+/* TC0_PERBV Predefined. */ -+ -+/* TC0.INTFLAGS bit masks and bit positions */ -+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ -+ -+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ -+ -+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC1.CTRLA bit masks and bit positions */ -+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC1.CTRLB bit masks and bit positions */ -+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC1.CTRLC bit masks and bit positions */ -+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC1.CTRLD bit masks and bit positions */ -+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC1_EVACT_gp 5 /* Event Action group position. */ -+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC1.CTRLE bit masks and bit positions */ -+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ -+ -+/* TC1.INTCTRLA bit masks and bit positions */ -+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC1.INTCTRLB bit masks and bit positions */ -+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC1.CTRLFCLR bit masks and bit positions */ -+#define TC1_CMD_gm 0x0C /* Command group mask. */ -+#define TC1_CMD_gp 2 /* Command group position. */ -+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC1_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC1_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC1_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC1.CTRLFSET bit masks and bit positions */ -+/* TC1_CMD Predefined. */ -+/* TC1_CMD Predefined. */ -+ -+/* TC1_LUPD Predefined. */ -+/* TC1_LUPD Predefined. */ -+ -+/* TC1_DIR Predefined. */ -+/* TC1_DIR Predefined. */ -+ -+/* TC1.CTRLGCLR bit masks and bit positions */ -+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC1.CTRLGSET bit masks and bit positions */ -+/* TC1_CCBBV Predefined. */ -+/* TC1_CCBBV Predefined. */ -+ -+/* TC1_CCABV Predefined. */ -+/* TC1_CCABV Predefined. */ -+ -+/* TC1_PERBV Predefined. */ -+/* TC1_PERBV Predefined. */ -+ -+/* TC1.INTFLAGS bit masks and bit positions */ -+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+/* TC2.CTRLA bit masks and bit positions */ -+#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC2.CTRLB bit masks and bit positions */ -+#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -+#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ -+ -+#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -+#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ -+ -+#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -+#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ -+ -+#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -+#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ -+ -+#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -+#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ -+ -+#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -+#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ -+ -+#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -+#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ -+ -+#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -+#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ -+ -+/* TC2.CTRLC bit masks and bit positions */ -+#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -+#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ -+ -+#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -+#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ -+ -+#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -+#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ -+ -+#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -+#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ -+ -+#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -+#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ -+ -+#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -+#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ -+ -+#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -+#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ -+ -+#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -+#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ -+ -+/* TC2.CTRLE bit masks and bit positions */ -+#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC2.INTCTRLA bit masks and bit positions */ -+#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -+#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -+#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -+#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -+#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -+#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ -+ -+#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -+#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -+#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -+#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -+#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -+#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ -+ -+/* TC2.INTCTRLB bit masks and bit positions */ -+#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -+#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -+#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -+#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -+#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -+#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -+#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -+#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -+#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -+#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -+#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -+#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -+#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -+#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -+#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -+#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -+#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -+#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -+#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -+#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -+#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ -+ -+/* TC2.CTRLF bit masks and bit positions */ -+#define TC2_CMD_gm 0x0C /* Command group mask. */ -+#define TC2_CMD_gp 2 /* Command group position. */ -+#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC2_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -+#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -+#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -+#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -+#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -+#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ -+ -+/* TC2.INTFLAGS bit masks and bit positions */ -+#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -+#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ -+ -+#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -+#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ -+ -+#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -+#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ -+ -+#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -+#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ -+ -+#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ -+ -+#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ -+ -+/* AWEX - Timer/Counter Advanced Waveform Extension */ -+/* AWEX.CTRL bit masks and bit positions */ -+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ -+ -+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ -+ -+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ -+ -+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ -+ -+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ -+ -+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ -+ -+/* AWEX.FDCTRL bit masks and bit positions */ -+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ -+ -+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ -+ -+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ -+ -+/* AWEX.STATUS bit masks and bit positions */ -+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ -+ -+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ -+ -+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ -+ -+/* AWEX.STATUSSET bit masks and bit positions */ -+/* AWEX_FDF Predefined. */ -+/* AWEX_FDF Predefined. */ -+ -+/* AWEX_DTHSBUFV Predefined. */ -+/* AWEX_DTHSBUFV Predefined. */ -+ -+/* AWEX_DTLSBUFV Predefined. */ -+/* AWEX_DTLSBUFV Predefined. */ -+ -+/* HIRES - Timer/Counter High-Resolution Extension */ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -+#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -+#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -+#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -+#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -+#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -+#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -+#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -+#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -+#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -+#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -+#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -+#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -+#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -+#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -+#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -+#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -+#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -+#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ -+ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -+#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -+#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* LOCKBIT - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT0_vect_num 2 -+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -+#define PORTC_INT1_vect_num 3 -+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT0_vect_num 4 -+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -+#define PORTR_INT1_vect_num 5 -+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ -+ -+/* DMA interrupt vectors */ -+#define DMA_CH0_vect_num 6 -+#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -+#define DMA_CH1_vect_num 7 -+#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -+#define DMA_CH2_vect_num 8 -+#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -+#define DMA_CH3_vect_num 9 -+#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ -+ -+/* RTC interrupt vectors */ -+#define RTC_OVF_vect_num 10 -+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -+#define RTC_COMP_vect_num 11 -+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 12 -+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 13 -+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_OVF_vect_num 14 -+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LUNF_vect_num 14 -+#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_ERR_vect_num 15 -+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_HUNF_vect_num 15 -+#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCA_vect_num 16 -+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPA_vect_num 16 -+#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCB_vect_num 17 -+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPB_vect_num 17 -+#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCC_vect_num 18 -+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPC_vect_num 18 -+#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCD_vect_num 19 -+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPD_vect_num 19 -+#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ -+ -+/* TCC1 interrupt vectors */ -+#define TCC1_OVF_vect_num 20 -+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -+#define TCC1_ERR_vect_num 21 -+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -+#define TCC1_CCA_vect_num 22 -+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -+#define TCC1_CCB_vect_num 23 -+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 24 -+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 25 -+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 26 -+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 27 -+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ -+ -+/* USARTC1 interrupt vectors */ -+#define USARTC1_RXC_vect_num 28 -+#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -+#define USARTC1_DRE_vect_num 29 -+#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -+#define USARTC1_TXC_vect_num 30 -+#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ -+ -+/* AES interrupt vectors */ -+#define AES_INT_vect_num 31 -+#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 32 -+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -+#define NVM_SPM_vect_num 33 -+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ -+ -+/* PORTB interrupt vectors */ -+#define PORTB_INT0_vect_num 34 -+#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -+#define PORTB_INT1_vect_num 35 -+#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ -+ -+/* ACB interrupt vectors */ -+#define ACB_AC0_vect_num 36 -+#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ -+#define ACB_AC1_vect_num 37 -+#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ -+#define ACB_ACW_vect_num 38 -+#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ -+ -+/* ADCB interrupt vectors */ -+#define ADCB_CH0_vect_num 39 -+#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ -+#define ADCB_CH1_vect_num 40 -+#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ -+#define ADCB_CH2_vect_num 41 -+#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ -+#define ADCB_CH3_vect_num 42 -+#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ -+ -+/* PORTE interrupt vectors */ -+#define PORTE_INT0_vect_num 43 -+#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -+#define PORTE_INT1_vect_num 44 -+#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ -+ -+/* TWIE interrupt vectors */ -+#define TWIE_TWIS_vect_num 45 -+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -+#define TWIE_TWIM_vect_num 46 -+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_OVF_vect_num 47 -+#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LUNF_vect_num 47 -+#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_ERR_vect_num 48 -+#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_HUNF_vect_num 48 -+#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCA_vect_num 49 -+#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPA_vect_num 49 -+#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCB_vect_num 50 -+#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPB_vect_num 50 -+#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCC_vect_num 51 -+#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPC_vect_num 51 -+#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCD_vect_num 52 -+#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPD_vect_num 52 -+#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ -+ -+/* TCE1 interrupt vectors */ -+#define TCE1_OVF_vect_num 53 -+#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ -+#define TCE1_ERR_vect_num 54 -+#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ -+#define TCE1_CCA_vect_num 55 -+#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ -+#define TCE1_CCB_vect_num 56 -+#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ -+ -+/* SPIE interrupt vectors */ -+#define SPIE_INT_vect_num 57 -+#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ -+ -+/* USARTE0 interrupt vectors */ -+#define USARTE0_RXC_vect_num 58 -+#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -+#define USARTE0_DRE_vect_num 59 -+#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -+#define USARTE0_TXC_vect_num 60 -+#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ -+ -+/* USARTE1 interrupt vectors */ -+#define USARTE1_RXC_vect_num 61 -+#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ -+#define USARTE1_DRE_vect_num 62 -+#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ -+#define USARTE1_TXC_vect_num 63 -+#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT0_vect_num 64 -+#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -+#define PORTD_INT1_vect_num 65 -+#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ -+ -+/* PORTA interrupt vectors */ -+#define PORTA_INT0_vect_num 66 -+#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -+#define PORTA_INT1_vect_num 67 -+#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ -+ -+/* ACA interrupt vectors */ -+#define ACA_AC0_vect_num 68 -+#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -+#define ACA_AC1_vect_num 69 -+#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -+#define ACA_ACW_vect_num 70 -+#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ -+ -+/* ADCA interrupt vectors */ -+#define ADCA_CH0_vect_num 71 -+#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -+#define ADCA_CH1_vect_num 72 -+#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -+#define ADCA_CH2_vect_num 73 -+#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -+#define ADCA_CH3_vect_num 74 -+#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_OVF_vect_num 77 -+#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LUNF_vect_num 77 -+#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_ERR_vect_num 78 -+#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_HUNF_vect_num 78 -+#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCA_vect_num 79 -+#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPA_vect_num 79 -+#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCB_vect_num 80 -+#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPB_vect_num 80 -+#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCC_vect_num 81 -+#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPC_vect_num 81 -+#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCD_vect_num 82 -+#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPD_vect_num 82 -+#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ -+ -+/* TCD1 interrupt vectors */ -+#define TCD1_OVF_vect_num 83 -+#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -+#define TCD1_ERR_vect_num 84 -+#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -+#define TCD1_CCA_vect_num 85 -+#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -+#define TCD1_CCB_vect_num 86 -+#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ -+ -+/* SPID interrupt vectors */ -+#define SPID_INT_vect_num 87 -+#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ -+ -+/* USARTD0 interrupt vectors */ -+#define USARTD0_RXC_vect_num 88 -+#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -+#define USARTD0_DRE_vect_num 89 -+#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -+#define USARTD0_TXC_vect_num 90 -+#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ -+ -+/* USARTD1 interrupt vectors */ -+#define USARTD1_RXC_vect_num 91 -+#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -+#define USARTD1_DRE_vect_num 92 -+#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -+#define USARTD1_TXC_vect_num 93 -+#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ -+ -+/* PORTF interrupt vectors */ -+#define PORTF_INT0_vect_num 104 -+#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -+#define PORTF_INT1_vect_num 105 -+#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_OVF_vect_num 108 -+#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LUNF_vect_num 108 -+#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_ERR_vect_num 109 -+#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_HUNF_vect_num 109 -+#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCA_vect_num 110 -+#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPA_vect_num 110 -+#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCB_vect_num 111 -+#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPB_vect_num 111 -+#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCC_vect_num 112 -+#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPC_vect_num 112 -+#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCD_vect_num 113 -+#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPD_vect_num 113 -+#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ -+ -+/* USARTF0 interrupt vectors */ -+#define USARTF0_RXC_vect_num 119 -+#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ -+#define USARTF0_DRE_vect_num 120 -+#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ -+#define USARTF0_TXC_vect_num 121 -+#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ -+ -+/* USB interrupt vectors */ -+#define USB_BUSEVENT_vect_num 125 -+#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -+#define USB_TRNCOMPL_vect_num 126 -+#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (127 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (139264) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (131072) -+#define APP_SECTION_PAGE_SIZE (512) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0x1E000) -+#define APPTABLE_SECTION_SIZE (8192) -+#define APPTABLE_SECTION_PAGE_SIZE (512) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x20000) -+#define BOOT_SECTION_SIZE (8192) -+#define BOOT_SECTION_PAGE_SIZE (512) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (16384) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (2048) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (8192) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (2048) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (6) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (512) -+#define USER_SIGNATURES_PAGE_SIZE (512) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (52) -+#define PROD_SIGNATURES_PAGE_SIZE (512) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 512 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 6 -+ -+/* Fuse Byte 0 */ -+#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -+#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -+#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -+#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -+#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -+#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -+#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -+#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -+#define FUSE0_DEFAULT (0xFF) -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x97 -+#define SIGNATURE_2 0x42 -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA128A3U_H_INCLUDED */ -+ -diff --git a/include/avr/iox128a4u.h b/include/avr/iox128a4u.h -new file mode 100644 -index 0000000..6f0280b ---- /dev/null -+++ b/include/avr/iox128a4u.h -@@ -0,0 +1,7240 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox128a4u.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA128A4U_H_INCLUDED -+#define _AVR_ATXMEGA128A4U_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -+#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -+#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -+#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -+#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -+#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -+#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -+#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -+#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -+#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -+#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -+#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -+#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -+#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -+#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -+#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -+#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -+#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -+#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -+#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -+#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -+#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -+#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+VPORT - Virtual Ports -+-------------------------------------------------------------------------- -+*/ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t USBCTRL; /* USB Control Register */ -+} CLK_t; -+ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t PRPB; /* Power Reduction Port B */ -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t PRPD; /* Power Reduction Port D */ -+ register8_t PRPE; /* Power Reduction Port E */ -+ register8_t PRPF; /* Power Reduction Port F */ -+} PR_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+/* USB Prescaler Division Factor */ -+typedef enum CLK_USBPSDIV_enum -+{ -+ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ -+ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ -+ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ -+ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ -+ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ -+ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -+} CLK_USBPSDIV_t; -+ -+/* USB Clock Source */ -+typedef enum CLK_USBSRC_enum -+{ -+ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ -+ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -+} CLK_USBSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control Register */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+/* 2 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC2MCREF_enum -+{ -+ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC2MCREF_t; -+ -+/* 32 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC32MCREF_enum -+{ -+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -+} OSC_RC32MCREF_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t JTAGUID; /* JTAG User ID */ -+ register8_t reserved_0x05; -+ register8_t MCUCR; /* MCU Control */ -+ register8_t ANAINIT; /* Analog Startup Delay */ -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t AWEXLOCK; /* AWEX Lock */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORTCFG - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t VPCTRLA; /* Virtual Port Control Register A */ -+ register8_t VPCTRLB; /* Virtual Port Control Register B */ -+ register8_t CLKEVOUT; /* Clock and Event Out Register */ -+ register8_t EBIOUT; /* EBI Output register */ -+ register8_t EVOUTSEL; /* Event Output Select */ -+} PORTCFG_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP02MAP_enum -+{ -+ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ -+ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ -+ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ -+ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ -+ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ -+ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ -+ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ -+ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ -+ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ -+ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ -+ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ -+ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ -+ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ -+ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ -+ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ -+ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -+} PORTCFG_VP02MAP_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP13MAP_enum -+{ -+ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ -+ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ -+ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ -+ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ -+ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ -+ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ -+ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ -+ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ -+ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ -+ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ -+ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ -+ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ -+ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ -+ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ -+ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ -+ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -+} PORTCFG_VP13MAP_t; -+ -+/* System Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ -+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ -+ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -+} PORTCFG_CLKOUT_t; -+ -+/* Peripheral Clock Output Select */ -+typedef enum PORTCFG_CLKOUTSEL_enum -+{ -+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -+} PORTCFG_CLKOUTSEL_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ -+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ -+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -+} PORTCFG_EVOUT_t; -+ -+/* Clock and Event Output Port */ -+typedef enum PORTCFG_CLKEVPIN_enum -+{ -+ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ -+ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -+} PORTCFG_CLKEVPIN_t; -+ -+/* EBI Address Output Port */ -+typedef enum PORTCFG_EBIADROUT_enum -+{ -+ PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ -+ PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ -+ PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ -+ PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ -+} PORTCFG_EBIADROUT_t; -+ -+/* EBI Chip Select Output Port */ -+typedef enum PORTCFG_EBICSOUT_enum -+{ -+ PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ -+} PORTCFG_EBICSOUT_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -+ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ -+ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ -+ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ -+ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AES - AES Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* AES Module */ -+typedef struct AES_struct -+{ -+ register8_t CTRL; /* AES Control Register */ -+ register8_t STATUS; /* AES Status Register */ -+ register8_t STATE; /* AES State Register */ -+ register8_t KEY; /* AES Key Register */ -+ register8_t INTCTRL; /* AES Interrupt Control Register */ -+} AES_t; -+ -+/* Interrupt level */ -+typedef enum AES_INTLVL_enum -+{ -+ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} AES_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ -+ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ -+ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ -+ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DMA - DMA Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* DMA Channel */ -+typedef struct DMA_CH_struct -+{ -+ register8_t CTRLA; /* Channel Control */ -+ register8_t CTRLB; /* Channel Control */ -+ register8_t ADDRCTRL; /* Address Control */ -+ register8_t TRIGSRC; /* Channel Trigger Source */ -+ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ -+ register8_t REPCNT; /* Channel Repeat Count */ -+ register8_t reserved_0x07; -+ register8_t SRCADDR0; /* Channel Source Address 0 */ -+ register8_t SRCADDR1; /* Channel Source Address 1 */ -+ register8_t SRCADDR2; /* Channel Source Address 2 */ -+ register8_t reserved_0x0B; -+ register8_t DESTADDR0; /* Channel Destination Address 0 */ -+ register8_t DESTADDR1; /* Channel Destination Address 1 */ -+ register8_t DESTADDR2; /* Channel Destination Address 2 */ -+ register8_t reserved_0x0F; -+} DMA_CH_t; -+ -+ -+/* DMA Controller */ -+typedef struct DMA_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t reserved_0x01; -+ register8_t reserved_0x02; -+ register8_t INTFLAGS; /* Transfer Interrupt Status */ -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x05; -+ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ DMA_CH_t CH0; /* DMA Channel 0 */ -+ DMA_CH_t CH1; /* DMA Channel 1 */ -+ DMA_CH_t CH2; /* DMA Channel 2 */ -+ DMA_CH_t CH3; /* DMA Channel 3 */ -+} DMA_t; -+ -+/* Burst mode */ -+typedef enum DMA_CH_BURSTLEN_enum -+{ -+ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ -+ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ -+ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ -+ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -+} DMA_CH_BURSTLEN_t; -+ -+/* Source address reload mode */ -+typedef enum DMA_CH_SRCRELOAD_enum -+{ -+ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ -+ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ -+ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ -+ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -+} DMA_CH_SRCRELOAD_t; -+ -+/* Source addressing mode */ -+typedef enum DMA_CH_SRCDIR_enum -+{ -+ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ -+ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ -+ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -+} DMA_CH_SRCDIR_t; -+ -+/* Destination adress reload mode */ -+typedef enum DMA_CH_DESTRELOAD_enum -+{ -+ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ -+ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ -+ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ -+ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -+} DMA_CH_DESTRELOAD_t; -+ -+/* Destination adressing mode */ -+typedef enum DMA_CH_DESTDIR_enum -+{ -+ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ -+ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ -+ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -+} DMA_CH_DESTDIR_t; -+ -+/* Transfer trigger source */ -+typedef enum DMA_CH_TRIGSRC_enum -+{ -+ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ -+ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ -+ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ -+ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ -+ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ -+ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ -+ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ -+ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ -+ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ -+ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ -+ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ -+ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ -+ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ -+ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ -+ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ -+ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ -+ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ -+ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ -+ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ -+ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ -+ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ -+ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ -+ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ -+ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ -+ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ -+ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ -+ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ -+ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ -+ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ -+ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ -+ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ -+ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ -+ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ -+ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ -+ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -+} DMA_CH_TRIGSRC_t; -+ -+/* Double buffering mode */ -+typedef enum DMA_DBUFMODE_enum -+{ -+ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ -+ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ -+ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ -+ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -+} DMA_DBUFMODE_t; -+ -+/* Priority mode */ -+typedef enum DMA_PRIMODE_enum -+{ -+ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ -+ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ -+ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ -+ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -+} DMA_PRIMODE_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_ERRINTLVL_enum -+{ -+ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ -+ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ -+ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -+} DMA_CH_ERRINTLVL_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_TRNINTLVL_enum -+{ -+ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ -+ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -+} DMA_CH_TRNINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ -+ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ -+ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ -+ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t CH4CTRL; /* Channel 4 Control Register */ -+ register8_t CH5CTRL; /* Channel 5 Control Register */ -+ register8_t CH6CTRL; /* Channel 6 Control Register */ -+ register8_t CH7CTRL; /* Channel 7 Control Register */ -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+} EVSYS_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ -+ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ -+ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ -+ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ -+ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ -+ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ -+ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ -+ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ -+ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ -+ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ -+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ -+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ -+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ -+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ -+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ -+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ -+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ -+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ -+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ -+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ -+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ -+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ -+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ -+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ -+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ -+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ -+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ -+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ -+ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ -+ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ -+ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ -+ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ -+ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ -+ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ -+ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ -+ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ -+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ -+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ -+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ -+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ -+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ -+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ -+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ -+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ -+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ -+ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ -+ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ -+ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ -+ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ -+ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ -+ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ -+ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ -+ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ -+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ -+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ -+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ -+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -+ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ -+ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ -+ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ -+ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ -+ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ -+ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ -+ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ -+ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -+ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ -+ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ -+ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ -+ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -+} EVSYS_CHMUX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ -+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ -+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ -+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ -+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} NVM_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t reserved_0x07; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ _WORDREGISTER(CH1RES); /* Channel 1 Result */ -+ _WORDREGISTER(CH2RES); /* Channel 2 Result */ -+ _WORDREGISTER(CH3RES); /* Channel 3 Result */ -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+ ADC_CH_t CH1; /* ADC Channel 1 */ -+ ADC_CH_t CH2; /* ADC Channel 2 */ -+ ADC_CH_t CH3; /* ADC Channel 3 */ -+} ADC_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -+ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+ ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 3) */ -+ ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Groud (Input Mode = 3) */ -+ ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Groud (Input Mode = 4) */ -+ ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 4) */ -+} ADC_CH_MUXNEG_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Current Limitation Mode */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ -+} ADC_CURRLIMIT_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Channel sweep selection */ -+typedef enum ADC_SWEEP_enum -+{ -+ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ -+ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ -+ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ -+ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -+} ADC_SWEEP_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ -+ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ -+ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ -+ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ -+ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ -+ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ -+ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ -+ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -+ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ -+ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ -+ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ -+ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* DMA request selection */ -+typedef enum ADC_DMASEL_enum -+{ -+ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ -+ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ -+ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ -+ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -+} ADC_DMASEL_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DAC - Digital/Analog Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Digital-to-Analog Converter */ -+typedef struct DAC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t EVCTRL; /* Event Input Control */ -+ register8_t reserved_0x04; -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0GAINCAL; /* Gain Calibration */ -+ register8_t CH0OFFSETCAL; /* Offset Calibration */ -+ register8_t CH1GAINCAL; /* Gain Calibration */ -+ register8_t CH1OFFSETCAL; /* Offset Calibration */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ -+ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -+} DAC_t; -+ -+/* Output channel selection */ -+typedef enum DAC_CHSEL_enum -+{ -+ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ -+ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ -+ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -+} DAC_CHSEL_t; -+ -+/* Reference voltage selection */ -+typedef enum DAC_REFSEL_enum -+{ -+ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ -+ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ -+ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ -+ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -+} DAC_REFSEL_t; -+ -+/* Event channel selection */ -+typedef enum DAC_EVSEL_enum -+{ -+ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ -+ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ -+ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ -+ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ -+ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ -+ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ -+ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ -+ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -+} DAC_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC - Real-Time Counter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Real-Time Counter */ -+typedef struct RTC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary register */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ _WORDREGISTER(CNT); /* Count Register */ -+ _WORDREGISTER(PER); /* Period Register */ -+ _WORDREGISTER(COMP); /* Compare Register */ -+} RTC_t; -+ -+/* Prescaler Factor */ -+typedef enum RTC_PRESCALER_enum -+{ -+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ -+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ -+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ -+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ -+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ -+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ -+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ -+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -+} RTC_PRESCALER_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC_COMPINTLVL_enum -+{ -+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC_OVFINTLVL_enum -+{ -+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+} TWI_t; -+ -+/* SDA Hold Time */ -+typedef enum TWI_SDAHOLD_enum -+{ -+ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ -+ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ -+ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ -+ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -+} TWI_SDAHOLD_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USB - USB -+-------------------------------------------------------------------------- -+*/ -+ -+/* USB Endpoint */ -+typedef struct USB_EP_struct -+{ -+ register8_t STATUS; /* Endpoint Status */ -+ register8_t CTRL; /* Endpoint Control */ -+ _WORDREGISTER(CNT); /* USB Endpoint Counter */ -+ _WORDREGISTER(DATAPTR); /* Data Pointer */ -+ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -+} USB_EP_t; -+ -+ -+/* Universal Serial Bus */ -+typedef struct USB_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t FIFOWP; /* FIFO Write Pointer Register */ -+ register8_t FIFORP; /* FIFO Read Pointer Register */ -+ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ -+ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ -+ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ -+ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t reserved_0x20; -+ register8_t reserved_0x21; -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t CAL0; /* Calibration Byte 0 */ -+ register8_t CAL1; /* Calibration Byte 1 */ -+} USB_t; -+ -+ -+/* USB Endpoint Table */ -+typedef struct USB_EP_TABLE_struct -+{ -+ USB_EP_t EP0OUT; /* Endpoint 0 */ -+ USB_EP_t EP0IN; /* Endpoint 0 */ -+ USB_EP_t EP1OUT; /* Endpoint 1 */ -+ USB_EP_t EP1IN; /* Endpoint 1 */ -+ USB_EP_t EP2OUT; /* Endpoint 2 */ -+ USB_EP_t EP2IN; /* Endpoint 2 */ -+ USB_EP_t EP3OUT; /* Endpoint 3 */ -+ USB_EP_t EP3IN; /* Endpoint 3 */ -+ USB_EP_t EP4OUT; /* Endpoint 4 */ -+ USB_EP_t EP4IN; /* Endpoint 4 */ -+ USB_EP_t EP5OUT; /* Endpoint 5 */ -+ USB_EP_t EP5IN; /* Endpoint 5 */ -+ USB_EP_t EP6OUT; /* Endpoint 6 */ -+ USB_EP_t EP6IN; /* Endpoint 6 */ -+ USB_EP_t EP7OUT; /* Endpoint 7 */ -+ USB_EP_t EP7IN; /* Endpoint 7 */ -+ USB_EP_t EP8OUT; /* Endpoint 8 */ -+ USB_EP_t EP8IN; /* Endpoint 8 */ -+ USB_EP_t EP9OUT; /* Endpoint 9 */ -+ USB_EP_t EP9IN; /* Endpoint 9 */ -+ USB_EP_t EP10OUT; /* Endpoint 10 */ -+ USB_EP_t EP10IN; /* Endpoint 10 */ -+ USB_EP_t EP11OUT; /* Endpoint 11 */ -+ USB_EP_t EP11IN; /* Endpoint 11 */ -+ USB_EP_t EP12OUT; /* Endpoint 12 */ -+ USB_EP_t EP12IN; /* Endpoint 12 */ -+ USB_EP_t EP13OUT; /* Endpoint 13 */ -+ USB_EP_t EP13IN; /* Endpoint 13 */ -+ USB_EP_t EP14OUT; /* Endpoint 14 */ -+ USB_EP_t EP14IN; /* Endpoint 14 */ -+ USB_EP_t EP15OUT; /* Endpoint 15 */ -+ USB_EP_t EP15IN; /* Endpoint 15 */ -+ register8_t reserved_0x100; -+ register8_t reserved_0x101; -+ register8_t reserved_0x102; -+ register8_t reserved_0x103; -+ register8_t reserved_0x104; -+ register8_t reserved_0x105; -+ register8_t reserved_0x106; -+ register8_t reserved_0x107; -+ register8_t reserved_0x108; -+ register8_t reserved_0x109; -+ register8_t reserved_0x10A; -+ register8_t reserved_0x10B; -+ register8_t reserved_0x10C; -+ register8_t reserved_0x10D; -+ register8_t reserved_0x10E; -+ register8_t reserved_0x10F; -+ register8_t FRAMENUML; /* Frame Number Low Byte */ -+ register8_t FRAMENUMH; /* Frame Number High Byte */ -+} USB_EP_TABLE_t; -+ -+/* Interrupt level */ -+typedef enum USB_INTLVL_enum -+{ -+ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} USB_INTLVL_t; -+ -+/* USB Endpoint Type */ -+typedef enum USB_EP_TYPE_enum -+{ -+ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ -+ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ -+ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ -+ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -+} USB_EP_TYPE_t; -+ -+/* USB Endpoint Buffersize */ -+typedef enum USB_EP_BUFSIZE_enum -+{ -+ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ -+ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ -+ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ -+ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ -+ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ -+ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ -+ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ -+ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -+} USB_EP_BUFSIZE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - I/O Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INT0MASK; /* Port Interrupt 0 Mask */ -+ register8_t INT1MASK; /* Port Interrupt 1 Mask */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t REMAP; /* I/O Port Pin Remap Register */ -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Port Interrupt 0 Level */ -+typedef enum PORT_INT0LVL_enum -+{ -+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INT0LVL_t; -+ -+/* Port Interrupt 1 Level */ -+typedef enum PORT_INT1LVL_enum -+{ -+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ -+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ -+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -+} PORT_INT1LVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 0 */ -+typedef struct TC0_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC0_t; -+ -+ -+/* 16-bit Timer/Counter 1 */ -+typedef struct TC1_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+} TC1_t; -+ -+/* Clock Selection */ -+typedef enum TC_CLKSEL_enum -+{ -+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC_CLKSEL_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC_WGMODE_enum -+{ -+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC_WGMODE_t; -+ -+/* Byte Mode */ -+typedef enum TC_BYTEM_enum -+{ -+ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ -+ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -+} TC_BYTEM_t; -+ -+/* Event Action */ -+typedef enum TC_EVACT_enum -+{ -+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ -+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ -+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ -+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ -+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ -+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC_EVSEL_enum -+{ -+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC_EVSEL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC_ERRINTLVL_enum -+{ -+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC_OVFINTLVL_enum -+{ -+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_OVFINTLVL_t; -+ -+/* Compare or Capture D Interrupt Level */ -+typedef enum TC_CCDINTLVL_enum -+{ -+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC_CCDINTLVL_t; -+ -+/* Compare or Capture C Interrupt Level */ -+typedef enum TC_CCCINTLVL_enum -+{ -+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC_CCCINTLVL_t; -+ -+/* Compare or Capture B Interrupt Level */ -+typedef enum TC_CCBINTLVL_enum -+{ -+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_CCBINTLVL_t; -+ -+/* Compare or Capture A Interrupt Level */ -+typedef enum TC_CCAINTLVL_enum -+{ -+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_CCAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC_CMD_enum -+{ -+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC2 - 16-bit Timer/Counter type 2 -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter type 2 */ -+typedef struct TC2_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t reserved_0x03; -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t reserved_0x08; -+ register8_t CTRLF; /* Control Register F */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t LCNT; /* Low Byte Count */ -+ register8_t HCNT; /* High Byte Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t LPER; /* Low Byte Period */ -+ register8_t HPER; /* High Byte Period */ -+ register8_t LCMPA; /* Low Byte Compare A */ -+ register8_t HCMPA; /* High Byte Compare A */ -+ register8_t LCMPB; /* Low Byte Compare B */ -+ register8_t HCMPB; /* High Byte Compare B */ -+ register8_t LCMPC; /* Low Byte Compare C */ -+ register8_t HCMPC; /* High Byte Compare C */ -+ register8_t LCMPD; /* Low Byte Compare D */ -+ register8_t HCMPD; /* High Byte Compare D */ -+} TC2_t; -+ -+/* Clock Selection */ -+typedef enum TC2_CLKSEL_enum -+{ -+ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC2_CLKSEL_t; -+ -+/* Byte Mode */ -+typedef enum TC2_BYTEM_enum -+{ -+ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ -+ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -+} TC2_BYTEM_t; -+ -+/* High Byte Underflow Interrupt Level */ -+typedef enum TC2_HUNFINTLVL_enum -+{ -+ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_HUNFINTLVL_t; -+ -+/* Low Byte Underflow Interrupt Level */ -+typedef enum TC2_LUNFINTLVL_enum -+{ -+ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LUNFINTLVL_t; -+ -+/* Low Byte Compare D Interrupt Level */ -+typedef enum TC2_LCMPDINTLVL_enum -+{ -+ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC2_LCMPDINTLVL_t; -+ -+/* Low Byte Compare C Interrupt Level */ -+typedef enum TC2_LCMPCINTLVL_enum -+{ -+ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC2_LCMPCINTLVL_t; -+ -+/* Low Byte Compare B Interrupt Level */ -+typedef enum TC2_LCMPBINTLVL_enum -+{ -+ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_LCMPBINTLVL_t; -+ -+/* Low Byte Compare A Interrupt Level */ -+typedef enum TC2_LCMPAINTLVL_enum -+{ -+ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LCMPAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMD_enum -+{ -+ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC2_CMD_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMDEN_enum -+{ -+ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ -+ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ -+ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -+} TC2_CMDEN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AWEX - Timer/Counter Advanced Waveform Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Advanced Waveform Extension */ -+typedef struct AWEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t FDEMASK; /* Fault Detection Event Mask */ -+ register8_t FDCTRL; /* Fault Detection Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t STATUSSET; /* Status Set Register */ -+ register8_t DTBOTH; /* Dead Time Both Sides */ -+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ -+ register8_t DTLS; /* Dead Time Low Side */ -+ register8_t DTHS; /* Dead Time High Side */ -+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ -+ register8_t DTHSBUF; /* Dead Time High Side Buffer */ -+ register8_t OUTOVEN; /* Output Override Enable */ -+} AWEX_t; -+ -+/* Fault Detect Action */ -+typedef enum AWEX_FDACT_enum -+{ -+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ -+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -+} AWEX_FDACT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+HIRES - Timer/Counter High-Resolution Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register */ -+} HIRES_t; -+ -+/* High Resolution Enable */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ -+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ -+ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ -+ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ -+ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -+} IRDA_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t reserved_0x00; -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+} NVM_FUSES_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* Timer Oscillator pin location */ -+typedef enum TOSCSEL_enum -+{ -+ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ -+ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -+} TOSCSEL_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -+} BOD_t; -+ -+/* BOD operation */ -+typedef enum BODACT_enum -+{ -+ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BODACT_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WDP_enum -+{ -+ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ -+ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ -+ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ -+ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ -+ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ -+ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ -+ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ -+ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ -+ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ -+ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ -+ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -+} WDP_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LOCKBIT - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ -+ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t USBCAL0; /* USB Calibration Byte 0 */ -+ register8_t USBCAL1; /* USB Calibration Byte 1 */ -+ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ -+ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ -+ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ -+ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ -+ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ -+ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ -+ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ -+ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ -+ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ -+ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+ register8_t reserved_0x40; -+ register8_t reserved_0x41; -+ register8_t reserved_0x42; -+ register8_t reserved_0x43; -+ register8_t reserved_0x44; -+ register8_t reserved_0x45; -+ register8_t reserved_0x46; -+ register8_t reserved_0x47; -+} NVM_PROD_SIGNATURES_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define AES (*(AES_t *) 0x00C0) /* AES Module */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -+#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -+#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -+#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -+#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -+#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ -+#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ -+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -+#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -+#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ -+#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -+#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -+#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -+#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -+#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -+#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -+#define GPIO_GPIORA _SFR_MEM8(0x000A) -+#define GPIO_GPIORB _SFR_MEM8(0x000B) -+#define GPIO_GPIORC _SFR_MEM8(0x000C) -+#define GPIO_GPIORD _SFR_MEM8(0x000D) -+#define GPIO_GPIORE _SFR_MEM8(0x000E) -+#define GPIO_GPIORF _SFR_MEM8(0x000F) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+#define GPIO_GPIO4 _SFR_MEM8(0x0004) -+#define GPIO_GPIO5 _SFR_MEM8(0x0005) -+#define GPIO_GPIO6 _SFR_MEM8(0x0006) -+#define GPIO_GPIO7 _SFR_MEM8(0x0007) -+#define GPIO_GPIO8 _SFR_MEM8(0x0008) -+#define GPIO_GPIO9 _SFR_MEM8(0x0009) -+#define GPIO_GPIOA _SFR_MEM8(0x000A) -+#define GPIO_GPIOB _SFR_MEM8(0x000B) -+#define GPIO_GPIOC _SFR_MEM8(0x000C) -+#define GPIO_GPIOD _SFR_MEM8(0x000D) -+#define GPIO_GPIOE _SFR_MEM8(0x000E) -+#define GPIO_GPIOF _SFR_MEM8(0x000F) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -+#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -+#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -+#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -+#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -+#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -+#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) -+#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) -+#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -+#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) -+#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) -+#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+#define CLK_USBCTRL _SFR_MEM8(0x0044) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* DFLL - DFLL */ -+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -+#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -+#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPB _SFR_MEM8(0x0072) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPD _SFR_MEM8(0x0074) -+#define PR_PRPE _SFR_MEM8(0x0075) -+#define PR_PRPF _SFR_MEM8(0x0076) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_JTAGUID _SFR_MEM8(0x0094) -+#define MCU_MCUCR _SFR_MEM8(0x0096) -+#define MCU_ANAINIT _SFR_MEM8(0x0097) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_AWEXLOCK _SFR_MEM8(0x0099) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) -+#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) -+ -+/* AES - AES Module */ -+#define AES_CTRL _SFR_MEM8(0x00C0) -+#define AES_STATUS _SFR_MEM8(0x00C1) -+#define AES_STATE _SFR_MEM8(0x00C2) -+#define AES_KEY _SFR_MEM8(0x00C3) -+#define AES_INTCTRL _SFR_MEM8(0x00C4) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* DMA - DMA Controller */ -+#define DMA_CTRL _SFR_MEM8(0x0100) -+#define DMA_INTFLAGS _SFR_MEM8(0x0103) -+#define DMA_STATUS _SFR_MEM8(0x0104) -+#define DMA_TEMP _SFR_MEM16(0x0106) -+#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -+#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -+#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -+#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -+#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -+#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -+#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -+#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -+#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -+#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -+#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -+#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -+#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -+#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -+#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -+#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -+#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -+#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -+#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -+#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -+#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -+#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -+#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -+#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -+#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -+#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -+#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -+#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -+#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -+#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -+#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -+#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -+#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -+#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -+#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -+#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -+#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -+#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -+#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -+#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -+#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -+#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -+#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -+#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -+#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -+#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -+#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -+#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -+#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -+#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -+#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -+#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -+#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -+#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCA_CTRLA _SFR_MEM8(0x0200) -+#define ADCA_CTRLB _SFR_MEM8(0x0201) -+#define ADCA_REFCTRL _SFR_MEM8(0x0202) -+#define ADCA_EVCTRL _SFR_MEM8(0x0203) -+#define ADCA_PRESCALER _SFR_MEM8(0x0204) -+#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -+#define ADCA_TEMP _SFR_MEM8(0x0207) -+#define ADCA_CAL _SFR_MEM16(0x020C) -+#define ADCA_CH0RES _SFR_MEM16(0x0210) -+#define ADCA_CH1RES _SFR_MEM16(0x0212) -+#define ADCA_CH2RES _SFR_MEM16(0x0214) -+#define ADCA_CH3RES _SFR_MEM16(0x0216) -+#define ADCA_CMP _SFR_MEM16(0x0218) -+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -+#define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -+#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -+#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -+#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -+#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -+#define ADCA_CH1_RES _SFR_MEM16(0x022C) -+#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) -+#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -+#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -+#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -+#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -+#define ADCA_CH2_RES _SFR_MEM16(0x0234) -+#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) -+#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -+#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -+#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -+#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -+#define ADCA_CH3_RES _SFR_MEM16(0x023C) -+#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) -+ -+/* DAC - Digital-to-Analog Converter */ -+#define DACB_CTRLA _SFR_MEM8(0x0320) -+#define DACB_CTRLB _SFR_MEM8(0x0321) -+#define DACB_CTRLC _SFR_MEM8(0x0322) -+#define DACB_EVCTRL _SFR_MEM8(0x0323) -+#define DACB_STATUS _SFR_MEM8(0x0325) -+#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) -+#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) -+#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) -+#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) -+#define DACB_CH0DATA _SFR_MEM16(0x0338) -+#define DACB_CH1DATA _SFR_MEM16(0x033A) -+ -+/* AC - Analog Comparator */ -+#define ACA_AC0CTRL _SFR_MEM8(0x0380) -+#define ACA_AC1CTRL _SFR_MEM8(0x0381) -+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -+#define ACA_CTRLA _SFR_MEM8(0x0384) -+#define ACA_CTRLB _SFR_MEM8(0x0385) -+#define ACA_WINCTRL _SFR_MEM8(0x0386) -+#define ACA_STATUS _SFR_MEM8(0x0387) -+ -+/* RTC - Real-Time Counter */ -+#define RTC_CTRL _SFR_MEM8(0x0400) -+#define RTC_STATUS _SFR_MEM8(0x0401) -+#define RTC_INTCTRL _SFR_MEM8(0x0402) -+#define RTC_INTFLAGS _SFR_MEM8(0x0403) -+#define RTC_TEMP _SFR_MEM8(0x0404) -+#define RTC_CNT _SFR_MEM16(0x0408) -+#define RTC_PER _SFR_MEM16(0x040A) -+#define RTC_COMP _SFR_MEM16(0x040C) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIE_CTRL _SFR_MEM8(0x04A0) -+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -+ -+/* USB - Universal Serial Bus */ -+#define USB_CTRLA _SFR_MEM8(0x04C0) -+#define USB_CTRLB _SFR_MEM8(0x04C1) -+#define USB_STATUS _SFR_MEM8(0x04C2) -+#define USB_ADDR _SFR_MEM8(0x04C3) -+#define USB_FIFOWP _SFR_MEM8(0x04C4) -+#define USB_FIFORP _SFR_MEM8(0x04C5) -+#define USB_EPPTR _SFR_MEM16(0x04C6) -+#define USB_INTCTRLA _SFR_MEM8(0x04C8) -+#define USB_INTCTRLB _SFR_MEM8(0x04C9) -+#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -+#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -+#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -+#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -+#define USB_CAL0 _SFR_MEM8(0x04FA) -+#define USB_CAL1 _SFR_MEM8(0x04FB) -+ -+/* PORT - I/O Ports */ -+#define PORTA_DIR _SFR_MEM8(0x0600) -+#define PORTA_DIRSET _SFR_MEM8(0x0601) -+#define PORTA_DIRCLR _SFR_MEM8(0x0602) -+#define PORTA_DIRTGL _SFR_MEM8(0x0603) -+#define PORTA_OUT _SFR_MEM8(0x0604) -+#define PORTA_OUTSET _SFR_MEM8(0x0605) -+#define PORTA_OUTCLR _SFR_MEM8(0x0606) -+#define PORTA_OUTTGL _SFR_MEM8(0x0607) -+#define PORTA_IN _SFR_MEM8(0x0608) -+#define PORTA_INTCTRL _SFR_MEM8(0x0609) -+#define PORTA_INT0MASK _SFR_MEM8(0x060A) -+#define PORTA_INT1MASK _SFR_MEM8(0x060B) -+#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_REMAP _SFR_MEM8(0x060E) -+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -+ -+/* PORT - I/O Ports */ -+#define PORTB_DIR _SFR_MEM8(0x0620) -+#define PORTB_DIRSET _SFR_MEM8(0x0621) -+#define PORTB_DIRCLR _SFR_MEM8(0x0622) -+#define PORTB_DIRTGL _SFR_MEM8(0x0623) -+#define PORTB_OUT _SFR_MEM8(0x0624) -+#define PORTB_OUTSET _SFR_MEM8(0x0625) -+#define PORTB_OUTCLR _SFR_MEM8(0x0626) -+#define PORTB_OUTTGL _SFR_MEM8(0x0627) -+#define PORTB_IN _SFR_MEM8(0x0628) -+#define PORTB_INTCTRL _SFR_MEM8(0x0629) -+#define PORTB_INT0MASK _SFR_MEM8(0x062A) -+#define PORTB_INT1MASK _SFR_MEM8(0x062B) -+#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -+#define PORTB_REMAP _SFR_MEM8(0x062E) -+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INT0MASK _SFR_MEM8(0x064A) -+#define PORTC_INT1MASK _SFR_MEM8(0x064B) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INT0MASK _SFR_MEM8(0x066A) -+#define PORTD_INT1MASK _SFR_MEM8(0x066B) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTE_DIR _SFR_MEM8(0x0680) -+#define PORTE_DIRSET _SFR_MEM8(0x0681) -+#define PORTE_DIRCLR _SFR_MEM8(0x0682) -+#define PORTE_DIRTGL _SFR_MEM8(0x0683) -+#define PORTE_OUT _SFR_MEM8(0x0684) -+#define PORTE_OUTSET _SFR_MEM8(0x0685) -+#define PORTE_OUTCLR _SFR_MEM8(0x0686) -+#define PORTE_OUTTGL _SFR_MEM8(0x0687) -+#define PORTE_IN _SFR_MEM8(0x0688) -+#define PORTE_INTCTRL _SFR_MEM8(0x0689) -+#define PORTE_INT0MASK _SFR_MEM8(0x068A) -+#define PORTE_INT1MASK _SFR_MEM8(0x068B) -+#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -+#define PORTE_REMAP _SFR_MEM8(0x068E) -+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -+#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCC0_CTRLA _SFR_MEM8(0x0800) -+#define TCC0_CTRLB _SFR_MEM8(0x0801) -+#define TCC0_CTRLC _SFR_MEM8(0x0802) -+#define TCC0_CTRLD _SFR_MEM8(0x0803) -+#define TCC0_CTRLE _SFR_MEM8(0x0804) -+#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -+#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -+#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -+#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC0_TEMP _SFR_MEM8(0x080F) -+#define TCC0_CNT _SFR_MEM16(0x0820) -+#define TCC0_PER _SFR_MEM16(0x0826) -+#define TCC0_CCA _SFR_MEM16(0x0828) -+#define TCC0_CCB _SFR_MEM16(0x082A) -+#define TCC0_CCC _SFR_MEM16(0x082C) -+#define TCC0_CCD _SFR_MEM16(0x082E) -+#define TCC0_PERBUF _SFR_MEM16(0x0836) -+#define TCC0_CCABUF _SFR_MEM16(0x0838) -+#define TCC0_CCBBUF _SFR_MEM16(0x083A) -+#define TCC0_CCCBUF _SFR_MEM16(0x083C) -+#define TCC0_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCC2_CTRLA _SFR_MEM8(0x0800) -+#define TCC2_CTRLB _SFR_MEM8(0x0801) -+#define TCC2_CTRLC _SFR_MEM8(0x0802) -+#define TCC2_CTRLE _SFR_MEM8(0x0804) -+#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC2_CTRLF _SFR_MEM8(0x0809) -+#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC2_LCNT _SFR_MEM8(0x0820) -+#define TCC2_HCNT _SFR_MEM8(0x0821) -+#define TCC2_LPER _SFR_MEM8(0x0826) -+#define TCC2_HPER _SFR_MEM8(0x0827) -+#define TCC2_LCMPA _SFR_MEM8(0x0828) -+#define TCC2_HCMPA _SFR_MEM8(0x0829) -+#define TCC2_LCMPB _SFR_MEM8(0x082A) -+#define TCC2_HCMPB _SFR_MEM8(0x082B) -+#define TCC2_LCMPC _SFR_MEM8(0x082C) -+#define TCC2_HCMPC _SFR_MEM8(0x082D) -+#define TCC2_LCMPD _SFR_MEM8(0x082E) -+#define TCC2_HCMPD _SFR_MEM8(0x082F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCC1_CTRLA _SFR_MEM8(0x0840) -+#define TCC1_CTRLB _SFR_MEM8(0x0841) -+#define TCC1_CTRLC _SFR_MEM8(0x0842) -+#define TCC1_CTRLD _SFR_MEM8(0x0843) -+#define TCC1_CTRLE _SFR_MEM8(0x0844) -+#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -+#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -+#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -+#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC1_TEMP _SFR_MEM8(0x084F) -+#define TCC1_CNT _SFR_MEM16(0x0860) -+#define TCC1_PER _SFR_MEM16(0x0866) -+#define TCC1_CCA _SFR_MEM16(0x0868) -+#define TCC1_CCB _SFR_MEM16(0x086A) -+#define TCC1_PERBUF _SFR_MEM16(0x0876) -+#define TCC1_CCABUF _SFR_MEM16(0x0878) -+#define TCC1_CCBBUF _SFR_MEM16(0x087A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXC_CTRL _SFR_MEM8(0x0880) -+#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -+#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -+#define AWEXC_STATUS _SFR_MEM8(0x0884) -+#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -+#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -+#define AWEXC_DTLS _SFR_MEM8(0x0888) -+#define AWEXC_DTHS _SFR_MEM8(0x0889) -+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x0890) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08A0) -+#define USARTC0_STATUS _SFR_MEM8(0x08A1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -+#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -+#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC1_DATA _SFR_MEM8(0x08B0) -+#define USARTC1_STATUS _SFR_MEM8(0x08B1) -+#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -+#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -+#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -+#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -+#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIC_CTRL _SFR_MEM8(0x08C0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -+#define SPIC_STATUS _SFR_MEM8(0x08C2) -+#define SPIC_DATA _SFR_MEM8(0x08C3) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCD0_CTRLA _SFR_MEM8(0x0900) -+#define TCD0_CTRLB _SFR_MEM8(0x0901) -+#define TCD0_CTRLC _SFR_MEM8(0x0902) -+#define TCD0_CTRLD _SFR_MEM8(0x0903) -+#define TCD0_CTRLE _SFR_MEM8(0x0904) -+#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -+#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -+#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -+#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -+#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD0_TEMP _SFR_MEM8(0x090F) -+#define TCD0_CNT _SFR_MEM16(0x0920) -+#define TCD0_PER _SFR_MEM16(0x0926) -+#define TCD0_CCA _SFR_MEM16(0x0928) -+#define TCD0_CCB _SFR_MEM16(0x092A) -+#define TCD0_CCC _SFR_MEM16(0x092C) -+#define TCD0_CCD _SFR_MEM16(0x092E) -+#define TCD0_PERBUF _SFR_MEM16(0x0936) -+#define TCD0_CCABUF _SFR_MEM16(0x0938) -+#define TCD0_CCBBUF _SFR_MEM16(0x093A) -+#define TCD0_CCCBUF _SFR_MEM16(0x093C) -+#define TCD0_CCDBUF _SFR_MEM16(0x093E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCD2_CTRLA _SFR_MEM8(0x0900) -+#define TCD2_CTRLB _SFR_MEM8(0x0901) -+#define TCD2_CTRLC _SFR_MEM8(0x0902) -+#define TCD2_CTRLE _SFR_MEM8(0x0904) -+#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD2_CTRLF _SFR_MEM8(0x0909) -+#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD2_LCNT _SFR_MEM8(0x0920) -+#define TCD2_HCNT _SFR_MEM8(0x0921) -+#define TCD2_LPER _SFR_MEM8(0x0926) -+#define TCD2_HPER _SFR_MEM8(0x0927) -+#define TCD2_LCMPA _SFR_MEM8(0x0928) -+#define TCD2_HCMPA _SFR_MEM8(0x0929) -+#define TCD2_LCMPB _SFR_MEM8(0x092A) -+#define TCD2_HCMPB _SFR_MEM8(0x092B) -+#define TCD2_LCMPC _SFR_MEM8(0x092C) -+#define TCD2_HCMPC _SFR_MEM8(0x092D) -+#define TCD2_LCMPD _SFR_MEM8(0x092E) -+#define TCD2_HCMPD _SFR_MEM8(0x092F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCD1_CTRLA _SFR_MEM8(0x0940) -+#define TCD1_CTRLB _SFR_MEM8(0x0941) -+#define TCD1_CTRLC _SFR_MEM8(0x0942) -+#define TCD1_CTRLD _SFR_MEM8(0x0943) -+#define TCD1_CTRLE _SFR_MEM8(0x0944) -+#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -+#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -+#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -+#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -+#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -+#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -+#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -+#define TCD1_TEMP _SFR_MEM8(0x094F) -+#define TCD1_CNT _SFR_MEM16(0x0960) -+#define TCD1_PER _SFR_MEM16(0x0966) -+#define TCD1_CCA _SFR_MEM16(0x0968) -+#define TCD1_CCB _SFR_MEM16(0x096A) -+#define TCD1_PERBUF _SFR_MEM16(0x0976) -+#define TCD1_CCABUF _SFR_MEM16(0x0978) -+#define TCD1_CCBBUF _SFR_MEM16(0x097A) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESD_CTRLA _SFR_MEM8(0x0990) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD0_DATA _SFR_MEM8(0x09A0) -+#define USARTD0_STATUS _SFR_MEM8(0x09A1) -+#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -+#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -+#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD1_DATA _SFR_MEM8(0x09B0) -+#define USARTD1_STATUS _SFR_MEM8(0x09B1) -+#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -+#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -+#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -+#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -+#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPID_CTRL _SFR_MEM8(0x09C0) -+#define SPID_INTCTRL _SFR_MEM8(0x09C1) -+#define SPID_STATUS _SFR_MEM8(0x09C2) -+#define SPID_DATA _SFR_MEM8(0x09C3) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCE0_CTRLA _SFR_MEM8(0x0A00) -+#define TCE0_CTRLB _SFR_MEM8(0x0A01) -+#define TCE0_CTRLC _SFR_MEM8(0x0A02) -+#define TCE0_CTRLD _SFR_MEM8(0x0A03) -+#define TCE0_CTRLE _SFR_MEM8(0x0A04) -+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE0_TEMP _SFR_MEM8(0x0A0F) -+#define TCE0_CNT _SFR_MEM16(0x0A20) -+#define TCE0_PER _SFR_MEM16(0x0A26) -+#define TCE0_CCA _SFR_MEM16(0x0A28) -+#define TCE0_CCB _SFR_MEM16(0x0A2A) -+#define TCE0_CCC _SFR_MEM16(0x0A2C) -+#define TCE0_CCD _SFR_MEM16(0x0A2E) -+#define TCE0_PERBUF _SFR_MEM16(0x0A36) -+#define TCE0_CCABUF _SFR_MEM16(0x0A38) -+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESE_CTRLA _SFR_MEM8(0x0A90) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE0_DATA _SFR_MEM8(0x0AA0) -+#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -+#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -+#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -+#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -+#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -+#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* VPORT - Virtual Ports */ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* CLK.USBCTRL bit masks and bit positions */ -+#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -+#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -+#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -+#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -+#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -+#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -+#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -+#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ -+ -+#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -+#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -+#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ -+ -+#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_USB_bm 0x40 /* USB bit mask. */ -+#define PR_USB_bp 6 /* USB bit position. */ -+ -+#define PR_AES_bm 0x10 /* AES bit mask. */ -+#define PR_AES_bp 4 /* AES bit position. */ -+ -+#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -+#define PR_EBI_bp 3 /* External Bus Interface bit position. */ -+ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -+#define PR_DMA_bp 0 /* DMA-Controller bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -+#define PR_DAC_bp 2 /* Port A DAC bit position. */ -+ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPB bit masks and bit positions */ -+/* PR_DAC Predefined. */ -+/* PR_DAC Predefined. */ -+ -+/* PR_ADC Predefined. */ -+/* PR_ADC Predefined. */ -+ -+/* PR_AC Predefined. */ -+/* PR_AC Predefined. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -+#define PR_USART1_bp 5 /* Port C USART1 bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -+#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ -+ -+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -+ -+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ -+ -+/* PR.PRPD bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPE bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPF bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -+#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -+#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ -+ -+#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ -+ -+#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -+#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.MCUCR bit masks and bit positions */ -+#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -+#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ -+ -+/* MCU.ANAINIT bit masks and bit positions */ -+#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -+#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -+#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -+#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -+#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -+#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ -+ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -+#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ -+ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.AWEXLOCK bit masks and bit positions */ -+#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ -+#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ -+ -+#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -+#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ -+ -+#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ -+#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ -+ -+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* PORTCFG - Port Configuration */ -+/* PORTCFG.VPCTRLA bit masks and bit positions */ -+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ -+ -+/* PORTCFG.VPCTRLB bit masks and bit positions */ -+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ -+ -+/* PORTCFG.CLKEVOUT bit masks and bit positions */ -+#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ -+ -+#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -+#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -+#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -+#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -+#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -+#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ -+ -+#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -+#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ -+ -+#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -+#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ -+ -+/* PORTCFG.EBIOUT bit masks and bit positions */ -+#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ -+#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ -+#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ -+#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ -+#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ -+#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ -+ -+#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ -+#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ -+#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ -+#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ -+#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ -+#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ -+ -+/* PORTCFG.EVOUTSEL bit masks and bit positions */ -+#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -+#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -+#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -+#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -+#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -+#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -+#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -+#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ -+ -+/* AES - AES Module */ -+/* AES.CTRL bit masks and bit positions */ -+#define AES_START_bm 0x80 /* Start/Run bit mask. */ -+#define AES_START_bp 7 /* Start/Run bit position. */ -+ -+#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -+#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ -+ -+#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -+#define AES_RESET_bp 5 /* AES Software Reset bit position. */ -+ -+#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -+#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ -+ -+#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -+#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ -+ -+/* AES.STATUS bit masks and bit positions */ -+#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -+#define AES_ERROR_bp 7 /* AES Error bit position. */ -+ -+#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -+#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ -+ -+/* AES.INTCTRL bit masks and bit positions */ -+#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -+#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* DMA - DMA Controller */ -+/* DMA_CH.CTRLA bit masks and bit positions */ -+#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -+#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ -+ -+#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -+#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ -+ -+#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -+#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ -+ -+#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -+#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ -+ -+#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -+#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ -+ -+#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -+#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -+#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -+#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -+#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -+#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ -+ -+/* DMA_CH.CTRLB bit masks and bit positions */ -+#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -+#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ -+ -+#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -+#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ -+ -+#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -+#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ -+ -+#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -+#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -+#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -+#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -+#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -+#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ -+ -+#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -+#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -+#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -+#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -+#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -+#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ -+ -+/* DMA_CH.ADDRCTRL bit masks and bit positions */ -+#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -+#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -+#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -+#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -+#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -+#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ -+ -+#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -+#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -+#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -+#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -+#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -+#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ -+ -+#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -+#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -+#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -+#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -+#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -+#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ -+ -+#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -+#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -+#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -+#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -+#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -+#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ -+ -+/* DMA_CH.TRIGSRC bit masks and bit positions */ -+#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -+#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -+#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -+#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -+#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -+#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -+#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -+#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -+#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -+#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -+#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -+#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -+#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -+#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -+#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -+#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -+#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -+#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ -+ -+/* DMA.CTRL bit masks and bit positions */ -+#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -+#define DMA_ENABLE_bp 7 /* Enable bit position. */ -+ -+#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -+#define DMA_RESET_bp 6 /* Software Reset bit position. */ -+ -+#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -+#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -+#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -+#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -+#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -+#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ -+ -+#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -+#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -+#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -+#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -+#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -+#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ -+ -+/* DMA.INTFLAGS bit masks and bit positions */ -+#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ -+ -+/* DMA.STATUS bit masks and bit positions */ -+#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -+#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ -+ -+#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -+#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ -+ -+#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -+#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ -+ -+#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -+#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ -+ -+#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -+#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ -+ -+#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -+#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ -+ -+#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -+#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ -+ -+#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -+#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH4MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH5MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH6MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH7MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_QDIRM Predefined. */ -+/* EVSYS_QDIRM Predefined. */ -+ -+/* EVSYS_QDIEN Predefined. */ -+/* EVSYS_QDIEN Predefined. */ -+ -+/* EVSYS_QDEN Predefined. */ -+/* EVSYS_QDEN Predefined. */ -+ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH4CTRL bit masks and bit positions */ -+/* EVSYS_QDIRM Predefined. */ -+/* EVSYS_QDIRM Predefined. */ -+ -+/* EVSYS_QDIEN Predefined. */ -+/* EVSYS_QDIEN Predefined. */ -+ -+/* EVSYS_QDEN Predefined. */ -+/* EVSYS_QDEN Predefined. */ -+ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH5CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH6CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH7CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0x7F /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ -+ -+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ -+ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -+#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ -+#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -+#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -+#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -+#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -+#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -+#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -+#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -+#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -+#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -+#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ -+ -+#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -+#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -+#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -+#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -+#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -+#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -+#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -+#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -+#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -+#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -+#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -+#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -+#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -+#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -+#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ -+ -+#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -+#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ -+ -+#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -+#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ -+ -+#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -+#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ -+ -+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -+#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ -+#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ -+ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -+#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -+#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -+#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -+#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -+#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ -+ -+#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -+#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -+#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ -+ -+#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -+#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ -+ -+#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -+#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ -+ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* DAC - Digital/Analog Converter */ -+/* DAC.CTRLA bit masks and bit positions */ -+#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -+#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ -+ -+#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -+#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ -+ -+#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -+#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ -+ -+#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -+#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ -+ -+#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define DAC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* DAC.CTRLB bit masks and bit positions */ -+#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -+#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -+#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -+#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -+#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -+#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ -+ -+#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -+#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ -+ -+#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -+#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ -+ -+/* DAC.CTRLC bit masks and bit positions */ -+#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -+#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -+#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -+#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -+#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -+#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ -+ -+#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -+#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ -+ -+/* DAC.EVCTRL bit masks and bit positions */ -+#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -+#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ -+ -+#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -+#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -+#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -+#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -+#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -+#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -+#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -+#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ -+ -+/* DAC.STATUS bit masks and bit positions */ -+#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -+#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ -+ -+#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -+#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ -+ -+/* DAC.CH0GAINCAL bit masks and bit positions */ -+#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -+#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -+#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -+#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -+#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -+#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -+#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -+#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -+#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -+#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -+#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -+#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -+#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -+#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -+#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -+#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ -+ -+/* DAC.CH0OFFSETCAL bit masks and bit positions */ -+#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -+#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -+#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -+#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -+#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -+#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -+#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -+#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -+#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -+#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -+#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -+#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -+#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -+#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -+#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -+#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ -+ -+/* DAC.CH1GAINCAL bit masks and bit positions */ -+#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -+#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -+#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -+#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -+#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -+#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -+#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -+#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -+#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -+#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -+#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -+#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -+#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -+#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -+#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -+#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ -+ -+/* DAC.CH1OFFSETCAL bit masks and bit positions */ -+#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -+#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -+#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -+#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -+#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -+#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -+#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -+#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -+#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -+#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -+#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -+#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -+#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -+#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -+#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -+#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -+#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HSMODE Predefined. */ -+/* AC_HSMODE Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* RTC - Real-Time Counter */ -+/* RTC.CTRL bit masks and bit positions */ -+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ -+ -+/* RTC.STATUS bit masks and bit positions */ -+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC.INTCTRL bit masks and bit positions */ -+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC.INTFLAGS bit masks and bit positions */ -+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* USB - USB */ -+/* USB_EP.STATUS bit masks and bit positions */ -+#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -+#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ -+ -+#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -+#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ -+ -+#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -+#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ -+ -+#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -+#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ -+ -+#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -+#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ -+ -+#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -+#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ -+ -+#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -+#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ -+ -+#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -+#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ -+ -+#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ -+ -+#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ -+ -+#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -+#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ -+ -+/* USB_EP.CTRL bit masks and bit positions */ -+#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -+#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -+#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -+#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -+#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -+#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ -+ -+#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -+#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ -+ -+#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -+#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ -+ -+#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -+#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ -+ -+#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -+#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ -+ -+#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -+#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -+#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -+#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -+#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -+#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -+#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -+#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ -+ -+/* USB_EP.CNT bit masks and bit positions */ -+#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -+#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ -+ -+/* USB.CTRLA bit masks and bit positions */ -+#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -+#define USB_ENABLE_bp 7 /* USB Enable bit position. */ -+ -+#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -+#define USB_SPEED_bp 6 /* Speed Select bit position. */ -+ -+#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -+#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ -+ -+#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -+#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ -+ -+#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -+#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -+#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -+#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -+#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -+#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -+#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -+#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -+#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -+#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ -+ -+/* USB.CTRLB bit masks and bit positions */ -+#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -+#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ -+ -+#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -+#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ -+ -+#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -+#define USB_GNACK_bp 1 /* Global NACK bit position. */ -+ -+#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -+#define USB_ATTACH_bp 0 /* Attach bit position. */ -+ -+/* USB.STATUS bit masks and bit positions */ -+#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -+#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ -+ -+#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -+#define USB_RESUME_bp 2 /* Resume bit position. */ -+ -+#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -+#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ -+ -+#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -+#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ -+ -+/* USB.ADDR bit masks and bit positions */ -+#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -+#define USB_ADDR_gp 0 /* Device Address group position. */ -+#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -+#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -+#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -+#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -+#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -+#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -+#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -+#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -+#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -+#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -+#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -+#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -+#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -+#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ -+ -+/* USB.FIFOWP bit masks and bit positions */ -+#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -+#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -+#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -+#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -+#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -+#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -+#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -+#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -+#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -+#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -+#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -+#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ -+ -+/* USB.FIFORP bit masks and bit positions */ -+#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -+#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -+#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -+#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -+#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -+#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -+#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -+#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -+#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -+#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -+#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -+#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ -+ -+/* USB.INTCTRLA bit masks and bit positions */ -+#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -+#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ -+ -+#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -+#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ -+ -+#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -+#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ -+ -+#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -+#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ -+ -+#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* USB.INTCTRLB bit masks and bit positions */ -+#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -+#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ -+ -+#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -+#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ -+ -+/* USB.INTFLAGSACLR bit masks and bit positions */ -+#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -+#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ -+ -+#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -+#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ -+ -+#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -+#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ -+ -+#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -+#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ -+ -+#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -+#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ -+ -+#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -+#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ -+ -+#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -+#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ -+ -+#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -+#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSASET bit masks and bit positions */ -+/* USB_SOFIF Predefined. */ -+/* USB_SOFIF Predefined. */ -+ -+/* USB_SUSPENDIF Predefined. */ -+/* USB_SUSPENDIF Predefined. */ -+ -+/* USB_RESUMEIF Predefined. */ -+/* USB_RESUMEIF Predefined. */ -+ -+/* USB_RSTIF Predefined. */ -+/* USB_RSTIF Predefined. */ -+ -+/* USB_CRCIF Predefined. */ -+/* USB_CRCIF Predefined. */ -+ -+/* USB_UNFIF Predefined. */ -+/* USB_UNFIF Predefined. */ -+ -+/* USB_OVFIF Predefined. */ -+/* USB_OVFIF Predefined. */ -+ -+/* USB_STALLIF Predefined. */ -+/* USB_STALLIF Predefined. */ -+ -+/* USB.INTFLAGSBCLR bit masks and bit positions */ -+#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -+#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ -+ -+#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -+#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSBSET bit masks and bit positions */ -+/* USB_TRNIF Predefined. */ -+/* USB_TRNIF Predefined. */ -+ -+/* USB_SETUPIF Predefined. */ -+/* USB_SETUPIF Predefined. */ -+ -+/* PORT - I/O Port Configuration */ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ -+ -+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -+#define PORT_SPI_bp 5 /* SPI bit position. */ -+ -+#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -+#define PORT_USART0_bp 4 /* USART0 bit position. */ -+ -+#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -+#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ -+ -+#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -+#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ -+ -+#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -+#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ -+ -+#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -+#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ -+ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC0.CTRLA bit masks and bit positions */ -+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC0.CTRLB bit masks and bit positions */ -+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ -+ -+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ -+ -+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC0.CTRLC bit masks and bit positions */ -+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ -+ -+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ -+ -+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC0.CTRLD bit masks and bit positions */ -+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC0_EVACT_gp 5 /* Event Action group position. */ -+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC0.CTRLE bit masks and bit positions */ -+#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC0.INTCTRLA bit masks and bit positions */ -+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC0.INTCTRLB bit masks and bit positions */ -+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ -+ -+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ -+ -+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC0.CTRLFCLR bit masks and bit positions */ -+#define TC0_CMD_gm 0x0C /* Command group mask. */ -+#define TC0_CMD_gp 2 /* Command group position. */ -+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC0_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC0_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC0_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC0.CTRLFSET bit masks and bit positions */ -+/* TC0_CMD Predefined. */ -+/* TC0_CMD Predefined. */ -+ -+/* TC0_LUPD Predefined. */ -+/* TC0_LUPD Predefined. */ -+ -+/* TC0_DIR Predefined. */ -+/* TC0_DIR Predefined. */ -+ -+/* TC0.CTRLGCLR bit masks and bit positions */ -+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ -+ -+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ -+ -+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC0.CTRLGSET bit masks and bit positions */ -+/* TC0_CCDBV Predefined. */ -+/* TC0_CCDBV Predefined. */ -+ -+/* TC0_CCCBV Predefined. */ -+/* TC0_CCCBV Predefined. */ -+ -+/* TC0_CCBBV Predefined. */ -+/* TC0_CCBBV Predefined. */ -+ -+/* TC0_CCABV Predefined. */ -+/* TC0_CCABV Predefined. */ -+ -+/* TC0_PERBV Predefined. */ -+/* TC0_PERBV Predefined. */ -+ -+/* TC0.INTFLAGS bit masks and bit positions */ -+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ -+ -+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ -+ -+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC1.CTRLA bit masks and bit positions */ -+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC1.CTRLB bit masks and bit positions */ -+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC1.CTRLC bit masks and bit positions */ -+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC1.CTRLD bit masks and bit positions */ -+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC1_EVACT_gp 5 /* Event Action group position. */ -+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC1.CTRLE bit masks and bit positions */ -+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ -+ -+/* TC1.INTCTRLA bit masks and bit positions */ -+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC1.INTCTRLB bit masks and bit positions */ -+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC1.CTRLFCLR bit masks and bit positions */ -+#define TC1_CMD_gm 0x0C /* Command group mask. */ -+#define TC1_CMD_gp 2 /* Command group position. */ -+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC1_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC1_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC1_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC1.CTRLFSET bit masks and bit positions */ -+/* TC1_CMD Predefined. */ -+/* TC1_CMD Predefined. */ -+ -+/* TC1_LUPD Predefined. */ -+/* TC1_LUPD Predefined. */ -+ -+/* TC1_DIR Predefined. */ -+/* TC1_DIR Predefined. */ -+ -+/* TC1.CTRLGCLR bit masks and bit positions */ -+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC1.CTRLGSET bit masks and bit positions */ -+/* TC1_CCBBV Predefined. */ -+/* TC1_CCBBV Predefined. */ -+ -+/* TC1_CCABV Predefined. */ -+/* TC1_CCABV Predefined. */ -+ -+/* TC1_PERBV Predefined. */ -+/* TC1_PERBV Predefined. */ -+ -+/* TC1.INTFLAGS bit masks and bit positions */ -+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+/* TC2.CTRLA bit masks and bit positions */ -+#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC2.CTRLB bit masks and bit positions */ -+#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -+#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ -+ -+#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -+#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ -+ -+#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -+#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ -+ -+#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -+#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ -+ -+#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -+#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ -+ -+#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -+#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ -+ -+#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -+#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ -+ -+#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -+#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ -+ -+/* TC2.CTRLC bit masks and bit positions */ -+#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -+#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ -+ -+#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -+#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ -+ -+#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -+#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ -+ -+#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -+#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ -+ -+#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -+#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ -+ -+#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -+#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ -+ -+#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -+#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ -+ -+#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -+#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ -+ -+/* TC2.CTRLE bit masks and bit positions */ -+#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC2.INTCTRLA bit masks and bit positions */ -+#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -+#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -+#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -+#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -+#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -+#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ -+ -+#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -+#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -+#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -+#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -+#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -+#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ -+ -+/* TC2.INTCTRLB bit masks and bit positions */ -+#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -+#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -+#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -+#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -+#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -+#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -+#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -+#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -+#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -+#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -+#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -+#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -+#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -+#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -+#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -+#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -+#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -+#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -+#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -+#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -+#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ -+ -+/* TC2.CTRLF bit masks and bit positions */ -+#define TC2_CMD_gm 0x0C /* Command group mask. */ -+#define TC2_CMD_gp 2 /* Command group position. */ -+#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC2_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -+#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -+#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -+#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -+#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -+#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ -+ -+/* TC2.INTFLAGS bit masks and bit positions */ -+#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -+#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ -+ -+#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -+#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ -+ -+#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -+#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ -+ -+#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -+#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ -+ -+#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ -+ -+#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ -+ -+/* AWEX - Timer/Counter Advanced Waveform Extension */ -+/* AWEX.CTRL bit masks and bit positions */ -+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ -+ -+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ -+ -+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ -+ -+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ -+ -+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ -+ -+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ -+ -+/* AWEX.FDCTRL bit masks and bit positions */ -+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ -+ -+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ -+ -+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ -+ -+/* AWEX.STATUS bit masks and bit positions */ -+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ -+ -+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ -+ -+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ -+ -+/* AWEX.STATUSSET bit masks and bit positions */ -+/* AWEX_FDF Predefined. */ -+/* AWEX_FDF Predefined. */ -+ -+/* AWEX_DTHSBUFV Predefined. */ -+/* AWEX_DTHSBUFV Predefined. */ -+ -+/* AWEX_DTLSBUFV Predefined. */ -+/* AWEX_DTLSBUFV Predefined. */ -+ -+/* HIRES - Timer/Counter High-Resolution Extension */ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -+#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* LOCKBIT - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT0_vect_num 2 -+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -+#define PORTC_INT1_vect_num 3 -+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT0_vect_num 4 -+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -+#define PORTR_INT1_vect_num 5 -+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ -+ -+/* DMA interrupt vectors */ -+#define DMA_CH0_vect_num 6 -+#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -+#define DMA_CH1_vect_num 7 -+#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -+#define DMA_CH2_vect_num 8 -+#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -+#define DMA_CH3_vect_num 9 -+#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ -+ -+/* RTC interrupt vectors */ -+#define RTC_OVF_vect_num 10 -+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -+#define RTC_COMP_vect_num 11 -+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 12 -+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 13 -+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_OVF_vect_num 14 -+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LUNF_vect_num 14 -+#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_ERR_vect_num 15 -+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_HUNF_vect_num 15 -+#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCA_vect_num 16 -+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPA_vect_num 16 -+#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCB_vect_num 17 -+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPB_vect_num 17 -+#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCC_vect_num 18 -+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPC_vect_num 18 -+#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCD_vect_num 19 -+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPD_vect_num 19 -+#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ -+ -+/* TCC1 interrupt vectors */ -+#define TCC1_OVF_vect_num 20 -+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -+#define TCC1_ERR_vect_num 21 -+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -+#define TCC1_CCA_vect_num 22 -+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -+#define TCC1_CCB_vect_num 23 -+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 24 -+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 25 -+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 26 -+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 27 -+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ -+ -+/* USARTC1 interrupt vectors */ -+#define USARTC1_RXC_vect_num 28 -+#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -+#define USARTC1_DRE_vect_num 29 -+#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -+#define USARTC1_TXC_vect_num 30 -+#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ -+ -+/* AES interrupt vectors */ -+#define AES_INT_vect_num 31 -+#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 32 -+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -+#define NVM_SPM_vect_num 33 -+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ -+ -+/* PORTB interrupt vectors */ -+#define PORTB_INT0_vect_num 34 -+#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -+#define PORTB_INT1_vect_num 35 -+#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ -+ -+/* PORTE interrupt vectors */ -+#define PORTE_INT0_vect_num 43 -+#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -+#define PORTE_INT1_vect_num 44 -+#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ -+ -+/* TWIE interrupt vectors */ -+#define TWIE_TWIS_vect_num 45 -+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -+#define TWIE_TWIM_vect_num 46 -+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_OVF_vect_num 47 -+#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -+#define TCE0_ERR_vect_num 48 -+#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -+#define TCE0_CCA_vect_num 49 -+#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -+#define TCE0_CCB_vect_num 50 -+#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -+#define TCE0_CCC_vect_num 51 -+#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -+#define TCE0_CCD_vect_num 52 -+#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ -+ -+/* USARTE0 interrupt vectors */ -+#define USARTE0_RXC_vect_num 58 -+#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -+#define USARTE0_DRE_vect_num 59 -+#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -+#define USARTE0_TXC_vect_num 60 -+#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT0_vect_num 64 -+#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -+#define PORTD_INT1_vect_num 65 -+#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ -+ -+/* PORTA interrupt vectors */ -+#define PORTA_INT0_vect_num 66 -+#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -+#define PORTA_INT1_vect_num 67 -+#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ -+ -+/* ACA interrupt vectors */ -+#define ACA_AC0_vect_num 68 -+#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -+#define ACA_AC1_vect_num 69 -+#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -+#define ACA_ACW_vect_num 70 -+#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ -+ -+/* ADCA interrupt vectors */ -+#define ADCA_CH0_vect_num 71 -+#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -+#define ADCA_CH1_vect_num 72 -+#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -+#define ADCA_CH2_vect_num 73 -+#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -+#define ADCA_CH3_vect_num 74 -+#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_OVF_vect_num 77 -+#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LUNF_vect_num 77 -+#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_ERR_vect_num 78 -+#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_HUNF_vect_num 78 -+#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCA_vect_num 79 -+#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPA_vect_num 79 -+#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCB_vect_num 80 -+#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPB_vect_num 80 -+#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCC_vect_num 81 -+#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPC_vect_num 81 -+#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCD_vect_num 82 -+#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPD_vect_num 82 -+#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ -+ -+/* TCD1 interrupt vectors */ -+#define TCD1_OVF_vect_num 83 -+#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -+#define TCD1_ERR_vect_num 84 -+#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -+#define TCD1_CCA_vect_num 85 -+#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -+#define TCD1_CCB_vect_num 86 -+#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ -+ -+/* SPID interrupt vectors */ -+#define SPID_INT_vect_num 87 -+#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ -+ -+/* USARTD0 interrupt vectors */ -+#define USARTD0_RXC_vect_num 88 -+#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -+#define USARTD0_DRE_vect_num 89 -+#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -+#define USARTD0_TXC_vect_num 90 -+#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ -+ -+/* USARTD1 interrupt vectors */ -+#define USARTD1_RXC_vect_num 91 -+#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -+#define USARTD1_DRE_vect_num 92 -+#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -+#define USARTD1_TXC_vect_num 93 -+#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ -+ -+/* USB interrupt vectors */ -+#define USB_BUSEVENT_vect_num 125 -+#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -+#define USB_TRNCOMPL_vect_num 126 -+#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (127 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (139264) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (131072) -+#define APP_SECTION_PAGE_SIZE (256) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0x1E000) -+#define APPTABLE_SECTION_SIZE (8192) -+#define APPTABLE_SECTION_PAGE_SIZE (256) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x20000) -+#define BOOT_SECTION_SIZE (8192) -+#define BOOT_SECTION_PAGE_SIZE (256) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (16384) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (2048) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (8192) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (2048) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (6) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (256) -+#define USER_SIGNATURES_PAGE_SIZE (256) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (64) -+#define PROD_SIGNATURES_PAGE_SIZE (256) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 256 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 6 -+ -+/* Fuse Byte 0 Reserved */ -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x97 -+#define SIGNATURE_2 0x46 -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA128A4U_H_INCLUDED */ -+ -diff --git a/include/avr/iox128b1.h b/include/avr/iox128b1.h -new file mode 100644 -index 0000000..6092348 ---- /dev/null -+++ b/include/avr/iox128b1.h -@@ -0,0 +1,6831 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox128b1.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA128B1_H_INCLUDED -+#define _AVR_ATXMEGA128B1_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+VPORT - Virtual Ports -+-------------------------------------------------------------------------- -+*/ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t USBCTRL; /* USB Control Register */ -+} CLK_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+/* USB Prescaler Division Factor */ -+typedef enum CLK_USBPSDIV_enum -+{ -+ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ -+ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ -+ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ -+ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ -+ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ -+ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -+} CLK_USBPSDIV_t; -+ -+/* USB Clock Source */ -+typedef enum CLK_USBSRC_enum -+{ -+ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ -+ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -+} CLK_USBSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control Register */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C0_gc = (0x01<<0), /* External Clock on port C0 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C1_gc = (0x05<<0), /* External Clock on port C1 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C2_gc = (0x09<<0), /* External Clock on port C2 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C3_gc = (0x0D<<0), /* External Clock on port C3 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C4_gc = (0x11<<0), /* External Clock on port C4 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C5_gc = (0x15<<0), /* External Clock on port C5 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C6_gc = (0x19<<0), /* External Clock on port C6 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C7_gc = (0x1D<<0), /* External Clock on port C7 - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+/* 2 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC2MCREF_enum -+{ -+ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC2MCREF_t; -+ -+/* 32 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC32MCREF_enum -+{ -+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -+} OSC_RC32MCREF_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PR - Power Reduction -+-------------------------------------------------------------------------- -+*/ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t PRPB; /* Power Reduction Port B */ -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t reserved_0x04; -+ register8_t PRPE; /* Power Reduction Port E */ -+} PR_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t JTAGUID; /* JTAG User ID */ -+ register8_t reserved_0x05; -+ register8_t MCUCR; /* MCU Control */ -+ register8_t ANAINIT; /* Analog Startup Delay */ -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t AWEXLOCK; /* AWEX Lock */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORTCFG - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t VPCTRLA; /* Virtual Port Control Register A */ -+ register8_t VPCTRLB; /* Virtual Port Control Register B */ -+ register8_t CLKEVOUT; /* Clock and Event Out Register */ -+ register8_t reserved_0x05; -+ register8_t EVOUTSEL; /* Event Output Select */ -+} PORTCFG_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP02MAP_enum -+{ -+ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ -+ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ -+ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ -+ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ -+ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ -+ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ -+ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ -+ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -+} PORTCFG_VP02MAP_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP13MAP_enum -+{ -+ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ -+ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ -+ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ -+ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ -+ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ -+ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ -+ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ -+ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -+} PORTCFG_VP13MAP_t; -+ -+/* System Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC_gc = (0x01<<0), /* System Clock Output on Port C */ -+ PORTCFG_CLKOUT_PE_gc = (0x03<<0), /* System Clock Output on Port E */ -+} PORTCFG_CLKOUT_t; -+ -+/* Peripheral Clock Output Select */ -+typedef enum PORTCFG_CLKOUTSEL_enum -+{ -+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -+} PORTCFG_CLKOUTSEL_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC_gc = (0x01<<4), /* Event Channel 0 Output on Port C */ -+ PORTCFG_EVOUT_PE_gc = (0x03<<4), /* Event Channel 0 Output on Port E */ -+} PORTCFG_EVOUT_t; -+ -+/* Clock and Event Output Port */ -+typedef enum PORTCFG_CLKEVPIN_enum -+{ -+ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ -+ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -+} PORTCFG_CLKEVPIN_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<2), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<2), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<2), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<2), /* Event Channel 3 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AES - AES Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* AES Module */ -+typedef struct AES_struct -+{ -+ register8_t CTRL; /* AES Control Register */ -+ register8_t STATUS; /* AES Status Register */ -+ register8_t STATE; /* AES State Register */ -+ register8_t KEY; /* AES Key Register */ -+ register8_t INTCTRL; /* AES Interrupt Control Register */ -+} AES_t; -+ -+/* Interrupt level */ -+typedef enum AES_INTLVL_enum -+{ -+ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} AES_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ -+ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DMA - DMA Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* DMA Channel */ -+typedef struct DMA_CH_struct -+{ -+ register8_t CTRLA; /* Channel Control */ -+ register8_t CTRLB; /* Channel Control */ -+ register8_t ADDRCTRL; /* Address Control */ -+ register8_t TRIGSRC; /* Channel Trigger Source */ -+ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ -+ register8_t REPCNT; /* Channel Repeat Count */ -+ register8_t reserved_0x07; -+ register8_t SRCADDR0; /* Channel Source Address 0 */ -+ register8_t SRCADDR1; /* Channel Source Address 1 */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t DESTADDR0; /* Channel Destination Address 0 */ -+ register8_t DESTADDR1; /* Channel Destination Address 1 */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} DMA_CH_t; -+ -+ -+/* DMA Controller */ -+typedef struct DMA_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t reserved_0x01; -+ register8_t reserved_0x02; -+ register8_t INTFLAGS; /* Transfer Interrupt Status */ -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x05; -+ _WORDREGISTER(TEMP); /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ DMA_CH_t CH0; /* DMA Channel 0 */ -+ DMA_CH_t CH1; /* DMA Channel 1 */ -+} DMA_t; -+ -+/* Burst mode */ -+typedef enum DMA_CH_BURSTLEN_enum -+{ -+ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ -+ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ -+ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ -+ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -+} DMA_CH_BURSTLEN_t; -+ -+/* Source address reload mode */ -+typedef enum DMA_CH_SRCRELOAD_enum -+{ -+ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ -+ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ -+ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ -+ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -+} DMA_CH_SRCRELOAD_t; -+ -+/* Source addressing mode */ -+typedef enum DMA_CH_SRCDIR_enum -+{ -+ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ -+ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ -+ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -+} DMA_CH_SRCDIR_t; -+ -+/* Destination adress reload mode */ -+typedef enum DMA_CH_DESTRELOAD_enum -+{ -+ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ -+ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ -+ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ -+ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -+} DMA_CH_DESTRELOAD_t; -+ -+/* Destination adressing mode */ -+typedef enum DMA_CH_DESTDIR_enum -+{ -+ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ -+ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ -+ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -+} DMA_CH_DESTDIR_t; -+ -+/* Transfer trigger source */ -+typedef enum DMA_CH_TRIGSRC_enum -+{ -+ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ -+ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ -+ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ -+ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ -+ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ -+ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ -+ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ -+ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ -+ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ -+ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ -+ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ -+ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ -+ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ -+} DMA_CH_TRIGSRC_t; -+ -+/* Double buffering mode */ -+typedef enum DMA_DBUFMODE_enum -+{ -+ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ -+ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ -+} DMA_DBUFMODE_t; -+ -+/* Priority mode */ -+typedef enum DMA_PRIMODE_enum -+{ -+ DMA_PRIMODE_RR01_gc = (0x00<<0), /* Round Robin */ -+ DMA_PRIMODE_CH0RR1_gc = (0x01<<0), /* Channel 0 > channel 1 */ -+} DMA_PRIMODE_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_ERRINTLVL_enum -+{ -+ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ -+ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ -+ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -+} DMA_CH_ERRINTLVL_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_TRNINTLVL_enum -+{ -+ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ -+ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -+} DMA_CH_TRNINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+} EVSYS_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ -+ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ -+ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ -+ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ -+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ -+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ -+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ -+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ -+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ -+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ -+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ -+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ -+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ -+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ -+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ -+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ -+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ -+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ -+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ -+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ -+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ -+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ -+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ -+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ -+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ -+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ -+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ -+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ -+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ -+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -+} EVSYS_CHMUX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ -+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ -+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ -+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ -+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} NVM_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t reserved_0x07; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+} ADC_t; -+ -+/* Current Limitation */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -+} ADC_CURRLIMIT_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+} ADC_CH_MUXNEG_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ -+ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ -+ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ -+ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+ register8_t CURRCTRL; /* Current Source Control Register */ -+ register8_t CURRCALIB; /* Current Source Calibration Register */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC - Real-Time Counter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Real-Time Counter */ -+typedef struct RTC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary register */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ _WORDREGISTER(CNT); /* Count Register */ -+ _WORDREGISTER(PER); /* Period Register */ -+ _WORDREGISTER(COMP); /* Compare Register */ -+} RTC_t; -+ -+/* Prescaler Factor */ -+typedef enum RTC_PRESCALER_enum -+{ -+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ -+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ -+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ -+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ -+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ -+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ -+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ -+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -+} RTC_PRESCALER_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC_COMPINTLVL_enum -+{ -+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC_OVFINTLVL_enum -+{ -+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+} TWI_t; -+ -+/* SDA Hold Time */ -+typedef enum TWI_SDAHOLD_enum -+{ -+ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ -+ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ -+ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ -+ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -+} TWI_SDAHOLD_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USB - USB -+-------------------------------------------------------------------------- -+*/ -+ -+/* USB Endpoint */ -+typedef struct USB_EP_struct -+{ -+ register8_t STATUS; /* Endpoint Status */ -+ register8_t CTRL; /* Endpoint Control */ -+ _WORDREGISTER(CNT); /* USB Endpoint Counter */ -+ _WORDREGISTER(DATAPTR); /* Data Pointer */ -+ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -+} USB_EP_t; -+ -+ -+/* Universal Serial Bus */ -+typedef struct USB_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t FIFOWP; /* FIFO Write Pointer Register */ -+ register8_t FIFORP; /* FIFO Read Pointer Register */ -+ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ -+ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ -+ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ -+ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t reserved_0x20; -+ register8_t reserved_0x21; -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t CAL0; /* Calibration Byte 0 */ -+ register8_t CAL1; /* Calibration Byte 1 */ -+} USB_t; -+ -+ -+/* USB Endpoint Table */ -+typedef struct USB_EP_TABLE_struct -+{ -+ USB_EP_t EP0OUT; /* Endpoint 0 */ -+ USB_EP_t EP0IN; /* Endpoint 0 */ -+ USB_EP_t EP1OUT; /* Endpoint 1 */ -+ USB_EP_t EP1IN; /* Endpoint 1 */ -+ USB_EP_t EP2OUT; /* Endpoint 2 */ -+ USB_EP_t EP2IN; /* Endpoint 2 */ -+ USB_EP_t EP3OUT; /* Endpoint 3 */ -+ USB_EP_t EP3IN; /* Endpoint 3 */ -+ USB_EP_t EP4OUT; /* Endpoint 4 */ -+ USB_EP_t EP4IN; /* Endpoint 4 */ -+ USB_EP_t EP5OUT; /* Endpoint 5 */ -+ USB_EP_t EP5IN; /* Endpoint 5 */ -+ USB_EP_t EP6OUT; /* Endpoint 6 */ -+ USB_EP_t EP6IN; /* Endpoint 6 */ -+ USB_EP_t EP7OUT; /* Endpoint 7 */ -+ USB_EP_t EP7IN; /* Endpoint 7 */ -+ USB_EP_t EP8OUT; /* Endpoint 8 */ -+ USB_EP_t EP8IN; /* Endpoint 8 */ -+ USB_EP_t EP9OUT; /* Endpoint 9 */ -+ USB_EP_t EP9IN; /* Endpoint 9 */ -+ USB_EP_t EP10OUT; /* Endpoint 10 */ -+ USB_EP_t EP10IN; /* Endpoint 10 */ -+ USB_EP_t EP11OUT; /* Endpoint 11 */ -+ USB_EP_t EP11IN; /* Endpoint 11 */ -+ USB_EP_t EP12OUT; /* Endpoint 12 */ -+ USB_EP_t EP12IN; /* Endpoint 12 */ -+ USB_EP_t EP13OUT; /* Endpoint 13 */ -+ USB_EP_t EP13IN; /* Endpoint 13 */ -+ USB_EP_t EP14OUT; /* Endpoint 14 */ -+ USB_EP_t EP14IN; /* Endpoint 14 */ -+ USB_EP_t EP15OUT; /* Endpoint 15 */ -+ USB_EP_t EP15IN; /* Endpoint 15 */ -+ register8_t reserved_0x100; -+ register8_t reserved_0x101; -+ register8_t reserved_0x102; -+ register8_t reserved_0x103; -+ register8_t reserved_0x104; -+ register8_t reserved_0x105; -+ register8_t reserved_0x106; -+ register8_t reserved_0x107; -+ register8_t reserved_0x108; -+ register8_t reserved_0x109; -+ register8_t reserved_0x10A; -+ register8_t reserved_0x10B; -+ register8_t reserved_0x10C; -+ register8_t reserved_0x10D; -+ register8_t reserved_0x10E; -+ register8_t reserved_0x10F; -+ register8_t FRAMENUML; /* Frame Number Low Byte */ -+ register8_t FRAMENUMH; /* Frame Number High Byte */ -+} USB_EP_TABLE_t; -+ -+/* Interrupt level */ -+typedef enum USB_INTLVL_enum -+{ -+ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} USB_INTLVL_t; -+ -+/* USB Endpoint Type */ -+typedef enum USB_EP_TYPE_enum -+{ -+ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ -+ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ -+ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ -+ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -+} USB_EP_TYPE_t; -+ -+/* USB Endpoint Buffersize */ -+typedef enum USB_EP_BUFSIZE_enum -+{ -+ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ -+ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ -+ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ -+ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ -+ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ -+ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ -+ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ -+ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -+} USB_EP_BUFSIZE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - I/O Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INT0MASK; /* Port Interrupt 0 Mask */ -+ register8_t INT1MASK; /* Port Interrupt 1 Mask */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t REMAP; /* I/O Port Pin Remap Register */ -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Port Interrupt 0 Level */ -+typedef enum PORT_INT0LVL_enum -+{ -+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INT0LVL_t; -+ -+/* Port Interrupt 1 Level */ -+typedef enum PORT_INT1LVL_enum -+{ -+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ -+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ -+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -+} PORT_INT1LVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 0 */ -+typedef struct TC0_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC0_t; -+ -+ -+/* 16-bit Timer/Counter 1 */ -+typedef struct TC1_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+} TC1_t; -+ -+/* Clock Selection */ -+typedef enum TC_CLKSEL_enum -+{ -+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_CLKSEL_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC_WGMODE_enum -+{ -+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC_WGMODE_t; -+ -+/* Byte Mode */ -+typedef enum TC_BYTEM_enum -+{ -+ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ -+ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -+} TC_BYTEM_t; -+ -+/* Event Action */ -+typedef enum TC_EVACT_enum -+{ -+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ -+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ -+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ -+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ -+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ -+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC_EVSEL_enum -+{ -+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_EVSEL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC_ERRINTLVL_enum -+{ -+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC_OVFINTLVL_enum -+{ -+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_OVFINTLVL_t; -+ -+/* Compare or Capture D Interrupt Level */ -+typedef enum TC_CCDINTLVL_enum -+{ -+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC_CCDINTLVL_t; -+ -+/* Compare or Capture C Interrupt Level */ -+typedef enum TC_CCCINTLVL_enum -+{ -+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC_CCCINTLVL_t; -+ -+/* Compare or Capture B Interrupt Level */ -+typedef enum TC_CCBINTLVL_enum -+{ -+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_CCBINTLVL_t; -+ -+/* Compare or Capture A Interrupt Level */ -+typedef enum TC_CCAINTLVL_enum -+{ -+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_CCAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC_CMD_enum -+{ -+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC2 - 16-bit Timer/Counter type 2 -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter type 2 */ -+typedef struct TC2_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t reserved_0x03; -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t reserved_0x08; -+ register8_t CTRLF; /* Control Register F */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t LCNT; /* Low Byte Count */ -+ register8_t HCNT; /* High Byte Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t LPER; /* Low Byte Period */ -+ register8_t HPER; /* High Byte Period */ -+ register8_t LCMPA; /* Low Byte Compare A */ -+ register8_t HCMPA; /* High Byte Compare A */ -+ register8_t LCMPB; /* Low Byte Compare B */ -+ register8_t HCMPB; /* High Byte Compare B */ -+ register8_t LCMPC; /* Low Byte Compare C */ -+ register8_t HCMPC; /* High Byte Compare C */ -+ register8_t LCMPD; /* Low Byte Compare D */ -+ register8_t HCMPD; /* High Byte Compare D */ -+} TC2_t; -+ -+/* Clock Selection */ -+typedef enum TC2_CLKSEL_enum -+{ -+ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC2_CLKSEL_t; -+ -+/* Byte Mode */ -+typedef enum TC2_BYTEM_enum -+{ -+ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ -+ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -+} TC2_BYTEM_t; -+ -+/* High Byte Underflow Interrupt Level */ -+typedef enum TC2_HUNFINTLVL_enum -+{ -+ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_HUNFINTLVL_t; -+ -+/* Low Byte Underflow Interrupt Level */ -+typedef enum TC2_LUNFINTLVL_enum -+{ -+ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LUNFINTLVL_t; -+ -+/* Low Byte Compare D Interrupt Level */ -+typedef enum TC2_LCMPDINTLVL_enum -+{ -+ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC2_LCMPDINTLVL_t; -+ -+/* Low Byte Compare C Interrupt Level */ -+typedef enum TC2_LCMPCINTLVL_enum -+{ -+ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC2_LCMPCINTLVL_t; -+ -+/* Low Byte Compare B Interrupt Level */ -+typedef enum TC2_LCMPBINTLVL_enum -+{ -+ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_LCMPBINTLVL_t; -+ -+/* Low Byte Compare A Interrupt Level */ -+typedef enum TC2_LCMPAINTLVL_enum -+{ -+ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LCMPAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMD_enum -+{ -+ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC2_CMD_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMDEN_enum -+{ -+ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ -+ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ -+ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -+} TC2_CMDEN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AWEX - Timer/Counter Advanced Waveform Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Advanced Waveform Extension */ -+typedef struct AWEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t FDEMASK; /* Fault Detection Event Mask */ -+ register8_t FDCTRL; /* Fault Detection Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t STATUSSET; /* Status Set Register */ -+ register8_t DTBOTH; /* Dead Time Both Sides */ -+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ -+ register8_t DTLS; /* Dead Time Low Side */ -+ register8_t DTHS; /* Dead Time High Side */ -+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ -+ register8_t DTHSBUF; /* Dead Time High Side Buffer */ -+ register8_t OUTOVEN; /* Output Override Enable */ -+} AWEX_t; -+ -+/* Fault Detect Action */ -+typedef enum AWEX_FDACT_enum -+{ -+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ -+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -+} AWEX_FDACT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+HIRES - Timer/Counter High-Resolution Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register */ -+} HIRES_t; -+ -+/* High Resolution Enable */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ -+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+} IRDA_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LCD - LCD Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* LCD Controller */ -+typedef struct LCD_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t INTCTRL; /* Interrupt Enable Register */ -+ register8_t INTFLAG; /* Interrupt Flag Register */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t CTRLF; /* Control Register F */ -+ register8_t CTRLG; /* Control Register G */ -+ register8_t CTRLH; /* Control Register H */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t DATA0; /* LCD Data Register 0 */ -+ register8_t DATA1; /* LCD Data Register 1 */ -+ register8_t DATA2; /* LCD Data Register 2 */ -+ register8_t DATA3; /* LCD Data Register 3 */ -+ register8_t DATA4; /* LCD Data Register 4 */ -+ register8_t DATA5; /* LCD Data Register 5 */ -+ register8_t DATA6; /* LCD Data Register 6 */ -+ register8_t DATA7; /* LCD Data Register 7 */ -+ register8_t DATA8; /* LCD Data Register 8 */ -+ register8_t DATA9; /* LCD Data Register 9 */ -+ register8_t DATA10; /* LCD Data Register 10 */ -+ register8_t DATA11; /* LCD Data Register 11 */ -+ register8_t DATA12; /* LCD Data Register 12 */ -+ register8_t DATA13; /* LCD Data Register 13 */ -+ register8_t DATA14; /* LCD Data Register 14 */ -+ register8_t DATA15; /* LCD Data Register 15 */ -+ register8_t DATA16; /* LCD Data Register 16 */ -+ register8_t DATA17; /* LCD Data Register 17 */ -+ register8_t DATA18; /* LCD Data Register 18 */ -+ register8_t DATA19; /* LCD Data Register 19 */ -+} LCD_t; -+ -+/* LCD Blink Rate */ -+typedef enum LCD_BLINKRATE_enum -+{ -+ LCD_BLINKRATE_4Hz_gc = (0x00<<0), /* 4Hz Blink Rate */ -+ LCD_BLINKRATE_2Hz_gc = (0x01<<0), /* 2Hz Blink Rate */ -+ LCD_BLINKRATE_1Hz_gc = (0x02<<0), /* 1Hz Blink Rate */ -+ LCD_BLINKRATE_0Hz5_gc = (0x03<<0), /* 0.5Hz Blink Rate */ -+} LCD_BLINKRATE_t; -+ -+/* LCD Clock Divide */ -+typedef enum LCD_CLKDIV_enum -+{ -+ LCD_CLKDIV_DivBy1_gc = (0x00<<4), /* frame rate of 256 Hz */ -+ LCD_CLKDIV_DivBy2_gc = (0x01<<4), /* frame rate of 128 Hz */ -+ LCD_CLKDIV_DivBy3_gc = (0x02<<4), /* frame rate of 83.5 Hz */ -+ LCD_CLKDIV_DivBy4_gc = (0x03<<4), /* frame rate of 64 Hz */ -+ LCD_CLKDIV_DivBy5_gc = (0x04<<4), /* frame rate of 51.2 Hz */ -+ LCD_CLKDIV_DivBy6_gc = (0x05<<4), /* frame rate of 42.7 Hz */ -+ LCD_CLKDIV_DivBy7_gc = (0x06<<4), /* frame rate of 36.6 Hz */ -+ LCD_CLKDIV_DivBy8_gc = (0x07<<4), /* frame rate of 32 Hz */ -+} LCD_CLKDIV_t; -+ -+/* Duty Select */ -+typedef enum LCD_DUTY_enum -+{ -+ LCD_DUTY_1_4_gc = (0x00<<0), /* Duty=1/4, Bias=1/3, COM0:3 */ -+ LCD_DUTY_Static_gc = (0x01<<0), /* Duty=Static, Bias=Static, COM0 */ -+ LCD_DUTY_1_2_gc = (0x02<<0), /* Duty=1/2, Bias=1/3, COM0:1 */ -+ LCD_DUTY_1_3_gc = (0x03<<0), /* Duty=1/3, Bias=1/3, COM0:2 */ -+} LCD_DUTY_t; -+ -+/* LCD Prescaler Select */ -+typedef enum LCD_PRESC_enum -+{ -+ LCD_PRESC_8_gc = (0x00<<7), /* clk_lcd/8 */ -+ LCD_PRESC_16_gc = (0x01<<7), /* clk_lcd/16 */ -+} LCD_PRESC_t; -+ -+/* Type of Digit */ -+typedef enum LCD_TDG_enum -+{ -+ LCD_TDG_7S_3C_gc = (0x00<<6), /* 7-segment with 3 COMs */ -+ LCD_TDG_7S_4C_gc = (0x01<<6), /* 7-segment with 4 COMs */ -+ LCD_TDG_14S_4C_gc = (0x02<<6), /* 14-segment with 4 COMs */ -+ LCD_TDG_16S_3C_gc = (0x03<<6), /* 16-segment with 3 COMs */ -+} LCD_TDG_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t FUSEBYTE0; /* JTAG User ID */ -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+} NVM_FUSES_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* Timer Oscillator pin location */ -+typedef enum TOSCSEL_enum -+{ -+ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ -+ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -+} TOSCSEL_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -+} BOD_t; -+ -+/* BOD operation */ -+typedef enum BODACT_enum -+{ -+ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BODACT_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WDP_enum -+{ -+ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ -+ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ -+ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ -+ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ -+ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ -+ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ -+ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ -+ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ -+ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ -+ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ -+ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -+} WDP_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LOCKBIT - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ -+ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t USBCAL0; /* USB Calibration Byte 0 */ -+ register8_t USBCAL1; /* USB Calibration Byte 1 */ -+ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ -+ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ -+ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+ register8_t reserved_0x40; -+ register8_t reserved_0x41; -+ register8_t reserved_0x42; -+ register8_t reserved_0x43; -+ register8_t reserved_0x44; -+ register8_t reserved_0x45; -+ register8_t reserved_0x46; -+ register8_t reserved_0x47; -+} NVM_PROD_SIGNATURES_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define AES (*(AES_t *) 0x00C0) /* AES Module */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ -+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -+#define PORTG (*(PORT_t *) 0x06C0) /* I/O Ports */ -+#define PORTM (*(PORT_t *) 0x0760) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -+#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -+#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -+#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -+#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define LCD (*(LCD_t *) 0x0D00) /* LCD Controller */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -+#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -+#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -+#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -+#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+#define CLK_USBCTRL _SFR_MEM8(0x0044) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* DFLL - DFLL */ -+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -+#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -+#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPB _SFR_MEM8(0x0072) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPE _SFR_MEM8(0x0075) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_JTAGUID _SFR_MEM8(0x0094) -+#define MCU_MCUCR _SFR_MEM8(0x0096) -+#define MCU_ANAINIT _SFR_MEM8(0x0097) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_AWEXLOCK _SFR_MEM8(0x0099) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) -+ -+/* AES - AES Module */ -+#define AES_CTRL _SFR_MEM8(0x00C0) -+#define AES_STATUS _SFR_MEM8(0x00C1) -+#define AES_STATE _SFR_MEM8(0x00C2) -+#define AES_KEY _SFR_MEM8(0x00C3) -+#define AES_INTCTRL _SFR_MEM8(0x00C4) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* DMA - DMA Controller */ -+#define DMA_CTRL _SFR_MEM8(0x0100) -+#define DMA_INTFLAGS _SFR_MEM8(0x0103) -+#define DMA_STATUS _SFR_MEM8(0x0104) -+#define DMA_TEMP _SFR_MEM16(0x0106) -+#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -+#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -+#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -+#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -+#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -+#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -+#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -+#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -+#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -+#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -+#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -+#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -+#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -+#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -+#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -+#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -+#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -+#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -+#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -+#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCA_CTRLA _SFR_MEM8(0x0200) -+#define ADCA_CTRLB _SFR_MEM8(0x0201) -+#define ADCA_REFCTRL _SFR_MEM8(0x0202) -+#define ADCA_EVCTRL _SFR_MEM8(0x0203) -+#define ADCA_PRESCALER _SFR_MEM8(0x0204) -+#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -+#define ADCA_TEMP _SFR_MEM8(0x0207) -+#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) -+#define ADCA_CAL _SFR_MEM16(0x020C) -+#define ADCA_CH0RES _SFR_MEM16(0x0210) -+#define ADCA_CMP _SFR_MEM16(0x0218) -+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -+#define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCB_CTRLA _SFR_MEM8(0x0240) -+#define ADCB_CTRLB _SFR_MEM8(0x0241) -+#define ADCB_REFCTRL _SFR_MEM8(0x0242) -+#define ADCB_EVCTRL _SFR_MEM8(0x0243) -+#define ADCB_PRESCALER _SFR_MEM8(0x0244) -+#define ADCB_INTFLAGS _SFR_MEM8(0x0246) -+#define ADCB_TEMP _SFR_MEM8(0x0247) -+#define ADCB_SAMPCTRL _SFR_MEM8(0x0248) -+#define ADCB_CAL _SFR_MEM16(0x024C) -+#define ADCB_CH0RES _SFR_MEM16(0x0250) -+#define ADCB_CMP _SFR_MEM16(0x0258) -+#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) -+#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) -+#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) -+#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) -+#define ADCB_CH0_RES _SFR_MEM16(0x0264) -+#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) -+ -+/* AC - Analog Comparator */ -+#define ACA_AC0CTRL _SFR_MEM8(0x0380) -+#define ACA_AC1CTRL _SFR_MEM8(0x0381) -+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -+#define ACA_CTRLA _SFR_MEM8(0x0384) -+#define ACA_CTRLB _SFR_MEM8(0x0385) -+#define ACA_WINCTRL _SFR_MEM8(0x0386) -+#define ACA_STATUS _SFR_MEM8(0x0387) -+#define ACA_CURRCTRL _SFR_MEM8(0x0388) -+#define ACA_CURRCALIB _SFR_MEM8(0x0389) -+ -+/* AC - Analog Comparator */ -+#define ACB_AC0CTRL _SFR_MEM8(0x0390) -+#define ACB_AC1CTRL _SFR_MEM8(0x0391) -+#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -+#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -+#define ACB_CTRLA _SFR_MEM8(0x0394) -+#define ACB_CTRLB _SFR_MEM8(0x0395) -+#define ACB_WINCTRL _SFR_MEM8(0x0396) -+#define ACB_STATUS _SFR_MEM8(0x0397) -+#define ACB_CURRCTRL _SFR_MEM8(0x0398) -+#define ACB_CURRCALIB _SFR_MEM8(0x0399) -+ -+/* RTC - Real-Time Counter */ -+#define RTC_CTRL _SFR_MEM8(0x0400) -+#define RTC_STATUS _SFR_MEM8(0x0401) -+#define RTC_INTCTRL _SFR_MEM8(0x0402) -+#define RTC_INTFLAGS _SFR_MEM8(0x0403) -+#define RTC_TEMP _SFR_MEM8(0x0404) -+#define RTC_CNT _SFR_MEM16(0x0408) -+#define RTC_PER _SFR_MEM16(0x040A) -+#define RTC_COMP _SFR_MEM16(0x040C) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+ -+/* USB - Universal Serial Bus */ -+#define USB_CTRLA _SFR_MEM8(0x04C0) -+#define USB_CTRLB _SFR_MEM8(0x04C1) -+#define USB_STATUS _SFR_MEM8(0x04C2) -+#define USB_ADDR _SFR_MEM8(0x04C3) -+#define USB_FIFOWP _SFR_MEM8(0x04C4) -+#define USB_FIFORP _SFR_MEM8(0x04C5) -+#define USB_EPPTR _SFR_MEM16(0x04C6) -+#define USB_INTCTRLA _SFR_MEM8(0x04C8) -+#define USB_INTCTRLB _SFR_MEM8(0x04C9) -+#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -+#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -+#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -+#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -+#define USB_CAL0 _SFR_MEM8(0x04FA) -+#define USB_CAL1 _SFR_MEM8(0x04FB) -+ -+/* PORT - I/O Ports */ -+#define PORTA_DIR _SFR_MEM8(0x0600) -+#define PORTA_DIRSET _SFR_MEM8(0x0601) -+#define PORTA_DIRCLR _SFR_MEM8(0x0602) -+#define PORTA_DIRTGL _SFR_MEM8(0x0603) -+#define PORTA_OUT _SFR_MEM8(0x0604) -+#define PORTA_OUTSET _SFR_MEM8(0x0605) -+#define PORTA_OUTCLR _SFR_MEM8(0x0606) -+#define PORTA_OUTTGL _SFR_MEM8(0x0607) -+#define PORTA_IN _SFR_MEM8(0x0608) -+#define PORTA_INTCTRL _SFR_MEM8(0x0609) -+#define PORTA_INT0MASK _SFR_MEM8(0x060A) -+#define PORTA_INT1MASK _SFR_MEM8(0x060B) -+#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_REMAP _SFR_MEM8(0x060E) -+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -+ -+/* PORT - I/O Ports */ -+#define PORTB_DIR _SFR_MEM8(0x0620) -+#define PORTB_DIRSET _SFR_MEM8(0x0621) -+#define PORTB_DIRCLR _SFR_MEM8(0x0622) -+#define PORTB_DIRTGL _SFR_MEM8(0x0623) -+#define PORTB_OUT _SFR_MEM8(0x0624) -+#define PORTB_OUTSET _SFR_MEM8(0x0625) -+#define PORTB_OUTCLR _SFR_MEM8(0x0626) -+#define PORTB_OUTTGL _SFR_MEM8(0x0627) -+#define PORTB_IN _SFR_MEM8(0x0628) -+#define PORTB_INTCTRL _SFR_MEM8(0x0629) -+#define PORTB_INT0MASK _SFR_MEM8(0x062A) -+#define PORTB_INT1MASK _SFR_MEM8(0x062B) -+#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -+#define PORTB_REMAP _SFR_MEM8(0x062E) -+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INT0MASK _SFR_MEM8(0x064A) -+#define PORTC_INT1MASK _SFR_MEM8(0x064B) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INT0MASK _SFR_MEM8(0x066A) -+#define PORTD_INT1MASK _SFR_MEM8(0x066B) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTE_DIR _SFR_MEM8(0x0680) -+#define PORTE_DIRSET _SFR_MEM8(0x0681) -+#define PORTE_DIRCLR _SFR_MEM8(0x0682) -+#define PORTE_DIRTGL _SFR_MEM8(0x0683) -+#define PORTE_OUT _SFR_MEM8(0x0684) -+#define PORTE_OUTSET _SFR_MEM8(0x0685) -+#define PORTE_OUTCLR _SFR_MEM8(0x0686) -+#define PORTE_OUTTGL _SFR_MEM8(0x0687) -+#define PORTE_IN _SFR_MEM8(0x0688) -+#define PORTE_INTCTRL _SFR_MEM8(0x0689) -+#define PORTE_INT0MASK _SFR_MEM8(0x068A) -+#define PORTE_INT1MASK _SFR_MEM8(0x068B) -+#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -+#define PORTE_REMAP _SFR_MEM8(0x068E) -+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) -+ -+/* PORT - I/O Ports */ -+#define PORTG_DIR _SFR_MEM8(0x06C0) -+#define PORTG_DIRSET _SFR_MEM8(0x06C1) -+#define PORTG_DIRCLR _SFR_MEM8(0x06C2) -+#define PORTG_DIRTGL _SFR_MEM8(0x06C3) -+#define PORTG_OUT _SFR_MEM8(0x06C4) -+#define PORTG_OUTSET _SFR_MEM8(0x06C5) -+#define PORTG_OUTCLR _SFR_MEM8(0x06C6) -+#define PORTG_OUTTGL _SFR_MEM8(0x06C7) -+#define PORTG_IN _SFR_MEM8(0x06C8) -+#define PORTG_INTCTRL _SFR_MEM8(0x06C9) -+#define PORTG_INT0MASK _SFR_MEM8(0x06CA) -+#define PORTG_INT1MASK _SFR_MEM8(0x06CB) -+#define PORTG_INTFLAGS _SFR_MEM8(0x06CC) -+#define PORTG_REMAP _SFR_MEM8(0x06CE) -+#define PORTG_PIN0CTRL _SFR_MEM8(0x06D0) -+#define PORTG_PIN1CTRL _SFR_MEM8(0x06D1) -+#define PORTG_PIN2CTRL _SFR_MEM8(0x06D2) -+#define PORTG_PIN3CTRL _SFR_MEM8(0x06D3) -+#define PORTG_PIN4CTRL _SFR_MEM8(0x06D4) -+#define PORTG_PIN5CTRL _SFR_MEM8(0x06D5) -+#define PORTG_PIN6CTRL _SFR_MEM8(0x06D6) -+#define PORTG_PIN7CTRL _SFR_MEM8(0x06D7) -+ -+/* PORT - I/O Ports */ -+#define PORTM_DIR _SFR_MEM8(0x0760) -+#define PORTM_DIRSET _SFR_MEM8(0x0761) -+#define PORTM_DIRCLR _SFR_MEM8(0x0762) -+#define PORTM_DIRTGL _SFR_MEM8(0x0763) -+#define PORTM_OUT _SFR_MEM8(0x0764) -+#define PORTM_OUTSET _SFR_MEM8(0x0765) -+#define PORTM_OUTCLR _SFR_MEM8(0x0766) -+#define PORTM_OUTTGL _SFR_MEM8(0x0767) -+#define PORTM_IN _SFR_MEM8(0x0768) -+#define PORTM_INTCTRL _SFR_MEM8(0x0769) -+#define PORTM_INT0MASK _SFR_MEM8(0x076A) -+#define PORTM_INT1MASK _SFR_MEM8(0x076B) -+#define PORTM_INTFLAGS _SFR_MEM8(0x076C) -+#define PORTM_REMAP _SFR_MEM8(0x076E) -+#define PORTM_PIN0CTRL _SFR_MEM8(0x0770) -+#define PORTM_PIN1CTRL _SFR_MEM8(0x0771) -+#define PORTM_PIN2CTRL _SFR_MEM8(0x0772) -+#define PORTM_PIN3CTRL _SFR_MEM8(0x0773) -+#define PORTM_PIN4CTRL _SFR_MEM8(0x0774) -+#define PORTM_PIN5CTRL _SFR_MEM8(0x0775) -+#define PORTM_PIN6CTRL _SFR_MEM8(0x0776) -+#define PORTM_PIN7CTRL _SFR_MEM8(0x0777) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -+#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCC0_CTRLA _SFR_MEM8(0x0800) -+#define TCC0_CTRLB _SFR_MEM8(0x0801) -+#define TCC0_CTRLC _SFR_MEM8(0x0802) -+#define TCC0_CTRLD _SFR_MEM8(0x0803) -+#define TCC0_CTRLE _SFR_MEM8(0x0804) -+#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -+#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -+#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -+#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC0_TEMP _SFR_MEM8(0x080F) -+#define TCC0_CNT _SFR_MEM16(0x0820) -+#define TCC0_PER _SFR_MEM16(0x0826) -+#define TCC0_CCA _SFR_MEM16(0x0828) -+#define TCC0_CCB _SFR_MEM16(0x082A) -+#define TCC0_CCC _SFR_MEM16(0x082C) -+#define TCC0_CCD _SFR_MEM16(0x082E) -+#define TCC0_PERBUF _SFR_MEM16(0x0836) -+#define TCC0_CCABUF _SFR_MEM16(0x0838) -+#define TCC0_CCBBUF _SFR_MEM16(0x083A) -+#define TCC0_CCCBUF _SFR_MEM16(0x083C) -+#define TCC0_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCC2_CTRLA _SFR_MEM8(0x0800) -+#define TCC2_CTRLB _SFR_MEM8(0x0801) -+#define TCC2_CTRLC _SFR_MEM8(0x0802) -+#define TCC2_CTRLE _SFR_MEM8(0x0804) -+#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC2_CTRLF _SFR_MEM8(0x0809) -+#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC2_LCNT _SFR_MEM8(0x0820) -+#define TCC2_HCNT _SFR_MEM8(0x0821) -+#define TCC2_LPER _SFR_MEM8(0x0826) -+#define TCC2_HPER _SFR_MEM8(0x0827) -+#define TCC2_LCMPA _SFR_MEM8(0x0828) -+#define TCC2_HCMPA _SFR_MEM8(0x0829) -+#define TCC2_LCMPB _SFR_MEM8(0x082A) -+#define TCC2_HCMPB _SFR_MEM8(0x082B) -+#define TCC2_LCMPC _SFR_MEM8(0x082C) -+#define TCC2_HCMPC _SFR_MEM8(0x082D) -+#define TCC2_LCMPD _SFR_MEM8(0x082E) -+#define TCC2_HCMPD _SFR_MEM8(0x082F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCC1_CTRLA _SFR_MEM8(0x0840) -+#define TCC1_CTRLB _SFR_MEM8(0x0841) -+#define TCC1_CTRLC _SFR_MEM8(0x0842) -+#define TCC1_CTRLD _SFR_MEM8(0x0843) -+#define TCC1_CTRLE _SFR_MEM8(0x0844) -+#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -+#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -+#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -+#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC1_TEMP _SFR_MEM8(0x084F) -+#define TCC1_CNT _SFR_MEM16(0x0860) -+#define TCC1_PER _SFR_MEM16(0x0866) -+#define TCC1_CCA _SFR_MEM16(0x0868) -+#define TCC1_CCB _SFR_MEM16(0x086A) -+#define TCC1_PERBUF _SFR_MEM16(0x0876) -+#define TCC1_CCABUF _SFR_MEM16(0x0878) -+#define TCC1_CCBBUF _SFR_MEM16(0x087A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXC_CTRL _SFR_MEM8(0x0880) -+#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -+#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -+#define AWEXC_STATUS _SFR_MEM8(0x0884) -+#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -+#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -+#define AWEXC_DTLS _SFR_MEM8(0x0888) -+#define AWEXC_DTHS _SFR_MEM8(0x0889) -+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x0890) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08A0) -+#define USARTC0_STATUS _SFR_MEM8(0x08A1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -+#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -+#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIC_CTRL _SFR_MEM8(0x08C0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -+#define SPIC_STATUS _SFR_MEM8(0x08C2) -+#define SPIC_DATA _SFR_MEM8(0x08C3) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCE0_CTRLA _SFR_MEM8(0x0A00) -+#define TCE0_CTRLB _SFR_MEM8(0x0A01) -+#define TCE0_CTRLC _SFR_MEM8(0x0A02) -+#define TCE0_CTRLD _SFR_MEM8(0x0A03) -+#define TCE0_CTRLE _SFR_MEM8(0x0A04) -+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE0_TEMP _SFR_MEM8(0x0A0F) -+#define TCE0_CNT _SFR_MEM16(0x0A20) -+#define TCE0_PER _SFR_MEM16(0x0A26) -+#define TCE0_CCA _SFR_MEM16(0x0A28) -+#define TCE0_CCB _SFR_MEM16(0x0A2A) -+#define TCE0_CCC _SFR_MEM16(0x0A2C) -+#define TCE0_CCD _SFR_MEM16(0x0A2E) -+#define TCE0_PERBUF _SFR_MEM16(0x0A36) -+#define TCE0_CCABUF _SFR_MEM16(0x0A38) -+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCE2_CTRLA _SFR_MEM8(0x0A00) -+#define TCE2_CTRLB _SFR_MEM8(0x0A01) -+#define TCE2_CTRLC _SFR_MEM8(0x0A02) -+#define TCE2_CTRLE _SFR_MEM8(0x0A04) -+#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE2_CTRLF _SFR_MEM8(0x0A09) -+#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE2_LCNT _SFR_MEM8(0x0A20) -+#define TCE2_HCNT _SFR_MEM8(0x0A21) -+#define TCE2_LPER _SFR_MEM8(0x0A26) -+#define TCE2_HPER _SFR_MEM8(0x0A27) -+#define TCE2_LCMPA _SFR_MEM8(0x0A28) -+#define TCE2_HCMPA _SFR_MEM8(0x0A29) -+#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -+#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -+#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -+#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -+#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -+#define TCE2_HCMPD _SFR_MEM8(0x0A2F) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE0_DATA _SFR_MEM8(0x0AA0) -+#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -+#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -+#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -+#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -+#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -+#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) -+ -+/* LCD - LCD Controller */ -+#define LCD_CTRLA _SFR_MEM8(0x0D00) -+#define LCD_CTRLB _SFR_MEM8(0x0D01) -+#define LCD_CTRLC _SFR_MEM8(0x0D02) -+#define LCD_INTCTRL _SFR_MEM8(0x0D03) -+#define LCD_INTFLAG _SFR_MEM8(0x0D04) -+#define LCD_CTRLD _SFR_MEM8(0x0D05) -+#define LCD_CTRLE _SFR_MEM8(0x0D06) -+#define LCD_CTRLF _SFR_MEM8(0x0D07) -+#define LCD_CTRLG _SFR_MEM8(0x0D08) -+#define LCD_CTRLH _SFR_MEM8(0x0D09) -+#define LCD_DATA0 _SFR_MEM8(0x0D10) -+#define LCD_DATA1 _SFR_MEM8(0x0D11) -+#define LCD_DATA2 _SFR_MEM8(0x0D12) -+#define LCD_DATA3 _SFR_MEM8(0x0D13) -+#define LCD_DATA4 _SFR_MEM8(0x0D14) -+#define LCD_DATA5 _SFR_MEM8(0x0D15) -+#define LCD_DATA6 _SFR_MEM8(0x0D16) -+#define LCD_DATA7 _SFR_MEM8(0x0D17) -+#define LCD_DATA8 _SFR_MEM8(0x0D18) -+#define LCD_DATA9 _SFR_MEM8(0x0D19) -+#define LCD_DATA10 _SFR_MEM8(0x0D1A) -+#define LCD_DATA11 _SFR_MEM8(0x0D1B) -+#define LCD_DATA12 _SFR_MEM8(0x0D1C) -+#define LCD_DATA13 _SFR_MEM8(0x0D1D) -+#define LCD_DATA14 _SFR_MEM8(0x0D1E) -+#define LCD_DATA15 _SFR_MEM8(0x0D1F) -+#define LCD_DATA16 _SFR_MEM8(0x0D20) -+#define LCD_DATA17 _SFR_MEM8(0x0D21) -+#define LCD_DATA18 _SFR_MEM8(0x0D22) -+#define LCD_DATA19 _SFR_MEM8(0x0D23) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* VPORT - Virtual Ports */ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* CLK.USBCTRL bit masks and bit positions */ -+#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -+#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -+#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -+#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -+#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -+#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -+#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -+#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ -+ -+#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -+#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -+#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ -+ -+#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ -+#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -+#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -+#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ -+ -+#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ -+ -+#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -+#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ -+ -+/* PR - Power Reduction */ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_LCD_bm 0x80 /* LCD Module bit mask. */ -+#define PR_LCD_bp 7 /* LCD Module bit position. */ -+ -+#define PR_USB_bm 0x40 /* USB bit mask. */ -+#define PR_USB_bp 6 /* USB bit position. */ -+ -+#define PR_AES_bm 0x10 /* AES bit mask. */ -+#define PR_AES_bp 4 /* AES bit position. */ -+ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -+#define PR_DMA_bp 0 /* DMA-Controller bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPB bit masks and bit positions */ -+/* PR_ADC Predefined. */ -+/* PR_ADC Predefined. */ -+ -+/* PR_AC Predefined. */ -+/* PR_AC Predefined. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -+#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ -+ -+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -+ -+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ -+ -+/* PR.PRPE bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.MCUCR bit masks and bit positions */ -+#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -+#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ -+ -+/* MCU.ANAINIT bit masks and bit positions */ -+#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -+#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -+#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -+#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -+#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -+#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ -+ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -+#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ -+ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.AWEXLOCK bit masks and bit positions */ -+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* PORTCFG - Port Configuration */ -+/* PORTCFG.VPCTRLA bit masks and bit positions */ -+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ -+ -+/* PORTCFG.VPCTRLB bit masks and bit positions */ -+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ -+ -+/* PORTCFG.CLKEVOUT bit masks and bit positions */ -+#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ -+ -+#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -+#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -+#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -+#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -+#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -+#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ -+ -+#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -+#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ -+ -+#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -+#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ -+ -+/* PORTCFG.EVOUTSEL bit masks and bit positions */ -+#define PORTCFG_EVOUTSEL_bm 0x04 /* Event Output Select bit mask. */ -+#define PORTCFG_EVOUTSEL_bp 2 /* Event Output Select bit position. */ -+ -+/* AES - AES Module */ -+/* AES.CTRL bit masks and bit positions */ -+#define AES_START_bm 0x80 /* Start/Run bit mask. */ -+#define AES_START_bp 7 /* Start/Run bit position. */ -+ -+#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -+#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ -+ -+#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -+#define AES_RESET_bp 5 /* AES Software Reset bit position. */ -+ -+#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -+#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ -+ -+#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -+#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ -+ -+/* AES.STATUS bit masks and bit positions */ -+#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -+#define AES_ERROR_bp 7 /* AES Error bit position. */ -+ -+#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -+#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ -+ -+/* AES.INTCTRL bit masks and bit positions */ -+#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -+#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* DMA - DMA Controller */ -+/* DMA_CH.CTRLA bit masks and bit positions */ -+#define DMA_CH_CHEN_bm 0x80 /* Channel Enable bit mask. */ -+#define DMA_CH_CHEN_bp 7 /* Channel Enable bit position. */ -+ -+#define DMA_CH_CHRST_bm 0x40 /* Channel Software Reset bit mask. */ -+#define DMA_CH_CHRST_bp 6 /* Channel Software Reset bit position. */ -+ -+#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -+#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ -+ -+#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -+#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ -+ -+#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -+#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ -+ -+#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -+#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -+#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -+#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -+#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -+#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ -+ -+/* DMA_CH.CTRLB bit masks and bit positions */ -+#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -+#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ -+ -+#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -+#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ -+ -+#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -+#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ -+ -+#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -+#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -+#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -+#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -+#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -+#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ -+ -+#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -+#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -+#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -+#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -+#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -+#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ -+ -+/* DMA_CH.ADDRCTRL bit masks and bit positions */ -+#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -+#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -+#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -+#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -+#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -+#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ -+ -+#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -+#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -+#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -+#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -+#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -+#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ -+ -+#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -+#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -+#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -+#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -+#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -+#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ -+ -+#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -+#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -+#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -+#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -+#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -+#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ -+ -+/* DMA_CH.TRIGSRC bit masks and bit positions */ -+#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -+#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -+#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -+#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -+#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -+#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -+#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -+#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -+#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -+#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -+#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -+#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -+#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -+#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -+#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -+#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -+#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -+#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ -+ -+/* DMA.CTRL bit masks and bit positions */ -+#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -+#define DMA_ENABLE_bp 7 /* Enable bit position. */ -+ -+#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -+#define DMA_RESET_bp 6 /* Software Reset bit position. */ -+ -+#define DMA_DBUFMODE_bm 0x04 /* Double Buffering Mode bit mask. */ -+#define DMA_DBUFMODE_bp 2 /* Double Buffering Mode bit position. */ -+ -+#define DMA_PRIMODE_bm 0x01 /* Channel Priority Mode bit mask. */ -+#define DMA_PRIMODE_bp 0 /* Channel Priority Mode bit position. */ -+ -+/* DMA.INTFLAGS bit masks and bit positions */ -+#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ -+ -+/* DMA.STATUS bit masks and bit positions */ -+#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -+#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ -+ -+#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -+#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ -+ -+#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -+#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ -+ -+#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -+#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0x7F /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ -+ -+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ -+ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -+#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -+#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -+#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -+#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -+#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -+#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -+#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -+#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -+#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ -+ -+#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */ -+#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */ -+#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -+#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */ -+#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -+#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */ -+#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -+#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */ -+#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -+#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -+#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* ADC.SAMPCTRL bit masks and bit positions */ -+#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ -+#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ -+#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ -+#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ -+#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ -+#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ -+#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ -+#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ -+#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ -+#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ -+#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ -+#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ -+#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ -+#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* AC.CURRCTRL bit masks and bit positions */ -+#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ -+#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ -+ -+#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ -+#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ -+ -+#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ -+#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ -+ -+#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ -+#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ -+ -+/* AC.CURRCALIB bit masks and bit positions */ -+#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ -+#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ -+#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ -+#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ -+#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ -+#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ -+#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ -+#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ -+#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ -+#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ -+ -+/* RTC - Real-Time Counter */ -+/* RTC.CTRL bit masks and bit positions */ -+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ -+ -+/* RTC.STATUS bit masks and bit positions */ -+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC.INTCTRL bit masks and bit positions */ -+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC.INTFLAGS bit masks and bit positions */ -+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* USB - USB */ -+/* USB_EP.STATUS bit masks and bit positions */ -+#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -+#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ -+ -+#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -+#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ -+ -+#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -+#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ -+ -+#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -+#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ -+ -+#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -+#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ -+ -+#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -+#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ -+ -+#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -+#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ -+ -+#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -+#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ -+ -+#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ -+ -+#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ -+ -+#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -+#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ -+ -+/* USB_EP.CTRL bit masks and bit positions */ -+#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -+#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -+#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -+#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -+#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -+#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ -+ -+#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -+#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ -+ -+#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -+#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ -+ -+#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -+#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ -+ -+#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -+#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ -+ -+#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -+#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -+#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -+#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -+#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -+#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -+#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -+#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ -+ -+/* USB_EP.CNT bit masks and bit positions */ -+#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -+#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ -+ -+/* USB.CTRLA bit masks and bit positions */ -+#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -+#define USB_ENABLE_bp 7 /* USB Enable bit position. */ -+ -+#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -+#define USB_SPEED_bp 6 /* Speed Select bit position. */ -+ -+#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -+#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ -+ -+#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -+#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ -+ -+#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -+#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -+#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -+#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -+#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -+#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -+#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -+#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -+#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -+#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ -+ -+/* USB.CTRLB bit masks and bit positions */ -+#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -+#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ -+ -+#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -+#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ -+ -+#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -+#define USB_GNACK_bp 1 /* Global NACK bit position. */ -+ -+#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -+#define USB_ATTACH_bp 0 /* Attach bit position. */ -+ -+/* USB.STATUS bit masks and bit positions */ -+#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -+#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ -+ -+#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -+#define USB_RESUME_bp 2 /* Resume bit position. */ -+ -+#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -+#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ -+ -+#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -+#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ -+ -+/* USB.ADDR bit masks and bit positions */ -+#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -+#define USB_ADDR_gp 0 /* Device Address group position. */ -+#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -+#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -+#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -+#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -+#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -+#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -+#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -+#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -+#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -+#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -+#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -+#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -+#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -+#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ -+ -+/* USB.FIFOWP bit masks and bit positions */ -+#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -+#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -+#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -+#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -+#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -+#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -+#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -+#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -+#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -+#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -+#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -+#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ -+ -+/* USB.FIFORP bit masks and bit positions */ -+#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -+#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -+#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -+#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -+#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -+#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -+#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -+#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -+#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -+#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -+#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -+#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ -+ -+/* USB.INTCTRLA bit masks and bit positions */ -+#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -+#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ -+ -+#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -+#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ -+ -+#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -+#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ -+ -+#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -+#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ -+ -+#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* USB.INTCTRLB bit masks and bit positions */ -+#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -+#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ -+ -+#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -+#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ -+ -+/* USB.INTFLAGSACLR bit masks and bit positions */ -+#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -+#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ -+ -+#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -+#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ -+ -+#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -+#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ -+ -+#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -+#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ -+ -+#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -+#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ -+ -+#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -+#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ -+ -+#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -+#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ -+ -+#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -+#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSASET bit masks and bit positions */ -+/* USB_SOFIF Predefined. */ -+/* USB_SOFIF Predefined. */ -+ -+/* USB_SUSPENDIF Predefined. */ -+/* USB_SUSPENDIF Predefined. */ -+ -+/* USB_RESUMEIF Predefined. */ -+/* USB_RESUMEIF Predefined. */ -+ -+/* USB_RSTIF Predefined. */ -+/* USB_RSTIF Predefined. */ -+ -+/* USB_CRCIF Predefined. */ -+/* USB_CRCIF Predefined. */ -+ -+/* USB_UNFIF Predefined. */ -+/* USB_UNFIF Predefined. */ -+ -+/* USB_OVFIF Predefined. */ -+/* USB_OVFIF Predefined. */ -+ -+/* USB_STALLIF Predefined. */ -+/* USB_STALLIF Predefined. */ -+ -+/* USB.INTFLAGSBCLR bit masks and bit positions */ -+#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -+#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ -+ -+#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -+#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSBSET bit masks and bit positions */ -+/* USB_TRNIF Predefined. */ -+/* USB_TRNIF Predefined. */ -+ -+/* USB_SETUPIF Predefined. */ -+/* USB_SETUPIF Predefined. */ -+ -+/* PORT - I/O Port Configuration */ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ -+ -+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -+#define PORT_SPI_bp 5 /* SPI bit position. */ -+ -+#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -+#define PORT_USART0_bp 4 /* USART0 bit position. */ -+ -+#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -+#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ -+ -+#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -+#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ -+ -+#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -+#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ -+ -+#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -+#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ -+ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC0.CTRLA bit masks and bit positions */ -+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC0.CTRLB bit masks and bit positions */ -+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ -+ -+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ -+ -+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC0.CTRLC bit masks and bit positions */ -+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ -+ -+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ -+ -+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC0.CTRLD bit masks and bit positions */ -+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC0_EVACT_gp 5 /* Event Action group position. */ -+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC0.CTRLE bit masks and bit positions */ -+#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC0.INTCTRLA bit masks and bit positions */ -+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC0.INTCTRLB bit masks and bit positions */ -+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ -+ -+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ -+ -+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC0.CTRLFCLR bit masks and bit positions */ -+#define TC0_CMD_gm 0x0C /* Command group mask. */ -+#define TC0_CMD_gp 2 /* Command group position. */ -+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC0_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC0_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC0_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC0.CTRLFSET bit masks and bit positions */ -+/* TC0_CMD Predefined. */ -+/* TC0_CMD Predefined. */ -+ -+/* TC0_LUPD Predefined. */ -+/* TC0_LUPD Predefined. */ -+ -+/* TC0_DIR Predefined. */ -+/* TC0_DIR Predefined. */ -+ -+/* TC0.CTRLGCLR bit masks and bit positions */ -+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ -+ -+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ -+ -+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC0.CTRLGSET bit masks and bit positions */ -+/* TC0_CCDBV Predefined. */ -+/* TC0_CCDBV Predefined. */ -+ -+/* TC0_CCCBV Predefined. */ -+/* TC0_CCCBV Predefined. */ -+ -+/* TC0_CCBBV Predefined. */ -+/* TC0_CCBBV Predefined. */ -+ -+/* TC0_CCABV Predefined. */ -+/* TC0_CCABV Predefined. */ -+ -+/* TC0_PERBV Predefined. */ -+/* TC0_PERBV Predefined. */ -+ -+/* TC0.INTFLAGS bit masks and bit positions */ -+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ -+ -+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ -+ -+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC1.CTRLA bit masks and bit positions */ -+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC1.CTRLB bit masks and bit positions */ -+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC1.CTRLC bit masks and bit positions */ -+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC1.CTRLD bit masks and bit positions */ -+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC1_EVACT_gp 5 /* Event Action group position. */ -+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC1.CTRLE bit masks and bit positions */ -+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ -+ -+/* TC1.INTCTRLA bit masks and bit positions */ -+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC1.INTCTRLB bit masks and bit positions */ -+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC1.CTRLFCLR bit masks and bit positions */ -+#define TC1_CMD_gm 0x0C /* Command group mask. */ -+#define TC1_CMD_gp 2 /* Command group position. */ -+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC1_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC1_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC1_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC1.CTRLFSET bit masks and bit positions */ -+/* TC1_CMD Predefined. */ -+/* TC1_CMD Predefined. */ -+ -+/* TC1_LUPD Predefined. */ -+/* TC1_LUPD Predefined. */ -+ -+/* TC1_DIR Predefined. */ -+/* TC1_DIR Predefined. */ -+ -+/* TC1.CTRLGCLR bit masks and bit positions */ -+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC1.CTRLGSET bit masks and bit positions */ -+/* TC1_CCBBV Predefined. */ -+/* TC1_CCBBV Predefined. */ -+ -+/* TC1_CCABV Predefined. */ -+/* TC1_CCABV Predefined. */ -+ -+/* TC1_PERBV Predefined. */ -+/* TC1_PERBV Predefined. */ -+ -+/* TC1.INTFLAGS bit masks and bit positions */ -+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+/* TC2.CTRLA bit masks and bit positions */ -+#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC2.CTRLB bit masks and bit positions */ -+#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -+#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ -+ -+#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -+#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ -+ -+#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -+#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ -+ -+#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -+#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ -+ -+#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -+#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ -+ -+#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -+#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ -+ -+#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -+#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ -+ -+#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -+#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ -+ -+/* TC2.CTRLC bit masks and bit positions */ -+#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -+#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ -+ -+#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -+#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ -+ -+#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -+#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ -+ -+#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -+#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ -+ -+#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -+#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ -+ -+#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -+#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ -+ -+#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -+#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ -+ -+#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -+#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ -+ -+/* TC2.CTRLE bit masks and bit positions */ -+#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC2.INTCTRLA bit masks and bit positions */ -+#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -+#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -+#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -+#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -+#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -+#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ -+ -+#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -+#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -+#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -+#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -+#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -+#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ -+ -+/* TC2.INTCTRLB bit masks and bit positions */ -+#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -+#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -+#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -+#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -+#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -+#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -+#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -+#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -+#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -+#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -+#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -+#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -+#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -+#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -+#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -+#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -+#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -+#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -+#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -+#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -+#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ -+ -+/* TC2.CTRLF bit masks and bit positions */ -+#define TC2_CMD_gm 0x0C /* Command group mask. */ -+#define TC2_CMD_gp 2 /* Command group position. */ -+#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC2_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -+#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -+#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -+#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -+#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -+#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ -+ -+/* TC2.INTFLAGS bit masks and bit positions */ -+#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -+#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ -+ -+#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -+#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ -+ -+#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -+#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ -+ -+#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -+#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ -+ -+#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ -+ -+#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ -+ -+/* AWEX - Timer/Counter Advanced Waveform Extension */ -+/* AWEX.CTRL bit masks and bit positions */ -+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ -+ -+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ -+ -+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ -+ -+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ -+ -+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ -+ -+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ -+ -+/* AWEX.FDCTRL bit masks and bit positions */ -+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ -+ -+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ -+ -+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ -+ -+/* AWEX.STATUS bit masks and bit positions */ -+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ -+ -+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ -+ -+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ -+ -+/* AWEX.STATUSSET bit masks and bit positions */ -+/* AWEX_FDF Predefined. */ -+/* AWEX_FDF Predefined. */ -+ -+/* AWEX_DTHSBUFV Predefined. */ -+/* AWEX_DTHSBUFV Predefined. */ -+ -+/* AWEX_DTLSBUFV Predefined. */ -+/* AWEX_DTLSBUFV Predefined. */ -+ -+/* HIRES - Timer/Counter High-Resolution Extension */ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+/* LCD - LCD Controller */ -+/* LCD.CTRLA bit masks and bit positions */ -+#define LCD_ENABLE_bm 0x80 /* LCD Enable bit mask. */ -+#define LCD_ENABLE_bp 7 /* LCD Enable bit position. */ -+ -+#define LCD_XBIAS_bm 0x40 /* External Register Bias Generation bit mask. */ -+#define LCD_XBIAS_bp 6 /* External Register Bias Generation bit position. */ -+ -+#define LCD_DATCLK_bm 0x20 /* Data Register Lock bit mask. */ -+#define LCD_DATCLK_bp 5 /* Data Register Lock bit position. */ -+ -+#define LCD_COMSWP_bm 0x10 /* Common Bus Swap bit mask. */ -+#define LCD_COMSWP_bp 4 /* Common Bus Swap bit position. */ -+ -+#define LCD_SEGSWP_bm 0x08 /* Segment Bus Swap bit mask. */ -+#define LCD_SEGSWP_bp 3 /* Segment Bus Swap bit position. */ -+ -+#define LCD_CLRDT_bm 0x04 /* Clear Data Register bit mask. */ -+#define LCD_CLRDT_bp 2 /* Clear Data Register bit position. */ -+ -+#define LCD_SEGON_bm 0x02 /* Segments On bit mask. */ -+#define LCD_SEGON_bp 1 /* Segments On bit position. */ -+ -+#define LCD_BLANK_bm 0x01 /* Blanking Display Mode bit mask. */ -+#define LCD_BLANK_bp 0 /* Blanking Display Mode bit position. */ -+ -+/* LCD.CTRLB bit masks and bit positions */ -+#define LCD_PRESC_bm 0x80 /* LCD Prescaler Select bit mask. */ -+#define LCD_PRESC_bp 7 /* LCD Prescaler Select bit position. */ -+ -+#define LCD_CLKDIV_gm 0x70 /* LCD Clock Divide group mask. */ -+#define LCD_CLKDIV_gp 4 /* LCD Clock Divide group position. */ -+#define LCD_CLKDIV0_bm (1<<4) /* LCD Clock Divide bit 0 mask. */ -+#define LCD_CLKDIV0_bp 4 /* LCD Clock Divide bit 0 position. */ -+#define LCD_CLKDIV1_bm (1<<5) /* LCD Clock Divide bit 1 mask. */ -+#define LCD_CLKDIV1_bp 5 /* LCD Clock Divide bit 1 position. */ -+#define LCD_CLKDIV2_bm (1<<6) /* LCD Clock Divide bit 2 mask. */ -+#define LCD_CLKDIV2_bp 6 /* LCD Clock Divide bit 2 position. */ -+ -+#define LCD_LPWAV_bm 0x08 /* Low Power Waveform bit mask. */ -+#define LCD_LPWAV_bp 3 /* Low Power Waveform bit position. */ -+ -+#define LCD_DUTY_gm 0x03 /* Duty Select group mask. */ -+#define LCD_DUTY_gp 0 /* Duty Select group position. */ -+#define LCD_DUTY0_bm (1<<0) /* Duty Select bit 0 mask. */ -+#define LCD_DUTY0_bp 0 /* Duty Select bit 0 position. */ -+#define LCD_DUTY1_bm (1<<1) /* Duty Select bit 1 mask. */ -+#define LCD_DUTY1_bp 1 /* Duty Select bit 1 position. */ -+ -+/* LCD.CTRLC bit masks and bit positions */ -+#define LCD_PMSK_gm 0x3F /* LCD Port Mask group mask. */ -+#define LCD_PMSK_gp 0 /* LCD Port Mask group position. */ -+#define LCD_PMSK0_bm (1<<0) /* LCD Port Mask bit 0 mask. */ -+#define LCD_PMSK0_bp 0 /* LCD Port Mask bit 0 position. */ -+#define LCD_PMSK1_bm (1<<1) /* LCD Port Mask bit 1 mask. */ -+#define LCD_PMSK1_bp 1 /* LCD Port Mask bit 1 position. */ -+#define LCD_PMSK2_bm (1<<2) /* LCD Port Mask bit 2 mask. */ -+#define LCD_PMSK2_bp 2 /* LCD Port Mask bit 2 position. */ -+#define LCD_PMSK3_bm (1<<3) /* LCD Port Mask bit 3 mask. */ -+#define LCD_PMSK3_bp 3 /* LCD Port Mask bit 3 position. */ -+#define LCD_PMSK4_bm (1<<4) /* LCD Port Mask bit 4 mask. */ -+#define LCD_PMSK4_bp 4 /* LCD Port Mask bit 4 position. */ -+#define LCD_PMSK5_bm (1<<5) /* LCD Port Mask bit 5 mask. */ -+#define LCD_PMSK5_bp 5 /* LCD Port Mask bit 5 position. */ -+ -+/* LCD.INTCTRL bit masks and bit positions */ -+#define LCD_XIME_gm 0xF8 /* eXtended Interrupt Mode Enable group mask. */ -+#define LCD_XIME_gp 3 /* eXtended Interrupt Mode Enable group position. */ -+#define LCD_XIME0_bm (1<<3) /* eXtended Interrupt Mode Enable bit 0 mask. */ -+#define LCD_XIME0_bp 3 /* eXtended Interrupt Mode Enable bit 0 position. */ -+#define LCD_XIME1_bm (1<<4) /* eXtended Interrupt Mode Enable bit 1 mask. */ -+#define LCD_XIME1_bp 4 /* eXtended Interrupt Mode Enable bit 1 position. */ -+#define LCD_XIME2_bm (1<<5) /* eXtended Interrupt Mode Enable bit 2 mask. */ -+#define LCD_XIME2_bp 5 /* eXtended Interrupt Mode Enable bit 2 position. */ -+#define LCD_XIME3_bm (1<<6) /* eXtended Interrupt Mode Enable bit 3 mask. */ -+#define LCD_XIME3_bp 6 /* eXtended Interrupt Mode Enable bit 3 position. */ -+#define LCD_XIME4_bm (1<<7) /* eXtended Interrupt Mode Enable bit 4 mask. */ -+#define LCD_XIME4_bp 7 /* eXtended Interrupt Mode Enable bit 4 position. */ -+ -+#define LCD_FCINTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define LCD_FCINTLVL_gp 0 /* Interrupt Level group position. */ -+#define LCD_FCINTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define LCD_FCINTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define LCD_FCINTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define LCD_FCINTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* LCD.INTFLAG bit masks and bit positions */ -+#define LCD_FCIF_bm 0x01 /* LCD Frame Completed Interrupt Flag bit mask. */ -+#define LCD_FCIF_bp 0 /* LCD Frame Completed Interrupt Flag bit position. */ -+ -+/* LCD.CTRLD bit masks and bit positions */ -+#define LCD_BLINKEN_bm 0x08 /* Blink Enable bit mask. */ -+#define LCD_BLINKEN_bp 3 /* Blink Enable bit position. */ -+ -+#define LCD_BLINKRATE_gm 0x03 /* LCD Blink Rate group mask. */ -+#define LCD_BLINKRATE_gp 0 /* LCD Blink Rate group position. */ -+#define LCD_BLINKRATE0_bm (1<<0) /* LCD Blink Rate bit 0 mask. */ -+#define LCD_BLINKRATE0_bp 0 /* LCD Blink Rate bit 0 position. */ -+#define LCD_BLINKRATE1_bm (1<<1) /* LCD Blink Rate bit 1 mask. */ -+#define LCD_BLINKRATE1_bp 1 /* LCD Blink Rate bit 1 position. */ -+ -+/* LCD.CTRLE bit masks and bit positions */ -+#define LCD_BPS1_gm 0xF0 /* Blink Pixel Selection 1 group mask. */ -+#define LCD_BPS1_gp 4 /* Blink Pixel Selection 1 group position. */ -+#define LCD_BPS10_bm (1<<4) /* Blink Pixel Selection 1 bit 0 mask. */ -+#define LCD_BPS10_bp 4 /* Blink Pixel Selection 1 bit 0 position. */ -+#define LCD_BPS11_bm (1<<5) /* Blink Pixel Selection 1 bit 1 mask. */ -+#define LCD_BPS11_bp 5 /* Blink Pixel Selection 1 bit 1 position. */ -+#define LCD_BPS12_bm (1<<6) /* Blink Pixel Selection 1 bit 2 mask. */ -+#define LCD_BPS12_bp 6 /* Blink Pixel Selection 1 bit 2 position. */ -+#define LCD_BPS13_bm (1<<7) /* Blink Pixel Selection 1 bit 3 mask. */ -+#define LCD_BPS13_bp 7 /* Blink Pixel Selection 1 bit 3 position. */ -+ -+#define LCD_BPS0_gm 0x0F /* Blink Pixel Selection 0 group mask. */ -+#define LCD_BPS0_gp 0 /* Blink Pixel Selection 0 group position. */ -+#define LCD_BPS00_bm (1<<0) /* Blink Pixel Selection 0 bit 0 mask. */ -+#define LCD_BPS00_bp 0 /* Blink Pixel Selection 0 bit 0 position. */ -+#define LCD_BPS01_bm (1<<1) /* Blink Pixel Selection 0 bit 1 mask. */ -+#define LCD_BPS01_bp 1 /* Blink Pixel Selection 0 bit 1 position. */ -+#define LCD_BPS02_bm (1<<2) /* Blink Pixel Selection 0 bit 2 mask. */ -+#define LCD_BPS02_bp 2 /* Blink Pixel Selection 0 bit 2 position. */ -+#define LCD_BPS03_bm (1<<3) /* Blink Pixel Selection 0 bit 3 mask. */ -+#define LCD_BPS03_bp 3 /* Blink Pixel Selection 0 bit 3 position. */ -+ -+/* LCD.CTRLF bit masks and bit positions */ -+#define LCD_FCONT_gm 0x3F /* Fine Contrast group mask. */ -+#define LCD_FCONT_gp 0 /* Fine Contrast group position. */ -+#define LCD_FCONT0_bm (1<<0) /* Fine Contrast bit 0 mask. */ -+#define LCD_FCONT0_bp 0 /* Fine Contrast bit 0 position. */ -+#define LCD_FCONT1_bm (1<<1) /* Fine Contrast bit 1 mask. */ -+#define LCD_FCONT1_bp 1 /* Fine Contrast bit 1 position. */ -+#define LCD_FCONT2_bm (1<<2) /* Fine Contrast bit 2 mask. */ -+#define LCD_FCONT2_bp 2 /* Fine Contrast bit 2 position. */ -+#define LCD_FCONT3_bm (1<<3) /* Fine Contrast bit 3 mask. */ -+#define LCD_FCONT3_bp 3 /* Fine Contrast bit 3 position. */ -+#define LCD_FCONT4_bm (1<<4) /* Fine Contrast bit 4 mask. */ -+#define LCD_FCONT4_bp 4 /* Fine Contrast bit 4 position. */ -+#define LCD_FCONT5_bm (1<<5) /* Fine Contrast bit 5 mask. */ -+#define LCD_FCONT5_bp 5 /* Fine Contrast bit 5 position. */ -+ -+/* LCD.CTRLG bit masks and bit positions */ -+#define LCD_TDG_gm 0xC0 /* Type of Digit group mask. */ -+#define LCD_TDG_gp 6 /* Type of Digit group position. */ -+#define LCD_TDG0_bm (1<<6) /* Type of Digit bit 0 mask. */ -+#define LCD_TDG0_bp 6 /* Type of Digit bit 0 position. */ -+#define LCD_TDG1_bm (1<<7) /* Type of Digit bit 1 mask. */ -+#define LCD_TDG1_bp 7 /* Type of Digit bit 1 position. */ -+ -+#define LCD_STSEG_gm 0x3F /* Start Segment group mask. */ -+#define LCD_STSEG_gp 0 /* Start Segment group position. */ -+#define LCD_STSEG0_bm (1<<0) /* Start Segment bit 0 mask. */ -+#define LCD_STSEG0_bp 0 /* Start Segment bit 0 position. */ -+#define LCD_STSEG1_bm (1<<1) /* Start Segment bit 1 mask. */ -+#define LCD_STSEG1_bp 1 /* Start Segment bit 1 position. */ -+#define LCD_STSEG2_bm (1<<2) /* Start Segment bit 2 mask. */ -+#define LCD_STSEG2_bp 2 /* Start Segment bit 2 position. */ -+#define LCD_STSEG3_bm (1<<3) /* Start Segment bit 3 mask. */ -+#define LCD_STSEG3_bp 3 /* Start Segment bit 3 position. */ -+#define LCD_STSEG4_bm (1<<4) /* Start Segment bit 4 mask. */ -+#define LCD_STSEG4_bp 4 /* Start Segment bit 4 position. */ -+#define LCD_STSEG5_bm (1<<5) /* Start Segment bit 5 mask. */ -+#define LCD_STSEG5_bp 5 /* Start Segment bit 5 position. */ -+ -+/* LCD.CTRLH bit masks and bit positions */ -+#define LCD_DEC_bm 0x80 /* Decrement of Start Segment bit mask. */ -+#define LCD_DEC_bp 7 /* Decrement of Start Segment bit position. */ -+ -+#define LCD_DCODE_gm 0x7F /* Display Code group mask. */ -+#define LCD_DCODE_gp 0 /* Display Code group position. */ -+#define LCD_DCODE0_bm (1<<0) /* Display Code bit 0 mask. */ -+#define LCD_DCODE0_bp 0 /* Display Code bit 0 position. */ -+#define LCD_DCODE1_bm (1<<1) /* Display Code bit 1 mask. */ -+#define LCD_DCODE1_bp 1 /* Display Code bit 1 position. */ -+#define LCD_DCODE2_bm (1<<2) /* Display Code bit 2 mask. */ -+#define LCD_DCODE2_bp 2 /* Display Code bit 2 position. */ -+#define LCD_DCODE3_bm (1<<3) /* Display Code bit 3 mask. */ -+#define LCD_DCODE3_bp 3 /* Display Code bit 3 position. */ -+#define LCD_DCODE4_bm (1<<4) /* Display Code bit 4 mask. */ -+#define LCD_DCODE4_bp 4 /* Display Code bit 4 position. */ -+#define LCD_DCODE5_bm (1<<5) /* Display Code bit 5 mask. */ -+#define LCD_DCODE5_bp 5 /* Display Code bit 5 position. */ -+#define LCD_DCODE6_bm (1<<6) /* Display Code bit 6 mask. */ -+#define LCD_DCODE6_bp 6 /* Display Code bit 6 position. */ -+ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -+#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -+#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -+#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -+#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -+#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -+#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -+#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -+#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -+#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -+#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -+#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -+#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -+#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -+#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -+#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -+#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -+#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -+#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ -+ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -+#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -+#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* LOCKBIT - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT0_vect_num 2 -+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -+#define PORTC_INT1_vect_num 3 -+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT0_vect_num 4 -+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -+#define PORTR_INT1_vect_num 5 -+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ -+ -+/* DMA interrupt vectors */ -+#define DMA_CH0_vect_num 6 -+#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -+#define DMA_CH1_vect_num 7 -+#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -+ -+/* RTC interrupt vectors */ -+#define RTC_OVF_vect_num 10 -+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -+#define RTC_COMP_vect_num 11 -+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 12 -+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 13 -+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_OVF_vect_num 14 -+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LUNF_vect_num 14 -+#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_ERR_vect_num 15 -+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_HUNF_vect_num 15 -+#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCA_vect_num 16 -+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPA_vect_num 16 -+#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCB_vect_num 17 -+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPB_vect_num 17 -+#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCC_vect_num 18 -+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPC_vect_num 18 -+#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCD_vect_num 19 -+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPD_vect_num 19 -+#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ -+ -+/* TCC1 interrupt vectors */ -+#define TCC1_OVF_vect_num 20 -+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -+#define TCC1_ERR_vect_num 21 -+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -+#define TCC1_CCA_vect_num 22 -+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -+#define TCC1_CCB_vect_num 23 -+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 24 -+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 25 -+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 26 -+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 27 -+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ -+ -+/* USB interrupt vectors */ -+#define USB_BUSEVENT_vect_num 31 -+#define USB_BUSEVENT_vect _VECTOR(31) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -+#define USB_TRNCOMPL_vect_num 32 -+#define USB_TRNCOMPL_vect _VECTOR(32) /* Transaction complete interrupt */ -+ -+/* LCD interrupt vectors */ -+#define LCD_INT_vect_num 35 -+#define LCD_INT_vect _VECTOR(35) /* LCD Interrupt */ -+ -+/* AES interrupt vectors */ -+#define AES_INT_vect_num 36 -+#define AES_INT_vect _VECTOR(36) /* AES Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 37 -+#define NVM_EE_vect _VECTOR(37) /* EE Interrupt */ -+#define NVM_SPM_vect_num 38 -+#define NVM_SPM_vect _VECTOR(38) /* SPM Interrupt */ -+ -+/* PORTB interrupt vectors */ -+#define PORTB_INT0_vect_num 39 -+#define PORTB_INT0_vect _VECTOR(39) /* External Interrupt 0 */ -+#define PORTB_INT1_vect_num 40 -+#define PORTB_INT1_vect _VECTOR(40) /* External Interrupt 1 */ -+ -+/* ACB interrupt vectors */ -+#define ACB_AC0_vect_num 41 -+#define ACB_AC0_vect _VECTOR(41) /* AC0 Interrupt */ -+#define ACB_AC1_vect_num 42 -+#define ACB_AC1_vect _VECTOR(42) /* AC1 Interrupt */ -+#define ACB_ACW_vect_num 43 -+#define ACB_ACW_vect _VECTOR(43) /* ACW Window Mode Interrupt */ -+ -+/* ADCB interrupt vectors */ -+#define ADCB_CH0_vect_num 44 -+#define ADCB_CH0_vect _VECTOR(44) /* Interrupt 0 */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT0_vect_num 48 -+#define PORTD_INT0_vect _VECTOR(48) /* External Interrupt 0 */ -+#define PORTD_INT1_vect_num 49 -+#define PORTD_INT1_vect _VECTOR(49) /* External Interrupt 1 */ -+ -+/* PORTG interrupt vectors */ -+#define PORTG_INT0_vect_num 50 -+#define PORTG_INT0_vect _VECTOR(50) /* External Interrupt 0 */ -+#define PORTG_INT1_vect_num 51 -+#define PORTG_INT1_vect _VECTOR(51) /* External Interrupt 1 */ -+ -+/* PORTM interrupt vectors */ -+#define PORTM_INT0_vect_num 52 -+#define PORTM_INT0_vect _VECTOR(52) /* External Interrupt 0 */ -+#define PORTM_INT1_vect_num 53 -+#define PORTM_INT1_vect _VECTOR(53) /* External Interrupt 1 */ -+ -+/* PORTE interrupt vectors */ -+#define PORTE_INT0_vect_num 54 -+#define PORTE_INT0_vect _VECTOR(54) /* External Interrupt 0 */ -+#define PORTE_INT1_vect_num 55 -+#define PORTE_INT1_vect _VECTOR(55) /* External Interrupt 1 */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_OVF_vect_num 58 -+#define TCE0_OVF_vect _VECTOR(58) /* Overflow Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LUNF_vect_num 58 -+#define TCE2_LUNF_vect _VECTOR(58) /* Low Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_ERR_vect_num 59 -+#define TCE0_ERR_vect _VECTOR(59) /* Error Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_HUNF_vect_num 59 -+#define TCE2_HUNF_vect _VECTOR(59) /* High Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCA_vect_num 60 -+#define TCE0_CCA_vect _VECTOR(60) /* Compare or Capture A Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPA_vect_num 60 -+#define TCE2_LCMPA_vect _VECTOR(60) /* Low Byte Compare A Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCB_vect_num 61 -+#define TCE0_CCB_vect _VECTOR(61) /* Compare or Capture B Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPB_vect_num 61 -+#define TCE2_LCMPB_vect _VECTOR(61) /* Low Byte Compare B Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCC_vect_num 62 -+#define TCE0_CCC_vect _VECTOR(62) /* Compare or Capture C Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPC_vect_num 62 -+#define TCE2_LCMPC_vect _VECTOR(62) /* Low Byte Compare C Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCD_vect_num 63 -+#define TCE0_CCD_vect _VECTOR(63) /* Compare or Capture D Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPD_vect_num 63 -+#define TCE2_LCMPD_vect _VECTOR(63) /* Low Byte Compare D Interrupt */ -+ -+/* USARTE0 interrupt vectors */ -+#define USARTE0_RXC_vect_num 69 -+#define USARTE0_RXC_vect _VECTOR(69) /* Reception Complete Interrupt */ -+#define USARTE0_DRE_vect_num 70 -+#define USARTE0_DRE_vect _VECTOR(70) /* Data Register Empty Interrupt */ -+#define USARTE0_TXC_vect_num 71 -+#define USARTE0_TXC_vect _VECTOR(71) /* Transmission Complete Interrupt */ -+ -+/* PORTA interrupt vectors */ -+#define PORTA_INT0_vect_num 75 -+#define PORTA_INT0_vect _VECTOR(75) /* External Interrupt 0 */ -+#define PORTA_INT1_vect_num 76 -+#define PORTA_INT1_vect _VECTOR(76) /* External Interrupt 1 */ -+ -+/* ACA interrupt vectors */ -+#define ACA_AC0_vect_num 77 -+#define ACA_AC0_vect _VECTOR(77) /* AC0 Interrupt */ -+#define ACA_AC1_vect_num 78 -+#define ACA_AC1_vect _VECTOR(78) /* AC1 Interrupt */ -+#define ACA_ACW_vect_num 79 -+#define ACA_ACW_vect _VECTOR(79) /* ACW Window Mode Interrupt */ -+ -+/* ADCA interrupt vectors */ -+#define ADCA_CH0_vect_num 80 -+#define ADCA_CH0_vect _VECTOR(80) /* Interrupt 0 */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (81 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (139264) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (131072) -+#define APP_SECTION_PAGE_SIZE (256) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0x1E000) -+#define APPTABLE_SECTION_SIZE (8192) -+#define APPTABLE_SECTION_PAGE_SIZE (256) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x20000) -+#define BOOT_SECTION_SIZE (8192) -+#define BOOT_SECTION_PAGE_SIZE (256) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (16384) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (2048) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (8192) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (2048) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (6) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (256) -+#define USER_SIGNATURES_PAGE_SIZE (256) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (52) -+#define PROD_SIGNATURES_PAGE_SIZE (256) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 256 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 6 -+ -+/* Fuse Byte 0 */ -+#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -+#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -+#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -+#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -+#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -+#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -+#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -+#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -+#define FUSE0_DEFAULT (0xFF) -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x97 -+#define SIGNATURE_2 0x4D -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA128B1_H_INCLUDED */ -+ -diff --git a/include/avr/iox128b3.h b/include/avr/iox128b3.h -new file mode 100644 -index 0000000..26ebdfb ---- /dev/null -+++ b/include/avr/iox128b3.h -@@ -0,0 +1,6247 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox128b3.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA128B3_H_INCLUDED -+#define _AVR_ATXMEGA128B3_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+VPORT - Virtual Ports -+-------------------------------------------------------------------------- -+*/ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t USBCTRL; /* USB Control Register */ -+} CLK_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+/* USB Prescaler Division Factor */ -+typedef enum CLK_USBPSDIV_enum -+{ -+ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ -+ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ -+ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ -+ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ -+ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ -+ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -+} CLK_USBPSDIV_t; -+ -+/* USB Clock Source */ -+typedef enum CLK_USBSRC_enum -+{ -+ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ -+ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -+} CLK_USBSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control Register */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C0_gc = (0x01<<0), /* External Clock on port C0 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C1_gc = (0x05<<0), /* External Clock on port C1 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C2_gc = (0x09<<0), /* External Clock on port C2 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C3_gc = (0x0D<<0), /* External Clock on port C3 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C4_gc = (0x11<<0), /* External Clock on port C4 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C5_gc = (0x15<<0), /* External Clock on port C5 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C6_gc = (0x19<<0), /* External Clock on port C6 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C7_gc = (0x1D<<0), /* External Clock on port C7 - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+/* 2 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC2MCREF_enum -+{ -+ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC2MCREF_t; -+ -+/* 32 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC32MCREF_enum -+{ -+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -+} OSC_RC32MCREF_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PR - Power Reduction -+-------------------------------------------------------------------------- -+*/ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t PRPB; /* Power Reduction Port B */ -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t reserved_0x04; -+ register8_t PRPE; /* Power Reduction Port E */ -+} PR_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t JTAGUID; /* JTAG User ID */ -+ register8_t reserved_0x05; -+ register8_t MCUCR; /* MCU Control */ -+ register8_t ANAINIT; /* Analog Startup Delay */ -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t AWEXLOCK; /* AWEX Lock */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORTCFG - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t VPCTRLA; /* Virtual Port Control Register A */ -+ register8_t VPCTRLB; /* Virtual Port Control Register B */ -+ register8_t CLKEVOUT; /* Clock and Event Out Register */ -+ register8_t reserved_0x05; -+ register8_t EVOUTSEL; /* Event Output Select */ -+} PORTCFG_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP02MAP_enum -+{ -+ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ -+ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ -+ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ -+ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ -+ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ -+ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ -+ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ -+ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -+} PORTCFG_VP02MAP_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP13MAP_enum -+{ -+ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ -+ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ -+ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ -+ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ -+ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ -+ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ -+ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ -+ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -+} PORTCFG_VP13MAP_t; -+ -+/* System Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC_gc = (0x01<<0), /* System Clock Output on Port C */ -+ PORTCFG_CLKOUT_PE_gc = (0x03<<0), /* System Clock Output on Port E */ -+} PORTCFG_CLKOUT_t; -+ -+/* Peripheral Clock Output Select */ -+typedef enum PORTCFG_CLKOUTSEL_enum -+{ -+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -+} PORTCFG_CLKOUTSEL_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC_gc = (0x01<<4), /* Event Channel 0 Output on Port C */ -+ PORTCFG_EVOUT_PE_gc = (0x03<<4), /* Event Channel 0 Output on Port E */ -+} PORTCFG_EVOUT_t; -+ -+/* Clock and Event Output Port */ -+typedef enum PORTCFG_CLKEVPIN_enum -+{ -+ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ -+ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -+} PORTCFG_CLKEVPIN_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<2), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<2), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<2), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<2), /* Event Channel 3 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AES - AES Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* AES Module */ -+typedef struct AES_struct -+{ -+ register8_t CTRL; /* AES Control Register */ -+ register8_t STATUS; /* AES Status Register */ -+ register8_t STATE; /* AES State Register */ -+ register8_t KEY; /* AES Key Register */ -+ register8_t INTCTRL; /* AES Interrupt Control Register */ -+} AES_t; -+ -+/* Interrupt level */ -+typedef enum AES_INTLVL_enum -+{ -+ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} AES_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ -+ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DMA - DMA Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* DMA Channel */ -+typedef struct DMA_CH_struct -+{ -+ register8_t CTRLA; /* Channel Control */ -+ register8_t CTRLB; /* Channel Control */ -+ register8_t ADDRCTRL; /* Address Control */ -+ register8_t TRIGSRC; /* Channel Trigger Source */ -+ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ -+ register8_t REPCNT; /* Channel Repeat Count */ -+ register8_t reserved_0x07; -+ register8_t SRCADDR0; /* Channel Source Address 0 */ -+ register8_t SRCADDR1; /* Channel Source Address 1 */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t DESTADDR0; /* Channel Destination Address 0 */ -+ register8_t DESTADDR1; /* Channel Destination Address 1 */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} DMA_CH_t; -+ -+ -+/* DMA Controller */ -+typedef struct DMA_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t reserved_0x01; -+ register8_t reserved_0x02; -+ register8_t INTFLAGS; /* Transfer Interrupt Status */ -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x05; -+ _WORDREGISTER(TEMP); /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ DMA_CH_t CH0; /* DMA Channel 0 */ -+ DMA_CH_t CH1; /* DMA Channel 1 */ -+} DMA_t; -+ -+/* Burst mode */ -+typedef enum DMA_CH_BURSTLEN_enum -+{ -+ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ -+ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ -+ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ -+ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -+} DMA_CH_BURSTLEN_t; -+ -+/* Source address reload mode */ -+typedef enum DMA_CH_SRCRELOAD_enum -+{ -+ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ -+ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ -+ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ -+ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -+} DMA_CH_SRCRELOAD_t; -+ -+/* Source addressing mode */ -+typedef enum DMA_CH_SRCDIR_enum -+{ -+ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ -+ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ -+ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -+} DMA_CH_SRCDIR_t; -+ -+/* Destination adress reload mode */ -+typedef enum DMA_CH_DESTRELOAD_enum -+{ -+ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ -+ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ -+ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ -+ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -+} DMA_CH_DESTRELOAD_t; -+ -+/* Destination adressing mode */ -+typedef enum DMA_CH_DESTDIR_enum -+{ -+ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ -+ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ -+ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -+} DMA_CH_DESTDIR_t; -+ -+/* Transfer trigger source */ -+typedef enum DMA_CH_TRIGSRC_enum -+{ -+ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ -+ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ -+ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ -+ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ -+ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ -+ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ -+ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ -+ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ -+ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ -+ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ -+ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ -+ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ -+ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ -+} DMA_CH_TRIGSRC_t; -+ -+/* Double buffering mode */ -+typedef enum DMA_DBUFMODE_enum -+{ -+ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ -+ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ -+} DMA_DBUFMODE_t; -+ -+/* Priority mode */ -+typedef enum DMA_PRIMODE_enum -+{ -+ DMA_PRIMODE_RR01_gc = (0x00<<0), /* Round Robin */ -+ DMA_PRIMODE_CH0RR1_gc = (0x01<<0), /* Channel 0 > channel 1 */ -+} DMA_PRIMODE_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_ERRINTLVL_enum -+{ -+ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ -+ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ -+ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -+} DMA_CH_ERRINTLVL_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_TRNINTLVL_enum -+{ -+ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ -+ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -+} DMA_CH_TRNINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+} EVSYS_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ -+ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ -+ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ -+ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ -+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ -+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ -+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ -+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ -+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ -+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ -+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ -+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ -+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ -+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ -+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ -+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ -+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ -+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ -+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ -+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ -+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ -+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ -+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ -+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ -+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ -+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ -+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ -+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ -+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ -+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -+} EVSYS_CHMUX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ -+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ -+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ -+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ -+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} NVM_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t reserved_0x07; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+} ADC_t; -+ -+/* Current Limitation */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -+} ADC_CURRLIMIT_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+} ADC_CH_MUXNEG_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ -+ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ -+ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ -+ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+ register8_t CURRCTRL; /* Current Source Control Register */ -+ register8_t CURRCALIB; /* Current Source Calibration Register */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC - Real-Time Counter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Real-Time Counter */ -+typedef struct RTC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary register */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ _WORDREGISTER(CNT); /* Count Register */ -+ _WORDREGISTER(PER); /* Period Register */ -+ _WORDREGISTER(COMP); /* Compare Register */ -+} RTC_t; -+ -+/* Prescaler Factor */ -+typedef enum RTC_PRESCALER_enum -+{ -+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ -+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ -+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ -+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ -+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ -+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ -+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ -+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -+} RTC_PRESCALER_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC_COMPINTLVL_enum -+{ -+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC_OVFINTLVL_enum -+{ -+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+} TWI_t; -+ -+/* SDA Hold Time */ -+typedef enum TWI_SDAHOLD_enum -+{ -+ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ -+ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ -+ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ -+ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -+} TWI_SDAHOLD_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USB - USB -+-------------------------------------------------------------------------- -+*/ -+ -+/* USB Endpoint */ -+typedef struct USB_EP_struct -+{ -+ register8_t STATUS; /* Endpoint Status */ -+ register8_t CTRL; /* Endpoint Control */ -+ _WORDREGISTER(CNT); /* USB Endpoint Counter */ -+ _WORDREGISTER(DATAPTR); /* Data Pointer */ -+ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -+} USB_EP_t; -+ -+ -+/* Universal Serial Bus */ -+typedef struct USB_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t FIFOWP; /* FIFO Write Pointer Register */ -+ register8_t FIFORP; /* FIFO Read Pointer Register */ -+ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ -+ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ -+ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ -+ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t reserved_0x20; -+ register8_t reserved_0x21; -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t CAL0; /* Calibration Byte 0 */ -+ register8_t CAL1; /* Calibration Byte 1 */ -+} USB_t; -+ -+ -+/* USB Endpoint Table */ -+typedef struct USB_EP_TABLE_struct -+{ -+ USB_EP_t EP0OUT; /* Endpoint 0 */ -+ USB_EP_t EP0IN; /* Endpoint 0 */ -+ USB_EP_t EP1OUT; /* Endpoint 1 */ -+ USB_EP_t EP1IN; /* Endpoint 1 */ -+ USB_EP_t EP2OUT; /* Endpoint 2 */ -+ USB_EP_t EP2IN; /* Endpoint 2 */ -+ USB_EP_t EP3OUT; /* Endpoint 3 */ -+ USB_EP_t EP3IN; /* Endpoint 3 */ -+ USB_EP_t EP4OUT; /* Endpoint 4 */ -+ USB_EP_t EP4IN; /* Endpoint 4 */ -+ USB_EP_t EP5OUT; /* Endpoint 5 */ -+ USB_EP_t EP5IN; /* Endpoint 5 */ -+ USB_EP_t EP6OUT; /* Endpoint 6 */ -+ USB_EP_t EP6IN; /* Endpoint 6 */ -+ USB_EP_t EP7OUT; /* Endpoint 7 */ -+ USB_EP_t EP7IN; /* Endpoint 7 */ -+ USB_EP_t EP8OUT; /* Endpoint 8 */ -+ USB_EP_t EP8IN; /* Endpoint 8 */ -+ USB_EP_t EP9OUT; /* Endpoint 9 */ -+ USB_EP_t EP9IN; /* Endpoint 9 */ -+ USB_EP_t EP10OUT; /* Endpoint 10 */ -+ USB_EP_t EP10IN; /* Endpoint 10 */ -+ USB_EP_t EP11OUT; /* Endpoint 11 */ -+ USB_EP_t EP11IN; /* Endpoint 11 */ -+ USB_EP_t EP12OUT; /* Endpoint 12 */ -+ USB_EP_t EP12IN; /* Endpoint 12 */ -+ USB_EP_t EP13OUT; /* Endpoint 13 */ -+ USB_EP_t EP13IN; /* Endpoint 13 */ -+ USB_EP_t EP14OUT; /* Endpoint 14 */ -+ USB_EP_t EP14IN; /* Endpoint 14 */ -+ USB_EP_t EP15OUT; /* Endpoint 15 */ -+ USB_EP_t EP15IN; /* Endpoint 15 */ -+ register8_t reserved_0x100; -+ register8_t reserved_0x101; -+ register8_t reserved_0x102; -+ register8_t reserved_0x103; -+ register8_t reserved_0x104; -+ register8_t reserved_0x105; -+ register8_t reserved_0x106; -+ register8_t reserved_0x107; -+ register8_t reserved_0x108; -+ register8_t reserved_0x109; -+ register8_t reserved_0x10A; -+ register8_t reserved_0x10B; -+ register8_t reserved_0x10C; -+ register8_t reserved_0x10D; -+ register8_t reserved_0x10E; -+ register8_t reserved_0x10F; -+ register8_t FRAMENUML; /* Frame Number Low Byte */ -+ register8_t FRAMENUMH; /* Frame Number High Byte */ -+} USB_EP_TABLE_t; -+ -+/* Interrupt level */ -+typedef enum USB_INTLVL_enum -+{ -+ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} USB_INTLVL_t; -+ -+/* USB Endpoint Type */ -+typedef enum USB_EP_TYPE_enum -+{ -+ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ -+ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ -+ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ -+ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -+} USB_EP_TYPE_t; -+ -+/* USB Endpoint Buffersize */ -+typedef enum USB_EP_BUFSIZE_enum -+{ -+ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ -+ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ -+ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ -+ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ -+ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ -+ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ -+ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ -+ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -+} USB_EP_BUFSIZE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - I/O Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INT0MASK; /* Port Interrupt 0 Mask */ -+ register8_t INT1MASK; /* Port Interrupt 1 Mask */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t REMAP; /* I/O Port Pin Remap Register */ -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Port Interrupt 0 Level */ -+typedef enum PORT_INT0LVL_enum -+{ -+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INT0LVL_t; -+ -+/* Port Interrupt 1 Level */ -+typedef enum PORT_INT1LVL_enum -+{ -+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ -+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ -+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -+} PORT_INT1LVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 0 */ -+typedef struct TC0_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC0_t; -+ -+ -+/* 16-bit Timer/Counter 1 */ -+typedef struct TC1_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+} TC1_t; -+ -+/* Clock Selection */ -+typedef enum TC_CLKSEL_enum -+{ -+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_CLKSEL_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC_WGMODE_enum -+{ -+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC_WGMODE_t; -+ -+/* Byte Mode */ -+typedef enum TC_BYTEM_enum -+{ -+ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ -+ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -+} TC_BYTEM_t; -+ -+/* Event Action */ -+typedef enum TC_EVACT_enum -+{ -+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ -+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ -+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ -+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ -+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ -+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC_EVSEL_enum -+{ -+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_EVSEL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC_ERRINTLVL_enum -+{ -+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC_OVFINTLVL_enum -+{ -+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_OVFINTLVL_t; -+ -+/* Compare or Capture D Interrupt Level */ -+typedef enum TC_CCDINTLVL_enum -+{ -+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC_CCDINTLVL_t; -+ -+/* Compare or Capture C Interrupt Level */ -+typedef enum TC_CCCINTLVL_enum -+{ -+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC_CCCINTLVL_t; -+ -+/* Compare or Capture B Interrupt Level */ -+typedef enum TC_CCBINTLVL_enum -+{ -+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_CCBINTLVL_t; -+ -+/* Compare or Capture A Interrupt Level */ -+typedef enum TC_CCAINTLVL_enum -+{ -+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_CCAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC_CMD_enum -+{ -+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AWEX - Timer/Counter Advanced Waveform Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Advanced Waveform Extension */ -+typedef struct AWEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t FDEMASK; /* Fault Detection Event Mask */ -+ register8_t FDCTRL; /* Fault Detection Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t STATUSSET; /* Status Set Register */ -+ register8_t DTBOTH; /* Dead Time Both Sides */ -+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ -+ register8_t DTLS; /* Dead Time Low Side */ -+ register8_t DTHS; /* Dead Time High Side */ -+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ -+ register8_t DTHSBUF; /* Dead Time High Side Buffer */ -+ register8_t OUTOVEN; /* Output Override Enable */ -+} AWEX_t; -+ -+/* Fault Detect Action */ -+typedef enum AWEX_FDACT_enum -+{ -+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ -+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -+} AWEX_FDACT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+HIRES - Timer/Counter High-Resolution Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register */ -+} HIRES_t; -+ -+/* High Resolution Enable */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ -+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+} IRDA_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LCD - LCD Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* LCD Controller */ -+typedef struct LCD_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t INTCTRL; /* Interrupt Enable Register */ -+ register8_t INTFLAG; /* Interrupt Flag Register */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t CTRLF; /* Control Register F */ -+ register8_t CTRLG; /* Control Register G */ -+ register8_t CTRLH; /* Control Register H */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t DATA0; /* LCD Data Register 0 */ -+ register8_t DATA1; /* LCD Data Register 1 */ -+ register8_t DATA2; /* LCD Data Register 2 */ -+ register8_t DATA3; /* LCD Data Register 3 */ -+ register8_t DATA4; /* LCD Data Register 4 */ -+ register8_t DATA5; /* LCD Data Register 5 */ -+ register8_t DATA6; /* LCD Data Register 6 */ -+ register8_t DATA7; /* LCD Data Register 7 */ -+ register8_t DATA8; /* LCD Data Register 8 */ -+ register8_t DATA9; /* LCD Data Register 9 */ -+ register8_t DATA10; /* LCD Data Register 10 */ -+ register8_t DATA11; /* LCD Data Register 11 */ -+ register8_t DATA12; /* LCD Data Register 12 */ -+ register8_t DATA13; /* LCD Data Register 13 */ -+ register8_t DATA14; /* LCD Data Register 14 */ -+ register8_t DATA15; /* LCD Data Register 15 */ -+ register8_t DATA16; /* LCD Data Register 16 */ -+ register8_t DATA17; /* LCD Data Register 17 */ -+ register8_t DATA18; /* LCD Data Register 18 */ -+ register8_t DATA19; /* LCD Data Register 19 */ -+} LCD_t; -+ -+/* LCD Blink Rate */ -+typedef enum LCD_BLINKRATE_enum -+{ -+ LCD_BLINKRATE_4Hz_gc = (0x00<<0), /* 4Hz Blink Rate */ -+ LCD_BLINKRATE_2Hz_gc = (0x01<<0), /* 2Hz Blink Rate */ -+ LCD_BLINKRATE_1Hz_gc = (0x02<<0), /* 1Hz Blink Rate */ -+ LCD_BLINKRATE_0Hz5_gc = (0x03<<0), /* 0.5Hz Blink Rate */ -+} LCD_BLINKRATE_t; -+ -+/* LCD Clock Divide */ -+typedef enum LCD_CLKDIV_enum -+{ -+ LCD_CLKDIV_DivBy1_gc = (0x00<<4), /* frame rate of 256 Hz */ -+ LCD_CLKDIV_DivBy2_gc = (0x01<<4), /* frame rate of 128 Hz */ -+ LCD_CLKDIV_DivBy3_gc = (0x02<<4), /* frame rate of 83.5 Hz */ -+ LCD_CLKDIV_DivBy4_gc = (0x03<<4), /* frame rate of 64 Hz */ -+ LCD_CLKDIV_DivBy5_gc = (0x04<<4), /* frame rate of 51.2 Hz */ -+ LCD_CLKDIV_DivBy6_gc = (0x05<<4), /* frame rate of 42.7 Hz */ -+ LCD_CLKDIV_DivBy7_gc = (0x06<<4), /* frame rate of 36.6 Hz */ -+ LCD_CLKDIV_DivBy8_gc = (0x07<<4), /* frame rate of 32 Hz */ -+} LCD_CLKDIV_t; -+ -+/* Duty Select */ -+typedef enum LCD_DUTY_enum -+{ -+ LCD_DUTY_1_4_gc = (0x00<<0), /* Duty=1/4, Bias=1/3, COM0:3 */ -+ LCD_DUTY_Static_gc = (0x01<<0), /* Duty=Static, Bias=Static, COM0 */ -+ LCD_DUTY_1_2_gc = (0x02<<0), /* Duty=1/2, Bias=1/3, COM0:1 */ -+ LCD_DUTY_1_3_gc = (0x03<<0), /* Duty=1/3, Bias=1/3, COM0:2 */ -+} LCD_DUTY_t; -+ -+/* LCD Prescaler Select */ -+typedef enum LCD_PRESC_enum -+{ -+ LCD_PRESC_8_gc = (0x00<<7), /* clk_lcd/8 */ -+ LCD_PRESC_16_gc = (0x01<<7), /* clk_lcd/16 */ -+} LCD_PRESC_t; -+ -+/* Type of Digit */ -+typedef enum LCD_TDG_enum -+{ -+ LCD_TDG_7S_3C_gc = (0x00<<6), /* 7-segment with 3 COMs */ -+ LCD_TDG_7S_4C_gc = (0x01<<6), /* 7-segment with 4 COMs */ -+ LCD_TDG_14S_4C_gc = (0x02<<6), /* 14-segment with 4 COMs */ -+ LCD_TDG_16S_3C_gc = (0x03<<6), /* 16-segment with 3 COMs */ -+} LCD_TDG_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t FUSEBYTE0; /* JTAG User ID */ -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+} NVM_FUSES_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* Timer Oscillator pin location */ -+typedef enum TOSCSEL_enum -+{ -+ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ -+ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -+} TOSCSEL_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -+} BOD_t; -+ -+/* BOD operation */ -+typedef enum BODACT_enum -+{ -+ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BODACT_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WDP_enum -+{ -+ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ -+ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ -+ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ -+ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ -+ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ -+ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ -+ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ -+ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ -+ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ -+ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ -+ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -+} WDP_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LOCKBIT - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ -+ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t USBCAL0; /* USB Calibration Byte 0 */ -+ register8_t USBCAL1; /* USB Calibration Byte 1 */ -+ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ -+ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ -+ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+ register8_t reserved_0x40; -+ register8_t reserved_0x41; -+ register8_t reserved_0x42; -+ register8_t reserved_0x43; -+ register8_t reserved_0x44; -+ register8_t reserved_0x45; -+ register8_t reserved_0x46; -+ register8_t reserved_0x47; -+} NVM_PROD_SIGNATURES_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define AES (*(AES_t *) 0x00C0) /* AES Module */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ -+#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ -+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -+#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTG (*(PORT_t *) 0x06C0) /* I/O Ports */ -+#define PORTM (*(PORT_t *) 0x0760) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -+#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define LCD (*(LCD_t *) 0x0D00) /* LCD Controller */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -+#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -+#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -+#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -+#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+#define CLK_USBCTRL _SFR_MEM8(0x0044) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* DFLL - DFLL */ -+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -+#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -+#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPB _SFR_MEM8(0x0072) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPE _SFR_MEM8(0x0075) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_JTAGUID _SFR_MEM8(0x0094) -+#define MCU_MCUCR _SFR_MEM8(0x0096) -+#define MCU_ANAINIT _SFR_MEM8(0x0097) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_AWEXLOCK _SFR_MEM8(0x0099) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) -+ -+/* AES - AES Module */ -+#define AES_CTRL _SFR_MEM8(0x00C0) -+#define AES_STATUS _SFR_MEM8(0x00C1) -+#define AES_STATE _SFR_MEM8(0x00C2) -+#define AES_KEY _SFR_MEM8(0x00C3) -+#define AES_INTCTRL _SFR_MEM8(0x00C4) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* DMA - DMA Controller */ -+#define DMA_CTRL _SFR_MEM8(0x0100) -+#define DMA_INTFLAGS _SFR_MEM8(0x0103) -+#define DMA_STATUS _SFR_MEM8(0x0104) -+#define DMA_TEMP _SFR_MEM16(0x0106) -+#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -+#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -+#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -+#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -+#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -+#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -+#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -+#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -+#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -+#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -+#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -+#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -+#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -+#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -+#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -+#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -+#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -+#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -+#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -+#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCB_CTRLA _SFR_MEM8(0x0240) -+#define ADCB_CTRLB _SFR_MEM8(0x0241) -+#define ADCB_REFCTRL _SFR_MEM8(0x0242) -+#define ADCB_EVCTRL _SFR_MEM8(0x0243) -+#define ADCB_PRESCALER _SFR_MEM8(0x0244) -+#define ADCB_INTFLAGS _SFR_MEM8(0x0246) -+#define ADCB_TEMP _SFR_MEM8(0x0247) -+#define ADCB_SAMPCTRL _SFR_MEM8(0x0248) -+#define ADCB_CAL _SFR_MEM16(0x024C) -+#define ADCB_CH0RES _SFR_MEM16(0x0250) -+#define ADCB_CMP _SFR_MEM16(0x0258) -+#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) -+#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) -+#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) -+#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) -+#define ADCB_CH0_RES _SFR_MEM16(0x0264) -+#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) -+ -+/* AC - Analog Comparator */ -+#define ACB_AC0CTRL _SFR_MEM8(0x0390) -+#define ACB_AC1CTRL _SFR_MEM8(0x0391) -+#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -+#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -+#define ACB_CTRLA _SFR_MEM8(0x0394) -+#define ACB_CTRLB _SFR_MEM8(0x0395) -+#define ACB_WINCTRL _SFR_MEM8(0x0396) -+#define ACB_STATUS _SFR_MEM8(0x0397) -+#define ACB_CURRCTRL _SFR_MEM8(0x0398) -+#define ACB_CURRCALIB _SFR_MEM8(0x0399) -+ -+/* RTC - Real-Time Counter */ -+#define RTC_CTRL _SFR_MEM8(0x0400) -+#define RTC_STATUS _SFR_MEM8(0x0401) -+#define RTC_INTCTRL _SFR_MEM8(0x0402) -+#define RTC_INTFLAGS _SFR_MEM8(0x0403) -+#define RTC_TEMP _SFR_MEM8(0x0404) -+#define RTC_CNT _SFR_MEM16(0x0408) -+#define RTC_PER _SFR_MEM16(0x040A) -+#define RTC_COMP _SFR_MEM16(0x040C) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+ -+/* USB - Universal Serial Bus */ -+#define USB_CTRLA _SFR_MEM8(0x04C0) -+#define USB_CTRLB _SFR_MEM8(0x04C1) -+#define USB_STATUS _SFR_MEM8(0x04C2) -+#define USB_ADDR _SFR_MEM8(0x04C3) -+#define USB_FIFOWP _SFR_MEM8(0x04C4) -+#define USB_FIFORP _SFR_MEM8(0x04C5) -+#define USB_EPPTR _SFR_MEM16(0x04C6) -+#define USB_INTCTRLA _SFR_MEM8(0x04C8) -+#define USB_INTCTRLB _SFR_MEM8(0x04C9) -+#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -+#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -+#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -+#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -+#define USB_CAL0 _SFR_MEM8(0x04FA) -+#define USB_CAL1 _SFR_MEM8(0x04FB) -+ -+/* PORT - I/O Ports */ -+#define PORTB_DIR _SFR_MEM8(0x0620) -+#define PORTB_DIRSET _SFR_MEM8(0x0621) -+#define PORTB_DIRCLR _SFR_MEM8(0x0622) -+#define PORTB_DIRTGL _SFR_MEM8(0x0623) -+#define PORTB_OUT _SFR_MEM8(0x0624) -+#define PORTB_OUTSET _SFR_MEM8(0x0625) -+#define PORTB_OUTCLR _SFR_MEM8(0x0626) -+#define PORTB_OUTTGL _SFR_MEM8(0x0627) -+#define PORTB_IN _SFR_MEM8(0x0628) -+#define PORTB_INTCTRL _SFR_MEM8(0x0629) -+#define PORTB_INT0MASK _SFR_MEM8(0x062A) -+#define PORTB_INT1MASK _SFR_MEM8(0x062B) -+#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -+#define PORTB_REMAP _SFR_MEM8(0x062E) -+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INT0MASK _SFR_MEM8(0x064A) -+#define PORTC_INT1MASK _SFR_MEM8(0x064B) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INT0MASK _SFR_MEM8(0x066A) -+#define PORTD_INT1MASK _SFR_MEM8(0x066B) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTG_DIR _SFR_MEM8(0x06C0) -+#define PORTG_DIRSET _SFR_MEM8(0x06C1) -+#define PORTG_DIRCLR _SFR_MEM8(0x06C2) -+#define PORTG_DIRTGL _SFR_MEM8(0x06C3) -+#define PORTG_OUT _SFR_MEM8(0x06C4) -+#define PORTG_OUTSET _SFR_MEM8(0x06C5) -+#define PORTG_OUTCLR _SFR_MEM8(0x06C6) -+#define PORTG_OUTTGL _SFR_MEM8(0x06C7) -+#define PORTG_IN _SFR_MEM8(0x06C8) -+#define PORTG_INTCTRL _SFR_MEM8(0x06C9) -+#define PORTG_INT0MASK _SFR_MEM8(0x06CA) -+#define PORTG_INT1MASK _SFR_MEM8(0x06CB) -+#define PORTG_INTFLAGS _SFR_MEM8(0x06CC) -+#define PORTG_REMAP _SFR_MEM8(0x06CE) -+#define PORTG_PIN0CTRL _SFR_MEM8(0x06D0) -+#define PORTG_PIN1CTRL _SFR_MEM8(0x06D1) -+#define PORTG_PIN2CTRL _SFR_MEM8(0x06D2) -+#define PORTG_PIN3CTRL _SFR_MEM8(0x06D3) -+#define PORTG_PIN4CTRL _SFR_MEM8(0x06D4) -+#define PORTG_PIN5CTRL _SFR_MEM8(0x06D5) -+#define PORTG_PIN6CTRL _SFR_MEM8(0x06D6) -+#define PORTG_PIN7CTRL _SFR_MEM8(0x06D7) -+ -+/* PORT - I/O Ports */ -+#define PORTM_DIR _SFR_MEM8(0x0760) -+#define PORTM_DIRSET _SFR_MEM8(0x0761) -+#define PORTM_DIRCLR _SFR_MEM8(0x0762) -+#define PORTM_DIRTGL _SFR_MEM8(0x0763) -+#define PORTM_OUT _SFR_MEM8(0x0764) -+#define PORTM_OUTSET _SFR_MEM8(0x0765) -+#define PORTM_OUTCLR _SFR_MEM8(0x0766) -+#define PORTM_OUTTGL _SFR_MEM8(0x0767) -+#define PORTM_IN _SFR_MEM8(0x0768) -+#define PORTM_INTCTRL _SFR_MEM8(0x0769) -+#define PORTM_INT0MASK _SFR_MEM8(0x076A) -+#define PORTM_INT1MASK _SFR_MEM8(0x076B) -+#define PORTM_INTFLAGS _SFR_MEM8(0x076C) -+#define PORTM_REMAP _SFR_MEM8(0x076E) -+#define PORTM_PIN0CTRL _SFR_MEM8(0x0770) -+#define PORTM_PIN1CTRL _SFR_MEM8(0x0771) -+#define PORTM_PIN2CTRL _SFR_MEM8(0x0772) -+#define PORTM_PIN3CTRL _SFR_MEM8(0x0773) -+#define PORTM_PIN4CTRL _SFR_MEM8(0x0774) -+#define PORTM_PIN5CTRL _SFR_MEM8(0x0775) -+#define PORTM_PIN6CTRL _SFR_MEM8(0x0776) -+#define PORTM_PIN7CTRL _SFR_MEM8(0x0777) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -+#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCC0_CTRLA _SFR_MEM8(0x0800) -+#define TCC0_CTRLB _SFR_MEM8(0x0801) -+#define TCC0_CTRLC _SFR_MEM8(0x0802) -+#define TCC0_CTRLD _SFR_MEM8(0x0803) -+#define TCC0_CTRLE _SFR_MEM8(0x0804) -+#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -+#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -+#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -+#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC0_TEMP _SFR_MEM8(0x080F) -+#define TCC0_CNT _SFR_MEM16(0x0820) -+#define TCC0_PER _SFR_MEM16(0x0826) -+#define TCC0_CCA _SFR_MEM16(0x0828) -+#define TCC0_CCB _SFR_MEM16(0x082A) -+#define TCC0_CCC _SFR_MEM16(0x082C) -+#define TCC0_CCD _SFR_MEM16(0x082E) -+#define TCC0_PERBUF _SFR_MEM16(0x0836) -+#define TCC0_CCABUF _SFR_MEM16(0x0838) -+#define TCC0_CCBBUF _SFR_MEM16(0x083A) -+#define TCC0_CCCBUF _SFR_MEM16(0x083C) -+#define TCC0_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCC1_CTRLA _SFR_MEM8(0x0840) -+#define TCC1_CTRLB _SFR_MEM8(0x0841) -+#define TCC1_CTRLC _SFR_MEM8(0x0842) -+#define TCC1_CTRLD _SFR_MEM8(0x0843) -+#define TCC1_CTRLE _SFR_MEM8(0x0844) -+#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -+#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -+#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -+#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC1_TEMP _SFR_MEM8(0x084F) -+#define TCC1_CNT _SFR_MEM16(0x0860) -+#define TCC1_PER _SFR_MEM16(0x0866) -+#define TCC1_CCA _SFR_MEM16(0x0868) -+#define TCC1_CCB _SFR_MEM16(0x086A) -+#define TCC1_PERBUF _SFR_MEM16(0x0876) -+#define TCC1_CCABUF _SFR_MEM16(0x0878) -+#define TCC1_CCBBUF _SFR_MEM16(0x087A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXC_CTRL _SFR_MEM8(0x0880) -+#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -+#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -+#define AWEXC_STATUS _SFR_MEM8(0x0884) -+#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -+#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -+#define AWEXC_DTLS _SFR_MEM8(0x0888) -+#define AWEXC_DTHS _SFR_MEM8(0x0889) -+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x0890) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08A0) -+#define USARTC0_STATUS _SFR_MEM8(0x08A1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -+#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -+#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIC_CTRL _SFR_MEM8(0x08C0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -+#define SPIC_STATUS _SFR_MEM8(0x08C2) -+#define SPIC_DATA _SFR_MEM8(0x08C3) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* LCD - LCD Controller */ -+#define LCD_CTRLA _SFR_MEM8(0x0D00) -+#define LCD_CTRLB _SFR_MEM8(0x0D01) -+#define LCD_CTRLC _SFR_MEM8(0x0D02) -+#define LCD_INTCTRL _SFR_MEM8(0x0D03) -+#define LCD_INTFLAG _SFR_MEM8(0x0D04) -+#define LCD_CTRLD _SFR_MEM8(0x0D05) -+#define LCD_CTRLE _SFR_MEM8(0x0D06) -+#define LCD_CTRLF _SFR_MEM8(0x0D07) -+#define LCD_CTRLG _SFR_MEM8(0x0D08) -+#define LCD_CTRLH _SFR_MEM8(0x0D09) -+#define LCD_DATA0 _SFR_MEM8(0x0D10) -+#define LCD_DATA1 _SFR_MEM8(0x0D11) -+#define LCD_DATA2 _SFR_MEM8(0x0D12) -+#define LCD_DATA3 _SFR_MEM8(0x0D13) -+#define LCD_DATA4 _SFR_MEM8(0x0D14) -+#define LCD_DATA5 _SFR_MEM8(0x0D15) -+#define LCD_DATA6 _SFR_MEM8(0x0D16) -+#define LCD_DATA7 _SFR_MEM8(0x0D17) -+#define LCD_DATA8 _SFR_MEM8(0x0D18) -+#define LCD_DATA9 _SFR_MEM8(0x0D19) -+#define LCD_DATA10 _SFR_MEM8(0x0D1A) -+#define LCD_DATA11 _SFR_MEM8(0x0D1B) -+#define LCD_DATA12 _SFR_MEM8(0x0D1C) -+#define LCD_DATA13 _SFR_MEM8(0x0D1D) -+#define LCD_DATA14 _SFR_MEM8(0x0D1E) -+#define LCD_DATA15 _SFR_MEM8(0x0D1F) -+#define LCD_DATA16 _SFR_MEM8(0x0D20) -+#define LCD_DATA17 _SFR_MEM8(0x0D21) -+#define LCD_DATA18 _SFR_MEM8(0x0D22) -+#define LCD_DATA19 _SFR_MEM8(0x0D23) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* VPORT - Virtual Ports */ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* CLK.USBCTRL bit masks and bit positions */ -+#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -+#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -+#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -+#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -+#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -+#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -+#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -+#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ -+ -+#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -+#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -+#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ -+ -+#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ -+#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -+#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -+#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ -+ -+#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ -+ -+#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -+#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ -+ -+/* PR - Power Reduction */ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_LCD_bm 0x80 /* LCD Module bit mask. */ -+#define PR_LCD_bp 7 /* LCD Module bit position. */ -+ -+#define PR_USB_bm 0x40 /* USB bit mask. */ -+#define PR_USB_bp 6 /* USB bit position. */ -+ -+#define PR_AES_bm 0x10 /* AES bit mask. */ -+#define PR_AES_bp 4 /* AES bit position. */ -+ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -+#define PR_DMA_bp 0 /* DMA-Controller bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPB bit masks and bit positions */ -+/* PR_ADC Predefined. */ -+/* PR_ADC Predefined. */ -+ -+/* PR_AC Predefined. */ -+/* PR_AC Predefined. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -+#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ -+ -+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -+ -+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ -+ -+/* PR.PRPE bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.MCUCR bit masks and bit positions */ -+#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -+#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ -+ -+/* MCU.ANAINIT bit masks and bit positions */ -+#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -+#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -+#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -+#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -+#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -+#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ -+ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -+#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ -+ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.AWEXLOCK bit masks and bit positions */ -+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* PORTCFG - Port Configuration */ -+/* PORTCFG.VPCTRLA bit masks and bit positions */ -+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ -+ -+/* PORTCFG.VPCTRLB bit masks and bit positions */ -+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ -+ -+/* PORTCFG.CLKEVOUT bit masks and bit positions */ -+#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ -+ -+#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -+#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -+#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -+#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -+#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -+#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ -+ -+#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -+#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ -+ -+#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -+#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ -+ -+/* PORTCFG.EVOUTSEL bit masks and bit positions */ -+#define PORTCFG_EVOUTSEL_bm 0x04 /* Event Output Select bit mask. */ -+#define PORTCFG_EVOUTSEL_bp 2 /* Event Output Select bit position. */ -+ -+/* AES - AES Module */ -+/* AES.CTRL bit masks and bit positions */ -+#define AES_START_bm 0x80 /* Start/Run bit mask. */ -+#define AES_START_bp 7 /* Start/Run bit position. */ -+ -+#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -+#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ -+ -+#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -+#define AES_RESET_bp 5 /* AES Software Reset bit position. */ -+ -+#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -+#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ -+ -+#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -+#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ -+ -+/* AES.STATUS bit masks and bit positions */ -+#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -+#define AES_ERROR_bp 7 /* AES Error bit position. */ -+ -+#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -+#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ -+ -+/* AES.INTCTRL bit masks and bit positions */ -+#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -+#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* DMA - DMA Controller */ -+/* DMA_CH.CTRLA bit masks and bit positions */ -+#define DMA_CH_CHEN_bm 0x80 /* Channel Enable bit mask. */ -+#define DMA_CH_CHEN_bp 7 /* Channel Enable bit position. */ -+ -+#define DMA_CH_CHRST_bm 0x40 /* Channel Software Reset bit mask. */ -+#define DMA_CH_CHRST_bp 6 /* Channel Software Reset bit position. */ -+ -+#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -+#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ -+ -+#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -+#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ -+ -+#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -+#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ -+ -+#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -+#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -+#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -+#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -+#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -+#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ -+ -+/* DMA_CH.CTRLB bit masks and bit positions */ -+#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -+#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ -+ -+#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -+#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ -+ -+#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -+#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ -+ -+#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -+#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -+#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -+#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -+#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -+#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ -+ -+#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -+#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -+#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -+#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -+#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -+#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ -+ -+/* DMA_CH.ADDRCTRL bit masks and bit positions */ -+#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -+#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -+#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -+#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -+#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -+#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ -+ -+#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -+#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -+#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -+#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -+#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -+#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ -+ -+#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -+#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -+#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -+#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -+#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -+#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ -+ -+#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -+#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -+#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -+#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -+#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -+#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ -+ -+/* DMA_CH.TRIGSRC bit masks and bit positions */ -+#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -+#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -+#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -+#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -+#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -+#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -+#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -+#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -+#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -+#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -+#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -+#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -+#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -+#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -+#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -+#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -+#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -+#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ -+ -+/* DMA.CTRL bit masks and bit positions */ -+#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -+#define DMA_ENABLE_bp 7 /* Enable bit position. */ -+ -+#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -+#define DMA_RESET_bp 6 /* Software Reset bit position. */ -+ -+#define DMA_DBUFMODE_bm 0x04 /* Double Buffering Mode bit mask. */ -+#define DMA_DBUFMODE_bp 2 /* Double Buffering Mode bit position. */ -+ -+#define DMA_PRIMODE_bm 0x01 /* Channel Priority Mode bit mask. */ -+#define DMA_PRIMODE_bp 0 /* Channel Priority Mode bit position. */ -+ -+/* DMA.INTFLAGS bit masks and bit positions */ -+#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ -+ -+/* DMA.STATUS bit masks and bit positions */ -+#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -+#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ -+ -+#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -+#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ -+ -+#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -+#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ -+ -+#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -+#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0x7F /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ -+ -+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ -+ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -+#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -+#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -+#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -+#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -+#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -+#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -+#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -+#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -+#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ -+ -+#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */ -+#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */ -+#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -+#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */ -+#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -+#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */ -+#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -+#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */ -+#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -+#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -+#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* ADC.SAMPCTRL bit masks and bit positions */ -+#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ -+#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ -+#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ -+#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ -+#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ -+#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ -+#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ -+#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ -+#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ -+#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ -+#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ -+#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ -+#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ -+#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* AC.CURRCTRL bit masks and bit positions */ -+#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ -+#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ -+ -+#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ -+#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ -+ -+#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ -+#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ -+ -+#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ -+#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ -+ -+/* AC.CURRCALIB bit masks and bit positions */ -+#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ -+#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ -+#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ -+#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ -+#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ -+#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ -+#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ -+#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ -+#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ -+#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ -+ -+/* RTC - Real-Time Counter */ -+/* RTC.CTRL bit masks and bit positions */ -+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ -+ -+/* RTC.STATUS bit masks and bit positions */ -+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC.INTCTRL bit masks and bit positions */ -+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC.INTFLAGS bit masks and bit positions */ -+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* USB - USB */ -+/* USB_EP.STATUS bit masks and bit positions */ -+#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -+#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ -+ -+#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -+#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ -+ -+#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -+#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ -+ -+#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -+#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ -+ -+#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -+#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ -+ -+#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -+#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ -+ -+#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -+#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ -+ -+#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -+#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ -+ -+#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ -+ -+#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ -+ -+#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -+#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ -+ -+/* USB_EP.CTRL bit masks and bit positions */ -+#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -+#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -+#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -+#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -+#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -+#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ -+ -+#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -+#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ -+ -+#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -+#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ -+ -+#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -+#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ -+ -+#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -+#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ -+ -+#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -+#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -+#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -+#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -+#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -+#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -+#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -+#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ -+ -+/* USB_EP.CNT bit masks and bit positions */ -+#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -+#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ -+ -+/* USB.CTRLA bit masks and bit positions */ -+#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -+#define USB_ENABLE_bp 7 /* USB Enable bit position. */ -+ -+#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -+#define USB_SPEED_bp 6 /* Speed Select bit position. */ -+ -+#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -+#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ -+ -+#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -+#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ -+ -+#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -+#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -+#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -+#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -+#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -+#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -+#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -+#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -+#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -+#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ -+ -+/* USB.CTRLB bit masks and bit positions */ -+#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -+#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ -+ -+#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -+#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ -+ -+#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -+#define USB_GNACK_bp 1 /* Global NACK bit position. */ -+ -+#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -+#define USB_ATTACH_bp 0 /* Attach bit position. */ -+ -+/* USB.STATUS bit masks and bit positions */ -+#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -+#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ -+ -+#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -+#define USB_RESUME_bp 2 /* Resume bit position. */ -+ -+#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -+#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ -+ -+#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -+#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ -+ -+/* USB.ADDR bit masks and bit positions */ -+#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -+#define USB_ADDR_gp 0 /* Device Address group position. */ -+#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -+#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -+#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -+#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -+#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -+#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -+#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -+#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -+#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -+#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -+#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -+#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -+#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -+#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ -+ -+/* USB.FIFOWP bit masks and bit positions */ -+#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -+#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -+#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -+#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -+#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -+#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -+#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -+#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -+#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -+#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -+#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -+#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ -+ -+/* USB.FIFORP bit masks and bit positions */ -+#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -+#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -+#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -+#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -+#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -+#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -+#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -+#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -+#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -+#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -+#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -+#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ -+ -+/* USB.INTCTRLA bit masks and bit positions */ -+#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -+#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ -+ -+#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -+#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ -+ -+#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -+#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ -+ -+#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -+#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ -+ -+#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* USB.INTCTRLB bit masks and bit positions */ -+#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -+#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ -+ -+#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -+#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ -+ -+/* USB.INTFLAGSACLR bit masks and bit positions */ -+#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -+#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ -+ -+#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -+#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ -+ -+#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -+#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ -+ -+#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -+#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ -+ -+#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -+#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ -+ -+#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -+#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ -+ -+#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -+#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ -+ -+#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -+#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSASET bit masks and bit positions */ -+/* USB_SOFIF Predefined. */ -+/* USB_SOFIF Predefined. */ -+ -+/* USB_SUSPENDIF Predefined. */ -+/* USB_SUSPENDIF Predefined. */ -+ -+/* USB_RESUMEIF Predefined. */ -+/* USB_RESUMEIF Predefined. */ -+ -+/* USB_RSTIF Predefined. */ -+/* USB_RSTIF Predefined. */ -+ -+/* USB_CRCIF Predefined. */ -+/* USB_CRCIF Predefined. */ -+ -+/* USB_UNFIF Predefined. */ -+/* USB_UNFIF Predefined. */ -+ -+/* USB_OVFIF Predefined. */ -+/* USB_OVFIF Predefined. */ -+ -+/* USB_STALLIF Predefined. */ -+/* USB_STALLIF Predefined. */ -+ -+/* USB.INTFLAGSBCLR bit masks and bit positions */ -+#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -+#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ -+ -+#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -+#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSBSET bit masks and bit positions */ -+/* USB_TRNIF Predefined. */ -+/* USB_TRNIF Predefined. */ -+ -+/* USB_SETUPIF Predefined. */ -+/* USB_SETUPIF Predefined. */ -+ -+/* PORT - I/O Port Configuration */ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ -+ -+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -+#define PORT_SPI_bp 5 /* SPI bit position. */ -+ -+#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -+#define PORT_USART0_bp 4 /* USART0 bit position. */ -+ -+#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -+#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ -+ -+#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -+#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ -+ -+#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -+#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ -+ -+#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -+#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ -+ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC0.CTRLA bit masks and bit positions */ -+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC0.CTRLB bit masks and bit positions */ -+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ -+ -+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ -+ -+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC0.CTRLC bit masks and bit positions */ -+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ -+ -+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ -+ -+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC0.CTRLD bit masks and bit positions */ -+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC0_EVACT_gp 5 /* Event Action group position. */ -+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC0.CTRLE bit masks and bit positions */ -+#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC0.INTCTRLA bit masks and bit positions */ -+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC0.INTCTRLB bit masks and bit positions */ -+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ -+ -+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ -+ -+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC0.CTRLFCLR bit masks and bit positions */ -+#define TC0_CMD_gm 0x0C /* Command group mask. */ -+#define TC0_CMD_gp 2 /* Command group position. */ -+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC0_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC0_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC0_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC0.CTRLFSET bit masks and bit positions */ -+/* TC0_CMD Predefined. */ -+/* TC0_CMD Predefined. */ -+ -+/* TC0_LUPD Predefined. */ -+/* TC0_LUPD Predefined. */ -+ -+/* TC0_DIR Predefined. */ -+/* TC0_DIR Predefined. */ -+ -+/* TC0.CTRLGCLR bit masks and bit positions */ -+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ -+ -+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ -+ -+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC0.CTRLGSET bit masks and bit positions */ -+/* TC0_CCDBV Predefined. */ -+/* TC0_CCDBV Predefined. */ -+ -+/* TC0_CCCBV Predefined. */ -+/* TC0_CCCBV Predefined. */ -+ -+/* TC0_CCBBV Predefined. */ -+/* TC0_CCBBV Predefined. */ -+ -+/* TC0_CCABV Predefined. */ -+/* TC0_CCABV Predefined. */ -+ -+/* TC0_PERBV Predefined. */ -+/* TC0_PERBV Predefined. */ -+ -+/* TC0.INTFLAGS bit masks and bit positions */ -+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ -+ -+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ -+ -+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC1.CTRLA bit masks and bit positions */ -+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC1.CTRLB bit masks and bit positions */ -+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC1.CTRLC bit masks and bit positions */ -+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC1.CTRLD bit masks and bit positions */ -+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC1_EVACT_gp 5 /* Event Action group position. */ -+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC1.CTRLE bit masks and bit positions */ -+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ -+ -+/* TC1.INTCTRLA bit masks and bit positions */ -+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC1.INTCTRLB bit masks and bit positions */ -+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC1.CTRLFCLR bit masks and bit positions */ -+#define TC1_CMD_gm 0x0C /* Command group mask. */ -+#define TC1_CMD_gp 2 /* Command group position. */ -+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC1_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC1_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC1_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC1.CTRLFSET bit masks and bit positions */ -+/* TC1_CMD Predefined. */ -+/* TC1_CMD Predefined. */ -+ -+/* TC1_LUPD Predefined. */ -+/* TC1_LUPD Predefined. */ -+ -+/* TC1_DIR Predefined. */ -+/* TC1_DIR Predefined. */ -+ -+/* TC1.CTRLGCLR bit masks and bit positions */ -+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC1.CTRLGSET bit masks and bit positions */ -+/* TC1_CCBBV Predefined. */ -+/* TC1_CCBBV Predefined. */ -+ -+/* TC1_CCABV Predefined. */ -+/* TC1_CCABV Predefined. */ -+ -+/* TC1_PERBV Predefined. */ -+/* TC1_PERBV Predefined. */ -+ -+/* TC1.INTFLAGS bit masks and bit positions */ -+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* AWEX - Timer/Counter Advanced Waveform Extension */ -+/* AWEX.CTRL bit masks and bit positions */ -+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ -+ -+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ -+ -+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ -+ -+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ -+ -+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ -+ -+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ -+ -+/* AWEX.FDCTRL bit masks and bit positions */ -+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ -+ -+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ -+ -+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ -+ -+/* AWEX.STATUS bit masks and bit positions */ -+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ -+ -+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ -+ -+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ -+ -+/* AWEX.STATUSSET bit masks and bit positions */ -+/* AWEX_FDF Predefined. */ -+/* AWEX_FDF Predefined. */ -+ -+/* AWEX_DTHSBUFV Predefined. */ -+/* AWEX_DTHSBUFV Predefined. */ -+ -+/* AWEX_DTLSBUFV Predefined. */ -+/* AWEX_DTLSBUFV Predefined. */ -+ -+/* HIRES - Timer/Counter High-Resolution Extension */ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+/* LCD - LCD Controller */ -+/* LCD.CTRLA bit masks and bit positions */ -+#define LCD_ENABLE_bm 0x80 /* LCD Enable bit mask. */ -+#define LCD_ENABLE_bp 7 /* LCD Enable bit position. */ -+ -+#define LCD_XBIAS_bm 0x40 /* External Register Bias Generation bit mask. */ -+#define LCD_XBIAS_bp 6 /* External Register Bias Generation bit position. */ -+ -+#define LCD_DATCLK_bm 0x20 /* Data Register Lock bit mask. */ -+#define LCD_DATCLK_bp 5 /* Data Register Lock bit position. */ -+ -+#define LCD_COMSWP_bm 0x10 /* Common Bus Swap bit mask. */ -+#define LCD_COMSWP_bp 4 /* Common Bus Swap bit position. */ -+ -+#define LCD_SEGSWP_bm 0x08 /* Segment Bus Swap bit mask. */ -+#define LCD_SEGSWP_bp 3 /* Segment Bus Swap bit position. */ -+ -+#define LCD_CLRDT_bm 0x04 /* Clear Data Register bit mask. */ -+#define LCD_CLRDT_bp 2 /* Clear Data Register bit position. */ -+ -+#define LCD_SEGON_bm 0x02 /* Segments On bit mask. */ -+#define LCD_SEGON_bp 1 /* Segments On bit position. */ -+ -+#define LCD_BLANK_bm 0x01 /* Blanking Display Mode bit mask. */ -+#define LCD_BLANK_bp 0 /* Blanking Display Mode bit position. */ -+ -+/* LCD.CTRLB bit masks and bit positions */ -+#define LCD_PRESC_bm 0x80 /* LCD Prescaler Select bit mask. */ -+#define LCD_PRESC_bp 7 /* LCD Prescaler Select bit position. */ -+ -+#define LCD_CLKDIV_gm 0x70 /* LCD Clock Divide group mask. */ -+#define LCD_CLKDIV_gp 4 /* LCD Clock Divide group position. */ -+#define LCD_CLKDIV0_bm (1<<4) /* LCD Clock Divide bit 0 mask. */ -+#define LCD_CLKDIV0_bp 4 /* LCD Clock Divide bit 0 position. */ -+#define LCD_CLKDIV1_bm (1<<5) /* LCD Clock Divide bit 1 mask. */ -+#define LCD_CLKDIV1_bp 5 /* LCD Clock Divide bit 1 position. */ -+#define LCD_CLKDIV2_bm (1<<6) /* LCD Clock Divide bit 2 mask. */ -+#define LCD_CLKDIV2_bp 6 /* LCD Clock Divide bit 2 position. */ -+ -+#define LCD_LPWAV_bm 0x08 /* Low Power Waveform bit mask. */ -+#define LCD_LPWAV_bp 3 /* Low Power Waveform bit position. */ -+ -+#define LCD_DUTY_gm 0x03 /* Duty Select group mask. */ -+#define LCD_DUTY_gp 0 /* Duty Select group position. */ -+#define LCD_DUTY0_bm (1<<0) /* Duty Select bit 0 mask. */ -+#define LCD_DUTY0_bp 0 /* Duty Select bit 0 position. */ -+#define LCD_DUTY1_bm (1<<1) /* Duty Select bit 1 mask. */ -+#define LCD_DUTY1_bp 1 /* Duty Select bit 1 position. */ -+ -+/* LCD.CTRLC bit masks and bit positions */ -+#define LCD_PMSK_gm 0x3F /* LCD Port Mask group mask. */ -+#define LCD_PMSK_gp 0 /* LCD Port Mask group position. */ -+#define LCD_PMSK0_bm (1<<0) /* LCD Port Mask bit 0 mask. */ -+#define LCD_PMSK0_bp 0 /* LCD Port Mask bit 0 position. */ -+#define LCD_PMSK1_bm (1<<1) /* LCD Port Mask bit 1 mask. */ -+#define LCD_PMSK1_bp 1 /* LCD Port Mask bit 1 position. */ -+#define LCD_PMSK2_bm (1<<2) /* LCD Port Mask bit 2 mask. */ -+#define LCD_PMSK2_bp 2 /* LCD Port Mask bit 2 position. */ -+#define LCD_PMSK3_bm (1<<3) /* LCD Port Mask bit 3 mask. */ -+#define LCD_PMSK3_bp 3 /* LCD Port Mask bit 3 position. */ -+#define LCD_PMSK4_bm (1<<4) /* LCD Port Mask bit 4 mask. */ -+#define LCD_PMSK4_bp 4 /* LCD Port Mask bit 4 position. */ -+#define LCD_PMSK5_bm (1<<5) /* LCD Port Mask bit 5 mask. */ -+#define LCD_PMSK5_bp 5 /* LCD Port Mask bit 5 position. */ -+ -+/* LCD.INTCTRL bit masks and bit positions */ -+#define LCD_XIME_gm 0xF8 /* eXtended Interrupt Mode Enable group mask. */ -+#define LCD_XIME_gp 3 /* eXtended Interrupt Mode Enable group position. */ -+#define LCD_XIME0_bm (1<<3) /* eXtended Interrupt Mode Enable bit 0 mask. */ -+#define LCD_XIME0_bp 3 /* eXtended Interrupt Mode Enable bit 0 position. */ -+#define LCD_XIME1_bm (1<<4) /* eXtended Interrupt Mode Enable bit 1 mask. */ -+#define LCD_XIME1_bp 4 /* eXtended Interrupt Mode Enable bit 1 position. */ -+#define LCD_XIME2_bm (1<<5) /* eXtended Interrupt Mode Enable bit 2 mask. */ -+#define LCD_XIME2_bp 5 /* eXtended Interrupt Mode Enable bit 2 position. */ -+#define LCD_XIME3_bm (1<<6) /* eXtended Interrupt Mode Enable bit 3 mask. */ -+#define LCD_XIME3_bp 6 /* eXtended Interrupt Mode Enable bit 3 position. */ -+#define LCD_XIME4_bm (1<<7) /* eXtended Interrupt Mode Enable bit 4 mask. */ -+#define LCD_XIME4_bp 7 /* eXtended Interrupt Mode Enable bit 4 position. */ -+ -+#define LCD_FCINTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define LCD_FCINTLVL_gp 0 /* Interrupt Level group position. */ -+#define LCD_FCINTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define LCD_FCINTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define LCD_FCINTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define LCD_FCINTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* LCD.INTFLAG bit masks and bit positions */ -+#define LCD_FCIF_bm 0x01 /* LCD Frame Completed Interrupt Flag bit mask. */ -+#define LCD_FCIF_bp 0 /* LCD Frame Completed Interrupt Flag bit position. */ -+ -+/* LCD.CTRLD bit masks and bit positions */ -+#define LCD_BLINKEN_bm 0x08 /* Blink Enable bit mask. */ -+#define LCD_BLINKEN_bp 3 /* Blink Enable bit position. */ -+ -+#define LCD_BLINKRATE_gm 0x03 /* LCD Blink Rate group mask. */ -+#define LCD_BLINKRATE_gp 0 /* LCD Blink Rate group position. */ -+#define LCD_BLINKRATE0_bm (1<<0) /* LCD Blink Rate bit 0 mask. */ -+#define LCD_BLINKRATE0_bp 0 /* LCD Blink Rate bit 0 position. */ -+#define LCD_BLINKRATE1_bm (1<<1) /* LCD Blink Rate bit 1 mask. */ -+#define LCD_BLINKRATE1_bp 1 /* LCD Blink Rate bit 1 position. */ -+ -+/* LCD.CTRLE bit masks and bit positions */ -+#define LCD_BPS1_gm 0xF0 /* Blink Pixel Selection 1 group mask. */ -+#define LCD_BPS1_gp 4 /* Blink Pixel Selection 1 group position. */ -+#define LCD_BPS10_bm (1<<4) /* Blink Pixel Selection 1 bit 0 mask. */ -+#define LCD_BPS10_bp 4 /* Blink Pixel Selection 1 bit 0 position. */ -+#define LCD_BPS11_bm (1<<5) /* Blink Pixel Selection 1 bit 1 mask. */ -+#define LCD_BPS11_bp 5 /* Blink Pixel Selection 1 bit 1 position. */ -+#define LCD_BPS12_bm (1<<6) /* Blink Pixel Selection 1 bit 2 mask. */ -+#define LCD_BPS12_bp 6 /* Blink Pixel Selection 1 bit 2 position. */ -+#define LCD_BPS13_bm (1<<7) /* Blink Pixel Selection 1 bit 3 mask. */ -+#define LCD_BPS13_bp 7 /* Blink Pixel Selection 1 bit 3 position. */ -+ -+#define LCD_BPS0_gm 0x0F /* Blink Pixel Selection 0 group mask. */ -+#define LCD_BPS0_gp 0 /* Blink Pixel Selection 0 group position. */ -+#define LCD_BPS00_bm (1<<0) /* Blink Pixel Selection 0 bit 0 mask. */ -+#define LCD_BPS00_bp 0 /* Blink Pixel Selection 0 bit 0 position. */ -+#define LCD_BPS01_bm (1<<1) /* Blink Pixel Selection 0 bit 1 mask. */ -+#define LCD_BPS01_bp 1 /* Blink Pixel Selection 0 bit 1 position. */ -+#define LCD_BPS02_bm (1<<2) /* Blink Pixel Selection 0 bit 2 mask. */ -+#define LCD_BPS02_bp 2 /* Blink Pixel Selection 0 bit 2 position. */ -+#define LCD_BPS03_bm (1<<3) /* Blink Pixel Selection 0 bit 3 mask. */ -+#define LCD_BPS03_bp 3 /* Blink Pixel Selection 0 bit 3 position. */ -+ -+/* LCD.CTRLF bit masks and bit positions */ -+#define LCD_FCONT_gm 0x3F /* Fine Contrast group mask. */ -+#define LCD_FCONT_gp 0 /* Fine Contrast group position. */ -+#define LCD_FCONT0_bm (1<<0) /* Fine Contrast bit 0 mask. */ -+#define LCD_FCONT0_bp 0 /* Fine Contrast bit 0 position. */ -+#define LCD_FCONT1_bm (1<<1) /* Fine Contrast bit 1 mask. */ -+#define LCD_FCONT1_bp 1 /* Fine Contrast bit 1 position. */ -+#define LCD_FCONT2_bm (1<<2) /* Fine Contrast bit 2 mask. */ -+#define LCD_FCONT2_bp 2 /* Fine Contrast bit 2 position. */ -+#define LCD_FCONT3_bm (1<<3) /* Fine Contrast bit 3 mask. */ -+#define LCD_FCONT3_bp 3 /* Fine Contrast bit 3 position. */ -+#define LCD_FCONT4_bm (1<<4) /* Fine Contrast bit 4 mask. */ -+#define LCD_FCONT4_bp 4 /* Fine Contrast bit 4 position. */ -+#define LCD_FCONT5_bm (1<<5) /* Fine Contrast bit 5 mask. */ -+#define LCD_FCONT5_bp 5 /* Fine Contrast bit 5 position. */ -+ -+/* LCD.CTRLG bit masks and bit positions */ -+#define LCD_TDG_gm 0xC0 /* Type of Digit group mask. */ -+#define LCD_TDG_gp 6 /* Type of Digit group position. */ -+#define LCD_TDG0_bm (1<<6) /* Type of Digit bit 0 mask. */ -+#define LCD_TDG0_bp 6 /* Type of Digit bit 0 position. */ -+#define LCD_TDG1_bm (1<<7) /* Type of Digit bit 1 mask. */ -+#define LCD_TDG1_bp 7 /* Type of Digit bit 1 position. */ -+ -+#define LCD_STSEG_gm 0x3F /* Start Segment group mask. */ -+#define LCD_STSEG_gp 0 /* Start Segment group position. */ -+#define LCD_STSEG0_bm (1<<0) /* Start Segment bit 0 mask. */ -+#define LCD_STSEG0_bp 0 /* Start Segment bit 0 position. */ -+#define LCD_STSEG1_bm (1<<1) /* Start Segment bit 1 mask. */ -+#define LCD_STSEG1_bp 1 /* Start Segment bit 1 position. */ -+#define LCD_STSEG2_bm (1<<2) /* Start Segment bit 2 mask. */ -+#define LCD_STSEG2_bp 2 /* Start Segment bit 2 position. */ -+#define LCD_STSEG3_bm (1<<3) /* Start Segment bit 3 mask. */ -+#define LCD_STSEG3_bp 3 /* Start Segment bit 3 position. */ -+#define LCD_STSEG4_bm (1<<4) /* Start Segment bit 4 mask. */ -+#define LCD_STSEG4_bp 4 /* Start Segment bit 4 position. */ -+#define LCD_STSEG5_bm (1<<5) /* Start Segment bit 5 mask. */ -+#define LCD_STSEG5_bp 5 /* Start Segment bit 5 position. */ -+ -+/* LCD.CTRLH bit masks and bit positions */ -+#define LCD_DEC_bm 0x80 /* Decrement of Start Segment bit mask. */ -+#define LCD_DEC_bp 7 /* Decrement of Start Segment bit position. */ -+ -+#define LCD_DCODE_gm 0x7F /* Display Code group mask. */ -+#define LCD_DCODE_gp 0 /* Display Code group position. */ -+#define LCD_DCODE0_bm (1<<0) /* Display Code bit 0 mask. */ -+#define LCD_DCODE0_bp 0 /* Display Code bit 0 position. */ -+#define LCD_DCODE1_bm (1<<1) /* Display Code bit 1 mask. */ -+#define LCD_DCODE1_bp 1 /* Display Code bit 1 position. */ -+#define LCD_DCODE2_bm (1<<2) /* Display Code bit 2 mask. */ -+#define LCD_DCODE2_bp 2 /* Display Code bit 2 position. */ -+#define LCD_DCODE3_bm (1<<3) /* Display Code bit 3 mask. */ -+#define LCD_DCODE3_bp 3 /* Display Code bit 3 position. */ -+#define LCD_DCODE4_bm (1<<4) /* Display Code bit 4 mask. */ -+#define LCD_DCODE4_bp 4 /* Display Code bit 4 position. */ -+#define LCD_DCODE5_bm (1<<5) /* Display Code bit 5 mask. */ -+#define LCD_DCODE5_bp 5 /* Display Code bit 5 position. */ -+#define LCD_DCODE6_bm (1<<6) /* Display Code bit 6 mask. */ -+#define LCD_DCODE6_bp 6 /* Display Code bit 6 position. */ -+ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -+#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -+#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -+#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -+#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -+#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -+#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -+#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -+#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -+#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -+#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -+#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -+#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -+#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -+#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -+#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -+#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -+#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -+#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ -+ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -+#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -+#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* LOCKBIT - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT0_vect_num 2 -+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -+#define PORTC_INT1_vect_num 3 -+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT0_vect_num 4 -+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -+#define PORTR_INT1_vect_num 5 -+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ -+ -+/* DMA interrupt vectors */ -+#define DMA_CH0_vect_num 6 -+#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -+#define DMA_CH1_vect_num 7 -+#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -+ -+/* RTC interrupt vectors */ -+#define RTC_OVF_vect_num 10 -+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -+#define RTC_COMP_vect_num 11 -+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 12 -+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 13 -+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_OVF_vect_num 14 -+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -+#define TCC0_ERR_vect_num 15 -+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -+#define TCC0_CCA_vect_num 16 -+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -+#define TCC0_CCB_vect_num 17 -+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -+#define TCC0_CCC_vect_num 18 -+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -+#define TCC0_CCD_vect_num 19 -+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ -+ -+/* TCC1 interrupt vectors */ -+#define TCC1_OVF_vect_num 20 -+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -+#define TCC1_ERR_vect_num 21 -+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -+#define TCC1_CCA_vect_num 22 -+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -+#define TCC1_CCB_vect_num 23 -+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 24 -+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 25 -+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 26 -+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 27 -+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ -+ -+/* USB interrupt vectors */ -+#define USB_BUSEVENT_vect_num 31 -+#define USB_BUSEVENT_vect _VECTOR(31) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -+#define USB_TRNCOMPL_vect_num 32 -+#define USB_TRNCOMPL_vect _VECTOR(32) /* Transaction complete interrupt */ -+ -+/* LCD interrupt vectors */ -+#define LCD_INT_vect_num 35 -+#define LCD_INT_vect _VECTOR(35) /* LCD Interrupt */ -+ -+/* AES interrupt vectors */ -+#define AES_INT_vect_num 36 -+#define AES_INT_vect _VECTOR(36) /* AES Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 37 -+#define NVM_EE_vect _VECTOR(37) /* EE Interrupt */ -+#define NVM_SPM_vect_num 38 -+#define NVM_SPM_vect _VECTOR(38) /* SPM Interrupt */ -+ -+/* PORTB interrupt vectors */ -+#define PORTB_INT0_vect_num 39 -+#define PORTB_INT0_vect _VECTOR(39) /* External Interrupt 0 */ -+#define PORTB_INT1_vect_num 40 -+#define PORTB_INT1_vect _VECTOR(40) /* External Interrupt 1 */ -+ -+/* ACB interrupt vectors */ -+#define ACB_AC0_vect_num 41 -+#define ACB_AC0_vect _VECTOR(41) /* AC0 Interrupt */ -+#define ACB_AC1_vect_num 42 -+#define ACB_AC1_vect _VECTOR(42) /* AC1 Interrupt */ -+#define ACB_ACW_vect_num 43 -+#define ACB_ACW_vect _VECTOR(43) /* ACW Window Mode Interrupt */ -+ -+/* ADCB interrupt vectors */ -+#define ADCB_CH0_vect_num 44 -+#define ADCB_CH0_vect _VECTOR(44) /* Interrupt 0 */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT0_vect_num 48 -+#define PORTD_INT0_vect _VECTOR(48) /* External Interrupt 0 */ -+#define PORTD_INT1_vect_num 49 -+#define PORTD_INT1_vect _VECTOR(49) /* External Interrupt 1 */ -+ -+/* PORTG interrupt vectors */ -+#define PORTG_INT0_vect_num 50 -+#define PORTG_INT0_vect _VECTOR(50) /* External Interrupt 0 */ -+#define PORTG_INT1_vect_num 51 -+#define PORTG_INT1_vect _VECTOR(51) /* External Interrupt 1 */ -+ -+/* PORTM interrupt vectors */ -+#define PORTM_INT0_vect_num 52 -+#define PORTM_INT0_vect _VECTOR(52) /* External Interrupt 0 */ -+#define PORTM_INT1_vect_num 53 -+#define PORTM_INT1_vect _VECTOR(53) /* External Interrupt 1 */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (54 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (139264) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (131072) -+#define APP_SECTION_PAGE_SIZE (256) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0x1E000) -+#define APPTABLE_SECTION_SIZE (8192) -+#define APPTABLE_SECTION_PAGE_SIZE (256) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x20000) -+#define BOOT_SECTION_SIZE (8192) -+#define BOOT_SECTION_PAGE_SIZE (256) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (16384) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (2048) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (8192) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (2048) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (6) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (256) -+#define USER_SIGNATURES_PAGE_SIZE (256) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (52) -+#define PROD_SIGNATURES_PAGE_SIZE (256) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 256 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 6 -+ -+/* Fuse Byte 0 */ -+#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -+#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -+#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -+#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -+#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -+#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -+#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -+#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -+#define FUSE0_DEFAULT (0xFF) -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x97 -+#define SIGNATURE_2 0x4B -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA128B3_H_INCLUDED */ -+ -diff --git a/include/avr/iox128c3.h b/include/avr/iox128c3.h -new file mode 100644 -index 0000000..348c2ec ---- /dev/null -+++ b/include/avr/iox128c3.h -@@ -0,0 +1,6216 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox128c3.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA128C3_H_INCLUDED -+#define _AVR_ATXMEGA128C3_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+VPORT - Virtual Ports -+-------------------------------------------------------------------------- -+*/ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t USBCTRL; /* USB Control Register */ -+} CLK_t; -+ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t reserved_0x02; -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t PRPD; /* Power Reduction Port D */ -+ register8_t PRPE; /* Power Reduction Port E */ -+ register8_t PRPF; /* Power Reduction Port F */ -+} PR_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+/* USB Prescaler Division Factor */ -+typedef enum CLK_USBPSDIV_enum -+{ -+ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ -+ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ -+ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ -+ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ -+ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ -+ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -+} CLK_USBPSDIV_t; -+ -+/* USB Clock Source */ -+typedef enum CLK_USBSRC_enum -+{ -+ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ -+ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -+} CLK_USBSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control Register */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+/* 2 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC2MCREF_enum -+{ -+ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC2MCREF_t; -+ -+/* 32 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC32MCREF_enum -+{ -+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -+} OSC_RC32MCREF_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t ANAINIT; /* Analog Startup Delay */ -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t AWEXLOCK; /* AWEX Lock */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORTCFG - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t VPCTRLA; /* Virtual Port Control Register A */ -+ register8_t VPCTRLB; /* Virtual Port Control Register B */ -+ register8_t CLKEVOUT; /* Clock and Event Out Register */ -+ register8_t reserved_0x05; -+ register8_t EVOUTSEL; /* Event Output Select */ -+} PORTCFG_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP02MAP_enum -+{ -+ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ -+ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ -+ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ -+ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ -+ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ -+ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ -+ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ -+ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ -+ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ -+ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ -+ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ -+ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ -+ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ -+ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ -+ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ -+ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -+} PORTCFG_VP02MAP_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP13MAP_enum -+{ -+ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ -+ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ -+ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ -+ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ -+ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ -+ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ -+ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ -+ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ -+ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ -+ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ -+ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ -+ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ -+ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ -+ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ -+ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ -+ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -+} PORTCFG_VP13MAP_t; -+ -+/* System Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ -+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ -+ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -+} PORTCFG_CLKOUT_t; -+ -+/* Peripheral Clock Output Select */ -+typedef enum PORTCFG_CLKOUTSEL_enum -+{ -+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -+} PORTCFG_CLKOUTSEL_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ -+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ -+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -+} PORTCFG_EVOUT_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+} EVSYS_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ -+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ -+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ -+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ -+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ -+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ -+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ -+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ -+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ -+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ -+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ -+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ -+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ -+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ -+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ -+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ -+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ -+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ -+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ -+ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ -+ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ -+ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ -+ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ -+ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ -+ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ -+ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ -+ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ -+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ -+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ -+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ -+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ -+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ -+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ -+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ -+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ -+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ -+ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ -+ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ -+ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ -+ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ -+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ -+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ -+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ -+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ -+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -+ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ -+ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ -+ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ -+ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ -+ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -+} EVSYS_CHMUX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ -+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ -+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ -+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ -+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} NVM_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t reserved_0x07; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+} ADC_t; -+ -+/* Current Limitation */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -+} ADC_CURRLIMIT_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+} ADC_CH_MUXNEG_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ -+ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ -+ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ -+ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC - Real-Time Counter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Real-Time Counter */ -+typedef struct RTC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary register */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ _WORDREGISTER(CNT); /* Count Register */ -+ _WORDREGISTER(PER); /* Period Register */ -+ _WORDREGISTER(COMP); /* Compare Register */ -+} RTC_t; -+ -+/* Prescaler Factor */ -+typedef enum RTC_PRESCALER_enum -+{ -+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ -+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ -+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ -+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ -+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ -+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ -+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ -+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -+} RTC_PRESCALER_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC_COMPINTLVL_enum -+{ -+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC_OVFINTLVL_enum -+{ -+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+} TWI_t; -+ -+/* SDA Hold Time */ -+typedef enum TWI_SDAHOLD_enum -+{ -+ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ -+ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ -+ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ -+ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -+} TWI_SDAHOLD_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USB - USB -+-------------------------------------------------------------------------- -+*/ -+ -+/* USB Endpoint */ -+typedef struct USB_EP_struct -+{ -+ register8_t STATUS; /* Endpoint Status */ -+ register8_t CTRL; /* Endpoint Control */ -+ _WORDREGISTER(CNT); /* USB Endpoint Counter */ -+ _WORDREGISTER(DATAPTR); /* Data Pointer */ -+ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -+} USB_EP_t; -+ -+ -+/* Universal Serial Bus */ -+typedef struct USB_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t FIFOWP; /* FIFO Write Pointer Register */ -+ register8_t FIFORP; /* FIFO Read Pointer Register */ -+ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ -+ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ -+ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ -+ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t reserved_0x20; -+ register8_t reserved_0x21; -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t CAL0; /* Calibration Byte 0 */ -+ register8_t CAL1; /* Calibration Byte 1 */ -+} USB_t; -+ -+ -+/* USB Endpoint Table */ -+typedef struct USB_EP_TABLE_struct -+{ -+ USB_EP_t EP0OUT; /* Endpoint 0 */ -+ USB_EP_t EP0IN; /* Endpoint 0 */ -+ USB_EP_t EP1OUT; /* Endpoint 1 */ -+ USB_EP_t EP1IN; /* Endpoint 1 */ -+ USB_EP_t EP2OUT; /* Endpoint 2 */ -+ USB_EP_t EP2IN; /* Endpoint 2 */ -+ USB_EP_t EP3OUT; /* Endpoint 3 */ -+ USB_EP_t EP3IN; /* Endpoint 3 */ -+ USB_EP_t EP4OUT; /* Endpoint 4 */ -+ USB_EP_t EP4IN; /* Endpoint 4 */ -+ USB_EP_t EP5OUT; /* Endpoint 5 */ -+ USB_EP_t EP5IN; /* Endpoint 5 */ -+ USB_EP_t EP6OUT; /* Endpoint 6 */ -+ USB_EP_t EP6IN; /* Endpoint 6 */ -+ USB_EP_t EP7OUT; /* Endpoint 7 */ -+ USB_EP_t EP7IN; /* Endpoint 7 */ -+ USB_EP_t EP8OUT; /* Endpoint 8 */ -+ USB_EP_t EP8IN; /* Endpoint 8 */ -+ USB_EP_t EP9OUT; /* Endpoint 9 */ -+ USB_EP_t EP9IN; /* Endpoint 9 */ -+ USB_EP_t EP10OUT; /* Endpoint 10 */ -+ USB_EP_t EP10IN; /* Endpoint 10 */ -+ USB_EP_t EP11OUT; /* Endpoint 11 */ -+ USB_EP_t EP11IN; /* Endpoint 11 */ -+ USB_EP_t EP12OUT; /* Endpoint 12 */ -+ USB_EP_t EP12IN; /* Endpoint 12 */ -+ USB_EP_t EP13OUT; /* Endpoint 13 */ -+ USB_EP_t EP13IN; /* Endpoint 13 */ -+ USB_EP_t EP14OUT; /* Endpoint 14 */ -+ USB_EP_t EP14IN; /* Endpoint 14 */ -+ USB_EP_t EP15OUT; /* Endpoint 15 */ -+ USB_EP_t EP15IN; /* Endpoint 15 */ -+ register8_t reserved_0x100; -+ register8_t reserved_0x101; -+ register8_t reserved_0x102; -+ register8_t reserved_0x103; -+ register8_t reserved_0x104; -+ register8_t reserved_0x105; -+ register8_t reserved_0x106; -+ register8_t reserved_0x107; -+ register8_t reserved_0x108; -+ register8_t reserved_0x109; -+ register8_t reserved_0x10A; -+ register8_t reserved_0x10B; -+ register8_t reserved_0x10C; -+ register8_t reserved_0x10D; -+ register8_t reserved_0x10E; -+ register8_t reserved_0x10F; -+ register8_t FRAMENUML; /* Frame Number Low Byte */ -+ register8_t FRAMENUMH; /* Frame Number High Byte */ -+} USB_EP_TABLE_t; -+ -+/* Interrupt level */ -+typedef enum USB_INTLVL_enum -+{ -+ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} USB_INTLVL_t; -+ -+/* USB Endpoint Type */ -+typedef enum USB_EP_TYPE_enum -+{ -+ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ -+ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ -+ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ -+ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -+} USB_EP_TYPE_t; -+ -+/* USB Endpoint Buffersize */ -+typedef enum USB_EP_BUFSIZE_enum -+{ -+ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ -+ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ -+ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ -+ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ -+ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ -+ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ -+ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ -+ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -+} USB_EP_BUFSIZE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - I/O Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INT0MASK; /* Port Interrupt 0 Mask */ -+ register8_t INT1MASK; /* Port Interrupt 1 Mask */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t REMAP; /* I/O Port Pin Remap Register */ -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Port Interrupt 0 Level */ -+typedef enum PORT_INT0LVL_enum -+{ -+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INT0LVL_t; -+ -+/* Port Interrupt 1 Level */ -+typedef enum PORT_INT1LVL_enum -+{ -+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ -+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ -+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -+} PORT_INT1LVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 0 */ -+typedef struct TC0_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC0_t; -+ -+ -+/* 16-bit Timer/Counter 1 */ -+typedef struct TC1_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+} TC1_t; -+ -+/* Clock Selection */ -+typedef enum TC_CLKSEL_enum -+{ -+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_CLKSEL_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC_WGMODE_enum -+{ -+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC_WGMODE_t; -+ -+/* Byte Mode */ -+typedef enum TC_BYTEM_enum -+{ -+ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ -+ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -+} TC_BYTEM_t; -+ -+/* Event Action */ -+typedef enum TC_EVACT_enum -+{ -+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ -+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ -+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ -+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ -+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ -+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC_EVSEL_enum -+{ -+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_EVSEL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC_ERRINTLVL_enum -+{ -+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC_OVFINTLVL_enum -+{ -+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_OVFINTLVL_t; -+ -+/* Compare or Capture D Interrupt Level */ -+typedef enum TC_CCDINTLVL_enum -+{ -+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC_CCDINTLVL_t; -+ -+/* Compare or Capture C Interrupt Level */ -+typedef enum TC_CCCINTLVL_enum -+{ -+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC_CCCINTLVL_t; -+ -+/* Compare or Capture B Interrupt Level */ -+typedef enum TC_CCBINTLVL_enum -+{ -+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_CCBINTLVL_t; -+ -+/* Compare or Capture A Interrupt Level */ -+typedef enum TC_CCAINTLVL_enum -+{ -+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_CCAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC_CMD_enum -+{ -+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC2 - 16-bit Timer/Counter type 2 -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter type 2 */ -+typedef struct TC2_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t reserved_0x03; -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t reserved_0x08; -+ register8_t CTRLF; /* Control Register F */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t LCNT; /* Low Byte Count */ -+ register8_t HCNT; /* High Byte Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t LPER; /* Low Byte Period */ -+ register8_t HPER; /* High Byte Period */ -+ register8_t LCMPA; /* Low Byte Compare A */ -+ register8_t HCMPA; /* High Byte Compare A */ -+ register8_t LCMPB; /* Low Byte Compare B */ -+ register8_t HCMPB; /* High Byte Compare B */ -+ register8_t LCMPC; /* Low Byte Compare C */ -+ register8_t HCMPC; /* High Byte Compare C */ -+ register8_t LCMPD; /* Low Byte Compare D */ -+ register8_t HCMPD; /* High Byte Compare D */ -+} TC2_t; -+ -+/* Clock Selection */ -+typedef enum TC2_CLKSEL_enum -+{ -+ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC2_CLKSEL_t; -+ -+/* Byte Mode */ -+typedef enum TC2_BYTEM_enum -+{ -+ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ -+ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -+} TC2_BYTEM_t; -+ -+/* High Byte Underflow Interrupt Level */ -+typedef enum TC2_HUNFINTLVL_enum -+{ -+ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_HUNFINTLVL_t; -+ -+/* Low Byte Underflow Interrupt Level */ -+typedef enum TC2_LUNFINTLVL_enum -+{ -+ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LUNFINTLVL_t; -+ -+/* Low Byte Compare D Interrupt Level */ -+typedef enum TC2_LCMPDINTLVL_enum -+{ -+ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC2_LCMPDINTLVL_t; -+ -+/* Low Byte Compare C Interrupt Level */ -+typedef enum TC2_LCMPCINTLVL_enum -+{ -+ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC2_LCMPCINTLVL_t; -+ -+/* Low Byte Compare B Interrupt Level */ -+typedef enum TC2_LCMPBINTLVL_enum -+{ -+ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_LCMPBINTLVL_t; -+ -+/* Low Byte Compare A Interrupt Level */ -+typedef enum TC2_LCMPAINTLVL_enum -+{ -+ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LCMPAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMD_enum -+{ -+ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC2_CMD_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMDEN_enum -+{ -+ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ -+ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ -+ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -+} TC2_CMDEN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AWEX - Timer/Counter Advanced Waveform Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Advanced Waveform Extension */ -+typedef struct AWEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t FDEMASK; /* Fault Detection Event Mask */ -+ register8_t FDCTRL; /* Fault Detection Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t STATUSSET; /* Status Set Register */ -+ register8_t DTBOTH; /* Dead Time Both Sides */ -+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ -+ register8_t DTLS; /* Dead Time Low Side */ -+ register8_t DTHS; /* Dead Time High Side */ -+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ -+ register8_t DTHSBUF; /* Dead Time High Side Buffer */ -+ register8_t OUTOVEN; /* Output Override Enable */ -+} AWEX_t; -+ -+/* Fault Detect Action */ -+typedef enum AWEX_FDACT_enum -+{ -+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ -+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -+} AWEX_FDACT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+HIRES - Timer/Counter High-Resolution Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register */ -+} HIRES_t; -+ -+/* High Resolution Enable */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ -+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+} IRDA_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t reserved_0x00; -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+} NVM_FUSES_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* Timer Oscillator pin location */ -+typedef enum TOSCSEL_enum -+{ -+ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ -+ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -+} TOSCSEL_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -+} BOD_t; -+ -+/* BOD operation */ -+typedef enum BODACT_enum -+{ -+ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BODACT_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WDP_enum -+{ -+ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ -+ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ -+ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ -+ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ -+ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ -+ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ -+ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ -+ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ -+ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ -+ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ -+ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -+} WDP_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LOCKBIT - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ -+ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t USBCAL0; /* USB Calibration Byte 0 */ -+ register8_t USBCAL1; /* USB Calibration Byte 1 */ -+ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ -+ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+} NVM_PROD_SIGNATURES_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -+#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -+#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -+#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -+#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -+#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -+#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -+#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -+#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -+#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -+#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -+#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -+#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+#define CLK_USBCTRL _SFR_MEM8(0x0044) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* DFLL - DFLL */ -+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -+#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -+#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPD _SFR_MEM8(0x0074) -+#define PR_PRPE _SFR_MEM8(0x0075) -+#define PR_PRPF _SFR_MEM8(0x0076) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_ANAINIT _SFR_MEM8(0x0097) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_AWEXLOCK _SFR_MEM8(0x0099) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCA_CTRLA _SFR_MEM8(0x0200) -+#define ADCA_CTRLB _SFR_MEM8(0x0201) -+#define ADCA_REFCTRL _SFR_MEM8(0x0202) -+#define ADCA_EVCTRL _SFR_MEM8(0x0203) -+#define ADCA_PRESCALER _SFR_MEM8(0x0204) -+#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -+#define ADCA_TEMP _SFR_MEM8(0x0207) -+#define ADCA_CAL _SFR_MEM16(0x020C) -+#define ADCA_CH0RES _SFR_MEM16(0x0210) -+#define ADCA_CMP _SFR_MEM16(0x0218) -+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -+#define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -+ -+/* AC - Analog Comparator */ -+#define ACA_AC0CTRL _SFR_MEM8(0x0380) -+#define ACA_AC1CTRL _SFR_MEM8(0x0381) -+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -+#define ACA_CTRLA _SFR_MEM8(0x0384) -+#define ACA_CTRLB _SFR_MEM8(0x0385) -+#define ACA_WINCTRL _SFR_MEM8(0x0386) -+#define ACA_STATUS _SFR_MEM8(0x0387) -+ -+/* RTC - Real-Time Counter */ -+#define RTC_CTRL _SFR_MEM8(0x0400) -+#define RTC_STATUS _SFR_MEM8(0x0401) -+#define RTC_INTCTRL _SFR_MEM8(0x0402) -+#define RTC_INTFLAGS _SFR_MEM8(0x0403) -+#define RTC_TEMP _SFR_MEM8(0x0404) -+#define RTC_CNT _SFR_MEM16(0x0408) -+#define RTC_PER _SFR_MEM16(0x040A) -+#define RTC_COMP _SFR_MEM16(0x040C) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIE_CTRL _SFR_MEM8(0x04A0) -+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -+ -+/* USB - Universal Serial Bus */ -+#define USB_CTRLA _SFR_MEM8(0x04C0) -+#define USB_CTRLB _SFR_MEM8(0x04C1) -+#define USB_STATUS _SFR_MEM8(0x04C2) -+#define USB_ADDR _SFR_MEM8(0x04C3) -+#define USB_FIFOWP _SFR_MEM8(0x04C4) -+#define USB_FIFORP _SFR_MEM8(0x04C5) -+#define USB_EPPTR _SFR_MEM16(0x04C6) -+#define USB_INTCTRLA _SFR_MEM8(0x04C8) -+#define USB_INTCTRLB _SFR_MEM8(0x04C9) -+#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -+#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -+#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -+#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -+#define USB_CAL0 _SFR_MEM8(0x04FA) -+#define USB_CAL1 _SFR_MEM8(0x04FB) -+ -+/* PORT - I/O Ports */ -+#define PORTA_DIR _SFR_MEM8(0x0600) -+#define PORTA_DIRSET _SFR_MEM8(0x0601) -+#define PORTA_DIRCLR _SFR_MEM8(0x0602) -+#define PORTA_DIRTGL _SFR_MEM8(0x0603) -+#define PORTA_OUT _SFR_MEM8(0x0604) -+#define PORTA_OUTSET _SFR_MEM8(0x0605) -+#define PORTA_OUTCLR _SFR_MEM8(0x0606) -+#define PORTA_OUTTGL _SFR_MEM8(0x0607) -+#define PORTA_IN _SFR_MEM8(0x0608) -+#define PORTA_INTCTRL _SFR_MEM8(0x0609) -+#define PORTA_INT0MASK _SFR_MEM8(0x060A) -+#define PORTA_INT1MASK _SFR_MEM8(0x060B) -+#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_REMAP _SFR_MEM8(0x060E) -+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -+ -+/* PORT - I/O Ports */ -+#define PORTB_DIR _SFR_MEM8(0x0620) -+#define PORTB_DIRSET _SFR_MEM8(0x0621) -+#define PORTB_DIRCLR _SFR_MEM8(0x0622) -+#define PORTB_DIRTGL _SFR_MEM8(0x0623) -+#define PORTB_OUT _SFR_MEM8(0x0624) -+#define PORTB_OUTSET _SFR_MEM8(0x0625) -+#define PORTB_OUTCLR _SFR_MEM8(0x0626) -+#define PORTB_OUTTGL _SFR_MEM8(0x0627) -+#define PORTB_IN _SFR_MEM8(0x0628) -+#define PORTB_INTCTRL _SFR_MEM8(0x0629) -+#define PORTB_INT0MASK _SFR_MEM8(0x062A) -+#define PORTB_INT1MASK _SFR_MEM8(0x062B) -+#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -+#define PORTB_REMAP _SFR_MEM8(0x062E) -+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INT0MASK _SFR_MEM8(0x064A) -+#define PORTC_INT1MASK _SFR_MEM8(0x064B) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INT0MASK _SFR_MEM8(0x066A) -+#define PORTD_INT1MASK _SFR_MEM8(0x066B) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTE_DIR _SFR_MEM8(0x0680) -+#define PORTE_DIRSET _SFR_MEM8(0x0681) -+#define PORTE_DIRCLR _SFR_MEM8(0x0682) -+#define PORTE_DIRTGL _SFR_MEM8(0x0683) -+#define PORTE_OUT _SFR_MEM8(0x0684) -+#define PORTE_OUTSET _SFR_MEM8(0x0685) -+#define PORTE_OUTCLR _SFR_MEM8(0x0686) -+#define PORTE_OUTTGL _SFR_MEM8(0x0687) -+#define PORTE_IN _SFR_MEM8(0x0688) -+#define PORTE_INTCTRL _SFR_MEM8(0x0689) -+#define PORTE_INT0MASK _SFR_MEM8(0x068A) -+#define PORTE_INT1MASK _SFR_MEM8(0x068B) -+#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -+#define PORTE_REMAP _SFR_MEM8(0x068E) -+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) -+ -+/* PORT - I/O Ports */ -+#define PORTF_DIR _SFR_MEM8(0x06A0) -+#define PORTF_DIRSET _SFR_MEM8(0x06A1) -+#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -+#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -+#define PORTF_OUT _SFR_MEM8(0x06A4) -+#define PORTF_OUTSET _SFR_MEM8(0x06A5) -+#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -+#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -+#define PORTF_IN _SFR_MEM8(0x06A8) -+#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -+#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -+#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -+#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -+#define PORTF_REMAP _SFR_MEM8(0x06AE) -+#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -+#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -+#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -+#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -+#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -+#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -+#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -+#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -+#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCC0_CTRLA _SFR_MEM8(0x0800) -+#define TCC0_CTRLB _SFR_MEM8(0x0801) -+#define TCC0_CTRLC _SFR_MEM8(0x0802) -+#define TCC0_CTRLD _SFR_MEM8(0x0803) -+#define TCC0_CTRLE _SFR_MEM8(0x0804) -+#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -+#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -+#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -+#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC0_TEMP _SFR_MEM8(0x080F) -+#define TCC0_CNT _SFR_MEM16(0x0820) -+#define TCC0_PER _SFR_MEM16(0x0826) -+#define TCC0_CCA _SFR_MEM16(0x0828) -+#define TCC0_CCB _SFR_MEM16(0x082A) -+#define TCC0_CCC _SFR_MEM16(0x082C) -+#define TCC0_CCD _SFR_MEM16(0x082E) -+#define TCC0_PERBUF _SFR_MEM16(0x0836) -+#define TCC0_CCABUF _SFR_MEM16(0x0838) -+#define TCC0_CCBBUF _SFR_MEM16(0x083A) -+#define TCC0_CCCBUF _SFR_MEM16(0x083C) -+#define TCC0_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCC2_CTRLA _SFR_MEM8(0x0800) -+#define TCC2_CTRLB _SFR_MEM8(0x0801) -+#define TCC2_CTRLC _SFR_MEM8(0x0802) -+#define TCC2_CTRLE _SFR_MEM8(0x0804) -+#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC2_CTRLF _SFR_MEM8(0x0809) -+#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC2_LCNT _SFR_MEM8(0x0820) -+#define TCC2_HCNT _SFR_MEM8(0x0821) -+#define TCC2_LPER _SFR_MEM8(0x0826) -+#define TCC2_HPER _SFR_MEM8(0x0827) -+#define TCC2_LCMPA _SFR_MEM8(0x0828) -+#define TCC2_HCMPA _SFR_MEM8(0x0829) -+#define TCC2_LCMPB _SFR_MEM8(0x082A) -+#define TCC2_HCMPB _SFR_MEM8(0x082B) -+#define TCC2_LCMPC _SFR_MEM8(0x082C) -+#define TCC2_HCMPC _SFR_MEM8(0x082D) -+#define TCC2_LCMPD _SFR_MEM8(0x082E) -+#define TCC2_HCMPD _SFR_MEM8(0x082F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCC1_CTRLA _SFR_MEM8(0x0840) -+#define TCC1_CTRLB _SFR_MEM8(0x0841) -+#define TCC1_CTRLC _SFR_MEM8(0x0842) -+#define TCC1_CTRLD _SFR_MEM8(0x0843) -+#define TCC1_CTRLE _SFR_MEM8(0x0844) -+#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -+#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -+#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -+#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC1_TEMP _SFR_MEM8(0x084F) -+#define TCC1_CNT _SFR_MEM16(0x0860) -+#define TCC1_PER _SFR_MEM16(0x0866) -+#define TCC1_CCA _SFR_MEM16(0x0868) -+#define TCC1_CCB _SFR_MEM16(0x086A) -+#define TCC1_PERBUF _SFR_MEM16(0x0876) -+#define TCC1_CCABUF _SFR_MEM16(0x0878) -+#define TCC1_CCBBUF _SFR_MEM16(0x087A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXC_CTRL _SFR_MEM8(0x0880) -+#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -+#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -+#define AWEXC_STATUS _SFR_MEM8(0x0884) -+#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -+#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -+#define AWEXC_DTLS _SFR_MEM8(0x0888) -+#define AWEXC_DTHS _SFR_MEM8(0x0889) -+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x0890) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08A0) -+#define USARTC0_STATUS _SFR_MEM8(0x08A1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -+#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -+#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIC_CTRL _SFR_MEM8(0x08C0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -+#define SPIC_STATUS _SFR_MEM8(0x08C2) -+#define SPIC_DATA _SFR_MEM8(0x08C3) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCD0_CTRLA _SFR_MEM8(0x0900) -+#define TCD0_CTRLB _SFR_MEM8(0x0901) -+#define TCD0_CTRLC _SFR_MEM8(0x0902) -+#define TCD0_CTRLD _SFR_MEM8(0x0903) -+#define TCD0_CTRLE _SFR_MEM8(0x0904) -+#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -+#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -+#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -+#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -+#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD0_TEMP _SFR_MEM8(0x090F) -+#define TCD0_CNT _SFR_MEM16(0x0920) -+#define TCD0_PER _SFR_MEM16(0x0926) -+#define TCD0_CCA _SFR_MEM16(0x0928) -+#define TCD0_CCB _SFR_MEM16(0x092A) -+#define TCD0_CCC _SFR_MEM16(0x092C) -+#define TCD0_CCD _SFR_MEM16(0x092E) -+#define TCD0_PERBUF _SFR_MEM16(0x0936) -+#define TCD0_CCABUF _SFR_MEM16(0x0938) -+#define TCD0_CCBBUF _SFR_MEM16(0x093A) -+#define TCD0_CCCBUF _SFR_MEM16(0x093C) -+#define TCD0_CCDBUF _SFR_MEM16(0x093E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCD2_CTRLA _SFR_MEM8(0x0900) -+#define TCD2_CTRLB _SFR_MEM8(0x0901) -+#define TCD2_CTRLC _SFR_MEM8(0x0902) -+#define TCD2_CTRLE _SFR_MEM8(0x0904) -+#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD2_CTRLF _SFR_MEM8(0x0909) -+#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD2_LCNT _SFR_MEM8(0x0920) -+#define TCD2_HCNT _SFR_MEM8(0x0921) -+#define TCD2_LPER _SFR_MEM8(0x0926) -+#define TCD2_HPER _SFR_MEM8(0x0927) -+#define TCD2_LCMPA _SFR_MEM8(0x0928) -+#define TCD2_HCMPA _SFR_MEM8(0x0929) -+#define TCD2_LCMPB _SFR_MEM8(0x092A) -+#define TCD2_HCMPB _SFR_MEM8(0x092B) -+#define TCD2_LCMPC _SFR_MEM8(0x092C) -+#define TCD2_HCMPC _SFR_MEM8(0x092D) -+#define TCD2_LCMPD _SFR_MEM8(0x092E) -+#define TCD2_HCMPD _SFR_MEM8(0x092F) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD0_DATA _SFR_MEM8(0x09A0) -+#define USARTD0_STATUS _SFR_MEM8(0x09A1) -+#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -+#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -+#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPID_CTRL _SFR_MEM8(0x09C0) -+#define SPID_INTCTRL _SFR_MEM8(0x09C1) -+#define SPID_STATUS _SFR_MEM8(0x09C2) -+#define SPID_DATA _SFR_MEM8(0x09C3) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCE0_CTRLA _SFR_MEM8(0x0A00) -+#define TCE0_CTRLB _SFR_MEM8(0x0A01) -+#define TCE0_CTRLC _SFR_MEM8(0x0A02) -+#define TCE0_CTRLD _SFR_MEM8(0x0A03) -+#define TCE0_CTRLE _SFR_MEM8(0x0A04) -+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE0_TEMP _SFR_MEM8(0x0A0F) -+#define TCE0_CNT _SFR_MEM16(0x0A20) -+#define TCE0_PER _SFR_MEM16(0x0A26) -+#define TCE0_CCA _SFR_MEM16(0x0A28) -+#define TCE0_CCB _SFR_MEM16(0x0A2A) -+#define TCE0_CCC _SFR_MEM16(0x0A2C) -+#define TCE0_CCD _SFR_MEM16(0x0A2E) -+#define TCE0_PERBUF _SFR_MEM16(0x0A36) -+#define TCE0_CCABUF _SFR_MEM16(0x0A38) -+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCE2_CTRLA _SFR_MEM8(0x0A00) -+#define TCE2_CTRLB _SFR_MEM8(0x0A01) -+#define TCE2_CTRLC _SFR_MEM8(0x0A02) -+#define TCE2_CTRLE _SFR_MEM8(0x0A04) -+#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE2_CTRLF _SFR_MEM8(0x0A09) -+#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE2_LCNT _SFR_MEM8(0x0A20) -+#define TCE2_HCNT _SFR_MEM8(0x0A21) -+#define TCE2_LPER _SFR_MEM8(0x0A26) -+#define TCE2_HPER _SFR_MEM8(0x0A27) -+#define TCE2_LCMPA _SFR_MEM8(0x0A28) -+#define TCE2_HCMPA _SFR_MEM8(0x0A29) -+#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -+#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -+#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -+#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -+#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -+#define TCE2_HCMPD _SFR_MEM8(0x0A2F) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE0_DATA _SFR_MEM8(0x0AA0) -+#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -+#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -+#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -+#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -+#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -+#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCF0_CTRLA _SFR_MEM8(0x0B00) -+#define TCF0_CTRLB _SFR_MEM8(0x0B01) -+#define TCF0_CTRLC _SFR_MEM8(0x0B02) -+#define TCF0_CTRLD _SFR_MEM8(0x0B03) -+#define TCF0_CTRLE _SFR_MEM8(0x0B04) -+#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -+#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -+#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -+#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -+#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -+#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -+#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -+#define TCF0_TEMP _SFR_MEM8(0x0B0F) -+#define TCF0_CNT _SFR_MEM16(0x0B20) -+#define TCF0_PER _SFR_MEM16(0x0B26) -+#define TCF0_CCA _SFR_MEM16(0x0B28) -+#define TCF0_CCB _SFR_MEM16(0x0B2A) -+#define TCF0_CCC _SFR_MEM16(0x0B2C) -+#define TCF0_CCD _SFR_MEM16(0x0B2E) -+#define TCF0_PERBUF _SFR_MEM16(0x0B36) -+#define TCF0_CCABUF _SFR_MEM16(0x0B38) -+#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -+#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -+#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCF2_CTRLA _SFR_MEM8(0x0B00) -+#define TCF2_CTRLB _SFR_MEM8(0x0B01) -+#define TCF2_CTRLC _SFR_MEM8(0x0B02) -+#define TCF2_CTRLE _SFR_MEM8(0x0B04) -+#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -+#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -+#define TCF2_CTRLF _SFR_MEM8(0x0B09) -+#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -+#define TCF2_LCNT _SFR_MEM8(0x0B20) -+#define TCF2_HCNT _SFR_MEM8(0x0B21) -+#define TCF2_LPER _SFR_MEM8(0x0B26) -+#define TCF2_HPER _SFR_MEM8(0x0B27) -+#define TCF2_LCMPA _SFR_MEM8(0x0B28) -+#define TCF2_HCMPA _SFR_MEM8(0x0B29) -+#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -+#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -+#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -+#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -+#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -+#define TCF2_HCMPD _SFR_MEM8(0x0B2F) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* VPORT - Virtual Ports */ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* CLK.USBCTRL bit masks and bit positions */ -+#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -+#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -+#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -+#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -+#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -+#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -+#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -+#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ -+ -+#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -+#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -+#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ -+ -+#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_USB_bm 0x40 /* USB bit mask. */ -+#define PR_USB_bp 6 /* USB bit position. */ -+ -+#define PR_AES_bm 0x10 /* AES bit mask. */ -+#define PR_AES_bp 4 /* AES bit position. */ -+ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -+#define PR_DMA_bp 0 /* DMA-Controller bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -+#define PR_USART1_bp 5 /* Port C USART1 bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -+#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ -+ -+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -+ -+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ -+ -+/* PR.PRPD bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPE bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPF bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -+#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -+#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ -+ -+#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ -+ -+#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -+#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.ANAINIT bit masks and bit positions */ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.AWEXLOCK bit masks and bit positions */ -+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* PORTCFG - Port Configuration */ -+/* PORTCFG.VPCTRLA bit masks and bit positions */ -+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ -+ -+/* PORTCFG.VPCTRLB bit masks and bit positions */ -+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ -+ -+/* PORTCFG.CLKEVOUT bit masks and bit positions */ -+#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ -+ -+#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -+#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -+#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -+#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -+#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -+#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ -+ -+#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -+#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ -+ -+#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -+#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ -+ -+/* PORTCFG.EVOUTSEL bit masks and bit positions */ -+#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -+#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -+#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -+#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -+#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -+#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -+#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -+#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0x7F /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ -+ -+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ -+ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -+#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -+#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -+#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -+#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -+#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -+#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -+#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -+#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -+#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ -+ -+#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -+#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -+#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -+#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -+#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -+#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -+#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -+#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -+#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -+#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -+#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* RTC - Real-Time Counter */ -+/* RTC.CTRL bit masks and bit positions */ -+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ -+ -+/* RTC.STATUS bit masks and bit positions */ -+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC.INTCTRL bit masks and bit positions */ -+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC.INTFLAGS bit masks and bit positions */ -+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* USB - USB */ -+/* USB_EP.STATUS bit masks and bit positions */ -+#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -+#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ -+ -+#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -+#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ -+ -+#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -+#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ -+ -+#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -+#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ -+ -+#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -+#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ -+ -+#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -+#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ -+ -+#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -+#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ -+ -+#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -+#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ -+ -+#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ -+ -+#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ -+ -+#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -+#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ -+ -+/* USB_EP.CTRL bit masks and bit positions */ -+#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -+#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -+#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -+#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -+#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -+#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ -+ -+#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -+#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ -+ -+#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -+#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ -+ -+#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -+#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ -+ -+#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -+#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ -+ -+#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -+#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -+#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -+#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -+#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -+#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -+#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -+#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ -+ -+/* USB_EP.CNT bit masks and bit positions */ -+#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -+#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ -+ -+/* USB.CTRLA bit masks and bit positions */ -+#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -+#define USB_ENABLE_bp 7 /* USB Enable bit position. */ -+ -+#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -+#define USB_SPEED_bp 6 /* Speed Select bit position. */ -+ -+#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -+#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ -+ -+#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -+#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ -+ -+#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -+#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -+#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -+#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -+#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -+#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -+#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -+#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -+#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -+#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ -+ -+/* USB.CTRLB bit masks and bit positions */ -+#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -+#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ -+ -+#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -+#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ -+ -+#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -+#define USB_GNACK_bp 1 /* Global NACK bit position. */ -+ -+#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -+#define USB_ATTACH_bp 0 /* Attach bit position. */ -+ -+/* USB.STATUS bit masks and bit positions */ -+#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -+#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ -+ -+#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -+#define USB_RESUME_bp 2 /* Resume bit position. */ -+ -+#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -+#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ -+ -+#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -+#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ -+ -+/* USB.ADDR bit masks and bit positions */ -+#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -+#define USB_ADDR_gp 0 /* Device Address group position. */ -+#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -+#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -+#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -+#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -+#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -+#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -+#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -+#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -+#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -+#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -+#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -+#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -+#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -+#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ -+ -+/* USB.FIFOWP bit masks and bit positions */ -+#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -+#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -+#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -+#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -+#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -+#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -+#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -+#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -+#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -+#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -+#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -+#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ -+ -+/* USB.FIFORP bit masks and bit positions */ -+#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -+#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -+#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -+#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -+#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -+#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -+#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -+#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -+#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -+#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -+#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -+#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ -+ -+/* USB.INTCTRLA bit masks and bit positions */ -+#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -+#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ -+ -+#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -+#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ -+ -+#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -+#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ -+ -+#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -+#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ -+ -+#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* USB.INTCTRLB bit masks and bit positions */ -+#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -+#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ -+ -+#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -+#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ -+ -+/* USB.INTFLAGSACLR bit masks and bit positions */ -+#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -+#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ -+ -+#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -+#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ -+ -+#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -+#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ -+ -+#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -+#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ -+ -+#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -+#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ -+ -+#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -+#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ -+ -+#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -+#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ -+ -+#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -+#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSASET bit masks and bit positions */ -+/* USB_SOFIF Predefined. */ -+/* USB_SOFIF Predefined. */ -+ -+/* USB_SUSPENDIF Predefined. */ -+/* USB_SUSPENDIF Predefined. */ -+ -+/* USB_RESUMEIF Predefined. */ -+/* USB_RESUMEIF Predefined. */ -+ -+/* USB_RSTIF Predefined. */ -+/* USB_RSTIF Predefined. */ -+ -+/* USB_CRCIF Predefined. */ -+/* USB_CRCIF Predefined. */ -+ -+/* USB_UNFIF Predefined. */ -+/* USB_UNFIF Predefined. */ -+ -+/* USB_OVFIF Predefined. */ -+/* USB_OVFIF Predefined. */ -+ -+/* USB_STALLIF Predefined. */ -+/* USB_STALLIF Predefined. */ -+ -+/* USB.INTFLAGSBCLR bit masks and bit positions */ -+#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -+#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ -+ -+#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -+#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSBSET bit masks and bit positions */ -+/* USB_TRNIF Predefined. */ -+/* USB_TRNIF Predefined. */ -+ -+/* USB_SETUPIF Predefined. */ -+/* USB_SETUPIF Predefined. */ -+ -+/* PORT - I/O Port Configuration */ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ -+ -+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -+#define PORT_SPI_bp 5 /* SPI bit position. */ -+ -+#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -+#define PORT_USART0_bp 4 /* USART0 bit position. */ -+ -+#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -+#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ -+ -+#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -+#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ -+ -+#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -+#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ -+ -+#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -+#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ -+ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC0.CTRLA bit masks and bit positions */ -+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC0.CTRLB bit masks and bit positions */ -+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ -+ -+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ -+ -+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC0.CTRLC bit masks and bit positions */ -+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ -+ -+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ -+ -+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC0.CTRLD bit masks and bit positions */ -+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC0_EVACT_gp 5 /* Event Action group position. */ -+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC0.CTRLE bit masks and bit positions */ -+#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC0.INTCTRLA bit masks and bit positions */ -+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC0.INTCTRLB bit masks and bit positions */ -+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ -+ -+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ -+ -+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC0.CTRLFCLR bit masks and bit positions */ -+#define TC0_CMD_gm 0x0C /* Command group mask. */ -+#define TC0_CMD_gp 2 /* Command group position. */ -+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC0_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC0_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC0_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC0.CTRLFSET bit masks and bit positions */ -+/* TC0_CMD Predefined. */ -+/* TC0_CMD Predefined. */ -+ -+/* TC0_LUPD Predefined. */ -+/* TC0_LUPD Predefined. */ -+ -+/* TC0_DIR Predefined. */ -+/* TC0_DIR Predefined. */ -+ -+/* TC0.CTRLGCLR bit masks and bit positions */ -+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ -+ -+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ -+ -+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC0.CTRLGSET bit masks and bit positions */ -+/* TC0_CCDBV Predefined. */ -+/* TC0_CCDBV Predefined. */ -+ -+/* TC0_CCCBV Predefined. */ -+/* TC0_CCCBV Predefined. */ -+ -+/* TC0_CCBBV Predefined. */ -+/* TC0_CCBBV Predefined. */ -+ -+/* TC0_CCABV Predefined. */ -+/* TC0_CCABV Predefined. */ -+ -+/* TC0_PERBV Predefined. */ -+/* TC0_PERBV Predefined. */ -+ -+/* TC0.INTFLAGS bit masks and bit positions */ -+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ -+ -+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ -+ -+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC1.CTRLA bit masks and bit positions */ -+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC1.CTRLB bit masks and bit positions */ -+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC1.CTRLC bit masks and bit positions */ -+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC1.CTRLD bit masks and bit positions */ -+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC1_EVACT_gp 5 /* Event Action group position. */ -+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC1.CTRLE bit masks and bit positions */ -+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ -+ -+/* TC1.INTCTRLA bit masks and bit positions */ -+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC1.INTCTRLB bit masks and bit positions */ -+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC1.CTRLFCLR bit masks and bit positions */ -+#define TC1_CMD_gm 0x0C /* Command group mask. */ -+#define TC1_CMD_gp 2 /* Command group position. */ -+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC1_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC1_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC1_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC1.CTRLFSET bit masks and bit positions */ -+/* TC1_CMD Predefined. */ -+/* TC1_CMD Predefined. */ -+ -+/* TC1_LUPD Predefined. */ -+/* TC1_LUPD Predefined. */ -+ -+/* TC1_DIR Predefined. */ -+/* TC1_DIR Predefined. */ -+ -+/* TC1.CTRLGCLR bit masks and bit positions */ -+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC1.CTRLGSET bit masks and bit positions */ -+/* TC1_CCBBV Predefined. */ -+/* TC1_CCBBV Predefined. */ -+ -+/* TC1_CCABV Predefined. */ -+/* TC1_CCABV Predefined. */ -+ -+/* TC1_PERBV Predefined. */ -+/* TC1_PERBV Predefined. */ -+ -+/* TC1.INTFLAGS bit masks and bit positions */ -+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+/* TC2.CTRLA bit masks and bit positions */ -+#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC2.CTRLB bit masks and bit positions */ -+#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -+#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ -+ -+#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -+#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ -+ -+#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -+#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ -+ -+#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -+#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ -+ -+#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -+#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ -+ -+#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -+#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ -+ -+#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -+#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ -+ -+#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -+#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ -+ -+/* TC2.CTRLC bit masks and bit positions */ -+#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -+#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ -+ -+#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -+#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ -+ -+#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -+#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ -+ -+#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -+#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ -+ -+#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -+#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ -+ -+#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -+#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ -+ -+#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -+#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ -+ -+#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -+#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ -+ -+/* TC2.CTRLE bit masks and bit positions */ -+#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC2.INTCTRLA bit masks and bit positions */ -+#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -+#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -+#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -+#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -+#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -+#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ -+ -+#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -+#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -+#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -+#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -+#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -+#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ -+ -+/* TC2.INTCTRLB bit masks and bit positions */ -+#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -+#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -+#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -+#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -+#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -+#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -+#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -+#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -+#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -+#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -+#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -+#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -+#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -+#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -+#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -+#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -+#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -+#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -+#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -+#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -+#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ -+ -+/* TC2.CTRLF bit masks and bit positions */ -+#define TC2_CMD_gm 0x0C /* Command group mask. */ -+#define TC2_CMD_gp 2 /* Command group position. */ -+#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC2_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -+#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -+#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -+#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -+#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -+#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ -+ -+/* TC2.INTFLAGS bit masks and bit positions */ -+#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -+#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ -+ -+#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -+#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ -+ -+#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -+#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ -+ -+#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -+#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ -+ -+#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ -+ -+#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ -+ -+/* AWEX - Timer/Counter Advanced Waveform Extension */ -+/* AWEX.CTRL bit masks and bit positions */ -+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ -+ -+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ -+ -+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ -+ -+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ -+ -+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ -+ -+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ -+ -+/* AWEX.FDCTRL bit masks and bit positions */ -+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ -+ -+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ -+ -+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ -+ -+/* AWEX.STATUS bit masks and bit positions */ -+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ -+ -+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ -+ -+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ -+ -+/* AWEX.STATUSSET bit masks and bit positions */ -+/* AWEX_FDF Predefined. */ -+/* AWEX_FDF Predefined. */ -+ -+/* AWEX_DTHSBUFV Predefined. */ -+/* AWEX_DTHSBUFV Predefined. */ -+ -+/* AWEX_DTLSBUFV Predefined. */ -+/* AWEX_DTLSBUFV Predefined. */ -+ -+/* HIRES - Timer/Counter High-Resolution Extension */ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -+#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* LOCKBIT - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT0_vect_num 2 -+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -+#define PORTC_INT1_vect_num 3 -+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT0_vect_num 4 -+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -+#define PORTR_INT1_vect_num 5 -+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ -+ -+/* RTC interrupt vectors */ -+#define RTC_OVF_vect_num 10 -+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -+#define RTC_COMP_vect_num 11 -+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 12 -+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 13 -+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_OVF_vect_num 14 -+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LUNF_vect_num 14 -+#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_ERR_vect_num 15 -+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_HUNF_vect_num 15 -+#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCA_vect_num 16 -+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPA_vect_num 16 -+#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCB_vect_num 17 -+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPB_vect_num 17 -+#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCC_vect_num 18 -+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPC_vect_num 18 -+#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCD_vect_num 19 -+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPD_vect_num 19 -+#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ -+ -+/* TCC1 interrupt vectors */ -+#define TCC1_OVF_vect_num 20 -+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -+#define TCC1_ERR_vect_num 21 -+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -+#define TCC1_CCA_vect_num 22 -+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -+#define TCC1_CCB_vect_num 23 -+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 24 -+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 25 -+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 26 -+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 27 -+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 32 -+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -+#define NVM_SPM_vect_num 33 -+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ -+ -+/* PORTB interrupt vectors */ -+#define PORTB_INT0_vect_num 34 -+#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -+#define PORTB_INT1_vect_num 35 -+#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ -+ -+/* PORTE interrupt vectors */ -+#define PORTE_INT0_vect_num 43 -+#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -+#define PORTE_INT1_vect_num 44 -+#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ -+ -+/* TWIE interrupt vectors */ -+#define TWIE_TWIS_vect_num 45 -+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -+#define TWIE_TWIM_vect_num 46 -+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_OVF_vect_num 47 -+#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LUNF_vect_num 47 -+#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_ERR_vect_num 48 -+#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_HUNF_vect_num 48 -+#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCA_vect_num 49 -+#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPA_vect_num 49 -+#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCB_vect_num 50 -+#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPB_vect_num 50 -+#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCC_vect_num 51 -+#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPC_vect_num 51 -+#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCD_vect_num 52 -+#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPD_vect_num 52 -+#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ -+ -+/* USARTE0 interrupt vectors */ -+#define USARTE0_RXC_vect_num 58 -+#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -+#define USARTE0_DRE_vect_num 59 -+#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -+#define USARTE0_TXC_vect_num 60 -+#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT0_vect_num 64 -+#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -+#define PORTD_INT1_vect_num 65 -+#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ -+ -+/* PORTA interrupt vectors */ -+#define PORTA_INT0_vect_num 66 -+#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -+#define PORTA_INT1_vect_num 67 -+#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ -+ -+/* ACA interrupt vectors */ -+#define ACA_AC0_vect_num 68 -+#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -+#define ACA_AC1_vect_num 69 -+#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -+#define ACA_ACW_vect_num 70 -+#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ -+ -+/* ADCA interrupt vectors */ -+#define ADCA_CH0_vect_num 71 -+#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_OVF_vect_num 77 -+#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LUNF_vect_num 77 -+#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_ERR_vect_num 78 -+#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_HUNF_vect_num 78 -+#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCA_vect_num 79 -+#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPA_vect_num 79 -+#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCB_vect_num 80 -+#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPB_vect_num 80 -+#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCC_vect_num 81 -+#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPC_vect_num 81 -+#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCD_vect_num 82 -+#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPD_vect_num 82 -+#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ -+ -+/* SPID interrupt vectors */ -+#define SPID_INT_vect_num 87 -+#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ -+ -+/* USARTD0 interrupt vectors */ -+#define USARTD0_RXC_vect_num 88 -+#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -+#define USARTD0_DRE_vect_num 89 -+#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -+#define USARTD0_TXC_vect_num 90 -+#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ -+ -+/* PORTF interrupt vectors */ -+#define PORTF_INT0_vect_num 104 -+#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -+#define PORTF_INT1_vect_num 105 -+#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_OVF_vect_num 108 -+#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LUNF_vect_num 108 -+#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_ERR_vect_num 109 -+#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_HUNF_vect_num 109 -+#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCA_vect_num 110 -+#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPA_vect_num 110 -+#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCB_vect_num 111 -+#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPB_vect_num 111 -+#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCC_vect_num 112 -+#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPC_vect_num 112 -+#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCD_vect_num 113 -+#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPD_vect_num 113 -+#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ -+ -+/* USB interrupt vectors */ -+#define USB_BUSEVENT_vect_num 125 -+#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -+#define USB_TRNCOMPL_vect_num 126 -+#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (127 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (139264) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (131072) -+#define APP_SECTION_PAGE_SIZE (512) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0x1E000) -+#define APPTABLE_SECTION_SIZE (8192) -+#define APPTABLE_SECTION_PAGE_SIZE (512) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x20000) -+#define BOOT_SECTION_SIZE (8192) -+#define BOOT_SECTION_PAGE_SIZE (512) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (16384) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (2048) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (8192) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (2048) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (6) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (512) -+#define USER_SIGNATURES_PAGE_SIZE (512) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (64) -+#define PROD_SIGNATURES_PAGE_SIZE (512) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 512 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 6 -+ -+/* Fuse Byte 0 Reserved */ -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x97 -+#define SIGNATURE_2 0x52 -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA128C3_H_INCLUDED */ -+ -diff --git a/include/avr/iox128d3.h b/include/avr/iox128d3.h -index df0ce13..8872ceb 100644 ---- a/include/avr/iox128d3.h -+++ b/include/avr/iox128d3.h -@@ -174,7 +174,7 @@ typedef struct PR_struct - { - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ +- ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox128a1u.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA128A1U_H_INCLUDED ++#define _AVR_ATXMEGA128A1U_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t USBCTRL; /* USB Control Register */ ++} CLK_t; ++ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t PRPB; /* Power Reduction Port B */ ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++/* USB Prescaler Division Factor */ ++typedef enum CLK_USBPSDIV_enum ++{ ++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ ++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ ++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ ++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ ++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ ++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ ++} CLK_USBPSDIV_t; ++ ++/* USB Clock Source */ ++typedef enum CLK_USBSRC_enum ++{ ++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ ++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ ++} CLK_USBSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 2 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC2MCREF_enum ++{ ++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC2MCREF_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++ register8_t EBIOUT; /* EBI Output register */ ++ register8_t EVOUTSEL; /* Event Output Select */ ++} PORTCFG_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP02MAP_enum ++{ ++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP02MAP_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP13MAP_enum ++{ ++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP13MAP_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Clock and Event Output Port */ ++typedef enum PORTCFG_CLKEVPIN_enum ++{ ++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ ++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ ++} PORTCFG_CLKEVPIN_t; ++ ++/* EBI Address Output Port */ ++typedef enum PORTCFG_EBIADROUT_enum ++{ ++ PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ ++ PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ ++ PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ ++ PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ ++} PORTCFG_EBIADROUT_t; ++ ++/* EBI Chip Select Output Port */ ++typedef enum PORTCFG_EBICSOUT_enum ++{ ++ PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ ++} PORTCFG_EBICSOUT_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ ++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ ++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ ++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ ++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AES - AES Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* AES Module */ ++typedef struct AES_struct ++{ ++ register8_t CTRL; /* AES Control Register */ ++ register8_t STATUS; /* AES Status Register */ ++ register8_t STATE; /* AES State Register */ ++ register8_t KEY; /* AES Key Register */ ++ register8_t INTCTRL; /* AES Interrupt Control Register */ ++} AES_t; ++ ++/* Interrupt level */ ++typedef enum AES_INTLVL_enum ++{ ++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} AES_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ ++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ ++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ ++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Channel */ ++typedef struct DMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Address Control */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ ++ register8_t REPCNT; /* Channel Repeat Count */ ++ register8_t reserved_0x07; ++ register8_t SRCADDR0; /* Channel Source Address 0 */ ++ register8_t SRCADDR1; /* Channel Source Address 1 */ ++ register8_t SRCADDR2; /* Channel Source Address 2 */ ++ register8_t reserved_0x0B; ++ register8_t DESTADDR0; /* Channel Destination Address 0 */ ++ register8_t DESTADDR1; /* Channel Destination Address 1 */ ++ register8_t DESTADDR2; /* Channel Destination Address 2 */ ++ register8_t reserved_0x0F; ++} DMA_CH_t; ++ ++ ++/* DMA Controller */ ++typedef struct DMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ DMA_CH_t CH0; /* DMA Channel 0 */ ++ DMA_CH_t CH1; /* DMA Channel 1 */ ++ DMA_CH_t CH2; /* DMA Channel 2 */ ++ DMA_CH_t CH3; /* DMA Channel 3 */ ++} DMA_t; ++ ++/* Burst mode */ ++typedef enum DMA_CH_BURSTLEN_enum ++{ ++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ ++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ ++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ ++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ ++} DMA_CH_BURSTLEN_t; ++ ++/* Source address reload mode */ ++typedef enum DMA_CH_SRCRELOAD_enum ++{ ++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ ++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ ++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ ++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ ++} DMA_CH_SRCRELOAD_t; ++ ++/* Source addressing mode */ ++typedef enum DMA_CH_SRCDIR_enum ++{ ++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ ++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ ++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ ++} DMA_CH_SRCDIR_t; ++ ++/* Destination adress reload mode */ ++typedef enum DMA_CH_DESTRELOAD_enum ++{ ++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ ++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ ++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ ++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ ++} DMA_CH_DESTRELOAD_t; ++ ++/* Destination adressing mode */ ++typedef enum DMA_CH_DESTDIR_enum ++{ ++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ ++} DMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum DMA_CH_TRIGSRC_enum ++{ ++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ ++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ ++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ ++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ ++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ ++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ ++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ ++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ ++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ ++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ ++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ ++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ ++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ ++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ ++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ ++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ ++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ ++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ ++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ ++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ ++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ ++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ ++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ ++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ ++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ ++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ ++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ ++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ ++} DMA_CH_TRIGSRC_t; ++ ++/* Double buffering mode */ ++typedef enum DMA_DBUFMODE_enum ++{ ++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ ++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ ++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ ++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ ++} DMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum DMA_PRIMODE_enum ++{ ++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ ++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ ++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ ++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ ++} DMA_PRIMODE_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_ERRINTLVL_enum ++{ ++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ ++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ ++} DMA_CH_ERRINTLVL_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_TRNINTLVL_enum ++{ ++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ ++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ ++} DMA_CH_TRNINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ ++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ ++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ ++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t CH4CTRL; /* Channel 4 Control Register */ ++ register8_t CH5CTRL; /* Channel 5 Control Register */ ++ register8_t CH6CTRL; /* Channel 6 Control Register */ ++ register8_t CH7CTRL; /* Channel 7 Control Register */ ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ ++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ ++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ ++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ ++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ ++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ ++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ ++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ ++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ ++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ ++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ ++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ ++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ ++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ ++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ ++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ ++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ ++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t reserved_0x07; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ _WORDREGISTER(CH1RES); /* Channel 1 Result */ ++ _WORDREGISTER(CH2RES); /* Channel 2 Result */ ++ _WORDREGISTER(CH3RES); /* Channel 3 Result */ ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++ ADC_CH_t CH1; /* ADC Channel 1 */ ++ ADC_CH_t CH2; /* ADC Channel 2 */ ++ ADC_CH_t CH3; /* ADC Channel 3 */ ++} ADC_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ ++ ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ ++ ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ ++ ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Current Limitation Mode */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ ++} ADC_CURRLIMIT_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Channel sweep selection */ ++typedef enum ADC_SWEEP_enum ++{ ++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ ++} ADC_SWEEP_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* DMA request selection */ ++typedef enum ADC_DMASEL_enum ++{ ++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ ++} ADC_DMASEL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DAC - Digital/Analog Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Digital-to-Analog Converter */ ++typedef struct DAC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t EVCTRL; /* Event Input Control */ ++ register8_t reserved_0x04; ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0GAINCAL; /* Gain Calibration */ ++ register8_t CH0OFFSETCAL; /* Offset Calibration */ ++ register8_t CH1GAINCAL; /* Gain Calibration */ ++ register8_t CH1OFFSETCAL; /* Offset Calibration */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ ++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ ++} DAC_t; ++ ++/* Output channel selection */ ++typedef enum DAC_CHSEL_enum ++{ ++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ ++ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ ++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ ++} DAC_CHSEL_t; ++ ++/* Reference voltage selection */ ++typedef enum DAC_REFSEL_enum ++{ ++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ ++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ ++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ ++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ ++} DAC_REFSEL_t; ++ ++/* Event channel selection */ ++typedef enum DAC_EVSEL_enum ++{ ++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ ++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ ++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ ++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ ++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ ++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ ++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ ++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ ++} DAC_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* EBI Chip Select Module */ ++typedef struct EBI_CS_struct ++{ ++ register8_t CTRLA; /* Chip Select Control Register A */ ++ register8_t CTRLB; /* Chip Select Control Register B */ ++ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ ++} EBI_CS_t; ++ ++ ++/* External Bus Interface */ ++typedef struct EBI_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ ++ register8_t reserved_0x02; ++ register8_t reserved_0x03; ++ _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ ++ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ ++ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ ++ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ EBI_CS_t CS0; /* Chip Select 0 */ ++ EBI_CS_t CS1; /* Chip Select 1 */ ++ EBI_CS_t CS2; /* Chip Select 2 */ ++ EBI_CS_t CS3; /* Chip Select 3 */ ++} EBI_t; ++ ++/* Chip Select adress space */ ++typedef enum EBI_CS_ASPACE_enum ++{ ++ EBI_CS_ASPACE_256B_gc = (0x00<<2), /* 256 bytes */ ++ EBI_CS_ASPACE_512B_gc = (0x01<<2), /* 512 bytes */ ++ EBI_CS_ASPACE_1KB_gc = (0x02<<2), /* 1K bytes */ ++ EBI_CS_ASPACE_2KB_gc = (0x03<<2), /* 2K bytes */ ++ EBI_CS_ASPACE_4KB_gc = (0x04<<2), /* 4K bytes */ ++ EBI_CS_ASPACE_8KB_gc = (0x05<<2), /* 8K bytes */ ++ EBI_CS_ASPACE_16KB_gc = (0x06<<2), /* 16K bytes */ ++ EBI_CS_ASPACE_32KB_gc = (0x07<<2), /* 32K bytes */ ++ EBI_CS_ASPACE_64KB_gc = (0x08<<2), /* 64K bytes */ ++ EBI_CS_ASPACE_128KB_gc = (0x09<<2), /* 128K bytes */ ++ EBI_CS_ASPACE_256KB_gc = (0x0A<<2), /* 256K bytes */ ++ EBI_CS_ASPACE_512KB_gc = (0x0B<<2), /* 512K bytes */ ++ EBI_CS_ASPACE_1MB_gc = (0x0C<<2), /* 1M bytes */ ++ EBI_CS_ASPACE_2MB_gc = (0x0D<<2), /* 2M bytes */ ++ EBI_CS_ASPACE_4MB_gc = (0x0E<<2), /* 4M bytes */ ++ EBI_CS_ASPACE_8MB_gc = (0x0F<<2), /* 8M bytes */ ++ EBI_CS_ASPACE_16M_gc = (0x10<<2), /* 16M bytes */ ++} EBI_CS_ASPACE_t; ++ ++/* SRAM Wait State Selection */ ++typedef enum EBI_CS_SRWS_enum ++{ ++ EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycles */ ++ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_CS_SRWS_t; ++ ++/* Chip Select address mode */ ++typedef enum EBI_CS_MODE_enum ++{ ++ EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ ++ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ ++ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ ++ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ ++} EBI_CS_MODE_t; ++ ++/* Chip Select SDRAM mode */ ++typedef enum EBI_CS_SDMODE_enum ++{ ++ EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ ++ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ ++} EBI_CS_SDMODE_t; ++ ++/* */ ++typedef enum EBI_SDDATAW_enum ++{ ++ EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ ++ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ ++} EBI_SDDATAW_t; ++ ++/* */ ++typedef enum EBI_LPCMODE_enum ++{ ++ EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ ++ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ ++} EBI_LPCMODE_t; ++ ++/* */ ++typedef enum EBI_SRMODE_enum ++{ ++ EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ ++ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ ++ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ ++ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ ++} EBI_SRMODE_t; ++ ++/* */ ++typedef enum EBI_IFMODE_enum ++{ ++ EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ ++ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ ++ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ ++ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ ++} EBI_IFMODE_t; ++ ++/* */ ++typedef enum EBI_SDCOL_enum ++{ ++ EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ ++ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ ++ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ ++ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ ++} EBI_SDCOL_t; ++ ++/* SDRAM Load Mode to Active delay */ ++typedef enum EBI_MRDLY_enum ++{ ++ EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_MRDLY_t; ++ ++/* SDRAM Row Cycle Delay */ ++typedef enum EBI_ROWCYCDLY_enum ++{ ++ EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycles */ ++ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ROWCYCDLY_t; ++ ++/* SDRAM Row to Precharge Delay */ ++typedef enum EBI_RPDLY_enum ++{ ++ EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycles */ ++ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_RPDLY_t; ++ ++/* SDRAM Write Recovery Delay */ ++typedef enum EBI_WRDLY_enum ++{ ++ EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_WRDLY_t; ++ ++/* SDRAM Exit Self Refresh to Active Delay */ ++typedef enum EBI_ESRDLY_enum ++{ ++ EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycles */ ++ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ESRDLY_t; ++ ++/* SDRAM Row to Column Delay */ ++typedef enum EBI_ROWCOLDLY_enum ++{ ++ EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycles */ ++ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_ROWCOLDLY_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++/* SDA hold time */ ++typedef enum SDA_HOLD_TIME_enum ++{ ++ SDA_HOLD_TIME_OFF_gc = (0x00<<1), /* SDA hold time off */ ++ SDA_HOLD_TIME_50NS_gc = (0x01<<1), /* Typical 50ns hold time */ ++ SDA_HOLD_TIME_300NS_gc = (0x02<<1), /* Typical 300ns hold time */ ++ SDA_HOLD_TIME_400NS_gc = (0x03<<1), /* Typical 400ns hold time */ ++} SDA_HOLD_TIME_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USB - USB ++-------------------------------------------------------------------------- ++*/ ++ ++/* USB Endpoint */ ++typedef struct USB_EP_struct ++{ ++ register8_t STATUS; /* Endpoint Status */ ++ register8_t CTRL; /* Endpoint Control */ ++ _WORDREGISTER(CNT); /* USB Endpoint Counter */ ++ _WORDREGISTER(DATAPTR); /* Data Pointer */ ++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ ++} USB_EP_t; ++ ++ ++/* Universal Serial Bus */ ++typedef struct USB_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t FIFOWP; /* FIFO Write Pointer Register */ ++ register8_t FIFORP; /* FIFO Read Pointer Register */ ++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ ++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ ++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ ++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t reserved_0x20; ++ register8_t reserved_0x21; ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t CAL0; /* Calibration Byte 0 */ ++ register8_t CAL1; /* Calibration Byte 1 */ ++} USB_t; ++ ++ ++/* USB Endpoint Table */ ++typedef struct USB_EP_TABLE_struct ++{ ++ USB_EP_t EP0OUT; /* Endpoint 0 */ ++ USB_EP_t EP0IN; /* Endpoint 0 */ ++ USB_EP_t EP1OUT; /* Endpoint 1 */ ++ USB_EP_t EP1IN; /* Endpoint 1 */ ++ USB_EP_t EP2OUT; /* Endpoint 2 */ ++ USB_EP_t EP2IN; /* Endpoint 2 */ ++ USB_EP_t EP3OUT; /* Endpoint 3 */ ++ USB_EP_t EP3IN; /* Endpoint 3 */ ++ USB_EP_t EP4OUT; /* Endpoint 4 */ ++ USB_EP_t EP4IN; /* Endpoint 4 */ ++ USB_EP_t EP5OUT; /* Endpoint 5 */ ++ USB_EP_t EP5IN; /* Endpoint 5 */ ++ USB_EP_t EP6OUT; /* Endpoint 6 */ ++ USB_EP_t EP6IN; /* Endpoint 6 */ ++ USB_EP_t EP7OUT; /* Endpoint 7 */ ++ USB_EP_t EP7IN; /* Endpoint 7 */ ++ USB_EP_t EP8OUT; /* Endpoint 8 */ ++ USB_EP_t EP8IN; /* Endpoint 8 */ ++ USB_EP_t EP9OUT; /* Endpoint 9 */ ++ USB_EP_t EP9IN; /* Endpoint 9 */ ++ USB_EP_t EP10OUT; /* Endpoint 10 */ ++ USB_EP_t EP10IN; /* Endpoint 10 */ ++ USB_EP_t EP11OUT; /* Endpoint 11 */ ++ USB_EP_t EP11IN; /* Endpoint 11 */ ++ USB_EP_t EP12OUT; /* Endpoint 12 */ ++ USB_EP_t EP12IN; /* Endpoint 12 */ ++ USB_EP_t EP13OUT; /* Endpoint 13 */ ++ USB_EP_t EP13IN; /* Endpoint 13 */ ++ USB_EP_t EP14OUT; /* Endpoint 14 */ ++ USB_EP_t EP14IN; /* Endpoint 14 */ ++ USB_EP_t EP15OUT; /* Endpoint 15 */ ++ USB_EP_t EP15IN; /* Endpoint 15 */ ++ register8_t reserved_0x100; ++ register8_t reserved_0x101; ++ register8_t reserved_0x102; ++ register8_t reserved_0x103; ++ register8_t reserved_0x104; ++ register8_t reserved_0x105; ++ register8_t reserved_0x106; ++ register8_t reserved_0x107; ++ register8_t reserved_0x108; ++ register8_t reserved_0x109; ++ register8_t reserved_0x10A; ++ register8_t reserved_0x10B; ++ register8_t reserved_0x10C; ++ register8_t reserved_0x10D; ++ register8_t reserved_0x10E; ++ register8_t reserved_0x10F; ++ register8_t FRAMENUML; /* Frame Number Low Byte */ ++ register8_t FRAMENUMH; /* Frame Number High Byte */ ++} USB_EP_TABLE_t; ++ ++/* Interrupt level */ ++typedef enum USB_INTLVL_enum ++{ ++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} USB_INTLVL_t; ++ ++/* USB Endpoint Type */ ++typedef enum USB_EP_TYPE_enum ++{ ++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ ++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ ++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ ++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ ++} USB_EP_TYPE_t; ++ ++/* USB Endpoint Buffersize */ ++typedef enum USB_EP_BUFSIZE_enum ++{ ++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ ++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ ++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ ++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ ++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ ++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ ++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ ++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ ++} USB_EP_BUFSIZE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - I/O Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* I/O Port Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Byte Mode */ ++typedef enum TC_BYTEM_enum ++{ ++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ ++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ ++} TC_BYTEM_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC2 - 16-bit Timer/Counter type 2 ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter type 2 */ ++typedef struct TC2_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t reserved_0x03; ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t reserved_0x08; ++ register8_t CTRLF; /* Control Register F */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t LCNT; /* Low Byte Count */ ++ register8_t HCNT; /* High Byte Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t LPER; /* Low Byte Period */ ++ register8_t HPER; /* High Byte Period */ ++ register8_t LCMPA; /* Low Byte Compare A */ ++ register8_t HCMPA; /* High Byte Compare A */ ++ register8_t LCMPB; /* Low Byte Compare B */ ++ register8_t HCMPB; /* High Byte Compare B */ ++ register8_t LCMPC; /* Low Byte Compare C */ ++ register8_t HCMPC; /* High Byte Compare C */ ++ register8_t LCMPD; /* Low Byte Compare D */ ++ register8_t HCMPD; /* High Byte Compare D */ ++} TC2_t; ++ ++/* Clock Selection */ ++typedef enum TC2_CLKSEL_enum ++{ ++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC2_CLKSEL_t; ++ ++/* Byte Mode */ ++typedef enum TC2_BYTEM_enum ++{ ++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ ++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ ++} TC2_BYTEM_t; ++ ++/* High Byte Underflow Interrupt Level */ ++typedef enum TC2_HUNFINTLVL_enum ++{ ++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_HUNFINTLVL_t; ++ ++/* Low Byte Underflow Interrupt Level */ ++typedef enum TC2_LUNFINTLVL_enum ++{ ++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LUNFINTLVL_t; ++ ++/* Low Byte Compare D Interrupt Level */ ++typedef enum TC2_LCMPDINTLVL_enum ++{ ++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC2_LCMPDINTLVL_t; ++ ++/* Low Byte Compare C Interrupt Level */ ++typedef enum TC2_LCMPCINTLVL_enum ++{ ++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC2_LCMPCINTLVL_t; ++ ++/* Low Byte Compare B Interrupt Level */ ++typedef enum TC2_LCMPBINTLVL_enum ++{ ++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_LCMPBINTLVL_t; ++ ++/* Low Byte Compare A Interrupt Level */ ++typedef enum TC2_LCMPAINTLVL_enum ++{ ++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LCMPAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMD_enum ++{ ++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC2_CMD_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMDEN_enum ++{ ++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ ++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ ++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ ++} TC2_CMDEN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AWEX - Timer/Counter Advanced Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - Timer/Counter High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t FUSEBYTE0; /* JTAG User ID */ ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* Timer Oscillator pin location */ ++typedef enum TOSCSEL_enum ++{ ++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ ++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ ++} TOSCSEL_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* BOD operation */ ++typedef enum BODACT_enum ++{ ++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BODACT_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WDP_enum ++{ ++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ ++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ ++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ ++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ ++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ ++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ ++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ ++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ ++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ ++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ ++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ ++} WDP_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LOCKBIT - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ ++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t USBCAL0; /* USB Calibration Byte 0 */ ++ register8_t USBCAL1; /* USB Calibration Byte 1 */ ++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ ++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ ++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ ++ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ ++ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ ++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ ++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ ++ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ ++ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++ register8_t reserved_0x40; ++ register8_t reserved_0x41; ++ register8_t reserved_0x42; ++ register8_t reserved_0x43; ++ register8_t reserved_0x44; ++ register8_t reserved_0x45; ++ register8_t reserved_0x46; ++ register8_t reserved_0x47; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define AES (*(AES_t *) 0x00C0) /* AES Module */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ ++#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ ++#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ ++#define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface */ ++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ ++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ ++#define PORTH (*(PORT_t *) 0x06E0) /* I/O Ports */ ++#define PORTJ (*(PORT_t *) 0x0700) /* I/O Ports */ ++#define PORTK (*(PORT_t *) 0x0720) /* I/O Ports */ ++#define PORTQ (*(PORT_t *) 0x07C0) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ ++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ ++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ ++#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ ++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ ++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ ++#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ ++#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ ++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ ++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ ++#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ ++#define TCF1 (*(TC1_t *) 0x0B40) /* 16-bit Timer/Counter 1 */ ++#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ ++#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++#define GPIO_GPIOR4 _SFR_MEM8(0x0004) ++#define GPIO_GPIOR5 _SFR_MEM8(0x0005) ++#define GPIO_GPIOR6 _SFR_MEM8(0x0006) ++#define GPIO_GPIOR7 _SFR_MEM8(0x0007) ++#define GPIO_GPIOR8 _SFR_MEM8(0x0008) ++#define GPIO_GPIOR9 _SFR_MEM8(0x0009) ++#define GPIO_GPIORA _SFR_MEM8(0x000A) ++#define GPIO_GPIORB _SFR_MEM8(0x000B) ++#define GPIO_GPIORC _SFR_MEM8(0x000C) ++#define GPIO_GPIORD _SFR_MEM8(0x000D) ++#define GPIO_GPIORE _SFR_MEM8(0x000E) ++#define GPIO_GPIORF _SFR_MEM8(0x000F) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++#define GPIO_GPIO4 _SFR_MEM8(0x0004) ++#define GPIO_GPIO5 _SFR_MEM8(0x0005) ++#define GPIO_GPIO6 _SFR_MEM8(0x0006) ++#define GPIO_GPIO7 _SFR_MEM8(0x0007) ++#define GPIO_GPIO8 _SFR_MEM8(0x0008) ++#define GPIO_GPIO9 _SFR_MEM8(0x0009) ++#define GPIO_GPIOA _SFR_MEM8(0x000A) ++#define GPIO_GPIOB _SFR_MEM8(0x000B) ++#define GPIO_GPIOC _SFR_MEM8(0x000C) ++#define GPIO_GPIOD _SFR_MEM8(0x000D) ++#define GPIO_GPIOE _SFR_MEM8(0x000E) ++#define GPIO_GPIOF _SFR_MEM8(0x000F) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) ++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) ++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) ++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) ++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) ++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) ++#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) ++#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) ++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) ++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) ++#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) ++#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++#define CLK_USBCTRL _SFR_MEM8(0x0044) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLL - DFLL */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPB _SFR_MEM8(0x0072) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) ++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) ++ ++/* AES - AES Module */ ++#define AES_CTRL _SFR_MEM8(0x00C0) ++#define AES_STATUS _SFR_MEM8(0x00C1) ++#define AES_STATE _SFR_MEM8(0x00C2) ++#define AES_KEY _SFR_MEM8(0x00C3) ++#define AES_INTCTRL _SFR_MEM8(0x00C4) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* DMA - DMA Controller */ ++#define DMA_CTRL _SFR_MEM8(0x0100) ++#define DMA_INTFLAGS _SFR_MEM8(0x0103) ++#define DMA_STATUS _SFR_MEM8(0x0104) ++#define DMA_TEMP _SFR_MEM16(0x0106) ++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) ++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) ++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) ++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) ++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) ++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) ++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) ++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) ++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) ++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) ++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) ++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) ++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) ++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) ++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) ++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) ++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) ++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) ++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) ++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) ++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) ++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) ++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) ++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) ++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) ++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) ++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) ++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) ++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) ++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) ++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) ++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) ++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) ++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) ++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) ++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) ++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) ++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) ++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) ++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) ++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) ++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH4MUX _SFR_MEM8(0x0184) ++#define EVSYS_CH5MUX _SFR_MEM8(0x0185) ++#define EVSYS_CH6MUX _SFR_MEM8(0x0186) ++#define EVSYS_CH7MUX _SFR_MEM8(0x0187) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) ++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) ++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) ++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CH1RES _SFR_MEM16(0x0212) ++#define ADCA_CH2RES _SFR_MEM16(0x0214) ++#define ADCA_CH3RES _SFR_MEM16(0x0216) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) ++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) ++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) ++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) ++#define ADCA_CH1_RES _SFR_MEM16(0x022C) ++#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) ++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) ++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) ++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) ++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) ++#define ADCA_CH2_RES _SFR_MEM16(0x0234) ++#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) ++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) ++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) ++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) ++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) ++#define ADCA_CH3_RES _SFR_MEM16(0x023C) ++#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCB_CTRLA _SFR_MEM8(0x0240) ++#define ADCB_CTRLB _SFR_MEM8(0x0241) ++#define ADCB_REFCTRL _SFR_MEM8(0x0242) ++#define ADCB_EVCTRL _SFR_MEM8(0x0243) ++#define ADCB_PRESCALER _SFR_MEM8(0x0244) ++#define ADCB_INTFLAGS _SFR_MEM8(0x0246) ++#define ADCB_TEMP _SFR_MEM8(0x0247) ++#define ADCB_CAL _SFR_MEM16(0x024C) ++#define ADCB_CH0RES _SFR_MEM16(0x0250) ++#define ADCB_CH1RES _SFR_MEM16(0x0252) ++#define ADCB_CH2RES _SFR_MEM16(0x0254) ++#define ADCB_CH3RES _SFR_MEM16(0x0256) ++#define ADCB_CMP _SFR_MEM16(0x0258) ++#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) ++#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) ++#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) ++#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) ++#define ADCB_CH0_RES _SFR_MEM16(0x0264) ++#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) ++#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) ++#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) ++#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) ++#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) ++#define ADCB_CH1_RES _SFR_MEM16(0x026C) ++#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) ++#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) ++#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) ++#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) ++#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) ++#define ADCB_CH2_RES _SFR_MEM16(0x0274) ++#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) ++#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) ++#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) ++#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) ++#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) ++#define ADCB_CH3_RES _SFR_MEM16(0x027C) ++#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) ++ ++/* DAC - Digital-to-Analog Converter */ ++#define DACA_CTRLA _SFR_MEM8(0x0300) ++#define DACA_CTRLB _SFR_MEM8(0x0301) ++#define DACA_CTRLC _SFR_MEM8(0x0302) ++#define DACA_EVCTRL _SFR_MEM8(0x0303) ++#define DACA_STATUS _SFR_MEM8(0x0305) ++#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) ++#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) ++#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) ++#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) ++#define DACA_CH0DATA _SFR_MEM16(0x0318) ++#define DACA_CH1DATA _SFR_MEM16(0x031A) ++ ++/* DAC - Digital-to-Analog Converter */ ++#define DACB_CTRLA _SFR_MEM8(0x0320) ++#define DACB_CTRLB _SFR_MEM8(0x0321) ++#define DACB_CTRLC _SFR_MEM8(0x0322) ++#define DACB_EVCTRL _SFR_MEM8(0x0323) ++#define DACB_STATUS _SFR_MEM8(0x0325) ++#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) ++#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) ++#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) ++#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) ++#define DACB_CH0DATA _SFR_MEM16(0x0338) ++#define DACB_CH1DATA _SFR_MEM16(0x033A) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* AC - Analog Comparator */ ++#define ACB_AC0CTRL _SFR_MEM8(0x0390) ++#define ACB_AC1CTRL _SFR_MEM8(0x0391) ++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) ++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) ++#define ACB_CTRLA _SFR_MEM8(0x0394) ++#define ACB_CTRLB _SFR_MEM8(0x0395) ++#define ACB_WINCTRL _SFR_MEM8(0x0396) ++#define ACB_STATUS _SFR_MEM8(0x0397) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* EBI - External Bus Interface */ ++#define EBI_CTRL _SFR_MEM8(0x0440) ++#define EBI_SDRAMCTRLA _SFR_MEM8(0x0441) ++#define EBI_REFRESH _SFR_MEM16(0x0444) ++#define EBI_INITDLY _SFR_MEM16(0x0446) ++#define EBI_SDRAMCTRLB _SFR_MEM8(0x0448) ++#define EBI_SDRAMCTRLC _SFR_MEM8(0x0449) ++#define EBI_CS0_CTRLA _SFR_MEM8(0x0450) ++#define EBI_CS0_CTRLB _SFR_MEM8(0x0451) ++#define EBI_CS0_BASEADDR _SFR_MEM16(0x0452) ++#define EBI_CS1_CTRLA _SFR_MEM8(0x0454) ++#define EBI_CS1_CTRLB _SFR_MEM8(0x0455) ++#define EBI_CS1_BASEADDR _SFR_MEM16(0x0456) ++#define EBI_CS2_CTRLA _SFR_MEM8(0x0458) ++#define EBI_CS2_CTRLB _SFR_MEM8(0x0459) ++#define EBI_CS2_BASEADDR _SFR_MEM16(0x045A) ++#define EBI_CS3_CTRLA _SFR_MEM8(0x045C) ++#define EBI_CS3_CTRLB _SFR_MEM8(0x045D) ++#define EBI_CS3_BASEADDR _SFR_MEM16(0x045E) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWI - Two-Wire Interface */ ++#define TWID_CTRL _SFR_MEM8(0x0490) ++#define TWID_MASTER_CTRLA _SFR_MEM8(0x0491) ++#define TWID_MASTER_CTRLB _SFR_MEM8(0x0492) ++#define TWID_MASTER_CTRLC _SFR_MEM8(0x0493) ++#define TWID_MASTER_STATUS _SFR_MEM8(0x0494) ++#define TWID_MASTER_BAUD _SFR_MEM8(0x0495) ++#define TWID_MASTER_ADDR _SFR_MEM8(0x0496) ++#define TWID_MASTER_DATA _SFR_MEM8(0x0497) ++#define TWID_SLAVE_CTRLA _SFR_MEM8(0x0498) ++#define TWID_SLAVE_CTRLB _SFR_MEM8(0x0499) ++#define TWID_SLAVE_STATUS _SFR_MEM8(0x049A) ++#define TWID_SLAVE_ADDR _SFR_MEM8(0x049B) ++#define TWID_SLAVE_DATA _SFR_MEM8(0x049C) ++#define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIF_CTRL _SFR_MEM8(0x04B0) ++#define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1) ++#define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2) ++#define TWIF_MASTER_CTRLC _SFR_MEM8(0x04B3) ++#define TWIF_MASTER_STATUS _SFR_MEM8(0x04B4) ++#define TWIF_MASTER_BAUD _SFR_MEM8(0x04B5) ++#define TWIF_MASTER_ADDR _SFR_MEM8(0x04B6) ++#define TWIF_MASTER_DATA _SFR_MEM8(0x04B7) ++#define TWIF_SLAVE_CTRLA _SFR_MEM8(0x04B8) ++#define TWIF_SLAVE_CTRLB _SFR_MEM8(0x04B9) ++#define TWIF_SLAVE_STATUS _SFR_MEM8(0x04BA) ++#define TWIF_SLAVE_ADDR _SFR_MEM8(0x04BB) ++#define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC) ++#define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD) ++ ++/* USB - Universal Serial Bus */ ++#define USB_CTRLA _SFR_MEM8(0x04C0) ++#define USB_CTRLB _SFR_MEM8(0x04C1) ++#define USB_STATUS _SFR_MEM8(0x04C2) ++#define USB_ADDR _SFR_MEM8(0x04C3) ++#define USB_FIFOWP _SFR_MEM8(0x04C4) ++#define USB_FIFORP _SFR_MEM8(0x04C5) ++#define USB_EPPTR _SFR_MEM16(0x04C6) ++#define USB_INTCTRLA _SFR_MEM8(0x04C8) ++#define USB_INTCTRLB _SFR_MEM8(0x04C9) ++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) ++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) ++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) ++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) ++#define USB_CAL0 _SFR_MEM8(0x04FA) ++#define USB_CAL1 _SFR_MEM8(0x04FB) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_REMAP _SFR_MEM8(0x060E) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_REMAP _SFR_MEM8(0x062E) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_REMAP _SFR_MEM8(0x068E) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORT - I/O Ports */ ++#define PORTF_DIR _SFR_MEM8(0x06A0) ++#define PORTF_DIRSET _SFR_MEM8(0x06A1) ++#define PORTF_DIRCLR _SFR_MEM8(0x06A2) ++#define PORTF_DIRTGL _SFR_MEM8(0x06A3) ++#define PORTF_OUT _SFR_MEM8(0x06A4) ++#define PORTF_OUTSET _SFR_MEM8(0x06A5) ++#define PORTF_OUTCLR _SFR_MEM8(0x06A6) ++#define PORTF_OUTTGL _SFR_MEM8(0x06A7) ++#define PORTF_IN _SFR_MEM8(0x06A8) ++#define PORTF_INTCTRL _SFR_MEM8(0x06A9) ++#define PORTF_INT0MASK _SFR_MEM8(0x06AA) ++#define PORTF_INT1MASK _SFR_MEM8(0x06AB) ++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) ++#define PORTF_REMAP _SFR_MEM8(0x06AE) ++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) ++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) ++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) ++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) ++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) ++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) ++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) ++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) ++ ++/* PORT - I/O Ports */ ++#define PORTH_DIR _SFR_MEM8(0x06E0) ++#define PORTH_DIRSET _SFR_MEM8(0x06E1) ++#define PORTH_DIRCLR _SFR_MEM8(0x06E2) ++#define PORTH_DIRTGL _SFR_MEM8(0x06E3) ++#define PORTH_OUT _SFR_MEM8(0x06E4) ++#define PORTH_OUTSET _SFR_MEM8(0x06E5) ++#define PORTH_OUTCLR _SFR_MEM8(0x06E6) ++#define PORTH_OUTTGL _SFR_MEM8(0x06E7) ++#define PORTH_IN _SFR_MEM8(0x06E8) ++#define PORTH_INTCTRL _SFR_MEM8(0x06E9) ++#define PORTH_INT0MASK _SFR_MEM8(0x06EA) ++#define PORTH_INT1MASK _SFR_MEM8(0x06EB) ++#define PORTH_INTFLAGS _SFR_MEM8(0x06EC) ++#define PORTH_REMAP _SFR_MEM8(0x06EE) ++#define PORTH_PIN0CTRL _SFR_MEM8(0x06F0) ++#define PORTH_PIN1CTRL _SFR_MEM8(0x06F1) ++#define PORTH_PIN2CTRL _SFR_MEM8(0x06F2) ++#define PORTH_PIN3CTRL _SFR_MEM8(0x06F3) ++#define PORTH_PIN4CTRL _SFR_MEM8(0x06F4) ++#define PORTH_PIN5CTRL _SFR_MEM8(0x06F5) ++#define PORTH_PIN6CTRL _SFR_MEM8(0x06F6) ++#define PORTH_PIN7CTRL _SFR_MEM8(0x06F7) ++ ++/* PORT - I/O Ports */ ++#define PORTJ_DIR _SFR_MEM8(0x0700) ++#define PORTJ_DIRSET _SFR_MEM8(0x0701) ++#define PORTJ_DIRCLR _SFR_MEM8(0x0702) ++#define PORTJ_DIRTGL _SFR_MEM8(0x0703) ++#define PORTJ_OUT _SFR_MEM8(0x0704) ++#define PORTJ_OUTSET _SFR_MEM8(0x0705) ++#define PORTJ_OUTCLR _SFR_MEM8(0x0706) ++#define PORTJ_OUTTGL _SFR_MEM8(0x0707) ++#define PORTJ_IN _SFR_MEM8(0x0708) ++#define PORTJ_INTCTRL _SFR_MEM8(0x0709) ++#define PORTJ_INT0MASK _SFR_MEM8(0x070A) ++#define PORTJ_INT1MASK _SFR_MEM8(0x070B) ++#define PORTJ_INTFLAGS _SFR_MEM8(0x070C) ++#define PORTJ_REMAP _SFR_MEM8(0x070E) ++#define PORTJ_PIN0CTRL _SFR_MEM8(0x0710) ++#define PORTJ_PIN1CTRL _SFR_MEM8(0x0711) ++#define PORTJ_PIN2CTRL _SFR_MEM8(0x0712) ++#define PORTJ_PIN3CTRL _SFR_MEM8(0x0713) ++#define PORTJ_PIN4CTRL _SFR_MEM8(0x0714) ++#define PORTJ_PIN5CTRL _SFR_MEM8(0x0715) ++#define PORTJ_PIN6CTRL _SFR_MEM8(0x0716) ++#define PORTJ_PIN7CTRL _SFR_MEM8(0x0717) ++ ++/* PORT - I/O Ports */ ++#define PORTK_DIR _SFR_MEM8(0x0720) ++#define PORTK_DIRSET _SFR_MEM8(0x0721) ++#define PORTK_DIRCLR _SFR_MEM8(0x0722) ++#define PORTK_DIRTGL _SFR_MEM8(0x0723) ++#define PORTK_OUT _SFR_MEM8(0x0724) ++#define PORTK_OUTSET _SFR_MEM8(0x0725) ++#define PORTK_OUTCLR _SFR_MEM8(0x0726) ++#define PORTK_OUTTGL _SFR_MEM8(0x0727) ++#define PORTK_IN _SFR_MEM8(0x0728) ++#define PORTK_INTCTRL _SFR_MEM8(0x0729) ++#define PORTK_INT0MASK _SFR_MEM8(0x072A) ++#define PORTK_INT1MASK _SFR_MEM8(0x072B) ++#define PORTK_INTFLAGS _SFR_MEM8(0x072C) ++#define PORTK_REMAP _SFR_MEM8(0x072E) ++#define PORTK_PIN0CTRL _SFR_MEM8(0x0730) ++#define PORTK_PIN1CTRL _SFR_MEM8(0x0731) ++#define PORTK_PIN2CTRL _SFR_MEM8(0x0732) ++#define PORTK_PIN3CTRL _SFR_MEM8(0x0733) ++#define PORTK_PIN4CTRL _SFR_MEM8(0x0734) ++#define PORTK_PIN5CTRL _SFR_MEM8(0x0735) ++#define PORTK_PIN6CTRL _SFR_MEM8(0x0736) ++#define PORTK_PIN7CTRL _SFR_MEM8(0x0737) ++ ++/* PORT - I/O Ports */ ++#define PORTQ_DIR _SFR_MEM8(0x07C0) ++#define PORTQ_DIRSET _SFR_MEM8(0x07C1) ++#define PORTQ_DIRCLR _SFR_MEM8(0x07C2) ++#define PORTQ_DIRTGL _SFR_MEM8(0x07C3) ++#define PORTQ_OUT _SFR_MEM8(0x07C4) ++#define PORTQ_OUTSET _SFR_MEM8(0x07C5) ++#define PORTQ_OUTCLR _SFR_MEM8(0x07C6) ++#define PORTQ_OUTTGL _SFR_MEM8(0x07C7) ++#define PORTQ_IN _SFR_MEM8(0x07C8) ++#define PORTQ_INTCTRL _SFR_MEM8(0x07C9) ++#define PORTQ_INT0MASK _SFR_MEM8(0x07CA) ++#define PORTQ_INT1MASK _SFR_MEM8(0x07CB) ++#define PORTQ_INTFLAGS _SFR_MEM8(0x07CC) ++#define PORTQ_REMAP _SFR_MEM8(0x07CE) ++#define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0) ++#define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1) ++#define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2) ++#define PORTQ_PIN3CTRL _SFR_MEM8(0x07D3) ++#define PORTQ_PIN4CTRL _SFR_MEM8(0x07D4) ++#define PORTQ_PIN5CTRL _SFR_MEM8(0x07D5) ++#define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6) ++#define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCC2_CTRLA _SFR_MEM8(0x0800) ++#define TCC2_CTRLB _SFR_MEM8(0x0801) ++#define TCC2_CTRLC _SFR_MEM8(0x0802) ++#define TCC2_CTRLE _SFR_MEM8(0x0804) ++#define TCC2_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC2_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC2_CTRLF _SFR_MEM8(0x0809) ++#define TCC2_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC2_LCNT _SFR_MEM8(0x0820) ++#define TCC2_HCNT _SFR_MEM8(0x0821) ++#define TCC2_LPER _SFR_MEM8(0x0826) ++#define TCC2_HPER _SFR_MEM8(0x0827) ++#define TCC2_LCMPA _SFR_MEM8(0x0828) ++#define TCC2_HCMPA _SFR_MEM8(0x0829) ++#define TCC2_LCMPB _SFR_MEM8(0x082A) ++#define TCC2_HCMPB _SFR_MEM8(0x082B) ++#define TCC2_LCMPC _SFR_MEM8(0x082C) ++#define TCC2_HCMPC _SFR_MEM8(0x082D) ++#define TCC2_LCMPD _SFR_MEM8(0x082E) ++#define TCC2_HCMPD _SFR_MEM8(0x082F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_STATUSSET _SFR_MEM8(0x0885) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1_DATA _SFR_MEM8(0x08B0) ++#define USARTC1_STATUS _SFR_MEM8(0x08B1) ++#define USARTC1_CTRLA _SFR_MEM8(0x08B3) ++#define USARTC1_CTRLB _SFR_MEM8(0x08B4) ++#define USARTC1_CTRLC _SFR_MEM8(0x08B5) ++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) ++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCD2_CTRLA _SFR_MEM8(0x0900) ++#define TCD2_CTRLB _SFR_MEM8(0x0901) ++#define TCD2_CTRLC _SFR_MEM8(0x0902) ++#define TCD2_CTRLE _SFR_MEM8(0x0904) ++#define TCD2_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD2_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD2_CTRLF _SFR_MEM8(0x0909) ++#define TCD2_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD2_LCNT _SFR_MEM8(0x0920) ++#define TCD2_HCNT _SFR_MEM8(0x0921) ++#define TCD2_LPER _SFR_MEM8(0x0926) ++#define TCD2_HPER _SFR_MEM8(0x0927) ++#define TCD2_LCMPA _SFR_MEM8(0x0928) ++#define TCD2_HCMPA _SFR_MEM8(0x0929) ++#define TCD2_LCMPB _SFR_MEM8(0x092A) ++#define TCD2_HCMPB _SFR_MEM8(0x092B) ++#define TCD2_LCMPC _SFR_MEM8(0x092C) ++#define TCD2_HCMPC _SFR_MEM8(0x092D) ++#define TCD2_LCMPD _SFR_MEM8(0x092E) ++#define TCD2_HCMPD _SFR_MEM8(0x092F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCD1_CTRLA _SFR_MEM8(0x0940) ++#define TCD1_CTRLB _SFR_MEM8(0x0941) ++#define TCD1_CTRLC _SFR_MEM8(0x0942) ++#define TCD1_CTRLD _SFR_MEM8(0x0943) ++#define TCD1_CTRLE _SFR_MEM8(0x0944) ++#define TCD1_INTCTRLA _SFR_MEM8(0x0946) ++#define TCD1_INTCTRLB _SFR_MEM8(0x0947) ++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) ++#define TCD1_CTRLFSET _SFR_MEM8(0x0949) ++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) ++#define TCD1_CTRLGSET _SFR_MEM8(0x094B) ++#define TCD1_INTFLAGS _SFR_MEM8(0x094C) ++#define TCD1_TEMP _SFR_MEM8(0x094F) ++#define TCD1_CNT _SFR_MEM16(0x0960) ++#define TCD1_PER _SFR_MEM16(0x0966) ++#define TCD1_CCA _SFR_MEM16(0x0968) ++#define TCD1_CCB _SFR_MEM16(0x096A) ++#define TCD1_PERBUF _SFR_MEM16(0x0976) ++#define TCD1_CCABUF _SFR_MEM16(0x0978) ++#define TCD1_CCBBUF _SFR_MEM16(0x097A) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESD_CTRLA _SFR_MEM8(0x0990) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD1_DATA _SFR_MEM8(0x09B0) ++#define USARTD1_STATUS _SFR_MEM8(0x09B1) ++#define USARTD1_CTRLA _SFR_MEM8(0x09B3) ++#define USARTD1_CTRLB _SFR_MEM8(0x09B4) ++#define USARTD1_CTRLC _SFR_MEM8(0x09B5) ++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) ++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCE2_CTRLA _SFR_MEM8(0x0A00) ++#define TCE2_CTRLB _SFR_MEM8(0x0A01) ++#define TCE2_CTRLC _SFR_MEM8(0x0A02) ++#define TCE2_CTRLE _SFR_MEM8(0x0A04) ++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE2_CTRLF _SFR_MEM8(0x0A09) ++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE2_LCNT _SFR_MEM8(0x0A20) ++#define TCE2_HCNT _SFR_MEM8(0x0A21) ++#define TCE2_LPER _SFR_MEM8(0x0A26) ++#define TCE2_HPER _SFR_MEM8(0x0A27) ++#define TCE2_LCMPA _SFR_MEM8(0x0A28) ++#define TCE2_HCMPA _SFR_MEM8(0x0A29) ++#define TCE2_LCMPB _SFR_MEM8(0x0A2A) ++#define TCE2_HCMPB _SFR_MEM8(0x0A2B) ++#define TCE2_LCMPC _SFR_MEM8(0x0A2C) ++#define TCE2_HCMPC _SFR_MEM8(0x0A2D) ++#define TCE2_LCMPD _SFR_MEM8(0x0A2E) ++#define TCE2_HCMPD _SFR_MEM8(0x0A2F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCE1_CTRLA _SFR_MEM8(0x0A40) ++#define TCE1_CTRLB _SFR_MEM8(0x0A41) ++#define TCE1_CTRLC _SFR_MEM8(0x0A42) ++#define TCE1_CTRLD _SFR_MEM8(0x0A43) ++#define TCE1_CTRLE _SFR_MEM8(0x0A44) ++#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) ++#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) ++#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) ++#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) ++#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) ++#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) ++#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) ++#define TCE1_TEMP _SFR_MEM8(0x0A4F) ++#define TCE1_CNT _SFR_MEM16(0x0A60) ++#define TCE1_PER _SFR_MEM16(0x0A66) ++#define TCE1_CCA _SFR_MEM16(0x0A68) ++#define TCE1_CCB _SFR_MEM16(0x0A6A) ++#define TCE1_PERBUF _SFR_MEM16(0x0A76) ++#define TCE1_CCABUF _SFR_MEM16(0x0A78) ++#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXE_CTRL _SFR_MEM8(0x0A80) ++#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) ++#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) ++#define AWEXE_STATUS _SFR_MEM8(0x0A84) ++#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) ++#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) ++#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) ++#define AWEXE_DTLS _SFR_MEM8(0x0A88) ++#define AWEXE_DTHS _SFR_MEM8(0x0A89) ++#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) ++#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) ++#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESE_CTRLA _SFR_MEM8(0x0A90) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE1_DATA _SFR_MEM8(0x0AB0) ++#define USARTE1_STATUS _SFR_MEM8(0x0AB1) ++#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) ++#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) ++#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) ++#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) ++#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIE_CTRL _SFR_MEM8(0x0AC0) ++#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) ++#define SPIE_STATUS _SFR_MEM8(0x0AC2) ++#define SPIE_DATA _SFR_MEM8(0x0AC3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCF0_CTRLA _SFR_MEM8(0x0B00) ++#define TCF0_CTRLB _SFR_MEM8(0x0B01) ++#define TCF0_CTRLC _SFR_MEM8(0x0B02) ++#define TCF0_CTRLD _SFR_MEM8(0x0B03) ++#define TCF0_CTRLE _SFR_MEM8(0x0B04) ++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) ++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) ++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) ++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) ++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF0_TEMP _SFR_MEM8(0x0B0F) ++#define TCF0_CNT _SFR_MEM16(0x0B20) ++#define TCF0_PER _SFR_MEM16(0x0B26) ++#define TCF0_CCA _SFR_MEM16(0x0B28) ++#define TCF0_CCB _SFR_MEM16(0x0B2A) ++#define TCF0_CCC _SFR_MEM16(0x0B2C) ++#define TCF0_CCD _SFR_MEM16(0x0B2E) ++#define TCF0_PERBUF _SFR_MEM16(0x0B36) ++#define TCF0_CCABUF _SFR_MEM16(0x0B38) ++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) ++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) ++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCF2_CTRLA _SFR_MEM8(0x0B00) ++#define TCF2_CTRLB _SFR_MEM8(0x0B01) ++#define TCF2_CTRLC _SFR_MEM8(0x0B02) ++#define TCF2_CTRLE _SFR_MEM8(0x0B04) ++#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF2_CTRLF _SFR_MEM8(0x0B09) ++#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF2_LCNT _SFR_MEM8(0x0B20) ++#define TCF2_HCNT _SFR_MEM8(0x0B21) ++#define TCF2_LPER _SFR_MEM8(0x0B26) ++#define TCF2_HPER _SFR_MEM8(0x0B27) ++#define TCF2_LCMPA _SFR_MEM8(0x0B28) ++#define TCF2_HCMPA _SFR_MEM8(0x0B29) ++#define TCF2_LCMPB _SFR_MEM8(0x0B2A) ++#define TCF2_HCMPB _SFR_MEM8(0x0B2B) ++#define TCF2_LCMPC _SFR_MEM8(0x0B2C) ++#define TCF2_HCMPC _SFR_MEM8(0x0B2D) ++#define TCF2_LCMPD _SFR_MEM8(0x0B2E) ++#define TCF2_HCMPD _SFR_MEM8(0x0B2F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCF1_CTRLA _SFR_MEM8(0x0B40) ++#define TCF1_CTRLB _SFR_MEM8(0x0B41) ++#define TCF1_CTRLC _SFR_MEM8(0x0B42) ++#define TCF1_CTRLD _SFR_MEM8(0x0B43) ++#define TCF1_CTRLE _SFR_MEM8(0x0B44) ++#define TCF1_INTCTRLA _SFR_MEM8(0x0B46) ++#define TCF1_INTCTRLB _SFR_MEM8(0x0B47) ++#define TCF1_CTRLFCLR _SFR_MEM8(0x0B48) ++#define TCF1_CTRLFSET _SFR_MEM8(0x0B49) ++#define TCF1_CTRLGCLR _SFR_MEM8(0x0B4A) ++#define TCF1_CTRLGSET _SFR_MEM8(0x0B4B) ++#define TCF1_INTFLAGS _SFR_MEM8(0x0B4C) ++#define TCF1_TEMP _SFR_MEM8(0x0B4F) ++#define TCF1_CNT _SFR_MEM16(0x0B60) ++#define TCF1_PER _SFR_MEM16(0x0B66) ++#define TCF1_CCA _SFR_MEM16(0x0B68) ++#define TCF1_CCB _SFR_MEM16(0x0B6A) ++#define TCF1_PERBUF _SFR_MEM16(0x0B76) ++#define TCF1_CCABUF _SFR_MEM16(0x0B78) ++#define TCF1_CCBBUF _SFR_MEM16(0x0B7A) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESF_CTRLA _SFR_MEM8(0x0B90) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTF0_DATA _SFR_MEM8(0x0BA0) ++#define USARTF0_STATUS _SFR_MEM8(0x0BA1) ++#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) ++#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) ++#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) ++#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) ++#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTF1_DATA _SFR_MEM8(0x0BB0) ++#define USARTF1_STATUS _SFR_MEM8(0x0BB1) ++#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) ++#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) ++#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) ++#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) ++#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIF_CTRL _SFR_MEM8(0x0BC0) ++#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) ++#define SPIF_STATUS _SFR_MEM8(0x0BC2) ++#define SPIF_DATA _SFR_MEM8(0x0BC3) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* CLK.USBCTRL bit masks and bit positions */ ++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ ++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ ++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ ++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ ++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ ++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ ++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ ++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ ++ ++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ ++#define CLK_USBSRC_gp 1 /* Clock Source group position. */ ++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ ++ ++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_USB_bm 0x40 /* USB bit mask. */ ++#define PR_USB_bp 6 /* USB bit position. */ ++ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ ++#define PR_EBI_bp 3 /* External Bus Interface bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ ++#define PR_DAC_bp 2 /* Port A DAC bit position. */ ++ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPB bit masks and bit positions */ ++/* PR_DAC Predefined. */ ++/* PR_DAC Predefined. */ ++ ++/* PR_ADC Predefined. */ ++/* PR_ADC Predefined. */ ++ ++/* PR_AC Predefined. */ ++/* PR_AC Predefined. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ ++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ ++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ ++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ ++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ ++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ ++ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ ++#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ ++ ++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ ++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ ++ ++#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ ++#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ ++ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ ++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ ++ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ ++ ++/* PORTCFG.EBIOUT bit masks and bit positions */ ++#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ ++#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ ++#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ ++#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ ++#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ ++#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ ++ ++#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ ++#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ ++#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ ++#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ ++#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ ++#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ ++ ++/* PORTCFG.EVOUTSEL bit masks and bit positions */ ++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ ++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ ++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ ++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ ++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ ++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ ++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ ++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ ++ ++/* AES - AES Module */ ++/* AES.CTRL bit masks and bit positions */ ++#define AES_START_bm 0x80 /* Start/Run bit mask. */ ++#define AES_START_bp 7 /* Start/Run bit position. */ ++ ++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ ++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ ++ ++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ ++#define AES_RESET_bp 5 /* AES Software Reset bit position. */ ++ ++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ ++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ ++ ++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ ++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ ++ ++/* AES.STATUS bit masks and bit positions */ ++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ ++#define AES_ERROR_bp 7 /* AES Error bit position. */ ++ ++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ ++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ ++ ++/* AES.INTCTRL bit masks and bit positions */ ++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define AES_INTLVL_gp 0 /* Interrupt level group position. */ ++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* DMA - DMA Controller */ ++/* DMA_CH.CTRLA bit masks and bit positions */ ++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ ++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ ++ ++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ ++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ ++ ++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ ++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ ++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ ++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ ++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ ++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ ++ ++/* DMA_CH.CTRLB bit masks and bit positions */ ++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ ++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ ++ ++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ ++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ ++ ++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ ++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ ++ ++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ ++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ ++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ ++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ ++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ ++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ ++ ++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ ++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ ++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ ++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ ++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ ++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ ++ ++/* DMA_CH.ADDRCTRL bit masks and bit positions */ ++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ ++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ ++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ ++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ ++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ ++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ ++ ++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ ++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ ++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ ++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ ++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ ++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ ++ ++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ ++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ ++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ ++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ ++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ ++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ ++ ++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ ++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ ++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ ++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ ++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ ++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ ++ ++/* DMA_CH.TRIGSRC bit masks and bit positions */ ++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++/* DMA.CTRL bit masks and bit positions */ ++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define DMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define DMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ ++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ ++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ ++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ ++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ ++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ ++ ++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ ++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ ++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ ++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ ++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ ++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ ++ ++/* DMA.INTFLAGS bit masks and bit positions */ ++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++/* DMA.STATUS bit masks and bit positions */ ++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ ++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ ++ ++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ ++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ ++ ++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ ++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ ++ ++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ ++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ ++ ++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ ++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ ++ ++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ ++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ ++ ++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ ++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ ++ ++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ ++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH4MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH5MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH6MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH7MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM Predefined. */ ++/* EVSYS_QDIRM Predefined. */ ++ ++/* EVSYS_QDIEN Predefined. */ ++/* EVSYS_QDIEN Predefined. */ ++ ++/* EVSYS_QDEN Predefined. */ ++/* EVSYS_QDEN Predefined. */ ++ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH4CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM Predefined. */ ++/* EVSYS_QDIRM Predefined. */ ++ ++/* EVSYS_QDIEN Predefined. */ ++/* EVSYS_QDIEN Predefined. */ ++ ++/* EVSYS_QDEN Predefined. */ ++/* EVSYS_QDEN Predefined. */ ++ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH5CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH6CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH7CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ ++#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ ++#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ ++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ ++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ ++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ ++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ ++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ ++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ ++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ ++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ ++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ ++ ++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ ++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ ++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ ++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ ++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ ++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ ++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ ++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ ++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ ++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ ++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ ++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ ++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ ++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ ++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ ++ ++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ ++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ ++ ++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ ++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ ++ ++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ ++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ ++ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ ++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ ++#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ ++ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ ++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ ++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ ++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ ++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ ++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ ++ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ ++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ ++ ++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ ++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ ++ ++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ ++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ ++ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* DAC - Digital/Analog Converter */ ++/* DAC.CTRLA bit masks and bit positions */ ++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ ++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ ++ ++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ ++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ ++ ++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ ++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ ++ ++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ ++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ ++ ++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define DAC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* DAC.CTRLB bit masks and bit positions */ ++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ ++#define DAC_CHSEL_gp 5 /* Channel Select group position. */ ++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ ++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ ++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ ++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ ++ ++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ ++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ ++ ++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ ++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ ++ ++/* DAC.CTRLC bit masks and bit positions */ ++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ ++#define DAC_REFSEL_gp 3 /* Reference Select group position. */ ++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ ++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ ++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ ++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ ++ ++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ ++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ ++ ++/* DAC.EVCTRL bit masks and bit positions */ ++#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ ++#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ ++ ++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ ++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ ++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ ++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ ++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ ++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ ++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ ++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ ++ ++/* DAC.STATUS bit masks and bit positions */ ++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ ++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ ++ ++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ ++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ ++ ++/* DAC.CH0GAINCAL bit masks and bit positions */ ++#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH0OFFSETCAL bit masks and bit positions */ ++#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* DAC.CH1GAINCAL bit masks and bit positions */ ++#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH1OFFSETCAL bit masks and bit positions */ ++#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ ++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HSMODE Predefined. */ ++/* AC_HSMODE Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* RTC - Real-Time Counter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* EBI - External Bus Interface */ ++/* EBI_CS.CTRLA bit masks and bit positions */ ++#define EBI_CS_ASPACE_gm 0x7C /* Address Space group mask. */ ++#define EBI_CS_ASPACE_gp 2 /* Address Space group position. */ ++#define EBI_CS_ASPACE0_bm (1<<2) /* Address Space bit 0 mask. */ ++#define EBI_CS_ASPACE0_bp 2 /* Address Space bit 0 position. */ ++#define EBI_CS_ASPACE1_bm (1<<3) /* Address Space bit 1 mask. */ ++#define EBI_CS_ASPACE1_bp 3 /* Address Space bit 1 position. */ ++#define EBI_CS_ASPACE2_bm (1<<4) /* Address Space bit 2 mask. */ ++#define EBI_CS_ASPACE2_bp 4 /* Address Space bit 2 position. */ ++#define EBI_CS_ASPACE3_bm (1<<5) /* Address Space bit 3 mask. */ ++#define EBI_CS_ASPACE3_bp 5 /* Address Space bit 3 position. */ ++#define EBI_CS_ASPACE4_bm (1<<6) /* Address Space bit 4 mask. */ ++#define EBI_CS_ASPACE4_bp 6 /* Address Space bit 4 position. */ ++ ++#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ ++#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ ++#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ ++#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ ++#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ ++#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ ++ ++/* EBI_CS.CTRLB bit masks and bit positions */ ++#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ ++#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ ++#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ ++#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ ++#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ ++#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ ++#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ ++#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ ++ ++#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ ++#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ ++ ++#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ ++#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ ++ ++#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ ++#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ ++#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ ++#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ ++#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ ++#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ ++ ++/* EBI.CTRL bit masks and bit positions */ ++#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ ++#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ ++#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ ++#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ ++#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ ++#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ ++ ++#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ ++#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ ++#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ ++#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ ++#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ ++#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ ++ ++#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ ++#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ ++#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ ++#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ ++#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ ++#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ ++ ++#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ ++#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ ++#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ ++#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ ++#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ ++#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ ++ ++/* EBI.SDRAMCTRLA bit masks and bit positions */ ++#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ ++#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ ++ ++#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ ++#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ ++ ++#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ ++#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ ++#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ ++#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ ++#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ ++#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ ++ ++/* EBI.SDRAMCTRLB bit masks and bit positions */ ++#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ ++#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ ++#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ ++#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ ++#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ ++#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ ++ ++#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ ++#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ ++#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ ++#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ ++#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ ++#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ ++#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ ++#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ ++ ++#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ ++#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ ++#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ ++#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ ++#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ ++#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ ++#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ ++#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ ++ ++/* EBI.SDRAMCTRLC bit masks and bit positions */ ++#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ ++#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ ++#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ ++#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ ++#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ ++#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ ++ ++#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ ++#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ ++#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ ++#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ ++#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ ++#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ ++#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ ++#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ ++ ++#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ ++#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ ++#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ ++#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ ++#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ ++#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ ++#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ ++#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Tisdahmeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Tisdahmeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Tisdahmeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Tisdahmeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Tisdahmeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Tisdahmeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* USB - USB */ ++/* USB_EP.STATUS bit masks and bit positions */ ++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ ++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ ++ ++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ ++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ ++ ++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ ++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ ++ ++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ ++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ ++ ++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ ++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ ++ ++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ ++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ ++ ++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ ++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ ++ ++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ ++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ ++ ++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ ++ ++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ ++ ++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ ++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ ++ ++/* USB_EP.CTRL bit masks and bit positions */ ++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ ++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ ++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ ++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ ++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ ++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ ++ ++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ ++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ ++ ++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ ++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ ++ ++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ ++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ ++ ++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ ++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ ++ ++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ ++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ ++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ ++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ ++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ ++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ ++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ ++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ ++ ++/* USB_EP.CNT bit masks and bit positions */ ++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ ++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ ++ ++/* USB.CTRLA bit masks and bit positions */ ++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ ++#define USB_ENABLE_bp 7 /* USB Enable bit position. */ ++ ++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ ++#define USB_SPEED_bp 6 /* Speed Select bit position. */ ++ ++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ ++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ ++ ++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ ++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ ++ ++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ ++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ ++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ ++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ ++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ ++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ ++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ ++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ ++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ ++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ ++ ++/* USB.CTRLB bit masks and bit positions */ ++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ ++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ ++ ++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ ++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ ++ ++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ ++#define USB_GNACK_bp 1 /* Global NACK bit position. */ ++ ++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ ++#define USB_ATTACH_bp 0 /* Attach bit position. */ ++ ++/* USB.STATUS bit masks and bit positions */ ++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ ++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ ++ ++#define USB_RESUME_bm 0x04 /* Resume bit mask. */ ++#define USB_RESUME_bp 2 /* Resume bit position. */ ++ ++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ ++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ ++ ++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ ++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ ++ ++/* USB.ADDR bit masks and bit positions */ ++#define USB_ADDR_gm 0x7F /* Device Address group mask. */ ++#define USB_ADDR_gp 0 /* Device Address group position. */ ++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ ++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ ++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ ++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ ++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ ++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ ++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ ++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ ++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ ++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ ++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ ++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ ++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ ++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ ++ ++/* USB.FIFOWP bit masks and bit positions */ ++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ ++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ ++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ ++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ ++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ ++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ ++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ ++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ ++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ ++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ ++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ ++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ ++ ++/* USB.FIFORP bit masks and bit positions */ ++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ ++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ ++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ ++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ ++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ ++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ ++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ ++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ ++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ ++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ ++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ ++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ ++ ++/* USB.INTCTRLA bit masks and bit positions */ ++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ ++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ ++ ++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ ++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ ++ ++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ ++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ ++ ++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ ++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ ++ ++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* USB.INTCTRLB bit masks and bit positions */ ++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ ++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ ++ ++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ ++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ ++ ++/* USB.INTFLAGSACLR bit masks and bit positions */ ++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ ++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ ++ ++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ ++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ ++ ++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ ++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ ++ ++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ ++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ ++ ++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ ++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ ++ ++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ ++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ ++ ++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ ++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ ++ ++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ ++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSASET bit masks and bit positions */ ++/* USB_SOFIF Predefined. */ ++/* USB_SOFIF Predefined. */ ++ ++/* USB_SUSPENDIF Predefined. */ ++/* USB_SUSPENDIF Predefined. */ ++ ++/* USB_RESUMEIF Predefined. */ ++/* USB_RESUMEIF Predefined. */ ++ ++/* USB_RSTIF Predefined. */ ++/* USB_RSTIF Predefined. */ ++ ++/* USB_CRCIF Predefined. */ ++/* USB_CRCIF Predefined. */ ++ ++/* USB_UNFIF Predefined. */ ++/* USB_UNFIF Predefined. */ ++ ++/* USB_OVFIF Predefined. */ ++/* USB_OVFIF Predefined. */ ++ ++/* USB_STALLIF Predefined. */ ++/* USB_STALLIF Predefined. */ ++ ++/* USB.INTFLAGSBCLR bit masks and bit positions */ ++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ ++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ ++ ++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ ++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSBSET bit masks and bit positions */ ++/* USB_TRNIF Predefined. */ ++/* USB_TRNIF Predefined. */ ++ ++/* USB_SETUPIF Predefined. */ ++/* USB_SETUPIF Predefined. */ ++ ++/* PORT - I/O Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_SPI_bm 0x20 /* SPI bit mask. */ ++#define PORT_SPI_bp 5 /* SPI bit position. */ ++ ++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ ++#define PORT_USART0_bp 4 /* USART0 bit position. */ ++ ++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ ++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ ++ ++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ ++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ ++ ++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ ++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ ++ ++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ ++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD Predefined. */ ++/* TC0_CMD Predefined. */ ++ ++/* TC0_LUPD Predefined. */ ++/* TC0_LUPD Predefined. */ ++ ++/* TC0_DIR Predefined. */ ++/* TC0_DIR Predefined. */ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV Predefined. */ ++/* TC0_CCDBV Predefined. */ ++ ++/* TC0_CCCBV Predefined. */ ++/* TC0_CCCBV Predefined. */ ++ ++/* TC0_CCBBV Predefined. */ ++/* TC0_CCBBV Predefined. */ ++ ++/* TC0_CCABV Predefined. */ ++/* TC0_CCABV Predefined. */ ++ ++/* TC0_PERBV Predefined. */ ++/* TC0_PERBV Predefined. */ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD Predefined. */ ++/* TC1_CMD Predefined. */ ++ ++/* TC1_LUPD Predefined. */ ++/* TC1_LUPD Predefined. */ ++ ++/* TC1_DIR Predefined. */ ++/* TC1_DIR Predefined. */ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV Predefined. */ ++/* TC1_CCBBV Predefined. */ ++ ++/* TC1_CCABV Predefined. */ ++/* TC1_CCABV Predefined. */ ++ ++/* TC1_PERBV Predefined. */ ++/* TC1_PERBV Predefined. */ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++/* TC2.CTRLA bit masks and bit positions */ ++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC2.CTRLB bit masks and bit positions */ ++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ ++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ ++ ++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ ++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ ++ ++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ ++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ ++ ++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ ++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ ++ ++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ ++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ ++ ++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ ++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ ++ ++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ ++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ ++ ++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ ++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ ++ ++/* TC2.CTRLC bit masks and bit positions */ ++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ ++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ ++ ++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ ++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ ++ ++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ ++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ ++ ++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ ++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ ++ ++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ ++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ ++ ++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ ++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ ++ ++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ ++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ ++ ++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ ++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ ++ ++/* TC2.CTRLE bit masks and bit positions */ ++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC2.INTCTRLA bit masks and bit positions */ ++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ ++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ ++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ ++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ ++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ ++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ ++ ++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ ++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ ++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ ++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ ++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ ++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ ++ ++/* TC2.INTCTRLB bit masks and bit positions */ ++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ ++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ ++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ ++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ ++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ ++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ ++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ ++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ ++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ ++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ ++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ ++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ ++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ ++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ ++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ ++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ ++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ ++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ ++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ ++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ ++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ ++ ++/* TC2.CTRLF bit masks and bit positions */ ++#define TC2_CMD_gm 0x0C /* Command group mask. */ ++#define TC2_CMD_gp 2 /* Command group position. */ ++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC2_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC2_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ ++#define TC2_CMDEN_gp 0 /* Command Enable group position. */ ++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ ++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ ++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ ++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ ++ ++/* TC2.INTFLAGS bit masks and bit positions */ ++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ ++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ ++ ++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ ++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ ++ ++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ ++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ ++ ++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ ++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ ++ ++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ ++ ++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ ++ ++/* AWEX - Timer/Counter Advanced Waveform Extension */ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++/* AWEX.STATUSSET bit masks and bit positions */ ++/* AWEX_FDF Predefined. */ ++/* AWEX_FDF Predefined. */ ++ ++/* AWEX_DTHSBUFV Predefined. */ ++/* AWEX_DTHSBUFV Predefined. */ ++ ++/* AWEX_DTLSBUFV Predefined. */ ++/* AWEX_DTLSBUFV Predefined. */ ++ ++/* HIRES - Timer/Counter High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ ++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ ++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ ++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ ++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ ++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ ++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ ++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ ++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ ++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ ++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ ++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ ++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ ++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ ++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ ++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ ++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ ++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ ++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ ++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ ++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* LOCKBIT - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* DMA interrupt vectors */ ++#define DMA_CH0_vect_num 6 ++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ ++#define DMA_CH1_vect_num 7 ++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ ++#define DMA_CH2_vect_num 8 ++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ ++#define DMA_CH3_vect_num 9 ++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LUNF_vect_num 14 ++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_HUNF_vect_num 15 ++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPA_vect_num 16 ++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPB_vect_num 17 ++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPC_vect_num 18 ++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPD_vect_num 19 ++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* USARTC1 interrupt vectors */ ++#define USARTC1_RXC_vect_num 28 ++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ ++#define USARTC1_DRE_vect_num 29 ++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ ++#define USARTC1_TXC_vect_num 30 ++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ ++ ++/* AES interrupt vectors */ ++#define AES_INT_vect_num 31 ++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* ACB interrupt vectors */ ++#define ACB_AC0_vect_num 36 ++#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ ++#define ACB_AC1_vect_num 37 ++#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ ++#define ACB_ACW_vect_num 38 ++#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ ++ ++/* ADCB interrupt vectors */ ++#define ADCB_CH0_vect_num 39 ++#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ ++#define ADCB_CH1_vect_num 40 ++#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ ++#define ADCB_CH2_vect_num 41 ++#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ ++#define ADCB_CH3_vect_num 42 ++#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LUNF_vect_num 47 ++#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_HUNF_vect_num 48 ++#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPA_vect_num 49 ++#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPB_vect_num 50 ++#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPC_vect_num 51 ++#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPD_vect_num 52 ++#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ ++ ++/* TCE1 interrupt vectors */ ++#define TCE1_OVF_vect_num 53 ++#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ ++#define TCE1_ERR_vect_num 54 ++#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ ++#define TCE1_CCA_vect_num 55 ++#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ ++#define TCE1_CCB_vect_num 56 ++#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ ++ ++/* SPIE interrupt vectors */ ++#define SPIE_INT_vect_num 57 ++#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* USARTE1 interrupt vectors */ ++#define USARTE1_RXC_vect_num 61 ++#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ ++#define USARTE1_DRE_vect_num 62 ++#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ ++#define USARTE1_TXC_vect_num 63 ++#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++#define ADCA_CH1_vect_num 72 ++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ ++#define ADCA_CH2_vect_num 73 ++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ ++#define ADCA_CH3_vect_num 74 ++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ ++ ++/* TWID interrupt vectors */ ++#define TWID_TWIS_vect_num 75 ++#define TWID_TWIS_vect _VECTOR(75) /* TWI Slave Interrupt */ ++#define TWID_TWIM_vect_num 76 ++#define TWID_TWIM_vect _VECTOR(76) /* TWI Master Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LUNF_vect_num 77 ++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_HUNF_vect_num 78 ++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPA_vect_num 79 ++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPB_vect_num 80 ++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPC_vect_num 81 ++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPD_vect_num 82 ++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ ++ ++/* TCD1 interrupt vectors */ ++#define TCD1_OVF_vect_num 83 ++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ ++#define TCD1_ERR_vect_num 84 ++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ ++#define TCD1_CCA_vect_num 85 ++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ ++#define TCD1_CCB_vect_num 86 ++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* USARTD1 interrupt vectors */ ++#define USARTD1_RXC_vect_num 91 ++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ ++#define USARTD1_DRE_vect_num 92 ++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ ++#define USARTD1_TXC_vect_num 93 ++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ ++ ++/* PORTQ interrupt vectors */ ++#define PORTQ_INT0_vect_num 94 ++#define PORTQ_INT0_vect _VECTOR(94) /* External Interrupt 0 */ ++#define PORTQ_INT1_vect_num 95 ++#define PORTQ_INT1_vect _VECTOR(95) /* External Interrupt 1 */ ++ ++/* PORTH interrupt vectors */ ++#define PORTH_INT0_vect_num 96 ++#define PORTH_INT0_vect _VECTOR(96) /* External Interrupt 0 */ ++#define PORTH_INT1_vect_num 97 ++#define PORTH_INT1_vect _VECTOR(97) /* External Interrupt 1 */ ++ ++/* PORTJ interrupt vectors */ ++#define PORTJ_INT0_vect_num 98 ++#define PORTJ_INT0_vect _VECTOR(98) /* External Interrupt 0 */ ++#define PORTJ_INT1_vect_num 99 ++#define PORTJ_INT1_vect _VECTOR(99) /* External Interrupt 1 */ ++ ++/* PORTK interrupt vectors */ ++#define PORTK_INT0_vect_num 100 ++#define PORTK_INT0_vect _VECTOR(100) /* External Interrupt 0 */ ++#define PORTK_INT1_vect_num 101 ++#define PORTK_INT1_vect _VECTOR(101) /* External Interrupt 1 */ ++ ++/* PORTF interrupt vectors */ ++#define PORTF_INT0_vect_num 104 ++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ ++#define PORTF_INT1_vect_num 105 ++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ ++ ++/* TWIF interrupt vectors */ ++#define TWIF_TWIS_vect_num 106 ++#define TWIF_TWIS_vect _VECTOR(106) /* TWI Slave Interrupt */ ++#define TWIF_TWIM_vect_num 107 ++#define TWIF_TWIM_vect _VECTOR(107) /* TWI Master Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_OVF_vect_num 108 ++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LUNF_vect_num 108 ++#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_ERR_vect_num 109 ++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_HUNF_vect_num 109 ++#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCA_vect_num 110 ++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPA_vect_num 110 ++#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCB_vect_num 111 ++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPB_vect_num 111 ++#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCC_vect_num 112 ++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPC_vect_num 112 ++#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCD_vect_num 113 ++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPD_vect_num 113 ++#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ ++ ++/* TCF1 interrupt vectors */ ++#define TCF1_OVF_vect_num 114 ++#define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */ ++#define TCF1_ERR_vect_num 115 ++#define TCF1_ERR_vect _VECTOR(115) /* Error Interrupt */ ++#define TCF1_CCA_vect_num 116 ++#define TCF1_CCA_vect _VECTOR(116) /* Compare or Capture A Interrupt */ ++#define TCF1_CCB_vect_num 117 ++#define TCF1_CCB_vect _VECTOR(117) /* Compare or Capture B Interrupt */ ++ ++/* SPIF interrupt vectors */ ++#define SPIF_INT_vect_num 118 ++#define SPIF_INT_vect _VECTOR(118) /* SPI Interrupt */ ++ ++/* USARTF0 interrupt vectors */ ++#define USARTF0_RXC_vect_num 119 ++#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ ++#define USARTF0_DRE_vect_num 120 ++#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ ++#define USARTF0_TXC_vect_num 121 ++#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ ++ ++/* USARTF1 interrupt vectors */ ++#define USARTF1_RXC_vect_num 122 ++#define USARTF1_RXC_vect _VECTOR(122) /* Reception Complete Interrupt */ ++#define USARTF1_DRE_vect_num 123 ++#define USARTF1_DRE_vect _VECTOR(123) /* Data Register Empty Interrupt */ ++#define USARTF1_TXC_vect_num 124 ++#define USARTF1_TXC_vect _VECTOR(124) /* Transmission Complete Interrupt */ ++ ++/* USB interrupt vectors */ ++#define USB_BUSEVENT_vect_num 125 ++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ ++#define USB_TRNCOMPL_vect_num 126 ++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (127 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (139264) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (131072) ++#define APP_SECTION_PAGE_SIZE (512) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x1E000) ++#define APPTABLE_SECTION_SIZE (8192) ++#define APPTABLE_SECTION_PAGE_SIZE (512) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x20000) ++#define BOOT_SECTION_SIZE (8192) ++#define BOOT_SECTION_PAGE_SIZE (512) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (16777216) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (2048) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (8192) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (2048) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (6) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (512) ++#define USER_SIGNATURES_PAGE_SIZE (512) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (64) ++#define PROD_SIGNATURES_PAGE_SIZE (512) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 512 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 */ ++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ ++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ ++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ ++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ ++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ ++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ ++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ ++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ ++#define FUSE0_DEFAULT (0xFF) ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x97 ++#define SIGNATURE_2 0x4C ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA128A1U_H_INCLUDED */ ++ +diff --git a/include/avr/iox128a3.h b/include/avr/iox128a3.h +index 7973b62..3d9e472 100644 +--- a/include/avr/iox128a3.h ++++ b/include/avr/iox128a3.h +@@ -1,6917 +1,6917 @@ +-/* Copyright (c) 2009-2010 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iox128a3.h 2200 2010-12-14 04:24:24Z arcanum $ */ +- +-/* avr/iox128a3.h - definitions for ATxmega128A3 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iox128a3.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATxmega128A3_H_ +-#define _AVR_ATxmega128A3_H_ 1 +- +- +-/* Ungrouped common registers */ +-#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +-#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +-#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +-#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +-#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +-#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +-#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +-#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +-#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +-#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +-#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +-#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +-#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +-#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +-#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +-#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +- +-/* Deprecated */ +-#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +-#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +-#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +-#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +-#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +-#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +-#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +-#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +-#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +-#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +-#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +-#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +-#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +-#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +-#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +-#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +- +-#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +-#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +-#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +-#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +-#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +-#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +-#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +-#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +-#define SREG _SFR_MEM8(0x003F) /* Status Register */ +- +- +-/* C Language Only */ +-#if !defined (__ASSEMBLER__) +- +-#include +- +-typedef volatile uint8_t register8_t; +-typedef volatile uint16_t register16_t; +-typedef volatile uint32_t register32_t; +- +- +-#ifdef _WORDREGISTER +-#undef _WORDREGISTER +-#endif +-#define _WORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register16_t regname; \ +- struct \ +- { \ +- register8_t regname ## L; \ +- register8_t regname ## H; \ +- }; \ +- } +- +-#ifdef _DWORDREGISTER +-#undef _DWORDREGISTER +-#endif +-#define _DWORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register32_t regname; \ +- struct \ +- { \ +- register8_t regname ## 0; \ +- register8_t regname ## 1; \ +- register8_t regname ## 2; \ +- register8_t regname ## 3; \ +- }; \ +- } +- +- +-/* +-========================================================================== +-IO Module Structures +-========================================================================== +-*/ +- +- +-/* +--------------------------------------------------------------------------- +-XOCD - On-Chip Debug System +--------------------------------------------------------------------------- +-*/ +- +-/* On-Chip Debug System */ +-typedef struct OCD_struct +-{ +- register8_t OCDR0; /* OCD Register 0 */ +- register8_t OCDR1; /* OCD Register 1 */ +-} OCD_t; +- +- +-/* CCP signatures */ +-typedef enum CCP_enum +-{ +- CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ +- CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +-} CCP_t; +- +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Clock System */ +-typedef struct CLK_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t PSCTRL; /* Prescaler Control Register */ +- register8_t LOCK; /* Lock register */ +- register8_t RTCCTRL; /* RTC Control Register */ +-} CLK_t; +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Power Reduction */ +-typedef struct PR_struct +-{ +- register8_t PRGEN; /* General Power Reduction */ +- register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ -+ register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ -@@ -416,6 +416,46 @@ typedef struct PMIC_struct - - /* - -------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ -+ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ -+ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ -+ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- - EVSYS - Event System - -------------------------------------------------------------------------- - */ -@@ -1005,6 +1045,15 @@ typedef struct ADC_struct - ADC_CH_t CH0; /* ADC Channel 0 */ - } ADC_t; - -+/* Current Limitation */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 225ksps max sampling rate */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 75ksps max sampling rate */ -+} ADC_CURRLIMIT_t; -+ - /* Positive input multiplexer selection */ - typedef enum ADC_CH_MUXPOS_enum - { -@@ -1059,6 +1108,7 @@ typedef enum ADC_CH_GAIN_enum - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ - } ADC_CH_GAIN_t; - - /* Conversion result resolution */ -@@ -2180,12 +2230,14 @@ IO Module Instances. Mapped to memory. - #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ - #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ - #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ - #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ - #define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ - #define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ - #define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ - #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ - #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ - #define PORTA (*(PORT_t *) 0x0600) /* Port A */ - #define PORTB (*(PORT_t *) 0x0620) /* Port B */ - #define PORTC (*(PORT_t *) 0x0640) /* Port C */ -@@ -2309,7 +2361,6 @@ IO Module Instances. Mapped to memory. - /* PR - Power Reduction */ - #define PR_PRGEN _SFR_MEM8(0x0070) - #define PR_PRPA _SFR_MEM8(0x0071) --#define PR_PRPB _SFR_MEM8(0x0072) - #define PR_PRPC _SFR_MEM8(0x0073) - #define PR_PRPD _SFR_MEM8(0x0074) - #define PR_PRPE _SFR_MEM8(0x0075) -@@ -2345,6 +2396,15 @@ IO Module Instances. Mapped to memory. - #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) - #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) - -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ - /* EVSYS - Event System */ - #define EVSYS_CH0MUX _SFR_MEM8(0x0180) - #define EVSYS_CH1MUX _SFR_MEM8(0x0181) -@@ -2423,6 +2483,22 @@ IO Module Instances. Mapped to memory. - #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) - #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -+/* TWIE - Two-Wire Interface E */ -+#define TWIE_CTRL _SFR_MEM8(0x04A0) -+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -+ - /* PORTA - Port A */ - #define PORTA_DIR _SFR_MEM8(0x0600) - #define PORTA_DIRSET _SFR_MEM8(0x0601) -@@ -2901,59 +2977,31 @@ IO Module Instances. Mapped to memory. - - - /* PR.PRGEN bit masks and bit positions */ --#define PR_AES_bm 0x10 /* AES bit mask. */ --#define PR_AES_bp 4 /* AES bit position. */ +- register8_t PRPC; /* Power Reduction Port C */ +- register8_t PRPD; /* Power Reduction Port D */ +- register8_t PRPE; /* Power Reduction Port E */ +- register8_t PRPF; /* Power Reduction Port F */ +-} PR_t; - --#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ --#define PR_EBI_bp 3 /* External Bus Interface bit position. */ +-/* System Clock Selection */ +-typedef enum CLK_SCLKSEL_enum +-{ +- CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ +- CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ +- CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ +- CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ +- CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +-} CLK_SCLKSEL_t; - - #define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ - #define PR_RTC_bp 2 /* Real-time Counter bit position. */ - - #define PR_EVSYS_bm 0x02 /* Event System bit mask. */ - #define PR_EVSYS_bp 1 /* Event System bit position. */ - --#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ --#define PR_DMA_bp 0 /* DMA-Controller bit position. */ +-/* Prescaler A Division Factor */ +-typedef enum CLK_PSADIV_enum +-{ +- CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ +- CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ +- CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ +- CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ +- CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ +- CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ +- CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ +- CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ +- CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ +- CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +-} CLK_PSADIV_t; +- +-/* Prescaler B and C Division Factor */ +-typedef enum CLK_PSBCDIV_enum +-{ +- CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ +- CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ +- CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ +- CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +-} CLK_PSBCDIV_t; +- +-/* RTC Clock Source */ +-typedef enum CLK_RTCSRC_enum +-{ +- CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ +- CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ +- CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ +- CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +-} CLK_RTCSRC_t; - - - /* PR.PRPA bit masks and bit positions */ --#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ --#define PR_DAC_bp 2 /* Port A DAC bit position. */ +-/* +--------------------------------------------------------------------------- +-SLEEP - Sleep Controller +--------------------------------------------------------------------------- +-*/ - - #define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ - #define PR_ADC_bp 1 /* Port A ADC bit position. */ - - #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ - #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - +-/* Sleep Controller */ +-typedef struct SLEEP_struct +-{ +- register8_t CTRL; /* Control Register */ +-} SLEEP_t; - --/* PR.PRPB bit masks and bit positions */ --/* PR_DAC_bm Predefined. */ --/* PR_DAC_bp Predefined. */ -- --/* PR_ADC_bm Predefined. */ --/* PR_ADC_bp Predefined. */ -- --/* PR_AC_bm Predefined. */ --/* PR_AC_bp Predefined. */ +-/* Sleep Mode */ +-typedef enum SLEEP_SMODE_enum +-{ +- SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ +- SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +- SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ +- SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ +- SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +-} SLEEP_SMODE_t; - - - /* PR.PRPC bit masks and bit positions */ - #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ - #define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - --#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ --#define PR_USART1_bp 5 /* Port C USART1 bit position. */ +-/* +--------------------------------------------------------------------------- +-OSC - Oscillator +--------------------------------------------------------------------------- +-*/ - - #define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ - #define PR_USART0_bp 4 /* Port C USART0 bit position. */ - - #define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ - #define PR_SPI_bp 3 /* Port C SPI bit position. */ - --#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ --#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ -+#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ -+#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ - - #define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ - #define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -@@ -2961,76 +3009,33 @@ IO Module Instances. Mapped to memory. - #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ - #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - +-/* Oscillator */ +-typedef struct OSC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t XOSCCTRL; /* External Oscillator Control Register */ +- register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ +- register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ +- register8_t PLLCTRL; /* PLL Control REgister */ +- register8_t DFLLCTRL; /* DFLL Control Register */ +-} OSC_t; - - /* PR.PRPD bit masks and bit positions */ --/* PR_TWI_bm Predefined. */ --/* PR_TWI_bp Predefined. */ +-/* Oscillator Frequency Range */ +-typedef enum OSC_FRQRANGE_enum +-{ +- OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ +- OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ +- OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ +- OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +-} OSC_FRQRANGE_t; - --/* PR_USART1_bm Predefined. */ --/* PR_USART1_bp Predefined. */ +-/* External Oscillator Selection and Startup Time */ +-typedef enum OSC_XOSCSEL_enum +-{ +- OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ +- OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ +- OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ +- OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ +- OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +-} OSC_XOSCSEL_t; - - /* PR_USART0_bm Predefined. */ - /* PR_USART0_bp Predefined. */ - - /* PR_SPI_bm Predefined. */ - /* PR_SPI_bp Predefined. */ - --/* PR_HIRES_bm Predefined. */ --/* PR_HIRES_bp Predefined. */ -- --/* PR_TC1_bm Predefined. */ --/* PR_TC1_bp Predefined. */ -- - /* PR_TC0_bm Predefined. */ - /* PR_TC0_bp Predefined. */ - -- - /* PR.PRPE bit masks and bit positions */ - /* PR_TWI_bm Predefined. */ - /* PR_TWI_bp Predefined. */ - --/* PR_USART1_bm Predefined. */ --/* PR_USART1_bp Predefined. */ -- - /* PR_USART0_bm Predefined. */ - /* PR_USART0_bp Predefined. */ - --/* PR_SPI_bm Predefined. */ --/* PR_SPI_bp Predefined. */ -- --/* PR_HIRES_bm Predefined. */ --/* PR_HIRES_bp Predefined. */ -- --/* PR_TC1_bm Predefined. */ --/* PR_TC1_bp Predefined. */ -- - /* PR_TC0_bm Predefined. */ - /* PR_TC0_bp Predefined. */ - -- - /* PR.PRPF bit masks and bit positions */ --/* PR_TWI_bm Predefined. */ --/* PR_TWI_bp Predefined. */ -- --/* PR_USART1_bm Predefined. */ --/* PR_USART1_bp Predefined. */ -- - /* PR_USART0_bm Predefined. */ - /* PR_USART0_bp Predefined. */ - --/* PR_SPI_bm Predefined. */ --/* PR_SPI_bp Predefined. */ -- --/* PR_HIRES_bm Predefined. */ --/* PR_HIRES_bp Predefined. */ -- --/* PR_TC1_bm Predefined. */ --/* PR_TC1_bp Predefined. */ -- - /* PR_TC0_bm Predefined. */ - /* PR_TC0_bp Predefined. */ - -- - /* SLEEP - Sleep Controller */ - /* SLEEP.CTRL bit masks and bit positions */ - #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -@@ -3311,6 +3316,37 @@ IO Module Instances. Mapped to memory. - #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - - -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+ - /* EVSYS - Event System */ - /* EVSYS.CH0MUX bit masks and bit positions */ - #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -@@ -3940,6 +3976,13 @@ IO Module Instances. Mapped to memory. - - - /* ADC.CTRLB bit masks and bit positions */ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ -+ - #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ - #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -@@ -5407,6 +5450,12 @@ IO Module Instances. Mapped to memory. - #define PORTE_INT1_vect_num 44 - #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -+/* TWIE interrupt vectors */ -+#define TWIE_TWIS_vect_num 45 -+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -+#define TWIE_TWIM_vect_num 46 -+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ -+ - /* TCE0 interrupt vectors */ - #define TCE0_OVF_vect_num 47 - #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -diff --git a/include/avr/iox128d4.h b/include/avr/iox128d4.h -new file mode 100644 -index 0000000..f1e7714 ---- /dev/null -+++ b/include/avr/iox128d4.h -@@ -0,0 +1,5515 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox128d4.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA128D4_H_INCLUDED -+#define _AVR_ATXMEGA128D4_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+VPORT - Virtual Ports -+-------------------------------------------------------------------------- -+*/ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t reserved_0x04; -+} CLK_t; -+ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t reserved_0x02; -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t PRPD; /* Power Reduction Port D */ -+ register8_t PRPE; /* Power Reduction Port E */ -+ register8_t PRPF; /* Power Reduction Port F */ -+} PR_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from 32.768 kHz internal oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from 32.768 kHz internal oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control Register */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+/* 2 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC2MCREF_enum -+{ -+ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC2MCREF_t; -+ -+/* 32 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC32MCREF_enum -+{ -+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC32MCREF_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t ANAINIT; /* Analog Startup Delay */ -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t AWEXLOCK; /* AWEX Lock */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORTCFG - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t VPCTRLA; /* Virtual Port Control Register A */ -+ register8_t VPCTRLB; /* Virtual Port Control Register B */ -+ register8_t CLKEVOUT; /* Clock and Event Out Register */ -+ register8_t reserved_0x05; -+ register8_t EVOUTSEL; /* Event Output Select */ -+} PORTCFG_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP02MAP_enum -+{ -+ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ -+ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ -+ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ -+ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ -+ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ -+ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ -+ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ -+ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ -+ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ -+ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ -+ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ -+ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ -+ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ -+ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ -+ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ -+ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -+} PORTCFG_VP02MAP_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP13MAP_enum -+{ -+ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ -+ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ -+ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ -+ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ -+ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ -+ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ -+ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ -+ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ -+ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ -+ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ -+ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ -+ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ -+ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ -+ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ -+ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ -+ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -+} PORTCFG_VP13MAP_t; -+ -+/* System Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ -+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ -+ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -+} PORTCFG_CLKOUT_t; -+ -+/* Peripheral Clock Output Select */ -+typedef enum PORTCFG_CLKOUTSEL_enum -+{ -+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -+} PORTCFG_CLKOUTSEL_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ -+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ -+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -+} PORTCFG_EVOUT_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+} EVSYS_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ -+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ -+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ -+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ -+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ -+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ -+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ -+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ -+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ -+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ -+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ -+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ -+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ -+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ -+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ -+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ -+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ -+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ -+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ -+ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ -+ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ -+ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ -+ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ -+ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ -+ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ -+ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ -+ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ -+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ -+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ -+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ -+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ -+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ -+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ -+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ -+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ -+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ -+ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ -+ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ -+ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ -+ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ -+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ -+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ -+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ -+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ -+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -+ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ -+ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ -+ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ -+ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ -+ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -+} EVSYS_CHMUX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ -+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ -+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ -+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ -+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} NVM_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t reserved_0x07; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+} ADC_t; -+ -+/* Current Limitation */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -+} ADC_CURRLIMIT_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+} ADC_CH_MUXNEG_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ -+ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ -+ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ -+ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC - Real-Time Counter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Real-Time Counter */ -+typedef struct RTC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary register */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ _WORDREGISTER(CNT); /* Count Register */ -+ _WORDREGISTER(PER); /* Period Register */ -+ _WORDREGISTER(COMP); /* Compare Register */ -+} RTC_t; -+ -+/* Prescaler Factor */ -+typedef enum RTC_PRESCALER_enum -+{ -+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ -+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ -+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ -+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ -+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ -+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ -+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ -+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -+} RTC_PRESCALER_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC_COMPINTLVL_enum -+{ -+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC_OVFINTLVL_enum -+{ -+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+} TWI_t; -+ -+/* SDA Hold Time */ -+typedef enum TWI_SDAHOLD_enum -+{ -+ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ -+ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ -+ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ -+ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -+} TWI_SDAHOLD_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - I/O Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INT0MASK; /* Port Interrupt 0 Mask */ -+ register8_t INT1MASK; /* Port Interrupt 1 Mask */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t REMAP; /* I/O Port Pin Remap Register */ -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Port Interrupt 0 Level */ -+typedef enum PORT_INT0LVL_enum -+{ -+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INT0LVL_t; -+ -+/* Port Interrupt 1 Level */ -+typedef enum PORT_INT1LVL_enum -+{ -+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ -+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ -+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -+} PORT_INT1LVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 0 */ -+typedef struct TC0_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC0_t; -+ -+ -+/* 16-bit Timer/Counter 1 */ -+typedef struct TC1_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+} TC1_t; -+ -+/* Clock Selection */ -+typedef enum TC_CLKSEL_enum -+{ -+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_CLKSEL_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC_WGMODE_enum -+{ -+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC_WGMODE_t; -+ -+/* Byte Mode */ -+typedef enum TC_BYTEM_enum -+{ -+ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ -+ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -+} TC_BYTEM_t; -+ -+/* Event Action */ -+typedef enum TC_EVACT_enum -+{ -+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ -+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ -+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ -+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ -+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ -+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC_EVSEL_enum -+{ -+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_EVSEL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC_ERRINTLVL_enum -+{ -+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC_OVFINTLVL_enum -+{ -+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_OVFINTLVL_t; -+ -+/* Compare or Capture D Interrupt Level */ -+typedef enum TC_CCDINTLVL_enum -+{ -+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC_CCDINTLVL_t; -+ -+/* Compare or Capture C Interrupt Level */ -+typedef enum TC_CCCINTLVL_enum -+{ -+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC_CCCINTLVL_t; -+ -+/* Compare or Capture B Interrupt Level */ -+typedef enum TC_CCBINTLVL_enum -+{ -+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_CCBINTLVL_t; -+ -+/* Compare or Capture A Interrupt Level */ -+typedef enum TC_CCAINTLVL_enum -+{ -+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_CCAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC_CMD_enum -+{ -+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC2 - 16-bit Timer/Counter type 2 -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter type 2 */ -+typedef struct TC2_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t reserved_0x03; -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t reserved_0x08; -+ register8_t CTRLF; /* Control Register F */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t LCNT; /* Low Byte Count */ -+ register8_t HCNT; /* High Byte Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t LPER; /* Low Byte Period */ -+ register8_t HPER; /* High Byte Period */ -+ register8_t LCMPA; /* Low Byte Compare A */ -+ register8_t HCMPA; /* High Byte Compare A */ -+ register8_t LCMPB; /* Low Byte Compare B */ -+ register8_t HCMPB; /* High Byte Compare B */ -+ register8_t LCMPC; /* Low Byte Compare C */ -+ register8_t HCMPC; /* High Byte Compare C */ -+ register8_t LCMPD; /* Low Byte Compare D */ -+ register8_t HCMPD; /* High Byte Compare D */ -+} TC2_t; -+ -+/* Clock Selection */ -+typedef enum TC2_CLKSEL_enum -+{ -+ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC2_CLKSEL_t; -+ -+/* Byte Mode */ -+typedef enum TC2_BYTEM_enum -+{ -+ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ -+ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -+} TC2_BYTEM_t; -+ -+/* High Byte Underflow Interrupt Level */ -+typedef enum TC2_HUNFINTLVL_enum -+{ -+ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_HUNFINTLVL_t; -+ -+/* Low Byte Underflow Interrupt Level */ -+typedef enum TC2_LUNFINTLVL_enum -+{ -+ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LUNFINTLVL_t; -+ -+/* Low Byte Compare D Interrupt Level */ -+typedef enum TC2_LCMPDINTLVL_enum -+{ -+ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC2_LCMPDINTLVL_t; -+ -+/* Low Byte Compare C Interrupt Level */ -+typedef enum TC2_LCMPCINTLVL_enum -+{ -+ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC2_LCMPCINTLVL_t; -+ -+/* Low Byte Compare B Interrupt Level */ -+typedef enum TC2_LCMPBINTLVL_enum -+{ -+ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_LCMPBINTLVL_t; -+ -+/* Low Byte Compare A Interrupt Level */ -+typedef enum TC2_LCMPAINTLVL_enum -+{ -+ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LCMPAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMD_enum -+{ -+ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC2_CMD_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMDEN_enum -+{ -+ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ -+ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ -+ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -+} TC2_CMDEN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AWEX - Timer/Counter Advanced Waveform Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Advanced Waveform Extension */ -+typedef struct AWEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t FDEMASK; /* Fault Detection Event Mask */ -+ register8_t FDCTRL; /* Fault Detection Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t STATUSSET; /* Status Set Register */ -+ register8_t DTBOTH; /* Dead Time Both Sides */ -+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ -+ register8_t DTLS; /* Dead Time Low Side */ -+ register8_t DTHS; /* Dead Time High Side */ -+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ -+ register8_t DTHSBUF; /* Dead Time High Side Buffer */ -+ register8_t OUTOVEN; /* Output Override Enable */ -+} AWEX_t; -+ -+/* Fault Detect Action */ -+typedef enum AWEX_FDACT_enum -+{ -+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ -+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -+} AWEX_FDACT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+HIRES - Timer/Counter High-Resolution Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register */ -+} HIRES_t; -+ -+/* High Resolution Enable */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ -+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+} IRDA_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t reserved_0x00; -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+} NVM_FUSES_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* Timer Oscillator pin location */ -+typedef enum TOSCSEL_enum -+{ -+ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ -+ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -+} TOSCSEL_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -+} BOD_t; -+ -+/* BOD operation */ -+typedef enum BODACT_enum -+{ -+ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BODACT_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WDP_enum -+{ -+ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ -+ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ -+ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ -+ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ -+ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ -+ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ -+ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ -+ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ -+ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ -+ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ -+ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -+} WDP_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LOCKBIT - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ -+ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+} NVM_PROD_SIGNATURES_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -+#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -+#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -+#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -+#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* DFLL - DFLL */ -+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -+#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -+#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPD _SFR_MEM8(0x0074) -+#define PR_PRPE _SFR_MEM8(0x0075) -+#define PR_PRPF _SFR_MEM8(0x0076) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_ANAINIT _SFR_MEM8(0x0097) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_AWEXLOCK _SFR_MEM8(0x0099) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCA_CTRLA _SFR_MEM8(0x0200) -+#define ADCA_CTRLB _SFR_MEM8(0x0201) -+#define ADCA_REFCTRL _SFR_MEM8(0x0202) -+#define ADCA_EVCTRL _SFR_MEM8(0x0203) -+#define ADCA_PRESCALER _SFR_MEM8(0x0204) -+#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -+#define ADCA_TEMP _SFR_MEM8(0x0207) -+#define ADCA_CAL _SFR_MEM16(0x020C) -+#define ADCA_CH0RES _SFR_MEM16(0x0210) -+#define ADCA_CMP _SFR_MEM16(0x0218) -+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -+#define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -+ -+/* AC - Analog Comparator */ -+#define ACA_AC0CTRL _SFR_MEM8(0x0380) -+#define ACA_AC1CTRL _SFR_MEM8(0x0381) -+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -+#define ACA_CTRLA _SFR_MEM8(0x0384) -+#define ACA_CTRLB _SFR_MEM8(0x0385) -+#define ACA_WINCTRL _SFR_MEM8(0x0386) -+#define ACA_STATUS _SFR_MEM8(0x0387) -+ -+/* RTC - Real-Time Counter */ -+#define RTC_CTRL _SFR_MEM8(0x0400) -+#define RTC_STATUS _SFR_MEM8(0x0401) -+#define RTC_INTCTRL _SFR_MEM8(0x0402) -+#define RTC_INTFLAGS _SFR_MEM8(0x0403) -+#define RTC_TEMP _SFR_MEM8(0x0404) -+#define RTC_CNT _SFR_MEM16(0x0408) -+#define RTC_PER _SFR_MEM16(0x040A) -+#define RTC_COMP _SFR_MEM16(0x040C) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIE_CTRL _SFR_MEM8(0x04A0) -+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -+ -+/* PORT - I/O Ports */ -+#define PORTA_DIR _SFR_MEM8(0x0600) -+#define PORTA_DIRSET _SFR_MEM8(0x0601) -+#define PORTA_DIRCLR _SFR_MEM8(0x0602) -+#define PORTA_DIRTGL _SFR_MEM8(0x0603) -+#define PORTA_OUT _SFR_MEM8(0x0604) -+#define PORTA_OUTSET _SFR_MEM8(0x0605) -+#define PORTA_OUTCLR _SFR_MEM8(0x0606) -+#define PORTA_OUTTGL _SFR_MEM8(0x0607) -+#define PORTA_IN _SFR_MEM8(0x0608) -+#define PORTA_INTCTRL _SFR_MEM8(0x0609) -+#define PORTA_INT0MASK _SFR_MEM8(0x060A) -+#define PORTA_INT1MASK _SFR_MEM8(0x060B) -+#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_REMAP _SFR_MEM8(0x060E) -+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -+ -+/* PORT - I/O Ports */ -+#define PORTB_DIR _SFR_MEM8(0x0620) -+#define PORTB_DIRSET _SFR_MEM8(0x0621) -+#define PORTB_DIRCLR _SFR_MEM8(0x0622) -+#define PORTB_DIRTGL _SFR_MEM8(0x0623) -+#define PORTB_OUT _SFR_MEM8(0x0624) -+#define PORTB_OUTSET _SFR_MEM8(0x0625) -+#define PORTB_OUTCLR _SFR_MEM8(0x0626) -+#define PORTB_OUTTGL _SFR_MEM8(0x0627) -+#define PORTB_IN _SFR_MEM8(0x0628) -+#define PORTB_INTCTRL _SFR_MEM8(0x0629) -+#define PORTB_INT0MASK _SFR_MEM8(0x062A) -+#define PORTB_INT1MASK _SFR_MEM8(0x062B) -+#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -+#define PORTB_REMAP _SFR_MEM8(0x062E) -+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INT0MASK _SFR_MEM8(0x064A) -+#define PORTC_INT1MASK _SFR_MEM8(0x064B) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INT0MASK _SFR_MEM8(0x066A) -+#define PORTD_INT1MASK _SFR_MEM8(0x066B) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTE_DIR _SFR_MEM8(0x0680) -+#define PORTE_DIRSET _SFR_MEM8(0x0681) -+#define PORTE_DIRCLR _SFR_MEM8(0x0682) -+#define PORTE_DIRTGL _SFR_MEM8(0x0683) -+#define PORTE_OUT _SFR_MEM8(0x0684) -+#define PORTE_OUTSET _SFR_MEM8(0x0685) -+#define PORTE_OUTCLR _SFR_MEM8(0x0686) -+#define PORTE_OUTTGL _SFR_MEM8(0x0687) -+#define PORTE_IN _SFR_MEM8(0x0688) -+#define PORTE_INTCTRL _SFR_MEM8(0x0689) -+#define PORTE_INT0MASK _SFR_MEM8(0x068A) -+#define PORTE_INT1MASK _SFR_MEM8(0x068B) -+#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -+#define PORTE_REMAP _SFR_MEM8(0x068E) -+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -+#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCC0_CTRLA _SFR_MEM8(0x0800) -+#define TCC0_CTRLB _SFR_MEM8(0x0801) -+#define TCC0_CTRLC _SFR_MEM8(0x0802) -+#define TCC0_CTRLD _SFR_MEM8(0x0803) -+#define TCC0_CTRLE _SFR_MEM8(0x0804) -+#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -+#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -+#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -+#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC0_TEMP _SFR_MEM8(0x080F) -+#define TCC0_CNT _SFR_MEM16(0x0820) -+#define TCC0_PER _SFR_MEM16(0x0826) -+#define TCC0_CCA _SFR_MEM16(0x0828) -+#define TCC0_CCB _SFR_MEM16(0x082A) -+#define TCC0_CCC _SFR_MEM16(0x082C) -+#define TCC0_CCD _SFR_MEM16(0x082E) -+#define TCC0_PERBUF _SFR_MEM16(0x0836) -+#define TCC0_CCABUF _SFR_MEM16(0x0838) -+#define TCC0_CCBBUF _SFR_MEM16(0x083A) -+#define TCC0_CCCBUF _SFR_MEM16(0x083C) -+#define TCC0_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCC2_CTRLA _SFR_MEM8(0x0800) -+#define TCC2_CTRLB _SFR_MEM8(0x0801) -+#define TCC2_CTRLC _SFR_MEM8(0x0802) -+#define TCC2_CTRLE _SFR_MEM8(0x0804) -+#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC2_CTRLF _SFR_MEM8(0x0809) -+#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC2_LCNT _SFR_MEM8(0x0820) -+#define TCC2_HCNT _SFR_MEM8(0x0821) -+#define TCC2_LPER _SFR_MEM8(0x0826) -+#define TCC2_HPER _SFR_MEM8(0x0827) -+#define TCC2_LCMPA _SFR_MEM8(0x0828) -+#define TCC2_HCMPA _SFR_MEM8(0x0829) -+#define TCC2_LCMPB _SFR_MEM8(0x082A) -+#define TCC2_HCMPB _SFR_MEM8(0x082B) -+#define TCC2_LCMPC _SFR_MEM8(0x082C) -+#define TCC2_HCMPC _SFR_MEM8(0x082D) -+#define TCC2_LCMPD _SFR_MEM8(0x082E) -+#define TCC2_HCMPD _SFR_MEM8(0x082F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCC1_CTRLA _SFR_MEM8(0x0840) -+#define TCC1_CTRLB _SFR_MEM8(0x0841) -+#define TCC1_CTRLC _SFR_MEM8(0x0842) -+#define TCC1_CTRLD _SFR_MEM8(0x0843) -+#define TCC1_CTRLE _SFR_MEM8(0x0844) -+#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -+#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -+#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -+#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC1_TEMP _SFR_MEM8(0x084F) -+#define TCC1_CNT _SFR_MEM16(0x0860) -+#define TCC1_PER _SFR_MEM16(0x0866) -+#define TCC1_CCA _SFR_MEM16(0x0868) -+#define TCC1_CCB _SFR_MEM16(0x086A) -+#define TCC1_PERBUF _SFR_MEM16(0x0876) -+#define TCC1_CCABUF _SFR_MEM16(0x0878) -+#define TCC1_CCBBUF _SFR_MEM16(0x087A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXC_CTRL _SFR_MEM8(0x0880) -+#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -+#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -+#define AWEXC_STATUS _SFR_MEM8(0x0884) -+#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -+#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -+#define AWEXC_DTLS _SFR_MEM8(0x0888) -+#define AWEXC_DTHS _SFR_MEM8(0x0889) -+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x0890) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08A0) -+#define USARTC0_STATUS _SFR_MEM8(0x08A1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -+#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -+#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIC_CTRL _SFR_MEM8(0x08C0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -+#define SPIC_STATUS _SFR_MEM8(0x08C2) -+#define SPIC_DATA _SFR_MEM8(0x08C3) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCD0_CTRLA _SFR_MEM8(0x0900) -+#define TCD0_CTRLB _SFR_MEM8(0x0901) -+#define TCD0_CTRLC _SFR_MEM8(0x0902) -+#define TCD0_CTRLD _SFR_MEM8(0x0903) -+#define TCD0_CTRLE _SFR_MEM8(0x0904) -+#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -+#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -+#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -+#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -+#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD0_TEMP _SFR_MEM8(0x090F) -+#define TCD0_CNT _SFR_MEM16(0x0920) -+#define TCD0_PER _SFR_MEM16(0x0926) -+#define TCD0_CCA _SFR_MEM16(0x0928) -+#define TCD0_CCB _SFR_MEM16(0x092A) -+#define TCD0_CCC _SFR_MEM16(0x092C) -+#define TCD0_CCD _SFR_MEM16(0x092E) -+#define TCD0_PERBUF _SFR_MEM16(0x0936) -+#define TCD0_CCABUF _SFR_MEM16(0x0938) -+#define TCD0_CCBBUF _SFR_MEM16(0x093A) -+#define TCD0_CCCBUF _SFR_MEM16(0x093C) -+#define TCD0_CCDBUF _SFR_MEM16(0x093E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCD2_CTRLA _SFR_MEM8(0x0900) -+#define TCD2_CTRLB _SFR_MEM8(0x0901) -+#define TCD2_CTRLC _SFR_MEM8(0x0902) -+#define TCD2_CTRLE _SFR_MEM8(0x0904) -+#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD2_CTRLF _SFR_MEM8(0x0909) -+#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD2_LCNT _SFR_MEM8(0x0920) -+#define TCD2_HCNT _SFR_MEM8(0x0921) -+#define TCD2_LPER _SFR_MEM8(0x0926) -+#define TCD2_HPER _SFR_MEM8(0x0927) -+#define TCD2_LCMPA _SFR_MEM8(0x0928) -+#define TCD2_HCMPA _SFR_MEM8(0x0929) -+#define TCD2_LCMPB _SFR_MEM8(0x092A) -+#define TCD2_HCMPB _SFR_MEM8(0x092B) -+#define TCD2_LCMPC _SFR_MEM8(0x092C) -+#define TCD2_HCMPC _SFR_MEM8(0x092D) -+#define TCD2_LCMPD _SFR_MEM8(0x092E) -+#define TCD2_HCMPD _SFR_MEM8(0x092F) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD0_DATA _SFR_MEM8(0x09A0) -+#define USARTD0_STATUS _SFR_MEM8(0x09A1) -+#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -+#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -+#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPID_CTRL _SFR_MEM8(0x09C0) -+#define SPID_INTCTRL _SFR_MEM8(0x09C1) -+#define SPID_STATUS _SFR_MEM8(0x09C2) -+#define SPID_DATA _SFR_MEM8(0x09C3) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCE0_CTRLA _SFR_MEM8(0x0A00) -+#define TCE0_CTRLB _SFR_MEM8(0x0A01) -+#define TCE0_CTRLC _SFR_MEM8(0x0A02) -+#define TCE0_CTRLD _SFR_MEM8(0x0A03) -+#define TCE0_CTRLE _SFR_MEM8(0x0A04) -+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE0_TEMP _SFR_MEM8(0x0A0F) -+#define TCE0_CNT _SFR_MEM16(0x0A20) -+#define TCE0_PER _SFR_MEM16(0x0A26) -+#define TCE0_CCA _SFR_MEM16(0x0A28) -+#define TCE0_CCB _SFR_MEM16(0x0A2A) -+#define TCE0_CCC _SFR_MEM16(0x0A2C) -+#define TCE0_CCD _SFR_MEM16(0x0A2E) -+#define TCE0_PERBUF _SFR_MEM16(0x0A36) -+#define TCE0_CCABUF _SFR_MEM16(0x0A38) -+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* VPORT - Virtual Ports */ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ -+#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ -+ -+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -+ -+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ -+ -+/* PR.PRPD bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPE bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPF bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -+#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -+#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ -+ -+#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ -+ -+#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -+#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.ANAINIT bit masks and bit positions */ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.AWEXLOCK bit masks and bit positions */ -+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* PORTCFG - Port Configuration */ -+/* PORTCFG.VPCTRLA bit masks and bit positions */ -+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ -+ -+/* PORTCFG.VPCTRLB bit masks and bit positions */ -+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ -+ -+/* PORTCFG.CLKEVOUT bit masks and bit positions */ -+#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ -+ -+#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -+#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -+#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -+#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -+#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -+#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ -+ -+#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -+#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ -+ -+#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -+#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ -+ -+/* PORTCFG.EVOUTSEL bit masks and bit positions */ -+#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -+#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -+#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -+#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -+#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -+#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -+#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -+#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0x7F /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ -+ -+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ -+ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -+#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -+#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -+#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -+#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -+#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -+#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -+#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -+#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -+#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ -+ -+#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -+#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -+#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -+#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -+#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -+#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -+#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -+#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -+#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -+#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -+#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* RTC - Real-Time Counter */ -+/* RTC.CTRL bit masks and bit positions */ -+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ -+ -+/* RTC.STATUS bit masks and bit positions */ -+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC.INTCTRL bit masks and bit positions */ -+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC.INTFLAGS bit masks and bit positions */ -+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* PORT - I/O Port Configuration */ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ -+ -+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -+#define PORT_SPI_bp 5 /* SPI bit position. */ -+ -+#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -+#define PORT_USART0_bp 4 /* USART0 bit position. */ -+ -+#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -+#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ -+ -+#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -+#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ -+ -+#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -+#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ -+ -+#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -+#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ -+ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC0.CTRLA bit masks and bit positions */ -+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC0.CTRLB bit masks and bit positions */ -+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ -+ -+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ -+ -+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC0.CTRLC bit masks and bit positions */ -+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ -+ -+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ -+ -+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC0.CTRLD bit masks and bit positions */ -+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC0_EVACT_gp 5 /* Event Action group position. */ -+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC0.CTRLE bit masks and bit positions */ -+#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC0.INTCTRLA bit masks and bit positions */ -+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC0.INTCTRLB bit masks and bit positions */ -+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ -+ -+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ -+ -+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC0.CTRLFCLR bit masks and bit positions */ -+#define TC0_CMD_gm 0x0C /* Command group mask. */ -+#define TC0_CMD_gp 2 /* Command group position. */ -+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC0_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC0_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC0_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC0.CTRLFSET bit masks and bit positions */ -+/* TC0_CMD Predefined. */ -+/* TC0_CMD Predefined. */ -+ -+/* TC0_LUPD Predefined. */ -+/* TC0_LUPD Predefined. */ -+ -+/* TC0_DIR Predefined. */ -+/* TC0_DIR Predefined. */ -+ -+/* TC0.CTRLGCLR bit masks and bit positions */ -+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ -+ -+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ -+ -+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC0.CTRLGSET bit masks and bit positions */ -+/* TC0_CCDBV Predefined. */ -+/* TC0_CCDBV Predefined. */ -+ -+/* TC0_CCCBV Predefined. */ -+/* TC0_CCCBV Predefined. */ -+ -+/* TC0_CCBBV Predefined. */ -+/* TC0_CCBBV Predefined. */ -+ -+/* TC0_CCABV Predefined. */ -+/* TC0_CCABV Predefined. */ -+ -+/* TC0_PERBV Predefined. */ -+/* TC0_PERBV Predefined. */ -+ -+/* TC0.INTFLAGS bit masks and bit positions */ -+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ -+ -+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ -+ -+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC1.CTRLA bit masks and bit positions */ -+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC1.CTRLB bit masks and bit positions */ -+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC1.CTRLC bit masks and bit positions */ -+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC1.CTRLD bit masks and bit positions */ -+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC1_EVACT_gp 5 /* Event Action group position. */ -+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC1.CTRLE bit masks and bit positions */ -+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ -+ -+/* TC1.INTCTRLA bit masks and bit positions */ -+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC1.INTCTRLB bit masks and bit positions */ -+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC1.CTRLFCLR bit masks and bit positions */ -+#define TC1_CMD_gm 0x0C /* Command group mask. */ -+#define TC1_CMD_gp 2 /* Command group position. */ -+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC1_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC1_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC1_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC1.CTRLFSET bit masks and bit positions */ -+/* TC1_CMD Predefined. */ -+/* TC1_CMD Predefined. */ -+ -+/* TC1_LUPD Predefined. */ -+/* TC1_LUPD Predefined. */ -+ -+/* TC1_DIR Predefined. */ -+/* TC1_DIR Predefined. */ -+ -+/* TC1.CTRLGCLR bit masks and bit positions */ -+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC1.CTRLGSET bit masks and bit positions */ -+/* TC1_CCBBV Predefined. */ -+/* TC1_CCBBV Predefined. */ -+ -+/* TC1_CCABV Predefined. */ -+/* TC1_CCABV Predefined. */ -+ -+/* TC1_PERBV Predefined. */ -+/* TC1_PERBV Predefined. */ -+ -+/* TC1.INTFLAGS bit masks and bit positions */ -+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+/* TC2.CTRLA bit masks and bit positions */ -+#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC2.CTRLB bit masks and bit positions */ -+#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -+#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ -+ -+#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -+#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ -+ -+#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -+#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ -+ -+#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -+#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ -+ -+#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -+#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ -+ -+#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -+#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ -+ -+#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -+#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ -+ -+#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -+#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ -+ -+/* TC2.CTRLC bit masks and bit positions */ -+#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -+#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ -+ -+#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -+#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ -+ -+#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -+#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ -+ -+#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -+#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ -+ -+#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -+#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ -+ -+#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -+#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ -+ -+#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -+#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ -+ -+#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -+#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ -+ -+/* TC2.CTRLE bit masks and bit positions */ -+#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC2.INTCTRLA bit masks and bit positions */ -+#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -+#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -+#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -+#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -+#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -+#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ -+ -+#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -+#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -+#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -+#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -+#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -+#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ -+ -+/* TC2.INTCTRLB bit masks and bit positions */ -+#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -+#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -+#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -+#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -+#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -+#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -+#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -+#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -+#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -+#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -+#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -+#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -+#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -+#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -+#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -+#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -+#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -+#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -+#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -+#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -+#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ -+ -+/* TC2.CTRLF bit masks and bit positions */ -+#define TC2_CMD_gm 0x0C /* Command group mask. */ -+#define TC2_CMD_gp 2 /* Command group position. */ -+#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC2_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -+#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -+#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -+#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -+#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -+#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ -+ -+/* TC2.INTFLAGS bit masks and bit positions */ -+#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -+#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ -+ -+#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -+#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ -+ -+#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -+#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ -+ -+#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -+#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ -+ -+#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ -+ -+#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ -+ -+/* AWEX - Timer/Counter Advanced Waveform Extension */ -+/* AWEX.CTRL bit masks and bit positions */ -+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ -+ -+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ -+ -+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ -+ -+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ -+ -+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ -+ -+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ -+ -+/* AWEX.FDCTRL bit masks and bit positions */ -+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ -+ -+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ -+ -+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ -+ -+/* AWEX.STATUS bit masks and bit positions */ -+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ -+ -+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ -+ -+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ -+ -+/* AWEX.STATUSSET bit masks and bit positions */ -+/* AWEX_FDF Predefined. */ -+/* AWEX_FDF Predefined. */ -+ -+/* AWEX_DTHSBUFV Predefined. */ -+/* AWEX_DTHSBUFV Predefined. */ -+ -+/* AWEX_DTLSBUFV Predefined. */ -+/* AWEX_DTLSBUFV Predefined. */ -+ -+/* HIRES - Timer/Counter High-Resolution Extension */ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -+#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* LOCKBIT - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT0_vect_num 2 -+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -+#define PORTC_INT1_vect_num 3 -+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT0_vect_num 4 -+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -+#define PORTR_INT1_vect_num 5 -+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ -+ -+/* RTC interrupt vectors */ -+#define RTC_OVF_vect_num 10 -+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -+#define RTC_COMP_vect_num 11 -+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 12 -+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 13 -+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_OVF_vect_num 14 -+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LUNF_vect_num 14 -+#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_ERR_vect_num 15 -+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_HUNF_vect_num 15 -+#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCA_vect_num 16 -+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPA_vect_num 16 -+#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCB_vect_num 17 -+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPB_vect_num 17 -+#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCC_vect_num 18 -+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPC_vect_num 18 -+#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCD_vect_num 19 -+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPD_vect_num 19 -+#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ -+ -+/* TCC1 interrupt vectors */ -+#define TCC1_OVF_vect_num 20 -+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -+#define TCC1_ERR_vect_num 21 -+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -+#define TCC1_CCA_vect_num 22 -+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -+#define TCC1_CCB_vect_num 23 -+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 24 -+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 25 -+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 26 -+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 27 -+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 32 -+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -+#define NVM_SPM_vect_num 33 -+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ -+ -+/* PORTB interrupt vectors */ -+#define PORTB_INT0_vect_num 34 -+#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -+#define PORTB_INT1_vect_num 35 -+#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ -+ -+/* PORTE interrupt vectors */ -+#define PORTE_INT0_vect_num 43 -+#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -+#define PORTE_INT1_vect_num 44 -+#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ -+ -+/* TWIE interrupt vectors */ -+#define TWIE_TWIS_vect_num 45 -+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -+#define TWIE_TWIM_vect_num 46 -+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_OVF_vect_num 47 -+#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -+#define TCE0_ERR_vect_num 48 -+#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -+#define TCE0_CCA_vect_num 49 -+#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -+#define TCE0_CCB_vect_num 50 -+#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -+#define TCE0_CCC_vect_num 51 -+#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -+#define TCE0_CCD_vect_num 52 -+#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ -+ -+/* USARTE0 interrupt vectors */ -+#define USARTE0_RXC_vect_num 58 -+#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -+#define USARTE0_DRE_vect_num 59 -+#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -+#define USARTE0_TXC_vect_num 60 -+#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT0_vect_num 64 -+#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -+#define PORTD_INT1_vect_num 65 -+#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ -+ -+/* PORTA interrupt vectors */ -+#define PORTA_INT0_vect_num 66 -+#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -+#define PORTA_INT1_vect_num 67 -+#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ -+ -+/* ACA interrupt vectors */ -+#define ACA_AC0_vect_num 68 -+#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -+#define ACA_AC1_vect_num 69 -+#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -+#define ACA_ACW_vect_num 70 -+#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ -+ -+/* ADCA interrupt vectors */ -+#define ADCA_CH0_vect_num 71 -+#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_OVF_vect_num 77 -+#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LUNF_vect_num 77 -+#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_ERR_vect_num 78 -+#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_HUNF_vect_num 78 -+#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCA_vect_num 79 -+#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPA_vect_num 79 -+#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCB_vect_num 80 -+#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPB_vect_num 80 -+#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCC_vect_num 81 -+#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPC_vect_num 81 -+#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCD_vect_num 82 -+#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPD_vect_num 82 -+#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ -+ -+/* SPID interrupt vectors */ -+#define SPID_INT_vect_num 87 -+#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ -+ -+/* USARTD0 interrupt vectors */ -+#define USARTD0_RXC_vect_num 88 -+#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -+#define USARTD0_DRE_vect_num 89 -+#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -+#define USARTD0_TXC_vect_num 90 -+#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (91 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (139264) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (131072) -+#define APP_SECTION_PAGE_SIZE (256) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0x1E000) -+#define APPTABLE_SECTION_SIZE (8192) -+#define APPTABLE_SECTION_PAGE_SIZE (256) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x20000) -+#define BOOT_SECTION_SIZE (8192) -+#define BOOT_SECTION_PAGE_SIZE (256) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (16384) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (2048) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (8192) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (2048) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (6) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (256) -+#define USER_SIGNATURES_PAGE_SIZE (256) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (64) -+#define PROD_SIGNATURES_PAGE_SIZE (256) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 256 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 6 -+ -+/* Fuse Byte 0 Reserved */ -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x97 -+#define SIGNATURE_2 0x47 -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA128D4_H_INCLUDED */ -+ -diff --git a/include/avr/iox16a4u.h b/include/avr/iox16a4u.h -new file mode 100644 -index 0000000..eb81490 ---- /dev/null -+++ b/include/avr/iox16a4u.h -@@ -0,0 +1,7240 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox16a4u.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA16A4U_H_INCLUDED -+#define _AVR_ATXMEGA16A4U_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -+#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -+#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -+#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -+#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -+#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -+#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -+#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -+#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -+#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -+#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -+#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -+#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -+#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -+#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -+#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -+#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -+#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -+#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -+#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -+#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -+#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -+#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+VPORT - Virtual Ports -+-------------------------------------------------------------------------- -+*/ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t USBCTRL; /* USB Control Register */ -+} CLK_t; -+ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t PRPB; /* Power Reduction Port B */ -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t PRPD; /* Power Reduction Port D */ -+ register8_t PRPE; /* Power Reduction Port E */ -+ register8_t PRPF; /* Power Reduction Port F */ -+} PR_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+/* USB Prescaler Division Factor */ -+typedef enum CLK_USBPSDIV_enum -+{ -+ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ -+ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ -+ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ -+ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ -+ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ -+ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -+} CLK_USBPSDIV_t; -+ -+/* USB Clock Source */ -+typedef enum CLK_USBSRC_enum -+{ -+ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ -+ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -+} CLK_USBSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control Register */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+/* 2 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC2MCREF_enum -+{ -+ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC2MCREF_t; -+ -+/* 32 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC32MCREF_enum -+{ -+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -+} OSC_RC32MCREF_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t JTAGUID; /* JTAG User ID */ -+ register8_t reserved_0x05; -+ register8_t MCUCR; /* MCU Control */ -+ register8_t ANAINIT; /* Analog Startup Delay */ -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t AWEXLOCK; /* AWEX Lock */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORTCFG - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t VPCTRLA; /* Virtual Port Control Register A */ -+ register8_t VPCTRLB; /* Virtual Port Control Register B */ -+ register8_t CLKEVOUT; /* Clock and Event Out Register */ -+ register8_t EBIOUT; /* EBI Output register */ -+ register8_t EVOUTSEL; /* Event Output Select */ -+} PORTCFG_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP02MAP_enum -+{ -+ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ -+ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ -+ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ -+ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ -+ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ -+ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ -+ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ -+ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ -+ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ -+ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ -+ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ -+ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ -+ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ -+ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ -+ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ -+ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -+} PORTCFG_VP02MAP_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP13MAP_enum -+{ -+ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ -+ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ -+ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ -+ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ -+ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ -+ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ -+ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ -+ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ -+ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ -+ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ -+ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ -+ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ -+ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ -+ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ -+ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ -+ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -+} PORTCFG_VP13MAP_t; -+ -+/* System Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ -+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ -+ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -+} PORTCFG_CLKOUT_t; -+ -+/* Peripheral Clock Output Select */ -+typedef enum PORTCFG_CLKOUTSEL_enum -+{ -+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -+} PORTCFG_CLKOUTSEL_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ -+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ -+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -+} PORTCFG_EVOUT_t; -+ -+/* Clock and Event Output Port */ -+typedef enum PORTCFG_CLKEVPIN_enum -+{ -+ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ -+ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -+} PORTCFG_CLKEVPIN_t; -+ -+/* EBI Address Output Port */ -+typedef enum PORTCFG_EBIADROUT_enum -+{ -+ PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ -+ PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ -+ PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ -+ PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ -+} PORTCFG_EBIADROUT_t; -+ -+/* EBI Chip Select Output Port */ -+typedef enum PORTCFG_EBICSOUT_enum -+{ -+ PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ -+} PORTCFG_EBICSOUT_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -+ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ -+ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ -+ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ -+ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AES - AES Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* AES Module */ -+typedef struct AES_struct -+{ -+ register8_t CTRL; /* AES Control Register */ -+ register8_t STATUS; /* AES Status Register */ -+ register8_t STATE; /* AES State Register */ -+ register8_t KEY; /* AES Key Register */ -+ register8_t INTCTRL; /* AES Interrupt Control Register */ -+} AES_t; -+ -+/* Interrupt level */ -+typedef enum AES_INTLVL_enum -+{ -+ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} AES_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ -+ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ -+ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ -+ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DMA - DMA Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* DMA Channel */ -+typedef struct DMA_CH_struct -+{ -+ register8_t CTRLA; /* Channel Control */ -+ register8_t CTRLB; /* Channel Control */ -+ register8_t ADDRCTRL; /* Address Control */ -+ register8_t TRIGSRC; /* Channel Trigger Source */ -+ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ -+ register8_t REPCNT; /* Channel Repeat Count */ -+ register8_t reserved_0x07; -+ register8_t SRCADDR0; /* Channel Source Address 0 */ -+ register8_t SRCADDR1; /* Channel Source Address 1 */ -+ register8_t SRCADDR2; /* Channel Source Address 2 */ -+ register8_t reserved_0x0B; -+ register8_t DESTADDR0; /* Channel Destination Address 0 */ -+ register8_t DESTADDR1; /* Channel Destination Address 1 */ -+ register8_t DESTADDR2; /* Channel Destination Address 2 */ -+ register8_t reserved_0x0F; -+} DMA_CH_t; -+ -+ -+/* DMA Controller */ -+typedef struct DMA_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t reserved_0x01; -+ register8_t reserved_0x02; -+ register8_t INTFLAGS; /* Transfer Interrupt Status */ -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x05; -+ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ DMA_CH_t CH0; /* DMA Channel 0 */ -+ DMA_CH_t CH1; /* DMA Channel 1 */ -+ DMA_CH_t CH2; /* DMA Channel 2 */ -+ DMA_CH_t CH3; /* DMA Channel 3 */ -+} DMA_t; -+ -+/* Burst mode */ -+typedef enum DMA_CH_BURSTLEN_enum -+{ -+ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ -+ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ -+ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ -+ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -+} DMA_CH_BURSTLEN_t; -+ -+/* Source address reload mode */ -+typedef enum DMA_CH_SRCRELOAD_enum -+{ -+ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ -+ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ -+ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ -+ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -+} DMA_CH_SRCRELOAD_t; -+ -+/* Source addressing mode */ -+typedef enum DMA_CH_SRCDIR_enum -+{ -+ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ -+ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ -+ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -+} DMA_CH_SRCDIR_t; -+ -+/* Destination adress reload mode */ -+typedef enum DMA_CH_DESTRELOAD_enum -+{ -+ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ -+ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ -+ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ -+ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -+} DMA_CH_DESTRELOAD_t; -+ -+/* Destination adressing mode */ -+typedef enum DMA_CH_DESTDIR_enum -+{ -+ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ -+ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ -+ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -+} DMA_CH_DESTDIR_t; -+ -+/* Transfer trigger source */ -+typedef enum DMA_CH_TRIGSRC_enum -+{ -+ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ -+ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ -+ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ -+ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ -+ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ -+ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ -+ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ -+ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ -+ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ -+ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ -+ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ -+ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ -+ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ -+ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ -+ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ -+ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ -+ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ -+ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ -+ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ -+ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ -+ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ -+ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ -+ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ -+ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ -+ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ -+ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ -+ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ -+ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ -+ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ -+ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ -+ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ -+ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ -+ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ -+ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ -+ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -+} DMA_CH_TRIGSRC_t; -+ -+/* Double buffering mode */ -+typedef enum DMA_DBUFMODE_enum -+{ -+ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ -+ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ -+ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ -+ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -+} DMA_DBUFMODE_t; -+ -+/* Priority mode */ -+typedef enum DMA_PRIMODE_enum -+{ -+ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ -+ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ -+ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ -+ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -+} DMA_PRIMODE_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_ERRINTLVL_enum -+{ -+ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ -+ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ -+ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -+} DMA_CH_ERRINTLVL_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_TRNINTLVL_enum -+{ -+ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ -+ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -+} DMA_CH_TRNINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ -+ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ -+ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ -+ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t CH4CTRL; /* Channel 4 Control Register */ -+ register8_t CH5CTRL; /* Channel 5 Control Register */ -+ register8_t CH6CTRL; /* Channel 6 Control Register */ -+ register8_t CH7CTRL; /* Channel 7 Control Register */ -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+} EVSYS_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ -+ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ -+ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ -+ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ -+ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ -+ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ -+ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ -+ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ -+ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ -+ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ -+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ -+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ -+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ -+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ -+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ -+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ -+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ -+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ -+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ -+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ -+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ -+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ -+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ -+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ -+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ -+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ -+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ -+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ -+ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ -+ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ -+ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ -+ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ -+ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ -+ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ -+ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ -+ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ -+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ -+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ -+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ -+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ -+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ -+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ -+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ -+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ -+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ -+ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ -+ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ -+ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ -+ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ -+ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ -+ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ -+ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ -+ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ -+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ -+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ -+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ -+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -+ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ -+ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ -+ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ -+ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ -+ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ -+ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ -+ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ -+ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -+ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ -+ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ -+ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ -+ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -+} EVSYS_CHMUX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ -+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ -+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ -+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ -+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} NVM_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t reserved_0x07; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ _WORDREGISTER(CH1RES); /* Channel 1 Result */ -+ _WORDREGISTER(CH2RES); /* Channel 2 Result */ -+ _WORDREGISTER(CH3RES); /* Channel 3 Result */ -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+ ADC_CH_t CH1; /* ADC Channel 1 */ -+ ADC_CH_t CH2; /* ADC Channel 2 */ -+ ADC_CH_t CH3; /* ADC Channel 3 */ -+} ADC_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -+ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+ ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 3) */ -+ ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Groud (Input Mode = 3) */ -+ ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Groud (Input Mode = 4) */ -+ ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 4) */ -+} ADC_CH_MUXNEG_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Current Limitation Mode */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ -+} ADC_CURRLIMIT_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Channel sweep selection */ -+typedef enum ADC_SWEEP_enum -+{ -+ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ -+ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ -+ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ -+ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -+} ADC_SWEEP_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ -+ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ -+ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ -+ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ -+ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ -+ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ -+ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ -+ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -+ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ -+ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ -+ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ -+ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* DMA request selection */ -+typedef enum ADC_DMASEL_enum -+{ -+ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ -+ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ -+ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ -+ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -+} ADC_DMASEL_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DAC - Digital/Analog Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Digital-to-Analog Converter */ -+typedef struct DAC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t EVCTRL; /* Event Input Control */ -+ register8_t reserved_0x04; -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0GAINCAL; /* Gain Calibration */ -+ register8_t CH0OFFSETCAL; /* Offset Calibration */ -+ register8_t CH1GAINCAL; /* Gain Calibration */ -+ register8_t CH1OFFSETCAL; /* Offset Calibration */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ -+ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -+} DAC_t; -+ -+/* Output channel selection */ -+typedef enum DAC_CHSEL_enum -+{ -+ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ -+ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ -+ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -+} DAC_CHSEL_t; -+ -+/* Reference voltage selection */ -+typedef enum DAC_REFSEL_enum -+{ -+ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ -+ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ -+ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ -+ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -+} DAC_REFSEL_t; -+ -+/* Event channel selection */ -+typedef enum DAC_EVSEL_enum -+{ -+ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ -+ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ -+ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ -+ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ -+ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ -+ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ -+ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ -+ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -+} DAC_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC - Real-Time Counter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Real-Time Counter */ -+typedef struct RTC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary register */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ _WORDREGISTER(CNT); /* Count Register */ -+ _WORDREGISTER(PER); /* Period Register */ -+ _WORDREGISTER(COMP); /* Compare Register */ -+} RTC_t; -+ -+/* Prescaler Factor */ -+typedef enum RTC_PRESCALER_enum -+{ -+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ -+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ -+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ -+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ -+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ -+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ -+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ -+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -+} RTC_PRESCALER_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC_COMPINTLVL_enum -+{ -+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC_OVFINTLVL_enum -+{ -+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+} TWI_t; -+ -+/* SDA Hold Time */ -+typedef enum TWI_SDAHOLD_enum -+{ -+ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ -+ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ -+ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ -+ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -+} TWI_SDAHOLD_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USB - USB -+-------------------------------------------------------------------------- -+*/ -+ -+/* USB Endpoint */ -+typedef struct USB_EP_struct -+{ -+ register8_t STATUS; /* Endpoint Status */ -+ register8_t CTRL; /* Endpoint Control */ -+ _WORDREGISTER(CNT); /* USB Endpoint Counter */ -+ _WORDREGISTER(DATAPTR); /* Data Pointer */ -+ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -+} USB_EP_t; -+ -+ -+/* Universal Serial Bus */ -+typedef struct USB_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t FIFOWP; /* FIFO Write Pointer Register */ -+ register8_t FIFORP; /* FIFO Read Pointer Register */ -+ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ -+ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ -+ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ -+ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t reserved_0x20; -+ register8_t reserved_0x21; -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t CAL0; /* Calibration Byte 0 */ -+ register8_t CAL1; /* Calibration Byte 1 */ -+} USB_t; -+ -+ -+/* USB Endpoint Table */ -+typedef struct USB_EP_TABLE_struct -+{ -+ USB_EP_t EP0OUT; /* Endpoint 0 */ -+ USB_EP_t EP0IN; /* Endpoint 0 */ -+ USB_EP_t EP1OUT; /* Endpoint 1 */ -+ USB_EP_t EP1IN; /* Endpoint 1 */ -+ USB_EP_t EP2OUT; /* Endpoint 2 */ -+ USB_EP_t EP2IN; /* Endpoint 2 */ -+ USB_EP_t EP3OUT; /* Endpoint 3 */ -+ USB_EP_t EP3IN; /* Endpoint 3 */ -+ USB_EP_t EP4OUT; /* Endpoint 4 */ -+ USB_EP_t EP4IN; /* Endpoint 4 */ -+ USB_EP_t EP5OUT; /* Endpoint 5 */ -+ USB_EP_t EP5IN; /* Endpoint 5 */ -+ USB_EP_t EP6OUT; /* Endpoint 6 */ -+ USB_EP_t EP6IN; /* Endpoint 6 */ -+ USB_EP_t EP7OUT; /* Endpoint 7 */ -+ USB_EP_t EP7IN; /* Endpoint 7 */ -+ USB_EP_t EP8OUT; /* Endpoint 8 */ -+ USB_EP_t EP8IN; /* Endpoint 8 */ -+ USB_EP_t EP9OUT; /* Endpoint 9 */ -+ USB_EP_t EP9IN; /* Endpoint 9 */ -+ USB_EP_t EP10OUT; /* Endpoint 10 */ -+ USB_EP_t EP10IN; /* Endpoint 10 */ -+ USB_EP_t EP11OUT; /* Endpoint 11 */ -+ USB_EP_t EP11IN; /* Endpoint 11 */ -+ USB_EP_t EP12OUT; /* Endpoint 12 */ -+ USB_EP_t EP12IN; /* Endpoint 12 */ -+ USB_EP_t EP13OUT; /* Endpoint 13 */ -+ USB_EP_t EP13IN; /* Endpoint 13 */ -+ USB_EP_t EP14OUT; /* Endpoint 14 */ -+ USB_EP_t EP14IN; /* Endpoint 14 */ -+ USB_EP_t EP15OUT; /* Endpoint 15 */ -+ USB_EP_t EP15IN; /* Endpoint 15 */ -+ register8_t reserved_0x100; -+ register8_t reserved_0x101; -+ register8_t reserved_0x102; -+ register8_t reserved_0x103; -+ register8_t reserved_0x104; -+ register8_t reserved_0x105; -+ register8_t reserved_0x106; -+ register8_t reserved_0x107; -+ register8_t reserved_0x108; -+ register8_t reserved_0x109; -+ register8_t reserved_0x10A; -+ register8_t reserved_0x10B; -+ register8_t reserved_0x10C; -+ register8_t reserved_0x10D; -+ register8_t reserved_0x10E; -+ register8_t reserved_0x10F; -+ register8_t FRAMENUML; /* Frame Number Low Byte */ -+ register8_t FRAMENUMH; /* Frame Number High Byte */ -+} USB_EP_TABLE_t; -+ -+/* Interrupt level */ -+typedef enum USB_INTLVL_enum -+{ -+ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} USB_INTLVL_t; -+ -+/* USB Endpoint Type */ -+typedef enum USB_EP_TYPE_enum -+{ -+ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ -+ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ -+ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ -+ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -+} USB_EP_TYPE_t; -+ -+/* USB Endpoint Buffersize */ -+typedef enum USB_EP_BUFSIZE_enum -+{ -+ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ -+ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ -+ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ -+ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ -+ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ -+ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ -+ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ -+ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -+} USB_EP_BUFSIZE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - I/O Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INT0MASK; /* Port Interrupt 0 Mask */ -+ register8_t INT1MASK; /* Port Interrupt 1 Mask */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t REMAP; /* I/O Port Pin Remap Register */ -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Port Interrupt 0 Level */ -+typedef enum PORT_INT0LVL_enum -+{ -+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INT0LVL_t; -+ -+/* Port Interrupt 1 Level */ -+typedef enum PORT_INT1LVL_enum -+{ -+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ -+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ -+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -+} PORT_INT1LVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 0 */ -+typedef struct TC0_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC0_t; -+ -+ -+/* 16-bit Timer/Counter 1 */ -+typedef struct TC1_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+} TC1_t; -+ -+/* Clock Selection */ -+typedef enum TC_CLKSEL_enum -+{ -+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC_CLKSEL_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC_WGMODE_enum -+{ -+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC_WGMODE_t; -+ -+/* Byte Mode */ -+typedef enum TC_BYTEM_enum -+{ -+ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ -+ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -+} TC_BYTEM_t; -+ -+/* Event Action */ -+typedef enum TC_EVACT_enum -+{ -+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ -+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ -+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ -+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ -+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ -+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC_EVSEL_enum -+{ -+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC_EVSEL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC_ERRINTLVL_enum -+{ -+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC_OVFINTLVL_enum -+{ -+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_OVFINTLVL_t; -+ -+/* Compare or Capture D Interrupt Level */ -+typedef enum TC_CCDINTLVL_enum -+{ -+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC_CCDINTLVL_t; -+ -+/* Compare or Capture C Interrupt Level */ -+typedef enum TC_CCCINTLVL_enum -+{ -+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC_CCCINTLVL_t; -+ -+/* Compare or Capture B Interrupt Level */ -+typedef enum TC_CCBINTLVL_enum -+{ -+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_CCBINTLVL_t; -+ -+/* Compare or Capture A Interrupt Level */ -+typedef enum TC_CCAINTLVL_enum -+{ -+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_CCAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC_CMD_enum -+{ -+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC2 - 16-bit Timer/Counter type 2 -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter type 2 */ -+typedef struct TC2_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t reserved_0x03; -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t reserved_0x08; -+ register8_t CTRLF; /* Control Register F */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t LCNT; /* Low Byte Count */ -+ register8_t HCNT; /* High Byte Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t LPER; /* Low Byte Period */ -+ register8_t HPER; /* High Byte Period */ -+ register8_t LCMPA; /* Low Byte Compare A */ -+ register8_t HCMPA; /* High Byte Compare A */ -+ register8_t LCMPB; /* Low Byte Compare B */ -+ register8_t HCMPB; /* High Byte Compare B */ -+ register8_t LCMPC; /* Low Byte Compare C */ -+ register8_t HCMPC; /* High Byte Compare C */ -+ register8_t LCMPD; /* Low Byte Compare D */ -+ register8_t HCMPD; /* High Byte Compare D */ -+} TC2_t; -+ -+/* Clock Selection */ -+typedef enum TC2_CLKSEL_enum -+{ -+ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC2_CLKSEL_t; -+ -+/* Byte Mode */ -+typedef enum TC2_BYTEM_enum -+{ -+ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ -+ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -+} TC2_BYTEM_t; -+ -+/* High Byte Underflow Interrupt Level */ -+typedef enum TC2_HUNFINTLVL_enum -+{ -+ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_HUNFINTLVL_t; -+ -+/* Low Byte Underflow Interrupt Level */ -+typedef enum TC2_LUNFINTLVL_enum -+{ -+ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LUNFINTLVL_t; -+ -+/* Low Byte Compare D Interrupt Level */ -+typedef enum TC2_LCMPDINTLVL_enum -+{ -+ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC2_LCMPDINTLVL_t; -+ -+/* Low Byte Compare C Interrupt Level */ -+typedef enum TC2_LCMPCINTLVL_enum -+{ -+ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC2_LCMPCINTLVL_t; -+ -+/* Low Byte Compare B Interrupt Level */ -+typedef enum TC2_LCMPBINTLVL_enum -+{ -+ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_LCMPBINTLVL_t; -+ -+/* Low Byte Compare A Interrupt Level */ -+typedef enum TC2_LCMPAINTLVL_enum -+{ -+ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LCMPAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMD_enum -+{ -+ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC2_CMD_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMDEN_enum -+{ -+ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ -+ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ -+ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -+} TC2_CMDEN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AWEX - Timer/Counter Advanced Waveform Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Advanced Waveform Extension */ -+typedef struct AWEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t FDEMASK; /* Fault Detection Event Mask */ -+ register8_t FDCTRL; /* Fault Detection Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t STATUSSET; /* Status Set Register */ -+ register8_t DTBOTH; /* Dead Time Both Sides */ -+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ -+ register8_t DTLS; /* Dead Time Low Side */ -+ register8_t DTHS; /* Dead Time High Side */ -+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ -+ register8_t DTHSBUF; /* Dead Time High Side Buffer */ -+ register8_t OUTOVEN; /* Output Override Enable */ -+} AWEX_t; -+ -+/* Fault Detect Action */ -+typedef enum AWEX_FDACT_enum -+{ -+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ -+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -+} AWEX_FDACT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+HIRES - Timer/Counter High-Resolution Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register */ -+} HIRES_t; -+ -+/* High Resolution Enable */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ -+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ -+ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ -+ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ -+ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -+} IRDA_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t reserved_0x00; -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+} NVM_FUSES_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* Timer Oscillator pin location */ -+typedef enum TOSCSEL_enum -+{ -+ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ -+ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -+} TOSCSEL_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -+} BOD_t; -+ -+/* BOD operation */ -+typedef enum BODACT_enum -+{ -+ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BODACT_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WDP_enum -+{ -+ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ -+ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ -+ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ -+ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ -+ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ -+ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ -+ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ -+ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ -+ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ -+ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ -+ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -+} WDP_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LOCKBIT - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ -+ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t USBCAL0; /* USB Calibration Byte 0 */ -+ register8_t USBCAL1; /* USB Calibration Byte 1 */ -+ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ -+ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ -+ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ -+ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ -+ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ -+ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ -+ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ -+ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ -+ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ -+ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+ register8_t reserved_0x40; -+ register8_t reserved_0x41; -+ register8_t reserved_0x42; -+ register8_t reserved_0x43; -+ register8_t reserved_0x44; -+ register8_t reserved_0x45; -+ register8_t reserved_0x46; -+ register8_t reserved_0x47; -+} NVM_PROD_SIGNATURES_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define AES (*(AES_t *) 0x00C0) /* AES Module */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -+#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -+#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -+#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -+#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -+#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ -+#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ -+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -+#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -+#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ -+#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -+#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -+#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -+#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -+#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -+#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -+#define GPIO_GPIORA _SFR_MEM8(0x000A) -+#define GPIO_GPIORB _SFR_MEM8(0x000B) -+#define GPIO_GPIORC _SFR_MEM8(0x000C) -+#define GPIO_GPIORD _SFR_MEM8(0x000D) -+#define GPIO_GPIORE _SFR_MEM8(0x000E) -+#define GPIO_GPIORF _SFR_MEM8(0x000F) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+#define GPIO_GPIO4 _SFR_MEM8(0x0004) -+#define GPIO_GPIO5 _SFR_MEM8(0x0005) -+#define GPIO_GPIO6 _SFR_MEM8(0x0006) -+#define GPIO_GPIO7 _SFR_MEM8(0x0007) -+#define GPIO_GPIO8 _SFR_MEM8(0x0008) -+#define GPIO_GPIO9 _SFR_MEM8(0x0009) -+#define GPIO_GPIOA _SFR_MEM8(0x000A) -+#define GPIO_GPIOB _SFR_MEM8(0x000B) -+#define GPIO_GPIOC _SFR_MEM8(0x000C) -+#define GPIO_GPIOD _SFR_MEM8(0x000D) -+#define GPIO_GPIOE _SFR_MEM8(0x000E) -+#define GPIO_GPIOF _SFR_MEM8(0x000F) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -+#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -+#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -+#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -+#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -+#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -+#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) -+#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) -+#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -+#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) -+#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) -+#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+#define CLK_USBCTRL _SFR_MEM8(0x0044) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* DFLL - DFLL */ -+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -+#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -+#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPB _SFR_MEM8(0x0072) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPD _SFR_MEM8(0x0074) -+#define PR_PRPE _SFR_MEM8(0x0075) -+#define PR_PRPF _SFR_MEM8(0x0076) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_JTAGUID _SFR_MEM8(0x0094) -+#define MCU_MCUCR _SFR_MEM8(0x0096) -+#define MCU_ANAINIT _SFR_MEM8(0x0097) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_AWEXLOCK _SFR_MEM8(0x0099) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) -+#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) -+ -+/* AES - AES Module */ -+#define AES_CTRL _SFR_MEM8(0x00C0) -+#define AES_STATUS _SFR_MEM8(0x00C1) -+#define AES_STATE _SFR_MEM8(0x00C2) -+#define AES_KEY _SFR_MEM8(0x00C3) -+#define AES_INTCTRL _SFR_MEM8(0x00C4) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* DMA - DMA Controller */ -+#define DMA_CTRL _SFR_MEM8(0x0100) -+#define DMA_INTFLAGS _SFR_MEM8(0x0103) -+#define DMA_STATUS _SFR_MEM8(0x0104) -+#define DMA_TEMP _SFR_MEM16(0x0106) -+#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -+#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -+#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -+#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -+#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -+#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -+#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -+#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -+#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -+#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -+#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -+#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -+#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -+#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -+#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -+#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -+#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -+#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -+#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -+#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -+#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -+#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -+#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -+#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -+#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -+#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -+#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -+#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -+#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -+#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -+#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -+#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -+#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -+#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -+#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -+#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -+#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -+#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -+#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -+#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -+#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -+#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -+#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -+#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -+#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -+#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -+#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -+#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -+#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -+#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -+#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -+#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -+#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -+#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCA_CTRLA _SFR_MEM8(0x0200) -+#define ADCA_CTRLB _SFR_MEM8(0x0201) -+#define ADCA_REFCTRL _SFR_MEM8(0x0202) -+#define ADCA_EVCTRL _SFR_MEM8(0x0203) -+#define ADCA_PRESCALER _SFR_MEM8(0x0204) -+#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -+#define ADCA_TEMP _SFR_MEM8(0x0207) -+#define ADCA_CAL _SFR_MEM16(0x020C) -+#define ADCA_CH0RES _SFR_MEM16(0x0210) -+#define ADCA_CH1RES _SFR_MEM16(0x0212) -+#define ADCA_CH2RES _SFR_MEM16(0x0214) -+#define ADCA_CH3RES _SFR_MEM16(0x0216) -+#define ADCA_CMP _SFR_MEM16(0x0218) -+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -+#define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -+#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -+#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -+#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -+#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -+#define ADCA_CH1_RES _SFR_MEM16(0x022C) -+#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) -+#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -+#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -+#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -+#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -+#define ADCA_CH2_RES _SFR_MEM16(0x0234) -+#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) -+#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -+#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -+#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -+#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -+#define ADCA_CH3_RES _SFR_MEM16(0x023C) -+#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) -+ -+/* DAC - Digital-to-Analog Converter */ -+#define DACB_CTRLA _SFR_MEM8(0x0320) -+#define DACB_CTRLB _SFR_MEM8(0x0321) -+#define DACB_CTRLC _SFR_MEM8(0x0322) -+#define DACB_EVCTRL _SFR_MEM8(0x0323) -+#define DACB_STATUS _SFR_MEM8(0x0325) -+#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) -+#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) -+#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) -+#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) -+#define DACB_CH0DATA _SFR_MEM16(0x0338) -+#define DACB_CH1DATA _SFR_MEM16(0x033A) -+ -+/* AC - Analog Comparator */ -+#define ACA_AC0CTRL _SFR_MEM8(0x0380) -+#define ACA_AC1CTRL _SFR_MEM8(0x0381) -+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -+#define ACA_CTRLA _SFR_MEM8(0x0384) -+#define ACA_CTRLB _SFR_MEM8(0x0385) -+#define ACA_WINCTRL _SFR_MEM8(0x0386) -+#define ACA_STATUS _SFR_MEM8(0x0387) -+ -+/* RTC - Real-Time Counter */ -+#define RTC_CTRL _SFR_MEM8(0x0400) -+#define RTC_STATUS _SFR_MEM8(0x0401) -+#define RTC_INTCTRL _SFR_MEM8(0x0402) -+#define RTC_INTFLAGS _SFR_MEM8(0x0403) -+#define RTC_TEMP _SFR_MEM8(0x0404) -+#define RTC_CNT _SFR_MEM16(0x0408) -+#define RTC_PER _SFR_MEM16(0x040A) -+#define RTC_COMP _SFR_MEM16(0x040C) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIE_CTRL _SFR_MEM8(0x04A0) -+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -+ -+/* USB - Universal Serial Bus */ -+#define USB_CTRLA _SFR_MEM8(0x04C0) -+#define USB_CTRLB _SFR_MEM8(0x04C1) -+#define USB_STATUS _SFR_MEM8(0x04C2) -+#define USB_ADDR _SFR_MEM8(0x04C3) -+#define USB_FIFOWP _SFR_MEM8(0x04C4) -+#define USB_FIFORP _SFR_MEM8(0x04C5) -+#define USB_EPPTR _SFR_MEM16(0x04C6) -+#define USB_INTCTRLA _SFR_MEM8(0x04C8) -+#define USB_INTCTRLB _SFR_MEM8(0x04C9) -+#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -+#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -+#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -+#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -+#define USB_CAL0 _SFR_MEM8(0x04FA) -+#define USB_CAL1 _SFR_MEM8(0x04FB) -+ -+/* PORT - I/O Ports */ -+#define PORTA_DIR _SFR_MEM8(0x0600) -+#define PORTA_DIRSET _SFR_MEM8(0x0601) -+#define PORTA_DIRCLR _SFR_MEM8(0x0602) -+#define PORTA_DIRTGL _SFR_MEM8(0x0603) -+#define PORTA_OUT _SFR_MEM8(0x0604) -+#define PORTA_OUTSET _SFR_MEM8(0x0605) -+#define PORTA_OUTCLR _SFR_MEM8(0x0606) -+#define PORTA_OUTTGL _SFR_MEM8(0x0607) -+#define PORTA_IN _SFR_MEM8(0x0608) -+#define PORTA_INTCTRL _SFR_MEM8(0x0609) -+#define PORTA_INT0MASK _SFR_MEM8(0x060A) -+#define PORTA_INT1MASK _SFR_MEM8(0x060B) -+#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_REMAP _SFR_MEM8(0x060E) -+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -+ -+/* PORT - I/O Ports */ -+#define PORTB_DIR _SFR_MEM8(0x0620) -+#define PORTB_DIRSET _SFR_MEM8(0x0621) -+#define PORTB_DIRCLR _SFR_MEM8(0x0622) -+#define PORTB_DIRTGL _SFR_MEM8(0x0623) -+#define PORTB_OUT _SFR_MEM8(0x0624) -+#define PORTB_OUTSET _SFR_MEM8(0x0625) -+#define PORTB_OUTCLR _SFR_MEM8(0x0626) -+#define PORTB_OUTTGL _SFR_MEM8(0x0627) -+#define PORTB_IN _SFR_MEM8(0x0628) -+#define PORTB_INTCTRL _SFR_MEM8(0x0629) -+#define PORTB_INT0MASK _SFR_MEM8(0x062A) -+#define PORTB_INT1MASK _SFR_MEM8(0x062B) -+#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -+#define PORTB_REMAP _SFR_MEM8(0x062E) -+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INT0MASK _SFR_MEM8(0x064A) -+#define PORTC_INT1MASK _SFR_MEM8(0x064B) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INT0MASK _SFR_MEM8(0x066A) -+#define PORTD_INT1MASK _SFR_MEM8(0x066B) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTE_DIR _SFR_MEM8(0x0680) -+#define PORTE_DIRSET _SFR_MEM8(0x0681) -+#define PORTE_DIRCLR _SFR_MEM8(0x0682) -+#define PORTE_DIRTGL _SFR_MEM8(0x0683) -+#define PORTE_OUT _SFR_MEM8(0x0684) -+#define PORTE_OUTSET _SFR_MEM8(0x0685) -+#define PORTE_OUTCLR _SFR_MEM8(0x0686) -+#define PORTE_OUTTGL _SFR_MEM8(0x0687) -+#define PORTE_IN _SFR_MEM8(0x0688) -+#define PORTE_INTCTRL _SFR_MEM8(0x0689) -+#define PORTE_INT0MASK _SFR_MEM8(0x068A) -+#define PORTE_INT1MASK _SFR_MEM8(0x068B) -+#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -+#define PORTE_REMAP _SFR_MEM8(0x068E) -+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -+#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCC0_CTRLA _SFR_MEM8(0x0800) -+#define TCC0_CTRLB _SFR_MEM8(0x0801) -+#define TCC0_CTRLC _SFR_MEM8(0x0802) -+#define TCC0_CTRLD _SFR_MEM8(0x0803) -+#define TCC0_CTRLE _SFR_MEM8(0x0804) -+#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -+#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -+#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -+#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC0_TEMP _SFR_MEM8(0x080F) -+#define TCC0_CNT _SFR_MEM16(0x0820) -+#define TCC0_PER _SFR_MEM16(0x0826) -+#define TCC0_CCA _SFR_MEM16(0x0828) -+#define TCC0_CCB _SFR_MEM16(0x082A) -+#define TCC0_CCC _SFR_MEM16(0x082C) -+#define TCC0_CCD _SFR_MEM16(0x082E) -+#define TCC0_PERBUF _SFR_MEM16(0x0836) -+#define TCC0_CCABUF _SFR_MEM16(0x0838) -+#define TCC0_CCBBUF _SFR_MEM16(0x083A) -+#define TCC0_CCCBUF _SFR_MEM16(0x083C) -+#define TCC0_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCC2_CTRLA _SFR_MEM8(0x0800) -+#define TCC2_CTRLB _SFR_MEM8(0x0801) -+#define TCC2_CTRLC _SFR_MEM8(0x0802) -+#define TCC2_CTRLE _SFR_MEM8(0x0804) -+#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC2_CTRLF _SFR_MEM8(0x0809) -+#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC2_LCNT _SFR_MEM8(0x0820) -+#define TCC2_HCNT _SFR_MEM8(0x0821) -+#define TCC2_LPER _SFR_MEM8(0x0826) -+#define TCC2_HPER _SFR_MEM8(0x0827) -+#define TCC2_LCMPA _SFR_MEM8(0x0828) -+#define TCC2_HCMPA _SFR_MEM8(0x0829) -+#define TCC2_LCMPB _SFR_MEM8(0x082A) -+#define TCC2_HCMPB _SFR_MEM8(0x082B) -+#define TCC2_LCMPC _SFR_MEM8(0x082C) -+#define TCC2_HCMPC _SFR_MEM8(0x082D) -+#define TCC2_LCMPD _SFR_MEM8(0x082E) -+#define TCC2_HCMPD _SFR_MEM8(0x082F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCC1_CTRLA _SFR_MEM8(0x0840) -+#define TCC1_CTRLB _SFR_MEM8(0x0841) -+#define TCC1_CTRLC _SFR_MEM8(0x0842) -+#define TCC1_CTRLD _SFR_MEM8(0x0843) -+#define TCC1_CTRLE _SFR_MEM8(0x0844) -+#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -+#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -+#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -+#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC1_TEMP _SFR_MEM8(0x084F) -+#define TCC1_CNT _SFR_MEM16(0x0860) -+#define TCC1_PER _SFR_MEM16(0x0866) -+#define TCC1_CCA _SFR_MEM16(0x0868) -+#define TCC1_CCB _SFR_MEM16(0x086A) -+#define TCC1_PERBUF _SFR_MEM16(0x0876) -+#define TCC1_CCABUF _SFR_MEM16(0x0878) -+#define TCC1_CCBBUF _SFR_MEM16(0x087A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXC_CTRL _SFR_MEM8(0x0880) -+#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -+#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -+#define AWEXC_STATUS _SFR_MEM8(0x0884) -+#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -+#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -+#define AWEXC_DTLS _SFR_MEM8(0x0888) -+#define AWEXC_DTHS _SFR_MEM8(0x0889) -+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x0890) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08A0) -+#define USARTC0_STATUS _SFR_MEM8(0x08A1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -+#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -+#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC1_DATA _SFR_MEM8(0x08B0) -+#define USARTC1_STATUS _SFR_MEM8(0x08B1) -+#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -+#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -+#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -+#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -+#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIC_CTRL _SFR_MEM8(0x08C0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -+#define SPIC_STATUS _SFR_MEM8(0x08C2) -+#define SPIC_DATA _SFR_MEM8(0x08C3) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCD0_CTRLA _SFR_MEM8(0x0900) -+#define TCD0_CTRLB _SFR_MEM8(0x0901) -+#define TCD0_CTRLC _SFR_MEM8(0x0902) -+#define TCD0_CTRLD _SFR_MEM8(0x0903) -+#define TCD0_CTRLE _SFR_MEM8(0x0904) -+#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -+#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -+#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -+#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -+#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD0_TEMP _SFR_MEM8(0x090F) -+#define TCD0_CNT _SFR_MEM16(0x0920) -+#define TCD0_PER _SFR_MEM16(0x0926) -+#define TCD0_CCA _SFR_MEM16(0x0928) -+#define TCD0_CCB _SFR_MEM16(0x092A) -+#define TCD0_CCC _SFR_MEM16(0x092C) -+#define TCD0_CCD _SFR_MEM16(0x092E) -+#define TCD0_PERBUF _SFR_MEM16(0x0936) -+#define TCD0_CCABUF _SFR_MEM16(0x0938) -+#define TCD0_CCBBUF _SFR_MEM16(0x093A) -+#define TCD0_CCCBUF _SFR_MEM16(0x093C) -+#define TCD0_CCDBUF _SFR_MEM16(0x093E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCD2_CTRLA _SFR_MEM8(0x0900) -+#define TCD2_CTRLB _SFR_MEM8(0x0901) -+#define TCD2_CTRLC _SFR_MEM8(0x0902) -+#define TCD2_CTRLE _SFR_MEM8(0x0904) -+#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD2_CTRLF _SFR_MEM8(0x0909) -+#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD2_LCNT _SFR_MEM8(0x0920) -+#define TCD2_HCNT _SFR_MEM8(0x0921) -+#define TCD2_LPER _SFR_MEM8(0x0926) -+#define TCD2_HPER _SFR_MEM8(0x0927) -+#define TCD2_LCMPA _SFR_MEM8(0x0928) -+#define TCD2_HCMPA _SFR_MEM8(0x0929) -+#define TCD2_LCMPB _SFR_MEM8(0x092A) -+#define TCD2_HCMPB _SFR_MEM8(0x092B) -+#define TCD2_LCMPC _SFR_MEM8(0x092C) -+#define TCD2_HCMPC _SFR_MEM8(0x092D) -+#define TCD2_LCMPD _SFR_MEM8(0x092E) -+#define TCD2_HCMPD _SFR_MEM8(0x092F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCD1_CTRLA _SFR_MEM8(0x0940) -+#define TCD1_CTRLB _SFR_MEM8(0x0941) -+#define TCD1_CTRLC _SFR_MEM8(0x0942) -+#define TCD1_CTRLD _SFR_MEM8(0x0943) -+#define TCD1_CTRLE _SFR_MEM8(0x0944) -+#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -+#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -+#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -+#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -+#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -+#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -+#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -+#define TCD1_TEMP _SFR_MEM8(0x094F) -+#define TCD1_CNT _SFR_MEM16(0x0960) -+#define TCD1_PER _SFR_MEM16(0x0966) -+#define TCD1_CCA _SFR_MEM16(0x0968) -+#define TCD1_CCB _SFR_MEM16(0x096A) -+#define TCD1_PERBUF _SFR_MEM16(0x0976) -+#define TCD1_CCABUF _SFR_MEM16(0x0978) -+#define TCD1_CCBBUF _SFR_MEM16(0x097A) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESD_CTRLA _SFR_MEM8(0x0990) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD0_DATA _SFR_MEM8(0x09A0) -+#define USARTD0_STATUS _SFR_MEM8(0x09A1) -+#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -+#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -+#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD1_DATA _SFR_MEM8(0x09B0) -+#define USARTD1_STATUS _SFR_MEM8(0x09B1) -+#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -+#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -+#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -+#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -+#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPID_CTRL _SFR_MEM8(0x09C0) -+#define SPID_INTCTRL _SFR_MEM8(0x09C1) -+#define SPID_STATUS _SFR_MEM8(0x09C2) -+#define SPID_DATA _SFR_MEM8(0x09C3) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCE0_CTRLA _SFR_MEM8(0x0A00) -+#define TCE0_CTRLB _SFR_MEM8(0x0A01) -+#define TCE0_CTRLC _SFR_MEM8(0x0A02) -+#define TCE0_CTRLD _SFR_MEM8(0x0A03) -+#define TCE0_CTRLE _SFR_MEM8(0x0A04) -+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE0_TEMP _SFR_MEM8(0x0A0F) -+#define TCE0_CNT _SFR_MEM16(0x0A20) -+#define TCE0_PER _SFR_MEM16(0x0A26) -+#define TCE0_CCA _SFR_MEM16(0x0A28) -+#define TCE0_CCB _SFR_MEM16(0x0A2A) -+#define TCE0_CCC _SFR_MEM16(0x0A2C) -+#define TCE0_CCD _SFR_MEM16(0x0A2E) -+#define TCE0_PERBUF _SFR_MEM16(0x0A36) -+#define TCE0_CCABUF _SFR_MEM16(0x0A38) -+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESE_CTRLA _SFR_MEM8(0x0A90) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE0_DATA _SFR_MEM8(0x0AA0) -+#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -+#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -+#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -+#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -+#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -+#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* VPORT - Virtual Ports */ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* CLK.USBCTRL bit masks and bit positions */ -+#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -+#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -+#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -+#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -+#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -+#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -+#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -+#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ -+ -+#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -+#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -+#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ -+ -+#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_USB_bm 0x40 /* USB bit mask. */ -+#define PR_USB_bp 6 /* USB bit position. */ -+ -+#define PR_AES_bm 0x10 /* AES bit mask. */ -+#define PR_AES_bp 4 /* AES bit position. */ -+ -+#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -+#define PR_EBI_bp 3 /* External Bus Interface bit position. */ -+ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -+#define PR_DMA_bp 0 /* DMA-Controller bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -+#define PR_DAC_bp 2 /* Port A DAC bit position. */ -+ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPB bit masks and bit positions */ -+/* PR_DAC Predefined. */ -+/* PR_DAC Predefined. */ -+ -+/* PR_ADC Predefined. */ -+/* PR_ADC Predefined. */ -+ -+/* PR_AC Predefined. */ -+/* PR_AC Predefined. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -+#define PR_USART1_bp 5 /* Port C USART1 bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -+#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ -+ -+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -+ -+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ -+ -+/* PR.PRPD bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPE bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPF bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -+#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -+#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ -+ -+#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ -+ -+#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -+#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.MCUCR bit masks and bit positions */ -+#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -+#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ -+ -+/* MCU.ANAINIT bit masks and bit positions */ -+#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -+#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -+#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -+#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -+#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -+#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ -+ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -+#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ -+ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.AWEXLOCK bit masks and bit positions */ -+#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ -+#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ -+ -+#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -+#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ -+ -+#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ -+#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ -+ -+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* PORTCFG - Port Configuration */ -+/* PORTCFG.VPCTRLA bit masks and bit positions */ -+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ -+ -+/* PORTCFG.VPCTRLB bit masks and bit positions */ -+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ -+ -+/* PORTCFG.CLKEVOUT bit masks and bit positions */ -+#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ -+ -+#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -+#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -+#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -+#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -+#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -+#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ -+ -+#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -+#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ -+ -+#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -+#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ -+ -+/* PORTCFG.EBIOUT bit masks and bit positions */ -+#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ -+#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ -+#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ -+#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ -+#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ -+#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ -+ -+#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ -+#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ -+#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ -+#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ -+#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ -+#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ -+ -+/* PORTCFG.EVOUTSEL bit masks and bit positions */ -+#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -+#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -+#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -+#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -+#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -+#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -+#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -+#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ -+ -+/* AES - AES Module */ -+/* AES.CTRL bit masks and bit positions */ -+#define AES_START_bm 0x80 /* Start/Run bit mask. */ -+#define AES_START_bp 7 /* Start/Run bit position. */ -+ -+#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -+#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ -+ -+#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -+#define AES_RESET_bp 5 /* AES Software Reset bit position. */ -+ -+#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -+#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ -+ -+#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -+#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ -+ -+/* AES.STATUS bit masks and bit positions */ -+#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -+#define AES_ERROR_bp 7 /* AES Error bit position. */ -+ -+#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -+#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ -+ -+/* AES.INTCTRL bit masks and bit positions */ -+#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -+#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* DMA - DMA Controller */ -+/* DMA_CH.CTRLA bit masks and bit positions */ -+#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -+#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ -+ -+#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -+#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ -+ -+#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -+#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ -+ -+#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -+#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ -+ -+#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -+#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ -+ -+#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -+#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -+#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -+#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -+#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -+#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ -+ -+/* DMA_CH.CTRLB bit masks and bit positions */ -+#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -+#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ -+ -+#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -+#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ -+ -+#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -+#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ -+ -+#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -+#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -+#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -+#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -+#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -+#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ -+ -+#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -+#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -+#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -+#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -+#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -+#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ -+ -+/* DMA_CH.ADDRCTRL bit masks and bit positions */ -+#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -+#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -+#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -+#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -+#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -+#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ -+ -+#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -+#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -+#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -+#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -+#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -+#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ -+ -+#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -+#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -+#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -+#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -+#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -+#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ -+ -+#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -+#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -+#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -+#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -+#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -+#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ -+ -+/* DMA_CH.TRIGSRC bit masks and bit positions */ -+#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -+#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -+#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -+#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -+#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -+#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -+#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -+#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -+#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -+#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -+#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -+#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -+#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -+#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -+#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -+#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -+#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -+#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ -+ -+/* DMA.CTRL bit masks and bit positions */ -+#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -+#define DMA_ENABLE_bp 7 /* Enable bit position. */ -+ -+#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -+#define DMA_RESET_bp 6 /* Software Reset bit position. */ -+ -+#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -+#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -+#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -+#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -+#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -+#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ -+ -+#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -+#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -+#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -+#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -+#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -+#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ -+ -+/* DMA.INTFLAGS bit masks and bit positions */ -+#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ -+ -+/* DMA.STATUS bit masks and bit positions */ -+#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -+#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ -+ -+#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -+#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ -+ -+#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -+#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ -+ -+#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -+#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ -+ -+#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -+#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ -+ -+#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -+#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ -+ -+#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -+#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ -+ -+#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -+#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH4MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH5MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH6MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH7MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_QDIRM Predefined. */ -+/* EVSYS_QDIRM Predefined. */ -+ -+/* EVSYS_QDIEN Predefined. */ -+/* EVSYS_QDIEN Predefined. */ -+ -+/* EVSYS_QDEN Predefined. */ -+/* EVSYS_QDEN Predefined. */ -+ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH4CTRL bit masks and bit positions */ -+/* EVSYS_QDIRM Predefined. */ -+/* EVSYS_QDIRM Predefined. */ -+ -+/* EVSYS_QDIEN Predefined. */ -+/* EVSYS_QDIEN Predefined. */ -+ -+/* EVSYS_QDEN Predefined. */ -+/* EVSYS_QDEN Predefined. */ -+ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH5CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH6CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH7CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0x7F /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ -+ -+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ -+ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -+#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ -+#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -+#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -+#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -+#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -+#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -+#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -+#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -+#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -+#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -+#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ -+ -+#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -+#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -+#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -+#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -+#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -+#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -+#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -+#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -+#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -+#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -+#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -+#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -+#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -+#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -+#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ -+ -+#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -+#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ -+ -+#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -+#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ -+ -+#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -+#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ -+ -+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -+#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ -+#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ -+ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -+#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -+#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -+#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -+#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -+#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ -+ -+#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -+#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -+#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ -+ -+#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -+#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ -+ -+#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -+#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ -+ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* DAC - Digital/Analog Converter */ -+/* DAC.CTRLA bit masks and bit positions */ -+#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -+#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ -+ -+#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -+#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ -+ -+#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -+#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ -+ -+#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -+#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ -+ -+#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define DAC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* DAC.CTRLB bit masks and bit positions */ -+#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -+#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -+#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -+#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -+#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -+#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ -+ -+#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -+#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ -+ -+#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -+#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ -+ -+/* DAC.CTRLC bit masks and bit positions */ -+#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -+#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -+#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -+#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -+#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -+#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ -+ -+#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -+#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ -+ -+/* DAC.EVCTRL bit masks and bit positions */ -+#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -+#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ -+ -+#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -+#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -+#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -+#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -+#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -+#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -+#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -+#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ -+ -+/* DAC.STATUS bit masks and bit positions */ -+#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -+#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ -+ -+#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -+#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ -+ -+/* DAC.CH0GAINCAL bit masks and bit positions */ -+#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -+#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -+#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -+#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -+#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -+#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -+#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -+#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -+#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -+#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -+#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -+#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -+#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -+#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -+#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -+#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ -+ -+/* DAC.CH0OFFSETCAL bit masks and bit positions */ -+#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -+#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -+#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -+#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -+#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -+#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -+#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -+#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -+#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -+#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -+#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -+#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -+#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -+#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -+#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -+#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ -+ -+/* DAC.CH1GAINCAL bit masks and bit positions */ -+#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -+#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -+#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -+#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -+#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -+#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -+#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -+#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -+#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -+#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -+#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -+#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -+#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -+#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -+#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -+#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ -+ -+/* DAC.CH1OFFSETCAL bit masks and bit positions */ -+#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -+#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -+#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -+#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -+#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -+#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -+#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -+#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -+#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -+#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -+#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -+#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -+#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -+#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -+#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -+#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -+#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HSMODE Predefined. */ -+/* AC_HSMODE Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* RTC - Real-Time Counter */ -+/* RTC.CTRL bit masks and bit positions */ -+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ -+ -+/* RTC.STATUS bit masks and bit positions */ -+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC.INTCTRL bit masks and bit positions */ -+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC.INTFLAGS bit masks and bit positions */ -+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* USB - USB */ -+/* USB_EP.STATUS bit masks and bit positions */ -+#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -+#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ -+ -+#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -+#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ -+ -+#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -+#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ -+ -+#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -+#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ -+ -+#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -+#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ -+ -+#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -+#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ -+ -+#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -+#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ -+ -+#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -+#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ -+ -+#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ -+ -+#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ -+ -+#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -+#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ -+ -+/* USB_EP.CTRL bit masks and bit positions */ -+#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -+#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -+#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -+#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -+#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -+#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ -+ -+#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -+#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ -+ -+#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -+#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ -+ -+#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -+#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ -+ -+#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -+#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ -+ -+#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -+#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -+#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -+#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -+#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -+#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -+#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -+#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ -+ -+/* USB_EP.CNT bit masks and bit positions */ -+#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -+#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ -+ -+/* USB.CTRLA bit masks and bit positions */ -+#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -+#define USB_ENABLE_bp 7 /* USB Enable bit position. */ -+ -+#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -+#define USB_SPEED_bp 6 /* Speed Select bit position. */ -+ -+#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -+#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ -+ -+#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -+#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ -+ -+#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -+#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -+#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -+#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -+#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -+#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -+#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -+#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -+#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -+#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ -+ -+/* USB.CTRLB bit masks and bit positions */ -+#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -+#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ -+ -+#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -+#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ -+ -+#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -+#define USB_GNACK_bp 1 /* Global NACK bit position. */ -+ -+#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -+#define USB_ATTACH_bp 0 /* Attach bit position. */ -+ -+/* USB.STATUS bit masks and bit positions */ -+#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -+#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ -+ -+#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -+#define USB_RESUME_bp 2 /* Resume bit position. */ -+ -+#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -+#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ -+ -+#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -+#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ -+ -+/* USB.ADDR bit masks and bit positions */ -+#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -+#define USB_ADDR_gp 0 /* Device Address group position. */ -+#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -+#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -+#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -+#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -+#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -+#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -+#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -+#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -+#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -+#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -+#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -+#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -+#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -+#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ -+ -+/* USB.FIFOWP bit masks and bit positions */ -+#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -+#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -+#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -+#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -+#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -+#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -+#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -+#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -+#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -+#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -+#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -+#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ -+ -+/* USB.FIFORP bit masks and bit positions */ -+#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -+#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -+#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -+#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -+#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -+#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -+#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -+#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -+#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -+#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -+#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -+#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ -+ -+/* USB.INTCTRLA bit masks and bit positions */ -+#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -+#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ -+ -+#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -+#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ -+ -+#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -+#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ -+ -+#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -+#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ -+ -+#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* USB.INTCTRLB bit masks and bit positions */ -+#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -+#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ -+ -+#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -+#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ -+ -+/* USB.INTFLAGSACLR bit masks and bit positions */ -+#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -+#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ -+ -+#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -+#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ -+ -+#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -+#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ -+ -+#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -+#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ -+ -+#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -+#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ -+ -+#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -+#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ -+ -+#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -+#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ -+ -+#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -+#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSASET bit masks and bit positions */ -+/* USB_SOFIF Predefined. */ -+/* USB_SOFIF Predefined. */ -+ -+/* USB_SUSPENDIF Predefined. */ -+/* USB_SUSPENDIF Predefined. */ -+ -+/* USB_RESUMEIF Predefined. */ -+/* USB_RESUMEIF Predefined. */ -+ -+/* USB_RSTIF Predefined. */ -+/* USB_RSTIF Predefined. */ -+ -+/* USB_CRCIF Predefined. */ -+/* USB_CRCIF Predefined. */ -+ -+/* USB_UNFIF Predefined. */ -+/* USB_UNFIF Predefined. */ -+ -+/* USB_OVFIF Predefined. */ -+/* USB_OVFIF Predefined. */ -+ -+/* USB_STALLIF Predefined. */ -+/* USB_STALLIF Predefined. */ -+ -+/* USB.INTFLAGSBCLR bit masks and bit positions */ -+#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -+#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ -+ -+#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -+#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSBSET bit masks and bit positions */ -+/* USB_TRNIF Predefined. */ -+/* USB_TRNIF Predefined. */ -+ -+/* USB_SETUPIF Predefined. */ -+/* USB_SETUPIF Predefined. */ -+ -+/* PORT - I/O Port Configuration */ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ -+ -+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -+#define PORT_SPI_bp 5 /* SPI bit position. */ -+ -+#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -+#define PORT_USART0_bp 4 /* USART0 bit position. */ -+ -+#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -+#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ -+ -+#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -+#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ -+ -+#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -+#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ -+ -+#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -+#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ -+ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC0.CTRLA bit masks and bit positions */ -+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC0.CTRLB bit masks and bit positions */ -+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ -+ -+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ -+ -+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC0.CTRLC bit masks and bit positions */ -+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ -+ -+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ -+ -+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC0.CTRLD bit masks and bit positions */ -+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC0_EVACT_gp 5 /* Event Action group position. */ -+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC0.CTRLE bit masks and bit positions */ -+#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC0.INTCTRLA bit masks and bit positions */ -+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC0.INTCTRLB bit masks and bit positions */ -+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ -+ -+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ -+ -+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC0.CTRLFCLR bit masks and bit positions */ -+#define TC0_CMD_gm 0x0C /* Command group mask. */ -+#define TC0_CMD_gp 2 /* Command group position. */ -+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC0_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC0_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC0_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC0.CTRLFSET bit masks and bit positions */ -+/* TC0_CMD Predefined. */ -+/* TC0_CMD Predefined. */ -+ -+/* TC0_LUPD Predefined. */ -+/* TC0_LUPD Predefined. */ -+ -+/* TC0_DIR Predefined. */ -+/* TC0_DIR Predefined. */ -+ -+/* TC0.CTRLGCLR bit masks and bit positions */ -+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ -+ -+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ -+ -+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC0.CTRLGSET bit masks and bit positions */ -+/* TC0_CCDBV Predefined. */ -+/* TC0_CCDBV Predefined. */ -+ -+/* TC0_CCCBV Predefined. */ -+/* TC0_CCCBV Predefined. */ -+ -+/* TC0_CCBBV Predefined. */ -+/* TC0_CCBBV Predefined. */ -+ -+/* TC0_CCABV Predefined. */ -+/* TC0_CCABV Predefined. */ -+ -+/* TC0_PERBV Predefined. */ -+/* TC0_PERBV Predefined. */ -+ -+/* TC0.INTFLAGS bit masks and bit positions */ -+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ -+ -+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ -+ -+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC1.CTRLA bit masks and bit positions */ -+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC1.CTRLB bit masks and bit positions */ -+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC1.CTRLC bit masks and bit positions */ -+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC1.CTRLD bit masks and bit positions */ -+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC1_EVACT_gp 5 /* Event Action group position. */ -+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC1.CTRLE bit masks and bit positions */ -+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ -+ -+/* TC1.INTCTRLA bit masks and bit positions */ -+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC1.INTCTRLB bit masks and bit positions */ -+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC1.CTRLFCLR bit masks and bit positions */ -+#define TC1_CMD_gm 0x0C /* Command group mask. */ -+#define TC1_CMD_gp 2 /* Command group position. */ -+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC1_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC1_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC1_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC1.CTRLFSET bit masks and bit positions */ -+/* TC1_CMD Predefined. */ -+/* TC1_CMD Predefined. */ -+ -+/* TC1_LUPD Predefined. */ -+/* TC1_LUPD Predefined. */ -+ -+/* TC1_DIR Predefined. */ -+/* TC1_DIR Predefined. */ -+ -+/* TC1.CTRLGCLR bit masks and bit positions */ -+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC1.CTRLGSET bit masks and bit positions */ -+/* TC1_CCBBV Predefined. */ -+/* TC1_CCBBV Predefined. */ -+ -+/* TC1_CCABV Predefined. */ -+/* TC1_CCABV Predefined. */ -+ -+/* TC1_PERBV Predefined. */ -+/* TC1_PERBV Predefined. */ -+ -+/* TC1.INTFLAGS bit masks and bit positions */ -+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+/* TC2.CTRLA bit masks and bit positions */ -+#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC2.CTRLB bit masks and bit positions */ -+#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -+#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ -+ -+#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -+#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ -+ -+#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -+#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ -+ -+#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -+#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ -+ -+#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -+#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ -+ -+#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -+#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ -+ -+#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -+#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ -+ -+#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -+#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ -+ -+/* TC2.CTRLC bit masks and bit positions */ -+#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -+#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ -+ -+#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -+#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ -+ -+#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -+#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ -+ -+#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -+#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ -+ -+#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -+#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ -+ -+#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -+#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ -+ -+#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -+#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ -+ -+#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -+#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ -+ -+/* TC2.CTRLE bit masks and bit positions */ -+#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC2.INTCTRLA bit masks and bit positions */ -+#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -+#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -+#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -+#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -+#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -+#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ -+ -+#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -+#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -+#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -+#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -+#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -+#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ -+ -+/* TC2.INTCTRLB bit masks and bit positions */ -+#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -+#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -+#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -+#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -+#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -+#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -+#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -+#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -+#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -+#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -+#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -+#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -+#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -+#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -+#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -+#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -+#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -+#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -+#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -+#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -+#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ -+ -+/* TC2.CTRLF bit masks and bit positions */ -+#define TC2_CMD_gm 0x0C /* Command group mask. */ -+#define TC2_CMD_gp 2 /* Command group position. */ -+#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC2_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -+#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -+#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -+#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -+#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -+#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ -+ -+/* TC2.INTFLAGS bit masks and bit positions */ -+#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -+#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ -+ -+#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -+#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ -+ -+#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -+#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ -+ -+#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -+#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ -+ -+#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ -+ -+#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ -+ -+/* AWEX - Timer/Counter Advanced Waveform Extension */ -+/* AWEX.CTRL bit masks and bit positions */ -+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ -+ -+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ -+ -+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ -+ -+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ -+ -+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ -+ -+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ -+ -+/* AWEX.FDCTRL bit masks and bit positions */ -+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ -+ -+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ -+ -+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ -+ -+/* AWEX.STATUS bit masks and bit positions */ -+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ -+ -+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ -+ -+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ -+ -+/* AWEX.STATUSSET bit masks and bit positions */ -+/* AWEX_FDF Predefined. */ -+/* AWEX_FDF Predefined. */ -+ -+/* AWEX_DTHSBUFV Predefined. */ -+/* AWEX_DTHSBUFV Predefined. */ -+ -+/* AWEX_DTLSBUFV Predefined. */ -+/* AWEX_DTLSBUFV Predefined. */ -+ -+/* HIRES - Timer/Counter High-Resolution Extension */ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -+#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* LOCKBIT - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT0_vect_num 2 -+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -+#define PORTC_INT1_vect_num 3 -+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT0_vect_num 4 -+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -+#define PORTR_INT1_vect_num 5 -+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ -+ -+/* DMA interrupt vectors */ -+#define DMA_CH0_vect_num 6 -+#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -+#define DMA_CH1_vect_num 7 -+#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -+#define DMA_CH2_vect_num 8 -+#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -+#define DMA_CH3_vect_num 9 -+#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ -+ -+/* RTC interrupt vectors */ -+#define RTC_OVF_vect_num 10 -+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -+#define RTC_COMP_vect_num 11 -+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 12 -+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 13 -+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_OVF_vect_num 14 -+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LUNF_vect_num 14 -+#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_ERR_vect_num 15 -+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_HUNF_vect_num 15 -+#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCA_vect_num 16 -+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPA_vect_num 16 -+#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCB_vect_num 17 -+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPB_vect_num 17 -+#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCC_vect_num 18 -+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPC_vect_num 18 -+#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCD_vect_num 19 -+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPD_vect_num 19 -+#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ -+ -+/* TCC1 interrupt vectors */ -+#define TCC1_OVF_vect_num 20 -+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -+#define TCC1_ERR_vect_num 21 -+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -+#define TCC1_CCA_vect_num 22 -+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -+#define TCC1_CCB_vect_num 23 -+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 24 -+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 25 -+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 26 -+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 27 -+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ -+ -+/* USARTC1 interrupt vectors */ -+#define USARTC1_RXC_vect_num 28 -+#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -+#define USARTC1_DRE_vect_num 29 -+#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -+#define USARTC1_TXC_vect_num 30 -+#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ -+ -+/* AES interrupt vectors */ -+#define AES_INT_vect_num 31 -+#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 32 -+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -+#define NVM_SPM_vect_num 33 -+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ -+ -+/* PORTB interrupt vectors */ -+#define PORTB_INT0_vect_num 34 -+#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -+#define PORTB_INT1_vect_num 35 -+#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ -+ -+/* PORTE interrupt vectors */ -+#define PORTE_INT0_vect_num 43 -+#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -+#define PORTE_INT1_vect_num 44 -+#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ -+ -+/* TWIE interrupt vectors */ -+#define TWIE_TWIS_vect_num 45 -+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -+#define TWIE_TWIM_vect_num 46 -+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_OVF_vect_num 47 -+#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -+#define TCE0_ERR_vect_num 48 -+#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -+#define TCE0_CCA_vect_num 49 -+#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -+#define TCE0_CCB_vect_num 50 -+#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -+#define TCE0_CCC_vect_num 51 -+#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -+#define TCE0_CCD_vect_num 52 -+#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ -+ -+/* USARTE0 interrupt vectors */ -+#define USARTE0_RXC_vect_num 58 -+#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -+#define USARTE0_DRE_vect_num 59 -+#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -+#define USARTE0_TXC_vect_num 60 -+#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT0_vect_num 64 -+#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -+#define PORTD_INT1_vect_num 65 -+#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ -+ -+/* PORTA interrupt vectors */ -+#define PORTA_INT0_vect_num 66 -+#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -+#define PORTA_INT1_vect_num 67 -+#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ -+ -+/* ACA interrupt vectors */ -+#define ACA_AC0_vect_num 68 -+#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -+#define ACA_AC1_vect_num 69 -+#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -+#define ACA_ACW_vect_num 70 -+#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ -+ -+/* ADCA interrupt vectors */ -+#define ADCA_CH0_vect_num 71 -+#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -+#define ADCA_CH1_vect_num 72 -+#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -+#define ADCA_CH2_vect_num 73 -+#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -+#define ADCA_CH3_vect_num 74 -+#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_OVF_vect_num 77 -+#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LUNF_vect_num 77 -+#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_ERR_vect_num 78 -+#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_HUNF_vect_num 78 -+#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCA_vect_num 79 -+#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPA_vect_num 79 -+#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCB_vect_num 80 -+#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPB_vect_num 80 -+#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCC_vect_num 81 -+#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPC_vect_num 81 -+#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCD_vect_num 82 -+#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPD_vect_num 82 -+#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ -+ -+/* TCD1 interrupt vectors */ -+#define TCD1_OVF_vect_num 83 -+#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -+#define TCD1_ERR_vect_num 84 -+#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -+#define TCD1_CCA_vect_num 85 -+#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -+#define TCD1_CCB_vect_num 86 -+#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ -+ -+/* SPID interrupt vectors */ -+#define SPID_INT_vect_num 87 -+#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ -+ -+/* USARTD0 interrupt vectors */ -+#define USARTD0_RXC_vect_num 88 -+#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -+#define USARTD0_DRE_vect_num 89 -+#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -+#define USARTD0_TXC_vect_num 90 -+#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ -+ -+/* USARTD1 interrupt vectors */ -+#define USARTD1_RXC_vect_num 91 -+#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -+#define USARTD1_DRE_vect_num 92 -+#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -+#define USARTD1_TXC_vect_num 93 -+#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ -+ -+/* USB interrupt vectors */ -+#define USB_BUSEVENT_vect_num 125 -+#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -+#define USB_TRNCOMPL_vect_num 126 -+#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (127 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (20480) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (16384) -+#define APP_SECTION_PAGE_SIZE (256) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0x3000) -+#define APPTABLE_SECTION_SIZE (4096) -+#define APPTABLE_SECTION_PAGE_SIZE (256) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x4000) -+#define BOOT_SECTION_SIZE (4096) -+#define BOOT_SECTION_PAGE_SIZE (256) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (10240) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (1024) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (2048) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (1024) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (6) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (256) -+#define USER_SIGNATURES_PAGE_SIZE (256) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (52) -+#define PROD_SIGNATURES_PAGE_SIZE (256) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 256 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 6 -+ -+/* Fuse Byte 0 Reserved */ -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x94 -+#define SIGNATURE_2 0x41 -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA16A4U_H_INCLUDED */ -+ -diff --git a/include/avr/iox16c4.h b/include/avr/iox16c4.h -new file mode 100644 -index 0000000..5ec8424 ---- /dev/null -+++ b/include/avr/iox16c4.h -@@ -0,0 +1,6030 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox16c4.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA16C4_H_INCLUDED -+#define _AVR_ATXMEGA16C4_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+VPORT - Virtual Ports -+-------------------------------------------------------------------------- -+*/ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t USBCTRL; /* USB Control Register */ -+} CLK_t; -+ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t reserved_0x02; -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t PRPD; /* Power Reduction Port D */ -+ register8_t PRPE; /* Power Reduction Port E */ -+ register8_t PRPF; /* Power Reduction Port F */ -+} PR_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+/* USB Prescaler Division Factor */ -+typedef enum CLK_USBPSDIV_enum -+{ -+ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ -+ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ -+ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ -+ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ -+ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ -+ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -+} CLK_USBPSDIV_t; -+ -+/* USB Clock Source */ -+typedef enum CLK_USBSRC_enum -+{ -+ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ -+ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -+} CLK_USBSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control Register */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+/* 2 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC2MCREF_enum -+{ -+ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC2MCREF_t; -+ -+/* 32 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC32MCREF_enum -+{ -+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -+} OSC_RC32MCREF_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t ANAINIT; /* Analog Startup Delay */ -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t AWEXLOCK; /* AWEX Lock */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORTCFG - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t VPCTRLA; /* Virtual Port Control Register A */ -+ register8_t VPCTRLB; /* Virtual Port Control Register B */ -+ register8_t CLKEVOUT; /* Clock and Event Out Register */ -+ register8_t reserved_0x05; -+ register8_t EVOUTSEL; /* Event Output Select */ -+} PORTCFG_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP02MAP_enum -+{ -+ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ -+ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ -+ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ -+ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ -+ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ -+ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ -+ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ -+ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ -+ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ -+ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ -+ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ -+ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ -+ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ -+ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ -+ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ -+ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -+} PORTCFG_VP02MAP_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP13MAP_enum -+{ -+ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ -+ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ -+ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ -+ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ -+ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ -+ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ -+ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ -+ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ -+ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ -+ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ -+ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ -+ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ -+ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ -+ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ -+ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ -+ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -+} PORTCFG_VP13MAP_t; -+ -+/* System Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ -+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ -+ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -+} PORTCFG_CLKOUT_t; -+ -+/* Peripheral Clock Output Select */ -+typedef enum PORTCFG_CLKOUTSEL_enum -+{ -+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -+} PORTCFG_CLKOUTSEL_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ -+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ -+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -+} PORTCFG_EVOUT_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+} EVSYS_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ -+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ -+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ -+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ -+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ -+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ -+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ -+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ -+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ -+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ -+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ -+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ -+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ -+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ -+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ -+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ -+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ -+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ -+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ -+ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ -+ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ -+ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ -+ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ -+ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ -+ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ -+ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ -+ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ -+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ -+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ -+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ -+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ -+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ -+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ -+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ -+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ -+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ -+ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ -+ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ -+ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ -+ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ -+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ -+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ -+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ -+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ -+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -+ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ -+ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ -+ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ -+ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ -+ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -+} EVSYS_CHMUX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ -+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ -+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ -+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ -+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} NVM_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t reserved_0x07; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+} ADC_t; -+ -+/* Current Limitation */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -+} ADC_CURRLIMIT_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+} ADC_CH_MUXNEG_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ -+ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ -+ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ -+ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC - Real-Time Counter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Real-Time Counter */ -+typedef struct RTC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary register */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ _WORDREGISTER(CNT); /* Count Register */ -+ _WORDREGISTER(PER); /* Period Register */ -+ _WORDREGISTER(COMP); /* Compare Register */ -+} RTC_t; -+ -+/* Prescaler Factor */ -+typedef enum RTC_PRESCALER_enum -+{ -+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ -+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ -+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ -+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ -+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ -+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ -+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ -+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -+} RTC_PRESCALER_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC_COMPINTLVL_enum -+{ -+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC_OVFINTLVL_enum -+{ -+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+} TWI_t; -+ -+/* SDA Hold Time */ -+typedef enum TWI_SDAHOLD_enum -+{ -+ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ -+ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ -+ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ -+ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -+} TWI_SDAHOLD_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USB - USB -+-------------------------------------------------------------------------- -+*/ -+ -+/* USB Endpoint */ -+typedef struct USB_EP_struct -+{ -+ register8_t STATUS; /* Endpoint Status */ -+ register8_t CTRL; /* Endpoint Control */ -+ _WORDREGISTER(CNT); /* USB Endpoint Counter */ -+ _WORDREGISTER(DATAPTR); /* Data Pointer */ -+ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -+} USB_EP_t; -+ -+ -+/* Universal Serial Bus */ -+typedef struct USB_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t FIFOWP; /* FIFO Write Pointer Register */ -+ register8_t FIFORP; /* FIFO Read Pointer Register */ -+ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ -+ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ -+ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ -+ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t reserved_0x20; -+ register8_t reserved_0x21; -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t CAL0; /* Calibration Byte 0 */ -+ register8_t CAL1; /* Calibration Byte 1 */ -+} USB_t; -+ -+ -+/* USB Endpoint Table */ -+typedef struct USB_EP_TABLE_struct -+{ -+ USB_EP_t EP0OUT; /* Endpoint 0 */ -+ USB_EP_t EP0IN; /* Endpoint 0 */ -+ USB_EP_t EP1OUT; /* Endpoint 1 */ -+ USB_EP_t EP1IN; /* Endpoint 1 */ -+ USB_EP_t EP2OUT; /* Endpoint 2 */ -+ USB_EP_t EP2IN; /* Endpoint 2 */ -+ USB_EP_t EP3OUT; /* Endpoint 3 */ -+ USB_EP_t EP3IN; /* Endpoint 3 */ -+ USB_EP_t EP4OUT; /* Endpoint 4 */ -+ USB_EP_t EP4IN; /* Endpoint 4 */ -+ USB_EP_t EP5OUT; /* Endpoint 5 */ -+ USB_EP_t EP5IN; /* Endpoint 5 */ -+ USB_EP_t EP6OUT; /* Endpoint 6 */ -+ USB_EP_t EP6IN; /* Endpoint 6 */ -+ USB_EP_t EP7OUT; /* Endpoint 7 */ -+ USB_EP_t EP7IN; /* Endpoint 7 */ -+ USB_EP_t EP8OUT; /* Endpoint 8 */ -+ USB_EP_t EP8IN; /* Endpoint 8 */ -+ USB_EP_t EP9OUT; /* Endpoint 9 */ -+ USB_EP_t EP9IN; /* Endpoint 9 */ -+ USB_EP_t EP10OUT; /* Endpoint 10 */ -+ USB_EP_t EP10IN; /* Endpoint 10 */ -+ USB_EP_t EP11OUT; /* Endpoint 11 */ -+ USB_EP_t EP11IN; /* Endpoint 11 */ -+ USB_EP_t EP12OUT; /* Endpoint 12 */ -+ USB_EP_t EP12IN; /* Endpoint 12 */ -+ USB_EP_t EP13OUT; /* Endpoint 13 */ -+ USB_EP_t EP13IN; /* Endpoint 13 */ -+ USB_EP_t EP14OUT; /* Endpoint 14 */ -+ USB_EP_t EP14IN; /* Endpoint 14 */ -+ USB_EP_t EP15OUT; /* Endpoint 15 */ -+ USB_EP_t EP15IN; /* Endpoint 15 */ -+ register8_t reserved_0x100; -+ register8_t reserved_0x101; -+ register8_t reserved_0x102; -+ register8_t reserved_0x103; -+ register8_t reserved_0x104; -+ register8_t reserved_0x105; -+ register8_t reserved_0x106; -+ register8_t reserved_0x107; -+ register8_t reserved_0x108; -+ register8_t reserved_0x109; -+ register8_t reserved_0x10A; -+ register8_t reserved_0x10B; -+ register8_t reserved_0x10C; -+ register8_t reserved_0x10D; -+ register8_t reserved_0x10E; -+ register8_t reserved_0x10F; -+ register8_t FRAMENUML; /* Frame Number Low Byte */ -+ register8_t FRAMENUMH; /* Frame Number High Byte */ -+} USB_EP_TABLE_t; -+ -+/* Interrupt level */ -+typedef enum USB_INTLVL_enum -+{ -+ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} USB_INTLVL_t; -+ -+/* USB Endpoint Type */ -+typedef enum USB_EP_TYPE_enum -+{ -+ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ -+ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ -+ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ -+ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -+} USB_EP_TYPE_t; -+ -+/* USB Endpoint Buffersize */ -+typedef enum USB_EP_BUFSIZE_enum -+{ -+ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ -+ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ -+ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ -+ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ -+ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ -+ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ -+ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ -+ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -+} USB_EP_BUFSIZE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - I/O Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INT0MASK; /* Port Interrupt 0 Mask */ -+ register8_t INT1MASK; /* Port Interrupt 1 Mask */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t REMAP; /* I/O Port Pin Remap Register */ -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Port Interrupt 0 Level */ -+typedef enum PORT_INT0LVL_enum -+{ -+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INT0LVL_t; -+ -+/* Port Interrupt 1 Level */ -+typedef enum PORT_INT1LVL_enum -+{ -+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ -+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ -+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -+} PORT_INT1LVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 0 */ -+typedef struct TC0_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC0_t; -+ -+ -+/* 16-bit Timer/Counter 1 */ -+typedef struct TC1_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+} TC1_t; -+ -+/* Clock Selection */ -+typedef enum TC_CLKSEL_enum -+{ -+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_CLKSEL_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC_WGMODE_enum -+{ -+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC_WGMODE_t; -+ -+/* Byte Mode */ -+typedef enum TC_BYTEM_enum -+{ -+ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ -+ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -+} TC_BYTEM_t; -+ -+/* Event Action */ -+typedef enum TC_EVACT_enum -+{ -+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ -+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ -+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ -+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ -+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ -+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC_EVSEL_enum -+{ -+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_EVSEL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC_ERRINTLVL_enum -+{ -+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC_OVFINTLVL_enum -+{ -+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_OVFINTLVL_t; -+ -+/* Compare or Capture D Interrupt Level */ -+typedef enum TC_CCDINTLVL_enum -+{ -+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC_CCDINTLVL_t; -+ -+/* Compare or Capture C Interrupt Level */ -+typedef enum TC_CCCINTLVL_enum -+{ -+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC_CCCINTLVL_t; -+ -+/* Compare or Capture B Interrupt Level */ -+typedef enum TC_CCBINTLVL_enum -+{ -+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_CCBINTLVL_t; -+ -+/* Compare or Capture A Interrupt Level */ -+typedef enum TC_CCAINTLVL_enum -+{ -+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_CCAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC_CMD_enum -+{ -+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC2 - 16-bit Timer/Counter type 2 -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter type 2 */ -+typedef struct TC2_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t reserved_0x03; -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t reserved_0x08; -+ register8_t CTRLF; /* Control Register F */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t LCNT; /* Low Byte Count */ -+ register8_t HCNT; /* High Byte Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t LPER; /* Low Byte Period */ -+ register8_t HPER; /* High Byte Period */ -+ register8_t LCMPA; /* Low Byte Compare A */ -+ register8_t HCMPA; /* High Byte Compare A */ -+ register8_t LCMPB; /* Low Byte Compare B */ -+ register8_t HCMPB; /* High Byte Compare B */ -+ register8_t LCMPC; /* Low Byte Compare C */ -+ register8_t HCMPC; /* High Byte Compare C */ -+ register8_t LCMPD; /* Low Byte Compare D */ -+ register8_t HCMPD; /* High Byte Compare D */ -+} TC2_t; -+ -+/* Clock Selection */ -+typedef enum TC2_CLKSEL_enum -+{ -+ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC2_CLKSEL_t; -+ -+/* Byte Mode */ -+typedef enum TC2_BYTEM_enum -+{ -+ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ -+ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -+} TC2_BYTEM_t; -+ -+/* High Byte Underflow Interrupt Level */ -+typedef enum TC2_HUNFINTLVL_enum -+{ -+ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_HUNFINTLVL_t; -+ -+/* Low Byte Underflow Interrupt Level */ -+typedef enum TC2_LUNFINTLVL_enum -+{ -+ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LUNFINTLVL_t; -+ -+/* Low Byte Compare D Interrupt Level */ -+typedef enum TC2_LCMPDINTLVL_enum -+{ -+ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC2_LCMPDINTLVL_t; -+ -+/* Low Byte Compare C Interrupt Level */ -+typedef enum TC2_LCMPCINTLVL_enum -+{ -+ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC2_LCMPCINTLVL_t; -+ -+/* Low Byte Compare B Interrupt Level */ -+typedef enum TC2_LCMPBINTLVL_enum -+{ -+ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_LCMPBINTLVL_t; -+ -+/* Low Byte Compare A Interrupt Level */ -+typedef enum TC2_LCMPAINTLVL_enum -+{ -+ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LCMPAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMD_enum -+{ -+ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC2_CMD_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMDEN_enum -+{ -+ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ -+ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ -+ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -+} TC2_CMDEN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AWEX - Timer/Counter Advanced Waveform Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Advanced Waveform Extension */ -+typedef struct AWEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t FDEMASK; /* Fault Detection Event Mask */ -+ register8_t FDCTRL; /* Fault Detection Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t STATUSSET; /* Status Set Register */ -+ register8_t DTBOTH; /* Dead Time Both Sides */ -+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ -+ register8_t DTLS; /* Dead Time Low Side */ -+ register8_t DTHS; /* Dead Time High Side */ -+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ -+ register8_t DTHSBUF; /* Dead Time High Side Buffer */ -+ register8_t OUTOVEN; /* Output Override Enable */ -+} AWEX_t; -+ -+/* Fault Detect Action */ -+typedef enum AWEX_FDACT_enum -+{ -+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ -+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -+} AWEX_FDACT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+HIRES - Timer/Counter High-Resolution Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register */ -+} HIRES_t; -+ -+/* High Resolution Enable */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ -+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+} IRDA_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t reserved_0x00; -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+} NVM_FUSES_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* Timer Oscillator pin location */ -+typedef enum TOSCSEL_enum -+{ -+ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ -+ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -+} TOSCSEL_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -+} BOD_t; -+ -+/* BOD operation */ -+typedef enum BODACT_enum -+{ -+ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BODACT_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WDP_enum -+{ -+ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ -+ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ -+ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ -+ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ -+ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ -+ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ -+ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ -+ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ -+ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ -+ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ -+ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -+} WDP_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LOCKBIT - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ -+ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t USBCAL0; /* USB Calibration Byte 0 */ -+ register8_t USBCAL1; /* USB Calibration Byte 1 */ -+ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ -+ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+} NVM_PROD_SIGNATURES_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -+#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -+#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -+#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -+#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -+#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -+#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -+#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -+#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+#define CLK_USBCTRL _SFR_MEM8(0x0044) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* DFLL - DFLL */ -+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -+#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -+#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPD _SFR_MEM8(0x0074) -+#define PR_PRPE _SFR_MEM8(0x0075) -+#define PR_PRPF _SFR_MEM8(0x0076) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_ANAINIT _SFR_MEM8(0x0097) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_AWEXLOCK _SFR_MEM8(0x0099) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCA_CTRLA _SFR_MEM8(0x0200) -+#define ADCA_CTRLB _SFR_MEM8(0x0201) -+#define ADCA_REFCTRL _SFR_MEM8(0x0202) -+#define ADCA_EVCTRL _SFR_MEM8(0x0203) -+#define ADCA_PRESCALER _SFR_MEM8(0x0204) -+#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -+#define ADCA_TEMP _SFR_MEM8(0x0207) -+#define ADCA_CAL _SFR_MEM16(0x020C) -+#define ADCA_CH0RES _SFR_MEM16(0x0210) -+#define ADCA_CMP _SFR_MEM16(0x0218) -+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -+#define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -+ -+/* AC - Analog Comparator */ -+#define ACA_AC0CTRL _SFR_MEM8(0x0380) -+#define ACA_AC1CTRL _SFR_MEM8(0x0381) -+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -+#define ACA_CTRLA _SFR_MEM8(0x0384) -+#define ACA_CTRLB _SFR_MEM8(0x0385) -+#define ACA_WINCTRL _SFR_MEM8(0x0386) -+#define ACA_STATUS _SFR_MEM8(0x0387) -+ -+/* RTC - Real-Time Counter */ -+#define RTC_CTRL _SFR_MEM8(0x0400) -+#define RTC_STATUS _SFR_MEM8(0x0401) -+#define RTC_INTCTRL _SFR_MEM8(0x0402) -+#define RTC_INTFLAGS _SFR_MEM8(0x0403) -+#define RTC_TEMP _SFR_MEM8(0x0404) -+#define RTC_CNT _SFR_MEM16(0x0408) -+#define RTC_PER _SFR_MEM16(0x040A) -+#define RTC_COMP _SFR_MEM16(0x040C) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIE_CTRL _SFR_MEM8(0x04A0) -+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -+ -+/* USB - Universal Serial Bus */ -+#define USB_CTRLA _SFR_MEM8(0x04C0) -+#define USB_CTRLB _SFR_MEM8(0x04C1) -+#define USB_STATUS _SFR_MEM8(0x04C2) -+#define USB_ADDR _SFR_MEM8(0x04C3) -+#define USB_FIFOWP _SFR_MEM8(0x04C4) -+#define USB_FIFORP _SFR_MEM8(0x04C5) -+#define USB_EPPTR _SFR_MEM16(0x04C6) -+#define USB_INTCTRLA _SFR_MEM8(0x04C8) -+#define USB_INTCTRLB _SFR_MEM8(0x04C9) -+#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -+#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -+#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -+#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -+#define USB_CAL0 _SFR_MEM8(0x04FA) -+#define USB_CAL1 _SFR_MEM8(0x04FB) -+ -+/* PORT - I/O Ports */ -+#define PORTA_DIR _SFR_MEM8(0x0600) -+#define PORTA_DIRSET _SFR_MEM8(0x0601) -+#define PORTA_DIRCLR _SFR_MEM8(0x0602) -+#define PORTA_DIRTGL _SFR_MEM8(0x0603) -+#define PORTA_OUT _SFR_MEM8(0x0604) -+#define PORTA_OUTSET _SFR_MEM8(0x0605) -+#define PORTA_OUTCLR _SFR_MEM8(0x0606) -+#define PORTA_OUTTGL _SFR_MEM8(0x0607) -+#define PORTA_IN _SFR_MEM8(0x0608) -+#define PORTA_INTCTRL _SFR_MEM8(0x0609) -+#define PORTA_INT0MASK _SFR_MEM8(0x060A) -+#define PORTA_INT1MASK _SFR_MEM8(0x060B) -+#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_REMAP _SFR_MEM8(0x060E) -+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -+ -+/* PORT - I/O Ports */ -+#define PORTB_DIR _SFR_MEM8(0x0620) -+#define PORTB_DIRSET _SFR_MEM8(0x0621) -+#define PORTB_DIRCLR _SFR_MEM8(0x0622) -+#define PORTB_DIRTGL _SFR_MEM8(0x0623) -+#define PORTB_OUT _SFR_MEM8(0x0624) -+#define PORTB_OUTSET _SFR_MEM8(0x0625) -+#define PORTB_OUTCLR _SFR_MEM8(0x0626) -+#define PORTB_OUTTGL _SFR_MEM8(0x0627) -+#define PORTB_IN _SFR_MEM8(0x0628) -+#define PORTB_INTCTRL _SFR_MEM8(0x0629) -+#define PORTB_INT0MASK _SFR_MEM8(0x062A) -+#define PORTB_INT1MASK _SFR_MEM8(0x062B) -+#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -+#define PORTB_REMAP _SFR_MEM8(0x062E) -+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INT0MASK _SFR_MEM8(0x064A) -+#define PORTC_INT1MASK _SFR_MEM8(0x064B) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INT0MASK _SFR_MEM8(0x066A) -+#define PORTD_INT1MASK _SFR_MEM8(0x066B) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTE_DIR _SFR_MEM8(0x0680) -+#define PORTE_DIRSET _SFR_MEM8(0x0681) -+#define PORTE_DIRCLR _SFR_MEM8(0x0682) -+#define PORTE_DIRTGL _SFR_MEM8(0x0683) -+#define PORTE_OUT _SFR_MEM8(0x0684) -+#define PORTE_OUTSET _SFR_MEM8(0x0685) -+#define PORTE_OUTCLR _SFR_MEM8(0x0686) -+#define PORTE_OUTTGL _SFR_MEM8(0x0687) -+#define PORTE_IN _SFR_MEM8(0x0688) -+#define PORTE_INTCTRL _SFR_MEM8(0x0689) -+#define PORTE_INT0MASK _SFR_MEM8(0x068A) -+#define PORTE_INT1MASK _SFR_MEM8(0x068B) -+#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -+#define PORTE_REMAP _SFR_MEM8(0x068E) -+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -+#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCC0_CTRLA _SFR_MEM8(0x0800) -+#define TCC0_CTRLB _SFR_MEM8(0x0801) -+#define TCC0_CTRLC _SFR_MEM8(0x0802) -+#define TCC0_CTRLD _SFR_MEM8(0x0803) -+#define TCC0_CTRLE _SFR_MEM8(0x0804) -+#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -+#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -+#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -+#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC0_TEMP _SFR_MEM8(0x080F) -+#define TCC0_CNT _SFR_MEM16(0x0820) -+#define TCC0_PER _SFR_MEM16(0x0826) -+#define TCC0_CCA _SFR_MEM16(0x0828) -+#define TCC0_CCB _SFR_MEM16(0x082A) -+#define TCC0_CCC _SFR_MEM16(0x082C) -+#define TCC0_CCD _SFR_MEM16(0x082E) -+#define TCC0_PERBUF _SFR_MEM16(0x0836) -+#define TCC0_CCABUF _SFR_MEM16(0x0838) -+#define TCC0_CCBBUF _SFR_MEM16(0x083A) -+#define TCC0_CCCBUF _SFR_MEM16(0x083C) -+#define TCC0_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCC2_CTRLA _SFR_MEM8(0x0800) -+#define TCC2_CTRLB _SFR_MEM8(0x0801) -+#define TCC2_CTRLC _SFR_MEM8(0x0802) -+#define TCC2_CTRLE _SFR_MEM8(0x0804) -+#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC2_CTRLF _SFR_MEM8(0x0809) -+#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC2_LCNT _SFR_MEM8(0x0820) -+#define TCC2_HCNT _SFR_MEM8(0x0821) -+#define TCC2_LPER _SFR_MEM8(0x0826) -+#define TCC2_HPER _SFR_MEM8(0x0827) -+#define TCC2_LCMPA _SFR_MEM8(0x0828) -+#define TCC2_HCMPA _SFR_MEM8(0x0829) -+#define TCC2_LCMPB _SFR_MEM8(0x082A) -+#define TCC2_HCMPB _SFR_MEM8(0x082B) -+#define TCC2_LCMPC _SFR_MEM8(0x082C) -+#define TCC2_HCMPC _SFR_MEM8(0x082D) -+#define TCC2_LCMPD _SFR_MEM8(0x082E) -+#define TCC2_HCMPD _SFR_MEM8(0x082F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCC1_CTRLA _SFR_MEM8(0x0840) -+#define TCC1_CTRLB _SFR_MEM8(0x0841) -+#define TCC1_CTRLC _SFR_MEM8(0x0842) -+#define TCC1_CTRLD _SFR_MEM8(0x0843) -+#define TCC1_CTRLE _SFR_MEM8(0x0844) -+#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -+#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -+#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -+#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC1_TEMP _SFR_MEM8(0x084F) -+#define TCC1_CNT _SFR_MEM16(0x0860) -+#define TCC1_PER _SFR_MEM16(0x0866) -+#define TCC1_CCA _SFR_MEM16(0x0868) -+#define TCC1_CCB _SFR_MEM16(0x086A) -+#define TCC1_PERBUF _SFR_MEM16(0x0876) -+#define TCC1_CCABUF _SFR_MEM16(0x0878) -+#define TCC1_CCBBUF _SFR_MEM16(0x087A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXC_CTRL _SFR_MEM8(0x0880) -+#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -+#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -+#define AWEXC_STATUS _SFR_MEM8(0x0884) -+#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -+#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -+#define AWEXC_DTLS _SFR_MEM8(0x0888) -+#define AWEXC_DTHS _SFR_MEM8(0x0889) -+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x0890) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08A0) -+#define USARTC0_STATUS _SFR_MEM8(0x08A1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -+#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -+#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC1_DATA _SFR_MEM8(0x08B0) -+#define USARTC1_STATUS _SFR_MEM8(0x08B1) -+#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -+#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -+#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -+#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -+#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIC_CTRL _SFR_MEM8(0x08C0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -+#define SPIC_STATUS _SFR_MEM8(0x08C2) -+#define SPIC_DATA _SFR_MEM8(0x08C3) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCD0_CTRLA _SFR_MEM8(0x0900) -+#define TCD0_CTRLB _SFR_MEM8(0x0901) -+#define TCD0_CTRLC _SFR_MEM8(0x0902) -+#define TCD0_CTRLD _SFR_MEM8(0x0903) -+#define TCD0_CTRLE _SFR_MEM8(0x0904) -+#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -+#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -+#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -+#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -+#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD0_TEMP _SFR_MEM8(0x090F) -+#define TCD0_CNT _SFR_MEM16(0x0920) -+#define TCD0_PER _SFR_MEM16(0x0926) -+#define TCD0_CCA _SFR_MEM16(0x0928) -+#define TCD0_CCB _SFR_MEM16(0x092A) -+#define TCD0_CCC _SFR_MEM16(0x092C) -+#define TCD0_CCD _SFR_MEM16(0x092E) -+#define TCD0_PERBUF _SFR_MEM16(0x0936) -+#define TCD0_CCABUF _SFR_MEM16(0x0938) -+#define TCD0_CCBBUF _SFR_MEM16(0x093A) -+#define TCD0_CCCBUF _SFR_MEM16(0x093C) -+#define TCD0_CCDBUF _SFR_MEM16(0x093E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCD2_CTRLA _SFR_MEM8(0x0900) -+#define TCD2_CTRLB _SFR_MEM8(0x0901) -+#define TCD2_CTRLC _SFR_MEM8(0x0902) -+#define TCD2_CTRLE _SFR_MEM8(0x0904) -+#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD2_CTRLF _SFR_MEM8(0x0909) -+#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD2_LCNT _SFR_MEM8(0x0920) -+#define TCD2_HCNT _SFR_MEM8(0x0921) -+#define TCD2_LPER _SFR_MEM8(0x0926) -+#define TCD2_HPER _SFR_MEM8(0x0927) -+#define TCD2_LCMPA _SFR_MEM8(0x0928) -+#define TCD2_HCMPA _SFR_MEM8(0x0929) -+#define TCD2_LCMPB _SFR_MEM8(0x092A) -+#define TCD2_HCMPB _SFR_MEM8(0x092B) -+#define TCD2_LCMPC _SFR_MEM8(0x092C) -+#define TCD2_HCMPC _SFR_MEM8(0x092D) -+#define TCD2_LCMPD _SFR_MEM8(0x092E) -+#define TCD2_HCMPD _SFR_MEM8(0x092F) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD0_DATA _SFR_MEM8(0x09A0) -+#define USARTD0_STATUS _SFR_MEM8(0x09A1) -+#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -+#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -+#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPID_CTRL _SFR_MEM8(0x09C0) -+#define SPID_INTCTRL _SFR_MEM8(0x09C1) -+#define SPID_STATUS _SFR_MEM8(0x09C2) -+#define SPID_DATA _SFR_MEM8(0x09C3) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCE0_CTRLA _SFR_MEM8(0x0A00) -+#define TCE0_CTRLB _SFR_MEM8(0x0A01) -+#define TCE0_CTRLC _SFR_MEM8(0x0A02) -+#define TCE0_CTRLD _SFR_MEM8(0x0A03) -+#define TCE0_CTRLE _SFR_MEM8(0x0A04) -+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE0_TEMP _SFR_MEM8(0x0A0F) -+#define TCE0_CNT _SFR_MEM16(0x0A20) -+#define TCE0_PER _SFR_MEM16(0x0A26) -+#define TCE0_CCA _SFR_MEM16(0x0A28) -+#define TCE0_CCB _SFR_MEM16(0x0A2A) -+#define TCE0_CCC _SFR_MEM16(0x0A2C) -+#define TCE0_CCD _SFR_MEM16(0x0A2E) -+#define TCE0_PERBUF _SFR_MEM16(0x0A36) -+#define TCE0_CCABUF _SFR_MEM16(0x0A38) -+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* VPORT - Virtual Ports */ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* CLK.USBCTRL bit masks and bit positions */ -+#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -+#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -+#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -+#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -+#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -+#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -+#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -+#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ -+ -+#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -+#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -+#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ -+ -+#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_USB_bm 0x40 /* USB bit mask. */ -+#define PR_USB_bp 6 /* USB bit position. */ -+ -+#define PR_AES_bm 0x10 /* AES bit mask. */ -+#define PR_AES_bp 4 /* AES bit position. */ -+ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -+#define PR_DMA_bp 0 /* DMA-Controller bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -+#define PR_USART1_bp 5 /* Port C USART1 bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -+#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ -+ -+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -+ -+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ -+ -+/* PR.PRPD bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPE bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPF bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -+#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -+#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ -+ -+#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ -+ -+#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -+#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.ANAINIT bit masks and bit positions */ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.AWEXLOCK bit masks and bit positions */ -+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* PORTCFG - Port Configuration */ -+/* PORTCFG.VPCTRLA bit masks and bit positions */ -+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ -+ -+/* PORTCFG.VPCTRLB bit masks and bit positions */ -+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ -+ -+/* PORTCFG.CLKEVOUT bit masks and bit positions */ -+#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ -+ -+#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -+#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -+#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -+#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -+#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -+#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ -+ -+#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -+#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ -+ -+#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -+#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ -+ -+/* PORTCFG.EVOUTSEL bit masks and bit positions */ -+#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -+#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -+#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -+#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -+#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -+#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -+#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -+#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0x7F /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ -+ -+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ -+ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -+#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -+#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -+#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -+#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -+#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -+#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -+#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -+#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -+#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ -+ -+#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -+#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -+#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -+#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -+#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -+#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -+#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -+#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -+#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -+#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -+#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* RTC - Real-Time Counter */ -+/* RTC.CTRL bit masks and bit positions */ -+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ -+ -+/* RTC.STATUS bit masks and bit positions */ -+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC.INTCTRL bit masks and bit positions */ -+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC.INTFLAGS bit masks and bit positions */ -+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* USB - USB */ -+/* USB_EP.STATUS bit masks and bit positions */ -+#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -+#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ -+ -+#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -+#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ -+ -+#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -+#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ -+ -+#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -+#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ -+ -+#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -+#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ -+ -+#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -+#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ -+ -+#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -+#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ -+ -+#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -+#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ -+ -+#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ -+ -+#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ -+ -+#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -+#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ -+ -+/* USB_EP.CTRL bit masks and bit positions */ -+#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -+#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -+#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -+#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -+#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -+#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ -+ -+#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -+#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ -+ -+#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -+#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ -+ -+#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -+#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ -+ -+#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -+#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ -+ -+#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -+#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -+#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -+#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -+#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -+#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -+#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -+#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ -+ -+/* USB_EP.CNT bit masks and bit positions */ -+#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -+#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ -+ -+/* USB.CTRLA bit masks and bit positions */ -+#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -+#define USB_ENABLE_bp 7 /* USB Enable bit position. */ -+ -+#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -+#define USB_SPEED_bp 6 /* Speed Select bit position. */ -+ -+#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -+#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ -+ -+#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -+#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ -+ -+#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -+#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -+#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -+#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -+#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -+#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -+#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -+#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -+#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -+#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ -+ -+/* USB.CTRLB bit masks and bit positions */ -+#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -+#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ -+ -+#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -+#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ -+ -+#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -+#define USB_GNACK_bp 1 /* Global NACK bit position. */ -+ -+#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -+#define USB_ATTACH_bp 0 /* Attach bit position. */ -+ -+/* USB.STATUS bit masks and bit positions */ -+#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -+#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ -+ -+#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -+#define USB_RESUME_bp 2 /* Resume bit position. */ -+ -+#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -+#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ -+ -+#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -+#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ -+ -+/* USB.ADDR bit masks and bit positions */ -+#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -+#define USB_ADDR_gp 0 /* Device Address group position. */ -+#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -+#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -+#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -+#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -+#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -+#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -+#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -+#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -+#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -+#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -+#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -+#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -+#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -+#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ -+ -+/* USB.FIFOWP bit masks and bit positions */ -+#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -+#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -+#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -+#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -+#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -+#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -+#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -+#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -+#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -+#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -+#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -+#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ -+ -+/* USB.FIFORP bit masks and bit positions */ -+#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -+#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -+#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -+#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -+#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -+#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -+#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -+#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -+#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -+#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -+#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -+#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ -+ -+/* USB.INTCTRLA bit masks and bit positions */ -+#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -+#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ -+ -+#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -+#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ -+ -+#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -+#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ -+ -+#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -+#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ -+ -+#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* USB.INTCTRLB bit masks and bit positions */ -+#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -+#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ -+ -+#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -+#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ -+ -+/* USB.INTFLAGSACLR bit masks and bit positions */ -+#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -+#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ -+ -+#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -+#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ -+ -+#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -+#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ -+ -+#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -+#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ -+ -+#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -+#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ -+ -+#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -+#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ -+ -+#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -+#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ -+ -+#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -+#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSASET bit masks and bit positions */ -+/* USB_SOFIF Predefined. */ -+/* USB_SOFIF Predefined. */ -+ -+/* USB_SUSPENDIF Predefined. */ -+/* USB_SUSPENDIF Predefined. */ -+ -+/* USB_RESUMEIF Predefined. */ -+/* USB_RESUMEIF Predefined. */ -+ -+/* USB_RSTIF Predefined. */ -+/* USB_RSTIF Predefined. */ -+ -+/* USB_CRCIF Predefined. */ -+/* USB_CRCIF Predefined. */ -+ -+/* USB_UNFIF Predefined. */ -+/* USB_UNFIF Predefined. */ -+ -+/* USB_OVFIF Predefined. */ -+/* USB_OVFIF Predefined. */ -+ -+/* USB_STALLIF Predefined. */ -+/* USB_STALLIF Predefined. */ -+ -+/* USB.INTFLAGSBCLR bit masks and bit positions */ -+#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -+#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ -+ -+#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -+#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSBSET bit masks and bit positions */ -+/* USB_TRNIF Predefined. */ -+/* USB_TRNIF Predefined. */ -+ -+/* USB_SETUPIF Predefined. */ -+/* USB_SETUPIF Predefined. */ -+ -+/* PORT - I/O Port Configuration */ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ -+ -+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -+#define PORT_SPI_bp 5 /* SPI bit position. */ -+ -+#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -+#define PORT_USART0_bp 4 /* USART0 bit position. */ -+ -+#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -+#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ -+ -+#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -+#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ -+ -+#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -+#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ -+ -+#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -+#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ -+ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC0.CTRLA bit masks and bit positions */ -+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC0.CTRLB bit masks and bit positions */ -+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ -+ -+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ -+ -+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC0.CTRLC bit masks and bit positions */ -+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ -+ -+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ -+ -+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC0.CTRLD bit masks and bit positions */ -+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC0_EVACT_gp 5 /* Event Action group position. */ -+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC0.CTRLE bit masks and bit positions */ -+#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC0.INTCTRLA bit masks and bit positions */ -+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC0.INTCTRLB bit masks and bit positions */ -+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ -+ -+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ -+ -+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC0.CTRLFCLR bit masks and bit positions */ -+#define TC0_CMD_gm 0x0C /* Command group mask. */ -+#define TC0_CMD_gp 2 /* Command group position. */ -+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC0_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC0_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC0_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC0.CTRLFSET bit masks and bit positions */ -+/* TC0_CMD Predefined. */ -+/* TC0_CMD Predefined. */ -+ -+/* TC0_LUPD Predefined. */ -+/* TC0_LUPD Predefined. */ -+ -+/* TC0_DIR Predefined. */ -+/* TC0_DIR Predefined. */ -+ -+/* TC0.CTRLGCLR bit masks and bit positions */ -+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ -+ -+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ -+ -+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC0.CTRLGSET bit masks and bit positions */ -+/* TC0_CCDBV Predefined. */ -+/* TC0_CCDBV Predefined. */ -+ -+/* TC0_CCCBV Predefined. */ -+/* TC0_CCCBV Predefined. */ -+ -+/* TC0_CCBBV Predefined. */ -+/* TC0_CCBBV Predefined. */ -+ -+/* TC0_CCABV Predefined. */ -+/* TC0_CCABV Predefined. */ -+ -+/* TC0_PERBV Predefined. */ -+/* TC0_PERBV Predefined. */ -+ -+/* TC0.INTFLAGS bit masks and bit positions */ -+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ -+ -+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ -+ -+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC1.CTRLA bit masks and bit positions */ -+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC1.CTRLB bit masks and bit positions */ -+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC1.CTRLC bit masks and bit positions */ -+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC1.CTRLD bit masks and bit positions */ -+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC1_EVACT_gp 5 /* Event Action group position. */ -+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC1.CTRLE bit masks and bit positions */ -+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ -+ -+/* TC1.INTCTRLA bit masks and bit positions */ -+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC1.INTCTRLB bit masks and bit positions */ -+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC1.CTRLFCLR bit masks and bit positions */ -+#define TC1_CMD_gm 0x0C /* Command group mask. */ -+#define TC1_CMD_gp 2 /* Command group position. */ -+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC1_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC1_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC1_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC1.CTRLFSET bit masks and bit positions */ -+/* TC1_CMD Predefined. */ -+/* TC1_CMD Predefined. */ -+ -+/* TC1_LUPD Predefined. */ -+/* TC1_LUPD Predefined. */ -+ -+/* TC1_DIR Predefined. */ -+/* TC1_DIR Predefined. */ -+ -+/* TC1.CTRLGCLR bit masks and bit positions */ -+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC1.CTRLGSET bit masks and bit positions */ -+/* TC1_CCBBV Predefined. */ -+/* TC1_CCBBV Predefined. */ -+ -+/* TC1_CCABV Predefined. */ -+/* TC1_CCABV Predefined. */ -+ -+/* TC1_PERBV Predefined. */ -+/* TC1_PERBV Predefined. */ -+ -+/* TC1.INTFLAGS bit masks and bit positions */ -+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+/* TC2.CTRLA bit masks and bit positions */ -+#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC2.CTRLB bit masks and bit positions */ -+#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -+#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ -+ -+#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -+#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ -+ -+#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -+#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ -+ -+#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -+#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ -+ -+#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -+#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ -+ -+#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -+#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ -+ -+#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -+#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ -+ -+#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -+#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ -+ -+/* TC2.CTRLC bit masks and bit positions */ -+#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -+#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ -+ -+#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -+#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ -+ -+#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -+#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ -+ -+#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -+#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ -+ -+#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -+#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ -+ -+#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -+#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ -+ -+#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -+#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ -+ -+#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -+#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ -+ -+/* TC2.CTRLE bit masks and bit positions */ -+#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC2.INTCTRLA bit masks and bit positions */ -+#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -+#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -+#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -+#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -+#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -+#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ -+ -+#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -+#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -+#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -+#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -+#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -+#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ -+ -+/* TC2.INTCTRLB bit masks and bit positions */ -+#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -+#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -+#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -+#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -+#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -+#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -+#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -+#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -+#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -+#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -+#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -+#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -+#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -+#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -+#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -+#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -+#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -+#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -+#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -+#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -+#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ -+ -+/* TC2.CTRLF bit masks and bit positions */ -+#define TC2_CMD_gm 0x0C /* Command group mask. */ -+#define TC2_CMD_gp 2 /* Command group position. */ -+#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC2_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -+#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -+#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -+#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -+#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -+#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ -+ -+/* TC2.INTFLAGS bit masks and bit positions */ -+#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -+#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ -+ -+#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -+#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ -+ -+#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -+#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ -+ -+#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -+#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ -+ -+#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ -+ -+#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ -+ -+/* AWEX - Timer/Counter Advanced Waveform Extension */ -+/* AWEX.CTRL bit masks and bit positions */ -+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ -+ -+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ -+ -+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ -+ -+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ -+ -+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ -+ -+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ -+ -+/* AWEX.FDCTRL bit masks and bit positions */ -+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ -+ -+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ -+ -+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ -+ -+/* AWEX.STATUS bit masks and bit positions */ -+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ -+ -+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ -+ -+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ -+ -+/* AWEX.STATUSSET bit masks and bit positions */ -+/* AWEX_FDF Predefined. */ -+/* AWEX_FDF Predefined. */ -+ -+/* AWEX_DTHSBUFV Predefined. */ -+/* AWEX_DTHSBUFV Predefined. */ -+ -+/* AWEX_DTLSBUFV Predefined. */ -+/* AWEX_DTLSBUFV Predefined. */ -+ -+/* HIRES - Timer/Counter High-Resolution Extension */ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -+#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* LOCKBIT - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT0_vect_num 2 -+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -+#define PORTC_INT1_vect_num 3 -+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT0_vect_num 4 -+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -+#define PORTR_INT1_vect_num 5 -+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ -+ -+/* RTC interrupt vectors */ -+#define RTC_OVF_vect_num 10 -+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -+#define RTC_COMP_vect_num 11 -+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 12 -+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 13 -+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_OVF_vect_num 14 -+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LUNF_vect_num 14 -+#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_ERR_vect_num 15 -+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_HUNF_vect_num 15 -+#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCA_vect_num 16 -+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPA_vect_num 16 -+#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCB_vect_num 17 -+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPB_vect_num 17 -+#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCC_vect_num 18 -+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPC_vect_num 18 -+#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCD_vect_num 19 -+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPD_vect_num 19 -+#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ -+ -+/* TCC1 interrupt vectors */ -+#define TCC1_OVF_vect_num 20 -+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -+#define TCC1_ERR_vect_num 21 -+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -+#define TCC1_CCA_vect_num 22 -+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -+#define TCC1_CCB_vect_num 23 -+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 24 -+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 25 -+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 26 -+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 27 -+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ -+ -+/* USARTC1 interrupt vectors */ -+#define USARTC1_RXC_vect_num 28 -+#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -+#define USARTC1_DRE_vect_num 29 -+#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -+#define USARTC1_TXC_vect_num 30 -+#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 32 -+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -+#define NVM_SPM_vect_num 33 -+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ -+ -+/* PORTB interrupt vectors */ -+#define PORTB_INT0_vect_num 34 -+#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -+#define PORTB_INT1_vect_num 35 -+#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ -+ -+/* PORTE interrupt vectors */ -+#define PORTE_INT0_vect_num 43 -+#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -+#define PORTE_INT1_vect_num 44 -+#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ -+ -+/* TWIE interrupt vectors */ -+#define TWIE_TWIS_vect_num 45 -+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -+#define TWIE_TWIM_vect_num 46 -+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_OVF_vect_num 47 -+#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -+#define TCE0_ERR_vect_num 48 -+#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -+#define TCE0_CCA_vect_num 49 -+#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -+#define TCE0_CCB_vect_num 50 -+#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -+#define TCE0_CCC_vect_num 51 -+#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -+#define TCE0_CCD_vect_num 52 -+#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT0_vect_num 64 -+#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -+#define PORTD_INT1_vect_num 65 -+#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ -+ -+/* PORTA interrupt vectors */ -+#define PORTA_INT0_vect_num 66 -+#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -+#define PORTA_INT1_vect_num 67 -+#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ -+ -+/* ACA interrupt vectors */ -+#define ACA_AC0_vect_num 68 -+#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -+#define ACA_AC1_vect_num 69 -+#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -+#define ACA_ACW_vect_num 70 -+#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ -+ -+/* ADCA interrupt vectors */ -+#define ADCA_CH0_vect_num 71 -+#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_OVF_vect_num 77 -+#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LUNF_vect_num 77 -+#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_ERR_vect_num 78 -+#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_HUNF_vect_num 78 -+#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCA_vect_num 79 -+#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPA_vect_num 79 -+#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCB_vect_num 80 -+#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPB_vect_num 80 -+#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCC_vect_num 81 -+#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPC_vect_num 81 -+#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCD_vect_num 82 -+#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPD_vect_num 82 -+#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ -+ -+/* SPID interrupt vectors */ -+#define SPID_INT_vect_num 87 -+#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ -+ -+/* USARTD0 interrupt vectors */ -+#define USARTD0_RXC_vect_num 88 -+#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -+#define USARTD0_DRE_vect_num 89 -+#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -+#define USARTD0_TXC_vect_num 90 -+#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ -+ -+/* USB interrupt vectors */ -+#define USB_BUSEVENT_vect_num 125 -+#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -+#define USB_TRNCOMPL_vect_num 126 -+#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (127 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (20480) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (16384) -+#define APP_SECTION_PAGE_SIZE (256) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0x3000) -+#define APPTABLE_SECTION_SIZE (4096) -+#define APPTABLE_SECTION_PAGE_SIZE (256) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x4000) -+#define BOOT_SECTION_SIZE (4096) -+#define BOOT_SECTION_PAGE_SIZE (256) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (10240) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (1024) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (2048) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (1024) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (6) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (256) -+#define USER_SIGNATURES_PAGE_SIZE (256) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (64) -+#define PROD_SIGNATURES_PAGE_SIZE (256) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 256 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 6 -+ -+/* Fuse Byte 0 Reserved */ -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x94 -+#define SIGNATURE_2 0x43 -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA16C4_H_INCLUDED */ -+ -diff --git a/include/avr/iox16d4.h b/include/avr/iox16d4.h -index 7518428..94dee02 100644 ---- a/include/avr/iox16d4.h -+++ b/include/avr/iox16d4.h -@@ -434,6 +434,42 @@ typedef struct PMIC_struct - - /* - -------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- - EVSYS - Event System - -------------------------------------------------------------------------- - */ -@@ -1077,6 +1113,7 @@ typedef enum ADC_CH_GAIN_enum - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ - } ADC_CH_GAIN_t; - - /* Conversion result resolution */ -@@ -1087,6 +1124,14 @@ typedef enum ADC_RESOLUTION_enum - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ - } ADC_RESOLUTION_t; - -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ -+} ADC_CURRLIMIT_t; -+ - /* Voltage reference selection */ - typedef enum ADC_REFSEL_enum - { -@@ -2204,6 +2249,7 @@ IO Module Instances. Mapped to memory. - #define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ - #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ - #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ - #define PORTA (*(PORT_t *) 0x0600) /* Port A */ - #define PORTB (*(PORT_t *) 0x0620) /* Port B */ - #define PORTC (*(PORT_t *) 0x0640) /* Port C */ -@@ -2454,6 +2500,23 @@ IO Module Instances. Mapped to memory. - #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) - #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -+/* TWIE - Two-Wire Interface E */ -+#define TWIE_CTRL _SFR_MEM8(0x04A0) -+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -+ -+ - /* PORTA - Port A */ - #define PORTA_DIR _SFR_MEM8(0x0600) - #define PORTA_DIRSET _SFR_MEM8(0x0601) -@@ -3841,6 +3904,8 @@ IO Module Instances. Mapped to memory. - #define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ - #define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ - #define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ -+#define ADC_CH_MUXPOS4_bm (1<<7) /* Positive Input Select bit 3 mask. */ -+#define ADC_CH_MUXPOS4_bp 7 /* Positive Input Select bit 3 position. */ - - #define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ - #define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ -@@ -3894,6 +3959,13 @@ IO Module Instances. Mapped to memory. - - - /* ADC.CTRLB bit masks and bit positions */ -+#define ADC_IMPMODE_bm 0x80 /* Impedance Mode bit mask. */ -+#define ADC_IMPMODE_bp 7 /* Impedance Mode bit position. */ -+ -+#define ADC_CURRENT_bm 0x60 /* Current bit mask. */ -+#define ADC_CURRENT1_bp 6 /* Current bit position. */ -+#define ADC_CURRENT0_bp 5 /* Current bit position. */ -+ - #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ - #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -@@ -3909,12 +3981,14 @@ IO Module Instances. Mapped to memory. - - - /* ADC.REFCTRL bit masks and bit positions */ --#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ - #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ - #define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ - #define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ - #define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ - #define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - - #define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ - #define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -@@ -5367,6 +5441,12 @@ IO Module Instances. Mapped to memory. - #define PORTE_INT1_vect_num 44 - #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -+/* TWIE interrupt vectors */ -+#define TWIE_TWIS_vect_num 45 -+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -+#define TWIE_TWIM_vect_num 46 -+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ -+ - /* TCE0 interrupt vectors */ - #define TCE0_OVF_vect_num 47 - #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -diff --git a/include/avr/iox16e5.h b/include/avr/iox16e5.h -new file mode 100644 -index 0000000..c417a88 ---- /dev/null -+++ b/include/avr/iox16e5.h -@@ -0,0 +1,7664 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox16e5.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA16E5_H_INCLUDED -+#define _AVR_ATXMEGA16E5_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+VPORT - Virtual Ports -+-------------------------------------------------------------------------- -+*/ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t reserved_0x04; -+} CLK_t; -+ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t reserved_0x02; -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t PRPD; /* Power Reduction Port D */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+} PR_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+ CLK_SCLKSEL_RC8M_gc = (0x05<<0), /* Internal 8 MHz RC Oscillator */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+ CLK_PSADIV_6_gc = (0x13<<2), /* Divide by 6 */ -+ CLK_PSADIV_10_gc = (0x15<<2), /* Divide by 10 */ -+ CLK_PSADIV_12_gc = (0x17<<2), /* Divide by 12 */ -+ CLK_PSADIV_24_gc = (0x19<<2), /* Divide by 24 */ -+ CLK_PSADIV_48_gc = (0x1B<<2), /* Divide by 48 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control Register */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+ register8_t RC8MCAL; /* Internal 8 MHz RC Oscillator Calibration Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -+ OSC_XOSCSEL_EXTCLK_C4_gc = (0x14<<0), /* External Clock on port C4 - 6 CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ -+ OSC_PLLSRC_RC8M_gc = (0x01<<6), /* Internal 8 MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+/* 32 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC32MCREF_enum -+{ -+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC32MCREF_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t ANAINIT; /* Analog Startup Delay */ -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t WEXLOCK; /* WEX Lock */ -+ register8_t FAULTLOCK; /* FAULT Lock */ -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORTCFG - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t reserved_0x02; -+ register8_t reserved_0x03; -+ register8_t CLKOUT; /* Clock Out Register */ -+ register8_t reserved_0x05; -+ register8_t ACEVOUT; /* Analog Comparator and Event Out Register */ -+ register8_t SRLCTRL; /* Slew Rate Limit Control Register */ -+} PORTCFG_t; -+ -+/* Clock and Event Output Port */ -+typedef enum PORTCFG_CLKEVPIN_enum -+{ -+ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ -+ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -+} PORTCFG_CLKEVPIN_t; -+ -+/* RTC Clock Output Port */ -+typedef enum PORTCFG_RTCCLKOUT_enum -+{ -+ PORTCFG_RTCCLKOUT_OFF_gc = (0x00<<5), /* System Clock Output Disabled */ -+ PORTCFG_RTCCLKOUT_PC6_gc = (0x01<<5), /* System Clock Output on Port C pin 6 */ -+ PORTCFG_RTCCLKOUT_PD6_gc = (0x02<<5), /* System Clock Output on Port D pin 6 */ -+ PORTCFG_RTCCLKOUT_PR0_gc = (0x03<<5), /* System Clock Output on Port R pin 0 */ -+} PORTCFG_RTCCLKOUT_t; -+ -+/* Peripheral Clock Output Select */ -+typedef enum PORTCFG_CLKOUTSEL_enum -+{ -+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -+} PORTCFG_CLKOUTSEL_t; -+ -+/* System Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ -+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ -+ PORTCFG_CLKOUT_PR0_gc = (0x03<<0), /* System Clock Output on Port R pin 0 */ -+} PORTCFG_CLKOUT_t; -+ -+/* Analog Comparator Output Port */ -+typedef enum PORTCFG_ACOUT_enum -+{ -+ PORTCFG_ACOUT_PA_gc = (0x00<<6), /* Analog Comparator Outputs on Port A, Pin 6-7 */ -+ PORTCFG_ACOUT_PC_gc = (0x01<<6), /* Analog Comparator Outputs on Port C, Pin 6-7 */ -+ PORTCFG_ACOUT_PD_gc = (0x02<<6), /* Analog Comparator Outputs on Port D, Pin 6-7 */ -+ PORTCFG_ACOUT_PR_gc = (0x03<<6), /* Analog Comparator Outputs on Port R, Pin 0-1 */ -+} PORTCFG_ACOUT_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel n Output on Port C pin 7 */ -+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel n Output on Port D pin 7 */ -+ PORTCFG_EVOUT_PR0_gc = (0x03<<4), /* Event Channel n Output on Port R pin 0 */ -+} PORTCFG_EVOUT_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -+ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ -+ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ -+ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ -+ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ -+ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ -+ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ -+ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EDMA - Enhanced DMA Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* EDMA Channel */ -+typedef struct EDMA_CH_struct -+{ -+ register8_t CTRLA; /* Channel Control A */ -+ register8_t CTRLB; /* Channel Control */ -+ register8_t ADDRCTRL; /* Memory Address Control for Peripheral Ch., or Source Address Control for Standard Ch. */ -+ register8_t DESTADDRCTRL; /* Destination Address Control for Standard Channels Only. */ -+ register8_t TRIGSRC; /* Channel Trigger Source */ -+ register8_t reserved_0x05; -+ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch. */ -+ _WORDREGISTER(ADDR); /* Channel Memory Address for Peripheral Ch., or Channel Source Address Low for Standard Ch. */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(DESTADDR); /* Channel Destination Address for Standard Channels Only. */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} EDMA_CH_t; -+ -+ -+/* Enhanced DMA Controller */ -+typedef struct EDMA_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t reserved_0x01; -+ register8_t reserved_0x02; -+ register8_t INTFLAGS; /* Transfer Interrupt Status */ -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x05; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ EDMA_CH_t CH0; /* EDMA Channel 0 */ -+ EDMA_CH_t CH1; /* EDMA Channel 1 */ -+ EDMA_CH_t CH2; /* EDMA Channel 2 */ -+ EDMA_CH_t CH3; /* EDMA Channel 3 */ -+} EDMA_t; -+ -+/* Channel mode */ -+typedef enum EDMA_CHMODE_enum -+{ -+ EDMA_CHMODE_PER0123_gc = (0x00<<4), /* Channels 0, 1, 2 and 3 in peripheal conf. */ -+ EDMA_CHMODE_STD0_gc = (0x01<<4), /* Channel 0 in standard conf.; channels 2 and 3 in peripheral conf. */ -+ EDMA_CHMODE_STD2_gc = (0x02<<4), /* Channel 2 in standard conf.; channels 0 and 1 in peripheral conf. */ -+ EDMA_CHMODE_STD02_gc = (0x03<<4), /* Channels 0 and 2 in standard conf. */ -+} EDMA_CHMODE_t; -+ -+/* Double buffer mode */ -+typedef enum EDMA_DBUFMODE_enum -+{ -+ EDMA_DBUFMODE_DISABLE_gc = (0x00<<2), /* No double buffer enabled */ -+ EDMA_DBUFMODE_BUF01_gc = (0x01<<2), /* Double buffer enabled on peripheral channels 0/1 (if exist) */ -+ EDMA_DBUFMODE_BUF23_gc = (0x02<<2), /* Double buffer enabled on peripheral channels 2/3 (if exist) */ -+ EDMA_DBUFMODE_BUF0123_gc = (0x03<<2), /* Double buffer enabled on peripheral channels 0/1 and 2/3 or standard channels 0/2 */ -+} EDMA_DBUFMODE_t; -+ -+/* Priority mode */ -+typedef enum EDMA_PRIMODE_enum -+{ -+ EDMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round robin on all channels */ -+ EDMA_PRIMODE_RR123_gc = (0x01<<0), /* Ch0 > round robin (Ch 1 ch2 Ch3) */ -+ EDMA_PRIMODE_RR23_gc = (0x02<<0), /* Ch0 > Ch 1 > round robin (Ch2 Ch3) */ -+ EDMA_PRIMODE_CH0123_gc = (0x03<<0), /* Ch0 > Ch1 > Ch2 > Ch3 */ -+} EDMA_PRIMODE_t; -+ -+/* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. */ -+typedef enum EDMA_CH_RELOAD_enum -+{ -+ EDMA_CH_RELOAD_NONE_gc = (0x00<<4), /* No reload */ -+ EDMA_CH_RELOAD_BLOCK_gc = (0x01<<4), /* Reload at end of each block transfer */ -+ EDMA_CH_RELOAD_BURST_gc = (0x02<<4), /* Reload at end of each burst transfer */ -+ EDMA_CH_RELOAD_TRANSACTION_gc = (0x03<<4), /* Reload at end of each transaction */ -+} EDMA_CH_RELOAD_t; -+ -+/* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. */ -+typedef enum EDMA_CH_DIR_enum -+{ -+ EDMA_CH_DIR_FIXED_gc = (0x00<<0), /* Fixed */ -+ EDMA_CH_DIR_INC_gc = (0x01<<0), /* Increment */ -+ EDMA_CH_DIR_MP1_gc = (0x04<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'mask-match' (data: ADDRL, mask: ADDRH), else reserved conf. */ -+ EDMA_CH_DIR_MP2_gc = (0x05<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH), else reserved conf. */ -+ EDMA_CH_DIR_MP3_gc = (0x06<<0), /* If Peripheral Ch. (Per ==> Mem), 2-byte 'match' (data-1: ADDRL followed by data-2: ADDRH), else reserved conf. */ -+} EDMA_CH_DIR_t; -+ -+/* Destination addressing mode */ -+typedef enum EDMA_CH_DESTDIR_enum -+{ -+ EDMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ -+ EDMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ -+ EDMA_CH_DESTDIR_MP1_gc = (0x04<<0), /* 1-byte 'mask-match' (data: ADDRL, mask: ADDRH) */ -+ EDMA_CH_DESTDIR_MP2_gc = (0x05<<0), /* 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH) */ -+ EDMA_CH_DESTDIR_MP3_gc = (0x06<<0), /* 2-byte 'match' (data1: ADDRL followed by data2: ADDRH) */ -+} EDMA_CH_DESTDIR_t; -+ -+/* Transfer trigger source */ -+typedef enum EDMA_CH_TRIGSRC_enum -+{ -+ EDMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Software triggers only */ -+ EDMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event CH0 as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event CH1 as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event CH2 as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA CH0 as trigger */ -+ EDMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA CH0 as trigger */ -+ EDMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA CH1 as trigger */ -+ EDMA_CH_TRIGSRC_TCC4_OVF_gc = (0x40<<0), /* TCC4 overflow/underflow as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCC4_ERR_gc = (0x41<<0), /* TCC4 error as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCC4_CCA_gc = (0x42<<0), /* TCC4 compare or capture channel A as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCC4_CCB_gc = (0x43<<0), /* TCC4 compare or capture channel B as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCC4_CCC_gc = (0x44<<0), /* TCC4 compare or capture channel C as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCC4_CCD_gc = (0x45<<0), /* TCC4 compare or capture channel D as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCC5_OVF_gc = (0x46<<0), /* TCC5 overflow/underflow as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCC5_ERR_gc = (0x47<<0), /* TCC5 error as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCC5_CCA_gc = (0x48<<0), /* TCC5 compare or capture channel A as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCC5_CCB_gc = (0x49<<0), /* TCC5 compare or capture channel B as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_SPIC_RXC_gc = (0x4A<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C receive complete as trigger (SPI Buffer Modes) */ -+ EDMA_CH_TRIGSRC_SPIC_DRE_gc = (0x4B<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C data register empty as trigger (SPI Buffer modes) */ -+ EDMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4C<<0), /* USART C0 receive complete as trigger */ -+ EDMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4D<<0), /* USART C0 data register empty as trigger */ -+ EDMA_CH_TRIGSRC_TCD5_OVF_gc = (0x66<<0), /* TCD5 overflow/underflow as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCD5_ERR_gc = (0x67<<0), /* TCD5 error as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCD5_CCA_gc = (0x68<<0), /* TCD5 compare or capture channel A as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCD5_CCB_gc = (0x69<<0), /* TCD5 compare or capture channel B as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6C<<0), /* USART D0 receive complete as trigger */ -+ EDMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6D<<0), /* USART D0 data register empty as trigger */ -+} EDMA_CH_TRIGSRC_t; -+ -+/* Interrupt level */ -+typedef enum EDMA_CH_INTLVL_enum -+{ -+ EDMA_CH_INTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ EDMA_CH_INTLVL_LO_gc = (0x01<<2), /* Low level */ -+ EDMA_CH_INTLVL_MED_gc = (0x02<<2), /* Medium level */ -+ EDMA_CH_INTLVL_HI_gc = (0x03<<2), /* High level */ -+} EDMA_CH_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ -+ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ -+ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ -+ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t CH4CTRL; /* Channel 4 Control Register */ -+ register8_t CH5CTRL; /* Channel 5 Control Register */ -+ register8_t CH6CTRL; /* Channel 6 Control Register */ -+ register8_t CH7CTRL; /* Channel 7 Control Register */ -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+ register8_t DFCTRL; /* Digital Filter Control Register */ -+} EVSYS_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ -+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ -+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ -+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ -+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_XCL_UNF0_gc = (0xB0<<0), /* XCL BTC0 underflow */ -+ EVSYS_CHMUX_XCL_UNF1_gc = (0xB1<<0), /* XCL BTC1 underflow */ -+ EVSYS_CHMUX_XCL_CC0_gc = (0xB2<<0), /* XCL BTC0 capture or compare */ -+ EVSYS_CHMUX_XCL_CC1_gc = (0xB3<<0), /* XCL BTC0 capture or compare */ -+ EVSYS_CHMUX_XCL_PEC0_gc = (0xB4<<0), /* XCL PEC0 restart */ -+ EVSYS_CHMUX_XCL_PEC1_gc = (0xB5<<0), /* XCL PEC1 restart */ -+ EVSYS_CHMUX_XCL_LUT0_gc = (0xB6<<0), /* XCL LUT0 output */ -+ EVSYS_CHMUX_XCL_LUT1_gc = (0xB7<<0), /* XCL LUT1 output */ -+ EVSYS_CHMUX_TCC4_OVF_gc = (0xC0<<0), /* Timer/Counter C4 Overflow */ -+ EVSYS_CHMUX_TCC4_ERR_gc = (0xC1<<0), /* Timer/Counter C4 Error */ -+ EVSYS_CHMUX_TCC4_CCA_gc = (0xC4<<0), /* Timer/Counter C4 Compare or Capture A */ -+ EVSYS_CHMUX_TCC4_CCB_gc = (0xC5<<0), /* Timer/Counter C4 Compare or Capture B */ -+ EVSYS_CHMUX_TCC4_CCC_gc = (0xC6<<0), /* Timer/Counter C4 Compare or Capture C */ -+ EVSYS_CHMUX_TCC4_CCD_gc = (0xC7<<0), /* Timer/Counter C4 Compare or Capture D */ -+ EVSYS_CHMUX_TCC5_OVF_gc = (0xC8<<0), /* Timer/Counter C5 Overflow */ -+ EVSYS_CHMUX_TCC5_ERR_gc = (0xC9<<0), /* Timer/Counter C5 Error */ -+ EVSYS_CHMUX_TCC5_CCA_gc = (0xCC<<0), /* Timer/Counter C5 Compare or Capture A */ -+ EVSYS_CHMUX_TCC5_CCB_gc = (0xCD<<0), /* Timer/Counter C5 Compare or Capture B */ -+ EVSYS_CHMUX_TCD5_OVF_gc = (0xD8<<0), /* Timer/Counter D5 Overflow */ -+ EVSYS_CHMUX_TCD5_ERR_gc = (0xD9<<0), /* Timer/Counter D5 Error */ -+ EVSYS_CHMUX_TCD5_CCA_gc = (0xDC<<0), /* Timer/Counter D5 Compare or Capture A */ -+ EVSYS_CHMUX_TCD5_CCB_gc = (0xDD<<0), /* Timer/Counter D5 Compare or Capture B */ -+} EVSYS_CHMUX_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Prescaler Filter */ -+typedef enum EVSYS_PRESCFILT_enum -+{ -+ EVSYS_PRESCFILT_CH04_gc = (0x01<<4), /* Enable prescaler filter for either channel 0 or 4 */ -+ EVSYS_PRESCFILT_CH15_gc = (0x02<<4), /* Enable prescaler filter for either channel 1 or 5 */ -+ EVSYS_PRESCFILT_CH26_gc = (0x04<<4), /* Enable prescaler filter for either channel 2 or 6 */ -+ EVSYS_PRESCFILT_CH37_gc = (0x08<<4), /* Enable prescaler filter for either channel 3 or 7 */ -+} EVSYS_PRESCFILT_t; -+ -+/* Prescaler */ -+typedef enum EVSYS_PRESCALER_enum -+{ -+ EVSYS_PRESCALER_CLKPER_8_gc = (0x00<<0), /* CLKPER, divide by 8 */ -+ EVSYS_PRESCALER_CLKPER_64_gc = (0x01<<0), /* CLKPER, divide by 64 */ -+ EVSYS_PRESCALER_CLKPER_512_gc = (0x02<<0), /* CLKPER, divide by 512 */ -+ EVSYS_PRESCALER_CLKPER_4096_gc = (0x03<<0), /* CLKPER, divide by 4096 */ -+ EVSYS_PRESCALER_CLKPER_32768_gc = (0x04<<0), /* CLKPER, divide by 32768 */ -+} EVSYS_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ -+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ -+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ -+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ -+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} NVM_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t CORRCTRL; /* Correction Control Register */ -+ register8_t OFFSETCORR0; /* Offset Correction Register 0 */ -+ register8_t OFFSETCORR1; /* Offset Correction Register 1 */ -+ register8_t GAINCORR0; /* Gain Correction Register 0 */ -+ register8_t GAINCORR1; /* Gain Correction Register 1 */ -+ register8_t AVGCTRL; /* Average Control Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+} ADC_t; -+ -+/* Current Limitation */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -+} ADC_CURRLIMIT_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_MT12BIT_gc = (0x01<<1), /* More than 12-bit (oversapling) right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFD_gc = (0x03<<4), /* External reference on PORT D */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ -+ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ -+ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ -+ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -+ ADC_EVSEL_4_gc = (0x04<<3), /* Event Channel 4 */ -+ ADC_EVSEL_5_gc = (0x05<<3), /* Event Channel 5 */ -+ ADC_EVSEL_6_gc = (0x06<<3), /* Event Channel 6 */ -+ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel conversion */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAINL_gc = (0x02<<0), /* Differential input, gain with 4 LSB pins selection */ -+ ADC_CH_INPUTMODE_DIFFWGAINH_gc = (0x03<<0), /* Differential input, gain with 4 MSB pins selection */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 Scaled VCC */ -+ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC Output */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection when gain on 4 LSB pins */ -+typedef enum ADC_CH_MUXNEGL_enum -+{ -+ ADC_CH_MUXNEGL_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEGL_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEGL_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEGL_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEGL_GND_gc = (0x05<<0), /* PAD ground */ -+ ADC_CH_MUXNEGL_INTGND_gc = (0x07<<0), /* Internal ground */ -+} ADC_CH_MUXNEGL_t; -+ -+/* Negative input multiplexer selection when gain on 4 MSB pins */ -+typedef enum ADC_CH_MUXNEGH_enum -+{ -+ ADC_CH_MUXNEGH_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEGH_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEGH_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEGH_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+ ADC_CH_MUXNEGH_GND_gc = (0x05<<0), /* PAD ground */ -+} ADC_CH_MUXNEGH_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+} ADC_CH_MUXNEG_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* Averaged Number of Samples */ -+typedef enum ADC_SAMPNUM_enum -+{ -+ ADC_SAMPNUM_1X_gc = (0x00<<0), /* 1 Sample */ -+ ADC_SAMPNUM_2X_gc = (0x01<<0), /* 2 Samples */ -+ ADC_SAMPNUM_4X_gc = (0x02<<0), /* 4 Samples */ -+ ADC_SAMPNUM_8X_gc = (0x03<<0), /* 8 Samples */ -+ ADC_SAMPNUM_16X_gc = (0x04<<0), /* 16 Samples */ -+ ADC_SAMPNUM_32X_gc = (0x05<<0), /* 32 Samples */ -+ ADC_SAMPNUM_64X_gc = (0x06<<0), /* 64 Samples */ -+ ADC_SAMPNUM_128X_gc = (0x07<<0), /* 128 Samples */ -+ ADC_SAMPNUM_256X_gc = (0x08<<0), /* 256 Samples */ -+ ADC_SAMPNUM_512X_gc = (0x09<<0), /* 512 Samples */ -+ ADC_SAMPNUM_1024X_gc = (0x0A<<0), /* 1024 Samples */ -+} ADC_SAMPNUM_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DAC - Digital/Analog Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Digital-to-Analog Converter */ -+typedef struct DAC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t EVCTRL; /* Event Input Control */ -+ register8_t reserved_0x04; -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0GAINCAL; /* Gain Calibration */ -+ register8_t CH0OFFSETCAL; /* Offset Calibration */ -+ register8_t CH1GAINCAL; /* Gain Calibration */ -+ register8_t CH1OFFSETCAL; /* Offset Calibration */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ -+ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -+} DAC_t; -+ -+/* Output channel selection */ -+typedef enum DAC_CHSEL_enum -+{ -+ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ -+ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ -+ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -+} DAC_CHSEL_t; -+ -+/* Reference voltage selection */ -+typedef enum DAC_REFSEL_enum -+{ -+ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ -+ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ -+ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ -+ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -+} DAC_REFSEL_t; -+ -+/* Event channel selection */ -+typedef enum DAC_EVSEL_enum -+{ -+ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ -+ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ -+ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ -+ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ -+ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ -+ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ -+ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ -+ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -+} DAC_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+ register8_t CURRCTRL; /* Current Source Control Register */ -+ register8_t CURRCALIB; /* Current Source Calibration Register */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC - Real-Time Clounter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Real-Time Counter */ -+typedef struct RTC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary register */ -+ register8_t reserved_0x05; -+ register8_t CALIB; /* Calibration Register */ -+ register8_t reserved_0x07; -+ _WORDREGISTER(CNT); /* Count Register */ -+ _WORDREGISTER(PER); /* Period Register */ -+ _WORDREGISTER(COMP); /* Compare Register */ -+} RTC_t; -+ -+/* Prescaler Factor */ -+typedef enum RTC_PRESCALER_enum -+{ -+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ -+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ -+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ -+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ -+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ -+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ -+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ -+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -+} RTC_PRESCALER_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC_COMPINTLVL_enum -+{ -+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC_OVFINTLVL_enum -+{ -+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XCL - XMEGA Custom Logic -+-------------------------------------------------------------------------- -+*/ -+ -+/* XMEGA Custom Logic */ -+typedef struct XCL_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t CTRLF; /* Control Register F */ -+ register8_t CTRLG; /* Control Register G */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t PLC; /* Peripheral Lenght Control Register */ -+ register8_t CNTL; /* Counter Register Low */ -+ register8_t CNTH; /* Counter Register High */ -+ register8_t CMPL; /* Compare Register Low */ -+ register8_t CMPH; /* Compare Register High */ -+ register8_t PERCAPTL; /* Period or Capture Register Low */ -+ register8_t PERCAPTH; /* Period or Capture Register High */ -+} XCL_t; -+ -+/* LUT0 Output Enable */ -+typedef enum XCL_LUTOUTEN_enum -+{ -+ XCL_LUTOUTEN_DISABLE_gc = (0x00<<6), /* LUT0 output disabled */ -+ XCL_LUTOUTEN_PIN0_gc = (0x01<<6), /* LUT0 Output to pin 0 */ -+ XCL_LUTOUTEN_PIN4_gc = (0x02<<6), /* LUT0 Output to pin 4 */ -+} XCL_LUTOUTEN_t; -+ -+/* Port Selection */ -+typedef enum XCL_PORTSEL_enum -+{ -+ XCL_PORTSEL_PC_gc = (0x00<<4), /* Port C for LUT or USARTC0 for PEC */ -+ XCL_PORTSEL_PD_gc = (0x01<<4), /* Port D for LUT or USARTD0 for PEC */ -+} XCL_PORTSEL_t; -+ -+/* LUT Configuration */ -+typedef enum XCL_LUTCONF_enum -+{ -+ XCL_LUTCONF_2LUT2IN_gc = (0x00<<0), /* 2-Input two LUT */ -+ XCL_LUTCONF_2LUT1IN_gc = (0x01<<0), /* Two LUT with duplicated input */ -+ XCL_LUTCONF_2LUT3IN_gc = (0x02<<0), /* Two LUT with one common input */ -+ XCL_LUTCONF_1LUT3IN_gc = (0x03<<0), /* 3-Input LUT */ -+ XCL_LUTCONF_MUX_gc = (0x04<<0), /* One LUT Mux */ -+ XCL_LUTCONF_DLATCH_gc = (0x05<<0), /* One D-Latch LUT */ -+ XCL_LUTCONF_RSLATCH_gc = (0x06<<0), /* One RS-Latch LUT */ -+ XCL_LUTCONF_DFF_gc = (0x07<<0), /* One DFF LUT */ -+} XCL_LUTCONF_t; -+ -+/* Input Selection */ -+typedef enum XCL_INSEL_enum -+{ -+ XCL_INSEL_EVSYS_gc = (0x00<<6), /* Event system selected as source */ -+ XCL_INSEL_XCL_gc = (0x01<<6), /* XCL selected as source */ -+ XCL_INSEL_PINL_gc = (0x02<<6), /* LSB port pin selected as source */ -+ XCL_INSEL_PINH_gc = (0x03<<6), /* MSB port pin selected as source */ -+} XCL_INSEL_t; -+ -+/* Delay Configuration on LUT */ -+typedef enum XCL_DLYCONF_enum -+{ -+ XCL_DLYCONF_DISABLE_gc = (0x00<<2), /* Delay element disabled */ -+ XCL_DLYCONF_IN_gc = (0x01<<2), /* Delay enabled on LUT input */ -+ XCL_DLYCONF_OUT_gc = (0x02<<2), /* Delay enabled on LUT output */ -+} XCL_DLYCONF_t; -+ -+/* Delay Selection */ -+typedef enum XCL_DLYSEL_enum -+{ -+ XCL_DLYSEL_DLY11_gc = (0x00<<4), /* One cycle delay for each LUT1 and LUT0 */ -+ XCL_DLYSEL_DLY12_gc = (0x01<<4), /* One cycle delay for LUT1 and two cycles for LUT0 */ -+ XCL_DLYSEL_DLY21_gc = (0x02<<4), /* Two cycles delay for LUT1 and one cycle for LUT0 */ -+ XCL_DLYSEL_DLY22_gc = (0x03<<4), /* Two cycle delays for each LUT1 and LUT0 */ -+} XCL_DLYSEL_t; -+ -+/* Clock Selection */ -+typedef enum XCL_CLKSEL_enum -+{ -+ XCL_CLKSEL_OFF_gc = (0x00<<0), /* OFF */ -+ XCL_CLKSEL_DIV1_gc = (0x01<<0), /* Prescaler clk */ -+ XCL_CLKSEL_DIV2_gc = (0x02<<0), /* Prescaler clk/2 */ -+ XCL_CLKSEL_DIV4_gc = (0x03<<0), /* Prescaler clk/4 */ -+ XCL_CLKSEL_DIV8_gc = (0x04<<0), /* Prescaler clk/8 */ -+ XCL_CLKSEL_DIV64_gc = (0x05<<0), /* Prescaler clk/64 */ -+ XCL_CLKSEL_DIV256_gc = (0x06<<0), /* Prescaler clk/256 */ -+ XCL_CLKSEL_DIV1024_gc = (0x07<<0), /* Prescaler clk/1024 */ -+ XCL_CLKSEL_EVCH0_gc = (0x08<<0), /* Event channel 0 */ -+ XCL_CLKSEL_EVCH1_gc = (0x09<<0), /* Event channel 1 */ -+ XCL_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event channel 2 */ -+ XCL_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event channel 3 */ -+ XCL_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event channel 4 */ -+ XCL_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event channel 5 */ -+ XCL_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event channel 6 */ -+ XCL_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event channel 7 */ -+} XCL_CLKSEL_t; -+ -+/* Timer/Counter Command Selection */ -+typedef enum XCL_CMDSEL_enum -+{ -+ XCL_CMDSEL_NONE_gc = (0x00<<7), /* None */ -+ XCL_CMDSEL_RESTART_gc = (0x01<<7), /* Force restart */ -+} XCL_CMDSEL_t; -+ -+/* Timer/Counter Selection */ -+typedef enum XCL_TCSEL_enum -+{ -+ XCL_TCSEL_TC16_gc = (0x00<<4), /* 16-bit timer/counter */ -+ XCL_TCSEL_BTC0_gc = (0x01<<4), /* One 8-bit timer/counter */ -+ XCL_TCSEL_BTC01_gc = (0x02<<4), /* Two 8-bit timer/counters */ -+ XCL_TCSEL_BTC0PEC1_gc = (0x03<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ -+ XCL_TCSEL_PEC0BTC1_gc = (0x04<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ -+ XCL_TCSEL_PEC01_gc = (0x05<<4), /* Two 8-bit peripheral counters */ -+ XCL_TCSEL_BTC0PEC2_gc = (0x06<<4), /* One 8-bit timer/counter and two 4-bit peripheral counters */ -+} XCL_TCSEL_t; -+ -+/* Timer/Counter Mode */ -+typedef enum XCL_TCMODE_enum -+{ -+ XCL_TCMODE_NORMAL_gc = (0x00<<0), /* Normal mode with compare/period */ -+ XCL_TCMODE_CAPT_gc = (0x01<<0), /* Capture mode */ -+ XCL_TCMODE_PWM_gc = (0x02<<0), /* Single Slope PWM */ -+} XCL_TCMODE_t; -+ -+/* Compare Output Value Timer */ -+typedef enum XCL_CMPEN_enum -+{ -+ XCL_CMPEN_CLEAR_gc = (0x00<<5), /* Clear WG Output */ -+ XCL_CMPEN_SET_gc = (0x01<<5), /* Set WG Output */ -+} XCL_CMPEN_t; -+ -+/* Command Enable */ -+typedef enum XCL_CMDEN_enum -+{ -+ XCL_CMDEN_DISABLE_gc = (0x00<<6), /* Command Ignored */ -+ XCL_CMDEN_CMD0_gc = (0x01<<6), /* Command valid for timer/counter 0 */ -+ XCL_CMDEN_CMD1_gc = (0x02<<6), /* Command valid for timer/counter 1 */ -+ XCL_CMDEN_CMD01_gc = (0x03<<6), /* Command valid for both timer/counter 0 and 1 */ -+} XCL_CMDEN_t; -+ -+/* Timer/Counter Event Source Selection */ -+typedef enum XCL_EVSRC_enum -+{ -+ XCL_EVSRC_EVCH0_gc = (0x00<<0), /* Event channel 0 */ -+ XCL_EVSRC_EVCH1_gc = (0x01<<0), /* Event channel 1 */ -+ XCL_EVSRC_EVCH2_gc = (0x02<<0), /* Event channel 2 */ -+ XCL_EVSRC_EVCH3_gc = (0x03<<0), /* Event channel 3 */ -+ XCL_EVSRC_EVCH4_gc = (0x04<<0), /* Event channel 4 */ -+ XCL_EVSRC_EVCH5_gc = (0x05<<0), /* Event channel 5 */ -+ XCL_EVSRC_EVCH6_gc = (0x06<<0), /* Event channel 6 */ -+ XCL_EVSRC_EVCH7_gc = (0x07<<0), /* Event channel 7 */ -+} XCL_EVSRC_t; -+ -+/* Timer/Counter Event Action Selection */ -+typedef enum XCL_EVACT_enum -+{ -+ XCL_EVACT_INPUT_gc = (0x00<<5), /* Input Capture */ -+ XCL_EVACT_FREQ_gc = (0x01<<5), /* Frequency Capture */ -+ XCL_EVACT_PW_gc = (0x02<<5), /* Pulse Width Capture */ -+ XCL_EVACT_RESTART_gc = (0x03<<5), /* Restart timer/counter */ -+} XCL_EVACT_t; -+ -+/* Underflow Interrupt level */ -+typedef enum XCL_UNF_INTLVL_enum -+{ -+ XCL_UNF_INTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ XCL_UNF_INTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ XCL_UNF_INTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ XCL_UNF_INTLVL_HI_gc = (0x03<<2), /* High Level */ -+} XCL_UNF_INTLVL_t; -+ -+/* Compare/Capture Interrupt level */ -+typedef enum XCL_CC_INTLVL_enum -+{ -+ XCL_CC_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ XCL_CC_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ XCL_CC_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ XCL_CC_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} XCL_CC_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* */ -+typedef struct TWI_TIMEOUT_struct -+{ -+ register8_t TOS; /* Timeout Status Register */ -+ register8_t TOCONF; /* Timeout Configuration Register */ -+} TWI_TIMEOUT_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+ TWI_TIMEOUT_t TIMEOUT; /* TWI SMBUS timeout module */ -+} TWI_t; -+ -+/* SDA Hold Time */ -+typedef enum TWI_SDAHOLD_enum -+{ -+ TWI_SDAHOLD_OFF_gc = (0x00<<4), /* SDA Hold Time off */ -+ TWI_SDAHOLD_50NS_gc = (0x01<<4), /* SDA Hold Time 50 ns */ -+ TWI_SDAHOLD_300NS_gc = (0x02<<4), /* SDA Hold Time 300 ns */ -+ TWI_SDAHOLD_400NS_gc = (0x03<<4), /* SDA Hold Time 400 ns */ -+} TWI_SDAHOLD_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+/* Master Timeout */ -+typedef enum TWI_MASTER_TTIMEOUT_enum -+{ -+ TWI_MASTER_TTIMEOUT_25MS_gc = (0x00<<0), /* 25 Milliseconds */ -+ TWI_MASTER_TTIMEOUT_24MS_gc = (0x01<<0), /* 24 Milliseconds */ -+ TWI_MASTER_TTIMEOUT_23MS_gc = (0x02<<0), /* 23 Milliseconds */ -+ TWI_MASTER_TTIMEOUT_22MS_gc = (0x03<<0), /* 22 Milliseconds */ -+ TWI_MASTER_TTIMEOUT_26MS_gc = (0x04<<0), /* 26 Milliseconds */ -+ TWI_MASTER_TTIMEOUT_27MS_gc = (0x05<<0), /* 27 Milliseconds */ -+ TWI_MASTER_TTIMEOUT_28MS_gc = (0x06<<0), /* 28 Milliseconds */ -+ TWI_MASTER_TTIMEOUT_29MS_gc = (0x07<<0), /* 29 Milliseconds */ -+} TWI_MASTER_TTIMEOUT_t; -+ -+/* Slave Ttimeout */ -+typedef enum TWI_SLAVE_TTIMEOUT_enum -+{ -+ TWI_SLAVE_TTIMEOUT_25MS_gc = (0x00<<5), /* 25 Milliseconds */ -+ TWI_SLAVE_TTIMEOUT_24MS_gc = (0x01<<5), /* 24 Milliseconds */ -+ TWI_SLAVE_TTIMEOUT_23MS_gc = (0x02<<5), /* 23 Milliseconds */ -+ TWI_SLAVE_TTIMEOUT_22MS_gc = (0x03<<5), /* 22 Milliseconds */ -+ TWI_SLAVE_TTIMEOUT_26MS_gc = (0x04<<5), /* 26 Milliseconds */ -+ TWI_SLAVE_TTIMEOUT_27MS_gc = (0x05<<5), /* 27 Milliseconds */ -+ TWI_SLAVE_TTIMEOUT_28MS_gc = (0x06<<5), /* 28 Milliseconds */ -+ TWI_SLAVE_TTIMEOUT_29MS_gc = (0x07<<5), /* 29 Milliseconds */ -+} TWI_SLAVE_TTIMEOUT_t; -+ -+/* Master/Slave Extend Timeout */ -+typedef enum TWI_MASTER_TMSEXT_enum -+{ -+ TWI_MASTER_TMSEXT_10MS25MS_gc = (0x00<<3), /* Tmext 10ms Tsext 25ms */ -+ TWI_MASTER_TMSEXT_9MS24MS_gc = (0x01<<3), /* Tmext 9ms Tsext 24ms */ -+ TWI_MASTER_TMSEXT_11MS26MS_gc = (0x02<<3), /* Tmext 11ms Tsext 26ms */ -+ TWI_MASTER_TMSEXT_12MS27MS_gc = (0x03<<3), /* Tmext 12ms Tsext 27ms */ -+} TWI_MASTER_TMSEXT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTMASK; /* Port Interrupt Mask */ -+ register8_t reserved_0x0B; -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t REMAP; /* Pin Remap Register */ -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Port Interrupt Level */ -+typedef enum PORT_INTLVL_enum -+{ -+ PORT_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INTLVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_FORCE_ENABLE_gc = (0x06<<0), /* Digital Input Buffer Forced Enable */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 4 */ -+typedef struct TC4_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t CTRLF; /* Control Register F */ -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t CTRLHCLR; /* Control Register H Clear */ -+ register8_t CTRLHSET; /* Control Register H Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC4_t; -+ -+ -+/* 16-bit Timer/Counter 5 */ -+typedef struct TC5_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t CTRLF; /* Control Register F */ -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t CTRLHCLR; /* Control Register H Clear */ -+ register8_t CTRLHSET; /* Control Register H Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+} TC5_t; -+ -+/* Clock Selection */ -+typedef enum TC45_CLKSEL_enum -+{ -+ TC45_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC45_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC45_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC45_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC45_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC45_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC45_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC45_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC45_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC45_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC45_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC45_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC45_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC45_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC45_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC45_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC45_CLKSEL_t; -+ -+/* Byte Mode */ -+typedef enum TC45_BYTEM_enum -+{ -+ TC45_BYTEM_NORMAL_gc = (0x00<<6), /* 16-bit mode */ -+ TC45_BYTEM_BYTEMODE_gc = (0x01<<6), /* Timer/Counter Operating in Byte Mode Only */ -+} TC45_BYTEM_t; -+ -+/* Circular Enable Mode */ -+typedef enum TC45_CIRCEN_enum -+{ -+ TC45_CIRCEN_DISABLE_gc = (0x00<<4), /* Circular Buffer Disabled */ -+ TC45_CIRCEN_PER_gc = (0x01<<4), /* Circular Buffer Enabled on PER/PERBUF */ -+ TC45_CIRCEN_CCA_gc = (0x02<<4), /* Circular Buffer Enabled on CCA/CCABUF */ -+ TC45_CIRCEN_BOTH_gc = (0x03<<4), /* Circular Buffer Enabled on All Buffered Registers */ -+} TC45_CIRCEN_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC45_WGMODE_enum -+{ -+ TC45_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC45_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC45_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ -+ TC45_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC45_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Both */ -+ TC45_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC45_WGMODE_t; -+ -+/* Event Action */ -+typedef enum TC45_EVACT_enum -+{ -+ TC45_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC45_EVACT_FMODE1_gc = (0x01<<5), /* Fault Mode 1 capture */ -+ TC45_EVACT_FMODE2_gc = (0x02<<5), /* Fault Mode 2 capture */ -+ TC45_EVACT_UPDOWN_gc = (0x03<<5), /* Up/down count */ -+ TC45_EVACT_QDEC_gc = (0x04<<5), /* Quadrature decode */ -+ TC45_EVACT_RESTART_gc = (0x05<<5), /* Restart */ -+ TC45_EVACT_PWF_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC45_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC45_EVSEL_enum -+{ -+ TC45_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC45_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC45_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC45_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC45_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC45_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC45_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC45_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC45_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC45_EVSEL_t; -+ -+/* Compare or Capture Channel A Mode */ -+typedef enum TC45_CCAMODE_enum -+{ -+ TC45_CCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ -+ TC45_CCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ -+ TC45_CCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ -+ TC45_CCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -+} TC45_CCAMODE_t; -+ -+/* Compare or Capture Channel B Mode */ -+typedef enum TC45_CCBMODE_enum -+{ -+ TC45_CCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ -+ TC45_CCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ -+ TC45_CCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ -+ TC45_CCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -+} TC45_CCBMODE_t; -+ -+/* Compare or Capture Channel C Mode */ -+typedef enum TC45_CCCMODE_enum -+{ -+ TC45_CCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ -+ TC45_CCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ -+ TC45_CCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ -+ TC45_CCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -+} TC45_CCCMODE_t; -+ -+/* Compare or Capture Channel D Mode */ -+typedef enum TC45_CCDMODE_enum -+{ -+ TC45_CCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ -+ TC45_CCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ -+ TC45_CCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ -+ TC45_CCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -+} TC45_CCDMODE_t; -+ -+/* Compare or Capture Low Channel A Mode */ -+typedef enum TC45_LCCAMODE_enum -+{ -+ TC45_LCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ -+ TC45_LCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ -+ TC45_LCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ -+ TC45_LCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -+} TC45_LCCAMODE_t; -+ -+/* Compare or Capture Low Channel B Mode */ -+typedef enum TC45_LCCBMODE_enum -+{ -+ TC45_LCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ -+ TC45_LCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ -+ TC45_LCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ -+ TC45_LCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -+} TC45_LCCBMODE_t; -+ -+/* Compare or Capture Low Channel C Mode */ -+typedef enum TC45_LCCCMODE_enum -+{ -+ TC45_LCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ -+ TC45_LCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ -+ TC45_LCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ -+ TC45_LCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -+} TC45_LCCCMODE_t; -+ -+/* Compare or Capture Low Channel D Mode */ -+typedef enum TC45_LCCDMODE_enum -+{ -+ TC45_LCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ -+ TC45_LCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ -+ TC45_LCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ -+ TC45_LCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -+} TC45_LCCDMODE_t; -+ -+/* Compare or Capture High Channel A Mode */ -+typedef enum TC45_HCCAMODE_enum -+{ -+ TC45_HCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ -+ TC45_HCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ -+ TC45_HCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ -+ TC45_HCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -+} TC45_HCCAMODE_t; -+ -+/* Compare or Capture High Channel B Mode */ -+typedef enum TC45_HCCBMODE_enum -+{ -+ TC45_HCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ -+ TC45_HCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ -+ TC45_HCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ -+ TC45_HCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -+} TC45_HCCBMODE_t; -+ -+/* Compare or Capture High Channel C Mode */ -+typedef enum TC45_HCCCMODE_enum -+{ -+ TC45_HCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ -+ TC45_HCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ -+ TC45_HCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ -+ TC45_HCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -+} TC45_HCCCMODE_t; -+ -+/* Compare or Capture High Channel D Mode */ -+typedef enum TC45_HCCDMODE_enum -+{ -+ TC45_HCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ -+ TC45_HCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ -+ TC45_HCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ -+ TC45_HCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -+} TC45_HCCDMODE_t; -+ -+/* Timer Trigger Restart Interrupt Level */ -+typedef enum TC45_TRGINTLVL_enum -+{ -+ TC45_TRGINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC45_TRGINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC45_TRGINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC45_TRGINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC45_TRGINTLVL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC45_ERRINTLVL_enum -+{ -+ TC45_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC45_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC45_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC45_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC45_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC45_OVFINTLVL_enum -+{ -+ TC45_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC45_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC45_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC45_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC45_OVFINTLVL_t; -+ -+/* Compare or Capture Channel A Interrupt Level */ -+typedef enum TC45_CCAINTLVL_enum -+{ -+ TC45_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC45_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC45_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC45_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC45_CCAINTLVL_t; -+ -+/* Compare or Capture Channel B Interrupt Level */ -+typedef enum TC45_CCBINTLVL_enum -+{ -+ TC45_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC45_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC45_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC45_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC45_CCBINTLVL_t; -+ -+/* Compare or Capture Channel C Interrupt Level */ -+typedef enum TC45_CCCINTLVL_enum -+{ -+ TC45_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC45_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC45_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC45_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC45_CCCINTLVL_t; -+ -+/* Compare or Capture Channel D Interrupt Level */ -+typedef enum TC45_CCDINTLVL_enum -+{ -+ TC45_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC45_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC45_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC45_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC45_CCDINTLVL_t; -+ -+/* Compare or Capture Low Channel A Interrupt Level */ -+typedef enum TC45_LCCAINTLVL_enum -+{ -+ TC45_LCCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC45_LCCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC45_LCCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC45_LCCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC45_LCCAINTLVL_t; -+ -+/* Compare or Capture Low Channel B Interrupt Level */ -+typedef enum TC45_LCCBINTLVL_enum -+{ -+ TC45_LCCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC45_LCCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC45_LCCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC45_LCCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC45_LCCBINTLVL_t; -+ -+/* Compare or Capture Low Channel C Interrupt Level */ -+typedef enum TC45_LCCCINTLVL_enum -+{ -+ TC45_LCCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC45_LCCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC45_LCCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC45_LCCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC45_LCCCINTLVL_t; -+ -+/* Compare or Capture Low Channel D Interrupt Level */ -+typedef enum TC45_LCCDINTLVL_enum -+{ -+ TC45_LCCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC45_LCCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC45_LCCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC45_LCCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC45_LCCDINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC45_CMD_enum -+{ -+ TC45_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC45_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC45_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC45_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC45_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FAULT - Fault Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fault Extension */ -+typedef struct FAULT_struct -+{ -+ register8_t CTRLA; /* Control A Register */ -+ register8_t CTRLB; /* Control B Register */ -+ register8_t CTRLC; /* Control C Register */ -+ register8_t CTRLD; /* Control D Register */ -+ register8_t CTRLE; /* Control E Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G set */ -+} FAULT_t; -+ -+/* Ramp Mode Selection */ -+typedef enum FAULT_RAMP_enum -+{ -+ FAULT_RAMP_RAMP1_gc = (0x00<<6), /* Normal Mode */ -+ FAULT_RAMP_RAMP2_gc = (0x02<<6), /* RAMP2 Mode */ -+} FAULT_RAMP_t; -+ -+/* Fault E Input Source Selection */ -+typedef enum FAULT_SRCE_enum -+{ -+ FAULT_SRCE_DISABLE_gc = (0x00<<0), /* Fault Protection Disabled */ -+ FAULT_SRCE_CHN_gc = (0x01<<0), /* Event Channel n */ -+ FAULT_SRCE_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ -+ FAULT_SRCE_CHN2_gc = (0x03<<0), /* Event Channel n+2 */ -+} FAULT_SRCE_t; -+ -+/* Fault A Halt Action Selection */ -+typedef enum FAULT_HALTA_enum -+{ -+ FAULT_HALTA_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ -+ FAULT_HALTA_HW_gc = (0x01<<5), /* Hardware Halt Action */ -+ FAULT_HALTA_SW_gc = (0x02<<5), /* Software Halt Action */ -+} FAULT_HALTA_t; -+ -+/* Fault A Source Selection */ -+typedef enum FAULT_SRCA_enum -+{ -+ FAULT_SRCA_DISABLE_gc = (0x00<<0), /* Fault A Disabled */ -+ FAULT_SRCA_CHN_gc = (0x01<<0), /* Event Channel n */ -+ FAULT_SRCA_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ -+ FAULT_SRCA_LINK_gc = (0x03<<0), /* Fault A linked to Fault B State from previous cycle */ -+} FAULT_SRCA_t; -+ -+/* Fault B Halt Action Selection */ -+typedef enum FAULT_HALTB_enum -+{ -+ FAULT_HALTB_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ -+ FAULT_HALTB_HW_gc = (0x01<<5), /* Hardware Halt Action */ -+ FAULT_HALTB_SW_gc = (0x02<<5), /* Software Halt Action */ -+} FAULT_HALTB_t; -+ -+/* Fault B Source Selection */ -+typedef enum FAULT_SRCB_enum -+{ -+ FAULT_SRCB_DISABLE_gc = (0x00<<0), /* Fault B disabled */ -+ FAULT_SRCB_CHN_gc = (0x01<<0), /* Event Channel n */ -+ FAULT_SRCB_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ -+ FAULT_SRCB_LINK_gc = (0x03<<0), /* Fault B linked to Fault A State from previous cycle */ -+} FAULT_SRCB_t; -+ -+/* Channel index Command */ -+typedef enum FAULT_IDXCMD_enum -+{ -+ FAULT_IDXCMD_DISABLE_gc = (0x00<<3), /* Command Disabled */ -+ FAULT_IDXCMD_SET_gc = (0x01<<3), /* Force Cycle B in Next Cycle */ -+ FAULT_IDXCMD_CLEAR_gc = (0x02<<3), /* Force Cycle A in Next Cycle */ -+ FAULT_IDXCMD_HOLD_gc = (0x03<<3), /* Hold Current Cycle Index in Next Cycle */ -+} FAULT_IDXCMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WEX - Waveform Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Waveform Extension */ -+typedef struct WEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t DTBOTH; /* Dead-time Concurrent Write to Both Sides Register */ -+ register8_t DTLS; /* Dead-time Low Side Register */ -+ register8_t DTHS; /* Dead-time High Side Register */ -+ register8_t STATUSCLR; /* Status Clear Register */ -+ register8_t STATUSSET; /* Status Set Register */ -+ register8_t SWAP; /* Swap Register */ -+ register8_t PGO; /* Pattern Generation Override Register */ -+ register8_t PGV; /* Pattern Generation Value Register */ -+ register8_t reserved_0x09; -+ register8_t SWAPBUF; /* Dead Time Low Side Buffer */ -+ register8_t PGOBUF; /* Pattern Generation Overwrite Buffer Register */ -+ register8_t PGVBUF; /* Pattern Generation Value Buffer Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t OUTOVDIS; /* Output Override Disable Register */ -+} WEX_t; -+ -+/* Output Matrix Mode */ -+typedef enum WEX_OTMX_enum -+{ -+ WEX_OTMX_DEFAULT_gc = (0x00<<4), /* Default Ouput Matrix Mode */ -+ WEX_OTMX_FIRST_gc = (0x01<<4), /* First Output matrix Mode */ -+ WEX_OTMX_SECOND_gc = (0x02<<4), /* Second Output matrix Mode */ -+ WEX_OTMX_THIRD_gc = (0x03<<4), /* Third Output matrix Mode */ -+ WEX_OTMX_FOURTH_gc = (0x04<<4), /* Fourth Output matrix Mode */ -+} WEX_OTMX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+HIRES - High-Resolution Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+} HIRES_t; -+ -+/* High Resolution Plus Mode */ -+typedef enum HIRES_HRPLUS_enum -+{ -+ HIRES_HRPLUS_NONE_gc = (0x00<<2), /* No Hi-Res Plus */ -+ HIRES_HRPLUS_HRP4_gc = (0x01<<2), /* Hi-Res Plus enabled on Timer 4 */ -+ HIRES_HRPLUS_HRP5_gc = (0x02<<2), /* Hi-Res Plus enabled on Timer 5 */ -+ HIRES_HRPLUS_BOTH_gc = (0x03<<2), /* Hi-Res Plus enabled on Timer 4 and 5 */ -+} HIRES_HRPLUS_t; -+ -+/* High Resolution Mode */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Hi-Res */ -+ HIRES_HREN_HRP4_gc = (0x01<<0), /* Hi-Res enabled on Timer 4 */ -+ HIRES_HREN_HRP5_gc = (0x02<<0), /* Hi-Res enabled on Timer 5 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Hi-Res enabled on Timer 4 and 5 */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Start Interrupt level */ -+typedef enum USART_RXSINTLVL_enum -+{ -+ USART_RXSINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_RXSINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_RXSINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_RXSINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_RXSINTLVL_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+/* Encoding and Decoding Type */ -+typedef enum USART_DECTYPE_enum -+{ -+ USART_DECTYPE_DATA_gc = (0x00<<4), /* DATA Field Encoding */ -+ USART_DECTYPE_SDATA_gc = (0x02<<4), /* Start and Data Fields Encoding */ -+ USART_DECTYPE_NOTSDATA_gc = (0x03<<4), /* Start and Data Fields Encoding, with invertion in START field */ -+} USART_DECTYPE_t; -+ -+/* XCL LUT Action */ -+typedef enum USART_LUTACT_enum -+{ -+ USART_LUTACT_OFF_gc = (0x00<<2), /* Standard Frame Configuration */ -+ USART_LUTACT_RX_gc = (0x01<<2), /* Receiver Decoding Enabled */ -+ USART_LUTACT_TX_gc = (0x02<<2), /* Transmitter Encoding Enabled */ -+ USART_LUTACT_BOTH_gc = (0x03<<2), /* Both Encoding and Decoding Enabled */ -+} USART_LUTACT_t; -+ -+/* XCL Peripheral Counter Action */ -+typedef enum USART_PECACT_enum -+{ -+ USART_PECACT_OFF_gc = (0x00<<0), /* Standard Mode */ -+ USART_PECACT_PEC0_gc = (0x01<<0), /* Variable Data Lenght in Reception */ -+ USART_PECACT_PEC1_gc = (0x02<<0), /* Variable Data Lenght in Transmission */ -+ USART_PECACT_PERC01_gc = (0x03<<0), /* Variable Data Lenght in both Reception and Transmission */ -+} USART_PECACT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface with Buffer Modes */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t CTRLB; /* Control Register B */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0, base clock at "0", sampling on leading edge (rising) & set-up on trailling edge (falling). */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1, base clock at "0", set-up on leading edge (rising) & sampling on trailling edge (falling). */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2, base clock at "1", sampling on leading edge (falling) & set-up on trailling edge (rising). */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3, base clock at "1", set-up on leading edge (falling) & sampling on trailling edge (rising). */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* If CLK2X=1 CLKper/2, else (CLK2X=0) CLKper/4. */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* If CLK2X=1 CLKper/8, else (CLK2X=0) CLKper/16. */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* If CLK2X=1 CLKper/32, else (CLK2X=0) CLKper/64. */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* If CLK2X=1 CLKper/64, else (CLK2X=0) CLKper/128. */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+/* Buffer Modes */ -+typedef enum SPI_BUFMODE_enum -+{ -+ SPI_BUFMODE_OFF_gc = (0x00<<6), /* SPI Unbuffered Mode */ -+ SPI_BUFMODE_BUFMODE1_gc = (0x02<<6), /* Buffer Mode 1 (with dummy byte) */ -+ SPI_BUFMODE_BUFMODE2_gc = (0x03<<6), /* Buffer Mode 2 (no dummy byte) */ -+} SPI_BUFMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ -+ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ -+ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ -+ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -+} IRDA_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t reserved_0x00; -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+ register8_t FUSEBYTE6; /* Fault State */ -+} NVM_FUSES_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BOD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC8M; /* RCOSC 8MHz Calibration Value */ -+ register8_t reserved_0x01; -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t ROOMTEMP; /* Temperature corresponds to TEMPSENSE3/2 */ -+ register8_t HOTTEMP; /* Temperature corresponds to TEMPSENSE1/0 */ -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t ACACURRCAL; /* ACA Current Calibration Byte */ -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t TEMPSENSE2; /* Temperature Sensor Calibration Byte 2 */ -+ register8_t TEMPSENSE3; /* Temperature Sensor Calibration Byte 3 */ -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ -+ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ -+ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+} NVM_PROD_SIGNATURES_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define EDMA (*(EDMA_t *) 0x0100) /* Enhanced DMA Controller */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -+#define XCL (*(XCL_t *) 0x0460) /* XMEGA Custom Logic */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC4 (*(TC4_t *) 0x0800) /* 16-bit Timer/Counter 4 */ -+#define TCC5 (*(TC5_t *) 0x0840) /* 16-bit Timer/Counter 5 */ -+#define FAULTC4 (*(FAULT_t *) 0x0880) /* Fault Extension */ -+#define FAULTC5 (*(FAULT_t *) 0x0890) /* Fault Extension */ -+#define WEXC (*(WEX_t *) 0x08A0) /* Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x08B0) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08E0) /* Serial Peripheral Interface with Buffer Modes */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define TCD5 (*(TC5_t *) 0x0940) /* 16-bit Timer/Counter 5 */ -+#define USARTD0 (*(USART_t *) 0x09C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+#define FUSE_FUSEBYTE6 _SFR_MEM8(0x0006) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC8M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_ROOMTEMP _SFR_MEM8(0x001E) -+#define PRODSIGNATURES_HOTTEMP _SFR_MEM8(0x001F) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_ACACURRCAL _SFR_MEM8(0x0028) -+#define PRODSIGNATURES_TEMPSENSE2 _SFR_MEM8(0x002C) -+#define PRODSIGNATURES_TEMPSENSE3 _SFR_MEM8(0x002D) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -+#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -+#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -+#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+#define OSC_RC8MCAL _SFR_MEM8(0x0057) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPD _SFR_MEM8(0x0074) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_ANAINIT _SFR_MEM8(0x0097) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_WEXLOCK _SFR_MEM8(0x0099) -+#define MCU_FAULTLOCK _SFR_MEM8(0x009A) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_CLKOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_ACEVOUT _SFR_MEM8(0x00B6) -+#define PORTCFG_SRLCTRL _SFR_MEM8(0x00B7) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* EDMA - Enhanced DMA Controller */ -+#define EDMA_CTRL _SFR_MEM8(0x0100) -+#define EDMA_INTFLAGS _SFR_MEM8(0x0103) -+#define EDMA_STATUS _SFR_MEM8(0x0104) -+#define EDMA_TEMP _SFR_MEM8(0x0106) -+#define EDMA_CH0_CTRLA _SFR_MEM8(0x0110) -+#define EDMA_CH0_CTRLB _SFR_MEM8(0x0111) -+#define EDMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -+#define EDMA_CH0_DESTADDRCTRL _SFR_MEM8(0x0113) -+#define EDMA_CH0_TRIGSRC _SFR_MEM8(0x0114) -+#define EDMA_CH0_TRFCNT _SFR_MEM16(0x0116) -+#define EDMA_CH0_ADDR _SFR_MEM16(0x0118) -+#define EDMA_CH0_DESTADDR _SFR_MEM16(0x011C) -+#define EDMA_CH1_CTRLA _SFR_MEM8(0x0120) -+#define EDMA_CH1_CTRLB _SFR_MEM8(0x0121) -+#define EDMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -+#define EDMA_CH1_DESTADDRCTRL _SFR_MEM8(0x0123) -+#define EDMA_CH1_TRIGSRC _SFR_MEM8(0x0124) -+#define EDMA_CH1_TRFCNT _SFR_MEM16(0x0126) -+#define EDMA_CH1_ADDR _SFR_MEM16(0x0128) -+#define EDMA_CH1_DESTADDR _SFR_MEM16(0x012C) -+#define EDMA_CH2_CTRLA _SFR_MEM8(0x0130) -+#define EDMA_CH2_CTRLB _SFR_MEM8(0x0131) -+#define EDMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -+#define EDMA_CH2_DESTADDRCTRL _SFR_MEM8(0x0133) -+#define EDMA_CH2_TRIGSRC _SFR_MEM8(0x0134) -+#define EDMA_CH2_TRFCNT _SFR_MEM16(0x0136) -+#define EDMA_CH2_ADDR _SFR_MEM16(0x0138) -+#define EDMA_CH2_DESTADDR _SFR_MEM16(0x013C) -+#define EDMA_CH3_CTRLA _SFR_MEM8(0x0140) -+#define EDMA_CH3_CTRLB _SFR_MEM8(0x0141) -+#define EDMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -+#define EDMA_CH3_DESTADDRCTRL _SFR_MEM8(0x0143) -+#define EDMA_CH3_TRIGSRC _SFR_MEM8(0x0144) -+#define EDMA_CH3_TRFCNT _SFR_MEM16(0x0146) -+#define EDMA_CH3_ADDR _SFR_MEM16(0x0148) -+#define EDMA_CH3_DESTADDR _SFR_MEM16(0x014C) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -+#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -+#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -+#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -+#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -+#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -+#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+#define EVSYS_DFCTRL _SFR_MEM8(0x0192) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCA_CTRLA _SFR_MEM8(0x0200) -+#define ADCA_CTRLB _SFR_MEM8(0x0201) -+#define ADCA_REFCTRL _SFR_MEM8(0x0202) -+#define ADCA_EVCTRL _SFR_MEM8(0x0203) -+#define ADCA_PRESCALER _SFR_MEM8(0x0204) -+#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -+#define ADCA_TEMP _SFR_MEM8(0x0207) -+#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) -+#define ADCA_CAL _SFR_MEM16(0x020C) -+#define ADCA_CH0RES _SFR_MEM16(0x0210) -+#define ADCA_CMP _SFR_MEM16(0x0218) -+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -+#define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -+#define ADCA_CH0_CORRCTRL _SFR_MEM8(0x0227) -+#define ADCA_CH0_OFFSETCORR0 _SFR_MEM8(0x0228) -+#define ADCA_CH0_OFFSETCORR1 _SFR_MEM8(0x0229) -+#define ADCA_CH0_GAINCORR0 _SFR_MEM8(0x022A) -+#define ADCA_CH0_GAINCORR1 _SFR_MEM8(0x022B) -+#define ADCA_CH0_AVGCTRL _SFR_MEM8(0x022C) -+ -+/* DAC - Digital-to-Analog Converter */ -+#define DACA_CTRLA _SFR_MEM8(0x0300) -+#define DACA_CTRLB _SFR_MEM8(0x0301) -+#define DACA_CTRLC _SFR_MEM8(0x0302) -+#define DACA_EVCTRL _SFR_MEM8(0x0303) -+#define DACA_STATUS _SFR_MEM8(0x0305) -+#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) -+#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) -+#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) -+#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) -+#define DACA_CH0DATA _SFR_MEM16(0x0318) -+#define DACA_CH1DATA _SFR_MEM16(0x031A) -+ -+/* AC - Analog Comparator */ -+#define ACA_AC0CTRL _SFR_MEM8(0x0380) -+#define ACA_AC1CTRL _SFR_MEM8(0x0381) -+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -+#define ACA_CTRLA _SFR_MEM8(0x0384) -+#define ACA_CTRLB _SFR_MEM8(0x0385) -+#define ACA_WINCTRL _SFR_MEM8(0x0386) -+#define ACA_STATUS _SFR_MEM8(0x0387) -+#define ACA_CURRCTRL _SFR_MEM8(0x0388) -+#define ACA_CURRCALIB _SFR_MEM8(0x0389) -+ -+/* RTC - Real-Time Counter */ -+#define RTC_CTRL _SFR_MEM8(0x0400) -+#define RTC_STATUS _SFR_MEM8(0x0401) -+#define RTC_INTCTRL _SFR_MEM8(0x0402) -+#define RTC_INTFLAGS _SFR_MEM8(0x0403) -+#define RTC_TEMP _SFR_MEM8(0x0404) -+#define RTC_CALIB _SFR_MEM8(0x0406) -+#define RTC_CNT _SFR_MEM16(0x0408) -+#define RTC_PER _SFR_MEM16(0x040A) -+#define RTC_COMP _SFR_MEM16(0x040C) -+ -+/* XCL - XMEGA Custom Logic */ -+#define XCL_CTRLA _SFR_MEM8(0x0460) -+#define XCL_CTRLB _SFR_MEM8(0x0461) -+#define XCL_CTRLC _SFR_MEM8(0x0462) -+#define XCL_CTRLD _SFR_MEM8(0x0463) -+#define XCL_CTRLE _SFR_MEM8(0x0464) -+#define XCL_CTRLF _SFR_MEM8(0x0465) -+#define XCL_CTRLG _SFR_MEM8(0x0466) -+#define XCL_INTCTRL _SFR_MEM8(0x0467) -+#define XCL_INTFLAGS _SFR_MEM8(0x0468) -+#define XCL_PLC _SFR_MEM8(0x0469) -+#define XCL_CNTL _SFR_MEM8(0x046A) -+#define XCL_CNTH _SFR_MEM8(0x046B) -+#define XCL_CMPL _SFR_MEM8(0x046C) -+#define XCL_CMPH _SFR_MEM8(0x046D) -+#define XCL_PERCAPTL _SFR_MEM8(0x046E) -+#define XCL_PERCAPTH _SFR_MEM8(0x046F) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+#define TWIC_TIMEOUT_TOS _SFR_MEM8(0x048E) -+#define TWIC_TIMEOUT_TOCONF _SFR_MEM8(0x048F) -+ -+/* PORT - I/O Ports */ -+#define PORTA_DIR _SFR_MEM8(0x0600) -+#define PORTA_DIRSET _SFR_MEM8(0x0601) -+#define PORTA_DIRCLR _SFR_MEM8(0x0602) -+#define PORTA_DIRTGL _SFR_MEM8(0x0603) -+#define PORTA_OUT _SFR_MEM8(0x0604) -+#define PORTA_OUTSET _SFR_MEM8(0x0605) -+#define PORTA_OUTCLR _SFR_MEM8(0x0606) -+#define PORTA_OUTTGL _SFR_MEM8(0x0607) -+#define PORTA_IN _SFR_MEM8(0x0608) -+#define PORTA_INTCTRL _SFR_MEM8(0x0609) -+#define PORTA_INTMASK _SFR_MEM8(0x060A) -+#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_REMAP _SFR_MEM8(0x060E) -+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INTMASK _SFR_MEM8(0x064A) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INTMASK _SFR_MEM8(0x066A) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INTMASK _SFR_MEM8(0x07EA) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC4 - 16-bit Timer/Counter 4 */ -+#define TCC4_CTRLA _SFR_MEM8(0x0800) -+#define TCC4_CTRLB _SFR_MEM8(0x0801) -+#define TCC4_CTRLC _SFR_MEM8(0x0802) -+#define TCC4_CTRLD _SFR_MEM8(0x0803) -+#define TCC4_CTRLE _SFR_MEM8(0x0804) -+#define TCC4_CTRLF _SFR_MEM8(0x0805) -+#define TCC4_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC4_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC4_CTRLGCLR _SFR_MEM8(0x0808) -+#define TCC4_CTRLGSET _SFR_MEM8(0x0809) -+#define TCC4_CTRLHCLR _SFR_MEM8(0x080A) -+#define TCC4_CTRLHSET _SFR_MEM8(0x080B) -+#define TCC4_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC4_TEMP _SFR_MEM8(0x080F) -+#define TCC4_CNT _SFR_MEM16(0x0820) -+#define TCC4_PER _SFR_MEM16(0x0826) -+#define TCC4_CCA _SFR_MEM16(0x0828) -+#define TCC4_CCB _SFR_MEM16(0x082A) -+#define TCC4_CCC _SFR_MEM16(0x082C) -+#define TCC4_CCD _SFR_MEM16(0x082E) -+#define TCC4_PERBUF _SFR_MEM16(0x0836) -+#define TCC4_CCABUF _SFR_MEM16(0x0838) -+#define TCC4_CCBBUF _SFR_MEM16(0x083A) -+#define TCC4_CCCBUF _SFR_MEM16(0x083C) -+#define TCC4_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC5 - 16-bit Timer/Counter 5 */ -+#define TCC5_CTRLA _SFR_MEM8(0x0840) -+#define TCC5_CTRLB _SFR_MEM8(0x0841) -+#define TCC5_CTRLC _SFR_MEM8(0x0842) -+#define TCC5_CTRLD _SFR_MEM8(0x0843) -+#define TCC5_CTRLE _SFR_MEM8(0x0844) -+#define TCC5_CTRLF _SFR_MEM8(0x0845) -+#define TCC5_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC5_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC5_CTRLGCLR _SFR_MEM8(0x0848) -+#define TCC5_CTRLGSET _SFR_MEM8(0x0849) -+#define TCC5_CTRLHCLR _SFR_MEM8(0x084A) -+#define TCC5_CTRLHSET _SFR_MEM8(0x084B) -+#define TCC5_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC5_TEMP _SFR_MEM8(0x084F) -+#define TCC5_CNT _SFR_MEM16(0x0860) -+#define TCC5_PER _SFR_MEM16(0x0866) -+#define TCC5_CCA _SFR_MEM16(0x0868) -+#define TCC5_CCB _SFR_MEM16(0x086A) -+#define TCC5_PERBUF _SFR_MEM16(0x0876) -+#define TCC5_CCABUF _SFR_MEM16(0x0878) -+#define TCC5_CCBBUF _SFR_MEM16(0x087A) -+ -+/* FAULT - Fault Extension */ -+#define FAULTC4_CTRLA _SFR_MEM8(0x0880) -+#define FAULTC4_CTRLB _SFR_MEM8(0x0881) -+#define FAULTC4_CTRLC _SFR_MEM8(0x0882) -+#define FAULTC4_CTRLD _SFR_MEM8(0x0883) -+#define FAULTC4_CTRLE _SFR_MEM8(0x0884) -+#define FAULTC4_STATUS _SFR_MEM8(0x0885) -+#define FAULTC4_CTRLGCLR _SFR_MEM8(0x0886) -+#define FAULTC4_CTRLGSET _SFR_MEM8(0x0887) -+ -+/* FAULT - Fault Extension */ -+#define FAULTC5_CTRLA _SFR_MEM8(0x0890) -+#define FAULTC5_CTRLB _SFR_MEM8(0x0891) -+#define FAULTC5_CTRLC _SFR_MEM8(0x0892) -+#define FAULTC5_CTRLD _SFR_MEM8(0x0893) -+#define FAULTC5_CTRLE _SFR_MEM8(0x0894) -+#define FAULTC5_STATUS _SFR_MEM8(0x0895) -+#define FAULTC5_CTRLGCLR _SFR_MEM8(0x0896) -+#define FAULTC5_CTRLGSET _SFR_MEM8(0x0897) -+ -+/* WEX - Waveform Extension */ -+#define WEXC_CTRL _SFR_MEM8(0x08A0) -+#define WEXC_DTBOTH _SFR_MEM8(0x08A1) -+#define WEXC_DTLS _SFR_MEM8(0x08A2) -+#define WEXC_DTHS _SFR_MEM8(0x08A3) -+#define WEXC_STATUSCLR _SFR_MEM8(0x08A4) -+#define WEXC_STATUSSET _SFR_MEM8(0x08A5) -+#define WEXC_SWAP _SFR_MEM8(0x08A6) -+#define WEXC_PGO _SFR_MEM8(0x08A7) -+#define WEXC_PGV _SFR_MEM8(0x08A8) -+#define WEXC_SWAPBUF _SFR_MEM8(0x08AA) -+#define WEXC_PGOBUF _SFR_MEM8(0x08AB) -+#define WEXC_PGVBUF _SFR_MEM8(0x08AC) -+#define WEXC_OUTOVDIS _SFR_MEM8(0x08AF) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x08B0) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08C0) -+#define USARTC0_STATUS _SFR_MEM8(0x08C1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08C2) -+#define USARTC0_CTRLB _SFR_MEM8(0x08C3) -+#define USARTC0_CTRLC _SFR_MEM8(0x08C4) -+#define USARTC0_CTRLD _SFR_MEM8(0x08C5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08C6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08C7) -+ -+/* SPI - Serial Peripheral Interface with Buffer Modes */ -+#define SPIC_CTRL _SFR_MEM8(0x08E0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08E1) -+#define SPIC_STATUS _SFR_MEM8(0x08E2) -+#define SPIC_DATA _SFR_MEM8(0x08E3) -+#define SPIC_CTRLB _SFR_MEM8(0x08E4) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* TC5 - 16-bit Timer/Counter 5 */ -+#define TCD5_CTRLA _SFR_MEM8(0x0940) -+#define TCD5_CTRLB _SFR_MEM8(0x0941) -+#define TCD5_CTRLC _SFR_MEM8(0x0942) -+#define TCD5_CTRLD _SFR_MEM8(0x0943) -+#define TCD5_CTRLE _SFR_MEM8(0x0944) -+#define TCD5_CTRLF _SFR_MEM8(0x0945) -+#define TCD5_INTCTRLA _SFR_MEM8(0x0946) -+#define TCD5_INTCTRLB _SFR_MEM8(0x0947) -+#define TCD5_CTRLGCLR _SFR_MEM8(0x0948) -+#define TCD5_CTRLGSET _SFR_MEM8(0x0949) -+#define TCD5_CTRLHCLR _SFR_MEM8(0x094A) -+#define TCD5_CTRLHSET _SFR_MEM8(0x094B) -+#define TCD5_INTFLAGS _SFR_MEM8(0x094C) -+#define TCD5_TEMP _SFR_MEM8(0x094F) -+#define TCD5_CNT _SFR_MEM16(0x0960) -+#define TCD5_PER _SFR_MEM16(0x0966) -+#define TCD5_CCA _SFR_MEM16(0x0968) -+#define TCD5_CCB _SFR_MEM16(0x096A) -+#define TCD5_PERBUF _SFR_MEM16(0x0976) -+#define TCD5_CCABUF _SFR_MEM16(0x0978) -+#define TCD5_CCBBUF _SFR_MEM16(0x097A) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD0_DATA _SFR_MEM8(0x09C0) -+#define USARTD0_STATUS _SFR_MEM8(0x09C1) -+#define USARTD0_CTRLA _SFR_MEM8(0x09C2) -+#define USARTD0_CTRLB _SFR_MEM8(0x09C3) -+#define USARTD0_CTRLC _SFR_MEM8(0x09C4) -+#define USARTD0_CTRLD _SFR_MEM8(0x09C5) -+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09C6) -+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09C7) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* VPORT - Virtual Ports */ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT7IF_bm 0x80 /* Interrupt Pin 7 Flag bit mask. */ -+#define VPORT_INT7IF_bp 7 /* Interrupt Pin 7 Flag bit position. */ -+ -+#define VPORT_INT6IF_bm 0x40 /* Interrupt Pin 6 Flag bit mask. */ -+#define VPORT_INT6IF_bp 6 /* Interrupt Pin 6 Flag bit position. */ -+ -+#define VPORT_INT5IF_bm 0x20 /* Interrupt Pin 5 Flag bit mask. */ -+#define VPORT_INT5IF_bp 5 /* Interrupt Pin 5 Flag bit position. */ -+ -+#define VPORT_INT4IF_bm 0x10 /* Interrupt Pin 4 Flag bit mask. */ -+#define VPORT_INT4IF_bp 4 /* Interrupt Pin 4 Flag bit position. */ -+ -+#define VPORT_INT3IF_bm 0x08 /* Interrupt Pin 3 Flag bit mask. */ -+#define VPORT_INT3IF_bp 3 /* Interrupt Pin 3 Flag bit position. */ -+ -+#define VPORT_INT2IF_bm 0x04 /* Interrupt Pin 2 Flag bit mask. */ -+#define VPORT_INT2IF_bp 2 /* Interrupt Pin 2 Flag bit position. */ -+ -+#define VPORT_INT1IF_bm 0x02 /* Interrupt Pin 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Interrupt Pin 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Interrupt Pin 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Interrupt Pin 0 Flag bit position. */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_XCL_bm 0x80 /* XMEGA Custom Logic bit mask. */ -+#define PR_XCL_bp 7 /* XMEGA Custom Logic bit position. */ -+ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+#define PR_EDMA_bm 0x01 /* Enhanced DMA-Controller bit mask. */ -+#define PR_EDMA_bp 0 /* Enhanced DMA-Controller bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -+#define PR_DAC_bp 2 /* Port A DAC bit position. */ -+ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C WEX bit mask. */ -+#define PR_HIRES_bp 2 /* Port C WEX bit position. */ -+ -+#define PR_TC5_bm 0x02 /* Port C Timer/Counter5 bit mask. */ -+#define PR_TC5_bp 1 /* Port C Timer/Counter5 bit position. */ -+ -+#define PR_TC4_bm 0x01 /* Port C Timer/Counter4 bit mask. */ -+#define PR_TC4_bp 0 /* Port C Timer/Counter4 bit position. */ -+ -+/* PR.PRPD bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC5 Predefined. */ -+/* PR_TC5 Predefined. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_RC8MLPM_bm 0x40 /* Internal 8 MHz RC Low Power Mode Enable bit mask. */ -+#define OSC_RC8MLPM_bp 6 /* Internal 8 MHz RC Low Power Mode Enable bit position. */ -+ -+#define OSC_RC8MEN_bm 0x20 /* Internal 8 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC8MEN_bp 5 /* Internal 8 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_RC8MRDY_bm 0x20 /* Internal 8 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC8MRDY_bp 5 /* Internal 8 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ -+#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -+#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -+#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ -+ -+#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ -+ -+/* OSC.RC8MCAL bit masks and bit positions */ -+#define OSC_RC8MCAL_gm 0xFF /* Calibration Bits group mask. */ -+#define OSC_RC8MCAL_gp 0 /* Calibration Bits group position. */ -+#define OSC_RC8MCAL0_bm (1<<0) /* Calibration Bits bit 0 mask. */ -+#define OSC_RC8MCAL0_bp 0 /* Calibration Bits bit 0 position. */ -+#define OSC_RC8MCAL1_bm (1<<1) /* Calibration Bits bit 1 mask. */ -+#define OSC_RC8MCAL1_bp 1 /* Calibration Bits bit 1 position. */ -+#define OSC_RC8MCAL2_bm (1<<2) /* Calibration Bits bit 2 mask. */ -+#define OSC_RC8MCAL2_bp 2 /* Calibration Bits bit 2 position. */ -+#define OSC_RC8MCAL3_bm (1<<3) /* Calibration Bits bit 3 mask. */ -+#define OSC_RC8MCAL3_bp 3 /* Calibration Bits bit 3 position. */ -+#define OSC_RC8MCAL4_bm (1<<4) /* Calibration Bits bit 4 mask. */ -+#define OSC_RC8MCAL4_bp 4 /* Calibration Bits bit 4 position. */ -+#define OSC_RC8MCAL5_bm (1<<5) /* Calibration Bits bit 5 mask. */ -+#define OSC_RC8MCAL5_bp 5 /* Calibration Bits bit 5 position. */ -+#define OSC_RC8MCAL6_bm (1<<6) /* Calibration Bits bit 6 mask. */ -+#define OSC_RC8MCAL6_bp 6 /* Calibration Bits bit 6 position. */ -+#define OSC_RC8MCAL7_bm (1<<7) /* Calibration Bits bit 7 mask. */ -+#define OSC_RC8MCAL7_bp 7 /* Calibration Bits bit 7 position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.ANAINIT bit masks and bit positions */ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -+#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ -+ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.WEXLOCK bit masks and bit positions */ -+#define MCU_WEXCLOCK_bm 0x01 /* WeX on T/C C4 Lock bit mask. */ -+#define MCU_WEXCLOCK_bp 0 /* WeX on T/C C4 Lock bit position. */ -+ -+/* MCU.FAULTLOCK bit masks and bit positions */ -+#define MCU_FAULTC5LOCK_bm 0x02 /* Fault on T/C C5 Lock bit mask. */ -+#define MCU_FAULTC5LOCK_bp 1 /* Fault on T/C C5 Lock bit position. */ -+ -+#define MCU_FAULTC4LOCK_bm 0x01 /* Fault on T/C C4 Lock bit mask. */ -+#define MCU_FAULTC4LOCK_bp 0 /* Fault on T/C C4 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* PORTCFG - Port Configuration */ -+/* PORTCFG.CLKOUT bit masks and bit positions */ -+#define PORTCFG_CLKEVPIN_bm 0x80 /* Clock and Event Output Pin Select bit mask. */ -+#define PORTCFG_CLKEVPIN_bp 7 /* Clock and Event Output Pin Select bit position. */ -+ -+#define PORTCFG_RTCOUT_gm 0x60 /* RTC Clock Output Enable group mask. */ -+#define PORTCFG_RTCOUT_gp 5 /* RTC Clock Output Enable group position. */ -+#define PORTCFG_RTCOUT0_bm (1<<5) /* RTC Clock Output Enable bit 0 mask. */ -+#define PORTCFG_RTCOUT0_bp 5 /* RTC Clock Output Enable bit 0 position. */ -+#define PORTCFG_RTCOUT1_bm (1<<6) /* RTC Clock Output Enable bit 1 mask. */ -+#define PORTCFG_RTCOUT1_bp 6 /* RTC Clock Output Enable bit 1 position. */ -+ -+#define PORTCFG_CLKOUTSEL_gm 0x0C /* Clock Output Select group mask. */ -+#define PORTCFG_CLKOUTSEL_gp 2 /* Clock Output Select group position. */ -+#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Clock Output Select bit 0 mask. */ -+#define PORTCFG_CLKOUTSEL0_bp 2 /* Clock Output Select bit 0 position. */ -+#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Clock Output Select bit 1 mask. */ -+#define PORTCFG_CLKOUTSEL1_bp 3 /* Clock Output Select bit 1 position. */ -+ -+#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ -+ -+/* PORTCFG.ACEVOUT bit masks and bit positions */ -+#define PORTCFG_ACOUT_gm 0xC0 /* Analog Comparator Output Port group mask. */ -+#define PORTCFG_ACOUT_gp 6 /* Analog Comparator Output Port group position. */ -+#define PORTCFG_ACOUT0_bm (1<<6) /* Analog Comparator Output Port bit 0 mask. */ -+#define PORTCFG_ACOUT0_bp 6 /* Analog Comparator Output Port bit 0 position. */ -+#define PORTCFG_ACOUT1_bm (1<<7) /* Analog Comparator Output Port bit 1 mask. */ -+#define PORTCFG_ACOUT1_bp 7 /* Analog Comparator Output Port bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Channel Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Channel Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Channel Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Channel Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Channel Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Channel Output Port bit 1 position. */ -+ -+#define PORTCFG_EVASYEN_bm 0x08 /* Asynchronous Event Enabled bit mask. */ -+#define PORTCFG_EVASYEN_bp 3 /* Asynchronous Event Enabled bit position. */ -+ -+#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Channel Output Selection group mask. */ -+#define PORTCFG_EVOUTSEL_gp 0 /* Event Channel Output Selection group position. */ -+#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Channel Output Selection bit 0 mask. */ -+#define PORTCFG_EVOUTSEL0_bp 0 /* Event Channel Output Selection bit 0 position. */ -+#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Channel Output Selection bit 1 mask. */ -+#define PORTCFG_EVOUTSEL1_bp 1 /* Event Channel Output Selection bit 1 position. */ -+#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Channel Output Selection bit 2 mask. */ -+#define PORTCFG_EVOUTSEL2_bp 2 /* Event Channel Output Selection bit 2 position. */ -+ -+/* PORTCFG.SRLCTRL bit masks and bit positions */ -+#define PORTCFG_SRLENRA_bm 0x01 /* Slew Rate Limit Enable on PORTA bit mask. */ -+#define PORTCFG_SRLENRA_bp 0 /* Slew Rate Limit Enable on PORTA bit position. */ -+ -+#define PORTCFG_SRLENRC_bm 0x04 /* Slew Rate Limit Enable on PORTC bit mask. */ -+#define PORTCFG_SRLENRC_bp 2 /* Slew Rate Limit Enable on PORTC bit position. */ -+ -+#define PORTCFG_SRLENRD_bm 0x08 /* Slew Rate Limit Enable on PORTD bit mask. */ -+#define PORTCFG_SRLENRD_bp 3 /* Slew Rate Limit Enable on PORTD bit position. */ -+ -+#define PORTCFG_SRLENRR_bm 0x80 /* Slew Rate Limit Enable on PORTR bit mask. */ -+#define PORTCFG_SRLENRR_bp 7 /* Slew Rate Limit Enable on PORTR bit position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* EDMA - Enhanced DMA Controller */ -+/* EDMA.CTRL bit masks and bit positions */ -+#define EDMA_ENABLE_bm 0x80 /* Enable bit mask. */ -+#define EDMA_ENABLE_bp 7 /* Enable bit position. */ -+ -+#define EDMA_RESET_bm 0x40 /* Software Reset bit mask. */ -+#define EDMA_RESET_bp 6 /* Software Reset bit position. */ -+ -+#define EDMA_CHMODE_gm 0x30 /* Channel Mode group mask. */ -+#define EDMA_CHMODE_gp 4 /* Channel Mode group position. */ -+#define EDMA_CHMODE0_bm (1<<4) /* Channel Mode bit 0 mask. */ -+#define EDMA_CHMODE0_bp 4 /* Channel Mode bit 0 position. */ -+#define EDMA_CHMODE1_bm (1<<5) /* Channel Mode bit 1 mask. */ -+#define EDMA_CHMODE1_bp 5 /* Channel Mode bit 1 position. */ -+ -+#define EDMA_DBUFMODE_gm 0x0C /* Double Buffer Mode group mask. */ -+#define EDMA_DBUFMODE_gp 2 /* Double Buffer Mode group position. */ -+#define EDMA_DBUFMODE0_bm (1<<2) /* Double Buffer Mode bit 0 mask. */ -+#define EDMA_DBUFMODE0_bp 2 /* Double Buffer Mode bit 0 position. */ -+#define EDMA_DBUFMODE1_bm (1<<3) /* Double Buffer Mode bit 1 mask. */ -+#define EDMA_DBUFMODE1_bp 3 /* Double Buffer Mode bit 1 position. */ -+ -+#define EDMA_PRIMODE_gm 0x03 /* Priority Mode group mask. */ -+#define EDMA_PRIMODE_gp 0 /* Priority Mode group position. */ -+#define EDMA_PRIMODE0_bm (1<<0) /* Priority Mode bit 0 mask. */ -+#define EDMA_PRIMODE0_bp 0 /* Priority Mode bit 0 position. */ -+#define EDMA_PRIMODE1_bm (1<<1) /* Priority Mode bit 1 mask. */ -+#define EDMA_PRIMODE1_bp 1 /* Priority Mode bit 1 position. */ -+ -+/* EDMA.INTFLAGS bit masks and bit positions */ -+#define EDMA_CH3ERRIF_bm 0x80 /* Channel 3 Transaction Error Interrupt Flag bit mask. */ -+#define EDMA_CH3ERRIF_bp 7 /* Channel 3 Transaction Error Interrupt Flag bit position. */ -+ -+#define EDMA_CH2ERRIF_bm 0x40 /* Channel 2 Transaction Error Interrupt Flag bit mask. */ -+#define EDMA_CH2ERRIF_bp 6 /* Channel 2 Transaction Error Interrupt Flag bit position. */ -+ -+#define EDMA_CH1ERRIF_bm 0x20 /* Channel 1 Transaction Error Interrupt Flag bit mask. */ -+#define EDMA_CH1ERRIF_bp 5 /* Channel 1 Transaction Error Interrupt Flag bit position. */ -+ -+#define EDMA_CH0ERRIF_bm 0x10 /* Channel 0 Transaction Error Interrupt Flag bit mask. */ -+#define EDMA_CH0ERRIF_bp 4 /* Channel 0 Transaction Error Interrupt Flag bit position. */ -+ -+#define EDMA_CH3TRNFIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -+#define EDMA_CH3TRNFIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ -+ -+#define EDMA_CH2TRNFIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -+#define EDMA_CH2TRNFIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ -+ -+#define EDMA_CH1TRNFIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -+#define EDMA_CH1TRNFIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ -+ -+#define EDMA_CH0TRNFIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -+#define EDMA_CH0TRNFIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ -+ -+/* EDMA.STATUS bit masks and bit positions */ -+#define EDMA_CH3BUSY_bm 0x80 /* Channel 3 Busy Flag bit mask. */ -+#define EDMA_CH3BUSY_bp 7 /* Channel 3 Busy Flag bit position. */ -+ -+#define EDMA_CH2BUSY_bm 0x40 /* Channel 2 Busy Flag bit mask. */ -+#define EDMA_CH2BUSY_bp 6 /* Channel 2 Busy Flag bit position. */ -+ -+#define EDMA_CH1BUSY_bm 0x20 /* Channel 1 Busy Flag bit mask. */ -+#define EDMA_CH1BUSY_bp 5 /* Channel 1 Busy Flag bit position. */ -+ -+#define EDMA_CH0BUSY_bm 0x10 /* Channel 0 Busy Flag bit mask. */ -+#define EDMA_CH0BUSY_bp 4 /* Channel 0 Busy Flag bit position. */ -+ -+#define EDMA_CH3PEND_bm 0x08 /* Channel 3 Pending Flag bit mask. */ -+#define EDMA_CH3PEND_bp 3 /* Channel 3 Pending Flag bit position. */ -+ -+#define EDMA_CH2PEND_bm 0x04 /* Channel 2 Pending Flag bit mask. */ -+#define EDMA_CH2PEND_bp 2 /* Channel 2 Pending Flag bit position. */ -+ -+#define EDMA_CH1PEND_bm 0x02 /* Channel 1 Pending Flag bit mask. */ -+#define EDMA_CH1PEND_bp 1 /* Channel 1 Pending Flag bit position. */ -+ -+#define EDMA_CH0PEND_bm 0x01 /* Channel 0 Pending Flag bit mask. */ -+#define EDMA_CH0PEND_bp 0 /* Channel 0 Pending Flag bit position. */ -+ -+/* EDMA_CH.CTRLA bit masks and bit positions */ -+#define EDMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -+#define EDMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ -+ -+#define EDMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -+#define EDMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ -+ -+#define EDMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -+#define EDMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ -+ -+#define EDMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -+#define EDMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ -+ -+#define EDMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -+#define EDMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ -+ -+#define EDMA_CH_BURSTLEN_bm 0x01 /* Channel 2-bytes Burst Length bit mask. */ -+#define EDMA_CH_BURSTLEN_bp 0 /* Channel 2-bytes Burst Length bit position. */ -+ -+/* EDMA_CH.CTRLB bit masks and bit positions */ -+#define EDMA_CH_CHBUSY_bm 0x80 /* Channel Block Transfer Busy bit mask. */ -+#define EDMA_CH_CHBUSY_bp 7 /* Channel Block Transfer Busy bit position. */ -+ -+#define EDMA_CH_CHPEND_bm 0x40 /* Channel Block Transfer Pending bit mask. */ -+#define EDMA_CH_CHPEND_bp 6 /* Channel Block Transfer Pending bit position. */ -+ -+#define EDMA_CH_ERRIF_bm 0x20 /* Channel Transaction Error Interrupt Flag bit mask. */ -+#define EDMA_CH_ERRIF_bp 5 /* Channel Transaction Error Interrupt Flag bit position. */ -+ -+#define EDMA_CH_TRNIF_bm 0x10 /* Channel Transaction Complete Interrup Flag bit mask. */ -+#define EDMA_CH_TRNIF_bp 4 /* Channel Transaction Complete Interrup Flag bit position. */ -+ -+#define EDMA_CH_ERRINTLVL_gm 0x0C /* Channel Transaction Error Interrupt Level group mask. */ -+#define EDMA_CH_ERRINTLVL_gp 2 /* Channel Transaction Error Interrupt Level group position. */ -+#define EDMA_CH_ERRINTLVL0_bm (1<<2) /* Channel Transaction Error Interrupt Level bit 0 mask. */ -+#define EDMA_CH_ERRINTLVL0_bp 2 /* Channel Transaction Error Interrupt Level bit 0 position. */ -+#define EDMA_CH_ERRINTLVL1_bm (1<<3) /* Channel Transaction Error Interrupt Level bit 1 mask. */ -+#define EDMA_CH_ERRINTLVL1_bp 3 /* Channel Transaction Error Interrupt Level bit 1 position. */ -+ -+#define EDMA_CH_TRNINTLVL_gm 0x03 /* Channel Transaction Complete Interrupt Level group mask. */ -+#define EDMA_CH_TRNINTLVL_gp 0 /* Channel Transaction Complete Interrupt Level group position. */ -+#define EDMA_CH_TRNINTLVL0_bm (1<<0) /* Channel Transaction Complete Interrupt Level bit 0 mask. */ -+#define EDMA_CH_TRNINTLVL0_bp 0 /* Channel Transaction Complete Interrupt Level bit 0 position. */ -+#define EDMA_CH_TRNINTLVL1_bm (1<<1) /* Channel Transaction Complete Interrupt Level bit 1 mask. */ -+#define EDMA_CH_TRNINTLVL1_bp 1 /* Channel Transaction Complete Interrupt Level bit 1 position. */ -+ -+/* EDMA_CH.ADDRCTRL bit masks and bit positions */ -+#define EDMA_CH_RELOAD_gm 0x30 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group mask. */ -+#define EDMA_CH_RELOAD_gp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group position. */ -+#define EDMA_CH_RELOAD0_bm (1<<4) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 mask. */ -+#define EDMA_CH_RELOAD0_bp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 position. */ -+#define EDMA_CH_RELOAD1_bm (1<<5) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 mask. */ -+#define EDMA_CH_RELOAD1_bp 5 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 position. */ -+ -+#define EDMA_CH_DIR_gm 0x07 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group mask. */ -+#define EDMA_CH_DIR_gp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group position. */ -+#define EDMA_CH_DIR0_bm (1<<0) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 mask. */ -+#define EDMA_CH_DIR0_bp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 position. */ -+#define EDMA_CH_DIR1_bm (1<<1) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 mask. */ -+#define EDMA_CH_DIR1_bp 1 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 position. */ -+#define EDMA_CH_DIR2_bm (1<<2) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 mask. */ -+#define EDMA_CH_DIR2_bp 2 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 position. */ -+ -+/* EDMA_CH.DESTADDRCTRL bit masks and bit positions */ -+#define EDMA_CH_DESTRELOAD_gm 0x30 /* Destination Address Reload for Standard Channels Only. group mask. */ -+#define EDMA_CH_DESTRELOAD_gp 4 /* Destination Address Reload for Standard Channels Only. group position. */ -+#define EDMA_CH_DESTRELOAD0_bm (1<<4) /* Destination Address Reload for Standard Channels Only. bit 0 mask. */ -+#define EDMA_CH_DESTRELOAD0_bp 4 /* Destination Address Reload for Standard Channels Only. bit 0 position. */ -+#define EDMA_CH_DESTRELOAD1_bm (1<<5) /* Destination Address Reload for Standard Channels Only. bit 1 mask. */ -+#define EDMA_CH_DESTRELOAD1_bp 5 /* Destination Address Reload for Standard Channels Only. bit 1 position. */ -+ -+#define EDMA_CH_DESTDIR_gm 0x07 /* Destination Address Mode for Standard Channels Only. group mask. */ -+#define EDMA_CH_DESTDIR_gp 0 /* Destination Address Mode for Standard Channels Only. group position. */ -+#define EDMA_CH_DESTDIR0_bm (1<<0) /* Destination Address Mode for Standard Channels Only. bit 0 mask. */ -+#define EDMA_CH_DESTDIR0_bp 0 /* Destination Address Mode for Standard Channels Only. bit 0 position. */ -+#define EDMA_CH_DESTDIR1_bm (1<<1) /* Destination Address Mode for Standard Channels Only. bit 1 mask. */ -+#define EDMA_CH_DESTDIR1_bp 1 /* Destination Address Mode for Standard Channels Only. bit 1 position. */ -+#define EDMA_CH_DESTDIR2_bm (1<<2) /* Destination Address Mode for Standard Channels Only. bit 2 mask. */ -+#define EDMA_CH_DESTDIR2_bp 2 /* Destination Address Mode for Standard Channels Only. bit 2 position. */ -+ -+/* EDMA_CH.TRIGSRC bit masks and bit positions */ -+#define EDMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -+#define EDMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -+#define EDMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -+#define EDMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -+#define EDMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -+#define EDMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -+#define EDMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -+#define EDMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -+#define EDMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -+#define EDMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -+#define EDMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -+#define EDMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -+#define EDMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -+#define EDMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -+#define EDMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -+#define EDMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -+#define EDMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -+#define EDMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH4MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH5MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH6MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH7MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_ROTARY_bm 0x80 /* Rotary Decoder Enable bit mask. */ -+#define EVSYS_ROTARY_bp 7 /* Rotary Decoder Enable bit position. */ -+ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH4CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH5CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH6CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH7CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.DFCTRL bit masks and bit positions */ -+#define EVSYS_PRESCFILT_gm 0xF0 /* Prescaler Filter group mask. */ -+#define EVSYS_PRESCFILT_gp 4 /* Prescaler Filter group position. */ -+#define EVSYS_PRESCFILT0_bm (1<<4) /* Prescaler Filter bit 0 mask. */ -+#define EVSYS_PRESCFILT0_bp 4 /* Prescaler Filter bit 0 position. */ -+#define EVSYS_PRESCFILT1_bm (1<<5) /* Prescaler Filter bit 1 mask. */ -+#define EVSYS_PRESCFILT1_bp 5 /* Prescaler Filter bit 1 position. */ -+#define EVSYS_PRESCFILT2_bm (1<<6) /* Prescaler Filter bit 2 mask. */ -+#define EVSYS_PRESCFILT2_bp 6 /* Prescaler Filter bit 2 position. */ -+#define EVSYS_PRESCFILT3_bm (1<<7) /* Prescaler Filter bit 3 mask. */ -+#define EVSYS_PRESCFILT3_bp 7 /* Prescaler Filter bit 3 position. */ -+ -+#define EVSYS_FILTSEL_bm 0x08 /* Prescaler Filter Select bit mask. */ -+#define EVSYS_FILTSEL_bp 3 /* Prescaler Filter Select bit position. */ -+ -+#define EVSYS_PRESC_gm 0x07 /* Prescaler group mask. */ -+#define EVSYS_PRESC_gp 0 /* Prescaler group position. */ -+#define EVSYS_PRESC0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define EVSYS_PRESC0_bp 0 /* Prescaler bit 0 position. */ -+#define EVSYS_PRESC1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define EVSYS_PRESC1_bp 1 /* Prescaler bit 1 position. */ -+#define EVSYS_PRESC2_bm (1<<2) /* Prescaler bit 2 mask. */ -+#define EVSYS_PRESC2_bp 2 /* Prescaler bit 2 position. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0x7F /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC Input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC Input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC Input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC Input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC Input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC Input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC Input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC Input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC Input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC Input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC Input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC Input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC Input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC Input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC Input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC Input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC Input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC Input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC Input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC Input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC Input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC Input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC Input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC Input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC Input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC Input bit 1 position. */ -+ -+#define ADC_CH_MUXNEGL_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group mask. */ -+#define ADC_CH_MUXNEGL_gp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group position. */ -+#define ADC_CH_MUXNEGL0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 mask. */ -+#define ADC_CH_MUXNEGL0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 position. */ -+#define ADC_CH_MUXNEGL1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 mask. */ -+#define ADC_CH_MUXNEGL1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 position. */ -+ -+#define ADC_CH_MUXNEGH_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group mask. */ -+#define ADC_CH_MUXNEGH_gp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group position. */ -+#define ADC_CH_MUXNEGH0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 mask. */ -+#define ADC_CH_MUXNEGH0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 position. */ -+#define ADC_CH_MUXNEGH1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 mask. */ -+#define ADC_CH_MUXNEGH1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_IF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_IF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_INPUTOFFSET_gm 0xF0 /* Positive MUX Setting Offset group mask. */ -+#define ADC_CH_INPUTOFFSET_gp 4 /* Positive MUX Setting Offset group position. */ -+#define ADC_CH_INPUTOFFSET0_bm (1<<4) /* Positive MUX Setting Offset bit 0 mask. */ -+#define ADC_CH_INPUTOFFSET0_bp 4 /* Positive MUX Setting Offset bit 0 position. */ -+#define ADC_CH_INPUTOFFSET1_bm (1<<5) /* Positive MUX Setting Offset bit 1 mask. */ -+#define ADC_CH_INPUTOFFSET1_bp 5 /* Positive MUX Setting Offset bit 1 position. */ -+#define ADC_CH_INPUTOFFSET2_bm (1<<6) /* Positive MUX Setting Offset bit 2 mask. */ -+#define ADC_CH_INPUTOFFSET2_bp 6 /* Positive MUX Setting Offset bit 2 position. */ -+#define ADC_CH_INPUTOFFSET3_bm (1<<7) /* Positive MUX Setting Offset bit 3 mask. */ -+#define ADC_CH_INPUTOFFSET3_bp 7 /* Positive MUX Setting Offset bit 3 position. */ -+ -+#define ADC_CH_INPUTSCAN_gm 0x0F /* Number of Channels Included in Scan group mask. */ -+#define ADC_CH_INPUTSCAN_gp 0 /* Number of Channels Included in Scan group position. */ -+#define ADC_CH_INPUTSCAN0_bm (1<<0) /* Number of Channels Included in Scan bit 0 mask. */ -+#define ADC_CH_INPUTSCAN0_bp 0 /* Number of Channels Included in Scan bit 0 position. */ -+#define ADC_CH_INPUTSCAN1_bm (1<<1) /* Number of Channels Included in Scan bit 1 mask. */ -+#define ADC_CH_INPUTSCAN1_bp 1 /* Number of Channels Included in Scan bit 1 position. */ -+#define ADC_CH_INPUTSCAN2_bm (1<<2) /* Number of Channels Included in Scan bit 2 mask. */ -+#define ADC_CH_INPUTSCAN2_bp 2 /* Number of Channels Included in Scan bit 2 position. */ -+#define ADC_CH_INPUTSCAN3_bm (1<<3) /* Number of Channels Included in Scan bit 3 mask. */ -+#define ADC_CH_INPUTSCAN3_bp 3 /* Number of Channels Included in Scan bit 3 position. */ -+ -+/* ADC_CH.CORRCTRL bit masks and bit positions */ -+#define ADC_CH_CORREN_bm 0x01 /* Correction Enable bit mask. */ -+#define ADC_CH_CORREN_bp 0 /* Correction Enable bit position. */ -+ -+/* ADC_CH.OFFSETCORR1 bit masks and bit positions */ -+#define ADC_CH_OFFSETCORR_gm 0x0F /* Offset Correction Byte 1 group mask. */ -+#define ADC_CH_OFFSETCORR_gp 0 /* Offset Correction Byte 1 group position. */ -+#define ADC_CH_OFFSETCORR0_bm (1<<0) /* Offset Correction Byte 1 bit 0 mask. */ -+#define ADC_CH_OFFSETCORR0_bp 0 /* Offset Correction Byte 1 bit 0 position. */ -+#define ADC_CH_OFFSETCORR1_bm (1<<1) /* Offset Correction Byte 1 bit 1 mask. */ -+#define ADC_CH_OFFSETCORR1_bp 1 /* Offset Correction Byte 1 bit 1 position. */ -+#define ADC_CH_OFFSETCORR2_bm (1<<2) /* Offset Correction Byte 1 bit 2 mask. */ -+#define ADC_CH_OFFSETCORR2_bp 2 /* Offset Correction Byte 1 bit 2 position. */ -+#define ADC_CH_OFFSETCORR3_bm (1<<3) /* Offset Correction Byte 1 bit 3 mask. */ -+#define ADC_CH_OFFSETCORR3_bp 3 /* Offset Correction Byte 1 bit 3 position. */ -+ -+/* ADC_CH.GAINCORR1 bit masks and bit positions */ -+#define ADC_CH_GAINCORR_gm 0x0F /* Gain Correction Byte 1 group mask. */ -+#define ADC_CH_GAINCORR_gp 0 /* Gain Correction Byte 1 group position. */ -+#define ADC_CH_GAINCORR0_bm (1<<0) /* Gain Correction Byte 1 bit 0 mask. */ -+#define ADC_CH_GAINCORR0_bp 0 /* Gain Correction Byte 1 bit 0 position. */ -+#define ADC_CH_GAINCORR1_bm (1<<1) /* Gain Correction Byte 1 bit 1 mask. */ -+#define ADC_CH_GAINCORR1_bp 1 /* Gain Correction Byte 1 bit 1 position. */ -+#define ADC_CH_GAINCORR2_bm (1<<2) /* Gain Correction Byte 1 bit 2 mask. */ -+#define ADC_CH_GAINCORR2_bp 2 /* Gain Correction Byte 1 bit 2 position. */ -+#define ADC_CH_GAINCORR3_bm (1<<3) /* Gain Correction Byte 1 bit 3 mask. */ -+#define ADC_CH_GAINCORR3_bp 3 /* Gain Correction Byte 1 bit 3 position. */ -+ -+/* ADC_CH.AVGCTRL bit masks and bit positions */ -+#define ADC_CH_RIGHTSHIFT_gm 0x70 /* Right Shift group mask. */ -+#define ADC_CH_RIGHTSHIFT_gp 4 /* Right Shift group position. */ -+#define ADC_CH_RIGHTSHIFT0_bm (1<<4) /* Right Shift bit 0 mask. */ -+#define ADC_CH_RIGHTSHIFT0_bp 4 /* Right Shift bit 0 position. */ -+#define ADC_CH_RIGHTSHIFT1_bm (1<<5) /* Right Shift bit 1 mask. */ -+#define ADC_CH_RIGHTSHIFT1_bp 5 /* Right Shift bit 1 position. */ -+#define ADC_CH_RIGHTSHIFT2_bm (1<<6) /* Right Shift bit 2 mask. */ -+#define ADC_CH_RIGHTSHIFT2_bp 6 /* Right Shift bit 2 position. */ -+ -+#define ADC_CH_SAMPNUM_gm 0x0F /* Averaged Number of Samples group mask. */ -+#define ADC_CH_SAMPNUM_gp 0 /* Averaged Number of Samples group position. */ -+#define ADC_CH_SAMPNUM0_bm (1<<0) /* Averaged Number of Samples bit 0 mask. */ -+#define ADC_CH_SAMPNUM0_bp 0 /* Averaged Number of Samples bit 0 position. */ -+#define ADC_CH_SAMPNUM1_bm (1<<1) /* Averaged Number of Samples bit 1 mask. */ -+#define ADC_CH_SAMPNUM1_bp 1 /* Averaged Number of Samples bit 1 position. */ -+#define ADC_CH_SAMPNUM2_bm (1<<2) /* Averaged Number of Samples bit 2 mask. */ -+#define ADC_CH_SAMPNUM2_bp 2 /* Averaged Number of Samples bit 2 position. */ -+#define ADC_CH_SAMPNUM3_bm (1<<3) /* Averaged Number of Samples bit 3 mask. */ -+#define ADC_CH_SAMPNUM3_bp 3 /* Averaged Number of Samples bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_START_bm 0x04 /* Start Conversion bit mask. */ -+#define ADC_START_bp 2 /* Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -+#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -+#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* ADC.SAMPCTRL bit masks and bit positions */ -+#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ -+#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ -+#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ -+#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ -+#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ -+#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ -+#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ -+#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ -+#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ -+#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ -+#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ -+#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ -+#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ -+#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ -+ -+/* DAC - Digital/Analog Converter */ -+/* DAC.CTRLA bit masks and bit positions */ -+#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -+#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ -+ -+#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -+#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ -+ -+#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -+#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ -+ -+#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -+#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ -+ -+#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define DAC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* DAC.CTRLB bit masks and bit positions */ -+#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -+#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -+#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -+#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -+#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -+#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ -+ -+#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -+#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ -+ -+#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -+#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ -+ -+/* DAC.CTRLC bit masks and bit positions */ -+#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -+#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -+#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -+#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -+#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -+#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ -+ -+#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -+#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ -+ -+/* DAC.EVCTRL bit masks and bit positions */ -+#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -+#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ -+ -+#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -+#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -+#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -+#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -+#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -+#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -+#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -+#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ -+ -+/* DAC.STATUS bit masks and bit positions */ -+#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -+#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ -+ -+#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -+#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ -+ -+/* DAC.CH0GAINCAL bit masks and bit positions */ -+#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -+#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -+#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -+#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -+#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -+#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -+#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -+#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -+#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -+#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -+#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -+#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -+#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -+#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -+#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -+#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ -+ -+/* DAC.CH0OFFSETCAL bit masks and bit positions */ -+#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -+#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -+#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -+#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -+#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -+#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -+#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -+#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -+#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -+#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -+#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -+#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -+#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -+#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -+#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -+#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ -+ -+/* DAC.CH1GAINCAL bit masks and bit positions */ -+#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -+#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -+#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -+#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -+#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -+#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -+#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -+#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -+#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -+#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -+#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -+#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -+#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -+#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -+#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -+#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ -+ -+/* DAC.CH1OFFSETCAL bit masks and bit positions */ -+#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -+#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -+#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -+#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -+#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -+#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -+#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -+#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -+#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -+#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -+#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -+#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -+#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -+#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -+#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -+#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1INVEN_bm 0x08 /* Analog Comparator 1 Output Invert Enable bit mask. */ -+#define AC_AC1INVEN_bp 3 /* Analog Comparator 1 Output Invert Enable bit position. */ -+ -+#define AC_AC0INVEN_bm 0x04 /* Analog Comparator 0 Output Invert Enable bit mask. */ -+#define AC_AC0INVEN_bp 2 /* Analog Comparator 0 Output Invert Enable bit position. */ -+ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* AC.CURRCTRL bit masks and bit positions */ -+#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ -+#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ -+ -+#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ -+#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ -+ -+#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ -+#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ -+ -+#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ -+#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ -+ -+/* AC.CURRCALIB bit masks and bit positions */ -+#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ -+#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ -+#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ -+#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ -+#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ -+#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ -+#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ -+#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ -+#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ -+#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ -+ -+/* RTC - Real-Time Clounter */ -+/* RTC.CTRL bit masks and bit positions */ -+#define RTC_CORREN_bm 0x08 /* Correction Enable bit mask. */ -+#define RTC_CORREN_bp 3 /* Correction Enable bit position. */ -+ -+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ -+ -+/* RTC.STATUS bit masks and bit positions */ -+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC.INTCTRL bit masks and bit positions */ -+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC.INTFLAGS bit masks and bit positions */ -+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* RTC.CALIB bit masks and bit positions */ -+#define RTC_SIGN_bm 0x80 /* Correction Sign bit mask. */ -+#define RTC_SIGN_bp 7 /* Correction Sign bit position. */ -+ -+#define RTC_ERROR_gm 0x7F /* Error Value group mask. */ -+#define RTC_ERROR_gp 0 /* Error Value group position. */ -+#define RTC_ERROR0_bm (1<<0) /* Error Value bit 0 mask. */ -+#define RTC_ERROR0_bp 0 /* Error Value bit 0 position. */ -+#define RTC_ERROR1_bm (1<<1) /* Error Value bit 1 mask. */ -+#define RTC_ERROR1_bp 1 /* Error Value bit 1 position. */ -+#define RTC_ERROR2_bm (1<<2) /* Error Value bit 2 mask. */ -+#define RTC_ERROR2_bp 2 /* Error Value bit 2 position. */ -+#define RTC_ERROR3_bm (1<<3) /* Error Value bit 3 mask. */ -+#define RTC_ERROR3_bp 3 /* Error Value bit 3 position. */ -+#define RTC_ERROR4_bm (1<<4) /* Error Value bit 4 mask. */ -+#define RTC_ERROR4_bp 4 /* Error Value bit 4 position. */ -+#define RTC_ERROR5_bm (1<<5) /* Error Value bit 5 mask. */ -+#define RTC_ERROR5_bp 5 /* Error Value bit 5 position. */ -+#define RTC_ERROR6_bm (1<<6) /* Error Value bit 6 mask. */ -+#define RTC_ERROR6_bp 6 /* Error Value bit 6 position. */ -+ -+/* XCL - XMEGA Custom Logic */ -+/* XCL.CTRLA bit masks and bit positions */ -+#define XCL_LUT0OUTEN_gm 0xC0 /* LUT0 Output Enable group mask. */ -+#define XCL_LUT0OUTEN_gp 6 /* LUT0 Output Enable group position. */ -+#define XCL_LUT0OUTEN0_bm (1<<6) /* LUT0 Output Enable bit 0 mask. */ -+#define XCL_LUT0OUTEN0_bp 6 /* LUT0 Output Enable bit 0 position. */ -+#define XCL_LUT0OUTEN1_bm (1<<7) /* LUT0 Output Enable bit 1 mask. */ -+#define XCL_LUT0OUTEN1_bp 7 /* LUT0 Output Enable bit 1 position. */ -+ -+#define XCL_PORTSEL_gm 0x30 /* Port Selection group mask. */ -+#define XCL_PORTSEL_gp 4 /* Port Selection group position. */ -+#define XCL_PORTSEL0_bm (1<<4) /* Port Selection bit 0 mask. */ -+#define XCL_PORTSEL0_bp 4 /* Port Selection bit 0 position. */ -+#define XCL_PORTSEL1_bm (1<<5) /* Port Selection bit 1 mask. */ -+#define XCL_PORTSEL1_bp 5 /* Port Selection bit 1 position. */ -+ -+#define XCL_LUTCONF_gm 0x07 /* LUT Configuration group mask. */ -+#define XCL_LUTCONF_gp 0 /* LUT Configuration group position. */ -+#define XCL_LUTCONF0_bm (1<<0) /* LUT Configuration bit 0 mask. */ -+#define XCL_LUTCONF0_bp 0 /* LUT Configuration bit 0 position. */ -+#define XCL_LUTCONF1_bm (1<<1) /* LUT Configuration bit 1 mask. */ -+#define XCL_LUTCONF1_bp 1 /* LUT Configuration bit 1 position. */ -+#define XCL_LUTCONF2_bm (1<<2) /* LUT Configuration bit 2 mask. */ -+#define XCL_LUTCONF2_bp 2 /* LUT Configuration bit 2 position. */ -+ -+/* XCL.CTRLB bit masks and bit positions */ -+#define XCL_IN3SEL_gm 0xC0 /* Input Selection 3 group mask. */ -+#define XCL_IN3SEL_gp 6 /* Input Selection 3 group position. */ -+#define XCL_IN3SEL0_bm (1<<6) /* Input Selection 3 bit 0 mask. */ -+#define XCL_IN3SEL0_bp 6 /* Input Selection 3 bit 0 position. */ -+#define XCL_IN3SEL1_bm (1<<7) /* Input Selection 3 bit 1 mask. */ -+#define XCL_IN3SEL1_bp 7 /* Input Selection 3 bit 1 position. */ -+ -+#define XCL_IN2SEL_gm 0x30 /* Input Selection 2 group mask. */ -+#define XCL_IN2SEL_gp 4 /* Input Selection 2 group position. */ -+#define XCL_IN2SEL0_bm (1<<4) /* Input Selection 2 bit 0 mask. */ -+#define XCL_IN2SEL0_bp 4 /* Input Selection 2 bit 0 position. */ -+#define XCL_IN2SEL1_bm (1<<5) /* Input Selection 2 bit 1 mask. */ -+#define XCL_IN2SEL1_bp 5 /* Input Selection 2 bit 1 position. */ -+ -+#define XCL_IN1SEL_gm 0x0C /* Input Selection 1 group mask. */ -+#define XCL_IN1SEL_gp 2 /* Input Selection 1 group position. */ -+#define XCL_IN1SEL0_bm (1<<2) /* Input Selection 1 bit 0 mask. */ -+#define XCL_IN1SEL0_bp 2 /* Input Selection 1 bit 0 position. */ -+#define XCL_IN1SEL1_bm (1<<3) /* Input Selection 1 bit 1 mask. */ -+#define XCL_IN1SEL1_bp 3 /* Input Selection 1 bit 1 position. */ -+ -+#define XCL_IN0SEL_gm 0x03 /* Input Selection 0 group mask. */ -+#define XCL_IN0SEL_gp 0 /* Input Selection 0 group position. */ -+#define XCL_IN0SEL0_bm (1<<0) /* Input Selection 0 bit 0 mask. */ -+#define XCL_IN0SEL0_bp 0 /* Input Selection 0 bit 0 position. */ -+#define XCL_IN0SEL1_bm (1<<1) /* Input Selection 0 bit 1 mask. */ -+#define XCL_IN0SEL1_bp 1 /* Input Selection 0 bit 1 position. */ -+ -+/* XCL.CTRLC bit masks and bit positions */ -+#define XCL_EVASYSEL1_bm 0x80 /* Asynchronous Event Line Selection for LUT1 bit mask. */ -+#define XCL_EVASYSEL1_bp 7 /* Asynchronous Event Line Selection for LUT1 bit position. */ -+ -+#define XCL_EVASYSEL0_bm 0x40 /* Asynchronous Event Line Selection for LUT0 bit mask. */ -+#define XCL_EVASYSEL0_bp 6 /* Asynchronous Event Line Selection for LUT0 bit position. */ -+ -+#define XCL_DLYSEL_gm 0x30 /* Delay Selection group mask. */ -+#define XCL_DLYSEL_gp 4 /* Delay Selection group position. */ -+#define XCL_DLYSEL0_bm (1<<4) /* Delay Selection bit 0 mask. */ -+#define XCL_DLYSEL0_bp 4 /* Delay Selection bit 0 position. */ -+#define XCL_DLYSEL1_bm (1<<5) /* Delay Selection bit 1 mask. */ -+#define XCL_DLYSEL1_bp 5 /* Delay Selection bit 1 position. */ -+ -+#define XCL_DLY1CONF_gm 0x0C /* Delay Configuration on LUT1 group mask. */ -+#define XCL_DLY1CONF_gp 2 /* Delay Configuration on LUT1 group position. */ -+#define XCL_DLY1CONF0_bm (1<<2) /* Delay Configuration on LUT1 bit 0 mask. */ -+#define XCL_DLY1CONF0_bp 2 /* Delay Configuration on LUT1 bit 0 position. */ -+#define XCL_DLY1CONF1_bm (1<<3) /* Delay Configuration on LUT1 bit 1 mask. */ -+#define XCL_DLY1CONF1_bp 3 /* Delay Configuration on LUT1 bit 1 position. */ -+ -+#define XCL_DLY0CONF_gm 0x03 /* Delay Configuration on LUT0 group mask. */ -+#define XCL_DLY0CONF_gp 0 /* Delay Configuration on LUT0 group position. */ -+#define XCL_DLY0CONF0_bm (1<<0) /* Delay Configuration on LUT0 bit 0 mask. */ -+#define XCL_DLY0CONF0_bp 0 /* Delay Configuration on LUT0 bit 0 position. */ -+#define XCL_DLY0CONF1_bm (1<<1) /* Delay Configuration on LUT0 bit 1 mask. */ -+#define XCL_DLY0CONF1_bp 1 /* Delay Configuration on LUT0 bit 1 position. */ -+ -+/* XCL.CTRLD bit masks and bit positions */ -+#define XCL_TRUTH1_gm 0xF0 /* Truth Table of LUT1 group mask. */ -+#define XCL_TRUTH1_gp 4 /* Truth Table of LUT1 group position. */ -+#define XCL_TRUTH10_bm (1<<4) /* Truth Table of LUT1 bit 0 mask. */ -+#define XCL_TRUTH10_bp 4 /* Truth Table of LUT1 bit 0 position. */ -+#define XCL_TRUTH11_bm (1<<5) /* Truth Table of LUT1 bit 1 mask. */ -+#define XCL_TRUTH11_bp 5 /* Truth Table of LUT1 bit 1 position. */ -+#define XCL_TRUTH12_bm (1<<6) /* Truth Table of LUT1 bit 2 mask. */ -+#define XCL_TRUTH12_bp 6 /* Truth Table of LUT1 bit 2 position. */ -+#define XCL_TRUTH13_bm (1<<7) /* Truth Table of LUT1 bit 3 mask. */ -+#define XCL_TRUTH13_bp 7 /* Truth Table of LUT1 bit 3 position. */ -+ -+#define XCL_TRUTH0_gm 0x0F /* Truth Table of LUT0 group mask. */ -+#define XCL_TRUTH0_gp 0 /* Truth Table of LUT0 group position. */ -+#define XCL_TRUTH00_bm (1<<0) /* Truth Table of LUT0 bit 0 mask. */ -+#define XCL_TRUTH00_bp 0 /* Truth Table of LUT0 bit 0 position. */ -+#define XCL_TRUTH01_bm (1<<1) /* Truth Table of LUT0 bit 1 mask. */ -+#define XCL_TRUTH01_bp 1 /* Truth Table of LUT0 bit 1 position. */ -+#define XCL_TRUTH02_bm (1<<2) /* Truth Table of LUT0 bit 2 mask. */ -+#define XCL_TRUTH02_bp 2 /* Truth Table of LUT0 bit 2 position. */ -+#define XCL_TRUTH03_bm (1<<3) /* Truth Table of LUT0 bit 3 mask. */ -+#define XCL_TRUTH03_bp 3 /* Truth Table of LUT0 bit 3 position. */ -+ -+/* XCL.CTRLE bit masks and bit positions */ -+#define XCL_CMDSEL_bm 0x80 /* Timer/Counter Command Selection bit mask. */ -+#define XCL_CMDSEL_bp 7 /* Timer/Counter Command Selection bit position. */ -+ -+#define XCL_TCSEL_gm 0x70 /* Timer/Counter Selection group mask. */ -+#define XCL_TCSEL_gp 4 /* Timer/Counter Selection group position. */ -+#define XCL_TCSEL0_bm (1<<4) /* Timer/Counter Selection bit 0 mask. */ -+#define XCL_TCSEL0_bp 4 /* Timer/Counter Selection bit 0 position. */ -+#define XCL_TCSEL1_bm (1<<5) /* Timer/Counter Selection bit 1 mask. */ -+#define XCL_TCSEL1_bp 5 /* Timer/Counter Selection bit 1 position. */ -+#define XCL_TCSEL2_bm (1<<6) /* Timer/Counter Selection bit 2 mask. */ -+#define XCL_TCSEL2_bp 6 /* Timer/Counter Selection bit 2 position. */ -+ -+#define XCL_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define XCL_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define XCL_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define XCL_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define XCL_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define XCL_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define XCL_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define XCL_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define XCL_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define XCL_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* XCL.CTRLF bit masks and bit positions */ -+#define XCL_CMDEN_gm 0xC0 /* Command Enable group mask. */ -+#define XCL_CMDEN_gp 6 /* Command Enable group position. */ -+#define XCL_CMDEN0_bm (1<<6) /* Command Enable bit 0 mask. */ -+#define XCL_CMDEN0_bp 6 /* Command Enable bit 0 position. */ -+#define XCL_CMDEN1_bm (1<<7) /* Command Enable bit 1 mask. */ -+#define XCL_CMDEN1_bp 7 /* Command Enable bit 1 position. */ -+ -+#define XCL_CMP1_bm 0x20 /* Compare Channel 1 Output Value bit mask. */ -+#define XCL_CMP1_bp 5 /* Compare Channel 1 Output Value bit position. */ -+ -+#define XCL_CMP0_bm 0x10 /* Compare Channel 0 Output Value bit mask. */ -+#define XCL_CMP0_bp 4 /* Compare Channel 0 Output Value bit position. */ -+ -+#define XCL_CCEN1_bm 0x08 /* Compare or Capture Channel 1 Enable bit mask. */ -+#define XCL_CCEN1_bp 3 /* Compare or Capture Channel 1 Enable bit position. */ -+ -+#define XCL_CCEN0_bm 0x04 /* Compare or Capture Channel 0 Enable bit mask. */ -+#define XCL_CCEN0_bp 2 /* Compare or Capture Channel 0 Enable bit position. */ -+ -+#define XCL_MODE_gm 0x03 /* Timer/Counter Mode group mask. */ -+#define XCL_MODE_gp 0 /* Timer/Counter Mode group position. */ -+#define XCL_MODE0_bm (1<<0) /* Timer/Counter Mode bit 0 mask. */ -+#define XCL_MODE0_bp 0 /* Timer/Counter Mode bit 0 position. */ -+#define XCL_MODE1_bm (1<<1) /* Timer/Counter Mode bit 1 mask. */ -+#define XCL_MODE1_bp 1 /* Timer/Counter Mode bit 1 position. */ -+ -+/* XCL.CTRLG bit masks and bit positions */ -+#define XCL_EVACTEN_bm 0x80 /* Event Action Enable bit mask. */ -+#define XCL_EVACTEN_bp 7 /* Event Action Enable bit position. */ -+ -+#define XCL_EVACT1_gm 0x60 /* Event Action Selection on Timer/Counter 1 group mask. */ -+#define XCL_EVACT1_gp 5 /* Event Action Selection on Timer/Counter 1 group position. */ -+#define XCL_EVACT10_bm (1<<5) /* Event Action Selection on Timer/Counter 1 bit 0 mask. */ -+#define XCL_EVACT10_bp 5 /* Event Action Selection on Timer/Counter 1 bit 0 position. */ -+#define XCL_EVACT11_bm (1<<6) /* Event Action Selection on Timer/Counter 1 bit 1 mask. */ -+#define XCL_EVACT11_bp 6 /* Event Action Selection on Timer/Counter 1 bit 1 position. */ -+ -+#define XCL_EVACT0_gm 0x18 /* Event Action Selection on Timer/Counter 0 group mask. */ -+#define XCL_EVACT0_gp 3 /* Event Action Selection on Timer/Counter 0 group position. */ -+#define XCL_EVACT00_bm (1<<3) /* Event Action Selection on Timer/Counter 0 bit 0 mask. */ -+#define XCL_EVACT00_bp 3 /* Event Action Selection on Timer/Counter 0 bit 0 position. */ -+#define XCL_EVACT01_bm (1<<4) /* Event Action Selection on Timer/Counter 0 bit 1 mask. */ -+#define XCL_EVACT01_bp 4 /* Event Action Selection on Timer/Counter 0 bit 1 position. */ -+ -+#define XCL_EVSRC_gm 0x07 /* Event Source Selection group mask. */ -+#define XCL_EVSRC_gp 0 /* Event Source Selection group position. */ -+#define XCL_EVSRC0_bm (1<<0) /* Event Source Selection bit 0 mask. */ -+#define XCL_EVSRC0_bp 0 /* Event Source Selection bit 0 position. */ -+#define XCL_EVSRC1_bm (1<<1) /* Event Source Selection bit 1 mask. */ -+#define XCL_EVSRC1_bp 1 /* Event Source Selection bit 1 position. */ -+#define XCL_EVSRC2_bm (1<<2) /* Event Source Selection bit 2 mask. */ -+#define XCL_EVSRC2_bp 2 /* Event Source Selection bit 2 position. */ -+ -+/* XCL.INTCTRL bit masks and bit positions */ -+#define XCL_UNF1IE_bm 0x80 /* Underflow 1 Interrupt Enable bit mask. */ -+#define XCL_UNF1IE_bp 7 /* Underflow 1 Interrupt Enable bit position. */ -+ -+#define XCL_PEC1IE_bm 0x80 /* Peripheral Counter 1 Interrupt Enable bit mask. */ -+#define XCL_PEC1IE_bp 7 /* Peripheral Counter 1 Interrupt Enable bit position. */ -+ -+#define XCL_PEC21IE_bm 0x80 /* Peripheral High Counter 2 Interrupt Enable bit mask. */ -+#define XCL_PEC21IE_bp 7 /* Peripheral High Counter 2 Interrupt Enable bit position. */ -+ -+#define XCL_UNF0IE_bm 0x40 /* Underflow 0 Interrupt Enable bit mask. */ -+#define XCL_UNF0IE_bp 6 /* Underflow 0 Interrupt Enable bit position. */ -+ -+#define XCL_PEC0IE_bm 0x40 /* Peripheral Counter 0 Interrupt Enable bit mask. */ -+#define XCL_PEC0IE_bp 6 /* Peripheral Counter 0 Interrupt Enable bit position. */ -+ -+#define XCL_CC1IE_bm 0x20 /* Compare Or Capture 1 Interrupt Enable bit mask. */ -+#define XCL_CC1IE_bp 5 /* Compare Or Capture 1 Interrupt Enable bit position. */ -+ -+#define XCL_PEC20IE_bm 0x20 /* Peripheral Low Counter 2 Interrupt Enable bit mask. */ -+#define XCL_PEC20IE_bp 5 /* Peripheral Low Counter 2 Interrupt Enable bit position. */ -+ -+#define XCL_CC0IE_bm 0x10 /* Compare Or Capture 0 Interrupt Enable bit mask. */ -+#define XCL_CC0IE_bp 4 /* Compare Or Capture 0 Interrupt Enable bit position. */ -+ -+#define XCL_UNFINTLVL_gm 0x0C /* Timer Underflow Interrupt Level group mask. */ -+#define XCL_UNFINTLVL_gp 2 /* Timer Underflow Interrupt Level group position. */ -+#define XCL_UNFINTLVL0_bm (1<<2) /* Timer Underflow Interrupt Level bit 0 mask. */ -+#define XCL_UNFINTLVL0_bp 2 /* Timer Underflow Interrupt Level bit 0 position. */ -+#define XCL_UNFINTLVL1_bm (1<<3) /* Timer Underflow Interrupt Level bit 1 mask. */ -+#define XCL_UNFINTLVL1_bp 3 /* Timer Underflow Interrupt Level bit 1 position. */ -+ -+#define XCL_CCINTLVL_gm 0x03 /* Timer Compare or Capture Interrupt Level group mask. */ -+#define XCL_CCINTLVL_gp 0 /* Timer Compare or Capture Interrupt Level group position. */ -+#define XCL_CCINTLVL0_bm (1<<0) /* Timer Compare or Capture Interrupt Level bit 0 mask. */ -+#define XCL_CCINTLVL0_bp 0 /* Timer Compare or Capture Interrupt Level bit 0 position. */ -+#define XCL_CCINTLVL1_bm (1<<1) /* Timer Compare or Capture Interrupt Level bit 1 mask. */ -+#define XCL_CCINTLVL1_bp 1 /* Timer Compare or Capture Interrupt Level bit 1 position. */ -+ -+/* XCL.INTFLAGS bit masks and bit positions */ -+#define XCL_UNF1IF_bm 0x80 /* Timer/Counter 1 Underflow Interrupt Flag bit mask. */ -+#define XCL_UNF1IF_bp 7 /* Timer/Counter 1 Underflow Interrupt Flag bit position. */ -+ -+#define XCL_PEC1IF_bm 0x80 /* Peripheral Counter 1 Interrupt Flag bit mask. */ -+#define XCL_PEC1IF_bp 7 /* Peripheral Counter 1 Interrupt Flag bit position. */ -+ -+#define XCL_PEC21IF_bm 0x80 /* Peripheral High Counter 2 Interrupt Flag bit mask. */ -+#define XCL_PEC21IF_bp 7 /* Peripheral High Counter 2 Interrupt Flag bit position. */ -+ -+#define XCL_UNF0IF_bm 0x40 /* Timer/Counter 0 Underflow Interrupt Flag bit mask. */ -+#define XCL_UNF0IF_bp 6 /* Timer/Counter 0 Underflow Interrupt Flag bit position. */ -+ -+#define XCL_PEC0IF_bm 0x40 /* Peripheral Counter 0 Interrupt Flag bit mask. */ -+#define XCL_PEC0IF_bp 6 /* Peripheral Counter 0 Interrupt Flag bit position. */ -+ -+#define XCL_CC1IF_bm 0x20 /* Compare or Capture Channel 1 Interrupt Flag bit mask. */ -+#define XCL_CC1IF_bp 5 /* Compare or Capture Channel 1 Interrupt Flag bit position. */ -+ -+#define XCL_PEC20IF_bm 0x20 /* Peripheral Low Counter 2 Interrupt Flag bit mask. */ -+#define XCL_PEC20IF_bp 5 /* Peripheral Low Counter 2 Interrupt Flag bit position. */ -+ -+#define XCL_CC0IF_bm 0x10 /* Compare or Capture Channel 0 Interrupt Flag bit mask. */ -+#define XCL_CC0IF_bp 4 /* Compare or Capture Channel 0 Interrupt Flag bit position. */ -+ -+/* XCL.PLC bit masks and bit positions */ -+#define XCL_PLC_gm 0xFF /* Peripheral Lenght Control Bits group mask. */ -+#define XCL_PLC_gp 0 /* Peripheral Lenght Control Bits group position. */ -+#define XCL_PLC0_bm (1<<0) /* Peripheral Lenght Control Bits bit 0 mask. */ -+#define XCL_PLC0_bp 0 /* Peripheral Lenght Control Bits bit 0 position. */ -+#define XCL_PLC1_bm (1<<1) /* Peripheral Lenght Control Bits bit 1 mask. */ -+#define XCL_PLC1_bp 1 /* Peripheral Lenght Control Bits bit 1 position. */ -+#define XCL_PLC2_bm (1<<2) /* Peripheral Lenght Control Bits bit 2 mask. */ -+#define XCL_PLC2_bp 2 /* Peripheral Lenght Control Bits bit 2 position. */ -+#define XCL_PLC3_bm (1<<3) /* Peripheral Lenght Control Bits bit 3 mask. */ -+#define XCL_PLC3_bp 3 /* Peripheral Lenght Control Bits bit 3 position. */ -+#define XCL_PLC4_bm (1<<4) /* Peripheral Lenght Control Bits bit 4 mask. */ -+#define XCL_PLC4_bp 4 /* Peripheral Lenght Control Bits bit 4 position. */ -+#define XCL_PLC5_bm (1<<5) /* Peripheral Lenght Control Bits bit 5 mask. */ -+#define XCL_PLC5_bp 5 /* Peripheral Lenght Control Bits bit 5 position. */ -+#define XCL_PLC6_bm (1<<6) /* Peripheral Lenght Control Bits bit 6 mask. */ -+#define XCL_PLC6_bp 6 /* Peripheral Lenght Control Bits bit 6 position. */ -+#define XCL_PLC7_bm (1<<7) /* Peripheral Lenght Control Bits bit 7 mask. */ -+#define XCL_PLC7_bp 7 /* Peripheral Lenght Control Bits bit 7 position. */ -+ -+/* XCL.CNTL bit masks and bit positions */ -+#define XCL_BCNTO_gm 0xFF /* BTC0 Counter Byte group mask. */ -+#define XCL_BCNTO_gp 0 /* BTC0 Counter Byte group position. */ -+#define XCL_BCNTO0_bm (1<<0) /* BTC0 Counter Byte bit 0 mask. */ -+#define XCL_BCNTO0_bp 0 /* BTC0 Counter Byte bit 0 position. */ -+#define XCL_BCNTO1_bm (1<<1) /* BTC0 Counter Byte bit 1 mask. */ -+#define XCL_BCNTO1_bp 1 /* BTC0 Counter Byte bit 1 position. */ -+#define XCL_BCNTO2_bm (1<<2) /* BTC0 Counter Byte bit 2 mask. */ -+#define XCL_BCNTO2_bp 2 /* BTC0 Counter Byte bit 2 position. */ -+#define XCL_BCNTO3_bm (1<<3) /* BTC0 Counter Byte bit 3 mask. */ -+#define XCL_BCNTO3_bp 3 /* BTC0 Counter Byte bit 3 position. */ -+#define XCL_BCNTO4_bm (1<<4) /* BTC0 Counter Byte bit 4 mask. */ -+#define XCL_BCNTO4_bp 4 /* BTC0 Counter Byte bit 4 position. */ -+#define XCL_BCNTO5_bm (1<<5) /* BTC0 Counter Byte bit 5 mask. */ -+#define XCL_BCNTO5_bp 5 /* BTC0 Counter Byte bit 5 position. */ -+#define XCL_BCNTO6_bm (1<<6) /* BTC0 Counter Byte bit 6 mask. */ -+#define XCL_BCNTO6_bp 6 /* BTC0 Counter Byte bit 6 position. */ -+#define XCL_BCNTO7_bm (1<<7) /* BTC0 Counter Byte bit 7 mask. */ -+#define XCL_BCNTO7_bp 7 /* BTC0 Counter Byte bit 7 position. */ -+ -+#define XCL_CNTL_gm 0xFF /* TC16 Counter Low Byte group mask. */ -+#define XCL_CNTL_gp 0 /* TC16 Counter Low Byte group position. */ -+#define XCL_CNTL0_bm (1<<0) /* TC16 Counter Low Byte bit 0 mask. */ -+#define XCL_CNTL0_bp 0 /* TC16 Counter Low Byte bit 0 position. */ -+#define XCL_CNTL1_bm (1<<1) /* TC16 Counter Low Byte bit 1 mask. */ -+#define XCL_CNTL1_bp 1 /* TC16 Counter Low Byte bit 1 position. */ -+#define XCL_CNTL2_bm (1<<2) /* TC16 Counter Low Byte bit 2 mask. */ -+#define XCL_CNTL2_bp 2 /* TC16 Counter Low Byte bit 2 position. */ -+#define XCL_CNTL3_bm (1<<3) /* TC16 Counter Low Byte bit 3 mask. */ -+#define XCL_CNTL3_bp 3 /* TC16 Counter Low Byte bit 3 position. */ -+#define XCL_CNTL4_bm (1<<4) /* TC16 Counter Low Byte bit 4 mask. */ -+#define XCL_CNTL4_bp 4 /* TC16 Counter Low Byte bit 4 position. */ -+#define XCL_CNTL5_bm (1<<5) /* TC16 Counter Low Byte bit 5 mask. */ -+#define XCL_CNTL5_bp 5 /* TC16 Counter Low Byte bit 5 position. */ -+#define XCL_CNTL6_bm (1<<6) /* TC16 Counter Low Byte bit 6 mask. */ -+#define XCL_CNTL6_bp 6 /* TC16 Counter Low Byte bit 6 position. */ -+#define XCL_CNTL7_bm (1<<7) /* TC16 Counter Low Byte bit 7 mask. */ -+#define XCL_CNTL7_bp 7 /* TC16 Counter Low Byte bit 7 position. */ -+ -+#define XCL_PCNTO_gm 0xFF /* Peripheral Counter 0 Byte group mask. */ -+#define XCL_PCNTO_gp 0 /* Peripheral Counter 0 Byte group position. */ -+#define XCL_PCNTO0_bm (1<<0) /* Peripheral Counter 0 Byte bit 0 mask. */ -+#define XCL_PCNTO0_bp 0 /* Peripheral Counter 0 Byte bit 0 position. */ -+#define XCL_PCNTO1_bm (1<<1) /* Peripheral Counter 0 Byte bit 1 mask. */ -+#define XCL_PCNTO1_bp 1 /* Peripheral Counter 0 Byte bit 1 position. */ -+#define XCL_PCNTO2_bm (1<<2) /* Peripheral Counter 0 Byte bit 2 mask. */ -+#define XCL_PCNTO2_bp 2 /* Peripheral Counter 0 Byte bit 2 position. */ -+#define XCL_PCNTO3_bm (1<<3) /* Peripheral Counter 0 Byte bit 3 mask. */ -+#define XCL_PCNTO3_bp 3 /* Peripheral Counter 0 Byte bit 3 position. */ -+#define XCL_PCNTO4_bm (1<<4) /* Peripheral Counter 0 Byte bit 4 mask. */ -+#define XCL_PCNTO4_bp 4 /* Peripheral Counter 0 Byte bit 4 position. */ -+#define XCL_PCNTO5_bm (1<<5) /* Peripheral Counter 0 Byte bit 5 mask. */ -+#define XCL_PCNTO5_bp 5 /* Peripheral Counter 0 Byte bit 5 position. */ -+#define XCL_PCNTO6_bm (1<<6) /* Peripheral Counter 0 Byte bit 6 mask. */ -+#define XCL_PCNTO6_bp 6 /* Peripheral Counter 0 Byte bit 6 position. */ -+#define XCL_PCNTO7_bm (1<<7) /* Peripheral Counter 0 Byte bit 7 mask. */ -+#define XCL_PCNTO7_bp 7 /* Peripheral Counter 0 Byte bit 7 position. */ -+ -+/* XCL.CNTH bit masks and bit positions */ -+#define XCL_BCNT1_gm 0xFF /* BTC1 Counter Byte group mask. */ -+#define XCL_BCNT1_gp 0 /* BTC1 Counter Byte group position. */ -+#define XCL_BCNT10_bm (1<<0) /* BTC1 Counter Byte bit 0 mask. */ -+#define XCL_BCNT10_bp 0 /* BTC1 Counter Byte bit 0 position. */ -+#define XCL_BCNT11_bm (1<<1) /* BTC1 Counter Byte bit 1 mask. */ -+#define XCL_BCNT11_bp 1 /* BTC1 Counter Byte bit 1 position. */ -+#define XCL_BCNT12_bm (1<<2) /* BTC1 Counter Byte bit 2 mask. */ -+#define XCL_BCNT12_bp 2 /* BTC1 Counter Byte bit 2 position. */ -+#define XCL_BCNT13_bm (1<<3) /* BTC1 Counter Byte bit 3 mask. */ -+#define XCL_BCNT13_bp 3 /* BTC1 Counter Byte bit 3 position. */ -+#define XCL_BCNT14_bm (1<<4) /* BTC1 Counter Byte bit 4 mask. */ -+#define XCL_BCNT14_bp 4 /* BTC1 Counter Byte bit 4 position. */ -+#define XCL_BCNT15_bm (1<<5) /* BTC1 Counter Byte bit 5 mask. */ -+#define XCL_BCNT15_bp 5 /* BTC1 Counter Byte bit 5 position. */ -+#define XCL_BCNT16_bm (1<<6) /* BTC1 Counter Byte bit 6 mask. */ -+#define XCL_BCNT16_bp 6 /* BTC1 Counter Byte bit 6 position. */ -+#define XCL_BCNT17_bm (1<<7) /* BTC1 Counter Byte bit 7 mask. */ -+#define XCL_BCNT17_bp 7 /* BTC1 Counter Byte bit 7 position. */ -+ -+#define XCL_CNTH_gm 0xFF /* TC16 Counter High Byte group mask. */ -+#define XCL_CNTH_gp 0 /* TC16 Counter High Byte group position. */ -+#define XCL_CNTH0_bm (1<<0) /* TC16 Counter High Byte bit 0 mask. */ -+#define XCL_CNTH0_bp 0 /* TC16 Counter High Byte bit 0 position. */ -+#define XCL_CNTH1_bm (1<<1) /* TC16 Counter High Byte bit 1 mask. */ -+#define XCL_CNTH1_bp 1 /* TC16 Counter High Byte bit 1 position. */ -+#define XCL_CNTH2_bm (1<<2) /* TC16 Counter High Byte bit 2 mask. */ -+#define XCL_CNTH2_bp 2 /* TC16 Counter High Byte bit 2 position. */ -+#define XCL_CNTH3_bm (1<<3) /* TC16 Counter High Byte bit 3 mask. */ -+#define XCL_CNTH3_bp 3 /* TC16 Counter High Byte bit 3 position. */ -+#define XCL_CNTH4_bm (1<<4) /* TC16 Counter High Byte bit 4 mask. */ -+#define XCL_CNTH4_bp 4 /* TC16 Counter High Byte bit 4 position. */ -+#define XCL_CNTH5_bm (1<<5) /* TC16 Counter High Byte bit 5 mask. */ -+#define XCL_CNTH5_bp 5 /* TC16 Counter High Byte bit 5 position. */ -+#define XCL_CNTH6_bm (1<<6) /* TC16 Counter High Byte bit 6 mask. */ -+#define XCL_CNTH6_bp 6 /* TC16 Counter High Byte bit 6 position. */ -+#define XCL_CNTH7_bm (1<<7) /* TC16 Counter High Byte bit 7 mask. */ -+#define XCL_CNTH7_bp 7 /* TC16 Counter High Byte bit 7 position. */ -+ -+#define XCL_PCNT1_gm 0xFF /* Peripheral Counter 1 Byte group mask. */ -+#define XCL_PCNT1_gp 0 /* Peripheral Counter 1 Byte group position. */ -+#define XCL_PCNT10_bm (1<<0) /* Peripheral Counter 1 Byte bit 0 mask. */ -+#define XCL_PCNT10_bp 0 /* Peripheral Counter 1 Byte bit 0 position. */ -+#define XCL_PCNT11_bm (1<<1) /* Peripheral Counter 1 Byte bit 1 mask. */ -+#define XCL_PCNT11_bp 1 /* Peripheral Counter 1 Byte bit 1 position. */ -+#define XCL_PCNT12_bm (1<<2) /* Peripheral Counter 1 Byte bit 2 mask. */ -+#define XCL_PCNT12_bp 2 /* Peripheral Counter 1 Byte bit 2 position. */ -+#define XCL_PCNT13_bm (1<<3) /* Peripheral Counter 1 Byte bit 3 mask. */ -+#define XCL_PCNT13_bp 3 /* Peripheral Counter 1 Byte bit 3 position. */ -+#define XCL_PCNT14_bm (1<<4) /* Peripheral Counter 1 Byte bit 4 mask. */ -+#define XCL_PCNT14_bp 4 /* Peripheral Counter 1 Byte bit 4 position. */ -+#define XCL_PCNT15_bm (1<<5) /* Peripheral Counter 1 Byte bit 5 mask. */ -+#define XCL_PCNT15_bp 5 /* Peripheral Counter 1 Byte bit 5 position. */ -+#define XCL_PCNT16_bm (1<<6) /* Peripheral Counter 1 Byte bit 6 mask. */ -+#define XCL_PCNT16_bp 6 /* Peripheral Counter 1 Byte bit 6 position. */ -+#define XCL_PCNT17_bm (1<<7) /* Peripheral Counter 1 Byte bit 7 mask. */ -+#define XCL_PCNT17_bp 7 /* Peripheral Counter 1 Byte bit 7 position. */ -+ -+#define XCL_PCNT21_gm 0xF0 /* Peripheral High Counter 2 Bits group mask. */ -+#define XCL_PCNT21_gp 4 /* Peripheral High Counter 2 Bits group position. */ -+#define XCL_PCNT210_bm (1<<4) /* Peripheral High Counter 2 Bits bit 0 mask. */ -+#define XCL_PCNT210_bp 4 /* Peripheral High Counter 2 Bits bit 0 position. */ -+#define XCL_PCNT211_bm (1<<5) /* Peripheral High Counter 2 Bits bit 1 mask. */ -+#define XCL_PCNT211_bp 5 /* Peripheral High Counter 2 Bits bit 1 position. */ -+#define XCL_PCNT212_bm (1<<6) /* Peripheral High Counter 2 Bits bit 2 mask. */ -+#define XCL_PCNT212_bp 6 /* Peripheral High Counter 2 Bits bit 2 position. */ -+#define XCL_PCNT213_bm (1<<7) /* Peripheral High Counter 2 Bits bit 3 mask. */ -+#define XCL_PCNT213_bp 7 /* Peripheral High Counter 2 Bits bit 3 position. */ -+ -+#define XCL_PCNT20_gm 0x0F /* Peripheral Low Counter 2 Bits group mask. */ -+#define XCL_PCNT20_gp 0 /* Peripheral Low Counter 2 Bits group position. */ -+#define XCL_PCNT200_bm (1<<0) /* Peripheral Low Counter 2 Bits bit 0 mask. */ -+#define XCL_PCNT200_bp 0 /* Peripheral Low Counter 2 Bits bit 0 position. */ -+#define XCL_PCNT201_bm (1<<1) /* Peripheral Low Counter 2 Bits bit 1 mask. */ -+#define XCL_PCNT201_bp 1 /* Peripheral Low Counter 2 Bits bit 1 position. */ -+#define XCL_PCNT202_bm (1<<2) /* Peripheral Low Counter 2 Bits bit 2 mask. */ -+#define XCL_PCNT202_bp 2 /* Peripheral Low Counter 2 Bits bit 2 position. */ -+#define XCL_PCNT203_bm (1<<3) /* Peripheral Low Counter 2 Bits bit 3 mask. */ -+#define XCL_PCNT203_bp 3 /* Peripheral Low Counter 2 Bits bit 3 position. */ -+ -+/* XCL.CMPL bit masks and bit positions */ -+#define XCL_CMPL_gm 0xFF /* TC16 Compare Low Byte group mask. */ -+#define XCL_CMPL_gp 0 /* TC16 Compare Low Byte group position. */ -+#define XCL_CMPL0_bm (1<<0) /* TC16 Compare Low Byte bit 0 mask. */ -+#define XCL_CMPL0_bp 0 /* TC16 Compare Low Byte bit 0 position. */ -+#define XCL_CMPL1_bm (1<<1) /* TC16 Compare Low Byte bit 1 mask. */ -+#define XCL_CMPL1_bp 1 /* TC16 Compare Low Byte bit 1 position. */ -+#define XCL_CMPL2_bm (1<<2) /* TC16 Compare Low Byte bit 2 mask. */ -+#define XCL_CMPL2_bp 2 /* TC16 Compare Low Byte bit 2 position. */ -+#define XCL_CMPL3_bm (1<<3) /* TC16 Compare Low Byte bit 3 mask. */ -+#define XCL_CMPL3_bp 3 /* TC16 Compare Low Byte bit 3 position. */ -+#define XCL_CMPL4_bm (1<<4) /* TC16 Compare Low Byte bit 4 mask. */ -+#define XCL_CMPL4_bp 4 /* TC16 Compare Low Byte bit 4 position. */ -+#define XCL_CMPL5_bm (1<<5) /* TC16 Compare Low Byte bit 5 mask. */ -+#define XCL_CMPL5_bp 5 /* TC16 Compare Low Byte bit 5 position. */ -+#define XCL_CMPL6_bm (1<<6) /* TC16 Compare Low Byte bit 6 mask. */ -+#define XCL_CMPL6_bp 6 /* TC16 Compare Low Byte bit 6 position. */ -+#define XCL_CMPL7_bm (1<<7) /* TC16 Compare Low Byte bit 7 mask. */ -+#define XCL_CMPL7_bp 7 /* TC16 Compare Low Byte bit 7 position. */ -+ -+#define XCL_BCMP0_gm 0xFF /* BTC0 Compare Byte group mask. */ -+#define XCL_BCMP0_gp 0 /* BTC0 Compare Byte group position. */ -+#define XCL_BCMP00_bm (1<<0) /* BTC0 Compare Byte bit 0 mask. */ -+#define XCL_BCMP00_bp 0 /* BTC0 Compare Byte bit 0 position. */ -+#define XCL_BCMP01_bm (1<<1) /* BTC0 Compare Byte bit 1 mask. */ -+#define XCL_BCMP01_bp 1 /* BTC0 Compare Byte bit 1 position. */ -+#define XCL_BCMP02_bm (1<<2) /* BTC0 Compare Byte bit 2 mask. */ -+#define XCL_BCMP02_bp 2 /* BTC0 Compare Byte bit 2 position. */ -+#define XCL_BCMP03_bm (1<<3) /* BTC0 Compare Byte bit 3 mask. */ -+#define XCL_BCMP03_bp 3 /* BTC0 Compare Byte bit 3 position. */ -+#define XCL_BCMP04_bm (1<<4) /* BTC0 Compare Byte bit 4 mask. */ -+#define XCL_BCMP04_bp 4 /* BTC0 Compare Byte bit 4 position. */ -+#define XCL_BCMP05_bm (1<<5) /* BTC0 Compare Byte bit 5 mask. */ -+#define XCL_BCMP05_bp 5 /* BTC0 Compare Byte bit 5 position. */ -+#define XCL_BCMP06_bm (1<<6) /* BTC0 Compare Byte bit 6 mask. */ -+#define XCL_BCMP06_bp 6 /* BTC0 Compare Byte bit 6 position. */ -+#define XCL_BCMP07_bm (1<<7) /* BTC0 Compare Byte bit 7 mask. */ -+#define XCL_BCMP07_bp 7 /* BTC0 Compare Byte bit 7 position. */ -+ -+/* XCL.CMPH bit masks and bit positions */ -+#define XCL_CMPH_gm 0xFF /* TC16 Compare High Byte group mask. */ -+#define XCL_CMPH_gp 0 /* TC16 Compare High Byte group position. */ -+#define XCL_CMPH0_bm (1<<0) /* TC16 Compare High Byte bit 0 mask. */ -+#define XCL_CMPH0_bp 0 /* TC16 Compare High Byte bit 0 position. */ -+#define XCL_CMPH1_bm (1<<1) /* TC16 Compare High Byte bit 1 mask. */ -+#define XCL_CMPH1_bp 1 /* TC16 Compare High Byte bit 1 position. */ -+#define XCL_CMPH2_bm (1<<2) /* TC16 Compare High Byte bit 2 mask. */ -+#define XCL_CMPH2_bp 2 /* TC16 Compare High Byte bit 2 position. */ -+#define XCL_CMPH3_bm (1<<3) /* TC16 Compare High Byte bit 3 mask. */ -+#define XCL_CMPH3_bp 3 /* TC16 Compare High Byte bit 3 position. */ -+#define XCL_CMPH4_bm (1<<4) /* TC16 Compare High Byte bit 4 mask. */ -+#define XCL_CMPH4_bp 4 /* TC16 Compare High Byte bit 4 position. */ -+#define XCL_CMPH5_bm (1<<5) /* TC16 Compare High Byte bit 5 mask. */ -+#define XCL_CMPH5_bp 5 /* TC16 Compare High Byte bit 5 position. */ -+#define XCL_CMPH6_bm (1<<6) /* TC16 Compare High Byte bit 6 mask. */ -+#define XCL_CMPH6_bp 6 /* TC16 Compare High Byte bit 6 position. */ -+#define XCL_CMPH7_bm (1<<7) /* TC16 Compare High Byte bit 7 mask. */ -+#define XCL_CMPH7_bp 7 /* TC16 Compare High Byte bit 7 position. */ -+ -+#define XCL_BCMP1_gm 0xFF /* BTC1 Compare Byte group mask. */ -+#define XCL_BCMP1_gp 0 /* BTC1 Compare Byte group position. */ -+#define XCL_BCMP10_bm (1<<0) /* BTC1 Compare Byte bit 0 mask. */ -+#define XCL_BCMP10_bp 0 /* BTC1 Compare Byte bit 0 position. */ -+#define XCL_BCMP11_bm (1<<1) /* BTC1 Compare Byte bit 1 mask. */ -+#define XCL_BCMP11_bp 1 /* BTC1 Compare Byte bit 1 position. */ -+#define XCL_BCMP12_bm (1<<2) /* BTC1 Compare Byte bit 2 mask. */ -+#define XCL_BCMP12_bp 2 /* BTC1 Compare Byte bit 2 position. */ -+#define XCL_BCMP13_bm (1<<3) /* BTC1 Compare Byte bit 3 mask. */ -+#define XCL_BCMP13_bp 3 /* BTC1 Compare Byte bit 3 position. */ -+#define XCL_BCMP14_bm (1<<4) /* BTC1 Compare Byte bit 4 mask. */ -+#define XCL_BCMP14_bp 4 /* BTC1 Compare Byte bit 4 position. */ -+#define XCL_BCMP15_bm (1<<5) /* BTC1 Compare Byte bit 5 mask. */ -+#define XCL_BCMP15_bp 5 /* BTC1 Compare Byte bit 5 position. */ -+#define XCL_BCMP16_bm (1<<6) /* BTC1 Compare Byte bit 6 mask. */ -+#define XCL_BCMP16_bp 6 /* BTC1 Compare Byte bit 6 position. */ -+#define XCL_BCMP17_bm (1<<7) /* BTC1 Compare Byte bit 7 mask. */ -+#define XCL_BCMP17_bp 7 /* BTC1 Compare Byte bit 7 position. */ -+ -+/* XCL.PERCAPTL bit masks and bit positions */ -+#define XCL_PERL_gm 0xFF /* TC16 Low Byte Period group mask. */ -+#define XCL_PERL_gp 0 /* TC16 Low Byte Period group position. */ -+#define XCL_PERL0_bm (1<<0) /* TC16 Low Byte Period bit 0 mask. */ -+#define XCL_PERL0_bp 0 /* TC16 Low Byte Period bit 0 position. */ -+#define XCL_PERL1_bm (1<<1) /* TC16 Low Byte Period bit 1 mask. */ -+#define XCL_PERL1_bp 1 /* TC16 Low Byte Period bit 1 position. */ -+#define XCL_PERL2_bm (1<<2) /* TC16 Low Byte Period bit 2 mask. */ -+#define XCL_PERL2_bp 2 /* TC16 Low Byte Period bit 2 position. */ -+#define XCL_PERL3_bm (1<<3) /* TC16 Low Byte Period bit 3 mask. */ -+#define XCL_PERL3_bp 3 /* TC16 Low Byte Period bit 3 position. */ -+#define XCL_PERL4_bm (1<<4) /* TC16 Low Byte Period bit 4 mask. */ -+#define XCL_PERL4_bp 4 /* TC16 Low Byte Period bit 4 position. */ -+#define XCL_PERL5_bm (1<<5) /* TC16 Low Byte Period bit 5 mask. */ -+#define XCL_PERL5_bp 5 /* TC16 Low Byte Period bit 5 position. */ -+#define XCL_PERL6_bm (1<<6) /* TC16 Low Byte Period bit 6 mask. */ -+#define XCL_PERL6_bp 6 /* TC16 Low Byte Period bit 6 position. */ -+#define XCL_PERL7_bm (1<<7) /* TC16 Low Byte Period bit 7 mask. */ -+#define XCL_PERL7_bp 7 /* TC16 Low Byte Period bit 7 position. */ -+ -+#define XCL_CAPTL_gm 0xFF /* TC16 Capture Value Low Byte group mask. */ -+#define XCL_CAPTL_gp 0 /* TC16 Capture Value Low Byte group position. */ -+#define XCL_CAPTL0_bm (1<<0) /* TC16 Capture Value Low Byte bit 0 mask. */ -+#define XCL_CAPTL0_bp 0 /* TC16 Capture Value Low Byte bit 0 position. */ -+#define XCL_CAPTL1_bm (1<<1) /* TC16 Capture Value Low Byte bit 1 mask. */ -+#define XCL_CAPTL1_bp 1 /* TC16 Capture Value Low Byte bit 1 position. */ -+#define XCL_CAPTL2_bm (1<<2) /* TC16 Capture Value Low Byte bit 2 mask. */ -+#define XCL_CAPTL2_bp 2 /* TC16 Capture Value Low Byte bit 2 position. */ -+#define XCL_CAPTL3_bm (1<<3) /* TC16 Capture Value Low Byte bit 3 mask. */ -+#define XCL_CAPTL3_bp 3 /* TC16 Capture Value Low Byte bit 3 position. */ -+#define XCL_CAPTL4_bm (1<<4) /* TC16 Capture Value Low Byte bit 4 mask. */ -+#define XCL_CAPTL4_bp 4 /* TC16 Capture Value Low Byte bit 4 position. */ -+#define XCL_CAPTL5_bm (1<<5) /* TC16 Capture Value Low Byte bit 5 mask. */ -+#define XCL_CAPTL5_bp 5 /* TC16 Capture Value Low Byte bit 5 position. */ -+#define XCL_CAPTL6_bm (1<<6) /* TC16 Capture Value Low Byte bit 6 mask. */ -+#define XCL_CAPTL6_bp 6 /* TC16 Capture Value Low Byte bit 6 position. */ -+#define XCL_CAPTL7_bm (1<<7) /* TC16 Capture Value Low Byte bit 7 mask. */ -+#define XCL_CAPTL7_bp 7 /* TC16 Capture Value Low Byte bit 7 position. */ -+ -+#define XCL_BPER0_gm 0xFF /* BTC0 Period group mask. */ -+#define XCL_BPER0_gp 0 /* BTC0 Period group position. */ -+#define XCL_BPER00_bm (1<<0) /* BTC0 Period bit 0 mask. */ -+#define XCL_BPER00_bp 0 /* BTC0 Period bit 0 position. */ -+#define XCL_BPER01_bm (1<<1) /* BTC0 Period bit 1 mask. */ -+#define XCL_BPER01_bp 1 /* BTC0 Period bit 1 position. */ -+#define XCL_BPER02_bm (1<<2) /* BTC0 Period bit 2 mask. */ -+#define XCL_BPER02_bp 2 /* BTC0 Period bit 2 position. */ -+#define XCL_BPER03_bm (1<<3) /* BTC0 Period bit 3 mask. */ -+#define XCL_BPER03_bp 3 /* BTC0 Period bit 3 position. */ -+#define XCL_BPER04_bm (1<<4) /* BTC0 Period bit 4 mask. */ -+#define XCL_BPER04_bp 4 /* BTC0 Period bit 4 position. */ -+#define XCL_BPER05_bm (1<<5) /* BTC0 Period bit 5 mask. */ -+#define XCL_BPER05_bp 5 /* BTC0 Period bit 5 position. */ -+#define XCL_BPER06_bm (1<<6) /* BTC0 Period bit 6 mask. */ -+#define XCL_BPER06_bp 6 /* BTC0 Period bit 6 position. */ -+#define XCL_BPER07_bm (1<<7) /* BTC0 Period bit 7 mask. */ -+#define XCL_BPER07_bp 7 /* BTC0 Period bit 7 position. */ -+ -+#define XCL_BCAPT0_gm 0xFF /* BTC0 Capture Value Byte group mask. */ -+#define XCL_BCAPT0_gp 0 /* BTC0 Capture Value Byte group position. */ -+#define XCL_BCAPT00_bm (1<<0) /* BTC0 Capture Value Byte bit 0 mask. */ -+#define XCL_BCAPT00_bp 0 /* BTC0 Capture Value Byte bit 0 position. */ -+#define XCL_BCAPT01_bm (1<<1) /* BTC0 Capture Value Byte bit 1 mask. */ -+#define XCL_BCAPT01_bp 1 /* BTC0 Capture Value Byte bit 1 position. */ -+#define XCL_BCAPT02_bm (1<<2) /* BTC0 Capture Value Byte bit 2 mask. */ -+#define XCL_BCAPT02_bp 2 /* BTC0 Capture Value Byte bit 2 position. */ -+#define XCL_BCAPT03_bm (1<<3) /* BTC0 Capture Value Byte bit 3 mask. */ -+#define XCL_BCAPT03_bp 3 /* BTC0 Capture Value Byte bit 3 position. */ -+#define XCL_BCAPT04_bm (1<<4) /* BTC0 Capture Value Byte bit 4 mask. */ -+#define XCL_BCAPT04_bp 4 /* BTC0 Capture Value Byte bit 4 position. */ -+#define XCL_BCAPT05_bm (1<<5) /* BTC0 Capture Value Byte bit 5 mask. */ -+#define XCL_BCAPT05_bp 5 /* BTC0 Capture Value Byte bit 5 position. */ -+#define XCL_BCAPT06_bm (1<<6) /* BTC0 Capture Value Byte bit 6 mask. */ -+#define XCL_BCAPT06_bp 6 /* BTC0 Capture Value Byte bit 6 position. */ -+#define XCL_BCAPT07_bm (1<<7) /* BTC0 Capture Value Byte bit 7 mask. */ -+#define XCL_BCAPT07_bp 7 /* BTC0 Capture Value Byte bit 7 position. */ -+ -+/* XCL.PERCAPTH bit masks and bit positions */ -+#define XCL_PERH_gm 0xFF /* TC16 High Byte Period group mask. */ -+#define XCL_PERH_gp 0 /* TC16 High Byte Period group position. */ -+#define XCL_PERH0_bm (1<<0) /* TC16 High Byte Period bit 0 mask. */ -+#define XCL_PERH0_bp 0 /* TC16 High Byte Period bit 0 position. */ -+#define XCL_PERH1_bm (1<<1) /* TC16 High Byte Period bit 1 mask. */ -+#define XCL_PERH1_bp 1 /* TC16 High Byte Period bit 1 position. */ -+#define XCL_PERH2_bm (1<<2) /* TC16 High Byte Period bit 2 mask. */ -+#define XCL_PERH2_bp 2 /* TC16 High Byte Period bit 2 position. */ -+#define XCL_PERH3_bm (1<<3) /* TC16 High Byte Period bit 3 mask. */ -+#define XCL_PERH3_bp 3 /* TC16 High Byte Period bit 3 position. */ -+#define XCL_PERH4_bm (1<<4) /* TC16 High Byte Period bit 4 mask. */ -+#define XCL_PERH4_bp 4 /* TC16 High Byte Period bit 4 position. */ -+#define XCL_PERH5_bm (1<<5) /* TC16 High Byte Period bit 5 mask. */ -+#define XCL_PERH5_bp 5 /* TC16 High Byte Period bit 5 position. */ -+#define XCL_PERH6_bm (1<<6) /* TC16 High Byte Period bit 6 mask. */ -+#define XCL_PERH6_bp 6 /* TC16 High Byte Period bit 6 position. */ -+#define XCL_PERH7_bm (1<<7) /* TC16 High Byte Period bit 7 mask. */ -+#define XCL_PERH7_bp 7 /* TC16 High Byte Period bit 7 position. */ -+ -+#define XCL_CAPTH_gm 0xFF /* TC16 Capture Value High Byte group mask. */ -+#define XCL_CAPTH_gp 0 /* TC16 Capture Value High Byte group position. */ -+#define XCL_CAPTH0_bm (1<<0) /* TC16 Capture Value High Byte bit 0 mask. */ -+#define XCL_CAPTH0_bp 0 /* TC16 Capture Value High Byte bit 0 position. */ -+#define XCL_CAPTH1_bm (1<<1) /* TC16 Capture Value High Byte bit 1 mask. */ -+#define XCL_CAPTH1_bp 1 /* TC16 Capture Value High Byte bit 1 position. */ -+#define XCL_CAPTH2_bm (1<<2) /* TC16 Capture Value High Byte bit 2 mask. */ -+#define XCL_CAPTH2_bp 2 /* TC16 Capture Value High Byte bit 2 position. */ -+#define XCL_CAPTH3_bm (1<<3) /* TC16 Capture Value High Byte bit 3 mask. */ -+#define XCL_CAPTH3_bp 3 /* TC16 Capture Value High Byte bit 3 position. */ -+#define XCL_CAPTH4_bm (1<<4) /* TC16 Capture Value High Byte bit 4 mask. */ -+#define XCL_CAPTH4_bp 4 /* TC16 Capture Value High Byte bit 4 position. */ -+#define XCL_CAPTH5_bm (1<<5) /* TC16 Capture Value High Byte bit 5 mask. */ -+#define XCL_CAPTH5_bp 5 /* TC16 Capture Value High Byte bit 5 position. */ -+#define XCL_CAPTH6_bm (1<<6) /* TC16 Capture Value High Byte bit 6 mask. */ -+#define XCL_CAPTH6_bp 6 /* TC16 Capture Value High Byte bit 6 position. */ -+#define XCL_CAPTH7_bm (1<<7) /* TC16 Capture Value High Byte bit 7 mask. */ -+#define XCL_CAPTH7_bp 7 /* TC16 Capture Value High Byte bit 7 position. */ -+ -+#define XCL_BPER1_gm 0xFF /* BTC1 Period group mask. */ -+#define XCL_BPER1_gp 0 /* BTC1 Period group position. */ -+#define XCL_BPER10_bm (1<<0) /* BTC1 Period bit 0 mask. */ -+#define XCL_BPER10_bp 0 /* BTC1 Period bit 0 position. */ -+#define XCL_BPER11_bm (1<<1) /* BTC1 Period bit 1 mask. */ -+#define XCL_BPER11_bp 1 /* BTC1 Period bit 1 position. */ -+#define XCL_BPER12_bm (1<<2) /* BTC1 Period bit 2 mask. */ -+#define XCL_BPER12_bp 2 /* BTC1 Period bit 2 position. */ -+#define XCL_BPER13_bm (1<<3) /* BTC1 Period bit 3 mask. */ -+#define XCL_BPER13_bp 3 /* BTC1 Period bit 3 position. */ -+#define XCL_BPER14_bm (1<<4) /* BTC1 Period bit 4 mask. */ -+#define XCL_BPER14_bp 4 /* BTC1 Period bit 4 position. */ -+#define XCL_BPER15_bm (1<<5) /* BTC1 Period bit 5 mask. */ -+#define XCL_BPER15_bp 5 /* BTC1 Period bit 5 position. */ -+#define XCL_BPER16_bm (1<<6) /* BTC1 Period bit 6 mask. */ -+#define XCL_BPER16_bp 6 /* BTC1 Period bit 6 position. */ -+#define XCL_BPER17_bm (1<<7) /* BTC1 Period bit 7 mask. */ -+#define XCL_BPER17_bp 7 /* BTC1 Period bit 7 position. */ -+ -+#define XCL_BCAPT1_gm 0xFF /* BTC1 Capture Value Byte group mask. */ -+#define XCL_BCAPT1_gp 0 /* BTC1 Capture Value Byte group position. */ -+#define XCL_BCAPT10_bm (1<<0) /* BTC1 Capture Value Byte bit 0 mask. */ -+#define XCL_BCAPT10_bp 0 /* BTC1 Capture Value Byte bit 0 position. */ -+#define XCL_BCAPT11_bm (1<<1) /* BTC1 Capture Value Byte bit 1 mask. */ -+#define XCL_BCAPT11_bp 1 /* BTC1 Capture Value Byte bit 1 position. */ -+#define XCL_BCAPT12_bm (1<<2) /* BTC1 Capture Value Byte bit 2 mask. */ -+#define XCL_BCAPT12_bp 2 /* BTC1 Capture Value Byte bit 2 position. */ -+#define XCL_BCAPT13_bm (1<<3) /* BTC1 Capture Value Byte bit 3 mask. */ -+#define XCL_BCAPT13_bp 3 /* BTC1 Capture Value Byte bit 3 position. */ -+#define XCL_BCAPT14_bm (1<<4) /* BTC1 Capture Value Byte bit 4 mask. */ -+#define XCL_BCAPT14_bp 4 /* BTC1 Capture Value Byte bit 4 position. */ -+#define XCL_BCAPT15_bm (1<<5) /* BTC1 Capture Value Byte bit 5 mask. */ -+#define XCL_BCAPT15_bp 5 /* BTC1 Capture Value Byte bit 5 position. */ -+#define XCL_BCAPT16_bm (1<<6) /* BTC1 Capture Value Byte bit 6 mask. */ -+#define XCL_BCAPT16_bp 6 /* BTC1 Capture Value Byte bit 6 position. */ -+#define XCL_BCAPT17_bm (1<<7) /* BTC1 Capture Value Byte bit 7 mask. */ -+#define XCL_BCAPT17_bp 7 /* BTC1 Capture Value Byte bit 7 position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_BRIDGEEN_bm 0x80 /* Bridge Enable bit mask. */ -+#define TWI_BRIDGEEN_bp 7 /* Bridge Enable bit position. */ -+ -+#define TWI_SFMPEN_bm 0x40 /* Slave Fast Mode Plus Enable bit mask. */ -+#define TWI_SFMPEN_bp 6 /* Slave Fast Mode Plus Enable bit position. */ -+ -+#define TWI_SSDAHOLD_gm 0x30 /* Slave SDA Hold Time Enable group mask. */ -+#define TWI_SSDAHOLD_gp 4 /* Slave SDA Hold Time Enable group position. */ -+#define TWI_SSDAHOLD0_bm (1<<4) /* Slave SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SSDAHOLD0_bp 4 /* Slave SDA Hold Time Enable bit 0 position. */ -+#define TWI_SSDAHOLD1_bm (1<<5) /* Slave SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SSDAHOLD1_bp 5 /* Slave SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_FMPEN_bm 0x08 /* FMPLUS Enable bit mask. */ -+#define TWI_FMPEN_bp 3 /* FMPLUS Enable bit position. */ -+ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+#define TWI_MASTER_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ -+#define TWI_MASTER_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ -+ -+#define TWI_MASTER_TSEXTEN_bm 0x20 /* Slave Extend Timeout Enable bit mask. */ -+#define TWI_MASTER_TSEXTEN_bp 5 /* Slave Extend Timeout Enable bit position. */ -+ -+#define TWI_MASTER_TMEXTEN_bm 0x40 /* Master Extend Timeout Enable bit mask. */ -+#define TWI_MASTER_TMEXTEN_bp 6 /* Master Extend Timeout Enable bit position. */ -+ -+#define TWI_MASTER_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ -+#define TWI_MASTER_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+#define TWI_SLAVE_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ -+#define TWI_SLAVE_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ -+ -+#define TWI_SLAVE_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ -+#define TWI_SLAVE_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI_TIMEOUT.TOS bit masks and bit positions */ -+#define TWI_TIMEOUT_TTOUTMIF_bm 0x01 /* Master Ttimeout Interrupt Flag bit mask. */ -+#define TWI_TIMEOUT_TTOUTMIF_bp 0 /* Master Ttimeout Interrupt Flag bit position. */ -+ -+#define TWI_TIMEOUT_TSEXTIF_bm 0x02 /* Slave Extend Interrupt Flag bit mask. */ -+#define TWI_TIMEOUT_TSEXTIF_bp 1 /* Slave Extend Interrupt Flag bit position. */ -+ -+#define TWI_TIMEOUT_TMEXTIF_bm 0x04 /* Master Extend Interrupt Flag bit mask. */ -+#define TWI_TIMEOUT_TMEXTIF_bp 2 /* Master Extend Interrupt Flag bit position. */ -+ -+#define TWI_TIMEOUT_TTOUTSIF_bm 0x10 /* Slave Ttimeout Interrupt Flag bit mask. */ -+#define TWI_TIMEOUT_TTOUTSIF_bp 4 /* Slave Ttimeout Interrupt Flag bit position. */ -+ -+/* TWI_TIMEOUT.TOCONF bit masks and bit positions */ -+#define TWI_TIMEOUT_TTOUTMSEL_gm 0x07 /* Master Ttimeout Select group mask. */ -+#define TWI_TIMEOUT_TTOUTMSEL_gp 0 /* Master Ttimeout Select group position. */ -+#define TWI_TIMEOUT_TTOUTMSEL0_bm (1<<0) /* Master Ttimeout Select bit 0 mask. */ -+#define TWI_TIMEOUT_TTOUTMSEL0_bp 0 /* Master Ttimeout Select bit 0 position. */ -+#define TWI_TIMEOUT_TTOUTMSEL1_bm (1<<1) /* Master Ttimeout Select bit 1 mask. */ -+#define TWI_TIMEOUT_TTOUTMSEL1_bp 1 /* Master Ttimeout Select bit 1 position. */ -+#define TWI_TIMEOUT_TTOUTMSEL2_bm (1<<2) /* Master Ttimeout Select bit 2 mask. */ -+#define TWI_TIMEOUT_TTOUTMSEL2_bp 2 /* Master Ttimeout Select bit 2 position. */ -+ -+#define TWI_TIMEOUT_TMSEXTSEL_gm 0x18 /* Master/Slave Timeout Select group mask. */ -+#define TWI_TIMEOUT_TMSEXTSEL_gp 3 /* Master/Slave Timeout Select group position. */ -+#define TWI_TIMEOUT_TMSEXTSEL0_bm (1<<3) /* Master/Slave Timeout Select bit 0 mask. */ -+#define TWI_TIMEOUT_TMSEXTSEL0_bp 3 /* Master/Slave Timeout Select bit 0 position. */ -+#define TWI_TIMEOUT_TMSEXTSEL1_bm (1<<4) /* Master/Slave Timeout Select bit 1 mask. */ -+#define TWI_TIMEOUT_TMSEXTSEL1_bp 4 /* Master/Slave Timeout Select bit 1 position. */ -+ -+#define TWI_TIMEOUT_TTOUTSSEL_gm 0xE0 /* Slave Ttimeout Select group mask. */ -+#define TWI_TIMEOUT_TTOUTSSEL_gp 5 /* Slave Ttimeout Select group position. */ -+#define TWI_TIMEOUT_TTOUTSSEL0_bm (1<<5) /* Slave Ttimeout Select bit 0 mask. */ -+#define TWI_TIMEOUT_TTOUTSSEL0_bp 5 /* Slave Ttimeout Select bit 0 position. */ -+#define TWI_TIMEOUT_TTOUTSSEL1_bm (1<<6) /* Slave Ttimeout Select bit 1 mask. */ -+#define TWI_TIMEOUT_TTOUTSSEL1_bp 6 /* Slave Ttimeout Select bit 1 position. */ -+#define TWI_TIMEOUT_TTOUTSSEL2_bm (1<<7) /* Slave Ttimeout Select bit 2 mask. */ -+#define TWI_TIMEOUT_TTOUTSSEL2_bp 7 /* Slave Ttimeout Select bit 2 position. */ -+ -+/* PORT - Port Configuration */ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INTLVL_gm 0x03 /* Port Interrupt Level group mask. */ -+#define PORT_INTLVL_gp 0 /* Port Interrupt Level group position. */ -+#define PORT_INTLVL0_bm (1<<0) /* Port Interrupt Level bit 0 mask. */ -+#define PORT_INTLVL0_bp 0 /* Port Interrupt Level bit 0 position. */ -+#define PORT_INTLVL1_bm (1<<1) /* Port Interrupt Level bit 1 mask. */ -+#define PORT_INTLVL1_bp 1 /* Port Interrupt Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT7IF_bm 0x80 /* Pin 7 Interrupt Flag bit mask. */ -+#define PORT_INT7IF_bp 7 /* Pin 7 Interrupt Flag bit position. */ -+ -+#define PORT_INT6IF_bm 0x40 /* Pin 6 Interrupt Flag bit mask. */ -+#define PORT_INT6IF_bp 6 /* Pin 6 Interrupt Flag bit position. */ -+ -+#define PORT_INT5IF_bm 0x20 /* Pin 5 Interrupt Flag bit mask. */ -+#define PORT_INT5IF_bp 5 /* Pin 5 Interrupt Flag bit position. */ -+ -+#define PORT_INT4IF_bm 0x10 /* Pin 4 Interrupt Flag bit mask. */ -+#define PORT_INT4IF_bp 4 /* Pin 4 Interrupt Flag bit position. */ -+ -+#define PORT_INT3IF_bm 0x08 /* Pin 3 Interrupt Flag bit mask. */ -+#define PORT_INT3IF_bp 3 /* Pin 3 Interrupt Flag bit position. */ -+ -+#define PORT_INT2IF_bm 0x04 /* Pin 2 Interrupt Flag bit mask. */ -+#define PORT_INT2IF_bp 2 /* Pin 2 Interrupt Flag bit position. */ -+ -+#define PORT_INT1IF_bm 0x02 /* Pin 1 Interrupt Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Pin 1 Interrupt Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Pin 0 Interrupt Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Pin 0 Interrupt Flag bit position. */ -+ -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_USART0_bm 0x10 /* Usart0 bit mask. */ -+#define PORT_USART0_bp 4 /* Usart0 bit position. */ -+ -+#define PORT_TC4D_bm 0x08 /* Timer/Counter 4 Output Compare D bit mask. */ -+#define PORT_TC4D_bp 3 /* Timer/Counter 4 Output Compare D bit position. */ -+ -+#define PORT_TC4C_bm 0x04 /* Timer/Counter 4 Output Compare C bit mask. */ -+#define PORT_TC4C_bp 2 /* Timer/Counter 4 Output Compare C bit position. */ -+ -+#define PORT_TC4B_bm 0x02 /* Timer/Counter 4 Output Compare B bit mask. */ -+#define PORT_TC4B_bp 1 /* Timer/Counter 4 Output Compare B bit position. */ -+ -+#define PORT_TC4A_bm 0x01 /* Timer/Counter 4 Output Compare A bit mask. */ -+#define PORT_TC4A_bp 0 /* Timer/Counter 4 Output Compare A bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC4.CTRLA bit masks and bit positions */ -+#define TC4_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ -+#define TC4_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ -+ -+#define TC4_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ -+#define TC4_EVSTART_bp 5 /* Start on Next Event bit position. */ -+ -+#define TC4_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ -+#define TC4_UPSTOP_bp 4 /* Stop on Next Update bit position. */ -+ -+#define TC4_CLKSEL_gm 0x0F /* Clock Select group mask. */ -+#define TC4_CLKSEL_gp 0 /* Clock Select group position. */ -+#define TC4_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ -+#define TC4_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ -+#define TC4_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ -+#define TC4_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ -+#define TC4_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ -+#define TC4_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ -+#define TC4_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ -+#define TC4_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ -+ -+/* TC4.CTRLB bit masks and bit positions */ -+#define TC4_BYTEM_gm 0xC0 /* Byte Mode group mask. */ -+#define TC4_BYTEM_gp 6 /* Byte Mode group position. */ -+#define TC4_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ -+#define TC4_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ -+#define TC4_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ -+#define TC4_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ -+ -+#define TC4_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ -+#define TC4_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ -+#define TC4_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ -+#define TC4_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ -+#define TC4_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ -+#define TC4_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ -+ -+#define TC4_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ -+#define TC4_WGMODE_gp 0 /* Waveform Generation Mode group position. */ -+#define TC4_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ -+#define TC4_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ -+#define TC4_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ -+#define TC4_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ -+#define TC4_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ -+#define TC4_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ -+ -+/* TC4.CTRLC bit masks and bit positions */ -+#define TC4_POLD_bm 0x80 /* Channel D Output Polarity bit mask. */ -+#define TC4_POLD_bp 7 /* Channel D Output Polarity bit position. */ -+ -+#define TC4_POLC_bm 0x40 /* Channel C Output Polarity bit mask. */ -+#define TC4_POLC_bp 6 /* Channel C Output Polarity bit position. */ -+ -+#define TC4_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ -+#define TC4_POLB_bp 5 /* Channel B Output Polarity bit position. */ -+ -+#define TC4_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ -+#define TC4_POLA_bp 4 /* Channel A Output Polarity bit position. */ -+ -+#define TC4_CMPD_bm 0x08 /* Channel D Compare Output Value bit mask. */ -+#define TC4_CMPD_bp 3 /* Channel D Compare Output Value bit position. */ -+ -+#define TC4_CMPC_bm 0x04 /* Channel C Compare Output Value bit mask. */ -+#define TC4_CMPC_bp 2 /* Channel C Compare Output Value bit position. */ -+ -+#define TC4_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ -+#define TC4_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ -+ -+#define TC4_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ -+#define TC4_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ -+ -+#define TC4_HCMPD_bm 0x80 /* High Channel D Compare Output Value bit mask. */ -+#define TC4_HCMPD_bp 7 /* High Channel D Compare Output Value bit position. */ -+ -+#define TC4_HCMPC_bm 0x40 /* High Channel C Compare Output Value bit mask. */ -+#define TC4_HCMPC_bp 6 /* High Channel C Compare Output Value bit position. */ -+ -+#define TC4_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ -+#define TC4_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ -+ -+#define TC4_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ -+#define TC4_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ -+ -+#define TC4_LCMPD_bm 0x08 /* Low Channel D Compare Output Value bit mask. */ -+#define TC4_LCMPD_bp 3 /* Low Channel D Compare Output Value bit position. */ -+ -+#define TC4_LCMPC_bm 0x04 /* Low Channel C Compare Output Value bit mask. */ -+#define TC4_LCMPC_bp 2 /* Low Channel C Compare Output Value bit position. */ -+ -+#define TC4_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ -+#define TC4_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ -+ -+#define TC4_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ -+#define TC4_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ -+ -+/* TC4.CTRLD bit masks and bit positions */ -+#define TC4_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC4_EVACT_gp 5 /* Event Action group position. */ -+#define TC4_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC4_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC4_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC4_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC4_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC4_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC4_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC4_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC4_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC4_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC4_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC4_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC4_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC4_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC4_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC4_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC4_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC4_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC4.CTRLE bit masks and bit positions */ -+#define TC4_CCDMODE_gm 0xC0 /* Channel D Compare or Capture Mode group mask. */ -+#define TC4_CCDMODE_gp 6 /* Channel D Compare or Capture Mode group position. */ -+#define TC4_CCDMODE0_bm (1<<6) /* Channel D Compare or Capture Mode bit 0 mask. */ -+#define TC4_CCDMODE0_bp 6 /* Channel D Compare or Capture Mode bit 0 position. */ -+#define TC4_CCDMODE1_bm (1<<7) /* Channel D Compare or Capture Mode bit 1 mask. */ -+#define TC4_CCDMODE1_bp 7 /* Channel D Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_CCCMODE_gm 0x30 /* Channel C Compare or Capture Mode group mask. */ -+#define TC4_CCCMODE_gp 4 /* Channel C Compare or Capture Mode group position. */ -+#define TC4_CCCMODE0_bm (1<<4) /* Channel C Compare or Capture Mode bit 0 mask. */ -+#define TC4_CCCMODE0_bp 4 /* Channel C Compare or Capture Mode bit 0 position. */ -+#define TC4_CCCMODE1_bm (1<<5) /* Channel C Compare or Capture Mode bit 1 mask. */ -+#define TC4_CCCMODE1_bp 5 /* Channel C Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ -+#define TC4_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ -+#define TC4_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ -+#define TC4_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ -+#define TC4_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ -+#define TC4_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ -+#define TC4_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ -+#define TC4_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ -+#define TC4_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ -+#define TC4_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ -+#define TC4_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_LCCDMODE_gm 0xC0 /* Channel Low D Compare or Capture Mode group mask. */ -+#define TC4_LCCDMODE_gp 6 /* Channel Low D Compare or Capture Mode group position. */ -+#define TC4_LCCDMODE0_bm (1<<6) /* Channel Low D Compare or Capture Mode bit 0 mask. */ -+#define TC4_LCCDMODE0_bp 6 /* Channel Low D Compare or Capture Mode bit 0 position. */ -+#define TC4_LCCDMODE1_bm (1<<7) /* Channel Low D Compare or Capture Mode bit 1 mask. */ -+#define TC4_LCCDMODE1_bp 7 /* Channel Low D Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_LCCCMODE_gm 0x30 /* Channel Low C Compare or Capture Mode group mask. */ -+#define TC4_LCCCMODE_gp 4 /* Channel Low C Compare or Capture Mode group position. */ -+#define TC4_LCCCMODE0_bm (1<<4) /* Channel Low C Compare or Capture Mode bit 0 mask. */ -+#define TC4_LCCCMODE0_bp 4 /* Channel Low C Compare or Capture Mode bit 0 position. */ -+#define TC4_LCCCMODE1_bm (1<<5) /* Channel Low C Compare or Capture Mode bit 1 mask. */ -+#define TC4_LCCCMODE1_bp 5 /* Channel Low C Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ -+#define TC4_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ -+#define TC4_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ -+#define TC4_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ -+#define TC4_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ -+#define TC4_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ -+#define TC4_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ -+#define TC4_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ -+#define TC4_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ -+#define TC4_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ -+#define TC4_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ -+ -+/* TC4.CTRLF bit masks and bit positions */ -+#define TC4_HCCDMODE_gm 0xC0 /* Channel High D Compare or Capture Mode group mask. */ -+#define TC4_HCCDMODE_gp 6 /* Channel High D Compare or Capture Mode group position. */ -+#define TC4_HCCDMODE0_bm (1<<6) /* Channel High D Compare or Capture Mode bit 0 mask. */ -+#define TC4_HCCDMODE0_bp 6 /* Channel High D Compare or Capture Mode bit 0 position. */ -+#define TC4_HCCDMODE1_bm (1<<7) /* Channel High D Compare or Capture Mode bit 1 mask. */ -+#define TC4_HCCDMODE1_bp 7 /* Channel High D Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_HCCCMODE_gm 0x30 /* Channel High C Compare or Capture Mode group mask. */ -+#define TC4_HCCCMODE_gp 4 /* Channel High C Compare or Capture Mode group position. */ -+#define TC4_HCCCMODE0_bm (1<<4) /* Channel High C Compare or Capture Mode bit 0 mask. */ -+#define TC4_HCCCMODE0_bp 4 /* Channel High C Compare or Capture Mode bit 0 position. */ -+#define TC4_HCCCMODE1_bm (1<<5) /* Channel High C Compare or Capture Mode bit 1 mask. */ -+#define TC4_HCCCMODE1_bp 5 /* Channel High C Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ -+#define TC4_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ -+#define TC4_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ -+#define TC4_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ -+#define TC4_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ -+#define TC4_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ -+#define TC4_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ -+#define TC4_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ -+#define TC4_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ -+#define TC4_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ -+#define TC4_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ -+ -+/* TC4.INTCTRLA bit masks and bit positions */ -+#define TC4_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ -+#define TC4_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ -+#define TC4_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ -+#define TC4_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ -+#define TC4_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ -+#define TC4_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ -+ -+#define TC4_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ -+#define TC4_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ -+#define TC4_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ -+#define TC4_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ -+#define TC4_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ -+#define TC4_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ -+ -+#define TC4_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ -+#define TC4_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ -+#define TC4_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ -+#define TC4_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ -+#define TC4_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ -+#define TC4_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ -+ -+/* TC4.INTCTRLB bit masks and bit positions */ -+#define TC4_CCDINTLVL_gm 0xC0 /* Channel D Compare or Capture Interrupt Level group mask. */ -+#define TC4_CCDINTLVL_gp 6 /* Channel D Compare or Capture Interrupt Level group position. */ -+#define TC4_CCDINTLVL0_bm (1<<6) /* Channel D Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC4_CCDINTLVL0_bp 6 /* Channel D Compare or Capture Interrupt Level bit 0 position. */ -+#define TC4_CCDINTLVL1_bm (1<<7) /* Channel D Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC4_CCDINTLVL1_bp 7 /* Channel D Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC4_CCCINTLVL_gm 0x30 /* Channel C Compare or Capture Interrupt Level group mask. */ -+#define TC4_CCCINTLVL_gp 4 /* Channel C Compare or Capture Interrupt Level group position. */ -+#define TC4_CCCINTLVL0_bm (1<<4) /* Channel C Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC4_CCCINTLVL0_bp 4 /* Channel C Compare or Capture Interrupt Level bit 0 position. */ -+#define TC4_CCCINTLVL1_bm (1<<5) /* Channel C Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC4_CCCINTLVL1_bp 5 /* Channel C Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC4_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ -+#define TC4_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ -+#define TC4_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC4_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ -+#define TC4_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC4_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC4_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ -+#define TC4_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ -+#define TC4_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC4_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ -+#define TC4_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC4_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC4_LCCDINTLVL_gm 0xC0 /* Channel Low D Compare or Capture Interrupt Level group mask. */ -+#define TC4_LCCDINTLVL_gp 6 /* Channel Low D Compare or Capture Interrupt Level group position. */ -+#define TC4_LCCDINTLVL0_bm (1<<6) /* Channel Low D Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC4_LCCDINTLVL0_bp 6 /* Channel Low D Compare or Capture Interrupt Level bit 0 position. */ -+#define TC4_LCCDINTLVL1_bm (1<<7) /* Channel Low D Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC4_LCCDINTLVL1_bp 7 /* Channel Low D Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC4_LCCCINTLVL_gm 0x30 /* Channel Low C Compare or Capture Interrupt Level group mask. */ -+#define TC4_LCCCINTLVL_gp 4 /* Channel Low C Compare or Capture Interrupt Level group position. */ -+#define TC4_LCCCINTLVL0_bm (1<<4) /* Channel Low C Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC4_LCCCINTLVL0_bp 4 /* Channel Low C Compare or Capture Interrupt Level bit 0 position. */ -+#define TC4_LCCCINTLVL1_bm (1<<5) /* Channel Low C Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC4_LCCCINTLVL1_bp 5 /* Channel Low C Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC4_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ -+#define TC4_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ -+#define TC4_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC4_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ -+#define TC4_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC4_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC4_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ -+#define TC4_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ -+#define TC4_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC4_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ -+#define TC4_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC4_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ -+ -+/* TC4.CTRLGCLR bit masks and bit positions */ -+#define TC4_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ -+#define TC4_STOP_bp 5 /* Timer/Counter Stop bit position. */ -+ -+#define TC4_CMD_gm 0x0C /* Command group mask. */ -+#define TC4_CMD_gp 2 /* Command group position. */ -+#define TC4_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC4_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC4_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC4_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC4_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC4_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC4_DIR_bm 0x01 /* Counter Direction bit mask. */ -+#define TC4_DIR_bp 0 /* Counter Direction bit position. */ -+ -+/* TC4.CTRLGSET bit masks and bit positions */ -+/* TC4_STOP Predefined. */ -+/* TC4_STOP Predefined. */ -+ -+/* TC4_CMD Predefined. */ -+/* TC4_CMD Predefined. */ -+ -+/* TC4_LUPD Predefined. */ -+/* TC4_LUPD Predefined. */ -+ -+/* TC4_DIR Predefined. */ -+/* TC4_DIR Predefined. */ -+ -+/* TC4.CTRLHCLR bit masks and bit positions */ -+#define TC4_CCDBV_bm 0x10 /* Channel D Compare or Capture Buffer Valid bit mask. */ -+#define TC4_CCDBV_bp 4 /* Channel D Compare or Capture Buffer Valid bit position. */ -+ -+#define TC4_CCCBV_bm 0x08 /* Channel C Compare or Capture Buffer Valid bit mask. */ -+#define TC4_CCCBV_bp 3 /* Channel C Compare or Capture Buffer Valid bit position. */ -+ -+#define TC4_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ -+#define TC4_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ -+ -+#define TC4_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ -+#define TC4_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ -+ -+#define TC4_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC4_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+#define TC4_LCCDBV_bm 0x10 /* Channel Low D Compare or Capture Buffer Valid bit mask. */ -+#define TC4_LCCDBV_bp 4 /* Channel Low D Compare or Capture Buffer Valid bit position. */ -+ -+#define TC4_LCCCBV_bm 0x08 /* Channel Low C Compare or Capture Buffer Valid bit mask. */ -+#define TC4_LCCCBV_bp 3 /* Channel Low C Compare or Capture Buffer Valid bit position. */ -+ -+#define TC4_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ -+#define TC4_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ -+ -+#define TC4_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ -+#define TC4_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ -+ -+#define TC4_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ -+#define TC4_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ -+ -+/* TC4.CTRLHSET bit masks and bit positions */ -+/* TC4_CCDBV Predefined. */ -+/* TC4_CCDBV Predefined. */ -+ -+/* TC4_CCCBV Predefined. */ -+/* TC4_CCCBV Predefined. */ -+ -+/* TC4_CCBBV Predefined. */ -+/* TC4_CCBBV Predefined. */ -+ -+/* TC4_CCABV Predefined. */ -+/* TC4_CCABV Predefined. */ -+ -+/* TC4_PERBV Predefined. */ -+/* TC4_PERBV Predefined. */ -+ -+/* TC4_LCCDBV Predefined. */ -+/* TC4_LCCDBV Predefined. */ -+ -+/* TC4_LCCCBV Predefined. */ -+/* TC4_LCCCBV Predefined. */ -+ -+/* TC4_LCCBBV Predefined. */ -+/* TC4_LCCBBV Predefined. */ -+ -+/* TC4_LCCABV Predefined. */ -+/* TC4_LCCABV Predefined. */ -+ -+/* TC4_LPERBV Predefined. */ -+/* TC4_LPERBV Predefined. */ -+ -+/* TC4.INTFLAGS bit masks and bit positions */ -+#define TC4_CCDIF_bm 0x80 /* Channel D Compare or Capture Interrupt Flag bit mask. */ -+#define TC4_CCDIF_bp 7 /* Channel D Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC4_CCCIF_bm 0x40 /* Channel C Compare or Capture Interrupt Flag bit mask. */ -+#define TC4_CCCIF_bp 6 /* Channel C Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC4_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ -+#define TC4_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC4_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ -+#define TC4_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC4_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ -+#define TC4_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ -+ -+#define TC4_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC4_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC4_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ -+#define TC4_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ -+ -+#define TC4_LCCDIF_bm 0x80 /* Channel Low D Compare or Capture Interrupt Flag bit mask. */ -+#define TC4_LCCDIF_bp 7 /* Channel Low D Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC4_LCCCIF_bm 0x40 /* Channel Low C Compare or Capture Interrupt Flag bit mask. */ -+#define TC4_LCCCIF_bp 6 /* Channel Low C Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC4_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ -+#define TC4_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC4_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ -+#define TC4_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ -+ -+/* TC5.CTRLA bit masks and bit positions */ -+#define TC5_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ -+#define TC5_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ -+ -+#define TC5_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ -+#define TC5_EVSTART_bp 5 /* Start on Next Event bit position. */ -+ -+#define TC5_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ -+#define TC5_UPSTOP_bp 4 /* Stop on Next Update bit position. */ -+ -+#define TC5_CLKSEL_gm 0x0F /* Clock Select group mask. */ -+#define TC5_CLKSEL_gp 0 /* Clock Select group position. */ -+#define TC5_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ -+#define TC5_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ -+#define TC5_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ -+#define TC5_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ -+#define TC5_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ -+#define TC5_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ -+#define TC5_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ -+#define TC5_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ -+ -+/* TC5.CTRLB bit masks and bit positions */ -+#define TC5_BYTEM_gm 0xC0 /* Byte Mode group mask. */ -+#define TC5_BYTEM_gp 6 /* Byte Mode group position. */ -+#define TC5_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ -+#define TC5_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ -+#define TC5_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ -+#define TC5_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ -+ -+#define TC5_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ -+#define TC5_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ -+#define TC5_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ -+#define TC5_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ -+#define TC5_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ -+#define TC5_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ -+ -+#define TC5_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ -+#define TC5_WGMODE_gp 0 /* Waveform Generation Mode group position. */ -+#define TC5_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ -+#define TC5_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ -+#define TC5_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ -+#define TC5_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ -+#define TC5_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ -+#define TC5_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ -+ -+/* TC5.CTRLC bit masks and bit positions */ -+#define TC5_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ -+#define TC5_POLB_bp 5 /* Channel B Output Polarity bit position. */ -+ -+#define TC5_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ -+#define TC5_POLA_bp 4 /* Channel A Output Polarity bit position. */ -+ -+#define TC5_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ -+#define TC5_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ -+ -+#define TC5_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ -+#define TC5_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ -+ -+#define TC5_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ -+#define TC5_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ -+ -+#define TC5_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ -+#define TC5_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ -+ -+#define TC5_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ -+#define TC5_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ -+ -+#define TC5_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ -+#define TC5_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ -+ -+/* TC5.CTRLD bit masks and bit positions */ -+#define TC5_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC5_EVACT_gp 5 /* Event Action group position. */ -+#define TC5_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC5_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC5_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC5_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC5_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC5_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC5_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC5_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC5_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC5_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC5_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC5_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC5_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC5_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC5_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC5_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC5_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC5_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC5.CTRLE bit masks and bit positions */ -+#define TC5_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ -+#define TC5_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ -+#define TC5_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ -+#define TC5_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ -+#define TC5_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ -+#define TC5_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ -+ -+#define TC5_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ -+#define TC5_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ -+#define TC5_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ -+#define TC5_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ -+#define TC5_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ -+#define TC5_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ -+ -+#define TC5_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ -+#define TC5_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ -+#define TC5_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ -+#define TC5_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ -+#define TC5_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ -+#define TC5_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ -+ -+#define TC5_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ -+#define TC5_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ -+#define TC5_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ -+#define TC5_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ -+#define TC5_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ -+#define TC5_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ -+ -+/* TC5.CTRLF bit masks and bit positions */ -+#define TC5_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ -+#define TC5_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ -+#define TC5_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ -+#define TC5_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ -+#define TC5_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ -+#define TC5_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ -+ -+#define TC5_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ -+#define TC5_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ -+#define TC5_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ -+#define TC5_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ -+#define TC5_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ -+#define TC5_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ -+ -+/* TC5.INTCTRLA bit masks and bit positions */ -+#define TC5_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ -+#define TC5_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ -+#define TC5_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ -+#define TC5_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ -+#define TC5_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ -+#define TC5_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ -+ -+#define TC5_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ -+#define TC5_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ -+#define TC5_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ -+#define TC5_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ -+#define TC5_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ -+#define TC5_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ -+ -+#define TC5_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ -+#define TC5_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ -+#define TC5_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ -+#define TC5_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ -+#define TC5_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ -+#define TC5_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ -+ -+/* TC5.INTCTRLB bit masks and bit positions */ -+#define TC5_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ -+#define TC5_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ -+#define TC5_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC5_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ -+#define TC5_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC5_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC5_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ -+#define TC5_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ -+#define TC5_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC5_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ -+#define TC5_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC5_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC5_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ -+#define TC5_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ -+#define TC5_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC5_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ -+#define TC5_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC5_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC5_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ -+#define TC5_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ -+#define TC5_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC5_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ -+#define TC5_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC5_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ -+ -+/* TC5.CTRLGCLR bit masks and bit positions */ -+#define TC5_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ -+#define TC5_STOP_bp 5 /* Timer/Counter Stop bit position. */ -+ -+#define TC5_CMD_gm 0x0C /* Command group mask. */ -+#define TC5_CMD_gp 2 /* Command group position. */ -+#define TC5_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC5_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC5_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC5_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC5_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC5_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC5_DIR_bm 0x01 /* Counter Direction bit mask. */ -+#define TC5_DIR_bp 0 /* Counter Direction bit position. */ -+ -+/* TC5.CTRLGSET bit masks and bit positions */ -+/* TC5_STOP Predefined. */ -+/* TC5_STOP Predefined. */ -+ -+/* TC5_CMD Predefined. */ -+/* TC5_CMD Predefined. */ -+ -+/* TC5_LUPD Predefined. */ -+/* TC5_LUPD Predefined. */ -+ -+/* TC5_DIR Predefined. */ -+/* TC5_DIR Predefined. */ -+ -+/* TC5.CTRLHCLR bit masks and bit positions */ -+#define TC5_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ -+#define TC5_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ -+ -+#define TC5_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ -+#define TC5_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ -+ -+#define TC5_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC5_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+#define TC5_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ -+#define TC5_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ -+ -+#define TC5_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ -+#define TC5_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ -+ -+#define TC5_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ -+#define TC5_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ -+ -+/* TC5.CTRLHSET bit masks and bit positions */ -+/* TC5_CCBBV Predefined. */ -+/* TC5_CCBBV Predefined. */ -+ -+/* TC5_CCABV Predefined. */ -+/* TC5_CCABV Predefined. */ -+ -+/* TC5_PERBV Predefined. */ -+/* TC5_PERBV Predefined. */ -+ -+/* TC5_LCCBBV Predefined. */ -+/* TC5_LCCBBV Predefined. */ -+ -+/* TC5_LCCABV Predefined. */ -+/* TC5_LCCABV Predefined. */ -+ -+/* TC5_LPERBV Predefined. */ -+/* TC5_LPERBV Predefined. */ -+ -+/* TC5.INTFLAGS bit masks and bit positions */ -+#define TC5_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ -+#define TC5_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC5_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ -+#define TC5_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC5_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ -+#define TC5_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ -+ -+#define TC5_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC5_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC5_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ -+#define TC5_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ -+ -+#define TC5_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ -+#define TC5_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC5_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ -+#define TC5_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ -+ -+/* FAULT - Fault Extension */ -+/* FAULT.CTRLA bit masks and bit positions */ -+#define FAULT_RAMP_gm 0xC0 /* Ramp Mode Selection group mask. */ -+#define FAULT_RAMP_gp 6 /* Ramp Mode Selection group position. */ -+#define FAULT_RAMP0_bm (1<<6) /* Ramp Mode Selection bit 0 mask. */ -+#define FAULT_RAMP0_bp 6 /* Ramp Mode Selection bit 0 position. */ -+#define FAULT_RAMP1_bm (1<<7) /* Ramp Mode Selection bit 1 mask. */ -+#define FAULT_RAMP1_bp 7 /* Ramp Mode Selection bit 1 position. */ -+ -+#define FAULT_FDDBD_bm 0x20 /* Fault on Debug Break Detection bit mask. */ -+#define FAULT_FDDBD_bp 5 /* Fault on Debug Break Detection bit position. */ -+ -+#define FAULT_PORTCTRL_bm 0x10 /* Port Control Mode bit mask. */ -+#define FAULT_PORTCTRL_bp 4 /* Port Control Mode bit position. */ -+ -+#define FAULT_FUSE_bm 0x08 /* Fuse State bit mask. */ -+#define FAULT_FUSE_bp 3 /* Fuse State bit position. */ -+ -+#define FAULT_FILTERE_bm 0x04 /* Fault E Digital Filter Selection bit mask. */ -+#define FAULT_FILTERE_bp 2 /* Fault E Digital Filter Selection bit position. */ -+ -+#define FAULT_SRCE_gm 0x03 /* Fault E Input selection group mask. */ -+#define FAULT_SRCE_gp 0 /* Fault E Input selection group position. */ -+#define FAULT_SRCE0_bm (1<<0) /* Fault E Input selection bit 0 mask. */ -+#define FAULT_SRCE0_bp 0 /* Fault E Input selection bit 0 position. */ -+#define FAULT_SRCE1_bm (1<<1) /* Fault E Input selection bit 1 mask. */ -+#define FAULT_SRCE1_bp 1 /* Fault E Input selection bit 1 position. */ -+ -+/* FAULT.CTRLB bit masks and bit positions */ -+#define FAULT_SOFTA_bm 0x80 /* Fault A Software Mode bit mask. */ -+#define FAULT_SOFTA_bp 7 /* Fault A Software Mode bit position. */ -+ -+#define FAULT_HALTA_gm 0x60 /* Fault A Halt Action group mask. */ -+#define FAULT_HALTA_gp 5 /* Fault A Halt Action group position. */ -+#define FAULT_HALTA0_bm (1<<5) /* Fault A Halt Action bit 0 mask. */ -+#define FAULT_HALTA0_bp 5 /* Fault A Halt Action bit 0 position. */ -+#define FAULT_HALTA1_bm (1<<6) /* Fault A Halt Action bit 1 mask. */ -+#define FAULT_HALTA1_bp 6 /* Fault A Halt Action bit 1 position. */ -+ -+#define FAULT_RESTARTA_bm 0x10 /* Fault A Restart Action bit mask. */ -+#define FAULT_RESTARTA_bp 4 /* Fault A Restart Action bit position. */ -+ -+#define FAULT_KEEPA_bm 0x08 /* Fault A Keep Action bit mask. */ -+#define FAULT_KEEPA_bp 3 /* Fault A Keep Action bit position. */ -+ -+#define FAULT_SRCA_gm 0x03 /* Fault A Source Selection group mask. */ -+#define FAULT_SRCA_gp 0 /* Fault A Source Selection group position. */ -+#define FAULT_SRCA0_bm (1<<0) /* Fault A Source Selection bit 0 mask. */ -+#define FAULT_SRCA0_bp 0 /* Fault A Source Selection bit 0 position. */ -+#define FAULT_SRCA1_bm (1<<1) /* Fault A Source Selection bit 1 mask. */ -+#define FAULT_SRCA1_bp 1 /* Fault A Source Selection bit 1 position. */ -+ -+/* FAULT.CTRLC bit masks and bit positions */ -+#define FAULT_CAPTA_bm 0x20 /* Fault A Capture bit mask. */ -+#define FAULT_CAPTA_bp 5 /* Fault A Capture bit position. */ -+ -+#define FAULT_FILTERA_bm 0x04 /* Fault A Digital Filter Selection bit mask. */ -+#define FAULT_FILTERA_bp 2 /* Fault A Digital Filter Selection bit position. */ -+ -+#define FAULT_BLANKA_bm 0x02 /* Fault A Blanking bit mask. */ -+#define FAULT_BLANKA_bp 1 /* Fault A Blanking bit position. */ -+ -+#define FAULT_QUALA_bm 0x01 /* Fault A Qualification bit mask. */ -+#define FAULT_QUALA_bp 0 /* Fault A Qualification bit position. */ -+ -+/* FAULT.CTRLD bit masks and bit positions */ -+#define FAULT_SOFTB_bm 0x80 /* Fault B Software Mode bit mask. */ -+#define FAULT_SOFTB_bp 7 /* Fault B Software Mode bit position. */ -+ -+#define FAULT_HALTB_gm 0x60 /* Fault B Halt Action group mask. */ -+#define FAULT_HALTB_gp 5 /* Fault B Halt Action group position. */ -+#define FAULT_HALTB0_bm (1<<5) /* Fault B Halt Action bit 0 mask. */ -+#define FAULT_HALTB0_bp 5 /* Fault B Halt Action bit 0 position. */ -+#define FAULT_HALTB1_bm (1<<6) /* Fault B Halt Action bit 1 mask. */ -+#define FAULT_HALTB1_bp 6 /* Fault B Halt Action bit 1 position. */ -+ -+#define FAULT_RESTARTB_bm 0x10 /* Fault B Restart Action bit mask. */ -+#define FAULT_RESTARTB_bp 4 /* Fault B Restart Action bit position. */ -+ -+#define FAULT_KEEPB_bm 0x08 /* Fault B Keep Action bit mask. */ -+#define FAULT_KEEPB_bp 3 /* Fault B Keep Action bit position. */ -+ -+#define FAULT_SRCB_gm 0x03 /* Fault B Source Selection group mask. */ -+#define FAULT_SRCB_gp 0 /* Fault B Source Selection group position. */ -+#define FAULT_SRCB0_bm (1<<0) /* Fault B Source Selection bit 0 mask. */ -+#define FAULT_SRCB0_bp 0 /* Fault B Source Selection bit 0 position. */ -+#define FAULT_SRCB1_bm (1<<1) /* Fault B Source Selection bit 1 mask. */ -+#define FAULT_SRCB1_bp 1 /* Fault B Source Selection bit 1 position. */ -+ -+/* FAULT.CTRLE bit masks and bit positions */ -+#define FAULT_CAPTB_bm 0x20 /* Fault B Capture bit mask. */ -+#define FAULT_CAPTB_bp 5 /* Fault B Capture bit position. */ -+ -+#define FAULT_FILTERB_bm 0x04 /* Fault B Digital Filter Selection bit mask. */ -+#define FAULT_FILTERB_bp 2 /* Fault B Digital Filter Selection bit position. */ -+ -+#define FAULT_BLANKB_bm 0x02 /* Fault B Blanking bit mask. */ -+#define FAULT_BLANKB_bp 1 /* Fault B Blanking bit position. */ -+ -+#define FAULT_QUALB_bm 0x01 /* Fault B Qualification bit mask. */ -+#define FAULT_QUALB_bp 0 /* Fault B Qualification bit position. */ -+ -+/* FAULT.STATUS bit masks and bit positions */ -+#define FAULT_STATEB_bm 0x80 /* Fault B State bit mask. */ -+#define FAULT_STATEB_bp 7 /* Fault B State bit position. */ -+ -+#define FAULT_STATEA_bm 0x40 /* Fault A State bit mask. */ -+#define FAULT_STATEA_bp 6 /* Fault A State bit position. */ -+ -+#define FAULT_STATEE_bm 0x20 /* Fault E State bit mask. */ -+#define FAULT_STATEE_bp 5 /* Fault E State bit position. */ -+ -+#define FAULT_IDX_bm 0x08 /* Channel Index Flag bit mask. */ -+#define FAULT_IDX_bp 3 /* Channel Index Flag bit position. */ -+ -+#define FAULT_FAULTBIN_bm 0x04 /* Fault B Flag bit mask. */ -+#define FAULT_FAULTBIN_bp 2 /* Fault B Flag bit position. */ -+ -+#define FAULT_FAULTAIN_bm 0x02 /* Fault A Flag bit mask. */ -+#define FAULT_FAULTAIN_bp 1 /* Fault A Flag bit position. */ -+ -+#define FAULT_FAULTEIN_bm 0x01 /* Fault E Flag bit mask. */ -+#define FAULT_FAULTEIN_bp 0 /* Fault E Flag bit position. */ -+ -+/* FAULT.CTRLGCLR bit masks and bit positions */ -+#define FAULT_HALTBCLR_bm 0x80 /* State B Clear bit mask. */ -+#define FAULT_HALTBCLR_bp 7 /* State B Clear bit position. */ -+ -+#define FAULT_HALTACLR_bm 0x40 /* State A Clear bit mask. */ -+#define FAULT_HALTACLR_bp 6 /* State A Clear bit position. */ -+ -+#define FAULT_STATEECLR_bm 0x20 /* State E Clear bit mask. */ -+#define FAULT_STATEECLR_bp 5 /* State E Clear bit position. */ -+ -+#define FAULT_FAULTB_bm 0x04 /* Fault B Flag bit mask. */ -+#define FAULT_FAULTB_bp 2 /* Fault B Flag bit position. */ -+ -+#define FAULT_FAULTA_bm 0x02 /* Fault A Flag bit mask. */ -+#define FAULT_FAULTA_bp 1 /* Fault A Flag bit position. */ -+ -+#define FAULT_FAULTE_bm 0x01 /* Fault E Flag bit mask. */ -+#define FAULT_FAULTE_bp 0 /* Fault E Flag bit position. */ -+ -+/* FAULT.CTRLGSET bit masks and bit positions */ -+#define FAULT_FAULTBSW_bm 0x80 /* Software Fault B bit mask. */ -+#define FAULT_FAULTBSW_bp 7 /* Software Fault B bit position. */ -+ -+#define FAULT_FAULTASW_bm 0x40 /* Software Fault A bit mask. */ -+#define FAULT_FAULTASW_bp 6 /* Software Fault A bit position. */ -+ -+#define FAULT_FAULTESW_bm 0x20 /* Software Fault E bit mask. */ -+#define FAULT_FAULTESW_bp 5 /* Software Fault E bit position. */ -+ -+#define FAULT_IDXCMD_gm 0x18 /* Channel index Command group mask. */ -+#define FAULT_IDXCMD_gp 3 /* Channel index Command group position. */ -+#define FAULT_IDXCMD0_bm (1<<3) /* Channel index Command bit 0 mask. */ -+#define FAULT_IDXCMD0_bp 3 /* Channel index Command bit 0 position. */ -+#define FAULT_IDXCMD1_bm (1<<4) /* Channel index Command bit 1 mask. */ -+#define FAULT_IDXCMD1_bp 4 /* Channel index Command bit 1 position. */ -+ -+/* WEX - Waveform Extension */ -+/* WEX.CTRL bit masks and bit positions */ -+#define WEX_UPSEL_bm 0x80 /* Update Source Selection bit mask. */ -+#define WEX_UPSEL_bp 7 /* Update Source Selection bit position. */ -+ -+#define WEX_OTMX_gm 0x70 /* Output Matrix group mask. */ -+#define WEX_OTMX_gp 4 /* Output Matrix group position. */ -+#define WEX_OTMX0_bm (1<<4) /* Output Matrix bit 0 mask. */ -+#define WEX_OTMX0_bp 4 /* Output Matrix bit 0 position. */ -+#define WEX_OTMX1_bm (1<<5) /* Output Matrix bit 1 mask. */ -+#define WEX_OTMX1_bp 5 /* Output Matrix bit 1 position. */ -+#define WEX_OTMX2_bm (1<<6) /* Output Matrix bit 2 mask. */ -+#define WEX_OTMX2_bp 6 /* Output Matrix bit 2 position. */ -+ -+#define WEX_DTI3EN_bm 0x08 /* Dead-Time Insertion Generator 3 Enable bit mask. */ -+#define WEX_DTI3EN_bp 3 /* Dead-Time Insertion Generator 3 Enable bit position. */ -+ -+#define WEX_DTI2EN_bm 0x04 /* Dead-Time Insertion Generator 2 Enable bit mask. */ -+#define WEX_DTI2EN_bp 2 /* Dead-Time Insertion Generator 2 Enable bit position. */ -+ -+#define WEX_DTI1EN_bm 0x02 /* Dead-Time Insertion Generator 1 Enable bit mask. */ -+#define WEX_DTI1EN_bp 1 /* Dead-Time Insertion Generator 1 Enable bit position. */ -+ -+#define WEX_DTI0EN_bm 0x01 /* Dead-Time Insertion Generator 0 Enable bit mask. */ -+#define WEX_DTI0EN_bp 0 /* Dead-Time Insertion Generator 0 Enable bit position. */ -+ -+/* WEX.STATUSCLR bit masks and bit positions */ -+#define WEX_SWAPBUF_bm 0x04 /* Swap Buffer Valid bit mask. */ -+#define WEX_SWAPBUF_bp 2 /* Swap Buffer Valid bit position. */ -+ -+#define WEX_PGVBUFV_bm 0x02 /* Pattern Generator Value Buffer Valid bit mask. */ -+#define WEX_PGVBUFV_bp 1 /* Pattern Generator Value Buffer Valid bit position. */ -+ -+#define WEX_PGOBUFV_bm 0x01 /* Pattern Generator Overwrite Buffer Valid bit mask. */ -+#define WEX_PGOBUFV_bp 0 /* Pattern Generator Overwrite Buffer Valid bit position. */ -+ -+/* WEX.STATUSSET bit masks and bit positions */ -+/* WEX_SWAPBUF Predefined. */ -+/* WEX_SWAPBUF Predefined. */ -+ -+/* WEX_PGVBUFV Predefined. */ -+/* WEX_PGVBUFV Predefined. */ -+ -+/* WEX_PGOBUFV Predefined. */ -+/* WEX_PGOBUFV Predefined. */ -+ -+/* WEX.SWAP bit masks and bit positions */ -+#define WEX_SWAP3_bm 0x08 /* Swap DTI output pair 3 bit mask. */ -+#define WEX_SWAP3_bp 3 /* Swap DTI output pair 3 bit position. */ -+ -+#define WEX_SWAP2_bm 0x04 /* Swap DTI output pair 2 bit mask. */ -+#define WEX_SWAP2_bp 2 /* Swap DTI output pair 2 bit position. */ -+ -+#define WEX_SWAP1_bm 0x02 /* Swap DTI output pair 1 bit mask. */ -+#define WEX_SWAP1_bp 1 /* Swap DTI output pair 1 bit position. */ -+ -+#define WEX_SWAP0_bm 0x01 /* Swap DTI output pair 0 bit mask. */ -+#define WEX_SWAP0_bp 0 /* Swap DTI output pair 0 bit position. */ -+ -+/* WEX.SWAPBUF bit masks and bit positions */ -+#define WEX_SWAP3BUF_bm 0x08 /* Swap DTI output pair 3 bit mask. */ -+#define WEX_SWAP3BUF_bp 3 /* Swap DTI output pair 3 bit position. */ -+ -+#define WEX_SWAP2BUF_bm 0x04 /* Swap DTI output pair 2 bit mask. */ -+#define WEX_SWAP2BUF_bp 2 /* Swap DTI output pair 2 bit position. */ -+ -+#define WEX_SWAP1BUF_bm 0x02 /* Swap DTI output pair 1 bit mask. */ -+#define WEX_SWAP1BUF_bp 1 /* Swap DTI output pair 1 bit position. */ -+ -+#define WEX_SWAP0BUF_bm 0x01 /* Swap DTI output pair 0 bit mask. */ -+#define WEX_SWAP0BUF_bp 0 /* Swap DTI output pair 0 bit position. */ -+ -+/* HIRES - High-Resolution Extension */ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HRPLUS_gm 0x0C /* High Resolution Plus group mask. */ -+#define HIRES_HRPLUS_gp 2 /* High Resolution Plus group position. */ -+#define HIRES_HRPLUS0_bm (1<<2) /* High Resolution Plus bit 0 mask. */ -+#define HIRES_HRPLUS0_bp 2 /* High Resolution Plus bit 0 position. */ -+#define HIRES_HRPLUS1_bm (1<<3) /* High Resolution Plus bit 1 mask. */ -+#define HIRES_HRPLUS1_bp 3 /* High Resolution Plus bit 1 position. */ -+ -+#define HIRES_HREN_gm 0x03 /* High Resolution Mode group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Mode group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Mode bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Mode bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Mode bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Mode bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXSIF_bm 0x02 /* Receive Start Bit Interrupt Flag bit mask. */ -+#define USART_RXSIF_bp 1 /* Receive Start Bit Interrupt Flag bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+#define USART_DRIF_bm 0x01 /* Data Reception Flag bit mask. */ -+#define USART_DRIF_bp 0 /* Data Reception Flag bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXSIE_bm 0x80 /* Receive Start Interrupt Enable bit mask. */ -+#define USART_RXSIE_bp 7 /* Receive Start Interrupt Enable bit position. */ -+ -+#define USART_DRIE_bm 0x40 /* Data Reception Interrupt Enable bit mask. */ -+#define USART_DRIE_bp 6 /* Data Reception Interrupt Enable bit position. */ -+ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_ONEWIRE_bm 0x80 /* One Wire Mode bit mask. */ -+#define USART_ONEWIRE_bp 7 /* One Wire Mode bit position. */ -+ -+#define USART_SFDEN_bm 0x40 /* Start Frame Detection Enable bit mask. */ -+#define USART_SFDEN_bp 6 /* Start Frame Detection Enable bit position. */ -+ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+/* USART.CTRLD bit masks and bit positions */ -+#define USART_DECTYPE_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_DECTYPE_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_DECTYPE0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_DECTYPE0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_DECTYPE1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_DECTYPE1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_LUTACT_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_LUTACT_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_LUTACT0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_LUTACT0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_LUTACT1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_LUTACT1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_PECACT_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_PECACT_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_PECACT0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_PECACT0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_PECACT1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_PECACT1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable SPI Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable SPI Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ -+#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit position. */ -+ -+#define SPI_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ -+#define SPI_TXCIE_bp 6 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit position. */ -+ -+#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit mask. */ -+#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit position. */ -+ -+#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit mask. */ -+#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit position. */ -+ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag (In Standard Mode Only). bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag (In Standard Mode Only). bit position. */ -+ -+#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ -+#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision Flag (In Standard Mode Only). bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision Flag (In Standard Mode Only). bit position. */ -+ -+#define SPI_TXCIF_bm 0x40 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ -+#define SPI_TXCIF_bp 6 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit position. */ -+ -+#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit mask. */ -+#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit position. */ -+ -+#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit mask. */ -+#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit position. */ -+ -+#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow (In Buffer Modes Only). bit mask. */ -+#define SPI_BUFOVF_bp 0 /* Buffer Overflow (In Buffer Modes Only). bit position. */ -+ -+/* SPI.CTRLB bit masks and bit positions */ -+#define SPI_BUFMODE_gm 0xC0 /* Buffer Modes group mask. */ -+#define SPI_BUFMODE_gp 6 /* Buffer Modes group position. */ -+#define SPI_BUFMODE0_bm (1<<6) /* Buffer Modes bit 0 mask. */ -+#define SPI_BUFMODE0_bp 6 /* Buffer Modes bit 0 position. */ -+#define SPI_BUFMODE1_bm (1<<7) /* Buffer Modes bit 1 mask. */ -+#define SPI_BUFMODE1_bp 7 /* Buffer Modes bit 1 position. */ -+ -+#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ -+#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* NVM_FUSES.FUSEBYTE6 bit masks and bit positions */ -+#define NVM_FUSES_FDACT5_bm 0x80 /* Fault Dectection Action on TC5 bit mask. */ -+#define NVM_FUSES_FDACT5_bp 7 /* Fault Dectection Action on TC5 bit position. */ -+ -+#define NVM_FUSES_FDACT4_bm 0x40 /* Fault Dectection Action on TC4 bit mask. */ -+#define NVM_FUSES_FDACT4_bp 6 /* Fault Dectection Action on TC4 bit position. */ -+ -+#define NVM_FUSES_VALUE_gm 0x3F /* Port Pin Value group mask. */ -+#define NVM_FUSES_VALUE_gp 0 /* Port Pin Value group position. */ -+#define NVM_FUSES_VALUE0_bm (1<<0) /* Port Pin Value bit 0 mask. */ -+#define NVM_FUSES_VALUE0_bp 0 /* Port Pin Value bit 0 position. */ -+#define NVM_FUSES_VALUE1_bm (1<<1) /* Port Pin Value bit 1 mask. */ -+#define NVM_FUSES_VALUE1_bp 1 /* Port Pin Value bit 1 position. */ -+#define NVM_FUSES_VALUE2_bm (1<<2) /* Port Pin Value bit 2 mask. */ -+#define NVM_FUSES_VALUE2_bp 2 /* Port Pin Value bit 2 position. */ -+#define NVM_FUSES_VALUE3_bm (1<<3) /* Port Pin Value bit 3 mask. */ -+#define NVM_FUSES_VALUE3_bp 3 /* Port Pin Value bit 3 position. */ -+#define NVM_FUSES_VALUE4_bm (1<<4) /* Port Pin Value bit 4 mask. */ -+#define NVM_FUSES_VALUE4_bp 4 /* Port Pin Value bit 4 position. */ -+#define NVM_FUSES_VALUE5_bm (1<<5) /* Port Pin Value bit 5 mask. */ -+#define NVM_FUSES_VALUE5_bp 5 /* Port Pin Value bit 5 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT_vect_num 2 -+#define PORTR_INT_vect _VECTOR(2) /* External Interrupt */ -+ -+/* EDMA interrupt vectors */ -+#define EDMA_CH0_vect_num 3 -+#define EDMA_CH0_vect _VECTOR(3) /* EDMA Channel 0 Interrupt */ -+#define EDMA_CH1_vect_num 4 -+#define EDMA_CH1_vect _VECTOR(4) /* EDMA Channel 1 Interrupt */ -+#define EDMA_CH2_vect_num 5 -+#define EDMA_CH2_vect _VECTOR(5) /* EDMA Channel 2 Interrupt */ -+#define EDMA_CH3_vect_num 6 -+#define EDMA_CH3_vect _VECTOR(6) /* EDMA Channel 3 Interrupt */ -+ -+/* RTC interrupt vectors */ -+#define RTC_OVF_vect_num 7 -+#define RTC_OVF_vect _VECTOR(7) /* Overflow Interrupt */ -+#define RTC_COMP_vect_num 8 -+#define RTC_COMP_vect _VECTOR(8) /* Compare Interrupt */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT_vect_num 9 -+#define PORTC_INT_vect _VECTOR(9) /* External Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 10 -+#define TWIC_TWIS_vect _VECTOR(10) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 11 -+#define TWIC_TWIM_vect _VECTOR(11) /* TWI Master Interrupt */ -+ -+/* TCC4 interrupt vectors */ -+#define TCC4_OVF_vect_num 12 -+#define TCC4_OVF_vect _VECTOR(12) /* Overflow Interrupt */ -+#define TCC4_ERR_vect_num 13 -+#define TCC4_ERR_vect _VECTOR(13) /* Error Interrupt */ -+#define TCC4_CCA_vect_num 14 -+#define TCC4_CCA_vect _VECTOR(14) /* Channel A Compare or Capture Interrupt */ -+#define TCC4_CCB_vect_num 15 -+#define TCC4_CCB_vect _VECTOR(15) /* Channel B Compare or Capture Interrupt */ -+#define TCC4_CCC_vect_num 16 -+#define TCC4_CCC_vect _VECTOR(16) /* Channel C Compare or Capture Interrupt */ -+#define TCC4_CCD_vect_num 17 -+#define TCC4_CCD_vect _VECTOR(17) /* Channel D Compare or Capture Interrupt */ -+ -+/* TCC5 interrupt vectors */ -+#define TCC5_OVF_vect_num 18 -+#define TCC5_OVF_vect _VECTOR(18) /* Overflow Interrupt */ -+#define TCC5_ERR_vect_num 19 -+#define TCC5_ERR_vect _VECTOR(19) /* Error Interrupt */ -+#define TCC5_CCA_vect_num 20 -+#define TCC5_CCA_vect _VECTOR(20) /* Channel A Compare or Capture Interrupt */ -+#define TCC5_CCB_vect_num 21 -+#define TCC5_CCB_vect _VECTOR(21) /* Channel B Compare or Capture Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 22 -+#define SPIC_INT_vect _VECTOR(22) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 23 -+#define USARTC0_RXC_vect _VECTOR(23) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 24 -+#define USARTC0_DRE_vect _VECTOR(24) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 25 -+#define USARTC0_TXC_vect _VECTOR(25) /* Transmission Complete Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 26 -+#define NVM_EE_vect _VECTOR(26) /* EE Interrupt */ -+#define NVM_SPM_vect_num 27 -+#define NVM_SPM_vect _VECTOR(27) /* SPM Interrupt */ -+ -+/* XCL interrupt vectors */ -+#define XCL_UNF_vect_num 28 -+#define XCL_UNF_vect _VECTOR(28) /* Timer/Counter Underflow Interrupt */ -+#define XCL_CC_vect_num 29 -+#define XCL_CC_vect _VECTOR(29) /* Timer/Counter Compare or Capture Interrupt */ -+ -+/* PORTA interrupt vectors */ -+#define PORTA_INT_vect_num 30 -+#define PORTA_INT_vect _VECTOR(30) /* External Interrupt */ -+ -+/* ACA interrupt vectors */ -+#define ACA_AC0_vect_num 31 -+#define ACA_AC0_vect _VECTOR(31) /* AC0 Interrupt */ -+#define ACA_AC1_vect_num 32 -+#define ACA_AC1_vect _VECTOR(32) /* AC1 Interrupt */ -+#define ACA_ACW_vect_num 33 -+#define ACA_ACW_vect _VECTOR(33) /* ACW Window Mode Interrupt */ -+ -+/* ADCA interrupt vectors */ -+#define ADCA_CH0_vect_num 34 -+#define ADCA_CH0_vect _VECTOR(34) /* ADC Channel Interrupt */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT_vect_num 35 -+#define PORTD_INT_vect _VECTOR(35) /* External Interrupt */ -+ -+/* TCD5 interrupt vectors */ -+#define TCD5_OVF_vect_num 36 -+#define TCD5_OVF_vect _VECTOR(36) /* Overflow Interrupt */ -+#define TCD5_ERR_vect_num 37 -+#define TCD5_ERR_vect _VECTOR(37) /* Error Interrupt */ -+#define TCD5_CCA_vect_num 38 -+#define TCD5_CCA_vect _VECTOR(38) /* Channel A Compare or Capture Interrupt */ -+#define TCD5_CCB_vect_num 39 -+#define TCD5_CCB_vect _VECTOR(39) /* Channel B Compare or Capture Interrupt */ -+ -+/* USARTD0 interrupt vectors */ -+#define USARTD0_RXC_vect_num 40 -+#define USARTD0_RXC_vect _VECTOR(40) /* Reception Complete Interrupt */ -+#define USARTD0_DRE_vect_num 41 -+#define USARTD0_DRE_vect _VECTOR(41) /* Data Register Empty Interrupt */ -+#define USARTD0_TXC_vect_num 42 -+#define USARTD0_TXC_vect _VECTOR(42) /* Transmission Complete Interrupt */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (43 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (20480) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (16384) -+#define APP_SECTION_PAGE_SIZE (128) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0x3000) -+#define APPTABLE_SECTION_SIZE (4096) -+#define APPTABLE_SECTION_PAGE_SIZE (128) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x4000) -+#define BOOT_SECTION_SIZE (4096) -+#define BOOT_SECTION_PAGE_SIZE (128) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (10240) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (512) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (2048) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (512) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (7) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (128) -+#define USER_SIGNATURES_PAGE_SIZE (128) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (52) -+#define PROD_SIGNATURES_PAGE_SIZE (128) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 128 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 7 -+ -+/* Fuse Byte 0 Reserved */ -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* Fuse Byte 6 */ -+#define FUSE_VALUE0 (unsigned char)~_BV(0) /* Port Pin Value Bit 0 */ -+#define FUSE_VALUE1 (unsigned char)~_BV(1) /* Port Pin Value Bit 1 */ -+#define FUSE_VALUE2 (unsigned char)~_BV(2) /* Port Pin Value Bit 2 */ -+#define FUSE_VALUE3 (unsigned char)~_BV(3) /* Port Pin Value Bit 3 */ -+#define FUSE_VALUE4 (unsigned char)~_BV(4) /* Port Pin Value Bit 4 */ -+#define FUSE_VALUE5 (unsigned char)~_BV(5) /* Port Pin Value Bit 5 */ -+#define FUSE_FDACT4 (unsigned char)~_BV(6) /* Fault Dectection Action on TC4 */ -+#define FUSE_FDACT5 (unsigned char)~_BV(7) /* Fault Dectection Action on TC5 */ -+#define FUSE6_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x94 -+#define SIGNATURE_2 0x45 -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA16E5_H_INCLUDED */ -+ -diff --git a/include/avr/iox192a3u.h b/include/avr/iox192a3u.h -new file mode 100644 -index 0000000..6c83e17 ---- /dev/null -+++ b/include/avr/iox192a3u.h -@@ -0,0 +1,7628 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox192a3u.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA192A3U_H_INCLUDED -+#define _AVR_ATXMEGA192A3U_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -+#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -+#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -+#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -+#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -+#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -+#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -+#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -+#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -+#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -+#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -+#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -+#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -+#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -+#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -+#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -+#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -+#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -+#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -+#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -+#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -+#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -+#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+VPORT - Virtual Ports -+-------------------------------------------------------------------------- -+*/ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t USBCTRL; /* USB Control Register */ -+} CLK_t; -+ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t PRPB; /* Power Reduction Port B */ -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t PRPD; /* Power Reduction Port D */ -+ register8_t PRPE; /* Power Reduction Port E */ -+ register8_t PRPF; /* Power Reduction Port F */ -+} PR_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+/* USB Prescaler Division Factor */ -+typedef enum CLK_USBPSDIV_enum -+{ -+ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ -+ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ -+ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ -+ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ -+ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ -+ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -+} CLK_USBPSDIV_t; -+ -+/* USB Clock Source */ -+typedef enum CLK_USBSRC_enum -+{ -+ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ -+ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -+} CLK_USBSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control Register */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+/* 2 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC2MCREF_enum -+{ -+ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC2MCREF_t; -+ -+/* 32 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC32MCREF_enum -+{ -+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -+} OSC_RC32MCREF_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t JTAGUID; /* JTAG User ID */ -+ register8_t reserved_0x05; -+ register8_t MCUCR; /* MCU Control */ -+ register8_t ANAINIT; /* Analog Startup Delay */ -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t AWEXLOCK; /* AWEX Lock */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORTCFG - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t VPCTRLA; /* Virtual Port Control Register A */ -+ register8_t VPCTRLB; /* Virtual Port Control Register B */ -+ register8_t CLKEVOUT; /* Clock and Event Out Register */ -+ register8_t EBIOUT; /* EBI Output register */ -+ register8_t EVOUTSEL; /* Event Output Select */ -+} PORTCFG_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP02MAP_enum -+{ -+ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ -+ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ -+ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ -+ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ -+ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ -+ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ -+ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ -+ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ -+ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ -+ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ -+ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ -+ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ -+ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ -+ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ -+ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ -+ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -+} PORTCFG_VP02MAP_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP13MAP_enum -+{ -+ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ -+ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ -+ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ -+ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ -+ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ -+ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ -+ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ -+ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ -+ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ -+ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ -+ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ -+ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ -+ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ -+ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ -+ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ -+ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -+} PORTCFG_VP13MAP_t; -+ -+/* System Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ -+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ -+ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -+} PORTCFG_CLKOUT_t; -+ -+/* Peripheral Clock Output Select */ -+typedef enum PORTCFG_CLKOUTSEL_enum -+{ -+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -+} PORTCFG_CLKOUTSEL_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ -+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ -+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -+} PORTCFG_EVOUT_t; -+ -+/* Clock and Event Output Port */ -+typedef enum PORTCFG_CLKEVPIN_enum -+{ -+ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ -+ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -+} PORTCFG_CLKEVPIN_t; -+ -+/* EBI Address Output Port */ -+typedef enum PORTCFG_EBIADROUT_enum -+{ -+ PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ -+ PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ -+ PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ -+ PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ -+} PORTCFG_EBIADROUT_t; -+ -+/* EBI Chip Select Output Port */ -+typedef enum PORTCFG_EBICSOUT_enum -+{ -+ PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ -+} PORTCFG_EBICSOUT_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -+ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ -+ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ -+ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ -+ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AES - AES Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* AES Module */ -+typedef struct AES_struct -+{ -+ register8_t CTRL; /* AES Control Register */ -+ register8_t STATUS; /* AES Status Register */ -+ register8_t STATE; /* AES State Register */ -+ register8_t KEY; /* AES Key Register */ -+ register8_t INTCTRL; /* AES Interrupt Control Register */ -+} AES_t; -+ -+/* Interrupt level */ -+typedef enum AES_INTLVL_enum -+{ -+ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} AES_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ -+ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ -+ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ -+ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DMA - DMA Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* DMA Channel */ -+typedef struct DMA_CH_struct -+{ -+ register8_t CTRLA; /* Channel Control */ -+ register8_t CTRLB; /* Channel Control */ -+ register8_t ADDRCTRL; /* Address Control */ -+ register8_t TRIGSRC; /* Channel Trigger Source */ -+ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ -+ register8_t REPCNT; /* Channel Repeat Count */ -+ register8_t reserved_0x07; -+ register8_t SRCADDR0; /* Channel Source Address 0 */ -+ register8_t SRCADDR1; /* Channel Source Address 1 */ -+ register8_t SRCADDR2; /* Channel Source Address 2 */ -+ register8_t reserved_0x0B; -+ register8_t DESTADDR0; /* Channel Destination Address 0 */ -+ register8_t DESTADDR1; /* Channel Destination Address 1 */ -+ register8_t DESTADDR2; /* Channel Destination Address 2 */ -+ register8_t reserved_0x0F; -+} DMA_CH_t; -+ -+ -+/* DMA Controller */ -+typedef struct DMA_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t reserved_0x01; -+ register8_t reserved_0x02; -+ register8_t INTFLAGS; /* Transfer Interrupt Status */ -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x05; -+ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ DMA_CH_t CH0; /* DMA Channel 0 */ -+ DMA_CH_t CH1; /* DMA Channel 1 */ -+ DMA_CH_t CH2; /* DMA Channel 2 */ -+ DMA_CH_t CH3; /* DMA Channel 3 */ -+} DMA_t; -+ -+/* Burst mode */ -+typedef enum DMA_CH_BURSTLEN_enum -+{ -+ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ -+ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ -+ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ -+ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -+} DMA_CH_BURSTLEN_t; -+ -+/* Source address reload mode */ -+typedef enum DMA_CH_SRCRELOAD_enum -+{ -+ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ -+ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ -+ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ -+ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -+} DMA_CH_SRCRELOAD_t; -+ -+/* Source addressing mode */ -+typedef enum DMA_CH_SRCDIR_enum -+{ -+ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ -+ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ -+ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -+} DMA_CH_SRCDIR_t; -+ -+/* Destination adress reload mode */ -+typedef enum DMA_CH_DESTRELOAD_enum -+{ -+ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ -+ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ -+ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ -+ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -+} DMA_CH_DESTRELOAD_t; -+ -+/* Destination adressing mode */ -+typedef enum DMA_CH_DESTDIR_enum -+{ -+ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ -+ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ -+ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -+} DMA_CH_DESTDIR_t; -+ -+/* Transfer trigger source */ -+typedef enum DMA_CH_TRIGSRC_enum -+{ -+ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ -+ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ -+ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ -+ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ -+ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ -+ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ -+ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ -+ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ -+ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ -+ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ -+ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ -+ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ -+ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ -+ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ -+ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ -+ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ -+ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ -+ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ -+ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ -+ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ -+ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ -+ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ -+ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ -+ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ -+ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ -+ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ -+ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ -+ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ -+ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ -+ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ -+ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ -+ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ -+ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ -+ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ -+ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -+} DMA_CH_TRIGSRC_t; -+ -+/* Double buffering mode */ -+typedef enum DMA_DBUFMODE_enum -+{ -+ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ -+ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ -+ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ -+ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -+} DMA_DBUFMODE_t; -+ -+/* Priority mode */ -+typedef enum DMA_PRIMODE_enum -+{ -+ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ -+ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ -+ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ -+ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -+} DMA_PRIMODE_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_ERRINTLVL_enum -+{ -+ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ -+ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ -+ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -+} DMA_CH_ERRINTLVL_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_TRNINTLVL_enum -+{ -+ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ -+ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -+} DMA_CH_TRNINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ -+ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ -+ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ -+ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t CH4CTRL; /* Channel 4 Control Register */ -+ register8_t CH5CTRL; /* Channel 5 Control Register */ -+ register8_t CH6CTRL; /* Channel 6 Control Register */ -+ register8_t CH7CTRL; /* Channel 7 Control Register */ -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+} EVSYS_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ -+ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ -+ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ -+ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ -+ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ -+ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ -+ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ -+ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ -+ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ -+ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ -+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ -+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ -+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ -+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ -+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ -+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ -+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ -+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ -+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ -+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ -+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ -+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ -+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ -+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ -+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ -+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ -+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ -+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ -+ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ -+ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ -+ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ -+ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ -+ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ -+ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ -+ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ -+ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ -+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ -+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ -+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ -+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ -+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ -+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ -+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ -+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ -+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ -+ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ -+ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ -+ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ -+ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ -+ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ -+ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ -+ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ -+ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ -+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ -+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ -+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ -+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -+ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ -+ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ -+ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ -+ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ -+ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ -+ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ -+ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ -+ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -+ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ -+ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ -+ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ -+ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -+} EVSYS_CHMUX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ -+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ -+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ -+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ -+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} NVM_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t reserved_0x07; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ _WORDREGISTER(CH1RES); /* Channel 1 Result */ -+ _WORDREGISTER(CH2RES); /* Channel 2 Result */ -+ _WORDREGISTER(CH3RES); /* Channel 3 Result */ -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+ ADC_CH_t CH1; /* ADC Channel 1 */ -+ ADC_CH_t CH2; /* ADC Channel 2 */ -+ ADC_CH_t CH3; /* ADC Channel 3 */ -+} ADC_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -+ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+ ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 3) */ -+ ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Groud (Input Mode = 3) */ -+ ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Groud (Input Mode = 4) */ -+ ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 4) */ -+} ADC_CH_MUXNEG_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Current Limitation Mode */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ -+} ADC_CURRLIMIT_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Channel sweep selection */ -+typedef enum ADC_SWEEP_enum -+{ -+ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ -+ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ -+ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ -+ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -+} ADC_SWEEP_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ -+ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ -+ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ -+ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ -+ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ -+ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ -+ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ -+ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -+ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ -+ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ -+ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ -+ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* DMA request selection */ -+typedef enum ADC_DMASEL_enum -+{ -+ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ -+ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ -+ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ -+ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -+} ADC_DMASEL_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DAC - Digital/Analog Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Digital-to-Analog Converter */ -+typedef struct DAC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t EVCTRL; /* Event Input Control */ -+ register8_t reserved_0x04; -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0GAINCAL; /* Gain Calibration */ -+ register8_t CH0OFFSETCAL; /* Offset Calibration */ -+ register8_t CH1GAINCAL; /* Gain Calibration */ -+ register8_t CH1OFFSETCAL; /* Offset Calibration */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ -+ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -+} DAC_t; -+ -+/* Output channel selection */ -+typedef enum DAC_CHSEL_enum -+{ -+ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ -+ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ -+ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -+} DAC_CHSEL_t; -+ -+/* Reference voltage selection */ -+typedef enum DAC_REFSEL_enum -+{ -+ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ -+ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ -+ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ -+ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -+} DAC_REFSEL_t; -+ -+/* Event channel selection */ -+typedef enum DAC_EVSEL_enum -+{ -+ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ -+ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ -+ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ -+ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ -+ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ -+ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ -+ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ -+ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -+} DAC_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC - Real-Time Counter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Real-Time Counter */ -+typedef struct RTC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary register */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ _WORDREGISTER(CNT); /* Count Register */ -+ _WORDREGISTER(PER); /* Period Register */ -+ _WORDREGISTER(COMP); /* Compare Register */ -+} RTC_t; -+ -+/* Prescaler Factor */ -+typedef enum RTC_PRESCALER_enum -+{ -+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ -+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ -+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ -+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ -+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ -+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ -+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ -+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -+} RTC_PRESCALER_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC_COMPINTLVL_enum -+{ -+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC_OVFINTLVL_enum -+{ -+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+} TWI_t; -+ -+/* SDA Hold Time */ -+typedef enum TWI_SDAHOLD_enum -+{ -+ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ -+ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ -+ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ -+ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -+} TWI_SDAHOLD_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USB - USB -+-------------------------------------------------------------------------- -+*/ -+ -+/* USB Endpoint */ -+typedef struct USB_EP_struct -+{ -+ register8_t STATUS; /* Endpoint Status */ -+ register8_t CTRL; /* Endpoint Control */ -+ _WORDREGISTER(CNT); /* USB Endpoint Counter */ -+ _WORDREGISTER(DATAPTR); /* Data Pointer */ -+ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -+} USB_EP_t; -+ -+ -+/* Universal Serial Bus */ -+typedef struct USB_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t FIFOWP; /* FIFO Write Pointer Register */ -+ register8_t FIFORP; /* FIFO Read Pointer Register */ -+ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ -+ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ -+ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ -+ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t reserved_0x20; -+ register8_t reserved_0x21; -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t CAL0; /* Calibration Byte 0 */ -+ register8_t CAL1; /* Calibration Byte 1 */ -+} USB_t; -+ -+ -+/* USB Endpoint Table */ -+typedef struct USB_EP_TABLE_struct -+{ -+ USB_EP_t EP0OUT; /* Endpoint 0 */ -+ USB_EP_t EP0IN; /* Endpoint 0 */ -+ USB_EP_t EP1OUT; /* Endpoint 1 */ -+ USB_EP_t EP1IN; /* Endpoint 1 */ -+ USB_EP_t EP2OUT; /* Endpoint 2 */ -+ USB_EP_t EP2IN; /* Endpoint 2 */ -+ USB_EP_t EP3OUT; /* Endpoint 3 */ -+ USB_EP_t EP3IN; /* Endpoint 3 */ -+ USB_EP_t EP4OUT; /* Endpoint 4 */ -+ USB_EP_t EP4IN; /* Endpoint 4 */ -+ USB_EP_t EP5OUT; /* Endpoint 5 */ -+ USB_EP_t EP5IN; /* Endpoint 5 */ -+ USB_EP_t EP6OUT; /* Endpoint 6 */ -+ USB_EP_t EP6IN; /* Endpoint 6 */ -+ USB_EP_t EP7OUT; /* Endpoint 7 */ -+ USB_EP_t EP7IN; /* Endpoint 7 */ -+ USB_EP_t EP8OUT; /* Endpoint 8 */ -+ USB_EP_t EP8IN; /* Endpoint 8 */ -+ USB_EP_t EP9OUT; /* Endpoint 9 */ -+ USB_EP_t EP9IN; /* Endpoint 9 */ -+ USB_EP_t EP10OUT; /* Endpoint 10 */ -+ USB_EP_t EP10IN; /* Endpoint 10 */ -+ USB_EP_t EP11OUT; /* Endpoint 11 */ -+ USB_EP_t EP11IN; /* Endpoint 11 */ -+ USB_EP_t EP12OUT; /* Endpoint 12 */ -+ USB_EP_t EP12IN; /* Endpoint 12 */ -+ USB_EP_t EP13OUT; /* Endpoint 13 */ -+ USB_EP_t EP13IN; /* Endpoint 13 */ -+ USB_EP_t EP14OUT; /* Endpoint 14 */ -+ USB_EP_t EP14IN; /* Endpoint 14 */ -+ USB_EP_t EP15OUT; /* Endpoint 15 */ -+ USB_EP_t EP15IN; /* Endpoint 15 */ -+ register8_t reserved_0x100; -+ register8_t reserved_0x101; -+ register8_t reserved_0x102; -+ register8_t reserved_0x103; -+ register8_t reserved_0x104; -+ register8_t reserved_0x105; -+ register8_t reserved_0x106; -+ register8_t reserved_0x107; -+ register8_t reserved_0x108; -+ register8_t reserved_0x109; -+ register8_t reserved_0x10A; -+ register8_t reserved_0x10B; -+ register8_t reserved_0x10C; -+ register8_t reserved_0x10D; -+ register8_t reserved_0x10E; -+ register8_t reserved_0x10F; -+ register8_t FRAMENUML; /* Frame Number Low Byte */ -+ register8_t FRAMENUMH; /* Frame Number High Byte */ -+} USB_EP_TABLE_t; -+ -+/* Interrupt level */ -+typedef enum USB_INTLVL_enum -+{ -+ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} USB_INTLVL_t; -+ -+/* USB Endpoint Type */ -+typedef enum USB_EP_TYPE_enum -+{ -+ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ -+ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ -+ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ -+ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -+} USB_EP_TYPE_t; -+ -+/* USB Endpoint Buffersize */ -+typedef enum USB_EP_BUFSIZE_enum -+{ -+ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ -+ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ -+ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ -+ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ -+ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ -+ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ -+ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ -+ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -+} USB_EP_BUFSIZE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - I/O Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INT0MASK; /* Port Interrupt 0 Mask */ -+ register8_t INT1MASK; /* Port Interrupt 1 Mask */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t REMAP; /* I/O Port Pin Remap Register */ -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Port Interrupt 0 Level */ -+typedef enum PORT_INT0LVL_enum -+{ -+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INT0LVL_t; -+ -+/* Port Interrupt 1 Level */ -+typedef enum PORT_INT1LVL_enum -+{ -+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ -+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ -+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -+} PORT_INT1LVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 0 */ -+typedef struct TC0_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC0_t; -+ -+ -+/* 16-bit Timer/Counter 1 */ -+typedef struct TC1_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+} TC1_t; -+ -+/* Clock Selection */ -+typedef enum TC_CLKSEL_enum -+{ -+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC_CLKSEL_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC_WGMODE_enum -+{ -+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC_WGMODE_t; -+ -+/* Byte Mode */ -+typedef enum TC_BYTEM_enum -+{ -+ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ -+ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -+} TC_BYTEM_t; -+ -+/* Event Action */ -+typedef enum TC_EVACT_enum -+{ -+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ -+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ -+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ -+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ -+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ -+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC_EVSEL_enum -+{ -+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC_EVSEL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC_ERRINTLVL_enum -+{ -+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC_OVFINTLVL_enum -+{ -+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_OVFINTLVL_t; -+ -+/* Compare or Capture D Interrupt Level */ -+typedef enum TC_CCDINTLVL_enum -+{ -+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC_CCDINTLVL_t; -+ -+/* Compare or Capture C Interrupt Level */ -+typedef enum TC_CCCINTLVL_enum -+{ -+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC_CCCINTLVL_t; -+ -+/* Compare or Capture B Interrupt Level */ -+typedef enum TC_CCBINTLVL_enum -+{ -+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_CCBINTLVL_t; -+ -+/* Compare or Capture A Interrupt Level */ -+typedef enum TC_CCAINTLVL_enum -+{ -+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_CCAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC_CMD_enum -+{ -+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC2 - 16-bit Timer/Counter type 2 -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter type 2 */ -+typedef struct TC2_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t reserved_0x03; -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t reserved_0x08; -+ register8_t CTRLF; /* Control Register F */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t LCNT; /* Low Byte Count */ -+ register8_t HCNT; /* High Byte Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t LPER; /* Low Byte Period */ -+ register8_t HPER; /* High Byte Period */ -+ register8_t LCMPA; /* Low Byte Compare A */ -+ register8_t HCMPA; /* High Byte Compare A */ -+ register8_t LCMPB; /* Low Byte Compare B */ -+ register8_t HCMPB; /* High Byte Compare B */ -+ register8_t LCMPC; /* Low Byte Compare C */ -+ register8_t HCMPC; /* High Byte Compare C */ -+ register8_t LCMPD; /* Low Byte Compare D */ -+ register8_t HCMPD; /* High Byte Compare D */ -+} TC2_t; -+ -+/* Clock Selection */ -+typedef enum TC2_CLKSEL_enum -+{ -+ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC2_CLKSEL_t; -+ -+/* Byte Mode */ -+typedef enum TC2_BYTEM_enum -+{ -+ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ -+ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -+} TC2_BYTEM_t; -+ -+/* High Byte Underflow Interrupt Level */ -+typedef enum TC2_HUNFINTLVL_enum -+{ -+ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_HUNFINTLVL_t; -+ -+/* Low Byte Underflow Interrupt Level */ -+typedef enum TC2_LUNFINTLVL_enum -+{ -+ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LUNFINTLVL_t; -+ -+/* Low Byte Compare D Interrupt Level */ -+typedef enum TC2_LCMPDINTLVL_enum -+{ -+ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC2_LCMPDINTLVL_t; -+ -+/* Low Byte Compare C Interrupt Level */ -+typedef enum TC2_LCMPCINTLVL_enum -+{ -+ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC2_LCMPCINTLVL_t; -+ -+/* Low Byte Compare B Interrupt Level */ -+typedef enum TC2_LCMPBINTLVL_enum -+{ -+ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_LCMPBINTLVL_t; -+ -+/* Low Byte Compare A Interrupt Level */ -+typedef enum TC2_LCMPAINTLVL_enum -+{ -+ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LCMPAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMD_enum -+{ -+ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC2_CMD_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMDEN_enum -+{ -+ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ -+ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ -+ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -+} TC2_CMDEN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AWEX - Timer/Counter Advanced Waveform Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Advanced Waveform Extension */ -+typedef struct AWEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t FDEMASK; /* Fault Detection Event Mask */ -+ register8_t FDCTRL; /* Fault Detection Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t STATUSSET; /* Status Set Register */ -+ register8_t DTBOTH; /* Dead Time Both Sides */ -+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ -+ register8_t DTLS; /* Dead Time Low Side */ -+ register8_t DTHS; /* Dead Time High Side */ -+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ -+ register8_t DTHSBUF; /* Dead Time High Side Buffer */ -+ register8_t OUTOVEN; /* Output Override Enable */ -+} AWEX_t; -+ -+/* Fault Detect Action */ -+typedef enum AWEX_FDACT_enum -+{ -+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ -+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -+} AWEX_FDACT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+HIRES - Timer/Counter High-Resolution Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register */ -+} HIRES_t; -+ -+/* High Resolution Enable */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ -+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ -+ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ -+ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ -+ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -+} IRDA_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t FUSEBYTE0; /* JTAG User ID */ -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+} NVM_FUSES_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* Timer Oscillator pin location */ -+typedef enum TOSCSEL_enum -+{ -+ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ -+ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -+} TOSCSEL_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -+} BOD_t; -+ -+/* BOD operation */ -+typedef enum BODACT_enum -+{ -+ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BODACT_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WDP_enum -+{ -+ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ -+ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ -+ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ -+ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ -+ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ -+ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ -+ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ -+ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ -+ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ -+ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ -+ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -+} WDP_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LOCKBIT - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ -+ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t USBCAL0; /* USB Calibration Byte 0 */ -+ register8_t USBCAL1; /* USB Calibration Byte 1 */ -+ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ -+ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ -+ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ -+ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ -+ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ -+ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ -+ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ -+ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ -+ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ -+ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+ register8_t reserved_0x40; -+ register8_t reserved_0x41; -+ register8_t reserved_0x42; -+ register8_t reserved_0x43; -+ register8_t reserved_0x44; -+ register8_t reserved_0x45; -+ register8_t reserved_0x46; -+ register8_t reserved_0x47; -+} NVM_PROD_SIGNATURES_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define AES (*(AES_t *) 0x00C0) /* AES Module */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ -+#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ -+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -+#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -+#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -+#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -+#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -+#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -+#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ -+#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ -+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -+#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -+#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -+#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ -+#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ -+#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ -+#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ -+#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -+#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ -+#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ -+#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -+#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -+#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -+#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -+#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -+#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -+#define GPIO_GPIORA _SFR_MEM8(0x000A) -+#define GPIO_GPIORB _SFR_MEM8(0x000B) -+#define GPIO_GPIORC _SFR_MEM8(0x000C) -+#define GPIO_GPIORD _SFR_MEM8(0x000D) -+#define GPIO_GPIORE _SFR_MEM8(0x000E) -+#define GPIO_GPIORF _SFR_MEM8(0x000F) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+#define GPIO_GPIO4 _SFR_MEM8(0x0004) -+#define GPIO_GPIO5 _SFR_MEM8(0x0005) -+#define GPIO_GPIO6 _SFR_MEM8(0x0006) -+#define GPIO_GPIO7 _SFR_MEM8(0x0007) -+#define GPIO_GPIO8 _SFR_MEM8(0x0008) -+#define GPIO_GPIO9 _SFR_MEM8(0x0009) -+#define GPIO_GPIOA _SFR_MEM8(0x000A) -+#define GPIO_GPIOB _SFR_MEM8(0x000B) -+#define GPIO_GPIOC _SFR_MEM8(0x000C) -+#define GPIO_GPIOD _SFR_MEM8(0x000D) -+#define GPIO_GPIOE _SFR_MEM8(0x000E) -+#define GPIO_GPIOF _SFR_MEM8(0x000F) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -+#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -+#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -+#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -+#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -+#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -+#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) -+#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) -+#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -+#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) -+#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) -+#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+#define CLK_USBCTRL _SFR_MEM8(0x0044) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* DFLL - DFLL */ -+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -+#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -+#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPB _SFR_MEM8(0x0072) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPD _SFR_MEM8(0x0074) -+#define PR_PRPE _SFR_MEM8(0x0075) -+#define PR_PRPF _SFR_MEM8(0x0076) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_JTAGUID _SFR_MEM8(0x0094) -+#define MCU_MCUCR _SFR_MEM8(0x0096) -+#define MCU_ANAINIT _SFR_MEM8(0x0097) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_AWEXLOCK _SFR_MEM8(0x0099) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) -+#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) -+ -+/* AES - AES Module */ -+#define AES_CTRL _SFR_MEM8(0x00C0) -+#define AES_STATUS _SFR_MEM8(0x00C1) -+#define AES_STATE _SFR_MEM8(0x00C2) -+#define AES_KEY _SFR_MEM8(0x00C3) -+#define AES_INTCTRL _SFR_MEM8(0x00C4) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* DMA - DMA Controller */ -+#define DMA_CTRL _SFR_MEM8(0x0100) -+#define DMA_INTFLAGS _SFR_MEM8(0x0103) -+#define DMA_STATUS _SFR_MEM8(0x0104) -+#define DMA_TEMP _SFR_MEM16(0x0106) -+#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -+#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -+#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -+#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -+#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -+#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -+#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -+#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -+#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -+#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -+#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -+#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -+#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -+#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -+#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -+#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -+#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -+#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -+#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -+#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -+#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -+#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -+#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -+#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -+#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -+#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -+#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -+#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -+#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -+#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -+#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -+#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -+#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -+#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -+#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -+#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -+#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -+#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -+#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -+#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -+#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -+#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -+#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -+#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -+#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -+#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -+#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -+#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -+#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -+#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -+#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -+#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -+#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -+#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCA_CTRLA _SFR_MEM8(0x0200) -+#define ADCA_CTRLB _SFR_MEM8(0x0201) -+#define ADCA_REFCTRL _SFR_MEM8(0x0202) -+#define ADCA_EVCTRL _SFR_MEM8(0x0203) -+#define ADCA_PRESCALER _SFR_MEM8(0x0204) -+#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -+#define ADCA_TEMP _SFR_MEM8(0x0207) -+#define ADCA_CAL _SFR_MEM16(0x020C) -+#define ADCA_CH0RES _SFR_MEM16(0x0210) -+#define ADCA_CH1RES _SFR_MEM16(0x0212) -+#define ADCA_CH2RES _SFR_MEM16(0x0214) -+#define ADCA_CH3RES _SFR_MEM16(0x0216) -+#define ADCA_CMP _SFR_MEM16(0x0218) -+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -+#define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -+#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -+#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -+#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -+#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -+#define ADCA_CH1_RES _SFR_MEM16(0x022C) -+#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) -+#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -+#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -+#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -+#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -+#define ADCA_CH2_RES _SFR_MEM16(0x0234) -+#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) -+#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -+#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -+#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -+#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -+#define ADCA_CH3_RES _SFR_MEM16(0x023C) -+#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCB_CTRLA _SFR_MEM8(0x0240) -+#define ADCB_CTRLB _SFR_MEM8(0x0241) -+#define ADCB_REFCTRL _SFR_MEM8(0x0242) -+#define ADCB_EVCTRL _SFR_MEM8(0x0243) -+#define ADCB_PRESCALER _SFR_MEM8(0x0244) -+#define ADCB_INTFLAGS _SFR_MEM8(0x0246) -+#define ADCB_TEMP _SFR_MEM8(0x0247) -+#define ADCB_CAL _SFR_MEM16(0x024C) -+#define ADCB_CH0RES _SFR_MEM16(0x0250) -+#define ADCB_CH1RES _SFR_MEM16(0x0252) -+#define ADCB_CH2RES _SFR_MEM16(0x0254) -+#define ADCB_CH3RES _SFR_MEM16(0x0256) -+#define ADCB_CMP _SFR_MEM16(0x0258) -+#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) -+#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) -+#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) -+#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) -+#define ADCB_CH0_RES _SFR_MEM16(0x0264) -+#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) -+#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) -+#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) -+#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) -+#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) -+#define ADCB_CH1_RES _SFR_MEM16(0x026C) -+#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) -+#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) -+#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) -+#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) -+#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) -+#define ADCB_CH2_RES _SFR_MEM16(0x0274) -+#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) -+#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) -+#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) -+#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) -+#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) -+#define ADCB_CH3_RES _SFR_MEM16(0x027C) -+#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) -+ -+/* DAC - Digital-to-Analog Converter */ -+#define DACB_CTRLA _SFR_MEM8(0x0320) -+#define DACB_CTRLB _SFR_MEM8(0x0321) -+#define DACB_CTRLC _SFR_MEM8(0x0322) -+#define DACB_EVCTRL _SFR_MEM8(0x0323) -+#define DACB_STATUS _SFR_MEM8(0x0325) -+#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) -+#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) -+#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) -+#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) -+#define DACB_CH0DATA _SFR_MEM16(0x0338) -+#define DACB_CH1DATA _SFR_MEM16(0x033A) -+ -+/* AC - Analog Comparator */ -+#define ACA_AC0CTRL _SFR_MEM8(0x0380) -+#define ACA_AC1CTRL _SFR_MEM8(0x0381) -+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -+#define ACA_CTRLA _SFR_MEM8(0x0384) -+#define ACA_CTRLB _SFR_MEM8(0x0385) -+#define ACA_WINCTRL _SFR_MEM8(0x0386) -+#define ACA_STATUS _SFR_MEM8(0x0387) -+ -+/* AC - Analog Comparator */ -+#define ACB_AC0CTRL _SFR_MEM8(0x0390) -+#define ACB_AC1CTRL _SFR_MEM8(0x0391) -+#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -+#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -+#define ACB_CTRLA _SFR_MEM8(0x0394) -+#define ACB_CTRLB _SFR_MEM8(0x0395) -+#define ACB_WINCTRL _SFR_MEM8(0x0396) -+#define ACB_STATUS _SFR_MEM8(0x0397) -+ -+/* RTC - Real-Time Counter */ -+#define RTC_CTRL _SFR_MEM8(0x0400) -+#define RTC_STATUS _SFR_MEM8(0x0401) -+#define RTC_INTCTRL _SFR_MEM8(0x0402) -+#define RTC_INTFLAGS _SFR_MEM8(0x0403) -+#define RTC_TEMP _SFR_MEM8(0x0404) -+#define RTC_CNT _SFR_MEM16(0x0408) -+#define RTC_PER _SFR_MEM16(0x040A) -+#define RTC_COMP _SFR_MEM16(0x040C) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIE_CTRL _SFR_MEM8(0x04A0) -+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -+ -+/* USB - Universal Serial Bus */ -+#define USB_CTRLA _SFR_MEM8(0x04C0) -+#define USB_CTRLB _SFR_MEM8(0x04C1) -+#define USB_STATUS _SFR_MEM8(0x04C2) -+#define USB_ADDR _SFR_MEM8(0x04C3) -+#define USB_FIFOWP _SFR_MEM8(0x04C4) -+#define USB_FIFORP _SFR_MEM8(0x04C5) -+#define USB_EPPTR _SFR_MEM16(0x04C6) -+#define USB_INTCTRLA _SFR_MEM8(0x04C8) -+#define USB_INTCTRLB _SFR_MEM8(0x04C9) -+#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -+#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -+#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -+#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -+#define USB_CAL0 _SFR_MEM8(0x04FA) -+#define USB_CAL1 _SFR_MEM8(0x04FB) -+ -+/* PORT - I/O Ports */ -+#define PORTA_DIR _SFR_MEM8(0x0600) -+#define PORTA_DIRSET _SFR_MEM8(0x0601) -+#define PORTA_DIRCLR _SFR_MEM8(0x0602) -+#define PORTA_DIRTGL _SFR_MEM8(0x0603) -+#define PORTA_OUT _SFR_MEM8(0x0604) -+#define PORTA_OUTSET _SFR_MEM8(0x0605) -+#define PORTA_OUTCLR _SFR_MEM8(0x0606) -+#define PORTA_OUTTGL _SFR_MEM8(0x0607) -+#define PORTA_IN _SFR_MEM8(0x0608) -+#define PORTA_INTCTRL _SFR_MEM8(0x0609) -+#define PORTA_INT0MASK _SFR_MEM8(0x060A) -+#define PORTA_INT1MASK _SFR_MEM8(0x060B) -+#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_REMAP _SFR_MEM8(0x060E) -+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -+ -+/* PORT - I/O Ports */ -+#define PORTB_DIR _SFR_MEM8(0x0620) -+#define PORTB_DIRSET _SFR_MEM8(0x0621) -+#define PORTB_DIRCLR _SFR_MEM8(0x0622) -+#define PORTB_DIRTGL _SFR_MEM8(0x0623) -+#define PORTB_OUT _SFR_MEM8(0x0624) -+#define PORTB_OUTSET _SFR_MEM8(0x0625) -+#define PORTB_OUTCLR _SFR_MEM8(0x0626) -+#define PORTB_OUTTGL _SFR_MEM8(0x0627) -+#define PORTB_IN _SFR_MEM8(0x0628) -+#define PORTB_INTCTRL _SFR_MEM8(0x0629) -+#define PORTB_INT0MASK _SFR_MEM8(0x062A) -+#define PORTB_INT1MASK _SFR_MEM8(0x062B) -+#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -+#define PORTB_REMAP _SFR_MEM8(0x062E) -+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INT0MASK _SFR_MEM8(0x064A) -+#define PORTC_INT1MASK _SFR_MEM8(0x064B) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INT0MASK _SFR_MEM8(0x066A) -+#define PORTD_INT1MASK _SFR_MEM8(0x066B) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTE_DIR _SFR_MEM8(0x0680) -+#define PORTE_DIRSET _SFR_MEM8(0x0681) -+#define PORTE_DIRCLR _SFR_MEM8(0x0682) -+#define PORTE_DIRTGL _SFR_MEM8(0x0683) -+#define PORTE_OUT _SFR_MEM8(0x0684) -+#define PORTE_OUTSET _SFR_MEM8(0x0685) -+#define PORTE_OUTCLR _SFR_MEM8(0x0686) -+#define PORTE_OUTTGL _SFR_MEM8(0x0687) -+#define PORTE_IN _SFR_MEM8(0x0688) -+#define PORTE_INTCTRL _SFR_MEM8(0x0689) -+#define PORTE_INT0MASK _SFR_MEM8(0x068A) -+#define PORTE_INT1MASK _SFR_MEM8(0x068B) -+#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -+#define PORTE_REMAP _SFR_MEM8(0x068E) -+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) -+ -+/* PORT - I/O Ports */ -+#define PORTF_DIR _SFR_MEM8(0x06A0) -+#define PORTF_DIRSET _SFR_MEM8(0x06A1) -+#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -+#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -+#define PORTF_OUT _SFR_MEM8(0x06A4) -+#define PORTF_OUTSET _SFR_MEM8(0x06A5) -+#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -+#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -+#define PORTF_IN _SFR_MEM8(0x06A8) -+#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -+#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -+#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -+#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -+#define PORTF_REMAP _SFR_MEM8(0x06AE) -+#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -+#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -+#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -+#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -+#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -+#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -+#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -+#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -+#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCC0_CTRLA _SFR_MEM8(0x0800) -+#define TCC0_CTRLB _SFR_MEM8(0x0801) -+#define TCC0_CTRLC _SFR_MEM8(0x0802) -+#define TCC0_CTRLD _SFR_MEM8(0x0803) -+#define TCC0_CTRLE _SFR_MEM8(0x0804) -+#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -+#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -+#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -+#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC0_TEMP _SFR_MEM8(0x080F) -+#define TCC0_CNT _SFR_MEM16(0x0820) -+#define TCC0_PER _SFR_MEM16(0x0826) -+#define TCC0_CCA _SFR_MEM16(0x0828) -+#define TCC0_CCB _SFR_MEM16(0x082A) -+#define TCC0_CCC _SFR_MEM16(0x082C) -+#define TCC0_CCD _SFR_MEM16(0x082E) -+#define TCC0_PERBUF _SFR_MEM16(0x0836) -+#define TCC0_CCABUF _SFR_MEM16(0x0838) -+#define TCC0_CCBBUF _SFR_MEM16(0x083A) -+#define TCC0_CCCBUF _SFR_MEM16(0x083C) -+#define TCC0_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCC2_CTRLA _SFR_MEM8(0x0800) -+#define TCC2_CTRLB _SFR_MEM8(0x0801) -+#define TCC2_CTRLC _SFR_MEM8(0x0802) -+#define TCC2_CTRLE _SFR_MEM8(0x0804) -+#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC2_CTRLF _SFR_MEM8(0x0809) -+#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC2_LCNT _SFR_MEM8(0x0820) -+#define TCC2_HCNT _SFR_MEM8(0x0821) -+#define TCC2_LPER _SFR_MEM8(0x0826) -+#define TCC2_HPER _SFR_MEM8(0x0827) -+#define TCC2_LCMPA _SFR_MEM8(0x0828) -+#define TCC2_HCMPA _SFR_MEM8(0x0829) -+#define TCC2_LCMPB _SFR_MEM8(0x082A) -+#define TCC2_HCMPB _SFR_MEM8(0x082B) -+#define TCC2_LCMPC _SFR_MEM8(0x082C) -+#define TCC2_HCMPC _SFR_MEM8(0x082D) -+#define TCC2_LCMPD _SFR_MEM8(0x082E) -+#define TCC2_HCMPD _SFR_MEM8(0x082F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCC1_CTRLA _SFR_MEM8(0x0840) -+#define TCC1_CTRLB _SFR_MEM8(0x0841) -+#define TCC1_CTRLC _SFR_MEM8(0x0842) -+#define TCC1_CTRLD _SFR_MEM8(0x0843) -+#define TCC1_CTRLE _SFR_MEM8(0x0844) -+#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -+#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -+#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -+#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC1_TEMP _SFR_MEM8(0x084F) -+#define TCC1_CNT _SFR_MEM16(0x0860) -+#define TCC1_PER _SFR_MEM16(0x0866) -+#define TCC1_CCA _SFR_MEM16(0x0868) -+#define TCC1_CCB _SFR_MEM16(0x086A) -+#define TCC1_PERBUF _SFR_MEM16(0x0876) -+#define TCC1_CCABUF _SFR_MEM16(0x0878) -+#define TCC1_CCBBUF _SFR_MEM16(0x087A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXC_CTRL _SFR_MEM8(0x0880) -+#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -+#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -+#define AWEXC_STATUS _SFR_MEM8(0x0884) -+#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -+#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -+#define AWEXC_DTLS _SFR_MEM8(0x0888) -+#define AWEXC_DTHS _SFR_MEM8(0x0889) -+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x0890) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08A0) -+#define USARTC0_STATUS _SFR_MEM8(0x08A1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -+#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -+#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC1_DATA _SFR_MEM8(0x08B0) -+#define USARTC1_STATUS _SFR_MEM8(0x08B1) -+#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -+#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -+#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -+#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -+#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIC_CTRL _SFR_MEM8(0x08C0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -+#define SPIC_STATUS _SFR_MEM8(0x08C2) -+#define SPIC_DATA _SFR_MEM8(0x08C3) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCD0_CTRLA _SFR_MEM8(0x0900) -+#define TCD0_CTRLB _SFR_MEM8(0x0901) -+#define TCD0_CTRLC _SFR_MEM8(0x0902) -+#define TCD0_CTRLD _SFR_MEM8(0x0903) -+#define TCD0_CTRLE _SFR_MEM8(0x0904) -+#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -+#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -+#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -+#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -+#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD0_TEMP _SFR_MEM8(0x090F) -+#define TCD0_CNT _SFR_MEM16(0x0920) -+#define TCD0_PER _SFR_MEM16(0x0926) -+#define TCD0_CCA _SFR_MEM16(0x0928) -+#define TCD0_CCB _SFR_MEM16(0x092A) -+#define TCD0_CCC _SFR_MEM16(0x092C) -+#define TCD0_CCD _SFR_MEM16(0x092E) -+#define TCD0_PERBUF _SFR_MEM16(0x0936) -+#define TCD0_CCABUF _SFR_MEM16(0x0938) -+#define TCD0_CCBBUF _SFR_MEM16(0x093A) -+#define TCD0_CCCBUF _SFR_MEM16(0x093C) -+#define TCD0_CCDBUF _SFR_MEM16(0x093E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCD2_CTRLA _SFR_MEM8(0x0900) -+#define TCD2_CTRLB _SFR_MEM8(0x0901) -+#define TCD2_CTRLC _SFR_MEM8(0x0902) -+#define TCD2_CTRLE _SFR_MEM8(0x0904) -+#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD2_CTRLF _SFR_MEM8(0x0909) -+#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD2_LCNT _SFR_MEM8(0x0920) -+#define TCD2_HCNT _SFR_MEM8(0x0921) -+#define TCD2_LPER _SFR_MEM8(0x0926) -+#define TCD2_HPER _SFR_MEM8(0x0927) -+#define TCD2_LCMPA _SFR_MEM8(0x0928) -+#define TCD2_HCMPA _SFR_MEM8(0x0929) -+#define TCD2_LCMPB _SFR_MEM8(0x092A) -+#define TCD2_HCMPB _SFR_MEM8(0x092B) -+#define TCD2_LCMPC _SFR_MEM8(0x092C) -+#define TCD2_HCMPC _SFR_MEM8(0x092D) -+#define TCD2_LCMPD _SFR_MEM8(0x092E) -+#define TCD2_HCMPD _SFR_MEM8(0x092F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCD1_CTRLA _SFR_MEM8(0x0940) -+#define TCD1_CTRLB _SFR_MEM8(0x0941) -+#define TCD1_CTRLC _SFR_MEM8(0x0942) -+#define TCD1_CTRLD _SFR_MEM8(0x0943) -+#define TCD1_CTRLE _SFR_MEM8(0x0944) -+#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -+#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -+#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -+#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -+#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -+#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -+#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -+#define TCD1_TEMP _SFR_MEM8(0x094F) -+#define TCD1_CNT _SFR_MEM16(0x0960) -+#define TCD1_PER _SFR_MEM16(0x0966) -+#define TCD1_CCA _SFR_MEM16(0x0968) -+#define TCD1_CCB _SFR_MEM16(0x096A) -+#define TCD1_PERBUF _SFR_MEM16(0x0976) -+#define TCD1_CCABUF _SFR_MEM16(0x0978) -+#define TCD1_CCBBUF _SFR_MEM16(0x097A) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESD_CTRLA _SFR_MEM8(0x0990) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD0_DATA _SFR_MEM8(0x09A0) -+#define USARTD0_STATUS _SFR_MEM8(0x09A1) -+#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -+#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -+#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD1_DATA _SFR_MEM8(0x09B0) -+#define USARTD1_STATUS _SFR_MEM8(0x09B1) -+#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -+#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -+#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -+#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -+#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPID_CTRL _SFR_MEM8(0x09C0) -+#define SPID_INTCTRL _SFR_MEM8(0x09C1) -+#define SPID_STATUS _SFR_MEM8(0x09C2) -+#define SPID_DATA _SFR_MEM8(0x09C3) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCE0_CTRLA _SFR_MEM8(0x0A00) -+#define TCE0_CTRLB _SFR_MEM8(0x0A01) -+#define TCE0_CTRLC _SFR_MEM8(0x0A02) -+#define TCE0_CTRLD _SFR_MEM8(0x0A03) -+#define TCE0_CTRLE _SFR_MEM8(0x0A04) -+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE0_TEMP _SFR_MEM8(0x0A0F) -+#define TCE0_CNT _SFR_MEM16(0x0A20) -+#define TCE0_PER _SFR_MEM16(0x0A26) -+#define TCE0_CCA _SFR_MEM16(0x0A28) -+#define TCE0_CCB _SFR_MEM16(0x0A2A) -+#define TCE0_CCC _SFR_MEM16(0x0A2C) -+#define TCE0_CCD _SFR_MEM16(0x0A2E) -+#define TCE0_PERBUF _SFR_MEM16(0x0A36) -+#define TCE0_CCABUF _SFR_MEM16(0x0A38) -+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCE2_CTRLA _SFR_MEM8(0x0A00) -+#define TCE2_CTRLB _SFR_MEM8(0x0A01) -+#define TCE2_CTRLC _SFR_MEM8(0x0A02) -+#define TCE2_CTRLE _SFR_MEM8(0x0A04) -+#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE2_CTRLF _SFR_MEM8(0x0A09) -+#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE2_LCNT _SFR_MEM8(0x0A20) -+#define TCE2_HCNT _SFR_MEM8(0x0A21) -+#define TCE2_LPER _SFR_MEM8(0x0A26) -+#define TCE2_HPER _SFR_MEM8(0x0A27) -+#define TCE2_LCMPA _SFR_MEM8(0x0A28) -+#define TCE2_HCMPA _SFR_MEM8(0x0A29) -+#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -+#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -+#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -+#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -+#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -+#define TCE2_HCMPD _SFR_MEM8(0x0A2F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCE1_CTRLA _SFR_MEM8(0x0A40) -+#define TCE1_CTRLB _SFR_MEM8(0x0A41) -+#define TCE1_CTRLC _SFR_MEM8(0x0A42) -+#define TCE1_CTRLD _SFR_MEM8(0x0A43) -+#define TCE1_CTRLE _SFR_MEM8(0x0A44) -+#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) -+#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) -+#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) -+#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) -+#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) -+#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) -+#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) -+#define TCE1_TEMP _SFR_MEM8(0x0A4F) -+#define TCE1_CNT _SFR_MEM16(0x0A60) -+#define TCE1_PER _SFR_MEM16(0x0A66) -+#define TCE1_CCA _SFR_MEM16(0x0A68) -+#define TCE1_CCB _SFR_MEM16(0x0A6A) -+#define TCE1_PERBUF _SFR_MEM16(0x0A76) -+#define TCE1_CCABUF _SFR_MEM16(0x0A78) -+#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXE_CTRL _SFR_MEM8(0x0A80) -+#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) -+#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) -+#define AWEXE_STATUS _SFR_MEM8(0x0A84) -+#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) -+#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) -+#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) -+#define AWEXE_DTLS _SFR_MEM8(0x0A88) -+#define AWEXE_DTHS _SFR_MEM8(0x0A89) -+#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) -+#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) -+#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESE_CTRLA _SFR_MEM8(0x0A90) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE0_DATA _SFR_MEM8(0x0AA0) -+#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -+#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -+#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -+#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -+#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -+#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE1_DATA _SFR_MEM8(0x0AB0) -+#define USARTE1_STATUS _SFR_MEM8(0x0AB1) -+#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) -+#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) -+#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) -+#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) -+#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIE_CTRL _SFR_MEM8(0x0AC0) -+#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) -+#define SPIE_STATUS _SFR_MEM8(0x0AC2) -+#define SPIE_DATA _SFR_MEM8(0x0AC3) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCF0_CTRLA _SFR_MEM8(0x0B00) -+#define TCF0_CTRLB _SFR_MEM8(0x0B01) -+#define TCF0_CTRLC _SFR_MEM8(0x0B02) -+#define TCF0_CTRLD _SFR_MEM8(0x0B03) -+#define TCF0_CTRLE _SFR_MEM8(0x0B04) -+#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -+#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -+#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -+#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -+#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -+#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -+#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -+#define TCF0_TEMP _SFR_MEM8(0x0B0F) -+#define TCF0_CNT _SFR_MEM16(0x0B20) -+#define TCF0_PER _SFR_MEM16(0x0B26) -+#define TCF0_CCA _SFR_MEM16(0x0B28) -+#define TCF0_CCB _SFR_MEM16(0x0B2A) -+#define TCF0_CCC _SFR_MEM16(0x0B2C) -+#define TCF0_CCD _SFR_MEM16(0x0B2E) -+#define TCF0_PERBUF _SFR_MEM16(0x0B36) -+#define TCF0_CCABUF _SFR_MEM16(0x0B38) -+#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -+#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -+#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCF2_CTRLA _SFR_MEM8(0x0B00) -+#define TCF2_CTRLB _SFR_MEM8(0x0B01) -+#define TCF2_CTRLC _SFR_MEM8(0x0B02) -+#define TCF2_CTRLE _SFR_MEM8(0x0B04) -+#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -+#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -+#define TCF2_CTRLF _SFR_MEM8(0x0B09) -+#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -+#define TCF2_LCNT _SFR_MEM8(0x0B20) -+#define TCF2_HCNT _SFR_MEM8(0x0B21) -+#define TCF2_LPER _SFR_MEM8(0x0B26) -+#define TCF2_HPER _SFR_MEM8(0x0B27) -+#define TCF2_LCMPA _SFR_MEM8(0x0B28) -+#define TCF2_HCMPA _SFR_MEM8(0x0B29) -+#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -+#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -+#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -+#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -+#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -+#define TCF2_HCMPD _SFR_MEM8(0x0B2F) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESF_CTRLA _SFR_MEM8(0x0B90) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTF0_DATA _SFR_MEM8(0x0BA0) -+#define USARTF0_STATUS _SFR_MEM8(0x0BA1) -+#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) -+#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) -+#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) -+#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) -+#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* VPORT - Virtual Ports */ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* CLK.USBCTRL bit masks and bit positions */ -+#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -+#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -+#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -+#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -+#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -+#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -+#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -+#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ -+ -+#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -+#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -+#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ -+ -+#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_USB_bm 0x40 /* USB bit mask. */ -+#define PR_USB_bp 6 /* USB bit position. */ -+ -+#define PR_AES_bm 0x10 /* AES bit mask. */ -+#define PR_AES_bp 4 /* AES bit position. */ -+ -+#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -+#define PR_EBI_bp 3 /* External Bus Interface bit position. */ -+ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -+#define PR_DMA_bp 0 /* DMA-Controller bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -+#define PR_DAC_bp 2 /* Port A DAC bit position. */ -+ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPB bit masks and bit positions */ -+/* PR_DAC Predefined. */ -+/* PR_DAC Predefined. */ -+ -+/* PR_ADC Predefined. */ -+/* PR_ADC Predefined. */ -+ -+/* PR_AC Predefined. */ -+/* PR_AC Predefined. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -+#define PR_USART1_bp 5 /* Port C USART1 bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -+#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ -+ -+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -+ -+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ -+ -+/* PR.PRPD bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPE bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPF bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -+#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -+#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ -+ -+#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ -+ -+#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -+#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.MCUCR bit masks and bit positions */ -+#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -+#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ -+ -+/* MCU.ANAINIT bit masks and bit positions */ -+#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -+#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -+#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -+#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -+#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -+#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ -+ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -+#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ -+ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.AWEXLOCK bit masks and bit positions */ -+#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ -+#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ -+ -+#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -+#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ -+ -+#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ -+#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ -+ -+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* PORTCFG - Port Configuration */ -+/* PORTCFG.VPCTRLA bit masks and bit positions */ -+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ -+ -+/* PORTCFG.VPCTRLB bit masks and bit positions */ -+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ -+ -+/* PORTCFG.CLKEVOUT bit masks and bit positions */ -+#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ -+ -+#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -+#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -+#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -+#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -+#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -+#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ -+ -+#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -+#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ -+ -+#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -+#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ -+ -+/* PORTCFG.EBIOUT bit masks and bit positions */ -+#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ -+#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ -+#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ -+#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ -+#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ -+#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ -+ -+#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ -+#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ -+#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ -+#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ -+#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ -+#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ -+ -+/* PORTCFG.EVOUTSEL bit masks and bit positions */ -+#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -+#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -+#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -+#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -+#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -+#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -+#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -+#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ -+ -+/* AES - AES Module */ -+/* AES.CTRL bit masks and bit positions */ -+#define AES_START_bm 0x80 /* Start/Run bit mask. */ -+#define AES_START_bp 7 /* Start/Run bit position. */ -+ -+#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -+#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ -+ -+#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -+#define AES_RESET_bp 5 /* AES Software Reset bit position. */ -+ -+#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -+#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ -+ -+#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -+#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ -+ -+/* AES.STATUS bit masks and bit positions */ -+#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -+#define AES_ERROR_bp 7 /* AES Error bit position. */ -+ -+#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -+#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ -+ -+/* AES.INTCTRL bit masks and bit positions */ -+#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -+#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* DMA - DMA Controller */ -+/* DMA_CH.CTRLA bit masks and bit positions */ -+#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -+#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ -+ -+#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -+#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ -+ -+#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -+#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ -+ -+#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -+#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ -+ -+#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -+#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ -+ -+#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -+#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -+#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -+#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -+#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -+#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ -+ -+/* DMA_CH.CTRLB bit masks and bit positions */ -+#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -+#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ -+ -+#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -+#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ -+ -+#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -+#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ -+ -+#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -+#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -+#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -+#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -+#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -+#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ -+ -+#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -+#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -+#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -+#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -+#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -+#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ -+ -+/* DMA_CH.ADDRCTRL bit masks and bit positions */ -+#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -+#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -+#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -+#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -+#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -+#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ -+ -+#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -+#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -+#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -+#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -+#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -+#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ -+ -+#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -+#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -+#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -+#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -+#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -+#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ -+ -+#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -+#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -+#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -+#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -+#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -+#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ -+ -+/* DMA_CH.TRIGSRC bit masks and bit positions */ -+#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -+#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -+#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -+#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -+#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -+#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -+#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -+#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -+#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -+#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -+#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -+#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -+#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -+#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -+#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -+#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -+#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -+#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ -+ -+/* DMA.CTRL bit masks and bit positions */ -+#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -+#define DMA_ENABLE_bp 7 /* Enable bit position. */ -+ -+#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -+#define DMA_RESET_bp 6 /* Software Reset bit position. */ -+ -+#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -+#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -+#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -+#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -+#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -+#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ -+ -+#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -+#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -+#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -+#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -+#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -+#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ -+ -+/* DMA.INTFLAGS bit masks and bit positions */ -+#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ -+ -+/* DMA.STATUS bit masks and bit positions */ -+#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -+#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ -+ -+#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -+#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ -+ -+#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -+#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ -+ -+#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -+#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ -+ -+#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -+#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ -+ -+#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -+#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ -+ -+#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -+#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ -+ -+#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -+#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH4MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH5MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH6MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH7MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_QDIRM Predefined. */ -+/* EVSYS_QDIRM Predefined. */ -+ -+/* EVSYS_QDIEN Predefined. */ -+/* EVSYS_QDIEN Predefined. */ -+ -+/* EVSYS_QDEN Predefined. */ -+/* EVSYS_QDEN Predefined. */ -+ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH4CTRL bit masks and bit positions */ -+/* EVSYS_QDIRM Predefined. */ -+/* EVSYS_QDIRM Predefined. */ -+ -+/* EVSYS_QDIEN Predefined. */ -+/* EVSYS_QDIEN Predefined. */ -+ -+/* EVSYS_QDEN Predefined. */ -+/* EVSYS_QDEN Predefined. */ -+ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH5CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH6CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH7CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0x7F /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ -+ -+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ -+ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -+#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HSMODE Predefined. */ -+/* AC_HSMODE Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -+#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ -+#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -+#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -+#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -+#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -+#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -+#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -+#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -+#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -+#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -+#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ -+ -+#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -+#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -+#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -+#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -+#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -+#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -+#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -+#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -+#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -+#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -+#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -+#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -+#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -+#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -+#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ -+ -+#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -+#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ -+ -+#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -+#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ -+ -+#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -+#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ -+ -+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -+#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ -+#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ -+ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -+#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -+#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -+#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -+#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -+#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ -+ -+#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -+#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -+#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ -+ -+#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -+#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ -+ -+#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -+#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ -+ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* DAC - Digital/Analog Converter */ -+/* DAC.CTRLA bit masks and bit positions */ -+#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -+#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ -+ -+#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -+#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ -+ -+#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -+#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ -+ -+#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -+#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ -+ -+#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define DAC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* DAC.CTRLB bit masks and bit positions */ -+#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -+#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -+#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -+#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -+#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -+#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ -+ -+#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -+#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ -+ -+#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -+#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ -+ -+/* DAC.CTRLC bit masks and bit positions */ -+#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -+#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -+#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -+#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -+#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -+#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ -+ -+#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -+#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ -+ -+/* DAC.EVCTRL bit masks and bit positions */ -+#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -+#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ -+ -+#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -+#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -+#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -+#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -+#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -+#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -+#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -+#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ -+ -+/* DAC.STATUS bit masks and bit positions */ -+#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -+#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ -+ -+#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -+#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ -+ -+/* DAC.CH0GAINCAL bit masks and bit positions */ -+#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -+#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -+#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -+#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -+#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -+#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -+#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -+#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -+#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -+#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -+#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -+#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -+#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -+#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -+#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -+#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ -+ -+/* DAC.CH0OFFSETCAL bit masks and bit positions */ -+#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -+#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -+#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -+#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -+#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -+#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -+#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -+#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -+#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -+#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -+#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -+#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -+#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -+#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -+#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -+#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ -+ -+/* DAC.CH1GAINCAL bit masks and bit positions */ -+#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -+#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -+#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -+#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -+#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -+#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -+#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -+#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -+#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -+#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -+#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -+#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -+#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -+#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -+#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -+#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ -+ -+/* DAC.CH1OFFSETCAL bit masks and bit positions */ -+#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -+#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -+#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -+#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -+#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -+#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -+#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -+#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -+#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -+#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -+#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -+#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -+#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -+#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -+#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -+#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ -+ -+/* RTC - Real-Time Counter */ -+/* RTC.CTRL bit masks and bit positions */ -+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ -+ -+/* RTC.STATUS bit masks and bit positions */ -+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC.INTCTRL bit masks and bit positions */ -+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC.INTFLAGS bit masks and bit positions */ -+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* USB - USB */ -+/* USB_EP.STATUS bit masks and bit positions */ -+#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -+#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ -+ -+#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -+#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ -+ -+#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -+#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ -+ -+#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -+#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ -+ -+#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -+#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ -+ -+#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -+#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ -+ -+#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -+#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ -+ -+#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -+#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ -+ -+#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ -+ -+#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ -+ -+#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -+#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ -+ -+/* USB_EP.CTRL bit masks and bit positions */ -+#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -+#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -+#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -+#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -+#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -+#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ -+ -+#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -+#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ -+ -+#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -+#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ -+ -+#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -+#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ -+ -+#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -+#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ -+ -+#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -+#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -+#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -+#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -+#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -+#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -+#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -+#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ -+ -+/* USB_EP.CNT bit masks and bit positions */ -+#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -+#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ -+ -+/* USB.CTRLA bit masks and bit positions */ -+#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -+#define USB_ENABLE_bp 7 /* USB Enable bit position. */ -+ -+#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -+#define USB_SPEED_bp 6 /* Speed Select bit position. */ -+ -+#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -+#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ -+ -+#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -+#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ -+ -+#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -+#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -+#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -+#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -+#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -+#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -+#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -+#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -+#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -+#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ -+ -+/* USB.CTRLB bit masks and bit positions */ -+#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -+#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ -+ -+#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -+#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ -+ -+#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -+#define USB_GNACK_bp 1 /* Global NACK bit position. */ -+ -+#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -+#define USB_ATTACH_bp 0 /* Attach bit position. */ -+ -+/* USB.STATUS bit masks and bit positions */ -+#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -+#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ -+ -+#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -+#define USB_RESUME_bp 2 /* Resume bit position. */ -+ -+#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -+#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ -+ -+#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -+#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ -+ -+/* USB.ADDR bit masks and bit positions */ -+#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -+#define USB_ADDR_gp 0 /* Device Address group position. */ -+#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -+#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -+#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -+#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -+#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -+#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -+#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -+#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -+#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -+#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -+#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -+#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -+#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -+#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ -+ -+/* USB.FIFOWP bit masks and bit positions */ -+#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -+#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -+#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -+#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -+#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -+#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -+#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -+#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -+#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -+#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -+#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -+#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ -+ -+/* USB.FIFORP bit masks and bit positions */ -+#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -+#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -+#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -+#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -+#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -+#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -+#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -+#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -+#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -+#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -+#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -+#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ -+ -+/* USB.INTCTRLA bit masks and bit positions */ -+#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -+#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ -+ -+#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -+#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ -+ -+#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -+#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ -+ -+#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -+#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ -+ -+#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* USB.INTCTRLB bit masks and bit positions */ -+#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -+#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ -+ -+#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -+#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ -+ -+/* USB.INTFLAGSACLR bit masks and bit positions */ -+#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -+#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ -+ -+#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -+#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ -+ -+#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -+#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ -+ -+#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -+#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ -+ -+#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -+#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ -+ -+#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -+#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ -+ -+#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -+#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ -+ -+#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -+#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSASET bit masks and bit positions */ -+/* USB_SOFIF Predefined. */ -+/* USB_SOFIF Predefined. */ -+ -+/* USB_SUSPENDIF Predefined. */ -+/* USB_SUSPENDIF Predefined. */ -+ -+/* USB_RESUMEIF Predefined. */ -+/* USB_RESUMEIF Predefined. */ -+ -+/* USB_RSTIF Predefined. */ -+/* USB_RSTIF Predefined. */ -+ -+/* USB_CRCIF Predefined. */ -+/* USB_CRCIF Predefined. */ -+ -+/* USB_UNFIF Predefined. */ -+/* USB_UNFIF Predefined. */ -+ -+/* USB_OVFIF Predefined. */ -+/* USB_OVFIF Predefined. */ -+ -+/* USB_STALLIF Predefined. */ -+/* USB_STALLIF Predefined. */ -+ -+/* USB.INTFLAGSBCLR bit masks and bit positions */ -+#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -+#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ -+ -+#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -+#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSBSET bit masks and bit positions */ -+/* USB_TRNIF Predefined. */ -+/* USB_TRNIF Predefined. */ -+ -+/* USB_SETUPIF Predefined. */ -+/* USB_SETUPIF Predefined. */ -+ -+/* PORT - I/O Port Configuration */ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ -+ -+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -+#define PORT_SPI_bp 5 /* SPI bit position. */ -+ -+#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -+#define PORT_USART0_bp 4 /* USART0 bit position. */ -+ -+#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -+#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ -+ -+#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -+#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ -+ -+#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -+#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ -+ -+#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -+#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ -+ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC0.CTRLA bit masks and bit positions */ -+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC0.CTRLB bit masks and bit positions */ -+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ -+ -+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ -+ -+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC0.CTRLC bit masks and bit positions */ -+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ -+ -+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ -+ -+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC0.CTRLD bit masks and bit positions */ -+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC0_EVACT_gp 5 /* Event Action group position. */ -+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC0.CTRLE bit masks and bit positions */ -+#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC0.INTCTRLA bit masks and bit positions */ -+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC0.INTCTRLB bit masks and bit positions */ -+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ -+ -+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ -+ -+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC0.CTRLFCLR bit masks and bit positions */ -+#define TC0_CMD_gm 0x0C /* Command group mask. */ -+#define TC0_CMD_gp 2 /* Command group position. */ -+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC0_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC0_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC0_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC0.CTRLFSET bit masks and bit positions */ -+/* TC0_CMD Predefined. */ -+/* TC0_CMD Predefined. */ -+ -+/* TC0_LUPD Predefined. */ -+/* TC0_LUPD Predefined. */ -+ -+/* TC0_DIR Predefined. */ -+/* TC0_DIR Predefined. */ -+ -+/* TC0.CTRLGCLR bit masks and bit positions */ -+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ -+ -+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ -+ -+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC0.CTRLGSET bit masks and bit positions */ -+/* TC0_CCDBV Predefined. */ -+/* TC0_CCDBV Predefined. */ -+ -+/* TC0_CCCBV Predefined. */ -+/* TC0_CCCBV Predefined. */ -+ -+/* TC0_CCBBV Predefined. */ -+/* TC0_CCBBV Predefined. */ -+ -+/* TC0_CCABV Predefined. */ -+/* TC0_CCABV Predefined. */ -+ -+/* TC0_PERBV Predefined. */ -+/* TC0_PERBV Predefined. */ -+ -+/* TC0.INTFLAGS bit masks and bit positions */ -+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ -+ -+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ -+ -+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC1.CTRLA bit masks and bit positions */ -+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC1.CTRLB bit masks and bit positions */ -+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC1.CTRLC bit masks and bit positions */ -+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC1.CTRLD bit masks and bit positions */ -+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC1_EVACT_gp 5 /* Event Action group position. */ -+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC1.CTRLE bit masks and bit positions */ -+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ -+ -+/* TC1.INTCTRLA bit masks and bit positions */ -+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC1.INTCTRLB bit masks and bit positions */ -+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC1.CTRLFCLR bit masks and bit positions */ -+#define TC1_CMD_gm 0x0C /* Command group mask. */ -+#define TC1_CMD_gp 2 /* Command group position. */ -+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC1_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC1_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC1_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC1.CTRLFSET bit masks and bit positions */ -+/* TC1_CMD Predefined. */ -+/* TC1_CMD Predefined. */ -+ -+/* TC1_LUPD Predefined. */ -+/* TC1_LUPD Predefined. */ -+ -+/* TC1_DIR Predefined. */ -+/* TC1_DIR Predefined. */ -+ -+/* TC1.CTRLGCLR bit masks and bit positions */ -+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC1.CTRLGSET bit masks and bit positions */ -+/* TC1_CCBBV Predefined. */ -+/* TC1_CCBBV Predefined. */ -+ -+/* TC1_CCABV Predefined. */ -+/* TC1_CCABV Predefined. */ -+ -+/* TC1_PERBV Predefined. */ -+/* TC1_PERBV Predefined. */ -+ -+/* TC1.INTFLAGS bit masks and bit positions */ -+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+/* TC2.CTRLA bit masks and bit positions */ -+#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC2.CTRLB bit masks and bit positions */ -+#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -+#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ -+ -+#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -+#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ -+ -+#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -+#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ -+ -+#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -+#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ -+ -+#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -+#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ -+ -+#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -+#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ -+ -+#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -+#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ -+ -+#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -+#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ -+ -+/* TC2.CTRLC bit masks and bit positions */ -+#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -+#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ -+ -+#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -+#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ -+ -+#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -+#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ -+ -+#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -+#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ -+ -+#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -+#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ -+ -+#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -+#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ -+ -+#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -+#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ -+ -+#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -+#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ -+ -+/* TC2.CTRLE bit masks and bit positions */ -+#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC2.INTCTRLA bit masks and bit positions */ -+#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -+#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -+#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -+#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -+#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -+#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ -+ -+#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -+#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -+#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -+#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -+#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -+#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ -+ -+/* TC2.INTCTRLB bit masks and bit positions */ -+#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -+#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -+#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -+#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -+#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -+#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -+#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -+#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -+#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -+#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -+#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -+#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -+#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -+#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -+#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -+#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -+#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -+#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -+#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -+#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -+#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ -+ -+/* TC2.CTRLF bit masks and bit positions */ -+#define TC2_CMD_gm 0x0C /* Command group mask. */ -+#define TC2_CMD_gp 2 /* Command group position. */ -+#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC2_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -+#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -+#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -+#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -+#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -+#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ -+ -+/* TC2.INTFLAGS bit masks and bit positions */ -+#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -+#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ -+ -+#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -+#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ -+ -+#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -+#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ -+ -+#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -+#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ -+ -+#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ -+ -+#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ -+ -+/* AWEX - Timer/Counter Advanced Waveform Extension */ -+/* AWEX.CTRL bit masks and bit positions */ -+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ -+ -+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ -+ -+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ -+ -+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ -+ -+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ -+ -+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ -+ -+/* AWEX.FDCTRL bit masks and bit positions */ -+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ -+ -+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ -+ -+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ -+ -+/* AWEX.STATUS bit masks and bit positions */ -+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ -+ -+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ -+ -+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ -+ -+/* AWEX.STATUSSET bit masks and bit positions */ -+/* AWEX_FDF Predefined. */ -+/* AWEX_FDF Predefined. */ -+ -+/* AWEX_DTHSBUFV Predefined. */ -+/* AWEX_DTHSBUFV Predefined. */ -+ -+/* AWEX_DTLSBUFV Predefined. */ -+/* AWEX_DTLSBUFV Predefined. */ -+ -+/* HIRES - Timer/Counter High-Resolution Extension */ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -+#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -+#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -+#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -+#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -+#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -+#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -+#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -+#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -+#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -+#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -+#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -+#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -+#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -+#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -+#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -+#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -+#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -+#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ -+ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -+#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -+#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* LOCKBIT - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT0_vect_num 2 -+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -+#define PORTC_INT1_vect_num 3 -+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT0_vect_num 4 -+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -+#define PORTR_INT1_vect_num 5 -+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ -+ -+/* DMA interrupt vectors */ -+#define DMA_CH0_vect_num 6 -+#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -+#define DMA_CH1_vect_num 7 -+#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -+#define DMA_CH2_vect_num 8 -+#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -+#define DMA_CH3_vect_num 9 -+#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ -+ -+/* RTC interrupt vectors */ -+#define RTC_OVF_vect_num 10 -+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -+#define RTC_COMP_vect_num 11 -+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 12 -+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 13 -+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_OVF_vect_num 14 -+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LUNF_vect_num 14 -+#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_ERR_vect_num 15 -+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_HUNF_vect_num 15 -+#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCA_vect_num 16 -+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPA_vect_num 16 -+#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCB_vect_num 17 -+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPB_vect_num 17 -+#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCC_vect_num 18 -+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPC_vect_num 18 -+#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCD_vect_num 19 -+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPD_vect_num 19 -+#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ -+ -+/* TCC1 interrupt vectors */ -+#define TCC1_OVF_vect_num 20 -+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -+#define TCC1_ERR_vect_num 21 -+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -+#define TCC1_CCA_vect_num 22 -+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -+#define TCC1_CCB_vect_num 23 -+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 24 -+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 25 -+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 26 -+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 27 -+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ -+ -+/* USARTC1 interrupt vectors */ -+#define USARTC1_RXC_vect_num 28 -+#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -+#define USARTC1_DRE_vect_num 29 -+#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -+#define USARTC1_TXC_vect_num 30 -+#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ -+ -+/* AES interrupt vectors */ -+#define AES_INT_vect_num 31 -+#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 32 -+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -+#define NVM_SPM_vect_num 33 -+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ -+ -+/* PORTB interrupt vectors */ -+#define PORTB_INT0_vect_num 34 -+#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -+#define PORTB_INT1_vect_num 35 -+#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ -+ -+/* ACB interrupt vectors */ -+#define ACB_AC0_vect_num 36 -+#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ -+#define ACB_AC1_vect_num 37 -+#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ -+#define ACB_ACW_vect_num 38 -+#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ -+ -+/* ADCB interrupt vectors */ -+#define ADCB_CH0_vect_num 39 -+#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ -+#define ADCB_CH1_vect_num 40 -+#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ -+#define ADCB_CH2_vect_num 41 -+#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ -+#define ADCB_CH3_vect_num 42 -+#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ -+ -+/* PORTE interrupt vectors */ -+#define PORTE_INT0_vect_num 43 -+#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -+#define PORTE_INT1_vect_num 44 -+#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ -+ -+/* TWIE interrupt vectors */ -+#define TWIE_TWIS_vect_num 45 -+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -+#define TWIE_TWIM_vect_num 46 -+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_OVF_vect_num 47 -+#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LUNF_vect_num 47 -+#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_ERR_vect_num 48 -+#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_HUNF_vect_num 48 -+#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCA_vect_num 49 -+#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPA_vect_num 49 -+#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCB_vect_num 50 -+#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPB_vect_num 50 -+#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCC_vect_num 51 -+#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPC_vect_num 51 -+#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCD_vect_num 52 -+#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPD_vect_num 52 -+#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ -+ -+/* TCE1 interrupt vectors */ -+#define TCE1_OVF_vect_num 53 -+#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ -+#define TCE1_ERR_vect_num 54 -+#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ -+#define TCE1_CCA_vect_num 55 -+#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ -+#define TCE1_CCB_vect_num 56 -+#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ -+ -+/* SPIE interrupt vectors */ -+#define SPIE_INT_vect_num 57 -+#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ -+ -+/* USARTE0 interrupt vectors */ -+#define USARTE0_RXC_vect_num 58 -+#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -+#define USARTE0_DRE_vect_num 59 -+#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -+#define USARTE0_TXC_vect_num 60 -+#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ -+ -+/* USARTE1 interrupt vectors */ -+#define USARTE1_RXC_vect_num 61 -+#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ -+#define USARTE1_DRE_vect_num 62 -+#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ -+#define USARTE1_TXC_vect_num 63 -+#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT0_vect_num 64 -+#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -+#define PORTD_INT1_vect_num 65 -+#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ -+ -+/* PORTA interrupt vectors */ -+#define PORTA_INT0_vect_num 66 -+#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -+#define PORTA_INT1_vect_num 67 -+#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ -+ -+/* ACA interrupt vectors */ -+#define ACA_AC0_vect_num 68 -+#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -+#define ACA_AC1_vect_num 69 -+#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -+#define ACA_ACW_vect_num 70 -+#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ -+ -+/* ADCA interrupt vectors */ -+#define ADCA_CH0_vect_num 71 -+#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -+#define ADCA_CH1_vect_num 72 -+#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -+#define ADCA_CH2_vect_num 73 -+#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -+#define ADCA_CH3_vect_num 74 -+#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_OVF_vect_num 77 -+#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LUNF_vect_num 77 -+#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_ERR_vect_num 78 -+#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_HUNF_vect_num 78 -+#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCA_vect_num 79 -+#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPA_vect_num 79 -+#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCB_vect_num 80 -+#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPB_vect_num 80 -+#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCC_vect_num 81 -+#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPC_vect_num 81 -+#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCD_vect_num 82 -+#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPD_vect_num 82 -+#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ -+ -+/* TCD1 interrupt vectors */ -+#define TCD1_OVF_vect_num 83 -+#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -+#define TCD1_ERR_vect_num 84 -+#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -+#define TCD1_CCA_vect_num 85 -+#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -+#define TCD1_CCB_vect_num 86 -+#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ -+ -+/* SPID interrupt vectors */ -+#define SPID_INT_vect_num 87 -+#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ -+ -+/* USARTD0 interrupt vectors */ -+#define USARTD0_RXC_vect_num 88 -+#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -+#define USARTD0_DRE_vect_num 89 -+#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -+#define USARTD0_TXC_vect_num 90 -+#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ -+ -+/* USARTD1 interrupt vectors */ -+#define USARTD1_RXC_vect_num 91 -+#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -+#define USARTD1_DRE_vect_num 92 -+#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -+#define USARTD1_TXC_vect_num 93 -+#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ -+ -+/* PORTF interrupt vectors */ -+#define PORTF_INT0_vect_num 104 -+#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -+#define PORTF_INT1_vect_num 105 -+#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_OVF_vect_num 108 -+#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LUNF_vect_num 108 -+#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_ERR_vect_num 109 -+#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_HUNF_vect_num 109 -+#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCA_vect_num 110 -+#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPA_vect_num 110 -+#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCB_vect_num 111 -+#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPB_vect_num 111 -+#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCC_vect_num 112 -+#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPC_vect_num 112 -+#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCD_vect_num 113 -+#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPD_vect_num 113 -+#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ -+ -+/* USARTF0 interrupt vectors */ -+#define USARTF0_RXC_vect_num 119 -+#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ -+#define USARTF0_DRE_vect_num 120 -+#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ -+#define USARTF0_TXC_vect_num 121 -+#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ -+ -+/* USB interrupt vectors */ -+#define USB_BUSEVENT_vect_num 125 -+#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -+#define USB_TRNCOMPL_vect_num 126 -+#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (127 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (204800) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (196608) -+#define APP_SECTION_PAGE_SIZE (512) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0x2E000) -+#define APPTABLE_SECTION_SIZE (8192) -+#define APPTABLE_SECTION_PAGE_SIZE (512) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x30000) -+#define BOOT_SECTION_SIZE (8192) -+#define BOOT_SECTION_PAGE_SIZE (512) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (24576) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (2048) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (16384) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (2048) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (6) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (512) -+#define USER_SIGNATURES_PAGE_SIZE (512) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (52) -+#define PROD_SIGNATURES_PAGE_SIZE (512) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 512 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 6 -+ -+/* Fuse Byte 0 */ -+#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -+#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -+#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -+#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -+#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -+#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -+#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -+#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -+#define FUSE0_DEFAULT (0xFF) -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x97 -+#define SIGNATURE_2 0x44 -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA192A3U_H_INCLUDED */ -+ -diff --git a/include/avr/iox192c3.h b/include/avr/iox192c3.h -new file mode 100644 -index 0000000..abc3ec3 ---- /dev/null -+++ b/include/avr/iox192c3.h -@@ -0,0 +1,6216 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox192c3.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA192C3_H_INCLUDED -+#define _AVR_ATXMEGA192C3_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+VPORT - Virtual Ports -+-------------------------------------------------------------------------- -+*/ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t USBCTRL; /* USB Control Register */ -+} CLK_t; -+ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t reserved_0x02; -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t PRPD; /* Power Reduction Port D */ -+ register8_t PRPE; /* Power Reduction Port E */ -+ register8_t PRPF; /* Power Reduction Port F */ -+} PR_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+/* USB Prescaler Division Factor */ -+typedef enum CLK_USBPSDIV_enum -+{ -+ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ -+ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ -+ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ -+ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ -+ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ -+ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -+} CLK_USBPSDIV_t; -+ -+/* USB Clock Source */ -+typedef enum CLK_USBSRC_enum -+{ -+ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ -+ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -+} CLK_USBSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control Register */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+/* 2 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC2MCREF_enum -+{ -+ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC2MCREF_t; -+ -+/* 32 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC32MCREF_enum -+{ -+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -+} OSC_RC32MCREF_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t ANAINIT; /* Analog Startup Delay */ -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t AWEXLOCK; /* AWEX Lock */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORTCFG - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t VPCTRLA; /* Virtual Port Control Register A */ -+ register8_t VPCTRLB; /* Virtual Port Control Register B */ -+ register8_t CLKEVOUT; /* Clock and Event Out Register */ -+ register8_t reserved_0x05; -+ register8_t EVOUTSEL; /* Event Output Select */ -+} PORTCFG_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP02MAP_enum -+{ -+ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ -+ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ -+ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ -+ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ -+ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ -+ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ -+ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ -+ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ -+ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ -+ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ -+ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ -+ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ -+ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ -+ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ -+ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ -+ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -+} PORTCFG_VP02MAP_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP13MAP_enum -+{ -+ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ -+ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ -+ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ -+ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ -+ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ -+ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ -+ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ -+ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ -+ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ -+ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ -+ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ -+ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ -+ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ -+ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ -+ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ -+ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -+} PORTCFG_VP13MAP_t; -+ -+/* System Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ -+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ -+ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -+} PORTCFG_CLKOUT_t; -+ -+/* Peripheral Clock Output Select */ -+typedef enum PORTCFG_CLKOUTSEL_enum -+{ -+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -+} PORTCFG_CLKOUTSEL_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ -+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ -+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -+} PORTCFG_EVOUT_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+} EVSYS_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ -+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ -+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ -+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ -+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ -+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ -+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ -+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ -+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ -+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ -+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ -+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ -+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ -+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ -+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ -+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ -+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ -+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ -+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ -+ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ -+ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ -+ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ -+ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ -+ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ -+ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ -+ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ -+ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ -+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ -+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ -+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ -+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ -+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ -+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ -+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ -+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ -+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ -+ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ -+ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ -+ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ -+ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ -+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ -+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ -+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ -+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ -+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -+ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ -+ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ -+ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ -+ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ -+ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -+} EVSYS_CHMUX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ -+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ -+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ -+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ -+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} NVM_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t reserved_0x07; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+} ADC_t; -+ -+/* Current Limitation */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -+} ADC_CURRLIMIT_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+} ADC_CH_MUXNEG_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ -+ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ -+ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ -+ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC - Real-Time Counter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Real-Time Counter */ -+typedef struct RTC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary register */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ _WORDREGISTER(CNT); /* Count Register */ -+ _WORDREGISTER(PER); /* Period Register */ -+ _WORDREGISTER(COMP); /* Compare Register */ -+} RTC_t; -+ -+/* Prescaler Factor */ -+typedef enum RTC_PRESCALER_enum -+{ -+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ -+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ -+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ -+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ -+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ -+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ -+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ -+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -+} RTC_PRESCALER_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC_COMPINTLVL_enum -+{ -+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC_OVFINTLVL_enum -+{ -+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+} TWI_t; -+ -+/* SDA Hold Time */ -+typedef enum TWI_SDAHOLD_enum -+{ -+ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ -+ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ -+ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ -+ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -+} TWI_SDAHOLD_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USB - USB -+-------------------------------------------------------------------------- -+*/ -+ -+/* USB Endpoint */ -+typedef struct USB_EP_struct -+{ -+ register8_t STATUS; /* Endpoint Status */ -+ register8_t CTRL; /* Endpoint Control */ -+ _WORDREGISTER(CNT); /* USB Endpoint Counter */ -+ _WORDREGISTER(DATAPTR); /* Data Pointer */ -+ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -+} USB_EP_t; -+ -+ -+/* Universal Serial Bus */ -+typedef struct USB_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t FIFOWP; /* FIFO Write Pointer Register */ -+ register8_t FIFORP; /* FIFO Read Pointer Register */ -+ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ -+ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ -+ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ -+ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t reserved_0x20; -+ register8_t reserved_0x21; -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t CAL0; /* Calibration Byte 0 */ -+ register8_t CAL1; /* Calibration Byte 1 */ -+} USB_t; -+ -+ -+/* USB Endpoint Table */ -+typedef struct USB_EP_TABLE_struct -+{ -+ USB_EP_t EP0OUT; /* Endpoint 0 */ -+ USB_EP_t EP0IN; /* Endpoint 0 */ -+ USB_EP_t EP1OUT; /* Endpoint 1 */ -+ USB_EP_t EP1IN; /* Endpoint 1 */ -+ USB_EP_t EP2OUT; /* Endpoint 2 */ -+ USB_EP_t EP2IN; /* Endpoint 2 */ -+ USB_EP_t EP3OUT; /* Endpoint 3 */ -+ USB_EP_t EP3IN; /* Endpoint 3 */ -+ USB_EP_t EP4OUT; /* Endpoint 4 */ -+ USB_EP_t EP4IN; /* Endpoint 4 */ -+ USB_EP_t EP5OUT; /* Endpoint 5 */ -+ USB_EP_t EP5IN; /* Endpoint 5 */ -+ USB_EP_t EP6OUT; /* Endpoint 6 */ -+ USB_EP_t EP6IN; /* Endpoint 6 */ -+ USB_EP_t EP7OUT; /* Endpoint 7 */ -+ USB_EP_t EP7IN; /* Endpoint 7 */ -+ USB_EP_t EP8OUT; /* Endpoint 8 */ -+ USB_EP_t EP8IN; /* Endpoint 8 */ -+ USB_EP_t EP9OUT; /* Endpoint 9 */ -+ USB_EP_t EP9IN; /* Endpoint 9 */ -+ USB_EP_t EP10OUT; /* Endpoint 10 */ -+ USB_EP_t EP10IN; /* Endpoint 10 */ -+ USB_EP_t EP11OUT; /* Endpoint 11 */ -+ USB_EP_t EP11IN; /* Endpoint 11 */ -+ USB_EP_t EP12OUT; /* Endpoint 12 */ -+ USB_EP_t EP12IN; /* Endpoint 12 */ -+ USB_EP_t EP13OUT; /* Endpoint 13 */ -+ USB_EP_t EP13IN; /* Endpoint 13 */ -+ USB_EP_t EP14OUT; /* Endpoint 14 */ -+ USB_EP_t EP14IN; /* Endpoint 14 */ -+ USB_EP_t EP15OUT; /* Endpoint 15 */ -+ USB_EP_t EP15IN; /* Endpoint 15 */ -+ register8_t reserved_0x100; -+ register8_t reserved_0x101; -+ register8_t reserved_0x102; -+ register8_t reserved_0x103; -+ register8_t reserved_0x104; -+ register8_t reserved_0x105; -+ register8_t reserved_0x106; -+ register8_t reserved_0x107; -+ register8_t reserved_0x108; -+ register8_t reserved_0x109; -+ register8_t reserved_0x10A; -+ register8_t reserved_0x10B; -+ register8_t reserved_0x10C; -+ register8_t reserved_0x10D; -+ register8_t reserved_0x10E; -+ register8_t reserved_0x10F; -+ register8_t FRAMENUML; /* Frame Number Low Byte */ -+ register8_t FRAMENUMH; /* Frame Number High Byte */ -+} USB_EP_TABLE_t; -+ -+/* Interrupt level */ -+typedef enum USB_INTLVL_enum -+{ -+ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} USB_INTLVL_t; -+ -+/* USB Endpoint Type */ -+typedef enum USB_EP_TYPE_enum -+{ -+ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ -+ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ -+ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ -+ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -+} USB_EP_TYPE_t; -+ -+/* USB Endpoint Buffersize */ -+typedef enum USB_EP_BUFSIZE_enum -+{ -+ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ -+ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ -+ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ -+ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ -+ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ -+ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ -+ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ -+ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -+} USB_EP_BUFSIZE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - I/O Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INT0MASK; /* Port Interrupt 0 Mask */ -+ register8_t INT1MASK; /* Port Interrupt 1 Mask */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t REMAP; /* I/O Port Pin Remap Register */ -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Port Interrupt 0 Level */ -+typedef enum PORT_INT0LVL_enum -+{ -+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INT0LVL_t; -+ -+/* Port Interrupt 1 Level */ -+typedef enum PORT_INT1LVL_enum -+{ -+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ -+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ -+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -+} PORT_INT1LVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 0 */ -+typedef struct TC0_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC0_t; -+ -+ -+/* 16-bit Timer/Counter 1 */ -+typedef struct TC1_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+} TC1_t; -+ -+/* Clock Selection */ -+typedef enum TC_CLKSEL_enum -+{ -+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_CLKSEL_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC_WGMODE_enum -+{ -+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC_WGMODE_t; -+ -+/* Byte Mode */ -+typedef enum TC_BYTEM_enum -+{ -+ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ -+ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -+} TC_BYTEM_t; -+ -+/* Event Action */ -+typedef enum TC_EVACT_enum -+{ -+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ -+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ -+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ -+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ -+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ -+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC_EVSEL_enum -+{ -+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_EVSEL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC_ERRINTLVL_enum -+{ -+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC_OVFINTLVL_enum -+{ -+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_OVFINTLVL_t; -+ -+/* Compare or Capture D Interrupt Level */ -+typedef enum TC_CCDINTLVL_enum -+{ -+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC_CCDINTLVL_t; -+ -+/* Compare or Capture C Interrupt Level */ -+typedef enum TC_CCCINTLVL_enum -+{ -+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC_CCCINTLVL_t; -+ -+/* Compare or Capture B Interrupt Level */ -+typedef enum TC_CCBINTLVL_enum -+{ -+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_CCBINTLVL_t; -+ -+/* Compare or Capture A Interrupt Level */ -+typedef enum TC_CCAINTLVL_enum -+{ -+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_CCAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC_CMD_enum -+{ -+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC2 - 16-bit Timer/Counter type 2 -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter type 2 */ -+typedef struct TC2_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t reserved_0x03; -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t reserved_0x08; -+ register8_t CTRLF; /* Control Register F */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t LCNT; /* Low Byte Count */ -+ register8_t HCNT; /* High Byte Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t LPER; /* Low Byte Period */ -+ register8_t HPER; /* High Byte Period */ -+ register8_t LCMPA; /* Low Byte Compare A */ -+ register8_t HCMPA; /* High Byte Compare A */ -+ register8_t LCMPB; /* Low Byte Compare B */ -+ register8_t HCMPB; /* High Byte Compare B */ -+ register8_t LCMPC; /* Low Byte Compare C */ -+ register8_t HCMPC; /* High Byte Compare C */ -+ register8_t LCMPD; /* Low Byte Compare D */ -+ register8_t HCMPD; /* High Byte Compare D */ -+} TC2_t; -+ -+/* Clock Selection */ -+typedef enum TC2_CLKSEL_enum -+{ -+ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC2_CLKSEL_t; -+ -+/* Byte Mode */ -+typedef enum TC2_BYTEM_enum -+{ -+ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ -+ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -+} TC2_BYTEM_t; -+ -+/* High Byte Underflow Interrupt Level */ -+typedef enum TC2_HUNFINTLVL_enum -+{ -+ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_HUNFINTLVL_t; -+ -+/* Low Byte Underflow Interrupt Level */ -+typedef enum TC2_LUNFINTLVL_enum -+{ -+ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LUNFINTLVL_t; -+ -+/* Low Byte Compare D Interrupt Level */ -+typedef enum TC2_LCMPDINTLVL_enum -+{ -+ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC2_LCMPDINTLVL_t; -+ -+/* Low Byte Compare C Interrupt Level */ -+typedef enum TC2_LCMPCINTLVL_enum -+{ -+ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC2_LCMPCINTLVL_t; -+ -+/* Low Byte Compare B Interrupt Level */ -+typedef enum TC2_LCMPBINTLVL_enum -+{ -+ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_LCMPBINTLVL_t; -+ -+/* Low Byte Compare A Interrupt Level */ -+typedef enum TC2_LCMPAINTLVL_enum -+{ -+ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LCMPAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMD_enum -+{ -+ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC2_CMD_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMDEN_enum -+{ -+ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ -+ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ -+ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -+} TC2_CMDEN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AWEX - Timer/Counter Advanced Waveform Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Advanced Waveform Extension */ -+typedef struct AWEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t FDEMASK; /* Fault Detection Event Mask */ -+ register8_t FDCTRL; /* Fault Detection Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t STATUSSET; /* Status Set Register */ -+ register8_t DTBOTH; /* Dead Time Both Sides */ -+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ -+ register8_t DTLS; /* Dead Time Low Side */ -+ register8_t DTHS; /* Dead Time High Side */ -+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ -+ register8_t DTHSBUF; /* Dead Time High Side Buffer */ -+ register8_t OUTOVEN; /* Output Override Enable */ -+} AWEX_t; -+ -+/* Fault Detect Action */ -+typedef enum AWEX_FDACT_enum -+{ -+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ -+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -+} AWEX_FDACT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+HIRES - Timer/Counter High-Resolution Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register */ -+} HIRES_t; -+ -+/* High Resolution Enable */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ -+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+} IRDA_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t reserved_0x00; -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+} NVM_FUSES_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* Timer Oscillator pin location */ -+typedef enum TOSCSEL_enum -+{ -+ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ -+ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -+} TOSCSEL_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -+} BOD_t; -+ -+/* BOD operation */ -+typedef enum BODACT_enum -+{ -+ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BODACT_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WDP_enum -+{ -+ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ -+ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ -+ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ -+ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ -+ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ -+ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ -+ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ -+ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ -+ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ -+ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ -+ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -+} WDP_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LOCKBIT - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ -+ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t USBCAL0; /* USB Calibration Byte 0 */ -+ register8_t USBCAL1; /* USB Calibration Byte 1 */ -+ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ -+ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+} NVM_PROD_SIGNATURES_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -+#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -+#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -+#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -+#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -+#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -+#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -+#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -+#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -+#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -+#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -+#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -+#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+#define CLK_USBCTRL _SFR_MEM8(0x0044) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* DFLL - DFLL */ -+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -+#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -+#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPD _SFR_MEM8(0x0074) -+#define PR_PRPE _SFR_MEM8(0x0075) -+#define PR_PRPF _SFR_MEM8(0x0076) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_ANAINIT _SFR_MEM8(0x0097) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_AWEXLOCK _SFR_MEM8(0x0099) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCA_CTRLA _SFR_MEM8(0x0200) -+#define ADCA_CTRLB _SFR_MEM8(0x0201) -+#define ADCA_REFCTRL _SFR_MEM8(0x0202) -+#define ADCA_EVCTRL _SFR_MEM8(0x0203) -+#define ADCA_PRESCALER _SFR_MEM8(0x0204) -+#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -+#define ADCA_TEMP _SFR_MEM8(0x0207) -+#define ADCA_CAL _SFR_MEM16(0x020C) -+#define ADCA_CH0RES _SFR_MEM16(0x0210) -+#define ADCA_CMP _SFR_MEM16(0x0218) -+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -+#define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -+ -+/* AC - Analog Comparator */ -+#define ACA_AC0CTRL _SFR_MEM8(0x0380) -+#define ACA_AC1CTRL _SFR_MEM8(0x0381) -+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -+#define ACA_CTRLA _SFR_MEM8(0x0384) -+#define ACA_CTRLB _SFR_MEM8(0x0385) -+#define ACA_WINCTRL _SFR_MEM8(0x0386) -+#define ACA_STATUS _SFR_MEM8(0x0387) -+ -+/* RTC - Real-Time Counter */ -+#define RTC_CTRL _SFR_MEM8(0x0400) -+#define RTC_STATUS _SFR_MEM8(0x0401) -+#define RTC_INTCTRL _SFR_MEM8(0x0402) -+#define RTC_INTFLAGS _SFR_MEM8(0x0403) -+#define RTC_TEMP _SFR_MEM8(0x0404) -+#define RTC_CNT _SFR_MEM16(0x0408) -+#define RTC_PER _SFR_MEM16(0x040A) -+#define RTC_COMP _SFR_MEM16(0x040C) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIE_CTRL _SFR_MEM8(0x04A0) -+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -+ -+/* USB - Universal Serial Bus */ -+#define USB_CTRLA _SFR_MEM8(0x04C0) -+#define USB_CTRLB _SFR_MEM8(0x04C1) -+#define USB_STATUS _SFR_MEM8(0x04C2) -+#define USB_ADDR _SFR_MEM8(0x04C3) -+#define USB_FIFOWP _SFR_MEM8(0x04C4) -+#define USB_FIFORP _SFR_MEM8(0x04C5) -+#define USB_EPPTR _SFR_MEM16(0x04C6) -+#define USB_INTCTRLA _SFR_MEM8(0x04C8) -+#define USB_INTCTRLB _SFR_MEM8(0x04C9) -+#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -+#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -+#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -+#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -+#define USB_CAL0 _SFR_MEM8(0x04FA) -+#define USB_CAL1 _SFR_MEM8(0x04FB) -+ -+/* PORT - I/O Ports */ -+#define PORTA_DIR _SFR_MEM8(0x0600) -+#define PORTA_DIRSET _SFR_MEM8(0x0601) -+#define PORTA_DIRCLR _SFR_MEM8(0x0602) -+#define PORTA_DIRTGL _SFR_MEM8(0x0603) -+#define PORTA_OUT _SFR_MEM8(0x0604) -+#define PORTA_OUTSET _SFR_MEM8(0x0605) -+#define PORTA_OUTCLR _SFR_MEM8(0x0606) -+#define PORTA_OUTTGL _SFR_MEM8(0x0607) -+#define PORTA_IN _SFR_MEM8(0x0608) -+#define PORTA_INTCTRL _SFR_MEM8(0x0609) -+#define PORTA_INT0MASK _SFR_MEM8(0x060A) -+#define PORTA_INT1MASK _SFR_MEM8(0x060B) -+#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_REMAP _SFR_MEM8(0x060E) -+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -+ -+/* PORT - I/O Ports */ -+#define PORTB_DIR _SFR_MEM8(0x0620) -+#define PORTB_DIRSET _SFR_MEM8(0x0621) -+#define PORTB_DIRCLR _SFR_MEM8(0x0622) -+#define PORTB_DIRTGL _SFR_MEM8(0x0623) -+#define PORTB_OUT _SFR_MEM8(0x0624) -+#define PORTB_OUTSET _SFR_MEM8(0x0625) -+#define PORTB_OUTCLR _SFR_MEM8(0x0626) -+#define PORTB_OUTTGL _SFR_MEM8(0x0627) -+#define PORTB_IN _SFR_MEM8(0x0628) -+#define PORTB_INTCTRL _SFR_MEM8(0x0629) -+#define PORTB_INT0MASK _SFR_MEM8(0x062A) -+#define PORTB_INT1MASK _SFR_MEM8(0x062B) -+#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -+#define PORTB_REMAP _SFR_MEM8(0x062E) -+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INT0MASK _SFR_MEM8(0x064A) -+#define PORTC_INT1MASK _SFR_MEM8(0x064B) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INT0MASK _SFR_MEM8(0x066A) -+#define PORTD_INT1MASK _SFR_MEM8(0x066B) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTE_DIR _SFR_MEM8(0x0680) -+#define PORTE_DIRSET _SFR_MEM8(0x0681) -+#define PORTE_DIRCLR _SFR_MEM8(0x0682) -+#define PORTE_DIRTGL _SFR_MEM8(0x0683) -+#define PORTE_OUT _SFR_MEM8(0x0684) -+#define PORTE_OUTSET _SFR_MEM8(0x0685) -+#define PORTE_OUTCLR _SFR_MEM8(0x0686) -+#define PORTE_OUTTGL _SFR_MEM8(0x0687) -+#define PORTE_IN _SFR_MEM8(0x0688) -+#define PORTE_INTCTRL _SFR_MEM8(0x0689) -+#define PORTE_INT0MASK _SFR_MEM8(0x068A) -+#define PORTE_INT1MASK _SFR_MEM8(0x068B) -+#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -+#define PORTE_REMAP _SFR_MEM8(0x068E) -+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) -+ -+/* PORT - I/O Ports */ -+#define PORTF_DIR _SFR_MEM8(0x06A0) -+#define PORTF_DIRSET _SFR_MEM8(0x06A1) -+#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -+#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -+#define PORTF_OUT _SFR_MEM8(0x06A4) -+#define PORTF_OUTSET _SFR_MEM8(0x06A5) -+#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -+#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -+#define PORTF_IN _SFR_MEM8(0x06A8) -+#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -+#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -+#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -+#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -+#define PORTF_REMAP _SFR_MEM8(0x06AE) -+#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -+#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -+#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -+#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -+#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -+#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -+#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -+#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -+#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCC0_CTRLA _SFR_MEM8(0x0800) -+#define TCC0_CTRLB _SFR_MEM8(0x0801) -+#define TCC0_CTRLC _SFR_MEM8(0x0802) -+#define TCC0_CTRLD _SFR_MEM8(0x0803) -+#define TCC0_CTRLE _SFR_MEM8(0x0804) -+#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -+#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -+#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -+#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC0_TEMP _SFR_MEM8(0x080F) -+#define TCC0_CNT _SFR_MEM16(0x0820) -+#define TCC0_PER _SFR_MEM16(0x0826) -+#define TCC0_CCA _SFR_MEM16(0x0828) -+#define TCC0_CCB _SFR_MEM16(0x082A) -+#define TCC0_CCC _SFR_MEM16(0x082C) -+#define TCC0_CCD _SFR_MEM16(0x082E) -+#define TCC0_PERBUF _SFR_MEM16(0x0836) -+#define TCC0_CCABUF _SFR_MEM16(0x0838) -+#define TCC0_CCBBUF _SFR_MEM16(0x083A) -+#define TCC0_CCCBUF _SFR_MEM16(0x083C) -+#define TCC0_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCC2_CTRLA _SFR_MEM8(0x0800) -+#define TCC2_CTRLB _SFR_MEM8(0x0801) -+#define TCC2_CTRLC _SFR_MEM8(0x0802) -+#define TCC2_CTRLE _SFR_MEM8(0x0804) -+#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC2_CTRLF _SFR_MEM8(0x0809) -+#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC2_LCNT _SFR_MEM8(0x0820) -+#define TCC2_HCNT _SFR_MEM8(0x0821) -+#define TCC2_LPER _SFR_MEM8(0x0826) -+#define TCC2_HPER _SFR_MEM8(0x0827) -+#define TCC2_LCMPA _SFR_MEM8(0x0828) -+#define TCC2_HCMPA _SFR_MEM8(0x0829) -+#define TCC2_LCMPB _SFR_MEM8(0x082A) -+#define TCC2_HCMPB _SFR_MEM8(0x082B) -+#define TCC2_LCMPC _SFR_MEM8(0x082C) -+#define TCC2_HCMPC _SFR_MEM8(0x082D) -+#define TCC2_LCMPD _SFR_MEM8(0x082E) -+#define TCC2_HCMPD _SFR_MEM8(0x082F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCC1_CTRLA _SFR_MEM8(0x0840) -+#define TCC1_CTRLB _SFR_MEM8(0x0841) -+#define TCC1_CTRLC _SFR_MEM8(0x0842) -+#define TCC1_CTRLD _SFR_MEM8(0x0843) -+#define TCC1_CTRLE _SFR_MEM8(0x0844) -+#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -+#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -+#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -+#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC1_TEMP _SFR_MEM8(0x084F) -+#define TCC1_CNT _SFR_MEM16(0x0860) -+#define TCC1_PER _SFR_MEM16(0x0866) -+#define TCC1_CCA _SFR_MEM16(0x0868) -+#define TCC1_CCB _SFR_MEM16(0x086A) -+#define TCC1_PERBUF _SFR_MEM16(0x0876) -+#define TCC1_CCABUF _SFR_MEM16(0x0878) -+#define TCC1_CCBBUF _SFR_MEM16(0x087A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXC_CTRL _SFR_MEM8(0x0880) -+#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -+#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -+#define AWEXC_STATUS _SFR_MEM8(0x0884) -+#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -+#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -+#define AWEXC_DTLS _SFR_MEM8(0x0888) -+#define AWEXC_DTHS _SFR_MEM8(0x0889) -+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x0890) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08A0) -+#define USARTC0_STATUS _SFR_MEM8(0x08A1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -+#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -+#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIC_CTRL _SFR_MEM8(0x08C0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -+#define SPIC_STATUS _SFR_MEM8(0x08C2) -+#define SPIC_DATA _SFR_MEM8(0x08C3) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCD0_CTRLA _SFR_MEM8(0x0900) -+#define TCD0_CTRLB _SFR_MEM8(0x0901) -+#define TCD0_CTRLC _SFR_MEM8(0x0902) -+#define TCD0_CTRLD _SFR_MEM8(0x0903) -+#define TCD0_CTRLE _SFR_MEM8(0x0904) -+#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -+#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -+#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -+#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -+#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD0_TEMP _SFR_MEM8(0x090F) -+#define TCD0_CNT _SFR_MEM16(0x0920) -+#define TCD0_PER _SFR_MEM16(0x0926) -+#define TCD0_CCA _SFR_MEM16(0x0928) -+#define TCD0_CCB _SFR_MEM16(0x092A) -+#define TCD0_CCC _SFR_MEM16(0x092C) -+#define TCD0_CCD _SFR_MEM16(0x092E) -+#define TCD0_PERBUF _SFR_MEM16(0x0936) -+#define TCD0_CCABUF _SFR_MEM16(0x0938) -+#define TCD0_CCBBUF _SFR_MEM16(0x093A) -+#define TCD0_CCCBUF _SFR_MEM16(0x093C) -+#define TCD0_CCDBUF _SFR_MEM16(0x093E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCD2_CTRLA _SFR_MEM8(0x0900) -+#define TCD2_CTRLB _SFR_MEM8(0x0901) -+#define TCD2_CTRLC _SFR_MEM8(0x0902) -+#define TCD2_CTRLE _SFR_MEM8(0x0904) -+#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD2_CTRLF _SFR_MEM8(0x0909) -+#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD2_LCNT _SFR_MEM8(0x0920) -+#define TCD2_HCNT _SFR_MEM8(0x0921) -+#define TCD2_LPER _SFR_MEM8(0x0926) -+#define TCD2_HPER _SFR_MEM8(0x0927) -+#define TCD2_LCMPA _SFR_MEM8(0x0928) -+#define TCD2_HCMPA _SFR_MEM8(0x0929) -+#define TCD2_LCMPB _SFR_MEM8(0x092A) -+#define TCD2_HCMPB _SFR_MEM8(0x092B) -+#define TCD2_LCMPC _SFR_MEM8(0x092C) -+#define TCD2_HCMPC _SFR_MEM8(0x092D) -+#define TCD2_LCMPD _SFR_MEM8(0x092E) -+#define TCD2_HCMPD _SFR_MEM8(0x092F) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD0_DATA _SFR_MEM8(0x09A0) -+#define USARTD0_STATUS _SFR_MEM8(0x09A1) -+#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -+#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -+#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPID_CTRL _SFR_MEM8(0x09C0) -+#define SPID_INTCTRL _SFR_MEM8(0x09C1) -+#define SPID_STATUS _SFR_MEM8(0x09C2) -+#define SPID_DATA _SFR_MEM8(0x09C3) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCE0_CTRLA _SFR_MEM8(0x0A00) -+#define TCE0_CTRLB _SFR_MEM8(0x0A01) -+#define TCE0_CTRLC _SFR_MEM8(0x0A02) -+#define TCE0_CTRLD _SFR_MEM8(0x0A03) -+#define TCE0_CTRLE _SFR_MEM8(0x0A04) -+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE0_TEMP _SFR_MEM8(0x0A0F) -+#define TCE0_CNT _SFR_MEM16(0x0A20) -+#define TCE0_PER _SFR_MEM16(0x0A26) -+#define TCE0_CCA _SFR_MEM16(0x0A28) -+#define TCE0_CCB _SFR_MEM16(0x0A2A) -+#define TCE0_CCC _SFR_MEM16(0x0A2C) -+#define TCE0_CCD _SFR_MEM16(0x0A2E) -+#define TCE0_PERBUF _SFR_MEM16(0x0A36) -+#define TCE0_CCABUF _SFR_MEM16(0x0A38) -+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCE2_CTRLA _SFR_MEM8(0x0A00) -+#define TCE2_CTRLB _SFR_MEM8(0x0A01) -+#define TCE2_CTRLC _SFR_MEM8(0x0A02) -+#define TCE2_CTRLE _SFR_MEM8(0x0A04) -+#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE2_CTRLF _SFR_MEM8(0x0A09) -+#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE2_LCNT _SFR_MEM8(0x0A20) -+#define TCE2_HCNT _SFR_MEM8(0x0A21) -+#define TCE2_LPER _SFR_MEM8(0x0A26) -+#define TCE2_HPER _SFR_MEM8(0x0A27) -+#define TCE2_LCMPA _SFR_MEM8(0x0A28) -+#define TCE2_HCMPA _SFR_MEM8(0x0A29) -+#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -+#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -+#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -+#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -+#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -+#define TCE2_HCMPD _SFR_MEM8(0x0A2F) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE0_DATA _SFR_MEM8(0x0AA0) -+#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -+#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -+#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -+#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -+#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -+#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCF0_CTRLA _SFR_MEM8(0x0B00) -+#define TCF0_CTRLB _SFR_MEM8(0x0B01) -+#define TCF0_CTRLC _SFR_MEM8(0x0B02) -+#define TCF0_CTRLD _SFR_MEM8(0x0B03) -+#define TCF0_CTRLE _SFR_MEM8(0x0B04) -+#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -+#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -+#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -+#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -+#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -+#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -+#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -+#define TCF0_TEMP _SFR_MEM8(0x0B0F) -+#define TCF0_CNT _SFR_MEM16(0x0B20) -+#define TCF0_PER _SFR_MEM16(0x0B26) -+#define TCF0_CCA _SFR_MEM16(0x0B28) -+#define TCF0_CCB _SFR_MEM16(0x0B2A) -+#define TCF0_CCC _SFR_MEM16(0x0B2C) -+#define TCF0_CCD _SFR_MEM16(0x0B2E) -+#define TCF0_PERBUF _SFR_MEM16(0x0B36) -+#define TCF0_CCABUF _SFR_MEM16(0x0B38) -+#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -+#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -+#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCF2_CTRLA _SFR_MEM8(0x0B00) -+#define TCF2_CTRLB _SFR_MEM8(0x0B01) -+#define TCF2_CTRLC _SFR_MEM8(0x0B02) -+#define TCF2_CTRLE _SFR_MEM8(0x0B04) -+#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -+#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -+#define TCF2_CTRLF _SFR_MEM8(0x0B09) -+#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -+#define TCF2_LCNT _SFR_MEM8(0x0B20) -+#define TCF2_HCNT _SFR_MEM8(0x0B21) -+#define TCF2_LPER _SFR_MEM8(0x0B26) -+#define TCF2_HPER _SFR_MEM8(0x0B27) -+#define TCF2_LCMPA _SFR_MEM8(0x0B28) -+#define TCF2_HCMPA _SFR_MEM8(0x0B29) -+#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -+#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -+#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -+#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -+#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -+#define TCF2_HCMPD _SFR_MEM8(0x0B2F) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* VPORT - Virtual Ports */ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* CLK.USBCTRL bit masks and bit positions */ -+#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -+#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -+#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -+#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -+#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -+#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -+#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -+#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ -+ -+#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -+#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -+#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ -+ -+#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_USB_bm 0x40 /* USB bit mask. */ -+#define PR_USB_bp 6 /* USB bit position. */ -+ -+#define PR_AES_bm 0x10 /* AES bit mask. */ -+#define PR_AES_bp 4 /* AES bit position. */ -+ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -+#define PR_DMA_bp 0 /* DMA-Controller bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -+#define PR_USART1_bp 5 /* Port C USART1 bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -+#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ -+ -+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -+ -+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ -+ -+/* PR.PRPD bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPE bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPF bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -+#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -+#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ -+ -+#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ -+ -+#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -+#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.ANAINIT bit masks and bit positions */ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.AWEXLOCK bit masks and bit positions */ -+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* PORTCFG - Port Configuration */ -+/* PORTCFG.VPCTRLA bit masks and bit positions */ -+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ -+ -+/* PORTCFG.VPCTRLB bit masks and bit positions */ -+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ -+ -+/* PORTCFG.CLKEVOUT bit masks and bit positions */ -+#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ -+ -+#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -+#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -+#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -+#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -+#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -+#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ -+ -+#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -+#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ -+ -+#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -+#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ -+ -+/* PORTCFG.EVOUTSEL bit masks and bit positions */ -+#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -+#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -+#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -+#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -+#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -+#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -+#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -+#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0x7F /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ -+ -+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ -+ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -+#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -+#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -+#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -+#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -+#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -+#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -+#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -+#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -+#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ -+ -+#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -+#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -+#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -+#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -+#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -+#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -+#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -+#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -+#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -+#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -+#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* RTC - Real-Time Counter */ -+/* RTC.CTRL bit masks and bit positions */ -+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ -+ -+/* RTC.STATUS bit masks and bit positions */ -+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC.INTCTRL bit masks and bit positions */ -+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC.INTFLAGS bit masks and bit positions */ -+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* USB - USB */ -+/* USB_EP.STATUS bit masks and bit positions */ -+#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -+#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ -+ -+#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -+#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ -+ -+#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -+#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ -+ -+#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -+#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ -+ -+#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -+#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ -+ -+#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -+#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ -+ -+#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -+#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ -+ -+#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -+#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ -+ -+#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ -+ -+#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ -+ -+#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -+#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ -+ -+/* USB_EP.CTRL bit masks and bit positions */ -+#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -+#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -+#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -+#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -+#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -+#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ -+ -+#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -+#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ -+ -+#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -+#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ -+ -+#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -+#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ -+ -+#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -+#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ -+ -+#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -+#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -+#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -+#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -+#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -+#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -+#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -+#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ -+ -+/* USB_EP.CNT bit masks and bit positions */ -+#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -+#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ -+ -+/* USB.CTRLA bit masks and bit positions */ -+#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -+#define USB_ENABLE_bp 7 /* USB Enable bit position. */ -+ -+#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -+#define USB_SPEED_bp 6 /* Speed Select bit position. */ -+ -+#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -+#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ -+ -+#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -+#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ -+ -+#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -+#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -+#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -+#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -+#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -+#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -+#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -+#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -+#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -+#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ -+ -+/* USB.CTRLB bit masks and bit positions */ -+#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -+#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ -+ -+#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -+#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ -+ -+#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -+#define USB_GNACK_bp 1 /* Global NACK bit position. */ -+ -+#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -+#define USB_ATTACH_bp 0 /* Attach bit position. */ -+ -+/* USB.STATUS bit masks and bit positions */ -+#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -+#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ -+ -+#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -+#define USB_RESUME_bp 2 /* Resume bit position. */ -+ -+#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -+#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ -+ -+#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -+#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ -+ -+/* USB.ADDR bit masks and bit positions */ -+#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -+#define USB_ADDR_gp 0 /* Device Address group position. */ -+#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -+#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -+#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -+#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -+#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -+#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -+#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -+#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -+#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -+#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -+#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -+#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -+#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -+#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ -+ -+/* USB.FIFOWP bit masks and bit positions */ -+#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -+#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -+#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -+#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -+#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -+#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -+#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -+#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -+#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -+#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -+#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -+#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ -+ -+/* USB.FIFORP bit masks and bit positions */ -+#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -+#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -+#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -+#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -+#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -+#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -+#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -+#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -+#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -+#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -+#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -+#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ -+ -+/* USB.INTCTRLA bit masks and bit positions */ -+#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -+#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ -+ -+#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -+#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ -+ -+#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -+#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ -+ -+#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -+#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ -+ -+#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* USB.INTCTRLB bit masks and bit positions */ -+#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -+#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ -+ -+#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -+#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ -+ -+/* USB.INTFLAGSACLR bit masks and bit positions */ -+#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -+#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ -+ -+#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -+#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ -+ -+#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -+#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ -+ -+#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -+#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ -+ -+#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -+#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ -+ -+#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -+#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ -+ -+#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -+#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ -+ -+#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -+#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSASET bit masks and bit positions */ -+/* USB_SOFIF Predefined. */ -+/* USB_SOFIF Predefined. */ -+ -+/* USB_SUSPENDIF Predefined. */ -+/* USB_SUSPENDIF Predefined. */ -+ -+/* USB_RESUMEIF Predefined. */ -+/* USB_RESUMEIF Predefined. */ -+ -+/* USB_RSTIF Predefined. */ -+/* USB_RSTIF Predefined. */ -+ -+/* USB_CRCIF Predefined. */ -+/* USB_CRCIF Predefined. */ -+ -+/* USB_UNFIF Predefined. */ -+/* USB_UNFIF Predefined. */ -+ -+/* USB_OVFIF Predefined. */ -+/* USB_OVFIF Predefined. */ -+ -+/* USB_STALLIF Predefined. */ -+/* USB_STALLIF Predefined. */ -+ -+/* USB.INTFLAGSBCLR bit masks and bit positions */ -+#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -+#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ -+ -+#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -+#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSBSET bit masks and bit positions */ -+/* USB_TRNIF Predefined. */ -+/* USB_TRNIF Predefined. */ -+ -+/* USB_SETUPIF Predefined. */ -+/* USB_SETUPIF Predefined. */ -+ -+/* PORT - I/O Port Configuration */ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ -+ -+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -+#define PORT_SPI_bp 5 /* SPI bit position. */ -+ -+#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -+#define PORT_USART0_bp 4 /* USART0 bit position. */ -+ -+#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -+#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ -+ -+#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -+#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ -+ -+#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -+#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ -+ -+#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -+#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ -+ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC0.CTRLA bit masks and bit positions */ -+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC0.CTRLB bit masks and bit positions */ -+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ -+ -+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ -+ -+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC0.CTRLC bit masks and bit positions */ -+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ -+ -+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ -+ -+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC0.CTRLD bit masks and bit positions */ -+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC0_EVACT_gp 5 /* Event Action group position. */ -+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC0.CTRLE bit masks and bit positions */ -+#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC0.INTCTRLA bit masks and bit positions */ -+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC0.INTCTRLB bit masks and bit positions */ -+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ -+ -+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ -+ -+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC0.CTRLFCLR bit masks and bit positions */ -+#define TC0_CMD_gm 0x0C /* Command group mask. */ -+#define TC0_CMD_gp 2 /* Command group position. */ -+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC0_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC0_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC0_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC0.CTRLFSET bit masks and bit positions */ -+/* TC0_CMD Predefined. */ -+/* TC0_CMD Predefined. */ -+ -+/* TC0_LUPD Predefined. */ -+/* TC0_LUPD Predefined. */ -+ -+/* TC0_DIR Predefined. */ -+/* TC0_DIR Predefined. */ -+ -+/* TC0.CTRLGCLR bit masks and bit positions */ -+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ -+ -+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ -+ -+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC0.CTRLGSET bit masks and bit positions */ -+/* TC0_CCDBV Predefined. */ -+/* TC0_CCDBV Predefined. */ -+ -+/* TC0_CCCBV Predefined. */ -+/* TC0_CCCBV Predefined. */ -+ -+/* TC0_CCBBV Predefined. */ -+/* TC0_CCBBV Predefined. */ -+ -+/* TC0_CCABV Predefined. */ -+/* TC0_CCABV Predefined. */ -+ -+/* TC0_PERBV Predefined. */ -+/* TC0_PERBV Predefined. */ -+ -+/* TC0.INTFLAGS bit masks and bit positions */ -+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ -+ -+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ -+ -+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC1.CTRLA bit masks and bit positions */ -+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC1.CTRLB bit masks and bit positions */ -+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC1.CTRLC bit masks and bit positions */ -+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC1.CTRLD bit masks and bit positions */ -+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC1_EVACT_gp 5 /* Event Action group position. */ -+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC1.CTRLE bit masks and bit positions */ -+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ -+ -+/* TC1.INTCTRLA bit masks and bit positions */ -+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC1.INTCTRLB bit masks and bit positions */ -+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC1.CTRLFCLR bit masks and bit positions */ -+#define TC1_CMD_gm 0x0C /* Command group mask. */ -+#define TC1_CMD_gp 2 /* Command group position. */ -+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC1_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC1_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC1_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC1.CTRLFSET bit masks and bit positions */ -+/* TC1_CMD Predefined. */ -+/* TC1_CMD Predefined. */ -+ -+/* TC1_LUPD Predefined. */ -+/* TC1_LUPD Predefined. */ -+ -+/* TC1_DIR Predefined. */ -+/* TC1_DIR Predefined. */ -+ -+/* TC1.CTRLGCLR bit masks and bit positions */ -+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC1.CTRLGSET bit masks and bit positions */ -+/* TC1_CCBBV Predefined. */ -+/* TC1_CCBBV Predefined. */ -+ -+/* TC1_CCABV Predefined. */ -+/* TC1_CCABV Predefined. */ -+ -+/* TC1_PERBV Predefined. */ -+/* TC1_PERBV Predefined. */ -+ -+/* TC1.INTFLAGS bit masks and bit positions */ -+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+/* TC2.CTRLA bit masks and bit positions */ -+#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC2.CTRLB bit masks and bit positions */ -+#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -+#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ -+ -+#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -+#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ -+ -+#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -+#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ -+ -+#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -+#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ -+ -+#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -+#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ -+ -+#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -+#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ -+ -+#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -+#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ -+ -+#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -+#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ -+ -+/* TC2.CTRLC bit masks and bit positions */ -+#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -+#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ -+ -+#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -+#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ -+ -+#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -+#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ -+ -+#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -+#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ -+ -+#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -+#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ -+ -+#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -+#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ -+ -+#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -+#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ -+ -+#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -+#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ -+ -+/* TC2.CTRLE bit masks and bit positions */ -+#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC2.INTCTRLA bit masks and bit positions */ -+#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -+#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -+#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -+#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -+#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -+#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ -+ -+#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -+#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -+#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -+#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -+#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -+#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ -+ -+/* TC2.INTCTRLB bit masks and bit positions */ -+#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -+#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -+#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -+#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -+#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -+#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -+#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -+#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -+#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -+#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -+#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -+#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -+#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -+#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -+#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -+#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -+#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -+#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -+#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -+#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -+#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ -+ -+/* TC2.CTRLF bit masks and bit positions */ -+#define TC2_CMD_gm 0x0C /* Command group mask. */ -+#define TC2_CMD_gp 2 /* Command group position. */ -+#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC2_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -+#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -+#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -+#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -+#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -+#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ -+ -+/* TC2.INTFLAGS bit masks and bit positions */ -+#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -+#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ -+ -+#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -+#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ -+ -+#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -+#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ -+ -+#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -+#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ -+ -+#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ -+ -+#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ -+ -+/* AWEX - Timer/Counter Advanced Waveform Extension */ -+/* AWEX.CTRL bit masks and bit positions */ -+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ -+ -+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ -+ -+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ -+ -+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ -+ -+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ -+ -+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ -+ -+/* AWEX.FDCTRL bit masks and bit positions */ -+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ -+ -+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ -+ -+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ -+ -+/* AWEX.STATUS bit masks and bit positions */ -+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ -+ -+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ -+ -+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ -+ -+/* AWEX.STATUSSET bit masks and bit positions */ -+/* AWEX_FDF Predefined. */ -+/* AWEX_FDF Predefined. */ -+ -+/* AWEX_DTHSBUFV Predefined. */ -+/* AWEX_DTHSBUFV Predefined. */ -+ -+/* AWEX_DTLSBUFV Predefined. */ -+/* AWEX_DTLSBUFV Predefined. */ -+ -+/* HIRES - Timer/Counter High-Resolution Extension */ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -+#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* LOCKBIT - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT0_vect_num 2 -+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -+#define PORTC_INT1_vect_num 3 -+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT0_vect_num 4 -+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -+#define PORTR_INT1_vect_num 5 -+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ -+ -+/* RTC interrupt vectors */ -+#define RTC_OVF_vect_num 10 -+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -+#define RTC_COMP_vect_num 11 -+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 12 -+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 13 -+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_OVF_vect_num 14 -+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LUNF_vect_num 14 -+#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_ERR_vect_num 15 -+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_HUNF_vect_num 15 -+#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCA_vect_num 16 -+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPA_vect_num 16 -+#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCB_vect_num 17 -+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPB_vect_num 17 -+#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCC_vect_num 18 -+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPC_vect_num 18 -+#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCD_vect_num 19 -+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPD_vect_num 19 -+#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ -+ -+/* TCC1 interrupt vectors */ -+#define TCC1_OVF_vect_num 20 -+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -+#define TCC1_ERR_vect_num 21 -+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -+#define TCC1_CCA_vect_num 22 -+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -+#define TCC1_CCB_vect_num 23 -+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 24 -+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 25 -+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 26 -+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 27 -+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 32 -+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -+#define NVM_SPM_vect_num 33 -+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ -+ -+/* PORTB interrupt vectors */ -+#define PORTB_INT0_vect_num 34 -+#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -+#define PORTB_INT1_vect_num 35 -+#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ -+ -+/* PORTE interrupt vectors */ -+#define PORTE_INT0_vect_num 43 -+#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -+#define PORTE_INT1_vect_num 44 -+#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ -+ -+/* TWIE interrupt vectors */ -+#define TWIE_TWIS_vect_num 45 -+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -+#define TWIE_TWIM_vect_num 46 -+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_OVF_vect_num 47 -+#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LUNF_vect_num 47 -+#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_ERR_vect_num 48 -+#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_HUNF_vect_num 48 -+#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCA_vect_num 49 -+#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPA_vect_num 49 -+#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCB_vect_num 50 -+#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPB_vect_num 50 -+#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCC_vect_num 51 -+#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPC_vect_num 51 -+#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCD_vect_num 52 -+#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPD_vect_num 52 -+#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ -+ -+/* USARTE0 interrupt vectors */ -+#define USARTE0_RXC_vect_num 58 -+#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -+#define USARTE0_DRE_vect_num 59 -+#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -+#define USARTE0_TXC_vect_num 60 -+#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT0_vect_num 64 -+#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -+#define PORTD_INT1_vect_num 65 -+#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ -+ -+/* PORTA interrupt vectors */ -+#define PORTA_INT0_vect_num 66 -+#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -+#define PORTA_INT1_vect_num 67 -+#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ -+ -+/* ACA interrupt vectors */ -+#define ACA_AC0_vect_num 68 -+#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -+#define ACA_AC1_vect_num 69 -+#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -+#define ACA_ACW_vect_num 70 -+#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ -+ -+/* ADCA interrupt vectors */ -+#define ADCA_CH0_vect_num 71 -+#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_OVF_vect_num 77 -+#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LUNF_vect_num 77 -+#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_ERR_vect_num 78 -+#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_HUNF_vect_num 78 -+#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCA_vect_num 79 -+#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPA_vect_num 79 -+#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCB_vect_num 80 -+#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPB_vect_num 80 -+#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCC_vect_num 81 -+#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPC_vect_num 81 -+#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCD_vect_num 82 -+#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPD_vect_num 82 -+#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ -+ -+/* SPID interrupt vectors */ -+#define SPID_INT_vect_num 87 -+#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ -+ -+/* USARTD0 interrupt vectors */ -+#define USARTD0_RXC_vect_num 88 -+#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -+#define USARTD0_DRE_vect_num 89 -+#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -+#define USARTD0_TXC_vect_num 90 -+#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ -+ -+/* PORTF interrupt vectors */ -+#define PORTF_INT0_vect_num 104 -+#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -+#define PORTF_INT1_vect_num 105 -+#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_OVF_vect_num 108 -+#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LUNF_vect_num 108 -+#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_ERR_vect_num 109 -+#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_HUNF_vect_num 109 -+#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCA_vect_num 110 -+#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPA_vect_num 110 -+#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCB_vect_num 111 -+#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPB_vect_num 111 -+#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCC_vect_num 112 -+#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPC_vect_num 112 -+#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCD_vect_num 113 -+#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPD_vect_num 113 -+#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ -+ -+/* USB interrupt vectors */ -+#define USB_BUSEVENT_vect_num 125 -+#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -+#define USB_TRNCOMPL_vect_num 126 -+#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (127 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (204800) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (196608) -+#define APP_SECTION_PAGE_SIZE (512) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0x2E000) -+#define APPTABLE_SECTION_SIZE (8192) -+#define APPTABLE_SECTION_PAGE_SIZE (512) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x30000) -+#define BOOT_SECTION_SIZE (8192) -+#define BOOT_SECTION_PAGE_SIZE (512) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (16384) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (2048) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (16384) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (2048) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (6) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (512) -+#define USER_SIGNATURES_PAGE_SIZE (512) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (64) -+#define PROD_SIGNATURES_PAGE_SIZE (512) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 512 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 6 -+ -+/* Fuse Byte 0 Reserved */ -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x97 -+#define SIGNATURE_2 0x51 -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA192C3_H_INCLUDED */ -+ -diff --git a/include/avr/iox192d3.h b/include/avr/iox192d3.h -index 874685f..101fa97 100644 ---- a/include/avr/iox192d3.h -+++ b/include/avr/iox192d3.h -@@ -174,7 +174,7 @@ typedef struct PR_struct - { - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ -- register8_t PRPB; /* Power Reduction Port B */ -+ register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ -@@ -416,6 +416,46 @@ typedef struct PMIC_struct - - /* - -------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ -+ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ -+ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ -+ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- - EVSYS - Event System - -------------------------------------------------------------------------- - */ -@@ -1005,6 +1045,15 @@ typedef struct ADC_struct - ADC_CH_t CH0; /* ADC Channel 0 */ - } ADC_t; - -+/* Current Limitation */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 225ksps max sampling rate */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 75ksps max sampling rate */ -+} ADC_CURRLIMIT_t; -+ - /* Positive input multiplexer selection */ - typedef enum ADC_CH_MUXPOS_enum - { -@@ -1059,6 +1108,7 @@ typedef enum ADC_CH_GAIN_enum - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ - } ADC_CH_GAIN_t; - - /* Conversion result resolution */ -@@ -2180,12 +2230,14 @@ IO Module Instances. Mapped to memory. - #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ - #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ - #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ - #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ - #define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ - #define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ - #define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ - #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ - #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ - #define PORTA (*(PORT_t *) 0x0600) /* Port A */ - #define PORTB (*(PORT_t *) 0x0620) /* Port B */ - #define PORTC (*(PORT_t *) 0x0640) /* Port C */ -@@ -2309,7 +2361,6 @@ IO Module Instances. Mapped to memory. - /* PR - Power Reduction */ - #define PR_PRGEN _SFR_MEM8(0x0070) - #define PR_PRPA _SFR_MEM8(0x0071) --#define PR_PRPB _SFR_MEM8(0x0072) - #define PR_PRPC _SFR_MEM8(0x0073) - #define PR_PRPD _SFR_MEM8(0x0074) - #define PR_PRPE _SFR_MEM8(0x0075) -@@ -2345,6 +2396,15 @@ IO Module Instances. Mapped to memory. - #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) - #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) - -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ - /* EVSYS - Event System */ - #define EVSYS_CH0MUX _SFR_MEM8(0x0180) - #define EVSYS_CH1MUX _SFR_MEM8(0x0181) -@@ -2423,6 +2483,22 @@ IO Module Instances. Mapped to memory. - #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) - #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -+/* TWIE - Two-Wire Interface E */ -+#define TWIE_CTRL _SFR_MEM8(0x04A0) -+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -+ - /* PORTA - Port A */ - #define PORTA_DIR _SFR_MEM8(0x0600) - #define PORTA_DIRSET _SFR_MEM8(0x0601) -@@ -2901,59 +2977,31 @@ IO Module Instances. Mapped to memory. - - - /* PR.PRGEN bit masks and bit positions */ --#define PR_AES_bm 0x10 /* AES bit mask. */ --#define PR_AES_bp 4 /* AES bit position. */ -- --#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ --#define PR_EBI_bp 3 /* External Bus Interface bit position. */ -- - #define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ - #define PR_RTC_bp 2 /* Real-time Counter bit position. */ - - #define PR_EVSYS_bm 0x02 /* Event System bit mask. */ - #define PR_EVSYS_bp 1 /* Event System bit position. */ - --#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ --#define PR_DMA_bp 0 /* DMA-Controller bit position. */ +-/* PLL Clock Source */ +-typedef enum OSC_PLLSRC_enum +-{ +- OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ +- OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ +- OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +-} OSC_PLLSRC_t; - - - /* PR.PRPA bit masks and bit positions */ --#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ --#define PR_DAC_bp 2 /* Port A DAC bit position. */ +-/* +--------------------------------------------------------------------------- +-DFLL - DFLL +--------------------------------------------------------------------------- +-*/ - - #define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ - #define PR_ADC_bp 1 /* Port A ADC bit position. */ - - #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ - #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - -- --/* PR.PRPB bit masks and bit positions */ --/* PR_DAC_bm Predefined. */ --/* PR_DAC_bp Predefined. */ -- --/* PR_ADC_bm Predefined. */ --/* PR_ADC_bp Predefined. */ -- --/* PR_AC_bm Predefined. */ --/* PR_AC_bp Predefined. */ +-/* DFLL */ +-typedef struct DFLL_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t CALA; /* Calibration Register A */ +- register8_t CALB; /* Calibration Register B */ +- register8_t COMP0; /* Oscillator Compare Register 0 */ +- register8_t COMP1; /* Oscillator Compare Register 1 */ +- register8_t COMP2; /* Oscillator Compare Register 2 */ +- register8_t reserved_0x07; +-} DFLL_t; - - - /* PR.PRPC bit masks and bit positions */ - #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ - #define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - --#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ --#define PR_USART1_bp 5 /* Port C USART1 bit position. */ +-/* +--------------------------------------------------------------------------- +-RST - Reset +--------------------------------------------------------------------------- +-*/ - - #define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ - #define PR_USART0_bp 4 /* Port C USART0 bit position. */ - - #define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ - #define PR_SPI_bp 3 /* Port C SPI bit position. */ - --#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ --#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ -+#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ -+#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ - - #define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ - #define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -@@ -2961,76 +3009,33 @@ IO Module Instances. Mapped to memory. - #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ - #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - +-/* Reset */ +-typedef struct RST_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t CTRL; /* Control Register */ +-} RST_t; - - /* PR.PRPD bit masks and bit positions */ --/* PR_TWI_bm Predefined. */ --/* PR_TWI_bp Predefined. */ - --/* PR_USART1_bm Predefined. */ --/* PR_USART1_bp Predefined. */ +-/* +--------------------------------------------------------------------------- +-WDT - Watch-Dog Timer +--------------------------------------------------------------------------- +-*/ - - /* PR_USART0_bm Predefined. */ - /* PR_USART0_bp Predefined. */ - - /* PR_SPI_bm Predefined. */ - /* PR_SPI_bp Predefined. */ - --/* PR_HIRES_bm Predefined. */ --/* PR_HIRES_bp Predefined. */ +-/* Watch-Dog Timer */ +-typedef struct WDT_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t WINCTRL; /* Windowed Mode Control */ +- register8_t STATUS; /* Status */ +-} WDT_t; - --/* PR_TC1_bm Predefined. */ --/* PR_TC1_bp Predefined. */ +-/* Period setting */ +-typedef enum WDT_PER_enum +-{ +- WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ +- WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ +- WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ +- WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_PER_t; - - /* PR_TC0_bm Predefined. */ - /* PR_TC0_bp Predefined. */ - +-/* Closed window period */ +-typedef enum WDT_WPER_enum +-{ +- WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ +- WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ +- WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ +- WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_WPER_t; - - /* PR.PRPE bit masks and bit positions */ - /* PR_TWI_bm Predefined. */ - /* PR_TWI_bp Predefined. */ - --/* PR_USART1_bm Predefined. */ --/* PR_USART1_bp Predefined. */ - - /* PR_USART0_bm Predefined. */ - /* PR_USART0_bp Predefined. */ - --/* PR_SPI_bm Predefined. */ --/* PR_SPI_bp Predefined. */ +-/* +--------------------------------------------------------------------------- +-MCU - MCU Control +--------------------------------------------------------------------------- +-*/ - --/* PR_HIRES_bm Predefined. */ --/* PR_HIRES_bp Predefined. */ +-/* MCU Control */ +-typedef struct MCU_struct +-{ +- register8_t DEVID0; /* Device ID byte 0 */ +- register8_t DEVID1; /* Device ID byte 1 */ +- register8_t DEVID2; /* Device ID byte 2 */ +- register8_t REVID; /* Revision ID */ +- register8_t JTAGUID; /* JTAG User ID */ +- register8_t reserved_0x05; +- register8_t MCUCR; /* MCU Control */ +- register8_t reserved_0x07; +- register8_t EVSYSLOCK; /* Event System Lock */ +- register8_t AWEXLOCK; /* AWEX Lock */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +-} MCU_t; - --/* PR_TC1_bm Predefined. */ --/* PR_TC1_bp Predefined. */ - - /* PR_TC0_bm Predefined. */ - /* PR_TC0_bp Predefined. */ - +-/* +--------------------------------------------------------------------------- +-PMIC - Programmable Multi-level Interrupt Controller +--------------------------------------------------------------------------- +-*/ - - /* PR.PRPF bit masks and bit positions */ --/* PR_TWI_bm Predefined. */ --/* PR_TWI_bp Predefined. */ +-/* Programmable Multi-level Interrupt Controller */ +-typedef struct PMIC_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t INTPRI; /* Interrupt Priority */ +- register8_t CTRL; /* Control Register */ +-} PMIC_t; - --/* PR_USART1_bm Predefined. */ --/* PR_USART1_bp Predefined. */ - - /* PR_USART0_bm Predefined. */ - /* PR_USART0_bp Predefined. */ - --/* PR_SPI_bm Predefined. */ --/* PR_SPI_bp Predefined. */ +-/* +--------------------------------------------------------------------------- +-DMA - DMA Controller +--------------------------------------------------------------------------- +-*/ - --/* PR_HIRES_bm Predefined. */ --/* PR_HIRES_bp Predefined. */ +-/* DMA Channel */ +-typedef struct DMA_CH_struct +-{ +- register8_t CTRLA; /* Channel Control */ +- register8_t CTRLB; /* Channel Control */ +- register8_t ADDRCTRL; /* Address Control */ +- register8_t TRIGSRC; /* Channel Trigger Source */ +- _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ +- register8_t REPCNT; /* Channel Repeat Count */ +- register8_t reserved_0x07; +- register8_t SRCADDR0; /* Channel Source Address 0 */ +- register8_t SRCADDR1; /* Channel Source Address 1 */ +- register8_t SRCADDR2; /* Channel Source Address 2 */ +- register8_t reserved_0x0B; +- register8_t DESTADDR0; /* Channel Destination Address 0 */ +- register8_t DESTADDR1; /* Channel Destination Address 1 */ +- register8_t DESTADDR2; /* Channel Destination Address 2 */ +- register8_t reserved_0x0F; +-} DMA_CH_t; - --/* PR_TC1_bm Predefined. */ --/* PR_TC1_bp Predefined. */ +-/* +--------------------------------------------------------------------------- +-DMA - DMA Controller +--------------------------------------------------------------------------- +-*/ - - /* PR_TC0_bm Predefined. */ - /* PR_TC0_bp Predefined. */ - +-/* DMA Controller */ +-typedef struct DMA_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t reserved_0x01; +- register8_t reserved_0x02; +- register8_t INTFLAGS; /* Transfer Interrupt Status */ +- register8_t STATUS; /* Status */ +- register8_t reserved_0x05; +- _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- DMA_CH_t CH0; /* DMA Channel 0 */ +- DMA_CH_t CH1; /* DMA Channel 1 */ +- DMA_CH_t CH2; /* DMA Channel 2 */ +- DMA_CH_t CH3; /* DMA Channel 3 */ +-} DMA_t; - - /* SLEEP - Sleep Controller */ - /* SLEEP.CTRL bit masks and bit positions */ - #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -@@ -3311,6 +3316,37 @@ IO Module Instances. Mapped to memory. - #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - - -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+ - /* EVSYS - Event System */ - /* EVSYS.CH0MUX bit masks and bit positions */ - #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -@@ -3940,6 +3976,13 @@ IO Module Instances. Mapped to memory. - - - /* ADC.CTRLB bit masks and bit positions */ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ -+ - #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ - #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -@@ -5407,6 +5450,12 @@ IO Module Instances. Mapped to memory. - #define PORTE_INT1_vect_num 44 - #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -+/* TWIE interrupt vectors */ -+#define TWIE_TWIS_vect_num 45 -+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -+#define TWIE_TWIM_vect_num 46 -+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ -+ - /* TCE0 interrupt vectors */ - #define TCE0_OVF_vect_num 47 - #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -diff --git a/include/avr/iox256a3b.h b/include/avr/iox256a3b.h -index aac039d..dcf31ba 100644 ---- a/include/avr/iox256a3b.h -+++ b/include/avr/iox256a3b.h -@@ -2611,7 +2611,6 @@ IO Module Instances. Mapped to memory. - #define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ - #define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ - #define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ +-/* Burst mode */ +-typedef enum DMA_CH_BURSTLEN_enum +-{ +- DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ +- DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ +- DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ +- DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +-} DMA_CH_BURSTLEN_t; +- +-/* Source address reload mode */ +-typedef enum DMA_CH_SRCRELOAD_enum +-{ +- DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ +- DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ +- DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ +- DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +-} DMA_CH_SRCRELOAD_t; +- +-/* Source addressing mode */ +-typedef enum DMA_CH_SRCDIR_enum +-{ +- DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ +- DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ +- DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +-} DMA_CH_SRCDIR_t; +- +-/* Destination adress reload mode */ +-typedef enum DMA_CH_DESTRELOAD_enum +-{ +- DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ +- DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ +- DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ +- DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +-} DMA_CH_DESTRELOAD_t; +- +-/* Destination adressing mode */ +-typedef enum DMA_CH_DESTDIR_enum +-{ +- DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ +- DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ +- DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +-} DMA_CH_DESTDIR_t; +- +-/* Transfer trigger source */ +-typedef enum DMA_CH_TRIGSRC_enum +-{ +- DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ +- DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ +- DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ +- DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ +- DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ +- DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ +- DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ +- DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ +- DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ +- DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ +- DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ +- DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ +- DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ +- DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ +- DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ +- DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ +- DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ +- DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ +- DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ +- DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ +- DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ +- DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ +- DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ +- DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ +- DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ +- DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ +- DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ +- DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ +- DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ +- DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ +- DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ +- DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ +- DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ +- DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ +- DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ +- DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ +- DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ +- DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ +- DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +-} DMA_CH_TRIGSRC_t; +- +-/* Double buffering mode */ +-typedef enum DMA_DBUFMODE_enum +-{ +- DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ +- DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ +- DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ +- DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +-} DMA_DBUFMODE_t; +- +-/* Priority mode */ +-typedef enum DMA_PRIMODE_enum +-{ +- DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ +- DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ +- DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ +- DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +-} DMA_PRIMODE_t; +- +-/* Interrupt level */ +-typedef enum DMA_CH_ERRINTLVL_enum +-{ +- DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ +- DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ +- DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +-} DMA_CH_ERRINTLVL_t; +- +-/* Interrupt level */ +-typedef enum DMA_CH_TRNINTLVL_enum +-{ +- DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ +- DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ +- DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +-} DMA_CH_TRNINTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-EVSYS - Event System +--------------------------------------------------------------------------- +-*/ +- +-/* Event System */ +-typedef struct EVSYS_struct +-{ +- register8_t CH0MUX; /* Event Channel 0 Multiplexer */ +- register8_t CH1MUX; /* Event Channel 1 Multiplexer */ +- register8_t CH2MUX; /* Event Channel 2 Multiplexer */ +- register8_t CH3MUX; /* Event Channel 3 Multiplexer */ +- register8_t CH4MUX; /* Event Channel 4 Multiplexer */ +- register8_t CH5MUX; /* Event Channel 5 Multiplexer */ +- register8_t CH6MUX; /* Event Channel 6 Multiplexer */ +- register8_t CH7MUX; /* Event Channel 7 Multiplexer */ +- register8_t CH0CTRL; /* Channel 0 Control Register */ +- register8_t CH1CTRL; /* Channel 1 Control Register */ +- register8_t CH2CTRL; /* Channel 2 Control Register */ +- register8_t CH3CTRL; /* Channel 3 Control Register */ +- register8_t CH4CTRL; /* Channel 4 Control Register */ +- register8_t CH5CTRL; /* Channel 5 Control Register */ +- register8_t CH6CTRL; /* Channel 6 Control Register */ +- register8_t CH7CTRL; /* Channel 7 Control Register */ +- register8_t STROBE; /* Event Strobe */ +- register8_t DATA; /* Event Data */ +-} EVSYS_t; +- +-/* Quadrature Decoder Index Recognition Mode */ +-typedef enum EVSYS_QDIRM_enum +-{ +- EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ +- EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ +- EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ +- EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +-} EVSYS_QDIRM_t; +- +-/* Digital filter coefficient */ +-typedef enum EVSYS_DIGFILT_enum +-{ +- EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ +- EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ +- EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ +- EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ +- EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ +- EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ +- EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ +- EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +-} EVSYS_DIGFILT_t; +- +-/* Event Channel multiplexer input selection */ +-typedef enum EVSYS_CHMUX_enum +-{ +- EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ +- EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ +- EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ +- EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ +- EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ +- EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ +- EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ +- EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ +- EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ +- EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ +- EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ +- EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ +- EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ +- EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ +- EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ +- EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ +- EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ +- EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ +- EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ +- EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ +- EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ +- EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ +- EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ +- EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ +- EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ +- EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ +- EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ +- EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ +- EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ +- EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ +- EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ +- EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ +- EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ +- EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ +- EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ +- EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ +- EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ +- EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ +- EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ +- EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ +- EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ +- EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ +- EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ +- EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ +- EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ +- EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ +- EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ +- EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ +- EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ +- EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ +- EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ +- EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ +- EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ +- EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ +- EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ +- EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ +- EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ +- EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ +- EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ +- EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ +- EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ +- EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ +- EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ +- EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ +- EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ +- EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ +- EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ +- EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ +- EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ +- EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ +- EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ +- EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ +- EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ +- EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ +- EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ +- EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ +- EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ +- EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ +- EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ +- EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ +- EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ +- EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ +- EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ +- EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ +- EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ +- EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ +- EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ +- EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ +- EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ +- EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ +- EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ +- EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ +- EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ +- EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ +- EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ +- EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ +- EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ +- EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ +- EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ +- EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ +- EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ +- EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ +- EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ +- EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ +- EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ +- EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ +- EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ +- EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ +- EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ +- EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ +- EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +- EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ +- EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ +- EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ +- EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +-} EVSYS_CHMUX_t; +- +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Non-volatile Memory Controller */ +-typedef struct NVM_struct +-{ +- register8_t ADDR0; /* Address Register 0 */ +- register8_t ADDR1; /* Address Register 1 */ +- register8_t ADDR2; /* Address Register 2 */ +- register8_t reserved_0x03; +- register8_t DATA0; /* Data Register 0 */ +- register8_t DATA1; /* Data Register 1 */ +- register8_t DATA2; /* Data Register 2 */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t CMD; /* Command */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t INTCTRL; /* Interrupt Control */ +- register8_t reserved_0x0E; +- register8_t STATUS; /* Status */ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Lock Bits */ +-typedef struct NVM_LOCKBITS_struct +-{ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_LOCKBITS_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Fuses */ +-typedef struct NVM_FUSES_struct +-{ +- register8_t FUSEBYTE0; /* JTAG User ID */ +- register8_t FUSEBYTE1; /* Watchdog Configuration */ +- register8_t FUSEBYTE2; /* Reset Configuration */ +- register8_t reserved_0x03; +- register8_t FUSEBYTE4; /* Start-up Configuration */ +- register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +-} NVM_FUSES_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Production Signatures */ +-typedef struct NVM_PROD_SIGNATURES_struct +-{ +- register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ +- register8_t reserved_0x01; +- register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ +- register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ +- register8_t reserved_0x04; +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ +- register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ +- register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ +- register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ +- register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ +- register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t WAFNUM; /* Wafer Number */ +- register8_t reserved_0x11; +- register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ +- register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ +- register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ +- register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ +- register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ +- register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ +- register8_t reserved_0x26; +- register8_t reserved_0x27; +- register8_t reserved_0x28; +- register8_t reserved_0x29; +- register8_t reserved_0x2A; +- register8_t reserved_0x2B; +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ +- register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ +- register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ +- register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ +- register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ +- register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- register8_t reserved_0x36; +- register8_t reserved_0x37; +- register8_t reserved_0x38; +- register8_t reserved_0x39; +- register8_t reserved_0x3A; +- register8_t reserved_0x3B; +- register8_t reserved_0x3C; +- register8_t reserved_0x3D; +- register8_t reserved_0x3E; +-} NVM_PROD_SIGNATURES_t; +- +-/* NVM Command */ +-typedef enum NVM_CMD_enum +-{ +- NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ +- NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ +- NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ +- NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ +- NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ +- NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ +- NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ +- NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ +- NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ +- NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ +- NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ +- NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ +- NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ +- NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ +- NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ +- NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ +- NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ +- NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ +- NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ +- NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ +- NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ +- NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ +- NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ +- NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ +- NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ +- NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +-} NVM_CMD_t; +- +-/* SPM ready interrupt level */ +-typedef enum NVM_SPMLVL_enum +-{ +- NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ +- NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ +- NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +-} NVM_SPMLVL_t; +- +-/* EEPROM ready interrupt level */ +-typedef enum NVM_EELVL_enum +-{ +- NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ +- NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ +- NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +-} NVM_EELVL_t; +- +-/* Boot lock bits - boot setcion */ +-typedef enum NVM_BLBB_enum +-{ +- NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +- NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ +- NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ +- NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +-} NVM_BLBB_t; +- +-/* Boot lock bits - application section */ +-typedef enum NVM_BLBA_enum +-{ +- NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +- NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ +- NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ +- NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +-} NVM_BLBA_t; +- +-/* Boot lock bits - application table section */ +-typedef enum NVM_BLBAT_enum +-{ +- NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +- NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ +- NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ +- NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +-} NVM_BLBAT_t; +- +-/* Lock bits */ +-typedef enum NVM_LB_enum +-{ +- NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +- NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ +- NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +-} NVM_LB_t; +- +-/* Boot Loader Section Reset Vector */ +-typedef enum BOOTRST_enum +-{ +- BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ +- BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +-} BOOTRST_t; +- +-/* BOD operation */ +-typedef enum BOD_enum +-{ +- BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ +- BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ +- BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +-} BOD_t; +- +-/* Watchdog (Window) Timeout Period */ +-typedef enum WD_enum +-{ +- WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ +- WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ +- WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ +- WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ +- WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ +- WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ +- WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ +- WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ +- WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ +- WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ +- WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +-} WD_t; +- +-/* Start-up Time */ +-typedef enum SUT_enum +-{ +- SUT_0MS_gc = (0x03<<2), /* 0 ms */ +- SUT_4MS_gc = (0x01<<2), /* 4 ms */ +- SUT_64MS_gc = (0x00<<2), /* 64 ms */ +-} SUT_t; +- +-/* Brown Out Detection Voltage Level */ +-typedef enum BODLVL_enum +-{ +- BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ +- BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ +- BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ +- BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ +- BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ +- BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ +- BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ +-} BODLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-AC - Analog Comparator +--------------------------------------------------------------------------- +-*/ +- +-/* Analog Comparator */ +-typedef struct AC_struct +-{ +- register8_t AC0CTRL; /* Comparator 0 Control */ +- register8_t AC1CTRL; /* Comparator 1 Control */ +- register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ +- register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t WINCTRL; /* Window Mode Control */ +- register8_t STATUS; /* Status */ +-} AC_t; +- +-/* Interrupt mode */ +-typedef enum AC_INTMODE_enum +-{ +- AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ +- AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ +- AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +-} AC_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum AC_INTLVL_enum +-{ +- AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ +- AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ +- AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ +- AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +-} AC_INTLVL_t; +- +-/* Hysteresis mode selection */ +-typedef enum AC_HYSMODE_enum +-{ +- AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ +- AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ +- AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +-} AC_HYSMODE_t; +- +-/* Positive input multiplexer selection */ +-typedef enum AC_MUXPOS_enum +-{ +- AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ +- AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ +- AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ +- AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ +- AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ +- AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ +- AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +- AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +-} AC_MUXPOS_t; +- +-/* Negative input multiplexer selection */ +-typedef enum AC_MUXNEG_enum +-{ +- AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ +- AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ +- AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ +- AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ +- AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ +- AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ +- AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ +- AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +-} AC_MUXNEG_t; +- +-/* Windows interrupt mode */ +-typedef enum AC_WINTMODE_enum +-{ +- AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ +- AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ +- AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ +- AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +-} AC_WINTMODE_t; +- +-/* Window interrupt level */ +-typedef enum AC_WINTLVL_enum +-{ +- AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ +- AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ +- AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +-} AC_WINTLVL_t; +- +-/* Window mode state */ +-typedef enum AC_WSTATE_enum +-{ +- AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ +- AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ +- AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +-} AC_WSTATE_t; +- +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* ADC Channel */ +-typedef struct ADC_CH_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t MUXCTRL; /* MUX Control */ +- register8_t INTCTRL; /* Channel Interrupt Control */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- _WORDREGISTER(RES); /* Channel Result */ +- register8_t reserved_0x6; +- register8_t reserved_0x7; +-} ADC_CH_t; +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Analog-to-Digital Converter */ +-typedef struct ADC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t REFCTRL; /* Reference Control */ +- register8_t EVCTRL; /* Event Control */ +- register8_t PRESCALER; /* Clock Prescaler */ +- register8_t reserved_0x05; +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- _WORDREGISTER(CAL); /* Calibration Value */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- _WORDREGISTER(CH0RES); /* Channel 0 Result */ +- _WORDREGISTER(CH1RES); /* Channel 1 Result */ +- _WORDREGISTER(CH2RES); /* Channel 2 Result */ +- _WORDREGISTER(CH3RES); /* Channel 3 Result */ +- _WORDREGISTER(CMP); /* Compare Value */ +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- ADC_CH_t CH0; /* ADC Channel 0 */ +- ADC_CH_t CH1; /* ADC Channel 1 */ +- ADC_CH_t CH2; /* ADC Channel 2 */ +- ADC_CH_t CH3; /* ADC Channel 3 */ +-} ADC_t; +- +-/* Positive input multiplexer selection */ +-typedef enum ADC_CH_MUXPOS_enum +-{ +- ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ +- ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ +- ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ +- ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ +- ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ +- ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ +- ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ +- ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +-} ADC_CH_MUXPOS_t; +- +-/* Internal input multiplexer selections */ +-typedef enum ADC_CH_MUXINT_enum +-{ +- ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ +- ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ +- ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +- ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +-} ADC_CH_MUXINT_t; +- +-/* Negative input multiplexer selection */ +-typedef enum ADC_CH_MUXNEG_enum +-{ +- ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ +- ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ +- ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ +- ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ +- ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ +- ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ +- ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ +- ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +-} ADC_CH_MUXNEG_t; +- +-/* Input mode */ +-typedef enum ADC_CH_INPUTMODE_enum +-{ +- ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ +- ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ +- ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ +- ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +-} ADC_CH_INPUTMODE_t; +- +-/* Gain factor */ +-typedef enum ADC_CH_GAIN_enum +-{ +- ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ +- ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ +- ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ +- ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ +- ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ +- ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ +- ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ +-} ADC_CH_GAIN_t; +- +-/* Conversion result resolution */ +-typedef enum ADC_RESOLUTION_enum +-{ +- ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ +- ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ +- ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +-} ADC_RESOLUTION_t; +- +-/* Voltage reference selection */ +-typedef enum ADC_REFSEL_enum +-{ +- ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ +- ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ +- ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ +- ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +-} ADC_REFSEL_t; +- +-/* Channel sweep selection */ +-typedef enum ADC_SWEEP_enum +-{ +- ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ +- ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ +- ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ +- ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +-} ADC_SWEEP_t; +- +-/* Event channel input selection */ +-typedef enum ADC_EVSEL_enum +-{ +- ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ +- ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ +- ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ +- ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ +- ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ +- ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ +- ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ +- ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +-} ADC_EVSEL_t; +- +-/* Event action selection */ +-typedef enum ADC_EVACT_enum +-{ +- ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ +- ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ +- ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ +- ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ +- ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ +- ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ +- ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ +-} ADC_EVACT_t; +- +-/* Interupt mode */ +-typedef enum ADC_CH_INTMODE_enum +-{ +- ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ +- ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ +- ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +-} ADC_CH_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum ADC_CH_INTLVL_enum +-{ +- ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ +- ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ +- ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +-} ADC_CH_INTLVL_t; +- +-/* DMA request selection */ +-typedef enum ADC_DMASEL_enum +-{ +- ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ +- ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ +- ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ +- ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +-} ADC_DMASEL_t; +- +-/* Clock prescaler */ +-typedef enum ADC_PRESCALER_enum +-{ +- ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ +- ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ +- ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ +- ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ +- ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ +- ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ +- ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ +- ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +-} ADC_PRESCALER_t; +- +- +-/* +--------------------------------------------------------------------------- +-DAC - Digital/Analog Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Digital-to-Analog Converter */ +-typedef struct DAC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t EVCTRL; /* Event Input Control */ +- register8_t TIMCTRL; /* Timing Control */ +- register8_t STATUS; /* Status */ +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t GAINCAL; /* Gain Calibration */ +- register8_t OFFSETCAL; /* Offset Calibration */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- _WORDREGISTER(CH0DATA); /* Channel 0 Data */ +- _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +-} DAC_t; +- +-/* Output channel selection */ +-typedef enum DAC_CHSEL_enum +-{ +- DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ +- DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ +-} DAC_CHSEL_t; +- +-/* Reference voltage selection */ +-typedef enum DAC_REFSEL_enum +-{ +- DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ +- DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ +- DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ +- DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +-} DAC_REFSEL_t; +- +-/* Event channel selection */ +-typedef enum DAC_EVSEL_enum +-{ +- DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ +- DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ +- DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ +- DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ +- DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ +- DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ +- DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ +- DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +-} DAC_EVSEL_t; +- +-/* Conversion interval */ +-typedef enum DAC_CONINTVAL_enum +-{ +- DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ +- DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ +- DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ +- DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ +- DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ +- DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ +- DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ +- DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ +-} DAC_CONINTVAL_t; +- +-/* Refresh rate */ +-typedef enum DAC_REFRESH_enum +-{ +- DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ +- DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ +- DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ +- DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ +- DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ +- DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ +- DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ +- DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ +- DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ +- DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ +- DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ +- DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ +- DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ +- DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ +-} DAC_REFRESH_t; +- +- +-/* +--------------------------------------------------------------------------- +-RTC - Real-Time Clounter +--------------------------------------------------------------------------- +-*/ +- +-/* Real-Time Counter */ +-typedef struct RTC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t TEMP; /* Temporary register */ +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- _WORDREGISTER(CNT); /* Count Register */ +- _WORDREGISTER(PER); /* Period Register */ +- _WORDREGISTER(COMP); /* Compare Register */ +-} RTC_t; +- +-/* Prescaler Factor */ +-typedef enum RTC_PRESCALER_enum +-{ +- RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ +- RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ +- RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ +- RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ +- RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ +- RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ +- RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ +- RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +-} RTC_PRESCALER_t; +- +-/* Compare Interrupt level */ +-typedef enum RTC_COMPINTLVL_enum +-{ +- RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} RTC_COMPINTLVL_t; +- +-/* Overflow Interrupt level */ +-typedef enum RTC_OVFINTLVL_enum +-{ +- RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} RTC_OVFINTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* EBI Chip Select Module */ +-typedef struct EBI_CS_struct +-{ +- register8_t CTRLA; /* Chip Select Control Register A */ +- register8_t CTRLB; /* Chip Select Control Register B */ +- _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +-} EBI_CS_t; +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* External Bus Interface */ +-typedef struct EBI_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t SDRAMCTRLA; /* SDRAM Control Register A */ +- register8_t reserved_0x02; +- register8_t reserved_0x03; +- _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ +- _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ +- register8_t SDRAMCTRLB; /* SDRAM Control Register B */ +- register8_t SDRAMCTRLC; /* SDRAM Control Register C */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- EBI_CS_t CS0; /* Chip Select 0 */ +- EBI_CS_t CS1; /* Chip Select 1 */ +- EBI_CS_t CS2; /* Chip Select 2 */ +- EBI_CS_t CS3; /* Chip Select 3 */ +-} EBI_t; +- +-/* Chip Select adress space */ +-typedef enum EBI_CS_ASIZE_enum +-{ +- EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ +- EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ +- EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ +- EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ +- EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ +- EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ +- EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ +- EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ +- EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ +- EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ +- EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ +- EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ +- EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ +- EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ +- EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ +- EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ +- EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +-} EBI_CS_ASIZE_t; +- +-/* */ +-typedef enum EBI_CS_SRWS_enum +-{ +- EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_CS_SRWS_t; +- +-/* Chip Select address mode */ +-typedef enum EBI_CS_MODE_enum +-{ +- EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ +- EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ +- EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ +- EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +-} EBI_CS_MODE_t; +- +-/* Chip Select SDRAM mode */ +-typedef enum EBI_CS_SDMODE_enum +-{ +- EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ +- EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +-} EBI_CS_SDMODE_t; +- +-/* */ +-typedef enum EBI_SDDATAW_enum +-{ +- EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ +- EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +-} EBI_SDDATAW_t; +- +-/* */ +-typedef enum EBI_LPCMODE_enum +-{ +- EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ +- EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +-} EBI_LPCMODE_t; +- +-/* */ +-typedef enum EBI_SRMODE_enum +-{ +- EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ +- EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ +- EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ +- EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +-} EBI_SRMODE_t; +- +-/* */ +-typedef enum EBI_IFMODE_enum +-{ +- EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ +- EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ +- EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ +- EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +-} EBI_IFMODE_t; +- +-/* */ +-typedef enum EBI_SDCOL_enum +-{ +- EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ +- EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ +- EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ +- EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +-} EBI_SDCOL_t; +- +-/* */ +-typedef enum EBI_MRDLY_enum +-{ +- EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_MRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCYCDLY_enum +-{ +- EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ROWCYCDLY_t; +- +-/* */ +-typedef enum EBI_RPDLY_enum +-{ +- EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_RPDLY_t; +- +-/* */ +-typedef enum EBI_WRDLY_enum +-{ +- EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_WRDLY_t; +- +-/* */ +-typedef enum EBI_ESRDLY_enum +-{ +- EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ESRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCOLDLY_enum +-{ +- EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_ROWCOLDLY_t; +- +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_MASTER_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t STATUS; /* Status Register */ +- register8_t BAUD; /* Baurd Rate Control Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +-} TWI_MASTER_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_SLAVE_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t STATUS; /* Status Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +- register8_t ADDRMASK; /* Address Mask Register */ +-} TWI_SLAVE_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Two-Wire Interface */ +-typedef struct TWI_struct +-{ +- register8_t CTRL; /* TWI Common Control Register */ +- TWI_MASTER_t MASTER; /* TWI master module */ +- TWI_SLAVE_t SLAVE; /* TWI slave module */ +-} TWI_t; +- +-/* Master Interrupt Level */ +-typedef enum TWI_MASTER_INTLVL_enum +-{ +- TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_MASTER_INTLVL_t; +- +-/* Inactive Timeout */ +-typedef enum TWI_MASTER_TIMEOUT_enum +-{ +- TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ +- TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ +- TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ +- TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +-} TWI_MASTER_TIMEOUT_t; +- +-/* Master Command */ +-typedef enum TWI_MASTER_CMD_enum +-{ +- TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ +- TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ +- TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +-} TWI_MASTER_CMD_t; +- +-/* Master Bus State */ +-typedef enum TWI_MASTER_BUSSTATE_enum +-{ +- TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ +- TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ +- TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ +- TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +-} TWI_MASTER_BUSSTATE_t; +- +-/* Slave Interrupt Level */ +-typedef enum TWI_SLAVE_INTLVL_enum +-{ +- TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_SLAVE_INTLVL_t; +- +-/* Slave Command */ +-typedef enum TWI_SLAVE_CMD_enum +-{ +- TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ +- TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +-} TWI_SLAVE_CMD_t; +- +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O port Configuration */ +-typedef struct PORTCFG_struct +-{ +- register8_t MPCMASK; /* Multi-pin Configuration Mask */ +- register8_t reserved_0x01; +- register8_t VPCTRLA; /* Virtual Port Control Register A */ +- register8_t VPCTRLB; /* Virtual Port Control Register B */ +- register8_t CLKEVOUT; /* Clock and Event Out Register */ +-} PORTCFG_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* Virtual Port */ +-typedef struct VPORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t OUT; /* I/O Port Output */ +- register8_t IN; /* I/O Port Input */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +-} VPORT_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O Ports */ +-typedef struct PORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t DIRSET; /* I/O Port Data Direction Set */ +- register8_t DIRCLR; /* I/O Port Data Direction Clear */ +- register8_t DIRTGL; /* I/O Port Data Direction Toggle */ +- register8_t OUT; /* I/O Port Output */ +- register8_t OUTSET; /* I/O Port Output Set */ +- register8_t OUTCLR; /* I/O Port Output Clear */ +- register8_t OUTTGL; /* I/O Port Output Toggle */ +- register8_t IN; /* I/O port Input */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INT0MASK; /* Port Interrupt 0 Mask */ +- register8_t INT1MASK; /* Port Interrupt 1 Mask */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t PIN0CTRL; /* Pin 0 Control Register */ +- register8_t PIN1CTRL; /* Pin 1 Control Register */ +- register8_t PIN2CTRL; /* Pin 2 Control Register */ +- register8_t PIN3CTRL; /* Pin 3 Control Register */ +- register8_t PIN4CTRL; /* Pin 4 Control Register */ +- register8_t PIN5CTRL; /* Pin 5 Control Register */ +- register8_t PIN6CTRL; /* Pin 6 Control Register */ +- register8_t PIN7CTRL; /* Pin 7 Control Register */ +-} PORT_t; +- +-/* Virtual Port 0 Mapping */ +-typedef enum PORTCFG_VP0MAP_enum +-{ +- PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP0MAP_t; +- +-/* Virtual Port 1 Mapping */ +-typedef enum PORTCFG_VP1MAP_enum +-{ +- PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP1MAP_t; +- +-/* Virtual Port 2 Mapping */ +-typedef enum PORTCFG_VP2MAP_enum +-{ +- PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP2MAP_t; +- +-/* Virtual Port 3 Mapping */ +-typedef enum PORTCFG_VP3MAP_enum +-{ +- PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP3MAP_t; +- +-/* Clock Output Port */ +-typedef enum PORTCFG_CLKOUT_enum +-{ +- PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ +- PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ +- PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ +- PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +-} PORTCFG_CLKOUT_t; +- +-/* Event Output Port */ +-typedef enum PORTCFG_EVOUT_enum +-{ +- PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ +- PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ +- PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ +- PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +-} PORTCFG_EVOUT_t; +- +-/* Port Interrupt 0 Level */ +-typedef enum PORT_INT0LVL_enum +-{ +- PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ +- PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ +- PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +-} PORT_INT0LVL_t; +- +-/* Port Interrupt 1 Level */ +-typedef enum PORT_INT1LVL_enum +-{ +- PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ +- PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ +- PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +-} PORT_INT1LVL_t; +- +-/* Output/Pull Configuration */ +-typedef enum PORT_OPC_enum +-{ +- PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ +- PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ +- PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ +- PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ +- PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ +- PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ +- PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ +- PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +-} PORT_OPC_t; +- +-/* Input/Sense Configuration */ +-typedef enum PORT_ISC_enum +-{ +- PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ +- PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ +- PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ +- PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ +- PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +-} PORT_ISC_t; +- +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 0 */ +-typedef struct TC0_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- _WORDREGISTER(CCC); /* Compare or Capture C */ +- _WORDREGISTER(CCD); /* Compare or Capture D */ +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +- _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ +- _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +-} TC0_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 1 */ +-typedef struct TC1_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t reserved_0x2E; +- register8_t reserved_0x2F; +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +-} TC1_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* Advanced Waveform Extension */ +-typedef struct AWEX_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t FDEMASK; /* Fault Detection Event Mask */ +- register8_t FDCTRL; /* Fault Detection Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x05; +- register8_t DTBOTH; /* Dead Time Both Sides */ +- register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ +- register8_t DTLS; /* Dead Time Low Side */ +- register8_t DTHS; /* Dead Time High Side */ +- register8_t DTLSBUF; /* Dead Time Low Side Buffer */ +- register8_t DTHSBUF; /* Dead Time High Side Buffer */ +- register8_t OUTOVEN; /* Output Override Enable */ +-} AWEX_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* High-Resolution Extension */ +-typedef struct HIRES_struct +-{ +- register8_t CTRLA; /* Control Register */ +-} HIRES_t; +- +-/* Clock Selection */ +-typedef enum TC_CLKSEL_enum +-{ +- TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ +- TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ +- TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ +- TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ +- TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ +- TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ +- TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ +- TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ +- TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_CLKSEL_t; +- +-/* Waveform Generation Mode */ +-typedef enum TC_WGMODE_enum +-{ +- TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ +- TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ +- TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ +- TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ +- TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ +- TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +-} TC_WGMODE_t; +- +-/* Event Action */ +-typedef enum TC_EVACT_enum +-{ +- TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ +- TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ +- TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ +- TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ +- TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ +- TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */ +- TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +-} TC_EVACT_t; +- +-/* Event Selection */ +-typedef enum TC_EVSEL_enum +-{ +- TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_EVSEL_t; +- +-/* Error Interrupt Level */ +-typedef enum TC_ERRINTLVL_enum +-{ +- TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_ERRINTLVL_t; +- +-/* Overflow Interrupt Level */ +-typedef enum TC_OVFINTLVL_enum +-{ +- TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_OVFINTLVL_t; +- +-/* Compare or Capture D Interrupt Level */ +-typedef enum TC_CCDINTLVL_enum +-{ +- TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TC_CCDINTLVL_t; +- +-/* Compare or Capture C Interrupt Level */ +-typedef enum TC_CCCINTLVL_enum +-{ +- TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} TC_CCCINTLVL_t; +- +-/* Compare or Capture B Interrupt Level */ +-typedef enum TC_CCBINTLVL_enum +-{ +- TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_CCBINTLVL_t; +- +-/* Compare or Capture A Interrupt Level */ +-typedef enum TC_CCAINTLVL_enum +-{ +- TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_CCAINTLVL_t; +- +-/* Timer/Counter Command */ +-typedef enum TC_CMD_enum +-{ +- TC_CMD_NONE_gc = (0x00<<2), /* No Command */ +- TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ +- TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ +- TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +-} TC_CMD_t; +- +-/* Fault Detect Action */ +-typedef enum AWEX_FDACT_enum +-{ +- AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ +- AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ +- AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +-} AWEX_FDACT_t; +- +-/* High Resolution Enable */ +-typedef enum HIRES_HREN_enum +-{ +- HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ +- HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ +- HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ +- HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +-} HIRES_HREN_t; +- +- +-/* +--------------------------------------------------------------------------- +-USART - Universal Asynchronous Receiver-Transmitter +--------------------------------------------------------------------------- +-*/ +- +-/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +-typedef struct USART_struct +-{ +- register8_t DATA; /* Data Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x02; +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t BAUDCTRLA; /* Baud Rate Control Register A */ +- register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +-} USART_t; +- +-/* Receive Complete Interrupt level */ +-typedef enum USART_RXCINTLVL_enum +-{ +- USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} USART_RXCINTLVL_t; +- +-/* Transmit Complete Interrupt level */ +-typedef enum USART_TXCINTLVL_enum +-{ +- USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} USART_TXCINTLVL_t; +- +-/* Data Register Empty Interrupt level */ +-typedef enum USART_DREINTLVL_enum +-{ +- USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} USART_DREINTLVL_t; +- +-/* Character Size */ +-typedef enum USART_CHSIZE_enum +-{ +- USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ +- USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ +- USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ +- USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ +- USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +-} USART_CHSIZE_t; +- +-/* Communication Mode */ +-typedef enum USART_CMODE_enum +-{ +- USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ +- USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ +- USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ +- USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +-} USART_CMODE_t; +- +-/* Parity Mode */ +-typedef enum USART_PMODE_enum +-{ +- USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ +- USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ +- USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +-} USART_PMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-SPI - Serial Peripheral Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Serial Peripheral Interface */ +-typedef struct SPI_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t DATA; /* Data Register */ +-} SPI_t; +- +-/* SPI Mode */ +-typedef enum SPI_MODE_enum +-{ +- SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ +- SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ +- SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ +- SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +-} SPI_MODE_t; +- +-/* Prescaler setting */ +-typedef enum SPI_PRESCALER_enum +-{ +- SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ +- SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ +- SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ +- SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +-} SPI_PRESCALER_t; +- +-/* Interrupt level */ +-typedef enum SPI_INTLVL_enum +-{ +- SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} SPI_INTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-IRCOM - IR Communication Module +--------------------------------------------------------------------------- +-*/ +- +-/* IR Communication Module */ +-typedef struct IRCOM_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ +- register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +-} IRCOM_t; +- +-/* Event channel selection */ +-typedef enum IRDA_EVSEL_enum +-{ +- IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ +- IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ +- IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ +- IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +- IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ +- IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ +- IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ +- IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +-} IRDA_EVSEL_t; +- +- +-/* +--------------------------------------------------------------------------- +-AES - AES Module +--------------------------------------------------------------------------- +-*/ +- +-/* AES Module */ +-typedef struct AES_struct +-{ +- register8_t CTRL; /* AES Control Register */ +- register8_t STATUS; /* AES Status Register */ +- register8_t STATE; /* AES State Register */ +- register8_t KEY; /* AES Key Register */ +- register8_t INTCTRL; /* AES Interrupt Control Register */ +-} AES_t; +- +-/* Interrupt level */ +-typedef enum AES_INTLVL_enum +-{ +- AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} AES_INTLVL_t; +- +- +- +-/* +-========================================================================== +-IO Module Instances. Mapped to memory. +-========================================================================== +-*/ +- +-#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +-#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +-#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +-#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +-#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +-#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +-#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +-#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +-#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +-#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +-#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +-#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +-#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +-#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +-#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +-#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +-#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ +-#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +-#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +-#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +-#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +-#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ +-#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ +-#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +-#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ +-#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +-#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +-#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ +-#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +-#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +-#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +-#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +-#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +-#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ +-#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +-#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +-#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +-#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +-#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +-#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +-#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ +-#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +-#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +-#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +-#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ +-#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ +-#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +-#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ +-#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +-#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +-#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ +-#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ +-#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ +-#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ +-#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ +-#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ +-#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ +-#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ +-#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ -#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ - #define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ - - -@@ -3448,15 +3447,6 @@ IO Module Instances. Mapped to memory. - #define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) - #define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) - +-#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ +- +- +-#endif /* !defined (__ASSEMBLER__) */ +- +- +-/* ========== Flattened fully qualified IO register names ========== */ +- +-/* GPIO - General Purpose IO Registers */ +-#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +-#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +-#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +-#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +-#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +-#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +-#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +-#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +-#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +-#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +-#define GPIO_GPIORA _SFR_MEM8(0x000A) +-#define GPIO_GPIORB _SFR_MEM8(0x000B) +-#define GPIO_GPIORC _SFR_MEM8(0x000C) +-#define GPIO_GPIORD _SFR_MEM8(0x000D) +-#define GPIO_GPIORE _SFR_MEM8(0x000E) +-#define GPIO_GPIORF _SFR_MEM8(0x000F) +- +-/* Deprecated */ +-#define GPIO_GPIO0 _SFR_MEM8(0x0000) +-#define GPIO_GPIO1 _SFR_MEM8(0x0001) +-#define GPIO_GPIO2 _SFR_MEM8(0x0002) +-#define GPIO_GPIO3 _SFR_MEM8(0x0003) +-#define GPIO_GPIO4 _SFR_MEM8(0x0004) +-#define GPIO_GPIO5 _SFR_MEM8(0x0005) +-#define GPIO_GPIO6 _SFR_MEM8(0x0006) +-#define GPIO_GPIO7 _SFR_MEM8(0x0007) +-#define GPIO_GPIO8 _SFR_MEM8(0x0008) +-#define GPIO_GPIO9 _SFR_MEM8(0x0009) +-#define GPIO_GPIOA _SFR_MEM8(0x000A) +-#define GPIO_GPIOB _SFR_MEM8(0x000B) +-#define GPIO_GPIOC _SFR_MEM8(0x000C) +-#define GPIO_GPIOD _SFR_MEM8(0x000D) +-#define GPIO_GPIOE _SFR_MEM8(0x000E) +-#define GPIO_GPIOF _SFR_MEM8(0x000F) +- +-/* VPORT0 - Virtual Port 0 */ +-#define VPORT0_DIR _SFR_MEM8(0x0010) +-#define VPORT0_OUT _SFR_MEM8(0x0011) +-#define VPORT0_IN _SFR_MEM8(0x0012) +-#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) +- +-/* VPORT1 - Virtual Port 1 */ +-#define VPORT1_DIR _SFR_MEM8(0x0014) +-#define VPORT1_OUT _SFR_MEM8(0x0015) +-#define VPORT1_IN _SFR_MEM8(0x0016) +-#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) +- +-/* VPORT2 - Virtual Port 2 */ +-#define VPORT2_DIR _SFR_MEM8(0x0018) +-#define VPORT2_OUT _SFR_MEM8(0x0019) +-#define VPORT2_IN _SFR_MEM8(0x001A) +-#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) +- +-/* VPORT3 - Virtual Port 3 */ +-#define VPORT3_DIR _SFR_MEM8(0x001C) +-#define VPORT3_OUT _SFR_MEM8(0x001D) +-#define VPORT3_IN _SFR_MEM8(0x001E) +-#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) +- +-/* OCD - On-Chip Debug System */ +-#define OCD_OCDR0 _SFR_MEM8(0x002E) +-#define OCD_OCDR1 _SFR_MEM8(0x002F) +- +-/* CPU - CPU Registers */ +-#define CPU_CCP _SFR_MEM8(0x0034) +-#define CPU_RAMPD _SFR_MEM8(0x0038) +-#define CPU_RAMPX _SFR_MEM8(0x0039) +-#define CPU_RAMPY _SFR_MEM8(0x003A) +-#define CPU_RAMPZ _SFR_MEM8(0x003B) +-#define CPU_EIND _SFR_MEM8(0x003C) +-#define CPU_SPL _SFR_MEM8(0x003D) +-#define CPU_SPH _SFR_MEM8(0x003E) +-#define CPU_SREG _SFR_MEM8(0x003F) +- +-/* CLK - Clock System */ +-#define CLK_CTRL _SFR_MEM8(0x0040) +-#define CLK_PSCTRL _SFR_MEM8(0x0041) +-#define CLK_LOCK _SFR_MEM8(0x0042) +-#define CLK_RTCCTRL _SFR_MEM8(0x0043) +- +-/* SLEEP - Sleep Controller */ +-#define SLEEP_CTRL _SFR_MEM8(0x0048) +- +-/* OSC - Oscillator Control */ +-#define OSC_CTRL _SFR_MEM8(0x0050) +-#define OSC_STATUS _SFR_MEM8(0x0051) +-#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +-#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +-#define OSC_RC32KCAL _SFR_MEM8(0x0054) +-#define OSC_PLLCTRL _SFR_MEM8(0x0055) +-#define OSC_DFLLCTRL _SFR_MEM8(0x0056) +- +-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +-#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +-#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +-#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +-#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +-#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +-#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) +- +-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +-#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +-#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +-#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +-#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +-#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +-#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) +- +-/* PR - Power Reduction */ +-#define PR_PRGEN _SFR_MEM8(0x0070) +-#define PR_PRPA _SFR_MEM8(0x0071) +-#define PR_PRPB _SFR_MEM8(0x0072) +-#define PR_PRPC _SFR_MEM8(0x0073) +-#define PR_PRPD _SFR_MEM8(0x0074) +-#define PR_PRPE _SFR_MEM8(0x0075) +-#define PR_PRPF _SFR_MEM8(0x0076) +- +-/* RST - Reset Controller */ +-#define RST_STATUS _SFR_MEM8(0x0078) +-#define RST_CTRL _SFR_MEM8(0x0079) +- +-/* WDT - Watch-Dog Timer */ +-#define WDT_CTRL _SFR_MEM8(0x0080) +-#define WDT_WINCTRL _SFR_MEM8(0x0081) +-#define WDT_STATUS _SFR_MEM8(0x0082) +- +-/* MCU - MCU Control */ +-#define MCU_DEVID0 _SFR_MEM8(0x0090) +-#define MCU_DEVID1 _SFR_MEM8(0x0091) +-#define MCU_DEVID2 _SFR_MEM8(0x0092) +-#define MCU_REVID _SFR_MEM8(0x0093) +-#define MCU_JTAGUID _SFR_MEM8(0x0094) +-#define MCU_MCUCR _SFR_MEM8(0x0096) +-#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +-#define MCU_AWEXLOCK _SFR_MEM8(0x0099) +- +-/* PMIC - Programmable Interrupt Controller */ +-#define PMIC_STATUS _SFR_MEM8(0x00A0) +-#define PMIC_INTPRI _SFR_MEM8(0x00A1) +-#define PMIC_CTRL _SFR_MEM8(0x00A2) +- +-/* PORTCFG - Port Configuration */ +-#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +-#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +-#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +-#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +- +-/* AES - AES Crypto Module */ +-#define AES_CTRL _SFR_MEM8(0x00C0) +-#define AES_STATUS _SFR_MEM8(0x00C1) +-#define AES_STATE _SFR_MEM8(0x00C2) +-#define AES_KEY _SFR_MEM8(0x00C3) +-#define AES_INTCTRL _SFR_MEM8(0x00C4) +- +-/* DMA - DMA Controller */ +-#define DMA_CTRL _SFR_MEM8(0x0100) +-#define DMA_INTFLAGS _SFR_MEM8(0x0103) +-#define DMA_STATUS _SFR_MEM8(0x0104) +-#define DMA_TEMP _SFR_MEM16(0x0106) +-#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +-#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +-#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +-#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +-#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +-#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +-#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +-#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +-#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +-#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +-#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +-#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +-#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +-#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +-#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +-#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +-#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +-#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +-#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +-#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +-#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +-#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +-#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +-#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +-#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +-#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +-#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +-#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +-#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +-#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +-#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +-#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +-#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +-#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +-#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +-#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +-#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +-#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +-#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +-#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +-#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +-#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +-#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +-#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +-#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +-#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +-#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +-#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) +- +-/* EVSYS - Event System */ +-#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +-#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +-#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +-#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +-#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +-#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +-#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +-#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +-#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +-#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +-#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +-#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +-#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +-#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +-#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +-#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +-#define EVSYS_STROBE _SFR_MEM8(0x0190) +-#define EVSYS_DATA _SFR_MEM8(0x0191) +- +-/* NVM - Non Volatile Memory Controller */ +-#define NVM_ADDR0 _SFR_MEM8(0x01C0) +-#define NVM_ADDR1 _SFR_MEM8(0x01C1) +-#define NVM_ADDR2 _SFR_MEM8(0x01C2) +-#define NVM_DATA0 _SFR_MEM8(0x01C4) +-#define NVM_DATA1 _SFR_MEM8(0x01C5) +-#define NVM_DATA2 _SFR_MEM8(0x01C6) +-#define NVM_CMD _SFR_MEM8(0x01CA) +-#define NVM_CTRLA _SFR_MEM8(0x01CB) +-#define NVM_CTRLB _SFR_MEM8(0x01CC) +-#define NVM_INTCTRL _SFR_MEM8(0x01CD) +-#define NVM_STATUS _SFR_MEM8(0x01CF) +-#define NVM_LOCKBITS _SFR_MEM8(0x01D0) +- +-/* ADCA - Analog to Digital Converter A */ +-#define ADCA_CTRLA _SFR_MEM8(0x0200) +-#define ADCA_CTRLB _SFR_MEM8(0x0201) +-#define ADCA_REFCTRL _SFR_MEM8(0x0202) +-#define ADCA_EVCTRL _SFR_MEM8(0x0203) +-#define ADCA_PRESCALER _SFR_MEM8(0x0204) +-#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +-#define ADCA_CAL _SFR_MEM16(0x020C) +-#define ADCA_CH0RES _SFR_MEM16(0x0210) +-#define ADCA_CH1RES _SFR_MEM16(0x0212) +-#define ADCA_CH2RES _SFR_MEM16(0x0214) +-#define ADCA_CH3RES _SFR_MEM16(0x0216) +-#define ADCA_CMP _SFR_MEM16(0x0218) +-#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +-#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +-#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +-#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +-#define ADCA_CH0_RES _SFR_MEM16(0x0224) +-#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +-#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +-#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +-#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +-#define ADCA_CH1_RES _SFR_MEM16(0x022C) +-#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +-#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +-#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +-#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +-#define ADCA_CH2_RES _SFR_MEM16(0x0234) +-#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +-#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +-#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +-#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +-#define ADCA_CH3_RES _SFR_MEM16(0x023C) +- +-/* ADCB - Analog to Digital Converter B */ +-#define ADCB_CTRLA _SFR_MEM8(0x0240) +-#define ADCB_CTRLB _SFR_MEM8(0x0241) +-#define ADCB_REFCTRL _SFR_MEM8(0x0242) +-#define ADCB_EVCTRL _SFR_MEM8(0x0243) +-#define ADCB_PRESCALER _SFR_MEM8(0x0244) +-#define ADCB_INTFLAGS _SFR_MEM8(0x0246) +-#define ADCB_CAL _SFR_MEM16(0x024C) +-#define ADCB_CH0RES _SFR_MEM16(0x0250) +-#define ADCB_CH1RES _SFR_MEM16(0x0252) +-#define ADCB_CH2RES _SFR_MEM16(0x0254) +-#define ADCB_CH3RES _SFR_MEM16(0x0256) +-#define ADCB_CMP _SFR_MEM16(0x0258) +-#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) +-#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) +-#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) +-#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) +-#define ADCB_CH0_RES _SFR_MEM16(0x0264) +-#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) +-#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) +-#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) +-#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) +-#define ADCB_CH1_RES _SFR_MEM16(0x026C) +-#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) +-#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) +-#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) +-#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) +-#define ADCB_CH2_RES _SFR_MEM16(0x0274) +-#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) +-#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) +-#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) +-#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) +-#define ADCB_CH3_RES _SFR_MEM16(0x027C) +- +-/* DACB - Digital to Analog Converter B */ +-#define DACB_CTRLA _SFR_MEM8(0x0320) +-#define DACB_CTRLB _SFR_MEM8(0x0321) +-#define DACB_CTRLC _SFR_MEM8(0x0322) +-#define DACB_EVCTRL _SFR_MEM8(0x0323) +-#define DACB_TIMCTRL _SFR_MEM8(0x0324) +-#define DACB_STATUS _SFR_MEM8(0x0325) +-#define DACB_GAINCAL _SFR_MEM8(0x0328) +-#define DACB_OFFSETCAL _SFR_MEM8(0x0329) +-#define DACB_CH0DATA _SFR_MEM16(0x0338) +-#define DACB_CH1DATA _SFR_MEM16(0x033A) +- +-/* ACA - Analog Comparator A */ +-#define ACA_AC0CTRL _SFR_MEM8(0x0380) +-#define ACA_AC1CTRL _SFR_MEM8(0x0381) +-#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +-#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +-#define ACA_CTRLA _SFR_MEM8(0x0384) +-#define ACA_CTRLB _SFR_MEM8(0x0385) +-#define ACA_WINCTRL _SFR_MEM8(0x0386) +-#define ACA_STATUS _SFR_MEM8(0x0387) +- +-/* ACB - Analog Comparator B */ +-#define ACB_AC0CTRL _SFR_MEM8(0x0390) +-#define ACB_AC1CTRL _SFR_MEM8(0x0391) +-#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +-#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +-#define ACB_CTRLA _SFR_MEM8(0x0394) +-#define ACB_CTRLB _SFR_MEM8(0x0395) +-#define ACB_WINCTRL _SFR_MEM8(0x0396) +-#define ACB_STATUS _SFR_MEM8(0x0397) +- +-/* RTC - Real-Time Counter */ +-#define RTC_CTRL _SFR_MEM8(0x0400) +-#define RTC_STATUS _SFR_MEM8(0x0401) +-#define RTC_INTCTRL _SFR_MEM8(0x0402) +-#define RTC_INTFLAGS _SFR_MEM8(0x0403) +-#define RTC_TEMP _SFR_MEM8(0x0404) +-#define RTC_CNT _SFR_MEM16(0x0408) +-#define RTC_PER _SFR_MEM16(0x040A) +-#define RTC_COMP _SFR_MEM16(0x040C) +- +-/* TWIC - Two-Wire Interface C */ +-#define TWIC_CTRL _SFR_MEM8(0x0480) +-#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +-#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +-#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +-#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +-#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +-#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +-#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +-#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +-#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +-#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +-#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +-#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +-#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) +- +-/* TWIE - Two-Wire Interface E */ +-#define TWIE_CTRL _SFR_MEM8(0x04A0) +-#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +-#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +-#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +-#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +-#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +-#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +-#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +-#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +-#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +-#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +-#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +-#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +-#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) +- +-/* PORTA - Port A */ +-#define PORTA_DIR _SFR_MEM8(0x0600) +-#define PORTA_DIRSET _SFR_MEM8(0x0601) +-#define PORTA_DIRCLR _SFR_MEM8(0x0602) +-#define PORTA_DIRTGL _SFR_MEM8(0x0603) +-#define PORTA_OUT _SFR_MEM8(0x0604) +-#define PORTA_OUTSET _SFR_MEM8(0x0605) +-#define PORTA_OUTCLR _SFR_MEM8(0x0606) +-#define PORTA_OUTTGL _SFR_MEM8(0x0607) +-#define PORTA_IN _SFR_MEM8(0x0608) +-#define PORTA_INTCTRL _SFR_MEM8(0x0609) +-#define PORTA_INT0MASK _SFR_MEM8(0x060A) +-#define PORTA_INT1MASK _SFR_MEM8(0x060B) +-#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +-#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +-#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +-#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +-#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +-#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +-#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +-#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +-#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) +- +-/* PORTB - Port B */ +-#define PORTB_DIR _SFR_MEM8(0x0620) +-#define PORTB_DIRSET _SFR_MEM8(0x0621) +-#define PORTB_DIRCLR _SFR_MEM8(0x0622) +-#define PORTB_DIRTGL _SFR_MEM8(0x0623) +-#define PORTB_OUT _SFR_MEM8(0x0624) +-#define PORTB_OUTSET _SFR_MEM8(0x0625) +-#define PORTB_OUTCLR _SFR_MEM8(0x0626) +-#define PORTB_OUTTGL _SFR_MEM8(0x0627) +-#define PORTB_IN _SFR_MEM8(0x0628) +-#define PORTB_INTCTRL _SFR_MEM8(0x0629) +-#define PORTB_INT0MASK _SFR_MEM8(0x062A) +-#define PORTB_INT1MASK _SFR_MEM8(0x062B) +-#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +-#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +-#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +-#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +-#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +-#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +-#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +-#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +-#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) +- +-/* PORTC - Port C */ +-#define PORTC_DIR _SFR_MEM8(0x0640) +-#define PORTC_DIRSET _SFR_MEM8(0x0641) +-#define PORTC_DIRCLR _SFR_MEM8(0x0642) +-#define PORTC_DIRTGL _SFR_MEM8(0x0643) +-#define PORTC_OUT _SFR_MEM8(0x0644) +-#define PORTC_OUTSET _SFR_MEM8(0x0645) +-#define PORTC_OUTCLR _SFR_MEM8(0x0646) +-#define PORTC_OUTTGL _SFR_MEM8(0x0647) +-#define PORTC_IN _SFR_MEM8(0x0648) +-#define PORTC_INTCTRL _SFR_MEM8(0x0649) +-#define PORTC_INT0MASK _SFR_MEM8(0x064A) +-#define PORTC_INT1MASK _SFR_MEM8(0x064B) +-#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +-#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +-#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +-#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +-#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +-#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +-#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +-#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +-#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) +- +-/* PORTD - Port D */ +-#define PORTD_DIR _SFR_MEM8(0x0660) +-#define PORTD_DIRSET _SFR_MEM8(0x0661) +-#define PORTD_DIRCLR _SFR_MEM8(0x0662) +-#define PORTD_DIRTGL _SFR_MEM8(0x0663) +-#define PORTD_OUT _SFR_MEM8(0x0664) +-#define PORTD_OUTSET _SFR_MEM8(0x0665) +-#define PORTD_OUTCLR _SFR_MEM8(0x0666) +-#define PORTD_OUTTGL _SFR_MEM8(0x0667) +-#define PORTD_IN _SFR_MEM8(0x0668) +-#define PORTD_INTCTRL _SFR_MEM8(0x0669) +-#define PORTD_INT0MASK _SFR_MEM8(0x066A) +-#define PORTD_INT1MASK _SFR_MEM8(0x066B) +-#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +-#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +-#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +-#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +-#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +-#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +-#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +-#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +-#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) +- +-/* PORTE - Port E */ +-#define PORTE_DIR _SFR_MEM8(0x0680) +-#define PORTE_DIRSET _SFR_MEM8(0x0681) +-#define PORTE_DIRCLR _SFR_MEM8(0x0682) +-#define PORTE_DIRTGL _SFR_MEM8(0x0683) +-#define PORTE_OUT _SFR_MEM8(0x0684) +-#define PORTE_OUTSET _SFR_MEM8(0x0685) +-#define PORTE_OUTCLR _SFR_MEM8(0x0686) +-#define PORTE_OUTTGL _SFR_MEM8(0x0687) +-#define PORTE_IN _SFR_MEM8(0x0688) +-#define PORTE_INTCTRL _SFR_MEM8(0x0689) +-#define PORTE_INT0MASK _SFR_MEM8(0x068A) +-#define PORTE_INT1MASK _SFR_MEM8(0x068B) +-#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +-#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +-#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +-#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +-#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +-#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +-#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +-#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +-#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) +- +-/* PORTF - Port F */ +-#define PORTF_DIR _SFR_MEM8(0x06A0) +-#define PORTF_DIRSET _SFR_MEM8(0x06A1) +-#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +-#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +-#define PORTF_OUT _SFR_MEM8(0x06A4) +-#define PORTF_OUTSET _SFR_MEM8(0x06A5) +-#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +-#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +-#define PORTF_IN _SFR_MEM8(0x06A8) +-#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +-#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +-#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +-#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +-#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +-#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +-#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +-#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +-#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +-#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +-#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +-#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) +- +-/* PORTR - Port R */ +-#define PORTR_DIR _SFR_MEM8(0x07E0) +-#define PORTR_DIRSET _SFR_MEM8(0x07E1) +-#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +-#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +-#define PORTR_OUT _SFR_MEM8(0x07E4) +-#define PORTR_OUTSET _SFR_MEM8(0x07E5) +-#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +-#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +-#define PORTR_IN _SFR_MEM8(0x07E8) +-#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +-#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +-#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +-#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +-#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +-#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +-#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +-#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +-#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +-#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +-#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +-#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) +- +-/* TCC0 - Timer/Counter C0 */ +-#define TCC0_CTRLA _SFR_MEM8(0x0800) +-#define TCC0_CTRLB _SFR_MEM8(0x0801) +-#define TCC0_CTRLC _SFR_MEM8(0x0802) +-#define TCC0_CTRLD _SFR_MEM8(0x0803) +-#define TCC0_CTRLE _SFR_MEM8(0x0804) +-#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +-#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +-#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +-#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +-#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +-#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +-#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +-#define TCC0_TEMP _SFR_MEM8(0x080F) +-#define TCC0_CNT _SFR_MEM16(0x0820) +-#define TCC0_PER _SFR_MEM16(0x0826) +-#define TCC0_CCA _SFR_MEM16(0x0828) +-#define TCC0_CCB _SFR_MEM16(0x082A) +-#define TCC0_CCC _SFR_MEM16(0x082C) +-#define TCC0_CCD _SFR_MEM16(0x082E) +-#define TCC0_PERBUF _SFR_MEM16(0x0836) +-#define TCC0_CCABUF _SFR_MEM16(0x0838) +-#define TCC0_CCBBUF _SFR_MEM16(0x083A) +-#define TCC0_CCCBUF _SFR_MEM16(0x083C) +-#define TCC0_CCDBUF _SFR_MEM16(0x083E) +- +-/* TCC1 - Timer/Counter C1 */ +-#define TCC1_CTRLA _SFR_MEM8(0x0840) +-#define TCC1_CTRLB _SFR_MEM8(0x0841) +-#define TCC1_CTRLC _SFR_MEM8(0x0842) +-#define TCC1_CTRLD _SFR_MEM8(0x0843) +-#define TCC1_CTRLE _SFR_MEM8(0x0844) +-#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +-#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +-#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +-#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +-#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +-#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +-#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +-#define TCC1_TEMP _SFR_MEM8(0x084F) +-#define TCC1_CNT _SFR_MEM16(0x0860) +-#define TCC1_PER _SFR_MEM16(0x0866) +-#define TCC1_CCA _SFR_MEM16(0x0868) +-#define TCC1_CCB _SFR_MEM16(0x086A) +-#define TCC1_PERBUF _SFR_MEM16(0x0876) +-#define TCC1_CCABUF _SFR_MEM16(0x0878) +-#define TCC1_CCBBUF _SFR_MEM16(0x087A) +- +-/* AWEXC - Advanced Waveform Extension C */ +-#define AWEXC_CTRL _SFR_MEM8(0x0880) +-#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +-#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +-#define AWEXC_STATUS _SFR_MEM8(0x0884) +-#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +-#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +-#define AWEXC_DTLS _SFR_MEM8(0x0888) +-#define AWEXC_DTHS _SFR_MEM8(0x0889) +-#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +-#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +-#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) +- +-/* HIRESC - High-Resolution Extension C */ +-#define HIRESC_CTRLA _SFR_MEM8(0x0890) +- +-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +-#define USARTC0_DATA _SFR_MEM8(0x08A0) +-#define USARTC0_STATUS _SFR_MEM8(0x08A1) +-#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +-#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +-#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +-#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +-#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) +- +-/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ +-#define USARTC1_DATA _SFR_MEM8(0x08B0) +-#define USARTC1_STATUS _SFR_MEM8(0x08B1) +-#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +-#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +-#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +-#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +-#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) +- +-/* SPIC - Serial Peripheral Interface C */ +-#define SPIC_CTRL _SFR_MEM8(0x08C0) +-#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +-#define SPIC_STATUS _SFR_MEM8(0x08C2) +-#define SPIC_DATA _SFR_MEM8(0x08C3) +- +-/* IRCOM - IR Communication Module */ +-#define IRCOM_CTRL _SFR_MEM8(0x08F8) +-#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +-#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) +- +-/* TCD0 - Timer/Counter D0 */ +-#define TCD0_CTRLA _SFR_MEM8(0x0900) +-#define TCD0_CTRLB _SFR_MEM8(0x0901) +-#define TCD0_CTRLC _SFR_MEM8(0x0902) +-#define TCD0_CTRLD _SFR_MEM8(0x0903) +-#define TCD0_CTRLE _SFR_MEM8(0x0904) +-#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +-#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +-#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +-#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +-#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +-#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +-#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +-#define TCD0_TEMP _SFR_MEM8(0x090F) +-#define TCD0_CNT _SFR_MEM16(0x0920) +-#define TCD0_PER _SFR_MEM16(0x0926) +-#define TCD0_CCA _SFR_MEM16(0x0928) +-#define TCD0_CCB _SFR_MEM16(0x092A) +-#define TCD0_CCC _SFR_MEM16(0x092C) +-#define TCD0_CCD _SFR_MEM16(0x092E) +-#define TCD0_PERBUF _SFR_MEM16(0x0936) +-#define TCD0_CCABUF _SFR_MEM16(0x0938) +-#define TCD0_CCBBUF _SFR_MEM16(0x093A) +-#define TCD0_CCCBUF _SFR_MEM16(0x093C) +-#define TCD0_CCDBUF _SFR_MEM16(0x093E) +- +-/* TCD1 - Timer/Counter D1 */ +-#define TCD1_CTRLA _SFR_MEM8(0x0940) +-#define TCD1_CTRLB _SFR_MEM8(0x0941) +-#define TCD1_CTRLC _SFR_MEM8(0x0942) +-#define TCD1_CTRLD _SFR_MEM8(0x0943) +-#define TCD1_CTRLE _SFR_MEM8(0x0944) +-#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +-#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +-#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +-#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +-#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +-#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +-#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +-#define TCD1_TEMP _SFR_MEM8(0x094F) +-#define TCD1_CNT _SFR_MEM16(0x0960) +-#define TCD1_PER _SFR_MEM16(0x0966) +-#define TCD1_CCA _SFR_MEM16(0x0968) +-#define TCD1_CCB _SFR_MEM16(0x096A) +-#define TCD1_PERBUF _SFR_MEM16(0x0976) +-#define TCD1_CCABUF _SFR_MEM16(0x0978) +-#define TCD1_CCBBUF _SFR_MEM16(0x097A) +- +-/* HIRESD - High-Resolution Extension D */ +-#define HIRESD_CTRLA _SFR_MEM8(0x0990) +- +-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +-#define USARTD0_DATA _SFR_MEM8(0x09A0) +-#define USARTD0_STATUS _SFR_MEM8(0x09A1) +-#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +-#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +-#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +-#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +-#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) +- +-/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ +-#define USARTD1_DATA _SFR_MEM8(0x09B0) +-#define USARTD1_STATUS _SFR_MEM8(0x09B1) +-#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +-#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +-#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +-#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +-#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) +- +-/* SPID - Serial Peripheral Interface D */ +-#define SPID_CTRL _SFR_MEM8(0x09C0) +-#define SPID_INTCTRL _SFR_MEM8(0x09C1) +-#define SPID_STATUS _SFR_MEM8(0x09C2) +-#define SPID_DATA _SFR_MEM8(0x09C3) +- +-/* TCE0 - Timer/Counter E0 */ +-#define TCE0_CTRLA _SFR_MEM8(0x0A00) +-#define TCE0_CTRLB _SFR_MEM8(0x0A01) +-#define TCE0_CTRLC _SFR_MEM8(0x0A02) +-#define TCE0_CTRLD _SFR_MEM8(0x0A03) +-#define TCE0_CTRLE _SFR_MEM8(0x0A04) +-#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +-#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +-#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +-#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +-#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +-#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +-#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +-#define TCE0_TEMP _SFR_MEM8(0x0A0F) +-#define TCE0_CNT _SFR_MEM16(0x0A20) +-#define TCE0_PER _SFR_MEM16(0x0A26) +-#define TCE0_CCA _SFR_MEM16(0x0A28) +-#define TCE0_CCB _SFR_MEM16(0x0A2A) +-#define TCE0_CCC _SFR_MEM16(0x0A2C) +-#define TCE0_CCD _SFR_MEM16(0x0A2E) +-#define TCE0_PERBUF _SFR_MEM16(0x0A36) +-#define TCE0_CCABUF _SFR_MEM16(0x0A38) +-#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +-#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +-#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) +- +-/* TCE1 - Timer/Counter E1 */ +-#define TCE1_CTRLA _SFR_MEM8(0x0A40) +-#define TCE1_CTRLB _SFR_MEM8(0x0A41) +-#define TCE1_CTRLC _SFR_MEM8(0x0A42) +-#define TCE1_CTRLD _SFR_MEM8(0x0A43) +-#define TCE1_CTRLE _SFR_MEM8(0x0A44) +-#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) +-#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) +-#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) +-#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) +-#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) +-#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) +-#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) +-#define TCE1_TEMP _SFR_MEM8(0x0A4F) +-#define TCE1_CNT _SFR_MEM16(0x0A60) +-#define TCE1_PER _SFR_MEM16(0x0A66) +-#define TCE1_CCA _SFR_MEM16(0x0A68) +-#define TCE1_CCB _SFR_MEM16(0x0A6A) +-#define TCE1_PERBUF _SFR_MEM16(0x0A76) +-#define TCE1_CCABUF _SFR_MEM16(0x0A78) +-#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) +- +-/* AWEXE - Advanced Waveform Extension E */ +-#define AWEXE_CTRL _SFR_MEM8(0x0A80) +-#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +-#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +-#define AWEXE_STATUS _SFR_MEM8(0x0A84) +-#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +-#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +-#define AWEXE_DTLS _SFR_MEM8(0x0A88) +-#define AWEXE_DTHS _SFR_MEM8(0x0A89) +-#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +-#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +-#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) +- +-/* HIRESE - High-Resolution Extension E */ +-#define HIRESE_CTRLA _SFR_MEM8(0x0A90) +- +-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +-#define USARTE0_DATA _SFR_MEM8(0x0AA0) +-#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +-#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +-#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +-#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +-#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +-#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) +- +-/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ +-#define USARTE1_DATA _SFR_MEM8(0x0AB0) +-#define USARTE1_STATUS _SFR_MEM8(0x0AB1) +-#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) +-#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) +-#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) +-#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) +-#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) +- +-/* SPIE - Serial Peripheral Interface E */ +-#define SPIE_CTRL _SFR_MEM8(0x0AC0) +-#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +-#define SPIE_STATUS _SFR_MEM8(0x0AC2) +-#define SPIE_DATA _SFR_MEM8(0x0AC3) +- +-/* TCF0 - Timer/Counter F0 */ +-#define TCF0_CTRLA _SFR_MEM8(0x0B00) +-#define TCF0_CTRLB _SFR_MEM8(0x0B01) +-#define TCF0_CTRLC _SFR_MEM8(0x0B02) +-#define TCF0_CTRLD _SFR_MEM8(0x0B03) +-#define TCF0_CTRLE _SFR_MEM8(0x0B04) +-#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +-#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +-#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +-#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +-#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +-#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +-#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +-#define TCF0_TEMP _SFR_MEM8(0x0B0F) +-#define TCF0_CNT _SFR_MEM16(0x0B20) +-#define TCF0_PER _SFR_MEM16(0x0B26) +-#define TCF0_CCA _SFR_MEM16(0x0B28) +-#define TCF0_CCB _SFR_MEM16(0x0B2A) +-#define TCF0_CCC _SFR_MEM16(0x0B2C) +-#define TCF0_CCD _SFR_MEM16(0x0B2E) +-#define TCF0_PERBUF _SFR_MEM16(0x0B36) +-#define TCF0_CCABUF _SFR_MEM16(0x0B38) +-#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +-#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +-#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) +- +-/* HIRESF - High-Resolution Extension F */ +-#define HIRESF_CTRLA _SFR_MEM8(0x0B90) +- +-/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ +-#define USARTF0_DATA _SFR_MEM8(0x0BA0) +-#define USARTF0_STATUS _SFR_MEM8(0x0BA1) +-#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) +-#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) +-#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) +-#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) +-#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) +- -/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ -#define USARTF1_DATA _SFR_MEM8(0x0BB0) -#define USARTF1_STATUS _SFR_MEM8(0x0BB1) @@ -146278,66824 +322124,290091 @@ index aac039d..dcf31ba 100644 -#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) -#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) - - /* SPIF - Serial Peripheral Interface F */ - #define SPIF_CTRL _SFR_MEM8(0x0BC0) - #define SPIF_INTCTRL _SFR_MEM8(0x0BC1) +-/* SPIF - Serial Peripheral Interface F */ +-#define SPIF_CTRL _SFR_MEM8(0x0BC0) +-#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) +-#define SPIF_STATUS _SFR_MEM8(0x0BC2) +-#define SPIF_DATA _SFR_MEM8(0x0BC3) +- +- +- +-/*================== Bitfield Definitions ================== */ +- +-/* XOCD - On-Chip Debug System */ +-/* OCD.OCDR1 bit masks and bit positions */ +-#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +-#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ +- +- +-/* CPU - CPU */ +-/* CPU.CCP bit masks and bit positions */ +-#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +-#define CPU_CCP_gp 0 /* CCP signature group position. */ +-#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +-#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +-#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +-#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +-#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +-#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +-#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +-#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +-#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +-#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +-#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +-#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +-#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +-#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +-#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +-#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ +- +- +-/* CPU.SREG bit masks and bit positions */ +-#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +-#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ +- +-#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +-#define CPU_T_bp 6 /* Transfer Bit bit position. */ +- +-#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +-#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +- +-#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +-#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +- +-#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +-#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +- +-#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +-#define CPU_N_bp 2 /* Negative Flag bit position. */ +- +-#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +-#define CPU_Z_bp 1 /* Zero Flag bit position. */ +- +-#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +-#define CPU_C_bp 0 /* Carry Flag bit position. */ +- +- +-/* CLK - Clock System */ +-/* CLK.CTRL bit masks and bit positions */ +-#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +-#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +-#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +-#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +-#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +-#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +-#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +-#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ +- +- +-/* CLK.PSCTRL bit masks and bit positions */ +-#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +-#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +-#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +-#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +-#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +-#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +-#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +-#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +-#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +-#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +-#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +-#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ +- +-#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +-#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +-#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +-#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +-#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +-#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ +- +- +-/* CLK.LOCK bit masks and bit positions */ +-#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +-#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ +- +- +-/* CLK.RTCCTRL bit masks and bit positions */ +-#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +-#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +-#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +-#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +-#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +-#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +-#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +-#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ +- +-#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +-#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ +- +- +-/* PR.PRGEN bit masks and bit positions */ +-#define PR_AES_bm 0x10 /* AES bit mask. */ +-#define PR_AES_bp 4 /* AES bit position. */ +- +-#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +-#define PR_EBI_bp 3 /* External Bus Interface bit position. */ +- +-#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +-#define PR_RTC_bp 2 /* Real-time Counter bit position. */ +- +-#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +-#define PR_EVSYS_bp 1 /* Event System bit position. */ +- +-#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +-#define PR_DMA_bp 0 /* DMA-Controller bit position. */ +- +- +-/* PR.PRPA bit masks and bit positions */ +-#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +-#define PR_DAC_bp 2 /* Port A DAC bit position. */ +- +-#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +-#define PR_ADC_bp 1 /* Port A ADC bit position. */ +- +-#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +-#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ +- +- +-/* PR.PRPB bit masks and bit positions */ +-/* PR_DAC_bm Predefined. */ +-/* PR_DAC_bp Predefined. */ +- +-/* PR_ADC_bm Predefined. */ +-/* PR_ADC_bp Predefined. */ +- +-/* PR_AC_bm Predefined. */ +-/* PR_AC_bp Predefined. */ +- +- +-/* PR.PRPC bit masks and bit positions */ +-#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +-#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ +- +-#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +-#define PR_USART1_bp 5 /* Port C USART1 bit position. */ +- +-#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +-#define PR_USART0_bp 4 /* Port C USART0 bit position. */ +- +-#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +-#define PR_SPI_bp 3 /* Port C SPI bit position. */ +- +-#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +-#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ +- +-#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +-#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ +- +-#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +-#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ +- +- +-/* PR.PRPD bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* PR.PRPE bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* PR.PRPF bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* SLEEP - Sleep Controller */ +-/* SLEEP.CTRL bit masks and bit positions */ +-#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +-#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +-#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +-#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +-#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +-#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +-#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +-#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ +- +-#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +-#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ +- +- +-/* OSC - Oscillator */ +-/* OSC.CTRL bit masks and bit positions */ +-#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +-#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ +- +-#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +-#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ +- +-#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ +- +- +-/* OSC.STATUS bit masks and bit positions */ +-#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +-#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ +- +-#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +-#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ +- +-#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ +- +- +-/* OSC.XOSCCTRL bit masks and bit positions */ +-#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +-#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +-#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +-#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +-#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +-#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ +- +-#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +-#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ +- +-#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +-#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +-#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +-#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +-#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +-#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +-#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +-#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +-#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +-#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +- +- +-/* OSC.XOSCFAIL bit masks and bit positions */ +-#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +-#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ +- +-#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +-#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ +- +- +-/* OSC.PLLCTRL bit masks and bit positions */ +-#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +-#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +-#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +-#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +-#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +-#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ +- +-#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +-#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +-#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +-#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +-#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +-#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +-#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +-#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +-#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +-#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +-#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +-#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ +- +- +-/* OSC.DFLLCTRL bit masks and bit positions */ +-#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +-#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ +- +-#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +-#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ +- +- +-/* DFLL - DFLL */ +-/* DFLL.CTRL bit masks and bit positions */ +-#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +-#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ +- +- +-/* DFLL.CALA bit masks and bit positions */ +-#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +-#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +-#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +-#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +-#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +-#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +-#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +-#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +-#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +-#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +-#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +-#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +-#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +-#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +-#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +-#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ +- +- +-/* DFLL.CALB bit masks and bit positions */ +-#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +-#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +-#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +-#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +-#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +-#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +-#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +-#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +-#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +-#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +-#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +-#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +-#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +-#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ +- +- +-/* RST - Reset */ +-/* RST.STATUS bit masks and bit positions */ +-#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +-#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ +- +-#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +-#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ +- +-#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +-#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ +- +-#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +-#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ +- +-#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +-#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ +- +-#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +-#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ +- +-#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +-#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ +- +- +-/* RST.CTRL bit masks and bit positions */ +-#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +-#define RST_SWRST_bp 0 /* Software Reset bit position. */ +- +- +-/* WDT - Watch-Dog Timer */ +-/* WDT.CTRL bit masks and bit positions */ +-#define WDT_PER_gm 0x3C /* Period group mask. */ +-#define WDT_PER_gp 2 /* Period group position. */ +-#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +-#define WDT_PER0_bp 2 /* Period bit 0 position. */ +-#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +-#define WDT_PER1_bp 3 /* Period bit 1 position. */ +-#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +-#define WDT_PER2_bp 4 /* Period bit 2 position. */ +-#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +-#define WDT_PER3_bp 5 /* Period bit 3 position. */ +- +-#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +-#define WDT_ENABLE_bp 1 /* Enable bit position. */ +- +-#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +-#define WDT_CEN_bp 0 /* Change Enable bit position. */ +- +- +-/* WDT.WINCTRL bit masks and bit positions */ +-#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +-#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +-#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +-#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +-#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +-#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +-#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +-#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +-#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +-#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ +- +-#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +-#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ +- +-#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +-#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ +- +- +-/* WDT.STATUS bit masks and bit positions */ +-#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +-#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +- +- +-/* MCU - MCU Control */ +-/* MCU.MCUCR bit masks and bit positions */ +-#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +-#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ +- +- +-/* MCU.EVSYSLOCK bit masks and bit positions */ +-#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +-#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ +- +-#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +-#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ +- +- +-/* MCU.AWEXLOCK bit masks and bit positions */ +-#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +-#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ +- +-#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +-#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ +- +- +-/* PMIC - Programmable Multi-level Interrupt Controller */ +-/* PMIC.STATUS bit masks and bit positions */ +-#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +-#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ +- +-#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +-#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ +- +-#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +-#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ +- +-#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +-#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ +- +- +-/* PMIC.CTRL bit masks and bit positions */ +-#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +-#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ +- +-#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +-#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ +- +-#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +-#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ +- +-#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +-#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ +- +-#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +-#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ +- +- +-/* DMA - DMA Controller */ +-/* DMA_CH.CTRLA bit masks and bit positions */ +-#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +-#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ +- +-#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +-#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ +- +-#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +-#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ +- +-#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +-#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ +- +-#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +-#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ +- +-#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +-#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +-#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +-#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +-#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +-#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ +- +- +-/* DMA_CH.CTRLB bit masks and bit positions */ +-#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +-#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ +- +-#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +-#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ +- +-#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +-#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ +- +-#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +-#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +-#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +-#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +-#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +-#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ +- +-#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +-#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +-#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +-#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +-#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +-#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ +- +- +-/* DMA_CH.ADDRCTRL bit masks and bit positions */ +-#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +-#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +-#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +-#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +-#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +-#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ +- +-#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +-#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +-#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +-#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +-#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +-#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ +- +-#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +-#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +-#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +-#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +-#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +-#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ +- +-#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +-#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +-#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +-#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +-#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +-#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ +- +- +-/* DMA_CH.TRIGSRC bit masks and bit positions */ +-#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +-#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +-#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +-#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +-#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +-#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +-#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +-#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +-#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +-#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +-#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +-#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +-#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +-#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +-#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +-#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +-#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +-#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ +- +- +-/* DMA.CTRL bit masks and bit positions */ +-#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +-#define DMA_ENABLE_bp 7 /* Enable bit position. */ +- +-#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +-#define DMA_RESET_bp 6 /* Software Reset bit position. */ +- +-#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +-#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +-#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +-#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +-#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +-#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ +- +-#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +-#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +-#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +-#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +-#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +-#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ +- +- +-/* DMA.INTFLAGS bit masks and bit positions */ +-#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ +- +- +-/* DMA.STATUS bit masks and bit positions */ +-#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +-#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ +- +-#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +-#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ +- +-#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +-#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ +- +-#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +-#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ +- +-#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +-#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ +- +-#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +-#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ +- +-#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +-#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ +- +-#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +-#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ +- +- +-/* EVSYS - Event System */ +-/* EVSYS.CH0MUX bit masks and bit positions */ +-#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +-#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +-#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +-#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +-#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +-#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +-#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +-#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +-#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +-#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +-#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +-#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +-#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +-#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +-#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +-#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +-#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +-#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ +- +- +-/* EVSYS.CH1MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH2MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH3MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH4MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH5MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH6MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH7MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH0CTRL bit masks and bit positions */ +-#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +-#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +-#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +-#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +-#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +-#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ +- +-#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +-#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ +- +-#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +-#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ +- +-#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +-#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +-#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +-#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +-#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +-#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +-#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +-#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ +- +- +-/* EVSYS.CH1CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH2CTRL bit masks and bit positions */ +-/* EVSYS_QDIRM_gm Predefined. */ +-/* EVSYS_QDIRM_gp Predefined. */ +-/* EVSYS_QDIRM0_bm Predefined. */ +-/* EVSYS_QDIRM0_bp Predefined. */ +-/* EVSYS_QDIRM1_bm Predefined. */ +-/* EVSYS_QDIRM1_bp Predefined. */ +- +-/* EVSYS_QDIEN_bm Predefined. */ +-/* EVSYS_QDIEN_bp Predefined. */ +- +-/* EVSYS_QDEN_bm Predefined. */ +-/* EVSYS_QDEN_bp Predefined. */ +- +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH3CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH4CTRL bit masks and bit positions */ +-/* EVSYS_QDIRM_gm Predefined. */ +-/* EVSYS_QDIRM_gp Predefined. */ +-/* EVSYS_QDIRM0_bm Predefined. */ +-/* EVSYS_QDIRM0_bp Predefined. */ +-/* EVSYS_QDIRM1_bm Predefined. */ +-/* EVSYS_QDIRM1_bp Predefined. */ +- +-/* EVSYS_QDIEN_bm Predefined. */ +-/* EVSYS_QDIEN_bp Predefined. */ +- +-/* EVSYS_QDEN_bm Predefined. */ +-/* EVSYS_QDEN_bp Predefined. */ +- +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH5CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH6CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH7CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* NVM - Non Volatile Memory Controller */ +-/* NVM.CMD bit masks and bit positions */ +-#define NVM_CMD_gm 0xFF /* Command group mask. */ +-#define NVM_CMD_gp 0 /* Command group position. */ +-#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +-#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +-#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +-#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +-#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +-#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +-#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +-#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +-#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +-#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +-#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +-#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +-#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +-#define NVM_CMD7_bp 7 /* Command bit 7 position. */ +- +- +-/* NVM.CTRLA bit masks and bit positions */ +-#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +-#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ +- +- +-/* NVM.CTRLB bit masks and bit positions */ +-#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +-#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ +- +-#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +-#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ +- +-#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +-#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ +- +-#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +-#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ +- +- +-/* NVM.INTCTRL bit masks and bit positions */ +-#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +-#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +-#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +-#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +-#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +-#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ +- +-#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +-#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +-#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +-#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +-#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +-#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ +- +- +-/* NVM.STATUS bit masks and bit positions */ +-#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +-#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ +- +-#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +-#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ +- +-#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +-#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ +- +-#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +-#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ +- +- +-/* NVM.LOCKBITS bit masks and bit positions */ +-#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +-#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +-#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ +-#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ +-#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ +-#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ +-#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ +-#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ +-#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ +-#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ +-#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ +-#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ +-#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ +-#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ +-#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ +-#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ +-#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ +-#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ +-#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ +-#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +-#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +-#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +-#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ +- +-#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +-#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +-#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +-#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +-#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ +- +-#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +-#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ +- +-#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +-#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +-#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +-#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +-#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +-#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +-#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +-#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +-#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +-#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +-#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +-#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ +- +-#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +-#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ +- +-#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ +-#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ +- +- +-/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +-#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +-#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +-#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +-#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +-#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +-#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ +- +-#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +-#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ +- +-#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +-#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +-#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +-#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +-#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +-#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +-#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +-#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +- +- +-/* AC - Analog Comparator */ +-/* AC.AC0CTRL bit masks and bit positions */ +-#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +-#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +-#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +-#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +-#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +-#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ +- +-#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +-#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +-#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +-#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +-#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +-#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ +- +-#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +-#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ +- +-#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +-#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +-#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +-#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +-#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +-#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +- +-#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define AC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* AC.AC1CTRL bit masks and bit positions */ +-/* AC_INTMODE_gm Predefined. */ +-/* AC_INTMODE_gp Predefined. */ +-/* AC_INTMODE0_bm Predefined. */ +-/* AC_INTMODE0_bp Predefined. */ +-/* AC_INTMODE1_bm Predefined. */ +-/* AC_INTMODE1_bp Predefined. */ +- +-/* AC_INTLVL_gm Predefined. */ +-/* AC_INTLVL_gp Predefined. */ +-/* AC_INTLVL0_bm Predefined. */ +-/* AC_INTLVL0_bp Predefined. */ +-/* AC_INTLVL1_bm Predefined. */ +-/* AC_INTLVL1_bp Predefined. */ +- +-/* AC_HSMODE_bm Predefined. */ +-/* AC_HSMODE_bp Predefined. */ +- +-/* AC_HYSMODE_gm Predefined. */ +-/* AC_HYSMODE_gp Predefined. */ +-/* AC_HYSMODE0_bm Predefined. */ +-/* AC_HYSMODE0_bp Predefined. */ +-/* AC_HYSMODE1_bm Predefined. */ +-/* AC_HYSMODE1_bp Predefined. */ +- +-/* AC_ENABLE_bm Predefined. */ +-/* AC_ENABLE_bp Predefined. */ +- +- +-/* AC.AC0MUXCTRL bit masks and bit positions */ +-#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +-#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +-#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +-#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +-#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +-#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +-#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +-#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ +- +-#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +-#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +-#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +-#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +-#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +-#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +-#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +-#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ +- +- +-/* AC.AC1MUXCTRL bit masks and bit positions */ +-/* AC_MUXPOS_gm Predefined. */ +-/* AC_MUXPOS_gp Predefined. */ +-/* AC_MUXPOS0_bm Predefined. */ +-/* AC_MUXPOS0_bp Predefined. */ +-/* AC_MUXPOS1_bm Predefined. */ +-/* AC_MUXPOS1_bp Predefined. */ +-/* AC_MUXPOS2_bm Predefined. */ +-/* AC_MUXPOS2_bp Predefined. */ +- +-/* AC_MUXNEG_gm Predefined. */ +-/* AC_MUXNEG_gp Predefined. */ +-/* AC_MUXNEG0_bm Predefined. */ +-/* AC_MUXNEG0_bp Predefined. */ +-/* AC_MUXNEG1_bm Predefined. */ +-/* AC_MUXNEG1_bp Predefined. */ +-/* AC_MUXNEG2_bm Predefined. */ +-/* AC_MUXNEG2_bp Predefined. */ +- +- +-/* AC.CTRLA bit masks and bit positions */ +-#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +-#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ +- +- +-/* AC.CTRLB bit masks and bit positions */ +-#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +-#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +-#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +-#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +-#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +-#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +-#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +-#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +-#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +-#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +-#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +-#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +-#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +-#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ +- +- +-/* AC.WINCTRL bit masks and bit positions */ +-#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +-#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ +- +-#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +-#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +-#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +-#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +-#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +-#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ +- +-#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +-#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +-#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +-#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +-#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +-#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ +- +- +-/* AC.STATUS bit masks and bit positions */ +-#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +-#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +-#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +-#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +-#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +-#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ +- +-#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +-#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ +- +-#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +-#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ +- +-#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +-#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ +- +-#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +-#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ +- +-#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +-#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ +- +- +-/* ADC - Analog/Digital Converter */ +-/* ADC_CH.CTRL bit masks and bit positions */ +-#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +-#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ +- +-#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +-#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +-#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +-#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +-#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +-#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +-#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +-#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ +- +-#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +-#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +-#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +-#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +-#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +-#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ +- +- +-/* ADC_CH.MUXCTRL bit masks and bit positions */ +-#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +-#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +-#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +-#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +-#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +-#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +-#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +-#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +-#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +-#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ +- +-#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +-#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +-#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +-#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +-#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +-#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +-#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +-#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +-#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +-#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ +- +-#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +-#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +-#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +-#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +-#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +-#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ +- +- +-/* ADC_CH.INTCTRL bit masks and bit positions */ +-#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +-#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +-#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +-#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +-#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +-#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ +- +-#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +-#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +-#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +-#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +-#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +-#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ +- +- +-/* ADC_CH.INTFLAGS bit masks and bit positions */ +-#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +-#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ +- +- +-/* ADC.CTRLA bit masks and bit positions */ +-#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +-#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +-#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +-#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +-#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +-#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ +- +-#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +-#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ +- +-#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +-#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ +- +-#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +-#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ +- +-#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +-#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ +- +-#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +-#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ +- +-#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +-#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ +- +- +-/* ADC.CTRLB bit masks and bit positions */ +-#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +-#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ +- +-#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +-#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ +- +-#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +-#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +-#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +-#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +-#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +-#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ +- +- +-/* ADC.REFCTRL bit masks and bit positions */ +-#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +-#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +-#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +-#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +-#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +-#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +- +-#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +-#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ +- +-#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +-#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ +- +- +-/* ADC.EVCTRL bit masks and bit positions */ +-#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +-#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +-#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +-#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +-#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +-#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ +- +-#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +-#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +-#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +-#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +-#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +-#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +-#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +-#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ +- +-#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +-#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +-#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +-#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +-#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +-#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +-#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +-#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ +- +- +-/* ADC.PRESCALER bit masks and bit positions */ +-#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +-#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +-#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +-#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +-#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +-#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +-#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +-#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ +- +- +-/* ADC.INTFLAGS bit masks and bit positions */ +-#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +-#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ +- +-#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +-#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ +- +-#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +-#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ +- +-#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +-#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ +- +- +-/* DAC - Digital/Analog Converter */ +-/* DAC.CTRLA bit masks and bit positions */ +-#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +-#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ +- +-#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +-#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ +- +-#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +-#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ +- +-#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +-#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ +- +-#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define DAC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* DAC.CTRLB bit masks and bit positions */ +-#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +-#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +-#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +-#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +-#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +-#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ +- +-#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +-#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ +- +-#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +-#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ +- +- +-/* DAC.CTRLC bit masks and bit positions */ +-#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +-#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +-#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +-#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +-#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +-#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ +- +-#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +-#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ +- +- +-/* DAC.EVCTRL bit masks and bit positions */ +-#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +-#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +-#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +-#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +-#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +-#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +-#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +-#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ +- +- +-/* DAC.TIMCTRL bit masks and bit positions */ +-#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ +-#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ +-#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ +-#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ +-#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ +-#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ +-#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ +-#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ +- +-#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ +-#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ +-#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ +-#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ +-#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ +-#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ +-#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ +-#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ +-#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ +-#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ +- +- +-/* DAC.STATUS bit masks and bit positions */ +-#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +-#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ +- +-#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +-#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ +- +- +-/* RTC - Real-Time Clounter */ +-/* RTC.CTRL bit masks and bit positions */ +-#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +-#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +-#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +-#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +-#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +-#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +-#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +-#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ +- +- +-/* RTC.STATUS bit masks and bit positions */ +-#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +-#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ +- +- +-/* RTC.INTCTRL bit masks and bit positions */ +-#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +-#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +-#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +-#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +-#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +-#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ +- +-#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +-#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +-#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +-#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +-#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +-#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ +- +- +-/* RTC.INTFLAGS bit masks and bit positions */ +-#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +-#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ +- +-#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* EBI - External Bus Interface */ +-/* EBI_CS.CTRLA bit masks and bit positions */ +-#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +-#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +-#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +-#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +-#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +-#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +-#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +-#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +-#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +-#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +-#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +-#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ +- +-#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +-#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +-#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +-#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +-#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +-#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ +- +- +-/* EBI_CS.CTRLB bit masks and bit positions */ +-#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +-#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +-#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +-#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +-#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +-#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +-#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +-#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ +- +-#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +-#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ +- +-#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +-#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ +- +-#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +-#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +-#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +-#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +-#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +-#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ +- +- +-/* EBI.CTRL bit masks and bit positions */ +-#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +-#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +-#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +-#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +-#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +-#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ +- +-#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +-#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +-#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +-#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +-#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +-#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ +- +-#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +-#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +-#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +-#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +-#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +-#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ +- +-#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +-#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +-#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +-#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +-#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +-#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLA bit masks and bit positions */ +-#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +-#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ +- +-#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +-#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ +- +-#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +-#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +-#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +-#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +-#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +-#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLB bit masks and bit positions */ +-#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +-#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +-#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +-#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +-#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +-#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ +- +-#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +-#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +-#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +-#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +-#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +-#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +-#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +-#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ +- +-#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +-#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +-#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +-#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +-#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +-#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +-#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +-#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ +- +- +-/* EBI.SDRAMCTRLC bit masks and bit positions */ +-#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +-#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +-#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +-#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +-#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +-#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ +- +-#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +-#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +-#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +-#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +-#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +-#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +-#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +-#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ +- +-#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +-#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +-#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +-#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +-#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +-#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +-#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +-#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ +- +- +-/* TWI - Two-Wire Interface */ +-/* TWI_MASTER.CTRLA bit masks and bit positions */ +-#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +-#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ +- +-#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +-#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ +- +-#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +-#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ +- +- +-/* TWI_MASTER.CTRLB bit masks and bit positions */ +-#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +-#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +-#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +-#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +-#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +-#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +- +-#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +-#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ +- +-#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_MASTER.CTRLC bit masks and bit positions */ +-#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +-#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_MASTER.STATUS bit masks and bit positions */ +-#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +-#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ +- +-#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +-#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ +- +-#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +-#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +- +-#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +-#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +-#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +-#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +-#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +-#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +- +- +-/* TWI_SLAVE.CTRLA bit masks and bit positions */ +-#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +-#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +-#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ +- +-#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +-#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ +- +-#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_SLAVE.CTRLB bit masks and bit positions */ +-#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +-#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_SLAVE.STATUS bit masks and bit positions */ +-#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +-#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +-#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +-#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ +- +-#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +-#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ +- +-#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +-#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ +- +- +-/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +-#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +-#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +-#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +-#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +-#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +-#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +-#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +-#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +-#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +-#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +-#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +-#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +-#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +-#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +-#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +-#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ +- +-#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +-#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ +- +- +-/* TWI.CTRL bit masks and bit positions */ +-#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +-#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ +- +-#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +-#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ +- +- +-/* PORT - Port Configuration */ +-/* PORTCFG.VPCTRLA bit masks and bit positions */ +-#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +-#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +-#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +-#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +-#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +-#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +-#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +-#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +-#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +-#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ +- +-#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +-#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +-#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +-#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +-#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +-#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +-#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +-#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +-#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +-#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ +- +- +-/* PORTCFG.VPCTRLB bit masks and bit positions */ +-#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +-#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +-#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +-#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +-#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +-#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +-#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +-#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +-#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +-#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ +- +-#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +-#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +-#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +-#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +-#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +-#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +-#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +-#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +-#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +-#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ +- +- +-/* PORTCFG.CLKEVOUT bit masks and bit positions */ +-#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +-#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +-#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +-#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +-#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +-#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ +- +-#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +-#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +-#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +-#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +-#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +-#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ +- +- +-/* VPORT.INTFLAGS bit masks and bit positions */ +-#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.INTCTRL bit masks and bit positions */ +-#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +-#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +-#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +-#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +-#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +-#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ +- +-#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +-#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +-#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +-#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +-#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +-#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ +- +- +-/* PORT.INTFLAGS bit masks and bit positions */ +-#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.PIN0CTRL bit masks and bit positions */ +-#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +-#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ +- +-#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +-#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ +- +-#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +-#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +-#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +-#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +-#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +-#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +-#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +-#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ +- +-#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +-#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +-#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +-#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +-#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +-#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +-#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +-#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +- +- +-/* PORT.PIN1CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN2CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN3CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN4CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN5CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN6CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN7CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* TC - 16-bit Timer/Counter With PWM */ +-/* TC0.CTRLA bit masks and bit positions */ +-#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC0.CTRLB bit masks and bit positions */ +-#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +-#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ +- +-#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +-#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ +- +-#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC0.CTRLC bit masks and bit positions */ +-#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +-#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ +- +-#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +-#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ +- +-#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC0.CTRLD bit masks and bit positions */ +-#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC0_EVACT_gp 5 /* Event Action group position. */ +-#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC0.CTRLE bit masks and bit positions */ +-#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +-#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ +- +-#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC0.INTCTRLA bit masks and bit positions */ +-#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC0.INTCTRLB bit masks and bit positions */ +-#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +-#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +-#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +-#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +-#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +-#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ +- +-#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +-#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +-#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +-#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +-#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +-#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ +- +-#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC0.CTRLFCLR bit masks and bit positions */ +-#define TC0_CMD_gm 0x0C /* Command group mask. */ +-#define TC0_CMD_gp 2 /* Command group position. */ +-#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC0_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC0_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC0_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC0.CTRLFSET bit masks and bit positions */ +-/* TC0_CMD_gm Predefined. */ +-/* TC0_CMD_gp Predefined. */ +-/* TC0_CMD0_bm Predefined. */ +-/* TC0_CMD0_bp Predefined. */ +-/* TC0_CMD1_bm Predefined. */ +-/* TC0_CMD1_bp Predefined. */ +- +-/* TC0_LUPD_bm Predefined. */ +-/* TC0_LUPD_bp Predefined. */ +- +-/* TC0_DIR_bm Predefined. */ +-/* TC0_DIR_bp Predefined. */ +- +- +-/* TC0.CTRLGCLR bit masks and bit positions */ +-#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +-#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ +- +-#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +-#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ +- +-#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC0.CTRLGSET bit masks and bit positions */ +-/* TC0_CCDBV_bm Predefined. */ +-/* TC0_CCDBV_bp Predefined. */ +- +-/* TC0_CCCBV_bm Predefined. */ +-/* TC0_CCCBV_bp Predefined. */ +- +-/* TC0_CCBBV_bm Predefined. */ +-/* TC0_CCBBV_bp Predefined. */ +- +-/* TC0_CCABV_bm Predefined. */ +-/* TC0_CCABV_bp Predefined. */ +- +-/* TC0_PERBV_bm Predefined. */ +-/* TC0_PERBV_bp Predefined. */ +- +- +-/* TC0.INTFLAGS bit masks and bit positions */ +-#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +-#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ +- +-#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +-#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ +- +-#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* TC1.CTRLA bit masks and bit positions */ +-#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC1.CTRLB bit masks and bit positions */ +-#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC1.CTRLC bit masks and bit positions */ +-#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC1.CTRLD bit masks and bit positions */ +-#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC1_EVACT_gp 5 /* Event Action group position. */ +-#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC1.CTRLE bit masks and bit positions */ +-#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +-#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ +- +-#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC1.INTCTRLA bit masks and bit positions */ +-#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC1.INTCTRLB bit masks and bit positions */ +-#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC1.CTRLFCLR bit masks and bit positions */ +-#define TC1_CMD_gm 0x0C /* Command group mask. */ +-#define TC1_CMD_gp 2 /* Command group position. */ +-#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC1_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC1_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC1_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC1.CTRLFSET bit masks and bit positions */ +-/* TC1_CMD_gm Predefined. */ +-/* TC1_CMD_gp Predefined. */ +-/* TC1_CMD0_bm Predefined. */ +-/* TC1_CMD0_bp Predefined. */ +-/* TC1_CMD1_bm Predefined. */ +-/* TC1_CMD1_bp Predefined. */ +- +-/* TC1_LUPD_bm Predefined. */ +-/* TC1_LUPD_bp Predefined. */ +- +-/* TC1_DIR_bm Predefined. */ +-/* TC1_DIR_bp Predefined. */ +- +- +-/* TC1.CTRLGCLR bit masks and bit positions */ +-#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC1.CTRLGSET bit masks and bit positions */ +-/* TC1_CCBBV_bm Predefined. */ +-/* TC1_CCBBV_bp Predefined. */ +- +-/* TC1_CCABV_bm Predefined. */ +-/* TC1_CCABV_bp Predefined. */ +- +-/* TC1_PERBV_bm Predefined. */ +-/* TC1_PERBV_bp Predefined. */ +- +- +-/* TC1.INTFLAGS bit masks and bit positions */ +-#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* AWEX.CTRL bit masks and bit positions */ +-#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +-#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ +- +-#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +-#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ +- +-#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +-#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ +- +-#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +-#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ +- +-#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +-#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ +- +-#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +-#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ +- +- +-/* AWEX.FDCTRL bit masks and bit positions */ +-#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +-#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ +- +-#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +-#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ +- +-#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +-#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +-#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +-#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +-#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +-#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ +- +- +-/* AWEX.STATUS bit masks and bit positions */ +-#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +-#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ +- +-#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +-#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ +- +-#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +-#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ +- +- +-/* HIRES.CTRL bit masks and bit positions */ +-#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +-#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +-#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +-#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +-#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +-#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ +- +- +-/* USART - Universal Asynchronous Receiver-Transmitter */ +-/* USART.STATUS bit masks and bit positions */ +-#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +-#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ +- +-#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +-#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +- +-#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +-#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +- +-#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +-#define USART_FERR_bp 4 /* Frame Error bit position. */ +- +-#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +-#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ +- +-#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +-#define USART_PERR_bp 2 /* Parity Error bit position. */ +- +-#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +-#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ +- +- +-/* USART.CTRLA bit masks and bit positions */ +-#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +-#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +-#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +-#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +-#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +-#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ +- +-#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +-#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +-#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +-#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +-#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +-#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ +- +-#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +-#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +-#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +-#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +-#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +-#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ +- +- +-/* USART.CTRLB bit masks and bit positions */ +-#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +-#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ +- +-#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +-#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ +- +-#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +-#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ +- +-#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +-#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ +- +-#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +-#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ +- +- +-/* USART.CTRLC bit masks and bit positions */ +-#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +-#define USART_CMODE_gp 6 /* Communication Mode group position. */ +-#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +-#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +-#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +-#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ +- +-#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +-#define USART_PMODE_gp 4 /* Parity Mode group position. */ +-#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +-#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +-#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +-#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +- +-#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +-#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +- +-#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +-#define USART_CHSIZE_gp 0 /* Character Size group position. */ +-#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +-#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +-#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +-#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +-#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +-#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +- +- +-/* USART.BAUDCTRLA bit masks and bit positions */ +-#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +-#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +-#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +-#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +-#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +-#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +-#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +-#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +-#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +-#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +-#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +-#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +-#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +-#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +-#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +-#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +-#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +-#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ +- +- +-/* USART.BAUDCTRLB bit masks and bit positions */ +-#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +-#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +-#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +-#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +-#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +-#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +-#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +-#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +-#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +-#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ +- +-/* USART_BSEL_gm Predefined. */ +-/* USART_BSEL_gp Predefined. */ +-/* USART_BSEL0_bm Predefined. */ +-/* USART_BSEL0_bp Predefined. */ +-/* USART_BSEL1_bm Predefined. */ +-/* USART_BSEL1_bp Predefined. */ +-/* USART_BSEL2_bm Predefined. */ +-/* USART_BSEL2_bp Predefined. */ +-/* USART_BSEL3_bm Predefined. */ +-/* USART_BSEL3_bp Predefined. */ +- +- +-/* SPI - Serial Peripheral Interface */ +-/* SPI.CTRL bit masks and bit positions */ +-#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +-#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ +- +-#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +-#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ +- +-#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +-#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ +- +-#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +-#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ +- +-#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +-#define SPI_MODE_gp 2 /* SPI Mode group position. */ +-#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +-#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +-#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +-#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ +- +-#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +-#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +-#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +-#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +-#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +-#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ +- +- +-/* SPI.INTCTRL bit masks and bit positions */ +-#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +-#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +-/* SPI.STATUS bit masks and bit positions */ +-#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +-#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ +- +-#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +-#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +- +- +-/* IRCOM - IR Communication Module */ +-/* IRCOM.CTRL bit masks and bit positions */ +-#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +-#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +-#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +-#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +-#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +-#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +-#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +-#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +-#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +-#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ +- +- +-/* AES - AES Module */ +-/* AES.CTRL bit masks and bit positions */ +-#define AES_START_bm 0x80 /* Start/Run bit mask. */ +-#define AES_START_bp 7 /* Start/Run bit position. */ +- +-#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +-#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ +- +-#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +-#define AES_RESET_bp 5 /* AES Software Reset bit position. */ +- +-#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +-#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ +- +-#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +-#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ +- +- +-/* AES.STATUS bit masks and bit positions */ +-#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +-#define AES_ERROR_bp 7 /* AES Error bit position. */ +- +-#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +-#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ +- +- +-/* AES.INTCTRL bit masks and bit positions */ +-#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +-#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +- +-// Generic Port Pins +- +-#define PIN0_bm 0x01 +-#define PIN0_bp 0 +-#define PIN1_bm 0x02 +-#define PIN1_bp 1 +-#define PIN2_bm 0x04 +-#define PIN2_bp 2 +-#define PIN3_bm 0x08 +-#define PIN3_bp 3 +-#define PIN4_bm 0x10 +-#define PIN4_bp 4 +-#define PIN5_bm 0x20 +-#define PIN5_bp 5 +-#define PIN6_bm 0x40 +-#define PIN6_bp 6 +-#define PIN7_bm 0x80 +-#define PIN7_bp 7 +- +- +-/* ========== Interrupt Vector Definitions ========== */ +-/* Vector 0 is the reset vector */ +- +-/* OSC interrupt vectors */ +-#define OSC_XOSCF_vect_num 1 +-#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ +- +-/* PORTC interrupt vectors */ +-#define PORTC_INT0_vect_num 2 +-#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +-#define PORTC_INT1_vect_num 3 +-#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ +- +-/* PORTR interrupt vectors */ +-#define PORTR_INT0_vect_num 4 +-#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +-#define PORTR_INT1_vect_num 5 +-#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ +- +-/* DMA interrupt vectors */ +-#define DMA_CH0_vect_num 6 +-#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +-#define DMA_CH1_vect_num 7 +-#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +-#define DMA_CH2_vect_num 8 +-#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +-#define DMA_CH3_vect_num 9 +-#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ +- +-/* RTC interrupt vectors */ +-#define RTC_OVF_vect_num 10 +-#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +-#define RTC_COMP_vect_num 11 +-#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ +- +-/* TWIC interrupt vectors */ +-#define TWIC_TWIS_vect_num 12 +-#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +-#define TWIC_TWIM_vect_num 13 +-#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ +- +-/* TCC0 interrupt vectors */ +-#define TCC0_OVF_vect_num 14 +-#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +-#define TCC0_ERR_vect_num 15 +-#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +-#define TCC0_CCA_vect_num 16 +-#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +-#define TCC0_CCB_vect_num 17 +-#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +-#define TCC0_CCC_vect_num 18 +-#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +-#define TCC0_CCD_vect_num 19 +-#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ +- +-/* TCC1 interrupt vectors */ +-#define TCC1_OVF_vect_num 20 +-#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +-#define TCC1_ERR_vect_num 21 +-#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +-#define TCC1_CCA_vect_num 22 +-#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +-#define TCC1_CCB_vect_num 23 +-#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ +- +-/* SPIC interrupt vectors */ +-#define SPIC_INT_vect_num 24 +-#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ +- +-/* USARTC0 interrupt vectors */ +-#define USARTC0_RXC_vect_num 25 +-#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +-#define USARTC0_DRE_vect_num 26 +-#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +-#define USARTC0_TXC_vect_num 27 +-#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ +- +-/* USARTC1 interrupt vectors */ +-#define USARTC1_RXC_vect_num 28 +-#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +-#define USARTC1_DRE_vect_num 29 +-#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +-#define USARTC1_TXC_vect_num 30 +-#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ +- +-/* AES interrupt vectors */ +-#define AES_INT_vect_num 31 +-#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ +- +-/* NVM interrupt vectors */ +-#define NVM_EE_vect_num 32 +-#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +-#define NVM_SPM_vect_num 33 +-#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ +- +-/* PORTB interrupt vectors */ +-#define PORTB_INT0_vect_num 34 +-#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +-#define PORTB_INT1_vect_num 35 +-#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ +- +-/* ACB interrupt vectors */ +-#define ACB_AC0_vect_num 36 +-#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ +-#define ACB_AC1_vect_num 37 +-#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ +-#define ACB_ACW_vect_num 38 +-#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ +- +-/* ADCB interrupt vectors */ +-#define ADCB_CH0_vect_num 39 +-#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ +-#define ADCB_CH1_vect_num 40 +-#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ +-#define ADCB_CH2_vect_num 41 +-#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ +-#define ADCB_CH3_vect_num 42 +-#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ +- +-/* PORTE interrupt vectors */ +-#define PORTE_INT0_vect_num 43 +-#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +-#define PORTE_INT1_vect_num 44 +-#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ +- +-/* TWIE interrupt vectors */ +-#define TWIE_TWIS_vect_num 45 +-#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +-#define TWIE_TWIM_vect_num 46 +-#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ +- +-/* TCE0 interrupt vectors */ +-#define TCE0_OVF_vect_num 47 +-#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +-#define TCE0_ERR_vect_num 48 +-#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +-#define TCE0_CCA_vect_num 49 +-#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +-#define TCE0_CCB_vect_num 50 +-#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +-#define TCE0_CCC_vect_num 51 +-#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +-#define TCE0_CCD_vect_num 52 +-#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ +- +-/* TCE1 interrupt vectors */ +-#define TCE1_OVF_vect_num 53 +-#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ +-#define TCE1_ERR_vect_num 54 +-#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ +-#define TCE1_CCA_vect_num 55 +-#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ +-#define TCE1_CCB_vect_num 56 +-#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ +- +-/* SPIE interrupt vectors */ +-#define SPIE_INT_vect_num 57 +-#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ +- +-/* USARTE0 interrupt vectors */ +-#define USARTE0_RXC_vect_num 58 +-#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +-#define USARTE0_DRE_vect_num 59 +-#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +-#define USARTE0_TXC_vect_num 60 +-#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ +- +-/* USARTE1 interrupt vectors */ +-#define USARTE1_RXC_vect_num 61 +-#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ +-#define USARTE1_DRE_vect_num 62 +-#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ +-#define USARTE1_TXC_vect_num 63 +-#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ +- +-/* PORTD interrupt vectors */ +-#define PORTD_INT0_vect_num 64 +-#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +-#define PORTD_INT1_vect_num 65 +-#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ +- +-/* PORTA interrupt vectors */ +-#define PORTA_INT0_vect_num 66 +-#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +-#define PORTA_INT1_vect_num 67 +-#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ +- +-/* ACA interrupt vectors */ +-#define ACA_AC0_vect_num 68 +-#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +-#define ACA_AC1_vect_num 69 +-#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +-#define ACA_ACW_vect_num 70 +-#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ +- +-/* ADCA interrupt vectors */ +-#define ADCA_CH0_vect_num 71 +-#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +-#define ADCA_CH1_vect_num 72 +-#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +-#define ADCA_CH2_vect_num 73 +-#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +-#define ADCA_CH3_vect_num 74 +-#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ +- +-/* TCD0 interrupt vectors */ +-#define TCD0_OVF_vect_num 77 +-#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +-#define TCD0_ERR_vect_num 78 +-#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +-#define TCD0_CCA_vect_num 79 +-#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +-#define TCD0_CCB_vect_num 80 +-#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +-#define TCD0_CCC_vect_num 81 +-#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +-#define TCD0_CCD_vect_num 82 +-#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ +- +-/* TCD1 interrupt vectors */ +-#define TCD1_OVF_vect_num 83 +-#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +-#define TCD1_ERR_vect_num 84 +-#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +-#define TCD1_CCA_vect_num 85 +-#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +-#define TCD1_CCB_vect_num 86 +-#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ +- +-/* SPID interrupt vectors */ +-#define SPID_INT_vect_num 87 +-#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ +- +-/* USARTD0 interrupt vectors */ +-#define USARTD0_RXC_vect_num 88 +-#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +-#define USARTD0_DRE_vect_num 89 +-#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +-#define USARTD0_TXC_vect_num 90 +-#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ +- +-/* USARTD1 interrupt vectors */ +-#define USARTD1_RXC_vect_num 91 +-#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +-#define USARTD1_DRE_vect_num 92 +-#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +-#define USARTD1_TXC_vect_num 93 +-#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ +- +-/* PORTF interrupt vectors */ +-#define PORTF_INT0_vect_num 104 +-#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +-#define PORTF_INT1_vect_num 105 +-#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ +- +-/* TCF0 interrupt vectors */ +-#define TCF0_OVF_vect_num 108 +-#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ +-#define TCF0_ERR_vect_num 109 +-#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ +-#define TCF0_CCA_vect_num 110 +-#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ +-#define TCF0_CCB_vect_num 111 +-#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ +-#define TCF0_CCC_vect_num 112 +-#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ +-#define TCF0_CCD_vect_num 113 +-#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ +- +-/* USARTF0 interrupt vectors */ +-#define USARTF0_RXC_vect_num 119 +-#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ +-#define USARTF0_DRE_vect_num 120 +-#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ +-#define USARTF0_TXC_vect_num 121 +-#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ +- +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (122 * _VECTOR_SIZE) +- +- +-/* ========== Constants ========== */ +- +-#define PROGMEM_START (0x0000) +-#define PROGMEM_SIZE (139264) +-#define PROGMEM_PAGE_SIZE (512) +-#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) +- +-#define APP_SECTION_START (0x0000) +-#define APP_SECTION_SIZE (131072) +-#define APP_SECTION_PAGE_SIZE (512) +-#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) +- +-#define APPTABLE_SECTION_START (0x1E000) +-#define APPTABLE_SECTION_SIZE (8192) +-#define APPTABLE_SECTION_PAGE_SIZE (512) +-#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) +- +-#define BOOT_SECTION_START (0x20000) +-#define BOOT_SECTION_SIZE (8192) +-#define BOOT_SECTION_PAGE_SIZE (512) +-#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) +- +-#define DATAMEM_START (0x0000) +-#define DATAMEM_SIZE (16384) +-#define DATAMEM_PAGE_SIZE (0) +-#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) +- +-#define IO_START (0x0000) +-#define IO_SIZE (4096) +-#define IO_PAGE_SIZE (0) +-#define IO_END (IO_START + IO_SIZE - 1) +- +-#define MAPPED_EEPROM_START (0x1000) +-#define MAPPED_EEPROM_SIZE (2048) +-#define MAPPED_EEPROM_PAGE_SIZE (0) +-#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) +- +-#define INTERNAL_SRAM_START (0x2000) +-#define INTERNAL_SRAM_SIZE (8192) +-#define INTERNAL_SRAM_PAGE_SIZE (0) +-#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) +- +-#define EEPROM_START (0x0000) +-#define EEPROM_SIZE (2048) +-#define EEPROM_PAGE_SIZE (32) +-#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) +- +-#define FUSE_START (0x0000) +-#define FUSE_SIZE (6) +-#define FUSE_PAGE_SIZE (0) +-#define FUSE_END (FUSE_START + FUSE_SIZE - 1) +- +-#define LOCKBIT_START (0x0000) +-#define LOCKBIT_SIZE (1) +-#define LOCKBIT_PAGE_SIZE (0) +-#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) +- +-#define SIGNATURES_START (0x0000) +-#define SIGNATURES_SIZE (3) +-#define SIGNATURES_PAGE_SIZE (0) +-#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) +- +-#define USER_SIGNATURES_START (0x0000) +-#define USER_SIGNATURES_SIZE (512) +-#define USER_SIGNATURES_PAGE_SIZE (0) +-#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) +- +-#define PROD_SIGNATURES_START (0x0000) +-#define PROD_SIGNATURES_SIZE (52) +-#define PROD_SIGNATURES_PAGE_SIZE (0) +-#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) +- +-#define FLASHEND PROGMEM_END +-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +-#define RAMSTART INTERNAL_SRAM_START +-#define RAMSIZE INTERNAL_SRAM_SIZE +-#define RAMEND INTERNAL_SRAM_END +-#define XRAMSTART EXTERNAL_SRAM_START +-#define XRAMSIZE EXTERNAL_SRAM_SIZE +-#define XRAMEND INTERNAL_SRAM_END +-#define E2END EEPROM_END +-#define E2PAGESIZE EEPROM_PAGE_SIZE +- +- +-/* ========== Fuses ========== */ +-#define FUSE_MEMORY_SIZE 6 +- +-/* Fuse Byte 0 */ +-#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ +-#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ +-#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ +-#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ +-#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ +-#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ +-#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ +-#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ +-#define FUSE0_DEFAULT (0xFF) +- +-/* Fuse Byte 1 */ +-#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +-#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +-#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +-#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +-#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +-#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +-#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +-#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +-#define FUSE1_DEFAULT (0xFF) +- +-/* Fuse Byte 2 */ +-#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +-#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +-#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +-#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +-#define FUSE2_DEFAULT (0xFF) +- +-/* Fuse Byte 3 Reserved */ +- +-/* Fuse Byte 4 */ +-#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ +-#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +-#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +-#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +-#define FUSE4_DEFAULT (0xFF) +- +-/* Fuse Byte 5 */ +-#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +-#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +-#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +-#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +-#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +-#define FUSE5_DEFAULT (0xFF) +- +- +-/* ========== Lock Bits ========== */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_BITS_EXIST +-#define __BOOT_LOCK_BOOT_BITS_EXIST +- +- +-/* ========== Signature ========== */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x97 +-#define SIGNATURE_2 0x42 +- +- +-#endif /* _AVR_ATxmega128A3_H_ */ +- ++/* Copyright (c) 2009-2010 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iox128a3.h 2200 2010-12-14 04:24:24Z arcanum $ */ ++ ++/* avr/iox128a3.h - definitions for ATxmega128A3 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox128a3.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATxmega128A3_H_ ++#define _AVR_ATxmega128A3_H_ 1 ++ ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++} CLK_t; ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t PRPB; /* Power Reduction Port B */ ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ ++} CLK_RTCSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control REgister */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t reserved_0x07; ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Channel */ ++typedef struct DMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Address Control */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ ++ register8_t REPCNT; /* Channel Repeat Count */ ++ register8_t reserved_0x07; ++ register8_t SRCADDR0; /* Channel Source Address 0 */ ++ register8_t SRCADDR1; /* Channel Source Address 1 */ ++ register8_t SRCADDR2; /* Channel Source Address 2 */ ++ register8_t reserved_0x0B; ++ register8_t DESTADDR0; /* Channel Destination Address 0 */ ++ register8_t DESTADDR1; /* Channel Destination Address 1 */ ++ register8_t DESTADDR2; /* Channel Destination Address 2 */ ++ register8_t reserved_0x0F; ++} DMA_CH_t; ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Controller */ ++typedef struct DMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ DMA_CH_t CH0; /* DMA Channel 0 */ ++ DMA_CH_t CH1; /* DMA Channel 1 */ ++ DMA_CH_t CH2; /* DMA Channel 2 */ ++ DMA_CH_t CH3; /* DMA Channel 3 */ ++} DMA_t; ++ ++/* Burst mode */ ++typedef enum DMA_CH_BURSTLEN_enum ++{ ++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ ++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ ++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ ++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ ++} DMA_CH_BURSTLEN_t; ++ ++/* Source address reload mode */ ++typedef enum DMA_CH_SRCRELOAD_enum ++{ ++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ ++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ ++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ ++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ ++} DMA_CH_SRCRELOAD_t; ++ ++/* Source addressing mode */ ++typedef enum DMA_CH_SRCDIR_enum ++{ ++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ ++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ ++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ ++} DMA_CH_SRCDIR_t; ++ ++/* Destination adress reload mode */ ++typedef enum DMA_CH_DESTRELOAD_enum ++{ ++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ ++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ ++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ ++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ ++} DMA_CH_DESTRELOAD_t; ++ ++/* Destination adressing mode */ ++typedef enum DMA_CH_DESTDIR_enum ++{ ++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ ++} DMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum DMA_CH_TRIGSRC_enum ++{ ++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ ++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ ++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ ++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ ++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ ++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ ++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ ++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ ++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ ++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ ++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ ++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ ++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ ++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ ++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ ++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ ++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ ++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ ++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ ++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ ++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ ++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ ++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ ++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ ++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ ++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ ++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ ++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ ++} DMA_CH_TRIGSRC_t; ++ ++/* Double buffering mode */ ++typedef enum DMA_DBUFMODE_enum ++{ ++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ ++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ ++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ ++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ ++} DMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum DMA_PRIMODE_enum ++{ ++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ ++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ ++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ ++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ ++} DMA_PRIMODE_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_ERRINTLVL_enum ++{ ++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ ++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ ++} DMA_CH_ERRINTLVL_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_TRNINTLVL_enum ++{ ++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ ++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ ++} DMA_CH_TRNINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ ++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ ++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ ++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t CH4CTRL; /* Channel 4 Control Register */ ++ register8_t CH5CTRL; /* Channel 5 Control Register */ ++ register8_t CH6CTRL; /* Channel 6 Control Register */ ++ register8_t CH7CTRL; /* Channel 7 Control Register */ ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ ++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ ++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ ++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ ++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ ++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ ++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ ++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ ++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ ++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ ++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ ++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ ++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ ++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ ++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ ++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ ++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ ++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t FUSEBYTE0; /* JTAG User ID */ ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ ++ register8_t reserved_0x01; ++ register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ ++ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ ++ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ ++ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++} NVM_PROD_SIGNATURES_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++} NVM_LB_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brown Out Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ ++ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Comparator 0 Control */ ++ register8_t AC1CTRL; /* Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t reserved_0x6; ++ register8_t reserved_0x7; ++} ADC_CH_t; ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ _WORDREGISTER(CH1RES); /* Channel 1 Result */ ++ _WORDREGISTER(CH2RES); /* Channel 2 Result */ ++ _WORDREGISTER(CH3RES); /* Channel 3 Result */ ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++ ADC_CH_t CH1; /* ADC Channel 1 */ ++ ADC_CH_t CH2; /* ADC Channel 2 */ ++ ADC_CH_t CH3; /* ADC Channel 3 */ ++} ADC_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++} ADC_REFSEL_t; ++ ++/* Channel sweep selection */ ++typedef enum ADC_SWEEP_enum ++{ ++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ ++} ADC_SWEEP_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ++ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* DMA request selection */ ++typedef enum ADC_DMASEL_enum ++{ ++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ ++} ADC_DMASEL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DAC - Digital/Analog Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Digital-to-Analog Converter */ ++typedef struct DAC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t EVCTRL; /* Event Input Control */ ++ register8_t TIMCTRL; /* Timing Control */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t GAINCAL; /* Gain Calibration */ ++ register8_t OFFSETCAL; /* Offset Calibration */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ ++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ ++} DAC_t; ++ ++/* Output channel selection */ ++typedef enum DAC_CHSEL_enum ++{ ++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ ++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ ++} DAC_CHSEL_t; ++ ++/* Reference voltage selection */ ++typedef enum DAC_REFSEL_enum ++{ ++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ ++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ ++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ ++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ ++} DAC_REFSEL_t; ++ ++/* Event channel selection */ ++typedef enum DAC_EVSEL_enum ++{ ++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ ++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ ++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ ++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ ++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ ++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ ++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ ++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ ++} DAC_EVSEL_t; ++ ++/* Conversion interval */ ++typedef enum DAC_CONINTVAL_enum ++{ ++ DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ ++ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ ++ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ ++ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ ++ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ ++ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ ++ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ ++ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ ++} DAC_CONINTVAL_t; ++ ++/* Refresh rate */ ++typedef enum DAC_REFRESH_enum ++{ ++ DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ ++ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ ++ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ ++ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ ++ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ ++ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ ++ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ ++ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ ++ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ ++ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ ++ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ ++ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ ++ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ ++ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ ++} DAC_REFRESH_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Clounter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* EBI Chip Select Module */ ++typedef struct EBI_CS_struct ++{ ++ register8_t CTRLA; /* Chip Select Control Register A */ ++ register8_t CTRLB; /* Chip Select Control Register B */ ++ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ ++} EBI_CS_t; ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* External Bus Interface */ ++typedef struct EBI_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ ++ register8_t reserved_0x02; ++ register8_t reserved_0x03; ++ _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ ++ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ ++ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ ++ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ EBI_CS_t CS0; /* Chip Select 0 */ ++ EBI_CS_t CS1; /* Chip Select 1 */ ++ EBI_CS_t CS2; /* Chip Select 2 */ ++ EBI_CS_t CS3; /* Chip Select 3 */ ++} EBI_t; ++ ++/* Chip Select adress space */ ++typedef enum EBI_CS_ASIZE_enum ++{ ++ EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ ++ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ ++ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ ++ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ ++ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ ++ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ ++ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ ++ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ ++ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ ++ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ ++ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ ++ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ ++ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ ++ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ ++ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ ++ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ ++ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ ++} EBI_CS_ASIZE_t; ++ ++/* */ ++typedef enum EBI_CS_SRWS_enum ++{ ++ EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_CS_SRWS_t; ++ ++/* Chip Select address mode */ ++typedef enum EBI_CS_MODE_enum ++{ ++ EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ ++ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ ++ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ ++ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ ++} EBI_CS_MODE_t; ++ ++/* Chip Select SDRAM mode */ ++typedef enum EBI_CS_SDMODE_enum ++{ ++ EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ ++ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ ++} EBI_CS_SDMODE_t; ++ ++/* */ ++typedef enum EBI_SDDATAW_enum ++{ ++ EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ ++ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ ++} EBI_SDDATAW_t; ++ ++/* */ ++typedef enum EBI_LPCMODE_enum ++{ ++ EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ ++ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ ++} EBI_LPCMODE_t; ++ ++/* */ ++typedef enum EBI_SRMODE_enum ++{ ++ EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ ++ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ ++ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ ++ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ ++} EBI_SRMODE_t; ++ ++/* */ ++typedef enum EBI_IFMODE_enum ++{ ++ EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ ++ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ ++ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ ++ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ ++} EBI_IFMODE_t; ++ ++/* */ ++typedef enum EBI_SDCOL_enum ++{ ++ EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ ++ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ ++ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ ++ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ ++} EBI_SDCOL_t; ++ ++/* */ ++typedef enum EBI_MRDLY_enum ++{ ++ EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_MRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCYCDLY_enum ++{ ++ EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ROWCYCDLY_t; ++ ++/* */ ++typedef enum EBI_RPDLY_enum ++{ ++ EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_RPDLY_t; ++ ++/* */ ++typedef enum EBI_WRDLY_enum ++{ ++ EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_WRDLY_t; ++ ++/* */ ++typedef enum EBI_ESRDLY_enum ++{ ++ EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ESRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCOLDLY_enum ++{ ++ EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_ROWCOLDLY_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++} PORTCFG_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Virtual Port 0 Mapping */ ++typedef enum PORTCFG_VP0MAP_enum ++{ ++ PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP0MAP_t; ++ ++/* Virtual Port 1 Mapping */ ++typedef enum PORTCFG_VP1MAP_enum ++{ ++ PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP1MAP_t; ++ ++/* Virtual Port 2 Mapping */ ++typedef enum PORTCFG_VP2MAP_enum ++{ ++ PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP2MAP_t; ++ ++/* Virtual Port 3 Mapping */ ++typedef enum PORTCFG_VP3MAP_enum ++{ ++ PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP3MAP_t; ++ ++/* Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x05; ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AES - AES Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* AES Module */ ++typedef struct AES_struct ++{ ++ register8_t CTRL; /* AES Control Register */ ++ register8_t STATUS; /* AES Status Register */ ++ register8_t STATE; /* AES State Register */ ++ register8_t KEY; /* AES Key Register */ ++ register8_t INTCTRL; /* AES Interrupt Control Register */ ++} AES_t; ++ ++/* Interrupt level */ ++typedef enum AES_INTLVL_enum ++{ ++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} AES_INTLVL_t; ++ ++ ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset Controller */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ ++#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ ++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ ++#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ ++#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ ++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ ++#define PORTA (*(PORT_t *) 0x0600) /* Port A */ ++#define PORTB (*(PORT_t *) 0x0620) /* Port B */ ++#define PORTC (*(PORT_t *) 0x0640) /* Port C */ ++#define PORTD (*(PORT_t *) 0x0660) /* Port D */ ++#define PORTE (*(PORT_t *) 0x0680) /* Port E */ ++#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ ++#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ ++#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ ++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ ++#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ ++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ ++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ ++#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ ++#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ ++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ ++#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ ++#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ ++#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ ++#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ ++#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ ++#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ ++#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++#define GPIO_GPIOR4 _SFR_MEM8(0x0004) ++#define GPIO_GPIOR5 _SFR_MEM8(0x0005) ++#define GPIO_GPIOR6 _SFR_MEM8(0x0006) ++#define GPIO_GPIOR7 _SFR_MEM8(0x0007) ++#define GPIO_GPIOR8 _SFR_MEM8(0x0008) ++#define GPIO_GPIOR9 _SFR_MEM8(0x0009) ++#define GPIO_GPIORA _SFR_MEM8(0x000A) ++#define GPIO_GPIORB _SFR_MEM8(0x000B) ++#define GPIO_GPIORC _SFR_MEM8(0x000C) ++#define GPIO_GPIORD _SFR_MEM8(0x000D) ++#define GPIO_GPIORE _SFR_MEM8(0x000E) ++#define GPIO_GPIORF _SFR_MEM8(0x000F) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++#define GPIO_GPIO4 _SFR_MEM8(0x0004) ++#define GPIO_GPIO5 _SFR_MEM8(0x0005) ++#define GPIO_GPIO6 _SFR_MEM8(0x0006) ++#define GPIO_GPIO7 _SFR_MEM8(0x0007) ++#define GPIO_GPIO8 _SFR_MEM8(0x0008) ++#define GPIO_GPIO9 _SFR_MEM8(0x0009) ++#define GPIO_GPIOA _SFR_MEM8(0x000A) ++#define GPIO_GPIOB _SFR_MEM8(0x000B) ++#define GPIO_GPIOC _SFR_MEM8(0x000C) ++#define GPIO_GPIOD _SFR_MEM8(0x000D) ++#define GPIO_GPIOE _SFR_MEM8(0x000E) ++#define GPIO_GPIOF _SFR_MEM8(0x000F) ++ ++/* VPORT0 - Virtual Port 0 */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT1 - Virtual Port 1 */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT2 - Virtual Port 2 */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT3 - Virtual Port 3 */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU Registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator Control */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPB _SFR_MEM8(0x0072) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset Controller */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - Port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++ ++/* AES - AES Crypto Module */ ++#define AES_CTRL _SFR_MEM8(0x00C0) ++#define AES_STATUS _SFR_MEM8(0x00C1) ++#define AES_STATE _SFR_MEM8(0x00C2) ++#define AES_KEY _SFR_MEM8(0x00C3) ++#define AES_INTCTRL _SFR_MEM8(0x00C4) ++ ++/* DMA - DMA Controller */ ++#define DMA_CTRL _SFR_MEM8(0x0100) ++#define DMA_INTFLAGS _SFR_MEM8(0x0103) ++#define DMA_STATUS _SFR_MEM8(0x0104) ++#define DMA_TEMP _SFR_MEM16(0x0106) ++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) ++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) ++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) ++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) ++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) ++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) ++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) ++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) ++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) ++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) ++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) ++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) ++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) ++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) ++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) ++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) ++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) ++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) ++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) ++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) ++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) ++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) ++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) ++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) ++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) ++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) ++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) ++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) ++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) ++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) ++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) ++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) ++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) ++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) ++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) ++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) ++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) ++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) ++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) ++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) ++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) ++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH4MUX _SFR_MEM8(0x0184) ++#define EVSYS_CH5MUX _SFR_MEM8(0x0185) ++#define EVSYS_CH6MUX _SFR_MEM8(0x0186) ++#define EVSYS_CH7MUX _SFR_MEM8(0x0187) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) ++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) ++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) ++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non Volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADCA - Analog to Digital Converter A */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CH1RES _SFR_MEM16(0x0212) ++#define ADCA_CH2RES _SFR_MEM16(0x0214) ++#define ADCA_CH3RES _SFR_MEM16(0x0216) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) ++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) ++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) ++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) ++#define ADCA_CH1_RES _SFR_MEM16(0x022C) ++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) ++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) ++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) ++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) ++#define ADCA_CH2_RES _SFR_MEM16(0x0234) ++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) ++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) ++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) ++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) ++#define ADCA_CH3_RES _SFR_MEM16(0x023C) ++ ++/* ADCB - Analog to Digital Converter B */ ++#define ADCB_CTRLA _SFR_MEM8(0x0240) ++#define ADCB_CTRLB _SFR_MEM8(0x0241) ++#define ADCB_REFCTRL _SFR_MEM8(0x0242) ++#define ADCB_EVCTRL _SFR_MEM8(0x0243) ++#define ADCB_PRESCALER _SFR_MEM8(0x0244) ++#define ADCB_INTFLAGS _SFR_MEM8(0x0246) ++#define ADCB_CAL _SFR_MEM16(0x024C) ++#define ADCB_CH0RES _SFR_MEM16(0x0250) ++#define ADCB_CH1RES _SFR_MEM16(0x0252) ++#define ADCB_CH2RES _SFR_MEM16(0x0254) ++#define ADCB_CH3RES _SFR_MEM16(0x0256) ++#define ADCB_CMP _SFR_MEM16(0x0258) ++#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) ++#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) ++#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) ++#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) ++#define ADCB_CH0_RES _SFR_MEM16(0x0264) ++#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) ++#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) ++#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) ++#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) ++#define ADCB_CH1_RES _SFR_MEM16(0x026C) ++#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) ++#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) ++#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) ++#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) ++#define ADCB_CH2_RES _SFR_MEM16(0x0274) ++#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) ++#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) ++#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) ++#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) ++#define ADCB_CH3_RES _SFR_MEM16(0x027C) ++ ++/* DACB - Digital to Analog Converter B */ ++#define DACB_CTRLA _SFR_MEM8(0x0320) ++#define DACB_CTRLB _SFR_MEM8(0x0321) ++#define DACB_CTRLC _SFR_MEM8(0x0322) ++#define DACB_EVCTRL _SFR_MEM8(0x0323) ++#define DACB_TIMCTRL _SFR_MEM8(0x0324) ++#define DACB_STATUS _SFR_MEM8(0x0325) ++#define DACB_GAINCAL _SFR_MEM8(0x0328) ++#define DACB_OFFSETCAL _SFR_MEM8(0x0329) ++#define DACB_CH0DATA _SFR_MEM16(0x0338) ++#define DACB_CH1DATA _SFR_MEM16(0x033A) ++ ++/* ACA - Analog Comparator A */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* ACB - Analog Comparator B */ ++#define ACB_AC0CTRL _SFR_MEM8(0x0390) ++#define ACB_AC1CTRL _SFR_MEM8(0x0391) ++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) ++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) ++#define ACB_CTRLA _SFR_MEM8(0x0394) ++#define ACB_CTRLB _SFR_MEM8(0x0395) ++#define ACB_WINCTRL _SFR_MEM8(0x0396) ++#define ACB_STATUS _SFR_MEM8(0x0397) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWIC - Two-Wire Interface C */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWIE - Two-Wire Interface E */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* PORTA - Port A */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORTB - Port B */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORTC - Port C */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORTD - Port D */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORTE - Port E */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORTF - Port F */ ++#define PORTF_DIR _SFR_MEM8(0x06A0) ++#define PORTF_DIRSET _SFR_MEM8(0x06A1) ++#define PORTF_DIRCLR _SFR_MEM8(0x06A2) ++#define PORTF_DIRTGL _SFR_MEM8(0x06A3) ++#define PORTF_OUT _SFR_MEM8(0x06A4) ++#define PORTF_OUTSET _SFR_MEM8(0x06A5) ++#define PORTF_OUTCLR _SFR_MEM8(0x06A6) ++#define PORTF_OUTTGL _SFR_MEM8(0x06A7) ++#define PORTF_IN _SFR_MEM8(0x06A8) ++#define PORTF_INTCTRL _SFR_MEM8(0x06A9) ++#define PORTF_INT0MASK _SFR_MEM8(0x06AA) ++#define PORTF_INT1MASK _SFR_MEM8(0x06AB) ++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) ++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) ++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) ++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) ++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) ++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) ++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) ++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) ++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) ++ ++/* PORTR - Port R */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TCC0 - Timer/Counter C0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TCC1 - Timer/Counter C1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEXC - Advanced Waveform Extension C */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRESC - High-Resolution Extension C */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ ++#define USARTC1_DATA _SFR_MEM8(0x08B0) ++#define USARTC1_STATUS _SFR_MEM8(0x08B1) ++#define USARTC1_CTRLA _SFR_MEM8(0x08B3) ++#define USARTC1_CTRLB _SFR_MEM8(0x08B4) ++#define USARTC1_CTRLC _SFR_MEM8(0x08B5) ++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) ++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) ++ ++/* SPIC - Serial Peripheral Interface C */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TCD0 - Timer/Counter D0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TCD1 - Timer/Counter D1 */ ++#define TCD1_CTRLA _SFR_MEM8(0x0940) ++#define TCD1_CTRLB _SFR_MEM8(0x0941) ++#define TCD1_CTRLC _SFR_MEM8(0x0942) ++#define TCD1_CTRLD _SFR_MEM8(0x0943) ++#define TCD1_CTRLE _SFR_MEM8(0x0944) ++#define TCD1_INTCTRLA _SFR_MEM8(0x0946) ++#define TCD1_INTCTRLB _SFR_MEM8(0x0947) ++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) ++#define TCD1_CTRLFSET _SFR_MEM8(0x0949) ++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) ++#define TCD1_CTRLGSET _SFR_MEM8(0x094B) ++#define TCD1_INTFLAGS _SFR_MEM8(0x094C) ++#define TCD1_TEMP _SFR_MEM8(0x094F) ++#define TCD1_CNT _SFR_MEM16(0x0960) ++#define TCD1_PER _SFR_MEM16(0x0966) ++#define TCD1_CCA _SFR_MEM16(0x0968) ++#define TCD1_CCB _SFR_MEM16(0x096A) ++#define TCD1_PERBUF _SFR_MEM16(0x0976) ++#define TCD1_CCABUF _SFR_MEM16(0x0978) ++#define TCD1_CCBBUF _SFR_MEM16(0x097A) ++ ++/* HIRESD - High-Resolution Extension D */ ++#define HIRESD_CTRLA _SFR_MEM8(0x0990) ++ ++/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ ++#define USARTD1_DATA _SFR_MEM8(0x09B0) ++#define USARTD1_STATUS _SFR_MEM8(0x09B1) ++#define USARTD1_CTRLA _SFR_MEM8(0x09B3) ++#define USARTD1_CTRLB _SFR_MEM8(0x09B4) ++#define USARTD1_CTRLC _SFR_MEM8(0x09B5) ++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) ++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) ++ ++/* SPID - Serial Peripheral Interface D */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TCE0 - Timer/Counter E0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* TCE1 - Timer/Counter E1 */ ++#define TCE1_CTRLA _SFR_MEM8(0x0A40) ++#define TCE1_CTRLB _SFR_MEM8(0x0A41) ++#define TCE1_CTRLC _SFR_MEM8(0x0A42) ++#define TCE1_CTRLD _SFR_MEM8(0x0A43) ++#define TCE1_CTRLE _SFR_MEM8(0x0A44) ++#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) ++#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) ++#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) ++#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) ++#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) ++#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) ++#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) ++#define TCE1_TEMP _SFR_MEM8(0x0A4F) ++#define TCE1_CNT _SFR_MEM16(0x0A60) ++#define TCE1_PER _SFR_MEM16(0x0A66) ++#define TCE1_CCA _SFR_MEM16(0x0A68) ++#define TCE1_CCB _SFR_MEM16(0x0A6A) ++#define TCE1_PERBUF _SFR_MEM16(0x0A76) ++#define TCE1_CCABUF _SFR_MEM16(0x0A78) ++#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) ++ ++/* AWEXE - Advanced Waveform Extension E */ ++#define AWEXE_CTRL _SFR_MEM8(0x0A80) ++#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) ++#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) ++#define AWEXE_STATUS _SFR_MEM8(0x0A84) ++#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) ++#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) ++#define AWEXE_DTLS _SFR_MEM8(0x0A88) ++#define AWEXE_DTHS _SFR_MEM8(0x0A89) ++#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) ++#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) ++#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) ++ ++/* HIRESE - High-Resolution Extension E */ ++#define HIRESE_CTRLA _SFR_MEM8(0x0A90) ++ ++/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ ++#define USARTE1_DATA _SFR_MEM8(0x0AB0) ++#define USARTE1_STATUS _SFR_MEM8(0x0AB1) ++#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) ++#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) ++#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) ++#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) ++#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) ++ ++/* SPIE - Serial Peripheral Interface E */ ++#define SPIE_CTRL _SFR_MEM8(0x0AC0) ++#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) ++#define SPIE_STATUS _SFR_MEM8(0x0AC2) ++#define SPIE_DATA _SFR_MEM8(0x0AC3) ++ ++/* TCF0 - Timer/Counter F0 */ ++#define TCF0_CTRLA _SFR_MEM8(0x0B00) ++#define TCF0_CTRLB _SFR_MEM8(0x0B01) ++#define TCF0_CTRLC _SFR_MEM8(0x0B02) ++#define TCF0_CTRLD _SFR_MEM8(0x0B03) ++#define TCF0_CTRLE _SFR_MEM8(0x0B04) ++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) ++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) ++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) ++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) ++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF0_TEMP _SFR_MEM8(0x0B0F) ++#define TCF0_CNT _SFR_MEM16(0x0B20) ++#define TCF0_PER _SFR_MEM16(0x0B26) ++#define TCF0_CCA _SFR_MEM16(0x0B28) ++#define TCF0_CCB _SFR_MEM16(0x0B2A) ++#define TCF0_CCC _SFR_MEM16(0x0B2C) ++#define TCF0_CCD _SFR_MEM16(0x0B2E) ++#define TCF0_PERBUF _SFR_MEM16(0x0B36) ++#define TCF0_CCABUF _SFR_MEM16(0x0B38) ++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) ++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) ++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) ++ ++/* HIRESF - High-Resolution Extension F */ ++#define HIRESF_CTRLA _SFR_MEM8(0x0B90) ++ ++/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ ++#define USARTF0_DATA _SFR_MEM8(0x0BA0) ++#define USARTF0_STATUS _SFR_MEM8(0x0BA1) ++#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) ++#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) ++#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) ++#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) ++#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) ++ ++/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ ++#define USARTF1_DATA _SFR_MEM8(0x0BB0) ++#define USARTF1_STATUS _SFR_MEM8(0x0BB1) ++#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) ++#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) ++#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) ++#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) ++#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) ++ ++/* SPIF - Serial Peripheral Interface F */ ++#define SPIF_CTRL _SFR_MEM8(0x0BC0) ++#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) ++#define SPIF_STATUS _SFR_MEM8(0x0BC2) ++#define SPIF_DATA _SFR_MEM8(0x0BC3) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR1 bit masks and bit positions */ ++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ ++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ ++ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ ++ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ ++#define PR_EBI_bp 3 /* External Bus Interface bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ ++#define PR_DAC_bp 2 /* Port A DAC bit position. */ ++ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++ ++/* PR.PRPB bit masks and bit positions */ ++/* PR_DAC_bm Predefined. */ ++/* PR_DAC_bp Predefined. */ ++ ++/* PR_ADC_bm Predefined. */ ++/* PR_ADC_bp Predefined. */ ++ ++/* PR_AC_bm Predefined. */ ++/* PR_AC_bp Predefined. */ ++ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ ++ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ ++ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ ++ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ ++#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ ++ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ ++ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ ++ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ ++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ ++ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++ ++/* DMA - DMA Controller */ ++/* DMA_CH.CTRLA bit masks and bit positions */ ++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ ++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ ++ ++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ ++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ ++ ++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ ++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ ++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ ++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ ++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ ++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ ++ ++ ++/* DMA_CH.CTRLB bit masks and bit positions */ ++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ ++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ ++ ++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ ++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ ++ ++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ ++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ ++ ++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ ++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ ++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ ++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ ++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ ++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ ++ ++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ ++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ ++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ ++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ ++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ ++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ ++ ++ ++/* DMA_CH.ADDRCTRL bit masks and bit positions */ ++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ ++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ ++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ ++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ ++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ ++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ ++ ++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ ++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ ++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ ++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ ++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ ++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ ++ ++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ ++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ ++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ ++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ ++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ ++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ ++ ++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ ++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ ++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ ++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ ++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ ++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ ++ ++ ++/* DMA_CH.TRIGSRC bit masks and bit positions */ ++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++ ++/* DMA.CTRL bit masks and bit positions */ ++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define DMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define DMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ ++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ ++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ ++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ ++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ ++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ ++ ++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ ++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ ++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ ++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ ++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ ++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ ++ ++ ++/* DMA.INTFLAGS bit masks and bit positions */ ++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++ ++/* DMA.STATUS bit masks and bit positions */ ++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ ++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ ++ ++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ ++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ ++ ++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ ++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ ++ ++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ ++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ ++ ++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ ++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ ++ ++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ ++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ ++ ++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ ++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ ++ ++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ ++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ ++ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH4MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH5MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH6MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH7MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM_gm Predefined. */ ++/* EVSYS_QDIRM_gp Predefined. */ ++/* EVSYS_QDIRM0_bm Predefined. */ ++/* EVSYS_QDIRM0_bp Predefined. */ ++/* EVSYS_QDIRM1_bm Predefined. */ ++/* EVSYS_QDIRM1_bp Predefined. */ ++ ++/* EVSYS_QDIEN_bm Predefined. */ ++/* EVSYS_QDIEN_bp Predefined. */ ++ ++/* EVSYS_QDEN_bm Predefined. */ ++/* EVSYS_QDEN_bp Predefined. */ ++ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH4CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM_gm Predefined. */ ++/* EVSYS_QDIRM_gp Predefined. */ ++/* EVSYS_QDIRM0_bm Predefined. */ ++/* EVSYS_QDIRM0_bp Predefined. */ ++/* EVSYS_QDIRM1_bm Predefined. */ ++/* EVSYS_QDIRM1_bp Predefined. */ ++ ++/* EVSYS_QDIEN_bm Predefined. */ ++/* EVSYS_QDIEN_bp Predefined. */ ++ ++/* EVSYS_QDEN_bm Predefined. */ ++/* EVSYS_QDEN_bp Predefined. */ ++ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH5CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH6CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH7CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0xFF /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ ++#define NVM_CMD7_bp 7 /* Command bit 7 position. */ ++ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ ++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ ++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ ++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ ++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ ++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ ++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ ++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ ++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ ++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ ++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ ++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ ++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ ++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ ++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ ++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ ++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ ++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ ++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ ++#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ ++ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ ++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ ++ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ ++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE_gm Predefined. */ ++/* AC_INTMODE_gp Predefined. */ ++/* AC_INTMODE0_bm Predefined. */ ++/* AC_INTMODE0_bp Predefined. */ ++/* AC_INTMODE1_bm Predefined. */ ++/* AC_INTMODE1_bp Predefined. */ ++ ++/* AC_INTLVL_gm Predefined. */ ++/* AC_INTLVL_gp Predefined. */ ++/* AC_INTLVL0_bm Predefined. */ ++/* AC_INTLVL0_bp Predefined. */ ++/* AC_INTLVL1_bm Predefined. */ ++/* AC_INTLVL1_bp Predefined. */ ++ ++/* AC_HSMODE_bm Predefined. */ ++/* AC_HSMODE_bp Predefined. */ ++ ++/* AC_HYSMODE_gm Predefined. */ ++/* AC_HYSMODE_gp Predefined. */ ++/* AC_HYSMODE0_bm Predefined. */ ++/* AC_HYSMODE0_bp Predefined. */ ++/* AC_HYSMODE1_bm Predefined. */ ++/* AC_HYSMODE1_bp Predefined. */ ++ ++/* AC_ENABLE_bm Predefined. */ ++/* AC_ENABLE_bp Predefined. */ ++ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS_gm Predefined. */ ++/* AC_MUXPOS_gp Predefined. */ ++/* AC_MUXPOS0_bm Predefined. */ ++/* AC_MUXPOS0_bp Predefined. */ ++/* AC_MUXPOS1_bm Predefined. */ ++/* AC_MUXPOS1_bp Predefined. */ ++/* AC_MUXPOS2_bm Predefined. */ ++/* AC_MUXPOS2_bp Predefined. */ ++ ++/* AC_MUXNEG_gm Predefined. */ ++/* AC_MUXNEG_gp Predefined. */ ++/* AC_MUXNEG0_bm Predefined. */ ++/* AC_MUXNEG0_bp Predefined. */ ++/* AC_MUXNEG1_bm Predefined. */ ++/* AC_MUXNEG1_bp Predefined. */ ++/* AC_MUXNEG2_bm Predefined. */ ++/* AC_MUXNEG2_bp Predefined. */ ++ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ ++ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ ++ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ ++ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ ++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ ++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ ++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ ++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ ++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ ++ ++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ ++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ ++ ++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ ++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ ++ ++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ ++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ ++ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ ++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ ++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ ++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ ++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ ++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ ++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ ++ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ ++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ ++ ++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ ++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ ++ ++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ ++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ ++ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++ ++/* DAC - Digital/Analog Converter */ ++/* DAC.CTRLA bit masks and bit positions */ ++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ ++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ ++ ++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ ++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ ++ ++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ ++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ ++ ++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ ++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ ++ ++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define DAC_ENABLE_bp 0 /* Enable bit position. */ ++ ++ ++/* DAC.CTRLB bit masks and bit positions */ ++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ ++#define DAC_CHSEL_gp 5 /* Channel Select group position. */ ++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ ++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ ++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ ++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ ++ ++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ ++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ ++ ++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ ++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ ++ ++ ++/* DAC.CTRLC bit masks and bit positions */ ++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ ++#define DAC_REFSEL_gp 3 /* Reference Select group position. */ ++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ ++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ ++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ ++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ ++ ++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ ++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ ++ ++ ++/* DAC.EVCTRL bit masks and bit positions */ ++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ ++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ ++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ ++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ ++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ ++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ ++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ ++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ ++ ++ ++/* DAC.TIMCTRL bit masks and bit positions */ ++#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ ++#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ ++#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ ++#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ ++#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ ++#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ ++#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ ++#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ ++ ++#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ ++#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ ++#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ ++#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ ++#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ ++#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ ++#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ ++#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ ++#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ ++#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ ++ ++ ++/* DAC.STATUS bit masks and bit positions */ ++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ ++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ ++ ++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ ++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ ++ ++ ++/* RTC - Real-Time Clounter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* EBI - External Bus Interface */ ++/* EBI_CS.CTRLA bit masks and bit positions */ ++#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ ++#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ ++#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ ++#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ ++#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ ++#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ ++#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ ++#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ ++#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ ++#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ ++#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ ++#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ ++ ++#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ ++#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ ++#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ ++#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ ++#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ ++#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ ++ ++ ++/* EBI_CS.CTRLB bit masks and bit positions */ ++#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ ++#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ ++#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ ++#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ ++#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ ++#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ ++#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ ++#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ ++ ++#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ ++#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ ++ ++#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ ++#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ ++ ++#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ ++#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ ++#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ ++#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ ++#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ ++#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ ++ ++ ++/* EBI.CTRL bit masks and bit positions */ ++#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ ++#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ ++#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ ++#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ ++#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ ++#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ ++ ++#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ ++#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ ++#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ ++#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ ++#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ ++#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ ++ ++#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ ++#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ ++#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ ++#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ ++#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ ++#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ ++ ++#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ ++#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ ++#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ ++#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ ++#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ ++#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLA bit masks and bit positions */ ++#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ ++#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ ++ ++#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ ++#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ ++ ++#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ ++#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ ++#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ ++#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ ++#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ ++#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLB bit masks and bit positions */ ++#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ ++#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ ++#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ ++#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ ++#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ ++#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ ++ ++#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ ++#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ ++#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ ++#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ ++#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ ++#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ ++#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ ++#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ ++ ++#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ ++#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ ++#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ ++#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ ++#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ ++#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ ++#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ ++#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ ++ ++ ++/* EBI.SDRAMCTRLC bit masks and bit positions */ ++#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ ++#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ ++#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ ++#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ ++#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ ++#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ ++ ++#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ ++#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ ++#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ ++#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ ++#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ ++#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ ++#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ ++#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ ++ ++#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ ++#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ ++#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ ++#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ ++#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ ++#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ ++#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ ++#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ ++ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ ++#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++ ++/* PORT - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ ++#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ ++ ++#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD_gm Predefined. */ ++/* TC0_CMD_gp Predefined. */ ++/* TC0_CMD0_bm Predefined. */ ++/* TC0_CMD0_bp Predefined. */ ++/* TC0_CMD1_bm Predefined. */ ++/* TC0_CMD1_bp Predefined. */ ++ ++/* TC0_LUPD_bm Predefined. */ ++/* TC0_LUPD_bp Predefined. */ ++ ++/* TC0_DIR_bm Predefined. */ ++/* TC0_DIR_bp Predefined. */ ++ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV_bm Predefined. */ ++/* TC0_CCDBV_bp Predefined. */ ++ ++/* TC0_CCCBV_bm Predefined. */ ++/* TC0_CCCBV_bp Predefined. */ ++ ++/* TC0_CCBBV_bm Predefined. */ ++/* TC0_CCBBV_bp Predefined. */ ++ ++/* TC0_CCABV_bm Predefined. */ ++/* TC0_CCABV_bp Predefined. */ ++ ++/* TC0_PERBV_bm Predefined. */ ++/* TC0_PERBV_bp Predefined. */ ++ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ ++#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ ++ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD_gm Predefined. */ ++/* TC1_CMD_gp Predefined. */ ++/* TC1_CMD0_bm Predefined. */ ++/* TC1_CMD0_bp Predefined. */ ++/* TC1_CMD1_bm Predefined. */ ++/* TC1_CMD1_bp Predefined. */ ++ ++/* TC1_LUPD_bm Predefined. */ ++/* TC1_LUPD_bp Predefined. */ ++ ++/* TC1_DIR_bm Predefined. */ ++/* TC1_DIR_bp Predefined. */ ++ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV_bm Predefined. */ ++/* TC1_CCBBV_bp Predefined. */ ++ ++/* TC1_CCABV_bm Predefined. */ ++/* TC1_CCABV_bp Predefined. */ ++ ++/* TC1_PERBV_bm Predefined. */ ++/* TC1_PERBV_bp Predefined. */ ++ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++ ++/* HIRES.CTRL bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL_gm Predefined. */ ++/* USART_BSEL_gp Predefined. */ ++/* USART_BSEL0_bm Predefined. */ ++/* USART_BSEL0_bp Predefined. */ ++/* USART_BSEL1_bm Predefined. */ ++/* USART_BSEL1_bp Predefined. */ ++/* USART_BSEL2_bm Predefined. */ ++/* USART_BSEL2_bp Predefined. */ ++/* USART_BSEL3_bm Predefined. */ ++/* USART_BSEL3_bp Predefined. */ ++ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++ ++/* AES - AES Module */ ++/* AES.CTRL bit masks and bit positions */ ++#define AES_START_bm 0x80 /* Start/Run bit mask. */ ++#define AES_START_bp 7 /* Start/Run bit position. */ ++ ++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ ++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ ++ ++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ ++#define AES_RESET_bp 5 /* AES Software Reset bit position. */ ++ ++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ ++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ ++ ++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ ++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ ++ ++ ++/* AES.STATUS bit masks and bit positions */ ++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ ++#define AES_ERROR_bp 7 /* AES Error bit position. */ ++ ++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ ++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ ++ ++ ++/* AES.INTCTRL bit masks and bit positions */ ++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define AES_INTLVL_gp 0 /* Interrupt level group position. */ ++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_XOSCF_vect_num 1 ++#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* DMA interrupt vectors */ ++#define DMA_CH0_vect_num 6 ++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ ++#define DMA_CH1_vect_num 7 ++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ ++#define DMA_CH2_vect_num 8 ++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ ++#define DMA_CH3_vect_num 9 ++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* USARTC1 interrupt vectors */ ++#define USARTC1_RXC_vect_num 28 ++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ ++#define USARTC1_DRE_vect_num 29 ++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ ++#define USARTC1_TXC_vect_num 30 ++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ ++ ++/* AES interrupt vectors */ ++#define AES_INT_vect_num 31 ++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* ACB interrupt vectors */ ++#define ACB_AC0_vect_num 36 ++#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ ++#define ACB_AC1_vect_num 37 ++#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ ++#define ACB_ACW_vect_num 38 ++#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ ++ ++/* ADCB interrupt vectors */ ++#define ADCB_CH0_vect_num 39 ++#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ ++#define ADCB_CH1_vect_num 40 ++#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ ++#define ADCB_CH2_vect_num 41 ++#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ ++#define ADCB_CH3_vect_num 42 ++#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* TCE1 interrupt vectors */ ++#define TCE1_OVF_vect_num 53 ++#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ ++#define TCE1_ERR_vect_num 54 ++#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ ++#define TCE1_CCA_vect_num 55 ++#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ ++#define TCE1_CCB_vect_num 56 ++#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ ++ ++/* SPIE interrupt vectors */ ++#define SPIE_INT_vect_num 57 ++#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* USARTE1 interrupt vectors */ ++#define USARTE1_RXC_vect_num 61 ++#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ ++#define USARTE1_DRE_vect_num 62 ++#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ ++#define USARTE1_TXC_vect_num 63 ++#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++#define ADCA_CH1_vect_num 72 ++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ ++#define ADCA_CH2_vect_num 73 ++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ ++#define ADCA_CH3_vect_num 74 ++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD1 interrupt vectors */ ++#define TCD1_OVF_vect_num 83 ++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ ++#define TCD1_ERR_vect_num 84 ++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ ++#define TCD1_CCA_vect_num 85 ++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ ++#define TCD1_CCB_vect_num 86 ++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* USARTD1 interrupt vectors */ ++#define USARTD1_RXC_vect_num 91 ++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ ++#define USARTD1_DRE_vect_num 92 ++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ ++#define USARTD1_TXC_vect_num 93 ++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ ++ ++/* PORTF interrupt vectors */ ++#define PORTF_INT0_vect_num 104 ++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ ++#define PORTF_INT1_vect_num 105 ++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_OVF_vect_num 108 ++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ ++#define TCF0_ERR_vect_num 109 ++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ ++#define TCF0_CCA_vect_num 110 ++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ ++#define TCF0_CCB_vect_num 111 ++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ ++#define TCF0_CCC_vect_num 112 ++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ ++#define TCF0_CCD_vect_num 113 ++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ ++ ++/* USARTF0 interrupt vectors */ ++#define USARTF0_RXC_vect_num 119 ++#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ ++#define USARTF0_DRE_vect_num 120 ++#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ ++#define USARTF0_TXC_vect_num 121 ++#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ ++ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (122 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (139264) ++#define PROGMEM_PAGE_SIZE (512) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (131072) ++#define APP_SECTION_PAGE_SIZE (512) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x1E000) ++#define APPTABLE_SECTION_SIZE (8192) ++#define APPTABLE_SECTION_PAGE_SIZE (512) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x20000) ++#define BOOT_SECTION_SIZE (8192) ++#define BOOT_SECTION_PAGE_SIZE (512) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (16384) ++#define DATAMEM_PAGE_SIZE (0) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (2048) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (8192) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (2048) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define FUSE_START (0x0000) ++#define FUSE_SIZE (6) ++#define FUSE_PAGE_SIZE (0) ++#define FUSE_END (FUSE_START + FUSE_SIZE - 1) ++ ++#define LOCKBIT_START (0x0000) ++#define LOCKBIT_SIZE (1) ++#define LOCKBIT_PAGE_SIZE (0) ++#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (512) ++#define USER_SIGNATURES_PAGE_SIZE (0) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (0) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE PROGMEM_PAGE_SIZE ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define XRAMSTART EXTERNAL_SRAM_START ++#define XRAMSIZE EXTERNAL_SRAM_SIZE ++#define XRAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 */ ++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ ++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ ++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ ++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ ++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ ++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ ++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ ++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ ++#define FUSE0_DEFAULT (0xFF) ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x97 ++#define SIGNATURE_2 0x42 ++ ++ ++#endif /* _AVR_ATxmega128A3_H_ */ ++ +diff --git a/include/avr/iox128a3u.h b/include/avr/iox128a3u.h +new file mode 100644 +index 0000000..c9fe038 +--- /dev/null ++++ b/include/avr/iox128a3u.h +@@ -0,0 +1,7628 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox128a3u.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA128A3U_H_INCLUDED ++#define _AVR_ATXMEGA128A3U_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t USBCTRL; /* USB Control Register */ ++} CLK_t; ++ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t PRPB; /* Power Reduction Port B */ ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++/* USB Prescaler Division Factor */ ++typedef enum CLK_USBPSDIV_enum ++{ ++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ ++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ ++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ ++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ ++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ ++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ ++} CLK_USBPSDIV_t; ++ ++/* USB Clock Source */ ++typedef enum CLK_USBSRC_enum ++{ ++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ ++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ ++} CLK_USBSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 2 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC2MCREF_enum ++{ ++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC2MCREF_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++ register8_t EBIOUT; /* EBI Output register */ ++ register8_t EVOUTSEL; /* Event Output Select */ ++} PORTCFG_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP02MAP_enum ++{ ++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP02MAP_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP13MAP_enum ++{ ++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP13MAP_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Clock and Event Output Port */ ++typedef enum PORTCFG_CLKEVPIN_enum ++{ ++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ ++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ ++} PORTCFG_CLKEVPIN_t; ++ ++/* EBI Address Output Port */ ++typedef enum PORTCFG_EBIADROUT_enum ++{ ++ PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ ++ PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ ++ PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ ++ PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ ++} PORTCFG_EBIADROUT_t; ++ ++/* EBI Chip Select Output Port */ ++typedef enum PORTCFG_EBICSOUT_enum ++{ ++ PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ ++} PORTCFG_EBICSOUT_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ ++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ ++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ ++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ ++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AES - AES Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* AES Module */ ++typedef struct AES_struct ++{ ++ register8_t CTRL; /* AES Control Register */ ++ register8_t STATUS; /* AES Status Register */ ++ register8_t STATE; /* AES State Register */ ++ register8_t KEY; /* AES Key Register */ ++ register8_t INTCTRL; /* AES Interrupt Control Register */ ++} AES_t; ++ ++/* Interrupt level */ ++typedef enum AES_INTLVL_enum ++{ ++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} AES_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ ++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ ++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ ++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Channel */ ++typedef struct DMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Address Control */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ ++ register8_t REPCNT; /* Channel Repeat Count */ ++ register8_t reserved_0x07; ++ register8_t SRCADDR0; /* Channel Source Address 0 */ ++ register8_t SRCADDR1; /* Channel Source Address 1 */ ++ register8_t SRCADDR2; /* Channel Source Address 2 */ ++ register8_t reserved_0x0B; ++ register8_t DESTADDR0; /* Channel Destination Address 0 */ ++ register8_t DESTADDR1; /* Channel Destination Address 1 */ ++ register8_t DESTADDR2; /* Channel Destination Address 2 */ ++ register8_t reserved_0x0F; ++} DMA_CH_t; ++ ++ ++/* DMA Controller */ ++typedef struct DMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ DMA_CH_t CH0; /* DMA Channel 0 */ ++ DMA_CH_t CH1; /* DMA Channel 1 */ ++ DMA_CH_t CH2; /* DMA Channel 2 */ ++ DMA_CH_t CH3; /* DMA Channel 3 */ ++} DMA_t; ++ ++/* Burst mode */ ++typedef enum DMA_CH_BURSTLEN_enum ++{ ++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ ++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ ++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ ++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ ++} DMA_CH_BURSTLEN_t; ++ ++/* Source address reload mode */ ++typedef enum DMA_CH_SRCRELOAD_enum ++{ ++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ ++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ ++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ ++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ ++} DMA_CH_SRCRELOAD_t; ++ ++/* Source addressing mode */ ++typedef enum DMA_CH_SRCDIR_enum ++{ ++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ ++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ ++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ ++} DMA_CH_SRCDIR_t; ++ ++/* Destination adress reload mode */ ++typedef enum DMA_CH_DESTRELOAD_enum ++{ ++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ ++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ ++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ ++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ ++} DMA_CH_DESTRELOAD_t; ++ ++/* Destination adressing mode */ ++typedef enum DMA_CH_DESTDIR_enum ++{ ++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ ++} DMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum DMA_CH_TRIGSRC_enum ++{ ++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ ++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ ++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ ++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ ++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ ++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ ++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ ++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ ++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ ++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ ++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ ++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ ++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ ++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ ++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ ++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ ++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ ++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ ++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ ++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ ++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ ++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ ++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ ++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ ++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ ++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ ++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ ++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ ++} DMA_CH_TRIGSRC_t; ++ ++/* Double buffering mode */ ++typedef enum DMA_DBUFMODE_enum ++{ ++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ ++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ ++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ ++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ ++} DMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum DMA_PRIMODE_enum ++{ ++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ ++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ ++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ ++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ ++} DMA_PRIMODE_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_ERRINTLVL_enum ++{ ++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ ++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ ++} DMA_CH_ERRINTLVL_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_TRNINTLVL_enum ++{ ++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ ++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ ++} DMA_CH_TRNINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ ++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ ++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ ++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t CH4CTRL; /* Channel 4 Control Register */ ++ register8_t CH5CTRL; /* Channel 5 Control Register */ ++ register8_t CH6CTRL; /* Channel 6 Control Register */ ++ register8_t CH7CTRL; /* Channel 7 Control Register */ ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ ++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ ++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ ++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ ++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ ++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ ++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ ++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ ++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ ++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ ++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ ++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ ++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ ++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ ++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ ++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ ++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ ++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t reserved_0x07; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ _WORDREGISTER(CH1RES); /* Channel 1 Result */ ++ _WORDREGISTER(CH2RES); /* Channel 2 Result */ ++ _WORDREGISTER(CH3RES); /* Channel 3 Result */ ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++ ADC_CH_t CH1; /* ADC Channel 1 */ ++ ADC_CH_t CH2; /* ADC Channel 2 */ ++ ADC_CH_t CH3; /* ADC Channel 3 */ ++} ADC_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ ++ ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ ++ ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ ++ ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Current Limitation Mode */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ ++} ADC_CURRLIMIT_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Channel sweep selection */ ++typedef enum ADC_SWEEP_enum ++{ ++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ ++} ADC_SWEEP_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* DMA request selection */ ++typedef enum ADC_DMASEL_enum ++{ ++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ ++} ADC_DMASEL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DAC - Digital/Analog Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Digital-to-Analog Converter */ ++typedef struct DAC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t EVCTRL; /* Event Input Control */ ++ register8_t reserved_0x04; ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0GAINCAL; /* Gain Calibration */ ++ register8_t CH0OFFSETCAL; /* Offset Calibration */ ++ register8_t CH1GAINCAL; /* Gain Calibration */ ++ register8_t CH1OFFSETCAL; /* Offset Calibration */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ ++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ ++} DAC_t; ++ ++/* Output channel selection */ ++typedef enum DAC_CHSEL_enum ++{ ++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ ++ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ ++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ ++} DAC_CHSEL_t; ++ ++/* Reference voltage selection */ ++typedef enum DAC_REFSEL_enum ++{ ++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ ++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ ++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ ++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ ++} DAC_REFSEL_t; ++ ++/* Event channel selection */ ++typedef enum DAC_EVSEL_enum ++{ ++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ ++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ ++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ ++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ ++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ ++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ ++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ ++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ ++} DAC_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* SDA Hold Time */ ++typedef enum TWI_SDAHOLD_enum ++{ ++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ ++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ ++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ ++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ ++} TWI_SDAHOLD_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USB - USB ++-------------------------------------------------------------------------- ++*/ ++ ++/* USB Endpoint */ ++typedef struct USB_EP_struct ++{ ++ register8_t STATUS; /* Endpoint Status */ ++ register8_t CTRL; /* Endpoint Control */ ++ _WORDREGISTER(CNT); /* USB Endpoint Counter */ ++ _WORDREGISTER(DATAPTR); /* Data Pointer */ ++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ ++} USB_EP_t; ++ ++ ++/* Universal Serial Bus */ ++typedef struct USB_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t FIFOWP; /* FIFO Write Pointer Register */ ++ register8_t FIFORP; /* FIFO Read Pointer Register */ ++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ ++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ ++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ ++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t reserved_0x20; ++ register8_t reserved_0x21; ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t CAL0; /* Calibration Byte 0 */ ++ register8_t CAL1; /* Calibration Byte 1 */ ++} USB_t; ++ ++ ++/* USB Endpoint Table */ ++typedef struct USB_EP_TABLE_struct ++{ ++ USB_EP_t EP0OUT; /* Endpoint 0 */ ++ USB_EP_t EP0IN; /* Endpoint 0 */ ++ USB_EP_t EP1OUT; /* Endpoint 1 */ ++ USB_EP_t EP1IN; /* Endpoint 1 */ ++ USB_EP_t EP2OUT; /* Endpoint 2 */ ++ USB_EP_t EP2IN; /* Endpoint 2 */ ++ USB_EP_t EP3OUT; /* Endpoint 3 */ ++ USB_EP_t EP3IN; /* Endpoint 3 */ ++ USB_EP_t EP4OUT; /* Endpoint 4 */ ++ USB_EP_t EP4IN; /* Endpoint 4 */ ++ USB_EP_t EP5OUT; /* Endpoint 5 */ ++ USB_EP_t EP5IN; /* Endpoint 5 */ ++ USB_EP_t EP6OUT; /* Endpoint 6 */ ++ USB_EP_t EP6IN; /* Endpoint 6 */ ++ USB_EP_t EP7OUT; /* Endpoint 7 */ ++ USB_EP_t EP7IN; /* Endpoint 7 */ ++ USB_EP_t EP8OUT; /* Endpoint 8 */ ++ USB_EP_t EP8IN; /* Endpoint 8 */ ++ USB_EP_t EP9OUT; /* Endpoint 9 */ ++ USB_EP_t EP9IN; /* Endpoint 9 */ ++ USB_EP_t EP10OUT; /* Endpoint 10 */ ++ USB_EP_t EP10IN; /* Endpoint 10 */ ++ USB_EP_t EP11OUT; /* Endpoint 11 */ ++ USB_EP_t EP11IN; /* Endpoint 11 */ ++ USB_EP_t EP12OUT; /* Endpoint 12 */ ++ USB_EP_t EP12IN; /* Endpoint 12 */ ++ USB_EP_t EP13OUT; /* Endpoint 13 */ ++ USB_EP_t EP13IN; /* Endpoint 13 */ ++ USB_EP_t EP14OUT; /* Endpoint 14 */ ++ USB_EP_t EP14IN; /* Endpoint 14 */ ++ USB_EP_t EP15OUT; /* Endpoint 15 */ ++ USB_EP_t EP15IN; /* Endpoint 15 */ ++ register8_t reserved_0x100; ++ register8_t reserved_0x101; ++ register8_t reserved_0x102; ++ register8_t reserved_0x103; ++ register8_t reserved_0x104; ++ register8_t reserved_0x105; ++ register8_t reserved_0x106; ++ register8_t reserved_0x107; ++ register8_t reserved_0x108; ++ register8_t reserved_0x109; ++ register8_t reserved_0x10A; ++ register8_t reserved_0x10B; ++ register8_t reserved_0x10C; ++ register8_t reserved_0x10D; ++ register8_t reserved_0x10E; ++ register8_t reserved_0x10F; ++ register8_t FRAMENUML; /* Frame Number Low Byte */ ++ register8_t FRAMENUMH; /* Frame Number High Byte */ ++} USB_EP_TABLE_t; ++ ++/* Interrupt level */ ++typedef enum USB_INTLVL_enum ++{ ++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} USB_INTLVL_t; ++ ++/* USB Endpoint Type */ ++typedef enum USB_EP_TYPE_enum ++{ ++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ ++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ ++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ ++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ ++} USB_EP_TYPE_t; ++ ++/* USB Endpoint Buffersize */ ++typedef enum USB_EP_BUFSIZE_enum ++{ ++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ ++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ ++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ ++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ ++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ ++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ ++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ ++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ ++} USB_EP_BUFSIZE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - I/O Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* I/O Port Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Byte Mode */ ++typedef enum TC_BYTEM_enum ++{ ++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ ++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ ++} TC_BYTEM_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC2 - 16-bit Timer/Counter type 2 ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter type 2 */ ++typedef struct TC2_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t reserved_0x03; ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t reserved_0x08; ++ register8_t CTRLF; /* Control Register F */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t LCNT; /* Low Byte Count */ ++ register8_t HCNT; /* High Byte Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t LPER; /* Low Byte Period */ ++ register8_t HPER; /* High Byte Period */ ++ register8_t LCMPA; /* Low Byte Compare A */ ++ register8_t HCMPA; /* High Byte Compare A */ ++ register8_t LCMPB; /* Low Byte Compare B */ ++ register8_t HCMPB; /* High Byte Compare B */ ++ register8_t LCMPC; /* Low Byte Compare C */ ++ register8_t HCMPC; /* High Byte Compare C */ ++ register8_t LCMPD; /* Low Byte Compare D */ ++ register8_t HCMPD; /* High Byte Compare D */ ++} TC2_t; ++ ++/* Clock Selection */ ++typedef enum TC2_CLKSEL_enum ++{ ++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC2_CLKSEL_t; ++ ++/* Byte Mode */ ++typedef enum TC2_BYTEM_enum ++{ ++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ ++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ ++} TC2_BYTEM_t; ++ ++/* High Byte Underflow Interrupt Level */ ++typedef enum TC2_HUNFINTLVL_enum ++{ ++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_HUNFINTLVL_t; ++ ++/* Low Byte Underflow Interrupt Level */ ++typedef enum TC2_LUNFINTLVL_enum ++{ ++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LUNFINTLVL_t; ++ ++/* Low Byte Compare D Interrupt Level */ ++typedef enum TC2_LCMPDINTLVL_enum ++{ ++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC2_LCMPDINTLVL_t; ++ ++/* Low Byte Compare C Interrupt Level */ ++typedef enum TC2_LCMPCINTLVL_enum ++{ ++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC2_LCMPCINTLVL_t; ++ ++/* Low Byte Compare B Interrupt Level */ ++typedef enum TC2_LCMPBINTLVL_enum ++{ ++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_LCMPBINTLVL_t; ++ ++/* Low Byte Compare A Interrupt Level */ ++typedef enum TC2_LCMPAINTLVL_enum ++{ ++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LCMPAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMD_enum ++{ ++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC2_CMD_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMDEN_enum ++{ ++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ ++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ ++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ ++} TC2_CMDEN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AWEX - Timer/Counter Advanced Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - Timer/Counter High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t FUSEBYTE0; /* JTAG User ID */ ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* Timer Oscillator pin location */ ++typedef enum TOSCSEL_enum ++{ ++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ ++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ ++} TOSCSEL_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* BOD operation */ ++typedef enum BODACT_enum ++{ ++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BODACT_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WDP_enum ++{ ++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ ++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ ++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ ++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ ++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ ++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ ++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ ++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ ++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ ++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ ++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ ++} WDP_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LOCKBIT - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ ++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t USBCAL0; /* USB Calibration Byte 0 */ ++ register8_t USBCAL1; /* USB Calibration Byte 1 */ ++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ ++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ ++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ ++ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ ++ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ ++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ ++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ ++ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ ++ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++ register8_t reserved_0x40; ++ register8_t reserved_0x41; ++ register8_t reserved_0x42; ++ register8_t reserved_0x43; ++ register8_t reserved_0x44; ++ register8_t reserved_0x45; ++ register8_t reserved_0x46; ++ register8_t reserved_0x47; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define AES (*(AES_t *) 0x00C0) /* AES Module */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ ++#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ ++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ ++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ ++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ ++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ ++#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ ++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ ++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ ++#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ ++#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ ++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ ++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ ++#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ ++#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ ++#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++#define GPIO_GPIOR4 _SFR_MEM8(0x0004) ++#define GPIO_GPIOR5 _SFR_MEM8(0x0005) ++#define GPIO_GPIOR6 _SFR_MEM8(0x0006) ++#define GPIO_GPIOR7 _SFR_MEM8(0x0007) ++#define GPIO_GPIOR8 _SFR_MEM8(0x0008) ++#define GPIO_GPIOR9 _SFR_MEM8(0x0009) ++#define GPIO_GPIORA _SFR_MEM8(0x000A) ++#define GPIO_GPIORB _SFR_MEM8(0x000B) ++#define GPIO_GPIORC _SFR_MEM8(0x000C) ++#define GPIO_GPIORD _SFR_MEM8(0x000D) ++#define GPIO_GPIORE _SFR_MEM8(0x000E) ++#define GPIO_GPIORF _SFR_MEM8(0x000F) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++#define GPIO_GPIO4 _SFR_MEM8(0x0004) ++#define GPIO_GPIO5 _SFR_MEM8(0x0005) ++#define GPIO_GPIO6 _SFR_MEM8(0x0006) ++#define GPIO_GPIO7 _SFR_MEM8(0x0007) ++#define GPIO_GPIO8 _SFR_MEM8(0x0008) ++#define GPIO_GPIO9 _SFR_MEM8(0x0009) ++#define GPIO_GPIOA _SFR_MEM8(0x000A) ++#define GPIO_GPIOB _SFR_MEM8(0x000B) ++#define GPIO_GPIOC _SFR_MEM8(0x000C) ++#define GPIO_GPIOD _SFR_MEM8(0x000D) ++#define GPIO_GPIOE _SFR_MEM8(0x000E) ++#define GPIO_GPIOF _SFR_MEM8(0x000F) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) ++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) ++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) ++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) ++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) ++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) ++#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) ++#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) ++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) ++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) ++#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) ++#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++#define CLK_USBCTRL _SFR_MEM8(0x0044) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLL - DFLL */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPB _SFR_MEM8(0x0072) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) ++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) ++ ++/* AES - AES Module */ ++#define AES_CTRL _SFR_MEM8(0x00C0) ++#define AES_STATUS _SFR_MEM8(0x00C1) ++#define AES_STATE _SFR_MEM8(0x00C2) ++#define AES_KEY _SFR_MEM8(0x00C3) ++#define AES_INTCTRL _SFR_MEM8(0x00C4) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* DMA - DMA Controller */ ++#define DMA_CTRL _SFR_MEM8(0x0100) ++#define DMA_INTFLAGS _SFR_MEM8(0x0103) ++#define DMA_STATUS _SFR_MEM8(0x0104) ++#define DMA_TEMP _SFR_MEM16(0x0106) ++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) ++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) ++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) ++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) ++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) ++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) ++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) ++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) ++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) ++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) ++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) ++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) ++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) ++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) ++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) ++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) ++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) ++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) ++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) ++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) ++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) ++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) ++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) ++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) ++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) ++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) ++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) ++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) ++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) ++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) ++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) ++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) ++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) ++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) ++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) ++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) ++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) ++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) ++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) ++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) ++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) ++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH4MUX _SFR_MEM8(0x0184) ++#define EVSYS_CH5MUX _SFR_MEM8(0x0185) ++#define EVSYS_CH6MUX _SFR_MEM8(0x0186) ++#define EVSYS_CH7MUX _SFR_MEM8(0x0187) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) ++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) ++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) ++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CH1RES _SFR_MEM16(0x0212) ++#define ADCA_CH2RES _SFR_MEM16(0x0214) ++#define ADCA_CH3RES _SFR_MEM16(0x0216) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) ++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) ++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) ++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) ++#define ADCA_CH1_RES _SFR_MEM16(0x022C) ++#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) ++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) ++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) ++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) ++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) ++#define ADCA_CH2_RES _SFR_MEM16(0x0234) ++#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) ++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) ++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) ++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) ++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) ++#define ADCA_CH3_RES _SFR_MEM16(0x023C) ++#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCB_CTRLA _SFR_MEM8(0x0240) ++#define ADCB_CTRLB _SFR_MEM8(0x0241) ++#define ADCB_REFCTRL _SFR_MEM8(0x0242) ++#define ADCB_EVCTRL _SFR_MEM8(0x0243) ++#define ADCB_PRESCALER _SFR_MEM8(0x0244) ++#define ADCB_INTFLAGS _SFR_MEM8(0x0246) ++#define ADCB_TEMP _SFR_MEM8(0x0247) ++#define ADCB_CAL _SFR_MEM16(0x024C) ++#define ADCB_CH0RES _SFR_MEM16(0x0250) ++#define ADCB_CH1RES _SFR_MEM16(0x0252) ++#define ADCB_CH2RES _SFR_MEM16(0x0254) ++#define ADCB_CH3RES _SFR_MEM16(0x0256) ++#define ADCB_CMP _SFR_MEM16(0x0258) ++#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) ++#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) ++#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) ++#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) ++#define ADCB_CH0_RES _SFR_MEM16(0x0264) ++#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) ++#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) ++#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) ++#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) ++#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) ++#define ADCB_CH1_RES _SFR_MEM16(0x026C) ++#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) ++#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) ++#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) ++#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) ++#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) ++#define ADCB_CH2_RES _SFR_MEM16(0x0274) ++#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) ++#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) ++#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) ++#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) ++#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) ++#define ADCB_CH3_RES _SFR_MEM16(0x027C) ++#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) ++ ++/* DAC - Digital-to-Analog Converter */ ++#define DACB_CTRLA _SFR_MEM8(0x0320) ++#define DACB_CTRLB _SFR_MEM8(0x0321) ++#define DACB_CTRLC _SFR_MEM8(0x0322) ++#define DACB_EVCTRL _SFR_MEM8(0x0323) ++#define DACB_STATUS _SFR_MEM8(0x0325) ++#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) ++#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) ++#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) ++#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) ++#define DACB_CH0DATA _SFR_MEM16(0x0338) ++#define DACB_CH1DATA _SFR_MEM16(0x033A) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* AC - Analog Comparator */ ++#define ACB_AC0CTRL _SFR_MEM8(0x0390) ++#define ACB_AC1CTRL _SFR_MEM8(0x0391) ++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) ++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) ++#define ACB_CTRLA _SFR_MEM8(0x0394) ++#define ACB_CTRLB _SFR_MEM8(0x0395) ++#define ACB_WINCTRL _SFR_MEM8(0x0396) ++#define ACB_STATUS _SFR_MEM8(0x0397) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* USB - Universal Serial Bus */ ++#define USB_CTRLA _SFR_MEM8(0x04C0) ++#define USB_CTRLB _SFR_MEM8(0x04C1) ++#define USB_STATUS _SFR_MEM8(0x04C2) ++#define USB_ADDR _SFR_MEM8(0x04C3) ++#define USB_FIFOWP _SFR_MEM8(0x04C4) ++#define USB_FIFORP _SFR_MEM8(0x04C5) ++#define USB_EPPTR _SFR_MEM16(0x04C6) ++#define USB_INTCTRLA _SFR_MEM8(0x04C8) ++#define USB_INTCTRLB _SFR_MEM8(0x04C9) ++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) ++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) ++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) ++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) ++#define USB_CAL0 _SFR_MEM8(0x04FA) ++#define USB_CAL1 _SFR_MEM8(0x04FB) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_REMAP _SFR_MEM8(0x060E) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_REMAP _SFR_MEM8(0x062E) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_REMAP _SFR_MEM8(0x068E) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORT - I/O Ports */ ++#define PORTF_DIR _SFR_MEM8(0x06A0) ++#define PORTF_DIRSET _SFR_MEM8(0x06A1) ++#define PORTF_DIRCLR _SFR_MEM8(0x06A2) ++#define PORTF_DIRTGL _SFR_MEM8(0x06A3) ++#define PORTF_OUT _SFR_MEM8(0x06A4) ++#define PORTF_OUTSET _SFR_MEM8(0x06A5) ++#define PORTF_OUTCLR _SFR_MEM8(0x06A6) ++#define PORTF_OUTTGL _SFR_MEM8(0x06A7) ++#define PORTF_IN _SFR_MEM8(0x06A8) ++#define PORTF_INTCTRL _SFR_MEM8(0x06A9) ++#define PORTF_INT0MASK _SFR_MEM8(0x06AA) ++#define PORTF_INT1MASK _SFR_MEM8(0x06AB) ++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) ++#define PORTF_REMAP _SFR_MEM8(0x06AE) ++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) ++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) ++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) ++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) ++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) ++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) ++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) ++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCC2_CTRLA _SFR_MEM8(0x0800) ++#define TCC2_CTRLB _SFR_MEM8(0x0801) ++#define TCC2_CTRLC _SFR_MEM8(0x0802) ++#define TCC2_CTRLE _SFR_MEM8(0x0804) ++#define TCC2_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC2_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC2_CTRLF _SFR_MEM8(0x0809) ++#define TCC2_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC2_LCNT _SFR_MEM8(0x0820) ++#define TCC2_HCNT _SFR_MEM8(0x0821) ++#define TCC2_LPER _SFR_MEM8(0x0826) ++#define TCC2_HPER _SFR_MEM8(0x0827) ++#define TCC2_LCMPA _SFR_MEM8(0x0828) ++#define TCC2_HCMPA _SFR_MEM8(0x0829) ++#define TCC2_LCMPB _SFR_MEM8(0x082A) ++#define TCC2_HCMPB _SFR_MEM8(0x082B) ++#define TCC2_LCMPC _SFR_MEM8(0x082C) ++#define TCC2_HCMPC _SFR_MEM8(0x082D) ++#define TCC2_LCMPD _SFR_MEM8(0x082E) ++#define TCC2_HCMPD _SFR_MEM8(0x082F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_STATUSSET _SFR_MEM8(0x0885) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1_DATA _SFR_MEM8(0x08B0) ++#define USARTC1_STATUS _SFR_MEM8(0x08B1) ++#define USARTC1_CTRLA _SFR_MEM8(0x08B3) ++#define USARTC1_CTRLB _SFR_MEM8(0x08B4) ++#define USARTC1_CTRLC _SFR_MEM8(0x08B5) ++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) ++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCD2_CTRLA _SFR_MEM8(0x0900) ++#define TCD2_CTRLB _SFR_MEM8(0x0901) ++#define TCD2_CTRLC _SFR_MEM8(0x0902) ++#define TCD2_CTRLE _SFR_MEM8(0x0904) ++#define TCD2_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD2_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD2_CTRLF _SFR_MEM8(0x0909) ++#define TCD2_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD2_LCNT _SFR_MEM8(0x0920) ++#define TCD2_HCNT _SFR_MEM8(0x0921) ++#define TCD2_LPER _SFR_MEM8(0x0926) ++#define TCD2_HPER _SFR_MEM8(0x0927) ++#define TCD2_LCMPA _SFR_MEM8(0x0928) ++#define TCD2_HCMPA _SFR_MEM8(0x0929) ++#define TCD2_LCMPB _SFR_MEM8(0x092A) ++#define TCD2_HCMPB _SFR_MEM8(0x092B) ++#define TCD2_LCMPC _SFR_MEM8(0x092C) ++#define TCD2_HCMPC _SFR_MEM8(0x092D) ++#define TCD2_LCMPD _SFR_MEM8(0x092E) ++#define TCD2_HCMPD _SFR_MEM8(0x092F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCD1_CTRLA _SFR_MEM8(0x0940) ++#define TCD1_CTRLB _SFR_MEM8(0x0941) ++#define TCD1_CTRLC _SFR_MEM8(0x0942) ++#define TCD1_CTRLD _SFR_MEM8(0x0943) ++#define TCD1_CTRLE _SFR_MEM8(0x0944) ++#define TCD1_INTCTRLA _SFR_MEM8(0x0946) ++#define TCD1_INTCTRLB _SFR_MEM8(0x0947) ++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) ++#define TCD1_CTRLFSET _SFR_MEM8(0x0949) ++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) ++#define TCD1_CTRLGSET _SFR_MEM8(0x094B) ++#define TCD1_INTFLAGS _SFR_MEM8(0x094C) ++#define TCD1_TEMP _SFR_MEM8(0x094F) ++#define TCD1_CNT _SFR_MEM16(0x0960) ++#define TCD1_PER _SFR_MEM16(0x0966) ++#define TCD1_CCA _SFR_MEM16(0x0968) ++#define TCD1_CCB _SFR_MEM16(0x096A) ++#define TCD1_PERBUF _SFR_MEM16(0x0976) ++#define TCD1_CCABUF _SFR_MEM16(0x0978) ++#define TCD1_CCBBUF _SFR_MEM16(0x097A) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESD_CTRLA _SFR_MEM8(0x0990) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD1_DATA _SFR_MEM8(0x09B0) ++#define USARTD1_STATUS _SFR_MEM8(0x09B1) ++#define USARTD1_CTRLA _SFR_MEM8(0x09B3) ++#define USARTD1_CTRLB _SFR_MEM8(0x09B4) ++#define USARTD1_CTRLC _SFR_MEM8(0x09B5) ++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) ++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCE2_CTRLA _SFR_MEM8(0x0A00) ++#define TCE2_CTRLB _SFR_MEM8(0x0A01) ++#define TCE2_CTRLC _SFR_MEM8(0x0A02) ++#define TCE2_CTRLE _SFR_MEM8(0x0A04) ++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE2_CTRLF _SFR_MEM8(0x0A09) ++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE2_LCNT _SFR_MEM8(0x0A20) ++#define TCE2_HCNT _SFR_MEM8(0x0A21) ++#define TCE2_LPER _SFR_MEM8(0x0A26) ++#define TCE2_HPER _SFR_MEM8(0x0A27) ++#define TCE2_LCMPA _SFR_MEM8(0x0A28) ++#define TCE2_HCMPA _SFR_MEM8(0x0A29) ++#define TCE2_LCMPB _SFR_MEM8(0x0A2A) ++#define TCE2_HCMPB _SFR_MEM8(0x0A2B) ++#define TCE2_LCMPC _SFR_MEM8(0x0A2C) ++#define TCE2_HCMPC _SFR_MEM8(0x0A2D) ++#define TCE2_LCMPD _SFR_MEM8(0x0A2E) ++#define TCE2_HCMPD _SFR_MEM8(0x0A2F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCE1_CTRLA _SFR_MEM8(0x0A40) ++#define TCE1_CTRLB _SFR_MEM8(0x0A41) ++#define TCE1_CTRLC _SFR_MEM8(0x0A42) ++#define TCE1_CTRLD _SFR_MEM8(0x0A43) ++#define TCE1_CTRLE _SFR_MEM8(0x0A44) ++#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) ++#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) ++#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) ++#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) ++#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) ++#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) ++#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) ++#define TCE1_TEMP _SFR_MEM8(0x0A4F) ++#define TCE1_CNT _SFR_MEM16(0x0A60) ++#define TCE1_PER _SFR_MEM16(0x0A66) ++#define TCE1_CCA _SFR_MEM16(0x0A68) ++#define TCE1_CCB _SFR_MEM16(0x0A6A) ++#define TCE1_PERBUF _SFR_MEM16(0x0A76) ++#define TCE1_CCABUF _SFR_MEM16(0x0A78) ++#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXE_CTRL _SFR_MEM8(0x0A80) ++#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) ++#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) ++#define AWEXE_STATUS _SFR_MEM8(0x0A84) ++#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) ++#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) ++#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) ++#define AWEXE_DTLS _SFR_MEM8(0x0A88) ++#define AWEXE_DTHS _SFR_MEM8(0x0A89) ++#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) ++#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) ++#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESE_CTRLA _SFR_MEM8(0x0A90) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE1_DATA _SFR_MEM8(0x0AB0) ++#define USARTE1_STATUS _SFR_MEM8(0x0AB1) ++#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) ++#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) ++#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) ++#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) ++#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIE_CTRL _SFR_MEM8(0x0AC0) ++#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) ++#define SPIE_STATUS _SFR_MEM8(0x0AC2) ++#define SPIE_DATA _SFR_MEM8(0x0AC3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCF0_CTRLA _SFR_MEM8(0x0B00) ++#define TCF0_CTRLB _SFR_MEM8(0x0B01) ++#define TCF0_CTRLC _SFR_MEM8(0x0B02) ++#define TCF0_CTRLD _SFR_MEM8(0x0B03) ++#define TCF0_CTRLE _SFR_MEM8(0x0B04) ++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) ++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) ++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) ++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) ++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF0_TEMP _SFR_MEM8(0x0B0F) ++#define TCF0_CNT _SFR_MEM16(0x0B20) ++#define TCF0_PER _SFR_MEM16(0x0B26) ++#define TCF0_CCA _SFR_MEM16(0x0B28) ++#define TCF0_CCB _SFR_MEM16(0x0B2A) ++#define TCF0_CCC _SFR_MEM16(0x0B2C) ++#define TCF0_CCD _SFR_MEM16(0x0B2E) ++#define TCF0_PERBUF _SFR_MEM16(0x0B36) ++#define TCF0_CCABUF _SFR_MEM16(0x0B38) ++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) ++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) ++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCF2_CTRLA _SFR_MEM8(0x0B00) ++#define TCF2_CTRLB _SFR_MEM8(0x0B01) ++#define TCF2_CTRLC _SFR_MEM8(0x0B02) ++#define TCF2_CTRLE _SFR_MEM8(0x0B04) ++#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF2_CTRLF _SFR_MEM8(0x0B09) ++#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF2_LCNT _SFR_MEM8(0x0B20) ++#define TCF2_HCNT _SFR_MEM8(0x0B21) ++#define TCF2_LPER _SFR_MEM8(0x0B26) ++#define TCF2_HPER _SFR_MEM8(0x0B27) ++#define TCF2_LCMPA _SFR_MEM8(0x0B28) ++#define TCF2_HCMPA _SFR_MEM8(0x0B29) ++#define TCF2_LCMPB _SFR_MEM8(0x0B2A) ++#define TCF2_HCMPB _SFR_MEM8(0x0B2B) ++#define TCF2_LCMPC _SFR_MEM8(0x0B2C) ++#define TCF2_HCMPC _SFR_MEM8(0x0B2D) ++#define TCF2_LCMPD _SFR_MEM8(0x0B2E) ++#define TCF2_HCMPD _SFR_MEM8(0x0B2F) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESF_CTRLA _SFR_MEM8(0x0B90) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTF0_DATA _SFR_MEM8(0x0BA0) ++#define USARTF0_STATUS _SFR_MEM8(0x0BA1) ++#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) ++#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) ++#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) ++#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) ++#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* CLK.USBCTRL bit masks and bit positions */ ++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ ++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ ++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ ++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ ++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ ++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ ++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ ++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ ++ ++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ ++#define CLK_USBSRC_gp 1 /* Clock Source group position. */ ++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ ++ ++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_USB_bm 0x40 /* USB bit mask. */ ++#define PR_USB_bp 6 /* USB bit position. */ ++ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ ++#define PR_EBI_bp 3 /* External Bus Interface bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ ++#define PR_DAC_bp 2 /* Port A DAC bit position. */ ++ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPB bit masks and bit positions */ ++/* PR_DAC Predefined. */ ++/* PR_DAC Predefined. */ ++ ++/* PR_ADC Predefined. */ ++/* PR_ADC Predefined. */ ++ ++/* PR_AC Predefined. */ ++/* PR_AC Predefined. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ ++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ ++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ ++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ ++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ ++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ ++ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ ++#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ ++ ++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ ++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ ++ ++#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ ++#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ ++ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ ++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ ++ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ ++ ++/* PORTCFG.EBIOUT bit masks and bit positions */ ++#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ ++#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ ++#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ ++#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ ++#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ ++#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ ++ ++#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ ++#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ ++#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ ++#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ ++#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ ++#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ ++ ++/* PORTCFG.EVOUTSEL bit masks and bit positions */ ++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ ++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ ++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ ++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ ++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ ++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ ++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ ++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ ++ ++/* AES - AES Module */ ++/* AES.CTRL bit masks and bit positions */ ++#define AES_START_bm 0x80 /* Start/Run bit mask. */ ++#define AES_START_bp 7 /* Start/Run bit position. */ ++ ++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ ++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ ++ ++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ ++#define AES_RESET_bp 5 /* AES Software Reset bit position. */ ++ ++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ ++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ ++ ++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ ++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ ++ ++/* AES.STATUS bit masks and bit positions */ ++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ ++#define AES_ERROR_bp 7 /* AES Error bit position. */ ++ ++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ ++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ ++ ++/* AES.INTCTRL bit masks and bit positions */ ++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define AES_INTLVL_gp 0 /* Interrupt level group position. */ ++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* DMA - DMA Controller */ ++/* DMA_CH.CTRLA bit masks and bit positions */ ++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ ++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ ++ ++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ ++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ ++ ++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ ++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ ++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ ++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ ++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ ++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ ++ ++/* DMA_CH.CTRLB bit masks and bit positions */ ++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ ++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ ++ ++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ ++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ ++ ++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ ++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ ++ ++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ ++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ ++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ ++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ ++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ ++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ ++ ++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ ++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ ++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ ++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ ++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ ++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ ++ ++/* DMA_CH.ADDRCTRL bit masks and bit positions */ ++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ ++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ ++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ ++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ ++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ ++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ ++ ++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ ++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ ++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ ++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ ++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ ++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ ++ ++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ ++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ ++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ ++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ ++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ ++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ ++ ++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ ++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ ++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ ++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ ++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ ++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ ++ ++/* DMA_CH.TRIGSRC bit masks and bit positions */ ++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++/* DMA.CTRL bit masks and bit positions */ ++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define DMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define DMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ ++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ ++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ ++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ ++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ ++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ ++ ++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ ++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ ++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ ++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ ++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ ++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ ++ ++/* DMA.INTFLAGS bit masks and bit positions */ ++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++/* DMA.STATUS bit masks and bit positions */ ++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ ++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ ++ ++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ ++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ ++ ++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ ++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ ++ ++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ ++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ ++ ++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ ++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ ++ ++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ ++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ ++ ++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ ++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ ++ ++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ ++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH4MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH5MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH6MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH7MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM Predefined. */ ++/* EVSYS_QDIRM Predefined. */ ++ ++/* EVSYS_QDIEN Predefined. */ ++/* EVSYS_QDIEN Predefined. */ ++ ++/* EVSYS_QDEN Predefined. */ ++/* EVSYS_QDEN Predefined. */ ++ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH4CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM Predefined. */ ++/* EVSYS_QDIRM Predefined. */ ++ ++/* EVSYS_QDIEN Predefined. */ ++/* EVSYS_QDIEN Predefined. */ ++ ++/* EVSYS_QDEN Predefined. */ ++/* EVSYS_QDEN Predefined. */ ++ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH5CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH6CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH7CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ ++#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ ++#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ ++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ ++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ ++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ ++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ ++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ ++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ ++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ ++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ ++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ ++ ++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ ++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ ++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ ++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ ++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ ++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ ++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ ++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ ++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ ++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ ++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ ++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ ++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ ++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ ++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ ++ ++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ ++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ ++ ++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ ++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ ++ ++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ ++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ ++ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ ++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ ++#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ ++ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ ++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ ++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ ++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ ++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ ++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ ++ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ ++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ ++ ++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ ++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ ++ ++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ ++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ ++ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* DAC - Digital/Analog Converter */ ++/* DAC.CTRLA bit masks and bit positions */ ++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ ++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ ++ ++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ ++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ ++ ++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ ++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ ++ ++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ ++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ ++ ++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define DAC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* DAC.CTRLB bit masks and bit positions */ ++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ ++#define DAC_CHSEL_gp 5 /* Channel Select group position. */ ++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ ++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ ++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ ++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ ++ ++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ ++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ ++ ++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ ++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ ++ ++/* DAC.CTRLC bit masks and bit positions */ ++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ ++#define DAC_REFSEL_gp 3 /* Reference Select group position. */ ++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ ++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ ++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ ++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ ++ ++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ ++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ ++ ++/* DAC.EVCTRL bit masks and bit positions */ ++#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ ++#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ ++ ++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ ++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ ++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ ++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ ++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ ++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ ++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ ++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ ++ ++/* DAC.STATUS bit masks and bit positions */ ++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ ++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ ++ ++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ ++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ ++ ++/* DAC.CH0GAINCAL bit masks and bit positions */ ++#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH0OFFSETCAL bit masks and bit positions */ ++#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* DAC.CH1GAINCAL bit masks and bit positions */ ++#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH1OFFSETCAL bit masks and bit positions */ ++#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ ++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HSMODE Predefined. */ ++/* AC_HSMODE Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* RTC - Real-Time Counter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* USB - USB */ ++/* USB_EP.STATUS bit masks and bit positions */ ++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ ++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ ++ ++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ ++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ ++ ++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ ++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ ++ ++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ ++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ ++ ++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ ++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ ++ ++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ ++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ ++ ++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ ++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ ++ ++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ ++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ ++ ++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ ++ ++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ ++ ++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ ++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ ++ ++/* USB_EP.CTRL bit masks and bit positions */ ++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ ++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ ++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ ++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ ++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ ++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ ++ ++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ ++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ ++ ++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ ++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ ++ ++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ ++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ ++ ++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ ++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ ++ ++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ ++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ ++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ ++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ ++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ ++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ ++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ ++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ ++ ++/* USB_EP.CNT bit masks and bit positions */ ++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ ++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ ++ ++/* USB.CTRLA bit masks and bit positions */ ++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ ++#define USB_ENABLE_bp 7 /* USB Enable bit position. */ ++ ++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ ++#define USB_SPEED_bp 6 /* Speed Select bit position. */ ++ ++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ ++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ ++ ++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ ++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ ++ ++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ ++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ ++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ ++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ ++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ ++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ ++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ ++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ ++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ ++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ ++ ++/* USB.CTRLB bit masks and bit positions */ ++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ ++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ ++ ++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ ++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ ++ ++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ ++#define USB_GNACK_bp 1 /* Global NACK bit position. */ ++ ++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ ++#define USB_ATTACH_bp 0 /* Attach bit position. */ ++ ++/* USB.STATUS bit masks and bit positions */ ++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ ++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ ++ ++#define USB_RESUME_bm 0x04 /* Resume bit mask. */ ++#define USB_RESUME_bp 2 /* Resume bit position. */ ++ ++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ ++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ ++ ++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ ++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ ++ ++/* USB.ADDR bit masks and bit positions */ ++#define USB_ADDR_gm 0x7F /* Device Address group mask. */ ++#define USB_ADDR_gp 0 /* Device Address group position. */ ++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ ++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ ++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ ++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ ++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ ++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ ++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ ++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ ++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ ++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ ++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ ++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ ++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ ++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ ++ ++/* USB.FIFOWP bit masks and bit positions */ ++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ ++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ ++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ ++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ ++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ ++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ ++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ ++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ ++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ ++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ ++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ ++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ ++ ++/* USB.FIFORP bit masks and bit positions */ ++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ ++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ ++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ ++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ ++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ ++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ ++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ ++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ ++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ ++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ ++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ ++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ ++ ++/* USB.INTCTRLA bit masks and bit positions */ ++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ ++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ ++ ++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ ++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ ++ ++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ ++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ ++ ++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ ++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ ++ ++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* USB.INTCTRLB bit masks and bit positions */ ++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ ++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ ++ ++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ ++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ ++ ++/* USB.INTFLAGSACLR bit masks and bit positions */ ++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ ++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ ++ ++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ ++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ ++ ++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ ++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ ++ ++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ ++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ ++ ++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ ++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ ++ ++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ ++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ ++ ++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ ++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ ++ ++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ ++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSASET bit masks and bit positions */ ++/* USB_SOFIF Predefined. */ ++/* USB_SOFIF Predefined. */ ++ ++/* USB_SUSPENDIF Predefined. */ ++/* USB_SUSPENDIF Predefined. */ ++ ++/* USB_RESUMEIF Predefined. */ ++/* USB_RESUMEIF Predefined. */ ++ ++/* USB_RSTIF Predefined. */ ++/* USB_RSTIF Predefined. */ ++ ++/* USB_CRCIF Predefined. */ ++/* USB_CRCIF Predefined. */ ++ ++/* USB_UNFIF Predefined. */ ++/* USB_UNFIF Predefined. */ ++ ++/* USB_OVFIF Predefined. */ ++/* USB_OVFIF Predefined. */ ++ ++/* USB_STALLIF Predefined. */ ++/* USB_STALLIF Predefined. */ ++ ++/* USB.INTFLAGSBCLR bit masks and bit positions */ ++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ ++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ ++ ++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ ++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSBSET bit masks and bit positions */ ++/* USB_TRNIF Predefined. */ ++/* USB_TRNIF Predefined. */ ++ ++/* USB_SETUPIF Predefined. */ ++/* USB_SETUPIF Predefined. */ ++ ++/* PORT - I/O Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_SPI_bm 0x20 /* SPI bit mask. */ ++#define PORT_SPI_bp 5 /* SPI bit position. */ ++ ++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ ++#define PORT_USART0_bp 4 /* USART0 bit position. */ ++ ++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ ++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ ++ ++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ ++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ ++ ++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ ++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ ++ ++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ ++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD Predefined. */ ++/* TC0_CMD Predefined. */ ++ ++/* TC0_LUPD Predefined. */ ++/* TC0_LUPD Predefined. */ ++ ++/* TC0_DIR Predefined. */ ++/* TC0_DIR Predefined. */ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV Predefined. */ ++/* TC0_CCDBV Predefined. */ ++ ++/* TC0_CCCBV Predefined. */ ++/* TC0_CCCBV Predefined. */ ++ ++/* TC0_CCBBV Predefined. */ ++/* TC0_CCBBV Predefined. */ ++ ++/* TC0_CCABV Predefined. */ ++/* TC0_CCABV Predefined. */ ++ ++/* TC0_PERBV Predefined. */ ++/* TC0_PERBV Predefined. */ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD Predefined. */ ++/* TC1_CMD Predefined. */ ++ ++/* TC1_LUPD Predefined. */ ++/* TC1_LUPD Predefined. */ ++ ++/* TC1_DIR Predefined. */ ++/* TC1_DIR Predefined. */ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV Predefined. */ ++/* TC1_CCBBV Predefined. */ ++ ++/* TC1_CCABV Predefined. */ ++/* TC1_CCABV Predefined. */ ++ ++/* TC1_PERBV Predefined. */ ++/* TC1_PERBV Predefined. */ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++/* TC2.CTRLA bit masks and bit positions */ ++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC2.CTRLB bit masks and bit positions */ ++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ ++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ ++ ++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ ++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ ++ ++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ ++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ ++ ++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ ++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ ++ ++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ ++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ ++ ++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ ++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ ++ ++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ ++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ ++ ++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ ++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ ++ ++/* TC2.CTRLC bit masks and bit positions */ ++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ ++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ ++ ++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ ++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ ++ ++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ ++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ ++ ++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ ++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ ++ ++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ ++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ ++ ++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ ++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ ++ ++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ ++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ ++ ++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ ++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ ++ ++/* TC2.CTRLE bit masks and bit positions */ ++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC2.INTCTRLA bit masks and bit positions */ ++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ ++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ ++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ ++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ ++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ ++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ ++ ++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ ++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ ++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ ++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ ++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ ++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ ++ ++/* TC2.INTCTRLB bit masks and bit positions */ ++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ ++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ ++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ ++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ ++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ ++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ ++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ ++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ ++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ ++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ ++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ ++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ ++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ ++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ ++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ ++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ ++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ ++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ ++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ ++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ ++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ ++ ++/* TC2.CTRLF bit masks and bit positions */ ++#define TC2_CMD_gm 0x0C /* Command group mask. */ ++#define TC2_CMD_gp 2 /* Command group position. */ ++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC2_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC2_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ ++#define TC2_CMDEN_gp 0 /* Command Enable group position. */ ++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ ++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ ++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ ++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ ++ ++/* TC2.INTFLAGS bit masks and bit positions */ ++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ ++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ ++ ++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ ++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ ++ ++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ ++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ ++ ++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ ++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ ++ ++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ ++ ++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ ++ ++/* AWEX - Timer/Counter Advanced Waveform Extension */ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++/* AWEX.STATUSSET bit masks and bit positions */ ++/* AWEX_FDF Predefined. */ ++/* AWEX_FDF Predefined. */ ++ ++/* AWEX_DTHSBUFV Predefined. */ ++/* AWEX_DTHSBUFV Predefined. */ ++ ++/* AWEX_DTLSBUFV Predefined. */ ++/* AWEX_DTLSBUFV Predefined. */ ++ ++/* HIRES - Timer/Counter High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ ++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ ++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ ++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ ++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ ++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ ++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ ++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ ++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ ++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ ++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ ++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ ++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ ++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ ++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ ++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ ++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ ++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ ++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ ++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ ++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* LOCKBIT - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* DMA interrupt vectors */ ++#define DMA_CH0_vect_num 6 ++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ ++#define DMA_CH1_vect_num 7 ++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ ++#define DMA_CH2_vect_num 8 ++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ ++#define DMA_CH3_vect_num 9 ++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LUNF_vect_num 14 ++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_HUNF_vect_num 15 ++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPA_vect_num 16 ++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPB_vect_num 17 ++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPC_vect_num 18 ++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPD_vect_num 19 ++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* USARTC1 interrupt vectors */ ++#define USARTC1_RXC_vect_num 28 ++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ ++#define USARTC1_DRE_vect_num 29 ++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ ++#define USARTC1_TXC_vect_num 30 ++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ ++ ++/* AES interrupt vectors */ ++#define AES_INT_vect_num 31 ++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* ACB interrupt vectors */ ++#define ACB_AC0_vect_num 36 ++#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ ++#define ACB_AC1_vect_num 37 ++#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ ++#define ACB_ACW_vect_num 38 ++#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ ++ ++/* ADCB interrupt vectors */ ++#define ADCB_CH0_vect_num 39 ++#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ ++#define ADCB_CH1_vect_num 40 ++#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ ++#define ADCB_CH2_vect_num 41 ++#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ ++#define ADCB_CH3_vect_num 42 ++#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LUNF_vect_num 47 ++#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_HUNF_vect_num 48 ++#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPA_vect_num 49 ++#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPB_vect_num 50 ++#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPC_vect_num 51 ++#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPD_vect_num 52 ++#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ ++ ++/* TCE1 interrupt vectors */ ++#define TCE1_OVF_vect_num 53 ++#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ ++#define TCE1_ERR_vect_num 54 ++#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ ++#define TCE1_CCA_vect_num 55 ++#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ ++#define TCE1_CCB_vect_num 56 ++#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ ++ ++/* SPIE interrupt vectors */ ++#define SPIE_INT_vect_num 57 ++#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* USARTE1 interrupt vectors */ ++#define USARTE1_RXC_vect_num 61 ++#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ ++#define USARTE1_DRE_vect_num 62 ++#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ ++#define USARTE1_TXC_vect_num 63 ++#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++#define ADCA_CH1_vect_num 72 ++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ ++#define ADCA_CH2_vect_num 73 ++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ ++#define ADCA_CH3_vect_num 74 ++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LUNF_vect_num 77 ++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_HUNF_vect_num 78 ++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPA_vect_num 79 ++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPB_vect_num 80 ++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPC_vect_num 81 ++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPD_vect_num 82 ++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ ++ ++/* TCD1 interrupt vectors */ ++#define TCD1_OVF_vect_num 83 ++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ ++#define TCD1_ERR_vect_num 84 ++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ ++#define TCD1_CCA_vect_num 85 ++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ ++#define TCD1_CCB_vect_num 86 ++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* USARTD1 interrupt vectors */ ++#define USARTD1_RXC_vect_num 91 ++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ ++#define USARTD1_DRE_vect_num 92 ++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ ++#define USARTD1_TXC_vect_num 93 ++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ ++ ++/* PORTF interrupt vectors */ ++#define PORTF_INT0_vect_num 104 ++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ ++#define PORTF_INT1_vect_num 105 ++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_OVF_vect_num 108 ++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LUNF_vect_num 108 ++#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_ERR_vect_num 109 ++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_HUNF_vect_num 109 ++#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCA_vect_num 110 ++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPA_vect_num 110 ++#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCB_vect_num 111 ++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPB_vect_num 111 ++#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCC_vect_num 112 ++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPC_vect_num 112 ++#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCD_vect_num 113 ++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPD_vect_num 113 ++#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ ++ ++/* USARTF0 interrupt vectors */ ++#define USARTF0_RXC_vect_num 119 ++#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ ++#define USARTF0_DRE_vect_num 120 ++#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ ++#define USARTF0_TXC_vect_num 121 ++#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ ++ ++/* USB interrupt vectors */ ++#define USB_BUSEVENT_vect_num 125 ++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ ++#define USB_TRNCOMPL_vect_num 126 ++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (127 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (139264) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (131072) ++#define APP_SECTION_PAGE_SIZE (512) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x1E000) ++#define APPTABLE_SECTION_SIZE (8192) ++#define APPTABLE_SECTION_PAGE_SIZE (512) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x20000) ++#define BOOT_SECTION_SIZE (8192) ++#define BOOT_SECTION_PAGE_SIZE (512) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (16384) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (2048) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (8192) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (2048) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (6) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (512) ++#define USER_SIGNATURES_PAGE_SIZE (512) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (512) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 512 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 */ ++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ ++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ ++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ ++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ ++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ ++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ ++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ ++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ ++#define FUSE0_DEFAULT (0xFF) ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x97 ++#define SIGNATURE_2 0x42 ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA128A3U_H_INCLUDED */ ++ +diff --git a/include/avr/iox128a4u.h b/include/avr/iox128a4u.h +new file mode 100644 +index 0000000..1036595 +--- /dev/null ++++ b/include/avr/iox128a4u.h +@@ -0,0 +1,7240 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox128a4u.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA128A4U_H_INCLUDED ++#define _AVR_ATXMEGA128A4U_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t USBCTRL; /* USB Control Register */ ++} CLK_t; ++ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t PRPB; /* Power Reduction Port B */ ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++/* USB Prescaler Division Factor */ ++typedef enum CLK_USBPSDIV_enum ++{ ++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ ++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ ++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ ++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ ++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ ++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ ++} CLK_USBPSDIV_t; ++ ++/* USB Clock Source */ ++typedef enum CLK_USBSRC_enum ++{ ++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ ++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ ++} CLK_USBSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 2 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC2MCREF_enum ++{ ++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC2MCREF_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++ register8_t EBIOUT; /* EBI Output register */ ++ register8_t EVOUTSEL; /* Event Output Select */ ++} PORTCFG_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP02MAP_enum ++{ ++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP02MAP_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP13MAP_enum ++{ ++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP13MAP_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Clock and Event Output Port */ ++typedef enum PORTCFG_CLKEVPIN_enum ++{ ++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ ++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ ++} PORTCFG_CLKEVPIN_t; ++ ++/* EBI Address Output Port */ ++typedef enum PORTCFG_EBIADROUT_enum ++{ ++ PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ ++ PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ ++ PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ ++ PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ ++} PORTCFG_EBIADROUT_t; ++ ++/* EBI Chip Select Output Port */ ++typedef enum PORTCFG_EBICSOUT_enum ++{ ++ PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ ++} PORTCFG_EBICSOUT_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ ++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ ++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ ++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ ++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AES - AES Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* AES Module */ ++typedef struct AES_struct ++{ ++ register8_t CTRL; /* AES Control Register */ ++ register8_t STATUS; /* AES Status Register */ ++ register8_t STATE; /* AES State Register */ ++ register8_t KEY; /* AES Key Register */ ++ register8_t INTCTRL; /* AES Interrupt Control Register */ ++} AES_t; ++ ++/* Interrupt level */ ++typedef enum AES_INTLVL_enum ++{ ++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} AES_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ ++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ ++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ ++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Channel */ ++typedef struct DMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Address Control */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ ++ register8_t REPCNT; /* Channel Repeat Count */ ++ register8_t reserved_0x07; ++ register8_t SRCADDR0; /* Channel Source Address 0 */ ++ register8_t SRCADDR1; /* Channel Source Address 1 */ ++ register8_t SRCADDR2; /* Channel Source Address 2 */ ++ register8_t reserved_0x0B; ++ register8_t DESTADDR0; /* Channel Destination Address 0 */ ++ register8_t DESTADDR1; /* Channel Destination Address 1 */ ++ register8_t DESTADDR2; /* Channel Destination Address 2 */ ++ register8_t reserved_0x0F; ++} DMA_CH_t; ++ ++ ++/* DMA Controller */ ++typedef struct DMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ DMA_CH_t CH0; /* DMA Channel 0 */ ++ DMA_CH_t CH1; /* DMA Channel 1 */ ++ DMA_CH_t CH2; /* DMA Channel 2 */ ++ DMA_CH_t CH3; /* DMA Channel 3 */ ++} DMA_t; ++ ++/* Burst mode */ ++typedef enum DMA_CH_BURSTLEN_enum ++{ ++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ ++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ ++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ ++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ ++} DMA_CH_BURSTLEN_t; ++ ++/* Source address reload mode */ ++typedef enum DMA_CH_SRCRELOAD_enum ++{ ++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ ++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ ++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ ++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ ++} DMA_CH_SRCRELOAD_t; ++ ++/* Source addressing mode */ ++typedef enum DMA_CH_SRCDIR_enum ++{ ++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ ++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ ++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ ++} DMA_CH_SRCDIR_t; ++ ++/* Destination adress reload mode */ ++typedef enum DMA_CH_DESTRELOAD_enum ++{ ++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ ++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ ++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ ++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ ++} DMA_CH_DESTRELOAD_t; ++ ++/* Destination adressing mode */ ++typedef enum DMA_CH_DESTDIR_enum ++{ ++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ ++} DMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum DMA_CH_TRIGSRC_enum ++{ ++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ ++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ ++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ ++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ ++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ ++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ ++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ ++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ ++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ ++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ ++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ ++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ ++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ ++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ ++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ ++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ ++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ ++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ ++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ ++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ ++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ ++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ ++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ ++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ ++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ ++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ ++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ ++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ ++} DMA_CH_TRIGSRC_t; ++ ++/* Double buffering mode */ ++typedef enum DMA_DBUFMODE_enum ++{ ++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ ++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ ++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ ++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ ++} DMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum DMA_PRIMODE_enum ++{ ++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ ++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ ++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ ++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ ++} DMA_PRIMODE_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_ERRINTLVL_enum ++{ ++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ ++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ ++} DMA_CH_ERRINTLVL_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_TRNINTLVL_enum ++{ ++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ ++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ ++} DMA_CH_TRNINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ ++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ ++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ ++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t CH4CTRL; /* Channel 4 Control Register */ ++ register8_t CH5CTRL; /* Channel 5 Control Register */ ++ register8_t CH6CTRL; /* Channel 6 Control Register */ ++ register8_t CH7CTRL; /* Channel 7 Control Register */ ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ ++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ ++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ ++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ ++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ ++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ ++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ ++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ ++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ ++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ ++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ ++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ ++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ ++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ ++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ ++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ ++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ ++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t reserved_0x07; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ _WORDREGISTER(CH1RES); /* Channel 1 Result */ ++ _WORDREGISTER(CH2RES); /* Channel 2 Result */ ++ _WORDREGISTER(CH3RES); /* Channel 3 Result */ ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++ ADC_CH_t CH1; /* ADC Channel 1 */ ++ ADC_CH_t CH2; /* ADC Channel 2 */ ++ ADC_CH_t CH3; /* ADC Channel 3 */ ++} ADC_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ ++ ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ ++ ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ ++ ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Current Limitation Mode */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ ++} ADC_CURRLIMIT_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Channel sweep selection */ ++typedef enum ADC_SWEEP_enum ++{ ++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ ++} ADC_SWEEP_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* DMA request selection */ ++typedef enum ADC_DMASEL_enum ++{ ++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ ++} ADC_DMASEL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DAC - Digital/Analog Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Digital-to-Analog Converter */ ++typedef struct DAC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t EVCTRL; /* Event Input Control */ ++ register8_t reserved_0x04; ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0GAINCAL; /* Gain Calibration */ ++ register8_t CH0OFFSETCAL; /* Offset Calibration */ ++ register8_t CH1GAINCAL; /* Gain Calibration */ ++ register8_t CH1OFFSETCAL; /* Offset Calibration */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ ++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ ++} DAC_t; ++ ++/* Output channel selection */ ++typedef enum DAC_CHSEL_enum ++{ ++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ ++ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ ++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ ++} DAC_CHSEL_t; ++ ++/* Reference voltage selection */ ++typedef enum DAC_REFSEL_enum ++{ ++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ ++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ ++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ ++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ ++} DAC_REFSEL_t; ++ ++/* Event channel selection */ ++typedef enum DAC_EVSEL_enum ++{ ++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ ++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ ++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ ++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ ++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ ++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ ++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ ++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ ++} DAC_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* SDA Hold Time */ ++typedef enum TWI_SDAHOLD_enum ++{ ++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ ++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ ++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ ++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ ++} TWI_SDAHOLD_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USB - USB ++-------------------------------------------------------------------------- ++*/ ++ ++/* USB Endpoint */ ++typedef struct USB_EP_struct ++{ ++ register8_t STATUS; /* Endpoint Status */ ++ register8_t CTRL; /* Endpoint Control */ ++ _WORDREGISTER(CNT); /* USB Endpoint Counter */ ++ _WORDREGISTER(DATAPTR); /* Data Pointer */ ++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ ++} USB_EP_t; ++ ++ ++/* Universal Serial Bus */ ++typedef struct USB_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t FIFOWP; /* FIFO Write Pointer Register */ ++ register8_t FIFORP; /* FIFO Read Pointer Register */ ++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ ++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ ++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ ++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t reserved_0x20; ++ register8_t reserved_0x21; ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t CAL0; /* Calibration Byte 0 */ ++ register8_t CAL1; /* Calibration Byte 1 */ ++} USB_t; ++ ++ ++/* USB Endpoint Table */ ++typedef struct USB_EP_TABLE_struct ++{ ++ USB_EP_t EP0OUT; /* Endpoint 0 */ ++ USB_EP_t EP0IN; /* Endpoint 0 */ ++ USB_EP_t EP1OUT; /* Endpoint 1 */ ++ USB_EP_t EP1IN; /* Endpoint 1 */ ++ USB_EP_t EP2OUT; /* Endpoint 2 */ ++ USB_EP_t EP2IN; /* Endpoint 2 */ ++ USB_EP_t EP3OUT; /* Endpoint 3 */ ++ USB_EP_t EP3IN; /* Endpoint 3 */ ++ USB_EP_t EP4OUT; /* Endpoint 4 */ ++ USB_EP_t EP4IN; /* Endpoint 4 */ ++ USB_EP_t EP5OUT; /* Endpoint 5 */ ++ USB_EP_t EP5IN; /* Endpoint 5 */ ++ USB_EP_t EP6OUT; /* Endpoint 6 */ ++ USB_EP_t EP6IN; /* Endpoint 6 */ ++ USB_EP_t EP7OUT; /* Endpoint 7 */ ++ USB_EP_t EP7IN; /* Endpoint 7 */ ++ USB_EP_t EP8OUT; /* Endpoint 8 */ ++ USB_EP_t EP8IN; /* Endpoint 8 */ ++ USB_EP_t EP9OUT; /* Endpoint 9 */ ++ USB_EP_t EP9IN; /* Endpoint 9 */ ++ USB_EP_t EP10OUT; /* Endpoint 10 */ ++ USB_EP_t EP10IN; /* Endpoint 10 */ ++ USB_EP_t EP11OUT; /* Endpoint 11 */ ++ USB_EP_t EP11IN; /* Endpoint 11 */ ++ USB_EP_t EP12OUT; /* Endpoint 12 */ ++ USB_EP_t EP12IN; /* Endpoint 12 */ ++ USB_EP_t EP13OUT; /* Endpoint 13 */ ++ USB_EP_t EP13IN; /* Endpoint 13 */ ++ USB_EP_t EP14OUT; /* Endpoint 14 */ ++ USB_EP_t EP14IN; /* Endpoint 14 */ ++ USB_EP_t EP15OUT; /* Endpoint 15 */ ++ USB_EP_t EP15IN; /* Endpoint 15 */ ++ register8_t reserved_0x100; ++ register8_t reserved_0x101; ++ register8_t reserved_0x102; ++ register8_t reserved_0x103; ++ register8_t reserved_0x104; ++ register8_t reserved_0x105; ++ register8_t reserved_0x106; ++ register8_t reserved_0x107; ++ register8_t reserved_0x108; ++ register8_t reserved_0x109; ++ register8_t reserved_0x10A; ++ register8_t reserved_0x10B; ++ register8_t reserved_0x10C; ++ register8_t reserved_0x10D; ++ register8_t reserved_0x10E; ++ register8_t reserved_0x10F; ++ register8_t FRAMENUML; /* Frame Number Low Byte */ ++ register8_t FRAMENUMH; /* Frame Number High Byte */ ++} USB_EP_TABLE_t; ++ ++/* Interrupt level */ ++typedef enum USB_INTLVL_enum ++{ ++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} USB_INTLVL_t; ++ ++/* USB Endpoint Type */ ++typedef enum USB_EP_TYPE_enum ++{ ++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ ++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ ++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ ++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ ++} USB_EP_TYPE_t; ++ ++/* USB Endpoint Buffersize */ ++typedef enum USB_EP_BUFSIZE_enum ++{ ++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ ++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ ++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ ++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ ++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ ++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ ++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ ++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ ++} USB_EP_BUFSIZE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - I/O Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* I/O Port Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Byte Mode */ ++typedef enum TC_BYTEM_enum ++{ ++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ ++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ ++} TC_BYTEM_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC2 - 16-bit Timer/Counter type 2 ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter type 2 */ ++typedef struct TC2_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t reserved_0x03; ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t reserved_0x08; ++ register8_t CTRLF; /* Control Register F */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t LCNT; /* Low Byte Count */ ++ register8_t HCNT; /* High Byte Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t LPER; /* Low Byte Period */ ++ register8_t HPER; /* High Byte Period */ ++ register8_t LCMPA; /* Low Byte Compare A */ ++ register8_t HCMPA; /* High Byte Compare A */ ++ register8_t LCMPB; /* Low Byte Compare B */ ++ register8_t HCMPB; /* High Byte Compare B */ ++ register8_t LCMPC; /* Low Byte Compare C */ ++ register8_t HCMPC; /* High Byte Compare C */ ++ register8_t LCMPD; /* Low Byte Compare D */ ++ register8_t HCMPD; /* High Byte Compare D */ ++} TC2_t; ++ ++/* Clock Selection */ ++typedef enum TC2_CLKSEL_enum ++{ ++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC2_CLKSEL_t; ++ ++/* Byte Mode */ ++typedef enum TC2_BYTEM_enum ++{ ++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ ++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ ++} TC2_BYTEM_t; ++ ++/* High Byte Underflow Interrupt Level */ ++typedef enum TC2_HUNFINTLVL_enum ++{ ++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_HUNFINTLVL_t; ++ ++/* Low Byte Underflow Interrupt Level */ ++typedef enum TC2_LUNFINTLVL_enum ++{ ++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LUNFINTLVL_t; ++ ++/* Low Byte Compare D Interrupt Level */ ++typedef enum TC2_LCMPDINTLVL_enum ++{ ++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC2_LCMPDINTLVL_t; ++ ++/* Low Byte Compare C Interrupt Level */ ++typedef enum TC2_LCMPCINTLVL_enum ++{ ++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC2_LCMPCINTLVL_t; ++ ++/* Low Byte Compare B Interrupt Level */ ++typedef enum TC2_LCMPBINTLVL_enum ++{ ++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_LCMPBINTLVL_t; ++ ++/* Low Byte Compare A Interrupt Level */ ++typedef enum TC2_LCMPAINTLVL_enum ++{ ++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LCMPAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMD_enum ++{ ++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC2_CMD_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMDEN_enum ++{ ++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ ++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ ++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ ++} TC2_CMDEN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AWEX - Timer/Counter Advanced Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - Timer/Counter High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t reserved_0x00; ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* Timer Oscillator pin location */ ++typedef enum TOSCSEL_enum ++{ ++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ ++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ ++} TOSCSEL_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* BOD operation */ ++typedef enum BODACT_enum ++{ ++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BODACT_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WDP_enum ++{ ++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ ++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ ++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ ++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ ++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ ++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ ++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ ++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ ++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ ++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ ++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ ++} WDP_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LOCKBIT - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ ++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t USBCAL0; /* USB Calibration Byte 0 */ ++ register8_t USBCAL1; /* USB Calibration Byte 1 */ ++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ ++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ ++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ ++ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ ++ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ ++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ ++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ ++ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ ++ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++ register8_t reserved_0x40; ++ register8_t reserved_0x41; ++ register8_t reserved_0x42; ++ register8_t reserved_0x43; ++ register8_t reserved_0x44; ++ register8_t reserved_0x45; ++ register8_t reserved_0x46; ++ register8_t reserved_0x47; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define AES (*(AES_t *) 0x00C0) /* AES Module */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ ++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ ++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ ++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ ++#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ ++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ ++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++#define GPIO_GPIOR4 _SFR_MEM8(0x0004) ++#define GPIO_GPIOR5 _SFR_MEM8(0x0005) ++#define GPIO_GPIOR6 _SFR_MEM8(0x0006) ++#define GPIO_GPIOR7 _SFR_MEM8(0x0007) ++#define GPIO_GPIOR8 _SFR_MEM8(0x0008) ++#define GPIO_GPIOR9 _SFR_MEM8(0x0009) ++#define GPIO_GPIORA _SFR_MEM8(0x000A) ++#define GPIO_GPIORB _SFR_MEM8(0x000B) ++#define GPIO_GPIORC _SFR_MEM8(0x000C) ++#define GPIO_GPIORD _SFR_MEM8(0x000D) ++#define GPIO_GPIORE _SFR_MEM8(0x000E) ++#define GPIO_GPIORF _SFR_MEM8(0x000F) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++#define GPIO_GPIO4 _SFR_MEM8(0x0004) ++#define GPIO_GPIO5 _SFR_MEM8(0x0005) ++#define GPIO_GPIO6 _SFR_MEM8(0x0006) ++#define GPIO_GPIO7 _SFR_MEM8(0x0007) ++#define GPIO_GPIO8 _SFR_MEM8(0x0008) ++#define GPIO_GPIO9 _SFR_MEM8(0x0009) ++#define GPIO_GPIOA _SFR_MEM8(0x000A) ++#define GPIO_GPIOB _SFR_MEM8(0x000B) ++#define GPIO_GPIOC _SFR_MEM8(0x000C) ++#define GPIO_GPIOD _SFR_MEM8(0x000D) ++#define GPIO_GPIOE _SFR_MEM8(0x000E) ++#define GPIO_GPIOF _SFR_MEM8(0x000F) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) ++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) ++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) ++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) ++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) ++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) ++#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) ++#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) ++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) ++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) ++#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) ++#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++#define CLK_USBCTRL _SFR_MEM8(0x0044) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLL - DFLL */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPB _SFR_MEM8(0x0072) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) ++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) ++ ++/* AES - AES Module */ ++#define AES_CTRL _SFR_MEM8(0x00C0) ++#define AES_STATUS _SFR_MEM8(0x00C1) ++#define AES_STATE _SFR_MEM8(0x00C2) ++#define AES_KEY _SFR_MEM8(0x00C3) ++#define AES_INTCTRL _SFR_MEM8(0x00C4) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* DMA - DMA Controller */ ++#define DMA_CTRL _SFR_MEM8(0x0100) ++#define DMA_INTFLAGS _SFR_MEM8(0x0103) ++#define DMA_STATUS _SFR_MEM8(0x0104) ++#define DMA_TEMP _SFR_MEM16(0x0106) ++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) ++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) ++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) ++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) ++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) ++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) ++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) ++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) ++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) ++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) ++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) ++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) ++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) ++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) ++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) ++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) ++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) ++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) ++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) ++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) ++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) ++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) ++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) ++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) ++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) ++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) ++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) ++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) ++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) ++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) ++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) ++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) ++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) ++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) ++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) ++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) ++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) ++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) ++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) ++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) ++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) ++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH4MUX _SFR_MEM8(0x0184) ++#define EVSYS_CH5MUX _SFR_MEM8(0x0185) ++#define EVSYS_CH6MUX _SFR_MEM8(0x0186) ++#define EVSYS_CH7MUX _SFR_MEM8(0x0187) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) ++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) ++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) ++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CH1RES _SFR_MEM16(0x0212) ++#define ADCA_CH2RES _SFR_MEM16(0x0214) ++#define ADCA_CH3RES _SFR_MEM16(0x0216) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) ++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) ++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) ++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) ++#define ADCA_CH1_RES _SFR_MEM16(0x022C) ++#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) ++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) ++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) ++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) ++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) ++#define ADCA_CH2_RES _SFR_MEM16(0x0234) ++#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) ++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) ++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) ++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) ++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) ++#define ADCA_CH3_RES _SFR_MEM16(0x023C) ++#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) ++ ++/* DAC - Digital-to-Analog Converter */ ++#define DACB_CTRLA _SFR_MEM8(0x0320) ++#define DACB_CTRLB _SFR_MEM8(0x0321) ++#define DACB_CTRLC _SFR_MEM8(0x0322) ++#define DACB_EVCTRL _SFR_MEM8(0x0323) ++#define DACB_STATUS _SFR_MEM8(0x0325) ++#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) ++#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) ++#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) ++#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) ++#define DACB_CH0DATA _SFR_MEM16(0x0338) ++#define DACB_CH1DATA _SFR_MEM16(0x033A) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* USB - Universal Serial Bus */ ++#define USB_CTRLA _SFR_MEM8(0x04C0) ++#define USB_CTRLB _SFR_MEM8(0x04C1) ++#define USB_STATUS _SFR_MEM8(0x04C2) ++#define USB_ADDR _SFR_MEM8(0x04C3) ++#define USB_FIFOWP _SFR_MEM8(0x04C4) ++#define USB_FIFORP _SFR_MEM8(0x04C5) ++#define USB_EPPTR _SFR_MEM16(0x04C6) ++#define USB_INTCTRLA _SFR_MEM8(0x04C8) ++#define USB_INTCTRLB _SFR_MEM8(0x04C9) ++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) ++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) ++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) ++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) ++#define USB_CAL0 _SFR_MEM8(0x04FA) ++#define USB_CAL1 _SFR_MEM8(0x04FB) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_REMAP _SFR_MEM8(0x060E) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_REMAP _SFR_MEM8(0x062E) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_REMAP _SFR_MEM8(0x068E) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCC2_CTRLA _SFR_MEM8(0x0800) ++#define TCC2_CTRLB _SFR_MEM8(0x0801) ++#define TCC2_CTRLC _SFR_MEM8(0x0802) ++#define TCC2_CTRLE _SFR_MEM8(0x0804) ++#define TCC2_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC2_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC2_CTRLF _SFR_MEM8(0x0809) ++#define TCC2_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC2_LCNT _SFR_MEM8(0x0820) ++#define TCC2_HCNT _SFR_MEM8(0x0821) ++#define TCC2_LPER _SFR_MEM8(0x0826) ++#define TCC2_HPER _SFR_MEM8(0x0827) ++#define TCC2_LCMPA _SFR_MEM8(0x0828) ++#define TCC2_HCMPA _SFR_MEM8(0x0829) ++#define TCC2_LCMPB _SFR_MEM8(0x082A) ++#define TCC2_HCMPB _SFR_MEM8(0x082B) ++#define TCC2_LCMPC _SFR_MEM8(0x082C) ++#define TCC2_HCMPC _SFR_MEM8(0x082D) ++#define TCC2_LCMPD _SFR_MEM8(0x082E) ++#define TCC2_HCMPD _SFR_MEM8(0x082F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_STATUSSET _SFR_MEM8(0x0885) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1_DATA _SFR_MEM8(0x08B0) ++#define USARTC1_STATUS _SFR_MEM8(0x08B1) ++#define USARTC1_CTRLA _SFR_MEM8(0x08B3) ++#define USARTC1_CTRLB _SFR_MEM8(0x08B4) ++#define USARTC1_CTRLC _SFR_MEM8(0x08B5) ++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) ++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCD2_CTRLA _SFR_MEM8(0x0900) ++#define TCD2_CTRLB _SFR_MEM8(0x0901) ++#define TCD2_CTRLC _SFR_MEM8(0x0902) ++#define TCD2_CTRLE _SFR_MEM8(0x0904) ++#define TCD2_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD2_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD2_CTRLF _SFR_MEM8(0x0909) ++#define TCD2_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD2_LCNT _SFR_MEM8(0x0920) ++#define TCD2_HCNT _SFR_MEM8(0x0921) ++#define TCD2_LPER _SFR_MEM8(0x0926) ++#define TCD2_HPER _SFR_MEM8(0x0927) ++#define TCD2_LCMPA _SFR_MEM8(0x0928) ++#define TCD2_HCMPA _SFR_MEM8(0x0929) ++#define TCD2_LCMPB _SFR_MEM8(0x092A) ++#define TCD2_HCMPB _SFR_MEM8(0x092B) ++#define TCD2_LCMPC _SFR_MEM8(0x092C) ++#define TCD2_HCMPC _SFR_MEM8(0x092D) ++#define TCD2_LCMPD _SFR_MEM8(0x092E) ++#define TCD2_HCMPD _SFR_MEM8(0x092F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCD1_CTRLA _SFR_MEM8(0x0940) ++#define TCD1_CTRLB _SFR_MEM8(0x0941) ++#define TCD1_CTRLC _SFR_MEM8(0x0942) ++#define TCD1_CTRLD _SFR_MEM8(0x0943) ++#define TCD1_CTRLE _SFR_MEM8(0x0944) ++#define TCD1_INTCTRLA _SFR_MEM8(0x0946) ++#define TCD1_INTCTRLB _SFR_MEM8(0x0947) ++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) ++#define TCD1_CTRLFSET _SFR_MEM8(0x0949) ++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) ++#define TCD1_CTRLGSET _SFR_MEM8(0x094B) ++#define TCD1_INTFLAGS _SFR_MEM8(0x094C) ++#define TCD1_TEMP _SFR_MEM8(0x094F) ++#define TCD1_CNT _SFR_MEM16(0x0960) ++#define TCD1_PER _SFR_MEM16(0x0966) ++#define TCD1_CCA _SFR_MEM16(0x0968) ++#define TCD1_CCB _SFR_MEM16(0x096A) ++#define TCD1_PERBUF _SFR_MEM16(0x0976) ++#define TCD1_CCABUF _SFR_MEM16(0x0978) ++#define TCD1_CCBBUF _SFR_MEM16(0x097A) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESD_CTRLA _SFR_MEM8(0x0990) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD1_DATA _SFR_MEM8(0x09B0) ++#define USARTD1_STATUS _SFR_MEM8(0x09B1) ++#define USARTD1_CTRLA _SFR_MEM8(0x09B3) ++#define USARTD1_CTRLB _SFR_MEM8(0x09B4) ++#define USARTD1_CTRLC _SFR_MEM8(0x09B5) ++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) ++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESE_CTRLA _SFR_MEM8(0x0A90) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* CLK.USBCTRL bit masks and bit positions */ ++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ ++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ ++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ ++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ ++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ ++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ ++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ ++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ ++ ++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ ++#define CLK_USBSRC_gp 1 /* Clock Source group position. */ ++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ ++ ++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_USB_bm 0x40 /* USB bit mask. */ ++#define PR_USB_bp 6 /* USB bit position. */ ++ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ ++#define PR_EBI_bp 3 /* External Bus Interface bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ ++#define PR_DAC_bp 2 /* Port A DAC bit position. */ ++ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPB bit masks and bit positions */ ++/* PR_DAC Predefined. */ ++/* PR_DAC Predefined. */ ++ ++/* PR_ADC Predefined. */ ++/* PR_ADC Predefined. */ ++ ++/* PR_AC Predefined. */ ++/* PR_AC Predefined. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ ++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ ++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ ++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ ++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ ++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ ++ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ ++#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ ++ ++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ ++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ ++ ++#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ ++#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ ++ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ ++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ ++ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ ++ ++/* PORTCFG.EBIOUT bit masks and bit positions */ ++#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ ++#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ ++#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ ++#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ ++#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ ++#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ ++ ++#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ ++#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ ++#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ ++#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ ++#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ ++#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ ++ ++/* PORTCFG.EVOUTSEL bit masks and bit positions */ ++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ ++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ ++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ ++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ ++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ ++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ ++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ ++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ ++ ++/* AES - AES Module */ ++/* AES.CTRL bit masks and bit positions */ ++#define AES_START_bm 0x80 /* Start/Run bit mask. */ ++#define AES_START_bp 7 /* Start/Run bit position. */ ++ ++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ ++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ ++ ++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ ++#define AES_RESET_bp 5 /* AES Software Reset bit position. */ ++ ++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ ++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ ++ ++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ ++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ ++ ++/* AES.STATUS bit masks and bit positions */ ++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ ++#define AES_ERROR_bp 7 /* AES Error bit position. */ ++ ++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ ++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ ++ ++/* AES.INTCTRL bit masks and bit positions */ ++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define AES_INTLVL_gp 0 /* Interrupt level group position. */ ++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* DMA - DMA Controller */ ++/* DMA_CH.CTRLA bit masks and bit positions */ ++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ ++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ ++ ++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ ++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ ++ ++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ ++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ ++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ ++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ ++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ ++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ ++ ++/* DMA_CH.CTRLB bit masks and bit positions */ ++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ ++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ ++ ++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ ++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ ++ ++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ ++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ ++ ++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ ++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ ++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ ++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ ++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ ++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ ++ ++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ ++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ ++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ ++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ ++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ ++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ ++ ++/* DMA_CH.ADDRCTRL bit masks and bit positions */ ++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ ++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ ++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ ++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ ++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ ++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ ++ ++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ ++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ ++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ ++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ ++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ ++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ ++ ++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ ++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ ++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ ++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ ++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ ++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ ++ ++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ ++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ ++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ ++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ ++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ ++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ ++ ++/* DMA_CH.TRIGSRC bit masks and bit positions */ ++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++/* DMA.CTRL bit masks and bit positions */ ++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define DMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define DMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ ++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ ++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ ++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ ++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ ++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ ++ ++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ ++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ ++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ ++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ ++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ ++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ ++ ++/* DMA.INTFLAGS bit masks and bit positions */ ++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++/* DMA.STATUS bit masks and bit positions */ ++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ ++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ ++ ++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ ++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ ++ ++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ ++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ ++ ++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ ++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ ++ ++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ ++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ ++ ++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ ++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ ++ ++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ ++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ ++ ++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ ++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH4MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH5MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH6MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH7MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM Predefined. */ ++/* EVSYS_QDIRM Predefined. */ ++ ++/* EVSYS_QDIEN Predefined. */ ++/* EVSYS_QDIEN Predefined. */ ++ ++/* EVSYS_QDEN Predefined. */ ++/* EVSYS_QDEN Predefined. */ ++ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH4CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM Predefined. */ ++/* EVSYS_QDIRM Predefined. */ ++ ++/* EVSYS_QDIEN Predefined. */ ++/* EVSYS_QDIEN Predefined. */ ++ ++/* EVSYS_QDEN Predefined. */ ++/* EVSYS_QDEN Predefined. */ ++ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH5CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH6CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH7CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ ++#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ ++#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ ++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ ++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ ++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ ++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ ++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ ++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ ++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ ++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ ++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ ++ ++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ ++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ ++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ ++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ ++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ ++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ ++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ ++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ ++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ ++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ ++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ ++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ ++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ ++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ ++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ ++ ++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ ++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ ++ ++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ ++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ ++ ++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ ++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ ++ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ ++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ ++#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ ++ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ ++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ ++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ ++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ ++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ ++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ ++ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ ++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ ++ ++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ ++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ ++ ++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ ++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ ++ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* DAC - Digital/Analog Converter */ ++/* DAC.CTRLA bit masks and bit positions */ ++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ ++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ ++ ++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ ++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ ++ ++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ ++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ ++ ++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ ++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ ++ ++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define DAC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* DAC.CTRLB bit masks and bit positions */ ++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ ++#define DAC_CHSEL_gp 5 /* Channel Select group position. */ ++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ ++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ ++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ ++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ ++ ++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ ++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ ++ ++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ ++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ ++ ++/* DAC.CTRLC bit masks and bit positions */ ++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ ++#define DAC_REFSEL_gp 3 /* Reference Select group position. */ ++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ ++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ ++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ ++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ ++ ++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ ++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ ++ ++/* DAC.EVCTRL bit masks and bit positions */ ++#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ ++#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ ++ ++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ ++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ ++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ ++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ ++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ ++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ ++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ ++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ ++ ++/* DAC.STATUS bit masks and bit positions */ ++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ ++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ ++ ++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ ++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ ++ ++/* DAC.CH0GAINCAL bit masks and bit positions */ ++#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH0OFFSETCAL bit masks and bit positions */ ++#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* DAC.CH1GAINCAL bit masks and bit positions */ ++#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH1OFFSETCAL bit masks and bit positions */ ++#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ ++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HSMODE Predefined. */ ++/* AC_HSMODE Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* RTC - Real-Time Counter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* USB - USB */ ++/* USB_EP.STATUS bit masks and bit positions */ ++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ ++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ ++ ++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ ++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ ++ ++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ ++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ ++ ++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ ++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ ++ ++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ ++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ ++ ++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ ++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ ++ ++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ ++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ ++ ++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ ++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ ++ ++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ ++ ++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ ++ ++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ ++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ ++ ++/* USB_EP.CTRL bit masks and bit positions */ ++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ ++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ ++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ ++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ ++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ ++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ ++ ++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ ++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ ++ ++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ ++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ ++ ++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ ++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ ++ ++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ ++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ ++ ++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ ++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ ++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ ++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ ++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ ++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ ++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ ++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ ++ ++/* USB_EP.CNT bit masks and bit positions */ ++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ ++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ ++ ++/* USB.CTRLA bit masks and bit positions */ ++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ ++#define USB_ENABLE_bp 7 /* USB Enable bit position. */ ++ ++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ ++#define USB_SPEED_bp 6 /* Speed Select bit position. */ ++ ++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ ++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ ++ ++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ ++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ ++ ++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ ++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ ++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ ++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ ++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ ++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ ++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ ++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ ++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ ++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ ++ ++/* USB.CTRLB bit masks and bit positions */ ++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ ++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ ++ ++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ ++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ ++ ++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ ++#define USB_GNACK_bp 1 /* Global NACK bit position. */ ++ ++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ ++#define USB_ATTACH_bp 0 /* Attach bit position. */ ++ ++/* USB.STATUS bit masks and bit positions */ ++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ ++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ ++ ++#define USB_RESUME_bm 0x04 /* Resume bit mask. */ ++#define USB_RESUME_bp 2 /* Resume bit position. */ ++ ++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ ++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ ++ ++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ ++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ ++ ++/* USB.ADDR bit masks and bit positions */ ++#define USB_ADDR_gm 0x7F /* Device Address group mask. */ ++#define USB_ADDR_gp 0 /* Device Address group position. */ ++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ ++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ ++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ ++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ ++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ ++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ ++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ ++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ ++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ ++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ ++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ ++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ ++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ ++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ ++ ++/* USB.FIFOWP bit masks and bit positions */ ++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ ++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ ++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ ++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ ++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ ++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ ++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ ++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ ++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ ++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ ++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ ++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ ++ ++/* USB.FIFORP bit masks and bit positions */ ++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ ++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ ++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ ++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ ++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ ++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ ++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ ++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ ++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ ++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ ++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ ++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ ++ ++/* USB.INTCTRLA bit masks and bit positions */ ++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ ++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ ++ ++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ ++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ ++ ++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ ++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ ++ ++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ ++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ ++ ++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* USB.INTCTRLB bit masks and bit positions */ ++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ ++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ ++ ++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ ++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ ++ ++/* USB.INTFLAGSACLR bit masks and bit positions */ ++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ ++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ ++ ++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ ++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ ++ ++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ ++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ ++ ++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ ++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ ++ ++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ ++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ ++ ++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ ++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ ++ ++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ ++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ ++ ++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ ++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSASET bit masks and bit positions */ ++/* USB_SOFIF Predefined. */ ++/* USB_SOFIF Predefined. */ ++ ++/* USB_SUSPENDIF Predefined. */ ++/* USB_SUSPENDIF Predefined. */ ++ ++/* USB_RESUMEIF Predefined. */ ++/* USB_RESUMEIF Predefined. */ ++ ++/* USB_RSTIF Predefined. */ ++/* USB_RSTIF Predefined. */ ++ ++/* USB_CRCIF Predefined. */ ++/* USB_CRCIF Predefined. */ ++ ++/* USB_UNFIF Predefined. */ ++/* USB_UNFIF Predefined. */ ++ ++/* USB_OVFIF Predefined. */ ++/* USB_OVFIF Predefined. */ ++ ++/* USB_STALLIF Predefined. */ ++/* USB_STALLIF Predefined. */ ++ ++/* USB.INTFLAGSBCLR bit masks and bit positions */ ++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ ++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ ++ ++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ ++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSBSET bit masks and bit positions */ ++/* USB_TRNIF Predefined. */ ++/* USB_TRNIF Predefined. */ ++ ++/* USB_SETUPIF Predefined. */ ++/* USB_SETUPIF Predefined. */ ++ ++/* PORT - I/O Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_SPI_bm 0x20 /* SPI bit mask. */ ++#define PORT_SPI_bp 5 /* SPI bit position. */ ++ ++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ ++#define PORT_USART0_bp 4 /* USART0 bit position. */ ++ ++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ ++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ ++ ++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ ++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ ++ ++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ ++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ ++ ++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ ++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD Predefined. */ ++/* TC0_CMD Predefined. */ ++ ++/* TC0_LUPD Predefined. */ ++/* TC0_LUPD Predefined. */ ++ ++/* TC0_DIR Predefined. */ ++/* TC0_DIR Predefined. */ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV Predefined. */ ++/* TC0_CCDBV Predefined. */ ++ ++/* TC0_CCCBV Predefined. */ ++/* TC0_CCCBV Predefined. */ ++ ++/* TC0_CCBBV Predefined. */ ++/* TC0_CCBBV Predefined. */ ++ ++/* TC0_CCABV Predefined. */ ++/* TC0_CCABV Predefined. */ ++ ++/* TC0_PERBV Predefined. */ ++/* TC0_PERBV Predefined. */ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD Predefined. */ ++/* TC1_CMD Predefined. */ ++ ++/* TC1_LUPD Predefined. */ ++/* TC1_LUPD Predefined. */ ++ ++/* TC1_DIR Predefined. */ ++/* TC1_DIR Predefined. */ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV Predefined. */ ++/* TC1_CCBBV Predefined. */ ++ ++/* TC1_CCABV Predefined. */ ++/* TC1_CCABV Predefined. */ ++ ++/* TC1_PERBV Predefined. */ ++/* TC1_PERBV Predefined. */ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++/* TC2.CTRLA bit masks and bit positions */ ++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC2.CTRLB bit masks and bit positions */ ++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ ++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ ++ ++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ ++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ ++ ++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ ++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ ++ ++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ ++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ ++ ++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ ++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ ++ ++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ ++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ ++ ++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ ++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ ++ ++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ ++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ ++ ++/* TC2.CTRLC bit masks and bit positions */ ++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ ++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ ++ ++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ ++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ ++ ++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ ++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ ++ ++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ ++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ ++ ++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ ++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ ++ ++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ ++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ ++ ++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ ++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ ++ ++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ ++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ ++ ++/* TC2.CTRLE bit masks and bit positions */ ++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC2.INTCTRLA bit masks and bit positions */ ++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ ++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ ++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ ++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ ++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ ++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ ++ ++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ ++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ ++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ ++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ ++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ ++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ ++ ++/* TC2.INTCTRLB bit masks and bit positions */ ++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ ++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ ++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ ++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ ++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ ++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ ++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ ++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ ++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ ++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ ++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ ++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ ++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ ++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ ++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ ++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ ++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ ++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ ++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ ++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ ++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ ++ ++/* TC2.CTRLF bit masks and bit positions */ ++#define TC2_CMD_gm 0x0C /* Command group mask. */ ++#define TC2_CMD_gp 2 /* Command group position. */ ++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC2_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC2_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ ++#define TC2_CMDEN_gp 0 /* Command Enable group position. */ ++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ ++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ ++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ ++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ ++ ++/* TC2.INTFLAGS bit masks and bit positions */ ++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ ++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ ++ ++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ ++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ ++ ++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ ++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ ++ ++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ ++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ ++ ++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ ++ ++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ ++ ++/* AWEX - Timer/Counter Advanced Waveform Extension */ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++/* AWEX.STATUSSET bit masks and bit positions */ ++/* AWEX_FDF Predefined. */ ++/* AWEX_FDF Predefined. */ ++ ++/* AWEX_DTHSBUFV Predefined. */ ++/* AWEX_DTHSBUFV Predefined. */ ++ ++/* AWEX_DTLSBUFV Predefined. */ ++/* AWEX_DTLSBUFV Predefined. */ ++ ++/* HIRES - Timer/Counter High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ ++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* LOCKBIT - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* DMA interrupt vectors */ ++#define DMA_CH0_vect_num 6 ++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ ++#define DMA_CH1_vect_num 7 ++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ ++#define DMA_CH2_vect_num 8 ++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ ++#define DMA_CH3_vect_num 9 ++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LUNF_vect_num 14 ++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_HUNF_vect_num 15 ++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPA_vect_num 16 ++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPB_vect_num 17 ++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPC_vect_num 18 ++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPD_vect_num 19 ++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* USARTC1 interrupt vectors */ ++#define USARTC1_RXC_vect_num 28 ++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ ++#define USARTC1_DRE_vect_num 29 ++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ ++#define USARTC1_TXC_vect_num 30 ++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ ++ ++/* AES interrupt vectors */ ++#define AES_INT_vect_num 31 ++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++#define ADCA_CH1_vect_num 72 ++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ ++#define ADCA_CH2_vect_num 73 ++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ ++#define ADCA_CH3_vect_num 74 ++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LUNF_vect_num 77 ++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_HUNF_vect_num 78 ++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPA_vect_num 79 ++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPB_vect_num 80 ++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPC_vect_num 81 ++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPD_vect_num 82 ++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ ++ ++/* TCD1 interrupt vectors */ ++#define TCD1_OVF_vect_num 83 ++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ ++#define TCD1_ERR_vect_num 84 ++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ ++#define TCD1_CCA_vect_num 85 ++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ ++#define TCD1_CCB_vect_num 86 ++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* USARTD1 interrupt vectors */ ++#define USARTD1_RXC_vect_num 91 ++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ ++#define USARTD1_DRE_vect_num 92 ++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ ++#define USARTD1_TXC_vect_num 93 ++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ ++ ++/* USB interrupt vectors */ ++#define USB_BUSEVENT_vect_num 125 ++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ ++#define USB_TRNCOMPL_vect_num 126 ++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (127 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (139264) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (131072) ++#define APP_SECTION_PAGE_SIZE (256) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x1E000) ++#define APPTABLE_SECTION_SIZE (8192) ++#define APPTABLE_SECTION_PAGE_SIZE (256) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x20000) ++#define BOOT_SECTION_SIZE (8192) ++#define BOOT_SECTION_PAGE_SIZE (256) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (16384) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (2048) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (8192) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (2048) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (6) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (256) ++#define USER_SIGNATURES_PAGE_SIZE (256) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (64) ++#define PROD_SIGNATURES_PAGE_SIZE (256) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 256 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 Reserved */ ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x97 ++#define SIGNATURE_2 0x46 ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA128A4U_H_INCLUDED */ ++ +diff --git a/include/avr/iox128b1.h b/include/avr/iox128b1.h +new file mode 100644 +index 0000000..9debd27 +--- /dev/null ++++ b/include/avr/iox128b1.h +@@ -0,0 +1,6831 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox128b1.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA128B1_H_INCLUDED ++#define _AVR_ATXMEGA128B1_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t USBCTRL; /* USB Control Register */ ++} CLK_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++/* USB Prescaler Division Factor */ ++typedef enum CLK_USBPSDIV_enum ++{ ++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ ++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ ++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ ++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ ++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ ++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ ++} CLK_USBPSDIV_t; ++ ++/* USB Clock Source */ ++typedef enum CLK_USBSRC_enum ++{ ++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ ++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ ++} CLK_USBSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C0_gc = (0x01<<0), /* External Clock on port C0 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C1_gc = (0x05<<0), /* External Clock on port C1 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C2_gc = (0x09<<0), /* External Clock on port C2 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C3_gc = (0x0D<<0), /* External Clock on port C3 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C4_gc = (0x11<<0), /* External Clock on port C4 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C5_gc = (0x15<<0), /* External Clock on port C5 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C6_gc = (0x19<<0), /* External Clock on port C6 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C7_gc = (0x1D<<0), /* External Clock on port C7 - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 2 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC2MCREF_enum ++{ ++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC2MCREF_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PR - Power Reduction ++-------------------------------------------------------------------------- ++*/ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t PRPB; /* Power Reduction Port B */ ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t reserved_0x04; ++ register8_t PRPE; /* Power Reduction Port E */ ++} PR_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++ register8_t reserved_0x05; ++ register8_t EVOUTSEL; /* Event Output Select */ ++} PORTCFG_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP02MAP_enum ++{ ++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP02MAP_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP13MAP_enum ++{ ++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP13MAP_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC_gc = (0x01<<0), /* System Clock Output on Port C */ ++ PORTCFG_CLKOUT_PE_gc = (0x03<<0), /* System Clock Output on Port E */ ++} PORTCFG_CLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC_gc = (0x01<<4), /* Event Channel 0 Output on Port C */ ++ PORTCFG_EVOUT_PE_gc = (0x03<<4), /* Event Channel 0 Output on Port E */ ++} PORTCFG_EVOUT_t; ++ ++/* Clock and Event Output Port */ ++typedef enum PORTCFG_CLKEVPIN_enum ++{ ++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ ++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ ++} PORTCFG_CLKEVPIN_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<2), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<2), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<2), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<2), /* Event Channel 3 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AES - AES Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* AES Module */ ++typedef struct AES_struct ++{ ++ register8_t CTRL; /* AES Control Register */ ++ register8_t STATUS; /* AES Status Register */ ++ register8_t STATE; /* AES State Register */ ++ register8_t KEY; /* AES Key Register */ ++ register8_t INTCTRL; /* AES Interrupt Control Register */ ++} AES_t; ++ ++/* Interrupt level */ ++typedef enum AES_INTLVL_enum ++{ ++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} AES_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ ++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Channel */ ++typedef struct DMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Address Control */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ ++ register8_t REPCNT; /* Channel Repeat Count */ ++ register8_t reserved_0x07; ++ register8_t SRCADDR0; /* Channel Source Address 0 */ ++ register8_t SRCADDR1; /* Channel Source Address 1 */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t DESTADDR0; /* Channel Destination Address 0 */ ++ register8_t DESTADDR1; /* Channel Destination Address 1 */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} DMA_CH_t; ++ ++ ++/* DMA Controller */ ++typedef struct DMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TEMP); /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ DMA_CH_t CH0; /* DMA Channel 0 */ ++ DMA_CH_t CH1; /* DMA Channel 1 */ ++} DMA_t; ++ ++/* Burst mode */ ++typedef enum DMA_CH_BURSTLEN_enum ++{ ++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ ++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ ++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ ++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ ++} DMA_CH_BURSTLEN_t; ++ ++/* Source address reload mode */ ++typedef enum DMA_CH_SRCRELOAD_enum ++{ ++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ ++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ ++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ ++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ ++} DMA_CH_SRCRELOAD_t; ++ ++/* Source addressing mode */ ++typedef enum DMA_CH_SRCDIR_enum ++{ ++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ ++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ ++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ ++} DMA_CH_SRCDIR_t; ++ ++/* Destination adress reload mode */ ++typedef enum DMA_CH_DESTRELOAD_enum ++{ ++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ ++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ ++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ ++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ ++} DMA_CH_DESTRELOAD_t; ++ ++/* Destination adressing mode */ ++typedef enum DMA_CH_DESTDIR_enum ++{ ++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ ++} DMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum DMA_CH_TRIGSRC_enum ++{ ++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ ++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ ++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ ++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ ++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ ++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ ++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ ++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ ++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ ++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ ++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ ++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ ++} DMA_CH_TRIGSRC_t; ++ ++/* Double buffering mode */ ++typedef enum DMA_DBUFMODE_enum ++{ ++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ ++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ ++} DMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum DMA_PRIMODE_enum ++{ ++ DMA_PRIMODE_RR01_gc = (0x00<<0), /* Round Robin */ ++ DMA_PRIMODE_CH0RR1_gc = (0x01<<0), /* Channel 0 > channel 1 */ ++} DMA_PRIMODE_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_ERRINTLVL_enum ++{ ++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ ++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ ++} DMA_CH_ERRINTLVL_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_TRNINTLVL_enum ++{ ++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ ++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ ++} DMA_CH_TRNINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ ++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ ++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ ++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t reserved_0x07; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++} ADC_t; ++ ++/* Current Limitation */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ ++} ADC_CURRLIMIT_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ ++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ ++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ ++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++ register8_t CURRCTRL; /* Current Source Control Register */ ++ register8_t CURRCALIB; /* Current Source Calibration Register */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* SDA Hold Time */ ++typedef enum TWI_SDAHOLD_enum ++{ ++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ ++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ ++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ ++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ ++} TWI_SDAHOLD_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USB - USB ++-------------------------------------------------------------------------- ++*/ ++ ++/* USB Endpoint */ ++typedef struct USB_EP_struct ++{ ++ register8_t STATUS; /* Endpoint Status */ ++ register8_t CTRL; /* Endpoint Control */ ++ _WORDREGISTER(CNT); /* USB Endpoint Counter */ ++ _WORDREGISTER(DATAPTR); /* Data Pointer */ ++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ ++} USB_EP_t; ++ ++ ++/* Universal Serial Bus */ ++typedef struct USB_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t FIFOWP; /* FIFO Write Pointer Register */ ++ register8_t FIFORP; /* FIFO Read Pointer Register */ ++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ ++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ ++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ ++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t reserved_0x20; ++ register8_t reserved_0x21; ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t CAL0; /* Calibration Byte 0 */ ++ register8_t CAL1; /* Calibration Byte 1 */ ++} USB_t; ++ ++ ++/* USB Endpoint Table */ ++typedef struct USB_EP_TABLE_struct ++{ ++ USB_EP_t EP0OUT; /* Endpoint 0 */ ++ USB_EP_t EP0IN; /* Endpoint 0 */ ++ USB_EP_t EP1OUT; /* Endpoint 1 */ ++ USB_EP_t EP1IN; /* Endpoint 1 */ ++ USB_EP_t EP2OUT; /* Endpoint 2 */ ++ USB_EP_t EP2IN; /* Endpoint 2 */ ++ USB_EP_t EP3OUT; /* Endpoint 3 */ ++ USB_EP_t EP3IN; /* Endpoint 3 */ ++ USB_EP_t EP4OUT; /* Endpoint 4 */ ++ USB_EP_t EP4IN; /* Endpoint 4 */ ++ USB_EP_t EP5OUT; /* Endpoint 5 */ ++ USB_EP_t EP5IN; /* Endpoint 5 */ ++ USB_EP_t EP6OUT; /* Endpoint 6 */ ++ USB_EP_t EP6IN; /* Endpoint 6 */ ++ USB_EP_t EP7OUT; /* Endpoint 7 */ ++ USB_EP_t EP7IN; /* Endpoint 7 */ ++ USB_EP_t EP8OUT; /* Endpoint 8 */ ++ USB_EP_t EP8IN; /* Endpoint 8 */ ++ USB_EP_t EP9OUT; /* Endpoint 9 */ ++ USB_EP_t EP9IN; /* Endpoint 9 */ ++ USB_EP_t EP10OUT; /* Endpoint 10 */ ++ USB_EP_t EP10IN; /* Endpoint 10 */ ++ USB_EP_t EP11OUT; /* Endpoint 11 */ ++ USB_EP_t EP11IN; /* Endpoint 11 */ ++ USB_EP_t EP12OUT; /* Endpoint 12 */ ++ USB_EP_t EP12IN; /* Endpoint 12 */ ++ USB_EP_t EP13OUT; /* Endpoint 13 */ ++ USB_EP_t EP13IN; /* Endpoint 13 */ ++ USB_EP_t EP14OUT; /* Endpoint 14 */ ++ USB_EP_t EP14IN; /* Endpoint 14 */ ++ USB_EP_t EP15OUT; /* Endpoint 15 */ ++ USB_EP_t EP15IN; /* Endpoint 15 */ ++ register8_t reserved_0x100; ++ register8_t reserved_0x101; ++ register8_t reserved_0x102; ++ register8_t reserved_0x103; ++ register8_t reserved_0x104; ++ register8_t reserved_0x105; ++ register8_t reserved_0x106; ++ register8_t reserved_0x107; ++ register8_t reserved_0x108; ++ register8_t reserved_0x109; ++ register8_t reserved_0x10A; ++ register8_t reserved_0x10B; ++ register8_t reserved_0x10C; ++ register8_t reserved_0x10D; ++ register8_t reserved_0x10E; ++ register8_t reserved_0x10F; ++ register8_t FRAMENUML; /* Frame Number Low Byte */ ++ register8_t FRAMENUMH; /* Frame Number High Byte */ ++} USB_EP_TABLE_t; ++ ++/* Interrupt level */ ++typedef enum USB_INTLVL_enum ++{ ++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} USB_INTLVL_t; ++ ++/* USB Endpoint Type */ ++typedef enum USB_EP_TYPE_enum ++{ ++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ ++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ ++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ ++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ ++} USB_EP_TYPE_t; ++ ++/* USB Endpoint Buffersize */ ++typedef enum USB_EP_BUFSIZE_enum ++{ ++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ ++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ ++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ ++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ ++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ ++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ ++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ ++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ ++} USB_EP_BUFSIZE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - I/O Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* I/O Port Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Byte Mode */ ++typedef enum TC_BYTEM_enum ++{ ++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ ++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ ++} TC_BYTEM_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC2 - 16-bit Timer/Counter type 2 ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter type 2 */ ++typedef struct TC2_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t reserved_0x03; ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t reserved_0x08; ++ register8_t CTRLF; /* Control Register F */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t LCNT; /* Low Byte Count */ ++ register8_t HCNT; /* High Byte Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t LPER; /* Low Byte Period */ ++ register8_t HPER; /* High Byte Period */ ++ register8_t LCMPA; /* Low Byte Compare A */ ++ register8_t HCMPA; /* High Byte Compare A */ ++ register8_t LCMPB; /* Low Byte Compare B */ ++ register8_t HCMPB; /* High Byte Compare B */ ++ register8_t LCMPC; /* Low Byte Compare C */ ++ register8_t HCMPC; /* High Byte Compare C */ ++ register8_t LCMPD; /* Low Byte Compare D */ ++ register8_t HCMPD; /* High Byte Compare D */ ++} TC2_t; ++ ++/* Clock Selection */ ++typedef enum TC2_CLKSEL_enum ++{ ++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC2_CLKSEL_t; ++ ++/* Byte Mode */ ++typedef enum TC2_BYTEM_enum ++{ ++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ ++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ ++} TC2_BYTEM_t; ++ ++/* High Byte Underflow Interrupt Level */ ++typedef enum TC2_HUNFINTLVL_enum ++{ ++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_HUNFINTLVL_t; ++ ++/* Low Byte Underflow Interrupt Level */ ++typedef enum TC2_LUNFINTLVL_enum ++{ ++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LUNFINTLVL_t; ++ ++/* Low Byte Compare D Interrupt Level */ ++typedef enum TC2_LCMPDINTLVL_enum ++{ ++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC2_LCMPDINTLVL_t; ++ ++/* Low Byte Compare C Interrupt Level */ ++typedef enum TC2_LCMPCINTLVL_enum ++{ ++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC2_LCMPCINTLVL_t; ++ ++/* Low Byte Compare B Interrupt Level */ ++typedef enum TC2_LCMPBINTLVL_enum ++{ ++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_LCMPBINTLVL_t; ++ ++/* Low Byte Compare A Interrupt Level */ ++typedef enum TC2_LCMPAINTLVL_enum ++{ ++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LCMPAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMD_enum ++{ ++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC2_CMD_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMDEN_enum ++{ ++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ ++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ ++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ ++} TC2_CMDEN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AWEX - Timer/Counter Advanced Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - Timer/Counter High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LCD - LCD Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* LCD Controller */ ++typedef struct LCD_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t INTCTRL; /* Interrupt Enable Register */ ++ register8_t INTFLAG; /* Interrupt Flag Register */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t CTRLF; /* Control Register F */ ++ register8_t CTRLG; /* Control Register G */ ++ register8_t CTRLH; /* Control Register H */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t DATA0; /* LCD Data Register 0 */ ++ register8_t DATA1; /* LCD Data Register 1 */ ++ register8_t DATA2; /* LCD Data Register 2 */ ++ register8_t DATA3; /* LCD Data Register 3 */ ++ register8_t DATA4; /* LCD Data Register 4 */ ++ register8_t DATA5; /* LCD Data Register 5 */ ++ register8_t DATA6; /* LCD Data Register 6 */ ++ register8_t DATA7; /* LCD Data Register 7 */ ++ register8_t DATA8; /* LCD Data Register 8 */ ++ register8_t DATA9; /* LCD Data Register 9 */ ++ register8_t DATA10; /* LCD Data Register 10 */ ++ register8_t DATA11; /* LCD Data Register 11 */ ++ register8_t DATA12; /* LCD Data Register 12 */ ++ register8_t DATA13; /* LCD Data Register 13 */ ++ register8_t DATA14; /* LCD Data Register 14 */ ++ register8_t DATA15; /* LCD Data Register 15 */ ++ register8_t DATA16; /* LCD Data Register 16 */ ++ register8_t DATA17; /* LCD Data Register 17 */ ++ register8_t DATA18; /* LCD Data Register 18 */ ++ register8_t DATA19; /* LCD Data Register 19 */ ++} LCD_t; ++ ++/* LCD Blink Rate */ ++typedef enum LCD_BLINKRATE_enum ++{ ++ LCD_BLINKRATE_4Hz_gc = (0x00<<0), /* 4Hz Blink Rate */ ++ LCD_BLINKRATE_2Hz_gc = (0x01<<0), /* 2Hz Blink Rate */ ++ LCD_BLINKRATE_1Hz_gc = (0x02<<0), /* 1Hz Blink Rate */ ++ LCD_BLINKRATE_0Hz5_gc = (0x03<<0), /* 0.5Hz Blink Rate */ ++} LCD_BLINKRATE_t; ++ ++/* LCD Clock Divide */ ++typedef enum LCD_CLKDIV_enum ++{ ++ LCD_CLKDIV_DivBy1_gc = (0x00<<4), /* frame rate of 256 Hz */ ++ LCD_CLKDIV_DivBy2_gc = (0x01<<4), /* frame rate of 128 Hz */ ++ LCD_CLKDIV_DivBy3_gc = (0x02<<4), /* frame rate of 83.5 Hz */ ++ LCD_CLKDIV_DivBy4_gc = (0x03<<4), /* frame rate of 64 Hz */ ++ LCD_CLKDIV_DivBy5_gc = (0x04<<4), /* frame rate of 51.2 Hz */ ++ LCD_CLKDIV_DivBy6_gc = (0x05<<4), /* frame rate of 42.7 Hz */ ++ LCD_CLKDIV_DivBy7_gc = (0x06<<4), /* frame rate of 36.6 Hz */ ++ LCD_CLKDIV_DivBy8_gc = (0x07<<4), /* frame rate of 32 Hz */ ++} LCD_CLKDIV_t; ++ ++/* Duty Select */ ++typedef enum LCD_DUTY_enum ++{ ++ LCD_DUTY_1_4_gc = (0x00<<0), /* Duty=1/4, Bias=1/3, COM0:3 */ ++ LCD_DUTY_Static_gc = (0x01<<0), /* Duty=Static, Bias=Static, COM0 */ ++ LCD_DUTY_1_2_gc = (0x02<<0), /* Duty=1/2, Bias=1/3, COM0:1 */ ++ LCD_DUTY_1_3_gc = (0x03<<0), /* Duty=1/3, Bias=1/3, COM0:2 */ ++} LCD_DUTY_t; ++ ++/* LCD Prescaler Select */ ++typedef enum LCD_PRESC_enum ++{ ++ LCD_PRESC_8_gc = (0x00<<7), /* clk_lcd/8 */ ++ LCD_PRESC_16_gc = (0x01<<7), /* clk_lcd/16 */ ++} LCD_PRESC_t; ++ ++/* Type of Digit */ ++typedef enum LCD_TDG_enum ++{ ++ LCD_TDG_7S_3C_gc = (0x00<<6), /* 7-segment with 3 COMs */ ++ LCD_TDG_7S_4C_gc = (0x01<<6), /* 7-segment with 4 COMs */ ++ LCD_TDG_14S_4C_gc = (0x02<<6), /* 14-segment with 4 COMs */ ++ LCD_TDG_16S_3C_gc = (0x03<<6), /* 16-segment with 3 COMs */ ++} LCD_TDG_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t FUSEBYTE0; /* JTAG User ID */ ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* Timer Oscillator pin location */ ++typedef enum TOSCSEL_enum ++{ ++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ ++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ ++} TOSCSEL_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* BOD operation */ ++typedef enum BODACT_enum ++{ ++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BODACT_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WDP_enum ++{ ++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ ++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ ++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ ++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ ++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ ++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ ++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ ++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ ++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ ++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ ++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ ++} WDP_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LOCKBIT - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ ++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t USBCAL0; /* USB Calibration Byte 0 */ ++ register8_t USBCAL1; /* USB Calibration Byte 1 */ ++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ ++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++ register8_t reserved_0x40; ++ register8_t reserved_0x41; ++ register8_t reserved_0x42; ++ register8_t reserved_0x43; ++ register8_t reserved_0x44; ++ register8_t reserved_0x45; ++ register8_t reserved_0x46; ++ register8_t reserved_0x47; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define AES (*(AES_t *) 0x00C0) /* AES Module */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ ++#define PORTG (*(PORT_t *) 0x06C0) /* I/O Ports */ ++#define PORTM (*(PORT_t *) 0x0760) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ ++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ ++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define LCD (*(LCD_t *) 0x0D00) /* LCD Controller */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) ++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) ++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) ++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) ++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++#define CLK_USBCTRL _SFR_MEM8(0x0044) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLL - DFLL */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPB _SFR_MEM8(0x0072) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPE _SFR_MEM8(0x0075) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) ++ ++/* AES - AES Module */ ++#define AES_CTRL _SFR_MEM8(0x00C0) ++#define AES_STATUS _SFR_MEM8(0x00C1) ++#define AES_STATE _SFR_MEM8(0x00C2) ++#define AES_KEY _SFR_MEM8(0x00C3) ++#define AES_INTCTRL _SFR_MEM8(0x00C4) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* DMA - DMA Controller */ ++#define DMA_CTRL _SFR_MEM8(0x0100) ++#define DMA_INTFLAGS _SFR_MEM8(0x0103) ++#define DMA_STATUS _SFR_MEM8(0x0104) ++#define DMA_TEMP _SFR_MEM16(0x0106) ++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) ++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) ++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) ++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) ++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) ++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) ++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) ++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) ++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) ++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) ++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) ++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) ++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) ++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCB_CTRLA _SFR_MEM8(0x0240) ++#define ADCB_CTRLB _SFR_MEM8(0x0241) ++#define ADCB_REFCTRL _SFR_MEM8(0x0242) ++#define ADCB_EVCTRL _SFR_MEM8(0x0243) ++#define ADCB_PRESCALER _SFR_MEM8(0x0244) ++#define ADCB_INTFLAGS _SFR_MEM8(0x0246) ++#define ADCB_TEMP _SFR_MEM8(0x0247) ++#define ADCB_SAMPCTRL _SFR_MEM8(0x0248) ++#define ADCB_CAL _SFR_MEM16(0x024C) ++#define ADCB_CH0RES _SFR_MEM16(0x0250) ++#define ADCB_CMP _SFR_MEM16(0x0258) ++#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) ++#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) ++#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) ++#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) ++#define ADCB_CH0_RES _SFR_MEM16(0x0264) ++#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++#define ACA_CURRCTRL _SFR_MEM8(0x0388) ++#define ACA_CURRCALIB _SFR_MEM8(0x0389) ++ ++/* AC - Analog Comparator */ ++#define ACB_AC0CTRL _SFR_MEM8(0x0390) ++#define ACB_AC1CTRL _SFR_MEM8(0x0391) ++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) ++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) ++#define ACB_CTRLA _SFR_MEM8(0x0394) ++#define ACB_CTRLB _SFR_MEM8(0x0395) ++#define ACB_WINCTRL _SFR_MEM8(0x0396) ++#define ACB_STATUS _SFR_MEM8(0x0397) ++#define ACB_CURRCTRL _SFR_MEM8(0x0398) ++#define ACB_CURRCALIB _SFR_MEM8(0x0399) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* USB - Universal Serial Bus */ ++#define USB_CTRLA _SFR_MEM8(0x04C0) ++#define USB_CTRLB _SFR_MEM8(0x04C1) ++#define USB_STATUS _SFR_MEM8(0x04C2) ++#define USB_ADDR _SFR_MEM8(0x04C3) ++#define USB_FIFOWP _SFR_MEM8(0x04C4) ++#define USB_FIFORP _SFR_MEM8(0x04C5) ++#define USB_EPPTR _SFR_MEM16(0x04C6) ++#define USB_INTCTRLA _SFR_MEM8(0x04C8) ++#define USB_INTCTRLB _SFR_MEM8(0x04C9) ++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) ++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) ++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) ++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) ++#define USB_CAL0 _SFR_MEM8(0x04FA) ++#define USB_CAL1 _SFR_MEM8(0x04FB) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_REMAP _SFR_MEM8(0x060E) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_REMAP _SFR_MEM8(0x062E) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_REMAP _SFR_MEM8(0x068E) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORT - I/O Ports */ ++#define PORTG_DIR _SFR_MEM8(0x06C0) ++#define PORTG_DIRSET _SFR_MEM8(0x06C1) ++#define PORTG_DIRCLR _SFR_MEM8(0x06C2) ++#define PORTG_DIRTGL _SFR_MEM8(0x06C3) ++#define PORTG_OUT _SFR_MEM8(0x06C4) ++#define PORTG_OUTSET _SFR_MEM8(0x06C5) ++#define PORTG_OUTCLR _SFR_MEM8(0x06C6) ++#define PORTG_OUTTGL _SFR_MEM8(0x06C7) ++#define PORTG_IN _SFR_MEM8(0x06C8) ++#define PORTG_INTCTRL _SFR_MEM8(0x06C9) ++#define PORTG_INT0MASK _SFR_MEM8(0x06CA) ++#define PORTG_INT1MASK _SFR_MEM8(0x06CB) ++#define PORTG_INTFLAGS _SFR_MEM8(0x06CC) ++#define PORTG_REMAP _SFR_MEM8(0x06CE) ++#define PORTG_PIN0CTRL _SFR_MEM8(0x06D0) ++#define PORTG_PIN1CTRL _SFR_MEM8(0x06D1) ++#define PORTG_PIN2CTRL _SFR_MEM8(0x06D2) ++#define PORTG_PIN3CTRL _SFR_MEM8(0x06D3) ++#define PORTG_PIN4CTRL _SFR_MEM8(0x06D4) ++#define PORTG_PIN5CTRL _SFR_MEM8(0x06D5) ++#define PORTG_PIN6CTRL _SFR_MEM8(0x06D6) ++#define PORTG_PIN7CTRL _SFR_MEM8(0x06D7) ++ ++/* PORT - I/O Ports */ ++#define PORTM_DIR _SFR_MEM8(0x0760) ++#define PORTM_DIRSET _SFR_MEM8(0x0761) ++#define PORTM_DIRCLR _SFR_MEM8(0x0762) ++#define PORTM_DIRTGL _SFR_MEM8(0x0763) ++#define PORTM_OUT _SFR_MEM8(0x0764) ++#define PORTM_OUTSET _SFR_MEM8(0x0765) ++#define PORTM_OUTCLR _SFR_MEM8(0x0766) ++#define PORTM_OUTTGL _SFR_MEM8(0x0767) ++#define PORTM_IN _SFR_MEM8(0x0768) ++#define PORTM_INTCTRL _SFR_MEM8(0x0769) ++#define PORTM_INT0MASK _SFR_MEM8(0x076A) ++#define PORTM_INT1MASK _SFR_MEM8(0x076B) ++#define PORTM_INTFLAGS _SFR_MEM8(0x076C) ++#define PORTM_REMAP _SFR_MEM8(0x076E) ++#define PORTM_PIN0CTRL _SFR_MEM8(0x0770) ++#define PORTM_PIN1CTRL _SFR_MEM8(0x0771) ++#define PORTM_PIN2CTRL _SFR_MEM8(0x0772) ++#define PORTM_PIN3CTRL _SFR_MEM8(0x0773) ++#define PORTM_PIN4CTRL _SFR_MEM8(0x0774) ++#define PORTM_PIN5CTRL _SFR_MEM8(0x0775) ++#define PORTM_PIN6CTRL _SFR_MEM8(0x0776) ++#define PORTM_PIN7CTRL _SFR_MEM8(0x0777) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCC2_CTRLA _SFR_MEM8(0x0800) ++#define TCC2_CTRLB _SFR_MEM8(0x0801) ++#define TCC2_CTRLC _SFR_MEM8(0x0802) ++#define TCC2_CTRLE _SFR_MEM8(0x0804) ++#define TCC2_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC2_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC2_CTRLF _SFR_MEM8(0x0809) ++#define TCC2_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC2_LCNT _SFR_MEM8(0x0820) ++#define TCC2_HCNT _SFR_MEM8(0x0821) ++#define TCC2_LPER _SFR_MEM8(0x0826) ++#define TCC2_HPER _SFR_MEM8(0x0827) ++#define TCC2_LCMPA _SFR_MEM8(0x0828) ++#define TCC2_HCMPA _SFR_MEM8(0x0829) ++#define TCC2_LCMPB _SFR_MEM8(0x082A) ++#define TCC2_HCMPB _SFR_MEM8(0x082B) ++#define TCC2_LCMPC _SFR_MEM8(0x082C) ++#define TCC2_HCMPC _SFR_MEM8(0x082D) ++#define TCC2_LCMPD _SFR_MEM8(0x082E) ++#define TCC2_HCMPD _SFR_MEM8(0x082F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_STATUSSET _SFR_MEM8(0x0885) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCE2_CTRLA _SFR_MEM8(0x0A00) ++#define TCE2_CTRLB _SFR_MEM8(0x0A01) ++#define TCE2_CTRLC _SFR_MEM8(0x0A02) ++#define TCE2_CTRLE _SFR_MEM8(0x0A04) ++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE2_CTRLF _SFR_MEM8(0x0A09) ++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE2_LCNT _SFR_MEM8(0x0A20) ++#define TCE2_HCNT _SFR_MEM8(0x0A21) ++#define TCE2_LPER _SFR_MEM8(0x0A26) ++#define TCE2_HPER _SFR_MEM8(0x0A27) ++#define TCE2_LCMPA _SFR_MEM8(0x0A28) ++#define TCE2_HCMPA _SFR_MEM8(0x0A29) ++#define TCE2_LCMPB _SFR_MEM8(0x0A2A) ++#define TCE2_HCMPB _SFR_MEM8(0x0A2B) ++#define TCE2_LCMPC _SFR_MEM8(0x0A2C) ++#define TCE2_HCMPC _SFR_MEM8(0x0A2D) ++#define TCE2_LCMPD _SFR_MEM8(0x0A2E) ++#define TCE2_HCMPD _SFR_MEM8(0x0A2F) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* LCD - LCD Controller */ ++#define LCD_CTRLA _SFR_MEM8(0x0D00) ++#define LCD_CTRLB _SFR_MEM8(0x0D01) ++#define LCD_CTRLC _SFR_MEM8(0x0D02) ++#define LCD_INTCTRL _SFR_MEM8(0x0D03) ++#define LCD_INTFLAG _SFR_MEM8(0x0D04) ++#define LCD_CTRLD _SFR_MEM8(0x0D05) ++#define LCD_CTRLE _SFR_MEM8(0x0D06) ++#define LCD_CTRLF _SFR_MEM8(0x0D07) ++#define LCD_CTRLG _SFR_MEM8(0x0D08) ++#define LCD_CTRLH _SFR_MEM8(0x0D09) ++#define LCD_DATA0 _SFR_MEM8(0x0D10) ++#define LCD_DATA1 _SFR_MEM8(0x0D11) ++#define LCD_DATA2 _SFR_MEM8(0x0D12) ++#define LCD_DATA3 _SFR_MEM8(0x0D13) ++#define LCD_DATA4 _SFR_MEM8(0x0D14) ++#define LCD_DATA5 _SFR_MEM8(0x0D15) ++#define LCD_DATA6 _SFR_MEM8(0x0D16) ++#define LCD_DATA7 _SFR_MEM8(0x0D17) ++#define LCD_DATA8 _SFR_MEM8(0x0D18) ++#define LCD_DATA9 _SFR_MEM8(0x0D19) ++#define LCD_DATA10 _SFR_MEM8(0x0D1A) ++#define LCD_DATA11 _SFR_MEM8(0x0D1B) ++#define LCD_DATA12 _SFR_MEM8(0x0D1C) ++#define LCD_DATA13 _SFR_MEM8(0x0D1D) ++#define LCD_DATA14 _SFR_MEM8(0x0D1E) ++#define LCD_DATA15 _SFR_MEM8(0x0D1F) ++#define LCD_DATA16 _SFR_MEM8(0x0D20) ++#define LCD_DATA17 _SFR_MEM8(0x0D21) ++#define LCD_DATA18 _SFR_MEM8(0x0D22) ++#define LCD_DATA19 _SFR_MEM8(0x0D23) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* CLK.USBCTRL bit masks and bit positions */ ++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ ++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ ++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ ++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ ++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ ++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ ++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ ++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ ++ ++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ ++#define CLK_USBSRC_gp 1 /* Clock Source group position. */ ++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ ++ ++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ ++#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* PR - Power Reduction */ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_LCD_bm 0x80 /* LCD Module bit mask. */ ++#define PR_LCD_bp 7 /* LCD Module bit position. */ ++ ++#define PR_USB_bm 0x40 /* USB bit mask. */ ++#define PR_USB_bp 6 /* USB bit position. */ ++ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPB bit masks and bit positions */ ++/* PR_ADC Predefined. */ ++/* PR_ADC Predefined. */ ++ ++/* PR_AC Predefined. */ ++/* PR_AC Predefined. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ ++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ ++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ ++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ ++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ ++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ ++ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ ++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ ++ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ ++ ++/* PORTCFG.EVOUTSEL bit masks and bit positions */ ++#define PORTCFG_EVOUTSEL_bm 0x04 /* Event Output Select bit mask. */ ++#define PORTCFG_EVOUTSEL_bp 2 /* Event Output Select bit position. */ ++ ++/* AES - AES Module */ ++/* AES.CTRL bit masks and bit positions */ ++#define AES_START_bm 0x80 /* Start/Run bit mask. */ ++#define AES_START_bp 7 /* Start/Run bit position. */ ++ ++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ ++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ ++ ++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ ++#define AES_RESET_bp 5 /* AES Software Reset bit position. */ ++ ++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ ++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ ++ ++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ ++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ ++ ++/* AES.STATUS bit masks and bit positions */ ++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ ++#define AES_ERROR_bp 7 /* AES Error bit position. */ ++ ++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ ++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ ++ ++/* AES.INTCTRL bit masks and bit positions */ ++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define AES_INTLVL_gp 0 /* Interrupt level group position. */ ++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* DMA - DMA Controller */ ++/* DMA_CH.CTRLA bit masks and bit positions */ ++#define DMA_CH_CHEN_bm 0x80 /* Channel Enable bit mask. */ ++#define DMA_CH_CHEN_bp 7 /* Channel Enable bit position. */ ++ ++#define DMA_CH_CHRST_bm 0x40 /* Channel Software Reset bit mask. */ ++#define DMA_CH_CHRST_bp 6 /* Channel Software Reset bit position. */ ++ ++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ ++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ ++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ ++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ ++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ ++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ ++ ++/* DMA_CH.CTRLB bit masks and bit positions */ ++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ ++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ ++ ++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ ++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ ++ ++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ ++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ ++ ++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ ++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ ++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ ++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ ++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ ++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ ++ ++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ ++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ ++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ ++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ ++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ ++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ ++ ++/* DMA_CH.ADDRCTRL bit masks and bit positions */ ++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ ++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ ++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ ++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ ++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ ++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ ++ ++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ ++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ ++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ ++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ ++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ ++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ ++ ++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ ++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ ++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ ++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ ++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ ++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ ++ ++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ ++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ ++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ ++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ ++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ ++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ ++ ++/* DMA_CH.TRIGSRC bit masks and bit positions */ ++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++/* DMA.CTRL bit masks and bit positions */ ++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define DMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define DMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define DMA_DBUFMODE_bm 0x04 /* Double Buffering Mode bit mask. */ ++#define DMA_DBUFMODE_bp 2 /* Double Buffering Mode bit position. */ ++ ++#define DMA_PRIMODE_bm 0x01 /* Channel Priority Mode bit mask. */ ++#define DMA_PRIMODE_bp 0 /* Channel Priority Mode bit position. */ ++ ++/* DMA.INTFLAGS bit masks and bit positions */ ++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++/* DMA.STATUS bit masks and bit positions */ ++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ ++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ ++ ++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ ++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ ++ ++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ ++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ ++ ++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ ++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ ++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ ++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ ++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ ++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ ++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ ++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ ++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ ++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ ++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ ++ ++#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */ ++#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */ ++#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ ++#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */ ++#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ ++#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */ ++#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ ++#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */ ++#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ ++#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ ++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* ADC.SAMPCTRL bit masks and bit positions */ ++#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ ++#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ ++#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ ++#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ ++#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ ++#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ ++#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ ++#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ ++#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ ++#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ ++#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ ++#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ ++#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ ++#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* AC.CURRCTRL bit masks and bit positions */ ++#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ ++#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ ++ ++#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ ++#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ ++ ++#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ ++#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ ++ ++#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ ++#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ ++ ++/* AC.CURRCALIB bit masks and bit positions */ ++#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ ++#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ ++#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ ++#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ ++#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ ++#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ ++#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ ++#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ ++#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ ++#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ ++ ++/* RTC - Real-Time Counter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* USB - USB */ ++/* USB_EP.STATUS bit masks and bit positions */ ++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ ++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ ++ ++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ ++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ ++ ++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ ++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ ++ ++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ ++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ ++ ++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ ++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ ++ ++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ ++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ ++ ++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ ++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ ++ ++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ ++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ ++ ++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ ++ ++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ ++ ++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ ++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ ++ ++/* USB_EP.CTRL bit masks and bit positions */ ++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ ++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ ++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ ++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ ++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ ++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ ++ ++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ ++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ ++ ++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ ++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ ++ ++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ ++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ ++ ++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ ++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ ++ ++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ ++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ ++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ ++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ ++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ ++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ ++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ ++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ ++ ++/* USB_EP.CNT bit masks and bit positions */ ++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ ++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ ++ ++/* USB.CTRLA bit masks and bit positions */ ++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ ++#define USB_ENABLE_bp 7 /* USB Enable bit position. */ ++ ++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ ++#define USB_SPEED_bp 6 /* Speed Select bit position. */ ++ ++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ ++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ ++ ++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ ++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ ++ ++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ ++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ ++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ ++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ ++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ ++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ ++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ ++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ ++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ ++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ ++ ++/* USB.CTRLB bit masks and bit positions */ ++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ ++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ ++ ++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ ++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ ++ ++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ ++#define USB_GNACK_bp 1 /* Global NACK bit position. */ ++ ++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ ++#define USB_ATTACH_bp 0 /* Attach bit position. */ ++ ++/* USB.STATUS bit masks and bit positions */ ++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ ++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ ++ ++#define USB_RESUME_bm 0x04 /* Resume bit mask. */ ++#define USB_RESUME_bp 2 /* Resume bit position. */ ++ ++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ ++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ ++ ++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ ++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ ++ ++/* USB.ADDR bit masks and bit positions */ ++#define USB_ADDR_gm 0x7F /* Device Address group mask. */ ++#define USB_ADDR_gp 0 /* Device Address group position. */ ++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ ++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ ++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ ++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ ++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ ++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ ++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ ++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ ++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ ++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ ++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ ++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ ++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ ++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ ++ ++/* USB.FIFOWP bit masks and bit positions */ ++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ ++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ ++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ ++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ ++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ ++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ ++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ ++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ ++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ ++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ ++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ ++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ ++ ++/* USB.FIFORP bit masks and bit positions */ ++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ ++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ ++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ ++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ ++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ ++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ ++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ ++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ ++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ ++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ ++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ ++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ ++ ++/* USB.INTCTRLA bit masks and bit positions */ ++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ ++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ ++ ++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ ++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ ++ ++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ ++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ ++ ++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ ++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ ++ ++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* USB.INTCTRLB bit masks and bit positions */ ++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ ++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ ++ ++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ ++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ ++ ++/* USB.INTFLAGSACLR bit masks and bit positions */ ++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ ++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ ++ ++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ ++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ ++ ++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ ++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ ++ ++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ ++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ ++ ++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ ++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ ++ ++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ ++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ ++ ++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ ++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ ++ ++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ ++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSASET bit masks and bit positions */ ++/* USB_SOFIF Predefined. */ ++/* USB_SOFIF Predefined. */ ++ ++/* USB_SUSPENDIF Predefined. */ ++/* USB_SUSPENDIF Predefined. */ ++ ++/* USB_RESUMEIF Predefined. */ ++/* USB_RESUMEIF Predefined. */ ++ ++/* USB_RSTIF Predefined. */ ++/* USB_RSTIF Predefined. */ ++ ++/* USB_CRCIF Predefined. */ ++/* USB_CRCIF Predefined. */ ++ ++/* USB_UNFIF Predefined. */ ++/* USB_UNFIF Predefined. */ ++ ++/* USB_OVFIF Predefined. */ ++/* USB_OVFIF Predefined. */ ++ ++/* USB_STALLIF Predefined. */ ++/* USB_STALLIF Predefined. */ ++ ++/* USB.INTFLAGSBCLR bit masks and bit positions */ ++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ ++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ ++ ++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ ++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSBSET bit masks and bit positions */ ++/* USB_TRNIF Predefined. */ ++/* USB_TRNIF Predefined. */ ++ ++/* USB_SETUPIF Predefined. */ ++/* USB_SETUPIF Predefined. */ ++ ++/* PORT - I/O Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_SPI_bm 0x20 /* SPI bit mask. */ ++#define PORT_SPI_bp 5 /* SPI bit position. */ ++ ++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ ++#define PORT_USART0_bp 4 /* USART0 bit position. */ ++ ++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ ++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ ++ ++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ ++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ ++ ++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ ++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ ++ ++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ ++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD Predefined. */ ++/* TC0_CMD Predefined. */ ++ ++/* TC0_LUPD Predefined. */ ++/* TC0_LUPD Predefined. */ ++ ++/* TC0_DIR Predefined. */ ++/* TC0_DIR Predefined. */ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV Predefined. */ ++/* TC0_CCDBV Predefined. */ ++ ++/* TC0_CCCBV Predefined. */ ++/* TC0_CCCBV Predefined. */ ++ ++/* TC0_CCBBV Predefined. */ ++/* TC0_CCBBV Predefined. */ ++ ++/* TC0_CCABV Predefined. */ ++/* TC0_CCABV Predefined. */ ++ ++/* TC0_PERBV Predefined. */ ++/* TC0_PERBV Predefined. */ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD Predefined. */ ++/* TC1_CMD Predefined. */ ++ ++/* TC1_LUPD Predefined. */ ++/* TC1_LUPD Predefined. */ ++ ++/* TC1_DIR Predefined. */ ++/* TC1_DIR Predefined. */ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV Predefined. */ ++/* TC1_CCBBV Predefined. */ ++ ++/* TC1_CCABV Predefined. */ ++/* TC1_CCABV Predefined. */ ++ ++/* TC1_PERBV Predefined. */ ++/* TC1_PERBV Predefined. */ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++/* TC2.CTRLA bit masks and bit positions */ ++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC2.CTRLB bit masks and bit positions */ ++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ ++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ ++ ++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ ++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ ++ ++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ ++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ ++ ++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ ++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ ++ ++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ ++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ ++ ++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ ++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ ++ ++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ ++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ ++ ++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ ++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ ++ ++/* TC2.CTRLC bit masks and bit positions */ ++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ ++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ ++ ++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ ++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ ++ ++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ ++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ ++ ++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ ++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ ++ ++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ ++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ ++ ++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ ++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ ++ ++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ ++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ ++ ++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ ++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ ++ ++/* TC2.CTRLE bit masks and bit positions */ ++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC2.INTCTRLA bit masks and bit positions */ ++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ ++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ ++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ ++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ ++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ ++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ ++ ++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ ++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ ++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ ++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ ++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ ++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ ++ ++/* TC2.INTCTRLB bit masks and bit positions */ ++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ ++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ ++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ ++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ ++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ ++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ ++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ ++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ ++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ ++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ ++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ ++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ ++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ ++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ ++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ ++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ ++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ ++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ ++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ ++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ ++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ ++ ++/* TC2.CTRLF bit masks and bit positions */ ++#define TC2_CMD_gm 0x0C /* Command group mask. */ ++#define TC2_CMD_gp 2 /* Command group position. */ ++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC2_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC2_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ ++#define TC2_CMDEN_gp 0 /* Command Enable group position. */ ++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ ++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ ++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ ++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ ++ ++/* TC2.INTFLAGS bit masks and bit positions */ ++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ ++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ ++ ++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ ++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ ++ ++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ ++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ ++ ++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ ++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ ++ ++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ ++ ++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ ++ ++/* AWEX - Timer/Counter Advanced Waveform Extension */ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++/* AWEX.STATUSSET bit masks and bit positions */ ++/* AWEX_FDF Predefined. */ ++/* AWEX_FDF Predefined. */ ++ ++/* AWEX_DTHSBUFV Predefined. */ ++/* AWEX_DTHSBUFV Predefined. */ ++ ++/* AWEX_DTLSBUFV Predefined. */ ++/* AWEX_DTLSBUFV Predefined. */ ++ ++/* HIRES - Timer/Counter High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* LCD - LCD Controller */ ++/* LCD.CTRLA bit masks and bit positions */ ++#define LCD_ENABLE_bm 0x80 /* LCD Enable bit mask. */ ++#define LCD_ENABLE_bp 7 /* LCD Enable bit position. */ ++ ++#define LCD_XBIAS_bm 0x40 /* External Register Bias Generation bit mask. */ ++#define LCD_XBIAS_bp 6 /* External Register Bias Generation bit position. */ ++ ++#define LCD_DATCLK_bm 0x20 /* Data Register Lock bit mask. */ ++#define LCD_DATCLK_bp 5 /* Data Register Lock bit position. */ ++ ++#define LCD_COMSWP_bm 0x10 /* Common Bus Swap bit mask. */ ++#define LCD_COMSWP_bp 4 /* Common Bus Swap bit position. */ ++ ++#define LCD_SEGSWP_bm 0x08 /* Segment Bus Swap bit mask. */ ++#define LCD_SEGSWP_bp 3 /* Segment Bus Swap bit position. */ ++ ++#define LCD_CLRDT_bm 0x04 /* Clear Data Register bit mask. */ ++#define LCD_CLRDT_bp 2 /* Clear Data Register bit position. */ ++ ++#define LCD_SEGON_bm 0x02 /* Segments On bit mask. */ ++#define LCD_SEGON_bp 1 /* Segments On bit position. */ ++ ++#define LCD_BLANK_bm 0x01 /* Blanking Display Mode bit mask. */ ++#define LCD_BLANK_bp 0 /* Blanking Display Mode bit position. */ ++ ++/* LCD.CTRLB bit masks and bit positions */ ++#define LCD_PRESC_bm 0x80 /* LCD Prescaler Select bit mask. */ ++#define LCD_PRESC_bp 7 /* LCD Prescaler Select bit position. */ ++ ++#define LCD_CLKDIV_gm 0x70 /* LCD Clock Divide group mask. */ ++#define LCD_CLKDIV_gp 4 /* LCD Clock Divide group position. */ ++#define LCD_CLKDIV0_bm (1<<4) /* LCD Clock Divide bit 0 mask. */ ++#define LCD_CLKDIV0_bp 4 /* LCD Clock Divide bit 0 position. */ ++#define LCD_CLKDIV1_bm (1<<5) /* LCD Clock Divide bit 1 mask. */ ++#define LCD_CLKDIV1_bp 5 /* LCD Clock Divide bit 1 position. */ ++#define LCD_CLKDIV2_bm (1<<6) /* LCD Clock Divide bit 2 mask. */ ++#define LCD_CLKDIV2_bp 6 /* LCD Clock Divide bit 2 position. */ ++ ++#define LCD_LPWAV_bm 0x08 /* Low Power Waveform bit mask. */ ++#define LCD_LPWAV_bp 3 /* Low Power Waveform bit position. */ ++ ++#define LCD_DUTY_gm 0x03 /* Duty Select group mask. */ ++#define LCD_DUTY_gp 0 /* Duty Select group position. */ ++#define LCD_DUTY0_bm (1<<0) /* Duty Select bit 0 mask. */ ++#define LCD_DUTY0_bp 0 /* Duty Select bit 0 position. */ ++#define LCD_DUTY1_bm (1<<1) /* Duty Select bit 1 mask. */ ++#define LCD_DUTY1_bp 1 /* Duty Select bit 1 position. */ ++ ++/* LCD.CTRLC bit masks and bit positions */ ++#define LCD_PMSK_gm 0x3F /* LCD Port Mask group mask. */ ++#define LCD_PMSK_gp 0 /* LCD Port Mask group position. */ ++#define LCD_PMSK0_bm (1<<0) /* LCD Port Mask bit 0 mask. */ ++#define LCD_PMSK0_bp 0 /* LCD Port Mask bit 0 position. */ ++#define LCD_PMSK1_bm (1<<1) /* LCD Port Mask bit 1 mask. */ ++#define LCD_PMSK1_bp 1 /* LCD Port Mask bit 1 position. */ ++#define LCD_PMSK2_bm (1<<2) /* LCD Port Mask bit 2 mask. */ ++#define LCD_PMSK2_bp 2 /* LCD Port Mask bit 2 position. */ ++#define LCD_PMSK3_bm (1<<3) /* LCD Port Mask bit 3 mask. */ ++#define LCD_PMSK3_bp 3 /* LCD Port Mask bit 3 position. */ ++#define LCD_PMSK4_bm (1<<4) /* LCD Port Mask bit 4 mask. */ ++#define LCD_PMSK4_bp 4 /* LCD Port Mask bit 4 position. */ ++#define LCD_PMSK5_bm (1<<5) /* LCD Port Mask bit 5 mask. */ ++#define LCD_PMSK5_bp 5 /* LCD Port Mask bit 5 position. */ ++ ++/* LCD.INTCTRL bit masks and bit positions */ ++#define LCD_XIME_gm 0xF8 /* eXtended Interrupt Mode Enable group mask. */ ++#define LCD_XIME_gp 3 /* eXtended Interrupt Mode Enable group position. */ ++#define LCD_XIME0_bm (1<<3) /* eXtended Interrupt Mode Enable bit 0 mask. */ ++#define LCD_XIME0_bp 3 /* eXtended Interrupt Mode Enable bit 0 position. */ ++#define LCD_XIME1_bm (1<<4) /* eXtended Interrupt Mode Enable bit 1 mask. */ ++#define LCD_XIME1_bp 4 /* eXtended Interrupt Mode Enable bit 1 position. */ ++#define LCD_XIME2_bm (1<<5) /* eXtended Interrupt Mode Enable bit 2 mask. */ ++#define LCD_XIME2_bp 5 /* eXtended Interrupt Mode Enable bit 2 position. */ ++#define LCD_XIME3_bm (1<<6) /* eXtended Interrupt Mode Enable bit 3 mask. */ ++#define LCD_XIME3_bp 6 /* eXtended Interrupt Mode Enable bit 3 position. */ ++#define LCD_XIME4_bm (1<<7) /* eXtended Interrupt Mode Enable bit 4 mask. */ ++#define LCD_XIME4_bp 7 /* eXtended Interrupt Mode Enable bit 4 position. */ ++ ++#define LCD_FCINTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define LCD_FCINTLVL_gp 0 /* Interrupt Level group position. */ ++#define LCD_FCINTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define LCD_FCINTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define LCD_FCINTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define LCD_FCINTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* LCD.INTFLAG bit masks and bit positions */ ++#define LCD_FCIF_bm 0x01 /* LCD Frame Completed Interrupt Flag bit mask. */ ++#define LCD_FCIF_bp 0 /* LCD Frame Completed Interrupt Flag bit position. */ ++ ++/* LCD.CTRLD bit masks and bit positions */ ++#define LCD_BLINKEN_bm 0x08 /* Blink Enable bit mask. */ ++#define LCD_BLINKEN_bp 3 /* Blink Enable bit position. */ ++ ++#define LCD_BLINKRATE_gm 0x03 /* LCD Blink Rate group mask. */ ++#define LCD_BLINKRATE_gp 0 /* LCD Blink Rate group position. */ ++#define LCD_BLINKRATE0_bm (1<<0) /* LCD Blink Rate bit 0 mask. */ ++#define LCD_BLINKRATE0_bp 0 /* LCD Blink Rate bit 0 position. */ ++#define LCD_BLINKRATE1_bm (1<<1) /* LCD Blink Rate bit 1 mask. */ ++#define LCD_BLINKRATE1_bp 1 /* LCD Blink Rate bit 1 position. */ ++ ++/* LCD.CTRLE bit masks and bit positions */ ++#define LCD_BPS1_gm 0xF0 /* Blink Pixel Selection 1 group mask. */ ++#define LCD_BPS1_gp 4 /* Blink Pixel Selection 1 group position. */ ++#define LCD_BPS10_bm (1<<4) /* Blink Pixel Selection 1 bit 0 mask. */ ++#define LCD_BPS10_bp 4 /* Blink Pixel Selection 1 bit 0 position. */ ++#define LCD_BPS11_bm (1<<5) /* Blink Pixel Selection 1 bit 1 mask. */ ++#define LCD_BPS11_bp 5 /* Blink Pixel Selection 1 bit 1 position. */ ++#define LCD_BPS12_bm (1<<6) /* Blink Pixel Selection 1 bit 2 mask. */ ++#define LCD_BPS12_bp 6 /* Blink Pixel Selection 1 bit 2 position. */ ++#define LCD_BPS13_bm (1<<7) /* Blink Pixel Selection 1 bit 3 mask. */ ++#define LCD_BPS13_bp 7 /* Blink Pixel Selection 1 bit 3 position. */ ++ ++#define LCD_BPS0_gm 0x0F /* Blink Pixel Selection 0 group mask. */ ++#define LCD_BPS0_gp 0 /* Blink Pixel Selection 0 group position. */ ++#define LCD_BPS00_bm (1<<0) /* Blink Pixel Selection 0 bit 0 mask. */ ++#define LCD_BPS00_bp 0 /* Blink Pixel Selection 0 bit 0 position. */ ++#define LCD_BPS01_bm (1<<1) /* Blink Pixel Selection 0 bit 1 mask. */ ++#define LCD_BPS01_bp 1 /* Blink Pixel Selection 0 bit 1 position. */ ++#define LCD_BPS02_bm (1<<2) /* Blink Pixel Selection 0 bit 2 mask. */ ++#define LCD_BPS02_bp 2 /* Blink Pixel Selection 0 bit 2 position. */ ++#define LCD_BPS03_bm (1<<3) /* Blink Pixel Selection 0 bit 3 mask. */ ++#define LCD_BPS03_bp 3 /* Blink Pixel Selection 0 bit 3 position. */ ++ ++/* LCD.CTRLF bit masks and bit positions */ ++#define LCD_FCONT_gm 0x3F /* Fine Contrast group mask. */ ++#define LCD_FCONT_gp 0 /* Fine Contrast group position. */ ++#define LCD_FCONT0_bm (1<<0) /* Fine Contrast bit 0 mask. */ ++#define LCD_FCONT0_bp 0 /* Fine Contrast bit 0 position. */ ++#define LCD_FCONT1_bm (1<<1) /* Fine Contrast bit 1 mask. */ ++#define LCD_FCONT1_bp 1 /* Fine Contrast bit 1 position. */ ++#define LCD_FCONT2_bm (1<<2) /* Fine Contrast bit 2 mask. */ ++#define LCD_FCONT2_bp 2 /* Fine Contrast bit 2 position. */ ++#define LCD_FCONT3_bm (1<<3) /* Fine Contrast bit 3 mask. */ ++#define LCD_FCONT3_bp 3 /* Fine Contrast bit 3 position. */ ++#define LCD_FCONT4_bm (1<<4) /* Fine Contrast bit 4 mask. */ ++#define LCD_FCONT4_bp 4 /* Fine Contrast bit 4 position. */ ++#define LCD_FCONT5_bm (1<<5) /* Fine Contrast bit 5 mask. */ ++#define LCD_FCONT5_bp 5 /* Fine Contrast bit 5 position. */ ++ ++/* LCD.CTRLG bit masks and bit positions */ ++#define LCD_TDG_gm 0xC0 /* Type of Digit group mask. */ ++#define LCD_TDG_gp 6 /* Type of Digit group position. */ ++#define LCD_TDG0_bm (1<<6) /* Type of Digit bit 0 mask. */ ++#define LCD_TDG0_bp 6 /* Type of Digit bit 0 position. */ ++#define LCD_TDG1_bm (1<<7) /* Type of Digit bit 1 mask. */ ++#define LCD_TDG1_bp 7 /* Type of Digit bit 1 position. */ ++ ++#define LCD_STSEG_gm 0x3F /* Start Segment group mask. */ ++#define LCD_STSEG_gp 0 /* Start Segment group position. */ ++#define LCD_STSEG0_bm (1<<0) /* Start Segment bit 0 mask. */ ++#define LCD_STSEG0_bp 0 /* Start Segment bit 0 position. */ ++#define LCD_STSEG1_bm (1<<1) /* Start Segment bit 1 mask. */ ++#define LCD_STSEG1_bp 1 /* Start Segment bit 1 position. */ ++#define LCD_STSEG2_bm (1<<2) /* Start Segment bit 2 mask. */ ++#define LCD_STSEG2_bp 2 /* Start Segment bit 2 position. */ ++#define LCD_STSEG3_bm (1<<3) /* Start Segment bit 3 mask. */ ++#define LCD_STSEG3_bp 3 /* Start Segment bit 3 position. */ ++#define LCD_STSEG4_bm (1<<4) /* Start Segment bit 4 mask. */ ++#define LCD_STSEG4_bp 4 /* Start Segment bit 4 position. */ ++#define LCD_STSEG5_bm (1<<5) /* Start Segment bit 5 mask. */ ++#define LCD_STSEG5_bp 5 /* Start Segment bit 5 position. */ ++ ++/* LCD.CTRLH bit masks and bit positions */ ++#define LCD_DEC_bm 0x80 /* Decrement of Start Segment bit mask. */ ++#define LCD_DEC_bp 7 /* Decrement of Start Segment bit position. */ ++ ++#define LCD_DCODE_gm 0x7F /* Display Code group mask. */ ++#define LCD_DCODE_gp 0 /* Display Code group position. */ ++#define LCD_DCODE0_bm (1<<0) /* Display Code bit 0 mask. */ ++#define LCD_DCODE0_bp 0 /* Display Code bit 0 position. */ ++#define LCD_DCODE1_bm (1<<1) /* Display Code bit 1 mask. */ ++#define LCD_DCODE1_bp 1 /* Display Code bit 1 position. */ ++#define LCD_DCODE2_bm (1<<2) /* Display Code bit 2 mask. */ ++#define LCD_DCODE2_bp 2 /* Display Code bit 2 position. */ ++#define LCD_DCODE3_bm (1<<3) /* Display Code bit 3 mask. */ ++#define LCD_DCODE3_bp 3 /* Display Code bit 3 position. */ ++#define LCD_DCODE4_bm (1<<4) /* Display Code bit 4 mask. */ ++#define LCD_DCODE4_bp 4 /* Display Code bit 4 position. */ ++#define LCD_DCODE5_bm (1<<5) /* Display Code bit 5 mask. */ ++#define LCD_DCODE5_bp 5 /* Display Code bit 5 position. */ ++#define LCD_DCODE6_bm (1<<6) /* Display Code bit 6 mask. */ ++#define LCD_DCODE6_bp 6 /* Display Code bit 6 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ ++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ ++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ ++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ ++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ ++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ ++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ ++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ ++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ ++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ ++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ ++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ ++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ ++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ ++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ ++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ ++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ ++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ ++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ ++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ ++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* LOCKBIT - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* DMA interrupt vectors */ ++#define DMA_CH0_vect_num 6 ++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ ++#define DMA_CH1_vect_num 7 ++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LUNF_vect_num 14 ++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_HUNF_vect_num 15 ++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPA_vect_num 16 ++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPB_vect_num 17 ++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPC_vect_num 18 ++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPD_vect_num 19 ++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* USB interrupt vectors */ ++#define USB_BUSEVENT_vect_num 31 ++#define USB_BUSEVENT_vect _VECTOR(31) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ ++#define USB_TRNCOMPL_vect_num 32 ++#define USB_TRNCOMPL_vect _VECTOR(32) /* Transaction complete interrupt */ ++ ++/* LCD interrupt vectors */ ++#define LCD_INT_vect_num 35 ++#define LCD_INT_vect _VECTOR(35) /* LCD Interrupt */ ++ ++/* AES interrupt vectors */ ++#define AES_INT_vect_num 36 ++#define AES_INT_vect _VECTOR(36) /* AES Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 37 ++#define NVM_EE_vect _VECTOR(37) /* EE Interrupt */ ++#define NVM_SPM_vect_num 38 ++#define NVM_SPM_vect _VECTOR(38) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 39 ++#define PORTB_INT0_vect _VECTOR(39) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 40 ++#define PORTB_INT1_vect _VECTOR(40) /* External Interrupt 1 */ ++ ++/* ACB interrupt vectors */ ++#define ACB_AC0_vect_num 41 ++#define ACB_AC0_vect _VECTOR(41) /* AC0 Interrupt */ ++#define ACB_AC1_vect_num 42 ++#define ACB_AC1_vect _VECTOR(42) /* AC1 Interrupt */ ++#define ACB_ACW_vect_num 43 ++#define ACB_ACW_vect _VECTOR(43) /* ACW Window Mode Interrupt */ ++ ++/* ADCB interrupt vectors */ ++#define ADCB_CH0_vect_num 44 ++#define ADCB_CH0_vect _VECTOR(44) /* Interrupt 0 */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 48 ++#define PORTD_INT0_vect _VECTOR(48) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 49 ++#define PORTD_INT1_vect _VECTOR(49) /* External Interrupt 1 */ ++ ++/* PORTG interrupt vectors */ ++#define PORTG_INT0_vect_num 50 ++#define PORTG_INT0_vect _VECTOR(50) /* External Interrupt 0 */ ++#define PORTG_INT1_vect_num 51 ++#define PORTG_INT1_vect _VECTOR(51) /* External Interrupt 1 */ ++ ++/* PORTM interrupt vectors */ ++#define PORTM_INT0_vect_num 52 ++#define PORTM_INT0_vect _VECTOR(52) /* External Interrupt 0 */ ++#define PORTM_INT1_vect_num 53 ++#define PORTM_INT1_vect _VECTOR(53) /* External Interrupt 1 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 54 ++#define PORTE_INT0_vect _VECTOR(54) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 55 ++#define PORTE_INT1_vect _VECTOR(55) /* External Interrupt 1 */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 58 ++#define TCE0_OVF_vect _VECTOR(58) /* Overflow Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LUNF_vect_num 58 ++#define TCE2_LUNF_vect _VECTOR(58) /* Low Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_ERR_vect_num 59 ++#define TCE0_ERR_vect _VECTOR(59) /* Error Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_HUNF_vect_num 59 ++#define TCE2_HUNF_vect _VECTOR(59) /* High Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCA_vect_num 60 ++#define TCE0_CCA_vect _VECTOR(60) /* Compare or Capture A Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPA_vect_num 60 ++#define TCE2_LCMPA_vect _VECTOR(60) /* Low Byte Compare A Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCB_vect_num 61 ++#define TCE0_CCB_vect _VECTOR(61) /* Compare or Capture B Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPB_vect_num 61 ++#define TCE2_LCMPB_vect _VECTOR(61) /* Low Byte Compare B Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCC_vect_num 62 ++#define TCE0_CCC_vect _VECTOR(62) /* Compare or Capture C Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPC_vect_num 62 ++#define TCE2_LCMPC_vect _VECTOR(62) /* Low Byte Compare C Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCD_vect_num 63 ++#define TCE0_CCD_vect _VECTOR(63) /* Compare or Capture D Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPD_vect_num 63 ++#define TCE2_LCMPD_vect _VECTOR(63) /* Low Byte Compare D Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 69 ++#define USARTE0_RXC_vect _VECTOR(69) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 70 ++#define USARTE0_DRE_vect _VECTOR(70) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 71 ++#define USARTE0_TXC_vect _VECTOR(71) /* Transmission Complete Interrupt */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 75 ++#define PORTA_INT0_vect _VECTOR(75) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 76 ++#define PORTA_INT1_vect _VECTOR(76) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 77 ++#define ACA_AC0_vect _VECTOR(77) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 78 ++#define ACA_AC1_vect _VECTOR(78) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 79 ++#define ACA_ACW_vect _VECTOR(79) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 80 ++#define ADCA_CH0_vect _VECTOR(80) /* Interrupt 0 */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (81 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (139264) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (131072) ++#define APP_SECTION_PAGE_SIZE (256) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x1E000) ++#define APPTABLE_SECTION_SIZE (8192) ++#define APPTABLE_SECTION_PAGE_SIZE (256) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x20000) ++#define BOOT_SECTION_SIZE (8192) ++#define BOOT_SECTION_PAGE_SIZE (256) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (16384) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (2048) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (8192) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (2048) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (6) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (256) ++#define USER_SIGNATURES_PAGE_SIZE (256) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (256) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 256 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 */ ++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ ++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ ++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ ++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ ++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ ++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ ++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ ++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ ++#define FUSE0_DEFAULT (0xFF) ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x97 ++#define SIGNATURE_2 0x4D ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA128B1_H_INCLUDED */ ++ +diff --git a/include/avr/iox128b3.h b/include/avr/iox128b3.h +new file mode 100644 +index 0000000..d10f64c +--- /dev/null ++++ b/include/avr/iox128b3.h +@@ -0,0 +1,6247 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox128b3.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA128B3_H_INCLUDED ++#define _AVR_ATXMEGA128B3_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t USBCTRL; /* USB Control Register */ ++} CLK_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++/* USB Prescaler Division Factor */ ++typedef enum CLK_USBPSDIV_enum ++{ ++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ ++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ ++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ ++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ ++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ ++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ ++} CLK_USBPSDIV_t; ++ ++/* USB Clock Source */ ++typedef enum CLK_USBSRC_enum ++{ ++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ ++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ ++} CLK_USBSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C0_gc = (0x01<<0), /* External Clock on port C0 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C1_gc = (0x05<<0), /* External Clock on port C1 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C2_gc = (0x09<<0), /* External Clock on port C2 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C3_gc = (0x0D<<0), /* External Clock on port C3 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C4_gc = (0x11<<0), /* External Clock on port C4 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C5_gc = (0x15<<0), /* External Clock on port C5 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C6_gc = (0x19<<0), /* External Clock on port C6 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C7_gc = (0x1D<<0), /* External Clock on port C7 - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 2 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC2MCREF_enum ++{ ++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC2MCREF_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PR - Power Reduction ++-------------------------------------------------------------------------- ++*/ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t PRPB; /* Power Reduction Port B */ ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t reserved_0x04; ++ register8_t PRPE; /* Power Reduction Port E */ ++} PR_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++ register8_t reserved_0x05; ++ register8_t EVOUTSEL; /* Event Output Select */ ++} PORTCFG_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP02MAP_enum ++{ ++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP02MAP_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP13MAP_enum ++{ ++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP13MAP_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC_gc = (0x01<<0), /* System Clock Output on Port C */ ++ PORTCFG_CLKOUT_PE_gc = (0x03<<0), /* System Clock Output on Port E */ ++} PORTCFG_CLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC_gc = (0x01<<4), /* Event Channel 0 Output on Port C */ ++ PORTCFG_EVOUT_PE_gc = (0x03<<4), /* Event Channel 0 Output on Port E */ ++} PORTCFG_EVOUT_t; ++ ++/* Clock and Event Output Port */ ++typedef enum PORTCFG_CLKEVPIN_enum ++{ ++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ ++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ ++} PORTCFG_CLKEVPIN_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<2), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<2), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<2), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<2), /* Event Channel 3 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AES - AES Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* AES Module */ ++typedef struct AES_struct ++{ ++ register8_t CTRL; /* AES Control Register */ ++ register8_t STATUS; /* AES Status Register */ ++ register8_t STATE; /* AES State Register */ ++ register8_t KEY; /* AES Key Register */ ++ register8_t INTCTRL; /* AES Interrupt Control Register */ ++} AES_t; ++ ++/* Interrupt level */ ++typedef enum AES_INTLVL_enum ++{ ++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} AES_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ ++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Channel */ ++typedef struct DMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Address Control */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ ++ register8_t REPCNT; /* Channel Repeat Count */ ++ register8_t reserved_0x07; ++ register8_t SRCADDR0; /* Channel Source Address 0 */ ++ register8_t SRCADDR1; /* Channel Source Address 1 */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t DESTADDR0; /* Channel Destination Address 0 */ ++ register8_t DESTADDR1; /* Channel Destination Address 1 */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} DMA_CH_t; ++ ++ ++/* DMA Controller */ ++typedef struct DMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TEMP); /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ DMA_CH_t CH0; /* DMA Channel 0 */ ++ DMA_CH_t CH1; /* DMA Channel 1 */ ++} DMA_t; ++ ++/* Burst mode */ ++typedef enum DMA_CH_BURSTLEN_enum ++{ ++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ ++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ ++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ ++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ ++} DMA_CH_BURSTLEN_t; ++ ++/* Source address reload mode */ ++typedef enum DMA_CH_SRCRELOAD_enum ++{ ++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ ++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ ++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ ++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ ++} DMA_CH_SRCRELOAD_t; ++ ++/* Source addressing mode */ ++typedef enum DMA_CH_SRCDIR_enum ++{ ++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ ++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ ++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ ++} DMA_CH_SRCDIR_t; ++ ++/* Destination adress reload mode */ ++typedef enum DMA_CH_DESTRELOAD_enum ++{ ++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ ++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ ++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ ++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ ++} DMA_CH_DESTRELOAD_t; ++ ++/* Destination adressing mode */ ++typedef enum DMA_CH_DESTDIR_enum ++{ ++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ ++} DMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum DMA_CH_TRIGSRC_enum ++{ ++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ ++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ ++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ ++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ ++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ ++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ ++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ ++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ ++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ ++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ ++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ ++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ ++} DMA_CH_TRIGSRC_t; ++ ++/* Double buffering mode */ ++typedef enum DMA_DBUFMODE_enum ++{ ++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ ++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ ++} DMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum DMA_PRIMODE_enum ++{ ++ DMA_PRIMODE_RR01_gc = (0x00<<0), /* Round Robin */ ++ DMA_PRIMODE_CH0RR1_gc = (0x01<<0), /* Channel 0 > channel 1 */ ++} DMA_PRIMODE_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_ERRINTLVL_enum ++{ ++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ ++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ ++} DMA_CH_ERRINTLVL_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_TRNINTLVL_enum ++{ ++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ ++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ ++} DMA_CH_TRNINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ ++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ ++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ ++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t reserved_0x07; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++} ADC_t; ++ ++/* Current Limitation */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ ++} ADC_CURRLIMIT_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ ++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ ++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ ++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++ register8_t CURRCTRL; /* Current Source Control Register */ ++ register8_t CURRCALIB; /* Current Source Calibration Register */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* SDA Hold Time */ ++typedef enum TWI_SDAHOLD_enum ++{ ++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ ++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ ++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ ++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ ++} TWI_SDAHOLD_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USB - USB ++-------------------------------------------------------------------------- ++*/ ++ ++/* USB Endpoint */ ++typedef struct USB_EP_struct ++{ ++ register8_t STATUS; /* Endpoint Status */ ++ register8_t CTRL; /* Endpoint Control */ ++ _WORDREGISTER(CNT); /* USB Endpoint Counter */ ++ _WORDREGISTER(DATAPTR); /* Data Pointer */ ++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ ++} USB_EP_t; ++ ++ ++/* Universal Serial Bus */ ++typedef struct USB_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t FIFOWP; /* FIFO Write Pointer Register */ ++ register8_t FIFORP; /* FIFO Read Pointer Register */ ++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ ++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ ++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ ++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t reserved_0x20; ++ register8_t reserved_0x21; ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t CAL0; /* Calibration Byte 0 */ ++ register8_t CAL1; /* Calibration Byte 1 */ ++} USB_t; ++ ++ ++/* USB Endpoint Table */ ++typedef struct USB_EP_TABLE_struct ++{ ++ USB_EP_t EP0OUT; /* Endpoint 0 */ ++ USB_EP_t EP0IN; /* Endpoint 0 */ ++ USB_EP_t EP1OUT; /* Endpoint 1 */ ++ USB_EP_t EP1IN; /* Endpoint 1 */ ++ USB_EP_t EP2OUT; /* Endpoint 2 */ ++ USB_EP_t EP2IN; /* Endpoint 2 */ ++ USB_EP_t EP3OUT; /* Endpoint 3 */ ++ USB_EP_t EP3IN; /* Endpoint 3 */ ++ USB_EP_t EP4OUT; /* Endpoint 4 */ ++ USB_EP_t EP4IN; /* Endpoint 4 */ ++ USB_EP_t EP5OUT; /* Endpoint 5 */ ++ USB_EP_t EP5IN; /* Endpoint 5 */ ++ USB_EP_t EP6OUT; /* Endpoint 6 */ ++ USB_EP_t EP6IN; /* Endpoint 6 */ ++ USB_EP_t EP7OUT; /* Endpoint 7 */ ++ USB_EP_t EP7IN; /* Endpoint 7 */ ++ USB_EP_t EP8OUT; /* Endpoint 8 */ ++ USB_EP_t EP8IN; /* Endpoint 8 */ ++ USB_EP_t EP9OUT; /* Endpoint 9 */ ++ USB_EP_t EP9IN; /* Endpoint 9 */ ++ USB_EP_t EP10OUT; /* Endpoint 10 */ ++ USB_EP_t EP10IN; /* Endpoint 10 */ ++ USB_EP_t EP11OUT; /* Endpoint 11 */ ++ USB_EP_t EP11IN; /* Endpoint 11 */ ++ USB_EP_t EP12OUT; /* Endpoint 12 */ ++ USB_EP_t EP12IN; /* Endpoint 12 */ ++ USB_EP_t EP13OUT; /* Endpoint 13 */ ++ USB_EP_t EP13IN; /* Endpoint 13 */ ++ USB_EP_t EP14OUT; /* Endpoint 14 */ ++ USB_EP_t EP14IN; /* Endpoint 14 */ ++ USB_EP_t EP15OUT; /* Endpoint 15 */ ++ USB_EP_t EP15IN; /* Endpoint 15 */ ++ register8_t reserved_0x100; ++ register8_t reserved_0x101; ++ register8_t reserved_0x102; ++ register8_t reserved_0x103; ++ register8_t reserved_0x104; ++ register8_t reserved_0x105; ++ register8_t reserved_0x106; ++ register8_t reserved_0x107; ++ register8_t reserved_0x108; ++ register8_t reserved_0x109; ++ register8_t reserved_0x10A; ++ register8_t reserved_0x10B; ++ register8_t reserved_0x10C; ++ register8_t reserved_0x10D; ++ register8_t reserved_0x10E; ++ register8_t reserved_0x10F; ++ register8_t FRAMENUML; /* Frame Number Low Byte */ ++ register8_t FRAMENUMH; /* Frame Number High Byte */ ++} USB_EP_TABLE_t; ++ ++/* Interrupt level */ ++typedef enum USB_INTLVL_enum ++{ ++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} USB_INTLVL_t; ++ ++/* USB Endpoint Type */ ++typedef enum USB_EP_TYPE_enum ++{ ++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ ++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ ++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ ++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ ++} USB_EP_TYPE_t; ++ ++/* USB Endpoint Buffersize */ ++typedef enum USB_EP_BUFSIZE_enum ++{ ++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ ++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ ++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ ++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ ++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ ++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ ++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ ++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ ++} USB_EP_BUFSIZE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - I/O Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* I/O Port Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Byte Mode */ ++typedef enum TC_BYTEM_enum ++{ ++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ ++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ ++} TC_BYTEM_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AWEX - Timer/Counter Advanced Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - Timer/Counter High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LCD - LCD Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* LCD Controller */ ++typedef struct LCD_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t INTCTRL; /* Interrupt Enable Register */ ++ register8_t INTFLAG; /* Interrupt Flag Register */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t CTRLF; /* Control Register F */ ++ register8_t CTRLG; /* Control Register G */ ++ register8_t CTRLH; /* Control Register H */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t DATA0; /* LCD Data Register 0 */ ++ register8_t DATA1; /* LCD Data Register 1 */ ++ register8_t DATA2; /* LCD Data Register 2 */ ++ register8_t DATA3; /* LCD Data Register 3 */ ++ register8_t DATA4; /* LCD Data Register 4 */ ++ register8_t DATA5; /* LCD Data Register 5 */ ++ register8_t DATA6; /* LCD Data Register 6 */ ++ register8_t DATA7; /* LCD Data Register 7 */ ++ register8_t DATA8; /* LCD Data Register 8 */ ++ register8_t DATA9; /* LCD Data Register 9 */ ++ register8_t DATA10; /* LCD Data Register 10 */ ++ register8_t DATA11; /* LCD Data Register 11 */ ++ register8_t DATA12; /* LCD Data Register 12 */ ++ register8_t DATA13; /* LCD Data Register 13 */ ++ register8_t DATA14; /* LCD Data Register 14 */ ++ register8_t DATA15; /* LCD Data Register 15 */ ++ register8_t DATA16; /* LCD Data Register 16 */ ++ register8_t DATA17; /* LCD Data Register 17 */ ++ register8_t DATA18; /* LCD Data Register 18 */ ++ register8_t DATA19; /* LCD Data Register 19 */ ++} LCD_t; ++ ++/* LCD Blink Rate */ ++typedef enum LCD_BLINKRATE_enum ++{ ++ LCD_BLINKRATE_4Hz_gc = (0x00<<0), /* 4Hz Blink Rate */ ++ LCD_BLINKRATE_2Hz_gc = (0x01<<0), /* 2Hz Blink Rate */ ++ LCD_BLINKRATE_1Hz_gc = (0x02<<0), /* 1Hz Blink Rate */ ++ LCD_BLINKRATE_0Hz5_gc = (0x03<<0), /* 0.5Hz Blink Rate */ ++} LCD_BLINKRATE_t; ++ ++/* LCD Clock Divide */ ++typedef enum LCD_CLKDIV_enum ++{ ++ LCD_CLKDIV_DivBy1_gc = (0x00<<4), /* frame rate of 256 Hz */ ++ LCD_CLKDIV_DivBy2_gc = (0x01<<4), /* frame rate of 128 Hz */ ++ LCD_CLKDIV_DivBy3_gc = (0x02<<4), /* frame rate of 83.5 Hz */ ++ LCD_CLKDIV_DivBy4_gc = (0x03<<4), /* frame rate of 64 Hz */ ++ LCD_CLKDIV_DivBy5_gc = (0x04<<4), /* frame rate of 51.2 Hz */ ++ LCD_CLKDIV_DivBy6_gc = (0x05<<4), /* frame rate of 42.7 Hz */ ++ LCD_CLKDIV_DivBy7_gc = (0x06<<4), /* frame rate of 36.6 Hz */ ++ LCD_CLKDIV_DivBy8_gc = (0x07<<4), /* frame rate of 32 Hz */ ++} LCD_CLKDIV_t; ++ ++/* Duty Select */ ++typedef enum LCD_DUTY_enum ++{ ++ LCD_DUTY_1_4_gc = (0x00<<0), /* Duty=1/4, Bias=1/3, COM0:3 */ ++ LCD_DUTY_Static_gc = (0x01<<0), /* Duty=Static, Bias=Static, COM0 */ ++ LCD_DUTY_1_2_gc = (0x02<<0), /* Duty=1/2, Bias=1/3, COM0:1 */ ++ LCD_DUTY_1_3_gc = (0x03<<0), /* Duty=1/3, Bias=1/3, COM0:2 */ ++} LCD_DUTY_t; ++ ++/* LCD Prescaler Select */ ++typedef enum LCD_PRESC_enum ++{ ++ LCD_PRESC_8_gc = (0x00<<7), /* clk_lcd/8 */ ++ LCD_PRESC_16_gc = (0x01<<7), /* clk_lcd/16 */ ++} LCD_PRESC_t; ++ ++/* Type of Digit */ ++typedef enum LCD_TDG_enum ++{ ++ LCD_TDG_7S_3C_gc = (0x00<<6), /* 7-segment with 3 COMs */ ++ LCD_TDG_7S_4C_gc = (0x01<<6), /* 7-segment with 4 COMs */ ++ LCD_TDG_14S_4C_gc = (0x02<<6), /* 14-segment with 4 COMs */ ++ LCD_TDG_16S_3C_gc = (0x03<<6), /* 16-segment with 3 COMs */ ++} LCD_TDG_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t FUSEBYTE0; /* JTAG User ID */ ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* Timer Oscillator pin location */ ++typedef enum TOSCSEL_enum ++{ ++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ ++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ ++} TOSCSEL_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* BOD operation */ ++typedef enum BODACT_enum ++{ ++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BODACT_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WDP_enum ++{ ++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ ++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ ++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ ++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ ++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ ++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ ++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ ++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ ++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ ++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ ++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ ++} WDP_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LOCKBIT - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ ++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t USBCAL0; /* USB Calibration Byte 0 */ ++ register8_t USBCAL1; /* USB Calibration Byte 1 */ ++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ ++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++ register8_t reserved_0x40; ++ register8_t reserved_0x41; ++ register8_t reserved_0x42; ++ register8_t reserved_0x43; ++ register8_t reserved_0x44; ++ register8_t reserved_0x45; ++ register8_t reserved_0x46; ++ register8_t reserved_0x47; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define AES (*(AES_t *) 0x00C0) /* AES Module */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ ++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ ++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTG (*(PORT_t *) 0x06C0) /* I/O Ports */ ++#define PORTM (*(PORT_t *) 0x0760) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define LCD (*(LCD_t *) 0x0D00) /* LCD Controller */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) ++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) ++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) ++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) ++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++#define CLK_USBCTRL _SFR_MEM8(0x0044) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLL - DFLL */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPB _SFR_MEM8(0x0072) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPE _SFR_MEM8(0x0075) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) ++ ++/* AES - AES Module */ ++#define AES_CTRL _SFR_MEM8(0x00C0) ++#define AES_STATUS _SFR_MEM8(0x00C1) ++#define AES_STATE _SFR_MEM8(0x00C2) ++#define AES_KEY _SFR_MEM8(0x00C3) ++#define AES_INTCTRL _SFR_MEM8(0x00C4) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* DMA - DMA Controller */ ++#define DMA_CTRL _SFR_MEM8(0x0100) ++#define DMA_INTFLAGS _SFR_MEM8(0x0103) ++#define DMA_STATUS _SFR_MEM8(0x0104) ++#define DMA_TEMP _SFR_MEM16(0x0106) ++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) ++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) ++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) ++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) ++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) ++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) ++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) ++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) ++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) ++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) ++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) ++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) ++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) ++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCB_CTRLA _SFR_MEM8(0x0240) ++#define ADCB_CTRLB _SFR_MEM8(0x0241) ++#define ADCB_REFCTRL _SFR_MEM8(0x0242) ++#define ADCB_EVCTRL _SFR_MEM8(0x0243) ++#define ADCB_PRESCALER _SFR_MEM8(0x0244) ++#define ADCB_INTFLAGS _SFR_MEM8(0x0246) ++#define ADCB_TEMP _SFR_MEM8(0x0247) ++#define ADCB_SAMPCTRL _SFR_MEM8(0x0248) ++#define ADCB_CAL _SFR_MEM16(0x024C) ++#define ADCB_CH0RES _SFR_MEM16(0x0250) ++#define ADCB_CMP _SFR_MEM16(0x0258) ++#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) ++#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) ++#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) ++#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) ++#define ADCB_CH0_RES _SFR_MEM16(0x0264) ++#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) ++ ++/* AC - Analog Comparator */ ++#define ACB_AC0CTRL _SFR_MEM8(0x0390) ++#define ACB_AC1CTRL _SFR_MEM8(0x0391) ++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) ++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) ++#define ACB_CTRLA _SFR_MEM8(0x0394) ++#define ACB_CTRLB _SFR_MEM8(0x0395) ++#define ACB_WINCTRL _SFR_MEM8(0x0396) ++#define ACB_STATUS _SFR_MEM8(0x0397) ++#define ACB_CURRCTRL _SFR_MEM8(0x0398) ++#define ACB_CURRCALIB _SFR_MEM8(0x0399) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* USB - Universal Serial Bus */ ++#define USB_CTRLA _SFR_MEM8(0x04C0) ++#define USB_CTRLB _SFR_MEM8(0x04C1) ++#define USB_STATUS _SFR_MEM8(0x04C2) ++#define USB_ADDR _SFR_MEM8(0x04C3) ++#define USB_FIFOWP _SFR_MEM8(0x04C4) ++#define USB_FIFORP _SFR_MEM8(0x04C5) ++#define USB_EPPTR _SFR_MEM16(0x04C6) ++#define USB_INTCTRLA _SFR_MEM8(0x04C8) ++#define USB_INTCTRLB _SFR_MEM8(0x04C9) ++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) ++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) ++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) ++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) ++#define USB_CAL0 _SFR_MEM8(0x04FA) ++#define USB_CAL1 _SFR_MEM8(0x04FB) ++ ++/* PORT - I/O Ports */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_REMAP _SFR_MEM8(0x062E) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTG_DIR _SFR_MEM8(0x06C0) ++#define PORTG_DIRSET _SFR_MEM8(0x06C1) ++#define PORTG_DIRCLR _SFR_MEM8(0x06C2) ++#define PORTG_DIRTGL _SFR_MEM8(0x06C3) ++#define PORTG_OUT _SFR_MEM8(0x06C4) ++#define PORTG_OUTSET _SFR_MEM8(0x06C5) ++#define PORTG_OUTCLR _SFR_MEM8(0x06C6) ++#define PORTG_OUTTGL _SFR_MEM8(0x06C7) ++#define PORTG_IN _SFR_MEM8(0x06C8) ++#define PORTG_INTCTRL _SFR_MEM8(0x06C9) ++#define PORTG_INT0MASK _SFR_MEM8(0x06CA) ++#define PORTG_INT1MASK _SFR_MEM8(0x06CB) ++#define PORTG_INTFLAGS _SFR_MEM8(0x06CC) ++#define PORTG_REMAP _SFR_MEM8(0x06CE) ++#define PORTG_PIN0CTRL _SFR_MEM8(0x06D0) ++#define PORTG_PIN1CTRL _SFR_MEM8(0x06D1) ++#define PORTG_PIN2CTRL _SFR_MEM8(0x06D2) ++#define PORTG_PIN3CTRL _SFR_MEM8(0x06D3) ++#define PORTG_PIN4CTRL _SFR_MEM8(0x06D4) ++#define PORTG_PIN5CTRL _SFR_MEM8(0x06D5) ++#define PORTG_PIN6CTRL _SFR_MEM8(0x06D6) ++#define PORTG_PIN7CTRL _SFR_MEM8(0x06D7) ++ ++/* PORT - I/O Ports */ ++#define PORTM_DIR _SFR_MEM8(0x0760) ++#define PORTM_DIRSET _SFR_MEM8(0x0761) ++#define PORTM_DIRCLR _SFR_MEM8(0x0762) ++#define PORTM_DIRTGL _SFR_MEM8(0x0763) ++#define PORTM_OUT _SFR_MEM8(0x0764) ++#define PORTM_OUTSET _SFR_MEM8(0x0765) ++#define PORTM_OUTCLR _SFR_MEM8(0x0766) ++#define PORTM_OUTTGL _SFR_MEM8(0x0767) ++#define PORTM_IN _SFR_MEM8(0x0768) ++#define PORTM_INTCTRL _SFR_MEM8(0x0769) ++#define PORTM_INT0MASK _SFR_MEM8(0x076A) ++#define PORTM_INT1MASK _SFR_MEM8(0x076B) ++#define PORTM_INTFLAGS _SFR_MEM8(0x076C) ++#define PORTM_REMAP _SFR_MEM8(0x076E) ++#define PORTM_PIN0CTRL _SFR_MEM8(0x0770) ++#define PORTM_PIN1CTRL _SFR_MEM8(0x0771) ++#define PORTM_PIN2CTRL _SFR_MEM8(0x0772) ++#define PORTM_PIN3CTRL _SFR_MEM8(0x0773) ++#define PORTM_PIN4CTRL _SFR_MEM8(0x0774) ++#define PORTM_PIN5CTRL _SFR_MEM8(0x0775) ++#define PORTM_PIN6CTRL _SFR_MEM8(0x0776) ++#define PORTM_PIN7CTRL _SFR_MEM8(0x0777) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_STATUSSET _SFR_MEM8(0x0885) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* LCD - LCD Controller */ ++#define LCD_CTRLA _SFR_MEM8(0x0D00) ++#define LCD_CTRLB _SFR_MEM8(0x0D01) ++#define LCD_CTRLC _SFR_MEM8(0x0D02) ++#define LCD_INTCTRL _SFR_MEM8(0x0D03) ++#define LCD_INTFLAG _SFR_MEM8(0x0D04) ++#define LCD_CTRLD _SFR_MEM8(0x0D05) ++#define LCD_CTRLE _SFR_MEM8(0x0D06) ++#define LCD_CTRLF _SFR_MEM8(0x0D07) ++#define LCD_CTRLG _SFR_MEM8(0x0D08) ++#define LCD_CTRLH _SFR_MEM8(0x0D09) ++#define LCD_DATA0 _SFR_MEM8(0x0D10) ++#define LCD_DATA1 _SFR_MEM8(0x0D11) ++#define LCD_DATA2 _SFR_MEM8(0x0D12) ++#define LCD_DATA3 _SFR_MEM8(0x0D13) ++#define LCD_DATA4 _SFR_MEM8(0x0D14) ++#define LCD_DATA5 _SFR_MEM8(0x0D15) ++#define LCD_DATA6 _SFR_MEM8(0x0D16) ++#define LCD_DATA7 _SFR_MEM8(0x0D17) ++#define LCD_DATA8 _SFR_MEM8(0x0D18) ++#define LCD_DATA9 _SFR_MEM8(0x0D19) ++#define LCD_DATA10 _SFR_MEM8(0x0D1A) ++#define LCD_DATA11 _SFR_MEM8(0x0D1B) ++#define LCD_DATA12 _SFR_MEM8(0x0D1C) ++#define LCD_DATA13 _SFR_MEM8(0x0D1D) ++#define LCD_DATA14 _SFR_MEM8(0x0D1E) ++#define LCD_DATA15 _SFR_MEM8(0x0D1F) ++#define LCD_DATA16 _SFR_MEM8(0x0D20) ++#define LCD_DATA17 _SFR_MEM8(0x0D21) ++#define LCD_DATA18 _SFR_MEM8(0x0D22) ++#define LCD_DATA19 _SFR_MEM8(0x0D23) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* CLK.USBCTRL bit masks and bit positions */ ++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ ++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ ++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ ++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ ++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ ++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ ++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ ++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ ++ ++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ ++#define CLK_USBSRC_gp 1 /* Clock Source group position. */ ++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ ++ ++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ ++#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* PR - Power Reduction */ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_LCD_bm 0x80 /* LCD Module bit mask. */ ++#define PR_LCD_bp 7 /* LCD Module bit position. */ ++ ++#define PR_USB_bm 0x40 /* USB bit mask. */ ++#define PR_USB_bp 6 /* USB bit position. */ ++ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPB bit masks and bit positions */ ++/* PR_ADC Predefined. */ ++/* PR_ADC Predefined. */ ++ ++/* PR_AC Predefined. */ ++/* PR_AC Predefined. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ ++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ ++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ ++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ ++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ ++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ ++ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ ++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ ++ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ ++ ++/* PORTCFG.EVOUTSEL bit masks and bit positions */ ++#define PORTCFG_EVOUTSEL_bm 0x04 /* Event Output Select bit mask. */ ++#define PORTCFG_EVOUTSEL_bp 2 /* Event Output Select bit position. */ ++ ++/* AES - AES Module */ ++/* AES.CTRL bit masks and bit positions */ ++#define AES_START_bm 0x80 /* Start/Run bit mask. */ ++#define AES_START_bp 7 /* Start/Run bit position. */ ++ ++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ ++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ ++ ++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ ++#define AES_RESET_bp 5 /* AES Software Reset bit position. */ ++ ++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ ++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ ++ ++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ ++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ ++ ++/* AES.STATUS bit masks and bit positions */ ++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ ++#define AES_ERROR_bp 7 /* AES Error bit position. */ ++ ++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ ++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ ++ ++/* AES.INTCTRL bit masks and bit positions */ ++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define AES_INTLVL_gp 0 /* Interrupt level group position. */ ++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* DMA - DMA Controller */ ++/* DMA_CH.CTRLA bit masks and bit positions */ ++#define DMA_CH_CHEN_bm 0x80 /* Channel Enable bit mask. */ ++#define DMA_CH_CHEN_bp 7 /* Channel Enable bit position. */ ++ ++#define DMA_CH_CHRST_bm 0x40 /* Channel Software Reset bit mask. */ ++#define DMA_CH_CHRST_bp 6 /* Channel Software Reset bit position. */ ++ ++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ ++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ ++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ ++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ ++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ ++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ ++ ++/* DMA_CH.CTRLB bit masks and bit positions */ ++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ ++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ ++ ++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ ++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ ++ ++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ ++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ ++ ++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ ++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ ++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ ++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ ++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ ++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ ++ ++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ ++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ ++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ ++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ ++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ ++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ ++ ++/* DMA_CH.ADDRCTRL bit masks and bit positions */ ++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ ++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ ++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ ++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ ++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ ++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ ++ ++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ ++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ ++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ ++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ ++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ ++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ ++ ++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ ++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ ++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ ++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ ++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ ++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ ++ ++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ ++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ ++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ ++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ ++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ ++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ ++ ++/* DMA_CH.TRIGSRC bit masks and bit positions */ ++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++/* DMA.CTRL bit masks and bit positions */ ++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define DMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define DMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define DMA_DBUFMODE_bm 0x04 /* Double Buffering Mode bit mask. */ ++#define DMA_DBUFMODE_bp 2 /* Double Buffering Mode bit position. */ ++ ++#define DMA_PRIMODE_bm 0x01 /* Channel Priority Mode bit mask. */ ++#define DMA_PRIMODE_bp 0 /* Channel Priority Mode bit position. */ ++ ++/* DMA.INTFLAGS bit masks and bit positions */ ++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++/* DMA.STATUS bit masks and bit positions */ ++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ ++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ ++ ++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ ++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ ++ ++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ ++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ ++ ++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ ++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ ++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ ++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ ++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ ++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ ++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ ++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ ++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ ++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ ++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ ++ ++#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */ ++#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */ ++#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ ++#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */ ++#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ ++#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */ ++#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ ++#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */ ++#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ ++#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ ++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* ADC.SAMPCTRL bit masks and bit positions */ ++#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ ++#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ ++#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ ++#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ ++#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ ++#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ ++#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ ++#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ ++#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ ++#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ ++#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ ++#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ ++#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ ++#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* AC.CURRCTRL bit masks and bit positions */ ++#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ ++#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ ++ ++#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ ++#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ ++ ++#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ ++#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ ++ ++#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ ++#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ ++ ++/* AC.CURRCALIB bit masks and bit positions */ ++#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ ++#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ ++#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ ++#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ ++#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ ++#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ ++#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ ++#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ ++#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ ++#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ ++ ++/* RTC - Real-Time Counter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* USB - USB */ ++/* USB_EP.STATUS bit masks and bit positions */ ++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ ++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ ++ ++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ ++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ ++ ++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ ++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ ++ ++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ ++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ ++ ++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ ++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ ++ ++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ ++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ ++ ++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ ++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ ++ ++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ ++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ ++ ++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ ++ ++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ ++ ++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ ++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ ++ ++/* USB_EP.CTRL bit masks and bit positions */ ++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ ++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ ++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ ++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ ++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ ++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ ++ ++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ ++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ ++ ++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ ++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ ++ ++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ ++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ ++ ++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ ++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ ++ ++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ ++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ ++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ ++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ ++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ ++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ ++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ ++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ ++ ++/* USB_EP.CNT bit masks and bit positions */ ++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ ++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ ++ ++/* USB.CTRLA bit masks and bit positions */ ++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ ++#define USB_ENABLE_bp 7 /* USB Enable bit position. */ ++ ++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ ++#define USB_SPEED_bp 6 /* Speed Select bit position. */ ++ ++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ ++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ ++ ++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ ++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ ++ ++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ ++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ ++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ ++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ ++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ ++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ ++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ ++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ ++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ ++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ ++ ++/* USB.CTRLB bit masks and bit positions */ ++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ ++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ ++ ++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ ++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ ++ ++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ ++#define USB_GNACK_bp 1 /* Global NACK bit position. */ ++ ++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ ++#define USB_ATTACH_bp 0 /* Attach bit position. */ ++ ++/* USB.STATUS bit masks and bit positions */ ++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ ++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ ++ ++#define USB_RESUME_bm 0x04 /* Resume bit mask. */ ++#define USB_RESUME_bp 2 /* Resume bit position. */ ++ ++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ ++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ ++ ++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ ++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ ++ ++/* USB.ADDR bit masks and bit positions */ ++#define USB_ADDR_gm 0x7F /* Device Address group mask. */ ++#define USB_ADDR_gp 0 /* Device Address group position. */ ++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ ++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ ++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ ++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ ++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ ++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ ++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ ++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ ++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ ++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ ++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ ++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ ++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ ++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ ++ ++/* USB.FIFOWP bit masks and bit positions */ ++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ ++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ ++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ ++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ ++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ ++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ ++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ ++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ ++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ ++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ ++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ ++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ ++ ++/* USB.FIFORP bit masks and bit positions */ ++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ ++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ ++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ ++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ ++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ ++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ ++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ ++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ ++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ ++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ ++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ ++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ ++ ++/* USB.INTCTRLA bit masks and bit positions */ ++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ ++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ ++ ++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ ++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ ++ ++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ ++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ ++ ++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ ++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ ++ ++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* USB.INTCTRLB bit masks and bit positions */ ++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ ++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ ++ ++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ ++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ ++ ++/* USB.INTFLAGSACLR bit masks and bit positions */ ++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ ++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ ++ ++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ ++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ ++ ++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ ++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ ++ ++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ ++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ ++ ++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ ++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ ++ ++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ ++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ ++ ++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ ++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ ++ ++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ ++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSASET bit masks and bit positions */ ++/* USB_SOFIF Predefined. */ ++/* USB_SOFIF Predefined. */ ++ ++/* USB_SUSPENDIF Predefined. */ ++/* USB_SUSPENDIF Predefined. */ ++ ++/* USB_RESUMEIF Predefined. */ ++/* USB_RESUMEIF Predefined. */ ++ ++/* USB_RSTIF Predefined. */ ++/* USB_RSTIF Predefined. */ ++ ++/* USB_CRCIF Predefined. */ ++/* USB_CRCIF Predefined. */ ++ ++/* USB_UNFIF Predefined. */ ++/* USB_UNFIF Predefined. */ ++ ++/* USB_OVFIF Predefined. */ ++/* USB_OVFIF Predefined. */ ++ ++/* USB_STALLIF Predefined. */ ++/* USB_STALLIF Predefined. */ ++ ++/* USB.INTFLAGSBCLR bit masks and bit positions */ ++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ ++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ ++ ++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ ++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSBSET bit masks and bit positions */ ++/* USB_TRNIF Predefined. */ ++/* USB_TRNIF Predefined. */ ++ ++/* USB_SETUPIF Predefined. */ ++/* USB_SETUPIF Predefined. */ ++ ++/* PORT - I/O Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_SPI_bm 0x20 /* SPI bit mask. */ ++#define PORT_SPI_bp 5 /* SPI bit position. */ ++ ++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ ++#define PORT_USART0_bp 4 /* USART0 bit position. */ ++ ++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ ++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ ++ ++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ ++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ ++ ++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ ++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ ++ ++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ ++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD Predefined. */ ++/* TC0_CMD Predefined. */ ++ ++/* TC0_LUPD Predefined. */ ++/* TC0_LUPD Predefined. */ ++ ++/* TC0_DIR Predefined. */ ++/* TC0_DIR Predefined. */ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV Predefined. */ ++/* TC0_CCDBV Predefined. */ ++ ++/* TC0_CCCBV Predefined. */ ++/* TC0_CCCBV Predefined. */ ++ ++/* TC0_CCBBV Predefined. */ ++/* TC0_CCBBV Predefined. */ ++ ++/* TC0_CCABV Predefined. */ ++/* TC0_CCABV Predefined. */ ++ ++/* TC0_PERBV Predefined. */ ++/* TC0_PERBV Predefined. */ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD Predefined. */ ++/* TC1_CMD Predefined. */ ++ ++/* TC1_LUPD Predefined. */ ++/* TC1_LUPD Predefined. */ ++ ++/* TC1_DIR Predefined. */ ++/* TC1_DIR Predefined. */ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV Predefined. */ ++/* TC1_CCBBV Predefined. */ ++ ++/* TC1_CCABV Predefined. */ ++/* TC1_CCABV Predefined. */ ++ ++/* TC1_PERBV Predefined. */ ++/* TC1_PERBV Predefined. */ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* AWEX - Timer/Counter Advanced Waveform Extension */ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++/* AWEX.STATUSSET bit masks and bit positions */ ++/* AWEX_FDF Predefined. */ ++/* AWEX_FDF Predefined. */ ++ ++/* AWEX_DTHSBUFV Predefined. */ ++/* AWEX_DTHSBUFV Predefined. */ ++ ++/* AWEX_DTLSBUFV Predefined. */ ++/* AWEX_DTLSBUFV Predefined. */ ++ ++/* HIRES - Timer/Counter High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* LCD - LCD Controller */ ++/* LCD.CTRLA bit masks and bit positions */ ++#define LCD_ENABLE_bm 0x80 /* LCD Enable bit mask. */ ++#define LCD_ENABLE_bp 7 /* LCD Enable bit position. */ ++ ++#define LCD_XBIAS_bm 0x40 /* External Register Bias Generation bit mask. */ ++#define LCD_XBIAS_bp 6 /* External Register Bias Generation bit position. */ ++ ++#define LCD_DATCLK_bm 0x20 /* Data Register Lock bit mask. */ ++#define LCD_DATCLK_bp 5 /* Data Register Lock bit position. */ ++ ++#define LCD_COMSWP_bm 0x10 /* Common Bus Swap bit mask. */ ++#define LCD_COMSWP_bp 4 /* Common Bus Swap bit position. */ ++ ++#define LCD_SEGSWP_bm 0x08 /* Segment Bus Swap bit mask. */ ++#define LCD_SEGSWP_bp 3 /* Segment Bus Swap bit position. */ ++ ++#define LCD_CLRDT_bm 0x04 /* Clear Data Register bit mask. */ ++#define LCD_CLRDT_bp 2 /* Clear Data Register bit position. */ ++ ++#define LCD_SEGON_bm 0x02 /* Segments On bit mask. */ ++#define LCD_SEGON_bp 1 /* Segments On bit position. */ ++ ++#define LCD_BLANK_bm 0x01 /* Blanking Display Mode bit mask. */ ++#define LCD_BLANK_bp 0 /* Blanking Display Mode bit position. */ ++ ++/* LCD.CTRLB bit masks and bit positions */ ++#define LCD_PRESC_bm 0x80 /* LCD Prescaler Select bit mask. */ ++#define LCD_PRESC_bp 7 /* LCD Prescaler Select bit position. */ ++ ++#define LCD_CLKDIV_gm 0x70 /* LCD Clock Divide group mask. */ ++#define LCD_CLKDIV_gp 4 /* LCD Clock Divide group position. */ ++#define LCD_CLKDIV0_bm (1<<4) /* LCD Clock Divide bit 0 mask. */ ++#define LCD_CLKDIV0_bp 4 /* LCD Clock Divide bit 0 position. */ ++#define LCD_CLKDIV1_bm (1<<5) /* LCD Clock Divide bit 1 mask. */ ++#define LCD_CLKDIV1_bp 5 /* LCD Clock Divide bit 1 position. */ ++#define LCD_CLKDIV2_bm (1<<6) /* LCD Clock Divide bit 2 mask. */ ++#define LCD_CLKDIV2_bp 6 /* LCD Clock Divide bit 2 position. */ ++ ++#define LCD_LPWAV_bm 0x08 /* Low Power Waveform bit mask. */ ++#define LCD_LPWAV_bp 3 /* Low Power Waveform bit position. */ ++ ++#define LCD_DUTY_gm 0x03 /* Duty Select group mask. */ ++#define LCD_DUTY_gp 0 /* Duty Select group position. */ ++#define LCD_DUTY0_bm (1<<0) /* Duty Select bit 0 mask. */ ++#define LCD_DUTY0_bp 0 /* Duty Select bit 0 position. */ ++#define LCD_DUTY1_bm (1<<1) /* Duty Select bit 1 mask. */ ++#define LCD_DUTY1_bp 1 /* Duty Select bit 1 position. */ ++ ++/* LCD.CTRLC bit masks and bit positions */ ++#define LCD_PMSK_gm 0x3F /* LCD Port Mask group mask. */ ++#define LCD_PMSK_gp 0 /* LCD Port Mask group position. */ ++#define LCD_PMSK0_bm (1<<0) /* LCD Port Mask bit 0 mask. */ ++#define LCD_PMSK0_bp 0 /* LCD Port Mask bit 0 position. */ ++#define LCD_PMSK1_bm (1<<1) /* LCD Port Mask bit 1 mask. */ ++#define LCD_PMSK1_bp 1 /* LCD Port Mask bit 1 position. */ ++#define LCD_PMSK2_bm (1<<2) /* LCD Port Mask bit 2 mask. */ ++#define LCD_PMSK2_bp 2 /* LCD Port Mask bit 2 position. */ ++#define LCD_PMSK3_bm (1<<3) /* LCD Port Mask bit 3 mask. */ ++#define LCD_PMSK3_bp 3 /* LCD Port Mask bit 3 position. */ ++#define LCD_PMSK4_bm (1<<4) /* LCD Port Mask bit 4 mask. */ ++#define LCD_PMSK4_bp 4 /* LCD Port Mask bit 4 position. */ ++#define LCD_PMSK5_bm (1<<5) /* LCD Port Mask bit 5 mask. */ ++#define LCD_PMSK5_bp 5 /* LCD Port Mask bit 5 position. */ ++ ++/* LCD.INTCTRL bit masks and bit positions */ ++#define LCD_XIME_gm 0xF8 /* eXtended Interrupt Mode Enable group mask. */ ++#define LCD_XIME_gp 3 /* eXtended Interrupt Mode Enable group position. */ ++#define LCD_XIME0_bm (1<<3) /* eXtended Interrupt Mode Enable bit 0 mask. */ ++#define LCD_XIME0_bp 3 /* eXtended Interrupt Mode Enable bit 0 position. */ ++#define LCD_XIME1_bm (1<<4) /* eXtended Interrupt Mode Enable bit 1 mask. */ ++#define LCD_XIME1_bp 4 /* eXtended Interrupt Mode Enable bit 1 position. */ ++#define LCD_XIME2_bm (1<<5) /* eXtended Interrupt Mode Enable bit 2 mask. */ ++#define LCD_XIME2_bp 5 /* eXtended Interrupt Mode Enable bit 2 position. */ ++#define LCD_XIME3_bm (1<<6) /* eXtended Interrupt Mode Enable bit 3 mask. */ ++#define LCD_XIME3_bp 6 /* eXtended Interrupt Mode Enable bit 3 position. */ ++#define LCD_XIME4_bm (1<<7) /* eXtended Interrupt Mode Enable bit 4 mask. */ ++#define LCD_XIME4_bp 7 /* eXtended Interrupt Mode Enable bit 4 position. */ ++ ++#define LCD_FCINTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define LCD_FCINTLVL_gp 0 /* Interrupt Level group position. */ ++#define LCD_FCINTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define LCD_FCINTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define LCD_FCINTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define LCD_FCINTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* LCD.INTFLAG bit masks and bit positions */ ++#define LCD_FCIF_bm 0x01 /* LCD Frame Completed Interrupt Flag bit mask. */ ++#define LCD_FCIF_bp 0 /* LCD Frame Completed Interrupt Flag bit position. */ ++ ++/* LCD.CTRLD bit masks and bit positions */ ++#define LCD_BLINKEN_bm 0x08 /* Blink Enable bit mask. */ ++#define LCD_BLINKEN_bp 3 /* Blink Enable bit position. */ ++ ++#define LCD_BLINKRATE_gm 0x03 /* LCD Blink Rate group mask. */ ++#define LCD_BLINKRATE_gp 0 /* LCD Blink Rate group position. */ ++#define LCD_BLINKRATE0_bm (1<<0) /* LCD Blink Rate bit 0 mask. */ ++#define LCD_BLINKRATE0_bp 0 /* LCD Blink Rate bit 0 position. */ ++#define LCD_BLINKRATE1_bm (1<<1) /* LCD Blink Rate bit 1 mask. */ ++#define LCD_BLINKRATE1_bp 1 /* LCD Blink Rate bit 1 position. */ ++ ++/* LCD.CTRLE bit masks and bit positions */ ++#define LCD_BPS1_gm 0xF0 /* Blink Pixel Selection 1 group mask. */ ++#define LCD_BPS1_gp 4 /* Blink Pixel Selection 1 group position. */ ++#define LCD_BPS10_bm (1<<4) /* Blink Pixel Selection 1 bit 0 mask. */ ++#define LCD_BPS10_bp 4 /* Blink Pixel Selection 1 bit 0 position. */ ++#define LCD_BPS11_bm (1<<5) /* Blink Pixel Selection 1 bit 1 mask. */ ++#define LCD_BPS11_bp 5 /* Blink Pixel Selection 1 bit 1 position. */ ++#define LCD_BPS12_bm (1<<6) /* Blink Pixel Selection 1 bit 2 mask. */ ++#define LCD_BPS12_bp 6 /* Blink Pixel Selection 1 bit 2 position. */ ++#define LCD_BPS13_bm (1<<7) /* Blink Pixel Selection 1 bit 3 mask. */ ++#define LCD_BPS13_bp 7 /* Blink Pixel Selection 1 bit 3 position. */ ++ ++#define LCD_BPS0_gm 0x0F /* Blink Pixel Selection 0 group mask. */ ++#define LCD_BPS0_gp 0 /* Blink Pixel Selection 0 group position. */ ++#define LCD_BPS00_bm (1<<0) /* Blink Pixel Selection 0 bit 0 mask. */ ++#define LCD_BPS00_bp 0 /* Blink Pixel Selection 0 bit 0 position. */ ++#define LCD_BPS01_bm (1<<1) /* Blink Pixel Selection 0 bit 1 mask. */ ++#define LCD_BPS01_bp 1 /* Blink Pixel Selection 0 bit 1 position. */ ++#define LCD_BPS02_bm (1<<2) /* Blink Pixel Selection 0 bit 2 mask. */ ++#define LCD_BPS02_bp 2 /* Blink Pixel Selection 0 bit 2 position. */ ++#define LCD_BPS03_bm (1<<3) /* Blink Pixel Selection 0 bit 3 mask. */ ++#define LCD_BPS03_bp 3 /* Blink Pixel Selection 0 bit 3 position. */ ++ ++/* LCD.CTRLF bit masks and bit positions */ ++#define LCD_FCONT_gm 0x3F /* Fine Contrast group mask. */ ++#define LCD_FCONT_gp 0 /* Fine Contrast group position. */ ++#define LCD_FCONT0_bm (1<<0) /* Fine Contrast bit 0 mask. */ ++#define LCD_FCONT0_bp 0 /* Fine Contrast bit 0 position. */ ++#define LCD_FCONT1_bm (1<<1) /* Fine Contrast bit 1 mask. */ ++#define LCD_FCONT1_bp 1 /* Fine Contrast bit 1 position. */ ++#define LCD_FCONT2_bm (1<<2) /* Fine Contrast bit 2 mask. */ ++#define LCD_FCONT2_bp 2 /* Fine Contrast bit 2 position. */ ++#define LCD_FCONT3_bm (1<<3) /* Fine Contrast bit 3 mask. */ ++#define LCD_FCONT3_bp 3 /* Fine Contrast bit 3 position. */ ++#define LCD_FCONT4_bm (1<<4) /* Fine Contrast bit 4 mask. */ ++#define LCD_FCONT4_bp 4 /* Fine Contrast bit 4 position. */ ++#define LCD_FCONT5_bm (1<<5) /* Fine Contrast bit 5 mask. */ ++#define LCD_FCONT5_bp 5 /* Fine Contrast bit 5 position. */ ++ ++/* LCD.CTRLG bit masks and bit positions */ ++#define LCD_TDG_gm 0xC0 /* Type of Digit group mask. */ ++#define LCD_TDG_gp 6 /* Type of Digit group position. */ ++#define LCD_TDG0_bm (1<<6) /* Type of Digit bit 0 mask. */ ++#define LCD_TDG0_bp 6 /* Type of Digit bit 0 position. */ ++#define LCD_TDG1_bm (1<<7) /* Type of Digit bit 1 mask. */ ++#define LCD_TDG1_bp 7 /* Type of Digit bit 1 position. */ ++ ++#define LCD_STSEG_gm 0x3F /* Start Segment group mask. */ ++#define LCD_STSEG_gp 0 /* Start Segment group position. */ ++#define LCD_STSEG0_bm (1<<0) /* Start Segment bit 0 mask. */ ++#define LCD_STSEG0_bp 0 /* Start Segment bit 0 position. */ ++#define LCD_STSEG1_bm (1<<1) /* Start Segment bit 1 mask. */ ++#define LCD_STSEG1_bp 1 /* Start Segment bit 1 position. */ ++#define LCD_STSEG2_bm (1<<2) /* Start Segment bit 2 mask. */ ++#define LCD_STSEG2_bp 2 /* Start Segment bit 2 position. */ ++#define LCD_STSEG3_bm (1<<3) /* Start Segment bit 3 mask. */ ++#define LCD_STSEG3_bp 3 /* Start Segment bit 3 position. */ ++#define LCD_STSEG4_bm (1<<4) /* Start Segment bit 4 mask. */ ++#define LCD_STSEG4_bp 4 /* Start Segment bit 4 position. */ ++#define LCD_STSEG5_bm (1<<5) /* Start Segment bit 5 mask. */ ++#define LCD_STSEG5_bp 5 /* Start Segment bit 5 position. */ ++ ++/* LCD.CTRLH bit masks and bit positions */ ++#define LCD_DEC_bm 0x80 /* Decrement of Start Segment bit mask. */ ++#define LCD_DEC_bp 7 /* Decrement of Start Segment bit position. */ ++ ++#define LCD_DCODE_gm 0x7F /* Display Code group mask. */ ++#define LCD_DCODE_gp 0 /* Display Code group position. */ ++#define LCD_DCODE0_bm (1<<0) /* Display Code bit 0 mask. */ ++#define LCD_DCODE0_bp 0 /* Display Code bit 0 position. */ ++#define LCD_DCODE1_bm (1<<1) /* Display Code bit 1 mask. */ ++#define LCD_DCODE1_bp 1 /* Display Code bit 1 position. */ ++#define LCD_DCODE2_bm (1<<2) /* Display Code bit 2 mask. */ ++#define LCD_DCODE2_bp 2 /* Display Code bit 2 position. */ ++#define LCD_DCODE3_bm (1<<3) /* Display Code bit 3 mask. */ ++#define LCD_DCODE3_bp 3 /* Display Code bit 3 position. */ ++#define LCD_DCODE4_bm (1<<4) /* Display Code bit 4 mask. */ ++#define LCD_DCODE4_bp 4 /* Display Code bit 4 position. */ ++#define LCD_DCODE5_bm (1<<5) /* Display Code bit 5 mask. */ ++#define LCD_DCODE5_bp 5 /* Display Code bit 5 position. */ ++#define LCD_DCODE6_bm (1<<6) /* Display Code bit 6 mask. */ ++#define LCD_DCODE6_bp 6 /* Display Code bit 6 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ ++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ ++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ ++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ ++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ ++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ ++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ ++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ ++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ ++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ ++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ ++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ ++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ ++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ ++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ ++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ ++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ ++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ ++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ ++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ ++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* LOCKBIT - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* DMA interrupt vectors */ ++#define DMA_CH0_vect_num 6 ++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ ++#define DMA_CH1_vect_num 7 ++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* USB interrupt vectors */ ++#define USB_BUSEVENT_vect_num 31 ++#define USB_BUSEVENT_vect _VECTOR(31) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ ++#define USB_TRNCOMPL_vect_num 32 ++#define USB_TRNCOMPL_vect _VECTOR(32) /* Transaction complete interrupt */ ++ ++/* LCD interrupt vectors */ ++#define LCD_INT_vect_num 35 ++#define LCD_INT_vect _VECTOR(35) /* LCD Interrupt */ ++ ++/* AES interrupt vectors */ ++#define AES_INT_vect_num 36 ++#define AES_INT_vect _VECTOR(36) /* AES Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 37 ++#define NVM_EE_vect _VECTOR(37) /* EE Interrupt */ ++#define NVM_SPM_vect_num 38 ++#define NVM_SPM_vect _VECTOR(38) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 39 ++#define PORTB_INT0_vect _VECTOR(39) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 40 ++#define PORTB_INT1_vect _VECTOR(40) /* External Interrupt 1 */ ++ ++/* ACB interrupt vectors */ ++#define ACB_AC0_vect_num 41 ++#define ACB_AC0_vect _VECTOR(41) /* AC0 Interrupt */ ++#define ACB_AC1_vect_num 42 ++#define ACB_AC1_vect _VECTOR(42) /* AC1 Interrupt */ ++#define ACB_ACW_vect_num 43 ++#define ACB_ACW_vect _VECTOR(43) /* ACW Window Mode Interrupt */ ++ ++/* ADCB interrupt vectors */ ++#define ADCB_CH0_vect_num 44 ++#define ADCB_CH0_vect _VECTOR(44) /* Interrupt 0 */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 48 ++#define PORTD_INT0_vect _VECTOR(48) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 49 ++#define PORTD_INT1_vect _VECTOR(49) /* External Interrupt 1 */ ++ ++/* PORTG interrupt vectors */ ++#define PORTG_INT0_vect_num 50 ++#define PORTG_INT0_vect _VECTOR(50) /* External Interrupt 0 */ ++#define PORTG_INT1_vect_num 51 ++#define PORTG_INT1_vect _VECTOR(51) /* External Interrupt 1 */ ++ ++/* PORTM interrupt vectors */ ++#define PORTM_INT0_vect_num 52 ++#define PORTM_INT0_vect _VECTOR(52) /* External Interrupt 0 */ ++#define PORTM_INT1_vect_num 53 ++#define PORTM_INT1_vect _VECTOR(53) /* External Interrupt 1 */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (54 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (139264) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (131072) ++#define APP_SECTION_PAGE_SIZE (256) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x1E000) ++#define APPTABLE_SECTION_SIZE (8192) ++#define APPTABLE_SECTION_PAGE_SIZE (256) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x20000) ++#define BOOT_SECTION_SIZE (8192) ++#define BOOT_SECTION_PAGE_SIZE (256) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (16384) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (2048) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (8192) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (2048) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (6) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (256) ++#define USER_SIGNATURES_PAGE_SIZE (256) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (256) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 256 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 */ ++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ ++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ ++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ ++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ ++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ ++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ ++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ ++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ ++#define FUSE0_DEFAULT (0xFF) ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x97 ++#define SIGNATURE_2 0x4B ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA128B3_H_INCLUDED */ ++ +diff --git a/include/avr/iox128c3.h b/include/avr/iox128c3.h +new file mode 100644 +index 0000000..f964085 +--- /dev/null ++++ b/include/avr/iox128c3.h +@@ -0,0 +1,6216 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox128c3.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA128C3_H_INCLUDED ++#define _AVR_ATXMEGA128C3_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t USBCTRL; /* USB Control Register */ ++} CLK_t; ++ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t reserved_0x02; ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++/* USB Prescaler Division Factor */ ++typedef enum CLK_USBPSDIV_enum ++{ ++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ ++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ ++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ ++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ ++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ ++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ ++} CLK_USBPSDIV_t; ++ ++/* USB Clock Source */ ++typedef enum CLK_USBSRC_enum ++{ ++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ ++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ ++} CLK_USBSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 2 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC2MCREF_enum ++{ ++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC2MCREF_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++ register8_t reserved_0x05; ++ register8_t EVOUTSEL; /* Event Output Select */ ++} PORTCFG_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP02MAP_enum ++{ ++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP02MAP_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP13MAP_enum ++{ ++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP13MAP_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t reserved_0x07; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++} ADC_t; ++ ++/* Current Limitation */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ ++} ADC_CURRLIMIT_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ ++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ ++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ ++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* SDA Hold Time */ ++typedef enum TWI_SDAHOLD_enum ++{ ++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ ++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ ++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ ++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ ++} TWI_SDAHOLD_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USB - USB ++-------------------------------------------------------------------------- ++*/ ++ ++/* USB Endpoint */ ++typedef struct USB_EP_struct ++{ ++ register8_t STATUS; /* Endpoint Status */ ++ register8_t CTRL; /* Endpoint Control */ ++ _WORDREGISTER(CNT); /* USB Endpoint Counter */ ++ _WORDREGISTER(DATAPTR); /* Data Pointer */ ++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ ++} USB_EP_t; ++ ++ ++/* Universal Serial Bus */ ++typedef struct USB_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t FIFOWP; /* FIFO Write Pointer Register */ ++ register8_t FIFORP; /* FIFO Read Pointer Register */ ++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ ++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ ++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ ++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t reserved_0x20; ++ register8_t reserved_0x21; ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t CAL0; /* Calibration Byte 0 */ ++ register8_t CAL1; /* Calibration Byte 1 */ ++} USB_t; ++ ++ ++/* USB Endpoint Table */ ++typedef struct USB_EP_TABLE_struct ++{ ++ USB_EP_t EP0OUT; /* Endpoint 0 */ ++ USB_EP_t EP0IN; /* Endpoint 0 */ ++ USB_EP_t EP1OUT; /* Endpoint 1 */ ++ USB_EP_t EP1IN; /* Endpoint 1 */ ++ USB_EP_t EP2OUT; /* Endpoint 2 */ ++ USB_EP_t EP2IN; /* Endpoint 2 */ ++ USB_EP_t EP3OUT; /* Endpoint 3 */ ++ USB_EP_t EP3IN; /* Endpoint 3 */ ++ USB_EP_t EP4OUT; /* Endpoint 4 */ ++ USB_EP_t EP4IN; /* Endpoint 4 */ ++ USB_EP_t EP5OUT; /* Endpoint 5 */ ++ USB_EP_t EP5IN; /* Endpoint 5 */ ++ USB_EP_t EP6OUT; /* Endpoint 6 */ ++ USB_EP_t EP6IN; /* Endpoint 6 */ ++ USB_EP_t EP7OUT; /* Endpoint 7 */ ++ USB_EP_t EP7IN; /* Endpoint 7 */ ++ USB_EP_t EP8OUT; /* Endpoint 8 */ ++ USB_EP_t EP8IN; /* Endpoint 8 */ ++ USB_EP_t EP9OUT; /* Endpoint 9 */ ++ USB_EP_t EP9IN; /* Endpoint 9 */ ++ USB_EP_t EP10OUT; /* Endpoint 10 */ ++ USB_EP_t EP10IN; /* Endpoint 10 */ ++ USB_EP_t EP11OUT; /* Endpoint 11 */ ++ USB_EP_t EP11IN; /* Endpoint 11 */ ++ USB_EP_t EP12OUT; /* Endpoint 12 */ ++ USB_EP_t EP12IN; /* Endpoint 12 */ ++ USB_EP_t EP13OUT; /* Endpoint 13 */ ++ USB_EP_t EP13IN; /* Endpoint 13 */ ++ USB_EP_t EP14OUT; /* Endpoint 14 */ ++ USB_EP_t EP14IN; /* Endpoint 14 */ ++ USB_EP_t EP15OUT; /* Endpoint 15 */ ++ USB_EP_t EP15IN; /* Endpoint 15 */ ++ register8_t reserved_0x100; ++ register8_t reserved_0x101; ++ register8_t reserved_0x102; ++ register8_t reserved_0x103; ++ register8_t reserved_0x104; ++ register8_t reserved_0x105; ++ register8_t reserved_0x106; ++ register8_t reserved_0x107; ++ register8_t reserved_0x108; ++ register8_t reserved_0x109; ++ register8_t reserved_0x10A; ++ register8_t reserved_0x10B; ++ register8_t reserved_0x10C; ++ register8_t reserved_0x10D; ++ register8_t reserved_0x10E; ++ register8_t reserved_0x10F; ++ register8_t FRAMENUML; /* Frame Number Low Byte */ ++ register8_t FRAMENUMH; /* Frame Number High Byte */ ++} USB_EP_TABLE_t; ++ ++/* Interrupt level */ ++typedef enum USB_INTLVL_enum ++{ ++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} USB_INTLVL_t; ++ ++/* USB Endpoint Type */ ++typedef enum USB_EP_TYPE_enum ++{ ++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ ++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ ++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ ++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ ++} USB_EP_TYPE_t; ++ ++/* USB Endpoint Buffersize */ ++typedef enum USB_EP_BUFSIZE_enum ++{ ++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ ++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ ++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ ++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ ++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ ++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ ++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ ++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ ++} USB_EP_BUFSIZE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - I/O Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* I/O Port Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Byte Mode */ ++typedef enum TC_BYTEM_enum ++{ ++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ ++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ ++} TC_BYTEM_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC2 - 16-bit Timer/Counter type 2 ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter type 2 */ ++typedef struct TC2_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t reserved_0x03; ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t reserved_0x08; ++ register8_t CTRLF; /* Control Register F */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t LCNT; /* Low Byte Count */ ++ register8_t HCNT; /* High Byte Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t LPER; /* Low Byte Period */ ++ register8_t HPER; /* High Byte Period */ ++ register8_t LCMPA; /* Low Byte Compare A */ ++ register8_t HCMPA; /* High Byte Compare A */ ++ register8_t LCMPB; /* Low Byte Compare B */ ++ register8_t HCMPB; /* High Byte Compare B */ ++ register8_t LCMPC; /* Low Byte Compare C */ ++ register8_t HCMPC; /* High Byte Compare C */ ++ register8_t LCMPD; /* Low Byte Compare D */ ++ register8_t HCMPD; /* High Byte Compare D */ ++} TC2_t; ++ ++/* Clock Selection */ ++typedef enum TC2_CLKSEL_enum ++{ ++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC2_CLKSEL_t; ++ ++/* Byte Mode */ ++typedef enum TC2_BYTEM_enum ++{ ++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ ++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ ++} TC2_BYTEM_t; ++ ++/* High Byte Underflow Interrupt Level */ ++typedef enum TC2_HUNFINTLVL_enum ++{ ++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_HUNFINTLVL_t; ++ ++/* Low Byte Underflow Interrupt Level */ ++typedef enum TC2_LUNFINTLVL_enum ++{ ++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LUNFINTLVL_t; ++ ++/* Low Byte Compare D Interrupt Level */ ++typedef enum TC2_LCMPDINTLVL_enum ++{ ++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC2_LCMPDINTLVL_t; ++ ++/* Low Byte Compare C Interrupt Level */ ++typedef enum TC2_LCMPCINTLVL_enum ++{ ++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC2_LCMPCINTLVL_t; ++ ++/* Low Byte Compare B Interrupt Level */ ++typedef enum TC2_LCMPBINTLVL_enum ++{ ++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_LCMPBINTLVL_t; ++ ++/* Low Byte Compare A Interrupt Level */ ++typedef enum TC2_LCMPAINTLVL_enum ++{ ++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LCMPAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMD_enum ++{ ++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC2_CMD_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMDEN_enum ++{ ++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ ++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ ++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ ++} TC2_CMDEN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AWEX - Timer/Counter Advanced Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - Timer/Counter High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t reserved_0x00; ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* Timer Oscillator pin location */ ++typedef enum TOSCSEL_enum ++{ ++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ ++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ ++} TOSCSEL_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* BOD operation */ ++typedef enum BODACT_enum ++{ ++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BODACT_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WDP_enum ++{ ++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ ++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ ++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ ++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ ++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ ++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ ++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ ++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ ++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ ++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ ++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ ++} WDP_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LOCKBIT - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ ++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t USBCAL0; /* USB Calibration Byte 0 */ ++ register8_t USBCAL1; /* USB Calibration Byte 1 */ ++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ ++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ ++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ ++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ ++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ ++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ ++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ ++#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) ++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) ++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) ++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++#define CLK_USBCTRL _SFR_MEM8(0x0044) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLL - DFLL */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* USB - Universal Serial Bus */ ++#define USB_CTRLA _SFR_MEM8(0x04C0) ++#define USB_CTRLB _SFR_MEM8(0x04C1) ++#define USB_STATUS _SFR_MEM8(0x04C2) ++#define USB_ADDR _SFR_MEM8(0x04C3) ++#define USB_FIFOWP _SFR_MEM8(0x04C4) ++#define USB_FIFORP _SFR_MEM8(0x04C5) ++#define USB_EPPTR _SFR_MEM16(0x04C6) ++#define USB_INTCTRLA _SFR_MEM8(0x04C8) ++#define USB_INTCTRLB _SFR_MEM8(0x04C9) ++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) ++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) ++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) ++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) ++#define USB_CAL0 _SFR_MEM8(0x04FA) ++#define USB_CAL1 _SFR_MEM8(0x04FB) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_REMAP _SFR_MEM8(0x060E) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_REMAP _SFR_MEM8(0x062E) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_REMAP _SFR_MEM8(0x068E) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORT - I/O Ports */ ++#define PORTF_DIR _SFR_MEM8(0x06A0) ++#define PORTF_DIRSET _SFR_MEM8(0x06A1) ++#define PORTF_DIRCLR _SFR_MEM8(0x06A2) ++#define PORTF_DIRTGL _SFR_MEM8(0x06A3) ++#define PORTF_OUT _SFR_MEM8(0x06A4) ++#define PORTF_OUTSET _SFR_MEM8(0x06A5) ++#define PORTF_OUTCLR _SFR_MEM8(0x06A6) ++#define PORTF_OUTTGL _SFR_MEM8(0x06A7) ++#define PORTF_IN _SFR_MEM8(0x06A8) ++#define PORTF_INTCTRL _SFR_MEM8(0x06A9) ++#define PORTF_INT0MASK _SFR_MEM8(0x06AA) ++#define PORTF_INT1MASK _SFR_MEM8(0x06AB) ++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) ++#define PORTF_REMAP _SFR_MEM8(0x06AE) ++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) ++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) ++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) ++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) ++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) ++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) ++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) ++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCC2_CTRLA _SFR_MEM8(0x0800) ++#define TCC2_CTRLB _SFR_MEM8(0x0801) ++#define TCC2_CTRLC _SFR_MEM8(0x0802) ++#define TCC2_CTRLE _SFR_MEM8(0x0804) ++#define TCC2_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC2_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC2_CTRLF _SFR_MEM8(0x0809) ++#define TCC2_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC2_LCNT _SFR_MEM8(0x0820) ++#define TCC2_HCNT _SFR_MEM8(0x0821) ++#define TCC2_LPER _SFR_MEM8(0x0826) ++#define TCC2_HPER _SFR_MEM8(0x0827) ++#define TCC2_LCMPA _SFR_MEM8(0x0828) ++#define TCC2_HCMPA _SFR_MEM8(0x0829) ++#define TCC2_LCMPB _SFR_MEM8(0x082A) ++#define TCC2_HCMPB _SFR_MEM8(0x082B) ++#define TCC2_LCMPC _SFR_MEM8(0x082C) ++#define TCC2_HCMPC _SFR_MEM8(0x082D) ++#define TCC2_LCMPD _SFR_MEM8(0x082E) ++#define TCC2_HCMPD _SFR_MEM8(0x082F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_STATUSSET _SFR_MEM8(0x0885) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCD2_CTRLA _SFR_MEM8(0x0900) ++#define TCD2_CTRLB _SFR_MEM8(0x0901) ++#define TCD2_CTRLC _SFR_MEM8(0x0902) ++#define TCD2_CTRLE _SFR_MEM8(0x0904) ++#define TCD2_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD2_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD2_CTRLF _SFR_MEM8(0x0909) ++#define TCD2_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD2_LCNT _SFR_MEM8(0x0920) ++#define TCD2_HCNT _SFR_MEM8(0x0921) ++#define TCD2_LPER _SFR_MEM8(0x0926) ++#define TCD2_HPER _SFR_MEM8(0x0927) ++#define TCD2_LCMPA _SFR_MEM8(0x0928) ++#define TCD2_HCMPA _SFR_MEM8(0x0929) ++#define TCD2_LCMPB _SFR_MEM8(0x092A) ++#define TCD2_HCMPB _SFR_MEM8(0x092B) ++#define TCD2_LCMPC _SFR_MEM8(0x092C) ++#define TCD2_HCMPC _SFR_MEM8(0x092D) ++#define TCD2_LCMPD _SFR_MEM8(0x092E) ++#define TCD2_HCMPD _SFR_MEM8(0x092F) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCE2_CTRLA _SFR_MEM8(0x0A00) ++#define TCE2_CTRLB _SFR_MEM8(0x0A01) ++#define TCE2_CTRLC _SFR_MEM8(0x0A02) ++#define TCE2_CTRLE _SFR_MEM8(0x0A04) ++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE2_CTRLF _SFR_MEM8(0x0A09) ++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE2_LCNT _SFR_MEM8(0x0A20) ++#define TCE2_HCNT _SFR_MEM8(0x0A21) ++#define TCE2_LPER _SFR_MEM8(0x0A26) ++#define TCE2_HPER _SFR_MEM8(0x0A27) ++#define TCE2_LCMPA _SFR_MEM8(0x0A28) ++#define TCE2_HCMPA _SFR_MEM8(0x0A29) ++#define TCE2_LCMPB _SFR_MEM8(0x0A2A) ++#define TCE2_HCMPB _SFR_MEM8(0x0A2B) ++#define TCE2_LCMPC _SFR_MEM8(0x0A2C) ++#define TCE2_HCMPC _SFR_MEM8(0x0A2D) ++#define TCE2_LCMPD _SFR_MEM8(0x0A2E) ++#define TCE2_HCMPD _SFR_MEM8(0x0A2F) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCF0_CTRLA _SFR_MEM8(0x0B00) ++#define TCF0_CTRLB _SFR_MEM8(0x0B01) ++#define TCF0_CTRLC _SFR_MEM8(0x0B02) ++#define TCF0_CTRLD _SFR_MEM8(0x0B03) ++#define TCF0_CTRLE _SFR_MEM8(0x0B04) ++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) ++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) ++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) ++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) ++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF0_TEMP _SFR_MEM8(0x0B0F) ++#define TCF0_CNT _SFR_MEM16(0x0B20) ++#define TCF0_PER _SFR_MEM16(0x0B26) ++#define TCF0_CCA _SFR_MEM16(0x0B28) ++#define TCF0_CCB _SFR_MEM16(0x0B2A) ++#define TCF0_CCC _SFR_MEM16(0x0B2C) ++#define TCF0_CCD _SFR_MEM16(0x0B2E) ++#define TCF0_PERBUF _SFR_MEM16(0x0B36) ++#define TCF0_CCABUF _SFR_MEM16(0x0B38) ++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) ++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) ++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCF2_CTRLA _SFR_MEM8(0x0B00) ++#define TCF2_CTRLB _SFR_MEM8(0x0B01) ++#define TCF2_CTRLC _SFR_MEM8(0x0B02) ++#define TCF2_CTRLE _SFR_MEM8(0x0B04) ++#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF2_CTRLF _SFR_MEM8(0x0B09) ++#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF2_LCNT _SFR_MEM8(0x0B20) ++#define TCF2_HCNT _SFR_MEM8(0x0B21) ++#define TCF2_LPER _SFR_MEM8(0x0B26) ++#define TCF2_HPER _SFR_MEM8(0x0B27) ++#define TCF2_LCMPA _SFR_MEM8(0x0B28) ++#define TCF2_HCMPA _SFR_MEM8(0x0B29) ++#define TCF2_LCMPB _SFR_MEM8(0x0B2A) ++#define TCF2_HCMPB _SFR_MEM8(0x0B2B) ++#define TCF2_LCMPC _SFR_MEM8(0x0B2C) ++#define TCF2_HCMPC _SFR_MEM8(0x0B2D) ++#define TCF2_LCMPD _SFR_MEM8(0x0B2E) ++#define TCF2_HCMPD _SFR_MEM8(0x0B2F) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* CLK.USBCTRL bit masks and bit positions */ ++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ ++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ ++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ ++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ ++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ ++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ ++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ ++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ ++ ++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ ++#define CLK_USBSRC_gp 1 /* Clock Source group position. */ ++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ ++ ++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_USB_bm 0x40 /* USB bit mask. */ ++#define PR_USB_bp 6 /* USB bit position. */ ++ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ ++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ ++ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ ++ ++/* PORTCFG.EVOUTSEL bit masks and bit positions */ ++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ ++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ ++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ ++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ ++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ ++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ ++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ ++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ ++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ ++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ ++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ ++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ ++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ ++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ ++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ ++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ ++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ ++ ++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ ++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ ++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ ++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ ++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ ++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ ++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ ++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ ++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ ++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ ++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* RTC - Real-Time Counter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* USB - USB */ ++/* USB_EP.STATUS bit masks and bit positions */ ++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ ++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ ++ ++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ ++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ ++ ++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ ++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ ++ ++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ ++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ ++ ++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ ++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ ++ ++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ ++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ ++ ++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ ++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ ++ ++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ ++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ ++ ++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ ++ ++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ ++ ++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ ++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ ++ ++/* USB_EP.CTRL bit masks and bit positions */ ++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ ++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ ++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ ++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ ++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ ++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ ++ ++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ ++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ ++ ++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ ++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ ++ ++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ ++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ ++ ++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ ++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ ++ ++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ ++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ ++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ ++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ ++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ ++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ ++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ ++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ ++ ++/* USB_EP.CNT bit masks and bit positions */ ++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ ++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ ++ ++/* USB.CTRLA bit masks and bit positions */ ++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ ++#define USB_ENABLE_bp 7 /* USB Enable bit position. */ ++ ++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ ++#define USB_SPEED_bp 6 /* Speed Select bit position. */ ++ ++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ ++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ ++ ++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ ++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ ++ ++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ ++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ ++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ ++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ ++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ ++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ ++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ ++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ ++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ ++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ ++ ++/* USB.CTRLB bit masks and bit positions */ ++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ ++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ ++ ++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ ++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ ++ ++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ ++#define USB_GNACK_bp 1 /* Global NACK bit position. */ ++ ++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ ++#define USB_ATTACH_bp 0 /* Attach bit position. */ ++ ++/* USB.STATUS bit masks and bit positions */ ++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ ++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ ++ ++#define USB_RESUME_bm 0x04 /* Resume bit mask. */ ++#define USB_RESUME_bp 2 /* Resume bit position. */ ++ ++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ ++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ ++ ++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ ++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ ++ ++/* USB.ADDR bit masks and bit positions */ ++#define USB_ADDR_gm 0x7F /* Device Address group mask. */ ++#define USB_ADDR_gp 0 /* Device Address group position. */ ++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ ++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ ++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ ++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ ++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ ++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ ++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ ++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ ++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ ++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ ++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ ++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ ++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ ++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ ++ ++/* USB.FIFOWP bit masks and bit positions */ ++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ ++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ ++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ ++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ ++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ ++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ ++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ ++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ ++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ ++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ ++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ ++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ ++ ++/* USB.FIFORP bit masks and bit positions */ ++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ ++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ ++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ ++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ ++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ ++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ ++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ ++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ ++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ ++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ ++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ ++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ ++ ++/* USB.INTCTRLA bit masks and bit positions */ ++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ ++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ ++ ++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ ++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ ++ ++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ ++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ ++ ++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ ++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ ++ ++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* USB.INTCTRLB bit masks and bit positions */ ++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ ++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ ++ ++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ ++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ ++ ++/* USB.INTFLAGSACLR bit masks and bit positions */ ++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ ++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ ++ ++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ ++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ ++ ++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ ++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ ++ ++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ ++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ ++ ++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ ++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ ++ ++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ ++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ ++ ++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ ++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ ++ ++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ ++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSASET bit masks and bit positions */ ++/* USB_SOFIF Predefined. */ ++/* USB_SOFIF Predefined. */ ++ ++/* USB_SUSPENDIF Predefined. */ ++/* USB_SUSPENDIF Predefined. */ ++ ++/* USB_RESUMEIF Predefined. */ ++/* USB_RESUMEIF Predefined. */ ++ ++/* USB_RSTIF Predefined. */ ++/* USB_RSTIF Predefined. */ ++ ++/* USB_CRCIF Predefined. */ ++/* USB_CRCIF Predefined. */ ++ ++/* USB_UNFIF Predefined. */ ++/* USB_UNFIF Predefined. */ ++ ++/* USB_OVFIF Predefined. */ ++/* USB_OVFIF Predefined. */ ++ ++/* USB_STALLIF Predefined. */ ++/* USB_STALLIF Predefined. */ ++ ++/* USB.INTFLAGSBCLR bit masks and bit positions */ ++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ ++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ ++ ++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ ++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSBSET bit masks and bit positions */ ++/* USB_TRNIF Predefined. */ ++/* USB_TRNIF Predefined. */ ++ ++/* USB_SETUPIF Predefined. */ ++/* USB_SETUPIF Predefined. */ ++ ++/* PORT - I/O Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_SPI_bm 0x20 /* SPI bit mask. */ ++#define PORT_SPI_bp 5 /* SPI bit position. */ ++ ++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ ++#define PORT_USART0_bp 4 /* USART0 bit position. */ ++ ++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ ++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ ++ ++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ ++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ ++ ++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ ++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ ++ ++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ ++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD Predefined. */ ++/* TC0_CMD Predefined. */ ++ ++/* TC0_LUPD Predefined. */ ++/* TC0_LUPD Predefined. */ ++ ++/* TC0_DIR Predefined. */ ++/* TC0_DIR Predefined. */ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV Predefined. */ ++/* TC0_CCDBV Predefined. */ ++ ++/* TC0_CCCBV Predefined. */ ++/* TC0_CCCBV Predefined. */ ++ ++/* TC0_CCBBV Predefined. */ ++/* TC0_CCBBV Predefined. */ ++ ++/* TC0_CCABV Predefined. */ ++/* TC0_CCABV Predefined. */ ++ ++/* TC0_PERBV Predefined. */ ++/* TC0_PERBV Predefined. */ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD Predefined. */ ++/* TC1_CMD Predefined. */ ++ ++/* TC1_LUPD Predefined. */ ++/* TC1_LUPD Predefined. */ ++ ++/* TC1_DIR Predefined. */ ++/* TC1_DIR Predefined. */ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV Predefined. */ ++/* TC1_CCBBV Predefined. */ ++ ++/* TC1_CCABV Predefined. */ ++/* TC1_CCABV Predefined. */ ++ ++/* TC1_PERBV Predefined. */ ++/* TC1_PERBV Predefined. */ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++/* TC2.CTRLA bit masks and bit positions */ ++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC2.CTRLB bit masks and bit positions */ ++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ ++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ ++ ++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ ++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ ++ ++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ ++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ ++ ++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ ++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ ++ ++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ ++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ ++ ++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ ++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ ++ ++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ ++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ ++ ++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ ++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ ++ ++/* TC2.CTRLC bit masks and bit positions */ ++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ ++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ ++ ++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ ++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ ++ ++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ ++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ ++ ++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ ++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ ++ ++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ ++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ ++ ++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ ++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ ++ ++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ ++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ ++ ++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ ++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ ++ ++/* TC2.CTRLE bit masks and bit positions */ ++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC2.INTCTRLA bit masks and bit positions */ ++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ ++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ ++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ ++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ ++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ ++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ ++ ++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ ++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ ++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ ++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ ++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ ++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ ++ ++/* TC2.INTCTRLB bit masks and bit positions */ ++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ ++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ ++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ ++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ ++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ ++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ ++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ ++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ ++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ ++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ ++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ ++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ ++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ ++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ ++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ ++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ ++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ ++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ ++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ ++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ ++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ ++ ++/* TC2.CTRLF bit masks and bit positions */ ++#define TC2_CMD_gm 0x0C /* Command group mask. */ ++#define TC2_CMD_gp 2 /* Command group position. */ ++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC2_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC2_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ ++#define TC2_CMDEN_gp 0 /* Command Enable group position. */ ++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ ++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ ++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ ++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ ++ ++/* TC2.INTFLAGS bit masks and bit positions */ ++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ ++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ ++ ++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ ++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ ++ ++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ ++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ ++ ++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ ++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ ++ ++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ ++ ++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ ++ ++/* AWEX - Timer/Counter Advanced Waveform Extension */ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++/* AWEX.STATUSSET bit masks and bit positions */ ++/* AWEX_FDF Predefined. */ ++/* AWEX_FDF Predefined. */ ++ ++/* AWEX_DTHSBUFV Predefined. */ ++/* AWEX_DTHSBUFV Predefined. */ ++ ++/* AWEX_DTLSBUFV Predefined. */ ++/* AWEX_DTLSBUFV Predefined. */ ++ ++/* HIRES - Timer/Counter High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ ++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* LOCKBIT - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LUNF_vect_num 14 ++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_HUNF_vect_num 15 ++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPA_vect_num 16 ++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPB_vect_num 17 ++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPC_vect_num 18 ++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPD_vect_num 19 ++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LUNF_vect_num 47 ++#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_HUNF_vect_num 48 ++#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPA_vect_num 49 ++#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPB_vect_num 50 ++#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPC_vect_num 51 ++#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPD_vect_num 52 ++#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LUNF_vect_num 77 ++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_HUNF_vect_num 78 ++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPA_vect_num 79 ++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPB_vect_num 80 ++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPC_vect_num 81 ++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPD_vect_num 82 ++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* PORTF interrupt vectors */ ++#define PORTF_INT0_vect_num 104 ++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ ++#define PORTF_INT1_vect_num 105 ++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_OVF_vect_num 108 ++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LUNF_vect_num 108 ++#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_ERR_vect_num 109 ++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_HUNF_vect_num 109 ++#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCA_vect_num 110 ++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPA_vect_num 110 ++#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCB_vect_num 111 ++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPB_vect_num 111 ++#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCC_vect_num 112 ++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPC_vect_num 112 ++#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCD_vect_num 113 ++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPD_vect_num 113 ++#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ ++ ++/* USB interrupt vectors */ ++#define USB_BUSEVENT_vect_num 125 ++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ ++#define USB_TRNCOMPL_vect_num 126 ++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (127 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (139264) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (131072) ++#define APP_SECTION_PAGE_SIZE (512) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x1E000) ++#define APPTABLE_SECTION_SIZE (8192) ++#define APPTABLE_SECTION_PAGE_SIZE (512) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x20000) ++#define BOOT_SECTION_SIZE (8192) ++#define BOOT_SECTION_PAGE_SIZE (512) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (16384) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (2048) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (8192) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (2048) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (6) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (512) ++#define USER_SIGNATURES_PAGE_SIZE (512) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (64) ++#define PROD_SIGNATURES_PAGE_SIZE (512) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 512 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 Reserved */ ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x97 ++#define SIGNATURE_2 0x52 ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA128C3_H_INCLUDED */ ++ +diff --git a/include/avr/iox128d3.h b/include/avr/iox128d3.h +index df0ce13..cfe1090 100644 +--- a/include/avr/iox128d3.h ++++ b/include/avr/iox128d3.h +@@ -1,5655 +1,5704 @@ +-/* Copyright (c) 2009-2010 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iox128d3.h 2194 2010-11-16 15:10:51Z arcanum $ */ +- +-/* avr/iox128d3.h - definitions for ATxmega128D3 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iox128d3.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATxmega128D3_H_ +-#define _AVR_ATxmega128D3_H_ 1 +- +- +-/* Ungrouped common registers */ +-#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +-#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +-#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +-#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +-#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +-#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +-#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +-#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +-#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +-#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +-#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +-#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +-#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +-#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +-#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +-#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +- +-#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +-#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +-#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +-#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +-#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +-#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +-#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +-#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +-#define SREG _SFR_MEM8(0x003F) /* Status Register */ +- +- +-/* C Language Only */ +-#if !defined (__ASSEMBLER__) +- +-#include +- +-typedef volatile uint8_t register8_t; +-typedef volatile uint16_t register16_t; +-typedef volatile uint32_t register32_t; +- +- +-#ifdef _WORDREGISTER +-#undef _WORDREGISTER +-#endif +-#define _WORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register16_t regname; \ +- struct \ +- { \ +- register8_t regname ## L; \ +- register8_t regname ## H; \ +- }; \ +- } +- +-#ifdef _DWORDREGISTER +-#undef _DWORDREGISTER +-#endif +-#define _DWORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register32_t regname; \ +- struct \ +- { \ +- register8_t regname ## 0; \ +- register8_t regname ## 1; \ +- register8_t regname ## 2; \ +- register8_t regname ## 3; \ +- }; \ +- } +- +- +-/* +-========================================================================== +-IO Module Structures +-========================================================================== +-*/ +- +- +-/* +--------------------------------------------------------------------------- +-XOCD - On-Chip Debug System +--------------------------------------------------------------------------- +-*/ +- +-/* On-Chip Debug System */ +-typedef struct OCD_struct +-{ +- register8_t OCDR0; /* OCD Register 0 */ +- register8_t OCDR1; /* OCD Register 1 */ +-} OCD_t; +- +- +-/* CCP signatures */ +-typedef enum CCP_enum +-{ +- CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ +- CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +-} CCP_t; +- +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Clock System */ +-typedef struct CLK_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t PSCTRL; /* Prescaler Control Register */ +- register8_t LOCK; /* Lock register */ +- register8_t RTCCTRL; /* RTC Control Register */ +-} CLK_t; +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Power Reduction */ +-typedef struct PR_struct +-{ +- register8_t PRGEN; /* General Power Reduction */ +- register8_t PRPA; /* Power Reduction Port A */ +- register8_t PRPB; /* Power Reduction Port B */ +- register8_t PRPC; /* Power Reduction Port C */ +- register8_t PRPD; /* Power Reduction Port D */ +- register8_t PRPE; /* Power Reduction Port E */ +- register8_t PRPF; /* Power Reduction Port F */ +-} PR_t; +- +-/* System Clock Selection */ +-typedef enum CLK_SCLKSEL_enum +-{ +- CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ +- CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ +- CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ +- CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ +- CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +-} CLK_SCLKSEL_t; +- +-/* Prescaler A Division Factor */ +-typedef enum CLK_PSADIV_enum +-{ +- CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ +- CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ +- CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ +- CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ +- CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ +- CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ +- CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ +- CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ +- CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ +- CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +-} CLK_PSADIV_t; +- +-/* Prescaler B and C Division Factor */ +-typedef enum CLK_PSBCDIV_enum +-{ +- CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ +- CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ +- CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ +- CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +-} CLK_PSBCDIV_t; +- +-/* RTC Clock Source */ +-typedef enum CLK_RTCSRC_enum +-{ +- CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ +- CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ +- CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ +- CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +-} CLK_RTCSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-SLEEP - Sleep Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Sleep Controller */ +-typedef struct SLEEP_struct +-{ +- register8_t CTRL; /* Control Register */ +-} SLEEP_t; +- +-/* Sleep Mode */ +-typedef enum SLEEP_SMODE_enum +-{ +- SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ +- SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +- SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ +- SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ +- SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +-} SLEEP_SMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-OSC - Oscillator +--------------------------------------------------------------------------- +-*/ +- +-/* Oscillator */ +-typedef struct OSC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t XOSCCTRL; /* External Oscillator Control Register */ +- register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ +- register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ +- register8_t PLLCTRL; /* PLL Control REgister */ +- register8_t DFLLCTRL; /* DFLL Control Register */ +-} OSC_t; +- +-/* Oscillator Frequency Range */ +-typedef enum OSC_FRQRANGE_enum +-{ +- OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ +- OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ +- OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ +- OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +-} OSC_FRQRANGE_t; +- +-/* External Oscillator Selection and Startup Time */ +-typedef enum OSC_XOSCSEL_enum +-{ +- OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ +- OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ +- OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ +- OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ +- OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +-} OSC_XOSCSEL_t; +- +-/* PLL Clock Source */ +-typedef enum OSC_PLLSRC_enum +-{ +- OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ +- OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ +- OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +-} OSC_PLLSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-DFLL - DFLL +--------------------------------------------------------------------------- +-*/ +- +-/* DFLL */ +-typedef struct DFLL_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t CALA; /* Calibration Register A */ +- register8_t CALB; /* Calibration Register B */ +- register8_t COMP0; /* Oscillator Compare Register 0 */ +- register8_t COMP1; /* Oscillator Compare Register 1 */ +- register8_t COMP2; /* Oscillator Compare Register 2 */ +- register8_t reserved_0x07; +-} DFLL_t; +- +- +-/* +--------------------------------------------------------------------------- +-RST - Reset +--------------------------------------------------------------------------- +-*/ +- +-/* Reset */ +-typedef struct RST_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t CTRL; /* Control Register */ +-} RST_t; +- +- +-/* +--------------------------------------------------------------------------- +-WDT - Watch-Dog Timer +--------------------------------------------------------------------------- +-*/ +- +-/* Watch-Dog Timer */ +-typedef struct WDT_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t WINCTRL; /* Windowed Mode Control */ +- register8_t STATUS; /* Status */ +-} WDT_t; +- +-/* Period setting */ +-typedef enum WDT_PER_enum +-{ +- WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ +- WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ +- WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ +- WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_PER_t; +- +-/* Closed window period */ +-typedef enum WDT_WPER_enum +-{ +- WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ +- WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ +- WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ +- WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_WPER_t; +- +- +-/* +--------------------------------------------------------------------------- +-MCU - MCU Control +--------------------------------------------------------------------------- +-*/ +- +-/* MCU Control */ +-typedef struct MCU_struct +-{ +- register8_t DEVID0; /* Device ID byte 0 */ +- register8_t DEVID1; /* Device ID byte 1 */ +- register8_t DEVID2; /* Device ID byte 2 */ +- register8_t REVID; /* Revision ID */ +- register8_t JTAGUID; /* JTAG User ID */ +- register8_t reserved_0x05; +- register8_t MCUCR; /* MCU Control */ +- register8_t reserved_0x07; +- register8_t EVSYSLOCK; /* Event System Lock */ +- register8_t AWEXLOCK; /* AWEX Lock */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +-} MCU_t; +- +- +-/* +--------------------------------------------------------------------------- +-PMIC - Programmable Multi-level Interrupt Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Programmable Multi-level Interrupt Controller */ +-typedef struct PMIC_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t INTPRI; /* Interrupt Priority */ +- register8_t CTRL; /* Control Register */ +-} PMIC_t; +- +- +-/* +--------------------------------------------------------------------------- +-EVSYS - Event System +--------------------------------------------------------------------------- +-*/ +- +-/* Event System */ +-typedef struct EVSYS_struct +-{ +- register8_t CH0MUX; /* Event Channel 0 Multiplexer */ +- register8_t CH1MUX; /* Event Channel 1 Multiplexer */ +- register8_t CH2MUX; /* Event Channel 2 Multiplexer */ +- register8_t CH3MUX; /* Event Channel 3 Multiplexer */ +- register8_t reserved_0x04; +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t CH0CTRL; /* Channel 0 Control Register */ +- register8_t CH1CTRL; /* Channel 1 Control Register */ +- register8_t CH2CTRL; /* Channel 2 Control Register */ +- register8_t CH3CTRL; /* Channel 3 Control Register */ +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t STROBE; /* Event Strobe */ +- register8_t DATA; /* Event Data */ +-} EVSYS_t; +- +-/* Quadrature Decoder Index Recognition Mode */ +-typedef enum EVSYS_QDIRM_enum +-{ +- EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ +- EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ +- EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ +- EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +-} EVSYS_QDIRM_t; +- +-/* Digital filter coefficient */ +-typedef enum EVSYS_DIGFILT_enum +-{ +- EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ +- EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ +- EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ +- EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ +- EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ +- EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ +- EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ +- EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +-} EVSYS_DIGFILT_t; +- +-/* Event Channel multiplexer input selection */ +-typedef enum EVSYS_CHMUX_enum +-{ +- EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ +- EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ +- EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ +- EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ +- EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ +- EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ +- EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ +- EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ +- EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ +- EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ +- EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ +- EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ +- EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ +- EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ +- EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ +- EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ +- EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ +- EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ +- EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ +- EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ +- EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ +- EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ +- EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ +- EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ +- EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ +- EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ +- EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ +- EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ +- EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ +- EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ +- EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ +- EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ +- EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ +- EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ +- EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ +- EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ +- EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ +- EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ +- EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ +- EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ +- EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ +- EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ +- EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ +- EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ +- EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ +- EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ +- EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ +- EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ +- EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ +- EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ +- EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ +- EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ +- EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ +- EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ +- EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ +- EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ +- EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ +- EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ +- EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ +- EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ +- EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ +- EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ +- EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ +- EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ +- EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ +- EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ +- EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ +- EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ +- EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ +- EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ +- EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ +- EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ +- EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ +- EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ +- EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ +- EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ +- EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ +- EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ +- EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ +- EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ +- EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ +- EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ +- EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ +- EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ +- EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ +- EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ +- EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ +- EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ +- EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ +- EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ +- EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ +- EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ +- EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ +- EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ +- EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ +- EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ +- EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ +- EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ +- EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ +- EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ +- EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +- EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ +- EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ +- EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ +- EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +-} EVSYS_CHMUX_t; +- +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Non-volatile Memory Controller */ +-typedef struct NVM_struct +-{ +- register8_t ADDR0; /* Address Register 0 */ +- register8_t ADDR1; /* Address Register 1 */ +- register8_t ADDR2; /* Address Register 2 */ +- register8_t reserved_0x03; +- register8_t DATA0; /* Data Register 0 */ +- register8_t DATA1; /* Data Register 1 */ +- register8_t DATA2; /* Data Register 2 */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t CMD; /* Command */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t INTCTRL; /* Interrupt Control */ +- register8_t reserved_0x0E; +- register8_t STATUS; /* Status */ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Lock Bits */ +-typedef struct NVM_LOCKBITS_struct +-{ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_LOCKBITS_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Fuses */ +-typedef struct NVM_FUSES_struct +-{ +- register8_t FUSEBYTE0; /* User ID */ +- register8_t FUSEBYTE1; /* Watchdog Configuration */ +- register8_t FUSEBYTE2; /* Reset Configuration */ +- register8_t reserved_0x03; +- register8_t FUSEBYTE4; /* Start-up Configuration */ +- register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +-} NVM_FUSES_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Production Signatures */ +-typedef struct NVM_PROD_SIGNATURES_struct +-{ +- register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ +- register8_t reserved_0x01; +- register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ +- register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ +- register8_t reserved_0x04; +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ +- register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ +- register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ +- register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ +- register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ +- register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t WAFNUM; /* Wafer Number */ +- register8_t reserved_0x11; +- register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ +- register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ +- register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ +- register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ +- register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ +- register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ +- register8_t reserved_0x26; +- register8_t reserved_0x27; +- register8_t reserved_0x28; +- register8_t reserved_0x29; +- register8_t reserved_0x2A; +- register8_t reserved_0x2B; +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ +- register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ +- register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ +- register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ +- register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ +- register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- register8_t reserved_0x36; +- register8_t reserved_0x37; +- register8_t reserved_0x38; +- register8_t reserved_0x39; +- register8_t reserved_0x3A; +- register8_t reserved_0x3B; +- register8_t reserved_0x3C; +- register8_t reserved_0x3D; +- register8_t reserved_0x3E; +-} NVM_PROD_SIGNATURES_t; +- +-/* NVM Command */ +-typedef enum NVM_CMD_enum +-{ +- NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ +- NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ +- NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ +- NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ +- NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ +- NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ +- NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ +- NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ +- NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ +- NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ +- NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ +- NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ +- NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ +- NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ +- NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ +- NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ +- NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ +- NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ +- NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ +- NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ +- NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ +- NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ +- NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ +- NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ +- NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ +- NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +-} NVM_CMD_t; +- +-/* SPM ready interrupt level */ +-typedef enum NVM_SPMLVL_enum +-{ +- NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ +- NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ +- NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +-} NVM_SPMLVL_t; +- +-/* EEPROM ready interrupt level */ +-typedef enum NVM_EELVL_enum +-{ +- NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ +- NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ +- NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +-} NVM_EELVL_t; +- +-/* Boot lock bits - boot setcion */ +-typedef enum NVM_BLBB_enum +-{ +- NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +- NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ +- NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ +- NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +-} NVM_BLBB_t; +- +-/* Boot lock bits - application section */ +-typedef enum NVM_BLBA_enum +-{ +- NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +- NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ +- NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ +- NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +-} NVM_BLBA_t; +- +-/* Boot lock bits - application table section */ +-typedef enum NVM_BLBAT_enum +-{ +- NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +- NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ +- NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ +- NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +-} NVM_BLBAT_t; +- +-/* Lock bits */ +-typedef enum NVM_LB_enum +-{ +- NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +- NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ +- NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +-} NVM_LB_t; +- +-/* Boot Loader Section Reset Vector */ +-typedef enum BOOTRST_enum +-{ +- BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ +- BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +-} BOOTRST_t; +- +-/* BOD operation */ +-typedef enum BOD_enum +-{ +- BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ +- BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ +- BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +-} BOD_t; +- +-/* Watchdog (Window) Timeout Period */ +-typedef enum WD_enum +-{ +- WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ +- WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ +- WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ +- WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ +- WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ +- WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ +- WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ +- WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ +- WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ +- WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ +- WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +-} WD_t; +- +-/* Start-up Time */ +-typedef enum SUT_enum +-{ +- SUT_0MS_gc = (0x03<<2), /* 0 ms */ +- SUT_4MS_gc = (0x01<<2), /* 4 ms */ +- SUT_64MS_gc = (0x00<<2), /* 64 ms */ +-} SUT_t; +- +-/* Brown Out Detection Voltage Level */ +-typedef enum BODLVL_enum +-{ +- BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ +- BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ +- BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ +- BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ +- BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ +- BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ +- BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ +-} BODLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-AC - Analog Comparator +--------------------------------------------------------------------------- +-*/ +- +-/* Analog Comparator */ +-typedef struct AC_struct +-{ +- register8_t AC0CTRL; /* Comparator 0 Control */ +- register8_t AC1CTRL; /* Comparator 1 Control */ +- register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ +- register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t WINCTRL; /* Window Mode Control */ +- register8_t STATUS; /* Status */ +-} AC_t; +- +-/* Interrupt mode */ +-typedef enum AC_INTMODE_enum +-{ +- AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ +- AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ +- AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +-} AC_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum AC_INTLVL_enum +-{ +- AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ +- AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ +- AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ +- AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +-} AC_INTLVL_t; +- +-/* Hysteresis mode selection */ +-typedef enum AC_HYSMODE_enum +-{ +- AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ +- AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ +- AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +-} AC_HYSMODE_t; +- +-/* Positive input multiplexer selection */ +-typedef enum AC_MUXPOS_enum +-{ +- AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ +- AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ +- AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ +- AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ +- AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ +- AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ +- AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +- AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +-} AC_MUXPOS_t; +- +-/* Negative input multiplexer selection */ +-typedef enum AC_MUXNEG_enum +-{ +- AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ +- AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ +- AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ +- AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ +- AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ +- AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ +- AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ +- AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +-} AC_MUXNEG_t; +- +-/* Windows interrupt mode */ +-typedef enum AC_WINTMODE_enum +-{ +- AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ +- AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ +- AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ +- AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +-} AC_WINTMODE_t; +- +-/* Window interrupt level */ +-typedef enum AC_WINTLVL_enum +-{ +- AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ +- AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ +- AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +-} AC_WINTLVL_t; +- +-/* Window mode state */ +-typedef enum AC_WSTATE_enum +-{ +- AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ +- AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ +- AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +-} AC_WSTATE_t; +- +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* ADC Channel */ +-typedef struct ADC_CH_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t MUXCTRL; /* MUX Control */ +- register8_t INTCTRL; /* Channel Interrupt Control */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- _WORDREGISTER(RES); /* Channel Result */ +- register8_t reserved_0x6; +- register8_t reserved_0x7; +-} ADC_CH_t; +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Analog-to-Digital Converter */ +-typedef struct ADC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t REFCTRL; /* Reference Control */ +- register8_t EVCTRL; /* Event Control */ +- register8_t PRESCALER; /* Clock Prescaler */ +- register8_t reserved_0x05; +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- _WORDREGISTER(CAL); /* Calibration Value */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- _WORDREGISTER(CH0RES); /* Channel 0 Result */ +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- _WORDREGISTER(CMP); /* Compare Value */ +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- ADC_CH_t CH0; /* ADC Channel 0 */ +-} ADC_t; +- +-/* Positive input multiplexer selection */ +-typedef enum ADC_CH_MUXPOS_enum +-{ +- ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ +- ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ +- ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ +- ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ +- ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ +- ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ +- ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ +- ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +-} ADC_CH_MUXPOS_t; +- +-/* Internal input multiplexer selections */ +-typedef enum ADC_CH_MUXINT_enum +-{ +- ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ +- ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ +- ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +- ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +-} ADC_CH_MUXINT_t; +- +-/* Negative input multiplexer selection */ +-typedef enum ADC_CH_MUXNEG_enum +-{ +- ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ +- ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ +- ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ +- ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ +- ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ +- ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ +- ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ +- ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +-} ADC_CH_MUXNEG_t; +- +-/* Input mode */ +-typedef enum ADC_CH_INPUTMODE_enum +-{ +- ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ +- ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ +- ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ +- ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +-} ADC_CH_INPUTMODE_t; +- +-/* Gain factor */ +-typedef enum ADC_CH_GAIN_enum +-{ +- ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ +- ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ +- ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ +- ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ +- ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ +- ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ +- ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ +-} ADC_CH_GAIN_t; +- +-/* Conversion result resolution */ +-typedef enum ADC_RESOLUTION_enum +-{ +- ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ +- ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ +- ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +-} ADC_RESOLUTION_t; +- +-/* Voltage reference selection */ +-typedef enum ADC_REFSEL_enum +-{ +- ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ +- ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ +- ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ +- ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +-} ADC_REFSEL_t; +- +-/* Channel sweep selection */ +-typedef enum ADC_SWEEP_enum +-{ +- ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ +-} ADC_SWEEP_t; +- +-/* Event channel input selection */ +-typedef enum ADC_EVSEL_enum +-{ +- ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ +- ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ +- ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ +- ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ +- ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ +- ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ +- ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ +- ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +-} ADC_EVSEL_t; +- +-/* Event action selection */ +-typedef enum ADC_EVACT_enum +-{ +- ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ +- ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ +-} ADC_EVACT_t; +- +-/* Interupt mode */ +-typedef enum ADC_CH_INTMODE_enum +-{ +- ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ +- ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ +- ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +-} ADC_CH_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum ADC_CH_INTLVL_enum +-{ +- ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ +- ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ +- ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +-} ADC_CH_INTLVL_t; +- +-/* Clock prescaler */ +-typedef enum ADC_PRESCALER_enum +-{ +- ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ +- ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ +- ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ +- ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ +- ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ +- ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ +- ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ +- ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +-} ADC_PRESCALER_t; +- +- +-/* +--------------------------------------------------------------------------- +-RTC - Real-Time Clounter +--------------------------------------------------------------------------- +-*/ +- +-/* Real-Time Counter */ +-typedef struct RTC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t TEMP; /* Temporary register */ +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- _WORDREGISTER(CNT); /* Count Register */ +- _WORDREGISTER(PER); /* Period Register */ +- _WORDREGISTER(COMP); /* Compare Register */ +-} RTC_t; +- +-/* Prescaler Factor */ +-typedef enum RTC_PRESCALER_enum +-{ +- RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ +- RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ +- RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ +- RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ +- RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ +- RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ +- RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ +- RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +-} RTC_PRESCALER_t; +- +-/* Compare Interrupt level */ +-typedef enum RTC_COMPINTLVL_enum +-{ +- RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} RTC_COMPINTLVL_t; +- +-/* Overflow Interrupt level */ +-typedef enum RTC_OVFINTLVL_enum +-{ +- RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} RTC_OVFINTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* EBI Chip Select Module */ +-typedef struct EBI_CS_struct +-{ +- register8_t CTRLA; /* Chip Select Control Register A */ +- register8_t CTRLB; /* Chip Select Control Register B */ +- _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +-} EBI_CS_t; +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* External Bus Interface */ +-typedef struct EBI_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t SDRAMCTRLA; /* SDRAM Control Register A */ +- register8_t reserved_0x02; +- register8_t reserved_0x03; +- _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ +- _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ +- register8_t SDRAMCTRLB; /* SDRAM Control Register B */ +- register8_t SDRAMCTRLC; /* SDRAM Control Register C */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- EBI_CS_t CS0; /* Chip Select 0 */ +- EBI_CS_t CS1; /* Chip Select 1 */ +- EBI_CS_t CS2; /* Chip Select 2 */ +- EBI_CS_t CS3; /* Chip Select 3 */ +-} EBI_t; +- +-/* Chip Select adress space */ +-typedef enum EBI_CS_ASIZE_enum +-{ +- EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ +- EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ +- EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ +- EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ +- EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ +- EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ +- EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ +- EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ +- EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ +- EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ +- EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ +- EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ +- EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ +- EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ +- EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ +- EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ +- EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +-} EBI_CS_ASIZE_t; +- +-/* */ +-typedef enum EBI_CS_SRWS_enum +-{ +- EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_CS_SRWS_t; +- +-/* Chip Select address mode */ +-typedef enum EBI_CS_MODE_enum +-{ +- EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ +- EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ +- EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ +- EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +-} EBI_CS_MODE_t; +- +-/* Chip Select SDRAM mode */ +-typedef enum EBI_CS_SDMODE_enum +-{ +- EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ +- EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +-} EBI_CS_SDMODE_t; +- +-/* */ +-typedef enum EBI_SDDATAW_enum +-{ +- EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ +- EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +-} EBI_SDDATAW_t; +- +-/* */ +-typedef enum EBI_LPCMODE_enum +-{ +- EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ +- EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +-} EBI_LPCMODE_t; +- +-/* */ +-typedef enum EBI_SRMODE_enum +-{ +- EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ +- EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ +- EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ +- EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +-} EBI_SRMODE_t; +- +-/* */ +-typedef enum EBI_IFMODE_enum +-{ +- EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ +- EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ +- EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ +- EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +-} EBI_IFMODE_t; +- +-/* */ +-typedef enum EBI_SDCOL_enum +-{ +- EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ +- EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ +- EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ +- EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +-} EBI_SDCOL_t; +- +-/* */ +-typedef enum EBI_MRDLY_enum +-{ +- EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_MRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCYCDLY_enum +-{ +- EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ROWCYCDLY_t; +- +-/* */ +-typedef enum EBI_RPDLY_enum +-{ +- EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_RPDLY_t; +- +-/* */ +-typedef enum EBI_WRDLY_enum +-{ +- EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_WRDLY_t; +- +-/* */ +-typedef enum EBI_ESRDLY_enum +-{ +- EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ESRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCOLDLY_enum +-{ +- EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_ROWCOLDLY_t; +- +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_MASTER_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t STATUS; /* Status Register */ +- register8_t BAUD; /* Baurd Rate Control Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +-} TWI_MASTER_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_SLAVE_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t STATUS; /* Status Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +- register8_t ADDRMASK; /* Address Mask Register */ +-} TWI_SLAVE_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Two-Wire Interface */ +-typedef struct TWI_struct +-{ +- register8_t CTRL; /* TWI Common Control Register */ +- TWI_MASTER_t MASTER; /* TWI master module */ +- TWI_SLAVE_t SLAVE; /* TWI slave module */ +-} TWI_t; +- +-/* Master Interrupt Level */ +-typedef enum TWI_MASTER_INTLVL_enum +-{ +- TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_MASTER_INTLVL_t; +- +-/* Inactive Timeout */ +-typedef enum TWI_MASTER_TIMEOUT_enum +-{ +- TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ +- TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ +- TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ +- TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +-} TWI_MASTER_TIMEOUT_t; +- +-/* Master Command */ +-typedef enum TWI_MASTER_CMD_enum +-{ +- TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ +- TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ +- TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +-} TWI_MASTER_CMD_t; +- +-/* Master Bus State */ +-typedef enum TWI_MASTER_BUSSTATE_enum +-{ +- TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ +- TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ +- TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ +- TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +-} TWI_MASTER_BUSSTATE_t; +- +-/* Slave Interrupt Level */ +-typedef enum TWI_SLAVE_INTLVL_enum +-{ +- TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_SLAVE_INTLVL_t; +- +-/* Slave Command */ +-typedef enum TWI_SLAVE_CMD_enum +-{ +- TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ +- TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +-} TWI_SLAVE_CMD_t; +- +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O port Configuration */ +-typedef struct PORTCFG_struct +-{ +- register8_t MPCMASK; /* Multi-pin Configuration Mask */ +- register8_t reserved_0x01; +- register8_t VPCTRLA; /* Virtual Port Control Register A */ +- register8_t VPCTRLB; /* Virtual Port Control Register B */ +- register8_t CLKEVOUT; /* Clock and Event Out Register */ +-} PORTCFG_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* Virtual Port */ +-typedef struct VPORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t OUT; /* I/O Port Output */ +- register8_t IN; /* I/O Port Input */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +-} VPORT_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O Ports */ +-typedef struct PORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t DIRSET; /* I/O Port Data Direction Set */ +- register8_t DIRCLR; /* I/O Port Data Direction Clear */ +- register8_t DIRTGL; /* I/O Port Data Direction Toggle */ +- register8_t OUT; /* I/O Port Output */ +- register8_t OUTSET; /* I/O Port Output Set */ +- register8_t OUTCLR; /* I/O Port Output Clear */ +- register8_t OUTTGL; /* I/O Port Output Toggle */ +- register8_t IN; /* I/O port Input */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INT0MASK; /* Port Interrupt 0 Mask */ +- register8_t INT1MASK; /* Port Interrupt 1 Mask */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t PIN0CTRL; /* Pin 0 Control Register */ +- register8_t PIN1CTRL; /* Pin 1 Control Register */ +- register8_t PIN2CTRL; /* Pin 2 Control Register */ +- register8_t PIN3CTRL; /* Pin 3 Control Register */ +- register8_t PIN4CTRL; /* Pin 4 Control Register */ +- register8_t PIN5CTRL; /* Pin 5 Control Register */ +- register8_t PIN6CTRL; /* Pin 6 Control Register */ +- register8_t PIN7CTRL; /* Pin 7 Control Register */ +-} PORT_t; +- +-/* Virtual Port 0 Mapping */ +-typedef enum PORTCFG_VP0MAP_enum +-{ +- PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP0MAP_t; +- +-/* Virtual Port 1 Mapping */ +-typedef enum PORTCFG_VP1MAP_enum +-{ +- PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP1MAP_t; +- +-/* Virtual Port 2 Mapping */ +-typedef enum PORTCFG_VP2MAP_enum +-{ +- PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP2MAP_t; +- +-/* Virtual Port 3 Mapping */ +-typedef enum PORTCFG_VP3MAP_enum +-{ +- PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP3MAP_t; +- +-/* Clock Output Port */ +-typedef enum PORTCFG_CLKOUT_enum +-{ +- PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ +- PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ +- PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ +- PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +-} PORTCFG_CLKOUT_t; +- +-/* Event Output Port */ +-typedef enum PORTCFG_EVOUT_enum +-{ +- PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ +- PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ +- PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ +- PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +-} PORTCFG_EVOUT_t; +- +-/* Port Interrupt 0 Level */ +-typedef enum PORT_INT0LVL_enum +-{ +- PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ +- PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ +- PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +-} PORT_INT0LVL_t; +- +-/* Port Interrupt 1 Level */ +-typedef enum PORT_INT1LVL_enum +-{ +- PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ +- PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ +- PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +-} PORT_INT1LVL_t; +- +-/* Output/Pull Configuration */ +-typedef enum PORT_OPC_enum +-{ +- PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ +- PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ +- PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ +- PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ +- PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ +- PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ +- PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ +- PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +-} PORT_OPC_t; +- +-/* Input/Sense Configuration */ +-typedef enum PORT_ISC_enum +-{ +- PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ +- PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ +- PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ +- PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ +- PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +-} PORT_ISC_t; +- +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 0 */ +-typedef struct TC0_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- _WORDREGISTER(CCC); /* Compare or Capture C */ +- _WORDREGISTER(CCD); /* Compare or Capture D */ +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +- _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ +- _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +-} TC0_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 1 */ +-typedef struct TC1_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t reserved_0x2E; +- register8_t reserved_0x2F; +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +-} TC1_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* Advanced Waveform Extension */ +-typedef struct AWEX_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t FDEMASK; /* Fault Detection Event Mask */ +- register8_t FDCTRL; /* Fault Detection Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x05; +- register8_t DTBOTH; /* Dead Time Both Sides */ +- register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ +- register8_t DTLS; /* Dead Time Low Side */ +- register8_t DTHS; /* Dead Time High Side */ +- register8_t DTLSBUF; /* Dead Time Low Side Buffer */ +- register8_t DTHSBUF; /* Dead Time High Side Buffer */ +- register8_t OUTOVEN; /* Output Override Enable */ +-} AWEX_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* High-Resolution Extension */ +-typedef struct HIRES_struct +-{ +- register8_t CTRLA; /* Control Register */ +-} HIRES_t; +- +-/* Clock Selection */ +-typedef enum TC_CLKSEL_enum +-{ +- TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ +- TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ +- TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ +- TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ +- TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ +- TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ +- TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ +- TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ +- TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_CLKSEL_t; +- +-/* Waveform Generation Mode */ +-typedef enum TC_WGMODE_enum +-{ +- TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ +- TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ +- TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ +- TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ +- TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ +- TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +-} TC_WGMODE_t; +- +-/* Event Action */ +-typedef enum TC_EVACT_enum +-{ +- TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ +- TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ +- TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ +- TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ +- TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ +- TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ +- TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +-} TC_EVACT_t; +- +-/* Event Selection */ +-typedef enum TC_EVSEL_enum +-{ +- TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_EVSEL_t; +- +-/* Error Interrupt Level */ +-typedef enum TC_ERRINTLVL_enum +-{ +- TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_ERRINTLVL_t; +- +-/* Overflow Interrupt Level */ +-typedef enum TC_OVFINTLVL_enum +-{ +- TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_OVFINTLVL_t; +- +-/* Compare or Capture D Interrupt Level */ +-typedef enum TC_CCDINTLVL_enum +-{ +- TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TC_CCDINTLVL_t; +- +-/* Compare or Capture C Interrupt Level */ +-typedef enum TC_CCCINTLVL_enum +-{ +- TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} TC_CCCINTLVL_t; +- +-/* Compare or Capture B Interrupt Level */ +-typedef enum TC_CCBINTLVL_enum +-{ +- TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_CCBINTLVL_t; +- +-/* Compare or Capture A Interrupt Level */ +-typedef enum TC_CCAINTLVL_enum +-{ +- TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_CCAINTLVL_t; +- +-/* Timer/Counter Command */ +-typedef enum TC_CMD_enum +-{ +- TC_CMD_NONE_gc = (0x00<<2), /* No Command */ +- TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ +- TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ +- TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +-} TC_CMD_t; +- +-/* Fault Detect Action */ +-typedef enum AWEX_FDACT_enum +-{ +- AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ +- AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ +- AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +-} AWEX_FDACT_t; +- +-/* High Resolution Enable */ +-typedef enum HIRES_HREN_enum +-{ +- HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ +- HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ +- HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ +- HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +-} HIRES_HREN_t; +- +- +-/* +--------------------------------------------------------------------------- +-USART - Universal Asynchronous Receiver-Transmitter +--------------------------------------------------------------------------- +-*/ +- +-/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +-typedef struct USART_struct +-{ +- register8_t DATA; /* Data Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x02; +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t BAUDCTRLA; /* Baud Rate Control Register A */ +- register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +-} USART_t; +- +-/* Receive Complete Interrupt level */ +-typedef enum USART_RXCINTLVL_enum +-{ +- USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} USART_RXCINTLVL_t; +- +-/* Transmit Complete Interrupt level */ +-typedef enum USART_TXCINTLVL_enum +-{ +- USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} USART_TXCINTLVL_t; +- +-/* Data Register Empty Interrupt level */ +-typedef enum USART_DREINTLVL_enum +-{ +- USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} USART_DREINTLVL_t; +- +-/* Character Size */ +-typedef enum USART_CHSIZE_enum +-{ +- USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ +- USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ +- USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ +- USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ +- USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +-} USART_CHSIZE_t; +- +-/* Communication Mode */ +-typedef enum USART_CMODE_enum +-{ +- USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ +- USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ +- USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ +- USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +-} USART_CMODE_t; +- +-/* Parity Mode */ +-typedef enum USART_PMODE_enum +-{ +- USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ +- USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ +- USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +-} USART_PMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-SPI - Serial Peripheral Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Serial Peripheral Interface */ +-typedef struct SPI_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t DATA; /* Data Register */ +-} SPI_t; +- +-/* SPI Mode */ +-typedef enum SPI_MODE_enum +-{ +- SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ +- SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ +- SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ +- SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +-} SPI_MODE_t; +- +-/* Prescaler setting */ +-typedef enum SPI_PRESCALER_enum +-{ +- SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ +- SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ +- SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ +- SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +-} SPI_PRESCALER_t; +- +-/* Interrupt level */ +-typedef enum SPI_INTLVL_enum +-{ +- SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} SPI_INTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-IRCOM - IR Communication Module +--------------------------------------------------------------------------- +-*/ +- +-/* IR Communication Module */ +-typedef struct IRCOM_struct +-{ +- register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ +- register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +- register8_t CTRL; /* Control Register */ +-} IRCOM_t; +- +-/* Event channel selection */ +-typedef enum IRDA_EVSEL_enum +-{ +- IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ +- IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ +- IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ +- IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +- IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ +- IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ +- IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ +- IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +-} IRDA_EVSEL_t; +- +- +- +-/* +-========================================================================== +-IO Module Instances. Mapped to memory. +-========================================================================== +-*/ +- +-#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +-#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +-#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +-#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +-#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +-#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +-#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +-#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +-#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +-#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +-#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +-#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +-#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +-#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +-#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +-#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +-#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +-#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +-#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +-#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +-#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +-#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +-#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +-#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +-#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +-#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +-#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +-#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ +-#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +-#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +-#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +-#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +-#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +-#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +-#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +-#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +-#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +-#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +-#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +-#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +-#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ +-#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ +-#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ +-#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ +- +- +-#endif /* !defined (__ASSEMBLER__) */ +- +- +-/* ========== Flattened fully qualified IO register names ========== */ +- +-/* GPIO - General Purpose IO Registers */ +-#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +-#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +-#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +-#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +-#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +-#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +-#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +-#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +-#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +-#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +-#define GPIO_GPIORA _SFR_MEM8(0x000A) +-#define GPIO_GPIORB _SFR_MEM8(0x000B) +-#define GPIO_GPIORC _SFR_MEM8(0x000C) +-#define GPIO_GPIORD _SFR_MEM8(0x000D) +-#define GPIO_GPIORE _SFR_MEM8(0x000E) +-#define GPIO_GPIORF _SFR_MEM8(0x000F) +- +-/* VPORT0 - Virtual Port 0 */ +-#define VPORT0_DIR _SFR_MEM8(0x0010) +-#define VPORT0_OUT _SFR_MEM8(0x0011) +-#define VPORT0_IN _SFR_MEM8(0x0012) +-#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) +- +-/* VPORT1 - Virtual Port 1 */ +-#define VPORT1_DIR _SFR_MEM8(0x0014) +-#define VPORT1_OUT _SFR_MEM8(0x0015) +-#define VPORT1_IN _SFR_MEM8(0x0016) +-#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) +- +-/* VPORT2 - Virtual Port 2 */ +-#define VPORT2_DIR _SFR_MEM8(0x0018) +-#define VPORT2_OUT _SFR_MEM8(0x0019) +-#define VPORT2_IN _SFR_MEM8(0x001A) +-#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) +- +-/* VPORT3 - Virtual Port 3 */ +-#define VPORT3_DIR _SFR_MEM8(0x001C) +-#define VPORT3_OUT _SFR_MEM8(0x001D) +-#define VPORT3_IN _SFR_MEM8(0x001E) +-#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) +- +-/* OCD - On-Chip Debug System */ +-#define OCD_OCDR0 _SFR_MEM8(0x002E) +-#define OCD_OCDR1 _SFR_MEM8(0x002F) +- +-/* CPU - CPU Registers */ +-#define CPU_CCP _SFR_MEM8(0x0034) +-#define CPU_RAMPD _SFR_MEM8(0x0038) +-#define CPU_RAMPX _SFR_MEM8(0x0039) +-#define CPU_RAMPY _SFR_MEM8(0x003A) +-#define CPU_RAMPZ _SFR_MEM8(0x003B) +-#define CPU_EIND _SFR_MEM8(0x003C) +-#define CPU_SPL _SFR_MEM8(0x003D) +-#define CPU_SPH _SFR_MEM8(0x003E) +-#define CPU_SREG _SFR_MEM8(0x003F) +- +-/* CLK - Clock System */ +-#define CLK_CTRL _SFR_MEM8(0x0040) +-#define CLK_PSCTRL _SFR_MEM8(0x0041) +-#define CLK_LOCK _SFR_MEM8(0x0042) +-#define CLK_RTCCTRL _SFR_MEM8(0x0043) +- +-/* SLEEP - Sleep Controller */ +-#define SLEEP_CTRL _SFR_MEM8(0x0048) +- +-/* OSC - Oscillator Control */ +-#define OSC_CTRL _SFR_MEM8(0x0050) +-#define OSC_STATUS _SFR_MEM8(0x0051) +-#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +-#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +-#define OSC_RC32KCAL _SFR_MEM8(0x0054) +-#define OSC_PLLCTRL _SFR_MEM8(0x0055) +-#define OSC_DFLLCTRL _SFR_MEM8(0x0056) +- +-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +-#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +-#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +-#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +-#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +-#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +-#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) +- +-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +-#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +-#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +-#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +-#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +-#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +-#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) +- +-/* PR - Power Reduction */ +-#define PR_PRGEN _SFR_MEM8(0x0070) +-#define PR_PRPA _SFR_MEM8(0x0071) +-#define PR_PRPB _SFR_MEM8(0x0072) +-#define PR_PRPC _SFR_MEM8(0x0073) +-#define PR_PRPD _SFR_MEM8(0x0074) +-#define PR_PRPE _SFR_MEM8(0x0075) +-#define PR_PRPF _SFR_MEM8(0x0076) +- +-/* RST - Reset Controller */ +-#define RST_STATUS _SFR_MEM8(0x0078) +-#define RST_CTRL _SFR_MEM8(0x0079) +- +-/* WDT - Watch-Dog Timer */ +-#define WDT_CTRL _SFR_MEM8(0x0080) +-#define WDT_WINCTRL _SFR_MEM8(0x0081) +-#define WDT_STATUS _SFR_MEM8(0x0082) +- +-/* MCU - MCU Control */ +-#define MCU_DEVID0 _SFR_MEM8(0x0090) +-#define MCU_DEVID1 _SFR_MEM8(0x0091) +-#define MCU_DEVID2 _SFR_MEM8(0x0092) +-#define MCU_REVID _SFR_MEM8(0x0093) +-#define MCU_JTAGUID _SFR_MEM8(0x0094) +-#define MCU_MCUCR _SFR_MEM8(0x0096) +-#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +-#define MCU_AWEXLOCK _SFR_MEM8(0x0099) +- +-/* PMIC - Programmable Interrupt Controller */ +-#define PMIC_STATUS _SFR_MEM8(0x00A0) +-#define PMIC_INTPRI _SFR_MEM8(0x00A1) +-#define PMIC_CTRL _SFR_MEM8(0x00A2) +- +-/* PORTCFG - Port Configuration */ +-#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +-#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +-#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +-#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +- +-/* EVSYS - Event System */ +-#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +-#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +-#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +-#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +-#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +-#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +-#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +-#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +-#define EVSYS_STROBE _SFR_MEM8(0x0190) +-#define EVSYS_DATA _SFR_MEM8(0x0191) +- +-/* NVM - Non Volatile Memory Controller */ +-#define NVM_ADDR0 _SFR_MEM8(0x01C0) +-#define NVM_ADDR1 _SFR_MEM8(0x01C1) +-#define NVM_ADDR2 _SFR_MEM8(0x01C2) +-#define NVM_DATA0 _SFR_MEM8(0x01C4) +-#define NVM_DATA1 _SFR_MEM8(0x01C5) +-#define NVM_DATA2 _SFR_MEM8(0x01C6) +-#define NVM_CMD _SFR_MEM8(0x01CA) +-#define NVM_CTRLA _SFR_MEM8(0x01CB) +-#define NVM_CTRLB _SFR_MEM8(0x01CC) +-#define NVM_INTCTRL _SFR_MEM8(0x01CD) +-#define NVM_STATUS _SFR_MEM8(0x01CF) +-#define NVM_LOCKBITS _SFR_MEM8(0x01D0) +- +-/* ADCA - Analog to Digital Converter A */ +-#define ADCA_CTRLA _SFR_MEM8(0x0200) +-#define ADCA_CTRLB _SFR_MEM8(0x0201) +-#define ADCA_REFCTRL _SFR_MEM8(0x0202) +-#define ADCA_EVCTRL _SFR_MEM8(0x0203) +-#define ADCA_PRESCALER _SFR_MEM8(0x0204) +-#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +-#define ADCA_CAL _SFR_MEM16(0x020C) +-#define ADCA_CH0RES _SFR_MEM16(0x0210) +-#define ADCA_CMP _SFR_MEM16(0x0218) +-#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +-#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +-#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +-#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +-#define ADCA_CH0_RES _SFR_MEM16(0x0224) +- +-/* ACA - Analog Comparator A */ +-#define ACA_AC0CTRL _SFR_MEM8(0x0380) +-#define ACA_AC1CTRL _SFR_MEM8(0x0381) +-#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +-#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +-#define ACA_CTRLA _SFR_MEM8(0x0384) +-#define ACA_CTRLB _SFR_MEM8(0x0385) +-#define ACA_WINCTRL _SFR_MEM8(0x0386) +-#define ACA_STATUS _SFR_MEM8(0x0387) +- +-/* RTC - Real-Time Counter */ +-#define RTC_CTRL _SFR_MEM8(0x0400) +-#define RTC_STATUS _SFR_MEM8(0x0401) +-#define RTC_INTCTRL _SFR_MEM8(0x0402) +-#define RTC_INTFLAGS _SFR_MEM8(0x0403) +-#define RTC_TEMP _SFR_MEM8(0x0404) +-#define RTC_CNT _SFR_MEM16(0x0408) +-#define RTC_PER _SFR_MEM16(0x040A) +-#define RTC_COMP _SFR_MEM16(0x040C) +- +-/* TWIC - Two-Wire Interface C */ +-#define TWIC_CTRL _SFR_MEM8(0x0480) +-#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0482) +-#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0483) +-#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0484) +-#define TWIC_MASTER_STATUS _SFR_MEM8(0x0485) +-#define TWIC_MASTER_BAUD _SFR_MEM8(0x0486) +-#define TWIC_MASTER_ADDR _SFR_MEM8(0x0487) +-#define TWIC_MASTER_DATA _SFR_MEM8(0x0488) +-#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +-#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +-#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +-#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +-#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +-#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) +- +-/* PORTA - Port A */ +-#define PORTA_DIR _SFR_MEM8(0x0600) +-#define PORTA_DIRSET _SFR_MEM8(0x0601) +-#define PORTA_DIRCLR _SFR_MEM8(0x0602) +-#define PORTA_DIRTGL _SFR_MEM8(0x0603) +-#define PORTA_OUT _SFR_MEM8(0x0604) +-#define PORTA_OUTSET _SFR_MEM8(0x0605) +-#define PORTA_OUTCLR _SFR_MEM8(0x0606) +-#define PORTA_OUTTGL _SFR_MEM8(0x0607) +-#define PORTA_IN _SFR_MEM8(0x0608) +-#define PORTA_INTCTRL _SFR_MEM8(0x0609) +-#define PORTA_INT0MASK _SFR_MEM8(0x060A) +-#define PORTA_INT1MASK _SFR_MEM8(0x060B) +-#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +-#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +-#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +-#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +-#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +-#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +-#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +-#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +-#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) +- +-/* PORTB - Port B */ +-#define PORTB_DIR _SFR_MEM8(0x0620) +-#define PORTB_DIRSET _SFR_MEM8(0x0621) +-#define PORTB_DIRCLR _SFR_MEM8(0x0622) +-#define PORTB_DIRTGL _SFR_MEM8(0x0623) +-#define PORTB_OUT _SFR_MEM8(0x0624) +-#define PORTB_OUTSET _SFR_MEM8(0x0625) +-#define PORTB_OUTCLR _SFR_MEM8(0x0626) +-#define PORTB_OUTTGL _SFR_MEM8(0x0627) +-#define PORTB_IN _SFR_MEM8(0x0628) +-#define PORTB_INTCTRL _SFR_MEM8(0x0629) +-#define PORTB_INT0MASK _SFR_MEM8(0x062A) +-#define PORTB_INT1MASK _SFR_MEM8(0x062B) +-#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +-#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +-#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +-#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +-#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +-#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +-#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +-#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +-#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) +- +-/* PORTC - Port C */ +-#define PORTC_DIR _SFR_MEM8(0x0640) +-#define PORTC_DIRSET _SFR_MEM8(0x0641) +-#define PORTC_DIRCLR _SFR_MEM8(0x0642) +-#define PORTC_DIRTGL _SFR_MEM8(0x0643) +-#define PORTC_OUT _SFR_MEM8(0x0644) +-#define PORTC_OUTSET _SFR_MEM8(0x0645) +-#define PORTC_OUTCLR _SFR_MEM8(0x0646) +-#define PORTC_OUTTGL _SFR_MEM8(0x0647) +-#define PORTC_IN _SFR_MEM8(0x0648) +-#define PORTC_INTCTRL _SFR_MEM8(0x0649) +-#define PORTC_INT0MASK _SFR_MEM8(0x064A) +-#define PORTC_INT1MASK _SFR_MEM8(0x064B) +-#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +-#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +-#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +-#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +-#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +-#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +-#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +-#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +-#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) +- +-/* PORTD - Port D */ +-#define PORTD_DIR _SFR_MEM8(0x0660) +-#define PORTD_DIRSET _SFR_MEM8(0x0661) +-#define PORTD_DIRCLR _SFR_MEM8(0x0662) +-#define PORTD_DIRTGL _SFR_MEM8(0x0663) +-#define PORTD_OUT _SFR_MEM8(0x0664) +-#define PORTD_OUTSET _SFR_MEM8(0x0665) +-#define PORTD_OUTCLR _SFR_MEM8(0x0666) +-#define PORTD_OUTTGL _SFR_MEM8(0x0667) +-#define PORTD_IN _SFR_MEM8(0x0668) +-#define PORTD_INTCTRL _SFR_MEM8(0x0669) +-#define PORTD_INT0MASK _SFR_MEM8(0x066A) +-#define PORTD_INT1MASK _SFR_MEM8(0x066B) +-#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +-#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +-#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +-#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +-#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +-#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +-#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +-#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +-#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) +- +-/* PORTE - Port E */ +-#define PORTE_DIR _SFR_MEM8(0x0680) +-#define PORTE_DIRSET _SFR_MEM8(0x0681) +-#define PORTE_DIRCLR _SFR_MEM8(0x0682) +-#define PORTE_DIRTGL _SFR_MEM8(0x0683) +-#define PORTE_OUT _SFR_MEM8(0x0684) +-#define PORTE_OUTSET _SFR_MEM8(0x0685) +-#define PORTE_OUTCLR _SFR_MEM8(0x0686) +-#define PORTE_OUTTGL _SFR_MEM8(0x0687) +-#define PORTE_IN _SFR_MEM8(0x0688) +-#define PORTE_INTCTRL _SFR_MEM8(0x0689) +-#define PORTE_INT0MASK _SFR_MEM8(0x068A) +-#define PORTE_INT1MASK _SFR_MEM8(0x068B) +-#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +-#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +-#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +-#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +-#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +-#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +-#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +-#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +-#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) +- +-/* PORTF - Port F */ +-#define PORTF_DIR _SFR_MEM8(0x06A0) +-#define PORTF_DIRSET _SFR_MEM8(0x06A1) +-#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +-#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +-#define PORTF_OUT _SFR_MEM8(0x06A4) +-#define PORTF_OUTSET _SFR_MEM8(0x06A5) +-#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +-#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +-#define PORTF_IN _SFR_MEM8(0x06A8) +-#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +-#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +-#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +-#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +-#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +-#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +-#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +-#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +-#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +-#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +-#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +-#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) +- +-/* PORTR - Port R */ +-#define PORTR_DIR _SFR_MEM8(0x07E0) +-#define PORTR_DIRSET _SFR_MEM8(0x07E1) +-#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +-#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +-#define PORTR_OUT _SFR_MEM8(0x07E4) +-#define PORTR_OUTSET _SFR_MEM8(0x07E5) +-#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +-#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +-#define PORTR_IN _SFR_MEM8(0x07E8) +-#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +-#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +-#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +-#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +-#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +-#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +-#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +-#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +-#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +-#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +-#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +-#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) +- +-/* TCC0 - Timer/Counter C0 */ +-#define TCC0_CTRLA _SFR_MEM8(0x0800) +-#define TCC0_CTRLB _SFR_MEM8(0x0801) +-#define TCC0_CTRLC _SFR_MEM8(0x0802) +-#define TCC0_CTRLD _SFR_MEM8(0x0803) +-#define TCC0_CTRLE _SFR_MEM8(0x0804) +-#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +-#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +-#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +-#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +-#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +-#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +-#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +-#define TCC0_TEMP _SFR_MEM8(0x080F) +-#define TCC0_CNT _SFR_MEM16(0x0820) +-#define TCC0_PER _SFR_MEM16(0x0826) +-#define TCC0_CCA _SFR_MEM16(0x0828) +-#define TCC0_CCB _SFR_MEM16(0x082A) +-#define TCC0_CCC _SFR_MEM16(0x082C) +-#define TCC0_CCD _SFR_MEM16(0x082E) +-#define TCC0_PERBUF _SFR_MEM16(0x0836) +-#define TCC0_CCABUF _SFR_MEM16(0x0838) +-#define TCC0_CCBBUF _SFR_MEM16(0x083A) +-#define TCC0_CCCBUF _SFR_MEM16(0x083C) +-#define TCC0_CCDBUF _SFR_MEM16(0x083E) +- +-/* TCC1 - Timer/Counter C1 */ +-#define TCC1_CTRLA _SFR_MEM8(0x0840) +-#define TCC1_CTRLB _SFR_MEM8(0x0841) +-#define TCC1_CTRLC _SFR_MEM8(0x0842) +-#define TCC1_CTRLD _SFR_MEM8(0x0843) +-#define TCC1_CTRLE _SFR_MEM8(0x0844) +-#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +-#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +-#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +-#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +-#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +-#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +-#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +-#define TCC1_TEMP _SFR_MEM8(0x084F) +-#define TCC1_CNT _SFR_MEM16(0x0860) +-#define TCC1_PER _SFR_MEM16(0x0866) +-#define TCC1_CCA _SFR_MEM16(0x0868) +-#define TCC1_CCB _SFR_MEM16(0x086A) +-#define TCC1_PERBUF _SFR_MEM16(0x0876) +-#define TCC1_CCABUF _SFR_MEM16(0x0878) +-#define TCC1_CCBBUF _SFR_MEM16(0x087A) +- +-/* AWEXC - Advanced Waveform Extension C */ +-#define AWEXC_CTRL _SFR_MEM8(0x0880) +-#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +-#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +-#define AWEXC_STATUS _SFR_MEM8(0x0884) +-#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +-#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +-#define AWEXC_DTLS _SFR_MEM8(0x0888) +-#define AWEXC_DTHS _SFR_MEM8(0x0889) +-#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +-#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +-#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) +- +-/* HIRESC - High-Resolution Extension C */ +-#define HIRESC_CTRLA _SFR_MEM8(0x0890) +- +-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +-#define USARTC0_DATA _SFR_MEM8(0x08A0) +-#define USARTC0_STATUS _SFR_MEM8(0x08A1) +-#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +-#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +-#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +-#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +-#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) +- +-/* SPIC - Serial Peripheral Interface C */ +-#define SPIC_CTRL _SFR_MEM8(0x08C0) +-#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +-#define SPIC_STATUS _SFR_MEM8(0x08C2) +-#define SPIC_DATA _SFR_MEM8(0x08C3) +- +-/* IRCOM - IR Communication Module */ +-#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F8) +-#define IRCOM_RXPLCTRL _SFR_MEM8(0x08F9) +-#define IRCOM_CTRL _SFR_MEM8(0x08FA) +- +-/* TCD0 - Timer/Counter D0 */ +-#define TCD0_CTRLA _SFR_MEM8(0x0900) +-#define TCD0_CTRLB _SFR_MEM8(0x0901) +-#define TCD0_CTRLC _SFR_MEM8(0x0902) +-#define TCD0_CTRLD _SFR_MEM8(0x0903) +-#define TCD0_CTRLE _SFR_MEM8(0x0904) +-#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +-#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +-#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +-#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +-#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +-#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +-#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +-#define TCD0_TEMP _SFR_MEM8(0x090F) +-#define TCD0_CNT _SFR_MEM16(0x0920) +-#define TCD0_PER _SFR_MEM16(0x0926) +-#define TCD0_CCA _SFR_MEM16(0x0928) +-#define TCD0_CCB _SFR_MEM16(0x092A) +-#define TCD0_CCC _SFR_MEM16(0x092C) +-#define TCD0_CCD _SFR_MEM16(0x092E) +-#define TCD0_PERBUF _SFR_MEM16(0x0936) +-#define TCD0_CCABUF _SFR_MEM16(0x0938) +-#define TCD0_CCBBUF _SFR_MEM16(0x093A) +-#define TCD0_CCCBUF _SFR_MEM16(0x093C) +-#define TCD0_CCDBUF _SFR_MEM16(0x093E) +- +-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +-#define USARTD0_DATA _SFR_MEM8(0x09A0) +-#define USARTD0_STATUS _SFR_MEM8(0x09A1) +-#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +-#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +-#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +-#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +-#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) +- +-/* SPID - Serial Peripheral Interface D */ +-#define SPID_CTRL _SFR_MEM8(0x09C0) +-#define SPID_INTCTRL _SFR_MEM8(0x09C1) +-#define SPID_STATUS _SFR_MEM8(0x09C2) +-#define SPID_DATA _SFR_MEM8(0x09C3) +- +-/* TCE0 - Timer/Counter E0 */ +-#define TCE0_CTRLA _SFR_MEM8(0x0A00) +-#define TCE0_CTRLB _SFR_MEM8(0x0A01) +-#define TCE0_CTRLC _SFR_MEM8(0x0A02) +-#define TCE0_CTRLD _SFR_MEM8(0x0A03) +-#define TCE0_CTRLE _SFR_MEM8(0x0A04) +-#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +-#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +-#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +-#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +-#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +-#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +-#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +-#define TCE0_TEMP _SFR_MEM8(0x0A0F) +-#define TCE0_CNT _SFR_MEM16(0x0A20) +-#define TCE0_PER _SFR_MEM16(0x0A26) +-#define TCE0_CCA _SFR_MEM16(0x0A28) +-#define TCE0_CCB _SFR_MEM16(0x0A2A) +-#define TCE0_CCC _SFR_MEM16(0x0A2C) +-#define TCE0_CCD _SFR_MEM16(0x0A2E) +-#define TCE0_PERBUF _SFR_MEM16(0x0A36) +-#define TCE0_CCABUF _SFR_MEM16(0x0A38) +-#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +-#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +-#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) +- +-/* AWEXE - Advanced Waveform Extension E */ +-#define AWEXE_CTRL _SFR_MEM8(0x0A80) +-#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +-#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +-#define AWEXE_STATUS _SFR_MEM8(0x0A84) +-#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +-#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +-#define AWEXE_DTLS _SFR_MEM8(0x0A88) +-#define AWEXE_DTHS _SFR_MEM8(0x0A89) +-#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +-#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +-#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) +- +-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +-#define USARTE0_DATA _SFR_MEM8(0x0AA0) +-#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +-#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +-#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +-#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +-#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +-#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) +- +-/* SPIE - Serial Peripheral Interface E */ +-#define SPIE_CTRL _SFR_MEM8(0x0AC0) +-#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +-#define SPIE_STATUS _SFR_MEM8(0x0AC2) +-#define SPIE_DATA _SFR_MEM8(0x0AC3) +- +-/* TCF0 - Timer/Counter F0 */ +-#define TCF0_CTRLA _SFR_MEM8(0x0B00) +-#define TCF0_CTRLB _SFR_MEM8(0x0B01) +-#define TCF0_CTRLC _SFR_MEM8(0x0B02) +-#define TCF0_CTRLD _SFR_MEM8(0x0B03) +-#define TCF0_CTRLE _SFR_MEM8(0x0B04) +-#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +-#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +-#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +-#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +-#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +-#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +-#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +-#define TCF0_TEMP _SFR_MEM8(0x0B0F) +-#define TCF0_CNT _SFR_MEM16(0x0B20) +-#define TCF0_PER _SFR_MEM16(0x0B26) +-#define TCF0_CCA _SFR_MEM16(0x0B28) +-#define TCF0_CCB _SFR_MEM16(0x0B2A) +-#define TCF0_CCC _SFR_MEM16(0x0B2C) +-#define TCF0_CCD _SFR_MEM16(0x0B2E) +-#define TCF0_PERBUF _SFR_MEM16(0x0B36) +-#define TCF0_CCABUF _SFR_MEM16(0x0B38) +-#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +-#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +-#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) +- +- +- +-/*================== Bitfield Definitions ================== */ +- +-/* XOCD - On-Chip Debug System */ +-/* OCD.OCDR1 bit masks and bit positions */ +-#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +-#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ +- +- +-/* CPU - CPU */ +-/* CPU.CCP bit masks and bit positions */ +-#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +-#define CPU_CCP_gp 0 /* CCP signature group position. */ +-#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +-#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +-#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +-#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +-#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +-#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +-#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +-#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +-#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +-#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +-#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +-#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +-#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +-#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +-#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +-#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ +- +- +-/* CPU.SREG bit masks and bit positions */ +-#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +-#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ +- +-#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +-#define CPU_T_bp 6 /* Transfer Bit bit position. */ +- +-#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +-#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +- +-#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +-#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +- +-#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +-#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +- +-#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +-#define CPU_N_bp 2 /* Negative Flag bit position. */ +- +-#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +-#define CPU_Z_bp 1 /* Zero Flag bit position. */ +- +-#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +-#define CPU_C_bp 0 /* Carry Flag bit position. */ +- +- +-/* CLK - Clock System */ +-/* CLK.CTRL bit masks and bit positions */ +-#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +-#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +-#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +-#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +-#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +-#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +-#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +-#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ +- +- +-/* CLK.PSCTRL bit masks and bit positions */ +-#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +-#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +-#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +-#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +-#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +-#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +-#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +-#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +-#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +-#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +-#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +-#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ +- +-#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +-#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +-#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +-#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +-#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +-#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ +- +- +-/* CLK.LOCK bit masks and bit positions */ +-#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +-#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ +- +- +-/* CLK.RTCCTRL bit masks and bit positions */ +-#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +-#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +-#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +-#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +-#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +-#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +-#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +-#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ +- +-#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +-#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ +- +- +-/* PR.PRGEN bit masks and bit positions */ +-#define PR_AES_bm 0x10 /* AES bit mask. */ +-#define PR_AES_bp 4 /* AES bit position. */ +- +-#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +-#define PR_EBI_bp 3 /* External Bus Interface bit position. */ +- +-#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +-#define PR_RTC_bp 2 /* Real-time Counter bit position. */ +- +-#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +-#define PR_EVSYS_bp 1 /* Event System bit position. */ +- +-#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +-#define PR_DMA_bp 0 /* DMA-Controller bit position. */ +- +- +-/* PR.PRPA bit masks and bit positions */ +-#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +-#define PR_DAC_bp 2 /* Port A DAC bit position. */ +- +-#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +-#define PR_ADC_bp 1 /* Port A ADC bit position. */ +- +-#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +-#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ +- +- +-/* PR.PRPB bit masks and bit positions */ +-/* PR_DAC_bm Predefined. */ +-/* PR_DAC_bp Predefined. */ +- +-/* PR_ADC_bm Predefined. */ +-/* PR_ADC_bp Predefined. */ +- +-/* PR_AC_bm Predefined. */ +-/* PR_AC_bp Predefined. */ +- +- +-/* PR.PRPC bit masks and bit positions */ +-#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +-#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ +- +-#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +-#define PR_USART1_bp 5 /* Port C USART1 bit position. */ +- +-#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +-#define PR_USART0_bp 4 /* Port C USART0 bit position. */ +- +-#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +-#define PR_SPI_bp 3 /* Port C SPI bit position. */ +- +-#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +-#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ +- +-#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +-#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ +- +-#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +-#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ +- +- +-/* PR.PRPD bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* PR.PRPE bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* PR.PRPF bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* SLEEP - Sleep Controller */ +-/* SLEEP.CTRL bit masks and bit positions */ +-#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +-#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +-#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +-#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +-#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +-#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +-#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +-#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ +- +-#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +-#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ +- +- +-/* OSC - Oscillator */ +-/* OSC.CTRL bit masks and bit positions */ +-#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +-#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ +- +-#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +-#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ +- +-#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ +- +- +-/* OSC.STATUS bit masks and bit positions */ +-#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +-#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ +- +-#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +-#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ +- +-#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ +- +- +-/* OSC.XOSCCTRL bit masks and bit positions */ +-#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +-#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +-#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +-#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +-#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +-#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ +- +-#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +-#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ +- +-#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +-#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +-#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +-#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +-#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +-#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +-#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +-#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +-#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +-#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +- +- +-/* OSC.XOSCFAIL bit masks and bit positions */ +-#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +-#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ +- +-#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +-#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ +- +- +-/* OSC.PLLCTRL bit masks and bit positions */ +-#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +-#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +-#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +-#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +-#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +-#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ +- +-#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +-#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +-#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +-#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +-#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +-#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +-#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +-#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +-#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +-#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +-#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +-#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ +- +- +-/* OSC.DFLLCTRL bit masks and bit positions */ +-#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +-#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ +- +-#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +-#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ +- +- +-/* DFLL - DFLL */ +-/* DFLL.CTRL bit masks and bit positions */ +-#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +-#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ +- +- +-/* DFLL.CALA bit masks and bit positions */ +-#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +-#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +-#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +-#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +-#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +-#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +-#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +-#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +-#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +-#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +-#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +-#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +-#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +-#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +-#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +-#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ +- +- +-/* DFLL.CALB bit masks and bit positions */ +-#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +-#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +-#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +-#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +-#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +-#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +-#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +-#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +-#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +-#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +-#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +-#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +-#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +-#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ +- +- +-/* RST - Reset */ +-/* RST.STATUS bit masks and bit positions */ +-#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +-#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ +- +-#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +-#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ +- +-#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +-#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ +- +-#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +-#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ +- +-#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +-#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ +- +-#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +-#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ +- +-#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +-#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ +- +- +-/* RST.CTRL bit masks and bit positions */ +-#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +-#define RST_SWRST_bp 0 /* Software Reset bit position. */ +- +- +-/* WDT - Watch-Dog Timer */ +-/* WDT.CTRL bit masks and bit positions */ +-#define WDT_PER_gm 0x3C /* Period group mask. */ +-#define WDT_PER_gp 2 /* Period group position. */ +-#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +-#define WDT_PER0_bp 2 /* Period bit 0 position. */ +-#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +-#define WDT_PER1_bp 3 /* Period bit 1 position. */ +-#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +-#define WDT_PER2_bp 4 /* Period bit 2 position. */ +-#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +-#define WDT_PER3_bp 5 /* Period bit 3 position. */ +- +-#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +-#define WDT_ENABLE_bp 1 /* Enable bit position. */ +- +-#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +-#define WDT_CEN_bp 0 /* Change Enable bit position. */ +- +- +-/* WDT.WINCTRL bit masks and bit positions */ +-#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +-#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +-#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +-#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +-#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +-#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +-#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +-#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +-#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +-#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ +- +-#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +-#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ +- +-#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +-#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ +- +- +-/* WDT.STATUS bit masks and bit positions */ +-#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +-#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +- +- +-/* MCU - MCU Control */ +-/* MCU.MCUCR bit masks and bit positions */ +-#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +-#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ +- +- +-/* MCU.EVSYSLOCK bit masks and bit positions */ +-#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +-#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ +- +-#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +-#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ +- +- +-/* MCU.AWEXLOCK bit masks and bit positions */ +-#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +-#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ +- +-#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +-#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ +- +- +-/* PMIC - Programmable Multi-level Interrupt Controller */ +-/* PMIC.STATUS bit masks and bit positions */ +-#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +-#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ +- +-#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +-#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ +- +-#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +-#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ +- +-#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +-#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ +- +- +-/* PMIC.CTRL bit masks and bit positions */ +-#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +-#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ +- +-#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +-#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ +- +-#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +-#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ +- +-#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +-#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ +- +-#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +-#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ +- +- +-/* EVSYS - Event System */ +-/* EVSYS.CH0MUX bit masks and bit positions */ +-#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +-#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +-#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +-#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +-#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +-#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +-#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +-#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +-#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +-#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +-#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +-#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +-#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +-#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +-#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +-#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +-#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +-#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ +- +- +-/* EVSYS.CH1MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH2MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH3MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH0CTRL bit masks and bit positions */ +-#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +-#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +-#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +-#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +-#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +-#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ +- +-#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +-#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ +- +-#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +-#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ +- +-#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +-#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +-#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +-#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +-#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +-#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +-#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +-#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ +- +- +-/* EVSYS.CH1CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH2CTRL bit masks and bit positions */ +-/* EVSYS_QDIRM_gm Predefined. */ +-/* EVSYS_QDIRM_gp Predefined. */ +-/* EVSYS_QDIRM0_bm Predefined. */ +-/* EVSYS_QDIRM0_bp Predefined. */ +-/* EVSYS_QDIRM1_bm Predefined. */ +-/* EVSYS_QDIRM1_bp Predefined. */ +- +-/* EVSYS_QDIEN_bm Predefined. */ +-/* EVSYS_QDIEN_bp Predefined. */ +- +-/* EVSYS_QDEN_bm Predefined. */ +-/* EVSYS_QDEN_bp Predefined. */ +- +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH3CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* NVM - Non Volatile Memory Controller */ +-/* NVM.CMD bit masks and bit positions */ +-#define NVM_CMD_gm 0xFF /* Command group mask. */ +-#define NVM_CMD_gp 0 /* Command group position. */ +-#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +-#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +-#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +-#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +-#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +-#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +-#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +-#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +-#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +-#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +-#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +-#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +-#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +-#define NVM_CMD7_bp 7 /* Command bit 7 position. */ +- +- +-/* NVM.CTRLA bit masks and bit positions */ +-#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +-#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ +- +- +-/* NVM.CTRLB bit masks and bit positions */ +-#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +-#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ +- +-#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +-#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ +- +-#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +-#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ +- +-#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +-#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ +- +- +-/* NVM.INTCTRL bit masks and bit positions */ +-#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +-#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +-#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +-#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +-#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +-#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ +- +-#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +-#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +-#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +-#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +-#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +-#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ +- +- +-/* NVM.STATUS bit masks and bit positions */ +-#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +-#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ +- +-#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +-#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ +- +-#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +-#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ +- +-#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +-#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ +- +- +-/* NVM.LOCKBITS bit masks and bit positions */ +-#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +-#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +-#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ +-#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ +-#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ +-#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ +-#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ +-#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ +-#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ +-#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ +-#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ +-#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ +-#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ +-#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ +-#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ +-#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ +-#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ +-#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ +-#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ +-#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +-#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +-#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +-#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ +- +-#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +-#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +-#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +-#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +-#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ +- +-#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +-#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ +- +-#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +-#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +-#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +-#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +-#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +-#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +-#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +-#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +-#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +-#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +-#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +-#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ +- +-#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +-#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ +- +- +-/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +-#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +-#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +-#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +-#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +-#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +-#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ +- +-#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +-#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ +- +-#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +-#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +-#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +-#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +-#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +-#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +-#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +-#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +- +- +-/* AC - Analog Comparator */ +-/* AC.AC0CTRL bit masks and bit positions */ +-#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +-#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +-#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +-#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +-#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +-#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ +- +-#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +-#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +-#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +-#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +-#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +-#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ +- +-#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +-#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ +- +-#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +-#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +-#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +-#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +-#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +-#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +- +-#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define AC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* AC.AC1CTRL bit masks and bit positions */ +-/* AC_INTMODE_gm Predefined. */ +-/* AC_INTMODE_gp Predefined. */ +-/* AC_INTMODE0_bm Predefined. */ +-/* AC_INTMODE0_bp Predefined. */ +-/* AC_INTMODE1_bm Predefined. */ +-/* AC_INTMODE1_bp Predefined. */ +- +-/* AC_INTLVL_gm Predefined. */ +-/* AC_INTLVL_gp Predefined. */ +-/* AC_INTLVL0_bm Predefined. */ +-/* AC_INTLVL0_bp Predefined. */ +-/* AC_INTLVL1_bm Predefined. */ +-/* AC_INTLVL1_bp Predefined. */ +- +-/* AC_HSMODE_bm Predefined. */ +-/* AC_HSMODE_bp Predefined. */ +- +-/* AC_HYSMODE_gm Predefined. */ +-/* AC_HYSMODE_gp Predefined. */ +-/* AC_HYSMODE0_bm Predefined. */ +-/* AC_HYSMODE0_bp Predefined. */ +-/* AC_HYSMODE1_bm Predefined. */ +-/* AC_HYSMODE1_bp Predefined. */ +- +-/* AC_ENABLE_bm Predefined. */ +-/* AC_ENABLE_bp Predefined. */ +- +- +-/* AC.AC0MUXCTRL bit masks and bit positions */ +-#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +-#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +-#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +-#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +-#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +-#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +-#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +-#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ +- +-#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +-#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +-#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +-#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +-#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +-#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +-#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +-#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ +- +- +-/* AC.AC1MUXCTRL bit masks and bit positions */ +-/* AC_MUXPOS_gm Predefined. */ +-/* AC_MUXPOS_gp Predefined. */ +-/* AC_MUXPOS0_bm Predefined. */ +-/* AC_MUXPOS0_bp Predefined. */ +-/* AC_MUXPOS1_bm Predefined. */ +-/* AC_MUXPOS1_bp Predefined. */ +-/* AC_MUXPOS2_bm Predefined. */ +-/* AC_MUXPOS2_bp Predefined. */ +- +-/* AC_MUXNEG_gm Predefined. */ +-/* AC_MUXNEG_gp Predefined. */ +-/* AC_MUXNEG0_bm Predefined. */ +-/* AC_MUXNEG0_bp Predefined. */ +-/* AC_MUXNEG1_bm Predefined. */ +-/* AC_MUXNEG1_bp Predefined. */ +-/* AC_MUXNEG2_bm Predefined. */ +-/* AC_MUXNEG2_bp Predefined. */ +- +- +-/* AC.CTRLA bit masks and bit positions */ +-#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +-#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ +- +- +-/* AC.CTRLB bit masks and bit positions */ +-#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +-#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +-#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +-#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +-#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +-#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +-#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +-#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +-#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +-#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +-#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +-#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +-#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +-#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ +- +- +-/* AC.WINCTRL bit masks and bit positions */ +-#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +-#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ +- +-#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +-#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +-#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +-#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +-#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +-#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ +- +-#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +-#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +-#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +-#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +-#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +-#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ +- +- +-/* AC.STATUS bit masks and bit positions */ +-#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +-#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +-#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +-#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +-#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +-#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ +- +-#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +-#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ +- +-#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +-#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ +- +-#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +-#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ +- +-#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +-#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ +- +-#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +-#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ +- +- +-/* ADC - Analog/Digital Converter */ +-/* ADC_CH.CTRL bit masks and bit positions */ +-#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +-#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ +- +-#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +-#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +-#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +-#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +-#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +-#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +-#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +-#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ +- +-#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +-#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +-#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +-#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +-#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +-#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ +- +- +-/* ADC_CH.MUXCTRL bit masks and bit positions */ +-#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +-#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +-#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +-#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +-#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +-#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +-#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +-#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +-#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +-#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ +- +-#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +-#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +-#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +-#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +-#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +-#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +-#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +-#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +-#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +-#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ +- +-#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +-#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +-#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +-#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +-#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +-#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ +- +- +-/* ADC_CH.INTCTRL bit masks and bit positions */ +-#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +-#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +-#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +-#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +-#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +-#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ +- +-#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +-#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +-#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +-#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +-#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +-#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ +- +- +-/* ADC_CH.INTFLAGS bit masks and bit positions */ +-#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +-#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ +- +- +-/* ADC.CTRLA bit masks and bit positions */ +-#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +-#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ +- +-#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +-#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ +- +-#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +-#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ +- +- +-/* ADC.CTRLB bit masks and bit positions */ +-#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +-#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ +- +-#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +-#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ +- +-#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +-#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +-#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +-#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +-#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +-#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ +- +- +-/* ADC.REFCTRL bit masks and bit positions */ +-#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +-#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +-#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +-#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +-#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +-#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +- +-#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +-#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ +- +-#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +-#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ +- +- +-/* ADC.EVCTRL bit masks and bit positions */ +-#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +-#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +-#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +-#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +-#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +-#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ +- +-#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +-#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +-#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +-#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +-#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +-#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +-#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +-#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ +- +-#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +-#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +-#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +-#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +-#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +-#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +-#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +-#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ +- +- +-/* ADC.PRESCALER bit masks and bit positions */ +-#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +-#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +-#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +-#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +-#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +-#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +-#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +-#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ +- +- +-/* ADC.INTFLAGS bit masks and bit positions */ +-#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +-#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ +- +- +-/* RTC - Real-Time Clounter */ +-/* RTC.CTRL bit masks and bit positions */ +-#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +-#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +-#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +-#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +-#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +-#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +-#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +-#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ +- +- +-/* RTC.STATUS bit masks and bit positions */ +-#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +-#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ +- +- +-/* RTC.INTCTRL bit masks and bit positions */ +-#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +-#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +-#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +-#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +-#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +-#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ +- +-#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +-#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +-#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +-#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +-#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +-#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ +- +- +-/* RTC.INTFLAGS bit masks and bit positions */ +-#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +-#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ +- +-#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* EBI - External Bus Interface */ +-/* EBI_CS.CTRLA bit masks and bit positions */ +-#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +-#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +-#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +-#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +-#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +-#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +-#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +-#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +-#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +-#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +-#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +-#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ +- +-#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +-#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +-#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +-#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +-#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +-#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ +- +- +-/* EBI_CS.CTRLB bit masks and bit positions */ +-#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +-#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +-#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +-#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +-#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +-#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +-#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +-#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ +- +-#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +-#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ +- +-#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +-#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ +- +-#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +-#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +-#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +-#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +-#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +-#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ +- +- +-/* EBI.CTRL bit masks and bit positions */ +-#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +-#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +-#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +-#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +-#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +-#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ +- +-#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +-#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +-#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +-#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +-#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +-#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ +- +-#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +-#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +-#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +-#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +-#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +-#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ +- +-#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +-#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +-#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +-#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +-#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +-#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLA bit masks and bit positions */ +-#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +-#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ +- +-#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +-#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ +- +-#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +-#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +-#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +-#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +-#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +-#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLB bit masks and bit positions */ +-#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +-#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +-#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +-#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +-#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +-#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ +- +-#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +-#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +-#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +-#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +-#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +-#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +-#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +-#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ +- +-#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +-#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +-#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +-#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +-#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +-#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +-#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +-#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ +- +- +-/* EBI.SDRAMCTRLC bit masks and bit positions */ +-#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +-#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +-#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +-#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +-#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +-#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ +- +-#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +-#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +-#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +-#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +-#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +-#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +-#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +-#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ +- +-#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +-#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +-#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +-#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +-#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +-#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +-#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +-#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ +- +- +-/* TWI - Two-Wire Interface */ +-/* TWI_MASTER.CTRLA bit masks and bit positions */ +-#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +-#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ +- +-#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +-#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ +- +-#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +-#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ +- +- +-/* TWI_MASTER.CTRLB bit masks and bit positions */ +-#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +-#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +-#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +-#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +-#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +-#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +- +-#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +-#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ +- +-#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_MASTER.CTRLC bit masks and bit positions */ +-#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +-#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_MASTER.STATUS bit masks and bit positions */ +-#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +-#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ +- +-#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +-#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ +- +-#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +-#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +- +-#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +-#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +-#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +-#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +-#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +-#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +- +- +-/* TWI_SLAVE.CTRLA bit masks and bit positions */ +-#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +-#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +-#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ +- +-#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +-#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ +- +-#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_SLAVE.CTRLB bit masks and bit positions */ +-#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +-#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_SLAVE.STATUS bit masks and bit positions */ +-#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +-#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +-#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +-#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ +- +-#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +-#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ +- +-#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +-#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ +- +- +-/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +-#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +-#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +-#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +-#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +-#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +-#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +-#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +-#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +-#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +-#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +-#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +-#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +-#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +-#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +-#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +-#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ +- +-#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +-#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ +- +- +-/* TWI.CTRL bit masks and bit positions */ +-#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +-#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ +- +-#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +-#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ +- +- +-/* PORT - Port Configuration */ +-/* PORTCFG.VPCTRLA bit masks and bit positions */ +-#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +-#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +-#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +-#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +-#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +-#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +-#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +-#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +-#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +-#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ +- +-#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +-#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +-#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +-#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +-#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +-#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +-#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +-#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +-#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +-#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ +- +- +-/* PORTCFG.VPCTRLB bit masks and bit positions */ +-#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +-#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +-#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +-#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +-#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +-#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +-#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +-#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +-#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +-#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ +- +-#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +-#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +-#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +-#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +-#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +-#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +-#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +-#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +-#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +-#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ +- +- +-/* PORTCFG.CLKEVOUT bit masks and bit positions */ +-#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +-#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +-#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +-#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +-#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +-#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ +- +-#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +-#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +-#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +-#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +-#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +-#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ +- +- +-/* VPORT.INTFLAGS bit masks and bit positions */ +-#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.INTCTRL bit masks and bit positions */ +-#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +-#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +-#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +-#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +-#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +-#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ +- +-#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +-#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +-#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +-#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +-#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +-#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ +- +- +-/* PORT.INTFLAGS bit masks and bit positions */ +-#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.PIN0CTRL bit masks and bit positions */ +-#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +-#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ +- +-#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +-#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ +- +-#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +-#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +-#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +-#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +-#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +-#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +-#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +-#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ +- +-#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +-#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +-#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +-#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +-#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +-#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +-#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +-#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +- +- +-/* PORT.PIN1CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN2CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN3CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN4CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN5CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN6CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN7CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* TC - 16-bit Timer/Counter With PWM */ +-/* TC0.CTRLA bit masks and bit positions */ +-#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC0.CTRLB bit masks and bit positions */ +-#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +-#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ +- +-#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +-#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ +- +-#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC0.CTRLC bit masks and bit positions */ +-#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +-#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ +- +-#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +-#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ +- +-#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC0.CTRLD bit masks and bit positions */ +-#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC0_EVACT_gp 5 /* Event Action group position. */ +-#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC0.CTRLE bit masks and bit positions */ +-#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC0.INTCTRLA bit masks and bit positions */ +-#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC0.INTCTRLB bit masks and bit positions */ +-#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +-#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +-#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +-#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +-#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +-#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ +- +-#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +-#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +-#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +-#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +-#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +-#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ +- +-#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC0.CTRLFCLR bit masks and bit positions */ +-#define TC0_CMD_gm 0x0C /* Command group mask. */ +-#define TC0_CMD_gp 2 /* Command group position. */ +-#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC0_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC0_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC0_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC0.CTRLFSET bit masks and bit positions */ +-/* TC0_CMD_gm Predefined. */ +-/* TC0_CMD_gp Predefined. */ +-/* TC0_CMD0_bm Predefined. */ +-/* TC0_CMD0_bp Predefined. */ +-/* TC0_CMD1_bm Predefined. */ +-/* TC0_CMD1_bp Predefined. */ +- +-/* TC0_LUPD_bm Predefined. */ +-/* TC0_LUPD_bp Predefined. */ +- +-/* TC0_DIR_bm Predefined. */ +-/* TC0_DIR_bp Predefined. */ +- +- +-/* TC0.CTRLGCLR bit masks and bit positions */ +-#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +-#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ +- +-#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +-#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ +- +-#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC0.CTRLGSET bit masks and bit positions */ +-/* TC0_CCDBV_bm Predefined. */ +-/* TC0_CCDBV_bp Predefined. */ +- +-/* TC0_CCCBV_bm Predefined. */ +-/* TC0_CCCBV_bp Predefined. */ +- +-/* TC0_CCBBV_bm Predefined. */ +-/* TC0_CCBBV_bp Predefined. */ +- +-/* TC0_CCABV_bm Predefined. */ +-/* TC0_CCABV_bp Predefined. */ +- +-/* TC0_PERBV_bm Predefined. */ +-/* TC0_PERBV_bp Predefined. */ +- +- +-/* TC0.INTFLAGS bit masks and bit positions */ +-#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +-#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ +- +-#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +-#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ +- +-#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* TC1.CTRLA bit masks and bit positions */ +-#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC1.CTRLB bit masks and bit positions */ +-#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC1.CTRLC bit masks and bit positions */ +-#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC1.CTRLD bit masks and bit positions */ +-#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC1_EVACT_gp 5 /* Event Action group position. */ +-#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC1.CTRLE bit masks and bit positions */ +-#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC1.INTCTRLA bit masks and bit positions */ +-#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC1.INTCTRLB bit masks and bit positions */ +-#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC1.CTRLFCLR bit masks and bit positions */ +-#define TC1_CMD_gm 0x0C /* Command group mask. */ +-#define TC1_CMD_gp 2 /* Command group position. */ +-#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC1_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC1_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC1_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC1.CTRLFSET bit masks and bit positions */ +-/* TC1_CMD_gm Predefined. */ +-/* TC1_CMD_gp Predefined. */ +-/* TC1_CMD0_bm Predefined. */ +-/* TC1_CMD0_bp Predefined. */ +-/* TC1_CMD1_bm Predefined. */ +-/* TC1_CMD1_bp Predefined. */ +- +-/* TC1_LUPD_bm Predefined. */ +-/* TC1_LUPD_bp Predefined. */ +- +-/* TC1_DIR_bm Predefined. */ +-/* TC1_DIR_bp Predefined. */ +- +- +-/* TC1.CTRLGCLR bit masks and bit positions */ +-#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC1.CTRLGSET bit masks and bit positions */ +-/* TC1_CCBBV_bm Predefined. */ +-/* TC1_CCBBV_bp Predefined. */ +- +-/* TC1_CCABV_bm Predefined. */ +-/* TC1_CCABV_bp Predefined. */ +- +-/* TC1_PERBV_bm Predefined. */ +-/* TC1_PERBV_bp Predefined. */ +- +- +-/* TC1.INTFLAGS bit masks and bit positions */ +-#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* AWEX.CTRL bit masks and bit positions */ +-#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +-#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ +- +-#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +-#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ +- +-#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +-#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ +- +-#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +-#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ +- +-#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +-#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ +- +-#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +-#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ +- +- +-/* AWEX.FDCTRL bit masks and bit positions */ +-#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +-#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ +- +-#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +-#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ +- +-#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +-#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +-#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +-#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +-#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +-#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ +- +- +-/* AWEX.STATUS bit masks and bit positions */ +-#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +-#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ +- +-#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +-#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ +- +-#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +-#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ +- +- +-/* HIRES.CTRLA bit masks and bit positions */ +-#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +-#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +-#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +-#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +-#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +-#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ +- +- +-/* USART - Universal Asynchronous Receiver-Transmitter */ +-/* USART.STATUS bit masks and bit positions */ +-#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +-#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ +- +-#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +-#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +- +-#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +-#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +- +-#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +-#define USART_FERR_bp 4 /* Frame Error bit position. */ +- +-#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +-#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ +- +-#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +-#define USART_PERR_bp 2 /* Parity Error bit position. */ +- +-#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +-#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ +- +- +-/* USART.CTRLA bit masks and bit positions */ +-#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +-#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +-#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +-#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +-#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +-#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ +- +-#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +-#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +-#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +-#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +-#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +-#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ +- +-#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +-#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +-#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +-#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +-#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +-#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ +- +- +-/* USART.CTRLB bit masks and bit positions */ +-#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +-#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ +- +-#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +-#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ +- +-#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +-#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ +- +-#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +-#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ +- +-#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +-#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ +- +- +-/* USART.CTRLC bit masks and bit positions */ +-#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +-#define USART_CMODE_gp 6 /* Communication Mode group position. */ +-#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +-#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +-#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +-#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ +- +-#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +-#define USART_PMODE_gp 4 /* Parity Mode group position. */ +-#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +-#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +-#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +-#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +- +-#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +-#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +- +-#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +-#define USART_CHSIZE_gp 0 /* Character Size group position. */ +-#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +-#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +-#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +-#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +-#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +-#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +- +- +-/* USART.BAUDCTRLA bit masks and bit positions */ +-#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +-#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +-#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +-#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +-#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +-#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +-#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +-#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +-#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +-#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +-#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +-#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +-#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +-#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +-#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +-#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +-#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +-#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ +- +- +-/* USART.BAUDCTRLB bit masks and bit positions */ +-#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +-#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +-#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +-#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +-#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +-#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +-#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +-#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +-#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +-#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ +- +-/* USART_BSEL_gm Predefined. */ +-/* USART_BSEL_gp Predefined. */ +-/* USART_BSEL0_bm Predefined. */ +-/* USART_BSEL0_bp Predefined. */ +-/* USART_BSEL1_bm Predefined. */ +-/* USART_BSEL1_bp Predefined. */ +-/* USART_BSEL2_bm Predefined. */ +-/* USART_BSEL2_bp Predefined. */ +-/* USART_BSEL3_bm Predefined. */ +-/* USART_BSEL3_bp Predefined. */ +- +- +-/* SPI - Serial Peripheral Interface */ +-/* SPI.CTRL bit masks and bit positions */ +-#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +-#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ +- +-#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +-#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ +- +-#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +-#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ +- +-#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +-#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ +- +-#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +-#define SPI_MODE_gp 2 /* SPI Mode group position. */ +-#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +-#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +-#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +-#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ +- +-#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +-#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +-#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +-#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +-#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +-#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ +- +- +-/* SPI.INTCTRL bit masks and bit positions */ +-#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +-#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +-/* SPI.STATUS bit masks and bit positions */ +-#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +-#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ +- +-#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +-#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +- +- +-/* IRCOM - IR Communication Module */ +-/* IRCOM.CTRL bit masks and bit positions */ +-#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +-#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +-#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +-#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +-#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +-#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +-#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +-#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +-#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +-#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ +- +- +- +-// Generic Port Pins +- +-#define PIN0_bm 0x01 +-#define PIN0_bp 0 +-#define PIN1_bm 0x02 +-#define PIN1_bp 1 +-#define PIN2_bm 0x04 +-#define PIN2_bp 2 +-#define PIN3_bm 0x08 +-#define PIN3_bp 3 +-#define PIN4_bm 0x10 +-#define PIN4_bp 4 +-#define PIN5_bm 0x20 +-#define PIN5_bp 5 +-#define PIN6_bm 0x40 +-#define PIN6_bp 6 +-#define PIN7_bm 0x80 +-#define PIN7_bp 7 +- +- +-/* ========== Interrupt Vector Definitions ========== */ +-/* Vector 0 is the reset vector */ +- +-/* OSC interrupt vectors */ +-#define OSC_XOSCF_vect_num 1 +-#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ +- +-/* PORTC interrupt vectors */ +-#define PORTC_INT0_vect_num 2 +-#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +-#define PORTC_INT1_vect_num 3 +-#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ +- +-/* PORTR interrupt vectors */ +-#define PORTR_INT0_vect_num 4 +-#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +-#define PORTR_INT1_vect_num 5 +-#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ +- +-/* RTC interrupt vectors */ +-#define RTC_OVF_vect_num 10 +-#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +-#define RTC_COMP_vect_num 11 +-#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ +- +-/* TWIC interrupt vectors */ +-#define TWIC_TWIS_vect_num 12 +-#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +-#define TWIC_TWIM_vect_num 13 +-#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ +- +-/* TCC0 interrupt vectors */ +-#define TCC0_OVF_vect_num 14 +-#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +-#define TCC0_ERR_vect_num 15 +-#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +-#define TCC0_CCA_vect_num 16 +-#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +-#define TCC0_CCB_vect_num 17 +-#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +-#define TCC0_CCC_vect_num 18 +-#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +-#define TCC0_CCD_vect_num 19 +-#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ +- +-/* TCC1 interrupt vectors */ +-#define TCC1_OVF_vect_num 20 +-#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +-#define TCC1_ERR_vect_num 21 +-#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +-#define TCC1_CCA_vect_num 22 +-#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +-#define TCC1_CCB_vect_num 23 +-#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ +- +-/* SPIC interrupt vectors */ +-#define SPIC_INT_vect_num 24 +-#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ +- +-/* USARTC0 interrupt vectors */ +-#define USARTC0_RXC_vect_num 25 +-#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +-#define USARTC0_DRE_vect_num 26 +-#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +-#define USARTC0_TXC_vect_num 27 +-#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ +- +-/* NVM interrupt vectors */ +-#define NVM_EE_vect_num 32 +-#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +-#define NVM_SPM_vect_num 33 +-#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ +- +-/* PORTB interrupt vectors */ +-#define PORTB_INT0_vect_num 34 +-#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +-#define PORTB_INT1_vect_num 35 +-#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ +- +-/* PORTE interrupt vectors */ +-#define PORTE_INT0_vect_num 43 +-#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +-#define PORTE_INT1_vect_num 44 +-#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ +- +-/* TCE0 interrupt vectors */ +-#define TCE0_OVF_vect_num 47 +-#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +-#define TCE0_ERR_vect_num 48 +-#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +-#define TCE0_CCA_vect_num 49 +-#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +-#define TCE0_CCB_vect_num 50 +-#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +-#define TCE0_CCC_vect_num 51 +-#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +-#define TCE0_CCD_vect_num 52 +-#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ +- +-/* USARTE0 interrupt vectors */ +-#define USARTE0_RXC_vect_num 58 +-#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +-#define USARTE0_DRE_vect_num 59 +-#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +-#define USARTE0_TXC_vect_num 60 +-#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ +- +-/* PORTD interrupt vectors */ +-#define PORTD_INT0_vect_num 64 +-#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +-#define PORTD_INT1_vect_num 65 +-#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ +- +-/* PORTA interrupt vectors */ +-#define PORTA_INT0_vect_num 66 +-#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +-#define PORTA_INT1_vect_num 67 +-#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ +- +-/* ACA interrupt vectors */ +-#define ACA_AC0_vect_num 68 +-#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +-#define ACA_AC1_vect_num 69 +-#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +-#define ACA_ACW_vect_num 70 +-#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ +- +-/* ADCA interrupt vectors */ +-#define ADCA_CH0_vect_num 71 +-#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +- +-/* TCD0 interrupt vectors */ +-#define TCD0_OVF_vect_num 77 +-#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +-#define TCD0_ERR_vect_num 78 +-#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +-#define TCD0_CCA_vect_num 79 +-#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +-#define TCD0_CCB_vect_num 80 +-#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +-#define TCD0_CCC_vect_num 81 +-#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +-#define TCD0_CCD_vect_num 82 +-#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ +- +-/* SPID interrupt vectors */ +-#define SPID_INT_vect_num 87 +-#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ +- +-/* USARTD0 interrupt vectors */ +-#define USARTD0_RXC_vect_num 88 +-#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +-#define USARTD0_DRE_vect_num 89 +-#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +-#define USARTD0_TXC_vect_num 90 +-#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ +- +-/* PORTF interrupt vectors */ +-#define PORTF_INT0_vect_num 104 +-#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +-#define PORTF_INT1_vect_num 105 +-#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ +- +-/* TCF0 interrupt vectors */ +-#define TCF0_OVF_vect_num 108 +-#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ +-#define TCF0_ERR_vect_num 109 +-#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ +-#define TCF0_CCA_vect_num 110 +-#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ +-#define TCF0_CCB_vect_num 111 +-#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ +-#define TCF0_CCC_vect_num 112 +-#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ +-#define TCF0_CCD_vect_num 113 +-#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ +- +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (114 * _VECTOR_SIZE) +- +- +-/* ========== Constants ========== */ +- +-#define PROGMEM_START (0x0000) +-#define PROGMEM_SIZE (139264) +-#define PROGMEM_PAGE_SIZE (512) +-#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) +- +-#define APP_SECTION_START (0x0000) +-#define APP_SECTION_SIZE (131072) +-#define APP_SECTION_PAGE_SIZE (512) +-#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) +- +-#define APPTABLE_SECTION_START (0x1E000) +-#define APPTABLE_SECTION_SIZE (8192) +-#define APPTABLE_SECTION_PAGE_SIZE (512) +-#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) +- +-#define BOOT_SECTION_START (0x20000) +-#define BOOT_SECTION_SIZE (8192) +-#define BOOT_SECTION_PAGE_SIZE (512) +-#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) +- +-#define DATAMEM_START (0x0000) +-#define DATAMEM_SIZE (16384) +-#define DATAMEM_PAGE_SIZE (0) +-#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) +- +-#define IO_START (0x0000) +-#define IO_SIZE (4096) +-#define IO_PAGE_SIZE (0) +-#define IO_END (IO_START + IO_SIZE - 1) +- +-#define MAPPED_EEPROM_START (0x1000) +-#define MAPPED_EEPROM_SIZE (2048) +-#define MAPPED_EEPROM_PAGE_SIZE (0) +-#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) +- +-#define INTERNAL_SRAM_START (0x2000) +-#define INTERNAL_SRAM_SIZE (8192) +-#define INTERNAL_SRAM_PAGE_SIZE (0) +-#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) +- +-#define EEPROM_START (0x0000) +-#define EEPROM_SIZE (2048) +-#define EEPROM_PAGE_SIZE (32) +-#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) +- +-#define FUSE_START (0x0000) +-#define FUSE_SIZE (6) +-#define FUSE_PAGE_SIZE (0) +-#define FUSE_END (FUSE_START + FUSE_SIZE - 1) +- +-#define LOCKBIT_START (0x0000) +-#define LOCKBIT_SIZE (1) +-#define LOCKBIT_PAGE_SIZE (0) +-#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) +- +-#define SIGNATURES_START (0x0000) +-#define SIGNATURES_SIZE (3) +-#define SIGNATURES_PAGE_SIZE (0) +-#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) +- +-#define USER_SIGNATURES_START (0x0000) +-#define USER_SIGNATURES_SIZE (512) +-#define USER_SIGNATURES_PAGE_SIZE (0) +-#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) +- +-#define PROD_SIGNATURES_START (0x0000) +-#define PROD_SIGNATURES_SIZE (52) +-#define PROD_SIGNATURES_PAGE_SIZE (0) +-#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) +- +-#define FLASHEND PROGMEM_END +-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +-#define RAMSTART INTERNAL_SRAM_START +-#define RAMSIZE INTERNAL_SRAM_SIZE +-#define RAMEND INTERNAL_SRAM_END +-#define XRAMSTART EXTERNAL_SRAM_START +-#define XRAMSIZE EXTERNAL_SRAM_SIZE +-#define XRAMEND INTERNAL_SRAM_END +-#define E2END EEPROM_END +-#define E2PAGESIZE EEPROM_PAGE_SIZE +- +- +-/* ========== Fuses ========== */ +-#define FUSE_MEMORY_SIZE 6 +- +-/* Fuse Byte 0 */ +-#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ +-#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ +-#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ +-#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ +-#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ +-#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ +-#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ +-#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ +-#define FUSE0_DEFAULT (0xFF) +- +-/* Fuse Byte 1 */ +-#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +-#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +-#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +-#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +-#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +-#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +-#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +-#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +-#define FUSE1_DEFAULT (0xFF) +- +-/* Fuse Byte 2 */ +-#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +-#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +-#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +-#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +-#define FUSE2_DEFAULT (0xFF) +- +-/* Fuse Byte 3 Reserved */ +- +-/* Fuse Byte 4 */ +-#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +-#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +-#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +-#define FUSE4_DEFAULT (0xFF) +- +-/* Fuse Byte 5 */ +-#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +-#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +-#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +-#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +-#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +-#define FUSE5_DEFAULT (0xFF) +- +- +-/* ========== Lock Bits ========== */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_BITS_EXIST +-#define __BOOT_LOCK_BOOT_BITS_EXIST +- +- +-/* ========== Signature ========== */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x97 +-#define SIGNATURE_2 0x48 +- +- +-#endif /* _AVR_ATxmega128D3_H_ */ +- ++/* Copyright (c) 2009-2010 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iox128d3.h 2194 2010-11-16 15:10:51Z arcanum $ */ ++ ++/* avr/iox128d3.h - definitions for ATxmega128D3 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox128d3.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATxmega128D3_H_ ++#define _AVR_ATxmega128D3_H_ 1 ++ ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++} CLK_t; ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t reserved_0x02; ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ ++} CLK_RTCSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control REgister */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ ++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ ++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ ++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ ++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t reserved_0x07; ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ ++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ ++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ ++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ ++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ ++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ ++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ ++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ ++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ ++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ ++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ ++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ ++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t FUSEBYTE0; /* User ID */ ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ ++ register8_t reserved_0x01; ++ register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ ++ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ ++ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ ++ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++} NVM_PROD_SIGNATURES_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++} NVM_LB_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brown Out Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ ++ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Comparator 0 Control */ ++ register8_t AC1CTRL; /* Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t reserved_0x6; ++ register8_t reserved_0x7; ++} ADC_CH_t; ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++} ADC_t; ++ ++/* Current Limitation */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 225ksps max sampling rate */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 75ksps max sampling rate */ ++} ADC_CURRLIMIT_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++} ADC_REFSEL_t; ++ ++/* Channel sweep selection */ ++typedef enum ADC_SWEEP_enum ++{ ++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ++} ADC_SWEEP_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Clounter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* EBI Chip Select Module */ ++typedef struct EBI_CS_struct ++{ ++ register8_t CTRLA; /* Chip Select Control Register A */ ++ register8_t CTRLB; /* Chip Select Control Register B */ ++ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ ++} EBI_CS_t; ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* External Bus Interface */ ++typedef struct EBI_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ ++ register8_t reserved_0x02; ++ register8_t reserved_0x03; ++ _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ ++ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ ++ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ ++ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ EBI_CS_t CS0; /* Chip Select 0 */ ++ EBI_CS_t CS1; /* Chip Select 1 */ ++ EBI_CS_t CS2; /* Chip Select 2 */ ++ EBI_CS_t CS3; /* Chip Select 3 */ ++} EBI_t; ++ ++/* Chip Select adress space */ ++typedef enum EBI_CS_ASIZE_enum ++{ ++ EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ ++ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ ++ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ ++ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ ++ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ ++ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ ++ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ ++ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ ++ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ ++ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ ++ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ ++ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ ++ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ ++ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ ++ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ ++ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ ++ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ ++} EBI_CS_ASIZE_t; ++ ++/* */ ++typedef enum EBI_CS_SRWS_enum ++{ ++ EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_CS_SRWS_t; ++ ++/* Chip Select address mode */ ++typedef enum EBI_CS_MODE_enum ++{ ++ EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ ++ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ ++ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ ++ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ ++} EBI_CS_MODE_t; ++ ++/* Chip Select SDRAM mode */ ++typedef enum EBI_CS_SDMODE_enum ++{ ++ EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ ++ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ ++} EBI_CS_SDMODE_t; ++ ++/* */ ++typedef enum EBI_SDDATAW_enum ++{ ++ EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ ++ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ ++} EBI_SDDATAW_t; ++ ++/* */ ++typedef enum EBI_LPCMODE_enum ++{ ++ EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ ++ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ ++} EBI_LPCMODE_t; ++ ++/* */ ++typedef enum EBI_SRMODE_enum ++{ ++ EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ ++ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ ++ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ ++ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ ++} EBI_SRMODE_t; ++ ++/* */ ++typedef enum EBI_IFMODE_enum ++{ ++ EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ ++ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ ++ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ ++ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ ++} EBI_IFMODE_t; ++ ++/* */ ++typedef enum EBI_SDCOL_enum ++{ ++ EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ ++ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ ++ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ ++ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ ++} EBI_SDCOL_t; ++ ++/* */ ++typedef enum EBI_MRDLY_enum ++{ ++ EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_MRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCYCDLY_enum ++{ ++ EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ROWCYCDLY_t; ++ ++/* */ ++typedef enum EBI_RPDLY_enum ++{ ++ EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_RPDLY_t; ++ ++/* */ ++typedef enum EBI_WRDLY_enum ++{ ++ EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_WRDLY_t; ++ ++/* */ ++typedef enum EBI_ESRDLY_enum ++{ ++ EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ESRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCOLDLY_enum ++{ ++ EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_ROWCOLDLY_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++} PORTCFG_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Virtual Port 0 Mapping */ ++typedef enum PORTCFG_VP0MAP_enum ++{ ++ PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP0MAP_t; ++ ++/* Virtual Port 1 Mapping */ ++typedef enum PORTCFG_VP1MAP_enum ++{ ++ PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP1MAP_t; ++ ++/* Virtual Port 2 Mapping */ ++typedef enum PORTCFG_VP2MAP_enum ++{ ++ PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP2MAP_t; ++ ++/* Virtual Port 3 Mapping */ ++typedef enum PORTCFG_VP3MAP_enum ++{ ++ PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP3MAP_t; ++ ++/* Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x05; ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++ register8_t CTRL; /* Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset Controller */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ ++#define PORTA (*(PORT_t *) 0x0600) /* Port A */ ++#define PORTB (*(PORT_t *) 0x0620) /* Port B */ ++#define PORTC (*(PORT_t *) 0x0640) /* Port C */ ++#define PORTD (*(PORT_t *) 0x0660) /* Port D */ ++#define PORTE (*(PORT_t *) 0x0680) /* Port E */ ++#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ ++#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ ++#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ ++#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ ++#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ ++#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++#define GPIO_GPIOR4 _SFR_MEM8(0x0004) ++#define GPIO_GPIOR5 _SFR_MEM8(0x0005) ++#define GPIO_GPIOR6 _SFR_MEM8(0x0006) ++#define GPIO_GPIOR7 _SFR_MEM8(0x0007) ++#define GPIO_GPIOR8 _SFR_MEM8(0x0008) ++#define GPIO_GPIOR9 _SFR_MEM8(0x0009) ++#define GPIO_GPIORA _SFR_MEM8(0x000A) ++#define GPIO_GPIORB _SFR_MEM8(0x000B) ++#define GPIO_GPIORC _SFR_MEM8(0x000C) ++#define GPIO_GPIORD _SFR_MEM8(0x000D) ++#define GPIO_GPIORE _SFR_MEM8(0x000E) ++#define GPIO_GPIORF _SFR_MEM8(0x000F) ++ ++/* VPORT0 - Virtual Port 0 */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT1 - Virtual Port 1 */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT2 - Virtual Port 2 */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT3 - Virtual Port 3 */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU Registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator Control */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset Controller */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - Port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non Volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADCA - Analog to Digital Converter A */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++ ++/* ACA - Analog Comparator A */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWIC - Two-Wire Interface C */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0483) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0484) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0485) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0486) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0487) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWIE - Two-Wire Interface E */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* PORTA - Port A */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORTB - Port B */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORTC - Port C */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORTD - Port D */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORTE - Port E */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORTF - Port F */ ++#define PORTF_DIR _SFR_MEM8(0x06A0) ++#define PORTF_DIRSET _SFR_MEM8(0x06A1) ++#define PORTF_DIRCLR _SFR_MEM8(0x06A2) ++#define PORTF_DIRTGL _SFR_MEM8(0x06A3) ++#define PORTF_OUT _SFR_MEM8(0x06A4) ++#define PORTF_OUTSET _SFR_MEM8(0x06A5) ++#define PORTF_OUTCLR _SFR_MEM8(0x06A6) ++#define PORTF_OUTTGL _SFR_MEM8(0x06A7) ++#define PORTF_IN _SFR_MEM8(0x06A8) ++#define PORTF_INTCTRL _SFR_MEM8(0x06A9) ++#define PORTF_INT0MASK _SFR_MEM8(0x06AA) ++#define PORTF_INT1MASK _SFR_MEM8(0x06AB) ++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) ++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) ++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) ++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) ++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) ++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) ++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) ++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) ++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) ++ ++/* PORTR - Port R */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TCC0 - Timer/Counter C0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TCC1 - Timer/Counter C1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEXC - Advanced Waveform Extension C */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRESC - High-Resolution Extension C */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* SPIC - Serial Peripheral Interface C */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F8) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_CTRL _SFR_MEM8(0x08FA) ++ ++/* TCD0 - Timer/Counter D0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* SPID - Serial Peripheral Interface D */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TCE0 - Timer/Counter E0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* AWEXE - Advanced Waveform Extension E */ ++#define AWEXE_CTRL _SFR_MEM8(0x0A80) ++#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) ++#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) ++#define AWEXE_STATUS _SFR_MEM8(0x0A84) ++#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) ++#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) ++#define AWEXE_DTLS _SFR_MEM8(0x0A88) ++#define AWEXE_DTHS _SFR_MEM8(0x0A89) ++#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) ++#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) ++#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) ++ ++/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* SPIE - Serial Peripheral Interface E */ ++#define SPIE_CTRL _SFR_MEM8(0x0AC0) ++#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) ++#define SPIE_STATUS _SFR_MEM8(0x0AC2) ++#define SPIE_DATA _SFR_MEM8(0x0AC3) ++ ++/* TCF0 - Timer/Counter F0 */ ++#define TCF0_CTRLA _SFR_MEM8(0x0B00) ++#define TCF0_CTRLB _SFR_MEM8(0x0B01) ++#define TCF0_CTRLC _SFR_MEM8(0x0B02) ++#define TCF0_CTRLD _SFR_MEM8(0x0B03) ++#define TCF0_CTRLE _SFR_MEM8(0x0B04) ++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) ++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) ++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) ++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) ++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF0_TEMP _SFR_MEM8(0x0B0F) ++#define TCF0_CNT _SFR_MEM16(0x0B20) ++#define TCF0_PER _SFR_MEM16(0x0B26) ++#define TCF0_CCA _SFR_MEM16(0x0B28) ++#define TCF0_CCB _SFR_MEM16(0x0B2A) ++#define TCF0_CCC _SFR_MEM16(0x0B2C) ++#define TCF0_CCD _SFR_MEM16(0x0B2E) ++#define TCF0_PERBUF _SFR_MEM16(0x0B36) ++#define TCF0_CCABUF _SFR_MEM16(0x0B38) ++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) ++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) ++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR1 bit masks and bit positions */ ++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ ++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ ++ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ ++ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ ++#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ ++ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ ++ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ ++ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ ++#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ ++ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ ++ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ ++ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ ++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ ++ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM_gm Predefined. */ ++/* EVSYS_QDIRM_gp Predefined. */ ++/* EVSYS_QDIRM0_bm Predefined. */ ++/* EVSYS_QDIRM0_bp Predefined. */ ++/* EVSYS_QDIRM1_bm Predefined. */ ++/* EVSYS_QDIRM1_bp Predefined. */ ++ ++/* EVSYS_QDIEN_bm Predefined. */ ++/* EVSYS_QDIEN_bp Predefined. */ ++ ++/* EVSYS_QDEN_bm Predefined. */ ++/* EVSYS_QDEN_bp Predefined. */ ++ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0xFF /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ ++#define NVM_CMD7_bp 7 /* Command bit 7 position. */ ++ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ ++#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ ++#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ ++#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ ++#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ ++#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ ++#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ ++#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ ++#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ ++#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ ++#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ ++#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ ++#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ ++#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ ++#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ ++#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ ++#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ ++#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ ++#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ ++#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ ++ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ ++ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ ++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE_gm Predefined. */ ++/* AC_INTMODE_gp Predefined. */ ++/* AC_INTMODE0_bm Predefined. */ ++/* AC_INTMODE0_bp Predefined. */ ++/* AC_INTMODE1_bm Predefined. */ ++/* AC_INTMODE1_bp Predefined. */ ++ ++/* AC_INTLVL_gm Predefined. */ ++/* AC_INTLVL_gp Predefined. */ ++/* AC_INTLVL0_bm Predefined. */ ++/* AC_INTLVL0_bp Predefined. */ ++/* AC_INTLVL1_bm Predefined. */ ++/* AC_INTLVL1_bp Predefined. */ ++ ++/* AC_HSMODE_bm Predefined. */ ++/* AC_HSMODE_bp Predefined. */ ++ ++/* AC_HYSMODE_gm Predefined. */ ++/* AC_HYSMODE_gp Predefined. */ ++/* AC_HYSMODE0_bm Predefined. */ ++/* AC_HYSMODE0_bp Predefined. */ ++/* AC_HYSMODE1_bm Predefined. */ ++/* AC_HYSMODE1_bp Predefined. */ ++ ++/* AC_ENABLE_bm Predefined. */ ++/* AC_ENABLE_bp Predefined. */ ++ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS_gm Predefined. */ ++/* AC_MUXPOS_gp Predefined. */ ++/* AC_MUXPOS0_bm Predefined. */ ++/* AC_MUXPOS0_bp Predefined. */ ++/* AC_MUXPOS1_bm Predefined. */ ++/* AC_MUXPOS1_bp Predefined. */ ++/* AC_MUXPOS2_bm Predefined. */ ++/* AC_MUXPOS2_bp Predefined. */ ++ ++/* AC_MUXNEG_gm Predefined. */ ++/* AC_MUXNEG_gp Predefined. */ ++/* AC_MUXNEG0_bm Predefined. */ ++/* AC_MUXNEG0_bp Predefined. */ ++/* AC_MUXNEG1_bm Predefined. */ ++/* AC_MUXNEG1_bp Predefined. */ ++/* AC_MUXNEG2_bm Predefined. */ ++/* AC_MUXNEG2_bp Predefined. */ ++ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ ++ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ ++ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ ++ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ ++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ ++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ ++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ ++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ ++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ ++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ ++ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++ ++/* RTC - Real-Time Clounter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* EBI - External Bus Interface */ ++/* EBI_CS.CTRLA bit masks and bit positions */ ++#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ ++#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ ++#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ ++#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ ++#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ ++#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ ++#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ ++#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ ++#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ ++#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ ++#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ ++#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ ++ ++#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ ++#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ ++#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ ++#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ ++#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ ++#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ ++ ++ ++/* EBI_CS.CTRLB bit masks and bit positions */ ++#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ ++#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ ++#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ ++#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ ++#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ ++#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ ++#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ ++#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ ++ ++#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ ++#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ ++ ++#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ ++#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ ++ ++#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ ++#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ ++#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ ++#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ ++#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ ++#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ ++ ++ ++/* EBI.CTRL bit masks and bit positions */ ++#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ ++#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ ++#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ ++#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ ++#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ ++#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ ++ ++#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ ++#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ ++#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ ++#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ ++#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ ++#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ ++ ++#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ ++#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ ++#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ ++#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ ++#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ ++#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ ++ ++#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ ++#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ ++#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ ++#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ ++#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ ++#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLA bit masks and bit positions */ ++#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ ++#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ ++ ++#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ ++#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ ++ ++#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ ++#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ ++#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ ++#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ ++#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ ++#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLB bit masks and bit positions */ ++#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ ++#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ ++#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ ++#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ ++#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ ++#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ ++ ++#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ ++#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ ++#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ ++#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ ++#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ ++#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ ++#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ ++#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ ++ ++#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ ++#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ ++#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ ++#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ ++#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ ++#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ ++#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ ++#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ ++ ++ ++/* EBI.SDRAMCTRLC bit masks and bit positions */ ++#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ ++#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ ++#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ ++#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ ++#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ ++#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ ++ ++#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ ++#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ ++#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ ++#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ ++#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ ++#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ ++#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ ++#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ ++ ++#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ ++#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ ++#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ ++#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ ++#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ ++#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ ++#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ ++#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ ++ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ ++#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++ ++/* PORT - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD_gm Predefined. */ ++/* TC0_CMD_gp Predefined. */ ++/* TC0_CMD0_bm Predefined. */ ++/* TC0_CMD0_bp Predefined. */ ++/* TC0_CMD1_bm Predefined. */ ++/* TC0_CMD1_bp Predefined. */ ++ ++/* TC0_LUPD_bm Predefined. */ ++/* TC0_LUPD_bp Predefined. */ ++ ++/* TC0_DIR_bm Predefined. */ ++/* TC0_DIR_bp Predefined. */ ++ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV_bm Predefined. */ ++/* TC0_CCDBV_bp Predefined. */ ++ ++/* TC0_CCCBV_bm Predefined. */ ++/* TC0_CCCBV_bp Predefined. */ ++ ++/* TC0_CCBBV_bm Predefined. */ ++/* TC0_CCBBV_bp Predefined. */ ++ ++/* TC0_CCABV_bm Predefined. */ ++/* TC0_CCABV_bp Predefined. */ ++ ++/* TC0_PERBV_bm Predefined. */ ++/* TC0_PERBV_bp Predefined. */ ++ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD_gm Predefined. */ ++/* TC1_CMD_gp Predefined. */ ++/* TC1_CMD0_bm Predefined. */ ++/* TC1_CMD0_bp Predefined. */ ++/* TC1_CMD1_bm Predefined. */ ++/* TC1_CMD1_bp Predefined. */ ++ ++/* TC1_LUPD_bm Predefined. */ ++/* TC1_LUPD_bp Predefined. */ ++ ++/* TC1_DIR_bm Predefined. */ ++/* TC1_DIR_bp Predefined. */ ++ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV_bm Predefined. */ ++/* TC1_CCBBV_bp Predefined. */ ++ ++/* TC1_CCABV_bm Predefined. */ ++/* TC1_CCABV_bp Predefined. */ ++ ++/* TC1_PERBV_bm Predefined. */ ++/* TC1_PERBV_bp Predefined. */ ++ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL_gm Predefined. */ ++/* USART_BSEL_gp Predefined. */ ++/* USART_BSEL0_bm Predefined. */ ++/* USART_BSEL0_bp Predefined. */ ++/* USART_BSEL1_bm Predefined. */ ++/* USART_BSEL1_bp Predefined. */ ++/* USART_BSEL2_bm Predefined. */ ++/* USART_BSEL2_bp Predefined. */ ++/* USART_BSEL3_bm Predefined. */ ++/* USART_BSEL3_bp Predefined. */ ++ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_XOSCF_vect_num 1 ++#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* PORTF interrupt vectors */ ++#define PORTF_INT0_vect_num 104 ++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ ++#define PORTF_INT1_vect_num 105 ++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_OVF_vect_num 108 ++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ ++#define TCF0_ERR_vect_num 109 ++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ ++#define TCF0_CCA_vect_num 110 ++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ ++#define TCF0_CCB_vect_num 111 ++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ ++#define TCF0_CCC_vect_num 112 ++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ ++#define TCF0_CCD_vect_num 113 ++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ ++ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (114 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (139264) ++#define PROGMEM_PAGE_SIZE (512) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (131072) ++#define APP_SECTION_PAGE_SIZE (512) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x1E000) ++#define APPTABLE_SECTION_SIZE (8192) ++#define APPTABLE_SECTION_PAGE_SIZE (512) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x20000) ++#define BOOT_SECTION_SIZE (8192) ++#define BOOT_SECTION_PAGE_SIZE (512) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (16384) ++#define DATAMEM_PAGE_SIZE (0) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (2048) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (8192) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (2048) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define FUSE_START (0x0000) ++#define FUSE_SIZE (6) ++#define FUSE_PAGE_SIZE (0) ++#define FUSE_END (FUSE_START + FUSE_SIZE - 1) ++ ++#define LOCKBIT_START (0x0000) ++#define LOCKBIT_SIZE (1) ++#define LOCKBIT_PAGE_SIZE (0) ++#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (512) ++#define USER_SIGNATURES_PAGE_SIZE (0) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (0) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE PROGMEM_PAGE_SIZE ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define XRAMSTART EXTERNAL_SRAM_START ++#define XRAMSIZE EXTERNAL_SRAM_SIZE ++#define XRAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 */ ++#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ ++#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ ++#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ ++#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ ++#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ ++#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ ++#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ ++#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ ++#define FUSE0_DEFAULT (0xFF) ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x97 ++#define SIGNATURE_2 0x48 ++ ++ ++#endif /* _AVR_ATxmega128D3_H_ */ ++ +diff --git a/include/avr/iox128d4.h b/include/avr/iox128d4.h +new file mode 100644 +index 0000000..e298db2 +--- /dev/null ++++ b/include/avr/iox128d4.h +@@ -0,0 +1,5511 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox128d4.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA128D4_H_INCLUDED ++#define _AVR_ATXMEGA128D4_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t reserved_0x04; ++} CLK_t; ++ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t reserved_0x02; ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from 32.768 kHz internal oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from 32.768 kHz internal oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 2 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC2MCREF_enum ++{ ++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC2MCREF_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++ register8_t reserved_0x05; ++ register8_t EVOUTSEL; /* Event Output Select */ ++} PORTCFG_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP02MAP_enum ++{ ++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP02MAP_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP13MAP_enum ++{ ++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP13MAP_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t reserved_0x07; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++} ADC_t; ++ ++/* Current Limitation */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ ++} ADC_CURRLIMIT_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ ++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ ++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ ++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* SDA Hold Time */ ++typedef enum TWI_SDAHOLD_enum ++{ ++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ ++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ ++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ ++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ ++} TWI_SDAHOLD_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - I/O Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* I/O Port Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Byte Mode */ ++typedef enum TC_BYTEM_enum ++{ ++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ ++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ ++} TC_BYTEM_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC2 - 16-bit Timer/Counter type 2 ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter type 2 */ ++typedef struct TC2_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t reserved_0x03; ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t reserved_0x08; ++ register8_t CTRLF; /* Control Register F */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t LCNT; /* Low Byte Count */ ++ register8_t HCNT; /* High Byte Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t LPER; /* Low Byte Period */ ++ register8_t HPER; /* High Byte Period */ ++ register8_t LCMPA; /* Low Byte Compare A */ ++ register8_t HCMPA; /* High Byte Compare A */ ++ register8_t LCMPB; /* Low Byte Compare B */ ++ register8_t HCMPB; /* High Byte Compare B */ ++ register8_t LCMPC; /* Low Byte Compare C */ ++ register8_t HCMPC; /* High Byte Compare C */ ++ register8_t LCMPD; /* Low Byte Compare D */ ++ register8_t HCMPD; /* High Byte Compare D */ ++} TC2_t; ++ ++/* Clock Selection */ ++typedef enum TC2_CLKSEL_enum ++{ ++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC2_CLKSEL_t; ++ ++/* Byte Mode */ ++typedef enum TC2_BYTEM_enum ++{ ++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ ++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ ++} TC2_BYTEM_t; ++ ++/* High Byte Underflow Interrupt Level */ ++typedef enum TC2_HUNFINTLVL_enum ++{ ++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_HUNFINTLVL_t; ++ ++/* Low Byte Underflow Interrupt Level */ ++typedef enum TC2_LUNFINTLVL_enum ++{ ++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LUNFINTLVL_t; ++ ++/* Low Byte Compare D Interrupt Level */ ++typedef enum TC2_LCMPDINTLVL_enum ++{ ++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC2_LCMPDINTLVL_t; ++ ++/* Low Byte Compare C Interrupt Level */ ++typedef enum TC2_LCMPCINTLVL_enum ++{ ++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC2_LCMPCINTLVL_t; ++ ++/* Low Byte Compare B Interrupt Level */ ++typedef enum TC2_LCMPBINTLVL_enum ++{ ++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_LCMPBINTLVL_t; ++ ++/* Low Byte Compare A Interrupt Level */ ++typedef enum TC2_LCMPAINTLVL_enum ++{ ++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LCMPAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMD_enum ++{ ++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC2_CMD_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMDEN_enum ++{ ++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ ++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ ++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ ++} TC2_CMDEN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AWEX - Timer/Counter Advanced Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - Timer/Counter High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t reserved_0x00; ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* Timer Oscillator pin location */ ++typedef enum TOSCSEL_enum ++{ ++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ ++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ ++} TOSCSEL_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* BOD operation */ ++typedef enum BODACT_enum ++{ ++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BODACT_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WDP_enum ++{ ++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ ++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ ++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ ++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ ++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ ++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ ++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ ++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ ++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ ++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ ++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ ++} WDP_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LOCKBIT - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ ++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ ++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ ++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLL - DFLL */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_REMAP _SFR_MEM8(0x060E) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_REMAP _SFR_MEM8(0x062E) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_REMAP _SFR_MEM8(0x068E) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCC2_CTRLA _SFR_MEM8(0x0800) ++#define TCC2_CTRLB _SFR_MEM8(0x0801) ++#define TCC2_CTRLC _SFR_MEM8(0x0802) ++#define TCC2_CTRLE _SFR_MEM8(0x0804) ++#define TCC2_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC2_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC2_CTRLF _SFR_MEM8(0x0809) ++#define TCC2_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC2_LCNT _SFR_MEM8(0x0820) ++#define TCC2_HCNT _SFR_MEM8(0x0821) ++#define TCC2_LPER _SFR_MEM8(0x0826) ++#define TCC2_HPER _SFR_MEM8(0x0827) ++#define TCC2_LCMPA _SFR_MEM8(0x0828) ++#define TCC2_HCMPA _SFR_MEM8(0x0829) ++#define TCC2_LCMPB _SFR_MEM8(0x082A) ++#define TCC2_HCMPB _SFR_MEM8(0x082B) ++#define TCC2_LCMPC _SFR_MEM8(0x082C) ++#define TCC2_HCMPC _SFR_MEM8(0x082D) ++#define TCC2_LCMPD _SFR_MEM8(0x082E) ++#define TCC2_HCMPD _SFR_MEM8(0x082F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_STATUSSET _SFR_MEM8(0x0885) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCD2_CTRLA _SFR_MEM8(0x0900) ++#define TCD2_CTRLB _SFR_MEM8(0x0901) ++#define TCD2_CTRLC _SFR_MEM8(0x0902) ++#define TCD2_CTRLE _SFR_MEM8(0x0904) ++#define TCD2_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD2_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD2_CTRLF _SFR_MEM8(0x0909) ++#define TCD2_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD2_LCNT _SFR_MEM8(0x0920) ++#define TCD2_HCNT _SFR_MEM8(0x0921) ++#define TCD2_LPER _SFR_MEM8(0x0926) ++#define TCD2_HPER _SFR_MEM8(0x0927) ++#define TCD2_LCMPA _SFR_MEM8(0x0928) ++#define TCD2_HCMPA _SFR_MEM8(0x0929) ++#define TCD2_LCMPB _SFR_MEM8(0x092A) ++#define TCD2_HCMPB _SFR_MEM8(0x092B) ++#define TCD2_LCMPC _SFR_MEM8(0x092C) ++#define TCD2_HCMPC _SFR_MEM8(0x092D) ++#define TCD2_LCMPD _SFR_MEM8(0x092E) ++#define TCD2_HCMPD _SFR_MEM8(0x092F) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ ++#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ ++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ ++ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ ++ ++/* PORTCFG.EVOUTSEL bit masks and bit positions */ ++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ ++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ ++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ ++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ ++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ ++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ ++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ ++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ ++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ ++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ ++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ ++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ ++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ ++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ ++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ ++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ ++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ ++ ++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ ++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ ++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ ++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ ++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ ++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ ++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ ++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ ++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ ++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ ++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* RTC - Real-Time Counter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* PORT - I/O Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_SPI_bm 0x20 /* SPI bit mask. */ ++#define PORT_SPI_bp 5 /* SPI bit position. */ ++ ++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ ++#define PORT_USART0_bp 4 /* USART0 bit position. */ ++ ++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ ++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ ++ ++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ ++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ ++ ++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ ++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ ++ ++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ ++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD Predefined. */ ++/* TC0_CMD Predefined. */ ++ ++/* TC0_LUPD Predefined. */ ++/* TC0_LUPD Predefined. */ ++ ++/* TC0_DIR Predefined. */ ++/* TC0_DIR Predefined. */ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV Predefined. */ ++/* TC0_CCDBV Predefined. */ ++ ++/* TC0_CCCBV Predefined. */ ++/* TC0_CCCBV Predefined. */ ++ ++/* TC0_CCBBV Predefined. */ ++/* TC0_CCBBV Predefined. */ ++ ++/* TC0_CCABV Predefined. */ ++/* TC0_CCABV Predefined. */ ++ ++/* TC0_PERBV Predefined. */ ++/* TC0_PERBV Predefined. */ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD Predefined. */ ++/* TC1_CMD Predefined. */ ++ ++/* TC1_LUPD Predefined. */ ++/* TC1_LUPD Predefined. */ ++ ++/* TC1_DIR Predefined. */ ++/* TC1_DIR Predefined. */ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV Predefined. */ ++/* TC1_CCBBV Predefined. */ ++ ++/* TC1_CCABV Predefined. */ ++/* TC1_CCABV Predefined. */ ++ ++/* TC1_PERBV Predefined. */ ++/* TC1_PERBV Predefined. */ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++/* TC2.CTRLA bit masks and bit positions */ ++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC2.CTRLB bit masks and bit positions */ ++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ ++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ ++ ++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ ++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ ++ ++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ ++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ ++ ++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ ++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ ++ ++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ ++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ ++ ++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ ++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ ++ ++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ ++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ ++ ++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ ++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ ++ ++/* TC2.CTRLC bit masks and bit positions */ ++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ ++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ ++ ++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ ++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ ++ ++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ ++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ ++ ++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ ++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ ++ ++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ ++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ ++ ++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ ++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ ++ ++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ ++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ ++ ++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ ++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ ++ ++/* TC2.CTRLE bit masks and bit positions */ ++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC2.INTCTRLA bit masks and bit positions */ ++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ ++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ ++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ ++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ ++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ ++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ ++ ++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ ++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ ++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ ++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ ++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ ++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ ++ ++/* TC2.INTCTRLB bit masks and bit positions */ ++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ ++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ ++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ ++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ ++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ ++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ ++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ ++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ ++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ ++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ ++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ ++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ ++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ ++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ ++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ ++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ ++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ ++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ ++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ ++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ ++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ ++ ++/* TC2.CTRLF bit masks and bit positions */ ++#define TC2_CMD_gm 0x0C /* Command group mask. */ ++#define TC2_CMD_gp 2 /* Command group position. */ ++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC2_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC2_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ ++#define TC2_CMDEN_gp 0 /* Command Enable group position. */ ++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ ++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ ++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ ++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ ++ ++/* TC2.INTFLAGS bit masks and bit positions */ ++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ ++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ ++ ++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ ++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ ++ ++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ ++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ ++ ++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ ++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ ++ ++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ ++ ++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ ++ ++/* AWEX - Timer/Counter Advanced Waveform Extension */ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++/* AWEX.STATUSSET bit masks and bit positions */ ++/* AWEX_FDF Predefined. */ ++/* AWEX_FDF Predefined. */ ++ ++/* AWEX_DTHSBUFV Predefined. */ ++/* AWEX_DTHSBUFV Predefined. */ ++ ++/* AWEX_DTLSBUFV Predefined. */ ++/* AWEX_DTLSBUFV Predefined. */ ++ ++/* HIRES - Timer/Counter High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ ++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* LOCKBIT - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LUNF_vect_num 14 ++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_HUNF_vect_num 15 ++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPA_vect_num 16 ++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPB_vect_num 17 ++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPC_vect_num 18 ++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPD_vect_num 19 ++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LUNF_vect_num 77 ++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_HUNF_vect_num 78 ++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPA_vect_num 79 ++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPB_vect_num 80 ++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPC_vect_num 81 ++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPD_vect_num 82 ++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (91 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (139264) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (131072) ++#define APP_SECTION_PAGE_SIZE (256) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x1E000) ++#define APPTABLE_SECTION_SIZE (8192) ++#define APPTABLE_SECTION_PAGE_SIZE (256) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x20000) ++#define BOOT_SECTION_SIZE (8192) ++#define BOOT_SECTION_PAGE_SIZE (256) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (16384) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (2048) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (8192) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (2048) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (6) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (256) ++#define USER_SIGNATURES_PAGE_SIZE (256) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (64) ++#define PROD_SIGNATURES_PAGE_SIZE (256) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 256 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 Reserved */ ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x97 ++#define SIGNATURE_2 0x47 ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA128D4_H_INCLUDED */ ++ +diff --git a/include/avr/iox16a4.h b/include/avr/iox16a4.h +index 38df6f9..45d39e9 100644 +--- a/include/avr/iox16a4.h ++++ b/include/avr/iox16a4.h +@@ -1,6673 +1,6673 @@ +-/* Copyright (c) 2009-2010 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iox16a4.h 2200 2010-12-14 04:24:24Z arcanum $ */ +- +-/* avr/iox16a4.h - definitions for ATxmega16A4 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iox16a4.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATxmega16A4_H_ +-#define _AVR_ATxmega16A4_H_ 1 +- +- +-/* Ungrouped common registers */ +-#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +-#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +-#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +-#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +-#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +-#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +-#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +-#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +-#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +-#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +-#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +-#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +-#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +-#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +-#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +-#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +- +-/* Deprecated */ +-#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +-#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +-#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +-#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +-#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +-#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +-#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +-#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +-#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +-#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +-#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +-#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +-#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +-#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +-#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +-#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +- +-#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +-#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +-#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +-#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +-#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +-#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +-#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +-#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +-#define SREG _SFR_MEM8(0x003F) /* Status Register */ +- +- +-/* C Language Only */ +-#if !defined (__ASSEMBLER__) +- +-#include +- +-typedef volatile uint8_t register8_t; +-typedef volatile uint16_t register16_t; +-typedef volatile uint32_t register32_t; +- +- +-#ifdef _WORDREGISTER +-#undef _WORDREGISTER +-#endif +-#define _WORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register16_t regname; \ +- struct \ +- { \ +- register8_t regname ## L; \ +- register8_t regname ## H; \ +- }; \ +- } +- +-#ifdef _DWORDREGISTER +-#undef _DWORDREGISTER +-#endif +-#define _DWORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register32_t regname; \ +- struct \ +- { \ +- register8_t regname ## 0; \ +- register8_t regname ## 1; \ +- register8_t regname ## 2; \ +- register8_t regname ## 3; \ +- }; \ +- } +- +- +-/* +-========================================================================== +-IO Module Structures +-========================================================================== +-*/ +- +- +-/* +--------------------------------------------------------------------------- +-XOCD - On-Chip Debug System +--------------------------------------------------------------------------- +-*/ +- +-/* On-Chip Debug System */ +-typedef struct OCD_struct +-{ +- register8_t OCDR0; /* OCD Register 0 */ +- register8_t OCDR1; /* OCD Register 1 */ +-} OCD_t; +- +- +-/* CCP signatures */ +-typedef enum CCP_enum +-{ +- CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ +- CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +-} CCP_t; +- +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Clock System */ +-typedef struct CLK_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t PSCTRL; /* Prescaler Control Register */ +- register8_t LOCK; /* Lock register */ +- register8_t RTCCTRL; /* RTC Control Register */ +-} CLK_t; +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Power Reduction */ +-typedef struct PR_struct +-{ +- register8_t PRGEN; /* General Power Reduction */ +- register8_t PRPA; /* Power Reduction Port A */ +- register8_t PRPB; /* Power Reduction Port B */ +- register8_t PRPC; /* Power Reduction Port C */ +- register8_t PRPD; /* Power Reduction Port D */ +- register8_t PRPE; /* Power Reduction Port E */ +- register8_t PRPF; /* Power Reduction Port F */ +-} PR_t; +- +-/* System Clock Selection */ +-typedef enum CLK_SCLKSEL_enum +-{ +- CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ +- CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ +- CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ +- CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ +- CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +-} CLK_SCLKSEL_t; +- +-/* Prescaler A Division Factor */ +-typedef enum CLK_PSADIV_enum +-{ +- CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ +- CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ +- CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ +- CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ +- CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ +- CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ +- CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ +- CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ +- CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ +- CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +-} CLK_PSADIV_t; +- +-/* Prescaler B and C Division Factor */ +-typedef enum CLK_PSBCDIV_enum +-{ +- CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ +- CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ +- CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ +- CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +-} CLK_PSBCDIV_t; +- +-/* RTC Clock Source */ +-typedef enum CLK_RTCSRC_enum +-{ +- CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ +- CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ +- CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ +- CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +-} CLK_RTCSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-SLEEP - Sleep Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Sleep Controller */ +-typedef struct SLEEP_struct +-{ +- register8_t CTRL; /* Control Register */ +-} SLEEP_t; +- +-/* Sleep Mode */ +-typedef enum SLEEP_SMODE_enum +-{ +- SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ +- SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +- SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ +- SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ +- SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +-} SLEEP_SMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-OSC - Oscillator +--------------------------------------------------------------------------- +-*/ +- +-/* Oscillator */ +-typedef struct OSC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t XOSCCTRL; /* External Oscillator Control Register */ +- register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ +- register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ +- register8_t PLLCTRL; /* PLL Control REgister */ +- register8_t DFLLCTRL; /* DFLL Control Register */ +-} OSC_t; +- +-/* Oscillator Frequency Range */ +-typedef enum OSC_FRQRANGE_enum +-{ +- OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ +- OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ +- OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ +- OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +-} OSC_FRQRANGE_t; +- +-/* External Oscillator Selection and Startup Time */ +-typedef enum OSC_XOSCSEL_enum +-{ +- OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ +- OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ +- OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ +- OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ +- OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +-} OSC_XOSCSEL_t; +- +-/* PLL Clock Source */ +-typedef enum OSC_PLLSRC_enum +-{ +- OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ +- OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ +- OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +-} OSC_PLLSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-DFLL - DFLL +--------------------------------------------------------------------------- +-*/ +- +-/* DFLL */ +-typedef struct DFLL_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t CALA; /* Calibration Register A */ +- register8_t CALB; /* Calibration Register B */ +- register8_t COMP0; /* Oscillator Compare Register 0 */ +- register8_t COMP1; /* Oscillator Compare Register 1 */ +- register8_t COMP2; /* Oscillator Compare Register 2 */ +- register8_t reserved_0x07; +-} DFLL_t; +- +- +-/* +--------------------------------------------------------------------------- +-RST - Reset +--------------------------------------------------------------------------- +-*/ +- +-/* Reset */ +-typedef struct RST_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t CTRL; /* Control Register */ +-} RST_t; +- +- +-/* +--------------------------------------------------------------------------- +-WDT - Watch-Dog Timer +--------------------------------------------------------------------------- +-*/ +- +-/* Watch-Dog Timer */ +-typedef struct WDT_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t WINCTRL; /* Windowed Mode Control */ +- register8_t STATUS; /* Status */ +-} WDT_t; +- +-/* Period setting */ +-typedef enum WDT_PER_enum +-{ +- WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ +- WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ +- WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ +- WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_PER_t; +- +-/* Closed window period */ +-typedef enum WDT_WPER_enum +-{ +- WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ +- WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ +- WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ +- WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_WPER_t; +- +- +-/* +--------------------------------------------------------------------------- +-MCU - MCU Control +--------------------------------------------------------------------------- +-*/ +- +-/* MCU Control */ +-typedef struct MCU_struct +-{ +- register8_t DEVID0; /* Device ID byte 0 */ +- register8_t DEVID1; /* Device ID byte 1 */ +- register8_t DEVID2; /* Device ID byte 2 */ +- register8_t REVID; /* Revision ID */ +- register8_t JTAGUID; /* JTAG User ID */ +- register8_t reserved_0x05; +- register8_t MCUCR; /* MCU Control */ +- register8_t reserved_0x07; +- register8_t EVSYSLOCK; /* Event System Lock */ +- register8_t AWEXLOCK; /* AWEX Lock */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +-} MCU_t; +- +- +-/* +--------------------------------------------------------------------------- +-PMIC - Programmable Multi-level Interrupt Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Programmable Multi-level Interrupt Controller */ +-typedef struct PMIC_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t INTPRI; /* Interrupt Priority */ +- register8_t CTRL; /* Control Register */ +-} PMIC_t; +- +- +-/* +--------------------------------------------------------------------------- +-DMA - DMA Controller +--------------------------------------------------------------------------- +-*/ +- +-/* DMA Channel */ +-typedef struct DMA_CH_struct +-{ +- register8_t CTRLA; /* Channel Control */ +- register8_t CTRLB; /* Channel Control */ +- register8_t ADDRCTRL; /* Address Control */ +- register8_t TRIGSRC; /* Channel Trigger Source */ +- _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ +- register8_t REPCNT; /* Channel Repeat Count */ +- register8_t reserved_0x07; +- register8_t SRCADDR0; /* Channel Source Address 0 */ +- register8_t SRCADDR1; /* Channel Source Address 1 */ +- register8_t SRCADDR2; /* Channel Source Address 2 */ +- register8_t reserved_0x0B; +- register8_t DESTADDR0; /* Channel Destination Address 0 */ +- register8_t DESTADDR1; /* Channel Destination Address 1 */ +- register8_t DESTADDR2; /* Channel Destination Address 2 */ +- register8_t reserved_0x0F; +-} DMA_CH_t; +- +-/* +--------------------------------------------------------------------------- +-DMA - DMA Controller +--------------------------------------------------------------------------- +-*/ +- +-/* DMA Controller */ +-typedef struct DMA_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t reserved_0x01; +- register8_t reserved_0x02; +- register8_t INTFLAGS; /* Transfer Interrupt Status */ +- register8_t STATUS; /* Status */ +- register8_t reserved_0x05; +- _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- DMA_CH_t CH0; /* DMA Channel 0 */ +- DMA_CH_t CH1; /* DMA Channel 1 */ +- DMA_CH_t CH2; /* DMA Channel 2 */ +- DMA_CH_t CH3; /* DMA Channel 3 */ +-} DMA_t; +- +-/* Burst mode */ +-typedef enum DMA_CH_BURSTLEN_enum +-{ +- DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ +- DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ +- DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ +- DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +-} DMA_CH_BURSTLEN_t; +- +-/* Source address reload mode */ +-typedef enum DMA_CH_SRCRELOAD_enum +-{ +- DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ +- DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ +- DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ +- DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +-} DMA_CH_SRCRELOAD_t; +- +-/* Source addressing mode */ +-typedef enum DMA_CH_SRCDIR_enum +-{ +- DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ +- DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ +- DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +-} DMA_CH_SRCDIR_t; +- +-/* Destination adress reload mode */ +-typedef enum DMA_CH_DESTRELOAD_enum +-{ +- DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ +- DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ +- DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ +- DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +-} DMA_CH_DESTRELOAD_t; +- +-/* Destination adressing mode */ +-typedef enum DMA_CH_DESTDIR_enum +-{ +- DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ +- DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ +- DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +-} DMA_CH_DESTDIR_t; +- +-/* Transfer trigger source */ +-typedef enum DMA_CH_TRIGSRC_enum +-{ +- DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ +- DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ +- DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ +- DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ +- DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ +- DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ +- DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ +- DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ +- DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ +- DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ +- DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ +- DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ +- DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ +- DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ +- DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ +- DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ +- DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ +- DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ +- DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ +- DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ +- DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ +- DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ +- DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ +- DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ +- DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ +- DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ +- DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ +- DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ +- DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ +- DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ +- DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ +- DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ +- DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ +- DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ +- DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ +- DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ +- DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ +- DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ +- DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +-} DMA_CH_TRIGSRC_t; +- +-/* Double buffering mode */ +-typedef enum DMA_DBUFMODE_enum +-{ +- DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ +- DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ +- DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ +- DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +-} DMA_DBUFMODE_t; +- +-/* Priority mode */ +-typedef enum DMA_PRIMODE_enum +-{ +- DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ +- DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ +- DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ +- DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +-} DMA_PRIMODE_t; +- +-/* Interrupt level */ +-typedef enum DMA_CH_ERRINTLVL_enum +-{ +- DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ +- DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ +- DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +-} DMA_CH_ERRINTLVL_t; +- +-/* Interrupt level */ +-typedef enum DMA_CH_TRNINTLVL_enum +-{ +- DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ +- DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ +- DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +-} DMA_CH_TRNINTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-EVSYS - Event System +--------------------------------------------------------------------------- +-*/ +- +-/* Event System */ +-typedef struct EVSYS_struct +-{ +- register8_t CH0MUX; /* Event Channel 0 Multiplexer */ +- register8_t CH1MUX; /* Event Channel 1 Multiplexer */ +- register8_t CH2MUX; /* Event Channel 2 Multiplexer */ +- register8_t CH3MUX; /* Event Channel 3 Multiplexer */ +- register8_t CH4MUX; /* Event Channel 4 Multiplexer */ +- register8_t CH5MUX; /* Event Channel 5 Multiplexer */ +- register8_t CH6MUX; /* Event Channel 6 Multiplexer */ +- register8_t CH7MUX; /* Event Channel 7 Multiplexer */ +- register8_t CH0CTRL; /* Channel 0 Control Register */ +- register8_t CH1CTRL; /* Channel 1 Control Register */ +- register8_t CH2CTRL; /* Channel 2 Control Register */ +- register8_t CH3CTRL; /* Channel 3 Control Register */ +- register8_t CH4CTRL; /* Channel 4 Control Register */ +- register8_t CH5CTRL; /* Channel 5 Control Register */ +- register8_t CH6CTRL; /* Channel 6 Control Register */ +- register8_t CH7CTRL; /* Channel 7 Control Register */ +- register8_t STROBE; /* Event Strobe */ +- register8_t DATA; /* Event Data */ +-} EVSYS_t; +- +-/* Quadrature Decoder Index Recognition Mode */ +-typedef enum EVSYS_QDIRM_enum +-{ +- EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ +- EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ +- EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ +- EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +-} EVSYS_QDIRM_t; +- +-/* Digital filter coefficient */ +-typedef enum EVSYS_DIGFILT_enum +-{ +- EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ +- EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ +- EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ +- EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ +- EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ +- EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ +- EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ +- EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +-} EVSYS_DIGFILT_t; +- +-/* Event Channel multiplexer input selection */ +-typedef enum EVSYS_CHMUX_enum +-{ +- EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ +- EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ +- EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ +- EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ +- EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ +- EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ +- EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ +- EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ +- EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ +- EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ +- EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ +- EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ +- EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ +- EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ +- EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ +- EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ +- EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ +- EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ +- EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ +- EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ +- EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ +- EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ +- EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ +- EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ +- EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ +- EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ +- EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ +- EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ +- EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ +- EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ +- EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ +- EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ +- EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ +- EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ +- EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ +- EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ +- EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ +- EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ +- EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ +- EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ +- EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ +- EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ +- EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ +- EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ +- EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ +- EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ +- EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ +- EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ +- EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ +- EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ +- EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ +- EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ +- EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ +- EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ +- EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ +- EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ +- EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ +- EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ +- EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ +- EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ +- EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ +- EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ +- EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ +- EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ +- EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ +- EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ +- EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ +- EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ +- EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ +- EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ +- EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ +- EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ +- EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ +- EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ +- EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ +- EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ +- EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ +- EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ +- EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ +- EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ +- EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ +- EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ +- EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ +- EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ +- EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ +- EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ +- EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ +- EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ +- EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ +- EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ +- EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ +- EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ +- EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ +- EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ +- EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ +- EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ +- EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ +- EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ +- EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ +- EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ +- EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ +- EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ +- EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ +- EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ +- EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ +- EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ +- EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ +- EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ +- EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ +- EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ +- EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +- EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ +- EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ +- EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ +- EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +-} EVSYS_CHMUX_t; +- +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Non-volatile Memory Controller */ +-typedef struct NVM_struct +-{ +- register8_t ADDR0; /* Address Register 0 */ +- register8_t ADDR1; /* Address Register 1 */ +- register8_t ADDR2; /* Address Register 2 */ +- register8_t reserved_0x03; +- register8_t DATA0; /* Data Register 0 */ +- register8_t DATA1; /* Data Register 1 */ +- register8_t DATA2; /* Data Register 2 */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t CMD; /* Command */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t INTCTRL; /* Interrupt Control */ +- register8_t reserved_0x0E; +- register8_t STATUS; /* Status */ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Lock Bits */ +-typedef struct NVM_LOCKBITS_struct +-{ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_LOCKBITS_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Fuses */ +-typedef struct NVM_FUSES_struct +-{ +- register8_t FUSEBYTE0; /* User ID */ +- register8_t FUSEBYTE1; /* Watchdog Configuration */ +- register8_t FUSEBYTE2; /* Reset Configuration */ +- register8_t reserved_0x03; +- register8_t FUSEBYTE4; /* Start-up Configuration */ +- register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +-} NVM_FUSES_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Production Signatures */ +-typedef struct NVM_PROD_SIGNATURES_struct +-{ +- register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ +- register8_t reserved_0x01; +- register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ +- register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ +- register8_t reserved_0x04; +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ +- register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ +- register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ +- register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ +- register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ +- register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t WAFNUM; /* Wafer Number */ +- register8_t reserved_0x11; +- register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ +- register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ +- register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ +- register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ +- register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ +- register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ +- register8_t reserved_0x26; +- register8_t reserved_0x27; +- register8_t reserved_0x28; +- register8_t reserved_0x29; +- register8_t reserved_0x2A; +- register8_t reserved_0x2B; +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ +- register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ +- register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ +- register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ +- register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ +- register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- register8_t reserved_0x36; +- register8_t reserved_0x37; +- register8_t reserved_0x38; +- register8_t reserved_0x39; +- register8_t reserved_0x3A; +- register8_t reserved_0x3B; +- register8_t reserved_0x3C; +- register8_t reserved_0x3D; +- register8_t reserved_0x3E; +-} NVM_PROD_SIGNATURES_t; +- +-/* NVM Command */ +-typedef enum NVM_CMD_enum +-{ +- NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ +- NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ +- NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ +- NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ +- NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ +- NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ +- NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ +- NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ +- NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ +- NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ +- NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ +- NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ +- NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ +- NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ +- NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ +- NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ +- NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ +- NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ +- NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ +- NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ +- NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ +- NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ +- NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ +- NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ +- NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ +- NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +-} NVM_CMD_t; +- +-/* SPM ready interrupt level */ +-typedef enum NVM_SPMLVL_enum +-{ +- NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ +- NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ +- NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +-} NVM_SPMLVL_t; +- +-/* EEPROM ready interrupt level */ +-typedef enum NVM_EELVL_enum +-{ +- NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ +- NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ +- NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +-} NVM_EELVL_t; +- +-/* Boot lock bits - boot setcion */ +-typedef enum NVM_BLBB_enum +-{ +- NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +- NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ +- NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ +- NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +-} NVM_BLBB_t; +- +-/* Boot lock bits - application section */ +-typedef enum NVM_BLBA_enum +-{ +- NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +- NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ +- NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ +- NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +-} NVM_BLBA_t; +- +-/* Boot lock bits - application table section */ +-typedef enum NVM_BLBAT_enum +-{ +- NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +- NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ +- NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ +- NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +-} NVM_BLBAT_t; +- +-/* Lock bits */ +-typedef enum NVM_LB_enum +-{ +- NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +- NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ +- NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +-} NVM_LB_t; +- +-/* Boot Loader Section Reset Vector */ +-typedef enum BOOTRST_enum +-{ +- BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ +- BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +-} BOOTRST_t; +- +-/* BOD operation */ +-typedef enum BOD_enum +-{ +- BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ +- BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ +- BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +-} BOD_t; +- +-/* Watchdog (Window) Timeout Period */ +-typedef enum WD_enum +-{ +- WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ +- WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ +- WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ +- WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ +- WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ +- WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ +- WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ +- WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ +- WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ +- WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ +- WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +-} WD_t; +- +-/* Start-up Time */ +-typedef enum SUT_enum +-{ +- SUT_0MS_gc = (0x03<<2), /* 0 ms */ +- SUT_4MS_gc = (0x01<<2), /* 4 ms */ +- SUT_64MS_gc = (0x00<<2), /* 64 ms */ +-} SUT_t; +- +-/* Brown Out Detection Voltage Level */ +-typedef enum BODLVL_enum +-{ +- BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ +- BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ +- BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ +- BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ +- BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ +- BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ +- BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ +-} BODLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-AC - Analog Comparator +--------------------------------------------------------------------------- +-*/ +- +-/* Analog Comparator */ +-typedef struct AC_struct +-{ +- register8_t AC0CTRL; /* Comparator 0 Control */ +- register8_t AC1CTRL; /* Comparator 1 Control */ +- register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ +- register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t WINCTRL; /* Window Mode Control */ +- register8_t STATUS; /* Status */ +-} AC_t; +- +-/* Interrupt mode */ +-typedef enum AC_INTMODE_enum +-{ +- AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ +- AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ +- AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +-} AC_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum AC_INTLVL_enum +-{ +- AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ +- AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ +- AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ +- AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +-} AC_INTLVL_t; +- +-/* Hysteresis mode selection */ +-typedef enum AC_HYSMODE_enum +-{ +- AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ +- AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ +- AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +-} AC_HYSMODE_t; +- +-/* Positive input multiplexer selection */ +-typedef enum AC_MUXPOS_enum +-{ +- AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ +- AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ +- AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ +- AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ +- AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ +- AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ +- AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +- AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +-} AC_MUXPOS_t; +- +-/* Negative input multiplexer selection */ +-typedef enum AC_MUXNEG_enum +-{ +- AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ +- AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ +- AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ +- AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ +- AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ +- AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ +- AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ +- AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +-} AC_MUXNEG_t; +- +-/* Windows interrupt mode */ +-typedef enum AC_WINTMODE_enum +-{ +- AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ +- AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ +- AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ +- AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +-} AC_WINTMODE_t; +- +-/* Window interrupt level */ +-typedef enum AC_WINTLVL_enum +-{ +- AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ +- AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ +- AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +-} AC_WINTLVL_t; +- +-/* Window mode state */ +-typedef enum AC_WSTATE_enum +-{ +- AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ +- AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ +- AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +-} AC_WSTATE_t; +- +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* ADC Channel */ +-typedef struct ADC_CH_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t MUXCTRL; /* MUX Control */ +- register8_t INTCTRL; /* Channel Interrupt Control */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- _WORDREGISTER(RES); /* Channel Result */ +- register8_t reserved_0x6; +- register8_t reserved_0x7; +-} ADC_CH_t; +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Analog-to-Digital Converter */ +-typedef struct ADC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t REFCTRL; /* Reference Control */ +- register8_t EVCTRL; /* Event Control */ +- register8_t PRESCALER; /* Clock Prescaler */ +- register8_t reserved_0x05; +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- _WORDREGISTER(CAL); /* Calibration Value */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- _WORDREGISTER(CH0RES); /* Channel 0 Result */ +- _WORDREGISTER(CH1RES); /* Channel 1 Result */ +- _WORDREGISTER(CH2RES); /* Channel 2 Result */ +- _WORDREGISTER(CH3RES); /* Channel 3 Result */ +- _WORDREGISTER(CMP); /* Compare Value */ +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- ADC_CH_t CH0; /* ADC Channel 0 */ +- ADC_CH_t CH1; /* ADC Channel 1 */ +- ADC_CH_t CH2; /* ADC Channel 2 */ +- ADC_CH_t CH3; /* ADC Channel 3 */ +-} ADC_t; +- +-/* Positive input multiplexer selection */ +-typedef enum ADC_CH_MUXPOS_enum +-{ +- ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ +- ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ +- ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ +- ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ +- ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ +- ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ +- ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ +- ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +-} ADC_CH_MUXPOS_t; +- +-/* Internal input multiplexer selections */ +-typedef enum ADC_CH_MUXINT_enum +-{ +- ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ +- ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ +- ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +- ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +-} ADC_CH_MUXINT_t; +- +-/* Negative input multiplexer selection */ +-typedef enum ADC_CH_MUXNEG_enum +-{ +- ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ +- ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ +- ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ +- ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ +- ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ +- ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ +- ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ +- ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +-} ADC_CH_MUXNEG_t; +- +-/* Input mode */ +-typedef enum ADC_CH_INPUTMODE_enum +-{ +- ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ +- ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ +- ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ +- ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +-} ADC_CH_INPUTMODE_t; +- +-/* Gain factor */ +-typedef enum ADC_CH_GAIN_enum +-{ +- ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ +- ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ +- ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ +- ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ +- ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ +- ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ +- ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ +-} ADC_CH_GAIN_t; +- +-/* Conversion result resolution */ +-typedef enum ADC_RESOLUTION_enum +-{ +- ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ +- ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ +- ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +-} ADC_RESOLUTION_t; +- +-/* Voltage reference selection */ +-typedef enum ADC_REFSEL_enum +-{ +- ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ +- ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ +- ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ +- ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +-} ADC_REFSEL_t; +- +-/* Channel sweep selection */ +-typedef enum ADC_SWEEP_enum +-{ +- ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ +- ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ +- ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ +- ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +-} ADC_SWEEP_t; +- +-/* Event channel input selection */ +-typedef enum ADC_EVSEL_enum +-{ +- ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ +- ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ +- ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ +- ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ +- ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ +- ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ +- ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ +- ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +-} ADC_EVSEL_t; +- +-/* Event action selection */ +-typedef enum ADC_EVACT_enum +-{ +- ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ +- ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ +- ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ +- ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ +- ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ +- ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ +- ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ +-} ADC_EVACT_t; +- +-/* Interupt mode */ +-typedef enum ADC_CH_INTMODE_enum +-{ +- ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ +- ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ +- ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +-} ADC_CH_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum ADC_CH_INTLVL_enum +-{ +- ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ +- ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ +- ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +-} ADC_CH_INTLVL_t; +- +-/* DMA request selection */ +-typedef enum ADC_DMASEL_enum +-{ +- ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ +- ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ +- ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ +- ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +-} ADC_DMASEL_t; +- +-/* Clock prescaler */ +-typedef enum ADC_PRESCALER_enum +-{ +- ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ +- ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ +- ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ +- ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ +- ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ +- ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ +- ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ +- ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +-} ADC_PRESCALER_t; +- +- +-/* +--------------------------------------------------------------------------- +-DAC - Digital/Analog Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Digital-to-Analog Converter */ +-typedef struct DAC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t EVCTRL; /* Event Input Control */ +- register8_t TIMCTRL; /* Timing Control */ +- register8_t STATUS; /* Status */ +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t GAINCAL; /* Gain Calibration */ +- register8_t OFFSETCAL; /* Offset Calibration */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- _WORDREGISTER(CH0DATA); /* Channel 0 Data */ +- _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +-} DAC_t; +- +-/* Output channel selection */ +-typedef enum DAC_CHSEL_enum +-{ +- DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ +- DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ +-} DAC_CHSEL_t; +- +-/* Reference voltage selection */ +-typedef enum DAC_REFSEL_enum +-{ +- DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ +- DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ +- DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ +- DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +-} DAC_REFSEL_t; +- +-/* Event channel selection */ +-typedef enum DAC_EVSEL_enum +-{ +- DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ +- DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ +- DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ +- DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ +- DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ +- DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ +- DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ +- DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +-} DAC_EVSEL_t; +- +-/* Conversion interval */ +-typedef enum DAC_CONINTVAL_enum +-{ +- DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ +- DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ +- DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ +- DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ +- DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ +- DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ +- DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ +- DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ +-} DAC_CONINTVAL_t; +- +-/* Refresh rate */ +-typedef enum DAC_REFRESH_enum +-{ +- DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ +- DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ +- DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ +- DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ +- DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ +- DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ +- DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ +- DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ +- DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ +- DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ +- DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ +- DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ +- DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ +- DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ +-} DAC_REFRESH_t; +- +- +-/* +--------------------------------------------------------------------------- +-RTC - Real-Time Clounter +--------------------------------------------------------------------------- +-*/ +- +-/* Real-Time Counter */ +-typedef struct RTC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t TEMP; /* Temporary register */ +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- _WORDREGISTER(CNT); /* Count Register */ +- _WORDREGISTER(PER); /* Period Register */ +- _WORDREGISTER(COMP); /* Compare Register */ +-} RTC_t; +- +-/* Prescaler Factor */ +-typedef enum RTC_PRESCALER_enum +-{ +- RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ +- RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ +- RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ +- RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ +- RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ +- RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ +- RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ +- RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +-} RTC_PRESCALER_t; +- +-/* Compare Interrupt level */ +-typedef enum RTC_COMPINTLVL_enum +-{ +- RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} RTC_COMPINTLVL_t; +- +-/* Overflow Interrupt level */ +-typedef enum RTC_OVFINTLVL_enum +-{ +- RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} RTC_OVFINTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* EBI Chip Select Module */ +-typedef struct EBI_CS_struct +-{ +- register8_t CTRLA; /* Chip Select Control Register A */ +- register8_t CTRLB; /* Chip Select Control Register B */ +- _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +-} EBI_CS_t; +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* External Bus Interface */ +-typedef struct EBI_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t SDRAMCTRLA; /* SDRAM Control Register A */ +- register8_t reserved_0x02; +- register8_t reserved_0x03; +- _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ +- _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ +- register8_t SDRAMCTRLB; /* SDRAM Control Register B */ +- register8_t SDRAMCTRLC; /* SDRAM Control Register C */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- EBI_CS_t CS0; /* Chip Select 0 */ +- EBI_CS_t CS1; /* Chip Select 1 */ +- EBI_CS_t CS2; /* Chip Select 2 */ +- EBI_CS_t CS3; /* Chip Select 3 */ +-} EBI_t; +- +-/* Chip Select adress space */ +-typedef enum EBI_CS_ASIZE_enum +-{ +- EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ +- EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ +- EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ +- EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ +- EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ +- EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ +- EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ +- EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ +- EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ +- EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ +- EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ +- EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ +- EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ +- EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ +- EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ +- EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ +- EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +-} EBI_CS_ASIZE_t; +- +-/* */ +-typedef enum EBI_CS_SRWS_enum +-{ +- EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_CS_SRWS_t; +- +-/* Chip Select address mode */ +-typedef enum EBI_CS_MODE_enum +-{ +- EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ +- EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ +- EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ +- EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +-} EBI_CS_MODE_t; +- +-/* Chip Select SDRAM mode */ +-typedef enum EBI_CS_SDMODE_enum +-{ +- EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ +- EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +-} EBI_CS_SDMODE_t; +- +-/* */ +-typedef enum EBI_SDDATAW_enum +-{ +- EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ +- EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +-} EBI_SDDATAW_t; +- +-/* */ +-typedef enum EBI_LPCMODE_enum +-{ +- EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ +- EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +-} EBI_LPCMODE_t; +- +-/* */ +-typedef enum EBI_SRMODE_enum +-{ +- EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ +- EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ +- EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ +- EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +-} EBI_SRMODE_t; +- +-/* */ +-typedef enum EBI_IFMODE_enum +-{ +- EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ +- EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ +- EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ +- EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +-} EBI_IFMODE_t; +- +-/* */ +-typedef enum EBI_SDCOL_enum +-{ +- EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ +- EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ +- EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ +- EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +-} EBI_SDCOL_t; +- +-/* */ +-typedef enum EBI_MRDLY_enum +-{ +- EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_MRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCYCDLY_enum +-{ +- EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ROWCYCDLY_t; +- +-/* */ +-typedef enum EBI_RPDLY_enum +-{ +- EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_RPDLY_t; +- +-/* */ +-typedef enum EBI_WRDLY_enum +-{ +- EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_WRDLY_t; +- +-/* */ +-typedef enum EBI_ESRDLY_enum +-{ +- EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ESRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCOLDLY_enum +-{ +- EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_ROWCOLDLY_t; +- +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_MASTER_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t STATUS; /* Status Register */ +- register8_t BAUD; /* Baurd Rate Control Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +-} TWI_MASTER_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_SLAVE_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t STATUS; /* Status Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +- register8_t ADDRMASK; /* Address Mask Register */ +-} TWI_SLAVE_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Two-Wire Interface */ +-typedef struct TWI_struct +-{ +- register8_t CTRL; /* TWI Common Control Register */ +- TWI_MASTER_t MASTER; /* TWI master module */ +- TWI_SLAVE_t SLAVE; /* TWI slave module */ +-} TWI_t; +- +-/* Master Interrupt Level */ +-typedef enum TWI_MASTER_INTLVL_enum +-{ +- TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_MASTER_INTLVL_t; +- +-/* Inactive Timeout */ +-typedef enum TWI_MASTER_TIMEOUT_enum +-{ +- TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ +- TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ +- TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ +- TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +-} TWI_MASTER_TIMEOUT_t; +- +-/* Master Command */ +-typedef enum TWI_MASTER_CMD_enum +-{ +- TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ +- TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ +- TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +-} TWI_MASTER_CMD_t; +- +-/* Master Bus State */ +-typedef enum TWI_MASTER_BUSSTATE_enum +-{ +- TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ +- TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ +- TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ +- TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +-} TWI_MASTER_BUSSTATE_t; +- +-/* Slave Interrupt Level */ +-typedef enum TWI_SLAVE_INTLVL_enum +-{ +- TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_SLAVE_INTLVL_t; +- +-/* Slave Command */ +-typedef enum TWI_SLAVE_CMD_enum +-{ +- TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ +- TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +-} TWI_SLAVE_CMD_t; +- +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O port Configuration */ +-typedef struct PORTCFG_struct +-{ +- register8_t MPCMASK; /* Multi-pin Configuration Mask */ +- register8_t reserved_0x01; +- register8_t VPCTRLA; /* Virtual Port Control Register A */ +- register8_t VPCTRLB; /* Virtual Port Control Register B */ +- register8_t CLKEVOUT; /* Clock and Event Out Register */ +-} PORTCFG_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* Virtual Port */ +-typedef struct VPORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t OUT; /* I/O Port Output */ +- register8_t IN; /* I/O Port Input */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +-} VPORT_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O Ports */ +-typedef struct PORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t DIRSET; /* I/O Port Data Direction Set */ +- register8_t DIRCLR; /* I/O Port Data Direction Clear */ +- register8_t DIRTGL; /* I/O Port Data Direction Toggle */ +- register8_t OUT; /* I/O Port Output */ +- register8_t OUTSET; /* I/O Port Output Set */ +- register8_t OUTCLR; /* I/O Port Output Clear */ +- register8_t OUTTGL; /* I/O Port Output Toggle */ +- register8_t IN; /* I/O port Input */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INT0MASK; /* Port Interrupt 0 Mask */ +- register8_t INT1MASK; /* Port Interrupt 1 Mask */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t PIN0CTRL; /* Pin 0 Control Register */ +- register8_t PIN1CTRL; /* Pin 1 Control Register */ +- register8_t PIN2CTRL; /* Pin 2 Control Register */ +- register8_t PIN3CTRL; /* Pin 3 Control Register */ +- register8_t PIN4CTRL; /* Pin 4 Control Register */ +- register8_t PIN5CTRL; /* Pin 5 Control Register */ +- register8_t PIN6CTRL; /* Pin 6 Control Register */ +- register8_t PIN7CTRL; /* Pin 7 Control Register */ +-} PORT_t; +- +-/* Virtual Port 0 Mapping */ +-typedef enum PORTCFG_VP0MAP_enum +-{ +- PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP0MAP_t; +- +-/* Virtual Port 1 Mapping */ +-typedef enum PORTCFG_VP1MAP_enum +-{ +- PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP1MAP_t; +- +-/* Virtual Port 2 Mapping */ +-typedef enum PORTCFG_VP2MAP_enum +-{ +- PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP2MAP_t; +- +-/* Virtual Port 3 Mapping */ +-typedef enum PORTCFG_VP3MAP_enum +-{ +- PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP3MAP_t; +- +-/* Clock Output Port */ +-typedef enum PORTCFG_CLKOUT_enum +-{ +- PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ +- PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ +- PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ +- PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +-} PORTCFG_CLKOUT_t; +- +-/* Event Output Port */ +-typedef enum PORTCFG_EVOUT_enum +-{ +- PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ +- PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ +- PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ +- PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +-} PORTCFG_EVOUT_t; +- +-/* Port Interrupt 0 Level */ +-typedef enum PORT_INT0LVL_enum +-{ +- PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ +- PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ +- PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +-} PORT_INT0LVL_t; +- +-/* Port Interrupt 1 Level */ +-typedef enum PORT_INT1LVL_enum +-{ +- PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ +- PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ +- PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +-} PORT_INT1LVL_t; +- +-/* Output/Pull Configuration */ +-typedef enum PORT_OPC_enum +-{ +- PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ +- PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ +- PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ +- PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ +- PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ +- PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ +- PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ +- PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +-} PORT_OPC_t; +- +-/* Input/Sense Configuration */ +-typedef enum PORT_ISC_enum +-{ +- PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ +- PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ +- PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ +- PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ +- PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +-} PORT_ISC_t; +- +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 0 */ +-typedef struct TC0_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- _WORDREGISTER(CCC); /* Compare or Capture C */ +- _WORDREGISTER(CCD); /* Compare or Capture D */ +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +- _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ +- _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +-} TC0_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 1 */ +-typedef struct TC1_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t reserved_0x2E; +- register8_t reserved_0x2F; +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +-} TC1_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* Advanced Waveform Extension */ +-typedef struct AWEX_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t FDEMASK; /* Fault Detection Event Mask */ +- register8_t FDCTRL; /* Fault Detection Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x05; +- register8_t DTBOTH; /* Dead Time Both Sides */ +- register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ +- register8_t DTLS; /* Dead Time Low Side */ +- register8_t DTHS; /* Dead Time High Side */ +- register8_t DTLSBUF; /* Dead Time Low Side Buffer */ +- register8_t DTHSBUF; /* Dead Time High Side Buffer */ +- register8_t OUTOVEN; /* Output Override Enable */ +-} AWEX_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* High-Resolution Extension */ +-typedef struct HIRES_struct +-{ +- register8_t CTRLA; /* Control Register */ +-} HIRES_t; +- +-/* Clock Selection */ +-typedef enum TC_CLKSEL_enum +-{ +- TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ +- TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ +- TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ +- TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ +- TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ +- TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ +- TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ +- TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ +- TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_CLKSEL_t; +- +-/* Waveform Generation Mode */ +-typedef enum TC_WGMODE_enum +-{ +- TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ +- TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ +- TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ +- TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ +- TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ +- TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +-} TC_WGMODE_t; +- +-/* Event Action */ +-typedef enum TC_EVACT_enum +-{ +- TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ +- TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ +- TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ +- TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ +- TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ +- TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */ +- TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +-} TC_EVACT_t; +- +-/* Event Selection */ +-typedef enum TC_EVSEL_enum +-{ +- TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_EVSEL_t; +- +-/* Error Interrupt Level */ +-typedef enum TC_ERRINTLVL_enum +-{ +- TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_ERRINTLVL_t; +- +-/* Overflow Interrupt Level */ +-typedef enum TC_OVFINTLVL_enum +-{ +- TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_OVFINTLVL_t; +- +-/* Compare or Capture D Interrupt Level */ +-typedef enum TC_CCDINTLVL_enum +-{ +- TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TC_CCDINTLVL_t; +- +-/* Compare or Capture C Interrupt Level */ +-typedef enum TC_CCCINTLVL_enum +-{ +- TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} TC_CCCINTLVL_t; +- +-/* Compare or Capture B Interrupt Level */ +-typedef enum TC_CCBINTLVL_enum +-{ +- TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_CCBINTLVL_t; +- +-/* Compare or Capture A Interrupt Level */ +-typedef enum TC_CCAINTLVL_enum +-{ +- TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_CCAINTLVL_t; +- +-/* Timer/Counter Command */ +-typedef enum TC_CMD_enum +-{ +- TC_CMD_NONE_gc = (0x00<<2), /* No Command */ +- TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ +- TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ +- TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +-} TC_CMD_t; +- +-/* Fault Detect Action */ +-typedef enum AWEX_FDACT_enum +-{ +- AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ +- AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ +- AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +-} AWEX_FDACT_t; +- +-/* High Resolution Enable */ +-typedef enum HIRES_HREN_enum +-{ +- HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ +- HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ +- HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ +- HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +-} HIRES_HREN_t; +- +- +-/* +--------------------------------------------------------------------------- +-USART - Universal Asynchronous Receiver-Transmitter +--------------------------------------------------------------------------- +-*/ +- +-/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +-typedef struct USART_struct +-{ +- register8_t DATA; /* Data Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x02; +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t BAUDCTRLA; /* Baud Rate Control Register A */ +- register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +-} USART_t; +- +-/* Receive Complete Interrupt level */ +-typedef enum USART_RXCINTLVL_enum +-{ +- USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} USART_RXCINTLVL_t; +- +-/* Transmit Complete Interrupt level */ +-typedef enum USART_TXCINTLVL_enum +-{ +- USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} USART_TXCINTLVL_t; +- +-/* Data Register Empty Interrupt level */ +-typedef enum USART_DREINTLVL_enum +-{ +- USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} USART_DREINTLVL_t; +- +-/* Character Size */ +-typedef enum USART_CHSIZE_enum +-{ +- USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ +- USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ +- USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ +- USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ +- USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +-} USART_CHSIZE_t; +- +-/* Communication Mode */ +-typedef enum USART_CMODE_enum +-{ +- USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ +- USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ +- USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ +- USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +-} USART_CMODE_t; +- +-/* Parity Mode */ +-typedef enum USART_PMODE_enum +-{ +- USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ +- USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ +- USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +-} USART_PMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-SPI - Serial Peripheral Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Serial Peripheral Interface */ +-typedef struct SPI_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t DATA; /* Data Register */ +-} SPI_t; +- +-/* SPI Mode */ +-typedef enum SPI_MODE_enum +-{ +- SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ +- SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ +- SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ +- SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +-} SPI_MODE_t; +- +-/* Prescaler setting */ +-typedef enum SPI_PRESCALER_enum +-{ +- SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ +- SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ +- SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ +- SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +-} SPI_PRESCALER_t; +- +-/* Interrupt level */ +-typedef enum SPI_INTLVL_enum +-{ +- SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} SPI_INTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-IRCOM - IR Communication Module +--------------------------------------------------------------------------- +-*/ +- +-/* IR Communication Module */ +-typedef struct IRCOM_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ +- register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +-} IRCOM_t; +- +-/* Event channel selection */ +-typedef enum IRDA_EVSEL_enum +-{ +- IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ +- IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ +- IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ +- IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +- IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ +- IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ +- IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ +- IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +-} IRDA_EVSEL_t; +- +- +-/* +--------------------------------------------------------------------------- +-AES - AES Module +--------------------------------------------------------------------------- +-*/ +- +-/* AES Module */ +-typedef struct AES_struct +-{ +- register8_t CTRL; /* AES Control Register */ +- register8_t STATUS; /* AES Status Register */ +- register8_t STATE; /* AES State Register */ +- register8_t KEY; /* AES Key Register */ +- register8_t INTCTRL; /* AES Interrupt Control Register */ +-} AES_t; +- +-/* Interrupt level */ +-typedef enum AES_INTLVL_enum +-{ +- AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} AES_INTLVL_t; +- +- +- +-/* +-========================================================================== +-IO Module Instances. Mapped to memory. +-========================================================================== +-*/ +- +-#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +-#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +-#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +-#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +-#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +-#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +-#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +-#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +-#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +-#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +-#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +-#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +-#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +-#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +-#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +-#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +-#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ +-#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +-#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +-#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +-#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +-#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ +-#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +-#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +-#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +-#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ +-#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +-#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +-#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +-#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +-#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +-#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +-#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +-#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +-#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +-#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +-#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +-#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ +-#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +-#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +-#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +-#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ +-#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ +-#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +-#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ +-#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +-#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +-#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ +-#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ +- +- +-#endif /* !defined (__ASSEMBLER__) */ +- +- +-/* ========== Flattened fully qualified IO register names ========== */ +- +-/* GPIO - General Purpose IO Registers */ +-#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +-#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +-#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +-#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +-#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +-#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +-#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +-#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +-#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +-#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +-#define GPIO_GPIORA _SFR_MEM8(0x000A) +-#define GPIO_GPIORB _SFR_MEM8(0x000B) +-#define GPIO_GPIORC _SFR_MEM8(0x000C) +-#define GPIO_GPIORD _SFR_MEM8(0x000D) +-#define GPIO_GPIORE _SFR_MEM8(0x000E) +-#define GPIO_GPIORF _SFR_MEM8(0x000F) +- +-/* Deprecated */ +-#define GPIO_GPIO0 _SFR_MEM8(0x0000) +-#define GPIO_GPIO1 _SFR_MEM8(0x0001) +-#define GPIO_GPIO2 _SFR_MEM8(0x0002) +-#define GPIO_GPIO3 _SFR_MEM8(0x0003) +-#define GPIO_GPIO4 _SFR_MEM8(0x0004) +-#define GPIO_GPIO5 _SFR_MEM8(0x0005) +-#define GPIO_GPIO6 _SFR_MEM8(0x0006) +-#define GPIO_GPIO7 _SFR_MEM8(0x0007) +-#define GPIO_GPIO8 _SFR_MEM8(0x0008) +-#define GPIO_GPIO9 _SFR_MEM8(0x0009) +-#define GPIO_GPIOA _SFR_MEM8(0x000A) +-#define GPIO_GPIOB _SFR_MEM8(0x000B) +-#define GPIO_GPIOC _SFR_MEM8(0x000C) +-#define GPIO_GPIOD _SFR_MEM8(0x000D) +-#define GPIO_GPIOE _SFR_MEM8(0x000E) +-#define GPIO_GPIOF _SFR_MEM8(0x000F) +- +-/* VPORT0 - Virtual Port 0 */ +-#define VPORT0_DIR _SFR_MEM8(0x0010) +-#define VPORT0_OUT _SFR_MEM8(0x0011) +-#define VPORT0_IN _SFR_MEM8(0x0012) +-#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) +- +-/* VPORT1 - Virtual Port 1 */ +-#define VPORT1_DIR _SFR_MEM8(0x0014) +-#define VPORT1_OUT _SFR_MEM8(0x0015) +-#define VPORT1_IN _SFR_MEM8(0x0016) +-#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) +- +-/* VPORT2 - Virtual Port 2 */ +-#define VPORT2_DIR _SFR_MEM8(0x0018) +-#define VPORT2_OUT _SFR_MEM8(0x0019) +-#define VPORT2_IN _SFR_MEM8(0x001A) +-#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) +- +-/* VPORT3 - Virtual Port 3 */ +-#define VPORT3_DIR _SFR_MEM8(0x001C) +-#define VPORT3_OUT _SFR_MEM8(0x001D) +-#define VPORT3_IN _SFR_MEM8(0x001E) +-#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) +- +-/* OCD - On-Chip Debug System */ +-#define OCD_OCDR0 _SFR_MEM8(0x002E) +-#define OCD_OCDR1 _SFR_MEM8(0x002F) +- +-/* CPU - CPU Registers */ +-#define CPU_CCP _SFR_MEM8(0x0034) +-#define CPU_RAMPD _SFR_MEM8(0x0038) +-#define CPU_RAMPX _SFR_MEM8(0x0039) +-#define CPU_RAMPY _SFR_MEM8(0x003A) +-#define CPU_RAMPZ _SFR_MEM8(0x003B) +-#define CPU_EIND _SFR_MEM8(0x003C) +-#define CPU_SPL _SFR_MEM8(0x003D) +-#define CPU_SPH _SFR_MEM8(0x003E) +-#define CPU_SREG _SFR_MEM8(0x003F) +- +-/* CLK - Clock System */ +-#define CLK_CTRL _SFR_MEM8(0x0040) +-#define CLK_PSCTRL _SFR_MEM8(0x0041) +-#define CLK_LOCK _SFR_MEM8(0x0042) +-#define CLK_RTCCTRL _SFR_MEM8(0x0043) +- +-/* SLEEP - Sleep Controller */ +-#define SLEEP_CTRL _SFR_MEM8(0x0048) +- +-/* OSC - Oscillator Control */ +-#define OSC_CTRL _SFR_MEM8(0x0050) +-#define OSC_STATUS _SFR_MEM8(0x0051) +-#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +-#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +-#define OSC_RC32KCAL _SFR_MEM8(0x0054) +-#define OSC_PLLCTRL _SFR_MEM8(0x0055) +-#define OSC_DFLLCTRL _SFR_MEM8(0x0056) +- +-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +-#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +-#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +-#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +-#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +-#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +-#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) +- +-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +-#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +-#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +-#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +-#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +-#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +-#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) +- +-/* PR - Power Reduction */ +-#define PR_PRGEN _SFR_MEM8(0x0070) +-#define PR_PRPA _SFR_MEM8(0x0071) +-#define PR_PRPB _SFR_MEM8(0x0072) +-#define PR_PRPC _SFR_MEM8(0x0073) +-#define PR_PRPD _SFR_MEM8(0x0074) +-#define PR_PRPE _SFR_MEM8(0x0075) +-#define PR_PRPF _SFR_MEM8(0x0076) +- +-/* RST - Reset Controller */ +-#define RST_STATUS _SFR_MEM8(0x0078) +-#define RST_CTRL _SFR_MEM8(0x0079) +- +-/* WDT - Watch-Dog Timer */ +-#define WDT_CTRL _SFR_MEM8(0x0080) +-#define WDT_WINCTRL _SFR_MEM8(0x0081) +-#define WDT_STATUS _SFR_MEM8(0x0082) +- +-/* MCU - MCU Control */ +-#define MCU_DEVID0 _SFR_MEM8(0x0090) +-#define MCU_DEVID1 _SFR_MEM8(0x0091) +-#define MCU_DEVID2 _SFR_MEM8(0x0092) +-#define MCU_REVID _SFR_MEM8(0x0093) +-#define MCU_JTAGUID _SFR_MEM8(0x0094) +-#define MCU_MCUCR _SFR_MEM8(0x0096) +-#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +-#define MCU_AWEXLOCK _SFR_MEM8(0x0099) +- +-/* PMIC - Programmable Interrupt Controller */ +-#define PMIC_STATUS _SFR_MEM8(0x00A0) +-#define PMIC_INTPRI _SFR_MEM8(0x00A1) +-#define PMIC_CTRL _SFR_MEM8(0x00A2) +- +-/* PORTCFG - Port Configuration */ +-#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +-#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +-#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +-#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +- +-/* AES - AES Crypto Module */ +-#define AES_CTRL _SFR_MEM8(0x00C0) +-#define AES_STATUS _SFR_MEM8(0x00C1) +-#define AES_STATE _SFR_MEM8(0x00C2) +-#define AES_KEY _SFR_MEM8(0x00C3) +-#define AES_INTCTRL _SFR_MEM8(0x00C4) +- +-/* DMA - DMA Controller */ +-#define DMA_CTRL _SFR_MEM8(0x0100) +-#define DMA_INTFLAGS _SFR_MEM8(0x0103) +-#define DMA_STATUS _SFR_MEM8(0x0104) +-#define DMA_TEMP _SFR_MEM16(0x0106) +-#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +-#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +-#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +-#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +-#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +-#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +-#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +-#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +-#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +-#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +-#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +-#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +-#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +-#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +-#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +-#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +-#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +-#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +-#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +-#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +-#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +-#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +-#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +-#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +-#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +-#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +-#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +-#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +-#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +-#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +-#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +-#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +-#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +-#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +-#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +-#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +-#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +-#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +-#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +-#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +-#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +-#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +-#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +-#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +-#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +-#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +-#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +-#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) +- +-/* EVSYS - Event System */ +-#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +-#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +-#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +-#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +-#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +-#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +-#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +-#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +-#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +-#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +-#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +-#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +-#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +-#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +-#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +-#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +-#define EVSYS_STROBE _SFR_MEM8(0x0190) +-#define EVSYS_DATA _SFR_MEM8(0x0191) +- +-/* NVM - Non Volatile Memory Controller */ +-#define NVM_ADDR0 _SFR_MEM8(0x01C0) +-#define NVM_ADDR1 _SFR_MEM8(0x01C1) +-#define NVM_ADDR2 _SFR_MEM8(0x01C2) +-#define NVM_DATA0 _SFR_MEM8(0x01C4) +-#define NVM_DATA1 _SFR_MEM8(0x01C5) +-#define NVM_DATA2 _SFR_MEM8(0x01C6) +-#define NVM_CMD _SFR_MEM8(0x01CA) +-#define NVM_CTRLA _SFR_MEM8(0x01CB) +-#define NVM_CTRLB _SFR_MEM8(0x01CC) +-#define NVM_INTCTRL _SFR_MEM8(0x01CD) +-#define NVM_STATUS _SFR_MEM8(0x01CF) +-#define NVM_LOCKBITS _SFR_MEM8(0x01D0) +- +-/* ADCA - Analog to Digital Converter A */ +-#define ADCA_CTRLA _SFR_MEM8(0x0200) +-#define ADCA_CTRLB _SFR_MEM8(0x0201) +-#define ADCA_REFCTRL _SFR_MEM8(0x0202) +-#define ADCA_EVCTRL _SFR_MEM8(0x0203) +-#define ADCA_PRESCALER _SFR_MEM8(0x0204) +-#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +-#define ADCA_CAL _SFR_MEM16(0x020C) +-#define ADCA_CH0RES _SFR_MEM16(0x0210) +-#define ADCA_CH1RES _SFR_MEM16(0x0212) +-#define ADCA_CH2RES _SFR_MEM16(0x0214) +-#define ADCA_CH3RES _SFR_MEM16(0x0216) +-#define ADCA_CMP _SFR_MEM16(0x0218) +-#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +-#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +-#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +-#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +-#define ADCA_CH0_RES _SFR_MEM16(0x0224) +-#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +-#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +-#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +-#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +-#define ADCA_CH1_RES _SFR_MEM16(0x022C) +-#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +-#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +-#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +-#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +-#define ADCA_CH2_RES _SFR_MEM16(0x0234) +-#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +-#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +-#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +-#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +-#define ADCA_CH3_RES _SFR_MEM16(0x023C) +- +-/* DACB - Digital to Analog Converter B */ +-#define DACB_CTRLA _SFR_MEM8(0x0320) +-#define DACB_CTRLB _SFR_MEM8(0x0321) +-#define DACB_CTRLC _SFR_MEM8(0x0322) +-#define DACB_EVCTRL _SFR_MEM8(0x0323) +-#define DACB_TIMCTRL _SFR_MEM8(0x0324) +-#define DACB_STATUS _SFR_MEM8(0x0325) +-#define DACB_GAINCAL _SFR_MEM8(0x0328) +-#define DACB_OFFSETCAL _SFR_MEM8(0x0329) +-#define DACB_CH0DATA _SFR_MEM16(0x0338) +-#define DACB_CH1DATA _SFR_MEM16(0x033A) +- +-/* ACA - Analog Comparator A */ +-#define ACA_AC0CTRL _SFR_MEM8(0x0380) +-#define ACA_AC1CTRL _SFR_MEM8(0x0381) +-#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +-#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +-#define ACA_CTRLA _SFR_MEM8(0x0384) +-#define ACA_CTRLB _SFR_MEM8(0x0385) +-#define ACA_WINCTRL _SFR_MEM8(0x0386) +-#define ACA_STATUS _SFR_MEM8(0x0387) +- +-/* RTC - Real-Time Counter */ +-#define RTC_CTRL _SFR_MEM8(0x0400) +-#define RTC_STATUS _SFR_MEM8(0x0401) +-#define RTC_INTCTRL _SFR_MEM8(0x0402) +-#define RTC_INTFLAGS _SFR_MEM8(0x0403) +-#define RTC_TEMP _SFR_MEM8(0x0404) +-#define RTC_CNT _SFR_MEM16(0x0408) +-#define RTC_PER _SFR_MEM16(0x040A) +-#define RTC_COMP _SFR_MEM16(0x040C) +- +-/* TWIC - Two-Wire Interface C */ +-#define TWIC_CTRL _SFR_MEM8(0x0480) +-#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +-#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +-#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +-#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +-#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +-#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +-#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +-#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +-#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +-#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +-#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +-#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +-#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) +- +-/* TWIE - Two-Wire Interface E */ +-#define TWIE_CTRL _SFR_MEM8(0x04A0) +-#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +-#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +-#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +-#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +-#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +-#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +-#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +-#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +-#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +-#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +-#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +-#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +-#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) +- +-/* PORTA - Port A */ +-#define PORTA_DIR _SFR_MEM8(0x0600) +-#define PORTA_DIRSET _SFR_MEM8(0x0601) +-#define PORTA_DIRCLR _SFR_MEM8(0x0602) +-#define PORTA_DIRTGL _SFR_MEM8(0x0603) +-#define PORTA_OUT _SFR_MEM8(0x0604) +-#define PORTA_OUTSET _SFR_MEM8(0x0605) +-#define PORTA_OUTCLR _SFR_MEM8(0x0606) +-#define PORTA_OUTTGL _SFR_MEM8(0x0607) +-#define PORTA_IN _SFR_MEM8(0x0608) +-#define PORTA_INTCTRL _SFR_MEM8(0x0609) +-#define PORTA_INT0MASK _SFR_MEM8(0x060A) +-#define PORTA_INT1MASK _SFR_MEM8(0x060B) +-#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +-#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +-#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +-#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +-#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +-#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +-#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +-#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +-#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) +- +-/* PORTB - Port B */ +-#define PORTB_DIR _SFR_MEM8(0x0620) +-#define PORTB_DIRSET _SFR_MEM8(0x0621) +-#define PORTB_DIRCLR _SFR_MEM8(0x0622) +-#define PORTB_DIRTGL _SFR_MEM8(0x0623) +-#define PORTB_OUT _SFR_MEM8(0x0624) +-#define PORTB_OUTSET _SFR_MEM8(0x0625) +-#define PORTB_OUTCLR _SFR_MEM8(0x0626) +-#define PORTB_OUTTGL _SFR_MEM8(0x0627) +-#define PORTB_IN _SFR_MEM8(0x0628) +-#define PORTB_INTCTRL _SFR_MEM8(0x0629) +-#define PORTB_INT0MASK _SFR_MEM8(0x062A) +-#define PORTB_INT1MASK _SFR_MEM8(0x062B) +-#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +-#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +-#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +-#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +-#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +-#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +-#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +-#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +-#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) +- +-/* PORTC - Port C */ +-#define PORTC_DIR _SFR_MEM8(0x0640) +-#define PORTC_DIRSET _SFR_MEM8(0x0641) +-#define PORTC_DIRCLR _SFR_MEM8(0x0642) +-#define PORTC_DIRTGL _SFR_MEM8(0x0643) +-#define PORTC_OUT _SFR_MEM8(0x0644) +-#define PORTC_OUTSET _SFR_MEM8(0x0645) +-#define PORTC_OUTCLR _SFR_MEM8(0x0646) +-#define PORTC_OUTTGL _SFR_MEM8(0x0647) +-#define PORTC_IN _SFR_MEM8(0x0648) +-#define PORTC_INTCTRL _SFR_MEM8(0x0649) +-#define PORTC_INT0MASK _SFR_MEM8(0x064A) +-#define PORTC_INT1MASK _SFR_MEM8(0x064B) +-#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +-#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +-#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +-#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +-#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +-#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +-#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +-#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +-#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) +- +-/* PORTD - Port D */ +-#define PORTD_DIR _SFR_MEM8(0x0660) +-#define PORTD_DIRSET _SFR_MEM8(0x0661) +-#define PORTD_DIRCLR _SFR_MEM8(0x0662) +-#define PORTD_DIRTGL _SFR_MEM8(0x0663) +-#define PORTD_OUT _SFR_MEM8(0x0664) +-#define PORTD_OUTSET _SFR_MEM8(0x0665) +-#define PORTD_OUTCLR _SFR_MEM8(0x0666) +-#define PORTD_OUTTGL _SFR_MEM8(0x0667) +-#define PORTD_IN _SFR_MEM8(0x0668) +-#define PORTD_INTCTRL _SFR_MEM8(0x0669) +-#define PORTD_INT0MASK _SFR_MEM8(0x066A) +-#define PORTD_INT1MASK _SFR_MEM8(0x066B) +-#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +-#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +-#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +-#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +-#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +-#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +-#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +-#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +-#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) +- +-/* PORTE - Port E */ +-#define PORTE_DIR _SFR_MEM8(0x0680) +-#define PORTE_DIRSET _SFR_MEM8(0x0681) +-#define PORTE_DIRCLR _SFR_MEM8(0x0682) +-#define PORTE_DIRTGL _SFR_MEM8(0x0683) +-#define PORTE_OUT _SFR_MEM8(0x0684) +-#define PORTE_OUTSET _SFR_MEM8(0x0685) +-#define PORTE_OUTCLR _SFR_MEM8(0x0686) +-#define PORTE_OUTTGL _SFR_MEM8(0x0687) +-#define PORTE_IN _SFR_MEM8(0x0688) +-#define PORTE_INTCTRL _SFR_MEM8(0x0689) +-#define PORTE_INT0MASK _SFR_MEM8(0x068A) +-#define PORTE_INT1MASK _SFR_MEM8(0x068B) +-#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +-#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +-#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +-#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +-#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +-#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +-#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +-#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +-#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) +- +-/* PORTR - Port R */ +-#define PORTR_DIR _SFR_MEM8(0x07E0) +-#define PORTR_DIRSET _SFR_MEM8(0x07E1) +-#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +-#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +-#define PORTR_OUT _SFR_MEM8(0x07E4) +-#define PORTR_OUTSET _SFR_MEM8(0x07E5) +-#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +-#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +-#define PORTR_IN _SFR_MEM8(0x07E8) +-#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +-#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +-#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +-#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +-#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +-#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +-#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +-#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +-#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +-#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +-#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +-#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) +- +-/* TCC0 - Timer/Counter C0 */ +-#define TCC0_CTRLA _SFR_MEM8(0x0800) +-#define TCC0_CTRLB _SFR_MEM8(0x0801) +-#define TCC0_CTRLC _SFR_MEM8(0x0802) +-#define TCC0_CTRLD _SFR_MEM8(0x0803) +-#define TCC0_CTRLE _SFR_MEM8(0x0804) +-#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +-#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +-#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +-#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +-#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +-#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +-#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +-#define TCC0_TEMP _SFR_MEM8(0x080F) +-#define TCC0_CNT _SFR_MEM16(0x0820) +-#define TCC0_PER _SFR_MEM16(0x0826) +-#define TCC0_CCA _SFR_MEM16(0x0828) +-#define TCC0_CCB _SFR_MEM16(0x082A) +-#define TCC0_CCC _SFR_MEM16(0x082C) +-#define TCC0_CCD _SFR_MEM16(0x082E) +-#define TCC0_PERBUF _SFR_MEM16(0x0836) +-#define TCC0_CCABUF _SFR_MEM16(0x0838) +-#define TCC0_CCBBUF _SFR_MEM16(0x083A) +-#define TCC0_CCCBUF _SFR_MEM16(0x083C) +-#define TCC0_CCDBUF _SFR_MEM16(0x083E) +- +-/* TCC1 - Timer/Counter C1 */ +-#define TCC1_CTRLA _SFR_MEM8(0x0840) +-#define TCC1_CTRLB _SFR_MEM8(0x0841) +-#define TCC1_CTRLC _SFR_MEM8(0x0842) +-#define TCC1_CTRLD _SFR_MEM8(0x0843) +-#define TCC1_CTRLE _SFR_MEM8(0x0844) +-#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +-#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +-#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +-#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +-#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +-#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +-#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +-#define TCC1_TEMP _SFR_MEM8(0x084F) +-#define TCC1_CNT _SFR_MEM16(0x0860) +-#define TCC1_PER _SFR_MEM16(0x0866) +-#define TCC1_CCA _SFR_MEM16(0x0868) +-#define TCC1_CCB _SFR_MEM16(0x086A) +-#define TCC1_PERBUF _SFR_MEM16(0x0876) +-#define TCC1_CCABUF _SFR_MEM16(0x0878) +-#define TCC1_CCBBUF _SFR_MEM16(0x087A) +- +-/* AWEXC - Advanced Waveform Extension C */ +-#define AWEXC_CTRL _SFR_MEM8(0x0880) +-#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +-#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +-#define AWEXC_STATUS _SFR_MEM8(0x0884) +-#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +-#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +-#define AWEXC_DTLS _SFR_MEM8(0x0888) +-#define AWEXC_DTHS _SFR_MEM8(0x0889) +-#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +-#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +-#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) +- +-/* HIRESC - High-Resolution Extension C */ +-#define HIRESC_CTRLA _SFR_MEM8(0x0890) +- +-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +-#define USARTC0_DATA _SFR_MEM8(0x08A0) +-#define USARTC0_STATUS _SFR_MEM8(0x08A1) +-#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +-#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +-#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +-#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +-#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) +- +-/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ +-#define USARTC1_DATA _SFR_MEM8(0x08B0) +-#define USARTC1_STATUS _SFR_MEM8(0x08B1) +-#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +-#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +-#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +-#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +-#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) +- +-/* SPIC - Serial Peripheral Interface C */ +-#define SPIC_CTRL _SFR_MEM8(0x08C0) +-#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +-#define SPIC_STATUS _SFR_MEM8(0x08C2) +-#define SPIC_DATA _SFR_MEM8(0x08C3) +- +-/* IRCOM - IR Communication Module */ +-#define IRCOM_CTRL _SFR_MEM8(0x08F8) +-#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +-#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) +- +-/* TCD0 - Timer/Counter D0 */ +-#define TCD0_CTRLA _SFR_MEM8(0x0900) +-#define TCD0_CTRLB _SFR_MEM8(0x0901) +-#define TCD0_CTRLC _SFR_MEM8(0x0902) +-#define TCD0_CTRLD _SFR_MEM8(0x0903) +-#define TCD0_CTRLE _SFR_MEM8(0x0904) +-#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +-#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +-#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +-#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +-#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +-#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +-#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +-#define TCD0_TEMP _SFR_MEM8(0x090F) +-#define TCD0_CNT _SFR_MEM16(0x0920) +-#define TCD0_PER _SFR_MEM16(0x0926) +-#define TCD0_CCA _SFR_MEM16(0x0928) +-#define TCD0_CCB _SFR_MEM16(0x092A) +-#define TCD0_CCC _SFR_MEM16(0x092C) +-#define TCD0_CCD _SFR_MEM16(0x092E) +-#define TCD0_PERBUF _SFR_MEM16(0x0936) +-#define TCD0_CCABUF _SFR_MEM16(0x0938) +-#define TCD0_CCBBUF _SFR_MEM16(0x093A) +-#define TCD0_CCCBUF _SFR_MEM16(0x093C) +-#define TCD0_CCDBUF _SFR_MEM16(0x093E) +- +-/* TCD1 - Timer/Counter D1 */ +-#define TCD1_CTRLA _SFR_MEM8(0x0940) +-#define TCD1_CTRLB _SFR_MEM8(0x0941) +-#define TCD1_CTRLC _SFR_MEM8(0x0942) +-#define TCD1_CTRLD _SFR_MEM8(0x0943) +-#define TCD1_CTRLE _SFR_MEM8(0x0944) +-#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +-#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +-#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +-#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +-#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +-#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +-#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +-#define TCD1_TEMP _SFR_MEM8(0x094F) +-#define TCD1_CNT _SFR_MEM16(0x0960) +-#define TCD1_PER _SFR_MEM16(0x0966) +-#define TCD1_CCA _SFR_MEM16(0x0968) +-#define TCD1_CCB _SFR_MEM16(0x096A) +-#define TCD1_PERBUF _SFR_MEM16(0x0976) +-#define TCD1_CCABUF _SFR_MEM16(0x0978) +-#define TCD1_CCBBUF _SFR_MEM16(0x097A) +- +-/* HIRESD - High-Resolution Extension D */ +-#define HIRESD_CTRLA _SFR_MEM8(0x0990) +- +-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +-#define USARTD0_DATA _SFR_MEM8(0x09A0) +-#define USARTD0_STATUS _SFR_MEM8(0x09A1) +-#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +-#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +-#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +-#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +-#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) +- +-/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ +-#define USARTD1_DATA _SFR_MEM8(0x09B0) +-#define USARTD1_STATUS _SFR_MEM8(0x09B1) +-#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +-#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +-#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +-#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +-#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) +- +-/* SPID - Serial Peripheral Interface D */ +-#define SPID_CTRL _SFR_MEM8(0x09C0) +-#define SPID_INTCTRL _SFR_MEM8(0x09C1) +-#define SPID_STATUS _SFR_MEM8(0x09C2) +-#define SPID_DATA _SFR_MEM8(0x09C3) +- +-/* TCE0 - Timer/Counter E0 */ +-#define TCE0_CTRLA _SFR_MEM8(0x0A00) +-#define TCE0_CTRLB _SFR_MEM8(0x0A01) +-#define TCE0_CTRLC _SFR_MEM8(0x0A02) +-#define TCE0_CTRLD _SFR_MEM8(0x0A03) +-#define TCE0_CTRLE _SFR_MEM8(0x0A04) +-#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +-#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +-#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +-#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +-#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +-#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +-#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +-#define TCE0_TEMP _SFR_MEM8(0x0A0F) +-#define TCE0_CNT _SFR_MEM16(0x0A20) +-#define TCE0_PER _SFR_MEM16(0x0A26) +-#define TCE0_CCA _SFR_MEM16(0x0A28) +-#define TCE0_CCB _SFR_MEM16(0x0A2A) +-#define TCE0_CCC _SFR_MEM16(0x0A2C) +-#define TCE0_CCD _SFR_MEM16(0x0A2E) +-#define TCE0_PERBUF _SFR_MEM16(0x0A36) +-#define TCE0_CCABUF _SFR_MEM16(0x0A38) +-#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +-#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +-#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) +- +-/* HIRESE - High-Resolution Extension E */ +-#define HIRESE_CTRLA _SFR_MEM8(0x0A90) +- +-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +-#define USARTE0_DATA _SFR_MEM8(0x0AA0) +-#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +-#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +-#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +-#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +-#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +-#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) +- +- +- +-/*================== Bitfield Definitions ================== */ +- +-/* XOCD - On-Chip Debug System */ +-/* OCD.OCDR1 bit masks and bit positions */ +-#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +-#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ +- +- +-/* CPU - CPU */ +-/* CPU.CCP bit masks and bit positions */ +-#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +-#define CPU_CCP_gp 0 /* CCP signature group position. */ +-#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +-#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +-#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +-#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +-#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +-#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +-#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +-#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +-#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +-#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +-#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +-#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +-#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +-#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +-#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +-#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ +- +- +-/* CPU.SREG bit masks and bit positions */ +-#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +-#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ +- +-#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +-#define CPU_T_bp 6 /* Transfer Bit bit position. */ +- +-#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +-#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +- +-#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +-#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +- +-#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +-#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +- +-#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +-#define CPU_N_bp 2 /* Negative Flag bit position. */ +- +-#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +-#define CPU_Z_bp 1 /* Zero Flag bit position. */ +- +-#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +-#define CPU_C_bp 0 /* Carry Flag bit position. */ +- +- +-/* CLK - Clock System */ +-/* CLK.CTRL bit masks and bit positions */ +-#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +-#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +-#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +-#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +-#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +-#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +-#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +-#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ +- +- +-/* CLK.PSCTRL bit masks and bit positions */ +-#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +-#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +-#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +-#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +-#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +-#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +-#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +-#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +-#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +-#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +-#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +-#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ +- +-#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +-#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +-#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +-#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +-#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +-#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ +- +- +-/* CLK.LOCK bit masks and bit positions */ +-#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +-#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ +- +- +-/* CLK.RTCCTRL bit masks and bit positions */ +-#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +-#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +-#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +-#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +-#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +-#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +-#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +-#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ +- +-#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +-#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ +- +- +-/* PR.PRGEN bit masks and bit positions */ +-#define PR_AES_bm 0x10 /* AES bit mask. */ +-#define PR_AES_bp 4 /* AES bit position. */ +- +-#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +-#define PR_EBI_bp 3 /* External Bus Interface bit position. */ +- +-#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +-#define PR_RTC_bp 2 /* Real-time Counter bit position. */ +- +-#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +-#define PR_EVSYS_bp 1 /* Event System bit position. */ +- +-#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +-#define PR_DMA_bp 0 /* DMA-Controller bit position. */ +- +- +-/* PR.PRPA bit masks and bit positions */ +-#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +-#define PR_DAC_bp 2 /* Port A DAC bit position. */ +- +-#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +-#define PR_ADC_bp 1 /* Port A ADC bit position. */ +- +-#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +-#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ +- +- +-/* PR.PRPB bit masks and bit positions */ +-/* PR_DAC_bm Predefined. */ +-/* PR_DAC_bp Predefined. */ +- +-/* PR_ADC_bm Predefined. */ +-/* PR_ADC_bp Predefined. */ +- +-/* PR_AC_bm Predefined. */ +-/* PR_AC_bp Predefined. */ +- +- +-/* PR.PRPC bit masks and bit positions */ +-#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +-#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ +- +-#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +-#define PR_USART1_bp 5 /* Port C USART1 bit position. */ +- +-#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +-#define PR_USART0_bp 4 /* Port C USART0 bit position. */ +- +-#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +-#define PR_SPI_bp 3 /* Port C SPI bit position. */ +- +-#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +-#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ +- +-#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +-#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ +- +-#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +-#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ +- +- +-/* PR.PRPD bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* PR.PRPE bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* PR.PRPF bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* SLEEP - Sleep Controller */ +-/* SLEEP.CTRL bit masks and bit positions */ +-#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +-#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +-#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +-#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +-#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +-#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +-#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +-#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ +- +-#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +-#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ +- +- +-/* OSC - Oscillator */ +-/* OSC.CTRL bit masks and bit positions */ +-#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +-#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ +- +-#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +-#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ +- +-#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ +- +- +-/* OSC.STATUS bit masks and bit positions */ +-#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +-#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ +- +-#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +-#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ +- +-#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ +- +- +-/* OSC.XOSCCTRL bit masks and bit positions */ +-#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +-#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +-#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +-#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +-#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +-#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ +- +-#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +-#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ +- +-#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +-#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +-#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +-#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +-#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +-#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +-#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +-#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +-#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +-#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +- +- +-/* OSC.XOSCFAIL bit masks and bit positions */ +-#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +-#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ +- +-#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +-#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ +- +- +-/* OSC.PLLCTRL bit masks and bit positions */ +-#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +-#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +-#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +-#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +-#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +-#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ +- +-#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +-#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +-#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +-#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +-#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +-#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +-#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +-#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +-#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +-#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +-#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +-#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ +- +- +-/* OSC.DFLLCTRL bit masks and bit positions */ +-#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +-#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ +- +-#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +-#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ +- +- +-/* DFLL - DFLL */ +-/* DFLL.CTRL bit masks and bit positions */ +-#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +-#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ +- +- +-/* DFLL.CALA bit masks and bit positions */ +-#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +-#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +-#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +-#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +-#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +-#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +-#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +-#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +-#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +-#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +-#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +-#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +-#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +-#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +-#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +-#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ +- +- +-/* DFLL.CALB bit masks and bit positions */ +-#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +-#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +-#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +-#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +-#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +-#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +-#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +-#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +-#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +-#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +-#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +-#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +-#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +-#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ +- +- +-/* RST - Reset */ +-/* RST.STATUS bit masks and bit positions */ +-#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +-#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ +- +-#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +-#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ +- +-#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +-#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ +- +-#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +-#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ +- +-#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +-#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ +- +-#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +-#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ +- +-#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +-#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ +- +- +-/* RST.CTRL bit masks and bit positions */ +-#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +-#define RST_SWRST_bp 0 /* Software Reset bit position. */ +- +- +-/* WDT - Watch-Dog Timer */ +-/* WDT.CTRL bit masks and bit positions */ +-#define WDT_PER_gm 0x3C /* Period group mask. */ +-#define WDT_PER_gp 2 /* Period group position. */ +-#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +-#define WDT_PER0_bp 2 /* Period bit 0 position. */ +-#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +-#define WDT_PER1_bp 3 /* Period bit 1 position. */ +-#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +-#define WDT_PER2_bp 4 /* Period bit 2 position. */ +-#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +-#define WDT_PER3_bp 5 /* Period bit 3 position. */ +- +-#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +-#define WDT_ENABLE_bp 1 /* Enable bit position. */ +- +-#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +-#define WDT_CEN_bp 0 /* Change Enable bit position. */ +- +- +-/* WDT.WINCTRL bit masks and bit positions */ +-#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +-#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +-#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +-#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +-#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +-#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +-#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +-#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +-#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +-#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ +- +-#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +-#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ +- +-#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +-#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ +- +- +-/* WDT.STATUS bit masks and bit positions */ +-#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +-#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +- +- +-/* MCU - MCU Control */ +-/* MCU.MCUCR bit masks and bit positions */ +-#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +-#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ +- +- +-/* MCU.EVSYSLOCK bit masks and bit positions */ +-#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +-#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ +- +-#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +-#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ +- +- +-/* MCU.AWEXLOCK bit masks and bit positions */ +-#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +-#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ +- +-#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +-#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ +- +- +-/* PMIC - Programmable Multi-level Interrupt Controller */ +-/* PMIC.STATUS bit masks and bit positions */ +-#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +-#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ +- +-#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +-#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ +- +-#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +-#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ +- +-#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +-#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ +- +- +-/* PMIC.CTRL bit masks and bit positions */ +-#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +-#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ +- +-#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +-#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ +- +-#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +-#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ +- +-#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +-#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ +- +-#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +-#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ +- +- +-/* DMA - DMA Controller */ +-/* DMA_CH.CTRLA bit masks and bit positions */ +-#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +-#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ +- +-#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +-#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ +- +-#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +-#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ +- +-#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +-#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ +- +-#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +-#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ +- +-#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +-#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +-#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +-#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +-#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +-#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ +- +- +-/* DMA_CH.CTRLB bit masks and bit positions */ +-#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +-#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ +- +-#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +-#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ +- +-#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +-#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ +- +-#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +-#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +-#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +-#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +-#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +-#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ +- +-#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +-#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +-#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +-#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +-#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +-#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ +- +- +-/* DMA_CH.ADDRCTRL bit masks and bit positions */ +-#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +-#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +-#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +-#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +-#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +-#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ +- +-#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +-#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +-#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +-#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +-#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +-#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ +- +-#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +-#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +-#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +-#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +-#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +-#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ +- +-#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +-#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +-#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +-#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +-#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +-#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ +- +- +-/* DMA_CH.TRIGSRC bit masks and bit positions */ +-#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +-#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +-#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +-#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +-#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +-#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +-#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +-#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +-#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +-#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +-#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +-#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +-#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +-#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +-#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +-#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +-#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +-#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ +- +- +-/* DMA.CTRL bit masks and bit positions */ +-#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +-#define DMA_ENABLE_bp 7 /* Enable bit position. */ +- +-#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +-#define DMA_RESET_bp 6 /* Software Reset bit position. */ +- +-#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +-#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +-#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +-#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +-#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +-#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ +- +-#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +-#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +-#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +-#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +-#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +-#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ +- +- +-/* DMA.INTFLAGS bit masks and bit positions */ +-#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ +- +- +-/* DMA.STATUS bit masks and bit positions */ +-#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +-#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ +- +-#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +-#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ +- +-#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +-#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ +- +-#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +-#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ +- +-#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +-#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ +- +-#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +-#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ +- +-#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +-#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ +- +-#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +-#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ +- +- +-/* EVSYS - Event System */ +-/* EVSYS.CH0MUX bit masks and bit positions */ +-#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +-#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +-#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +-#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +-#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +-#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +-#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +-#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +-#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +-#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +-#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +-#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +-#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +-#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +-#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +-#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +-#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +-#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ +- +- +-/* EVSYS.CH1MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH2MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH3MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH4MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH5MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH6MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH7MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH0CTRL bit masks and bit positions */ +-#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +-#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +-#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +-#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +-#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +-#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ +- +-#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +-#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ +- +-#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +-#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ +- +-#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +-#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +-#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +-#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +-#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +-#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +-#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +-#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ +- +- +-/* EVSYS.CH1CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH2CTRL bit masks and bit positions */ +-/* EVSYS_QDIRM_gm Predefined. */ +-/* EVSYS_QDIRM_gp Predefined. */ +-/* EVSYS_QDIRM0_bm Predefined. */ +-/* EVSYS_QDIRM0_bp Predefined. */ +-/* EVSYS_QDIRM1_bm Predefined. */ +-/* EVSYS_QDIRM1_bp Predefined. */ +- +-/* EVSYS_QDIEN_bm Predefined. */ +-/* EVSYS_QDIEN_bp Predefined. */ +- +-/* EVSYS_QDEN_bm Predefined. */ +-/* EVSYS_QDEN_bp Predefined. */ +- +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH3CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH4CTRL bit masks and bit positions */ +-/* EVSYS_QDIRM_gm Predefined. */ +-/* EVSYS_QDIRM_gp Predefined. */ +-/* EVSYS_QDIRM0_bm Predefined. */ +-/* EVSYS_QDIRM0_bp Predefined. */ +-/* EVSYS_QDIRM1_bm Predefined. */ +-/* EVSYS_QDIRM1_bp Predefined. */ +- +-/* EVSYS_QDIEN_bm Predefined. */ +-/* EVSYS_QDIEN_bp Predefined. */ +- +-/* EVSYS_QDEN_bm Predefined. */ +-/* EVSYS_QDEN_bp Predefined. */ +- +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH5CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH6CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH7CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* NVM - Non Volatile Memory Controller */ +-/* NVM.CMD bit masks and bit positions */ +-#define NVM_CMD_gm 0xFF /* Command group mask. */ +-#define NVM_CMD_gp 0 /* Command group position. */ +-#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +-#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +-#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +-#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +-#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +-#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +-#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +-#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +-#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +-#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +-#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +-#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +-#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +-#define NVM_CMD7_bp 7 /* Command bit 7 position. */ +- +- +-/* NVM.CTRLA bit masks and bit positions */ +-#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +-#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ +- +- +-/* NVM.CTRLB bit masks and bit positions */ +-#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +-#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ +- +-#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +-#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ +- +-#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +-#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ +- +-#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +-#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ +- +- +-/* NVM.INTCTRL bit masks and bit positions */ +-#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +-#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +-#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +-#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +-#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +-#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ +- +-#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +-#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +-#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +-#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +-#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +-#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ +- +- +-/* NVM.STATUS bit masks and bit positions */ +-#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +-#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ +- +-#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +-#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ +- +-#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +-#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ +- +-#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +-#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ +- +- +-/* NVM.LOCKBITS bit masks and bit positions */ +-#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +-#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +-#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ +-#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ +-#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ +-#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ +-#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ +-#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ +-#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ +-#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ +-#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ +-#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ +-#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ +-#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ +-#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ +-#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ +-#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ +-#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ +-#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ +-#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +-#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +-#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +-#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ +- +-#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +-#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +-#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +-#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +-#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ +- +-#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +-#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ +- +-#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +-#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +-#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +-#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +-#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +-#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +-#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +-#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +-#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +-#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +-#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +-#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ +- +-#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +-#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ +- +- +-/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +-#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +-#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +-#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +-#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +-#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +-#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ +- +-#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +-#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ +- +-#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +-#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +-#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +-#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +-#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +-#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +-#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +-#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +- +- +-/* AC - Analog Comparator */ +-/* AC.AC0CTRL bit masks and bit positions */ +-#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +-#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +-#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +-#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +-#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +-#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ +- +-#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +-#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +-#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +-#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +-#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +-#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ +- +-#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +-#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ +- +-#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +-#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +-#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +-#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +-#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +-#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +- +-#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define AC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* AC.AC1CTRL bit masks and bit positions */ +-/* AC_INTMODE_gm Predefined. */ +-/* AC_INTMODE_gp Predefined. */ +-/* AC_INTMODE0_bm Predefined. */ +-/* AC_INTMODE0_bp Predefined. */ +-/* AC_INTMODE1_bm Predefined. */ +-/* AC_INTMODE1_bp Predefined. */ +- +-/* AC_INTLVL_gm Predefined. */ +-/* AC_INTLVL_gp Predefined. */ +-/* AC_INTLVL0_bm Predefined. */ +-/* AC_INTLVL0_bp Predefined. */ +-/* AC_INTLVL1_bm Predefined. */ +-/* AC_INTLVL1_bp Predefined. */ +- +-/* AC_HSMODE_bm Predefined. */ +-/* AC_HSMODE_bp Predefined. */ +- +-/* AC_HYSMODE_gm Predefined. */ +-/* AC_HYSMODE_gp Predefined. */ +-/* AC_HYSMODE0_bm Predefined. */ +-/* AC_HYSMODE0_bp Predefined. */ +-/* AC_HYSMODE1_bm Predefined. */ +-/* AC_HYSMODE1_bp Predefined. */ +- +-/* AC_ENABLE_bm Predefined. */ +-/* AC_ENABLE_bp Predefined. */ +- +- +-/* AC.AC0MUXCTRL bit masks and bit positions */ +-#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +-#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +-#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +-#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +-#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +-#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +-#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +-#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ +- +-#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +-#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +-#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +-#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +-#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +-#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +-#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +-#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ +- +- +-/* AC.AC1MUXCTRL bit masks and bit positions */ +-/* AC_MUXPOS_gm Predefined. */ +-/* AC_MUXPOS_gp Predefined. */ +-/* AC_MUXPOS0_bm Predefined. */ +-/* AC_MUXPOS0_bp Predefined. */ +-/* AC_MUXPOS1_bm Predefined. */ +-/* AC_MUXPOS1_bp Predefined. */ +-/* AC_MUXPOS2_bm Predefined. */ +-/* AC_MUXPOS2_bp Predefined. */ +- +-/* AC_MUXNEG_gm Predefined. */ +-/* AC_MUXNEG_gp Predefined. */ +-/* AC_MUXNEG0_bm Predefined. */ +-/* AC_MUXNEG0_bp Predefined. */ +-/* AC_MUXNEG1_bm Predefined. */ +-/* AC_MUXNEG1_bp Predefined. */ +-/* AC_MUXNEG2_bm Predefined. */ +-/* AC_MUXNEG2_bp Predefined. */ +- +- +-/* AC.CTRLA bit masks and bit positions */ +-#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +-#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ +- +- +-/* AC.CTRLB bit masks and bit positions */ +-#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +-#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +-#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +-#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +-#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +-#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +-#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +-#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +-#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +-#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +-#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +-#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +-#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +-#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ +- +- +-/* AC.WINCTRL bit masks and bit positions */ +-#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +-#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ +- +-#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +-#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +-#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +-#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +-#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +-#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ +- +-#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +-#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +-#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +-#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +-#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +-#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ +- +- +-/* AC.STATUS bit masks and bit positions */ +-#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +-#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +-#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +-#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +-#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +-#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ +- +-#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +-#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ +- +-#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +-#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ +- +-#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +-#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ +- +-#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +-#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ +- +-#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +-#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ +- +- +-/* ADC - Analog/Digital Converter */ +-/* ADC_CH.CTRL bit masks and bit positions */ +-#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +-#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ +- +-#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +-#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +-#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +-#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +-#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +-#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +-#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +-#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ +- +-#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +-#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +-#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +-#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +-#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +-#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ +- +- +-/* ADC_CH.MUXCTRL bit masks and bit positions */ +-#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +-#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +-#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +-#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +-#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +-#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +-#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +-#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +-#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +-#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ +- +-#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +-#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +-#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +-#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +-#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +-#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +-#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +-#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +-#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +-#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ +- +-#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +-#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +-#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +-#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +-#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +-#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ +- +- +-/* ADC_CH.INTCTRL bit masks and bit positions */ +-#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +-#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +-#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +-#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +-#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +-#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ +- +-#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +-#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +-#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +-#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +-#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +-#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ +- +- +-/* ADC_CH.INTFLAGS bit masks and bit positions */ +-#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +-#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ +- +- +-/* ADC.CTRLA bit masks and bit positions */ +-#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +-#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +-#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +-#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +-#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +-#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ +- +-#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +-#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ +- +-#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +-#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ +- +-#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +-#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ +- +-#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +-#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ +- +-#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +-#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ +- +-#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +-#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ +- +- +-/* ADC.CTRLB bit masks and bit positions */ +-#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +-#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ +- +-#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +-#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ +- +-#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +-#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +-#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +-#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +-#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +-#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ +- +- +-/* ADC.REFCTRL bit masks and bit positions */ +-#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +-#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +-#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +-#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +-#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +-#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +- +-#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +-#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ +- +-#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +-#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ +- +- +-/* ADC.EVCTRL bit masks and bit positions */ +-#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +-#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +-#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +-#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +-#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +-#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ +- +-#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +-#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +-#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +-#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +-#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +-#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +-#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +-#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ +- +-#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +-#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +-#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +-#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +-#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +-#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +-#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +-#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ +- +- +-/* ADC.PRESCALER bit masks and bit positions */ +-#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +-#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +-#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +-#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +-#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +-#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +-#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +-#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ +- +- +-/* ADC.INTFLAGS bit masks and bit positions */ +-#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +-#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ +- +-#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +-#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ +- +-#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +-#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ +- +-#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +-#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ +- +- +-/* DAC - Digital/Analog Converter */ +-/* DAC.CTRLA bit masks and bit positions */ +-#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +-#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ +- +-#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +-#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ +- +-#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +-#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ +- +-#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +-#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ +- +-#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define DAC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* DAC.CTRLB bit masks and bit positions */ +-#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +-#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +-#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +-#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +-#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +-#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ +- +-#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +-#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ +- +-#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +-#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ +- +- +-/* DAC.CTRLC bit masks and bit positions */ +-#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +-#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +-#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +-#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +-#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +-#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ +- +-#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +-#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ +- +- +-/* DAC.EVCTRL bit masks and bit positions */ +-#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +-#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +-#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +-#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +-#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +-#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +-#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +-#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ +- +- +-/* DAC.TIMCTRL bit masks and bit positions */ +-#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ +-#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ +-#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ +-#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ +-#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ +-#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ +-#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ +-#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ +- +-#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ +-#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ +-#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ +-#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ +-#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ +-#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ +-#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ +-#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ +-#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ +-#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ +- +- +-/* DAC.STATUS bit masks and bit positions */ +-#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +-#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ +- +-#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +-#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ +- +- +-/* RTC - Real-Time Clounter */ +-/* RTC.CTRL bit masks and bit positions */ +-#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +-#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +-#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +-#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +-#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +-#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +-#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +-#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ +- +- +-/* RTC.STATUS bit masks and bit positions */ +-#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +-#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ +- +- +-/* RTC.INTCTRL bit masks and bit positions */ +-#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +-#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +-#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +-#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +-#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +-#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ +- +-#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +-#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +-#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +-#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +-#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +-#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ +- +- +-/* RTC.INTFLAGS bit masks and bit positions */ +-#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +-#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ +- +-#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* EBI - External Bus Interface */ +-/* EBI_CS.CTRLA bit masks and bit positions */ +-#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +-#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +-#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +-#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +-#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +-#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +-#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +-#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +-#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +-#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +-#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +-#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ +- +-#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +-#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +-#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +-#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +-#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +-#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ +- +- +-/* EBI_CS.CTRLB bit masks and bit positions */ +-#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +-#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +-#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +-#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +-#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +-#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +-#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +-#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ +- +-#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +-#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ +- +-#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +-#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ +- +-#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +-#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +-#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +-#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +-#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +-#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ +- +- +-/* EBI.CTRL bit masks and bit positions */ +-#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +-#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +-#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +-#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +-#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +-#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ +- +-#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +-#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +-#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +-#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +-#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +-#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ +- +-#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +-#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +-#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +-#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +-#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +-#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ +- +-#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +-#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +-#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +-#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +-#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +-#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLA bit masks and bit positions */ +-#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +-#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ +- +-#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +-#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ +- +-#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +-#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +-#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +-#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +-#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +-#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLB bit masks and bit positions */ +-#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +-#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +-#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +-#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +-#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +-#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ +- +-#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +-#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +-#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +-#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +-#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +-#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +-#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +-#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ +- +-#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +-#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +-#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +-#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +-#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +-#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +-#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +-#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ +- +- +-/* EBI.SDRAMCTRLC bit masks and bit positions */ +-#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +-#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +-#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +-#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +-#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +-#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ +- +-#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +-#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +-#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +-#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +-#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +-#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +-#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +-#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ +- +-#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +-#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +-#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +-#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +-#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +-#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +-#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +-#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ +- +- +-/* TWI - Two-Wire Interface */ +-/* TWI_MASTER.CTRLA bit masks and bit positions */ +-#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +-#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ +- +-#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +-#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ +- +-#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +-#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ +- +- +-/* TWI_MASTER.CTRLB bit masks and bit positions */ +-#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +-#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +-#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +-#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +-#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +-#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +- +-#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +-#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ +- +-#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_MASTER.CTRLC bit masks and bit positions */ +-#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +-#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_MASTER.STATUS bit masks and bit positions */ +-#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +-#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ +- +-#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +-#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ +- +-#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +-#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +- +-#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +-#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +-#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +-#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +-#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +-#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +- +- +-/* TWI_SLAVE.CTRLA bit masks and bit positions */ +-#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +-#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +-#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ +- +-#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +-#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ +- +-#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_SLAVE.CTRLB bit masks and bit positions */ +-#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +-#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_SLAVE.STATUS bit masks and bit positions */ +-#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +-#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +-#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +-#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ +- +-#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +-#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ +- +-#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +-#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ +- +- +-/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +-#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +-#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +-#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +-#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +-#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +-#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +-#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +-#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +-#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +-#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +-#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +-#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +-#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +-#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +-#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +-#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ +- +-#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +-#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ +- +- +-/* TWI.CTRL bit masks and bit positions */ +-#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +-#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ +- +-#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +-#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ +- +- +-/* PORT - Port Configuration */ +-/* PORTCFG.VPCTRLA bit masks and bit positions */ +-#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +-#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +-#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +-#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +-#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +-#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +-#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +-#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +-#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +-#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ +- +-#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +-#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +-#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +-#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +-#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +-#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +-#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +-#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +-#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +-#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ +- +- +-/* PORTCFG.VPCTRLB bit masks and bit positions */ +-#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +-#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +-#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +-#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +-#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +-#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +-#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +-#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +-#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +-#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ +- +-#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +-#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +-#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +-#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +-#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +-#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +-#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +-#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +-#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +-#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ +- +- +-/* PORTCFG.CLKEVOUT bit masks and bit positions */ +-#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +-#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +-#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +-#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +-#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +-#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ +- +-#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +-#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +-#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +-#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +-#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +-#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ +- +- +-/* VPORT.INTFLAGS bit masks and bit positions */ +-#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.INTCTRL bit masks and bit positions */ +-#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +-#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +-#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +-#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +-#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +-#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ +- +-#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +-#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +-#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +-#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +-#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +-#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ +- +- +-/* PORT.INTFLAGS bit masks and bit positions */ +-#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.PIN0CTRL bit masks and bit positions */ +-#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +-#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ +- +-#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +-#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ +- +-#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +-#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +-#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +-#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +-#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +-#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +-#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +-#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ +- +-#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +-#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +-#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +-#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +-#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +-#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +-#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +-#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +- +- +-/* PORT.PIN1CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN2CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN3CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN4CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN5CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN6CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN7CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* TC - 16-bit Timer/Counter With PWM */ +-/* TC0.CTRLA bit masks and bit positions */ +-#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC0.CTRLB bit masks and bit positions */ +-#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +-#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ +- +-#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +-#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ +- +-#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC0.CTRLC bit masks and bit positions */ +-#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +-#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ +- +-#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +-#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ +- +-#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC0.CTRLD bit masks and bit positions */ +-#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC0_EVACT_gp 5 /* Event Action group position. */ +-#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC0.CTRLE bit masks and bit positions */ +-#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +-#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ +- +-#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC0.INTCTRLA bit masks and bit positions */ +-#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC0.INTCTRLB bit masks and bit positions */ +-#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +-#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +-#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +-#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +-#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +-#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ +- +-#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +-#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +-#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +-#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +-#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +-#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ +- +-#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC0.CTRLFCLR bit masks and bit positions */ +-#define TC0_CMD_gm 0x0C /* Command group mask. */ +-#define TC0_CMD_gp 2 /* Command group position. */ +-#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC0_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC0_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC0_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC0.CTRLFSET bit masks and bit positions */ +-/* TC0_CMD_gm Predefined. */ +-/* TC0_CMD_gp Predefined. */ +-/* TC0_CMD0_bm Predefined. */ +-/* TC0_CMD0_bp Predefined. */ +-/* TC0_CMD1_bm Predefined. */ +-/* TC0_CMD1_bp Predefined. */ +- +-/* TC0_LUPD_bm Predefined. */ +-/* TC0_LUPD_bp Predefined. */ +- +-/* TC0_DIR_bm Predefined. */ +-/* TC0_DIR_bp Predefined. */ +- +- +-/* TC0.CTRLGCLR bit masks and bit positions */ +-#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +-#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ +- +-#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +-#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ +- +-#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC0.CTRLGSET bit masks and bit positions */ +-/* TC0_CCDBV_bm Predefined. */ +-/* TC0_CCDBV_bp Predefined. */ +- +-/* TC0_CCCBV_bm Predefined. */ +-/* TC0_CCCBV_bp Predefined. */ +- +-/* TC0_CCBBV_bm Predefined. */ +-/* TC0_CCBBV_bp Predefined. */ +- +-/* TC0_CCABV_bm Predefined. */ +-/* TC0_CCABV_bp Predefined. */ +- +-/* TC0_PERBV_bm Predefined. */ +-/* TC0_PERBV_bp Predefined. */ +- +- +-/* TC0.INTFLAGS bit masks and bit positions */ +-#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +-#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ +- +-#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +-#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ +- +-#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* TC1.CTRLA bit masks and bit positions */ +-#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC1.CTRLB bit masks and bit positions */ +-#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC1.CTRLC bit masks and bit positions */ +-#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC1.CTRLD bit masks and bit positions */ +-#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC1_EVACT_gp 5 /* Event Action group position. */ +-#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC1.CTRLE bit masks and bit positions */ +-#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +-#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ +- +-#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC1.INTCTRLA bit masks and bit positions */ +-#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC1.INTCTRLB bit masks and bit positions */ +-#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC1.CTRLFCLR bit masks and bit positions */ +-#define TC1_CMD_gm 0x0C /* Command group mask. */ +-#define TC1_CMD_gp 2 /* Command group position. */ +-#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC1_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC1_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC1_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC1.CTRLFSET bit masks and bit positions */ +-/* TC1_CMD_gm Predefined. */ +-/* TC1_CMD_gp Predefined. */ +-/* TC1_CMD0_bm Predefined. */ +-/* TC1_CMD0_bp Predefined. */ +-/* TC1_CMD1_bm Predefined. */ +-/* TC1_CMD1_bp Predefined. */ +- +-/* TC1_LUPD_bm Predefined. */ +-/* TC1_LUPD_bp Predefined. */ +- +-/* TC1_DIR_bm Predefined. */ +-/* TC1_DIR_bp Predefined. */ +- +- +-/* TC1.CTRLGCLR bit masks and bit positions */ +-#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC1.CTRLGSET bit masks and bit positions */ +-/* TC1_CCBBV_bm Predefined. */ +-/* TC1_CCBBV_bp Predefined. */ +- +-/* TC1_CCABV_bm Predefined. */ +-/* TC1_CCABV_bp Predefined. */ +- +-/* TC1_PERBV_bm Predefined. */ +-/* TC1_PERBV_bp Predefined. */ +- +- +-/* TC1.INTFLAGS bit masks and bit positions */ +-#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* AWEX.CTRL bit masks and bit positions */ +-#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +-#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ +- +-#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +-#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ +- +-#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +-#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ +- +-#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +-#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ +- +-#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +-#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ +- +-#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +-#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ +- +- +-/* AWEX.FDCTRL bit masks and bit positions */ +-#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +-#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ +- +-#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +-#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ +- +-#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +-#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +-#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +-#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +-#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +-#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ +- +- +-/* AWEX.STATUS bit masks and bit positions */ +-#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +-#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ +- +-#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +-#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ +- +-#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +-#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ +- +- +-/* HIRES.CTRL bit masks and bit positions */ +-#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +-#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +-#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +-#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +-#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +-#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ +- +- +-/* USART - Universal Asynchronous Receiver-Transmitter */ +-/* USART.STATUS bit masks and bit positions */ +-#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +-#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ +- +-#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +-#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +- +-#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +-#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +- +-#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +-#define USART_FERR_bp 4 /* Frame Error bit position. */ +- +-#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +-#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ +- +-#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +-#define USART_PERR_bp 2 /* Parity Error bit position. */ +- +-#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +-#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ +- +- +-/* USART.CTRLA bit masks and bit positions */ +-#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +-#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +-#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +-#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +-#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +-#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ +- +-#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +-#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +-#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +-#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +-#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +-#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ +- +-#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +-#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +-#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +-#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +-#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +-#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ +- +- +-/* USART.CTRLB bit masks and bit positions */ +-#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +-#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ +- +-#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +-#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ +- +-#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +-#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ +- +-#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +-#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ +- +-#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +-#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ +- +- +-/* USART.CTRLC bit masks and bit positions */ +-#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +-#define USART_CMODE_gp 6 /* Communication Mode group position. */ +-#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +-#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +-#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +-#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ +- +-#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +-#define USART_PMODE_gp 4 /* Parity Mode group position. */ +-#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +-#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +-#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +-#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +- +-#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +-#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +- +-#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +-#define USART_CHSIZE_gp 0 /* Character Size group position. */ +-#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +-#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +-#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +-#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +-#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +-#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +- +- +-/* USART.BAUDCTRLA bit masks and bit positions */ +-#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +-#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +-#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +-#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +-#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +-#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +-#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +-#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +-#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +-#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +-#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +-#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +-#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +-#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +-#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +-#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +-#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +-#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ +- +- +-/* USART.BAUDCTRLB bit masks and bit positions */ +-#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +-#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +-#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +-#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +-#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +-#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +-#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +-#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +-#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +-#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ +- +-/* USART_BSEL_gm Predefined. */ +-/* USART_BSEL_gp Predefined. */ +-/* USART_BSEL0_bm Predefined. */ +-/* USART_BSEL0_bp Predefined. */ +-/* USART_BSEL1_bm Predefined. */ +-/* USART_BSEL1_bp Predefined. */ +-/* USART_BSEL2_bm Predefined. */ +-/* USART_BSEL2_bp Predefined. */ +-/* USART_BSEL3_bm Predefined. */ +-/* USART_BSEL3_bp Predefined. */ +- +- +-/* SPI - Serial Peripheral Interface */ +-/* SPI.CTRL bit masks and bit positions */ +-#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +-#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ +- +-#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +-#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ +- +-#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +-#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ +- +-#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +-#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ +- +-#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +-#define SPI_MODE_gp 2 /* SPI Mode group position. */ +-#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +-#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +-#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +-#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ +- +-#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +-#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +-#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +-#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +-#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +-#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ +- +- +-/* SPI.INTCTRL bit masks and bit positions */ +-#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +-#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +-/* SPI.STATUS bit masks and bit positions */ +-#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +-#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ +- +-#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +-#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +- +- +-/* IRCOM - IR Communication Module */ +-/* IRCOM.CTRL bit masks and bit positions */ +-#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +-#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +-#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +-#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +-#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +-#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +-#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +-#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +-#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +-#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ +- +- +-/* AES - AES Module */ +-/* AES.CTRL bit masks and bit positions */ +-#define AES_START_bm 0x80 /* Start/Run bit mask. */ +-#define AES_START_bp 7 /* Start/Run bit position. */ +- +-#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +-#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ +- +-#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +-#define AES_RESET_bp 5 /* AES Software Reset bit position. */ +- +-#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +-#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ +- +-#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +-#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ +- +- +-/* AES.STATUS bit masks and bit positions */ +-#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +-#define AES_ERROR_bp 7 /* AES Error bit position. */ +- +-#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +-#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ +- +- +-/* AES.INTCTRL bit masks and bit positions */ +-#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +-#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +- +-// Generic Port Pins +- +-#define PIN0_bm 0x01 +-#define PIN0_bp 0 +-#define PIN1_bm 0x02 +-#define PIN1_bp 1 +-#define PIN2_bm 0x04 +-#define PIN2_bp 2 +-#define PIN3_bm 0x08 +-#define PIN3_bp 3 +-#define PIN4_bm 0x10 +-#define PIN4_bp 4 +-#define PIN5_bm 0x20 +-#define PIN5_bp 5 +-#define PIN6_bm 0x40 +-#define PIN6_bp 6 +-#define PIN7_bm 0x80 +-#define PIN7_bp 7 +- +- +-/* ========== Interrupt Vector Definitions ========== */ +-/* Vector 0 is the reset vector */ +- +-/* OSC interrupt vectors */ +-#define OSC_XOSCF_vect_num 1 +-#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ +- +-/* PORTC interrupt vectors */ +-#define PORTC_INT0_vect_num 2 +-#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +-#define PORTC_INT1_vect_num 3 +-#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ +- +-/* PORTR interrupt vectors */ +-#define PORTR_INT0_vect_num 4 +-#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +-#define PORTR_INT1_vect_num 5 +-#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ +- +-/* DMA interrupt vectors */ +-#define DMA_CH0_vect_num 6 +-#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +-#define DMA_CH1_vect_num 7 +-#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +-#define DMA_CH2_vect_num 8 +-#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +-#define DMA_CH3_vect_num 9 +-#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ +- +-/* RTC interrupt vectors */ +-#define RTC_OVF_vect_num 10 +-#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +-#define RTC_COMP_vect_num 11 +-#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ +- +-/* TWIC interrupt vectors */ +-#define TWIC_TWIS_vect_num 12 +-#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +-#define TWIC_TWIM_vect_num 13 +-#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ +- +-/* TCC0 interrupt vectors */ +-#define TCC0_OVF_vect_num 14 +-#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +-#define TCC0_ERR_vect_num 15 +-#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +-#define TCC0_CCA_vect_num 16 +-#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +-#define TCC0_CCB_vect_num 17 +-#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +-#define TCC0_CCC_vect_num 18 +-#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +-#define TCC0_CCD_vect_num 19 +-#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ +- +-/* TCC1 interrupt vectors */ +-#define TCC1_OVF_vect_num 20 +-#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +-#define TCC1_ERR_vect_num 21 +-#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +-#define TCC1_CCA_vect_num 22 +-#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +-#define TCC1_CCB_vect_num 23 +-#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ +- +-/* SPIC interrupt vectors */ +-#define SPIC_INT_vect_num 24 +-#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ +- +-/* USARTC0 interrupt vectors */ +-#define USARTC0_RXC_vect_num 25 +-#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +-#define USARTC0_DRE_vect_num 26 +-#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +-#define USARTC0_TXC_vect_num 27 +-#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ +- +-/* USARTC1 interrupt vectors */ +-#define USARTC1_RXC_vect_num 28 +-#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +-#define USARTC1_DRE_vect_num 29 +-#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +-#define USARTC1_TXC_vect_num 30 +-#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ +- +-/* AES interrupt vectors */ +-#define AES_INT_vect_num 31 +-#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ +- +-/* NVM interrupt vectors */ +-#define NVM_EE_vect_num 32 +-#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +-#define NVM_SPM_vect_num 33 +-#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ +- +-/* PORTB interrupt vectors */ +-#define PORTB_INT0_vect_num 34 +-#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +-#define PORTB_INT1_vect_num 35 +-#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ +- +-/* PORTE interrupt vectors */ +-#define PORTE_INT0_vect_num 43 +-#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +-#define PORTE_INT1_vect_num 44 +-#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ +- +-/* TWIE interrupt vectors */ +-#define TWIE_TWIS_vect_num 45 +-#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +-#define TWIE_TWIM_vect_num 46 +-#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ +- +-/* TCE0 interrupt vectors */ +-#define TCE0_OVF_vect_num 47 +-#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +-#define TCE0_ERR_vect_num 48 +-#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +-#define TCE0_CCA_vect_num 49 +-#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +-#define TCE0_CCB_vect_num 50 +-#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +-#define TCE0_CCC_vect_num 51 +-#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +-#define TCE0_CCD_vect_num 52 +-#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ +- +-/* TCE1 interrupt vectors */ +-#define TCE1_OVF_vect_num 53 +-#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ +-#define TCE1_ERR_vect_num 54 +-#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ +-#define TCE1_CCA_vect_num 55 +-#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ +-#define TCE1_CCB_vect_num 56 +-#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ +- +-/* USARTE0 interrupt vectors */ +-#define USARTE0_RXC_vect_num 58 +-#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +-#define USARTE0_DRE_vect_num 59 +-#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +-#define USARTE0_TXC_vect_num 60 +-#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ +- +-/* PORTD interrupt vectors */ +-#define PORTD_INT0_vect_num 64 +-#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +-#define PORTD_INT1_vect_num 65 +-#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ +- +-/* PORTA interrupt vectors */ +-#define PORTA_INT0_vect_num 66 +-#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +-#define PORTA_INT1_vect_num 67 +-#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ +- +-/* ACA interrupt vectors */ +-#define ACA_AC0_vect_num 68 +-#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +-#define ACA_AC1_vect_num 69 +-#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +-#define ACA_ACW_vect_num 70 +-#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ +- +-/* ADCA interrupt vectors */ +-#define ADCA_CH0_vect_num 71 +-#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +-#define ADCA_CH1_vect_num 72 +-#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +-#define ADCA_CH2_vect_num 73 +-#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +-#define ADCA_CH3_vect_num 74 +-#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ +- +-/* TCD0 interrupt vectors */ +-#define TCD0_OVF_vect_num 77 +-#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +-#define TCD0_ERR_vect_num 78 +-#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +-#define TCD0_CCA_vect_num 79 +-#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +-#define TCD0_CCB_vect_num 80 +-#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +-#define TCD0_CCC_vect_num 81 +-#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +-#define TCD0_CCD_vect_num 82 +-#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ +- +-/* TCD1 interrupt vectors */ +-#define TCD1_OVF_vect_num 83 +-#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +-#define TCD1_ERR_vect_num 84 +-#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +-#define TCD1_CCA_vect_num 85 +-#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +-#define TCD1_CCB_vect_num 86 +-#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ +- +-/* SPID interrupt vectors */ +-#define SPID_INT_vect_num 87 +-#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ +- +-/* USARTD0 interrupt vectors */ +-#define USARTD0_RXC_vect_num 88 +-#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +-#define USARTD0_DRE_vect_num 89 +-#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +-#define USARTD0_TXC_vect_num 90 +-#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ +- +-/* USARTD1 interrupt vectors */ +-#define USARTD1_RXC_vect_num 91 +-#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +-#define USARTD1_DRE_vect_num 92 +-#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +-#define USARTD1_TXC_vect_num 93 +-#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ +- +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (94 * _VECTOR_SIZE) +- +- +-/* ========== Constants ========== */ +- +-#define PROGMEM_START (0x0000) +-#define PROGMEM_SIZE (20480) +-#define PROGMEM_PAGE_SIZE (256) +-#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) +- +-#define APP_SECTION_START (0x0000) +-#define APP_SECTION_SIZE (16384) +-#define APP_SECTION_PAGE_SIZE (256) +-#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) +- +-#define APPTABLE_SECTION_START (0x3000) +-#define APPTABLE_SECTION_SIZE (4096) +-#define APPTABLE_SECTION_PAGE_SIZE (256) +-#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) +- +-#define BOOT_SECTION_START (0x4000) +-#define BOOT_SECTION_SIZE (4096) +-#define BOOT_SECTION_PAGE_SIZE (256) +-#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) +- +-#define DATAMEM_START (0x0000) +-#define DATAMEM_SIZE (10240) +-#define DATAMEM_PAGE_SIZE (0) +-#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) +- +-#define IO_START (0x0000) +-#define IO_SIZE (4096) +-#define IO_PAGE_SIZE (0) +-#define IO_END (IO_START + IO_SIZE - 1) +- +-#define MAPPED_EEPROM_START (0x1000) +-#define MAPPED_EEPROM_SIZE (1024) +-#define MAPPED_EEPROM_PAGE_SIZE (0) +-#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) +- +-#define INTERNAL_SRAM_START (0x2000) +-#define INTERNAL_SRAM_SIZE (2048) +-#define INTERNAL_SRAM_PAGE_SIZE (0) +-#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) +- +-#define EEPROM_START (0x0000) +-#define EEPROM_SIZE (1024) +-#define EEPROM_PAGE_SIZE (32) +-#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) +- +-#define FUSE_START (0x0000) +-#define FUSE_SIZE (6) +-#define FUSE_PAGE_SIZE (0) +-#define FUSE_END (FUSE_START + FUSE_SIZE - 1) +- +-#define LOCKBIT_START (0x0000) +-#define LOCKBIT_SIZE (1) +-#define LOCKBIT_PAGE_SIZE (0) +-#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) +- +-#define SIGNATURES_START (0x0000) +-#define SIGNATURES_SIZE (3) +-#define SIGNATURES_PAGE_SIZE (0) +-#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) +- +-#define USER_SIGNATURES_START (0x0000) +-#define USER_SIGNATURES_SIZE (256) +-#define USER_SIGNATURES_PAGE_SIZE (0) +-#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) +- +-#define PROD_SIGNATURES_START (0x0000) +-#define PROD_SIGNATURES_SIZE (52) +-#define PROD_SIGNATURES_PAGE_SIZE (0) +-#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) +- +-#define FLASHEND PROGMEM_END +-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +-#define RAMSTART INTERNAL_SRAM_START +-#define RAMSIZE INTERNAL_SRAM_SIZE +-#define RAMEND INTERNAL_SRAM_END +-#define XRAMSTART EXTERNAL_SRAM_START +-#define XRAMSIZE EXTERNAL_SRAM_SIZE +-#define XRAMEND INTERNAL_SRAM_END +-#define E2END EEPROM_END +-#define E2PAGESIZE EEPROM_PAGE_SIZE +- +- +-/* ========== Fuses ========== */ +-#define FUSE_MEMORY_SIZE 6 +- +-/* Fuse Byte 0 */ +-#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ +-#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ +-#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ +-#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ +-#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ +-#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ +-#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ +-#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ +-#define FUSE0_DEFAULT (0xFF) +- +-/* Fuse Byte 1 */ +-#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +-#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +-#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +-#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +-#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +-#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +-#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +-#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +-#define FUSE1_DEFAULT (0xFF) +- +-/* Fuse Byte 2 */ +-#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +-#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +-#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +-#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +-#define FUSE2_DEFAULT (0xFF) +- +-/* Fuse Byte 3 Reserved */ +- +-/* Fuse Byte 4 */ +-#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +-#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +-#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +-#define FUSE4_DEFAULT (0xFF) +- +-/* Fuse Byte 5 */ +-#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +-#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +-#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +-#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +-#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +-#define FUSE5_DEFAULT (0xFF) +- +- +-/* ========== Lock Bits ========== */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_BITS_EXIST +-#define __BOOT_LOCK_BOOT_BITS_EXIST +- +- +-/* ========== Signature ========== */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x94 +-#define SIGNATURE_2 0x41 +- +- +-#endif /* _AVR_ATxmega16A4_H_ */ +- ++/* Copyright (c) 2009-2010 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iox16a4.h 2200 2010-12-14 04:24:24Z arcanum $ */ ++ ++/* avr/iox16a4.h - definitions for ATxmega16A4 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox16a4.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATxmega16A4_H_ ++#define _AVR_ATxmega16A4_H_ 1 ++ ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++} CLK_t; ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t PRPB; /* Power Reduction Port B */ ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ ++} CLK_RTCSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control REgister */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t reserved_0x07; ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Channel */ ++typedef struct DMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Address Control */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ ++ register8_t REPCNT; /* Channel Repeat Count */ ++ register8_t reserved_0x07; ++ register8_t SRCADDR0; /* Channel Source Address 0 */ ++ register8_t SRCADDR1; /* Channel Source Address 1 */ ++ register8_t SRCADDR2; /* Channel Source Address 2 */ ++ register8_t reserved_0x0B; ++ register8_t DESTADDR0; /* Channel Destination Address 0 */ ++ register8_t DESTADDR1; /* Channel Destination Address 1 */ ++ register8_t DESTADDR2; /* Channel Destination Address 2 */ ++ register8_t reserved_0x0F; ++} DMA_CH_t; ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Controller */ ++typedef struct DMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ DMA_CH_t CH0; /* DMA Channel 0 */ ++ DMA_CH_t CH1; /* DMA Channel 1 */ ++ DMA_CH_t CH2; /* DMA Channel 2 */ ++ DMA_CH_t CH3; /* DMA Channel 3 */ ++} DMA_t; ++ ++/* Burst mode */ ++typedef enum DMA_CH_BURSTLEN_enum ++{ ++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ ++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ ++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ ++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ ++} DMA_CH_BURSTLEN_t; ++ ++/* Source address reload mode */ ++typedef enum DMA_CH_SRCRELOAD_enum ++{ ++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ ++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ ++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ ++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ ++} DMA_CH_SRCRELOAD_t; ++ ++/* Source addressing mode */ ++typedef enum DMA_CH_SRCDIR_enum ++{ ++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ ++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ ++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ ++} DMA_CH_SRCDIR_t; ++ ++/* Destination adress reload mode */ ++typedef enum DMA_CH_DESTRELOAD_enum ++{ ++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ ++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ ++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ ++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ ++} DMA_CH_DESTRELOAD_t; ++ ++/* Destination adressing mode */ ++typedef enum DMA_CH_DESTDIR_enum ++{ ++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ ++} DMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum DMA_CH_TRIGSRC_enum ++{ ++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ ++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ ++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ ++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ ++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ ++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ ++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ ++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ ++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ ++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ ++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ ++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ ++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ ++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ ++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ ++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ ++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ ++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ ++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ ++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ ++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ ++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ ++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ ++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ ++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ ++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ ++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ ++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ ++} DMA_CH_TRIGSRC_t; ++ ++/* Double buffering mode */ ++typedef enum DMA_DBUFMODE_enum ++{ ++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ ++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ ++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ ++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ ++} DMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum DMA_PRIMODE_enum ++{ ++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ ++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ ++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ ++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ ++} DMA_PRIMODE_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_ERRINTLVL_enum ++{ ++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ ++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ ++} DMA_CH_ERRINTLVL_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_TRNINTLVL_enum ++{ ++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ ++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ ++} DMA_CH_TRNINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ ++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ ++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ ++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t CH4CTRL; /* Channel 4 Control Register */ ++ register8_t CH5CTRL; /* Channel 5 Control Register */ ++ register8_t CH6CTRL; /* Channel 6 Control Register */ ++ register8_t CH7CTRL; /* Channel 7 Control Register */ ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ ++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ ++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ ++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ ++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ ++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ ++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ ++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ ++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ ++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ ++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ ++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ ++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ ++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ ++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ ++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ ++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ ++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t FUSEBYTE0; /* User ID */ ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ ++ register8_t reserved_0x01; ++ register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ ++ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ ++ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ ++ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++} NVM_PROD_SIGNATURES_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++} NVM_LB_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brown Out Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ ++ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Comparator 0 Control */ ++ register8_t AC1CTRL; /* Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t reserved_0x6; ++ register8_t reserved_0x7; ++} ADC_CH_t; ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ _WORDREGISTER(CH1RES); /* Channel 1 Result */ ++ _WORDREGISTER(CH2RES); /* Channel 2 Result */ ++ _WORDREGISTER(CH3RES); /* Channel 3 Result */ ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++ ADC_CH_t CH1; /* ADC Channel 1 */ ++ ADC_CH_t CH2; /* ADC Channel 2 */ ++ ADC_CH_t CH3; /* ADC Channel 3 */ ++} ADC_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++} ADC_REFSEL_t; ++ ++/* Channel sweep selection */ ++typedef enum ADC_SWEEP_enum ++{ ++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ ++} ADC_SWEEP_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ++ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* DMA request selection */ ++typedef enum ADC_DMASEL_enum ++{ ++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ ++} ADC_DMASEL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DAC - Digital/Analog Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Digital-to-Analog Converter */ ++typedef struct DAC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t EVCTRL; /* Event Input Control */ ++ register8_t TIMCTRL; /* Timing Control */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t GAINCAL; /* Gain Calibration */ ++ register8_t OFFSETCAL; /* Offset Calibration */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ ++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ ++} DAC_t; ++ ++/* Output channel selection */ ++typedef enum DAC_CHSEL_enum ++{ ++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ ++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ ++} DAC_CHSEL_t; ++ ++/* Reference voltage selection */ ++typedef enum DAC_REFSEL_enum ++{ ++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ ++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ ++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ ++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ ++} DAC_REFSEL_t; ++ ++/* Event channel selection */ ++typedef enum DAC_EVSEL_enum ++{ ++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ ++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ ++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ ++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ ++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ ++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ ++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ ++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ ++} DAC_EVSEL_t; ++ ++/* Conversion interval */ ++typedef enum DAC_CONINTVAL_enum ++{ ++ DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ ++ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ ++ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ ++ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ ++ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ ++ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ ++ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ ++ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ ++} DAC_CONINTVAL_t; ++ ++/* Refresh rate */ ++typedef enum DAC_REFRESH_enum ++{ ++ DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ ++ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ ++ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ ++ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ ++ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ ++ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ ++ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ ++ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ ++ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ ++ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ ++ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ ++ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ ++ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ ++ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ ++} DAC_REFRESH_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Clounter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* EBI Chip Select Module */ ++typedef struct EBI_CS_struct ++{ ++ register8_t CTRLA; /* Chip Select Control Register A */ ++ register8_t CTRLB; /* Chip Select Control Register B */ ++ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ ++} EBI_CS_t; ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* External Bus Interface */ ++typedef struct EBI_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ ++ register8_t reserved_0x02; ++ register8_t reserved_0x03; ++ _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ ++ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ ++ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ ++ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ EBI_CS_t CS0; /* Chip Select 0 */ ++ EBI_CS_t CS1; /* Chip Select 1 */ ++ EBI_CS_t CS2; /* Chip Select 2 */ ++ EBI_CS_t CS3; /* Chip Select 3 */ ++} EBI_t; ++ ++/* Chip Select adress space */ ++typedef enum EBI_CS_ASIZE_enum ++{ ++ EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ ++ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ ++ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ ++ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ ++ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ ++ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ ++ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ ++ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ ++ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ ++ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ ++ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ ++ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ ++ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ ++ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ ++ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ ++ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ ++ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ ++} EBI_CS_ASIZE_t; ++ ++/* */ ++typedef enum EBI_CS_SRWS_enum ++{ ++ EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_CS_SRWS_t; ++ ++/* Chip Select address mode */ ++typedef enum EBI_CS_MODE_enum ++{ ++ EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ ++ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ ++ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ ++ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ ++} EBI_CS_MODE_t; ++ ++/* Chip Select SDRAM mode */ ++typedef enum EBI_CS_SDMODE_enum ++{ ++ EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ ++ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ ++} EBI_CS_SDMODE_t; ++ ++/* */ ++typedef enum EBI_SDDATAW_enum ++{ ++ EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ ++ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ ++} EBI_SDDATAW_t; ++ ++/* */ ++typedef enum EBI_LPCMODE_enum ++{ ++ EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ ++ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ ++} EBI_LPCMODE_t; ++ ++/* */ ++typedef enum EBI_SRMODE_enum ++{ ++ EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ ++ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ ++ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ ++ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ ++} EBI_SRMODE_t; ++ ++/* */ ++typedef enum EBI_IFMODE_enum ++{ ++ EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ ++ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ ++ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ ++ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ ++} EBI_IFMODE_t; ++ ++/* */ ++typedef enum EBI_SDCOL_enum ++{ ++ EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ ++ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ ++ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ ++ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ ++} EBI_SDCOL_t; ++ ++/* */ ++typedef enum EBI_MRDLY_enum ++{ ++ EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_MRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCYCDLY_enum ++{ ++ EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ROWCYCDLY_t; ++ ++/* */ ++typedef enum EBI_RPDLY_enum ++{ ++ EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_RPDLY_t; ++ ++/* */ ++typedef enum EBI_WRDLY_enum ++{ ++ EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_WRDLY_t; ++ ++/* */ ++typedef enum EBI_ESRDLY_enum ++{ ++ EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ESRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCOLDLY_enum ++{ ++ EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_ROWCOLDLY_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++} PORTCFG_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Virtual Port 0 Mapping */ ++typedef enum PORTCFG_VP0MAP_enum ++{ ++ PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP0MAP_t; ++ ++/* Virtual Port 1 Mapping */ ++typedef enum PORTCFG_VP1MAP_enum ++{ ++ PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP1MAP_t; ++ ++/* Virtual Port 2 Mapping */ ++typedef enum PORTCFG_VP2MAP_enum ++{ ++ PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP2MAP_t; ++ ++/* Virtual Port 3 Mapping */ ++typedef enum PORTCFG_VP3MAP_enum ++{ ++ PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP3MAP_t; ++ ++/* Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x05; ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AES - AES Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* AES Module */ ++typedef struct AES_struct ++{ ++ register8_t CTRL; /* AES Control Register */ ++ register8_t STATUS; /* AES Status Register */ ++ register8_t STATE; /* AES State Register */ ++ register8_t KEY; /* AES Key Register */ ++ register8_t INTCTRL; /* AES Interrupt Control Register */ ++} AES_t; ++ ++/* Interrupt level */ ++typedef enum AES_INTLVL_enum ++{ ++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} AES_INTLVL_t; ++ ++ ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset Controller */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ ++#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ ++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ ++#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ ++#define PORTA (*(PORT_t *) 0x0600) /* Port A */ ++#define PORTB (*(PORT_t *) 0x0620) /* Port B */ ++#define PORTC (*(PORT_t *) 0x0640) /* Port C */ ++#define PORTD (*(PORT_t *) 0x0660) /* Port D */ ++#define PORTE (*(PORT_t *) 0x0680) /* Port E */ ++#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ ++#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ ++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ ++#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ ++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ ++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ ++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++#define GPIO_GPIOR4 _SFR_MEM8(0x0004) ++#define GPIO_GPIOR5 _SFR_MEM8(0x0005) ++#define GPIO_GPIOR6 _SFR_MEM8(0x0006) ++#define GPIO_GPIOR7 _SFR_MEM8(0x0007) ++#define GPIO_GPIOR8 _SFR_MEM8(0x0008) ++#define GPIO_GPIOR9 _SFR_MEM8(0x0009) ++#define GPIO_GPIORA _SFR_MEM8(0x000A) ++#define GPIO_GPIORB _SFR_MEM8(0x000B) ++#define GPIO_GPIORC _SFR_MEM8(0x000C) ++#define GPIO_GPIORD _SFR_MEM8(0x000D) ++#define GPIO_GPIORE _SFR_MEM8(0x000E) ++#define GPIO_GPIORF _SFR_MEM8(0x000F) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++#define GPIO_GPIO4 _SFR_MEM8(0x0004) ++#define GPIO_GPIO5 _SFR_MEM8(0x0005) ++#define GPIO_GPIO6 _SFR_MEM8(0x0006) ++#define GPIO_GPIO7 _SFR_MEM8(0x0007) ++#define GPIO_GPIO8 _SFR_MEM8(0x0008) ++#define GPIO_GPIO9 _SFR_MEM8(0x0009) ++#define GPIO_GPIOA _SFR_MEM8(0x000A) ++#define GPIO_GPIOB _SFR_MEM8(0x000B) ++#define GPIO_GPIOC _SFR_MEM8(0x000C) ++#define GPIO_GPIOD _SFR_MEM8(0x000D) ++#define GPIO_GPIOE _SFR_MEM8(0x000E) ++#define GPIO_GPIOF _SFR_MEM8(0x000F) ++ ++/* VPORT0 - Virtual Port 0 */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT1 - Virtual Port 1 */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT2 - Virtual Port 2 */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT3 - Virtual Port 3 */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU Registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator Control */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPB _SFR_MEM8(0x0072) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset Controller */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - Port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++ ++/* AES - AES Crypto Module */ ++#define AES_CTRL _SFR_MEM8(0x00C0) ++#define AES_STATUS _SFR_MEM8(0x00C1) ++#define AES_STATE _SFR_MEM8(0x00C2) ++#define AES_KEY _SFR_MEM8(0x00C3) ++#define AES_INTCTRL _SFR_MEM8(0x00C4) ++ ++/* DMA - DMA Controller */ ++#define DMA_CTRL _SFR_MEM8(0x0100) ++#define DMA_INTFLAGS _SFR_MEM8(0x0103) ++#define DMA_STATUS _SFR_MEM8(0x0104) ++#define DMA_TEMP _SFR_MEM16(0x0106) ++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) ++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) ++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) ++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) ++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) ++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) ++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) ++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) ++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) ++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) ++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) ++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) ++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) ++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) ++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) ++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) ++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) ++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) ++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) ++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) ++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) ++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) ++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) ++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) ++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) ++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) ++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) ++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) ++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) ++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) ++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) ++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) ++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) ++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) ++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) ++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) ++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) ++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) ++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) ++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) ++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) ++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH4MUX _SFR_MEM8(0x0184) ++#define EVSYS_CH5MUX _SFR_MEM8(0x0185) ++#define EVSYS_CH6MUX _SFR_MEM8(0x0186) ++#define EVSYS_CH7MUX _SFR_MEM8(0x0187) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) ++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) ++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) ++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non Volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADCA - Analog to Digital Converter A */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CH1RES _SFR_MEM16(0x0212) ++#define ADCA_CH2RES _SFR_MEM16(0x0214) ++#define ADCA_CH3RES _SFR_MEM16(0x0216) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) ++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) ++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) ++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) ++#define ADCA_CH1_RES _SFR_MEM16(0x022C) ++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) ++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) ++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) ++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) ++#define ADCA_CH2_RES _SFR_MEM16(0x0234) ++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) ++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) ++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) ++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) ++#define ADCA_CH3_RES _SFR_MEM16(0x023C) ++ ++/* DACB - Digital to Analog Converter B */ ++#define DACB_CTRLA _SFR_MEM8(0x0320) ++#define DACB_CTRLB _SFR_MEM8(0x0321) ++#define DACB_CTRLC _SFR_MEM8(0x0322) ++#define DACB_EVCTRL _SFR_MEM8(0x0323) ++#define DACB_TIMCTRL _SFR_MEM8(0x0324) ++#define DACB_STATUS _SFR_MEM8(0x0325) ++#define DACB_GAINCAL _SFR_MEM8(0x0328) ++#define DACB_OFFSETCAL _SFR_MEM8(0x0329) ++#define DACB_CH0DATA _SFR_MEM16(0x0338) ++#define DACB_CH1DATA _SFR_MEM16(0x033A) ++ ++/* ACA - Analog Comparator A */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWIC - Two-Wire Interface C */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWIE - Two-Wire Interface E */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* PORTA - Port A */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORTB - Port B */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORTC - Port C */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORTD - Port D */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORTE - Port E */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORTR - Port R */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TCC0 - Timer/Counter C0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TCC1 - Timer/Counter C1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEXC - Advanced Waveform Extension C */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRESC - High-Resolution Extension C */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ ++#define USARTC1_DATA _SFR_MEM8(0x08B0) ++#define USARTC1_STATUS _SFR_MEM8(0x08B1) ++#define USARTC1_CTRLA _SFR_MEM8(0x08B3) ++#define USARTC1_CTRLB _SFR_MEM8(0x08B4) ++#define USARTC1_CTRLC _SFR_MEM8(0x08B5) ++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) ++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) ++ ++/* SPIC - Serial Peripheral Interface C */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TCD0 - Timer/Counter D0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TCD1 - Timer/Counter D1 */ ++#define TCD1_CTRLA _SFR_MEM8(0x0940) ++#define TCD1_CTRLB _SFR_MEM8(0x0941) ++#define TCD1_CTRLC _SFR_MEM8(0x0942) ++#define TCD1_CTRLD _SFR_MEM8(0x0943) ++#define TCD1_CTRLE _SFR_MEM8(0x0944) ++#define TCD1_INTCTRLA _SFR_MEM8(0x0946) ++#define TCD1_INTCTRLB _SFR_MEM8(0x0947) ++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) ++#define TCD1_CTRLFSET _SFR_MEM8(0x0949) ++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) ++#define TCD1_CTRLGSET _SFR_MEM8(0x094B) ++#define TCD1_INTFLAGS _SFR_MEM8(0x094C) ++#define TCD1_TEMP _SFR_MEM8(0x094F) ++#define TCD1_CNT _SFR_MEM16(0x0960) ++#define TCD1_PER _SFR_MEM16(0x0966) ++#define TCD1_CCA _SFR_MEM16(0x0968) ++#define TCD1_CCB _SFR_MEM16(0x096A) ++#define TCD1_PERBUF _SFR_MEM16(0x0976) ++#define TCD1_CCABUF _SFR_MEM16(0x0978) ++#define TCD1_CCBBUF _SFR_MEM16(0x097A) ++ ++/* HIRESD - High-Resolution Extension D */ ++#define HIRESD_CTRLA _SFR_MEM8(0x0990) ++ ++/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ ++#define USARTD1_DATA _SFR_MEM8(0x09B0) ++#define USARTD1_STATUS _SFR_MEM8(0x09B1) ++#define USARTD1_CTRLA _SFR_MEM8(0x09B3) ++#define USARTD1_CTRLB _SFR_MEM8(0x09B4) ++#define USARTD1_CTRLC _SFR_MEM8(0x09B5) ++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) ++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) ++ ++/* SPID - Serial Peripheral Interface D */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TCE0 - Timer/Counter E0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* HIRESE - High-Resolution Extension E */ ++#define HIRESE_CTRLA _SFR_MEM8(0x0A90) ++ ++/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR1 bit masks and bit positions */ ++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ ++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ ++ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ ++ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ ++#define PR_EBI_bp 3 /* External Bus Interface bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ ++#define PR_DAC_bp 2 /* Port A DAC bit position. */ ++ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++ ++/* PR.PRPB bit masks and bit positions */ ++/* PR_DAC_bm Predefined. */ ++/* PR_DAC_bp Predefined. */ ++ ++/* PR_ADC_bm Predefined. */ ++/* PR_ADC_bp Predefined. */ ++ ++/* PR_AC_bm Predefined. */ ++/* PR_AC_bp Predefined. */ ++ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ ++ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ ++ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ ++ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ ++#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ ++ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ ++ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ ++ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ ++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ ++ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++ ++/* DMA - DMA Controller */ ++/* DMA_CH.CTRLA bit masks and bit positions */ ++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ ++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ ++ ++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ ++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ ++ ++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ ++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ ++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ ++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ ++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ ++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ ++ ++ ++/* DMA_CH.CTRLB bit masks and bit positions */ ++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ ++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ ++ ++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ ++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ ++ ++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ ++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ ++ ++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ ++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ ++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ ++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ ++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ ++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ ++ ++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ ++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ ++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ ++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ ++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ ++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ ++ ++ ++/* DMA_CH.ADDRCTRL bit masks and bit positions */ ++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ ++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ ++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ ++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ ++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ ++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ ++ ++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ ++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ ++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ ++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ ++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ ++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ ++ ++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ ++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ ++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ ++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ ++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ ++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ ++ ++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ ++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ ++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ ++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ ++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ ++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ ++ ++ ++/* DMA_CH.TRIGSRC bit masks and bit positions */ ++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++ ++/* DMA.CTRL bit masks and bit positions */ ++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define DMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define DMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ ++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ ++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ ++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ ++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ ++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ ++ ++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ ++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ ++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ ++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ ++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ ++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ ++ ++ ++/* DMA.INTFLAGS bit masks and bit positions */ ++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++ ++/* DMA.STATUS bit masks and bit positions */ ++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ ++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ ++ ++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ ++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ ++ ++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ ++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ ++ ++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ ++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ ++ ++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ ++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ ++ ++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ ++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ ++ ++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ ++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ ++ ++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ ++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ ++ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH4MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH5MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH6MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH7MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM_gm Predefined. */ ++/* EVSYS_QDIRM_gp Predefined. */ ++/* EVSYS_QDIRM0_bm Predefined. */ ++/* EVSYS_QDIRM0_bp Predefined. */ ++/* EVSYS_QDIRM1_bm Predefined. */ ++/* EVSYS_QDIRM1_bp Predefined. */ ++ ++/* EVSYS_QDIEN_bm Predefined. */ ++/* EVSYS_QDIEN_bp Predefined. */ ++ ++/* EVSYS_QDEN_bm Predefined. */ ++/* EVSYS_QDEN_bp Predefined. */ ++ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH4CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM_gm Predefined. */ ++/* EVSYS_QDIRM_gp Predefined. */ ++/* EVSYS_QDIRM0_bm Predefined. */ ++/* EVSYS_QDIRM0_bp Predefined. */ ++/* EVSYS_QDIRM1_bm Predefined. */ ++/* EVSYS_QDIRM1_bp Predefined. */ ++ ++/* EVSYS_QDIEN_bm Predefined. */ ++/* EVSYS_QDIEN_bp Predefined. */ ++ ++/* EVSYS_QDEN_bm Predefined. */ ++/* EVSYS_QDEN_bp Predefined. */ ++ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH5CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH6CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH7CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0xFF /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ ++#define NVM_CMD7_bp 7 /* Command bit 7 position. */ ++ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ ++#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ ++#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ ++#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ ++#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ ++#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ ++#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ ++#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ ++#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ ++#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ ++#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ ++#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ ++#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ ++#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ ++#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ ++#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ ++#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ ++#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ ++#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ ++#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ ++ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ ++ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ ++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE_gm Predefined. */ ++/* AC_INTMODE_gp Predefined. */ ++/* AC_INTMODE0_bm Predefined. */ ++/* AC_INTMODE0_bp Predefined. */ ++/* AC_INTMODE1_bm Predefined. */ ++/* AC_INTMODE1_bp Predefined. */ ++ ++/* AC_INTLVL_gm Predefined. */ ++/* AC_INTLVL_gp Predefined. */ ++/* AC_INTLVL0_bm Predefined. */ ++/* AC_INTLVL0_bp Predefined. */ ++/* AC_INTLVL1_bm Predefined. */ ++/* AC_INTLVL1_bp Predefined. */ ++ ++/* AC_HSMODE_bm Predefined. */ ++/* AC_HSMODE_bp Predefined. */ ++ ++/* AC_HYSMODE_gm Predefined. */ ++/* AC_HYSMODE_gp Predefined. */ ++/* AC_HYSMODE0_bm Predefined. */ ++/* AC_HYSMODE0_bp Predefined. */ ++/* AC_HYSMODE1_bm Predefined. */ ++/* AC_HYSMODE1_bp Predefined. */ ++ ++/* AC_ENABLE_bm Predefined. */ ++/* AC_ENABLE_bp Predefined. */ ++ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS_gm Predefined. */ ++/* AC_MUXPOS_gp Predefined. */ ++/* AC_MUXPOS0_bm Predefined. */ ++/* AC_MUXPOS0_bp Predefined. */ ++/* AC_MUXPOS1_bm Predefined. */ ++/* AC_MUXPOS1_bp Predefined. */ ++/* AC_MUXPOS2_bm Predefined. */ ++/* AC_MUXPOS2_bp Predefined. */ ++ ++/* AC_MUXNEG_gm Predefined. */ ++/* AC_MUXNEG_gp Predefined. */ ++/* AC_MUXNEG0_bm Predefined. */ ++/* AC_MUXNEG0_bp Predefined. */ ++/* AC_MUXNEG1_bm Predefined. */ ++/* AC_MUXNEG1_bp Predefined. */ ++/* AC_MUXNEG2_bm Predefined. */ ++/* AC_MUXNEG2_bp Predefined. */ ++ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ ++ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ ++ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ ++ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ ++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ ++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ ++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ ++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ ++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ ++ ++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ ++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ ++ ++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ ++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ ++ ++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ ++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ ++ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ ++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ ++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ ++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ ++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ ++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ ++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ ++ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ ++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ ++ ++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ ++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ ++ ++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ ++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ ++ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++ ++/* DAC - Digital/Analog Converter */ ++/* DAC.CTRLA bit masks and bit positions */ ++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ ++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ ++ ++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ ++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ ++ ++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ ++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ ++ ++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ ++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ ++ ++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define DAC_ENABLE_bp 0 /* Enable bit position. */ ++ ++ ++/* DAC.CTRLB bit masks and bit positions */ ++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ ++#define DAC_CHSEL_gp 5 /* Channel Select group position. */ ++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ ++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ ++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ ++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ ++ ++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ ++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ ++ ++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ ++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ ++ ++ ++/* DAC.CTRLC bit masks and bit positions */ ++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ ++#define DAC_REFSEL_gp 3 /* Reference Select group position. */ ++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ ++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ ++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ ++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ ++ ++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ ++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ ++ ++ ++/* DAC.EVCTRL bit masks and bit positions */ ++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ ++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ ++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ ++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ ++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ ++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ ++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ ++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ ++ ++ ++/* DAC.TIMCTRL bit masks and bit positions */ ++#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ ++#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ ++#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ ++#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ ++#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ ++#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ ++#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ ++#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ ++ ++#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ ++#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ ++#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ ++#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ ++#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ ++#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ ++#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ ++#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ ++#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ ++#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ ++ ++ ++/* DAC.STATUS bit masks and bit positions */ ++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ ++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ ++ ++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ ++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ ++ ++ ++/* RTC - Real-Time Clounter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* EBI - External Bus Interface */ ++/* EBI_CS.CTRLA bit masks and bit positions */ ++#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ ++#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ ++#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ ++#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ ++#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ ++#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ ++#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ ++#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ ++#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ ++#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ ++#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ ++#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ ++ ++#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ ++#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ ++#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ ++#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ ++#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ ++#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ ++ ++ ++/* EBI_CS.CTRLB bit masks and bit positions */ ++#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ ++#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ ++#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ ++#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ ++#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ ++#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ ++#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ ++#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ ++ ++#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ ++#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ ++ ++#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ ++#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ ++ ++#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ ++#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ ++#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ ++#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ ++#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ ++#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ ++ ++ ++/* EBI.CTRL bit masks and bit positions */ ++#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ ++#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ ++#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ ++#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ ++#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ ++#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ ++ ++#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ ++#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ ++#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ ++#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ ++#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ ++#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ ++ ++#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ ++#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ ++#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ ++#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ ++#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ ++#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ ++ ++#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ ++#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ ++#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ ++#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ ++#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ ++#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLA bit masks and bit positions */ ++#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ ++#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ ++ ++#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ ++#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ ++ ++#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ ++#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ ++#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ ++#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ ++#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ ++#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLB bit masks and bit positions */ ++#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ ++#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ ++#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ ++#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ ++#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ ++#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ ++ ++#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ ++#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ ++#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ ++#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ ++#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ ++#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ ++#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ ++#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ ++ ++#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ ++#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ ++#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ ++#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ ++#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ ++#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ ++#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ ++#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ ++ ++ ++/* EBI.SDRAMCTRLC bit masks and bit positions */ ++#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ ++#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ ++#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ ++#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ ++#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ ++#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ ++ ++#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ ++#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ ++#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ ++#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ ++#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ ++#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ ++#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ ++#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ ++ ++#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ ++#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ ++#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ ++#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ ++#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ ++#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ ++#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ ++#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ ++ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ ++#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++ ++/* PORT - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ ++#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ ++ ++#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD_gm Predefined. */ ++/* TC0_CMD_gp Predefined. */ ++/* TC0_CMD0_bm Predefined. */ ++/* TC0_CMD0_bp Predefined. */ ++/* TC0_CMD1_bm Predefined. */ ++/* TC0_CMD1_bp Predefined. */ ++ ++/* TC0_LUPD_bm Predefined. */ ++/* TC0_LUPD_bp Predefined. */ ++ ++/* TC0_DIR_bm Predefined. */ ++/* TC0_DIR_bp Predefined. */ ++ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV_bm Predefined. */ ++/* TC0_CCDBV_bp Predefined. */ ++ ++/* TC0_CCCBV_bm Predefined. */ ++/* TC0_CCCBV_bp Predefined. */ ++ ++/* TC0_CCBBV_bm Predefined. */ ++/* TC0_CCBBV_bp Predefined. */ ++ ++/* TC0_CCABV_bm Predefined. */ ++/* TC0_CCABV_bp Predefined. */ ++ ++/* TC0_PERBV_bm Predefined. */ ++/* TC0_PERBV_bp Predefined. */ ++ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ ++#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ ++ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD_gm Predefined. */ ++/* TC1_CMD_gp Predefined. */ ++/* TC1_CMD0_bm Predefined. */ ++/* TC1_CMD0_bp Predefined. */ ++/* TC1_CMD1_bm Predefined. */ ++/* TC1_CMD1_bp Predefined. */ ++ ++/* TC1_LUPD_bm Predefined. */ ++/* TC1_LUPD_bp Predefined. */ ++ ++/* TC1_DIR_bm Predefined. */ ++/* TC1_DIR_bp Predefined. */ ++ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV_bm Predefined. */ ++/* TC1_CCBBV_bp Predefined. */ ++ ++/* TC1_CCABV_bm Predefined. */ ++/* TC1_CCABV_bp Predefined. */ ++ ++/* TC1_PERBV_bm Predefined. */ ++/* TC1_PERBV_bp Predefined. */ ++ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++ ++/* HIRES.CTRL bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL_gm Predefined. */ ++/* USART_BSEL_gp Predefined. */ ++/* USART_BSEL0_bm Predefined. */ ++/* USART_BSEL0_bp Predefined. */ ++/* USART_BSEL1_bm Predefined. */ ++/* USART_BSEL1_bp Predefined. */ ++/* USART_BSEL2_bm Predefined. */ ++/* USART_BSEL2_bp Predefined. */ ++/* USART_BSEL3_bm Predefined. */ ++/* USART_BSEL3_bp Predefined. */ ++ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++ ++/* AES - AES Module */ ++/* AES.CTRL bit masks and bit positions */ ++#define AES_START_bm 0x80 /* Start/Run bit mask. */ ++#define AES_START_bp 7 /* Start/Run bit position. */ ++ ++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ ++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ ++ ++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ ++#define AES_RESET_bp 5 /* AES Software Reset bit position. */ ++ ++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ ++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ ++ ++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ ++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ ++ ++ ++/* AES.STATUS bit masks and bit positions */ ++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ ++#define AES_ERROR_bp 7 /* AES Error bit position. */ ++ ++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ ++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ ++ ++ ++/* AES.INTCTRL bit masks and bit positions */ ++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define AES_INTLVL_gp 0 /* Interrupt level group position. */ ++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_XOSCF_vect_num 1 ++#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* DMA interrupt vectors */ ++#define DMA_CH0_vect_num 6 ++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ ++#define DMA_CH1_vect_num 7 ++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ ++#define DMA_CH2_vect_num 8 ++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ ++#define DMA_CH3_vect_num 9 ++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* USARTC1 interrupt vectors */ ++#define USARTC1_RXC_vect_num 28 ++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ ++#define USARTC1_DRE_vect_num 29 ++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ ++#define USARTC1_TXC_vect_num 30 ++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ ++ ++/* AES interrupt vectors */ ++#define AES_INT_vect_num 31 ++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* TCE1 interrupt vectors */ ++#define TCE1_OVF_vect_num 53 ++#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ ++#define TCE1_ERR_vect_num 54 ++#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ ++#define TCE1_CCA_vect_num 55 ++#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ ++#define TCE1_CCB_vect_num 56 ++#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++#define ADCA_CH1_vect_num 72 ++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ ++#define ADCA_CH2_vect_num 73 ++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ ++#define ADCA_CH3_vect_num 74 ++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD1 interrupt vectors */ ++#define TCD1_OVF_vect_num 83 ++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ ++#define TCD1_ERR_vect_num 84 ++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ ++#define TCD1_CCA_vect_num 85 ++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ ++#define TCD1_CCB_vect_num 86 ++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* USARTD1 interrupt vectors */ ++#define USARTD1_RXC_vect_num 91 ++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ ++#define USARTD1_DRE_vect_num 92 ++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ ++#define USARTD1_TXC_vect_num 93 ++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ ++ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (94 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (20480) ++#define PROGMEM_PAGE_SIZE (256) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (16384) ++#define APP_SECTION_PAGE_SIZE (256) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x3000) ++#define APPTABLE_SECTION_SIZE (4096) ++#define APPTABLE_SECTION_PAGE_SIZE (256) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x4000) ++#define BOOT_SECTION_SIZE (4096) ++#define BOOT_SECTION_PAGE_SIZE (256) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (10240) ++#define DATAMEM_PAGE_SIZE (0) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (1024) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (2048) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (1024) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define FUSE_START (0x0000) ++#define FUSE_SIZE (6) ++#define FUSE_PAGE_SIZE (0) ++#define FUSE_END (FUSE_START + FUSE_SIZE - 1) ++ ++#define LOCKBIT_START (0x0000) ++#define LOCKBIT_SIZE (1) ++#define LOCKBIT_PAGE_SIZE (0) ++#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (256) ++#define USER_SIGNATURES_PAGE_SIZE (0) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (0) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE PROGMEM_PAGE_SIZE ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define XRAMSTART EXTERNAL_SRAM_START ++#define XRAMSIZE EXTERNAL_SRAM_SIZE ++#define XRAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 */ ++#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ ++#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ ++#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ ++#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ ++#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ ++#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ ++#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ ++#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ ++#define FUSE0_DEFAULT (0xFF) ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x41 ++ ++ ++#endif /* _AVR_ATxmega16A4_H_ */ ++ +diff --git a/include/avr/iox16a4u.h b/include/avr/iox16a4u.h +new file mode 100644 +index 0000000..a3455f1 +--- /dev/null ++++ b/include/avr/iox16a4u.h +@@ -0,0 +1,7240 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox16a4u.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA16A4U_H_INCLUDED ++#define _AVR_ATXMEGA16A4U_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t USBCTRL; /* USB Control Register */ ++} CLK_t; ++ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t PRPB; /* Power Reduction Port B */ ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++/* USB Prescaler Division Factor */ ++typedef enum CLK_USBPSDIV_enum ++{ ++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ ++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ ++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ ++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ ++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ ++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ ++} CLK_USBPSDIV_t; ++ ++/* USB Clock Source */ ++typedef enum CLK_USBSRC_enum ++{ ++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ ++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ ++} CLK_USBSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 2 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC2MCREF_enum ++{ ++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC2MCREF_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++ register8_t EBIOUT; /* EBI Output register */ ++ register8_t EVOUTSEL; /* Event Output Select */ ++} PORTCFG_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP02MAP_enum ++{ ++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP02MAP_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP13MAP_enum ++{ ++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP13MAP_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Clock and Event Output Port */ ++typedef enum PORTCFG_CLKEVPIN_enum ++{ ++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ ++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ ++} PORTCFG_CLKEVPIN_t; ++ ++/* EBI Address Output Port */ ++typedef enum PORTCFG_EBIADROUT_enum ++{ ++ PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ ++ PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ ++ PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ ++ PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ ++} PORTCFG_EBIADROUT_t; ++ ++/* EBI Chip Select Output Port */ ++typedef enum PORTCFG_EBICSOUT_enum ++{ ++ PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ ++} PORTCFG_EBICSOUT_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ ++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ ++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ ++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ ++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AES - AES Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* AES Module */ ++typedef struct AES_struct ++{ ++ register8_t CTRL; /* AES Control Register */ ++ register8_t STATUS; /* AES Status Register */ ++ register8_t STATE; /* AES State Register */ ++ register8_t KEY; /* AES Key Register */ ++ register8_t INTCTRL; /* AES Interrupt Control Register */ ++} AES_t; ++ ++/* Interrupt level */ ++typedef enum AES_INTLVL_enum ++{ ++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} AES_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ ++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ ++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ ++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Channel */ ++typedef struct DMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Address Control */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ ++ register8_t REPCNT; /* Channel Repeat Count */ ++ register8_t reserved_0x07; ++ register8_t SRCADDR0; /* Channel Source Address 0 */ ++ register8_t SRCADDR1; /* Channel Source Address 1 */ ++ register8_t SRCADDR2; /* Channel Source Address 2 */ ++ register8_t reserved_0x0B; ++ register8_t DESTADDR0; /* Channel Destination Address 0 */ ++ register8_t DESTADDR1; /* Channel Destination Address 1 */ ++ register8_t DESTADDR2; /* Channel Destination Address 2 */ ++ register8_t reserved_0x0F; ++} DMA_CH_t; ++ ++ ++/* DMA Controller */ ++typedef struct DMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ DMA_CH_t CH0; /* DMA Channel 0 */ ++ DMA_CH_t CH1; /* DMA Channel 1 */ ++ DMA_CH_t CH2; /* DMA Channel 2 */ ++ DMA_CH_t CH3; /* DMA Channel 3 */ ++} DMA_t; ++ ++/* Burst mode */ ++typedef enum DMA_CH_BURSTLEN_enum ++{ ++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ ++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ ++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ ++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ ++} DMA_CH_BURSTLEN_t; ++ ++/* Source address reload mode */ ++typedef enum DMA_CH_SRCRELOAD_enum ++{ ++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ ++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ ++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ ++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ ++} DMA_CH_SRCRELOAD_t; ++ ++/* Source addressing mode */ ++typedef enum DMA_CH_SRCDIR_enum ++{ ++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ ++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ ++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ ++} DMA_CH_SRCDIR_t; ++ ++/* Destination adress reload mode */ ++typedef enum DMA_CH_DESTRELOAD_enum ++{ ++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ ++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ ++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ ++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ ++} DMA_CH_DESTRELOAD_t; ++ ++/* Destination adressing mode */ ++typedef enum DMA_CH_DESTDIR_enum ++{ ++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ ++} DMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum DMA_CH_TRIGSRC_enum ++{ ++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ ++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ ++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ ++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ ++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ ++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ ++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ ++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ ++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ ++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ ++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ ++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ ++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ ++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ ++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ ++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ ++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ ++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ ++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ ++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ ++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ ++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ ++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ ++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ ++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ ++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ ++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ ++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ ++} DMA_CH_TRIGSRC_t; ++ ++/* Double buffering mode */ ++typedef enum DMA_DBUFMODE_enum ++{ ++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ ++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ ++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ ++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ ++} DMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum DMA_PRIMODE_enum ++{ ++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ ++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ ++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ ++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ ++} DMA_PRIMODE_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_ERRINTLVL_enum ++{ ++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ ++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ ++} DMA_CH_ERRINTLVL_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_TRNINTLVL_enum ++{ ++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ ++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ ++} DMA_CH_TRNINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ ++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ ++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ ++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t CH4CTRL; /* Channel 4 Control Register */ ++ register8_t CH5CTRL; /* Channel 5 Control Register */ ++ register8_t CH6CTRL; /* Channel 6 Control Register */ ++ register8_t CH7CTRL; /* Channel 7 Control Register */ ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ ++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ ++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ ++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ ++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ ++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ ++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ ++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ ++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ ++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ ++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ ++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ ++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ ++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ ++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ ++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ ++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ ++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t reserved_0x07; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ _WORDREGISTER(CH1RES); /* Channel 1 Result */ ++ _WORDREGISTER(CH2RES); /* Channel 2 Result */ ++ _WORDREGISTER(CH3RES); /* Channel 3 Result */ ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++ ADC_CH_t CH1; /* ADC Channel 1 */ ++ ADC_CH_t CH2; /* ADC Channel 2 */ ++ ADC_CH_t CH3; /* ADC Channel 3 */ ++} ADC_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ ++ ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ ++ ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ ++ ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Current Limitation Mode */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ ++} ADC_CURRLIMIT_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Channel sweep selection */ ++typedef enum ADC_SWEEP_enum ++{ ++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ ++} ADC_SWEEP_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* DMA request selection */ ++typedef enum ADC_DMASEL_enum ++{ ++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ ++} ADC_DMASEL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DAC - Digital/Analog Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Digital-to-Analog Converter */ ++typedef struct DAC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t EVCTRL; /* Event Input Control */ ++ register8_t reserved_0x04; ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0GAINCAL; /* Gain Calibration */ ++ register8_t CH0OFFSETCAL; /* Offset Calibration */ ++ register8_t CH1GAINCAL; /* Gain Calibration */ ++ register8_t CH1OFFSETCAL; /* Offset Calibration */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ ++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ ++} DAC_t; ++ ++/* Output channel selection */ ++typedef enum DAC_CHSEL_enum ++{ ++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ ++ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ ++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ ++} DAC_CHSEL_t; ++ ++/* Reference voltage selection */ ++typedef enum DAC_REFSEL_enum ++{ ++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ ++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ ++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ ++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ ++} DAC_REFSEL_t; ++ ++/* Event channel selection */ ++typedef enum DAC_EVSEL_enum ++{ ++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ ++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ ++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ ++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ ++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ ++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ ++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ ++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ ++} DAC_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* SDA Hold Time */ ++typedef enum TWI_SDAHOLD_enum ++{ ++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ ++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ ++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ ++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ ++} TWI_SDAHOLD_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USB - USB ++-------------------------------------------------------------------------- ++*/ ++ ++/* USB Endpoint */ ++typedef struct USB_EP_struct ++{ ++ register8_t STATUS; /* Endpoint Status */ ++ register8_t CTRL; /* Endpoint Control */ ++ _WORDREGISTER(CNT); /* USB Endpoint Counter */ ++ _WORDREGISTER(DATAPTR); /* Data Pointer */ ++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ ++} USB_EP_t; ++ ++ ++/* Universal Serial Bus */ ++typedef struct USB_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t FIFOWP; /* FIFO Write Pointer Register */ ++ register8_t FIFORP; /* FIFO Read Pointer Register */ ++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ ++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ ++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ ++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t reserved_0x20; ++ register8_t reserved_0x21; ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t CAL0; /* Calibration Byte 0 */ ++ register8_t CAL1; /* Calibration Byte 1 */ ++} USB_t; ++ ++ ++/* USB Endpoint Table */ ++typedef struct USB_EP_TABLE_struct ++{ ++ USB_EP_t EP0OUT; /* Endpoint 0 */ ++ USB_EP_t EP0IN; /* Endpoint 0 */ ++ USB_EP_t EP1OUT; /* Endpoint 1 */ ++ USB_EP_t EP1IN; /* Endpoint 1 */ ++ USB_EP_t EP2OUT; /* Endpoint 2 */ ++ USB_EP_t EP2IN; /* Endpoint 2 */ ++ USB_EP_t EP3OUT; /* Endpoint 3 */ ++ USB_EP_t EP3IN; /* Endpoint 3 */ ++ USB_EP_t EP4OUT; /* Endpoint 4 */ ++ USB_EP_t EP4IN; /* Endpoint 4 */ ++ USB_EP_t EP5OUT; /* Endpoint 5 */ ++ USB_EP_t EP5IN; /* Endpoint 5 */ ++ USB_EP_t EP6OUT; /* Endpoint 6 */ ++ USB_EP_t EP6IN; /* Endpoint 6 */ ++ USB_EP_t EP7OUT; /* Endpoint 7 */ ++ USB_EP_t EP7IN; /* Endpoint 7 */ ++ USB_EP_t EP8OUT; /* Endpoint 8 */ ++ USB_EP_t EP8IN; /* Endpoint 8 */ ++ USB_EP_t EP9OUT; /* Endpoint 9 */ ++ USB_EP_t EP9IN; /* Endpoint 9 */ ++ USB_EP_t EP10OUT; /* Endpoint 10 */ ++ USB_EP_t EP10IN; /* Endpoint 10 */ ++ USB_EP_t EP11OUT; /* Endpoint 11 */ ++ USB_EP_t EP11IN; /* Endpoint 11 */ ++ USB_EP_t EP12OUT; /* Endpoint 12 */ ++ USB_EP_t EP12IN; /* Endpoint 12 */ ++ USB_EP_t EP13OUT; /* Endpoint 13 */ ++ USB_EP_t EP13IN; /* Endpoint 13 */ ++ USB_EP_t EP14OUT; /* Endpoint 14 */ ++ USB_EP_t EP14IN; /* Endpoint 14 */ ++ USB_EP_t EP15OUT; /* Endpoint 15 */ ++ USB_EP_t EP15IN; /* Endpoint 15 */ ++ register8_t reserved_0x100; ++ register8_t reserved_0x101; ++ register8_t reserved_0x102; ++ register8_t reserved_0x103; ++ register8_t reserved_0x104; ++ register8_t reserved_0x105; ++ register8_t reserved_0x106; ++ register8_t reserved_0x107; ++ register8_t reserved_0x108; ++ register8_t reserved_0x109; ++ register8_t reserved_0x10A; ++ register8_t reserved_0x10B; ++ register8_t reserved_0x10C; ++ register8_t reserved_0x10D; ++ register8_t reserved_0x10E; ++ register8_t reserved_0x10F; ++ register8_t FRAMENUML; /* Frame Number Low Byte */ ++ register8_t FRAMENUMH; /* Frame Number High Byte */ ++} USB_EP_TABLE_t; ++ ++/* Interrupt level */ ++typedef enum USB_INTLVL_enum ++{ ++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} USB_INTLVL_t; ++ ++/* USB Endpoint Type */ ++typedef enum USB_EP_TYPE_enum ++{ ++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ ++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ ++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ ++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ ++} USB_EP_TYPE_t; ++ ++/* USB Endpoint Buffersize */ ++typedef enum USB_EP_BUFSIZE_enum ++{ ++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ ++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ ++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ ++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ ++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ ++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ ++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ ++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ ++} USB_EP_BUFSIZE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - I/O Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* I/O Port Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Byte Mode */ ++typedef enum TC_BYTEM_enum ++{ ++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ ++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ ++} TC_BYTEM_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC2 - 16-bit Timer/Counter type 2 ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter type 2 */ ++typedef struct TC2_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t reserved_0x03; ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t reserved_0x08; ++ register8_t CTRLF; /* Control Register F */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t LCNT; /* Low Byte Count */ ++ register8_t HCNT; /* High Byte Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t LPER; /* Low Byte Period */ ++ register8_t HPER; /* High Byte Period */ ++ register8_t LCMPA; /* Low Byte Compare A */ ++ register8_t HCMPA; /* High Byte Compare A */ ++ register8_t LCMPB; /* Low Byte Compare B */ ++ register8_t HCMPB; /* High Byte Compare B */ ++ register8_t LCMPC; /* Low Byte Compare C */ ++ register8_t HCMPC; /* High Byte Compare C */ ++ register8_t LCMPD; /* Low Byte Compare D */ ++ register8_t HCMPD; /* High Byte Compare D */ ++} TC2_t; ++ ++/* Clock Selection */ ++typedef enum TC2_CLKSEL_enum ++{ ++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC2_CLKSEL_t; ++ ++/* Byte Mode */ ++typedef enum TC2_BYTEM_enum ++{ ++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ ++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ ++} TC2_BYTEM_t; ++ ++/* High Byte Underflow Interrupt Level */ ++typedef enum TC2_HUNFINTLVL_enum ++{ ++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_HUNFINTLVL_t; ++ ++/* Low Byte Underflow Interrupt Level */ ++typedef enum TC2_LUNFINTLVL_enum ++{ ++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LUNFINTLVL_t; ++ ++/* Low Byte Compare D Interrupt Level */ ++typedef enum TC2_LCMPDINTLVL_enum ++{ ++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC2_LCMPDINTLVL_t; ++ ++/* Low Byte Compare C Interrupt Level */ ++typedef enum TC2_LCMPCINTLVL_enum ++{ ++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC2_LCMPCINTLVL_t; ++ ++/* Low Byte Compare B Interrupt Level */ ++typedef enum TC2_LCMPBINTLVL_enum ++{ ++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_LCMPBINTLVL_t; ++ ++/* Low Byte Compare A Interrupt Level */ ++typedef enum TC2_LCMPAINTLVL_enum ++{ ++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LCMPAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMD_enum ++{ ++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC2_CMD_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMDEN_enum ++{ ++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ ++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ ++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ ++} TC2_CMDEN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AWEX - Timer/Counter Advanced Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - Timer/Counter High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t reserved_0x00; ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* Timer Oscillator pin location */ ++typedef enum TOSCSEL_enum ++{ ++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ ++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ ++} TOSCSEL_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* BOD operation */ ++typedef enum BODACT_enum ++{ ++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BODACT_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WDP_enum ++{ ++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ ++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ ++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ ++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ ++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ ++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ ++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ ++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ ++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ ++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ ++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ ++} WDP_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LOCKBIT - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ ++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t USBCAL0; /* USB Calibration Byte 0 */ ++ register8_t USBCAL1; /* USB Calibration Byte 1 */ ++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ ++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ ++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ ++ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ ++ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ ++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ ++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ ++ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ ++ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++ register8_t reserved_0x40; ++ register8_t reserved_0x41; ++ register8_t reserved_0x42; ++ register8_t reserved_0x43; ++ register8_t reserved_0x44; ++ register8_t reserved_0x45; ++ register8_t reserved_0x46; ++ register8_t reserved_0x47; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define AES (*(AES_t *) 0x00C0) /* AES Module */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ ++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ ++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ ++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ ++#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ ++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ ++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++#define GPIO_GPIOR4 _SFR_MEM8(0x0004) ++#define GPIO_GPIOR5 _SFR_MEM8(0x0005) ++#define GPIO_GPIOR6 _SFR_MEM8(0x0006) ++#define GPIO_GPIOR7 _SFR_MEM8(0x0007) ++#define GPIO_GPIOR8 _SFR_MEM8(0x0008) ++#define GPIO_GPIOR9 _SFR_MEM8(0x0009) ++#define GPIO_GPIORA _SFR_MEM8(0x000A) ++#define GPIO_GPIORB _SFR_MEM8(0x000B) ++#define GPIO_GPIORC _SFR_MEM8(0x000C) ++#define GPIO_GPIORD _SFR_MEM8(0x000D) ++#define GPIO_GPIORE _SFR_MEM8(0x000E) ++#define GPIO_GPIORF _SFR_MEM8(0x000F) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++#define GPIO_GPIO4 _SFR_MEM8(0x0004) ++#define GPIO_GPIO5 _SFR_MEM8(0x0005) ++#define GPIO_GPIO6 _SFR_MEM8(0x0006) ++#define GPIO_GPIO7 _SFR_MEM8(0x0007) ++#define GPIO_GPIO8 _SFR_MEM8(0x0008) ++#define GPIO_GPIO9 _SFR_MEM8(0x0009) ++#define GPIO_GPIOA _SFR_MEM8(0x000A) ++#define GPIO_GPIOB _SFR_MEM8(0x000B) ++#define GPIO_GPIOC _SFR_MEM8(0x000C) ++#define GPIO_GPIOD _SFR_MEM8(0x000D) ++#define GPIO_GPIOE _SFR_MEM8(0x000E) ++#define GPIO_GPIOF _SFR_MEM8(0x000F) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) ++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) ++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) ++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) ++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) ++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) ++#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) ++#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) ++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) ++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) ++#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) ++#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++#define CLK_USBCTRL _SFR_MEM8(0x0044) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLL - DFLL */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPB _SFR_MEM8(0x0072) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) ++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) ++ ++/* AES - AES Module */ ++#define AES_CTRL _SFR_MEM8(0x00C0) ++#define AES_STATUS _SFR_MEM8(0x00C1) ++#define AES_STATE _SFR_MEM8(0x00C2) ++#define AES_KEY _SFR_MEM8(0x00C3) ++#define AES_INTCTRL _SFR_MEM8(0x00C4) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* DMA - DMA Controller */ ++#define DMA_CTRL _SFR_MEM8(0x0100) ++#define DMA_INTFLAGS _SFR_MEM8(0x0103) ++#define DMA_STATUS _SFR_MEM8(0x0104) ++#define DMA_TEMP _SFR_MEM16(0x0106) ++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) ++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) ++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) ++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) ++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) ++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) ++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) ++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) ++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) ++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) ++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) ++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) ++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) ++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) ++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) ++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) ++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) ++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) ++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) ++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) ++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) ++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) ++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) ++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) ++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) ++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) ++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) ++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) ++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) ++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) ++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) ++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) ++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) ++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) ++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) ++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) ++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) ++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) ++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) ++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) ++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) ++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH4MUX _SFR_MEM8(0x0184) ++#define EVSYS_CH5MUX _SFR_MEM8(0x0185) ++#define EVSYS_CH6MUX _SFR_MEM8(0x0186) ++#define EVSYS_CH7MUX _SFR_MEM8(0x0187) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) ++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) ++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) ++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CH1RES _SFR_MEM16(0x0212) ++#define ADCA_CH2RES _SFR_MEM16(0x0214) ++#define ADCA_CH3RES _SFR_MEM16(0x0216) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) ++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) ++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) ++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) ++#define ADCA_CH1_RES _SFR_MEM16(0x022C) ++#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) ++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) ++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) ++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) ++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) ++#define ADCA_CH2_RES _SFR_MEM16(0x0234) ++#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) ++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) ++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) ++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) ++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) ++#define ADCA_CH3_RES _SFR_MEM16(0x023C) ++#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) ++ ++/* DAC - Digital-to-Analog Converter */ ++#define DACB_CTRLA _SFR_MEM8(0x0320) ++#define DACB_CTRLB _SFR_MEM8(0x0321) ++#define DACB_CTRLC _SFR_MEM8(0x0322) ++#define DACB_EVCTRL _SFR_MEM8(0x0323) ++#define DACB_STATUS _SFR_MEM8(0x0325) ++#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) ++#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) ++#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) ++#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) ++#define DACB_CH0DATA _SFR_MEM16(0x0338) ++#define DACB_CH1DATA _SFR_MEM16(0x033A) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* USB - Universal Serial Bus */ ++#define USB_CTRLA _SFR_MEM8(0x04C0) ++#define USB_CTRLB _SFR_MEM8(0x04C1) ++#define USB_STATUS _SFR_MEM8(0x04C2) ++#define USB_ADDR _SFR_MEM8(0x04C3) ++#define USB_FIFOWP _SFR_MEM8(0x04C4) ++#define USB_FIFORP _SFR_MEM8(0x04C5) ++#define USB_EPPTR _SFR_MEM16(0x04C6) ++#define USB_INTCTRLA _SFR_MEM8(0x04C8) ++#define USB_INTCTRLB _SFR_MEM8(0x04C9) ++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) ++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) ++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) ++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) ++#define USB_CAL0 _SFR_MEM8(0x04FA) ++#define USB_CAL1 _SFR_MEM8(0x04FB) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_REMAP _SFR_MEM8(0x060E) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_REMAP _SFR_MEM8(0x062E) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_REMAP _SFR_MEM8(0x068E) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCC2_CTRLA _SFR_MEM8(0x0800) ++#define TCC2_CTRLB _SFR_MEM8(0x0801) ++#define TCC2_CTRLC _SFR_MEM8(0x0802) ++#define TCC2_CTRLE _SFR_MEM8(0x0804) ++#define TCC2_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC2_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC2_CTRLF _SFR_MEM8(0x0809) ++#define TCC2_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC2_LCNT _SFR_MEM8(0x0820) ++#define TCC2_HCNT _SFR_MEM8(0x0821) ++#define TCC2_LPER _SFR_MEM8(0x0826) ++#define TCC2_HPER _SFR_MEM8(0x0827) ++#define TCC2_LCMPA _SFR_MEM8(0x0828) ++#define TCC2_HCMPA _SFR_MEM8(0x0829) ++#define TCC2_LCMPB _SFR_MEM8(0x082A) ++#define TCC2_HCMPB _SFR_MEM8(0x082B) ++#define TCC2_LCMPC _SFR_MEM8(0x082C) ++#define TCC2_HCMPC _SFR_MEM8(0x082D) ++#define TCC2_LCMPD _SFR_MEM8(0x082E) ++#define TCC2_HCMPD _SFR_MEM8(0x082F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_STATUSSET _SFR_MEM8(0x0885) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1_DATA _SFR_MEM8(0x08B0) ++#define USARTC1_STATUS _SFR_MEM8(0x08B1) ++#define USARTC1_CTRLA _SFR_MEM8(0x08B3) ++#define USARTC1_CTRLB _SFR_MEM8(0x08B4) ++#define USARTC1_CTRLC _SFR_MEM8(0x08B5) ++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) ++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCD2_CTRLA _SFR_MEM8(0x0900) ++#define TCD2_CTRLB _SFR_MEM8(0x0901) ++#define TCD2_CTRLC _SFR_MEM8(0x0902) ++#define TCD2_CTRLE _SFR_MEM8(0x0904) ++#define TCD2_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD2_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD2_CTRLF _SFR_MEM8(0x0909) ++#define TCD2_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD2_LCNT _SFR_MEM8(0x0920) ++#define TCD2_HCNT _SFR_MEM8(0x0921) ++#define TCD2_LPER _SFR_MEM8(0x0926) ++#define TCD2_HPER _SFR_MEM8(0x0927) ++#define TCD2_LCMPA _SFR_MEM8(0x0928) ++#define TCD2_HCMPA _SFR_MEM8(0x0929) ++#define TCD2_LCMPB _SFR_MEM8(0x092A) ++#define TCD2_HCMPB _SFR_MEM8(0x092B) ++#define TCD2_LCMPC _SFR_MEM8(0x092C) ++#define TCD2_HCMPC _SFR_MEM8(0x092D) ++#define TCD2_LCMPD _SFR_MEM8(0x092E) ++#define TCD2_HCMPD _SFR_MEM8(0x092F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCD1_CTRLA _SFR_MEM8(0x0940) ++#define TCD1_CTRLB _SFR_MEM8(0x0941) ++#define TCD1_CTRLC _SFR_MEM8(0x0942) ++#define TCD1_CTRLD _SFR_MEM8(0x0943) ++#define TCD1_CTRLE _SFR_MEM8(0x0944) ++#define TCD1_INTCTRLA _SFR_MEM8(0x0946) ++#define TCD1_INTCTRLB _SFR_MEM8(0x0947) ++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) ++#define TCD1_CTRLFSET _SFR_MEM8(0x0949) ++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) ++#define TCD1_CTRLGSET _SFR_MEM8(0x094B) ++#define TCD1_INTFLAGS _SFR_MEM8(0x094C) ++#define TCD1_TEMP _SFR_MEM8(0x094F) ++#define TCD1_CNT _SFR_MEM16(0x0960) ++#define TCD1_PER _SFR_MEM16(0x0966) ++#define TCD1_CCA _SFR_MEM16(0x0968) ++#define TCD1_CCB _SFR_MEM16(0x096A) ++#define TCD1_PERBUF _SFR_MEM16(0x0976) ++#define TCD1_CCABUF _SFR_MEM16(0x0978) ++#define TCD1_CCBBUF _SFR_MEM16(0x097A) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESD_CTRLA _SFR_MEM8(0x0990) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD1_DATA _SFR_MEM8(0x09B0) ++#define USARTD1_STATUS _SFR_MEM8(0x09B1) ++#define USARTD1_CTRLA _SFR_MEM8(0x09B3) ++#define USARTD1_CTRLB _SFR_MEM8(0x09B4) ++#define USARTD1_CTRLC _SFR_MEM8(0x09B5) ++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) ++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESE_CTRLA _SFR_MEM8(0x0A90) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* CLK.USBCTRL bit masks and bit positions */ ++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ ++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ ++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ ++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ ++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ ++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ ++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ ++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ ++ ++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ ++#define CLK_USBSRC_gp 1 /* Clock Source group position. */ ++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ ++ ++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_USB_bm 0x40 /* USB bit mask. */ ++#define PR_USB_bp 6 /* USB bit position. */ ++ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ ++#define PR_EBI_bp 3 /* External Bus Interface bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ ++#define PR_DAC_bp 2 /* Port A DAC bit position. */ ++ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPB bit masks and bit positions */ ++/* PR_DAC Predefined. */ ++/* PR_DAC Predefined. */ ++ ++/* PR_ADC Predefined. */ ++/* PR_ADC Predefined. */ ++ ++/* PR_AC Predefined. */ ++/* PR_AC Predefined. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ ++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ ++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ ++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ ++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ ++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ ++ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ ++#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ ++ ++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ ++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ ++ ++#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ ++#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ ++ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ ++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ ++ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ ++ ++/* PORTCFG.EBIOUT bit masks and bit positions */ ++#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ ++#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ ++#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ ++#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ ++#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ ++#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ ++ ++#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ ++#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ ++#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ ++#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ ++#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ ++#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ ++ ++/* PORTCFG.EVOUTSEL bit masks and bit positions */ ++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ ++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ ++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ ++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ ++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ ++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ ++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ ++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ ++ ++/* AES - AES Module */ ++/* AES.CTRL bit masks and bit positions */ ++#define AES_START_bm 0x80 /* Start/Run bit mask. */ ++#define AES_START_bp 7 /* Start/Run bit position. */ ++ ++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ ++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ ++ ++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ ++#define AES_RESET_bp 5 /* AES Software Reset bit position. */ ++ ++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ ++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ ++ ++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ ++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ ++ ++/* AES.STATUS bit masks and bit positions */ ++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ ++#define AES_ERROR_bp 7 /* AES Error bit position. */ ++ ++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ ++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ ++ ++/* AES.INTCTRL bit masks and bit positions */ ++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define AES_INTLVL_gp 0 /* Interrupt level group position. */ ++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* DMA - DMA Controller */ ++/* DMA_CH.CTRLA bit masks and bit positions */ ++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ ++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ ++ ++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ ++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ ++ ++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ ++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ ++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ ++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ ++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ ++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ ++ ++/* DMA_CH.CTRLB bit masks and bit positions */ ++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ ++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ ++ ++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ ++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ ++ ++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ ++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ ++ ++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ ++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ ++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ ++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ ++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ ++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ ++ ++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ ++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ ++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ ++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ ++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ ++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ ++ ++/* DMA_CH.ADDRCTRL bit masks and bit positions */ ++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ ++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ ++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ ++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ ++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ ++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ ++ ++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ ++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ ++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ ++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ ++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ ++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ ++ ++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ ++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ ++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ ++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ ++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ ++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ ++ ++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ ++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ ++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ ++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ ++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ ++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ ++ ++/* DMA_CH.TRIGSRC bit masks and bit positions */ ++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++/* DMA.CTRL bit masks and bit positions */ ++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define DMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define DMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ ++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ ++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ ++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ ++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ ++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ ++ ++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ ++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ ++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ ++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ ++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ ++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ ++ ++/* DMA.INTFLAGS bit masks and bit positions */ ++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++/* DMA.STATUS bit masks and bit positions */ ++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ ++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ ++ ++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ ++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ ++ ++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ ++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ ++ ++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ ++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ ++ ++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ ++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ ++ ++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ ++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ ++ ++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ ++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ ++ ++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ ++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH4MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH5MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH6MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH7MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM Predefined. */ ++/* EVSYS_QDIRM Predefined. */ ++ ++/* EVSYS_QDIEN Predefined. */ ++/* EVSYS_QDIEN Predefined. */ ++ ++/* EVSYS_QDEN Predefined. */ ++/* EVSYS_QDEN Predefined. */ ++ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH4CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM Predefined. */ ++/* EVSYS_QDIRM Predefined. */ ++ ++/* EVSYS_QDIEN Predefined. */ ++/* EVSYS_QDIEN Predefined. */ ++ ++/* EVSYS_QDEN Predefined. */ ++/* EVSYS_QDEN Predefined. */ ++ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH5CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH6CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH7CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ ++#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ ++#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ ++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ ++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ ++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ ++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ ++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ ++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ ++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ ++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ ++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ ++ ++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ ++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ ++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ ++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ ++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ ++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ ++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ ++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ ++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ ++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ ++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ ++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ ++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ ++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ ++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ ++ ++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ ++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ ++ ++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ ++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ ++ ++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ ++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ ++ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ ++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ ++#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ ++ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ ++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ ++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ ++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ ++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ ++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ ++ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ ++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ ++ ++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ ++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ ++ ++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ ++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ ++ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* DAC - Digital/Analog Converter */ ++/* DAC.CTRLA bit masks and bit positions */ ++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ ++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ ++ ++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ ++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ ++ ++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ ++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ ++ ++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ ++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ ++ ++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define DAC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* DAC.CTRLB bit masks and bit positions */ ++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ ++#define DAC_CHSEL_gp 5 /* Channel Select group position. */ ++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ ++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ ++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ ++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ ++ ++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ ++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ ++ ++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ ++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ ++ ++/* DAC.CTRLC bit masks and bit positions */ ++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ ++#define DAC_REFSEL_gp 3 /* Reference Select group position. */ ++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ ++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ ++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ ++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ ++ ++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ ++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ ++ ++/* DAC.EVCTRL bit masks and bit positions */ ++#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ ++#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ ++ ++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ ++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ ++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ ++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ ++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ ++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ ++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ ++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ ++ ++/* DAC.STATUS bit masks and bit positions */ ++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ ++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ ++ ++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ ++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ ++ ++/* DAC.CH0GAINCAL bit masks and bit positions */ ++#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH0OFFSETCAL bit masks and bit positions */ ++#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* DAC.CH1GAINCAL bit masks and bit positions */ ++#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH1OFFSETCAL bit masks and bit positions */ ++#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ ++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HSMODE Predefined. */ ++/* AC_HSMODE Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* RTC - Real-Time Counter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* USB - USB */ ++/* USB_EP.STATUS bit masks and bit positions */ ++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ ++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ ++ ++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ ++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ ++ ++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ ++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ ++ ++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ ++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ ++ ++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ ++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ ++ ++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ ++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ ++ ++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ ++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ ++ ++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ ++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ ++ ++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ ++ ++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ ++ ++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ ++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ ++ ++/* USB_EP.CTRL bit masks and bit positions */ ++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ ++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ ++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ ++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ ++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ ++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ ++ ++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ ++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ ++ ++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ ++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ ++ ++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ ++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ ++ ++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ ++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ ++ ++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ ++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ ++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ ++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ ++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ ++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ ++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ ++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ ++ ++/* USB_EP.CNT bit masks and bit positions */ ++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ ++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ ++ ++/* USB.CTRLA bit masks and bit positions */ ++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ ++#define USB_ENABLE_bp 7 /* USB Enable bit position. */ ++ ++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ ++#define USB_SPEED_bp 6 /* Speed Select bit position. */ ++ ++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ ++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ ++ ++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ ++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ ++ ++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ ++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ ++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ ++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ ++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ ++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ ++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ ++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ ++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ ++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ ++ ++/* USB.CTRLB bit masks and bit positions */ ++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ ++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ ++ ++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ ++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ ++ ++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ ++#define USB_GNACK_bp 1 /* Global NACK bit position. */ ++ ++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ ++#define USB_ATTACH_bp 0 /* Attach bit position. */ ++ ++/* USB.STATUS bit masks and bit positions */ ++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ ++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ ++ ++#define USB_RESUME_bm 0x04 /* Resume bit mask. */ ++#define USB_RESUME_bp 2 /* Resume bit position. */ ++ ++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ ++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ ++ ++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ ++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ ++ ++/* USB.ADDR bit masks and bit positions */ ++#define USB_ADDR_gm 0x7F /* Device Address group mask. */ ++#define USB_ADDR_gp 0 /* Device Address group position. */ ++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ ++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ ++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ ++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ ++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ ++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ ++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ ++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ ++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ ++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ ++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ ++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ ++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ ++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ ++ ++/* USB.FIFOWP bit masks and bit positions */ ++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ ++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ ++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ ++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ ++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ ++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ ++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ ++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ ++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ ++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ ++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ ++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ ++ ++/* USB.FIFORP bit masks and bit positions */ ++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ ++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ ++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ ++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ ++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ ++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ ++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ ++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ ++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ ++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ ++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ ++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ ++ ++/* USB.INTCTRLA bit masks and bit positions */ ++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ ++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ ++ ++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ ++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ ++ ++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ ++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ ++ ++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ ++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ ++ ++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* USB.INTCTRLB bit masks and bit positions */ ++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ ++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ ++ ++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ ++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ ++ ++/* USB.INTFLAGSACLR bit masks and bit positions */ ++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ ++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ ++ ++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ ++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ ++ ++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ ++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ ++ ++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ ++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ ++ ++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ ++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ ++ ++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ ++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ ++ ++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ ++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ ++ ++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ ++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSASET bit masks and bit positions */ ++/* USB_SOFIF Predefined. */ ++/* USB_SOFIF Predefined. */ ++ ++/* USB_SUSPENDIF Predefined. */ ++/* USB_SUSPENDIF Predefined. */ ++ ++/* USB_RESUMEIF Predefined. */ ++/* USB_RESUMEIF Predefined. */ ++ ++/* USB_RSTIF Predefined. */ ++/* USB_RSTIF Predefined. */ ++ ++/* USB_CRCIF Predefined. */ ++/* USB_CRCIF Predefined. */ ++ ++/* USB_UNFIF Predefined. */ ++/* USB_UNFIF Predefined. */ ++ ++/* USB_OVFIF Predefined. */ ++/* USB_OVFIF Predefined. */ ++ ++/* USB_STALLIF Predefined. */ ++/* USB_STALLIF Predefined. */ ++ ++/* USB.INTFLAGSBCLR bit masks and bit positions */ ++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ ++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ ++ ++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ ++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSBSET bit masks and bit positions */ ++/* USB_TRNIF Predefined. */ ++/* USB_TRNIF Predefined. */ ++ ++/* USB_SETUPIF Predefined. */ ++/* USB_SETUPIF Predefined. */ ++ ++/* PORT - I/O Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_SPI_bm 0x20 /* SPI bit mask. */ ++#define PORT_SPI_bp 5 /* SPI bit position. */ ++ ++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ ++#define PORT_USART0_bp 4 /* USART0 bit position. */ ++ ++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ ++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ ++ ++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ ++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ ++ ++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ ++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ ++ ++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ ++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD Predefined. */ ++/* TC0_CMD Predefined. */ ++ ++/* TC0_LUPD Predefined. */ ++/* TC0_LUPD Predefined. */ ++ ++/* TC0_DIR Predefined. */ ++/* TC0_DIR Predefined. */ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV Predefined. */ ++/* TC0_CCDBV Predefined. */ ++ ++/* TC0_CCCBV Predefined. */ ++/* TC0_CCCBV Predefined. */ ++ ++/* TC0_CCBBV Predefined. */ ++/* TC0_CCBBV Predefined. */ ++ ++/* TC0_CCABV Predefined. */ ++/* TC0_CCABV Predefined. */ ++ ++/* TC0_PERBV Predefined. */ ++/* TC0_PERBV Predefined. */ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD Predefined. */ ++/* TC1_CMD Predefined. */ ++ ++/* TC1_LUPD Predefined. */ ++/* TC1_LUPD Predefined. */ ++ ++/* TC1_DIR Predefined. */ ++/* TC1_DIR Predefined. */ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV Predefined. */ ++/* TC1_CCBBV Predefined. */ ++ ++/* TC1_CCABV Predefined. */ ++/* TC1_CCABV Predefined. */ ++ ++/* TC1_PERBV Predefined. */ ++/* TC1_PERBV Predefined. */ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++/* TC2.CTRLA bit masks and bit positions */ ++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC2.CTRLB bit masks and bit positions */ ++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ ++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ ++ ++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ ++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ ++ ++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ ++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ ++ ++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ ++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ ++ ++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ ++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ ++ ++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ ++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ ++ ++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ ++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ ++ ++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ ++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ ++ ++/* TC2.CTRLC bit masks and bit positions */ ++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ ++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ ++ ++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ ++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ ++ ++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ ++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ ++ ++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ ++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ ++ ++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ ++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ ++ ++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ ++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ ++ ++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ ++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ ++ ++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ ++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ ++ ++/* TC2.CTRLE bit masks and bit positions */ ++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC2.INTCTRLA bit masks and bit positions */ ++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ ++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ ++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ ++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ ++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ ++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ ++ ++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ ++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ ++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ ++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ ++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ ++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ ++ ++/* TC2.INTCTRLB bit masks and bit positions */ ++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ ++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ ++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ ++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ ++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ ++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ ++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ ++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ ++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ ++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ ++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ ++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ ++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ ++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ ++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ ++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ ++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ ++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ ++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ ++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ ++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ ++ ++/* TC2.CTRLF bit masks and bit positions */ ++#define TC2_CMD_gm 0x0C /* Command group mask. */ ++#define TC2_CMD_gp 2 /* Command group position. */ ++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC2_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC2_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ ++#define TC2_CMDEN_gp 0 /* Command Enable group position. */ ++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ ++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ ++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ ++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ ++ ++/* TC2.INTFLAGS bit masks and bit positions */ ++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ ++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ ++ ++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ ++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ ++ ++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ ++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ ++ ++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ ++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ ++ ++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ ++ ++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ ++ ++/* AWEX - Timer/Counter Advanced Waveform Extension */ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++/* AWEX.STATUSSET bit masks and bit positions */ ++/* AWEX_FDF Predefined. */ ++/* AWEX_FDF Predefined. */ ++ ++/* AWEX_DTHSBUFV Predefined. */ ++/* AWEX_DTHSBUFV Predefined. */ ++ ++/* AWEX_DTLSBUFV Predefined. */ ++/* AWEX_DTLSBUFV Predefined. */ ++ ++/* HIRES - Timer/Counter High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ ++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* LOCKBIT - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* DMA interrupt vectors */ ++#define DMA_CH0_vect_num 6 ++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ ++#define DMA_CH1_vect_num 7 ++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ ++#define DMA_CH2_vect_num 8 ++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ ++#define DMA_CH3_vect_num 9 ++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LUNF_vect_num 14 ++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_HUNF_vect_num 15 ++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPA_vect_num 16 ++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPB_vect_num 17 ++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPC_vect_num 18 ++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPD_vect_num 19 ++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* USARTC1 interrupt vectors */ ++#define USARTC1_RXC_vect_num 28 ++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ ++#define USARTC1_DRE_vect_num 29 ++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ ++#define USARTC1_TXC_vect_num 30 ++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ ++ ++/* AES interrupt vectors */ ++#define AES_INT_vect_num 31 ++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++#define ADCA_CH1_vect_num 72 ++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ ++#define ADCA_CH2_vect_num 73 ++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ ++#define ADCA_CH3_vect_num 74 ++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LUNF_vect_num 77 ++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_HUNF_vect_num 78 ++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPA_vect_num 79 ++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPB_vect_num 80 ++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPC_vect_num 81 ++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPD_vect_num 82 ++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ ++ ++/* TCD1 interrupt vectors */ ++#define TCD1_OVF_vect_num 83 ++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ ++#define TCD1_ERR_vect_num 84 ++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ ++#define TCD1_CCA_vect_num 85 ++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ ++#define TCD1_CCB_vect_num 86 ++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* USARTD1 interrupt vectors */ ++#define USARTD1_RXC_vect_num 91 ++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ ++#define USARTD1_DRE_vect_num 92 ++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ ++#define USARTD1_TXC_vect_num 93 ++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ ++ ++/* USB interrupt vectors */ ++#define USB_BUSEVENT_vect_num 125 ++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ ++#define USB_TRNCOMPL_vect_num 126 ++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (127 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (20480) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (16384) ++#define APP_SECTION_PAGE_SIZE (256) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x3000) ++#define APPTABLE_SECTION_SIZE (4096) ++#define APPTABLE_SECTION_PAGE_SIZE (256) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x4000) ++#define BOOT_SECTION_SIZE (4096) ++#define BOOT_SECTION_PAGE_SIZE (256) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (10240) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (1024) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (2048) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (1024) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (6) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (256) ++#define USER_SIGNATURES_PAGE_SIZE (256) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (256) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 256 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 Reserved */ ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x41 ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA16A4U_H_INCLUDED */ ++ +diff --git a/include/avr/iox16c4.h b/include/avr/iox16c4.h +new file mode 100644 +index 0000000..9ef9778 +--- /dev/null ++++ b/include/avr/iox16c4.h +@@ -0,0 +1,6030 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox16c4.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA16C4_H_INCLUDED ++#define _AVR_ATXMEGA16C4_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t USBCTRL; /* USB Control Register */ ++} CLK_t; ++ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t reserved_0x02; ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++/* USB Prescaler Division Factor */ ++typedef enum CLK_USBPSDIV_enum ++{ ++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ ++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ ++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ ++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ ++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ ++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ ++} CLK_USBPSDIV_t; ++ ++/* USB Clock Source */ ++typedef enum CLK_USBSRC_enum ++{ ++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ ++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ ++} CLK_USBSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 2 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC2MCREF_enum ++{ ++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC2MCREF_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++ register8_t reserved_0x05; ++ register8_t EVOUTSEL; /* Event Output Select */ ++} PORTCFG_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP02MAP_enum ++{ ++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP02MAP_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP13MAP_enum ++{ ++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP13MAP_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t reserved_0x07; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++} ADC_t; ++ ++/* Current Limitation */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ ++} ADC_CURRLIMIT_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ ++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ ++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ ++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* SDA Hold Time */ ++typedef enum TWI_SDAHOLD_enum ++{ ++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ ++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ ++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ ++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ ++} TWI_SDAHOLD_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USB - USB ++-------------------------------------------------------------------------- ++*/ ++ ++/* USB Endpoint */ ++typedef struct USB_EP_struct ++{ ++ register8_t STATUS; /* Endpoint Status */ ++ register8_t CTRL; /* Endpoint Control */ ++ _WORDREGISTER(CNT); /* USB Endpoint Counter */ ++ _WORDREGISTER(DATAPTR); /* Data Pointer */ ++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ ++} USB_EP_t; ++ ++ ++/* Universal Serial Bus */ ++typedef struct USB_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t FIFOWP; /* FIFO Write Pointer Register */ ++ register8_t FIFORP; /* FIFO Read Pointer Register */ ++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ ++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ ++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ ++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t reserved_0x20; ++ register8_t reserved_0x21; ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t CAL0; /* Calibration Byte 0 */ ++ register8_t CAL1; /* Calibration Byte 1 */ ++} USB_t; ++ ++ ++/* USB Endpoint Table */ ++typedef struct USB_EP_TABLE_struct ++{ ++ USB_EP_t EP0OUT; /* Endpoint 0 */ ++ USB_EP_t EP0IN; /* Endpoint 0 */ ++ USB_EP_t EP1OUT; /* Endpoint 1 */ ++ USB_EP_t EP1IN; /* Endpoint 1 */ ++ USB_EP_t EP2OUT; /* Endpoint 2 */ ++ USB_EP_t EP2IN; /* Endpoint 2 */ ++ USB_EP_t EP3OUT; /* Endpoint 3 */ ++ USB_EP_t EP3IN; /* Endpoint 3 */ ++ USB_EP_t EP4OUT; /* Endpoint 4 */ ++ USB_EP_t EP4IN; /* Endpoint 4 */ ++ USB_EP_t EP5OUT; /* Endpoint 5 */ ++ USB_EP_t EP5IN; /* Endpoint 5 */ ++ USB_EP_t EP6OUT; /* Endpoint 6 */ ++ USB_EP_t EP6IN; /* Endpoint 6 */ ++ USB_EP_t EP7OUT; /* Endpoint 7 */ ++ USB_EP_t EP7IN; /* Endpoint 7 */ ++ USB_EP_t EP8OUT; /* Endpoint 8 */ ++ USB_EP_t EP8IN; /* Endpoint 8 */ ++ USB_EP_t EP9OUT; /* Endpoint 9 */ ++ USB_EP_t EP9IN; /* Endpoint 9 */ ++ USB_EP_t EP10OUT; /* Endpoint 10 */ ++ USB_EP_t EP10IN; /* Endpoint 10 */ ++ USB_EP_t EP11OUT; /* Endpoint 11 */ ++ USB_EP_t EP11IN; /* Endpoint 11 */ ++ USB_EP_t EP12OUT; /* Endpoint 12 */ ++ USB_EP_t EP12IN; /* Endpoint 12 */ ++ USB_EP_t EP13OUT; /* Endpoint 13 */ ++ USB_EP_t EP13IN; /* Endpoint 13 */ ++ USB_EP_t EP14OUT; /* Endpoint 14 */ ++ USB_EP_t EP14IN; /* Endpoint 14 */ ++ USB_EP_t EP15OUT; /* Endpoint 15 */ ++ USB_EP_t EP15IN; /* Endpoint 15 */ ++ register8_t reserved_0x100; ++ register8_t reserved_0x101; ++ register8_t reserved_0x102; ++ register8_t reserved_0x103; ++ register8_t reserved_0x104; ++ register8_t reserved_0x105; ++ register8_t reserved_0x106; ++ register8_t reserved_0x107; ++ register8_t reserved_0x108; ++ register8_t reserved_0x109; ++ register8_t reserved_0x10A; ++ register8_t reserved_0x10B; ++ register8_t reserved_0x10C; ++ register8_t reserved_0x10D; ++ register8_t reserved_0x10E; ++ register8_t reserved_0x10F; ++ register8_t FRAMENUML; /* Frame Number Low Byte */ ++ register8_t FRAMENUMH; /* Frame Number High Byte */ ++} USB_EP_TABLE_t; ++ ++/* Interrupt level */ ++typedef enum USB_INTLVL_enum ++{ ++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} USB_INTLVL_t; ++ ++/* USB Endpoint Type */ ++typedef enum USB_EP_TYPE_enum ++{ ++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ ++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ ++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ ++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ ++} USB_EP_TYPE_t; ++ ++/* USB Endpoint Buffersize */ ++typedef enum USB_EP_BUFSIZE_enum ++{ ++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ ++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ ++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ ++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ ++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ ++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ ++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ ++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ ++} USB_EP_BUFSIZE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - I/O Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* I/O Port Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Byte Mode */ ++typedef enum TC_BYTEM_enum ++{ ++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ ++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ ++} TC_BYTEM_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC2 - 16-bit Timer/Counter type 2 ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter type 2 */ ++typedef struct TC2_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t reserved_0x03; ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t reserved_0x08; ++ register8_t CTRLF; /* Control Register F */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t LCNT; /* Low Byte Count */ ++ register8_t HCNT; /* High Byte Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t LPER; /* Low Byte Period */ ++ register8_t HPER; /* High Byte Period */ ++ register8_t LCMPA; /* Low Byte Compare A */ ++ register8_t HCMPA; /* High Byte Compare A */ ++ register8_t LCMPB; /* Low Byte Compare B */ ++ register8_t HCMPB; /* High Byte Compare B */ ++ register8_t LCMPC; /* Low Byte Compare C */ ++ register8_t HCMPC; /* High Byte Compare C */ ++ register8_t LCMPD; /* Low Byte Compare D */ ++ register8_t HCMPD; /* High Byte Compare D */ ++} TC2_t; ++ ++/* Clock Selection */ ++typedef enum TC2_CLKSEL_enum ++{ ++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC2_CLKSEL_t; ++ ++/* Byte Mode */ ++typedef enum TC2_BYTEM_enum ++{ ++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ ++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ ++} TC2_BYTEM_t; ++ ++/* High Byte Underflow Interrupt Level */ ++typedef enum TC2_HUNFINTLVL_enum ++{ ++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_HUNFINTLVL_t; ++ ++/* Low Byte Underflow Interrupt Level */ ++typedef enum TC2_LUNFINTLVL_enum ++{ ++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LUNFINTLVL_t; ++ ++/* Low Byte Compare D Interrupt Level */ ++typedef enum TC2_LCMPDINTLVL_enum ++{ ++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC2_LCMPDINTLVL_t; ++ ++/* Low Byte Compare C Interrupt Level */ ++typedef enum TC2_LCMPCINTLVL_enum ++{ ++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC2_LCMPCINTLVL_t; ++ ++/* Low Byte Compare B Interrupt Level */ ++typedef enum TC2_LCMPBINTLVL_enum ++{ ++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_LCMPBINTLVL_t; ++ ++/* Low Byte Compare A Interrupt Level */ ++typedef enum TC2_LCMPAINTLVL_enum ++{ ++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LCMPAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMD_enum ++{ ++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC2_CMD_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMDEN_enum ++{ ++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ ++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ ++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ ++} TC2_CMDEN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AWEX - Timer/Counter Advanced Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - Timer/Counter High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t reserved_0x00; ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* Timer Oscillator pin location */ ++typedef enum TOSCSEL_enum ++{ ++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ ++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ ++} TOSCSEL_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* BOD operation */ ++typedef enum BODACT_enum ++{ ++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BODACT_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WDP_enum ++{ ++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ ++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ ++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ ++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ ++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ ++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ ++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ ++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ ++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ ++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ ++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ ++} WDP_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LOCKBIT - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ ++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t USBCAL0; /* USB Calibration Byte 0 */ ++ register8_t USBCAL1; /* USB Calibration Byte 1 */ ++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ ++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ ++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ ++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ ++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) ++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) ++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) ++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++#define CLK_USBCTRL _SFR_MEM8(0x0044) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLL - DFLL */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* USB - Universal Serial Bus */ ++#define USB_CTRLA _SFR_MEM8(0x04C0) ++#define USB_CTRLB _SFR_MEM8(0x04C1) ++#define USB_STATUS _SFR_MEM8(0x04C2) ++#define USB_ADDR _SFR_MEM8(0x04C3) ++#define USB_FIFOWP _SFR_MEM8(0x04C4) ++#define USB_FIFORP _SFR_MEM8(0x04C5) ++#define USB_EPPTR _SFR_MEM16(0x04C6) ++#define USB_INTCTRLA _SFR_MEM8(0x04C8) ++#define USB_INTCTRLB _SFR_MEM8(0x04C9) ++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) ++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) ++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) ++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) ++#define USB_CAL0 _SFR_MEM8(0x04FA) ++#define USB_CAL1 _SFR_MEM8(0x04FB) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_REMAP _SFR_MEM8(0x060E) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_REMAP _SFR_MEM8(0x062E) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_REMAP _SFR_MEM8(0x068E) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCC2_CTRLA _SFR_MEM8(0x0800) ++#define TCC2_CTRLB _SFR_MEM8(0x0801) ++#define TCC2_CTRLC _SFR_MEM8(0x0802) ++#define TCC2_CTRLE _SFR_MEM8(0x0804) ++#define TCC2_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC2_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC2_CTRLF _SFR_MEM8(0x0809) ++#define TCC2_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC2_LCNT _SFR_MEM8(0x0820) ++#define TCC2_HCNT _SFR_MEM8(0x0821) ++#define TCC2_LPER _SFR_MEM8(0x0826) ++#define TCC2_HPER _SFR_MEM8(0x0827) ++#define TCC2_LCMPA _SFR_MEM8(0x0828) ++#define TCC2_HCMPA _SFR_MEM8(0x0829) ++#define TCC2_LCMPB _SFR_MEM8(0x082A) ++#define TCC2_HCMPB _SFR_MEM8(0x082B) ++#define TCC2_LCMPC _SFR_MEM8(0x082C) ++#define TCC2_HCMPC _SFR_MEM8(0x082D) ++#define TCC2_LCMPD _SFR_MEM8(0x082E) ++#define TCC2_HCMPD _SFR_MEM8(0x082F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_STATUSSET _SFR_MEM8(0x0885) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1_DATA _SFR_MEM8(0x08B0) ++#define USARTC1_STATUS _SFR_MEM8(0x08B1) ++#define USARTC1_CTRLA _SFR_MEM8(0x08B3) ++#define USARTC1_CTRLB _SFR_MEM8(0x08B4) ++#define USARTC1_CTRLC _SFR_MEM8(0x08B5) ++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) ++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCD2_CTRLA _SFR_MEM8(0x0900) ++#define TCD2_CTRLB _SFR_MEM8(0x0901) ++#define TCD2_CTRLC _SFR_MEM8(0x0902) ++#define TCD2_CTRLE _SFR_MEM8(0x0904) ++#define TCD2_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD2_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD2_CTRLF _SFR_MEM8(0x0909) ++#define TCD2_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD2_LCNT _SFR_MEM8(0x0920) ++#define TCD2_HCNT _SFR_MEM8(0x0921) ++#define TCD2_LPER _SFR_MEM8(0x0926) ++#define TCD2_HPER _SFR_MEM8(0x0927) ++#define TCD2_LCMPA _SFR_MEM8(0x0928) ++#define TCD2_HCMPA _SFR_MEM8(0x0929) ++#define TCD2_LCMPB _SFR_MEM8(0x092A) ++#define TCD2_HCMPB _SFR_MEM8(0x092B) ++#define TCD2_LCMPC _SFR_MEM8(0x092C) ++#define TCD2_HCMPC _SFR_MEM8(0x092D) ++#define TCD2_LCMPD _SFR_MEM8(0x092E) ++#define TCD2_HCMPD _SFR_MEM8(0x092F) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* CLK.USBCTRL bit masks and bit positions */ ++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ ++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ ++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ ++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ ++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ ++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ ++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ ++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ ++ ++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ ++#define CLK_USBSRC_gp 1 /* Clock Source group position. */ ++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ ++ ++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_USB_bm 0x40 /* USB bit mask. */ ++#define PR_USB_bp 6 /* USB bit position. */ ++ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ ++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ ++ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ ++ ++/* PORTCFG.EVOUTSEL bit masks and bit positions */ ++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ ++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ ++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ ++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ ++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ ++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ ++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ ++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ ++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ ++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ ++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ ++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ ++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ ++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ ++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ ++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ ++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ ++ ++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ ++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ ++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ ++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ ++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ ++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ ++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ ++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ ++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ ++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ ++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* RTC - Real-Time Counter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* USB - USB */ ++/* USB_EP.STATUS bit masks and bit positions */ ++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ ++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ ++ ++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ ++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ ++ ++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ ++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ ++ ++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ ++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ ++ ++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ ++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ ++ ++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ ++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ ++ ++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ ++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ ++ ++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ ++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ ++ ++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ ++ ++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ ++ ++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ ++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ ++ ++/* USB_EP.CTRL bit masks and bit positions */ ++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ ++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ ++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ ++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ ++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ ++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ ++ ++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ ++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ ++ ++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ ++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ ++ ++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ ++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ ++ ++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ ++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ ++ ++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ ++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ ++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ ++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ ++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ ++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ ++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ ++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ ++ ++/* USB_EP.CNT bit masks and bit positions */ ++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ ++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ ++ ++/* USB.CTRLA bit masks and bit positions */ ++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ ++#define USB_ENABLE_bp 7 /* USB Enable bit position. */ ++ ++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ ++#define USB_SPEED_bp 6 /* Speed Select bit position. */ ++ ++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ ++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ ++ ++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ ++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ ++ ++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ ++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ ++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ ++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ ++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ ++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ ++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ ++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ ++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ ++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ ++ ++/* USB.CTRLB bit masks and bit positions */ ++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ ++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ ++ ++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ ++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ ++ ++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ ++#define USB_GNACK_bp 1 /* Global NACK bit position. */ ++ ++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ ++#define USB_ATTACH_bp 0 /* Attach bit position. */ ++ ++/* USB.STATUS bit masks and bit positions */ ++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ ++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ ++ ++#define USB_RESUME_bm 0x04 /* Resume bit mask. */ ++#define USB_RESUME_bp 2 /* Resume bit position. */ ++ ++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ ++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ ++ ++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ ++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ ++ ++/* USB.ADDR bit masks and bit positions */ ++#define USB_ADDR_gm 0x7F /* Device Address group mask. */ ++#define USB_ADDR_gp 0 /* Device Address group position. */ ++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ ++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ ++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ ++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ ++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ ++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ ++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ ++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ ++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ ++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ ++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ ++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ ++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ ++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ ++ ++/* USB.FIFOWP bit masks and bit positions */ ++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ ++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ ++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ ++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ ++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ ++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ ++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ ++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ ++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ ++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ ++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ ++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ ++ ++/* USB.FIFORP bit masks and bit positions */ ++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ ++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ ++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ ++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ ++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ ++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ ++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ ++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ ++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ ++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ ++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ ++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ ++ ++/* USB.INTCTRLA bit masks and bit positions */ ++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ ++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ ++ ++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ ++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ ++ ++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ ++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ ++ ++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ ++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ ++ ++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* USB.INTCTRLB bit masks and bit positions */ ++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ ++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ ++ ++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ ++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ ++ ++/* USB.INTFLAGSACLR bit masks and bit positions */ ++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ ++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ ++ ++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ ++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ ++ ++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ ++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ ++ ++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ ++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ ++ ++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ ++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ ++ ++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ ++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ ++ ++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ ++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ ++ ++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ ++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSASET bit masks and bit positions */ ++/* USB_SOFIF Predefined. */ ++/* USB_SOFIF Predefined. */ ++ ++/* USB_SUSPENDIF Predefined. */ ++/* USB_SUSPENDIF Predefined. */ ++ ++/* USB_RESUMEIF Predefined. */ ++/* USB_RESUMEIF Predefined. */ ++ ++/* USB_RSTIF Predefined. */ ++/* USB_RSTIF Predefined. */ ++ ++/* USB_CRCIF Predefined. */ ++/* USB_CRCIF Predefined. */ ++ ++/* USB_UNFIF Predefined. */ ++/* USB_UNFIF Predefined. */ ++ ++/* USB_OVFIF Predefined. */ ++/* USB_OVFIF Predefined. */ ++ ++/* USB_STALLIF Predefined. */ ++/* USB_STALLIF Predefined. */ ++ ++/* USB.INTFLAGSBCLR bit masks and bit positions */ ++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ ++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ ++ ++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ ++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSBSET bit masks and bit positions */ ++/* USB_TRNIF Predefined. */ ++/* USB_TRNIF Predefined. */ ++ ++/* USB_SETUPIF Predefined. */ ++/* USB_SETUPIF Predefined. */ ++ ++/* PORT - I/O Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_SPI_bm 0x20 /* SPI bit mask. */ ++#define PORT_SPI_bp 5 /* SPI bit position. */ ++ ++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ ++#define PORT_USART0_bp 4 /* USART0 bit position. */ ++ ++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ ++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ ++ ++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ ++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ ++ ++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ ++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ ++ ++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ ++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD Predefined. */ ++/* TC0_CMD Predefined. */ ++ ++/* TC0_LUPD Predefined. */ ++/* TC0_LUPD Predefined. */ ++ ++/* TC0_DIR Predefined. */ ++/* TC0_DIR Predefined. */ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV Predefined. */ ++/* TC0_CCDBV Predefined. */ ++ ++/* TC0_CCCBV Predefined. */ ++/* TC0_CCCBV Predefined. */ ++ ++/* TC0_CCBBV Predefined. */ ++/* TC0_CCBBV Predefined. */ ++ ++/* TC0_CCABV Predefined. */ ++/* TC0_CCABV Predefined. */ ++ ++/* TC0_PERBV Predefined. */ ++/* TC0_PERBV Predefined. */ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD Predefined. */ ++/* TC1_CMD Predefined. */ ++ ++/* TC1_LUPD Predefined. */ ++/* TC1_LUPD Predefined. */ ++ ++/* TC1_DIR Predefined. */ ++/* TC1_DIR Predefined. */ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV Predefined. */ ++/* TC1_CCBBV Predefined. */ ++ ++/* TC1_CCABV Predefined. */ ++/* TC1_CCABV Predefined. */ ++ ++/* TC1_PERBV Predefined. */ ++/* TC1_PERBV Predefined. */ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++/* TC2.CTRLA bit masks and bit positions */ ++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC2.CTRLB bit masks and bit positions */ ++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ ++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ ++ ++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ ++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ ++ ++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ ++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ ++ ++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ ++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ ++ ++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ ++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ ++ ++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ ++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ ++ ++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ ++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ ++ ++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ ++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ ++ ++/* TC2.CTRLC bit masks and bit positions */ ++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ ++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ ++ ++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ ++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ ++ ++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ ++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ ++ ++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ ++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ ++ ++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ ++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ ++ ++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ ++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ ++ ++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ ++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ ++ ++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ ++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ ++ ++/* TC2.CTRLE bit masks and bit positions */ ++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC2.INTCTRLA bit masks and bit positions */ ++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ ++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ ++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ ++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ ++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ ++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ ++ ++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ ++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ ++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ ++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ ++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ ++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ ++ ++/* TC2.INTCTRLB bit masks and bit positions */ ++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ ++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ ++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ ++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ ++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ ++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ ++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ ++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ ++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ ++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ ++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ ++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ ++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ ++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ ++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ ++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ ++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ ++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ ++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ ++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ ++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ ++ ++/* TC2.CTRLF bit masks and bit positions */ ++#define TC2_CMD_gm 0x0C /* Command group mask. */ ++#define TC2_CMD_gp 2 /* Command group position. */ ++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC2_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC2_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ ++#define TC2_CMDEN_gp 0 /* Command Enable group position. */ ++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ ++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ ++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ ++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ ++ ++/* TC2.INTFLAGS bit masks and bit positions */ ++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ ++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ ++ ++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ ++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ ++ ++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ ++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ ++ ++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ ++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ ++ ++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ ++ ++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ ++ ++/* AWEX - Timer/Counter Advanced Waveform Extension */ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++/* AWEX.STATUSSET bit masks and bit positions */ ++/* AWEX_FDF Predefined. */ ++/* AWEX_FDF Predefined. */ ++ ++/* AWEX_DTHSBUFV Predefined. */ ++/* AWEX_DTHSBUFV Predefined. */ ++ ++/* AWEX_DTLSBUFV Predefined. */ ++/* AWEX_DTLSBUFV Predefined. */ ++ ++/* HIRES - Timer/Counter High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ ++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* LOCKBIT - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LUNF_vect_num 14 ++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_HUNF_vect_num 15 ++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPA_vect_num 16 ++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPB_vect_num 17 ++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPC_vect_num 18 ++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPD_vect_num 19 ++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* USARTC1 interrupt vectors */ ++#define USARTC1_RXC_vect_num 28 ++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ ++#define USARTC1_DRE_vect_num 29 ++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ ++#define USARTC1_TXC_vect_num 30 ++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LUNF_vect_num 77 ++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_HUNF_vect_num 78 ++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPA_vect_num 79 ++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPB_vect_num 80 ++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPC_vect_num 81 ++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPD_vect_num 82 ++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* USB interrupt vectors */ ++#define USB_BUSEVENT_vect_num 125 ++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ ++#define USB_TRNCOMPL_vect_num 126 ++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (127 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (20480) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (16384) ++#define APP_SECTION_PAGE_SIZE (256) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x3000) ++#define APPTABLE_SECTION_SIZE (4096) ++#define APPTABLE_SECTION_PAGE_SIZE (256) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x4000) ++#define BOOT_SECTION_SIZE (4096) ++#define BOOT_SECTION_PAGE_SIZE (256) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (10240) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (1024) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (2048) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (1024) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (6) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (256) ++#define USER_SIGNATURES_PAGE_SIZE (256) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (64) ++#define PROD_SIGNATURES_PAGE_SIZE (256) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 256 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 Reserved */ ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x43 ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA16C4_H_INCLUDED */ ++ +diff --git a/include/avr/iox16d4.h b/include/avr/iox16d4.h +index 7518428..3ffd1d3 100644 +--- a/include/avr/iox16d4.h ++++ b/include/avr/iox16d4.h +@@ -1,5587 +1,5667 @@ +-/* Copyright (c) 2009-2010 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iox16d4.h 2200 2010-12-14 04:24:24Z arcanum $ */ +- +-/* avr/iox16d4.h - definitions for ATxmega16D4 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iox16d4.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATxmega16D4_H_ +-#define _AVR_ATxmega16D4_H_ 1 +- +- +-/* Ungrouped common registers */ +-#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +-#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +-#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +-#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +-#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +-#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +-#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +-#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +-#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +-#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +-#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +-#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +-#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +-#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +-#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +-#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +- +-/* Deprecated */ +-#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +-#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +-#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +-#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +-#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +-#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +-#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +-#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +-#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +-#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +-#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +-#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +-#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +-#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +-#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +-#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +- +-#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +-#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +-#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +-#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +-#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +-#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +-#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +-#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +-#define SREG _SFR_MEM8(0x003F) /* Status Register */ +- +- +-/* C Language Only */ +-#if !defined (__ASSEMBLER__) +- +-#include +- +-typedef volatile uint8_t register8_t; +-typedef volatile uint16_t register16_t; +-typedef volatile uint32_t register32_t; +- +- +-#ifdef _WORDREGISTER +-#undef _WORDREGISTER +-#endif +-#define _WORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register16_t regname; \ +- struct \ +- { \ +- register8_t regname ## L; \ +- register8_t regname ## H; \ +- }; \ +- } +- +-#ifdef _DWORDREGISTER +-#undef _DWORDREGISTER +-#endif +-#define _DWORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register32_t regname; \ +- struct \ +- { \ +- register8_t regname ## 0; \ +- register8_t regname ## 1; \ +- register8_t regname ## 2; \ +- register8_t regname ## 3; \ +- }; \ +- } +- +- +-/* +-========================================================================== +-IO Module Structures +-========================================================================== +-*/ +- +- +-/* +--------------------------------------------------------------------------- +-XOCD - On-Chip Debug System +--------------------------------------------------------------------------- +-*/ +- +-/* On-Chip Debug System */ +-typedef struct OCD_struct +-{ +- register8_t OCDR0; /* OCD Register 0 */ +- register8_t OCDR1; /* OCD Register 1 */ +-} OCD_t; +- +- +-/* CCP signatures */ +-typedef enum CCP_enum +-{ +- CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ +- CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +-} CCP_t; +- +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Clock System */ +-typedef struct CLK_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t PSCTRL; /* Prescaler Control Register */ +- register8_t LOCK; /* Lock register */ +- register8_t RTCCTRL; /* RTC Control Register */ +-} CLK_t; +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Power Reduction */ +-typedef struct PR_struct +-{ +- register8_t PRGEN; /* General Power Reduction */ +- register8_t PRPA; /* Power Reduction Port A */ +- register8_t PRPB; /* Power Reduction Port B */ +- register8_t PRPC; /* Power Reduction Port C */ +- register8_t PRPD; /* Power Reduction Port D */ +- register8_t PRPE; /* Power Reduction Port E */ +- register8_t PRPF; /* Power Reduction Port F */ +-} PR_t; +- +-/* System Clock Selection */ +-typedef enum CLK_SCLKSEL_enum +-{ +- CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ +- CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ +- CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ +- CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ +- CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +-} CLK_SCLKSEL_t; +- +-/* Prescaler A Division Factor */ +-typedef enum CLK_PSADIV_enum +-{ +- CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ +- CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ +- CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ +- CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ +- CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ +- CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ +- CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ +- CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ +- CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ +- CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +-} CLK_PSADIV_t; +- +-/* Prescaler B and C Division Factor */ +-typedef enum CLK_PSBCDIV_enum +-{ +- CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ +- CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ +- CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ +- CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +-} CLK_PSBCDIV_t; +- +-/* RTC Clock Source */ +-typedef enum CLK_RTCSRC_enum +-{ +- CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ +- CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ +- CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ +- CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +-} CLK_RTCSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-SLEEP - Sleep Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Sleep Controller */ +-typedef struct SLEEP_struct +-{ +- register8_t CTRL; /* Control Register */ +-} SLEEP_t; +- +-/* Sleep Mode */ +-typedef enum SLEEP_SMODE_enum +-{ +- SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ +- SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +- SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ +- SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ +- SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +-} SLEEP_SMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-OSC - Oscillator +--------------------------------------------------------------------------- +-*/ +- +-/* Oscillator */ +-typedef struct OSC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t XOSCCTRL; /* External Oscillator Control Register */ +- register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ +- register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ +- register8_t PLLCTRL; /* PLL Control REgister */ +- register8_t DFLLCTRL; /* DFLL Control Register */ +-} OSC_t; +- +-/* Oscillator Frequency Range */ +-typedef enum OSC_FRQRANGE_enum +-{ +- OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ +- OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ +- OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ +- OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +-} OSC_FRQRANGE_t; +- +-/* External Oscillator Selection and Startup Time */ +-typedef enum OSC_XOSCSEL_enum +-{ +- OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ +- OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ +- OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ +- OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ +- OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +-} OSC_XOSCSEL_t; +- +-/* PLL Clock Source */ +-typedef enum OSC_PLLSRC_enum +-{ +- OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ +- OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ +- OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +-} OSC_PLLSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-DFLL - DFLL +--------------------------------------------------------------------------- +-*/ +- +-/* DFLL */ +-typedef struct DFLL_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t CALA; /* Calibration Register A */ +- register8_t CALB; /* Calibration Register B */ +- register8_t COMP0; /* Oscillator Compare Register 0 */ +- register8_t COMP1; /* Oscillator Compare Register 1 */ +- register8_t COMP2; /* Oscillator Compare Register 2 */ +- register8_t reserved_0x07; +-} DFLL_t; +- +- +-/* +--------------------------------------------------------------------------- +-RST - Reset +--------------------------------------------------------------------------- +-*/ +- +-/* Reset */ +-typedef struct RST_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t CTRL; /* Control Register */ +-} RST_t; +- +- +-/* +--------------------------------------------------------------------------- +-WDT - Watch-Dog Timer +--------------------------------------------------------------------------- +-*/ +- +-/* Watch-Dog Timer */ +-typedef struct WDT_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t WINCTRL; /* Windowed Mode Control */ +- register8_t STATUS; /* Status */ +-} WDT_t; +- +-/* Period setting */ +-typedef enum WDT_PER_enum +-{ +- WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ +- WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ +- WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ +- WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_PER_t; +- +-/* Closed window period */ +-typedef enum WDT_WPER_enum +-{ +- WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ +- WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ +- WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ +- WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_WPER_t; +- +- +-/* +--------------------------------------------------------------------------- +-MCU - MCU Control +--------------------------------------------------------------------------- +-*/ +- +-/* MCU Control */ +-typedef struct MCU_struct +-{ +- register8_t DEVID0; /* Device ID byte 0 */ +- register8_t DEVID1; /* Device ID byte 1 */ +- register8_t DEVID2; /* Device ID byte 2 */ +- register8_t REVID; /* Revision ID */ +- register8_t JTAGUID; /* JTAG User ID */ +- register8_t reserved_0x05; +- register8_t MCUCR; /* MCU Control */ +- register8_t reserved_0x07; +- register8_t EVSYSLOCK; /* Event System Lock */ +- register8_t AWEXLOCK; /* AWEX Lock */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +-} MCU_t; +- +- +-/* +--------------------------------------------------------------------------- +-PMIC - Programmable Multi-level Interrupt Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Programmable Multi-level Interrupt Controller */ +-typedef struct PMIC_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t INTPRI; /* Interrupt Priority */ +- register8_t CTRL; /* Control Register */ +-} PMIC_t; +- +- +-/* +--------------------------------------------------------------------------- +-EVSYS - Event System +--------------------------------------------------------------------------- +-*/ +- +-/* Event System */ +-typedef struct EVSYS_struct +-{ +- register8_t CH0MUX; /* Event Channel 0 Multiplexer */ +- register8_t CH1MUX; /* Event Channel 1 Multiplexer */ +- register8_t CH2MUX; /* Event Channel 2 Multiplexer */ +- register8_t CH3MUX; /* Event Channel 3 Multiplexer */ +- register8_t reserved_0x04; +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t CH0CTRL; /* Channel 0 Control Register */ +- register8_t CH1CTRL; /* Channel 1 Control Register */ +- register8_t CH2CTRL; /* Channel 2 Control Register */ +- register8_t CH3CTRL; /* Channel 3 Control Register */ +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t STROBE; /* Event Strobe */ +- register8_t DATA; /* Event Data */ +-} EVSYS_t; +- +-/* Quadrature Decoder Index Recognition Mode */ +-typedef enum EVSYS_QDIRM_enum +-{ +- EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ +- EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ +- EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ +- EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +-} EVSYS_QDIRM_t; +- +-/* Digital filter coefficient */ +-typedef enum EVSYS_DIGFILT_enum +-{ +- EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ +- EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ +- EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ +- EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ +- EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ +- EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ +- EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ +- EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +-} EVSYS_DIGFILT_t; +- +-/* Event Channel multiplexer input selection */ +-typedef enum EVSYS_CHMUX_enum +-{ +- EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ +- EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ +- EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ +- EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ +- EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ +- EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ +- EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ +- EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ +- EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ +- EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ +- EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ +- EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ +- EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ +- EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ +- EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ +- EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ +- EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ +- EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ +- EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ +- EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ +- EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ +- EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ +- EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ +- EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ +- EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ +- EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ +- EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ +- EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ +- EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ +- EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ +- EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ +- EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ +- EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ +- EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ +- EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ +- EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ +- EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ +- EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ +- EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ +- EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ +- EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ +- EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ +- EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ +- EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ +- EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ +- EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ +- EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ +- EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ +- EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ +- EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ +- EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ +- EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ +- EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ +- EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ +- EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ +- EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ +- EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ +- EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ +- EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ +- EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ +- EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ +- EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ +- EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ +- EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ +- EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ +- EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ +- EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ +- EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ +- EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ +- EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ +- EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ +- EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ +- EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ +- EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ +- EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ +- EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ +- EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ +- EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ +- EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ +- EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ +- EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ +- EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ +- EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ +- EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ +- EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ +- EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ +- EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ +- EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ +- EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ +- EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ +- EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ +- EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ +- EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ +- EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ +- EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ +- EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ +- EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ +- EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ +- EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ +- EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ +- EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +- EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ +- EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ +- EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ +- EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +-} EVSYS_CHMUX_t; +- +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Non-volatile Memory Controller */ +-typedef struct NVM_struct +-{ +- register8_t ADDR0; /* Address Register 0 */ +- register8_t ADDR1; /* Address Register 1 */ +- register8_t ADDR2; /* Address Register 2 */ +- register8_t reserved_0x03; +- register8_t DATA0; /* Data Register 0 */ +- register8_t DATA1; /* Data Register 1 */ +- register8_t DATA2; /* Data Register 2 */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t CMD; /* Command */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t INTCTRL; /* Interrupt Control */ +- register8_t reserved_0x0E; +- register8_t STATUS; /* Status */ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Lock Bits */ +-typedef struct NVM_LOCKBITS_struct +-{ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_LOCKBITS_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Fuses */ +-typedef struct NVM_FUSES_struct +-{ +- register8_t FUSEBYTE0; /* User ID */ +- register8_t FUSEBYTE1; /* Watchdog Configuration */ +- register8_t FUSEBYTE2; /* Reset Configuration */ +- register8_t reserved_0x03; +- register8_t FUSEBYTE4; /* Start-up Configuration */ +- register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +-} NVM_FUSES_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Production Signatures */ +-typedef struct NVM_PROD_SIGNATURES_struct +-{ +- register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ +- register8_t reserved_0x01; +- register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ +- register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ +- register8_t reserved_0x04; +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ +- register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ +- register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ +- register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ +- register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ +- register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t WAFNUM; /* Wafer Number */ +- register8_t reserved_0x11; +- register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ +- register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ +- register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ +- register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ +- register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ +- register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ +- register8_t reserved_0x26; +- register8_t reserved_0x27; +- register8_t reserved_0x28; +- register8_t reserved_0x29; +- register8_t reserved_0x2A; +- register8_t reserved_0x2B; +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ +- register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ +- register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ +- register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ +- register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ +- register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- register8_t reserved_0x36; +- register8_t reserved_0x37; +- register8_t reserved_0x38; +- register8_t reserved_0x39; +- register8_t reserved_0x3A; +- register8_t reserved_0x3B; +- register8_t reserved_0x3C; +- register8_t reserved_0x3D; +- register8_t reserved_0x3E; +-} NVM_PROD_SIGNATURES_t; +- +-/* NVM Command */ +-typedef enum NVM_CMD_enum +-{ +- NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ +- NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ +- NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ +- NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ +- NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ +- NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ +- NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ +- NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ +- NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ +- NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ +- NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ +- NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ +- NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ +- NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ +- NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ +- NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ +- NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ +- NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ +- NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ +- NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ +- NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ +- NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ +- NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ +- NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ +- NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ +- NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +-} NVM_CMD_t; +- +-/* SPM ready interrupt level */ +-typedef enum NVM_SPMLVL_enum +-{ +- NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ +- NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ +- NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +-} NVM_SPMLVL_t; +- +-/* EEPROM ready interrupt level */ +-typedef enum NVM_EELVL_enum +-{ +- NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ +- NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ +- NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +-} NVM_EELVL_t; +- +-/* Boot lock bits - boot setcion */ +-typedef enum NVM_BLBB_enum +-{ +- NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +- NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ +- NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ +- NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +-} NVM_BLBB_t; +- +-/* Boot lock bits - application section */ +-typedef enum NVM_BLBA_enum +-{ +- NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +- NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ +- NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ +- NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +-} NVM_BLBA_t; +- +-/* Boot lock bits - application table section */ +-typedef enum NVM_BLBAT_enum +-{ +- NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +- NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ +- NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ +- NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +-} NVM_BLBAT_t; +- +-/* Lock bits */ +-typedef enum NVM_LB_enum +-{ +- NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +- NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ +- NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +-} NVM_LB_t; +- +-/* Boot Loader Section Reset Vector */ +-typedef enum BOOTRST_enum +-{ +- BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ +- BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +-} BOOTRST_t; +- +-/* BOD operation */ +-typedef enum BOD_enum +-{ +- BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ +- BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ +- BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +-} BOD_t; +- +-/* Watchdog (Window) Timeout Period */ +-typedef enum WD_enum +-{ +- WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ +- WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ +- WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ +- WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ +- WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ +- WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ +- WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ +- WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ +- WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ +- WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ +- WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +-} WD_t; +- +-/* Start-up Time */ +-typedef enum SUT_enum +-{ +- SUT_0MS_gc = (0x03<<2), /* 0 ms */ +- SUT_4MS_gc = (0x01<<2), /* 4 ms */ +- SUT_64MS_gc = (0x00<<2), /* 64 ms */ +-} SUT_t; +- +-/* Brown Out Detection Voltage Level */ +-typedef enum BODLVL_enum +-{ +- BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ +- BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ +- BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ +- BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ +- BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ +- BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ +- BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ +-} BODLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-AC - Analog Comparator +--------------------------------------------------------------------------- +-*/ +- +-/* Analog Comparator */ +-typedef struct AC_struct +-{ +- register8_t AC0CTRL; /* Comparator 0 Control */ +- register8_t AC1CTRL; /* Comparator 1 Control */ +- register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ +- register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t WINCTRL; /* Window Mode Control */ +- register8_t STATUS; /* Status */ +-} AC_t; +- +-/* Interrupt mode */ +-typedef enum AC_INTMODE_enum +-{ +- AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ +- AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ +- AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +-} AC_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum AC_INTLVL_enum +-{ +- AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ +- AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ +- AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ +- AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +-} AC_INTLVL_t; +- +-/* Hysteresis mode selection */ +-typedef enum AC_HYSMODE_enum +-{ +- AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ +- AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ +- AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +-} AC_HYSMODE_t; +- +-/* Positive input multiplexer selection */ +-typedef enum AC_MUXPOS_enum +-{ +- AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ +- AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ +- AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ +- AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ +- AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ +- AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ +- AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +- AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +-} AC_MUXPOS_t; +- +-/* Negative input multiplexer selection */ +-typedef enum AC_MUXNEG_enum +-{ +- AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ +- AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ +- AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ +- AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ +- AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ +- AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ +- AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ +- AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +-} AC_MUXNEG_t; +- +-/* Windows interrupt mode */ +-typedef enum AC_WINTMODE_enum +-{ +- AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ +- AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ +- AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ +- AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +-} AC_WINTMODE_t; +- +-/* Window interrupt level */ +-typedef enum AC_WINTLVL_enum +-{ +- AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ +- AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ +- AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +-} AC_WINTLVL_t; +- +-/* Window mode state */ +-typedef enum AC_WSTATE_enum +-{ +- AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ +- AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ +- AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +-} AC_WSTATE_t; +- +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* ADC Channel */ +-typedef struct ADC_CH_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t MUXCTRL; /* MUX Control */ +- register8_t INTCTRL; /* Channel Interrupt Control */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- _WORDREGISTER(RES); /* Channel Result */ +- register8_t reserved_0x6; +- register8_t reserved_0x7; +-} ADC_CH_t; +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Analog-to-Digital Converter */ +-typedef struct ADC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t REFCTRL; /* Reference Control */ +- register8_t EVCTRL; /* Event Control */ +- register8_t PRESCALER; /* Clock Prescaler */ +- register8_t reserved_0x05; +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- _WORDREGISTER(CAL); /* Calibration Value */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- _WORDREGISTER(CH0RES); /* Channel 0 Result */ +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- _WORDREGISTER(CMP); /* Compare Value */ +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- ADC_CH_t CH0; /* ADC Channel 0 */ +-} ADC_t; +- +-/* Positive input multiplexer selection */ +-typedef enum ADC_CH_MUXPOS_enum +-{ +- ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ +- ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ +- ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ +- ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ +- ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ +- ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ +- ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ +- ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +-} ADC_CH_MUXPOS_t; +- +-/* Internal input multiplexer selections */ +-typedef enum ADC_CH_MUXINT_enum +-{ +- ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ +- ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ +- ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +- ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +-} ADC_CH_MUXINT_t; +- +-/* Negative input multiplexer selection */ +-typedef enum ADC_CH_MUXNEG_enum +-{ +- ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ +- ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ +- ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ +- ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ +- ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ +- ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ +- ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ +- ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +-} ADC_CH_MUXNEG_t; +- +-/* Input mode */ +-typedef enum ADC_CH_INPUTMODE_enum +-{ +- ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ +- ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ +- ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ +- ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +-} ADC_CH_INPUTMODE_t; +- +-/* Gain factor */ +-typedef enum ADC_CH_GAIN_enum +-{ +- ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ +- ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ +- ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ +- ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ +- ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ +- ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ +- ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ +-} ADC_CH_GAIN_t; +- +-/* Conversion result resolution */ +-typedef enum ADC_RESOLUTION_enum +-{ +- ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ +- ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ +- ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +-} ADC_RESOLUTION_t; +- +-/* Voltage reference selection */ +-typedef enum ADC_REFSEL_enum +-{ +- ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ +- ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ +- ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ +- ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +-} ADC_REFSEL_t; +- +-/* Channel sweep selection */ +-typedef enum ADC_SWEEP_enum +-{ +- ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ +-} ADC_SWEEP_t; +- +-/* Event channel input selection */ +-typedef enum ADC_EVSEL_enum +-{ +- ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ +- ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ +- ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ +- ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ +- ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ +- ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ +- ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ +- ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +-} ADC_EVSEL_t; +- +-/* Event action selection */ +-typedef enum ADC_EVACT_enum +-{ +- ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ +- ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ +-} ADC_EVACT_t; +- +-/* Interupt mode */ +-typedef enum ADC_CH_INTMODE_enum +-{ +- ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ +- ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ +- ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +-} ADC_CH_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum ADC_CH_INTLVL_enum +-{ +- ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ +- ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ +- ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +-} ADC_CH_INTLVL_t; +- +-/* Clock prescaler */ +-typedef enum ADC_PRESCALER_enum +-{ +- ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ +- ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ +- ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ +- ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ +- ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ +- ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ +- ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ +- ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +-} ADC_PRESCALER_t; +- +- +-/* +--------------------------------------------------------------------------- +-RTC - Real-Time Clounter +--------------------------------------------------------------------------- +-*/ +- +-/* Real-Time Counter */ +-typedef struct RTC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t TEMP; /* Temporary register */ +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- _WORDREGISTER(CNT); /* Count Register */ +- _WORDREGISTER(PER); /* Period Register */ +- _WORDREGISTER(COMP); /* Compare Register */ +-} RTC_t; +- +-/* Prescaler Factor */ +-typedef enum RTC_PRESCALER_enum +-{ +- RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ +- RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ +- RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ +- RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ +- RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ +- RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ +- RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ +- RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +-} RTC_PRESCALER_t; +- +-/* Compare Interrupt level */ +-typedef enum RTC_COMPINTLVL_enum +-{ +- RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} RTC_COMPINTLVL_t; +- +-/* Overflow Interrupt level */ +-typedef enum RTC_OVFINTLVL_enum +-{ +- RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} RTC_OVFINTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* EBI Chip Select Module */ +-typedef struct EBI_CS_struct +-{ +- register8_t CTRLA; /* Chip Select Control Register A */ +- register8_t CTRLB; /* Chip Select Control Register B */ +- _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +-} EBI_CS_t; +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* External Bus Interface */ +-typedef struct EBI_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t SDRAMCTRLA; /* SDRAM Control Register A */ +- register8_t reserved_0x02; +- register8_t reserved_0x03; +- _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ +- _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ +- register8_t SDRAMCTRLB; /* SDRAM Control Register B */ +- register8_t SDRAMCTRLC; /* SDRAM Control Register C */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- EBI_CS_t CS0; /* Chip Select 0 */ +- EBI_CS_t CS1; /* Chip Select 1 */ +- EBI_CS_t CS2; /* Chip Select 2 */ +- EBI_CS_t CS3; /* Chip Select 3 */ +-} EBI_t; +- +-/* Chip Select adress space */ +-typedef enum EBI_CS_ASIZE_enum +-{ +- EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ +- EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ +- EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ +- EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ +- EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ +- EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ +- EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ +- EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ +- EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ +- EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ +- EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ +- EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ +- EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ +- EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ +- EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ +- EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ +- EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +-} EBI_CS_ASIZE_t; +- +-/* */ +-typedef enum EBI_CS_SRWS_enum +-{ +- EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_CS_SRWS_t; +- +-/* Chip Select address mode */ +-typedef enum EBI_CS_MODE_enum +-{ +- EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ +- EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ +- EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ +- EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +-} EBI_CS_MODE_t; +- +-/* Chip Select SDRAM mode */ +-typedef enum EBI_CS_SDMODE_enum +-{ +- EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ +- EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +-} EBI_CS_SDMODE_t; +- +-/* */ +-typedef enum EBI_SDDATAW_enum +-{ +- EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ +- EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +-} EBI_SDDATAW_t; +- +-/* */ +-typedef enum EBI_LPCMODE_enum +-{ +- EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ +- EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +-} EBI_LPCMODE_t; +- +-/* */ +-typedef enum EBI_SRMODE_enum +-{ +- EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ +- EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ +- EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ +- EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +-} EBI_SRMODE_t; +- +-/* */ +-typedef enum EBI_IFMODE_enum +-{ +- EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ +- EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ +- EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ +- EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +-} EBI_IFMODE_t; +- +-/* */ +-typedef enum EBI_SDCOL_enum +-{ +- EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ +- EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ +- EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ +- EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +-} EBI_SDCOL_t; +- +-/* */ +-typedef enum EBI_MRDLY_enum +-{ +- EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_MRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCYCDLY_enum +-{ +- EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ROWCYCDLY_t; +- +-/* */ +-typedef enum EBI_RPDLY_enum +-{ +- EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_RPDLY_t; +- +-/* */ +-typedef enum EBI_WRDLY_enum +-{ +- EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_WRDLY_t; +- +-/* */ +-typedef enum EBI_ESRDLY_enum +-{ +- EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ESRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCOLDLY_enum +-{ +- EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_ROWCOLDLY_t; +- +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_MASTER_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t STATUS; /* Status Register */ +- register8_t BAUD; /* Baurd Rate Control Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +-} TWI_MASTER_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_SLAVE_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t STATUS; /* Status Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +- register8_t ADDRMASK; /* Address Mask Register */ +-} TWI_SLAVE_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Two-Wire Interface */ +-typedef struct TWI_struct +-{ +- register8_t CTRL; /* TWI Common Control Register */ +- TWI_MASTER_t MASTER; /* TWI master module */ +- TWI_SLAVE_t SLAVE; /* TWI slave module */ +-} TWI_t; +- +-/* Master Interrupt Level */ +-typedef enum TWI_MASTER_INTLVL_enum +-{ +- TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_MASTER_INTLVL_t; +- +-/* Inactive Timeout */ +-typedef enum TWI_MASTER_TIMEOUT_enum +-{ +- TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ +- TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ +- TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ +- TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +-} TWI_MASTER_TIMEOUT_t; +- +-/* Master Command */ +-typedef enum TWI_MASTER_CMD_enum +-{ +- TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ +- TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ +- TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +-} TWI_MASTER_CMD_t; +- +-/* Master Bus State */ +-typedef enum TWI_MASTER_BUSSTATE_enum +-{ +- TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ +- TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ +- TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ +- TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +-} TWI_MASTER_BUSSTATE_t; +- +-/* Slave Interrupt Level */ +-typedef enum TWI_SLAVE_INTLVL_enum +-{ +- TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_SLAVE_INTLVL_t; +- +-/* Slave Command */ +-typedef enum TWI_SLAVE_CMD_enum +-{ +- TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ +- TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +-} TWI_SLAVE_CMD_t; +- +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O port Configuration */ +-typedef struct PORTCFG_struct +-{ +- register8_t MPCMASK; /* Multi-pin Configuration Mask */ +- register8_t reserved_0x01; +- register8_t VPCTRLA; /* Virtual Port Control Register A */ +- register8_t VPCTRLB; /* Virtual Port Control Register B */ +- register8_t CLKEVOUT; /* Clock and Event Out Register */ +-} PORTCFG_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* Virtual Port */ +-typedef struct VPORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t OUT; /* I/O Port Output */ +- register8_t IN; /* I/O Port Input */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +-} VPORT_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O Ports */ +-typedef struct PORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t DIRSET; /* I/O Port Data Direction Set */ +- register8_t DIRCLR; /* I/O Port Data Direction Clear */ +- register8_t DIRTGL; /* I/O Port Data Direction Toggle */ +- register8_t OUT; /* I/O Port Output */ +- register8_t OUTSET; /* I/O Port Output Set */ +- register8_t OUTCLR; /* I/O Port Output Clear */ +- register8_t OUTTGL; /* I/O Port Output Toggle */ +- register8_t IN; /* I/O port Input */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INT0MASK; /* Port Interrupt 0 Mask */ +- register8_t INT1MASK; /* Port Interrupt 1 Mask */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t PIN0CTRL; /* Pin 0 Control Register */ +- register8_t PIN1CTRL; /* Pin 1 Control Register */ +- register8_t PIN2CTRL; /* Pin 2 Control Register */ +- register8_t PIN3CTRL; /* Pin 3 Control Register */ +- register8_t PIN4CTRL; /* Pin 4 Control Register */ +- register8_t PIN5CTRL; /* Pin 5 Control Register */ +- register8_t PIN6CTRL; /* Pin 6 Control Register */ +- register8_t PIN7CTRL; /* Pin 7 Control Register */ +-} PORT_t; +- +-/* Virtual Port 0 Mapping */ +-typedef enum PORTCFG_VP0MAP_enum +-{ +- PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP0MAP_t; +- +-/* Virtual Port 1 Mapping */ +-typedef enum PORTCFG_VP1MAP_enum +-{ +- PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP1MAP_t; +- +-/* Virtual Port 2 Mapping */ +-typedef enum PORTCFG_VP2MAP_enum +-{ +- PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP2MAP_t; +- +-/* Virtual Port 3 Mapping */ +-typedef enum PORTCFG_VP3MAP_enum +-{ +- PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP3MAP_t; +- +-/* Clock Output Port */ +-typedef enum PORTCFG_CLKOUT_enum +-{ +- PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ +- PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ +- PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ +- PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +-} PORTCFG_CLKOUT_t; +- +-/* Event Output Port */ +-typedef enum PORTCFG_EVOUT_enum +-{ +- PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ +- PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ +- PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ +- PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +-} PORTCFG_EVOUT_t; +- +-/* Port Interrupt 0 Level */ +-typedef enum PORT_INT0LVL_enum +-{ +- PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ +- PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ +- PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +-} PORT_INT0LVL_t; +- +-/* Port Interrupt 1 Level */ +-typedef enum PORT_INT1LVL_enum +-{ +- PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ +- PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ +- PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +-} PORT_INT1LVL_t; +- +-/* Output/Pull Configuration */ +-typedef enum PORT_OPC_enum +-{ +- PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ +- PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ +- PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ +- PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ +- PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ +- PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ +- PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ +- PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +-} PORT_OPC_t; +- +-/* Input/Sense Configuration */ +-typedef enum PORT_ISC_enum +-{ +- PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ +- PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ +- PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ +- PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ +- PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +-} PORT_ISC_t; +- +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 0 */ +-typedef struct TC0_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- _WORDREGISTER(CCC); /* Compare or Capture C */ +- _WORDREGISTER(CCD); /* Compare or Capture D */ +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +- _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ +- _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +-} TC0_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 1 */ +-typedef struct TC1_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t reserved_0x2E; +- register8_t reserved_0x2F; +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +-} TC1_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* Advanced Waveform Extension */ +-typedef struct AWEX_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t FDEMASK; /* Fault Detection Event Mask */ +- register8_t FDCTRL; /* Fault Detection Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x05; +- register8_t DTBOTH; /* Dead Time Both Sides */ +- register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ +- register8_t DTLS; /* Dead Time Low Side */ +- register8_t DTHS; /* Dead Time High Side */ +- register8_t DTLSBUF; /* Dead Time Low Side Buffer */ +- register8_t DTHSBUF; /* Dead Time High Side Buffer */ +- register8_t OUTOVEN; /* Output Override Enable */ +-} AWEX_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* High-Resolution Extension */ +-typedef struct HIRES_struct +-{ +- register8_t CTRLA; /* Control Register */ +-} HIRES_t; +- +-/* Clock Selection */ +-typedef enum TC_CLKSEL_enum +-{ +- TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ +- TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ +- TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ +- TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ +- TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ +- TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ +- TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ +- TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ +- TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_CLKSEL_t; +- +-/* Waveform Generation Mode */ +-typedef enum TC_WGMODE_enum +-{ +- TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ +- TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ +- TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ +- TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ +- TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ +- TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +-} TC_WGMODE_t; +- +-/* Event Action */ +-typedef enum TC_EVACT_enum +-{ +- TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ +- TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ +- TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ +- TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ +- TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ +- TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */ +- TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +-} TC_EVACT_t; +- +-/* Event Selection */ +-typedef enum TC_EVSEL_enum +-{ +- TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_EVSEL_t; +- +-/* Error Interrupt Level */ +-typedef enum TC_ERRINTLVL_enum +-{ +- TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_ERRINTLVL_t; +- +-/* Overflow Interrupt Level */ +-typedef enum TC_OVFINTLVL_enum +-{ +- TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_OVFINTLVL_t; +- +-/* Compare or Capture D Interrupt Level */ +-typedef enum TC_CCDINTLVL_enum +-{ +- TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TC_CCDINTLVL_t; +- +-/* Compare or Capture C Interrupt Level */ +-typedef enum TC_CCCINTLVL_enum +-{ +- TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} TC_CCCINTLVL_t; +- +-/* Compare or Capture B Interrupt Level */ +-typedef enum TC_CCBINTLVL_enum +-{ +- TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_CCBINTLVL_t; +- +-/* Compare or Capture A Interrupt Level */ +-typedef enum TC_CCAINTLVL_enum +-{ +- TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_CCAINTLVL_t; +- +-/* Timer/Counter Command */ +-typedef enum TC_CMD_enum +-{ +- TC_CMD_NONE_gc = (0x00<<2), /* No Command */ +- TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ +- TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ +- TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +-} TC_CMD_t; +- +-/* Fault Detect Action */ +-typedef enum AWEX_FDACT_enum +-{ +- AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ +- AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ +- AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +-} AWEX_FDACT_t; +- +-/* High Resolution Enable */ +-typedef enum HIRES_HREN_enum +-{ +- HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ +- HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ +- HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ +- HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +-} HIRES_HREN_t; +- +- +-/* +--------------------------------------------------------------------------- +-USART - Universal Asynchronous Receiver-Transmitter +--------------------------------------------------------------------------- +-*/ +- +-/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +-typedef struct USART_struct +-{ +- register8_t DATA; /* Data Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x02; +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t BAUDCTRLA; /* Baud Rate Control Register A */ +- register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +-} USART_t; +- +-/* Receive Complete Interrupt level */ +-typedef enum USART_RXCINTLVL_enum +-{ +- USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} USART_RXCINTLVL_t; +- +-/* Transmit Complete Interrupt level */ +-typedef enum USART_TXCINTLVL_enum +-{ +- USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} USART_TXCINTLVL_t; +- +-/* Data Register Empty Interrupt level */ +-typedef enum USART_DREINTLVL_enum +-{ +- USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} USART_DREINTLVL_t; +- +-/* Character Size */ +-typedef enum USART_CHSIZE_enum +-{ +- USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ +- USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ +- USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ +- USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ +- USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +-} USART_CHSIZE_t; +- +-/* Communication Mode */ +-typedef enum USART_CMODE_enum +-{ +- USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ +- USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ +- USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ +- USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +-} USART_CMODE_t; +- +-/* Parity Mode */ +-typedef enum USART_PMODE_enum +-{ +- USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ +- USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ +- USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +-} USART_PMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-SPI - Serial Peripheral Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Serial Peripheral Interface */ +-typedef struct SPI_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t DATA; /* Data Register */ +-} SPI_t; +- +-/* SPI Mode */ +-typedef enum SPI_MODE_enum +-{ +- SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ +- SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ +- SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ +- SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +-} SPI_MODE_t; +- +-/* Prescaler setting */ +-typedef enum SPI_PRESCALER_enum +-{ +- SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ +- SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ +- SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ +- SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +-} SPI_PRESCALER_t; +- +-/* Interrupt level */ +-typedef enum SPI_INTLVL_enum +-{ +- SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} SPI_INTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-IRCOM - IR Communication Module +--------------------------------------------------------------------------- +-*/ +- +-/* IR Communication Module */ +-typedef struct IRCOM_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ +- register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +-} IRCOM_t; +- +-/* Event channel selection */ +-typedef enum IRDA_EVSEL_enum +-{ +- IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ +- IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ +- IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ +- IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +- IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ +- IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ +- IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ +- IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +-} IRDA_EVSEL_t; +- +- +- +-/* +-========================================================================== +-IO Module Instances. Mapped to memory. +-========================================================================== +-*/ +- +-#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +-#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +-#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +-#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +-#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +-#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +-#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +-#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +-#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +-#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +-#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +-#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +-#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +-#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +-#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +-#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +-#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +-#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +-#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +-#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +-#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +-#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +-#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +-#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +-#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +-#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +-#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +-#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +-#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +-#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +-#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +-#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +-#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +-#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +-#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +-#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +-#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +-#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +-#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +- +- +-#endif /* !defined (__ASSEMBLER__) */ +- +- +-/* ========== Flattened fully qualified IO register names ========== */ +- +-/* GPIO - General Purpose IO Registers */ +-#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +-#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +-#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +-#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +-#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +-#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +-#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +-#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +-#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +-#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +-#define GPIO_GPIORA _SFR_MEM8(0x000A) +-#define GPIO_GPIORB _SFR_MEM8(0x000B) +-#define GPIO_GPIORC _SFR_MEM8(0x000C) +-#define GPIO_GPIORD _SFR_MEM8(0x000D) +-#define GPIO_GPIORE _SFR_MEM8(0x000E) +-#define GPIO_GPIORF _SFR_MEM8(0x000F) +- +-/* Deprecated */ +-#define GPIO_GPIO0 _SFR_MEM8(0x0000) +-#define GPIO_GPIO1 _SFR_MEM8(0x0001) +-#define GPIO_GPIO2 _SFR_MEM8(0x0002) +-#define GPIO_GPIO3 _SFR_MEM8(0x0003) +-#define GPIO_GPIO4 _SFR_MEM8(0x0004) +-#define GPIO_GPIO5 _SFR_MEM8(0x0005) +-#define GPIO_GPIO6 _SFR_MEM8(0x0006) +-#define GPIO_GPIO7 _SFR_MEM8(0x0007) +-#define GPIO_GPIO8 _SFR_MEM8(0x0008) +-#define GPIO_GPIO9 _SFR_MEM8(0x0009) +-#define GPIO_GPIOA _SFR_MEM8(0x000A) +-#define GPIO_GPIOB _SFR_MEM8(0x000B) +-#define GPIO_GPIOC _SFR_MEM8(0x000C) +-#define GPIO_GPIOD _SFR_MEM8(0x000D) +-#define GPIO_GPIOE _SFR_MEM8(0x000E) +-#define GPIO_GPIOF _SFR_MEM8(0x000F) +- +-/* VPORT0 - Virtual Port 0 */ +-#define VPORT0_DIR _SFR_MEM8(0x0010) +-#define VPORT0_OUT _SFR_MEM8(0x0011) +-#define VPORT0_IN _SFR_MEM8(0x0012) +-#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) +- +-/* VPORT1 - Virtual Port 1 */ +-#define VPORT1_DIR _SFR_MEM8(0x0014) +-#define VPORT1_OUT _SFR_MEM8(0x0015) +-#define VPORT1_IN _SFR_MEM8(0x0016) +-#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) +- +-/* VPORT2 - Virtual Port 2 */ +-#define VPORT2_DIR _SFR_MEM8(0x0018) +-#define VPORT2_OUT _SFR_MEM8(0x0019) +-#define VPORT2_IN _SFR_MEM8(0x001A) +-#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) +- +-/* VPORT3 - Virtual Port 3 */ +-#define VPORT3_DIR _SFR_MEM8(0x001C) +-#define VPORT3_OUT _SFR_MEM8(0x001D) +-#define VPORT3_IN _SFR_MEM8(0x001E) +-#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) +- +-/* OCD - On-Chip Debug System */ +-#define OCD_OCDR0 _SFR_MEM8(0x002E) +-#define OCD_OCDR1 _SFR_MEM8(0x002F) +- +-/* CPU - CPU Registers */ +-#define CPU_CCP _SFR_MEM8(0x0034) +-#define CPU_RAMPD _SFR_MEM8(0x0038) +-#define CPU_RAMPX _SFR_MEM8(0x0039) +-#define CPU_RAMPY _SFR_MEM8(0x003A) +-#define CPU_RAMPZ _SFR_MEM8(0x003B) +-#define CPU_EIND _SFR_MEM8(0x003C) +-#define CPU_SPL _SFR_MEM8(0x003D) +-#define CPU_SPH _SFR_MEM8(0x003E) +-#define CPU_SREG _SFR_MEM8(0x003F) +- +-/* CLK - Clock System */ +-#define CLK_CTRL _SFR_MEM8(0x0040) +-#define CLK_PSCTRL _SFR_MEM8(0x0041) +-#define CLK_LOCK _SFR_MEM8(0x0042) +-#define CLK_RTCCTRL _SFR_MEM8(0x0043) +- +-/* SLEEP - Sleep Controller */ +-#define SLEEP_CTRL _SFR_MEM8(0x0048) +- +-/* OSC - Oscillator Control */ +-#define OSC_CTRL _SFR_MEM8(0x0050) +-#define OSC_STATUS _SFR_MEM8(0x0051) +-#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +-#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +-#define OSC_RC32KCAL _SFR_MEM8(0x0054) +-#define OSC_PLLCTRL _SFR_MEM8(0x0055) +-#define OSC_DFLLCTRL _SFR_MEM8(0x0056) +- +-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +-#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +-#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +-#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +-#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +-#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +-#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) +- +-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +-#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +-#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +-#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +-#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +-#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +-#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) +- +-/* PR - Power Reduction */ +-#define PR_PRGEN _SFR_MEM8(0x0070) +-#define PR_PRPA _SFR_MEM8(0x0071) +-#define PR_PRPB _SFR_MEM8(0x0072) +-#define PR_PRPC _SFR_MEM8(0x0073) +-#define PR_PRPD _SFR_MEM8(0x0074) +-#define PR_PRPE _SFR_MEM8(0x0075) +-#define PR_PRPF _SFR_MEM8(0x0076) +- +-/* RST - Reset Controller */ +-#define RST_STATUS _SFR_MEM8(0x0078) +-#define RST_CTRL _SFR_MEM8(0x0079) +- +-/* WDT - Watch-Dog Timer */ +-#define WDT_CTRL _SFR_MEM8(0x0080) +-#define WDT_WINCTRL _SFR_MEM8(0x0081) +-#define WDT_STATUS _SFR_MEM8(0x0082) +- +-/* MCU - MCU Control */ +-#define MCU_DEVID0 _SFR_MEM8(0x0090) +-#define MCU_DEVID1 _SFR_MEM8(0x0091) +-#define MCU_DEVID2 _SFR_MEM8(0x0092) +-#define MCU_REVID _SFR_MEM8(0x0093) +-#define MCU_JTAGUID _SFR_MEM8(0x0094) +-#define MCU_MCUCR _SFR_MEM8(0x0096) +-#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +-#define MCU_AWEXLOCK _SFR_MEM8(0x0099) +- +-/* PMIC - Programmable Interrupt Controller */ +-#define PMIC_STATUS _SFR_MEM8(0x00A0) +-#define PMIC_INTPRI _SFR_MEM8(0x00A1) +-#define PMIC_CTRL _SFR_MEM8(0x00A2) +- +-/* PORTCFG - Port Configuration */ +-#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +-#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +-#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +-#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +- +-/* EVSYS - Event System */ +-#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +-#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +-#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +-#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +-#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +-#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +-#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +-#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +-#define EVSYS_STROBE _SFR_MEM8(0x0190) +-#define EVSYS_DATA _SFR_MEM8(0x0191) +- +-/* NVM - Non Volatile Memory Controller */ +-#define NVM_ADDR0 _SFR_MEM8(0x01C0) +-#define NVM_ADDR1 _SFR_MEM8(0x01C1) +-#define NVM_ADDR2 _SFR_MEM8(0x01C2) +-#define NVM_DATA0 _SFR_MEM8(0x01C4) +-#define NVM_DATA1 _SFR_MEM8(0x01C5) +-#define NVM_DATA2 _SFR_MEM8(0x01C6) +-#define NVM_CMD _SFR_MEM8(0x01CA) +-#define NVM_CTRLA _SFR_MEM8(0x01CB) +-#define NVM_CTRLB _SFR_MEM8(0x01CC) +-#define NVM_INTCTRL _SFR_MEM8(0x01CD) +-#define NVM_STATUS _SFR_MEM8(0x01CF) +-#define NVM_LOCKBITS _SFR_MEM8(0x01D0) +- +-/* ADCA - Analog to Digital Converter A */ +-#define ADCA_CTRLA _SFR_MEM8(0x0200) +-#define ADCA_CTRLB _SFR_MEM8(0x0201) +-#define ADCA_REFCTRL _SFR_MEM8(0x0202) +-#define ADCA_EVCTRL _SFR_MEM8(0x0203) +-#define ADCA_PRESCALER _SFR_MEM8(0x0204) +-#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +-#define ADCA_CAL _SFR_MEM16(0x020C) +-#define ADCA_CH0RES _SFR_MEM16(0x0210) +-#define ADCA_CMP _SFR_MEM16(0x0218) +-#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +-#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +-#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +-#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +-#define ADCA_CH0_RES _SFR_MEM16(0x0224) +- +-/* ACA - Analog Comparator A */ +-#define ACA_AC0CTRL _SFR_MEM8(0x0380) +-#define ACA_AC1CTRL _SFR_MEM8(0x0381) +-#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +-#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +-#define ACA_CTRLA _SFR_MEM8(0x0384) +-#define ACA_CTRLB _SFR_MEM8(0x0385) +-#define ACA_WINCTRL _SFR_MEM8(0x0386) +-#define ACA_STATUS _SFR_MEM8(0x0387) +- +-/* RTC - Real-Time Counter */ +-#define RTC_CTRL _SFR_MEM8(0x0400) +-#define RTC_STATUS _SFR_MEM8(0x0401) +-#define RTC_INTCTRL _SFR_MEM8(0x0402) +-#define RTC_INTFLAGS _SFR_MEM8(0x0403) +-#define RTC_TEMP _SFR_MEM8(0x0404) +-#define RTC_CNT _SFR_MEM16(0x0408) +-#define RTC_PER _SFR_MEM16(0x040A) +-#define RTC_COMP _SFR_MEM16(0x040C) +- +-/* TWIC - Two-Wire Interface C */ +-#define TWIC_CTRL _SFR_MEM8(0x0480) +-#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +-#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +-#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +-#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +-#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +-#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +-#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +-#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +-#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +-#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +-#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +-#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +-#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) +- +-/* PORTA - Port A */ +-#define PORTA_DIR _SFR_MEM8(0x0600) +-#define PORTA_DIRSET _SFR_MEM8(0x0601) +-#define PORTA_DIRCLR _SFR_MEM8(0x0602) +-#define PORTA_DIRTGL _SFR_MEM8(0x0603) +-#define PORTA_OUT _SFR_MEM8(0x0604) +-#define PORTA_OUTSET _SFR_MEM8(0x0605) +-#define PORTA_OUTCLR _SFR_MEM8(0x0606) +-#define PORTA_OUTTGL _SFR_MEM8(0x0607) +-#define PORTA_IN _SFR_MEM8(0x0608) +-#define PORTA_INTCTRL _SFR_MEM8(0x0609) +-#define PORTA_INT0MASK _SFR_MEM8(0x060A) +-#define PORTA_INT1MASK _SFR_MEM8(0x060B) +-#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +-#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +-#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +-#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +-#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +-#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +-#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +-#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +-#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) +- +-/* PORTB - Port B */ +-#define PORTB_DIR _SFR_MEM8(0x0620) +-#define PORTB_DIRSET _SFR_MEM8(0x0621) +-#define PORTB_DIRCLR _SFR_MEM8(0x0622) +-#define PORTB_DIRTGL _SFR_MEM8(0x0623) +-#define PORTB_OUT _SFR_MEM8(0x0624) +-#define PORTB_OUTSET _SFR_MEM8(0x0625) +-#define PORTB_OUTCLR _SFR_MEM8(0x0626) +-#define PORTB_OUTTGL _SFR_MEM8(0x0627) +-#define PORTB_IN _SFR_MEM8(0x0628) +-#define PORTB_INTCTRL _SFR_MEM8(0x0629) +-#define PORTB_INT0MASK _SFR_MEM8(0x062A) +-#define PORTB_INT1MASK _SFR_MEM8(0x062B) +-#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +-#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +-#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +-#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +-#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +-#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +-#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +-#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +-#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) +- +-/* PORTC - Port C */ +-#define PORTC_DIR _SFR_MEM8(0x0640) +-#define PORTC_DIRSET _SFR_MEM8(0x0641) +-#define PORTC_DIRCLR _SFR_MEM8(0x0642) +-#define PORTC_DIRTGL _SFR_MEM8(0x0643) +-#define PORTC_OUT _SFR_MEM8(0x0644) +-#define PORTC_OUTSET _SFR_MEM8(0x0645) +-#define PORTC_OUTCLR _SFR_MEM8(0x0646) +-#define PORTC_OUTTGL _SFR_MEM8(0x0647) +-#define PORTC_IN _SFR_MEM8(0x0648) +-#define PORTC_INTCTRL _SFR_MEM8(0x0649) +-#define PORTC_INT0MASK _SFR_MEM8(0x064A) +-#define PORTC_INT1MASK _SFR_MEM8(0x064B) +-#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +-#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +-#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +-#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +-#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +-#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +-#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +-#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +-#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) +- +-/* PORTD - Port D */ +-#define PORTD_DIR _SFR_MEM8(0x0660) +-#define PORTD_DIRSET _SFR_MEM8(0x0661) +-#define PORTD_DIRCLR _SFR_MEM8(0x0662) +-#define PORTD_DIRTGL _SFR_MEM8(0x0663) +-#define PORTD_OUT _SFR_MEM8(0x0664) +-#define PORTD_OUTSET _SFR_MEM8(0x0665) +-#define PORTD_OUTCLR _SFR_MEM8(0x0666) +-#define PORTD_OUTTGL _SFR_MEM8(0x0667) +-#define PORTD_IN _SFR_MEM8(0x0668) +-#define PORTD_INTCTRL _SFR_MEM8(0x0669) +-#define PORTD_INT0MASK _SFR_MEM8(0x066A) +-#define PORTD_INT1MASK _SFR_MEM8(0x066B) +-#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +-#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +-#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +-#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +-#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +-#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +-#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +-#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +-#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) +- +-/* PORTE - Port E */ +-#define PORTE_DIR _SFR_MEM8(0x0680) +-#define PORTE_DIRSET _SFR_MEM8(0x0681) +-#define PORTE_DIRCLR _SFR_MEM8(0x0682) +-#define PORTE_DIRTGL _SFR_MEM8(0x0683) +-#define PORTE_OUT _SFR_MEM8(0x0684) +-#define PORTE_OUTSET _SFR_MEM8(0x0685) +-#define PORTE_OUTCLR _SFR_MEM8(0x0686) +-#define PORTE_OUTTGL _SFR_MEM8(0x0687) +-#define PORTE_IN _SFR_MEM8(0x0688) +-#define PORTE_INTCTRL _SFR_MEM8(0x0689) +-#define PORTE_INT0MASK _SFR_MEM8(0x068A) +-#define PORTE_INT1MASK _SFR_MEM8(0x068B) +-#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +-#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +-#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +-#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +-#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +-#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +-#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +-#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +-#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) +- +-/* PORTR - Port R */ +-#define PORTR_DIR _SFR_MEM8(0x07E0) +-#define PORTR_DIRSET _SFR_MEM8(0x07E1) +-#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +-#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +-#define PORTR_OUT _SFR_MEM8(0x07E4) +-#define PORTR_OUTSET _SFR_MEM8(0x07E5) +-#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +-#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +-#define PORTR_IN _SFR_MEM8(0x07E8) +-#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +-#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +-#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +-#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +-#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +-#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +-#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +-#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +-#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +-#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +-#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +-#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) +- +-/* TCC0 - Timer/Counter C0 */ +-#define TCC0_CTRLA _SFR_MEM8(0x0800) +-#define TCC0_CTRLB _SFR_MEM8(0x0801) +-#define TCC0_CTRLC _SFR_MEM8(0x0802) +-#define TCC0_CTRLD _SFR_MEM8(0x0803) +-#define TCC0_CTRLE _SFR_MEM8(0x0804) +-#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +-#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +-#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +-#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +-#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +-#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +-#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +-#define TCC0_TEMP _SFR_MEM8(0x080F) +-#define TCC0_CNT _SFR_MEM16(0x0820) +-#define TCC0_PER _SFR_MEM16(0x0826) +-#define TCC0_CCA _SFR_MEM16(0x0828) +-#define TCC0_CCB _SFR_MEM16(0x082A) +-#define TCC0_CCC _SFR_MEM16(0x082C) +-#define TCC0_CCD _SFR_MEM16(0x082E) +-#define TCC0_PERBUF _SFR_MEM16(0x0836) +-#define TCC0_CCABUF _SFR_MEM16(0x0838) +-#define TCC0_CCBBUF _SFR_MEM16(0x083A) +-#define TCC0_CCCBUF _SFR_MEM16(0x083C) +-#define TCC0_CCDBUF _SFR_MEM16(0x083E) +- +-/* TCC1 - Timer/Counter C1 */ +-#define TCC1_CTRLA _SFR_MEM8(0x0840) +-#define TCC1_CTRLB _SFR_MEM8(0x0841) +-#define TCC1_CTRLC _SFR_MEM8(0x0842) +-#define TCC1_CTRLD _SFR_MEM8(0x0843) +-#define TCC1_CTRLE _SFR_MEM8(0x0844) +-#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +-#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +-#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +-#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +-#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +-#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +-#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +-#define TCC1_TEMP _SFR_MEM8(0x084F) +-#define TCC1_CNT _SFR_MEM16(0x0860) +-#define TCC1_PER _SFR_MEM16(0x0866) +-#define TCC1_CCA _SFR_MEM16(0x0868) +-#define TCC1_CCB _SFR_MEM16(0x086A) +-#define TCC1_PERBUF _SFR_MEM16(0x0876) +-#define TCC1_CCABUF _SFR_MEM16(0x0878) +-#define TCC1_CCBBUF _SFR_MEM16(0x087A) +- +-/* AWEXC - Advanced Waveform Extension C */ +-#define AWEXC_CTRL _SFR_MEM8(0x0880) +-#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +-#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +-#define AWEXC_STATUS _SFR_MEM8(0x0884) +-#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +-#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +-#define AWEXC_DTLS _SFR_MEM8(0x0888) +-#define AWEXC_DTHS _SFR_MEM8(0x0889) +-#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +-#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +-#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) +- +-/* HIRESC - High-Resolution Extension C */ +-#define HIRESC_CTRLA _SFR_MEM8(0x0890) +- +-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +-#define USARTC0_DATA _SFR_MEM8(0x08A0) +-#define USARTC0_STATUS _SFR_MEM8(0x08A1) +-#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +-#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +-#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +-#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +-#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) +- +-/* SPIC - Serial Peripheral Interface C */ +-#define SPIC_CTRL _SFR_MEM8(0x08C0) +-#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +-#define SPIC_STATUS _SFR_MEM8(0x08C2) +-#define SPIC_DATA _SFR_MEM8(0x08C3) +- +-/* IRCOM - IR Communication Module */ +-#define IRCOM_CTRL _SFR_MEM8(0x08F8) +-#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +-#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) +- +-/* TCD0 - Timer/Counter D0 */ +-#define TCD0_CTRLA _SFR_MEM8(0x0900) +-#define TCD0_CTRLB _SFR_MEM8(0x0901) +-#define TCD0_CTRLC _SFR_MEM8(0x0902) +-#define TCD0_CTRLD _SFR_MEM8(0x0903) +-#define TCD0_CTRLE _SFR_MEM8(0x0904) +-#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +-#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +-#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +-#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +-#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +-#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +-#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +-#define TCD0_TEMP _SFR_MEM8(0x090F) +-#define TCD0_CNT _SFR_MEM16(0x0920) +-#define TCD0_PER _SFR_MEM16(0x0926) +-#define TCD0_CCA _SFR_MEM16(0x0928) +-#define TCD0_CCB _SFR_MEM16(0x092A) +-#define TCD0_CCC _SFR_MEM16(0x092C) +-#define TCD0_CCD _SFR_MEM16(0x092E) +-#define TCD0_PERBUF _SFR_MEM16(0x0936) +-#define TCD0_CCABUF _SFR_MEM16(0x0938) +-#define TCD0_CCBBUF _SFR_MEM16(0x093A) +-#define TCD0_CCCBUF _SFR_MEM16(0x093C) +-#define TCD0_CCDBUF _SFR_MEM16(0x093E) +- +-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +-#define USARTD0_DATA _SFR_MEM8(0x09A0) +-#define USARTD0_STATUS _SFR_MEM8(0x09A1) +-#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +-#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +-#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +-#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +-#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) +- +-/* SPID - Serial Peripheral Interface D */ +-#define SPID_CTRL _SFR_MEM8(0x09C0) +-#define SPID_INTCTRL _SFR_MEM8(0x09C1) +-#define SPID_STATUS _SFR_MEM8(0x09C2) +-#define SPID_DATA _SFR_MEM8(0x09C3) +- +-/* TCE0 - Timer/Counter E0 */ +-#define TCE0_CTRLA _SFR_MEM8(0x0A00) +-#define TCE0_CTRLB _SFR_MEM8(0x0A01) +-#define TCE0_CTRLC _SFR_MEM8(0x0A02) +-#define TCE0_CTRLD _SFR_MEM8(0x0A03) +-#define TCE0_CTRLE _SFR_MEM8(0x0A04) +-#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +-#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +-#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +-#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +-#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +-#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +-#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +-#define TCE0_TEMP _SFR_MEM8(0x0A0F) +-#define TCE0_CNT _SFR_MEM16(0x0A20) +-#define TCE0_PER _SFR_MEM16(0x0A26) +-#define TCE0_CCA _SFR_MEM16(0x0A28) +-#define TCE0_CCB _SFR_MEM16(0x0A2A) +-#define TCE0_CCC _SFR_MEM16(0x0A2C) +-#define TCE0_CCD _SFR_MEM16(0x0A2E) +-#define TCE0_PERBUF _SFR_MEM16(0x0A36) +-#define TCE0_CCABUF _SFR_MEM16(0x0A38) +-#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +-#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +-#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) +- +- +- +-/*================== Bitfield Definitions ================== */ +- +-/* XOCD - On-Chip Debug System */ +-/* OCD.OCDR1 bit masks and bit positions */ +-#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +-#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ +- +- +-/* CPU - CPU */ +-/* CPU.CCP bit masks and bit positions */ +-#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +-#define CPU_CCP_gp 0 /* CCP signature group position. */ +-#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +-#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +-#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +-#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +-#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +-#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +-#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +-#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +-#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +-#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +-#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +-#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +-#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +-#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +-#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +-#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ +- +- +-/* CPU.SREG bit masks and bit positions */ +-#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +-#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ +- +-#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +-#define CPU_T_bp 6 /* Transfer Bit bit position. */ +- +-#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +-#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +- +-#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +-#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +- +-#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +-#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +- +-#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +-#define CPU_N_bp 2 /* Negative Flag bit position. */ +- +-#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +-#define CPU_Z_bp 1 /* Zero Flag bit position. */ +- +-#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +-#define CPU_C_bp 0 /* Carry Flag bit position. */ +- +- +-/* CLK - Clock System */ +-/* CLK.CTRL bit masks and bit positions */ +-#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +-#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +-#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +-#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +-#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +-#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +-#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +-#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ +- +- +-/* CLK.PSCTRL bit masks and bit positions */ +-#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +-#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +-#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +-#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +-#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +-#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +-#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +-#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +-#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +-#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +-#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +-#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ +- +-#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +-#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +-#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +-#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +-#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +-#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ +- +- +-/* CLK.LOCK bit masks and bit positions */ +-#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +-#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ +- +- +-/* CLK.RTCCTRL bit masks and bit positions */ +-#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +-#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +-#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +-#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +-#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +-#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +-#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +-#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ +- +-#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +-#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ +- +- +-/* PR.PRGEN bit masks and bit positions */ +-#define PR_AES_bm 0x10 /* AES bit mask. */ +-#define PR_AES_bp 4 /* AES bit position. */ +- +-#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +-#define PR_EBI_bp 3 /* External Bus Interface bit position. */ +- +-#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +-#define PR_RTC_bp 2 /* Real-time Counter bit position. */ +- +-#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +-#define PR_EVSYS_bp 1 /* Event System bit position. */ +- +-#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +-#define PR_DMA_bp 0 /* DMA-Controller bit position. */ +- +- +-/* PR.PRPA bit masks and bit positions */ +-#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +-#define PR_DAC_bp 2 /* Port A DAC bit position. */ +- +-#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +-#define PR_ADC_bp 1 /* Port A ADC bit position. */ +- +-#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +-#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ +- +- +-/* PR.PRPB bit masks and bit positions */ +-/* PR_DAC_bm Predefined. */ +-/* PR_DAC_bp Predefined. */ +- +-/* PR_ADC_bm Predefined. */ +-/* PR_ADC_bp Predefined. */ +- +-/* PR_AC_bm Predefined. */ +-/* PR_AC_bp Predefined. */ +- +- +-/* PR.PRPC bit masks and bit positions */ +-#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +-#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ +- +-#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +-#define PR_USART1_bp 5 /* Port C USART1 bit position. */ +- +-#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +-#define PR_USART0_bp 4 /* Port C USART0 bit position. */ +- +-#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +-#define PR_SPI_bp 3 /* Port C SPI bit position. */ +- +-#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +-#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ +- +-#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +-#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ +- +-#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +-#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ +- +- +-/* PR.PRPD bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* PR.PRPE bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* PR.PRPF bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* SLEEP - Sleep Controller */ +-/* SLEEP.CTRL bit masks and bit positions */ +-#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +-#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +-#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +-#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +-#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +-#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +-#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +-#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ +- +-#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +-#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ +- +- +-/* OSC - Oscillator */ +-/* OSC.CTRL bit masks and bit positions */ +-#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +-#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ +- +-#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +-#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ +- +-#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ +- +- +-/* OSC.STATUS bit masks and bit positions */ +-#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +-#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ +- +-#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +-#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ +- +-#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ +- +- +-/* OSC.XOSCCTRL bit masks and bit positions */ +-#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +-#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +-#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +-#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +-#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +-#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ +- +-#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +-#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ +- +-#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +-#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +-#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +-#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +-#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +-#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +-#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +-#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +-#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +-#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +- +- +-/* OSC.XOSCFAIL bit masks and bit positions */ +-#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +-#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ +- +-#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +-#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ +- +- +-/* OSC.PLLCTRL bit masks and bit positions */ +-#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +-#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +-#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +-#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +-#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +-#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ +- +-#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +-#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +-#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +-#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +-#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +-#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +-#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +-#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +-#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +-#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +-#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +-#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ +- +- +-/* OSC.DFLLCTRL bit masks and bit positions */ +-#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +-#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ +- +-#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +-#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ +- +- +-/* DFLL - DFLL */ +-/* DFLL.CTRL bit masks and bit positions */ +-#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +-#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ +- +- +-/* DFLL.CALA bit masks and bit positions */ +-#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +-#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +-#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +-#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +-#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +-#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +-#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +-#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +-#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +-#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +-#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +-#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +-#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +-#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +-#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +-#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ +- +- +-/* DFLL.CALB bit masks and bit positions */ +-#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +-#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +-#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +-#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +-#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +-#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +-#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +-#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +-#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +-#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +-#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +-#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +-#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +-#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ +- +- +-/* RST - Reset */ +-/* RST.STATUS bit masks and bit positions */ +-#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +-#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ +- +-#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +-#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ +- +-#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +-#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ +- +-#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +-#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ +- +-#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +-#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ +- +-#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +-#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ +- +-#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +-#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ +- +- +-/* RST.CTRL bit masks and bit positions */ +-#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +-#define RST_SWRST_bp 0 /* Software Reset bit position. */ +- +- +-/* WDT - Watch-Dog Timer */ +-/* WDT.CTRL bit masks and bit positions */ +-#define WDT_PER_gm 0x3C /* Period group mask. */ +-#define WDT_PER_gp 2 /* Period group position. */ +-#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +-#define WDT_PER0_bp 2 /* Period bit 0 position. */ +-#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +-#define WDT_PER1_bp 3 /* Period bit 1 position. */ +-#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +-#define WDT_PER2_bp 4 /* Period bit 2 position. */ +-#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +-#define WDT_PER3_bp 5 /* Period bit 3 position. */ +- +-#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +-#define WDT_ENABLE_bp 1 /* Enable bit position. */ +- +-#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +-#define WDT_CEN_bp 0 /* Change Enable bit position. */ +- +- +-/* WDT.WINCTRL bit masks and bit positions */ +-#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +-#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +-#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +-#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +-#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +-#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +-#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +-#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +-#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +-#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ +- +-#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +-#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ +- +-#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +-#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ +- +- +-/* WDT.STATUS bit masks and bit positions */ +-#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +-#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +- +- +-/* MCU - MCU Control */ +-/* MCU.MCUCR bit masks and bit positions */ +-#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +-#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ +- +- +-/* MCU.EVSYSLOCK bit masks and bit positions */ +-#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +-#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ +- +-#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +-#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ +- +- +-/* MCU.AWEXLOCK bit masks and bit positions */ +-#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +-#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ +- +-#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +-#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ +- +- +-/* PMIC - Programmable Multi-level Interrupt Controller */ +-/* PMIC.STATUS bit masks and bit positions */ +-#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +-#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ +- +-#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +-#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ +- +-#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +-#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ +- +-#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +-#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ +- +- +-/* PMIC.CTRL bit masks and bit positions */ +-#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +-#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ +- +-#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +-#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ +- +-#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +-#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ +- +-#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +-#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ +- +-#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +-#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ +- +- +-/* EVSYS - Event System */ +-/* EVSYS.CH0MUX bit masks and bit positions */ +-#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +-#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +-#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +-#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +-#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +-#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +-#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +-#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +-#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +-#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +-#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +-#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +-#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +-#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +-#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +-#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +-#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +-#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ +- +- +-/* EVSYS.CH1MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH2MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH3MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH0CTRL bit masks and bit positions */ +-#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +-#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +-#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +-#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +-#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +-#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ +- +-#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +-#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ +- +-#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +-#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ +- +-#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +-#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +-#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +-#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +-#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +-#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +-#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +-#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ +- +- +-/* EVSYS.CH1CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH2CTRL bit masks and bit positions */ +-/* EVSYS_QDIRM_gm Predefined. */ +-/* EVSYS_QDIRM_gp Predefined. */ +-/* EVSYS_QDIRM0_bm Predefined. */ +-/* EVSYS_QDIRM0_bp Predefined. */ +-/* EVSYS_QDIRM1_bm Predefined. */ +-/* EVSYS_QDIRM1_bp Predefined. */ +- +-/* EVSYS_QDIEN_bm Predefined. */ +-/* EVSYS_QDIEN_bp Predefined. */ +- +-/* EVSYS_QDEN_bm Predefined. */ +-/* EVSYS_QDEN_bp Predefined. */ +- +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH3CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* NVM - Non Volatile Memory Controller */ +-/* NVM.CMD bit masks and bit positions */ +-#define NVM_CMD_gm 0xFF /* Command group mask. */ +-#define NVM_CMD_gp 0 /* Command group position. */ +-#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +-#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +-#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +-#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +-#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +-#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +-#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +-#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +-#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +-#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +-#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +-#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +-#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +-#define NVM_CMD7_bp 7 /* Command bit 7 position. */ +- +- +-/* NVM.CTRLA bit masks and bit positions */ +-#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +-#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ +- +- +-/* NVM.CTRLB bit masks and bit positions */ +-#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +-#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ +- +-#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +-#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ +- +-#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +-#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ +- +-#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +-#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ +- +- +-/* NVM.INTCTRL bit masks and bit positions */ +-#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +-#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +-#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +-#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +-#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +-#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ +- +-#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +-#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +-#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +-#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +-#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +-#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ +- +- +-/* NVM.STATUS bit masks and bit positions */ +-#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +-#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ +- +-#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +-#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ +- +-#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +-#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ +- +-#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +-#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ +- +- +-/* NVM.LOCKBITS bit masks and bit positions */ +-#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +-#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +-#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ +-#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ +-#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ +-#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ +-#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ +-#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ +-#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ +-#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ +-#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ +-#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ +-#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ +-#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ +-#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ +-#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ +-#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ +-#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ +-#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ +-#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +-#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +-#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +-#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ +- +-#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +-#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +-#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +-#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +-#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ +- +-#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +-#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ +- +-#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +-#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +-#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +-#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +-#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +-#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +-#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +-#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +-#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +-#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +-#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +-#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ +- +-#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +-#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ +- +- +-/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +-#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +-#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +-#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +-#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +-#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +-#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ +- +-#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +-#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ +- +-#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +-#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +-#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +-#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +-#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +-#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +-#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +-#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +- +- +-/* AC - Analog Comparator */ +-/* AC.AC0CTRL bit masks and bit positions */ +-#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +-#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +-#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +-#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +-#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +-#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ +- +-#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +-#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +-#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +-#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +-#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +-#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ +- +-#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +-#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ +- +-#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +-#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +-#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +-#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +-#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +-#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +- +-#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define AC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* AC.AC1CTRL bit masks and bit positions */ +-/* AC_INTMODE_gm Predefined. */ +-/* AC_INTMODE_gp Predefined. */ +-/* AC_INTMODE0_bm Predefined. */ +-/* AC_INTMODE0_bp Predefined. */ +-/* AC_INTMODE1_bm Predefined. */ +-/* AC_INTMODE1_bp Predefined. */ +- +-/* AC_INTLVL_gm Predefined. */ +-/* AC_INTLVL_gp Predefined. */ +-/* AC_INTLVL0_bm Predefined. */ +-/* AC_INTLVL0_bp Predefined. */ +-/* AC_INTLVL1_bm Predefined. */ +-/* AC_INTLVL1_bp Predefined. */ +- +-/* AC_HSMODE_bm Predefined. */ +-/* AC_HSMODE_bp Predefined. */ +- +-/* AC_HYSMODE_gm Predefined. */ +-/* AC_HYSMODE_gp Predefined. */ +-/* AC_HYSMODE0_bm Predefined. */ +-/* AC_HYSMODE0_bp Predefined. */ +-/* AC_HYSMODE1_bm Predefined. */ +-/* AC_HYSMODE1_bp Predefined. */ +- +-/* AC_ENABLE_bm Predefined. */ +-/* AC_ENABLE_bp Predefined. */ +- +- +-/* AC.AC0MUXCTRL bit masks and bit positions */ +-#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +-#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +-#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +-#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +-#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +-#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +-#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +-#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ +- +-#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +-#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +-#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +-#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +-#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +-#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +-#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +-#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ +- +- +-/* AC.AC1MUXCTRL bit masks and bit positions */ +-/* AC_MUXPOS_gm Predefined. */ +-/* AC_MUXPOS_gp Predefined. */ +-/* AC_MUXPOS0_bm Predefined. */ +-/* AC_MUXPOS0_bp Predefined. */ +-/* AC_MUXPOS1_bm Predefined. */ +-/* AC_MUXPOS1_bp Predefined. */ +-/* AC_MUXPOS2_bm Predefined. */ +-/* AC_MUXPOS2_bp Predefined. */ +- +-/* AC_MUXNEG_gm Predefined. */ +-/* AC_MUXNEG_gp Predefined. */ +-/* AC_MUXNEG0_bm Predefined. */ +-/* AC_MUXNEG0_bp Predefined. */ +-/* AC_MUXNEG1_bm Predefined. */ +-/* AC_MUXNEG1_bp Predefined. */ +-/* AC_MUXNEG2_bm Predefined. */ +-/* AC_MUXNEG2_bp Predefined. */ +- +- +-/* AC.CTRLA bit masks and bit positions */ +-#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +-#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ +- +- +-/* AC.CTRLB bit masks and bit positions */ +-#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +-#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +-#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +-#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +-#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +-#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +-#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +-#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +-#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +-#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +-#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +-#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +-#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +-#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ +- +- +-/* AC.WINCTRL bit masks and bit positions */ +-#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +-#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ +- +-#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +-#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +-#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +-#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +-#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +-#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ +- +-#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +-#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +-#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +-#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +-#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +-#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ +- +- +-/* AC.STATUS bit masks and bit positions */ +-#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +-#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +-#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +-#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +-#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +-#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ +- +-#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +-#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ +- +-#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +-#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ +- +-#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +-#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ +- +-#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +-#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ +- +-#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +-#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ +- +- +-/* ADC - Analog/Digital Converter */ +-/* ADC_CH.CTRL bit masks and bit positions */ +-#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +-#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ +- +-#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +-#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +-#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +-#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +-#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +-#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +-#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +-#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ +- +-#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +-#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +-#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +-#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +-#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +-#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ +- +- +-/* ADC_CH.MUXCTRL bit masks and bit positions */ +-#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +-#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +-#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +-#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +-#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +-#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +-#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +-#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +-#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +-#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ +- +-#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +-#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +-#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +-#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +-#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +-#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +-#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +-#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +-#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +-#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ +- +-#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +-#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +-#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +-#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +-#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +-#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ +- +- +-/* ADC_CH.INTCTRL bit masks and bit positions */ +-#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +-#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +-#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +-#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +-#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +-#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ +- +-#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +-#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +-#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +-#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +-#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +-#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ +- +- +-/* ADC_CH.INTFLAGS bit masks and bit positions */ +-#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +-#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ +- +- +-/* ADC.CTRLA bit masks and bit positions */ +-#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +-#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ +- +-#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +-#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ +- +-#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +-#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ +- +- +-/* ADC.CTRLB bit masks and bit positions */ +-#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +-#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ +- +-#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +-#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ +- +-#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +-#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +-#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +-#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +-#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +-#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ +- +- +-/* ADC.REFCTRL bit masks and bit positions */ +-#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +-#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +-#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +-#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +-#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +-#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +- +-#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +-#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ +- +-#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +-#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ +- +- +-/* ADC.EVCTRL bit masks and bit positions */ +-#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +-#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +-#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +-#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +-#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +-#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ +- +-#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +-#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +-#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +-#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +-#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +-#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +-#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +-#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ +- +-#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +-#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +-#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +-#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +-#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +-#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +-#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +-#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ +- +- +-/* ADC.PRESCALER bit masks and bit positions */ +-#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +-#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +-#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +-#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +-#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +-#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +-#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +-#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ +- +- +-/* ADC.INTFLAGS bit masks and bit positions */ +-#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +-#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ +- +- +-/* RTC - Real-Time Clounter */ +-/* RTC.CTRL bit masks and bit positions */ +-#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +-#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +-#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +-#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +-#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +-#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +-#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +-#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ +- +- +-/* RTC.STATUS bit masks and bit positions */ +-#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +-#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ +- +- +-/* RTC.INTCTRL bit masks and bit positions */ +-#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +-#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +-#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +-#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +-#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +-#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ +- +-#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +-#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +-#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +-#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +-#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +-#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ +- +- +-/* RTC.INTFLAGS bit masks and bit positions */ +-#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +-#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ +- +-#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* EBI - External Bus Interface */ +-/* EBI_CS.CTRLA bit masks and bit positions */ +-#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +-#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +-#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +-#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +-#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +-#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +-#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +-#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +-#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +-#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +-#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +-#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ +- +-#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +-#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +-#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +-#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +-#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +-#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ +- +- +-/* EBI_CS.CTRLB bit masks and bit positions */ +-#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +-#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +-#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +-#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +-#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +-#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +-#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +-#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ +- +-#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +-#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ +- +-#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +-#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ +- +-#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +-#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +-#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +-#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +-#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +-#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ +- +- +-/* EBI.CTRL bit masks and bit positions */ +-#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +-#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +-#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +-#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +-#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +-#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ +- +-#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +-#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +-#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +-#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +-#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +-#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ +- +-#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +-#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +-#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +-#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +-#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +-#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ +- +-#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +-#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +-#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +-#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +-#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +-#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLA bit masks and bit positions */ +-#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +-#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ +- +-#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +-#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ +- +-#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +-#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +-#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +-#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +-#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +-#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLB bit masks and bit positions */ +-#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +-#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +-#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +-#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +-#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +-#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ +- +-#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +-#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +-#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +-#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +-#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +-#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +-#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +-#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ +- +-#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +-#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +-#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +-#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +-#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +-#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +-#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +-#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ +- +- +-/* EBI.SDRAMCTRLC bit masks and bit positions */ +-#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +-#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +-#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +-#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +-#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +-#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ +- +-#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +-#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +-#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +-#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +-#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +-#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +-#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +-#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ +- +-#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +-#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +-#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +-#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +-#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +-#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +-#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +-#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ +- +- +-/* TWI - Two-Wire Interface */ +-/* TWI_MASTER.CTRLA bit masks and bit positions */ +-#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +-#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ +- +-#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +-#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ +- +-#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +-#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ +- +- +-/* TWI_MASTER.CTRLB bit masks and bit positions */ +-#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +-#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +-#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +-#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +-#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +-#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +- +-#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +-#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ +- +-#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_MASTER.CTRLC bit masks and bit positions */ +-#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +-#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_MASTER.STATUS bit masks and bit positions */ +-#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +-#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ +- +-#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +-#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ +- +-#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +-#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +- +-#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +-#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +-#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +-#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +-#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +-#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +- +- +-/* TWI_SLAVE.CTRLA bit masks and bit positions */ +-#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +-#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +-#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ +- +-#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +-#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ +- +-#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_SLAVE.CTRLB bit masks and bit positions */ +-#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +-#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_SLAVE.STATUS bit masks and bit positions */ +-#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +-#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +-#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +-#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ +- +-#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +-#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ +- +-#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +-#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ +- +- +-/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +-#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +-#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +-#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +-#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +-#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +-#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +-#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +-#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +-#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +-#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +-#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +-#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +-#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +-#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +-#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +-#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ +- +-#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +-#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ +- +- +-/* TWI.CTRL bit masks and bit positions */ +-#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +-#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ +- +-#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +-#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ +- +- +-/* PORT - Port Configuration */ +-/* PORTCFG.VPCTRLA bit masks and bit positions */ +-#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +-#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +-#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +-#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +-#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +-#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +-#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +-#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +-#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +-#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ +- +-#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +-#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +-#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +-#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +-#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +-#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +-#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +-#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +-#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +-#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ +- +- +-/* PORTCFG.VPCTRLB bit masks and bit positions */ +-#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +-#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +-#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +-#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +-#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +-#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +-#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +-#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +-#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +-#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ +- +-#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +-#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +-#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +-#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +-#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +-#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +-#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +-#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +-#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +-#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ +- +- +-/* PORTCFG.CLKEVOUT bit masks and bit positions */ +-#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +-#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +-#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +-#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +-#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +-#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ +- +-#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +-#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +-#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +-#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +-#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +-#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ +- +- +-/* VPORT.INTFLAGS bit masks and bit positions */ +-#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.INTCTRL bit masks and bit positions */ +-#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +-#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +-#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +-#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +-#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +-#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ +- +-#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +-#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +-#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +-#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +-#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +-#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ +- +- +-/* PORT.INTFLAGS bit masks and bit positions */ +-#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.PIN0CTRL bit masks and bit positions */ +-#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +-#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ +- +-#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +-#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ +- +-#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +-#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +-#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +-#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +-#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +-#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +-#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +-#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ +- +-#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +-#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +-#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +-#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +-#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +-#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +-#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +-#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +- +- +-/* PORT.PIN1CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN2CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN3CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN4CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN5CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN6CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN7CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* TC - 16-bit Timer/Counter With PWM */ +-/* TC0.CTRLA bit masks and bit positions */ +-#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC0.CTRLB bit masks and bit positions */ +-#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +-#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ +- +-#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +-#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ +- +-#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC0.CTRLC bit masks and bit positions */ +-#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +-#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ +- +-#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +-#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ +- +-#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC0.CTRLD bit masks and bit positions */ +-#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC0_EVACT_gp 5 /* Event Action group position. */ +-#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC0.CTRLE bit masks and bit positions */ +-#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +-#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ +- +-#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC0.INTCTRLA bit masks and bit positions */ +-#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC0.INTCTRLB bit masks and bit positions */ +-#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +-#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +-#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +-#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +-#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +-#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ +- +-#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +-#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +-#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +-#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +-#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +-#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ +- +-#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC0.CTRLFCLR bit masks and bit positions */ +-#define TC0_CMD_gm 0x0C /* Command group mask. */ +-#define TC0_CMD_gp 2 /* Command group position. */ +-#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC0_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC0_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC0_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC0.CTRLFSET bit masks and bit positions */ +-/* TC0_CMD_gm Predefined. */ +-/* TC0_CMD_gp Predefined. */ +-/* TC0_CMD0_bm Predefined. */ +-/* TC0_CMD0_bp Predefined. */ +-/* TC0_CMD1_bm Predefined. */ +-/* TC0_CMD1_bp Predefined. */ +- +-/* TC0_LUPD_bm Predefined. */ +-/* TC0_LUPD_bp Predefined. */ +- +-/* TC0_DIR_bm Predefined. */ +-/* TC0_DIR_bp Predefined. */ +- +- +-/* TC0.CTRLGCLR bit masks and bit positions */ +-#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +-#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ +- +-#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +-#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ +- +-#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC0.CTRLGSET bit masks and bit positions */ +-/* TC0_CCDBV_bm Predefined. */ +-/* TC0_CCDBV_bp Predefined. */ +- +-/* TC0_CCCBV_bm Predefined. */ +-/* TC0_CCCBV_bp Predefined. */ +- +-/* TC0_CCBBV_bm Predefined. */ +-/* TC0_CCBBV_bp Predefined. */ +- +-/* TC0_CCABV_bm Predefined. */ +-/* TC0_CCABV_bp Predefined. */ +- +-/* TC0_PERBV_bm Predefined. */ +-/* TC0_PERBV_bp Predefined. */ +- +- +-/* TC0.INTFLAGS bit masks and bit positions */ +-#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +-#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ +- +-#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +-#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ +- +-#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* TC1.CTRLA bit masks and bit positions */ +-#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC1.CTRLB bit masks and bit positions */ +-#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC1.CTRLC bit masks and bit positions */ +-#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC1.CTRLD bit masks and bit positions */ +-#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC1_EVACT_gp 5 /* Event Action group position. */ +-#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC1.CTRLE bit masks and bit positions */ +-#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +-#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ +- +-#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC1.INTCTRLA bit masks and bit positions */ +-#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC1.INTCTRLB bit masks and bit positions */ +-#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC1.CTRLFCLR bit masks and bit positions */ +-#define TC1_CMD_gm 0x0C /* Command group mask. */ +-#define TC1_CMD_gp 2 /* Command group position. */ +-#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC1_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC1_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC1_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC1.CTRLFSET bit masks and bit positions */ +-/* TC1_CMD_gm Predefined. */ +-/* TC1_CMD_gp Predefined. */ +-/* TC1_CMD0_bm Predefined. */ +-/* TC1_CMD0_bp Predefined. */ +-/* TC1_CMD1_bm Predefined. */ +-/* TC1_CMD1_bp Predefined. */ +- +-/* TC1_LUPD_bm Predefined. */ +-/* TC1_LUPD_bp Predefined. */ +- +-/* TC1_DIR_bm Predefined. */ +-/* TC1_DIR_bp Predefined. */ +- +- +-/* TC1.CTRLGCLR bit masks and bit positions */ +-#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC1.CTRLGSET bit masks and bit positions */ +-/* TC1_CCBBV_bm Predefined. */ +-/* TC1_CCBBV_bp Predefined. */ +- +-/* TC1_CCABV_bm Predefined. */ +-/* TC1_CCABV_bp Predefined. */ +- +-/* TC1_PERBV_bm Predefined. */ +-/* TC1_PERBV_bp Predefined. */ +- +- +-/* TC1.INTFLAGS bit masks and bit positions */ +-#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* AWEX.CTRL bit masks and bit positions */ +-#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +-#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ +- +-#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +-#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ +- +-#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +-#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ +- +-#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +-#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ +- +-#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +-#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ +- +-#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +-#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ +- +- +-/* AWEX.FDCTRL bit masks and bit positions */ +-#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +-#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ +- +-#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +-#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ +- +-#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +-#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +-#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +-#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +-#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +-#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ +- +- +-/* AWEX.STATUS bit masks and bit positions */ +-#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +-#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ +- +-#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +-#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ +- +-#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +-#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ +- +- +-/* HIRES.CTRL bit masks and bit positions */ +-#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +-#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +-#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +-#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +-#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +-#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ +- +- +-/* USART - Universal Asynchronous Receiver-Transmitter */ +-/* USART.STATUS bit masks and bit positions */ +-#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +-#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ +- +-#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +-#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +- +-#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +-#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +- +-#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +-#define USART_FERR_bp 4 /* Frame Error bit position. */ +- +-#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +-#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ +- +-#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +-#define USART_PERR_bp 2 /* Parity Error bit position. */ +- +-#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +-#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ +- +- +-/* USART.CTRLA bit masks and bit positions */ +-#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +-#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +-#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +-#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +-#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +-#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ +- +-#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +-#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +-#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +-#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +-#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +-#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ +- +-#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +-#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +-#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +-#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +-#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +-#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ +- +- +-/* USART.CTRLB bit masks and bit positions */ +-#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +-#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ +- +-#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +-#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ +- +-#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +-#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ +- +-#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +-#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ +- +-#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +-#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ +- +- +-/* USART.CTRLC bit masks and bit positions */ +-#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +-#define USART_CMODE_gp 6 /* Communication Mode group position. */ +-#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +-#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +-#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +-#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ +- +-#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +-#define USART_PMODE_gp 4 /* Parity Mode group position. */ +-#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +-#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +-#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +-#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +- +-#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +-#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +- +-#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +-#define USART_CHSIZE_gp 0 /* Character Size group position. */ +-#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +-#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +-#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +-#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +-#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +-#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +- +- +-/* USART.BAUDCTRLA bit masks and bit positions */ +-#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +-#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +-#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +-#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +-#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +-#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +-#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +-#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +-#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +-#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +-#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +-#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +-#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +-#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +-#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +-#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +-#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +-#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ +- +- +-/* USART.BAUDCTRLB bit masks and bit positions */ +-#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +-#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +-#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +-#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +-#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +-#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +-#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +-#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +-#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +-#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ +- +-/* USART_BSEL_gm Predefined. */ +-/* USART_BSEL_gp Predefined. */ +-/* USART_BSEL0_bm Predefined. */ +-/* USART_BSEL0_bp Predefined. */ +-/* USART_BSEL1_bm Predefined. */ +-/* USART_BSEL1_bp Predefined. */ +-/* USART_BSEL2_bm Predefined. */ +-/* USART_BSEL2_bp Predefined. */ +-/* USART_BSEL3_bm Predefined. */ +-/* USART_BSEL3_bp Predefined. */ +- +- +-/* SPI - Serial Peripheral Interface */ +-/* SPI.CTRL bit masks and bit positions */ +-#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +-#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ +- +-#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +-#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ +- +-#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +-#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ +- +-#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +-#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ +- +-#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +-#define SPI_MODE_gp 2 /* SPI Mode group position. */ +-#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +-#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +-#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +-#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ +- +-#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +-#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +-#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +-#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +-#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +-#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ +- +- +-/* SPI.INTCTRL bit masks and bit positions */ +-#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +-#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +-/* SPI.STATUS bit masks and bit positions */ +-#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +-#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ +- +-#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +-#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +- +- +-/* IRCOM - IR Communication Module */ +-/* IRCOM.CTRL bit masks and bit positions */ +-#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +-#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +-#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +-#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +-#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +-#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +-#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +-#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +-#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +-#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ +- +- +- +-// Generic Port Pins +- +-#define PIN0_bm 0x01 +-#define PIN0_bp 0 +-#define PIN1_bm 0x02 +-#define PIN1_bp 1 +-#define PIN2_bm 0x04 +-#define PIN2_bp 2 +-#define PIN3_bm 0x08 +-#define PIN3_bp 3 +-#define PIN4_bm 0x10 +-#define PIN4_bp 4 +-#define PIN5_bm 0x20 +-#define PIN5_bp 5 +-#define PIN6_bm 0x40 +-#define PIN6_bp 6 +-#define PIN7_bm 0x80 +-#define PIN7_bp 7 +- +- +-/* ========== Interrupt Vector Definitions ========== */ +-/* Vector 0 is the reset vector */ +- +-/* OSC interrupt vectors */ +-#define OSC_XOSCF_vect_num 1 +-#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ +- +-/* PORTC interrupt vectors */ +-#define PORTC_INT0_vect_num 2 +-#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +-#define PORTC_INT1_vect_num 3 +-#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ +- +-/* PORTR interrupt vectors */ +-#define PORTR_INT0_vect_num 4 +-#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +-#define PORTR_INT1_vect_num 5 +-#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ +- +-/* RTC interrupt vectors */ +-#define RTC_OVF_vect_num 10 +-#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +-#define RTC_COMP_vect_num 11 +-#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ +- +-/* TWIC interrupt vectors */ +-#define TWIC_TWIS_vect_num 12 +-#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +-#define TWIC_TWIM_vect_num 13 +-#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ +- +-/* TCC0 interrupt vectors */ +-#define TCC0_OVF_vect_num 14 +-#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +-#define TCC0_ERR_vect_num 15 +-#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +-#define TCC0_CCA_vect_num 16 +-#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +-#define TCC0_CCB_vect_num 17 +-#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +-#define TCC0_CCC_vect_num 18 +-#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +-#define TCC0_CCD_vect_num 19 +-#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ +- +-/* TCC1 interrupt vectors */ +-#define TCC1_OVF_vect_num 20 +-#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +-#define TCC1_ERR_vect_num 21 +-#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +-#define TCC1_CCA_vect_num 22 +-#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +-#define TCC1_CCB_vect_num 23 +-#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ +- +-/* SPIC interrupt vectors */ +-#define SPIC_INT_vect_num 24 +-#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ +- +-/* USARTC0 interrupt vectors */ +-#define USARTC0_RXC_vect_num 25 +-#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +-#define USARTC0_DRE_vect_num 26 +-#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +-#define USARTC0_TXC_vect_num 27 +-#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ +- +-/* NVM interrupt vectors */ +-#define NVM_EE_vect_num 32 +-#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +-#define NVM_SPM_vect_num 33 +-#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ +- +-/* PORTB interrupt vectors */ +-#define PORTB_INT0_vect_num 34 +-#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +-#define PORTB_INT1_vect_num 35 +-#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ +- +-/* PORTE interrupt vectors */ +-#define PORTE_INT0_vect_num 43 +-#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +-#define PORTE_INT1_vect_num 44 +-#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ +- +-/* TCE0 interrupt vectors */ +-#define TCE0_OVF_vect_num 47 +-#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +-#define TCE0_ERR_vect_num 48 +-#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +-#define TCE0_CCA_vect_num 49 +-#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +-#define TCE0_CCB_vect_num 50 +-#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +-#define TCE0_CCC_vect_num 51 +-#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +-#define TCE0_CCD_vect_num 52 +-#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ +- +-/* PORTD interrupt vectors */ +-#define PORTD_INT0_vect_num 64 +-#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +-#define PORTD_INT1_vect_num 65 +-#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ +- +-/* PORTA interrupt vectors */ +-#define PORTA_INT0_vect_num 66 +-#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +-#define PORTA_INT1_vect_num 67 +-#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ +- +-/* ACA interrupt vectors */ +-#define ACA_AC0_vect_num 68 +-#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +-#define ACA_AC1_vect_num 69 +-#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +-#define ACA_ACW_vect_num 70 +-#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ +- +-/* ADCA interrupt vectors */ +-#define ADCA_CH0_vect_num 71 +-#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +- +-/* TCD0 interrupt vectors */ +-#define TCD0_OVF_vect_num 77 +-#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +-#define TCD0_ERR_vect_num 78 +-#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +-#define TCD0_CCA_vect_num 79 +-#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +-#define TCD0_CCB_vect_num 80 +-#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +-#define TCD0_CCC_vect_num 81 +-#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +-#define TCD0_CCD_vect_num 82 +-#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ +- +-/* SPID interrupt vectors */ +-#define SPID_INT_vect_num 87 +-#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ +- +-/* USARTD0 interrupt vectors */ +-#define USARTD0_RXC_vect_num 88 +-#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +-#define USARTD0_DRE_vect_num 89 +-#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +-#define USARTD0_TXC_vect_num 90 +-#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ +- +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (91 * _VECTOR_SIZE) +- +- +-/* ========== Constants ========== */ +- +-#define PROGMEM_START (0x0000) +-#define PROGMEM_SIZE (20480) +-#define PROGMEM_PAGE_SIZE (256) +-#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) +- +-#define APP_SECTION_START (0x0000) +-#define APP_SECTION_SIZE (16384) +-#define APP_SECTION_PAGE_SIZE (256) +-#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) +- +-#define APPTABLE_SECTION_START (0x3000) +-#define APPTABLE_SECTION_SIZE (4096) +-#define APPTABLE_SECTION_PAGE_SIZE (256) +-#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) +- +-#define BOOT_SECTION_START (0x4000) +-#define BOOT_SECTION_SIZE (4096) +-#define BOOT_SECTION_PAGE_SIZE (256) +-#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) +- +-#define DATAMEM_START (0x0000) +-#define DATAMEM_SIZE (10240) +-#define DATAMEM_PAGE_SIZE (0) +-#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) +- +-#define IO_START (0x0000) +-#define IO_SIZE (4096) +-#define IO_PAGE_SIZE (0) +-#define IO_END (IO_START + IO_SIZE - 1) +- +-#define MAPPED_EEPROM_START (0x1000) +-#define MAPPED_EEPROM_SIZE (1024) +-#define MAPPED_EEPROM_PAGE_SIZE (0) +-#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) +- +-#define INTERNAL_SRAM_START (0x2000) +-#define INTERNAL_SRAM_SIZE (2048) +-#define INTERNAL_SRAM_PAGE_SIZE (0) +-#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) +- +-#define EEPROM_START (0x0000) +-#define EEPROM_SIZE (1024) +-#define EEPROM_PAGE_SIZE (32) +-#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) +- +-#define FUSE_START (0x0000) +-#define FUSE_SIZE (6) +-#define FUSE_PAGE_SIZE (0) +-#define FUSE_END (FUSE_START + FUSE_SIZE - 1) +- +-#define LOCKBIT_START (0x0000) +-#define LOCKBIT_SIZE (1) +-#define LOCKBIT_PAGE_SIZE (0) +-#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) +- +-#define SIGNATURES_START (0x0000) +-#define SIGNATURES_SIZE (3) +-#define SIGNATURES_PAGE_SIZE (0) +-#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) +- +-#define USER_SIGNATURES_START (0x0000) +-#define USER_SIGNATURES_SIZE (256) +-#define USER_SIGNATURES_PAGE_SIZE (0) +-#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) +- +-#define PROD_SIGNATURES_START (0x0000) +-#define PROD_SIGNATURES_SIZE (52) +-#define PROD_SIGNATURES_PAGE_SIZE (0) +-#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) +- +-#define FLASHEND PROGMEM_END +-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +-#define RAMSTART INTERNAL_SRAM_START +-#define RAMSIZE INTERNAL_SRAM_SIZE +-#define RAMEND INTERNAL_SRAM_END +-#define XRAMSTART EXTERNAL_SRAM_START +-#define XRAMSIZE EXTERNAL_SRAM_SIZE +-#define XRAMEND INTERNAL_SRAM_END +-#define E2END EEPROM_END +-#define E2PAGESIZE EEPROM_PAGE_SIZE +- +- +-/* ========== Fuses ========== */ +-#define FUSE_MEMORY_SIZE 6 +- +-/* Fuse Byte 0 */ +-#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ +-#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ +-#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ +-#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ +-#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ +-#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ +-#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ +-#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ +-#define FUSE0_DEFAULT (0xFF) +- +-/* Fuse Byte 1 */ +-#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +-#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +-#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +-#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +-#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +-#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +-#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +-#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +-#define FUSE1_DEFAULT (0xFF) +- +-/* Fuse Byte 2 */ +-#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +-#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +-#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +-#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +-#define FUSE2_DEFAULT (0xFF) +- +-/* Fuse Byte 3 Reserved */ +- +-/* Fuse Byte 4 */ +-#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +-#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +-#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +-#define FUSE4_DEFAULT (0xFF) +- +-/* Fuse Byte 5 */ +-#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +-#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +-#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +-#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +-#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +-#define FUSE5_DEFAULT (0xFF) +- +- +-/* ========== Lock Bits ========== */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_BITS_EXIST +-#define __BOOT_LOCK_BOOT_BITS_EXIST +- +- +-/* ========== Signature ========== */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x94 +-#define SIGNATURE_2 0x42 +- +- +-#endif /* _AVR_ATxmega16D4_H_ */ +- ++/* Copyright (c) 2009-2010 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iox16d4.h 2200 2010-12-14 04:24:24Z arcanum $ */ ++ ++/* avr/iox16d4.h - definitions for ATxmega16D4 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox16d4.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATxmega16D4_H_ ++#define _AVR_ATxmega16D4_H_ 1 ++ ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++} CLK_t; ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t PRPB; /* Power Reduction Port B */ ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ ++} CLK_RTCSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control REgister */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t reserved_0x07; ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ ++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ ++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ ++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ ++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ ++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ ++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ ++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ ++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ ++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t FUSEBYTE0; /* User ID */ ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ ++ register8_t reserved_0x01; ++ register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ ++ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ ++ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ ++ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++} NVM_PROD_SIGNATURES_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++} NVM_LB_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brown Out Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ ++ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Comparator 0 Control */ ++ register8_t AC1CTRL; /* Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t reserved_0x6; ++ register8_t reserved_0x7; ++} ADC_CH_t; ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++} ADC_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0, INPUTMODE[1:0] = 10 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1, INPUTMODE[1:0] = 10 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2, INPUTMODE[1:0] = 10 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3, INPUTMODE[1:0] = 10 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4, INPUTMODE[1:0] = 11 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5, INPUTMODE[1:0] = 11 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6, INPUTMODE[1:0] = 11 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7, INPUTMODE[1:0] = 11 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ ++} ADC_CURRLIMIT_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++} ADC_REFSEL_t; ++ ++/* Channel sweep selection */ ++typedef enum ADC_SWEEP_enum ++{ ++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ++} ADC_SWEEP_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Clounter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* EBI Chip Select Module */ ++typedef struct EBI_CS_struct ++{ ++ register8_t CTRLA; /* Chip Select Control Register A */ ++ register8_t CTRLB; /* Chip Select Control Register B */ ++ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ ++} EBI_CS_t; ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* External Bus Interface */ ++typedef struct EBI_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ ++ register8_t reserved_0x02; ++ register8_t reserved_0x03; ++ _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ ++ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ ++ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ ++ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ EBI_CS_t CS0; /* Chip Select 0 */ ++ EBI_CS_t CS1; /* Chip Select 1 */ ++ EBI_CS_t CS2; /* Chip Select 2 */ ++ EBI_CS_t CS3; /* Chip Select 3 */ ++} EBI_t; ++ ++/* Chip Select adress space */ ++typedef enum EBI_CS_ASIZE_enum ++{ ++ EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ ++ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ ++ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ ++ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ ++ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ ++ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ ++ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ ++ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ ++ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ ++ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ ++ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ ++ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ ++ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ ++ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ ++ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ ++ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ ++ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ ++} EBI_CS_ASIZE_t; ++ ++/* */ ++typedef enum EBI_CS_SRWS_enum ++{ ++ EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_CS_SRWS_t; ++ ++/* Chip Select address mode */ ++typedef enum EBI_CS_MODE_enum ++{ ++ EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ ++ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ ++ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ ++ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ ++} EBI_CS_MODE_t; ++ ++/* Chip Select SDRAM mode */ ++typedef enum EBI_CS_SDMODE_enum ++{ ++ EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ ++ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ ++} EBI_CS_SDMODE_t; ++ ++/* */ ++typedef enum EBI_SDDATAW_enum ++{ ++ EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ ++ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ ++} EBI_SDDATAW_t; ++ ++/* */ ++typedef enum EBI_LPCMODE_enum ++{ ++ EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ ++ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ ++} EBI_LPCMODE_t; ++ ++/* */ ++typedef enum EBI_SRMODE_enum ++{ ++ EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ ++ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ ++ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ ++ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ ++} EBI_SRMODE_t; ++ ++/* */ ++typedef enum EBI_IFMODE_enum ++{ ++ EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ ++ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ ++ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ ++ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ ++} EBI_IFMODE_t; ++ ++/* */ ++typedef enum EBI_SDCOL_enum ++{ ++ EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ ++ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ ++ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ ++ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ ++} EBI_SDCOL_t; ++ ++/* */ ++typedef enum EBI_MRDLY_enum ++{ ++ EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_MRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCYCDLY_enum ++{ ++ EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ROWCYCDLY_t; ++ ++/* */ ++typedef enum EBI_RPDLY_enum ++{ ++ EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_RPDLY_t; ++ ++/* */ ++typedef enum EBI_WRDLY_enum ++{ ++ EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_WRDLY_t; ++ ++/* */ ++typedef enum EBI_ESRDLY_enum ++{ ++ EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ESRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCOLDLY_enum ++{ ++ EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_ROWCOLDLY_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++} PORTCFG_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Virtual Port 0 Mapping */ ++typedef enum PORTCFG_VP0MAP_enum ++{ ++ PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP0MAP_t; ++ ++/* Virtual Port 1 Mapping */ ++typedef enum PORTCFG_VP1MAP_enum ++{ ++ PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP1MAP_t; ++ ++/* Virtual Port 2 Mapping */ ++typedef enum PORTCFG_VP2MAP_enum ++{ ++ PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP2MAP_t; ++ ++/* Virtual Port 3 Mapping */ ++typedef enum PORTCFG_VP3MAP_enum ++{ ++ PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP3MAP_t; ++ ++/* Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x05; ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset Controller */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ ++#define PORTA (*(PORT_t *) 0x0600) /* Port A */ ++#define PORTB (*(PORT_t *) 0x0620) /* Port B */ ++#define PORTC (*(PORT_t *) 0x0640) /* Port C */ ++#define PORTD (*(PORT_t *) 0x0660) /* Port D */ ++#define PORTE (*(PORT_t *) 0x0680) /* Port E */ ++#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ ++#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++#define GPIO_GPIOR4 _SFR_MEM8(0x0004) ++#define GPIO_GPIOR5 _SFR_MEM8(0x0005) ++#define GPIO_GPIOR6 _SFR_MEM8(0x0006) ++#define GPIO_GPIOR7 _SFR_MEM8(0x0007) ++#define GPIO_GPIOR8 _SFR_MEM8(0x0008) ++#define GPIO_GPIOR9 _SFR_MEM8(0x0009) ++#define GPIO_GPIORA _SFR_MEM8(0x000A) ++#define GPIO_GPIORB _SFR_MEM8(0x000B) ++#define GPIO_GPIORC _SFR_MEM8(0x000C) ++#define GPIO_GPIORD _SFR_MEM8(0x000D) ++#define GPIO_GPIORE _SFR_MEM8(0x000E) ++#define GPIO_GPIORF _SFR_MEM8(0x000F) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++#define GPIO_GPIO4 _SFR_MEM8(0x0004) ++#define GPIO_GPIO5 _SFR_MEM8(0x0005) ++#define GPIO_GPIO6 _SFR_MEM8(0x0006) ++#define GPIO_GPIO7 _SFR_MEM8(0x0007) ++#define GPIO_GPIO8 _SFR_MEM8(0x0008) ++#define GPIO_GPIO9 _SFR_MEM8(0x0009) ++#define GPIO_GPIOA _SFR_MEM8(0x000A) ++#define GPIO_GPIOB _SFR_MEM8(0x000B) ++#define GPIO_GPIOC _SFR_MEM8(0x000C) ++#define GPIO_GPIOD _SFR_MEM8(0x000D) ++#define GPIO_GPIOE _SFR_MEM8(0x000E) ++#define GPIO_GPIOF _SFR_MEM8(0x000F) ++ ++/* VPORT0 - Virtual Port 0 */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT1 - Virtual Port 1 */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT2 - Virtual Port 2 */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT3 - Virtual Port 3 */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU Registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator Control */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPB _SFR_MEM8(0x0072) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset Controller */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - Port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non Volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADCA - Analog to Digital Converter A */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++ ++/* ACA - Analog Comparator A */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWIC - Two-Wire Interface C */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWIE - Two-Wire Interface E */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++ ++/* PORTA - Port A */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORTB - Port B */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORTC - Port C */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORTD - Port D */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORTE - Port E */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORTR - Port R */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TCC0 - Timer/Counter C0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TCC1 - Timer/Counter C1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEXC - Advanced Waveform Extension C */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRESC - High-Resolution Extension C */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* SPIC - Serial Peripheral Interface C */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TCD0 - Timer/Counter D0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* SPID - Serial Peripheral Interface D */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TCE0 - Timer/Counter E0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR1 bit masks and bit positions */ ++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ ++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ ++ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ ++ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ ++#define PR_EBI_bp 3 /* External Bus Interface bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ ++#define PR_DAC_bp 2 /* Port A DAC bit position. */ ++ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++ ++/* PR.PRPB bit masks and bit positions */ ++/* PR_DAC_bm Predefined. */ ++/* PR_DAC_bp Predefined. */ ++ ++/* PR_ADC_bm Predefined. */ ++/* PR_ADC_bp Predefined. */ ++ ++/* PR_AC_bm Predefined. */ ++/* PR_AC_bp Predefined. */ ++ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ ++ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ ++ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ ++ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ ++#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ ++ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ ++ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ ++ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ ++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ ++ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM_gm Predefined. */ ++/* EVSYS_QDIRM_gp Predefined. */ ++/* EVSYS_QDIRM0_bm Predefined. */ ++/* EVSYS_QDIRM0_bp Predefined. */ ++/* EVSYS_QDIRM1_bm Predefined. */ ++/* EVSYS_QDIRM1_bp Predefined. */ ++ ++/* EVSYS_QDIEN_bm Predefined. */ ++/* EVSYS_QDIEN_bp Predefined. */ ++ ++/* EVSYS_QDEN_bm Predefined. */ ++/* EVSYS_QDEN_bp Predefined. */ ++ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0xFF /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ ++#define NVM_CMD7_bp 7 /* Command bit 7 position. */ ++ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ ++#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ ++#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ ++#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ ++#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ ++#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ ++#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ ++#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ ++#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ ++#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ ++#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ ++#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ ++#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ ++#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ ++#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ ++#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ ++#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ ++#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ ++#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ ++#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ ++ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ ++ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ ++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE_gm Predefined. */ ++/* AC_INTMODE_gp Predefined. */ ++/* AC_INTMODE0_bm Predefined. */ ++/* AC_INTMODE0_bp Predefined. */ ++/* AC_INTMODE1_bm Predefined. */ ++/* AC_INTMODE1_bp Predefined. */ ++ ++/* AC_INTLVL_gm Predefined. */ ++/* AC_INTLVL_gp Predefined. */ ++/* AC_INTLVL0_bm Predefined. */ ++/* AC_INTLVL0_bp Predefined. */ ++/* AC_INTLVL1_bm Predefined. */ ++/* AC_INTLVL1_bp Predefined. */ ++ ++/* AC_HSMODE_bm Predefined. */ ++/* AC_HSMODE_bp Predefined. */ ++ ++/* AC_HYSMODE_gm Predefined. */ ++/* AC_HYSMODE_gp Predefined. */ ++/* AC_HYSMODE0_bm Predefined. */ ++/* AC_HYSMODE0_bp Predefined. */ ++/* AC_HYSMODE1_bm Predefined. */ ++/* AC_HYSMODE1_bp Predefined. */ ++ ++/* AC_ENABLE_bm Predefined. */ ++/* AC_ENABLE_bp Predefined. */ ++ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS_gm Predefined. */ ++/* AC_MUXPOS_gp Predefined. */ ++/* AC_MUXPOS0_bm Predefined. */ ++/* AC_MUXPOS0_bp Predefined. */ ++/* AC_MUXPOS1_bm Predefined. */ ++/* AC_MUXPOS1_bp Predefined. */ ++/* AC_MUXPOS2_bm Predefined. */ ++/* AC_MUXPOS2_bp Predefined. */ ++ ++/* AC_MUXNEG_gm Predefined. */ ++/* AC_MUXNEG_gp Predefined. */ ++/* AC_MUXNEG0_bm Predefined. */ ++/* AC_MUXNEG0_bp Predefined. */ ++/* AC_MUXNEG1_bm Predefined. */ ++/* AC_MUXNEG1_bp Predefined. */ ++/* AC_MUXNEG2_bm Predefined. */ ++/* AC_MUXNEG2_bp Predefined. */ ++ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ ++ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ ++ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ ++#define ADC_CH_MUXPOS4_bm (1<<7) /* Positive Input Select bit 3 mask. */ ++#define ADC_CH_MUXPOS4_bp 7 /* Positive Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ ++ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ ++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_IMPMODE_bm 0x80 /* Impedance Mode bit mask. */ ++#define ADC_IMPMODE_bp 7 /* Impedance Mode bit position. */ ++ ++#define ADC_CURRENT_bm 0x60 /* Current bit mask. */ ++#define ADC_CURRENT1_bp 6 /* Current bit position. */ ++#define ADC_CURRENT0_bp 5 /* Current bit position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ ++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ ++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ ++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ ++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ ++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ ++ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++ ++/* RTC - Real-Time Clounter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* EBI - External Bus Interface */ ++/* EBI_CS.CTRLA bit masks and bit positions */ ++#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ ++#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ ++#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ ++#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ ++#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ ++#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ ++#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ ++#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ ++#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ ++#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ ++#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ ++#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ ++ ++#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ ++#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ ++#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ ++#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ ++#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ ++#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ ++ ++ ++/* EBI_CS.CTRLB bit masks and bit positions */ ++#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ ++#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ ++#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ ++#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ ++#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ ++#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ ++#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ ++#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ ++ ++#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ ++#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ ++ ++#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ ++#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ ++ ++#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ ++#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ ++#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ ++#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ ++#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ ++#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ ++ ++ ++/* EBI.CTRL bit masks and bit positions */ ++#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ ++#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ ++#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ ++#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ ++#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ ++#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ ++ ++#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ ++#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ ++#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ ++#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ ++#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ ++#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ ++ ++#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ ++#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ ++#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ ++#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ ++#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ ++#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ ++ ++#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ ++#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ ++#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ ++#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ ++#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ ++#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLA bit masks and bit positions */ ++#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ ++#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ ++ ++#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ ++#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ ++ ++#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ ++#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ ++#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ ++#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ ++#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ ++#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLB bit masks and bit positions */ ++#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ ++#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ ++#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ ++#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ ++#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ ++#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ ++ ++#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ ++#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ ++#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ ++#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ ++#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ ++#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ ++#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ ++#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ ++ ++#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ ++#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ ++#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ ++#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ ++#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ ++#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ ++#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ ++#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ ++ ++ ++/* EBI.SDRAMCTRLC bit masks and bit positions */ ++#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ ++#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ ++#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ ++#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ ++#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ ++#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ ++ ++#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ ++#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ ++#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ ++#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ ++#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ ++#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ ++#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ ++#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ ++ ++#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ ++#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ ++#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ ++#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ ++#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ ++#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ ++#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ ++#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ ++ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ ++#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++ ++/* PORT - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ ++#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ ++ ++#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD_gm Predefined. */ ++/* TC0_CMD_gp Predefined. */ ++/* TC0_CMD0_bm Predefined. */ ++/* TC0_CMD0_bp Predefined. */ ++/* TC0_CMD1_bm Predefined. */ ++/* TC0_CMD1_bp Predefined. */ ++ ++/* TC0_LUPD_bm Predefined. */ ++/* TC0_LUPD_bp Predefined. */ ++ ++/* TC0_DIR_bm Predefined. */ ++/* TC0_DIR_bp Predefined. */ ++ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV_bm Predefined. */ ++/* TC0_CCDBV_bp Predefined. */ ++ ++/* TC0_CCCBV_bm Predefined. */ ++/* TC0_CCCBV_bp Predefined. */ ++ ++/* TC0_CCBBV_bm Predefined. */ ++/* TC0_CCBBV_bp Predefined. */ ++ ++/* TC0_CCABV_bm Predefined. */ ++/* TC0_CCABV_bp Predefined. */ ++ ++/* TC0_PERBV_bm Predefined. */ ++/* TC0_PERBV_bp Predefined. */ ++ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ ++#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ ++ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD_gm Predefined. */ ++/* TC1_CMD_gp Predefined. */ ++/* TC1_CMD0_bm Predefined. */ ++/* TC1_CMD0_bp Predefined. */ ++/* TC1_CMD1_bm Predefined. */ ++/* TC1_CMD1_bp Predefined. */ ++ ++/* TC1_LUPD_bm Predefined. */ ++/* TC1_LUPD_bp Predefined. */ ++ ++/* TC1_DIR_bm Predefined. */ ++/* TC1_DIR_bp Predefined. */ ++ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV_bm Predefined. */ ++/* TC1_CCBBV_bp Predefined. */ ++ ++/* TC1_CCABV_bm Predefined. */ ++/* TC1_CCABV_bp Predefined. */ ++ ++/* TC1_PERBV_bm Predefined. */ ++/* TC1_PERBV_bp Predefined. */ ++ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++ ++/* HIRES.CTRL bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL_gm Predefined. */ ++/* USART_BSEL_gp Predefined. */ ++/* USART_BSEL0_bm Predefined. */ ++/* USART_BSEL0_bp Predefined. */ ++/* USART_BSEL1_bm Predefined. */ ++/* USART_BSEL1_bp Predefined. */ ++/* USART_BSEL2_bm Predefined. */ ++/* USART_BSEL2_bp Predefined. */ ++/* USART_BSEL3_bm Predefined. */ ++/* USART_BSEL3_bp Predefined. */ ++ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_XOSCF_vect_num 1 ++#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (91 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (20480) ++#define PROGMEM_PAGE_SIZE (256) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (16384) ++#define APP_SECTION_PAGE_SIZE (256) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x3000) ++#define APPTABLE_SECTION_SIZE (4096) ++#define APPTABLE_SECTION_PAGE_SIZE (256) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x4000) ++#define BOOT_SECTION_SIZE (4096) ++#define BOOT_SECTION_PAGE_SIZE (256) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (10240) ++#define DATAMEM_PAGE_SIZE (0) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (1024) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (2048) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (1024) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define FUSE_START (0x0000) ++#define FUSE_SIZE (6) ++#define FUSE_PAGE_SIZE (0) ++#define FUSE_END (FUSE_START + FUSE_SIZE - 1) ++ ++#define LOCKBIT_START (0x0000) ++#define LOCKBIT_SIZE (1) ++#define LOCKBIT_PAGE_SIZE (0) ++#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (256) ++#define USER_SIGNATURES_PAGE_SIZE (0) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (0) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE PROGMEM_PAGE_SIZE ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define XRAMSTART EXTERNAL_SRAM_START ++#define XRAMSIZE EXTERNAL_SRAM_SIZE ++#define XRAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 */ ++#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ ++#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ ++#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ ++#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ ++#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ ++#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ ++#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ ++#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ ++#define FUSE0_DEFAULT (0xFF) ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x42 ++ ++ ++#endif /* _AVR_ATxmega16D4_H_ */ ++ +diff --git a/include/avr/iox16e5.h b/include/avr/iox16e5.h +new file mode 100644 +index 0000000..974b168 +--- /dev/null ++++ b/include/avr/iox16e5.h +@@ -0,0 +1,7664 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox16e5.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA16E5_H_INCLUDED ++#define _AVR_ATXMEGA16E5_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t reserved_0x04; ++} CLK_t; ++ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t reserved_0x02; ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++ CLK_SCLKSEL_RC8M_gc = (0x05<<0), /* Internal 8 MHz RC Oscillator */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++ CLK_PSADIV_6_gc = (0x13<<2), /* Divide by 6 */ ++ CLK_PSADIV_10_gc = (0x15<<2), /* Divide by 10 */ ++ CLK_PSADIV_12_gc = (0x17<<2), /* Divide by 12 */ ++ CLK_PSADIV_24_gc = (0x19<<2), /* Divide by 24 */ ++ CLK_PSADIV_48_gc = (0x1B<<2), /* Divide by 48 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++ register8_t RC8MCAL; /* Internal 8 MHz RC Oscillator Calibration Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ ++ OSC_XOSCSEL_EXTCLK_C4_gc = (0x14<<0), /* External Clock on port C4 - 6 CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC8M_gc = (0x01<<6), /* Internal 8 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t WEXLOCK; /* WEX Lock */ ++ register8_t FAULTLOCK; /* FAULT Lock */ ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t reserved_0x03; ++ register8_t CLKOUT; /* Clock Out Register */ ++ register8_t reserved_0x05; ++ register8_t ACEVOUT; /* Analog Comparator and Event Out Register */ ++ register8_t SRLCTRL; /* Slew Rate Limit Control Register */ ++} PORTCFG_t; ++ ++/* Clock and Event Output Port */ ++typedef enum PORTCFG_CLKEVPIN_enum ++{ ++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ ++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ ++} PORTCFG_CLKEVPIN_t; ++ ++/* RTC Clock Output Port */ ++typedef enum PORTCFG_RTCCLKOUT_enum ++{ ++ PORTCFG_RTCCLKOUT_OFF_gc = (0x00<<5), /* System Clock Output Disabled */ ++ PORTCFG_RTCCLKOUT_PC6_gc = (0x01<<5), /* System Clock Output on Port C pin 6 */ ++ PORTCFG_RTCCLKOUT_PD6_gc = (0x02<<5), /* System Clock Output on Port D pin 6 */ ++ PORTCFG_RTCCLKOUT_PR0_gc = (0x03<<5), /* System Clock Output on Port R pin 0 */ ++} PORTCFG_RTCCLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PR0_gc = (0x03<<0), /* System Clock Output on Port R pin 0 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Analog Comparator Output Port */ ++typedef enum PORTCFG_ACOUT_enum ++{ ++ PORTCFG_ACOUT_PA_gc = (0x00<<6), /* Analog Comparator Outputs on Port A, Pin 6-7 */ ++ PORTCFG_ACOUT_PC_gc = (0x01<<6), /* Analog Comparator Outputs on Port C, Pin 6-7 */ ++ PORTCFG_ACOUT_PD_gc = (0x02<<6), /* Analog Comparator Outputs on Port D, Pin 6-7 */ ++ PORTCFG_ACOUT_PR_gc = (0x03<<6), /* Analog Comparator Outputs on Port R, Pin 0-1 */ ++} PORTCFG_ACOUT_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel n Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel n Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PR0_gc = (0x03<<4), /* Event Channel n Output on Port R pin 0 */ ++} PORTCFG_EVOUT_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ ++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ ++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ ++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ ++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ ++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ ++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ ++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EDMA - Enhanced DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* EDMA Channel */ ++typedef struct EDMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control A */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Memory Address Control for Peripheral Ch., or Source Address Control for Standard Ch. */ ++ register8_t DESTADDRCTRL; /* Destination Address Control for Standard Channels Only. */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch. */ ++ _WORDREGISTER(ADDR); /* Channel Memory Address for Peripheral Ch., or Channel Source Address Low for Standard Ch. */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(DESTADDR); /* Channel Destination Address for Standard Channels Only. */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} EDMA_CH_t; ++ ++ ++/* Enhanced DMA Controller */ ++typedef struct EDMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ EDMA_CH_t CH0; /* EDMA Channel 0 */ ++ EDMA_CH_t CH1; /* EDMA Channel 1 */ ++ EDMA_CH_t CH2; /* EDMA Channel 2 */ ++ EDMA_CH_t CH3; /* EDMA Channel 3 */ ++} EDMA_t; ++ ++/* Channel mode */ ++typedef enum EDMA_CHMODE_enum ++{ ++ EDMA_CHMODE_PER0123_gc = (0x00<<4), /* Channels 0, 1, 2 and 3 in peripheal conf. */ ++ EDMA_CHMODE_STD0_gc = (0x01<<4), /* Channel 0 in standard conf.; channels 2 and 3 in peripheral conf. */ ++ EDMA_CHMODE_STD2_gc = (0x02<<4), /* Channel 2 in standard conf.; channels 0 and 1 in peripheral conf. */ ++ EDMA_CHMODE_STD02_gc = (0x03<<4), /* Channels 0 and 2 in standard conf. */ ++} EDMA_CHMODE_t; ++ ++/* Double buffer mode */ ++typedef enum EDMA_DBUFMODE_enum ++{ ++ EDMA_DBUFMODE_DISABLE_gc = (0x00<<2), /* No double buffer enabled */ ++ EDMA_DBUFMODE_BUF01_gc = (0x01<<2), /* Double buffer enabled on peripheral channels 0/1 (if exist) */ ++ EDMA_DBUFMODE_BUF23_gc = (0x02<<2), /* Double buffer enabled on peripheral channels 2/3 (if exist) */ ++ EDMA_DBUFMODE_BUF0123_gc = (0x03<<2), /* Double buffer enabled on peripheral channels 0/1 and 2/3 or standard channels 0/2 */ ++} EDMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum EDMA_PRIMODE_enum ++{ ++ EDMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round robin on all channels */ ++ EDMA_PRIMODE_RR123_gc = (0x01<<0), /* Ch0 > round robin (Ch 1 ch2 Ch3) */ ++ EDMA_PRIMODE_RR23_gc = (0x02<<0), /* Ch0 > Ch 1 > round robin (Ch2 Ch3) */ ++ EDMA_PRIMODE_CH0123_gc = (0x03<<0), /* Ch0 > Ch1 > Ch2 > Ch3 */ ++} EDMA_PRIMODE_t; ++ ++/* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. */ ++typedef enum EDMA_CH_RELOAD_enum ++{ ++ EDMA_CH_RELOAD_NONE_gc = (0x00<<4), /* No reload */ ++ EDMA_CH_RELOAD_BLOCK_gc = (0x01<<4), /* Reload at end of each block transfer */ ++ EDMA_CH_RELOAD_BURST_gc = (0x02<<4), /* Reload at end of each burst transfer */ ++ EDMA_CH_RELOAD_TRANSACTION_gc = (0x03<<4), /* Reload at end of each transaction */ ++} EDMA_CH_RELOAD_t; ++ ++/* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. */ ++typedef enum EDMA_CH_DIR_enum ++{ ++ EDMA_CH_DIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ EDMA_CH_DIR_INC_gc = (0x01<<0), /* Increment */ ++ EDMA_CH_DIR_MP1_gc = (0x04<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'mask-match' (data: ADDRL, mask: ADDRH), else reserved conf. */ ++ EDMA_CH_DIR_MP2_gc = (0x05<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH), else reserved conf. */ ++ EDMA_CH_DIR_MP3_gc = (0x06<<0), /* If Peripheral Ch. (Per ==> Mem), 2-byte 'match' (data-1: ADDRL followed by data-2: ADDRH), else reserved conf. */ ++} EDMA_CH_DIR_t; ++ ++/* Destination addressing mode */ ++typedef enum EDMA_CH_DESTDIR_enum ++{ ++ EDMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ EDMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ EDMA_CH_DESTDIR_MP1_gc = (0x04<<0), /* 1-byte 'mask-match' (data: ADDRL, mask: ADDRH) */ ++ EDMA_CH_DESTDIR_MP2_gc = (0x05<<0), /* 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH) */ ++ EDMA_CH_DESTDIR_MP3_gc = (0x06<<0), /* 2-byte 'match' (data1: ADDRL followed by data2: ADDRH) */ ++} EDMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum EDMA_CH_TRIGSRC_enum ++{ ++ EDMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Software triggers only */ ++ EDMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event CH0 as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event CH1 as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event CH2 as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA CH0 as trigger */ ++ EDMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA CH0 as trigger */ ++ EDMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA CH1 as trigger */ ++ EDMA_CH_TRIGSRC_TCC4_OVF_gc = (0x40<<0), /* TCC4 overflow/underflow as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCC4_ERR_gc = (0x41<<0), /* TCC4 error as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCC4_CCA_gc = (0x42<<0), /* TCC4 compare or capture channel A as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCC4_CCB_gc = (0x43<<0), /* TCC4 compare or capture channel B as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCC4_CCC_gc = (0x44<<0), /* TCC4 compare or capture channel C as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCC4_CCD_gc = (0x45<<0), /* TCC4 compare or capture channel D as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCC5_OVF_gc = (0x46<<0), /* TCC5 overflow/underflow as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCC5_ERR_gc = (0x47<<0), /* TCC5 error as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCC5_CCA_gc = (0x48<<0), /* TCC5 compare or capture channel A as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCC5_CCB_gc = (0x49<<0), /* TCC5 compare or capture channel B as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_SPIC_RXC_gc = (0x4A<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C receive complete as trigger (SPI Buffer Modes) */ ++ EDMA_CH_TRIGSRC_SPIC_DRE_gc = (0x4B<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C data register empty as trigger (SPI Buffer modes) */ ++ EDMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4C<<0), /* USART C0 receive complete as trigger */ ++ EDMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4D<<0), /* USART C0 data register empty as trigger */ ++ EDMA_CH_TRIGSRC_TCD5_OVF_gc = (0x66<<0), /* TCD5 overflow/underflow as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCD5_ERR_gc = (0x67<<0), /* TCD5 error as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCD5_CCA_gc = (0x68<<0), /* TCD5 compare or capture channel A as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCD5_CCB_gc = (0x69<<0), /* TCD5 compare or capture channel B as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6C<<0), /* USART D0 receive complete as trigger */ ++ EDMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6D<<0), /* USART D0 data register empty as trigger */ ++} EDMA_CH_TRIGSRC_t; ++ ++/* Interrupt level */ ++typedef enum EDMA_CH_INTLVL_enum ++{ ++ EDMA_CH_INTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ EDMA_CH_INTLVL_LO_gc = (0x01<<2), /* Low level */ ++ EDMA_CH_INTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ EDMA_CH_INTLVL_HI_gc = (0x03<<2), /* High level */ ++} EDMA_CH_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ ++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ ++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ ++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t CH4CTRL; /* Channel 4 Control Register */ ++ register8_t CH5CTRL; /* Channel 5 Control Register */ ++ register8_t CH6CTRL; /* Channel 6 Control Register */ ++ register8_t CH7CTRL; /* Channel 7 Control Register */ ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++ register8_t DFCTRL; /* Digital Filter Control Register */ ++} EVSYS_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_XCL_UNF0_gc = (0xB0<<0), /* XCL BTC0 underflow */ ++ EVSYS_CHMUX_XCL_UNF1_gc = (0xB1<<0), /* XCL BTC1 underflow */ ++ EVSYS_CHMUX_XCL_CC0_gc = (0xB2<<0), /* XCL BTC0 capture or compare */ ++ EVSYS_CHMUX_XCL_CC1_gc = (0xB3<<0), /* XCL BTC0 capture or compare */ ++ EVSYS_CHMUX_XCL_PEC0_gc = (0xB4<<0), /* XCL PEC0 restart */ ++ EVSYS_CHMUX_XCL_PEC1_gc = (0xB5<<0), /* XCL PEC1 restart */ ++ EVSYS_CHMUX_XCL_LUT0_gc = (0xB6<<0), /* XCL LUT0 output */ ++ EVSYS_CHMUX_XCL_LUT1_gc = (0xB7<<0), /* XCL LUT1 output */ ++ EVSYS_CHMUX_TCC4_OVF_gc = (0xC0<<0), /* Timer/Counter C4 Overflow */ ++ EVSYS_CHMUX_TCC4_ERR_gc = (0xC1<<0), /* Timer/Counter C4 Error */ ++ EVSYS_CHMUX_TCC4_CCA_gc = (0xC4<<0), /* Timer/Counter C4 Compare or Capture A */ ++ EVSYS_CHMUX_TCC4_CCB_gc = (0xC5<<0), /* Timer/Counter C4 Compare or Capture B */ ++ EVSYS_CHMUX_TCC4_CCC_gc = (0xC6<<0), /* Timer/Counter C4 Compare or Capture C */ ++ EVSYS_CHMUX_TCC4_CCD_gc = (0xC7<<0), /* Timer/Counter C4 Compare or Capture D */ ++ EVSYS_CHMUX_TCC5_OVF_gc = (0xC8<<0), /* Timer/Counter C5 Overflow */ ++ EVSYS_CHMUX_TCC5_ERR_gc = (0xC9<<0), /* Timer/Counter C5 Error */ ++ EVSYS_CHMUX_TCC5_CCA_gc = (0xCC<<0), /* Timer/Counter C5 Compare or Capture A */ ++ EVSYS_CHMUX_TCC5_CCB_gc = (0xCD<<0), /* Timer/Counter C5 Compare or Capture B */ ++ EVSYS_CHMUX_TCD5_OVF_gc = (0xD8<<0), /* Timer/Counter D5 Overflow */ ++ EVSYS_CHMUX_TCD5_ERR_gc = (0xD9<<0), /* Timer/Counter D5 Error */ ++ EVSYS_CHMUX_TCD5_CCA_gc = (0xDC<<0), /* Timer/Counter D5 Compare or Capture A */ ++ EVSYS_CHMUX_TCD5_CCB_gc = (0xDD<<0), /* Timer/Counter D5 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Prescaler Filter */ ++typedef enum EVSYS_PRESCFILT_enum ++{ ++ EVSYS_PRESCFILT_CH04_gc = (0x01<<4), /* Enable prescaler filter for either channel 0 or 4 */ ++ EVSYS_PRESCFILT_CH15_gc = (0x02<<4), /* Enable prescaler filter for either channel 1 or 5 */ ++ EVSYS_PRESCFILT_CH26_gc = (0x04<<4), /* Enable prescaler filter for either channel 2 or 6 */ ++ EVSYS_PRESCFILT_CH37_gc = (0x08<<4), /* Enable prescaler filter for either channel 3 or 7 */ ++} EVSYS_PRESCFILT_t; ++ ++/* Prescaler */ ++typedef enum EVSYS_PRESCALER_enum ++{ ++ EVSYS_PRESCALER_CLKPER_8_gc = (0x00<<0), /* CLKPER, divide by 8 */ ++ EVSYS_PRESCALER_CLKPER_64_gc = (0x01<<0), /* CLKPER, divide by 64 */ ++ EVSYS_PRESCALER_CLKPER_512_gc = (0x02<<0), /* CLKPER, divide by 512 */ ++ EVSYS_PRESCALER_CLKPER_4096_gc = (0x03<<0), /* CLKPER, divide by 4096 */ ++ EVSYS_PRESCALER_CLKPER_32768_gc = (0x04<<0), /* CLKPER, divide by 32768 */ ++} EVSYS_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t CORRCTRL; /* Correction Control Register */ ++ register8_t OFFSETCORR0; /* Offset Correction Register 0 */ ++ register8_t OFFSETCORR1; /* Offset Correction Register 1 */ ++ register8_t GAINCORR0; /* Gain Correction Register 0 */ ++ register8_t GAINCORR1; /* Gain Correction Register 1 */ ++ register8_t AVGCTRL; /* Average Control Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++} ADC_t; ++ ++/* Current Limitation */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ ++} ADC_CURRLIMIT_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_MT12BIT_gc = (0x01<<1), /* More than 12-bit (oversapling) right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFD_gc = (0x03<<4), /* External reference on PORT D */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ ++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ ++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ ++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ ++ ADC_EVSEL_4_gc = (0x04<<3), /* Event Channel 4 */ ++ ADC_EVSEL_5_gc = (0x05<<3), /* Event Channel 5 */ ++ ADC_EVSEL_6_gc = (0x06<<3), /* Event Channel 6 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel conversion */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAINL_gc = (0x02<<0), /* Differential input, gain with 4 LSB pins selection */ ++ ADC_CH_INPUTMODE_DIFFWGAINH_gc = (0x03<<0), /* Differential input, gain with 4 MSB pins selection */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 Scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC Output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection when gain on 4 LSB pins */ ++typedef enum ADC_CH_MUXNEGL_enum ++{ ++ ADC_CH_MUXNEGL_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEGL_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEGL_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEGL_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEGL_GND_gc = (0x05<<0), /* PAD ground */ ++ ADC_CH_MUXNEGL_INTGND_gc = (0x07<<0), /* Internal ground */ ++} ADC_CH_MUXNEGL_t; ++ ++/* Negative input multiplexer selection when gain on 4 MSB pins */ ++typedef enum ADC_CH_MUXNEGH_enum ++{ ++ ADC_CH_MUXNEGH_PIN4_gc = (0x00<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEGH_PIN5_gc = (0x01<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEGH_PIN6_gc = (0x02<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEGH_PIN7_gc = (0x03<<0), /* Input pin 7 */ ++ ADC_CH_MUXNEGH_GND_gc = (0x05<<0), /* PAD ground */ ++} ADC_CH_MUXNEGH_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* Averaged Number of Samples */ ++typedef enum ADC_SAMPNUM_enum ++{ ++ ADC_SAMPNUM_1X_gc = (0x00<<0), /* 1 Sample */ ++ ADC_SAMPNUM_2X_gc = (0x01<<0), /* 2 Samples */ ++ ADC_SAMPNUM_4X_gc = (0x02<<0), /* 4 Samples */ ++ ADC_SAMPNUM_8X_gc = (0x03<<0), /* 8 Samples */ ++ ADC_SAMPNUM_16X_gc = (0x04<<0), /* 16 Samples */ ++ ADC_SAMPNUM_32X_gc = (0x05<<0), /* 32 Samples */ ++ ADC_SAMPNUM_64X_gc = (0x06<<0), /* 64 Samples */ ++ ADC_SAMPNUM_128X_gc = (0x07<<0), /* 128 Samples */ ++ ADC_SAMPNUM_256X_gc = (0x08<<0), /* 256 Samples */ ++ ADC_SAMPNUM_512X_gc = (0x09<<0), /* 512 Samples */ ++ ADC_SAMPNUM_1024X_gc = (0x0A<<0), /* 1024 Samples */ ++} ADC_SAMPNUM_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DAC - Digital/Analog Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Digital-to-Analog Converter */ ++typedef struct DAC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t EVCTRL; /* Event Input Control */ ++ register8_t reserved_0x04; ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0GAINCAL; /* Gain Calibration */ ++ register8_t CH0OFFSETCAL; /* Offset Calibration */ ++ register8_t CH1GAINCAL; /* Gain Calibration */ ++ register8_t CH1OFFSETCAL; /* Offset Calibration */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ ++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ ++} DAC_t; ++ ++/* Output channel selection */ ++typedef enum DAC_CHSEL_enum ++{ ++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ ++ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ ++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ ++} DAC_CHSEL_t; ++ ++/* Reference voltage selection */ ++typedef enum DAC_REFSEL_enum ++{ ++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ ++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ ++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ ++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ ++} DAC_REFSEL_t; ++ ++/* Event channel selection */ ++typedef enum DAC_EVSEL_enum ++{ ++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ ++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ ++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ ++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ ++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ ++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ ++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ ++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ ++} DAC_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++ register8_t CURRCTRL; /* Current Source Control Register */ ++ register8_t CURRCALIB; /* Current Source Calibration Register */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Clounter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t CALIB; /* Calibration Register */ ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XCL - XMEGA Custom Logic ++-------------------------------------------------------------------------- ++*/ ++ ++/* XMEGA Custom Logic */ ++typedef struct XCL_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t CTRLF; /* Control Register F */ ++ register8_t CTRLG; /* Control Register G */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t PLC; /* Peripheral Lenght Control Register */ ++ register8_t CNTL; /* Counter Register Low */ ++ register8_t CNTH; /* Counter Register High */ ++ register8_t CMPL; /* Compare Register Low */ ++ register8_t CMPH; /* Compare Register High */ ++ register8_t PERCAPTL; /* Period or Capture Register Low */ ++ register8_t PERCAPTH; /* Period or Capture Register High */ ++} XCL_t; ++ ++/* LUT0 Output Enable */ ++typedef enum XCL_LUTOUTEN_enum ++{ ++ XCL_LUTOUTEN_DISABLE_gc = (0x00<<6), /* LUT0 output disabled */ ++ XCL_LUTOUTEN_PIN0_gc = (0x01<<6), /* LUT0 Output to pin 0 */ ++ XCL_LUTOUTEN_PIN4_gc = (0x02<<6), /* LUT0 Output to pin 4 */ ++} XCL_LUTOUTEN_t; ++ ++/* Port Selection */ ++typedef enum XCL_PORTSEL_enum ++{ ++ XCL_PORTSEL_PC_gc = (0x00<<4), /* Port C for LUT or USARTC0 for PEC */ ++ XCL_PORTSEL_PD_gc = (0x01<<4), /* Port D for LUT or USARTD0 for PEC */ ++} XCL_PORTSEL_t; ++ ++/* LUT Configuration */ ++typedef enum XCL_LUTCONF_enum ++{ ++ XCL_LUTCONF_2LUT2IN_gc = (0x00<<0), /* 2-Input two LUT */ ++ XCL_LUTCONF_2LUT1IN_gc = (0x01<<0), /* Two LUT with duplicated input */ ++ XCL_LUTCONF_2LUT3IN_gc = (0x02<<0), /* Two LUT with one common input */ ++ XCL_LUTCONF_1LUT3IN_gc = (0x03<<0), /* 3-Input LUT */ ++ XCL_LUTCONF_MUX_gc = (0x04<<0), /* One LUT Mux */ ++ XCL_LUTCONF_DLATCH_gc = (0x05<<0), /* One D-Latch LUT */ ++ XCL_LUTCONF_RSLATCH_gc = (0x06<<0), /* One RS-Latch LUT */ ++ XCL_LUTCONF_DFF_gc = (0x07<<0), /* One DFF LUT */ ++} XCL_LUTCONF_t; ++ ++/* Input Selection */ ++typedef enum XCL_INSEL_enum ++{ ++ XCL_INSEL_EVSYS_gc = (0x00<<6), /* Event system selected as source */ ++ XCL_INSEL_XCL_gc = (0x01<<6), /* XCL selected as source */ ++ XCL_INSEL_PINL_gc = (0x02<<6), /* LSB port pin selected as source */ ++ XCL_INSEL_PINH_gc = (0x03<<6), /* MSB port pin selected as source */ ++} XCL_INSEL_t; ++ ++/* Delay Configuration on LUT */ ++typedef enum XCL_DLYCONF_enum ++{ ++ XCL_DLYCONF_DISABLE_gc = (0x00<<2), /* Delay element disabled */ ++ XCL_DLYCONF_IN_gc = (0x01<<2), /* Delay enabled on LUT input */ ++ XCL_DLYCONF_OUT_gc = (0x02<<2), /* Delay enabled on LUT output */ ++} XCL_DLYCONF_t; ++ ++/* Delay Selection */ ++typedef enum XCL_DLYSEL_enum ++{ ++ XCL_DLYSEL_DLY11_gc = (0x00<<4), /* One cycle delay for each LUT1 and LUT0 */ ++ XCL_DLYSEL_DLY12_gc = (0x01<<4), /* One cycle delay for LUT1 and two cycles for LUT0 */ ++ XCL_DLYSEL_DLY21_gc = (0x02<<4), /* Two cycles delay for LUT1 and one cycle for LUT0 */ ++ XCL_DLYSEL_DLY22_gc = (0x03<<4), /* Two cycle delays for each LUT1 and LUT0 */ ++} XCL_DLYSEL_t; ++ ++/* Clock Selection */ ++typedef enum XCL_CLKSEL_enum ++{ ++ XCL_CLKSEL_OFF_gc = (0x00<<0), /* OFF */ ++ XCL_CLKSEL_DIV1_gc = (0x01<<0), /* Prescaler clk */ ++ XCL_CLKSEL_DIV2_gc = (0x02<<0), /* Prescaler clk/2 */ ++ XCL_CLKSEL_DIV4_gc = (0x03<<0), /* Prescaler clk/4 */ ++ XCL_CLKSEL_DIV8_gc = (0x04<<0), /* Prescaler clk/8 */ ++ XCL_CLKSEL_DIV64_gc = (0x05<<0), /* Prescaler clk/64 */ ++ XCL_CLKSEL_DIV256_gc = (0x06<<0), /* Prescaler clk/256 */ ++ XCL_CLKSEL_DIV1024_gc = (0x07<<0), /* Prescaler clk/1024 */ ++ XCL_CLKSEL_EVCH0_gc = (0x08<<0), /* Event channel 0 */ ++ XCL_CLKSEL_EVCH1_gc = (0x09<<0), /* Event channel 1 */ ++ XCL_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event channel 2 */ ++ XCL_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event channel 3 */ ++ XCL_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event channel 4 */ ++ XCL_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event channel 5 */ ++ XCL_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event channel 6 */ ++ XCL_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event channel 7 */ ++} XCL_CLKSEL_t; ++ ++/* Timer/Counter Command Selection */ ++typedef enum XCL_CMDSEL_enum ++{ ++ XCL_CMDSEL_NONE_gc = (0x00<<7), /* None */ ++ XCL_CMDSEL_RESTART_gc = (0x01<<7), /* Force restart */ ++} XCL_CMDSEL_t; ++ ++/* Timer/Counter Selection */ ++typedef enum XCL_TCSEL_enum ++{ ++ XCL_TCSEL_TC16_gc = (0x00<<4), /* 16-bit timer/counter */ ++ XCL_TCSEL_BTC0_gc = (0x01<<4), /* One 8-bit timer/counter */ ++ XCL_TCSEL_BTC01_gc = (0x02<<4), /* Two 8-bit timer/counters */ ++ XCL_TCSEL_BTC0PEC1_gc = (0x03<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ ++ XCL_TCSEL_PEC0BTC1_gc = (0x04<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ ++ XCL_TCSEL_PEC01_gc = (0x05<<4), /* Two 8-bit peripheral counters */ ++ XCL_TCSEL_BTC0PEC2_gc = (0x06<<4), /* One 8-bit timer/counter and two 4-bit peripheral counters */ ++} XCL_TCSEL_t; ++ ++/* Timer/Counter Mode */ ++typedef enum XCL_TCMODE_enum ++{ ++ XCL_TCMODE_NORMAL_gc = (0x00<<0), /* Normal mode with compare/period */ ++ XCL_TCMODE_CAPT_gc = (0x01<<0), /* Capture mode */ ++ XCL_TCMODE_PWM_gc = (0x02<<0), /* Single Slope PWM */ ++} XCL_TCMODE_t; ++ ++/* Compare Output Value Timer */ ++typedef enum XCL_CMPEN_enum ++{ ++ XCL_CMPEN_CLEAR_gc = (0x00<<5), /* Clear WG Output */ ++ XCL_CMPEN_SET_gc = (0x01<<5), /* Set WG Output */ ++} XCL_CMPEN_t; ++ ++/* Command Enable */ ++typedef enum XCL_CMDEN_enum ++{ ++ XCL_CMDEN_DISABLE_gc = (0x00<<6), /* Command Ignored */ ++ XCL_CMDEN_CMD0_gc = (0x01<<6), /* Command valid for timer/counter 0 */ ++ XCL_CMDEN_CMD1_gc = (0x02<<6), /* Command valid for timer/counter 1 */ ++ XCL_CMDEN_CMD01_gc = (0x03<<6), /* Command valid for both timer/counter 0 and 1 */ ++} XCL_CMDEN_t; ++ ++/* Timer/Counter Event Source Selection */ ++typedef enum XCL_EVSRC_enum ++{ ++ XCL_EVSRC_EVCH0_gc = (0x00<<0), /* Event channel 0 */ ++ XCL_EVSRC_EVCH1_gc = (0x01<<0), /* Event channel 1 */ ++ XCL_EVSRC_EVCH2_gc = (0x02<<0), /* Event channel 2 */ ++ XCL_EVSRC_EVCH3_gc = (0x03<<0), /* Event channel 3 */ ++ XCL_EVSRC_EVCH4_gc = (0x04<<0), /* Event channel 4 */ ++ XCL_EVSRC_EVCH5_gc = (0x05<<0), /* Event channel 5 */ ++ XCL_EVSRC_EVCH6_gc = (0x06<<0), /* Event channel 6 */ ++ XCL_EVSRC_EVCH7_gc = (0x07<<0), /* Event channel 7 */ ++} XCL_EVSRC_t; ++ ++/* Timer/Counter Event Action Selection */ ++typedef enum XCL_EVACT_enum ++{ ++ XCL_EVACT_INPUT_gc = (0x00<<5), /* Input Capture */ ++ XCL_EVACT_FREQ_gc = (0x01<<5), /* Frequency Capture */ ++ XCL_EVACT_PW_gc = (0x02<<5), /* Pulse Width Capture */ ++ XCL_EVACT_RESTART_gc = (0x03<<5), /* Restart timer/counter */ ++} XCL_EVACT_t; ++ ++/* Underflow Interrupt level */ ++typedef enum XCL_UNF_INTLVL_enum ++{ ++ XCL_UNF_INTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ XCL_UNF_INTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ XCL_UNF_INTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ XCL_UNF_INTLVL_HI_gc = (0x03<<2), /* High Level */ ++} XCL_UNF_INTLVL_t; ++ ++/* Compare/Capture Interrupt level */ ++typedef enum XCL_CC_INTLVL_enum ++{ ++ XCL_CC_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ XCL_CC_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ XCL_CC_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ XCL_CC_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} XCL_CC_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* */ ++typedef struct TWI_TIMEOUT_struct ++{ ++ register8_t TOS; /* Timeout Status Register */ ++ register8_t TOCONF; /* Timeout Configuration Register */ ++} TWI_TIMEOUT_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++ TWI_TIMEOUT_t TIMEOUT; /* TWI SMBUS timeout module */ ++} TWI_t; ++ ++/* SDA Hold Time */ ++typedef enum TWI_SDAHOLD_enum ++{ ++ TWI_SDAHOLD_OFF_gc = (0x00<<4), /* SDA Hold Time off */ ++ TWI_SDAHOLD_50NS_gc = (0x01<<4), /* SDA Hold Time 50 ns */ ++ TWI_SDAHOLD_300NS_gc = (0x02<<4), /* SDA Hold Time 300 ns */ ++ TWI_SDAHOLD_400NS_gc = (0x03<<4), /* SDA Hold Time 400 ns */ ++} TWI_SDAHOLD_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++/* Master Timeout */ ++typedef enum TWI_MASTER_TTIMEOUT_enum ++{ ++ TWI_MASTER_TTIMEOUT_25MS_gc = (0x00<<0), /* 25 Milliseconds */ ++ TWI_MASTER_TTIMEOUT_24MS_gc = (0x01<<0), /* 24 Milliseconds */ ++ TWI_MASTER_TTIMEOUT_23MS_gc = (0x02<<0), /* 23 Milliseconds */ ++ TWI_MASTER_TTIMEOUT_22MS_gc = (0x03<<0), /* 22 Milliseconds */ ++ TWI_MASTER_TTIMEOUT_26MS_gc = (0x04<<0), /* 26 Milliseconds */ ++ TWI_MASTER_TTIMEOUT_27MS_gc = (0x05<<0), /* 27 Milliseconds */ ++ TWI_MASTER_TTIMEOUT_28MS_gc = (0x06<<0), /* 28 Milliseconds */ ++ TWI_MASTER_TTIMEOUT_29MS_gc = (0x07<<0), /* 29 Milliseconds */ ++} TWI_MASTER_TTIMEOUT_t; ++ ++/* Slave Ttimeout */ ++typedef enum TWI_SLAVE_TTIMEOUT_enum ++{ ++ TWI_SLAVE_TTIMEOUT_25MS_gc = (0x00<<5), /* 25 Milliseconds */ ++ TWI_SLAVE_TTIMEOUT_24MS_gc = (0x01<<5), /* 24 Milliseconds */ ++ TWI_SLAVE_TTIMEOUT_23MS_gc = (0x02<<5), /* 23 Milliseconds */ ++ TWI_SLAVE_TTIMEOUT_22MS_gc = (0x03<<5), /* 22 Milliseconds */ ++ TWI_SLAVE_TTIMEOUT_26MS_gc = (0x04<<5), /* 26 Milliseconds */ ++ TWI_SLAVE_TTIMEOUT_27MS_gc = (0x05<<5), /* 27 Milliseconds */ ++ TWI_SLAVE_TTIMEOUT_28MS_gc = (0x06<<5), /* 28 Milliseconds */ ++ TWI_SLAVE_TTIMEOUT_29MS_gc = (0x07<<5), /* 29 Milliseconds */ ++} TWI_SLAVE_TTIMEOUT_t; ++ ++/* Master/Slave Extend Timeout */ ++typedef enum TWI_MASTER_TMSEXT_enum ++{ ++ TWI_MASTER_TMSEXT_10MS25MS_gc = (0x00<<3), /* Tmext 10ms Tsext 25ms */ ++ TWI_MASTER_TMSEXT_9MS24MS_gc = (0x01<<3), /* Tmext 9ms Tsext 24ms */ ++ TWI_MASTER_TMSEXT_11MS26MS_gc = (0x02<<3), /* Tmext 11ms Tsext 26ms */ ++ TWI_MASTER_TMSEXT_12MS27MS_gc = (0x03<<3), /* Tmext 12ms Tsext 27ms */ ++} TWI_MASTER_TMSEXT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTMASK; /* Port Interrupt Mask */ ++ register8_t reserved_0x0B; ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt Level */ ++typedef enum PORT_INTLVL_enum ++{ ++ PORT_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INTLVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_FORCE_ENABLE_gc = (0x06<<0), /* Digital Input Buffer Forced Enable */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 4 */ ++typedef struct TC4_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t CTRLF; /* Control Register F */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t CTRLHCLR; /* Control Register H Clear */ ++ register8_t CTRLHSET; /* Control Register H Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC4_t; ++ ++ ++/* 16-bit Timer/Counter 5 */ ++typedef struct TC5_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t CTRLF; /* Control Register F */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t CTRLHCLR; /* Control Register H Clear */ ++ register8_t CTRLHSET; /* Control Register H Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++} TC5_t; ++ ++/* Clock Selection */ ++typedef enum TC45_CLKSEL_enum ++{ ++ TC45_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC45_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC45_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC45_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC45_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC45_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC45_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC45_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC45_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC45_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC45_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC45_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC45_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC45_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC45_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC45_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC45_CLKSEL_t; ++ ++/* Byte Mode */ ++typedef enum TC45_BYTEM_enum ++{ ++ TC45_BYTEM_NORMAL_gc = (0x00<<6), /* 16-bit mode */ ++ TC45_BYTEM_BYTEMODE_gc = (0x01<<6), /* Timer/Counter Operating in Byte Mode Only */ ++} TC45_BYTEM_t; ++ ++/* Circular Enable Mode */ ++typedef enum TC45_CIRCEN_enum ++{ ++ TC45_CIRCEN_DISABLE_gc = (0x00<<4), /* Circular Buffer Disabled */ ++ TC45_CIRCEN_PER_gc = (0x01<<4), /* Circular Buffer Enabled on PER/PERBUF */ ++ TC45_CIRCEN_CCA_gc = (0x02<<4), /* Circular Buffer Enabled on CCA/CCABUF */ ++ TC45_CIRCEN_BOTH_gc = (0x03<<4), /* Circular Buffer Enabled on All Buffered Registers */ ++} TC45_CIRCEN_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC45_WGMODE_enum ++{ ++ TC45_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC45_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC45_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC45_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC45_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Both */ ++ TC45_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC45_WGMODE_t; ++ ++/* Event Action */ ++typedef enum TC45_EVACT_enum ++{ ++ TC45_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC45_EVACT_FMODE1_gc = (0x01<<5), /* Fault Mode 1 capture */ ++ TC45_EVACT_FMODE2_gc = (0x02<<5), /* Fault Mode 2 capture */ ++ TC45_EVACT_UPDOWN_gc = (0x03<<5), /* Up/down count */ ++ TC45_EVACT_QDEC_gc = (0x04<<5), /* Quadrature decode */ ++ TC45_EVACT_RESTART_gc = (0x05<<5), /* Restart */ ++ TC45_EVACT_PWF_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC45_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC45_EVSEL_enum ++{ ++ TC45_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC45_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC45_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC45_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC45_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC45_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC45_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC45_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC45_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC45_EVSEL_t; ++ ++/* Compare or Capture Channel A Mode */ ++typedef enum TC45_CCAMODE_enum ++{ ++ TC45_CCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ ++ TC45_CCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ ++ TC45_CCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ ++ TC45_CCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ ++} TC45_CCAMODE_t; ++ ++/* Compare or Capture Channel B Mode */ ++typedef enum TC45_CCBMODE_enum ++{ ++ TC45_CCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ ++ TC45_CCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ ++ TC45_CCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ ++ TC45_CCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ ++} TC45_CCBMODE_t; ++ ++/* Compare or Capture Channel C Mode */ ++typedef enum TC45_CCCMODE_enum ++{ ++ TC45_CCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ ++ TC45_CCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ ++ TC45_CCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ ++ TC45_CCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ ++} TC45_CCCMODE_t; ++ ++/* Compare or Capture Channel D Mode */ ++typedef enum TC45_CCDMODE_enum ++{ ++ TC45_CCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ ++ TC45_CCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ ++ TC45_CCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ ++ TC45_CCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ ++} TC45_CCDMODE_t; ++ ++/* Compare or Capture Low Channel A Mode */ ++typedef enum TC45_LCCAMODE_enum ++{ ++ TC45_LCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ ++ TC45_LCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ ++ TC45_LCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ ++ TC45_LCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ ++} TC45_LCCAMODE_t; ++ ++/* Compare or Capture Low Channel B Mode */ ++typedef enum TC45_LCCBMODE_enum ++{ ++ TC45_LCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ ++ TC45_LCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ ++ TC45_LCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ ++ TC45_LCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ ++} TC45_LCCBMODE_t; ++ ++/* Compare or Capture Low Channel C Mode */ ++typedef enum TC45_LCCCMODE_enum ++{ ++ TC45_LCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ ++ TC45_LCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ ++ TC45_LCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ ++ TC45_LCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ ++} TC45_LCCCMODE_t; ++ ++/* Compare or Capture Low Channel D Mode */ ++typedef enum TC45_LCCDMODE_enum ++{ ++ TC45_LCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ ++ TC45_LCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ ++ TC45_LCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ ++ TC45_LCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ ++} TC45_LCCDMODE_t; ++ ++/* Compare or Capture High Channel A Mode */ ++typedef enum TC45_HCCAMODE_enum ++{ ++ TC45_HCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ ++ TC45_HCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ ++ TC45_HCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ ++ TC45_HCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ ++} TC45_HCCAMODE_t; ++ ++/* Compare or Capture High Channel B Mode */ ++typedef enum TC45_HCCBMODE_enum ++{ ++ TC45_HCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ ++ TC45_HCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ ++ TC45_HCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ ++ TC45_HCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ ++} TC45_HCCBMODE_t; ++ ++/* Compare or Capture High Channel C Mode */ ++typedef enum TC45_HCCCMODE_enum ++{ ++ TC45_HCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ ++ TC45_HCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ ++ TC45_HCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ ++ TC45_HCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ ++} TC45_HCCCMODE_t; ++ ++/* Compare or Capture High Channel D Mode */ ++typedef enum TC45_HCCDMODE_enum ++{ ++ TC45_HCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ ++ TC45_HCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ ++ TC45_HCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ ++ TC45_HCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ ++} TC45_HCCDMODE_t; ++ ++/* Timer Trigger Restart Interrupt Level */ ++typedef enum TC45_TRGINTLVL_enum ++{ ++ TC45_TRGINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC45_TRGINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC45_TRGINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC45_TRGINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC45_TRGINTLVL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC45_ERRINTLVL_enum ++{ ++ TC45_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC45_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC45_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC45_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC45_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC45_OVFINTLVL_enum ++{ ++ TC45_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC45_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC45_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC45_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC45_OVFINTLVL_t; ++ ++/* Compare or Capture Channel A Interrupt Level */ ++typedef enum TC45_CCAINTLVL_enum ++{ ++ TC45_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC45_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC45_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC45_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC45_CCAINTLVL_t; ++ ++/* Compare or Capture Channel B Interrupt Level */ ++typedef enum TC45_CCBINTLVL_enum ++{ ++ TC45_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC45_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC45_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC45_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC45_CCBINTLVL_t; ++ ++/* Compare or Capture Channel C Interrupt Level */ ++typedef enum TC45_CCCINTLVL_enum ++{ ++ TC45_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC45_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC45_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC45_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC45_CCCINTLVL_t; ++ ++/* Compare or Capture Channel D Interrupt Level */ ++typedef enum TC45_CCDINTLVL_enum ++{ ++ TC45_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC45_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC45_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC45_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC45_CCDINTLVL_t; ++ ++/* Compare or Capture Low Channel A Interrupt Level */ ++typedef enum TC45_LCCAINTLVL_enum ++{ ++ TC45_LCCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC45_LCCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC45_LCCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC45_LCCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC45_LCCAINTLVL_t; ++ ++/* Compare or Capture Low Channel B Interrupt Level */ ++typedef enum TC45_LCCBINTLVL_enum ++{ ++ TC45_LCCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC45_LCCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC45_LCCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC45_LCCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC45_LCCBINTLVL_t; ++ ++/* Compare or Capture Low Channel C Interrupt Level */ ++typedef enum TC45_LCCCINTLVL_enum ++{ ++ TC45_LCCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC45_LCCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC45_LCCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC45_LCCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC45_LCCCINTLVL_t; ++ ++/* Compare or Capture Low Channel D Interrupt Level */ ++typedef enum TC45_LCCDINTLVL_enum ++{ ++ TC45_LCCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC45_LCCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC45_LCCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC45_LCCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC45_LCCDINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC45_CMD_enum ++{ ++ TC45_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC45_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC45_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC45_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC45_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FAULT - Fault Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fault Extension */ ++typedef struct FAULT_struct ++{ ++ register8_t CTRLA; /* Control A Register */ ++ register8_t CTRLB; /* Control B Register */ ++ register8_t CTRLC; /* Control C Register */ ++ register8_t CTRLD; /* Control D Register */ ++ register8_t CTRLE; /* Control E Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G set */ ++} FAULT_t; ++ ++/* Ramp Mode Selection */ ++typedef enum FAULT_RAMP_enum ++{ ++ FAULT_RAMP_RAMP1_gc = (0x00<<6), /* Normal Mode */ ++ FAULT_RAMP_RAMP2_gc = (0x02<<6), /* RAMP2 Mode */ ++} FAULT_RAMP_t; ++ ++/* Fault E Input Source Selection */ ++typedef enum FAULT_SRCE_enum ++{ ++ FAULT_SRCE_DISABLE_gc = (0x00<<0), /* Fault Protection Disabled */ ++ FAULT_SRCE_CHN_gc = (0x01<<0), /* Event Channel n */ ++ FAULT_SRCE_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ ++ FAULT_SRCE_CHN2_gc = (0x03<<0), /* Event Channel n+2 */ ++} FAULT_SRCE_t; ++ ++/* Fault A Halt Action Selection */ ++typedef enum FAULT_HALTA_enum ++{ ++ FAULT_HALTA_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ ++ FAULT_HALTA_HW_gc = (0x01<<5), /* Hardware Halt Action */ ++ FAULT_HALTA_SW_gc = (0x02<<5), /* Software Halt Action */ ++} FAULT_HALTA_t; ++ ++/* Fault A Source Selection */ ++typedef enum FAULT_SRCA_enum ++{ ++ FAULT_SRCA_DISABLE_gc = (0x00<<0), /* Fault A Disabled */ ++ FAULT_SRCA_CHN_gc = (0x01<<0), /* Event Channel n */ ++ FAULT_SRCA_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ ++ FAULT_SRCA_LINK_gc = (0x03<<0), /* Fault A linked to Fault B State from previous cycle */ ++} FAULT_SRCA_t; ++ ++/* Fault B Halt Action Selection */ ++typedef enum FAULT_HALTB_enum ++{ ++ FAULT_HALTB_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ ++ FAULT_HALTB_HW_gc = (0x01<<5), /* Hardware Halt Action */ ++ FAULT_HALTB_SW_gc = (0x02<<5), /* Software Halt Action */ ++} FAULT_HALTB_t; ++ ++/* Fault B Source Selection */ ++typedef enum FAULT_SRCB_enum ++{ ++ FAULT_SRCB_DISABLE_gc = (0x00<<0), /* Fault B disabled */ ++ FAULT_SRCB_CHN_gc = (0x01<<0), /* Event Channel n */ ++ FAULT_SRCB_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ ++ FAULT_SRCB_LINK_gc = (0x03<<0), /* Fault B linked to Fault A State from previous cycle */ ++} FAULT_SRCB_t; ++ ++/* Channel index Command */ ++typedef enum FAULT_IDXCMD_enum ++{ ++ FAULT_IDXCMD_DISABLE_gc = (0x00<<3), /* Command Disabled */ ++ FAULT_IDXCMD_SET_gc = (0x01<<3), /* Force Cycle B in Next Cycle */ ++ FAULT_IDXCMD_CLEAR_gc = (0x02<<3), /* Force Cycle A in Next Cycle */ ++ FAULT_IDXCMD_HOLD_gc = (0x03<<3), /* Hold Current Cycle Index in Next Cycle */ ++} FAULT_IDXCMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WEX - Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Waveform Extension */ ++typedef struct WEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t DTBOTH; /* Dead-time Concurrent Write to Both Sides Register */ ++ register8_t DTLS; /* Dead-time Low Side Register */ ++ register8_t DTHS; /* Dead-time High Side Register */ ++ register8_t STATUSCLR; /* Status Clear Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t SWAP; /* Swap Register */ ++ register8_t PGO; /* Pattern Generation Override Register */ ++ register8_t PGV; /* Pattern Generation Value Register */ ++ register8_t reserved_0x09; ++ register8_t SWAPBUF; /* Dead Time Low Side Buffer */ ++ register8_t PGOBUF; /* Pattern Generation Overwrite Buffer Register */ ++ register8_t PGVBUF; /* Pattern Generation Value Buffer Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t OUTOVDIS; /* Output Override Disable Register */ ++} WEX_t; ++ ++/* Output Matrix Mode */ ++typedef enum WEX_OTMX_enum ++{ ++ WEX_OTMX_DEFAULT_gc = (0x00<<4), /* Default Ouput Matrix Mode */ ++ WEX_OTMX_FIRST_gc = (0x01<<4), /* First Output matrix Mode */ ++ WEX_OTMX_SECOND_gc = (0x02<<4), /* Second Output matrix Mode */ ++ WEX_OTMX_THIRD_gc = (0x03<<4), /* Third Output matrix Mode */ ++ WEX_OTMX_FOURTH_gc = (0x04<<4), /* Fourth Output matrix Mode */ ++} WEX_OTMX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++} HIRES_t; ++ ++/* High Resolution Plus Mode */ ++typedef enum HIRES_HRPLUS_enum ++{ ++ HIRES_HRPLUS_NONE_gc = (0x00<<2), /* No Hi-Res Plus */ ++ HIRES_HRPLUS_HRP4_gc = (0x01<<2), /* Hi-Res Plus enabled on Timer 4 */ ++ HIRES_HRPLUS_HRP5_gc = (0x02<<2), /* Hi-Res Plus enabled on Timer 5 */ ++ HIRES_HRPLUS_BOTH_gc = (0x03<<2), /* Hi-Res Plus enabled on Timer 4 and 5 */ ++} HIRES_HRPLUS_t; ++ ++/* High Resolution Mode */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Hi-Res */ ++ HIRES_HREN_HRP4_gc = (0x01<<0), /* Hi-Res enabled on Timer 4 */ ++ HIRES_HREN_HRP5_gc = (0x02<<0), /* Hi-Res enabled on Timer 5 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Hi-Res enabled on Timer 4 and 5 */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Start Interrupt level */ ++typedef enum USART_RXSINTLVL_enum ++{ ++ USART_RXSINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_RXSINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_RXSINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_RXSINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_RXSINTLVL_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++/* Encoding and Decoding Type */ ++typedef enum USART_DECTYPE_enum ++{ ++ USART_DECTYPE_DATA_gc = (0x00<<4), /* DATA Field Encoding */ ++ USART_DECTYPE_SDATA_gc = (0x02<<4), /* Start and Data Fields Encoding */ ++ USART_DECTYPE_NOTSDATA_gc = (0x03<<4), /* Start and Data Fields Encoding, with invertion in START field */ ++} USART_DECTYPE_t; ++ ++/* XCL LUT Action */ ++typedef enum USART_LUTACT_enum ++{ ++ USART_LUTACT_OFF_gc = (0x00<<2), /* Standard Frame Configuration */ ++ USART_LUTACT_RX_gc = (0x01<<2), /* Receiver Decoding Enabled */ ++ USART_LUTACT_TX_gc = (0x02<<2), /* Transmitter Encoding Enabled */ ++ USART_LUTACT_BOTH_gc = (0x03<<2), /* Both Encoding and Decoding Enabled */ ++} USART_LUTACT_t; ++ ++/* XCL Peripheral Counter Action */ ++typedef enum USART_PECACT_enum ++{ ++ USART_PECACT_OFF_gc = (0x00<<0), /* Standard Mode */ ++ USART_PECACT_PEC0_gc = (0x01<<0), /* Variable Data Lenght in Reception */ ++ USART_PECACT_PEC1_gc = (0x02<<0), /* Variable Data Lenght in Transmission */ ++ USART_PECACT_PERC01_gc = (0x03<<0), /* Variable Data Lenght in both Reception and Transmission */ ++} USART_PECACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface with Buffer Modes */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t CTRLB; /* Control Register B */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0, base clock at "0", sampling on leading edge (rising) & set-up on trailling edge (falling). */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1, base clock at "0", set-up on leading edge (rising) & sampling on trailling edge (falling). */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2, base clock at "1", sampling on leading edge (falling) & set-up on trailling edge (rising). */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3, base clock at "1", set-up on leading edge (falling) & sampling on trailling edge (rising). */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* If CLK2X=1 CLKper/2, else (CLK2X=0) CLKper/4. */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* If CLK2X=1 CLKper/8, else (CLK2X=0) CLKper/16. */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* If CLK2X=1 CLKper/32, else (CLK2X=0) CLKper/64. */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* If CLK2X=1 CLKper/64, else (CLK2X=0) CLKper/128. */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++/* Buffer Modes */ ++typedef enum SPI_BUFMODE_enum ++{ ++ SPI_BUFMODE_OFF_gc = (0x00<<6), /* SPI Unbuffered Mode */ ++ SPI_BUFMODE_BUFMODE1_gc = (0x02<<6), /* Buffer Mode 1 (with dummy byte) */ ++ SPI_BUFMODE_BUFMODE2_gc = (0x03<<6), /* Buffer Mode 2 (no dummy byte) */ ++} SPI_BUFMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t reserved_0x00; ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++ register8_t FUSEBYTE6; /* Fault State */ ++} NVM_FUSES_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BOD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC8M; /* RCOSC 8MHz Calibration Value */ ++ register8_t reserved_0x01; ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t ROOMTEMP; /* Temperature corresponds to TEMPSENSE3/2 */ ++ register8_t HOTTEMP; /* Temperature corresponds to TEMPSENSE1/0 */ ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t ACACURRCAL; /* ACA Current Calibration Byte */ ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t TEMPSENSE2; /* Temperature Sensor Calibration Byte 2 */ ++ register8_t TEMPSENSE3; /* Temperature Sensor Calibration Byte 3 */ ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ ++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ ++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define EDMA (*(EDMA_t *) 0x0100) /* Enhanced DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define XCL (*(XCL_t *) 0x0460) /* XMEGA Custom Logic */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC4 (*(TC4_t *) 0x0800) /* 16-bit Timer/Counter 4 */ ++#define TCC5 (*(TC5_t *) 0x0840) /* 16-bit Timer/Counter 5 */ ++#define FAULTC4 (*(FAULT_t *) 0x0880) /* Fault Extension */ ++#define FAULTC5 (*(FAULT_t *) 0x0890) /* Fault Extension */ ++#define WEXC (*(WEX_t *) 0x08A0) /* Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x08B0) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08E0) /* Serial Peripheral Interface with Buffer Modes */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD5 (*(TC5_t *) 0x0940) /* 16-bit Timer/Counter 5 */ ++#define USARTD0 (*(USART_t *) 0x09C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++#define FUSE_FUSEBYTE6 _SFR_MEM8(0x0006) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC8M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_ROOMTEMP _SFR_MEM8(0x001E) ++#define PRODSIGNATURES_HOTTEMP _SFR_MEM8(0x001F) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_ACACURRCAL _SFR_MEM8(0x0028) ++#define PRODSIGNATURES_TEMPSENSE2 _SFR_MEM8(0x002C) ++#define PRODSIGNATURES_TEMPSENSE3 _SFR_MEM8(0x002D) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) ++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) ++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) ++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++#define OSC_RC8MCAL _SFR_MEM8(0x0057) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_WEXLOCK _SFR_MEM8(0x0099) ++#define MCU_FAULTLOCK _SFR_MEM8(0x009A) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_CLKOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_ACEVOUT _SFR_MEM8(0x00B6) ++#define PORTCFG_SRLCTRL _SFR_MEM8(0x00B7) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* EDMA - Enhanced DMA Controller */ ++#define EDMA_CTRL _SFR_MEM8(0x0100) ++#define EDMA_INTFLAGS _SFR_MEM8(0x0103) ++#define EDMA_STATUS _SFR_MEM8(0x0104) ++#define EDMA_TEMP _SFR_MEM8(0x0106) ++#define EDMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define EDMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define EDMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define EDMA_CH0_DESTADDRCTRL _SFR_MEM8(0x0113) ++#define EDMA_CH0_TRIGSRC _SFR_MEM8(0x0114) ++#define EDMA_CH0_TRFCNT _SFR_MEM16(0x0116) ++#define EDMA_CH0_ADDR _SFR_MEM16(0x0118) ++#define EDMA_CH0_DESTADDR _SFR_MEM16(0x011C) ++#define EDMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define EDMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define EDMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define EDMA_CH1_DESTADDRCTRL _SFR_MEM8(0x0123) ++#define EDMA_CH1_TRIGSRC _SFR_MEM8(0x0124) ++#define EDMA_CH1_TRFCNT _SFR_MEM16(0x0126) ++#define EDMA_CH1_ADDR _SFR_MEM16(0x0128) ++#define EDMA_CH1_DESTADDR _SFR_MEM16(0x012C) ++#define EDMA_CH2_CTRLA _SFR_MEM8(0x0130) ++#define EDMA_CH2_CTRLB _SFR_MEM8(0x0131) ++#define EDMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) ++#define EDMA_CH2_DESTADDRCTRL _SFR_MEM8(0x0133) ++#define EDMA_CH2_TRIGSRC _SFR_MEM8(0x0134) ++#define EDMA_CH2_TRFCNT _SFR_MEM16(0x0136) ++#define EDMA_CH2_ADDR _SFR_MEM16(0x0138) ++#define EDMA_CH2_DESTADDR _SFR_MEM16(0x013C) ++#define EDMA_CH3_CTRLA _SFR_MEM8(0x0140) ++#define EDMA_CH3_CTRLB _SFR_MEM8(0x0141) ++#define EDMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) ++#define EDMA_CH3_DESTADDRCTRL _SFR_MEM8(0x0143) ++#define EDMA_CH3_TRIGSRC _SFR_MEM8(0x0144) ++#define EDMA_CH3_TRFCNT _SFR_MEM16(0x0146) ++#define EDMA_CH3_ADDR _SFR_MEM16(0x0148) ++#define EDMA_CH3_DESTADDR _SFR_MEM16(0x014C) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH4MUX _SFR_MEM8(0x0184) ++#define EVSYS_CH5MUX _SFR_MEM8(0x0185) ++#define EVSYS_CH6MUX _SFR_MEM8(0x0186) ++#define EVSYS_CH7MUX _SFR_MEM8(0x0187) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) ++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) ++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) ++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++#define EVSYS_DFCTRL _SFR_MEM8(0x0192) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++#define ADCA_CH0_CORRCTRL _SFR_MEM8(0x0227) ++#define ADCA_CH0_OFFSETCORR0 _SFR_MEM8(0x0228) ++#define ADCA_CH0_OFFSETCORR1 _SFR_MEM8(0x0229) ++#define ADCA_CH0_GAINCORR0 _SFR_MEM8(0x022A) ++#define ADCA_CH0_GAINCORR1 _SFR_MEM8(0x022B) ++#define ADCA_CH0_AVGCTRL _SFR_MEM8(0x022C) ++ ++/* DAC - Digital-to-Analog Converter */ ++#define DACA_CTRLA _SFR_MEM8(0x0300) ++#define DACA_CTRLB _SFR_MEM8(0x0301) ++#define DACA_CTRLC _SFR_MEM8(0x0302) ++#define DACA_EVCTRL _SFR_MEM8(0x0303) ++#define DACA_STATUS _SFR_MEM8(0x0305) ++#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) ++#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) ++#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) ++#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) ++#define DACA_CH0DATA _SFR_MEM16(0x0318) ++#define DACA_CH1DATA _SFR_MEM16(0x031A) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++#define ACA_CURRCTRL _SFR_MEM8(0x0388) ++#define ACA_CURRCALIB _SFR_MEM8(0x0389) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CALIB _SFR_MEM8(0x0406) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* XCL - XMEGA Custom Logic */ ++#define XCL_CTRLA _SFR_MEM8(0x0460) ++#define XCL_CTRLB _SFR_MEM8(0x0461) ++#define XCL_CTRLC _SFR_MEM8(0x0462) ++#define XCL_CTRLD _SFR_MEM8(0x0463) ++#define XCL_CTRLE _SFR_MEM8(0x0464) ++#define XCL_CTRLF _SFR_MEM8(0x0465) ++#define XCL_CTRLG _SFR_MEM8(0x0466) ++#define XCL_INTCTRL _SFR_MEM8(0x0467) ++#define XCL_INTFLAGS _SFR_MEM8(0x0468) ++#define XCL_PLC _SFR_MEM8(0x0469) ++#define XCL_CNTL _SFR_MEM8(0x046A) ++#define XCL_CNTH _SFR_MEM8(0x046B) ++#define XCL_CMPL _SFR_MEM8(0x046C) ++#define XCL_CMPH _SFR_MEM8(0x046D) ++#define XCL_PERCAPTL _SFR_MEM8(0x046E) ++#define XCL_PERCAPTH _SFR_MEM8(0x046F) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++#define TWIC_TIMEOUT_TOS _SFR_MEM8(0x048E) ++#define TWIC_TIMEOUT_TOCONF _SFR_MEM8(0x048F) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INTMASK _SFR_MEM8(0x060A) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_REMAP _SFR_MEM8(0x060E) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INTMASK _SFR_MEM8(0x064A) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INTMASK _SFR_MEM8(0x066A) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INTMASK _SFR_MEM8(0x07EA) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC4 - 16-bit Timer/Counter 4 */ ++#define TCC4_CTRLA _SFR_MEM8(0x0800) ++#define TCC4_CTRLB _SFR_MEM8(0x0801) ++#define TCC4_CTRLC _SFR_MEM8(0x0802) ++#define TCC4_CTRLD _SFR_MEM8(0x0803) ++#define TCC4_CTRLE _SFR_MEM8(0x0804) ++#define TCC4_CTRLF _SFR_MEM8(0x0805) ++#define TCC4_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC4_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC4_CTRLGCLR _SFR_MEM8(0x0808) ++#define TCC4_CTRLGSET _SFR_MEM8(0x0809) ++#define TCC4_CTRLHCLR _SFR_MEM8(0x080A) ++#define TCC4_CTRLHSET _SFR_MEM8(0x080B) ++#define TCC4_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC4_TEMP _SFR_MEM8(0x080F) ++#define TCC4_CNT _SFR_MEM16(0x0820) ++#define TCC4_PER _SFR_MEM16(0x0826) ++#define TCC4_CCA _SFR_MEM16(0x0828) ++#define TCC4_CCB _SFR_MEM16(0x082A) ++#define TCC4_CCC _SFR_MEM16(0x082C) ++#define TCC4_CCD _SFR_MEM16(0x082E) ++#define TCC4_PERBUF _SFR_MEM16(0x0836) ++#define TCC4_CCABUF _SFR_MEM16(0x0838) ++#define TCC4_CCBBUF _SFR_MEM16(0x083A) ++#define TCC4_CCCBUF _SFR_MEM16(0x083C) ++#define TCC4_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC5 - 16-bit Timer/Counter 5 */ ++#define TCC5_CTRLA _SFR_MEM8(0x0840) ++#define TCC5_CTRLB _SFR_MEM8(0x0841) ++#define TCC5_CTRLC _SFR_MEM8(0x0842) ++#define TCC5_CTRLD _SFR_MEM8(0x0843) ++#define TCC5_CTRLE _SFR_MEM8(0x0844) ++#define TCC5_CTRLF _SFR_MEM8(0x0845) ++#define TCC5_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC5_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC5_CTRLGCLR _SFR_MEM8(0x0848) ++#define TCC5_CTRLGSET _SFR_MEM8(0x0849) ++#define TCC5_CTRLHCLR _SFR_MEM8(0x084A) ++#define TCC5_CTRLHSET _SFR_MEM8(0x084B) ++#define TCC5_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC5_TEMP _SFR_MEM8(0x084F) ++#define TCC5_CNT _SFR_MEM16(0x0860) ++#define TCC5_PER _SFR_MEM16(0x0866) ++#define TCC5_CCA _SFR_MEM16(0x0868) ++#define TCC5_CCB _SFR_MEM16(0x086A) ++#define TCC5_PERBUF _SFR_MEM16(0x0876) ++#define TCC5_CCABUF _SFR_MEM16(0x0878) ++#define TCC5_CCBBUF _SFR_MEM16(0x087A) ++ ++/* FAULT - Fault Extension */ ++#define FAULTC4_CTRLA _SFR_MEM8(0x0880) ++#define FAULTC4_CTRLB _SFR_MEM8(0x0881) ++#define FAULTC4_CTRLC _SFR_MEM8(0x0882) ++#define FAULTC4_CTRLD _SFR_MEM8(0x0883) ++#define FAULTC4_CTRLE _SFR_MEM8(0x0884) ++#define FAULTC4_STATUS _SFR_MEM8(0x0885) ++#define FAULTC4_CTRLGCLR _SFR_MEM8(0x0886) ++#define FAULTC4_CTRLGSET _SFR_MEM8(0x0887) ++ ++/* FAULT - Fault Extension */ ++#define FAULTC5_CTRLA _SFR_MEM8(0x0890) ++#define FAULTC5_CTRLB _SFR_MEM8(0x0891) ++#define FAULTC5_CTRLC _SFR_MEM8(0x0892) ++#define FAULTC5_CTRLD _SFR_MEM8(0x0893) ++#define FAULTC5_CTRLE _SFR_MEM8(0x0894) ++#define FAULTC5_STATUS _SFR_MEM8(0x0895) ++#define FAULTC5_CTRLGCLR _SFR_MEM8(0x0896) ++#define FAULTC5_CTRLGSET _SFR_MEM8(0x0897) ++ ++/* WEX - Waveform Extension */ ++#define WEXC_CTRL _SFR_MEM8(0x08A0) ++#define WEXC_DTBOTH _SFR_MEM8(0x08A1) ++#define WEXC_DTLS _SFR_MEM8(0x08A2) ++#define WEXC_DTHS _SFR_MEM8(0x08A3) ++#define WEXC_STATUSCLR _SFR_MEM8(0x08A4) ++#define WEXC_STATUSSET _SFR_MEM8(0x08A5) ++#define WEXC_SWAP _SFR_MEM8(0x08A6) ++#define WEXC_PGO _SFR_MEM8(0x08A7) ++#define WEXC_PGV _SFR_MEM8(0x08A8) ++#define WEXC_SWAPBUF _SFR_MEM8(0x08AA) ++#define WEXC_PGOBUF _SFR_MEM8(0x08AB) ++#define WEXC_PGVBUF _SFR_MEM8(0x08AC) ++#define WEXC_OUTOVDIS _SFR_MEM8(0x08AF) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x08B0) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08C0) ++#define USARTC0_STATUS _SFR_MEM8(0x08C1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08C2) ++#define USARTC0_CTRLB _SFR_MEM8(0x08C3) ++#define USARTC0_CTRLC _SFR_MEM8(0x08C4) ++#define USARTC0_CTRLD _SFR_MEM8(0x08C5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08C6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08C7) ++ ++/* SPI - Serial Peripheral Interface with Buffer Modes */ ++#define SPIC_CTRL _SFR_MEM8(0x08E0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08E1) ++#define SPIC_STATUS _SFR_MEM8(0x08E2) ++#define SPIC_DATA _SFR_MEM8(0x08E3) ++#define SPIC_CTRLB _SFR_MEM8(0x08E4) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC5 - 16-bit Timer/Counter 5 */ ++#define TCD5_CTRLA _SFR_MEM8(0x0940) ++#define TCD5_CTRLB _SFR_MEM8(0x0941) ++#define TCD5_CTRLC _SFR_MEM8(0x0942) ++#define TCD5_CTRLD _SFR_MEM8(0x0943) ++#define TCD5_CTRLE _SFR_MEM8(0x0944) ++#define TCD5_CTRLF _SFR_MEM8(0x0945) ++#define TCD5_INTCTRLA _SFR_MEM8(0x0946) ++#define TCD5_INTCTRLB _SFR_MEM8(0x0947) ++#define TCD5_CTRLGCLR _SFR_MEM8(0x0948) ++#define TCD5_CTRLGSET _SFR_MEM8(0x0949) ++#define TCD5_CTRLHCLR _SFR_MEM8(0x094A) ++#define TCD5_CTRLHSET _SFR_MEM8(0x094B) ++#define TCD5_INTFLAGS _SFR_MEM8(0x094C) ++#define TCD5_TEMP _SFR_MEM8(0x094F) ++#define TCD5_CNT _SFR_MEM16(0x0960) ++#define TCD5_PER _SFR_MEM16(0x0966) ++#define TCD5_CCA _SFR_MEM16(0x0968) ++#define TCD5_CCB _SFR_MEM16(0x096A) ++#define TCD5_PERBUF _SFR_MEM16(0x0976) ++#define TCD5_CCABUF _SFR_MEM16(0x0978) ++#define TCD5_CCBBUF _SFR_MEM16(0x097A) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD0_DATA _SFR_MEM8(0x09C0) ++#define USARTD0_STATUS _SFR_MEM8(0x09C1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09C2) ++#define USARTD0_CTRLB _SFR_MEM8(0x09C3) ++#define USARTD0_CTRLC _SFR_MEM8(0x09C4) ++#define USARTD0_CTRLD _SFR_MEM8(0x09C5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09C6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09C7) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT7IF_bm 0x80 /* Interrupt Pin 7 Flag bit mask. */ ++#define VPORT_INT7IF_bp 7 /* Interrupt Pin 7 Flag bit position. */ ++ ++#define VPORT_INT6IF_bm 0x40 /* Interrupt Pin 6 Flag bit mask. */ ++#define VPORT_INT6IF_bp 6 /* Interrupt Pin 6 Flag bit position. */ ++ ++#define VPORT_INT5IF_bm 0x20 /* Interrupt Pin 5 Flag bit mask. */ ++#define VPORT_INT5IF_bp 5 /* Interrupt Pin 5 Flag bit position. */ ++ ++#define VPORT_INT4IF_bm 0x10 /* Interrupt Pin 4 Flag bit mask. */ ++#define VPORT_INT4IF_bp 4 /* Interrupt Pin 4 Flag bit position. */ ++ ++#define VPORT_INT3IF_bm 0x08 /* Interrupt Pin 3 Flag bit mask. */ ++#define VPORT_INT3IF_bp 3 /* Interrupt Pin 3 Flag bit position. */ ++ ++#define VPORT_INT2IF_bm 0x04 /* Interrupt Pin 2 Flag bit mask. */ ++#define VPORT_INT2IF_bp 2 /* Interrupt Pin 2 Flag bit position. */ ++ ++#define VPORT_INT1IF_bm 0x02 /* Interrupt Pin 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Interrupt Pin 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Interrupt Pin 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Interrupt Pin 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_XCL_bm 0x80 /* XMEGA Custom Logic bit mask. */ ++#define PR_XCL_bp 7 /* XMEGA Custom Logic bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_EDMA_bm 0x01 /* Enhanced DMA-Controller bit mask. */ ++#define PR_EDMA_bp 0 /* Enhanced DMA-Controller bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ ++#define PR_DAC_bp 2 /* Port A DAC bit position. */ ++ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C WEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C WEX bit position. */ ++ ++#define PR_TC5_bm 0x02 /* Port C Timer/Counter5 bit mask. */ ++#define PR_TC5_bp 1 /* Port C Timer/Counter5 bit position. */ ++ ++#define PR_TC4_bm 0x01 /* Port C Timer/Counter4 bit mask. */ ++#define PR_TC4_bp 0 /* Port C Timer/Counter4 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC5 Predefined. */ ++/* PR_TC5 Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_RC8MLPM_bm 0x40 /* Internal 8 MHz RC Low Power Mode Enable bit mask. */ ++#define OSC_RC8MLPM_bp 6 /* Internal 8 MHz RC Low Power Mode Enable bit position. */ ++ ++#define OSC_RC8MEN_bm 0x20 /* Internal 8 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC8MEN_bp 5 /* Internal 8 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_RC8MRDY_bm 0x20 /* Internal 8 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC8MRDY_bp 5 /* Internal 8 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ ++#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++/* OSC.RC8MCAL bit masks and bit positions */ ++#define OSC_RC8MCAL_gm 0xFF /* Calibration Bits group mask. */ ++#define OSC_RC8MCAL_gp 0 /* Calibration Bits group position. */ ++#define OSC_RC8MCAL0_bm (1<<0) /* Calibration Bits bit 0 mask. */ ++#define OSC_RC8MCAL0_bp 0 /* Calibration Bits bit 0 position. */ ++#define OSC_RC8MCAL1_bm (1<<1) /* Calibration Bits bit 1 mask. */ ++#define OSC_RC8MCAL1_bp 1 /* Calibration Bits bit 1 position. */ ++#define OSC_RC8MCAL2_bm (1<<2) /* Calibration Bits bit 2 mask. */ ++#define OSC_RC8MCAL2_bp 2 /* Calibration Bits bit 2 position. */ ++#define OSC_RC8MCAL3_bm (1<<3) /* Calibration Bits bit 3 mask. */ ++#define OSC_RC8MCAL3_bp 3 /* Calibration Bits bit 3 position. */ ++#define OSC_RC8MCAL4_bm (1<<4) /* Calibration Bits bit 4 mask. */ ++#define OSC_RC8MCAL4_bp 4 /* Calibration Bits bit 4 position. */ ++#define OSC_RC8MCAL5_bm (1<<5) /* Calibration Bits bit 5 mask. */ ++#define OSC_RC8MCAL5_bp 5 /* Calibration Bits bit 5 position. */ ++#define OSC_RC8MCAL6_bm (1<<6) /* Calibration Bits bit 6 mask. */ ++#define OSC_RC8MCAL6_bp 6 /* Calibration Bits bit 6 position. */ ++#define OSC_RC8MCAL7_bm (1<<7) /* Calibration Bits bit 7 mask. */ ++#define OSC_RC8MCAL7_bp 7 /* Calibration Bits bit 7 position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.WEXLOCK bit masks and bit positions */ ++#define MCU_WEXCLOCK_bm 0x01 /* WeX on T/C C4 Lock bit mask. */ ++#define MCU_WEXCLOCK_bp 0 /* WeX on T/C C4 Lock bit position. */ ++ ++/* MCU.FAULTLOCK bit masks and bit positions */ ++#define MCU_FAULTC5LOCK_bm 0x02 /* Fault on T/C C5 Lock bit mask. */ ++#define MCU_FAULTC5LOCK_bp 1 /* Fault on T/C C5 Lock bit position. */ ++ ++#define MCU_FAULTC4LOCK_bm 0x01 /* Fault on T/C C4 Lock bit mask. */ ++#define MCU_FAULTC4LOCK_bp 0 /* Fault on T/C C4 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.CLKOUT bit masks and bit positions */ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Clock and Event Output Pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Clock and Event Output Pin Select bit position. */ ++ ++#define PORTCFG_RTCOUT_gm 0x60 /* RTC Clock Output Enable group mask. */ ++#define PORTCFG_RTCOUT_gp 5 /* RTC Clock Output Enable group position. */ ++#define PORTCFG_RTCOUT0_bm (1<<5) /* RTC Clock Output Enable bit 0 mask. */ ++#define PORTCFG_RTCOUT0_bp 5 /* RTC Clock Output Enable bit 0 position. */ ++#define PORTCFG_RTCOUT1_bm (1<<6) /* RTC Clock Output Enable bit 1 mask. */ ++#define PORTCFG_RTCOUT1_bp 6 /* RTC Clock Output Enable bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ ++ ++/* PORTCFG.ACEVOUT bit masks and bit positions */ ++#define PORTCFG_ACOUT_gm 0xC0 /* Analog Comparator Output Port group mask. */ ++#define PORTCFG_ACOUT_gp 6 /* Analog Comparator Output Port group position. */ ++#define PORTCFG_ACOUT0_bm (1<<6) /* Analog Comparator Output Port bit 0 mask. */ ++#define PORTCFG_ACOUT0_bp 6 /* Analog Comparator Output Port bit 0 position. */ ++#define PORTCFG_ACOUT1_bm (1<<7) /* Analog Comparator Output Port bit 1 mask. */ ++#define PORTCFG_ACOUT1_bp 7 /* Analog Comparator Output Port bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Channel Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Channel Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Channel Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Channel Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Channel Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Channel Output Port bit 1 position. */ ++ ++#define PORTCFG_EVASYEN_bm 0x08 /* Asynchronous Event Enabled bit mask. */ ++#define PORTCFG_EVASYEN_bp 3 /* Asynchronous Event Enabled bit position. */ ++ ++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Channel Output Selection group mask. */ ++#define PORTCFG_EVOUTSEL_gp 0 /* Event Channel Output Selection group position. */ ++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Channel Output Selection bit 0 mask. */ ++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Channel Output Selection bit 0 position. */ ++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Channel Output Selection bit 1 mask. */ ++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Channel Output Selection bit 1 position. */ ++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Channel Output Selection bit 2 mask. */ ++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Channel Output Selection bit 2 position. */ ++ ++/* PORTCFG.SRLCTRL bit masks and bit positions */ ++#define PORTCFG_SRLENRA_bm 0x01 /* Slew Rate Limit Enable on PORTA bit mask. */ ++#define PORTCFG_SRLENRA_bp 0 /* Slew Rate Limit Enable on PORTA bit position. */ ++ ++#define PORTCFG_SRLENRC_bm 0x04 /* Slew Rate Limit Enable on PORTC bit mask. */ ++#define PORTCFG_SRLENRC_bp 2 /* Slew Rate Limit Enable on PORTC bit position. */ ++ ++#define PORTCFG_SRLENRD_bm 0x08 /* Slew Rate Limit Enable on PORTD bit mask. */ ++#define PORTCFG_SRLENRD_bp 3 /* Slew Rate Limit Enable on PORTD bit position. */ ++ ++#define PORTCFG_SRLENRR_bm 0x80 /* Slew Rate Limit Enable on PORTR bit mask. */ ++#define PORTCFG_SRLENRR_bp 7 /* Slew Rate Limit Enable on PORTR bit position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* EDMA - Enhanced DMA Controller */ ++/* EDMA.CTRL bit masks and bit positions */ ++#define EDMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define EDMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define EDMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define EDMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define EDMA_CHMODE_gm 0x30 /* Channel Mode group mask. */ ++#define EDMA_CHMODE_gp 4 /* Channel Mode group position. */ ++#define EDMA_CHMODE0_bm (1<<4) /* Channel Mode bit 0 mask. */ ++#define EDMA_CHMODE0_bp 4 /* Channel Mode bit 0 position. */ ++#define EDMA_CHMODE1_bm (1<<5) /* Channel Mode bit 1 mask. */ ++#define EDMA_CHMODE1_bp 5 /* Channel Mode bit 1 position. */ ++ ++#define EDMA_DBUFMODE_gm 0x0C /* Double Buffer Mode group mask. */ ++#define EDMA_DBUFMODE_gp 2 /* Double Buffer Mode group position. */ ++#define EDMA_DBUFMODE0_bm (1<<2) /* Double Buffer Mode bit 0 mask. */ ++#define EDMA_DBUFMODE0_bp 2 /* Double Buffer Mode bit 0 position. */ ++#define EDMA_DBUFMODE1_bm (1<<3) /* Double Buffer Mode bit 1 mask. */ ++#define EDMA_DBUFMODE1_bp 3 /* Double Buffer Mode bit 1 position. */ ++ ++#define EDMA_PRIMODE_gm 0x03 /* Priority Mode group mask. */ ++#define EDMA_PRIMODE_gp 0 /* Priority Mode group position. */ ++#define EDMA_PRIMODE0_bm (1<<0) /* Priority Mode bit 0 mask. */ ++#define EDMA_PRIMODE0_bp 0 /* Priority Mode bit 0 position. */ ++#define EDMA_PRIMODE1_bm (1<<1) /* Priority Mode bit 1 mask. */ ++#define EDMA_PRIMODE1_bp 1 /* Priority Mode bit 1 position. */ ++ ++/* EDMA.INTFLAGS bit masks and bit positions */ ++#define EDMA_CH3ERRIF_bm 0x80 /* Channel 3 Transaction Error Interrupt Flag bit mask. */ ++#define EDMA_CH3ERRIF_bp 7 /* Channel 3 Transaction Error Interrupt Flag bit position. */ ++ ++#define EDMA_CH2ERRIF_bm 0x40 /* Channel 2 Transaction Error Interrupt Flag bit mask. */ ++#define EDMA_CH2ERRIF_bp 6 /* Channel 2 Transaction Error Interrupt Flag bit position. */ ++ ++#define EDMA_CH1ERRIF_bm 0x20 /* Channel 1 Transaction Error Interrupt Flag bit mask. */ ++#define EDMA_CH1ERRIF_bp 5 /* Channel 1 Transaction Error Interrupt Flag bit position. */ ++ ++#define EDMA_CH0ERRIF_bm 0x10 /* Channel 0 Transaction Error Interrupt Flag bit mask. */ ++#define EDMA_CH0ERRIF_bp 4 /* Channel 0 Transaction Error Interrupt Flag bit position. */ ++ ++#define EDMA_CH3TRNFIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ ++#define EDMA_CH3TRNFIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ ++ ++#define EDMA_CH2TRNFIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ ++#define EDMA_CH2TRNFIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ ++ ++#define EDMA_CH1TRNFIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define EDMA_CH1TRNFIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define EDMA_CH0TRNFIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define EDMA_CH0TRNFIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++/* EDMA.STATUS bit masks and bit positions */ ++#define EDMA_CH3BUSY_bm 0x80 /* Channel 3 Busy Flag bit mask. */ ++#define EDMA_CH3BUSY_bp 7 /* Channel 3 Busy Flag bit position. */ ++ ++#define EDMA_CH2BUSY_bm 0x40 /* Channel 2 Busy Flag bit mask. */ ++#define EDMA_CH2BUSY_bp 6 /* Channel 2 Busy Flag bit position. */ ++ ++#define EDMA_CH1BUSY_bm 0x20 /* Channel 1 Busy Flag bit mask. */ ++#define EDMA_CH1BUSY_bp 5 /* Channel 1 Busy Flag bit position. */ ++ ++#define EDMA_CH0BUSY_bm 0x10 /* Channel 0 Busy Flag bit mask. */ ++#define EDMA_CH0BUSY_bp 4 /* Channel 0 Busy Flag bit position. */ ++ ++#define EDMA_CH3PEND_bm 0x08 /* Channel 3 Pending Flag bit mask. */ ++#define EDMA_CH3PEND_bp 3 /* Channel 3 Pending Flag bit position. */ ++ ++#define EDMA_CH2PEND_bm 0x04 /* Channel 2 Pending Flag bit mask. */ ++#define EDMA_CH2PEND_bp 2 /* Channel 2 Pending Flag bit position. */ ++ ++#define EDMA_CH1PEND_bm 0x02 /* Channel 1 Pending Flag bit mask. */ ++#define EDMA_CH1PEND_bp 1 /* Channel 1 Pending Flag bit position. */ ++ ++#define EDMA_CH0PEND_bm 0x01 /* Channel 0 Pending Flag bit mask. */ ++#define EDMA_CH0PEND_bp 0 /* Channel 0 Pending Flag bit position. */ ++ ++/* EDMA_CH.CTRLA bit masks and bit positions */ ++#define EDMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ ++#define EDMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ ++ ++#define EDMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ ++#define EDMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ ++ ++#define EDMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define EDMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define EDMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define EDMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define EDMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define EDMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define EDMA_CH_BURSTLEN_bm 0x01 /* Channel 2-bytes Burst Length bit mask. */ ++#define EDMA_CH_BURSTLEN_bp 0 /* Channel 2-bytes Burst Length bit position. */ ++ ++/* EDMA_CH.CTRLB bit masks and bit positions */ ++#define EDMA_CH_CHBUSY_bm 0x80 /* Channel Block Transfer Busy bit mask. */ ++#define EDMA_CH_CHBUSY_bp 7 /* Channel Block Transfer Busy bit position. */ ++ ++#define EDMA_CH_CHPEND_bm 0x40 /* Channel Block Transfer Pending bit mask. */ ++#define EDMA_CH_CHPEND_bp 6 /* Channel Block Transfer Pending bit position. */ ++ ++#define EDMA_CH_ERRIF_bm 0x20 /* Channel Transaction Error Interrupt Flag bit mask. */ ++#define EDMA_CH_ERRIF_bp 5 /* Channel Transaction Error Interrupt Flag bit position. */ ++ ++#define EDMA_CH_TRNIF_bm 0x10 /* Channel Transaction Complete Interrup Flag bit mask. */ ++#define EDMA_CH_TRNIF_bp 4 /* Channel Transaction Complete Interrup Flag bit position. */ ++ ++#define EDMA_CH_ERRINTLVL_gm 0x0C /* Channel Transaction Error Interrupt Level group mask. */ ++#define EDMA_CH_ERRINTLVL_gp 2 /* Channel Transaction Error Interrupt Level group position. */ ++#define EDMA_CH_ERRINTLVL0_bm (1<<2) /* Channel Transaction Error Interrupt Level bit 0 mask. */ ++#define EDMA_CH_ERRINTLVL0_bp 2 /* Channel Transaction Error Interrupt Level bit 0 position. */ ++#define EDMA_CH_ERRINTLVL1_bm (1<<3) /* Channel Transaction Error Interrupt Level bit 1 mask. */ ++#define EDMA_CH_ERRINTLVL1_bp 3 /* Channel Transaction Error Interrupt Level bit 1 position. */ ++ ++#define EDMA_CH_TRNINTLVL_gm 0x03 /* Channel Transaction Complete Interrupt Level group mask. */ ++#define EDMA_CH_TRNINTLVL_gp 0 /* Channel Transaction Complete Interrupt Level group position. */ ++#define EDMA_CH_TRNINTLVL0_bm (1<<0) /* Channel Transaction Complete Interrupt Level bit 0 mask. */ ++#define EDMA_CH_TRNINTLVL0_bp 0 /* Channel Transaction Complete Interrupt Level bit 0 position. */ ++#define EDMA_CH_TRNINTLVL1_bm (1<<1) /* Channel Transaction Complete Interrupt Level bit 1 mask. */ ++#define EDMA_CH_TRNINTLVL1_bp 1 /* Channel Transaction Complete Interrupt Level bit 1 position. */ ++ ++/* EDMA_CH.ADDRCTRL bit masks and bit positions */ ++#define EDMA_CH_RELOAD_gm 0x30 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group mask. */ ++#define EDMA_CH_RELOAD_gp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group position. */ ++#define EDMA_CH_RELOAD0_bm (1<<4) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 mask. */ ++#define EDMA_CH_RELOAD0_bp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 position. */ ++#define EDMA_CH_RELOAD1_bm (1<<5) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 mask. */ ++#define EDMA_CH_RELOAD1_bp 5 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 position. */ ++ ++#define EDMA_CH_DIR_gm 0x07 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group mask. */ ++#define EDMA_CH_DIR_gp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group position. */ ++#define EDMA_CH_DIR0_bm (1<<0) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 mask. */ ++#define EDMA_CH_DIR0_bp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 position. */ ++#define EDMA_CH_DIR1_bm (1<<1) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 mask. */ ++#define EDMA_CH_DIR1_bp 1 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 position. */ ++#define EDMA_CH_DIR2_bm (1<<2) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 mask. */ ++#define EDMA_CH_DIR2_bp 2 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 position. */ ++ ++/* EDMA_CH.DESTADDRCTRL bit masks and bit positions */ ++#define EDMA_CH_DESTRELOAD_gm 0x30 /* Destination Address Reload for Standard Channels Only. group mask. */ ++#define EDMA_CH_DESTRELOAD_gp 4 /* Destination Address Reload for Standard Channels Only. group position. */ ++#define EDMA_CH_DESTRELOAD0_bm (1<<4) /* Destination Address Reload for Standard Channels Only. bit 0 mask. */ ++#define EDMA_CH_DESTRELOAD0_bp 4 /* Destination Address Reload for Standard Channels Only. bit 0 position. */ ++#define EDMA_CH_DESTRELOAD1_bm (1<<5) /* Destination Address Reload for Standard Channels Only. bit 1 mask. */ ++#define EDMA_CH_DESTRELOAD1_bp 5 /* Destination Address Reload for Standard Channels Only. bit 1 position. */ ++ ++#define EDMA_CH_DESTDIR_gm 0x07 /* Destination Address Mode for Standard Channels Only. group mask. */ ++#define EDMA_CH_DESTDIR_gp 0 /* Destination Address Mode for Standard Channels Only. group position. */ ++#define EDMA_CH_DESTDIR0_bm (1<<0) /* Destination Address Mode for Standard Channels Only. bit 0 mask. */ ++#define EDMA_CH_DESTDIR0_bp 0 /* Destination Address Mode for Standard Channels Only. bit 0 position. */ ++#define EDMA_CH_DESTDIR1_bm (1<<1) /* Destination Address Mode for Standard Channels Only. bit 1 mask. */ ++#define EDMA_CH_DESTDIR1_bp 1 /* Destination Address Mode for Standard Channels Only. bit 1 position. */ ++#define EDMA_CH_DESTDIR2_bm (1<<2) /* Destination Address Mode for Standard Channels Only. bit 2 mask. */ ++#define EDMA_CH_DESTDIR2_bp 2 /* Destination Address Mode for Standard Channels Only. bit 2 position. */ ++ ++/* EDMA_CH.TRIGSRC bit masks and bit positions */ ++#define EDMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define EDMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define EDMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define EDMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define EDMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define EDMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define EDMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define EDMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define EDMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define EDMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define EDMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define EDMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define EDMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define EDMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define EDMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define EDMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define EDMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define EDMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH4MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH5MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH6MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH7MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_ROTARY_bm 0x80 /* Rotary Decoder Enable bit mask. */ ++#define EVSYS_ROTARY_bp 7 /* Rotary Decoder Enable bit position. */ ++ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH4CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH5CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH6CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH7CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.DFCTRL bit masks and bit positions */ ++#define EVSYS_PRESCFILT_gm 0xF0 /* Prescaler Filter group mask. */ ++#define EVSYS_PRESCFILT_gp 4 /* Prescaler Filter group position. */ ++#define EVSYS_PRESCFILT0_bm (1<<4) /* Prescaler Filter bit 0 mask. */ ++#define EVSYS_PRESCFILT0_bp 4 /* Prescaler Filter bit 0 position. */ ++#define EVSYS_PRESCFILT1_bm (1<<5) /* Prescaler Filter bit 1 mask. */ ++#define EVSYS_PRESCFILT1_bp 5 /* Prescaler Filter bit 1 position. */ ++#define EVSYS_PRESCFILT2_bm (1<<6) /* Prescaler Filter bit 2 mask. */ ++#define EVSYS_PRESCFILT2_bp 6 /* Prescaler Filter bit 2 position. */ ++#define EVSYS_PRESCFILT3_bm (1<<7) /* Prescaler Filter bit 3 mask. */ ++#define EVSYS_PRESCFILT3_bp 7 /* Prescaler Filter bit 3 position. */ ++ ++#define EVSYS_FILTSEL_bm 0x08 /* Prescaler Filter Select bit mask. */ ++#define EVSYS_FILTSEL_bp 3 /* Prescaler Filter Select bit position. */ ++ ++#define EVSYS_PRESC_gm 0x07 /* Prescaler group mask. */ ++#define EVSYS_PRESC_gp 0 /* Prescaler group position. */ ++#define EVSYS_PRESC0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define EVSYS_PRESC0_bp 0 /* Prescaler bit 0 position. */ ++#define EVSYS_PRESC1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define EVSYS_PRESC1_bp 1 /* Prescaler bit 1 position. */ ++#define EVSYS_PRESC2_bm (1<<2) /* Prescaler bit 2 mask. */ ++#define EVSYS_PRESC2_bp 2 /* Prescaler bit 2 position. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC Input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC Input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC Input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC Input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC Input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC Input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC Input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC Input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC Input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC Input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC Input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC Input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC Input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC Input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC Input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC Input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC Input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC Input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC Input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC Input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC Input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC Input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC Input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC Input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC Input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC Input bit 1 position. */ ++ ++#define ADC_CH_MUXNEGL_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group mask. */ ++#define ADC_CH_MUXNEGL_gp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group position. */ ++#define ADC_CH_MUXNEGL0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 mask. */ ++#define ADC_CH_MUXNEGL0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 position. */ ++#define ADC_CH_MUXNEGL1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 mask. */ ++#define ADC_CH_MUXNEGL1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 position. */ ++ ++#define ADC_CH_MUXNEGH_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group mask. */ ++#define ADC_CH_MUXNEGH_gp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group position. */ ++#define ADC_CH_MUXNEGH0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 mask. */ ++#define ADC_CH_MUXNEGH0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 position. */ ++#define ADC_CH_MUXNEGH1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 mask. */ ++#define ADC_CH_MUXNEGH1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_IF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_IF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_INPUTOFFSET_gm 0xF0 /* Positive MUX Setting Offset group mask. */ ++#define ADC_CH_INPUTOFFSET_gp 4 /* Positive MUX Setting Offset group position. */ ++#define ADC_CH_INPUTOFFSET0_bm (1<<4) /* Positive MUX Setting Offset bit 0 mask. */ ++#define ADC_CH_INPUTOFFSET0_bp 4 /* Positive MUX Setting Offset bit 0 position. */ ++#define ADC_CH_INPUTOFFSET1_bm (1<<5) /* Positive MUX Setting Offset bit 1 mask. */ ++#define ADC_CH_INPUTOFFSET1_bp 5 /* Positive MUX Setting Offset bit 1 position. */ ++#define ADC_CH_INPUTOFFSET2_bm (1<<6) /* Positive MUX Setting Offset bit 2 mask. */ ++#define ADC_CH_INPUTOFFSET2_bp 6 /* Positive MUX Setting Offset bit 2 position. */ ++#define ADC_CH_INPUTOFFSET3_bm (1<<7) /* Positive MUX Setting Offset bit 3 mask. */ ++#define ADC_CH_INPUTOFFSET3_bp 7 /* Positive MUX Setting Offset bit 3 position. */ ++ ++#define ADC_CH_INPUTSCAN_gm 0x0F /* Number of Channels Included in Scan group mask. */ ++#define ADC_CH_INPUTSCAN_gp 0 /* Number of Channels Included in Scan group position. */ ++#define ADC_CH_INPUTSCAN0_bm (1<<0) /* Number of Channels Included in Scan bit 0 mask. */ ++#define ADC_CH_INPUTSCAN0_bp 0 /* Number of Channels Included in Scan bit 0 position. */ ++#define ADC_CH_INPUTSCAN1_bm (1<<1) /* Number of Channels Included in Scan bit 1 mask. */ ++#define ADC_CH_INPUTSCAN1_bp 1 /* Number of Channels Included in Scan bit 1 position. */ ++#define ADC_CH_INPUTSCAN2_bm (1<<2) /* Number of Channels Included in Scan bit 2 mask. */ ++#define ADC_CH_INPUTSCAN2_bp 2 /* Number of Channels Included in Scan bit 2 position. */ ++#define ADC_CH_INPUTSCAN3_bm (1<<3) /* Number of Channels Included in Scan bit 3 mask. */ ++#define ADC_CH_INPUTSCAN3_bp 3 /* Number of Channels Included in Scan bit 3 position. */ ++ ++/* ADC_CH.CORRCTRL bit masks and bit positions */ ++#define ADC_CH_CORREN_bm 0x01 /* Correction Enable bit mask. */ ++#define ADC_CH_CORREN_bp 0 /* Correction Enable bit position. */ ++ ++/* ADC_CH.OFFSETCORR1 bit masks and bit positions */ ++#define ADC_CH_OFFSETCORR_gm 0x0F /* Offset Correction Byte 1 group mask. */ ++#define ADC_CH_OFFSETCORR_gp 0 /* Offset Correction Byte 1 group position. */ ++#define ADC_CH_OFFSETCORR0_bm (1<<0) /* Offset Correction Byte 1 bit 0 mask. */ ++#define ADC_CH_OFFSETCORR0_bp 0 /* Offset Correction Byte 1 bit 0 position. */ ++#define ADC_CH_OFFSETCORR1_bm (1<<1) /* Offset Correction Byte 1 bit 1 mask. */ ++#define ADC_CH_OFFSETCORR1_bp 1 /* Offset Correction Byte 1 bit 1 position. */ ++#define ADC_CH_OFFSETCORR2_bm (1<<2) /* Offset Correction Byte 1 bit 2 mask. */ ++#define ADC_CH_OFFSETCORR2_bp 2 /* Offset Correction Byte 1 bit 2 position. */ ++#define ADC_CH_OFFSETCORR3_bm (1<<3) /* Offset Correction Byte 1 bit 3 mask. */ ++#define ADC_CH_OFFSETCORR3_bp 3 /* Offset Correction Byte 1 bit 3 position. */ ++ ++/* ADC_CH.GAINCORR1 bit masks and bit positions */ ++#define ADC_CH_GAINCORR_gm 0x0F /* Gain Correction Byte 1 group mask. */ ++#define ADC_CH_GAINCORR_gp 0 /* Gain Correction Byte 1 group position. */ ++#define ADC_CH_GAINCORR0_bm (1<<0) /* Gain Correction Byte 1 bit 0 mask. */ ++#define ADC_CH_GAINCORR0_bp 0 /* Gain Correction Byte 1 bit 0 position. */ ++#define ADC_CH_GAINCORR1_bm (1<<1) /* Gain Correction Byte 1 bit 1 mask. */ ++#define ADC_CH_GAINCORR1_bp 1 /* Gain Correction Byte 1 bit 1 position. */ ++#define ADC_CH_GAINCORR2_bm (1<<2) /* Gain Correction Byte 1 bit 2 mask. */ ++#define ADC_CH_GAINCORR2_bp 2 /* Gain Correction Byte 1 bit 2 position. */ ++#define ADC_CH_GAINCORR3_bm (1<<3) /* Gain Correction Byte 1 bit 3 mask. */ ++#define ADC_CH_GAINCORR3_bp 3 /* Gain Correction Byte 1 bit 3 position. */ ++ ++/* ADC_CH.AVGCTRL bit masks and bit positions */ ++#define ADC_CH_RIGHTSHIFT_gm 0x70 /* Right Shift group mask. */ ++#define ADC_CH_RIGHTSHIFT_gp 4 /* Right Shift group position. */ ++#define ADC_CH_RIGHTSHIFT0_bm (1<<4) /* Right Shift bit 0 mask. */ ++#define ADC_CH_RIGHTSHIFT0_bp 4 /* Right Shift bit 0 position. */ ++#define ADC_CH_RIGHTSHIFT1_bm (1<<5) /* Right Shift bit 1 mask. */ ++#define ADC_CH_RIGHTSHIFT1_bp 5 /* Right Shift bit 1 position. */ ++#define ADC_CH_RIGHTSHIFT2_bm (1<<6) /* Right Shift bit 2 mask. */ ++#define ADC_CH_RIGHTSHIFT2_bp 6 /* Right Shift bit 2 position. */ ++ ++#define ADC_CH_SAMPNUM_gm 0x0F /* Averaged Number of Samples group mask. */ ++#define ADC_CH_SAMPNUM_gp 0 /* Averaged Number of Samples group position. */ ++#define ADC_CH_SAMPNUM0_bm (1<<0) /* Averaged Number of Samples bit 0 mask. */ ++#define ADC_CH_SAMPNUM0_bp 0 /* Averaged Number of Samples bit 0 position. */ ++#define ADC_CH_SAMPNUM1_bm (1<<1) /* Averaged Number of Samples bit 1 mask. */ ++#define ADC_CH_SAMPNUM1_bp 1 /* Averaged Number of Samples bit 1 position. */ ++#define ADC_CH_SAMPNUM2_bm (1<<2) /* Averaged Number of Samples bit 2 mask. */ ++#define ADC_CH_SAMPNUM2_bp 2 /* Averaged Number of Samples bit 2 position. */ ++#define ADC_CH_SAMPNUM3_bm (1<<3) /* Averaged Number of Samples bit 3 mask. */ ++#define ADC_CH_SAMPNUM3_bp 3 /* Averaged Number of Samples bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_START_bm 0x04 /* Start Conversion bit mask. */ ++#define ADC_START_bp 2 /* Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ ++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* ADC.SAMPCTRL bit masks and bit positions */ ++#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ ++#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ ++#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ ++#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ ++#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ ++#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ ++#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ ++#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ ++#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ ++#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ ++#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ ++#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ ++#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ ++#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ ++ ++/* DAC - Digital/Analog Converter */ ++/* DAC.CTRLA bit masks and bit positions */ ++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ ++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ ++ ++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ ++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ ++ ++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ ++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ ++ ++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ ++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ ++ ++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define DAC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* DAC.CTRLB bit masks and bit positions */ ++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ ++#define DAC_CHSEL_gp 5 /* Channel Select group position. */ ++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ ++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ ++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ ++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ ++ ++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ ++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ ++ ++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ ++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ ++ ++/* DAC.CTRLC bit masks and bit positions */ ++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ ++#define DAC_REFSEL_gp 3 /* Reference Select group position. */ ++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ ++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ ++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ ++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ ++ ++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ ++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ ++ ++/* DAC.EVCTRL bit masks and bit positions */ ++#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ ++#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ ++ ++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ ++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ ++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ ++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ ++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ ++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ ++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ ++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ ++ ++/* DAC.STATUS bit masks and bit positions */ ++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ ++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ ++ ++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ ++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ ++ ++/* DAC.CH0GAINCAL bit masks and bit positions */ ++#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH0OFFSETCAL bit masks and bit positions */ ++#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* DAC.CH1GAINCAL bit masks and bit positions */ ++#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH1OFFSETCAL bit masks and bit positions */ ++#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1INVEN_bm 0x08 /* Analog Comparator 1 Output Invert Enable bit mask. */ ++#define AC_AC1INVEN_bp 3 /* Analog Comparator 1 Output Invert Enable bit position. */ ++ ++#define AC_AC0INVEN_bm 0x04 /* Analog Comparator 0 Output Invert Enable bit mask. */ ++#define AC_AC0INVEN_bp 2 /* Analog Comparator 0 Output Invert Enable bit position. */ ++ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* AC.CURRCTRL bit masks and bit positions */ ++#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ ++#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ ++ ++#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ ++#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ ++ ++#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ ++#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ ++ ++#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ ++#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ ++ ++/* AC.CURRCALIB bit masks and bit positions */ ++#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ ++#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ ++#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ ++#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ ++#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ ++#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ ++#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ ++#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ ++#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ ++#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ ++ ++/* RTC - Real-Time Clounter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_CORREN_bm 0x08 /* Correction Enable bit mask. */ ++#define RTC_CORREN_bp 3 /* Correction Enable bit position. */ ++ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* RTC.CALIB bit masks and bit positions */ ++#define RTC_SIGN_bm 0x80 /* Correction Sign bit mask. */ ++#define RTC_SIGN_bp 7 /* Correction Sign bit position. */ ++ ++#define RTC_ERROR_gm 0x7F /* Error Value group mask. */ ++#define RTC_ERROR_gp 0 /* Error Value group position. */ ++#define RTC_ERROR0_bm (1<<0) /* Error Value bit 0 mask. */ ++#define RTC_ERROR0_bp 0 /* Error Value bit 0 position. */ ++#define RTC_ERROR1_bm (1<<1) /* Error Value bit 1 mask. */ ++#define RTC_ERROR1_bp 1 /* Error Value bit 1 position. */ ++#define RTC_ERROR2_bm (1<<2) /* Error Value bit 2 mask. */ ++#define RTC_ERROR2_bp 2 /* Error Value bit 2 position. */ ++#define RTC_ERROR3_bm (1<<3) /* Error Value bit 3 mask. */ ++#define RTC_ERROR3_bp 3 /* Error Value bit 3 position. */ ++#define RTC_ERROR4_bm (1<<4) /* Error Value bit 4 mask. */ ++#define RTC_ERROR4_bp 4 /* Error Value bit 4 position. */ ++#define RTC_ERROR5_bm (1<<5) /* Error Value bit 5 mask. */ ++#define RTC_ERROR5_bp 5 /* Error Value bit 5 position. */ ++#define RTC_ERROR6_bm (1<<6) /* Error Value bit 6 mask. */ ++#define RTC_ERROR6_bp 6 /* Error Value bit 6 position. */ ++ ++/* XCL - XMEGA Custom Logic */ ++/* XCL.CTRLA bit masks and bit positions */ ++#define XCL_LUT0OUTEN_gm 0xC0 /* LUT0 Output Enable group mask. */ ++#define XCL_LUT0OUTEN_gp 6 /* LUT0 Output Enable group position. */ ++#define XCL_LUT0OUTEN0_bm (1<<6) /* LUT0 Output Enable bit 0 mask. */ ++#define XCL_LUT0OUTEN0_bp 6 /* LUT0 Output Enable bit 0 position. */ ++#define XCL_LUT0OUTEN1_bm (1<<7) /* LUT0 Output Enable bit 1 mask. */ ++#define XCL_LUT0OUTEN1_bp 7 /* LUT0 Output Enable bit 1 position. */ ++ ++#define XCL_PORTSEL_gm 0x30 /* Port Selection group mask. */ ++#define XCL_PORTSEL_gp 4 /* Port Selection group position. */ ++#define XCL_PORTSEL0_bm (1<<4) /* Port Selection bit 0 mask. */ ++#define XCL_PORTSEL0_bp 4 /* Port Selection bit 0 position. */ ++#define XCL_PORTSEL1_bm (1<<5) /* Port Selection bit 1 mask. */ ++#define XCL_PORTSEL1_bp 5 /* Port Selection bit 1 position. */ ++ ++#define XCL_LUTCONF_gm 0x07 /* LUT Configuration group mask. */ ++#define XCL_LUTCONF_gp 0 /* LUT Configuration group position. */ ++#define XCL_LUTCONF0_bm (1<<0) /* LUT Configuration bit 0 mask. */ ++#define XCL_LUTCONF0_bp 0 /* LUT Configuration bit 0 position. */ ++#define XCL_LUTCONF1_bm (1<<1) /* LUT Configuration bit 1 mask. */ ++#define XCL_LUTCONF1_bp 1 /* LUT Configuration bit 1 position. */ ++#define XCL_LUTCONF2_bm (1<<2) /* LUT Configuration bit 2 mask. */ ++#define XCL_LUTCONF2_bp 2 /* LUT Configuration bit 2 position. */ ++ ++/* XCL.CTRLB bit masks and bit positions */ ++#define XCL_IN3SEL_gm 0xC0 /* Input Selection 3 group mask. */ ++#define XCL_IN3SEL_gp 6 /* Input Selection 3 group position. */ ++#define XCL_IN3SEL0_bm (1<<6) /* Input Selection 3 bit 0 mask. */ ++#define XCL_IN3SEL0_bp 6 /* Input Selection 3 bit 0 position. */ ++#define XCL_IN3SEL1_bm (1<<7) /* Input Selection 3 bit 1 mask. */ ++#define XCL_IN3SEL1_bp 7 /* Input Selection 3 bit 1 position. */ ++ ++#define XCL_IN2SEL_gm 0x30 /* Input Selection 2 group mask. */ ++#define XCL_IN2SEL_gp 4 /* Input Selection 2 group position. */ ++#define XCL_IN2SEL0_bm (1<<4) /* Input Selection 2 bit 0 mask. */ ++#define XCL_IN2SEL0_bp 4 /* Input Selection 2 bit 0 position. */ ++#define XCL_IN2SEL1_bm (1<<5) /* Input Selection 2 bit 1 mask. */ ++#define XCL_IN2SEL1_bp 5 /* Input Selection 2 bit 1 position. */ ++ ++#define XCL_IN1SEL_gm 0x0C /* Input Selection 1 group mask. */ ++#define XCL_IN1SEL_gp 2 /* Input Selection 1 group position. */ ++#define XCL_IN1SEL0_bm (1<<2) /* Input Selection 1 bit 0 mask. */ ++#define XCL_IN1SEL0_bp 2 /* Input Selection 1 bit 0 position. */ ++#define XCL_IN1SEL1_bm (1<<3) /* Input Selection 1 bit 1 mask. */ ++#define XCL_IN1SEL1_bp 3 /* Input Selection 1 bit 1 position. */ ++ ++#define XCL_IN0SEL_gm 0x03 /* Input Selection 0 group mask. */ ++#define XCL_IN0SEL_gp 0 /* Input Selection 0 group position. */ ++#define XCL_IN0SEL0_bm (1<<0) /* Input Selection 0 bit 0 mask. */ ++#define XCL_IN0SEL0_bp 0 /* Input Selection 0 bit 0 position. */ ++#define XCL_IN0SEL1_bm (1<<1) /* Input Selection 0 bit 1 mask. */ ++#define XCL_IN0SEL1_bp 1 /* Input Selection 0 bit 1 position. */ ++ ++/* XCL.CTRLC bit masks and bit positions */ ++#define XCL_EVASYSEL1_bm 0x80 /* Asynchronous Event Line Selection for LUT1 bit mask. */ ++#define XCL_EVASYSEL1_bp 7 /* Asynchronous Event Line Selection for LUT1 bit position. */ ++ ++#define XCL_EVASYSEL0_bm 0x40 /* Asynchronous Event Line Selection for LUT0 bit mask. */ ++#define XCL_EVASYSEL0_bp 6 /* Asynchronous Event Line Selection for LUT0 bit position. */ ++ ++#define XCL_DLYSEL_gm 0x30 /* Delay Selection group mask. */ ++#define XCL_DLYSEL_gp 4 /* Delay Selection group position. */ ++#define XCL_DLYSEL0_bm (1<<4) /* Delay Selection bit 0 mask. */ ++#define XCL_DLYSEL0_bp 4 /* Delay Selection bit 0 position. */ ++#define XCL_DLYSEL1_bm (1<<5) /* Delay Selection bit 1 mask. */ ++#define XCL_DLYSEL1_bp 5 /* Delay Selection bit 1 position. */ ++ ++#define XCL_DLY1CONF_gm 0x0C /* Delay Configuration on LUT1 group mask. */ ++#define XCL_DLY1CONF_gp 2 /* Delay Configuration on LUT1 group position. */ ++#define XCL_DLY1CONF0_bm (1<<2) /* Delay Configuration on LUT1 bit 0 mask. */ ++#define XCL_DLY1CONF0_bp 2 /* Delay Configuration on LUT1 bit 0 position. */ ++#define XCL_DLY1CONF1_bm (1<<3) /* Delay Configuration on LUT1 bit 1 mask. */ ++#define XCL_DLY1CONF1_bp 3 /* Delay Configuration on LUT1 bit 1 position. */ ++ ++#define XCL_DLY0CONF_gm 0x03 /* Delay Configuration on LUT0 group mask. */ ++#define XCL_DLY0CONF_gp 0 /* Delay Configuration on LUT0 group position. */ ++#define XCL_DLY0CONF0_bm (1<<0) /* Delay Configuration on LUT0 bit 0 mask. */ ++#define XCL_DLY0CONF0_bp 0 /* Delay Configuration on LUT0 bit 0 position. */ ++#define XCL_DLY0CONF1_bm (1<<1) /* Delay Configuration on LUT0 bit 1 mask. */ ++#define XCL_DLY0CONF1_bp 1 /* Delay Configuration on LUT0 bit 1 position. */ ++ ++/* XCL.CTRLD bit masks and bit positions */ ++#define XCL_TRUTH1_gm 0xF0 /* Truth Table of LUT1 group mask. */ ++#define XCL_TRUTH1_gp 4 /* Truth Table of LUT1 group position. */ ++#define XCL_TRUTH10_bm (1<<4) /* Truth Table of LUT1 bit 0 mask. */ ++#define XCL_TRUTH10_bp 4 /* Truth Table of LUT1 bit 0 position. */ ++#define XCL_TRUTH11_bm (1<<5) /* Truth Table of LUT1 bit 1 mask. */ ++#define XCL_TRUTH11_bp 5 /* Truth Table of LUT1 bit 1 position. */ ++#define XCL_TRUTH12_bm (1<<6) /* Truth Table of LUT1 bit 2 mask. */ ++#define XCL_TRUTH12_bp 6 /* Truth Table of LUT1 bit 2 position. */ ++#define XCL_TRUTH13_bm (1<<7) /* Truth Table of LUT1 bit 3 mask. */ ++#define XCL_TRUTH13_bp 7 /* Truth Table of LUT1 bit 3 position. */ ++ ++#define XCL_TRUTH0_gm 0x0F /* Truth Table of LUT0 group mask. */ ++#define XCL_TRUTH0_gp 0 /* Truth Table of LUT0 group position. */ ++#define XCL_TRUTH00_bm (1<<0) /* Truth Table of LUT0 bit 0 mask. */ ++#define XCL_TRUTH00_bp 0 /* Truth Table of LUT0 bit 0 position. */ ++#define XCL_TRUTH01_bm (1<<1) /* Truth Table of LUT0 bit 1 mask. */ ++#define XCL_TRUTH01_bp 1 /* Truth Table of LUT0 bit 1 position. */ ++#define XCL_TRUTH02_bm (1<<2) /* Truth Table of LUT0 bit 2 mask. */ ++#define XCL_TRUTH02_bp 2 /* Truth Table of LUT0 bit 2 position. */ ++#define XCL_TRUTH03_bm (1<<3) /* Truth Table of LUT0 bit 3 mask. */ ++#define XCL_TRUTH03_bp 3 /* Truth Table of LUT0 bit 3 position. */ ++ ++/* XCL.CTRLE bit masks and bit positions */ ++#define XCL_CMDSEL_bm 0x80 /* Timer/Counter Command Selection bit mask. */ ++#define XCL_CMDSEL_bp 7 /* Timer/Counter Command Selection bit position. */ ++ ++#define XCL_TCSEL_gm 0x70 /* Timer/Counter Selection group mask. */ ++#define XCL_TCSEL_gp 4 /* Timer/Counter Selection group position. */ ++#define XCL_TCSEL0_bm (1<<4) /* Timer/Counter Selection bit 0 mask. */ ++#define XCL_TCSEL0_bp 4 /* Timer/Counter Selection bit 0 position. */ ++#define XCL_TCSEL1_bm (1<<5) /* Timer/Counter Selection bit 1 mask. */ ++#define XCL_TCSEL1_bp 5 /* Timer/Counter Selection bit 1 position. */ ++#define XCL_TCSEL2_bm (1<<6) /* Timer/Counter Selection bit 2 mask. */ ++#define XCL_TCSEL2_bp 6 /* Timer/Counter Selection bit 2 position. */ ++ ++#define XCL_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define XCL_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define XCL_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define XCL_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define XCL_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define XCL_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define XCL_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define XCL_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define XCL_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define XCL_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* XCL.CTRLF bit masks and bit positions */ ++#define XCL_CMDEN_gm 0xC0 /* Command Enable group mask. */ ++#define XCL_CMDEN_gp 6 /* Command Enable group position. */ ++#define XCL_CMDEN0_bm (1<<6) /* Command Enable bit 0 mask. */ ++#define XCL_CMDEN0_bp 6 /* Command Enable bit 0 position. */ ++#define XCL_CMDEN1_bm (1<<7) /* Command Enable bit 1 mask. */ ++#define XCL_CMDEN1_bp 7 /* Command Enable bit 1 position. */ ++ ++#define XCL_CMP1_bm 0x20 /* Compare Channel 1 Output Value bit mask. */ ++#define XCL_CMP1_bp 5 /* Compare Channel 1 Output Value bit position. */ ++ ++#define XCL_CMP0_bm 0x10 /* Compare Channel 0 Output Value bit mask. */ ++#define XCL_CMP0_bp 4 /* Compare Channel 0 Output Value bit position. */ ++ ++#define XCL_CCEN1_bm 0x08 /* Compare or Capture Channel 1 Enable bit mask. */ ++#define XCL_CCEN1_bp 3 /* Compare or Capture Channel 1 Enable bit position. */ ++ ++#define XCL_CCEN0_bm 0x04 /* Compare or Capture Channel 0 Enable bit mask. */ ++#define XCL_CCEN0_bp 2 /* Compare or Capture Channel 0 Enable bit position. */ ++ ++#define XCL_MODE_gm 0x03 /* Timer/Counter Mode group mask. */ ++#define XCL_MODE_gp 0 /* Timer/Counter Mode group position. */ ++#define XCL_MODE0_bm (1<<0) /* Timer/Counter Mode bit 0 mask. */ ++#define XCL_MODE0_bp 0 /* Timer/Counter Mode bit 0 position. */ ++#define XCL_MODE1_bm (1<<1) /* Timer/Counter Mode bit 1 mask. */ ++#define XCL_MODE1_bp 1 /* Timer/Counter Mode bit 1 position. */ ++ ++/* XCL.CTRLG bit masks and bit positions */ ++#define XCL_EVACTEN_bm 0x80 /* Event Action Enable bit mask. */ ++#define XCL_EVACTEN_bp 7 /* Event Action Enable bit position. */ ++ ++#define XCL_EVACT1_gm 0x60 /* Event Action Selection on Timer/Counter 1 group mask. */ ++#define XCL_EVACT1_gp 5 /* Event Action Selection on Timer/Counter 1 group position. */ ++#define XCL_EVACT10_bm (1<<5) /* Event Action Selection on Timer/Counter 1 bit 0 mask. */ ++#define XCL_EVACT10_bp 5 /* Event Action Selection on Timer/Counter 1 bit 0 position. */ ++#define XCL_EVACT11_bm (1<<6) /* Event Action Selection on Timer/Counter 1 bit 1 mask. */ ++#define XCL_EVACT11_bp 6 /* Event Action Selection on Timer/Counter 1 bit 1 position. */ ++ ++#define XCL_EVACT0_gm 0x18 /* Event Action Selection on Timer/Counter 0 group mask. */ ++#define XCL_EVACT0_gp 3 /* Event Action Selection on Timer/Counter 0 group position. */ ++#define XCL_EVACT00_bm (1<<3) /* Event Action Selection on Timer/Counter 0 bit 0 mask. */ ++#define XCL_EVACT00_bp 3 /* Event Action Selection on Timer/Counter 0 bit 0 position. */ ++#define XCL_EVACT01_bm (1<<4) /* Event Action Selection on Timer/Counter 0 bit 1 mask. */ ++#define XCL_EVACT01_bp 4 /* Event Action Selection on Timer/Counter 0 bit 1 position. */ ++ ++#define XCL_EVSRC_gm 0x07 /* Event Source Selection group mask. */ ++#define XCL_EVSRC_gp 0 /* Event Source Selection group position. */ ++#define XCL_EVSRC0_bm (1<<0) /* Event Source Selection bit 0 mask. */ ++#define XCL_EVSRC0_bp 0 /* Event Source Selection bit 0 position. */ ++#define XCL_EVSRC1_bm (1<<1) /* Event Source Selection bit 1 mask. */ ++#define XCL_EVSRC1_bp 1 /* Event Source Selection bit 1 position. */ ++#define XCL_EVSRC2_bm (1<<2) /* Event Source Selection bit 2 mask. */ ++#define XCL_EVSRC2_bp 2 /* Event Source Selection bit 2 position. */ ++ ++/* XCL.INTCTRL bit masks and bit positions */ ++#define XCL_UNF1IE_bm 0x80 /* Underflow 1 Interrupt Enable bit mask. */ ++#define XCL_UNF1IE_bp 7 /* Underflow 1 Interrupt Enable bit position. */ ++ ++#define XCL_PEC1IE_bm 0x80 /* Peripheral Counter 1 Interrupt Enable bit mask. */ ++#define XCL_PEC1IE_bp 7 /* Peripheral Counter 1 Interrupt Enable bit position. */ ++ ++#define XCL_PEC21IE_bm 0x80 /* Peripheral High Counter 2 Interrupt Enable bit mask. */ ++#define XCL_PEC21IE_bp 7 /* Peripheral High Counter 2 Interrupt Enable bit position. */ ++ ++#define XCL_UNF0IE_bm 0x40 /* Underflow 0 Interrupt Enable bit mask. */ ++#define XCL_UNF0IE_bp 6 /* Underflow 0 Interrupt Enable bit position. */ ++ ++#define XCL_PEC0IE_bm 0x40 /* Peripheral Counter 0 Interrupt Enable bit mask. */ ++#define XCL_PEC0IE_bp 6 /* Peripheral Counter 0 Interrupt Enable bit position. */ ++ ++#define XCL_CC1IE_bm 0x20 /* Compare Or Capture 1 Interrupt Enable bit mask. */ ++#define XCL_CC1IE_bp 5 /* Compare Or Capture 1 Interrupt Enable bit position. */ ++ ++#define XCL_PEC20IE_bm 0x20 /* Peripheral Low Counter 2 Interrupt Enable bit mask. */ ++#define XCL_PEC20IE_bp 5 /* Peripheral Low Counter 2 Interrupt Enable bit position. */ ++ ++#define XCL_CC0IE_bm 0x10 /* Compare Or Capture 0 Interrupt Enable bit mask. */ ++#define XCL_CC0IE_bp 4 /* Compare Or Capture 0 Interrupt Enable bit position. */ ++ ++#define XCL_UNFINTLVL_gm 0x0C /* Timer Underflow Interrupt Level group mask. */ ++#define XCL_UNFINTLVL_gp 2 /* Timer Underflow Interrupt Level group position. */ ++#define XCL_UNFINTLVL0_bm (1<<2) /* Timer Underflow Interrupt Level bit 0 mask. */ ++#define XCL_UNFINTLVL0_bp 2 /* Timer Underflow Interrupt Level bit 0 position. */ ++#define XCL_UNFINTLVL1_bm (1<<3) /* Timer Underflow Interrupt Level bit 1 mask. */ ++#define XCL_UNFINTLVL1_bp 3 /* Timer Underflow Interrupt Level bit 1 position. */ ++ ++#define XCL_CCINTLVL_gm 0x03 /* Timer Compare or Capture Interrupt Level group mask. */ ++#define XCL_CCINTLVL_gp 0 /* Timer Compare or Capture Interrupt Level group position. */ ++#define XCL_CCINTLVL0_bm (1<<0) /* Timer Compare or Capture Interrupt Level bit 0 mask. */ ++#define XCL_CCINTLVL0_bp 0 /* Timer Compare or Capture Interrupt Level bit 0 position. */ ++#define XCL_CCINTLVL1_bm (1<<1) /* Timer Compare or Capture Interrupt Level bit 1 mask. */ ++#define XCL_CCINTLVL1_bp 1 /* Timer Compare or Capture Interrupt Level bit 1 position. */ ++ ++/* XCL.INTFLAGS bit masks and bit positions */ ++#define XCL_UNF1IF_bm 0x80 /* Timer/Counter 1 Underflow Interrupt Flag bit mask. */ ++#define XCL_UNF1IF_bp 7 /* Timer/Counter 1 Underflow Interrupt Flag bit position. */ ++ ++#define XCL_PEC1IF_bm 0x80 /* Peripheral Counter 1 Interrupt Flag bit mask. */ ++#define XCL_PEC1IF_bp 7 /* Peripheral Counter 1 Interrupt Flag bit position. */ ++ ++#define XCL_PEC21IF_bm 0x80 /* Peripheral High Counter 2 Interrupt Flag bit mask. */ ++#define XCL_PEC21IF_bp 7 /* Peripheral High Counter 2 Interrupt Flag bit position. */ ++ ++#define XCL_UNF0IF_bm 0x40 /* Timer/Counter 0 Underflow Interrupt Flag bit mask. */ ++#define XCL_UNF0IF_bp 6 /* Timer/Counter 0 Underflow Interrupt Flag bit position. */ ++ ++#define XCL_PEC0IF_bm 0x40 /* Peripheral Counter 0 Interrupt Flag bit mask. */ ++#define XCL_PEC0IF_bp 6 /* Peripheral Counter 0 Interrupt Flag bit position. */ ++ ++#define XCL_CC1IF_bm 0x20 /* Compare or Capture Channel 1 Interrupt Flag bit mask. */ ++#define XCL_CC1IF_bp 5 /* Compare or Capture Channel 1 Interrupt Flag bit position. */ ++ ++#define XCL_PEC20IF_bm 0x20 /* Peripheral Low Counter 2 Interrupt Flag bit mask. */ ++#define XCL_PEC20IF_bp 5 /* Peripheral Low Counter 2 Interrupt Flag bit position. */ ++ ++#define XCL_CC0IF_bm 0x10 /* Compare or Capture Channel 0 Interrupt Flag bit mask. */ ++#define XCL_CC0IF_bp 4 /* Compare or Capture Channel 0 Interrupt Flag bit position. */ ++ ++/* XCL.PLC bit masks and bit positions */ ++#define XCL_PLC_gm 0xFF /* Peripheral Lenght Control Bits group mask. */ ++#define XCL_PLC_gp 0 /* Peripheral Lenght Control Bits group position. */ ++#define XCL_PLC0_bm (1<<0) /* Peripheral Lenght Control Bits bit 0 mask. */ ++#define XCL_PLC0_bp 0 /* Peripheral Lenght Control Bits bit 0 position. */ ++#define XCL_PLC1_bm (1<<1) /* Peripheral Lenght Control Bits bit 1 mask. */ ++#define XCL_PLC1_bp 1 /* Peripheral Lenght Control Bits bit 1 position. */ ++#define XCL_PLC2_bm (1<<2) /* Peripheral Lenght Control Bits bit 2 mask. */ ++#define XCL_PLC2_bp 2 /* Peripheral Lenght Control Bits bit 2 position. */ ++#define XCL_PLC3_bm (1<<3) /* Peripheral Lenght Control Bits bit 3 mask. */ ++#define XCL_PLC3_bp 3 /* Peripheral Lenght Control Bits bit 3 position. */ ++#define XCL_PLC4_bm (1<<4) /* Peripheral Lenght Control Bits bit 4 mask. */ ++#define XCL_PLC4_bp 4 /* Peripheral Lenght Control Bits bit 4 position. */ ++#define XCL_PLC5_bm (1<<5) /* Peripheral Lenght Control Bits bit 5 mask. */ ++#define XCL_PLC5_bp 5 /* Peripheral Lenght Control Bits bit 5 position. */ ++#define XCL_PLC6_bm (1<<6) /* Peripheral Lenght Control Bits bit 6 mask. */ ++#define XCL_PLC6_bp 6 /* Peripheral Lenght Control Bits bit 6 position. */ ++#define XCL_PLC7_bm (1<<7) /* Peripheral Lenght Control Bits bit 7 mask. */ ++#define XCL_PLC7_bp 7 /* Peripheral Lenght Control Bits bit 7 position. */ ++ ++/* XCL.CNTL bit masks and bit positions */ ++#define XCL_BCNTO_gm 0xFF /* BTC0 Counter Byte group mask. */ ++#define XCL_BCNTO_gp 0 /* BTC0 Counter Byte group position. */ ++#define XCL_BCNTO0_bm (1<<0) /* BTC0 Counter Byte bit 0 mask. */ ++#define XCL_BCNTO0_bp 0 /* BTC0 Counter Byte bit 0 position. */ ++#define XCL_BCNTO1_bm (1<<1) /* BTC0 Counter Byte bit 1 mask. */ ++#define XCL_BCNTO1_bp 1 /* BTC0 Counter Byte bit 1 position. */ ++#define XCL_BCNTO2_bm (1<<2) /* BTC0 Counter Byte bit 2 mask. */ ++#define XCL_BCNTO2_bp 2 /* BTC0 Counter Byte bit 2 position. */ ++#define XCL_BCNTO3_bm (1<<3) /* BTC0 Counter Byte bit 3 mask. */ ++#define XCL_BCNTO3_bp 3 /* BTC0 Counter Byte bit 3 position. */ ++#define XCL_BCNTO4_bm (1<<4) /* BTC0 Counter Byte bit 4 mask. */ ++#define XCL_BCNTO4_bp 4 /* BTC0 Counter Byte bit 4 position. */ ++#define XCL_BCNTO5_bm (1<<5) /* BTC0 Counter Byte bit 5 mask. */ ++#define XCL_BCNTO5_bp 5 /* BTC0 Counter Byte bit 5 position. */ ++#define XCL_BCNTO6_bm (1<<6) /* BTC0 Counter Byte bit 6 mask. */ ++#define XCL_BCNTO6_bp 6 /* BTC0 Counter Byte bit 6 position. */ ++#define XCL_BCNTO7_bm (1<<7) /* BTC0 Counter Byte bit 7 mask. */ ++#define XCL_BCNTO7_bp 7 /* BTC0 Counter Byte bit 7 position. */ ++ ++#define XCL_CNTL_gm 0xFF /* TC16 Counter Low Byte group mask. */ ++#define XCL_CNTL_gp 0 /* TC16 Counter Low Byte group position. */ ++#define XCL_CNTL0_bm (1<<0) /* TC16 Counter Low Byte bit 0 mask. */ ++#define XCL_CNTL0_bp 0 /* TC16 Counter Low Byte bit 0 position. */ ++#define XCL_CNTL1_bm (1<<1) /* TC16 Counter Low Byte bit 1 mask. */ ++#define XCL_CNTL1_bp 1 /* TC16 Counter Low Byte bit 1 position. */ ++#define XCL_CNTL2_bm (1<<2) /* TC16 Counter Low Byte bit 2 mask. */ ++#define XCL_CNTL2_bp 2 /* TC16 Counter Low Byte bit 2 position. */ ++#define XCL_CNTL3_bm (1<<3) /* TC16 Counter Low Byte bit 3 mask. */ ++#define XCL_CNTL3_bp 3 /* TC16 Counter Low Byte bit 3 position. */ ++#define XCL_CNTL4_bm (1<<4) /* TC16 Counter Low Byte bit 4 mask. */ ++#define XCL_CNTL4_bp 4 /* TC16 Counter Low Byte bit 4 position. */ ++#define XCL_CNTL5_bm (1<<5) /* TC16 Counter Low Byte bit 5 mask. */ ++#define XCL_CNTL5_bp 5 /* TC16 Counter Low Byte bit 5 position. */ ++#define XCL_CNTL6_bm (1<<6) /* TC16 Counter Low Byte bit 6 mask. */ ++#define XCL_CNTL6_bp 6 /* TC16 Counter Low Byte bit 6 position. */ ++#define XCL_CNTL7_bm (1<<7) /* TC16 Counter Low Byte bit 7 mask. */ ++#define XCL_CNTL7_bp 7 /* TC16 Counter Low Byte bit 7 position. */ ++ ++#define XCL_PCNTO_gm 0xFF /* Peripheral Counter 0 Byte group mask. */ ++#define XCL_PCNTO_gp 0 /* Peripheral Counter 0 Byte group position. */ ++#define XCL_PCNTO0_bm (1<<0) /* Peripheral Counter 0 Byte bit 0 mask. */ ++#define XCL_PCNTO0_bp 0 /* Peripheral Counter 0 Byte bit 0 position. */ ++#define XCL_PCNTO1_bm (1<<1) /* Peripheral Counter 0 Byte bit 1 mask. */ ++#define XCL_PCNTO1_bp 1 /* Peripheral Counter 0 Byte bit 1 position. */ ++#define XCL_PCNTO2_bm (1<<2) /* Peripheral Counter 0 Byte bit 2 mask. */ ++#define XCL_PCNTO2_bp 2 /* Peripheral Counter 0 Byte bit 2 position. */ ++#define XCL_PCNTO3_bm (1<<3) /* Peripheral Counter 0 Byte bit 3 mask. */ ++#define XCL_PCNTO3_bp 3 /* Peripheral Counter 0 Byte bit 3 position. */ ++#define XCL_PCNTO4_bm (1<<4) /* Peripheral Counter 0 Byte bit 4 mask. */ ++#define XCL_PCNTO4_bp 4 /* Peripheral Counter 0 Byte bit 4 position. */ ++#define XCL_PCNTO5_bm (1<<5) /* Peripheral Counter 0 Byte bit 5 mask. */ ++#define XCL_PCNTO5_bp 5 /* Peripheral Counter 0 Byte bit 5 position. */ ++#define XCL_PCNTO6_bm (1<<6) /* Peripheral Counter 0 Byte bit 6 mask. */ ++#define XCL_PCNTO6_bp 6 /* Peripheral Counter 0 Byte bit 6 position. */ ++#define XCL_PCNTO7_bm (1<<7) /* Peripheral Counter 0 Byte bit 7 mask. */ ++#define XCL_PCNTO7_bp 7 /* Peripheral Counter 0 Byte bit 7 position. */ ++ ++/* XCL.CNTH bit masks and bit positions */ ++#define XCL_BCNT1_gm 0xFF /* BTC1 Counter Byte group mask. */ ++#define XCL_BCNT1_gp 0 /* BTC1 Counter Byte group position. */ ++#define XCL_BCNT10_bm (1<<0) /* BTC1 Counter Byte bit 0 mask. */ ++#define XCL_BCNT10_bp 0 /* BTC1 Counter Byte bit 0 position. */ ++#define XCL_BCNT11_bm (1<<1) /* BTC1 Counter Byte bit 1 mask. */ ++#define XCL_BCNT11_bp 1 /* BTC1 Counter Byte bit 1 position. */ ++#define XCL_BCNT12_bm (1<<2) /* BTC1 Counter Byte bit 2 mask. */ ++#define XCL_BCNT12_bp 2 /* BTC1 Counter Byte bit 2 position. */ ++#define XCL_BCNT13_bm (1<<3) /* BTC1 Counter Byte bit 3 mask. */ ++#define XCL_BCNT13_bp 3 /* BTC1 Counter Byte bit 3 position. */ ++#define XCL_BCNT14_bm (1<<4) /* BTC1 Counter Byte bit 4 mask. */ ++#define XCL_BCNT14_bp 4 /* BTC1 Counter Byte bit 4 position. */ ++#define XCL_BCNT15_bm (1<<5) /* BTC1 Counter Byte bit 5 mask. */ ++#define XCL_BCNT15_bp 5 /* BTC1 Counter Byte bit 5 position. */ ++#define XCL_BCNT16_bm (1<<6) /* BTC1 Counter Byte bit 6 mask. */ ++#define XCL_BCNT16_bp 6 /* BTC1 Counter Byte bit 6 position. */ ++#define XCL_BCNT17_bm (1<<7) /* BTC1 Counter Byte bit 7 mask. */ ++#define XCL_BCNT17_bp 7 /* BTC1 Counter Byte bit 7 position. */ ++ ++#define XCL_CNTH_gm 0xFF /* TC16 Counter High Byte group mask. */ ++#define XCL_CNTH_gp 0 /* TC16 Counter High Byte group position. */ ++#define XCL_CNTH0_bm (1<<0) /* TC16 Counter High Byte bit 0 mask. */ ++#define XCL_CNTH0_bp 0 /* TC16 Counter High Byte bit 0 position. */ ++#define XCL_CNTH1_bm (1<<1) /* TC16 Counter High Byte bit 1 mask. */ ++#define XCL_CNTH1_bp 1 /* TC16 Counter High Byte bit 1 position. */ ++#define XCL_CNTH2_bm (1<<2) /* TC16 Counter High Byte bit 2 mask. */ ++#define XCL_CNTH2_bp 2 /* TC16 Counter High Byte bit 2 position. */ ++#define XCL_CNTH3_bm (1<<3) /* TC16 Counter High Byte bit 3 mask. */ ++#define XCL_CNTH3_bp 3 /* TC16 Counter High Byte bit 3 position. */ ++#define XCL_CNTH4_bm (1<<4) /* TC16 Counter High Byte bit 4 mask. */ ++#define XCL_CNTH4_bp 4 /* TC16 Counter High Byte bit 4 position. */ ++#define XCL_CNTH5_bm (1<<5) /* TC16 Counter High Byte bit 5 mask. */ ++#define XCL_CNTH5_bp 5 /* TC16 Counter High Byte bit 5 position. */ ++#define XCL_CNTH6_bm (1<<6) /* TC16 Counter High Byte bit 6 mask. */ ++#define XCL_CNTH6_bp 6 /* TC16 Counter High Byte bit 6 position. */ ++#define XCL_CNTH7_bm (1<<7) /* TC16 Counter High Byte bit 7 mask. */ ++#define XCL_CNTH7_bp 7 /* TC16 Counter High Byte bit 7 position. */ ++ ++#define XCL_PCNT1_gm 0xFF /* Peripheral Counter 1 Byte group mask. */ ++#define XCL_PCNT1_gp 0 /* Peripheral Counter 1 Byte group position. */ ++#define XCL_PCNT10_bm (1<<0) /* Peripheral Counter 1 Byte bit 0 mask. */ ++#define XCL_PCNT10_bp 0 /* Peripheral Counter 1 Byte bit 0 position. */ ++#define XCL_PCNT11_bm (1<<1) /* Peripheral Counter 1 Byte bit 1 mask. */ ++#define XCL_PCNT11_bp 1 /* Peripheral Counter 1 Byte bit 1 position. */ ++#define XCL_PCNT12_bm (1<<2) /* Peripheral Counter 1 Byte bit 2 mask. */ ++#define XCL_PCNT12_bp 2 /* Peripheral Counter 1 Byte bit 2 position. */ ++#define XCL_PCNT13_bm (1<<3) /* Peripheral Counter 1 Byte bit 3 mask. */ ++#define XCL_PCNT13_bp 3 /* Peripheral Counter 1 Byte bit 3 position. */ ++#define XCL_PCNT14_bm (1<<4) /* Peripheral Counter 1 Byte bit 4 mask. */ ++#define XCL_PCNT14_bp 4 /* Peripheral Counter 1 Byte bit 4 position. */ ++#define XCL_PCNT15_bm (1<<5) /* Peripheral Counter 1 Byte bit 5 mask. */ ++#define XCL_PCNT15_bp 5 /* Peripheral Counter 1 Byte bit 5 position. */ ++#define XCL_PCNT16_bm (1<<6) /* Peripheral Counter 1 Byte bit 6 mask. */ ++#define XCL_PCNT16_bp 6 /* Peripheral Counter 1 Byte bit 6 position. */ ++#define XCL_PCNT17_bm (1<<7) /* Peripheral Counter 1 Byte bit 7 mask. */ ++#define XCL_PCNT17_bp 7 /* Peripheral Counter 1 Byte bit 7 position. */ ++ ++#define XCL_PCNT21_gm 0xF0 /* Peripheral High Counter 2 Bits group mask. */ ++#define XCL_PCNT21_gp 4 /* Peripheral High Counter 2 Bits group position. */ ++#define XCL_PCNT210_bm (1<<4) /* Peripheral High Counter 2 Bits bit 0 mask. */ ++#define XCL_PCNT210_bp 4 /* Peripheral High Counter 2 Bits bit 0 position. */ ++#define XCL_PCNT211_bm (1<<5) /* Peripheral High Counter 2 Bits bit 1 mask. */ ++#define XCL_PCNT211_bp 5 /* Peripheral High Counter 2 Bits bit 1 position. */ ++#define XCL_PCNT212_bm (1<<6) /* Peripheral High Counter 2 Bits bit 2 mask. */ ++#define XCL_PCNT212_bp 6 /* Peripheral High Counter 2 Bits bit 2 position. */ ++#define XCL_PCNT213_bm (1<<7) /* Peripheral High Counter 2 Bits bit 3 mask. */ ++#define XCL_PCNT213_bp 7 /* Peripheral High Counter 2 Bits bit 3 position. */ ++ ++#define XCL_PCNT20_gm 0x0F /* Peripheral Low Counter 2 Bits group mask. */ ++#define XCL_PCNT20_gp 0 /* Peripheral Low Counter 2 Bits group position. */ ++#define XCL_PCNT200_bm (1<<0) /* Peripheral Low Counter 2 Bits bit 0 mask. */ ++#define XCL_PCNT200_bp 0 /* Peripheral Low Counter 2 Bits bit 0 position. */ ++#define XCL_PCNT201_bm (1<<1) /* Peripheral Low Counter 2 Bits bit 1 mask. */ ++#define XCL_PCNT201_bp 1 /* Peripheral Low Counter 2 Bits bit 1 position. */ ++#define XCL_PCNT202_bm (1<<2) /* Peripheral Low Counter 2 Bits bit 2 mask. */ ++#define XCL_PCNT202_bp 2 /* Peripheral Low Counter 2 Bits bit 2 position. */ ++#define XCL_PCNT203_bm (1<<3) /* Peripheral Low Counter 2 Bits bit 3 mask. */ ++#define XCL_PCNT203_bp 3 /* Peripheral Low Counter 2 Bits bit 3 position. */ ++ ++/* XCL.CMPL bit masks and bit positions */ ++#define XCL_CMPL_gm 0xFF /* TC16 Compare Low Byte group mask. */ ++#define XCL_CMPL_gp 0 /* TC16 Compare Low Byte group position. */ ++#define XCL_CMPL0_bm (1<<0) /* TC16 Compare Low Byte bit 0 mask. */ ++#define XCL_CMPL0_bp 0 /* TC16 Compare Low Byte bit 0 position. */ ++#define XCL_CMPL1_bm (1<<1) /* TC16 Compare Low Byte bit 1 mask. */ ++#define XCL_CMPL1_bp 1 /* TC16 Compare Low Byte bit 1 position. */ ++#define XCL_CMPL2_bm (1<<2) /* TC16 Compare Low Byte bit 2 mask. */ ++#define XCL_CMPL2_bp 2 /* TC16 Compare Low Byte bit 2 position. */ ++#define XCL_CMPL3_bm (1<<3) /* TC16 Compare Low Byte bit 3 mask. */ ++#define XCL_CMPL3_bp 3 /* TC16 Compare Low Byte bit 3 position. */ ++#define XCL_CMPL4_bm (1<<4) /* TC16 Compare Low Byte bit 4 mask. */ ++#define XCL_CMPL4_bp 4 /* TC16 Compare Low Byte bit 4 position. */ ++#define XCL_CMPL5_bm (1<<5) /* TC16 Compare Low Byte bit 5 mask. */ ++#define XCL_CMPL5_bp 5 /* TC16 Compare Low Byte bit 5 position. */ ++#define XCL_CMPL6_bm (1<<6) /* TC16 Compare Low Byte bit 6 mask. */ ++#define XCL_CMPL6_bp 6 /* TC16 Compare Low Byte bit 6 position. */ ++#define XCL_CMPL7_bm (1<<7) /* TC16 Compare Low Byte bit 7 mask. */ ++#define XCL_CMPL7_bp 7 /* TC16 Compare Low Byte bit 7 position. */ ++ ++#define XCL_BCMP0_gm 0xFF /* BTC0 Compare Byte group mask. */ ++#define XCL_BCMP0_gp 0 /* BTC0 Compare Byte group position. */ ++#define XCL_BCMP00_bm (1<<0) /* BTC0 Compare Byte bit 0 mask. */ ++#define XCL_BCMP00_bp 0 /* BTC0 Compare Byte bit 0 position. */ ++#define XCL_BCMP01_bm (1<<1) /* BTC0 Compare Byte bit 1 mask. */ ++#define XCL_BCMP01_bp 1 /* BTC0 Compare Byte bit 1 position. */ ++#define XCL_BCMP02_bm (1<<2) /* BTC0 Compare Byte bit 2 mask. */ ++#define XCL_BCMP02_bp 2 /* BTC0 Compare Byte bit 2 position. */ ++#define XCL_BCMP03_bm (1<<3) /* BTC0 Compare Byte bit 3 mask. */ ++#define XCL_BCMP03_bp 3 /* BTC0 Compare Byte bit 3 position. */ ++#define XCL_BCMP04_bm (1<<4) /* BTC0 Compare Byte bit 4 mask. */ ++#define XCL_BCMP04_bp 4 /* BTC0 Compare Byte bit 4 position. */ ++#define XCL_BCMP05_bm (1<<5) /* BTC0 Compare Byte bit 5 mask. */ ++#define XCL_BCMP05_bp 5 /* BTC0 Compare Byte bit 5 position. */ ++#define XCL_BCMP06_bm (1<<6) /* BTC0 Compare Byte bit 6 mask. */ ++#define XCL_BCMP06_bp 6 /* BTC0 Compare Byte bit 6 position. */ ++#define XCL_BCMP07_bm (1<<7) /* BTC0 Compare Byte bit 7 mask. */ ++#define XCL_BCMP07_bp 7 /* BTC0 Compare Byte bit 7 position. */ ++ ++/* XCL.CMPH bit masks and bit positions */ ++#define XCL_CMPH_gm 0xFF /* TC16 Compare High Byte group mask. */ ++#define XCL_CMPH_gp 0 /* TC16 Compare High Byte group position. */ ++#define XCL_CMPH0_bm (1<<0) /* TC16 Compare High Byte bit 0 mask. */ ++#define XCL_CMPH0_bp 0 /* TC16 Compare High Byte bit 0 position. */ ++#define XCL_CMPH1_bm (1<<1) /* TC16 Compare High Byte bit 1 mask. */ ++#define XCL_CMPH1_bp 1 /* TC16 Compare High Byte bit 1 position. */ ++#define XCL_CMPH2_bm (1<<2) /* TC16 Compare High Byte bit 2 mask. */ ++#define XCL_CMPH2_bp 2 /* TC16 Compare High Byte bit 2 position. */ ++#define XCL_CMPH3_bm (1<<3) /* TC16 Compare High Byte bit 3 mask. */ ++#define XCL_CMPH3_bp 3 /* TC16 Compare High Byte bit 3 position. */ ++#define XCL_CMPH4_bm (1<<4) /* TC16 Compare High Byte bit 4 mask. */ ++#define XCL_CMPH4_bp 4 /* TC16 Compare High Byte bit 4 position. */ ++#define XCL_CMPH5_bm (1<<5) /* TC16 Compare High Byte bit 5 mask. */ ++#define XCL_CMPH5_bp 5 /* TC16 Compare High Byte bit 5 position. */ ++#define XCL_CMPH6_bm (1<<6) /* TC16 Compare High Byte bit 6 mask. */ ++#define XCL_CMPH6_bp 6 /* TC16 Compare High Byte bit 6 position. */ ++#define XCL_CMPH7_bm (1<<7) /* TC16 Compare High Byte bit 7 mask. */ ++#define XCL_CMPH7_bp 7 /* TC16 Compare High Byte bit 7 position. */ ++ ++#define XCL_BCMP1_gm 0xFF /* BTC1 Compare Byte group mask. */ ++#define XCL_BCMP1_gp 0 /* BTC1 Compare Byte group position. */ ++#define XCL_BCMP10_bm (1<<0) /* BTC1 Compare Byte bit 0 mask. */ ++#define XCL_BCMP10_bp 0 /* BTC1 Compare Byte bit 0 position. */ ++#define XCL_BCMP11_bm (1<<1) /* BTC1 Compare Byte bit 1 mask. */ ++#define XCL_BCMP11_bp 1 /* BTC1 Compare Byte bit 1 position. */ ++#define XCL_BCMP12_bm (1<<2) /* BTC1 Compare Byte bit 2 mask. */ ++#define XCL_BCMP12_bp 2 /* BTC1 Compare Byte bit 2 position. */ ++#define XCL_BCMP13_bm (1<<3) /* BTC1 Compare Byte bit 3 mask. */ ++#define XCL_BCMP13_bp 3 /* BTC1 Compare Byte bit 3 position. */ ++#define XCL_BCMP14_bm (1<<4) /* BTC1 Compare Byte bit 4 mask. */ ++#define XCL_BCMP14_bp 4 /* BTC1 Compare Byte bit 4 position. */ ++#define XCL_BCMP15_bm (1<<5) /* BTC1 Compare Byte bit 5 mask. */ ++#define XCL_BCMP15_bp 5 /* BTC1 Compare Byte bit 5 position. */ ++#define XCL_BCMP16_bm (1<<6) /* BTC1 Compare Byte bit 6 mask. */ ++#define XCL_BCMP16_bp 6 /* BTC1 Compare Byte bit 6 position. */ ++#define XCL_BCMP17_bm (1<<7) /* BTC1 Compare Byte bit 7 mask. */ ++#define XCL_BCMP17_bp 7 /* BTC1 Compare Byte bit 7 position. */ ++ ++/* XCL.PERCAPTL bit masks and bit positions */ ++#define XCL_PERL_gm 0xFF /* TC16 Low Byte Period group mask. */ ++#define XCL_PERL_gp 0 /* TC16 Low Byte Period group position. */ ++#define XCL_PERL0_bm (1<<0) /* TC16 Low Byte Period bit 0 mask. */ ++#define XCL_PERL0_bp 0 /* TC16 Low Byte Period bit 0 position. */ ++#define XCL_PERL1_bm (1<<1) /* TC16 Low Byte Period bit 1 mask. */ ++#define XCL_PERL1_bp 1 /* TC16 Low Byte Period bit 1 position. */ ++#define XCL_PERL2_bm (1<<2) /* TC16 Low Byte Period bit 2 mask. */ ++#define XCL_PERL2_bp 2 /* TC16 Low Byte Period bit 2 position. */ ++#define XCL_PERL3_bm (1<<3) /* TC16 Low Byte Period bit 3 mask. */ ++#define XCL_PERL3_bp 3 /* TC16 Low Byte Period bit 3 position. */ ++#define XCL_PERL4_bm (1<<4) /* TC16 Low Byte Period bit 4 mask. */ ++#define XCL_PERL4_bp 4 /* TC16 Low Byte Period bit 4 position. */ ++#define XCL_PERL5_bm (1<<5) /* TC16 Low Byte Period bit 5 mask. */ ++#define XCL_PERL5_bp 5 /* TC16 Low Byte Period bit 5 position. */ ++#define XCL_PERL6_bm (1<<6) /* TC16 Low Byte Period bit 6 mask. */ ++#define XCL_PERL6_bp 6 /* TC16 Low Byte Period bit 6 position. */ ++#define XCL_PERL7_bm (1<<7) /* TC16 Low Byte Period bit 7 mask. */ ++#define XCL_PERL7_bp 7 /* TC16 Low Byte Period bit 7 position. */ ++ ++#define XCL_CAPTL_gm 0xFF /* TC16 Capture Value Low Byte group mask. */ ++#define XCL_CAPTL_gp 0 /* TC16 Capture Value Low Byte group position. */ ++#define XCL_CAPTL0_bm (1<<0) /* TC16 Capture Value Low Byte bit 0 mask. */ ++#define XCL_CAPTL0_bp 0 /* TC16 Capture Value Low Byte bit 0 position. */ ++#define XCL_CAPTL1_bm (1<<1) /* TC16 Capture Value Low Byte bit 1 mask. */ ++#define XCL_CAPTL1_bp 1 /* TC16 Capture Value Low Byte bit 1 position. */ ++#define XCL_CAPTL2_bm (1<<2) /* TC16 Capture Value Low Byte bit 2 mask. */ ++#define XCL_CAPTL2_bp 2 /* TC16 Capture Value Low Byte bit 2 position. */ ++#define XCL_CAPTL3_bm (1<<3) /* TC16 Capture Value Low Byte bit 3 mask. */ ++#define XCL_CAPTL3_bp 3 /* TC16 Capture Value Low Byte bit 3 position. */ ++#define XCL_CAPTL4_bm (1<<4) /* TC16 Capture Value Low Byte bit 4 mask. */ ++#define XCL_CAPTL4_bp 4 /* TC16 Capture Value Low Byte bit 4 position. */ ++#define XCL_CAPTL5_bm (1<<5) /* TC16 Capture Value Low Byte bit 5 mask. */ ++#define XCL_CAPTL5_bp 5 /* TC16 Capture Value Low Byte bit 5 position. */ ++#define XCL_CAPTL6_bm (1<<6) /* TC16 Capture Value Low Byte bit 6 mask. */ ++#define XCL_CAPTL6_bp 6 /* TC16 Capture Value Low Byte bit 6 position. */ ++#define XCL_CAPTL7_bm (1<<7) /* TC16 Capture Value Low Byte bit 7 mask. */ ++#define XCL_CAPTL7_bp 7 /* TC16 Capture Value Low Byte bit 7 position. */ ++ ++#define XCL_BPER0_gm 0xFF /* BTC0 Period group mask. */ ++#define XCL_BPER0_gp 0 /* BTC0 Period group position. */ ++#define XCL_BPER00_bm (1<<0) /* BTC0 Period bit 0 mask. */ ++#define XCL_BPER00_bp 0 /* BTC0 Period bit 0 position. */ ++#define XCL_BPER01_bm (1<<1) /* BTC0 Period bit 1 mask. */ ++#define XCL_BPER01_bp 1 /* BTC0 Period bit 1 position. */ ++#define XCL_BPER02_bm (1<<2) /* BTC0 Period bit 2 mask. */ ++#define XCL_BPER02_bp 2 /* BTC0 Period bit 2 position. */ ++#define XCL_BPER03_bm (1<<3) /* BTC0 Period bit 3 mask. */ ++#define XCL_BPER03_bp 3 /* BTC0 Period bit 3 position. */ ++#define XCL_BPER04_bm (1<<4) /* BTC0 Period bit 4 mask. */ ++#define XCL_BPER04_bp 4 /* BTC0 Period bit 4 position. */ ++#define XCL_BPER05_bm (1<<5) /* BTC0 Period bit 5 mask. */ ++#define XCL_BPER05_bp 5 /* BTC0 Period bit 5 position. */ ++#define XCL_BPER06_bm (1<<6) /* BTC0 Period bit 6 mask. */ ++#define XCL_BPER06_bp 6 /* BTC0 Period bit 6 position. */ ++#define XCL_BPER07_bm (1<<7) /* BTC0 Period bit 7 mask. */ ++#define XCL_BPER07_bp 7 /* BTC0 Period bit 7 position. */ ++ ++#define XCL_BCAPT0_gm 0xFF /* BTC0 Capture Value Byte group mask. */ ++#define XCL_BCAPT0_gp 0 /* BTC0 Capture Value Byte group position. */ ++#define XCL_BCAPT00_bm (1<<0) /* BTC0 Capture Value Byte bit 0 mask. */ ++#define XCL_BCAPT00_bp 0 /* BTC0 Capture Value Byte bit 0 position. */ ++#define XCL_BCAPT01_bm (1<<1) /* BTC0 Capture Value Byte bit 1 mask. */ ++#define XCL_BCAPT01_bp 1 /* BTC0 Capture Value Byte bit 1 position. */ ++#define XCL_BCAPT02_bm (1<<2) /* BTC0 Capture Value Byte bit 2 mask. */ ++#define XCL_BCAPT02_bp 2 /* BTC0 Capture Value Byte bit 2 position. */ ++#define XCL_BCAPT03_bm (1<<3) /* BTC0 Capture Value Byte bit 3 mask. */ ++#define XCL_BCAPT03_bp 3 /* BTC0 Capture Value Byte bit 3 position. */ ++#define XCL_BCAPT04_bm (1<<4) /* BTC0 Capture Value Byte bit 4 mask. */ ++#define XCL_BCAPT04_bp 4 /* BTC0 Capture Value Byte bit 4 position. */ ++#define XCL_BCAPT05_bm (1<<5) /* BTC0 Capture Value Byte bit 5 mask. */ ++#define XCL_BCAPT05_bp 5 /* BTC0 Capture Value Byte bit 5 position. */ ++#define XCL_BCAPT06_bm (1<<6) /* BTC0 Capture Value Byte bit 6 mask. */ ++#define XCL_BCAPT06_bp 6 /* BTC0 Capture Value Byte bit 6 position. */ ++#define XCL_BCAPT07_bm (1<<7) /* BTC0 Capture Value Byte bit 7 mask. */ ++#define XCL_BCAPT07_bp 7 /* BTC0 Capture Value Byte bit 7 position. */ ++ ++/* XCL.PERCAPTH bit masks and bit positions */ ++#define XCL_PERH_gm 0xFF /* TC16 High Byte Period group mask. */ ++#define XCL_PERH_gp 0 /* TC16 High Byte Period group position. */ ++#define XCL_PERH0_bm (1<<0) /* TC16 High Byte Period bit 0 mask. */ ++#define XCL_PERH0_bp 0 /* TC16 High Byte Period bit 0 position. */ ++#define XCL_PERH1_bm (1<<1) /* TC16 High Byte Period bit 1 mask. */ ++#define XCL_PERH1_bp 1 /* TC16 High Byte Period bit 1 position. */ ++#define XCL_PERH2_bm (1<<2) /* TC16 High Byte Period bit 2 mask. */ ++#define XCL_PERH2_bp 2 /* TC16 High Byte Period bit 2 position. */ ++#define XCL_PERH3_bm (1<<3) /* TC16 High Byte Period bit 3 mask. */ ++#define XCL_PERH3_bp 3 /* TC16 High Byte Period bit 3 position. */ ++#define XCL_PERH4_bm (1<<4) /* TC16 High Byte Period bit 4 mask. */ ++#define XCL_PERH4_bp 4 /* TC16 High Byte Period bit 4 position. */ ++#define XCL_PERH5_bm (1<<5) /* TC16 High Byte Period bit 5 mask. */ ++#define XCL_PERH5_bp 5 /* TC16 High Byte Period bit 5 position. */ ++#define XCL_PERH6_bm (1<<6) /* TC16 High Byte Period bit 6 mask. */ ++#define XCL_PERH6_bp 6 /* TC16 High Byte Period bit 6 position. */ ++#define XCL_PERH7_bm (1<<7) /* TC16 High Byte Period bit 7 mask. */ ++#define XCL_PERH7_bp 7 /* TC16 High Byte Period bit 7 position. */ ++ ++#define XCL_CAPTH_gm 0xFF /* TC16 Capture Value High Byte group mask. */ ++#define XCL_CAPTH_gp 0 /* TC16 Capture Value High Byte group position. */ ++#define XCL_CAPTH0_bm (1<<0) /* TC16 Capture Value High Byte bit 0 mask. */ ++#define XCL_CAPTH0_bp 0 /* TC16 Capture Value High Byte bit 0 position. */ ++#define XCL_CAPTH1_bm (1<<1) /* TC16 Capture Value High Byte bit 1 mask. */ ++#define XCL_CAPTH1_bp 1 /* TC16 Capture Value High Byte bit 1 position. */ ++#define XCL_CAPTH2_bm (1<<2) /* TC16 Capture Value High Byte bit 2 mask. */ ++#define XCL_CAPTH2_bp 2 /* TC16 Capture Value High Byte bit 2 position. */ ++#define XCL_CAPTH3_bm (1<<3) /* TC16 Capture Value High Byte bit 3 mask. */ ++#define XCL_CAPTH3_bp 3 /* TC16 Capture Value High Byte bit 3 position. */ ++#define XCL_CAPTH4_bm (1<<4) /* TC16 Capture Value High Byte bit 4 mask. */ ++#define XCL_CAPTH4_bp 4 /* TC16 Capture Value High Byte bit 4 position. */ ++#define XCL_CAPTH5_bm (1<<5) /* TC16 Capture Value High Byte bit 5 mask. */ ++#define XCL_CAPTH5_bp 5 /* TC16 Capture Value High Byte bit 5 position. */ ++#define XCL_CAPTH6_bm (1<<6) /* TC16 Capture Value High Byte bit 6 mask. */ ++#define XCL_CAPTH6_bp 6 /* TC16 Capture Value High Byte bit 6 position. */ ++#define XCL_CAPTH7_bm (1<<7) /* TC16 Capture Value High Byte bit 7 mask. */ ++#define XCL_CAPTH7_bp 7 /* TC16 Capture Value High Byte bit 7 position. */ ++ ++#define XCL_BPER1_gm 0xFF /* BTC1 Period group mask. */ ++#define XCL_BPER1_gp 0 /* BTC1 Period group position. */ ++#define XCL_BPER10_bm (1<<0) /* BTC1 Period bit 0 mask. */ ++#define XCL_BPER10_bp 0 /* BTC1 Period bit 0 position. */ ++#define XCL_BPER11_bm (1<<1) /* BTC1 Period bit 1 mask. */ ++#define XCL_BPER11_bp 1 /* BTC1 Period bit 1 position. */ ++#define XCL_BPER12_bm (1<<2) /* BTC1 Period bit 2 mask. */ ++#define XCL_BPER12_bp 2 /* BTC1 Period bit 2 position. */ ++#define XCL_BPER13_bm (1<<3) /* BTC1 Period bit 3 mask. */ ++#define XCL_BPER13_bp 3 /* BTC1 Period bit 3 position. */ ++#define XCL_BPER14_bm (1<<4) /* BTC1 Period bit 4 mask. */ ++#define XCL_BPER14_bp 4 /* BTC1 Period bit 4 position. */ ++#define XCL_BPER15_bm (1<<5) /* BTC1 Period bit 5 mask. */ ++#define XCL_BPER15_bp 5 /* BTC1 Period bit 5 position. */ ++#define XCL_BPER16_bm (1<<6) /* BTC1 Period bit 6 mask. */ ++#define XCL_BPER16_bp 6 /* BTC1 Period bit 6 position. */ ++#define XCL_BPER17_bm (1<<7) /* BTC1 Period bit 7 mask. */ ++#define XCL_BPER17_bp 7 /* BTC1 Period bit 7 position. */ ++ ++#define XCL_BCAPT1_gm 0xFF /* BTC1 Capture Value Byte group mask. */ ++#define XCL_BCAPT1_gp 0 /* BTC1 Capture Value Byte group position. */ ++#define XCL_BCAPT10_bm (1<<0) /* BTC1 Capture Value Byte bit 0 mask. */ ++#define XCL_BCAPT10_bp 0 /* BTC1 Capture Value Byte bit 0 position. */ ++#define XCL_BCAPT11_bm (1<<1) /* BTC1 Capture Value Byte bit 1 mask. */ ++#define XCL_BCAPT11_bp 1 /* BTC1 Capture Value Byte bit 1 position. */ ++#define XCL_BCAPT12_bm (1<<2) /* BTC1 Capture Value Byte bit 2 mask. */ ++#define XCL_BCAPT12_bp 2 /* BTC1 Capture Value Byte bit 2 position. */ ++#define XCL_BCAPT13_bm (1<<3) /* BTC1 Capture Value Byte bit 3 mask. */ ++#define XCL_BCAPT13_bp 3 /* BTC1 Capture Value Byte bit 3 position. */ ++#define XCL_BCAPT14_bm (1<<4) /* BTC1 Capture Value Byte bit 4 mask. */ ++#define XCL_BCAPT14_bp 4 /* BTC1 Capture Value Byte bit 4 position. */ ++#define XCL_BCAPT15_bm (1<<5) /* BTC1 Capture Value Byte bit 5 mask. */ ++#define XCL_BCAPT15_bp 5 /* BTC1 Capture Value Byte bit 5 position. */ ++#define XCL_BCAPT16_bm (1<<6) /* BTC1 Capture Value Byte bit 6 mask. */ ++#define XCL_BCAPT16_bp 6 /* BTC1 Capture Value Byte bit 6 position. */ ++#define XCL_BCAPT17_bm (1<<7) /* BTC1 Capture Value Byte bit 7 mask. */ ++#define XCL_BCAPT17_bp 7 /* BTC1 Capture Value Byte bit 7 position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_BRIDGEEN_bm 0x80 /* Bridge Enable bit mask. */ ++#define TWI_BRIDGEEN_bp 7 /* Bridge Enable bit position. */ ++ ++#define TWI_SFMPEN_bm 0x40 /* Slave Fast Mode Plus Enable bit mask. */ ++#define TWI_SFMPEN_bp 6 /* Slave Fast Mode Plus Enable bit position. */ ++ ++#define TWI_SSDAHOLD_gm 0x30 /* Slave SDA Hold Time Enable group mask. */ ++#define TWI_SSDAHOLD_gp 4 /* Slave SDA Hold Time Enable group position. */ ++#define TWI_SSDAHOLD0_bm (1<<4) /* Slave SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SSDAHOLD0_bp 4 /* Slave SDA Hold Time Enable bit 0 position. */ ++#define TWI_SSDAHOLD1_bm (1<<5) /* Slave SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SSDAHOLD1_bp 5 /* Slave SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_FMPEN_bm 0x08 /* FMPLUS Enable bit mask. */ ++#define TWI_FMPEN_bp 3 /* FMPLUS Enable bit position. */ ++ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++#define TWI_MASTER_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ ++#define TWI_MASTER_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ ++ ++#define TWI_MASTER_TSEXTEN_bm 0x20 /* Slave Extend Timeout Enable bit mask. */ ++#define TWI_MASTER_TSEXTEN_bp 5 /* Slave Extend Timeout Enable bit position. */ ++ ++#define TWI_MASTER_TMEXTEN_bm 0x40 /* Master Extend Timeout Enable bit mask. */ ++#define TWI_MASTER_TMEXTEN_bp 6 /* Master Extend Timeout Enable bit position. */ ++ ++#define TWI_MASTER_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ ++#define TWI_MASTER_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++#define TWI_SLAVE_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ ++#define TWI_SLAVE_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ ++ ++#define TWI_SLAVE_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ ++#define TWI_SLAVE_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI_TIMEOUT.TOS bit masks and bit positions */ ++#define TWI_TIMEOUT_TTOUTMIF_bm 0x01 /* Master Ttimeout Interrupt Flag bit mask. */ ++#define TWI_TIMEOUT_TTOUTMIF_bp 0 /* Master Ttimeout Interrupt Flag bit position. */ ++ ++#define TWI_TIMEOUT_TSEXTIF_bm 0x02 /* Slave Extend Interrupt Flag bit mask. */ ++#define TWI_TIMEOUT_TSEXTIF_bp 1 /* Slave Extend Interrupt Flag bit position. */ ++ ++#define TWI_TIMEOUT_TMEXTIF_bm 0x04 /* Master Extend Interrupt Flag bit mask. */ ++#define TWI_TIMEOUT_TMEXTIF_bp 2 /* Master Extend Interrupt Flag bit position. */ ++ ++#define TWI_TIMEOUT_TTOUTSIF_bm 0x10 /* Slave Ttimeout Interrupt Flag bit mask. */ ++#define TWI_TIMEOUT_TTOUTSIF_bp 4 /* Slave Ttimeout Interrupt Flag bit position. */ ++ ++/* TWI_TIMEOUT.TOCONF bit masks and bit positions */ ++#define TWI_TIMEOUT_TTOUTMSEL_gm 0x07 /* Master Ttimeout Select group mask. */ ++#define TWI_TIMEOUT_TTOUTMSEL_gp 0 /* Master Ttimeout Select group position. */ ++#define TWI_TIMEOUT_TTOUTMSEL0_bm (1<<0) /* Master Ttimeout Select bit 0 mask. */ ++#define TWI_TIMEOUT_TTOUTMSEL0_bp 0 /* Master Ttimeout Select bit 0 position. */ ++#define TWI_TIMEOUT_TTOUTMSEL1_bm (1<<1) /* Master Ttimeout Select bit 1 mask. */ ++#define TWI_TIMEOUT_TTOUTMSEL1_bp 1 /* Master Ttimeout Select bit 1 position. */ ++#define TWI_TIMEOUT_TTOUTMSEL2_bm (1<<2) /* Master Ttimeout Select bit 2 mask. */ ++#define TWI_TIMEOUT_TTOUTMSEL2_bp 2 /* Master Ttimeout Select bit 2 position. */ ++ ++#define TWI_TIMEOUT_TMSEXTSEL_gm 0x18 /* Master/Slave Timeout Select group mask. */ ++#define TWI_TIMEOUT_TMSEXTSEL_gp 3 /* Master/Slave Timeout Select group position. */ ++#define TWI_TIMEOUT_TMSEXTSEL0_bm (1<<3) /* Master/Slave Timeout Select bit 0 mask. */ ++#define TWI_TIMEOUT_TMSEXTSEL0_bp 3 /* Master/Slave Timeout Select bit 0 position. */ ++#define TWI_TIMEOUT_TMSEXTSEL1_bm (1<<4) /* Master/Slave Timeout Select bit 1 mask. */ ++#define TWI_TIMEOUT_TMSEXTSEL1_bp 4 /* Master/Slave Timeout Select bit 1 position. */ ++ ++#define TWI_TIMEOUT_TTOUTSSEL_gm 0xE0 /* Slave Ttimeout Select group mask. */ ++#define TWI_TIMEOUT_TTOUTSSEL_gp 5 /* Slave Ttimeout Select group position. */ ++#define TWI_TIMEOUT_TTOUTSSEL0_bm (1<<5) /* Slave Ttimeout Select bit 0 mask. */ ++#define TWI_TIMEOUT_TTOUTSSEL0_bp 5 /* Slave Ttimeout Select bit 0 position. */ ++#define TWI_TIMEOUT_TTOUTSSEL1_bm (1<<6) /* Slave Ttimeout Select bit 1 mask. */ ++#define TWI_TIMEOUT_TTOUTSSEL1_bp 6 /* Slave Ttimeout Select bit 1 position. */ ++#define TWI_TIMEOUT_TTOUTSSEL2_bm (1<<7) /* Slave Ttimeout Select bit 2 mask. */ ++#define TWI_TIMEOUT_TTOUTSSEL2_bp 7 /* Slave Ttimeout Select bit 2 position. */ ++ ++/* PORT - Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INTLVL_gm 0x03 /* Port Interrupt Level group mask. */ ++#define PORT_INTLVL_gp 0 /* Port Interrupt Level group position. */ ++#define PORT_INTLVL0_bm (1<<0) /* Port Interrupt Level bit 0 mask. */ ++#define PORT_INTLVL0_bp 0 /* Port Interrupt Level bit 0 position. */ ++#define PORT_INTLVL1_bm (1<<1) /* Port Interrupt Level bit 1 mask. */ ++#define PORT_INTLVL1_bp 1 /* Port Interrupt Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT7IF_bm 0x80 /* Pin 7 Interrupt Flag bit mask. */ ++#define PORT_INT7IF_bp 7 /* Pin 7 Interrupt Flag bit position. */ ++ ++#define PORT_INT6IF_bm 0x40 /* Pin 6 Interrupt Flag bit mask. */ ++#define PORT_INT6IF_bp 6 /* Pin 6 Interrupt Flag bit position. */ ++ ++#define PORT_INT5IF_bm 0x20 /* Pin 5 Interrupt Flag bit mask. */ ++#define PORT_INT5IF_bp 5 /* Pin 5 Interrupt Flag bit position. */ ++ ++#define PORT_INT4IF_bm 0x10 /* Pin 4 Interrupt Flag bit mask. */ ++#define PORT_INT4IF_bp 4 /* Pin 4 Interrupt Flag bit position. */ ++ ++#define PORT_INT3IF_bm 0x08 /* Pin 3 Interrupt Flag bit mask. */ ++#define PORT_INT3IF_bp 3 /* Pin 3 Interrupt Flag bit position. */ ++ ++#define PORT_INT2IF_bm 0x04 /* Pin 2 Interrupt Flag bit mask. */ ++#define PORT_INT2IF_bp 2 /* Pin 2 Interrupt Flag bit position. */ ++ ++#define PORT_INT1IF_bm 0x02 /* Pin 1 Interrupt Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Pin 1 Interrupt Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Pin 0 Interrupt Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Pin 0 Interrupt Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_USART0_bm 0x10 /* Usart0 bit mask. */ ++#define PORT_USART0_bp 4 /* Usart0 bit position. */ ++ ++#define PORT_TC4D_bm 0x08 /* Timer/Counter 4 Output Compare D bit mask. */ ++#define PORT_TC4D_bp 3 /* Timer/Counter 4 Output Compare D bit position. */ ++ ++#define PORT_TC4C_bm 0x04 /* Timer/Counter 4 Output Compare C bit mask. */ ++#define PORT_TC4C_bp 2 /* Timer/Counter 4 Output Compare C bit position. */ ++ ++#define PORT_TC4B_bm 0x02 /* Timer/Counter 4 Output Compare B bit mask. */ ++#define PORT_TC4B_bp 1 /* Timer/Counter 4 Output Compare B bit position. */ ++ ++#define PORT_TC4A_bm 0x01 /* Timer/Counter 4 Output Compare A bit mask. */ ++#define PORT_TC4A_bp 0 /* Timer/Counter 4 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC4.CTRLA bit masks and bit positions */ ++#define TC4_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ ++#define TC4_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ ++ ++#define TC4_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ ++#define TC4_EVSTART_bp 5 /* Start on Next Event bit position. */ ++ ++#define TC4_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ ++#define TC4_UPSTOP_bp 4 /* Stop on Next Update bit position. */ ++ ++#define TC4_CLKSEL_gm 0x0F /* Clock Select group mask. */ ++#define TC4_CLKSEL_gp 0 /* Clock Select group position. */ ++#define TC4_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ ++#define TC4_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ ++#define TC4_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ ++#define TC4_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ ++#define TC4_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ ++#define TC4_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ ++#define TC4_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ ++#define TC4_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ ++ ++/* TC4.CTRLB bit masks and bit positions */ ++#define TC4_BYTEM_gm 0xC0 /* Byte Mode group mask. */ ++#define TC4_BYTEM_gp 6 /* Byte Mode group position. */ ++#define TC4_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ ++#define TC4_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ ++#define TC4_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ ++#define TC4_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ ++ ++#define TC4_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ ++#define TC4_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ ++#define TC4_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ ++#define TC4_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ ++#define TC4_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ ++#define TC4_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ ++ ++#define TC4_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ ++#define TC4_WGMODE_gp 0 /* Waveform Generation Mode group position. */ ++#define TC4_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ ++#define TC4_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ ++#define TC4_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ ++#define TC4_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ ++#define TC4_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ ++#define TC4_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ ++ ++/* TC4.CTRLC bit masks and bit positions */ ++#define TC4_POLD_bm 0x80 /* Channel D Output Polarity bit mask. */ ++#define TC4_POLD_bp 7 /* Channel D Output Polarity bit position. */ ++ ++#define TC4_POLC_bm 0x40 /* Channel C Output Polarity bit mask. */ ++#define TC4_POLC_bp 6 /* Channel C Output Polarity bit position. */ ++ ++#define TC4_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ ++#define TC4_POLB_bp 5 /* Channel B Output Polarity bit position. */ ++ ++#define TC4_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ ++#define TC4_POLA_bp 4 /* Channel A Output Polarity bit position. */ ++ ++#define TC4_CMPD_bm 0x08 /* Channel D Compare Output Value bit mask. */ ++#define TC4_CMPD_bp 3 /* Channel D Compare Output Value bit position. */ ++ ++#define TC4_CMPC_bm 0x04 /* Channel C Compare Output Value bit mask. */ ++#define TC4_CMPC_bp 2 /* Channel C Compare Output Value bit position. */ ++ ++#define TC4_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ ++#define TC4_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ ++ ++#define TC4_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ ++#define TC4_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ ++ ++#define TC4_HCMPD_bm 0x80 /* High Channel D Compare Output Value bit mask. */ ++#define TC4_HCMPD_bp 7 /* High Channel D Compare Output Value bit position. */ ++ ++#define TC4_HCMPC_bm 0x40 /* High Channel C Compare Output Value bit mask. */ ++#define TC4_HCMPC_bp 6 /* High Channel C Compare Output Value bit position. */ ++ ++#define TC4_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ ++#define TC4_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ ++ ++#define TC4_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ ++#define TC4_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ ++ ++#define TC4_LCMPD_bm 0x08 /* Low Channel D Compare Output Value bit mask. */ ++#define TC4_LCMPD_bp 3 /* Low Channel D Compare Output Value bit position. */ ++ ++#define TC4_LCMPC_bm 0x04 /* Low Channel C Compare Output Value bit mask. */ ++#define TC4_LCMPC_bp 2 /* Low Channel C Compare Output Value bit position. */ ++ ++#define TC4_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ ++#define TC4_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ ++ ++#define TC4_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ ++#define TC4_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ ++ ++/* TC4.CTRLD bit masks and bit positions */ ++#define TC4_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC4_EVACT_gp 5 /* Event Action group position. */ ++#define TC4_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC4_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC4_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC4_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC4_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC4_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC4_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC4_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC4_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC4_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC4_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC4_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC4_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC4_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC4_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC4_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC4_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC4_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC4.CTRLE bit masks and bit positions */ ++#define TC4_CCDMODE_gm 0xC0 /* Channel D Compare or Capture Mode group mask. */ ++#define TC4_CCDMODE_gp 6 /* Channel D Compare or Capture Mode group position. */ ++#define TC4_CCDMODE0_bm (1<<6) /* Channel D Compare or Capture Mode bit 0 mask. */ ++#define TC4_CCDMODE0_bp 6 /* Channel D Compare or Capture Mode bit 0 position. */ ++#define TC4_CCDMODE1_bm (1<<7) /* Channel D Compare or Capture Mode bit 1 mask. */ ++#define TC4_CCDMODE1_bp 7 /* Channel D Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_CCCMODE_gm 0x30 /* Channel C Compare or Capture Mode group mask. */ ++#define TC4_CCCMODE_gp 4 /* Channel C Compare or Capture Mode group position. */ ++#define TC4_CCCMODE0_bm (1<<4) /* Channel C Compare or Capture Mode bit 0 mask. */ ++#define TC4_CCCMODE0_bp 4 /* Channel C Compare or Capture Mode bit 0 position. */ ++#define TC4_CCCMODE1_bm (1<<5) /* Channel C Compare or Capture Mode bit 1 mask. */ ++#define TC4_CCCMODE1_bp 5 /* Channel C Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ ++#define TC4_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ ++#define TC4_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ ++#define TC4_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ ++#define TC4_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ ++#define TC4_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ ++#define TC4_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ ++#define TC4_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ ++#define TC4_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ ++#define TC4_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ ++#define TC4_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_LCCDMODE_gm 0xC0 /* Channel Low D Compare or Capture Mode group mask. */ ++#define TC4_LCCDMODE_gp 6 /* Channel Low D Compare or Capture Mode group position. */ ++#define TC4_LCCDMODE0_bm (1<<6) /* Channel Low D Compare or Capture Mode bit 0 mask. */ ++#define TC4_LCCDMODE0_bp 6 /* Channel Low D Compare or Capture Mode bit 0 position. */ ++#define TC4_LCCDMODE1_bm (1<<7) /* Channel Low D Compare or Capture Mode bit 1 mask. */ ++#define TC4_LCCDMODE1_bp 7 /* Channel Low D Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_LCCCMODE_gm 0x30 /* Channel Low C Compare or Capture Mode group mask. */ ++#define TC4_LCCCMODE_gp 4 /* Channel Low C Compare or Capture Mode group position. */ ++#define TC4_LCCCMODE0_bm (1<<4) /* Channel Low C Compare or Capture Mode bit 0 mask. */ ++#define TC4_LCCCMODE0_bp 4 /* Channel Low C Compare or Capture Mode bit 0 position. */ ++#define TC4_LCCCMODE1_bm (1<<5) /* Channel Low C Compare or Capture Mode bit 1 mask. */ ++#define TC4_LCCCMODE1_bp 5 /* Channel Low C Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ ++#define TC4_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ ++#define TC4_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ ++#define TC4_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ ++#define TC4_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ ++#define TC4_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ ++#define TC4_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ ++#define TC4_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ ++#define TC4_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ ++#define TC4_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ ++#define TC4_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ ++ ++/* TC4.CTRLF bit masks and bit positions */ ++#define TC4_HCCDMODE_gm 0xC0 /* Channel High D Compare or Capture Mode group mask. */ ++#define TC4_HCCDMODE_gp 6 /* Channel High D Compare or Capture Mode group position. */ ++#define TC4_HCCDMODE0_bm (1<<6) /* Channel High D Compare or Capture Mode bit 0 mask. */ ++#define TC4_HCCDMODE0_bp 6 /* Channel High D Compare or Capture Mode bit 0 position. */ ++#define TC4_HCCDMODE1_bm (1<<7) /* Channel High D Compare or Capture Mode bit 1 mask. */ ++#define TC4_HCCDMODE1_bp 7 /* Channel High D Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_HCCCMODE_gm 0x30 /* Channel High C Compare or Capture Mode group mask. */ ++#define TC4_HCCCMODE_gp 4 /* Channel High C Compare or Capture Mode group position. */ ++#define TC4_HCCCMODE0_bm (1<<4) /* Channel High C Compare or Capture Mode bit 0 mask. */ ++#define TC4_HCCCMODE0_bp 4 /* Channel High C Compare or Capture Mode bit 0 position. */ ++#define TC4_HCCCMODE1_bm (1<<5) /* Channel High C Compare or Capture Mode bit 1 mask. */ ++#define TC4_HCCCMODE1_bp 5 /* Channel High C Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ ++#define TC4_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ ++#define TC4_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ ++#define TC4_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ ++#define TC4_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ ++#define TC4_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ ++#define TC4_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ ++#define TC4_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ ++#define TC4_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ ++#define TC4_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ ++#define TC4_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ ++ ++/* TC4.INTCTRLA bit masks and bit positions */ ++#define TC4_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ ++#define TC4_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ ++#define TC4_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ ++#define TC4_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ ++#define TC4_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ ++#define TC4_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ ++ ++#define TC4_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ ++#define TC4_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ ++#define TC4_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ ++#define TC4_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ ++#define TC4_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ ++#define TC4_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ ++ ++#define TC4_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ ++#define TC4_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ ++#define TC4_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ ++#define TC4_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ ++#define TC4_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ ++#define TC4_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ ++ ++/* TC4.INTCTRLB bit masks and bit positions */ ++#define TC4_CCDINTLVL_gm 0xC0 /* Channel D Compare or Capture Interrupt Level group mask. */ ++#define TC4_CCDINTLVL_gp 6 /* Channel D Compare or Capture Interrupt Level group position. */ ++#define TC4_CCDINTLVL0_bm (1<<6) /* Channel D Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC4_CCDINTLVL0_bp 6 /* Channel D Compare or Capture Interrupt Level bit 0 position. */ ++#define TC4_CCDINTLVL1_bm (1<<7) /* Channel D Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC4_CCDINTLVL1_bp 7 /* Channel D Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC4_CCCINTLVL_gm 0x30 /* Channel C Compare or Capture Interrupt Level group mask. */ ++#define TC4_CCCINTLVL_gp 4 /* Channel C Compare or Capture Interrupt Level group position. */ ++#define TC4_CCCINTLVL0_bm (1<<4) /* Channel C Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC4_CCCINTLVL0_bp 4 /* Channel C Compare or Capture Interrupt Level bit 0 position. */ ++#define TC4_CCCINTLVL1_bm (1<<5) /* Channel C Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC4_CCCINTLVL1_bp 5 /* Channel C Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC4_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ ++#define TC4_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ ++#define TC4_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC4_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ ++#define TC4_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC4_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC4_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ ++#define TC4_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ ++#define TC4_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC4_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ ++#define TC4_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC4_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC4_LCCDINTLVL_gm 0xC0 /* Channel Low D Compare or Capture Interrupt Level group mask. */ ++#define TC4_LCCDINTLVL_gp 6 /* Channel Low D Compare or Capture Interrupt Level group position. */ ++#define TC4_LCCDINTLVL0_bm (1<<6) /* Channel Low D Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC4_LCCDINTLVL0_bp 6 /* Channel Low D Compare or Capture Interrupt Level bit 0 position. */ ++#define TC4_LCCDINTLVL1_bm (1<<7) /* Channel Low D Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC4_LCCDINTLVL1_bp 7 /* Channel Low D Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC4_LCCCINTLVL_gm 0x30 /* Channel Low C Compare or Capture Interrupt Level group mask. */ ++#define TC4_LCCCINTLVL_gp 4 /* Channel Low C Compare or Capture Interrupt Level group position. */ ++#define TC4_LCCCINTLVL0_bm (1<<4) /* Channel Low C Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC4_LCCCINTLVL0_bp 4 /* Channel Low C Compare or Capture Interrupt Level bit 0 position. */ ++#define TC4_LCCCINTLVL1_bm (1<<5) /* Channel Low C Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC4_LCCCINTLVL1_bp 5 /* Channel Low C Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC4_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ ++#define TC4_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ ++#define TC4_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC4_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ ++#define TC4_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC4_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC4_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ ++#define TC4_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ ++#define TC4_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC4_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ ++#define TC4_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC4_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ ++ ++/* TC4.CTRLGCLR bit masks and bit positions */ ++#define TC4_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ ++#define TC4_STOP_bp 5 /* Timer/Counter Stop bit position. */ ++ ++#define TC4_CMD_gm 0x0C /* Command group mask. */ ++#define TC4_CMD_gp 2 /* Command group position. */ ++#define TC4_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC4_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC4_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC4_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC4_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC4_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC4_DIR_bm 0x01 /* Counter Direction bit mask. */ ++#define TC4_DIR_bp 0 /* Counter Direction bit position. */ ++ ++/* TC4.CTRLGSET bit masks and bit positions */ ++/* TC4_STOP Predefined. */ ++/* TC4_STOP Predefined. */ ++ ++/* TC4_CMD Predefined. */ ++/* TC4_CMD Predefined. */ ++ ++/* TC4_LUPD Predefined. */ ++/* TC4_LUPD Predefined. */ ++ ++/* TC4_DIR Predefined. */ ++/* TC4_DIR Predefined. */ ++ ++/* TC4.CTRLHCLR bit masks and bit positions */ ++#define TC4_CCDBV_bm 0x10 /* Channel D Compare or Capture Buffer Valid bit mask. */ ++#define TC4_CCDBV_bp 4 /* Channel D Compare or Capture Buffer Valid bit position. */ ++ ++#define TC4_CCCBV_bm 0x08 /* Channel C Compare or Capture Buffer Valid bit mask. */ ++#define TC4_CCCBV_bp 3 /* Channel C Compare or Capture Buffer Valid bit position. */ ++ ++#define TC4_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ ++#define TC4_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ ++ ++#define TC4_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ ++#define TC4_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ ++ ++#define TC4_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC4_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++#define TC4_LCCDBV_bm 0x10 /* Channel Low D Compare or Capture Buffer Valid bit mask. */ ++#define TC4_LCCDBV_bp 4 /* Channel Low D Compare or Capture Buffer Valid bit position. */ ++ ++#define TC4_LCCCBV_bm 0x08 /* Channel Low C Compare or Capture Buffer Valid bit mask. */ ++#define TC4_LCCCBV_bp 3 /* Channel Low C Compare or Capture Buffer Valid bit position. */ ++ ++#define TC4_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ ++#define TC4_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ ++ ++#define TC4_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ ++#define TC4_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ ++ ++#define TC4_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ ++#define TC4_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ ++ ++/* TC4.CTRLHSET bit masks and bit positions */ ++/* TC4_CCDBV Predefined. */ ++/* TC4_CCDBV Predefined. */ ++ ++/* TC4_CCCBV Predefined. */ ++/* TC4_CCCBV Predefined. */ ++ ++/* TC4_CCBBV Predefined. */ ++/* TC4_CCBBV Predefined. */ ++ ++/* TC4_CCABV Predefined. */ ++/* TC4_CCABV Predefined. */ ++ ++/* TC4_PERBV Predefined. */ ++/* TC4_PERBV Predefined. */ ++ ++/* TC4_LCCDBV Predefined. */ ++/* TC4_LCCDBV Predefined. */ ++ ++/* TC4_LCCCBV Predefined. */ ++/* TC4_LCCCBV Predefined. */ ++ ++/* TC4_LCCBBV Predefined. */ ++/* TC4_LCCBBV Predefined. */ ++ ++/* TC4_LCCABV Predefined. */ ++/* TC4_LCCABV Predefined. */ ++ ++/* TC4_LPERBV Predefined. */ ++/* TC4_LPERBV Predefined. */ ++ ++/* TC4.INTFLAGS bit masks and bit positions */ ++#define TC4_CCDIF_bm 0x80 /* Channel D Compare or Capture Interrupt Flag bit mask. */ ++#define TC4_CCDIF_bp 7 /* Channel D Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC4_CCCIF_bm 0x40 /* Channel C Compare or Capture Interrupt Flag bit mask. */ ++#define TC4_CCCIF_bp 6 /* Channel C Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC4_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ ++#define TC4_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC4_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ ++#define TC4_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC4_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ ++#define TC4_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ ++ ++#define TC4_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC4_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC4_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ ++#define TC4_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ ++ ++#define TC4_LCCDIF_bm 0x80 /* Channel Low D Compare or Capture Interrupt Flag bit mask. */ ++#define TC4_LCCDIF_bp 7 /* Channel Low D Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC4_LCCCIF_bm 0x40 /* Channel Low C Compare or Capture Interrupt Flag bit mask. */ ++#define TC4_LCCCIF_bp 6 /* Channel Low C Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC4_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ ++#define TC4_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC4_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ ++#define TC4_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ ++ ++/* TC5.CTRLA bit masks and bit positions */ ++#define TC5_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ ++#define TC5_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ ++ ++#define TC5_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ ++#define TC5_EVSTART_bp 5 /* Start on Next Event bit position. */ ++ ++#define TC5_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ ++#define TC5_UPSTOP_bp 4 /* Stop on Next Update bit position. */ ++ ++#define TC5_CLKSEL_gm 0x0F /* Clock Select group mask. */ ++#define TC5_CLKSEL_gp 0 /* Clock Select group position. */ ++#define TC5_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ ++#define TC5_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ ++#define TC5_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ ++#define TC5_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ ++#define TC5_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ ++#define TC5_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ ++#define TC5_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ ++#define TC5_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ ++ ++/* TC5.CTRLB bit masks and bit positions */ ++#define TC5_BYTEM_gm 0xC0 /* Byte Mode group mask. */ ++#define TC5_BYTEM_gp 6 /* Byte Mode group position. */ ++#define TC5_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ ++#define TC5_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ ++#define TC5_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ ++#define TC5_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ ++ ++#define TC5_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ ++#define TC5_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ ++#define TC5_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ ++#define TC5_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ ++#define TC5_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ ++#define TC5_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ ++ ++#define TC5_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ ++#define TC5_WGMODE_gp 0 /* Waveform Generation Mode group position. */ ++#define TC5_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ ++#define TC5_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ ++#define TC5_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ ++#define TC5_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ ++#define TC5_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ ++#define TC5_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ ++ ++/* TC5.CTRLC bit masks and bit positions */ ++#define TC5_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ ++#define TC5_POLB_bp 5 /* Channel B Output Polarity bit position. */ ++ ++#define TC5_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ ++#define TC5_POLA_bp 4 /* Channel A Output Polarity bit position. */ ++ ++#define TC5_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ ++#define TC5_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ ++ ++#define TC5_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ ++#define TC5_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ ++ ++#define TC5_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ ++#define TC5_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ ++ ++#define TC5_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ ++#define TC5_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ ++ ++#define TC5_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ ++#define TC5_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ ++ ++#define TC5_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ ++#define TC5_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ ++ ++/* TC5.CTRLD bit masks and bit positions */ ++#define TC5_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC5_EVACT_gp 5 /* Event Action group position. */ ++#define TC5_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC5_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC5_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC5_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC5_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC5_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC5_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC5_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC5_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC5_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC5_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC5_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC5_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC5_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC5_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC5_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC5_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC5_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC5.CTRLE bit masks and bit positions */ ++#define TC5_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ ++#define TC5_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ ++#define TC5_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ ++#define TC5_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ ++#define TC5_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ ++#define TC5_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ ++ ++#define TC5_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ ++#define TC5_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ ++#define TC5_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ ++#define TC5_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ ++#define TC5_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ ++#define TC5_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ ++ ++#define TC5_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ ++#define TC5_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ ++#define TC5_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ ++#define TC5_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ ++#define TC5_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ ++#define TC5_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ ++ ++#define TC5_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ ++#define TC5_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ ++#define TC5_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ ++#define TC5_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ ++#define TC5_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ ++#define TC5_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ ++ ++/* TC5.CTRLF bit masks and bit positions */ ++#define TC5_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ ++#define TC5_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ ++#define TC5_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ ++#define TC5_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ ++#define TC5_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ ++#define TC5_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ ++ ++#define TC5_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ ++#define TC5_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ ++#define TC5_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ ++#define TC5_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ ++#define TC5_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ ++#define TC5_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ ++ ++/* TC5.INTCTRLA bit masks and bit positions */ ++#define TC5_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ ++#define TC5_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ ++#define TC5_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ ++#define TC5_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ ++#define TC5_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ ++#define TC5_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ ++ ++#define TC5_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ ++#define TC5_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ ++#define TC5_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ ++#define TC5_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ ++#define TC5_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ ++#define TC5_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ ++ ++#define TC5_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ ++#define TC5_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ ++#define TC5_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ ++#define TC5_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ ++#define TC5_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ ++#define TC5_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ ++ ++/* TC5.INTCTRLB bit masks and bit positions */ ++#define TC5_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ ++#define TC5_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ ++#define TC5_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC5_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ ++#define TC5_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC5_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC5_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ ++#define TC5_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ ++#define TC5_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC5_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ ++#define TC5_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC5_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC5_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ ++#define TC5_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ ++#define TC5_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC5_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ ++#define TC5_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC5_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC5_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ ++#define TC5_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ ++#define TC5_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC5_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ ++#define TC5_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC5_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ ++ ++/* TC5.CTRLGCLR bit masks and bit positions */ ++#define TC5_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ ++#define TC5_STOP_bp 5 /* Timer/Counter Stop bit position. */ ++ ++#define TC5_CMD_gm 0x0C /* Command group mask. */ ++#define TC5_CMD_gp 2 /* Command group position. */ ++#define TC5_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC5_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC5_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC5_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC5_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC5_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC5_DIR_bm 0x01 /* Counter Direction bit mask. */ ++#define TC5_DIR_bp 0 /* Counter Direction bit position. */ ++ ++/* TC5.CTRLGSET bit masks and bit positions */ ++/* TC5_STOP Predefined. */ ++/* TC5_STOP Predefined. */ ++ ++/* TC5_CMD Predefined. */ ++/* TC5_CMD Predefined. */ ++ ++/* TC5_LUPD Predefined. */ ++/* TC5_LUPD Predefined. */ ++ ++/* TC5_DIR Predefined. */ ++/* TC5_DIR Predefined. */ ++ ++/* TC5.CTRLHCLR bit masks and bit positions */ ++#define TC5_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ ++#define TC5_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ ++ ++#define TC5_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ ++#define TC5_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ ++ ++#define TC5_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC5_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++#define TC5_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ ++#define TC5_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ ++ ++#define TC5_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ ++#define TC5_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ ++ ++#define TC5_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ ++#define TC5_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ ++ ++/* TC5.CTRLHSET bit masks and bit positions */ ++/* TC5_CCBBV Predefined. */ ++/* TC5_CCBBV Predefined. */ ++ ++/* TC5_CCABV Predefined. */ ++/* TC5_CCABV Predefined. */ ++ ++/* TC5_PERBV Predefined. */ ++/* TC5_PERBV Predefined. */ ++ ++/* TC5_LCCBBV Predefined. */ ++/* TC5_LCCBBV Predefined. */ ++ ++/* TC5_LCCABV Predefined. */ ++/* TC5_LCCABV Predefined. */ ++ ++/* TC5_LPERBV Predefined. */ ++/* TC5_LPERBV Predefined. */ ++ ++/* TC5.INTFLAGS bit masks and bit positions */ ++#define TC5_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ ++#define TC5_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC5_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ ++#define TC5_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC5_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ ++#define TC5_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ ++ ++#define TC5_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC5_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC5_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ ++#define TC5_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ ++ ++#define TC5_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ ++#define TC5_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC5_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ ++#define TC5_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ ++ ++/* FAULT - Fault Extension */ ++/* FAULT.CTRLA bit masks and bit positions */ ++#define FAULT_RAMP_gm 0xC0 /* Ramp Mode Selection group mask. */ ++#define FAULT_RAMP_gp 6 /* Ramp Mode Selection group position. */ ++#define FAULT_RAMP0_bm (1<<6) /* Ramp Mode Selection bit 0 mask. */ ++#define FAULT_RAMP0_bp 6 /* Ramp Mode Selection bit 0 position. */ ++#define FAULT_RAMP1_bm (1<<7) /* Ramp Mode Selection bit 1 mask. */ ++#define FAULT_RAMP1_bp 7 /* Ramp Mode Selection bit 1 position. */ ++ ++#define FAULT_FDDBD_bm 0x20 /* Fault on Debug Break Detection bit mask. */ ++#define FAULT_FDDBD_bp 5 /* Fault on Debug Break Detection bit position. */ ++ ++#define FAULT_PORTCTRL_bm 0x10 /* Port Control Mode bit mask. */ ++#define FAULT_PORTCTRL_bp 4 /* Port Control Mode bit position. */ ++ ++#define FAULT_FUSE_bm 0x08 /* Fuse State bit mask. */ ++#define FAULT_FUSE_bp 3 /* Fuse State bit position. */ ++ ++#define FAULT_FILTERE_bm 0x04 /* Fault E Digital Filter Selection bit mask. */ ++#define FAULT_FILTERE_bp 2 /* Fault E Digital Filter Selection bit position. */ ++ ++#define FAULT_SRCE_gm 0x03 /* Fault E Input selection group mask. */ ++#define FAULT_SRCE_gp 0 /* Fault E Input selection group position. */ ++#define FAULT_SRCE0_bm (1<<0) /* Fault E Input selection bit 0 mask. */ ++#define FAULT_SRCE0_bp 0 /* Fault E Input selection bit 0 position. */ ++#define FAULT_SRCE1_bm (1<<1) /* Fault E Input selection bit 1 mask. */ ++#define FAULT_SRCE1_bp 1 /* Fault E Input selection bit 1 position. */ ++ ++/* FAULT.CTRLB bit masks and bit positions */ ++#define FAULT_SOFTA_bm 0x80 /* Fault A Software Mode bit mask. */ ++#define FAULT_SOFTA_bp 7 /* Fault A Software Mode bit position. */ ++ ++#define FAULT_HALTA_gm 0x60 /* Fault A Halt Action group mask. */ ++#define FAULT_HALTA_gp 5 /* Fault A Halt Action group position. */ ++#define FAULT_HALTA0_bm (1<<5) /* Fault A Halt Action bit 0 mask. */ ++#define FAULT_HALTA0_bp 5 /* Fault A Halt Action bit 0 position. */ ++#define FAULT_HALTA1_bm (1<<6) /* Fault A Halt Action bit 1 mask. */ ++#define FAULT_HALTA1_bp 6 /* Fault A Halt Action bit 1 position. */ ++ ++#define FAULT_RESTARTA_bm 0x10 /* Fault A Restart Action bit mask. */ ++#define FAULT_RESTARTA_bp 4 /* Fault A Restart Action bit position. */ ++ ++#define FAULT_KEEPA_bm 0x08 /* Fault A Keep Action bit mask. */ ++#define FAULT_KEEPA_bp 3 /* Fault A Keep Action bit position. */ ++ ++#define FAULT_SRCA_gm 0x03 /* Fault A Source Selection group mask. */ ++#define FAULT_SRCA_gp 0 /* Fault A Source Selection group position. */ ++#define FAULT_SRCA0_bm (1<<0) /* Fault A Source Selection bit 0 mask. */ ++#define FAULT_SRCA0_bp 0 /* Fault A Source Selection bit 0 position. */ ++#define FAULT_SRCA1_bm (1<<1) /* Fault A Source Selection bit 1 mask. */ ++#define FAULT_SRCA1_bp 1 /* Fault A Source Selection bit 1 position. */ ++ ++/* FAULT.CTRLC bit masks and bit positions */ ++#define FAULT_CAPTA_bm 0x20 /* Fault A Capture bit mask. */ ++#define FAULT_CAPTA_bp 5 /* Fault A Capture bit position. */ ++ ++#define FAULT_FILTERA_bm 0x04 /* Fault A Digital Filter Selection bit mask. */ ++#define FAULT_FILTERA_bp 2 /* Fault A Digital Filter Selection bit position. */ ++ ++#define FAULT_BLANKA_bm 0x02 /* Fault A Blanking bit mask. */ ++#define FAULT_BLANKA_bp 1 /* Fault A Blanking bit position. */ ++ ++#define FAULT_QUALA_bm 0x01 /* Fault A Qualification bit mask. */ ++#define FAULT_QUALA_bp 0 /* Fault A Qualification bit position. */ ++ ++/* FAULT.CTRLD bit masks and bit positions */ ++#define FAULT_SOFTB_bm 0x80 /* Fault B Software Mode bit mask. */ ++#define FAULT_SOFTB_bp 7 /* Fault B Software Mode bit position. */ ++ ++#define FAULT_HALTB_gm 0x60 /* Fault B Halt Action group mask. */ ++#define FAULT_HALTB_gp 5 /* Fault B Halt Action group position. */ ++#define FAULT_HALTB0_bm (1<<5) /* Fault B Halt Action bit 0 mask. */ ++#define FAULT_HALTB0_bp 5 /* Fault B Halt Action bit 0 position. */ ++#define FAULT_HALTB1_bm (1<<6) /* Fault B Halt Action bit 1 mask. */ ++#define FAULT_HALTB1_bp 6 /* Fault B Halt Action bit 1 position. */ ++ ++#define FAULT_RESTARTB_bm 0x10 /* Fault B Restart Action bit mask. */ ++#define FAULT_RESTARTB_bp 4 /* Fault B Restart Action bit position. */ ++ ++#define FAULT_KEEPB_bm 0x08 /* Fault B Keep Action bit mask. */ ++#define FAULT_KEEPB_bp 3 /* Fault B Keep Action bit position. */ ++ ++#define FAULT_SRCB_gm 0x03 /* Fault B Source Selection group mask. */ ++#define FAULT_SRCB_gp 0 /* Fault B Source Selection group position. */ ++#define FAULT_SRCB0_bm (1<<0) /* Fault B Source Selection bit 0 mask. */ ++#define FAULT_SRCB0_bp 0 /* Fault B Source Selection bit 0 position. */ ++#define FAULT_SRCB1_bm (1<<1) /* Fault B Source Selection bit 1 mask. */ ++#define FAULT_SRCB1_bp 1 /* Fault B Source Selection bit 1 position. */ ++ ++/* FAULT.CTRLE bit masks and bit positions */ ++#define FAULT_CAPTB_bm 0x20 /* Fault B Capture bit mask. */ ++#define FAULT_CAPTB_bp 5 /* Fault B Capture bit position. */ ++ ++#define FAULT_FILTERB_bm 0x04 /* Fault B Digital Filter Selection bit mask. */ ++#define FAULT_FILTERB_bp 2 /* Fault B Digital Filter Selection bit position. */ ++ ++#define FAULT_BLANKB_bm 0x02 /* Fault B Blanking bit mask. */ ++#define FAULT_BLANKB_bp 1 /* Fault B Blanking bit position. */ ++ ++#define FAULT_QUALB_bm 0x01 /* Fault B Qualification bit mask. */ ++#define FAULT_QUALB_bp 0 /* Fault B Qualification bit position. */ ++ ++/* FAULT.STATUS bit masks and bit positions */ ++#define FAULT_STATEB_bm 0x80 /* Fault B State bit mask. */ ++#define FAULT_STATEB_bp 7 /* Fault B State bit position. */ ++ ++#define FAULT_STATEA_bm 0x40 /* Fault A State bit mask. */ ++#define FAULT_STATEA_bp 6 /* Fault A State bit position. */ ++ ++#define FAULT_STATEE_bm 0x20 /* Fault E State bit mask. */ ++#define FAULT_STATEE_bp 5 /* Fault E State bit position. */ ++ ++#define FAULT_IDX_bm 0x08 /* Channel Index Flag bit mask. */ ++#define FAULT_IDX_bp 3 /* Channel Index Flag bit position. */ ++ ++#define FAULT_FAULTBIN_bm 0x04 /* Fault B Flag bit mask. */ ++#define FAULT_FAULTBIN_bp 2 /* Fault B Flag bit position. */ ++ ++#define FAULT_FAULTAIN_bm 0x02 /* Fault A Flag bit mask. */ ++#define FAULT_FAULTAIN_bp 1 /* Fault A Flag bit position. */ ++ ++#define FAULT_FAULTEIN_bm 0x01 /* Fault E Flag bit mask. */ ++#define FAULT_FAULTEIN_bp 0 /* Fault E Flag bit position. */ ++ ++/* FAULT.CTRLGCLR bit masks and bit positions */ ++#define FAULT_HALTBCLR_bm 0x80 /* State B Clear bit mask. */ ++#define FAULT_HALTBCLR_bp 7 /* State B Clear bit position. */ ++ ++#define FAULT_HALTACLR_bm 0x40 /* State A Clear bit mask. */ ++#define FAULT_HALTACLR_bp 6 /* State A Clear bit position. */ ++ ++#define FAULT_STATEECLR_bm 0x20 /* State E Clear bit mask. */ ++#define FAULT_STATEECLR_bp 5 /* State E Clear bit position. */ ++ ++#define FAULT_FAULTB_bm 0x04 /* Fault B Flag bit mask. */ ++#define FAULT_FAULTB_bp 2 /* Fault B Flag bit position. */ ++ ++#define FAULT_FAULTA_bm 0x02 /* Fault A Flag bit mask. */ ++#define FAULT_FAULTA_bp 1 /* Fault A Flag bit position. */ ++ ++#define FAULT_FAULTE_bm 0x01 /* Fault E Flag bit mask. */ ++#define FAULT_FAULTE_bp 0 /* Fault E Flag bit position. */ ++ ++/* FAULT.CTRLGSET bit masks and bit positions */ ++#define FAULT_FAULTBSW_bm 0x80 /* Software Fault B bit mask. */ ++#define FAULT_FAULTBSW_bp 7 /* Software Fault B bit position. */ ++ ++#define FAULT_FAULTASW_bm 0x40 /* Software Fault A bit mask. */ ++#define FAULT_FAULTASW_bp 6 /* Software Fault A bit position. */ ++ ++#define FAULT_FAULTESW_bm 0x20 /* Software Fault E bit mask. */ ++#define FAULT_FAULTESW_bp 5 /* Software Fault E bit position. */ ++ ++#define FAULT_IDXCMD_gm 0x18 /* Channel index Command group mask. */ ++#define FAULT_IDXCMD_gp 3 /* Channel index Command group position. */ ++#define FAULT_IDXCMD0_bm (1<<3) /* Channel index Command bit 0 mask. */ ++#define FAULT_IDXCMD0_bp 3 /* Channel index Command bit 0 position. */ ++#define FAULT_IDXCMD1_bm (1<<4) /* Channel index Command bit 1 mask. */ ++#define FAULT_IDXCMD1_bp 4 /* Channel index Command bit 1 position. */ ++ ++/* WEX - Waveform Extension */ ++/* WEX.CTRL bit masks and bit positions */ ++#define WEX_UPSEL_bm 0x80 /* Update Source Selection bit mask. */ ++#define WEX_UPSEL_bp 7 /* Update Source Selection bit position. */ ++ ++#define WEX_OTMX_gm 0x70 /* Output Matrix group mask. */ ++#define WEX_OTMX_gp 4 /* Output Matrix group position. */ ++#define WEX_OTMX0_bm (1<<4) /* Output Matrix bit 0 mask. */ ++#define WEX_OTMX0_bp 4 /* Output Matrix bit 0 position. */ ++#define WEX_OTMX1_bm (1<<5) /* Output Matrix bit 1 mask. */ ++#define WEX_OTMX1_bp 5 /* Output Matrix bit 1 position. */ ++#define WEX_OTMX2_bm (1<<6) /* Output Matrix bit 2 mask. */ ++#define WEX_OTMX2_bp 6 /* Output Matrix bit 2 position. */ ++ ++#define WEX_DTI3EN_bm 0x08 /* Dead-Time Insertion Generator 3 Enable bit mask. */ ++#define WEX_DTI3EN_bp 3 /* Dead-Time Insertion Generator 3 Enable bit position. */ ++ ++#define WEX_DTI2EN_bm 0x04 /* Dead-Time Insertion Generator 2 Enable bit mask. */ ++#define WEX_DTI2EN_bp 2 /* Dead-Time Insertion Generator 2 Enable bit position. */ ++ ++#define WEX_DTI1EN_bm 0x02 /* Dead-Time Insertion Generator 1 Enable bit mask. */ ++#define WEX_DTI1EN_bp 1 /* Dead-Time Insertion Generator 1 Enable bit position. */ ++ ++#define WEX_DTI0EN_bm 0x01 /* Dead-Time Insertion Generator 0 Enable bit mask. */ ++#define WEX_DTI0EN_bp 0 /* Dead-Time Insertion Generator 0 Enable bit position. */ ++ ++/* WEX.STATUSCLR bit masks and bit positions */ ++#define WEX_SWAPBUF_bm 0x04 /* Swap Buffer Valid bit mask. */ ++#define WEX_SWAPBUF_bp 2 /* Swap Buffer Valid bit position. */ ++ ++#define WEX_PGVBUFV_bm 0x02 /* Pattern Generator Value Buffer Valid bit mask. */ ++#define WEX_PGVBUFV_bp 1 /* Pattern Generator Value Buffer Valid bit position. */ ++ ++#define WEX_PGOBUFV_bm 0x01 /* Pattern Generator Overwrite Buffer Valid bit mask. */ ++#define WEX_PGOBUFV_bp 0 /* Pattern Generator Overwrite Buffer Valid bit position. */ ++ ++/* WEX.STATUSSET bit masks and bit positions */ ++/* WEX_SWAPBUF Predefined. */ ++/* WEX_SWAPBUF Predefined. */ ++ ++/* WEX_PGVBUFV Predefined. */ ++/* WEX_PGVBUFV Predefined. */ ++ ++/* WEX_PGOBUFV Predefined. */ ++/* WEX_PGOBUFV Predefined. */ ++ ++/* WEX.SWAP bit masks and bit positions */ ++#define WEX_SWAP3_bm 0x08 /* Swap DTI output pair 3 bit mask. */ ++#define WEX_SWAP3_bp 3 /* Swap DTI output pair 3 bit position. */ ++ ++#define WEX_SWAP2_bm 0x04 /* Swap DTI output pair 2 bit mask. */ ++#define WEX_SWAP2_bp 2 /* Swap DTI output pair 2 bit position. */ ++ ++#define WEX_SWAP1_bm 0x02 /* Swap DTI output pair 1 bit mask. */ ++#define WEX_SWAP1_bp 1 /* Swap DTI output pair 1 bit position. */ ++ ++#define WEX_SWAP0_bm 0x01 /* Swap DTI output pair 0 bit mask. */ ++#define WEX_SWAP0_bp 0 /* Swap DTI output pair 0 bit position. */ ++ ++/* WEX.SWAPBUF bit masks and bit positions */ ++#define WEX_SWAP3BUF_bm 0x08 /* Swap DTI output pair 3 bit mask. */ ++#define WEX_SWAP3BUF_bp 3 /* Swap DTI output pair 3 bit position. */ ++ ++#define WEX_SWAP2BUF_bm 0x04 /* Swap DTI output pair 2 bit mask. */ ++#define WEX_SWAP2BUF_bp 2 /* Swap DTI output pair 2 bit position. */ ++ ++#define WEX_SWAP1BUF_bm 0x02 /* Swap DTI output pair 1 bit mask. */ ++#define WEX_SWAP1BUF_bp 1 /* Swap DTI output pair 1 bit position. */ ++ ++#define WEX_SWAP0BUF_bm 0x01 /* Swap DTI output pair 0 bit mask. */ ++#define WEX_SWAP0BUF_bp 0 /* Swap DTI output pair 0 bit position. */ ++ ++/* HIRES - High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HRPLUS_gm 0x0C /* High Resolution Plus group mask. */ ++#define HIRES_HRPLUS_gp 2 /* High Resolution Plus group position. */ ++#define HIRES_HRPLUS0_bm (1<<2) /* High Resolution Plus bit 0 mask. */ ++#define HIRES_HRPLUS0_bp 2 /* High Resolution Plus bit 0 position. */ ++#define HIRES_HRPLUS1_bm (1<<3) /* High Resolution Plus bit 1 mask. */ ++#define HIRES_HRPLUS1_bp 3 /* High Resolution Plus bit 1 position. */ ++ ++#define HIRES_HREN_gm 0x03 /* High Resolution Mode group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Mode group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Mode bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Mode bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Mode bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Mode bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXSIF_bm 0x02 /* Receive Start Bit Interrupt Flag bit mask. */ ++#define USART_RXSIF_bp 1 /* Receive Start Bit Interrupt Flag bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++#define USART_DRIF_bm 0x01 /* Data Reception Flag bit mask. */ ++#define USART_DRIF_bp 0 /* Data Reception Flag bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXSIE_bm 0x80 /* Receive Start Interrupt Enable bit mask. */ ++#define USART_RXSIE_bp 7 /* Receive Start Interrupt Enable bit position. */ ++ ++#define USART_DRIE_bm 0x40 /* Data Reception Interrupt Enable bit mask. */ ++#define USART_DRIE_bp 6 /* Data Reception Interrupt Enable bit position. */ ++ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_ONEWIRE_bm 0x80 /* One Wire Mode bit mask. */ ++#define USART_ONEWIRE_bp 7 /* One Wire Mode bit position. */ ++ ++#define USART_SFDEN_bm 0x40 /* Start Frame Detection Enable bit mask. */ ++#define USART_SFDEN_bp 6 /* Start Frame Detection Enable bit position. */ ++ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.CTRLD bit masks and bit positions */ ++#define USART_DECTYPE_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_DECTYPE_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_DECTYPE0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_DECTYPE0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_DECTYPE1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_DECTYPE1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_LUTACT_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_LUTACT_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_LUTACT0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_LUTACT0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_LUTACT1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_LUTACT1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_PECACT_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_PECACT_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_PECACT0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_PECACT0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_PECACT1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_PECACT1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable SPI Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable SPI Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ ++#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit position. */ ++ ++#define SPI_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ ++#define SPI_TXCIE_bp 6 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit position. */ ++ ++#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit mask. */ ++#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit position. */ ++ ++#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit mask. */ ++#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit position. */ ++ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag (In Standard Mode Only). bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag (In Standard Mode Only). bit position. */ ++ ++#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ ++#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision Flag (In Standard Mode Only). bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision Flag (In Standard Mode Only). bit position. */ ++ ++#define SPI_TXCIF_bm 0x40 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ ++#define SPI_TXCIF_bp 6 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit position. */ ++ ++#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit mask. */ ++#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit position. */ ++ ++#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit mask. */ ++#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit position. */ ++ ++#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow (In Buffer Modes Only). bit mask. */ ++#define SPI_BUFOVF_bp 0 /* Buffer Overflow (In Buffer Modes Only). bit position. */ ++ ++/* SPI.CTRLB bit masks and bit positions */ ++#define SPI_BUFMODE_gm 0xC0 /* Buffer Modes group mask. */ ++#define SPI_BUFMODE_gp 6 /* Buffer Modes group position. */ ++#define SPI_BUFMODE0_bm (1<<6) /* Buffer Modes bit 0 mask. */ ++#define SPI_BUFMODE0_bp 6 /* Buffer Modes bit 0 position. */ ++#define SPI_BUFMODE1_bm (1<<7) /* Buffer Modes bit 1 mask. */ ++#define SPI_BUFMODE1_bp 7 /* Buffer Modes bit 1 position. */ ++ ++#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ ++#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* NVM_FUSES.FUSEBYTE6 bit masks and bit positions */ ++#define NVM_FUSES_FDACT5_bm 0x80 /* Fault Dectection Action on TC5 bit mask. */ ++#define NVM_FUSES_FDACT5_bp 7 /* Fault Dectection Action on TC5 bit position. */ ++ ++#define NVM_FUSES_FDACT4_bm 0x40 /* Fault Dectection Action on TC4 bit mask. */ ++#define NVM_FUSES_FDACT4_bp 6 /* Fault Dectection Action on TC4 bit position. */ ++ ++#define NVM_FUSES_VALUE_gm 0x3F /* Port Pin Value group mask. */ ++#define NVM_FUSES_VALUE_gp 0 /* Port Pin Value group position. */ ++#define NVM_FUSES_VALUE0_bm (1<<0) /* Port Pin Value bit 0 mask. */ ++#define NVM_FUSES_VALUE0_bp 0 /* Port Pin Value bit 0 position. */ ++#define NVM_FUSES_VALUE1_bm (1<<1) /* Port Pin Value bit 1 mask. */ ++#define NVM_FUSES_VALUE1_bp 1 /* Port Pin Value bit 1 position. */ ++#define NVM_FUSES_VALUE2_bm (1<<2) /* Port Pin Value bit 2 mask. */ ++#define NVM_FUSES_VALUE2_bp 2 /* Port Pin Value bit 2 position. */ ++#define NVM_FUSES_VALUE3_bm (1<<3) /* Port Pin Value bit 3 mask. */ ++#define NVM_FUSES_VALUE3_bp 3 /* Port Pin Value bit 3 position. */ ++#define NVM_FUSES_VALUE4_bm (1<<4) /* Port Pin Value bit 4 mask. */ ++#define NVM_FUSES_VALUE4_bp 4 /* Port Pin Value bit 4 position. */ ++#define NVM_FUSES_VALUE5_bm (1<<5) /* Port Pin Value bit 5 mask. */ ++#define NVM_FUSES_VALUE5_bp 5 /* Port Pin Value bit 5 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT_vect_num 2 ++#define PORTR_INT_vect _VECTOR(2) /* External Interrupt */ ++ ++/* EDMA interrupt vectors */ ++#define EDMA_CH0_vect_num 3 ++#define EDMA_CH0_vect _VECTOR(3) /* EDMA Channel 0 Interrupt */ ++#define EDMA_CH1_vect_num 4 ++#define EDMA_CH1_vect _VECTOR(4) /* EDMA Channel 1 Interrupt */ ++#define EDMA_CH2_vect_num 5 ++#define EDMA_CH2_vect _VECTOR(5) /* EDMA Channel 2 Interrupt */ ++#define EDMA_CH3_vect_num 6 ++#define EDMA_CH3_vect _VECTOR(6) /* EDMA Channel 3 Interrupt */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 7 ++#define RTC_OVF_vect _VECTOR(7) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 8 ++#define RTC_COMP_vect _VECTOR(8) /* Compare Interrupt */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT_vect_num 9 ++#define PORTC_INT_vect _VECTOR(9) /* External Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 10 ++#define TWIC_TWIS_vect _VECTOR(10) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 11 ++#define TWIC_TWIM_vect _VECTOR(11) /* TWI Master Interrupt */ ++ ++/* TCC4 interrupt vectors */ ++#define TCC4_OVF_vect_num 12 ++#define TCC4_OVF_vect _VECTOR(12) /* Overflow Interrupt */ ++#define TCC4_ERR_vect_num 13 ++#define TCC4_ERR_vect _VECTOR(13) /* Error Interrupt */ ++#define TCC4_CCA_vect_num 14 ++#define TCC4_CCA_vect _VECTOR(14) /* Channel A Compare or Capture Interrupt */ ++#define TCC4_CCB_vect_num 15 ++#define TCC4_CCB_vect _VECTOR(15) /* Channel B Compare or Capture Interrupt */ ++#define TCC4_CCC_vect_num 16 ++#define TCC4_CCC_vect _VECTOR(16) /* Channel C Compare or Capture Interrupt */ ++#define TCC4_CCD_vect_num 17 ++#define TCC4_CCD_vect _VECTOR(17) /* Channel D Compare or Capture Interrupt */ ++ ++/* TCC5 interrupt vectors */ ++#define TCC5_OVF_vect_num 18 ++#define TCC5_OVF_vect _VECTOR(18) /* Overflow Interrupt */ ++#define TCC5_ERR_vect_num 19 ++#define TCC5_ERR_vect _VECTOR(19) /* Error Interrupt */ ++#define TCC5_CCA_vect_num 20 ++#define TCC5_CCA_vect _VECTOR(20) /* Channel A Compare or Capture Interrupt */ ++#define TCC5_CCB_vect_num 21 ++#define TCC5_CCB_vect _VECTOR(21) /* Channel B Compare or Capture Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 22 ++#define SPIC_INT_vect _VECTOR(22) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 23 ++#define USARTC0_RXC_vect _VECTOR(23) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 24 ++#define USARTC0_DRE_vect _VECTOR(24) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 25 ++#define USARTC0_TXC_vect _VECTOR(25) /* Transmission Complete Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 26 ++#define NVM_EE_vect _VECTOR(26) /* EE Interrupt */ ++#define NVM_SPM_vect_num 27 ++#define NVM_SPM_vect _VECTOR(27) /* SPM Interrupt */ ++ ++/* XCL interrupt vectors */ ++#define XCL_UNF_vect_num 28 ++#define XCL_UNF_vect _VECTOR(28) /* Timer/Counter Underflow Interrupt */ ++#define XCL_CC_vect_num 29 ++#define XCL_CC_vect _VECTOR(29) /* Timer/Counter Compare or Capture Interrupt */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT_vect_num 30 ++#define PORTA_INT_vect _VECTOR(30) /* External Interrupt */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 31 ++#define ACA_AC0_vect _VECTOR(31) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 32 ++#define ACA_AC1_vect _VECTOR(32) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 33 ++#define ACA_ACW_vect _VECTOR(33) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 34 ++#define ADCA_CH0_vect _VECTOR(34) /* ADC Channel Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT_vect_num 35 ++#define PORTD_INT_vect _VECTOR(35) /* External Interrupt */ ++ ++/* TCD5 interrupt vectors */ ++#define TCD5_OVF_vect_num 36 ++#define TCD5_OVF_vect _VECTOR(36) /* Overflow Interrupt */ ++#define TCD5_ERR_vect_num 37 ++#define TCD5_ERR_vect _VECTOR(37) /* Error Interrupt */ ++#define TCD5_CCA_vect_num 38 ++#define TCD5_CCA_vect _VECTOR(38) /* Channel A Compare or Capture Interrupt */ ++#define TCD5_CCB_vect_num 39 ++#define TCD5_CCB_vect _VECTOR(39) /* Channel B Compare or Capture Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 40 ++#define USARTD0_RXC_vect _VECTOR(40) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 41 ++#define USARTD0_DRE_vect _VECTOR(41) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 42 ++#define USARTD0_TXC_vect _VECTOR(42) /* Transmission Complete Interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (43 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (20480) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (16384) ++#define APP_SECTION_PAGE_SIZE (128) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x3000) ++#define APPTABLE_SECTION_SIZE (4096) ++#define APPTABLE_SECTION_PAGE_SIZE (128) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x4000) ++#define BOOT_SECTION_SIZE (4096) ++#define BOOT_SECTION_PAGE_SIZE (128) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (10240) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (512) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (2048) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (512) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (7) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (128) ++#define USER_SIGNATURES_PAGE_SIZE (128) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (128) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 128 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 7 ++ ++/* Fuse Byte 0 Reserved */ ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* Fuse Byte 6 */ ++#define FUSE_VALUE0 (unsigned char)~_BV(0) /* Port Pin Value Bit 0 */ ++#define FUSE_VALUE1 (unsigned char)~_BV(1) /* Port Pin Value Bit 1 */ ++#define FUSE_VALUE2 (unsigned char)~_BV(2) /* Port Pin Value Bit 2 */ ++#define FUSE_VALUE3 (unsigned char)~_BV(3) /* Port Pin Value Bit 3 */ ++#define FUSE_VALUE4 (unsigned char)~_BV(4) /* Port Pin Value Bit 4 */ ++#define FUSE_VALUE5 (unsigned char)~_BV(5) /* Port Pin Value Bit 5 */ ++#define FUSE_FDACT4 (unsigned char)~_BV(6) /* Fault Dectection Action on TC4 */ ++#define FUSE_FDACT5 (unsigned char)~_BV(7) /* Fault Dectection Action on TC5 */ ++#define FUSE6_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x94 ++#define SIGNATURE_2 0x45 ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA16E5_H_INCLUDED */ ++ +diff --git a/include/avr/iox192a3.h b/include/avr/iox192a3.h +index 35e9b4e..957f3c8 100644 +--- a/include/avr/iox192a3.h ++++ b/include/avr/iox192a3.h +@@ -1,6917 +1,6917 @@ +-/* Copyright (c) 2009-2010 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iox192a3.h 2218 2011-02-21 19:43:03Z arcanum $ */ +- +-/* avr/iox192a3.h - definitions for ATxmega192A3 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iox192a3.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATxmega192A3_H_ +-#define _AVR_ATxmega192A3_H_ 1 +- +- +-/* Ungrouped common registers */ +-#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +-#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +-#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +-#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +-#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +-#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +-#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +-#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +-#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +-#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +-#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +-#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +-#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +-#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +-#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +-#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +- +-/* Deprecated */ +-#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +-#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +-#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +-#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +-#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +-#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +-#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +-#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +-#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +-#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +-#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +-#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +-#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +-#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +-#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +-#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +- +-#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +-#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +-#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +-#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +-#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +-#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +-#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +-#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +-#define SREG _SFR_MEM8(0x003F) /* Status Register */ +- +- +-/* C Language Only */ +-#if !defined (__ASSEMBLER__) +- +-#include +- +-typedef volatile uint8_t register8_t; +-typedef volatile uint16_t register16_t; +-typedef volatile uint32_t register32_t; +- +- +-#ifdef _WORDREGISTER +-#undef _WORDREGISTER +-#endif +-#define _WORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register16_t regname; \ +- struct \ +- { \ +- register8_t regname ## L; \ +- register8_t regname ## H; \ +- }; \ +- } +- +-#ifdef _DWORDREGISTER +-#undef _DWORDREGISTER +-#endif +-#define _DWORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register32_t regname; \ +- struct \ +- { \ +- register8_t regname ## 0; \ +- register8_t regname ## 1; \ +- register8_t regname ## 2; \ +- register8_t regname ## 3; \ +- }; \ +- } +- +- +-/* +-========================================================================== +-IO Module Structures +-========================================================================== +-*/ +- +- +-/* +--------------------------------------------------------------------------- +-XOCD - On-Chip Debug System +--------------------------------------------------------------------------- +-*/ +- +-/* On-Chip Debug System */ +-typedef struct OCD_struct +-{ +- register8_t OCDR0; /* OCD Register 0 */ +- register8_t OCDR1; /* OCD Register 1 */ +-} OCD_t; +- +- +-/* CCP signatures */ +-typedef enum CCP_enum +-{ +- CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ +- CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +-} CCP_t; +- +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Clock System */ +-typedef struct CLK_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t PSCTRL; /* Prescaler Control Register */ +- register8_t LOCK; /* Lock register */ +- register8_t RTCCTRL; /* RTC Control Register */ +-} CLK_t; +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Power Reduction */ +-typedef struct PR_struct +-{ +- register8_t PRGEN; /* General Power Reduction */ +- register8_t PRPA; /* Power Reduction Port A */ +- register8_t PRPB; /* Power Reduction Port B */ +- register8_t PRPC; /* Power Reduction Port C */ +- register8_t PRPD; /* Power Reduction Port D */ +- register8_t PRPE; /* Power Reduction Port E */ +- register8_t PRPF; /* Power Reduction Port F */ +-} PR_t; +- +-/* System Clock Selection */ +-typedef enum CLK_SCLKSEL_enum +-{ +- CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ +- CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ +- CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ +- CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ +- CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +-} CLK_SCLKSEL_t; +- +-/* Prescaler A Division Factor */ +-typedef enum CLK_PSADIV_enum +-{ +- CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ +- CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ +- CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ +- CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ +- CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ +- CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ +- CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ +- CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ +- CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ +- CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +-} CLK_PSADIV_t; +- +-/* Prescaler B and C Division Factor */ +-typedef enum CLK_PSBCDIV_enum +-{ +- CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ +- CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ +- CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ +- CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +-} CLK_PSBCDIV_t; +- +-/* RTC Clock Source */ +-typedef enum CLK_RTCSRC_enum +-{ +- CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ +- CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ +- CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ +- CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +-} CLK_RTCSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-SLEEP - Sleep Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Sleep Controller */ +-typedef struct SLEEP_struct +-{ +- register8_t CTRL; /* Control Register */ +-} SLEEP_t; +- +-/* Sleep Mode */ +-typedef enum SLEEP_SMODE_enum +-{ +- SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ +- SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +- SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ +- SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ +- SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +-} SLEEP_SMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-OSC - Oscillator +--------------------------------------------------------------------------- +-*/ +- +-/* Oscillator */ +-typedef struct OSC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t XOSCCTRL; /* External Oscillator Control Register */ +- register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ +- register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ +- register8_t PLLCTRL; /* PLL Control REgister */ +- register8_t DFLLCTRL; /* DFLL Control Register */ +-} OSC_t; +- +-/* Oscillator Frequency Range */ +-typedef enum OSC_FRQRANGE_enum +-{ +- OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ +- OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ +- OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ +- OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +-} OSC_FRQRANGE_t; +- +-/* External Oscillator Selection and Startup Time */ +-typedef enum OSC_XOSCSEL_enum +-{ +- OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ +- OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ +- OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ +- OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ +- OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +-} OSC_XOSCSEL_t; +- +-/* PLL Clock Source */ +-typedef enum OSC_PLLSRC_enum +-{ +- OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ +- OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ +- OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +-} OSC_PLLSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-DFLL - DFLL +--------------------------------------------------------------------------- +-*/ +- +-/* DFLL */ +-typedef struct DFLL_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t CALA; /* Calibration Register A */ +- register8_t CALB; /* Calibration Register B */ +- register8_t COMP0; /* Oscillator Compare Register 0 */ +- register8_t COMP1; /* Oscillator Compare Register 1 */ +- register8_t COMP2; /* Oscillator Compare Register 2 */ +- register8_t reserved_0x07; +-} DFLL_t; +- +- +-/* +--------------------------------------------------------------------------- +-RST - Reset +--------------------------------------------------------------------------- +-*/ +- +-/* Reset */ +-typedef struct RST_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t CTRL; /* Control Register */ +-} RST_t; +- +- +-/* +--------------------------------------------------------------------------- +-WDT - Watch-Dog Timer +--------------------------------------------------------------------------- +-*/ +- +-/* Watch-Dog Timer */ +-typedef struct WDT_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t WINCTRL; /* Windowed Mode Control */ +- register8_t STATUS; /* Status */ +-} WDT_t; +- +-/* Period setting */ +-typedef enum WDT_PER_enum +-{ +- WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ +- WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ +- WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ +- WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_PER_t; +- +-/* Closed window period */ +-typedef enum WDT_WPER_enum +-{ +- WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ +- WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ +- WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ +- WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_WPER_t; +- +- +-/* +--------------------------------------------------------------------------- +-MCU - MCU Control +--------------------------------------------------------------------------- +-*/ +- +-/* MCU Control */ +-typedef struct MCU_struct +-{ +- register8_t DEVID0; /* Device ID byte 0 */ +- register8_t DEVID1; /* Device ID byte 1 */ +- register8_t DEVID2; /* Device ID byte 2 */ +- register8_t REVID; /* Revision ID */ +- register8_t JTAGUID; /* JTAG User ID */ +- register8_t reserved_0x05; +- register8_t MCUCR; /* MCU Control */ +- register8_t reserved_0x07; +- register8_t EVSYSLOCK; /* Event System Lock */ +- register8_t AWEXLOCK; /* AWEX Lock */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +-} MCU_t; +- +- +-/* +--------------------------------------------------------------------------- +-PMIC - Programmable Multi-level Interrupt Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Programmable Multi-level Interrupt Controller */ +-typedef struct PMIC_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t INTPRI; /* Interrupt Priority */ +- register8_t CTRL; /* Control Register */ +-} PMIC_t; +- +- +-/* +--------------------------------------------------------------------------- +-DMA - DMA Controller +--------------------------------------------------------------------------- +-*/ +- +-/* DMA Channel */ +-typedef struct DMA_CH_struct +-{ +- register8_t CTRLA; /* Channel Control */ +- register8_t CTRLB; /* Channel Control */ +- register8_t ADDRCTRL; /* Address Control */ +- register8_t TRIGSRC; /* Channel Trigger Source */ +- _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ +- register8_t REPCNT; /* Channel Repeat Count */ +- register8_t reserved_0x07; +- register8_t SRCADDR0; /* Channel Source Address 0 */ +- register8_t SRCADDR1; /* Channel Source Address 1 */ +- register8_t SRCADDR2; /* Channel Source Address 2 */ +- register8_t reserved_0x0B; +- register8_t DESTADDR0; /* Channel Destination Address 0 */ +- register8_t DESTADDR1; /* Channel Destination Address 1 */ +- register8_t DESTADDR2; /* Channel Destination Address 2 */ +- register8_t reserved_0x0F; +-} DMA_CH_t; +- +-/* +--------------------------------------------------------------------------- +-DMA - DMA Controller +--------------------------------------------------------------------------- +-*/ +- +-/* DMA Controller */ +-typedef struct DMA_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t reserved_0x01; +- register8_t reserved_0x02; +- register8_t INTFLAGS; /* Transfer Interrupt Status */ +- register8_t STATUS; /* Status */ +- register8_t reserved_0x05; +- _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- DMA_CH_t CH0; /* DMA Channel 0 */ +- DMA_CH_t CH1; /* DMA Channel 1 */ +- DMA_CH_t CH2; /* DMA Channel 2 */ +- DMA_CH_t CH3; /* DMA Channel 3 */ +-} DMA_t; +- +-/* Burst mode */ +-typedef enum DMA_CH_BURSTLEN_enum +-{ +- DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ +- DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ +- DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ +- DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +-} DMA_CH_BURSTLEN_t; +- +-/* Source address reload mode */ +-typedef enum DMA_CH_SRCRELOAD_enum +-{ +- DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ +- DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ +- DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ +- DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +-} DMA_CH_SRCRELOAD_t; +- +-/* Source addressing mode */ +-typedef enum DMA_CH_SRCDIR_enum +-{ +- DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ +- DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ +- DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +-} DMA_CH_SRCDIR_t; +- +-/* Destination adress reload mode */ +-typedef enum DMA_CH_DESTRELOAD_enum +-{ +- DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ +- DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ +- DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ +- DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +-} DMA_CH_DESTRELOAD_t; +- +-/* Destination adressing mode */ +-typedef enum DMA_CH_DESTDIR_enum +-{ +- DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ +- DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ +- DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +-} DMA_CH_DESTDIR_t; +- +-/* Transfer trigger source */ +-typedef enum DMA_CH_TRIGSRC_enum +-{ +- DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ +- DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ +- DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ +- DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ +- DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ +- DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ +- DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ +- DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ +- DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ +- DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ +- DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ +- DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ +- DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ +- DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ +- DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ +- DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ +- DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ +- DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ +- DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ +- DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ +- DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ +- DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ +- DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ +- DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ +- DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ +- DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ +- DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ +- DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ +- DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ +- DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ +- DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ +- DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ +- DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ +- DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ +- DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ +- DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ +- DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ +- DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ +- DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +-} DMA_CH_TRIGSRC_t; +- +-/* Double buffering mode */ +-typedef enum DMA_DBUFMODE_enum +-{ +- DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ +- DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ +- DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ +- DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +-} DMA_DBUFMODE_t; +- +-/* Priority mode */ +-typedef enum DMA_PRIMODE_enum +-{ +- DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ +- DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ +- DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ +- DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +-} DMA_PRIMODE_t; +- +-/* Interrupt level */ +-typedef enum DMA_CH_ERRINTLVL_enum +-{ +- DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ +- DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ +- DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +-} DMA_CH_ERRINTLVL_t; +- +-/* Interrupt level */ +-typedef enum DMA_CH_TRNINTLVL_enum +-{ +- DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ +- DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ +- DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +-} DMA_CH_TRNINTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-EVSYS - Event System +--------------------------------------------------------------------------- +-*/ +- +-/* Event System */ +-typedef struct EVSYS_struct +-{ +- register8_t CH0MUX; /* Event Channel 0 Multiplexer */ +- register8_t CH1MUX; /* Event Channel 1 Multiplexer */ +- register8_t CH2MUX; /* Event Channel 2 Multiplexer */ +- register8_t CH3MUX; /* Event Channel 3 Multiplexer */ +- register8_t CH4MUX; /* Event Channel 4 Multiplexer */ +- register8_t CH5MUX; /* Event Channel 5 Multiplexer */ +- register8_t CH6MUX; /* Event Channel 6 Multiplexer */ +- register8_t CH7MUX; /* Event Channel 7 Multiplexer */ +- register8_t CH0CTRL; /* Channel 0 Control Register */ +- register8_t CH1CTRL; /* Channel 1 Control Register */ +- register8_t CH2CTRL; /* Channel 2 Control Register */ +- register8_t CH3CTRL; /* Channel 3 Control Register */ +- register8_t CH4CTRL; /* Channel 4 Control Register */ +- register8_t CH5CTRL; /* Channel 5 Control Register */ +- register8_t CH6CTRL; /* Channel 6 Control Register */ +- register8_t CH7CTRL; /* Channel 7 Control Register */ +- register8_t STROBE; /* Event Strobe */ +- register8_t DATA; /* Event Data */ +-} EVSYS_t; +- +-/* Quadrature Decoder Index Recognition Mode */ +-typedef enum EVSYS_QDIRM_enum +-{ +- EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ +- EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ +- EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ +- EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +-} EVSYS_QDIRM_t; +- +-/* Digital filter coefficient */ +-typedef enum EVSYS_DIGFILT_enum +-{ +- EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ +- EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ +- EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ +- EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ +- EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ +- EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ +- EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ +- EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +-} EVSYS_DIGFILT_t; +- +-/* Event Channel multiplexer input selection */ +-typedef enum EVSYS_CHMUX_enum +-{ +- EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ +- EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ +- EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ +- EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ +- EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ +- EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ +- EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ +- EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ +- EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ +- EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ +- EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ +- EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ +- EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ +- EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ +- EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ +- EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ +- EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ +- EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ +- EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ +- EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ +- EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ +- EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ +- EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ +- EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ +- EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ +- EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ +- EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ +- EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ +- EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ +- EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ +- EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ +- EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ +- EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ +- EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ +- EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ +- EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ +- EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ +- EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ +- EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ +- EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ +- EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ +- EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ +- EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ +- EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ +- EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ +- EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ +- EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ +- EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ +- EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ +- EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ +- EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ +- EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ +- EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ +- EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ +- EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ +- EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ +- EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ +- EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ +- EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ +- EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ +- EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ +- EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ +- EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ +- EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ +- EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ +- EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ +- EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ +- EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ +- EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ +- EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ +- EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ +- EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ +- EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ +- EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ +- EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ +- EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ +- EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ +- EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ +- EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ +- EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ +- EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ +- EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ +- EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ +- EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ +- EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ +- EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ +- EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ +- EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ +- EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ +- EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ +- EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ +- EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ +- EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ +- EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ +- EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ +- EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ +- EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ +- EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ +- EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ +- EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ +- EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ +- EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ +- EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ +- EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ +- EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ +- EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ +- EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ +- EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ +- EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ +- EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ +- EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +- EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ +- EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ +- EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ +- EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +-} EVSYS_CHMUX_t; +- +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Non-volatile Memory Controller */ +-typedef struct NVM_struct +-{ +- register8_t ADDR0; /* Address Register 0 */ +- register8_t ADDR1; /* Address Register 1 */ +- register8_t ADDR2; /* Address Register 2 */ +- register8_t reserved_0x03; +- register8_t DATA0; /* Data Register 0 */ +- register8_t DATA1; /* Data Register 1 */ +- register8_t DATA2; /* Data Register 2 */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t CMD; /* Command */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t INTCTRL; /* Interrupt Control */ +- register8_t reserved_0x0E; +- register8_t STATUS; /* Status */ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Lock Bits */ +-typedef struct NVM_LOCKBITS_struct +-{ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_LOCKBITS_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Fuses */ +-typedef struct NVM_FUSES_struct +-{ +- register8_t FUSEBYTE0; /* JTAG User ID */ +- register8_t FUSEBYTE1; /* Watchdog Configuration */ +- register8_t FUSEBYTE2; /* Reset Configuration */ +- register8_t reserved_0x03; +- register8_t FUSEBYTE4; /* Start-up Configuration */ +- register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +-} NVM_FUSES_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Production Signatures */ +-typedef struct NVM_PROD_SIGNATURES_struct +-{ +- register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ +- register8_t reserved_0x01; +- register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ +- register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ +- register8_t reserved_0x04; +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ +- register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ +- register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ +- register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ +- register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ +- register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t WAFNUM; /* Wafer Number */ +- register8_t reserved_0x11; +- register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ +- register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ +- register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ +- register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ +- register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ +- register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ +- register8_t reserved_0x26; +- register8_t reserved_0x27; +- register8_t reserved_0x28; +- register8_t reserved_0x29; +- register8_t reserved_0x2A; +- register8_t reserved_0x2B; +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ +- register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ +- register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ +- register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ +- register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ +- register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- register8_t reserved_0x36; +- register8_t reserved_0x37; +- register8_t reserved_0x38; +- register8_t reserved_0x39; +- register8_t reserved_0x3A; +- register8_t reserved_0x3B; +- register8_t reserved_0x3C; +- register8_t reserved_0x3D; +- register8_t reserved_0x3E; +-} NVM_PROD_SIGNATURES_t; +- +-/* NVM Command */ +-typedef enum NVM_CMD_enum +-{ +- NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ +- NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ +- NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ +- NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ +- NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ +- NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ +- NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ +- NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ +- NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ +- NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ +- NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ +- NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ +- NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ +- NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ +- NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ +- NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ +- NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ +- NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ +- NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ +- NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ +- NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ +- NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ +- NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ +- NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ +- NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ +- NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +-} NVM_CMD_t; +- +-/* SPM ready interrupt level */ +-typedef enum NVM_SPMLVL_enum +-{ +- NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ +- NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ +- NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +-} NVM_SPMLVL_t; +- +-/* EEPROM ready interrupt level */ +-typedef enum NVM_EELVL_enum +-{ +- NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ +- NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ +- NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +-} NVM_EELVL_t; +- +-/* Boot lock bits - boot setcion */ +-typedef enum NVM_BLBB_enum +-{ +- NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +- NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ +- NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ +- NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +-} NVM_BLBB_t; +- +-/* Boot lock bits - application section */ +-typedef enum NVM_BLBA_enum +-{ +- NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +- NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ +- NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ +- NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +-} NVM_BLBA_t; +- +-/* Boot lock bits - application table section */ +-typedef enum NVM_BLBAT_enum +-{ +- NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +- NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ +- NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ +- NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +-} NVM_BLBAT_t; +- +-/* Lock bits */ +-typedef enum NVM_LB_enum +-{ +- NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +- NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ +- NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +-} NVM_LB_t; +- +-/* Boot Loader Section Reset Vector */ +-typedef enum BOOTRST_enum +-{ +- BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ +- BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +-} BOOTRST_t; +- +-/* BOD operation */ +-typedef enum BOD_enum +-{ +- BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ +- BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ +- BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +-} BOD_t; +- +-/* Watchdog (Window) Timeout Period */ +-typedef enum WD_enum +-{ +- WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ +- WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ +- WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ +- WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ +- WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ +- WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ +- WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ +- WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ +- WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ +- WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ +- WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +-} WD_t; +- +-/* Start-up Time */ +-typedef enum SUT_enum +-{ +- SUT_0MS_gc = (0x03<<2), /* 0 ms */ +- SUT_4MS_gc = (0x01<<2), /* 4 ms */ +- SUT_64MS_gc = (0x00<<2), /* 64 ms */ +-} SUT_t; +- +-/* Brown Out Detection Voltage Level */ +-typedef enum BODLVL_enum +-{ +- BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ +- BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ +- BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ +- BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ +- BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ +- BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ +- BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ +-} BODLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-AC - Analog Comparator +--------------------------------------------------------------------------- +-*/ +- +-/* Analog Comparator */ +-typedef struct AC_struct +-{ +- register8_t AC0CTRL; /* Comparator 0 Control */ +- register8_t AC1CTRL; /* Comparator 1 Control */ +- register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ +- register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t WINCTRL; /* Window Mode Control */ +- register8_t STATUS; /* Status */ +-} AC_t; +- +-/* Interrupt mode */ +-typedef enum AC_INTMODE_enum +-{ +- AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ +- AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ +- AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +-} AC_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum AC_INTLVL_enum +-{ +- AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ +- AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ +- AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ +- AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +-} AC_INTLVL_t; +- +-/* Hysteresis mode selection */ +-typedef enum AC_HYSMODE_enum +-{ +- AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ +- AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ +- AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +-} AC_HYSMODE_t; +- +-/* Positive input multiplexer selection */ +-typedef enum AC_MUXPOS_enum +-{ +- AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ +- AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ +- AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ +- AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ +- AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ +- AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ +- AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +- AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +-} AC_MUXPOS_t; +- +-/* Negative input multiplexer selection */ +-typedef enum AC_MUXNEG_enum +-{ +- AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ +- AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ +- AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ +- AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ +- AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ +- AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ +- AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ +- AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +-} AC_MUXNEG_t; +- +-/* Windows interrupt mode */ +-typedef enum AC_WINTMODE_enum +-{ +- AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ +- AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ +- AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ +- AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +-} AC_WINTMODE_t; +- +-/* Window interrupt level */ +-typedef enum AC_WINTLVL_enum +-{ +- AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ +- AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ +- AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +-} AC_WINTLVL_t; +- +-/* Window mode state */ +-typedef enum AC_WSTATE_enum +-{ +- AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ +- AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ +- AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +-} AC_WSTATE_t; +- +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* ADC Channel */ +-typedef struct ADC_CH_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t MUXCTRL; /* MUX Control */ +- register8_t INTCTRL; /* Channel Interrupt Control */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- _WORDREGISTER(RES); /* Channel Result */ +- register8_t reserved_0x6; +- register8_t reserved_0x7; +-} ADC_CH_t; +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Analog-to-Digital Converter */ +-typedef struct ADC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t REFCTRL; /* Reference Control */ +- register8_t EVCTRL; /* Event Control */ +- register8_t PRESCALER; /* Clock Prescaler */ +- register8_t reserved_0x05; +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- _WORDREGISTER(CAL); /* Calibration Value */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- _WORDREGISTER(CH0RES); /* Channel 0 Result */ +- _WORDREGISTER(CH1RES); /* Channel 1 Result */ +- _WORDREGISTER(CH2RES); /* Channel 2 Result */ +- _WORDREGISTER(CH3RES); /* Channel 3 Result */ +- _WORDREGISTER(CMP); /* Compare Value */ +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- ADC_CH_t CH0; /* ADC Channel 0 */ +- ADC_CH_t CH1; /* ADC Channel 1 */ +- ADC_CH_t CH2; /* ADC Channel 2 */ +- ADC_CH_t CH3; /* ADC Channel 3 */ +-} ADC_t; +- +-/* Positive input multiplexer selection */ +-typedef enum ADC_CH_MUXPOS_enum +-{ +- ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ +- ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ +- ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ +- ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ +- ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ +- ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ +- ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ +- ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +-} ADC_CH_MUXPOS_t; +- +-/* Internal input multiplexer selections */ +-typedef enum ADC_CH_MUXINT_enum +-{ +- ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ +- ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ +- ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +- ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +-} ADC_CH_MUXINT_t; +- +-/* Negative input multiplexer selection */ +-typedef enum ADC_CH_MUXNEG_enum +-{ +- ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ +- ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ +- ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ +- ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ +- ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ +- ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ +- ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ +- ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +-} ADC_CH_MUXNEG_t; +- +-/* Input mode */ +-typedef enum ADC_CH_INPUTMODE_enum +-{ +- ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ +- ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ +- ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ +- ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +-} ADC_CH_INPUTMODE_t; +- +-/* Gain factor */ +-typedef enum ADC_CH_GAIN_enum +-{ +- ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ +- ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ +- ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ +- ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ +- ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ +- ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ +- ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ +-} ADC_CH_GAIN_t; +- +-/* Conversion result resolution */ +-typedef enum ADC_RESOLUTION_enum +-{ +- ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ +- ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ +- ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +-} ADC_RESOLUTION_t; +- +-/* Voltage reference selection */ +-typedef enum ADC_REFSEL_enum +-{ +- ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ +- ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ +- ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ +- ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +-} ADC_REFSEL_t; +- +-/* Channel sweep selection */ +-typedef enum ADC_SWEEP_enum +-{ +- ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ +- ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ +- ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ +- ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +-} ADC_SWEEP_t; +- +-/* Event channel input selection */ +-typedef enum ADC_EVSEL_enum +-{ +- ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ +- ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ +- ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ +- ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ +- ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ +- ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ +- ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ +- ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +-} ADC_EVSEL_t; +- +-/* Event action selection */ +-typedef enum ADC_EVACT_enum +-{ +- ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ +- ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ +- ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ +- ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ +- ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ +- ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ +- ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ +-} ADC_EVACT_t; +- +-/* Interupt mode */ +-typedef enum ADC_CH_INTMODE_enum +-{ +- ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ +- ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ +- ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +-} ADC_CH_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum ADC_CH_INTLVL_enum +-{ +- ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ +- ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ +- ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +-} ADC_CH_INTLVL_t; +- +-/* DMA request selection */ +-typedef enum ADC_DMASEL_enum +-{ +- ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ +- ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ +- ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ +- ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +-} ADC_DMASEL_t; +- +-/* Clock prescaler */ +-typedef enum ADC_PRESCALER_enum +-{ +- ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ +- ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ +- ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ +- ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ +- ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ +- ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ +- ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ +- ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +-} ADC_PRESCALER_t; +- +- +-/* +--------------------------------------------------------------------------- +-DAC - Digital/Analog Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Digital-to-Analog Converter */ +-typedef struct DAC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t EVCTRL; /* Event Input Control */ +- register8_t TIMCTRL; /* Timing Control */ +- register8_t STATUS; /* Status */ +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t GAINCAL; /* Gain Calibration */ +- register8_t OFFSETCAL; /* Offset Calibration */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- _WORDREGISTER(CH0DATA); /* Channel 0 Data */ +- _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +-} DAC_t; +- +-/* Output channel selection */ +-typedef enum DAC_CHSEL_enum +-{ +- DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ +- DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ +-} DAC_CHSEL_t; +- +-/* Reference voltage selection */ +-typedef enum DAC_REFSEL_enum +-{ +- DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ +- DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ +- DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ +- DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +-} DAC_REFSEL_t; +- +-/* Event channel selection */ +-typedef enum DAC_EVSEL_enum +-{ +- DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ +- DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ +- DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ +- DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ +- DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ +- DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ +- DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ +- DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +-} DAC_EVSEL_t; +- +-/* Conversion interval */ +-typedef enum DAC_CONINTVAL_enum +-{ +- DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ +- DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ +- DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ +- DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ +- DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ +- DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ +- DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ +- DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ +-} DAC_CONINTVAL_t; +- +-/* Refresh rate */ +-typedef enum DAC_REFRESH_enum +-{ +- DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ +- DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ +- DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ +- DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ +- DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ +- DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ +- DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ +- DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ +- DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ +- DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ +- DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ +- DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ +- DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ +- DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ +-} DAC_REFRESH_t; +- +- +-/* +--------------------------------------------------------------------------- +-RTC - Real-Time Clounter +--------------------------------------------------------------------------- +-*/ +- +-/* Real-Time Counter */ +-typedef struct RTC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t TEMP; /* Temporary register */ +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- _WORDREGISTER(CNT); /* Count Register */ +- _WORDREGISTER(PER); /* Period Register */ +- _WORDREGISTER(COMP); /* Compare Register */ +-} RTC_t; +- +-/* Prescaler Factor */ +-typedef enum RTC_PRESCALER_enum +-{ +- RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ +- RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ +- RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ +- RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ +- RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ +- RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ +- RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ +- RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +-} RTC_PRESCALER_t; +- +-/* Compare Interrupt level */ +-typedef enum RTC_COMPINTLVL_enum +-{ +- RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} RTC_COMPINTLVL_t; +- +-/* Overflow Interrupt level */ +-typedef enum RTC_OVFINTLVL_enum +-{ +- RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} RTC_OVFINTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* EBI Chip Select Module */ +-typedef struct EBI_CS_struct +-{ +- register8_t CTRLA; /* Chip Select Control Register A */ +- register8_t CTRLB; /* Chip Select Control Register B */ +- _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +-} EBI_CS_t; +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* External Bus Interface */ +-typedef struct EBI_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t SDRAMCTRLA; /* SDRAM Control Register A */ +- register8_t reserved_0x02; +- register8_t reserved_0x03; +- _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ +- _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ +- register8_t SDRAMCTRLB; /* SDRAM Control Register B */ +- register8_t SDRAMCTRLC; /* SDRAM Control Register C */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- EBI_CS_t CS0; /* Chip Select 0 */ +- EBI_CS_t CS1; /* Chip Select 1 */ +- EBI_CS_t CS2; /* Chip Select 2 */ +- EBI_CS_t CS3; /* Chip Select 3 */ +-} EBI_t; +- +-/* Chip Select adress space */ +-typedef enum EBI_CS_ASIZE_enum +-{ +- EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ +- EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ +- EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ +- EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ +- EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ +- EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ +- EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ +- EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ +- EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ +- EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ +- EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ +- EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ +- EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ +- EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ +- EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ +- EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ +- EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +-} EBI_CS_ASIZE_t; +- +-/* */ +-typedef enum EBI_CS_SRWS_enum +-{ +- EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_CS_SRWS_t; +- +-/* Chip Select address mode */ +-typedef enum EBI_CS_MODE_enum +-{ +- EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ +- EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ +- EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ +- EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +-} EBI_CS_MODE_t; +- +-/* Chip Select SDRAM mode */ +-typedef enum EBI_CS_SDMODE_enum +-{ +- EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ +- EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +-} EBI_CS_SDMODE_t; +- +-/* */ +-typedef enum EBI_SDDATAW_enum +-{ +- EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ +- EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +-} EBI_SDDATAW_t; +- +-/* */ +-typedef enum EBI_LPCMODE_enum +-{ +- EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ +- EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +-} EBI_LPCMODE_t; +- +-/* */ +-typedef enum EBI_SRMODE_enum +-{ +- EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ +- EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ +- EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ +- EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +-} EBI_SRMODE_t; +- +-/* */ +-typedef enum EBI_IFMODE_enum +-{ +- EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ +- EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ +- EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ +- EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +-} EBI_IFMODE_t; +- +-/* */ +-typedef enum EBI_SDCOL_enum +-{ +- EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ +- EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ +- EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ +- EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +-} EBI_SDCOL_t; +- +-/* */ +-typedef enum EBI_MRDLY_enum +-{ +- EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_MRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCYCDLY_enum +-{ +- EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ROWCYCDLY_t; +- +-/* */ +-typedef enum EBI_RPDLY_enum +-{ +- EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_RPDLY_t; +- +-/* */ +-typedef enum EBI_WRDLY_enum +-{ +- EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_WRDLY_t; +- +-/* */ +-typedef enum EBI_ESRDLY_enum +-{ +- EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ESRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCOLDLY_enum +-{ +- EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_ROWCOLDLY_t; +- +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_MASTER_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t STATUS; /* Status Register */ +- register8_t BAUD; /* Baurd Rate Control Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +-} TWI_MASTER_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_SLAVE_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t STATUS; /* Status Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +- register8_t ADDRMASK; /* Address Mask Register */ +-} TWI_SLAVE_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Two-Wire Interface */ +-typedef struct TWI_struct +-{ +- register8_t CTRL; /* TWI Common Control Register */ +- TWI_MASTER_t MASTER; /* TWI master module */ +- TWI_SLAVE_t SLAVE; /* TWI slave module */ +-} TWI_t; +- +-/* Master Interrupt Level */ +-typedef enum TWI_MASTER_INTLVL_enum +-{ +- TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_MASTER_INTLVL_t; +- +-/* Inactive Timeout */ +-typedef enum TWI_MASTER_TIMEOUT_enum +-{ +- TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ +- TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ +- TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ +- TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +-} TWI_MASTER_TIMEOUT_t; +- +-/* Master Command */ +-typedef enum TWI_MASTER_CMD_enum +-{ +- TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ +- TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ +- TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +-} TWI_MASTER_CMD_t; +- +-/* Master Bus State */ +-typedef enum TWI_MASTER_BUSSTATE_enum +-{ +- TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ +- TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ +- TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ +- TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +-} TWI_MASTER_BUSSTATE_t; +- +-/* Slave Interrupt Level */ +-typedef enum TWI_SLAVE_INTLVL_enum +-{ +- TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_SLAVE_INTLVL_t; +- +-/* Slave Command */ +-typedef enum TWI_SLAVE_CMD_enum +-{ +- TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ +- TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +-} TWI_SLAVE_CMD_t; +- +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O port Configuration */ +-typedef struct PORTCFG_struct +-{ +- register8_t MPCMASK; /* Multi-pin Configuration Mask */ +- register8_t reserved_0x01; +- register8_t VPCTRLA; /* Virtual Port Control Register A */ +- register8_t VPCTRLB; /* Virtual Port Control Register B */ +- register8_t CLKEVOUT; /* Clock and Event Out Register */ +-} PORTCFG_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* Virtual Port */ +-typedef struct VPORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t OUT; /* I/O Port Output */ +- register8_t IN; /* I/O Port Input */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +-} VPORT_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O Ports */ +-typedef struct PORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t DIRSET; /* I/O Port Data Direction Set */ +- register8_t DIRCLR; /* I/O Port Data Direction Clear */ +- register8_t DIRTGL; /* I/O Port Data Direction Toggle */ +- register8_t OUT; /* I/O Port Output */ +- register8_t OUTSET; /* I/O Port Output Set */ +- register8_t OUTCLR; /* I/O Port Output Clear */ +- register8_t OUTTGL; /* I/O Port Output Toggle */ +- register8_t IN; /* I/O port Input */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INT0MASK; /* Port Interrupt 0 Mask */ +- register8_t INT1MASK; /* Port Interrupt 1 Mask */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t PIN0CTRL; /* Pin 0 Control Register */ +- register8_t PIN1CTRL; /* Pin 1 Control Register */ +- register8_t PIN2CTRL; /* Pin 2 Control Register */ +- register8_t PIN3CTRL; /* Pin 3 Control Register */ +- register8_t PIN4CTRL; /* Pin 4 Control Register */ +- register8_t PIN5CTRL; /* Pin 5 Control Register */ +- register8_t PIN6CTRL; /* Pin 6 Control Register */ +- register8_t PIN7CTRL; /* Pin 7 Control Register */ +-} PORT_t; +- +-/* Virtual Port 0 Mapping */ +-typedef enum PORTCFG_VP0MAP_enum +-{ +- PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP0MAP_t; +- +-/* Virtual Port 1 Mapping */ +-typedef enum PORTCFG_VP1MAP_enum +-{ +- PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP1MAP_t; +- +-/* Virtual Port 2 Mapping */ +-typedef enum PORTCFG_VP2MAP_enum +-{ +- PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP2MAP_t; +- +-/* Virtual Port 3 Mapping */ +-typedef enum PORTCFG_VP3MAP_enum +-{ +- PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP3MAP_t; +- +-/* Clock Output Port */ +-typedef enum PORTCFG_CLKOUT_enum +-{ +- PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ +- PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ +- PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ +- PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +-} PORTCFG_CLKOUT_t; +- +-/* Event Output Port */ +-typedef enum PORTCFG_EVOUT_enum +-{ +- PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ +- PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ +- PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ +- PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +-} PORTCFG_EVOUT_t; +- +-/* Port Interrupt 0 Level */ +-typedef enum PORT_INT0LVL_enum +-{ +- PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ +- PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ +- PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +-} PORT_INT0LVL_t; +- +-/* Port Interrupt 1 Level */ +-typedef enum PORT_INT1LVL_enum +-{ +- PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ +- PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ +- PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +-} PORT_INT1LVL_t; +- +-/* Output/Pull Configuration */ +-typedef enum PORT_OPC_enum +-{ +- PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ +- PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ +- PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ +- PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ +- PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ +- PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ +- PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ +- PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +-} PORT_OPC_t; +- +-/* Input/Sense Configuration */ +-typedef enum PORT_ISC_enum +-{ +- PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ +- PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ +- PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ +- PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ +- PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +-} PORT_ISC_t; +- +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 0 */ +-typedef struct TC0_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- _WORDREGISTER(CCC); /* Compare or Capture C */ +- _WORDREGISTER(CCD); /* Compare or Capture D */ +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +- _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ +- _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +-} TC0_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 1 */ +-typedef struct TC1_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t reserved_0x2E; +- register8_t reserved_0x2F; +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +-} TC1_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* Advanced Waveform Extension */ +-typedef struct AWEX_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t FDEMASK; /* Fault Detection Event Mask */ +- register8_t FDCTRL; /* Fault Detection Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x05; +- register8_t DTBOTH; /* Dead Time Both Sides */ +- register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ +- register8_t DTLS; /* Dead Time Low Side */ +- register8_t DTHS; /* Dead Time High Side */ +- register8_t DTLSBUF; /* Dead Time Low Side Buffer */ +- register8_t DTHSBUF; /* Dead Time High Side Buffer */ +- register8_t OUTOVEN; /* Output Override Enable */ +-} AWEX_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* High-Resolution Extension */ +-typedef struct HIRES_struct +-{ +- register8_t CTRLA; /* Control Register */ +-} HIRES_t; +- +-/* Clock Selection */ +-typedef enum TC_CLKSEL_enum +-{ +- TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ +- TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ +- TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ +- TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ +- TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ +- TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ +- TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ +- TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ +- TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_CLKSEL_t; +- +-/* Waveform Generation Mode */ +-typedef enum TC_WGMODE_enum +-{ +- TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ +- TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ +- TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ +- TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ +- TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ +- TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +-} TC_WGMODE_t; +- +-/* Event Action */ +-typedef enum TC_EVACT_enum +-{ +- TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ +- TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ +- TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ +- TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ +- TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ +- TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */ +- TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +-} TC_EVACT_t; +- +-/* Event Selection */ +-typedef enum TC_EVSEL_enum +-{ +- TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_EVSEL_t; +- +-/* Error Interrupt Level */ +-typedef enum TC_ERRINTLVL_enum +-{ +- TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_ERRINTLVL_t; +- +-/* Overflow Interrupt Level */ +-typedef enum TC_OVFINTLVL_enum +-{ +- TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_OVFINTLVL_t; +- +-/* Compare or Capture D Interrupt Level */ +-typedef enum TC_CCDINTLVL_enum +-{ +- TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TC_CCDINTLVL_t; +- +-/* Compare or Capture C Interrupt Level */ +-typedef enum TC_CCCINTLVL_enum +-{ +- TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} TC_CCCINTLVL_t; +- +-/* Compare or Capture B Interrupt Level */ +-typedef enum TC_CCBINTLVL_enum +-{ +- TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_CCBINTLVL_t; +- +-/* Compare or Capture A Interrupt Level */ +-typedef enum TC_CCAINTLVL_enum +-{ +- TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_CCAINTLVL_t; +- +-/* Timer/Counter Command */ +-typedef enum TC_CMD_enum +-{ +- TC_CMD_NONE_gc = (0x00<<2), /* No Command */ +- TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ +- TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ +- TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +-} TC_CMD_t; +- +-/* Fault Detect Action */ +-typedef enum AWEX_FDACT_enum +-{ +- AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ +- AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ +- AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +-} AWEX_FDACT_t; +- +-/* High Resolution Enable */ +-typedef enum HIRES_HREN_enum +-{ +- HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ +- HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ +- HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ +- HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +-} HIRES_HREN_t; +- +- +-/* +--------------------------------------------------------------------------- +-USART - Universal Asynchronous Receiver-Transmitter +--------------------------------------------------------------------------- +-*/ +- +-/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +-typedef struct USART_struct +-{ +- register8_t DATA; /* Data Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x02; +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t BAUDCTRLA; /* Baud Rate Control Register A */ +- register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +-} USART_t; +- +-/* Receive Complete Interrupt level */ +-typedef enum USART_RXCINTLVL_enum +-{ +- USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} USART_RXCINTLVL_t; +- +-/* Transmit Complete Interrupt level */ +-typedef enum USART_TXCINTLVL_enum +-{ +- USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} USART_TXCINTLVL_t; +- +-/* Data Register Empty Interrupt level */ +-typedef enum USART_DREINTLVL_enum +-{ +- USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} USART_DREINTLVL_t; +- +-/* Character Size */ +-typedef enum USART_CHSIZE_enum +-{ +- USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ +- USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ +- USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ +- USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ +- USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +-} USART_CHSIZE_t; +- +-/* Communication Mode */ +-typedef enum USART_CMODE_enum +-{ +- USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ +- USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ +- USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ +- USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +-} USART_CMODE_t; +- +-/* Parity Mode */ +-typedef enum USART_PMODE_enum +-{ +- USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ +- USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ +- USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +-} USART_PMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-SPI - Serial Peripheral Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Serial Peripheral Interface */ +-typedef struct SPI_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t DATA; /* Data Register */ +-} SPI_t; +- +-/* SPI Mode */ +-typedef enum SPI_MODE_enum +-{ +- SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ +- SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ +- SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ +- SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +-} SPI_MODE_t; +- +-/* Prescaler setting */ +-typedef enum SPI_PRESCALER_enum +-{ +- SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ +- SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ +- SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ +- SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +-} SPI_PRESCALER_t; +- +-/* Interrupt level */ +-typedef enum SPI_INTLVL_enum +-{ +- SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} SPI_INTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-IRCOM - IR Communication Module +--------------------------------------------------------------------------- +-*/ +- +-/* IR Communication Module */ +-typedef struct IRCOM_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ +- register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +-} IRCOM_t; +- +-/* Event channel selection */ +-typedef enum IRDA_EVSEL_enum +-{ +- IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ +- IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ +- IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ +- IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +- IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ +- IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ +- IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ +- IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +-} IRDA_EVSEL_t; +- +- +-/* +--------------------------------------------------------------------------- +-AES - AES Module +--------------------------------------------------------------------------- +-*/ +- +-/* AES Module */ +-typedef struct AES_struct +-{ +- register8_t CTRL; /* AES Control Register */ +- register8_t STATUS; /* AES Status Register */ +- register8_t STATE; /* AES State Register */ +- register8_t KEY; /* AES Key Register */ +- register8_t INTCTRL; /* AES Interrupt Control Register */ +-} AES_t; +- +-/* Interrupt level */ +-typedef enum AES_INTLVL_enum +-{ +- AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} AES_INTLVL_t; +- +- +- +-/* +-========================================================================== +-IO Module Instances. Mapped to memory. +-========================================================================== +-*/ +- +-#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +-#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +-#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +-#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +-#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +-#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +-#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +-#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +-#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +-#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +-#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +-#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +-#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +-#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +-#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +-#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +-#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ +-#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +-#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +-#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +-#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +-#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ +-#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ +-#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +-#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ +-#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +-#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +-#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ +-#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +-#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +-#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +-#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +-#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +-#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ +-#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +-#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +-#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +-#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +-#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +-#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +-#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ +-#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +-#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +-#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +-#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ +-#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ +-#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +-#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ +-#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +-#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +-#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ +-#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ +-#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ +-#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ +-#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ +-#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ +-#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ +-#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ +-#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ +-#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ +-#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ +- +- +-#endif /* !defined (__ASSEMBLER__) */ +- +- +-/* ========== Flattened fully qualified IO register names ========== */ +- +-/* GPIO - General Purpose IO Registers */ +-#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +-#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +-#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +-#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +-#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +-#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +-#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +-#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +-#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +-#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +-#define GPIO_GPIORA _SFR_MEM8(0x000A) +-#define GPIO_GPIORB _SFR_MEM8(0x000B) +-#define GPIO_GPIORC _SFR_MEM8(0x000C) +-#define GPIO_GPIORD _SFR_MEM8(0x000D) +-#define GPIO_GPIORE _SFR_MEM8(0x000E) +-#define GPIO_GPIORF _SFR_MEM8(0x000F) +- +-/* Deprecated */ +-#define GPIO_GPIO0 _SFR_MEM8(0x0000) +-#define GPIO_GPIO1 _SFR_MEM8(0x0001) +-#define GPIO_GPIO2 _SFR_MEM8(0x0002) +-#define GPIO_GPIO3 _SFR_MEM8(0x0003) +-#define GPIO_GPIO4 _SFR_MEM8(0x0004) +-#define GPIO_GPIO5 _SFR_MEM8(0x0005) +-#define GPIO_GPIO6 _SFR_MEM8(0x0006) +-#define GPIO_GPIO7 _SFR_MEM8(0x0007) +-#define GPIO_GPIO8 _SFR_MEM8(0x0008) +-#define GPIO_GPIO9 _SFR_MEM8(0x0009) +-#define GPIO_GPIOA _SFR_MEM8(0x000A) +-#define GPIO_GPIOB _SFR_MEM8(0x000B) +-#define GPIO_GPIOC _SFR_MEM8(0x000C) +-#define GPIO_GPIOD _SFR_MEM8(0x000D) +-#define GPIO_GPIOE _SFR_MEM8(0x000E) +-#define GPIO_GPIOF _SFR_MEM8(0x000F) +- +-/* VPORT0 - Virtual Port 0 */ +-#define VPORT0_DIR _SFR_MEM8(0x0010) +-#define VPORT0_OUT _SFR_MEM8(0x0011) +-#define VPORT0_IN _SFR_MEM8(0x0012) +-#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) +- +-/* VPORT1 - Virtual Port 1 */ +-#define VPORT1_DIR _SFR_MEM8(0x0014) +-#define VPORT1_OUT _SFR_MEM8(0x0015) +-#define VPORT1_IN _SFR_MEM8(0x0016) +-#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) +- +-/* VPORT2 - Virtual Port 2 */ +-#define VPORT2_DIR _SFR_MEM8(0x0018) +-#define VPORT2_OUT _SFR_MEM8(0x0019) +-#define VPORT2_IN _SFR_MEM8(0x001A) +-#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) +- +-/* VPORT3 - Virtual Port 3 */ +-#define VPORT3_DIR _SFR_MEM8(0x001C) +-#define VPORT3_OUT _SFR_MEM8(0x001D) +-#define VPORT3_IN _SFR_MEM8(0x001E) +-#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) +- +-/* OCD - On-Chip Debug System */ +-#define OCD_OCDR0 _SFR_MEM8(0x002E) +-#define OCD_OCDR1 _SFR_MEM8(0x002F) +- +-/* CPU - CPU Registers */ +-#define CPU_CCP _SFR_MEM8(0x0034) +-#define CPU_RAMPD _SFR_MEM8(0x0038) +-#define CPU_RAMPX _SFR_MEM8(0x0039) +-#define CPU_RAMPY _SFR_MEM8(0x003A) +-#define CPU_RAMPZ _SFR_MEM8(0x003B) +-#define CPU_EIND _SFR_MEM8(0x003C) +-#define CPU_SPL _SFR_MEM8(0x003D) +-#define CPU_SPH _SFR_MEM8(0x003E) +-#define CPU_SREG _SFR_MEM8(0x003F) +- +-/* CLK - Clock System */ +-#define CLK_CTRL _SFR_MEM8(0x0040) +-#define CLK_PSCTRL _SFR_MEM8(0x0041) +-#define CLK_LOCK _SFR_MEM8(0x0042) +-#define CLK_RTCCTRL _SFR_MEM8(0x0043) +- +-/* SLEEP - Sleep Controller */ +-#define SLEEP_CTRL _SFR_MEM8(0x0048) +- +-/* OSC - Oscillator Control */ +-#define OSC_CTRL _SFR_MEM8(0x0050) +-#define OSC_STATUS _SFR_MEM8(0x0051) +-#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +-#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +-#define OSC_RC32KCAL _SFR_MEM8(0x0054) +-#define OSC_PLLCTRL _SFR_MEM8(0x0055) +-#define OSC_DFLLCTRL _SFR_MEM8(0x0056) +- +-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +-#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +-#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +-#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +-#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +-#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +-#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) +- +-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +-#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +-#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +-#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +-#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +-#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +-#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) +- +-/* PR - Power Reduction */ +-#define PR_PRGEN _SFR_MEM8(0x0070) +-#define PR_PRPA _SFR_MEM8(0x0071) +-#define PR_PRPB _SFR_MEM8(0x0072) +-#define PR_PRPC _SFR_MEM8(0x0073) +-#define PR_PRPD _SFR_MEM8(0x0074) +-#define PR_PRPE _SFR_MEM8(0x0075) +-#define PR_PRPF _SFR_MEM8(0x0076) +- +-/* RST - Reset Controller */ +-#define RST_STATUS _SFR_MEM8(0x0078) +-#define RST_CTRL _SFR_MEM8(0x0079) +- +-/* WDT - Watch-Dog Timer */ +-#define WDT_CTRL _SFR_MEM8(0x0080) +-#define WDT_WINCTRL _SFR_MEM8(0x0081) +-#define WDT_STATUS _SFR_MEM8(0x0082) +- +-/* MCU - MCU Control */ +-#define MCU_DEVID0 _SFR_MEM8(0x0090) +-#define MCU_DEVID1 _SFR_MEM8(0x0091) +-#define MCU_DEVID2 _SFR_MEM8(0x0092) +-#define MCU_REVID _SFR_MEM8(0x0093) +-#define MCU_JTAGUID _SFR_MEM8(0x0094) +-#define MCU_MCUCR _SFR_MEM8(0x0096) +-#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +-#define MCU_AWEXLOCK _SFR_MEM8(0x0099) +- +-/* PMIC - Programmable Interrupt Controller */ +-#define PMIC_STATUS _SFR_MEM8(0x00A0) +-#define PMIC_INTPRI _SFR_MEM8(0x00A1) +-#define PMIC_CTRL _SFR_MEM8(0x00A2) +- +-/* PORTCFG - Port Configuration */ +-#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +-#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +-#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +-#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +- +-/* AES - AES Crypto Module */ +-#define AES_CTRL _SFR_MEM8(0x00C0) +-#define AES_STATUS _SFR_MEM8(0x00C1) +-#define AES_STATE _SFR_MEM8(0x00C2) +-#define AES_KEY _SFR_MEM8(0x00C3) +-#define AES_INTCTRL _SFR_MEM8(0x00C4) +- +-/* DMA - DMA Controller */ +-#define DMA_CTRL _SFR_MEM8(0x0100) +-#define DMA_INTFLAGS _SFR_MEM8(0x0103) +-#define DMA_STATUS _SFR_MEM8(0x0104) +-#define DMA_TEMP _SFR_MEM16(0x0106) +-#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +-#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +-#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +-#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +-#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +-#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +-#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +-#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +-#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +-#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +-#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +-#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +-#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +-#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +-#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +-#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +-#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +-#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +-#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +-#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +-#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +-#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +-#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +-#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +-#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +-#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +-#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +-#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +-#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +-#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +-#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +-#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +-#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +-#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +-#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +-#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +-#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +-#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +-#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +-#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +-#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +-#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +-#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +-#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +-#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +-#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +-#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +-#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) +- +-/* EVSYS - Event System */ +-#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +-#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +-#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +-#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +-#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +-#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +-#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +-#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +-#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +-#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +-#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +-#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +-#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +-#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +-#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +-#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +-#define EVSYS_STROBE _SFR_MEM8(0x0190) +-#define EVSYS_DATA _SFR_MEM8(0x0191) +- +-/* NVM - Non Volatile Memory Controller */ +-#define NVM_ADDR0 _SFR_MEM8(0x01C0) +-#define NVM_ADDR1 _SFR_MEM8(0x01C1) +-#define NVM_ADDR2 _SFR_MEM8(0x01C2) +-#define NVM_DATA0 _SFR_MEM8(0x01C4) +-#define NVM_DATA1 _SFR_MEM8(0x01C5) +-#define NVM_DATA2 _SFR_MEM8(0x01C6) +-#define NVM_CMD _SFR_MEM8(0x01CA) +-#define NVM_CTRLA _SFR_MEM8(0x01CB) +-#define NVM_CTRLB _SFR_MEM8(0x01CC) +-#define NVM_INTCTRL _SFR_MEM8(0x01CD) +-#define NVM_STATUS _SFR_MEM8(0x01CF) +-#define NVM_LOCKBITS _SFR_MEM8(0x01D0) +- +-/* ADCA - Analog to Digital Converter A */ +-#define ADCA_CTRLA _SFR_MEM8(0x0200) +-#define ADCA_CTRLB _SFR_MEM8(0x0201) +-#define ADCA_REFCTRL _SFR_MEM8(0x0202) +-#define ADCA_EVCTRL _SFR_MEM8(0x0203) +-#define ADCA_PRESCALER _SFR_MEM8(0x0204) +-#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +-#define ADCA_CAL _SFR_MEM16(0x020C) +-#define ADCA_CH0RES _SFR_MEM16(0x0210) +-#define ADCA_CH1RES _SFR_MEM16(0x0212) +-#define ADCA_CH2RES _SFR_MEM16(0x0214) +-#define ADCA_CH3RES _SFR_MEM16(0x0216) +-#define ADCA_CMP _SFR_MEM16(0x0218) +-#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +-#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +-#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +-#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +-#define ADCA_CH0_RES _SFR_MEM16(0x0224) +-#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +-#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +-#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +-#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +-#define ADCA_CH1_RES _SFR_MEM16(0x022C) +-#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +-#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +-#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +-#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +-#define ADCA_CH2_RES _SFR_MEM16(0x0234) +-#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +-#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +-#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +-#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +-#define ADCA_CH3_RES _SFR_MEM16(0x023C) +- +-/* ADCB - Analog to Digital Converter B */ +-#define ADCB_CTRLA _SFR_MEM8(0x0240) +-#define ADCB_CTRLB _SFR_MEM8(0x0241) +-#define ADCB_REFCTRL _SFR_MEM8(0x0242) +-#define ADCB_EVCTRL _SFR_MEM8(0x0243) +-#define ADCB_PRESCALER _SFR_MEM8(0x0244) +-#define ADCB_INTFLAGS _SFR_MEM8(0x0246) +-#define ADCB_CAL _SFR_MEM16(0x024C) +-#define ADCB_CH0RES _SFR_MEM16(0x0250) +-#define ADCB_CH1RES _SFR_MEM16(0x0252) +-#define ADCB_CH2RES _SFR_MEM16(0x0254) +-#define ADCB_CH3RES _SFR_MEM16(0x0256) +-#define ADCB_CMP _SFR_MEM16(0x0258) +-#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) +-#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) +-#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) +-#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) +-#define ADCB_CH0_RES _SFR_MEM16(0x0264) +-#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) +-#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) +-#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) +-#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) +-#define ADCB_CH1_RES _SFR_MEM16(0x026C) +-#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) +-#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) +-#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) +-#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) +-#define ADCB_CH2_RES _SFR_MEM16(0x0274) +-#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) +-#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) +-#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) +-#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) +-#define ADCB_CH3_RES _SFR_MEM16(0x027C) +- +-/* DACB - Digital to Analog Converter B */ +-#define DACB_CTRLA _SFR_MEM8(0x0320) +-#define DACB_CTRLB _SFR_MEM8(0x0321) +-#define DACB_CTRLC _SFR_MEM8(0x0322) +-#define DACB_EVCTRL _SFR_MEM8(0x0323) +-#define DACB_TIMCTRL _SFR_MEM8(0x0324) +-#define DACB_STATUS _SFR_MEM8(0x0325) +-#define DACB_GAINCAL _SFR_MEM8(0x0328) +-#define DACB_OFFSETCAL _SFR_MEM8(0x0329) +-#define DACB_CH0DATA _SFR_MEM16(0x0338) +-#define DACB_CH1DATA _SFR_MEM16(0x033A) +- +-/* ACA - Analog Comparator A */ +-#define ACA_AC0CTRL _SFR_MEM8(0x0380) +-#define ACA_AC1CTRL _SFR_MEM8(0x0381) +-#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +-#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +-#define ACA_CTRLA _SFR_MEM8(0x0384) +-#define ACA_CTRLB _SFR_MEM8(0x0385) +-#define ACA_WINCTRL _SFR_MEM8(0x0386) +-#define ACA_STATUS _SFR_MEM8(0x0387) +- +-/* ACB - Analog Comparator B */ +-#define ACB_AC0CTRL _SFR_MEM8(0x0390) +-#define ACB_AC1CTRL _SFR_MEM8(0x0391) +-#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +-#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +-#define ACB_CTRLA _SFR_MEM8(0x0394) +-#define ACB_CTRLB _SFR_MEM8(0x0395) +-#define ACB_WINCTRL _SFR_MEM8(0x0396) +-#define ACB_STATUS _SFR_MEM8(0x0397) +- +-/* RTC - Real-Time Counter */ +-#define RTC_CTRL _SFR_MEM8(0x0400) +-#define RTC_STATUS _SFR_MEM8(0x0401) +-#define RTC_INTCTRL _SFR_MEM8(0x0402) +-#define RTC_INTFLAGS _SFR_MEM8(0x0403) +-#define RTC_TEMP _SFR_MEM8(0x0404) +-#define RTC_CNT _SFR_MEM16(0x0408) +-#define RTC_PER _SFR_MEM16(0x040A) +-#define RTC_COMP _SFR_MEM16(0x040C) +- +-/* TWIC - Two-Wire Interface C */ +-#define TWIC_CTRL _SFR_MEM8(0x0480) +-#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +-#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +-#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +-#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +-#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +-#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +-#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +-#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +-#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +-#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +-#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +-#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +-#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) +- +-/* TWIE - Two-Wire Interface E */ +-#define TWIE_CTRL _SFR_MEM8(0x04A0) +-#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +-#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +-#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +-#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +-#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +-#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +-#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +-#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +-#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +-#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +-#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +-#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +-#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) +- +-/* PORTA - Port A */ +-#define PORTA_DIR _SFR_MEM8(0x0600) +-#define PORTA_DIRSET _SFR_MEM8(0x0601) +-#define PORTA_DIRCLR _SFR_MEM8(0x0602) +-#define PORTA_DIRTGL _SFR_MEM8(0x0603) +-#define PORTA_OUT _SFR_MEM8(0x0604) +-#define PORTA_OUTSET _SFR_MEM8(0x0605) +-#define PORTA_OUTCLR _SFR_MEM8(0x0606) +-#define PORTA_OUTTGL _SFR_MEM8(0x0607) +-#define PORTA_IN _SFR_MEM8(0x0608) +-#define PORTA_INTCTRL _SFR_MEM8(0x0609) +-#define PORTA_INT0MASK _SFR_MEM8(0x060A) +-#define PORTA_INT1MASK _SFR_MEM8(0x060B) +-#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +-#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +-#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +-#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +-#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +-#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +-#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +-#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +-#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) +- +-/* PORTB - Port B */ +-#define PORTB_DIR _SFR_MEM8(0x0620) +-#define PORTB_DIRSET _SFR_MEM8(0x0621) +-#define PORTB_DIRCLR _SFR_MEM8(0x0622) +-#define PORTB_DIRTGL _SFR_MEM8(0x0623) +-#define PORTB_OUT _SFR_MEM8(0x0624) +-#define PORTB_OUTSET _SFR_MEM8(0x0625) +-#define PORTB_OUTCLR _SFR_MEM8(0x0626) +-#define PORTB_OUTTGL _SFR_MEM8(0x0627) +-#define PORTB_IN _SFR_MEM8(0x0628) +-#define PORTB_INTCTRL _SFR_MEM8(0x0629) +-#define PORTB_INT0MASK _SFR_MEM8(0x062A) +-#define PORTB_INT1MASK _SFR_MEM8(0x062B) +-#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +-#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +-#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +-#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +-#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +-#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +-#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +-#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +-#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) +- +-/* PORTC - Port C */ +-#define PORTC_DIR _SFR_MEM8(0x0640) +-#define PORTC_DIRSET _SFR_MEM8(0x0641) +-#define PORTC_DIRCLR _SFR_MEM8(0x0642) +-#define PORTC_DIRTGL _SFR_MEM8(0x0643) +-#define PORTC_OUT _SFR_MEM8(0x0644) +-#define PORTC_OUTSET _SFR_MEM8(0x0645) +-#define PORTC_OUTCLR _SFR_MEM8(0x0646) +-#define PORTC_OUTTGL _SFR_MEM8(0x0647) +-#define PORTC_IN _SFR_MEM8(0x0648) +-#define PORTC_INTCTRL _SFR_MEM8(0x0649) +-#define PORTC_INT0MASK _SFR_MEM8(0x064A) +-#define PORTC_INT1MASK _SFR_MEM8(0x064B) +-#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +-#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +-#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +-#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +-#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +-#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +-#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +-#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +-#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) +- +-/* PORTD - Port D */ +-#define PORTD_DIR _SFR_MEM8(0x0660) +-#define PORTD_DIRSET _SFR_MEM8(0x0661) +-#define PORTD_DIRCLR _SFR_MEM8(0x0662) +-#define PORTD_DIRTGL _SFR_MEM8(0x0663) +-#define PORTD_OUT _SFR_MEM8(0x0664) +-#define PORTD_OUTSET _SFR_MEM8(0x0665) +-#define PORTD_OUTCLR _SFR_MEM8(0x0666) +-#define PORTD_OUTTGL _SFR_MEM8(0x0667) +-#define PORTD_IN _SFR_MEM8(0x0668) +-#define PORTD_INTCTRL _SFR_MEM8(0x0669) +-#define PORTD_INT0MASK _SFR_MEM8(0x066A) +-#define PORTD_INT1MASK _SFR_MEM8(0x066B) +-#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +-#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +-#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +-#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +-#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +-#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +-#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +-#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +-#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) +- +-/* PORTE - Port E */ +-#define PORTE_DIR _SFR_MEM8(0x0680) +-#define PORTE_DIRSET _SFR_MEM8(0x0681) +-#define PORTE_DIRCLR _SFR_MEM8(0x0682) +-#define PORTE_DIRTGL _SFR_MEM8(0x0683) +-#define PORTE_OUT _SFR_MEM8(0x0684) +-#define PORTE_OUTSET _SFR_MEM8(0x0685) +-#define PORTE_OUTCLR _SFR_MEM8(0x0686) +-#define PORTE_OUTTGL _SFR_MEM8(0x0687) +-#define PORTE_IN _SFR_MEM8(0x0688) +-#define PORTE_INTCTRL _SFR_MEM8(0x0689) +-#define PORTE_INT0MASK _SFR_MEM8(0x068A) +-#define PORTE_INT1MASK _SFR_MEM8(0x068B) +-#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +-#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +-#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +-#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +-#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +-#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +-#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +-#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +-#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) +- +-/* PORTF - Port F */ +-#define PORTF_DIR _SFR_MEM8(0x06A0) +-#define PORTF_DIRSET _SFR_MEM8(0x06A1) +-#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +-#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +-#define PORTF_OUT _SFR_MEM8(0x06A4) +-#define PORTF_OUTSET _SFR_MEM8(0x06A5) +-#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +-#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +-#define PORTF_IN _SFR_MEM8(0x06A8) +-#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +-#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +-#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +-#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +-#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +-#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +-#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +-#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +-#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +-#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +-#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +-#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) +- +-/* PORTR - Port R */ +-#define PORTR_DIR _SFR_MEM8(0x07E0) +-#define PORTR_DIRSET _SFR_MEM8(0x07E1) +-#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +-#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +-#define PORTR_OUT _SFR_MEM8(0x07E4) +-#define PORTR_OUTSET _SFR_MEM8(0x07E5) +-#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +-#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +-#define PORTR_IN _SFR_MEM8(0x07E8) +-#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +-#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +-#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +-#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +-#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +-#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +-#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +-#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +-#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +-#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +-#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +-#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) +- +-/* TCC0 - Timer/Counter C0 */ +-#define TCC0_CTRLA _SFR_MEM8(0x0800) +-#define TCC0_CTRLB _SFR_MEM8(0x0801) +-#define TCC0_CTRLC _SFR_MEM8(0x0802) +-#define TCC0_CTRLD _SFR_MEM8(0x0803) +-#define TCC0_CTRLE _SFR_MEM8(0x0804) +-#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +-#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +-#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +-#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +-#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +-#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +-#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +-#define TCC0_TEMP _SFR_MEM8(0x080F) +-#define TCC0_CNT _SFR_MEM16(0x0820) +-#define TCC0_PER _SFR_MEM16(0x0826) +-#define TCC0_CCA _SFR_MEM16(0x0828) +-#define TCC0_CCB _SFR_MEM16(0x082A) +-#define TCC0_CCC _SFR_MEM16(0x082C) +-#define TCC0_CCD _SFR_MEM16(0x082E) +-#define TCC0_PERBUF _SFR_MEM16(0x0836) +-#define TCC0_CCABUF _SFR_MEM16(0x0838) +-#define TCC0_CCBBUF _SFR_MEM16(0x083A) +-#define TCC0_CCCBUF _SFR_MEM16(0x083C) +-#define TCC0_CCDBUF _SFR_MEM16(0x083E) +- +-/* TCC1 - Timer/Counter C1 */ +-#define TCC1_CTRLA _SFR_MEM8(0x0840) +-#define TCC1_CTRLB _SFR_MEM8(0x0841) +-#define TCC1_CTRLC _SFR_MEM8(0x0842) +-#define TCC1_CTRLD _SFR_MEM8(0x0843) +-#define TCC1_CTRLE _SFR_MEM8(0x0844) +-#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +-#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +-#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +-#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +-#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +-#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +-#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +-#define TCC1_TEMP _SFR_MEM8(0x084F) +-#define TCC1_CNT _SFR_MEM16(0x0860) +-#define TCC1_PER _SFR_MEM16(0x0866) +-#define TCC1_CCA _SFR_MEM16(0x0868) +-#define TCC1_CCB _SFR_MEM16(0x086A) +-#define TCC1_PERBUF _SFR_MEM16(0x0876) +-#define TCC1_CCABUF _SFR_MEM16(0x0878) +-#define TCC1_CCBBUF _SFR_MEM16(0x087A) +- +-/* AWEXC - Advanced Waveform Extension C */ +-#define AWEXC_CTRL _SFR_MEM8(0x0880) +-#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +-#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +-#define AWEXC_STATUS _SFR_MEM8(0x0884) +-#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +-#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +-#define AWEXC_DTLS _SFR_MEM8(0x0888) +-#define AWEXC_DTHS _SFR_MEM8(0x0889) +-#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +-#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +-#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) +- +-/* HIRESC - High-Resolution Extension C */ +-#define HIRESC_CTRLA _SFR_MEM8(0x0890) +- +-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +-#define USARTC0_DATA _SFR_MEM8(0x08A0) +-#define USARTC0_STATUS _SFR_MEM8(0x08A1) +-#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +-#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +-#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +-#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +-#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) +- +-/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ +-#define USARTC1_DATA _SFR_MEM8(0x08B0) +-#define USARTC1_STATUS _SFR_MEM8(0x08B1) +-#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +-#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +-#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +-#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +-#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) +- +-/* SPIC - Serial Peripheral Interface C */ +-#define SPIC_CTRL _SFR_MEM8(0x08C0) +-#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +-#define SPIC_STATUS _SFR_MEM8(0x08C2) +-#define SPIC_DATA _SFR_MEM8(0x08C3) +- +-/* IRCOM - IR Communication Module */ +-#define IRCOM_CTRL _SFR_MEM8(0x08F8) +-#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +-#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) +- +-/* TCD0 - Timer/Counter D0 */ +-#define TCD0_CTRLA _SFR_MEM8(0x0900) +-#define TCD0_CTRLB _SFR_MEM8(0x0901) +-#define TCD0_CTRLC _SFR_MEM8(0x0902) +-#define TCD0_CTRLD _SFR_MEM8(0x0903) +-#define TCD0_CTRLE _SFR_MEM8(0x0904) +-#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +-#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +-#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +-#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +-#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +-#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +-#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +-#define TCD0_TEMP _SFR_MEM8(0x090F) +-#define TCD0_CNT _SFR_MEM16(0x0920) +-#define TCD0_PER _SFR_MEM16(0x0926) +-#define TCD0_CCA _SFR_MEM16(0x0928) +-#define TCD0_CCB _SFR_MEM16(0x092A) +-#define TCD0_CCC _SFR_MEM16(0x092C) +-#define TCD0_CCD _SFR_MEM16(0x092E) +-#define TCD0_PERBUF _SFR_MEM16(0x0936) +-#define TCD0_CCABUF _SFR_MEM16(0x0938) +-#define TCD0_CCBBUF _SFR_MEM16(0x093A) +-#define TCD0_CCCBUF _SFR_MEM16(0x093C) +-#define TCD0_CCDBUF _SFR_MEM16(0x093E) +- +-/* TCD1 - Timer/Counter D1 */ +-#define TCD1_CTRLA _SFR_MEM8(0x0940) +-#define TCD1_CTRLB _SFR_MEM8(0x0941) +-#define TCD1_CTRLC _SFR_MEM8(0x0942) +-#define TCD1_CTRLD _SFR_MEM8(0x0943) +-#define TCD1_CTRLE _SFR_MEM8(0x0944) +-#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +-#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +-#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +-#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +-#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +-#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +-#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +-#define TCD1_TEMP _SFR_MEM8(0x094F) +-#define TCD1_CNT _SFR_MEM16(0x0960) +-#define TCD1_PER _SFR_MEM16(0x0966) +-#define TCD1_CCA _SFR_MEM16(0x0968) +-#define TCD1_CCB _SFR_MEM16(0x096A) +-#define TCD1_PERBUF _SFR_MEM16(0x0976) +-#define TCD1_CCABUF _SFR_MEM16(0x0978) +-#define TCD1_CCBBUF _SFR_MEM16(0x097A) +- +-/* HIRESD - High-Resolution Extension D */ +-#define HIRESD_CTRLA _SFR_MEM8(0x0990) +- +-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +-#define USARTD0_DATA _SFR_MEM8(0x09A0) +-#define USARTD0_STATUS _SFR_MEM8(0x09A1) +-#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +-#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +-#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +-#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +-#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) +- +-/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ +-#define USARTD1_DATA _SFR_MEM8(0x09B0) +-#define USARTD1_STATUS _SFR_MEM8(0x09B1) +-#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +-#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +-#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +-#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +-#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) +- +-/* SPID - Serial Peripheral Interface D */ +-#define SPID_CTRL _SFR_MEM8(0x09C0) +-#define SPID_INTCTRL _SFR_MEM8(0x09C1) +-#define SPID_STATUS _SFR_MEM8(0x09C2) +-#define SPID_DATA _SFR_MEM8(0x09C3) +- +-/* TCE0 - Timer/Counter E0 */ +-#define TCE0_CTRLA _SFR_MEM8(0x0A00) +-#define TCE0_CTRLB _SFR_MEM8(0x0A01) +-#define TCE0_CTRLC _SFR_MEM8(0x0A02) +-#define TCE0_CTRLD _SFR_MEM8(0x0A03) +-#define TCE0_CTRLE _SFR_MEM8(0x0A04) +-#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +-#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +-#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +-#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +-#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +-#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +-#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +-#define TCE0_TEMP _SFR_MEM8(0x0A0F) +-#define TCE0_CNT _SFR_MEM16(0x0A20) +-#define TCE0_PER _SFR_MEM16(0x0A26) +-#define TCE0_CCA _SFR_MEM16(0x0A28) +-#define TCE0_CCB _SFR_MEM16(0x0A2A) +-#define TCE0_CCC _SFR_MEM16(0x0A2C) +-#define TCE0_CCD _SFR_MEM16(0x0A2E) +-#define TCE0_PERBUF _SFR_MEM16(0x0A36) +-#define TCE0_CCABUF _SFR_MEM16(0x0A38) +-#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +-#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +-#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) +- +-/* TCE1 - Timer/Counter E1 */ +-#define TCE1_CTRLA _SFR_MEM8(0x0A40) +-#define TCE1_CTRLB _SFR_MEM8(0x0A41) +-#define TCE1_CTRLC _SFR_MEM8(0x0A42) +-#define TCE1_CTRLD _SFR_MEM8(0x0A43) +-#define TCE1_CTRLE _SFR_MEM8(0x0A44) +-#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) +-#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) +-#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) +-#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) +-#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) +-#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) +-#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) +-#define TCE1_TEMP _SFR_MEM8(0x0A4F) +-#define TCE1_CNT _SFR_MEM16(0x0A60) +-#define TCE1_PER _SFR_MEM16(0x0A66) +-#define TCE1_CCA _SFR_MEM16(0x0A68) +-#define TCE1_CCB _SFR_MEM16(0x0A6A) +-#define TCE1_PERBUF _SFR_MEM16(0x0A76) +-#define TCE1_CCABUF _SFR_MEM16(0x0A78) +-#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) +- +-/* AWEXE - Advanced Waveform Extension E */ +-#define AWEXE_CTRL _SFR_MEM8(0x0A80) +-#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +-#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +-#define AWEXE_STATUS _SFR_MEM8(0x0A84) +-#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +-#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +-#define AWEXE_DTLS _SFR_MEM8(0x0A88) +-#define AWEXE_DTHS _SFR_MEM8(0x0A89) +-#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +-#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +-#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) +- +-/* HIRESE - High-Resolution Extension E */ +-#define HIRESE_CTRLA _SFR_MEM8(0x0A90) +- +-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +-#define USARTE0_DATA _SFR_MEM8(0x0AA0) +-#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +-#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +-#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +-#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +-#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +-#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) +- +-/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ +-#define USARTE1_DATA _SFR_MEM8(0x0AB0) +-#define USARTE1_STATUS _SFR_MEM8(0x0AB1) +-#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) +-#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) +-#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) +-#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) +-#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) +- +-/* SPIE - Serial Peripheral Interface E */ +-#define SPIE_CTRL _SFR_MEM8(0x0AC0) +-#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +-#define SPIE_STATUS _SFR_MEM8(0x0AC2) +-#define SPIE_DATA _SFR_MEM8(0x0AC3) +- +-/* TCF0 - Timer/Counter F0 */ +-#define TCF0_CTRLA _SFR_MEM8(0x0B00) +-#define TCF0_CTRLB _SFR_MEM8(0x0B01) +-#define TCF0_CTRLC _SFR_MEM8(0x0B02) +-#define TCF0_CTRLD _SFR_MEM8(0x0B03) +-#define TCF0_CTRLE _SFR_MEM8(0x0B04) +-#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +-#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +-#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +-#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +-#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +-#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +-#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +-#define TCF0_TEMP _SFR_MEM8(0x0B0F) +-#define TCF0_CNT _SFR_MEM16(0x0B20) +-#define TCF0_PER _SFR_MEM16(0x0B26) +-#define TCF0_CCA _SFR_MEM16(0x0B28) +-#define TCF0_CCB _SFR_MEM16(0x0B2A) +-#define TCF0_CCC _SFR_MEM16(0x0B2C) +-#define TCF0_CCD _SFR_MEM16(0x0B2E) +-#define TCF0_PERBUF _SFR_MEM16(0x0B36) +-#define TCF0_CCABUF _SFR_MEM16(0x0B38) +-#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +-#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +-#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) +- +-/* HIRESF - High-Resolution Extension F */ +-#define HIRESF_CTRLA _SFR_MEM8(0x0B90) +- +-/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ +-#define USARTF0_DATA _SFR_MEM8(0x0BA0) +-#define USARTF0_STATUS _SFR_MEM8(0x0BA1) +-#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) +-#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) +-#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) +-#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) +-#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) +- +-/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ +-#define USARTF1_DATA _SFR_MEM8(0x0BB0) +-#define USARTF1_STATUS _SFR_MEM8(0x0BB1) +-#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) +-#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) +-#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) +-#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) +-#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) +- +-/* SPIF - Serial Peripheral Interface F */ +-#define SPIF_CTRL _SFR_MEM8(0x0BC0) +-#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) +-#define SPIF_STATUS _SFR_MEM8(0x0BC2) +-#define SPIF_DATA _SFR_MEM8(0x0BC3) +- +- +- +-/*================== Bitfield Definitions ================== */ +- +-/* XOCD - On-Chip Debug System */ +-/* OCD.OCDR1 bit masks and bit positions */ +-#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +-#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ +- +- +-/* CPU - CPU */ +-/* CPU.CCP bit masks and bit positions */ +-#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +-#define CPU_CCP_gp 0 /* CCP signature group position. */ +-#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +-#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +-#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +-#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +-#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +-#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +-#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +-#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +-#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +-#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +-#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +-#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +-#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +-#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +-#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +-#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ +- +- +-/* CPU.SREG bit masks and bit positions */ +-#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +-#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ +- +-#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +-#define CPU_T_bp 6 /* Transfer Bit bit position. */ +- +-#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +-#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +- +-#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +-#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +- +-#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +-#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +- +-#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +-#define CPU_N_bp 2 /* Negative Flag bit position. */ +- +-#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +-#define CPU_Z_bp 1 /* Zero Flag bit position. */ +- +-#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +-#define CPU_C_bp 0 /* Carry Flag bit position. */ +- +- +-/* CLK - Clock System */ +-/* CLK.CTRL bit masks and bit positions */ +-#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +-#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +-#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +-#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +-#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +-#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +-#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +-#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ +- +- +-/* CLK.PSCTRL bit masks and bit positions */ +-#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +-#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +-#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +-#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +-#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +-#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +-#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +-#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +-#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +-#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +-#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +-#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ +- +-#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +-#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +-#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +-#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +-#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +-#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ +- +- +-/* CLK.LOCK bit masks and bit positions */ +-#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +-#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ +- +- +-/* CLK.RTCCTRL bit masks and bit positions */ +-#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +-#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +-#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +-#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +-#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +-#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +-#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +-#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ +- +-#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +-#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ +- +- +-/* PR.PRGEN bit masks and bit positions */ +-#define PR_AES_bm 0x10 /* AES bit mask. */ +-#define PR_AES_bp 4 /* AES bit position. */ +- +-#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +-#define PR_EBI_bp 3 /* External Bus Interface bit position. */ +- +-#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +-#define PR_RTC_bp 2 /* Real-time Counter bit position. */ +- +-#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +-#define PR_EVSYS_bp 1 /* Event System bit position. */ +- +-#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +-#define PR_DMA_bp 0 /* DMA-Controller bit position. */ +- +- +-/* PR.PRPA bit masks and bit positions */ +-#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +-#define PR_DAC_bp 2 /* Port A DAC bit position. */ +- +-#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +-#define PR_ADC_bp 1 /* Port A ADC bit position. */ +- +-#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +-#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ +- +- +-/* PR.PRPB bit masks and bit positions */ +-/* PR_DAC_bm Predefined. */ +-/* PR_DAC_bp Predefined. */ +- +-/* PR_ADC_bm Predefined. */ +-/* PR_ADC_bp Predefined. */ +- +-/* PR_AC_bm Predefined. */ +-/* PR_AC_bp Predefined. */ +- +- +-/* PR.PRPC bit masks and bit positions */ +-#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +-#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ +- +-#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +-#define PR_USART1_bp 5 /* Port C USART1 bit position. */ +- +-#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +-#define PR_USART0_bp 4 /* Port C USART0 bit position. */ +- +-#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +-#define PR_SPI_bp 3 /* Port C SPI bit position. */ +- +-#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +-#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ +- +-#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +-#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ +- +-#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +-#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ +- +- +-/* PR.PRPD bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* PR.PRPE bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* PR.PRPF bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* SLEEP - Sleep Controller */ +-/* SLEEP.CTRL bit masks and bit positions */ +-#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +-#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +-#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +-#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +-#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +-#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +-#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +-#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ +- +-#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +-#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ +- +- +-/* OSC - Oscillator */ +-/* OSC.CTRL bit masks and bit positions */ +-#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +-#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ +- +-#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +-#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ +- +-#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ +- +- +-/* OSC.STATUS bit masks and bit positions */ +-#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +-#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ +- +-#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +-#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ +- +-#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ +- +- +-/* OSC.XOSCCTRL bit masks and bit positions */ +-#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +-#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +-#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +-#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +-#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +-#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ +- +-#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +-#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ +- +-#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +-#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +-#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +-#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +-#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +-#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +-#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +-#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +-#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +-#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +- +- +-/* OSC.XOSCFAIL bit masks and bit positions */ +-#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +-#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ +- +-#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +-#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ +- +- +-/* OSC.PLLCTRL bit masks and bit positions */ +-#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +-#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +-#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +-#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +-#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +-#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ +- +-#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +-#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +-#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +-#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +-#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +-#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +-#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +-#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +-#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +-#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +-#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +-#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ +- +- +-/* OSC.DFLLCTRL bit masks and bit positions */ +-#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +-#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ +- +-#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +-#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ +- +- +-/* DFLL - DFLL */ +-/* DFLL.CTRL bit masks and bit positions */ +-#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +-#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ +- +- +-/* DFLL.CALA bit masks and bit positions */ +-#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +-#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +-#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +-#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +-#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +-#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +-#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +-#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +-#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +-#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +-#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +-#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +-#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +-#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +-#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +-#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ +- +- +-/* DFLL.CALB bit masks and bit positions */ +-#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +-#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +-#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +-#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +-#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +-#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +-#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +-#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +-#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +-#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +-#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +-#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +-#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +-#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ +- +- +-/* RST - Reset */ +-/* RST.STATUS bit masks and bit positions */ +-#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +-#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ +- +-#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +-#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ +- +-#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +-#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ +- +-#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +-#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ +- +-#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +-#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ +- +-#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +-#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ +- +-#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +-#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ +- +- +-/* RST.CTRL bit masks and bit positions */ +-#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +-#define RST_SWRST_bp 0 /* Software Reset bit position. */ +- +- +-/* WDT - Watch-Dog Timer */ +-/* WDT.CTRL bit masks and bit positions */ +-#define WDT_PER_gm 0x3C /* Period group mask. */ +-#define WDT_PER_gp 2 /* Period group position. */ +-#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +-#define WDT_PER0_bp 2 /* Period bit 0 position. */ +-#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +-#define WDT_PER1_bp 3 /* Period bit 1 position. */ +-#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +-#define WDT_PER2_bp 4 /* Period bit 2 position. */ +-#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +-#define WDT_PER3_bp 5 /* Period bit 3 position. */ +- +-#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +-#define WDT_ENABLE_bp 1 /* Enable bit position. */ +- +-#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +-#define WDT_CEN_bp 0 /* Change Enable bit position. */ +- +- +-/* WDT.WINCTRL bit masks and bit positions */ +-#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +-#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +-#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +-#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +-#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +-#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +-#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +-#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +-#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +-#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ +- +-#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +-#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ +- +-#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +-#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ +- +- +-/* WDT.STATUS bit masks and bit positions */ +-#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +-#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +- +- +-/* MCU - MCU Control */ +-/* MCU.MCUCR bit masks and bit positions */ +-#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +-#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ +- +- +-/* MCU.EVSYSLOCK bit masks and bit positions */ +-#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +-#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ +- +-#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +-#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ +- +- +-/* MCU.AWEXLOCK bit masks and bit positions */ +-#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +-#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ +- +-#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +-#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ +- +- +-/* PMIC - Programmable Multi-level Interrupt Controller */ +-/* PMIC.STATUS bit masks and bit positions */ +-#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +-#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ +- +-#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +-#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ +- +-#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +-#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ +- +-#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +-#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ +- +- +-/* PMIC.CTRL bit masks and bit positions */ +-#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +-#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ +- +-#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +-#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ +- +-#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +-#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ +- +-#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +-#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ +- +-#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +-#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ +- +- +-/* DMA - DMA Controller */ +-/* DMA_CH.CTRLA bit masks and bit positions */ +-#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +-#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ +- +-#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +-#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ +- +-#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +-#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ +- +-#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +-#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ +- +-#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +-#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ +- +-#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +-#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +-#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +-#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +-#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +-#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ +- +- +-/* DMA_CH.CTRLB bit masks and bit positions */ +-#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +-#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ +- +-#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +-#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ +- +-#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +-#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ +- +-#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +-#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +-#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +-#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +-#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +-#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ +- +-#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +-#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +-#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +-#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +-#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +-#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ +- +- +-/* DMA_CH.ADDRCTRL bit masks and bit positions */ +-#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +-#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +-#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +-#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +-#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +-#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ +- +-#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +-#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +-#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +-#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +-#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +-#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ +- +-#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +-#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +-#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +-#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +-#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +-#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ +- +-#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +-#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +-#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +-#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +-#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +-#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ +- +- +-/* DMA_CH.TRIGSRC bit masks and bit positions */ +-#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +-#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +-#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +-#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +-#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +-#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +-#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +-#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +-#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +-#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +-#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +-#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +-#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +-#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +-#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +-#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +-#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +-#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ +- +- +-/* DMA.CTRL bit masks and bit positions */ +-#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +-#define DMA_ENABLE_bp 7 /* Enable bit position. */ +- +-#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +-#define DMA_RESET_bp 6 /* Software Reset bit position. */ +- +-#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +-#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +-#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +-#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +-#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +-#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ +- +-#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +-#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +-#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +-#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +-#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +-#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ +- +- +-/* DMA.INTFLAGS bit masks and bit positions */ +-#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ +- +- +-/* DMA.STATUS bit masks and bit positions */ +-#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +-#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ +- +-#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +-#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ +- +-#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +-#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ +- +-#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +-#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ +- +-#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +-#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ +- +-#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +-#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ +- +-#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +-#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ +- +-#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +-#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ +- +- +-/* EVSYS - Event System */ +-/* EVSYS.CH0MUX bit masks and bit positions */ +-#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +-#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +-#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +-#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +-#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +-#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +-#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +-#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +-#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +-#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +-#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +-#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +-#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +-#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +-#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +-#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +-#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +-#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ +- +- +-/* EVSYS.CH1MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH2MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH3MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH4MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH5MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH6MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH7MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH0CTRL bit masks and bit positions */ +-#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +-#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +-#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +-#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +-#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +-#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ +- +-#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +-#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ +- +-#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +-#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ +- +-#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +-#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +-#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +-#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +-#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +-#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +-#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +-#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ +- +- +-/* EVSYS.CH1CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH2CTRL bit masks and bit positions */ +-/* EVSYS_QDIRM_gm Predefined. */ +-/* EVSYS_QDIRM_gp Predefined. */ +-/* EVSYS_QDIRM0_bm Predefined. */ +-/* EVSYS_QDIRM0_bp Predefined. */ +-/* EVSYS_QDIRM1_bm Predefined. */ +-/* EVSYS_QDIRM1_bp Predefined. */ +- +-/* EVSYS_QDIEN_bm Predefined. */ +-/* EVSYS_QDIEN_bp Predefined. */ +- +-/* EVSYS_QDEN_bm Predefined. */ +-/* EVSYS_QDEN_bp Predefined. */ +- +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH3CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH4CTRL bit masks and bit positions */ +-/* EVSYS_QDIRM_gm Predefined. */ +-/* EVSYS_QDIRM_gp Predefined. */ +-/* EVSYS_QDIRM0_bm Predefined. */ +-/* EVSYS_QDIRM0_bp Predefined. */ +-/* EVSYS_QDIRM1_bm Predefined. */ +-/* EVSYS_QDIRM1_bp Predefined. */ +- +-/* EVSYS_QDIEN_bm Predefined. */ +-/* EVSYS_QDIEN_bp Predefined. */ +- +-/* EVSYS_QDEN_bm Predefined. */ +-/* EVSYS_QDEN_bp Predefined. */ +- +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH5CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH6CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH7CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* NVM - Non Volatile Memory Controller */ +-/* NVM.CMD bit masks and bit positions */ +-#define NVM_CMD_gm 0xFF /* Command group mask. */ +-#define NVM_CMD_gp 0 /* Command group position. */ +-#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +-#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +-#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +-#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +-#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +-#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +-#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +-#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +-#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +-#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +-#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +-#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +-#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +-#define NVM_CMD7_bp 7 /* Command bit 7 position. */ +- +- +-/* NVM.CTRLA bit masks and bit positions */ +-#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +-#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ +- +- +-/* NVM.CTRLB bit masks and bit positions */ +-#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +-#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ +- +-#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +-#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ +- +-#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +-#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ +- +-#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +-#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ +- +- +-/* NVM.INTCTRL bit masks and bit positions */ +-#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +-#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +-#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +-#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +-#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +-#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ +- +-#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +-#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +-#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +-#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +-#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +-#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ +- +- +-/* NVM.STATUS bit masks and bit positions */ +-#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +-#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ +- +-#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +-#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ +- +-#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +-#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ +- +-#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +-#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ +- +- +-/* NVM.LOCKBITS bit masks and bit positions */ +-#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +-#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +-#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ +-#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ +-#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ +-#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ +-#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ +-#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ +-#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ +-#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ +-#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ +-#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ +-#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ +-#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ +-#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ +-#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ +-#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ +-#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ +-#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ +-#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +-#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +-#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +-#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ +- +-#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +-#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +-#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +-#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +-#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ +- +-#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +-#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ +- +-#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +-#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +-#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +-#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +-#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +-#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +-#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +-#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +-#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +-#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +-#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +-#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ +- +-#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +-#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ +- +-#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ +-#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ +- +- +-/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +-#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +-#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +-#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +-#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +-#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +-#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ +- +-#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +-#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ +- +-#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +-#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +-#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +-#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +-#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +-#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +-#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +-#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +- +- +-/* AC - Analog Comparator */ +-/* AC.AC0CTRL bit masks and bit positions */ +-#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +-#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +-#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +-#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +-#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +-#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ +- +-#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +-#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +-#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +-#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +-#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +-#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ +- +-#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +-#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ +- +-#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +-#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +-#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +-#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +-#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +-#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +- +-#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define AC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* AC.AC1CTRL bit masks and bit positions */ +-/* AC_INTMODE_gm Predefined. */ +-/* AC_INTMODE_gp Predefined. */ +-/* AC_INTMODE0_bm Predefined. */ +-/* AC_INTMODE0_bp Predefined. */ +-/* AC_INTMODE1_bm Predefined. */ +-/* AC_INTMODE1_bp Predefined. */ +- +-/* AC_INTLVL_gm Predefined. */ +-/* AC_INTLVL_gp Predefined. */ +-/* AC_INTLVL0_bm Predefined. */ +-/* AC_INTLVL0_bp Predefined. */ +-/* AC_INTLVL1_bm Predefined. */ +-/* AC_INTLVL1_bp Predefined. */ +- +-/* AC_HSMODE_bm Predefined. */ +-/* AC_HSMODE_bp Predefined. */ +- +-/* AC_HYSMODE_gm Predefined. */ +-/* AC_HYSMODE_gp Predefined. */ +-/* AC_HYSMODE0_bm Predefined. */ +-/* AC_HYSMODE0_bp Predefined. */ +-/* AC_HYSMODE1_bm Predefined. */ +-/* AC_HYSMODE1_bp Predefined. */ +- +-/* AC_ENABLE_bm Predefined. */ +-/* AC_ENABLE_bp Predefined. */ +- +- +-/* AC.AC0MUXCTRL bit masks and bit positions */ +-#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +-#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +-#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +-#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +-#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +-#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +-#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +-#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ +- +-#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +-#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +-#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +-#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +-#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +-#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +-#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +-#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ +- +- +-/* AC.AC1MUXCTRL bit masks and bit positions */ +-/* AC_MUXPOS_gm Predefined. */ +-/* AC_MUXPOS_gp Predefined. */ +-/* AC_MUXPOS0_bm Predefined. */ +-/* AC_MUXPOS0_bp Predefined. */ +-/* AC_MUXPOS1_bm Predefined. */ +-/* AC_MUXPOS1_bp Predefined. */ +-/* AC_MUXPOS2_bm Predefined. */ +-/* AC_MUXPOS2_bp Predefined. */ +- +-/* AC_MUXNEG_gm Predefined. */ +-/* AC_MUXNEG_gp Predefined. */ +-/* AC_MUXNEG0_bm Predefined. */ +-/* AC_MUXNEG0_bp Predefined. */ +-/* AC_MUXNEG1_bm Predefined. */ +-/* AC_MUXNEG1_bp Predefined. */ +-/* AC_MUXNEG2_bm Predefined. */ +-/* AC_MUXNEG2_bp Predefined. */ +- +- +-/* AC.CTRLA bit masks and bit positions */ +-#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +-#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ +- +- +-/* AC.CTRLB bit masks and bit positions */ +-#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +-#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +-#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +-#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +-#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +-#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +-#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +-#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +-#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +-#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +-#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +-#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +-#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +-#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ +- +- +-/* AC.WINCTRL bit masks and bit positions */ +-#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +-#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ +- +-#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +-#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +-#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +-#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +-#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +-#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ +- +-#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +-#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +-#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +-#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +-#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +-#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ +- +- +-/* AC.STATUS bit masks and bit positions */ +-#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +-#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +-#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +-#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +-#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +-#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ +- +-#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +-#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ +- +-#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +-#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ +- +-#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +-#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ +- +-#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +-#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ +- +-#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +-#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ +- +- +-/* ADC - Analog/Digital Converter */ +-/* ADC_CH.CTRL bit masks and bit positions */ +-#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +-#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ +- +-#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +-#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +-#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +-#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +-#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +-#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +-#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +-#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ +- +-#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +-#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +-#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +-#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +-#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +-#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ +- +- +-/* ADC_CH.MUXCTRL bit masks and bit positions */ +-#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +-#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +-#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +-#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +-#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +-#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +-#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +-#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +-#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +-#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ +- +-#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +-#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +-#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +-#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +-#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +-#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +-#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +-#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +-#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +-#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ +- +-#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +-#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +-#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +-#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +-#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +-#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ +- +- +-/* ADC_CH.INTCTRL bit masks and bit positions */ +-#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +-#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +-#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +-#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +-#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +-#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ +- +-#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +-#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +-#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +-#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +-#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +-#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ +- +- +-/* ADC_CH.INTFLAGS bit masks and bit positions */ +-#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +-#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ +- +- +-/* ADC.CTRLA bit masks and bit positions */ +-#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +-#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +-#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +-#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +-#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +-#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ +- +-#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +-#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ +- +-#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +-#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ +- +-#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +-#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ +- +-#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +-#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ +- +-#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +-#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ +- +-#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +-#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ +- +- +-/* ADC.CTRLB bit masks and bit positions */ +-#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +-#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ +- +-#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +-#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ +- +-#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +-#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +-#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +-#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +-#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +-#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ +- +- +-/* ADC.REFCTRL bit masks and bit positions */ +-#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +-#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +-#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +-#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +-#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +-#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +- +-#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +-#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ +- +-#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +-#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ +- +- +-/* ADC.EVCTRL bit masks and bit positions */ +-#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +-#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +-#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +-#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +-#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +-#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ +- +-#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +-#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +-#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +-#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +-#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +-#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +-#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +-#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ +- +-#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +-#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +-#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +-#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +-#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +-#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +-#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +-#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ +- +- +-/* ADC.PRESCALER bit masks and bit positions */ +-#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +-#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +-#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +-#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +-#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +-#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +-#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +-#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ +- +- +-/* ADC.INTFLAGS bit masks and bit positions */ +-#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +-#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ +- +-#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +-#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ +- +-#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +-#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ +- +-#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +-#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ +- +- +-/* DAC - Digital/Analog Converter */ +-/* DAC.CTRLA bit masks and bit positions */ +-#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +-#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ +- +-#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +-#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ +- +-#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +-#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ +- +-#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +-#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ +- +-#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define DAC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* DAC.CTRLB bit masks and bit positions */ +-#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +-#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +-#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +-#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +-#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +-#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ +- +-#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +-#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ +- +-#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +-#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ +- +- +-/* DAC.CTRLC bit masks and bit positions */ +-#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +-#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +-#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +-#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +-#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +-#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ +- +-#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +-#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ +- +- +-/* DAC.EVCTRL bit masks and bit positions */ +-#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +-#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +-#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +-#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +-#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +-#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +-#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +-#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ +- +- +-/* DAC.TIMCTRL bit masks and bit positions */ +-#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ +-#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ +-#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ +-#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ +-#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ +-#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ +-#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ +-#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ +- +-#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ +-#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ +-#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ +-#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ +-#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ +-#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ +-#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ +-#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ +-#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ +-#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ +- +- +-/* DAC.STATUS bit masks and bit positions */ +-#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +-#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ +- +-#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +-#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ +- +- +-/* RTC - Real-Time Clounter */ +-/* RTC.CTRL bit masks and bit positions */ +-#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +-#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +-#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +-#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +-#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +-#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +-#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +-#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ +- +- +-/* RTC.STATUS bit masks and bit positions */ +-#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +-#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ +- +- +-/* RTC.INTCTRL bit masks and bit positions */ +-#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +-#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +-#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +-#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +-#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +-#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ +- +-#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +-#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +-#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +-#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +-#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +-#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ +- +- +-/* RTC.INTFLAGS bit masks and bit positions */ +-#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +-#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ +- +-#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* EBI - External Bus Interface */ +-/* EBI_CS.CTRLA bit masks and bit positions */ +-#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +-#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +-#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +-#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +-#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +-#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +-#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +-#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +-#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +-#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +-#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +-#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ +- +-#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +-#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +-#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +-#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +-#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +-#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ +- +- +-/* EBI_CS.CTRLB bit masks and bit positions */ +-#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +-#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +-#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +-#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +-#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +-#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +-#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +-#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ +- +-#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +-#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ +- +-#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +-#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ +- +-#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +-#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +-#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +-#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +-#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +-#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ +- +- +-/* EBI.CTRL bit masks and bit positions */ +-#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +-#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +-#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +-#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +-#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +-#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ +- +-#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +-#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +-#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +-#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +-#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +-#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ +- +-#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +-#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +-#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +-#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +-#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +-#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ +- +-#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +-#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +-#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +-#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +-#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +-#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLA bit masks and bit positions */ +-#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +-#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ +- +-#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +-#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ +- +-#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +-#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +-#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +-#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +-#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +-#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLB bit masks and bit positions */ +-#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +-#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +-#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +-#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +-#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +-#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ +- +-#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +-#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +-#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +-#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +-#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +-#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +-#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +-#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ +- +-#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +-#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +-#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +-#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +-#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +-#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +-#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +-#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ +- +- +-/* EBI.SDRAMCTRLC bit masks and bit positions */ +-#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +-#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +-#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +-#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +-#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +-#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ +- +-#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +-#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +-#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +-#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +-#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +-#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +-#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +-#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ +- +-#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +-#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +-#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +-#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +-#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +-#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +-#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +-#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ +- +- +-/* TWI - Two-Wire Interface */ +-/* TWI_MASTER.CTRLA bit masks and bit positions */ +-#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +-#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ +- +-#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +-#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ +- +-#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +-#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ +- +- +-/* TWI_MASTER.CTRLB bit masks and bit positions */ +-#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +-#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +-#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +-#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +-#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +-#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +- +-#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +-#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ +- +-#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_MASTER.CTRLC bit masks and bit positions */ +-#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +-#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_MASTER.STATUS bit masks and bit positions */ +-#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +-#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ +- +-#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +-#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ +- +-#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +-#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +- +-#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +-#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +-#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +-#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +-#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +-#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +- +- +-/* TWI_SLAVE.CTRLA bit masks and bit positions */ +-#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +-#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +-#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ +- +-#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +-#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ +- +-#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_SLAVE.CTRLB bit masks and bit positions */ +-#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +-#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_SLAVE.STATUS bit masks and bit positions */ +-#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +-#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +-#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +-#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ +- +-#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +-#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ +- +-#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +-#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ +- +- +-/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +-#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +-#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +-#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +-#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +-#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +-#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +-#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +-#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +-#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +-#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +-#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +-#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +-#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +-#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +-#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +-#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ +- +-#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +-#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ +- +- +-/* TWI.CTRL bit masks and bit positions */ +-#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +-#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ +- +-#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +-#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ +- +- +-/* PORT - Port Configuration */ +-/* PORTCFG.VPCTRLA bit masks and bit positions */ +-#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +-#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +-#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +-#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +-#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +-#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +-#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +-#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +-#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +-#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ +- +-#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +-#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +-#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +-#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +-#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +-#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +-#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +-#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +-#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +-#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ +- +- +-/* PORTCFG.VPCTRLB bit masks and bit positions */ +-#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +-#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +-#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +-#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +-#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +-#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +-#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +-#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +-#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +-#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ +- +-#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +-#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +-#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +-#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +-#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +-#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +-#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +-#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +-#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +-#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ +- +- +-/* PORTCFG.CLKEVOUT bit masks and bit positions */ +-#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +-#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +-#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +-#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +-#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +-#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ +- +-#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +-#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +-#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +-#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +-#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +-#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ +- +- +-/* VPORT.INTFLAGS bit masks and bit positions */ +-#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.INTCTRL bit masks and bit positions */ +-#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +-#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +-#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +-#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +-#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +-#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ +- +-#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +-#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +-#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +-#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +-#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +-#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ +- +- +-/* PORT.INTFLAGS bit masks and bit positions */ +-#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.PIN0CTRL bit masks and bit positions */ +-#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +-#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ +- +-#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +-#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ +- +-#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +-#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +-#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +-#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +-#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +-#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +-#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +-#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ +- +-#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +-#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +-#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +-#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +-#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +-#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +-#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +-#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +- +- +-/* PORT.PIN1CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN2CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN3CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN4CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN5CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN6CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN7CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* TC - 16-bit Timer/Counter With PWM */ +-/* TC0.CTRLA bit masks and bit positions */ +-#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC0.CTRLB bit masks and bit positions */ +-#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +-#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ +- +-#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +-#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ +- +-#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC0.CTRLC bit masks and bit positions */ +-#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +-#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ +- +-#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +-#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ +- +-#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC0.CTRLD bit masks and bit positions */ +-#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC0_EVACT_gp 5 /* Event Action group position. */ +-#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC0.CTRLE bit masks and bit positions */ +-#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +-#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ +- +-#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC0.INTCTRLA bit masks and bit positions */ +-#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC0.INTCTRLB bit masks and bit positions */ +-#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +-#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +-#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +-#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +-#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +-#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ +- +-#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +-#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +-#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +-#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +-#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +-#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ +- +-#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC0.CTRLFCLR bit masks and bit positions */ +-#define TC0_CMD_gm 0x0C /* Command group mask. */ +-#define TC0_CMD_gp 2 /* Command group position. */ +-#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC0_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC0_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC0_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC0.CTRLFSET bit masks and bit positions */ +-/* TC0_CMD_gm Predefined. */ +-/* TC0_CMD_gp Predefined. */ +-/* TC0_CMD0_bm Predefined. */ +-/* TC0_CMD0_bp Predefined. */ +-/* TC0_CMD1_bm Predefined. */ +-/* TC0_CMD1_bp Predefined. */ +- +-/* TC0_LUPD_bm Predefined. */ +-/* TC0_LUPD_bp Predefined. */ +- +-/* TC0_DIR_bm Predefined. */ +-/* TC0_DIR_bp Predefined. */ +- +- +-/* TC0.CTRLGCLR bit masks and bit positions */ +-#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +-#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ +- +-#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +-#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ +- +-#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC0.CTRLGSET bit masks and bit positions */ +-/* TC0_CCDBV_bm Predefined. */ +-/* TC0_CCDBV_bp Predefined. */ +- +-/* TC0_CCCBV_bm Predefined. */ +-/* TC0_CCCBV_bp Predefined. */ +- +-/* TC0_CCBBV_bm Predefined. */ +-/* TC0_CCBBV_bp Predefined. */ +- +-/* TC0_CCABV_bm Predefined. */ +-/* TC0_CCABV_bp Predefined. */ +- +-/* TC0_PERBV_bm Predefined. */ +-/* TC0_PERBV_bp Predefined. */ +- +- +-/* TC0.INTFLAGS bit masks and bit positions */ +-#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +-#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ +- +-#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +-#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ +- +-#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* TC1.CTRLA bit masks and bit positions */ +-#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC1.CTRLB bit masks and bit positions */ +-#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC1.CTRLC bit masks and bit positions */ +-#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC1.CTRLD bit masks and bit positions */ +-#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC1_EVACT_gp 5 /* Event Action group position. */ +-#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC1.CTRLE bit masks and bit positions */ +-#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +-#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ +- +-#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC1.INTCTRLA bit masks and bit positions */ +-#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC1.INTCTRLB bit masks and bit positions */ +-#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC1.CTRLFCLR bit masks and bit positions */ +-#define TC1_CMD_gm 0x0C /* Command group mask. */ +-#define TC1_CMD_gp 2 /* Command group position. */ +-#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC1_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC1_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC1_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC1.CTRLFSET bit masks and bit positions */ +-/* TC1_CMD_gm Predefined. */ +-/* TC1_CMD_gp Predefined. */ +-/* TC1_CMD0_bm Predefined. */ +-/* TC1_CMD0_bp Predefined. */ +-/* TC1_CMD1_bm Predefined. */ +-/* TC1_CMD1_bp Predefined. */ +- +-/* TC1_LUPD_bm Predefined. */ +-/* TC1_LUPD_bp Predefined. */ +- +-/* TC1_DIR_bm Predefined. */ +-/* TC1_DIR_bp Predefined. */ +- +- +-/* TC1.CTRLGCLR bit masks and bit positions */ +-#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC1.CTRLGSET bit masks and bit positions */ +-/* TC1_CCBBV_bm Predefined. */ +-/* TC1_CCBBV_bp Predefined. */ +- +-/* TC1_CCABV_bm Predefined. */ +-/* TC1_CCABV_bp Predefined. */ +- +-/* TC1_PERBV_bm Predefined. */ +-/* TC1_PERBV_bp Predefined. */ +- +- +-/* TC1.INTFLAGS bit masks and bit positions */ +-#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* AWEX.CTRL bit masks and bit positions */ +-#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +-#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ +- +-#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +-#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ +- +-#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +-#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ +- +-#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +-#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ +- +-#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +-#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ +- +-#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +-#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ +- +- +-/* AWEX.FDCTRL bit masks and bit positions */ +-#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +-#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ +- +-#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +-#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ +- +-#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +-#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +-#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +-#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +-#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +-#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ +- +- +-/* AWEX.STATUS bit masks and bit positions */ +-#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +-#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ +- +-#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +-#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ +- +-#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +-#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ +- +- +-/* HIRES.CTRL bit masks and bit positions */ +-#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +-#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +-#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +-#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +-#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +-#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ +- +- +-/* USART - Universal Asynchronous Receiver-Transmitter */ +-/* USART.STATUS bit masks and bit positions */ +-#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +-#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ +- +-#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +-#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +- +-#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +-#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +- +-#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +-#define USART_FERR_bp 4 /* Frame Error bit position. */ +- +-#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +-#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ +- +-#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +-#define USART_PERR_bp 2 /* Parity Error bit position. */ +- +-#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +-#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ +- +- +-/* USART.CTRLA bit masks and bit positions */ +-#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +-#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +-#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +-#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +-#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +-#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ +- +-#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +-#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +-#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +-#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +-#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +-#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ +- +-#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +-#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +-#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +-#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +-#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +-#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ +- +- +-/* USART.CTRLB bit masks and bit positions */ +-#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +-#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ +- +-#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +-#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ +- +-#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +-#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ +- +-#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +-#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ +- +-#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +-#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ +- +- +-/* USART.CTRLC bit masks and bit positions */ +-#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +-#define USART_CMODE_gp 6 /* Communication Mode group position. */ +-#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +-#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +-#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +-#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ +- +-#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +-#define USART_PMODE_gp 4 /* Parity Mode group position. */ +-#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +-#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +-#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +-#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +- +-#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +-#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +- +-#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +-#define USART_CHSIZE_gp 0 /* Character Size group position. */ +-#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +-#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +-#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +-#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +-#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +-#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +- +- +-/* USART.BAUDCTRLA bit masks and bit positions */ +-#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +-#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +-#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +-#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +-#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +-#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +-#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +-#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +-#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +-#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +-#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +-#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +-#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +-#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +-#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +-#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +-#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +-#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ +- +- +-/* USART.BAUDCTRLB bit masks and bit positions */ +-#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +-#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +-#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +-#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +-#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +-#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +-#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +-#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +-#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +-#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ +- +-/* USART_BSEL_gm Predefined. */ +-/* USART_BSEL_gp Predefined. */ +-/* USART_BSEL0_bm Predefined. */ +-/* USART_BSEL0_bp Predefined. */ +-/* USART_BSEL1_bm Predefined. */ +-/* USART_BSEL1_bp Predefined. */ +-/* USART_BSEL2_bm Predefined. */ +-/* USART_BSEL2_bp Predefined. */ +-/* USART_BSEL3_bm Predefined. */ +-/* USART_BSEL3_bp Predefined. */ +- +- +-/* SPI - Serial Peripheral Interface */ +-/* SPI.CTRL bit masks and bit positions */ +-#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +-#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ +- +-#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +-#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ +- +-#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +-#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ +- +-#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +-#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ +- +-#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +-#define SPI_MODE_gp 2 /* SPI Mode group position. */ +-#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +-#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +-#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +-#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ +- +-#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +-#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +-#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +-#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +-#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +-#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ +- +- +-/* SPI.INTCTRL bit masks and bit positions */ +-#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +-#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +-/* SPI.STATUS bit masks and bit positions */ +-#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +-#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ +- +-#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +-#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +- +- +-/* IRCOM - IR Communication Module */ +-/* IRCOM.CTRL bit masks and bit positions */ +-#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +-#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +-#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +-#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +-#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +-#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +-#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +-#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +-#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +-#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ +- +- +-/* AES - AES Module */ +-/* AES.CTRL bit masks and bit positions */ +-#define AES_START_bm 0x80 /* Start/Run bit mask. */ +-#define AES_START_bp 7 /* Start/Run bit position. */ +- +-#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +-#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ +- +-#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +-#define AES_RESET_bp 5 /* AES Software Reset bit position. */ +- +-#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +-#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ +- +-#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +-#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ +- +- +-/* AES.STATUS bit masks and bit positions */ +-#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +-#define AES_ERROR_bp 7 /* AES Error bit position. */ +- +-#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +-#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ +- +- +-/* AES.INTCTRL bit masks and bit positions */ +-#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +-#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +- +-// Generic Port Pins +- +-#define PIN0_bm 0x01 +-#define PIN0_bp 0 +-#define PIN1_bm 0x02 +-#define PIN1_bp 1 +-#define PIN2_bm 0x04 +-#define PIN2_bp 2 +-#define PIN3_bm 0x08 +-#define PIN3_bp 3 +-#define PIN4_bm 0x10 +-#define PIN4_bp 4 +-#define PIN5_bm 0x20 +-#define PIN5_bp 5 +-#define PIN6_bm 0x40 +-#define PIN6_bp 6 +-#define PIN7_bm 0x80 +-#define PIN7_bp 7 +- +- +-/* ========== Interrupt Vector Definitions ========== */ +-/* Vector 0 is the reset vector */ +- +-/* OSC interrupt vectors */ +-#define OSC_XOSCF_vect_num 1 +-#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ +- +-/* PORTC interrupt vectors */ +-#define PORTC_INT0_vect_num 2 +-#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +-#define PORTC_INT1_vect_num 3 +-#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ +- +-/* PORTR interrupt vectors */ +-#define PORTR_INT0_vect_num 4 +-#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +-#define PORTR_INT1_vect_num 5 +-#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ +- +-/* DMA interrupt vectors */ +-#define DMA_CH0_vect_num 6 +-#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +-#define DMA_CH1_vect_num 7 +-#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +-#define DMA_CH2_vect_num 8 +-#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +-#define DMA_CH3_vect_num 9 +-#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ +- +-/* RTC interrupt vectors */ +-#define RTC_OVF_vect_num 10 +-#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +-#define RTC_COMP_vect_num 11 +-#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ +- +-/* TWIC interrupt vectors */ +-#define TWIC_TWIS_vect_num 12 +-#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +-#define TWIC_TWIM_vect_num 13 +-#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ +- +-/* TCC0 interrupt vectors */ +-#define TCC0_OVF_vect_num 14 +-#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +-#define TCC0_ERR_vect_num 15 +-#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +-#define TCC0_CCA_vect_num 16 +-#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +-#define TCC0_CCB_vect_num 17 +-#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +-#define TCC0_CCC_vect_num 18 +-#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +-#define TCC0_CCD_vect_num 19 +-#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ +- +-/* TCC1 interrupt vectors */ +-#define TCC1_OVF_vect_num 20 +-#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +-#define TCC1_ERR_vect_num 21 +-#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +-#define TCC1_CCA_vect_num 22 +-#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +-#define TCC1_CCB_vect_num 23 +-#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ +- +-/* SPIC interrupt vectors */ +-#define SPIC_INT_vect_num 24 +-#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ +- +-/* USARTC0 interrupt vectors */ +-#define USARTC0_RXC_vect_num 25 +-#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +-#define USARTC0_DRE_vect_num 26 +-#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +-#define USARTC0_TXC_vect_num 27 +-#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ +- +-/* USARTC1 interrupt vectors */ +-#define USARTC1_RXC_vect_num 28 +-#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +-#define USARTC1_DRE_vect_num 29 +-#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +-#define USARTC1_TXC_vect_num 30 +-#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ +- +-/* AES interrupt vectors */ +-#define AES_INT_vect_num 31 +-#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ +- +-/* NVM interrupt vectors */ +-#define NVM_EE_vect_num 32 +-#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +-#define NVM_SPM_vect_num 33 +-#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ +- +-/* PORTB interrupt vectors */ +-#define PORTB_INT0_vect_num 34 +-#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +-#define PORTB_INT1_vect_num 35 +-#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ +- +-/* ACB interrupt vectors */ +-#define ACB_AC0_vect_num 36 +-#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ +-#define ACB_AC1_vect_num 37 +-#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ +-#define ACB_ACW_vect_num 38 +-#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ +- +-/* ADCB interrupt vectors */ +-#define ADCB_CH0_vect_num 39 +-#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ +-#define ADCB_CH1_vect_num 40 +-#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ +-#define ADCB_CH2_vect_num 41 +-#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ +-#define ADCB_CH3_vect_num 42 +-#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ +- +-/* PORTE interrupt vectors */ +-#define PORTE_INT0_vect_num 43 +-#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +-#define PORTE_INT1_vect_num 44 +-#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ +- +-/* TWIE interrupt vectors */ +-#define TWIE_TWIS_vect_num 45 +-#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +-#define TWIE_TWIM_vect_num 46 +-#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ +- +-/* TCE0 interrupt vectors */ +-#define TCE0_OVF_vect_num 47 +-#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +-#define TCE0_ERR_vect_num 48 +-#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +-#define TCE0_CCA_vect_num 49 +-#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +-#define TCE0_CCB_vect_num 50 +-#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +-#define TCE0_CCC_vect_num 51 +-#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +-#define TCE0_CCD_vect_num 52 +-#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ +- +-/* TCE1 interrupt vectors */ +-#define TCE1_OVF_vect_num 53 +-#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ +-#define TCE1_ERR_vect_num 54 +-#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ +-#define TCE1_CCA_vect_num 55 +-#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ +-#define TCE1_CCB_vect_num 56 +-#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ +- +-/* SPIE interrupt vectors */ +-#define SPIE_INT_vect_num 57 +-#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ +- +-/* USARTE0 interrupt vectors */ +-#define USARTE0_RXC_vect_num 58 +-#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +-#define USARTE0_DRE_vect_num 59 +-#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +-#define USARTE0_TXC_vect_num 60 +-#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ +- +-/* USARTE1 interrupt vectors */ +-#define USARTE1_RXC_vect_num 61 +-#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ +-#define USARTE1_DRE_vect_num 62 +-#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ +-#define USARTE1_TXC_vect_num 63 +-#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ +- +-/* PORTD interrupt vectors */ +-#define PORTD_INT0_vect_num 64 +-#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +-#define PORTD_INT1_vect_num 65 +-#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ +- +-/* PORTA interrupt vectors */ +-#define PORTA_INT0_vect_num 66 +-#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +-#define PORTA_INT1_vect_num 67 +-#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ +- +-/* ACA interrupt vectors */ +-#define ACA_AC0_vect_num 68 +-#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +-#define ACA_AC1_vect_num 69 +-#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +-#define ACA_ACW_vect_num 70 +-#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ +- +-/* ADCA interrupt vectors */ +-#define ADCA_CH0_vect_num 71 +-#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +-#define ADCA_CH1_vect_num 72 +-#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +-#define ADCA_CH2_vect_num 73 +-#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +-#define ADCA_CH3_vect_num 74 +-#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ +- +-/* TCD0 interrupt vectors */ +-#define TCD0_OVF_vect_num 77 +-#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +-#define TCD0_ERR_vect_num 78 +-#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +-#define TCD0_CCA_vect_num 79 +-#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +-#define TCD0_CCB_vect_num 80 +-#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +-#define TCD0_CCC_vect_num 81 +-#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +-#define TCD0_CCD_vect_num 82 +-#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ +- +-/* TCD1 interrupt vectors */ +-#define TCD1_OVF_vect_num 83 +-#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +-#define TCD1_ERR_vect_num 84 +-#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +-#define TCD1_CCA_vect_num 85 +-#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +-#define TCD1_CCB_vect_num 86 +-#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ +- +-/* SPID interrupt vectors */ +-#define SPID_INT_vect_num 87 +-#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ +- +-/* USARTD0 interrupt vectors */ +-#define USARTD0_RXC_vect_num 88 +-#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +-#define USARTD0_DRE_vect_num 89 +-#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +-#define USARTD0_TXC_vect_num 90 +-#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ +- +-/* USARTD1 interrupt vectors */ +-#define USARTD1_RXC_vect_num 91 +-#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +-#define USARTD1_DRE_vect_num 92 +-#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +-#define USARTD1_TXC_vect_num 93 +-#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ +- +-/* PORTF interrupt vectors */ +-#define PORTF_INT0_vect_num 104 +-#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +-#define PORTF_INT1_vect_num 105 +-#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ +- +-/* TCF0 interrupt vectors */ +-#define TCF0_OVF_vect_num 108 +-#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ +-#define TCF0_ERR_vect_num 109 +-#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ +-#define TCF0_CCA_vect_num 110 +-#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ +-#define TCF0_CCB_vect_num 111 +-#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ +-#define TCF0_CCC_vect_num 112 +-#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ +-#define TCF0_CCD_vect_num 113 +-#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ +- +-/* USARTF0 interrupt vectors */ +-#define USARTF0_RXC_vect_num 119 +-#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ +-#define USARTF0_DRE_vect_num 120 +-#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ +-#define USARTF0_TXC_vect_num 121 +-#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ +- +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (122 * _VECTOR_SIZE) +- +- +-/* ========== Constants ========== */ +- +-#define PROGMEM_START (0x0000) +-#define PROGMEM_SIZE (204800) +-#define PROGMEM_PAGE_SIZE (512) +-#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) +- +-#define APP_SECTION_START (0x0000) +-#define APP_SECTION_SIZE (196608) +-#define APP_SECTION_PAGE_SIZE (512) +-#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) +- +-#define APPTABLE_SECTION_START (0x2E000) +-#define APPTABLE_SECTION_SIZE (8192) +-#define APPTABLE_SECTION_PAGE_SIZE (512) +-#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) +- +-#define BOOT_SECTION_START (0x30000) +-#define BOOT_SECTION_SIZE (8192) +-#define BOOT_SECTION_PAGE_SIZE (512) +-#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) +- +-#define DATAMEM_START (0x0000) +-#define DATAMEM_SIZE (16777216) +-#define DATAMEM_PAGE_SIZE (0) +-#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) +- +-#define IO_START (0x0000) +-#define IO_SIZE (4096) +-#define IO_PAGE_SIZE (0) +-#define IO_END (IO_START + IO_SIZE - 1) +- +-#define MAPPED_EEPROM_START (0x1000) +-#define MAPPED_EEPROM_SIZE (2048) +-#define MAPPED_EEPROM_PAGE_SIZE (0) +-#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) +- +-#define INTERNAL_SRAM_START (0x2000) +-#define INTERNAL_SRAM_SIZE (16384) +-#define INTERNAL_SRAM_PAGE_SIZE (0) +-#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) +- +-#define EEPROM_START (0x0000) +-#define EEPROM_SIZE (2048) +-#define EEPROM_PAGE_SIZE (32) +-#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) +- +-#define FUSE_START (0x0000) +-#define FUSE_SIZE (6) +-#define FUSE_PAGE_SIZE (0) +-#define FUSE_END (FUSE_START + FUSE_SIZE - 1) +- +-#define LOCKBIT_START (0x0000) +-#define LOCKBIT_SIZE (1) +-#define LOCKBIT_PAGE_SIZE (0) +-#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) +- +-#define SIGNATURES_START (0x0000) +-#define SIGNATURES_SIZE (3) +-#define SIGNATURES_PAGE_SIZE (0) +-#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) +- +-#define USER_SIGNATURES_START (0x0000) +-#define USER_SIGNATURES_SIZE (512) +-#define USER_SIGNATURES_PAGE_SIZE (0) +-#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) +- +-#define PROD_SIGNATURES_START (0x0000) +-#define PROD_SIGNATURES_SIZE (52) +-#define PROD_SIGNATURES_PAGE_SIZE (0) +-#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) +- +-#define FLASHEND PROGMEM_END +-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +-#define RAMSTART INTERNAL_SRAM_START +-#define RAMSIZE INTERNAL_SRAM_SIZE +-#define RAMEND INTERNAL_SRAM_END +-#define XRAMSTART EXTERNAL_SRAM_START +-#define XRAMSIZE EXTERNAL_SRAM_SIZE +-#define XRAMEND INTERNAL_SRAM_END +-#define E2END EEPROM_END +-#define E2PAGESIZE EEPROM_PAGE_SIZE +- +- +-/* ========== Fuses ========== */ +-#define FUSE_MEMORY_SIZE 6 +- +-/* Fuse Byte 0 */ +-#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ +-#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ +-#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ +-#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ +-#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ +-#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ +-#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ +-#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ +-#define FUSE0_DEFAULT (0xFF) +- +-/* Fuse Byte 1 */ +-#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +-#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +-#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +-#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +-#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +-#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +-#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +-#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +-#define FUSE1_DEFAULT (0xFF) +- +-/* Fuse Byte 2 */ +-#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +-#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +-#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +-#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +-#define FUSE2_DEFAULT (0xFF) +- +-/* Fuse Byte 3 Reserved */ +- +-/* Fuse Byte 4 */ +-#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ +-#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +-#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +-#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +-#define FUSE4_DEFAULT (0xFF) +- +-/* Fuse Byte 5 */ +-#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +-#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +-#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +-#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +-#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +-#define FUSE5_DEFAULT (0xFF) +- +- +-/* ========== Lock Bits ========== */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_BITS_EXIST +-#define __BOOT_LOCK_BOOT_BITS_EXIST +- +- +-/* ========== Signature ========== */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x97 +-#define SIGNATURE_2 0x44 +- +- +-#endif /* _AVR_ATxmega192A3_H_ */ +- ++/* Copyright (c) 2009-2010 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iox192a3.h 2218 2011-02-21 19:43:03Z arcanum $ */ ++ ++/* avr/iox192a3.h - definitions for ATxmega192A3 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox192a3.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATxmega192A3_H_ ++#define _AVR_ATxmega192A3_H_ 1 ++ ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++} CLK_t; ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t PRPB; /* Power Reduction Port B */ ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ ++} CLK_RTCSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control REgister */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t reserved_0x07; ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Channel */ ++typedef struct DMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Address Control */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ ++ register8_t REPCNT; /* Channel Repeat Count */ ++ register8_t reserved_0x07; ++ register8_t SRCADDR0; /* Channel Source Address 0 */ ++ register8_t SRCADDR1; /* Channel Source Address 1 */ ++ register8_t SRCADDR2; /* Channel Source Address 2 */ ++ register8_t reserved_0x0B; ++ register8_t DESTADDR0; /* Channel Destination Address 0 */ ++ register8_t DESTADDR1; /* Channel Destination Address 1 */ ++ register8_t DESTADDR2; /* Channel Destination Address 2 */ ++ register8_t reserved_0x0F; ++} DMA_CH_t; ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Controller */ ++typedef struct DMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ DMA_CH_t CH0; /* DMA Channel 0 */ ++ DMA_CH_t CH1; /* DMA Channel 1 */ ++ DMA_CH_t CH2; /* DMA Channel 2 */ ++ DMA_CH_t CH3; /* DMA Channel 3 */ ++} DMA_t; ++ ++/* Burst mode */ ++typedef enum DMA_CH_BURSTLEN_enum ++{ ++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ ++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ ++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ ++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ ++} DMA_CH_BURSTLEN_t; ++ ++/* Source address reload mode */ ++typedef enum DMA_CH_SRCRELOAD_enum ++{ ++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ ++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ ++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ ++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ ++} DMA_CH_SRCRELOAD_t; ++ ++/* Source addressing mode */ ++typedef enum DMA_CH_SRCDIR_enum ++{ ++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ ++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ ++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ ++} DMA_CH_SRCDIR_t; ++ ++/* Destination adress reload mode */ ++typedef enum DMA_CH_DESTRELOAD_enum ++{ ++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ ++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ ++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ ++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ ++} DMA_CH_DESTRELOAD_t; ++ ++/* Destination adressing mode */ ++typedef enum DMA_CH_DESTDIR_enum ++{ ++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ ++} DMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum DMA_CH_TRIGSRC_enum ++{ ++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ ++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ ++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ ++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ ++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ ++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ ++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ ++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ ++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ ++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ ++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ ++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ ++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ ++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ ++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ ++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ ++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ ++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ ++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ ++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ ++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ ++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ ++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ ++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ ++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ ++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ ++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ ++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ ++} DMA_CH_TRIGSRC_t; ++ ++/* Double buffering mode */ ++typedef enum DMA_DBUFMODE_enum ++{ ++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ ++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ ++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ ++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ ++} DMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum DMA_PRIMODE_enum ++{ ++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ ++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ ++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ ++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ ++} DMA_PRIMODE_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_ERRINTLVL_enum ++{ ++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ ++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ ++} DMA_CH_ERRINTLVL_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_TRNINTLVL_enum ++{ ++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ ++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ ++} DMA_CH_TRNINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ ++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ ++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ ++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t CH4CTRL; /* Channel 4 Control Register */ ++ register8_t CH5CTRL; /* Channel 5 Control Register */ ++ register8_t CH6CTRL; /* Channel 6 Control Register */ ++ register8_t CH7CTRL; /* Channel 7 Control Register */ ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ ++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ ++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ ++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ ++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ ++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ ++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ ++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ ++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ ++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ ++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ ++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ ++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ ++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ ++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ ++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ ++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ ++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t FUSEBYTE0; /* JTAG User ID */ ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ ++ register8_t reserved_0x01; ++ register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ ++ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ ++ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ ++ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++} NVM_PROD_SIGNATURES_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++} NVM_LB_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brown Out Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ ++ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Comparator 0 Control */ ++ register8_t AC1CTRL; /* Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t reserved_0x6; ++ register8_t reserved_0x7; ++} ADC_CH_t; ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ _WORDREGISTER(CH1RES); /* Channel 1 Result */ ++ _WORDREGISTER(CH2RES); /* Channel 2 Result */ ++ _WORDREGISTER(CH3RES); /* Channel 3 Result */ ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++ ADC_CH_t CH1; /* ADC Channel 1 */ ++ ADC_CH_t CH2; /* ADC Channel 2 */ ++ ADC_CH_t CH3; /* ADC Channel 3 */ ++} ADC_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++} ADC_REFSEL_t; ++ ++/* Channel sweep selection */ ++typedef enum ADC_SWEEP_enum ++{ ++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ ++} ADC_SWEEP_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ++ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* DMA request selection */ ++typedef enum ADC_DMASEL_enum ++{ ++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ ++} ADC_DMASEL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DAC - Digital/Analog Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Digital-to-Analog Converter */ ++typedef struct DAC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t EVCTRL; /* Event Input Control */ ++ register8_t TIMCTRL; /* Timing Control */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t GAINCAL; /* Gain Calibration */ ++ register8_t OFFSETCAL; /* Offset Calibration */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ ++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ ++} DAC_t; ++ ++/* Output channel selection */ ++typedef enum DAC_CHSEL_enum ++{ ++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ ++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ ++} DAC_CHSEL_t; ++ ++/* Reference voltage selection */ ++typedef enum DAC_REFSEL_enum ++{ ++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ ++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ ++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ ++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ ++} DAC_REFSEL_t; ++ ++/* Event channel selection */ ++typedef enum DAC_EVSEL_enum ++{ ++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ ++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ ++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ ++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ ++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ ++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ ++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ ++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ ++} DAC_EVSEL_t; ++ ++/* Conversion interval */ ++typedef enum DAC_CONINTVAL_enum ++{ ++ DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ ++ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ ++ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ ++ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ ++ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ ++ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ ++ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ ++ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ ++} DAC_CONINTVAL_t; ++ ++/* Refresh rate */ ++typedef enum DAC_REFRESH_enum ++{ ++ DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ ++ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ ++ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ ++ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ ++ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ ++ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ ++ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ ++ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ ++ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ ++ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ ++ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ ++ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ ++ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ ++ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ ++} DAC_REFRESH_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Clounter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* EBI Chip Select Module */ ++typedef struct EBI_CS_struct ++{ ++ register8_t CTRLA; /* Chip Select Control Register A */ ++ register8_t CTRLB; /* Chip Select Control Register B */ ++ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ ++} EBI_CS_t; ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* External Bus Interface */ ++typedef struct EBI_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ ++ register8_t reserved_0x02; ++ register8_t reserved_0x03; ++ _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ ++ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ ++ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ ++ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ EBI_CS_t CS0; /* Chip Select 0 */ ++ EBI_CS_t CS1; /* Chip Select 1 */ ++ EBI_CS_t CS2; /* Chip Select 2 */ ++ EBI_CS_t CS3; /* Chip Select 3 */ ++} EBI_t; ++ ++/* Chip Select adress space */ ++typedef enum EBI_CS_ASIZE_enum ++{ ++ EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ ++ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ ++ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ ++ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ ++ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ ++ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ ++ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ ++ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ ++ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ ++ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ ++ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ ++ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ ++ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ ++ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ ++ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ ++ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ ++ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ ++} EBI_CS_ASIZE_t; ++ ++/* */ ++typedef enum EBI_CS_SRWS_enum ++{ ++ EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_CS_SRWS_t; ++ ++/* Chip Select address mode */ ++typedef enum EBI_CS_MODE_enum ++{ ++ EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ ++ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ ++ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ ++ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ ++} EBI_CS_MODE_t; ++ ++/* Chip Select SDRAM mode */ ++typedef enum EBI_CS_SDMODE_enum ++{ ++ EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ ++ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ ++} EBI_CS_SDMODE_t; ++ ++/* */ ++typedef enum EBI_SDDATAW_enum ++{ ++ EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ ++ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ ++} EBI_SDDATAW_t; ++ ++/* */ ++typedef enum EBI_LPCMODE_enum ++{ ++ EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ ++ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ ++} EBI_LPCMODE_t; ++ ++/* */ ++typedef enum EBI_SRMODE_enum ++{ ++ EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ ++ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ ++ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ ++ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ ++} EBI_SRMODE_t; ++ ++/* */ ++typedef enum EBI_IFMODE_enum ++{ ++ EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ ++ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ ++ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ ++ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ ++} EBI_IFMODE_t; ++ ++/* */ ++typedef enum EBI_SDCOL_enum ++{ ++ EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ ++ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ ++ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ ++ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ ++} EBI_SDCOL_t; ++ ++/* */ ++typedef enum EBI_MRDLY_enum ++{ ++ EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_MRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCYCDLY_enum ++{ ++ EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ROWCYCDLY_t; ++ ++/* */ ++typedef enum EBI_RPDLY_enum ++{ ++ EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_RPDLY_t; ++ ++/* */ ++typedef enum EBI_WRDLY_enum ++{ ++ EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_WRDLY_t; ++ ++/* */ ++typedef enum EBI_ESRDLY_enum ++{ ++ EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ESRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCOLDLY_enum ++{ ++ EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_ROWCOLDLY_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++} PORTCFG_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Virtual Port 0 Mapping */ ++typedef enum PORTCFG_VP0MAP_enum ++{ ++ PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP0MAP_t; ++ ++/* Virtual Port 1 Mapping */ ++typedef enum PORTCFG_VP1MAP_enum ++{ ++ PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP1MAP_t; ++ ++/* Virtual Port 2 Mapping */ ++typedef enum PORTCFG_VP2MAP_enum ++{ ++ PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP2MAP_t; ++ ++/* Virtual Port 3 Mapping */ ++typedef enum PORTCFG_VP3MAP_enum ++{ ++ PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP3MAP_t; ++ ++/* Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x05; ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AES - AES Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* AES Module */ ++typedef struct AES_struct ++{ ++ register8_t CTRL; /* AES Control Register */ ++ register8_t STATUS; /* AES Status Register */ ++ register8_t STATE; /* AES State Register */ ++ register8_t KEY; /* AES Key Register */ ++ register8_t INTCTRL; /* AES Interrupt Control Register */ ++} AES_t; ++ ++/* Interrupt level */ ++typedef enum AES_INTLVL_enum ++{ ++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} AES_INTLVL_t; ++ ++ ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset Controller */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ ++#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ ++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ ++#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ ++#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ ++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ ++#define PORTA (*(PORT_t *) 0x0600) /* Port A */ ++#define PORTB (*(PORT_t *) 0x0620) /* Port B */ ++#define PORTC (*(PORT_t *) 0x0640) /* Port C */ ++#define PORTD (*(PORT_t *) 0x0660) /* Port D */ ++#define PORTE (*(PORT_t *) 0x0680) /* Port E */ ++#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ ++#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ ++#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ ++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ ++#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ ++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ ++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ ++#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ ++#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ ++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ ++#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ ++#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ ++#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ ++#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ ++#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ ++#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ ++#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++#define GPIO_GPIOR4 _SFR_MEM8(0x0004) ++#define GPIO_GPIOR5 _SFR_MEM8(0x0005) ++#define GPIO_GPIOR6 _SFR_MEM8(0x0006) ++#define GPIO_GPIOR7 _SFR_MEM8(0x0007) ++#define GPIO_GPIOR8 _SFR_MEM8(0x0008) ++#define GPIO_GPIOR9 _SFR_MEM8(0x0009) ++#define GPIO_GPIORA _SFR_MEM8(0x000A) ++#define GPIO_GPIORB _SFR_MEM8(0x000B) ++#define GPIO_GPIORC _SFR_MEM8(0x000C) ++#define GPIO_GPIORD _SFR_MEM8(0x000D) ++#define GPIO_GPIORE _SFR_MEM8(0x000E) ++#define GPIO_GPIORF _SFR_MEM8(0x000F) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++#define GPIO_GPIO4 _SFR_MEM8(0x0004) ++#define GPIO_GPIO5 _SFR_MEM8(0x0005) ++#define GPIO_GPIO6 _SFR_MEM8(0x0006) ++#define GPIO_GPIO7 _SFR_MEM8(0x0007) ++#define GPIO_GPIO8 _SFR_MEM8(0x0008) ++#define GPIO_GPIO9 _SFR_MEM8(0x0009) ++#define GPIO_GPIOA _SFR_MEM8(0x000A) ++#define GPIO_GPIOB _SFR_MEM8(0x000B) ++#define GPIO_GPIOC _SFR_MEM8(0x000C) ++#define GPIO_GPIOD _SFR_MEM8(0x000D) ++#define GPIO_GPIOE _SFR_MEM8(0x000E) ++#define GPIO_GPIOF _SFR_MEM8(0x000F) ++ ++/* VPORT0 - Virtual Port 0 */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT1 - Virtual Port 1 */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT2 - Virtual Port 2 */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT3 - Virtual Port 3 */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU Registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator Control */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPB _SFR_MEM8(0x0072) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset Controller */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - Port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++ ++/* AES - AES Crypto Module */ ++#define AES_CTRL _SFR_MEM8(0x00C0) ++#define AES_STATUS _SFR_MEM8(0x00C1) ++#define AES_STATE _SFR_MEM8(0x00C2) ++#define AES_KEY _SFR_MEM8(0x00C3) ++#define AES_INTCTRL _SFR_MEM8(0x00C4) ++ ++/* DMA - DMA Controller */ ++#define DMA_CTRL _SFR_MEM8(0x0100) ++#define DMA_INTFLAGS _SFR_MEM8(0x0103) ++#define DMA_STATUS _SFR_MEM8(0x0104) ++#define DMA_TEMP _SFR_MEM16(0x0106) ++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) ++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) ++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) ++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) ++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) ++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) ++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) ++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) ++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) ++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) ++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) ++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) ++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) ++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) ++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) ++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) ++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) ++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) ++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) ++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) ++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) ++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) ++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) ++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) ++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) ++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) ++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) ++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) ++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) ++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) ++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) ++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) ++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) ++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) ++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) ++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) ++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) ++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) ++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) ++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) ++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) ++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH4MUX _SFR_MEM8(0x0184) ++#define EVSYS_CH5MUX _SFR_MEM8(0x0185) ++#define EVSYS_CH6MUX _SFR_MEM8(0x0186) ++#define EVSYS_CH7MUX _SFR_MEM8(0x0187) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) ++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) ++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) ++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non Volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADCA - Analog to Digital Converter A */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CH1RES _SFR_MEM16(0x0212) ++#define ADCA_CH2RES _SFR_MEM16(0x0214) ++#define ADCA_CH3RES _SFR_MEM16(0x0216) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) ++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) ++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) ++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) ++#define ADCA_CH1_RES _SFR_MEM16(0x022C) ++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) ++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) ++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) ++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) ++#define ADCA_CH2_RES _SFR_MEM16(0x0234) ++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) ++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) ++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) ++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) ++#define ADCA_CH3_RES _SFR_MEM16(0x023C) ++ ++/* ADCB - Analog to Digital Converter B */ ++#define ADCB_CTRLA _SFR_MEM8(0x0240) ++#define ADCB_CTRLB _SFR_MEM8(0x0241) ++#define ADCB_REFCTRL _SFR_MEM8(0x0242) ++#define ADCB_EVCTRL _SFR_MEM8(0x0243) ++#define ADCB_PRESCALER _SFR_MEM8(0x0244) ++#define ADCB_INTFLAGS _SFR_MEM8(0x0246) ++#define ADCB_CAL _SFR_MEM16(0x024C) ++#define ADCB_CH0RES _SFR_MEM16(0x0250) ++#define ADCB_CH1RES _SFR_MEM16(0x0252) ++#define ADCB_CH2RES _SFR_MEM16(0x0254) ++#define ADCB_CH3RES _SFR_MEM16(0x0256) ++#define ADCB_CMP _SFR_MEM16(0x0258) ++#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) ++#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) ++#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) ++#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) ++#define ADCB_CH0_RES _SFR_MEM16(0x0264) ++#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) ++#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) ++#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) ++#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) ++#define ADCB_CH1_RES _SFR_MEM16(0x026C) ++#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) ++#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) ++#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) ++#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) ++#define ADCB_CH2_RES _SFR_MEM16(0x0274) ++#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) ++#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) ++#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) ++#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) ++#define ADCB_CH3_RES _SFR_MEM16(0x027C) ++ ++/* DACB - Digital to Analog Converter B */ ++#define DACB_CTRLA _SFR_MEM8(0x0320) ++#define DACB_CTRLB _SFR_MEM8(0x0321) ++#define DACB_CTRLC _SFR_MEM8(0x0322) ++#define DACB_EVCTRL _SFR_MEM8(0x0323) ++#define DACB_TIMCTRL _SFR_MEM8(0x0324) ++#define DACB_STATUS _SFR_MEM8(0x0325) ++#define DACB_GAINCAL _SFR_MEM8(0x0328) ++#define DACB_OFFSETCAL _SFR_MEM8(0x0329) ++#define DACB_CH0DATA _SFR_MEM16(0x0338) ++#define DACB_CH1DATA _SFR_MEM16(0x033A) ++ ++/* ACA - Analog Comparator A */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* ACB - Analog Comparator B */ ++#define ACB_AC0CTRL _SFR_MEM8(0x0390) ++#define ACB_AC1CTRL _SFR_MEM8(0x0391) ++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) ++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) ++#define ACB_CTRLA _SFR_MEM8(0x0394) ++#define ACB_CTRLB _SFR_MEM8(0x0395) ++#define ACB_WINCTRL _SFR_MEM8(0x0396) ++#define ACB_STATUS _SFR_MEM8(0x0397) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWIC - Two-Wire Interface C */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWIE - Two-Wire Interface E */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* PORTA - Port A */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORTB - Port B */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORTC - Port C */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORTD - Port D */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORTE - Port E */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORTF - Port F */ ++#define PORTF_DIR _SFR_MEM8(0x06A0) ++#define PORTF_DIRSET _SFR_MEM8(0x06A1) ++#define PORTF_DIRCLR _SFR_MEM8(0x06A2) ++#define PORTF_DIRTGL _SFR_MEM8(0x06A3) ++#define PORTF_OUT _SFR_MEM8(0x06A4) ++#define PORTF_OUTSET _SFR_MEM8(0x06A5) ++#define PORTF_OUTCLR _SFR_MEM8(0x06A6) ++#define PORTF_OUTTGL _SFR_MEM8(0x06A7) ++#define PORTF_IN _SFR_MEM8(0x06A8) ++#define PORTF_INTCTRL _SFR_MEM8(0x06A9) ++#define PORTF_INT0MASK _SFR_MEM8(0x06AA) ++#define PORTF_INT1MASK _SFR_MEM8(0x06AB) ++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) ++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) ++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) ++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) ++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) ++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) ++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) ++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) ++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) ++ ++/* PORTR - Port R */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TCC0 - Timer/Counter C0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TCC1 - Timer/Counter C1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEXC - Advanced Waveform Extension C */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRESC - High-Resolution Extension C */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ ++#define USARTC1_DATA _SFR_MEM8(0x08B0) ++#define USARTC1_STATUS _SFR_MEM8(0x08B1) ++#define USARTC1_CTRLA _SFR_MEM8(0x08B3) ++#define USARTC1_CTRLB _SFR_MEM8(0x08B4) ++#define USARTC1_CTRLC _SFR_MEM8(0x08B5) ++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) ++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) ++ ++/* SPIC - Serial Peripheral Interface C */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TCD0 - Timer/Counter D0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TCD1 - Timer/Counter D1 */ ++#define TCD1_CTRLA _SFR_MEM8(0x0940) ++#define TCD1_CTRLB _SFR_MEM8(0x0941) ++#define TCD1_CTRLC _SFR_MEM8(0x0942) ++#define TCD1_CTRLD _SFR_MEM8(0x0943) ++#define TCD1_CTRLE _SFR_MEM8(0x0944) ++#define TCD1_INTCTRLA _SFR_MEM8(0x0946) ++#define TCD1_INTCTRLB _SFR_MEM8(0x0947) ++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) ++#define TCD1_CTRLFSET _SFR_MEM8(0x0949) ++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) ++#define TCD1_CTRLGSET _SFR_MEM8(0x094B) ++#define TCD1_INTFLAGS _SFR_MEM8(0x094C) ++#define TCD1_TEMP _SFR_MEM8(0x094F) ++#define TCD1_CNT _SFR_MEM16(0x0960) ++#define TCD1_PER _SFR_MEM16(0x0966) ++#define TCD1_CCA _SFR_MEM16(0x0968) ++#define TCD1_CCB _SFR_MEM16(0x096A) ++#define TCD1_PERBUF _SFR_MEM16(0x0976) ++#define TCD1_CCABUF _SFR_MEM16(0x0978) ++#define TCD1_CCBBUF _SFR_MEM16(0x097A) ++ ++/* HIRESD - High-Resolution Extension D */ ++#define HIRESD_CTRLA _SFR_MEM8(0x0990) ++ ++/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ ++#define USARTD1_DATA _SFR_MEM8(0x09B0) ++#define USARTD1_STATUS _SFR_MEM8(0x09B1) ++#define USARTD1_CTRLA _SFR_MEM8(0x09B3) ++#define USARTD1_CTRLB _SFR_MEM8(0x09B4) ++#define USARTD1_CTRLC _SFR_MEM8(0x09B5) ++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) ++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) ++ ++/* SPID - Serial Peripheral Interface D */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TCE0 - Timer/Counter E0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* TCE1 - Timer/Counter E1 */ ++#define TCE1_CTRLA _SFR_MEM8(0x0A40) ++#define TCE1_CTRLB _SFR_MEM8(0x0A41) ++#define TCE1_CTRLC _SFR_MEM8(0x0A42) ++#define TCE1_CTRLD _SFR_MEM8(0x0A43) ++#define TCE1_CTRLE _SFR_MEM8(0x0A44) ++#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) ++#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) ++#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) ++#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) ++#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) ++#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) ++#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) ++#define TCE1_TEMP _SFR_MEM8(0x0A4F) ++#define TCE1_CNT _SFR_MEM16(0x0A60) ++#define TCE1_PER _SFR_MEM16(0x0A66) ++#define TCE1_CCA _SFR_MEM16(0x0A68) ++#define TCE1_CCB _SFR_MEM16(0x0A6A) ++#define TCE1_PERBUF _SFR_MEM16(0x0A76) ++#define TCE1_CCABUF _SFR_MEM16(0x0A78) ++#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) ++ ++/* AWEXE - Advanced Waveform Extension E */ ++#define AWEXE_CTRL _SFR_MEM8(0x0A80) ++#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) ++#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) ++#define AWEXE_STATUS _SFR_MEM8(0x0A84) ++#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) ++#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) ++#define AWEXE_DTLS _SFR_MEM8(0x0A88) ++#define AWEXE_DTHS _SFR_MEM8(0x0A89) ++#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) ++#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) ++#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) ++ ++/* HIRESE - High-Resolution Extension E */ ++#define HIRESE_CTRLA _SFR_MEM8(0x0A90) ++ ++/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ ++#define USARTE1_DATA _SFR_MEM8(0x0AB0) ++#define USARTE1_STATUS _SFR_MEM8(0x0AB1) ++#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) ++#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) ++#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) ++#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) ++#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) ++ ++/* SPIE - Serial Peripheral Interface E */ ++#define SPIE_CTRL _SFR_MEM8(0x0AC0) ++#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) ++#define SPIE_STATUS _SFR_MEM8(0x0AC2) ++#define SPIE_DATA _SFR_MEM8(0x0AC3) ++ ++/* TCF0 - Timer/Counter F0 */ ++#define TCF0_CTRLA _SFR_MEM8(0x0B00) ++#define TCF0_CTRLB _SFR_MEM8(0x0B01) ++#define TCF0_CTRLC _SFR_MEM8(0x0B02) ++#define TCF0_CTRLD _SFR_MEM8(0x0B03) ++#define TCF0_CTRLE _SFR_MEM8(0x0B04) ++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) ++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) ++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) ++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) ++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF0_TEMP _SFR_MEM8(0x0B0F) ++#define TCF0_CNT _SFR_MEM16(0x0B20) ++#define TCF0_PER _SFR_MEM16(0x0B26) ++#define TCF0_CCA _SFR_MEM16(0x0B28) ++#define TCF0_CCB _SFR_MEM16(0x0B2A) ++#define TCF0_CCC _SFR_MEM16(0x0B2C) ++#define TCF0_CCD _SFR_MEM16(0x0B2E) ++#define TCF0_PERBUF _SFR_MEM16(0x0B36) ++#define TCF0_CCABUF _SFR_MEM16(0x0B38) ++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) ++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) ++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) ++ ++/* HIRESF - High-Resolution Extension F */ ++#define HIRESF_CTRLA _SFR_MEM8(0x0B90) ++ ++/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ ++#define USARTF0_DATA _SFR_MEM8(0x0BA0) ++#define USARTF0_STATUS _SFR_MEM8(0x0BA1) ++#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) ++#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) ++#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) ++#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) ++#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) ++ ++/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ ++#define USARTF1_DATA _SFR_MEM8(0x0BB0) ++#define USARTF1_STATUS _SFR_MEM8(0x0BB1) ++#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) ++#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) ++#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) ++#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) ++#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) ++ ++/* SPIF - Serial Peripheral Interface F */ ++#define SPIF_CTRL _SFR_MEM8(0x0BC0) ++#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) ++#define SPIF_STATUS _SFR_MEM8(0x0BC2) ++#define SPIF_DATA _SFR_MEM8(0x0BC3) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR1 bit masks and bit positions */ ++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ ++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ ++ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ ++ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ ++#define PR_EBI_bp 3 /* External Bus Interface bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ ++#define PR_DAC_bp 2 /* Port A DAC bit position. */ ++ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++ ++/* PR.PRPB bit masks and bit positions */ ++/* PR_DAC_bm Predefined. */ ++/* PR_DAC_bp Predefined. */ ++ ++/* PR_ADC_bm Predefined. */ ++/* PR_ADC_bp Predefined. */ ++ ++/* PR_AC_bm Predefined. */ ++/* PR_AC_bp Predefined. */ ++ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ ++ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ ++ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ ++ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ ++#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ ++ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ ++ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ ++ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ ++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ ++ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++ ++/* DMA - DMA Controller */ ++/* DMA_CH.CTRLA bit masks and bit positions */ ++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ ++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ ++ ++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ ++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ ++ ++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ ++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ ++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ ++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ ++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ ++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ ++ ++ ++/* DMA_CH.CTRLB bit masks and bit positions */ ++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ ++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ ++ ++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ ++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ ++ ++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ ++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ ++ ++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ ++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ ++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ ++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ ++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ ++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ ++ ++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ ++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ ++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ ++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ ++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ ++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ ++ ++ ++/* DMA_CH.ADDRCTRL bit masks and bit positions */ ++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ ++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ ++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ ++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ ++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ ++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ ++ ++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ ++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ ++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ ++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ ++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ ++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ ++ ++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ ++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ ++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ ++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ ++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ ++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ ++ ++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ ++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ ++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ ++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ ++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ ++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ ++ ++ ++/* DMA_CH.TRIGSRC bit masks and bit positions */ ++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++ ++/* DMA.CTRL bit masks and bit positions */ ++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define DMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define DMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ ++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ ++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ ++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ ++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ ++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ ++ ++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ ++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ ++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ ++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ ++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ ++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ ++ ++ ++/* DMA.INTFLAGS bit masks and bit positions */ ++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++ ++/* DMA.STATUS bit masks and bit positions */ ++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ ++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ ++ ++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ ++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ ++ ++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ ++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ ++ ++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ ++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ ++ ++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ ++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ ++ ++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ ++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ ++ ++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ ++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ ++ ++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ ++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ ++ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH4MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH5MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH6MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH7MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM_gm Predefined. */ ++/* EVSYS_QDIRM_gp Predefined. */ ++/* EVSYS_QDIRM0_bm Predefined. */ ++/* EVSYS_QDIRM0_bp Predefined. */ ++/* EVSYS_QDIRM1_bm Predefined. */ ++/* EVSYS_QDIRM1_bp Predefined. */ ++ ++/* EVSYS_QDIEN_bm Predefined. */ ++/* EVSYS_QDIEN_bp Predefined. */ ++ ++/* EVSYS_QDEN_bm Predefined. */ ++/* EVSYS_QDEN_bp Predefined. */ ++ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH4CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM_gm Predefined. */ ++/* EVSYS_QDIRM_gp Predefined. */ ++/* EVSYS_QDIRM0_bm Predefined. */ ++/* EVSYS_QDIRM0_bp Predefined. */ ++/* EVSYS_QDIRM1_bm Predefined. */ ++/* EVSYS_QDIRM1_bp Predefined. */ ++ ++/* EVSYS_QDIEN_bm Predefined. */ ++/* EVSYS_QDIEN_bp Predefined. */ ++ ++/* EVSYS_QDEN_bm Predefined. */ ++/* EVSYS_QDEN_bp Predefined. */ ++ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH5CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH6CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH7CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0xFF /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ ++#define NVM_CMD7_bp 7 /* Command bit 7 position. */ ++ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ ++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ ++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ ++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ ++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ ++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ ++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ ++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ ++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ ++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ ++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ ++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ ++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ ++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ ++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ ++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ ++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ ++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ ++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ ++#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ ++ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ ++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ ++ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ ++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE_gm Predefined. */ ++/* AC_INTMODE_gp Predefined. */ ++/* AC_INTMODE0_bm Predefined. */ ++/* AC_INTMODE0_bp Predefined. */ ++/* AC_INTMODE1_bm Predefined. */ ++/* AC_INTMODE1_bp Predefined. */ ++ ++/* AC_INTLVL_gm Predefined. */ ++/* AC_INTLVL_gp Predefined. */ ++/* AC_INTLVL0_bm Predefined. */ ++/* AC_INTLVL0_bp Predefined. */ ++/* AC_INTLVL1_bm Predefined. */ ++/* AC_INTLVL1_bp Predefined. */ ++ ++/* AC_HSMODE_bm Predefined. */ ++/* AC_HSMODE_bp Predefined. */ ++ ++/* AC_HYSMODE_gm Predefined. */ ++/* AC_HYSMODE_gp Predefined. */ ++/* AC_HYSMODE0_bm Predefined. */ ++/* AC_HYSMODE0_bp Predefined. */ ++/* AC_HYSMODE1_bm Predefined. */ ++/* AC_HYSMODE1_bp Predefined. */ ++ ++/* AC_ENABLE_bm Predefined. */ ++/* AC_ENABLE_bp Predefined. */ ++ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS_gm Predefined. */ ++/* AC_MUXPOS_gp Predefined. */ ++/* AC_MUXPOS0_bm Predefined. */ ++/* AC_MUXPOS0_bp Predefined. */ ++/* AC_MUXPOS1_bm Predefined. */ ++/* AC_MUXPOS1_bp Predefined. */ ++/* AC_MUXPOS2_bm Predefined. */ ++/* AC_MUXPOS2_bp Predefined. */ ++ ++/* AC_MUXNEG_gm Predefined. */ ++/* AC_MUXNEG_gp Predefined. */ ++/* AC_MUXNEG0_bm Predefined. */ ++/* AC_MUXNEG0_bp Predefined. */ ++/* AC_MUXNEG1_bm Predefined. */ ++/* AC_MUXNEG1_bp Predefined. */ ++/* AC_MUXNEG2_bm Predefined. */ ++/* AC_MUXNEG2_bp Predefined. */ ++ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ ++ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ ++ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ ++ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ ++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ ++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ ++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ ++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ ++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ ++ ++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ ++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ ++ ++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ ++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ ++ ++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ ++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ ++ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ ++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ ++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ ++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ ++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ ++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ ++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ ++ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ ++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ ++ ++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ ++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ ++ ++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ ++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ ++ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++ ++/* DAC - Digital/Analog Converter */ ++/* DAC.CTRLA bit masks and bit positions */ ++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ ++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ ++ ++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ ++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ ++ ++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ ++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ ++ ++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ ++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ ++ ++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define DAC_ENABLE_bp 0 /* Enable bit position. */ ++ ++ ++/* DAC.CTRLB bit masks and bit positions */ ++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ ++#define DAC_CHSEL_gp 5 /* Channel Select group position. */ ++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ ++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ ++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ ++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ ++ ++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ ++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ ++ ++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ ++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ ++ ++ ++/* DAC.CTRLC bit masks and bit positions */ ++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ ++#define DAC_REFSEL_gp 3 /* Reference Select group position. */ ++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ ++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ ++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ ++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ ++ ++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ ++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ ++ ++ ++/* DAC.EVCTRL bit masks and bit positions */ ++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ ++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ ++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ ++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ ++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ ++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ ++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ ++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ ++ ++ ++/* DAC.TIMCTRL bit masks and bit positions */ ++#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ ++#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ ++#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ ++#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ ++#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ ++#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ ++#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ ++#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ ++ ++#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ ++#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ ++#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ ++#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ ++#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ ++#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ ++#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ ++#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ ++#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ ++#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ ++ ++ ++/* DAC.STATUS bit masks and bit positions */ ++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ ++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ ++ ++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ ++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ ++ ++ ++/* RTC - Real-Time Clounter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* EBI - External Bus Interface */ ++/* EBI_CS.CTRLA bit masks and bit positions */ ++#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ ++#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ ++#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ ++#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ ++#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ ++#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ ++#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ ++#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ ++#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ ++#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ ++#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ ++#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ ++ ++#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ ++#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ ++#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ ++#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ ++#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ ++#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ ++ ++ ++/* EBI_CS.CTRLB bit masks and bit positions */ ++#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ ++#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ ++#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ ++#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ ++#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ ++#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ ++#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ ++#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ ++ ++#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ ++#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ ++ ++#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ ++#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ ++ ++#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ ++#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ ++#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ ++#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ ++#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ ++#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ ++ ++ ++/* EBI.CTRL bit masks and bit positions */ ++#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ ++#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ ++#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ ++#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ ++#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ ++#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ ++ ++#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ ++#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ ++#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ ++#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ ++#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ ++#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ ++ ++#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ ++#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ ++#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ ++#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ ++#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ ++#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ ++ ++#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ ++#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ ++#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ ++#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ ++#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ ++#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLA bit masks and bit positions */ ++#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ ++#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ ++ ++#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ ++#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ ++ ++#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ ++#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ ++#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ ++#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ ++#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ ++#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLB bit masks and bit positions */ ++#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ ++#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ ++#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ ++#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ ++#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ ++#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ ++ ++#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ ++#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ ++#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ ++#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ ++#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ ++#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ ++#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ ++#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ ++ ++#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ ++#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ ++#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ ++#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ ++#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ ++#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ ++#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ ++#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ ++ ++ ++/* EBI.SDRAMCTRLC bit masks and bit positions */ ++#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ ++#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ ++#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ ++#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ ++#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ ++#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ ++ ++#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ ++#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ ++#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ ++#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ ++#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ ++#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ ++#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ ++#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ ++ ++#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ ++#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ ++#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ ++#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ ++#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ ++#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ ++#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ ++#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ ++ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ ++#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++ ++/* PORT - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ ++#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ ++ ++#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD_gm Predefined. */ ++/* TC0_CMD_gp Predefined. */ ++/* TC0_CMD0_bm Predefined. */ ++/* TC0_CMD0_bp Predefined. */ ++/* TC0_CMD1_bm Predefined. */ ++/* TC0_CMD1_bp Predefined. */ ++ ++/* TC0_LUPD_bm Predefined. */ ++/* TC0_LUPD_bp Predefined. */ ++ ++/* TC0_DIR_bm Predefined. */ ++/* TC0_DIR_bp Predefined. */ ++ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV_bm Predefined. */ ++/* TC0_CCDBV_bp Predefined. */ ++ ++/* TC0_CCCBV_bm Predefined. */ ++/* TC0_CCCBV_bp Predefined. */ ++ ++/* TC0_CCBBV_bm Predefined. */ ++/* TC0_CCBBV_bp Predefined. */ ++ ++/* TC0_CCABV_bm Predefined. */ ++/* TC0_CCABV_bp Predefined. */ ++ ++/* TC0_PERBV_bm Predefined. */ ++/* TC0_PERBV_bp Predefined. */ ++ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ ++#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ ++ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD_gm Predefined. */ ++/* TC1_CMD_gp Predefined. */ ++/* TC1_CMD0_bm Predefined. */ ++/* TC1_CMD0_bp Predefined. */ ++/* TC1_CMD1_bm Predefined. */ ++/* TC1_CMD1_bp Predefined. */ ++ ++/* TC1_LUPD_bm Predefined. */ ++/* TC1_LUPD_bp Predefined. */ ++ ++/* TC1_DIR_bm Predefined. */ ++/* TC1_DIR_bp Predefined. */ ++ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV_bm Predefined. */ ++/* TC1_CCBBV_bp Predefined. */ ++ ++/* TC1_CCABV_bm Predefined. */ ++/* TC1_CCABV_bp Predefined. */ ++ ++/* TC1_PERBV_bm Predefined. */ ++/* TC1_PERBV_bp Predefined. */ ++ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++ ++/* HIRES.CTRL bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL_gm Predefined. */ ++/* USART_BSEL_gp Predefined. */ ++/* USART_BSEL0_bm Predefined. */ ++/* USART_BSEL0_bp Predefined. */ ++/* USART_BSEL1_bm Predefined. */ ++/* USART_BSEL1_bp Predefined. */ ++/* USART_BSEL2_bm Predefined. */ ++/* USART_BSEL2_bp Predefined. */ ++/* USART_BSEL3_bm Predefined. */ ++/* USART_BSEL3_bp Predefined. */ ++ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++ ++/* AES - AES Module */ ++/* AES.CTRL bit masks and bit positions */ ++#define AES_START_bm 0x80 /* Start/Run bit mask. */ ++#define AES_START_bp 7 /* Start/Run bit position. */ ++ ++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ ++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ ++ ++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ ++#define AES_RESET_bp 5 /* AES Software Reset bit position. */ ++ ++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ ++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ ++ ++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ ++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ ++ ++ ++/* AES.STATUS bit masks and bit positions */ ++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ ++#define AES_ERROR_bp 7 /* AES Error bit position. */ ++ ++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ ++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ ++ ++ ++/* AES.INTCTRL bit masks and bit positions */ ++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define AES_INTLVL_gp 0 /* Interrupt level group position. */ ++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_XOSCF_vect_num 1 ++#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* DMA interrupt vectors */ ++#define DMA_CH0_vect_num 6 ++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ ++#define DMA_CH1_vect_num 7 ++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ ++#define DMA_CH2_vect_num 8 ++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ ++#define DMA_CH3_vect_num 9 ++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* USARTC1 interrupt vectors */ ++#define USARTC1_RXC_vect_num 28 ++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ ++#define USARTC1_DRE_vect_num 29 ++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ ++#define USARTC1_TXC_vect_num 30 ++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ ++ ++/* AES interrupt vectors */ ++#define AES_INT_vect_num 31 ++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* ACB interrupt vectors */ ++#define ACB_AC0_vect_num 36 ++#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ ++#define ACB_AC1_vect_num 37 ++#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ ++#define ACB_ACW_vect_num 38 ++#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ ++ ++/* ADCB interrupt vectors */ ++#define ADCB_CH0_vect_num 39 ++#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ ++#define ADCB_CH1_vect_num 40 ++#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ ++#define ADCB_CH2_vect_num 41 ++#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ ++#define ADCB_CH3_vect_num 42 ++#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* TCE1 interrupt vectors */ ++#define TCE1_OVF_vect_num 53 ++#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ ++#define TCE1_ERR_vect_num 54 ++#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ ++#define TCE1_CCA_vect_num 55 ++#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ ++#define TCE1_CCB_vect_num 56 ++#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ ++ ++/* SPIE interrupt vectors */ ++#define SPIE_INT_vect_num 57 ++#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* USARTE1 interrupt vectors */ ++#define USARTE1_RXC_vect_num 61 ++#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ ++#define USARTE1_DRE_vect_num 62 ++#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ ++#define USARTE1_TXC_vect_num 63 ++#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++#define ADCA_CH1_vect_num 72 ++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ ++#define ADCA_CH2_vect_num 73 ++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ ++#define ADCA_CH3_vect_num 74 ++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD1 interrupt vectors */ ++#define TCD1_OVF_vect_num 83 ++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ ++#define TCD1_ERR_vect_num 84 ++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ ++#define TCD1_CCA_vect_num 85 ++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ ++#define TCD1_CCB_vect_num 86 ++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* USARTD1 interrupt vectors */ ++#define USARTD1_RXC_vect_num 91 ++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ ++#define USARTD1_DRE_vect_num 92 ++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ ++#define USARTD1_TXC_vect_num 93 ++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ ++ ++/* PORTF interrupt vectors */ ++#define PORTF_INT0_vect_num 104 ++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ ++#define PORTF_INT1_vect_num 105 ++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_OVF_vect_num 108 ++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ ++#define TCF0_ERR_vect_num 109 ++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ ++#define TCF0_CCA_vect_num 110 ++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ ++#define TCF0_CCB_vect_num 111 ++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ ++#define TCF0_CCC_vect_num 112 ++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ ++#define TCF0_CCD_vect_num 113 ++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ ++ ++/* USARTF0 interrupt vectors */ ++#define USARTF0_RXC_vect_num 119 ++#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ ++#define USARTF0_DRE_vect_num 120 ++#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ ++#define USARTF0_TXC_vect_num 121 ++#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ ++ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (122 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (204800) ++#define PROGMEM_PAGE_SIZE (512) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (196608) ++#define APP_SECTION_PAGE_SIZE (512) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x2E000) ++#define APPTABLE_SECTION_SIZE (8192) ++#define APPTABLE_SECTION_PAGE_SIZE (512) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x30000) ++#define BOOT_SECTION_SIZE (8192) ++#define BOOT_SECTION_PAGE_SIZE (512) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (16777216) ++#define DATAMEM_PAGE_SIZE (0) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (2048) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (16384) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (2048) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define FUSE_START (0x0000) ++#define FUSE_SIZE (6) ++#define FUSE_PAGE_SIZE (0) ++#define FUSE_END (FUSE_START + FUSE_SIZE - 1) ++ ++#define LOCKBIT_START (0x0000) ++#define LOCKBIT_SIZE (1) ++#define LOCKBIT_PAGE_SIZE (0) ++#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (512) ++#define USER_SIGNATURES_PAGE_SIZE (0) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (0) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE PROGMEM_PAGE_SIZE ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define XRAMSTART EXTERNAL_SRAM_START ++#define XRAMSIZE EXTERNAL_SRAM_SIZE ++#define XRAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 */ ++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ ++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ ++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ ++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ ++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ ++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ ++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ ++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ ++#define FUSE0_DEFAULT (0xFF) ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x97 ++#define SIGNATURE_2 0x44 ++ ++ ++#endif /* _AVR_ATxmega192A3_H_ */ ++ +diff --git a/include/avr/iox192a3u.h b/include/avr/iox192a3u.h +new file mode 100644 +index 0000000..4c429aa +--- /dev/null ++++ b/include/avr/iox192a3u.h +@@ -0,0 +1,7628 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox192a3u.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA192A3U_H_INCLUDED ++#define _AVR_ATXMEGA192A3U_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t USBCTRL; /* USB Control Register */ ++} CLK_t; ++ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t PRPB; /* Power Reduction Port B */ ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++/* USB Prescaler Division Factor */ ++typedef enum CLK_USBPSDIV_enum ++{ ++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ ++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ ++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ ++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ ++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ ++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ ++} CLK_USBPSDIV_t; ++ ++/* USB Clock Source */ ++typedef enum CLK_USBSRC_enum ++{ ++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ ++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ ++} CLK_USBSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 2 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC2MCREF_enum ++{ ++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC2MCREF_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++ register8_t EBIOUT; /* EBI Output register */ ++ register8_t EVOUTSEL; /* Event Output Select */ ++} PORTCFG_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP02MAP_enum ++{ ++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP02MAP_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP13MAP_enum ++{ ++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP13MAP_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Clock and Event Output Port */ ++typedef enum PORTCFG_CLKEVPIN_enum ++{ ++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ ++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ ++} PORTCFG_CLKEVPIN_t; ++ ++/* EBI Address Output Port */ ++typedef enum PORTCFG_EBIADROUT_enum ++{ ++ PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ ++ PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ ++ PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ ++ PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ ++} PORTCFG_EBIADROUT_t; ++ ++/* EBI Chip Select Output Port */ ++typedef enum PORTCFG_EBICSOUT_enum ++{ ++ PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ ++} PORTCFG_EBICSOUT_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ ++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ ++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ ++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ ++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AES - AES Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* AES Module */ ++typedef struct AES_struct ++{ ++ register8_t CTRL; /* AES Control Register */ ++ register8_t STATUS; /* AES Status Register */ ++ register8_t STATE; /* AES State Register */ ++ register8_t KEY; /* AES Key Register */ ++ register8_t INTCTRL; /* AES Interrupt Control Register */ ++} AES_t; ++ ++/* Interrupt level */ ++typedef enum AES_INTLVL_enum ++{ ++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} AES_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ ++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ ++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ ++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Channel */ ++typedef struct DMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Address Control */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ ++ register8_t REPCNT; /* Channel Repeat Count */ ++ register8_t reserved_0x07; ++ register8_t SRCADDR0; /* Channel Source Address 0 */ ++ register8_t SRCADDR1; /* Channel Source Address 1 */ ++ register8_t SRCADDR2; /* Channel Source Address 2 */ ++ register8_t reserved_0x0B; ++ register8_t DESTADDR0; /* Channel Destination Address 0 */ ++ register8_t DESTADDR1; /* Channel Destination Address 1 */ ++ register8_t DESTADDR2; /* Channel Destination Address 2 */ ++ register8_t reserved_0x0F; ++} DMA_CH_t; ++ ++ ++/* DMA Controller */ ++typedef struct DMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ DMA_CH_t CH0; /* DMA Channel 0 */ ++ DMA_CH_t CH1; /* DMA Channel 1 */ ++ DMA_CH_t CH2; /* DMA Channel 2 */ ++ DMA_CH_t CH3; /* DMA Channel 3 */ ++} DMA_t; ++ ++/* Burst mode */ ++typedef enum DMA_CH_BURSTLEN_enum ++{ ++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ ++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ ++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ ++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ ++} DMA_CH_BURSTLEN_t; ++ ++/* Source address reload mode */ ++typedef enum DMA_CH_SRCRELOAD_enum ++{ ++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ ++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ ++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ ++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ ++} DMA_CH_SRCRELOAD_t; ++ ++/* Source addressing mode */ ++typedef enum DMA_CH_SRCDIR_enum ++{ ++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ ++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ ++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ ++} DMA_CH_SRCDIR_t; ++ ++/* Destination adress reload mode */ ++typedef enum DMA_CH_DESTRELOAD_enum ++{ ++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ ++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ ++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ ++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ ++} DMA_CH_DESTRELOAD_t; ++ ++/* Destination adressing mode */ ++typedef enum DMA_CH_DESTDIR_enum ++{ ++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ ++} DMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum DMA_CH_TRIGSRC_enum ++{ ++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ ++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ ++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ ++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ ++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ ++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ ++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ ++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ ++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ ++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ ++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ ++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ ++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ ++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ ++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ ++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ ++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ ++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ ++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ ++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ ++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ ++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ ++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ ++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ ++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ ++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ ++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ ++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ ++} DMA_CH_TRIGSRC_t; ++ ++/* Double buffering mode */ ++typedef enum DMA_DBUFMODE_enum ++{ ++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ ++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ ++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ ++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ ++} DMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum DMA_PRIMODE_enum ++{ ++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ ++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ ++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ ++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ ++} DMA_PRIMODE_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_ERRINTLVL_enum ++{ ++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ ++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ ++} DMA_CH_ERRINTLVL_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_TRNINTLVL_enum ++{ ++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ ++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ ++} DMA_CH_TRNINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ ++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ ++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ ++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t CH4CTRL; /* Channel 4 Control Register */ ++ register8_t CH5CTRL; /* Channel 5 Control Register */ ++ register8_t CH6CTRL; /* Channel 6 Control Register */ ++ register8_t CH7CTRL; /* Channel 7 Control Register */ ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ ++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ ++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ ++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ ++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ ++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ ++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ ++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ ++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ ++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ ++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ ++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ ++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ ++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ ++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ ++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ ++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ ++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t reserved_0x07; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ _WORDREGISTER(CH1RES); /* Channel 1 Result */ ++ _WORDREGISTER(CH2RES); /* Channel 2 Result */ ++ _WORDREGISTER(CH3RES); /* Channel 3 Result */ ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++ ADC_CH_t CH1; /* ADC Channel 1 */ ++ ADC_CH_t CH2; /* ADC Channel 2 */ ++ ADC_CH_t CH3; /* ADC Channel 3 */ ++} ADC_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ ++ ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ ++ ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ ++ ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Current Limitation Mode */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ ++} ADC_CURRLIMIT_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Channel sweep selection */ ++typedef enum ADC_SWEEP_enum ++{ ++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ ++} ADC_SWEEP_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* DMA request selection */ ++typedef enum ADC_DMASEL_enum ++{ ++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ ++} ADC_DMASEL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DAC - Digital/Analog Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Digital-to-Analog Converter */ ++typedef struct DAC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t EVCTRL; /* Event Input Control */ ++ register8_t reserved_0x04; ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0GAINCAL; /* Gain Calibration */ ++ register8_t CH0OFFSETCAL; /* Offset Calibration */ ++ register8_t CH1GAINCAL; /* Gain Calibration */ ++ register8_t CH1OFFSETCAL; /* Offset Calibration */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ ++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ ++} DAC_t; ++ ++/* Output channel selection */ ++typedef enum DAC_CHSEL_enum ++{ ++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ ++ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ ++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ ++} DAC_CHSEL_t; ++ ++/* Reference voltage selection */ ++typedef enum DAC_REFSEL_enum ++{ ++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ ++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ ++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ ++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ ++} DAC_REFSEL_t; ++ ++/* Event channel selection */ ++typedef enum DAC_EVSEL_enum ++{ ++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ ++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ ++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ ++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ ++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ ++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ ++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ ++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ ++} DAC_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* SDA Hold Time */ ++typedef enum TWI_SDAHOLD_enum ++{ ++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ ++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ ++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ ++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ ++} TWI_SDAHOLD_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USB - USB ++-------------------------------------------------------------------------- ++*/ ++ ++/* USB Endpoint */ ++typedef struct USB_EP_struct ++{ ++ register8_t STATUS; /* Endpoint Status */ ++ register8_t CTRL; /* Endpoint Control */ ++ _WORDREGISTER(CNT); /* USB Endpoint Counter */ ++ _WORDREGISTER(DATAPTR); /* Data Pointer */ ++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ ++} USB_EP_t; ++ ++ ++/* Universal Serial Bus */ ++typedef struct USB_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t FIFOWP; /* FIFO Write Pointer Register */ ++ register8_t FIFORP; /* FIFO Read Pointer Register */ ++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ ++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ ++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ ++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t reserved_0x20; ++ register8_t reserved_0x21; ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t CAL0; /* Calibration Byte 0 */ ++ register8_t CAL1; /* Calibration Byte 1 */ ++} USB_t; ++ ++ ++/* USB Endpoint Table */ ++typedef struct USB_EP_TABLE_struct ++{ ++ USB_EP_t EP0OUT; /* Endpoint 0 */ ++ USB_EP_t EP0IN; /* Endpoint 0 */ ++ USB_EP_t EP1OUT; /* Endpoint 1 */ ++ USB_EP_t EP1IN; /* Endpoint 1 */ ++ USB_EP_t EP2OUT; /* Endpoint 2 */ ++ USB_EP_t EP2IN; /* Endpoint 2 */ ++ USB_EP_t EP3OUT; /* Endpoint 3 */ ++ USB_EP_t EP3IN; /* Endpoint 3 */ ++ USB_EP_t EP4OUT; /* Endpoint 4 */ ++ USB_EP_t EP4IN; /* Endpoint 4 */ ++ USB_EP_t EP5OUT; /* Endpoint 5 */ ++ USB_EP_t EP5IN; /* Endpoint 5 */ ++ USB_EP_t EP6OUT; /* Endpoint 6 */ ++ USB_EP_t EP6IN; /* Endpoint 6 */ ++ USB_EP_t EP7OUT; /* Endpoint 7 */ ++ USB_EP_t EP7IN; /* Endpoint 7 */ ++ USB_EP_t EP8OUT; /* Endpoint 8 */ ++ USB_EP_t EP8IN; /* Endpoint 8 */ ++ USB_EP_t EP9OUT; /* Endpoint 9 */ ++ USB_EP_t EP9IN; /* Endpoint 9 */ ++ USB_EP_t EP10OUT; /* Endpoint 10 */ ++ USB_EP_t EP10IN; /* Endpoint 10 */ ++ USB_EP_t EP11OUT; /* Endpoint 11 */ ++ USB_EP_t EP11IN; /* Endpoint 11 */ ++ USB_EP_t EP12OUT; /* Endpoint 12 */ ++ USB_EP_t EP12IN; /* Endpoint 12 */ ++ USB_EP_t EP13OUT; /* Endpoint 13 */ ++ USB_EP_t EP13IN; /* Endpoint 13 */ ++ USB_EP_t EP14OUT; /* Endpoint 14 */ ++ USB_EP_t EP14IN; /* Endpoint 14 */ ++ USB_EP_t EP15OUT; /* Endpoint 15 */ ++ USB_EP_t EP15IN; /* Endpoint 15 */ ++ register8_t reserved_0x100; ++ register8_t reserved_0x101; ++ register8_t reserved_0x102; ++ register8_t reserved_0x103; ++ register8_t reserved_0x104; ++ register8_t reserved_0x105; ++ register8_t reserved_0x106; ++ register8_t reserved_0x107; ++ register8_t reserved_0x108; ++ register8_t reserved_0x109; ++ register8_t reserved_0x10A; ++ register8_t reserved_0x10B; ++ register8_t reserved_0x10C; ++ register8_t reserved_0x10D; ++ register8_t reserved_0x10E; ++ register8_t reserved_0x10F; ++ register8_t FRAMENUML; /* Frame Number Low Byte */ ++ register8_t FRAMENUMH; /* Frame Number High Byte */ ++} USB_EP_TABLE_t; ++ ++/* Interrupt level */ ++typedef enum USB_INTLVL_enum ++{ ++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} USB_INTLVL_t; ++ ++/* USB Endpoint Type */ ++typedef enum USB_EP_TYPE_enum ++{ ++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ ++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ ++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ ++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ ++} USB_EP_TYPE_t; ++ ++/* USB Endpoint Buffersize */ ++typedef enum USB_EP_BUFSIZE_enum ++{ ++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ ++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ ++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ ++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ ++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ ++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ ++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ ++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ ++} USB_EP_BUFSIZE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - I/O Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* I/O Port Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Byte Mode */ ++typedef enum TC_BYTEM_enum ++{ ++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ ++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ ++} TC_BYTEM_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC2 - 16-bit Timer/Counter type 2 ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter type 2 */ ++typedef struct TC2_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t reserved_0x03; ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t reserved_0x08; ++ register8_t CTRLF; /* Control Register F */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t LCNT; /* Low Byte Count */ ++ register8_t HCNT; /* High Byte Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t LPER; /* Low Byte Period */ ++ register8_t HPER; /* High Byte Period */ ++ register8_t LCMPA; /* Low Byte Compare A */ ++ register8_t HCMPA; /* High Byte Compare A */ ++ register8_t LCMPB; /* Low Byte Compare B */ ++ register8_t HCMPB; /* High Byte Compare B */ ++ register8_t LCMPC; /* Low Byte Compare C */ ++ register8_t HCMPC; /* High Byte Compare C */ ++ register8_t LCMPD; /* Low Byte Compare D */ ++ register8_t HCMPD; /* High Byte Compare D */ ++} TC2_t; ++ ++/* Clock Selection */ ++typedef enum TC2_CLKSEL_enum ++{ ++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC2_CLKSEL_t; ++ ++/* Byte Mode */ ++typedef enum TC2_BYTEM_enum ++{ ++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ ++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ ++} TC2_BYTEM_t; ++ ++/* High Byte Underflow Interrupt Level */ ++typedef enum TC2_HUNFINTLVL_enum ++{ ++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_HUNFINTLVL_t; ++ ++/* Low Byte Underflow Interrupt Level */ ++typedef enum TC2_LUNFINTLVL_enum ++{ ++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LUNFINTLVL_t; ++ ++/* Low Byte Compare D Interrupt Level */ ++typedef enum TC2_LCMPDINTLVL_enum ++{ ++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC2_LCMPDINTLVL_t; ++ ++/* Low Byte Compare C Interrupt Level */ ++typedef enum TC2_LCMPCINTLVL_enum ++{ ++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC2_LCMPCINTLVL_t; ++ ++/* Low Byte Compare B Interrupt Level */ ++typedef enum TC2_LCMPBINTLVL_enum ++{ ++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_LCMPBINTLVL_t; ++ ++/* Low Byte Compare A Interrupt Level */ ++typedef enum TC2_LCMPAINTLVL_enum ++{ ++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LCMPAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMD_enum ++{ ++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC2_CMD_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMDEN_enum ++{ ++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ ++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ ++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ ++} TC2_CMDEN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AWEX - Timer/Counter Advanced Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - Timer/Counter High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t FUSEBYTE0; /* JTAG User ID */ ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* Timer Oscillator pin location */ ++typedef enum TOSCSEL_enum ++{ ++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ ++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ ++} TOSCSEL_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* BOD operation */ ++typedef enum BODACT_enum ++{ ++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BODACT_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WDP_enum ++{ ++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ ++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ ++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ ++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ ++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ ++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ ++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ ++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ ++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ ++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ ++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ ++} WDP_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LOCKBIT - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ ++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t USBCAL0; /* USB Calibration Byte 0 */ ++ register8_t USBCAL1; /* USB Calibration Byte 1 */ ++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ ++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ ++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ ++ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ ++ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ ++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ ++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ ++ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ ++ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++ register8_t reserved_0x40; ++ register8_t reserved_0x41; ++ register8_t reserved_0x42; ++ register8_t reserved_0x43; ++ register8_t reserved_0x44; ++ register8_t reserved_0x45; ++ register8_t reserved_0x46; ++ register8_t reserved_0x47; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define AES (*(AES_t *) 0x00C0) /* AES Module */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ ++#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ ++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ ++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ ++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ ++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ ++#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ ++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ ++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ ++#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ ++#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ ++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ ++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ ++#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ ++#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ ++#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++#define GPIO_GPIOR4 _SFR_MEM8(0x0004) ++#define GPIO_GPIOR5 _SFR_MEM8(0x0005) ++#define GPIO_GPIOR6 _SFR_MEM8(0x0006) ++#define GPIO_GPIOR7 _SFR_MEM8(0x0007) ++#define GPIO_GPIOR8 _SFR_MEM8(0x0008) ++#define GPIO_GPIOR9 _SFR_MEM8(0x0009) ++#define GPIO_GPIORA _SFR_MEM8(0x000A) ++#define GPIO_GPIORB _SFR_MEM8(0x000B) ++#define GPIO_GPIORC _SFR_MEM8(0x000C) ++#define GPIO_GPIORD _SFR_MEM8(0x000D) ++#define GPIO_GPIORE _SFR_MEM8(0x000E) ++#define GPIO_GPIORF _SFR_MEM8(0x000F) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++#define GPIO_GPIO4 _SFR_MEM8(0x0004) ++#define GPIO_GPIO5 _SFR_MEM8(0x0005) ++#define GPIO_GPIO6 _SFR_MEM8(0x0006) ++#define GPIO_GPIO7 _SFR_MEM8(0x0007) ++#define GPIO_GPIO8 _SFR_MEM8(0x0008) ++#define GPIO_GPIO9 _SFR_MEM8(0x0009) ++#define GPIO_GPIOA _SFR_MEM8(0x000A) ++#define GPIO_GPIOB _SFR_MEM8(0x000B) ++#define GPIO_GPIOC _SFR_MEM8(0x000C) ++#define GPIO_GPIOD _SFR_MEM8(0x000D) ++#define GPIO_GPIOE _SFR_MEM8(0x000E) ++#define GPIO_GPIOF _SFR_MEM8(0x000F) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) ++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) ++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) ++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) ++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) ++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) ++#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) ++#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) ++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) ++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) ++#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) ++#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++#define CLK_USBCTRL _SFR_MEM8(0x0044) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLL - DFLL */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPB _SFR_MEM8(0x0072) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) ++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) ++ ++/* AES - AES Module */ ++#define AES_CTRL _SFR_MEM8(0x00C0) ++#define AES_STATUS _SFR_MEM8(0x00C1) ++#define AES_STATE _SFR_MEM8(0x00C2) ++#define AES_KEY _SFR_MEM8(0x00C3) ++#define AES_INTCTRL _SFR_MEM8(0x00C4) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* DMA - DMA Controller */ ++#define DMA_CTRL _SFR_MEM8(0x0100) ++#define DMA_INTFLAGS _SFR_MEM8(0x0103) ++#define DMA_STATUS _SFR_MEM8(0x0104) ++#define DMA_TEMP _SFR_MEM16(0x0106) ++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) ++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) ++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) ++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) ++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) ++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) ++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) ++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) ++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) ++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) ++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) ++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) ++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) ++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) ++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) ++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) ++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) ++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) ++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) ++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) ++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) ++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) ++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) ++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) ++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) ++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) ++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) ++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) ++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) ++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) ++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) ++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) ++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) ++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) ++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) ++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) ++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) ++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) ++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) ++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) ++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) ++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH4MUX _SFR_MEM8(0x0184) ++#define EVSYS_CH5MUX _SFR_MEM8(0x0185) ++#define EVSYS_CH6MUX _SFR_MEM8(0x0186) ++#define EVSYS_CH7MUX _SFR_MEM8(0x0187) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) ++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) ++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) ++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CH1RES _SFR_MEM16(0x0212) ++#define ADCA_CH2RES _SFR_MEM16(0x0214) ++#define ADCA_CH3RES _SFR_MEM16(0x0216) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) ++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) ++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) ++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) ++#define ADCA_CH1_RES _SFR_MEM16(0x022C) ++#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) ++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) ++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) ++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) ++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) ++#define ADCA_CH2_RES _SFR_MEM16(0x0234) ++#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) ++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) ++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) ++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) ++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) ++#define ADCA_CH3_RES _SFR_MEM16(0x023C) ++#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCB_CTRLA _SFR_MEM8(0x0240) ++#define ADCB_CTRLB _SFR_MEM8(0x0241) ++#define ADCB_REFCTRL _SFR_MEM8(0x0242) ++#define ADCB_EVCTRL _SFR_MEM8(0x0243) ++#define ADCB_PRESCALER _SFR_MEM8(0x0244) ++#define ADCB_INTFLAGS _SFR_MEM8(0x0246) ++#define ADCB_TEMP _SFR_MEM8(0x0247) ++#define ADCB_CAL _SFR_MEM16(0x024C) ++#define ADCB_CH0RES _SFR_MEM16(0x0250) ++#define ADCB_CH1RES _SFR_MEM16(0x0252) ++#define ADCB_CH2RES _SFR_MEM16(0x0254) ++#define ADCB_CH3RES _SFR_MEM16(0x0256) ++#define ADCB_CMP _SFR_MEM16(0x0258) ++#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) ++#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) ++#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) ++#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) ++#define ADCB_CH0_RES _SFR_MEM16(0x0264) ++#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) ++#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) ++#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) ++#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) ++#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) ++#define ADCB_CH1_RES _SFR_MEM16(0x026C) ++#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) ++#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) ++#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) ++#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) ++#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) ++#define ADCB_CH2_RES _SFR_MEM16(0x0274) ++#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) ++#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) ++#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) ++#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) ++#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) ++#define ADCB_CH3_RES _SFR_MEM16(0x027C) ++#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) ++ ++/* DAC - Digital-to-Analog Converter */ ++#define DACB_CTRLA _SFR_MEM8(0x0320) ++#define DACB_CTRLB _SFR_MEM8(0x0321) ++#define DACB_CTRLC _SFR_MEM8(0x0322) ++#define DACB_EVCTRL _SFR_MEM8(0x0323) ++#define DACB_STATUS _SFR_MEM8(0x0325) ++#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) ++#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) ++#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) ++#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) ++#define DACB_CH0DATA _SFR_MEM16(0x0338) ++#define DACB_CH1DATA _SFR_MEM16(0x033A) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* AC - Analog Comparator */ ++#define ACB_AC0CTRL _SFR_MEM8(0x0390) ++#define ACB_AC1CTRL _SFR_MEM8(0x0391) ++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) ++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) ++#define ACB_CTRLA _SFR_MEM8(0x0394) ++#define ACB_CTRLB _SFR_MEM8(0x0395) ++#define ACB_WINCTRL _SFR_MEM8(0x0396) ++#define ACB_STATUS _SFR_MEM8(0x0397) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* USB - Universal Serial Bus */ ++#define USB_CTRLA _SFR_MEM8(0x04C0) ++#define USB_CTRLB _SFR_MEM8(0x04C1) ++#define USB_STATUS _SFR_MEM8(0x04C2) ++#define USB_ADDR _SFR_MEM8(0x04C3) ++#define USB_FIFOWP _SFR_MEM8(0x04C4) ++#define USB_FIFORP _SFR_MEM8(0x04C5) ++#define USB_EPPTR _SFR_MEM16(0x04C6) ++#define USB_INTCTRLA _SFR_MEM8(0x04C8) ++#define USB_INTCTRLB _SFR_MEM8(0x04C9) ++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) ++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) ++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) ++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) ++#define USB_CAL0 _SFR_MEM8(0x04FA) ++#define USB_CAL1 _SFR_MEM8(0x04FB) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_REMAP _SFR_MEM8(0x060E) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_REMAP _SFR_MEM8(0x062E) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_REMAP _SFR_MEM8(0x068E) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORT - I/O Ports */ ++#define PORTF_DIR _SFR_MEM8(0x06A0) ++#define PORTF_DIRSET _SFR_MEM8(0x06A1) ++#define PORTF_DIRCLR _SFR_MEM8(0x06A2) ++#define PORTF_DIRTGL _SFR_MEM8(0x06A3) ++#define PORTF_OUT _SFR_MEM8(0x06A4) ++#define PORTF_OUTSET _SFR_MEM8(0x06A5) ++#define PORTF_OUTCLR _SFR_MEM8(0x06A6) ++#define PORTF_OUTTGL _SFR_MEM8(0x06A7) ++#define PORTF_IN _SFR_MEM8(0x06A8) ++#define PORTF_INTCTRL _SFR_MEM8(0x06A9) ++#define PORTF_INT0MASK _SFR_MEM8(0x06AA) ++#define PORTF_INT1MASK _SFR_MEM8(0x06AB) ++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) ++#define PORTF_REMAP _SFR_MEM8(0x06AE) ++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) ++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) ++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) ++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) ++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) ++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) ++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) ++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCC2_CTRLA _SFR_MEM8(0x0800) ++#define TCC2_CTRLB _SFR_MEM8(0x0801) ++#define TCC2_CTRLC _SFR_MEM8(0x0802) ++#define TCC2_CTRLE _SFR_MEM8(0x0804) ++#define TCC2_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC2_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC2_CTRLF _SFR_MEM8(0x0809) ++#define TCC2_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC2_LCNT _SFR_MEM8(0x0820) ++#define TCC2_HCNT _SFR_MEM8(0x0821) ++#define TCC2_LPER _SFR_MEM8(0x0826) ++#define TCC2_HPER _SFR_MEM8(0x0827) ++#define TCC2_LCMPA _SFR_MEM8(0x0828) ++#define TCC2_HCMPA _SFR_MEM8(0x0829) ++#define TCC2_LCMPB _SFR_MEM8(0x082A) ++#define TCC2_HCMPB _SFR_MEM8(0x082B) ++#define TCC2_LCMPC _SFR_MEM8(0x082C) ++#define TCC2_HCMPC _SFR_MEM8(0x082D) ++#define TCC2_LCMPD _SFR_MEM8(0x082E) ++#define TCC2_HCMPD _SFR_MEM8(0x082F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_STATUSSET _SFR_MEM8(0x0885) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1_DATA _SFR_MEM8(0x08B0) ++#define USARTC1_STATUS _SFR_MEM8(0x08B1) ++#define USARTC1_CTRLA _SFR_MEM8(0x08B3) ++#define USARTC1_CTRLB _SFR_MEM8(0x08B4) ++#define USARTC1_CTRLC _SFR_MEM8(0x08B5) ++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) ++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCD2_CTRLA _SFR_MEM8(0x0900) ++#define TCD2_CTRLB _SFR_MEM8(0x0901) ++#define TCD2_CTRLC _SFR_MEM8(0x0902) ++#define TCD2_CTRLE _SFR_MEM8(0x0904) ++#define TCD2_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD2_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD2_CTRLF _SFR_MEM8(0x0909) ++#define TCD2_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD2_LCNT _SFR_MEM8(0x0920) ++#define TCD2_HCNT _SFR_MEM8(0x0921) ++#define TCD2_LPER _SFR_MEM8(0x0926) ++#define TCD2_HPER _SFR_MEM8(0x0927) ++#define TCD2_LCMPA _SFR_MEM8(0x0928) ++#define TCD2_HCMPA _SFR_MEM8(0x0929) ++#define TCD2_LCMPB _SFR_MEM8(0x092A) ++#define TCD2_HCMPB _SFR_MEM8(0x092B) ++#define TCD2_LCMPC _SFR_MEM8(0x092C) ++#define TCD2_HCMPC _SFR_MEM8(0x092D) ++#define TCD2_LCMPD _SFR_MEM8(0x092E) ++#define TCD2_HCMPD _SFR_MEM8(0x092F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCD1_CTRLA _SFR_MEM8(0x0940) ++#define TCD1_CTRLB _SFR_MEM8(0x0941) ++#define TCD1_CTRLC _SFR_MEM8(0x0942) ++#define TCD1_CTRLD _SFR_MEM8(0x0943) ++#define TCD1_CTRLE _SFR_MEM8(0x0944) ++#define TCD1_INTCTRLA _SFR_MEM8(0x0946) ++#define TCD1_INTCTRLB _SFR_MEM8(0x0947) ++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) ++#define TCD1_CTRLFSET _SFR_MEM8(0x0949) ++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) ++#define TCD1_CTRLGSET _SFR_MEM8(0x094B) ++#define TCD1_INTFLAGS _SFR_MEM8(0x094C) ++#define TCD1_TEMP _SFR_MEM8(0x094F) ++#define TCD1_CNT _SFR_MEM16(0x0960) ++#define TCD1_PER _SFR_MEM16(0x0966) ++#define TCD1_CCA _SFR_MEM16(0x0968) ++#define TCD1_CCB _SFR_MEM16(0x096A) ++#define TCD1_PERBUF _SFR_MEM16(0x0976) ++#define TCD1_CCABUF _SFR_MEM16(0x0978) ++#define TCD1_CCBBUF _SFR_MEM16(0x097A) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESD_CTRLA _SFR_MEM8(0x0990) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD1_DATA _SFR_MEM8(0x09B0) ++#define USARTD1_STATUS _SFR_MEM8(0x09B1) ++#define USARTD1_CTRLA _SFR_MEM8(0x09B3) ++#define USARTD1_CTRLB _SFR_MEM8(0x09B4) ++#define USARTD1_CTRLC _SFR_MEM8(0x09B5) ++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) ++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCE2_CTRLA _SFR_MEM8(0x0A00) ++#define TCE2_CTRLB _SFR_MEM8(0x0A01) ++#define TCE2_CTRLC _SFR_MEM8(0x0A02) ++#define TCE2_CTRLE _SFR_MEM8(0x0A04) ++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE2_CTRLF _SFR_MEM8(0x0A09) ++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE2_LCNT _SFR_MEM8(0x0A20) ++#define TCE2_HCNT _SFR_MEM8(0x0A21) ++#define TCE2_LPER _SFR_MEM8(0x0A26) ++#define TCE2_HPER _SFR_MEM8(0x0A27) ++#define TCE2_LCMPA _SFR_MEM8(0x0A28) ++#define TCE2_HCMPA _SFR_MEM8(0x0A29) ++#define TCE2_LCMPB _SFR_MEM8(0x0A2A) ++#define TCE2_HCMPB _SFR_MEM8(0x0A2B) ++#define TCE2_LCMPC _SFR_MEM8(0x0A2C) ++#define TCE2_HCMPC _SFR_MEM8(0x0A2D) ++#define TCE2_LCMPD _SFR_MEM8(0x0A2E) ++#define TCE2_HCMPD _SFR_MEM8(0x0A2F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCE1_CTRLA _SFR_MEM8(0x0A40) ++#define TCE1_CTRLB _SFR_MEM8(0x0A41) ++#define TCE1_CTRLC _SFR_MEM8(0x0A42) ++#define TCE1_CTRLD _SFR_MEM8(0x0A43) ++#define TCE1_CTRLE _SFR_MEM8(0x0A44) ++#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) ++#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) ++#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) ++#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) ++#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) ++#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) ++#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) ++#define TCE1_TEMP _SFR_MEM8(0x0A4F) ++#define TCE1_CNT _SFR_MEM16(0x0A60) ++#define TCE1_PER _SFR_MEM16(0x0A66) ++#define TCE1_CCA _SFR_MEM16(0x0A68) ++#define TCE1_CCB _SFR_MEM16(0x0A6A) ++#define TCE1_PERBUF _SFR_MEM16(0x0A76) ++#define TCE1_CCABUF _SFR_MEM16(0x0A78) ++#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXE_CTRL _SFR_MEM8(0x0A80) ++#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) ++#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) ++#define AWEXE_STATUS _SFR_MEM8(0x0A84) ++#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) ++#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) ++#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) ++#define AWEXE_DTLS _SFR_MEM8(0x0A88) ++#define AWEXE_DTHS _SFR_MEM8(0x0A89) ++#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) ++#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) ++#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESE_CTRLA _SFR_MEM8(0x0A90) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE1_DATA _SFR_MEM8(0x0AB0) ++#define USARTE1_STATUS _SFR_MEM8(0x0AB1) ++#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) ++#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) ++#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) ++#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) ++#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIE_CTRL _SFR_MEM8(0x0AC0) ++#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) ++#define SPIE_STATUS _SFR_MEM8(0x0AC2) ++#define SPIE_DATA _SFR_MEM8(0x0AC3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCF0_CTRLA _SFR_MEM8(0x0B00) ++#define TCF0_CTRLB _SFR_MEM8(0x0B01) ++#define TCF0_CTRLC _SFR_MEM8(0x0B02) ++#define TCF0_CTRLD _SFR_MEM8(0x0B03) ++#define TCF0_CTRLE _SFR_MEM8(0x0B04) ++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) ++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) ++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) ++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) ++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF0_TEMP _SFR_MEM8(0x0B0F) ++#define TCF0_CNT _SFR_MEM16(0x0B20) ++#define TCF0_PER _SFR_MEM16(0x0B26) ++#define TCF0_CCA _SFR_MEM16(0x0B28) ++#define TCF0_CCB _SFR_MEM16(0x0B2A) ++#define TCF0_CCC _SFR_MEM16(0x0B2C) ++#define TCF0_CCD _SFR_MEM16(0x0B2E) ++#define TCF0_PERBUF _SFR_MEM16(0x0B36) ++#define TCF0_CCABUF _SFR_MEM16(0x0B38) ++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) ++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) ++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCF2_CTRLA _SFR_MEM8(0x0B00) ++#define TCF2_CTRLB _SFR_MEM8(0x0B01) ++#define TCF2_CTRLC _SFR_MEM8(0x0B02) ++#define TCF2_CTRLE _SFR_MEM8(0x0B04) ++#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF2_CTRLF _SFR_MEM8(0x0B09) ++#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF2_LCNT _SFR_MEM8(0x0B20) ++#define TCF2_HCNT _SFR_MEM8(0x0B21) ++#define TCF2_LPER _SFR_MEM8(0x0B26) ++#define TCF2_HPER _SFR_MEM8(0x0B27) ++#define TCF2_LCMPA _SFR_MEM8(0x0B28) ++#define TCF2_HCMPA _SFR_MEM8(0x0B29) ++#define TCF2_LCMPB _SFR_MEM8(0x0B2A) ++#define TCF2_HCMPB _SFR_MEM8(0x0B2B) ++#define TCF2_LCMPC _SFR_MEM8(0x0B2C) ++#define TCF2_HCMPC _SFR_MEM8(0x0B2D) ++#define TCF2_LCMPD _SFR_MEM8(0x0B2E) ++#define TCF2_HCMPD _SFR_MEM8(0x0B2F) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESF_CTRLA _SFR_MEM8(0x0B90) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTF0_DATA _SFR_MEM8(0x0BA0) ++#define USARTF0_STATUS _SFR_MEM8(0x0BA1) ++#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) ++#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) ++#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) ++#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) ++#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* CLK.USBCTRL bit masks and bit positions */ ++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ ++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ ++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ ++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ ++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ ++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ ++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ ++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ ++ ++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ ++#define CLK_USBSRC_gp 1 /* Clock Source group position. */ ++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ ++ ++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_USB_bm 0x40 /* USB bit mask. */ ++#define PR_USB_bp 6 /* USB bit position. */ ++ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ ++#define PR_EBI_bp 3 /* External Bus Interface bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ ++#define PR_DAC_bp 2 /* Port A DAC bit position. */ ++ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPB bit masks and bit positions */ ++/* PR_DAC Predefined. */ ++/* PR_DAC Predefined. */ ++ ++/* PR_ADC Predefined. */ ++/* PR_ADC Predefined. */ ++ ++/* PR_AC Predefined. */ ++/* PR_AC Predefined. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ ++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ ++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ ++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ ++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ ++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ ++ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ ++#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ ++ ++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ ++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ ++ ++#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ ++#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ ++ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ ++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ ++ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ ++ ++/* PORTCFG.EBIOUT bit masks and bit positions */ ++#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ ++#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ ++#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ ++#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ ++#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ ++#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ ++ ++#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ ++#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ ++#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ ++#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ ++#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ ++#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ ++ ++/* PORTCFG.EVOUTSEL bit masks and bit positions */ ++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ ++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ ++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ ++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ ++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ ++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ ++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ ++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ ++ ++/* AES - AES Module */ ++/* AES.CTRL bit masks and bit positions */ ++#define AES_START_bm 0x80 /* Start/Run bit mask. */ ++#define AES_START_bp 7 /* Start/Run bit position. */ ++ ++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ ++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ ++ ++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ ++#define AES_RESET_bp 5 /* AES Software Reset bit position. */ ++ ++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ ++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ ++ ++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ ++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ ++ ++/* AES.STATUS bit masks and bit positions */ ++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ ++#define AES_ERROR_bp 7 /* AES Error bit position. */ ++ ++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ ++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ ++ ++/* AES.INTCTRL bit masks and bit positions */ ++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define AES_INTLVL_gp 0 /* Interrupt level group position. */ ++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* DMA - DMA Controller */ ++/* DMA_CH.CTRLA bit masks and bit positions */ ++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ ++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ ++ ++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ ++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ ++ ++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ ++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ ++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ ++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ ++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ ++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ ++ ++/* DMA_CH.CTRLB bit masks and bit positions */ ++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ ++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ ++ ++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ ++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ ++ ++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ ++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ ++ ++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ ++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ ++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ ++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ ++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ ++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ ++ ++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ ++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ ++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ ++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ ++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ ++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ ++ ++/* DMA_CH.ADDRCTRL bit masks and bit positions */ ++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ ++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ ++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ ++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ ++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ ++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ ++ ++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ ++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ ++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ ++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ ++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ ++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ ++ ++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ ++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ ++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ ++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ ++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ ++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ ++ ++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ ++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ ++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ ++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ ++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ ++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ ++ ++/* DMA_CH.TRIGSRC bit masks and bit positions */ ++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++/* DMA.CTRL bit masks and bit positions */ ++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define DMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define DMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ ++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ ++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ ++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ ++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ ++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ ++ ++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ ++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ ++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ ++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ ++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ ++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ ++ ++/* DMA.INTFLAGS bit masks and bit positions */ ++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++/* DMA.STATUS bit masks and bit positions */ ++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ ++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ ++ ++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ ++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ ++ ++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ ++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ ++ ++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ ++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ ++ ++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ ++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ ++ ++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ ++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ ++ ++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ ++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ ++ ++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ ++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH4MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH5MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH6MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH7MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM Predefined. */ ++/* EVSYS_QDIRM Predefined. */ ++ ++/* EVSYS_QDIEN Predefined. */ ++/* EVSYS_QDIEN Predefined. */ ++ ++/* EVSYS_QDEN Predefined. */ ++/* EVSYS_QDEN Predefined. */ ++ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH4CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM Predefined. */ ++/* EVSYS_QDIRM Predefined. */ ++ ++/* EVSYS_QDIEN Predefined. */ ++/* EVSYS_QDIEN Predefined. */ ++ ++/* EVSYS_QDEN Predefined. */ ++/* EVSYS_QDEN Predefined. */ ++ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH5CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH6CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH7CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ ++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HSMODE Predefined. */ ++/* AC_HSMODE Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ ++#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ ++#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ ++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ ++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ ++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ ++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ ++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ ++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ ++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ ++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ ++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ ++ ++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ ++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ ++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ ++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ ++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ ++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ ++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ ++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ ++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ ++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ ++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ ++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ ++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ ++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ ++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ ++ ++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ ++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ ++ ++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ ++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ ++ ++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ ++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ ++ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ ++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ ++#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ ++ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ ++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ ++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ ++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ ++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ ++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ ++ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ ++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ ++ ++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ ++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ ++ ++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ ++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ ++ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* DAC - Digital/Analog Converter */ ++/* DAC.CTRLA bit masks and bit positions */ ++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ ++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ ++ ++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ ++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ ++ ++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ ++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ ++ ++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ ++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ ++ ++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define DAC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* DAC.CTRLB bit masks and bit positions */ ++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ ++#define DAC_CHSEL_gp 5 /* Channel Select group position. */ ++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ ++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ ++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ ++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ ++ ++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ ++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ ++ ++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ ++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ ++ ++/* DAC.CTRLC bit masks and bit positions */ ++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ ++#define DAC_REFSEL_gp 3 /* Reference Select group position. */ ++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ ++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ ++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ ++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ ++ ++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ ++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ ++ ++/* DAC.EVCTRL bit masks and bit positions */ ++#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ ++#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ ++ ++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ ++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ ++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ ++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ ++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ ++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ ++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ ++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ ++ ++/* DAC.STATUS bit masks and bit positions */ ++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ ++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ ++ ++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ ++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ ++ ++/* DAC.CH0GAINCAL bit masks and bit positions */ ++#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH0OFFSETCAL bit masks and bit positions */ ++#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* DAC.CH1GAINCAL bit masks and bit positions */ ++#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH1OFFSETCAL bit masks and bit positions */ ++#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* RTC - Real-Time Counter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* USB - USB */ ++/* USB_EP.STATUS bit masks and bit positions */ ++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ ++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ ++ ++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ ++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ ++ ++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ ++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ ++ ++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ ++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ ++ ++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ ++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ ++ ++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ ++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ ++ ++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ ++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ ++ ++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ ++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ ++ ++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ ++ ++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ ++ ++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ ++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ ++ ++/* USB_EP.CTRL bit masks and bit positions */ ++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ ++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ ++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ ++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ ++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ ++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ ++ ++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ ++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ ++ ++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ ++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ ++ ++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ ++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ ++ ++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ ++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ ++ ++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ ++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ ++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ ++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ ++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ ++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ ++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ ++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ ++ ++/* USB_EP.CNT bit masks and bit positions */ ++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ ++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ ++ ++/* USB.CTRLA bit masks and bit positions */ ++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ ++#define USB_ENABLE_bp 7 /* USB Enable bit position. */ ++ ++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ ++#define USB_SPEED_bp 6 /* Speed Select bit position. */ ++ ++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ ++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ ++ ++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ ++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ ++ ++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ ++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ ++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ ++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ ++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ ++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ ++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ ++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ ++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ ++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ ++ ++/* USB.CTRLB bit masks and bit positions */ ++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ ++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ ++ ++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ ++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ ++ ++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ ++#define USB_GNACK_bp 1 /* Global NACK bit position. */ ++ ++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ ++#define USB_ATTACH_bp 0 /* Attach bit position. */ ++ ++/* USB.STATUS bit masks and bit positions */ ++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ ++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ ++ ++#define USB_RESUME_bm 0x04 /* Resume bit mask. */ ++#define USB_RESUME_bp 2 /* Resume bit position. */ ++ ++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ ++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ ++ ++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ ++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ ++ ++/* USB.ADDR bit masks and bit positions */ ++#define USB_ADDR_gm 0x7F /* Device Address group mask. */ ++#define USB_ADDR_gp 0 /* Device Address group position. */ ++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ ++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ ++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ ++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ ++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ ++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ ++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ ++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ ++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ ++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ ++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ ++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ ++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ ++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ ++ ++/* USB.FIFOWP bit masks and bit positions */ ++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ ++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ ++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ ++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ ++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ ++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ ++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ ++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ ++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ ++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ ++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ ++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ ++ ++/* USB.FIFORP bit masks and bit positions */ ++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ ++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ ++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ ++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ ++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ ++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ ++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ ++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ ++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ ++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ ++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ ++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ ++ ++/* USB.INTCTRLA bit masks and bit positions */ ++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ ++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ ++ ++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ ++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ ++ ++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ ++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ ++ ++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ ++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ ++ ++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* USB.INTCTRLB bit masks and bit positions */ ++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ ++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ ++ ++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ ++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ ++ ++/* USB.INTFLAGSACLR bit masks and bit positions */ ++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ ++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ ++ ++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ ++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ ++ ++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ ++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ ++ ++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ ++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ ++ ++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ ++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ ++ ++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ ++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ ++ ++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ ++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ ++ ++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ ++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSASET bit masks and bit positions */ ++/* USB_SOFIF Predefined. */ ++/* USB_SOFIF Predefined. */ ++ ++/* USB_SUSPENDIF Predefined. */ ++/* USB_SUSPENDIF Predefined. */ ++ ++/* USB_RESUMEIF Predefined. */ ++/* USB_RESUMEIF Predefined. */ ++ ++/* USB_RSTIF Predefined. */ ++/* USB_RSTIF Predefined. */ ++ ++/* USB_CRCIF Predefined. */ ++/* USB_CRCIF Predefined. */ ++ ++/* USB_UNFIF Predefined. */ ++/* USB_UNFIF Predefined. */ ++ ++/* USB_OVFIF Predefined. */ ++/* USB_OVFIF Predefined. */ ++ ++/* USB_STALLIF Predefined. */ ++/* USB_STALLIF Predefined. */ ++ ++/* USB.INTFLAGSBCLR bit masks and bit positions */ ++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ ++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ ++ ++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ ++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSBSET bit masks and bit positions */ ++/* USB_TRNIF Predefined. */ ++/* USB_TRNIF Predefined. */ ++ ++/* USB_SETUPIF Predefined. */ ++/* USB_SETUPIF Predefined. */ ++ ++/* PORT - I/O Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_SPI_bm 0x20 /* SPI bit mask. */ ++#define PORT_SPI_bp 5 /* SPI bit position. */ ++ ++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ ++#define PORT_USART0_bp 4 /* USART0 bit position. */ ++ ++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ ++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ ++ ++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ ++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ ++ ++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ ++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ ++ ++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ ++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD Predefined. */ ++/* TC0_CMD Predefined. */ ++ ++/* TC0_LUPD Predefined. */ ++/* TC0_LUPD Predefined. */ ++ ++/* TC0_DIR Predefined. */ ++/* TC0_DIR Predefined. */ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV Predefined. */ ++/* TC0_CCDBV Predefined. */ ++ ++/* TC0_CCCBV Predefined. */ ++/* TC0_CCCBV Predefined. */ ++ ++/* TC0_CCBBV Predefined. */ ++/* TC0_CCBBV Predefined. */ ++ ++/* TC0_CCABV Predefined. */ ++/* TC0_CCABV Predefined. */ ++ ++/* TC0_PERBV Predefined. */ ++/* TC0_PERBV Predefined. */ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD Predefined. */ ++/* TC1_CMD Predefined. */ ++ ++/* TC1_LUPD Predefined. */ ++/* TC1_LUPD Predefined. */ ++ ++/* TC1_DIR Predefined. */ ++/* TC1_DIR Predefined. */ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV Predefined. */ ++/* TC1_CCBBV Predefined. */ ++ ++/* TC1_CCABV Predefined. */ ++/* TC1_CCABV Predefined. */ ++ ++/* TC1_PERBV Predefined. */ ++/* TC1_PERBV Predefined. */ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++/* TC2.CTRLA bit masks and bit positions */ ++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC2.CTRLB bit masks and bit positions */ ++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ ++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ ++ ++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ ++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ ++ ++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ ++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ ++ ++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ ++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ ++ ++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ ++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ ++ ++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ ++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ ++ ++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ ++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ ++ ++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ ++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ ++ ++/* TC2.CTRLC bit masks and bit positions */ ++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ ++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ ++ ++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ ++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ ++ ++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ ++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ ++ ++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ ++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ ++ ++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ ++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ ++ ++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ ++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ ++ ++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ ++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ ++ ++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ ++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ ++ ++/* TC2.CTRLE bit masks and bit positions */ ++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC2.INTCTRLA bit masks and bit positions */ ++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ ++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ ++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ ++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ ++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ ++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ ++ ++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ ++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ ++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ ++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ ++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ ++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ ++ ++/* TC2.INTCTRLB bit masks and bit positions */ ++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ ++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ ++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ ++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ ++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ ++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ ++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ ++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ ++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ ++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ ++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ ++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ ++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ ++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ ++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ ++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ ++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ ++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ ++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ ++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ ++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ ++ ++/* TC2.CTRLF bit masks and bit positions */ ++#define TC2_CMD_gm 0x0C /* Command group mask. */ ++#define TC2_CMD_gp 2 /* Command group position. */ ++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC2_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC2_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ ++#define TC2_CMDEN_gp 0 /* Command Enable group position. */ ++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ ++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ ++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ ++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ ++ ++/* TC2.INTFLAGS bit masks and bit positions */ ++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ ++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ ++ ++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ ++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ ++ ++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ ++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ ++ ++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ ++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ ++ ++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ ++ ++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ ++ ++/* AWEX - Timer/Counter Advanced Waveform Extension */ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++/* AWEX.STATUSSET bit masks and bit positions */ ++/* AWEX_FDF Predefined. */ ++/* AWEX_FDF Predefined. */ ++ ++/* AWEX_DTHSBUFV Predefined. */ ++/* AWEX_DTHSBUFV Predefined. */ ++ ++/* AWEX_DTLSBUFV Predefined. */ ++/* AWEX_DTLSBUFV Predefined. */ ++ ++/* HIRES - Timer/Counter High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ ++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ ++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ ++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ ++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ ++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ ++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ ++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ ++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ ++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ ++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ ++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ ++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ ++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ ++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ ++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ ++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ ++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ ++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ ++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ ++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* LOCKBIT - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* DMA interrupt vectors */ ++#define DMA_CH0_vect_num 6 ++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ ++#define DMA_CH1_vect_num 7 ++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ ++#define DMA_CH2_vect_num 8 ++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ ++#define DMA_CH3_vect_num 9 ++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LUNF_vect_num 14 ++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_HUNF_vect_num 15 ++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPA_vect_num 16 ++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPB_vect_num 17 ++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPC_vect_num 18 ++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPD_vect_num 19 ++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* USARTC1 interrupt vectors */ ++#define USARTC1_RXC_vect_num 28 ++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ ++#define USARTC1_DRE_vect_num 29 ++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ ++#define USARTC1_TXC_vect_num 30 ++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ ++ ++/* AES interrupt vectors */ ++#define AES_INT_vect_num 31 ++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* ACB interrupt vectors */ ++#define ACB_AC0_vect_num 36 ++#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ ++#define ACB_AC1_vect_num 37 ++#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ ++#define ACB_ACW_vect_num 38 ++#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ ++ ++/* ADCB interrupt vectors */ ++#define ADCB_CH0_vect_num 39 ++#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ ++#define ADCB_CH1_vect_num 40 ++#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ ++#define ADCB_CH2_vect_num 41 ++#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ ++#define ADCB_CH3_vect_num 42 ++#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LUNF_vect_num 47 ++#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_HUNF_vect_num 48 ++#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPA_vect_num 49 ++#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPB_vect_num 50 ++#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPC_vect_num 51 ++#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPD_vect_num 52 ++#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ ++ ++/* TCE1 interrupt vectors */ ++#define TCE1_OVF_vect_num 53 ++#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ ++#define TCE1_ERR_vect_num 54 ++#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ ++#define TCE1_CCA_vect_num 55 ++#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ ++#define TCE1_CCB_vect_num 56 ++#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ ++ ++/* SPIE interrupt vectors */ ++#define SPIE_INT_vect_num 57 ++#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* USARTE1 interrupt vectors */ ++#define USARTE1_RXC_vect_num 61 ++#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ ++#define USARTE1_DRE_vect_num 62 ++#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ ++#define USARTE1_TXC_vect_num 63 ++#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++#define ADCA_CH1_vect_num 72 ++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ ++#define ADCA_CH2_vect_num 73 ++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ ++#define ADCA_CH3_vect_num 74 ++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LUNF_vect_num 77 ++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_HUNF_vect_num 78 ++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPA_vect_num 79 ++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPB_vect_num 80 ++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPC_vect_num 81 ++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPD_vect_num 82 ++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ ++ ++/* TCD1 interrupt vectors */ ++#define TCD1_OVF_vect_num 83 ++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ ++#define TCD1_ERR_vect_num 84 ++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ ++#define TCD1_CCA_vect_num 85 ++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ ++#define TCD1_CCB_vect_num 86 ++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* USARTD1 interrupt vectors */ ++#define USARTD1_RXC_vect_num 91 ++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ ++#define USARTD1_DRE_vect_num 92 ++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ ++#define USARTD1_TXC_vect_num 93 ++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ ++ ++/* PORTF interrupt vectors */ ++#define PORTF_INT0_vect_num 104 ++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ ++#define PORTF_INT1_vect_num 105 ++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_OVF_vect_num 108 ++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LUNF_vect_num 108 ++#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_ERR_vect_num 109 ++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_HUNF_vect_num 109 ++#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCA_vect_num 110 ++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPA_vect_num 110 ++#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCB_vect_num 111 ++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPB_vect_num 111 ++#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCC_vect_num 112 ++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPC_vect_num 112 ++#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCD_vect_num 113 ++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPD_vect_num 113 ++#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ ++ ++/* USARTF0 interrupt vectors */ ++#define USARTF0_RXC_vect_num 119 ++#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ ++#define USARTF0_DRE_vect_num 120 ++#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ ++#define USARTF0_TXC_vect_num 121 ++#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ ++ ++/* USB interrupt vectors */ ++#define USB_BUSEVENT_vect_num 125 ++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ ++#define USB_TRNCOMPL_vect_num 126 ++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (127 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (204800) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (196608) ++#define APP_SECTION_PAGE_SIZE (512) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x2E000) ++#define APPTABLE_SECTION_SIZE (8192) ++#define APPTABLE_SECTION_PAGE_SIZE (512) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x30000) ++#define BOOT_SECTION_SIZE (8192) ++#define BOOT_SECTION_PAGE_SIZE (512) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (24576) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (2048) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (16384) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (2048) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (6) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (512) ++#define USER_SIGNATURES_PAGE_SIZE (512) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (512) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 512 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 */ ++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ ++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ ++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ ++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ ++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ ++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ ++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ ++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ ++#define FUSE0_DEFAULT (0xFF) ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x97 ++#define SIGNATURE_2 0x44 ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA192A3U_H_INCLUDED */ ++ +diff --git a/include/avr/iox192c3.h b/include/avr/iox192c3.h +new file mode 100644 +index 0000000..3b8a6be +--- /dev/null ++++ b/include/avr/iox192c3.h +@@ -0,0 +1,6216 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox192c3.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA192C3_H_INCLUDED ++#define _AVR_ATXMEGA192C3_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t USBCTRL; /* USB Control Register */ ++} CLK_t; ++ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t reserved_0x02; ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++/* USB Prescaler Division Factor */ ++typedef enum CLK_USBPSDIV_enum ++{ ++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ ++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ ++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ ++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ ++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ ++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ ++} CLK_USBPSDIV_t; ++ ++/* USB Clock Source */ ++typedef enum CLK_USBSRC_enum ++{ ++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ ++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ ++} CLK_USBSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 2 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC2MCREF_enum ++{ ++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC2MCREF_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++ register8_t reserved_0x05; ++ register8_t EVOUTSEL; /* Event Output Select */ ++} PORTCFG_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP02MAP_enum ++{ ++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP02MAP_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP13MAP_enum ++{ ++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP13MAP_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t reserved_0x07; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++} ADC_t; ++ ++/* Current Limitation */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ ++} ADC_CURRLIMIT_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ ++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ ++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ ++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* SDA Hold Time */ ++typedef enum TWI_SDAHOLD_enum ++{ ++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ ++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ ++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ ++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ ++} TWI_SDAHOLD_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USB - USB ++-------------------------------------------------------------------------- ++*/ ++ ++/* USB Endpoint */ ++typedef struct USB_EP_struct ++{ ++ register8_t STATUS; /* Endpoint Status */ ++ register8_t CTRL; /* Endpoint Control */ ++ _WORDREGISTER(CNT); /* USB Endpoint Counter */ ++ _WORDREGISTER(DATAPTR); /* Data Pointer */ ++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ ++} USB_EP_t; ++ ++ ++/* Universal Serial Bus */ ++typedef struct USB_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t FIFOWP; /* FIFO Write Pointer Register */ ++ register8_t FIFORP; /* FIFO Read Pointer Register */ ++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ ++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ ++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ ++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t reserved_0x20; ++ register8_t reserved_0x21; ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t CAL0; /* Calibration Byte 0 */ ++ register8_t CAL1; /* Calibration Byte 1 */ ++} USB_t; ++ ++ ++/* USB Endpoint Table */ ++typedef struct USB_EP_TABLE_struct ++{ ++ USB_EP_t EP0OUT; /* Endpoint 0 */ ++ USB_EP_t EP0IN; /* Endpoint 0 */ ++ USB_EP_t EP1OUT; /* Endpoint 1 */ ++ USB_EP_t EP1IN; /* Endpoint 1 */ ++ USB_EP_t EP2OUT; /* Endpoint 2 */ ++ USB_EP_t EP2IN; /* Endpoint 2 */ ++ USB_EP_t EP3OUT; /* Endpoint 3 */ ++ USB_EP_t EP3IN; /* Endpoint 3 */ ++ USB_EP_t EP4OUT; /* Endpoint 4 */ ++ USB_EP_t EP4IN; /* Endpoint 4 */ ++ USB_EP_t EP5OUT; /* Endpoint 5 */ ++ USB_EP_t EP5IN; /* Endpoint 5 */ ++ USB_EP_t EP6OUT; /* Endpoint 6 */ ++ USB_EP_t EP6IN; /* Endpoint 6 */ ++ USB_EP_t EP7OUT; /* Endpoint 7 */ ++ USB_EP_t EP7IN; /* Endpoint 7 */ ++ USB_EP_t EP8OUT; /* Endpoint 8 */ ++ USB_EP_t EP8IN; /* Endpoint 8 */ ++ USB_EP_t EP9OUT; /* Endpoint 9 */ ++ USB_EP_t EP9IN; /* Endpoint 9 */ ++ USB_EP_t EP10OUT; /* Endpoint 10 */ ++ USB_EP_t EP10IN; /* Endpoint 10 */ ++ USB_EP_t EP11OUT; /* Endpoint 11 */ ++ USB_EP_t EP11IN; /* Endpoint 11 */ ++ USB_EP_t EP12OUT; /* Endpoint 12 */ ++ USB_EP_t EP12IN; /* Endpoint 12 */ ++ USB_EP_t EP13OUT; /* Endpoint 13 */ ++ USB_EP_t EP13IN; /* Endpoint 13 */ ++ USB_EP_t EP14OUT; /* Endpoint 14 */ ++ USB_EP_t EP14IN; /* Endpoint 14 */ ++ USB_EP_t EP15OUT; /* Endpoint 15 */ ++ USB_EP_t EP15IN; /* Endpoint 15 */ ++ register8_t reserved_0x100; ++ register8_t reserved_0x101; ++ register8_t reserved_0x102; ++ register8_t reserved_0x103; ++ register8_t reserved_0x104; ++ register8_t reserved_0x105; ++ register8_t reserved_0x106; ++ register8_t reserved_0x107; ++ register8_t reserved_0x108; ++ register8_t reserved_0x109; ++ register8_t reserved_0x10A; ++ register8_t reserved_0x10B; ++ register8_t reserved_0x10C; ++ register8_t reserved_0x10D; ++ register8_t reserved_0x10E; ++ register8_t reserved_0x10F; ++ register8_t FRAMENUML; /* Frame Number Low Byte */ ++ register8_t FRAMENUMH; /* Frame Number High Byte */ ++} USB_EP_TABLE_t; ++ ++/* Interrupt level */ ++typedef enum USB_INTLVL_enum ++{ ++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} USB_INTLVL_t; ++ ++/* USB Endpoint Type */ ++typedef enum USB_EP_TYPE_enum ++{ ++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ ++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ ++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ ++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ ++} USB_EP_TYPE_t; ++ ++/* USB Endpoint Buffersize */ ++typedef enum USB_EP_BUFSIZE_enum ++{ ++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ ++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ ++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ ++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ ++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ ++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ ++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ ++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ ++} USB_EP_BUFSIZE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - I/O Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* I/O Port Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Byte Mode */ ++typedef enum TC_BYTEM_enum ++{ ++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ ++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ ++} TC_BYTEM_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC2 - 16-bit Timer/Counter type 2 ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter type 2 */ ++typedef struct TC2_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t reserved_0x03; ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t reserved_0x08; ++ register8_t CTRLF; /* Control Register F */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t LCNT; /* Low Byte Count */ ++ register8_t HCNT; /* High Byte Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t LPER; /* Low Byte Period */ ++ register8_t HPER; /* High Byte Period */ ++ register8_t LCMPA; /* Low Byte Compare A */ ++ register8_t HCMPA; /* High Byte Compare A */ ++ register8_t LCMPB; /* Low Byte Compare B */ ++ register8_t HCMPB; /* High Byte Compare B */ ++ register8_t LCMPC; /* Low Byte Compare C */ ++ register8_t HCMPC; /* High Byte Compare C */ ++ register8_t LCMPD; /* Low Byte Compare D */ ++ register8_t HCMPD; /* High Byte Compare D */ ++} TC2_t; ++ ++/* Clock Selection */ ++typedef enum TC2_CLKSEL_enum ++{ ++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC2_CLKSEL_t; ++ ++/* Byte Mode */ ++typedef enum TC2_BYTEM_enum ++{ ++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ ++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ ++} TC2_BYTEM_t; ++ ++/* High Byte Underflow Interrupt Level */ ++typedef enum TC2_HUNFINTLVL_enum ++{ ++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_HUNFINTLVL_t; ++ ++/* Low Byte Underflow Interrupt Level */ ++typedef enum TC2_LUNFINTLVL_enum ++{ ++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LUNFINTLVL_t; ++ ++/* Low Byte Compare D Interrupt Level */ ++typedef enum TC2_LCMPDINTLVL_enum ++{ ++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC2_LCMPDINTLVL_t; ++ ++/* Low Byte Compare C Interrupt Level */ ++typedef enum TC2_LCMPCINTLVL_enum ++{ ++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC2_LCMPCINTLVL_t; ++ ++/* Low Byte Compare B Interrupt Level */ ++typedef enum TC2_LCMPBINTLVL_enum ++{ ++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_LCMPBINTLVL_t; ++ ++/* Low Byte Compare A Interrupt Level */ ++typedef enum TC2_LCMPAINTLVL_enum ++{ ++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LCMPAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMD_enum ++{ ++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC2_CMD_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMDEN_enum ++{ ++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ ++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ ++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ ++} TC2_CMDEN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AWEX - Timer/Counter Advanced Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - Timer/Counter High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t reserved_0x00; ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* Timer Oscillator pin location */ ++typedef enum TOSCSEL_enum ++{ ++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ ++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ ++} TOSCSEL_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* BOD operation */ ++typedef enum BODACT_enum ++{ ++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BODACT_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WDP_enum ++{ ++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ ++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ ++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ ++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ ++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ ++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ ++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ ++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ ++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ ++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ ++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ ++} WDP_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LOCKBIT - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ ++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t USBCAL0; /* USB Calibration Byte 0 */ ++ register8_t USBCAL1; /* USB Calibration Byte 1 */ ++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ ++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ ++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ ++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ ++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ ++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ ++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ ++#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) ++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) ++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) ++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++#define CLK_USBCTRL _SFR_MEM8(0x0044) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLL - DFLL */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* USB - Universal Serial Bus */ ++#define USB_CTRLA _SFR_MEM8(0x04C0) ++#define USB_CTRLB _SFR_MEM8(0x04C1) ++#define USB_STATUS _SFR_MEM8(0x04C2) ++#define USB_ADDR _SFR_MEM8(0x04C3) ++#define USB_FIFOWP _SFR_MEM8(0x04C4) ++#define USB_FIFORP _SFR_MEM8(0x04C5) ++#define USB_EPPTR _SFR_MEM16(0x04C6) ++#define USB_INTCTRLA _SFR_MEM8(0x04C8) ++#define USB_INTCTRLB _SFR_MEM8(0x04C9) ++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) ++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) ++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) ++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) ++#define USB_CAL0 _SFR_MEM8(0x04FA) ++#define USB_CAL1 _SFR_MEM8(0x04FB) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_REMAP _SFR_MEM8(0x060E) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_REMAP _SFR_MEM8(0x062E) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_REMAP _SFR_MEM8(0x068E) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORT - I/O Ports */ ++#define PORTF_DIR _SFR_MEM8(0x06A0) ++#define PORTF_DIRSET _SFR_MEM8(0x06A1) ++#define PORTF_DIRCLR _SFR_MEM8(0x06A2) ++#define PORTF_DIRTGL _SFR_MEM8(0x06A3) ++#define PORTF_OUT _SFR_MEM8(0x06A4) ++#define PORTF_OUTSET _SFR_MEM8(0x06A5) ++#define PORTF_OUTCLR _SFR_MEM8(0x06A6) ++#define PORTF_OUTTGL _SFR_MEM8(0x06A7) ++#define PORTF_IN _SFR_MEM8(0x06A8) ++#define PORTF_INTCTRL _SFR_MEM8(0x06A9) ++#define PORTF_INT0MASK _SFR_MEM8(0x06AA) ++#define PORTF_INT1MASK _SFR_MEM8(0x06AB) ++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) ++#define PORTF_REMAP _SFR_MEM8(0x06AE) ++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) ++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) ++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) ++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) ++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) ++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) ++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) ++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCC2_CTRLA _SFR_MEM8(0x0800) ++#define TCC2_CTRLB _SFR_MEM8(0x0801) ++#define TCC2_CTRLC _SFR_MEM8(0x0802) ++#define TCC2_CTRLE _SFR_MEM8(0x0804) ++#define TCC2_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC2_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC2_CTRLF _SFR_MEM8(0x0809) ++#define TCC2_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC2_LCNT _SFR_MEM8(0x0820) ++#define TCC2_HCNT _SFR_MEM8(0x0821) ++#define TCC2_LPER _SFR_MEM8(0x0826) ++#define TCC2_HPER _SFR_MEM8(0x0827) ++#define TCC2_LCMPA _SFR_MEM8(0x0828) ++#define TCC2_HCMPA _SFR_MEM8(0x0829) ++#define TCC2_LCMPB _SFR_MEM8(0x082A) ++#define TCC2_HCMPB _SFR_MEM8(0x082B) ++#define TCC2_LCMPC _SFR_MEM8(0x082C) ++#define TCC2_HCMPC _SFR_MEM8(0x082D) ++#define TCC2_LCMPD _SFR_MEM8(0x082E) ++#define TCC2_HCMPD _SFR_MEM8(0x082F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_STATUSSET _SFR_MEM8(0x0885) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCD2_CTRLA _SFR_MEM8(0x0900) ++#define TCD2_CTRLB _SFR_MEM8(0x0901) ++#define TCD2_CTRLC _SFR_MEM8(0x0902) ++#define TCD2_CTRLE _SFR_MEM8(0x0904) ++#define TCD2_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD2_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD2_CTRLF _SFR_MEM8(0x0909) ++#define TCD2_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD2_LCNT _SFR_MEM8(0x0920) ++#define TCD2_HCNT _SFR_MEM8(0x0921) ++#define TCD2_LPER _SFR_MEM8(0x0926) ++#define TCD2_HPER _SFR_MEM8(0x0927) ++#define TCD2_LCMPA _SFR_MEM8(0x0928) ++#define TCD2_HCMPA _SFR_MEM8(0x0929) ++#define TCD2_LCMPB _SFR_MEM8(0x092A) ++#define TCD2_HCMPB _SFR_MEM8(0x092B) ++#define TCD2_LCMPC _SFR_MEM8(0x092C) ++#define TCD2_HCMPC _SFR_MEM8(0x092D) ++#define TCD2_LCMPD _SFR_MEM8(0x092E) ++#define TCD2_HCMPD _SFR_MEM8(0x092F) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCE2_CTRLA _SFR_MEM8(0x0A00) ++#define TCE2_CTRLB _SFR_MEM8(0x0A01) ++#define TCE2_CTRLC _SFR_MEM8(0x0A02) ++#define TCE2_CTRLE _SFR_MEM8(0x0A04) ++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE2_CTRLF _SFR_MEM8(0x0A09) ++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE2_LCNT _SFR_MEM8(0x0A20) ++#define TCE2_HCNT _SFR_MEM8(0x0A21) ++#define TCE2_LPER _SFR_MEM8(0x0A26) ++#define TCE2_HPER _SFR_MEM8(0x0A27) ++#define TCE2_LCMPA _SFR_MEM8(0x0A28) ++#define TCE2_HCMPA _SFR_MEM8(0x0A29) ++#define TCE2_LCMPB _SFR_MEM8(0x0A2A) ++#define TCE2_HCMPB _SFR_MEM8(0x0A2B) ++#define TCE2_LCMPC _SFR_MEM8(0x0A2C) ++#define TCE2_HCMPC _SFR_MEM8(0x0A2D) ++#define TCE2_LCMPD _SFR_MEM8(0x0A2E) ++#define TCE2_HCMPD _SFR_MEM8(0x0A2F) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCF0_CTRLA _SFR_MEM8(0x0B00) ++#define TCF0_CTRLB _SFR_MEM8(0x0B01) ++#define TCF0_CTRLC _SFR_MEM8(0x0B02) ++#define TCF0_CTRLD _SFR_MEM8(0x0B03) ++#define TCF0_CTRLE _SFR_MEM8(0x0B04) ++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) ++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) ++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) ++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) ++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF0_TEMP _SFR_MEM8(0x0B0F) ++#define TCF0_CNT _SFR_MEM16(0x0B20) ++#define TCF0_PER _SFR_MEM16(0x0B26) ++#define TCF0_CCA _SFR_MEM16(0x0B28) ++#define TCF0_CCB _SFR_MEM16(0x0B2A) ++#define TCF0_CCC _SFR_MEM16(0x0B2C) ++#define TCF0_CCD _SFR_MEM16(0x0B2E) ++#define TCF0_PERBUF _SFR_MEM16(0x0B36) ++#define TCF0_CCABUF _SFR_MEM16(0x0B38) ++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) ++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) ++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCF2_CTRLA _SFR_MEM8(0x0B00) ++#define TCF2_CTRLB _SFR_MEM8(0x0B01) ++#define TCF2_CTRLC _SFR_MEM8(0x0B02) ++#define TCF2_CTRLE _SFR_MEM8(0x0B04) ++#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF2_CTRLF _SFR_MEM8(0x0B09) ++#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF2_LCNT _SFR_MEM8(0x0B20) ++#define TCF2_HCNT _SFR_MEM8(0x0B21) ++#define TCF2_LPER _SFR_MEM8(0x0B26) ++#define TCF2_HPER _SFR_MEM8(0x0B27) ++#define TCF2_LCMPA _SFR_MEM8(0x0B28) ++#define TCF2_HCMPA _SFR_MEM8(0x0B29) ++#define TCF2_LCMPB _SFR_MEM8(0x0B2A) ++#define TCF2_HCMPB _SFR_MEM8(0x0B2B) ++#define TCF2_LCMPC _SFR_MEM8(0x0B2C) ++#define TCF2_HCMPC _SFR_MEM8(0x0B2D) ++#define TCF2_LCMPD _SFR_MEM8(0x0B2E) ++#define TCF2_HCMPD _SFR_MEM8(0x0B2F) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* CLK.USBCTRL bit masks and bit positions */ ++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ ++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ ++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ ++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ ++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ ++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ ++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ ++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ ++ ++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ ++#define CLK_USBSRC_gp 1 /* Clock Source group position. */ ++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ ++ ++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_USB_bm 0x40 /* USB bit mask. */ ++#define PR_USB_bp 6 /* USB bit position. */ ++ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ ++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ ++ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ ++ ++/* PORTCFG.EVOUTSEL bit masks and bit positions */ ++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ ++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ ++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ ++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ ++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ ++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ ++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ ++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ ++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ ++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ ++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ ++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ ++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ ++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ ++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ ++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ ++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ ++ ++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ ++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ ++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ ++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ ++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ ++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ ++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ ++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ ++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ ++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ ++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* RTC - Real-Time Counter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* USB - USB */ ++/* USB_EP.STATUS bit masks and bit positions */ ++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ ++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ ++ ++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ ++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ ++ ++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ ++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ ++ ++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ ++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ ++ ++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ ++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ ++ ++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ ++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ ++ ++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ ++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ ++ ++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ ++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ ++ ++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ ++ ++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ ++ ++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ ++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ ++ ++/* USB_EP.CTRL bit masks and bit positions */ ++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ ++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ ++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ ++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ ++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ ++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ ++ ++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ ++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ ++ ++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ ++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ ++ ++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ ++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ ++ ++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ ++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ ++ ++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ ++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ ++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ ++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ ++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ ++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ ++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ ++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ ++ ++/* USB_EP.CNT bit masks and bit positions */ ++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ ++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ ++ ++/* USB.CTRLA bit masks and bit positions */ ++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ ++#define USB_ENABLE_bp 7 /* USB Enable bit position. */ ++ ++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ ++#define USB_SPEED_bp 6 /* Speed Select bit position. */ ++ ++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ ++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ ++ ++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ ++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ ++ ++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ ++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ ++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ ++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ ++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ ++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ ++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ ++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ ++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ ++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ ++ ++/* USB.CTRLB bit masks and bit positions */ ++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ ++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ ++ ++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ ++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ ++ ++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ ++#define USB_GNACK_bp 1 /* Global NACK bit position. */ ++ ++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ ++#define USB_ATTACH_bp 0 /* Attach bit position. */ ++ ++/* USB.STATUS bit masks and bit positions */ ++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ ++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ ++ ++#define USB_RESUME_bm 0x04 /* Resume bit mask. */ ++#define USB_RESUME_bp 2 /* Resume bit position. */ ++ ++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ ++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ ++ ++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ ++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ ++ ++/* USB.ADDR bit masks and bit positions */ ++#define USB_ADDR_gm 0x7F /* Device Address group mask. */ ++#define USB_ADDR_gp 0 /* Device Address group position. */ ++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ ++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ ++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ ++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ ++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ ++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ ++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ ++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ ++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ ++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ ++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ ++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ ++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ ++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ ++ ++/* USB.FIFOWP bit masks and bit positions */ ++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ ++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ ++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ ++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ ++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ ++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ ++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ ++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ ++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ ++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ ++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ ++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ ++ ++/* USB.FIFORP bit masks and bit positions */ ++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ ++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ ++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ ++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ ++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ ++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ ++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ ++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ ++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ ++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ ++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ ++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ ++ ++/* USB.INTCTRLA bit masks and bit positions */ ++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ ++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ ++ ++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ ++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ ++ ++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ ++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ ++ ++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ ++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ ++ ++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* USB.INTCTRLB bit masks and bit positions */ ++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ ++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ ++ ++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ ++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ ++ ++/* USB.INTFLAGSACLR bit masks and bit positions */ ++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ ++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ ++ ++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ ++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ ++ ++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ ++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ ++ ++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ ++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ ++ ++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ ++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ ++ ++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ ++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ ++ ++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ ++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ ++ ++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ ++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSASET bit masks and bit positions */ ++/* USB_SOFIF Predefined. */ ++/* USB_SOFIF Predefined. */ ++ ++/* USB_SUSPENDIF Predefined. */ ++/* USB_SUSPENDIF Predefined. */ ++ ++/* USB_RESUMEIF Predefined. */ ++/* USB_RESUMEIF Predefined. */ ++ ++/* USB_RSTIF Predefined. */ ++/* USB_RSTIF Predefined. */ ++ ++/* USB_CRCIF Predefined. */ ++/* USB_CRCIF Predefined. */ ++ ++/* USB_UNFIF Predefined. */ ++/* USB_UNFIF Predefined. */ ++ ++/* USB_OVFIF Predefined. */ ++/* USB_OVFIF Predefined. */ ++ ++/* USB_STALLIF Predefined. */ ++/* USB_STALLIF Predefined. */ ++ ++/* USB.INTFLAGSBCLR bit masks and bit positions */ ++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ ++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ ++ ++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ ++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSBSET bit masks and bit positions */ ++/* USB_TRNIF Predefined. */ ++/* USB_TRNIF Predefined. */ ++ ++/* USB_SETUPIF Predefined. */ ++/* USB_SETUPIF Predefined. */ ++ ++/* PORT - I/O Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_SPI_bm 0x20 /* SPI bit mask. */ ++#define PORT_SPI_bp 5 /* SPI bit position. */ ++ ++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ ++#define PORT_USART0_bp 4 /* USART0 bit position. */ ++ ++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ ++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ ++ ++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ ++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ ++ ++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ ++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ ++ ++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ ++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD Predefined. */ ++/* TC0_CMD Predefined. */ ++ ++/* TC0_LUPD Predefined. */ ++/* TC0_LUPD Predefined. */ ++ ++/* TC0_DIR Predefined. */ ++/* TC0_DIR Predefined. */ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV Predefined. */ ++/* TC0_CCDBV Predefined. */ ++ ++/* TC0_CCCBV Predefined. */ ++/* TC0_CCCBV Predefined. */ ++ ++/* TC0_CCBBV Predefined. */ ++/* TC0_CCBBV Predefined. */ ++ ++/* TC0_CCABV Predefined. */ ++/* TC0_CCABV Predefined. */ ++ ++/* TC0_PERBV Predefined. */ ++/* TC0_PERBV Predefined. */ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD Predefined. */ ++/* TC1_CMD Predefined. */ ++ ++/* TC1_LUPD Predefined. */ ++/* TC1_LUPD Predefined. */ ++ ++/* TC1_DIR Predefined. */ ++/* TC1_DIR Predefined. */ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV Predefined. */ ++/* TC1_CCBBV Predefined. */ ++ ++/* TC1_CCABV Predefined. */ ++/* TC1_CCABV Predefined. */ ++ ++/* TC1_PERBV Predefined. */ ++/* TC1_PERBV Predefined. */ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++/* TC2.CTRLA bit masks and bit positions */ ++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC2.CTRLB bit masks and bit positions */ ++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ ++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ ++ ++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ ++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ ++ ++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ ++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ ++ ++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ ++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ ++ ++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ ++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ ++ ++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ ++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ ++ ++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ ++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ ++ ++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ ++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ ++ ++/* TC2.CTRLC bit masks and bit positions */ ++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ ++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ ++ ++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ ++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ ++ ++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ ++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ ++ ++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ ++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ ++ ++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ ++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ ++ ++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ ++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ ++ ++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ ++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ ++ ++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ ++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ ++ ++/* TC2.CTRLE bit masks and bit positions */ ++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC2.INTCTRLA bit masks and bit positions */ ++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ ++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ ++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ ++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ ++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ ++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ ++ ++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ ++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ ++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ ++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ ++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ ++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ ++ ++/* TC2.INTCTRLB bit masks and bit positions */ ++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ ++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ ++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ ++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ ++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ ++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ ++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ ++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ ++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ ++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ ++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ ++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ ++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ ++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ ++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ ++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ ++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ ++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ ++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ ++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ ++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ ++ ++/* TC2.CTRLF bit masks and bit positions */ ++#define TC2_CMD_gm 0x0C /* Command group mask. */ ++#define TC2_CMD_gp 2 /* Command group position. */ ++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC2_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC2_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ ++#define TC2_CMDEN_gp 0 /* Command Enable group position. */ ++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ ++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ ++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ ++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ ++ ++/* TC2.INTFLAGS bit masks and bit positions */ ++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ ++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ ++ ++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ ++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ ++ ++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ ++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ ++ ++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ ++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ ++ ++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ ++ ++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ ++ ++/* AWEX - Timer/Counter Advanced Waveform Extension */ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++/* AWEX.STATUSSET bit masks and bit positions */ ++/* AWEX_FDF Predefined. */ ++/* AWEX_FDF Predefined. */ ++ ++/* AWEX_DTHSBUFV Predefined. */ ++/* AWEX_DTHSBUFV Predefined. */ ++ ++/* AWEX_DTLSBUFV Predefined. */ ++/* AWEX_DTLSBUFV Predefined. */ ++ ++/* HIRES - Timer/Counter High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ ++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* LOCKBIT - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LUNF_vect_num 14 ++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_HUNF_vect_num 15 ++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPA_vect_num 16 ++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPB_vect_num 17 ++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPC_vect_num 18 ++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPD_vect_num 19 ++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LUNF_vect_num 47 ++#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_HUNF_vect_num 48 ++#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPA_vect_num 49 ++#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPB_vect_num 50 ++#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPC_vect_num 51 ++#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPD_vect_num 52 ++#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LUNF_vect_num 77 ++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_HUNF_vect_num 78 ++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPA_vect_num 79 ++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPB_vect_num 80 ++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPC_vect_num 81 ++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPD_vect_num 82 ++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* PORTF interrupt vectors */ ++#define PORTF_INT0_vect_num 104 ++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ ++#define PORTF_INT1_vect_num 105 ++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_OVF_vect_num 108 ++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LUNF_vect_num 108 ++#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_ERR_vect_num 109 ++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_HUNF_vect_num 109 ++#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCA_vect_num 110 ++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPA_vect_num 110 ++#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCB_vect_num 111 ++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPB_vect_num 111 ++#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCC_vect_num 112 ++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPC_vect_num 112 ++#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCD_vect_num 113 ++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPD_vect_num 113 ++#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ ++ ++/* USB interrupt vectors */ ++#define USB_BUSEVENT_vect_num 125 ++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ ++#define USB_TRNCOMPL_vect_num 126 ++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (127 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (204800) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (196608) ++#define APP_SECTION_PAGE_SIZE (512) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x2E000) ++#define APPTABLE_SECTION_SIZE (8192) ++#define APPTABLE_SECTION_PAGE_SIZE (512) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x30000) ++#define BOOT_SECTION_SIZE (8192) ++#define BOOT_SECTION_PAGE_SIZE (512) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (16384) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (2048) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (16384) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (2048) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (6) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (512) ++#define USER_SIGNATURES_PAGE_SIZE (512) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (64) ++#define PROD_SIGNATURES_PAGE_SIZE (512) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 512 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 Reserved */ ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x97 ++#define SIGNATURE_2 0x51 ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA192C3_H_INCLUDED */ ++ +diff --git a/include/avr/iox192d3.h b/include/avr/iox192d3.h +index 874685f..4a3c13a 100644 +--- a/include/avr/iox192d3.h ++++ b/include/avr/iox192d3.h +@@ -1,5655 +1,5704 @@ +-/* Copyright (c) 2009-2010 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iox192d3.h 2194 2010-11-16 15:10:51Z arcanum $ */ +- +-/* avr/iox192d3.h - definitions for ATxmega192D3 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iox192d3.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATxmega192D3_H_ +-#define _AVR_ATxmega192D3_H_ 1 +- +- +-/* Ungrouped common registers */ +-#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +-#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +-#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +-#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +-#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +-#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +-#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +-#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +-#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +-#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +-#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +-#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +-#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +-#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +-#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +-#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +- +-#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +-#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +-#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +-#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +-#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +-#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +-#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +-#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +-#define SREG _SFR_MEM8(0x003F) /* Status Register */ +- +- +-/* C Language Only */ +-#if !defined (__ASSEMBLER__) +- +-#include +- +-typedef volatile uint8_t register8_t; +-typedef volatile uint16_t register16_t; +-typedef volatile uint32_t register32_t; +- +- +-#ifdef _WORDREGISTER +-#undef _WORDREGISTER +-#endif +-#define _WORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register16_t regname; \ +- struct \ +- { \ +- register8_t regname ## L; \ +- register8_t regname ## H; \ +- }; \ +- } +- +-#ifdef _DWORDREGISTER +-#undef _DWORDREGISTER +-#endif +-#define _DWORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register32_t regname; \ +- struct \ +- { \ +- register8_t regname ## 0; \ +- register8_t regname ## 1; \ +- register8_t regname ## 2; \ +- register8_t regname ## 3; \ +- }; \ +- } +- +- +-/* +-========================================================================== +-IO Module Structures +-========================================================================== +-*/ +- +- +-/* +--------------------------------------------------------------------------- +-XOCD - On-Chip Debug System +--------------------------------------------------------------------------- +-*/ +- +-/* On-Chip Debug System */ +-typedef struct OCD_struct +-{ +- register8_t OCDR0; /* OCD Register 0 */ +- register8_t OCDR1; /* OCD Register 1 */ +-} OCD_t; +- +- +-/* CCP signatures */ +-typedef enum CCP_enum +-{ +- CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ +- CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +-} CCP_t; +- +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Clock System */ +-typedef struct CLK_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t PSCTRL; /* Prescaler Control Register */ +- register8_t LOCK; /* Lock register */ +- register8_t RTCCTRL; /* RTC Control Register */ +-} CLK_t; +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Power Reduction */ +-typedef struct PR_struct +-{ +- register8_t PRGEN; /* General Power Reduction */ +- register8_t PRPA; /* Power Reduction Port A */ +- register8_t PRPB; /* Power Reduction Port B */ +- register8_t PRPC; /* Power Reduction Port C */ +- register8_t PRPD; /* Power Reduction Port D */ +- register8_t PRPE; /* Power Reduction Port E */ +- register8_t PRPF; /* Power Reduction Port F */ +-} PR_t; +- +-/* System Clock Selection */ +-typedef enum CLK_SCLKSEL_enum +-{ +- CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ +- CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ +- CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ +- CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ +- CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +-} CLK_SCLKSEL_t; +- +-/* Prescaler A Division Factor */ +-typedef enum CLK_PSADIV_enum +-{ +- CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ +- CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ +- CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ +- CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ +- CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ +- CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ +- CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ +- CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ +- CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ +- CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +-} CLK_PSADIV_t; +- +-/* Prescaler B and C Division Factor */ +-typedef enum CLK_PSBCDIV_enum +-{ +- CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ +- CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ +- CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ +- CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +-} CLK_PSBCDIV_t; +- +-/* RTC Clock Source */ +-typedef enum CLK_RTCSRC_enum +-{ +- CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ +- CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ +- CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ +- CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +-} CLK_RTCSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-SLEEP - Sleep Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Sleep Controller */ +-typedef struct SLEEP_struct +-{ +- register8_t CTRL; /* Control Register */ +-} SLEEP_t; +- +-/* Sleep Mode */ +-typedef enum SLEEP_SMODE_enum +-{ +- SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ +- SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +- SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ +- SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ +- SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +-} SLEEP_SMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-OSC - Oscillator +--------------------------------------------------------------------------- +-*/ +- +-/* Oscillator */ +-typedef struct OSC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t XOSCCTRL; /* External Oscillator Control Register */ +- register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ +- register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ +- register8_t PLLCTRL; /* PLL Control REgister */ +- register8_t DFLLCTRL; /* DFLL Control Register */ +-} OSC_t; +- +-/* Oscillator Frequency Range */ +-typedef enum OSC_FRQRANGE_enum +-{ +- OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ +- OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ +- OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ +- OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +-} OSC_FRQRANGE_t; +- +-/* External Oscillator Selection and Startup Time */ +-typedef enum OSC_XOSCSEL_enum +-{ +- OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ +- OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ +- OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ +- OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ +- OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +-} OSC_XOSCSEL_t; +- +-/* PLL Clock Source */ +-typedef enum OSC_PLLSRC_enum +-{ +- OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ +- OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ +- OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +-} OSC_PLLSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-DFLL - DFLL +--------------------------------------------------------------------------- +-*/ +- +-/* DFLL */ +-typedef struct DFLL_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t CALA; /* Calibration Register A */ +- register8_t CALB; /* Calibration Register B */ +- register8_t COMP0; /* Oscillator Compare Register 0 */ +- register8_t COMP1; /* Oscillator Compare Register 1 */ +- register8_t COMP2; /* Oscillator Compare Register 2 */ +- register8_t reserved_0x07; +-} DFLL_t; +- +- +-/* +--------------------------------------------------------------------------- +-RST - Reset +--------------------------------------------------------------------------- +-*/ +- +-/* Reset */ +-typedef struct RST_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t CTRL; /* Control Register */ +-} RST_t; +- +- +-/* +--------------------------------------------------------------------------- +-WDT - Watch-Dog Timer +--------------------------------------------------------------------------- +-*/ +- +-/* Watch-Dog Timer */ +-typedef struct WDT_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t WINCTRL; /* Windowed Mode Control */ +- register8_t STATUS; /* Status */ +-} WDT_t; +- +-/* Period setting */ +-typedef enum WDT_PER_enum +-{ +- WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ +- WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ +- WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ +- WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_PER_t; +- +-/* Closed window period */ +-typedef enum WDT_WPER_enum +-{ +- WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ +- WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ +- WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ +- WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_WPER_t; +- +- +-/* +--------------------------------------------------------------------------- +-MCU - MCU Control +--------------------------------------------------------------------------- +-*/ +- +-/* MCU Control */ +-typedef struct MCU_struct +-{ +- register8_t DEVID0; /* Device ID byte 0 */ +- register8_t DEVID1; /* Device ID byte 1 */ +- register8_t DEVID2; /* Device ID byte 2 */ +- register8_t REVID; /* Revision ID */ +- register8_t JTAGUID; /* JTAG User ID */ +- register8_t reserved_0x05; +- register8_t MCUCR; /* MCU Control */ +- register8_t reserved_0x07; +- register8_t EVSYSLOCK; /* Event System Lock */ +- register8_t AWEXLOCK; /* AWEX Lock */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +-} MCU_t; +- +- +-/* +--------------------------------------------------------------------------- +-PMIC - Programmable Multi-level Interrupt Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Programmable Multi-level Interrupt Controller */ +-typedef struct PMIC_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t INTPRI; /* Interrupt Priority */ +- register8_t CTRL; /* Control Register */ +-} PMIC_t; +- +- +-/* +--------------------------------------------------------------------------- +-EVSYS - Event System +--------------------------------------------------------------------------- +-*/ +- +-/* Event System */ +-typedef struct EVSYS_struct +-{ +- register8_t CH0MUX; /* Event Channel 0 Multiplexer */ +- register8_t CH1MUX; /* Event Channel 1 Multiplexer */ +- register8_t CH2MUX; /* Event Channel 2 Multiplexer */ +- register8_t CH3MUX; /* Event Channel 3 Multiplexer */ +- register8_t reserved_0x04; +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t CH0CTRL; /* Channel 0 Control Register */ +- register8_t CH1CTRL; /* Channel 1 Control Register */ +- register8_t CH2CTRL; /* Channel 2 Control Register */ +- register8_t CH3CTRL; /* Channel 3 Control Register */ +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t STROBE; /* Event Strobe */ +- register8_t DATA; /* Event Data */ +-} EVSYS_t; +- +-/* Quadrature Decoder Index Recognition Mode */ +-typedef enum EVSYS_QDIRM_enum +-{ +- EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ +- EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ +- EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ +- EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +-} EVSYS_QDIRM_t; +- +-/* Digital filter coefficient */ +-typedef enum EVSYS_DIGFILT_enum +-{ +- EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ +- EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ +- EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ +- EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ +- EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ +- EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ +- EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ +- EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +-} EVSYS_DIGFILT_t; +- +-/* Event Channel multiplexer input selection */ +-typedef enum EVSYS_CHMUX_enum +-{ +- EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ +- EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ +- EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ +- EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ +- EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ +- EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ +- EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ +- EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ +- EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ +- EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ +- EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ +- EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ +- EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ +- EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ +- EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ +- EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ +- EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ +- EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ +- EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ +- EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ +- EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ +- EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ +- EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ +- EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ +- EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ +- EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ +- EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ +- EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ +- EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ +- EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ +- EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ +- EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ +- EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ +- EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ +- EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ +- EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ +- EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ +- EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ +- EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ +- EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ +- EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ +- EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ +- EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ +- EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ +- EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ +- EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ +- EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ +- EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ +- EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ +- EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ +- EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ +- EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ +- EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ +- EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ +- EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ +- EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ +- EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ +- EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ +- EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ +- EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ +- EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ +- EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ +- EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ +- EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ +- EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ +- EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ +- EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ +- EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ +- EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ +- EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ +- EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ +- EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ +- EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ +- EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ +- EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ +- EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ +- EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ +- EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ +- EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ +- EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ +- EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ +- EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ +- EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ +- EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ +- EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ +- EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ +- EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ +- EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ +- EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ +- EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ +- EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ +- EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ +- EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ +- EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ +- EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ +- EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ +- EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ +- EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ +- EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ +- EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ +- EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +- EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ +- EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ +- EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ +- EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +-} EVSYS_CHMUX_t; +- +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Non-volatile Memory Controller */ +-typedef struct NVM_struct +-{ +- register8_t ADDR0; /* Address Register 0 */ +- register8_t ADDR1; /* Address Register 1 */ +- register8_t ADDR2; /* Address Register 2 */ +- register8_t reserved_0x03; +- register8_t DATA0; /* Data Register 0 */ +- register8_t DATA1; /* Data Register 1 */ +- register8_t DATA2; /* Data Register 2 */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t CMD; /* Command */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t INTCTRL; /* Interrupt Control */ +- register8_t reserved_0x0E; +- register8_t STATUS; /* Status */ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Lock Bits */ +-typedef struct NVM_LOCKBITS_struct +-{ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_LOCKBITS_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Fuses */ +-typedef struct NVM_FUSES_struct +-{ +- register8_t FUSEBYTE0; /* User ID */ +- register8_t FUSEBYTE1; /* Watchdog Configuration */ +- register8_t FUSEBYTE2; /* Reset Configuration */ +- register8_t reserved_0x03; +- register8_t FUSEBYTE4; /* Start-up Configuration */ +- register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +-} NVM_FUSES_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Production Signatures */ +-typedef struct NVM_PROD_SIGNATURES_struct +-{ +- register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ +- register8_t reserved_0x01; +- register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ +- register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ +- register8_t reserved_0x04; +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ +- register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ +- register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ +- register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ +- register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ +- register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t WAFNUM; /* Wafer Number */ +- register8_t reserved_0x11; +- register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ +- register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ +- register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ +- register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ +- register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ +- register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ +- register8_t reserved_0x26; +- register8_t reserved_0x27; +- register8_t reserved_0x28; +- register8_t reserved_0x29; +- register8_t reserved_0x2A; +- register8_t reserved_0x2B; +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ +- register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ +- register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ +- register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ +- register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ +- register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- register8_t reserved_0x36; +- register8_t reserved_0x37; +- register8_t reserved_0x38; +- register8_t reserved_0x39; +- register8_t reserved_0x3A; +- register8_t reserved_0x3B; +- register8_t reserved_0x3C; +- register8_t reserved_0x3D; +- register8_t reserved_0x3E; +-} NVM_PROD_SIGNATURES_t; +- +-/* NVM Command */ +-typedef enum NVM_CMD_enum +-{ +- NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ +- NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ +- NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ +- NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ +- NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ +- NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ +- NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ +- NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ +- NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ +- NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ +- NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ +- NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ +- NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ +- NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ +- NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ +- NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ +- NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ +- NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ +- NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ +- NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ +- NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ +- NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ +- NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ +- NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ +- NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ +- NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +-} NVM_CMD_t; +- +-/* SPM ready interrupt level */ +-typedef enum NVM_SPMLVL_enum +-{ +- NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ +- NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ +- NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +-} NVM_SPMLVL_t; +- +-/* EEPROM ready interrupt level */ +-typedef enum NVM_EELVL_enum +-{ +- NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ +- NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ +- NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +-} NVM_EELVL_t; +- +-/* Boot lock bits - boot setcion */ +-typedef enum NVM_BLBB_enum +-{ +- NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +- NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ +- NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ +- NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +-} NVM_BLBB_t; +- +-/* Boot lock bits - application section */ +-typedef enum NVM_BLBA_enum +-{ +- NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +- NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ +- NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ +- NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +-} NVM_BLBA_t; +- +-/* Boot lock bits - application table section */ +-typedef enum NVM_BLBAT_enum +-{ +- NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +- NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ +- NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ +- NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +-} NVM_BLBAT_t; +- +-/* Lock bits */ +-typedef enum NVM_LB_enum +-{ +- NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +- NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ +- NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +-} NVM_LB_t; +- +-/* Boot Loader Section Reset Vector */ +-typedef enum BOOTRST_enum +-{ +- BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ +- BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +-} BOOTRST_t; +- +-/* BOD operation */ +-typedef enum BOD_enum +-{ +- BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ +- BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ +- BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +-} BOD_t; +- +-/* Watchdog (Window) Timeout Period */ +-typedef enum WD_enum +-{ +- WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ +- WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ +- WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ +- WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ +- WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ +- WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ +- WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ +- WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ +- WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ +- WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ +- WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +-} WD_t; +- +-/* Start-up Time */ +-typedef enum SUT_enum +-{ +- SUT_0MS_gc = (0x03<<2), /* 0 ms */ +- SUT_4MS_gc = (0x01<<2), /* 4 ms */ +- SUT_64MS_gc = (0x00<<2), /* 64 ms */ +-} SUT_t; +- +-/* Brown Out Detection Voltage Level */ +-typedef enum BODLVL_enum +-{ +- BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ +- BODLVL_1V9_gc = (0x06<<0), /* 1.9 V */ +- BODLVL_2V1_gc = (0x05<<0), /* 2.1 V */ +- BODLVL_2V4_gc = (0x04<<0), /* 2.4 V */ +- BODLVL_2V6_gc = (0x03<<0), /* 2.6 V */ +- BODLVL_2V9_gc = (0x02<<0), /* 2.9 V */ +- BODLVL_3V2_gc = (0x01<<0), /* 3.2 V */ +-} BODLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-AC - Analog Comparator +--------------------------------------------------------------------------- +-*/ +- +-/* Analog Comparator */ +-typedef struct AC_struct +-{ +- register8_t AC0CTRL; /* Comparator 0 Control */ +- register8_t AC1CTRL; /* Comparator 1 Control */ +- register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ +- register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t WINCTRL; /* Window Mode Control */ +- register8_t STATUS; /* Status */ +-} AC_t; +- +-/* Interrupt mode */ +-typedef enum AC_INTMODE_enum +-{ +- AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ +- AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ +- AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +-} AC_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum AC_INTLVL_enum +-{ +- AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ +- AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ +- AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ +- AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +-} AC_INTLVL_t; +- +-/* Hysteresis mode selection */ +-typedef enum AC_HYSMODE_enum +-{ +- AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ +- AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ +- AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +-} AC_HYSMODE_t; +- +-/* Positive input multiplexer selection */ +-typedef enum AC_MUXPOS_enum +-{ +- AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ +- AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ +- AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ +- AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ +- AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ +- AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ +- AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +- AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +-} AC_MUXPOS_t; +- +-/* Negative input multiplexer selection */ +-typedef enum AC_MUXNEG_enum +-{ +- AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ +- AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ +- AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ +- AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ +- AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ +- AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ +- AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ +- AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +-} AC_MUXNEG_t; +- +-/* Windows interrupt mode */ +-typedef enum AC_WINTMODE_enum +-{ +- AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ +- AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ +- AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ +- AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +-} AC_WINTMODE_t; +- +-/* Window interrupt level */ +-typedef enum AC_WINTLVL_enum +-{ +- AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ +- AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ +- AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +-} AC_WINTLVL_t; +- +-/* Window mode state */ +-typedef enum AC_WSTATE_enum +-{ +- AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ +- AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ +- AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +-} AC_WSTATE_t; +- +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* ADC Channel */ +-typedef struct ADC_CH_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t MUXCTRL; /* MUX Control */ +- register8_t INTCTRL; /* Channel Interrupt Control */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- _WORDREGISTER(RES); /* Channel Result */ +- register8_t reserved_0x6; +- register8_t reserved_0x7; +-} ADC_CH_t; +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Analog-to-Digital Converter */ +-typedef struct ADC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t REFCTRL; /* Reference Control */ +- register8_t EVCTRL; /* Event Control */ +- register8_t PRESCALER; /* Clock Prescaler */ +- register8_t reserved_0x05; +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- _WORDREGISTER(CAL); /* Calibration Value */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- _WORDREGISTER(CH0RES); /* Channel 0 Result */ +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- _WORDREGISTER(CMP); /* Compare Value */ +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- ADC_CH_t CH0; /* ADC Channel 0 */ +-} ADC_t; +- +-/* Positive input multiplexer selection */ +-typedef enum ADC_CH_MUXPOS_enum +-{ +- ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ +- ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ +- ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ +- ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ +- ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ +- ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ +- ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ +- ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +-} ADC_CH_MUXPOS_t; +- +-/* Internal input multiplexer selections */ +-typedef enum ADC_CH_MUXINT_enum +-{ +- ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ +- ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ +- ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +- ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +-} ADC_CH_MUXINT_t; +- +-/* Negative input multiplexer selection */ +-typedef enum ADC_CH_MUXNEG_enum +-{ +- ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ +- ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ +- ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ +- ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ +- ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ +- ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ +- ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ +- ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +-} ADC_CH_MUXNEG_t; +- +-/* Input mode */ +-typedef enum ADC_CH_INPUTMODE_enum +-{ +- ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ +- ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ +- ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ +- ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +-} ADC_CH_INPUTMODE_t; +- +-/* Gain factor */ +-typedef enum ADC_CH_GAIN_enum +-{ +- ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ +- ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ +- ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ +- ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ +- ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ +- ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ +- ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ +-} ADC_CH_GAIN_t; +- +-/* Conversion result resolution */ +-typedef enum ADC_RESOLUTION_enum +-{ +- ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ +- ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ +- ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +-} ADC_RESOLUTION_t; +- +-/* Voltage reference selection */ +-typedef enum ADC_REFSEL_enum +-{ +- ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ +- ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ +- ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ +- ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +-} ADC_REFSEL_t; +- +-/* Channel sweep selection */ +-typedef enum ADC_SWEEP_enum +-{ +- ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ +-} ADC_SWEEP_t; +- +-/* Event channel input selection */ +-typedef enum ADC_EVSEL_enum +-{ +- ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ +- ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ +- ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ +- ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ +- ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ +- ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ +- ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ +- ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +-} ADC_EVSEL_t; +- +-/* Event action selection */ +-typedef enum ADC_EVACT_enum +-{ +- ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ +- ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ +-} ADC_EVACT_t; +- +-/* Interupt mode */ +-typedef enum ADC_CH_INTMODE_enum +-{ +- ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ +- ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ +- ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +-} ADC_CH_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum ADC_CH_INTLVL_enum +-{ +- ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ +- ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ +- ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +-} ADC_CH_INTLVL_t; +- +-/* Clock prescaler */ +-typedef enum ADC_PRESCALER_enum +-{ +- ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ +- ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ +- ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ +- ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ +- ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ +- ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ +- ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ +- ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +-} ADC_PRESCALER_t; +- +- +-/* +--------------------------------------------------------------------------- +-RTC - Real-Time Clounter +--------------------------------------------------------------------------- +-*/ +- +-/* Real-Time Counter */ +-typedef struct RTC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t TEMP; /* Temporary register */ +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- _WORDREGISTER(CNT); /* Count Register */ +- _WORDREGISTER(PER); /* Period Register */ +- _WORDREGISTER(COMP); /* Compare Register */ +-} RTC_t; +- +-/* Prescaler Factor */ +-typedef enum RTC_PRESCALER_enum +-{ +- RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ +- RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ +- RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ +- RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ +- RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ +- RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ +- RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ +- RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +-} RTC_PRESCALER_t; +- +-/* Compare Interrupt level */ +-typedef enum RTC_COMPINTLVL_enum +-{ +- RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} RTC_COMPINTLVL_t; +- +-/* Overflow Interrupt level */ +-typedef enum RTC_OVFINTLVL_enum +-{ +- RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} RTC_OVFINTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* EBI Chip Select Module */ +-typedef struct EBI_CS_struct +-{ +- register8_t CTRLA; /* Chip Select Control Register A */ +- register8_t CTRLB; /* Chip Select Control Register B */ +- _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +-} EBI_CS_t; +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* External Bus Interface */ +-typedef struct EBI_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t SDRAMCTRLA; /* SDRAM Control Register A */ +- register8_t reserved_0x02; +- register8_t reserved_0x03; +- _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ +- _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ +- register8_t SDRAMCTRLB; /* SDRAM Control Register B */ +- register8_t SDRAMCTRLC; /* SDRAM Control Register C */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- EBI_CS_t CS0; /* Chip Select 0 */ +- EBI_CS_t CS1; /* Chip Select 1 */ +- EBI_CS_t CS2; /* Chip Select 2 */ +- EBI_CS_t CS3; /* Chip Select 3 */ +-} EBI_t; +- +-/* Chip Select adress space */ +-typedef enum EBI_CS_ASIZE_enum +-{ +- EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ +- EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ +- EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ +- EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ +- EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ +- EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ +- EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ +- EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ +- EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ +- EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ +- EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ +- EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ +- EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ +- EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ +- EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ +- EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ +- EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +-} EBI_CS_ASIZE_t; +- +-/* */ +-typedef enum EBI_CS_SRWS_enum +-{ +- EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_CS_SRWS_t; +- +-/* Chip Select address mode */ +-typedef enum EBI_CS_MODE_enum +-{ +- EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ +- EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ +- EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ +- EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +-} EBI_CS_MODE_t; +- +-/* Chip Select SDRAM mode */ +-typedef enum EBI_CS_SDMODE_enum +-{ +- EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ +- EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +-} EBI_CS_SDMODE_t; +- +-/* */ +-typedef enum EBI_SDDATAW_enum +-{ +- EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ +- EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +-} EBI_SDDATAW_t; +- +-/* */ +-typedef enum EBI_LPCMODE_enum +-{ +- EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ +- EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +-} EBI_LPCMODE_t; +- +-/* */ +-typedef enum EBI_SRMODE_enum +-{ +- EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ +- EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ +- EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ +- EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +-} EBI_SRMODE_t; +- +-/* */ +-typedef enum EBI_IFMODE_enum +-{ +- EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ +- EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ +- EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ +- EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +-} EBI_IFMODE_t; +- +-/* */ +-typedef enum EBI_SDCOL_enum +-{ +- EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ +- EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ +- EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ +- EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +-} EBI_SDCOL_t; +- +-/* */ +-typedef enum EBI_MRDLY_enum +-{ +- EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_MRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCYCDLY_enum +-{ +- EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ROWCYCDLY_t; +- +-/* */ +-typedef enum EBI_RPDLY_enum +-{ +- EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_RPDLY_t; +- +-/* */ +-typedef enum EBI_WRDLY_enum +-{ +- EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_WRDLY_t; +- +-/* */ +-typedef enum EBI_ESRDLY_enum +-{ +- EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ESRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCOLDLY_enum +-{ +- EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_ROWCOLDLY_t; +- +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_MASTER_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t STATUS; /* Status Register */ +- register8_t BAUD; /* Baurd Rate Control Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +-} TWI_MASTER_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_SLAVE_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t STATUS; /* Status Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +- register8_t ADDRMASK; /* Address Mask Register */ +-} TWI_SLAVE_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Two-Wire Interface */ +-typedef struct TWI_struct +-{ +- register8_t CTRL; /* TWI Common Control Register */ +- TWI_MASTER_t MASTER; /* TWI master module */ +- TWI_SLAVE_t SLAVE; /* TWI slave module */ +-} TWI_t; +- +-/* Master Interrupt Level */ +-typedef enum TWI_MASTER_INTLVL_enum +-{ +- TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_MASTER_INTLVL_t; +- +-/* Inactive Timeout */ +-typedef enum TWI_MASTER_TIMEOUT_enum +-{ +- TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ +- TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ +- TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ +- TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +-} TWI_MASTER_TIMEOUT_t; +- +-/* Master Command */ +-typedef enum TWI_MASTER_CMD_enum +-{ +- TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ +- TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ +- TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +-} TWI_MASTER_CMD_t; +- +-/* Master Bus State */ +-typedef enum TWI_MASTER_BUSSTATE_enum +-{ +- TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ +- TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ +- TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ +- TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +-} TWI_MASTER_BUSSTATE_t; +- +-/* Slave Interrupt Level */ +-typedef enum TWI_SLAVE_INTLVL_enum +-{ +- TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_SLAVE_INTLVL_t; +- +-/* Slave Command */ +-typedef enum TWI_SLAVE_CMD_enum +-{ +- TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ +- TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +-} TWI_SLAVE_CMD_t; +- +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O port Configuration */ +-typedef struct PORTCFG_struct +-{ +- register8_t MPCMASK; /* Multi-pin Configuration Mask */ +- register8_t reserved_0x01; +- register8_t VPCTRLA; /* Virtual Port Control Register A */ +- register8_t VPCTRLB; /* Virtual Port Control Register B */ +- register8_t CLKEVOUT; /* Clock and Event Out Register */ +-} PORTCFG_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* Virtual Port */ +-typedef struct VPORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t OUT; /* I/O Port Output */ +- register8_t IN; /* I/O Port Input */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +-} VPORT_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O Ports */ +-typedef struct PORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t DIRSET; /* I/O Port Data Direction Set */ +- register8_t DIRCLR; /* I/O Port Data Direction Clear */ +- register8_t DIRTGL; /* I/O Port Data Direction Toggle */ +- register8_t OUT; /* I/O Port Output */ +- register8_t OUTSET; /* I/O Port Output Set */ +- register8_t OUTCLR; /* I/O Port Output Clear */ +- register8_t OUTTGL; /* I/O Port Output Toggle */ +- register8_t IN; /* I/O port Input */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INT0MASK; /* Port Interrupt 0 Mask */ +- register8_t INT1MASK; /* Port Interrupt 1 Mask */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t PIN0CTRL; /* Pin 0 Control Register */ +- register8_t PIN1CTRL; /* Pin 1 Control Register */ +- register8_t PIN2CTRL; /* Pin 2 Control Register */ +- register8_t PIN3CTRL; /* Pin 3 Control Register */ +- register8_t PIN4CTRL; /* Pin 4 Control Register */ +- register8_t PIN5CTRL; /* Pin 5 Control Register */ +- register8_t PIN6CTRL; /* Pin 6 Control Register */ +- register8_t PIN7CTRL; /* Pin 7 Control Register */ +-} PORT_t; +- +-/* Virtual Port 0 Mapping */ +-typedef enum PORTCFG_VP0MAP_enum +-{ +- PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP0MAP_t; +- +-/* Virtual Port 1 Mapping */ +-typedef enum PORTCFG_VP1MAP_enum +-{ +- PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP1MAP_t; +- +-/* Virtual Port 2 Mapping */ +-typedef enum PORTCFG_VP2MAP_enum +-{ +- PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP2MAP_t; +- +-/* Virtual Port 3 Mapping */ +-typedef enum PORTCFG_VP3MAP_enum +-{ +- PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP3MAP_t; +- +-/* Clock Output Port */ +-typedef enum PORTCFG_CLKOUT_enum +-{ +- PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ +- PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ +- PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ +- PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +-} PORTCFG_CLKOUT_t; +- +-/* Event Output Port */ +-typedef enum PORTCFG_EVOUT_enum +-{ +- PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ +- PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ +- PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ +- PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +-} PORTCFG_EVOUT_t; +- +-/* Port Interrupt 0 Level */ +-typedef enum PORT_INT0LVL_enum +-{ +- PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ +- PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ +- PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +-} PORT_INT0LVL_t; +- +-/* Port Interrupt 1 Level */ +-typedef enum PORT_INT1LVL_enum +-{ +- PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ +- PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ +- PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +-} PORT_INT1LVL_t; +- +-/* Output/Pull Configuration */ +-typedef enum PORT_OPC_enum +-{ +- PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ +- PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ +- PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ +- PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ +- PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ +- PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ +- PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ +- PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +-} PORT_OPC_t; +- +-/* Input/Sense Configuration */ +-typedef enum PORT_ISC_enum +-{ +- PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ +- PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ +- PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ +- PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ +- PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +-} PORT_ISC_t; +- +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 0 */ +-typedef struct TC0_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- _WORDREGISTER(CCC); /* Compare or Capture C */ +- _WORDREGISTER(CCD); /* Compare or Capture D */ +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +- _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ +- _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +-} TC0_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 1 */ +-typedef struct TC1_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t reserved_0x2E; +- register8_t reserved_0x2F; +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +-} TC1_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* Advanced Waveform Extension */ +-typedef struct AWEX_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t FDEMASK; /* Fault Detection Event Mask */ +- register8_t FDCTRL; /* Fault Detection Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x05; +- register8_t DTBOTH; /* Dead Time Both Sides */ +- register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ +- register8_t DTLS; /* Dead Time Low Side */ +- register8_t DTHS; /* Dead Time High Side */ +- register8_t DTLSBUF; /* Dead Time Low Side Buffer */ +- register8_t DTHSBUF; /* Dead Time High Side Buffer */ +- register8_t OUTOVEN; /* Output Override Enable */ +-} AWEX_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* High-Resolution Extension */ +-typedef struct HIRES_struct +-{ +- register8_t CTRLA; /* Control Register */ +-} HIRES_t; +- +-/* Clock Selection */ +-typedef enum TC_CLKSEL_enum +-{ +- TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ +- TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ +- TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ +- TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ +- TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ +- TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ +- TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ +- TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ +- TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_CLKSEL_t; +- +-/* Waveform Generation Mode */ +-typedef enum TC_WGMODE_enum +-{ +- TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ +- TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ +- TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ +- TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ +- TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ +- TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +-} TC_WGMODE_t; +- +-/* Event Action */ +-typedef enum TC_EVACT_enum +-{ +- TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ +- TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ +- TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ +- TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ +- TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ +- TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ +- TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +-} TC_EVACT_t; +- +-/* Event Selection */ +-typedef enum TC_EVSEL_enum +-{ +- TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_EVSEL_t; +- +-/* Error Interrupt Level */ +-typedef enum TC_ERRINTLVL_enum +-{ +- TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_ERRINTLVL_t; +- +-/* Overflow Interrupt Level */ +-typedef enum TC_OVFINTLVL_enum +-{ +- TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_OVFINTLVL_t; +- +-/* Compare or Capture D Interrupt Level */ +-typedef enum TC_CCDINTLVL_enum +-{ +- TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TC_CCDINTLVL_t; +- +-/* Compare or Capture C Interrupt Level */ +-typedef enum TC_CCCINTLVL_enum +-{ +- TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} TC_CCCINTLVL_t; +- +-/* Compare or Capture B Interrupt Level */ +-typedef enum TC_CCBINTLVL_enum +-{ +- TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_CCBINTLVL_t; +- +-/* Compare or Capture A Interrupt Level */ +-typedef enum TC_CCAINTLVL_enum +-{ +- TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_CCAINTLVL_t; +- +-/* Timer/Counter Command */ +-typedef enum TC_CMD_enum +-{ +- TC_CMD_NONE_gc = (0x00<<2), /* No Command */ +- TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ +- TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ +- TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +-} TC_CMD_t; +- +-/* Fault Detect Action */ +-typedef enum AWEX_FDACT_enum +-{ +- AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ +- AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ +- AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +-} AWEX_FDACT_t; +- +-/* High Resolution Enable */ +-typedef enum HIRES_HREN_enum +-{ +- HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ +- HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ +- HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ +- HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +-} HIRES_HREN_t; +- +- +-/* +--------------------------------------------------------------------------- +-USART - Universal Asynchronous Receiver-Transmitter +--------------------------------------------------------------------------- +-*/ +- +-/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +-typedef struct USART_struct +-{ +- register8_t DATA; /* Data Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x02; +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t BAUDCTRLA; /* Baud Rate Control Register A */ +- register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +-} USART_t; +- +-/* Receive Complete Interrupt level */ +-typedef enum USART_RXCINTLVL_enum +-{ +- USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} USART_RXCINTLVL_t; +- +-/* Transmit Complete Interrupt level */ +-typedef enum USART_TXCINTLVL_enum +-{ +- USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} USART_TXCINTLVL_t; +- +-/* Data Register Empty Interrupt level */ +-typedef enum USART_DREINTLVL_enum +-{ +- USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} USART_DREINTLVL_t; +- +-/* Character Size */ +-typedef enum USART_CHSIZE_enum +-{ +- USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ +- USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ +- USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ +- USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ +- USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +-} USART_CHSIZE_t; +- +-/* Communication Mode */ +-typedef enum USART_CMODE_enum +-{ +- USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ +- USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ +- USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ +- USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +-} USART_CMODE_t; +- +-/* Parity Mode */ +-typedef enum USART_PMODE_enum +-{ +- USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ +- USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ +- USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +-} USART_PMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-SPI - Serial Peripheral Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Serial Peripheral Interface */ +-typedef struct SPI_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t DATA; /* Data Register */ +-} SPI_t; +- +-/* SPI Mode */ +-typedef enum SPI_MODE_enum +-{ +- SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ +- SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ +- SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ +- SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +-} SPI_MODE_t; +- +-/* Prescaler setting */ +-typedef enum SPI_PRESCALER_enum +-{ +- SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ +- SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ +- SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ +- SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +-} SPI_PRESCALER_t; +- +-/* Interrupt level */ +-typedef enum SPI_INTLVL_enum +-{ +- SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} SPI_INTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-IRCOM - IR Communication Module +--------------------------------------------------------------------------- +-*/ +- +-/* IR Communication Module */ +-typedef struct IRCOM_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ +- register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +-} IRCOM_t; +- +-/* Event channel selection */ +-typedef enum IRDA_EVSEL_enum +-{ +- IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ +- IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ +- IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ +- IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +- IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ +- IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ +- IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ +- IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +-} IRDA_EVSEL_t; +- +- +- +-/* +-========================================================================== +-IO Module Instances. Mapped to memory. +-========================================================================== +-*/ +- +-#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +-#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +-#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +-#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +-#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +-#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +-#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +-#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +-#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +-#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +-#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +-#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +-#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +-#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +-#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +-#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +-#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +-#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +-#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +-#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +-#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +-#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +-#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +-#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +-#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +-#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +-#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +-#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ +-#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +-#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +-#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +-#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +-#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +-#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +-#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +-#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +-#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +-#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +-#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +-#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +-#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ +-#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ +-#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ +-#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ +- +- +-#endif /* !defined (__ASSEMBLER__) */ +- +- +-/* ========== Flattened fully qualified IO register names ========== */ +- +-/* GPIO - General Purpose IO Registers */ +-#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +-#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +-#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +-#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +-#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +-#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +-#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +-#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +-#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +-#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +-#define GPIO_GPIORA _SFR_MEM8(0x000A) +-#define GPIO_GPIORB _SFR_MEM8(0x000B) +-#define GPIO_GPIORC _SFR_MEM8(0x000C) +-#define GPIO_GPIORD _SFR_MEM8(0x000D) +-#define GPIO_GPIORE _SFR_MEM8(0x000E) +-#define GPIO_GPIORF _SFR_MEM8(0x000F) +- +-/* VPORT0 - Virtual Port 0 */ +-#define VPORT0_DIR _SFR_MEM8(0x0010) +-#define VPORT0_OUT _SFR_MEM8(0x0011) +-#define VPORT0_IN _SFR_MEM8(0x0012) +-#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) +- +-/* VPORT1 - Virtual Port 1 */ +-#define VPORT1_DIR _SFR_MEM8(0x0014) +-#define VPORT1_OUT _SFR_MEM8(0x0015) +-#define VPORT1_IN _SFR_MEM8(0x0016) +-#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) +- +-/* VPORT2 - Virtual Port 2 */ +-#define VPORT2_DIR _SFR_MEM8(0x0018) +-#define VPORT2_OUT _SFR_MEM8(0x0019) +-#define VPORT2_IN _SFR_MEM8(0x001A) +-#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) +- +-/* VPORT3 - Virtual Port 3 */ +-#define VPORT3_DIR _SFR_MEM8(0x001C) +-#define VPORT3_OUT _SFR_MEM8(0x001D) +-#define VPORT3_IN _SFR_MEM8(0x001E) +-#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) +- +-/* OCD - On-Chip Debug System */ +-#define OCD_OCDR0 _SFR_MEM8(0x002E) +-#define OCD_OCDR1 _SFR_MEM8(0x002F) +- +-/* CPU - CPU Registers */ +-#define CPU_CCP _SFR_MEM8(0x0034) +-#define CPU_RAMPD _SFR_MEM8(0x0038) +-#define CPU_RAMPX _SFR_MEM8(0x0039) +-#define CPU_RAMPY _SFR_MEM8(0x003A) +-#define CPU_RAMPZ _SFR_MEM8(0x003B) +-#define CPU_EIND _SFR_MEM8(0x003C) +-#define CPU_SPL _SFR_MEM8(0x003D) +-#define CPU_SPH _SFR_MEM8(0x003E) +-#define CPU_SREG _SFR_MEM8(0x003F) +- +-/* CLK - Clock System */ +-#define CLK_CTRL _SFR_MEM8(0x0040) +-#define CLK_PSCTRL _SFR_MEM8(0x0041) +-#define CLK_LOCK _SFR_MEM8(0x0042) +-#define CLK_RTCCTRL _SFR_MEM8(0x0043) +- +-/* SLEEP - Sleep Controller */ +-#define SLEEP_CTRL _SFR_MEM8(0x0048) +- +-/* OSC - Oscillator Control */ +-#define OSC_CTRL _SFR_MEM8(0x0050) +-#define OSC_STATUS _SFR_MEM8(0x0051) +-#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +-#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +-#define OSC_RC32KCAL _SFR_MEM8(0x0054) +-#define OSC_PLLCTRL _SFR_MEM8(0x0055) +-#define OSC_DFLLCTRL _SFR_MEM8(0x0056) +- +-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +-#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +-#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +-#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +-#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +-#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +-#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) +- +-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +-#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +-#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +-#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +-#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +-#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +-#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) +- +-/* PR - Power Reduction */ +-#define PR_PRGEN _SFR_MEM8(0x0070) +-#define PR_PRPA _SFR_MEM8(0x0071) +-#define PR_PRPB _SFR_MEM8(0x0072) +-#define PR_PRPC _SFR_MEM8(0x0073) +-#define PR_PRPD _SFR_MEM8(0x0074) +-#define PR_PRPE _SFR_MEM8(0x0075) +-#define PR_PRPF _SFR_MEM8(0x0076) +- +-/* RST - Reset Controller */ +-#define RST_STATUS _SFR_MEM8(0x0078) +-#define RST_CTRL _SFR_MEM8(0x0079) +- +-/* WDT - Watch-Dog Timer */ +-#define WDT_CTRL _SFR_MEM8(0x0080) +-#define WDT_WINCTRL _SFR_MEM8(0x0081) +-#define WDT_STATUS _SFR_MEM8(0x0082) +- +-/* MCU - MCU Control */ +-#define MCU_DEVID0 _SFR_MEM8(0x0090) +-#define MCU_DEVID1 _SFR_MEM8(0x0091) +-#define MCU_DEVID2 _SFR_MEM8(0x0092) +-#define MCU_REVID _SFR_MEM8(0x0093) +-#define MCU_JTAGUID _SFR_MEM8(0x0094) +-#define MCU_MCUCR _SFR_MEM8(0x0096) +-#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +-#define MCU_AWEXLOCK _SFR_MEM8(0x0099) +- +-/* PMIC - Programmable Interrupt Controller */ +-#define PMIC_STATUS _SFR_MEM8(0x00A0) +-#define PMIC_INTPRI _SFR_MEM8(0x00A1) +-#define PMIC_CTRL _SFR_MEM8(0x00A2) +- +-/* PORTCFG - Port Configuration */ +-#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +-#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +-#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +-#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +- +-/* EVSYS - Event System */ +-#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +-#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +-#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +-#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +-#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +-#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +-#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +-#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +-#define EVSYS_STROBE _SFR_MEM8(0x0190) +-#define EVSYS_DATA _SFR_MEM8(0x0191) +- +-/* NVM - Non Volatile Memory Controller */ +-#define NVM_ADDR0 _SFR_MEM8(0x01C0) +-#define NVM_ADDR1 _SFR_MEM8(0x01C1) +-#define NVM_ADDR2 _SFR_MEM8(0x01C2) +-#define NVM_DATA0 _SFR_MEM8(0x01C4) +-#define NVM_DATA1 _SFR_MEM8(0x01C5) +-#define NVM_DATA2 _SFR_MEM8(0x01C6) +-#define NVM_CMD _SFR_MEM8(0x01CA) +-#define NVM_CTRLA _SFR_MEM8(0x01CB) +-#define NVM_CTRLB _SFR_MEM8(0x01CC) +-#define NVM_INTCTRL _SFR_MEM8(0x01CD) +-#define NVM_STATUS _SFR_MEM8(0x01CF) +-#define NVM_LOCKBITS _SFR_MEM8(0x01D0) +- +-/* ADCA - Analog to Digital Converter A */ +-#define ADCA_CTRLA _SFR_MEM8(0x0200) +-#define ADCA_CTRLB _SFR_MEM8(0x0201) +-#define ADCA_REFCTRL _SFR_MEM8(0x0202) +-#define ADCA_EVCTRL _SFR_MEM8(0x0203) +-#define ADCA_PRESCALER _SFR_MEM8(0x0204) +-#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +-#define ADCA_CAL _SFR_MEM16(0x020C) +-#define ADCA_CH0RES _SFR_MEM16(0x0210) +-#define ADCA_CMP _SFR_MEM16(0x0218) +-#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +-#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +-#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +-#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +-#define ADCA_CH0_RES _SFR_MEM16(0x0224) +- +-/* ACA - Analog Comparator A */ +-#define ACA_AC0CTRL _SFR_MEM8(0x0380) +-#define ACA_AC1CTRL _SFR_MEM8(0x0381) +-#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +-#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +-#define ACA_CTRLA _SFR_MEM8(0x0384) +-#define ACA_CTRLB _SFR_MEM8(0x0385) +-#define ACA_WINCTRL _SFR_MEM8(0x0386) +-#define ACA_STATUS _SFR_MEM8(0x0387) +- +-/* RTC - Real-Time Counter */ +-#define RTC_CTRL _SFR_MEM8(0x0400) +-#define RTC_STATUS _SFR_MEM8(0x0401) +-#define RTC_INTCTRL _SFR_MEM8(0x0402) +-#define RTC_INTFLAGS _SFR_MEM8(0x0403) +-#define RTC_TEMP _SFR_MEM8(0x0404) +-#define RTC_CNT _SFR_MEM16(0x0408) +-#define RTC_PER _SFR_MEM16(0x040A) +-#define RTC_COMP _SFR_MEM16(0x040C) +- +-/* TWIC - Two-Wire Interface C */ +-#define TWIC_CTRL _SFR_MEM8(0x0480) +-#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0482) +-#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0483) +-#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0484) +-#define TWIC_MASTER_STATUS _SFR_MEM8(0x0485) +-#define TWIC_MASTER_BAUD _SFR_MEM8(0x0486) +-#define TWIC_MASTER_ADDR _SFR_MEM8(0x0487) +-#define TWIC_MASTER_DATA _SFR_MEM8(0x0488) +-#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +-#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +-#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +-#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +-#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +-#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) +- +-/* PORTA - Port A */ +-#define PORTA_DIR _SFR_MEM8(0x0600) +-#define PORTA_DIRSET _SFR_MEM8(0x0601) +-#define PORTA_DIRCLR _SFR_MEM8(0x0602) +-#define PORTA_DIRTGL _SFR_MEM8(0x0603) +-#define PORTA_OUT _SFR_MEM8(0x0604) +-#define PORTA_OUTSET _SFR_MEM8(0x0605) +-#define PORTA_OUTCLR _SFR_MEM8(0x0606) +-#define PORTA_OUTTGL _SFR_MEM8(0x0607) +-#define PORTA_IN _SFR_MEM8(0x0608) +-#define PORTA_INTCTRL _SFR_MEM8(0x0609) +-#define PORTA_INT0MASK _SFR_MEM8(0x060A) +-#define PORTA_INT1MASK _SFR_MEM8(0x060B) +-#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +-#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +-#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +-#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +-#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +-#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +-#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +-#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +-#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) +- +-/* PORTB - Port B */ +-#define PORTB_DIR _SFR_MEM8(0x0620) +-#define PORTB_DIRSET _SFR_MEM8(0x0621) +-#define PORTB_DIRCLR _SFR_MEM8(0x0622) +-#define PORTB_DIRTGL _SFR_MEM8(0x0623) +-#define PORTB_OUT _SFR_MEM8(0x0624) +-#define PORTB_OUTSET _SFR_MEM8(0x0625) +-#define PORTB_OUTCLR _SFR_MEM8(0x0626) +-#define PORTB_OUTTGL _SFR_MEM8(0x0627) +-#define PORTB_IN _SFR_MEM8(0x0628) +-#define PORTB_INTCTRL _SFR_MEM8(0x0629) +-#define PORTB_INT0MASK _SFR_MEM8(0x062A) +-#define PORTB_INT1MASK _SFR_MEM8(0x062B) +-#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +-#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +-#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +-#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +-#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +-#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +-#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +-#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +-#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) +- +-/* PORTC - Port C */ +-#define PORTC_DIR _SFR_MEM8(0x0640) +-#define PORTC_DIRSET _SFR_MEM8(0x0641) +-#define PORTC_DIRCLR _SFR_MEM8(0x0642) +-#define PORTC_DIRTGL _SFR_MEM8(0x0643) +-#define PORTC_OUT _SFR_MEM8(0x0644) +-#define PORTC_OUTSET _SFR_MEM8(0x0645) +-#define PORTC_OUTCLR _SFR_MEM8(0x0646) +-#define PORTC_OUTTGL _SFR_MEM8(0x0647) +-#define PORTC_IN _SFR_MEM8(0x0648) +-#define PORTC_INTCTRL _SFR_MEM8(0x0649) +-#define PORTC_INT0MASK _SFR_MEM8(0x064A) +-#define PORTC_INT1MASK _SFR_MEM8(0x064B) +-#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +-#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +-#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +-#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +-#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +-#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +-#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +-#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +-#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) +- +-/* PORTD - Port D */ +-#define PORTD_DIR _SFR_MEM8(0x0660) +-#define PORTD_DIRSET _SFR_MEM8(0x0661) +-#define PORTD_DIRCLR _SFR_MEM8(0x0662) +-#define PORTD_DIRTGL _SFR_MEM8(0x0663) +-#define PORTD_OUT _SFR_MEM8(0x0664) +-#define PORTD_OUTSET _SFR_MEM8(0x0665) +-#define PORTD_OUTCLR _SFR_MEM8(0x0666) +-#define PORTD_OUTTGL _SFR_MEM8(0x0667) +-#define PORTD_IN _SFR_MEM8(0x0668) +-#define PORTD_INTCTRL _SFR_MEM8(0x0669) +-#define PORTD_INT0MASK _SFR_MEM8(0x066A) +-#define PORTD_INT1MASK _SFR_MEM8(0x066B) +-#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +-#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +-#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +-#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +-#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +-#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +-#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +-#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +-#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) +- +-/* PORTE - Port E */ +-#define PORTE_DIR _SFR_MEM8(0x0680) +-#define PORTE_DIRSET _SFR_MEM8(0x0681) +-#define PORTE_DIRCLR _SFR_MEM8(0x0682) +-#define PORTE_DIRTGL _SFR_MEM8(0x0683) +-#define PORTE_OUT _SFR_MEM8(0x0684) +-#define PORTE_OUTSET _SFR_MEM8(0x0685) +-#define PORTE_OUTCLR _SFR_MEM8(0x0686) +-#define PORTE_OUTTGL _SFR_MEM8(0x0687) +-#define PORTE_IN _SFR_MEM8(0x0688) +-#define PORTE_INTCTRL _SFR_MEM8(0x0689) +-#define PORTE_INT0MASK _SFR_MEM8(0x068A) +-#define PORTE_INT1MASK _SFR_MEM8(0x068B) +-#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +-#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +-#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +-#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +-#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +-#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +-#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +-#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +-#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) +- +-/* PORTF - Port F */ +-#define PORTF_DIR _SFR_MEM8(0x06A0) +-#define PORTF_DIRSET _SFR_MEM8(0x06A1) +-#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +-#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +-#define PORTF_OUT _SFR_MEM8(0x06A4) +-#define PORTF_OUTSET _SFR_MEM8(0x06A5) +-#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +-#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +-#define PORTF_IN _SFR_MEM8(0x06A8) +-#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +-#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +-#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +-#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +-#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +-#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +-#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +-#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +-#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +-#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +-#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +-#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) +- +-/* PORTR - Port R */ +-#define PORTR_DIR _SFR_MEM8(0x07E0) +-#define PORTR_DIRSET _SFR_MEM8(0x07E1) +-#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +-#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +-#define PORTR_OUT _SFR_MEM8(0x07E4) +-#define PORTR_OUTSET _SFR_MEM8(0x07E5) +-#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +-#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +-#define PORTR_IN _SFR_MEM8(0x07E8) +-#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +-#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +-#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +-#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +-#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +-#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +-#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +-#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +-#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +-#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +-#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +-#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) +- +-/* TCC0 - Timer/Counter C0 */ +-#define TCC0_CTRLA _SFR_MEM8(0x0800) +-#define TCC0_CTRLB _SFR_MEM8(0x0801) +-#define TCC0_CTRLC _SFR_MEM8(0x0802) +-#define TCC0_CTRLD _SFR_MEM8(0x0803) +-#define TCC0_CTRLE _SFR_MEM8(0x0804) +-#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +-#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +-#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +-#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +-#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +-#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +-#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +-#define TCC0_TEMP _SFR_MEM8(0x080F) +-#define TCC0_CNT _SFR_MEM16(0x0820) +-#define TCC0_PER _SFR_MEM16(0x0826) +-#define TCC0_CCA _SFR_MEM16(0x0828) +-#define TCC0_CCB _SFR_MEM16(0x082A) +-#define TCC0_CCC _SFR_MEM16(0x082C) +-#define TCC0_CCD _SFR_MEM16(0x082E) +-#define TCC0_PERBUF _SFR_MEM16(0x0836) +-#define TCC0_CCABUF _SFR_MEM16(0x0838) +-#define TCC0_CCBBUF _SFR_MEM16(0x083A) +-#define TCC0_CCCBUF _SFR_MEM16(0x083C) +-#define TCC0_CCDBUF _SFR_MEM16(0x083E) +- +-/* TCC1 - Timer/Counter C1 */ +-#define TCC1_CTRLA _SFR_MEM8(0x0840) +-#define TCC1_CTRLB _SFR_MEM8(0x0841) +-#define TCC1_CTRLC _SFR_MEM8(0x0842) +-#define TCC1_CTRLD _SFR_MEM8(0x0843) +-#define TCC1_CTRLE _SFR_MEM8(0x0844) +-#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +-#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +-#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +-#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +-#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +-#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +-#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +-#define TCC1_TEMP _SFR_MEM8(0x084F) +-#define TCC1_CNT _SFR_MEM16(0x0860) +-#define TCC1_PER _SFR_MEM16(0x0866) +-#define TCC1_CCA _SFR_MEM16(0x0868) +-#define TCC1_CCB _SFR_MEM16(0x086A) +-#define TCC1_PERBUF _SFR_MEM16(0x0876) +-#define TCC1_CCABUF _SFR_MEM16(0x0878) +-#define TCC1_CCBBUF _SFR_MEM16(0x087A) +- +-/* AWEXC - Advanced Waveform Extension C */ +-#define AWEXC_CTRL _SFR_MEM8(0x0880) +-#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +-#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +-#define AWEXC_STATUS _SFR_MEM8(0x0884) +-#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +-#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +-#define AWEXC_DTLS _SFR_MEM8(0x0888) +-#define AWEXC_DTHS _SFR_MEM8(0x0889) +-#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +-#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +-#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) +- +-/* HIRESC - High-Resolution Extension C */ +-#define HIRESC_CTRLA _SFR_MEM8(0x0890) +- +-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +-#define USARTC0_DATA _SFR_MEM8(0x08A0) +-#define USARTC0_STATUS _SFR_MEM8(0x08A1) +-#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +-#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +-#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +-#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +-#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) +- +-/* SPIC - Serial Peripheral Interface C */ +-#define SPIC_CTRL _SFR_MEM8(0x08C0) +-#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +-#define SPIC_STATUS _SFR_MEM8(0x08C2) +-#define SPIC_DATA _SFR_MEM8(0x08C3) +- +-/* IRCOM - IR Communication Module */ +-#define IRCOM_CTRL _SFR_MEM8(0x08F8) +-#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +-#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) +- +-/* TCD0 - Timer/Counter D0 */ +-#define TCD0_CTRLA _SFR_MEM8(0x0900) +-#define TCD0_CTRLB _SFR_MEM8(0x0901) +-#define TCD0_CTRLC _SFR_MEM8(0x0902) +-#define TCD0_CTRLD _SFR_MEM8(0x0903) +-#define TCD0_CTRLE _SFR_MEM8(0x0904) +-#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +-#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +-#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +-#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +-#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +-#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +-#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +-#define TCD0_TEMP _SFR_MEM8(0x090F) +-#define TCD0_CNT _SFR_MEM16(0x0920) +-#define TCD0_PER _SFR_MEM16(0x0926) +-#define TCD0_CCA _SFR_MEM16(0x0928) +-#define TCD0_CCB _SFR_MEM16(0x092A) +-#define TCD0_CCC _SFR_MEM16(0x092C) +-#define TCD0_CCD _SFR_MEM16(0x092E) +-#define TCD0_PERBUF _SFR_MEM16(0x0936) +-#define TCD0_CCABUF _SFR_MEM16(0x0938) +-#define TCD0_CCBBUF _SFR_MEM16(0x093A) +-#define TCD0_CCCBUF _SFR_MEM16(0x093C) +-#define TCD0_CCDBUF _SFR_MEM16(0x093E) +- +-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +-#define USARTD0_DATA _SFR_MEM8(0x09A0) +-#define USARTD0_STATUS _SFR_MEM8(0x09A1) +-#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +-#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +-#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +-#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +-#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) +- +-/* SPID - Serial Peripheral Interface D */ +-#define SPID_CTRL _SFR_MEM8(0x09C0) +-#define SPID_INTCTRL _SFR_MEM8(0x09C1) +-#define SPID_STATUS _SFR_MEM8(0x09C2) +-#define SPID_DATA _SFR_MEM8(0x09C3) +- +-/* TCE0 - Timer/Counter E0 */ +-#define TCE0_CTRLA _SFR_MEM8(0x0A00) +-#define TCE0_CTRLB _SFR_MEM8(0x0A01) +-#define TCE0_CTRLC _SFR_MEM8(0x0A02) +-#define TCE0_CTRLD _SFR_MEM8(0x0A03) +-#define TCE0_CTRLE _SFR_MEM8(0x0A04) +-#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +-#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +-#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +-#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +-#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +-#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +-#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +-#define TCE0_TEMP _SFR_MEM8(0x0A0F) +-#define TCE0_CNT _SFR_MEM16(0x0A20) +-#define TCE0_PER _SFR_MEM16(0x0A26) +-#define TCE0_CCA _SFR_MEM16(0x0A28) +-#define TCE0_CCB _SFR_MEM16(0x0A2A) +-#define TCE0_CCC _SFR_MEM16(0x0A2C) +-#define TCE0_CCD _SFR_MEM16(0x0A2E) +-#define TCE0_PERBUF _SFR_MEM16(0x0A36) +-#define TCE0_CCABUF _SFR_MEM16(0x0A38) +-#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +-#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +-#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) +- +-/* AWEXE - Advanced Waveform Extension E */ +-#define AWEXE_CTRL _SFR_MEM8(0x0A80) +-#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +-#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +-#define AWEXE_STATUS _SFR_MEM8(0x0A84) +-#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +-#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +-#define AWEXE_DTLS _SFR_MEM8(0x0A88) +-#define AWEXE_DTHS _SFR_MEM8(0x0A89) +-#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +-#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +-#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) +- +-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +-#define USARTE0_DATA _SFR_MEM8(0x0AA0) +-#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +-#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +-#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +-#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +-#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +-#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) +- +-/* SPIE - Serial Peripheral Interface E */ +-#define SPIE_CTRL _SFR_MEM8(0x0AC0) +-#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +-#define SPIE_STATUS _SFR_MEM8(0x0AC2) +-#define SPIE_DATA _SFR_MEM8(0x0AC3) +- +-/* TCF0 - Timer/Counter F0 */ +-#define TCF0_CTRLA _SFR_MEM8(0x0B00) +-#define TCF0_CTRLB _SFR_MEM8(0x0B01) +-#define TCF0_CTRLC _SFR_MEM8(0x0B02) +-#define TCF0_CTRLD _SFR_MEM8(0x0B03) +-#define TCF0_CTRLE _SFR_MEM8(0x0B04) +-#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +-#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +-#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +-#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +-#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +-#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +-#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +-#define TCF0_TEMP _SFR_MEM8(0x0B0F) +-#define TCF0_CNT _SFR_MEM16(0x0B20) +-#define TCF0_PER _SFR_MEM16(0x0B26) +-#define TCF0_CCA _SFR_MEM16(0x0B28) +-#define TCF0_CCB _SFR_MEM16(0x0B2A) +-#define TCF0_CCC _SFR_MEM16(0x0B2C) +-#define TCF0_CCD _SFR_MEM16(0x0B2E) +-#define TCF0_PERBUF _SFR_MEM16(0x0B36) +-#define TCF0_CCABUF _SFR_MEM16(0x0B38) +-#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +-#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +-#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) +- +- +- +-/*================== Bitfield Definitions ================== */ +- +-/* XOCD - On-Chip Debug System */ +-/* OCD.OCDR1 bit masks and bit positions */ +-#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +-#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ +- +- +-/* CPU - CPU */ +-/* CPU.CCP bit masks and bit positions */ +-#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +-#define CPU_CCP_gp 0 /* CCP signature group position. */ +-#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +-#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +-#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +-#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +-#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +-#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +-#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +-#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +-#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +-#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +-#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +-#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +-#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +-#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +-#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +-#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ +- +- +-/* CPU.SREG bit masks and bit positions */ +-#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +-#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ +- +-#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +-#define CPU_T_bp 6 /* Transfer Bit bit position. */ +- +-#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +-#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +- +-#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +-#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +- +-#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +-#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +- +-#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +-#define CPU_N_bp 2 /* Negative Flag bit position. */ +- +-#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +-#define CPU_Z_bp 1 /* Zero Flag bit position. */ +- +-#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +-#define CPU_C_bp 0 /* Carry Flag bit position. */ +- +- +-/* CLK - Clock System */ +-/* CLK.CTRL bit masks and bit positions */ +-#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +-#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +-#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +-#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +-#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +-#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +-#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +-#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ +- +- +-/* CLK.PSCTRL bit masks and bit positions */ +-#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +-#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +-#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +-#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +-#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +-#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +-#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +-#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +-#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +-#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +-#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +-#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ +- +-#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +-#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +-#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +-#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +-#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +-#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ +- +- +-/* CLK.LOCK bit masks and bit positions */ +-#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +-#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ +- +- +-/* CLK.RTCCTRL bit masks and bit positions */ +-#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +-#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +-#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +-#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +-#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +-#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +-#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +-#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ +- +-#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +-#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ +- +- +-/* PR.PRGEN bit masks and bit positions */ +-#define PR_AES_bm 0x10 /* AES bit mask. */ +-#define PR_AES_bp 4 /* AES bit position. */ +- +-#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +-#define PR_EBI_bp 3 /* External Bus Interface bit position. */ +- +-#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +-#define PR_RTC_bp 2 /* Real-time Counter bit position. */ +- +-#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +-#define PR_EVSYS_bp 1 /* Event System bit position. */ +- +-#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +-#define PR_DMA_bp 0 /* DMA-Controller bit position. */ +- +- +-/* PR.PRPA bit masks and bit positions */ +-#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +-#define PR_DAC_bp 2 /* Port A DAC bit position. */ +- +-#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +-#define PR_ADC_bp 1 /* Port A ADC bit position. */ +- +-#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +-#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ +- +- +-/* PR.PRPB bit masks and bit positions */ +-/* PR_DAC_bm Predefined. */ +-/* PR_DAC_bp Predefined. */ +- +-/* PR_ADC_bm Predefined. */ +-/* PR_ADC_bp Predefined. */ +- +-/* PR_AC_bm Predefined. */ +-/* PR_AC_bp Predefined. */ +- +- +-/* PR.PRPC bit masks and bit positions */ +-#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +-#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ +- +-#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +-#define PR_USART1_bp 5 /* Port C USART1 bit position. */ +- +-#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +-#define PR_USART0_bp 4 /* Port C USART0 bit position. */ +- +-#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +-#define PR_SPI_bp 3 /* Port C SPI bit position. */ +- +-#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +-#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ +- +-#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +-#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ +- +-#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +-#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ +- +- +-/* PR.PRPD bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* PR.PRPE bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* PR.PRPF bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* SLEEP - Sleep Controller */ +-/* SLEEP.CTRL bit masks and bit positions */ +-#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +-#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +-#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +-#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +-#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +-#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +-#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +-#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ +- +-#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +-#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ +- +- +-/* OSC - Oscillator */ +-/* OSC.CTRL bit masks and bit positions */ +-#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +-#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ +- +-#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +-#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ +- +-#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ +- +- +-/* OSC.STATUS bit masks and bit positions */ +-#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +-#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ +- +-#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +-#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ +- +-#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ +- +- +-/* OSC.XOSCCTRL bit masks and bit positions */ +-#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +-#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +-#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +-#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +-#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +-#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ +- +-#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +-#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ +- +-#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +-#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +-#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +-#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +-#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +-#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +-#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +-#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +-#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +-#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +- +- +-/* OSC.XOSCFAIL bit masks and bit positions */ +-#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +-#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ +- +-#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +-#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ +- +- +-/* OSC.PLLCTRL bit masks and bit positions */ +-#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +-#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +-#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +-#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +-#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +-#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ +- +-#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +-#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +-#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +-#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +-#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +-#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +-#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +-#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +-#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +-#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +-#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +-#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ +- +- +-/* OSC.DFLLCTRL bit masks and bit positions */ +-#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +-#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ +- +-#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +-#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ +- +- +-/* DFLL - DFLL */ +-/* DFLL.CTRL bit masks and bit positions */ +-#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +-#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ +- +- +-/* DFLL.CALA bit masks and bit positions */ +-#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +-#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +-#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +-#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +-#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +-#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +-#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +-#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +-#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +-#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +-#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +-#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +-#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +-#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +-#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +-#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ +- +- +-/* DFLL.CALB bit masks and bit positions */ +-#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +-#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +-#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +-#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +-#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +-#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +-#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +-#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +-#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +-#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +-#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +-#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +-#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +-#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ +- +- +-/* RST - Reset */ +-/* RST.STATUS bit masks and bit positions */ +-#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +-#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ +- +-#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +-#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ +- +-#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +-#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ +- +-#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +-#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ +- +-#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +-#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ +- +-#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +-#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ +- +-#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +-#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ +- +- +-/* RST.CTRL bit masks and bit positions */ +-#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +-#define RST_SWRST_bp 0 /* Software Reset bit position. */ +- +- +-/* WDT - Watch-Dog Timer */ +-/* WDT.CTRL bit masks and bit positions */ +-#define WDT_PER_gm 0x3C /* Period group mask. */ +-#define WDT_PER_gp 2 /* Period group position. */ +-#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +-#define WDT_PER0_bp 2 /* Period bit 0 position. */ +-#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +-#define WDT_PER1_bp 3 /* Period bit 1 position. */ +-#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +-#define WDT_PER2_bp 4 /* Period bit 2 position. */ +-#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +-#define WDT_PER3_bp 5 /* Period bit 3 position. */ +- +-#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +-#define WDT_ENABLE_bp 1 /* Enable bit position. */ +- +-#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +-#define WDT_CEN_bp 0 /* Change Enable bit position. */ +- +- +-/* WDT.WINCTRL bit masks and bit positions */ +-#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +-#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +-#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +-#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +-#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +-#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +-#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +-#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +-#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +-#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ +- +-#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +-#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ +- +-#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +-#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ +- +- +-/* WDT.STATUS bit masks and bit positions */ +-#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +-#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +- +- +-/* MCU - MCU Control */ +-/* MCU.MCUCR bit masks and bit positions */ +-#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +-#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ +- +- +-/* MCU.EVSYSLOCK bit masks and bit positions */ +-#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +-#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ +- +-#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +-#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ +- +- +-/* MCU.AWEXLOCK bit masks and bit positions */ +-#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +-#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ +- +-#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +-#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ +- +- +-/* PMIC - Programmable Multi-level Interrupt Controller */ +-/* PMIC.STATUS bit masks and bit positions */ +-#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +-#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ +- +-#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +-#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ +- +-#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +-#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ +- +-#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +-#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ +- +- +-/* PMIC.CTRL bit masks and bit positions */ +-#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +-#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ +- +-#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +-#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ +- +-#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +-#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ +- +-#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +-#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ +- +-#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +-#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ +- +- +-/* EVSYS - Event System */ +-/* EVSYS.CH0MUX bit masks and bit positions */ +-#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +-#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +-#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +-#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +-#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +-#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +-#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +-#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +-#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +-#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +-#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +-#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +-#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +-#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +-#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +-#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +-#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +-#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ +- +- +-/* EVSYS.CH1MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH2MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH3MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH0CTRL bit masks and bit positions */ +-#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +-#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +-#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +-#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +-#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +-#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ +- +-#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +-#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ +- +-#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +-#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ +- +-#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +-#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +-#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +-#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +-#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +-#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +-#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +-#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ +- +- +-/* EVSYS.CH1CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH2CTRL bit masks and bit positions */ +-/* EVSYS_QDIRM_gm Predefined. */ +-/* EVSYS_QDIRM_gp Predefined. */ +-/* EVSYS_QDIRM0_bm Predefined. */ +-/* EVSYS_QDIRM0_bp Predefined. */ +-/* EVSYS_QDIRM1_bm Predefined. */ +-/* EVSYS_QDIRM1_bp Predefined. */ +- +-/* EVSYS_QDIEN_bm Predefined. */ +-/* EVSYS_QDIEN_bp Predefined. */ +- +-/* EVSYS_QDEN_bm Predefined. */ +-/* EVSYS_QDEN_bp Predefined. */ +- +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH3CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* NVM - Non Volatile Memory Controller */ +-/* NVM.CMD bit masks and bit positions */ +-#define NVM_CMD_gm 0xFF /* Command group mask. */ +-#define NVM_CMD_gp 0 /* Command group position. */ +-#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +-#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +-#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +-#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +-#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +-#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +-#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +-#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +-#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +-#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +-#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +-#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +-#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +-#define NVM_CMD7_bp 7 /* Command bit 7 position. */ +- +- +-/* NVM.CTRLA bit masks and bit positions */ +-#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +-#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ +- +- +-/* NVM.CTRLB bit masks and bit positions */ +-#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +-#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ +- +-#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +-#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ +- +-#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +-#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ +- +-#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +-#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ +- +- +-/* NVM.INTCTRL bit masks and bit positions */ +-#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +-#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +-#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +-#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +-#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +-#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ +- +-#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +-#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +-#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +-#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +-#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +-#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ +- +- +-/* NVM.STATUS bit masks and bit positions */ +-#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +-#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ +- +-#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +-#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ +- +-#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +-#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ +- +-#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +-#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ +- +- +-/* NVM.LOCKBITS bit masks and bit positions */ +-#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +-#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +-#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ +-#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ +-#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ +-#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ +-#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ +-#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ +-#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ +-#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ +-#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ +-#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ +-#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ +-#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ +-#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ +-#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ +-#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ +-#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ +-#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ +-#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +-#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +-#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +-#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ +- +-#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +-#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +-#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +-#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +-#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ +- +-#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +-#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ +- +-#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +-#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +-#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +-#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +-#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +-#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +-#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +-#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +-#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +-#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +-#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +-#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ +- +-#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +-#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ +- +- +-/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +-#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +-#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +-#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +-#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +-#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +-#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ +- +-#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +-#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ +- +-#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +-#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +-#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +-#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +-#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +-#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +-#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +-#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +- +- +-/* AC - Analog Comparator */ +-/* AC.AC0CTRL bit masks and bit positions */ +-#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +-#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +-#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +-#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +-#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +-#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ +- +-#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +-#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +-#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +-#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +-#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +-#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ +- +-#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +-#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ +- +-#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +-#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +-#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +-#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +-#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +-#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +- +-#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define AC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* AC.AC1CTRL bit masks and bit positions */ +-/* AC_INTMODE_gm Predefined. */ +-/* AC_INTMODE_gp Predefined. */ +-/* AC_INTMODE0_bm Predefined. */ +-/* AC_INTMODE0_bp Predefined. */ +-/* AC_INTMODE1_bm Predefined. */ +-/* AC_INTMODE1_bp Predefined. */ +- +-/* AC_INTLVL_gm Predefined. */ +-/* AC_INTLVL_gp Predefined. */ +-/* AC_INTLVL0_bm Predefined. */ +-/* AC_INTLVL0_bp Predefined. */ +-/* AC_INTLVL1_bm Predefined. */ +-/* AC_INTLVL1_bp Predefined. */ +- +-/* AC_HSMODE_bm Predefined. */ +-/* AC_HSMODE_bp Predefined. */ +- +-/* AC_HYSMODE_gm Predefined. */ +-/* AC_HYSMODE_gp Predefined. */ +-/* AC_HYSMODE0_bm Predefined. */ +-/* AC_HYSMODE0_bp Predefined. */ +-/* AC_HYSMODE1_bm Predefined. */ +-/* AC_HYSMODE1_bp Predefined. */ +- +-/* AC_ENABLE_bm Predefined. */ +-/* AC_ENABLE_bp Predefined. */ +- +- +-/* AC.AC0MUXCTRL bit masks and bit positions */ +-#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +-#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +-#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +-#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +-#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +-#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +-#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +-#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ +- +-#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +-#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +-#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +-#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +-#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +-#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +-#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +-#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ +- +- +-/* AC.AC1MUXCTRL bit masks and bit positions */ +-/* AC_MUXPOS_gm Predefined. */ +-/* AC_MUXPOS_gp Predefined. */ +-/* AC_MUXPOS0_bm Predefined. */ +-/* AC_MUXPOS0_bp Predefined. */ +-/* AC_MUXPOS1_bm Predefined. */ +-/* AC_MUXPOS1_bp Predefined. */ +-/* AC_MUXPOS2_bm Predefined. */ +-/* AC_MUXPOS2_bp Predefined. */ +- +-/* AC_MUXNEG_gm Predefined. */ +-/* AC_MUXNEG_gp Predefined. */ +-/* AC_MUXNEG0_bm Predefined. */ +-/* AC_MUXNEG0_bp Predefined. */ +-/* AC_MUXNEG1_bm Predefined. */ +-/* AC_MUXNEG1_bp Predefined. */ +-/* AC_MUXNEG2_bm Predefined. */ +-/* AC_MUXNEG2_bp Predefined. */ +- +- +-/* AC.CTRLA bit masks and bit positions */ +-#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +-#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ +- +- +-/* AC.CTRLB bit masks and bit positions */ +-#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +-#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +-#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +-#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +-#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +-#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +-#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +-#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +-#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +-#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +-#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +-#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +-#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +-#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ +- +- +-/* AC.WINCTRL bit masks and bit positions */ +-#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +-#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ +- +-#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +-#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +-#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +-#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +-#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +-#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ +- +-#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +-#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +-#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +-#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +-#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +-#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ +- +- +-/* AC.STATUS bit masks and bit positions */ +-#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +-#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +-#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +-#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +-#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +-#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ +- +-#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +-#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ +- +-#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +-#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ +- +-#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +-#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ +- +-#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +-#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ +- +-#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +-#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ +- +- +-/* ADC - Analog/Digital Converter */ +-/* ADC_CH.CTRL bit masks and bit positions */ +-#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +-#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ +- +-#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +-#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +-#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +-#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +-#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +-#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +-#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +-#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ +- +-#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +-#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +-#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +-#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +-#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +-#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ +- +- +-/* ADC_CH.MUXCTRL bit masks and bit positions */ +-#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +-#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +-#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +-#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +-#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +-#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +-#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +-#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +-#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +-#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ +- +-#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +-#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +-#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +-#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +-#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +-#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +-#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +-#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +-#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +-#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ +- +-#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +-#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +-#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +-#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +-#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +-#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ +- +- +-/* ADC_CH.INTCTRL bit masks and bit positions */ +-#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +-#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +-#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +-#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +-#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +-#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ +- +-#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +-#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +-#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +-#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +-#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +-#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ +- +- +-/* ADC_CH.INTFLAGS bit masks and bit positions */ +-#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +-#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ +- +- +-/* ADC.CTRLA bit masks and bit positions */ +-#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +-#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ +- +-#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +-#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ +- +-#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +-#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ +- +- +-/* ADC.CTRLB bit masks and bit positions */ +-#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +-#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ +- +-#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +-#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ +- +-#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +-#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +-#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +-#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +-#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +-#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ +- +- +-/* ADC.REFCTRL bit masks and bit positions */ +-#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +-#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +-#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +-#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +-#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +-#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +- +-#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +-#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ +- +-#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +-#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ +- +- +-/* ADC.EVCTRL bit masks and bit positions */ +-#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +-#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +-#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +-#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +-#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +-#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ +- +-#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +-#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +-#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +-#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +-#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +-#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +-#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +-#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ +- +-#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +-#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +-#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +-#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +-#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +-#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +-#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +-#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ +- +- +-/* ADC.PRESCALER bit masks and bit positions */ +-#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +-#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +-#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +-#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +-#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +-#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +-#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +-#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ +- +- +-/* ADC.INTFLAGS bit masks and bit positions */ +-#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +-#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ +- +- +-/* RTC - Real-Time Clounter */ +-/* RTC.CTRL bit masks and bit positions */ +-#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +-#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +-#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +-#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +-#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +-#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +-#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +-#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ +- +- +-/* RTC.STATUS bit masks and bit positions */ +-#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +-#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ +- +- +-/* RTC.INTCTRL bit masks and bit positions */ +-#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +-#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +-#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +-#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +-#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +-#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ +- +-#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +-#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +-#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +-#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +-#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +-#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ +- +- +-/* RTC.INTFLAGS bit masks and bit positions */ +-#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +-#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ +- +-#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* EBI - External Bus Interface */ +-/* EBI_CS.CTRLA bit masks and bit positions */ +-#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +-#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +-#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +-#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +-#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +-#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +-#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +-#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +-#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +-#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +-#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +-#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ +- +-#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +-#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +-#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +-#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +-#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +-#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ +- +- +-/* EBI_CS.CTRLB bit masks and bit positions */ +-#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +-#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +-#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +-#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +-#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +-#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +-#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +-#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ +- +-#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +-#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ +- +-#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +-#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ +- +-#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +-#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +-#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +-#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +-#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +-#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ +- +- +-/* EBI.CTRL bit masks and bit positions */ +-#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +-#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +-#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +-#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +-#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +-#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ +- +-#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +-#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +-#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +-#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +-#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +-#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ +- +-#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +-#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +-#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +-#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +-#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +-#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ +- +-#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +-#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +-#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +-#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +-#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +-#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLA bit masks and bit positions */ +-#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +-#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ +- +-#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +-#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ +- +-#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +-#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +-#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +-#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +-#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +-#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLB bit masks and bit positions */ +-#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +-#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +-#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +-#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +-#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +-#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ +- +-#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +-#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +-#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +-#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +-#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +-#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +-#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +-#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ +- +-#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +-#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +-#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +-#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +-#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +-#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +-#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +-#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ +- +- +-/* EBI.SDRAMCTRLC bit masks and bit positions */ +-#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +-#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +-#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +-#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +-#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +-#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ +- +-#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +-#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +-#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +-#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +-#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +-#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +-#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +-#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ +- +-#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +-#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +-#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +-#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +-#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +-#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +-#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +-#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ +- +- +-/* TWI - Two-Wire Interface */ +-/* TWI_MASTER.CTRLA bit masks and bit positions */ +-#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +-#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ +- +-#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +-#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ +- +-#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +-#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ +- +- +-/* TWI_MASTER.CTRLB bit masks and bit positions */ +-#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +-#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +-#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +-#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +-#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +-#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +- +-#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +-#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ +- +-#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_MASTER.CTRLC bit masks and bit positions */ +-#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +-#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_MASTER.STATUS bit masks and bit positions */ +-#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +-#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ +- +-#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +-#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ +- +-#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +-#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +- +-#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +-#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +-#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +-#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +-#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +-#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +- +- +-/* TWI_SLAVE.CTRLA bit masks and bit positions */ +-#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +-#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +-#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ +- +-#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +-#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ +- +-#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_SLAVE.CTRLB bit masks and bit positions */ +-#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +-#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_SLAVE.STATUS bit masks and bit positions */ +-#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +-#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +-#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +-#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ +- +-#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +-#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ +- +-#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +-#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ +- +- +-/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +-#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +-#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +-#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +-#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +-#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +-#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +-#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +-#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +-#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +-#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +-#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +-#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +-#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +-#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +-#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +-#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ +- +-#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +-#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ +- +- +-/* TWI.CTRL bit masks and bit positions */ +-#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +-#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ +- +-#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +-#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ +- +- +-/* PORT - Port Configuration */ +-/* PORTCFG.VPCTRLA bit masks and bit positions */ +-#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +-#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +-#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +-#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +-#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +-#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +-#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +-#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +-#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +-#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ +- +-#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +-#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +-#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +-#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +-#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +-#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +-#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +-#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +-#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +-#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ +- +- +-/* PORTCFG.VPCTRLB bit masks and bit positions */ +-#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +-#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +-#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +-#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +-#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +-#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +-#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +-#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +-#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +-#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ +- +-#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +-#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +-#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +-#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +-#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +-#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +-#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +-#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +-#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +-#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ +- +- +-/* PORTCFG.CLKEVOUT bit masks and bit positions */ +-#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +-#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +-#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +-#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +-#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +-#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ +- +-#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +-#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +-#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +-#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +-#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +-#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ +- +- +-/* VPORT.INTFLAGS bit masks and bit positions */ +-#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.INTCTRL bit masks and bit positions */ +-#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +-#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +-#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +-#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +-#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +-#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ +- +-#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +-#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +-#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +-#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +-#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +-#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ +- +- +-/* PORT.INTFLAGS bit masks and bit positions */ +-#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.PIN0CTRL bit masks and bit positions */ +-#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +-#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ +- +-#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +-#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ +- +-#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +-#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +-#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +-#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +-#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +-#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +-#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +-#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ +- +-#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +-#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +-#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +-#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +-#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +-#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +-#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +-#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +- +- +-/* PORT.PIN1CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN2CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN3CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN4CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN5CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN6CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN7CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* TC - 16-bit Timer/Counter With PWM */ +-/* TC0.CTRLA bit masks and bit positions */ +-#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC0.CTRLB bit masks and bit positions */ +-#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +-#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ +- +-#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +-#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ +- +-#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC0.CTRLC bit masks and bit positions */ +-#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +-#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ +- +-#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +-#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ +- +-#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC0.CTRLD bit masks and bit positions */ +-#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC0_EVACT_gp 5 /* Event Action group position. */ +-#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC0.CTRLE bit masks and bit positions */ +-#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC0.INTCTRLA bit masks and bit positions */ +-#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC0.INTCTRLB bit masks and bit positions */ +-#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +-#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +-#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +-#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +-#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +-#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ +- +-#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +-#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +-#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +-#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +-#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +-#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ +- +-#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC0.CTRLFCLR bit masks and bit positions */ +-#define TC0_CMD_gm 0x0C /* Command group mask. */ +-#define TC0_CMD_gp 2 /* Command group position. */ +-#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC0_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC0_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC0_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC0.CTRLFSET bit masks and bit positions */ +-/* TC0_CMD_gm Predefined. */ +-/* TC0_CMD_gp Predefined. */ +-/* TC0_CMD0_bm Predefined. */ +-/* TC0_CMD0_bp Predefined. */ +-/* TC0_CMD1_bm Predefined. */ +-/* TC0_CMD1_bp Predefined. */ +- +-/* TC0_LUPD_bm Predefined. */ +-/* TC0_LUPD_bp Predefined. */ +- +-/* TC0_DIR_bm Predefined. */ +-/* TC0_DIR_bp Predefined. */ +- +- +-/* TC0.CTRLGCLR bit masks and bit positions */ +-#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +-#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ +- +-#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +-#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ +- +-#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC0.CTRLGSET bit masks and bit positions */ +-/* TC0_CCDBV_bm Predefined. */ +-/* TC0_CCDBV_bp Predefined. */ +- +-/* TC0_CCCBV_bm Predefined. */ +-/* TC0_CCCBV_bp Predefined. */ +- +-/* TC0_CCBBV_bm Predefined. */ +-/* TC0_CCBBV_bp Predefined. */ +- +-/* TC0_CCABV_bm Predefined. */ +-/* TC0_CCABV_bp Predefined. */ +- +-/* TC0_PERBV_bm Predefined. */ +-/* TC0_PERBV_bp Predefined. */ +- +- +-/* TC0.INTFLAGS bit masks and bit positions */ +-#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +-#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ +- +-#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +-#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ +- +-#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* TC1.CTRLA bit masks and bit positions */ +-#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC1.CTRLB bit masks and bit positions */ +-#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC1.CTRLC bit masks and bit positions */ +-#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC1.CTRLD bit masks and bit positions */ +-#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC1_EVACT_gp 5 /* Event Action group position. */ +-#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC1.CTRLE bit masks and bit positions */ +-#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC1.INTCTRLA bit masks and bit positions */ +-#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC1.INTCTRLB bit masks and bit positions */ +-#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC1.CTRLFCLR bit masks and bit positions */ +-#define TC1_CMD_gm 0x0C /* Command group mask. */ +-#define TC1_CMD_gp 2 /* Command group position. */ +-#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC1_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC1_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC1_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC1.CTRLFSET bit masks and bit positions */ +-/* TC1_CMD_gm Predefined. */ +-/* TC1_CMD_gp Predefined. */ +-/* TC1_CMD0_bm Predefined. */ +-/* TC1_CMD0_bp Predefined. */ +-/* TC1_CMD1_bm Predefined. */ +-/* TC1_CMD1_bp Predefined. */ +- +-/* TC1_LUPD_bm Predefined. */ +-/* TC1_LUPD_bp Predefined. */ +- +-/* TC1_DIR_bm Predefined. */ +-/* TC1_DIR_bp Predefined. */ +- +- +-/* TC1.CTRLGCLR bit masks and bit positions */ +-#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC1.CTRLGSET bit masks and bit positions */ +-/* TC1_CCBBV_bm Predefined. */ +-/* TC1_CCBBV_bp Predefined. */ +- +-/* TC1_CCABV_bm Predefined. */ +-/* TC1_CCABV_bp Predefined. */ +- +-/* TC1_PERBV_bm Predefined. */ +-/* TC1_PERBV_bp Predefined. */ +- +- +-/* TC1.INTFLAGS bit masks and bit positions */ +-#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* AWEX.CTRL bit masks and bit positions */ +-#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +-#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ +- +-#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +-#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ +- +-#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +-#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ +- +-#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +-#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ +- +-#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +-#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ +- +-#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +-#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ +- +- +-/* AWEX.FDCTRL bit masks and bit positions */ +-#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +-#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ +- +-#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +-#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ +- +-#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +-#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +-#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +-#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +-#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +-#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ +- +- +-/* AWEX.STATUS bit masks and bit positions */ +-#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +-#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ +- +-#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +-#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ +- +-#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +-#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ +- +- +-/* HIRES.CTRLA bit masks and bit positions */ +-#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +-#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +-#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +-#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +-#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +-#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ +- +- +-/* USART - Universal Asynchronous Receiver-Transmitter */ +-/* USART.STATUS bit masks and bit positions */ +-#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +-#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ +- +-#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +-#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +- +-#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +-#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +- +-#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +-#define USART_FERR_bp 4 /* Frame Error bit position. */ +- +-#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +-#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ +- +-#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +-#define USART_PERR_bp 2 /* Parity Error bit position. */ +- +-#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +-#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ +- +- +-/* USART.CTRLA bit masks and bit positions */ +-#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +-#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +-#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +-#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +-#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +-#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ +- +-#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +-#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +-#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +-#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +-#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +-#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ +- +-#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +-#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +-#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +-#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +-#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +-#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ +- +- +-/* USART.CTRLB bit masks and bit positions */ +-#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +-#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ +- +-#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +-#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ +- +-#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +-#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ +- +-#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +-#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ +- +-#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +-#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ +- +- +-/* USART.CTRLC bit masks and bit positions */ +-#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +-#define USART_CMODE_gp 6 /* Communication Mode group position. */ +-#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +-#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +-#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +-#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ +- +-#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +-#define USART_PMODE_gp 4 /* Parity Mode group position. */ +-#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +-#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +-#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +-#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +- +-#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +-#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +- +-#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +-#define USART_CHSIZE_gp 0 /* Character Size group position. */ +-#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +-#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +-#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +-#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +-#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +-#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +- +- +-/* USART.BAUDCTRLA bit masks and bit positions */ +-#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +-#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +-#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +-#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +-#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +-#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +-#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +-#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +-#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +-#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +-#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +-#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +-#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +-#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +-#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +-#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +-#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +-#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ +- +- +-/* USART.BAUDCTRLB bit masks and bit positions */ +-#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +-#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +-#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +-#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +-#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +-#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +-#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +-#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +-#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +-#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ +- +-/* USART_BSEL_gm Predefined. */ +-/* USART_BSEL_gp Predefined. */ +-/* USART_BSEL0_bm Predefined. */ +-/* USART_BSEL0_bp Predefined. */ +-/* USART_BSEL1_bm Predefined. */ +-/* USART_BSEL1_bp Predefined. */ +-/* USART_BSEL2_bm Predefined. */ +-/* USART_BSEL2_bp Predefined. */ +-/* USART_BSEL3_bm Predefined. */ +-/* USART_BSEL3_bp Predefined. */ +- +- +-/* SPI - Serial Peripheral Interface */ +-/* SPI.CTRL bit masks and bit positions */ +-#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +-#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ +- +-#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +-#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ +- +-#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +-#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ +- +-#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +-#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ +- +-#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +-#define SPI_MODE_gp 2 /* SPI Mode group position. */ +-#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +-#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +-#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +-#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ +- +-#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +-#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +-#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +-#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +-#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +-#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ +- +- +-/* SPI.INTCTRL bit masks and bit positions */ +-#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +-#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +-/* SPI.STATUS bit masks and bit positions */ +-#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +-#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ +- +-#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +-#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +- +- +-/* IRCOM - IR Communication Module */ +-/* IRCOM.CTRL bit masks and bit positions */ +-#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +-#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +-#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +-#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +-#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +-#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +-#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +-#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +-#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +-#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ +- +- +- +-// Generic Port Pins +- +-#define PIN0_bm 0x01 +-#define PIN0_bp 0 +-#define PIN1_bm 0x02 +-#define PIN1_bp 1 +-#define PIN2_bm 0x04 +-#define PIN2_bp 2 +-#define PIN3_bm 0x08 +-#define PIN3_bp 3 +-#define PIN4_bm 0x10 +-#define PIN4_bp 4 +-#define PIN5_bm 0x20 +-#define PIN5_bp 5 +-#define PIN6_bm 0x40 +-#define PIN6_bp 6 +-#define PIN7_bm 0x80 +-#define PIN7_bp 7 +- +- +-/* ========== Interrupt Vector Definitions ========== */ +-/* Vector 0 is the reset vector */ +- +-/* OSC interrupt vectors */ +-#define OSC_XOSCF_vect_num 1 +-#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ +- +-/* PORTC interrupt vectors */ +-#define PORTC_INT0_vect_num 2 +-#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +-#define PORTC_INT1_vect_num 3 +-#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ +- +-/* PORTR interrupt vectors */ +-#define PORTR_INT0_vect_num 4 +-#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +-#define PORTR_INT1_vect_num 5 +-#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ +- +-/* RTC interrupt vectors */ +-#define RTC_OVF_vect_num 10 +-#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +-#define RTC_COMP_vect_num 11 +-#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ +- +-/* TWIC interrupt vectors */ +-#define TWIC_TWIS_vect_num 12 +-#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +-#define TWIC_TWIM_vect_num 13 +-#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ +- +-/* TCC0 interrupt vectors */ +-#define TCC0_OVF_vect_num 14 +-#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +-#define TCC0_ERR_vect_num 15 +-#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +-#define TCC0_CCA_vect_num 16 +-#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +-#define TCC0_CCB_vect_num 17 +-#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +-#define TCC0_CCC_vect_num 18 +-#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +-#define TCC0_CCD_vect_num 19 +-#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ +- +-/* TCC1 interrupt vectors */ +-#define TCC1_OVF_vect_num 20 +-#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +-#define TCC1_ERR_vect_num 21 +-#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +-#define TCC1_CCA_vect_num 22 +-#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +-#define TCC1_CCB_vect_num 23 +-#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ +- +-/* SPIC interrupt vectors */ +-#define SPIC_INT_vect_num 24 +-#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ +- +-/* USARTC0 interrupt vectors */ +-#define USARTC0_RXC_vect_num 25 +-#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +-#define USARTC0_DRE_vect_num 26 +-#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +-#define USARTC0_TXC_vect_num 27 +-#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ +- +-/* NVM interrupt vectors */ +-#define NVM_EE_vect_num 32 +-#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +-#define NVM_SPM_vect_num 33 +-#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ +- +-/* PORTB interrupt vectors */ +-#define PORTB_INT0_vect_num 34 +-#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +-#define PORTB_INT1_vect_num 35 +-#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ +- +-/* PORTE interrupt vectors */ +-#define PORTE_INT0_vect_num 43 +-#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +-#define PORTE_INT1_vect_num 44 +-#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ +- +-/* TCE0 interrupt vectors */ +-#define TCE0_OVF_vect_num 47 +-#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +-#define TCE0_ERR_vect_num 48 +-#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +-#define TCE0_CCA_vect_num 49 +-#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +-#define TCE0_CCB_vect_num 50 +-#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +-#define TCE0_CCC_vect_num 51 +-#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +-#define TCE0_CCD_vect_num 52 +-#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ +- +-/* USARTE0 interrupt vectors */ +-#define USARTE0_RXC_vect_num 58 +-#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +-#define USARTE0_DRE_vect_num 59 +-#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +-#define USARTE0_TXC_vect_num 60 +-#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ +- +-/* PORTD interrupt vectors */ +-#define PORTD_INT0_vect_num 64 +-#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +-#define PORTD_INT1_vect_num 65 +-#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ +- +-/* PORTA interrupt vectors */ +-#define PORTA_INT0_vect_num 66 +-#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +-#define PORTA_INT1_vect_num 67 +-#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ +- +-/* ACA interrupt vectors */ +-#define ACA_AC0_vect_num 68 +-#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +-#define ACA_AC1_vect_num 69 +-#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +-#define ACA_ACW_vect_num 70 +-#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ +- +-/* ADCA interrupt vectors */ +-#define ADCA_CH0_vect_num 71 +-#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +- +-/* TCD0 interrupt vectors */ +-#define TCD0_OVF_vect_num 77 +-#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +-#define TCD0_ERR_vect_num 78 +-#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +-#define TCD0_CCA_vect_num 79 +-#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +-#define TCD0_CCB_vect_num 80 +-#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +-#define TCD0_CCC_vect_num 81 +-#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +-#define TCD0_CCD_vect_num 82 +-#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ +- +-/* SPID interrupt vectors */ +-#define SPID_INT_vect_num 87 +-#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ +- +-/* USARTD0 interrupt vectors */ +-#define USARTD0_RXC_vect_num 88 +-#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +-#define USARTD0_DRE_vect_num 89 +-#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +-#define USARTD0_TXC_vect_num 90 +-#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ +- +-/* PORTF interrupt vectors */ +-#define PORTF_INT0_vect_num 104 +-#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +-#define PORTF_INT1_vect_num 105 +-#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ +- +-/* TCF0 interrupt vectors */ +-#define TCF0_OVF_vect_num 108 +-#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ +-#define TCF0_ERR_vect_num 109 +-#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ +-#define TCF0_CCA_vect_num 110 +-#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ +-#define TCF0_CCB_vect_num 111 +-#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ +-#define TCF0_CCC_vect_num 112 +-#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ +-#define TCF0_CCD_vect_num 113 +-#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ +- +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (114 * _VECTOR_SIZE) +- +- +-/* ========== Constants ========== */ +- +-#define PROGMEM_START (0x0000) +-#define PROGMEM_SIZE (204800) +-#define PROGMEM_PAGE_SIZE (512) +-#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) +- +-#define APP_SECTION_START (0x0000) +-#define APP_SECTION_SIZE (196608) +-#define APP_SECTION_PAGE_SIZE (512) +-#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) +- +-#define APPTABLE_SECTION_START (0x2E000) +-#define APPTABLE_SECTION_SIZE (8192) +-#define APPTABLE_SECTION_PAGE_SIZE (512) +-#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) +- +-#define BOOT_SECTION_START (0x30000) +-#define BOOT_SECTION_SIZE (8192) +-#define BOOT_SECTION_PAGE_SIZE (512) +-#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) +- +-#define DATAMEM_START (0x0000) +-#define DATAMEM_SIZE (24576) +-#define DATAMEM_PAGE_SIZE (0) +-#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) +- +-#define IO_START (0x0000) +-#define IO_SIZE (4096) +-#define IO_PAGE_SIZE (0) +-#define IO_END (IO_START + IO_SIZE - 1) +- +-#define MAPPED_EEPROM_START (0x1000) +-#define MAPPED_EEPROM_SIZE (2048) +-#define MAPPED_EEPROM_PAGE_SIZE (0) +-#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) +- +-#define INTERNAL_SRAM_START (0x2000) +-#define INTERNAL_SRAM_SIZE (16384) +-#define INTERNAL_SRAM_PAGE_SIZE (0) +-#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) +- +-#define EEPROM_START (0x0000) +-#define EEPROM_SIZE (2048) +-#define EEPROM_PAGE_SIZE (32) +-#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) +- +-#define FUSE_START (0x0000) +-#define FUSE_SIZE (6) +-#define FUSE_PAGE_SIZE (0) +-#define FUSE_END (FUSE_START + FUSE_SIZE - 1) +- +-#define LOCKBIT_START (0x0000) +-#define LOCKBIT_SIZE (1) +-#define LOCKBIT_PAGE_SIZE (0) +-#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) +- +-#define SIGNATURES_START (0x0000) +-#define SIGNATURES_SIZE (3) +-#define SIGNATURES_PAGE_SIZE (0) +-#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) +- +-#define USER_SIGNATURES_START (0x0000) +-#define USER_SIGNATURES_SIZE (512) +-#define USER_SIGNATURES_PAGE_SIZE (0) +-#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) +- +-#define PROD_SIGNATURES_START (0x0000) +-#define PROD_SIGNATURES_SIZE (52) +-#define PROD_SIGNATURES_PAGE_SIZE (0) +-#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) +- +-#define FLASHEND PROGMEM_END +-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +-#define RAMSTART INTERNAL_SRAM_START +-#define RAMSIZE INTERNAL_SRAM_SIZE +-#define RAMEND INTERNAL_SRAM_END +-#define XRAMSTART EXTERNAL_SRAM_START +-#define XRAMSIZE EXTERNAL_SRAM_SIZE +-#define XRAMEND INTERNAL_SRAM_END +-#define E2END EEPROM_END +-#define E2PAGESIZE EEPROM_PAGE_SIZE +- +- +-/* ========== Fuses ========== */ +-#define FUSE_MEMORY_SIZE 6 +- +-/* Fuse Byte 0 */ +-#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ +-#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ +-#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ +-#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ +-#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ +-#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ +-#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ +-#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ +-#define FUSE0_DEFAULT (0xFF) +- +-/* Fuse Byte 1 */ +-#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +-#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +-#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +-#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +-#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +-#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +-#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +-#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +-#define FUSE1_DEFAULT (0xFF) +- +-/* Fuse Byte 2 */ +-#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +-#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +-#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +-#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +-#define FUSE2_DEFAULT (0xFF) +- +-/* Fuse Byte 3 Reserved */ +- +-/* Fuse Byte 4 */ +-#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +-#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +-#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +-#define FUSE4_DEFAULT (0xFF) +- +-/* Fuse Byte 5 */ +-#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +-#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +-#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +-#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +-#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +-#define FUSE5_DEFAULT (0xFF) +- +- +-/* ========== Lock Bits ========== */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_BITS_EXIST +-#define __BOOT_LOCK_BOOT_BITS_EXIST +- +- +-/* ========== Signature ========== */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x97 +-#define SIGNATURE_2 0x49 +- +- +-#endif /* _AVR_ATxmega192D3_H_ */ +- ++/* Copyright (c) 2009-2010 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iox192d3.h 2194 2010-11-16 15:10:51Z arcanum $ */ ++ ++/* avr/iox192d3.h - definitions for ATxmega192D3 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox192d3.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATxmega192D3_H_ ++#define _AVR_ATxmega192D3_H_ 1 ++ ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++} CLK_t; ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t reserved_0x02; ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ ++} CLK_RTCSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control REgister */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ ++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ ++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ ++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ ++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t reserved_0x07; ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ ++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ ++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ ++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ ++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ ++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ ++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ ++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ ++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ ++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ ++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ ++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ ++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t FUSEBYTE0; /* User ID */ ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ ++ register8_t reserved_0x01; ++ register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ ++ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ ++ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ ++ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++} NVM_PROD_SIGNATURES_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++} NVM_LB_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brown Out Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V9_gc = (0x06<<0), /* 1.9 V */ ++ BODLVL_2V1_gc = (0x05<<0), /* 2.1 V */ ++ BODLVL_2V4_gc = (0x04<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x03<<0), /* 2.6 V */ ++ BODLVL_2V9_gc = (0x02<<0), /* 2.9 V */ ++ BODLVL_3V2_gc = (0x01<<0), /* 3.2 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Comparator 0 Control */ ++ register8_t AC1CTRL; /* Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t reserved_0x6; ++ register8_t reserved_0x7; ++} ADC_CH_t; ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++} ADC_t; ++ ++/* Current Limitation */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 225ksps max sampling rate */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 75ksps max sampling rate */ ++} ADC_CURRLIMIT_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++} ADC_REFSEL_t; ++ ++/* Channel sweep selection */ ++typedef enum ADC_SWEEP_enum ++{ ++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ++} ADC_SWEEP_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Clounter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* EBI Chip Select Module */ ++typedef struct EBI_CS_struct ++{ ++ register8_t CTRLA; /* Chip Select Control Register A */ ++ register8_t CTRLB; /* Chip Select Control Register B */ ++ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ ++} EBI_CS_t; ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* External Bus Interface */ ++typedef struct EBI_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ ++ register8_t reserved_0x02; ++ register8_t reserved_0x03; ++ _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ ++ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ ++ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ ++ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ EBI_CS_t CS0; /* Chip Select 0 */ ++ EBI_CS_t CS1; /* Chip Select 1 */ ++ EBI_CS_t CS2; /* Chip Select 2 */ ++ EBI_CS_t CS3; /* Chip Select 3 */ ++} EBI_t; ++ ++/* Chip Select adress space */ ++typedef enum EBI_CS_ASIZE_enum ++{ ++ EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ ++ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ ++ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ ++ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ ++ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ ++ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ ++ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ ++ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ ++ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ ++ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ ++ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ ++ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ ++ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ ++ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ ++ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ ++ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ ++ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ ++} EBI_CS_ASIZE_t; ++ ++/* */ ++typedef enum EBI_CS_SRWS_enum ++{ ++ EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_CS_SRWS_t; ++ ++/* Chip Select address mode */ ++typedef enum EBI_CS_MODE_enum ++{ ++ EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ ++ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ ++ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ ++ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ ++} EBI_CS_MODE_t; ++ ++/* Chip Select SDRAM mode */ ++typedef enum EBI_CS_SDMODE_enum ++{ ++ EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ ++ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ ++} EBI_CS_SDMODE_t; ++ ++/* */ ++typedef enum EBI_SDDATAW_enum ++{ ++ EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ ++ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ ++} EBI_SDDATAW_t; ++ ++/* */ ++typedef enum EBI_LPCMODE_enum ++{ ++ EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ ++ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ ++} EBI_LPCMODE_t; ++ ++/* */ ++typedef enum EBI_SRMODE_enum ++{ ++ EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ ++ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ ++ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ ++ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ ++} EBI_SRMODE_t; ++ ++/* */ ++typedef enum EBI_IFMODE_enum ++{ ++ EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ ++ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ ++ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ ++ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ ++} EBI_IFMODE_t; ++ ++/* */ ++typedef enum EBI_SDCOL_enum ++{ ++ EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ ++ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ ++ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ ++ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ ++} EBI_SDCOL_t; ++ ++/* */ ++typedef enum EBI_MRDLY_enum ++{ ++ EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_MRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCYCDLY_enum ++{ ++ EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ROWCYCDLY_t; ++ ++/* */ ++typedef enum EBI_RPDLY_enum ++{ ++ EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_RPDLY_t; ++ ++/* */ ++typedef enum EBI_WRDLY_enum ++{ ++ EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_WRDLY_t; ++ ++/* */ ++typedef enum EBI_ESRDLY_enum ++{ ++ EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ESRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCOLDLY_enum ++{ ++ EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_ROWCOLDLY_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++} PORTCFG_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Virtual Port 0 Mapping */ ++typedef enum PORTCFG_VP0MAP_enum ++{ ++ PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP0MAP_t; ++ ++/* Virtual Port 1 Mapping */ ++typedef enum PORTCFG_VP1MAP_enum ++{ ++ PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP1MAP_t; ++ ++/* Virtual Port 2 Mapping */ ++typedef enum PORTCFG_VP2MAP_enum ++{ ++ PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP2MAP_t; ++ ++/* Virtual Port 3 Mapping */ ++typedef enum PORTCFG_VP3MAP_enum ++{ ++ PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP3MAP_t; ++ ++/* Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x05; ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset Controller */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ ++#define PORTA (*(PORT_t *) 0x0600) /* Port A */ ++#define PORTB (*(PORT_t *) 0x0620) /* Port B */ ++#define PORTC (*(PORT_t *) 0x0640) /* Port C */ ++#define PORTD (*(PORT_t *) 0x0660) /* Port D */ ++#define PORTE (*(PORT_t *) 0x0680) /* Port E */ ++#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ ++#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ ++#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ ++#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ ++#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ ++#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++#define GPIO_GPIOR4 _SFR_MEM8(0x0004) ++#define GPIO_GPIOR5 _SFR_MEM8(0x0005) ++#define GPIO_GPIOR6 _SFR_MEM8(0x0006) ++#define GPIO_GPIOR7 _SFR_MEM8(0x0007) ++#define GPIO_GPIOR8 _SFR_MEM8(0x0008) ++#define GPIO_GPIOR9 _SFR_MEM8(0x0009) ++#define GPIO_GPIORA _SFR_MEM8(0x000A) ++#define GPIO_GPIORB _SFR_MEM8(0x000B) ++#define GPIO_GPIORC _SFR_MEM8(0x000C) ++#define GPIO_GPIORD _SFR_MEM8(0x000D) ++#define GPIO_GPIORE _SFR_MEM8(0x000E) ++#define GPIO_GPIORF _SFR_MEM8(0x000F) ++ ++/* VPORT0 - Virtual Port 0 */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT1 - Virtual Port 1 */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT2 - Virtual Port 2 */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT3 - Virtual Port 3 */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU Registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator Control */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset Controller */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - Port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non Volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADCA - Analog to Digital Converter A */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++ ++/* ACA - Analog Comparator A */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWIC - Two-Wire Interface C */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0483) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0484) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0485) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0486) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0487) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWIE - Two-Wire Interface E */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* PORTA - Port A */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORTB - Port B */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORTC - Port C */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORTD - Port D */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORTE - Port E */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORTF - Port F */ ++#define PORTF_DIR _SFR_MEM8(0x06A0) ++#define PORTF_DIRSET _SFR_MEM8(0x06A1) ++#define PORTF_DIRCLR _SFR_MEM8(0x06A2) ++#define PORTF_DIRTGL _SFR_MEM8(0x06A3) ++#define PORTF_OUT _SFR_MEM8(0x06A4) ++#define PORTF_OUTSET _SFR_MEM8(0x06A5) ++#define PORTF_OUTCLR _SFR_MEM8(0x06A6) ++#define PORTF_OUTTGL _SFR_MEM8(0x06A7) ++#define PORTF_IN _SFR_MEM8(0x06A8) ++#define PORTF_INTCTRL _SFR_MEM8(0x06A9) ++#define PORTF_INT0MASK _SFR_MEM8(0x06AA) ++#define PORTF_INT1MASK _SFR_MEM8(0x06AB) ++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) ++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) ++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) ++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) ++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) ++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) ++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) ++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) ++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) ++ ++/* PORTR - Port R */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TCC0 - Timer/Counter C0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TCC1 - Timer/Counter C1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEXC - Advanced Waveform Extension C */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRESC - High-Resolution Extension C */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* SPIC - Serial Peripheral Interface C */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TCD0 - Timer/Counter D0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* SPID - Serial Peripheral Interface D */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TCE0 - Timer/Counter E0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* AWEXE - Advanced Waveform Extension E */ ++#define AWEXE_CTRL _SFR_MEM8(0x0A80) ++#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) ++#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) ++#define AWEXE_STATUS _SFR_MEM8(0x0A84) ++#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) ++#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) ++#define AWEXE_DTLS _SFR_MEM8(0x0A88) ++#define AWEXE_DTHS _SFR_MEM8(0x0A89) ++#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) ++#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) ++#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) ++ ++/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* SPIE - Serial Peripheral Interface E */ ++#define SPIE_CTRL _SFR_MEM8(0x0AC0) ++#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) ++#define SPIE_STATUS _SFR_MEM8(0x0AC2) ++#define SPIE_DATA _SFR_MEM8(0x0AC3) ++ ++/* TCF0 - Timer/Counter F0 */ ++#define TCF0_CTRLA _SFR_MEM8(0x0B00) ++#define TCF0_CTRLB _SFR_MEM8(0x0B01) ++#define TCF0_CTRLC _SFR_MEM8(0x0B02) ++#define TCF0_CTRLD _SFR_MEM8(0x0B03) ++#define TCF0_CTRLE _SFR_MEM8(0x0B04) ++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) ++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) ++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) ++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) ++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF0_TEMP _SFR_MEM8(0x0B0F) ++#define TCF0_CNT _SFR_MEM16(0x0B20) ++#define TCF0_PER _SFR_MEM16(0x0B26) ++#define TCF0_CCA _SFR_MEM16(0x0B28) ++#define TCF0_CCB _SFR_MEM16(0x0B2A) ++#define TCF0_CCC _SFR_MEM16(0x0B2C) ++#define TCF0_CCD _SFR_MEM16(0x0B2E) ++#define TCF0_PERBUF _SFR_MEM16(0x0B36) ++#define TCF0_CCABUF _SFR_MEM16(0x0B38) ++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) ++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) ++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR1 bit masks and bit positions */ ++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ ++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ ++ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ ++ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ ++#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ ++ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ ++ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ ++ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ ++#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ ++ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ ++ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ ++ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ ++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ ++ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM_gm Predefined. */ ++/* EVSYS_QDIRM_gp Predefined. */ ++/* EVSYS_QDIRM0_bm Predefined. */ ++/* EVSYS_QDIRM0_bp Predefined. */ ++/* EVSYS_QDIRM1_bm Predefined. */ ++/* EVSYS_QDIRM1_bp Predefined. */ ++ ++/* EVSYS_QDIEN_bm Predefined. */ ++/* EVSYS_QDIEN_bp Predefined. */ ++ ++/* EVSYS_QDEN_bm Predefined. */ ++/* EVSYS_QDEN_bp Predefined. */ ++ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0xFF /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ ++#define NVM_CMD7_bp 7 /* Command bit 7 position. */ ++ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ ++#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ ++#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ ++#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ ++#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ ++#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ ++#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ ++#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ ++#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ ++#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ ++#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ ++#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ ++#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ ++#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ ++#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ ++#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ ++#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ ++#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ ++#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ ++#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ ++ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ ++ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ ++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE_gm Predefined. */ ++/* AC_INTMODE_gp Predefined. */ ++/* AC_INTMODE0_bm Predefined. */ ++/* AC_INTMODE0_bp Predefined. */ ++/* AC_INTMODE1_bm Predefined. */ ++/* AC_INTMODE1_bp Predefined. */ ++ ++/* AC_INTLVL_gm Predefined. */ ++/* AC_INTLVL_gp Predefined. */ ++/* AC_INTLVL0_bm Predefined. */ ++/* AC_INTLVL0_bp Predefined. */ ++/* AC_INTLVL1_bm Predefined. */ ++/* AC_INTLVL1_bp Predefined. */ ++ ++/* AC_HSMODE_bm Predefined. */ ++/* AC_HSMODE_bp Predefined. */ ++ ++/* AC_HYSMODE_gm Predefined. */ ++/* AC_HYSMODE_gp Predefined. */ ++/* AC_HYSMODE0_bm Predefined. */ ++/* AC_HYSMODE0_bp Predefined. */ ++/* AC_HYSMODE1_bm Predefined. */ ++/* AC_HYSMODE1_bp Predefined. */ ++ ++/* AC_ENABLE_bm Predefined. */ ++/* AC_ENABLE_bp Predefined. */ ++ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS_gm Predefined. */ ++/* AC_MUXPOS_gp Predefined. */ ++/* AC_MUXPOS0_bm Predefined. */ ++/* AC_MUXPOS0_bp Predefined. */ ++/* AC_MUXPOS1_bm Predefined. */ ++/* AC_MUXPOS1_bp Predefined. */ ++/* AC_MUXPOS2_bm Predefined. */ ++/* AC_MUXPOS2_bp Predefined. */ ++ ++/* AC_MUXNEG_gm Predefined. */ ++/* AC_MUXNEG_gp Predefined. */ ++/* AC_MUXNEG0_bm Predefined. */ ++/* AC_MUXNEG0_bp Predefined. */ ++/* AC_MUXNEG1_bm Predefined. */ ++/* AC_MUXNEG1_bp Predefined. */ ++/* AC_MUXNEG2_bm Predefined. */ ++/* AC_MUXNEG2_bp Predefined. */ ++ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ ++ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ ++ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ ++ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ ++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ ++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ ++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ ++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ ++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ ++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ ++ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++ ++/* RTC - Real-Time Clounter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* EBI - External Bus Interface */ ++/* EBI_CS.CTRLA bit masks and bit positions */ ++#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ ++#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ ++#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ ++#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ ++#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ ++#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ ++#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ ++#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ ++#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ ++#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ ++#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ ++#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ ++ ++#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ ++#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ ++#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ ++#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ ++#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ ++#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ ++ ++ ++/* EBI_CS.CTRLB bit masks and bit positions */ ++#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ ++#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ ++#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ ++#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ ++#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ ++#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ ++#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ ++#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ ++ ++#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ ++#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ ++ ++#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ ++#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ ++ ++#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ ++#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ ++#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ ++#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ ++#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ ++#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ ++ ++ ++/* EBI.CTRL bit masks and bit positions */ ++#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ ++#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ ++#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ ++#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ ++#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ ++#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ ++ ++#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ ++#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ ++#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ ++#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ ++#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ ++#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ ++ ++#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ ++#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ ++#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ ++#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ ++#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ ++#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ ++ ++#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ ++#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ ++#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ ++#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ ++#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ ++#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLA bit masks and bit positions */ ++#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ ++#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ ++ ++#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ ++#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ ++ ++#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ ++#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ ++#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ ++#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ ++#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ ++#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLB bit masks and bit positions */ ++#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ ++#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ ++#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ ++#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ ++#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ ++#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ ++ ++#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ ++#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ ++#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ ++#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ ++#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ ++#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ ++#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ ++#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ ++ ++#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ ++#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ ++#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ ++#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ ++#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ ++#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ ++#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ ++#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ ++ ++ ++/* EBI.SDRAMCTRLC bit masks and bit positions */ ++#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ ++#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ ++#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ ++#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ ++#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ ++#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ ++ ++#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ ++#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ ++#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ ++#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ ++#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ ++#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ ++#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ ++#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ ++ ++#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ ++#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ ++#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ ++#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ ++#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ ++#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ ++#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ ++#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ ++ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ ++#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++ ++/* PORT - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD_gm Predefined. */ ++/* TC0_CMD_gp Predefined. */ ++/* TC0_CMD0_bm Predefined. */ ++/* TC0_CMD0_bp Predefined. */ ++/* TC0_CMD1_bm Predefined. */ ++/* TC0_CMD1_bp Predefined. */ ++ ++/* TC0_LUPD_bm Predefined. */ ++/* TC0_LUPD_bp Predefined. */ ++ ++/* TC0_DIR_bm Predefined. */ ++/* TC0_DIR_bp Predefined. */ ++ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV_bm Predefined. */ ++/* TC0_CCDBV_bp Predefined. */ ++ ++/* TC0_CCCBV_bm Predefined. */ ++/* TC0_CCCBV_bp Predefined. */ ++ ++/* TC0_CCBBV_bm Predefined. */ ++/* TC0_CCBBV_bp Predefined. */ ++ ++/* TC0_CCABV_bm Predefined. */ ++/* TC0_CCABV_bp Predefined. */ ++ ++/* TC0_PERBV_bm Predefined. */ ++/* TC0_PERBV_bp Predefined. */ ++ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD_gm Predefined. */ ++/* TC1_CMD_gp Predefined. */ ++/* TC1_CMD0_bm Predefined. */ ++/* TC1_CMD0_bp Predefined. */ ++/* TC1_CMD1_bm Predefined. */ ++/* TC1_CMD1_bp Predefined. */ ++ ++/* TC1_LUPD_bm Predefined. */ ++/* TC1_LUPD_bp Predefined. */ ++ ++/* TC1_DIR_bm Predefined. */ ++/* TC1_DIR_bp Predefined. */ ++ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV_bm Predefined. */ ++/* TC1_CCBBV_bp Predefined. */ ++ ++/* TC1_CCABV_bm Predefined. */ ++/* TC1_CCABV_bp Predefined. */ ++ ++/* TC1_PERBV_bm Predefined. */ ++/* TC1_PERBV_bp Predefined. */ ++ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL_gm Predefined. */ ++/* USART_BSEL_gp Predefined. */ ++/* USART_BSEL0_bm Predefined. */ ++/* USART_BSEL0_bp Predefined. */ ++/* USART_BSEL1_bm Predefined. */ ++/* USART_BSEL1_bp Predefined. */ ++/* USART_BSEL2_bm Predefined. */ ++/* USART_BSEL2_bp Predefined. */ ++/* USART_BSEL3_bm Predefined. */ ++/* USART_BSEL3_bp Predefined. */ ++ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_XOSCF_vect_num 1 ++#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* PORTF interrupt vectors */ ++#define PORTF_INT0_vect_num 104 ++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ ++#define PORTF_INT1_vect_num 105 ++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_OVF_vect_num 108 ++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ ++#define TCF0_ERR_vect_num 109 ++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ ++#define TCF0_CCA_vect_num 110 ++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ ++#define TCF0_CCB_vect_num 111 ++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ ++#define TCF0_CCC_vect_num 112 ++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ ++#define TCF0_CCD_vect_num 113 ++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ ++ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (114 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (204800) ++#define PROGMEM_PAGE_SIZE (512) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (196608) ++#define APP_SECTION_PAGE_SIZE (512) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x2E000) ++#define APPTABLE_SECTION_SIZE (8192) ++#define APPTABLE_SECTION_PAGE_SIZE (512) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x30000) ++#define BOOT_SECTION_SIZE (8192) ++#define BOOT_SECTION_PAGE_SIZE (512) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (24576) ++#define DATAMEM_PAGE_SIZE (0) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (2048) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (16384) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (2048) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define FUSE_START (0x0000) ++#define FUSE_SIZE (6) ++#define FUSE_PAGE_SIZE (0) ++#define FUSE_END (FUSE_START + FUSE_SIZE - 1) ++ ++#define LOCKBIT_START (0x0000) ++#define LOCKBIT_SIZE (1) ++#define LOCKBIT_PAGE_SIZE (0) ++#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (512) ++#define USER_SIGNATURES_PAGE_SIZE (0) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (0) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE PROGMEM_PAGE_SIZE ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define XRAMSTART EXTERNAL_SRAM_START ++#define XRAMSIZE EXTERNAL_SRAM_SIZE ++#define XRAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 */ ++#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ ++#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ ++#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ ++#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ ++#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ ++#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ ++#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ ++#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ ++#define FUSE0_DEFAULT (0xFF) ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x97 ++#define SIGNATURE_2 0x49 ++ ++ ++#endif /* _AVR_ATxmega192D3_H_ */ ++ +diff --git a/include/avr/iox256a3.h b/include/avr/iox256a3.h +index 1048d46..c7eef30 100644 +--- a/include/avr/iox256a3.h ++++ b/include/avr/iox256a3.h +@@ -1,6917 +1,6917 @@ +-/* Copyright (c) 2009-2010 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iox256a3.h 2200 2010-12-14 04:24:24Z arcanum $ */ +- +-/* avr/iox256a3.h - definitions for ATxmega256A3 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iox256a3.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATxmega256A3_H_ +-#define _AVR_ATxmega256A3_H_ 1 +- +- +-/* Ungrouped common registers */ +-#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +-#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +-#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +-#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +-#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +-#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +-#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +-#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +-#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +-#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +-#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +-#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +-#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +-#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +-#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +-#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +- +-/* Deprecated */ +-#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +-#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +-#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +-#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +-#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +-#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +-#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +-#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +-#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +-#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +-#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +-#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +-#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +-#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +-#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +-#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +- +-#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +-#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +-#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +-#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +-#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +-#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +-#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +-#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +-#define SREG _SFR_MEM8(0x003F) /* Status Register */ +- +- +-/* C Language Only */ +-#if !defined (__ASSEMBLER__) +- +-#include +- +-typedef volatile uint8_t register8_t; +-typedef volatile uint16_t register16_t; +-typedef volatile uint32_t register32_t; +- +- +-#ifdef _WORDREGISTER +-#undef _WORDREGISTER +-#endif +-#define _WORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register16_t regname; \ +- struct \ +- { \ +- register8_t regname ## L; \ +- register8_t regname ## H; \ +- }; \ +- } +- +-#ifdef _DWORDREGISTER +-#undef _DWORDREGISTER +-#endif +-#define _DWORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register32_t regname; \ +- struct \ +- { \ +- register8_t regname ## 0; \ +- register8_t regname ## 1; \ +- register8_t regname ## 2; \ +- register8_t regname ## 3; \ +- }; \ +- } +- +- +-/* +-========================================================================== +-IO Module Structures +-========================================================================== +-*/ +- +- +-/* +--------------------------------------------------------------------------- +-XOCD - On-Chip Debug System +--------------------------------------------------------------------------- +-*/ +- +-/* On-Chip Debug System */ +-typedef struct OCD_struct +-{ +- register8_t OCDR0; /* OCD Register 0 */ +- register8_t OCDR1; /* OCD Register 1 */ +-} OCD_t; +- +- +-/* CCP signatures */ +-typedef enum CCP_enum +-{ +- CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ +- CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +-} CCP_t; +- +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Clock System */ +-typedef struct CLK_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t PSCTRL; /* Prescaler Control Register */ +- register8_t LOCK; /* Lock register */ +- register8_t RTCCTRL; /* RTC Control Register */ +-} CLK_t; +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Power Reduction */ +-typedef struct PR_struct +-{ +- register8_t PRGEN; /* General Power Reduction */ +- register8_t PRPA; /* Power Reduction Port A */ +- register8_t PRPB; /* Power Reduction Port B */ +- register8_t PRPC; /* Power Reduction Port C */ +- register8_t PRPD; /* Power Reduction Port D */ +- register8_t PRPE; /* Power Reduction Port E */ +- register8_t PRPF; /* Power Reduction Port F */ +-} PR_t; +- +-/* System Clock Selection */ +-typedef enum CLK_SCLKSEL_enum +-{ +- CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ +- CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ +- CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ +- CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ +- CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +-} CLK_SCLKSEL_t; +- +-/* Prescaler A Division Factor */ +-typedef enum CLK_PSADIV_enum +-{ +- CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ +- CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ +- CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ +- CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ +- CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ +- CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ +- CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ +- CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ +- CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ +- CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +-} CLK_PSADIV_t; +- +-/* Prescaler B and C Division Factor */ +-typedef enum CLK_PSBCDIV_enum +-{ +- CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ +- CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ +- CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ +- CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +-} CLK_PSBCDIV_t; +- +-/* RTC Clock Source */ +-typedef enum CLK_RTCSRC_enum +-{ +- CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ +- CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ +- CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ +- CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +-} CLK_RTCSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-SLEEP - Sleep Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Sleep Controller */ +-typedef struct SLEEP_struct +-{ +- register8_t CTRL; /* Control Register */ +-} SLEEP_t; +- +-/* Sleep Mode */ +-typedef enum SLEEP_SMODE_enum +-{ +- SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ +- SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +- SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ +- SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ +- SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +-} SLEEP_SMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-OSC - Oscillator +--------------------------------------------------------------------------- +-*/ +- +-/* Oscillator */ +-typedef struct OSC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t XOSCCTRL; /* External Oscillator Control Register */ +- register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ +- register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ +- register8_t PLLCTRL; /* PLL Control REgister */ +- register8_t DFLLCTRL; /* DFLL Control Register */ +-} OSC_t; +- +-/* Oscillator Frequency Range */ +-typedef enum OSC_FRQRANGE_enum +-{ +- OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ +- OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ +- OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ +- OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +-} OSC_FRQRANGE_t; +- +-/* External Oscillator Selection and Startup Time */ +-typedef enum OSC_XOSCSEL_enum +-{ +- OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ +- OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ +- OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ +- OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ +- OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +-} OSC_XOSCSEL_t; +- +-/* PLL Clock Source */ +-typedef enum OSC_PLLSRC_enum +-{ +- OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ +- OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ +- OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +-} OSC_PLLSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-DFLL - DFLL +--------------------------------------------------------------------------- +-*/ +- +-/* DFLL */ +-typedef struct DFLL_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t CALA; /* Calibration Register A */ +- register8_t CALB; /* Calibration Register B */ +- register8_t COMP0; /* Oscillator Compare Register 0 */ +- register8_t COMP1; /* Oscillator Compare Register 1 */ +- register8_t COMP2; /* Oscillator Compare Register 2 */ +- register8_t reserved_0x07; +-} DFLL_t; +- +- +-/* +--------------------------------------------------------------------------- +-RST - Reset +--------------------------------------------------------------------------- +-*/ +- +-/* Reset */ +-typedef struct RST_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t CTRL; /* Control Register */ +-} RST_t; +- +- +-/* +--------------------------------------------------------------------------- +-WDT - Watch-Dog Timer +--------------------------------------------------------------------------- +-*/ +- +-/* Watch-Dog Timer */ +-typedef struct WDT_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t WINCTRL; /* Windowed Mode Control */ +- register8_t STATUS; /* Status */ +-} WDT_t; +- +-/* Period setting */ +-typedef enum WDT_PER_enum +-{ +- WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ +- WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ +- WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ +- WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_PER_t; +- +-/* Closed window period */ +-typedef enum WDT_WPER_enum +-{ +- WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ +- WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ +- WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ +- WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_WPER_t; +- +- +-/* +--------------------------------------------------------------------------- +-MCU - MCU Control +--------------------------------------------------------------------------- +-*/ +- +-/* MCU Control */ +-typedef struct MCU_struct +-{ +- register8_t DEVID0; /* Device ID byte 0 */ +- register8_t DEVID1; /* Device ID byte 1 */ +- register8_t DEVID2; /* Device ID byte 2 */ +- register8_t REVID; /* Revision ID */ +- register8_t JTAGUID; /* JTAG User ID */ +- register8_t reserved_0x05; +- register8_t MCUCR; /* MCU Control */ +- register8_t reserved_0x07; +- register8_t EVSYSLOCK; /* Event System Lock */ +- register8_t AWEXLOCK; /* AWEX Lock */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +-} MCU_t; +- +- +-/* +--------------------------------------------------------------------------- +-PMIC - Programmable Multi-level Interrupt Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Programmable Multi-level Interrupt Controller */ +-typedef struct PMIC_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t INTPRI; /* Interrupt Priority */ +- register8_t CTRL; /* Control Register */ +-} PMIC_t; +- +- +-/* +--------------------------------------------------------------------------- +-DMA - DMA Controller +--------------------------------------------------------------------------- +-*/ +- +-/* DMA Channel */ +-typedef struct DMA_CH_struct +-{ +- register8_t CTRLA; /* Channel Control */ +- register8_t CTRLB; /* Channel Control */ +- register8_t ADDRCTRL; /* Address Control */ +- register8_t TRIGSRC; /* Channel Trigger Source */ +- _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ +- register8_t REPCNT; /* Channel Repeat Count */ +- register8_t reserved_0x07; +- register8_t SRCADDR0; /* Channel Source Address 0 */ +- register8_t SRCADDR1; /* Channel Source Address 1 */ +- register8_t SRCADDR2; /* Channel Source Address 2 */ +- register8_t reserved_0x0B; +- register8_t DESTADDR0; /* Channel Destination Address 0 */ +- register8_t DESTADDR1; /* Channel Destination Address 1 */ +- register8_t DESTADDR2; /* Channel Destination Address 2 */ +- register8_t reserved_0x0F; +-} DMA_CH_t; +- +-/* +--------------------------------------------------------------------------- +-DMA - DMA Controller +--------------------------------------------------------------------------- +-*/ +- +-/* DMA Controller */ +-typedef struct DMA_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t reserved_0x01; +- register8_t reserved_0x02; +- register8_t INTFLAGS; /* Transfer Interrupt Status */ +- register8_t STATUS; /* Status */ +- register8_t reserved_0x05; +- _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- DMA_CH_t CH0; /* DMA Channel 0 */ +- DMA_CH_t CH1; /* DMA Channel 1 */ +- DMA_CH_t CH2; /* DMA Channel 2 */ +- DMA_CH_t CH3; /* DMA Channel 3 */ +-} DMA_t; +- +-/* Burst mode */ +-typedef enum DMA_CH_BURSTLEN_enum +-{ +- DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ +- DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ +- DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ +- DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +-} DMA_CH_BURSTLEN_t; +- +-/* Source address reload mode */ +-typedef enum DMA_CH_SRCRELOAD_enum +-{ +- DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ +- DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ +- DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ +- DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +-} DMA_CH_SRCRELOAD_t; +- +-/* Source addressing mode */ +-typedef enum DMA_CH_SRCDIR_enum +-{ +- DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ +- DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ +- DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +-} DMA_CH_SRCDIR_t; +- +-/* Destination adress reload mode */ +-typedef enum DMA_CH_DESTRELOAD_enum +-{ +- DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ +- DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ +- DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ +- DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +-} DMA_CH_DESTRELOAD_t; +- +-/* Destination adressing mode */ +-typedef enum DMA_CH_DESTDIR_enum +-{ +- DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ +- DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ +- DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +-} DMA_CH_DESTDIR_t; +- +-/* Transfer trigger source */ +-typedef enum DMA_CH_TRIGSRC_enum +-{ +- DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ +- DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ +- DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ +- DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ +- DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ +- DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ +- DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ +- DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ +- DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ +- DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ +- DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ +- DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ +- DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ +- DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ +- DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ +- DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ +- DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ +- DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ +- DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ +- DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ +- DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ +- DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ +- DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ +- DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ +- DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ +- DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ +- DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ +- DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ +- DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ +- DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ +- DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ +- DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ +- DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ +- DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ +- DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ +- DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ +- DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ +- DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ +- DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +-} DMA_CH_TRIGSRC_t; +- +-/* Double buffering mode */ +-typedef enum DMA_DBUFMODE_enum +-{ +- DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ +- DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ +- DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ +- DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +-} DMA_DBUFMODE_t; +- +-/* Priority mode */ +-typedef enum DMA_PRIMODE_enum +-{ +- DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ +- DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ +- DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ +- DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +-} DMA_PRIMODE_t; +- +-/* Interrupt level */ +-typedef enum DMA_CH_ERRINTLVL_enum +-{ +- DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ +- DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ +- DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +-} DMA_CH_ERRINTLVL_t; +- +-/* Interrupt level */ +-typedef enum DMA_CH_TRNINTLVL_enum +-{ +- DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ +- DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ +- DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +-} DMA_CH_TRNINTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-EVSYS - Event System +--------------------------------------------------------------------------- +-*/ +- +-/* Event System */ +-typedef struct EVSYS_struct +-{ +- register8_t CH0MUX; /* Event Channel 0 Multiplexer */ +- register8_t CH1MUX; /* Event Channel 1 Multiplexer */ +- register8_t CH2MUX; /* Event Channel 2 Multiplexer */ +- register8_t CH3MUX; /* Event Channel 3 Multiplexer */ +- register8_t CH4MUX; /* Event Channel 4 Multiplexer */ +- register8_t CH5MUX; /* Event Channel 5 Multiplexer */ +- register8_t CH6MUX; /* Event Channel 6 Multiplexer */ +- register8_t CH7MUX; /* Event Channel 7 Multiplexer */ +- register8_t CH0CTRL; /* Channel 0 Control Register */ +- register8_t CH1CTRL; /* Channel 1 Control Register */ +- register8_t CH2CTRL; /* Channel 2 Control Register */ +- register8_t CH3CTRL; /* Channel 3 Control Register */ +- register8_t CH4CTRL; /* Channel 4 Control Register */ +- register8_t CH5CTRL; /* Channel 5 Control Register */ +- register8_t CH6CTRL; /* Channel 6 Control Register */ +- register8_t CH7CTRL; /* Channel 7 Control Register */ +- register8_t STROBE; /* Event Strobe */ +- register8_t DATA; /* Event Data */ +-} EVSYS_t; +- +-/* Quadrature Decoder Index Recognition Mode */ +-typedef enum EVSYS_QDIRM_enum +-{ +- EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ +- EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ +- EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ +- EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +-} EVSYS_QDIRM_t; +- +-/* Digital filter coefficient */ +-typedef enum EVSYS_DIGFILT_enum +-{ +- EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ +- EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ +- EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ +- EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ +- EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ +- EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ +- EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ +- EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +-} EVSYS_DIGFILT_t; +- +-/* Event Channel multiplexer input selection */ +-typedef enum EVSYS_CHMUX_enum +-{ +- EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ +- EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ +- EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ +- EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ +- EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ +- EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ +- EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ +- EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ +- EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ +- EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ +- EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ +- EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ +- EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ +- EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ +- EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ +- EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ +- EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ +- EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ +- EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ +- EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ +- EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ +- EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ +- EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ +- EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ +- EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ +- EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ +- EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ +- EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ +- EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ +- EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ +- EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ +- EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ +- EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ +- EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ +- EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ +- EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ +- EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ +- EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ +- EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ +- EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ +- EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ +- EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ +- EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ +- EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ +- EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ +- EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ +- EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ +- EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ +- EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ +- EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ +- EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ +- EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ +- EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ +- EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ +- EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ +- EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ +- EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ +- EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ +- EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ +- EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ +- EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ +- EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ +- EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ +- EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ +- EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ +- EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ +- EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ +- EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ +- EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ +- EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ +- EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ +- EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ +- EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ +- EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ +- EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ +- EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ +- EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ +- EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ +- EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ +- EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ +- EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ +- EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ +- EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ +- EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ +- EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ +- EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ +- EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ +- EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ +- EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ +- EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ +- EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ +- EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ +- EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ +- EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ +- EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ +- EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ +- EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ +- EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ +- EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ +- EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ +- EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ +- EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ +- EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ +- EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ +- EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ +- EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ +- EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ +- EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ +- EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ +- EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ +- EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +- EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ +- EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ +- EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ +- EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +-} EVSYS_CHMUX_t; +- +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Non-volatile Memory Controller */ +-typedef struct NVM_struct +-{ +- register8_t ADDR0; /* Address Register 0 */ +- register8_t ADDR1; /* Address Register 1 */ +- register8_t ADDR2; /* Address Register 2 */ +- register8_t reserved_0x03; +- register8_t DATA0; /* Data Register 0 */ +- register8_t DATA1; /* Data Register 1 */ +- register8_t DATA2; /* Data Register 2 */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t CMD; /* Command */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t INTCTRL; /* Interrupt Control */ +- register8_t reserved_0x0E; +- register8_t STATUS; /* Status */ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Lock Bits */ +-typedef struct NVM_LOCKBITS_struct +-{ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_LOCKBITS_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Fuses */ +-typedef struct NVM_FUSES_struct +-{ +- register8_t FUSEBYTE0; /* JTAG User ID */ +- register8_t FUSEBYTE1; /* Watchdog Configuration */ +- register8_t FUSEBYTE2; /* Reset Configuration */ +- register8_t reserved_0x03; +- register8_t FUSEBYTE4; /* Start-up Configuration */ +- register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +-} NVM_FUSES_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Production Signatures */ +-typedef struct NVM_PROD_SIGNATURES_struct +-{ +- register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ +- register8_t reserved_0x01; +- register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ +- register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ +- register8_t reserved_0x04; +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ +- register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ +- register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ +- register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ +- register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ +- register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t WAFNUM; /* Wafer Number */ +- register8_t reserved_0x11; +- register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ +- register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ +- register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ +- register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ +- register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ +- register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ +- register8_t reserved_0x26; +- register8_t reserved_0x27; +- register8_t reserved_0x28; +- register8_t reserved_0x29; +- register8_t reserved_0x2A; +- register8_t reserved_0x2B; +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ +- register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ +- register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ +- register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ +- register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ +- register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- register8_t reserved_0x36; +- register8_t reserved_0x37; +- register8_t reserved_0x38; +- register8_t reserved_0x39; +- register8_t reserved_0x3A; +- register8_t reserved_0x3B; +- register8_t reserved_0x3C; +- register8_t reserved_0x3D; +- register8_t reserved_0x3E; +-} NVM_PROD_SIGNATURES_t; +- +-/* NVM Command */ +-typedef enum NVM_CMD_enum +-{ +- NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ +- NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ +- NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ +- NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ +- NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ +- NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ +- NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ +- NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ +- NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ +- NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ +- NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ +- NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ +- NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ +- NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ +- NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ +- NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ +- NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ +- NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ +- NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ +- NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ +- NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ +- NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ +- NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ +- NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ +- NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ +- NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +-} NVM_CMD_t; +- +-/* SPM ready interrupt level */ +-typedef enum NVM_SPMLVL_enum +-{ +- NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ +- NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ +- NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +-} NVM_SPMLVL_t; +- +-/* EEPROM ready interrupt level */ +-typedef enum NVM_EELVL_enum +-{ +- NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ +- NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ +- NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +-} NVM_EELVL_t; +- +-/* Boot lock bits - boot setcion */ +-typedef enum NVM_BLBB_enum +-{ +- NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +- NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ +- NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ +- NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +-} NVM_BLBB_t; +- +-/* Boot lock bits - application section */ +-typedef enum NVM_BLBA_enum +-{ +- NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +- NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ +- NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ +- NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +-} NVM_BLBA_t; +- +-/* Boot lock bits - application table section */ +-typedef enum NVM_BLBAT_enum +-{ +- NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +- NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ +- NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ +- NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +-} NVM_BLBAT_t; +- +-/* Lock bits */ +-typedef enum NVM_LB_enum +-{ +- NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +- NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ +- NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +-} NVM_LB_t; +- +-/* Boot Loader Section Reset Vector */ +-typedef enum BOOTRST_enum +-{ +- BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ +- BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +-} BOOTRST_t; +- +-/* BOD operation */ +-typedef enum BOD_enum +-{ +- BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ +- BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ +- BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +-} BOD_t; +- +-/* Watchdog (Window) Timeout Period */ +-typedef enum WD_enum +-{ +- WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ +- WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ +- WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ +- WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ +- WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ +- WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ +- WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ +- WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ +- WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ +- WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ +- WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +-} WD_t; +- +-/* Start-up Time */ +-typedef enum SUT_enum +-{ +- SUT_0MS_gc = (0x03<<2), /* 0 ms */ +- SUT_4MS_gc = (0x01<<2), /* 4 ms */ +- SUT_64MS_gc = (0x00<<2), /* 64 ms */ +-} SUT_t; +- +-/* Brown Out Detection Voltage Level */ +-typedef enum BODLVL_enum +-{ +- BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ +- BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ +- BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ +- BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ +- BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ +- BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ +- BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ +-} BODLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-AC - Analog Comparator +--------------------------------------------------------------------------- +-*/ +- +-/* Analog Comparator */ +-typedef struct AC_struct +-{ +- register8_t AC0CTRL; /* Comparator 0 Control */ +- register8_t AC1CTRL; /* Comparator 1 Control */ +- register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ +- register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t WINCTRL; /* Window Mode Control */ +- register8_t STATUS; /* Status */ +-} AC_t; +- +-/* Interrupt mode */ +-typedef enum AC_INTMODE_enum +-{ +- AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ +- AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ +- AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +-} AC_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum AC_INTLVL_enum +-{ +- AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ +- AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ +- AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ +- AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +-} AC_INTLVL_t; +- +-/* Hysteresis mode selection */ +-typedef enum AC_HYSMODE_enum +-{ +- AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ +- AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ +- AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +-} AC_HYSMODE_t; +- +-/* Positive input multiplexer selection */ +-typedef enum AC_MUXPOS_enum +-{ +- AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ +- AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ +- AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ +- AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ +- AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ +- AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ +- AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +- AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +-} AC_MUXPOS_t; +- +-/* Negative input multiplexer selection */ +-typedef enum AC_MUXNEG_enum +-{ +- AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ +- AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ +- AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ +- AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ +- AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ +- AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ +- AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ +- AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +-} AC_MUXNEG_t; +- +-/* Windows interrupt mode */ +-typedef enum AC_WINTMODE_enum +-{ +- AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ +- AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ +- AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ +- AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +-} AC_WINTMODE_t; +- +-/* Window interrupt level */ +-typedef enum AC_WINTLVL_enum +-{ +- AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ +- AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ +- AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +-} AC_WINTLVL_t; +- +-/* Window mode state */ +-typedef enum AC_WSTATE_enum +-{ +- AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ +- AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ +- AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +-} AC_WSTATE_t; +- +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* ADC Channel */ +-typedef struct ADC_CH_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t MUXCTRL; /* MUX Control */ +- register8_t INTCTRL; /* Channel Interrupt Control */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- _WORDREGISTER(RES); /* Channel Result */ +- register8_t reserved_0x6; +- register8_t reserved_0x7; +-} ADC_CH_t; +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Analog-to-Digital Converter */ +-typedef struct ADC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t REFCTRL; /* Reference Control */ +- register8_t EVCTRL; /* Event Control */ +- register8_t PRESCALER; /* Clock Prescaler */ +- register8_t reserved_0x05; +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- _WORDREGISTER(CAL); /* Calibration Value */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- _WORDREGISTER(CH0RES); /* Channel 0 Result */ +- _WORDREGISTER(CH1RES); /* Channel 1 Result */ +- _WORDREGISTER(CH2RES); /* Channel 2 Result */ +- _WORDREGISTER(CH3RES); /* Channel 3 Result */ +- _WORDREGISTER(CMP); /* Compare Value */ +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- ADC_CH_t CH0; /* ADC Channel 0 */ +- ADC_CH_t CH1; /* ADC Channel 1 */ +- ADC_CH_t CH2; /* ADC Channel 2 */ +- ADC_CH_t CH3; /* ADC Channel 3 */ +-} ADC_t; +- +-/* Positive input multiplexer selection */ +-typedef enum ADC_CH_MUXPOS_enum +-{ +- ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ +- ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ +- ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ +- ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ +- ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ +- ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ +- ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ +- ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +-} ADC_CH_MUXPOS_t; +- +-/* Internal input multiplexer selections */ +-typedef enum ADC_CH_MUXINT_enum +-{ +- ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ +- ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ +- ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +- ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +-} ADC_CH_MUXINT_t; +- +-/* Negative input multiplexer selection */ +-typedef enum ADC_CH_MUXNEG_enum +-{ +- ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ +- ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ +- ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ +- ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ +- ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ +- ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ +- ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ +- ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +-} ADC_CH_MUXNEG_t; +- +-/* Input mode */ +-typedef enum ADC_CH_INPUTMODE_enum +-{ +- ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ +- ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ +- ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ +- ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +-} ADC_CH_INPUTMODE_t; +- +-/* Gain factor */ +-typedef enum ADC_CH_GAIN_enum +-{ +- ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ +- ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ +- ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ +- ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ +- ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ +- ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ +- ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ +-} ADC_CH_GAIN_t; +- +-/* Conversion result resolution */ +-typedef enum ADC_RESOLUTION_enum +-{ +- ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ +- ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ +- ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +-} ADC_RESOLUTION_t; +- +-/* Voltage reference selection */ +-typedef enum ADC_REFSEL_enum +-{ +- ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ +- ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ +- ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ +- ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +-} ADC_REFSEL_t; +- +-/* Channel sweep selection */ +-typedef enum ADC_SWEEP_enum +-{ +- ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ +- ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ +- ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ +- ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +-} ADC_SWEEP_t; +- +-/* Event channel input selection */ +-typedef enum ADC_EVSEL_enum +-{ +- ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ +- ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ +- ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ +- ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ +- ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ +- ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ +- ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ +- ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +-} ADC_EVSEL_t; +- +-/* Event action selection */ +-typedef enum ADC_EVACT_enum +-{ +- ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ +- ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ +- ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ +- ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ +- ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ +- ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ +- ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ +-} ADC_EVACT_t; +- +-/* Interupt mode */ +-typedef enum ADC_CH_INTMODE_enum +-{ +- ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ +- ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ +- ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +-} ADC_CH_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum ADC_CH_INTLVL_enum +-{ +- ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ +- ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ +- ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +-} ADC_CH_INTLVL_t; +- +-/* DMA request selection */ +-typedef enum ADC_DMASEL_enum +-{ +- ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ +- ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ +- ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ +- ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +-} ADC_DMASEL_t; +- +-/* Clock prescaler */ +-typedef enum ADC_PRESCALER_enum +-{ +- ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ +- ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ +- ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ +- ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ +- ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ +- ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ +- ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ +- ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +-} ADC_PRESCALER_t; +- +- +-/* +--------------------------------------------------------------------------- +-DAC - Digital/Analog Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Digital-to-Analog Converter */ +-typedef struct DAC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t EVCTRL; /* Event Input Control */ +- register8_t TIMCTRL; /* Timing Control */ +- register8_t STATUS; /* Status */ +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t GAINCAL; /* Gain Calibration */ +- register8_t OFFSETCAL; /* Offset Calibration */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- _WORDREGISTER(CH0DATA); /* Channel 0 Data */ +- _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +-} DAC_t; +- +-/* Output channel selection */ +-typedef enum DAC_CHSEL_enum +-{ +- DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ +- DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ +-} DAC_CHSEL_t; +- +-/* Reference voltage selection */ +-typedef enum DAC_REFSEL_enum +-{ +- DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ +- DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ +- DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ +- DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +-} DAC_REFSEL_t; +- +-/* Event channel selection */ +-typedef enum DAC_EVSEL_enum +-{ +- DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ +- DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ +- DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ +- DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ +- DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ +- DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ +- DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ +- DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +-} DAC_EVSEL_t; +- +-/* Conversion interval */ +-typedef enum DAC_CONINTVAL_enum +-{ +- DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ +- DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ +- DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ +- DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ +- DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ +- DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ +- DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ +- DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ +-} DAC_CONINTVAL_t; +- +-/* Refresh rate */ +-typedef enum DAC_REFRESH_enum +-{ +- DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ +- DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ +- DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ +- DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ +- DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ +- DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ +- DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ +- DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ +- DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ +- DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ +- DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ +- DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ +- DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ +- DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ +-} DAC_REFRESH_t; +- +- +-/* +--------------------------------------------------------------------------- +-RTC - Real-Time Clounter +--------------------------------------------------------------------------- +-*/ +- +-/* Real-Time Counter */ +-typedef struct RTC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t TEMP; /* Temporary register */ +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- _WORDREGISTER(CNT); /* Count Register */ +- _WORDREGISTER(PER); /* Period Register */ +- _WORDREGISTER(COMP); /* Compare Register */ +-} RTC_t; +- +-/* Prescaler Factor */ +-typedef enum RTC_PRESCALER_enum +-{ +- RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ +- RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ +- RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ +- RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ +- RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ +- RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ +- RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ +- RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +-} RTC_PRESCALER_t; +- +-/* Compare Interrupt level */ +-typedef enum RTC_COMPINTLVL_enum +-{ +- RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} RTC_COMPINTLVL_t; +- +-/* Overflow Interrupt level */ +-typedef enum RTC_OVFINTLVL_enum +-{ +- RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} RTC_OVFINTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* EBI Chip Select Module */ +-typedef struct EBI_CS_struct +-{ +- register8_t CTRLA; /* Chip Select Control Register A */ +- register8_t CTRLB; /* Chip Select Control Register B */ +- _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +-} EBI_CS_t; +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* External Bus Interface */ +-typedef struct EBI_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t SDRAMCTRLA; /* SDRAM Control Register A */ +- register8_t reserved_0x02; +- register8_t reserved_0x03; +- _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ +- _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ +- register8_t SDRAMCTRLB; /* SDRAM Control Register B */ +- register8_t SDRAMCTRLC; /* SDRAM Control Register C */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- EBI_CS_t CS0; /* Chip Select 0 */ +- EBI_CS_t CS1; /* Chip Select 1 */ +- EBI_CS_t CS2; /* Chip Select 2 */ +- EBI_CS_t CS3; /* Chip Select 3 */ +-} EBI_t; +- +-/* Chip Select adress space */ +-typedef enum EBI_CS_ASIZE_enum +-{ +- EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ +- EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ +- EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ +- EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ +- EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ +- EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ +- EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ +- EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ +- EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ +- EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ +- EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ +- EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ +- EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ +- EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ +- EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ +- EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ +- EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +-} EBI_CS_ASIZE_t; +- +-/* */ +-typedef enum EBI_CS_SRWS_enum +-{ +- EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_CS_SRWS_t; +- +-/* Chip Select address mode */ +-typedef enum EBI_CS_MODE_enum +-{ +- EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ +- EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ +- EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ +- EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +-} EBI_CS_MODE_t; +- +-/* Chip Select SDRAM mode */ +-typedef enum EBI_CS_SDMODE_enum +-{ +- EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ +- EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +-} EBI_CS_SDMODE_t; +- +-/* */ +-typedef enum EBI_SDDATAW_enum +-{ +- EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ +- EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +-} EBI_SDDATAW_t; +- +-/* */ +-typedef enum EBI_LPCMODE_enum +-{ +- EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ +- EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +-} EBI_LPCMODE_t; +- +-/* */ +-typedef enum EBI_SRMODE_enum +-{ +- EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ +- EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ +- EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ +- EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +-} EBI_SRMODE_t; +- +-/* */ +-typedef enum EBI_IFMODE_enum +-{ +- EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ +- EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ +- EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ +- EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +-} EBI_IFMODE_t; +- +-/* */ +-typedef enum EBI_SDCOL_enum +-{ +- EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ +- EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ +- EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ +- EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +-} EBI_SDCOL_t; +- +-/* */ +-typedef enum EBI_MRDLY_enum +-{ +- EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_MRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCYCDLY_enum +-{ +- EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ROWCYCDLY_t; +- +-/* */ +-typedef enum EBI_RPDLY_enum +-{ +- EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_RPDLY_t; +- +-/* */ +-typedef enum EBI_WRDLY_enum +-{ +- EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_WRDLY_t; +- +-/* */ +-typedef enum EBI_ESRDLY_enum +-{ +- EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ESRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCOLDLY_enum +-{ +- EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_ROWCOLDLY_t; +- +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_MASTER_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t STATUS; /* Status Register */ +- register8_t BAUD; /* Baurd Rate Control Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +-} TWI_MASTER_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_SLAVE_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t STATUS; /* Status Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +- register8_t ADDRMASK; /* Address Mask Register */ +-} TWI_SLAVE_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Two-Wire Interface */ +-typedef struct TWI_struct +-{ +- register8_t CTRL; /* TWI Common Control Register */ +- TWI_MASTER_t MASTER; /* TWI master module */ +- TWI_SLAVE_t SLAVE; /* TWI slave module */ +-} TWI_t; +- +-/* Master Interrupt Level */ +-typedef enum TWI_MASTER_INTLVL_enum +-{ +- TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_MASTER_INTLVL_t; +- +-/* Inactive Timeout */ +-typedef enum TWI_MASTER_TIMEOUT_enum +-{ +- TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ +- TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ +- TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ +- TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +-} TWI_MASTER_TIMEOUT_t; +- +-/* Master Command */ +-typedef enum TWI_MASTER_CMD_enum +-{ +- TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ +- TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ +- TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +-} TWI_MASTER_CMD_t; +- +-/* Master Bus State */ +-typedef enum TWI_MASTER_BUSSTATE_enum +-{ +- TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ +- TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ +- TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ +- TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +-} TWI_MASTER_BUSSTATE_t; +- +-/* Slave Interrupt Level */ +-typedef enum TWI_SLAVE_INTLVL_enum +-{ +- TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_SLAVE_INTLVL_t; +- +-/* Slave Command */ +-typedef enum TWI_SLAVE_CMD_enum +-{ +- TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ +- TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +-} TWI_SLAVE_CMD_t; +- +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O port Configuration */ +-typedef struct PORTCFG_struct +-{ +- register8_t MPCMASK; /* Multi-pin Configuration Mask */ +- register8_t reserved_0x01; +- register8_t VPCTRLA; /* Virtual Port Control Register A */ +- register8_t VPCTRLB; /* Virtual Port Control Register B */ +- register8_t CLKEVOUT; /* Clock and Event Out Register */ +-} PORTCFG_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* Virtual Port */ +-typedef struct VPORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t OUT; /* I/O Port Output */ +- register8_t IN; /* I/O Port Input */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +-} VPORT_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O Ports */ +-typedef struct PORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t DIRSET; /* I/O Port Data Direction Set */ +- register8_t DIRCLR; /* I/O Port Data Direction Clear */ +- register8_t DIRTGL; /* I/O Port Data Direction Toggle */ +- register8_t OUT; /* I/O Port Output */ +- register8_t OUTSET; /* I/O Port Output Set */ +- register8_t OUTCLR; /* I/O Port Output Clear */ +- register8_t OUTTGL; /* I/O Port Output Toggle */ +- register8_t IN; /* I/O port Input */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INT0MASK; /* Port Interrupt 0 Mask */ +- register8_t INT1MASK; /* Port Interrupt 1 Mask */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t PIN0CTRL; /* Pin 0 Control Register */ +- register8_t PIN1CTRL; /* Pin 1 Control Register */ +- register8_t PIN2CTRL; /* Pin 2 Control Register */ +- register8_t PIN3CTRL; /* Pin 3 Control Register */ +- register8_t PIN4CTRL; /* Pin 4 Control Register */ +- register8_t PIN5CTRL; /* Pin 5 Control Register */ +- register8_t PIN6CTRL; /* Pin 6 Control Register */ +- register8_t PIN7CTRL; /* Pin 7 Control Register */ +-} PORT_t; +- +-/* Virtual Port 0 Mapping */ +-typedef enum PORTCFG_VP0MAP_enum +-{ +- PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP0MAP_t; +- +-/* Virtual Port 1 Mapping */ +-typedef enum PORTCFG_VP1MAP_enum +-{ +- PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP1MAP_t; +- +-/* Virtual Port 2 Mapping */ +-typedef enum PORTCFG_VP2MAP_enum +-{ +- PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP2MAP_t; +- +-/* Virtual Port 3 Mapping */ +-typedef enum PORTCFG_VP3MAP_enum +-{ +- PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP3MAP_t; +- +-/* Clock Output Port */ +-typedef enum PORTCFG_CLKOUT_enum +-{ +- PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ +- PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ +- PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ +- PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +-} PORTCFG_CLKOUT_t; +- +-/* Event Output Port */ +-typedef enum PORTCFG_EVOUT_enum +-{ +- PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ +- PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ +- PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ +- PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +-} PORTCFG_EVOUT_t; +- +-/* Port Interrupt 0 Level */ +-typedef enum PORT_INT0LVL_enum +-{ +- PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ +- PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ +- PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +-} PORT_INT0LVL_t; +- +-/* Port Interrupt 1 Level */ +-typedef enum PORT_INT1LVL_enum +-{ +- PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ +- PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ +- PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +-} PORT_INT1LVL_t; +- +-/* Output/Pull Configuration */ +-typedef enum PORT_OPC_enum +-{ +- PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ +- PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ +- PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ +- PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ +- PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ +- PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ +- PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ +- PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +-} PORT_OPC_t; +- +-/* Input/Sense Configuration */ +-typedef enum PORT_ISC_enum +-{ +- PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ +- PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ +- PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ +- PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ +- PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +-} PORT_ISC_t; +- +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 0 */ +-typedef struct TC0_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- _WORDREGISTER(CCC); /* Compare or Capture C */ +- _WORDREGISTER(CCD); /* Compare or Capture D */ +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +- _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ +- _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +-} TC0_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 1 */ +-typedef struct TC1_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t reserved_0x2E; +- register8_t reserved_0x2F; +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +-} TC1_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* Advanced Waveform Extension */ +-typedef struct AWEX_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t FDEMASK; /* Fault Detection Event Mask */ +- register8_t FDCTRL; /* Fault Detection Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x05; +- register8_t DTBOTH; /* Dead Time Both Sides */ +- register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ +- register8_t DTLS; /* Dead Time Low Side */ +- register8_t DTHS; /* Dead Time High Side */ +- register8_t DTLSBUF; /* Dead Time Low Side Buffer */ +- register8_t DTHSBUF; /* Dead Time High Side Buffer */ +- register8_t OUTOVEN; /* Output Override Enable */ +-} AWEX_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* High-Resolution Extension */ +-typedef struct HIRES_struct +-{ +- register8_t CTRLA; /* Control Register */ +-} HIRES_t; +- +-/* Clock Selection */ +-typedef enum TC_CLKSEL_enum +-{ +- TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ +- TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ +- TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ +- TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ +- TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ +- TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ +- TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ +- TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ +- TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_CLKSEL_t; +- +-/* Waveform Generation Mode */ +-typedef enum TC_WGMODE_enum +-{ +- TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ +- TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ +- TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ +- TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ +- TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ +- TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +-} TC_WGMODE_t; +- +-/* Event Action */ +-typedef enum TC_EVACT_enum +-{ +- TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ +- TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ +- TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ +- TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ +- TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ +- TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */ +- TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +-} TC_EVACT_t; +- +-/* Event Selection */ +-typedef enum TC_EVSEL_enum +-{ +- TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_EVSEL_t; +- +-/* Error Interrupt Level */ +-typedef enum TC_ERRINTLVL_enum +-{ +- TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_ERRINTLVL_t; +- +-/* Overflow Interrupt Level */ +-typedef enum TC_OVFINTLVL_enum +-{ +- TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_OVFINTLVL_t; +- +-/* Compare or Capture D Interrupt Level */ +-typedef enum TC_CCDINTLVL_enum +-{ +- TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TC_CCDINTLVL_t; +- +-/* Compare or Capture C Interrupt Level */ +-typedef enum TC_CCCINTLVL_enum +-{ +- TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} TC_CCCINTLVL_t; +- +-/* Compare or Capture B Interrupt Level */ +-typedef enum TC_CCBINTLVL_enum +-{ +- TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_CCBINTLVL_t; +- +-/* Compare or Capture A Interrupt Level */ +-typedef enum TC_CCAINTLVL_enum +-{ +- TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_CCAINTLVL_t; +- +-/* Timer/Counter Command */ +-typedef enum TC_CMD_enum +-{ +- TC_CMD_NONE_gc = (0x00<<2), /* No Command */ +- TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ +- TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ +- TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +-} TC_CMD_t; +- +-/* Fault Detect Action */ +-typedef enum AWEX_FDACT_enum +-{ +- AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ +- AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ +- AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +-} AWEX_FDACT_t; +- +-/* High Resolution Enable */ +-typedef enum HIRES_HREN_enum +-{ +- HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ +- HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ +- HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ +- HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +-} HIRES_HREN_t; +- +- +-/* +--------------------------------------------------------------------------- +-USART - Universal Asynchronous Receiver-Transmitter +--------------------------------------------------------------------------- +-*/ +- +-/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +-typedef struct USART_struct +-{ +- register8_t DATA; /* Data Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x02; +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t BAUDCTRLA; /* Baud Rate Control Register A */ +- register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +-} USART_t; +- +-/* Receive Complete Interrupt level */ +-typedef enum USART_RXCINTLVL_enum +-{ +- USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} USART_RXCINTLVL_t; +- +-/* Transmit Complete Interrupt level */ +-typedef enum USART_TXCINTLVL_enum +-{ +- USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} USART_TXCINTLVL_t; +- +-/* Data Register Empty Interrupt level */ +-typedef enum USART_DREINTLVL_enum +-{ +- USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} USART_DREINTLVL_t; +- +-/* Character Size */ +-typedef enum USART_CHSIZE_enum +-{ +- USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ +- USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ +- USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ +- USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ +- USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +-} USART_CHSIZE_t; +- +-/* Communication Mode */ +-typedef enum USART_CMODE_enum +-{ +- USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ +- USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ +- USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ +- USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +-} USART_CMODE_t; +- +-/* Parity Mode */ +-typedef enum USART_PMODE_enum +-{ +- USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ +- USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ +- USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +-} USART_PMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-SPI - Serial Peripheral Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Serial Peripheral Interface */ +-typedef struct SPI_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t DATA; /* Data Register */ +-} SPI_t; +- +-/* SPI Mode */ +-typedef enum SPI_MODE_enum +-{ +- SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ +- SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ +- SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ +- SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +-} SPI_MODE_t; +- +-/* Prescaler setting */ +-typedef enum SPI_PRESCALER_enum +-{ +- SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ +- SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ +- SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ +- SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +-} SPI_PRESCALER_t; +- +-/* Interrupt level */ +-typedef enum SPI_INTLVL_enum +-{ +- SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} SPI_INTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-IRCOM - IR Communication Module +--------------------------------------------------------------------------- +-*/ +- +-/* IR Communication Module */ +-typedef struct IRCOM_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ +- register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +-} IRCOM_t; +- +-/* Event channel selection */ +-typedef enum IRDA_EVSEL_enum +-{ +- IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ +- IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ +- IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ +- IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +- IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ +- IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ +- IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ +- IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +-} IRDA_EVSEL_t; +- +- +-/* +--------------------------------------------------------------------------- +-AES - AES Module +--------------------------------------------------------------------------- +-*/ +- +-/* AES Module */ +-typedef struct AES_struct +-{ +- register8_t CTRL; /* AES Control Register */ +- register8_t STATUS; /* AES Status Register */ +- register8_t STATE; /* AES State Register */ +- register8_t KEY; /* AES Key Register */ +- register8_t INTCTRL; /* AES Interrupt Control Register */ +-} AES_t; +- +-/* Interrupt level */ +-typedef enum AES_INTLVL_enum +-{ +- AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} AES_INTLVL_t; +- +- +- +-/* +-========================================================================== +-IO Module Instances. Mapped to memory. +-========================================================================== +-*/ +- +-#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +-#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +-#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +-#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +-#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +-#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +-#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +-#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +-#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +-#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +-#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +-#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +-#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +-#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +-#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +-#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +-#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ +-#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +-#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +-#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +-#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +-#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ +-#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ +-#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +-#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ +-#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +-#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +-#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ +-#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +-#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +-#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +-#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +-#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +-#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ +-#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +-#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +-#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +-#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +-#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +-#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +-#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ +-#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +-#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +-#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +-#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ +-#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ +-#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +-#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ +-#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +-#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +-#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ +-#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ +-#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ +-#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ +-#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ +-#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ +-#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ +-#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ +-#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ +-#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ +-#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ +- +- +-#endif /* !defined (__ASSEMBLER__) */ +- +- +-/* ========== Flattened fully qualified IO register names ========== */ +- +-/* GPIO - General Purpose IO Registers */ +-#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +-#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +-#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +-#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +-#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +-#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +-#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +-#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +-#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +-#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +-#define GPIO_GPIORA _SFR_MEM8(0x000A) +-#define GPIO_GPIORB _SFR_MEM8(0x000B) +-#define GPIO_GPIORC _SFR_MEM8(0x000C) +-#define GPIO_GPIORD _SFR_MEM8(0x000D) +-#define GPIO_GPIORE _SFR_MEM8(0x000E) +-#define GPIO_GPIORF _SFR_MEM8(0x000F) +- +-/* Deprecated */ +-#define GPIO_GPIO0 _SFR_MEM8(0x0000) +-#define GPIO_GPIO1 _SFR_MEM8(0x0001) +-#define GPIO_GPIO2 _SFR_MEM8(0x0002) +-#define GPIO_GPIO3 _SFR_MEM8(0x0003) +-#define GPIO_GPIO4 _SFR_MEM8(0x0004) +-#define GPIO_GPIO5 _SFR_MEM8(0x0005) +-#define GPIO_GPIO6 _SFR_MEM8(0x0006) +-#define GPIO_GPIO7 _SFR_MEM8(0x0007) +-#define GPIO_GPIO8 _SFR_MEM8(0x0008) +-#define GPIO_GPIO9 _SFR_MEM8(0x0009) +-#define GPIO_GPIOA _SFR_MEM8(0x000A) +-#define GPIO_GPIOB _SFR_MEM8(0x000B) +-#define GPIO_GPIOC _SFR_MEM8(0x000C) +-#define GPIO_GPIOD _SFR_MEM8(0x000D) +-#define GPIO_GPIOE _SFR_MEM8(0x000E) +-#define GPIO_GPIOF _SFR_MEM8(0x000F) +- +-/* VPORT0 - Virtual Port 0 */ +-#define VPORT0_DIR _SFR_MEM8(0x0010) +-#define VPORT0_OUT _SFR_MEM8(0x0011) +-#define VPORT0_IN _SFR_MEM8(0x0012) +-#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) +- +-/* VPORT1 - Virtual Port 1 */ +-#define VPORT1_DIR _SFR_MEM8(0x0014) +-#define VPORT1_OUT _SFR_MEM8(0x0015) +-#define VPORT1_IN _SFR_MEM8(0x0016) +-#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) +- +-/* VPORT2 - Virtual Port 2 */ +-#define VPORT2_DIR _SFR_MEM8(0x0018) +-#define VPORT2_OUT _SFR_MEM8(0x0019) +-#define VPORT2_IN _SFR_MEM8(0x001A) +-#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) +- +-/* VPORT3 - Virtual Port 3 */ +-#define VPORT3_DIR _SFR_MEM8(0x001C) +-#define VPORT3_OUT _SFR_MEM8(0x001D) +-#define VPORT3_IN _SFR_MEM8(0x001E) +-#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) +- +-/* OCD - On-Chip Debug System */ +-#define OCD_OCDR0 _SFR_MEM8(0x002E) +-#define OCD_OCDR1 _SFR_MEM8(0x002F) +- +-/* CPU - CPU Registers */ +-#define CPU_CCP _SFR_MEM8(0x0034) +-#define CPU_RAMPD _SFR_MEM8(0x0038) +-#define CPU_RAMPX _SFR_MEM8(0x0039) +-#define CPU_RAMPY _SFR_MEM8(0x003A) +-#define CPU_RAMPZ _SFR_MEM8(0x003B) +-#define CPU_EIND _SFR_MEM8(0x003C) +-#define CPU_SPL _SFR_MEM8(0x003D) +-#define CPU_SPH _SFR_MEM8(0x003E) +-#define CPU_SREG _SFR_MEM8(0x003F) +- +-/* CLK - Clock System */ +-#define CLK_CTRL _SFR_MEM8(0x0040) +-#define CLK_PSCTRL _SFR_MEM8(0x0041) +-#define CLK_LOCK _SFR_MEM8(0x0042) +-#define CLK_RTCCTRL _SFR_MEM8(0x0043) +- +-/* SLEEP - Sleep Controller */ +-#define SLEEP_CTRL _SFR_MEM8(0x0048) +- +-/* OSC - Oscillator Control */ +-#define OSC_CTRL _SFR_MEM8(0x0050) +-#define OSC_STATUS _SFR_MEM8(0x0051) +-#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +-#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +-#define OSC_RC32KCAL _SFR_MEM8(0x0054) +-#define OSC_PLLCTRL _SFR_MEM8(0x0055) +-#define OSC_DFLLCTRL _SFR_MEM8(0x0056) +- +-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +-#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +-#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +-#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +-#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +-#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +-#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) +- +-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +-#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +-#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +-#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +-#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +-#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +-#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) +- +-/* PR - Power Reduction */ +-#define PR_PRGEN _SFR_MEM8(0x0070) +-#define PR_PRPA _SFR_MEM8(0x0071) +-#define PR_PRPB _SFR_MEM8(0x0072) +-#define PR_PRPC _SFR_MEM8(0x0073) +-#define PR_PRPD _SFR_MEM8(0x0074) +-#define PR_PRPE _SFR_MEM8(0x0075) +-#define PR_PRPF _SFR_MEM8(0x0076) +- +-/* RST - Reset Controller */ +-#define RST_STATUS _SFR_MEM8(0x0078) +-#define RST_CTRL _SFR_MEM8(0x0079) +- +-/* WDT - Watch-Dog Timer */ +-#define WDT_CTRL _SFR_MEM8(0x0080) +-#define WDT_WINCTRL _SFR_MEM8(0x0081) +-#define WDT_STATUS _SFR_MEM8(0x0082) +- +-/* MCU - MCU Control */ +-#define MCU_DEVID0 _SFR_MEM8(0x0090) +-#define MCU_DEVID1 _SFR_MEM8(0x0091) +-#define MCU_DEVID2 _SFR_MEM8(0x0092) +-#define MCU_REVID _SFR_MEM8(0x0093) +-#define MCU_JTAGUID _SFR_MEM8(0x0094) +-#define MCU_MCUCR _SFR_MEM8(0x0096) +-#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +-#define MCU_AWEXLOCK _SFR_MEM8(0x0099) +- +-/* PMIC - Programmable Interrupt Controller */ +-#define PMIC_STATUS _SFR_MEM8(0x00A0) +-#define PMIC_INTPRI _SFR_MEM8(0x00A1) +-#define PMIC_CTRL _SFR_MEM8(0x00A2) +- +-/* PORTCFG - Port Configuration */ +-#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +-#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +-#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +-#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +- +-/* AES - AES Crypto Module */ +-#define AES_CTRL _SFR_MEM8(0x00C0) +-#define AES_STATUS _SFR_MEM8(0x00C1) +-#define AES_STATE _SFR_MEM8(0x00C2) +-#define AES_KEY _SFR_MEM8(0x00C3) +-#define AES_INTCTRL _SFR_MEM8(0x00C4) +- +-/* DMA - DMA Controller */ +-#define DMA_CTRL _SFR_MEM8(0x0100) +-#define DMA_INTFLAGS _SFR_MEM8(0x0103) +-#define DMA_STATUS _SFR_MEM8(0x0104) +-#define DMA_TEMP _SFR_MEM16(0x0106) +-#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +-#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +-#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +-#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +-#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +-#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +-#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +-#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +-#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +-#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +-#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +-#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +-#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +-#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +-#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +-#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +-#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +-#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +-#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +-#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +-#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +-#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +-#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +-#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +-#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +-#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +-#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +-#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +-#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +-#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +-#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +-#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +-#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +-#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +-#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +-#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +-#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +-#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +-#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +-#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +-#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +-#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +-#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +-#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +-#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +-#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +-#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +-#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) +- +-/* EVSYS - Event System */ +-#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +-#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +-#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +-#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +-#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +-#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +-#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +-#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +-#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +-#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +-#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +-#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +-#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +-#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +-#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +-#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +-#define EVSYS_STROBE _SFR_MEM8(0x0190) +-#define EVSYS_DATA _SFR_MEM8(0x0191) +- +-/* NVM - Non Volatile Memory Controller */ +-#define NVM_ADDR0 _SFR_MEM8(0x01C0) +-#define NVM_ADDR1 _SFR_MEM8(0x01C1) +-#define NVM_ADDR2 _SFR_MEM8(0x01C2) +-#define NVM_DATA0 _SFR_MEM8(0x01C4) +-#define NVM_DATA1 _SFR_MEM8(0x01C5) +-#define NVM_DATA2 _SFR_MEM8(0x01C6) +-#define NVM_CMD _SFR_MEM8(0x01CA) +-#define NVM_CTRLA _SFR_MEM8(0x01CB) +-#define NVM_CTRLB _SFR_MEM8(0x01CC) +-#define NVM_INTCTRL _SFR_MEM8(0x01CD) +-#define NVM_STATUS _SFR_MEM8(0x01CF) +-#define NVM_LOCKBITS _SFR_MEM8(0x01D0) +- +-/* ADCA - Analog to Digital Converter A */ +-#define ADCA_CTRLA _SFR_MEM8(0x0200) +-#define ADCA_CTRLB _SFR_MEM8(0x0201) +-#define ADCA_REFCTRL _SFR_MEM8(0x0202) +-#define ADCA_EVCTRL _SFR_MEM8(0x0203) +-#define ADCA_PRESCALER _SFR_MEM8(0x0204) +-#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +-#define ADCA_CAL _SFR_MEM16(0x020C) +-#define ADCA_CH0RES _SFR_MEM16(0x0210) +-#define ADCA_CH1RES _SFR_MEM16(0x0212) +-#define ADCA_CH2RES _SFR_MEM16(0x0214) +-#define ADCA_CH3RES _SFR_MEM16(0x0216) +-#define ADCA_CMP _SFR_MEM16(0x0218) +-#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +-#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +-#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +-#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +-#define ADCA_CH0_RES _SFR_MEM16(0x0224) +-#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +-#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +-#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +-#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +-#define ADCA_CH1_RES _SFR_MEM16(0x022C) +-#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +-#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +-#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +-#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +-#define ADCA_CH2_RES _SFR_MEM16(0x0234) +-#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +-#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +-#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +-#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +-#define ADCA_CH3_RES _SFR_MEM16(0x023C) +- +-/* ADCB - Analog to Digital Converter B */ +-#define ADCB_CTRLA _SFR_MEM8(0x0240) +-#define ADCB_CTRLB _SFR_MEM8(0x0241) +-#define ADCB_REFCTRL _SFR_MEM8(0x0242) +-#define ADCB_EVCTRL _SFR_MEM8(0x0243) +-#define ADCB_PRESCALER _SFR_MEM8(0x0244) +-#define ADCB_INTFLAGS _SFR_MEM8(0x0246) +-#define ADCB_CAL _SFR_MEM16(0x024C) +-#define ADCB_CH0RES _SFR_MEM16(0x0250) +-#define ADCB_CH1RES _SFR_MEM16(0x0252) +-#define ADCB_CH2RES _SFR_MEM16(0x0254) +-#define ADCB_CH3RES _SFR_MEM16(0x0256) +-#define ADCB_CMP _SFR_MEM16(0x0258) +-#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) +-#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) +-#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) +-#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) +-#define ADCB_CH0_RES _SFR_MEM16(0x0264) +-#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) +-#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) +-#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) +-#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) +-#define ADCB_CH1_RES _SFR_MEM16(0x026C) +-#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) +-#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) +-#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) +-#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) +-#define ADCB_CH2_RES _SFR_MEM16(0x0274) +-#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) +-#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) +-#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) +-#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) +-#define ADCB_CH3_RES _SFR_MEM16(0x027C) +- +-/* DACB - Digital to Analog Converter B */ +-#define DACB_CTRLA _SFR_MEM8(0x0320) +-#define DACB_CTRLB _SFR_MEM8(0x0321) +-#define DACB_CTRLC _SFR_MEM8(0x0322) +-#define DACB_EVCTRL _SFR_MEM8(0x0323) +-#define DACB_TIMCTRL _SFR_MEM8(0x0324) +-#define DACB_STATUS _SFR_MEM8(0x0325) +-#define DACB_GAINCAL _SFR_MEM8(0x0328) +-#define DACB_OFFSETCAL _SFR_MEM8(0x0329) +-#define DACB_CH0DATA _SFR_MEM16(0x0338) +-#define DACB_CH1DATA _SFR_MEM16(0x033A) +- +-/* ACA - Analog Comparator A */ +-#define ACA_AC0CTRL _SFR_MEM8(0x0380) +-#define ACA_AC1CTRL _SFR_MEM8(0x0381) +-#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +-#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +-#define ACA_CTRLA _SFR_MEM8(0x0384) +-#define ACA_CTRLB _SFR_MEM8(0x0385) +-#define ACA_WINCTRL _SFR_MEM8(0x0386) +-#define ACA_STATUS _SFR_MEM8(0x0387) +- +-/* ACB - Analog Comparator B */ +-#define ACB_AC0CTRL _SFR_MEM8(0x0390) +-#define ACB_AC1CTRL _SFR_MEM8(0x0391) +-#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +-#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +-#define ACB_CTRLA _SFR_MEM8(0x0394) +-#define ACB_CTRLB _SFR_MEM8(0x0395) +-#define ACB_WINCTRL _SFR_MEM8(0x0396) +-#define ACB_STATUS _SFR_MEM8(0x0397) +- +-/* RTC - Real-Time Counter */ +-#define RTC_CTRL _SFR_MEM8(0x0400) +-#define RTC_STATUS _SFR_MEM8(0x0401) +-#define RTC_INTCTRL _SFR_MEM8(0x0402) +-#define RTC_INTFLAGS _SFR_MEM8(0x0403) +-#define RTC_TEMP _SFR_MEM8(0x0404) +-#define RTC_CNT _SFR_MEM16(0x0408) +-#define RTC_PER _SFR_MEM16(0x040A) +-#define RTC_COMP _SFR_MEM16(0x040C) +- +-/* TWIC - Two-Wire Interface C */ +-#define TWIC_CTRL _SFR_MEM8(0x0480) +-#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +-#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +-#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +-#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +-#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +-#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +-#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +-#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +-#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +-#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +-#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +-#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +-#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) +- +-/* TWIE - Two-Wire Interface E */ +-#define TWIE_CTRL _SFR_MEM8(0x04A0) +-#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +-#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +-#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +-#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +-#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +-#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +-#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +-#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +-#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +-#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +-#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +-#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +-#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) +- +-/* PORTA - Port A */ +-#define PORTA_DIR _SFR_MEM8(0x0600) +-#define PORTA_DIRSET _SFR_MEM8(0x0601) +-#define PORTA_DIRCLR _SFR_MEM8(0x0602) +-#define PORTA_DIRTGL _SFR_MEM8(0x0603) +-#define PORTA_OUT _SFR_MEM8(0x0604) +-#define PORTA_OUTSET _SFR_MEM8(0x0605) +-#define PORTA_OUTCLR _SFR_MEM8(0x0606) +-#define PORTA_OUTTGL _SFR_MEM8(0x0607) +-#define PORTA_IN _SFR_MEM8(0x0608) +-#define PORTA_INTCTRL _SFR_MEM8(0x0609) +-#define PORTA_INT0MASK _SFR_MEM8(0x060A) +-#define PORTA_INT1MASK _SFR_MEM8(0x060B) +-#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +-#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +-#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +-#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +-#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +-#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +-#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +-#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +-#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) +- +-/* PORTB - Port B */ +-#define PORTB_DIR _SFR_MEM8(0x0620) +-#define PORTB_DIRSET _SFR_MEM8(0x0621) +-#define PORTB_DIRCLR _SFR_MEM8(0x0622) +-#define PORTB_DIRTGL _SFR_MEM8(0x0623) +-#define PORTB_OUT _SFR_MEM8(0x0624) +-#define PORTB_OUTSET _SFR_MEM8(0x0625) +-#define PORTB_OUTCLR _SFR_MEM8(0x0626) +-#define PORTB_OUTTGL _SFR_MEM8(0x0627) +-#define PORTB_IN _SFR_MEM8(0x0628) +-#define PORTB_INTCTRL _SFR_MEM8(0x0629) +-#define PORTB_INT0MASK _SFR_MEM8(0x062A) +-#define PORTB_INT1MASK _SFR_MEM8(0x062B) +-#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +-#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +-#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +-#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +-#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +-#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +-#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +-#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +-#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) +- +-/* PORTC - Port C */ +-#define PORTC_DIR _SFR_MEM8(0x0640) +-#define PORTC_DIRSET _SFR_MEM8(0x0641) +-#define PORTC_DIRCLR _SFR_MEM8(0x0642) +-#define PORTC_DIRTGL _SFR_MEM8(0x0643) +-#define PORTC_OUT _SFR_MEM8(0x0644) +-#define PORTC_OUTSET _SFR_MEM8(0x0645) +-#define PORTC_OUTCLR _SFR_MEM8(0x0646) +-#define PORTC_OUTTGL _SFR_MEM8(0x0647) +-#define PORTC_IN _SFR_MEM8(0x0648) +-#define PORTC_INTCTRL _SFR_MEM8(0x0649) +-#define PORTC_INT0MASK _SFR_MEM8(0x064A) +-#define PORTC_INT1MASK _SFR_MEM8(0x064B) +-#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +-#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +-#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +-#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +-#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +-#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +-#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +-#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +-#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) +- +-/* PORTD - Port D */ +-#define PORTD_DIR _SFR_MEM8(0x0660) +-#define PORTD_DIRSET _SFR_MEM8(0x0661) +-#define PORTD_DIRCLR _SFR_MEM8(0x0662) +-#define PORTD_DIRTGL _SFR_MEM8(0x0663) +-#define PORTD_OUT _SFR_MEM8(0x0664) +-#define PORTD_OUTSET _SFR_MEM8(0x0665) +-#define PORTD_OUTCLR _SFR_MEM8(0x0666) +-#define PORTD_OUTTGL _SFR_MEM8(0x0667) +-#define PORTD_IN _SFR_MEM8(0x0668) +-#define PORTD_INTCTRL _SFR_MEM8(0x0669) +-#define PORTD_INT0MASK _SFR_MEM8(0x066A) +-#define PORTD_INT1MASK _SFR_MEM8(0x066B) +-#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +-#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +-#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +-#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +-#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +-#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +-#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +-#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +-#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) +- +-/* PORTE - Port E */ +-#define PORTE_DIR _SFR_MEM8(0x0680) +-#define PORTE_DIRSET _SFR_MEM8(0x0681) +-#define PORTE_DIRCLR _SFR_MEM8(0x0682) +-#define PORTE_DIRTGL _SFR_MEM8(0x0683) +-#define PORTE_OUT _SFR_MEM8(0x0684) +-#define PORTE_OUTSET _SFR_MEM8(0x0685) +-#define PORTE_OUTCLR _SFR_MEM8(0x0686) +-#define PORTE_OUTTGL _SFR_MEM8(0x0687) +-#define PORTE_IN _SFR_MEM8(0x0688) +-#define PORTE_INTCTRL _SFR_MEM8(0x0689) +-#define PORTE_INT0MASK _SFR_MEM8(0x068A) +-#define PORTE_INT1MASK _SFR_MEM8(0x068B) +-#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +-#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +-#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +-#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +-#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +-#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +-#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +-#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +-#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) +- +-/* PORTF - Port F */ +-#define PORTF_DIR _SFR_MEM8(0x06A0) +-#define PORTF_DIRSET _SFR_MEM8(0x06A1) +-#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +-#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +-#define PORTF_OUT _SFR_MEM8(0x06A4) +-#define PORTF_OUTSET _SFR_MEM8(0x06A5) +-#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +-#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +-#define PORTF_IN _SFR_MEM8(0x06A8) +-#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +-#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +-#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +-#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +-#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +-#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +-#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +-#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +-#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +-#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +-#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +-#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) +- +-/* PORTR - Port R */ +-#define PORTR_DIR _SFR_MEM8(0x07E0) +-#define PORTR_DIRSET _SFR_MEM8(0x07E1) +-#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +-#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +-#define PORTR_OUT _SFR_MEM8(0x07E4) +-#define PORTR_OUTSET _SFR_MEM8(0x07E5) +-#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +-#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +-#define PORTR_IN _SFR_MEM8(0x07E8) +-#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +-#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +-#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +-#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +-#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +-#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +-#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +-#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +-#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +-#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +-#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +-#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) +- +-/* TCC0 - Timer/Counter C0 */ +-#define TCC0_CTRLA _SFR_MEM8(0x0800) +-#define TCC0_CTRLB _SFR_MEM8(0x0801) +-#define TCC0_CTRLC _SFR_MEM8(0x0802) +-#define TCC0_CTRLD _SFR_MEM8(0x0803) +-#define TCC0_CTRLE _SFR_MEM8(0x0804) +-#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +-#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +-#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +-#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +-#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +-#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +-#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +-#define TCC0_TEMP _SFR_MEM8(0x080F) +-#define TCC0_CNT _SFR_MEM16(0x0820) +-#define TCC0_PER _SFR_MEM16(0x0826) +-#define TCC0_CCA _SFR_MEM16(0x0828) +-#define TCC0_CCB _SFR_MEM16(0x082A) +-#define TCC0_CCC _SFR_MEM16(0x082C) +-#define TCC0_CCD _SFR_MEM16(0x082E) +-#define TCC0_PERBUF _SFR_MEM16(0x0836) +-#define TCC0_CCABUF _SFR_MEM16(0x0838) +-#define TCC0_CCBBUF _SFR_MEM16(0x083A) +-#define TCC0_CCCBUF _SFR_MEM16(0x083C) +-#define TCC0_CCDBUF _SFR_MEM16(0x083E) +- +-/* TCC1 - Timer/Counter C1 */ +-#define TCC1_CTRLA _SFR_MEM8(0x0840) +-#define TCC1_CTRLB _SFR_MEM8(0x0841) +-#define TCC1_CTRLC _SFR_MEM8(0x0842) +-#define TCC1_CTRLD _SFR_MEM8(0x0843) +-#define TCC1_CTRLE _SFR_MEM8(0x0844) +-#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +-#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +-#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +-#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +-#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +-#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +-#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +-#define TCC1_TEMP _SFR_MEM8(0x084F) +-#define TCC1_CNT _SFR_MEM16(0x0860) +-#define TCC1_PER _SFR_MEM16(0x0866) +-#define TCC1_CCA _SFR_MEM16(0x0868) +-#define TCC1_CCB _SFR_MEM16(0x086A) +-#define TCC1_PERBUF _SFR_MEM16(0x0876) +-#define TCC1_CCABUF _SFR_MEM16(0x0878) +-#define TCC1_CCBBUF _SFR_MEM16(0x087A) +- +-/* AWEXC - Advanced Waveform Extension C */ +-#define AWEXC_CTRL _SFR_MEM8(0x0880) +-#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +-#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +-#define AWEXC_STATUS _SFR_MEM8(0x0884) +-#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +-#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +-#define AWEXC_DTLS _SFR_MEM8(0x0888) +-#define AWEXC_DTHS _SFR_MEM8(0x0889) +-#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +-#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +-#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) +- +-/* HIRESC - High-Resolution Extension C */ +-#define HIRESC_CTRLA _SFR_MEM8(0x0890) +- +-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +-#define USARTC0_DATA _SFR_MEM8(0x08A0) +-#define USARTC0_STATUS _SFR_MEM8(0x08A1) +-#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +-#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +-#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +-#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +-#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) +- +-/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ +-#define USARTC1_DATA _SFR_MEM8(0x08B0) +-#define USARTC1_STATUS _SFR_MEM8(0x08B1) +-#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +-#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +-#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +-#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +-#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) +- +-/* SPIC - Serial Peripheral Interface C */ +-#define SPIC_CTRL _SFR_MEM8(0x08C0) +-#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +-#define SPIC_STATUS _SFR_MEM8(0x08C2) +-#define SPIC_DATA _SFR_MEM8(0x08C3) +- +-/* IRCOM - IR Communication Module */ +-#define IRCOM_CTRL _SFR_MEM8(0x08F8) +-#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +-#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) +- +-/* TCD0 - Timer/Counter D0 */ +-#define TCD0_CTRLA _SFR_MEM8(0x0900) +-#define TCD0_CTRLB _SFR_MEM8(0x0901) +-#define TCD0_CTRLC _SFR_MEM8(0x0902) +-#define TCD0_CTRLD _SFR_MEM8(0x0903) +-#define TCD0_CTRLE _SFR_MEM8(0x0904) +-#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +-#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +-#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +-#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +-#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +-#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +-#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +-#define TCD0_TEMP _SFR_MEM8(0x090F) +-#define TCD0_CNT _SFR_MEM16(0x0920) +-#define TCD0_PER _SFR_MEM16(0x0926) +-#define TCD0_CCA _SFR_MEM16(0x0928) +-#define TCD0_CCB _SFR_MEM16(0x092A) +-#define TCD0_CCC _SFR_MEM16(0x092C) +-#define TCD0_CCD _SFR_MEM16(0x092E) +-#define TCD0_PERBUF _SFR_MEM16(0x0936) +-#define TCD0_CCABUF _SFR_MEM16(0x0938) +-#define TCD0_CCBBUF _SFR_MEM16(0x093A) +-#define TCD0_CCCBUF _SFR_MEM16(0x093C) +-#define TCD0_CCDBUF _SFR_MEM16(0x093E) +- +-/* TCD1 - Timer/Counter D1 */ +-#define TCD1_CTRLA _SFR_MEM8(0x0940) +-#define TCD1_CTRLB _SFR_MEM8(0x0941) +-#define TCD1_CTRLC _SFR_MEM8(0x0942) +-#define TCD1_CTRLD _SFR_MEM8(0x0943) +-#define TCD1_CTRLE _SFR_MEM8(0x0944) +-#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +-#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +-#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +-#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +-#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +-#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +-#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +-#define TCD1_TEMP _SFR_MEM8(0x094F) +-#define TCD1_CNT _SFR_MEM16(0x0960) +-#define TCD1_PER _SFR_MEM16(0x0966) +-#define TCD1_CCA _SFR_MEM16(0x0968) +-#define TCD1_CCB _SFR_MEM16(0x096A) +-#define TCD1_PERBUF _SFR_MEM16(0x0976) +-#define TCD1_CCABUF _SFR_MEM16(0x0978) +-#define TCD1_CCBBUF _SFR_MEM16(0x097A) +- +-/* HIRESD - High-Resolution Extension D */ +-#define HIRESD_CTRLA _SFR_MEM8(0x0990) +- +-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +-#define USARTD0_DATA _SFR_MEM8(0x09A0) +-#define USARTD0_STATUS _SFR_MEM8(0x09A1) +-#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +-#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +-#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +-#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +-#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) +- +-/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ +-#define USARTD1_DATA _SFR_MEM8(0x09B0) +-#define USARTD1_STATUS _SFR_MEM8(0x09B1) +-#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +-#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +-#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +-#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +-#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) +- +-/* SPID - Serial Peripheral Interface D */ +-#define SPID_CTRL _SFR_MEM8(0x09C0) +-#define SPID_INTCTRL _SFR_MEM8(0x09C1) +-#define SPID_STATUS _SFR_MEM8(0x09C2) +-#define SPID_DATA _SFR_MEM8(0x09C3) +- +-/* TCE0 - Timer/Counter E0 */ +-#define TCE0_CTRLA _SFR_MEM8(0x0A00) +-#define TCE0_CTRLB _SFR_MEM8(0x0A01) +-#define TCE0_CTRLC _SFR_MEM8(0x0A02) +-#define TCE0_CTRLD _SFR_MEM8(0x0A03) +-#define TCE0_CTRLE _SFR_MEM8(0x0A04) +-#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +-#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +-#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +-#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +-#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +-#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +-#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +-#define TCE0_TEMP _SFR_MEM8(0x0A0F) +-#define TCE0_CNT _SFR_MEM16(0x0A20) +-#define TCE0_PER _SFR_MEM16(0x0A26) +-#define TCE0_CCA _SFR_MEM16(0x0A28) +-#define TCE0_CCB _SFR_MEM16(0x0A2A) +-#define TCE0_CCC _SFR_MEM16(0x0A2C) +-#define TCE0_CCD _SFR_MEM16(0x0A2E) +-#define TCE0_PERBUF _SFR_MEM16(0x0A36) +-#define TCE0_CCABUF _SFR_MEM16(0x0A38) +-#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +-#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +-#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) +- +-/* TCE1 - Timer/Counter E1 */ +-#define TCE1_CTRLA _SFR_MEM8(0x0A40) +-#define TCE1_CTRLB _SFR_MEM8(0x0A41) +-#define TCE1_CTRLC _SFR_MEM8(0x0A42) +-#define TCE1_CTRLD _SFR_MEM8(0x0A43) +-#define TCE1_CTRLE _SFR_MEM8(0x0A44) +-#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) +-#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) +-#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) +-#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) +-#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) +-#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) +-#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) +-#define TCE1_TEMP _SFR_MEM8(0x0A4F) +-#define TCE1_CNT _SFR_MEM16(0x0A60) +-#define TCE1_PER _SFR_MEM16(0x0A66) +-#define TCE1_CCA _SFR_MEM16(0x0A68) +-#define TCE1_CCB _SFR_MEM16(0x0A6A) +-#define TCE1_PERBUF _SFR_MEM16(0x0A76) +-#define TCE1_CCABUF _SFR_MEM16(0x0A78) +-#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) +- +-/* AWEXE - Advanced Waveform Extension E */ +-#define AWEXE_CTRL _SFR_MEM8(0x0A80) +-#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +-#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +-#define AWEXE_STATUS _SFR_MEM8(0x0A84) +-#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +-#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +-#define AWEXE_DTLS _SFR_MEM8(0x0A88) +-#define AWEXE_DTHS _SFR_MEM8(0x0A89) +-#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +-#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +-#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) +- +-/* HIRESE - High-Resolution Extension E */ +-#define HIRESE_CTRLA _SFR_MEM8(0x0A90) +- +-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +-#define USARTE0_DATA _SFR_MEM8(0x0AA0) +-#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +-#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +-#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +-#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +-#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +-#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) +- +-/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ +-#define USARTE1_DATA _SFR_MEM8(0x0AB0) +-#define USARTE1_STATUS _SFR_MEM8(0x0AB1) +-#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) +-#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) +-#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) +-#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) +-#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) +- +-/* SPIE - Serial Peripheral Interface E */ +-#define SPIE_CTRL _SFR_MEM8(0x0AC0) +-#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +-#define SPIE_STATUS _SFR_MEM8(0x0AC2) +-#define SPIE_DATA _SFR_MEM8(0x0AC3) +- +-/* TCF0 - Timer/Counter F0 */ +-#define TCF0_CTRLA _SFR_MEM8(0x0B00) +-#define TCF0_CTRLB _SFR_MEM8(0x0B01) +-#define TCF0_CTRLC _SFR_MEM8(0x0B02) +-#define TCF0_CTRLD _SFR_MEM8(0x0B03) +-#define TCF0_CTRLE _SFR_MEM8(0x0B04) +-#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +-#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +-#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +-#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +-#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +-#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +-#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +-#define TCF0_TEMP _SFR_MEM8(0x0B0F) +-#define TCF0_CNT _SFR_MEM16(0x0B20) +-#define TCF0_PER _SFR_MEM16(0x0B26) +-#define TCF0_CCA _SFR_MEM16(0x0B28) +-#define TCF0_CCB _SFR_MEM16(0x0B2A) +-#define TCF0_CCC _SFR_MEM16(0x0B2C) +-#define TCF0_CCD _SFR_MEM16(0x0B2E) +-#define TCF0_PERBUF _SFR_MEM16(0x0B36) +-#define TCF0_CCABUF _SFR_MEM16(0x0B38) +-#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +-#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +-#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) +- +-/* HIRESF - High-Resolution Extension F */ +-#define HIRESF_CTRLA _SFR_MEM8(0x0B90) +- +-/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ +-#define USARTF0_DATA _SFR_MEM8(0x0BA0) +-#define USARTF0_STATUS _SFR_MEM8(0x0BA1) +-#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) +-#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) +-#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) +-#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) +-#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) +- +-/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ +-#define USARTF1_DATA _SFR_MEM8(0x0BB0) +-#define USARTF1_STATUS _SFR_MEM8(0x0BB1) +-#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) +-#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) +-#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) +-#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) +-#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) +- +-/* SPIF - Serial Peripheral Interface F */ +-#define SPIF_CTRL _SFR_MEM8(0x0BC0) +-#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) +-#define SPIF_STATUS _SFR_MEM8(0x0BC2) +-#define SPIF_DATA _SFR_MEM8(0x0BC3) +- +- +- +-/*================== Bitfield Definitions ================== */ +- +-/* XOCD - On-Chip Debug System */ +-/* OCD.OCDR1 bit masks and bit positions */ +-#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +-#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ +- +- +-/* CPU - CPU */ +-/* CPU.CCP bit masks and bit positions */ +-#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +-#define CPU_CCP_gp 0 /* CCP signature group position. */ +-#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +-#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +-#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +-#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +-#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +-#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +-#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +-#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +-#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +-#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +-#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +-#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +-#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +-#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +-#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +-#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ +- +- +-/* CPU.SREG bit masks and bit positions */ +-#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +-#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ +- +-#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +-#define CPU_T_bp 6 /* Transfer Bit bit position. */ +- +-#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +-#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +- +-#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +-#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +- +-#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +-#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +- +-#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +-#define CPU_N_bp 2 /* Negative Flag bit position. */ +- +-#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +-#define CPU_Z_bp 1 /* Zero Flag bit position. */ +- +-#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +-#define CPU_C_bp 0 /* Carry Flag bit position. */ +- +- +-/* CLK - Clock System */ +-/* CLK.CTRL bit masks and bit positions */ +-#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +-#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +-#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +-#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +-#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +-#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +-#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +-#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ +- +- +-/* CLK.PSCTRL bit masks and bit positions */ +-#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +-#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +-#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +-#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +-#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +-#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +-#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +-#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +-#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +-#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +-#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +-#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ +- +-#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +-#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +-#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +-#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +-#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +-#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ +- +- +-/* CLK.LOCK bit masks and bit positions */ +-#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +-#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ +- +- +-/* CLK.RTCCTRL bit masks and bit positions */ +-#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +-#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +-#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +-#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +-#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +-#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +-#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +-#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ +- +-#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +-#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ +- +- +-/* PR.PRGEN bit masks and bit positions */ +-#define PR_AES_bm 0x10 /* AES bit mask. */ +-#define PR_AES_bp 4 /* AES bit position. */ +- +-#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +-#define PR_EBI_bp 3 /* External Bus Interface bit position. */ +- +-#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +-#define PR_RTC_bp 2 /* Real-time Counter bit position. */ +- +-#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +-#define PR_EVSYS_bp 1 /* Event System bit position. */ +- +-#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +-#define PR_DMA_bp 0 /* DMA-Controller bit position. */ +- +- +-/* PR.PRPA bit masks and bit positions */ +-#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +-#define PR_DAC_bp 2 /* Port A DAC bit position. */ +- +-#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +-#define PR_ADC_bp 1 /* Port A ADC bit position. */ +- +-#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +-#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ +- +- +-/* PR.PRPB bit masks and bit positions */ +-/* PR_DAC_bm Predefined. */ +-/* PR_DAC_bp Predefined. */ +- +-/* PR_ADC_bm Predefined. */ +-/* PR_ADC_bp Predefined. */ +- +-/* PR_AC_bm Predefined. */ +-/* PR_AC_bp Predefined. */ +- +- +-/* PR.PRPC bit masks and bit positions */ +-#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +-#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ +- +-#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +-#define PR_USART1_bp 5 /* Port C USART1 bit position. */ +- +-#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +-#define PR_USART0_bp 4 /* Port C USART0 bit position. */ +- +-#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +-#define PR_SPI_bp 3 /* Port C SPI bit position. */ +- +-#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +-#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ +- +-#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +-#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ +- +-#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +-#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ +- +- +-/* PR.PRPD bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* PR.PRPE bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* PR.PRPF bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* SLEEP - Sleep Controller */ +-/* SLEEP.CTRL bit masks and bit positions */ +-#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +-#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +-#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +-#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +-#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +-#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +-#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +-#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ +- +-#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +-#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ +- +- +-/* OSC - Oscillator */ +-/* OSC.CTRL bit masks and bit positions */ +-#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +-#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ +- +-#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +-#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ +- +-#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ +- +- +-/* OSC.STATUS bit masks and bit positions */ +-#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +-#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ +- +-#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +-#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ +- +-#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ +- +- +-/* OSC.XOSCCTRL bit masks and bit positions */ +-#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +-#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +-#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +-#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +-#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +-#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ +- +-#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +-#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ +- +-#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +-#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +-#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +-#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +-#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +-#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +-#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +-#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +-#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +-#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +- +- +-/* OSC.XOSCFAIL bit masks and bit positions */ +-#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +-#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ +- +-#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +-#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ +- +- +-/* OSC.PLLCTRL bit masks and bit positions */ +-#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +-#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +-#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +-#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +-#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +-#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ +- +-#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +-#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +-#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +-#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +-#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +-#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +-#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +-#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +-#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +-#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +-#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +-#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ +- +- +-/* OSC.DFLLCTRL bit masks and bit positions */ +-#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +-#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ +- +-#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +-#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ +- +- +-/* DFLL - DFLL */ +-/* DFLL.CTRL bit masks and bit positions */ +-#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +-#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ +- +- +-/* DFLL.CALA bit masks and bit positions */ +-#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +-#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +-#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +-#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +-#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +-#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +-#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +-#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +-#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +-#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +-#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +-#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +-#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +-#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +-#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +-#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ +- +- +-/* DFLL.CALB bit masks and bit positions */ +-#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +-#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +-#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +-#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +-#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +-#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +-#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +-#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +-#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +-#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +-#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +-#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +-#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +-#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ +- +- +-/* RST - Reset */ +-/* RST.STATUS bit masks and bit positions */ +-#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +-#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ +- +-#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +-#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ +- +-#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +-#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ +- +-#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +-#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ +- +-#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +-#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ +- +-#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +-#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ +- +-#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +-#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ +- +- +-/* RST.CTRL bit masks and bit positions */ +-#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +-#define RST_SWRST_bp 0 /* Software Reset bit position. */ +- +- +-/* WDT - Watch-Dog Timer */ +-/* WDT.CTRL bit masks and bit positions */ +-#define WDT_PER_gm 0x3C /* Period group mask. */ +-#define WDT_PER_gp 2 /* Period group position. */ +-#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +-#define WDT_PER0_bp 2 /* Period bit 0 position. */ +-#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +-#define WDT_PER1_bp 3 /* Period bit 1 position. */ +-#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +-#define WDT_PER2_bp 4 /* Period bit 2 position. */ +-#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +-#define WDT_PER3_bp 5 /* Period bit 3 position. */ +- +-#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +-#define WDT_ENABLE_bp 1 /* Enable bit position. */ +- +-#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +-#define WDT_CEN_bp 0 /* Change Enable bit position. */ +- +- +-/* WDT.WINCTRL bit masks and bit positions */ +-#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +-#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +-#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +-#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +-#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +-#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +-#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +-#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +-#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +-#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ +- +-#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +-#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ +- +-#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +-#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ +- +- +-/* WDT.STATUS bit masks and bit positions */ +-#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +-#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +- +- +-/* MCU - MCU Control */ +-/* MCU.MCUCR bit masks and bit positions */ +-#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +-#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ +- +- +-/* MCU.EVSYSLOCK bit masks and bit positions */ +-#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +-#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ +- +-#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +-#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ +- +- +-/* MCU.AWEXLOCK bit masks and bit positions */ +-#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +-#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ +- +-#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +-#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ +- +- +-/* PMIC - Programmable Multi-level Interrupt Controller */ +-/* PMIC.STATUS bit masks and bit positions */ +-#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +-#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ +- +-#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +-#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ +- +-#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +-#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ +- +-#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +-#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ +- +- +-/* PMIC.CTRL bit masks and bit positions */ +-#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +-#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ +- +-#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +-#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ +- +-#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +-#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ +- +-#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +-#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ +- +-#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +-#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ +- +- +-/* DMA - DMA Controller */ +-/* DMA_CH.CTRLA bit masks and bit positions */ +-#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +-#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ +- +-#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +-#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ +- +-#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +-#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ +- +-#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +-#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ +- +-#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +-#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ +- +-#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +-#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +-#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +-#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +-#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +-#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ +- +- +-/* DMA_CH.CTRLB bit masks and bit positions */ +-#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +-#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ +- +-#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +-#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ +- +-#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +-#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ +- +-#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +-#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +-#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +-#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +-#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +-#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ +- +-#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +-#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +-#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +-#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +-#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +-#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ +- +- +-/* DMA_CH.ADDRCTRL bit masks and bit positions */ +-#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +-#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +-#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +-#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +-#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +-#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ +- +-#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +-#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +-#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +-#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +-#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +-#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ +- +-#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +-#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +-#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +-#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +-#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +-#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ +- +-#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +-#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +-#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +-#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +-#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +-#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ +- +- +-/* DMA_CH.TRIGSRC bit masks and bit positions */ +-#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +-#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +-#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +-#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +-#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +-#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +-#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +-#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +-#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +-#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +-#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +-#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +-#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +-#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +-#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +-#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +-#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +-#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ +- +- +-/* DMA.CTRL bit masks and bit positions */ +-#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +-#define DMA_ENABLE_bp 7 /* Enable bit position. */ +- +-#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +-#define DMA_RESET_bp 6 /* Software Reset bit position. */ +- +-#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +-#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +-#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +-#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +-#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +-#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ +- +-#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +-#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +-#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +-#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +-#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +-#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ +- +- +-/* DMA.INTFLAGS bit masks and bit positions */ +-#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ +- +- +-/* DMA.STATUS bit masks and bit positions */ +-#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +-#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ +- +-#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +-#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ +- +-#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +-#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ +- +-#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +-#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ +- +-#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +-#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ +- +-#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +-#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ +- +-#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +-#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ +- +-#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +-#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ +- +- +-/* EVSYS - Event System */ +-/* EVSYS.CH0MUX bit masks and bit positions */ +-#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +-#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +-#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +-#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +-#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +-#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +-#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +-#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +-#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +-#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +-#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +-#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +-#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +-#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +-#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +-#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +-#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +-#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ +- +- +-/* EVSYS.CH1MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH2MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH3MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH4MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH5MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH6MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH7MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH0CTRL bit masks and bit positions */ +-#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +-#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +-#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +-#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +-#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +-#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ +- +-#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +-#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ +- +-#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +-#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ +- +-#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +-#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +-#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +-#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +-#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +-#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +-#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +-#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ +- +- +-/* EVSYS.CH1CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH2CTRL bit masks and bit positions */ +-/* EVSYS_QDIRM_gm Predefined. */ +-/* EVSYS_QDIRM_gp Predefined. */ +-/* EVSYS_QDIRM0_bm Predefined. */ +-/* EVSYS_QDIRM0_bp Predefined. */ +-/* EVSYS_QDIRM1_bm Predefined. */ +-/* EVSYS_QDIRM1_bp Predefined. */ +- +-/* EVSYS_QDIEN_bm Predefined. */ +-/* EVSYS_QDIEN_bp Predefined. */ +- +-/* EVSYS_QDEN_bm Predefined. */ +-/* EVSYS_QDEN_bp Predefined. */ +- +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH3CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH4CTRL bit masks and bit positions */ +-/* EVSYS_QDIRM_gm Predefined. */ +-/* EVSYS_QDIRM_gp Predefined. */ +-/* EVSYS_QDIRM0_bm Predefined. */ +-/* EVSYS_QDIRM0_bp Predefined. */ +-/* EVSYS_QDIRM1_bm Predefined. */ +-/* EVSYS_QDIRM1_bp Predefined. */ +- +-/* EVSYS_QDIEN_bm Predefined. */ +-/* EVSYS_QDIEN_bp Predefined. */ +- +-/* EVSYS_QDEN_bm Predefined. */ +-/* EVSYS_QDEN_bp Predefined. */ +- +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH5CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH6CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH7CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* NVM - Non Volatile Memory Controller */ +-/* NVM.CMD bit masks and bit positions */ +-#define NVM_CMD_gm 0xFF /* Command group mask. */ +-#define NVM_CMD_gp 0 /* Command group position. */ +-#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +-#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +-#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +-#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +-#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +-#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +-#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +-#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +-#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +-#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +-#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +-#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +-#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +-#define NVM_CMD7_bp 7 /* Command bit 7 position. */ +- +- +-/* NVM.CTRLA bit masks and bit positions */ +-#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +-#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ +- +- +-/* NVM.CTRLB bit masks and bit positions */ +-#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +-#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ +- +-#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +-#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ +- +-#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +-#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ +- +-#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +-#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ +- +- +-/* NVM.INTCTRL bit masks and bit positions */ +-#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +-#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +-#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +-#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +-#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +-#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ +- +-#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +-#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +-#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +-#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +-#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +-#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ +- +- +-/* NVM.STATUS bit masks and bit positions */ +-#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +-#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ +- +-#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +-#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ +- +-#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +-#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ +- +-#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +-#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ +- +- +-/* NVM.LOCKBITS bit masks and bit positions */ +-#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +-#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +-#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ +-#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ +-#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ +-#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ +-#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ +-#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ +-#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ +-#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ +-#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ +-#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ +-#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ +-#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ +-#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ +-#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ +-#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ +-#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ +-#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ +-#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +-#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +-#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +-#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ +- +-#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +-#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +-#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +-#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +-#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ +- +-#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +-#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ +- +-#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +-#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +-#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +-#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +-#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +-#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +-#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +-#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +-#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +-#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +-#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +-#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ +- +-#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +-#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ +- +-#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ +-#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ +- +- +-/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +-#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +-#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +-#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +-#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +-#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +-#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ +- +-#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +-#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ +- +-#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +-#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +-#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +-#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +-#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +-#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +-#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +-#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +- +- +-/* AC - Analog Comparator */ +-/* AC.AC0CTRL bit masks and bit positions */ +-#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +-#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +-#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +-#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +-#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +-#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ +- +-#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +-#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +-#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +-#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +-#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +-#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ +- +-#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +-#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ +- +-#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +-#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +-#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +-#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +-#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +-#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +- +-#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define AC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* AC.AC1CTRL bit masks and bit positions */ +-/* AC_INTMODE_gm Predefined. */ +-/* AC_INTMODE_gp Predefined. */ +-/* AC_INTMODE0_bm Predefined. */ +-/* AC_INTMODE0_bp Predefined. */ +-/* AC_INTMODE1_bm Predefined. */ +-/* AC_INTMODE1_bp Predefined. */ +- +-/* AC_INTLVL_gm Predefined. */ +-/* AC_INTLVL_gp Predefined. */ +-/* AC_INTLVL0_bm Predefined. */ +-/* AC_INTLVL0_bp Predefined. */ +-/* AC_INTLVL1_bm Predefined. */ +-/* AC_INTLVL1_bp Predefined. */ +- +-/* AC_HSMODE_bm Predefined. */ +-/* AC_HSMODE_bp Predefined. */ +- +-/* AC_HYSMODE_gm Predefined. */ +-/* AC_HYSMODE_gp Predefined. */ +-/* AC_HYSMODE0_bm Predefined. */ +-/* AC_HYSMODE0_bp Predefined. */ +-/* AC_HYSMODE1_bm Predefined. */ +-/* AC_HYSMODE1_bp Predefined. */ +- +-/* AC_ENABLE_bm Predefined. */ +-/* AC_ENABLE_bp Predefined. */ +- +- +-/* AC.AC0MUXCTRL bit masks and bit positions */ +-#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +-#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +-#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +-#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +-#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +-#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +-#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +-#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ +- +-#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +-#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +-#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +-#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +-#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +-#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +-#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +-#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ +- +- +-/* AC.AC1MUXCTRL bit masks and bit positions */ +-/* AC_MUXPOS_gm Predefined. */ +-/* AC_MUXPOS_gp Predefined. */ +-/* AC_MUXPOS0_bm Predefined. */ +-/* AC_MUXPOS0_bp Predefined. */ +-/* AC_MUXPOS1_bm Predefined. */ +-/* AC_MUXPOS1_bp Predefined. */ +-/* AC_MUXPOS2_bm Predefined. */ +-/* AC_MUXPOS2_bp Predefined. */ +- +-/* AC_MUXNEG_gm Predefined. */ +-/* AC_MUXNEG_gp Predefined. */ +-/* AC_MUXNEG0_bm Predefined. */ +-/* AC_MUXNEG0_bp Predefined. */ +-/* AC_MUXNEG1_bm Predefined. */ +-/* AC_MUXNEG1_bp Predefined. */ +-/* AC_MUXNEG2_bm Predefined. */ +-/* AC_MUXNEG2_bp Predefined. */ +- +- +-/* AC.CTRLA bit masks and bit positions */ +-#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +-#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ +- +- +-/* AC.CTRLB bit masks and bit positions */ +-#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +-#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +-#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +-#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +-#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +-#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +-#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +-#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +-#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +-#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +-#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +-#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +-#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +-#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ +- +- +-/* AC.WINCTRL bit masks and bit positions */ +-#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +-#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ +- +-#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +-#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +-#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +-#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +-#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +-#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ +- +-#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +-#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +-#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +-#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +-#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +-#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ +- +- +-/* AC.STATUS bit masks and bit positions */ +-#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +-#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +-#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +-#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +-#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +-#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ +- +-#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +-#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ +- +-#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +-#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ +- +-#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +-#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ +- +-#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +-#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ +- +-#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +-#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ +- +- +-/* ADC - Analog/Digital Converter */ +-/* ADC_CH.CTRL bit masks and bit positions */ +-#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +-#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ +- +-#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +-#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +-#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +-#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +-#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +-#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +-#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +-#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ +- +-#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +-#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +-#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +-#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +-#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +-#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ +- +- +-/* ADC_CH.MUXCTRL bit masks and bit positions */ +-#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +-#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +-#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +-#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +-#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +-#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +-#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +-#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +-#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +-#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ +- +-#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +-#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +-#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +-#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +-#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +-#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +-#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +-#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +-#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +-#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ +- +-#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +-#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +-#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +-#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +-#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +-#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ +- +- +-/* ADC_CH.INTCTRL bit masks and bit positions */ +-#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +-#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +-#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +-#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +-#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +-#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ +- +-#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +-#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +-#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +-#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +-#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +-#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ +- +- +-/* ADC_CH.INTFLAGS bit masks and bit positions */ +-#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +-#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ +- +- +-/* ADC.CTRLA bit masks and bit positions */ +-#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +-#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +-#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +-#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +-#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +-#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ +- +-#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +-#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ +- +-#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +-#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ +- +-#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +-#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ +- +-#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +-#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ +- +-#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +-#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ +- +-#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +-#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ +- +- +-/* ADC.CTRLB bit masks and bit positions */ +-#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +-#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ +- +-#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +-#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ +- +-#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +-#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +-#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +-#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +-#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +-#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ +- +- +-/* ADC.REFCTRL bit masks and bit positions */ +-#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +-#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +-#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +-#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +-#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +-#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +- +-#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +-#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ +- +-#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +-#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ +- +- +-/* ADC.EVCTRL bit masks and bit positions */ +-#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +-#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +-#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +-#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +-#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +-#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ +- +-#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +-#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +-#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +-#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +-#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +-#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +-#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +-#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ +- +-#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +-#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +-#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +-#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +-#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +-#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +-#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +-#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ +- +- +-/* ADC.PRESCALER bit masks and bit positions */ +-#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +-#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +-#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +-#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +-#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +-#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +-#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +-#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ +- +- +-/* ADC.INTFLAGS bit masks and bit positions */ +-#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +-#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ +- +-#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +-#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ +- +-#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +-#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ +- +-#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +-#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ +- +- +-/* DAC - Digital/Analog Converter */ +-/* DAC.CTRLA bit masks and bit positions */ +-#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +-#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ +- +-#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +-#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ +- +-#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +-#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ +- +-#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +-#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ +- +-#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define DAC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* DAC.CTRLB bit masks and bit positions */ +-#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +-#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +-#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +-#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +-#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +-#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ +- +-#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +-#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ +- +-#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +-#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ +- +- +-/* DAC.CTRLC bit masks and bit positions */ +-#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +-#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +-#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +-#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +-#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +-#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ +- +-#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +-#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ +- +- +-/* DAC.EVCTRL bit masks and bit positions */ +-#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +-#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +-#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +-#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +-#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +-#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +-#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +-#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ +- +- +-/* DAC.TIMCTRL bit masks and bit positions */ +-#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ +-#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ +-#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ +-#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ +-#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ +-#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ +-#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ +-#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ +- +-#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ +-#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ +-#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ +-#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ +-#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ +-#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ +-#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ +-#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ +-#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ +-#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ +- +- +-/* DAC.STATUS bit masks and bit positions */ +-#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +-#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ +- +-#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +-#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ +- +- +-/* RTC - Real-Time Clounter */ +-/* RTC.CTRL bit masks and bit positions */ +-#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +-#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +-#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +-#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +-#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +-#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +-#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +-#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ +- +- +-/* RTC.STATUS bit masks and bit positions */ +-#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +-#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ +- +- +-/* RTC.INTCTRL bit masks and bit positions */ +-#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +-#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +-#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +-#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +-#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +-#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ +- +-#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +-#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +-#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +-#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +-#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +-#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ +- +- +-/* RTC.INTFLAGS bit masks and bit positions */ +-#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +-#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ +- +-#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* EBI - External Bus Interface */ +-/* EBI_CS.CTRLA bit masks and bit positions */ +-#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +-#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +-#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +-#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +-#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +-#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +-#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +-#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +-#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +-#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +-#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +-#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ +- +-#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +-#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +-#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +-#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +-#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +-#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ +- +- +-/* EBI_CS.CTRLB bit masks and bit positions */ +-#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +-#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +-#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +-#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +-#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +-#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +-#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +-#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ +- +-#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +-#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ +- +-#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +-#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ +- +-#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +-#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +-#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +-#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +-#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +-#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ +- +- +-/* EBI.CTRL bit masks and bit positions */ +-#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +-#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +-#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +-#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +-#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +-#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ +- +-#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +-#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +-#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +-#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +-#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +-#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ +- +-#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +-#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +-#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +-#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +-#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +-#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ +- +-#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +-#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +-#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +-#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +-#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +-#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLA bit masks and bit positions */ +-#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +-#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ +- +-#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +-#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ +- +-#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +-#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +-#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +-#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +-#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +-#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLB bit masks and bit positions */ +-#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +-#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +-#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +-#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +-#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +-#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ +- +-#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +-#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +-#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +-#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +-#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +-#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +-#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +-#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ +- +-#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +-#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +-#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +-#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +-#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +-#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +-#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +-#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ +- +- +-/* EBI.SDRAMCTRLC bit masks and bit positions */ +-#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +-#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +-#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +-#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +-#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +-#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ +- +-#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +-#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +-#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +-#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +-#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +-#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +-#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +-#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ +- +-#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +-#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +-#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +-#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +-#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +-#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +-#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +-#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ +- +- +-/* TWI - Two-Wire Interface */ +-/* TWI_MASTER.CTRLA bit masks and bit positions */ +-#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +-#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ +- +-#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +-#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ +- +-#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +-#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ +- +- +-/* TWI_MASTER.CTRLB bit masks and bit positions */ +-#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +-#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +-#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +-#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +-#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +-#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +- +-#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +-#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ +- +-#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_MASTER.CTRLC bit masks and bit positions */ +-#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +-#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_MASTER.STATUS bit masks and bit positions */ +-#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +-#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ +- +-#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +-#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ +- +-#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +-#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +- +-#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +-#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +-#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +-#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +-#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +-#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +- +- +-/* TWI_SLAVE.CTRLA bit masks and bit positions */ +-#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +-#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +-#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ +- +-#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +-#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ +- +-#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_SLAVE.CTRLB bit masks and bit positions */ +-#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +-#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_SLAVE.STATUS bit masks and bit positions */ +-#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +-#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +-#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +-#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ +- +-#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +-#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ +- +-#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +-#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ +- +- +-/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +-#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +-#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +-#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +-#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +-#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +-#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +-#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +-#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +-#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +-#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +-#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +-#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +-#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +-#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +-#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +-#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ +- +-#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +-#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ +- +- +-/* TWI.CTRL bit masks and bit positions */ +-#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +-#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ +- +-#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +-#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ +- +- +-/* PORT - Port Configuration */ +-/* PORTCFG.VPCTRLA bit masks and bit positions */ +-#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +-#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +-#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +-#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +-#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +-#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +-#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +-#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +-#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +-#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ +- +-#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +-#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +-#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +-#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +-#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +-#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +-#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +-#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +-#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +-#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ +- +- +-/* PORTCFG.VPCTRLB bit masks and bit positions */ +-#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +-#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +-#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +-#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +-#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +-#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +-#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +-#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +-#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +-#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ +- +-#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +-#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +-#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +-#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +-#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +-#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +-#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +-#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +-#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +-#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ +- +- +-/* PORTCFG.CLKEVOUT bit masks and bit positions */ +-#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +-#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +-#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +-#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +-#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +-#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ +- +-#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +-#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +-#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +-#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +-#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +-#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ +- +- +-/* VPORT.INTFLAGS bit masks and bit positions */ +-#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.INTCTRL bit masks and bit positions */ +-#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +-#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +-#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +-#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +-#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +-#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ +- +-#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +-#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +-#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +-#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +-#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +-#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ +- +- +-/* PORT.INTFLAGS bit masks and bit positions */ +-#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.PIN0CTRL bit masks and bit positions */ +-#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +-#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ +- +-#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +-#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ +- +-#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +-#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +-#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +-#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +-#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +-#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +-#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +-#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ +- +-#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +-#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +-#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +-#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +-#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +-#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +-#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +-#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +- +- +-/* PORT.PIN1CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN2CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN3CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN4CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN5CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN6CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN7CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* TC - 16-bit Timer/Counter With PWM */ +-/* TC0.CTRLA bit masks and bit positions */ +-#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC0.CTRLB bit masks and bit positions */ +-#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +-#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ +- +-#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +-#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ +- +-#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC0.CTRLC bit masks and bit positions */ +-#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +-#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ +- +-#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +-#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ +- +-#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC0.CTRLD bit masks and bit positions */ +-#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC0_EVACT_gp 5 /* Event Action group position. */ +-#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC0.CTRLE bit masks and bit positions */ +-#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +-#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ +- +-#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC0.INTCTRLA bit masks and bit positions */ +-#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC0.INTCTRLB bit masks and bit positions */ +-#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +-#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +-#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +-#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +-#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +-#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ +- +-#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +-#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +-#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +-#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +-#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +-#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ +- +-#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC0.CTRLFCLR bit masks and bit positions */ +-#define TC0_CMD_gm 0x0C /* Command group mask. */ +-#define TC0_CMD_gp 2 /* Command group position. */ +-#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC0_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC0_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC0_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC0.CTRLFSET bit masks and bit positions */ +-/* TC0_CMD_gm Predefined. */ +-/* TC0_CMD_gp Predefined. */ +-/* TC0_CMD0_bm Predefined. */ +-/* TC0_CMD0_bp Predefined. */ +-/* TC0_CMD1_bm Predefined. */ +-/* TC0_CMD1_bp Predefined. */ +- +-/* TC0_LUPD_bm Predefined. */ +-/* TC0_LUPD_bp Predefined. */ +- +-/* TC0_DIR_bm Predefined. */ +-/* TC0_DIR_bp Predefined. */ +- +- +-/* TC0.CTRLGCLR bit masks and bit positions */ +-#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +-#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ +- +-#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +-#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ +- +-#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC0.CTRLGSET bit masks and bit positions */ +-/* TC0_CCDBV_bm Predefined. */ +-/* TC0_CCDBV_bp Predefined. */ +- +-/* TC0_CCCBV_bm Predefined. */ +-/* TC0_CCCBV_bp Predefined. */ +- +-/* TC0_CCBBV_bm Predefined. */ +-/* TC0_CCBBV_bp Predefined. */ +- +-/* TC0_CCABV_bm Predefined. */ +-/* TC0_CCABV_bp Predefined. */ +- +-/* TC0_PERBV_bm Predefined. */ +-/* TC0_PERBV_bp Predefined. */ +- +- +-/* TC0.INTFLAGS bit masks and bit positions */ +-#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +-#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ +- +-#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +-#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ +- +-#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* TC1.CTRLA bit masks and bit positions */ +-#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC1.CTRLB bit masks and bit positions */ +-#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC1.CTRLC bit masks and bit positions */ +-#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC1.CTRLD bit masks and bit positions */ +-#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC1_EVACT_gp 5 /* Event Action group position. */ +-#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC1.CTRLE bit masks and bit positions */ +-#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +-#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ +- +-#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC1.INTCTRLA bit masks and bit positions */ +-#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC1.INTCTRLB bit masks and bit positions */ +-#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC1.CTRLFCLR bit masks and bit positions */ +-#define TC1_CMD_gm 0x0C /* Command group mask. */ +-#define TC1_CMD_gp 2 /* Command group position. */ +-#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC1_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC1_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC1_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC1.CTRLFSET bit masks and bit positions */ +-/* TC1_CMD_gm Predefined. */ +-/* TC1_CMD_gp Predefined. */ +-/* TC1_CMD0_bm Predefined. */ +-/* TC1_CMD0_bp Predefined. */ +-/* TC1_CMD1_bm Predefined. */ +-/* TC1_CMD1_bp Predefined. */ +- +-/* TC1_LUPD_bm Predefined. */ +-/* TC1_LUPD_bp Predefined. */ +- +-/* TC1_DIR_bm Predefined. */ +-/* TC1_DIR_bp Predefined. */ +- +- +-/* TC1.CTRLGCLR bit masks and bit positions */ +-#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC1.CTRLGSET bit masks and bit positions */ +-/* TC1_CCBBV_bm Predefined. */ +-/* TC1_CCBBV_bp Predefined. */ +- +-/* TC1_CCABV_bm Predefined. */ +-/* TC1_CCABV_bp Predefined. */ +- +-/* TC1_PERBV_bm Predefined. */ +-/* TC1_PERBV_bp Predefined. */ +- +- +-/* TC1.INTFLAGS bit masks and bit positions */ +-#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* AWEX.CTRL bit masks and bit positions */ +-#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +-#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ +- +-#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +-#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ +- +-#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +-#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ +- +-#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +-#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ +- +-#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +-#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ +- +-#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +-#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ +- +- +-/* AWEX.FDCTRL bit masks and bit positions */ +-#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +-#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ +- +-#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +-#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ +- +-#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +-#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +-#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +-#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +-#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +-#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ +- +- +-/* AWEX.STATUS bit masks and bit positions */ +-#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +-#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ +- +-#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +-#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ +- +-#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +-#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ +- +- +-/* HIRES.CTRL bit masks and bit positions */ +-#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +-#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +-#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +-#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +-#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +-#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ +- +- +-/* USART - Universal Asynchronous Receiver-Transmitter */ +-/* USART.STATUS bit masks and bit positions */ +-#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +-#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ +- +-#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +-#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +- +-#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +-#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +- +-#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +-#define USART_FERR_bp 4 /* Frame Error bit position. */ +- +-#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +-#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ +- +-#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +-#define USART_PERR_bp 2 /* Parity Error bit position. */ +- +-#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +-#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ +- +- +-/* USART.CTRLA bit masks and bit positions */ +-#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +-#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +-#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +-#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +-#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +-#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ +- +-#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +-#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +-#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +-#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +-#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +-#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ +- +-#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +-#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +-#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +-#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +-#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +-#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ +- +- +-/* USART.CTRLB bit masks and bit positions */ +-#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +-#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ +- +-#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +-#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ +- +-#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +-#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ +- +-#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +-#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ +- +-#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +-#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ +- +- +-/* USART.CTRLC bit masks and bit positions */ +-#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +-#define USART_CMODE_gp 6 /* Communication Mode group position. */ +-#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +-#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +-#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +-#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ +- +-#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +-#define USART_PMODE_gp 4 /* Parity Mode group position. */ +-#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +-#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +-#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +-#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +- +-#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +-#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +- +-#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +-#define USART_CHSIZE_gp 0 /* Character Size group position. */ +-#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +-#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +-#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +-#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +-#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +-#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +- +- +-/* USART.BAUDCTRLA bit masks and bit positions */ +-#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +-#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +-#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +-#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +-#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +-#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +-#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +-#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +-#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +-#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +-#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +-#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +-#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +-#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +-#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +-#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +-#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +-#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ +- +- +-/* USART.BAUDCTRLB bit masks and bit positions */ +-#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +-#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +-#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +-#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +-#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +-#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +-#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +-#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +-#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +-#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ +- +-/* USART_BSEL_gm Predefined. */ +-/* USART_BSEL_gp Predefined. */ +-/* USART_BSEL0_bm Predefined. */ +-/* USART_BSEL0_bp Predefined. */ +-/* USART_BSEL1_bm Predefined. */ +-/* USART_BSEL1_bp Predefined. */ +-/* USART_BSEL2_bm Predefined. */ +-/* USART_BSEL2_bp Predefined. */ +-/* USART_BSEL3_bm Predefined. */ +-/* USART_BSEL3_bp Predefined. */ +- +- +-/* SPI - Serial Peripheral Interface */ +-/* SPI.CTRL bit masks and bit positions */ +-#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +-#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ +- +-#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +-#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ +- +-#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +-#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ +- +-#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +-#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ +- +-#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +-#define SPI_MODE_gp 2 /* SPI Mode group position. */ +-#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +-#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +-#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +-#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ +- +-#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +-#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +-#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +-#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +-#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +-#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ +- +- +-/* SPI.INTCTRL bit masks and bit positions */ +-#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +-#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +-/* SPI.STATUS bit masks and bit positions */ +-#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +-#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ +- +-#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +-#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +- +- +-/* IRCOM - IR Communication Module */ +-/* IRCOM.CTRL bit masks and bit positions */ +-#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +-#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +-#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +-#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +-#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +-#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +-#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +-#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +-#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +-#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ +- +- +-/* AES - AES Module */ +-/* AES.CTRL bit masks and bit positions */ +-#define AES_START_bm 0x80 /* Start/Run bit mask. */ +-#define AES_START_bp 7 /* Start/Run bit position. */ +- +-#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +-#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ +- +-#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +-#define AES_RESET_bp 5 /* AES Software Reset bit position. */ +- +-#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +-#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ +- +-#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +-#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ +- +- +-/* AES.STATUS bit masks and bit positions */ +-#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +-#define AES_ERROR_bp 7 /* AES Error bit position. */ +- +-#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +-#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ +- +- +-/* AES.INTCTRL bit masks and bit positions */ +-#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +-#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +- +-// Generic Port Pins +- +-#define PIN0_bm 0x01 +-#define PIN0_bp 0 +-#define PIN1_bm 0x02 +-#define PIN1_bp 1 +-#define PIN2_bm 0x04 +-#define PIN2_bp 2 +-#define PIN3_bm 0x08 +-#define PIN3_bp 3 +-#define PIN4_bm 0x10 +-#define PIN4_bp 4 +-#define PIN5_bm 0x20 +-#define PIN5_bp 5 +-#define PIN6_bm 0x40 +-#define PIN6_bp 6 +-#define PIN7_bm 0x80 +-#define PIN7_bp 7 +- +- +-/* ========== Interrupt Vector Definitions ========== */ +-/* Vector 0 is the reset vector */ +- +-/* OSC interrupt vectors */ +-#define OSC_XOSCF_vect_num 1 +-#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ +- +-/* PORTC interrupt vectors */ +-#define PORTC_INT0_vect_num 2 +-#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +-#define PORTC_INT1_vect_num 3 +-#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ +- +-/* PORTR interrupt vectors */ +-#define PORTR_INT0_vect_num 4 +-#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +-#define PORTR_INT1_vect_num 5 +-#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ +- +-/* DMA interrupt vectors */ +-#define DMA_CH0_vect_num 6 +-#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +-#define DMA_CH1_vect_num 7 +-#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +-#define DMA_CH2_vect_num 8 +-#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +-#define DMA_CH3_vect_num 9 +-#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ +- +-/* RTC interrupt vectors */ +-#define RTC_OVF_vect_num 10 +-#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +-#define RTC_COMP_vect_num 11 +-#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ +- +-/* TWIC interrupt vectors */ +-#define TWIC_TWIS_vect_num 12 +-#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +-#define TWIC_TWIM_vect_num 13 +-#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ +- +-/* TCC0 interrupt vectors */ +-#define TCC0_OVF_vect_num 14 +-#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +-#define TCC0_ERR_vect_num 15 +-#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +-#define TCC0_CCA_vect_num 16 +-#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +-#define TCC0_CCB_vect_num 17 +-#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +-#define TCC0_CCC_vect_num 18 +-#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +-#define TCC0_CCD_vect_num 19 +-#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ +- +-/* TCC1 interrupt vectors */ +-#define TCC1_OVF_vect_num 20 +-#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +-#define TCC1_ERR_vect_num 21 +-#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +-#define TCC1_CCA_vect_num 22 +-#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +-#define TCC1_CCB_vect_num 23 +-#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ +- +-/* SPIC interrupt vectors */ +-#define SPIC_INT_vect_num 24 +-#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ +- +-/* USARTC0 interrupt vectors */ +-#define USARTC0_RXC_vect_num 25 +-#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +-#define USARTC0_DRE_vect_num 26 +-#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +-#define USARTC0_TXC_vect_num 27 +-#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ +- +-/* USARTC1 interrupt vectors */ +-#define USARTC1_RXC_vect_num 28 +-#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +-#define USARTC1_DRE_vect_num 29 +-#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +-#define USARTC1_TXC_vect_num 30 +-#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ +- +-/* AES interrupt vectors */ +-#define AES_INT_vect_num 31 +-#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ +- +-/* NVM interrupt vectors */ +-#define NVM_EE_vect_num 32 +-#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +-#define NVM_SPM_vect_num 33 +-#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ +- +-/* PORTB interrupt vectors */ +-#define PORTB_INT0_vect_num 34 +-#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +-#define PORTB_INT1_vect_num 35 +-#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ +- +-/* ACB interrupt vectors */ +-#define ACB_AC0_vect_num 36 +-#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ +-#define ACB_AC1_vect_num 37 +-#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ +-#define ACB_ACW_vect_num 38 +-#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ +- +-/* ADCB interrupt vectors */ +-#define ADCB_CH0_vect_num 39 +-#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ +-#define ADCB_CH1_vect_num 40 +-#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ +-#define ADCB_CH2_vect_num 41 +-#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ +-#define ADCB_CH3_vect_num 42 +-#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ +- +-/* PORTE interrupt vectors */ +-#define PORTE_INT0_vect_num 43 +-#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +-#define PORTE_INT1_vect_num 44 +-#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ +- +-/* TWIE interrupt vectors */ +-#define TWIE_TWIS_vect_num 45 +-#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +-#define TWIE_TWIM_vect_num 46 +-#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ +- +-/* TCE0 interrupt vectors */ +-#define TCE0_OVF_vect_num 47 +-#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +-#define TCE0_ERR_vect_num 48 +-#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +-#define TCE0_CCA_vect_num 49 +-#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +-#define TCE0_CCB_vect_num 50 +-#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +-#define TCE0_CCC_vect_num 51 +-#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +-#define TCE0_CCD_vect_num 52 +-#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ +- +-/* TCE1 interrupt vectors */ +-#define TCE1_OVF_vect_num 53 +-#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ +-#define TCE1_ERR_vect_num 54 +-#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ +-#define TCE1_CCA_vect_num 55 +-#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ +-#define TCE1_CCB_vect_num 56 +-#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ +- +-/* SPIE interrupt vectors */ +-#define SPIE_INT_vect_num 57 +-#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ +- +-/* USARTE0 interrupt vectors */ +-#define USARTE0_RXC_vect_num 58 +-#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +-#define USARTE0_DRE_vect_num 59 +-#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +-#define USARTE0_TXC_vect_num 60 +-#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ +- +-/* USARTE1 interrupt vectors */ +-#define USARTE1_RXC_vect_num 61 +-#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ +-#define USARTE1_DRE_vect_num 62 +-#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ +-#define USARTE1_TXC_vect_num 63 +-#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ +- +-/* PORTD interrupt vectors */ +-#define PORTD_INT0_vect_num 64 +-#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +-#define PORTD_INT1_vect_num 65 +-#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ +- +-/* PORTA interrupt vectors */ +-#define PORTA_INT0_vect_num 66 +-#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +-#define PORTA_INT1_vect_num 67 +-#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ +- +-/* ACA interrupt vectors */ +-#define ACA_AC0_vect_num 68 +-#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +-#define ACA_AC1_vect_num 69 +-#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +-#define ACA_ACW_vect_num 70 +-#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ +- +-/* ADCA interrupt vectors */ +-#define ADCA_CH0_vect_num 71 +-#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +-#define ADCA_CH1_vect_num 72 +-#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +-#define ADCA_CH2_vect_num 73 +-#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +-#define ADCA_CH3_vect_num 74 +-#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ +- +-/* TCD0 interrupt vectors */ +-#define TCD0_OVF_vect_num 77 +-#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +-#define TCD0_ERR_vect_num 78 +-#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +-#define TCD0_CCA_vect_num 79 +-#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +-#define TCD0_CCB_vect_num 80 +-#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +-#define TCD0_CCC_vect_num 81 +-#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +-#define TCD0_CCD_vect_num 82 +-#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ +- +-/* TCD1 interrupt vectors */ +-#define TCD1_OVF_vect_num 83 +-#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +-#define TCD1_ERR_vect_num 84 +-#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +-#define TCD1_CCA_vect_num 85 +-#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +-#define TCD1_CCB_vect_num 86 +-#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ +- +-/* SPID interrupt vectors */ +-#define SPID_INT_vect_num 87 +-#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ +- +-/* USARTD0 interrupt vectors */ +-#define USARTD0_RXC_vect_num 88 +-#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +-#define USARTD0_DRE_vect_num 89 +-#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +-#define USARTD0_TXC_vect_num 90 +-#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ +- +-/* USARTD1 interrupt vectors */ +-#define USARTD1_RXC_vect_num 91 +-#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +-#define USARTD1_DRE_vect_num 92 +-#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +-#define USARTD1_TXC_vect_num 93 +-#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ +- +-/* PORTF interrupt vectors */ +-#define PORTF_INT0_vect_num 104 +-#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +-#define PORTF_INT1_vect_num 105 +-#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ +- +-/* TCF0 interrupt vectors */ +-#define TCF0_OVF_vect_num 108 +-#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ +-#define TCF0_ERR_vect_num 109 +-#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ +-#define TCF0_CCA_vect_num 110 +-#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ +-#define TCF0_CCB_vect_num 111 +-#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ +-#define TCF0_CCC_vect_num 112 +-#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ +-#define TCF0_CCD_vect_num 113 +-#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ +- +-/* USARTF0 interrupt vectors */ +-#define USARTF0_RXC_vect_num 119 +-#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ +-#define USARTF0_DRE_vect_num 120 +-#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ +-#define USARTF0_TXC_vect_num 121 +-#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ +- +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (122 * _VECTOR_SIZE) +- +- +-/* ========== Constants ========== */ +- +-#define PROGMEM_START (0x0000) +-#define PROGMEM_SIZE (270336) +-#define PROGMEM_PAGE_SIZE (512) +-#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) +- +-#define APP_SECTION_START (0x0000) +-#define APP_SECTION_SIZE (262144) +-#define APP_SECTION_PAGE_SIZE (512) +-#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) +- +-#define APPTABLE_SECTION_START (0x3E000) +-#define APPTABLE_SECTION_SIZE (8192) +-#define APPTABLE_SECTION_PAGE_SIZE (512) +-#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) +- +-#define BOOT_SECTION_START (0x40000) +-#define BOOT_SECTION_SIZE (8192) +-#define BOOT_SECTION_PAGE_SIZE (512) +-#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) +- +-#define DATAMEM_START (0x0000) +-#define DATAMEM_SIZE (24576) +-#define DATAMEM_PAGE_SIZE (0) +-#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) +- +-#define IO_START (0x0000) +-#define IO_SIZE (4096) +-#define IO_PAGE_SIZE (0) +-#define IO_END (IO_START + IO_SIZE - 1) +- +-#define MAPPED_EEPROM_START (0x1000) +-#define MAPPED_EEPROM_SIZE (4096) +-#define MAPPED_EEPROM_PAGE_SIZE (0) +-#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) +- +-#define INTERNAL_SRAM_START (0x2000) +-#define INTERNAL_SRAM_SIZE (16384) +-#define INTERNAL_SRAM_PAGE_SIZE (0) +-#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) +- +-#define EEPROM_START (0x0000) +-#define EEPROM_SIZE (4096) +-#define EEPROM_PAGE_SIZE (32) +-#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) +- +-#define FUSE_START (0x0000) +-#define FUSE_SIZE (6) +-#define FUSE_PAGE_SIZE (0) +-#define FUSE_END (FUSE_START + FUSE_SIZE - 1) +- +-#define LOCKBIT_START (0x0000) +-#define LOCKBIT_SIZE (1) +-#define LOCKBIT_PAGE_SIZE (0) +-#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) +- +-#define SIGNATURES_START (0x0000) +-#define SIGNATURES_SIZE (3) +-#define SIGNATURES_PAGE_SIZE (0) +-#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) +- +-#define USER_SIGNATURES_START (0x0000) +-#define USER_SIGNATURES_SIZE (512) +-#define USER_SIGNATURES_PAGE_SIZE (0) +-#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) +- +-#define PROD_SIGNATURES_START (0x0000) +-#define PROD_SIGNATURES_SIZE (52) +-#define PROD_SIGNATURES_PAGE_SIZE (0) +-#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) +- +-#define FLASHEND PROGMEM_END +-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +-#define RAMSTART INTERNAL_SRAM_START +-#define RAMSIZE INTERNAL_SRAM_SIZE +-#define RAMEND INTERNAL_SRAM_END +-#define XRAMSTART EXTERNAL_SRAM_START +-#define XRAMSIZE EXTERNAL_SRAM_SIZE +-#define XRAMEND INTERNAL_SRAM_END +-#define E2END EEPROM_END +-#define E2PAGESIZE EEPROM_PAGE_SIZE +- +- +-/* ========== Fuses ========== */ +-#define FUSE_MEMORY_SIZE 6 +- +-/* Fuse Byte 0 */ +-#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ +-#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ +-#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ +-#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ +-#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ +-#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ +-#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ +-#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ +-#define FUSE0_DEFAULT (0xFF) +- +-/* Fuse Byte 1 */ +-#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +-#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +-#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +-#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +-#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +-#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +-#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +-#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +-#define FUSE1_DEFAULT (0xFF) +- +-/* Fuse Byte 2 */ +-#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +-#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +-#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +-#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +-#define FUSE2_DEFAULT (0xFF) +- +-/* Fuse Byte 3 Reserved */ +- +-/* Fuse Byte 4 */ +-#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ +-#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +-#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +-#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +-#define FUSE4_DEFAULT (0xFF) +- +-/* Fuse Byte 5 */ +-#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +-#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +-#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +-#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +-#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +-#define FUSE5_DEFAULT (0xFF) +- +- +-/* ========== Lock Bits ========== */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_BITS_EXIST +-#define __BOOT_LOCK_BOOT_BITS_EXIST +- +- +-/* ========== Signature ========== */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x98 +-#define SIGNATURE_2 0x42 +- +- +-#endif /* _AVR_ATxmega256A3_H_ */ +- ++/* Copyright (c) 2009-2010 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iox256a3.h 2200 2010-12-14 04:24:24Z arcanum $ */ ++ ++/* avr/iox256a3.h - definitions for ATxmega256A3 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox256a3.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATxmega256A3_H_ ++#define _AVR_ATxmega256A3_H_ 1 ++ ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++} CLK_t; ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t PRPB; /* Power Reduction Port B */ ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ ++} CLK_RTCSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control REgister */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t reserved_0x07; ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Channel */ ++typedef struct DMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Address Control */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ ++ register8_t REPCNT; /* Channel Repeat Count */ ++ register8_t reserved_0x07; ++ register8_t SRCADDR0; /* Channel Source Address 0 */ ++ register8_t SRCADDR1; /* Channel Source Address 1 */ ++ register8_t SRCADDR2; /* Channel Source Address 2 */ ++ register8_t reserved_0x0B; ++ register8_t DESTADDR0; /* Channel Destination Address 0 */ ++ register8_t DESTADDR1; /* Channel Destination Address 1 */ ++ register8_t DESTADDR2; /* Channel Destination Address 2 */ ++ register8_t reserved_0x0F; ++} DMA_CH_t; ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Controller */ ++typedef struct DMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ DMA_CH_t CH0; /* DMA Channel 0 */ ++ DMA_CH_t CH1; /* DMA Channel 1 */ ++ DMA_CH_t CH2; /* DMA Channel 2 */ ++ DMA_CH_t CH3; /* DMA Channel 3 */ ++} DMA_t; ++ ++/* Burst mode */ ++typedef enum DMA_CH_BURSTLEN_enum ++{ ++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ ++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ ++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ ++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ ++} DMA_CH_BURSTLEN_t; ++ ++/* Source address reload mode */ ++typedef enum DMA_CH_SRCRELOAD_enum ++{ ++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ ++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ ++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ ++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ ++} DMA_CH_SRCRELOAD_t; ++ ++/* Source addressing mode */ ++typedef enum DMA_CH_SRCDIR_enum ++{ ++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ ++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ ++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ ++} DMA_CH_SRCDIR_t; ++ ++/* Destination adress reload mode */ ++typedef enum DMA_CH_DESTRELOAD_enum ++{ ++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ ++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ ++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ ++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ ++} DMA_CH_DESTRELOAD_t; ++ ++/* Destination adressing mode */ ++typedef enum DMA_CH_DESTDIR_enum ++{ ++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ ++} DMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum DMA_CH_TRIGSRC_enum ++{ ++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ ++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ ++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ ++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ ++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ ++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ ++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ ++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ ++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ ++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ ++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ ++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ ++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ ++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ ++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ ++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ ++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ ++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ ++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ ++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ ++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ ++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ ++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ ++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ ++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ ++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ ++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ ++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ ++} DMA_CH_TRIGSRC_t; ++ ++/* Double buffering mode */ ++typedef enum DMA_DBUFMODE_enum ++{ ++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ ++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ ++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ ++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ ++} DMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum DMA_PRIMODE_enum ++{ ++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ ++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ ++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ ++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ ++} DMA_PRIMODE_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_ERRINTLVL_enum ++{ ++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ ++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ ++} DMA_CH_ERRINTLVL_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_TRNINTLVL_enum ++{ ++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ ++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ ++} DMA_CH_TRNINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ ++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ ++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ ++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t CH4CTRL; /* Channel 4 Control Register */ ++ register8_t CH5CTRL; /* Channel 5 Control Register */ ++ register8_t CH6CTRL; /* Channel 6 Control Register */ ++ register8_t CH7CTRL; /* Channel 7 Control Register */ ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ ++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ ++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ ++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ ++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ ++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ ++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ ++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ ++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ ++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ ++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ ++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ ++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ ++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ ++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ ++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ ++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ ++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t FUSEBYTE0; /* JTAG User ID */ ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ ++ register8_t reserved_0x01; ++ register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ ++ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ ++ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ ++ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++} NVM_PROD_SIGNATURES_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++} NVM_LB_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brown Out Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ ++ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Comparator 0 Control */ ++ register8_t AC1CTRL; /* Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t reserved_0x6; ++ register8_t reserved_0x7; ++} ADC_CH_t; ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ _WORDREGISTER(CH1RES); /* Channel 1 Result */ ++ _WORDREGISTER(CH2RES); /* Channel 2 Result */ ++ _WORDREGISTER(CH3RES); /* Channel 3 Result */ ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++ ADC_CH_t CH1; /* ADC Channel 1 */ ++ ADC_CH_t CH2; /* ADC Channel 2 */ ++ ADC_CH_t CH3; /* ADC Channel 3 */ ++} ADC_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++} ADC_REFSEL_t; ++ ++/* Channel sweep selection */ ++typedef enum ADC_SWEEP_enum ++{ ++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ ++} ADC_SWEEP_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ++ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* DMA request selection */ ++typedef enum ADC_DMASEL_enum ++{ ++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ ++} ADC_DMASEL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DAC - Digital/Analog Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Digital-to-Analog Converter */ ++typedef struct DAC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t EVCTRL; /* Event Input Control */ ++ register8_t TIMCTRL; /* Timing Control */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t GAINCAL; /* Gain Calibration */ ++ register8_t OFFSETCAL; /* Offset Calibration */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ ++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ ++} DAC_t; ++ ++/* Output channel selection */ ++typedef enum DAC_CHSEL_enum ++{ ++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ ++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ ++} DAC_CHSEL_t; ++ ++/* Reference voltage selection */ ++typedef enum DAC_REFSEL_enum ++{ ++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ ++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ ++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ ++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ ++} DAC_REFSEL_t; ++ ++/* Event channel selection */ ++typedef enum DAC_EVSEL_enum ++{ ++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ ++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ ++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ ++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ ++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ ++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ ++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ ++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ ++} DAC_EVSEL_t; ++ ++/* Conversion interval */ ++typedef enum DAC_CONINTVAL_enum ++{ ++ DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ ++ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ ++ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ ++ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ ++ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ ++ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ ++ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ ++ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ ++} DAC_CONINTVAL_t; ++ ++/* Refresh rate */ ++typedef enum DAC_REFRESH_enum ++{ ++ DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ ++ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ ++ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ ++ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ ++ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ ++ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ ++ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ ++ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ ++ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ ++ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ ++ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ ++ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ ++ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ ++ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ ++} DAC_REFRESH_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Clounter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* EBI Chip Select Module */ ++typedef struct EBI_CS_struct ++{ ++ register8_t CTRLA; /* Chip Select Control Register A */ ++ register8_t CTRLB; /* Chip Select Control Register B */ ++ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ ++} EBI_CS_t; ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* External Bus Interface */ ++typedef struct EBI_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ ++ register8_t reserved_0x02; ++ register8_t reserved_0x03; ++ _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ ++ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ ++ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ ++ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ EBI_CS_t CS0; /* Chip Select 0 */ ++ EBI_CS_t CS1; /* Chip Select 1 */ ++ EBI_CS_t CS2; /* Chip Select 2 */ ++ EBI_CS_t CS3; /* Chip Select 3 */ ++} EBI_t; ++ ++/* Chip Select adress space */ ++typedef enum EBI_CS_ASIZE_enum ++{ ++ EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ ++ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ ++ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ ++ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ ++ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ ++ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ ++ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ ++ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ ++ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ ++ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ ++ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ ++ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ ++ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ ++ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ ++ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ ++ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ ++ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ ++} EBI_CS_ASIZE_t; ++ ++/* */ ++typedef enum EBI_CS_SRWS_enum ++{ ++ EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_CS_SRWS_t; ++ ++/* Chip Select address mode */ ++typedef enum EBI_CS_MODE_enum ++{ ++ EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ ++ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ ++ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ ++ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ ++} EBI_CS_MODE_t; ++ ++/* Chip Select SDRAM mode */ ++typedef enum EBI_CS_SDMODE_enum ++{ ++ EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ ++ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ ++} EBI_CS_SDMODE_t; ++ ++/* */ ++typedef enum EBI_SDDATAW_enum ++{ ++ EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ ++ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ ++} EBI_SDDATAW_t; ++ ++/* */ ++typedef enum EBI_LPCMODE_enum ++{ ++ EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ ++ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ ++} EBI_LPCMODE_t; ++ ++/* */ ++typedef enum EBI_SRMODE_enum ++{ ++ EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ ++ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ ++ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ ++ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ ++} EBI_SRMODE_t; ++ ++/* */ ++typedef enum EBI_IFMODE_enum ++{ ++ EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ ++ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ ++ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ ++ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ ++} EBI_IFMODE_t; ++ ++/* */ ++typedef enum EBI_SDCOL_enum ++{ ++ EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ ++ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ ++ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ ++ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ ++} EBI_SDCOL_t; ++ ++/* */ ++typedef enum EBI_MRDLY_enum ++{ ++ EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_MRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCYCDLY_enum ++{ ++ EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ROWCYCDLY_t; ++ ++/* */ ++typedef enum EBI_RPDLY_enum ++{ ++ EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_RPDLY_t; ++ ++/* */ ++typedef enum EBI_WRDLY_enum ++{ ++ EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_WRDLY_t; ++ ++/* */ ++typedef enum EBI_ESRDLY_enum ++{ ++ EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ESRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCOLDLY_enum ++{ ++ EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_ROWCOLDLY_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++} PORTCFG_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Virtual Port 0 Mapping */ ++typedef enum PORTCFG_VP0MAP_enum ++{ ++ PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP0MAP_t; ++ ++/* Virtual Port 1 Mapping */ ++typedef enum PORTCFG_VP1MAP_enum ++{ ++ PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP1MAP_t; ++ ++/* Virtual Port 2 Mapping */ ++typedef enum PORTCFG_VP2MAP_enum ++{ ++ PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP2MAP_t; ++ ++/* Virtual Port 3 Mapping */ ++typedef enum PORTCFG_VP3MAP_enum ++{ ++ PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP3MAP_t; ++ ++/* Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x05; ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AES - AES Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* AES Module */ ++typedef struct AES_struct ++{ ++ register8_t CTRL; /* AES Control Register */ ++ register8_t STATUS; /* AES Status Register */ ++ register8_t STATE; /* AES State Register */ ++ register8_t KEY; /* AES Key Register */ ++ register8_t INTCTRL; /* AES Interrupt Control Register */ ++} AES_t; ++ ++/* Interrupt level */ ++typedef enum AES_INTLVL_enum ++{ ++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} AES_INTLVL_t; ++ ++ ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset Controller */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ ++#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ ++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ ++#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ ++#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ ++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ ++#define PORTA (*(PORT_t *) 0x0600) /* Port A */ ++#define PORTB (*(PORT_t *) 0x0620) /* Port B */ ++#define PORTC (*(PORT_t *) 0x0640) /* Port C */ ++#define PORTD (*(PORT_t *) 0x0660) /* Port D */ ++#define PORTE (*(PORT_t *) 0x0680) /* Port E */ ++#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ ++#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ ++#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ ++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ ++#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ ++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ ++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ ++#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ ++#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ ++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ ++#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ ++#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ ++#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ ++#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ ++#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ ++#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ ++#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++#define GPIO_GPIOR4 _SFR_MEM8(0x0004) ++#define GPIO_GPIOR5 _SFR_MEM8(0x0005) ++#define GPIO_GPIOR6 _SFR_MEM8(0x0006) ++#define GPIO_GPIOR7 _SFR_MEM8(0x0007) ++#define GPIO_GPIOR8 _SFR_MEM8(0x0008) ++#define GPIO_GPIOR9 _SFR_MEM8(0x0009) ++#define GPIO_GPIORA _SFR_MEM8(0x000A) ++#define GPIO_GPIORB _SFR_MEM8(0x000B) ++#define GPIO_GPIORC _SFR_MEM8(0x000C) ++#define GPIO_GPIORD _SFR_MEM8(0x000D) ++#define GPIO_GPIORE _SFR_MEM8(0x000E) ++#define GPIO_GPIORF _SFR_MEM8(0x000F) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++#define GPIO_GPIO4 _SFR_MEM8(0x0004) ++#define GPIO_GPIO5 _SFR_MEM8(0x0005) ++#define GPIO_GPIO6 _SFR_MEM8(0x0006) ++#define GPIO_GPIO7 _SFR_MEM8(0x0007) ++#define GPIO_GPIO8 _SFR_MEM8(0x0008) ++#define GPIO_GPIO9 _SFR_MEM8(0x0009) ++#define GPIO_GPIOA _SFR_MEM8(0x000A) ++#define GPIO_GPIOB _SFR_MEM8(0x000B) ++#define GPIO_GPIOC _SFR_MEM8(0x000C) ++#define GPIO_GPIOD _SFR_MEM8(0x000D) ++#define GPIO_GPIOE _SFR_MEM8(0x000E) ++#define GPIO_GPIOF _SFR_MEM8(0x000F) ++ ++/* VPORT0 - Virtual Port 0 */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT1 - Virtual Port 1 */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT2 - Virtual Port 2 */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT3 - Virtual Port 3 */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU Registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator Control */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPB _SFR_MEM8(0x0072) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset Controller */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - Port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++ ++/* AES - AES Crypto Module */ ++#define AES_CTRL _SFR_MEM8(0x00C0) ++#define AES_STATUS _SFR_MEM8(0x00C1) ++#define AES_STATE _SFR_MEM8(0x00C2) ++#define AES_KEY _SFR_MEM8(0x00C3) ++#define AES_INTCTRL _SFR_MEM8(0x00C4) ++ ++/* DMA - DMA Controller */ ++#define DMA_CTRL _SFR_MEM8(0x0100) ++#define DMA_INTFLAGS _SFR_MEM8(0x0103) ++#define DMA_STATUS _SFR_MEM8(0x0104) ++#define DMA_TEMP _SFR_MEM16(0x0106) ++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) ++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) ++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) ++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) ++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) ++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) ++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) ++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) ++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) ++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) ++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) ++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) ++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) ++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) ++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) ++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) ++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) ++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) ++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) ++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) ++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) ++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) ++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) ++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) ++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) ++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) ++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) ++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) ++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) ++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) ++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) ++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) ++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) ++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) ++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) ++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) ++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) ++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) ++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) ++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) ++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) ++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH4MUX _SFR_MEM8(0x0184) ++#define EVSYS_CH5MUX _SFR_MEM8(0x0185) ++#define EVSYS_CH6MUX _SFR_MEM8(0x0186) ++#define EVSYS_CH7MUX _SFR_MEM8(0x0187) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) ++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) ++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) ++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non Volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADCA - Analog to Digital Converter A */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CH1RES _SFR_MEM16(0x0212) ++#define ADCA_CH2RES _SFR_MEM16(0x0214) ++#define ADCA_CH3RES _SFR_MEM16(0x0216) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) ++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) ++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) ++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) ++#define ADCA_CH1_RES _SFR_MEM16(0x022C) ++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) ++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) ++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) ++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) ++#define ADCA_CH2_RES _SFR_MEM16(0x0234) ++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) ++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) ++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) ++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) ++#define ADCA_CH3_RES _SFR_MEM16(0x023C) ++ ++/* ADCB - Analog to Digital Converter B */ ++#define ADCB_CTRLA _SFR_MEM8(0x0240) ++#define ADCB_CTRLB _SFR_MEM8(0x0241) ++#define ADCB_REFCTRL _SFR_MEM8(0x0242) ++#define ADCB_EVCTRL _SFR_MEM8(0x0243) ++#define ADCB_PRESCALER _SFR_MEM8(0x0244) ++#define ADCB_INTFLAGS _SFR_MEM8(0x0246) ++#define ADCB_CAL _SFR_MEM16(0x024C) ++#define ADCB_CH0RES _SFR_MEM16(0x0250) ++#define ADCB_CH1RES _SFR_MEM16(0x0252) ++#define ADCB_CH2RES _SFR_MEM16(0x0254) ++#define ADCB_CH3RES _SFR_MEM16(0x0256) ++#define ADCB_CMP _SFR_MEM16(0x0258) ++#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) ++#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) ++#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) ++#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) ++#define ADCB_CH0_RES _SFR_MEM16(0x0264) ++#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) ++#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) ++#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) ++#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) ++#define ADCB_CH1_RES _SFR_MEM16(0x026C) ++#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) ++#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) ++#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) ++#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) ++#define ADCB_CH2_RES _SFR_MEM16(0x0274) ++#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) ++#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) ++#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) ++#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) ++#define ADCB_CH3_RES _SFR_MEM16(0x027C) ++ ++/* DACB - Digital to Analog Converter B */ ++#define DACB_CTRLA _SFR_MEM8(0x0320) ++#define DACB_CTRLB _SFR_MEM8(0x0321) ++#define DACB_CTRLC _SFR_MEM8(0x0322) ++#define DACB_EVCTRL _SFR_MEM8(0x0323) ++#define DACB_TIMCTRL _SFR_MEM8(0x0324) ++#define DACB_STATUS _SFR_MEM8(0x0325) ++#define DACB_GAINCAL _SFR_MEM8(0x0328) ++#define DACB_OFFSETCAL _SFR_MEM8(0x0329) ++#define DACB_CH0DATA _SFR_MEM16(0x0338) ++#define DACB_CH1DATA _SFR_MEM16(0x033A) ++ ++/* ACA - Analog Comparator A */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* ACB - Analog Comparator B */ ++#define ACB_AC0CTRL _SFR_MEM8(0x0390) ++#define ACB_AC1CTRL _SFR_MEM8(0x0391) ++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) ++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) ++#define ACB_CTRLA _SFR_MEM8(0x0394) ++#define ACB_CTRLB _SFR_MEM8(0x0395) ++#define ACB_WINCTRL _SFR_MEM8(0x0396) ++#define ACB_STATUS _SFR_MEM8(0x0397) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWIC - Two-Wire Interface C */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWIE - Two-Wire Interface E */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* PORTA - Port A */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORTB - Port B */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORTC - Port C */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORTD - Port D */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORTE - Port E */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORTF - Port F */ ++#define PORTF_DIR _SFR_MEM8(0x06A0) ++#define PORTF_DIRSET _SFR_MEM8(0x06A1) ++#define PORTF_DIRCLR _SFR_MEM8(0x06A2) ++#define PORTF_DIRTGL _SFR_MEM8(0x06A3) ++#define PORTF_OUT _SFR_MEM8(0x06A4) ++#define PORTF_OUTSET _SFR_MEM8(0x06A5) ++#define PORTF_OUTCLR _SFR_MEM8(0x06A6) ++#define PORTF_OUTTGL _SFR_MEM8(0x06A7) ++#define PORTF_IN _SFR_MEM8(0x06A8) ++#define PORTF_INTCTRL _SFR_MEM8(0x06A9) ++#define PORTF_INT0MASK _SFR_MEM8(0x06AA) ++#define PORTF_INT1MASK _SFR_MEM8(0x06AB) ++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) ++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) ++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) ++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) ++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) ++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) ++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) ++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) ++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) ++ ++/* PORTR - Port R */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TCC0 - Timer/Counter C0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TCC1 - Timer/Counter C1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEXC - Advanced Waveform Extension C */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRESC - High-Resolution Extension C */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ ++#define USARTC1_DATA _SFR_MEM8(0x08B0) ++#define USARTC1_STATUS _SFR_MEM8(0x08B1) ++#define USARTC1_CTRLA _SFR_MEM8(0x08B3) ++#define USARTC1_CTRLB _SFR_MEM8(0x08B4) ++#define USARTC1_CTRLC _SFR_MEM8(0x08B5) ++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) ++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) ++ ++/* SPIC - Serial Peripheral Interface C */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TCD0 - Timer/Counter D0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TCD1 - Timer/Counter D1 */ ++#define TCD1_CTRLA _SFR_MEM8(0x0940) ++#define TCD1_CTRLB _SFR_MEM8(0x0941) ++#define TCD1_CTRLC _SFR_MEM8(0x0942) ++#define TCD1_CTRLD _SFR_MEM8(0x0943) ++#define TCD1_CTRLE _SFR_MEM8(0x0944) ++#define TCD1_INTCTRLA _SFR_MEM8(0x0946) ++#define TCD1_INTCTRLB _SFR_MEM8(0x0947) ++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) ++#define TCD1_CTRLFSET _SFR_MEM8(0x0949) ++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) ++#define TCD1_CTRLGSET _SFR_MEM8(0x094B) ++#define TCD1_INTFLAGS _SFR_MEM8(0x094C) ++#define TCD1_TEMP _SFR_MEM8(0x094F) ++#define TCD1_CNT _SFR_MEM16(0x0960) ++#define TCD1_PER _SFR_MEM16(0x0966) ++#define TCD1_CCA _SFR_MEM16(0x0968) ++#define TCD1_CCB _SFR_MEM16(0x096A) ++#define TCD1_PERBUF _SFR_MEM16(0x0976) ++#define TCD1_CCABUF _SFR_MEM16(0x0978) ++#define TCD1_CCBBUF _SFR_MEM16(0x097A) ++ ++/* HIRESD - High-Resolution Extension D */ ++#define HIRESD_CTRLA _SFR_MEM8(0x0990) ++ ++/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ ++#define USARTD1_DATA _SFR_MEM8(0x09B0) ++#define USARTD1_STATUS _SFR_MEM8(0x09B1) ++#define USARTD1_CTRLA _SFR_MEM8(0x09B3) ++#define USARTD1_CTRLB _SFR_MEM8(0x09B4) ++#define USARTD1_CTRLC _SFR_MEM8(0x09B5) ++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) ++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) ++ ++/* SPID - Serial Peripheral Interface D */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TCE0 - Timer/Counter E0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* TCE1 - Timer/Counter E1 */ ++#define TCE1_CTRLA _SFR_MEM8(0x0A40) ++#define TCE1_CTRLB _SFR_MEM8(0x0A41) ++#define TCE1_CTRLC _SFR_MEM8(0x0A42) ++#define TCE1_CTRLD _SFR_MEM8(0x0A43) ++#define TCE1_CTRLE _SFR_MEM8(0x0A44) ++#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) ++#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) ++#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) ++#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) ++#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) ++#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) ++#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) ++#define TCE1_TEMP _SFR_MEM8(0x0A4F) ++#define TCE1_CNT _SFR_MEM16(0x0A60) ++#define TCE1_PER _SFR_MEM16(0x0A66) ++#define TCE1_CCA _SFR_MEM16(0x0A68) ++#define TCE1_CCB _SFR_MEM16(0x0A6A) ++#define TCE1_PERBUF _SFR_MEM16(0x0A76) ++#define TCE1_CCABUF _SFR_MEM16(0x0A78) ++#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) ++ ++/* AWEXE - Advanced Waveform Extension E */ ++#define AWEXE_CTRL _SFR_MEM8(0x0A80) ++#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) ++#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) ++#define AWEXE_STATUS _SFR_MEM8(0x0A84) ++#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) ++#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) ++#define AWEXE_DTLS _SFR_MEM8(0x0A88) ++#define AWEXE_DTHS _SFR_MEM8(0x0A89) ++#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) ++#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) ++#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) ++ ++/* HIRESE - High-Resolution Extension E */ ++#define HIRESE_CTRLA _SFR_MEM8(0x0A90) ++ ++/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ ++#define USARTE1_DATA _SFR_MEM8(0x0AB0) ++#define USARTE1_STATUS _SFR_MEM8(0x0AB1) ++#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) ++#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) ++#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) ++#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) ++#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) ++ ++/* SPIE - Serial Peripheral Interface E */ ++#define SPIE_CTRL _SFR_MEM8(0x0AC0) ++#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) ++#define SPIE_STATUS _SFR_MEM8(0x0AC2) ++#define SPIE_DATA _SFR_MEM8(0x0AC3) ++ ++/* TCF0 - Timer/Counter F0 */ ++#define TCF0_CTRLA _SFR_MEM8(0x0B00) ++#define TCF0_CTRLB _SFR_MEM8(0x0B01) ++#define TCF0_CTRLC _SFR_MEM8(0x0B02) ++#define TCF0_CTRLD _SFR_MEM8(0x0B03) ++#define TCF0_CTRLE _SFR_MEM8(0x0B04) ++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) ++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) ++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) ++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) ++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF0_TEMP _SFR_MEM8(0x0B0F) ++#define TCF0_CNT _SFR_MEM16(0x0B20) ++#define TCF0_PER _SFR_MEM16(0x0B26) ++#define TCF0_CCA _SFR_MEM16(0x0B28) ++#define TCF0_CCB _SFR_MEM16(0x0B2A) ++#define TCF0_CCC _SFR_MEM16(0x0B2C) ++#define TCF0_CCD _SFR_MEM16(0x0B2E) ++#define TCF0_PERBUF _SFR_MEM16(0x0B36) ++#define TCF0_CCABUF _SFR_MEM16(0x0B38) ++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) ++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) ++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) ++ ++/* HIRESF - High-Resolution Extension F */ ++#define HIRESF_CTRLA _SFR_MEM8(0x0B90) ++ ++/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ ++#define USARTF0_DATA _SFR_MEM8(0x0BA0) ++#define USARTF0_STATUS _SFR_MEM8(0x0BA1) ++#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) ++#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) ++#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) ++#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) ++#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) ++ ++/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ ++#define USARTF1_DATA _SFR_MEM8(0x0BB0) ++#define USARTF1_STATUS _SFR_MEM8(0x0BB1) ++#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) ++#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) ++#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) ++#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) ++#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) ++ ++/* SPIF - Serial Peripheral Interface F */ ++#define SPIF_CTRL _SFR_MEM8(0x0BC0) ++#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) ++#define SPIF_STATUS _SFR_MEM8(0x0BC2) ++#define SPIF_DATA _SFR_MEM8(0x0BC3) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR1 bit masks and bit positions */ ++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ ++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ ++ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ ++ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ ++#define PR_EBI_bp 3 /* External Bus Interface bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ ++#define PR_DAC_bp 2 /* Port A DAC bit position. */ ++ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++ ++/* PR.PRPB bit masks and bit positions */ ++/* PR_DAC_bm Predefined. */ ++/* PR_DAC_bp Predefined. */ ++ ++/* PR_ADC_bm Predefined. */ ++/* PR_ADC_bp Predefined. */ ++ ++/* PR_AC_bm Predefined. */ ++/* PR_AC_bp Predefined. */ ++ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ ++ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ ++ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ ++ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ ++#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ ++ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ ++ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ ++ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ ++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ ++ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++ ++/* DMA - DMA Controller */ ++/* DMA_CH.CTRLA bit masks and bit positions */ ++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ ++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ ++ ++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ ++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ ++ ++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ ++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ ++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ ++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ ++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ ++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ ++ ++ ++/* DMA_CH.CTRLB bit masks and bit positions */ ++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ ++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ ++ ++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ ++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ ++ ++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ ++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ ++ ++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ ++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ ++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ ++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ ++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ ++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ ++ ++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ ++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ ++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ ++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ ++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ ++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ ++ ++ ++/* DMA_CH.ADDRCTRL bit masks and bit positions */ ++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ ++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ ++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ ++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ ++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ ++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ ++ ++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ ++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ ++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ ++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ ++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ ++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ ++ ++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ ++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ ++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ ++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ ++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ ++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ ++ ++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ ++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ ++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ ++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ ++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ ++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ ++ ++ ++/* DMA_CH.TRIGSRC bit masks and bit positions */ ++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++ ++/* DMA.CTRL bit masks and bit positions */ ++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define DMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define DMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ ++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ ++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ ++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ ++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ ++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ ++ ++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ ++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ ++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ ++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ ++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ ++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ ++ ++ ++/* DMA.INTFLAGS bit masks and bit positions */ ++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++ ++/* DMA.STATUS bit masks and bit positions */ ++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ ++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ ++ ++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ ++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ ++ ++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ ++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ ++ ++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ ++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ ++ ++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ ++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ ++ ++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ ++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ ++ ++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ ++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ ++ ++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ ++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ ++ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH4MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH5MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH6MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH7MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM_gm Predefined. */ ++/* EVSYS_QDIRM_gp Predefined. */ ++/* EVSYS_QDIRM0_bm Predefined. */ ++/* EVSYS_QDIRM0_bp Predefined. */ ++/* EVSYS_QDIRM1_bm Predefined. */ ++/* EVSYS_QDIRM1_bp Predefined. */ ++ ++/* EVSYS_QDIEN_bm Predefined. */ ++/* EVSYS_QDIEN_bp Predefined. */ ++ ++/* EVSYS_QDEN_bm Predefined. */ ++/* EVSYS_QDEN_bp Predefined. */ ++ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH4CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM_gm Predefined. */ ++/* EVSYS_QDIRM_gp Predefined. */ ++/* EVSYS_QDIRM0_bm Predefined. */ ++/* EVSYS_QDIRM0_bp Predefined. */ ++/* EVSYS_QDIRM1_bm Predefined. */ ++/* EVSYS_QDIRM1_bp Predefined. */ ++ ++/* EVSYS_QDIEN_bm Predefined. */ ++/* EVSYS_QDIEN_bp Predefined. */ ++ ++/* EVSYS_QDEN_bm Predefined. */ ++/* EVSYS_QDEN_bp Predefined. */ ++ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH5CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH6CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH7CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0xFF /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ ++#define NVM_CMD7_bp 7 /* Command bit 7 position. */ ++ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ ++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ ++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ ++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ ++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ ++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ ++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ ++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ ++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ ++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ ++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ ++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ ++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ ++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ ++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ ++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ ++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ ++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ ++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ ++#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ ++ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ ++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ ++ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ ++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE_gm Predefined. */ ++/* AC_INTMODE_gp Predefined. */ ++/* AC_INTMODE0_bm Predefined. */ ++/* AC_INTMODE0_bp Predefined. */ ++/* AC_INTMODE1_bm Predefined. */ ++/* AC_INTMODE1_bp Predefined. */ ++ ++/* AC_INTLVL_gm Predefined. */ ++/* AC_INTLVL_gp Predefined. */ ++/* AC_INTLVL0_bm Predefined. */ ++/* AC_INTLVL0_bp Predefined. */ ++/* AC_INTLVL1_bm Predefined. */ ++/* AC_INTLVL1_bp Predefined. */ ++ ++/* AC_HSMODE_bm Predefined. */ ++/* AC_HSMODE_bp Predefined. */ ++ ++/* AC_HYSMODE_gm Predefined. */ ++/* AC_HYSMODE_gp Predefined. */ ++/* AC_HYSMODE0_bm Predefined. */ ++/* AC_HYSMODE0_bp Predefined. */ ++/* AC_HYSMODE1_bm Predefined. */ ++/* AC_HYSMODE1_bp Predefined. */ ++ ++/* AC_ENABLE_bm Predefined. */ ++/* AC_ENABLE_bp Predefined. */ ++ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS_gm Predefined. */ ++/* AC_MUXPOS_gp Predefined. */ ++/* AC_MUXPOS0_bm Predefined. */ ++/* AC_MUXPOS0_bp Predefined. */ ++/* AC_MUXPOS1_bm Predefined. */ ++/* AC_MUXPOS1_bp Predefined. */ ++/* AC_MUXPOS2_bm Predefined. */ ++/* AC_MUXPOS2_bp Predefined. */ ++ ++/* AC_MUXNEG_gm Predefined. */ ++/* AC_MUXNEG_gp Predefined. */ ++/* AC_MUXNEG0_bm Predefined. */ ++/* AC_MUXNEG0_bp Predefined. */ ++/* AC_MUXNEG1_bm Predefined. */ ++/* AC_MUXNEG1_bp Predefined. */ ++/* AC_MUXNEG2_bm Predefined. */ ++/* AC_MUXNEG2_bp Predefined. */ ++ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ ++ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ ++ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ ++ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ ++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ ++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ ++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ ++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ ++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ ++ ++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ ++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ ++ ++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ ++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ ++ ++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ ++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ ++ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ ++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ ++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ ++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ ++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ ++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ ++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ ++ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ ++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ ++ ++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ ++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ ++ ++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ ++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ ++ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++ ++/* DAC - Digital/Analog Converter */ ++/* DAC.CTRLA bit masks and bit positions */ ++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ ++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ ++ ++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ ++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ ++ ++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ ++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ ++ ++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ ++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ ++ ++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define DAC_ENABLE_bp 0 /* Enable bit position. */ ++ ++ ++/* DAC.CTRLB bit masks and bit positions */ ++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ ++#define DAC_CHSEL_gp 5 /* Channel Select group position. */ ++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ ++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ ++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ ++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ ++ ++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ ++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ ++ ++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ ++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ ++ ++ ++/* DAC.CTRLC bit masks and bit positions */ ++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ ++#define DAC_REFSEL_gp 3 /* Reference Select group position. */ ++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ ++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ ++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ ++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ ++ ++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ ++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ ++ ++ ++/* DAC.EVCTRL bit masks and bit positions */ ++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ ++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ ++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ ++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ ++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ ++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ ++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ ++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ ++ ++ ++/* DAC.TIMCTRL bit masks and bit positions */ ++#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ ++#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ ++#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ ++#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ ++#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ ++#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ ++#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ ++#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ ++ ++#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ ++#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ ++#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ ++#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ ++#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ ++#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ ++#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ ++#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ ++#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ ++#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ ++ ++ ++/* DAC.STATUS bit masks and bit positions */ ++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ ++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ ++ ++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ ++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ ++ ++ ++/* RTC - Real-Time Clounter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* EBI - External Bus Interface */ ++/* EBI_CS.CTRLA bit masks and bit positions */ ++#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ ++#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ ++#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ ++#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ ++#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ ++#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ ++#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ ++#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ ++#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ ++#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ ++#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ ++#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ ++ ++#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ ++#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ ++#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ ++#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ ++#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ ++#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ ++ ++ ++/* EBI_CS.CTRLB bit masks and bit positions */ ++#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ ++#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ ++#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ ++#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ ++#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ ++#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ ++#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ ++#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ ++ ++#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ ++#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ ++ ++#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ ++#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ ++ ++#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ ++#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ ++#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ ++#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ ++#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ ++#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ ++ ++ ++/* EBI.CTRL bit masks and bit positions */ ++#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ ++#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ ++#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ ++#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ ++#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ ++#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ ++ ++#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ ++#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ ++#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ ++#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ ++#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ ++#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ ++ ++#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ ++#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ ++#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ ++#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ ++#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ ++#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ ++ ++#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ ++#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ ++#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ ++#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ ++#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ ++#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLA bit masks and bit positions */ ++#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ ++#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ ++ ++#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ ++#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ ++ ++#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ ++#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ ++#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ ++#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ ++#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ ++#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLB bit masks and bit positions */ ++#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ ++#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ ++#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ ++#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ ++#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ ++#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ ++ ++#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ ++#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ ++#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ ++#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ ++#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ ++#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ ++#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ ++#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ ++ ++#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ ++#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ ++#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ ++#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ ++#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ ++#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ ++#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ ++#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ ++ ++ ++/* EBI.SDRAMCTRLC bit masks and bit positions */ ++#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ ++#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ ++#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ ++#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ ++#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ ++#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ ++ ++#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ ++#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ ++#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ ++#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ ++#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ ++#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ ++#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ ++#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ ++ ++#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ ++#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ ++#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ ++#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ ++#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ ++#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ ++#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ ++#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ ++ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ ++#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++ ++/* PORT - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ ++#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ ++ ++#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD_gm Predefined. */ ++/* TC0_CMD_gp Predefined. */ ++/* TC0_CMD0_bm Predefined. */ ++/* TC0_CMD0_bp Predefined. */ ++/* TC0_CMD1_bm Predefined. */ ++/* TC0_CMD1_bp Predefined. */ ++ ++/* TC0_LUPD_bm Predefined. */ ++/* TC0_LUPD_bp Predefined. */ ++ ++/* TC0_DIR_bm Predefined. */ ++/* TC0_DIR_bp Predefined. */ ++ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV_bm Predefined. */ ++/* TC0_CCDBV_bp Predefined. */ ++ ++/* TC0_CCCBV_bm Predefined. */ ++/* TC0_CCCBV_bp Predefined. */ ++ ++/* TC0_CCBBV_bm Predefined. */ ++/* TC0_CCBBV_bp Predefined. */ ++ ++/* TC0_CCABV_bm Predefined. */ ++/* TC0_CCABV_bp Predefined. */ ++ ++/* TC0_PERBV_bm Predefined. */ ++/* TC0_PERBV_bp Predefined. */ ++ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ ++#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ ++ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD_gm Predefined. */ ++/* TC1_CMD_gp Predefined. */ ++/* TC1_CMD0_bm Predefined. */ ++/* TC1_CMD0_bp Predefined. */ ++/* TC1_CMD1_bm Predefined. */ ++/* TC1_CMD1_bp Predefined. */ ++ ++/* TC1_LUPD_bm Predefined. */ ++/* TC1_LUPD_bp Predefined. */ ++ ++/* TC1_DIR_bm Predefined. */ ++/* TC1_DIR_bp Predefined. */ ++ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV_bm Predefined. */ ++/* TC1_CCBBV_bp Predefined. */ ++ ++/* TC1_CCABV_bm Predefined. */ ++/* TC1_CCABV_bp Predefined. */ ++ ++/* TC1_PERBV_bm Predefined. */ ++/* TC1_PERBV_bp Predefined. */ ++ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++ ++/* HIRES.CTRL bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL_gm Predefined. */ ++/* USART_BSEL_gp Predefined. */ ++/* USART_BSEL0_bm Predefined. */ ++/* USART_BSEL0_bp Predefined. */ ++/* USART_BSEL1_bm Predefined. */ ++/* USART_BSEL1_bp Predefined. */ ++/* USART_BSEL2_bm Predefined. */ ++/* USART_BSEL2_bp Predefined. */ ++/* USART_BSEL3_bm Predefined. */ ++/* USART_BSEL3_bp Predefined. */ ++ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++ ++/* AES - AES Module */ ++/* AES.CTRL bit masks and bit positions */ ++#define AES_START_bm 0x80 /* Start/Run bit mask. */ ++#define AES_START_bp 7 /* Start/Run bit position. */ ++ ++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ ++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ ++ ++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ ++#define AES_RESET_bp 5 /* AES Software Reset bit position. */ ++ ++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ ++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ ++ ++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ ++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ ++ ++ ++/* AES.STATUS bit masks and bit positions */ ++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ ++#define AES_ERROR_bp 7 /* AES Error bit position. */ ++ ++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ ++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ ++ ++ ++/* AES.INTCTRL bit masks and bit positions */ ++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define AES_INTLVL_gp 0 /* Interrupt level group position. */ ++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_XOSCF_vect_num 1 ++#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* DMA interrupt vectors */ ++#define DMA_CH0_vect_num 6 ++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ ++#define DMA_CH1_vect_num 7 ++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ ++#define DMA_CH2_vect_num 8 ++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ ++#define DMA_CH3_vect_num 9 ++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* USARTC1 interrupt vectors */ ++#define USARTC1_RXC_vect_num 28 ++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ ++#define USARTC1_DRE_vect_num 29 ++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ ++#define USARTC1_TXC_vect_num 30 ++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ ++ ++/* AES interrupt vectors */ ++#define AES_INT_vect_num 31 ++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* ACB interrupt vectors */ ++#define ACB_AC0_vect_num 36 ++#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ ++#define ACB_AC1_vect_num 37 ++#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ ++#define ACB_ACW_vect_num 38 ++#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ ++ ++/* ADCB interrupt vectors */ ++#define ADCB_CH0_vect_num 39 ++#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ ++#define ADCB_CH1_vect_num 40 ++#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ ++#define ADCB_CH2_vect_num 41 ++#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ ++#define ADCB_CH3_vect_num 42 ++#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* TCE1 interrupt vectors */ ++#define TCE1_OVF_vect_num 53 ++#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ ++#define TCE1_ERR_vect_num 54 ++#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ ++#define TCE1_CCA_vect_num 55 ++#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ ++#define TCE1_CCB_vect_num 56 ++#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ ++ ++/* SPIE interrupt vectors */ ++#define SPIE_INT_vect_num 57 ++#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* USARTE1 interrupt vectors */ ++#define USARTE1_RXC_vect_num 61 ++#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ ++#define USARTE1_DRE_vect_num 62 ++#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ ++#define USARTE1_TXC_vect_num 63 ++#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++#define ADCA_CH1_vect_num 72 ++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ ++#define ADCA_CH2_vect_num 73 ++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ ++#define ADCA_CH3_vect_num 74 ++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD1 interrupt vectors */ ++#define TCD1_OVF_vect_num 83 ++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ ++#define TCD1_ERR_vect_num 84 ++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ ++#define TCD1_CCA_vect_num 85 ++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ ++#define TCD1_CCB_vect_num 86 ++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* USARTD1 interrupt vectors */ ++#define USARTD1_RXC_vect_num 91 ++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ ++#define USARTD1_DRE_vect_num 92 ++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ ++#define USARTD1_TXC_vect_num 93 ++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ ++ ++/* PORTF interrupt vectors */ ++#define PORTF_INT0_vect_num 104 ++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ ++#define PORTF_INT1_vect_num 105 ++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_OVF_vect_num 108 ++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ ++#define TCF0_ERR_vect_num 109 ++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ ++#define TCF0_CCA_vect_num 110 ++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ ++#define TCF0_CCB_vect_num 111 ++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ ++#define TCF0_CCC_vect_num 112 ++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ ++#define TCF0_CCD_vect_num 113 ++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ ++ ++/* USARTF0 interrupt vectors */ ++#define USARTF0_RXC_vect_num 119 ++#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ ++#define USARTF0_DRE_vect_num 120 ++#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ ++#define USARTF0_TXC_vect_num 121 ++#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ ++ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (122 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (270336) ++#define PROGMEM_PAGE_SIZE (512) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (262144) ++#define APP_SECTION_PAGE_SIZE (512) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x3E000) ++#define APPTABLE_SECTION_SIZE (8192) ++#define APPTABLE_SECTION_PAGE_SIZE (512) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x40000) ++#define BOOT_SECTION_SIZE (8192) ++#define BOOT_SECTION_PAGE_SIZE (512) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (24576) ++#define DATAMEM_PAGE_SIZE (0) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (4096) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (16384) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (4096) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define FUSE_START (0x0000) ++#define FUSE_SIZE (6) ++#define FUSE_PAGE_SIZE (0) ++#define FUSE_END (FUSE_START + FUSE_SIZE - 1) ++ ++#define LOCKBIT_START (0x0000) ++#define LOCKBIT_SIZE (1) ++#define LOCKBIT_PAGE_SIZE (0) ++#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (512) ++#define USER_SIGNATURES_PAGE_SIZE (0) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (0) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE PROGMEM_PAGE_SIZE ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define XRAMSTART EXTERNAL_SRAM_START ++#define XRAMSIZE EXTERNAL_SRAM_SIZE ++#define XRAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 */ ++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ ++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ ++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ ++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ ++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ ++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ ++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ ++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ ++#define FUSE0_DEFAULT (0xFF) ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x98 ++#define SIGNATURE_2 0x42 ++ ++ ++#endif /* _AVR_ATxmega256A3_H_ */ ++ +diff --git a/include/avr/iox256a3b.h b/include/avr/iox256a3b.h +index aac039d..8f593f8 100644 +--- a/include/avr/iox256a3b.h ++++ b/include/avr/iox256a3b.h +@@ -1,6924 +1,6914 @@ +-/* Copyright (c) 2009-2010 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iox256a3b.h 2200 2010-12-14 04:24:24Z arcanum $ */ +- +-/* avr/iox256a3b.h - definitions for ATxmega256A3B */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iox256a3b.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATxmega256A3B_H_ +-#define _AVR_ATxmega256A3B_H_ 1 +- +- +-/* Ungrouped common registers */ +-#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +-#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +-#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +-#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +-#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +-#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +-#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +-#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +-#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +-#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +-#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +-#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +-#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +-#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +-#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +-#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +- +-/* Deprecated*/ +-#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +-#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +-#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +-#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +-#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +-#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +-#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +-#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +-#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +-#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +-#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +-#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +-#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +-#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +-#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +-#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +- +- +-#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +-#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +-#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +-#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +-#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +-#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +-#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +-#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +-#define SREG _SFR_MEM8(0x003F) /* Status Register */ +- +- +-/* C Language Only */ +-#if !defined (__ASSEMBLER__) +- +-#include +- +-typedef volatile uint8_t register8_t; +-typedef volatile uint16_t register16_t; +-typedef volatile uint32_t register32_t; +- +- +-#ifdef _WORDREGISTER +-#undef _WORDREGISTER +-#endif +-#define _WORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register16_t regname; \ +- struct \ +- { \ +- register8_t regname ## L; \ +- register8_t regname ## H; \ +- }; \ +- } +- +-#ifdef _DWORDREGISTER +-#undef _DWORDREGISTER +-#endif +-#define _DWORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register32_t regname; \ +- struct \ +- { \ +- register8_t regname ## 0; \ +- register8_t regname ## 1; \ +- register8_t regname ## 2; \ +- register8_t regname ## 3; \ +- }; \ +- } +- +- +-/* +-========================================================================== +-IO Module Structures +-========================================================================== +-*/ +- +- +-/* +--------------------------------------------------------------------------- +-XOCD - On-Chip Debug System +--------------------------------------------------------------------------- +-*/ +- +-/* On-Chip Debug System */ +-typedef struct OCD_struct +-{ +- register8_t OCDR0; /* OCD Register 0 */ +- register8_t OCDR1; /* OCD Register 1 */ +-} OCD_t; +- +- +-/* CCP signatures */ +-typedef enum CCP_enum +-{ +- CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ +- CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +-} CCP_t; +- +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Clock System */ +-typedef struct CLK_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t PSCTRL; /* Prescaler Control Register */ +- register8_t LOCK; /* Lock register */ +- register8_t RTCCTRL; /* RTC Control Register */ +-} CLK_t; +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Power Reduction */ +-typedef struct PR_struct +-{ +- register8_t PRGEN; /* General Power Reduction */ +- register8_t PRPA; /* Power Reduction Port A */ +- register8_t PRPB; /* Power Reduction Port B */ +- register8_t PRPC; /* Power Reduction Port C */ +- register8_t PRPD; /* Power Reduction Port D */ +- register8_t PRPE; /* Power Reduction Port E */ +- register8_t PRPF; /* Power Reduction Port F */ +-} PR_t; +- +-/* System Clock Selection */ +-typedef enum CLK_SCLKSEL_enum +-{ +- CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ +- CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ +- CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ +- CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ +- CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +-} CLK_SCLKSEL_t; +- +-/* Prescaler A Division Factor */ +-typedef enum CLK_PSADIV_enum +-{ +- CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ +- CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ +- CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ +- CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ +- CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ +- CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ +- CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ +- CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ +- CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ +- CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +-} CLK_PSADIV_t; +- +-/* Prescaler B and C Division Factor */ +-typedef enum CLK_PSBCDIV_enum +-{ +- CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ +- CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ +- CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ +- CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +-} CLK_PSBCDIV_t; +- +-/* RTC Clock Source */ +-typedef enum CLK_RTCSRC_enum +-{ +- CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ +- CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ +- CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ +- CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +-} CLK_RTCSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-SLEEP - Sleep Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Sleep Controller */ +-typedef struct SLEEP_struct +-{ +- register8_t CTRL; /* Control Register */ +-} SLEEP_t; +- +-/* Sleep Mode */ +-typedef enum SLEEP_SMODE_enum +-{ +- SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ +- SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +- SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ +- SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ +- SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +-} SLEEP_SMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-OSC - Oscillator +--------------------------------------------------------------------------- +-*/ +- +-/* Oscillator */ +-typedef struct OSC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t XOSCCTRL; /* External Oscillator Control Register */ +- register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ +- register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ +- register8_t PLLCTRL; /* PLL Control REgister */ +- register8_t DFLLCTRL; /* DFLL Control Register */ +-} OSC_t; +- +-/* Oscillator Frequency Range */ +-typedef enum OSC_FRQRANGE_enum +-{ +- OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ +- OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ +- OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ +- OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +-} OSC_FRQRANGE_t; +- +-/* External Oscillator Selection and Startup Time */ +-typedef enum OSC_XOSCSEL_enum +-{ +- OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ +- OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ +- OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ +- OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ +- OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +-} OSC_XOSCSEL_t; +- +-/* PLL Clock Source */ +-typedef enum OSC_PLLSRC_enum +-{ +- OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ +- OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ +- OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +-} OSC_PLLSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-DFLL - DFLL +--------------------------------------------------------------------------- +-*/ +- +-/* DFLL */ +-typedef struct DFLL_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t CALA; /* Calibration Register A */ +- register8_t CALB; /* Calibration Register B */ +- register8_t COMP0; /* Oscillator Compare Register 0 */ +- register8_t COMP1; /* Oscillator Compare Register 1 */ +- register8_t COMP2; /* Oscillator Compare Register 2 */ +- register8_t reserved_0x07; +-} DFLL_t; +- +- +-/* +--------------------------------------------------------------------------- +-RST - Reset +--------------------------------------------------------------------------- +-*/ +- +-/* Reset */ +-typedef struct RST_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t CTRL; /* Control Register */ +-} RST_t; +- +- +-/* +--------------------------------------------------------------------------- +-WDT - Watch-Dog Timer +--------------------------------------------------------------------------- +-*/ +- +-/* Watch-Dog Timer */ +-typedef struct WDT_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t WINCTRL; /* Windowed Mode Control */ +- register8_t STATUS; /* Status */ +-} WDT_t; +- +-/* Period setting */ +-typedef enum WDT_PER_enum +-{ +- WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ +- WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ +- WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ +- WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_PER_t; +- +-/* Closed window period */ +-typedef enum WDT_WPER_enum +-{ +- WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ +- WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ +- WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ +- WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_WPER_t; +- +- +-/* +--------------------------------------------------------------------------- +-MCU - MCU Control +--------------------------------------------------------------------------- +-*/ +- +-/* MCU Control */ +-typedef struct MCU_struct +-{ +- register8_t DEVID0; /* Device ID byte 0 */ +- register8_t DEVID1; /* Device ID byte 1 */ +- register8_t DEVID2; /* Device ID byte 2 */ +- register8_t REVID; /* Revision ID */ +- register8_t JTAGUID; /* JTAG User ID */ +- register8_t reserved_0x05; +- register8_t MCUCR; /* MCU Control */ +- register8_t reserved_0x07; +- register8_t EVSYSLOCK; /* Event System Lock */ +- register8_t AWEXLOCK; /* AWEX Lock */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +-} MCU_t; +- +- +-/* +--------------------------------------------------------------------------- +-PMIC - Programmable Multi-level Interrupt Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Programmable Multi-level Interrupt Controller */ +-typedef struct PMIC_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t INTPRI; /* Interrupt Priority */ +- register8_t CTRL; /* Control Register */ +-} PMIC_t; +- +- +-/* +--------------------------------------------------------------------------- +-DMA - DMA Controller +--------------------------------------------------------------------------- +-*/ +- +-/* DMA Channel */ +-typedef struct DMA_CH_struct +-{ +- register8_t CTRLA; /* Channel Control */ +- register8_t CTRLB; /* Channel Control */ +- register8_t ADDRCTRL; /* Address Control */ +- register8_t TRIGSRC; /* Channel Trigger Source */ +- _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ +- register8_t REPCNT; /* Channel Repeat Count */ +- register8_t reserved_0x07; +- register8_t SRCADDR0; /* Channel Source Address 0 */ +- register8_t SRCADDR1; /* Channel Source Address 1 */ +- register8_t SRCADDR2; /* Channel Source Address 2 */ +- register8_t reserved_0x0B; +- register8_t DESTADDR0; /* Channel Destination Address 0 */ +- register8_t DESTADDR1; /* Channel Destination Address 1 */ +- register8_t DESTADDR2; /* Channel Destination Address 2 */ +- register8_t reserved_0x0F; +-} DMA_CH_t; +- +-/* +--------------------------------------------------------------------------- +-DMA - DMA Controller +--------------------------------------------------------------------------- +-*/ +- +-/* DMA Controller */ +-typedef struct DMA_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t reserved_0x01; +- register8_t reserved_0x02; +- register8_t INTFLAGS; /* Transfer Interrupt Status */ +- register8_t STATUS; /* Status */ +- register8_t reserved_0x05; +- _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- DMA_CH_t CH0; /* DMA Channel 0 */ +- DMA_CH_t CH1; /* DMA Channel 1 */ +- DMA_CH_t CH2; /* DMA Channel 2 */ +- DMA_CH_t CH3; /* DMA Channel 3 */ +-} DMA_t; +- +-/* Burst mode */ +-typedef enum DMA_CH_BURSTLEN_enum +-{ +- DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ +- DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ +- DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ +- DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +-} DMA_CH_BURSTLEN_t; +- +-/* Source address reload mode */ +-typedef enum DMA_CH_SRCRELOAD_enum +-{ +- DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ +- DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ +- DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ +- DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +-} DMA_CH_SRCRELOAD_t; +- +-/* Source addressing mode */ +-typedef enum DMA_CH_SRCDIR_enum +-{ +- DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ +- DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ +- DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +-} DMA_CH_SRCDIR_t; +- +-/* Destination adress reload mode */ +-typedef enum DMA_CH_DESTRELOAD_enum +-{ +- DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ +- DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ +- DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ +- DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +-} DMA_CH_DESTRELOAD_t; +- +-/* Destination adressing mode */ +-typedef enum DMA_CH_DESTDIR_enum +-{ +- DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ +- DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ +- DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +-} DMA_CH_DESTDIR_t; +- +-/* Transfer trigger source */ +-typedef enum DMA_CH_TRIGSRC_enum +-{ +- DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ +- DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ +- DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ +- DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ +- DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ +- DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ +- DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ +- DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ +- DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ +- DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ +- DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ +- DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ +- DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ +- DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ +- DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ +- DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ +- DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ +- DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ +- DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ +- DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ +- DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ +- DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ +- DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ +- DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ +- DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ +- DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ +- DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ +- DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ +- DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ +- DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ +- DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ +- DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ +- DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ +- DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ +- DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ +- DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ +- DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ +- DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ +- DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +-} DMA_CH_TRIGSRC_t; +- +-/* Double buffering mode */ +-typedef enum DMA_DBUFMODE_enum +-{ +- DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ +- DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ +- DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ +- DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +-} DMA_DBUFMODE_t; +- +-/* Priority mode */ +-typedef enum DMA_PRIMODE_enum +-{ +- DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ +- DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ +- DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ +- DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +-} DMA_PRIMODE_t; +- +-/* Interrupt level */ +-typedef enum DMA_CH_ERRINTLVL_enum +-{ +- DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ +- DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ +- DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +-} DMA_CH_ERRINTLVL_t; +- +-/* Interrupt level */ +-typedef enum DMA_CH_TRNINTLVL_enum +-{ +- DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ +- DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ +- DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +-} DMA_CH_TRNINTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-EVSYS - Event System +--------------------------------------------------------------------------- +-*/ +- +-/* Event System */ +-typedef struct EVSYS_struct +-{ +- register8_t CH0MUX; /* Event Channel 0 Multiplexer */ +- register8_t CH1MUX; /* Event Channel 1 Multiplexer */ +- register8_t CH2MUX; /* Event Channel 2 Multiplexer */ +- register8_t CH3MUX; /* Event Channel 3 Multiplexer */ +- register8_t CH4MUX; /* Event Channel 4 Multiplexer */ +- register8_t CH5MUX; /* Event Channel 5 Multiplexer */ +- register8_t CH6MUX; /* Event Channel 6 Multiplexer */ +- register8_t CH7MUX; /* Event Channel 7 Multiplexer */ +- register8_t CH0CTRL; /* Channel 0 Control Register */ +- register8_t CH1CTRL; /* Channel 1 Control Register */ +- register8_t CH2CTRL; /* Channel 2 Control Register */ +- register8_t CH3CTRL; /* Channel 3 Control Register */ +- register8_t CH4CTRL; /* Channel 4 Control Register */ +- register8_t CH5CTRL; /* Channel 5 Control Register */ +- register8_t CH6CTRL; /* Channel 6 Control Register */ +- register8_t CH7CTRL; /* Channel 7 Control Register */ +- register8_t STROBE; /* Event Strobe */ +- register8_t DATA; /* Event Data */ +-} EVSYS_t; +- +-/* Quadrature Decoder Index Recognition Mode */ +-typedef enum EVSYS_QDIRM_enum +-{ +- EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ +- EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ +- EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ +- EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +-} EVSYS_QDIRM_t; +- +-/* Digital filter coefficient */ +-typedef enum EVSYS_DIGFILT_enum +-{ +- EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ +- EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ +- EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ +- EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ +- EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ +- EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ +- EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ +- EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +-} EVSYS_DIGFILT_t; +- +-/* Event Channel multiplexer input selection */ +-typedef enum EVSYS_CHMUX_enum +-{ +- EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ +- EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ +- EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ +- EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ +- EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ +- EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ +- EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ +- EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ +- EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ +- EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ +- EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ +- EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ +- EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ +- EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ +- EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ +- EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ +- EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ +- EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ +- EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ +- EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ +- EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ +- EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ +- EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ +- EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ +- EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ +- EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ +- EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ +- EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ +- EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ +- EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ +- EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ +- EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ +- EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ +- EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ +- EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ +- EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ +- EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ +- EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ +- EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ +- EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ +- EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ +- EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ +- EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ +- EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ +- EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ +- EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ +- EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ +- EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ +- EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ +- EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ +- EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ +- EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ +- EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ +- EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ +- EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ +- EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ +- EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ +- EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ +- EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ +- EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ +- EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ +- EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ +- EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ +- EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ +- EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ +- EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ +- EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ +- EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ +- EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ +- EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ +- EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ +- EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ +- EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ +- EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ +- EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ +- EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ +- EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ +- EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ +- EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ +- EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ +- EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ +- EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ +- EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ +- EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ +- EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ +- EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ +- EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ +- EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ +- EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ +- EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ +- EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ +- EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ +- EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ +- EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ +- EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ +- EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ +- EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ +- EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ +- EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ +- EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ +- EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ +- EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ +- EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ +- EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ +- EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ +- EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ +- EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ +- EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ +- EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ +- EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ +- EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +- EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ +- EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ +- EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ +- EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +-} EVSYS_CHMUX_t; +- +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Non-volatile Memory Controller */ +-typedef struct NVM_struct +-{ +- register8_t ADDR0; /* Address Register 0 */ +- register8_t ADDR1; /* Address Register 1 */ +- register8_t ADDR2; /* Address Register 2 */ +- register8_t reserved_0x03; +- register8_t DATA0; /* Data Register 0 */ +- register8_t DATA1; /* Data Register 1 */ +- register8_t DATA2; /* Data Register 2 */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t CMD; /* Command */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t INTCTRL; /* Interrupt Control */ +- register8_t reserved_0x0E; +- register8_t STATUS; /* Status */ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Lock Bits */ +-typedef struct NVM_LOCKBITS_struct +-{ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_LOCKBITS_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Fuses */ +-typedef struct NVM_FUSES_struct +-{ +- register8_t FUSEBYTE0; /* JTAG User ID */ +- register8_t FUSEBYTE1; /* Watchdog Configuration */ +- register8_t FUSEBYTE2; /* Reset Configuration */ +- register8_t reserved_0x03; +- register8_t FUSEBYTE4; /* Start-up Configuration */ +- register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +-} NVM_FUSES_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Production Signatures */ +-typedef struct NVM_PROD_SIGNATURES_struct +-{ +- register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ +- register8_t reserved_0x01; +- register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ +- register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ +- register8_t reserved_0x04; +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ +- register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ +- register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ +- register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ +- register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ +- register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t WAFNUM; /* Wafer Number */ +- register8_t reserved_0x11; +- register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ +- register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ +- register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ +- register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ +- register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ +- register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ +- register8_t reserved_0x26; +- register8_t reserved_0x27; +- register8_t reserved_0x28; +- register8_t reserved_0x29; +- register8_t reserved_0x2A; +- register8_t reserved_0x2B; +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ +- register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ +- register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ +- register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ +- register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ +- register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- register8_t reserved_0x36; +- register8_t reserved_0x37; +- register8_t reserved_0x38; +- register8_t reserved_0x39; +- register8_t reserved_0x3A; +- register8_t reserved_0x3B; +- register8_t reserved_0x3C; +- register8_t reserved_0x3D; +- register8_t reserved_0x3E; +-} NVM_PROD_SIGNATURES_t; +- +-/* NVM Command */ +-typedef enum NVM_CMD_enum +-{ +- NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ +- NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ +- NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ +- NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ +- NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ +- NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ +- NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ +- NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ +- NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ +- NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ +- NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ +- NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ +- NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ +- NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ +- NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ +- NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ +- NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ +- NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ +- NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ +- NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ +- NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ +- NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ +- NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ +- NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ +- NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ +- NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +-} NVM_CMD_t; +- +-/* SPM ready interrupt level */ +-typedef enum NVM_SPMLVL_enum +-{ +- NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ +- NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ +- NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +-} NVM_SPMLVL_t; +- +-/* EEPROM ready interrupt level */ +-typedef enum NVM_EELVL_enum +-{ +- NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ +- NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ +- NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +-} NVM_EELVL_t; +- +-/* Boot lock bits - boot setcion */ +-typedef enum NVM_BLBB_enum +-{ +- NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +- NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ +- NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ +- NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +-} NVM_BLBB_t; +- +-/* Boot lock bits - application section */ +-typedef enum NVM_BLBA_enum +-{ +- NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +- NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ +- NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ +- NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +-} NVM_BLBA_t; +- +-/* Boot lock bits - application table section */ +-typedef enum NVM_BLBAT_enum +-{ +- NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +- NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ +- NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ +- NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +-} NVM_BLBAT_t; +- +-/* Lock bits */ +-typedef enum NVM_LB_enum +-{ +- NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +- NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ +- NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +-} NVM_LB_t; +- +-/* Boot Loader Section Reset Vector */ +-typedef enum BOOTRST_enum +-{ +- BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ +- BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +-} BOOTRST_t; +- +-/* BOD operation */ +-typedef enum BOD_enum +-{ +- BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ +- BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ +- BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +-} BOD_t; +- +-/* Watchdog (Window) Timeout Period */ +-typedef enum WD_enum +-{ +- WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ +- WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ +- WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ +- WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ +- WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ +- WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ +- WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ +- WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ +- WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ +- WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ +- WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +-} WD_t; +- +-/* Start-up Time */ +-typedef enum SUT_enum +-{ +- SUT_0MS_gc = (0x03<<2), /* 0 ms */ +- SUT_4MS_gc = (0x01<<2), /* 4 ms */ +- SUT_64MS_gc = (0x00<<2), /* 64 ms */ +-} SUT_t; +- +-/* Brown Out Detection Voltage Level */ +-typedef enum BODLVL_enum +-{ +- BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ +- BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ +- BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ +- BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ +- BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ +- BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ +- BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ +-} BODLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-AC - Analog Comparator +--------------------------------------------------------------------------- +-*/ +- +-/* Analog Comparator */ +-typedef struct AC_struct +-{ +- register8_t AC0CTRL; /* Comparator 0 Control */ +- register8_t AC1CTRL; /* Comparator 1 Control */ +- register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ +- register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t WINCTRL; /* Window Mode Control */ +- register8_t STATUS; /* Status */ +-} AC_t; +- +-/* Interrupt mode */ +-typedef enum AC_INTMODE_enum +-{ +- AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ +- AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ +- AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +-} AC_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum AC_INTLVL_enum +-{ +- AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ +- AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ +- AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ +- AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +-} AC_INTLVL_t; +- +-/* Hysteresis mode selection */ +-typedef enum AC_HYSMODE_enum +-{ +- AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ +- AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ +- AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +-} AC_HYSMODE_t; +- +-/* Positive input multiplexer selection */ +-typedef enum AC_MUXPOS_enum +-{ +- AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ +- AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ +- AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ +- AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ +- AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ +- AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ +- AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +- AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +-} AC_MUXPOS_t; +- +-/* Negative input multiplexer selection */ +-typedef enum AC_MUXNEG_enum +-{ +- AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ +- AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ +- AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ +- AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ +- AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ +- AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ +- AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ +- AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +-} AC_MUXNEG_t; +- +-/* Windows interrupt mode */ +-typedef enum AC_WINTMODE_enum +-{ +- AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ +- AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ +- AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ +- AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +-} AC_WINTMODE_t; +- +-/* Window interrupt level */ +-typedef enum AC_WINTLVL_enum +-{ +- AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ +- AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ +- AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +-} AC_WINTLVL_t; +- +-/* Window mode state */ +-typedef enum AC_WSTATE_enum +-{ +- AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ +- AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ +- AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +-} AC_WSTATE_t; +- +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* ADC Channel */ +-typedef struct ADC_CH_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t MUXCTRL; /* MUX Control */ +- register8_t INTCTRL; /* Channel Interrupt Control */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- _WORDREGISTER(RES); /* Channel Result */ +- register8_t reserved_0x6; +- register8_t reserved_0x7; +-} ADC_CH_t; +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Analog-to-Digital Converter */ +-typedef struct ADC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t REFCTRL; /* Reference Control */ +- register8_t EVCTRL; /* Event Control */ +- register8_t PRESCALER; /* Clock Prescaler */ +- register8_t reserved_0x05; +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- _WORDREGISTER(CAL); /* Calibration Value */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- _WORDREGISTER(CH0RES); /* Channel 0 Result */ +- _WORDREGISTER(CH1RES); /* Channel 1 Result */ +- _WORDREGISTER(CH2RES); /* Channel 2 Result */ +- _WORDREGISTER(CH3RES); /* Channel 3 Result */ +- _WORDREGISTER(CMP); /* Compare Value */ +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- ADC_CH_t CH0; /* ADC Channel 0 */ +- ADC_CH_t CH1; /* ADC Channel 1 */ +- ADC_CH_t CH2; /* ADC Channel 2 */ +- ADC_CH_t CH3; /* ADC Channel 3 */ +-} ADC_t; +- +-/* Positive input multiplexer selection */ +-typedef enum ADC_CH_MUXPOS_enum +-{ +- ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ +- ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ +- ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ +- ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ +- ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ +- ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ +- ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ +- ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +-} ADC_CH_MUXPOS_t; +- +-/* Internal input multiplexer selections */ +-typedef enum ADC_CH_MUXINT_enum +-{ +- ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ +- ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ +- ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +- ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +-} ADC_CH_MUXINT_t; +- +-/* Negative input multiplexer selection */ +-typedef enum ADC_CH_MUXNEG_enum +-{ +- ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ +- ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ +- ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ +- ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ +- ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ +- ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ +- ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ +- ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +-} ADC_CH_MUXNEG_t; +- +-/* Input mode */ +-typedef enum ADC_CH_INPUTMODE_enum +-{ +- ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ +- ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ +- ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ +- ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +-} ADC_CH_INPUTMODE_t; +- +-/* Gain factor */ +-typedef enum ADC_CH_GAIN_enum +-{ +- ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ +- ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ +- ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ +- ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ +- ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ +- ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ +- ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ +-} ADC_CH_GAIN_t; +- +-/* Conversion result resolution */ +-typedef enum ADC_RESOLUTION_enum +-{ +- ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ +- ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ +- ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +-} ADC_RESOLUTION_t; +- +-/* Voltage reference selection */ +-typedef enum ADC_REFSEL_enum +-{ +- ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ +- ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ +- ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ +- ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +-} ADC_REFSEL_t; +- +-/* Channel sweep selection */ +-typedef enum ADC_SWEEP_enum +-{ +- ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ +- ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ +- ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ +- ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +-} ADC_SWEEP_t; +- +-/* Event channel input selection */ +-typedef enum ADC_EVSEL_enum +-{ +- ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ +- ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ +- ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ +- ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ +- ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ +- ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ +- ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ +- ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +-} ADC_EVSEL_t; +- +-/* Event action selection */ +-typedef enum ADC_EVACT_enum +-{ +- ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ +- ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ +- ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ +- ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ +- ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ +- ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ +- ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ +-} ADC_EVACT_t; +- +-/* Interupt mode */ +-typedef enum ADC_CH_INTMODE_enum +-{ +- ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ +- ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ +- ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +-} ADC_CH_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum ADC_CH_INTLVL_enum +-{ +- ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ +- ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ +- ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +-} ADC_CH_INTLVL_t; +- +-/* DMA request selection */ +-typedef enum ADC_DMASEL_enum +-{ +- ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ +- ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ +- ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ +- ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +-} ADC_DMASEL_t; +- +-/* Clock prescaler */ +-typedef enum ADC_PRESCALER_enum +-{ +- ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ +- ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ +- ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ +- ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ +- ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ +- ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ +- ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ +- ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +-} ADC_PRESCALER_t; +- +- +-/* +--------------------------------------------------------------------------- +-DAC - Digital/Analog Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Digital-to-Analog Converter */ +-typedef struct DAC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t EVCTRL; /* Event Input Control */ +- register8_t TIMCTRL; /* Timing Control */ +- register8_t STATUS; /* Status */ +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t GAINCAL; /* Gain Calibration */ +- register8_t OFFSETCAL; /* Offset Calibration */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- _WORDREGISTER(CH0DATA); /* Channel 0 Data */ +- _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +-} DAC_t; +- +-/* Output channel selection */ +-typedef enum DAC_CHSEL_enum +-{ +- DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ +- DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ +-} DAC_CHSEL_t; +- +-/* Reference voltage selection */ +-typedef enum DAC_REFSEL_enum +-{ +- DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ +- DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ +- DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ +- DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +-} DAC_REFSEL_t; +- +-/* Event channel selection */ +-typedef enum DAC_EVSEL_enum +-{ +- DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ +- DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ +- DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ +- DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ +- DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ +- DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ +- DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ +- DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +-} DAC_EVSEL_t; +- +-/* Conversion interval */ +-typedef enum DAC_CONINTVAL_enum +-{ +- DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ +- DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ +- DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ +- DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ +- DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ +- DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ +- DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ +- DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ +-} DAC_CONINTVAL_t; +- +-/* Refresh rate */ +-typedef enum DAC_REFRESH_enum +-{ +- DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ +- DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ +- DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ +- DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ +- DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ +- DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ +- DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ +- DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ +- DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ +- DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ +- DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ +- DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ +- DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ +- DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ +-} DAC_REFRESH_t; +- +- +-/* +--------------------------------------------------------------------------- +-RTC32 - 32-bit Real-Time Counter +--------------------------------------------------------------------------- +-*/ +- +-/* 32-bit Real-Time Clounter */ +-typedef struct RTC32_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t SYNCCTRL; /* Synchronization Control/Status Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- _DWORDREGISTER(CNT); /* Count Register */ +- _DWORDREGISTER(PER); /* Period Register */ +- _DWORDREGISTER(COMP); /* Compare Register */ +-} RTC32_t; +- +-/* Compare Interrupt level */ +-typedef enum RTC32_COMPINTLVL_enum +-{ +- RTC32_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- RTC32_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- RTC32_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- RTC32_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} RTC32_COMPINTLVL_t; +- +-/* Overflow Interrupt level */ +-typedef enum RTC32_OVFINTLVL_enum +-{ +- RTC32_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- RTC32_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- RTC32_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- RTC32_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} RTC32_OVFINTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* EBI Chip Select Module */ +-typedef struct EBI_CS_struct +-{ +- register8_t CTRLA; /* Chip Select Control Register A */ +- register8_t CTRLB; /* Chip Select Control Register B */ +- _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +-} EBI_CS_t; +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* External Bus Interface */ +-typedef struct EBI_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t SDRAMCTRLA; /* SDRAM Control Register A */ +- register8_t reserved_0x02; +- register8_t reserved_0x03; +- _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ +- _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ +- register8_t SDRAMCTRLB; /* SDRAM Control Register B */ +- register8_t SDRAMCTRLC; /* SDRAM Control Register C */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- EBI_CS_t CS0; /* Chip Select 0 */ +- EBI_CS_t CS1; /* Chip Select 1 */ +- EBI_CS_t CS2; /* Chip Select 2 */ +- EBI_CS_t CS3; /* Chip Select 3 */ +-} EBI_t; +- +-/* Chip Select adress space */ +-typedef enum EBI_CS_ASIZE_enum +-{ +- EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ +- EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ +- EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ +- EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ +- EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ +- EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ +- EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ +- EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ +- EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ +- EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ +- EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ +- EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ +- EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ +- EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ +- EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ +- EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ +- EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +-} EBI_CS_ASIZE_t; +- +-/* */ +-typedef enum EBI_CS_SRWS_enum +-{ +- EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_CS_SRWS_t; +- +-/* Chip Select address mode */ +-typedef enum EBI_CS_MODE_enum +-{ +- EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ +- EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ +- EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ +- EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +-} EBI_CS_MODE_t; +- +-/* Chip Select SDRAM mode */ +-typedef enum EBI_CS_SDMODE_enum +-{ +- EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ +- EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +-} EBI_CS_SDMODE_t; +- +-/* */ +-typedef enum EBI_SDDATAW_enum +-{ +- EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ +- EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +-} EBI_SDDATAW_t; +- +-/* */ +-typedef enum EBI_LPCMODE_enum +-{ +- EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ +- EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +-} EBI_LPCMODE_t; +- +-/* */ +-typedef enum EBI_SRMODE_enum +-{ +- EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ +- EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ +- EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ +- EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +-} EBI_SRMODE_t; +- +-/* */ +-typedef enum EBI_IFMODE_enum +-{ +- EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ +- EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ +- EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ +- EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +-} EBI_IFMODE_t; +- +-/* */ +-typedef enum EBI_SDCOL_enum +-{ +- EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ +- EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ +- EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ +- EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +-} EBI_SDCOL_t; +- +-/* */ +-typedef enum EBI_MRDLY_enum +-{ +- EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_MRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCYCDLY_enum +-{ +- EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ROWCYCDLY_t; +- +-/* */ +-typedef enum EBI_RPDLY_enum +-{ +- EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_RPDLY_t; +- +-/* */ +-typedef enum EBI_WRDLY_enum +-{ +- EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_WRDLY_t; +- +-/* */ +-typedef enum EBI_ESRDLY_enum +-{ +- EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ESRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCOLDLY_enum +-{ +- EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_ROWCOLDLY_t; +- +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_MASTER_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t STATUS; /* Status Register */ +- register8_t BAUD; /* Baurd Rate Control Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +-} TWI_MASTER_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_SLAVE_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t STATUS; /* Status Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +- register8_t ADDRMASK; /* Address Mask Register */ +-} TWI_SLAVE_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Two-Wire Interface */ +-typedef struct TWI_struct +-{ +- register8_t CTRL; /* TWI Common Control Register */ +- TWI_MASTER_t MASTER; /* TWI master module */ +- TWI_SLAVE_t SLAVE; /* TWI slave module */ +-} TWI_t; +- +-/* Master Interrupt Level */ +-typedef enum TWI_MASTER_INTLVL_enum +-{ +- TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_MASTER_INTLVL_t; +- +-/* Inactive Timeout */ +-typedef enum TWI_MASTER_TIMEOUT_enum +-{ +- TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ +- TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ +- TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ +- TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +-} TWI_MASTER_TIMEOUT_t; +- +-/* Master Command */ +-typedef enum TWI_MASTER_CMD_enum +-{ +- TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ +- TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ +- TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +-} TWI_MASTER_CMD_t; +- +-/* Master Bus State */ +-typedef enum TWI_MASTER_BUSSTATE_enum +-{ +- TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ +- TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ +- TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ +- TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +-} TWI_MASTER_BUSSTATE_t; +- +-/* Slave Interrupt Level */ +-typedef enum TWI_SLAVE_INTLVL_enum +-{ +- TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_SLAVE_INTLVL_t; +- +-/* Slave Command */ +-typedef enum TWI_SLAVE_CMD_enum +-{ +- TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ +- TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +-} TWI_SLAVE_CMD_t; +- +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O port Configuration */ +-typedef struct PORTCFG_struct +-{ +- register8_t MPCMASK; /* Multi-pin Configuration Mask */ +- register8_t reserved_0x01; +- register8_t VPCTRLA; /* Virtual Port Control Register A */ +- register8_t VPCTRLB; /* Virtual Port Control Register B */ +- register8_t CLKEVOUT; /* Clock and Event Out Register */ +-} PORTCFG_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* Virtual Port */ +-typedef struct VPORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t OUT; /* I/O Port Output */ +- register8_t IN; /* I/O Port Input */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +-} VPORT_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O Ports */ +-typedef struct PORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t DIRSET; /* I/O Port Data Direction Set */ +- register8_t DIRCLR; /* I/O Port Data Direction Clear */ +- register8_t DIRTGL; /* I/O Port Data Direction Toggle */ +- register8_t OUT; /* I/O Port Output */ +- register8_t OUTSET; /* I/O Port Output Set */ +- register8_t OUTCLR; /* I/O Port Output Clear */ +- register8_t OUTTGL; /* I/O Port Output Toggle */ +- register8_t IN; /* I/O port Input */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INT0MASK; /* Port Interrupt 0 Mask */ +- register8_t INT1MASK; /* Port Interrupt 1 Mask */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t PIN0CTRL; /* Pin 0 Control Register */ +- register8_t PIN1CTRL; /* Pin 1 Control Register */ +- register8_t PIN2CTRL; /* Pin 2 Control Register */ +- register8_t PIN3CTRL; /* Pin 3 Control Register */ +- register8_t PIN4CTRL; /* Pin 4 Control Register */ +- register8_t PIN5CTRL; /* Pin 5 Control Register */ +- register8_t PIN6CTRL; /* Pin 6 Control Register */ +- register8_t PIN7CTRL; /* Pin 7 Control Register */ +-} PORT_t; +- +-/* Virtual Port 0 Mapping */ +-typedef enum PORTCFG_VP0MAP_enum +-{ +- PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP0MAP_t; +- +-/* Virtual Port 1 Mapping */ +-typedef enum PORTCFG_VP1MAP_enum +-{ +- PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP1MAP_t; +- +-/* Virtual Port 2 Mapping */ +-typedef enum PORTCFG_VP2MAP_enum +-{ +- PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP2MAP_t; +- +-/* Virtual Port 3 Mapping */ +-typedef enum PORTCFG_VP3MAP_enum +-{ +- PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP3MAP_t; +- +-/* Clock Output Port */ +-typedef enum PORTCFG_CLKOUT_enum +-{ +- PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ +- PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ +- PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ +- PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +-} PORTCFG_CLKOUT_t; +- +-/* Event Output Port */ +-typedef enum PORTCFG_EVOUT_enum +-{ +- PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ +- PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ +- PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ +- PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +-} PORTCFG_EVOUT_t; +- +-/* Port Interrupt 0 Level */ +-typedef enum PORT_INT0LVL_enum +-{ +- PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ +- PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ +- PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +-} PORT_INT0LVL_t; +- +-/* Port Interrupt 1 Level */ +-typedef enum PORT_INT1LVL_enum +-{ +- PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ +- PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ +- PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +-} PORT_INT1LVL_t; +- +-/* Output/Pull Configuration */ +-typedef enum PORT_OPC_enum +-{ +- PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ +- PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ +- PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ +- PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ +- PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ +- PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ +- PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ +- PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +-} PORT_OPC_t; +- +-/* Input/Sense Configuration */ +-typedef enum PORT_ISC_enum +-{ +- PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ +- PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ +- PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ +- PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ +- PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +-} PORT_ISC_t; +- +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 0 */ +-typedef struct TC0_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- _WORDREGISTER(CCC); /* Compare or Capture C */ +- _WORDREGISTER(CCD); /* Compare or Capture D */ +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +- _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ +- _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +-} TC0_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 1 */ +-typedef struct TC1_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t reserved_0x2E; +- register8_t reserved_0x2F; +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +-} TC1_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* Advanced Waveform Extension */ +-typedef struct AWEX_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t FDEMASK; /* Fault Detection Event Mask */ +- register8_t FDCTRL; /* Fault Detection Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x05; +- register8_t DTBOTH; /* Dead Time Both Sides */ +- register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ +- register8_t DTLS; /* Dead Time Low Side */ +- register8_t DTHS; /* Dead Time High Side */ +- register8_t DTLSBUF; /* Dead Time Low Side Buffer */ +- register8_t DTHSBUF; /* Dead Time High Side Buffer */ +- register8_t OUTOVEN; /* Output Override Enable */ +-} AWEX_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* High-Resolution Extension */ +-typedef struct HIRES_struct +-{ +- register8_t CTRLA; /* Control Register */ +-} HIRES_t; +- +-/* Clock Selection */ +-typedef enum TC_CLKSEL_enum +-{ +- TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ +- TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ +- TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ +- TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ +- TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ +- TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ +- TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ +- TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ +- TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_CLKSEL_t; +- +-/* Waveform Generation Mode */ +-typedef enum TC_WGMODE_enum +-{ +- TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ +- TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ +- TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ +- TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ +- TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ +- TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +-} TC_WGMODE_t; +- +-/* Event Action */ +-typedef enum TC_EVACT_enum +-{ +- TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ +- TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ +- TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ +- TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ +- TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ +- TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */ +- TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +-} TC_EVACT_t; +- +-/* Event Selection */ +-typedef enum TC_EVSEL_enum +-{ +- TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_EVSEL_t; +- +-/* Error Interrupt Level */ +-typedef enum TC_ERRINTLVL_enum +-{ +- TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_ERRINTLVL_t; +- +-/* Overflow Interrupt Level */ +-typedef enum TC_OVFINTLVL_enum +-{ +- TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_OVFINTLVL_t; +- +-/* Compare or Capture D Interrupt Level */ +-typedef enum TC_CCDINTLVL_enum +-{ +- TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TC_CCDINTLVL_t; +- +-/* Compare or Capture C Interrupt Level */ +-typedef enum TC_CCCINTLVL_enum +-{ +- TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} TC_CCCINTLVL_t; +- +-/* Compare or Capture B Interrupt Level */ +-typedef enum TC_CCBINTLVL_enum +-{ +- TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_CCBINTLVL_t; +- +-/* Compare or Capture A Interrupt Level */ +-typedef enum TC_CCAINTLVL_enum +-{ +- TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_CCAINTLVL_t; +- +-/* Timer/Counter Command */ +-typedef enum TC_CMD_enum +-{ +- TC_CMD_NONE_gc = (0x00<<2), /* No Command */ +- TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ +- TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ +- TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +-} TC_CMD_t; +- +-/* Fault Detect Action */ +-typedef enum AWEX_FDACT_enum +-{ +- AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ +- AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ +- AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +-} AWEX_FDACT_t; +- +-/* High Resolution Enable */ +-typedef enum HIRES_HREN_enum +-{ +- HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ +- HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ +- HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ +- HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +-} HIRES_HREN_t; +- +- +-/* +--------------------------------------------------------------------------- +-USART - Universal Asynchronous Receiver-Transmitter +--------------------------------------------------------------------------- +-*/ +- +-/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +-typedef struct USART_struct +-{ +- register8_t DATA; /* Data Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x02; +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t BAUDCTRLA; /* Baud Rate Control Register A */ +- register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +-} USART_t; +- +-/* Receive Complete Interrupt level */ +-typedef enum USART_RXCINTLVL_enum +-{ +- USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} USART_RXCINTLVL_t; +- +-/* Transmit Complete Interrupt level */ +-typedef enum USART_TXCINTLVL_enum +-{ +- USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} USART_TXCINTLVL_t; +- +-/* Data Register Empty Interrupt level */ +-typedef enum USART_DREINTLVL_enum +-{ +- USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} USART_DREINTLVL_t; +- +-/* Character Size */ +-typedef enum USART_CHSIZE_enum +-{ +- USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ +- USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ +- USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ +- USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ +- USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +-} USART_CHSIZE_t; +- +-/* Communication Mode */ +-typedef enum USART_CMODE_enum +-{ +- USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ +- USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ +- USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ +- USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +-} USART_CMODE_t; +- +-/* Parity Mode */ +-typedef enum USART_PMODE_enum +-{ +- USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ +- USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ +- USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +-} USART_PMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-SPI - Serial Peripheral Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Serial Peripheral Interface */ +-typedef struct SPI_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t DATA; /* Data Register */ +-} SPI_t; +- +-/* SPI Mode */ +-typedef enum SPI_MODE_enum +-{ +- SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ +- SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ +- SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ +- SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +-} SPI_MODE_t; +- +-/* Prescaler setting */ +-typedef enum SPI_PRESCALER_enum +-{ +- SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ +- SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ +- SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ +- SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +-} SPI_PRESCALER_t; +- +-/* Interrupt level */ +-typedef enum SPI_INTLVL_enum +-{ +- SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} SPI_INTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-IRCOM - IR Communication Module +--------------------------------------------------------------------------- +-*/ +- +-/* IR Communication Module */ +-typedef struct IRCOM_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ +- register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +-} IRCOM_t; +- +-/* Event channel selection */ +-typedef enum IRDA_EVSEL_enum +-{ +- IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ +- IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ +- IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ +- IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +- IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ +- IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ +- IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ +- IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +-} IRDA_EVSEL_t; +- +- +-/* +--------------------------------------------------------------------------- +-AES - AES Module +--------------------------------------------------------------------------- +-*/ +- +-/* AES Module */ +-typedef struct AES_struct +-{ +- register8_t CTRL; /* AES Control Register */ +- register8_t STATUS; /* AES Status Register */ +- register8_t STATE; /* AES State Register */ +- register8_t KEY; /* AES Key Register */ +- register8_t INTCTRL; /* AES Interrupt Control Register */ +-} AES_t; +- +-/* Interrupt level */ +-typedef enum AES_INTLVL_enum +-{ +- AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} AES_INTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-VBAT - VBAT Battery Backup Module +--------------------------------------------------------------------------- +-*/ +- +-/* VBAT Battery Backup Module */ +-typedef struct VBAT_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t BACKUP0; /* Battery Bacup Register 0 */ +- register8_t BACKUP1; /* Battery Backup Register 1 */ +-} VBAT_t; +- +- +- +-/* +-========================================================================== +-IO Module Instances. Mapped to memory. +-========================================================================== +-*/ +- +-#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +-#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +-#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +-#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +-#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +-#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +-#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +-#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +-#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +-#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +-#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +-#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +-#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +-#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +-#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +-#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +-#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ +-#define VBAT (*(VBAT_t *) 0x00F0) /* VBAT Battery Backup Module */ +-#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +-#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +-#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +-#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +-#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ +-#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ +-#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +-#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ +-#define RTC32 (*(RTC32_t *) 0x0420) /* 32-bit Real-Time Counter */ +-#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +-#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ +-#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +-#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +-#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +-#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +-#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +-#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ +-#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +-#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +-#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +-#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +-#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +-#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +-#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ +-#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +-#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +-#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +-#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ +-#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ +-#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +-#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ +-#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +-#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +-#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ +-#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ +-#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ +-#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ +-#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ +-#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ +-#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ +-#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ +-#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ +- +- +-#endif /* !defined (__ASSEMBLER__) */ +- +- +-/* ========== Flattened fully qualified IO register names ========== */ +- +-/* GPIO - General Purpose IO Registers */ +-#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +-#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +-#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +-#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +-#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +-#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +-#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +-#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +-#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +-#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +-#define GPIO_GPIORA _SFR_MEM8(0x000A) +-#define GPIO_GPIORB _SFR_MEM8(0x000B) +-#define GPIO_GPIORC _SFR_MEM8(0x000C) +-#define GPIO_GPIORD _SFR_MEM8(0x000D) +-#define GPIO_GPIORE _SFR_MEM8(0x000E) +-#define GPIO_GPIORF _SFR_MEM8(0x000F) +- +-/* Deprecated */ +-#define GPIO_GPIO0 _SFR_MEM8(0x0000) +-#define GPIO_GPIO1 _SFR_MEM8(0x0001) +-#define GPIO_GPIO2 _SFR_MEM8(0x0002) +-#define GPIO_GPIO3 _SFR_MEM8(0x0003) +-#define GPIO_GPIO4 _SFR_MEM8(0x0004) +-#define GPIO_GPIO5 _SFR_MEM8(0x0005) +-#define GPIO_GPIO6 _SFR_MEM8(0x0006) +-#define GPIO_GPIO7 _SFR_MEM8(0x0007) +-#define GPIO_GPIO8 _SFR_MEM8(0x0008) +-#define GPIO_GPIO9 _SFR_MEM8(0x0009) +-#define GPIO_GPIOA _SFR_MEM8(0x000A) +-#define GPIO_GPIOB _SFR_MEM8(0x000B) +-#define GPIO_GPIOC _SFR_MEM8(0x000C) +-#define GPIO_GPIOD _SFR_MEM8(0x000D) +-#define GPIO_GPIOE _SFR_MEM8(0x000E) +-#define GPIO_GPIOF _SFR_MEM8(0x000F) +- +- +-/* VPORT0 - Virtual Port 0 */ +-#define VPORT0_DIR _SFR_MEM8(0x0010) +-#define VPORT0_OUT _SFR_MEM8(0x0011) +-#define VPORT0_IN _SFR_MEM8(0x0012) +-#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) +- +-/* VPORT1 - Virtual Port 1 */ +-#define VPORT1_DIR _SFR_MEM8(0x0014) +-#define VPORT1_OUT _SFR_MEM8(0x0015) +-#define VPORT1_IN _SFR_MEM8(0x0016) +-#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) +- +-/* VPORT2 - Virtual Port 2 */ +-#define VPORT2_DIR _SFR_MEM8(0x0018) +-#define VPORT2_OUT _SFR_MEM8(0x0019) +-#define VPORT2_IN _SFR_MEM8(0x001A) +-#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) +- +-/* VPORT3 - Virtual Port 3 */ +-#define VPORT3_DIR _SFR_MEM8(0x001C) +-#define VPORT3_OUT _SFR_MEM8(0x001D) +-#define VPORT3_IN _SFR_MEM8(0x001E) +-#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) +- +-/* OCD - On-Chip Debug System */ +-#define OCD_OCDR0 _SFR_MEM8(0x002E) +-#define OCD_OCDR1 _SFR_MEM8(0x002F) +- +-/* CPU - CPU Registers */ +-#define CPU_CCP _SFR_MEM8(0x0034) +-#define CPU_RAMPD _SFR_MEM8(0x0038) +-#define CPU_RAMPX _SFR_MEM8(0x0039) +-#define CPU_RAMPY _SFR_MEM8(0x003A) +-#define CPU_RAMPZ _SFR_MEM8(0x003B) +-#define CPU_EIND _SFR_MEM8(0x003C) +-#define CPU_SPL _SFR_MEM8(0x003D) +-#define CPU_SPH _SFR_MEM8(0x003E) +-#define CPU_SREG _SFR_MEM8(0x003F) +- +-/* CLK - Clock System */ +-#define CLK_CTRL _SFR_MEM8(0x0040) +-#define CLK_PSCTRL _SFR_MEM8(0x0041) +-#define CLK_LOCK _SFR_MEM8(0x0042) +-#define CLK_RTCCTRL _SFR_MEM8(0x0043) +- +-/* SLEEP - Sleep Controller */ +-#define SLEEP_CTRL _SFR_MEM8(0x0048) +- +-/* OSC - Oscillator Control */ +-#define OSC_CTRL _SFR_MEM8(0x0050) +-#define OSC_STATUS _SFR_MEM8(0x0051) +-#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +-#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +-#define OSC_RC32KCAL _SFR_MEM8(0x0054) +-#define OSC_PLLCTRL _SFR_MEM8(0x0055) +-#define OSC_DFLLCTRL _SFR_MEM8(0x0056) +- +-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +-#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +-#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +-#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +-#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +-#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +-#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) +- +-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +-#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +-#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +-#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +-#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +-#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +-#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) +- +-/* PR - Power Reduction */ +-#define PR_PRGEN _SFR_MEM8(0x0070) +-#define PR_PRPA _SFR_MEM8(0x0071) +-#define PR_PRPB _SFR_MEM8(0x0072) +-#define PR_PRPC _SFR_MEM8(0x0073) +-#define PR_PRPD _SFR_MEM8(0x0074) +-#define PR_PRPE _SFR_MEM8(0x0075) +-#define PR_PRPF _SFR_MEM8(0x0076) +- +-/* RST - Reset Controller */ +-#define RST_STATUS _SFR_MEM8(0x0078) +-#define RST_CTRL _SFR_MEM8(0x0079) +- +-/* WDT - Watch-Dog Timer */ +-#define WDT_CTRL _SFR_MEM8(0x0080) +-#define WDT_WINCTRL _SFR_MEM8(0x0081) +-#define WDT_STATUS _SFR_MEM8(0x0082) +- +-/* MCU - MCU Control */ +-#define MCU_DEVID0 _SFR_MEM8(0x0090) +-#define MCU_DEVID1 _SFR_MEM8(0x0091) +-#define MCU_DEVID2 _SFR_MEM8(0x0092) +-#define MCU_REVID _SFR_MEM8(0x0093) +-#define MCU_JTAGUID _SFR_MEM8(0x0094) +-#define MCU_MCUCR _SFR_MEM8(0x0096) +-#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +-#define MCU_AWEXLOCK _SFR_MEM8(0x0099) +- +-/* PMIC - Programmable Interrupt Controller */ +-#define PMIC_STATUS _SFR_MEM8(0x00A0) +-#define PMIC_INTPRI _SFR_MEM8(0x00A1) +-#define PMIC_CTRL _SFR_MEM8(0x00A2) +- +-/* PORTCFG - Port Configuration */ +-#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +-#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +-#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +-#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +- +-/* AES - AES Crypto Module */ +-#define AES_CTRL _SFR_MEM8(0x00C0) +-#define AES_STATUS _SFR_MEM8(0x00C1) +-#define AES_STATE _SFR_MEM8(0x00C2) +-#define AES_KEY _SFR_MEM8(0x00C3) +-#define AES_INTCTRL _SFR_MEM8(0x00C4) +- +-/* VBAT - VBAT Battery Backup Module */ +-#define VBAT_CTRL _SFR_MEM8(0x00F0) +-#define VBAT_STATUS _SFR_MEM8(0x00F1) +-#define VBAT_BACKUP0 _SFR_MEM8(0x00F2) +-#define VBAT_BACKUP1 _SFR_MEM8(0x00F3) +- +-/* DMA - DMA Controller */ +-#define DMA_CTRL _SFR_MEM8(0x0100) +-#define DMA_INTFLAGS _SFR_MEM8(0x0103) +-#define DMA_STATUS _SFR_MEM8(0x0104) +-#define DMA_TEMP _SFR_MEM16(0x0106) +-#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +-#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +-#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +-#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +-#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +-#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +-#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +-#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +-#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +-#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +-#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +-#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +-#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +-#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +-#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +-#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +-#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +-#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +-#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +-#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +-#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +-#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +-#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +-#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +-#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +-#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +-#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +-#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +-#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +-#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +-#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +-#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +-#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +-#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +-#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +-#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +-#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +-#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +-#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +-#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +-#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +-#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +-#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +-#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +-#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +-#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +-#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +-#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) +- +-/* EVSYS - Event System */ +-#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +-#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +-#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +-#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +-#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +-#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +-#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +-#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +-#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +-#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +-#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +-#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +-#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +-#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +-#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +-#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +-#define EVSYS_STROBE _SFR_MEM8(0x0190) +-#define EVSYS_DATA _SFR_MEM8(0x0191) +- +-/* NVM - Non Volatile Memory Controller */ +-#define NVM_ADDR0 _SFR_MEM8(0x01C0) +-#define NVM_ADDR1 _SFR_MEM8(0x01C1) +-#define NVM_ADDR2 _SFR_MEM8(0x01C2) +-#define NVM_DATA0 _SFR_MEM8(0x01C4) +-#define NVM_DATA1 _SFR_MEM8(0x01C5) +-#define NVM_DATA2 _SFR_MEM8(0x01C6) +-#define NVM_CMD _SFR_MEM8(0x01CA) +-#define NVM_CTRLA _SFR_MEM8(0x01CB) +-#define NVM_CTRLB _SFR_MEM8(0x01CC) +-#define NVM_INTCTRL _SFR_MEM8(0x01CD) +-#define NVM_STATUS _SFR_MEM8(0x01CF) +-#define NVM_LOCKBITS _SFR_MEM8(0x01D0) +- +-/* ADCA - Analog to Digital Converter A */ +-#define ADCA_CTRLA _SFR_MEM8(0x0200) +-#define ADCA_CTRLB _SFR_MEM8(0x0201) +-#define ADCA_REFCTRL _SFR_MEM8(0x0202) +-#define ADCA_EVCTRL _SFR_MEM8(0x0203) +-#define ADCA_PRESCALER _SFR_MEM8(0x0204) +-#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +-#define ADCA_CAL _SFR_MEM16(0x020C) +-#define ADCA_CH0RES _SFR_MEM16(0x0210) +-#define ADCA_CH1RES _SFR_MEM16(0x0212) +-#define ADCA_CH2RES _SFR_MEM16(0x0214) +-#define ADCA_CH3RES _SFR_MEM16(0x0216) +-#define ADCA_CMP _SFR_MEM16(0x0218) +-#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +-#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +-#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +-#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +-#define ADCA_CH0_RES _SFR_MEM16(0x0224) +-#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +-#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +-#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +-#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +-#define ADCA_CH1_RES _SFR_MEM16(0x022C) +-#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +-#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +-#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +-#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +-#define ADCA_CH2_RES _SFR_MEM16(0x0234) +-#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +-#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +-#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +-#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +-#define ADCA_CH3_RES _SFR_MEM16(0x023C) +- +-/* ADCB - Analog to Digital Converter B */ +-#define ADCB_CTRLA _SFR_MEM8(0x0240) +-#define ADCB_CTRLB _SFR_MEM8(0x0241) +-#define ADCB_REFCTRL _SFR_MEM8(0x0242) +-#define ADCB_EVCTRL _SFR_MEM8(0x0243) +-#define ADCB_PRESCALER _SFR_MEM8(0x0244) +-#define ADCB_INTFLAGS _SFR_MEM8(0x0246) +-#define ADCB_CAL _SFR_MEM16(0x024C) +-#define ADCB_CH0RES _SFR_MEM16(0x0250) +-#define ADCB_CH1RES _SFR_MEM16(0x0252) +-#define ADCB_CH2RES _SFR_MEM16(0x0254) +-#define ADCB_CH3RES _SFR_MEM16(0x0256) +-#define ADCB_CMP _SFR_MEM16(0x0258) +-#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) +-#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) +-#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) +-#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) +-#define ADCB_CH0_RES _SFR_MEM16(0x0264) +-#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) +-#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) +-#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) +-#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) +-#define ADCB_CH1_RES _SFR_MEM16(0x026C) +-#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) +-#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) +-#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) +-#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) +-#define ADCB_CH2_RES _SFR_MEM16(0x0274) +-#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) +-#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) +-#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) +-#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) +-#define ADCB_CH3_RES _SFR_MEM16(0x027C) +- +-/* DACB - Digital to Analog Converter B */ +-#define DACB_CTRLA _SFR_MEM8(0x0320) +-#define DACB_CTRLB _SFR_MEM8(0x0321) +-#define DACB_CTRLC _SFR_MEM8(0x0322) +-#define DACB_EVCTRL _SFR_MEM8(0x0323) +-#define DACB_TIMCTRL _SFR_MEM8(0x0324) +-#define DACB_STATUS _SFR_MEM8(0x0325) +-#define DACB_GAINCAL _SFR_MEM8(0x0328) +-#define DACB_OFFSETCAL _SFR_MEM8(0x0329) +-#define DACB_CH0DATA _SFR_MEM16(0x0338) +-#define DACB_CH1DATA _SFR_MEM16(0x033A) +- +-/* ACA - Analog Comparator A */ +-#define ACA_AC0CTRL _SFR_MEM8(0x0380) +-#define ACA_AC1CTRL _SFR_MEM8(0x0381) +-#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +-#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +-#define ACA_CTRLA _SFR_MEM8(0x0384) +-#define ACA_CTRLB _SFR_MEM8(0x0385) +-#define ACA_WINCTRL _SFR_MEM8(0x0386) +-#define ACA_STATUS _SFR_MEM8(0x0387) +- +-/* ACB - Analog Comparator B */ +-#define ACB_AC0CTRL _SFR_MEM8(0x0390) +-#define ACB_AC1CTRL _SFR_MEM8(0x0391) +-#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +-#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +-#define ACB_CTRLA _SFR_MEM8(0x0394) +-#define ACB_CTRLB _SFR_MEM8(0x0395) +-#define ACB_WINCTRL _SFR_MEM8(0x0396) +-#define ACB_STATUS _SFR_MEM8(0x0397) +- +-/* RTC32 - 32-bit Real-Time Counter */ +-#define RTC32_CTRL _SFR_MEM8(0x0420) +-#define RTC32_SYNCCTRL _SFR_MEM8(0x0421) +-#define RTC32_INTCTRL _SFR_MEM8(0x0422) +-#define RTC32_INTFLAGS _SFR_MEM8(0x0423) +- +-/* TWIC - Two-Wire Interface C */ +-#define TWIC_CTRL _SFR_MEM8(0x0480) +-#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +-#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +-#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +-#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +-#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +-#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +-#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +-#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +-#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +-#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +-#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +-#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +-#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) +- +-/* TWIE - Two-Wire Interface E */ +-#define TWIE_CTRL _SFR_MEM8(0x04A0) +-#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +-#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +-#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +-#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +-#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +-#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +-#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +-#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +-#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +-#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +-#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +-#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +-#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) +- +-/* PORTA - Port A */ +-#define PORTA_DIR _SFR_MEM8(0x0600) +-#define PORTA_DIRSET _SFR_MEM8(0x0601) +-#define PORTA_DIRCLR _SFR_MEM8(0x0602) +-#define PORTA_DIRTGL _SFR_MEM8(0x0603) +-#define PORTA_OUT _SFR_MEM8(0x0604) +-#define PORTA_OUTSET _SFR_MEM8(0x0605) +-#define PORTA_OUTCLR _SFR_MEM8(0x0606) +-#define PORTA_OUTTGL _SFR_MEM8(0x0607) +-#define PORTA_IN _SFR_MEM8(0x0608) +-#define PORTA_INTCTRL _SFR_MEM8(0x0609) +-#define PORTA_INT0MASK _SFR_MEM8(0x060A) +-#define PORTA_INT1MASK _SFR_MEM8(0x060B) +-#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +-#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +-#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +-#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +-#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +-#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +-#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +-#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +-#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) +- +-/* PORTB - Port B */ +-#define PORTB_DIR _SFR_MEM8(0x0620) +-#define PORTB_DIRSET _SFR_MEM8(0x0621) +-#define PORTB_DIRCLR _SFR_MEM8(0x0622) +-#define PORTB_DIRTGL _SFR_MEM8(0x0623) +-#define PORTB_OUT _SFR_MEM8(0x0624) +-#define PORTB_OUTSET _SFR_MEM8(0x0625) +-#define PORTB_OUTCLR _SFR_MEM8(0x0626) +-#define PORTB_OUTTGL _SFR_MEM8(0x0627) +-#define PORTB_IN _SFR_MEM8(0x0628) +-#define PORTB_INTCTRL _SFR_MEM8(0x0629) +-#define PORTB_INT0MASK _SFR_MEM8(0x062A) +-#define PORTB_INT1MASK _SFR_MEM8(0x062B) +-#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +-#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +-#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +-#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +-#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +-#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +-#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +-#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +-#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) +- +-/* PORTC - Port C */ +-#define PORTC_DIR _SFR_MEM8(0x0640) +-#define PORTC_DIRSET _SFR_MEM8(0x0641) +-#define PORTC_DIRCLR _SFR_MEM8(0x0642) +-#define PORTC_DIRTGL _SFR_MEM8(0x0643) +-#define PORTC_OUT _SFR_MEM8(0x0644) +-#define PORTC_OUTSET _SFR_MEM8(0x0645) +-#define PORTC_OUTCLR _SFR_MEM8(0x0646) +-#define PORTC_OUTTGL _SFR_MEM8(0x0647) +-#define PORTC_IN _SFR_MEM8(0x0648) +-#define PORTC_INTCTRL _SFR_MEM8(0x0649) +-#define PORTC_INT0MASK _SFR_MEM8(0x064A) +-#define PORTC_INT1MASK _SFR_MEM8(0x064B) +-#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +-#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +-#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +-#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +-#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +-#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +-#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +-#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +-#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) +- +-/* PORTD - Port D */ +-#define PORTD_DIR _SFR_MEM8(0x0660) +-#define PORTD_DIRSET _SFR_MEM8(0x0661) +-#define PORTD_DIRCLR _SFR_MEM8(0x0662) +-#define PORTD_DIRTGL _SFR_MEM8(0x0663) +-#define PORTD_OUT _SFR_MEM8(0x0664) +-#define PORTD_OUTSET _SFR_MEM8(0x0665) +-#define PORTD_OUTCLR _SFR_MEM8(0x0666) +-#define PORTD_OUTTGL _SFR_MEM8(0x0667) +-#define PORTD_IN _SFR_MEM8(0x0668) +-#define PORTD_INTCTRL _SFR_MEM8(0x0669) +-#define PORTD_INT0MASK _SFR_MEM8(0x066A) +-#define PORTD_INT1MASK _SFR_MEM8(0x066B) +-#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +-#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +-#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +-#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +-#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +-#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +-#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +-#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +-#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) +- +-/* PORTE - Port E */ +-#define PORTE_DIR _SFR_MEM8(0x0680) +-#define PORTE_DIRSET _SFR_MEM8(0x0681) +-#define PORTE_DIRCLR _SFR_MEM8(0x0682) +-#define PORTE_DIRTGL _SFR_MEM8(0x0683) +-#define PORTE_OUT _SFR_MEM8(0x0684) +-#define PORTE_OUTSET _SFR_MEM8(0x0685) +-#define PORTE_OUTCLR _SFR_MEM8(0x0686) +-#define PORTE_OUTTGL _SFR_MEM8(0x0687) +-#define PORTE_IN _SFR_MEM8(0x0688) +-#define PORTE_INTCTRL _SFR_MEM8(0x0689) +-#define PORTE_INT0MASK _SFR_MEM8(0x068A) +-#define PORTE_INT1MASK _SFR_MEM8(0x068B) +-#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +-#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +-#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +-#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +-#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +-#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +-#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +-#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +-#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) +- +-/* PORTF - Port F */ +-#define PORTF_DIR _SFR_MEM8(0x06A0) +-#define PORTF_DIRSET _SFR_MEM8(0x06A1) +-#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +-#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +-#define PORTF_OUT _SFR_MEM8(0x06A4) +-#define PORTF_OUTSET _SFR_MEM8(0x06A5) +-#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +-#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +-#define PORTF_IN _SFR_MEM8(0x06A8) +-#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +-#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +-#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +-#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +-#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +-#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +-#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +-#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +-#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +-#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +-#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +-#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) +- +-/* PORTR - Port R */ +-#define PORTR_DIR _SFR_MEM8(0x07E0) +-#define PORTR_DIRSET _SFR_MEM8(0x07E1) +-#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +-#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +-#define PORTR_OUT _SFR_MEM8(0x07E4) +-#define PORTR_OUTSET _SFR_MEM8(0x07E5) +-#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +-#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +-#define PORTR_IN _SFR_MEM8(0x07E8) +-#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +-#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +-#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +-#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +-#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +-#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +-#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +-#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +-#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +-#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +-#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +-#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) +- +-/* TCC0 - Timer/Counter C0 */ +-#define TCC0_CTRLA _SFR_MEM8(0x0800) +-#define TCC0_CTRLB _SFR_MEM8(0x0801) +-#define TCC0_CTRLC _SFR_MEM8(0x0802) +-#define TCC0_CTRLD _SFR_MEM8(0x0803) +-#define TCC0_CTRLE _SFR_MEM8(0x0804) +-#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +-#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +-#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +-#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +-#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +-#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +-#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +-#define TCC0_TEMP _SFR_MEM8(0x080F) +-#define TCC0_CNT _SFR_MEM16(0x0820) +-#define TCC0_PER _SFR_MEM16(0x0826) +-#define TCC0_CCA _SFR_MEM16(0x0828) +-#define TCC0_CCB _SFR_MEM16(0x082A) +-#define TCC0_CCC _SFR_MEM16(0x082C) +-#define TCC0_CCD _SFR_MEM16(0x082E) +-#define TCC0_PERBUF _SFR_MEM16(0x0836) +-#define TCC0_CCABUF _SFR_MEM16(0x0838) +-#define TCC0_CCBBUF _SFR_MEM16(0x083A) +-#define TCC0_CCCBUF _SFR_MEM16(0x083C) +-#define TCC0_CCDBUF _SFR_MEM16(0x083E) +- +-/* TCC1 - Timer/Counter C1 */ +-#define TCC1_CTRLA _SFR_MEM8(0x0840) +-#define TCC1_CTRLB _SFR_MEM8(0x0841) +-#define TCC1_CTRLC _SFR_MEM8(0x0842) +-#define TCC1_CTRLD _SFR_MEM8(0x0843) +-#define TCC1_CTRLE _SFR_MEM8(0x0844) +-#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +-#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +-#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +-#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +-#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +-#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +-#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +-#define TCC1_TEMP _SFR_MEM8(0x084F) +-#define TCC1_CNT _SFR_MEM16(0x0860) +-#define TCC1_PER _SFR_MEM16(0x0866) +-#define TCC1_CCA _SFR_MEM16(0x0868) +-#define TCC1_CCB _SFR_MEM16(0x086A) +-#define TCC1_PERBUF _SFR_MEM16(0x0876) +-#define TCC1_CCABUF _SFR_MEM16(0x0878) +-#define TCC1_CCBBUF _SFR_MEM16(0x087A) +- +-/* AWEXC - Advanced Waveform Extension C */ +-#define AWEXC_CTRL _SFR_MEM8(0x0880) +-#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +-#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +-#define AWEXC_STATUS _SFR_MEM8(0x0884) +-#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +-#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +-#define AWEXC_DTLS _SFR_MEM8(0x0888) +-#define AWEXC_DTHS _SFR_MEM8(0x0889) +-#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +-#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +-#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) +- +-/* HIRESC - High-Resolution Extension C */ +-#define HIRESC_CTRLA _SFR_MEM8(0x0890) +- +-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +-#define USARTC0_DATA _SFR_MEM8(0x08A0) +-#define USARTC0_STATUS _SFR_MEM8(0x08A1) +-#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +-#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +-#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +-#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +-#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) +- +-/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ +-#define USARTC1_DATA _SFR_MEM8(0x08B0) +-#define USARTC1_STATUS _SFR_MEM8(0x08B1) +-#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +-#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +-#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +-#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +-#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) +- +-/* SPIC - Serial Peripheral Interface C */ +-#define SPIC_CTRL _SFR_MEM8(0x08C0) +-#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +-#define SPIC_STATUS _SFR_MEM8(0x08C2) +-#define SPIC_DATA _SFR_MEM8(0x08C3) +- +-/* IRCOM - IR Communication Module */ +-#define IRCOM_CTRL _SFR_MEM8(0x08F8) +-#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +-#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) +- +-/* TCD0 - Timer/Counter D0 */ +-#define TCD0_CTRLA _SFR_MEM8(0x0900) +-#define TCD0_CTRLB _SFR_MEM8(0x0901) +-#define TCD0_CTRLC _SFR_MEM8(0x0902) +-#define TCD0_CTRLD _SFR_MEM8(0x0903) +-#define TCD0_CTRLE _SFR_MEM8(0x0904) +-#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +-#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +-#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +-#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +-#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +-#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +-#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +-#define TCD0_TEMP _SFR_MEM8(0x090F) +-#define TCD0_CNT _SFR_MEM16(0x0920) +-#define TCD0_PER _SFR_MEM16(0x0926) +-#define TCD0_CCA _SFR_MEM16(0x0928) +-#define TCD0_CCB _SFR_MEM16(0x092A) +-#define TCD0_CCC _SFR_MEM16(0x092C) +-#define TCD0_CCD _SFR_MEM16(0x092E) +-#define TCD0_PERBUF _SFR_MEM16(0x0936) +-#define TCD0_CCABUF _SFR_MEM16(0x0938) +-#define TCD0_CCBBUF _SFR_MEM16(0x093A) +-#define TCD0_CCCBUF _SFR_MEM16(0x093C) +-#define TCD0_CCDBUF _SFR_MEM16(0x093E) +- +-/* TCD1 - Timer/Counter D1 */ +-#define TCD1_CTRLA _SFR_MEM8(0x0940) +-#define TCD1_CTRLB _SFR_MEM8(0x0941) +-#define TCD1_CTRLC _SFR_MEM8(0x0942) +-#define TCD1_CTRLD _SFR_MEM8(0x0943) +-#define TCD1_CTRLE _SFR_MEM8(0x0944) +-#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +-#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +-#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +-#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +-#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +-#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +-#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +-#define TCD1_TEMP _SFR_MEM8(0x094F) +-#define TCD1_CNT _SFR_MEM16(0x0960) +-#define TCD1_PER _SFR_MEM16(0x0966) +-#define TCD1_CCA _SFR_MEM16(0x0968) +-#define TCD1_CCB _SFR_MEM16(0x096A) +-#define TCD1_PERBUF _SFR_MEM16(0x0976) +-#define TCD1_CCABUF _SFR_MEM16(0x0978) +-#define TCD1_CCBBUF _SFR_MEM16(0x097A) +- +-/* HIRESD - High-Resolution Extension D */ +-#define HIRESD_CTRLA _SFR_MEM8(0x0990) +- +-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +-#define USARTD0_DATA _SFR_MEM8(0x09A0) +-#define USARTD0_STATUS _SFR_MEM8(0x09A1) +-#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +-#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +-#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +-#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +-#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) +- +-/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ +-#define USARTD1_DATA _SFR_MEM8(0x09B0) +-#define USARTD1_STATUS _SFR_MEM8(0x09B1) +-#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +-#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +-#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +-#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +-#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) +- +-/* SPID - Serial Peripheral Interface D */ +-#define SPID_CTRL _SFR_MEM8(0x09C0) +-#define SPID_INTCTRL _SFR_MEM8(0x09C1) +-#define SPID_STATUS _SFR_MEM8(0x09C2) +-#define SPID_DATA _SFR_MEM8(0x09C3) +- +-/* TCE0 - Timer/Counter E0 */ +-#define TCE0_CTRLA _SFR_MEM8(0x0A00) +-#define TCE0_CTRLB _SFR_MEM8(0x0A01) +-#define TCE0_CTRLC _SFR_MEM8(0x0A02) +-#define TCE0_CTRLD _SFR_MEM8(0x0A03) +-#define TCE0_CTRLE _SFR_MEM8(0x0A04) +-#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +-#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +-#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +-#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +-#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +-#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +-#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +-#define TCE0_TEMP _SFR_MEM8(0x0A0F) +-#define TCE0_CNT _SFR_MEM16(0x0A20) +-#define TCE0_PER _SFR_MEM16(0x0A26) +-#define TCE0_CCA _SFR_MEM16(0x0A28) +-#define TCE0_CCB _SFR_MEM16(0x0A2A) +-#define TCE0_CCC _SFR_MEM16(0x0A2C) +-#define TCE0_CCD _SFR_MEM16(0x0A2E) +-#define TCE0_PERBUF _SFR_MEM16(0x0A36) +-#define TCE0_CCABUF _SFR_MEM16(0x0A38) +-#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +-#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +-#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) +- +-/* TCE1 - Timer/Counter E1 */ +-#define TCE1_CTRLA _SFR_MEM8(0x0A40) +-#define TCE1_CTRLB _SFR_MEM8(0x0A41) +-#define TCE1_CTRLC _SFR_MEM8(0x0A42) +-#define TCE1_CTRLD _SFR_MEM8(0x0A43) +-#define TCE1_CTRLE _SFR_MEM8(0x0A44) +-#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) +-#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) +-#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) +-#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) +-#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) +-#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) +-#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) +-#define TCE1_TEMP _SFR_MEM8(0x0A4F) +-#define TCE1_CNT _SFR_MEM16(0x0A60) +-#define TCE1_PER _SFR_MEM16(0x0A66) +-#define TCE1_CCA _SFR_MEM16(0x0A68) +-#define TCE1_CCB _SFR_MEM16(0x0A6A) +-#define TCE1_PERBUF _SFR_MEM16(0x0A76) +-#define TCE1_CCABUF _SFR_MEM16(0x0A78) +-#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) +- +-/* AWEXE - Advanced Waveform Extension E */ +-#define AWEXE_CTRL _SFR_MEM8(0x0A80) +-#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +-#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +-#define AWEXE_STATUS _SFR_MEM8(0x0A84) +-#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +-#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +-#define AWEXE_DTLS _SFR_MEM8(0x0A88) +-#define AWEXE_DTHS _SFR_MEM8(0x0A89) +-#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +-#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +-#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) +- +-/* HIRESE - High-Resolution Extension E */ +-#define HIRESE_CTRLA _SFR_MEM8(0x0A90) +- +-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +-#define USARTE0_DATA _SFR_MEM8(0x0AA0) +-#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +-#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +-#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +-#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +-#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +-#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) +- +-/* TCF0 - Timer/Counter F0 */ +-#define TCF0_CTRLA _SFR_MEM8(0x0B00) +-#define TCF0_CTRLB _SFR_MEM8(0x0B01) +-#define TCF0_CTRLC _SFR_MEM8(0x0B02) +-#define TCF0_CTRLD _SFR_MEM8(0x0B03) +-#define TCF0_CTRLE _SFR_MEM8(0x0B04) +-#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +-#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +-#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +-#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +-#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +-#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +-#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +-#define TCF0_TEMP _SFR_MEM8(0x0B0F) +-#define TCF0_CNT _SFR_MEM16(0x0B20) +-#define TCF0_PER _SFR_MEM16(0x0B26) +-#define TCF0_CCA _SFR_MEM16(0x0B28) +-#define TCF0_CCB _SFR_MEM16(0x0B2A) +-#define TCF0_CCC _SFR_MEM16(0x0B2C) +-#define TCF0_CCD _SFR_MEM16(0x0B2E) +-#define TCF0_PERBUF _SFR_MEM16(0x0B36) +-#define TCF0_CCABUF _SFR_MEM16(0x0B38) +-#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +-#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +-#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) +- +-/* HIRESF - High-Resolution Extension F */ +-#define HIRESF_CTRLA _SFR_MEM8(0x0B90) +- +-/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ +-#define USARTF0_DATA _SFR_MEM8(0x0BA0) +-#define USARTF0_STATUS _SFR_MEM8(0x0BA1) +-#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) +-#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) +-#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) +-#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) +-#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) +- +-/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ +-#define USARTF1_DATA _SFR_MEM8(0x0BB0) +-#define USARTF1_STATUS _SFR_MEM8(0x0BB1) +-#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) +-#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) +-#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) +-#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) +-#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) +- +-/* SPIF - Serial Peripheral Interface F */ +-#define SPIF_CTRL _SFR_MEM8(0x0BC0) +-#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) +-#define SPIF_STATUS _SFR_MEM8(0x0BC2) +-#define SPIF_DATA _SFR_MEM8(0x0BC3) +- +- +- +-/*================== Bitfield Definitions ================== */ +- +-/* XOCD - On-Chip Debug System */ +-/* OCD.OCDR1 bit masks and bit positions */ +-#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +-#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ +- +- +-/* CPU - CPU */ +-/* CPU.CCP bit masks and bit positions */ +-#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +-#define CPU_CCP_gp 0 /* CCP signature group position. */ +-#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +-#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +-#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +-#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +-#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +-#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +-#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +-#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +-#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +-#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +-#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +-#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +-#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +-#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +-#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +-#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ +- +- +-/* CPU.SREG bit masks and bit positions */ +-#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +-#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ +- +-#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +-#define CPU_T_bp 6 /* Transfer Bit bit position. */ +- +-#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +-#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +- +-#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +-#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +- +-#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +-#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +- +-#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +-#define CPU_N_bp 2 /* Negative Flag bit position. */ +- +-#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +-#define CPU_Z_bp 1 /* Zero Flag bit position. */ +- +-#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +-#define CPU_C_bp 0 /* Carry Flag bit position. */ +- +- +-/* CLK - Clock System */ +-/* CLK.CTRL bit masks and bit positions */ +-#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +-#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +-#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +-#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +-#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +-#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +-#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +-#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ +- +- +-/* CLK.PSCTRL bit masks and bit positions */ +-#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +-#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +-#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +-#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +-#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +-#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +-#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +-#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +-#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +-#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +-#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +-#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ +- +-#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +-#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +-#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +-#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +-#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +-#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ +- +- +-/* CLK.LOCK bit masks and bit positions */ +-#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +-#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ +- +- +-/* CLK.RTCCTRL bit masks and bit positions */ +-#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +-#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +-#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +-#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +-#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +-#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +-#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +-#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ +- +-#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +-#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ +- +- +-/* PR.PRGEN bit masks and bit positions */ +-#define PR_AES_bm 0x10 /* AES bit mask. */ +-#define PR_AES_bp 4 /* AES bit position. */ +- +-#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +-#define PR_EBI_bp 3 /* External Bus Interface bit position. */ +- +-#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +-#define PR_RTC_bp 2 /* Real-time Counter bit position. */ +- +-#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +-#define PR_EVSYS_bp 1 /* Event System bit position. */ +- +-#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +-#define PR_DMA_bp 0 /* DMA-Controller bit position. */ +- +- +-/* PR.PRPA bit masks and bit positions */ +-#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +-#define PR_DAC_bp 2 /* Port A DAC bit position. */ +- +-#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +-#define PR_ADC_bp 1 /* Port A ADC bit position. */ +- +-#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +-#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ +- +- +-/* PR.PRPB bit masks and bit positions */ +-/* PR_DAC_bm Predefined. */ +-/* PR_DAC_bp Predefined. */ +- +-/* PR_ADC_bm Predefined. */ +-/* PR_ADC_bp Predefined. */ +- +-/* PR_AC_bm Predefined. */ +-/* PR_AC_bp Predefined. */ +- +- +-/* PR.PRPC bit masks and bit positions */ +-#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +-#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ +- +-#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +-#define PR_USART1_bp 5 /* Port C USART1 bit position. */ +- +-#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +-#define PR_USART0_bp 4 /* Port C USART0 bit position. */ +- +-#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +-#define PR_SPI_bp 3 /* Port C SPI bit position. */ +- +-#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +-#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ +- +-#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +-#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ +- +-#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +-#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ +- +- +-/* PR.PRPD bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* PR.PRPE bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* PR.PRPF bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* SLEEP - Sleep Controller */ +-/* SLEEP.CTRL bit masks and bit positions */ +-#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +-#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +-#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +-#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +-#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +-#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +-#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +-#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ +- +-#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +-#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ +- +- +-/* OSC - Oscillator */ +-/* OSC.CTRL bit masks and bit positions */ +-#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +-#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ +- +-#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +-#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ +- +-#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ +- +- +-/* OSC.STATUS bit masks and bit positions */ +-#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +-#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ +- +-#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +-#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ +- +-#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ +- +- +-/* OSC.XOSCCTRL bit masks and bit positions */ +-#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +-#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +-#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +-#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +-#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +-#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ +- +-#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +-#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ +- +-#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +-#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +-#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +-#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +-#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +-#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +-#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +-#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +-#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +-#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +- +- +-/* OSC.XOSCFAIL bit masks and bit positions */ +-#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +-#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ +- +-#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +-#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ +- +- +-/* OSC.PLLCTRL bit masks and bit positions */ +-#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +-#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +-#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +-#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +-#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +-#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ +- +-#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +-#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +-#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +-#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +-#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +-#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +-#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +-#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +-#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +-#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +-#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +-#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ +- +- +-/* OSC.DFLLCTRL bit masks and bit positions */ +-#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +-#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ +- +-#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +-#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ +- +- +-/* DFLL - DFLL */ +-/* DFLL.CTRL bit masks and bit positions */ +-#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +-#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ +- +- +-/* DFLL.CALA bit masks and bit positions */ +-#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +-#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +-#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +-#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +-#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +-#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +-#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +-#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +-#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +-#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +-#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +-#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +-#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +-#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +-#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +-#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ +- +- +-/* DFLL.CALB bit masks and bit positions */ +-#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +-#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +-#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +-#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +-#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +-#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +-#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +-#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +-#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +-#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +-#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +-#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +-#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +-#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ +- +- +-/* RST - Reset */ +-/* RST.STATUS bit masks and bit positions */ +-#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +-#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ +- +-#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +-#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ +- +-#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +-#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ +- +-#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +-#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ +- +-#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +-#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ +- +-#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +-#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ +- +-#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +-#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ +- +- +-/* RST.CTRL bit masks and bit positions */ +-#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +-#define RST_SWRST_bp 0 /* Software Reset bit position. */ +- +- +-/* WDT - Watch-Dog Timer */ +-/* WDT.CTRL bit masks and bit positions */ +-#define WDT_PER_gm 0x3C /* Period group mask. */ +-#define WDT_PER_gp 2 /* Period group position. */ +-#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +-#define WDT_PER0_bp 2 /* Period bit 0 position. */ +-#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +-#define WDT_PER1_bp 3 /* Period bit 1 position. */ +-#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +-#define WDT_PER2_bp 4 /* Period bit 2 position. */ +-#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +-#define WDT_PER3_bp 5 /* Period bit 3 position. */ +- +-#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +-#define WDT_ENABLE_bp 1 /* Enable bit position. */ +- +-#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +-#define WDT_CEN_bp 0 /* Change Enable bit position. */ +- +- +-/* WDT.WINCTRL bit masks and bit positions */ +-#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +-#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +-#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +-#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +-#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +-#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +-#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +-#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +-#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +-#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ +- +-#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +-#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ +- +-#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +-#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ +- +- +-/* WDT.STATUS bit masks and bit positions */ +-#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +-#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +- +- +-/* MCU - MCU Control */ +-/* MCU.MCUCR bit masks and bit positions */ +-#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +-#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ +- +- +-/* MCU.EVSYSLOCK bit masks and bit positions */ +-#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +-#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ +- +-#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +-#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ +- +- +-/* MCU.AWEXLOCK bit masks and bit positions */ +-#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +-#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ +- +-#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +-#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ +- +- +-/* PMIC - Programmable Multi-level Interrupt Controller */ +-/* PMIC.STATUS bit masks and bit positions */ +-#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +-#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ +- +-#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +-#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ +- +-#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +-#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ +- +-#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +-#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ +- +- +-/* PMIC.CTRL bit masks and bit positions */ +-#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +-#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ +- +-#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +-#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ +- +-#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +-#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ +- +-#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +-#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ +- +-#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +-#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ +- +- +-/* DMA - DMA Controller */ +-/* DMA_CH.CTRLA bit masks and bit positions */ +-#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +-#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ +- +-#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +-#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ +- +-#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +-#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ +- +-#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +-#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ +- +-#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +-#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ +- +-#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +-#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +-#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +-#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +-#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +-#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ +- +- +-/* DMA_CH.CTRLB bit masks and bit positions */ +-#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +-#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ +- +-#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +-#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ +- +-#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +-#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ +- +-#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +-#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +-#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +-#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +-#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +-#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ +- +-#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +-#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +-#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +-#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +-#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +-#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ +- +- +-/* DMA_CH.ADDRCTRL bit masks and bit positions */ +-#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +-#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +-#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +-#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +-#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +-#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ +- +-#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +-#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +-#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +-#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +-#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +-#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ +- +-#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +-#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +-#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +-#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +-#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +-#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ +- +-#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +-#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +-#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +-#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +-#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +-#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ +- +- +-/* DMA_CH.TRIGSRC bit masks and bit positions */ +-#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +-#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +-#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +-#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +-#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +-#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +-#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +-#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +-#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +-#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +-#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +-#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +-#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +-#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +-#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +-#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +-#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +-#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ +- +- +-/* DMA.CTRL bit masks and bit positions */ +-#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +-#define DMA_ENABLE_bp 7 /* Enable bit position. */ +- +-#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +-#define DMA_RESET_bp 6 /* Software Reset bit position. */ +- +-#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +-#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +-#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +-#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +-#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +-#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ +- +-#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +-#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +-#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +-#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +-#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +-#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ +- +- +-/* DMA.INTFLAGS bit masks and bit positions */ +-#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ +- +- +-/* DMA.STATUS bit masks and bit positions */ +-#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +-#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ +- +-#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +-#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ +- +-#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +-#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ +- +-#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +-#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ +- +-#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +-#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ +- +-#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +-#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ +- +-#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +-#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ +- +-#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +-#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ +- +- +-/* EVSYS - Event System */ +-/* EVSYS.CH0MUX bit masks and bit positions */ +-#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +-#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +-#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +-#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +-#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +-#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +-#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +-#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +-#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +-#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +-#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +-#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +-#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +-#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +-#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +-#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +-#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +-#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ +- +- +-/* EVSYS.CH1MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH2MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH3MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH4MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH5MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH6MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH7MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH0CTRL bit masks and bit positions */ +-#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +-#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +-#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +-#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +-#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +-#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ +- +-#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +-#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ +- +-#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +-#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ +- +-#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +-#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +-#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +-#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +-#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +-#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +-#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +-#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ +- +- +-/* EVSYS.CH1CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH2CTRL bit masks and bit positions */ +-/* EVSYS_QDIRM_gm Predefined. */ +-/* EVSYS_QDIRM_gp Predefined. */ +-/* EVSYS_QDIRM0_bm Predefined. */ +-/* EVSYS_QDIRM0_bp Predefined. */ +-/* EVSYS_QDIRM1_bm Predefined. */ +-/* EVSYS_QDIRM1_bp Predefined. */ +- +-/* EVSYS_QDIEN_bm Predefined. */ +-/* EVSYS_QDIEN_bp Predefined. */ +- +-/* EVSYS_QDEN_bm Predefined. */ +-/* EVSYS_QDEN_bp Predefined. */ +- +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH3CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH4CTRL bit masks and bit positions */ +-/* EVSYS_QDIRM_gm Predefined. */ +-/* EVSYS_QDIRM_gp Predefined. */ +-/* EVSYS_QDIRM0_bm Predefined. */ +-/* EVSYS_QDIRM0_bp Predefined. */ +-/* EVSYS_QDIRM1_bm Predefined. */ +-/* EVSYS_QDIRM1_bp Predefined. */ +- +-/* EVSYS_QDIEN_bm Predefined. */ +-/* EVSYS_QDIEN_bp Predefined. */ +- +-/* EVSYS_QDEN_bm Predefined. */ +-/* EVSYS_QDEN_bp Predefined. */ +- +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH5CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH6CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH7CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* NVM - Non Volatile Memory Controller */ +-/* NVM.CMD bit masks and bit positions */ +-#define NVM_CMD_gm 0xFF /* Command group mask. */ +-#define NVM_CMD_gp 0 /* Command group position. */ +-#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +-#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +-#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +-#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +-#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +-#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +-#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +-#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +-#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +-#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +-#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +-#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +-#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +-#define NVM_CMD7_bp 7 /* Command bit 7 position. */ +- +- +-/* NVM.CTRLA bit masks and bit positions */ +-#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +-#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ +- +- +-/* NVM.CTRLB bit masks and bit positions */ +-#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +-#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ +- +-#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +-#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ +- +-#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +-#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ +- +-#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +-#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ +- +- +-/* NVM.INTCTRL bit masks and bit positions */ +-#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +-#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +-#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +-#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +-#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +-#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ +- +-#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +-#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +-#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +-#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +-#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +-#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ +- +- +-/* NVM.STATUS bit masks and bit positions */ +-#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +-#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ +- +-#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +-#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ +- +-#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +-#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ +- +-#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +-#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ +- +- +-/* NVM.LOCKBITS bit masks and bit positions */ +-#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +-#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +-#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ +-#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ +-#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ +-#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ +-#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ +-#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ +-#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ +-#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ +-#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ +-#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ +-#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ +-#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ +-#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ +-#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ +-#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ +-#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ +-#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ +-#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +-#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +-#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +-#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ +- +-#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +-#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +-#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +-#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +-#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ +- +-#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +-#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ +- +-#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +-#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +-#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +-#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +-#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +-#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +-#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +-#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +-#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +-#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +-#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +-#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ +- +-#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +-#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ +- +-#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ +-#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ +- +- +-/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +-#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +-#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +-#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +-#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +-#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +-#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ +- +-#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +-#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ +- +-#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +-#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +-#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +-#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +-#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +-#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +-#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +-#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +- +- +-/* AC - Analog Comparator */ +-/* AC.AC0CTRL bit masks and bit positions */ +-#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +-#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +-#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +-#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +-#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +-#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ +- +-#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +-#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +-#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +-#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +-#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +-#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ +- +-#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +-#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ +- +-#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +-#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +-#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +-#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +-#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +-#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +- +-#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define AC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* AC.AC1CTRL bit masks and bit positions */ +-/* AC_INTMODE_gm Predefined. */ +-/* AC_INTMODE_gp Predefined. */ +-/* AC_INTMODE0_bm Predefined. */ +-/* AC_INTMODE0_bp Predefined. */ +-/* AC_INTMODE1_bm Predefined. */ +-/* AC_INTMODE1_bp Predefined. */ +- +-/* AC_INTLVL_gm Predefined. */ +-/* AC_INTLVL_gp Predefined. */ +-/* AC_INTLVL0_bm Predefined. */ +-/* AC_INTLVL0_bp Predefined. */ +-/* AC_INTLVL1_bm Predefined. */ +-/* AC_INTLVL1_bp Predefined. */ +- +-/* AC_HSMODE_bm Predefined. */ +-/* AC_HSMODE_bp Predefined. */ +- +-/* AC_HYSMODE_gm Predefined. */ +-/* AC_HYSMODE_gp Predefined. */ +-/* AC_HYSMODE0_bm Predefined. */ +-/* AC_HYSMODE0_bp Predefined. */ +-/* AC_HYSMODE1_bm Predefined. */ +-/* AC_HYSMODE1_bp Predefined. */ +- +-/* AC_ENABLE_bm Predefined. */ +-/* AC_ENABLE_bp Predefined. */ +- +- +-/* AC.AC0MUXCTRL bit masks and bit positions */ +-#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +-#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +-#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +-#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +-#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +-#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +-#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +-#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ +- +-#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +-#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +-#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +-#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +-#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +-#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +-#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +-#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ +- +- +-/* AC.AC1MUXCTRL bit masks and bit positions */ +-/* AC_MUXPOS_gm Predefined. */ +-/* AC_MUXPOS_gp Predefined. */ +-/* AC_MUXPOS0_bm Predefined. */ +-/* AC_MUXPOS0_bp Predefined. */ +-/* AC_MUXPOS1_bm Predefined. */ +-/* AC_MUXPOS1_bp Predefined. */ +-/* AC_MUXPOS2_bm Predefined. */ +-/* AC_MUXPOS2_bp Predefined. */ +- +-/* AC_MUXNEG_gm Predefined. */ +-/* AC_MUXNEG_gp Predefined. */ +-/* AC_MUXNEG0_bm Predefined. */ +-/* AC_MUXNEG0_bp Predefined. */ +-/* AC_MUXNEG1_bm Predefined. */ +-/* AC_MUXNEG1_bp Predefined. */ +-/* AC_MUXNEG2_bm Predefined. */ +-/* AC_MUXNEG2_bp Predefined. */ +- +- +-/* AC.CTRLA bit masks and bit positions */ +-#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +-#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ +- +- +-/* AC.CTRLB bit masks and bit positions */ +-#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +-#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +-#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +-#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +-#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +-#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +-#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +-#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +-#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +-#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +-#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +-#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +-#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +-#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ +- +- +-/* AC.WINCTRL bit masks and bit positions */ +-#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +-#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ +- +-#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +-#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +-#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +-#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +-#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +-#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ +- +-#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +-#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +-#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +-#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +-#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +-#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ +- +- +-/* AC.STATUS bit masks and bit positions */ +-#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +-#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +-#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +-#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +-#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +-#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ +- +-#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +-#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ +- +-#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +-#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ +- +-#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +-#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ +- +-#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +-#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ +- +-#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +-#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ +- +- +-/* ADC - Analog/Digital Converter */ +-/* ADC_CH.CTRL bit masks and bit positions */ +-#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +-#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ +- +-#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +-#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +-#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +-#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +-#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +-#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +-#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +-#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ +- +-#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +-#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +-#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +-#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +-#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +-#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ +- +- +-/* ADC_CH.MUXCTRL bit masks and bit positions */ +-#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +-#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +-#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +-#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +-#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +-#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +-#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +-#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +-#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +-#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ +- +-#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +-#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +-#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +-#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +-#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +-#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +-#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +-#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +-#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +-#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ +- +-#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +-#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +-#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +-#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +-#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +-#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ +- +- +-/* ADC_CH.INTCTRL bit masks and bit positions */ +-#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +-#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +-#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +-#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +-#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +-#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ +- +-#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +-#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +-#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +-#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +-#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +-#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ +- +- +-/* ADC_CH.INTFLAGS bit masks and bit positions */ +-#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +-#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ +- +- +-/* ADC.CTRLA bit masks and bit positions */ +-#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +-#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +-#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +-#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +-#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +-#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ +- +-#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +-#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ +- +-#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +-#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ +- +-#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +-#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ +- +-#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +-#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ +- +-#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +-#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ +- +-#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +-#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ +- +- +-/* ADC.CTRLB bit masks and bit positions */ +-#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +-#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ +- +-#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +-#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ +- +-#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +-#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +-#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +-#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +-#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +-#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ +- +- +-/* ADC.REFCTRL bit masks and bit positions */ +-#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +-#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +-#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +-#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +-#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +-#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +- +-#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +-#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ +- +-#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +-#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ +- +- +-/* ADC.EVCTRL bit masks and bit positions */ +-#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +-#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +-#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +-#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +-#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +-#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ +- +-#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +-#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +-#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +-#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +-#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +-#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +-#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +-#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ +- +-#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +-#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +-#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +-#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +-#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +-#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +-#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +-#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ +- +- +-/* ADC.PRESCALER bit masks and bit positions */ +-#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +-#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +-#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +-#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +-#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +-#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +-#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +-#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ +- +- +-/* ADC.INTFLAGS bit masks and bit positions */ +-#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +-#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ +- +-#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +-#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ +- +-#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +-#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ +- +-#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +-#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ +- +- +-/* DAC - Digital/Analog Converter */ +-/* DAC.CTRLA bit masks and bit positions */ +-#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +-#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ +- +-#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +-#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ +- +-#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +-#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ +- +-#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +-#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ +- +-#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define DAC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* DAC.CTRLB bit masks and bit positions */ +-#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +-#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +-#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +-#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +-#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +-#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ +- +-#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +-#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ +- +-#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +-#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ +- +- +-/* DAC.CTRLC bit masks and bit positions */ +-#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +-#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +-#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +-#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +-#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +-#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ +- +-#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +-#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ +- +- +-/* DAC.EVCTRL bit masks and bit positions */ +-#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +-#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +-#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +-#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +-#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +-#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +-#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +-#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ +- +- +-/* DAC.TIMCTRL bit masks and bit positions */ +-#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ +-#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ +-#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ +-#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ +-#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ +-#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ +-#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ +-#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ +- +-#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ +-#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ +-#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ +-#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ +-#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ +-#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ +-#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ +-#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ +-#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ +-#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ +- +- +-/* DAC.STATUS bit masks and bit positions */ +-#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +-#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ +- +-#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +-#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ +- +- +-/* RTC32 - 32-bit Real-Time Counter */ +-/* RTC32.CTRL bit masks and bit positions */ +-#define RTC32_ENABLE_bm 0x01 /* RTC enable bit mask. */ +-#define RTC32_ENABLE_bp 0 /* RTC enable bit position. */ +- +- +-/* RTC32.SYNCCTRL bit masks and bit positions */ +-#define RTC32_SYNCCNT_bm 0x10 /* Synchronization Busy Flag bit mask. */ +-#define RTC32_SYNCCNT_bp 4 /* Synchronization Busy Flag bit position. */ +- +-#define RTC32_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +-#define RTC32_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ +- +- +-/* RTC32.INTCTRL bit masks and bit positions */ +-#define RTC32_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +-#define RTC32_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +-#define RTC32_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +-#define RTC32_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +-#define RTC32_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +-#define RTC32_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ +- +-#define RTC32_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +-#define RTC32_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +-#define RTC32_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +-#define RTC32_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +-#define RTC32_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +-#define RTC32_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ +- +- +-/* RTC32.INTFLAGS bit masks and bit positions */ +-#define RTC32_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +-#define RTC32_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ +- +-#define RTC32_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define RTC32_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* EBI - External Bus Interface */ +-/* EBI_CS.CTRLA bit masks and bit positions */ +-#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +-#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +-#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +-#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +-#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +-#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +-#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +-#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +-#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +-#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +-#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +-#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ +- +-#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +-#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +-#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +-#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +-#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +-#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ +- +- +-/* EBI_CS.CTRLB bit masks and bit positions */ +-#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +-#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +-#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +-#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +-#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +-#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +-#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +-#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ +- +-#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +-#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ +- +-#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +-#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ +- +-#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +-#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +-#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +-#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +-#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +-#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ +- +- +-/* EBI.CTRL bit masks and bit positions */ +-#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +-#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +-#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +-#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +-#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +-#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ +- +-#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +-#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +-#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +-#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +-#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +-#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ +- +-#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +-#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +-#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +-#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +-#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +-#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ +- +-#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +-#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +-#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +-#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +-#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +-#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLA bit masks and bit positions */ +-#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +-#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ +- +-#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +-#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ +- +-#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +-#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +-#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +-#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +-#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +-#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLB bit masks and bit positions */ +-#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +-#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +-#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +-#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +-#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +-#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ +- +-#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +-#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +-#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +-#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +-#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +-#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +-#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +-#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ +- +-#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +-#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +-#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +-#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +-#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +-#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +-#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +-#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ +- +- +-/* EBI.SDRAMCTRLC bit masks and bit positions */ +-#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +-#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +-#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +-#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +-#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +-#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ +- +-#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +-#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +-#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +-#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +-#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +-#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +-#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +-#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ +- +-#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +-#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +-#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +-#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +-#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +-#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +-#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +-#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ +- +- +-/* TWI - Two-Wire Interface */ +-/* TWI_MASTER.CTRLA bit masks and bit positions */ +-#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +-#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ +- +-#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +-#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ +- +-#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +-#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ +- +- +-/* TWI_MASTER.CTRLB bit masks and bit positions */ +-#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +-#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +-#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +-#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +-#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +-#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +- +-#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +-#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ +- +-#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_MASTER.CTRLC bit masks and bit positions */ +-#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +-#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_MASTER.STATUS bit masks and bit positions */ +-#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +-#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ +- +-#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +-#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ +- +-#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +-#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +- +-#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +-#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +-#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +-#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +-#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +-#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +- +- +-/* TWI_SLAVE.CTRLA bit masks and bit positions */ +-#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +-#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +-#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ +- +-#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +-#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ +- +-#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_SLAVE.CTRLB bit masks and bit positions */ +-#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +-#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_SLAVE.STATUS bit masks and bit positions */ +-#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +-#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +-#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +-#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ +- +-#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +-#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ +- +-#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +-#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ +- +- +-/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +-#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +-#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +-#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +-#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +-#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +-#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +-#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +-#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +-#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +-#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +-#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +-#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +-#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +-#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +-#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +-#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ +- +-#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +-#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ +- +- +-/* TWI.CTRL bit masks and bit positions */ +-#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +-#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ +- +-#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +-#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ +- +- +-/* PORT - Port Configuration */ +-/* PORTCFG.VPCTRLA bit masks and bit positions */ +-#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +-#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +-#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +-#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +-#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +-#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +-#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +-#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +-#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +-#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ +- +-#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +-#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +-#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +-#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +-#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +-#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +-#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +-#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +-#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +-#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ +- +- +-/* PORTCFG.VPCTRLB bit masks and bit positions */ +-#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +-#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +-#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +-#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +-#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +-#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +-#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +-#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +-#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +-#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ +- +-#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +-#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +-#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +-#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +-#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +-#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +-#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +-#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +-#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +-#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ +- +- +-/* PORTCFG.CLKEVOUT bit masks and bit positions */ +-#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +-#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +-#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +-#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +-#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +-#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ +- +-#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +-#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +-#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +-#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +-#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +-#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ +- +- +-/* VPORT.INTFLAGS bit masks and bit positions */ +-#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.INTCTRL bit masks and bit positions */ +-#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +-#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +-#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +-#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +-#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +-#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ +- +-#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +-#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +-#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +-#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +-#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +-#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ +- +- +-/* PORT.INTFLAGS bit masks and bit positions */ +-#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.PIN0CTRL bit masks and bit positions */ +-#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +-#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ +- +-#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +-#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ +- +-#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +-#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +-#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +-#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +-#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +-#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +-#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +-#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ +- +-#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +-#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +-#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +-#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +-#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +-#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +-#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +-#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +- +- +-/* PORT.PIN1CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN2CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN3CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN4CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN5CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN6CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN7CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* TC - 16-bit Timer/Counter With PWM */ +-/* TC0.CTRLA bit masks and bit positions */ +-#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC0.CTRLB bit masks and bit positions */ +-#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +-#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ +- +-#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +-#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ +- +-#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC0.CTRLC bit masks and bit positions */ +-#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +-#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ +- +-#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +-#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ +- +-#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC0.CTRLD bit masks and bit positions */ +-#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC0_EVACT_gp 5 /* Event Action group position. */ +-#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC0.CTRLE bit masks and bit positions */ +-#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +-#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ +- +-#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC0.INTCTRLA bit masks and bit positions */ +-#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC0.INTCTRLB bit masks and bit positions */ +-#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +-#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +-#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +-#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +-#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +-#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ +- +-#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +-#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +-#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +-#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +-#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +-#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ +- +-#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC0.CTRLFCLR bit masks and bit positions */ +-#define TC0_CMD_gm 0x0C /* Command group mask. */ +-#define TC0_CMD_gp 2 /* Command group position. */ +-#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC0_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC0_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC0_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC0.CTRLFSET bit masks and bit positions */ +-/* TC0_CMD_gm Predefined. */ +-/* TC0_CMD_gp Predefined. */ +-/* TC0_CMD0_bm Predefined. */ +-/* TC0_CMD0_bp Predefined. */ +-/* TC0_CMD1_bm Predefined. */ +-/* TC0_CMD1_bp Predefined. */ +- +-/* TC0_LUPD_bm Predefined. */ +-/* TC0_LUPD_bp Predefined. */ +- +-/* TC0_DIR_bm Predefined. */ +-/* TC0_DIR_bp Predefined. */ +- +- +-/* TC0.CTRLGCLR bit masks and bit positions */ +-#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +-#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ +- +-#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +-#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ +- +-#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC0.CTRLGSET bit masks and bit positions */ +-/* TC0_CCDBV_bm Predefined. */ +-/* TC0_CCDBV_bp Predefined. */ +- +-/* TC0_CCCBV_bm Predefined. */ +-/* TC0_CCCBV_bp Predefined. */ +- +-/* TC0_CCBBV_bm Predefined. */ +-/* TC0_CCBBV_bp Predefined. */ +- +-/* TC0_CCABV_bm Predefined. */ +-/* TC0_CCABV_bp Predefined. */ +- +-/* TC0_PERBV_bm Predefined. */ +-/* TC0_PERBV_bp Predefined. */ +- +- +-/* TC0.INTFLAGS bit masks and bit positions */ +-#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +-#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ +- +-#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +-#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ +- +-#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* TC1.CTRLA bit masks and bit positions */ +-#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC1.CTRLB bit masks and bit positions */ +-#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC1.CTRLC bit masks and bit positions */ +-#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC1.CTRLD bit masks and bit positions */ +-#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC1_EVACT_gp 5 /* Event Action group position. */ +-#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC1.CTRLE bit masks and bit positions */ +-#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +-#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ +- +-#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC1.INTCTRLA bit masks and bit positions */ +-#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC1.INTCTRLB bit masks and bit positions */ +-#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC1.CTRLFCLR bit masks and bit positions */ +-#define TC1_CMD_gm 0x0C /* Command group mask. */ +-#define TC1_CMD_gp 2 /* Command group position. */ +-#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC1_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC1_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC1_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC1.CTRLFSET bit masks and bit positions */ +-/* TC1_CMD_gm Predefined. */ +-/* TC1_CMD_gp Predefined. */ +-/* TC1_CMD0_bm Predefined. */ +-/* TC1_CMD0_bp Predefined. */ +-/* TC1_CMD1_bm Predefined. */ +-/* TC1_CMD1_bp Predefined. */ +- +-/* TC1_LUPD_bm Predefined. */ +-/* TC1_LUPD_bp Predefined. */ +- +-/* TC1_DIR_bm Predefined. */ +-/* TC1_DIR_bp Predefined. */ +- +- +-/* TC1.CTRLGCLR bit masks and bit positions */ +-#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC1.CTRLGSET bit masks and bit positions */ +-/* TC1_CCBBV_bm Predefined. */ +-/* TC1_CCBBV_bp Predefined. */ +- +-/* TC1_CCABV_bm Predefined. */ +-/* TC1_CCABV_bp Predefined. */ +- +-/* TC1_PERBV_bm Predefined. */ +-/* TC1_PERBV_bp Predefined. */ +- +- +-/* TC1.INTFLAGS bit masks and bit positions */ +-#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* AWEX.CTRL bit masks and bit positions */ +-#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +-#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ +- +-#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +-#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ +- +-#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +-#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ +- +-#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +-#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ +- +-#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +-#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ +- +-#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +-#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ +- +- +-/* AWEX.FDCTRL bit masks and bit positions */ +-#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +-#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ +- +-#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +-#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ +- +-#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +-#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +-#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +-#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +-#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +-#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ +- +- +-/* AWEX.STATUS bit masks and bit positions */ +-#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +-#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ +- +-#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +-#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ +- +-#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +-#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ +- +- +-/* HIRES.CTRL bit masks and bit positions */ +-#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +-#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +-#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +-#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +-#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +-#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ +- +- +-/* USART - Universal Asynchronous Receiver-Transmitter */ +-/* USART.STATUS bit masks and bit positions */ +-#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +-#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ +- +-#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +-#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +- +-#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +-#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +- +-#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +-#define USART_FERR_bp 4 /* Frame Error bit position. */ +- +-#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +-#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ +- +-#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +-#define USART_PERR_bp 2 /* Parity Error bit position. */ +- +-#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +-#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ +- +- +-/* USART.CTRLA bit masks and bit positions */ +-#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +-#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +-#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +-#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +-#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +-#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ +- +-#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +-#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +-#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +-#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +-#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +-#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ +- +-#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +-#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +-#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +-#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +-#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +-#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ +- +- +-/* USART.CTRLB bit masks and bit positions */ +-#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +-#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ +- +-#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +-#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ +- +-#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +-#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ +- +-#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +-#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ +- +-#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +-#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ +- +- +-/* USART.CTRLC bit masks and bit positions */ +-#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +-#define USART_CMODE_gp 6 /* Communication Mode group position. */ +-#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +-#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +-#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +-#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ +- +-#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +-#define USART_PMODE_gp 4 /* Parity Mode group position. */ +-#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +-#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +-#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +-#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +- +-#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +-#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +- +-#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +-#define USART_CHSIZE_gp 0 /* Character Size group position. */ +-#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +-#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +-#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +-#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +-#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +-#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +- +- +-/* USART.BAUDCTRLA bit masks and bit positions */ +-#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +-#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +-#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +-#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +-#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +-#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +-#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +-#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +-#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +-#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +-#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +-#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +-#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +-#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +-#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +-#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +-#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +-#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ +- +- +-/* USART.BAUDCTRLB bit masks and bit positions */ +-#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +-#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +-#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +-#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +-#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +-#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +-#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +-#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +-#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +-#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ +- +-/* USART_BSEL_gm Predefined. */ +-/* USART_BSEL_gp Predefined. */ +-/* USART_BSEL0_bm Predefined. */ +-/* USART_BSEL0_bp Predefined. */ +-/* USART_BSEL1_bm Predefined. */ +-/* USART_BSEL1_bp Predefined. */ +-/* USART_BSEL2_bm Predefined. */ +-/* USART_BSEL2_bp Predefined. */ +-/* USART_BSEL3_bm Predefined. */ +-/* USART_BSEL3_bp Predefined. */ +- +- +-/* SPI - Serial Peripheral Interface */ +-/* SPI.CTRL bit masks and bit positions */ +-#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +-#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ +- +-#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +-#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ +- +-#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +-#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ +- +-#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +-#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ +- +-#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +-#define SPI_MODE_gp 2 /* SPI Mode group position. */ +-#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +-#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +-#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +-#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ +- +-#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +-#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +-#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +-#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +-#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +-#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ +- +- +-/* SPI.INTCTRL bit masks and bit positions */ +-#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +-#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +-/* SPI.STATUS bit masks and bit positions */ +-#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +-#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ +- +-#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +-#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +- +- +-/* IRCOM - IR Communication Module */ +-/* IRCOM.CTRL bit masks and bit positions */ +-#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +-#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +-#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +-#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +-#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +-#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +-#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +-#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +-#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +-#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ +- +- +-/* AES - AES Module */ +-/* AES.CTRL bit masks and bit positions */ +-#define AES_START_bm 0x80 /* Start/Run bit mask. */ +-#define AES_START_bp 7 /* Start/Run bit position. */ +- +-#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +-#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ +- +-#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +-#define AES_RESET_bp 5 /* AES Software Reset bit position. */ +- +-#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +-#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ +- +-#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +-#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ +- +- +-/* AES.STATUS bit masks and bit positions */ +-#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +-#define AES_ERROR_bp 7 /* AES Error bit position. */ +- +-#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +-#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ +- +- +-/* AES.INTCTRL bit masks and bit positions */ +-#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +-#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +-/* VBAT - VBAT Battery Backup Module */ +-/* VBAT.CTRL bit masks and bit positions */ +-#define VBAT_XOSCSEL_bm 0x10 /* 32-kHz Crystal Oscillator Output Selection bit mask. */ +-#define VBAT_XOSCSEL_bp 4 /* 32-kHz Crystal Oscillator Output Selection bit position. */ +- +-#define VBAT_XOSCEN_bm 0x08 /* Crystal Oscillator Enable bit mask. */ +-#define VBAT_XOSCEN_bp 3 /* Crystal Oscillator Enable bit position. */ +- +-#define VBAT_XOSCFDEN_bm 0x04 /* Crystal Oscillator Failure Detection Monitor Enable bit mask. */ +-#define VBAT_XOSCFDEN_bp 2 /* Crystal Oscillator Failure Detection Monitor Enable bit position. */ +- +-#define VBAT_ACCEN_bm 0x02 /* Battery Backup Access Enable bit mask. */ +-#define VBAT_ACCEN_bp 1 /* Battery Backup Access Enable bit position. */ +- +-#define VBAT_RESET_bm 0x01 /* Battery Backup Reset bit mask. */ +-#define VBAT_RESET_bp 0 /* Battery Backup Reset bit position. */ +- +- +-/* VBAT.STATUS bit masks and bit positions */ +-#define VBAT_BBPWR_bm 0x80 /* Battery backup Power bit mask. */ +-#define VBAT_BBPWR_bp 7 /* Battery backup Power bit position. */ +- +-#define VBAT_XOSCRDY_bm 0x08 /* Crystal Oscillator Ready bit mask. */ +-#define VBAT_XOSCRDY_bp 3 /* Crystal Oscillator Ready bit position. */ +- +-#define VBAT_XOSCFAIL_bm 0x04 /* Crystal Oscillator Failure bit mask. */ +-#define VBAT_XOSCFAIL_bp 2 /* Crystal Oscillator Failure bit position. */ +- +-#define VBAT_BBBORF_bm 0x02 /* Battery Backup Brown-Out Reset Flag bit mask. */ +-#define VBAT_BBBORF_bp 1 /* Battery Backup Brown-Out Reset Flag bit position. */ +- +-#define VBAT_BBPORF_bm 0x01 /* Battery Backup Power-On Reset Flag bit mask. */ +-#define VBAT_BBPORF_bp 0 /* Battery Backup Power-On Reset Flag bit position. */ +- +- +- +-// Generic Port Pins +- +-#define PIN0_bm 0x01 +-#define PIN0_bp 0 +-#define PIN1_bm 0x02 +-#define PIN1_bp 1 +-#define PIN2_bm 0x04 +-#define PIN2_bp 2 +-#define PIN3_bm 0x08 +-#define PIN3_bp 3 +-#define PIN4_bm 0x10 +-#define PIN4_bp 4 +-#define PIN5_bm 0x20 +-#define PIN5_bp 5 +-#define PIN6_bm 0x40 +-#define PIN6_bp 6 +-#define PIN7_bm 0x80 +-#define PIN7_bp 7 +- +- +-/* ========== Interrupt Vector Definitions ========== */ +-/* Vector 0 is the reset vector */ +- +-/* OSC interrupt vectors */ +-#define OSC_XOSCF_vect_num 1 +-#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ +- +-/* PORTC interrupt vectors */ +-#define PORTC_INT0_vect_num 2 +-#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +-#define PORTC_INT1_vect_num 3 +-#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ +- +-/* PORTR interrupt vectors */ +-#define PORTR_INT0_vect_num 4 +-#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +-#define PORTR_INT1_vect_num 5 +-#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ +- +-/* DMA interrupt vectors */ +-#define DMA_CH0_vect_num 6 +-#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +-#define DMA_CH1_vect_num 7 +-#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +-#define DMA_CH2_vect_num 8 +-#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +-#define DMA_CH3_vect_num 9 +-#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ +- +-/* RTC32 interrupt vectors */ +-#define RTC32_OVF_vect_num 10 +-#define RTC32_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +-#define RTC32_COMP_vect_num 11 +-#define RTC32_COMP_vect _VECTOR(11) /* Compare Interrupt */ +- +-/* TWIC interrupt vectors */ +-#define TWIC_TWIS_vect_num 12 +-#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +-#define TWIC_TWIM_vect_num 13 +-#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ +- +-/* TCC0 interrupt vectors */ +-#define TCC0_OVF_vect_num 14 +-#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +-#define TCC0_ERR_vect_num 15 +-#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +-#define TCC0_CCA_vect_num 16 +-#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +-#define TCC0_CCB_vect_num 17 +-#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +-#define TCC0_CCC_vect_num 18 +-#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +-#define TCC0_CCD_vect_num 19 +-#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ +- +-/* TCC1 interrupt vectors */ +-#define TCC1_OVF_vect_num 20 +-#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +-#define TCC1_ERR_vect_num 21 +-#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +-#define TCC1_CCA_vect_num 22 +-#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +-#define TCC1_CCB_vect_num 23 +-#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ +- +-/* SPIC interrupt vectors */ +-#define SPIC_INT_vect_num 24 +-#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ +- +-/* USARTC0 interrupt vectors */ +-#define USARTC0_RXC_vect_num 25 +-#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +-#define USARTC0_DRE_vect_num 26 +-#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +-#define USARTC0_TXC_vect_num 27 +-#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ +- +-/* USARTC1 interrupt vectors */ +-#define USARTC1_RXC_vect_num 28 +-#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +-#define USARTC1_DRE_vect_num 29 +-#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +-#define USARTC1_TXC_vect_num 30 +-#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ +- +-/* AES interrupt vectors */ +-#define AES_INT_vect_num 31 +-#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ +- +-/* NVM interrupt vectors */ +-#define NVM_EE_vect_num 32 +-#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +-#define NVM_SPM_vect_num 33 +-#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ +- +-/* PORTB interrupt vectors */ +-#define PORTB_INT0_vect_num 34 +-#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +-#define PORTB_INT1_vect_num 35 +-#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ +- +-/* ACB interrupt vectors */ +-#define ACB_AC0_vect_num 36 +-#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ +-#define ACB_AC1_vect_num 37 +-#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ +-#define ACB_ACW_vect_num 38 +-#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ +- +-/* ADCB interrupt vectors */ +-#define ADCB_CH0_vect_num 39 +-#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ +-#define ADCB_CH1_vect_num 40 +-#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ +-#define ADCB_CH2_vect_num 41 +-#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ +-#define ADCB_CH3_vect_num 42 +-#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ +- +-/* PORTE interrupt vectors */ +-#define PORTE_INT0_vect_num 43 +-#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +-#define PORTE_INT1_vect_num 44 +-#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ +- +-/* TWIE interrupt vectors */ +-#define TWIE_TWIS_vect_num 45 +-#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +-#define TWIE_TWIM_vect_num 46 +-#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ +- +-/* TCE0 interrupt vectors */ +-#define TCE0_OVF_vect_num 47 +-#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +-#define TCE0_ERR_vect_num 48 +-#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +-#define TCE0_CCA_vect_num 49 +-#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +-#define TCE0_CCB_vect_num 50 +-#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +-#define TCE0_CCC_vect_num 51 +-#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +-#define TCE0_CCD_vect_num 52 +-#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ +- +-/* TCE1 interrupt vectors */ +-#define TCE1_OVF_vect_num 53 +-#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ +-#define TCE1_ERR_vect_num 54 +-#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ +-#define TCE1_CCA_vect_num 55 +-#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ +-#define TCE1_CCB_vect_num 56 +-#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ +- +-/* USARTE0 interrupt vectors */ +-#define USARTE0_RXC_vect_num 58 +-#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +-#define USARTE0_DRE_vect_num 59 +-#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +-#define USARTE0_TXC_vect_num 60 +-#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ +- +-/* PORTD interrupt vectors */ +-#define PORTD_INT0_vect_num 64 +-#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +-#define PORTD_INT1_vect_num 65 +-#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ +- +-/* PORTA interrupt vectors */ +-#define PORTA_INT0_vect_num 66 +-#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +-#define PORTA_INT1_vect_num 67 +-#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ +- +-/* ACA interrupt vectors */ +-#define ACA_AC0_vect_num 68 +-#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +-#define ACA_AC1_vect_num 69 +-#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +-#define ACA_ACW_vect_num 70 +-#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ +- +-/* ADCA interrupt vectors */ +-#define ADCA_CH0_vect_num 71 +-#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +-#define ADCA_CH1_vect_num 72 +-#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +-#define ADCA_CH2_vect_num 73 +-#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +-#define ADCA_CH3_vect_num 74 +-#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ +- +-/* TCD0 interrupt vectors */ +-#define TCD0_OVF_vect_num 77 +-#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +-#define TCD0_ERR_vect_num 78 +-#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +-#define TCD0_CCA_vect_num 79 +-#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +-#define TCD0_CCB_vect_num 80 +-#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +-#define TCD0_CCC_vect_num 81 +-#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +-#define TCD0_CCD_vect_num 82 +-#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ +- +-/* TCD1 interrupt vectors */ +-#define TCD1_OVF_vect_num 83 +-#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +-#define TCD1_ERR_vect_num 84 +-#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +-#define TCD1_CCA_vect_num 85 +-#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +-#define TCD1_CCB_vect_num 86 +-#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ +- +-/* SPID interrupt vectors */ +-#define SPID_INT_vect_num 87 +-#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ +- +-/* USARTD0 interrupt vectors */ +-#define USARTD0_RXC_vect_num 88 +-#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +-#define USARTD0_DRE_vect_num 89 +-#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +-#define USARTD0_TXC_vect_num 90 +-#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ +- +-/* USARTD1 interrupt vectors */ +-#define USARTD1_RXC_vect_num 91 +-#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +-#define USARTD1_DRE_vect_num 92 +-#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +-#define USARTD1_TXC_vect_num 93 +-#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ +- +-/* PORTF interrupt vectors */ +-#define PORTF_INT0_vect_num 104 +-#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +-#define PORTF_INT1_vect_num 105 +-#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ +- +-/* TCF0 interrupt vectors */ +-#define TCF0_OVF_vect_num 108 +-#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ +-#define TCF0_ERR_vect_num 109 +-#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ +-#define TCF0_CCA_vect_num 110 +-#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ +-#define TCF0_CCB_vect_num 111 +-#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ +-#define TCF0_CCC_vect_num 112 +-#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ +-#define TCF0_CCD_vect_num 113 +-#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ +- +-/* USARTF0 interrupt vectors */ +-#define USARTF0_RXC_vect_num 119 +-#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ +-#define USARTF0_DRE_vect_num 120 +-#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ +-#define USARTF0_TXC_vect_num 121 +-#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ +- +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (122 * _VECTOR_SIZE) +- +- +-/* ========== Constants ========== */ +- +-#define PROGMEM_START (0x0000) +-#define PROGMEM_SIZE (270336) +-#define PROGMEM_PAGE_SIZE (512) +-#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) +- +-#define APP_SECTION_START (0x0000) +-#define APP_SECTION_SIZE (262144) +-#define APP_SECTION_PAGE_SIZE (512) +-#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) +- +-#define APPTABLE_SECTION_START (0x3E000) +-#define APPTABLE_SECTION_SIZE (8192) +-#define APPTABLE_SECTION_PAGE_SIZE (512) +-#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) +- +-#define BOOT_SECTION_START (0x40000) +-#define BOOT_SECTION_SIZE (8192) +-#define BOOT_SECTION_PAGE_SIZE (512) +-#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) +- +-#define DATAMEM_START (0x0000) +-#define DATAMEM_SIZE (24576) +-#define DATAMEM_PAGE_SIZE (0) +-#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) +- +-#define IO_START (0x0000) +-#define IO_SIZE (4096) +-#define IO_PAGE_SIZE (0) +-#define IO_END (IO_START + IO_SIZE - 1) +- +-#define MAPPED_EEPROM_START (0x1000) +-#define MAPPED_EEPROM_SIZE (4096) +-#define MAPPED_EEPROM_PAGE_SIZE (0) +-#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) +- +-#define INTERNAL_SRAM_START (0x2000) +-#define INTERNAL_SRAM_SIZE (16384) +-#define INTERNAL_SRAM_PAGE_SIZE (0) +-#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) +- +-#define EEPROM_START (0x0000) +-#define EEPROM_SIZE (4096) +-#define EEPROM_PAGE_SIZE (32) +-#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) +- +-#define FUSE_START (0x0000) +-#define FUSE_SIZE (6) +-#define FUSE_PAGE_SIZE (0) +-#define FUSE_END (FUSE_START + FUSE_SIZE - 1) +- +-#define LOCKBIT_START (0x0000) +-#define LOCKBIT_SIZE (1) +-#define LOCKBIT_PAGE_SIZE (0) +-#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) +- +-#define SIGNATURES_START (0x0000) +-#define SIGNATURES_SIZE (3) +-#define SIGNATURES_PAGE_SIZE (0) +-#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) +- +-#define USER_SIGNATURES_START (0x0000) +-#define USER_SIGNATURES_SIZE (512) +-#define USER_SIGNATURES_PAGE_SIZE (0) +-#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) +- +-#define PROD_SIGNATURES_START (0x0000) +-#define PROD_SIGNATURES_SIZE (52) +-#define PROD_SIGNATURES_PAGE_SIZE (0) +-#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) +- +-#define FLASHEND PROGMEM_END +-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +-#define RAMSTART INTERNAL_SRAM_START +-#define RAMSIZE INTERNAL_SRAM_SIZE +-#define RAMEND INTERNAL_SRAM_END +-#define XRAMSTART EXTERNAL_SRAM_START +-#define XRAMSIZE EXTERNAL_SRAM_SIZE +-#define XRAMEND INTERNAL_SRAM_END +-#define E2END EEPROM_END +-#define E2PAGESIZE EEPROM_PAGE_SIZE +- +- +-/* ========== Fuses ========== */ +-#define FUSE_MEMORY_SIZE 6 +- +-/* Fuse Byte 0 */ +-#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ +-#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ +-#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ +-#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ +-#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ +-#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ +-#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ +-#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ +-#define FUSE0_DEFAULT (0xFF) +- +-/* Fuse Byte 1 */ +-#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +-#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +-#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +-#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +-#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +-#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +-#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +-#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +-#define FUSE1_DEFAULT (0xFF) +- +-/* Fuse Byte 2 */ +-#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +-#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +-#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +-#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +-#define FUSE2_DEFAULT (0xFF) +- +-/* Fuse Byte 3 Reserved */ +- +-/* Fuse Byte 4 */ +-#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ +-#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +-#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +-#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +-#define FUSE4_DEFAULT (0xFF) +- +-/* Fuse Byte 5 */ +-#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +-#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +-#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +-#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +-#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +-#define FUSE5_DEFAULT (0xFF) +- +- +-/* ========== Lock Bits ========== */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_BITS_EXIST +-#define __BOOT_LOCK_BOOT_BITS_EXIST +- +- +-/* ========== Signature ========== */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x98 +-#define SIGNATURE_2 0x43 +- +- +-#endif /* _AVR_ATxmega256A3B_H_ */ +- ++/* Copyright (c) 2009-2010 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iox256a3b.h 2200 2010-12-14 04:24:24Z arcanum $ */ ++ ++/* avr/iox256a3b.h - definitions for ATxmega256A3B */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox256a3b.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATxmega256A3B_H_ ++#define _AVR_ATxmega256A3B_H_ 1 ++ ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++/* Deprecated*/ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++} CLK_t; ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t PRPB; /* Power Reduction Port B */ ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ ++} CLK_RTCSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control REgister */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t reserved_0x07; ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Channel */ ++typedef struct DMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Address Control */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ ++ register8_t REPCNT; /* Channel Repeat Count */ ++ register8_t reserved_0x07; ++ register8_t SRCADDR0; /* Channel Source Address 0 */ ++ register8_t SRCADDR1; /* Channel Source Address 1 */ ++ register8_t SRCADDR2; /* Channel Source Address 2 */ ++ register8_t reserved_0x0B; ++ register8_t DESTADDR0; /* Channel Destination Address 0 */ ++ register8_t DESTADDR1; /* Channel Destination Address 1 */ ++ register8_t DESTADDR2; /* Channel Destination Address 2 */ ++ register8_t reserved_0x0F; ++} DMA_CH_t; ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Controller */ ++typedef struct DMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ DMA_CH_t CH0; /* DMA Channel 0 */ ++ DMA_CH_t CH1; /* DMA Channel 1 */ ++ DMA_CH_t CH2; /* DMA Channel 2 */ ++ DMA_CH_t CH3; /* DMA Channel 3 */ ++} DMA_t; ++ ++/* Burst mode */ ++typedef enum DMA_CH_BURSTLEN_enum ++{ ++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ ++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ ++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ ++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ ++} DMA_CH_BURSTLEN_t; ++ ++/* Source address reload mode */ ++typedef enum DMA_CH_SRCRELOAD_enum ++{ ++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ ++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ ++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ ++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ ++} DMA_CH_SRCRELOAD_t; ++ ++/* Source addressing mode */ ++typedef enum DMA_CH_SRCDIR_enum ++{ ++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ ++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ ++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ ++} DMA_CH_SRCDIR_t; ++ ++/* Destination adress reload mode */ ++typedef enum DMA_CH_DESTRELOAD_enum ++{ ++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ ++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ ++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ ++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ ++} DMA_CH_DESTRELOAD_t; ++ ++/* Destination adressing mode */ ++typedef enum DMA_CH_DESTDIR_enum ++{ ++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ ++} DMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum DMA_CH_TRIGSRC_enum ++{ ++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ ++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ ++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ ++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ ++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ ++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ ++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ ++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ ++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ ++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ ++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ ++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ ++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ ++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ ++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ ++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ ++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ ++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ ++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ ++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ ++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ ++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ ++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ ++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ ++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ ++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ ++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ ++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ ++} DMA_CH_TRIGSRC_t; ++ ++/* Double buffering mode */ ++typedef enum DMA_DBUFMODE_enum ++{ ++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ ++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ ++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ ++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ ++} DMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum DMA_PRIMODE_enum ++{ ++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ ++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ ++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ ++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ ++} DMA_PRIMODE_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_ERRINTLVL_enum ++{ ++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ ++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ ++} DMA_CH_ERRINTLVL_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_TRNINTLVL_enum ++{ ++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ ++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ ++} DMA_CH_TRNINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ ++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ ++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ ++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t CH4CTRL; /* Channel 4 Control Register */ ++ register8_t CH5CTRL; /* Channel 5 Control Register */ ++ register8_t CH6CTRL; /* Channel 6 Control Register */ ++ register8_t CH7CTRL; /* Channel 7 Control Register */ ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ ++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ ++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ ++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ ++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ ++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ ++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ ++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ ++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ ++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ ++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ ++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ ++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ ++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ ++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ ++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ ++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ ++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t FUSEBYTE0; /* JTAG User ID */ ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ ++ register8_t reserved_0x01; ++ register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ ++ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ ++ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ ++ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++} NVM_PROD_SIGNATURES_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++} NVM_LB_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brown Out Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ ++ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Comparator 0 Control */ ++ register8_t AC1CTRL; /* Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t reserved_0x6; ++ register8_t reserved_0x7; ++} ADC_CH_t; ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ _WORDREGISTER(CH1RES); /* Channel 1 Result */ ++ _WORDREGISTER(CH2RES); /* Channel 2 Result */ ++ _WORDREGISTER(CH3RES); /* Channel 3 Result */ ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++ ADC_CH_t CH1; /* ADC Channel 1 */ ++ ADC_CH_t CH2; /* ADC Channel 2 */ ++ ADC_CH_t CH3; /* ADC Channel 3 */ ++} ADC_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++} ADC_REFSEL_t; ++ ++/* Channel sweep selection */ ++typedef enum ADC_SWEEP_enum ++{ ++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ ++} ADC_SWEEP_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ++ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* DMA request selection */ ++typedef enum ADC_DMASEL_enum ++{ ++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ ++} ADC_DMASEL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DAC - Digital/Analog Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Digital-to-Analog Converter */ ++typedef struct DAC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t EVCTRL; /* Event Input Control */ ++ register8_t TIMCTRL; /* Timing Control */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t GAINCAL; /* Gain Calibration */ ++ register8_t OFFSETCAL; /* Offset Calibration */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ ++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ ++} DAC_t; ++ ++/* Output channel selection */ ++typedef enum DAC_CHSEL_enum ++{ ++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ ++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ ++} DAC_CHSEL_t; ++ ++/* Reference voltage selection */ ++typedef enum DAC_REFSEL_enum ++{ ++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ ++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ ++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ ++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ ++} DAC_REFSEL_t; ++ ++/* Event channel selection */ ++typedef enum DAC_EVSEL_enum ++{ ++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ ++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ ++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ ++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ ++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ ++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ ++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ ++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ ++} DAC_EVSEL_t; ++ ++/* Conversion interval */ ++typedef enum DAC_CONINTVAL_enum ++{ ++ DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ ++ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ ++ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ ++ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ ++ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ ++ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ ++ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ ++ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ ++} DAC_CONINTVAL_t; ++ ++/* Refresh rate */ ++typedef enum DAC_REFRESH_enum ++{ ++ DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ ++ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ ++ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ ++ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ ++ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ ++ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ ++ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ ++ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ ++ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ ++ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ ++ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ ++ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ ++ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ ++ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ ++} DAC_REFRESH_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC32 - 32-bit Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* 32-bit Real-Time Clounter */ ++typedef struct RTC32_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t SYNCCTRL; /* Synchronization Control/Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _DWORDREGISTER(CNT); /* Count Register */ ++ _DWORDREGISTER(PER); /* Period Register */ ++ _DWORDREGISTER(COMP); /* Compare Register */ ++} RTC32_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC32_COMPINTLVL_enum ++{ ++ RTC32_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC32_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC32_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC32_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC32_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC32_OVFINTLVL_enum ++{ ++ RTC32_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC32_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC32_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC32_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC32_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* EBI Chip Select Module */ ++typedef struct EBI_CS_struct ++{ ++ register8_t CTRLA; /* Chip Select Control Register A */ ++ register8_t CTRLB; /* Chip Select Control Register B */ ++ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ ++} EBI_CS_t; ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* External Bus Interface */ ++typedef struct EBI_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ ++ register8_t reserved_0x02; ++ register8_t reserved_0x03; ++ _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ ++ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ ++ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ ++ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ EBI_CS_t CS0; /* Chip Select 0 */ ++ EBI_CS_t CS1; /* Chip Select 1 */ ++ EBI_CS_t CS2; /* Chip Select 2 */ ++ EBI_CS_t CS3; /* Chip Select 3 */ ++} EBI_t; ++ ++/* Chip Select adress space */ ++typedef enum EBI_CS_ASIZE_enum ++{ ++ EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ ++ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ ++ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ ++ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ ++ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ ++ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ ++ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ ++ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ ++ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ ++ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ ++ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ ++ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ ++ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ ++ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ ++ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ ++ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ ++ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ ++} EBI_CS_ASIZE_t; ++ ++/* */ ++typedef enum EBI_CS_SRWS_enum ++{ ++ EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_CS_SRWS_t; ++ ++/* Chip Select address mode */ ++typedef enum EBI_CS_MODE_enum ++{ ++ EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ ++ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ ++ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ ++ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ ++} EBI_CS_MODE_t; ++ ++/* Chip Select SDRAM mode */ ++typedef enum EBI_CS_SDMODE_enum ++{ ++ EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ ++ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ ++} EBI_CS_SDMODE_t; ++ ++/* */ ++typedef enum EBI_SDDATAW_enum ++{ ++ EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ ++ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ ++} EBI_SDDATAW_t; ++ ++/* */ ++typedef enum EBI_LPCMODE_enum ++{ ++ EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ ++ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ ++} EBI_LPCMODE_t; ++ ++/* */ ++typedef enum EBI_SRMODE_enum ++{ ++ EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ ++ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ ++ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ ++ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ ++} EBI_SRMODE_t; ++ ++/* */ ++typedef enum EBI_IFMODE_enum ++{ ++ EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ ++ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ ++ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ ++ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ ++} EBI_IFMODE_t; ++ ++/* */ ++typedef enum EBI_SDCOL_enum ++{ ++ EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ ++ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ ++ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ ++ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ ++} EBI_SDCOL_t; ++ ++/* */ ++typedef enum EBI_MRDLY_enum ++{ ++ EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_MRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCYCDLY_enum ++{ ++ EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ROWCYCDLY_t; ++ ++/* */ ++typedef enum EBI_RPDLY_enum ++{ ++ EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_RPDLY_t; ++ ++/* */ ++typedef enum EBI_WRDLY_enum ++{ ++ EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_WRDLY_t; ++ ++/* */ ++typedef enum EBI_ESRDLY_enum ++{ ++ EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ESRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCOLDLY_enum ++{ ++ EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_ROWCOLDLY_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++} PORTCFG_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Virtual Port 0 Mapping */ ++typedef enum PORTCFG_VP0MAP_enum ++{ ++ PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP0MAP_t; ++ ++/* Virtual Port 1 Mapping */ ++typedef enum PORTCFG_VP1MAP_enum ++{ ++ PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP1MAP_t; ++ ++/* Virtual Port 2 Mapping */ ++typedef enum PORTCFG_VP2MAP_enum ++{ ++ PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP2MAP_t; ++ ++/* Virtual Port 3 Mapping */ ++typedef enum PORTCFG_VP3MAP_enum ++{ ++ PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP3MAP_t; ++ ++/* Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x05; ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AES - AES Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* AES Module */ ++typedef struct AES_struct ++{ ++ register8_t CTRL; /* AES Control Register */ ++ register8_t STATUS; /* AES Status Register */ ++ register8_t STATE; /* AES State Register */ ++ register8_t KEY; /* AES Key Register */ ++ register8_t INTCTRL; /* AES Interrupt Control Register */ ++} AES_t; ++ ++/* Interrupt level */ ++typedef enum AES_INTLVL_enum ++{ ++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} AES_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++VBAT - VBAT Battery Backup Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* VBAT Battery Backup Module */ ++typedef struct VBAT_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BACKUP0; /* Battery Bacup Register 0 */ ++ register8_t BACKUP1; /* Battery Backup Register 1 */ ++} VBAT_t; ++ ++ ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset Controller */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ ++#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ ++#define VBAT (*(VBAT_t *) 0x00F0) /* VBAT Battery Backup Module */ ++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ ++#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ ++#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ ++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ ++#define RTC32 (*(RTC32_t *) 0x0420) /* 32-bit Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ ++#define PORTA (*(PORT_t *) 0x0600) /* Port A */ ++#define PORTB (*(PORT_t *) 0x0620) /* Port B */ ++#define PORTC (*(PORT_t *) 0x0640) /* Port C */ ++#define PORTD (*(PORT_t *) 0x0660) /* Port D */ ++#define PORTE (*(PORT_t *) 0x0680) /* Port E */ ++#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ ++#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ ++#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ ++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ ++#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ ++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ ++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ ++#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ ++#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ ++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ ++#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ ++#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ ++#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ ++#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++#define GPIO_GPIOR4 _SFR_MEM8(0x0004) ++#define GPIO_GPIOR5 _SFR_MEM8(0x0005) ++#define GPIO_GPIOR6 _SFR_MEM8(0x0006) ++#define GPIO_GPIOR7 _SFR_MEM8(0x0007) ++#define GPIO_GPIOR8 _SFR_MEM8(0x0008) ++#define GPIO_GPIOR9 _SFR_MEM8(0x0009) ++#define GPIO_GPIORA _SFR_MEM8(0x000A) ++#define GPIO_GPIORB _SFR_MEM8(0x000B) ++#define GPIO_GPIORC _SFR_MEM8(0x000C) ++#define GPIO_GPIORD _SFR_MEM8(0x000D) ++#define GPIO_GPIORE _SFR_MEM8(0x000E) ++#define GPIO_GPIORF _SFR_MEM8(0x000F) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++#define GPIO_GPIO4 _SFR_MEM8(0x0004) ++#define GPIO_GPIO5 _SFR_MEM8(0x0005) ++#define GPIO_GPIO6 _SFR_MEM8(0x0006) ++#define GPIO_GPIO7 _SFR_MEM8(0x0007) ++#define GPIO_GPIO8 _SFR_MEM8(0x0008) ++#define GPIO_GPIO9 _SFR_MEM8(0x0009) ++#define GPIO_GPIOA _SFR_MEM8(0x000A) ++#define GPIO_GPIOB _SFR_MEM8(0x000B) ++#define GPIO_GPIOC _SFR_MEM8(0x000C) ++#define GPIO_GPIOD _SFR_MEM8(0x000D) ++#define GPIO_GPIOE _SFR_MEM8(0x000E) ++#define GPIO_GPIOF _SFR_MEM8(0x000F) ++ ++ ++/* VPORT0 - Virtual Port 0 */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT1 - Virtual Port 1 */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT2 - Virtual Port 2 */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT3 - Virtual Port 3 */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU Registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator Control */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPB _SFR_MEM8(0x0072) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset Controller */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - Port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++ ++/* AES - AES Crypto Module */ ++#define AES_CTRL _SFR_MEM8(0x00C0) ++#define AES_STATUS _SFR_MEM8(0x00C1) ++#define AES_STATE _SFR_MEM8(0x00C2) ++#define AES_KEY _SFR_MEM8(0x00C3) ++#define AES_INTCTRL _SFR_MEM8(0x00C4) ++ ++/* VBAT - VBAT Battery Backup Module */ ++#define VBAT_CTRL _SFR_MEM8(0x00F0) ++#define VBAT_STATUS _SFR_MEM8(0x00F1) ++#define VBAT_BACKUP0 _SFR_MEM8(0x00F2) ++#define VBAT_BACKUP1 _SFR_MEM8(0x00F3) ++ ++/* DMA - DMA Controller */ ++#define DMA_CTRL _SFR_MEM8(0x0100) ++#define DMA_INTFLAGS _SFR_MEM8(0x0103) ++#define DMA_STATUS _SFR_MEM8(0x0104) ++#define DMA_TEMP _SFR_MEM16(0x0106) ++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) ++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) ++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) ++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) ++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) ++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) ++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) ++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) ++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) ++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) ++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) ++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) ++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) ++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) ++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) ++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) ++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) ++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) ++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) ++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) ++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) ++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) ++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) ++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) ++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) ++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) ++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) ++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) ++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) ++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) ++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) ++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) ++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) ++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) ++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) ++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) ++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) ++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) ++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) ++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) ++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) ++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH4MUX _SFR_MEM8(0x0184) ++#define EVSYS_CH5MUX _SFR_MEM8(0x0185) ++#define EVSYS_CH6MUX _SFR_MEM8(0x0186) ++#define EVSYS_CH7MUX _SFR_MEM8(0x0187) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) ++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) ++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) ++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non Volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADCA - Analog to Digital Converter A */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CH1RES _SFR_MEM16(0x0212) ++#define ADCA_CH2RES _SFR_MEM16(0x0214) ++#define ADCA_CH3RES _SFR_MEM16(0x0216) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) ++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) ++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) ++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) ++#define ADCA_CH1_RES _SFR_MEM16(0x022C) ++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) ++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) ++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) ++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) ++#define ADCA_CH2_RES _SFR_MEM16(0x0234) ++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) ++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) ++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) ++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) ++#define ADCA_CH3_RES _SFR_MEM16(0x023C) ++ ++/* ADCB - Analog to Digital Converter B */ ++#define ADCB_CTRLA _SFR_MEM8(0x0240) ++#define ADCB_CTRLB _SFR_MEM8(0x0241) ++#define ADCB_REFCTRL _SFR_MEM8(0x0242) ++#define ADCB_EVCTRL _SFR_MEM8(0x0243) ++#define ADCB_PRESCALER _SFR_MEM8(0x0244) ++#define ADCB_INTFLAGS _SFR_MEM8(0x0246) ++#define ADCB_CAL _SFR_MEM16(0x024C) ++#define ADCB_CH0RES _SFR_MEM16(0x0250) ++#define ADCB_CH1RES _SFR_MEM16(0x0252) ++#define ADCB_CH2RES _SFR_MEM16(0x0254) ++#define ADCB_CH3RES _SFR_MEM16(0x0256) ++#define ADCB_CMP _SFR_MEM16(0x0258) ++#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) ++#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) ++#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) ++#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) ++#define ADCB_CH0_RES _SFR_MEM16(0x0264) ++#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) ++#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) ++#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) ++#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) ++#define ADCB_CH1_RES _SFR_MEM16(0x026C) ++#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) ++#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) ++#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) ++#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) ++#define ADCB_CH2_RES _SFR_MEM16(0x0274) ++#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) ++#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) ++#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) ++#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) ++#define ADCB_CH3_RES _SFR_MEM16(0x027C) ++ ++/* DACB - Digital to Analog Converter B */ ++#define DACB_CTRLA _SFR_MEM8(0x0320) ++#define DACB_CTRLB _SFR_MEM8(0x0321) ++#define DACB_CTRLC _SFR_MEM8(0x0322) ++#define DACB_EVCTRL _SFR_MEM8(0x0323) ++#define DACB_TIMCTRL _SFR_MEM8(0x0324) ++#define DACB_STATUS _SFR_MEM8(0x0325) ++#define DACB_GAINCAL _SFR_MEM8(0x0328) ++#define DACB_OFFSETCAL _SFR_MEM8(0x0329) ++#define DACB_CH0DATA _SFR_MEM16(0x0338) ++#define DACB_CH1DATA _SFR_MEM16(0x033A) ++ ++/* ACA - Analog Comparator A */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* ACB - Analog Comparator B */ ++#define ACB_AC0CTRL _SFR_MEM8(0x0390) ++#define ACB_AC1CTRL _SFR_MEM8(0x0391) ++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) ++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) ++#define ACB_CTRLA _SFR_MEM8(0x0394) ++#define ACB_CTRLB _SFR_MEM8(0x0395) ++#define ACB_WINCTRL _SFR_MEM8(0x0396) ++#define ACB_STATUS _SFR_MEM8(0x0397) ++ ++/* RTC32 - 32-bit Real-Time Counter */ ++#define RTC32_CTRL _SFR_MEM8(0x0420) ++#define RTC32_SYNCCTRL _SFR_MEM8(0x0421) ++#define RTC32_INTCTRL _SFR_MEM8(0x0422) ++#define RTC32_INTFLAGS _SFR_MEM8(0x0423) ++ ++/* TWIC - Two-Wire Interface C */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWIE - Two-Wire Interface E */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* PORTA - Port A */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORTB - Port B */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORTC - Port C */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORTD - Port D */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORTE - Port E */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORTF - Port F */ ++#define PORTF_DIR _SFR_MEM8(0x06A0) ++#define PORTF_DIRSET _SFR_MEM8(0x06A1) ++#define PORTF_DIRCLR _SFR_MEM8(0x06A2) ++#define PORTF_DIRTGL _SFR_MEM8(0x06A3) ++#define PORTF_OUT _SFR_MEM8(0x06A4) ++#define PORTF_OUTSET _SFR_MEM8(0x06A5) ++#define PORTF_OUTCLR _SFR_MEM8(0x06A6) ++#define PORTF_OUTTGL _SFR_MEM8(0x06A7) ++#define PORTF_IN _SFR_MEM8(0x06A8) ++#define PORTF_INTCTRL _SFR_MEM8(0x06A9) ++#define PORTF_INT0MASK _SFR_MEM8(0x06AA) ++#define PORTF_INT1MASK _SFR_MEM8(0x06AB) ++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) ++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) ++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) ++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) ++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) ++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) ++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) ++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) ++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) ++ ++/* PORTR - Port R */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TCC0 - Timer/Counter C0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TCC1 - Timer/Counter C1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEXC - Advanced Waveform Extension C */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRESC - High-Resolution Extension C */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ ++#define USARTC1_DATA _SFR_MEM8(0x08B0) ++#define USARTC1_STATUS _SFR_MEM8(0x08B1) ++#define USARTC1_CTRLA _SFR_MEM8(0x08B3) ++#define USARTC1_CTRLB _SFR_MEM8(0x08B4) ++#define USARTC1_CTRLC _SFR_MEM8(0x08B5) ++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) ++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) ++ ++/* SPIC - Serial Peripheral Interface C */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TCD0 - Timer/Counter D0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TCD1 - Timer/Counter D1 */ ++#define TCD1_CTRLA _SFR_MEM8(0x0940) ++#define TCD1_CTRLB _SFR_MEM8(0x0941) ++#define TCD1_CTRLC _SFR_MEM8(0x0942) ++#define TCD1_CTRLD _SFR_MEM8(0x0943) ++#define TCD1_CTRLE _SFR_MEM8(0x0944) ++#define TCD1_INTCTRLA _SFR_MEM8(0x0946) ++#define TCD1_INTCTRLB _SFR_MEM8(0x0947) ++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) ++#define TCD1_CTRLFSET _SFR_MEM8(0x0949) ++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) ++#define TCD1_CTRLGSET _SFR_MEM8(0x094B) ++#define TCD1_INTFLAGS _SFR_MEM8(0x094C) ++#define TCD1_TEMP _SFR_MEM8(0x094F) ++#define TCD1_CNT _SFR_MEM16(0x0960) ++#define TCD1_PER _SFR_MEM16(0x0966) ++#define TCD1_CCA _SFR_MEM16(0x0968) ++#define TCD1_CCB _SFR_MEM16(0x096A) ++#define TCD1_PERBUF _SFR_MEM16(0x0976) ++#define TCD1_CCABUF _SFR_MEM16(0x0978) ++#define TCD1_CCBBUF _SFR_MEM16(0x097A) ++ ++/* HIRESD - High-Resolution Extension D */ ++#define HIRESD_CTRLA _SFR_MEM8(0x0990) ++ ++/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ ++#define USARTD1_DATA _SFR_MEM8(0x09B0) ++#define USARTD1_STATUS _SFR_MEM8(0x09B1) ++#define USARTD1_CTRLA _SFR_MEM8(0x09B3) ++#define USARTD1_CTRLB _SFR_MEM8(0x09B4) ++#define USARTD1_CTRLC _SFR_MEM8(0x09B5) ++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) ++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) ++ ++/* SPID - Serial Peripheral Interface D */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TCE0 - Timer/Counter E0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* TCE1 - Timer/Counter E1 */ ++#define TCE1_CTRLA _SFR_MEM8(0x0A40) ++#define TCE1_CTRLB _SFR_MEM8(0x0A41) ++#define TCE1_CTRLC _SFR_MEM8(0x0A42) ++#define TCE1_CTRLD _SFR_MEM8(0x0A43) ++#define TCE1_CTRLE _SFR_MEM8(0x0A44) ++#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) ++#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) ++#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) ++#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) ++#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) ++#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) ++#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) ++#define TCE1_TEMP _SFR_MEM8(0x0A4F) ++#define TCE1_CNT _SFR_MEM16(0x0A60) ++#define TCE1_PER _SFR_MEM16(0x0A66) ++#define TCE1_CCA _SFR_MEM16(0x0A68) ++#define TCE1_CCB _SFR_MEM16(0x0A6A) ++#define TCE1_PERBUF _SFR_MEM16(0x0A76) ++#define TCE1_CCABUF _SFR_MEM16(0x0A78) ++#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) ++ ++/* AWEXE - Advanced Waveform Extension E */ ++#define AWEXE_CTRL _SFR_MEM8(0x0A80) ++#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) ++#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) ++#define AWEXE_STATUS _SFR_MEM8(0x0A84) ++#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) ++#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) ++#define AWEXE_DTLS _SFR_MEM8(0x0A88) ++#define AWEXE_DTHS _SFR_MEM8(0x0A89) ++#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) ++#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) ++#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) ++ ++/* HIRESE - High-Resolution Extension E */ ++#define HIRESE_CTRLA _SFR_MEM8(0x0A90) ++ ++/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* TCF0 - Timer/Counter F0 */ ++#define TCF0_CTRLA _SFR_MEM8(0x0B00) ++#define TCF0_CTRLB _SFR_MEM8(0x0B01) ++#define TCF0_CTRLC _SFR_MEM8(0x0B02) ++#define TCF0_CTRLD _SFR_MEM8(0x0B03) ++#define TCF0_CTRLE _SFR_MEM8(0x0B04) ++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) ++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) ++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) ++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) ++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF0_TEMP _SFR_MEM8(0x0B0F) ++#define TCF0_CNT _SFR_MEM16(0x0B20) ++#define TCF0_PER _SFR_MEM16(0x0B26) ++#define TCF0_CCA _SFR_MEM16(0x0B28) ++#define TCF0_CCB _SFR_MEM16(0x0B2A) ++#define TCF0_CCC _SFR_MEM16(0x0B2C) ++#define TCF0_CCD _SFR_MEM16(0x0B2E) ++#define TCF0_PERBUF _SFR_MEM16(0x0B36) ++#define TCF0_CCABUF _SFR_MEM16(0x0B38) ++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) ++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) ++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) ++ ++/* HIRESF - High-Resolution Extension F */ ++#define HIRESF_CTRLA _SFR_MEM8(0x0B90) ++ ++/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ ++#define USARTF0_DATA _SFR_MEM8(0x0BA0) ++#define USARTF0_STATUS _SFR_MEM8(0x0BA1) ++#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) ++#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) ++#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) ++#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) ++#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) ++ ++/* SPIF - Serial Peripheral Interface F */ ++#define SPIF_CTRL _SFR_MEM8(0x0BC0) ++#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) ++#define SPIF_STATUS _SFR_MEM8(0x0BC2) ++#define SPIF_DATA _SFR_MEM8(0x0BC3) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR1 bit masks and bit positions */ ++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ ++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ ++ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ ++ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ ++#define PR_EBI_bp 3 /* External Bus Interface bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ ++#define PR_DAC_bp 2 /* Port A DAC bit position. */ ++ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++ ++/* PR.PRPB bit masks and bit positions */ ++/* PR_DAC_bm Predefined. */ ++/* PR_DAC_bp Predefined. */ ++ ++/* PR_ADC_bm Predefined. */ ++/* PR_ADC_bp Predefined. */ ++ ++/* PR_AC_bm Predefined. */ ++/* PR_AC_bp Predefined. */ ++ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ ++ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ ++ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ ++ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ ++#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ ++ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ ++ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ ++ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ ++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ ++ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++ ++/* DMA - DMA Controller */ ++/* DMA_CH.CTRLA bit masks and bit positions */ ++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ ++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ ++ ++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ ++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ ++ ++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ ++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ ++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ ++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ ++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ ++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ ++ ++ ++/* DMA_CH.CTRLB bit masks and bit positions */ ++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ ++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ ++ ++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ ++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ ++ ++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ ++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ ++ ++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ ++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ ++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ ++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ ++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ ++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ ++ ++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ ++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ ++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ ++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ ++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ ++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ ++ ++ ++/* DMA_CH.ADDRCTRL bit masks and bit positions */ ++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ ++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ ++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ ++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ ++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ ++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ ++ ++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ ++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ ++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ ++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ ++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ ++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ ++ ++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ ++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ ++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ ++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ ++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ ++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ ++ ++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ ++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ ++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ ++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ ++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ ++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ ++ ++ ++/* DMA_CH.TRIGSRC bit masks and bit positions */ ++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++ ++/* DMA.CTRL bit masks and bit positions */ ++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define DMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define DMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ ++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ ++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ ++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ ++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ ++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ ++ ++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ ++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ ++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ ++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ ++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ ++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ ++ ++ ++/* DMA.INTFLAGS bit masks and bit positions */ ++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++ ++/* DMA.STATUS bit masks and bit positions */ ++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ ++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ ++ ++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ ++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ ++ ++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ ++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ ++ ++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ ++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ ++ ++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ ++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ ++ ++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ ++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ ++ ++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ ++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ ++ ++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ ++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ ++ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH4MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH5MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH6MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH7MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM_gm Predefined. */ ++/* EVSYS_QDIRM_gp Predefined. */ ++/* EVSYS_QDIRM0_bm Predefined. */ ++/* EVSYS_QDIRM0_bp Predefined. */ ++/* EVSYS_QDIRM1_bm Predefined. */ ++/* EVSYS_QDIRM1_bp Predefined. */ ++ ++/* EVSYS_QDIEN_bm Predefined. */ ++/* EVSYS_QDIEN_bp Predefined. */ ++ ++/* EVSYS_QDEN_bm Predefined. */ ++/* EVSYS_QDEN_bp Predefined. */ ++ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH4CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM_gm Predefined. */ ++/* EVSYS_QDIRM_gp Predefined. */ ++/* EVSYS_QDIRM0_bm Predefined. */ ++/* EVSYS_QDIRM0_bp Predefined. */ ++/* EVSYS_QDIRM1_bm Predefined. */ ++/* EVSYS_QDIRM1_bp Predefined. */ ++ ++/* EVSYS_QDIEN_bm Predefined. */ ++/* EVSYS_QDIEN_bp Predefined. */ ++ ++/* EVSYS_QDEN_bm Predefined. */ ++/* EVSYS_QDEN_bp Predefined. */ ++ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH5CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH6CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH7CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0xFF /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ ++#define NVM_CMD7_bp 7 /* Command bit 7 position. */ ++ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ ++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ ++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ ++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ ++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ ++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ ++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ ++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ ++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ ++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ ++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ ++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ ++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ ++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ ++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ ++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ ++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ ++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ ++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ ++#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ ++ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ ++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ ++ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ ++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE_gm Predefined. */ ++/* AC_INTMODE_gp Predefined. */ ++/* AC_INTMODE0_bm Predefined. */ ++/* AC_INTMODE0_bp Predefined. */ ++/* AC_INTMODE1_bm Predefined. */ ++/* AC_INTMODE1_bp Predefined. */ ++ ++/* AC_INTLVL_gm Predefined. */ ++/* AC_INTLVL_gp Predefined. */ ++/* AC_INTLVL0_bm Predefined. */ ++/* AC_INTLVL0_bp Predefined. */ ++/* AC_INTLVL1_bm Predefined. */ ++/* AC_INTLVL1_bp Predefined. */ ++ ++/* AC_HSMODE_bm Predefined. */ ++/* AC_HSMODE_bp Predefined. */ ++ ++/* AC_HYSMODE_gm Predefined. */ ++/* AC_HYSMODE_gp Predefined. */ ++/* AC_HYSMODE0_bm Predefined. */ ++/* AC_HYSMODE0_bp Predefined. */ ++/* AC_HYSMODE1_bm Predefined. */ ++/* AC_HYSMODE1_bp Predefined. */ ++ ++/* AC_ENABLE_bm Predefined. */ ++/* AC_ENABLE_bp Predefined. */ ++ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS_gm Predefined. */ ++/* AC_MUXPOS_gp Predefined. */ ++/* AC_MUXPOS0_bm Predefined. */ ++/* AC_MUXPOS0_bp Predefined. */ ++/* AC_MUXPOS1_bm Predefined. */ ++/* AC_MUXPOS1_bp Predefined. */ ++/* AC_MUXPOS2_bm Predefined. */ ++/* AC_MUXPOS2_bp Predefined. */ ++ ++/* AC_MUXNEG_gm Predefined. */ ++/* AC_MUXNEG_gp Predefined. */ ++/* AC_MUXNEG0_bm Predefined. */ ++/* AC_MUXNEG0_bp Predefined. */ ++/* AC_MUXNEG1_bm Predefined. */ ++/* AC_MUXNEG1_bp Predefined. */ ++/* AC_MUXNEG2_bm Predefined. */ ++/* AC_MUXNEG2_bp Predefined. */ ++ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ ++ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ ++ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ ++ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ ++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ ++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ ++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ ++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ ++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ ++ ++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ ++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ ++ ++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ ++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ ++ ++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ ++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ ++ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ ++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ ++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ ++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ ++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ ++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ ++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ ++ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ ++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ ++ ++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ ++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ ++ ++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ ++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ ++ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++ ++/* DAC - Digital/Analog Converter */ ++/* DAC.CTRLA bit masks and bit positions */ ++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ ++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ ++ ++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ ++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ ++ ++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ ++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ ++ ++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ ++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ ++ ++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define DAC_ENABLE_bp 0 /* Enable bit position. */ ++ ++ ++/* DAC.CTRLB bit masks and bit positions */ ++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ ++#define DAC_CHSEL_gp 5 /* Channel Select group position. */ ++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ ++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ ++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ ++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ ++ ++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ ++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ ++ ++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ ++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ ++ ++ ++/* DAC.CTRLC bit masks and bit positions */ ++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ ++#define DAC_REFSEL_gp 3 /* Reference Select group position. */ ++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ ++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ ++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ ++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ ++ ++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ ++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ ++ ++ ++/* DAC.EVCTRL bit masks and bit positions */ ++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ ++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ ++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ ++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ ++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ ++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ ++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ ++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ ++ ++ ++/* DAC.TIMCTRL bit masks and bit positions */ ++#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ ++#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ ++#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ ++#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ ++#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ ++#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ ++#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ ++#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ ++ ++#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ ++#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ ++#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ ++#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ ++#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ ++#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ ++#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ ++#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ ++#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ ++#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ ++ ++ ++/* DAC.STATUS bit masks and bit positions */ ++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ ++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ ++ ++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ ++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ ++ ++ ++/* RTC32 - 32-bit Real-Time Counter */ ++/* RTC32.CTRL bit masks and bit positions */ ++#define RTC32_ENABLE_bm 0x01 /* RTC enable bit mask. */ ++#define RTC32_ENABLE_bp 0 /* RTC enable bit position. */ ++ ++ ++/* RTC32.SYNCCTRL bit masks and bit positions */ ++#define RTC32_SYNCCNT_bm 0x10 /* Synchronization Busy Flag bit mask. */ ++#define RTC32_SYNCCNT_bp 4 /* Synchronization Busy Flag bit position. */ ++ ++#define RTC32_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC32_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++ ++/* RTC32.INTCTRL bit masks and bit positions */ ++#define RTC32_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC32_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC32_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC32_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC32_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC32_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC32_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC32_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC32_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC32_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC32_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC32_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++ ++/* RTC32.INTFLAGS bit masks and bit positions */ ++#define RTC32_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC32_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC32_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC32_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* EBI - External Bus Interface */ ++/* EBI_CS.CTRLA bit masks and bit positions */ ++#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ ++#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ ++#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ ++#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ ++#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ ++#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ ++#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ ++#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ ++#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ ++#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ ++#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ ++#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ ++ ++#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ ++#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ ++#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ ++#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ ++#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ ++#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ ++ ++ ++/* EBI_CS.CTRLB bit masks and bit positions */ ++#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ ++#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ ++#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ ++#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ ++#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ ++#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ ++#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ ++#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ ++ ++#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ ++#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ ++ ++#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ ++#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ ++ ++#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ ++#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ ++#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ ++#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ ++#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ ++#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ ++ ++ ++/* EBI.CTRL bit masks and bit positions */ ++#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ ++#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ ++#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ ++#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ ++#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ ++#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ ++ ++#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ ++#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ ++#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ ++#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ ++#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ ++#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ ++ ++#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ ++#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ ++#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ ++#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ ++#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ ++#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ ++ ++#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ ++#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ ++#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ ++#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ ++#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ ++#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLA bit masks and bit positions */ ++#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ ++#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ ++ ++#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ ++#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ ++ ++#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ ++#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ ++#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ ++#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ ++#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ ++#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLB bit masks and bit positions */ ++#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ ++#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ ++#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ ++#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ ++#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ ++#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ ++ ++#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ ++#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ ++#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ ++#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ ++#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ ++#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ ++#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ ++#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ ++ ++#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ ++#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ ++#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ ++#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ ++#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ ++#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ ++#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ ++#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ ++ ++ ++/* EBI.SDRAMCTRLC bit masks and bit positions */ ++#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ ++#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ ++#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ ++#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ ++#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ ++#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ ++ ++#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ ++#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ ++#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ ++#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ ++#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ ++#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ ++#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ ++#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ ++ ++#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ ++#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ ++#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ ++#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ ++#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ ++#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ ++#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ ++#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ ++ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ ++#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++ ++/* PORT - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ ++#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ ++ ++#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD_gm Predefined. */ ++/* TC0_CMD_gp Predefined. */ ++/* TC0_CMD0_bm Predefined. */ ++/* TC0_CMD0_bp Predefined. */ ++/* TC0_CMD1_bm Predefined. */ ++/* TC0_CMD1_bp Predefined. */ ++ ++/* TC0_LUPD_bm Predefined. */ ++/* TC0_LUPD_bp Predefined. */ ++ ++/* TC0_DIR_bm Predefined. */ ++/* TC0_DIR_bp Predefined. */ ++ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV_bm Predefined. */ ++/* TC0_CCDBV_bp Predefined. */ ++ ++/* TC0_CCCBV_bm Predefined. */ ++/* TC0_CCCBV_bp Predefined. */ ++ ++/* TC0_CCBBV_bm Predefined. */ ++/* TC0_CCBBV_bp Predefined. */ ++ ++/* TC0_CCABV_bm Predefined. */ ++/* TC0_CCABV_bp Predefined. */ ++ ++/* TC0_PERBV_bm Predefined. */ ++/* TC0_PERBV_bp Predefined. */ ++ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ ++#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ ++ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD_gm Predefined. */ ++/* TC1_CMD_gp Predefined. */ ++/* TC1_CMD0_bm Predefined. */ ++/* TC1_CMD0_bp Predefined. */ ++/* TC1_CMD1_bm Predefined. */ ++/* TC1_CMD1_bp Predefined. */ ++ ++/* TC1_LUPD_bm Predefined. */ ++/* TC1_LUPD_bp Predefined. */ ++ ++/* TC1_DIR_bm Predefined. */ ++/* TC1_DIR_bp Predefined. */ ++ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV_bm Predefined. */ ++/* TC1_CCBBV_bp Predefined. */ ++ ++/* TC1_CCABV_bm Predefined. */ ++/* TC1_CCABV_bp Predefined. */ ++ ++/* TC1_PERBV_bm Predefined. */ ++/* TC1_PERBV_bp Predefined. */ ++ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++ ++/* HIRES.CTRL bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL_gm Predefined. */ ++/* USART_BSEL_gp Predefined. */ ++/* USART_BSEL0_bm Predefined. */ ++/* USART_BSEL0_bp Predefined. */ ++/* USART_BSEL1_bm Predefined. */ ++/* USART_BSEL1_bp Predefined. */ ++/* USART_BSEL2_bm Predefined. */ ++/* USART_BSEL2_bp Predefined. */ ++/* USART_BSEL3_bm Predefined. */ ++/* USART_BSEL3_bp Predefined. */ ++ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++ ++/* AES - AES Module */ ++/* AES.CTRL bit masks and bit positions */ ++#define AES_START_bm 0x80 /* Start/Run bit mask. */ ++#define AES_START_bp 7 /* Start/Run bit position. */ ++ ++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ ++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ ++ ++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ ++#define AES_RESET_bp 5 /* AES Software Reset bit position. */ ++ ++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ ++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ ++ ++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ ++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ ++ ++ ++/* AES.STATUS bit masks and bit positions */ ++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ ++#define AES_ERROR_bp 7 /* AES Error bit position. */ ++ ++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ ++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ ++ ++ ++/* AES.INTCTRL bit masks and bit positions */ ++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define AES_INTLVL_gp 0 /* Interrupt level group position. */ ++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++ ++/* VBAT - VBAT Battery Backup Module */ ++/* VBAT.CTRL bit masks and bit positions */ ++#define VBAT_XOSCSEL_bm 0x10 /* 32-kHz Crystal Oscillator Output Selection bit mask. */ ++#define VBAT_XOSCSEL_bp 4 /* 32-kHz Crystal Oscillator Output Selection bit position. */ ++ ++#define VBAT_XOSCEN_bm 0x08 /* Crystal Oscillator Enable bit mask. */ ++#define VBAT_XOSCEN_bp 3 /* Crystal Oscillator Enable bit position. */ ++ ++#define VBAT_XOSCFDEN_bm 0x04 /* Crystal Oscillator Failure Detection Monitor Enable bit mask. */ ++#define VBAT_XOSCFDEN_bp 2 /* Crystal Oscillator Failure Detection Monitor Enable bit position. */ ++ ++#define VBAT_ACCEN_bm 0x02 /* Battery Backup Access Enable bit mask. */ ++#define VBAT_ACCEN_bp 1 /* Battery Backup Access Enable bit position. */ ++ ++#define VBAT_RESET_bm 0x01 /* Battery Backup Reset bit mask. */ ++#define VBAT_RESET_bp 0 /* Battery Backup Reset bit position. */ ++ ++ ++/* VBAT.STATUS bit masks and bit positions */ ++#define VBAT_BBPWR_bm 0x80 /* Battery backup Power bit mask. */ ++#define VBAT_BBPWR_bp 7 /* Battery backup Power bit position. */ ++ ++#define VBAT_XOSCRDY_bm 0x08 /* Crystal Oscillator Ready bit mask. */ ++#define VBAT_XOSCRDY_bp 3 /* Crystal Oscillator Ready bit position. */ ++ ++#define VBAT_XOSCFAIL_bm 0x04 /* Crystal Oscillator Failure bit mask. */ ++#define VBAT_XOSCFAIL_bp 2 /* Crystal Oscillator Failure bit position. */ ++ ++#define VBAT_BBBORF_bm 0x02 /* Battery Backup Brown-Out Reset Flag bit mask. */ ++#define VBAT_BBBORF_bp 1 /* Battery Backup Brown-Out Reset Flag bit position. */ ++ ++#define VBAT_BBPORF_bm 0x01 /* Battery Backup Power-On Reset Flag bit mask. */ ++#define VBAT_BBPORF_bp 0 /* Battery Backup Power-On Reset Flag bit position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_XOSCF_vect_num 1 ++#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* DMA interrupt vectors */ ++#define DMA_CH0_vect_num 6 ++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ ++#define DMA_CH1_vect_num 7 ++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ ++#define DMA_CH2_vect_num 8 ++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ ++#define DMA_CH3_vect_num 9 ++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ ++ ++/* RTC32 interrupt vectors */ ++#define RTC32_OVF_vect_num 10 ++#define RTC32_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC32_COMP_vect_num 11 ++#define RTC32_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* USARTC1 interrupt vectors */ ++#define USARTC1_RXC_vect_num 28 ++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ ++#define USARTC1_DRE_vect_num 29 ++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ ++#define USARTC1_TXC_vect_num 30 ++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ ++ ++/* AES interrupt vectors */ ++#define AES_INT_vect_num 31 ++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* ACB interrupt vectors */ ++#define ACB_AC0_vect_num 36 ++#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ ++#define ACB_AC1_vect_num 37 ++#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ ++#define ACB_ACW_vect_num 38 ++#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ ++ ++/* ADCB interrupt vectors */ ++#define ADCB_CH0_vect_num 39 ++#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ ++#define ADCB_CH1_vect_num 40 ++#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ ++#define ADCB_CH2_vect_num 41 ++#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ ++#define ADCB_CH3_vect_num 42 ++#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* TCE1 interrupt vectors */ ++#define TCE1_OVF_vect_num 53 ++#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ ++#define TCE1_ERR_vect_num 54 ++#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ ++#define TCE1_CCA_vect_num 55 ++#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ ++#define TCE1_CCB_vect_num 56 ++#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++#define ADCA_CH1_vect_num 72 ++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ ++#define ADCA_CH2_vect_num 73 ++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ ++#define ADCA_CH3_vect_num 74 ++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD1 interrupt vectors */ ++#define TCD1_OVF_vect_num 83 ++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ ++#define TCD1_ERR_vect_num 84 ++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ ++#define TCD1_CCA_vect_num 85 ++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ ++#define TCD1_CCB_vect_num 86 ++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* USARTD1 interrupt vectors */ ++#define USARTD1_RXC_vect_num 91 ++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ ++#define USARTD1_DRE_vect_num 92 ++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ ++#define USARTD1_TXC_vect_num 93 ++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ ++ ++/* PORTF interrupt vectors */ ++#define PORTF_INT0_vect_num 104 ++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ ++#define PORTF_INT1_vect_num 105 ++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_OVF_vect_num 108 ++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ ++#define TCF0_ERR_vect_num 109 ++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ ++#define TCF0_CCA_vect_num 110 ++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ ++#define TCF0_CCB_vect_num 111 ++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ ++#define TCF0_CCC_vect_num 112 ++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ ++#define TCF0_CCD_vect_num 113 ++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ ++ ++/* USARTF0 interrupt vectors */ ++#define USARTF0_RXC_vect_num 119 ++#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ ++#define USARTF0_DRE_vect_num 120 ++#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ ++#define USARTF0_TXC_vect_num 121 ++#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ ++ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (122 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (270336) ++#define PROGMEM_PAGE_SIZE (512) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (262144) ++#define APP_SECTION_PAGE_SIZE (512) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x3E000) ++#define APPTABLE_SECTION_SIZE (8192) ++#define APPTABLE_SECTION_PAGE_SIZE (512) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x40000) ++#define BOOT_SECTION_SIZE (8192) ++#define BOOT_SECTION_PAGE_SIZE (512) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (24576) ++#define DATAMEM_PAGE_SIZE (0) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (4096) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (16384) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (4096) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define FUSE_START (0x0000) ++#define FUSE_SIZE (6) ++#define FUSE_PAGE_SIZE (0) ++#define FUSE_END (FUSE_START + FUSE_SIZE - 1) ++ ++#define LOCKBIT_START (0x0000) ++#define LOCKBIT_SIZE (1) ++#define LOCKBIT_PAGE_SIZE (0) ++#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (512) ++#define USER_SIGNATURES_PAGE_SIZE (0) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (0) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE PROGMEM_PAGE_SIZE ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define XRAMSTART EXTERNAL_SRAM_START ++#define XRAMSIZE EXTERNAL_SRAM_SIZE ++#define XRAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 */ ++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ ++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ ++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ ++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ ++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ ++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ ++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ ++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ ++#define FUSE0_DEFAULT (0xFF) ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x98 ++#define SIGNATURE_2 0x43 ++ ++ ++#endif /* _AVR_ATxmega256A3B_H_ */ ++ diff --git a/include/avr/iox256a3bu.h b/include/avr/iox256a3bu.h new file mode 100644 -index 0000000..ab7ee61 +index 0000000..51c2424 --- /dev/null +++ b/include/avr/iox256a3bu.h @@ -0,0 +1,7637 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox256a3bu.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA256A3BU_H_INCLUDED -+#define _AVR_ATXMEGA256A3BU_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -+#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -+#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -+#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -+#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -+#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -+#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -+#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -+#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -+#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -+#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -+#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -+#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -+#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -+#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -+#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -+#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -+#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -+#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -+#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -+#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -+#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -+#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+VPORT - Virtual Ports -+-------------------------------------------------------------------------- -+*/ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t USBCTRL; /* USB Control Register */ -+} CLK_t; -+ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t PRPB; /* Power Reduction Port B */ -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t PRPD; /* Power Reduction Port D */ -+ register8_t PRPE; /* Power Reduction Port E */ -+ register8_t PRPF; /* Power Reduction Port F */ -+} PR_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+/* USB Prescaler Division Factor */ -+typedef enum CLK_USBPSDIV_enum -+{ -+ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ -+ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ -+ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ -+ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ -+ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ -+ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -+} CLK_USBPSDIV_t; -+ -+/* USB Clock Source */ -+typedef enum CLK_USBSRC_enum -+{ -+ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ -+ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -+} CLK_USBSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control Register */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+/* 2 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC2MCREF_enum -+{ -+ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC2MCREF_t; -+ -+/* 32 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC32MCREF_enum -+{ -+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -+} OSC_RC32MCREF_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t JTAGUID; /* JTAG User ID */ -+ register8_t reserved_0x05; -+ register8_t MCUCR; /* MCU Control */ -+ register8_t ANAINIT; /* Analog Startup Delay */ -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t AWEXLOCK; /* AWEX Lock */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORTCFG - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t VPCTRLA; /* Virtual Port Control Register A */ -+ register8_t VPCTRLB; /* Virtual Port Control Register B */ -+ register8_t CLKEVOUT; /* Clock and Event Out Register */ -+ register8_t EBIOUT; /* EBI Output register */ -+ register8_t EVOUTSEL; /* Event Output Select */ -+} PORTCFG_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP02MAP_enum -+{ -+ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ -+ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ -+ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ -+ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ -+ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ -+ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ -+ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ -+ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ -+ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ -+ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ -+ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ -+ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ -+ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ -+ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ -+ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ -+ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -+} PORTCFG_VP02MAP_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP13MAP_enum -+{ -+ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ -+ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ -+ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ -+ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ -+ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ -+ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ -+ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ -+ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ -+ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ -+ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ -+ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ -+ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ -+ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ -+ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ -+ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ -+ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -+} PORTCFG_VP13MAP_t; -+ -+/* System Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ -+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ -+ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -+} PORTCFG_CLKOUT_t; -+ -+/* Peripheral Clock Output Select */ -+typedef enum PORTCFG_CLKOUTSEL_enum -+{ -+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -+} PORTCFG_CLKOUTSEL_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ -+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ -+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -+} PORTCFG_EVOUT_t; -+ -+/* Clock and Event Output Port */ -+typedef enum PORTCFG_CLKEVPIN_enum -+{ -+ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ -+ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -+} PORTCFG_CLKEVPIN_t; -+ -+/* EBI Address Output Port */ -+typedef enum PORTCFG_EBIADROUT_enum -+{ -+ PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ -+ PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ -+ PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ -+ PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ -+} PORTCFG_EBIADROUT_t; -+ -+/* EBI Chip Select Output Port */ -+typedef enum PORTCFG_EBICSOUT_enum -+{ -+ PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ -+} PORTCFG_EBICSOUT_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -+ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ -+ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ -+ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ -+ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AES - AES Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* AES Module */ -+typedef struct AES_struct -+{ -+ register8_t CTRL; /* AES Control Register */ -+ register8_t STATUS; /* AES Status Register */ -+ register8_t STATE; /* AES State Register */ -+ register8_t KEY; /* AES Key Register */ -+ register8_t INTCTRL; /* AES Interrupt Control Register */ -+} AES_t; -+ -+/* Interrupt level */ -+typedef enum AES_INTLVL_enum -+{ -+ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} AES_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ -+ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ -+ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ -+ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+VBAT - Battery Backup Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* Battery Backup Module */ -+typedef struct VBAT_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BACKUP0; /* Backup Register 0 */ -+ register8_t BACKUP1; /* Backup Register 1 */ -+} VBAT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DMA - DMA Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* DMA Channel */ -+typedef struct DMA_CH_struct -+{ -+ register8_t CTRLA; /* Channel Control */ -+ register8_t CTRLB; /* Channel Control */ -+ register8_t ADDRCTRL; /* Address Control */ -+ register8_t TRIGSRC; /* Channel Trigger Source */ -+ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ -+ register8_t REPCNT; /* Channel Repeat Count */ -+ register8_t reserved_0x07; -+ register8_t SRCADDR0; /* Channel Source Address 0 */ -+ register8_t SRCADDR1; /* Channel Source Address 1 */ -+ register8_t SRCADDR2; /* Channel Source Address 2 */ -+ register8_t reserved_0x0B; -+ register8_t DESTADDR0; /* Channel Destination Address 0 */ -+ register8_t DESTADDR1; /* Channel Destination Address 1 */ -+ register8_t DESTADDR2; /* Channel Destination Address 2 */ -+ register8_t reserved_0x0F; -+} DMA_CH_t; -+ -+ -+/* DMA Controller */ -+typedef struct DMA_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t reserved_0x01; -+ register8_t reserved_0x02; -+ register8_t INTFLAGS; /* Transfer Interrupt Status */ -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x05; -+ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ DMA_CH_t CH0; /* DMA Channel 0 */ -+ DMA_CH_t CH1; /* DMA Channel 1 */ -+ DMA_CH_t CH2; /* DMA Channel 2 */ -+ DMA_CH_t CH3; /* DMA Channel 3 */ -+} DMA_t; -+ -+/* Burst mode */ -+typedef enum DMA_CH_BURSTLEN_enum -+{ -+ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ -+ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ -+ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ -+ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -+} DMA_CH_BURSTLEN_t; -+ -+/* Source address reload mode */ -+typedef enum DMA_CH_SRCRELOAD_enum -+{ -+ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ -+ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ -+ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ -+ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -+} DMA_CH_SRCRELOAD_t; -+ -+/* Source addressing mode */ -+typedef enum DMA_CH_SRCDIR_enum -+{ -+ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ -+ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ -+ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -+} DMA_CH_SRCDIR_t; -+ -+/* Destination adress reload mode */ -+typedef enum DMA_CH_DESTRELOAD_enum -+{ -+ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ -+ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ -+ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ -+ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -+} DMA_CH_DESTRELOAD_t; -+ -+/* Destination adressing mode */ -+typedef enum DMA_CH_DESTDIR_enum -+{ -+ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ -+ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ -+ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -+} DMA_CH_DESTDIR_t; -+ -+/* Transfer trigger source */ -+typedef enum DMA_CH_TRIGSRC_enum -+{ -+ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ -+ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ -+ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ -+ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ -+ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ -+ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ -+ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ -+ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ -+ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ -+ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ -+ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ -+ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ -+ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ -+ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ -+ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ -+ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ -+ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ -+ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ -+ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ -+ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ -+ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ -+ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ -+ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ -+ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ -+ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ -+ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ -+ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ -+ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ -+ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ -+ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ -+ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ -+ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ -+ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ -+ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ -+ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -+} DMA_CH_TRIGSRC_t; -+ -+/* Double buffering mode */ -+typedef enum DMA_DBUFMODE_enum -+{ -+ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ -+ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ -+ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ -+ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -+} DMA_DBUFMODE_t; -+ -+/* Priority mode */ -+typedef enum DMA_PRIMODE_enum -+{ -+ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ -+ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ -+ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ -+ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -+} DMA_PRIMODE_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_ERRINTLVL_enum -+{ -+ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ -+ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ -+ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -+} DMA_CH_ERRINTLVL_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_TRNINTLVL_enum -+{ -+ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ -+ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -+} DMA_CH_TRNINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ -+ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ -+ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ -+ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t CH4CTRL; /* Channel 4 Control Register */ -+ register8_t CH5CTRL; /* Channel 5 Control Register */ -+ register8_t CH6CTRL; /* Channel 6 Control Register */ -+ register8_t CH7CTRL; /* Channel 7 Control Register */ -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+} EVSYS_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ -+ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ -+ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ -+ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ -+ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ -+ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ -+ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ -+ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ -+ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ -+ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ -+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ -+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ -+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ -+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ -+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ -+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ -+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ -+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ -+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ -+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ -+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ -+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ -+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ -+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ -+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ -+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ -+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ -+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ -+ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ -+ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ -+ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ -+ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ -+ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ -+ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ -+ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ -+ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ -+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ -+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ -+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ -+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ -+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ -+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ -+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ -+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ -+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ -+ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ -+ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ -+ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ -+ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ -+ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ -+ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ -+ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ -+ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ -+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ -+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ -+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ -+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -+ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ -+ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ -+ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ -+ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ -+ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ -+ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ -+ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ -+ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -+ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ -+ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ -+ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ -+ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -+} EVSYS_CHMUX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ -+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ -+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ -+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ -+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} NVM_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t reserved_0x07; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ _WORDREGISTER(CH1RES); /* Channel 1 Result */ -+ _WORDREGISTER(CH2RES); /* Channel 2 Result */ -+ _WORDREGISTER(CH3RES); /* Channel 3 Result */ -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+ ADC_CH_t CH1; /* ADC Channel 1 */ -+ ADC_CH_t CH2; /* ADC Channel 2 */ -+ ADC_CH_t CH3; /* ADC Channel 3 */ -+} ADC_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -+ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+ ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 3) */ -+ ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Groud (Input Mode = 3) */ -+ ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Groud (Input Mode = 4) */ -+ ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 4) */ -+} ADC_CH_MUXNEG_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Current Limitation Mode */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ -+} ADC_CURRLIMIT_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Channel sweep selection */ -+typedef enum ADC_SWEEP_enum -+{ -+ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ -+ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ -+ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ -+ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -+} ADC_SWEEP_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ -+ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ -+ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ -+ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ -+ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ -+ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ -+ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ -+ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -+ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ -+ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ -+ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ -+ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* DMA request selection */ -+typedef enum ADC_DMASEL_enum -+{ -+ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ -+ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ -+ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ -+ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -+} ADC_DMASEL_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DAC - Digital/Analog Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Digital-to-Analog Converter */ -+typedef struct DAC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t EVCTRL; /* Event Input Control */ -+ register8_t reserved_0x04; -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0GAINCAL; /* Gain Calibration */ -+ register8_t CH0OFFSETCAL; /* Offset Calibration */ -+ register8_t CH1GAINCAL; /* Gain Calibration */ -+ register8_t CH1OFFSETCAL; /* Offset Calibration */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ -+ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -+} DAC_t; -+ -+/* Output channel selection */ -+typedef enum DAC_CHSEL_enum -+{ -+ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ -+ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ -+ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -+} DAC_CHSEL_t; -+ -+/* Reference voltage selection */ -+typedef enum DAC_REFSEL_enum -+{ -+ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ -+ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ -+ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ -+ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -+} DAC_REFSEL_t; -+ -+/* Event channel selection */ -+typedef enum DAC_EVSEL_enum -+{ -+ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ -+ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ -+ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ -+ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ -+ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ -+ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ -+ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ -+ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -+} DAC_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC32 - 32-bit Real-Time Counter -+-------------------------------------------------------------------------- -+*/ -+ -+/* 32-bit Real-Time Counter */ -+typedef struct RTC32_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t SYNCCTRL; /* Synchronization Control/Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _DWORDREGISTER(CNT); /* Count Register */ -+ _DWORDREGISTER(PER); /* Period Register */ -+ _DWORDREGISTER(COMP); /* Compare Register */ -+} RTC32_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC32_COMPINTLVL_enum -+{ -+ RTC32_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC32_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC32_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC32_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC32_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC32_OVFINTLVL_enum -+{ -+ RTC32_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC32_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC32_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC32_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC32_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+} TWI_t; -+ -+/* SDA Hold Time */ -+typedef enum TWI_SDAHOLD_enum -+{ -+ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ -+ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ -+ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ -+ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -+} TWI_SDAHOLD_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USB - USB -+-------------------------------------------------------------------------- -+*/ -+ -+/* USB Endpoint */ -+typedef struct USB_EP_struct -+{ -+ register8_t STATUS; /* Endpoint Status */ -+ register8_t CTRL; /* Endpoint Control */ -+ _WORDREGISTER(CNT); /* USB Endpoint Counter */ -+ _WORDREGISTER(DATAPTR); /* Data Pointer */ -+ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -+} USB_EP_t; -+ -+ -+/* Universal Serial Bus */ -+typedef struct USB_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t FIFOWP; /* FIFO Write Pointer Register */ -+ register8_t FIFORP; /* FIFO Read Pointer Register */ -+ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ -+ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ -+ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ -+ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t reserved_0x20; -+ register8_t reserved_0x21; -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t CAL0; /* Calibration Byte 0 */ -+ register8_t CAL1; /* Calibration Byte 1 */ -+} USB_t; -+ -+ -+/* USB Endpoint Table */ -+typedef struct USB_EP_TABLE_struct -+{ -+ USB_EP_t EP0OUT; /* Endpoint 0 */ -+ USB_EP_t EP0IN; /* Endpoint 0 */ -+ USB_EP_t EP1OUT; /* Endpoint 1 */ -+ USB_EP_t EP1IN; /* Endpoint 1 */ -+ USB_EP_t EP2OUT; /* Endpoint 2 */ -+ USB_EP_t EP2IN; /* Endpoint 2 */ -+ USB_EP_t EP3OUT; /* Endpoint 3 */ -+ USB_EP_t EP3IN; /* Endpoint 3 */ -+ USB_EP_t EP4OUT; /* Endpoint 4 */ -+ USB_EP_t EP4IN; /* Endpoint 4 */ -+ USB_EP_t EP5OUT; /* Endpoint 5 */ -+ USB_EP_t EP5IN; /* Endpoint 5 */ -+ USB_EP_t EP6OUT; /* Endpoint 6 */ -+ USB_EP_t EP6IN; /* Endpoint 6 */ -+ USB_EP_t EP7OUT; /* Endpoint 7 */ -+ USB_EP_t EP7IN; /* Endpoint 7 */ -+ USB_EP_t EP8OUT; /* Endpoint 8 */ -+ USB_EP_t EP8IN; /* Endpoint 8 */ -+ USB_EP_t EP9OUT; /* Endpoint 9 */ -+ USB_EP_t EP9IN; /* Endpoint 9 */ -+ USB_EP_t EP10OUT; /* Endpoint 10 */ -+ USB_EP_t EP10IN; /* Endpoint 10 */ -+ USB_EP_t EP11OUT; /* Endpoint 11 */ -+ USB_EP_t EP11IN; /* Endpoint 11 */ -+ USB_EP_t EP12OUT; /* Endpoint 12 */ -+ USB_EP_t EP12IN; /* Endpoint 12 */ -+ USB_EP_t EP13OUT; /* Endpoint 13 */ -+ USB_EP_t EP13IN; /* Endpoint 13 */ -+ USB_EP_t EP14OUT; /* Endpoint 14 */ -+ USB_EP_t EP14IN; /* Endpoint 14 */ -+ USB_EP_t EP15OUT; /* Endpoint 15 */ -+ USB_EP_t EP15IN; /* Endpoint 15 */ -+ register8_t reserved_0x100; -+ register8_t reserved_0x101; -+ register8_t reserved_0x102; -+ register8_t reserved_0x103; -+ register8_t reserved_0x104; -+ register8_t reserved_0x105; -+ register8_t reserved_0x106; -+ register8_t reserved_0x107; -+ register8_t reserved_0x108; -+ register8_t reserved_0x109; -+ register8_t reserved_0x10A; -+ register8_t reserved_0x10B; -+ register8_t reserved_0x10C; -+ register8_t reserved_0x10D; -+ register8_t reserved_0x10E; -+ register8_t reserved_0x10F; -+ register8_t FRAMENUML; /* Frame Number Low Byte */ -+ register8_t FRAMENUMH; /* Frame Number High Byte */ -+} USB_EP_TABLE_t; -+ -+/* Interrupt level */ -+typedef enum USB_INTLVL_enum -+{ -+ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} USB_INTLVL_t; -+ -+/* USB Endpoint Type */ -+typedef enum USB_EP_TYPE_enum -+{ -+ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ -+ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ -+ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ -+ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -+} USB_EP_TYPE_t; -+ -+/* USB Endpoint Buffersize */ -+typedef enum USB_EP_BUFSIZE_enum -+{ -+ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ -+ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ -+ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ -+ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ -+ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ -+ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ -+ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ -+ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -+} USB_EP_BUFSIZE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - I/O Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INT0MASK; /* Port Interrupt 0 Mask */ -+ register8_t INT1MASK; /* Port Interrupt 1 Mask */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t REMAP; /* I/O Port Pin Remap Register */ -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Port Interrupt 0 Level */ -+typedef enum PORT_INT0LVL_enum -+{ -+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INT0LVL_t; -+ -+/* Port Interrupt 1 Level */ -+typedef enum PORT_INT1LVL_enum -+{ -+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ -+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ -+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -+} PORT_INT1LVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 0 */ -+typedef struct TC0_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC0_t; -+ -+ -+/* 16-bit Timer/Counter 1 */ -+typedef struct TC1_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+} TC1_t; -+ -+/* Clock Selection */ -+typedef enum TC_CLKSEL_enum -+{ -+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC_CLKSEL_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC_WGMODE_enum -+{ -+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC_WGMODE_t; -+ -+/* Byte Mode */ -+typedef enum TC_BYTEM_enum -+{ -+ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ -+ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -+} TC_BYTEM_t; -+ -+/* Event Action */ -+typedef enum TC_EVACT_enum -+{ -+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ -+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ -+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ -+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ -+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ -+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC_EVSEL_enum -+{ -+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC_EVSEL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC_ERRINTLVL_enum -+{ -+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC_OVFINTLVL_enum -+{ -+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_OVFINTLVL_t; -+ -+/* Compare or Capture D Interrupt Level */ -+typedef enum TC_CCDINTLVL_enum -+{ -+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC_CCDINTLVL_t; -+ -+/* Compare or Capture C Interrupt Level */ -+typedef enum TC_CCCINTLVL_enum -+{ -+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC_CCCINTLVL_t; -+ -+/* Compare or Capture B Interrupt Level */ -+typedef enum TC_CCBINTLVL_enum -+{ -+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_CCBINTLVL_t; -+ -+/* Compare or Capture A Interrupt Level */ -+typedef enum TC_CCAINTLVL_enum -+{ -+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_CCAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC_CMD_enum -+{ -+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC2 - 16-bit Timer/Counter type 2 -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter type 2 */ -+typedef struct TC2_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t reserved_0x03; -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t reserved_0x08; -+ register8_t CTRLF; /* Control Register F */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t LCNT; /* Low Byte Count */ -+ register8_t HCNT; /* High Byte Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t LPER; /* Low Byte Period */ -+ register8_t HPER; /* High Byte Period */ -+ register8_t LCMPA; /* Low Byte Compare A */ -+ register8_t HCMPA; /* High Byte Compare A */ -+ register8_t LCMPB; /* Low Byte Compare B */ -+ register8_t HCMPB; /* High Byte Compare B */ -+ register8_t LCMPC; /* Low Byte Compare C */ -+ register8_t HCMPC; /* High Byte Compare C */ -+ register8_t LCMPD; /* Low Byte Compare D */ -+ register8_t HCMPD; /* High Byte Compare D */ -+} TC2_t; -+ -+/* Clock Selection */ -+typedef enum TC2_CLKSEL_enum -+{ -+ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC2_CLKSEL_t; -+ -+/* Byte Mode */ -+typedef enum TC2_BYTEM_enum -+{ -+ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ -+ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -+} TC2_BYTEM_t; -+ -+/* High Byte Underflow Interrupt Level */ -+typedef enum TC2_HUNFINTLVL_enum -+{ -+ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_HUNFINTLVL_t; -+ -+/* Low Byte Underflow Interrupt Level */ -+typedef enum TC2_LUNFINTLVL_enum -+{ -+ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LUNFINTLVL_t; -+ -+/* Low Byte Compare D Interrupt Level */ -+typedef enum TC2_LCMPDINTLVL_enum -+{ -+ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC2_LCMPDINTLVL_t; -+ -+/* Low Byte Compare C Interrupt Level */ -+typedef enum TC2_LCMPCINTLVL_enum -+{ -+ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC2_LCMPCINTLVL_t; -+ -+/* Low Byte Compare B Interrupt Level */ -+typedef enum TC2_LCMPBINTLVL_enum -+{ -+ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_LCMPBINTLVL_t; -+ -+/* Low Byte Compare A Interrupt Level */ -+typedef enum TC2_LCMPAINTLVL_enum -+{ -+ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LCMPAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMD_enum -+{ -+ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC2_CMD_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMDEN_enum -+{ -+ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ -+ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ -+ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -+} TC2_CMDEN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AWEX - Timer/Counter Advanced Waveform Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Advanced Waveform Extension */ -+typedef struct AWEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t FDEMASK; /* Fault Detection Event Mask */ -+ register8_t FDCTRL; /* Fault Detection Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t STATUSSET; /* Status Set Register */ -+ register8_t DTBOTH; /* Dead Time Both Sides */ -+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ -+ register8_t DTLS; /* Dead Time Low Side */ -+ register8_t DTHS; /* Dead Time High Side */ -+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ -+ register8_t DTHSBUF; /* Dead Time High Side Buffer */ -+ register8_t OUTOVEN; /* Output Override Enable */ -+} AWEX_t; -+ -+/* Fault Detect Action */ -+typedef enum AWEX_FDACT_enum -+{ -+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ -+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -+} AWEX_FDACT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+HIRES - Timer/Counter High-Resolution Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register */ -+} HIRES_t; -+ -+/* High Resolution Enable */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ -+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ -+ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ -+ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ -+ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -+} IRDA_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t FUSEBYTE0; /* JTAG User ID */ -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+} NVM_FUSES_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* Timer Oscillator pin location */ -+typedef enum TOSCSEL_enum -+{ -+ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ -+ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -+} TOSCSEL_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -+} BOD_t; -+ -+/* BOD operation */ -+typedef enum BODACT_enum -+{ -+ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BODACT_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WDP_enum -+{ -+ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ -+ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ -+ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ -+ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ -+ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ -+ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ -+ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ -+ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ -+ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ -+ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ -+ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -+} WDP_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LOCKBIT - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ -+ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t USBCAL0; /* USB Calibration Byte 0 */ -+ register8_t USBCAL1; /* USB Calibration Byte 1 */ -+ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ -+ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ -+ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ -+ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ -+ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ -+ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ -+ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ -+ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ -+ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ -+ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+ register8_t reserved_0x40; -+ register8_t reserved_0x41; -+ register8_t reserved_0x42; -+ register8_t reserved_0x43; -+ register8_t reserved_0x44; -+ register8_t reserved_0x45; -+ register8_t reserved_0x46; -+ register8_t reserved_0x47; -+} NVM_PROD_SIGNATURES_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define AES (*(AES_t *) 0x00C0) /* AES Module */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define VBAT (*(VBAT_t *) 0x00F0) /* Battery Backup Module */ -+#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ -+#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ -+#define RTC32 (*(RTC32_t *) 0x0420) /* 32-bit Real-Time Counter */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -+#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -+#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -+#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -+#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -+#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -+#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ -+#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ -+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -+#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -+#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -+#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ -+#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ -+#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ -+#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -+#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ -+#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ -+#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -+#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -+#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -+#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -+#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -+#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -+#define GPIO_GPIORA _SFR_MEM8(0x000A) -+#define GPIO_GPIORB _SFR_MEM8(0x000B) -+#define GPIO_GPIORC _SFR_MEM8(0x000C) -+#define GPIO_GPIORD _SFR_MEM8(0x000D) -+#define GPIO_GPIORE _SFR_MEM8(0x000E) -+#define GPIO_GPIORF _SFR_MEM8(0x000F) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+#define GPIO_GPIO4 _SFR_MEM8(0x0004) -+#define GPIO_GPIO5 _SFR_MEM8(0x0005) -+#define GPIO_GPIO6 _SFR_MEM8(0x0006) -+#define GPIO_GPIO7 _SFR_MEM8(0x0007) -+#define GPIO_GPIO8 _SFR_MEM8(0x0008) -+#define GPIO_GPIO9 _SFR_MEM8(0x0009) -+#define GPIO_GPIOA _SFR_MEM8(0x000A) -+#define GPIO_GPIOB _SFR_MEM8(0x000B) -+#define GPIO_GPIOC _SFR_MEM8(0x000C) -+#define GPIO_GPIOD _SFR_MEM8(0x000D) -+#define GPIO_GPIOE _SFR_MEM8(0x000E) -+#define GPIO_GPIOF _SFR_MEM8(0x000F) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -+#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -+#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -+#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -+#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -+#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -+#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) -+#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) -+#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -+#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) -+#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) -+#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+#define CLK_USBCTRL _SFR_MEM8(0x0044) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* DFLL - DFLL */ -+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -+#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -+#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPB _SFR_MEM8(0x0072) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPD _SFR_MEM8(0x0074) -+#define PR_PRPE _SFR_MEM8(0x0075) -+#define PR_PRPF _SFR_MEM8(0x0076) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_JTAGUID _SFR_MEM8(0x0094) -+#define MCU_MCUCR _SFR_MEM8(0x0096) -+#define MCU_ANAINIT _SFR_MEM8(0x0097) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_AWEXLOCK _SFR_MEM8(0x0099) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) -+#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) -+ -+/* AES - AES Module */ -+#define AES_CTRL _SFR_MEM8(0x00C0) -+#define AES_STATUS _SFR_MEM8(0x00C1) -+#define AES_STATE _SFR_MEM8(0x00C2) -+#define AES_KEY _SFR_MEM8(0x00C3) -+#define AES_INTCTRL _SFR_MEM8(0x00C4) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* VBAT - Battery Backup Module */ -+#define VBAT_CTRL _SFR_MEM8(0x00F0) -+#define VBAT_STATUS _SFR_MEM8(0x00F1) -+#define VBAT_BACKUP0 _SFR_MEM8(0x00F2) -+#define VBAT_BACKUP1 _SFR_MEM8(0x00F3) -+ -+/* DMA - DMA Controller */ -+#define DMA_CTRL _SFR_MEM8(0x0100) -+#define DMA_INTFLAGS _SFR_MEM8(0x0103) -+#define DMA_STATUS _SFR_MEM8(0x0104) -+#define DMA_TEMP _SFR_MEM16(0x0106) -+#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -+#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -+#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -+#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -+#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -+#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -+#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -+#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -+#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -+#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -+#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -+#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -+#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -+#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -+#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -+#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -+#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -+#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -+#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -+#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -+#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -+#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -+#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -+#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -+#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -+#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -+#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -+#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -+#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -+#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -+#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -+#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -+#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -+#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -+#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -+#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -+#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -+#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -+#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -+#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -+#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -+#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -+#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -+#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -+#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -+#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -+#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -+#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -+#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -+#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -+#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -+#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -+#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -+#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCA_CTRLA _SFR_MEM8(0x0200) -+#define ADCA_CTRLB _SFR_MEM8(0x0201) -+#define ADCA_REFCTRL _SFR_MEM8(0x0202) -+#define ADCA_EVCTRL _SFR_MEM8(0x0203) -+#define ADCA_PRESCALER _SFR_MEM8(0x0204) -+#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -+#define ADCA_TEMP _SFR_MEM8(0x0207) -+#define ADCA_CAL _SFR_MEM16(0x020C) -+#define ADCA_CH0RES _SFR_MEM16(0x0210) -+#define ADCA_CH1RES _SFR_MEM16(0x0212) -+#define ADCA_CH2RES _SFR_MEM16(0x0214) -+#define ADCA_CH3RES _SFR_MEM16(0x0216) -+#define ADCA_CMP _SFR_MEM16(0x0218) -+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -+#define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -+#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -+#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -+#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -+#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -+#define ADCA_CH1_RES _SFR_MEM16(0x022C) -+#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) -+#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -+#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -+#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -+#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -+#define ADCA_CH2_RES _SFR_MEM16(0x0234) -+#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) -+#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -+#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -+#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -+#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -+#define ADCA_CH3_RES _SFR_MEM16(0x023C) -+#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCB_CTRLA _SFR_MEM8(0x0240) -+#define ADCB_CTRLB _SFR_MEM8(0x0241) -+#define ADCB_REFCTRL _SFR_MEM8(0x0242) -+#define ADCB_EVCTRL _SFR_MEM8(0x0243) -+#define ADCB_PRESCALER _SFR_MEM8(0x0244) -+#define ADCB_INTFLAGS _SFR_MEM8(0x0246) -+#define ADCB_TEMP _SFR_MEM8(0x0247) -+#define ADCB_CAL _SFR_MEM16(0x024C) -+#define ADCB_CH0RES _SFR_MEM16(0x0250) -+#define ADCB_CH1RES _SFR_MEM16(0x0252) -+#define ADCB_CH2RES _SFR_MEM16(0x0254) -+#define ADCB_CH3RES _SFR_MEM16(0x0256) -+#define ADCB_CMP _SFR_MEM16(0x0258) -+#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) -+#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) -+#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) -+#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) -+#define ADCB_CH0_RES _SFR_MEM16(0x0264) -+#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) -+#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) -+#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) -+#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) -+#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) -+#define ADCB_CH1_RES _SFR_MEM16(0x026C) -+#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) -+#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) -+#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) -+#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) -+#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) -+#define ADCB_CH2_RES _SFR_MEM16(0x0274) -+#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) -+#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) -+#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) -+#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) -+#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) -+#define ADCB_CH3_RES _SFR_MEM16(0x027C) -+#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) -+ -+/* DAC - Digital-to-Analog Converter */ -+#define DACB_CTRLA _SFR_MEM8(0x0320) -+#define DACB_CTRLB _SFR_MEM8(0x0321) -+#define DACB_CTRLC _SFR_MEM8(0x0322) -+#define DACB_EVCTRL _SFR_MEM8(0x0323) -+#define DACB_STATUS _SFR_MEM8(0x0325) -+#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) -+#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) -+#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) -+#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) -+#define DACB_CH0DATA _SFR_MEM16(0x0338) -+#define DACB_CH1DATA _SFR_MEM16(0x033A) -+ -+/* AC - Analog Comparator */ -+#define ACA_AC0CTRL _SFR_MEM8(0x0380) -+#define ACA_AC1CTRL _SFR_MEM8(0x0381) -+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -+#define ACA_CTRLA _SFR_MEM8(0x0384) -+#define ACA_CTRLB _SFR_MEM8(0x0385) -+#define ACA_WINCTRL _SFR_MEM8(0x0386) -+#define ACA_STATUS _SFR_MEM8(0x0387) -+ -+/* AC - Analog Comparator */ -+#define ACB_AC0CTRL _SFR_MEM8(0x0390) -+#define ACB_AC1CTRL _SFR_MEM8(0x0391) -+#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -+#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -+#define ACB_CTRLA _SFR_MEM8(0x0394) -+#define ACB_CTRLB _SFR_MEM8(0x0395) -+#define ACB_WINCTRL _SFR_MEM8(0x0396) -+#define ACB_STATUS _SFR_MEM8(0x0397) -+ -+/* RTC32 - 32-bit Real-Time Counter */ -+#define RTC32_CTRL _SFR_MEM8(0x0420) -+#define RTC32_SYNCCTRL _SFR_MEM8(0x0421) -+#define RTC32_INTCTRL _SFR_MEM8(0x0422) -+#define RTC32_INTFLAGS _SFR_MEM8(0x0423) -+#define RTC32_CNT _SFR_MEM32(0x0424) -+#define RTC32_PER _SFR_MEM32(0x0428) -+#define RTC32_COMP _SFR_MEM32(0x042C) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIE_CTRL _SFR_MEM8(0x04A0) -+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -+ -+/* USB - Universal Serial Bus */ -+#define USB_CTRLA _SFR_MEM8(0x04C0) -+#define USB_CTRLB _SFR_MEM8(0x04C1) -+#define USB_STATUS _SFR_MEM8(0x04C2) -+#define USB_ADDR _SFR_MEM8(0x04C3) -+#define USB_FIFOWP _SFR_MEM8(0x04C4) -+#define USB_FIFORP _SFR_MEM8(0x04C5) -+#define USB_EPPTR _SFR_MEM16(0x04C6) -+#define USB_INTCTRLA _SFR_MEM8(0x04C8) -+#define USB_INTCTRLB _SFR_MEM8(0x04C9) -+#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -+#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -+#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -+#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -+#define USB_CAL0 _SFR_MEM8(0x04FA) -+#define USB_CAL1 _SFR_MEM8(0x04FB) -+ -+/* PORT - I/O Ports */ -+#define PORTA_DIR _SFR_MEM8(0x0600) -+#define PORTA_DIRSET _SFR_MEM8(0x0601) -+#define PORTA_DIRCLR _SFR_MEM8(0x0602) -+#define PORTA_DIRTGL _SFR_MEM8(0x0603) -+#define PORTA_OUT _SFR_MEM8(0x0604) -+#define PORTA_OUTSET _SFR_MEM8(0x0605) -+#define PORTA_OUTCLR _SFR_MEM8(0x0606) -+#define PORTA_OUTTGL _SFR_MEM8(0x0607) -+#define PORTA_IN _SFR_MEM8(0x0608) -+#define PORTA_INTCTRL _SFR_MEM8(0x0609) -+#define PORTA_INT0MASK _SFR_MEM8(0x060A) -+#define PORTA_INT1MASK _SFR_MEM8(0x060B) -+#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_REMAP _SFR_MEM8(0x060E) -+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -+ -+/* PORT - I/O Ports */ -+#define PORTB_DIR _SFR_MEM8(0x0620) -+#define PORTB_DIRSET _SFR_MEM8(0x0621) -+#define PORTB_DIRCLR _SFR_MEM8(0x0622) -+#define PORTB_DIRTGL _SFR_MEM8(0x0623) -+#define PORTB_OUT _SFR_MEM8(0x0624) -+#define PORTB_OUTSET _SFR_MEM8(0x0625) -+#define PORTB_OUTCLR _SFR_MEM8(0x0626) -+#define PORTB_OUTTGL _SFR_MEM8(0x0627) -+#define PORTB_IN _SFR_MEM8(0x0628) -+#define PORTB_INTCTRL _SFR_MEM8(0x0629) -+#define PORTB_INT0MASK _SFR_MEM8(0x062A) -+#define PORTB_INT1MASK _SFR_MEM8(0x062B) -+#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -+#define PORTB_REMAP _SFR_MEM8(0x062E) -+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INT0MASK _SFR_MEM8(0x064A) -+#define PORTC_INT1MASK _SFR_MEM8(0x064B) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INT0MASK _SFR_MEM8(0x066A) -+#define PORTD_INT1MASK _SFR_MEM8(0x066B) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTE_DIR _SFR_MEM8(0x0680) -+#define PORTE_DIRSET _SFR_MEM8(0x0681) -+#define PORTE_DIRCLR _SFR_MEM8(0x0682) -+#define PORTE_DIRTGL _SFR_MEM8(0x0683) -+#define PORTE_OUT _SFR_MEM8(0x0684) -+#define PORTE_OUTSET _SFR_MEM8(0x0685) -+#define PORTE_OUTCLR _SFR_MEM8(0x0686) -+#define PORTE_OUTTGL _SFR_MEM8(0x0687) -+#define PORTE_IN _SFR_MEM8(0x0688) -+#define PORTE_INTCTRL _SFR_MEM8(0x0689) -+#define PORTE_INT0MASK _SFR_MEM8(0x068A) -+#define PORTE_INT1MASK _SFR_MEM8(0x068B) -+#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -+#define PORTE_REMAP _SFR_MEM8(0x068E) -+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) -+ -+/* PORT - I/O Ports */ -+#define PORTF_DIR _SFR_MEM8(0x06A0) -+#define PORTF_DIRSET _SFR_MEM8(0x06A1) -+#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -+#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -+#define PORTF_OUT _SFR_MEM8(0x06A4) -+#define PORTF_OUTSET _SFR_MEM8(0x06A5) -+#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -+#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -+#define PORTF_IN _SFR_MEM8(0x06A8) -+#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -+#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -+#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -+#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -+#define PORTF_REMAP _SFR_MEM8(0x06AE) -+#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -+#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -+#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -+#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -+#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -+#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -+#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -+#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -+#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCC0_CTRLA _SFR_MEM8(0x0800) -+#define TCC0_CTRLB _SFR_MEM8(0x0801) -+#define TCC0_CTRLC _SFR_MEM8(0x0802) -+#define TCC0_CTRLD _SFR_MEM8(0x0803) -+#define TCC0_CTRLE _SFR_MEM8(0x0804) -+#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -+#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -+#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -+#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC0_TEMP _SFR_MEM8(0x080F) -+#define TCC0_CNT _SFR_MEM16(0x0820) -+#define TCC0_PER _SFR_MEM16(0x0826) -+#define TCC0_CCA _SFR_MEM16(0x0828) -+#define TCC0_CCB _SFR_MEM16(0x082A) -+#define TCC0_CCC _SFR_MEM16(0x082C) -+#define TCC0_CCD _SFR_MEM16(0x082E) -+#define TCC0_PERBUF _SFR_MEM16(0x0836) -+#define TCC0_CCABUF _SFR_MEM16(0x0838) -+#define TCC0_CCBBUF _SFR_MEM16(0x083A) -+#define TCC0_CCCBUF _SFR_MEM16(0x083C) -+#define TCC0_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCC2_CTRLA _SFR_MEM8(0x0800) -+#define TCC2_CTRLB _SFR_MEM8(0x0801) -+#define TCC2_CTRLC _SFR_MEM8(0x0802) -+#define TCC2_CTRLE _SFR_MEM8(0x0804) -+#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC2_CTRLF _SFR_MEM8(0x0809) -+#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC2_LCNT _SFR_MEM8(0x0820) -+#define TCC2_HCNT _SFR_MEM8(0x0821) -+#define TCC2_LPER _SFR_MEM8(0x0826) -+#define TCC2_HPER _SFR_MEM8(0x0827) -+#define TCC2_LCMPA _SFR_MEM8(0x0828) -+#define TCC2_HCMPA _SFR_MEM8(0x0829) -+#define TCC2_LCMPB _SFR_MEM8(0x082A) -+#define TCC2_HCMPB _SFR_MEM8(0x082B) -+#define TCC2_LCMPC _SFR_MEM8(0x082C) -+#define TCC2_HCMPC _SFR_MEM8(0x082D) -+#define TCC2_LCMPD _SFR_MEM8(0x082E) -+#define TCC2_HCMPD _SFR_MEM8(0x082F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCC1_CTRLA _SFR_MEM8(0x0840) -+#define TCC1_CTRLB _SFR_MEM8(0x0841) -+#define TCC1_CTRLC _SFR_MEM8(0x0842) -+#define TCC1_CTRLD _SFR_MEM8(0x0843) -+#define TCC1_CTRLE _SFR_MEM8(0x0844) -+#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -+#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -+#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -+#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC1_TEMP _SFR_MEM8(0x084F) -+#define TCC1_CNT _SFR_MEM16(0x0860) -+#define TCC1_PER _SFR_MEM16(0x0866) -+#define TCC1_CCA _SFR_MEM16(0x0868) -+#define TCC1_CCB _SFR_MEM16(0x086A) -+#define TCC1_PERBUF _SFR_MEM16(0x0876) -+#define TCC1_CCABUF _SFR_MEM16(0x0878) -+#define TCC1_CCBBUF _SFR_MEM16(0x087A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXC_CTRL _SFR_MEM8(0x0880) -+#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -+#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -+#define AWEXC_STATUS _SFR_MEM8(0x0884) -+#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -+#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -+#define AWEXC_DTLS _SFR_MEM8(0x0888) -+#define AWEXC_DTHS _SFR_MEM8(0x0889) -+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x0890) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08A0) -+#define USARTC0_STATUS _SFR_MEM8(0x08A1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -+#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -+#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC1_DATA _SFR_MEM8(0x08B0) -+#define USARTC1_STATUS _SFR_MEM8(0x08B1) -+#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -+#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -+#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -+#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -+#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIC_CTRL _SFR_MEM8(0x08C0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -+#define SPIC_STATUS _SFR_MEM8(0x08C2) -+#define SPIC_DATA _SFR_MEM8(0x08C3) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCD0_CTRLA _SFR_MEM8(0x0900) -+#define TCD0_CTRLB _SFR_MEM8(0x0901) -+#define TCD0_CTRLC _SFR_MEM8(0x0902) -+#define TCD0_CTRLD _SFR_MEM8(0x0903) -+#define TCD0_CTRLE _SFR_MEM8(0x0904) -+#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -+#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -+#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -+#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -+#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD0_TEMP _SFR_MEM8(0x090F) -+#define TCD0_CNT _SFR_MEM16(0x0920) -+#define TCD0_PER _SFR_MEM16(0x0926) -+#define TCD0_CCA _SFR_MEM16(0x0928) -+#define TCD0_CCB _SFR_MEM16(0x092A) -+#define TCD0_CCC _SFR_MEM16(0x092C) -+#define TCD0_CCD _SFR_MEM16(0x092E) -+#define TCD0_PERBUF _SFR_MEM16(0x0936) -+#define TCD0_CCABUF _SFR_MEM16(0x0938) -+#define TCD0_CCBBUF _SFR_MEM16(0x093A) -+#define TCD0_CCCBUF _SFR_MEM16(0x093C) -+#define TCD0_CCDBUF _SFR_MEM16(0x093E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCD2_CTRLA _SFR_MEM8(0x0900) -+#define TCD2_CTRLB _SFR_MEM8(0x0901) -+#define TCD2_CTRLC _SFR_MEM8(0x0902) -+#define TCD2_CTRLE _SFR_MEM8(0x0904) -+#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD2_CTRLF _SFR_MEM8(0x0909) -+#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD2_LCNT _SFR_MEM8(0x0920) -+#define TCD2_HCNT _SFR_MEM8(0x0921) -+#define TCD2_LPER _SFR_MEM8(0x0926) -+#define TCD2_HPER _SFR_MEM8(0x0927) -+#define TCD2_LCMPA _SFR_MEM8(0x0928) -+#define TCD2_HCMPA _SFR_MEM8(0x0929) -+#define TCD2_LCMPB _SFR_MEM8(0x092A) -+#define TCD2_HCMPB _SFR_MEM8(0x092B) -+#define TCD2_LCMPC _SFR_MEM8(0x092C) -+#define TCD2_HCMPC _SFR_MEM8(0x092D) -+#define TCD2_LCMPD _SFR_MEM8(0x092E) -+#define TCD2_HCMPD _SFR_MEM8(0x092F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCD1_CTRLA _SFR_MEM8(0x0940) -+#define TCD1_CTRLB _SFR_MEM8(0x0941) -+#define TCD1_CTRLC _SFR_MEM8(0x0942) -+#define TCD1_CTRLD _SFR_MEM8(0x0943) -+#define TCD1_CTRLE _SFR_MEM8(0x0944) -+#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -+#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -+#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -+#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -+#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -+#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -+#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -+#define TCD1_TEMP _SFR_MEM8(0x094F) -+#define TCD1_CNT _SFR_MEM16(0x0960) -+#define TCD1_PER _SFR_MEM16(0x0966) -+#define TCD1_CCA _SFR_MEM16(0x0968) -+#define TCD1_CCB _SFR_MEM16(0x096A) -+#define TCD1_PERBUF _SFR_MEM16(0x0976) -+#define TCD1_CCABUF _SFR_MEM16(0x0978) -+#define TCD1_CCBBUF _SFR_MEM16(0x097A) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESD_CTRLA _SFR_MEM8(0x0990) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD0_DATA _SFR_MEM8(0x09A0) -+#define USARTD0_STATUS _SFR_MEM8(0x09A1) -+#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -+#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -+#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD1_DATA _SFR_MEM8(0x09B0) -+#define USARTD1_STATUS _SFR_MEM8(0x09B1) -+#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -+#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -+#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -+#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -+#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPID_CTRL _SFR_MEM8(0x09C0) -+#define SPID_INTCTRL _SFR_MEM8(0x09C1) -+#define SPID_STATUS _SFR_MEM8(0x09C2) -+#define SPID_DATA _SFR_MEM8(0x09C3) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCE0_CTRLA _SFR_MEM8(0x0A00) -+#define TCE0_CTRLB _SFR_MEM8(0x0A01) -+#define TCE0_CTRLC _SFR_MEM8(0x0A02) -+#define TCE0_CTRLD _SFR_MEM8(0x0A03) -+#define TCE0_CTRLE _SFR_MEM8(0x0A04) -+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE0_TEMP _SFR_MEM8(0x0A0F) -+#define TCE0_CNT _SFR_MEM16(0x0A20) -+#define TCE0_PER _SFR_MEM16(0x0A26) -+#define TCE0_CCA _SFR_MEM16(0x0A28) -+#define TCE0_CCB _SFR_MEM16(0x0A2A) -+#define TCE0_CCC _SFR_MEM16(0x0A2C) -+#define TCE0_CCD _SFR_MEM16(0x0A2E) -+#define TCE0_PERBUF _SFR_MEM16(0x0A36) -+#define TCE0_CCABUF _SFR_MEM16(0x0A38) -+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCE2_CTRLA _SFR_MEM8(0x0A00) -+#define TCE2_CTRLB _SFR_MEM8(0x0A01) -+#define TCE2_CTRLC _SFR_MEM8(0x0A02) -+#define TCE2_CTRLE _SFR_MEM8(0x0A04) -+#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE2_CTRLF _SFR_MEM8(0x0A09) -+#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE2_LCNT _SFR_MEM8(0x0A20) -+#define TCE2_HCNT _SFR_MEM8(0x0A21) -+#define TCE2_LPER _SFR_MEM8(0x0A26) -+#define TCE2_HPER _SFR_MEM8(0x0A27) -+#define TCE2_LCMPA _SFR_MEM8(0x0A28) -+#define TCE2_HCMPA _SFR_MEM8(0x0A29) -+#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -+#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -+#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -+#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -+#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -+#define TCE2_HCMPD _SFR_MEM8(0x0A2F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCE1_CTRLA _SFR_MEM8(0x0A40) -+#define TCE1_CTRLB _SFR_MEM8(0x0A41) -+#define TCE1_CTRLC _SFR_MEM8(0x0A42) -+#define TCE1_CTRLD _SFR_MEM8(0x0A43) -+#define TCE1_CTRLE _SFR_MEM8(0x0A44) -+#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) -+#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) -+#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) -+#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) -+#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) -+#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) -+#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) -+#define TCE1_TEMP _SFR_MEM8(0x0A4F) -+#define TCE1_CNT _SFR_MEM16(0x0A60) -+#define TCE1_PER _SFR_MEM16(0x0A66) -+#define TCE1_CCA _SFR_MEM16(0x0A68) -+#define TCE1_CCB _SFR_MEM16(0x0A6A) -+#define TCE1_PERBUF _SFR_MEM16(0x0A76) -+#define TCE1_CCABUF _SFR_MEM16(0x0A78) -+#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXE_CTRL _SFR_MEM8(0x0A80) -+#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) -+#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) -+#define AWEXE_STATUS _SFR_MEM8(0x0A84) -+#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) -+#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) -+#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) -+#define AWEXE_DTLS _SFR_MEM8(0x0A88) -+#define AWEXE_DTHS _SFR_MEM8(0x0A89) -+#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) -+#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) -+#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESE_CTRLA _SFR_MEM8(0x0A90) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE0_DATA _SFR_MEM8(0x0AA0) -+#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -+#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -+#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -+#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -+#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -+#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCF0_CTRLA _SFR_MEM8(0x0B00) -+#define TCF0_CTRLB _SFR_MEM8(0x0B01) -+#define TCF0_CTRLC _SFR_MEM8(0x0B02) -+#define TCF0_CTRLD _SFR_MEM8(0x0B03) -+#define TCF0_CTRLE _SFR_MEM8(0x0B04) -+#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -+#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -+#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -+#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -+#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -+#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -+#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -+#define TCF0_TEMP _SFR_MEM8(0x0B0F) -+#define TCF0_CNT _SFR_MEM16(0x0B20) -+#define TCF0_PER _SFR_MEM16(0x0B26) -+#define TCF0_CCA _SFR_MEM16(0x0B28) -+#define TCF0_CCB _SFR_MEM16(0x0B2A) -+#define TCF0_CCC _SFR_MEM16(0x0B2C) -+#define TCF0_CCD _SFR_MEM16(0x0B2E) -+#define TCF0_PERBUF _SFR_MEM16(0x0B36) -+#define TCF0_CCABUF _SFR_MEM16(0x0B38) -+#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -+#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -+#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCF2_CTRLA _SFR_MEM8(0x0B00) -+#define TCF2_CTRLB _SFR_MEM8(0x0B01) -+#define TCF2_CTRLC _SFR_MEM8(0x0B02) -+#define TCF2_CTRLE _SFR_MEM8(0x0B04) -+#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -+#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -+#define TCF2_CTRLF _SFR_MEM8(0x0B09) -+#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -+#define TCF2_LCNT _SFR_MEM8(0x0B20) -+#define TCF2_HCNT _SFR_MEM8(0x0B21) -+#define TCF2_LPER _SFR_MEM8(0x0B26) -+#define TCF2_HPER _SFR_MEM8(0x0B27) -+#define TCF2_LCMPA _SFR_MEM8(0x0B28) -+#define TCF2_HCMPA _SFR_MEM8(0x0B29) -+#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -+#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -+#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -+#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -+#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -+#define TCF2_HCMPD _SFR_MEM8(0x0B2F) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESF_CTRLA _SFR_MEM8(0x0B90) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTF0_DATA _SFR_MEM8(0x0BA0) -+#define USARTF0_STATUS _SFR_MEM8(0x0BA1) -+#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) -+#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) -+#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) -+#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) -+#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* VPORT - Virtual Ports */ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* CLK.USBCTRL bit masks and bit positions */ -+#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -+#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -+#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -+#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -+#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -+#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -+#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -+#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ -+ -+#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -+#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -+#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ -+ -+#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_USB_bm 0x40 /* USB bit mask. */ -+#define PR_USB_bp 6 /* USB bit position. */ -+ -+#define PR_AES_bm 0x10 /* AES bit mask. */ -+#define PR_AES_bp 4 /* AES bit position. */ -+ -+#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -+#define PR_EBI_bp 3 /* External Bus Interface bit position. */ -+ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -+#define PR_DMA_bp 0 /* DMA-Controller bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -+#define PR_DAC_bp 2 /* Port A DAC bit position. */ -+ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPB bit masks and bit positions */ -+/* PR_DAC Predefined. */ -+/* PR_DAC Predefined. */ -+ -+/* PR_ADC Predefined. */ -+/* PR_ADC Predefined. */ -+ -+/* PR_AC Predefined. */ -+/* PR_AC Predefined. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -+#define PR_USART1_bp 5 /* Port C USART1 bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -+#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ -+ -+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -+ -+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ -+ -+/* PR.PRPD bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPE bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPF bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -+#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -+#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ -+ -+#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ -+ -+#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -+#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.MCUCR bit masks and bit positions */ -+#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -+#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ -+ -+/* MCU.ANAINIT bit masks and bit positions */ -+#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -+#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -+#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -+#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -+#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -+#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ -+ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -+#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ -+ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.AWEXLOCK bit masks and bit positions */ -+#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ -+#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ -+ -+#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -+#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ -+ -+#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ -+#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ -+ -+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* PORTCFG - Port Configuration */ -+/* PORTCFG.VPCTRLA bit masks and bit positions */ -+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ -+ -+/* PORTCFG.VPCTRLB bit masks and bit positions */ -+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ -+ -+/* PORTCFG.CLKEVOUT bit masks and bit positions */ -+#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ -+ -+#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -+#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -+#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -+#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -+#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -+#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ -+ -+#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -+#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ -+ -+#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -+#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ -+ -+/* PORTCFG.EBIOUT bit masks and bit positions */ -+#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ -+#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ -+#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ -+#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ -+#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ -+#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ -+ -+#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ -+#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ -+#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ -+#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ -+#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ -+#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ -+ -+/* PORTCFG.EVOUTSEL bit masks and bit positions */ -+#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -+#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -+#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -+#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -+#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -+#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -+#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -+#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ -+ -+/* AES - AES Module */ -+/* AES.CTRL bit masks and bit positions */ -+#define AES_START_bm 0x80 /* Start/Run bit mask. */ -+#define AES_START_bp 7 /* Start/Run bit position. */ -+ -+#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -+#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ -+ -+#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -+#define AES_RESET_bp 5 /* AES Software Reset bit position. */ -+ -+#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -+#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ -+ -+#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -+#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ -+ -+/* AES.STATUS bit masks and bit positions */ -+#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -+#define AES_ERROR_bp 7 /* AES Error bit position. */ -+ -+#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -+#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ -+ -+/* AES.INTCTRL bit masks and bit positions */ -+#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -+#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* VBAT - Battery Backup Module */ -+/* VBAT.CTRL bit masks and bit positions */ -+#define VBAT_HIGHESR_bm 0x20 /* 32-kHz Crystal Oscillator High Power Mode bit mask. */ -+#define VBAT_HIGHESR_bp 5 /* 32-kHz Crystal Oscillator High Power Mode bit position. */ -+ -+#define VBAT_XOSCSEL_bm 0x10 /* 32-kHz Crystal Oscillator Output Selection bit mask. */ -+#define VBAT_XOSCSEL_bp 4 /* 32-kHz Crystal Oscillator Output Selection bit position. */ -+ -+#define VBAT_XOSCEN_bm 0x08 /* Crystal Oscillator Enable bit mask. */ -+#define VBAT_XOSCEN_bp 3 /* Crystal Oscillator Enable bit position. */ -+ -+#define VBAT_XOSCFDEN_bm 0x04 /* Crystal Oscillator Failure Detection Monitor Enable bit mask. */ -+#define VBAT_XOSCFDEN_bp 2 /* Crystal Oscillator Failure Detection Monitor Enable bit position. */ -+ -+#define VBAT_ACCEN_bm 0x02 /* Access Enable bit mask. */ -+#define VBAT_ACCEN_bp 1 /* Access Enable bit position. */ -+ -+#define VBAT_RESET_bm 0x01 /* Reset bit mask. */ -+#define VBAT_RESET_bp 0 /* Reset bit position. */ -+ -+/* VBAT.STATUS bit masks and bit positions */ -+#define VBAT_BBPWR_bm 0x80 /* Battery backup Power bit mask. */ -+#define VBAT_BBPWR_bp 7 /* Battery backup Power bit position. */ -+ -+#define VBAT_XOSCRDY_bm 0x08 /* Crystal Oscillator Ready bit mask. */ -+#define VBAT_XOSCRDY_bp 3 /* Crystal Oscillator Ready bit position. */ -+ -+#define VBAT_XOSCFAIL_bm 0x04 /* Crystal Oscillator Failure bit mask. */ -+#define VBAT_XOSCFAIL_bp 2 /* Crystal Oscillator Failure bit position. */ -+ -+#define VBAT_BBBORF_bm 0x02 /* Battery Backup Brown-Out Reset Flag bit mask. */ -+#define VBAT_BBBORF_bp 1 /* Battery Backup Brown-Out Reset Flag bit position. */ -+ -+#define VBAT_BBPORF_bm 0x01 /* Battery Backup Power-On Reset Flag bit mask. */ -+#define VBAT_BBPORF_bp 0 /* Battery Backup Power-On Reset Flag bit position. */ -+ -+/* DMA - DMA Controller */ -+/* DMA_CH.CTRLA bit masks and bit positions */ -+#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -+#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ -+ -+#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -+#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ -+ -+#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -+#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ -+ -+#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -+#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ -+ -+#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -+#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ -+ -+#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -+#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -+#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -+#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -+#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -+#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ -+ -+/* DMA_CH.CTRLB bit masks and bit positions */ -+#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -+#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ -+ -+#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -+#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ -+ -+#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -+#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ -+ -+#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -+#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -+#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -+#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -+#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -+#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ -+ -+#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -+#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -+#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -+#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -+#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -+#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ -+ -+/* DMA_CH.ADDRCTRL bit masks and bit positions */ -+#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -+#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -+#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -+#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -+#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -+#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ -+ -+#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -+#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -+#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -+#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -+#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -+#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ -+ -+#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -+#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -+#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -+#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -+#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -+#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ -+ -+#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -+#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -+#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -+#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -+#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -+#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ -+ -+/* DMA_CH.TRIGSRC bit masks and bit positions */ -+#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -+#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -+#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -+#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -+#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -+#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -+#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -+#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -+#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -+#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -+#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -+#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -+#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -+#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -+#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -+#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -+#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -+#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ -+ -+/* DMA.CTRL bit masks and bit positions */ -+#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -+#define DMA_ENABLE_bp 7 /* Enable bit position. */ -+ -+#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -+#define DMA_RESET_bp 6 /* Software Reset bit position. */ -+ -+#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -+#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -+#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -+#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -+#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -+#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ -+ -+#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -+#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -+#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -+#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -+#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -+#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ -+ -+/* DMA.INTFLAGS bit masks and bit positions */ -+#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ -+ -+/* DMA.STATUS bit masks and bit positions */ -+#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -+#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ -+ -+#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -+#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ -+ -+#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -+#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ -+ -+#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -+#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ -+ -+#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -+#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ -+ -+#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -+#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ -+ -+#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -+#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ -+ -+#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -+#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH4MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH5MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH6MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH7MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_QDIRM Predefined. */ -+/* EVSYS_QDIRM Predefined. */ -+ -+/* EVSYS_QDIEN Predefined. */ -+/* EVSYS_QDIEN Predefined. */ -+ -+/* EVSYS_QDEN Predefined. */ -+/* EVSYS_QDEN Predefined. */ -+ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH4CTRL bit masks and bit positions */ -+/* EVSYS_QDIRM Predefined. */ -+/* EVSYS_QDIRM Predefined. */ -+ -+/* EVSYS_QDIEN Predefined. */ -+/* EVSYS_QDIEN Predefined. */ -+ -+/* EVSYS_QDEN Predefined. */ -+/* EVSYS_QDEN Predefined. */ -+ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH5CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH6CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH7CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0x7F /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ -+ -+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ -+ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -+#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ -+#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -+#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -+#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -+#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -+#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -+#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -+#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -+#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -+#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -+#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ -+ -+#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -+#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -+#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -+#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -+#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -+#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -+#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -+#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -+#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -+#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -+#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -+#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -+#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -+#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -+#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ -+ -+#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -+#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ -+ -+#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -+#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ -+ -+#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -+#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ -+ -+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -+#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ -+#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ -+ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -+#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -+#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -+#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -+#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -+#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ -+ -+#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -+#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -+#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ -+ -+#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -+#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ -+ -+#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -+#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ -+ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* DAC - Digital/Analog Converter */ -+/* DAC.CTRLA bit masks and bit positions */ -+#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -+#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ -+ -+#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -+#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ -+ -+#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -+#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ -+ -+#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -+#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ -+ -+#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define DAC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* DAC.CTRLB bit masks and bit positions */ -+#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -+#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -+#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -+#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -+#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -+#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ -+ -+#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -+#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ -+ -+#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -+#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ -+ -+/* DAC.CTRLC bit masks and bit positions */ -+#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -+#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -+#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -+#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -+#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -+#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ -+ -+#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -+#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ -+ -+/* DAC.EVCTRL bit masks and bit positions */ -+#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -+#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ -+ -+#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -+#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -+#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -+#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -+#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -+#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -+#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -+#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ -+ -+/* DAC.STATUS bit masks and bit positions */ -+#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -+#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ -+ -+#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -+#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ -+ -+/* DAC.CH0GAINCAL bit masks and bit positions */ -+#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -+#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -+#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -+#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -+#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -+#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -+#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -+#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -+#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -+#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -+#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -+#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -+#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -+#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -+#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -+#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ -+ -+/* DAC.CH0OFFSETCAL bit masks and bit positions */ -+#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -+#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -+#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -+#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -+#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -+#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -+#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -+#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -+#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -+#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -+#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -+#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -+#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -+#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -+#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -+#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ -+ -+/* DAC.CH1GAINCAL bit masks and bit positions */ -+#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -+#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -+#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -+#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -+#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -+#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -+#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -+#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -+#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -+#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -+#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -+#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -+#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -+#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -+#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -+#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ -+ -+/* DAC.CH1OFFSETCAL bit masks and bit positions */ -+#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -+#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -+#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -+#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -+#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -+#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -+#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -+#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -+#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -+#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -+#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -+#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -+#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -+#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -+#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -+#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -+#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HSMODE Predefined. */ -+/* AC_HSMODE Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* RTC32 - 32-bit Real-Time Counter */ -+/* RTC32.CTRL bit masks and bit positions */ -+#define RTC32_ENABLE_bm 0x01 /* RTC enable bit mask. */ -+#define RTC32_ENABLE_bp 0 /* RTC enable bit position. */ -+ -+/* RTC32.SYNCCTRL bit masks and bit positions */ -+#define RTC32_SYNCCNT_bm 0x10 /* Synchronization Busy Flag bit mask. */ -+#define RTC32_SYNCCNT_bp 4 /* Synchronization Busy Flag bit position. */ -+ -+#define RTC32_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC32_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC32.INTCTRL bit masks and bit positions */ -+#define RTC32_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC32_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC32_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC32_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC32_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC32_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC32_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC32_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC32_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC32_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC32_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC32_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC32.INTFLAGS bit masks and bit positions */ -+#define RTC32_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC32_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC32_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC32_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* USB - USB */ -+/* USB_EP.STATUS bit masks and bit positions */ -+#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -+#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ -+ -+#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -+#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ -+ -+#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -+#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ -+ -+#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -+#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ -+ -+#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -+#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ -+ -+#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -+#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ -+ -+#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -+#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ -+ -+#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -+#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ -+ -+#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ -+ -+#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ -+ -+#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -+#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ -+ -+/* USB_EP.CTRL bit masks and bit positions */ -+#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -+#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -+#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -+#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -+#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -+#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ -+ -+#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -+#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ -+ -+#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -+#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ -+ -+#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -+#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ -+ -+#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -+#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ -+ -+#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -+#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -+#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -+#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -+#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -+#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -+#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -+#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ -+ -+/* USB_EP.CNT bit masks and bit positions */ -+#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -+#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ -+ -+/* USB.CTRLA bit masks and bit positions */ -+#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -+#define USB_ENABLE_bp 7 /* USB Enable bit position. */ -+ -+#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -+#define USB_SPEED_bp 6 /* Speed Select bit position. */ -+ -+#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -+#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ -+ -+#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -+#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ -+ -+#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -+#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -+#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -+#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -+#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -+#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -+#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -+#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -+#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -+#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ -+ -+/* USB.CTRLB bit masks and bit positions */ -+#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -+#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ -+ -+#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -+#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ -+ -+#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -+#define USB_GNACK_bp 1 /* Global NACK bit position. */ -+ -+#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -+#define USB_ATTACH_bp 0 /* Attach bit position. */ -+ -+/* USB.STATUS bit masks and bit positions */ -+#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -+#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ -+ -+#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -+#define USB_RESUME_bp 2 /* Resume bit position. */ -+ -+#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -+#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ -+ -+#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -+#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ -+ -+/* USB.ADDR bit masks and bit positions */ -+#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -+#define USB_ADDR_gp 0 /* Device Address group position. */ -+#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -+#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -+#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -+#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -+#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -+#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -+#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -+#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -+#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -+#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -+#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -+#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -+#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -+#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ -+ -+/* USB.FIFOWP bit masks and bit positions */ -+#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -+#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -+#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -+#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -+#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -+#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -+#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -+#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -+#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -+#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -+#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -+#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ -+ -+/* USB.FIFORP bit masks and bit positions */ -+#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -+#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -+#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -+#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -+#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -+#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -+#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -+#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -+#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -+#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -+#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -+#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ -+ -+/* USB.INTCTRLA bit masks and bit positions */ -+#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -+#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ -+ -+#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -+#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ -+ -+#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -+#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ -+ -+#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -+#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ -+ -+#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* USB.INTCTRLB bit masks and bit positions */ -+#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -+#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ -+ -+#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -+#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ -+ -+/* USB.INTFLAGSACLR bit masks and bit positions */ -+#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -+#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ -+ -+#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -+#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ -+ -+#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -+#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ -+ -+#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -+#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ -+ -+#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -+#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ -+ -+#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -+#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ -+ -+#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -+#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ -+ -+#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -+#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSASET bit masks and bit positions */ -+/* USB_SOFIF Predefined. */ -+/* USB_SOFIF Predefined. */ -+ -+/* USB_SUSPENDIF Predefined. */ -+/* USB_SUSPENDIF Predefined. */ -+ -+/* USB_RESUMEIF Predefined. */ -+/* USB_RESUMEIF Predefined. */ -+ -+/* USB_RSTIF Predefined. */ -+/* USB_RSTIF Predefined. */ -+ -+/* USB_CRCIF Predefined. */ -+/* USB_CRCIF Predefined. */ -+ -+/* USB_UNFIF Predefined. */ -+/* USB_UNFIF Predefined. */ -+ -+/* USB_OVFIF Predefined. */ -+/* USB_OVFIF Predefined. */ -+ -+/* USB_STALLIF Predefined. */ -+/* USB_STALLIF Predefined. */ -+ -+/* USB.INTFLAGSBCLR bit masks and bit positions */ -+#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -+#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ -+ -+#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -+#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSBSET bit masks and bit positions */ -+/* USB_TRNIF Predefined. */ -+/* USB_TRNIF Predefined. */ -+ -+/* USB_SETUPIF Predefined. */ -+/* USB_SETUPIF Predefined. */ -+ -+/* PORT - I/O Port Configuration */ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ -+ -+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -+#define PORT_SPI_bp 5 /* SPI bit position. */ -+ -+#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -+#define PORT_USART0_bp 4 /* USART0 bit position. */ -+ -+#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -+#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ -+ -+#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -+#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ -+ -+#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -+#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ -+ -+#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -+#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ -+ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC0.CTRLA bit masks and bit positions */ -+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC0.CTRLB bit masks and bit positions */ -+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ -+ -+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ -+ -+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC0.CTRLC bit masks and bit positions */ -+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ -+ -+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ -+ -+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC0.CTRLD bit masks and bit positions */ -+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC0_EVACT_gp 5 /* Event Action group position. */ -+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC0.CTRLE bit masks and bit positions */ -+#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC0.INTCTRLA bit masks and bit positions */ -+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC0.INTCTRLB bit masks and bit positions */ -+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ -+ -+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ -+ -+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC0.CTRLFCLR bit masks and bit positions */ -+#define TC0_CMD_gm 0x0C /* Command group mask. */ -+#define TC0_CMD_gp 2 /* Command group position. */ -+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC0_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC0_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC0_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC0.CTRLFSET bit masks and bit positions */ -+/* TC0_CMD Predefined. */ -+/* TC0_CMD Predefined. */ -+ -+/* TC0_LUPD Predefined. */ -+/* TC0_LUPD Predefined. */ -+ -+/* TC0_DIR Predefined. */ -+/* TC0_DIR Predefined. */ -+ -+/* TC0.CTRLGCLR bit masks and bit positions */ -+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ -+ -+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ -+ -+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC0.CTRLGSET bit masks and bit positions */ -+/* TC0_CCDBV Predefined. */ -+/* TC0_CCDBV Predefined. */ -+ -+/* TC0_CCCBV Predefined. */ -+/* TC0_CCCBV Predefined. */ -+ -+/* TC0_CCBBV Predefined. */ -+/* TC0_CCBBV Predefined. */ -+ -+/* TC0_CCABV Predefined. */ -+/* TC0_CCABV Predefined. */ -+ -+/* TC0_PERBV Predefined. */ -+/* TC0_PERBV Predefined. */ -+ -+/* TC0.INTFLAGS bit masks and bit positions */ -+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ -+ -+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ -+ -+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC1.CTRLA bit masks and bit positions */ -+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC1.CTRLB bit masks and bit positions */ -+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC1.CTRLC bit masks and bit positions */ -+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC1.CTRLD bit masks and bit positions */ -+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC1_EVACT_gp 5 /* Event Action group position. */ -+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC1.CTRLE bit masks and bit positions */ -+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ -+ -+/* TC1.INTCTRLA bit masks and bit positions */ -+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC1.INTCTRLB bit masks and bit positions */ -+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC1.CTRLFCLR bit masks and bit positions */ -+#define TC1_CMD_gm 0x0C /* Command group mask. */ -+#define TC1_CMD_gp 2 /* Command group position. */ -+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC1_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC1_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC1_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC1.CTRLFSET bit masks and bit positions */ -+/* TC1_CMD Predefined. */ -+/* TC1_CMD Predefined. */ -+ -+/* TC1_LUPD Predefined. */ -+/* TC1_LUPD Predefined. */ -+ -+/* TC1_DIR Predefined. */ -+/* TC1_DIR Predefined. */ -+ -+/* TC1.CTRLGCLR bit masks and bit positions */ -+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC1.CTRLGSET bit masks and bit positions */ -+/* TC1_CCBBV Predefined. */ -+/* TC1_CCBBV Predefined. */ -+ -+/* TC1_CCABV Predefined. */ -+/* TC1_CCABV Predefined. */ -+ -+/* TC1_PERBV Predefined. */ -+/* TC1_PERBV Predefined. */ -+ -+/* TC1.INTFLAGS bit masks and bit positions */ -+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+/* TC2.CTRLA bit masks and bit positions */ -+#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC2.CTRLB bit masks and bit positions */ -+#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -+#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ -+ -+#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -+#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ -+ -+#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -+#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ -+ -+#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -+#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ -+ -+#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -+#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ -+ -+#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -+#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ -+ -+#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -+#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ -+ -+#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -+#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ -+ -+/* TC2.CTRLC bit masks and bit positions */ -+#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -+#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ -+ -+#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -+#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ -+ -+#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -+#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ -+ -+#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -+#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ -+ -+#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -+#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ -+ -+#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -+#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ -+ -+#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -+#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ -+ -+#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -+#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ -+ -+/* TC2.CTRLE bit masks and bit positions */ -+#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC2.INTCTRLA bit masks and bit positions */ -+#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -+#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -+#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -+#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -+#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -+#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ -+ -+#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -+#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -+#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -+#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -+#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -+#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ -+ -+/* TC2.INTCTRLB bit masks and bit positions */ -+#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -+#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -+#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -+#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -+#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -+#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -+#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -+#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -+#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -+#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -+#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -+#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -+#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -+#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -+#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -+#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -+#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -+#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -+#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -+#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -+#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ -+ -+/* TC2.CTRLF bit masks and bit positions */ -+#define TC2_CMD_gm 0x0C /* Command group mask. */ -+#define TC2_CMD_gp 2 /* Command group position. */ -+#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC2_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -+#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -+#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -+#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -+#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -+#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ -+ -+/* TC2.INTFLAGS bit masks and bit positions */ -+#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -+#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ -+ -+#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -+#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ -+ -+#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -+#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ -+ -+#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -+#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ -+ -+#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ -+ -+#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ -+ -+/* AWEX - Timer/Counter Advanced Waveform Extension */ -+/* AWEX.CTRL bit masks and bit positions */ -+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ -+ -+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ -+ -+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ -+ -+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ -+ -+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ -+ -+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ -+ -+/* AWEX.FDCTRL bit masks and bit positions */ -+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ -+ -+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ -+ -+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ -+ -+/* AWEX.STATUS bit masks and bit positions */ -+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ -+ -+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ -+ -+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ -+ -+/* AWEX.STATUSSET bit masks and bit positions */ -+/* AWEX_FDF Predefined. */ -+/* AWEX_FDF Predefined. */ -+ -+/* AWEX_DTHSBUFV Predefined. */ -+/* AWEX_DTHSBUFV Predefined. */ -+ -+/* AWEX_DTLSBUFV Predefined. */ -+/* AWEX_DTLSBUFV Predefined. */ -+ -+/* HIRES - Timer/Counter High-Resolution Extension */ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -+#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -+#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -+#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -+#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -+#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -+#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -+#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -+#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -+#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -+#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -+#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -+#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -+#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -+#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -+#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -+#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -+#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -+#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ -+ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -+#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -+#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* LOCKBIT - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT0_vect_num 2 -+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -+#define PORTC_INT1_vect_num 3 -+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT0_vect_num 4 -+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -+#define PORTR_INT1_vect_num 5 -+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ -+ -+/* DMA interrupt vectors */ -+#define DMA_CH0_vect_num 6 -+#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -+#define DMA_CH1_vect_num 7 -+#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -+#define DMA_CH2_vect_num 8 -+#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -+#define DMA_CH3_vect_num 9 -+#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ -+ -+/* RTC32 interrupt vectors */ -+#define RTC32_OVF_vect_num 10 -+#define RTC32_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -+#define RTC32_COMP_vect_num 11 -+#define RTC32_COMP_vect _VECTOR(11) /* Compare Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 12 -+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 13 -+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_OVF_vect_num 14 -+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LUNF_vect_num 14 -+#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_ERR_vect_num 15 -+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_HUNF_vect_num 15 -+#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCA_vect_num 16 -+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPA_vect_num 16 -+#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCB_vect_num 17 -+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPB_vect_num 17 -+#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCC_vect_num 18 -+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPC_vect_num 18 -+#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCD_vect_num 19 -+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPD_vect_num 19 -+#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ -+ -+/* TCC1 interrupt vectors */ -+#define TCC1_OVF_vect_num 20 -+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -+#define TCC1_ERR_vect_num 21 -+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -+#define TCC1_CCA_vect_num 22 -+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -+#define TCC1_CCB_vect_num 23 -+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 24 -+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 25 -+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 26 -+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 27 -+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ -+ -+/* USARTC1 interrupt vectors */ -+#define USARTC1_RXC_vect_num 28 -+#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -+#define USARTC1_DRE_vect_num 29 -+#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -+#define USARTC1_TXC_vect_num 30 -+#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ -+ -+/* AES interrupt vectors */ -+#define AES_INT_vect_num 31 -+#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 32 -+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -+#define NVM_SPM_vect_num 33 -+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ -+ -+/* PORTB interrupt vectors */ -+#define PORTB_INT0_vect_num 34 -+#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -+#define PORTB_INT1_vect_num 35 -+#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ -+ -+/* ACB interrupt vectors */ -+#define ACB_AC0_vect_num 36 -+#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ -+#define ACB_AC1_vect_num 37 -+#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ -+#define ACB_ACW_vect_num 38 -+#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ -+ -+/* ADCB interrupt vectors */ -+#define ADCB_CH0_vect_num 39 -+#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ -+#define ADCB_CH1_vect_num 40 -+#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ -+#define ADCB_CH2_vect_num 41 -+#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ -+#define ADCB_CH3_vect_num 42 -+#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ -+ -+/* PORTE interrupt vectors */ -+#define PORTE_INT0_vect_num 43 -+#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -+#define PORTE_INT1_vect_num 44 -+#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ -+ -+/* TWIE interrupt vectors */ -+#define TWIE_TWIS_vect_num 45 -+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -+#define TWIE_TWIM_vect_num 46 -+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_OVF_vect_num 47 -+#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LUNF_vect_num 47 -+#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_ERR_vect_num 48 -+#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_HUNF_vect_num 48 -+#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCA_vect_num 49 -+#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPA_vect_num 49 -+#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCB_vect_num 50 -+#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPB_vect_num 50 -+#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCC_vect_num 51 -+#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPC_vect_num 51 -+#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCD_vect_num 52 -+#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPD_vect_num 52 -+#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ -+ -+/* TCE1 interrupt vectors */ -+#define TCE1_OVF_vect_num 53 -+#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ -+#define TCE1_ERR_vect_num 54 -+#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ -+#define TCE1_CCA_vect_num 55 -+#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ -+#define TCE1_CCB_vect_num 56 -+#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ -+ -+/* USARTE0 interrupt vectors */ -+#define USARTE0_RXC_vect_num 58 -+#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -+#define USARTE0_DRE_vect_num 59 -+#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -+#define USARTE0_TXC_vect_num 60 -+#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT0_vect_num 64 -+#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -+#define PORTD_INT1_vect_num 65 -+#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ -+ -+/* PORTA interrupt vectors */ -+#define PORTA_INT0_vect_num 66 -+#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -+#define PORTA_INT1_vect_num 67 -+#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ -+ -+/* ACA interrupt vectors */ -+#define ACA_AC0_vect_num 68 -+#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -+#define ACA_AC1_vect_num 69 -+#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -+#define ACA_ACW_vect_num 70 -+#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ -+ -+/* ADCA interrupt vectors */ -+#define ADCA_CH0_vect_num 71 -+#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -+#define ADCA_CH1_vect_num 72 -+#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -+#define ADCA_CH2_vect_num 73 -+#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -+#define ADCA_CH3_vect_num 74 -+#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_OVF_vect_num 77 -+#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LUNF_vect_num 77 -+#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_ERR_vect_num 78 -+#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_HUNF_vect_num 78 -+#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCA_vect_num 79 -+#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPA_vect_num 79 -+#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCB_vect_num 80 -+#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPB_vect_num 80 -+#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCC_vect_num 81 -+#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPC_vect_num 81 -+#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCD_vect_num 82 -+#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPD_vect_num 82 -+#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ -+ -+/* TCD1 interrupt vectors */ -+#define TCD1_OVF_vect_num 83 -+#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -+#define TCD1_ERR_vect_num 84 -+#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -+#define TCD1_CCA_vect_num 85 -+#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -+#define TCD1_CCB_vect_num 86 -+#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ -+ -+/* SPID interrupt vectors */ -+#define SPID_INT_vect_num 87 -+#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ -+ -+/* USARTD0 interrupt vectors */ -+#define USARTD0_RXC_vect_num 88 -+#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -+#define USARTD0_DRE_vect_num 89 -+#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -+#define USARTD0_TXC_vect_num 90 -+#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ -+ -+/* USARTD1 interrupt vectors */ -+#define USARTD1_RXC_vect_num 91 -+#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -+#define USARTD1_DRE_vect_num 92 -+#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -+#define USARTD1_TXC_vect_num 93 -+#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ -+ -+/* PORTF interrupt vectors */ -+#define PORTF_INT0_vect_num 104 -+#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -+#define PORTF_INT1_vect_num 105 -+#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_OVF_vect_num 108 -+#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LUNF_vect_num 108 -+#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_ERR_vect_num 109 -+#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_HUNF_vect_num 109 -+#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCA_vect_num 110 -+#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPA_vect_num 110 -+#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCB_vect_num 111 -+#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPB_vect_num 111 -+#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCC_vect_num 112 -+#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPC_vect_num 112 -+#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCD_vect_num 113 -+#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPD_vect_num 113 -+#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ -+ -+/* USARTF0 interrupt vectors */ -+#define USARTF0_RXC_vect_num 119 -+#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ -+#define USARTF0_DRE_vect_num 120 -+#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ -+#define USARTF0_TXC_vect_num 121 -+#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ -+ -+/* USB interrupt vectors */ -+#define USB_BUSEVENT_vect_num 125 -+#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -+#define USB_TRNCOMPL_vect_num 126 -+#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (127 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (270336) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (262144) -+#define APP_SECTION_PAGE_SIZE (512) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0x3E000) -+#define APPTABLE_SECTION_SIZE (8192) -+#define APPTABLE_SECTION_PAGE_SIZE (512) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x40000) -+#define BOOT_SECTION_SIZE (8192) -+#define BOOT_SECTION_PAGE_SIZE (512) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (24576) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (4096) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (16384) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (4096) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (6) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (512) -+#define USER_SIGNATURES_PAGE_SIZE (512) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (52) -+#define PROD_SIGNATURES_PAGE_SIZE (512) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 512 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 6 -+ -+/* Fuse Byte 0 */ -+#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -+#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -+#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -+#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -+#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -+#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -+#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -+#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -+#define FUSE0_DEFAULT (0xFF) -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x98 -+#define SIGNATURE_2 0x43 -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA256A3BU_H_INCLUDED */ -+ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox256a3bu.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA256A3BU_H_INCLUDED ++#define _AVR_ATXMEGA256A3BU_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t USBCTRL; /* USB Control Register */ ++} CLK_t; ++ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t PRPB; /* Power Reduction Port B */ ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++/* USB Prescaler Division Factor */ ++typedef enum CLK_USBPSDIV_enum ++{ ++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ ++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ ++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ ++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ ++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ ++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ ++} CLK_USBPSDIV_t; ++ ++/* USB Clock Source */ ++typedef enum CLK_USBSRC_enum ++{ ++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ ++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ ++} CLK_USBSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 2 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC2MCREF_enum ++{ ++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC2MCREF_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++ register8_t EBIOUT; /* EBI Output register */ ++ register8_t EVOUTSEL; /* Event Output Select */ ++} PORTCFG_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP02MAP_enum ++{ ++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP02MAP_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP13MAP_enum ++{ ++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP13MAP_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Clock and Event Output Port */ ++typedef enum PORTCFG_CLKEVPIN_enum ++{ ++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ ++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ ++} PORTCFG_CLKEVPIN_t; ++ ++/* EBI Address Output Port */ ++typedef enum PORTCFG_EBIADROUT_enum ++{ ++ PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ ++ PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ ++ PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ ++ PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ ++} PORTCFG_EBIADROUT_t; ++ ++/* EBI Chip Select Output Port */ ++typedef enum PORTCFG_EBICSOUT_enum ++{ ++ PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ ++} PORTCFG_EBICSOUT_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ ++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ ++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ ++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ ++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AES - AES Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* AES Module */ ++typedef struct AES_struct ++{ ++ register8_t CTRL; /* AES Control Register */ ++ register8_t STATUS; /* AES Status Register */ ++ register8_t STATE; /* AES State Register */ ++ register8_t KEY; /* AES Key Register */ ++ register8_t INTCTRL; /* AES Interrupt Control Register */ ++} AES_t; ++ ++/* Interrupt level */ ++typedef enum AES_INTLVL_enum ++{ ++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} AES_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ ++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ ++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ ++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++VBAT - Battery Backup Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* Battery Backup Module */ ++typedef struct VBAT_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BACKUP0; /* Backup Register 0 */ ++ register8_t BACKUP1; /* Backup Register 1 */ ++} VBAT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Channel */ ++typedef struct DMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Address Control */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ ++ register8_t REPCNT; /* Channel Repeat Count */ ++ register8_t reserved_0x07; ++ register8_t SRCADDR0; /* Channel Source Address 0 */ ++ register8_t SRCADDR1; /* Channel Source Address 1 */ ++ register8_t SRCADDR2; /* Channel Source Address 2 */ ++ register8_t reserved_0x0B; ++ register8_t DESTADDR0; /* Channel Destination Address 0 */ ++ register8_t DESTADDR1; /* Channel Destination Address 1 */ ++ register8_t DESTADDR2; /* Channel Destination Address 2 */ ++ register8_t reserved_0x0F; ++} DMA_CH_t; ++ ++ ++/* DMA Controller */ ++typedef struct DMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ DMA_CH_t CH0; /* DMA Channel 0 */ ++ DMA_CH_t CH1; /* DMA Channel 1 */ ++ DMA_CH_t CH2; /* DMA Channel 2 */ ++ DMA_CH_t CH3; /* DMA Channel 3 */ ++} DMA_t; ++ ++/* Burst mode */ ++typedef enum DMA_CH_BURSTLEN_enum ++{ ++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ ++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ ++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ ++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ ++} DMA_CH_BURSTLEN_t; ++ ++/* Source address reload mode */ ++typedef enum DMA_CH_SRCRELOAD_enum ++{ ++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ ++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ ++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ ++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ ++} DMA_CH_SRCRELOAD_t; ++ ++/* Source addressing mode */ ++typedef enum DMA_CH_SRCDIR_enum ++{ ++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ ++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ ++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ ++} DMA_CH_SRCDIR_t; ++ ++/* Destination adress reload mode */ ++typedef enum DMA_CH_DESTRELOAD_enum ++{ ++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ ++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ ++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ ++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ ++} DMA_CH_DESTRELOAD_t; ++ ++/* Destination adressing mode */ ++typedef enum DMA_CH_DESTDIR_enum ++{ ++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ ++} DMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum DMA_CH_TRIGSRC_enum ++{ ++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ ++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ ++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ ++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ ++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ ++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ ++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ ++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ ++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ ++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ ++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ ++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ ++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ ++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ ++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ ++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ ++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ ++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ ++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ ++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ ++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ ++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ ++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ ++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ ++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ ++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ ++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ ++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ ++} DMA_CH_TRIGSRC_t; ++ ++/* Double buffering mode */ ++typedef enum DMA_DBUFMODE_enum ++{ ++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ ++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ ++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ ++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ ++} DMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum DMA_PRIMODE_enum ++{ ++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ ++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ ++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ ++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ ++} DMA_PRIMODE_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_ERRINTLVL_enum ++{ ++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ ++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ ++} DMA_CH_ERRINTLVL_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_TRNINTLVL_enum ++{ ++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ ++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ ++} DMA_CH_TRNINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ ++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ ++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ ++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t CH4CTRL; /* Channel 4 Control Register */ ++ register8_t CH5CTRL; /* Channel 5 Control Register */ ++ register8_t CH6CTRL; /* Channel 6 Control Register */ ++ register8_t CH7CTRL; /* Channel 7 Control Register */ ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ ++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ ++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ ++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ ++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ ++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ ++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ ++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ ++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ ++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ ++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ ++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ ++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ ++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ ++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ ++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ ++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ ++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t reserved_0x07; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ _WORDREGISTER(CH1RES); /* Channel 1 Result */ ++ _WORDREGISTER(CH2RES); /* Channel 2 Result */ ++ _WORDREGISTER(CH3RES); /* Channel 3 Result */ ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++ ADC_CH_t CH1; /* ADC Channel 1 */ ++ ADC_CH_t CH2; /* ADC Channel 2 */ ++ ADC_CH_t CH3; /* ADC Channel 3 */ ++} ADC_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ ++ ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ ++ ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ ++ ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Current Limitation Mode */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ ++} ADC_CURRLIMIT_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Channel sweep selection */ ++typedef enum ADC_SWEEP_enum ++{ ++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ ++} ADC_SWEEP_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* DMA request selection */ ++typedef enum ADC_DMASEL_enum ++{ ++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ ++} ADC_DMASEL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DAC - Digital/Analog Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Digital-to-Analog Converter */ ++typedef struct DAC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t EVCTRL; /* Event Input Control */ ++ register8_t reserved_0x04; ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0GAINCAL; /* Gain Calibration */ ++ register8_t CH0OFFSETCAL; /* Offset Calibration */ ++ register8_t CH1GAINCAL; /* Gain Calibration */ ++ register8_t CH1OFFSETCAL; /* Offset Calibration */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ ++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ ++} DAC_t; ++ ++/* Output channel selection */ ++typedef enum DAC_CHSEL_enum ++{ ++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ ++ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ ++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ ++} DAC_CHSEL_t; ++ ++/* Reference voltage selection */ ++typedef enum DAC_REFSEL_enum ++{ ++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ ++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ ++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ ++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ ++} DAC_REFSEL_t; ++ ++/* Event channel selection */ ++typedef enum DAC_EVSEL_enum ++{ ++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ ++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ ++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ ++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ ++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ ++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ ++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ ++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ ++} DAC_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC32 - 32-bit Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* 32-bit Real-Time Counter */ ++typedef struct RTC32_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t SYNCCTRL; /* Synchronization Control/Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _DWORDREGISTER(CNT); /* Count Register */ ++ _DWORDREGISTER(PER); /* Period Register */ ++ _DWORDREGISTER(COMP); /* Compare Register */ ++} RTC32_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC32_COMPINTLVL_enum ++{ ++ RTC32_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC32_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC32_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC32_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC32_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC32_OVFINTLVL_enum ++{ ++ RTC32_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC32_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC32_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC32_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC32_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* SDA Hold Time */ ++typedef enum TWI_SDAHOLD_enum ++{ ++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ ++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ ++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ ++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ ++} TWI_SDAHOLD_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USB - USB ++-------------------------------------------------------------------------- ++*/ ++ ++/* USB Endpoint */ ++typedef struct USB_EP_struct ++{ ++ register8_t STATUS; /* Endpoint Status */ ++ register8_t CTRL; /* Endpoint Control */ ++ _WORDREGISTER(CNT); /* USB Endpoint Counter */ ++ _WORDREGISTER(DATAPTR); /* Data Pointer */ ++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ ++} USB_EP_t; ++ ++ ++/* Universal Serial Bus */ ++typedef struct USB_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t FIFOWP; /* FIFO Write Pointer Register */ ++ register8_t FIFORP; /* FIFO Read Pointer Register */ ++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ ++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ ++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ ++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t reserved_0x20; ++ register8_t reserved_0x21; ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t CAL0; /* Calibration Byte 0 */ ++ register8_t CAL1; /* Calibration Byte 1 */ ++} USB_t; ++ ++ ++/* USB Endpoint Table */ ++typedef struct USB_EP_TABLE_struct ++{ ++ USB_EP_t EP0OUT; /* Endpoint 0 */ ++ USB_EP_t EP0IN; /* Endpoint 0 */ ++ USB_EP_t EP1OUT; /* Endpoint 1 */ ++ USB_EP_t EP1IN; /* Endpoint 1 */ ++ USB_EP_t EP2OUT; /* Endpoint 2 */ ++ USB_EP_t EP2IN; /* Endpoint 2 */ ++ USB_EP_t EP3OUT; /* Endpoint 3 */ ++ USB_EP_t EP3IN; /* Endpoint 3 */ ++ USB_EP_t EP4OUT; /* Endpoint 4 */ ++ USB_EP_t EP4IN; /* Endpoint 4 */ ++ USB_EP_t EP5OUT; /* Endpoint 5 */ ++ USB_EP_t EP5IN; /* Endpoint 5 */ ++ USB_EP_t EP6OUT; /* Endpoint 6 */ ++ USB_EP_t EP6IN; /* Endpoint 6 */ ++ USB_EP_t EP7OUT; /* Endpoint 7 */ ++ USB_EP_t EP7IN; /* Endpoint 7 */ ++ USB_EP_t EP8OUT; /* Endpoint 8 */ ++ USB_EP_t EP8IN; /* Endpoint 8 */ ++ USB_EP_t EP9OUT; /* Endpoint 9 */ ++ USB_EP_t EP9IN; /* Endpoint 9 */ ++ USB_EP_t EP10OUT; /* Endpoint 10 */ ++ USB_EP_t EP10IN; /* Endpoint 10 */ ++ USB_EP_t EP11OUT; /* Endpoint 11 */ ++ USB_EP_t EP11IN; /* Endpoint 11 */ ++ USB_EP_t EP12OUT; /* Endpoint 12 */ ++ USB_EP_t EP12IN; /* Endpoint 12 */ ++ USB_EP_t EP13OUT; /* Endpoint 13 */ ++ USB_EP_t EP13IN; /* Endpoint 13 */ ++ USB_EP_t EP14OUT; /* Endpoint 14 */ ++ USB_EP_t EP14IN; /* Endpoint 14 */ ++ USB_EP_t EP15OUT; /* Endpoint 15 */ ++ USB_EP_t EP15IN; /* Endpoint 15 */ ++ register8_t reserved_0x100; ++ register8_t reserved_0x101; ++ register8_t reserved_0x102; ++ register8_t reserved_0x103; ++ register8_t reserved_0x104; ++ register8_t reserved_0x105; ++ register8_t reserved_0x106; ++ register8_t reserved_0x107; ++ register8_t reserved_0x108; ++ register8_t reserved_0x109; ++ register8_t reserved_0x10A; ++ register8_t reserved_0x10B; ++ register8_t reserved_0x10C; ++ register8_t reserved_0x10D; ++ register8_t reserved_0x10E; ++ register8_t reserved_0x10F; ++ register8_t FRAMENUML; /* Frame Number Low Byte */ ++ register8_t FRAMENUMH; /* Frame Number High Byte */ ++} USB_EP_TABLE_t; ++ ++/* Interrupt level */ ++typedef enum USB_INTLVL_enum ++{ ++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} USB_INTLVL_t; ++ ++/* USB Endpoint Type */ ++typedef enum USB_EP_TYPE_enum ++{ ++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ ++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ ++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ ++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ ++} USB_EP_TYPE_t; ++ ++/* USB Endpoint Buffersize */ ++typedef enum USB_EP_BUFSIZE_enum ++{ ++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ ++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ ++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ ++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ ++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ ++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ ++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ ++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ ++} USB_EP_BUFSIZE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - I/O Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* I/O Port Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Byte Mode */ ++typedef enum TC_BYTEM_enum ++{ ++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ ++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ ++} TC_BYTEM_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC2 - 16-bit Timer/Counter type 2 ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter type 2 */ ++typedef struct TC2_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t reserved_0x03; ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t reserved_0x08; ++ register8_t CTRLF; /* Control Register F */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t LCNT; /* Low Byte Count */ ++ register8_t HCNT; /* High Byte Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t LPER; /* Low Byte Period */ ++ register8_t HPER; /* High Byte Period */ ++ register8_t LCMPA; /* Low Byte Compare A */ ++ register8_t HCMPA; /* High Byte Compare A */ ++ register8_t LCMPB; /* Low Byte Compare B */ ++ register8_t HCMPB; /* High Byte Compare B */ ++ register8_t LCMPC; /* Low Byte Compare C */ ++ register8_t HCMPC; /* High Byte Compare C */ ++ register8_t LCMPD; /* Low Byte Compare D */ ++ register8_t HCMPD; /* High Byte Compare D */ ++} TC2_t; ++ ++/* Clock Selection */ ++typedef enum TC2_CLKSEL_enum ++{ ++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC2_CLKSEL_t; ++ ++/* Byte Mode */ ++typedef enum TC2_BYTEM_enum ++{ ++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ ++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ ++} TC2_BYTEM_t; ++ ++/* High Byte Underflow Interrupt Level */ ++typedef enum TC2_HUNFINTLVL_enum ++{ ++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_HUNFINTLVL_t; ++ ++/* Low Byte Underflow Interrupt Level */ ++typedef enum TC2_LUNFINTLVL_enum ++{ ++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LUNFINTLVL_t; ++ ++/* Low Byte Compare D Interrupt Level */ ++typedef enum TC2_LCMPDINTLVL_enum ++{ ++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC2_LCMPDINTLVL_t; ++ ++/* Low Byte Compare C Interrupt Level */ ++typedef enum TC2_LCMPCINTLVL_enum ++{ ++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC2_LCMPCINTLVL_t; ++ ++/* Low Byte Compare B Interrupt Level */ ++typedef enum TC2_LCMPBINTLVL_enum ++{ ++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_LCMPBINTLVL_t; ++ ++/* Low Byte Compare A Interrupt Level */ ++typedef enum TC2_LCMPAINTLVL_enum ++{ ++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LCMPAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMD_enum ++{ ++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC2_CMD_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMDEN_enum ++{ ++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ ++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ ++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ ++} TC2_CMDEN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AWEX - Timer/Counter Advanced Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - Timer/Counter High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t FUSEBYTE0; /* JTAG User ID */ ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* Timer Oscillator pin location */ ++typedef enum TOSCSEL_enum ++{ ++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ ++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ ++} TOSCSEL_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* BOD operation */ ++typedef enum BODACT_enum ++{ ++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BODACT_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WDP_enum ++{ ++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ ++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ ++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ ++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ ++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ ++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ ++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ ++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ ++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ ++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ ++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ ++} WDP_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LOCKBIT - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ ++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t USBCAL0; /* USB Calibration Byte 0 */ ++ register8_t USBCAL1; /* USB Calibration Byte 1 */ ++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ ++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ ++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ ++ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ ++ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ ++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ ++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ ++ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ ++ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++ register8_t reserved_0x40; ++ register8_t reserved_0x41; ++ register8_t reserved_0x42; ++ register8_t reserved_0x43; ++ register8_t reserved_0x44; ++ register8_t reserved_0x45; ++ register8_t reserved_0x46; ++ register8_t reserved_0x47; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define AES (*(AES_t *) 0x00C0) /* AES Module */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define VBAT (*(VBAT_t *) 0x00F0) /* Battery Backup Module */ ++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ ++#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ ++#define RTC32 (*(RTC32_t *) 0x0420) /* 32-bit Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ ++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ ++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ ++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ ++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ ++#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ ++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ ++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ ++#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ ++#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ ++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ ++#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ ++#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ ++#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++#define GPIO_GPIOR4 _SFR_MEM8(0x0004) ++#define GPIO_GPIOR5 _SFR_MEM8(0x0005) ++#define GPIO_GPIOR6 _SFR_MEM8(0x0006) ++#define GPIO_GPIOR7 _SFR_MEM8(0x0007) ++#define GPIO_GPIOR8 _SFR_MEM8(0x0008) ++#define GPIO_GPIOR9 _SFR_MEM8(0x0009) ++#define GPIO_GPIORA _SFR_MEM8(0x000A) ++#define GPIO_GPIORB _SFR_MEM8(0x000B) ++#define GPIO_GPIORC _SFR_MEM8(0x000C) ++#define GPIO_GPIORD _SFR_MEM8(0x000D) ++#define GPIO_GPIORE _SFR_MEM8(0x000E) ++#define GPIO_GPIORF _SFR_MEM8(0x000F) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++#define GPIO_GPIO4 _SFR_MEM8(0x0004) ++#define GPIO_GPIO5 _SFR_MEM8(0x0005) ++#define GPIO_GPIO6 _SFR_MEM8(0x0006) ++#define GPIO_GPIO7 _SFR_MEM8(0x0007) ++#define GPIO_GPIO8 _SFR_MEM8(0x0008) ++#define GPIO_GPIO9 _SFR_MEM8(0x0009) ++#define GPIO_GPIOA _SFR_MEM8(0x000A) ++#define GPIO_GPIOB _SFR_MEM8(0x000B) ++#define GPIO_GPIOC _SFR_MEM8(0x000C) ++#define GPIO_GPIOD _SFR_MEM8(0x000D) ++#define GPIO_GPIOE _SFR_MEM8(0x000E) ++#define GPIO_GPIOF _SFR_MEM8(0x000F) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) ++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) ++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) ++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) ++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) ++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) ++#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) ++#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) ++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) ++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) ++#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) ++#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++#define CLK_USBCTRL _SFR_MEM8(0x0044) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLL - DFLL */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPB _SFR_MEM8(0x0072) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) ++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) ++ ++/* AES - AES Module */ ++#define AES_CTRL _SFR_MEM8(0x00C0) ++#define AES_STATUS _SFR_MEM8(0x00C1) ++#define AES_STATE _SFR_MEM8(0x00C2) ++#define AES_KEY _SFR_MEM8(0x00C3) ++#define AES_INTCTRL _SFR_MEM8(0x00C4) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* VBAT - Battery Backup Module */ ++#define VBAT_CTRL _SFR_MEM8(0x00F0) ++#define VBAT_STATUS _SFR_MEM8(0x00F1) ++#define VBAT_BACKUP0 _SFR_MEM8(0x00F2) ++#define VBAT_BACKUP1 _SFR_MEM8(0x00F3) ++ ++/* DMA - DMA Controller */ ++#define DMA_CTRL _SFR_MEM8(0x0100) ++#define DMA_INTFLAGS _SFR_MEM8(0x0103) ++#define DMA_STATUS _SFR_MEM8(0x0104) ++#define DMA_TEMP _SFR_MEM16(0x0106) ++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) ++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) ++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) ++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) ++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) ++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) ++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) ++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) ++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) ++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) ++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) ++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) ++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) ++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) ++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) ++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) ++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) ++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) ++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) ++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) ++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) ++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) ++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) ++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) ++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) ++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) ++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) ++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) ++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) ++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) ++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) ++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) ++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) ++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) ++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) ++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) ++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) ++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) ++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) ++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) ++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) ++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH4MUX _SFR_MEM8(0x0184) ++#define EVSYS_CH5MUX _SFR_MEM8(0x0185) ++#define EVSYS_CH6MUX _SFR_MEM8(0x0186) ++#define EVSYS_CH7MUX _SFR_MEM8(0x0187) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) ++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) ++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) ++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CH1RES _SFR_MEM16(0x0212) ++#define ADCA_CH2RES _SFR_MEM16(0x0214) ++#define ADCA_CH3RES _SFR_MEM16(0x0216) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) ++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) ++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) ++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) ++#define ADCA_CH1_RES _SFR_MEM16(0x022C) ++#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) ++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) ++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) ++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) ++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) ++#define ADCA_CH2_RES _SFR_MEM16(0x0234) ++#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) ++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) ++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) ++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) ++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) ++#define ADCA_CH3_RES _SFR_MEM16(0x023C) ++#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCB_CTRLA _SFR_MEM8(0x0240) ++#define ADCB_CTRLB _SFR_MEM8(0x0241) ++#define ADCB_REFCTRL _SFR_MEM8(0x0242) ++#define ADCB_EVCTRL _SFR_MEM8(0x0243) ++#define ADCB_PRESCALER _SFR_MEM8(0x0244) ++#define ADCB_INTFLAGS _SFR_MEM8(0x0246) ++#define ADCB_TEMP _SFR_MEM8(0x0247) ++#define ADCB_CAL _SFR_MEM16(0x024C) ++#define ADCB_CH0RES _SFR_MEM16(0x0250) ++#define ADCB_CH1RES _SFR_MEM16(0x0252) ++#define ADCB_CH2RES _SFR_MEM16(0x0254) ++#define ADCB_CH3RES _SFR_MEM16(0x0256) ++#define ADCB_CMP _SFR_MEM16(0x0258) ++#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) ++#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) ++#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) ++#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) ++#define ADCB_CH0_RES _SFR_MEM16(0x0264) ++#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) ++#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) ++#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) ++#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) ++#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) ++#define ADCB_CH1_RES _SFR_MEM16(0x026C) ++#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) ++#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) ++#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) ++#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) ++#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) ++#define ADCB_CH2_RES _SFR_MEM16(0x0274) ++#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) ++#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) ++#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) ++#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) ++#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) ++#define ADCB_CH3_RES _SFR_MEM16(0x027C) ++#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) ++ ++/* DAC - Digital-to-Analog Converter */ ++#define DACB_CTRLA _SFR_MEM8(0x0320) ++#define DACB_CTRLB _SFR_MEM8(0x0321) ++#define DACB_CTRLC _SFR_MEM8(0x0322) ++#define DACB_EVCTRL _SFR_MEM8(0x0323) ++#define DACB_STATUS _SFR_MEM8(0x0325) ++#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) ++#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) ++#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) ++#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) ++#define DACB_CH0DATA _SFR_MEM16(0x0338) ++#define DACB_CH1DATA _SFR_MEM16(0x033A) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* AC - Analog Comparator */ ++#define ACB_AC0CTRL _SFR_MEM8(0x0390) ++#define ACB_AC1CTRL _SFR_MEM8(0x0391) ++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) ++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) ++#define ACB_CTRLA _SFR_MEM8(0x0394) ++#define ACB_CTRLB _SFR_MEM8(0x0395) ++#define ACB_WINCTRL _SFR_MEM8(0x0396) ++#define ACB_STATUS _SFR_MEM8(0x0397) ++ ++/* RTC32 - 32-bit Real-Time Counter */ ++#define RTC32_CTRL _SFR_MEM8(0x0420) ++#define RTC32_SYNCCTRL _SFR_MEM8(0x0421) ++#define RTC32_INTCTRL _SFR_MEM8(0x0422) ++#define RTC32_INTFLAGS _SFR_MEM8(0x0423) ++#define RTC32_CNT _SFR_MEM32(0x0424) ++#define RTC32_PER _SFR_MEM32(0x0428) ++#define RTC32_COMP _SFR_MEM32(0x042C) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* USB - Universal Serial Bus */ ++#define USB_CTRLA _SFR_MEM8(0x04C0) ++#define USB_CTRLB _SFR_MEM8(0x04C1) ++#define USB_STATUS _SFR_MEM8(0x04C2) ++#define USB_ADDR _SFR_MEM8(0x04C3) ++#define USB_FIFOWP _SFR_MEM8(0x04C4) ++#define USB_FIFORP _SFR_MEM8(0x04C5) ++#define USB_EPPTR _SFR_MEM16(0x04C6) ++#define USB_INTCTRLA _SFR_MEM8(0x04C8) ++#define USB_INTCTRLB _SFR_MEM8(0x04C9) ++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) ++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) ++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) ++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) ++#define USB_CAL0 _SFR_MEM8(0x04FA) ++#define USB_CAL1 _SFR_MEM8(0x04FB) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_REMAP _SFR_MEM8(0x060E) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_REMAP _SFR_MEM8(0x062E) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_REMAP _SFR_MEM8(0x068E) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORT - I/O Ports */ ++#define PORTF_DIR _SFR_MEM8(0x06A0) ++#define PORTF_DIRSET _SFR_MEM8(0x06A1) ++#define PORTF_DIRCLR _SFR_MEM8(0x06A2) ++#define PORTF_DIRTGL _SFR_MEM8(0x06A3) ++#define PORTF_OUT _SFR_MEM8(0x06A4) ++#define PORTF_OUTSET _SFR_MEM8(0x06A5) ++#define PORTF_OUTCLR _SFR_MEM8(0x06A6) ++#define PORTF_OUTTGL _SFR_MEM8(0x06A7) ++#define PORTF_IN _SFR_MEM8(0x06A8) ++#define PORTF_INTCTRL _SFR_MEM8(0x06A9) ++#define PORTF_INT0MASK _SFR_MEM8(0x06AA) ++#define PORTF_INT1MASK _SFR_MEM8(0x06AB) ++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) ++#define PORTF_REMAP _SFR_MEM8(0x06AE) ++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) ++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) ++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) ++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) ++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) ++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) ++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) ++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCC2_CTRLA _SFR_MEM8(0x0800) ++#define TCC2_CTRLB _SFR_MEM8(0x0801) ++#define TCC2_CTRLC _SFR_MEM8(0x0802) ++#define TCC2_CTRLE _SFR_MEM8(0x0804) ++#define TCC2_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC2_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC2_CTRLF _SFR_MEM8(0x0809) ++#define TCC2_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC2_LCNT _SFR_MEM8(0x0820) ++#define TCC2_HCNT _SFR_MEM8(0x0821) ++#define TCC2_LPER _SFR_MEM8(0x0826) ++#define TCC2_HPER _SFR_MEM8(0x0827) ++#define TCC2_LCMPA _SFR_MEM8(0x0828) ++#define TCC2_HCMPA _SFR_MEM8(0x0829) ++#define TCC2_LCMPB _SFR_MEM8(0x082A) ++#define TCC2_HCMPB _SFR_MEM8(0x082B) ++#define TCC2_LCMPC _SFR_MEM8(0x082C) ++#define TCC2_HCMPC _SFR_MEM8(0x082D) ++#define TCC2_LCMPD _SFR_MEM8(0x082E) ++#define TCC2_HCMPD _SFR_MEM8(0x082F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_STATUSSET _SFR_MEM8(0x0885) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1_DATA _SFR_MEM8(0x08B0) ++#define USARTC1_STATUS _SFR_MEM8(0x08B1) ++#define USARTC1_CTRLA _SFR_MEM8(0x08B3) ++#define USARTC1_CTRLB _SFR_MEM8(0x08B4) ++#define USARTC1_CTRLC _SFR_MEM8(0x08B5) ++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) ++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCD2_CTRLA _SFR_MEM8(0x0900) ++#define TCD2_CTRLB _SFR_MEM8(0x0901) ++#define TCD2_CTRLC _SFR_MEM8(0x0902) ++#define TCD2_CTRLE _SFR_MEM8(0x0904) ++#define TCD2_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD2_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD2_CTRLF _SFR_MEM8(0x0909) ++#define TCD2_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD2_LCNT _SFR_MEM8(0x0920) ++#define TCD2_HCNT _SFR_MEM8(0x0921) ++#define TCD2_LPER _SFR_MEM8(0x0926) ++#define TCD2_HPER _SFR_MEM8(0x0927) ++#define TCD2_LCMPA _SFR_MEM8(0x0928) ++#define TCD2_HCMPA _SFR_MEM8(0x0929) ++#define TCD2_LCMPB _SFR_MEM8(0x092A) ++#define TCD2_HCMPB _SFR_MEM8(0x092B) ++#define TCD2_LCMPC _SFR_MEM8(0x092C) ++#define TCD2_HCMPC _SFR_MEM8(0x092D) ++#define TCD2_LCMPD _SFR_MEM8(0x092E) ++#define TCD2_HCMPD _SFR_MEM8(0x092F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCD1_CTRLA _SFR_MEM8(0x0940) ++#define TCD1_CTRLB _SFR_MEM8(0x0941) ++#define TCD1_CTRLC _SFR_MEM8(0x0942) ++#define TCD1_CTRLD _SFR_MEM8(0x0943) ++#define TCD1_CTRLE _SFR_MEM8(0x0944) ++#define TCD1_INTCTRLA _SFR_MEM8(0x0946) ++#define TCD1_INTCTRLB _SFR_MEM8(0x0947) ++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) ++#define TCD1_CTRLFSET _SFR_MEM8(0x0949) ++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) ++#define TCD1_CTRLGSET _SFR_MEM8(0x094B) ++#define TCD1_INTFLAGS _SFR_MEM8(0x094C) ++#define TCD1_TEMP _SFR_MEM8(0x094F) ++#define TCD1_CNT _SFR_MEM16(0x0960) ++#define TCD1_PER _SFR_MEM16(0x0966) ++#define TCD1_CCA _SFR_MEM16(0x0968) ++#define TCD1_CCB _SFR_MEM16(0x096A) ++#define TCD1_PERBUF _SFR_MEM16(0x0976) ++#define TCD1_CCABUF _SFR_MEM16(0x0978) ++#define TCD1_CCBBUF _SFR_MEM16(0x097A) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESD_CTRLA _SFR_MEM8(0x0990) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD1_DATA _SFR_MEM8(0x09B0) ++#define USARTD1_STATUS _SFR_MEM8(0x09B1) ++#define USARTD1_CTRLA _SFR_MEM8(0x09B3) ++#define USARTD1_CTRLB _SFR_MEM8(0x09B4) ++#define USARTD1_CTRLC _SFR_MEM8(0x09B5) ++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) ++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCE2_CTRLA _SFR_MEM8(0x0A00) ++#define TCE2_CTRLB _SFR_MEM8(0x0A01) ++#define TCE2_CTRLC _SFR_MEM8(0x0A02) ++#define TCE2_CTRLE _SFR_MEM8(0x0A04) ++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE2_CTRLF _SFR_MEM8(0x0A09) ++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE2_LCNT _SFR_MEM8(0x0A20) ++#define TCE2_HCNT _SFR_MEM8(0x0A21) ++#define TCE2_LPER _SFR_MEM8(0x0A26) ++#define TCE2_HPER _SFR_MEM8(0x0A27) ++#define TCE2_LCMPA _SFR_MEM8(0x0A28) ++#define TCE2_HCMPA _SFR_MEM8(0x0A29) ++#define TCE2_LCMPB _SFR_MEM8(0x0A2A) ++#define TCE2_HCMPB _SFR_MEM8(0x0A2B) ++#define TCE2_LCMPC _SFR_MEM8(0x0A2C) ++#define TCE2_HCMPC _SFR_MEM8(0x0A2D) ++#define TCE2_LCMPD _SFR_MEM8(0x0A2E) ++#define TCE2_HCMPD _SFR_MEM8(0x0A2F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCE1_CTRLA _SFR_MEM8(0x0A40) ++#define TCE1_CTRLB _SFR_MEM8(0x0A41) ++#define TCE1_CTRLC _SFR_MEM8(0x0A42) ++#define TCE1_CTRLD _SFR_MEM8(0x0A43) ++#define TCE1_CTRLE _SFR_MEM8(0x0A44) ++#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) ++#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) ++#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) ++#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) ++#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) ++#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) ++#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) ++#define TCE1_TEMP _SFR_MEM8(0x0A4F) ++#define TCE1_CNT _SFR_MEM16(0x0A60) ++#define TCE1_PER _SFR_MEM16(0x0A66) ++#define TCE1_CCA _SFR_MEM16(0x0A68) ++#define TCE1_CCB _SFR_MEM16(0x0A6A) ++#define TCE1_PERBUF _SFR_MEM16(0x0A76) ++#define TCE1_CCABUF _SFR_MEM16(0x0A78) ++#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXE_CTRL _SFR_MEM8(0x0A80) ++#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) ++#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) ++#define AWEXE_STATUS _SFR_MEM8(0x0A84) ++#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) ++#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) ++#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) ++#define AWEXE_DTLS _SFR_MEM8(0x0A88) ++#define AWEXE_DTHS _SFR_MEM8(0x0A89) ++#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) ++#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) ++#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESE_CTRLA _SFR_MEM8(0x0A90) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCF0_CTRLA _SFR_MEM8(0x0B00) ++#define TCF0_CTRLB _SFR_MEM8(0x0B01) ++#define TCF0_CTRLC _SFR_MEM8(0x0B02) ++#define TCF0_CTRLD _SFR_MEM8(0x0B03) ++#define TCF0_CTRLE _SFR_MEM8(0x0B04) ++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) ++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) ++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) ++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) ++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF0_TEMP _SFR_MEM8(0x0B0F) ++#define TCF0_CNT _SFR_MEM16(0x0B20) ++#define TCF0_PER _SFR_MEM16(0x0B26) ++#define TCF0_CCA _SFR_MEM16(0x0B28) ++#define TCF0_CCB _SFR_MEM16(0x0B2A) ++#define TCF0_CCC _SFR_MEM16(0x0B2C) ++#define TCF0_CCD _SFR_MEM16(0x0B2E) ++#define TCF0_PERBUF _SFR_MEM16(0x0B36) ++#define TCF0_CCABUF _SFR_MEM16(0x0B38) ++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) ++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) ++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCF2_CTRLA _SFR_MEM8(0x0B00) ++#define TCF2_CTRLB _SFR_MEM8(0x0B01) ++#define TCF2_CTRLC _SFR_MEM8(0x0B02) ++#define TCF2_CTRLE _SFR_MEM8(0x0B04) ++#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF2_CTRLF _SFR_MEM8(0x0B09) ++#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF2_LCNT _SFR_MEM8(0x0B20) ++#define TCF2_HCNT _SFR_MEM8(0x0B21) ++#define TCF2_LPER _SFR_MEM8(0x0B26) ++#define TCF2_HPER _SFR_MEM8(0x0B27) ++#define TCF2_LCMPA _SFR_MEM8(0x0B28) ++#define TCF2_HCMPA _SFR_MEM8(0x0B29) ++#define TCF2_LCMPB _SFR_MEM8(0x0B2A) ++#define TCF2_HCMPB _SFR_MEM8(0x0B2B) ++#define TCF2_LCMPC _SFR_MEM8(0x0B2C) ++#define TCF2_HCMPC _SFR_MEM8(0x0B2D) ++#define TCF2_LCMPD _SFR_MEM8(0x0B2E) ++#define TCF2_HCMPD _SFR_MEM8(0x0B2F) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESF_CTRLA _SFR_MEM8(0x0B90) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTF0_DATA _SFR_MEM8(0x0BA0) ++#define USARTF0_STATUS _SFR_MEM8(0x0BA1) ++#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) ++#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) ++#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) ++#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) ++#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* CLK.USBCTRL bit masks and bit positions */ ++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ ++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ ++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ ++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ ++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ ++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ ++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ ++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ ++ ++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ ++#define CLK_USBSRC_gp 1 /* Clock Source group position. */ ++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ ++ ++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_USB_bm 0x40 /* USB bit mask. */ ++#define PR_USB_bp 6 /* USB bit position. */ ++ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ ++#define PR_EBI_bp 3 /* External Bus Interface bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ ++#define PR_DAC_bp 2 /* Port A DAC bit position. */ ++ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPB bit masks and bit positions */ ++/* PR_DAC Predefined. */ ++/* PR_DAC Predefined. */ ++ ++/* PR_ADC Predefined. */ ++/* PR_ADC Predefined. */ ++ ++/* PR_AC Predefined. */ ++/* PR_AC Predefined. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ ++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ ++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ ++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ ++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ ++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ ++ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ ++#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ ++ ++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ ++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ ++ ++#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ ++#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ ++ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ ++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ ++ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ ++ ++/* PORTCFG.EBIOUT bit masks and bit positions */ ++#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ ++#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ ++#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ ++#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ ++#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ ++#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ ++ ++#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ ++#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ ++#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ ++#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ ++#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ ++#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ ++ ++/* PORTCFG.EVOUTSEL bit masks and bit positions */ ++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ ++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ ++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ ++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ ++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ ++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ ++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ ++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ ++ ++/* AES - AES Module */ ++/* AES.CTRL bit masks and bit positions */ ++#define AES_START_bm 0x80 /* Start/Run bit mask. */ ++#define AES_START_bp 7 /* Start/Run bit position. */ ++ ++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ ++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ ++ ++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ ++#define AES_RESET_bp 5 /* AES Software Reset bit position. */ ++ ++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ ++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ ++ ++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ ++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ ++ ++/* AES.STATUS bit masks and bit positions */ ++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ ++#define AES_ERROR_bp 7 /* AES Error bit position. */ ++ ++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ ++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ ++ ++/* AES.INTCTRL bit masks and bit positions */ ++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define AES_INTLVL_gp 0 /* Interrupt level group position. */ ++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* VBAT - Battery Backup Module */ ++/* VBAT.CTRL bit masks and bit positions */ ++#define VBAT_HIGHESR_bm 0x20 /* 32-kHz Crystal Oscillator High Power Mode bit mask. */ ++#define VBAT_HIGHESR_bp 5 /* 32-kHz Crystal Oscillator High Power Mode bit position. */ ++ ++#define VBAT_XOSCSEL_bm 0x10 /* 32-kHz Crystal Oscillator Output Selection bit mask. */ ++#define VBAT_XOSCSEL_bp 4 /* 32-kHz Crystal Oscillator Output Selection bit position. */ ++ ++#define VBAT_XOSCEN_bm 0x08 /* Crystal Oscillator Enable bit mask. */ ++#define VBAT_XOSCEN_bp 3 /* Crystal Oscillator Enable bit position. */ ++ ++#define VBAT_XOSCFDEN_bm 0x04 /* Crystal Oscillator Failure Detection Monitor Enable bit mask. */ ++#define VBAT_XOSCFDEN_bp 2 /* Crystal Oscillator Failure Detection Monitor Enable bit position. */ ++ ++#define VBAT_ACCEN_bm 0x02 /* Access Enable bit mask. */ ++#define VBAT_ACCEN_bp 1 /* Access Enable bit position. */ ++ ++#define VBAT_RESET_bm 0x01 /* Reset bit mask. */ ++#define VBAT_RESET_bp 0 /* Reset bit position. */ ++ ++/* VBAT.STATUS bit masks and bit positions */ ++#define VBAT_BBPWR_bm 0x80 /* Battery backup Power bit mask. */ ++#define VBAT_BBPWR_bp 7 /* Battery backup Power bit position. */ ++ ++#define VBAT_XOSCRDY_bm 0x08 /* Crystal Oscillator Ready bit mask. */ ++#define VBAT_XOSCRDY_bp 3 /* Crystal Oscillator Ready bit position. */ ++ ++#define VBAT_XOSCFAIL_bm 0x04 /* Crystal Oscillator Failure bit mask. */ ++#define VBAT_XOSCFAIL_bp 2 /* Crystal Oscillator Failure bit position. */ ++ ++#define VBAT_BBBORF_bm 0x02 /* Battery Backup Brown-Out Reset Flag bit mask. */ ++#define VBAT_BBBORF_bp 1 /* Battery Backup Brown-Out Reset Flag bit position. */ ++ ++#define VBAT_BBPORF_bm 0x01 /* Battery Backup Power-On Reset Flag bit mask. */ ++#define VBAT_BBPORF_bp 0 /* Battery Backup Power-On Reset Flag bit position. */ ++ ++/* DMA - DMA Controller */ ++/* DMA_CH.CTRLA bit masks and bit positions */ ++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ ++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ ++ ++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ ++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ ++ ++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ ++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ ++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ ++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ ++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ ++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ ++ ++/* DMA_CH.CTRLB bit masks and bit positions */ ++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ ++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ ++ ++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ ++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ ++ ++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ ++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ ++ ++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ ++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ ++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ ++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ ++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ ++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ ++ ++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ ++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ ++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ ++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ ++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ ++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ ++ ++/* DMA_CH.ADDRCTRL bit masks and bit positions */ ++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ ++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ ++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ ++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ ++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ ++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ ++ ++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ ++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ ++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ ++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ ++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ ++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ ++ ++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ ++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ ++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ ++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ ++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ ++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ ++ ++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ ++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ ++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ ++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ ++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ ++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ ++ ++/* DMA_CH.TRIGSRC bit masks and bit positions */ ++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++/* DMA.CTRL bit masks and bit positions */ ++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define DMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define DMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ ++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ ++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ ++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ ++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ ++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ ++ ++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ ++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ ++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ ++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ ++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ ++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ ++ ++/* DMA.INTFLAGS bit masks and bit positions */ ++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++/* DMA.STATUS bit masks and bit positions */ ++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ ++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ ++ ++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ ++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ ++ ++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ ++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ ++ ++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ ++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ ++ ++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ ++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ ++ ++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ ++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ ++ ++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ ++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ ++ ++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ ++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH4MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH5MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH6MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH7MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM Predefined. */ ++/* EVSYS_QDIRM Predefined. */ ++ ++/* EVSYS_QDIEN Predefined. */ ++/* EVSYS_QDIEN Predefined. */ ++ ++/* EVSYS_QDEN Predefined. */ ++/* EVSYS_QDEN Predefined. */ ++ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH4CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM Predefined. */ ++/* EVSYS_QDIRM Predefined. */ ++ ++/* EVSYS_QDIEN Predefined. */ ++/* EVSYS_QDIEN Predefined. */ ++ ++/* EVSYS_QDEN Predefined. */ ++/* EVSYS_QDEN Predefined. */ ++ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH5CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH6CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH7CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ ++#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ ++#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ ++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ ++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ ++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ ++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ ++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ ++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ ++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ ++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ ++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ ++ ++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ ++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ ++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ ++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ ++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ ++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ ++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ ++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ ++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ ++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ ++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ ++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ ++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ ++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ ++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ ++ ++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ ++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ ++ ++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ ++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ ++ ++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ ++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ ++ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ ++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ ++#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ ++ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ ++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ ++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ ++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ ++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ ++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ ++ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ ++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ ++ ++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ ++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ ++ ++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ ++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ ++ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* DAC - Digital/Analog Converter */ ++/* DAC.CTRLA bit masks and bit positions */ ++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ ++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ ++ ++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ ++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ ++ ++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ ++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ ++ ++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ ++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ ++ ++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define DAC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* DAC.CTRLB bit masks and bit positions */ ++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ ++#define DAC_CHSEL_gp 5 /* Channel Select group position. */ ++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ ++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ ++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ ++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ ++ ++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ ++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ ++ ++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ ++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ ++ ++/* DAC.CTRLC bit masks and bit positions */ ++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ ++#define DAC_REFSEL_gp 3 /* Reference Select group position. */ ++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ ++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ ++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ ++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ ++ ++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ ++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ ++ ++/* DAC.EVCTRL bit masks and bit positions */ ++#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ ++#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ ++ ++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ ++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ ++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ ++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ ++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ ++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ ++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ ++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ ++ ++/* DAC.STATUS bit masks and bit positions */ ++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ ++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ ++ ++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ ++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ ++ ++/* DAC.CH0GAINCAL bit masks and bit positions */ ++#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH0OFFSETCAL bit masks and bit positions */ ++#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* DAC.CH1GAINCAL bit masks and bit positions */ ++#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH1OFFSETCAL bit masks and bit positions */ ++#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ ++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HSMODE Predefined. */ ++/* AC_HSMODE Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* RTC32 - 32-bit Real-Time Counter */ ++/* RTC32.CTRL bit masks and bit positions */ ++#define RTC32_ENABLE_bm 0x01 /* RTC enable bit mask. */ ++#define RTC32_ENABLE_bp 0 /* RTC enable bit position. */ ++ ++/* RTC32.SYNCCTRL bit masks and bit positions */ ++#define RTC32_SYNCCNT_bm 0x10 /* Synchronization Busy Flag bit mask. */ ++#define RTC32_SYNCCNT_bp 4 /* Synchronization Busy Flag bit position. */ ++ ++#define RTC32_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC32_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC32.INTCTRL bit masks and bit positions */ ++#define RTC32_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC32_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC32_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC32_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC32_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC32_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC32_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC32_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC32_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC32_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC32_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC32_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC32.INTFLAGS bit masks and bit positions */ ++#define RTC32_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC32_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC32_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC32_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* USB - USB */ ++/* USB_EP.STATUS bit masks and bit positions */ ++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ ++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ ++ ++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ ++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ ++ ++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ ++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ ++ ++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ ++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ ++ ++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ ++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ ++ ++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ ++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ ++ ++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ ++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ ++ ++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ ++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ ++ ++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ ++ ++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ ++ ++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ ++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ ++ ++/* USB_EP.CTRL bit masks and bit positions */ ++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ ++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ ++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ ++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ ++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ ++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ ++ ++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ ++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ ++ ++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ ++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ ++ ++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ ++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ ++ ++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ ++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ ++ ++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ ++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ ++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ ++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ ++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ ++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ ++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ ++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ ++ ++/* USB_EP.CNT bit masks and bit positions */ ++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ ++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ ++ ++/* USB.CTRLA bit masks and bit positions */ ++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ ++#define USB_ENABLE_bp 7 /* USB Enable bit position. */ ++ ++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ ++#define USB_SPEED_bp 6 /* Speed Select bit position. */ ++ ++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ ++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ ++ ++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ ++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ ++ ++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ ++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ ++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ ++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ ++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ ++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ ++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ ++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ ++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ ++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ ++ ++/* USB.CTRLB bit masks and bit positions */ ++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ ++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ ++ ++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ ++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ ++ ++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ ++#define USB_GNACK_bp 1 /* Global NACK bit position. */ ++ ++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ ++#define USB_ATTACH_bp 0 /* Attach bit position. */ ++ ++/* USB.STATUS bit masks and bit positions */ ++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ ++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ ++ ++#define USB_RESUME_bm 0x04 /* Resume bit mask. */ ++#define USB_RESUME_bp 2 /* Resume bit position. */ ++ ++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ ++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ ++ ++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ ++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ ++ ++/* USB.ADDR bit masks and bit positions */ ++#define USB_ADDR_gm 0x7F /* Device Address group mask. */ ++#define USB_ADDR_gp 0 /* Device Address group position. */ ++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ ++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ ++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ ++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ ++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ ++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ ++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ ++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ ++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ ++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ ++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ ++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ ++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ ++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ ++ ++/* USB.FIFOWP bit masks and bit positions */ ++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ ++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ ++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ ++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ ++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ ++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ ++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ ++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ ++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ ++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ ++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ ++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ ++ ++/* USB.FIFORP bit masks and bit positions */ ++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ ++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ ++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ ++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ ++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ ++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ ++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ ++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ ++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ ++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ ++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ ++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ ++ ++/* USB.INTCTRLA bit masks and bit positions */ ++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ ++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ ++ ++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ ++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ ++ ++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ ++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ ++ ++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ ++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ ++ ++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* USB.INTCTRLB bit masks and bit positions */ ++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ ++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ ++ ++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ ++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ ++ ++/* USB.INTFLAGSACLR bit masks and bit positions */ ++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ ++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ ++ ++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ ++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ ++ ++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ ++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ ++ ++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ ++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ ++ ++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ ++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ ++ ++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ ++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ ++ ++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ ++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ ++ ++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ ++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSASET bit masks and bit positions */ ++/* USB_SOFIF Predefined. */ ++/* USB_SOFIF Predefined. */ ++ ++/* USB_SUSPENDIF Predefined. */ ++/* USB_SUSPENDIF Predefined. */ ++ ++/* USB_RESUMEIF Predefined. */ ++/* USB_RESUMEIF Predefined. */ ++ ++/* USB_RSTIF Predefined. */ ++/* USB_RSTIF Predefined. */ ++ ++/* USB_CRCIF Predefined. */ ++/* USB_CRCIF Predefined. */ ++ ++/* USB_UNFIF Predefined. */ ++/* USB_UNFIF Predefined. */ ++ ++/* USB_OVFIF Predefined. */ ++/* USB_OVFIF Predefined. */ ++ ++/* USB_STALLIF Predefined. */ ++/* USB_STALLIF Predefined. */ ++ ++/* USB.INTFLAGSBCLR bit masks and bit positions */ ++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ ++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ ++ ++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ ++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSBSET bit masks and bit positions */ ++/* USB_TRNIF Predefined. */ ++/* USB_TRNIF Predefined. */ ++ ++/* USB_SETUPIF Predefined. */ ++/* USB_SETUPIF Predefined. */ ++ ++/* PORT - I/O Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_SPI_bm 0x20 /* SPI bit mask. */ ++#define PORT_SPI_bp 5 /* SPI bit position. */ ++ ++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ ++#define PORT_USART0_bp 4 /* USART0 bit position. */ ++ ++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ ++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ ++ ++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ ++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ ++ ++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ ++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ ++ ++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ ++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD Predefined. */ ++/* TC0_CMD Predefined. */ ++ ++/* TC0_LUPD Predefined. */ ++/* TC0_LUPD Predefined. */ ++ ++/* TC0_DIR Predefined. */ ++/* TC0_DIR Predefined. */ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV Predefined. */ ++/* TC0_CCDBV Predefined. */ ++ ++/* TC0_CCCBV Predefined. */ ++/* TC0_CCCBV Predefined. */ ++ ++/* TC0_CCBBV Predefined. */ ++/* TC0_CCBBV Predefined. */ ++ ++/* TC0_CCABV Predefined. */ ++/* TC0_CCABV Predefined. */ ++ ++/* TC0_PERBV Predefined. */ ++/* TC0_PERBV Predefined. */ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD Predefined. */ ++/* TC1_CMD Predefined. */ ++ ++/* TC1_LUPD Predefined. */ ++/* TC1_LUPD Predefined. */ ++ ++/* TC1_DIR Predefined. */ ++/* TC1_DIR Predefined. */ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV Predefined. */ ++/* TC1_CCBBV Predefined. */ ++ ++/* TC1_CCABV Predefined. */ ++/* TC1_CCABV Predefined. */ ++ ++/* TC1_PERBV Predefined. */ ++/* TC1_PERBV Predefined. */ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++/* TC2.CTRLA bit masks and bit positions */ ++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC2.CTRLB bit masks and bit positions */ ++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ ++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ ++ ++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ ++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ ++ ++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ ++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ ++ ++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ ++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ ++ ++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ ++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ ++ ++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ ++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ ++ ++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ ++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ ++ ++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ ++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ ++ ++/* TC2.CTRLC bit masks and bit positions */ ++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ ++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ ++ ++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ ++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ ++ ++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ ++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ ++ ++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ ++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ ++ ++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ ++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ ++ ++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ ++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ ++ ++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ ++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ ++ ++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ ++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ ++ ++/* TC2.CTRLE bit masks and bit positions */ ++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC2.INTCTRLA bit masks and bit positions */ ++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ ++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ ++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ ++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ ++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ ++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ ++ ++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ ++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ ++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ ++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ ++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ ++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ ++ ++/* TC2.INTCTRLB bit masks and bit positions */ ++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ ++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ ++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ ++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ ++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ ++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ ++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ ++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ ++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ ++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ ++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ ++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ ++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ ++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ ++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ ++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ ++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ ++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ ++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ ++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ ++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ ++ ++/* TC2.CTRLF bit masks and bit positions */ ++#define TC2_CMD_gm 0x0C /* Command group mask. */ ++#define TC2_CMD_gp 2 /* Command group position. */ ++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC2_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC2_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ ++#define TC2_CMDEN_gp 0 /* Command Enable group position. */ ++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ ++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ ++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ ++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ ++ ++/* TC2.INTFLAGS bit masks and bit positions */ ++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ ++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ ++ ++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ ++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ ++ ++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ ++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ ++ ++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ ++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ ++ ++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ ++ ++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ ++ ++/* AWEX - Timer/Counter Advanced Waveform Extension */ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++/* AWEX.STATUSSET bit masks and bit positions */ ++/* AWEX_FDF Predefined. */ ++/* AWEX_FDF Predefined. */ ++ ++/* AWEX_DTHSBUFV Predefined. */ ++/* AWEX_DTHSBUFV Predefined. */ ++ ++/* AWEX_DTLSBUFV Predefined. */ ++/* AWEX_DTLSBUFV Predefined. */ ++ ++/* HIRES - Timer/Counter High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ ++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ ++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ ++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ ++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ ++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ ++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ ++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ ++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ ++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ ++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ ++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ ++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ ++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ ++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ ++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ ++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ ++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ ++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ ++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ ++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* LOCKBIT - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* DMA interrupt vectors */ ++#define DMA_CH0_vect_num 6 ++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ ++#define DMA_CH1_vect_num 7 ++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ ++#define DMA_CH2_vect_num 8 ++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ ++#define DMA_CH3_vect_num 9 ++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ ++ ++/* RTC32 interrupt vectors */ ++#define RTC32_OVF_vect_num 10 ++#define RTC32_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC32_COMP_vect_num 11 ++#define RTC32_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LUNF_vect_num 14 ++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_HUNF_vect_num 15 ++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPA_vect_num 16 ++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPB_vect_num 17 ++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPC_vect_num 18 ++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPD_vect_num 19 ++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* USARTC1 interrupt vectors */ ++#define USARTC1_RXC_vect_num 28 ++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ ++#define USARTC1_DRE_vect_num 29 ++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ ++#define USARTC1_TXC_vect_num 30 ++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ ++ ++/* AES interrupt vectors */ ++#define AES_INT_vect_num 31 ++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* ACB interrupt vectors */ ++#define ACB_AC0_vect_num 36 ++#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ ++#define ACB_AC1_vect_num 37 ++#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ ++#define ACB_ACW_vect_num 38 ++#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ ++ ++/* ADCB interrupt vectors */ ++#define ADCB_CH0_vect_num 39 ++#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ ++#define ADCB_CH1_vect_num 40 ++#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ ++#define ADCB_CH2_vect_num 41 ++#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ ++#define ADCB_CH3_vect_num 42 ++#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LUNF_vect_num 47 ++#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_HUNF_vect_num 48 ++#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPA_vect_num 49 ++#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPB_vect_num 50 ++#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPC_vect_num 51 ++#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPD_vect_num 52 ++#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ ++ ++/* TCE1 interrupt vectors */ ++#define TCE1_OVF_vect_num 53 ++#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ ++#define TCE1_ERR_vect_num 54 ++#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ ++#define TCE1_CCA_vect_num 55 ++#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ ++#define TCE1_CCB_vect_num 56 ++#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++#define ADCA_CH1_vect_num 72 ++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ ++#define ADCA_CH2_vect_num 73 ++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ ++#define ADCA_CH3_vect_num 74 ++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LUNF_vect_num 77 ++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_HUNF_vect_num 78 ++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPA_vect_num 79 ++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPB_vect_num 80 ++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPC_vect_num 81 ++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPD_vect_num 82 ++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ ++ ++/* TCD1 interrupt vectors */ ++#define TCD1_OVF_vect_num 83 ++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ ++#define TCD1_ERR_vect_num 84 ++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ ++#define TCD1_CCA_vect_num 85 ++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ ++#define TCD1_CCB_vect_num 86 ++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* USARTD1 interrupt vectors */ ++#define USARTD1_RXC_vect_num 91 ++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ ++#define USARTD1_DRE_vect_num 92 ++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ ++#define USARTD1_TXC_vect_num 93 ++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ ++ ++/* PORTF interrupt vectors */ ++#define PORTF_INT0_vect_num 104 ++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ ++#define PORTF_INT1_vect_num 105 ++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_OVF_vect_num 108 ++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LUNF_vect_num 108 ++#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_ERR_vect_num 109 ++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_HUNF_vect_num 109 ++#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCA_vect_num 110 ++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPA_vect_num 110 ++#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCB_vect_num 111 ++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPB_vect_num 111 ++#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCC_vect_num 112 ++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPC_vect_num 112 ++#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCD_vect_num 113 ++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPD_vect_num 113 ++#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ ++ ++/* USARTF0 interrupt vectors */ ++#define USARTF0_RXC_vect_num 119 ++#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ ++#define USARTF0_DRE_vect_num 120 ++#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ ++#define USARTF0_TXC_vect_num 121 ++#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ ++ ++/* USB interrupt vectors */ ++#define USB_BUSEVENT_vect_num 125 ++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ ++#define USB_TRNCOMPL_vect_num 126 ++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (127 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (270336) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (262144) ++#define APP_SECTION_PAGE_SIZE (512) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x3E000) ++#define APPTABLE_SECTION_SIZE (8192) ++#define APPTABLE_SECTION_PAGE_SIZE (512) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x40000) ++#define BOOT_SECTION_SIZE (8192) ++#define BOOT_SECTION_PAGE_SIZE (512) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (24576) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (4096) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (16384) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (4096) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (6) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (512) ++#define USER_SIGNATURES_PAGE_SIZE (512) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (512) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 512 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 */ ++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ ++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ ++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ ++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ ++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ ++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ ++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ ++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ ++#define FUSE0_DEFAULT (0xFF) ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x98 ++#define SIGNATURE_2 0x43 ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA256A3BU_H_INCLUDED */ ++ diff --git a/include/avr/iox256a3u.h b/include/avr/iox256a3u.h new file mode 100644 -index 0000000..1e42a88 +index 0000000..6a2039d --- /dev/null +++ b/include/avr/iox256a3u.h @@ -0,0 +1,7628 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox256a3u.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA256A3U_H_INCLUDED -+#define _AVR_ATXMEGA256A3U_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -+#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -+#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -+#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -+#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -+#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -+#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -+#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -+#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -+#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -+#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -+#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -+#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -+#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -+#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -+#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -+#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -+#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -+#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -+#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -+#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -+#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -+#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+VPORT - Virtual Ports -+-------------------------------------------------------------------------- -+*/ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t USBCTRL; /* USB Control Register */ -+} CLK_t; -+ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t PRPB; /* Power Reduction Port B */ -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t PRPD; /* Power Reduction Port D */ -+ register8_t PRPE; /* Power Reduction Port E */ -+ register8_t PRPF; /* Power Reduction Port F */ -+} PR_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+/* USB Prescaler Division Factor */ -+typedef enum CLK_USBPSDIV_enum -+{ -+ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ -+ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ -+ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ -+ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ -+ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ -+ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -+} CLK_USBPSDIV_t; -+ -+/* USB Clock Source */ -+typedef enum CLK_USBSRC_enum -+{ -+ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ -+ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -+} CLK_USBSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control Register */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+/* 2 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC2MCREF_enum -+{ -+ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC2MCREF_t; -+ -+/* 32 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC32MCREF_enum -+{ -+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -+} OSC_RC32MCREF_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t JTAGUID; /* JTAG User ID */ -+ register8_t reserved_0x05; -+ register8_t MCUCR; /* MCU Control */ -+ register8_t ANAINIT; /* Analog Startup Delay */ -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t AWEXLOCK; /* AWEX Lock */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORTCFG - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t VPCTRLA; /* Virtual Port Control Register A */ -+ register8_t VPCTRLB; /* Virtual Port Control Register B */ -+ register8_t CLKEVOUT; /* Clock and Event Out Register */ -+ register8_t EBIOUT; /* EBI Output register */ -+ register8_t EVOUTSEL; /* Event Output Select */ -+} PORTCFG_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP02MAP_enum -+{ -+ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ -+ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ -+ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ -+ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ -+ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ -+ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ -+ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ -+ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ -+ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ -+ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ -+ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ -+ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ -+ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ -+ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ -+ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ -+ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -+} PORTCFG_VP02MAP_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP13MAP_enum -+{ -+ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ -+ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ -+ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ -+ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ -+ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ -+ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ -+ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ -+ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ -+ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ -+ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ -+ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ -+ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ -+ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ -+ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ -+ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ -+ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -+} PORTCFG_VP13MAP_t; -+ -+/* System Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ -+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ -+ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -+} PORTCFG_CLKOUT_t; -+ -+/* Peripheral Clock Output Select */ -+typedef enum PORTCFG_CLKOUTSEL_enum -+{ -+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -+} PORTCFG_CLKOUTSEL_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ -+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ -+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -+} PORTCFG_EVOUT_t; -+ -+/* Clock and Event Output Port */ -+typedef enum PORTCFG_CLKEVPIN_enum -+{ -+ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ -+ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -+} PORTCFG_CLKEVPIN_t; -+ -+/* EBI Address Output Port */ -+typedef enum PORTCFG_EBIADROUT_enum -+{ -+ PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ -+ PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ -+ PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ -+ PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ -+} PORTCFG_EBIADROUT_t; -+ -+/* EBI Chip Select Output Port */ -+typedef enum PORTCFG_EBICSOUT_enum -+{ -+ PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ -+} PORTCFG_EBICSOUT_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -+ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ -+ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ -+ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ -+ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AES - AES Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* AES Module */ -+typedef struct AES_struct -+{ -+ register8_t CTRL; /* AES Control Register */ -+ register8_t STATUS; /* AES Status Register */ -+ register8_t STATE; /* AES State Register */ -+ register8_t KEY; /* AES Key Register */ -+ register8_t INTCTRL; /* AES Interrupt Control Register */ -+} AES_t; -+ -+/* Interrupt level */ -+typedef enum AES_INTLVL_enum -+{ -+ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} AES_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ -+ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ -+ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ -+ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DMA - DMA Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* DMA Channel */ -+typedef struct DMA_CH_struct -+{ -+ register8_t CTRLA; /* Channel Control */ -+ register8_t CTRLB; /* Channel Control */ -+ register8_t ADDRCTRL; /* Address Control */ -+ register8_t TRIGSRC; /* Channel Trigger Source */ -+ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ -+ register8_t REPCNT; /* Channel Repeat Count */ -+ register8_t reserved_0x07; -+ register8_t SRCADDR0; /* Channel Source Address 0 */ -+ register8_t SRCADDR1; /* Channel Source Address 1 */ -+ register8_t SRCADDR2; /* Channel Source Address 2 */ -+ register8_t reserved_0x0B; -+ register8_t DESTADDR0; /* Channel Destination Address 0 */ -+ register8_t DESTADDR1; /* Channel Destination Address 1 */ -+ register8_t DESTADDR2; /* Channel Destination Address 2 */ -+ register8_t reserved_0x0F; -+} DMA_CH_t; -+ -+ -+/* DMA Controller */ -+typedef struct DMA_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t reserved_0x01; -+ register8_t reserved_0x02; -+ register8_t INTFLAGS; /* Transfer Interrupt Status */ -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x05; -+ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ DMA_CH_t CH0; /* DMA Channel 0 */ -+ DMA_CH_t CH1; /* DMA Channel 1 */ -+ DMA_CH_t CH2; /* DMA Channel 2 */ -+ DMA_CH_t CH3; /* DMA Channel 3 */ -+} DMA_t; -+ -+/* Burst mode */ -+typedef enum DMA_CH_BURSTLEN_enum -+{ -+ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ -+ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ -+ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ -+ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -+} DMA_CH_BURSTLEN_t; -+ -+/* Source address reload mode */ -+typedef enum DMA_CH_SRCRELOAD_enum -+{ -+ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ -+ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ -+ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ -+ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -+} DMA_CH_SRCRELOAD_t; -+ -+/* Source addressing mode */ -+typedef enum DMA_CH_SRCDIR_enum -+{ -+ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ -+ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ -+ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -+} DMA_CH_SRCDIR_t; -+ -+/* Destination adress reload mode */ -+typedef enum DMA_CH_DESTRELOAD_enum -+{ -+ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ -+ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ -+ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ -+ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -+} DMA_CH_DESTRELOAD_t; -+ -+/* Destination adressing mode */ -+typedef enum DMA_CH_DESTDIR_enum -+{ -+ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ -+ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ -+ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -+} DMA_CH_DESTDIR_t; -+ -+/* Transfer trigger source */ -+typedef enum DMA_CH_TRIGSRC_enum -+{ -+ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ -+ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ -+ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ -+ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ -+ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ -+ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ -+ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ -+ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ -+ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ -+ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ -+ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ -+ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ -+ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ -+ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ -+ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ -+ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ -+ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ -+ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ -+ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ -+ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ -+ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ -+ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ -+ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ -+ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ -+ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ -+ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ -+ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ -+ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ -+ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ -+ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ -+ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ -+ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ -+ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ -+ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ -+ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -+} DMA_CH_TRIGSRC_t; -+ -+/* Double buffering mode */ -+typedef enum DMA_DBUFMODE_enum -+{ -+ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ -+ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ -+ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ -+ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -+} DMA_DBUFMODE_t; -+ -+/* Priority mode */ -+typedef enum DMA_PRIMODE_enum -+{ -+ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ -+ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ -+ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ -+ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -+} DMA_PRIMODE_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_ERRINTLVL_enum -+{ -+ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ -+ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ -+ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -+} DMA_CH_ERRINTLVL_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_TRNINTLVL_enum -+{ -+ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ -+ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -+} DMA_CH_TRNINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ -+ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ -+ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ -+ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t CH4CTRL; /* Channel 4 Control Register */ -+ register8_t CH5CTRL; /* Channel 5 Control Register */ -+ register8_t CH6CTRL; /* Channel 6 Control Register */ -+ register8_t CH7CTRL; /* Channel 7 Control Register */ -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+} EVSYS_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ -+ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ -+ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ -+ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ -+ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ -+ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ -+ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ -+ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ -+ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ -+ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ -+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ -+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ -+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ -+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ -+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ -+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ -+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ -+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ -+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ -+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ -+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ -+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ -+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ -+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ -+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ -+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ -+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ -+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ -+ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ -+ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ -+ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ -+ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ -+ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ -+ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ -+ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ -+ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ -+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ -+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ -+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ -+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ -+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ -+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ -+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ -+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ -+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ -+ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ -+ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ -+ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ -+ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ -+ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ -+ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ -+ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ -+ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ -+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ -+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ -+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ -+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -+ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ -+ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ -+ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ -+ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ -+ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ -+ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ -+ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ -+ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -+ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ -+ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ -+ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ -+ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -+} EVSYS_CHMUX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ -+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ -+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ -+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ -+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} NVM_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t reserved_0x07; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ _WORDREGISTER(CH1RES); /* Channel 1 Result */ -+ _WORDREGISTER(CH2RES); /* Channel 2 Result */ -+ _WORDREGISTER(CH3RES); /* Channel 3 Result */ -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+ ADC_CH_t CH1; /* ADC Channel 1 */ -+ ADC_CH_t CH2; /* ADC Channel 2 */ -+ ADC_CH_t CH3; /* ADC Channel 3 */ -+} ADC_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -+ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+ ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 3) */ -+ ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Groud (Input Mode = 3) */ -+ ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Groud (Input Mode = 4) */ -+ ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 4) */ -+} ADC_CH_MUXNEG_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Current Limitation Mode */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ -+} ADC_CURRLIMIT_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Channel sweep selection */ -+typedef enum ADC_SWEEP_enum -+{ -+ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ -+ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ -+ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ -+ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -+} ADC_SWEEP_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ -+ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ -+ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ -+ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ -+ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ -+ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ -+ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ -+ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -+ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ -+ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ -+ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ -+ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* DMA request selection */ -+typedef enum ADC_DMASEL_enum -+{ -+ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ -+ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ -+ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ -+ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -+} ADC_DMASEL_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DAC - Digital/Analog Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Digital-to-Analog Converter */ -+typedef struct DAC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t EVCTRL; /* Event Input Control */ -+ register8_t reserved_0x04; -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0GAINCAL; /* Gain Calibration */ -+ register8_t CH0OFFSETCAL; /* Offset Calibration */ -+ register8_t CH1GAINCAL; /* Gain Calibration */ -+ register8_t CH1OFFSETCAL; /* Offset Calibration */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ -+ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -+} DAC_t; -+ -+/* Output channel selection */ -+typedef enum DAC_CHSEL_enum -+{ -+ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ -+ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ -+ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -+} DAC_CHSEL_t; -+ -+/* Reference voltage selection */ -+typedef enum DAC_REFSEL_enum -+{ -+ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ -+ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ -+ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ -+ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -+} DAC_REFSEL_t; -+ -+/* Event channel selection */ -+typedef enum DAC_EVSEL_enum -+{ -+ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ -+ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ -+ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ -+ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ -+ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ -+ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ -+ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ -+ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -+} DAC_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC - Real-Time Counter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Real-Time Counter */ -+typedef struct RTC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary register */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ _WORDREGISTER(CNT); /* Count Register */ -+ _WORDREGISTER(PER); /* Period Register */ -+ _WORDREGISTER(COMP); /* Compare Register */ -+} RTC_t; -+ -+/* Prescaler Factor */ -+typedef enum RTC_PRESCALER_enum -+{ -+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ -+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ -+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ -+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ -+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ -+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ -+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ -+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -+} RTC_PRESCALER_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC_COMPINTLVL_enum -+{ -+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC_OVFINTLVL_enum -+{ -+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+} TWI_t; -+ -+/* SDA Hold Time */ -+typedef enum TWI_SDAHOLD_enum -+{ -+ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ -+ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ -+ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ -+ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -+} TWI_SDAHOLD_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USB - USB -+-------------------------------------------------------------------------- -+*/ -+ -+/* USB Endpoint */ -+typedef struct USB_EP_struct -+{ -+ register8_t STATUS; /* Endpoint Status */ -+ register8_t CTRL; /* Endpoint Control */ -+ _WORDREGISTER(CNT); /* USB Endpoint Counter */ -+ _WORDREGISTER(DATAPTR); /* Data Pointer */ -+ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -+} USB_EP_t; -+ -+ -+/* Universal Serial Bus */ -+typedef struct USB_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t FIFOWP; /* FIFO Write Pointer Register */ -+ register8_t FIFORP; /* FIFO Read Pointer Register */ -+ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ -+ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ -+ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ -+ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t reserved_0x20; -+ register8_t reserved_0x21; -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t CAL0; /* Calibration Byte 0 */ -+ register8_t CAL1; /* Calibration Byte 1 */ -+} USB_t; -+ -+ -+/* USB Endpoint Table */ -+typedef struct USB_EP_TABLE_struct -+{ -+ USB_EP_t EP0OUT; /* Endpoint 0 */ -+ USB_EP_t EP0IN; /* Endpoint 0 */ -+ USB_EP_t EP1OUT; /* Endpoint 1 */ -+ USB_EP_t EP1IN; /* Endpoint 1 */ -+ USB_EP_t EP2OUT; /* Endpoint 2 */ -+ USB_EP_t EP2IN; /* Endpoint 2 */ -+ USB_EP_t EP3OUT; /* Endpoint 3 */ -+ USB_EP_t EP3IN; /* Endpoint 3 */ -+ USB_EP_t EP4OUT; /* Endpoint 4 */ -+ USB_EP_t EP4IN; /* Endpoint 4 */ -+ USB_EP_t EP5OUT; /* Endpoint 5 */ -+ USB_EP_t EP5IN; /* Endpoint 5 */ -+ USB_EP_t EP6OUT; /* Endpoint 6 */ -+ USB_EP_t EP6IN; /* Endpoint 6 */ -+ USB_EP_t EP7OUT; /* Endpoint 7 */ -+ USB_EP_t EP7IN; /* Endpoint 7 */ -+ USB_EP_t EP8OUT; /* Endpoint 8 */ -+ USB_EP_t EP8IN; /* Endpoint 8 */ -+ USB_EP_t EP9OUT; /* Endpoint 9 */ -+ USB_EP_t EP9IN; /* Endpoint 9 */ -+ USB_EP_t EP10OUT; /* Endpoint 10 */ -+ USB_EP_t EP10IN; /* Endpoint 10 */ -+ USB_EP_t EP11OUT; /* Endpoint 11 */ -+ USB_EP_t EP11IN; /* Endpoint 11 */ -+ USB_EP_t EP12OUT; /* Endpoint 12 */ -+ USB_EP_t EP12IN; /* Endpoint 12 */ -+ USB_EP_t EP13OUT; /* Endpoint 13 */ -+ USB_EP_t EP13IN; /* Endpoint 13 */ -+ USB_EP_t EP14OUT; /* Endpoint 14 */ -+ USB_EP_t EP14IN; /* Endpoint 14 */ -+ USB_EP_t EP15OUT; /* Endpoint 15 */ -+ USB_EP_t EP15IN; /* Endpoint 15 */ -+ register8_t reserved_0x100; -+ register8_t reserved_0x101; -+ register8_t reserved_0x102; -+ register8_t reserved_0x103; -+ register8_t reserved_0x104; -+ register8_t reserved_0x105; -+ register8_t reserved_0x106; -+ register8_t reserved_0x107; -+ register8_t reserved_0x108; -+ register8_t reserved_0x109; -+ register8_t reserved_0x10A; -+ register8_t reserved_0x10B; -+ register8_t reserved_0x10C; -+ register8_t reserved_0x10D; -+ register8_t reserved_0x10E; -+ register8_t reserved_0x10F; -+ register8_t FRAMENUML; /* Frame Number Low Byte */ -+ register8_t FRAMENUMH; /* Frame Number High Byte */ -+} USB_EP_TABLE_t; -+ -+/* Interrupt level */ -+typedef enum USB_INTLVL_enum -+{ -+ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} USB_INTLVL_t; -+ -+/* USB Endpoint Type */ -+typedef enum USB_EP_TYPE_enum -+{ -+ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ -+ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ -+ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ -+ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -+} USB_EP_TYPE_t; -+ -+/* USB Endpoint Buffersize */ -+typedef enum USB_EP_BUFSIZE_enum -+{ -+ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ -+ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ -+ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ -+ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ -+ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ -+ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ -+ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ -+ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -+} USB_EP_BUFSIZE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - I/O Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INT0MASK; /* Port Interrupt 0 Mask */ -+ register8_t INT1MASK; /* Port Interrupt 1 Mask */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t REMAP; /* I/O Port Pin Remap Register */ -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Port Interrupt 0 Level */ -+typedef enum PORT_INT0LVL_enum -+{ -+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INT0LVL_t; -+ -+/* Port Interrupt 1 Level */ -+typedef enum PORT_INT1LVL_enum -+{ -+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ -+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ -+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -+} PORT_INT1LVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 0 */ -+typedef struct TC0_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC0_t; -+ -+ -+/* 16-bit Timer/Counter 1 */ -+typedef struct TC1_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+} TC1_t; -+ -+/* Clock Selection */ -+typedef enum TC_CLKSEL_enum -+{ -+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC_CLKSEL_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC_WGMODE_enum -+{ -+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC_WGMODE_t; -+ -+/* Byte Mode */ -+typedef enum TC_BYTEM_enum -+{ -+ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ -+ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -+} TC_BYTEM_t; -+ -+/* Event Action */ -+typedef enum TC_EVACT_enum -+{ -+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ -+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ -+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ -+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ -+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ -+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC_EVSEL_enum -+{ -+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC_EVSEL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC_ERRINTLVL_enum -+{ -+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC_OVFINTLVL_enum -+{ -+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_OVFINTLVL_t; -+ -+/* Compare or Capture D Interrupt Level */ -+typedef enum TC_CCDINTLVL_enum -+{ -+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC_CCDINTLVL_t; -+ -+/* Compare or Capture C Interrupt Level */ -+typedef enum TC_CCCINTLVL_enum -+{ -+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC_CCCINTLVL_t; -+ -+/* Compare or Capture B Interrupt Level */ -+typedef enum TC_CCBINTLVL_enum -+{ -+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_CCBINTLVL_t; -+ -+/* Compare or Capture A Interrupt Level */ -+typedef enum TC_CCAINTLVL_enum -+{ -+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_CCAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC_CMD_enum -+{ -+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC2 - 16-bit Timer/Counter type 2 -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter type 2 */ -+typedef struct TC2_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t reserved_0x03; -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t reserved_0x08; -+ register8_t CTRLF; /* Control Register F */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t LCNT; /* Low Byte Count */ -+ register8_t HCNT; /* High Byte Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t LPER; /* Low Byte Period */ -+ register8_t HPER; /* High Byte Period */ -+ register8_t LCMPA; /* Low Byte Compare A */ -+ register8_t HCMPA; /* High Byte Compare A */ -+ register8_t LCMPB; /* Low Byte Compare B */ -+ register8_t HCMPB; /* High Byte Compare B */ -+ register8_t LCMPC; /* Low Byte Compare C */ -+ register8_t HCMPC; /* High Byte Compare C */ -+ register8_t LCMPD; /* Low Byte Compare D */ -+ register8_t HCMPD; /* High Byte Compare D */ -+} TC2_t; -+ -+/* Clock Selection */ -+typedef enum TC2_CLKSEL_enum -+{ -+ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC2_CLKSEL_t; -+ -+/* Byte Mode */ -+typedef enum TC2_BYTEM_enum -+{ -+ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ -+ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -+} TC2_BYTEM_t; -+ -+/* High Byte Underflow Interrupt Level */ -+typedef enum TC2_HUNFINTLVL_enum -+{ -+ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_HUNFINTLVL_t; -+ -+/* Low Byte Underflow Interrupt Level */ -+typedef enum TC2_LUNFINTLVL_enum -+{ -+ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LUNFINTLVL_t; -+ -+/* Low Byte Compare D Interrupt Level */ -+typedef enum TC2_LCMPDINTLVL_enum -+{ -+ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC2_LCMPDINTLVL_t; -+ -+/* Low Byte Compare C Interrupt Level */ -+typedef enum TC2_LCMPCINTLVL_enum -+{ -+ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC2_LCMPCINTLVL_t; -+ -+/* Low Byte Compare B Interrupt Level */ -+typedef enum TC2_LCMPBINTLVL_enum -+{ -+ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_LCMPBINTLVL_t; -+ -+/* Low Byte Compare A Interrupt Level */ -+typedef enum TC2_LCMPAINTLVL_enum -+{ -+ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LCMPAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMD_enum -+{ -+ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC2_CMD_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMDEN_enum -+{ -+ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ -+ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ -+ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -+} TC2_CMDEN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AWEX - Timer/Counter Advanced Waveform Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Advanced Waveform Extension */ -+typedef struct AWEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t FDEMASK; /* Fault Detection Event Mask */ -+ register8_t FDCTRL; /* Fault Detection Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t STATUSSET; /* Status Set Register */ -+ register8_t DTBOTH; /* Dead Time Both Sides */ -+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ -+ register8_t DTLS; /* Dead Time Low Side */ -+ register8_t DTHS; /* Dead Time High Side */ -+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ -+ register8_t DTHSBUF; /* Dead Time High Side Buffer */ -+ register8_t OUTOVEN; /* Output Override Enable */ -+} AWEX_t; -+ -+/* Fault Detect Action */ -+typedef enum AWEX_FDACT_enum -+{ -+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ -+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -+} AWEX_FDACT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+HIRES - Timer/Counter High-Resolution Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register */ -+} HIRES_t; -+ -+/* High Resolution Enable */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ -+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ -+ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ -+ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ -+ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -+} IRDA_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t FUSEBYTE0; /* JTAG User ID */ -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+} NVM_FUSES_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* Timer Oscillator pin location */ -+typedef enum TOSCSEL_enum -+{ -+ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ -+ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -+} TOSCSEL_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -+} BOD_t; -+ -+/* BOD operation */ -+typedef enum BODACT_enum -+{ -+ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BODACT_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WDP_enum -+{ -+ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ -+ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ -+ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ -+ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ -+ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ -+ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ -+ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ -+ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ -+ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ -+ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ -+ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -+} WDP_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LOCKBIT - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ -+ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t USBCAL0; /* USB Calibration Byte 0 */ -+ register8_t USBCAL1; /* USB Calibration Byte 1 */ -+ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ -+ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ -+ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ -+ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ -+ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ -+ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ -+ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ -+ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ -+ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ -+ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+ register8_t reserved_0x40; -+ register8_t reserved_0x41; -+ register8_t reserved_0x42; -+ register8_t reserved_0x43; -+ register8_t reserved_0x44; -+ register8_t reserved_0x45; -+ register8_t reserved_0x46; -+ register8_t reserved_0x47; -+} NVM_PROD_SIGNATURES_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define AES (*(AES_t *) 0x00C0) /* AES Module */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ -+#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ -+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -+#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -+#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -+#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -+#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -+#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -+#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ -+#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ -+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -+#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -+#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -+#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ -+#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ -+#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ -+#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ -+#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -+#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ -+#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ -+#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -+#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -+#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -+#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -+#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -+#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -+#define GPIO_GPIORA _SFR_MEM8(0x000A) -+#define GPIO_GPIORB _SFR_MEM8(0x000B) -+#define GPIO_GPIORC _SFR_MEM8(0x000C) -+#define GPIO_GPIORD _SFR_MEM8(0x000D) -+#define GPIO_GPIORE _SFR_MEM8(0x000E) -+#define GPIO_GPIORF _SFR_MEM8(0x000F) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+#define GPIO_GPIO4 _SFR_MEM8(0x0004) -+#define GPIO_GPIO5 _SFR_MEM8(0x0005) -+#define GPIO_GPIO6 _SFR_MEM8(0x0006) -+#define GPIO_GPIO7 _SFR_MEM8(0x0007) -+#define GPIO_GPIO8 _SFR_MEM8(0x0008) -+#define GPIO_GPIO9 _SFR_MEM8(0x0009) -+#define GPIO_GPIOA _SFR_MEM8(0x000A) -+#define GPIO_GPIOB _SFR_MEM8(0x000B) -+#define GPIO_GPIOC _SFR_MEM8(0x000C) -+#define GPIO_GPIOD _SFR_MEM8(0x000D) -+#define GPIO_GPIOE _SFR_MEM8(0x000E) -+#define GPIO_GPIOF _SFR_MEM8(0x000F) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -+#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -+#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -+#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -+#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -+#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -+#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) -+#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) -+#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -+#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) -+#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) -+#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+#define CLK_USBCTRL _SFR_MEM8(0x0044) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* DFLL - DFLL */ -+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -+#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -+#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPB _SFR_MEM8(0x0072) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPD _SFR_MEM8(0x0074) -+#define PR_PRPE _SFR_MEM8(0x0075) -+#define PR_PRPF _SFR_MEM8(0x0076) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_JTAGUID _SFR_MEM8(0x0094) -+#define MCU_MCUCR _SFR_MEM8(0x0096) -+#define MCU_ANAINIT _SFR_MEM8(0x0097) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_AWEXLOCK _SFR_MEM8(0x0099) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) -+#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) -+ -+/* AES - AES Module */ -+#define AES_CTRL _SFR_MEM8(0x00C0) -+#define AES_STATUS _SFR_MEM8(0x00C1) -+#define AES_STATE _SFR_MEM8(0x00C2) -+#define AES_KEY _SFR_MEM8(0x00C3) -+#define AES_INTCTRL _SFR_MEM8(0x00C4) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* DMA - DMA Controller */ -+#define DMA_CTRL _SFR_MEM8(0x0100) -+#define DMA_INTFLAGS _SFR_MEM8(0x0103) -+#define DMA_STATUS _SFR_MEM8(0x0104) -+#define DMA_TEMP _SFR_MEM16(0x0106) -+#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -+#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -+#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -+#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -+#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -+#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -+#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -+#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -+#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -+#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -+#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -+#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -+#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -+#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -+#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -+#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -+#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -+#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -+#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -+#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -+#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -+#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -+#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -+#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -+#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -+#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -+#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -+#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -+#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -+#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -+#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -+#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -+#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -+#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -+#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -+#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -+#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -+#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -+#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -+#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -+#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -+#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -+#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -+#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -+#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -+#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -+#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -+#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -+#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -+#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -+#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -+#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -+#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -+#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCA_CTRLA _SFR_MEM8(0x0200) -+#define ADCA_CTRLB _SFR_MEM8(0x0201) -+#define ADCA_REFCTRL _SFR_MEM8(0x0202) -+#define ADCA_EVCTRL _SFR_MEM8(0x0203) -+#define ADCA_PRESCALER _SFR_MEM8(0x0204) -+#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -+#define ADCA_TEMP _SFR_MEM8(0x0207) -+#define ADCA_CAL _SFR_MEM16(0x020C) -+#define ADCA_CH0RES _SFR_MEM16(0x0210) -+#define ADCA_CH1RES _SFR_MEM16(0x0212) -+#define ADCA_CH2RES _SFR_MEM16(0x0214) -+#define ADCA_CH3RES _SFR_MEM16(0x0216) -+#define ADCA_CMP _SFR_MEM16(0x0218) -+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -+#define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -+#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -+#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -+#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -+#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -+#define ADCA_CH1_RES _SFR_MEM16(0x022C) -+#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) -+#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -+#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -+#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -+#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -+#define ADCA_CH2_RES _SFR_MEM16(0x0234) -+#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) -+#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -+#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -+#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -+#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -+#define ADCA_CH3_RES _SFR_MEM16(0x023C) -+#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCB_CTRLA _SFR_MEM8(0x0240) -+#define ADCB_CTRLB _SFR_MEM8(0x0241) -+#define ADCB_REFCTRL _SFR_MEM8(0x0242) -+#define ADCB_EVCTRL _SFR_MEM8(0x0243) -+#define ADCB_PRESCALER _SFR_MEM8(0x0244) -+#define ADCB_INTFLAGS _SFR_MEM8(0x0246) -+#define ADCB_TEMP _SFR_MEM8(0x0247) -+#define ADCB_CAL _SFR_MEM16(0x024C) -+#define ADCB_CH0RES _SFR_MEM16(0x0250) -+#define ADCB_CH1RES _SFR_MEM16(0x0252) -+#define ADCB_CH2RES _SFR_MEM16(0x0254) -+#define ADCB_CH3RES _SFR_MEM16(0x0256) -+#define ADCB_CMP _SFR_MEM16(0x0258) -+#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) -+#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) -+#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) -+#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) -+#define ADCB_CH0_RES _SFR_MEM16(0x0264) -+#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) -+#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) -+#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) -+#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) -+#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) -+#define ADCB_CH1_RES _SFR_MEM16(0x026C) -+#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) -+#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) -+#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) -+#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) -+#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) -+#define ADCB_CH2_RES _SFR_MEM16(0x0274) -+#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) -+#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) -+#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) -+#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) -+#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) -+#define ADCB_CH3_RES _SFR_MEM16(0x027C) -+#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) -+ -+/* DAC - Digital-to-Analog Converter */ -+#define DACB_CTRLA _SFR_MEM8(0x0320) -+#define DACB_CTRLB _SFR_MEM8(0x0321) -+#define DACB_CTRLC _SFR_MEM8(0x0322) -+#define DACB_EVCTRL _SFR_MEM8(0x0323) -+#define DACB_STATUS _SFR_MEM8(0x0325) -+#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) -+#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) -+#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) -+#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) -+#define DACB_CH0DATA _SFR_MEM16(0x0338) -+#define DACB_CH1DATA _SFR_MEM16(0x033A) -+ -+/* AC - Analog Comparator */ -+#define ACA_AC0CTRL _SFR_MEM8(0x0380) -+#define ACA_AC1CTRL _SFR_MEM8(0x0381) -+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -+#define ACA_CTRLA _SFR_MEM8(0x0384) -+#define ACA_CTRLB _SFR_MEM8(0x0385) -+#define ACA_WINCTRL _SFR_MEM8(0x0386) -+#define ACA_STATUS _SFR_MEM8(0x0387) -+ -+/* AC - Analog Comparator */ -+#define ACB_AC0CTRL _SFR_MEM8(0x0390) -+#define ACB_AC1CTRL _SFR_MEM8(0x0391) -+#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -+#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -+#define ACB_CTRLA _SFR_MEM8(0x0394) -+#define ACB_CTRLB _SFR_MEM8(0x0395) -+#define ACB_WINCTRL _SFR_MEM8(0x0396) -+#define ACB_STATUS _SFR_MEM8(0x0397) -+ -+/* RTC - Real-Time Counter */ -+#define RTC_CTRL _SFR_MEM8(0x0400) -+#define RTC_STATUS _SFR_MEM8(0x0401) -+#define RTC_INTCTRL _SFR_MEM8(0x0402) -+#define RTC_INTFLAGS _SFR_MEM8(0x0403) -+#define RTC_TEMP _SFR_MEM8(0x0404) -+#define RTC_CNT _SFR_MEM16(0x0408) -+#define RTC_PER _SFR_MEM16(0x040A) -+#define RTC_COMP _SFR_MEM16(0x040C) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIE_CTRL _SFR_MEM8(0x04A0) -+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -+ -+/* USB - Universal Serial Bus */ -+#define USB_CTRLA _SFR_MEM8(0x04C0) -+#define USB_CTRLB _SFR_MEM8(0x04C1) -+#define USB_STATUS _SFR_MEM8(0x04C2) -+#define USB_ADDR _SFR_MEM8(0x04C3) -+#define USB_FIFOWP _SFR_MEM8(0x04C4) -+#define USB_FIFORP _SFR_MEM8(0x04C5) -+#define USB_EPPTR _SFR_MEM16(0x04C6) -+#define USB_INTCTRLA _SFR_MEM8(0x04C8) -+#define USB_INTCTRLB _SFR_MEM8(0x04C9) -+#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -+#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -+#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -+#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -+#define USB_CAL0 _SFR_MEM8(0x04FA) -+#define USB_CAL1 _SFR_MEM8(0x04FB) -+ -+/* PORT - I/O Ports */ -+#define PORTA_DIR _SFR_MEM8(0x0600) -+#define PORTA_DIRSET _SFR_MEM8(0x0601) -+#define PORTA_DIRCLR _SFR_MEM8(0x0602) -+#define PORTA_DIRTGL _SFR_MEM8(0x0603) -+#define PORTA_OUT _SFR_MEM8(0x0604) -+#define PORTA_OUTSET _SFR_MEM8(0x0605) -+#define PORTA_OUTCLR _SFR_MEM8(0x0606) -+#define PORTA_OUTTGL _SFR_MEM8(0x0607) -+#define PORTA_IN _SFR_MEM8(0x0608) -+#define PORTA_INTCTRL _SFR_MEM8(0x0609) -+#define PORTA_INT0MASK _SFR_MEM8(0x060A) -+#define PORTA_INT1MASK _SFR_MEM8(0x060B) -+#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_REMAP _SFR_MEM8(0x060E) -+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -+ -+/* PORT - I/O Ports */ -+#define PORTB_DIR _SFR_MEM8(0x0620) -+#define PORTB_DIRSET _SFR_MEM8(0x0621) -+#define PORTB_DIRCLR _SFR_MEM8(0x0622) -+#define PORTB_DIRTGL _SFR_MEM8(0x0623) -+#define PORTB_OUT _SFR_MEM8(0x0624) -+#define PORTB_OUTSET _SFR_MEM8(0x0625) -+#define PORTB_OUTCLR _SFR_MEM8(0x0626) -+#define PORTB_OUTTGL _SFR_MEM8(0x0627) -+#define PORTB_IN _SFR_MEM8(0x0628) -+#define PORTB_INTCTRL _SFR_MEM8(0x0629) -+#define PORTB_INT0MASK _SFR_MEM8(0x062A) -+#define PORTB_INT1MASK _SFR_MEM8(0x062B) -+#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -+#define PORTB_REMAP _SFR_MEM8(0x062E) -+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INT0MASK _SFR_MEM8(0x064A) -+#define PORTC_INT1MASK _SFR_MEM8(0x064B) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INT0MASK _SFR_MEM8(0x066A) -+#define PORTD_INT1MASK _SFR_MEM8(0x066B) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTE_DIR _SFR_MEM8(0x0680) -+#define PORTE_DIRSET _SFR_MEM8(0x0681) -+#define PORTE_DIRCLR _SFR_MEM8(0x0682) -+#define PORTE_DIRTGL _SFR_MEM8(0x0683) -+#define PORTE_OUT _SFR_MEM8(0x0684) -+#define PORTE_OUTSET _SFR_MEM8(0x0685) -+#define PORTE_OUTCLR _SFR_MEM8(0x0686) -+#define PORTE_OUTTGL _SFR_MEM8(0x0687) -+#define PORTE_IN _SFR_MEM8(0x0688) -+#define PORTE_INTCTRL _SFR_MEM8(0x0689) -+#define PORTE_INT0MASK _SFR_MEM8(0x068A) -+#define PORTE_INT1MASK _SFR_MEM8(0x068B) -+#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -+#define PORTE_REMAP _SFR_MEM8(0x068E) -+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) -+ -+/* PORT - I/O Ports */ -+#define PORTF_DIR _SFR_MEM8(0x06A0) -+#define PORTF_DIRSET _SFR_MEM8(0x06A1) -+#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -+#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -+#define PORTF_OUT _SFR_MEM8(0x06A4) -+#define PORTF_OUTSET _SFR_MEM8(0x06A5) -+#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -+#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -+#define PORTF_IN _SFR_MEM8(0x06A8) -+#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -+#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -+#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -+#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -+#define PORTF_REMAP _SFR_MEM8(0x06AE) -+#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -+#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -+#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -+#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -+#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -+#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -+#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -+#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -+#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCC0_CTRLA _SFR_MEM8(0x0800) -+#define TCC0_CTRLB _SFR_MEM8(0x0801) -+#define TCC0_CTRLC _SFR_MEM8(0x0802) -+#define TCC0_CTRLD _SFR_MEM8(0x0803) -+#define TCC0_CTRLE _SFR_MEM8(0x0804) -+#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -+#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -+#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -+#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC0_TEMP _SFR_MEM8(0x080F) -+#define TCC0_CNT _SFR_MEM16(0x0820) -+#define TCC0_PER _SFR_MEM16(0x0826) -+#define TCC0_CCA _SFR_MEM16(0x0828) -+#define TCC0_CCB _SFR_MEM16(0x082A) -+#define TCC0_CCC _SFR_MEM16(0x082C) -+#define TCC0_CCD _SFR_MEM16(0x082E) -+#define TCC0_PERBUF _SFR_MEM16(0x0836) -+#define TCC0_CCABUF _SFR_MEM16(0x0838) -+#define TCC0_CCBBUF _SFR_MEM16(0x083A) -+#define TCC0_CCCBUF _SFR_MEM16(0x083C) -+#define TCC0_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCC2_CTRLA _SFR_MEM8(0x0800) -+#define TCC2_CTRLB _SFR_MEM8(0x0801) -+#define TCC2_CTRLC _SFR_MEM8(0x0802) -+#define TCC2_CTRLE _SFR_MEM8(0x0804) -+#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC2_CTRLF _SFR_MEM8(0x0809) -+#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC2_LCNT _SFR_MEM8(0x0820) -+#define TCC2_HCNT _SFR_MEM8(0x0821) -+#define TCC2_LPER _SFR_MEM8(0x0826) -+#define TCC2_HPER _SFR_MEM8(0x0827) -+#define TCC2_LCMPA _SFR_MEM8(0x0828) -+#define TCC2_HCMPA _SFR_MEM8(0x0829) -+#define TCC2_LCMPB _SFR_MEM8(0x082A) -+#define TCC2_HCMPB _SFR_MEM8(0x082B) -+#define TCC2_LCMPC _SFR_MEM8(0x082C) -+#define TCC2_HCMPC _SFR_MEM8(0x082D) -+#define TCC2_LCMPD _SFR_MEM8(0x082E) -+#define TCC2_HCMPD _SFR_MEM8(0x082F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCC1_CTRLA _SFR_MEM8(0x0840) -+#define TCC1_CTRLB _SFR_MEM8(0x0841) -+#define TCC1_CTRLC _SFR_MEM8(0x0842) -+#define TCC1_CTRLD _SFR_MEM8(0x0843) -+#define TCC1_CTRLE _SFR_MEM8(0x0844) -+#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -+#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -+#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -+#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC1_TEMP _SFR_MEM8(0x084F) -+#define TCC1_CNT _SFR_MEM16(0x0860) -+#define TCC1_PER _SFR_MEM16(0x0866) -+#define TCC1_CCA _SFR_MEM16(0x0868) -+#define TCC1_CCB _SFR_MEM16(0x086A) -+#define TCC1_PERBUF _SFR_MEM16(0x0876) -+#define TCC1_CCABUF _SFR_MEM16(0x0878) -+#define TCC1_CCBBUF _SFR_MEM16(0x087A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXC_CTRL _SFR_MEM8(0x0880) -+#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -+#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -+#define AWEXC_STATUS _SFR_MEM8(0x0884) -+#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -+#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -+#define AWEXC_DTLS _SFR_MEM8(0x0888) -+#define AWEXC_DTHS _SFR_MEM8(0x0889) -+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x0890) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08A0) -+#define USARTC0_STATUS _SFR_MEM8(0x08A1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -+#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -+#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC1_DATA _SFR_MEM8(0x08B0) -+#define USARTC1_STATUS _SFR_MEM8(0x08B1) -+#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -+#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -+#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -+#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -+#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIC_CTRL _SFR_MEM8(0x08C0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -+#define SPIC_STATUS _SFR_MEM8(0x08C2) -+#define SPIC_DATA _SFR_MEM8(0x08C3) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCD0_CTRLA _SFR_MEM8(0x0900) -+#define TCD0_CTRLB _SFR_MEM8(0x0901) -+#define TCD0_CTRLC _SFR_MEM8(0x0902) -+#define TCD0_CTRLD _SFR_MEM8(0x0903) -+#define TCD0_CTRLE _SFR_MEM8(0x0904) -+#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -+#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -+#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -+#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -+#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD0_TEMP _SFR_MEM8(0x090F) -+#define TCD0_CNT _SFR_MEM16(0x0920) -+#define TCD0_PER _SFR_MEM16(0x0926) -+#define TCD0_CCA _SFR_MEM16(0x0928) -+#define TCD0_CCB _SFR_MEM16(0x092A) -+#define TCD0_CCC _SFR_MEM16(0x092C) -+#define TCD0_CCD _SFR_MEM16(0x092E) -+#define TCD0_PERBUF _SFR_MEM16(0x0936) -+#define TCD0_CCABUF _SFR_MEM16(0x0938) -+#define TCD0_CCBBUF _SFR_MEM16(0x093A) -+#define TCD0_CCCBUF _SFR_MEM16(0x093C) -+#define TCD0_CCDBUF _SFR_MEM16(0x093E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCD2_CTRLA _SFR_MEM8(0x0900) -+#define TCD2_CTRLB _SFR_MEM8(0x0901) -+#define TCD2_CTRLC _SFR_MEM8(0x0902) -+#define TCD2_CTRLE _SFR_MEM8(0x0904) -+#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD2_CTRLF _SFR_MEM8(0x0909) -+#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD2_LCNT _SFR_MEM8(0x0920) -+#define TCD2_HCNT _SFR_MEM8(0x0921) -+#define TCD2_LPER _SFR_MEM8(0x0926) -+#define TCD2_HPER _SFR_MEM8(0x0927) -+#define TCD2_LCMPA _SFR_MEM8(0x0928) -+#define TCD2_HCMPA _SFR_MEM8(0x0929) -+#define TCD2_LCMPB _SFR_MEM8(0x092A) -+#define TCD2_HCMPB _SFR_MEM8(0x092B) -+#define TCD2_LCMPC _SFR_MEM8(0x092C) -+#define TCD2_HCMPC _SFR_MEM8(0x092D) -+#define TCD2_LCMPD _SFR_MEM8(0x092E) -+#define TCD2_HCMPD _SFR_MEM8(0x092F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCD1_CTRLA _SFR_MEM8(0x0940) -+#define TCD1_CTRLB _SFR_MEM8(0x0941) -+#define TCD1_CTRLC _SFR_MEM8(0x0942) -+#define TCD1_CTRLD _SFR_MEM8(0x0943) -+#define TCD1_CTRLE _SFR_MEM8(0x0944) -+#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -+#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -+#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -+#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -+#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -+#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -+#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -+#define TCD1_TEMP _SFR_MEM8(0x094F) -+#define TCD1_CNT _SFR_MEM16(0x0960) -+#define TCD1_PER _SFR_MEM16(0x0966) -+#define TCD1_CCA _SFR_MEM16(0x0968) -+#define TCD1_CCB _SFR_MEM16(0x096A) -+#define TCD1_PERBUF _SFR_MEM16(0x0976) -+#define TCD1_CCABUF _SFR_MEM16(0x0978) -+#define TCD1_CCBBUF _SFR_MEM16(0x097A) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESD_CTRLA _SFR_MEM8(0x0990) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD0_DATA _SFR_MEM8(0x09A0) -+#define USARTD0_STATUS _SFR_MEM8(0x09A1) -+#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -+#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -+#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD1_DATA _SFR_MEM8(0x09B0) -+#define USARTD1_STATUS _SFR_MEM8(0x09B1) -+#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -+#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -+#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -+#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -+#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPID_CTRL _SFR_MEM8(0x09C0) -+#define SPID_INTCTRL _SFR_MEM8(0x09C1) -+#define SPID_STATUS _SFR_MEM8(0x09C2) -+#define SPID_DATA _SFR_MEM8(0x09C3) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCE0_CTRLA _SFR_MEM8(0x0A00) -+#define TCE0_CTRLB _SFR_MEM8(0x0A01) -+#define TCE0_CTRLC _SFR_MEM8(0x0A02) -+#define TCE0_CTRLD _SFR_MEM8(0x0A03) -+#define TCE0_CTRLE _SFR_MEM8(0x0A04) -+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE0_TEMP _SFR_MEM8(0x0A0F) -+#define TCE0_CNT _SFR_MEM16(0x0A20) -+#define TCE0_PER _SFR_MEM16(0x0A26) -+#define TCE0_CCA _SFR_MEM16(0x0A28) -+#define TCE0_CCB _SFR_MEM16(0x0A2A) -+#define TCE0_CCC _SFR_MEM16(0x0A2C) -+#define TCE0_CCD _SFR_MEM16(0x0A2E) -+#define TCE0_PERBUF _SFR_MEM16(0x0A36) -+#define TCE0_CCABUF _SFR_MEM16(0x0A38) -+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCE2_CTRLA _SFR_MEM8(0x0A00) -+#define TCE2_CTRLB _SFR_MEM8(0x0A01) -+#define TCE2_CTRLC _SFR_MEM8(0x0A02) -+#define TCE2_CTRLE _SFR_MEM8(0x0A04) -+#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE2_CTRLF _SFR_MEM8(0x0A09) -+#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE2_LCNT _SFR_MEM8(0x0A20) -+#define TCE2_HCNT _SFR_MEM8(0x0A21) -+#define TCE2_LPER _SFR_MEM8(0x0A26) -+#define TCE2_HPER _SFR_MEM8(0x0A27) -+#define TCE2_LCMPA _SFR_MEM8(0x0A28) -+#define TCE2_HCMPA _SFR_MEM8(0x0A29) -+#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -+#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -+#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -+#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -+#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -+#define TCE2_HCMPD _SFR_MEM8(0x0A2F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCE1_CTRLA _SFR_MEM8(0x0A40) -+#define TCE1_CTRLB _SFR_MEM8(0x0A41) -+#define TCE1_CTRLC _SFR_MEM8(0x0A42) -+#define TCE1_CTRLD _SFR_MEM8(0x0A43) -+#define TCE1_CTRLE _SFR_MEM8(0x0A44) -+#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) -+#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) -+#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) -+#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) -+#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) -+#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) -+#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) -+#define TCE1_TEMP _SFR_MEM8(0x0A4F) -+#define TCE1_CNT _SFR_MEM16(0x0A60) -+#define TCE1_PER _SFR_MEM16(0x0A66) -+#define TCE1_CCA _SFR_MEM16(0x0A68) -+#define TCE1_CCB _SFR_MEM16(0x0A6A) -+#define TCE1_PERBUF _SFR_MEM16(0x0A76) -+#define TCE1_CCABUF _SFR_MEM16(0x0A78) -+#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXE_CTRL _SFR_MEM8(0x0A80) -+#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) -+#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) -+#define AWEXE_STATUS _SFR_MEM8(0x0A84) -+#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) -+#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) -+#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) -+#define AWEXE_DTLS _SFR_MEM8(0x0A88) -+#define AWEXE_DTHS _SFR_MEM8(0x0A89) -+#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) -+#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) -+#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESE_CTRLA _SFR_MEM8(0x0A90) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE0_DATA _SFR_MEM8(0x0AA0) -+#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -+#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -+#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -+#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -+#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -+#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE1_DATA _SFR_MEM8(0x0AB0) -+#define USARTE1_STATUS _SFR_MEM8(0x0AB1) -+#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) -+#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) -+#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) -+#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) -+#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIE_CTRL _SFR_MEM8(0x0AC0) -+#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) -+#define SPIE_STATUS _SFR_MEM8(0x0AC2) -+#define SPIE_DATA _SFR_MEM8(0x0AC3) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCF0_CTRLA _SFR_MEM8(0x0B00) -+#define TCF0_CTRLB _SFR_MEM8(0x0B01) -+#define TCF0_CTRLC _SFR_MEM8(0x0B02) -+#define TCF0_CTRLD _SFR_MEM8(0x0B03) -+#define TCF0_CTRLE _SFR_MEM8(0x0B04) -+#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -+#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -+#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -+#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -+#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -+#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -+#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -+#define TCF0_TEMP _SFR_MEM8(0x0B0F) -+#define TCF0_CNT _SFR_MEM16(0x0B20) -+#define TCF0_PER _SFR_MEM16(0x0B26) -+#define TCF0_CCA _SFR_MEM16(0x0B28) -+#define TCF0_CCB _SFR_MEM16(0x0B2A) -+#define TCF0_CCC _SFR_MEM16(0x0B2C) -+#define TCF0_CCD _SFR_MEM16(0x0B2E) -+#define TCF0_PERBUF _SFR_MEM16(0x0B36) -+#define TCF0_CCABUF _SFR_MEM16(0x0B38) -+#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -+#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -+#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCF2_CTRLA _SFR_MEM8(0x0B00) -+#define TCF2_CTRLB _SFR_MEM8(0x0B01) -+#define TCF2_CTRLC _SFR_MEM8(0x0B02) -+#define TCF2_CTRLE _SFR_MEM8(0x0B04) -+#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -+#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -+#define TCF2_CTRLF _SFR_MEM8(0x0B09) -+#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -+#define TCF2_LCNT _SFR_MEM8(0x0B20) -+#define TCF2_HCNT _SFR_MEM8(0x0B21) -+#define TCF2_LPER _SFR_MEM8(0x0B26) -+#define TCF2_HPER _SFR_MEM8(0x0B27) -+#define TCF2_LCMPA _SFR_MEM8(0x0B28) -+#define TCF2_HCMPA _SFR_MEM8(0x0B29) -+#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -+#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -+#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -+#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -+#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -+#define TCF2_HCMPD _SFR_MEM8(0x0B2F) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESF_CTRLA _SFR_MEM8(0x0B90) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTF0_DATA _SFR_MEM8(0x0BA0) -+#define USARTF0_STATUS _SFR_MEM8(0x0BA1) -+#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) -+#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) -+#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) -+#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) -+#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* VPORT - Virtual Ports */ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* CLK.USBCTRL bit masks and bit positions */ -+#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -+#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -+#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -+#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -+#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -+#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -+#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -+#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ -+ -+#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -+#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -+#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ -+ -+#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_USB_bm 0x40 /* USB bit mask. */ -+#define PR_USB_bp 6 /* USB bit position. */ -+ -+#define PR_AES_bm 0x10 /* AES bit mask. */ -+#define PR_AES_bp 4 /* AES bit position. */ -+ -+#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -+#define PR_EBI_bp 3 /* External Bus Interface bit position. */ -+ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -+#define PR_DMA_bp 0 /* DMA-Controller bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -+#define PR_DAC_bp 2 /* Port A DAC bit position. */ -+ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPB bit masks and bit positions */ -+/* PR_DAC Predefined. */ -+/* PR_DAC Predefined. */ -+ -+/* PR_ADC Predefined. */ -+/* PR_ADC Predefined. */ -+ -+/* PR_AC Predefined. */ -+/* PR_AC Predefined. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -+#define PR_USART1_bp 5 /* Port C USART1 bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -+#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ -+ -+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -+ -+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ -+ -+/* PR.PRPD bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPE bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPF bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -+#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -+#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ -+ -+#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ -+ -+#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -+#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.MCUCR bit masks and bit positions */ -+#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -+#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ -+ -+/* MCU.ANAINIT bit masks and bit positions */ -+#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -+#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -+#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -+#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -+#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -+#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ -+ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -+#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ -+ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.AWEXLOCK bit masks and bit positions */ -+#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ -+#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ -+ -+#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -+#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ -+ -+#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ -+#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ -+ -+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* PORTCFG - Port Configuration */ -+/* PORTCFG.VPCTRLA bit masks and bit positions */ -+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ -+ -+/* PORTCFG.VPCTRLB bit masks and bit positions */ -+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ -+ -+/* PORTCFG.CLKEVOUT bit masks and bit positions */ -+#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ -+ -+#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -+#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -+#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -+#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -+#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -+#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ -+ -+#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -+#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ -+ -+#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -+#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ -+ -+/* PORTCFG.EBIOUT bit masks and bit positions */ -+#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ -+#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ -+#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ -+#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ -+#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ -+#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ -+ -+#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ -+#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ -+#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ -+#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ -+#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ -+#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ -+ -+/* PORTCFG.EVOUTSEL bit masks and bit positions */ -+#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -+#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -+#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -+#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -+#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -+#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -+#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -+#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ -+ -+/* AES - AES Module */ -+/* AES.CTRL bit masks and bit positions */ -+#define AES_START_bm 0x80 /* Start/Run bit mask. */ -+#define AES_START_bp 7 /* Start/Run bit position. */ -+ -+#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -+#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ -+ -+#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -+#define AES_RESET_bp 5 /* AES Software Reset bit position. */ -+ -+#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -+#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ -+ -+#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -+#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ -+ -+/* AES.STATUS bit masks and bit positions */ -+#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -+#define AES_ERROR_bp 7 /* AES Error bit position. */ -+ -+#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -+#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ -+ -+/* AES.INTCTRL bit masks and bit positions */ -+#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -+#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* DMA - DMA Controller */ -+/* DMA_CH.CTRLA bit masks and bit positions */ -+#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -+#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ -+ -+#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -+#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ -+ -+#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -+#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ -+ -+#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -+#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ -+ -+#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -+#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ -+ -+#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -+#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -+#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -+#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -+#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -+#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ -+ -+/* DMA_CH.CTRLB bit masks and bit positions */ -+#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -+#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ -+ -+#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -+#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ -+ -+#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -+#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ -+ -+#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -+#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -+#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -+#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -+#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -+#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ -+ -+#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -+#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -+#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -+#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -+#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -+#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ -+ -+/* DMA_CH.ADDRCTRL bit masks and bit positions */ -+#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -+#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -+#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -+#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -+#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -+#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ -+ -+#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -+#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -+#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -+#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -+#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -+#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ -+ -+#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -+#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -+#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -+#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -+#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -+#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ -+ -+#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -+#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -+#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -+#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -+#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -+#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ -+ -+/* DMA_CH.TRIGSRC bit masks and bit positions */ -+#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -+#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -+#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -+#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -+#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -+#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -+#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -+#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -+#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -+#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -+#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -+#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -+#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -+#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -+#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -+#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -+#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -+#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ -+ -+/* DMA.CTRL bit masks and bit positions */ -+#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -+#define DMA_ENABLE_bp 7 /* Enable bit position. */ -+ -+#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -+#define DMA_RESET_bp 6 /* Software Reset bit position. */ -+ -+#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -+#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -+#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -+#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -+#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -+#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ -+ -+#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -+#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -+#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -+#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -+#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -+#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ -+ -+/* DMA.INTFLAGS bit masks and bit positions */ -+#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ -+ -+/* DMA.STATUS bit masks and bit positions */ -+#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -+#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ -+ -+#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -+#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ -+ -+#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -+#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ -+ -+#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -+#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ -+ -+#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -+#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ -+ -+#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -+#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ -+ -+#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -+#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ -+ -+#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -+#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH4MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH5MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH6MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH7MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_QDIRM Predefined. */ -+/* EVSYS_QDIRM Predefined. */ -+ -+/* EVSYS_QDIEN Predefined. */ -+/* EVSYS_QDIEN Predefined. */ -+ -+/* EVSYS_QDEN Predefined. */ -+/* EVSYS_QDEN Predefined. */ -+ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH4CTRL bit masks and bit positions */ -+/* EVSYS_QDIRM Predefined. */ -+/* EVSYS_QDIRM Predefined. */ -+ -+/* EVSYS_QDIEN Predefined. */ -+/* EVSYS_QDIEN Predefined. */ -+ -+/* EVSYS_QDEN Predefined. */ -+/* EVSYS_QDEN Predefined. */ -+ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH5CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH6CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH7CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0x7F /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ -+ -+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ -+ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -+#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ -+#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -+#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -+#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -+#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -+#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -+#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -+#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -+#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -+#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -+#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ -+ -+#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -+#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -+#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -+#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -+#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -+#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -+#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -+#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -+#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -+#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -+#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -+#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -+#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -+#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -+#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ -+ -+#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -+#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ -+ -+#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -+#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ -+ -+#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -+#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ -+ -+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -+#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ -+#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ -+ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -+#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -+#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -+#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -+#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -+#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ -+ -+#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -+#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -+#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ -+ -+#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -+#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ -+ -+#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -+#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ -+ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* DAC - Digital/Analog Converter */ -+/* DAC.CTRLA bit masks and bit positions */ -+#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -+#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ -+ -+#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -+#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ -+ -+#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -+#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ -+ -+#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -+#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ -+ -+#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define DAC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* DAC.CTRLB bit masks and bit positions */ -+#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -+#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -+#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -+#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -+#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -+#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ -+ -+#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -+#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ -+ -+#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -+#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ -+ -+/* DAC.CTRLC bit masks and bit positions */ -+#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -+#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -+#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -+#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -+#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -+#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ -+ -+#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -+#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ -+ -+/* DAC.EVCTRL bit masks and bit positions */ -+#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -+#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ -+ -+#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -+#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -+#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -+#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -+#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -+#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -+#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -+#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ -+ -+/* DAC.STATUS bit masks and bit positions */ -+#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -+#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ -+ -+#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -+#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ -+ -+/* DAC.CH0GAINCAL bit masks and bit positions */ -+#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -+#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -+#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -+#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -+#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -+#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -+#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -+#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -+#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -+#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -+#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -+#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -+#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -+#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -+#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -+#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ -+ -+/* DAC.CH0OFFSETCAL bit masks and bit positions */ -+#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -+#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -+#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -+#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -+#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -+#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -+#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -+#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -+#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -+#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -+#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -+#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -+#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -+#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -+#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -+#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ -+ -+/* DAC.CH1GAINCAL bit masks and bit positions */ -+#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -+#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -+#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -+#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -+#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -+#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -+#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -+#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -+#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -+#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -+#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -+#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -+#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -+#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -+#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -+#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ -+ -+/* DAC.CH1OFFSETCAL bit masks and bit positions */ -+#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -+#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -+#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -+#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -+#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -+#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -+#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -+#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -+#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -+#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -+#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -+#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -+#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -+#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -+#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -+#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -+#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HSMODE Predefined. */ -+/* AC_HSMODE Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* RTC - Real-Time Counter */ -+/* RTC.CTRL bit masks and bit positions */ -+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ -+ -+/* RTC.STATUS bit masks and bit positions */ -+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC.INTCTRL bit masks and bit positions */ -+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC.INTFLAGS bit masks and bit positions */ -+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* USB - USB */ -+/* USB_EP.STATUS bit masks and bit positions */ -+#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -+#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ -+ -+#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -+#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ -+ -+#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -+#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ -+ -+#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -+#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ -+ -+#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -+#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ -+ -+#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -+#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ -+ -+#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -+#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ -+ -+#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -+#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ -+ -+#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ -+ -+#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ -+ -+#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -+#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ -+ -+/* USB_EP.CTRL bit masks and bit positions */ -+#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -+#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -+#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -+#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -+#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -+#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ -+ -+#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -+#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ -+ -+#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -+#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ -+ -+#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -+#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ -+ -+#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -+#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ -+ -+#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -+#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -+#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -+#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -+#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -+#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -+#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -+#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ -+ -+/* USB_EP.CNT bit masks and bit positions */ -+#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -+#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ -+ -+/* USB.CTRLA bit masks and bit positions */ -+#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -+#define USB_ENABLE_bp 7 /* USB Enable bit position. */ -+ -+#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -+#define USB_SPEED_bp 6 /* Speed Select bit position. */ -+ -+#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -+#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ -+ -+#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -+#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ -+ -+#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -+#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -+#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -+#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -+#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -+#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -+#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -+#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -+#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -+#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ -+ -+/* USB.CTRLB bit masks and bit positions */ -+#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -+#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ -+ -+#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -+#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ -+ -+#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -+#define USB_GNACK_bp 1 /* Global NACK bit position. */ -+ -+#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -+#define USB_ATTACH_bp 0 /* Attach bit position. */ -+ -+/* USB.STATUS bit masks and bit positions */ -+#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -+#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ -+ -+#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -+#define USB_RESUME_bp 2 /* Resume bit position. */ -+ -+#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -+#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ -+ -+#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -+#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ -+ -+/* USB.ADDR bit masks and bit positions */ -+#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -+#define USB_ADDR_gp 0 /* Device Address group position. */ -+#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -+#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -+#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -+#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -+#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -+#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -+#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -+#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -+#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -+#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -+#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -+#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -+#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -+#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ -+ -+/* USB.FIFOWP bit masks and bit positions */ -+#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -+#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -+#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -+#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -+#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -+#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -+#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -+#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -+#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -+#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -+#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -+#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ -+ -+/* USB.FIFORP bit masks and bit positions */ -+#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -+#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -+#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -+#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -+#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -+#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -+#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -+#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -+#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -+#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -+#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -+#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ -+ -+/* USB.INTCTRLA bit masks and bit positions */ -+#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -+#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ -+ -+#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -+#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ -+ -+#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -+#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ -+ -+#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -+#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ -+ -+#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* USB.INTCTRLB bit masks and bit positions */ -+#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -+#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ -+ -+#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -+#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ -+ -+/* USB.INTFLAGSACLR bit masks and bit positions */ -+#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -+#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ -+ -+#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -+#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ -+ -+#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -+#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ -+ -+#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -+#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ -+ -+#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -+#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ -+ -+#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -+#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ -+ -+#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -+#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ -+ -+#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -+#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSASET bit masks and bit positions */ -+/* USB_SOFIF Predefined. */ -+/* USB_SOFIF Predefined. */ -+ -+/* USB_SUSPENDIF Predefined. */ -+/* USB_SUSPENDIF Predefined. */ -+ -+/* USB_RESUMEIF Predefined. */ -+/* USB_RESUMEIF Predefined. */ -+ -+/* USB_RSTIF Predefined. */ -+/* USB_RSTIF Predefined. */ -+ -+/* USB_CRCIF Predefined. */ -+/* USB_CRCIF Predefined. */ -+ -+/* USB_UNFIF Predefined. */ -+/* USB_UNFIF Predefined. */ -+ -+/* USB_OVFIF Predefined. */ -+/* USB_OVFIF Predefined. */ -+ -+/* USB_STALLIF Predefined. */ -+/* USB_STALLIF Predefined. */ -+ -+/* USB.INTFLAGSBCLR bit masks and bit positions */ -+#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -+#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ -+ -+#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -+#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSBSET bit masks and bit positions */ -+/* USB_TRNIF Predefined. */ -+/* USB_TRNIF Predefined. */ -+ -+/* USB_SETUPIF Predefined. */ -+/* USB_SETUPIF Predefined. */ -+ -+/* PORT - I/O Port Configuration */ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ -+ -+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -+#define PORT_SPI_bp 5 /* SPI bit position. */ -+ -+#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -+#define PORT_USART0_bp 4 /* USART0 bit position. */ -+ -+#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -+#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ -+ -+#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -+#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ -+ -+#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -+#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ -+ -+#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -+#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ -+ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC0.CTRLA bit masks and bit positions */ -+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC0.CTRLB bit masks and bit positions */ -+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ -+ -+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ -+ -+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC0.CTRLC bit masks and bit positions */ -+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ -+ -+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ -+ -+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC0.CTRLD bit masks and bit positions */ -+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC0_EVACT_gp 5 /* Event Action group position. */ -+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC0.CTRLE bit masks and bit positions */ -+#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC0.INTCTRLA bit masks and bit positions */ -+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC0.INTCTRLB bit masks and bit positions */ -+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ -+ -+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ -+ -+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC0.CTRLFCLR bit masks and bit positions */ -+#define TC0_CMD_gm 0x0C /* Command group mask. */ -+#define TC0_CMD_gp 2 /* Command group position. */ -+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC0_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC0_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC0_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC0.CTRLFSET bit masks and bit positions */ -+/* TC0_CMD Predefined. */ -+/* TC0_CMD Predefined. */ -+ -+/* TC0_LUPD Predefined. */ -+/* TC0_LUPD Predefined. */ -+ -+/* TC0_DIR Predefined. */ -+/* TC0_DIR Predefined. */ -+ -+/* TC0.CTRLGCLR bit masks and bit positions */ -+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ -+ -+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ -+ -+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC0.CTRLGSET bit masks and bit positions */ -+/* TC0_CCDBV Predefined. */ -+/* TC0_CCDBV Predefined. */ -+ -+/* TC0_CCCBV Predefined. */ -+/* TC0_CCCBV Predefined. */ -+ -+/* TC0_CCBBV Predefined. */ -+/* TC0_CCBBV Predefined. */ -+ -+/* TC0_CCABV Predefined. */ -+/* TC0_CCABV Predefined. */ -+ -+/* TC0_PERBV Predefined. */ -+/* TC0_PERBV Predefined. */ -+ -+/* TC0.INTFLAGS bit masks and bit positions */ -+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ -+ -+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ -+ -+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC1.CTRLA bit masks and bit positions */ -+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC1.CTRLB bit masks and bit positions */ -+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC1.CTRLC bit masks and bit positions */ -+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC1.CTRLD bit masks and bit positions */ -+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC1_EVACT_gp 5 /* Event Action group position. */ -+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC1.CTRLE bit masks and bit positions */ -+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ -+ -+/* TC1.INTCTRLA bit masks and bit positions */ -+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC1.INTCTRLB bit masks and bit positions */ -+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC1.CTRLFCLR bit masks and bit positions */ -+#define TC1_CMD_gm 0x0C /* Command group mask. */ -+#define TC1_CMD_gp 2 /* Command group position. */ -+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC1_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC1_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC1_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC1.CTRLFSET bit masks and bit positions */ -+/* TC1_CMD Predefined. */ -+/* TC1_CMD Predefined. */ -+ -+/* TC1_LUPD Predefined. */ -+/* TC1_LUPD Predefined. */ -+ -+/* TC1_DIR Predefined. */ -+/* TC1_DIR Predefined. */ -+ -+/* TC1.CTRLGCLR bit masks and bit positions */ -+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC1.CTRLGSET bit masks and bit positions */ -+/* TC1_CCBBV Predefined. */ -+/* TC1_CCBBV Predefined. */ -+ -+/* TC1_CCABV Predefined. */ -+/* TC1_CCABV Predefined. */ -+ -+/* TC1_PERBV Predefined. */ -+/* TC1_PERBV Predefined. */ -+ -+/* TC1.INTFLAGS bit masks and bit positions */ -+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+/* TC2.CTRLA bit masks and bit positions */ -+#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC2.CTRLB bit masks and bit positions */ -+#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -+#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ -+ -+#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -+#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ -+ -+#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -+#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ -+ -+#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -+#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ -+ -+#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -+#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ -+ -+#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -+#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ -+ -+#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -+#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ -+ -+#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -+#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ -+ -+/* TC2.CTRLC bit masks and bit positions */ -+#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -+#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ -+ -+#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -+#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ -+ -+#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -+#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ -+ -+#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -+#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ -+ -+#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -+#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ -+ -+#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -+#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ -+ -+#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -+#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ -+ -+#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -+#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ -+ -+/* TC2.CTRLE bit masks and bit positions */ -+#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC2.INTCTRLA bit masks and bit positions */ -+#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -+#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -+#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -+#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -+#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -+#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ -+ -+#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -+#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -+#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -+#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -+#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -+#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ -+ -+/* TC2.INTCTRLB bit masks and bit positions */ -+#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -+#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -+#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -+#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -+#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -+#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -+#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -+#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -+#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -+#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -+#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -+#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -+#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -+#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -+#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -+#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -+#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -+#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -+#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -+#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -+#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ -+ -+/* TC2.CTRLF bit masks and bit positions */ -+#define TC2_CMD_gm 0x0C /* Command group mask. */ -+#define TC2_CMD_gp 2 /* Command group position. */ -+#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC2_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -+#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -+#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -+#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -+#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -+#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ -+ -+/* TC2.INTFLAGS bit masks and bit positions */ -+#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -+#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ -+ -+#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -+#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ -+ -+#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -+#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ -+ -+#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -+#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ -+ -+#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ -+ -+#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ -+ -+/* AWEX - Timer/Counter Advanced Waveform Extension */ -+/* AWEX.CTRL bit masks and bit positions */ -+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ -+ -+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ -+ -+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ -+ -+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ -+ -+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ -+ -+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ -+ -+/* AWEX.FDCTRL bit masks and bit positions */ -+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ -+ -+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ -+ -+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ -+ -+/* AWEX.STATUS bit masks and bit positions */ -+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ -+ -+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ -+ -+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ -+ -+/* AWEX.STATUSSET bit masks and bit positions */ -+/* AWEX_FDF Predefined. */ -+/* AWEX_FDF Predefined. */ -+ -+/* AWEX_DTHSBUFV Predefined. */ -+/* AWEX_DTHSBUFV Predefined. */ -+ -+/* AWEX_DTLSBUFV Predefined. */ -+/* AWEX_DTLSBUFV Predefined. */ -+ -+/* HIRES - Timer/Counter High-Resolution Extension */ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -+#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -+#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -+#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -+#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -+#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -+#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -+#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -+#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -+#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -+#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -+#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -+#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -+#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -+#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -+#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -+#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -+#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -+#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ -+ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -+#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -+#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* LOCKBIT - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT0_vect_num 2 -+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -+#define PORTC_INT1_vect_num 3 -+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT0_vect_num 4 -+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -+#define PORTR_INT1_vect_num 5 -+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ -+ -+/* DMA interrupt vectors */ -+#define DMA_CH0_vect_num 6 -+#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -+#define DMA_CH1_vect_num 7 -+#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -+#define DMA_CH2_vect_num 8 -+#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -+#define DMA_CH3_vect_num 9 -+#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ -+ -+/* RTC interrupt vectors */ -+#define RTC_OVF_vect_num 10 -+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -+#define RTC_COMP_vect_num 11 -+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 12 -+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 13 -+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_OVF_vect_num 14 -+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LUNF_vect_num 14 -+#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_ERR_vect_num 15 -+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_HUNF_vect_num 15 -+#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCA_vect_num 16 -+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPA_vect_num 16 -+#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCB_vect_num 17 -+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPB_vect_num 17 -+#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCC_vect_num 18 -+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPC_vect_num 18 -+#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCD_vect_num 19 -+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPD_vect_num 19 -+#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ -+ -+/* TCC1 interrupt vectors */ -+#define TCC1_OVF_vect_num 20 -+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -+#define TCC1_ERR_vect_num 21 -+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -+#define TCC1_CCA_vect_num 22 -+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -+#define TCC1_CCB_vect_num 23 -+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 24 -+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 25 -+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 26 -+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 27 -+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ -+ -+/* USARTC1 interrupt vectors */ -+#define USARTC1_RXC_vect_num 28 -+#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -+#define USARTC1_DRE_vect_num 29 -+#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -+#define USARTC1_TXC_vect_num 30 -+#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ -+ -+/* AES interrupt vectors */ -+#define AES_INT_vect_num 31 -+#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 32 -+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -+#define NVM_SPM_vect_num 33 -+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ -+ -+/* PORTB interrupt vectors */ -+#define PORTB_INT0_vect_num 34 -+#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -+#define PORTB_INT1_vect_num 35 -+#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ -+ -+/* ACB interrupt vectors */ -+#define ACB_AC0_vect_num 36 -+#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ -+#define ACB_AC1_vect_num 37 -+#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ -+#define ACB_ACW_vect_num 38 -+#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ -+ -+/* ADCB interrupt vectors */ -+#define ADCB_CH0_vect_num 39 -+#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ -+#define ADCB_CH1_vect_num 40 -+#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ -+#define ADCB_CH2_vect_num 41 -+#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ -+#define ADCB_CH3_vect_num 42 -+#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ -+ -+/* PORTE interrupt vectors */ -+#define PORTE_INT0_vect_num 43 -+#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -+#define PORTE_INT1_vect_num 44 -+#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ -+ -+/* TWIE interrupt vectors */ -+#define TWIE_TWIS_vect_num 45 -+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -+#define TWIE_TWIM_vect_num 46 -+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_OVF_vect_num 47 -+#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LUNF_vect_num 47 -+#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_ERR_vect_num 48 -+#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_HUNF_vect_num 48 -+#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCA_vect_num 49 -+#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPA_vect_num 49 -+#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCB_vect_num 50 -+#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPB_vect_num 50 -+#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCC_vect_num 51 -+#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPC_vect_num 51 -+#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCD_vect_num 52 -+#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPD_vect_num 52 -+#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ -+ -+/* TCE1 interrupt vectors */ -+#define TCE1_OVF_vect_num 53 -+#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ -+#define TCE1_ERR_vect_num 54 -+#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ -+#define TCE1_CCA_vect_num 55 -+#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ -+#define TCE1_CCB_vect_num 56 -+#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ -+ -+/* SPIE interrupt vectors */ -+#define SPIE_INT_vect_num 57 -+#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ -+ -+/* USARTE0 interrupt vectors */ -+#define USARTE0_RXC_vect_num 58 -+#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -+#define USARTE0_DRE_vect_num 59 -+#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -+#define USARTE0_TXC_vect_num 60 -+#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ -+ -+/* USARTE1 interrupt vectors */ -+#define USARTE1_RXC_vect_num 61 -+#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ -+#define USARTE1_DRE_vect_num 62 -+#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ -+#define USARTE1_TXC_vect_num 63 -+#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT0_vect_num 64 -+#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -+#define PORTD_INT1_vect_num 65 -+#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ -+ -+/* PORTA interrupt vectors */ -+#define PORTA_INT0_vect_num 66 -+#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -+#define PORTA_INT1_vect_num 67 -+#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ -+ -+/* ACA interrupt vectors */ -+#define ACA_AC0_vect_num 68 -+#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -+#define ACA_AC1_vect_num 69 -+#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -+#define ACA_ACW_vect_num 70 -+#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ -+ -+/* ADCA interrupt vectors */ -+#define ADCA_CH0_vect_num 71 -+#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -+#define ADCA_CH1_vect_num 72 -+#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -+#define ADCA_CH2_vect_num 73 -+#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -+#define ADCA_CH3_vect_num 74 -+#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_OVF_vect_num 77 -+#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LUNF_vect_num 77 -+#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_ERR_vect_num 78 -+#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_HUNF_vect_num 78 -+#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCA_vect_num 79 -+#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPA_vect_num 79 -+#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCB_vect_num 80 -+#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPB_vect_num 80 -+#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCC_vect_num 81 -+#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPC_vect_num 81 -+#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCD_vect_num 82 -+#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPD_vect_num 82 -+#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ -+ -+/* TCD1 interrupt vectors */ -+#define TCD1_OVF_vect_num 83 -+#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -+#define TCD1_ERR_vect_num 84 -+#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -+#define TCD1_CCA_vect_num 85 -+#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -+#define TCD1_CCB_vect_num 86 -+#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ -+ -+/* SPID interrupt vectors */ -+#define SPID_INT_vect_num 87 -+#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ -+ -+/* USARTD0 interrupt vectors */ -+#define USARTD0_RXC_vect_num 88 -+#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -+#define USARTD0_DRE_vect_num 89 -+#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -+#define USARTD0_TXC_vect_num 90 -+#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ -+ -+/* USARTD1 interrupt vectors */ -+#define USARTD1_RXC_vect_num 91 -+#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -+#define USARTD1_DRE_vect_num 92 -+#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -+#define USARTD1_TXC_vect_num 93 -+#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ -+ -+/* PORTF interrupt vectors */ -+#define PORTF_INT0_vect_num 104 -+#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -+#define PORTF_INT1_vect_num 105 -+#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_OVF_vect_num 108 -+#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LUNF_vect_num 108 -+#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_ERR_vect_num 109 -+#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_HUNF_vect_num 109 -+#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCA_vect_num 110 -+#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPA_vect_num 110 -+#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCB_vect_num 111 -+#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPB_vect_num 111 -+#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCC_vect_num 112 -+#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPC_vect_num 112 -+#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCD_vect_num 113 -+#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPD_vect_num 113 -+#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ -+ -+/* USARTF0 interrupt vectors */ -+#define USARTF0_RXC_vect_num 119 -+#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ -+#define USARTF0_DRE_vect_num 120 -+#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ -+#define USARTF0_TXC_vect_num 121 -+#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ -+ -+/* USB interrupt vectors */ -+#define USB_BUSEVENT_vect_num 125 -+#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -+#define USB_TRNCOMPL_vect_num 126 -+#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (127 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (270336) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (262144) -+#define APP_SECTION_PAGE_SIZE (512) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0x3E000) -+#define APPTABLE_SECTION_SIZE (8192) -+#define APPTABLE_SECTION_PAGE_SIZE (512) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x40000) -+#define BOOT_SECTION_SIZE (8192) -+#define BOOT_SECTION_PAGE_SIZE (512) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (24576) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (4096) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (16384) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (4096) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (6) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (512) -+#define USER_SIGNATURES_PAGE_SIZE (512) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (52) -+#define PROD_SIGNATURES_PAGE_SIZE (512) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 512 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 6 -+ -+/* Fuse Byte 0 */ -+#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -+#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -+#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -+#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -+#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -+#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -+#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -+#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -+#define FUSE0_DEFAULT (0xFF) -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x98 -+#define SIGNATURE_2 0x42 -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA256A3U_H_INCLUDED */ -+ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox256a3u.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA256A3U_H_INCLUDED ++#define _AVR_ATXMEGA256A3U_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t USBCTRL; /* USB Control Register */ ++} CLK_t; ++ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t PRPB; /* Power Reduction Port B */ ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++/* USB Prescaler Division Factor */ ++typedef enum CLK_USBPSDIV_enum ++{ ++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ ++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ ++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ ++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ ++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ ++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ ++} CLK_USBPSDIV_t; ++ ++/* USB Clock Source */ ++typedef enum CLK_USBSRC_enum ++{ ++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ ++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ ++} CLK_USBSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 2 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC2MCREF_enum ++{ ++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC2MCREF_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++ register8_t EBIOUT; /* EBI Output register */ ++ register8_t EVOUTSEL; /* Event Output Select */ ++} PORTCFG_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP02MAP_enum ++{ ++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP02MAP_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP13MAP_enum ++{ ++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP13MAP_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Clock and Event Output Port */ ++typedef enum PORTCFG_CLKEVPIN_enum ++{ ++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ ++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ ++} PORTCFG_CLKEVPIN_t; ++ ++/* EBI Address Output Port */ ++typedef enum PORTCFG_EBIADROUT_enum ++{ ++ PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ ++ PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ ++ PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ ++ PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ ++} PORTCFG_EBIADROUT_t; ++ ++/* EBI Chip Select Output Port */ ++typedef enum PORTCFG_EBICSOUT_enum ++{ ++ PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ ++} PORTCFG_EBICSOUT_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ ++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ ++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ ++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ ++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AES - AES Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* AES Module */ ++typedef struct AES_struct ++{ ++ register8_t CTRL; /* AES Control Register */ ++ register8_t STATUS; /* AES Status Register */ ++ register8_t STATE; /* AES State Register */ ++ register8_t KEY; /* AES Key Register */ ++ register8_t INTCTRL; /* AES Interrupt Control Register */ ++} AES_t; ++ ++/* Interrupt level */ ++typedef enum AES_INTLVL_enum ++{ ++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} AES_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ ++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ ++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ ++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Channel */ ++typedef struct DMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Address Control */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ ++ register8_t REPCNT; /* Channel Repeat Count */ ++ register8_t reserved_0x07; ++ register8_t SRCADDR0; /* Channel Source Address 0 */ ++ register8_t SRCADDR1; /* Channel Source Address 1 */ ++ register8_t SRCADDR2; /* Channel Source Address 2 */ ++ register8_t reserved_0x0B; ++ register8_t DESTADDR0; /* Channel Destination Address 0 */ ++ register8_t DESTADDR1; /* Channel Destination Address 1 */ ++ register8_t DESTADDR2; /* Channel Destination Address 2 */ ++ register8_t reserved_0x0F; ++} DMA_CH_t; ++ ++ ++/* DMA Controller */ ++typedef struct DMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ DMA_CH_t CH0; /* DMA Channel 0 */ ++ DMA_CH_t CH1; /* DMA Channel 1 */ ++ DMA_CH_t CH2; /* DMA Channel 2 */ ++ DMA_CH_t CH3; /* DMA Channel 3 */ ++} DMA_t; ++ ++/* Burst mode */ ++typedef enum DMA_CH_BURSTLEN_enum ++{ ++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ ++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ ++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ ++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ ++} DMA_CH_BURSTLEN_t; ++ ++/* Source address reload mode */ ++typedef enum DMA_CH_SRCRELOAD_enum ++{ ++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ ++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ ++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ ++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ ++} DMA_CH_SRCRELOAD_t; ++ ++/* Source addressing mode */ ++typedef enum DMA_CH_SRCDIR_enum ++{ ++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ ++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ ++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ ++} DMA_CH_SRCDIR_t; ++ ++/* Destination adress reload mode */ ++typedef enum DMA_CH_DESTRELOAD_enum ++{ ++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ ++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ ++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ ++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ ++} DMA_CH_DESTRELOAD_t; ++ ++/* Destination adressing mode */ ++typedef enum DMA_CH_DESTDIR_enum ++{ ++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ ++} DMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum DMA_CH_TRIGSRC_enum ++{ ++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ ++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ ++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ ++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ ++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ ++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ ++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ ++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ ++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ ++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ ++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ ++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ ++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ ++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ ++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ ++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ ++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ ++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ ++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ ++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ ++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ ++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ ++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ ++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ ++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ ++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ ++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ ++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ ++} DMA_CH_TRIGSRC_t; ++ ++/* Double buffering mode */ ++typedef enum DMA_DBUFMODE_enum ++{ ++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ ++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ ++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ ++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ ++} DMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum DMA_PRIMODE_enum ++{ ++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ ++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ ++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ ++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ ++} DMA_PRIMODE_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_ERRINTLVL_enum ++{ ++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ ++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ ++} DMA_CH_ERRINTLVL_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_TRNINTLVL_enum ++{ ++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ ++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ ++} DMA_CH_TRNINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ ++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ ++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ ++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t CH4CTRL; /* Channel 4 Control Register */ ++ register8_t CH5CTRL; /* Channel 5 Control Register */ ++ register8_t CH6CTRL; /* Channel 6 Control Register */ ++ register8_t CH7CTRL; /* Channel 7 Control Register */ ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ ++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ ++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ ++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ ++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ ++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ ++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ ++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ ++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ ++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ ++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ ++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ ++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ ++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ ++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ ++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ ++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ ++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t reserved_0x07; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ _WORDREGISTER(CH1RES); /* Channel 1 Result */ ++ _WORDREGISTER(CH2RES); /* Channel 2 Result */ ++ _WORDREGISTER(CH3RES); /* Channel 3 Result */ ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++ ADC_CH_t CH1; /* ADC Channel 1 */ ++ ADC_CH_t CH2; /* ADC Channel 2 */ ++ ADC_CH_t CH3; /* ADC Channel 3 */ ++} ADC_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ ++ ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ ++ ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ ++ ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Current Limitation Mode */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ ++} ADC_CURRLIMIT_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Channel sweep selection */ ++typedef enum ADC_SWEEP_enum ++{ ++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ ++} ADC_SWEEP_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* DMA request selection */ ++typedef enum ADC_DMASEL_enum ++{ ++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ ++} ADC_DMASEL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DAC - Digital/Analog Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Digital-to-Analog Converter */ ++typedef struct DAC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t EVCTRL; /* Event Input Control */ ++ register8_t reserved_0x04; ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0GAINCAL; /* Gain Calibration */ ++ register8_t CH0OFFSETCAL; /* Offset Calibration */ ++ register8_t CH1GAINCAL; /* Gain Calibration */ ++ register8_t CH1OFFSETCAL; /* Offset Calibration */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ ++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ ++} DAC_t; ++ ++/* Output channel selection */ ++typedef enum DAC_CHSEL_enum ++{ ++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ ++ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ ++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ ++} DAC_CHSEL_t; ++ ++/* Reference voltage selection */ ++typedef enum DAC_REFSEL_enum ++{ ++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ ++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ ++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ ++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ ++} DAC_REFSEL_t; ++ ++/* Event channel selection */ ++typedef enum DAC_EVSEL_enum ++{ ++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ ++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ ++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ ++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ ++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ ++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ ++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ ++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ ++} DAC_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* SDA Hold Time */ ++typedef enum TWI_SDAHOLD_enum ++{ ++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ ++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ ++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ ++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ ++} TWI_SDAHOLD_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USB - USB ++-------------------------------------------------------------------------- ++*/ ++ ++/* USB Endpoint */ ++typedef struct USB_EP_struct ++{ ++ register8_t STATUS; /* Endpoint Status */ ++ register8_t CTRL; /* Endpoint Control */ ++ _WORDREGISTER(CNT); /* USB Endpoint Counter */ ++ _WORDREGISTER(DATAPTR); /* Data Pointer */ ++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ ++} USB_EP_t; ++ ++ ++/* Universal Serial Bus */ ++typedef struct USB_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t FIFOWP; /* FIFO Write Pointer Register */ ++ register8_t FIFORP; /* FIFO Read Pointer Register */ ++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ ++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ ++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ ++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t reserved_0x20; ++ register8_t reserved_0x21; ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t CAL0; /* Calibration Byte 0 */ ++ register8_t CAL1; /* Calibration Byte 1 */ ++} USB_t; ++ ++ ++/* USB Endpoint Table */ ++typedef struct USB_EP_TABLE_struct ++{ ++ USB_EP_t EP0OUT; /* Endpoint 0 */ ++ USB_EP_t EP0IN; /* Endpoint 0 */ ++ USB_EP_t EP1OUT; /* Endpoint 1 */ ++ USB_EP_t EP1IN; /* Endpoint 1 */ ++ USB_EP_t EP2OUT; /* Endpoint 2 */ ++ USB_EP_t EP2IN; /* Endpoint 2 */ ++ USB_EP_t EP3OUT; /* Endpoint 3 */ ++ USB_EP_t EP3IN; /* Endpoint 3 */ ++ USB_EP_t EP4OUT; /* Endpoint 4 */ ++ USB_EP_t EP4IN; /* Endpoint 4 */ ++ USB_EP_t EP5OUT; /* Endpoint 5 */ ++ USB_EP_t EP5IN; /* Endpoint 5 */ ++ USB_EP_t EP6OUT; /* Endpoint 6 */ ++ USB_EP_t EP6IN; /* Endpoint 6 */ ++ USB_EP_t EP7OUT; /* Endpoint 7 */ ++ USB_EP_t EP7IN; /* Endpoint 7 */ ++ USB_EP_t EP8OUT; /* Endpoint 8 */ ++ USB_EP_t EP8IN; /* Endpoint 8 */ ++ USB_EP_t EP9OUT; /* Endpoint 9 */ ++ USB_EP_t EP9IN; /* Endpoint 9 */ ++ USB_EP_t EP10OUT; /* Endpoint 10 */ ++ USB_EP_t EP10IN; /* Endpoint 10 */ ++ USB_EP_t EP11OUT; /* Endpoint 11 */ ++ USB_EP_t EP11IN; /* Endpoint 11 */ ++ USB_EP_t EP12OUT; /* Endpoint 12 */ ++ USB_EP_t EP12IN; /* Endpoint 12 */ ++ USB_EP_t EP13OUT; /* Endpoint 13 */ ++ USB_EP_t EP13IN; /* Endpoint 13 */ ++ USB_EP_t EP14OUT; /* Endpoint 14 */ ++ USB_EP_t EP14IN; /* Endpoint 14 */ ++ USB_EP_t EP15OUT; /* Endpoint 15 */ ++ USB_EP_t EP15IN; /* Endpoint 15 */ ++ register8_t reserved_0x100; ++ register8_t reserved_0x101; ++ register8_t reserved_0x102; ++ register8_t reserved_0x103; ++ register8_t reserved_0x104; ++ register8_t reserved_0x105; ++ register8_t reserved_0x106; ++ register8_t reserved_0x107; ++ register8_t reserved_0x108; ++ register8_t reserved_0x109; ++ register8_t reserved_0x10A; ++ register8_t reserved_0x10B; ++ register8_t reserved_0x10C; ++ register8_t reserved_0x10D; ++ register8_t reserved_0x10E; ++ register8_t reserved_0x10F; ++ register8_t FRAMENUML; /* Frame Number Low Byte */ ++ register8_t FRAMENUMH; /* Frame Number High Byte */ ++} USB_EP_TABLE_t; ++ ++/* Interrupt level */ ++typedef enum USB_INTLVL_enum ++{ ++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} USB_INTLVL_t; ++ ++/* USB Endpoint Type */ ++typedef enum USB_EP_TYPE_enum ++{ ++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ ++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ ++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ ++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ ++} USB_EP_TYPE_t; ++ ++/* USB Endpoint Buffersize */ ++typedef enum USB_EP_BUFSIZE_enum ++{ ++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ ++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ ++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ ++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ ++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ ++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ ++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ ++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ ++} USB_EP_BUFSIZE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - I/O Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* I/O Port Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Byte Mode */ ++typedef enum TC_BYTEM_enum ++{ ++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ ++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ ++} TC_BYTEM_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC2 - 16-bit Timer/Counter type 2 ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter type 2 */ ++typedef struct TC2_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t reserved_0x03; ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t reserved_0x08; ++ register8_t CTRLF; /* Control Register F */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t LCNT; /* Low Byte Count */ ++ register8_t HCNT; /* High Byte Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t LPER; /* Low Byte Period */ ++ register8_t HPER; /* High Byte Period */ ++ register8_t LCMPA; /* Low Byte Compare A */ ++ register8_t HCMPA; /* High Byte Compare A */ ++ register8_t LCMPB; /* Low Byte Compare B */ ++ register8_t HCMPB; /* High Byte Compare B */ ++ register8_t LCMPC; /* Low Byte Compare C */ ++ register8_t HCMPC; /* High Byte Compare C */ ++ register8_t LCMPD; /* Low Byte Compare D */ ++ register8_t HCMPD; /* High Byte Compare D */ ++} TC2_t; ++ ++/* Clock Selection */ ++typedef enum TC2_CLKSEL_enum ++{ ++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC2_CLKSEL_t; ++ ++/* Byte Mode */ ++typedef enum TC2_BYTEM_enum ++{ ++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ ++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ ++} TC2_BYTEM_t; ++ ++/* High Byte Underflow Interrupt Level */ ++typedef enum TC2_HUNFINTLVL_enum ++{ ++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_HUNFINTLVL_t; ++ ++/* Low Byte Underflow Interrupt Level */ ++typedef enum TC2_LUNFINTLVL_enum ++{ ++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LUNFINTLVL_t; ++ ++/* Low Byte Compare D Interrupt Level */ ++typedef enum TC2_LCMPDINTLVL_enum ++{ ++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC2_LCMPDINTLVL_t; ++ ++/* Low Byte Compare C Interrupt Level */ ++typedef enum TC2_LCMPCINTLVL_enum ++{ ++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC2_LCMPCINTLVL_t; ++ ++/* Low Byte Compare B Interrupt Level */ ++typedef enum TC2_LCMPBINTLVL_enum ++{ ++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_LCMPBINTLVL_t; ++ ++/* Low Byte Compare A Interrupt Level */ ++typedef enum TC2_LCMPAINTLVL_enum ++{ ++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LCMPAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMD_enum ++{ ++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC2_CMD_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMDEN_enum ++{ ++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ ++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ ++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ ++} TC2_CMDEN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AWEX - Timer/Counter Advanced Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - Timer/Counter High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t FUSEBYTE0; /* JTAG User ID */ ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* Timer Oscillator pin location */ ++typedef enum TOSCSEL_enum ++{ ++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ ++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ ++} TOSCSEL_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* BOD operation */ ++typedef enum BODACT_enum ++{ ++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BODACT_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WDP_enum ++{ ++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ ++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ ++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ ++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ ++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ ++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ ++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ ++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ ++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ ++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ ++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ ++} WDP_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LOCKBIT - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ ++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t USBCAL0; /* USB Calibration Byte 0 */ ++ register8_t USBCAL1; /* USB Calibration Byte 1 */ ++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ ++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ ++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ ++ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ ++ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ ++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ ++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ ++ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ ++ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++ register8_t reserved_0x40; ++ register8_t reserved_0x41; ++ register8_t reserved_0x42; ++ register8_t reserved_0x43; ++ register8_t reserved_0x44; ++ register8_t reserved_0x45; ++ register8_t reserved_0x46; ++ register8_t reserved_0x47; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define AES (*(AES_t *) 0x00C0) /* AES Module */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ ++#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ ++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ ++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ ++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ ++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ ++#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ ++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ ++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ ++#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ ++#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ ++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ ++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ ++#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ ++#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ ++#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++#define GPIO_GPIOR4 _SFR_MEM8(0x0004) ++#define GPIO_GPIOR5 _SFR_MEM8(0x0005) ++#define GPIO_GPIOR6 _SFR_MEM8(0x0006) ++#define GPIO_GPIOR7 _SFR_MEM8(0x0007) ++#define GPIO_GPIOR8 _SFR_MEM8(0x0008) ++#define GPIO_GPIOR9 _SFR_MEM8(0x0009) ++#define GPIO_GPIORA _SFR_MEM8(0x000A) ++#define GPIO_GPIORB _SFR_MEM8(0x000B) ++#define GPIO_GPIORC _SFR_MEM8(0x000C) ++#define GPIO_GPIORD _SFR_MEM8(0x000D) ++#define GPIO_GPIORE _SFR_MEM8(0x000E) ++#define GPIO_GPIORF _SFR_MEM8(0x000F) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++#define GPIO_GPIO4 _SFR_MEM8(0x0004) ++#define GPIO_GPIO5 _SFR_MEM8(0x0005) ++#define GPIO_GPIO6 _SFR_MEM8(0x0006) ++#define GPIO_GPIO7 _SFR_MEM8(0x0007) ++#define GPIO_GPIO8 _SFR_MEM8(0x0008) ++#define GPIO_GPIO9 _SFR_MEM8(0x0009) ++#define GPIO_GPIOA _SFR_MEM8(0x000A) ++#define GPIO_GPIOB _SFR_MEM8(0x000B) ++#define GPIO_GPIOC _SFR_MEM8(0x000C) ++#define GPIO_GPIOD _SFR_MEM8(0x000D) ++#define GPIO_GPIOE _SFR_MEM8(0x000E) ++#define GPIO_GPIOF _SFR_MEM8(0x000F) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) ++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) ++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) ++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) ++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) ++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) ++#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) ++#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) ++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) ++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) ++#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) ++#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++#define CLK_USBCTRL _SFR_MEM8(0x0044) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLL - DFLL */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPB _SFR_MEM8(0x0072) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) ++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) ++ ++/* AES - AES Module */ ++#define AES_CTRL _SFR_MEM8(0x00C0) ++#define AES_STATUS _SFR_MEM8(0x00C1) ++#define AES_STATE _SFR_MEM8(0x00C2) ++#define AES_KEY _SFR_MEM8(0x00C3) ++#define AES_INTCTRL _SFR_MEM8(0x00C4) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* DMA - DMA Controller */ ++#define DMA_CTRL _SFR_MEM8(0x0100) ++#define DMA_INTFLAGS _SFR_MEM8(0x0103) ++#define DMA_STATUS _SFR_MEM8(0x0104) ++#define DMA_TEMP _SFR_MEM16(0x0106) ++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) ++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) ++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) ++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) ++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) ++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) ++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) ++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) ++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) ++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) ++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) ++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) ++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) ++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) ++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) ++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) ++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) ++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) ++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) ++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) ++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) ++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) ++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) ++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) ++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) ++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) ++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) ++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) ++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) ++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) ++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) ++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) ++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) ++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) ++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) ++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) ++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) ++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) ++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) ++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) ++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) ++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH4MUX _SFR_MEM8(0x0184) ++#define EVSYS_CH5MUX _SFR_MEM8(0x0185) ++#define EVSYS_CH6MUX _SFR_MEM8(0x0186) ++#define EVSYS_CH7MUX _SFR_MEM8(0x0187) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) ++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) ++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) ++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CH1RES _SFR_MEM16(0x0212) ++#define ADCA_CH2RES _SFR_MEM16(0x0214) ++#define ADCA_CH3RES _SFR_MEM16(0x0216) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) ++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) ++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) ++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) ++#define ADCA_CH1_RES _SFR_MEM16(0x022C) ++#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) ++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) ++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) ++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) ++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) ++#define ADCA_CH2_RES _SFR_MEM16(0x0234) ++#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) ++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) ++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) ++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) ++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) ++#define ADCA_CH3_RES _SFR_MEM16(0x023C) ++#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCB_CTRLA _SFR_MEM8(0x0240) ++#define ADCB_CTRLB _SFR_MEM8(0x0241) ++#define ADCB_REFCTRL _SFR_MEM8(0x0242) ++#define ADCB_EVCTRL _SFR_MEM8(0x0243) ++#define ADCB_PRESCALER _SFR_MEM8(0x0244) ++#define ADCB_INTFLAGS _SFR_MEM8(0x0246) ++#define ADCB_TEMP _SFR_MEM8(0x0247) ++#define ADCB_CAL _SFR_MEM16(0x024C) ++#define ADCB_CH0RES _SFR_MEM16(0x0250) ++#define ADCB_CH1RES _SFR_MEM16(0x0252) ++#define ADCB_CH2RES _SFR_MEM16(0x0254) ++#define ADCB_CH3RES _SFR_MEM16(0x0256) ++#define ADCB_CMP _SFR_MEM16(0x0258) ++#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) ++#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) ++#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) ++#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) ++#define ADCB_CH0_RES _SFR_MEM16(0x0264) ++#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) ++#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) ++#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) ++#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) ++#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) ++#define ADCB_CH1_RES _SFR_MEM16(0x026C) ++#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) ++#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) ++#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) ++#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) ++#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) ++#define ADCB_CH2_RES _SFR_MEM16(0x0274) ++#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) ++#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) ++#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) ++#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) ++#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) ++#define ADCB_CH3_RES _SFR_MEM16(0x027C) ++#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) ++ ++/* DAC - Digital-to-Analog Converter */ ++#define DACB_CTRLA _SFR_MEM8(0x0320) ++#define DACB_CTRLB _SFR_MEM8(0x0321) ++#define DACB_CTRLC _SFR_MEM8(0x0322) ++#define DACB_EVCTRL _SFR_MEM8(0x0323) ++#define DACB_STATUS _SFR_MEM8(0x0325) ++#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) ++#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) ++#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) ++#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) ++#define DACB_CH0DATA _SFR_MEM16(0x0338) ++#define DACB_CH1DATA _SFR_MEM16(0x033A) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* AC - Analog Comparator */ ++#define ACB_AC0CTRL _SFR_MEM8(0x0390) ++#define ACB_AC1CTRL _SFR_MEM8(0x0391) ++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) ++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) ++#define ACB_CTRLA _SFR_MEM8(0x0394) ++#define ACB_CTRLB _SFR_MEM8(0x0395) ++#define ACB_WINCTRL _SFR_MEM8(0x0396) ++#define ACB_STATUS _SFR_MEM8(0x0397) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* USB - Universal Serial Bus */ ++#define USB_CTRLA _SFR_MEM8(0x04C0) ++#define USB_CTRLB _SFR_MEM8(0x04C1) ++#define USB_STATUS _SFR_MEM8(0x04C2) ++#define USB_ADDR _SFR_MEM8(0x04C3) ++#define USB_FIFOWP _SFR_MEM8(0x04C4) ++#define USB_FIFORP _SFR_MEM8(0x04C5) ++#define USB_EPPTR _SFR_MEM16(0x04C6) ++#define USB_INTCTRLA _SFR_MEM8(0x04C8) ++#define USB_INTCTRLB _SFR_MEM8(0x04C9) ++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) ++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) ++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) ++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) ++#define USB_CAL0 _SFR_MEM8(0x04FA) ++#define USB_CAL1 _SFR_MEM8(0x04FB) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_REMAP _SFR_MEM8(0x060E) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_REMAP _SFR_MEM8(0x062E) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_REMAP _SFR_MEM8(0x068E) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORT - I/O Ports */ ++#define PORTF_DIR _SFR_MEM8(0x06A0) ++#define PORTF_DIRSET _SFR_MEM8(0x06A1) ++#define PORTF_DIRCLR _SFR_MEM8(0x06A2) ++#define PORTF_DIRTGL _SFR_MEM8(0x06A3) ++#define PORTF_OUT _SFR_MEM8(0x06A4) ++#define PORTF_OUTSET _SFR_MEM8(0x06A5) ++#define PORTF_OUTCLR _SFR_MEM8(0x06A6) ++#define PORTF_OUTTGL _SFR_MEM8(0x06A7) ++#define PORTF_IN _SFR_MEM8(0x06A8) ++#define PORTF_INTCTRL _SFR_MEM8(0x06A9) ++#define PORTF_INT0MASK _SFR_MEM8(0x06AA) ++#define PORTF_INT1MASK _SFR_MEM8(0x06AB) ++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) ++#define PORTF_REMAP _SFR_MEM8(0x06AE) ++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) ++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) ++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) ++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) ++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) ++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) ++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) ++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCC2_CTRLA _SFR_MEM8(0x0800) ++#define TCC2_CTRLB _SFR_MEM8(0x0801) ++#define TCC2_CTRLC _SFR_MEM8(0x0802) ++#define TCC2_CTRLE _SFR_MEM8(0x0804) ++#define TCC2_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC2_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC2_CTRLF _SFR_MEM8(0x0809) ++#define TCC2_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC2_LCNT _SFR_MEM8(0x0820) ++#define TCC2_HCNT _SFR_MEM8(0x0821) ++#define TCC2_LPER _SFR_MEM8(0x0826) ++#define TCC2_HPER _SFR_MEM8(0x0827) ++#define TCC2_LCMPA _SFR_MEM8(0x0828) ++#define TCC2_HCMPA _SFR_MEM8(0x0829) ++#define TCC2_LCMPB _SFR_MEM8(0x082A) ++#define TCC2_HCMPB _SFR_MEM8(0x082B) ++#define TCC2_LCMPC _SFR_MEM8(0x082C) ++#define TCC2_HCMPC _SFR_MEM8(0x082D) ++#define TCC2_LCMPD _SFR_MEM8(0x082E) ++#define TCC2_HCMPD _SFR_MEM8(0x082F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_STATUSSET _SFR_MEM8(0x0885) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1_DATA _SFR_MEM8(0x08B0) ++#define USARTC1_STATUS _SFR_MEM8(0x08B1) ++#define USARTC1_CTRLA _SFR_MEM8(0x08B3) ++#define USARTC1_CTRLB _SFR_MEM8(0x08B4) ++#define USARTC1_CTRLC _SFR_MEM8(0x08B5) ++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) ++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCD2_CTRLA _SFR_MEM8(0x0900) ++#define TCD2_CTRLB _SFR_MEM8(0x0901) ++#define TCD2_CTRLC _SFR_MEM8(0x0902) ++#define TCD2_CTRLE _SFR_MEM8(0x0904) ++#define TCD2_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD2_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD2_CTRLF _SFR_MEM8(0x0909) ++#define TCD2_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD2_LCNT _SFR_MEM8(0x0920) ++#define TCD2_HCNT _SFR_MEM8(0x0921) ++#define TCD2_LPER _SFR_MEM8(0x0926) ++#define TCD2_HPER _SFR_MEM8(0x0927) ++#define TCD2_LCMPA _SFR_MEM8(0x0928) ++#define TCD2_HCMPA _SFR_MEM8(0x0929) ++#define TCD2_LCMPB _SFR_MEM8(0x092A) ++#define TCD2_HCMPB _SFR_MEM8(0x092B) ++#define TCD2_LCMPC _SFR_MEM8(0x092C) ++#define TCD2_HCMPC _SFR_MEM8(0x092D) ++#define TCD2_LCMPD _SFR_MEM8(0x092E) ++#define TCD2_HCMPD _SFR_MEM8(0x092F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCD1_CTRLA _SFR_MEM8(0x0940) ++#define TCD1_CTRLB _SFR_MEM8(0x0941) ++#define TCD1_CTRLC _SFR_MEM8(0x0942) ++#define TCD1_CTRLD _SFR_MEM8(0x0943) ++#define TCD1_CTRLE _SFR_MEM8(0x0944) ++#define TCD1_INTCTRLA _SFR_MEM8(0x0946) ++#define TCD1_INTCTRLB _SFR_MEM8(0x0947) ++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) ++#define TCD1_CTRLFSET _SFR_MEM8(0x0949) ++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) ++#define TCD1_CTRLGSET _SFR_MEM8(0x094B) ++#define TCD1_INTFLAGS _SFR_MEM8(0x094C) ++#define TCD1_TEMP _SFR_MEM8(0x094F) ++#define TCD1_CNT _SFR_MEM16(0x0960) ++#define TCD1_PER _SFR_MEM16(0x0966) ++#define TCD1_CCA _SFR_MEM16(0x0968) ++#define TCD1_CCB _SFR_MEM16(0x096A) ++#define TCD1_PERBUF _SFR_MEM16(0x0976) ++#define TCD1_CCABUF _SFR_MEM16(0x0978) ++#define TCD1_CCBBUF _SFR_MEM16(0x097A) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESD_CTRLA _SFR_MEM8(0x0990) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD1_DATA _SFR_MEM8(0x09B0) ++#define USARTD1_STATUS _SFR_MEM8(0x09B1) ++#define USARTD1_CTRLA _SFR_MEM8(0x09B3) ++#define USARTD1_CTRLB _SFR_MEM8(0x09B4) ++#define USARTD1_CTRLC _SFR_MEM8(0x09B5) ++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) ++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCE2_CTRLA _SFR_MEM8(0x0A00) ++#define TCE2_CTRLB _SFR_MEM8(0x0A01) ++#define TCE2_CTRLC _SFR_MEM8(0x0A02) ++#define TCE2_CTRLE _SFR_MEM8(0x0A04) ++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE2_CTRLF _SFR_MEM8(0x0A09) ++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE2_LCNT _SFR_MEM8(0x0A20) ++#define TCE2_HCNT _SFR_MEM8(0x0A21) ++#define TCE2_LPER _SFR_MEM8(0x0A26) ++#define TCE2_HPER _SFR_MEM8(0x0A27) ++#define TCE2_LCMPA _SFR_MEM8(0x0A28) ++#define TCE2_HCMPA _SFR_MEM8(0x0A29) ++#define TCE2_LCMPB _SFR_MEM8(0x0A2A) ++#define TCE2_HCMPB _SFR_MEM8(0x0A2B) ++#define TCE2_LCMPC _SFR_MEM8(0x0A2C) ++#define TCE2_HCMPC _SFR_MEM8(0x0A2D) ++#define TCE2_LCMPD _SFR_MEM8(0x0A2E) ++#define TCE2_HCMPD _SFR_MEM8(0x0A2F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCE1_CTRLA _SFR_MEM8(0x0A40) ++#define TCE1_CTRLB _SFR_MEM8(0x0A41) ++#define TCE1_CTRLC _SFR_MEM8(0x0A42) ++#define TCE1_CTRLD _SFR_MEM8(0x0A43) ++#define TCE1_CTRLE _SFR_MEM8(0x0A44) ++#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) ++#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) ++#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) ++#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) ++#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) ++#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) ++#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) ++#define TCE1_TEMP _SFR_MEM8(0x0A4F) ++#define TCE1_CNT _SFR_MEM16(0x0A60) ++#define TCE1_PER _SFR_MEM16(0x0A66) ++#define TCE1_CCA _SFR_MEM16(0x0A68) ++#define TCE1_CCB _SFR_MEM16(0x0A6A) ++#define TCE1_PERBUF _SFR_MEM16(0x0A76) ++#define TCE1_CCABUF _SFR_MEM16(0x0A78) ++#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXE_CTRL _SFR_MEM8(0x0A80) ++#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) ++#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) ++#define AWEXE_STATUS _SFR_MEM8(0x0A84) ++#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) ++#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) ++#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) ++#define AWEXE_DTLS _SFR_MEM8(0x0A88) ++#define AWEXE_DTHS _SFR_MEM8(0x0A89) ++#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) ++#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) ++#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESE_CTRLA _SFR_MEM8(0x0A90) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE1_DATA _SFR_MEM8(0x0AB0) ++#define USARTE1_STATUS _SFR_MEM8(0x0AB1) ++#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) ++#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) ++#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) ++#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) ++#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIE_CTRL _SFR_MEM8(0x0AC0) ++#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) ++#define SPIE_STATUS _SFR_MEM8(0x0AC2) ++#define SPIE_DATA _SFR_MEM8(0x0AC3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCF0_CTRLA _SFR_MEM8(0x0B00) ++#define TCF0_CTRLB _SFR_MEM8(0x0B01) ++#define TCF0_CTRLC _SFR_MEM8(0x0B02) ++#define TCF0_CTRLD _SFR_MEM8(0x0B03) ++#define TCF0_CTRLE _SFR_MEM8(0x0B04) ++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) ++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) ++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) ++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) ++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF0_TEMP _SFR_MEM8(0x0B0F) ++#define TCF0_CNT _SFR_MEM16(0x0B20) ++#define TCF0_PER _SFR_MEM16(0x0B26) ++#define TCF0_CCA _SFR_MEM16(0x0B28) ++#define TCF0_CCB _SFR_MEM16(0x0B2A) ++#define TCF0_CCC _SFR_MEM16(0x0B2C) ++#define TCF0_CCD _SFR_MEM16(0x0B2E) ++#define TCF0_PERBUF _SFR_MEM16(0x0B36) ++#define TCF0_CCABUF _SFR_MEM16(0x0B38) ++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) ++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) ++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCF2_CTRLA _SFR_MEM8(0x0B00) ++#define TCF2_CTRLB _SFR_MEM8(0x0B01) ++#define TCF2_CTRLC _SFR_MEM8(0x0B02) ++#define TCF2_CTRLE _SFR_MEM8(0x0B04) ++#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF2_CTRLF _SFR_MEM8(0x0B09) ++#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF2_LCNT _SFR_MEM8(0x0B20) ++#define TCF2_HCNT _SFR_MEM8(0x0B21) ++#define TCF2_LPER _SFR_MEM8(0x0B26) ++#define TCF2_HPER _SFR_MEM8(0x0B27) ++#define TCF2_LCMPA _SFR_MEM8(0x0B28) ++#define TCF2_HCMPA _SFR_MEM8(0x0B29) ++#define TCF2_LCMPB _SFR_MEM8(0x0B2A) ++#define TCF2_HCMPB _SFR_MEM8(0x0B2B) ++#define TCF2_LCMPC _SFR_MEM8(0x0B2C) ++#define TCF2_HCMPC _SFR_MEM8(0x0B2D) ++#define TCF2_LCMPD _SFR_MEM8(0x0B2E) ++#define TCF2_HCMPD _SFR_MEM8(0x0B2F) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESF_CTRLA _SFR_MEM8(0x0B90) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTF0_DATA _SFR_MEM8(0x0BA0) ++#define USARTF0_STATUS _SFR_MEM8(0x0BA1) ++#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) ++#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) ++#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) ++#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) ++#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* CLK.USBCTRL bit masks and bit positions */ ++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ ++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ ++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ ++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ ++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ ++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ ++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ ++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ ++ ++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ ++#define CLK_USBSRC_gp 1 /* Clock Source group position. */ ++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ ++ ++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_USB_bm 0x40 /* USB bit mask. */ ++#define PR_USB_bp 6 /* USB bit position. */ ++ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ ++#define PR_EBI_bp 3 /* External Bus Interface bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ ++#define PR_DAC_bp 2 /* Port A DAC bit position. */ ++ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPB bit masks and bit positions */ ++/* PR_DAC Predefined. */ ++/* PR_DAC Predefined. */ ++ ++/* PR_ADC Predefined. */ ++/* PR_ADC Predefined. */ ++ ++/* PR_AC Predefined. */ ++/* PR_AC Predefined. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ ++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ ++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ ++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ ++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ ++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ ++ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ ++#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ ++ ++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ ++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ ++ ++#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ ++#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ ++ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ ++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ ++ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ ++ ++/* PORTCFG.EBIOUT bit masks and bit positions */ ++#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ ++#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ ++#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ ++#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ ++#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ ++#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ ++ ++#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ ++#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ ++#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ ++#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ ++#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ ++#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ ++ ++/* PORTCFG.EVOUTSEL bit masks and bit positions */ ++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ ++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ ++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ ++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ ++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ ++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ ++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ ++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ ++ ++/* AES - AES Module */ ++/* AES.CTRL bit masks and bit positions */ ++#define AES_START_bm 0x80 /* Start/Run bit mask. */ ++#define AES_START_bp 7 /* Start/Run bit position. */ ++ ++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ ++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ ++ ++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ ++#define AES_RESET_bp 5 /* AES Software Reset bit position. */ ++ ++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ ++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ ++ ++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ ++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ ++ ++/* AES.STATUS bit masks and bit positions */ ++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ ++#define AES_ERROR_bp 7 /* AES Error bit position. */ ++ ++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ ++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ ++ ++/* AES.INTCTRL bit masks and bit positions */ ++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define AES_INTLVL_gp 0 /* Interrupt level group position. */ ++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* DMA - DMA Controller */ ++/* DMA_CH.CTRLA bit masks and bit positions */ ++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ ++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ ++ ++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ ++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ ++ ++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ ++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ ++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ ++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ ++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ ++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ ++ ++/* DMA_CH.CTRLB bit masks and bit positions */ ++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ ++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ ++ ++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ ++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ ++ ++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ ++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ ++ ++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ ++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ ++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ ++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ ++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ ++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ ++ ++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ ++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ ++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ ++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ ++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ ++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ ++ ++/* DMA_CH.ADDRCTRL bit masks and bit positions */ ++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ ++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ ++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ ++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ ++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ ++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ ++ ++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ ++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ ++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ ++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ ++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ ++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ ++ ++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ ++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ ++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ ++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ ++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ ++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ ++ ++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ ++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ ++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ ++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ ++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ ++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ ++ ++/* DMA_CH.TRIGSRC bit masks and bit positions */ ++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++/* DMA.CTRL bit masks and bit positions */ ++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define DMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define DMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ ++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ ++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ ++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ ++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ ++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ ++ ++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ ++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ ++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ ++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ ++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ ++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ ++ ++/* DMA.INTFLAGS bit masks and bit positions */ ++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++/* DMA.STATUS bit masks and bit positions */ ++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ ++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ ++ ++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ ++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ ++ ++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ ++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ ++ ++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ ++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ ++ ++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ ++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ ++ ++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ ++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ ++ ++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ ++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ ++ ++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ ++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH4MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH5MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH6MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH7MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM Predefined. */ ++/* EVSYS_QDIRM Predefined. */ ++ ++/* EVSYS_QDIEN Predefined. */ ++/* EVSYS_QDIEN Predefined. */ ++ ++/* EVSYS_QDEN Predefined. */ ++/* EVSYS_QDEN Predefined. */ ++ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH4CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM Predefined. */ ++/* EVSYS_QDIRM Predefined. */ ++ ++/* EVSYS_QDIEN Predefined. */ ++/* EVSYS_QDIEN Predefined. */ ++ ++/* EVSYS_QDEN Predefined. */ ++/* EVSYS_QDEN Predefined. */ ++ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH5CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH6CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH7CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ ++#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ ++#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ ++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ ++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ ++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ ++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ ++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ ++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ ++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ ++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ ++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ ++ ++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ ++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ ++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ ++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ ++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ ++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ ++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ ++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ ++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ ++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ ++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ ++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ ++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ ++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ ++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ ++ ++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ ++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ ++ ++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ ++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ ++ ++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ ++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ ++ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ ++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ ++#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ ++ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ ++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ ++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ ++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ ++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ ++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ ++ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ ++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ ++ ++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ ++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ ++ ++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ ++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ ++ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* DAC - Digital/Analog Converter */ ++/* DAC.CTRLA bit masks and bit positions */ ++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ ++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ ++ ++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ ++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ ++ ++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ ++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ ++ ++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ ++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ ++ ++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define DAC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* DAC.CTRLB bit masks and bit positions */ ++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ ++#define DAC_CHSEL_gp 5 /* Channel Select group position. */ ++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ ++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ ++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ ++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ ++ ++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ ++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ ++ ++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ ++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ ++ ++/* DAC.CTRLC bit masks and bit positions */ ++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ ++#define DAC_REFSEL_gp 3 /* Reference Select group position. */ ++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ ++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ ++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ ++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ ++ ++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ ++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ ++ ++/* DAC.EVCTRL bit masks and bit positions */ ++#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ ++#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ ++ ++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ ++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ ++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ ++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ ++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ ++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ ++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ ++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ ++ ++/* DAC.STATUS bit masks and bit positions */ ++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ ++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ ++ ++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ ++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ ++ ++/* DAC.CH0GAINCAL bit masks and bit positions */ ++#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH0OFFSETCAL bit masks and bit positions */ ++#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* DAC.CH1GAINCAL bit masks and bit positions */ ++#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH1OFFSETCAL bit masks and bit positions */ ++#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ ++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HSMODE Predefined. */ ++/* AC_HSMODE Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* RTC - Real-Time Counter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* USB - USB */ ++/* USB_EP.STATUS bit masks and bit positions */ ++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ ++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ ++ ++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ ++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ ++ ++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ ++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ ++ ++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ ++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ ++ ++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ ++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ ++ ++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ ++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ ++ ++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ ++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ ++ ++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ ++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ ++ ++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ ++ ++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ ++ ++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ ++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ ++ ++/* USB_EP.CTRL bit masks and bit positions */ ++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ ++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ ++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ ++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ ++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ ++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ ++ ++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ ++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ ++ ++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ ++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ ++ ++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ ++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ ++ ++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ ++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ ++ ++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ ++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ ++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ ++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ ++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ ++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ ++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ ++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ ++ ++/* USB_EP.CNT bit masks and bit positions */ ++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ ++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ ++ ++/* USB.CTRLA bit masks and bit positions */ ++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ ++#define USB_ENABLE_bp 7 /* USB Enable bit position. */ ++ ++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ ++#define USB_SPEED_bp 6 /* Speed Select bit position. */ ++ ++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ ++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ ++ ++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ ++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ ++ ++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ ++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ ++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ ++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ ++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ ++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ ++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ ++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ ++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ ++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ ++ ++/* USB.CTRLB bit masks and bit positions */ ++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ ++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ ++ ++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ ++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ ++ ++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ ++#define USB_GNACK_bp 1 /* Global NACK bit position. */ ++ ++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ ++#define USB_ATTACH_bp 0 /* Attach bit position. */ ++ ++/* USB.STATUS bit masks and bit positions */ ++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ ++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ ++ ++#define USB_RESUME_bm 0x04 /* Resume bit mask. */ ++#define USB_RESUME_bp 2 /* Resume bit position. */ ++ ++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ ++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ ++ ++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ ++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ ++ ++/* USB.ADDR bit masks and bit positions */ ++#define USB_ADDR_gm 0x7F /* Device Address group mask. */ ++#define USB_ADDR_gp 0 /* Device Address group position. */ ++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ ++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ ++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ ++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ ++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ ++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ ++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ ++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ ++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ ++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ ++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ ++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ ++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ ++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ ++ ++/* USB.FIFOWP bit masks and bit positions */ ++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ ++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ ++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ ++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ ++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ ++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ ++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ ++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ ++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ ++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ ++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ ++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ ++ ++/* USB.FIFORP bit masks and bit positions */ ++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ ++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ ++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ ++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ ++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ ++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ ++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ ++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ ++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ ++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ ++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ ++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ ++ ++/* USB.INTCTRLA bit masks and bit positions */ ++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ ++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ ++ ++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ ++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ ++ ++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ ++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ ++ ++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ ++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ ++ ++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* USB.INTCTRLB bit masks and bit positions */ ++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ ++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ ++ ++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ ++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ ++ ++/* USB.INTFLAGSACLR bit masks and bit positions */ ++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ ++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ ++ ++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ ++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ ++ ++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ ++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ ++ ++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ ++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ ++ ++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ ++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ ++ ++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ ++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ ++ ++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ ++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ ++ ++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ ++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSASET bit masks and bit positions */ ++/* USB_SOFIF Predefined. */ ++/* USB_SOFIF Predefined. */ ++ ++/* USB_SUSPENDIF Predefined. */ ++/* USB_SUSPENDIF Predefined. */ ++ ++/* USB_RESUMEIF Predefined. */ ++/* USB_RESUMEIF Predefined. */ ++ ++/* USB_RSTIF Predefined. */ ++/* USB_RSTIF Predefined. */ ++ ++/* USB_CRCIF Predefined. */ ++/* USB_CRCIF Predefined. */ ++ ++/* USB_UNFIF Predefined. */ ++/* USB_UNFIF Predefined. */ ++ ++/* USB_OVFIF Predefined. */ ++/* USB_OVFIF Predefined. */ ++ ++/* USB_STALLIF Predefined. */ ++/* USB_STALLIF Predefined. */ ++ ++/* USB.INTFLAGSBCLR bit masks and bit positions */ ++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ ++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ ++ ++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ ++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSBSET bit masks and bit positions */ ++/* USB_TRNIF Predefined. */ ++/* USB_TRNIF Predefined. */ ++ ++/* USB_SETUPIF Predefined. */ ++/* USB_SETUPIF Predefined. */ ++ ++/* PORT - I/O Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_SPI_bm 0x20 /* SPI bit mask. */ ++#define PORT_SPI_bp 5 /* SPI bit position. */ ++ ++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ ++#define PORT_USART0_bp 4 /* USART0 bit position. */ ++ ++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ ++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ ++ ++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ ++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ ++ ++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ ++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ ++ ++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ ++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD Predefined. */ ++/* TC0_CMD Predefined. */ ++ ++/* TC0_LUPD Predefined. */ ++/* TC0_LUPD Predefined. */ ++ ++/* TC0_DIR Predefined. */ ++/* TC0_DIR Predefined. */ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV Predefined. */ ++/* TC0_CCDBV Predefined. */ ++ ++/* TC0_CCCBV Predefined. */ ++/* TC0_CCCBV Predefined. */ ++ ++/* TC0_CCBBV Predefined. */ ++/* TC0_CCBBV Predefined. */ ++ ++/* TC0_CCABV Predefined. */ ++/* TC0_CCABV Predefined. */ ++ ++/* TC0_PERBV Predefined. */ ++/* TC0_PERBV Predefined. */ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD Predefined. */ ++/* TC1_CMD Predefined. */ ++ ++/* TC1_LUPD Predefined. */ ++/* TC1_LUPD Predefined. */ ++ ++/* TC1_DIR Predefined. */ ++/* TC1_DIR Predefined. */ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV Predefined. */ ++/* TC1_CCBBV Predefined. */ ++ ++/* TC1_CCABV Predefined. */ ++/* TC1_CCABV Predefined. */ ++ ++/* TC1_PERBV Predefined. */ ++/* TC1_PERBV Predefined. */ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++/* TC2.CTRLA bit masks and bit positions */ ++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC2.CTRLB bit masks and bit positions */ ++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ ++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ ++ ++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ ++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ ++ ++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ ++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ ++ ++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ ++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ ++ ++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ ++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ ++ ++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ ++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ ++ ++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ ++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ ++ ++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ ++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ ++ ++/* TC2.CTRLC bit masks and bit positions */ ++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ ++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ ++ ++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ ++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ ++ ++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ ++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ ++ ++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ ++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ ++ ++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ ++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ ++ ++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ ++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ ++ ++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ ++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ ++ ++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ ++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ ++ ++/* TC2.CTRLE bit masks and bit positions */ ++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC2.INTCTRLA bit masks and bit positions */ ++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ ++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ ++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ ++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ ++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ ++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ ++ ++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ ++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ ++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ ++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ ++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ ++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ ++ ++/* TC2.INTCTRLB bit masks and bit positions */ ++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ ++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ ++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ ++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ ++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ ++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ ++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ ++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ ++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ ++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ ++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ ++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ ++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ ++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ ++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ ++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ ++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ ++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ ++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ ++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ ++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ ++ ++/* TC2.CTRLF bit masks and bit positions */ ++#define TC2_CMD_gm 0x0C /* Command group mask. */ ++#define TC2_CMD_gp 2 /* Command group position. */ ++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC2_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC2_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ ++#define TC2_CMDEN_gp 0 /* Command Enable group position. */ ++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ ++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ ++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ ++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ ++ ++/* TC2.INTFLAGS bit masks and bit positions */ ++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ ++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ ++ ++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ ++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ ++ ++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ ++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ ++ ++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ ++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ ++ ++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ ++ ++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ ++ ++/* AWEX - Timer/Counter Advanced Waveform Extension */ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++/* AWEX.STATUSSET bit masks and bit positions */ ++/* AWEX_FDF Predefined. */ ++/* AWEX_FDF Predefined. */ ++ ++/* AWEX_DTHSBUFV Predefined. */ ++/* AWEX_DTHSBUFV Predefined. */ ++ ++/* AWEX_DTLSBUFV Predefined. */ ++/* AWEX_DTLSBUFV Predefined. */ ++ ++/* HIRES - Timer/Counter High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ ++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ ++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ ++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ ++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ ++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ ++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ ++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ ++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ ++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ ++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ ++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ ++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ ++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ ++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ ++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ ++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ ++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ ++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ ++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ ++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* LOCKBIT - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* DMA interrupt vectors */ ++#define DMA_CH0_vect_num 6 ++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ ++#define DMA_CH1_vect_num 7 ++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ ++#define DMA_CH2_vect_num 8 ++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ ++#define DMA_CH3_vect_num 9 ++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LUNF_vect_num 14 ++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_HUNF_vect_num 15 ++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPA_vect_num 16 ++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPB_vect_num 17 ++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPC_vect_num 18 ++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPD_vect_num 19 ++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* USARTC1 interrupt vectors */ ++#define USARTC1_RXC_vect_num 28 ++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ ++#define USARTC1_DRE_vect_num 29 ++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ ++#define USARTC1_TXC_vect_num 30 ++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ ++ ++/* AES interrupt vectors */ ++#define AES_INT_vect_num 31 ++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* ACB interrupt vectors */ ++#define ACB_AC0_vect_num 36 ++#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ ++#define ACB_AC1_vect_num 37 ++#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ ++#define ACB_ACW_vect_num 38 ++#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ ++ ++/* ADCB interrupt vectors */ ++#define ADCB_CH0_vect_num 39 ++#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ ++#define ADCB_CH1_vect_num 40 ++#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ ++#define ADCB_CH2_vect_num 41 ++#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ ++#define ADCB_CH3_vect_num 42 ++#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LUNF_vect_num 47 ++#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_HUNF_vect_num 48 ++#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPA_vect_num 49 ++#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPB_vect_num 50 ++#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPC_vect_num 51 ++#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPD_vect_num 52 ++#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ ++ ++/* TCE1 interrupt vectors */ ++#define TCE1_OVF_vect_num 53 ++#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ ++#define TCE1_ERR_vect_num 54 ++#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ ++#define TCE1_CCA_vect_num 55 ++#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ ++#define TCE1_CCB_vect_num 56 ++#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ ++ ++/* SPIE interrupt vectors */ ++#define SPIE_INT_vect_num 57 ++#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* USARTE1 interrupt vectors */ ++#define USARTE1_RXC_vect_num 61 ++#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ ++#define USARTE1_DRE_vect_num 62 ++#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ ++#define USARTE1_TXC_vect_num 63 ++#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++#define ADCA_CH1_vect_num 72 ++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ ++#define ADCA_CH2_vect_num 73 ++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ ++#define ADCA_CH3_vect_num 74 ++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LUNF_vect_num 77 ++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_HUNF_vect_num 78 ++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPA_vect_num 79 ++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPB_vect_num 80 ++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPC_vect_num 81 ++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPD_vect_num 82 ++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ ++ ++/* TCD1 interrupt vectors */ ++#define TCD1_OVF_vect_num 83 ++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ ++#define TCD1_ERR_vect_num 84 ++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ ++#define TCD1_CCA_vect_num 85 ++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ ++#define TCD1_CCB_vect_num 86 ++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* USARTD1 interrupt vectors */ ++#define USARTD1_RXC_vect_num 91 ++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ ++#define USARTD1_DRE_vect_num 92 ++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ ++#define USARTD1_TXC_vect_num 93 ++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ ++ ++/* PORTF interrupt vectors */ ++#define PORTF_INT0_vect_num 104 ++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ ++#define PORTF_INT1_vect_num 105 ++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_OVF_vect_num 108 ++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LUNF_vect_num 108 ++#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_ERR_vect_num 109 ++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_HUNF_vect_num 109 ++#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCA_vect_num 110 ++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPA_vect_num 110 ++#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCB_vect_num 111 ++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPB_vect_num 111 ++#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCC_vect_num 112 ++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPC_vect_num 112 ++#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCD_vect_num 113 ++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPD_vect_num 113 ++#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ ++ ++/* USARTF0 interrupt vectors */ ++#define USARTF0_RXC_vect_num 119 ++#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ ++#define USARTF0_DRE_vect_num 120 ++#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ ++#define USARTF0_TXC_vect_num 121 ++#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ ++ ++/* USB interrupt vectors */ ++#define USB_BUSEVENT_vect_num 125 ++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ ++#define USB_TRNCOMPL_vect_num 126 ++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (127 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (270336) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (262144) ++#define APP_SECTION_PAGE_SIZE (512) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x3E000) ++#define APPTABLE_SECTION_SIZE (8192) ++#define APPTABLE_SECTION_PAGE_SIZE (512) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x40000) ++#define BOOT_SECTION_SIZE (8192) ++#define BOOT_SECTION_PAGE_SIZE (512) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (24576) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (4096) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (16384) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (4096) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (6) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (512) ++#define USER_SIGNATURES_PAGE_SIZE (512) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (512) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 512 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 */ ++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ ++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ ++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ ++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ ++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ ++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ ++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ ++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ ++#define FUSE0_DEFAULT (0xFF) ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x98 ++#define SIGNATURE_2 0x42 ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA256A3U_H_INCLUDED */ ++ diff --git a/include/avr/iox256c3.h b/include/avr/iox256c3.h new file mode 100644 -index 0000000..3d23667 +index 0000000..50658b1 --- /dev/null +++ b/include/avr/iox256c3.h @@ -0,0 +1,6216 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox256c3.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA256C3_H_INCLUDED -+#define _AVR_ATXMEGA256C3_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+VPORT - Virtual Ports -+-------------------------------------------------------------------------- -+*/ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t USBCTRL; /* USB Control Register */ -+} CLK_t; -+ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t reserved_0x02; -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t PRPD; /* Power Reduction Port D */ -+ register8_t PRPE; /* Power Reduction Port E */ -+ register8_t PRPF; /* Power Reduction Port F */ -+} PR_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+/* USB Prescaler Division Factor */ -+typedef enum CLK_USBPSDIV_enum -+{ -+ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ -+ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ -+ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ -+ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ -+ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ -+ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -+} CLK_USBPSDIV_t; -+ -+/* USB Clock Source */ -+typedef enum CLK_USBSRC_enum -+{ -+ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ -+ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -+} CLK_USBSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control Register */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+/* 2 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC2MCREF_enum -+{ -+ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC2MCREF_t; -+ -+/* 32 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC32MCREF_enum -+{ -+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -+} OSC_RC32MCREF_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t ANAINIT; /* Analog Startup Delay */ -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t AWEXLOCK; /* AWEX Lock */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORTCFG - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t VPCTRLA; /* Virtual Port Control Register A */ -+ register8_t VPCTRLB; /* Virtual Port Control Register B */ -+ register8_t CLKEVOUT; /* Clock and Event Out Register */ -+ register8_t reserved_0x05; -+ register8_t EVOUTSEL; /* Event Output Select */ -+} PORTCFG_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP02MAP_enum -+{ -+ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ -+ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ -+ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ -+ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ -+ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ -+ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ -+ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ -+ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ -+ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ -+ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ -+ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ -+ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ -+ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ -+ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ -+ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ -+ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -+} PORTCFG_VP02MAP_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP13MAP_enum -+{ -+ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ -+ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ -+ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ -+ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ -+ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ -+ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ -+ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ -+ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ -+ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ -+ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ -+ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ -+ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ -+ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ -+ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ -+ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ -+ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -+} PORTCFG_VP13MAP_t; -+ -+/* System Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ -+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ -+ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -+} PORTCFG_CLKOUT_t; -+ -+/* Peripheral Clock Output Select */ -+typedef enum PORTCFG_CLKOUTSEL_enum -+{ -+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -+} PORTCFG_CLKOUTSEL_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ -+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ -+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -+} PORTCFG_EVOUT_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+} EVSYS_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ -+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ -+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ -+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ -+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ -+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ -+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ -+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ -+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ -+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ -+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ -+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ -+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ -+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ -+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ -+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ -+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ -+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ -+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ -+ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ -+ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ -+ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ -+ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ -+ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ -+ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ -+ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ -+ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ -+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ -+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ -+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ -+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ -+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ -+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ -+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ -+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ -+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ -+ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ -+ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ -+ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ -+ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ -+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ -+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ -+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ -+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ -+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -+ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ -+ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ -+ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ -+ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ -+ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -+} EVSYS_CHMUX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ -+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ -+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ -+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ -+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} NVM_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t reserved_0x07; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+} ADC_t; -+ -+/* Current Limitation */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -+} ADC_CURRLIMIT_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+} ADC_CH_MUXNEG_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ -+ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ -+ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ -+ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC - Real-Time Counter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Real-Time Counter */ -+typedef struct RTC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary register */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ _WORDREGISTER(CNT); /* Count Register */ -+ _WORDREGISTER(PER); /* Period Register */ -+ _WORDREGISTER(COMP); /* Compare Register */ -+} RTC_t; -+ -+/* Prescaler Factor */ -+typedef enum RTC_PRESCALER_enum -+{ -+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ -+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ -+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ -+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ -+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ -+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ -+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ -+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -+} RTC_PRESCALER_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC_COMPINTLVL_enum -+{ -+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC_OVFINTLVL_enum -+{ -+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+} TWI_t; -+ -+/* SDA Hold Time */ -+typedef enum TWI_SDAHOLD_enum -+{ -+ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ -+ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ -+ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ -+ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -+} TWI_SDAHOLD_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USB - USB -+-------------------------------------------------------------------------- -+*/ -+ -+/* USB Endpoint */ -+typedef struct USB_EP_struct -+{ -+ register8_t STATUS; /* Endpoint Status */ -+ register8_t CTRL; /* Endpoint Control */ -+ _WORDREGISTER(CNT); /* USB Endpoint Counter */ -+ _WORDREGISTER(DATAPTR); /* Data Pointer */ -+ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -+} USB_EP_t; -+ -+ -+/* Universal Serial Bus */ -+typedef struct USB_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t FIFOWP; /* FIFO Write Pointer Register */ -+ register8_t FIFORP; /* FIFO Read Pointer Register */ -+ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ -+ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ -+ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ -+ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t reserved_0x20; -+ register8_t reserved_0x21; -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t CAL0; /* Calibration Byte 0 */ -+ register8_t CAL1; /* Calibration Byte 1 */ -+} USB_t; -+ -+ -+/* USB Endpoint Table */ -+typedef struct USB_EP_TABLE_struct -+{ -+ USB_EP_t EP0OUT; /* Endpoint 0 */ -+ USB_EP_t EP0IN; /* Endpoint 0 */ -+ USB_EP_t EP1OUT; /* Endpoint 1 */ -+ USB_EP_t EP1IN; /* Endpoint 1 */ -+ USB_EP_t EP2OUT; /* Endpoint 2 */ -+ USB_EP_t EP2IN; /* Endpoint 2 */ -+ USB_EP_t EP3OUT; /* Endpoint 3 */ -+ USB_EP_t EP3IN; /* Endpoint 3 */ -+ USB_EP_t EP4OUT; /* Endpoint 4 */ -+ USB_EP_t EP4IN; /* Endpoint 4 */ -+ USB_EP_t EP5OUT; /* Endpoint 5 */ -+ USB_EP_t EP5IN; /* Endpoint 5 */ -+ USB_EP_t EP6OUT; /* Endpoint 6 */ -+ USB_EP_t EP6IN; /* Endpoint 6 */ -+ USB_EP_t EP7OUT; /* Endpoint 7 */ -+ USB_EP_t EP7IN; /* Endpoint 7 */ -+ USB_EP_t EP8OUT; /* Endpoint 8 */ -+ USB_EP_t EP8IN; /* Endpoint 8 */ -+ USB_EP_t EP9OUT; /* Endpoint 9 */ -+ USB_EP_t EP9IN; /* Endpoint 9 */ -+ USB_EP_t EP10OUT; /* Endpoint 10 */ -+ USB_EP_t EP10IN; /* Endpoint 10 */ -+ USB_EP_t EP11OUT; /* Endpoint 11 */ -+ USB_EP_t EP11IN; /* Endpoint 11 */ -+ USB_EP_t EP12OUT; /* Endpoint 12 */ -+ USB_EP_t EP12IN; /* Endpoint 12 */ -+ USB_EP_t EP13OUT; /* Endpoint 13 */ -+ USB_EP_t EP13IN; /* Endpoint 13 */ -+ USB_EP_t EP14OUT; /* Endpoint 14 */ -+ USB_EP_t EP14IN; /* Endpoint 14 */ -+ USB_EP_t EP15OUT; /* Endpoint 15 */ -+ USB_EP_t EP15IN; /* Endpoint 15 */ -+ register8_t reserved_0x100; -+ register8_t reserved_0x101; -+ register8_t reserved_0x102; -+ register8_t reserved_0x103; -+ register8_t reserved_0x104; -+ register8_t reserved_0x105; -+ register8_t reserved_0x106; -+ register8_t reserved_0x107; -+ register8_t reserved_0x108; -+ register8_t reserved_0x109; -+ register8_t reserved_0x10A; -+ register8_t reserved_0x10B; -+ register8_t reserved_0x10C; -+ register8_t reserved_0x10D; -+ register8_t reserved_0x10E; -+ register8_t reserved_0x10F; -+ register8_t FRAMENUML; /* Frame Number Low Byte */ -+ register8_t FRAMENUMH; /* Frame Number High Byte */ -+} USB_EP_TABLE_t; -+ -+/* Interrupt level */ -+typedef enum USB_INTLVL_enum -+{ -+ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} USB_INTLVL_t; -+ -+/* USB Endpoint Type */ -+typedef enum USB_EP_TYPE_enum -+{ -+ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ -+ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ -+ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ -+ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -+} USB_EP_TYPE_t; -+ -+/* USB Endpoint Buffersize */ -+typedef enum USB_EP_BUFSIZE_enum -+{ -+ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ -+ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ -+ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ -+ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ -+ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ -+ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ -+ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ -+ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -+} USB_EP_BUFSIZE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - I/O Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INT0MASK; /* Port Interrupt 0 Mask */ -+ register8_t INT1MASK; /* Port Interrupt 1 Mask */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t REMAP; /* I/O Port Pin Remap Register */ -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Port Interrupt 0 Level */ -+typedef enum PORT_INT0LVL_enum -+{ -+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INT0LVL_t; -+ -+/* Port Interrupt 1 Level */ -+typedef enum PORT_INT1LVL_enum -+{ -+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ -+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ -+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -+} PORT_INT1LVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 0 */ -+typedef struct TC0_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC0_t; -+ -+ -+/* 16-bit Timer/Counter 1 */ -+typedef struct TC1_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+} TC1_t; -+ -+/* Clock Selection */ -+typedef enum TC_CLKSEL_enum -+{ -+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_CLKSEL_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC_WGMODE_enum -+{ -+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC_WGMODE_t; -+ -+/* Byte Mode */ -+typedef enum TC_BYTEM_enum -+{ -+ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ -+ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -+} TC_BYTEM_t; -+ -+/* Event Action */ -+typedef enum TC_EVACT_enum -+{ -+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ -+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ -+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ -+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ -+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ -+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC_EVSEL_enum -+{ -+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_EVSEL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC_ERRINTLVL_enum -+{ -+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC_OVFINTLVL_enum -+{ -+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_OVFINTLVL_t; -+ -+/* Compare or Capture D Interrupt Level */ -+typedef enum TC_CCDINTLVL_enum -+{ -+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC_CCDINTLVL_t; -+ -+/* Compare or Capture C Interrupt Level */ -+typedef enum TC_CCCINTLVL_enum -+{ -+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC_CCCINTLVL_t; -+ -+/* Compare or Capture B Interrupt Level */ -+typedef enum TC_CCBINTLVL_enum -+{ -+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_CCBINTLVL_t; -+ -+/* Compare or Capture A Interrupt Level */ -+typedef enum TC_CCAINTLVL_enum -+{ -+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_CCAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC_CMD_enum -+{ -+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC2 - 16-bit Timer/Counter type 2 -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter type 2 */ -+typedef struct TC2_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t reserved_0x03; -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t reserved_0x08; -+ register8_t CTRLF; /* Control Register F */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t LCNT; /* Low Byte Count */ -+ register8_t HCNT; /* High Byte Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t LPER; /* Low Byte Period */ -+ register8_t HPER; /* High Byte Period */ -+ register8_t LCMPA; /* Low Byte Compare A */ -+ register8_t HCMPA; /* High Byte Compare A */ -+ register8_t LCMPB; /* Low Byte Compare B */ -+ register8_t HCMPB; /* High Byte Compare B */ -+ register8_t LCMPC; /* Low Byte Compare C */ -+ register8_t HCMPC; /* High Byte Compare C */ -+ register8_t LCMPD; /* Low Byte Compare D */ -+ register8_t HCMPD; /* High Byte Compare D */ -+} TC2_t; -+ -+/* Clock Selection */ -+typedef enum TC2_CLKSEL_enum -+{ -+ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC2_CLKSEL_t; -+ -+/* Byte Mode */ -+typedef enum TC2_BYTEM_enum -+{ -+ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ -+ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -+} TC2_BYTEM_t; -+ -+/* High Byte Underflow Interrupt Level */ -+typedef enum TC2_HUNFINTLVL_enum -+{ -+ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_HUNFINTLVL_t; -+ -+/* Low Byte Underflow Interrupt Level */ -+typedef enum TC2_LUNFINTLVL_enum -+{ -+ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LUNFINTLVL_t; -+ -+/* Low Byte Compare D Interrupt Level */ -+typedef enum TC2_LCMPDINTLVL_enum -+{ -+ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC2_LCMPDINTLVL_t; -+ -+/* Low Byte Compare C Interrupt Level */ -+typedef enum TC2_LCMPCINTLVL_enum -+{ -+ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC2_LCMPCINTLVL_t; -+ -+/* Low Byte Compare B Interrupt Level */ -+typedef enum TC2_LCMPBINTLVL_enum -+{ -+ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_LCMPBINTLVL_t; -+ -+/* Low Byte Compare A Interrupt Level */ -+typedef enum TC2_LCMPAINTLVL_enum -+{ -+ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LCMPAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMD_enum -+{ -+ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC2_CMD_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMDEN_enum -+{ -+ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ -+ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ -+ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -+} TC2_CMDEN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AWEX - Timer/Counter Advanced Waveform Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Advanced Waveform Extension */ -+typedef struct AWEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t FDEMASK; /* Fault Detection Event Mask */ -+ register8_t FDCTRL; /* Fault Detection Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t STATUSSET; /* Status Set Register */ -+ register8_t DTBOTH; /* Dead Time Both Sides */ -+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ -+ register8_t DTLS; /* Dead Time Low Side */ -+ register8_t DTHS; /* Dead Time High Side */ -+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ -+ register8_t DTHSBUF; /* Dead Time High Side Buffer */ -+ register8_t OUTOVEN; /* Output Override Enable */ -+} AWEX_t; -+ -+/* Fault Detect Action */ -+typedef enum AWEX_FDACT_enum -+{ -+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ -+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -+} AWEX_FDACT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+HIRES - Timer/Counter High-Resolution Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register */ -+} HIRES_t; -+ -+/* High Resolution Enable */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ -+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+} IRDA_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t reserved_0x00; -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+} NVM_FUSES_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* Timer Oscillator pin location */ -+typedef enum TOSCSEL_enum -+{ -+ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ -+ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -+} TOSCSEL_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -+} BOD_t; -+ -+/* BOD operation */ -+typedef enum BODACT_enum -+{ -+ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BODACT_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WDP_enum -+{ -+ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ -+ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ -+ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ -+ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ -+ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ -+ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ -+ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ -+ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ -+ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ -+ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ -+ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -+} WDP_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LOCKBIT - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ -+ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t USBCAL0; /* USB Calibration Byte 0 */ -+ register8_t USBCAL1; /* USB Calibration Byte 1 */ -+ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ -+ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+} NVM_PROD_SIGNATURES_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -+#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -+#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -+#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -+#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -+#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -+#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -+#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -+#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -+#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -+#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -+#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -+#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+#define CLK_USBCTRL _SFR_MEM8(0x0044) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* DFLL - DFLL */ -+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -+#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -+#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPD _SFR_MEM8(0x0074) -+#define PR_PRPE _SFR_MEM8(0x0075) -+#define PR_PRPF _SFR_MEM8(0x0076) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_ANAINIT _SFR_MEM8(0x0097) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_AWEXLOCK _SFR_MEM8(0x0099) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCA_CTRLA _SFR_MEM8(0x0200) -+#define ADCA_CTRLB _SFR_MEM8(0x0201) -+#define ADCA_REFCTRL _SFR_MEM8(0x0202) -+#define ADCA_EVCTRL _SFR_MEM8(0x0203) -+#define ADCA_PRESCALER _SFR_MEM8(0x0204) -+#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -+#define ADCA_TEMP _SFR_MEM8(0x0207) -+#define ADCA_CAL _SFR_MEM16(0x020C) -+#define ADCA_CH0RES _SFR_MEM16(0x0210) -+#define ADCA_CMP _SFR_MEM16(0x0218) -+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -+#define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -+ -+/* AC - Analog Comparator */ -+#define ACA_AC0CTRL _SFR_MEM8(0x0380) -+#define ACA_AC1CTRL _SFR_MEM8(0x0381) -+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -+#define ACA_CTRLA _SFR_MEM8(0x0384) -+#define ACA_CTRLB _SFR_MEM8(0x0385) -+#define ACA_WINCTRL _SFR_MEM8(0x0386) -+#define ACA_STATUS _SFR_MEM8(0x0387) -+ -+/* RTC - Real-Time Counter */ -+#define RTC_CTRL _SFR_MEM8(0x0400) -+#define RTC_STATUS _SFR_MEM8(0x0401) -+#define RTC_INTCTRL _SFR_MEM8(0x0402) -+#define RTC_INTFLAGS _SFR_MEM8(0x0403) -+#define RTC_TEMP _SFR_MEM8(0x0404) -+#define RTC_CNT _SFR_MEM16(0x0408) -+#define RTC_PER _SFR_MEM16(0x040A) -+#define RTC_COMP _SFR_MEM16(0x040C) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIE_CTRL _SFR_MEM8(0x04A0) -+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -+ -+/* USB - Universal Serial Bus */ -+#define USB_CTRLA _SFR_MEM8(0x04C0) -+#define USB_CTRLB _SFR_MEM8(0x04C1) -+#define USB_STATUS _SFR_MEM8(0x04C2) -+#define USB_ADDR _SFR_MEM8(0x04C3) -+#define USB_FIFOWP _SFR_MEM8(0x04C4) -+#define USB_FIFORP _SFR_MEM8(0x04C5) -+#define USB_EPPTR _SFR_MEM16(0x04C6) -+#define USB_INTCTRLA _SFR_MEM8(0x04C8) -+#define USB_INTCTRLB _SFR_MEM8(0x04C9) -+#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -+#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -+#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -+#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -+#define USB_CAL0 _SFR_MEM8(0x04FA) -+#define USB_CAL1 _SFR_MEM8(0x04FB) -+ -+/* PORT - I/O Ports */ -+#define PORTA_DIR _SFR_MEM8(0x0600) -+#define PORTA_DIRSET _SFR_MEM8(0x0601) -+#define PORTA_DIRCLR _SFR_MEM8(0x0602) -+#define PORTA_DIRTGL _SFR_MEM8(0x0603) -+#define PORTA_OUT _SFR_MEM8(0x0604) -+#define PORTA_OUTSET _SFR_MEM8(0x0605) -+#define PORTA_OUTCLR _SFR_MEM8(0x0606) -+#define PORTA_OUTTGL _SFR_MEM8(0x0607) -+#define PORTA_IN _SFR_MEM8(0x0608) -+#define PORTA_INTCTRL _SFR_MEM8(0x0609) -+#define PORTA_INT0MASK _SFR_MEM8(0x060A) -+#define PORTA_INT1MASK _SFR_MEM8(0x060B) -+#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_REMAP _SFR_MEM8(0x060E) -+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -+ -+/* PORT - I/O Ports */ -+#define PORTB_DIR _SFR_MEM8(0x0620) -+#define PORTB_DIRSET _SFR_MEM8(0x0621) -+#define PORTB_DIRCLR _SFR_MEM8(0x0622) -+#define PORTB_DIRTGL _SFR_MEM8(0x0623) -+#define PORTB_OUT _SFR_MEM8(0x0624) -+#define PORTB_OUTSET _SFR_MEM8(0x0625) -+#define PORTB_OUTCLR _SFR_MEM8(0x0626) -+#define PORTB_OUTTGL _SFR_MEM8(0x0627) -+#define PORTB_IN _SFR_MEM8(0x0628) -+#define PORTB_INTCTRL _SFR_MEM8(0x0629) -+#define PORTB_INT0MASK _SFR_MEM8(0x062A) -+#define PORTB_INT1MASK _SFR_MEM8(0x062B) -+#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -+#define PORTB_REMAP _SFR_MEM8(0x062E) -+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INT0MASK _SFR_MEM8(0x064A) -+#define PORTC_INT1MASK _SFR_MEM8(0x064B) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INT0MASK _SFR_MEM8(0x066A) -+#define PORTD_INT1MASK _SFR_MEM8(0x066B) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTE_DIR _SFR_MEM8(0x0680) -+#define PORTE_DIRSET _SFR_MEM8(0x0681) -+#define PORTE_DIRCLR _SFR_MEM8(0x0682) -+#define PORTE_DIRTGL _SFR_MEM8(0x0683) -+#define PORTE_OUT _SFR_MEM8(0x0684) -+#define PORTE_OUTSET _SFR_MEM8(0x0685) -+#define PORTE_OUTCLR _SFR_MEM8(0x0686) -+#define PORTE_OUTTGL _SFR_MEM8(0x0687) -+#define PORTE_IN _SFR_MEM8(0x0688) -+#define PORTE_INTCTRL _SFR_MEM8(0x0689) -+#define PORTE_INT0MASK _SFR_MEM8(0x068A) -+#define PORTE_INT1MASK _SFR_MEM8(0x068B) -+#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -+#define PORTE_REMAP _SFR_MEM8(0x068E) -+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) -+ -+/* PORT - I/O Ports */ -+#define PORTF_DIR _SFR_MEM8(0x06A0) -+#define PORTF_DIRSET _SFR_MEM8(0x06A1) -+#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -+#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -+#define PORTF_OUT _SFR_MEM8(0x06A4) -+#define PORTF_OUTSET _SFR_MEM8(0x06A5) -+#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -+#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -+#define PORTF_IN _SFR_MEM8(0x06A8) -+#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -+#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -+#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -+#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -+#define PORTF_REMAP _SFR_MEM8(0x06AE) -+#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -+#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -+#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -+#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -+#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -+#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -+#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -+#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -+#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCC0_CTRLA _SFR_MEM8(0x0800) -+#define TCC0_CTRLB _SFR_MEM8(0x0801) -+#define TCC0_CTRLC _SFR_MEM8(0x0802) -+#define TCC0_CTRLD _SFR_MEM8(0x0803) -+#define TCC0_CTRLE _SFR_MEM8(0x0804) -+#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -+#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -+#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -+#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC0_TEMP _SFR_MEM8(0x080F) -+#define TCC0_CNT _SFR_MEM16(0x0820) -+#define TCC0_PER _SFR_MEM16(0x0826) -+#define TCC0_CCA _SFR_MEM16(0x0828) -+#define TCC0_CCB _SFR_MEM16(0x082A) -+#define TCC0_CCC _SFR_MEM16(0x082C) -+#define TCC0_CCD _SFR_MEM16(0x082E) -+#define TCC0_PERBUF _SFR_MEM16(0x0836) -+#define TCC0_CCABUF _SFR_MEM16(0x0838) -+#define TCC0_CCBBUF _SFR_MEM16(0x083A) -+#define TCC0_CCCBUF _SFR_MEM16(0x083C) -+#define TCC0_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCC2_CTRLA _SFR_MEM8(0x0800) -+#define TCC2_CTRLB _SFR_MEM8(0x0801) -+#define TCC2_CTRLC _SFR_MEM8(0x0802) -+#define TCC2_CTRLE _SFR_MEM8(0x0804) -+#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC2_CTRLF _SFR_MEM8(0x0809) -+#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC2_LCNT _SFR_MEM8(0x0820) -+#define TCC2_HCNT _SFR_MEM8(0x0821) -+#define TCC2_LPER _SFR_MEM8(0x0826) -+#define TCC2_HPER _SFR_MEM8(0x0827) -+#define TCC2_LCMPA _SFR_MEM8(0x0828) -+#define TCC2_HCMPA _SFR_MEM8(0x0829) -+#define TCC2_LCMPB _SFR_MEM8(0x082A) -+#define TCC2_HCMPB _SFR_MEM8(0x082B) -+#define TCC2_LCMPC _SFR_MEM8(0x082C) -+#define TCC2_HCMPC _SFR_MEM8(0x082D) -+#define TCC2_LCMPD _SFR_MEM8(0x082E) -+#define TCC2_HCMPD _SFR_MEM8(0x082F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCC1_CTRLA _SFR_MEM8(0x0840) -+#define TCC1_CTRLB _SFR_MEM8(0x0841) -+#define TCC1_CTRLC _SFR_MEM8(0x0842) -+#define TCC1_CTRLD _SFR_MEM8(0x0843) -+#define TCC1_CTRLE _SFR_MEM8(0x0844) -+#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -+#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -+#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -+#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC1_TEMP _SFR_MEM8(0x084F) -+#define TCC1_CNT _SFR_MEM16(0x0860) -+#define TCC1_PER _SFR_MEM16(0x0866) -+#define TCC1_CCA _SFR_MEM16(0x0868) -+#define TCC1_CCB _SFR_MEM16(0x086A) -+#define TCC1_PERBUF _SFR_MEM16(0x0876) -+#define TCC1_CCABUF _SFR_MEM16(0x0878) -+#define TCC1_CCBBUF _SFR_MEM16(0x087A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXC_CTRL _SFR_MEM8(0x0880) -+#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -+#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -+#define AWEXC_STATUS _SFR_MEM8(0x0884) -+#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -+#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -+#define AWEXC_DTLS _SFR_MEM8(0x0888) -+#define AWEXC_DTHS _SFR_MEM8(0x0889) -+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x0890) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08A0) -+#define USARTC0_STATUS _SFR_MEM8(0x08A1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -+#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -+#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIC_CTRL _SFR_MEM8(0x08C0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -+#define SPIC_STATUS _SFR_MEM8(0x08C2) -+#define SPIC_DATA _SFR_MEM8(0x08C3) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCD0_CTRLA _SFR_MEM8(0x0900) -+#define TCD0_CTRLB _SFR_MEM8(0x0901) -+#define TCD0_CTRLC _SFR_MEM8(0x0902) -+#define TCD0_CTRLD _SFR_MEM8(0x0903) -+#define TCD0_CTRLE _SFR_MEM8(0x0904) -+#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -+#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -+#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -+#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -+#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD0_TEMP _SFR_MEM8(0x090F) -+#define TCD0_CNT _SFR_MEM16(0x0920) -+#define TCD0_PER _SFR_MEM16(0x0926) -+#define TCD0_CCA _SFR_MEM16(0x0928) -+#define TCD0_CCB _SFR_MEM16(0x092A) -+#define TCD0_CCC _SFR_MEM16(0x092C) -+#define TCD0_CCD _SFR_MEM16(0x092E) -+#define TCD0_PERBUF _SFR_MEM16(0x0936) -+#define TCD0_CCABUF _SFR_MEM16(0x0938) -+#define TCD0_CCBBUF _SFR_MEM16(0x093A) -+#define TCD0_CCCBUF _SFR_MEM16(0x093C) -+#define TCD0_CCDBUF _SFR_MEM16(0x093E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCD2_CTRLA _SFR_MEM8(0x0900) -+#define TCD2_CTRLB _SFR_MEM8(0x0901) -+#define TCD2_CTRLC _SFR_MEM8(0x0902) -+#define TCD2_CTRLE _SFR_MEM8(0x0904) -+#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD2_CTRLF _SFR_MEM8(0x0909) -+#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD2_LCNT _SFR_MEM8(0x0920) -+#define TCD2_HCNT _SFR_MEM8(0x0921) -+#define TCD2_LPER _SFR_MEM8(0x0926) -+#define TCD2_HPER _SFR_MEM8(0x0927) -+#define TCD2_LCMPA _SFR_MEM8(0x0928) -+#define TCD2_HCMPA _SFR_MEM8(0x0929) -+#define TCD2_LCMPB _SFR_MEM8(0x092A) -+#define TCD2_HCMPB _SFR_MEM8(0x092B) -+#define TCD2_LCMPC _SFR_MEM8(0x092C) -+#define TCD2_HCMPC _SFR_MEM8(0x092D) -+#define TCD2_LCMPD _SFR_MEM8(0x092E) -+#define TCD2_HCMPD _SFR_MEM8(0x092F) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD0_DATA _SFR_MEM8(0x09A0) -+#define USARTD0_STATUS _SFR_MEM8(0x09A1) -+#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -+#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -+#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPID_CTRL _SFR_MEM8(0x09C0) -+#define SPID_INTCTRL _SFR_MEM8(0x09C1) -+#define SPID_STATUS _SFR_MEM8(0x09C2) -+#define SPID_DATA _SFR_MEM8(0x09C3) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCE0_CTRLA _SFR_MEM8(0x0A00) -+#define TCE0_CTRLB _SFR_MEM8(0x0A01) -+#define TCE0_CTRLC _SFR_MEM8(0x0A02) -+#define TCE0_CTRLD _SFR_MEM8(0x0A03) -+#define TCE0_CTRLE _SFR_MEM8(0x0A04) -+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE0_TEMP _SFR_MEM8(0x0A0F) -+#define TCE0_CNT _SFR_MEM16(0x0A20) -+#define TCE0_PER _SFR_MEM16(0x0A26) -+#define TCE0_CCA _SFR_MEM16(0x0A28) -+#define TCE0_CCB _SFR_MEM16(0x0A2A) -+#define TCE0_CCC _SFR_MEM16(0x0A2C) -+#define TCE0_CCD _SFR_MEM16(0x0A2E) -+#define TCE0_PERBUF _SFR_MEM16(0x0A36) -+#define TCE0_CCABUF _SFR_MEM16(0x0A38) -+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCE2_CTRLA _SFR_MEM8(0x0A00) -+#define TCE2_CTRLB _SFR_MEM8(0x0A01) -+#define TCE2_CTRLC _SFR_MEM8(0x0A02) -+#define TCE2_CTRLE _SFR_MEM8(0x0A04) -+#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE2_CTRLF _SFR_MEM8(0x0A09) -+#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE2_LCNT _SFR_MEM8(0x0A20) -+#define TCE2_HCNT _SFR_MEM8(0x0A21) -+#define TCE2_LPER _SFR_MEM8(0x0A26) -+#define TCE2_HPER _SFR_MEM8(0x0A27) -+#define TCE2_LCMPA _SFR_MEM8(0x0A28) -+#define TCE2_HCMPA _SFR_MEM8(0x0A29) -+#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -+#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -+#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -+#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -+#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -+#define TCE2_HCMPD _SFR_MEM8(0x0A2F) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE0_DATA _SFR_MEM8(0x0AA0) -+#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -+#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -+#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -+#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -+#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -+#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCF0_CTRLA _SFR_MEM8(0x0B00) -+#define TCF0_CTRLB _SFR_MEM8(0x0B01) -+#define TCF0_CTRLC _SFR_MEM8(0x0B02) -+#define TCF0_CTRLD _SFR_MEM8(0x0B03) -+#define TCF0_CTRLE _SFR_MEM8(0x0B04) -+#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -+#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -+#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -+#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -+#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -+#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -+#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -+#define TCF0_TEMP _SFR_MEM8(0x0B0F) -+#define TCF0_CNT _SFR_MEM16(0x0B20) -+#define TCF0_PER _SFR_MEM16(0x0B26) -+#define TCF0_CCA _SFR_MEM16(0x0B28) -+#define TCF0_CCB _SFR_MEM16(0x0B2A) -+#define TCF0_CCC _SFR_MEM16(0x0B2C) -+#define TCF0_CCD _SFR_MEM16(0x0B2E) -+#define TCF0_PERBUF _SFR_MEM16(0x0B36) -+#define TCF0_CCABUF _SFR_MEM16(0x0B38) -+#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -+#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -+#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCF2_CTRLA _SFR_MEM8(0x0B00) -+#define TCF2_CTRLB _SFR_MEM8(0x0B01) -+#define TCF2_CTRLC _SFR_MEM8(0x0B02) -+#define TCF2_CTRLE _SFR_MEM8(0x0B04) -+#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -+#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -+#define TCF2_CTRLF _SFR_MEM8(0x0B09) -+#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -+#define TCF2_LCNT _SFR_MEM8(0x0B20) -+#define TCF2_HCNT _SFR_MEM8(0x0B21) -+#define TCF2_LPER _SFR_MEM8(0x0B26) -+#define TCF2_HPER _SFR_MEM8(0x0B27) -+#define TCF2_LCMPA _SFR_MEM8(0x0B28) -+#define TCF2_HCMPA _SFR_MEM8(0x0B29) -+#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -+#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -+#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -+#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -+#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -+#define TCF2_HCMPD _SFR_MEM8(0x0B2F) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* VPORT - Virtual Ports */ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* CLK.USBCTRL bit masks and bit positions */ -+#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -+#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -+#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -+#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -+#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -+#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -+#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -+#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ -+ -+#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -+#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -+#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ -+ -+#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_USB_bm 0x40 /* USB bit mask. */ -+#define PR_USB_bp 6 /* USB bit position. */ -+ -+#define PR_AES_bm 0x10 /* AES bit mask. */ -+#define PR_AES_bp 4 /* AES bit position. */ -+ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -+#define PR_DMA_bp 0 /* DMA-Controller bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -+#define PR_USART1_bp 5 /* Port C USART1 bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -+#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ -+ -+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -+ -+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ -+ -+/* PR.PRPD bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPE bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPF bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -+#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -+#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ -+ -+#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ -+ -+#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -+#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.ANAINIT bit masks and bit positions */ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.AWEXLOCK bit masks and bit positions */ -+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* PORTCFG - Port Configuration */ -+/* PORTCFG.VPCTRLA bit masks and bit positions */ -+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ -+ -+/* PORTCFG.VPCTRLB bit masks and bit positions */ -+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ -+ -+/* PORTCFG.CLKEVOUT bit masks and bit positions */ -+#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ -+ -+#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -+#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -+#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -+#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -+#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -+#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ -+ -+#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -+#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ -+ -+#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -+#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ -+ -+/* PORTCFG.EVOUTSEL bit masks and bit positions */ -+#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -+#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -+#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -+#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -+#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -+#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -+#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -+#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0x7F /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ -+ -+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ -+ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -+#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -+#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -+#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -+#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -+#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -+#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -+#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -+#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -+#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ -+ -+#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -+#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -+#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -+#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -+#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -+#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -+#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -+#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -+#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -+#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -+#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* RTC - Real-Time Counter */ -+/* RTC.CTRL bit masks and bit positions */ -+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ -+ -+/* RTC.STATUS bit masks and bit positions */ -+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC.INTCTRL bit masks and bit positions */ -+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC.INTFLAGS bit masks and bit positions */ -+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* USB - USB */ -+/* USB_EP.STATUS bit masks and bit positions */ -+#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -+#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ -+ -+#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -+#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ -+ -+#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -+#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ -+ -+#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -+#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ -+ -+#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -+#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ -+ -+#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -+#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ -+ -+#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -+#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ -+ -+#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -+#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ -+ -+#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ -+ -+#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ -+ -+#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -+#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ -+ -+/* USB_EP.CTRL bit masks and bit positions */ -+#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -+#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -+#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -+#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -+#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -+#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ -+ -+#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -+#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ -+ -+#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -+#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ -+ -+#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -+#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ -+ -+#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -+#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ -+ -+#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -+#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -+#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -+#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -+#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -+#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -+#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -+#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ -+ -+/* USB_EP.CNT bit masks and bit positions */ -+#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -+#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ -+ -+/* USB.CTRLA bit masks and bit positions */ -+#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -+#define USB_ENABLE_bp 7 /* USB Enable bit position. */ -+ -+#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -+#define USB_SPEED_bp 6 /* Speed Select bit position. */ -+ -+#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -+#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ -+ -+#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -+#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ -+ -+#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -+#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -+#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -+#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -+#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -+#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -+#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -+#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -+#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -+#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ -+ -+/* USB.CTRLB bit masks and bit positions */ -+#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -+#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ -+ -+#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -+#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ -+ -+#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -+#define USB_GNACK_bp 1 /* Global NACK bit position. */ -+ -+#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -+#define USB_ATTACH_bp 0 /* Attach bit position. */ -+ -+/* USB.STATUS bit masks and bit positions */ -+#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -+#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ -+ -+#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -+#define USB_RESUME_bp 2 /* Resume bit position. */ -+ -+#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -+#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ -+ -+#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -+#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ -+ -+/* USB.ADDR bit masks and bit positions */ -+#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -+#define USB_ADDR_gp 0 /* Device Address group position. */ -+#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -+#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -+#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -+#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -+#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -+#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -+#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -+#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -+#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -+#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -+#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -+#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -+#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -+#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ -+ -+/* USB.FIFOWP bit masks and bit positions */ -+#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -+#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -+#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -+#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -+#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -+#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -+#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -+#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -+#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -+#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -+#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -+#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ -+ -+/* USB.FIFORP bit masks and bit positions */ -+#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -+#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -+#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -+#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -+#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -+#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -+#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -+#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -+#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -+#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -+#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -+#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ -+ -+/* USB.INTCTRLA bit masks and bit positions */ -+#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -+#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ -+ -+#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -+#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ -+ -+#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -+#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ -+ -+#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -+#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ -+ -+#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* USB.INTCTRLB bit masks and bit positions */ -+#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -+#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ -+ -+#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -+#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ -+ -+/* USB.INTFLAGSACLR bit masks and bit positions */ -+#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -+#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ -+ -+#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -+#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ -+ -+#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -+#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ -+ -+#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -+#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ -+ -+#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -+#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ -+ -+#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -+#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ -+ -+#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -+#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ -+ -+#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -+#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSASET bit masks and bit positions */ -+/* USB_SOFIF Predefined. */ -+/* USB_SOFIF Predefined. */ -+ -+/* USB_SUSPENDIF Predefined. */ -+/* USB_SUSPENDIF Predefined. */ -+ -+/* USB_RESUMEIF Predefined. */ -+/* USB_RESUMEIF Predefined. */ -+ -+/* USB_RSTIF Predefined. */ -+/* USB_RSTIF Predefined. */ -+ -+/* USB_CRCIF Predefined. */ -+/* USB_CRCIF Predefined. */ -+ -+/* USB_UNFIF Predefined. */ -+/* USB_UNFIF Predefined. */ -+ -+/* USB_OVFIF Predefined. */ -+/* USB_OVFIF Predefined. */ -+ -+/* USB_STALLIF Predefined. */ -+/* USB_STALLIF Predefined. */ -+ -+/* USB.INTFLAGSBCLR bit masks and bit positions */ -+#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -+#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ -+ -+#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -+#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSBSET bit masks and bit positions */ -+/* USB_TRNIF Predefined. */ -+/* USB_TRNIF Predefined. */ -+ -+/* USB_SETUPIF Predefined. */ -+/* USB_SETUPIF Predefined. */ -+ -+/* PORT - I/O Port Configuration */ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ -+ -+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -+#define PORT_SPI_bp 5 /* SPI bit position. */ -+ -+#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -+#define PORT_USART0_bp 4 /* USART0 bit position. */ -+ -+#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -+#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ -+ -+#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -+#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ -+ -+#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -+#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ -+ -+#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -+#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ -+ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC0.CTRLA bit masks and bit positions */ -+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC0.CTRLB bit masks and bit positions */ -+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ -+ -+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ -+ -+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC0.CTRLC bit masks and bit positions */ -+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ -+ -+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ -+ -+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC0.CTRLD bit masks and bit positions */ -+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC0_EVACT_gp 5 /* Event Action group position. */ -+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC0.CTRLE bit masks and bit positions */ -+#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC0.INTCTRLA bit masks and bit positions */ -+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC0.INTCTRLB bit masks and bit positions */ -+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ -+ -+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ -+ -+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC0.CTRLFCLR bit masks and bit positions */ -+#define TC0_CMD_gm 0x0C /* Command group mask. */ -+#define TC0_CMD_gp 2 /* Command group position. */ -+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC0_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC0_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC0_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC0.CTRLFSET bit masks and bit positions */ -+/* TC0_CMD Predefined. */ -+/* TC0_CMD Predefined. */ -+ -+/* TC0_LUPD Predefined. */ -+/* TC0_LUPD Predefined. */ -+ -+/* TC0_DIR Predefined. */ -+/* TC0_DIR Predefined. */ -+ -+/* TC0.CTRLGCLR bit masks and bit positions */ -+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ -+ -+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ -+ -+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC0.CTRLGSET bit masks and bit positions */ -+/* TC0_CCDBV Predefined. */ -+/* TC0_CCDBV Predefined. */ -+ -+/* TC0_CCCBV Predefined. */ -+/* TC0_CCCBV Predefined. */ -+ -+/* TC0_CCBBV Predefined. */ -+/* TC0_CCBBV Predefined. */ -+ -+/* TC0_CCABV Predefined. */ -+/* TC0_CCABV Predefined. */ -+ -+/* TC0_PERBV Predefined. */ -+/* TC0_PERBV Predefined. */ -+ -+/* TC0.INTFLAGS bit masks and bit positions */ -+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ -+ -+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ -+ -+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC1.CTRLA bit masks and bit positions */ -+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC1.CTRLB bit masks and bit positions */ -+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC1.CTRLC bit masks and bit positions */ -+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC1.CTRLD bit masks and bit positions */ -+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC1_EVACT_gp 5 /* Event Action group position. */ -+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC1.CTRLE bit masks and bit positions */ -+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ -+ -+/* TC1.INTCTRLA bit masks and bit positions */ -+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC1.INTCTRLB bit masks and bit positions */ -+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC1.CTRLFCLR bit masks and bit positions */ -+#define TC1_CMD_gm 0x0C /* Command group mask. */ -+#define TC1_CMD_gp 2 /* Command group position. */ -+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC1_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC1_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC1_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC1.CTRLFSET bit masks and bit positions */ -+/* TC1_CMD Predefined. */ -+/* TC1_CMD Predefined. */ -+ -+/* TC1_LUPD Predefined. */ -+/* TC1_LUPD Predefined. */ -+ -+/* TC1_DIR Predefined. */ -+/* TC1_DIR Predefined. */ -+ -+/* TC1.CTRLGCLR bit masks and bit positions */ -+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC1.CTRLGSET bit masks and bit positions */ -+/* TC1_CCBBV Predefined. */ -+/* TC1_CCBBV Predefined. */ -+ -+/* TC1_CCABV Predefined. */ -+/* TC1_CCABV Predefined. */ -+ -+/* TC1_PERBV Predefined. */ -+/* TC1_PERBV Predefined. */ -+ -+/* TC1.INTFLAGS bit masks and bit positions */ -+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+/* TC2.CTRLA bit masks and bit positions */ -+#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC2.CTRLB bit masks and bit positions */ -+#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -+#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ -+ -+#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -+#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ -+ -+#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -+#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ -+ -+#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -+#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ -+ -+#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -+#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ -+ -+#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -+#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ -+ -+#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -+#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ -+ -+#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -+#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ -+ -+/* TC2.CTRLC bit masks and bit positions */ -+#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -+#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ -+ -+#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -+#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ -+ -+#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -+#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ -+ -+#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -+#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ -+ -+#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -+#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ -+ -+#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -+#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ -+ -+#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -+#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ -+ -+#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -+#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ -+ -+/* TC2.CTRLE bit masks and bit positions */ -+#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC2.INTCTRLA bit masks and bit positions */ -+#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -+#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -+#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -+#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -+#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -+#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ -+ -+#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -+#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -+#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -+#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -+#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -+#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ -+ -+/* TC2.INTCTRLB bit masks and bit positions */ -+#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -+#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -+#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -+#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -+#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -+#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -+#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -+#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -+#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -+#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -+#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -+#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -+#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -+#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -+#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -+#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -+#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -+#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -+#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -+#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -+#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ -+ -+/* TC2.CTRLF bit masks and bit positions */ -+#define TC2_CMD_gm 0x0C /* Command group mask. */ -+#define TC2_CMD_gp 2 /* Command group position. */ -+#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC2_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -+#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -+#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -+#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -+#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -+#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ -+ -+/* TC2.INTFLAGS bit masks and bit positions */ -+#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -+#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ -+ -+#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -+#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ -+ -+#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -+#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ -+ -+#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -+#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ -+ -+#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ -+ -+#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ -+ -+/* AWEX - Timer/Counter Advanced Waveform Extension */ -+/* AWEX.CTRL bit masks and bit positions */ -+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ -+ -+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ -+ -+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ -+ -+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ -+ -+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ -+ -+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ -+ -+/* AWEX.FDCTRL bit masks and bit positions */ -+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ -+ -+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ -+ -+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ -+ -+/* AWEX.STATUS bit masks and bit positions */ -+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ -+ -+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ -+ -+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ -+ -+/* AWEX.STATUSSET bit masks and bit positions */ -+/* AWEX_FDF Predefined. */ -+/* AWEX_FDF Predefined. */ -+ -+/* AWEX_DTHSBUFV Predefined. */ -+/* AWEX_DTHSBUFV Predefined. */ -+ -+/* AWEX_DTLSBUFV Predefined. */ -+/* AWEX_DTLSBUFV Predefined. */ -+ -+/* HIRES - Timer/Counter High-Resolution Extension */ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -+#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* LOCKBIT - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT0_vect_num 2 -+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -+#define PORTC_INT1_vect_num 3 -+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT0_vect_num 4 -+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -+#define PORTR_INT1_vect_num 5 -+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ -+ -+/* RTC interrupt vectors */ -+#define RTC_OVF_vect_num 10 -+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -+#define RTC_COMP_vect_num 11 -+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 12 -+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 13 -+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_OVF_vect_num 14 -+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LUNF_vect_num 14 -+#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_ERR_vect_num 15 -+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_HUNF_vect_num 15 -+#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCA_vect_num 16 -+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPA_vect_num 16 -+#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCB_vect_num 17 -+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPB_vect_num 17 -+#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCC_vect_num 18 -+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPC_vect_num 18 -+#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCD_vect_num 19 -+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPD_vect_num 19 -+#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ -+ -+/* TCC1 interrupt vectors */ -+#define TCC1_OVF_vect_num 20 -+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -+#define TCC1_ERR_vect_num 21 -+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -+#define TCC1_CCA_vect_num 22 -+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -+#define TCC1_CCB_vect_num 23 -+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 24 -+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 25 -+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 26 -+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 27 -+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 32 -+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -+#define NVM_SPM_vect_num 33 -+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ -+ -+/* PORTB interrupt vectors */ -+#define PORTB_INT0_vect_num 34 -+#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -+#define PORTB_INT1_vect_num 35 -+#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ -+ -+/* PORTE interrupt vectors */ -+#define PORTE_INT0_vect_num 43 -+#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -+#define PORTE_INT1_vect_num 44 -+#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ -+ -+/* TWIE interrupt vectors */ -+#define TWIE_TWIS_vect_num 45 -+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -+#define TWIE_TWIM_vect_num 46 -+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_OVF_vect_num 47 -+#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LUNF_vect_num 47 -+#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_ERR_vect_num 48 -+#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_HUNF_vect_num 48 -+#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCA_vect_num 49 -+#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPA_vect_num 49 -+#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCB_vect_num 50 -+#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPB_vect_num 50 -+#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCC_vect_num 51 -+#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPC_vect_num 51 -+#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCD_vect_num 52 -+#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPD_vect_num 52 -+#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ -+ -+/* USARTE0 interrupt vectors */ -+#define USARTE0_RXC_vect_num 58 -+#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -+#define USARTE0_DRE_vect_num 59 -+#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -+#define USARTE0_TXC_vect_num 60 -+#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT0_vect_num 64 -+#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -+#define PORTD_INT1_vect_num 65 -+#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ -+ -+/* PORTA interrupt vectors */ -+#define PORTA_INT0_vect_num 66 -+#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -+#define PORTA_INT1_vect_num 67 -+#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ -+ -+/* ACA interrupt vectors */ -+#define ACA_AC0_vect_num 68 -+#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -+#define ACA_AC1_vect_num 69 -+#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -+#define ACA_ACW_vect_num 70 -+#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ -+ -+/* ADCA interrupt vectors */ -+#define ADCA_CH0_vect_num 71 -+#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_OVF_vect_num 77 -+#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LUNF_vect_num 77 -+#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_ERR_vect_num 78 -+#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_HUNF_vect_num 78 -+#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCA_vect_num 79 -+#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPA_vect_num 79 -+#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCB_vect_num 80 -+#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPB_vect_num 80 -+#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCC_vect_num 81 -+#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPC_vect_num 81 -+#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCD_vect_num 82 -+#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPD_vect_num 82 -+#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ -+ -+/* SPID interrupt vectors */ -+#define SPID_INT_vect_num 87 -+#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ -+ -+/* USARTD0 interrupt vectors */ -+#define USARTD0_RXC_vect_num 88 -+#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -+#define USARTD0_DRE_vect_num 89 -+#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -+#define USARTD0_TXC_vect_num 90 -+#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ -+ -+/* PORTF interrupt vectors */ -+#define PORTF_INT0_vect_num 104 -+#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -+#define PORTF_INT1_vect_num 105 -+#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_OVF_vect_num 108 -+#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LUNF_vect_num 108 -+#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_ERR_vect_num 109 -+#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_HUNF_vect_num 109 -+#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCA_vect_num 110 -+#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPA_vect_num 110 -+#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCB_vect_num 111 -+#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPB_vect_num 111 -+#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCC_vect_num 112 -+#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPC_vect_num 112 -+#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCD_vect_num 113 -+#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPD_vect_num 113 -+#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ -+ -+/* USB interrupt vectors */ -+#define USB_BUSEVENT_vect_num 125 -+#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -+#define USB_TRNCOMPL_vect_num 126 -+#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (127 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (270336) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (262144) -+#define APP_SECTION_PAGE_SIZE (512) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0x3E000) -+#define APPTABLE_SECTION_SIZE (8192) -+#define APPTABLE_SECTION_PAGE_SIZE (512) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x40000) -+#define BOOT_SECTION_SIZE (8192) -+#define BOOT_SECTION_PAGE_SIZE (512) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (24576) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (4096) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (16384) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (4096) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (6) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (512) -+#define USER_SIGNATURES_PAGE_SIZE (512) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (64) -+#define PROD_SIGNATURES_PAGE_SIZE (512) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 512 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 6 -+ -+/* Fuse Byte 0 Reserved */ -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x98 -+#define SIGNATURE_2 0x46 -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA256C3_H_INCLUDED */ -+ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox256c3.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA256C3_H_INCLUDED ++#define _AVR_ATXMEGA256C3_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t USBCTRL; /* USB Control Register */ ++} CLK_t; ++ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t reserved_0x02; ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++/* USB Prescaler Division Factor */ ++typedef enum CLK_USBPSDIV_enum ++{ ++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ ++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ ++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ ++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ ++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ ++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ ++} CLK_USBPSDIV_t; ++ ++/* USB Clock Source */ ++typedef enum CLK_USBSRC_enum ++{ ++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ ++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ ++} CLK_USBSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 2 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC2MCREF_enum ++{ ++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC2MCREF_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++ register8_t reserved_0x05; ++ register8_t EVOUTSEL; /* Event Output Select */ ++} PORTCFG_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP02MAP_enum ++{ ++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP02MAP_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP13MAP_enum ++{ ++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP13MAP_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t reserved_0x07; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++} ADC_t; ++ ++/* Current Limitation */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ ++} ADC_CURRLIMIT_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ ++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ ++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ ++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* SDA Hold Time */ ++typedef enum TWI_SDAHOLD_enum ++{ ++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ ++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ ++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ ++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ ++} TWI_SDAHOLD_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USB - USB ++-------------------------------------------------------------------------- ++*/ ++ ++/* USB Endpoint */ ++typedef struct USB_EP_struct ++{ ++ register8_t STATUS; /* Endpoint Status */ ++ register8_t CTRL; /* Endpoint Control */ ++ _WORDREGISTER(CNT); /* USB Endpoint Counter */ ++ _WORDREGISTER(DATAPTR); /* Data Pointer */ ++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ ++} USB_EP_t; ++ ++ ++/* Universal Serial Bus */ ++typedef struct USB_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t FIFOWP; /* FIFO Write Pointer Register */ ++ register8_t FIFORP; /* FIFO Read Pointer Register */ ++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ ++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ ++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ ++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t reserved_0x20; ++ register8_t reserved_0x21; ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t CAL0; /* Calibration Byte 0 */ ++ register8_t CAL1; /* Calibration Byte 1 */ ++} USB_t; ++ ++ ++/* USB Endpoint Table */ ++typedef struct USB_EP_TABLE_struct ++{ ++ USB_EP_t EP0OUT; /* Endpoint 0 */ ++ USB_EP_t EP0IN; /* Endpoint 0 */ ++ USB_EP_t EP1OUT; /* Endpoint 1 */ ++ USB_EP_t EP1IN; /* Endpoint 1 */ ++ USB_EP_t EP2OUT; /* Endpoint 2 */ ++ USB_EP_t EP2IN; /* Endpoint 2 */ ++ USB_EP_t EP3OUT; /* Endpoint 3 */ ++ USB_EP_t EP3IN; /* Endpoint 3 */ ++ USB_EP_t EP4OUT; /* Endpoint 4 */ ++ USB_EP_t EP4IN; /* Endpoint 4 */ ++ USB_EP_t EP5OUT; /* Endpoint 5 */ ++ USB_EP_t EP5IN; /* Endpoint 5 */ ++ USB_EP_t EP6OUT; /* Endpoint 6 */ ++ USB_EP_t EP6IN; /* Endpoint 6 */ ++ USB_EP_t EP7OUT; /* Endpoint 7 */ ++ USB_EP_t EP7IN; /* Endpoint 7 */ ++ USB_EP_t EP8OUT; /* Endpoint 8 */ ++ USB_EP_t EP8IN; /* Endpoint 8 */ ++ USB_EP_t EP9OUT; /* Endpoint 9 */ ++ USB_EP_t EP9IN; /* Endpoint 9 */ ++ USB_EP_t EP10OUT; /* Endpoint 10 */ ++ USB_EP_t EP10IN; /* Endpoint 10 */ ++ USB_EP_t EP11OUT; /* Endpoint 11 */ ++ USB_EP_t EP11IN; /* Endpoint 11 */ ++ USB_EP_t EP12OUT; /* Endpoint 12 */ ++ USB_EP_t EP12IN; /* Endpoint 12 */ ++ USB_EP_t EP13OUT; /* Endpoint 13 */ ++ USB_EP_t EP13IN; /* Endpoint 13 */ ++ USB_EP_t EP14OUT; /* Endpoint 14 */ ++ USB_EP_t EP14IN; /* Endpoint 14 */ ++ USB_EP_t EP15OUT; /* Endpoint 15 */ ++ USB_EP_t EP15IN; /* Endpoint 15 */ ++ register8_t reserved_0x100; ++ register8_t reserved_0x101; ++ register8_t reserved_0x102; ++ register8_t reserved_0x103; ++ register8_t reserved_0x104; ++ register8_t reserved_0x105; ++ register8_t reserved_0x106; ++ register8_t reserved_0x107; ++ register8_t reserved_0x108; ++ register8_t reserved_0x109; ++ register8_t reserved_0x10A; ++ register8_t reserved_0x10B; ++ register8_t reserved_0x10C; ++ register8_t reserved_0x10D; ++ register8_t reserved_0x10E; ++ register8_t reserved_0x10F; ++ register8_t FRAMENUML; /* Frame Number Low Byte */ ++ register8_t FRAMENUMH; /* Frame Number High Byte */ ++} USB_EP_TABLE_t; ++ ++/* Interrupt level */ ++typedef enum USB_INTLVL_enum ++{ ++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} USB_INTLVL_t; ++ ++/* USB Endpoint Type */ ++typedef enum USB_EP_TYPE_enum ++{ ++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ ++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ ++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ ++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ ++} USB_EP_TYPE_t; ++ ++/* USB Endpoint Buffersize */ ++typedef enum USB_EP_BUFSIZE_enum ++{ ++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ ++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ ++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ ++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ ++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ ++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ ++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ ++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ ++} USB_EP_BUFSIZE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - I/O Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* I/O Port Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Byte Mode */ ++typedef enum TC_BYTEM_enum ++{ ++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ ++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ ++} TC_BYTEM_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC2 - 16-bit Timer/Counter type 2 ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter type 2 */ ++typedef struct TC2_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t reserved_0x03; ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t reserved_0x08; ++ register8_t CTRLF; /* Control Register F */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t LCNT; /* Low Byte Count */ ++ register8_t HCNT; /* High Byte Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t LPER; /* Low Byte Period */ ++ register8_t HPER; /* High Byte Period */ ++ register8_t LCMPA; /* Low Byte Compare A */ ++ register8_t HCMPA; /* High Byte Compare A */ ++ register8_t LCMPB; /* Low Byte Compare B */ ++ register8_t HCMPB; /* High Byte Compare B */ ++ register8_t LCMPC; /* Low Byte Compare C */ ++ register8_t HCMPC; /* High Byte Compare C */ ++ register8_t LCMPD; /* Low Byte Compare D */ ++ register8_t HCMPD; /* High Byte Compare D */ ++} TC2_t; ++ ++/* Clock Selection */ ++typedef enum TC2_CLKSEL_enum ++{ ++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC2_CLKSEL_t; ++ ++/* Byte Mode */ ++typedef enum TC2_BYTEM_enum ++{ ++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ ++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ ++} TC2_BYTEM_t; ++ ++/* High Byte Underflow Interrupt Level */ ++typedef enum TC2_HUNFINTLVL_enum ++{ ++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_HUNFINTLVL_t; ++ ++/* Low Byte Underflow Interrupt Level */ ++typedef enum TC2_LUNFINTLVL_enum ++{ ++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LUNFINTLVL_t; ++ ++/* Low Byte Compare D Interrupt Level */ ++typedef enum TC2_LCMPDINTLVL_enum ++{ ++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC2_LCMPDINTLVL_t; ++ ++/* Low Byte Compare C Interrupt Level */ ++typedef enum TC2_LCMPCINTLVL_enum ++{ ++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC2_LCMPCINTLVL_t; ++ ++/* Low Byte Compare B Interrupt Level */ ++typedef enum TC2_LCMPBINTLVL_enum ++{ ++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_LCMPBINTLVL_t; ++ ++/* Low Byte Compare A Interrupt Level */ ++typedef enum TC2_LCMPAINTLVL_enum ++{ ++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LCMPAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMD_enum ++{ ++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC2_CMD_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMDEN_enum ++{ ++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ ++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ ++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ ++} TC2_CMDEN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AWEX - Timer/Counter Advanced Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - Timer/Counter High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t reserved_0x00; ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* Timer Oscillator pin location */ ++typedef enum TOSCSEL_enum ++{ ++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ ++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ ++} TOSCSEL_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* BOD operation */ ++typedef enum BODACT_enum ++{ ++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BODACT_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WDP_enum ++{ ++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ ++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ ++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ ++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ ++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ ++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ ++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ ++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ ++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ ++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ ++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ ++} WDP_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LOCKBIT - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ ++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t USBCAL0; /* USB Calibration Byte 0 */ ++ register8_t USBCAL1; /* USB Calibration Byte 1 */ ++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ ++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ ++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ ++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ ++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ ++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ ++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ ++#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) ++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) ++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) ++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++#define CLK_USBCTRL _SFR_MEM8(0x0044) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLL - DFLL */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* USB - Universal Serial Bus */ ++#define USB_CTRLA _SFR_MEM8(0x04C0) ++#define USB_CTRLB _SFR_MEM8(0x04C1) ++#define USB_STATUS _SFR_MEM8(0x04C2) ++#define USB_ADDR _SFR_MEM8(0x04C3) ++#define USB_FIFOWP _SFR_MEM8(0x04C4) ++#define USB_FIFORP _SFR_MEM8(0x04C5) ++#define USB_EPPTR _SFR_MEM16(0x04C6) ++#define USB_INTCTRLA _SFR_MEM8(0x04C8) ++#define USB_INTCTRLB _SFR_MEM8(0x04C9) ++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) ++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) ++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) ++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) ++#define USB_CAL0 _SFR_MEM8(0x04FA) ++#define USB_CAL1 _SFR_MEM8(0x04FB) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_REMAP _SFR_MEM8(0x060E) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_REMAP _SFR_MEM8(0x062E) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_REMAP _SFR_MEM8(0x068E) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORT - I/O Ports */ ++#define PORTF_DIR _SFR_MEM8(0x06A0) ++#define PORTF_DIRSET _SFR_MEM8(0x06A1) ++#define PORTF_DIRCLR _SFR_MEM8(0x06A2) ++#define PORTF_DIRTGL _SFR_MEM8(0x06A3) ++#define PORTF_OUT _SFR_MEM8(0x06A4) ++#define PORTF_OUTSET _SFR_MEM8(0x06A5) ++#define PORTF_OUTCLR _SFR_MEM8(0x06A6) ++#define PORTF_OUTTGL _SFR_MEM8(0x06A7) ++#define PORTF_IN _SFR_MEM8(0x06A8) ++#define PORTF_INTCTRL _SFR_MEM8(0x06A9) ++#define PORTF_INT0MASK _SFR_MEM8(0x06AA) ++#define PORTF_INT1MASK _SFR_MEM8(0x06AB) ++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) ++#define PORTF_REMAP _SFR_MEM8(0x06AE) ++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) ++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) ++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) ++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) ++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) ++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) ++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) ++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCC2_CTRLA _SFR_MEM8(0x0800) ++#define TCC2_CTRLB _SFR_MEM8(0x0801) ++#define TCC2_CTRLC _SFR_MEM8(0x0802) ++#define TCC2_CTRLE _SFR_MEM8(0x0804) ++#define TCC2_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC2_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC2_CTRLF _SFR_MEM8(0x0809) ++#define TCC2_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC2_LCNT _SFR_MEM8(0x0820) ++#define TCC2_HCNT _SFR_MEM8(0x0821) ++#define TCC2_LPER _SFR_MEM8(0x0826) ++#define TCC2_HPER _SFR_MEM8(0x0827) ++#define TCC2_LCMPA _SFR_MEM8(0x0828) ++#define TCC2_HCMPA _SFR_MEM8(0x0829) ++#define TCC2_LCMPB _SFR_MEM8(0x082A) ++#define TCC2_HCMPB _SFR_MEM8(0x082B) ++#define TCC2_LCMPC _SFR_MEM8(0x082C) ++#define TCC2_HCMPC _SFR_MEM8(0x082D) ++#define TCC2_LCMPD _SFR_MEM8(0x082E) ++#define TCC2_HCMPD _SFR_MEM8(0x082F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_STATUSSET _SFR_MEM8(0x0885) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCD2_CTRLA _SFR_MEM8(0x0900) ++#define TCD2_CTRLB _SFR_MEM8(0x0901) ++#define TCD2_CTRLC _SFR_MEM8(0x0902) ++#define TCD2_CTRLE _SFR_MEM8(0x0904) ++#define TCD2_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD2_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD2_CTRLF _SFR_MEM8(0x0909) ++#define TCD2_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD2_LCNT _SFR_MEM8(0x0920) ++#define TCD2_HCNT _SFR_MEM8(0x0921) ++#define TCD2_LPER _SFR_MEM8(0x0926) ++#define TCD2_HPER _SFR_MEM8(0x0927) ++#define TCD2_LCMPA _SFR_MEM8(0x0928) ++#define TCD2_HCMPA _SFR_MEM8(0x0929) ++#define TCD2_LCMPB _SFR_MEM8(0x092A) ++#define TCD2_HCMPB _SFR_MEM8(0x092B) ++#define TCD2_LCMPC _SFR_MEM8(0x092C) ++#define TCD2_HCMPC _SFR_MEM8(0x092D) ++#define TCD2_LCMPD _SFR_MEM8(0x092E) ++#define TCD2_HCMPD _SFR_MEM8(0x092F) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCE2_CTRLA _SFR_MEM8(0x0A00) ++#define TCE2_CTRLB _SFR_MEM8(0x0A01) ++#define TCE2_CTRLC _SFR_MEM8(0x0A02) ++#define TCE2_CTRLE _SFR_MEM8(0x0A04) ++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE2_CTRLF _SFR_MEM8(0x0A09) ++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE2_LCNT _SFR_MEM8(0x0A20) ++#define TCE2_HCNT _SFR_MEM8(0x0A21) ++#define TCE2_LPER _SFR_MEM8(0x0A26) ++#define TCE2_HPER _SFR_MEM8(0x0A27) ++#define TCE2_LCMPA _SFR_MEM8(0x0A28) ++#define TCE2_HCMPA _SFR_MEM8(0x0A29) ++#define TCE2_LCMPB _SFR_MEM8(0x0A2A) ++#define TCE2_HCMPB _SFR_MEM8(0x0A2B) ++#define TCE2_LCMPC _SFR_MEM8(0x0A2C) ++#define TCE2_HCMPC _SFR_MEM8(0x0A2D) ++#define TCE2_LCMPD _SFR_MEM8(0x0A2E) ++#define TCE2_HCMPD _SFR_MEM8(0x0A2F) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCF0_CTRLA _SFR_MEM8(0x0B00) ++#define TCF0_CTRLB _SFR_MEM8(0x0B01) ++#define TCF0_CTRLC _SFR_MEM8(0x0B02) ++#define TCF0_CTRLD _SFR_MEM8(0x0B03) ++#define TCF0_CTRLE _SFR_MEM8(0x0B04) ++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) ++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) ++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) ++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) ++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF0_TEMP _SFR_MEM8(0x0B0F) ++#define TCF0_CNT _SFR_MEM16(0x0B20) ++#define TCF0_PER _SFR_MEM16(0x0B26) ++#define TCF0_CCA _SFR_MEM16(0x0B28) ++#define TCF0_CCB _SFR_MEM16(0x0B2A) ++#define TCF0_CCC _SFR_MEM16(0x0B2C) ++#define TCF0_CCD _SFR_MEM16(0x0B2E) ++#define TCF0_PERBUF _SFR_MEM16(0x0B36) ++#define TCF0_CCABUF _SFR_MEM16(0x0B38) ++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) ++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) ++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCF2_CTRLA _SFR_MEM8(0x0B00) ++#define TCF2_CTRLB _SFR_MEM8(0x0B01) ++#define TCF2_CTRLC _SFR_MEM8(0x0B02) ++#define TCF2_CTRLE _SFR_MEM8(0x0B04) ++#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF2_CTRLF _SFR_MEM8(0x0B09) ++#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF2_LCNT _SFR_MEM8(0x0B20) ++#define TCF2_HCNT _SFR_MEM8(0x0B21) ++#define TCF2_LPER _SFR_MEM8(0x0B26) ++#define TCF2_HPER _SFR_MEM8(0x0B27) ++#define TCF2_LCMPA _SFR_MEM8(0x0B28) ++#define TCF2_HCMPA _SFR_MEM8(0x0B29) ++#define TCF2_LCMPB _SFR_MEM8(0x0B2A) ++#define TCF2_HCMPB _SFR_MEM8(0x0B2B) ++#define TCF2_LCMPC _SFR_MEM8(0x0B2C) ++#define TCF2_HCMPC _SFR_MEM8(0x0B2D) ++#define TCF2_LCMPD _SFR_MEM8(0x0B2E) ++#define TCF2_HCMPD _SFR_MEM8(0x0B2F) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* CLK.USBCTRL bit masks and bit positions */ ++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ ++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ ++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ ++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ ++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ ++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ ++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ ++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ ++ ++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ ++#define CLK_USBSRC_gp 1 /* Clock Source group position. */ ++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ ++ ++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_USB_bm 0x40 /* USB bit mask. */ ++#define PR_USB_bp 6 /* USB bit position. */ ++ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ ++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ ++ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ ++ ++/* PORTCFG.EVOUTSEL bit masks and bit positions */ ++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ ++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ ++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ ++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ ++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ ++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ ++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ ++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ ++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ ++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ ++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ ++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ ++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ ++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ ++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ ++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ ++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ ++ ++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ ++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ ++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ ++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ ++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ ++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ ++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ ++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ ++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ ++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ ++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* RTC - Real-Time Counter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* USB - USB */ ++/* USB_EP.STATUS bit masks and bit positions */ ++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ ++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ ++ ++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ ++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ ++ ++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ ++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ ++ ++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ ++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ ++ ++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ ++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ ++ ++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ ++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ ++ ++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ ++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ ++ ++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ ++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ ++ ++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ ++ ++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ ++ ++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ ++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ ++ ++/* USB_EP.CTRL bit masks and bit positions */ ++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ ++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ ++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ ++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ ++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ ++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ ++ ++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ ++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ ++ ++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ ++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ ++ ++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ ++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ ++ ++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ ++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ ++ ++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ ++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ ++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ ++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ ++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ ++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ ++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ ++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ ++ ++/* USB_EP.CNT bit masks and bit positions */ ++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ ++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ ++ ++/* USB.CTRLA bit masks and bit positions */ ++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ ++#define USB_ENABLE_bp 7 /* USB Enable bit position. */ ++ ++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ ++#define USB_SPEED_bp 6 /* Speed Select bit position. */ ++ ++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ ++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ ++ ++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ ++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ ++ ++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ ++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ ++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ ++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ ++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ ++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ ++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ ++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ ++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ ++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ ++ ++/* USB.CTRLB bit masks and bit positions */ ++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ ++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ ++ ++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ ++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ ++ ++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ ++#define USB_GNACK_bp 1 /* Global NACK bit position. */ ++ ++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ ++#define USB_ATTACH_bp 0 /* Attach bit position. */ ++ ++/* USB.STATUS bit masks and bit positions */ ++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ ++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ ++ ++#define USB_RESUME_bm 0x04 /* Resume bit mask. */ ++#define USB_RESUME_bp 2 /* Resume bit position. */ ++ ++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ ++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ ++ ++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ ++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ ++ ++/* USB.ADDR bit masks and bit positions */ ++#define USB_ADDR_gm 0x7F /* Device Address group mask. */ ++#define USB_ADDR_gp 0 /* Device Address group position. */ ++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ ++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ ++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ ++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ ++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ ++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ ++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ ++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ ++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ ++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ ++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ ++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ ++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ ++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ ++ ++/* USB.FIFOWP bit masks and bit positions */ ++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ ++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ ++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ ++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ ++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ ++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ ++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ ++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ ++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ ++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ ++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ ++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ ++ ++/* USB.FIFORP bit masks and bit positions */ ++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ ++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ ++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ ++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ ++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ ++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ ++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ ++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ ++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ ++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ ++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ ++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ ++ ++/* USB.INTCTRLA bit masks and bit positions */ ++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ ++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ ++ ++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ ++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ ++ ++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ ++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ ++ ++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ ++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ ++ ++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* USB.INTCTRLB bit masks and bit positions */ ++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ ++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ ++ ++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ ++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ ++ ++/* USB.INTFLAGSACLR bit masks and bit positions */ ++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ ++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ ++ ++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ ++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ ++ ++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ ++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ ++ ++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ ++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ ++ ++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ ++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ ++ ++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ ++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ ++ ++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ ++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ ++ ++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ ++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSASET bit masks and bit positions */ ++/* USB_SOFIF Predefined. */ ++/* USB_SOFIF Predefined. */ ++ ++/* USB_SUSPENDIF Predefined. */ ++/* USB_SUSPENDIF Predefined. */ ++ ++/* USB_RESUMEIF Predefined. */ ++/* USB_RESUMEIF Predefined. */ ++ ++/* USB_RSTIF Predefined. */ ++/* USB_RSTIF Predefined. */ ++ ++/* USB_CRCIF Predefined. */ ++/* USB_CRCIF Predefined. */ ++ ++/* USB_UNFIF Predefined. */ ++/* USB_UNFIF Predefined. */ ++ ++/* USB_OVFIF Predefined. */ ++/* USB_OVFIF Predefined. */ ++ ++/* USB_STALLIF Predefined. */ ++/* USB_STALLIF Predefined. */ ++ ++/* USB.INTFLAGSBCLR bit masks and bit positions */ ++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ ++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ ++ ++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ ++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSBSET bit masks and bit positions */ ++/* USB_TRNIF Predefined. */ ++/* USB_TRNIF Predefined. */ ++ ++/* USB_SETUPIF Predefined. */ ++/* USB_SETUPIF Predefined. */ ++ ++/* PORT - I/O Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_SPI_bm 0x20 /* SPI bit mask. */ ++#define PORT_SPI_bp 5 /* SPI bit position. */ ++ ++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ ++#define PORT_USART0_bp 4 /* USART0 bit position. */ ++ ++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ ++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ ++ ++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ ++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ ++ ++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ ++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ ++ ++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ ++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD Predefined. */ ++/* TC0_CMD Predefined. */ ++ ++/* TC0_LUPD Predefined. */ ++/* TC0_LUPD Predefined. */ ++ ++/* TC0_DIR Predefined. */ ++/* TC0_DIR Predefined. */ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV Predefined. */ ++/* TC0_CCDBV Predefined. */ ++ ++/* TC0_CCCBV Predefined. */ ++/* TC0_CCCBV Predefined. */ ++ ++/* TC0_CCBBV Predefined. */ ++/* TC0_CCBBV Predefined. */ ++ ++/* TC0_CCABV Predefined. */ ++/* TC0_CCABV Predefined. */ ++ ++/* TC0_PERBV Predefined. */ ++/* TC0_PERBV Predefined. */ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD Predefined. */ ++/* TC1_CMD Predefined. */ ++ ++/* TC1_LUPD Predefined. */ ++/* TC1_LUPD Predefined. */ ++ ++/* TC1_DIR Predefined. */ ++/* TC1_DIR Predefined. */ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV Predefined. */ ++/* TC1_CCBBV Predefined. */ ++ ++/* TC1_CCABV Predefined. */ ++/* TC1_CCABV Predefined. */ ++ ++/* TC1_PERBV Predefined. */ ++/* TC1_PERBV Predefined. */ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++/* TC2.CTRLA bit masks and bit positions */ ++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC2.CTRLB bit masks and bit positions */ ++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ ++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ ++ ++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ ++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ ++ ++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ ++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ ++ ++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ ++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ ++ ++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ ++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ ++ ++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ ++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ ++ ++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ ++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ ++ ++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ ++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ ++ ++/* TC2.CTRLC bit masks and bit positions */ ++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ ++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ ++ ++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ ++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ ++ ++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ ++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ ++ ++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ ++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ ++ ++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ ++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ ++ ++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ ++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ ++ ++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ ++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ ++ ++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ ++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ ++ ++/* TC2.CTRLE bit masks and bit positions */ ++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC2.INTCTRLA bit masks and bit positions */ ++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ ++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ ++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ ++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ ++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ ++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ ++ ++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ ++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ ++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ ++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ ++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ ++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ ++ ++/* TC2.INTCTRLB bit masks and bit positions */ ++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ ++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ ++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ ++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ ++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ ++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ ++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ ++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ ++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ ++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ ++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ ++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ ++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ ++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ ++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ ++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ ++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ ++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ ++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ ++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ ++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ ++ ++/* TC2.CTRLF bit masks and bit positions */ ++#define TC2_CMD_gm 0x0C /* Command group mask. */ ++#define TC2_CMD_gp 2 /* Command group position. */ ++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC2_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC2_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ ++#define TC2_CMDEN_gp 0 /* Command Enable group position. */ ++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ ++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ ++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ ++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ ++ ++/* TC2.INTFLAGS bit masks and bit positions */ ++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ ++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ ++ ++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ ++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ ++ ++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ ++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ ++ ++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ ++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ ++ ++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ ++ ++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ ++ ++/* AWEX - Timer/Counter Advanced Waveform Extension */ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++/* AWEX.STATUSSET bit masks and bit positions */ ++/* AWEX_FDF Predefined. */ ++/* AWEX_FDF Predefined. */ ++ ++/* AWEX_DTHSBUFV Predefined. */ ++/* AWEX_DTHSBUFV Predefined. */ ++ ++/* AWEX_DTLSBUFV Predefined. */ ++/* AWEX_DTLSBUFV Predefined. */ ++ ++/* HIRES - Timer/Counter High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ ++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* LOCKBIT - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LUNF_vect_num 14 ++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_HUNF_vect_num 15 ++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPA_vect_num 16 ++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPB_vect_num 17 ++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPC_vect_num 18 ++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPD_vect_num 19 ++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LUNF_vect_num 47 ++#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_HUNF_vect_num 48 ++#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPA_vect_num 49 ++#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPB_vect_num 50 ++#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPC_vect_num 51 ++#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPD_vect_num 52 ++#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LUNF_vect_num 77 ++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_HUNF_vect_num 78 ++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPA_vect_num 79 ++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPB_vect_num 80 ++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPC_vect_num 81 ++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPD_vect_num 82 ++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* PORTF interrupt vectors */ ++#define PORTF_INT0_vect_num 104 ++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ ++#define PORTF_INT1_vect_num 105 ++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_OVF_vect_num 108 ++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LUNF_vect_num 108 ++#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_ERR_vect_num 109 ++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_HUNF_vect_num 109 ++#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCA_vect_num 110 ++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPA_vect_num 110 ++#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCB_vect_num 111 ++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPB_vect_num 111 ++#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCC_vect_num 112 ++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPC_vect_num 112 ++#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCD_vect_num 113 ++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPD_vect_num 113 ++#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ ++ ++/* USB interrupt vectors */ ++#define USB_BUSEVENT_vect_num 125 ++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ ++#define USB_TRNCOMPL_vect_num 126 ++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (127 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (270336) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (262144) ++#define APP_SECTION_PAGE_SIZE (512) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x3E000) ++#define APPTABLE_SECTION_SIZE (8192) ++#define APPTABLE_SECTION_PAGE_SIZE (512) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x40000) ++#define BOOT_SECTION_SIZE (8192) ++#define BOOT_SECTION_PAGE_SIZE (512) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (24576) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (4096) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (16384) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (4096) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (6) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (512) ++#define USER_SIGNATURES_PAGE_SIZE (512) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (64) ++#define PROD_SIGNATURES_PAGE_SIZE (512) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 512 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 Reserved */ ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x98 ++#define SIGNATURE_2 0x46 ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA256C3_H_INCLUDED */ ++ diff --git a/include/avr/iox256d3.h b/include/avr/iox256d3.h -index 72e167b..f6d476d 100644 +index 72e167b..37b1818 100644 --- a/include/avr/iox256d3.h +++ b/include/avr/iox256d3.h -@@ -163,6 +163,19 @@ typedef struct CLK_struct - register8_t RTCCTRL; /* RTC Control Register */ - } CLK_t; - -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t reserved_0x02; -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t PRPD; /* Power Reduction Port D */ -+ register8_t PRPE; /* Power Reduction Port E */ -+ register8_t PRPF; /* Power Reduction Port F */ -+} PR_t; -+ - /* System Clock Selection */ - typedef enum CLK_SCLKSEL_enum - { -@@ -398,6 +411,46 @@ typedef struct PMIC_struct - - /* - -------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ -+ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ -+ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ -+ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- - EVSYS - Event System - -------------------------------------------------------------------------- - */ -@@ -985,6 +1038,15 @@ typedef struct ADC_struct - ADC_CH_t CH0; /* ADC Channel 0 */ - } ADC_t; - -+/* Current Limitation */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 225ksps max sampling rate */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 75ksps max sampling rate */ -+} ADC_CURRLIMIT_t; -+ - /* Positive input multiplexer selection */ - typedef enum ADC_CH_MUXPOS_enum - { -@@ -1030,6 +1092,7 @@ typedef enum ADC_CH_GAIN_enum - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ - } ADC_CH_GAIN_t; - - /* Conversion result resolution */ -@@ -2144,12 +2207,14 @@ IO Module Instances. Mapped to memory. - #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ - #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ - #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ - #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ - #define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ - #define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ - #define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ - #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ - #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ - #define PORTA (*(PORT_t *) 0x0600) /* Port A */ - #define PORTB (*(PORT_t *) 0x0620) /* Port B */ - #define PORTC (*(PORT_t *) 0x0640) /* Port C */ -@@ -2270,6 +2335,14 @@ IO Module Instances. Mapped to memory. - #define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) - #define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) - -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPD _SFR_MEM8(0x0074) -+#define PR_PRPE _SFR_MEM8(0x0075) -+#define PR_PRPF _SFR_MEM8(0x0076) -+ - /* RST - Reset Controller */ - #define RST_STATUS _SFR_MEM8(0x0078) - #define RST_CTRL _SFR_MEM8(0x0079) -@@ -2300,6 +2373,15 @@ IO Module Instances. Mapped to memory. - #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) - #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) - -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ - /* EVSYS - Event System */ - #define EVSYS_CH0MUX _SFR_MEM8(0x0180) - #define EVSYS_CH1MUX _SFR_MEM8(0x0181) -@@ -2379,6 +2461,22 @@ IO Module Instances. Mapped to memory. - #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) - #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -+/* TWIE - Two-Wire Interface E */ -+#define TWIE_CTRL _SFR_MEM8(0x04A0) -+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -+ - /* PORTA - Port A */ - #define PORTA_DIR _SFR_MEM8(0x0600) - #define PORTA_DIRSET _SFR_MEM8(0x0601) -@@ -2855,6 +2953,65 @@ IO Module Instances. Mapped to memory. - #define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ - #define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ - -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ -+#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ -+ -+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -+ -+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ -+ -+/* PR.PRPD bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPE bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPF bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ - - /* SLEEP - Sleep Controller */ - /* SLEEP.CTRL bit masks and bit positions */ -@@ -3136,6 +3293,37 @@ IO Module Instances. Mapped to memory. - #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - - -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+ - /* EVSYS - Event System */ - /* EVSYS.CH0MUX bit masks and bit positions */ - #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -@@ -3757,6 +3945,13 @@ IO Module Instances. Mapped to memory. - - - /* ADC.CTRLB bit masks and bit positions */ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ -+ - #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ - #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -@@ -5213,6 +5408,12 @@ IO Module Instances. Mapped to memory. - #define PORTE_INT1_vect_num 44 - #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -+/* TWIE interrupt vectors */ -+#define TWIE_TWIS_vect_num 45 -+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -+#define TWIE_TWIM_vect_num 46 -+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ -+ - /* TCE0 interrupt vectors */ - #define TCE0_OVF_vect_num 47 - #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +@@ -1,5462 +1,5663 @@ +-/* Copyright (c) 2009-2010 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iox256d3.h 2162 2010-06-11 17:26:12Z arcanum $ */ +- +-/* avr/iox256d3.h - definitions for ATxmega256D3 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iox256d3.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATxmega256D3_H_ +-#define _AVR_ATxmega256D3_H_ 1 +- +- +-/* Ungrouped common registers */ +-#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +-#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +-#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +-#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +-#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +-#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +-#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +-#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +-#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +-#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +-#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +-#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +-#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +-#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +-#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +-#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +- +-#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +-#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +-#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +-#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +-#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +-#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +-#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +-#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +-#define SREG _SFR_MEM8(0x003F) /* Status Register */ +- +- +-/* C Language Only */ +-#if !defined (__ASSEMBLER__) +- +-#include +- +-typedef volatile uint8_t register8_t; +-typedef volatile uint16_t register16_t; +-typedef volatile uint32_t register32_t; +- +- +-#ifdef _WORDREGISTER +-#undef _WORDREGISTER +-#endif +-#define _WORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register16_t regname; \ +- struct \ +- { \ +- register8_t regname ## L; \ +- register8_t regname ## H; \ +- }; \ +- } +- +-#ifdef _DWORDREGISTER +-#undef _DWORDREGISTER +-#endif +-#define _DWORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register32_t regname; \ +- struct \ +- { \ +- register8_t regname ## 0; \ +- register8_t regname ## 1; \ +- register8_t regname ## 2; \ +- register8_t regname ## 3; \ +- }; \ +- } +- +- +-/* +-========================================================================== +-IO Module Structures +-========================================================================== +-*/ +- +- +-/* +--------------------------------------------------------------------------- +-XOCD - On-Chip Debug System +--------------------------------------------------------------------------- +-*/ +- +-/* On-Chip Debug System */ +-typedef struct OCD_struct +-{ +- register8_t OCDR0; /* OCD Register 0 */ +- register8_t OCDR1; /* OCD Register 1 */ +-} OCD_t; +- +- +-/* CCP signatures */ +-typedef enum CCP_enum +-{ +- CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ +- CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +-} CCP_t; +- +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Clock System */ +-typedef struct CLK_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t PSCTRL; /* Prescaler Control Register */ +- register8_t LOCK; /* Lock register */ +- register8_t RTCCTRL; /* RTC Control Register */ +-} CLK_t; +- +-/* System Clock Selection */ +-typedef enum CLK_SCLKSEL_enum +-{ +- CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ +- CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ +- CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ +- CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ +- CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +-} CLK_SCLKSEL_t; +- +-/* Prescaler A Division Factor */ +-typedef enum CLK_PSADIV_enum +-{ +- CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ +- CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ +- CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ +- CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ +- CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ +- CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ +- CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ +- CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ +- CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ +- CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +-} CLK_PSADIV_t; +- +-/* Prescaler B and C Division Factor */ +-typedef enum CLK_PSBCDIV_enum +-{ +- CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ +- CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ +- CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ +- CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +-} CLK_PSBCDIV_t; +- +-/* RTC Clock Source */ +-typedef enum CLK_RTCSRC_enum +-{ +- CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ +- CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ +- CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ +- CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +-} CLK_RTCSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-SLEEP - Sleep Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Sleep Controller */ +-typedef struct SLEEP_struct +-{ +- register8_t CTRL; /* Control Register */ +-} SLEEP_t; +- +-/* Sleep Mode */ +-typedef enum SLEEP_SMODE_enum +-{ +- SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ +- SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +- SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ +- SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ +- SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +-} SLEEP_SMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-OSC - Oscillator +--------------------------------------------------------------------------- +-*/ +- +-/* Oscillator */ +-typedef struct OSC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t XOSCCTRL; /* External Oscillator Control Register */ +- register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ +- register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ +- register8_t PLLCTRL; /* PLL Control REgister */ +- register8_t DFLLCTRL; /* DFLL Control Register */ +-} OSC_t; +- +-/* Oscillator Frequency Range */ +-typedef enum OSC_FRQRANGE_enum +-{ +- OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ +- OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ +- OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ +- OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +-} OSC_FRQRANGE_t; +- +-/* External Oscillator Selection and Startup Time */ +-typedef enum OSC_XOSCSEL_enum +-{ +- OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ +- OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ +- OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ +- OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ +- OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +-} OSC_XOSCSEL_t; +- +-/* PLL Clock Source */ +-typedef enum OSC_PLLSRC_enum +-{ +- OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ +- OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ +- OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +-} OSC_PLLSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-DFLL - DFLL +--------------------------------------------------------------------------- +-*/ +- +-/* DFLL */ +-typedef struct DFLL_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t CALA; /* Calibration Register A */ +- register8_t CALB; /* Calibration Register B */ +- register8_t COMP0; /* Oscillator Compare Register 0 */ +- register8_t COMP1; /* Oscillator Compare Register 1 */ +- register8_t COMP2; /* Oscillator Compare Register 2 */ +- register8_t reserved_0x07; +-} DFLL_t; +- +- +-/* +--------------------------------------------------------------------------- +-RST - Reset +--------------------------------------------------------------------------- +-*/ +- +-/* Reset */ +-typedef struct RST_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t CTRL; /* Control Register */ +-} RST_t; +- +- +-/* +--------------------------------------------------------------------------- +-WDT - Watch-Dog Timer +--------------------------------------------------------------------------- +-*/ +- +-/* Watch-Dog Timer */ +-typedef struct WDT_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t WINCTRL; /* Windowed Mode Control */ +- register8_t STATUS; /* Status */ +-} WDT_t; +- +-/* Period setting */ +-typedef enum WDT_PER_enum +-{ +- WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ +- WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ +- WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ +- WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_PER_t; +- +-/* Closed window period */ +-typedef enum WDT_WPER_enum +-{ +- WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ +- WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ +- WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ +- WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_WPER_t; +- +- +-/* +--------------------------------------------------------------------------- +-MCU - MCU Control +--------------------------------------------------------------------------- +-*/ +- +-/* MCU Control */ +-typedef struct MCU_struct +-{ +- register8_t DEVID0; /* Device ID byte 0 */ +- register8_t DEVID1; /* Device ID byte 1 */ +- register8_t DEVID2; /* Device ID byte 2 */ +- register8_t REVID; /* Revision ID */ +- register8_t JTAGUID; /* JTAG User ID */ +- register8_t reserved_0x05; +- register8_t MCUCR; /* MCU Control */ +- register8_t reserved_0x07; +- register8_t EVSYSLOCK; /* Event System Lock */ +- register8_t AWEXLOCK; /* AWEX Lock */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +-} MCU_t; +- +- +-/* +--------------------------------------------------------------------------- +-PMIC - Programmable Multi-level Interrupt Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Programmable Multi-level Interrupt Controller */ +-typedef struct PMIC_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t INTPRI; /* Interrupt Priority */ +- register8_t CTRL; /* Control Register */ +-} PMIC_t; +- +- +-/* +--------------------------------------------------------------------------- +-EVSYS - Event System +--------------------------------------------------------------------------- +-*/ +- +-/* Event System */ +-typedef struct EVSYS_struct +-{ +- register8_t CH0MUX; /* Event Channel 0 Multiplexer */ +- register8_t CH1MUX; /* Event Channel 1 Multiplexer */ +- register8_t CH2MUX; /* Event Channel 2 Multiplexer */ +- register8_t CH3MUX; /* Event Channel 3 Multiplexer */ +- register8_t reserved_0x04; +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t CH0CTRL; /* Channel 0 Control Register */ +- register8_t CH1CTRL; /* Channel 1 Control Register */ +- register8_t CH2CTRL; /* Channel 2 Control Register */ +- register8_t CH3CTRL; /* Channel 3 Control Register */ +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t STROBE; /* Event Strobe */ +- register8_t DATA; /* Event Data */ +-} EVSYS_t; +- +-/* Quadrature Decoder Index Recognition Mode */ +-typedef enum EVSYS_QDIRM_enum +-{ +- EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ +- EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ +- EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ +- EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +-} EVSYS_QDIRM_t; +- +-/* Digital filter coefficient */ +-typedef enum EVSYS_DIGFILT_enum +-{ +- EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ +- EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ +- EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ +- EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ +- EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ +- EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ +- EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ +- EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +-} EVSYS_DIGFILT_t; +- +-/* Event Channel multiplexer input selection */ +-typedef enum EVSYS_CHMUX_enum +-{ +- EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ +- EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ +- EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ +- EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ +- EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ +- EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ +- EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ +- EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ +- EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ +- EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ +- EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ +- EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ +- EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ +- EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ +- EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ +- EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ +- EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ +- EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ +- EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ +- EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ +- EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ +- EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ +- EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ +- EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ +- EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ +- EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ +- EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ +- EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ +- EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ +- EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ +- EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ +- EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ +- EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ +- EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ +- EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ +- EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ +- EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ +- EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ +- EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ +- EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ +- EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ +- EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ +- EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ +- EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ +- EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ +- EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ +- EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ +- EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ +- EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ +- EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ +- EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ +- EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ +- EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ +- EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ +- EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ +- EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ +- EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ +- EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ +- EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ +- EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ +- EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ +- EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ +- EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ +- EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ +- EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ +- EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ +- EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ +- EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ +- EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ +- EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ +- EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ +- EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ +- EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ +- EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ +- EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ +- EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ +- EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ +- EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ +- EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ +- EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ +- EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ +- EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ +- EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ +- EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ +- EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ +- EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ +- EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ +- EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ +- EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ +- EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ +- EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ +- EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ +- EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ +- EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ +- EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ +- EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ +- EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ +- EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ +- EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ +- EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ +- EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +- EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ +- EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ +- EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ +- EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +-} EVSYS_CHMUX_t; +- +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Non-volatile Memory Controller */ +-typedef struct NVM_struct +-{ +- register8_t ADDR0; /* Address Register 0 */ +- register8_t ADDR1; /* Address Register 1 */ +- register8_t ADDR2; /* Address Register 2 */ +- register8_t reserved_0x03; +- register8_t DATA0; /* Data Register 0 */ +- register8_t DATA1; /* Data Register 1 */ +- register8_t DATA2; /* Data Register 2 */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t CMD; /* Command */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t INTCTRL; /* Interrupt Control */ +- register8_t reserved_0x0E; +- register8_t STATUS; /* Status */ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Lock Bits */ +-typedef struct NVM_LOCKBITS_struct +-{ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_LOCKBITS_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Fuses */ +-typedef struct NVM_FUSES_struct +-{ +- register8_t FUSEBYTE0; /* User ID */ +- register8_t FUSEBYTE1; /* Watchdog Configuration */ +- register8_t FUSEBYTE2; /* Reset Configuration */ +- register8_t reserved_0x03; +- register8_t FUSEBYTE4; /* Start-up Configuration */ +- register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +-} NVM_FUSES_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Production Signatures */ +-typedef struct NVM_PROD_SIGNATURES_struct +-{ +- register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ +- register8_t reserved_0x01; +- register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ +- register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ +- register8_t reserved_0x04; +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ +- register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ +- register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ +- register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ +- register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ +- register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t WAFNUM; /* Wafer Number */ +- register8_t reserved_0x11; +- register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ +- register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ +- register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ +- register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ +- register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ +- register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ +- register8_t reserved_0x26; +- register8_t reserved_0x27; +- register8_t reserved_0x28; +- register8_t reserved_0x29; +- register8_t reserved_0x2A; +- register8_t reserved_0x2B; +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ +- register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- register8_t reserved_0x36; +- register8_t reserved_0x37; +- register8_t reserved_0x38; +- register8_t reserved_0x39; +- register8_t reserved_0x3A; +- register8_t reserved_0x3B; +- register8_t reserved_0x3C; +- register8_t reserved_0x3D; +- register8_t reserved_0x3E; +-} NVM_PROD_SIGNATURES_t; +- +-/* NVM Command */ +-typedef enum NVM_CMD_enum +-{ +- NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ +- NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ +- NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ +- NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ +- NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ +- NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ +- NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ +- NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ +- NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ +- NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ +- NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ +- NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ +- NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ +- NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ +- NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ +- NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ +- NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ +- NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ +- NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ +- NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ +- NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ +- NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ +- NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ +- NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ +- NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ +- NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +-} NVM_CMD_t; +- +-/* SPM ready interrupt level */ +-typedef enum NVM_SPMLVL_enum +-{ +- NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ +- NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ +- NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +-} NVM_SPMLVL_t; +- +-/* EEPROM ready interrupt level */ +-typedef enum NVM_EELVL_enum +-{ +- NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ +- NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ +- NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +-} NVM_EELVL_t; +- +-/* Boot lock bits - boot setcion */ +-typedef enum NVM_BLBB_enum +-{ +- NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +- NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ +- NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ +- NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +-} NVM_BLBB_t; +- +-/* Boot lock bits - application section */ +-typedef enum NVM_BLBA_enum +-{ +- NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +- NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ +- NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ +- NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +-} NVM_BLBA_t; +- +-/* Boot lock bits - application table section */ +-typedef enum NVM_BLBAT_enum +-{ +- NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +- NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ +- NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ +- NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +-} NVM_BLBAT_t; +- +-/* Lock bits */ +-typedef enum NVM_LB_enum +-{ +- NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +- NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ +- NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +-} NVM_LB_t; +- +-/* Boot Loader Section Reset Vector */ +-typedef enum BOOTRST_enum +-{ +- BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ +- BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +-} BOOTRST_t; +- +-/* BOD operation */ +-typedef enum BOD_enum +-{ +- BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ +- BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ +- BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +-} BOD_t; +- +-/* Watchdog (Window) Timeout Period */ +-typedef enum WD_enum +-{ +- WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ +- WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ +- WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ +- WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ +- WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ +- WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ +- WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ +- WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ +- WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ +- WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ +- WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +-} WD_t; +- +-/* Start-up Time */ +-typedef enum SUT_enum +-{ +- SUT_0MS_gc = (0x03<<2), /* 0 ms */ +- SUT_4MS_gc = (0x01<<2), /* 4 ms */ +- SUT_64MS_gc = (0x00<<2), /* 64 ms */ +-} SUT_t; +- +-/* Brown Out Detection Voltage Level */ +-typedef enum BODLVL_enum +-{ +- BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ +- BODLVL_1V9_gc = (0x06<<0), /* 1.9 V */ +- BODLVL_2V1_gc = (0x05<<0), /* 2.1 V */ +- BODLVL_2V4_gc = (0x04<<0), /* 2.4 V */ +- BODLVL_2V6_gc = (0x03<<0), /* 2.6 V */ +- BODLVL_2V9_gc = (0x02<<0), /* 2.9 V */ +- BODLVL_3V2_gc = (0x01<<0), /* 3.2 V */ +-} BODLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-AC - Analog Comparator +--------------------------------------------------------------------------- +-*/ +- +-/* Analog Comparator */ +-typedef struct AC_struct +-{ +- register8_t AC0CTRL; /* Comparator 0 Control */ +- register8_t AC1CTRL; /* Comparator 1 Control */ +- register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ +- register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t WINCTRL; /* Window Mode Control */ +- register8_t STATUS; /* Status */ +-} AC_t; +- +-/* Interrupt mode */ +-typedef enum AC_INTMODE_enum +-{ +- AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ +- AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ +- AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +-} AC_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum AC_INTLVL_enum +-{ +- AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ +- AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ +- AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ +- AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +-} AC_INTLVL_t; +- +-/* Hysteresis mode selection */ +-typedef enum AC_HYSMODE_enum +-{ +- AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ +- AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ +- AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +-} AC_HYSMODE_t; +- +-/* Positive input multiplexer selection */ +-typedef enum AC_MUXPOS_enum +-{ +- AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ +- AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ +- AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ +- AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ +- AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ +- AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ +- AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +-} AC_MUXPOS_t; +- +-/* Negative input multiplexer selection */ +-typedef enum AC_MUXNEG_enum +-{ +- AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ +- AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ +- AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ +- AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ +- AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ +- AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ +- AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +-} AC_MUXNEG_t; +- +-/* Windows interrupt mode */ +-typedef enum AC_WINTMODE_enum +-{ +- AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ +- AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ +- AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ +- AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +-} AC_WINTMODE_t; +- +-/* Window interrupt level */ +-typedef enum AC_WINTLVL_enum +-{ +- AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ +- AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ +- AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +-} AC_WINTLVL_t; +- +-/* Window mode state */ +-typedef enum AC_WSTATE_enum +-{ +- AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ +- AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ +- AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +-} AC_WSTATE_t; +- +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* ADC Channel */ +-typedef struct ADC_CH_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t MUXCTRL; /* MUX Control */ +- register8_t INTCTRL; /* Channel Interrupt Control */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- _WORDREGISTER(RES); /* Channel Result */ +- register8_t reserved_0x6; +- register8_t reserved_0x7; +-} ADC_CH_t; +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Analog-to-Digital Converter */ +-typedef struct ADC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t REFCTRL; /* Reference Control */ +- register8_t EVCTRL; /* Event Control */ +- register8_t PRESCALER; /* Clock Prescaler */ +- register8_t reserved_0x05; +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t TEMP; /* ACD Temporary Register */ +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- _WORDREGISTER(CAL); /* Calibration Value */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- _WORDREGISTER(CH0RES); /* Channel 0 Result */ +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- _WORDREGISTER(CMP); /* Compare Value */ +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- ADC_CH_t CH0; /* ADC Channel 0 */ +-} ADC_t; +- +-/* Positive input multiplexer selection */ +-typedef enum ADC_CH_MUXPOS_enum +-{ +- ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ +- ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ +- ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ +- ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ +- ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ +- ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ +- ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ +- ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +-} ADC_CH_MUXPOS_t; +- +-/* Negative input multiplexer selection */ +-typedef enum ADC_CH_MUXNEG_enum +-{ +- ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ +- ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ +- ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ +- ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ +- ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ +- ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ +- ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ +- ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +-} ADC_CH_MUXNEG_t; +- +-/* Input mode */ +-typedef enum ADC_CH_INPUTMODE_enum +-{ +- ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ +- ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ +- ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ +- ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +-} ADC_CH_INPUTMODE_t; +- +-/* Gain factor */ +-typedef enum ADC_CH_GAIN_enum +-{ +- ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ +- ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ +- ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ +- ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ +- ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ +- ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ +- ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ +-} ADC_CH_GAIN_t; +- +-/* Conversion result resolution */ +-typedef enum ADC_RESOLUTION_enum +-{ +- ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ +- ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ +- ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +-} ADC_RESOLUTION_t; +- +-/* Voltage reference selection */ +-typedef enum ADC_REFSEL_enum +-{ +- ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ +- ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ +- ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ +- ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +-} ADC_REFSEL_t; +- +-/* Event channel input selection */ +-typedef enum ADC_EVSEL_enum +-{ +- ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ +- ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ +- ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ +- ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ +- ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ +- ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ +- ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ +- ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +-} ADC_EVSEL_t; +- +-/* Event action selection */ +-typedef enum ADC_EVACT_enum +-{ +- ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ +- ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ +-} ADC_EVACT_t; +- +-/* Interupt mode */ +-typedef enum ADC_CH_INTMODE_enum +-{ +- ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ +- ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ +- ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +-} ADC_CH_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum ADC_CH_INTLVL_enum +-{ +- ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ +- ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ +- ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +-} ADC_CH_INTLVL_t; +- +-/* Clock prescaler */ +-typedef enum ADC_PRESCALER_enum +-{ +- ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ +- ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ +- ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ +- ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ +- ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ +- ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ +- ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ +- ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +-} ADC_PRESCALER_t; +- +- +-/* +--------------------------------------------------------------------------- +-RTC - Real-Time Clounter +--------------------------------------------------------------------------- +-*/ +- +-/* Real-Time Counter */ +-typedef struct RTC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t TEMP; /* Temporary register */ +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- _WORDREGISTER(CNT); /* Count Register */ +- _WORDREGISTER(PER); /* Period Register */ +- _WORDREGISTER(COMP); /* Compare Register */ +-} RTC_t; +- +-/* Prescaler Factor */ +-typedef enum RTC_PRESCALER_enum +-{ +- RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ +- RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ +- RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ +- RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ +- RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ +- RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ +- RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ +- RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +-} RTC_PRESCALER_t; +- +-/* Compare Interrupt level */ +-typedef enum RTC_COMPINTLVL_enum +-{ +- RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} RTC_COMPINTLVL_t; +- +-/* Overflow Interrupt level */ +-typedef enum RTC_OVFINTLVL_enum +-{ +- RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} RTC_OVFINTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* EBI Chip Select Module */ +-typedef struct EBI_CS_struct +-{ +- register8_t CTRLA; /* Chip Select Control Register A */ +- register8_t CTRLB; /* Chip Select Control Register B */ +- _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +-} EBI_CS_t; +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* External Bus Interface */ +-typedef struct EBI_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t SDRAMCTRLA; /* SDRAM Control Register A */ +- register8_t reserved_0x02; +- register8_t reserved_0x03; +- _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ +- _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ +- register8_t SDRAMCTRLB; /* SDRAM Control Register B */ +- register8_t SDRAMCTRLC; /* SDRAM Control Register C */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- EBI_CS_t CS0; /* Chip Select 0 */ +- EBI_CS_t CS1; /* Chip Select 1 */ +- EBI_CS_t CS2; /* Chip Select 2 */ +- EBI_CS_t CS3; /* Chip Select 3 */ +-} EBI_t; +- +-/* Chip Select adress space */ +-typedef enum EBI_CS_ASIZE_enum +-{ +- EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ +- EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ +- EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ +- EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ +- EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ +- EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ +- EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ +- EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ +- EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ +- EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ +- EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ +- EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ +- EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ +- EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ +- EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ +- EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ +- EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +-} EBI_CS_ASIZE_t; +- +-/* */ +-typedef enum EBI_CS_SRWS_enum +-{ +- EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_CS_SRWS_t; +- +-/* Chip Select address mode */ +-typedef enum EBI_CS_MODE_enum +-{ +- EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ +- EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ +- EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ +- EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +-} EBI_CS_MODE_t; +- +-/* Chip Select SDRAM mode */ +-typedef enum EBI_CS_SDMODE_enum +-{ +- EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ +- EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +-} EBI_CS_SDMODE_t; +- +-/* */ +-typedef enum EBI_SDDATAW_enum +-{ +- EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ +- EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +-} EBI_SDDATAW_t; +- +-/* */ +-typedef enum EBI_LPCMODE_enum +-{ +- EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ +- EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +-} EBI_LPCMODE_t; +- +-/* */ +-typedef enum EBI_SRMODE_enum +-{ +- EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ +- EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ +- EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ +- EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +-} EBI_SRMODE_t; +- +-/* */ +-typedef enum EBI_IFMODE_enum +-{ +- EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ +- EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ +- EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ +- EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +-} EBI_IFMODE_t; +- +-/* */ +-typedef enum EBI_SDCOL_enum +-{ +- EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ +- EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ +- EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ +- EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +-} EBI_SDCOL_t; +- +-/* */ +-typedef enum EBI_MRDLY_enum +-{ +- EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_MRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCYCDLY_enum +-{ +- EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ROWCYCDLY_t; +- +-/* */ +-typedef enum EBI_RPDLY_enum +-{ +- EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_RPDLY_t; +- +-/* */ +-typedef enum EBI_WRDLY_enum +-{ +- EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_WRDLY_t; +- +-/* */ +-typedef enum EBI_ESRDLY_enum +-{ +- EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ESRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCOLDLY_enum +-{ +- EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_ROWCOLDLY_t; +- +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_MASTER_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t STATUS; /* Status Register */ +- register8_t BAUD; /* Baurd Rate Control Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +-} TWI_MASTER_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_SLAVE_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t STATUS; /* Status Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +- register8_t ADDRMASK; /* Address Mask Register */ +-} TWI_SLAVE_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Two-Wire Interface */ +-typedef struct TWI_struct +-{ +- register8_t CTRL; /* TWI Common Control Register */ +- TWI_MASTER_t MASTER; /* TWI master module */ +- TWI_SLAVE_t SLAVE; /* TWI slave module */ +-} TWI_t; +- +-/* Master Interrupt Level */ +-typedef enum TWI_MASTER_INTLVL_enum +-{ +- TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_MASTER_INTLVL_t; +- +-/* Inactive Timeout */ +-typedef enum TWI_MASTER_TIMEOUT_enum +-{ +- TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ +- TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ +- TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ +- TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +-} TWI_MASTER_TIMEOUT_t; +- +-/* Master Command */ +-typedef enum TWI_MASTER_CMD_enum +-{ +- TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ +- TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ +- TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +-} TWI_MASTER_CMD_t; +- +-/* Master Bus State */ +-typedef enum TWI_MASTER_BUSSTATE_enum +-{ +- TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ +- TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ +- TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ +- TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +-} TWI_MASTER_BUSSTATE_t; +- +-/* Slave Interrupt Level */ +-typedef enum TWI_SLAVE_INTLVL_enum +-{ +- TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_SLAVE_INTLVL_t; +- +-/* Slave Command */ +-typedef enum TWI_SLAVE_CMD_enum +-{ +- TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ +- TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +-} TWI_SLAVE_CMD_t; +- +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O port Configuration */ +-typedef struct PORTCFG_struct +-{ +- register8_t MPCMASK; /* Multi-pin Configuration Mask */ +- register8_t reserved_0x01; +- register8_t VPCTRLA; /* Virtual Port Control Register A */ +- register8_t VPCTRLB; /* Virtual Port Control Register B */ +- register8_t CLKEVOUT; /* Clock and Event Out Register */ +-} PORTCFG_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* Virtual Port */ +-typedef struct VPORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t OUT; /* I/O Port Output */ +- register8_t IN; /* I/O Port Input */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +-} VPORT_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O Ports */ +-typedef struct PORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t DIRSET; /* I/O Port Data Direction Set */ +- register8_t DIRCLR; /* I/O Port Data Direction Clear */ +- register8_t DIRTGL; /* I/O Port Data Direction Toggle */ +- register8_t OUT; /* I/O Port Output */ +- register8_t OUTSET; /* I/O Port Output Set */ +- register8_t OUTCLR; /* I/O Port Output Clear */ +- register8_t OUTTGL; /* I/O Port Output Toggle */ +- register8_t IN; /* I/O port Input */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INT0MASK; /* Port Interrupt 0 Mask */ +- register8_t INT1MASK; /* Port Interrupt 1 Mask */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t PIN0CTRL; /* Pin 0 Control Register */ +- register8_t PIN1CTRL; /* Pin 1 Control Register */ +- register8_t PIN2CTRL; /* Pin 2 Control Register */ +- register8_t PIN3CTRL; /* Pin 3 Control Register */ +- register8_t PIN4CTRL; /* Pin 4 Control Register */ +- register8_t PIN5CTRL; /* Pin 5 Control Register */ +- register8_t PIN6CTRL; /* Pin 6 Control Register */ +- register8_t PIN7CTRL; /* Pin 7 Control Register */ +-} PORT_t; +- +-/* Virtual Port 0 Mapping */ +-typedef enum PORTCFG_VP0MAP_enum +-{ +- PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP0MAP_t; +- +-/* Virtual Port 1 Mapping */ +-typedef enum PORTCFG_VP1MAP_enum +-{ +- PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP1MAP_t; +- +-/* Virtual Port 2 Mapping */ +-typedef enum PORTCFG_VP2MAP_enum +-{ +- PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP2MAP_t; +- +-/* Virtual Port 3 Mapping */ +-typedef enum PORTCFG_VP3MAP_enum +-{ +- PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP3MAP_t; +- +-/* Clock Output Port */ +-typedef enum PORTCFG_CLKOUT_enum +-{ +- PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ +- PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ +- PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ +- PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +-} PORTCFG_CLKOUT_t; +- +-/* Event Output Port */ +-typedef enum PORTCFG_EVOUT_enum +-{ +- PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ +- PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ +- PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ +- PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +-} PORTCFG_EVOUT_t; +- +-/* Port Interrupt 0 Level */ +-typedef enum PORT_INT0LVL_enum +-{ +- PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ +- PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ +- PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +-} PORT_INT0LVL_t; +- +-/* Port Interrupt 1 Level */ +-typedef enum PORT_INT1LVL_enum +-{ +- PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ +- PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ +- PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +-} PORT_INT1LVL_t; +- +-/* Output/Pull Configuration */ +-typedef enum PORT_OPC_enum +-{ +- PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ +- PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ +- PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ +- PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ +- PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ +- PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ +- PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ +- PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +-} PORT_OPC_t; +- +-/* Input/Sense Configuration */ +-typedef enum PORT_ISC_enum +-{ +- PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ +- PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ +- PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ +- PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ +- PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +-} PORT_ISC_t; +- +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 0 */ +-typedef struct TC0_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- _WORDREGISTER(CCC); /* Compare or Capture C */ +- _WORDREGISTER(CCD); /* Compare or Capture D */ +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +- _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ +- _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +-} TC0_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 1 */ +-typedef struct TC1_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t reserved_0x2E; +- register8_t reserved_0x2F; +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +-} TC1_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* Advanced Waveform Extension */ +-typedef struct AWEX_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t FDEMASK; /* Fault Detection Event Mask */ +- register8_t FDCTRL; /* Fault Detection Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x05; +- register8_t DTBOTH; /* Dead Time Both Sides */ +- register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ +- register8_t DTLS; /* Dead Time Low Side */ +- register8_t DTHS; /* Dead Time High Side */ +- register8_t DTLSBUF; /* Dead Time Low Side Buffer */ +- register8_t DTHSBUF; /* Dead Time High Side Buffer */ +- register8_t OUTOVEN; /* Output Override Enable */ +-} AWEX_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* High-Resolution Extension */ +-typedef struct HIRES_struct +-{ +- register8_t CTRLA; /* Control Register */ +-} HIRES_t; +- +-/* Clock Selection */ +-typedef enum TC_CLKSEL_enum +-{ +- TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ +- TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ +- TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ +- TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ +- TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ +- TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ +- TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ +- TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ +- TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_CLKSEL_t; +- +-/* Waveform Generation Mode */ +-typedef enum TC_WGMODE_enum +-{ +- TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ +- TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ +- TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ +- TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ +- TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ +- TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +-} TC_WGMODE_t; +- +-/* Event Action */ +-typedef enum TC_EVACT_enum +-{ +- TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ +- TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ +- TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ +- TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ +- TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ +- TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ +- TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +-} TC_EVACT_t; +- +-/* Event Selection */ +-typedef enum TC_EVSEL_enum +-{ +- TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_EVSEL_t; +- +-/* Error Interrupt Level */ +-typedef enum TC_ERRINTLVL_enum +-{ +- TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_ERRINTLVL_t; +- +-/* Overflow Interrupt Level */ +-typedef enum TC_OVFINTLVL_enum +-{ +- TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_OVFINTLVL_t; +- +-/* Compare or Capture D Interrupt Level */ +-typedef enum TC_CCDINTLVL_enum +-{ +- TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TC_CCDINTLVL_t; +- +-/* Compare or Capture C Interrupt Level */ +-typedef enum TC_CCCINTLVL_enum +-{ +- TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} TC_CCCINTLVL_t; +- +-/* Compare or Capture B Interrupt Level */ +-typedef enum TC_CCBINTLVL_enum +-{ +- TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_CCBINTLVL_t; +- +-/* Compare or Capture A Interrupt Level */ +-typedef enum TC_CCAINTLVL_enum +-{ +- TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_CCAINTLVL_t; +- +-/* Timer/Counter Command */ +-typedef enum TC_CMD_enum +-{ +- TC_CMD_NONE_gc = (0x00<<2), /* No Command */ +- TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ +- TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ +- TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +-} TC_CMD_t; +- +-/* Fault Detect Action */ +-typedef enum AWEX_FDACT_enum +-{ +- AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ +- AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ +- AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +-} AWEX_FDACT_t; +- +-/* High Resolution Enable */ +-typedef enum HIRES_HREN_enum +-{ +- HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ +- HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ +- HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ +- HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +-} HIRES_HREN_t; +- +- +-/* +--------------------------------------------------------------------------- +-USART - Universal Asynchronous Receiver-Transmitter +--------------------------------------------------------------------------- +-*/ +- +-/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +-typedef struct USART_struct +-{ +- register8_t DATA; /* Data Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x02; +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t BAUDCTRLA; /* Baud Rate Control Register A */ +- register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +-} USART_t; +- +-/* Receive Complete Interrupt level */ +-typedef enum USART_RXCINTLVL_enum +-{ +- USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} USART_RXCINTLVL_t; +- +-/* Transmit Complete Interrupt level */ +-typedef enum USART_TXCINTLVL_enum +-{ +- USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} USART_TXCINTLVL_t; +- +-/* Data Register Empty Interrupt level */ +-typedef enum USART_DREINTLVL_enum +-{ +- USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} USART_DREINTLVL_t; +- +-/* Character Size */ +-typedef enum USART_CHSIZE_enum +-{ +- USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ +- USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ +- USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ +- USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ +- USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +-} USART_CHSIZE_t; +- +-/* Communication Mode */ +-typedef enum USART_CMODE_enum +-{ +- USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ +- USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ +- USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ +- USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +-} USART_CMODE_t; +- +-/* Parity Mode */ +-typedef enum USART_PMODE_enum +-{ +- USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ +- USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ +- USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +-} USART_PMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-SPI - Serial Peripheral Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Serial Peripheral Interface */ +-typedef struct SPI_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t DATA; /* Data Register */ +-} SPI_t; +- +-/* SPI Mode */ +-typedef enum SPI_MODE_enum +-{ +- SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ +- SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ +- SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ +- SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +-} SPI_MODE_t; +- +-/* Prescaler setting */ +-typedef enum SPI_PRESCALER_enum +-{ +- SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ +- SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ +- SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ +- SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +-} SPI_PRESCALER_t; +- +-/* Interrupt level */ +-typedef enum SPI_INTLVL_enum +-{ +- SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} SPI_INTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-IRCOM - IR Communication Module +--------------------------------------------------------------------------- +-*/ +- +-/* IR Communication Module */ +-typedef struct IRCOM_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ +- register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +-} IRCOM_t; +- +-/* Event channel selection */ +-typedef enum IRDA_EVSEL_enum +-{ +- IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ +- IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ +- IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ +- IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +- IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ +- IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ +- IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ +- IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +-} IRDA_EVSEL_t; +- +- +- +-/* +-========================================================================== +-IO Module Instances. Mapped to memory. +-========================================================================== +-*/ +- +-#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +-#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +-#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +-#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +-#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +-#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +-#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +-#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +-#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +-#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +-#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +-#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +-#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +-#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +-#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +-#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +-#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +-#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +-#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +-#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +-#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +-#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +-#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +-#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +-#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +-#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +-#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ +-#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +-#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +-#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +-#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +-#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +-#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +-#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +-#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +-#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +-#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +-#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +-#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +-#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ +-#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ +-#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ +-#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ +- +- +-#endif /* !defined (__ASSEMBLER__) */ +- +- +-/* ========== Flattened fully qualified IO register names ========== */ +- +-/* GPIO - General Purpose IO Registers */ +-#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +-#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +-#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +-#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +-#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +-#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +-#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +-#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +-#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +-#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +-#define GPIO_GPIORA _SFR_MEM8(0x000A) +-#define GPIO_GPIORB _SFR_MEM8(0x000B) +-#define GPIO_GPIORC _SFR_MEM8(0x000C) +-#define GPIO_GPIORD _SFR_MEM8(0x000D) +-#define GPIO_GPIORE _SFR_MEM8(0x000E) +-#define GPIO_GPIORF _SFR_MEM8(0x000F) +- +-/* VPORT0 - Virtual Port 0 */ +-#define VPORT0_DIR _SFR_MEM8(0x0010) +-#define VPORT0_OUT _SFR_MEM8(0x0011) +-#define VPORT0_IN _SFR_MEM8(0x0012) +-#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) +- +-/* VPORT1 - Virtual Port 1 */ +-#define VPORT1_DIR _SFR_MEM8(0x0014) +-#define VPORT1_OUT _SFR_MEM8(0x0015) +-#define VPORT1_IN _SFR_MEM8(0x0016) +-#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) +- +-/* VPORT2 - Virtual Port 2 */ +-#define VPORT2_DIR _SFR_MEM8(0x0018) +-#define VPORT2_OUT _SFR_MEM8(0x0019) +-#define VPORT2_IN _SFR_MEM8(0x001A) +-#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) +- +-/* VPORT3 - Virtual Port 3 */ +-#define VPORT3_DIR _SFR_MEM8(0x001C) +-#define VPORT3_OUT _SFR_MEM8(0x001D) +-#define VPORT3_IN _SFR_MEM8(0x001E) +-#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) +- +-/* OCD - On-Chip Debug System */ +-#define OCD_OCDR0 _SFR_MEM8(0x002E) +-#define OCD_OCDR1 _SFR_MEM8(0x002F) +- +-/* CPU - CPU Registers */ +-#define CPU_CCP _SFR_MEM8(0x0034) +-#define CPU_RAMPD _SFR_MEM8(0x0038) +-#define CPU_RAMPX _SFR_MEM8(0x0039) +-#define CPU_RAMPY _SFR_MEM8(0x003A) +-#define CPU_RAMPZ _SFR_MEM8(0x003B) +-#define CPU_EIND _SFR_MEM8(0x003C) +-#define CPU_SPL _SFR_MEM8(0x003D) +-#define CPU_SPH _SFR_MEM8(0x003E) +-#define CPU_SREG _SFR_MEM8(0x003F) +- +-/* CLK - Clock System */ +-#define CLK_CTRL _SFR_MEM8(0x0040) +-#define CLK_PSCTRL _SFR_MEM8(0x0041) +-#define CLK_LOCK _SFR_MEM8(0x0042) +-#define CLK_RTCCTRL _SFR_MEM8(0x0043) +- +-/* SLEEP - Sleep Controller */ +-#define SLEEP_CTRL _SFR_MEM8(0x0048) +- +-/* OSC - Oscillator Control */ +-#define OSC_CTRL _SFR_MEM8(0x0050) +-#define OSC_STATUS _SFR_MEM8(0x0051) +-#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +-#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +-#define OSC_RC32KCAL _SFR_MEM8(0x0054) +-#define OSC_PLLCTRL _SFR_MEM8(0x0055) +-#define OSC_DFLLCTRL _SFR_MEM8(0x0056) +- +-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +-#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +-#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +-#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +-#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +-#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +-#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) +- +-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +-#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +-#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +-#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +-#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +-#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +-#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) +- +-/* RST - Reset Controller */ +-#define RST_STATUS _SFR_MEM8(0x0078) +-#define RST_CTRL _SFR_MEM8(0x0079) +- +-/* WDT - Watch-Dog Timer */ +-#define WDT_CTRL _SFR_MEM8(0x0080) +-#define WDT_WINCTRL _SFR_MEM8(0x0081) +-#define WDT_STATUS _SFR_MEM8(0x0082) +- +-/* MCU - MCU Control */ +-#define MCU_DEVID0 _SFR_MEM8(0x0090) +-#define MCU_DEVID1 _SFR_MEM8(0x0091) +-#define MCU_DEVID2 _SFR_MEM8(0x0092) +-#define MCU_REVID _SFR_MEM8(0x0093) +-#define MCU_JTAGUID _SFR_MEM8(0x0094) +-#define MCU_MCUCR _SFR_MEM8(0x0096) +-#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +-#define MCU_AWEXLOCK _SFR_MEM8(0x0099) +- +-/* PMIC - Programmable Interrupt Controller */ +-#define PMIC_STATUS _SFR_MEM8(0x00A0) +-#define PMIC_INTPRI _SFR_MEM8(0x00A1) +-#define PMIC_CTRL _SFR_MEM8(0x00A2) +- +-/* PORTCFG - Port Configuration */ +-#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +-#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +-#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +-#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +- +-/* EVSYS - Event System */ +-#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +-#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +-#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +-#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +-#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +-#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +-#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +-#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +-#define EVSYS_STROBE _SFR_MEM8(0x0190) +-#define EVSYS_DATA _SFR_MEM8(0x0191) +- +-/* NVM - Non Volatile Memory Controller */ +-#define NVM_ADDR0 _SFR_MEM8(0x01C0) +-#define NVM_ADDR1 _SFR_MEM8(0x01C1) +-#define NVM_ADDR2 _SFR_MEM8(0x01C2) +-#define NVM_DATA0 _SFR_MEM8(0x01C4) +-#define NVM_DATA1 _SFR_MEM8(0x01C5) +-#define NVM_DATA2 _SFR_MEM8(0x01C6) +-#define NVM_CMD _SFR_MEM8(0x01CA) +-#define NVM_CTRLA _SFR_MEM8(0x01CB) +-#define NVM_CTRLB _SFR_MEM8(0x01CC) +-#define NVM_INTCTRL _SFR_MEM8(0x01CD) +-#define NVM_STATUS _SFR_MEM8(0x01CF) +-#define NVM_LOCKBITS _SFR_MEM8(0x01D0) +- +-/* ADCA - Analog to Digital Converter A */ +-#define ADCA_CTRLA _SFR_MEM8(0x0200) +-#define ADCA_CTRLB _SFR_MEM8(0x0201) +-#define ADCA_REFCTRL _SFR_MEM8(0x0202) +-#define ADCA_EVCTRL _SFR_MEM8(0x0203) +-#define ADCA_PRESCALER _SFR_MEM8(0x0204) +-#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +-#define ADCA_TEMP _SFR_MEM8(0x0207) +-#define ADCA_CAL _SFR_MEM16(0x020C) +-#define ADCA_CH0RES _SFR_MEM16(0x0210) +-#define ADCA_CMP _SFR_MEM16(0x0218) +-#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +-#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +-#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +-#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +-#define ADCA_CH0_RES _SFR_MEM16(0x0224) +- +-/* ACA - Analog Comparator A */ +-#define ACA_AC0CTRL _SFR_MEM8(0x0380) +-#define ACA_AC1CTRL _SFR_MEM8(0x0381) +-#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +-#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +-#define ACA_CTRLA _SFR_MEM8(0x0384) +-#define ACA_CTRLB _SFR_MEM8(0x0385) +-#define ACA_WINCTRL _SFR_MEM8(0x0386) +-#define ACA_STATUS _SFR_MEM8(0x0387) +- +-/* RTC - Real-Time Counter */ +-#define RTC_CTRL _SFR_MEM8(0x0400) +-#define RTC_STATUS _SFR_MEM8(0x0401) +-#define RTC_INTCTRL _SFR_MEM8(0x0402) +-#define RTC_INTFLAGS _SFR_MEM8(0x0403) +-#define RTC_TEMP _SFR_MEM8(0x0404) +-#define RTC_CNT _SFR_MEM16(0x0408) +-#define RTC_PER _SFR_MEM16(0x040A) +-#define RTC_COMP _SFR_MEM16(0x040C) +- +-/* TWIC - Two-Wire Interface C */ +-#define TWIC_CTRL _SFR_MEM8(0x0480) +-#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +-#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +-#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +-#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +-#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +-#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +-#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +-#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +-#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +-#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +-#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +-#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +-#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) +- +-/* PORTA - Port A */ +-#define PORTA_DIR _SFR_MEM8(0x0600) +-#define PORTA_DIRSET _SFR_MEM8(0x0601) +-#define PORTA_DIRCLR _SFR_MEM8(0x0602) +-#define PORTA_DIRTGL _SFR_MEM8(0x0603) +-#define PORTA_OUT _SFR_MEM8(0x0604) +-#define PORTA_OUTSET _SFR_MEM8(0x0605) +-#define PORTA_OUTCLR _SFR_MEM8(0x0606) +-#define PORTA_OUTTGL _SFR_MEM8(0x0607) +-#define PORTA_IN _SFR_MEM8(0x0608) +-#define PORTA_INTCTRL _SFR_MEM8(0x0609) +-#define PORTA_INT0MASK _SFR_MEM8(0x060A) +-#define PORTA_INT1MASK _SFR_MEM8(0x060B) +-#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +-#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +-#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +-#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +-#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +-#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +-#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +-#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +-#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) +- +-/* PORTB - Port B */ +-#define PORTB_DIR _SFR_MEM8(0x0620) +-#define PORTB_DIRSET _SFR_MEM8(0x0621) +-#define PORTB_DIRCLR _SFR_MEM8(0x0622) +-#define PORTB_DIRTGL _SFR_MEM8(0x0623) +-#define PORTB_OUT _SFR_MEM8(0x0624) +-#define PORTB_OUTSET _SFR_MEM8(0x0625) +-#define PORTB_OUTCLR _SFR_MEM8(0x0626) +-#define PORTB_OUTTGL _SFR_MEM8(0x0627) +-#define PORTB_IN _SFR_MEM8(0x0628) +-#define PORTB_INTCTRL _SFR_MEM8(0x0629) +-#define PORTB_INT0MASK _SFR_MEM8(0x062A) +-#define PORTB_INT1MASK _SFR_MEM8(0x062B) +-#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +-#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +-#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +-#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +-#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +-#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +-#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +-#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +-#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) +- +-/* PORTC - Port C */ +-#define PORTC_DIR _SFR_MEM8(0x0640) +-#define PORTC_DIRSET _SFR_MEM8(0x0641) +-#define PORTC_DIRCLR _SFR_MEM8(0x0642) +-#define PORTC_DIRTGL _SFR_MEM8(0x0643) +-#define PORTC_OUT _SFR_MEM8(0x0644) +-#define PORTC_OUTSET _SFR_MEM8(0x0645) +-#define PORTC_OUTCLR _SFR_MEM8(0x0646) +-#define PORTC_OUTTGL _SFR_MEM8(0x0647) +-#define PORTC_IN _SFR_MEM8(0x0648) +-#define PORTC_INTCTRL _SFR_MEM8(0x0649) +-#define PORTC_INT0MASK _SFR_MEM8(0x064A) +-#define PORTC_INT1MASK _SFR_MEM8(0x064B) +-#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +-#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +-#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +-#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +-#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +-#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +-#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +-#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +-#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) +- +-/* PORTD - Port D */ +-#define PORTD_DIR _SFR_MEM8(0x0660) +-#define PORTD_DIRSET _SFR_MEM8(0x0661) +-#define PORTD_DIRCLR _SFR_MEM8(0x0662) +-#define PORTD_DIRTGL _SFR_MEM8(0x0663) +-#define PORTD_OUT _SFR_MEM8(0x0664) +-#define PORTD_OUTSET _SFR_MEM8(0x0665) +-#define PORTD_OUTCLR _SFR_MEM8(0x0666) +-#define PORTD_OUTTGL _SFR_MEM8(0x0667) +-#define PORTD_IN _SFR_MEM8(0x0668) +-#define PORTD_INTCTRL _SFR_MEM8(0x0669) +-#define PORTD_INT0MASK _SFR_MEM8(0x066A) +-#define PORTD_INT1MASK _SFR_MEM8(0x066B) +-#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +-#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +-#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +-#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +-#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +-#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +-#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +-#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +-#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) +- +-/* PORTE - Port E */ +-#define PORTE_DIR _SFR_MEM8(0x0680) +-#define PORTE_DIRSET _SFR_MEM8(0x0681) +-#define PORTE_DIRCLR _SFR_MEM8(0x0682) +-#define PORTE_DIRTGL _SFR_MEM8(0x0683) +-#define PORTE_OUT _SFR_MEM8(0x0684) +-#define PORTE_OUTSET _SFR_MEM8(0x0685) +-#define PORTE_OUTCLR _SFR_MEM8(0x0686) +-#define PORTE_OUTTGL _SFR_MEM8(0x0687) +-#define PORTE_IN _SFR_MEM8(0x0688) +-#define PORTE_INTCTRL _SFR_MEM8(0x0689) +-#define PORTE_INT0MASK _SFR_MEM8(0x068A) +-#define PORTE_INT1MASK _SFR_MEM8(0x068B) +-#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +-#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +-#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +-#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +-#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +-#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +-#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +-#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +-#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) +- +-/* PORTF - Port F */ +-#define PORTF_DIR _SFR_MEM8(0x06A0) +-#define PORTF_DIRSET _SFR_MEM8(0x06A1) +-#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +-#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +-#define PORTF_OUT _SFR_MEM8(0x06A4) +-#define PORTF_OUTSET _SFR_MEM8(0x06A5) +-#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +-#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +-#define PORTF_IN _SFR_MEM8(0x06A8) +-#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +-#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +-#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +-#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +-#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +-#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +-#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +-#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +-#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +-#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +-#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +-#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) +- +-/* PORTR - Port R */ +-#define PORTR_DIR _SFR_MEM8(0x07E0) +-#define PORTR_DIRSET _SFR_MEM8(0x07E1) +-#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +-#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +-#define PORTR_OUT _SFR_MEM8(0x07E4) +-#define PORTR_OUTSET _SFR_MEM8(0x07E5) +-#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +-#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +-#define PORTR_IN _SFR_MEM8(0x07E8) +-#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +-#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +-#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +-#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +-#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +-#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +-#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +-#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +-#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +-#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +-#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +-#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) +- +-/* TCC0 - Timer/Counter C0 */ +-#define TCC0_CTRLA _SFR_MEM8(0x0800) +-#define TCC0_CTRLB _SFR_MEM8(0x0801) +-#define TCC0_CTRLC _SFR_MEM8(0x0802) +-#define TCC0_CTRLD _SFR_MEM8(0x0803) +-#define TCC0_CTRLE _SFR_MEM8(0x0804) +-#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +-#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +-#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +-#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +-#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +-#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +-#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +-#define TCC0_TEMP _SFR_MEM8(0x080F) +-#define TCC0_CNT _SFR_MEM16(0x0820) +-#define TCC0_PER _SFR_MEM16(0x0826) +-#define TCC0_CCA _SFR_MEM16(0x0828) +-#define TCC0_CCB _SFR_MEM16(0x082A) +-#define TCC0_CCC _SFR_MEM16(0x082C) +-#define TCC0_CCD _SFR_MEM16(0x082E) +-#define TCC0_PERBUF _SFR_MEM16(0x0836) +-#define TCC0_CCABUF _SFR_MEM16(0x0838) +-#define TCC0_CCBBUF _SFR_MEM16(0x083A) +-#define TCC0_CCCBUF _SFR_MEM16(0x083C) +-#define TCC0_CCDBUF _SFR_MEM16(0x083E) +- +-/* TCC1 - Timer/Counter C1 */ +-#define TCC1_CTRLA _SFR_MEM8(0x0840) +-#define TCC1_CTRLB _SFR_MEM8(0x0841) +-#define TCC1_CTRLC _SFR_MEM8(0x0842) +-#define TCC1_CTRLD _SFR_MEM8(0x0843) +-#define TCC1_CTRLE _SFR_MEM8(0x0844) +-#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +-#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +-#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +-#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +-#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +-#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +-#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +-#define TCC1_TEMP _SFR_MEM8(0x084F) +-#define TCC1_CNT _SFR_MEM16(0x0860) +-#define TCC1_PER _SFR_MEM16(0x0866) +-#define TCC1_CCA _SFR_MEM16(0x0868) +-#define TCC1_CCB _SFR_MEM16(0x086A) +-#define TCC1_PERBUF _SFR_MEM16(0x0876) +-#define TCC1_CCABUF _SFR_MEM16(0x0878) +-#define TCC1_CCBBUF _SFR_MEM16(0x087A) +- +-/* AWEXC - Advanced Waveform Extension C */ +-#define AWEXC_CTRL _SFR_MEM8(0x0880) +-#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +-#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +-#define AWEXC_STATUS _SFR_MEM8(0x0884) +-#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +-#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +-#define AWEXC_DTLS _SFR_MEM8(0x0888) +-#define AWEXC_DTHS _SFR_MEM8(0x0889) +-#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +-#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +-#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) +- +-/* HIRESC - High-Resolution Extension C */ +-#define HIRESC_CTRLA _SFR_MEM8(0x0890) +- +-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +-#define USARTC0_DATA _SFR_MEM8(0x08A0) +-#define USARTC0_STATUS _SFR_MEM8(0x08A1) +-#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +-#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +-#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +-#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +-#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) +- +-/* SPIC - Serial Peripheral Interface C */ +-#define SPIC_CTRL _SFR_MEM8(0x08C0) +-#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +-#define SPIC_STATUS _SFR_MEM8(0x08C2) +-#define SPIC_DATA _SFR_MEM8(0x08C3) +- +-/* IRCOM - IR Communication Module */ +-#define IRCOM_CTRL _SFR_MEM8(0x08F8) +-#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +-#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) +- +-/* TCD0 - Timer/Counter D0 */ +-#define TCD0_CTRLA _SFR_MEM8(0x0900) +-#define TCD0_CTRLB _SFR_MEM8(0x0901) +-#define TCD0_CTRLC _SFR_MEM8(0x0902) +-#define TCD0_CTRLD _SFR_MEM8(0x0903) +-#define TCD0_CTRLE _SFR_MEM8(0x0904) +-#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +-#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +-#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +-#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +-#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +-#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +-#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +-#define TCD0_TEMP _SFR_MEM8(0x090F) +-#define TCD0_CNT _SFR_MEM16(0x0920) +-#define TCD0_PER _SFR_MEM16(0x0926) +-#define TCD0_CCA _SFR_MEM16(0x0928) +-#define TCD0_CCB _SFR_MEM16(0x092A) +-#define TCD0_CCC _SFR_MEM16(0x092C) +-#define TCD0_CCD _SFR_MEM16(0x092E) +-#define TCD0_PERBUF _SFR_MEM16(0x0936) +-#define TCD0_CCABUF _SFR_MEM16(0x0938) +-#define TCD0_CCBBUF _SFR_MEM16(0x093A) +-#define TCD0_CCCBUF _SFR_MEM16(0x093C) +-#define TCD0_CCDBUF _SFR_MEM16(0x093E) +- +-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +-#define USARTD0_DATA _SFR_MEM8(0x09A0) +-#define USARTD0_STATUS _SFR_MEM8(0x09A1) +-#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +-#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +-#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +-#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +-#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) +- +-/* SPID - Serial Peripheral Interface D */ +-#define SPID_CTRL _SFR_MEM8(0x09C0) +-#define SPID_INTCTRL _SFR_MEM8(0x09C1) +-#define SPID_STATUS _SFR_MEM8(0x09C2) +-#define SPID_DATA _SFR_MEM8(0x09C3) +- +-/* TCE0 - Timer/Counter E0 */ +-#define TCE0_CTRLA _SFR_MEM8(0x0A00) +-#define TCE0_CTRLB _SFR_MEM8(0x0A01) +-#define TCE0_CTRLC _SFR_MEM8(0x0A02) +-#define TCE0_CTRLD _SFR_MEM8(0x0A03) +-#define TCE0_CTRLE _SFR_MEM8(0x0A04) +-#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +-#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +-#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +-#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +-#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +-#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +-#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +-#define TCE0_TEMP _SFR_MEM8(0x0A0F) +-#define TCE0_CNT _SFR_MEM16(0x0A20) +-#define TCE0_PER _SFR_MEM16(0x0A26) +-#define TCE0_CCA _SFR_MEM16(0x0A28) +-#define TCE0_CCB _SFR_MEM16(0x0A2A) +-#define TCE0_CCC _SFR_MEM16(0x0A2C) +-#define TCE0_CCD _SFR_MEM16(0x0A2E) +-#define TCE0_PERBUF _SFR_MEM16(0x0A36) +-#define TCE0_CCABUF _SFR_MEM16(0x0A38) +-#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +-#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +-#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) +- +-/* AWEXE - Advanced Waveform Extension E */ +-#define AWEXE_CTRL _SFR_MEM8(0x0A80) +-#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +-#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +-#define AWEXE_STATUS _SFR_MEM8(0x0A84) +-#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +-#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +-#define AWEXE_DTLS _SFR_MEM8(0x0A88) +-#define AWEXE_DTHS _SFR_MEM8(0x0A89) +-#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +-#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +-#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) +- +-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +-#define USARTE0_DATA _SFR_MEM8(0x0AA0) +-#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +-#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +-#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +-#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +-#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +-#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) +- +-/* SPIE - Serial Peripheral Interface E */ +-#define SPIE_CTRL _SFR_MEM8(0x0AC0) +-#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +-#define SPIE_STATUS _SFR_MEM8(0x0AC2) +-#define SPIE_DATA _SFR_MEM8(0x0AC3) +- +-/* TCF0 - Timer/Counter F0 */ +-#define TCF0_CTRLA _SFR_MEM8(0x0B00) +-#define TCF0_CTRLB _SFR_MEM8(0x0B01) +-#define TCF0_CTRLC _SFR_MEM8(0x0B02) +-#define TCF0_CTRLD _SFR_MEM8(0x0B03) +-#define TCF0_CTRLE _SFR_MEM8(0x0B04) +-#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +-#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +-#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +-#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +-#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +-#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +-#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +-#define TCF0_TEMP _SFR_MEM8(0x0B0F) +-#define TCF0_CNT _SFR_MEM16(0x0B20) +-#define TCF0_PER _SFR_MEM16(0x0B26) +-#define TCF0_CCA _SFR_MEM16(0x0B28) +-#define TCF0_CCB _SFR_MEM16(0x0B2A) +-#define TCF0_CCC _SFR_MEM16(0x0B2C) +-#define TCF0_CCD _SFR_MEM16(0x0B2E) +-#define TCF0_PERBUF _SFR_MEM16(0x0B36) +-#define TCF0_CCABUF _SFR_MEM16(0x0B38) +-#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +-#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +-#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) +- +- +- +-/*================== Bitfield Definitions ================== */ +- +-/* XOCD - On-Chip Debug System */ +-/* OCD.OCDR1 bit masks and bit positions */ +-#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +-#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ +- +- +-/* CPU - CPU */ +-/* CPU.CCP bit masks and bit positions */ +-#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +-#define CPU_CCP_gp 0 /* CCP signature group position. */ +-#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +-#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +-#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +-#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +-#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +-#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +-#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +-#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +-#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +-#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +-#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +-#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +-#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +-#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +-#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +-#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ +- +- +-/* CPU.SREG bit masks and bit positions */ +-#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +-#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ +- +-#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +-#define CPU_T_bp 6 /* Transfer Bit bit position. */ +- +-#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +-#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +- +-#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +-#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +- +-#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +-#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +- +-#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +-#define CPU_N_bp 2 /* Negative Flag bit position. */ +- +-#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +-#define CPU_Z_bp 1 /* Zero Flag bit position. */ +- +-#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +-#define CPU_C_bp 0 /* Carry Flag bit position. */ +- +- +-/* CLK - Clock System */ +-/* CLK.CTRL bit masks and bit positions */ +-#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +-#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +-#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +-#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +-#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +-#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +-#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +-#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ +- +- +-/* CLK.PSCTRL bit masks and bit positions */ +-#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +-#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +-#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +-#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +-#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +-#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +-#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +-#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +-#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +-#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +-#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +-#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ +- +-#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +-#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +-#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +-#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +-#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +-#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ +- +- +-/* CLK.LOCK bit masks and bit positions */ +-#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +-#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ +- +- +-/* CLK.RTCCTRL bit masks and bit positions */ +-#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +-#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +-#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +-#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +-#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +-#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +-#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +-#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ +- +-#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +-#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ +- +- +-/* SLEEP - Sleep Controller */ +-/* SLEEP.CTRL bit masks and bit positions */ +-#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +-#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +-#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +-#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +-#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +-#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +-#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +-#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ +- +-#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +-#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ +- +- +-/* OSC - Oscillator */ +-/* OSC.CTRL bit masks and bit positions */ +-#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +-#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ +- +-#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +-#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ +- +-#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ +- +- +-/* OSC.STATUS bit masks and bit positions */ +-#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +-#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ +- +-#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +-#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ +- +-#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ +- +- +-/* OSC.XOSCCTRL bit masks and bit positions */ +-#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +-#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +-#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +-#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +-#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +-#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ +- +-#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +-#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ +- +-#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +-#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +-#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +-#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +-#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +-#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +-#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +-#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +-#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +-#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +- +- +-/* OSC.XOSCFAIL bit masks and bit positions */ +-#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +-#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ +- +-#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +-#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ +- +- +-/* OSC.PLLCTRL bit masks and bit positions */ +-#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +-#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +-#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +-#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +-#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +-#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ +- +-#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +-#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +-#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +-#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +-#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +-#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +-#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +-#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +-#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +-#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +-#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +-#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ +- +- +-/* OSC.DFLLCTRL bit masks and bit positions */ +-#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +-#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ +- +-#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +-#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ +- +- +-/* DFLL - DFLL */ +-/* DFLL.CTRL bit masks and bit positions */ +-#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +-#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ +- +- +-/* DFLL.CALA bit masks and bit positions */ +-#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +-#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +-#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +-#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +-#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +-#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +-#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +-#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +-#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +-#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +-#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +-#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +-#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +-#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +-#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +-#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ +- +- +-/* DFLL.CALB bit masks and bit positions */ +-#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +-#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +-#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +-#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +-#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +-#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +-#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +-#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +-#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +-#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +-#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +-#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +-#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +-#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ +- +- +-/* RST - Reset */ +-/* RST.STATUS bit masks and bit positions */ +-#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +-#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ +- +-#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +-#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ +- +-#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +-#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ +- +-#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +-#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ +- +-#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +-#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ +- +-#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +-#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ +- +-#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +-#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ +- +- +-/* RST.CTRL bit masks and bit positions */ +-#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +-#define RST_SWRST_bp 0 /* Software Reset bit position. */ +- +- +-/* WDT - Watch-Dog Timer */ +-/* WDT.CTRL bit masks and bit positions */ +-#define WDT_PER_gm 0x3C /* Period group mask. */ +-#define WDT_PER_gp 2 /* Period group position. */ +-#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +-#define WDT_PER0_bp 2 /* Period bit 0 position. */ +-#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +-#define WDT_PER1_bp 3 /* Period bit 1 position. */ +-#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +-#define WDT_PER2_bp 4 /* Period bit 2 position. */ +-#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +-#define WDT_PER3_bp 5 /* Period bit 3 position. */ +- +-#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +-#define WDT_ENABLE_bp 1 /* Enable bit position. */ +- +-#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +-#define WDT_CEN_bp 0 /* Change Enable bit position. */ +- +- +-/* WDT.WINCTRL bit masks and bit positions */ +-#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +-#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +-#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +-#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +-#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +-#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +-#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +-#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +-#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +-#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ +- +-#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +-#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ +- +-#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +-#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ +- +- +-/* WDT.STATUS bit masks and bit positions */ +-#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +-#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +- +- +-/* MCU - MCU Control */ +-/* MCU.MCUCR bit masks and bit positions */ +-#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +-#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ +- +- +-/* MCU.EVSYSLOCK bit masks and bit positions */ +-#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +-#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ +- +-#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +-#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ +- +- +-/* MCU.AWEXLOCK bit masks and bit positions */ +-#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +-#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ +- +-#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +-#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ +- +- +-/* PMIC - Programmable Multi-level Interrupt Controller */ +-/* PMIC.STATUS bit masks and bit positions */ +-#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +-#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ +- +-#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +-#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ +- +-#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +-#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ +- +-#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +-#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ +- +- +-/* PMIC.CTRL bit masks and bit positions */ +-#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +-#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ +- +-#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +-#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ +- +-#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +-#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ +- +-#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +-#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ +- +-#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +-#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ +- +- +-/* EVSYS - Event System */ +-/* EVSYS.CH0MUX bit masks and bit positions */ +-#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +-#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +-#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +-#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +-#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +-#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +-#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +-#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +-#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +-#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +-#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +-#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +-#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +-#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +-#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +-#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +-#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +-#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ +- +- +-/* EVSYS.CH1MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH2MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH3MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH0CTRL bit masks and bit positions */ +-#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +-#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +-#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +-#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +-#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +-#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ +- +-#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +-#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ +- +-#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +-#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ +- +-#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +-#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +-#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +-#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +-#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +-#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +-#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +-#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ +- +- +-/* EVSYS.CH1CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH2CTRL bit masks and bit positions */ +-/* EVSYS_QDIRM_gm Predefined. */ +-/* EVSYS_QDIRM_gp Predefined. */ +-/* EVSYS_QDIRM0_bm Predefined. */ +-/* EVSYS_QDIRM0_bp Predefined. */ +-/* EVSYS_QDIRM1_bm Predefined. */ +-/* EVSYS_QDIRM1_bp Predefined. */ +- +-/* EVSYS_QDIEN_bm Predefined. */ +-/* EVSYS_QDIEN_bp Predefined. */ +- +-/* EVSYS_QDEN_bm Predefined. */ +-/* EVSYS_QDEN_bp Predefined. */ +- +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH3CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* NVM - Non Volatile Memory Controller */ +-/* NVM.CMD bit masks and bit positions */ +-#define NVM_CMD_gm 0xFF /* Command group mask. */ +-#define NVM_CMD_gp 0 /* Command group position. */ +-#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +-#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +-#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +-#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +-#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +-#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +-#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +-#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +-#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +-#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +-#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +-#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +-#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +-#define NVM_CMD7_bp 7 /* Command bit 7 position. */ +- +- +-/* NVM.CTRLA bit masks and bit positions */ +-#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +-#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ +- +- +-/* NVM.CTRLB bit masks and bit positions */ +-#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +-#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ +- +-#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +-#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ +- +-#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +-#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ +- +-#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +-#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ +- +- +-/* NVM.INTCTRL bit masks and bit positions */ +-#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +-#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +-#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +-#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +-#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +-#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ +- +-#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +-#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +-#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +-#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +-#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +-#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ +- +- +-/* NVM.STATUS bit masks and bit positions */ +-#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +-#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ +- +-#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +-#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ +- +-#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +-#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ +- +-#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +-#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ +- +- +-/* NVM.LOCKBITS bit masks and bit positions */ +-#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +-#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +-#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ +-#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ +-#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ +-#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ +-#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ +-#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ +-#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ +-#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ +-#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ +-#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ +-#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ +-#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ +-#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ +-#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ +-#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ +-#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ +-#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ +-#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +-#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +-#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +-#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ +- +-#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +-#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +-#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +-#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +-#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ +- +-#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +-#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ +- +-#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +-#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +-#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +-#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +-#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +-#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +-#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ +-#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ +- +-#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +-#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +-#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +-#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +-#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +-#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ +- +-#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +-#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ +- +- +-/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +-#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +-#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +-#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +-#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +-#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +-#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ +- +-#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +-#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ +- +-#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +-#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +-#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +-#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +-#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +-#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +-#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +-#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +- +- +-/* AC - Analog Comparator */ +-/* AC.AC0CTRL bit masks and bit positions */ +-#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +-#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +-#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +-#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +-#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +-#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ +- +-#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +-#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +-#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +-#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +-#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +-#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ +- +-#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +-#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ +- +-#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +-#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +-#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +-#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +-#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +-#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +- +-#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define AC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* AC.AC1CTRL bit masks and bit positions */ +-/* AC_INTMODE_gm Predefined. */ +-/* AC_INTMODE_gp Predefined. */ +-/* AC_INTMODE0_bm Predefined. */ +-/* AC_INTMODE0_bp Predefined. */ +-/* AC_INTMODE1_bm Predefined. */ +-/* AC_INTMODE1_bp Predefined. */ +- +-/* AC_INTLVL_gm Predefined. */ +-/* AC_INTLVL_gp Predefined. */ +-/* AC_INTLVL0_bm Predefined. */ +-/* AC_INTLVL0_bp Predefined. */ +-/* AC_INTLVL1_bm Predefined. */ +-/* AC_INTLVL1_bp Predefined. */ +- +-/* AC_HSMODE_bm Predefined. */ +-/* AC_HSMODE_bp Predefined. */ +- +-/* AC_HYSMODE_gm Predefined. */ +-/* AC_HYSMODE_gp Predefined. */ +-/* AC_HYSMODE0_bm Predefined. */ +-/* AC_HYSMODE0_bp Predefined. */ +-/* AC_HYSMODE1_bm Predefined. */ +-/* AC_HYSMODE1_bp Predefined. */ +- +-/* AC_ENABLE_bm Predefined. */ +-/* AC_ENABLE_bp Predefined. */ +- +- +-/* AC.AC0MUXCTRL bit masks and bit positions */ +-#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +-#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +-#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +-#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +-#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +-#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +-#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +-#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ +- +-#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +-#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +-#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +-#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +-#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +-#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +-#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +-#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ +- +- +-/* AC.AC1MUXCTRL bit masks and bit positions */ +-/* AC_MUXPOS_gm Predefined. */ +-/* AC_MUXPOS_gp Predefined. */ +-/* AC_MUXPOS0_bm Predefined. */ +-/* AC_MUXPOS0_bp Predefined. */ +-/* AC_MUXPOS1_bm Predefined. */ +-/* AC_MUXPOS1_bp Predefined. */ +-/* AC_MUXPOS2_bm Predefined. */ +-/* AC_MUXPOS2_bp Predefined. */ +- +-/* AC_MUXNEG_gm Predefined. */ +-/* AC_MUXNEG_gp Predefined. */ +-/* AC_MUXNEG0_bm Predefined. */ +-/* AC_MUXNEG0_bp Predefined. */ +-/* AC_MUXNEG1_bm Predefined. */ +-/* AC_MUXNEG1_bp Predefined. */ +-/* AC_MUXNEG2_bm Predefined. */ +-/* AC_MUXNEG2_bp Predefined. */ +- +- +-/* AC.CTRLA bit masks and bit positions */ +-#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +-#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ +- +- +-/* AC.CTRLB bit masks and bit positions */ +-#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +-#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +-#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +-#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +-#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +-#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +-#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +-#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +-#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +-#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +-#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +-#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +-#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +-#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ +- +- +-/* AC.WINCTRL bit masks and bit positions */ +-#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +-#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ +- +-#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +-#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +-#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +-#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +-#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +-#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ +- +-#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +-#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +-#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +-#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +-#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +-#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ +- +- +-/* AC.STATUS bit masks and bit positions */ +-#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +-#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +-#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +-#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +-#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +-#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ +- +-#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +-#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ +- +-#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +-#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ +- +-#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +-#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ +- +-#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +-#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ +- +-#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +-#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ +- +- +-/* ADC - Analog/Digital Converter */ +-/* ADC_CH.CTRL bit masks and bit positions */ +-#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +-#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ +- +-#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +-#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +-#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +-#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +-#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +-#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +-#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +-#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ +- +-#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +-#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +-#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +-#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +-#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +-#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ +- +- +-/* ADC_CH.MUXCTRL bit masks and bit positions */ +-#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +-#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +-#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +-#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +-#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +-#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +-#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +-#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +-#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +-#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ +- +-#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +-#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +-#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +-#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +-#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +-#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ +- +- +-/* ADC_CH.INTCTRL bit masks and bit positions */ +-#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +-#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +-#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +-#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +-#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +-#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ +- +-#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +-#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +-#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +-#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +-#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +-#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ +- +- +-/* ADC_CH.INTFLAGS bit masks and bit positions */ +-#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +-#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ +- +- +-/* ADC.CTRLA bit masks and bit positions */ +-#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +-#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ +- +-#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +-#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ +- +-#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +-#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ +- +- +-/* ADC.CTRLB bit masks and bit positions */ +-#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +-#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ +- +-#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +-#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ +- +-#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +-#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +-#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +-#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +-#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +-#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ +- +- +-/* ADC.REFCTRL bit masks and bit positions */ +-#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +-#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +-#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +-#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +-#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +-#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +-#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +-#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ +- +-#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +-#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ +- +-#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +-#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ +- +- +-/* ADC.EVCTRL bit masks and bit positions */ +-#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +-#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +-#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +-#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +-#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +-#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +-#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +-#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ +- +-#define ADC_EVACT_bm 0x01 /* Event Action Select bit mask. */ +-#define ADC_EVACT_bp 0 /* Event Action Select bit position. */ +- +- +-/* ADC.PRESCALER bit masks and bit positions */ +-#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +-#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +-#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +-#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +-#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +-#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +-#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +-#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ +- +- +-/* ADC.INTFLAGS bit masks and bit positions */ +-#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +-#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ +- +- +-/* RTC - Real-Time Clounter */ +-/* RTC.CTRL bit masks and bit positions */ +-#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +-#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +-#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +-#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +-#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +-#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +-#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +-#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ +- +- +-/* RTC.STATUS bit masks and bit positions */ +-#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +-#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ +- +- +-/* RTC.INTCTRL bit masks and bit positions */ +-#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +-#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +-#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +-#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +-#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +-#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ +- +-#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +-#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +-#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +-#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +-#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +-#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ +- +- +-/* RTC.INTFLAGS bit masks and bit positions */ +-#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +-#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ +- +-#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* EBI - External Bus Interface */ +-/* EBI_CS.CTRLA bit masks and bit positions */ +-#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +-#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +-#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +-#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +-#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +-#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +-#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +-#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +-#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +-#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +-#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +-#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ +- +-#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +-#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +-#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +-#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +-#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +-#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ +- +- +-/* EBI_CS.CTRLB bit masks and bit positions */ +-#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +-#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +-#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +-#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +-#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +-#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +-#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +-#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ +- +-#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +-#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ +- +-#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +-#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ +- +-#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +-#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +-#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +-#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +-#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +-#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ +- +- +-/* EBI.CTRL bit masks and bit positions */ +-#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +-#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +-#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +-#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +-#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +-#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ +- +-#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +-#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +-#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +-#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +-#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +-#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ +- +-#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +-#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +-#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +-#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +-#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +-#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ +- +-#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +-#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +-#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +-#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +-#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +-#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLA bit masks and bit positions */ +-#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +-#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ +- +-#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +-#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ +- +-#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +-#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +-#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +-#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +-#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +-#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLB bit masks and bit positions */ +-#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +-#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +-#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +-#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +-#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +-#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ +- +-#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +-#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +-#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +-#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +-#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +-#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +-#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +-#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ +- +-#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +-#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +-#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +-#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +-#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +-#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +-#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +-#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ +- +- +-/* EBI.SDRAMCTRLC bit masks and bit positions */ +-#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +-#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +-#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +-#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +-#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +-#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ +- +-#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +-#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +-#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +-#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +-#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +-#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +-#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +-#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ +- +-#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +-#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +-#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +-#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +-#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +-#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +-#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +-#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ +- +- +-/* TWI - Two-Wire Interface */ +-/* TWI_MASTER.CTRLA bit masks and bit positions */ +-#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +-#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ +- +-#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +-#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ +- +-#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +-#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ +- +- +-/* TWI_MASTER.CTRLB bit masks and bit positions */ +-#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +-#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +-#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +-#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +-#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +-#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +- +-#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +-#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ +- +-#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_MASTER.CTRLC bit masks and bit positions */ +-#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +-#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_MASTER.STATUS bit masks and bit positions */ +-#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +-#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ +- +-#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +-#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ +- +-#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +-#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +- +-#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +-#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +-#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +-#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +-#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +-#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +- +- +-/* TWI_SLAVE.CTRLA bit masks and bit positions */ +-#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +-#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +-#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ +- +-#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +-#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ +- +-#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_SLAVE.CTRLB bit masks and bit positions */ +-#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +-#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_SLAVE.STATUS bit masks and bit positions */ +-#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +-#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +-#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +-#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ +- +-#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +-#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ +- +-#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +-#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ +- +- +-/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +-#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +-#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +-#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +-#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +-#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +-#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +-#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +-#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +-#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +-#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +-#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +-#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +-#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +-#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +-#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +-#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ +- +-#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +-#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ +- +- +-/* TWI.CTRL bit masks and bit positions */ +-#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +-#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ +- +-#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +-#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ +- +- +-/* PORT - Port Configuration */ +-/* PORTCFG.VPCTRLA bit masks and bit positions */ +-#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +-#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +-#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +-#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +-#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +-#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +-#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +-#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +-#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +-#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ +- +-#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +-#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +-#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +-#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +-#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +-#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +-#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +-#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +-#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +-#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ +- +- +-/* PORTCFG.VPCTRLB bit masks and bit positions */ +-#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +-#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +-#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +-#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +-#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +-#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +-#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +-#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +-#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +-#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ +- +-#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +-#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +-#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +-#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +-#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +-#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +-#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +-#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +-#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +-#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ +- +- +-/* PORTCFG.CLKEVOUT bit masks and bit positions */ +-#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +-#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +-#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +-#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +-#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +-#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ +- +-#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +-#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +-#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +-#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +-#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +-#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ +- +- +-/* VPORT.INTFLAGS bit masks and bit positions */ +-#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.INTCTRL bit masks and bit positions */ +-#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +-#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +-#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +-#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +-#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +-#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ +- +-#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +-#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +-#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +-#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +-#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +-#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ +- +- +-/* PORT.INTFLAGS bit masks and bit positions */ +-#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.PIN0CTRL bit masks and bit positions */ +-#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +-#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ +- +-#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +-#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ +- +-#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +-#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +-#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +-#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +-#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +-#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +-#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +-#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ +- +-#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +-#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +-#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +-#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +-#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +-#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +-#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +-#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +- +- +-/* PORT.PIN1CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN2CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN3CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN4CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN5CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN6CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN7CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* TC - 16-bit Timer/Counter With PWM */ +-/* TC0.CTRLA bit masks and bit positions */ +-#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC0.CTRLB bit masks and bit positions */ +-#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +-#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ +- +-#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +-#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ +- +-#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC0.CTRLC bit masks and bit positions */ +-#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +-#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ +- +-#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +-#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ +- +-#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC0.CTRLD bit masks and bit positions */ +-#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC0_EVACT_gp 5 /* Event Action group position. */ +-#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC0.CTRLE bit masks and bit positions */ +-#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC0.INTCTRLA bit masks and bit positions */ +-#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC0.INTCTRLB bit masks and bit positions */ +-#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +-#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +-#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +-#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +-#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +-#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ +- +-#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +-#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +-#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +-#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +-#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +-#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ +- +-#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC0.CTRLFCLR bit masks and bit positions */ +-#define TC0_CMD_gm 0x0C /* Command group mask. */ +-#define TC0_CMD_gp 2 /* Command group position. */ +-#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC0_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC0_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC0_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC0.CTRLFSET bit masks and bit positions */ +-/* TC0_CMD_gm Predefined. */ +-/* TC0_CMD_gp Predefined. */ +-/* TC0_CMD0_bm Predefined. */ +-/* TC0_CMD0_bp Predefined. */ +-/* TC0_CMD1_bm Predefined. */ +-/* TC0_CMD1_bp Predefined. */ +- +-/* TC0_LUPD_bm Predefined. */ +-/* TC0_LUPD_bp Predefined. */ +- +-/* TC0_DIR_bm Predefined. */ +-/* TC0_DIR_bp Predefined. */ +- +- +-/* TC0.CTRLGCLR bit masks and bit positions */ +-#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +-#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ +- +-#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +-#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ +- +-#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC0.CTRLGSET bit masks and bit positions */ +-/* TC0_CCDBV_bm Predefined. */ +-/* TC0_CCDBV_bp Predefined. */ +- +-/* TC0_CCCBV_bm Predefined. */ +-/* TC0_CCCBV_bp Predefined. */ +- +-/* TC0_CCBBV_bm Predefined. */ +-/* TC0_CCBBV_bp Predefined. */ +- +-/* TC0_CCABV_bm Predefined. */ +-/* TC0_CCABV_bp Predefined. */ +- +-/* TC0_PERBV_bm Predefined. */ +-/* TC0_PERBV_bp Predefined. */ +- +- +-/* TC0.INTFLAGS bit masks and bit positions */ +-#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +-#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ +- +-#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +-#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ +- +-#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* TC1.CTRLA bit masks and bit positions */ +-#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC1.CTRLB bit masks and bit positions */ +-#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC1.CTRLC bit masks and bit positions */ +-#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC1.CTRLD bit masks and bit positions */ +-#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC1_EVACT_gp 5 /* Event Action group position. */ +-#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC1.CTRLE bit masks and bit positions */ +-#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC1.INTCTRLA bit masks and bit positions */ +-#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC1.INTCTRLB bit masks and bit positions */ +-#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC1.CTRLFCLR bit masks and bit positions */ +-#define TC1_CMD_gm 0x0C /* Command group mask. */ +-#define TC1_CMD_gp 2 /* Command group position. */ +-#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC1_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC1_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC1_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC1.CTRLFSET bit masks and bit positions */ +-/* TC1_CMD_gm Predefined. */ +-/* TC1_CMD_gp Predefined. */ +-/* TC1_CMD0_bm Predefined. */ +-/* TC1_CMD0_bp Predefined. */ +-/* TC1_CMD1_bm Predefined. */ +-/* TC1_CMD1_bp Predefined. */ +- +-/* TC1_LUPD_bm Predefined. */ +-/* TC1_LUPD_bp Predefined. */ +- +-/* TC1_DIR_bm Predefined. */ +-/* TC1_DIR_bp Predefined. */ +- +- +-/* TC1.CTRLGCLR bit masks and bit positions */ +-#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC1.CTRLGSET bit masks and bit positions */ +-/* TC1_CCBBV_bm Predefined. */ +-/* TC1_CCBBV_bp Predefined. */ +- +-/* TC1_CCABV_bm Predefined. */ +-/* TC1_CCABV_bp Predefined. */ +- +-/* TC1_PERBV_bm Predefined. */ +-/* TC1_PERBV_bp Predefined. */ +- +- +-/* TC1.INTFLAGS bit masks and bit positions */ +-#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* AWEX.CTRL bit masks and bit positions */ +-#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +-#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ +- +-#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +-#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ +- +-#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +-#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ +- +-#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +-#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ +- +-#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +-#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ +- +-#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +-#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ +- +- +-/* AWEX.FDCTRL bit masks and bit positions */ +-#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +-#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ +- +-#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +-#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ +- +-#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +-#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +-#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +-#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +-#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +-#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ +- +- +-/* AWEX.STATUS bit masks and bit positions */ +-#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +-#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ +- +-#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +-#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ +- +-#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +-#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ +- +- +-/* HIRES.CTRLA bit masks and bit positions */ +-#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +-#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +-#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +-#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +-#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +-#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ +- +- +-/* USART - Universal Asynchronous Receiver-Transmitter */ +-/* USART.STATUS bit masks and bit positions */ +-#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +-#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ +- +-#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +-#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +- +-#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +-#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +- +-#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +-#define USART_FERR_bp 4 /* Frame Error bit position. */ +- +-#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +-#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ +- +-#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +-#define USART_PERR_bp 2 /* Parity Error bit position. */ +- +-#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +-#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ +- +- +-/* USART.CTRLA bit masks and bit positions */ +-#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +-#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +-#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +-#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +-#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +-#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ +- +-#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +-#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +-#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +-#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +-#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +-#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ +- +-#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +-#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +-#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +-#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +-#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +-#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ +- +- +-/* USART.CTRLB bit masks and bit positions */ +-#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +-#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ +- +-#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +-#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ +- +-#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +-#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ +- +-#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +-#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ +- +-#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +-#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ +- +- +-/* USART.CTRLC bit masks and bit positions */ +-#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +-#define USART_CMODE_gp 6 /* Communication Mode group position. */ +-#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +-#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +-#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +-#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ +- +-#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +-#define USART_PMODE_gp 4 /* Parity Mode group position. */ +-#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +-#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +-#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +-#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +- +-#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +-#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +- +-#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +-#define USART_CHSIZE_gp 0 /* Character Size group position. */ +-#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +-#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +-#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +-#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +-#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +-#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +- +- +-/* USART.BAUDCTRLA bit masks and bit positions */ +-#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +-#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +-#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +-#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +-#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +-#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +-#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +-#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +-#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +-#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +-#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +-#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +-#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +-#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +-#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +-#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +-#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +-#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ +- +- +-/* USART.BAUDCTRLB bit masks and bit positions */ +-#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +-#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +-#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +-#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +-#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +-#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +-#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +-#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +-#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +-#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ +- +-/* USART_BSEL_gm Predefined. */ +-/* USART_BSEL_gp Predefined. */ +-/* USART_BSEL0_bm Predefined. */ +-/* USART_BSEL0_bp Predefined. */ +-/* USART_BSEL1_bm Predefined. */ +-/* USART_BSEL1_bp Predefined. */ +-/* USART_BSEL2_bm Predefined. */ +-/* USART_BSEL2_bp Predefined. */ +-/* USART_BSEL3_bm Predefined. */ +-/* USART_BSEL3_bp Predefined. */ +- +- +-/* SPI - Serial Peripheral Interface */ +-/* SPI.CTRL bit masks and bit positions */ +-#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +-#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ +- +-#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +-#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ +- +-#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +-#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ +- +-#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +-#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ +- +-#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +-#define SPI_MODE_gp 2 /* SPI Mode group position. */ +-#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +-#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +-#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +-#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ +- +-#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +-#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +-#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +-#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +-#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +-#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ +- +- +-/* SPI.INTCTRL bit masks and bit positions */ +-#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +-#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +-/* SPI.STATUS bit masks and bit positions */ +-#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +-#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ +- +-#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +-#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +- +- +-/* IRCOM - IR Communication Module */ +-/* IRCOM.CTRL bit masks and bit positions */ +-#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +-#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +-#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +-#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +-#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +-#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +-#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +-#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +-#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +-#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ +- +- +- +-// Generic Port Pins +- +-#define PIN0_bm 0x01 +-#define PIN0_bp 0 +-#define PIN1_bm 0x02 +-#define PIN1_bp 1 +-#define PIN2_bm 0x04 +-#define PIN2_bp 2 +-#define PIN3_bm 0x08 +-#define PIN3_bp 3 +-#define PIN4_bm 0x10 +-#define PIN4_bp 4 +-#define PIN5_bm 0x20 +-#define PIN5_bp 5 +-#define PIN6_bm 0x40 +-#define PIN6_bp 6 +-#define PIN7_bm 0x80 +-#define PIN7_bp 7 +- +- +-/* ========== Interrupt Vector Definitions ========== */ +-/* Vector 0 is the reset vector */ +- +-/* OSC interrupt vectors */ +-#define OSC_XOSCF_vect_num 1 +-#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ +- +-/* PORTC interrupt vectors */ +-#define PORTC_INT0_vect_num 2 +-#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +-#define PORTC_INT1_vect_num 3 +-#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ +- +-/* PORTR interrupt vectors */ +-#define PORTR_INT0_vect_num 4 +-#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +-#define PORTR_INT1_vect_num 5 +-#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ +- +-/* RTC interrupt vectors */ +-#define RTC_OVF_vect_num 10 +-#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +-#define RTC_COMP_vect_num 11 +-#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ +- +-/* TWIC interrupt vectors */ +-#define TWIC_TWIS_vect_num 12 +-#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +-#define TWIC_TWIM_vect_num 13 +-#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ +- +-/* TCC0 interrupt vectors */ +-#define TCC0_OVF_vect_num 14 +-#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +-#define TCC0_ERR_vect_num 15 +-#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +-#define TCC0_CCA_vect_num 16 +-#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +-#define TCC0_CCB_vect_num 17 +-#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +-#define TCC0_CCC_vect_num 18 +-#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +-#define TCC0_CCD_vect_num 19 +-#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ +- +-/* TCC1 interrupt vectors */ +-#define TCC1_OVF_vect_num 20 +-#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +-#define TCC1_ERR_vect_num 21 +-#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +-#define TCC1_CCA_vect_num 22 +-#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +-#define TCC1_CCB_vect_num 23 +-#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ +- +-/* SPIC interrupt vectors */ +-#define SPIC_INT_vect_num 24 +-#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ +- +-/* USARTC0 interrupt vectors */ +-#define USARTC0_RXC_vect_num 25 +-#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +-#define USARTC0_DRE_vect_num 26 +-#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +-#define USARTC0_TXC_vect_num 27 +-#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ +- +-/* NVM interrupt vectors */ +-#define NVM_EE_vect_num 32 +-#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +-#define NVM_SPM_vect_num 33 +-#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ +- +-/* PORTB interrupt vectors */ +-#define PORTB_INT0_vect_num 34 +-#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +-#define PORTB_INT1_vect_num 35 +-#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ +- +-/* PORTE interrupt vectors */ +-#define PORTE_INT0_vect_num 43 +-#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +-#define PORTE_INT1_vect_num 44 +-#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ +- +-/* TCE0 interrupt vectors */ +-#define TCE0_OVF_vect_num 47 +-#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +-#define TCE0_ERR_vect_num 48 +-#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +-#define TCE0_CCA_vect_num 49 +-#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +-#define TCE0_CCB_vect_num 50 +-#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +-#define TCE0_CCC_vect_num 51 +-#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +-#define TCE0_CCD_vect_num 52 +-#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ +- +-/* USARTE0 interrupt vectors */ +-#define USARTE0_RXC_vect_num 58 +-#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +-#define USARTE0_DRE_vect_num 59 +-#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +-#define USARTE0_TXC_vect_num 60 +-#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ +- +-/* PORTD interrupt vectors */ +-#define PORTD_INT0_vect_num 64 +-#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +-#define PORTD_INT1_vect_num 65 +-#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ +- +-/* PORTA interrupt vectors */ +-#define PORTA_INT0_vect_num 66 +-#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +-#define PORTA_INT1_vect_num 67 +-#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ +- +-/* ACA interrupt vectors */ +-#define ACA_AC0_vect_num 68 +-#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +-#define ACA_AC1_vect_num 69 +-#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +-#define ACA_ACW_vect_num 70 +-#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ +- +-/* ADCA interrupt vectors */ +-#define ADCA_CH0_vect_num 71 +-#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +- +-/* TCD0 interrupt vectors */ +-#define TCD0_OVF_vect_num 77 +-#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +-#define TCD0_ERR_vect_num 78 +-#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +-#define TCD0_CCA_vect_num 79 +-#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +-#define TCD0_CCB_vect_num 80 +-#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +-#define TCD0_CCC_vect_num 81 +-#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +-#define TCD0_CCD_vect_num 82 +-#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ +- +-/* SPID interrupt vectors */ +-#define SPID_INT_vect_num 87 +-#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ +- +-/* USARTD0 interrupt vectors */ +-#define USARTD0_RXC_vect_num 88 +-#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +-#define USARTD0_DRE_vect_num 89 +-#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +-#define USARTD0_TXC_vect_num 90 +-#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ +- +-/* PORTF interrupt vectors */ +-#define PORTF_INT0_vect_num 104 +-#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +-#define PORTF_INT1_vect_num 105 +-#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ +- +-/* TCF0 interrupt vectors */ +-#define TCF0_OVF_vect_num 108 +-#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ +-#define TCF0_ERR_vect_num 109 +-#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ +-#define TCF0_CCA_vect_num 110 +-#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ +-#define TCF0_CCB_vect_num 111 +-#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ +-#define TCF0_CCC_vect_num 112 +-#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ +-#define TCF0_CCD_vect_num 113 +-#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ +- +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (114 * _VECTOR_SIZE) +- +- +-/* ========== Constants ========== */ +- +-#define PROGMEM_START (0x0000) +-#define PROGMEM_SIZE (270336) +-#define PROGMEM_PAGE_SIZE (512) +-#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) +- +-#define APP_SECTION_START (0x0000) +-#define APP_SECTION_SIZE (262144) +-#define APP_SECTION_PAGE_SIZE (512) +-#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) +- +-#define APPTABLE_SECTION_START (0x3E000) +-#define APPTABLE_SECTION_SIZE (8192) +-#define APPTABLE_SECTION_PAGE_SIZE (512) +-#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) +- +-#define BOOT_SECTION_START (0x40000) +-#define BOOT_SECTION_SIZE (8192) +-#define BOOT_SECTION_PAGE_SIZE (512) +-#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) +- +-#define DATAMEM_START (0x0000) +-#define DATAMEM_SIZE (24576) +-#define DATAMEM_PAGE_SIZE (0) +-#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) +- +-#define IO_START (0x0000) +-#define IO_SIZE (4096) +-#define IO_PAGE_SIZE (0) +-#define IO_END (IO_START + IO_SIZE - 1) +- +-#define MAPPED_EEPROM_START (0x1000) +-#define MAPPED_EEPROM_SIZE (4096) +-#define MAPPED_EEPROM_PAGE_SIZE (0) +-#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) +- +-#define INTERNAL_SRAM_START (0x2000) +-#define INTERNAL_SRAM_SIZE (16384) +-#define INTERNAL_SRAM_PAGE_SIZE (0) +-#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) +- +-#define EEPROM_START (0x0000) +-#define EEPROM_SIZE (4096) +-#define EEPROM_PAGE_SIZE (32) +-#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) +- +-#define FUSE_START (0x0000) +-#define FUSE_SIZE (6) +-#define FUSE_PAGE_SIZE (0) +-#define FUSE_END (FUSE_START + FUSE_SIZE - 1) +- +-#define LOCKBIT_START (0x0000) +-#define LOCKBIT_SIZE (1) +-#define LOCKBIT_PAGE_SIZE (0) +-#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) +- +-#define SIGNATURES_START (0x0000) +-#define SIGNATURES_SIZE (3) +-#define SIGNATURES_PAGE_SIZE (0) +-#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) +- +-#define USER_SIGNATURES_START (0x0000) +-#define USER_SIGNATURES_SIZE (512) +-#define USER_SIGNATURES_PAGE_SIZE (0) +-#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) +- +-#define PROD_SIGNATURES_START (0x0000) +-#define PROD_SIGNATURES_SIZE (52) +-#define PROD_SIGNATURES_PAGE_SIZE (0) +-#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) +- +-#define FLASHEND PROGMEM_END +-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +-#define RAMSTART INTERNAL_SRAM_START +-#define RAMSIZE INTERNAL_SRAM_SIZE +-#define RAMEND INTERNAL_SRAM_END +-#define XRAMSTART EXTERNAL_SRAM_START +-#define XRAMSIZE EXTERNAL_SRAM_SIZE +-#define XRAMEND INTERNAL_SRAM_END +-#define E2END EEPROM_END +-#define E2PAGESIZE EEPROM_PAGE_SIZE +- +- +-/* ========== Fuses ========== */ +-#define FUSE_MEMORY_SIZE 6 +- +-/* Fuse Byte 0 */ +-#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ +-#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ +-#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ +-#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ +-#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ +-#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ +-#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ +-#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ +-#define FUSE0_DEFAULT (0xFF) +- +-/* Fuse Byte 1 */ +-#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +-#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +-#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +-#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +-#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +-#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +-#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +-#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +-#define FUSE1_DEFAULT (0xFF) +- +-/* Fuse Byte 2 */ +-#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +-#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +-#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +-#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +-#define FUSE2_DEFAULT (0xFF) +- +-/* Fuse Byte 3 Reserved */ +- +-/* Fuse Byte 4 */ +-#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +-#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +-#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +-#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ +-#define FUSE4_DEFAULT (0xFF) +- +-/* Fuse Byte 5 */ +-#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +-#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +-#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +-#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +-#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +-#define FUSE5_DEFAULT (0xFF) +- +- +-/* ========== Lock Bits ========== */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_BITS_EXIST +-#define __BOOT_LOCK_BOOT_BITS_EXIST +- +- +-/* ========== Signature ========== */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x98 +-#define SIGNATURE_2 0x44 +- +- +-#endif /* _AVR_ATxmega256D3_H_ */ +- ++/* Copyright (c) 2009-2010 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iox256d3.h 2162 2010-06-11 17:26:12Z arcanum $ */ ++ ++/* avr/iox256d3.h - definitions for ATxmega256D3 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox256d3.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATxmega256D3_H_ ++#define _AVR_ATxmega256D3_H_ 1 ++ ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++} CLK_t; ++ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t reserved_0x02; ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ ++} CLK_RTCSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control REgister */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ ++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ ++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ ++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ ++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t reserved_0x07; ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ ++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ ++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ ++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ ++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ ++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ ++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ ++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ ++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ ++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ ++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ ++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ ++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t FUSEBYTE0; /* User ID */ ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ ++ register8_t reserved_0x01; ++ register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++} NVM_PROD_SIGNATURES_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++} NVM_LB_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brown Out Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V9_gc = (0x06<<0), /* 1.9 V */ ++ BODLVL_2V1_gc = (0x05<<0), /* 2.1 V */ ++ BODLVL_2V4_gc = (0x04<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x03<<0), /* 2.6 V */ ++ BODLVL_2V9_gc = (0x02<<0), /* 2.9 V */ ++ BODLVL_3V2_gc = (0x01<<0), /* 3.2 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Comparator 0 Control */ ++ register8_t AC1CTRL; /* Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t reserved_0x6; ++ register8_t reserved_0x7; ++} ADC_CH_t; ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* ACD Temporary Register */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++} ADC_t; ++ ++/* Current Limitation */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 225ksps max sampling rate */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 75ksps max sampling rate */ ++} ADC_CURRLIMIT_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++} ADC_REFSEL_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Clounter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* EBI Chip Select Module */ ++typedef struct EBI_CS_struct ++{ ++ register8_t CTRLA; /* Chip Select Control Register A */ ++ register8_t CTRLB; /* Chip Select Control Register B */ ++ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ ++} EBI_CS_t; ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* External Bus Interface */ ++typedef struct EBI_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ ++ register8_t reserved_0x02; ++ register8_t reserved_0x03; ++ _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ ++ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ ++ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ ++ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ EBI_CS_t CS0; /* Chip Select 0 */ ++ EBI_CS_t CS1; /* Chip Select 1 */ ++ EBI_CS_t CS2; /* Chip Select 2 */ ++ EBI_CS_t CS3; /* Chip Select 3 */ ++} EBI_t; ++ ++/* Chip Select adress space */ ++typedef enum EBI_CS_ASIZE_enum ++{ ++ EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ ++ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ ++ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ ++ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ ++ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ ++ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ ++ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ ++ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ ++ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ ++ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ ++ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ ++ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ ++ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ ++ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ ++ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ ++ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ ++ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ ++} EBI_CS_ASIZE_t; ++ ++/* */ ++typedef enum EBI_CS_SRWS_enum ++{ ++ EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_CS_SRWS_t; ++ ++/* Chip Select address mode */ ++typedef enum EBI_CS_MODE_enum ++{ ++ EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ ++ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ ++ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ ++ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ ++} EBI_CS_MODE_t; ++ ++/* Chip Select SDRAM mode */ ++typedef enum EBI_CS_SDMODE_enum ++{ ++ EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ ++ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ ++} EBI_CS_SDMODE_t; ++ ++/* */ ++typedef enum EBI_SDDATAW_enum ++{ ++ EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ ++ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ ++} EBI_SDDATAW_t; ++ ++/* */ ++typedef enum EBI_LPCMODE_enum ++{ ++ EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ ++ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ ++} EBI_LPCMODE_t; ++ ++/* */ ++typedef enum EBI_SRMODE_enum ++{ ++ EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ ++ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ ++ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ ++ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ ++} EBI_SRMODE_t; ++ ++/* */ ++typedef enum EBI_IFMODE_enum ++{ ++ EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ ++ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ ++ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ ++ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ ++} EBI_IFMODE_t; ++ ++/* */ ++typedef enum EBI_SDCOL_enum ++{ ++ EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ ++ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ ++ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ ++ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ ++} EBI_SDCOL_t; ++ ++/* */ ++typedef enum EBI_MRDLY_enum ++{ ++ EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_MRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCYCDLY_enum ++{ ++ EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ROWCYCDLY_t; ++ ++/* */ ++typedef enum EBI_RPDLY_enum ++{ ++ EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_RPDLY_t; ++ ++/* */ ++typedef enum EBI_WRDLY_enum ++{ ++ EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_WRDLY_t; ++ ++/* */ ++typedef enum EBI_ESRDLY_enum ++{ ++ EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ESRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCOLDLY_enum ++{ ++ EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_ROWCOLDLY_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++} PORTCFG_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Virtual Port 0 Mapping */ ++typedef enum PORTCFG_VP0MAP_enum ++{ ++ PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP0MAP_t; ++ ++/* Virtual Port 1 Mapping */ ++typedef enum PORTCFG_VP1MAP_enum ++{ ++ PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP1MAP_t; ++ ++/* Virtual Port 2 Mapping */ ++typedef enum PORTCFG_VP2MAP_enum ++{ ++ PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP2MAP_t; ++ ++/* Virtual Port 3 Mapping */ ++typedef enum PORTCFG_VP3MAP_enum ++{ ++ PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP3MAP_t; ++ ++/* Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x05; ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ ++#define RST (*(RST_t *) 0x0078) /* Reset Controller */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ ++#define PORTA (*(PORT_t *) 0x0600) /* Port A */ ++#define PORTB (*(PORT_t *) 0x0620) /* Port B */ ++#define PORTC (*(PORT_t *) 0x0640) /* Port C */ ++#define PORTD (*(PORT_t *) 0x0660) /* Port D */ ++#define PORTE (*(PORT_t *) 0x0680) /* Port E */ ++#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ ++#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ ++#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ ++#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ ++#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ ++#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++#define GPIO_GPIOR4 _SFR_MEM8(0x0004) ++#define GPIO_GPIOR5 _SFR_MEM8(0x0005) ++#define GPIO_GPIOR6 _SFR_MEM8(0x0006) ++#define GPIO_GPIOR7 _SFR_MEM8(0x0007) ++#define GPIO_GPIOR8 _SFR_MEM8(0x0008) ++#define GPIO_GPIOR9 _SFR_MEM8(0x0009) ++#define GPIO_GPIORA _SFR_MEM8(0x000A) ++#define GPIO_GPIORB _SFR_MEM8(0x000B) ++#define GPIO_GPIORC _SFR_MEM8(0x000C) ++#define GPIO_GPIORD _SFR_MEM8(0x000D) ++#define GPIO_GPIORE _SFR_MEM8(0x000E) ++#define GPIO_GPIORF _SFR_MEM8(0x000F) ++ ++/* VPORT0 - Virtual Port 0 */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT1 - Virtual Port 1 */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT2 - Virtual Port 2 */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT3 - Virtual Port 3 */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU Registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator Control */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset Controller */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - Port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non Volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADCA - Analog to Digital Converter A */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++ ++/* ACA - Analog Comparator A */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWIC - Two-Wire Interface C */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWIE - Two-Wire Interface E */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* PORTA - Port A */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORTB - Port B */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORTC - Port C */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORTD - Port D */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORTE - Port E */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORTF - Port F */ ++#define PORTF_DIR _SFR_MEM8(0x06A0) ++#define PORTF_DIRSET _SFR_MEM8(0x06A1) ++#define PORTF_DIRCLR _SFR_MEM8(0x06A2) ++#define PORTF_DIRTGL _SFR_MEM8(0x06A3) ++#define PORTF_OUT _SFR_MEM8(0x06A4) ++#define PORTF_OUTSET _SFR_MEM8(0x06A5) ++#define PORTF_OUTCLR _SFR_MEM8(0x06A6) ++#define PORTF_OUTTGL _SFR_MEM8(0x06A7) ++#define PORTF_IN _SFR_MEM8(0x06A8) ++#define PORTF_INTCTRL _SFR_MEM8(0x06A9) ++#define PORTF_INT0MASK _SFR_MEM8(0x06AA) ++#define PORTF_INT1MASK _SFR_MEM8(0x06AB) ++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) ++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) ++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) ++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) ++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) ++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) ++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) ++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) ++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) ++ ++/* PORTR - Port R */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TCC0 - Timer/Counter C0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TCC1 - Timer/Counter C1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEXC - Advanced Waveform Extension C */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRESC - High-Resolution Extension C */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* SPIC - Serial Peripheral Interface C */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TCD0 - Timer/Counter D0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* SPID - Serial Peripheral Interface D */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TCE0 - Timer/Counter E0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* AWEXE - Advanced Waveform Extension E */ ++#define AWEXE_CTRL _SFR_MEM8(0x0A80) ++#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) ++#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) ++#define AWEXE_STATUS _SFR_MEM8(0x0A84) ++#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) ++#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) ++#define AWEXE_DTLS _SFR_MEM8(0x0A88) ++#define AWEXE_DTHS _SFR_MEM8(0x0A89) ++#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) ++#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) ++#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) ++ ++/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* SPIE - Serial Peripheral Interface E */ ++#define SPIE_CTRL _SFR_MEM8(0x0AC0) ++#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) ++#define SPIE_STATUS _SFR_MEM8(0x0AC2) ++#define SPIE_DATA _SFR_MEM8(0x0AC3) ++ ++/* TCF0 - Timer/Counter F0 */ ++#define TCF0_CTRLA _SFR_MEM8(0x0B00) ++#define TCF0_CTRLB _SFR_MEM8(0x0B01) ++#define TCF0_CTRLC _SFR_MEM8(0x0B02) ++#define TCF0_CTRLD _SFR_MEM8(0x0B03) ++#define TCF0_CTRLE _SFR_MEM8(0x0B04) ++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) ++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) ++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) ++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) ++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF0_TEMP _SFR_MEM8(0x0B0F) ++#define TCF0_CNT _SFR_MEM16(0x0B20) ++#define TCF0_PER _SFR_MEM16(0x0B26) ++#define TCF0_CCA _SFR_MEM16(0x0B28) ++#define TCF0_CCB _SFR_MEM16(0x0B2A) ++#define TCF0_CCC _SFR_MEM16(0x0B2C) ++#define TCF0_CCD _SFR_MEM16(0x0B2E) ++#define TCF0_PERBUF _SFR_MEM16(0x0B36) ++#define TCF0_CCABUF _SFR_MEM16(0x0B38) ++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) ++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) ++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR1 bit masks and bit positions */ ++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ ++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ ++ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ ++#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ ++ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ ++ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ ++ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ ++#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ ++ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ ++ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ ++ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ ++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ ++ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM_gm Predefined. */ ++/* EVSYS_QDIRM_gp Predefined. */ ++/* EVSYS_QDIRM0_bm Predefined. */ ++/* EVSYS_QDIRM0_bp Predefined. */ ++/* EVSYS_QDIRM1_bm Predefined. */ ++/* EVSYS_QDIRM1_bp Predefined. */ ++ ++/* EVSYS_QDIEN_bm Predefined. */ ++/* EVSYS_QDIEN_bp Predefined. */ ++ ++/* EVSYS_QDEN_bm Predefined. */ ++/* EVSYS_QDEN_bp Predefined. */ ++ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0xFF /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ ++#define NVM_CMD7_bp 7 /* Command bit 7 position. */ ++ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ ++#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ ++#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ ++#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ ++#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ ++#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ ++#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ ++#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ ++#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ ++#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ ++#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ ++#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ ++#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ ++#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ ++#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ ++#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ ++#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ ++#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ ++#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ ++#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ ++ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ ++ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ ++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE_gm Predefined. */ ++/* AC_INTMODE_gp Predefined. */ ++/* AC_INTMODE0_bm Predefined. */ ++/* AC_INTMODE0_bp Predefined. */ ++/* AC_INTMODE1_bm Predefined. */ ++/* AC_INTMODE1_bp Predefined. */ ++ ++/* AC_INTLVL_gm Predefined. */ ++/* AC_INTLVL_gp Predefined. */ ++/* AC_INTLVL0_bm Predefined. */ ++/* AC_INTLVL0_bp Predefined. */ ++/* AC_INTLVL1_bm Predefined. */ ++/* AC_INTLVL1_bp Predefined. */ ++ ++/* AC_HSMODE_bm Predefined. */ ++/* AC_HSMODE_bp Predefined. */ ++ ++/* AC_HYSMODE_gm Predefined. */ ++/* AC_HYSMODE_gp Predefined. */ ++/* AC_HYSMODE0_bm Predefined. */ ++/* AC_HYSMODE0_bp Predefined. */ ++/* AC_HYSMODE1_bm Predefined. */ ++/* AC_HYSMODE1_bp Predefined. */ ++ ++/* AC_ENABLE_bm Predefined. */ ++/* AC_ENABLE_bp Predefined. */ ++ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS_gm Predefined. */ ++/* AC_MUXPOS_gp Predefined. */ ++/* AC_MUXPOS0_bm Predefined. */ ++/* AC_MUXPOS0_bp Predefined. */ ++/* AC_MUXPOS1_bm Predefined. */ ++/* AC_MUXPOS1_bp Predefined. */ ++/* AC_MUXPOS2_bm Predefined. */ ++/* AC_MUXPOS2_bp Predefined. */ ++ ++/* AC_MUXNEG_gm Predefined. */ ++/* AC_MUXNEG_gp Predefined. */ ++/* AC_MUXNEG0_bm Predefined. */ ++/* AC_MUXNEG0_bp Predefined. */ ++/* AC_MUXNEG1_bm Predefined. */ ++/* AC_MUXNEG1_bp Predefined. */ ++/* AC_MUXNEG2_bm Predefined. */ ++/* AC_MUXNEG2_bp Predefined. */ ++ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ ++ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ ++ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ ++ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ ++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_bm 0x01 /* Event Action Select bit mask. */ ++#define ADC_EVACT_bp 0 /* Event Action Select bit position. */ ++ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++ ++/* RTC - Real-Time Clounter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* EBI - External Bus Interface */ ++/* EBI_CS.CTRLA bit masks and bit positions */ ++#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ ++#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ ++#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ ++#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ ++#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ ++#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ ++#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ ++#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ ++#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ ++#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ ++#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ ++#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ ++ ++#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ ++#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ ++#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ ++#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ ++#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ ++#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ ++ ++ ++/* EBI_CS.CTRLB bit masks and bit positions */ ++#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ ++#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ ++#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ ++#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ ++#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ ++#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ ++#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ ++#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ ++ ++#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ ++#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ ++ ++#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ ++#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ ++ ++#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ ++#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ ++#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ ++#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ ++#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ ++#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ ++ ++ ++/* EBI.CTRL bit masks and bit positions */ ++#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ ++#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ ++#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ ++#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ ++#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ ++#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ ++ ++#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ ++#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ ++#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ ++#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ ++#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ ++#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ ++ ++#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ ++#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ ++#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ ++#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ ++#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ ++#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ ++ ++#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ ++#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ ++#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ ++#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ ++#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ ++#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLA bit masks and bit positions */ ++#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ ++#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ ++ ++#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ ++#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ ++ ++#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ ++#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ ++#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ ++#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ ++#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ ++#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLB bit masks and bit positions */ ++#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ ++#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ ++#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ ++#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ ++#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ ++#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ ++ ++#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ ++#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ ++#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ ++#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ ++#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ ++#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ ++#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ ++#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ ++ ++#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ ++#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ ++#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ ++#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ ++#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ ++#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ ++#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ ++#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ ++ ++ ++/* EBI.SDRAMCTRLC bit masks and bit positions */ ++#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ ++#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ ++#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ ++#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ ++#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ ++#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ ++ ++#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ ++#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ ++#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ ++#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ ++#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ ++#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ ++#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ ++#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ ++ ++#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ ++#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ ++#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ ++#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ ++#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ ++#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ ++#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ ++#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ ++ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ ++#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++ ++/* PORT - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD_gm Predefined. */ ++/* TC0_CMD_gp Predefined. */ ++/* TC0_CMD0_bm Predefined. */ ++/* TC0_CMD0_bp Predefined. */ ++/* TC0_CMD1_bm Predefined. */ ++/* TC0_CMD1_bp Predefined. */ ++ ++/* TC0_LUPD_bm Predefined. */ ++/* TC0_LUPD_bp Predefined. */ ++ ++/* TC0_DIR_bm Predefined. */ ++/* TC0_DIR_bp Predefined. */ ++ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV_bm Predefined. */ ++/* TC0_CCDBV_bp Predefined. */ ++ ++/* TC0_CCCBV_bm Predefined. */ ++/* TC0_CCCBV_bp Predefined. */ ++ ++/* TC0_CCBBV_bm Predefined. */ ++/* TC0_CCBBV_bp Predefined. */ ++ ++/* TC0_CCABV_bm Predefined. */ ++/* TC0_CCABV_bp Predefined. */ ++ ++/* TC0_PERBV_bm Predefined. */ ++/* TC0_PERBV_bp Predefined. */ ++ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD_gm Predefined. */ ++/* TC1_CMD_gp Predefined. */ ++/* TC1_CMD0_bm Predefined. */ ++/* TC1_CMD0_bp Predefined. */ ++/* TC1_CMD1_bm Predefined. */ ++/* TC1_CMD1_bp Predefined. */ ++ ++/* TC1_LUPD_bm Predefined. */ ++/* TC1_LUPD_bp Predefined. */ ++ ++/* TC1_DIR_bm Predefined. */ ++/* TC1_DIR_bp Predefined. */ ++ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV_bm Predefined. */ ++/* TC1_CCBBV_bp Predefined. */ ++ ++/* TC1_CCABV_bm Predefined. */ ++/* TC1_CCABV_bp Predefined. */ ++ ++/* TC1_PERBV_bm Predefined. */ ++/* TC1_PERBV_bp Predefined. */ ++ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL_gm Predefined. */ ++/* USART_BSEL_gp Predefined. */ ++/* USART_BSEL0_bm Predefined. */ ++/* USART_BSEL0_bp Predefined. */ ++/* USART_BSEL1_bm Predefined. */ ++/* USART_BSEL1_bp Predefined. */ ++/* USART_BSEL2_bm Predefined. */ ++/* USART_BSEL2_bp Predefined. */ ++/* USART_BSEL3_bm Predefined. */ ++/* USART_BSEL3_bp Predefined. */ ++ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_XOSCF_vect_num 1 ++#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* PORTF interrupt vectors */ ++#define PORTF_INT0_vect_num 104 ++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ ++#define PORTF_INT1_vect_num 105 ++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_OVF_vect_num 108 ++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ ++#define TCF0_ERR_vect_num 109 ++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ ++#define TCF0_CCA_vect_num 110 ++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ ++#define TCF0_CCB_vect_num 111 ++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ ++#define TCF0_CCC_vect_num 112 ++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ ++#define TCF0_CCD_vect_num 113 ++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ ++ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (114 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (270336) ++#define PROGMEM_PAGE_SIZE (512) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (262144) ++#define APP_SECTION_PAGE_SIZE (512) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x3E000) ++#define APPTABLE_SECTION_SIZE (8192) ++#define APPTABLE_SECTION_PAGE_SIZE (512) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x40000) ++#define BOOT_SECTION_SIZE (8192) ++#define BOOT_SECTION_PAGE_SIZE (512) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (24576) ++#define DATAMEM_PAGE_SIZE (0) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (4096) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (16384) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (4096) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define FUSE_START (0x0000) ++#define FUSE_SIZE (6) ++#define FUSE_PAGE_SIZE (0) ++#define FUSE_END (FUSE_START + FUSE_SIZE - 1) ++ ++#define LOCKBIT_START (0x0000) ++#define LOCKBIT_SIZE (1) ++#define LOCKBIT_PAGE_SIZE (0) ++#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (512) ++#define USER_SIGNATURES_PAGE_SIZE (0) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (0) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE PROGMEM_PAGE_SIZE ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define XRAMSTART EXTERNAL_SRAM_START ++#define XRAMSIZE EXTERNAL_SRAM_SIZE ++#define XRAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 */ ++#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ ++#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ ++#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ ++#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ ++#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ ++#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ ++#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ ++#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ ++#define FUSE0_DEFAULT (0xFF) ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x98 ++#define SIGNATURE_2 0x44 ++ ++ ++#endif /* _AVR_ATxmega256D3_H_ */ ++ +diff --git a/include/avr/iox32a4.h b/include/avr/iox32a4.h +index d27bde1..3104cc0 100644 +--- a/include/avr/iox32a4.h ++++ b/include/avr/iox32a4.h +@@ -1,6673 +1,6673 @@ +-/* Copyright (c) 2009-2010 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iox32a4.h 2200 2010-12-14 04:24:24Z arcanum $ */ +- +-/* avr/iox32a4.h - definitions for ATxmega32A4 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iox32a4.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATxmega32A4_H_ +-#define _AVR_ATxmega32A4_H_ 1 +- +- +-/* Ungrouped common registers */ +-#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +-#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +-#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +-#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +-#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +-#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +-#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +-#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +-#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +-#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +-#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +-#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +-#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +-#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +-#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +-#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +- +-/* Deprecated */ +-#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +-#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +-#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +-#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +-#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +-#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +-#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +-#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +-#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +-#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +-#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +-#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +-#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +-#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +-#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +-#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +- +-#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +-#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +-#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +-#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +-#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +-#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +-#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +-#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +-#define SREG _SFR_MEM8(0x003F) /* Status Register */ +- +- +-/* C Language Only */ +-#if !defined (__ASSEMBLER__) +- +-#include +- +-typedef volatile uint8_t register8_t; +-typedef volatile uint16_t register16_t; +-typedef volatile uint32_t register32_t; +- +- +-#ifdef _WORDREGISTER +-#undef _WORDREGISTER +-#endif +-#define _WORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register16_t regname; \ +- struct \ +- { \ +- register8_t regname ## L; \ +- register8_t regname ## H; \ +- }; \ +- } +- +-#ifdef _DWORDREGISTER +-#undef _DWORDREGISTER +-#endif +-#define _DWORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register32_t regname; \ +- struct \ +- { \ +- register8_t regname ## 0; \ +- register8_t regname ## 1; \ +- register8_t regname ## 2; \ +- register8_t regname ## 3; \ +- }; \ +- } +- +- +-/* +-========================================================================== +-IO Module Structures +-========================================================================== +-*/ +- +- +-/* +--------------------------------------------------------------------------- +-XOCD - On-Chip Debug System +--------------------------------------------------------------------------- +-*/ +- +-/* On-Chip Debug System */ +-typedef struct OCD_struct +-{ +- register8_t OCDR0; /* OCD Register 0 */ +- register8_t OCDR1; /* OCD Register 1 */ +-} OCD_t; +- +- +-/* CCP signatures */ +-typedef enum CCP_enum +-{ +- CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ +- CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +-} CCP_t; +- +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Clock System */ +-typedef struct CLK_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t PSCTRL; /* Prescaler Control Register */ +- register8_t LOCK; /* Lock register */ +- register8_t RTCCTRL; /* RTC Control Register */ +-} CLK_t; +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Power Reduction */ +-typedef struct PR_struct +-{ +- register8_t PRGEN; /* General Power Reduction */ +- register8_t PRPA; /* Power Reduction Port A */ +- register8_t PRPB; /* Power Reduction Port B */ +- register8_t PRPC; /* Power Reduction Port C */ +- register8_t PRPD; /* Power Reduction Port D */ +- register8_t PRPE; /* Power Reduction Port E */ +- register8_t PRPF; /* Power Reduction Port F */ +-} PR_t; +- +-/* System Clock Selection */ +-typedef enum CLK_SCLKSEL_enum +-{ +- CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ +- CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ +- CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ +- CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ +- CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +-} CLK_SCLKSEL_t; +- +-/* Prescaler A Division Factor */ +-typedef enum CLK_PSADIV_enum +-{ +- CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ +- CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ +- CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ +- CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ +- CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ +- CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ +- CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ +- CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ +- CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ +- CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +-} CLK_PSADIV_t; +- +-/* Prescaler B and C Division Factor */ +-typedef enum CLK_PSBCDIV_enum +-{ +- CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ +- CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ +- CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ +- CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +-} CLK_PSBCDIV_t; +- +-/* RTC Clock Source */ +-typedef enum CLK_RTCSRC_enum +-{ +- CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ +- CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ +- CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ +- CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +-} CLK_RTCSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-SLEEP - Sleep Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Sleep Controller */ +-typedef struct SLEEP_struct +-{ +- register8_t CTRL; /* Control Register */ +-} SLEEP_t; +- +-/* Sleep Mode */ +-typedef enum SLEEP_SMODE_enum +-{ +- SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ +- SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +- SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ +- SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ +- SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +-} SLEEP_SMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-OSC - Oscillator +--------------------------------------------------------------------------- +-*/ +- +-/* Oscillator */ +-typedef struct OSC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t XOSCCTRL; /* External Oscillator Control Register */ +- register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ +- register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ +- register8_t PLLCTRL; /* PLL Control REgister */ +- register8_t DFLLCTRL; /* DFLL Control Register */ +-} OSC_t; +- +-/* Oscillator Frequency Range */ +-typedef enum OSC_FRQRANGE_enum +-{ +- OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ +- OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ +- OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ +- OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +-} OSC_FRQRANGE_t; +- +-/* External Oscillator Selection and Startup Time */ +-typedef enum OSC_XOSCSEL_enum +-{ +- OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ +- OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ +- OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ +- OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ +- OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +-} OSC_XOSCSEL_t; +- +-/* PLL Clock Source */ +-typedef enum OSC_PLLSRC_enum +-{ +- OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ +- OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ +- OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +-} OSC_PLLSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-DFLL - DFLL +--------------------------------------------------------------------------- +-*/ +- +-/* DFLL */ +-typedef struct DFLL_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t CALA; /* Calibration Register A */ +- register8_t CALB; /* Calibration Register B */ +- register8_t COMP0; /* Oscillator Compare Register 0 */ +- register8_t COMP1; /* Oscillator Compare Register 1 */ +- register8_t COMP2; /* Oscillator Compare Register 2 */ +- register8_t reserved_0x07; +-} DFLL_t; +- +- +-/* +--------------------------------------------------------------------------- +-RST - Reset +--------------------------------------------------------------------------- +-*/ +- +-/* Reset */ +-typedef struct RST_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t CTRL; /* Control Register */ +-} RST_t; +- +- +-/* +--------------------------------------------------------------------------- +-WDT - Watch-Dog Timer +--------------------------------------------------------------------------- +-*/ +- +-/* Watch-Dog Timer */ +-typedef struct WDT_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t WINCTRL; /* Windowed Mode Control */ +- register8_t STATUS; /* Status */ +-} WDT_t; +- +-/* Period setting */ +-typedef enum WDT_PER_enum +-{ +- WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ +- WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ +- WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ +- WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_PER_t; +- +-/* Closed window period */ +-typedef enum WDT_WPER_enum +-{ +- WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ +- WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ +- WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ +- WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_WPER_t; +- +- +-/* +--------------------------------------------------------------------------- +-MCU - MCU Control +--------------------------------------------------------------------------- +-*/ +- +-/* MCU Control */ +-typedef struct MCU_struct +-{ +- register8_t DEVID0; /* Device ID byte 0 */ +- register8_t DEVID1; /* Device ID byte 1 */ +- register8_t DEVID2; /* Device ID byte 2 */ +- register8_t REVID; /* Revision ID */ +- register8_t JTAGUID; /* JTAG User ID */ +- register8_t reserved_0x05; +- register8_t MCUCR; /* MCU Control */ +- register8_t reserved_0x07; +- register8_t EVSYSLOCK; /* Event System Lock */ +- register8_t AWEXLOCK; /* AWEX Lock */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +-} MCU_t; +- +- +-/* +--------------------------------------------------------------------------- +-PMIC - Programmable Multi-level Interrupt Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Programmable Multi-level Interrupt Controller */ +-typedef struct PMIC_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t INTPRI; /* Interrupt Priority */ +- register8_t CTRL; /* Control Register */ +-} PMIC_t; +- +- +-/* +--------------------------------------------------------------------------- +-DMA - DMA Controller +--------------------------------------------------------------------------- +-*/ +- +-/* DMA Channel */ +-typedef struct DMA_CH_struct +-{ +- register8_t CTRLA; /* Channel Control */ +- register8_t CTRLB; /* Channel Control */ +- register8_t ADDRCTRL; /* Address Control */ +- register8_t TRIGSRC; /* Channel Trigger Source */ +- _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ +- register8_t REPCNT; /* Channel Repeat Count */ +- register8_t reserved_0x07; +- register8_t SRCADDR0; /* Channel Source Address 0 */ +- register8_t SRCADDR1; /* Channel Source Address 1 */ +- register8_t SRCADDR2; /* Channel Source Address 2 */ +- register8_t reserved_0x0B; +- register8_t DESTADDR0; /* Channel Destination Address 0 */ +- register8_t DESTADDR1; /* Channel Destination Address 1 */ +- register8_t DESTADDR2; /* Channel Destination Address 2 */ +- register8_t reserved_0x0F; +-} DMA_CH_t; +- +-/* +--------------------------------------------------------------------------- +-DMA - DMA Controller +--------------------------------------------------------------------------- +-*/ +- +-/* DMA Controller */ +-typedef struct DMA_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t reserved_0x01; +- register8_t reserved_0x02; +- register8_t INTFLAGS; /* Transfer Interrupt Status */ +- register8_t STATUS; /* Status */ +- register8_t reserved_0x05; +- _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- DMA_CH_t CH0; /* DMA Channel 0 */ +- DMA_CH_t CH1; /* DMA Channel 1 */ +- DMA_CH_t CH2; /* DMA Channel 2 */ +- DMA_CH_t CH3; /* DMA Channel 3 */ +-} DMA_t; +- +-/* Burst mode */ +-typedef enum DMA_CH_BURSTLEN_enum +-{ +- DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ +- DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ +- DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ +- DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +-} DMA_CH_BURSTLEN_t; +- +-/* Source address reload mode */ +-typedef enum DMA_CH_SRCRELOAD_enum +-{ +- DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ +- DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ +- DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ +- DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +-} DMA_CH_SRCRELOAD_t; +- +-/* Source addressing mode */ +-typedef enum DMA_CH_SRCDIR_enum +-{ +- DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ +- DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ +- DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +-} DMA_CH_SRCDIR_t; +- +-/* Destination adress reload mode */ +-typedef enum DMA_CH_DESTRELOAD_enum +-{ +- DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ +- DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ +- DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ +- DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +-} DMA_CH_DESTRELOAD_t; +- +-/* Destination adressing mode */ +-typedef enum DMA_CH_DESTDIR_enum +-{ +- DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ +- DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ +- DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +-} DMA_CH_DESTDIR_t; +- +-/* Transfer trigger source */ +-typedef enum DMA_CH_TRIGSRC_enum +-{ +- DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ +- DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ +- DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ +- DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ +- DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ +- DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ +- DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ +- DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ +- DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ +- DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ +- DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ +- DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ +- DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ +- DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ +- DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ +- DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ +- DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ +- DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ +- DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ +- DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ +- DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ +- DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ +- DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ +- DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ +- DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ +- DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ +- DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ +- DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ +- DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ +- DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ +- DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ +- DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ +- DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ +- DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ +- DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ +- DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ +- DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ +- DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ +- DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +-} DMA_CH_TRIGSRC_t; +- +-/* Double buffering mode */ +-typedef enum DMA_DBUFMODE_enum +-{ +- DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ +- DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ +- DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ +- DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +-} DMA_DBUFMODE_t; +- +-/* Priority mode */ +-typedef enum DMA_PRIMODE_enum +-{ +- DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ +- DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ +- DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ +- DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +-} DMA_PRIMODE_t; +- +-/* Interrupt level */ +-typedef enum DMA_CH_ERRINTLVL_enum +-{ +- DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ +- DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ +- DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +-} DMA_CH_ERRINTLVL_t; +- +-/* Interrupt level */ +-typedef enum DMA_CH_TRNINTLVL_enum +-{ +- DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ +- DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ +- DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +-} DMA_CH_TRNINTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-EVSYS - Event System +--------------------------------------------------------------------------- +-*/ +- +-/* Event System */ +-typedef struct EVSYS_struct +-{ +- register8_t CH0MUX; /* Event Channel 0 Multiplexer */ +- register8_t CH1MUX; /* Event Channel 1 Multiplexer */ +- register8_t CH2MUX; /* Event Channel 2 Multiplexer */ +- register8_t CH3MUX; /* Event Channel 3 Multiplexer */ +- register8_t CH4MUX; /* Event Channel 4 Multiplexer */ +- register8_t CH5MUX; /* Event Channel 5 Multiplexer */ +- register8_t CH6MUX; /* Event Channel 6 Multiplexer */ +- register8_t CH7MUX; /* Event Channel 7 Multiplexer */ +- register8_t CH0CTRL; /* Channel 0 Control Register */ +- register8_t CH1CTRL; /* Channel 1 Control Register */ +- register8_t CH2CTRL; /* Channel 2 Control Register */ +- register8_t CH3CTRL; /* Channel 3 Control Register */ +- register8_t CH4CTRL; /* Channel 4 Control Register */ +- register8_t CH5CTRL; /* Channel 5 Control Register */ +- register8_t CH6CTRL; /* Channel 6 Control Register */ +- register8_t CH7CTRL; /* Channel 7 Control Register */ +- register8_t STROBE; /* Event Strobe */ +- register8_t DATA; /* Event Data */ +-} EVSYS_t; +- +-/* Quadrature Decoder Index Recognition Mode */ +-typedef enum EVSYS_QDIRM_enum +-{ +- EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ +- EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ +- EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ +- EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +-} EVSYS_QDIRM_t; +- +-/* Digital filter coefficient */ +-typedef enum EVSYS_DIGFILT_enum +-{ +- EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ +- EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ +- EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ +- EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ +- EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ +- EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ +- EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ +- EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +-} EVSYS_DIGFILT_t; +- +-/* Event Channel multiplexer input selection */ +-typedef enum EVSYS_CHMUX_enum +-{ +- EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ +- EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ +- EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ +- EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ +- EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ +- EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ +- EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ +- EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ +- EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ +- EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ +- EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ +- EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ +- EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ +- EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ +- EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ +- EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ +- EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ +- EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ +- EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ +- EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ +- EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ +- EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ +- EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ +- EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ +- EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ +- EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ +- EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ +- EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ +- EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ +- EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ +- EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ +- EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ +- EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ +- EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ +- EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ +- EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ +- EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ +- EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ +- EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ +- EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ +- EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ +- EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ +- EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ +- EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ +- EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ +- EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ +- EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ +- EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ +- EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ +- EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ +- EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ +- EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ +- EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ +- EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ +- EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ +- EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ +- EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ +- EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ +- EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ +- EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ +- EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ +- EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ +- EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ +- EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ +- EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ +- EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ +- EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ +- EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ +- EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ +- EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ +- EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ +- EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ +- EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ +- EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ +- EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ +- EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ +- EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ +- EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ +- EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ +- EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ +- EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ +- EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ +- EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ +- EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ +- EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ +- EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ +- EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ +- EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ +- EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ +- EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ +- EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ +- EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ +- EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ +- EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ +- EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ +- EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ +- EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ +- EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ +- EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ +- EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ +- EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ +- EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ +- EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ +- EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ +- EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ +- EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ +- EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ +- EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ +- EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ +- EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ +- EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +- EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ +- EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ +- EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ +- EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +-} EVSYS_CHMUX_t; +- +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Non-volatile Memory Controller */ +-typedef struct NVM_struct +-{ +- register8_t ADDR0; /* Address Register 0 */ +- register8_t ADDR1; /* Address Register 1 */ +- register8_t ADDR2; /* Address Register 2 */ +- register8_t reserved_0x03; +- register8_t DATA0; /* Data Register 0 */ +- register8_t DATA1; /* Data Register 1 */ +- register8_t DATA2; /* Data Register 2 */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t CMD; /* Command */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t INTCTRL; /* Interrupt Control */ +- register8_t reserved_0x0E; +- register8_t STATUS; /* Status */ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Lock Bits */ +-typedef struct NVM_LOCKBITS_struct +-{ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_LOCKBITS_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Fuses */ +-typedef struct NVM_FUSES_struct +-{ +- register8_t FUSEBYTE0; /* User ID */ +- register8_t FUSEBYTE1; /* Watchdog Configuration */ +- register8_t FUSEBYTE2; /* Reset Configuration */ +- register8_t reserved_0x03; +- register8_t FUSEBYTE4; /* Start-up Configuration */ +- register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +-} NVM_FUSES_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Production Signatures */ +-typedef struct NVM_PROD_SIGNATURES_struct +-{ +- register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ +- register8_t reserved_0x01; +- register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ +- register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ +- register8_t reserved_0x04; +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ +- register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ +- register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ +- register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ +- register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ +- register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t WAFNUM; /* Wafer Number */ +- register8_t reserved_0x11; +- register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ +- register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ +- register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ +- register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ +- register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ +- register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ +- register8_t reserved_0x26; +- register8_t reserved_0x27; +- register8_t reserved_0x28; +- register8_t reserved_0x29; +- register8_t reserved_0x2A; +- register8_t reserved_0x2B; +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ +- register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ +- register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ +- register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ +- register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ +- register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- register8_t reserved_0x36; +- register8_t reserved_0x37; +- register8_t reserved_0x38; +- register8_t reserved_0x39; +- register8_t reserved_0x3A; +- register8_t reserved_0x3B; +- register8_t reserved_0x3C; +- register8_t reserved_0x3D; +- register8_t reserved_0x3E; +-} NVM_PROD_SIGNATURES_t; +- +-/* NVM Command */ +-typedef enum NVM_CMD_enum +-{ +- NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ +- NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ +- NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ +- NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ +- NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ +- NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ +- NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ +- NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ +- NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ +- NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ +- NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ +- NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ +- NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ +- NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ +- NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ +- NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ +- NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ +- NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ +- NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ +- NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ +- NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ +- NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ +- NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ +- NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ +- NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ +- NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +-} NVM_CMD_t; +- +-/* SPM ready interrupt level */ +-typedef enum NVM_SPMLVL_enum +-{ +- NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ +- NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ +- NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +-} NVM_SPMLVL_t; +- +-/* EEPROM ready interrupt level */ +-typedef enum NVM_EELVL_enum +-{ +- NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ +- NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ +- NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +-} NVM_EELVL_t; +- +-/* Boot lock bits - boot setcion */ +-typedef enum NVM_BLBB_enum +-{ +- NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +- NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ +- NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ +- NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +-} NVM_BLBB_t; +- +-/* Boot lock bits - application section */ +-typedef enum NVM_BLBA_enum +-{ +- NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +- NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ +- NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ +- NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +-} NVM_BLBA_t; +- +-/* Boot lock bits - application table section */ +-typedef enum NVM_BLBAT_enum +-{ +- NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +- NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ +- NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ +- NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +-} NVM_BLBAT_t; +- +-/* Lock bits */ +-typedef enum NVM_LB_enum +-{ +- NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +- NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ +- NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +-} NVM_LB_t; +- +-/* Boot Loader Section Reset Vector */ +-typedef enum BOOTRST_enum +-{ +- BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ +- BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +-} BOOTRST_t; +- +-/* BOD operation */ +-typedef enum BOD_enum +-{ +- BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ +- BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ +- BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +-} BOD_t; +- +-/* Watchdog (Window) Timeout Period */ +-typedef enum WD_enum +-{ +- WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ +- WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ +- WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ +- WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ +- WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ +- WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ +- WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ +- WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ +- WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ +- WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ +- WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +-} WD_t; +- +-/* Start-up Time */ +-typedef enum SUT_enum +-{ +- SUT_0MS_gc = (0x03<<2), /* 0 ms */ +- SUT_4MS_gc = (0x01<<2), /* 4 ms */ +- SUT_64MS_gc = (0x00<<2), /* 64 ms */ +-} SUT_t; +- +-/* Brown Out Detection Voltage Level */ +-typedef enum BODLVL_enum +-{ +- BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ +- BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ +- BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ +- BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ +- BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ +- BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ +- BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ +-} BODLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-AC - Analog Comparator +--------------------------------------------------------------------------- +-*/ +- +-/* Analog Comparator */ +-typedef struct AC_struct +-{ +- register8_t AC0CTRL; /* Comparator 0 Control */ +- register8_t AC1CTRL; /* Comparator 1 Control */ +- register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ +- register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t WINCTRL; /* Window Mode Control */ +- register8_t STATUS; /* Status */ +-} AC_t; +- +-/* Interrupt mode */ +-typedef enum AC_INTMODE_enum +-{ +- AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ +- AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ +- AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +-} AC_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum AC_INTLVL_enum +-{ +- AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ +- AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ +- AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ +- AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +-} AC_INTLVL_t; +- +-/* Hysteresis mode selection */ +-typedef enum AC_HYSMODE_enum +-{ +- AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ +- AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ +- AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +-} AC_HYSMODE_t; +- +-/* Positive input multiplexer selection */ +-typedef enum AC_MUXPOS_enum +-{ +- AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ +- AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ +- AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ +- AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ +- AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ +- AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ +- AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +- AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +-} AC_MUXPOS_t; +- +-/* Negative input multiplexer selection */ +-typedef enum AC_MUXNEG_enum +-{ +- AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ +- AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ +- AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ +- AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ +- AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ +- AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ +- AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ +- AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +-} AC_MUXNEG_t; +- +-/* Windows interrupt mode */ +-typedef enum AC_WINTMODE_enum +-{ +- AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ +- AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ +- AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ +- AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +-} AC_WINTMODE_t; +- +-/* Window interrupt level */ +-typedef enum AC_WINTLVL_enum +-{ +- AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ +- AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ +- AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +-} AC_WINTLVL_t; +- +-/* Window mode state */ +-typedef enum AC_WSTATE_enum +-{ +- AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ +- AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ +- AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +-} AC_WSTATE_t; +- +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* ADC Channel */ +-typedef struct ADC_CH_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t MUXCTRL; /* MUX Control */ +- register8_t INTCTRL; /* Channel Interrupt Control */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- _WORDREGISTER(RES); /* Channel Result */ +- register8_t reserved_0x6; +- register8_t reserved_0x7; +-} ADC_CH_t; +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Analog-to-Digital Converter */ +-typedef struct ADC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t REFCTRL; /* Reference Control */ +- register8_t EVCTRL; /* Event Control */ +- register8_t PRESCALER; /* Clock Prescaler */ +- register8_t reserved_0x05; +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- _WORDREGISTER(CAL); /* Calibration Value */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- _WORDREGISTER(CH0RES); /* Channel 0 Result */ +- _WORDREGISTER(CH1RES); /* Channel 1 Result */ +- _WORDREGISTER(CH2RES); /* Channel 2 Result */ +- _WORDREGISTER(CH3RES); /* Channel 3 Result */ +- _WORDREGISTER(CMP); /* Compare Value */ +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- ADC_CH_t CH0; /* ADC Channel 0 */ +- ADC_CH_t CH1; /* ADC Channel 1 */ +- ADC_CH_t CH2; /* ADC Channel 2 */ +- ADC_CH_t CH3; /* ADC Channel 3 */ +-} ADC_t; +- +-/* Positive input multiplexer selection */ +-typedef enum ADC_CH_MUXPOS_enum +-{ +- ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ +- ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ +- ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ +- ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ +- ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ +- ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ +- ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ +- ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +-} ADC_CH_MUXPOS_t; +- +-/* Internal input multiplexer selections */ +-typedef enum ADC_CH_MUXINT_enum +-{ +- ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ +- ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ +- ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +- ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +-} ADC_CH_MUXINT_t; +- +-/* Negative input multiplexer selection */ +-typedef enum ADC_CH_MUXNEG_enum +-{ +- ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ +- ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ +- ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ +- ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ +- ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ +- ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ +- ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ +- ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +-} ADC_CH_MUXNEG_t; +- +-/* Input mode */ +-typedef enum ADC_CH_INPUTMODE_enum +-{ +- ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ +- ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ +- ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ +- ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +-} ADC_CH_INPUTMODE_t; +- +-/* Gain factor */ +-typedef enum ADC_CH_GAIN_enum +-{ +- ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ +- ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ +- ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ +- ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ +- ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ +- ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ +- ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ +-} ADC_CH_GAIN_t; +- +-/* Conversion result resolution */ +-typedef enum ADC_RESOLUTION_enum +-{ +- ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ +- ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ +- ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +-} ADC_RESOLUTION_t; +- +-/* Voltage reference selection */ +-typedef enum ADC_REFSEL_enum +-{ +- ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ +- ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ +- ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ +- ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +-} ADC_REFSEL_t; +- +-/* Channel sweep selection */ +-typedef enum ADC_SWEEP_enum +-{ +- ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ +- ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ +- ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ +- ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +-} ADC_SWEEP_t; +- +-/* Event channel input selection */ +-typedef enum ADC_EVSEL_enum +-{ +- ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ +- ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ +- ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ +- ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ +- ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ +- ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ +- ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ +- ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +-} ADC_EVSEL_t; +- +-/* Event action selection */ +-typedef enum ADC_EVACT_enum +-{ +- ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ +- ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ +- ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ +- ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ +- ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ +- ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ +- ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ +-} ADC_EVACT_t; +- +-/* Interupt mode */ +-typedef enum ADC_CH_INTMODE_enum +-{ +- ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ +- ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ +- ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +-} ADC_CH_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum ADC_CH_INTLVL_enum +-{ +- ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ +- ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ +- ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +-} ADC_CH_INTLVL_t; +- +-/* DMA request selection */ +-typedef enum ADC_DMASEL_enum +-{ +- ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ +- ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ +- ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ +- ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +-} ADC_DMASEL_t; +- +-/* Clock prescaler */ +-typedef enum ADC_PRESCALER_enum +-{ +- ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ +- ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ +- ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ +- ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ +- ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ +- ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ +- ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ +- ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +-} ADC_PRESCALER_t; +- +- +-/* +--------------------------------------------------------------------------- +-DAC - Digital/Analog Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Digital-to-Analog Converter */ +-typedef struct DAC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t EVCTRL; /* Event Input Control */ +- register8_t TIMCTRL; /* Timing Control */ +- register8_t STATUS; /* Status */ +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t GAINCAL; /* Gain Calibration */ +- register8_t OFFSETCAL; /* Offset Calibration */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- _WORDREGISTER(CH0DATA); /* Channel 0 Data */ +- _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +-} DAC_t; +- +-/* Output channel selection */ +-typedef enum DAC_CHSEL_enum +-{ +- DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ +- DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ +-} DAC_CHSEL_t; +- +-/* Reference voltage selection */ +-typedef enum DAC_REFSEL_enum +-{ +- DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ +- DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ +- DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ +- DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +-} DAC_REFSEL_t; +- +-/* Event channel selection */ +-typedef enum DAC_EVSEL_enum +-{ +- DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ +- DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ +- DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ +- DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ +- DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ +- DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ +- DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ +- DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +-} DAC_EVSEL_t; +- +-/* Conversion interval */ +-typedef enum DAC_CONINTVAL_enum +-{ +- DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ +- DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ +- DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ +- DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ +- DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ +- DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ +- DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ +- DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ +-} DAC_CONINTVAL_t; +- +-/* Refresh rate */ +-typedef enum DAC_REFRESH_enum +-{ +- DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ +- DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ +- DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ +- DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ +- DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ +- DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ +- DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ +- DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ +- DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ +- DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ +- DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ +- DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ +- DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ +- DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ +-} DAC_REFRESH_t; +- +- +-/* +--------------------------------------------------------------------------- +-RTC - Real-Time Clounter +--------------------------------------------------------------------------- +-*/ +- +-/* Real-Time Counter */ +-typedef struct RTC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t TEMP; /* Temporary register */ +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- _WORDREGISTER(CNT); /* Count Register */ +- _WORDREGISTER(PER); /* Period Register */ +- _WORDREGISTER(COMP); /* Compare Register */ +-} RTC_t; +- +-/* Prescaler Factor */ +-typedef enum RTC_PRESCALER_enum +-{ +- RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ +- RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ +- RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ +- RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ +- RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ +- RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ +- RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ +- RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +-} RTC_PRESCALER_t; +- +-/* Compare Interrupt level */ +-typedef enum RTC_COMPINTLVL_enum +-{ +- RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} RTC_COMPINTLVL_t; +- +-/* Overflow Interrupt level */ +-typedef enum RTC_OVFINTLVL_enum +-{ +- RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} RTC_OVFINTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* EBI Chip Select Module */ +-typedef struct EBI_CS_struct +-{ +- register8_t CTRLA; /* Chip Select Control Register A */ +- register8_t CTRLB; /* Chip Select Control Register B */ +- _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +-} EBI_CS_t; +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* External Bus Interface */ +-typedef struct EBI_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t SDRAMCTRLA; /* SDRAM Control Register A */ +- register8_t reserved_0x02; +- register8_t reserved_0x03; +- _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ +- _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ +- register8_t SDRAMCTRLB; /* SDRAM Control Register B */ +- register8_t SDRAMCTRLC; /* SDRAM Control Register C */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- EBI_CS_t CS0; /* Chip Select 0 */ +- EBI_CS_t CS1; /* Chip Select 1 */ +- EBI_CS_t CS2; /* Chip Select 2 */ +- EBI_CS_t CS3; /* Chip Select 3 */ +-} EBI_t; +- +-/* Chip Select adress space */ +-typedef enum EBI_CS_ASIZE_enum +-{ +- EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ +- EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ +- EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ +- EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ +- EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ +- EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ +- EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ +- EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ +- EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ +- EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ +- EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ +- EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ +- EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ +- EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ +- EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ +- EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ +- EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +-} EBI_CS_ASIZE_t; +- +-/* */ +-typedef enum EBI_CS_SRWS_enum +-{ +- EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_CS_SRWS_t; +- +-/* Chip Select address mode */ +-typedef enum EBI_CS_MODE_enum +-{ +- EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ +- EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ +- EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ +- EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +-} EBI_CS_MODE_t; +- +-/* Chip Select SDRAM mode */ +-typedef enum EBI_CS_SDMODE_enum +-{ +- EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ +- EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +-} EBI_CS_SDMODE_t; +- +-/* */ +-typedef enum EBI_SDDATAW_enum +-{ +- EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ +- EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +-} EBI_SDDATAW_t; +- +-/* */ +-typedef enum EBI_LPCMODE_enum +-{ +- EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ +- EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +-} EBI_LPCMODE_t; +- +-/* */ +-typedef enum EBI_SRMODE_enum +-{ +- EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ +- EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ +- EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ +- EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +-} EBI_SRMODE_t; +- +-/* */ +-typedef enum EBI_IFMODE_enum +-{ +- EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ +- EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ +- EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ +- EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +-} EBI_IFMODE_t; +- +-/* */ +-typedef enum EBI_SDCOL_enum +-{ +- EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ +- EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ +- EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ +- EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +-} EBI_SDCOL_t; +- +-/* */ +-typedef enum EBI_MRDLY_enum +-{ +- EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_MRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCYCDLY_enum +-{ +- EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ROWCYCDLY_t; +- +-/* */ +-typedef enum EBI_RPDLY_enum +-{ +- EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_RPDLY_t; +- +-/* */ +-typedef enum EBI_WRDLY_enum +-{ +- EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_WRDLY_t; +- +-/* */ +-typedef enum EBI_ESRDLY_enum +-{ +- EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ESRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCOLDLY_enum +-{ +- EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_ROWCOLDLY_t; +- +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_MASTER_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t STATUS; /* Status Register */ +- register8_t BAUD; /* Baurd Rate Control Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +-} TWI_MASTER_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_SLAVE_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t STATUS; /* Status Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +- register8_t ADDRMASK; /* Address Mask Register */ +-} TWI_SLAVE_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Two-Wire Interface */ +-typedef struct TWI_struct +-{ +- register8_t CTRL; /* TWI Common Control Register */ +- TWI_MASTER_t MASTER; /* TWI master module */ +- TWI_SLAVE_t SLAVE; /* TWI slave module */ +-} TWI_t; +- +-/* Master Interrupt Level */ +-typedef enum TWI_MASTER_INTLVL_enum +-{ +- TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_MASTER_INTLVL_t; +- +-/* Inactive Timeout */ +-typedef enum TWI_MASTER_TIMEOUT_enum +-{ +- TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ +- TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ +- TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ +- TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +-} TWI_MASTER_TIMEOUT_t; +- +-/* Master Command */ +-typedef enum TWI_MASTER_CMD_enum +-{ +- TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ +- TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ +- TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +-} TWI_MASTER_CMD_t; +- +-/* Master Bus State */ +-typedef enum TWI_MASTER_BUSSTATE_enum +-{ +- TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ +- TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ +- TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ +- TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +-} TWI_MASTER_BUSSTATE_t; +- +-/* Slave Interrupt Level */ +-typedef enum TWI_SLAVE_INTLVL_enum +-{ +- TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_SLAVE_INTLVL_t; +- +-/* Slave Command */ +-typedef enum TWI_SLAVE_CMD_enum +-{ +- TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ +- TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +-} TWI_SLAVE_CMD_t; +- +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O port Configuration */ +-typedef struct PORTCFG_struct +-{ +- register8_t MPCMASK; /* Multi-pin Configuration Mask */ +- register8_t reserved_0x01; +- register8_t VPCTRLA; /* Virtual Port Control Register A */ +- register8_t VPCTRLB; /* Virtual Port Control Register B */ +- register8_t CLKEVOUT; /* Clock and Event Out Register */ +-} PORTCFG_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* Virtual Port */ +-typedef struct VPORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t OUT; /* I/O Port Output */ +- register8_t IN; /* I/O Port Input */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +-} VPORT_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O Ports */ +-typedef struct PORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t DIRSET; /* I/O Port Data Direction Set */ +- register8_t DIRCLR; /* I/O Port Data Direction Clear */ +- register8_t DIRTGL; /* I/O Port Data Direction Toggle */ +- register8_t OUT; /* I/O Port Output */ +- register8_t OUTSET; /* I/O Port Output Set */ +- register8_t OUTCLR; /* I/O Port Output Clear */ +- register8_t OUTTGL; /* I/O Port Output Toggle */ +- register8_t IN; /* I/O port Input */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INT0MASK; /* Port Interrupt 0 Mask */ +- register8_t INT1MASK; /* Port Interrupt 1 Mask */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t PIN0CTRL; /* Pin 0 Control Register */ +- register8_t PIN1CTRL; /* Pin 1 Control Register */ +- register8_t PIN2CTRL; /* Pin 2 Control Register */ +- register8_t PIN3CTRL; /* Pin 3 Control Register */ +- register8_t PIN4CTRL; /* Pin 4 Control Register */ +- register8_t PIN5CTRL; /* Pin 5 Control Register */ +- register8_t PIN6CTRL; /* Pin 6 Control Register */ +- register8_t PIN7CTRL; /* Pin 7 Control Register */ +-} PORT_t; +- +-/* Virtual Port 0 Mapping */ +-typedef enum PORTCFG_VP0MAP_enum +-{ +- PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP0MAP_t; +- +-/* Virtual Port 1 Mapping */ +-typedef enum PORTCFG_VP1MAP_enum +-{ +- PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP1MAP_t; +- +-/* Virtual Port 2 Mapping */ +-typedef enum PORTCFG_VP2MAP_enum +-{ +- PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP2MAP_t; +- +-/* Virtual Port 3 Mapping */ +-typedef enum PORTCFG_VP3MAP_enum +-{ +- PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP3MAP_t; +- +-/* Clock Output Port */ +-typedef enum PORTCFG_CLKOUT_enum +-{ +- PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ +- PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ +- PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ +- PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +-} PORTCFG_CLKOUT_t; +- +-/* Event Output Port */ +-typedef enum PORTCFG_EVOUT_enum +-{ +- PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ +- PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ +- PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ +- PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +-} PORTCFG_EVOUT_t; +- +-/* Port Interrupt 0 Level */ +-typedef enum PORT_INT0LVL_enum +-{ +- PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ +- PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ +- PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +-} PORT_INT0LVL_t; +- +-/* Port Interrupt 1 Level */ +-typedef enum PORT_INT1LVL_enum +-{ +- PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ +- PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ +- PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +-} PORT_INT1LVL_t; +- +-/* Output/Pull Configuration */ +-typedef enum PORT_OPC_enum +-{ +- PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ +- PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ +- PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ +- PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ +- PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ +- PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ +- PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ +- PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +-} PORT_OPC_t; +- +-/* Input/Sense Configuration */ +-typedef enum PORT_ISC_enum +-{ +- PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ +- PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ +- PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ +- PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ +- PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +-} PORT_ISC_t; +- +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 0 */ +-typedef struct TC0_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- _WORDREGISTER(CCC); /* Compare or Capture C */ +- _WORDREGISTER(CCD); /* Compare or Capture D */ +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +- _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ +- _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +-} TC0_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 1 */ +-typedef struct TC1_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t reserved_0x2E; +- register8_t reserved_0x2F; +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +-} TC1_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* Advanced Waveform Extension */ +-typedef struct AWEX_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t FDEMASK; /* Fault Detection Event Mask */ +- register8_t FDCTRL; /* Fault Detection Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x05; +- register8_t DTBOTH; /* Dead Time Both Sides */ +- register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ +- register8_t DTLS; /* Dead Time Low Side */ +- register8_t DTHS; /* Dead Time High Side */ +- register8_t DTLSBUF; /* Dead Time Low Side Buffer */ +- register8_t DTHSBUF; /* Dead Time High Side Buffer */ +- register8_t OUTOVEN; /* Output Override Enable */ +-} AWEX_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* High-Resolution Extension */ +-typedef struct HIRES_struct +-{ +- register8_t CTRLA; /* Control Register */ +-} HIRES_t; +- +-/* Clock Selection */ +-typedef enum TC_CLKSEL_enum +-{ +- TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ +- TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ +- TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ +- TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ +- TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ +- TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ +- TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ +- TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ +- TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_CLKSEL_t; +- +-/* Waveform Generation Mode */ +-typedef enum TC_WGMODE_enum +-{ +- TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ +- TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ +- TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ +- TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ +- TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ +- TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +-} TC_WGMODE_t; +- +-/* Event Action */ +-typedef enum TC_EVACT_enum +-{ +- TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ +- TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ +- TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ +- TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ +- TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ +- TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */ +- TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +-} TC_EVACT_t; +- +-/* Event Selection */ +-typedef enum TC_EVSEL_enum +-{ +- TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_EVSEL_t; +- +-/* Error Interrupt Level */ +-typedef enum TC_ERRINTLVL_enum +-{ +- TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_ERRINTLVL_t; +- +-/* Overflow Interrupt Level */ +-typedef enum TC_OVFINTLVL_enum +-{ +- TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_OVFINTLVL_t; +- +-/* Compare or Capture D Interrupt Level */ +-typedef enum TC_CCDINTLVL_enum +-{ +- TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TC_CCDINTLVL_t; +- +-/* Compare or Capture C Interrupt Level */ +-typedef enum TC_CCCINTLVL_enum +-{ +- TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} TC_CCCINTLVL_t; +- +-/* Compare or Capture B Interrupt Level */ +-typedef enum TC_CCBINTLVL_enum +-{ +- TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_CCBINTLVL_t; +- +-/* Compare or Capture A Interrupt Level */ +-typedef enum TC_CCAINTLVL_enum +-{ +- TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_CCAINTLVL_t; +- +-/* Timer/Counter Command */ +-typedef enum TC_CMD_enum +-{ +- TC_CMD_NONE_gc = (0x00<<2), /* No Command */ +- TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ +- TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ +- TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +-} TC_CMD_t; +- +-/* Fault Detect Action */ +-typedef enum AWEX_FDACT_enum +-{ +- AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ +- AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ +- AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +-} AWEX_FDACT_t; +- +-/* High Resolution Enable */ +-typedef enum HIRES_HREN_enum +-{ +- HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ +- HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ +- HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ +- HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +-} HIRES_HREN_t; +- +- +-/* +--------------------------------------------------------------------------- +-USART - Universal Asynchronous Receiver-Transmitter +--------------------------------------------------------------------------- +-*/ +- +-/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +-typedef struct USART_struct +-{ +- register8_t DATA; /* Data Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x02; +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t BAUDCTRLA; /* Baud Rate Control Register A */ +- register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +-} USART_t; +- +-/* Receive Complete Interrupt level */ +-typedef enum USART_RXCINTLVL_enum +-{ +- USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} USART_RXCINTLVL_t; +- +-/* Transmit Complete Interrupt level */ +-typedef enum USART_TXCINTLVL_enum +-{ +- USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} USART_TXCINTLVL_t; +- +-/* Data Register Empty Interrupt level */ +-typedef enum USART_DREINTLVL_enum +-{ +- USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} USART_DREINTLVL_t; +- +-/* Character Size */ +-typedef enum USART_CHSIZE_enum +-{ +- USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ +- USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ +- USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ +- USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ +- USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +-} USART_CHSIZE_t; +- +-/* Communication Mode */ +-typedef enum USART_CMODE_enum +-{ +- USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ +- USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ +- USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ +- USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +-} USART_CMODE_t; +- +-/* Parity Mode */ +-typedef enum USART_PMODE_enum +-{ +- USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ +- USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ +- USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +-} USART_PMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-SPI - Serial Peripheral Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Serial Peripheral Interface */ +-typedef struct SPI_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t DATA; /* Data Register */ +-} SPI_t; +- +-/* SPI Mode */ +-typedef enum SPI_MODE_enum +-{ +- SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ +- SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ +- SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ +- SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +-} SPI_MODE_t; +- +-/* Prescaler setting */ +-typedef enum SPI_PRESCALER_enum +-{ +- SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ +- SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ +- SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ +- SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +-} SPI_PRESCALER_t; +- +-/* Interrupt level */ +-typedef enum SPI_INTLVL_enum +-{ +- SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} SPI_INTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-IRCOM - IR Communication Module +--------------------------------------------------------------------------- +-*/ +- +-/* IR Communication Module */ +-typedef struct IRCOM_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ +- register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +-} IRCOM_t; +- +-/* Event channel selection */ +-typedef enum IRDA_EVSEL_enum +-{ +- IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ +- IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ +- IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ +- IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +- IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ +- IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ +- IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ +- IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +-} IRDA_EVSEL_t; +- +- +-/* +--------------------------------------------------------------------------- +-AES - AES Module +--------------------------------------------------------------------------- +-*/ +- +-/* AES Module */ +-typedef struct AES_struct +-{ +- register8_t CTRL; /* AES Control Register */ +- register8_t STATUS; /* AES Status Register */ +- register8_t STATE; /* AES State Register */ +- register8_t KEY; /* AES Key Register */ +- register8_t INTCTRL; /* AES Interrupt Control Register */ +-} AES_t; +- +-/* Interrupt level */ +-typedef enum AES_INTLVL_enum +-{ +- AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} AES_INTLVL_t; +- +- +- +-/* +-========================================================================== +-IO Module Instances. Mapped to memory. +-========================================================================== +-*/ +- +-#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +-#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +-#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +-#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +-#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +-#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +-#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +-#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +-#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +-#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +-#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +-#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +-#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +-#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +-#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +-#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +-#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ +-#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +-#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +-#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +-#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +-#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ +-#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +-#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +-#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +-#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ +-#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +-#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +-#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +-#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +-#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +-#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +-#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +-#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +-#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +-#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +-#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +-#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ +-#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +-#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +-#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +-#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ +-#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ +-#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +-#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ +-#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +-#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +-#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ +-#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ +- +- +-#endif /* !defined (__ASSEMBLER__) */ +- +- +-/* ========== Flattened fully qualified IO register names ========== */ +- +-/* GPIO - General Purpose IO Registers */ +-#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +-#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +-#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +-#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +-#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +-#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +-#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +-#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +-#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +-#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +-#define GPIO_GPIORA _SFR_MEM8(0x000A) +-#define GPIO_GPIORB _SFR_MEM8(0x000B) +-#define GPIO_GPIORC _SFR_MEM8(0x000C) +-#define GPIO_GPIORD _SFR_MEM8(0x000D) +-#define GPIO_GPIORE _SFR_MEM8(0x000E) +-#define GPIO_GPIORF _SFR_MEM8(0x000F) +- +-/* Deprecated */ +-#define GPIO_GPIO0 _SFR_MEM8(0x0000) +-#define GPIO_GPIO1 _SFR_MEM8(0x0001) +-#define GPIO_GPIO2 _SFR_MEM8(0x0002) +-#define GPIO_GPIO3 _SFR_MEM8(0x0003) +-#define GPIO_GPIO4 _SFR_MEM8(0x0004) +-#define GPIO_GPIO5 _SFR_MEM8(0x0005) +-#define GPIO_GPIO6 _SFR_MEM8(0x0006) +-#define GPIO_GPIO7 _SFR_MEM8(0x0007) +-#define GPIO_GPIO8 _SFR_MEM8(0x0008) +-#define GPIO_GPIO9 _SFR_MEM8(0x0009) +-#define GPIO_GPIOA _SFR_MEM8(0x000A) +-#define GPIO_GPIOB _SFR_MEM8(0x000B) +-#define GPIO_GPIOC _SFR_MEM8(0x000C) +-#define GPIO_GPIOD _SFR_MEM8(0x000D) +-#define GPIO_GPIOE _SFR_MEM8(0x000E) +-#define GPIO_GPIOF _SFR_MEM8(0x000F) +- +-/* VPORT0 - Virtual Port 0 */ +-#define VPORT0_DIR _SFR_MEM8(0x0010) +-#define VPORT0_OUT _SFR_MEM8(0x0011) +-#define VPORT0_IN _SFR_MEM8(0x0012) +-#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) +- +-/* VPORT1 - Virtual Port 1 */ +-#define VPORT1_DIR _SFR_MEM8(0x0014) +-#define VPORT1_OUT _SFR_MEM8(0x0015) +-#define VPORT1_IN _SFR_MEM8(0x0016) +-#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) +- +-/* VPORT2 - Virtual Port 2 */ +-#define VPORT2_DIR _SFR_MEM8(0x0018) +-#define VPORT2_OUT _SFR_MEM8(0x0019) +-#define VPORT2_IN _SFR_MEM8(0x001A) +-#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) +- +-/* VPORT3 - Virtual Port 3 */ +-#define VPORT3_DIR _SFR_MEM8(0x001C) +-#define VPORT3_OUT _SFR_MEM8(0x001D) +-#define VPORT3_IN _SFR_MEM8(0x001E) +-#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) +- +-/* OCD - On-Chip Debug System */ +-#define OCD_OCDR0 _SFR_MEM8(0x002E) +-#define OCD_OCDR1 _SFR_MEM8(0x002F) +- +-/* CPU - CPU Registers */ +-#define CPU_CCP _SFR_MEM8(0x0034) +-#define CPU_RAMPD _SFR_MEM8(0x0038) +-#define CPU_RAMPX _SFR_MEM8(0x0039) +-#define CPU_RAMPY _SFR_MEM8(0x003A) +-#define CPU_RAMPZ _SFR_MEM8(0x003B) +-#define CPU_EIND _SFR_MEM8(0x003C) +-#define CPU_SPL _SFR_MEM8(0x003D) +-#define CPU_SPH _SFR_MEM8(0x003E) +-#define CPU_SREG _SFR_MEM8(0x003F) +- +-/* CLK - Clock System */ +-#define CLK_CTRL _SFR_MEM8(0x0040) +-#define CLK_PSCTRL _SFR_MEM8(0x0041) +-#define CLK_LOCK _SFR_MEM8(0x0042) +-#define CLK_RTCCTRL _SFR_MEM8(0x0043) +- +-/* SLEEP - Sleep Controller */ +-#define SLEEP_CTRL _SFR_MEM8(0x0048) +- +-/* OSC - Oscillator Control */ +-#define OSC_CTRL _SFR_MEM8(0x0050) +-#define OSC_STATUS _SFR_MEM8(0x0051) +-#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +-#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +-#define OSC_RC32KCAL _SFR_MEM8(0x0054) +-#define OSC_PLLCTRL _SFR_MEM8(0x0055) +-#define OSC_DFLLCTRL _SFR_MEM8(0x0056) +- +-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +-#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +-#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +-#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +-#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +-#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +-#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) +- +-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +-#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +-#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +-#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +-#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +-#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +-#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) +- +-/* PR - Power Reduction */ +-#define PR_PRGEN _SFR_MEM8(0x0070) +-#define PR_PRPA _SFR_MEM8(0x0071) +-#define PR_PRPB _SFR_MEM8(0x0072) +-#define PR_PRPC _SFR_MEM8(0x0073) +-#define PR_PRPD _SFR_MEM8(0x0074) +-#define PR_PRPE _SFR_MEM8(0x0075) +-#define PR_PRPF _SFR_MEM8(0x0076) +- +-/* RST - Reset Controller */ +-#define RST_STATUS _SFR_MEM8(0x0078) +-#define RST_CTRL _SFR_MEM8(0x0079) +- +-/* WDT - Watch-Dog Timer */ +-#define WDT_CTRL _SFR_MEM8(0x0080) +-#define WDT_WINCTRL _SFR_MEM8(0x0081) +-#define WDT_STATUS _SFR_MEM8(0x0082) +- +-/* MCU - MCU Control */ +-#define MCU_DEVID0 _SFR_MEM8(0x0090) +-#define MCU_DEVID1 _SFR_MEM8(0x0091) +-#define MCU_DEVID2 _SFR_MEM8(0x0092) +-#define MCU_REVID _SFR_MEM8(0x0093) +-#define MCU_JTAGUID _SFR_MEM8(0x0094) +-#define MCU_MCUCR _SFR_MEM8(0x0096) +-#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +-#define MCU_AWEXLOCK _SFR_MEM8(0x0099) +- +-/* PMIC - Programmable Interrupt Controller */ +-#define PMIC_STATUS _SFR_MEM8(0x00A0) +-#define PMIC_INTPRI _SFR_MEM8(0x00A1) +-#define PMIC_CTRL _SFR_MEM8(0x00A2) +- +-/* PORTCFG - Port Configuration */ +-#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +-#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +-#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +-#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +- +-/* AES - AES Crypto Module */ +-#define AES_CTRL _SFR_MEM8(0x00C0) +-#define AES_STATUS _SFR_MEM8(0x00C1) +-#define AES_STATE _SFR_MEM8(0x00C2) +-#define AES_KEY _SFR_MEM8(0x00C3) +-#define AES_INTCTRL _SFR_MEM8(0x00C4) +- +-/* DMA - DMA Controller */ +-#define DMA_CTRL _SFR_MEM8(0x0100) +-#define DMA_INTFLAGS _SFR_MEM8(0x0103) +-#define DMA_STATUS _SFR_MEM8(0x0104) +-#define DMA_TEMP _SFR_MEM16(0x0106) +-#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +-#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +-#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +-#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +-#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +-#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +-#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +-#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +-#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +-#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +-#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +-#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +-#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +-#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +-#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +-#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +-#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +-#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +-#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +-#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +-#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +-#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +-#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +-#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +-#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +-#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +-#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +-#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +-#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +-#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +-#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +-#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +-#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +-#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +-#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +-#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +-#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +-#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +-#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +-#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +-#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +-#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +-#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +-#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +-#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +-#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +-#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +-#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) +- +-/* EVSYS - Event System */ +-#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +-#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +-#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +-#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +-#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +-#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +-#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +-#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +-#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +-#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +-#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +-#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +-#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +-#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +-#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +-#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +-#define EVSYS_STROBE _SFR_MEM8(0x0190) +-#define EVSYS_DATA _SFR_MEM8(0x0191) +- +-/* NVM - Non Volatile Memory Controller */ +-#define NVM_ADDR0 _SFR_MEM8(0x01C0) +-#define NVM_ADDR1 _SFR_MEM8(0x01C1) +-#define NVM_ADDR2 _SFR_MEM8(0x01C2) +-#define NVM_DATA0 _SFR_MEM8(0x01C4) +-#define NVM_DATA1 _SFR_MEM8(0x01C5) +-#define NVM_DATA2 _SFR_MEM8(0x01C6) +-#define NVM_CMD _SFR_MEM8(0x01CA) +-#define NVM_CTRLA _SFR_MEM8(0x01CB) +-#define NVM_CTRLB _SFR_MEM8(0x01CC) +-#define NVM_INTCTRL _SFR_MEM8(0x01CD) +-#define NVM_STATUS _SFR_MEM8(0x01CF) +-#define NVM_LOCKBITS _SFR_MEM8(0x01D0) +- +-/* ADCA - Analog to Digital Converter A */ +-#define ADCA_CTRLA _SFR_MEM8(0x0200) +-#define ADCA_CTRLB _SFR_MEM8(0x0201) +-#define ADCA_REFCTRL _SFR_MEM8(0x0202) +-#define ADCA_EVCTRL _SFR_MEM8(0x0203) +-#define ADCA_PRESCALER _SFR_MEM8(0x0204) +-#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +-#define ADCA_CAL _SFR_MEM16(0x020C) +-#define ADCA_CH0RES _SFR_MEM16(0x0210) +-#define ADCA_CH1RES _SFR_MEM16(0x0212) +-#define ADCA_CH2RES _SFR_MEM16(0x0214) +-#define ADCA_CH3RES _SFR_MEM16(0x0216) +-#define ADCA_CMP _SFR_MEM16(0x0218) +-#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +-#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +-#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +-#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +-#define ADCA_CH0_RES _SFR_MEM16(0x0224) +-#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +-#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +-#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +-#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +-#define ADCA_CH1_RES _SFR_MEM16(0x022C) +-#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +-#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +-#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +-#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +-#define ADCA_CH2_RES _SFR_MEM16(0x0234) +-#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +-#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +-#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +-#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +-#define ADCA_CH3_RES _SFR_MEM16(0x023C) +- +-/* DACB - Digital to Analog Converter B */ +-#define DACB_CTRLA _SFR_MEM8(0x0320) +-#define DACB_CTRLB _SFR_MEM8(0x0321) +-#define DACB_CTRLC _SFR_MEM8(0x0322) +-#define DACB_EVCTRL _SFR_MEM8(0x0323) +-#define DACB_TIMCTRL _SFR_MEM8(0x0324) +-#define DACB_STATUS _SFR_MEM8(0x0325) +-#define DACB_GAINCAL _SFR_MEM8(0x0328) +-#define DACB_OFFSETCAL _SFR_MEM8(0x0329) +-#define DACB_CH0DATA _SFR_MEM16(0x0338) +-#define DACB_CH1DATA _SFR_MEM16(0x033A) +- +-/* ACA - Analog Comparator A */ +-#define ACA_AC0CTRL _SFR_MEM8(0x0380) +-#define ACA_AC1CTRL _SFR_MEM8(0x0381) +-#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +-#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +-#define ACA_CTRLA _SFR_MEM8(0x0384) +-#define ACA_CTRLB _SFR_MEM8(0x0385) +-#define ACA_WINCTRL _SFR_MEM8(0x0386) +-#define ACA_STATUS _SFR_MEM8(0x0387) +- +-/* RTC - Real-Time Counter */ +-#define RTC_CTRL _SFR_MEM8(0x0400) +-#define RTC_STATUS _SFR_MEM8(0x0401) +-#define RTC_INTCTRL _SFR_MEM8(0x0402) +-#define RTC_INTFLAGS _SFR_MEM8(0x0403) +-#define RTC_TEMP _SFR_MEM8(0x0404) +-#define RTC_CNT _SFR_MEM16(0x0408) +-#define RTC_PER _SFR_MEM16(0x040A) +-#define RTC_COMP _SFR_MEM16(0x040C) +- +-/* TWIC - Two-Wire Interface C */ +-#define TWIC_CTRL _SFR_MEM8(0x0480) +-#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +-#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +-#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +-#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +-#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +-#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +-#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +-#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +-#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +-#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +-#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +-#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +-#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) +- +-/* TWIE - Two-Wire Interface E */ +-#define TWIE_CTRL _SFR_MEM8(0x04A0) +-#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +-#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +-#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +-#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +-#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +-#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +-#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +-#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +-#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +-#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +-#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +-#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +-#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) +- +-/* PORTA - Port A */ +-#define PORTA_DIR _SFR_MEM8(0x0600) +-#define PORTA_DIRSET _SFR_MEM8(0x0601) +-#define PORTA_DIRCLR _SFR_MEM8(0x0602) +-#define PORTA_DIRTGL _SFR_MEM8(0x0603) +-#define PORTA_OUT _SFR_MEM8(0x0604) +-#define PORTA_OUTSET _SFR_MEM8(0x0605) +-#define PORTA_OUTCLR _SFR_MEM8(0x0606) +-#define PORTA_OUTTGL _SFR_MEM8(0x0607) +-#define PORTA_IN _SFR_MEM8(0x0608) +-#define PORTA_INTCTRL _SFR_MEM8(0x0609) +-#define PORTA_INT0MASK _SFR_MEM8(0x060A) +-#define PORTA_INT1MASK _SFR_MEM8(0x060B) +-#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +-#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +-#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +-#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +-#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +-#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +-#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +-#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +-#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) +- +-/* PORTB - Port B */ +-#define PORTB_DIR _SFR_MEM8(0x0620) +-#define PORTB_DIRSET _SFR_MEM8(0x0621) +-#define PORTB_DIRCLR _SFR_MEM8(0x0622) +-#define PORTB_DIRTGL _SFR_MEM8(0x0623) +-#define PORTB_OUT _SFR_MEM8(0x0624) +-#define PORTB_OUTSET _SFR_MEM8(0x0625) +-#define PORTB_OUTCLR _SFR_MEM8(0x0626) +-#define PORTB_OUTTGL _SFR_MEM8(0x0627) +-#define PORTB_IN _SFR_MEM8(0x0628) +-#define PORTB_INTCTRL _SFR_MEM8(0x0629) +-#define PORTB_INT0MASK _SFR_MEM8(0x062A) +-#define PORTB_INT1MASK _SFR_MEM8(0x062B) +-#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +-#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +-#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +-#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +-#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +-#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +-#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +-#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +-#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) +- +-/* PORTC - Port C */ +-#define PORTC_DIR _SFR_MEM8(0x0640) +-#define PORTC_DIRSET _SFR_MEM8(0x0641) +-#define PORTC_DIRCLR _SFR_MEM8(0x0642) +-#define PORTC_DIRTGL _SFR_MEM8(0x0643) +-#define PORTC_OUT _SFR_MEM8(0x0644) +-#define PORTC_OUTSET _SFR_MEM8(0x0645) +-#define PORTC_OUTCLR _SFR_MEM8(0x0646) +-#define PORTC_OUTTGL _SFR_MEM8(0x0647) +-#define PORTC_IN _SFR_MEM8(0x0648) +-#define PORTC_INTCTRL _SFR_MEM8(0x0649) +-#define PORTC_INT0MASK _SFR_MEM8(0x064A) +-#define PORTC_INT1MASK _SFR_MEM8(0x064B) +-#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +-#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +-#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +-#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +-#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +-#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +-#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +-#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +-#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) +- +-/* PORTD - Port D */ +-#define PORTD_DIR _SFR_MEM8(0x0660) +-#define PORTD_DIRSET _SFR_MEM8(0x0661) +-#define PORTD_DIRCLR _SFR_MEM8(0x0662) +-#define PORTD_DIRTGL _SFR_MEM8(0x0663) +-#define PORTD_OUT _SFR_MEM8(0x0664) +-#define PORTD_OUTSET _SFR_MEM8(0x0665) +-#define PORTD_OUTCLR _SFR_MEM8(0x0666) +-#define PORTD_OUTTGL _SFR_MEM8(0x0667) +-#define PORTD_IN _SFR_MEM8(0x0668) +-#define PORTD_INTCTRL _SFR_MEM8(0x0669) +-#define PORTD_INT0MASK _SFR_MEM8(0x066A) +-#define PORTD_INT1MASK _SFR_MEM8(0x066B) +-#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +-#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +-#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +-#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +-#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +-#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +-#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +-#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +-#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) +- +-/* PORTE - Port E */ +-#define PORTE_DIR _SFR_MEM8(0x0680) +-#define PORTE_DIRSET _SFR_MEM8(0x0681) +-#define PORTE_DIRCLR _SFR_MEM8(0x0682) +-#define PORTE_DIRTGL _SFR_MEM8(0x0683) +-#define PORTE_OUT _SFR_MEM8(0x0684) +-#define PORTE_OUTSET _SFR_MEM8(0x0685) +-#define PORTE_OUTCLR _SFR_MEM8(0x0686) +-#define PORTE_OUTTGL _SFR_MEM8(0x0687) +-#define PORTE_IN _SFR_MEM8(0x0688) +-#define PORTE_INTCTRL _SFR_MEM8(0x0689) +-#define PORTE_INT0MASK _SFR_MEM8(0x068A) +-#define PORTE_INT1MASK _SFR_MEM8(0x068B) +-#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +-#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +-#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +-#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +-#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +-#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +-#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +-#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +-#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) +- +-/* PORTR - Port R */ +-#define PORTR_DIR _SFR_MEM8(0x07E0) +-#define PORTR_DIRSET _SFR_MEM8(0x07E1) +-#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +-#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +-#define PORTR_OUT _SFR_MEM8(0x07E4) +-#define PORTR_OUTSET _SFR_MEM8(0x07E5) +-#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +-#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +-#define PORTR_IN _SFR_MEM8(0x07E8) +-#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +-#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +-#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +-#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +-#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +-#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +-#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +-#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +-#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +-#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +-#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +-#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) +- +-/* TCC0 - Timer/Counter C0 */ +-#define TCC0_CTRLA _SFR_MEM8(0x0800) +-#define TCC0_CTRLB _SFR_MEM8(0x0801) +-#define TCC0_CTRLC _SFR_MEM8(0x0802) +-#define TCC0_CTRLD _SFR_MEM8(0x0803) +-#define TCC0_CTRLE _SFR_MEM8(0x0804) +-#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +-#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +-#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +-#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +-#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +-#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +-#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +-#define TCC0_TEMP _SFR_MEM8(0x080F) +-#define TCC0_CNT _SFR_MEM16(0x0820) +-#define TCC0_PER _SFR_MEM16(0x0826) +-#define TCC0_CCA _SFR_MEM16(0x0828) +-#define TCC0_CCB _SFR_MEM16(0x082A) +-#define TCC0_CCC _SFR_MEM16(0x082C) +-#define TCC0_CCD _SFR_MEM16(0x082E) +-#define TCC0_PERBUF _SFR_MEM16(0x0836) +-#define TCC0_CCABUF _SFR_MEM16(0x0838) +-#define TCC0_CCBBUF _SFR_MEM16(0x083A) +-#define TCC0_CCCBUF _SFR_MEM16(0x083C) +-#define TCC0_CCDBUF _SFR_MEM16(0x083E) +- +-/* TCC1 - Timer/Counter C1 */ +-#define TCC1_CTRLA _SFR_MEM8(0x0840) +-#define TCC1_CTRLB _SFR_MEM8(0x0841) +-#define TCC1_CTRLC _SFR_MEM8(0x0842) +-#define TCC1_CTRLD _SFR_MEM8(0x0843) +-#define TCC1_CTRLE _SFR_MEM8(0x0844) +-#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +-#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +-#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +-#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +-#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +-#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +-#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +-#define TCC1_TEMP _SFR_MEM8(0x084F) +-#define TCC1_CNT _SFR_MEM16(0x0860) +-#define TCC1_PER _SFR_MEM16(0x0866) +-#define TCC1_CCA _SFR_MEM16(0x0868) +-#define TCC1_CCB _SFR_MEM16(0x086A) +-#define TCC1_PERBUF _SFR_MEM16(0x0876) +-#define TCC1_CCABUF _SFR_MEM16(0x0878) +-#define TCC1_CCBBUF _SFR_MEM16(0x087A) +- +-/* AWEXC - Advanced Waveform Extension C */ +-#define AWEXC_CTRL _SFR_MEM8(0x0880) +-#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +-#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +-#define AWEXC_STATUS _SFR_MEM8(0x0884) +-#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +-#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +-#define AWEXC_DTLS _SFR_MEM8(0x0888) +-#define AWEXC_DTHS _SFR_MEM8(0x0889) +-#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +-#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +-#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) +- +-/* HIRESC - High-Resolution Extension C */ +-#define HIRESC_CTRLA _SFR_MEM8(0x0890) +- +-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +-#define USARTC0_DATA _SFR_MEM8(0x08A0) +-#define USARTC0_STATUS _SFR_MEM8(0x08A1) +-#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +-#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +-#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +-#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +-#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) +- +-/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ +-#define USARTC1_DATA _SFR_MEM8(0x08B0) +-#define USARTC1_STATUS _SFR_MEM8(0x08B1) +-#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +-#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +-#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +-#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +-#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) +- +-/* SPIC - Serial Peripheral Interface C */ +-#define SPIC_CTRL _SFR_MEM8(0x08C0) +-#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +-#define SPIC_STATUS _SFR_MEM8(0x08C2) +-#define SPIC_DATA _SFR_MEM8(0x08C3) +- +-/* IRCOM - IR Communication Module */ +-#define IRCOM_CTRL _SFR_MEM8(0x08F8) +-#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +-#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) +- +-/* TCD0 - Timer/Counter D0 */ +-#define TCD0_CTRLA _SFR_MEM8(0x0900) +-#define TCD0_CTRLB _SFR_MEM8(0x0901) +-#define TCD0_CTRLC _SFR_MEM8(0x0902) +-#define TCD0_CTRLD _SFR_MEM8(0x0903) +-#define TCD0_CTRLE _SFR_MEM8(0x0904) +-#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +-#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +-#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +-#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +-#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +-#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +-#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +-#define TCD0_TEMP _SFR_MEM8(0x090F) +-#define TCD0_CNT _SFR_MEM16(0x0920) +-#define TCD0_PER _SFR_MEM16(0x0926) +-#define TCD0_CCA _SFR_MEM16(0x0928) +-#define TCD0_CCB _SFR_MEM16(0x092A) +-#define TCD0_CCC _SFR_MEM16(0x092C) +-#define TCD0_CCD _SFR_MEM16(0x092E) +-#define TCD0_PERBUF _SFR_MEM16(0x0936) +-#define TCD0_CCABUF _SFR_MEM16(0x0938) +-#define TCD0_CCBBUF _SFR_MEM16(0x093A) +-#define TCD0_CCCBUF _SFR_MEM16(0x093C) +-#define TCD0_CCDBUF _SFR_MEM16(0x093E) +- +-/* TCD1 - Timer/Counter D1 */ +-#define TCD1_CTRLA _SFR_MEM8(0x0940) +-#define TCD1_CTRLB _SFR_MEM8(0x0941) +-#define TCD1_CTRLC _SFR_MEM8(0x0942) +-#define TCD1_CTRLD _SFR_MEM8(0x0943) +-#define TCD1_CTRLE _SFR_MEM8(0x0944) +-#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +-#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +-#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +-#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +-#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +-#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +-#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +-#define TCD1_TEMP _SFR_MEM8(0x094F) +-#define TCD1_CNT _SFR_MEM16(0x0960) +-#define TCD1_PER _SFR_MEM16(0x0966) +-#define TCD1_CCA _SFR_MEM16(0x0968) +-#define TCD1_CCB _SFR_MEM16(0x096A) +-#define TCD1_PERBUF _SFR_MEM16(0x0976) +-#define TCD1_CCABUF _SFR_MEM16(0x0978) +-#define TCD1_CCBBUF _SFR_MEM16(0x097A) +- +-/* HIRESD - High-Resolution Extension D */ +-#define HIRESD_CTRLA _SFR_MEM8(0x0990) +- +-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +-#define USARTD0_DATA _SFR_MEM8(0x09A0) +-#define USARTD0_STATUS _SFR_MEM8(0x09A1) +-#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +-#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +-#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +-#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +-#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) +- +-/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ +-#define USARTD1_DATA _SFR_MEM8(0x09B0) +-#define USARTD1_STATUS _SFR_MEM8(0x09B1) +-#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +-#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +-#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +-#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +-#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) +- +-/* SPID - Serial Peripheral Interface D */ +-#define SPID_CTRL _SFR_MEM8(0x09C0) +-#define SPID_INTCTRL _SFR_MEM8(0x09C1) +-#define SPID_STATUS _SFR_MEM8(0x09C2) +-#define SPID_DATA _SFR_MEM8(0x09C3) +- +-/* TCE0 - Timer/Counter E0 */ +-#define TCE0_CTRLA _SFR_MEM8(0x0A00) +-#define TCE0_CTRLB _SFR_MEM8(0x0A01) +-#define TCE0_CTRLC _SFR_MEM8(0x0A02) +-#define TCE0_CTRLD _SFR_MEM8(0x0A03) +-#define TCE0_CTRLE _SFR_MEM8(0x0A04) +-#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +-#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +-#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +-#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +-#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +-#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +-#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +-#define TCE0_TEMP _SFR_MEM8(0x0A0F) +-#define TCE0_CNT _SFR_MEM16(0x0A20) +-#define TCE0_PER _SFR_MEM16(0x0A26) +-#define TCE0_CCA _SFR_MEM16(0x0A28) +-#define TCE0_CCB _SFR_MEM16(0x0A2A) +-#define TCE0_CCC _SFR_MEM16(0x0A2C) +-#define TCE0_CCD _SFR_MEM16(0x0A2E) +-#define TCE0_PERBUF _SFR_MEM16(0x0A36) +-#define TCE0_CCABUF _SFR_MEM16(0x0A38) +-#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +-#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +-#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) +- +-/* HIRESE - High-Resolution Extension E */ +-#define HIRESE_CTRLA _SFR_MEM8(0x0A90) +- +-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +-#define USARTE0_DATA _SFR_MEM8(0x0AA0) +-#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +-#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +-#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +-#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +-#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +-#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) +- +- +- +-/*================== Bitfield Definitions ================== */ +- +-/* XOCD - On-Chip Debug System */ +-/* OCD.OCDR1 bit masks and bit positions */ +-#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +-#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ +- +- +-/* CPU - CPU */ +-/* CPU.CCP bit masks and bit positions */ +-#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +-#define CPU_CCP_gp 0 /* CCP signature group position. */ +-#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +-#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +-#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +-#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +-#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +-#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +-#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +-#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +-#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +-#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +-#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +-#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +-#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +-#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +-#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +-#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ +- +- +-/* CPU.SREG bit masks and bit positions */ +-#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +-#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ +- +-#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +-#define CPU_T_bp 6 /* Transfer Bit bit position. */ +- +-#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +-#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +- +-#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +-#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +- +-#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +-#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +- +-#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +-#define CPU_N_bp 2 /* Negative Flag bit position. */ +- +-#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +-#define CPU_Z_bp 1 /* Zero Flag bit position. */ +- +-#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +-#define CPU_C_bp 0 /* Carry Flag bit position. */ +- +- +-/* CLK - Clock System */ +-/* CLK.CTRL bit masks and bit positions */ +-#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +-#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +-#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +-#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +-#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +-#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +-#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +-#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ +- +- +-/* CLK.PSCTRL bit masks and bit positions */ +-#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +-#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +-#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +-#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +-#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +-#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +-#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +-#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +-#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +-#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +-#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +-#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ +- +-#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +-#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +-#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +-#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +-#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +-#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ +- +- +-/* CLK.LOCK bit masks and bit positions */ +-#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +-#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ +- +- +-/* CLK.RTCCTRL bit masks and bit positions */ +-#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +-#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +-#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +-#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +-#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +-#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +-#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +-#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ +- +-#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +-#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ +- +- +-/* PR.PRGEN bit masks and bit positions */ +-#define PR_AES_bm 0x10 /* AES bit mask. */ +-#define PR_AES_bp 4 /* AES bit position. */ +- +-#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +-#define PR_EBI_bp 3 /* External Bus Interface bit position. */ +- +-#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +-#define PR_RTC_bp 2 /* Real-time Counter bit position. */ +- +-#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +-#define PR_EVSYS_bp 1 /* Event System bit position. */ +- +-#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +-#define PR_DMA_bp 0 /* DMA-Controller bit position. */ +- +- +-/* PR.PRPA bit masks and bit positions */ +-#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +-#define PR_DAC_bp 2 /* Port A DAC bit position. */ +- +-#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +-#define PR_ADC_bp 1 /* Port A ADC bit position. */ +- +-#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +-#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ +- +- +-/* PR.PRPB bit masks and bit positions */ +-/* PR_DAC_bm Predefined. */ +-/* PR_DAC_bp Predefined. */ +- +-/* PR_ADC_bm Predefined. */ +-/* PR_ADC_bp Predefined. */ +- +-/* PR_AC_bm Predefined. */ +-/* PR_AC_bp Predefined. */ +- +- +-/* PR.PRPC bit masks and bit positions */ +-#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +-#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ +- +-#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +-#define PR_USART1_bp 5 /* Port C USART1 bit position. */ +- +-#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +-#define PR_USART0_bp 4 /* Port C USART0 bit position. */ +- +-#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +-#define PR_SPI_bp 3 /* Port C SPI bit position. */ +- +-#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +-#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ +- +-#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +-#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ +- +-#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +-#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ +- +- +-/* PR.PRPD bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* PR.PRPE bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* PR.PRPF bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* SLEEP - Sleep Controller */ +-/* SLEEP.CTRL bit masks and bit positions */ +-#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +-#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +-#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +-#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +-#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +-#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +-#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +-#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ +- +-#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +-#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ +- +- +-/* OSC - Oscillator */ +-/* OSC.CTRL bit masks and bit positions */ +-#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +-#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ +- +-#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +-#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ +- +-#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ +- +- +-/* OSC.STATUS bit masks and bit positions */ +-#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +-#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ +- +-#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +-#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ +- +-#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ +- +- +-/* OSC.XOSCCTRL bit masks and bit positions */ +-#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +-#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +-#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +-#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +-#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +-#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ +- +-#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +-#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ +- +-#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +-#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +-#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +-#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +-#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +-#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +-#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +-#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +-#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +-#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +- +- +-/* OSC.XOSCFAIL bit masks and bit positions */ +-#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +-#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ +- +-#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +-#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ +- +- +-/* OSC.PLLCTRL bit masks and bit positions */ +-#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +-#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +-#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +-#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +-#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +-#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ +- +-#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +-#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +-#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +-#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +-#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +-#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +-#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +-#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +-#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +-#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +-#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +-#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ +- +- +-/* OSC.DFLLCTRL bit masks and bit positions */ +-#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +-#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ +- +-#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +-#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ +- +- +-/* DFLL - DFLL */ +-/* DFLL.CTRL bit masks and bit positions */ +-#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +-#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ +- +- +-/* DFLL.CALA bit masks and bit positions */ +-#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +-#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +-#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +-#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +-#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +-#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +-#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +-#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +-#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +-#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +-#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +-#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +-#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +-#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +-#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +-#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ +- +- +-/* DFLL.CALB bit masks and bit positions */ +-#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +-#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +-#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +-#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +-#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +-#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +-#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +-#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +-#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +-#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +-#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +-#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +-#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +-#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ +- +- +-/* RST - Reset */ +-/* RST.STATUS bit masks and bit positions */ +-#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +-#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ +- +-#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +-#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ +- +-#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +-#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ +- +-#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +-#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ +- +-#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +-#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ +- +-#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +-#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ +- +-#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +-#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ +- +- +-/* RST.CTRL bit masks and bit positions */ +-#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +-#define RST_SWRST_bp 0 /* Software Reset bit position. */ +- +- +-/* WDT - Watch-Dog Timer */ +-/* WDT.CTRL bit masks and bit positions */ +-#define WDT_PER_gm 0x3C /* Period group mask. */ +-#define WDT_PER_gp 2 /* Period group position. */ +-#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +-#define WDT_PER0_bp 2 /* Period bit 0 position. */ +-#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +-#define WDT_PER1_bp 3 /* Period bit 1 position. */ +-#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +-#define WDT_PER2_bp 4 /* Period bit 2 position. */ +-#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +-#define WDT_PER3_bp 5 /* Period bit 3 position. */ +- +-#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +-#define WDT_ENABLE_bp 1 /* Enable bit position. */ +- +-#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +-#define WDT_CEN_bp 0 /* Change Enable bit position. */ +- +- +-/* WDT.WINCTRL bit masks and bit positions */ +-#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +-#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +-#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +-#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +-#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +-#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +-#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +-#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +-#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +-#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ +- +-#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +-#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ +- +-#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +-#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ +- +- +-/* WDT.STATUS bit masks and bit positions */ +-#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +-#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +- +- +-/* MCU - MCU Control */ +-/* MCU.MCUCR bit masks and bit positions */ +-#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +-#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ +- +- +-/* MCU.EVSYSLOCK bit masks and bit positions */ +-#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +-#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ +- +-#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +-#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ +- +- +-/* MCU.AWEXLOCK bit masks and bit positions */ +-#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +-#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ +- +-#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +-#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ +- +- +-/* PMIC - Programmable Multi-level Interrupt Controller */ +-/* PMIC.STATUS bit masks and bit positions */ +-#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +-#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ +- +-#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +-#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ +- +-#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +-#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ +- +-#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +-#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ +- +- +-/* PMIC.CTRL bit masks and bit positions */ +-#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +-#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ +- +-#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +-#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ +- +-#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +-#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ +- +-#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +-#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ +- +-#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +-#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ +- +- +-/* DMA - DMA Controller */ +-/* DMA_CH.CTRLA bit masks and bit positions */ +-#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +-#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ +- +-#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +-#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ +- +-#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +-#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ +- +-#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +-#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ +- +-#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +-#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ +- +-#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +-#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +-#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +-#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +-#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +-#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ +- +- +-/* DMA_CH.CTRLB bit masks and bit positions */ +-#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +-#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ +- +-#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +-#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ +- +-#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +-#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ +- +-#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +-#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +-#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +-#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +-#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +-#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ +- +-#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +-#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +-#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +-#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +-#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +-#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ +- +- +-/* DMA_CH.ADDRCTRL bit masks and bit positions */ +-#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +-#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +-#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +-#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +-#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +-#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ +- +-#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +-#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +-#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +-#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +-#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +-#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ +- +-#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +-#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +-#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +-#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +-#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +-#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ +- +-#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +-#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +-#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +-#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +-#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +-#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ +- +- +-/* DMA_CH.TRIGSRC bit masks and bit positions */ +-#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +-#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +-#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +-#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +-#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +-#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +-#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +-#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +-#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +-#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +-#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +-#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +-#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +-#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +-#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +-#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +-#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +-#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ +- +- +-/* DMA.CTRL bit masks and bit positions */ +-#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +-#define DMA_ENABLE_bp 7 /* Enable bit position. */ +- +-#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +-#define DMA_RESET_bp 6 /* Software Reset bit position. */ +- +-#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +-#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +-#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +-#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +-#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +-#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ +- +-#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +-#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +-#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +-#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +-#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +-#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ +- +- +-/* DMA.INTFLAGS bit masks and bit positions */ +-#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ +- +- +-/* DMA.STATUS bit masks and bit positions */ +-#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +-#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ +- +-#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +-#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ +- +-#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +-#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ +- +-#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +-#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ +- +-#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +-#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ +- +-#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +-#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ +- +-#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +-#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ +- +-#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +-#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ +- +- +-/* EVSYS - Event System */ +-/* EVSYS.CH0MUX bit masks and bit positions */ +-#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +-#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +-#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +-#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +-#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +-#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +-#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +-#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +-#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +-#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +-#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +-#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +-#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +-#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +-#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +-#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +-#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +-#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ +- +- +-/* EVSYS.CH1MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH2MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH3MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH4MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH5MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH6MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH7MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH0CTRL bit masks and bit positions */ +-#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +-#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +-#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +-#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +-#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +-#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ +- +-#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +-#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ +- +-#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +-#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ +- +-#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +-#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +-#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +-#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +-#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +-#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +-#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +-#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ +- +- +-/* EVSYS.CH1CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH2CTRL bit masks and bit positions */ +-/* EVSYS_QDIRM_gm Predefined. */ +-/* EVSYS_QDIRM_gp Predefined. */ +-/* EVSYS_QDIRM0_bm Predefined. */ +-/* EVSYS_QDIRM0_bp Predefined. */ +-/* EVSYS_QDIRM1_bm Predefined. */ +-/* EVSYS_QDIRM1_bp Predefined. */ +- +-/* EVSYS_QDIEN_bm Predefined. */ +-/* EVSYS_QDIEN_bp Predefined. */ +- +-/* EVSYS_QDEN_bm Predefined. */ +-/* EVSYS_QDEN_bp Predefined. */ +- +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH3CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH4CTRL bit masks and bit positions */ +-/* EVSYS_QDIRM_gm Predefined. */ +-/* EVSYS_QDIRM_gp Predefined. */ +-/* EVSYS_QDIRM0_bm Predefined. */ +-/* EVSYS_QDIRM0_bp Predefined. */ +-/* EVSYS_QDIRM1_bm Predefined. */ +-/* EVSYS_QDIRM1_bp Predefined. */ +- +-/* EVSYS_QDIEN_bm Predefined. */ +-/* EVSYS_QDIEN_bp Predefined. */ +- +-/* EVSYS_QDEN_bm Predefined. */ +-/* EVSYS_QDEN_bp Predefined. */ +- +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH5CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH6CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH7CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* NVM - Non Volatile Memory Controller */ +-/* NVM.CMD bit masks and bit positions */ +-#define NVM_CMD_gm 0xFF /* Command group mask. */ +-#define NVM_CMD_gp 0 /* Command group position. */ +-#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +-#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +-#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +-#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +-#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +-#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +-#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +-#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +-#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +-#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +-#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +-#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +-#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +-#define NVM_CMD7_bp 7 /* Command bit 7 position. */ +- +- +-/* NVM.CTRLA bit masks and bit positions */ +-#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +-#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ +- +- +-/* NVM.CTRLB bit masks and bit positions */ +-#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +-#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ +- +-#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +-#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ +- +-#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +-#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ +- +-#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +-#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ +- +- +-/* NVM.INTCTRL bit masks and bit positions */ +-#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +-#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +-#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +-#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +-#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +-#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ +- +-#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +-#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +-#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +-#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +-#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +-#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ +- +- +-/* NVM.STATUS bit masks and bit positions */ +-#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +-#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ +- +-#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +-#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ +- +-#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +-#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ +- +-#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +-#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ +- +- +-/* NVM.LOCKBITS bit masks and bit positions */ +-#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +-#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +-#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ +-#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ +-#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ +-#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ +-#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ +-#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ +-#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ +-#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ +-#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ +-#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ +-#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ +-#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ +-#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ +-#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ +-#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ +-#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ +-#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ +-#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +-#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +-#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +-#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ +- +-#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +-#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +-#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +-#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +-#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ +- +-#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +-#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ +- +-#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +-#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +-#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +-#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +-#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +-#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +-#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +-#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +-#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +-#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +-#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +-#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ +- +-#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +-#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ +- +- +-/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +-#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +-#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +-#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +-#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +-#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +-#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ +- +-#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +-#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ +- +-#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +-#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +-#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +-#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +-#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +-#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +-#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +-#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +- +- +-/* AC - Analog Comparator */ +-/* AC.AC0CTRL bit masks and bit positions */ +-#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +-#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +-#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +-#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +-#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +-#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ +- +-#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +-#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +-#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +-#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +-#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +-#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ +- +-#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +-#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ +- +-#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +-#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +-#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +-#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +-#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +-#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +- +-#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define AC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* AC.AC1CTRL bit masks and bit positions */ +-/* AC_INTMODE_gm Predefined. */ +-/* AC_INTMODE_gp Predefined. */ +-/* AC_INTMODE0_bm Predefined. */ +-/* AC_INTMODE0_bp Predefined. */ +-/* AC_INTMODE1_bm Predefined. */ +-/* AC_INTMODE1_bp Predefined. */ +- +-/* AC_INTLVL_gm Predefined. */ +-/* AC_INTLVL_gp Predefined. */ +-/* AC_INTLVL0_bm Predefined. */ +-/* AC_INTLVL0_bp Predefined. */ +-/* AC_INTLVL1_bm Predefined. */ +-/* AC_INTLVL1_bp Predefined. */ +- +-/* AC_HSMODE_bm Predefined. */ +-/* AC_HSMODE_bp Predefined. */ +- +-/* AC_HYSMODE_gm Predefined. */ +-/* AC_HYSMODE_gp Predefined. */ +-/* AC_HYSMODE0_bm Predefined. */ +-/* AC_HYSMODE0_bp Predefined. */ +-/* AC_HYSMODE1_bm Predefined. */ +-/* AC_HYSMODE1_bp Predefined. */ +- +-/* AC_ENABLE_bm Predefined. */ +-/* AC_ENABLE_bp Predefined. */ +- +- +-/* AC.AC0MUXCTRL bit masks and bit positions */ +-#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +-#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +-#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +-#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +-#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +-#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +-#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +-#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ +- +-#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +-#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +-#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +-#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +-#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +-#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +-#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +-#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ +- +- +-/* AC.AC1MUXCTRL bit masks and bit positions */ +-/* AC_MUXPOS_gm Predefined. */ +-/* AC_MUXPOS_gp Predefined. */ +-/* AC_MUXPOS0_bm Predefined. */ +-/* AC_MUXPOS0_bp Predefined. */ +-/* AC_MUXPOS1_bm Predefined. */ +-/* AC_MUXPOS1_bp Predefined. */ +-/* AC_MUXPOS2_bm Predefined. */ +-/* AC_MUXPOS2_bp Predefined. */ +- +-/* AC_MUXNEG_gm Predefined. */ +-/* AC_MUXNEG_gp Predefined. */ +-/* AC_MUXNEG0_bm Predefined. */ +-/* AC_MUXNEG0_bp Predefined. */ +-/* AC_MUXNEG1_bm Predefined. */ +-/* AC_MUXNEG1_bp Predefined. */ +-/* AC_MUXNEG2_bm Predefined. */ +-/* AC_MUXNEG2_bp Predefined. */ +- +- +-/* AC.CTRLA bit masks and bit positions */ +-#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +-#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ +- +- +-/* AC.CTRLB bit masks and bit positions */ +-#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +-#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +-#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +-#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +-#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +-#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +-#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +-#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +-#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +-#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +-#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +-#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +-#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +-#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ +- +- +-/* AC.WINCTRL bit masks and bit positions */ +-#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +-#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ +- +-#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +-#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +-#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +-#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +-#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +-#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ +- +-#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +-#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +-#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +-#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +-#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +-#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ +- +- +-/* AC.STATUS bit masks and bit positions */ +-#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +-#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +-#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +-#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +-#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +-#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ +- +-#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +-#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ +- +-#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +-#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ +- +-#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +-#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ +- +-#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +-#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ +- +-#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +-#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ +- +- +-/* ADC - Analog/Digital Converter */ +-/* ADC_CH.CTRL bit masks and bit positions */ +-#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +-#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ +- +-#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +-#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +-#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +-#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +-#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +-#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +-#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +-#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ +- +-#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +-#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +-#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +-#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +-#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +-#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ +- +- +-/* ADC_CH.MUXCTRL bit masks and bit positions */ +-#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +-#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +-#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +-#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +-#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +-#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +-#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +-#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +-#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +-#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ +- +-#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +-#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +-#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +-#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +-#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +-#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +-#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +-#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +-#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +-#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ +- +-#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +-#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +-#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +-#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +-#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +-#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ +- +- +-/* ADC_CH.INTCTRL bit masks and bit positions */ +-#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +-#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +-#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +-#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +-#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +-#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ +- +-#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +-#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +-#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +-#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +-#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +-#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ +- +- +-/* ADC_CH.INTFLAGS bit masks and bit positions */ +-#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +-#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ +- +- +-/* ADC.CTRLA bit masks and bit positions */ +-#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +-#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +-#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +-#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +-#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +-#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ +- +-#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +-#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ +- +-#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +-#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ +- +-#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +-#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ +- +-#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +-#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ +- +-#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +-#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ +- +-#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +-#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ +- +- +-/* ADC.CTRLB bit masks and bit positions */ +-#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +-#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ +- +-#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +-#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ +- +-#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +-#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +-#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +-#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +-#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +-#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ +- +- +-/* ADC.REFCTRL bit masks and bit positions */ +-#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +-#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +-#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +-#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +-#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +-#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +- +-#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +-#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ +- +-#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +-#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ +- +- +-/* ADC.EVCTRL bit masks and bit positions */ +-#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +-#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +-#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +-#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +-#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +-#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ +- +-#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +-#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +-#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +-#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +-#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +-#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +-#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +-#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ +- +-#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +-#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +-#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +-#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +-#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +-#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +-#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +-#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ +- +- +-/* ADC.PRESCALER bit masks and bit positions */ +-#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +-#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +-#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +-#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +-#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +-#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +-#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +-#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ +- +- +-/* ADC.INTFLAGS bit masks and bit positions */ +-#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +-#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ +- +-#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +-#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ +- +-#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +-#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ +- +-#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +-#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ +- +- +-/* DAC - Digital/Analog Converter */ +-/* DAC.CTRLA bit masks and bit positions */ +-#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +-#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ +- +-#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +-#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ +- +-#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +-#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ +- +-#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +-#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ +- +-#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define DAC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* DAC.CTRLB bit masks and bit positions */ +-#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +-#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +-#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +-#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +-#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +-#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ +- +-#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +-#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ +- +-#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +-#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ +- +- +-/* DAC.CTRLC bit masks and bit positions */ +-#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +-#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +-#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +-#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +-#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +-#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ +- +-#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +-#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ +- +- +-/* DAC.EVCTRL bit masks and bit positions */ +-#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +-#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +-#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +-#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +-#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +-#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +-#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +-#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ +- +- +-/* DAC.TIMCTRL bit masks and bit positions */ +-#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ +-#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ +-#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ +-#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ +-#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ +-#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ +-#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ +-#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ +- +-#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ +-#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ +-#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ +-#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ +-#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ +-#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ +-#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ +-#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ +-#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ +-#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ +- +- +-/* DAC.STATUS bit masks and bit positions */ +-#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +-#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ +- +-#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +-#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ +- +- +-/* RTC - Real-Time Clounter */ +-/* RTC.CTRL bit masks and bit positions */ +-#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +-#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +-#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +-#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +-#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +-#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +-#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +-#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ +- +- +-/* RTC.STATUS bit masks and bit positions */ +-#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +-#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ +- +- +-/* RTC.INTCTRL bit masks and bit positions */ +-#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +-#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +-#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +-#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +-#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +-#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ +- +-#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +-#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +-#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +-#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +-#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +-#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ +- +- +-/* RTC.INTFLAGS bit masks and bit positions */ +-#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +-#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ +- +-#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* EBI - External Bus Interface */ +-/* EBI_CS.CTRLA bit masks and bit positions */ +-#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +-#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +-#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +-#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +-#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +-#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +-#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +-#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +-#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +-#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +-#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +-#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ +- +-#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +-#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +-#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +-#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +-#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +-#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ +- +- +-/* EBI_CS.CTRLB bit masks and bit positions */ +-#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +-#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +-#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +-#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +-#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +-#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +-#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +-#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ +- +-#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +-#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ +- +-#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +-#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ +- +-#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +-#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +-#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +-#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +-#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +-#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ +- +- +-/* EBI.CTRL bit masks and bit positions */ +-#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +-#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +-#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +-#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +-#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +-#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ +- +-#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +-#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +-#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +-#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +-#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +-#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ +- +-#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +-#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +-#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +-#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +-#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +-#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ +- +-#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +-#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +-#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +-#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +-#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +-#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLA bit masks and bit positions */ +-#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +-#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ +- +-#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +-#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ +- +-#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +-#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +-#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +-#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +-#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +-#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLB bit masks and bit positions */ +-#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +-#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +-#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +-#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +-#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +-#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ +- +-#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +-#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +-#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +-#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +-#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +-#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +-#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +-#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ +- +-#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +-#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +-#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +-#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +-#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +-#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +-#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +-#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ +- +- +-/* EBI.SDRAMCTRLC bit masks and bit positions */ +-#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +-#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +-#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +-#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +-#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +-#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ +- +-#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +-#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +-#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +-#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +-#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +-#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +-#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +-#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ +- +-#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +-#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +-#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +-#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +-#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +-#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +-#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +-#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ +- +- +-/* TWI - Two-Wire Interface */ +-/* TWI_MASTER.CTRLA bit masks and bit positions */ +-#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +-#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ +- +-#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +-#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ +- +-#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +-#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ +- +- +-/* TWI_MASTER.CTRLB bit masks and bit positions */ +-#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +-#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +-#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +-#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +-#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +-#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +- +-#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +-#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ +- +-#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_MASTER.CTRLC bit masks and bit positions */ +-#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +-#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_MASTER.STATUS bit masks and bit positions */ +-#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +-#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ +- +-#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +-#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ +- +-#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +-#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +- +-#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +-#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +-#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +-#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +-#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +-#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +- +- +-/* TWI_SLAVE.CTRLA bit masks and bit positions */ +-#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +-#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +-#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ +- +-#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +-#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ +- +-#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_SLAVE.CTRLB bit masks and bit positions */ +-#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +-#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_SLAVE.STATUS bit masks and bit positions */ +-#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +-#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +-#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +-#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ +- +-#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +-#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ +- +-#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +-#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ +- +- +-/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +-#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +-#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +-#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +-#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +-#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +-#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +-#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +-#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +-#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +-#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +-#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +-#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +-#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +-#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +-#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +-#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ +- +-#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +-#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ +- +- +-/* TWI.CTRL bit masks and bit positions */ +-#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +-#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ +- +-#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +-#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ +- +- +-/* PORT - Port Configuration */ +-/* PORTCFG.VPCTRLA bit masks and bit positions */ +-#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +-#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +-#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +-#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +-#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +-#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +-#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +-#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +-#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +-#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ +- +-#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +-#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +-#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +-#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +-#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +-#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +-#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +-#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +-#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +-#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ +- +- +-/* PORTCFG.VPCTRLB bit masks and bit positions */ +-#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +-#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +-#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +-#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +-#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +-#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +-#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +-#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +-#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +-#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ +- +-#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +-#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +-#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +-#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +-#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +-#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +-#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +-#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +-#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +-#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ +- +- +-/* PORTCFG.CLKEVOUT bit masks and bit positions */ +-#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +-#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +-#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +-#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +-#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +-#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ +- +-#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +-#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +-#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +-#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +-#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +-#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ +- +- +-/* VPORT.INTFLAGS bit masks and bit positions */ +-#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.INTCTRL bit masks and bit positions */ +-#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +-#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +-#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +-#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +-#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +-#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ +- +-#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +-#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +-#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +-#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +-#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +-#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ +- +- +-/* PORT.INTFLAGS bit masks and bit positions */ +-#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.PIN0CTRL bit masks and bit positions */ +-#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +-#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ +- +-#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +-#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ +- +-#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +-#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +-#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +-#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +-#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +-#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +-#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +-#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ +- +-#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +-#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +-#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +-#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +-#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +-#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +-#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +-#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +- +- +-/* PORT.PIN1CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN2CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN3CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN4CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN5CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN6CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN7CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* TC - 16-bit Timer/Counter With PWM */ +-/* TC0.CTRLA bit masks and bit positions */ +-#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC0.CTRLB bit masks and bit positions */ +-#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +-#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ +- +-#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +-#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ +- +-#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC0.CTRLC bit masks and bit positions */ +-#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +-#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ +- +-#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +-#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ +- +-#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC0.CTRLD bit masks and bit positions */ +-#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC0_EVACT_gp 5 /* Event Action group position. */ +-#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC0.CTRLE bit masks and bit positions */ +-#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +-#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ +- +-#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC0.INTCTRLA bit masks and bit positions */ +-#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC0.INTCTRLB bit masks and bit positions */ +-#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +-#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +-#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +-#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +-#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +-#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ +- +-#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +-#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +-#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +-#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +-#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +-#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ +- +-#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC0.CTRLFCLR bit masks and bit positions */ +-#define TC0_CMD_gm 0x0C /* Command group mask. */ +-#define TC0_CMD_gp 2 /* Command group position. */ +-#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC0_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC0_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC0_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC0.CTRLFSET bit masks and bit positions */ +-/* TC0_CMD_gm Predefined. */ +-/* TC0_CMD_gp Predefined. */ +-/* TC0_CMD0_bm Predefined. */ +-/* TC0_CMD0_bp Predefined. */ +-/* TC0_CMD1_bm Predefined. */ +-/* TC0_CMD1_bp Predefined. */ +- +-/* TC0_LUPD_bm Predefined. */ +-/* TC0_LUPD_bp Predefined. */ +- +-/* TC0_DIR_bm Predefined. */ +-/* TC0_DIR_bp Predefined. */ +- +- +-/* TC0.CTRLGCLR bit masks and bit positions */ +-#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +-#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ +- +-#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +-#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ +- +-#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC0.CTRLGSET bit masks and bit positions */ +-/* TC0_CCDBV_bm Predefined. */ +-/* TC0_CCDBV_bp Predefined. */ +- +-/* TC0_CCCBV_bm Predefined. */ +-/* TC0_CCCBV_bp Predefined. */ +- +-/* TC0_CCBBV_bm Predefined. */ +-/* TC0_CCBBV_bp Predefined. */ +- +-/* TC0_CCABV_bm Predefined. */ +-/* TC0_CCABV_bp Predefined. */ +- +-/* TC0_PERBV_bm Predefined. */ +-/* TC0_PERBV_bp Predefined. */ +- +- +-/* TC0.INTFLAGS bit masks and bit positions */ +-#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +-#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ +- +-#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +-#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ +- +-#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* TC1.CTRLA bit masks and bit positions */ +-#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC1.CTRLB bit masks and bit positions */ +-#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC1.CTRLC bit masks and bit positions */ +-#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC1.CTRLD bit masks and bit positions */ +-#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC1_EVACT_gp 5 /* Event Action group position. */ +-#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC1.CTRLE bit masks and bit positions */ +-#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +-#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ +- +-#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC1.INTCTRLA bit masks and bit positions */ +-#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC1.INTCTRLB bit masks and bit positions */ +-#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC1.CTRLFCLR bit masks and bit positions */ +-#define TC1_CMD_gm 0x0C /* Command group mask. */ +-#define TC1_CMD_gp 2 /* Command group position. */ +-#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC1_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC1_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC1_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC1.CTRLFSET bit masks and bit positions */ +-/* TC1_CMD_gm Predefined. */ +-/* TC1_CMD_gp Predefined. */ +-/* TC1_CMD0_bm Predefined. */ +-/* TC1_CMD0_bp Predefined. */ +-/* TC1_CMD1_bm Predefined. */ +-/* TC1_CMD1_bp Predefined. */ +- +-/* TC1_LUPD_bm Predefined. */ +-/* TC1_LUPD_bp Predefined. */ +- +-/* TC1_DIR_bm Predefined. */ +-/* TC1_DIR_bp Predefined. */ +- +- +-/* TC1.CTRLGCLR bit masks and bit positions */ +-#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC1.CTRLGSET bit masks and bit positions */ +-/* TC1_CCBBV_bm Predefined. */ +-/* TC1_CCBBV_bp Predefined. */ +- +-/* TC1_CCABV_bm Predefined. */ +-/* TC1_CCABV_bp Predefined. */ +- +-/* TC1_PERBV_bm Predefined. */ +-/* TC1_PERBV_bp Predefined. */ +- +- +-/* TC1.INTFLAGS bit masks and bit positions */ +-#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* AWEX.CTRL bit masks and bit positions */ +-#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +-#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ +- +-#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +-#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ +- +-#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +-#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ +- +-#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +-#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ +- +-#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +-#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ +- +-#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +-#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ +- +- +-/* AWEX.FDCTRL bit masks and bit positions */ +-#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +-#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ +- +-#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +-#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ +- +-#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +-#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +-#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +-#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +-#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +-#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ +- +- +-/* AWEX.STATUS bit masks and bit positions */ +-#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +-#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ +- +-#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +-#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ +- +-#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +-#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ +- +- +-/* HIRES.CTRL bit masks and bit positions */ +-#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +-#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +-#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +-#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +-#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +-#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ +- +- +-/* USART - Universal Asynchronous Receiver-Transmitter */ +-/* USART.STATUS bit masks and bit positions */ +-#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +-#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ +- +-#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +-#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +- +-#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +-#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +- +-#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +-#define USART_FERR_bp 4 /* Frame Error bit position. */ +- +-#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +-#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ +- +-#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +-#define USART_PERR_bp 2 /* Parity Error bit position. */ +- +-#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +-#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ +- +- +-/* USART.CTRLA bit masks and bit positions */ +-#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +-#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +-#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +-#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +-#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +-#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ +- +-#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +-#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +-#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +-#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +-#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +-#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ +- +-#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +-#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +-#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +-#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +-#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +-#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ +- +- +-/* USART.CTRLB bit masks and bit positions */ +-#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +-#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ +- +-#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +-#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ +- +-#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +-#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ +- +-#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +-#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ +- +-#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +-#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ +- +- +-/* USART.CTRLC bit masks and bit positions */ +-#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +-#define USART_CMODE_gp 6 /* Communication Mode group position. */ +-#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +-#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +-#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +-#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ +- +-#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +-#define USART_PMODE_gp 4 /* Parity Mode group position. */ +-#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +-#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +-#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +-#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +- +-#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +-#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +- +-#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +-#define USART_CHSIZE_gp 0 /* Character Size group position. */ +-#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +-#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +-#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +-#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +-#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +-#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +- +- +-/* USART.BAUDCTRLA bit masks and bit positions */ +-#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +-#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +-#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +-#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +-#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +-#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +-#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +-#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +-#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +-#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +-#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +-#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +-#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +-#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +-#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +-#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +-#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +-#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ +- +- +-/* USART.BAUDCTRLB bit masks and bit positions */ +-#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +-#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +-#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +-#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +-#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +-#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +-#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +-#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +-#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +-#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ +- +-/* USART_BSEL_gm Predefined. */ +-/* USART_BSEL_gp Predefined. */ +-/* USART_BSEL0_bm Predefined. */ +-/* USART_BSEL0_bp Predefined. */ +-/* USART_BSEL1_bm Predefined. */ +-/* USART_BSEL1_bp Predefined. */ +-/* USART_BSEL2_bm Predefined. */ +-/* USART_BSEL2_bp Predefined. */ +-/* USART_BSEL3_bm Predefined. */ +-/* USART_BSEL3_bp Predefined. */ +- +- +-/* SPI - Serial Peripheral Interface */ +-/* SPI.CTRL bit masks and bit positions */ +-#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +-#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ +- +-#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +-#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ +- +-#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +-#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ +- +-#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +-#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ +- +-#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +-#define SPI_MODE_gp 2 /* SPI Mode group position. */ +-#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +-#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +-#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +-#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ +- +-#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +-#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +-#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +-#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +-#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +-#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ +- +- +-/* SPI.INTCTRL bit masks and bit positions */ +-#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +-#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +-/* SPI.STATUS bit masks and bit positions */ +-#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +-#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ +- +-#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +-#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +- +- +-/* IRCOM - IR Communication Module */ +-/* IRCOM.CTRL bit masks and bit positions */ +-#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +-#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +-#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +-#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +-#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +-#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +-#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +-#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +-#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +-#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ +- +- +-/* AES - AES Module */ +-/* AES.CTRL bit masks and bit positions */ +-#define AES_START_bm 0x80 /* Start/Run bit mask. */ +-#define AES_START_bp 7 /* Start/Run bit position. */ +- +-#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +-#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ +- +-#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +-#define AES_RESET_bp 5 /* AES Software Reset bit position. */ +- +-#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +-#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ +- +-#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +-#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ +- +- +-/* AES.STATUS bit masks and bit positions */ +-#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +-#define AES_ERROR_bp 7 /* AES Error bit position. */ +- +-#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +-#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ +- +- +-/* AES.INTCTRL bit masks and bit positions */ +-#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +-#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +- +-// Generic Port Pins +- +-#define PIN0_bm 0x01 +-#define PIN0_bp 0 +-#define PIN1_bm 0x02 +-#define PIN1_bp 1 +-#define PIN2_bm 0x04 +-#define PIN2_bp 2 +-#define PIN3_bm 0x08 +-#define PIN3_bp 3 +-#define PIN4_bm 0x10 +-#define PIN4_bp 4 +-#define PIN5_bm 0x20 +-#define PIN5_bp 5 +-#define PIN6_bm 0x40 +-#define PIN6_bp 6 +-#define PIN7_bm 0x80 +-#define PIN7_bp 7 +- +- +-/* ========== Interrupt Vector Definitions ========== */ +-/* Vector 0 is the reset vector */ +- +-/* OSC interrupt vectors */ +-#define OSC_XOSCF_vect_num 1 +-#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ +- +-/* PORTC interrupt vectors */ +-#define PORTC_INT0_vect_num 2 +-#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +-#define PORTC_INT1_vect_num 3 +-#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ +- +-/* PORTR interrupt vectors */ +-#define PORTR_INT0_vect_num 4 +-#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +-#define PORTR_INT1_vect_num 5 +-#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ +- +-/* DMA interrupt vectors */ +-#define DMA_CH0_vect_num 6 +-#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +-#define DMA_CH1_vect_num 7 +-#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +-#define DMA_CH2_vect_num 8 +-#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +-#define DMA_CH3_vect_num 9 +-#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ +- +-/* RTC interrupt vectors */ +-#define RTC_OVF_vect_num 10 +-#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +-#define RTC_COMP_vect_num 11 +-#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ +- +-/* TWIC interrupt vectors */ +-#define TWIC_TWIS_vect_num 12 +-#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +-#define TWIC_TWIM_vect_num 13 +-#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ +- +-/* TCC0 interrupt vectors */ +-#define TCC0_OVF_vect_num 14 +-#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +-#define TCC0_ERR_vect_num 15 +-#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +-#define TCC0_CCA_vect_num 16 +-#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +-#define TCC0_CCB_vect_num 17 +-#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +-#define TCC0_CCC_vect_num 18 +-#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +-#define TCC0_CCD_vect_num 19 +-#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ +- +-/* TCC1 interrupt vectors */ +-#define TCC1_OVF_vect_num 20 +-#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +-#define TCC1_ERR_vect_num 21 +-#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +-#define TCC1_CCA_vect_num 22 +-#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +-#define TCC1_CCB_vect_num 23 +-#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ +- +-/* SPIC interrupt vectors */ +-#define SPIC_INT_vect_num 24 +-#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ +- +-/* USARTC0 interrupt vectors */ +-#define USARTC0_RXC_vect_num 25 +-#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +-#define USARTC0_DRE_vect_num 26 +-#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +-#define USARTC0_TXC_vect_num 27 +-#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ +- +-/* USARTC1 interrupt vectors */ +-#define USARTC1_RXC_vect_num 28 +-#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +-#define USARTC1_DRE_vect_num 29 +-#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +-#define USARTC1_TXC_vect_num 30 +-#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ +- +-/* AES interrupt vectors */ +-#define AES_INT_vect_num 31 +-#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ +- +-/* NVM interrupt vectors */ +-#define NVM_EE_vect_num 32 +-#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +-#define NVM_SPM_vect_num 33 +-#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ +- +-/* PORTB interrupt vectors */ +-#define PORTB_INT0_vect_num 34 +-#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +-#define PORTB_INT1_vect_num 35 +-#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ +- +-/* PORTE interrupt vectors */ +-#define PORTE_INT0_vect_num 43 +-#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +-#define PORTE_INT1_vect_num 44 +-#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ +- +-/* TWIE interrupt vectors */ +-#define TWIE_TWIS_vect_num 45 +-#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +-#define TWIE_TWIM_vect_num 46 +-#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ +- +-/* TCE0 interrupt vectors */ +-#define TCE0_OVF_vect_num 47 +-#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +-#define TCE0_ERR_vect_num 48 +-#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +-#define TCE0_CCA_vect_num 49 +-#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +-#define TCE0_CCB_vect_num 50 +-#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +-#define TCE0_CCC_vect_num 51 +-#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +-#define TCE0_CCD_vect_num 52 +-#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ +- +-/* TCE1 interrupt vectors */ +-#define TCE1_OVF_vect_num 53 +-#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ +-#define TCE1_ERR_vect_num 54 +-#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ +-#define TCE1_CCA_vect_num 55 +-#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ +-#define TCE1_CCB_vect_num 56 +-#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ +- +-/* USARTE0 interrupt vectors */ +-#define USARTE0_RXC_vect_num 58 +-#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +-#define USARTE0_DRE_vect_num 59 +-#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +-#define USARTE0_TXC_vect_num 60 +-#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ +- +-/* PORTD interrupt vectors */ +-#define PORTD_INT0_vect_num 64 +-#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +-#define PORTD_INT1_vect_num 65 +-#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ +- +-/* PORTA interrupt vectors */ +-#define PORTA_INT0_vect_num 66 +-#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +-#define PORTA_INT1_vect_num 67 +-#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ +- +-/* ACA interrupt vectors */ +-#define ACA_AC0_vect_num 68 +-#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +-#define ACA_AC1_vect_num 69 +-#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +-#define ACA_ACW_vect_num 70 +-#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ +- +-/* ADCA interrupt vectors */ +-#define ADCA_CH0_vect_num 71 +-#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +-#define ADCA_CH1_vect_num 72 +-#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +-#define ADCA_CH2_vect_num 73 +-#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +-#define ADCA_CH3_vect_num 74 +-#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ +- +-/* TCD0 interrupt vectors */ +-#define TCD0_OVF_vect_num 77 +-#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +-#define TCD0_ERR_vect_num 78 +-#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +-#define TCD0_CCA_vect_num 79 +-#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +-#define TCD0_CCB_vect_num 80 +-#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +-#define TCD0_CCC_vect_num 81 +-#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +-#define TCD0_CCD_vect_num 82 +-#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ +- +-/* TCD1 interrupt vectors */ +-#define TCD1_OVF_vect_num 83 +-#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +-#define TCD1_ERR_vect_num 84 +-#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +-#define TCD1_CCA_vect_num 85 +-#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +-#define TCD1_CCB_vect_num 86 +-#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ +- +-/* SPID interrupt vectors */ +-#define SPID_INT_vect_num 87 +-#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ +- +-/* USARTD0 interrupt vectors */ +-#define USARTD0_RXC_vect_num 88 +-#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +-#define USARTD0_DRE_vect_num 89 +-#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +-#define USARTD0_TXC_vect_num 90 +-#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ +- +-/* USARTD1 interrupt vectors */ +-#define USARTD1_RXC_vect_num 91 +-#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +-#define USARTD1_DRE_vect_num 92 +-#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +-#define USARTD1_TXC_vect_num 93 +-#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ +- +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (94 * _VECTOR_SIZE) +- +- +-/* ========== Constants ========== */ +- +-#define PROGMEM_START (0x0000) +-#define PROGMEM_SIZE (36864) +-#define PROGMEM_PAGE_SIZE (256) +-#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) +- +-#define APP_SECTION_START (0x0000) +-#define APP_SECTION_SIZE (32768) +-#define APP_SECTION_PAGE_SIZE (256) +-#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) +- +-#define APPTABLE_SECTION_START (0x07000) +-#define APPTABLE_SECTION_SIZE (4096) +-#define APPTABLE_SECTION_PAGE_SIZE (256) +-#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) +- +-#define BOOT_SECTION_START (0x8000) +-#define BOOT_SECTION_SIZE (4096) +-#define BOOT_SECTION_PAGE_SIZE (256) +-#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) +- +-#define DATAMEM_START (0x0000) +-#define DATAMEM_SIZE (12288) +-#define DATAMEM_PAGE_SIZE (0) +-#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) +- +-#define IO_START (0x0000) +-#define IO_SIZE (4096) +-#define IO_PAGE_SIZE (0) +-#define IO_END (IO_START + IO_SIZE - 1) +- +-#define MAPPED_EEPROM_START (0x1000) +-#define MAPPED_EEPROM_SIZE (1024) +-#define MAPPED_EEPROM_PAGE_SIZE (0) +-#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) +- +-#define INTERNAL_SRAM_START (0x2000) +-#define INTERNAL_SRAM_SIZE (4096) +-#define INTERNAL_SRAM_PAGE_SIZE (0) +-#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) +- +-#define EEPROM_START (0x0000) +-#define EEPROM_SIZE (1024) +-#define EEPROM_PAGE_SIZE (32) +-#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) +- +-#define FUSE_START (0x0000) +-#define FUSE_SIZE (6) +-#define FUSE_PAGE_SIZE (0) +-#define FUSE_END (FUSE_START + FUSE_SIZE - 1) +- +-#define LOCKBIT_START (0x0000) +-#define LOCKBIT_SIZE (1) +-#define LOCKBIT_PAGE_SIZE (0) +-#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) +- +-#define SIGNATURES_START (0x0000) +-#define SIGNATURES_SIZE (3) +-#define SIGNATURES_PAGE_SIZE (0) +-#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) +- +-#define USER_SIGNATURES_START (0x0000) +-#define USER_SIGNATURES_SIZE (256) +-#define USER_SIGNATURES_PAGE_SIZE (0) +-#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) +- +-#define PROD_SIGNATURES_START (0x0000) +-#define PROD_SIGNATURES_SIZE (52) +-#define PROD_SIGNATURES_PAGE_SIZE (0) +-#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) +- +-#define FLASHEND PROGMEM_END +-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +-#define RAMSTART INTERNAL_SRAM_START +-#define RAMSIZE INTERNAL_SRAM_SIZE +-#define RAMEND INTERNAL_SRAM_END +-#define XRAMSTART EXTERNAL_SRAM_START +-#define XRAMSIZE EXTERNAL_SRAM_SIZE +-#define XRAMEND INTERNAL_SRAM_END +-#define E2END EEPROM_END +-#define E2PAGESIZE EEPROM_PAGE_SIZE +- +- +-/* ========== Fuses ========== */ +-#define FUSE_MEMORY_SIZE 6 +- +-/* Fuse Byte 0 */ +-#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ +-#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ +-#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ +-#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ +-#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ +-#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ +-#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ +-#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ +-#define FUSE0_DEFAULT (0xFF) +- +-/* Fuse Byte 1 */ +-#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +-#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +-#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +-#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +-#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +-#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +-#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +-#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +-#define FUSE1_DEFAULT (0xFF) +- +-/* Fuse Byte 2 */ +-#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +-#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +-#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +-#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +-#define FUSE2_DEFAULT (0xFF) +- +-/* Fuse Byte 3 Reserved */ +- +-/* Fuse Byte 4 */ +-#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +-#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +-#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +-#define FUSE4_DEFAULT (0xFF) +- +-/* Fuse Byte 5 */ +-#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +-#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +-#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +-#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +-#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +-#define FUSE5_DEFAULT (0xFF) +- +- +-/* ========== Lock Bits ========== */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_BITS_EXIST +-#define __BOOT_LOCK_BOOT_BITS_EXIST +- +- +-/* ========== Signature ========== */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x95 +-#define SIGNATURE_2 0x41 +- +- +-#endif /* _AVR_ATxmega32A4_H_ */ +- ++/* Copyright (c) 2009-2010 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iox32a4.h 2200 2010-12-14 04:24:24Z arcanum $ */ ++ ++/* avr/iox32a4.h - definitions for ATxmega32A4 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox32a4.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATxmega32A4_H_ ++#define _AVR_ATxmega32A4_H_ 1 ++ ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++} CLK_t; ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t PRPB; /* Power Reduction Port B */ ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ ++} CLK_RTCSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control REgister */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t reserved_0x07; ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Channel */ ++typedef struct DMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Address Control */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ ++ register8_t REPCNT; /* Channel Repeat Count */ ++ register8_t reserved_0x07; ++ register8_t SRCADDR0; /* Channel Source Address 0 */ ++ register8_t SRCADDR1; /* Channel Source Address 1 */ ++ register8_t SRCADDR2; /* Channel Source Address 2 */ ++ register8_t reserved_0x0B; ++ register8_t DESTADDR0; /* Channel Destination Address 0 */ ++ register8_t DESTADDR1; /* Channel Destination Address 1 */ ++ register8_t DESTADDR2; /* Channel Destination Address 2 */ ++ register8_t reserved_0x0F; ++} DMA_CH_t; ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Controller */ ++typedef struct DMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ DMA_CH_t CH0; /* DMA Channel 0 */ ++ DMA_CH_t CH1; /* DMA Channel 1 */ ++ DMA_CH_t CH2; /* DMA Channel 2 */ ++ DMA_CH_t CH3; /* DMA Channel 3 */ ++} DMA_t; ++ ++/* Burst mode */ ++typedef enum DMA_CH_BURSTLEN_enum ++{ ++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ ++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ ++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ ++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ ++} DMA_CH_BURSTLEN_t; ++ ++/* Source address reload mode */ ++typedef enum DMA_CH_SRCRELOAD_enum ++{ ++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ ++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ ++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ ++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ ++} DMA_CH_SRCRELOAD_t; ++ ++/* Source addressing mode */ ++typedef enum DMA_CH_SRCDIR_enum ++{ ++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ ++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ ++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ ++} DMA_CH_SRCDIR_t; ++ ++/* Destination adress reload mode */ ++typedef enum DMA_CH_DESTRELOAD_enum ++{ ++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ ++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ ++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ ++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ ++} DMA_CH_DESTRELOAD_t; ++ ++/* Destination adressing mode */ ++typedef enum DMA_CH_DESTDIR_enum ++{ ++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ ++} DMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum DMA_CH_TRIGSRC_enum ++{ ++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ ++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ ++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ ++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ ++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ ++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ ++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ ++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ ++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ ++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ ++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ ++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ ++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ ++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ ++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ ++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ ++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ ++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ ++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ ++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ ++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ ++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ ++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ ++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ ++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ ++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ ++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ ++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ ++} DMA_CH_TRIGSRC_t; ++ ++/* Double buffering mode */ ++typedef enum DMA_DBUFMODE_enum ++{ ++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ ++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ ++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ ++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ ++} DMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum DMA_PRIMODE_enum ++{ ++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ ++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ ++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ ++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ ++} DMA_PRIMODE_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_ERRINTLVL_enum ++{ ++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ ++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ ++} DMA_CH_ERRINTLVL_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_TRNINTLVL_enum ++{ ++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ ++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ ++} DMA_CH_TRNINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ ++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ ++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ ++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t CH4CTRL; /* Channel 4 Control Register */ ++ register8_t CH5CTRL; /* Channel 5 Control Register */ ++ register8_t CH6CTRL; /* Channel 6 Control Register */ ++ register8_t CH7CTRL; /* Channel 7 Control Register */ ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ ++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ ++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ ++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ ++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ ++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ ++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ ++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ ++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ ++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ ++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ ++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ ++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ ++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ ++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ ++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ ++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ ++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t FUSEBYTE0; /* User ID */ ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ ++ register8_t reserved_0x01; ++ register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ ++ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ ++ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ ++ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++} NVM_PROD_SIGNATURES_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++} NVM_LB_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brown Out Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ ++ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Comparator 0 Control */ ++ register8_t AC1CTRL; /* Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t reserved_0x6; ++ register8_t reserved_0x7; ++} ADC_CH_t; ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ _WORDREGISTER(CH1RES); /* Channel 1 Result */ ++ _WORDREGISTER(CH2RES); /* Channel 2 Result */ ++ _WORDREGISTER(CH3RES); /* Channel 3 Result */ ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++ ADC_CH_t CH1; /* ADC Channel 1 */ ++ ADC_CH_t CH2; /* ADC Channel 2 */ ++ ADC_CH_t CH3; /* ADC Channel 3 */ ++} ADC_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++} ADC_REFSEL_t; ++ ++/* Channel sweep selection */ ++typedef enum ADC_SWEEP_enum ++{ ++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ ++} ADC_SWEEP_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ++ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* DMA request selection */ ++typedef enum ADC_DMASEL_enum ++{ ++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ ++} ADC_DMASEL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DAC - Digital/Analog Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Digital-to-Analog Converter */ ++typedef struct DAC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t EVCTRL; /* Event Input Control */ ++ register8_t TIMCTRL; /* Timing Control */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t GAINCAL; /* Gain Calibration */ ++ register8_t OFFSETCAL; /* Offset Calibration */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ ++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ ++} DAC_t; ++ ++/* Output channel selection */ ++typedef enum DAC_CHSEL_enum ++{ ++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ ++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ ++} DAC_CHSEL_t; ++ ++/* Reference voltage selection */ ++typedef enum DAC_REFSEL_enum ++{ ++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ ++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ ++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ ++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ ++} DAC_REFSEL_t; ++ ++/* Event channel selection */ ++typedef enum DAC_EVSEL_enum ++{ ++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ ++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ ++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ ++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ ++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ ++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ ++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ ++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ ++} DAC_EVSEL_t; ++ ++/* Conversion interval */ ++typedef enum DAC_CONINTVAL_enum ++{ ++ DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ ++ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ ++ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ ++ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ ++ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ ++ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ ++ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ ++ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ ++} DAC_CONINTVAL_t; ++ ++/* Refresh rate */ ++typedef enum DAC_REFRESH_enum ++{ ++ DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ ++ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ ++ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ ++ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ ++ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ ++ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ ++ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ ++ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ ++ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ ++ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ ++ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ ++ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ ++ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ ++ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ ++} DAC_REFRESH_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Clounter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* EBI Chip Select Module */ ++typedef struct EBI_CS_struct ++{ ++ register8_t CTRLA; /* Chip Select Control Register A */ ++ register8_t CTRLB; /* Chip Select Control Register B */ ++ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ ++} EBI_CS_t; ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* External Bus Interface */ ++typedef struct EBI_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ ++ register8_t reserved_0x02; ++ register8_t reserved_0x03; ++ _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ ++ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ ++ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ ++ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ EBI_CS_t CS0; /* Chip Select 0 */ ++ EBI_CS_t CS1; /* Chip Select 1 */ ++ EBI_CS_t CS2; /* Chip Select 2 */ ++ EBI_CS_t CS3; /* Chip Select 3 */ ++} EBI_t; ++ ++/* Chip Select adress space */ ++typedef enum EBI_CS_ASIZE_enum ++{ ++ EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ ++ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ ++ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ ++ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ ++ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ ++ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ ++ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ ++ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ ++ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ ++ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ ++ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ ++ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ ++ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ ++ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ ++ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ ++ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ ++ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ ++} EBI_CS_ASIZE_t; ++ ++/* */ ++typedef enum EBI_CS_SRWS_enum ++{ ++ EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_CS_SRWS_t; ++ ++/* Chip Select address mode */ ++typedef enum EBI_CS_MODE_enum ++{ ++ EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ ++ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ ++ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ ++ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ ++} EBI_CS_MODE_t; ++ ++/* Chip Select SDRAM mode */ ++typedef enum EBI_CS_SDMODE_enum ++{ ++ EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ ++ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ ++} EBI_CS_SDMODE_t; ++ ++/* */ ++typedef enum EBI_SDDATAW_enum ++{ ++ EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ ++ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ ++} EBI_SDDATAW_t; ++ ++/* */ ++typedef enum EBI_LPCMODE_enum ++{ ++ EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ ++ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ ++} EBI_LPCMODE_t; ++ ++/* */ ++typedef enum EBI_SRMODE_enum ++{ ++ EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ ++ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ ++ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ ++ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ ++} EBI_SRMODE_t; ++ ++/* */ ++typedef enum EBI_IFMODE_enum ++{ ++ EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ ++ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ ++ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ ++ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ ++} EBI_IFMODE_t; ++ ++/* */ ++typedef enum EBI_SDCOL_enum ++{ ++ EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ ++ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ ++ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ ++ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ ++} EBI_SDCOL_t; ++ ++/* */ ++typedef enum EBI_MRDLY_enum ++{ ++ EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_MRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCYCDLY_enum ++{ ++ EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ROWCYCDLY_t; ++ ++/* */ ++typedef enum EBI_RPDLY_enum ++{ ++ EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_RPDLY_t; ++ ++/* */ ++typedef enum EBI_WRDLY_enum ++{ ++ EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_WRDLY_t; ++ ++/* */ ++typedef enum EBI_ESRDLY_enum ++{ ++ EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ESRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCOLDLY_enum ++{ ++ EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_ROWCOLDLY_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++} PORTCFG_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Virtual Port 0 Mapping */ ++typedef enum PORTCFG_VP0MAP_enum ++{ ++ PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP0MAP_t; ++ ++/* Virtual Port 1 Mapping */ ++typedef enum PORTCFG_VP1MAP_enum ++{ ++ PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP1MAP_t; ++ ++/* Virtual Port 2 Mapping */ ++typedef enum PORTCFG_VP2MAP_enum ++{ ++ PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP2MAP_t; ++ ++/* Virtual Port 3 Mapping */ ++typedef enum PORTCFG_VP3MAP_enum ++{ ++ PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP3MAP_t; ++ ++/* Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x05; ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AES - AES Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* AES Module */ ++typedef struct AES_struct ++{ ++ register8_t CTRL; /* AES Control Register */ ++ register8_t STATUS; /* AES Status Register */ ++ register8_t STATE; /* AES State Register */ ++ register8_t KEY; /* AES Key Register */ ++ register8_t INTCTRL; /* AES Interrupt Control Register */ ++} AES_t; ++ ++/* Interrupt level */ ++typedef enum AES_INTLVL_enum ++{ ++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} AES_INTLVL_t; ++ ++ ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset Controller */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ ++#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ ++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ ++#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ ++#define PORTA (*(PORT_t *) 0x0600) /* Port A */ ++#define PORTB (*(PORT_t *) 0x0620) /* Port B */ ++#define PORTC (*(PORT_t *) 0x0640) /* Port C */ ++#define PORTD (*(PORT_t *) 0x0660) /* Port D */ ++#define PORTE (*(PORT_t *) 0x0680) /* Port E */ ++#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ ++#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ ++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ ++#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ ++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ ++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ ++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++#define GPIO_GPIOR4 _SFR_MEM8(0x0004) ++#define GPIO_GPIOR5 _SFR_MEM8(0x0005) ++#define GPIO_GPIOR6 _SFR_MEM8(0x0006) ++#define GPIO_GPIOR7 _SFR_MEM8(0x0007) ++#define GPIO_GPIOR8 _SFR_MEM8(0x0008) ++#define GPIO_GPIOR9 _SFR_MEM8(0x0009) ++#define GPIO_GPIORA _SFR_MEM8(0x000A) ++#define GPIO_GPIORB _SFR_MEM8(0x000B) ++#define GPIO_GPIORC _SFR_MEM8(0x000C) ++#define GPIO_GPIORD _SFR_MEM8(0x000D) ++#define GPIO_GPIORE _SFR_MEM8(0x000E) ++#define GPIO_GPIORF _SFR_MEM8(0x000F) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++#define GPIO_GPIO4 _SFR_MEM8(0x0004) ++#define GPIO_GPIO5 _SFR_MEM8(0x0005) ++#define GPIO_GPIO6 _SFR_MEM8(0x0006) ++#define GPIO_GPIO7 _SFR_MEM8(0x0007) ++#define GPIO_GPIO8 _SFR_MEM8(0x0008) ++#define GPIO_GPIO9 _SFR_MEM8(0x0009) ++#define GPIO_GPIOA _SFR_MEM8(0x000A) ++#define GPIO_GPIOB _SFR_MEM8(0x000B) ++#define GPIO_GPIOC _SFR_MEM8(0x000C) ++#define GPIO_GPIOD _SFR_MEM8(0x000D) ++#define GPIO_GPIOE _SFR_MEM8(0x000E) ++#define GPIO_GPIOF _SFR_MEM8(0x000F) ++ ++/* VPORT0 - Virtual Port 0 */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT1 - Virtual Port 1 */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT2 - Virtual Port 2 */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT3 - Virtual Port 3 */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU Registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator Control */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPB _SFR_MEM8(0x0072) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset Controller */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - Port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++ ++/* AES - AES Crypto Module */ ++#define AES_CTRL _SFR_MEM8(0x00C0) ++#define AES_STATUS _SFR_MEM8(0x00C1) ++#define AES_STATE _SFR_MEM8(0x00C2) ++#define AES_KEY _SFR_MEM8(0x00C3) ++#define AES_INTCTRL _SFR_MEM8(0x00C4) ++ ++/* DMA - DMA Controller */ ++#define DMA_CTRL _SFR_MEM8(0x0100) ++#define DMA_INTFLAGS _SFR_MEM8(0x0103) ++#define DMA_STATUS _SFR_MEM8(0x0104) ++#define DMA_TEMP _SFR_MEM16(0x0106) ++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) ++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) ++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) ++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) ++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) ++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) ++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) ++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) ++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) ++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) ++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) ++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) ++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) ++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) ++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) ++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) ++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) ++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) ++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) ++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) ++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) ++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) ++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) ++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) ++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) ++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) ++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) ++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) ++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) ++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) ++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) ++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) ++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) ++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) ++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) ++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) ++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) ++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) ++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) ++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) ++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) ++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH4MUX _SFR_MEM8(0x0184) ++#define EVSYS_CH5MUX _SFR_MEM8(0x0185) ++#define EVSYS_CH6MUX _SFR_MEM8(0x0186) ++#define EVSYS_CH7MUX _SFR_MEM8(0x0187) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) ++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) ++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) ++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non Volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADCA - Analog to Digital Converter A */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CH1RES _SFR_MEM16(0x0212) ++#define ADCA_CH2RES _SFR_MEM16(0x0214) ++#define ADCA_CH3RES _SFR_MEM16(0x0216) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) ++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) ++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) ++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) ++#define ADCA_CH1_RES _SFR_MEM16(0x022C) ++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) ++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) ++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) ++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) ++#define ADCA_CH2_RES _SFR_MEM16(0x0234) ++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) ++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) ++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) ++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) ++#define ADCA_CH3_RES _SFR_MEM16(0x023C) ++ ++/* DACB - Digital to Analog Converter B */ ++#define DACB_CTRLA _SFR_MEM8(0x0320) ++#define DACB_CTRLB _SFR_MEM8(0x0321) ++#define DACB_CTRLC _SFR_MEM8(0x0322) ++#define DACB_EVCTRL _SFR_MEM8(0x0323) ++#define DACB_TIMCTRL _SFR_MEM8(0x0324) ++#define DACB_STATUS _SFR_MEM8(0x0325) ++#define DACB_GAINCAL _SFR_MEM8(0x0328) ++#define DACB_OFFSETCAL _SFR_MEM8(0x0329) ++#define DACB_CH0DATA _SFR_MEM16(0x0338) ++#define DACB_CH1DATA _SFR_MEM16(0x033A) ++ ++/* ACA - Analog Comparator A */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWIC - Two-Wire Interface C */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWIE - Two-Wire Interface E */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* PORTA - Port A */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORTB - Port B */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORTC - Port C */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORTD - Port D */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORTE - Port E */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORTR - Port R */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TCC0 - Timer/Counter C0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TCC1 - Timer/Counter C1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEXC - Advanced Waveform Extension C */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRESC - High-Resolution Extension C */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ ++#define USARTC1_DATA _SFR_MEM8(0x08B0) ++#define USARTC1_STATUS _SFR_MEM8(0x08B1) ++#define USARTC1_CTRLA _SFR_MEM8(0x08B3) ++#define USARTC1_CTRLB _SFR_MEM8(0x08B4) ++#define USARTC1_CTRLC _SFR_MEM8(0x08B5) ++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) ++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) ++ ++/* SPIC - Serial Peripheral Interface C */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TCD0 - Timer/Counter D0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TCD1 - Timer/Counter D1 */ ++#define TCD1_CTRLA _SFR_MEM8(0x0940) ++#define TCD1_CTRLB _SFR_MEM8(0x0941) ++#define TCD1_CTRLC _SFR_MEM8(0x0942) ++#define TCD1_CTRLD _SFR_MEM8(0x0943) ++#define TCD1_CTRLE _SFR_MEM8(0x0944) ++#define TCD1_INTCTRLA _SFR_MEM8(0x0946) ++#define TCD1_INTCTRLB _SFR_MEM8(0x0947) ++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) ++#define TCD1_CTRLFSET _SFR_MEM8(0x0949) ++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) ++#define TCD1_CTRLGSET _SFR_MEM8(0x094B) ++#define TCD1_INTFLAGS _SFR_MEM8(0x094C) ++#define TCD1_TEMP _SFR_MEM8(0x094F) ++#define TCD1_CNT _SFR_MEM16(0x0960) ++#define TCD1_PER _SFR_MEM16(0x0966) ++#define TCD1_CCA _SFR_MEM16(0x0968) ++#define TCD1_CCB _SFR_MEM16(0x096A) ++#define TCD1_PERBUF _SFR_MEM16(0x0976) ++#define TCD1_CCABUF _SFR_MEM16(0x0978) ++#define TCD1_CCBBUF _SFR_MEM16(0x097A) ++ ++/* HIRESD - High-Resolution Extension D */ ++#define HIRESD_CTRLA _SFR_MEM8(0x0990) ++ ++/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ ++#define USARTD1_DATA _SFR_MEM8(0x09B0) ++#define USARTD1_STATUS _SFR_MEM8(0x09B1) ++#define USARTD1_CTRLA _SFR_MEM8(0x09B3) ++#define USARTD1_CTRLB _SFR_MEM8(0x09B4) ++#define USARTD1_CTRLC _SFR_MEM8(0x09B5) ++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) ++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) ++ ++/* SPID - Serial Peripheral Interface D */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TCE0 - Timer/Counter E0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* HIRESE - High-Resolution Extension E */ ++#define HIRESE_CTRLA _SFR_MEM8(0x0A90) ++ ++/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR1 bit masks and bit positions */ ++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ ++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ ++ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ ++ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ ++#define PR_EBI_bp 3 /* External Bus Interface bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ ++#define PR_DAC_bp 2 /* Port A DAC bit position. */ ++ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++ ++/* PR.PRPB bit masks and bit positions */ ++/* PR_DAC_bm Predefined. */ ++/* PR_DAC_bp Predefined. */ ++ ++/* PR_ADC_bm Predefined. */ ++/* PR_ADC_bp Predefined. */ ++ ++/* PR_AC_bm Predefined. */ ++/* PR_AC_bp Predefined. */ ++ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ ++ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ ++ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ ++ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ ++#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ ++ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ ++ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ ++ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ ++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ ++ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++ ++/* DMA - DMA Controller */ ++/* DMA_CH.CTRLA bit masks and bit positions */ ++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ ++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ ++ ++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ ++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ ++ ++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ ++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ ++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ ++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ ++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ ++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ ++ ++ ++/* DMA_CH.CTRLB bit masks and bit positions */ ++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ ++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ ++ ++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ ++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ ++ ++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ ++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ ++ ++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ ++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ ++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ ++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ ++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ ++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ ++ ++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ ++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ ++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ ++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ ++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ ++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ ++ ++ ++/* DMA_CH.ADDRCTRL bit masks and bit positions */ ++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ ++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ ++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ ++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ ++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ ++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ ++ ++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ ++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ ++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ ++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ ++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ ++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ ++ ++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ ++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ ++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ ++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ ++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ ++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ ++ ++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ ++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ ++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ ++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ ++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ ++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ ++ ++ ++/* DMA_CH.TRIGSRC bit masks and bit positions */ ++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++ ++/* DMA.CTRL bit masks and bit positions */ ++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define DMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define DMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ ++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ ++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ ++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ ++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ ++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ ++ ++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ ++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ ++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ ++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ ++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ ++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ ++ ++ ++/* DMA.INTFLAGS bit masks and bit positions */ ++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++ ++/* DMA.STATUS bit masks and bit positions */ ++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ ++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ ++ ++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ ++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ ++ ++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ ++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ ++ ++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ ++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ ++ ++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ ++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ ++ ++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ ++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ ++ ++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ ++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ ++ ++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ ++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ ++ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH4MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH5MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH6MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH7MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM_gm Predefined. */ ++/* EVSYS_QDIRM_gp Predefined. */ ++/* EVSYS_QDIRM0_bm Predefined. */ ++/* EVSYS_QDIRM0_bp Predefined. */ ++/* EVSYS_QDIRM1_bm Predefined. */ ++/* EVSYS_QDIRM1_bp Predefined. */ ++ ++/* EVSYS_QDIEN_bm Predefined. */ ++/* EVSYS_QDIEN_bp Predefined. */ ++ ++/* EVSYS_QDEN_bm Predefined. */ ++/* EVSYS_QDEN_bp Predefined. */ ++ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH4CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM_gm Predefined. */ ++/* EVSYS_QDIRM_gp Predefined. */ ++/* EVSYS_QDIRM0_bm Predefined. */ ++/* EVSYS_QDIRM0_bp Predefined. */ ++/* EVSYS_QDIRM1_bm Predefined. */ ++/* EVSYS_QDIRM1_bp Predefined. */ ++ ++/* EVSYS_QDIEN_bm Predefined. */ ++/* EVSYS_QDIEN_bp Predefined. */ ++ ++/* EVSYS_QDEN_bm Predefined. */ ++/* EVSYS_QDEN_bp Predefined. */ ++ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH5CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH6CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH7CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0xFF /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ ++#define NVM_CMD7_bp 7 /* Command bit 7 position. */ ++ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ ++#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ ++#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ ++#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ ++#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ ++#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ ++#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ ++#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ ++#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ ++#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ ++#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ ++#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ ++#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ ++#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ ++#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ ++#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ ++#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ ++#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ ++#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ ++#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ ++ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ ++ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ ++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE_gm Predefined. */ ++/* AC_INTMODE_gp Predefined. */ ++/* AC_INTMODE0_bm Predefined. */ ++/* AC_INTMODE0_bp Predefined. */ ++/* AC_INTMODE1_bm Predefined. */ ++/* AC_INTMODE1_bp Predefined. */ ++ ++/* AC_INTLVL_gm Predefined. */ ++/* AC_INTLVL_gp Predefined. */ ++/* AC_INTLVL0_bm Predefined. */ ++/* AC_INTLVL0_bp Predefined. */ ++/* AC_INTLVL1_bm Predefined. */ ++/* AC_INTLVL1_bp Predefined. */ ++ ++/* AC_HSMODE_bm Predefined. */ ++/* AC_HSMODE_bp Predefined. */ ++ ++/* AC_HYSMODE_gm Predefined. */ ++/* AC_HYSMODE_gp Predefined. */ ++/* AC_HYSMODE0_bm Predefined. */ ++/* AC_HYSMODE0_bp Predefined. */ ++/* AC_HYSMODE1_bm Predefined. */ ++/* AC_HYSMODE1_bp Predefined. */ ++ ++/* AC_ENABLE_bm Predefined. */ ++/* AC_ENABLE_bp Predefined. */ ++ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS_gm Predefined. */ ++/* AC_MUXPOS_gp Predefined. */ ++/* AC_MUXPOS0_bm Predefined. */ ++/* AC_MUXPOS0_bp Predefined. */ ++/* AC_MUXPOS1_bm Predefined. */ ++/* AC_MUXPOS1_bp Predefined. */ ++/* AC_MUXPOS2_bm Predefined. */ ++/* AC_MUXPOS2_bp Predefined. */ ++ ++/* AC_MUXNEG_gm Predefined. */ ++/* AC_MUXNEG_gp Predefined. */ ++/* AC_MUXNEG0_bm Predefined. */ ++/* AC_MUXNEG0_bp Predefined. */ ++/* AC_MUXNEG1_bm Predefined. */ ++/* AC_MUXNEG1_bp Predefined. */ ++/* AC_MUXNEG2_bm Predefined. */ ++/* AC_MUXNEG2_bp Predefined. */ ++ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ ++ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ ++ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ ++ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ ++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ ++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ ++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ ++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ ++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ ++ ++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ ++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ ++ ++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ ++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ ++ ++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ ++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ ++ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ ++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ ++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ ++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ ++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ ++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ ++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ ++ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ ++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ ++ ++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ ++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ ++ ++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ ++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ ++ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++ ++/* DAC - Digital/Analog Converter */ ++/* DAC.CTRLA bit masks and bit positions */ ++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ ++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ ++ ++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ ++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ ++ ++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ ++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ ++ ++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ ++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ ++ ++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define DAC_ENABLE_bp 0 /* Enable bit position. */ ++ ++ ++/* DAC.CTRLB bit masks and bit positions */ ++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ ++#define DAC_CHSEL_gp 5 /* Channel Select group position. */ ++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ ++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ ++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ ++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ ++ ++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ ++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ ++ ++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ ++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ ++ ++ ++/* DAC.CTRLC bit masks and bit positions */ ++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ ++#define DAC_REFSEL_gp 3 /* Reference Select group position. */ ++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ ++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ ++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ ++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ ++ ++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ ++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ ++ ++ ++/* DAC.EVCTRL bit masks and bit positions */ ++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ ++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ ++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ ++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ ++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ ++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ ++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ ++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ ++ ++ ++/* DAC.TIMCTRL bit masks and bit positions */ ++#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ ++#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ ++#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ ++#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ ++#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ ++#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ ++#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ ++#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ ++ ++#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ ++#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ ++#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ ++#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ ++#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ ++#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ ++#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ ++#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ ++#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ ++#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ ++ ++ ++/* DAC.STATUS bit masks and bit positions */ ++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ ++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ ++ ++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ ++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ ++ ++ ++/* RTC - Real-Time Clounter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* EBI - External Bus Interface */ ++/* EBI_CS.CTRLA bit masks and bit positions */ ++#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ ++#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ ++#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ ++#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ ++#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ ++#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ ++#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ ++#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ ++#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ ++#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ ++#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ ++#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ ++ ++#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ ++#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ ++#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ ++#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ ++#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ ++#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ ++ ++ ++/* EBI_CS.CTRLB bit masks and bit positions */ ++#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ ++#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ ++#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ ++#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ ++#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ ++#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ ++#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ ++#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ ++ ++#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ ++#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ ++ ++#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ ++#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ ++ ++#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ ++#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ ++#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ ++#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ ++#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ ++#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ ++ ++ ++/* EBI.CTRL bit masks and bit positions */ ++#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ ++#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ ++#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ ++#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ ++#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ ++#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ ++ ++#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ ++#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ ++#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ ++#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ ++#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ ++#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ ++ ++#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ ++#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ ++#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ ++#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ ++#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ ++#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ ++ ++#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ ++#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ ++#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ ++#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ ++#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ ++#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLA bit masks and bit positions */ ++#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ ++#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ ++ ++#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ ++#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ ++ ++#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ ++#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ ++#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ ++#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ ++#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ ++#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLB bit masks and bit positions */ ++#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ ++#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ ++#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ ++#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ ++#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ ++#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ ++ ++#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ ++#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ ++#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ ++#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ ++#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ ++#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ ++#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ ++#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ ++ ++#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ ++#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ ++#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ ++#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ ++#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ ++#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ ++#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ ++#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ ++ ++ ++/* EBI.SDRAMCTRLC bit masks and bit positions */ ++#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ ++#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ ++#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ ++#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ ++#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ ++#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ ++ ++#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ ++#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ ++#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ ++#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ ++#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ ++#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ ++#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ ++#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ ++ ++#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ ++#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ ++#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ ++#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ ++#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ ++#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ ++#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ ++#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ ++ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ ++#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++ ++/* PORT - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ ++#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ ++ ++#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD_gm Predefined. */ ++/* TC0_CMD_gp Predefined. */ ++/* TC0_CMD0_bm Predefined. */ ++/* TC0_CMD0_bp Predefined. */ ++/* TC0_CMD1_bm Predefined. */ ++/* TC0_CMD1_bp Predefined. */ ++ ++/* TC0_LUPD_bm Predefined. */ ++/* TC0_LUPD_bp Predefined. */ ++ ++/* TC0_DIR_bm Predefined. */ ++/* TC0_DIR_bp Predefined. */ ++ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV_bm Predefined. */ ++/* TC0_CCDBV_bp Predefined. */ ++ ++/* TC0_CCCBV_bm Predefined. */ ++/* TC0_CCCBV_bp Predefined. */ ++ ++/* TC0_CCBBV_bm Predefined. */ ++/* TC0_CCBBV_bp Predefined. */ ++ ++/* TC0_CCABV_bm Predefined. */ ++/* TC0_CCABV_bp Predefined. */ ++ ++/* TC0_PERBV_bm Predefined. */ ++/* TC0_PERBV_bp Predefined. */ ++ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ ++#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ ++ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD_gm Predefined. */ ++/* TC1_CMD_gp Predefined. */ ++/* TC1_CMD0_bm Predefined. */ ++/* TC1_CMD0_bp Predefined. */ ++/* TC1_CMD1_bm Predefined. */ ++/* TC1_CMD1_bp Predefined. */ ++ ++/* TC1_LUPD_bm Predefined. */ ++/* TC1_LUPD_bp Predefined. */ ++ ++/* TC1_DIR_bm Predefined. */ ++/* TC1_DIR_bp Predefined. */ ++ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV_bm Predefined. */ ++/* TC1_CCBBV_bp Predefined. */ ++ ++/* TC1_CCABV_bm Predefined. */ ++/* TC1_CCABV_bp Predefined. */ ++ ++/* TC1_PERBV_bm Predefined. */ ++/* TC1_PERBV_bp Predefined. */ ++ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++ ++/* HIRES.CTRL bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL_gm Predefined. */ ++/* USART_BSEL_gp Predefined. */ ++/* USART_BSEL0_bm Predefined. */ ++/* USART_BSEL0_bp Predefined. */ ++/* USART_BSEL1_bm Predefined. */ ++/* USART_BSEL1_bp Predefined. */ ++/* USART_BSEL2_bm Predefined. */ ++/* USART_BSEL2_bp Predefined. */ ++/* USART_BSEL3_bm Predefined. */ ++/* USART_BSEL3_bp Predefined. */ ++ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++ ++/* AES - AES Module */ ++/* AES.CTRL bit masks and bit positions */ ++#define AES_START_bm 0x80 /* Start/Run bit mask. */ ++#define AES_START_bp 7 /* Start/Run bit position. */ ++ ++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ ++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ ++ ++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ ++#define AES_RESET_bp 5 /* AES Software Reset bit position. */ ++ ++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ ++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ ++ ++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ ++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ ++ ++ ++/* AES.STATUS bit masks and bit positions */ ++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ ++#define AES_ERROR_bp 7 /* AES Error bit position. */ ++ ++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ ++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ ++ ++ ++/* AES.INTCTRL bit masks and bit positions */ ++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define AES_INTLVL_gp 0 /* Interrupt level group position. */ ++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_XOSCF_vect_num 1 ++#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* DMA interrupt vectors */ ++#define DMA_CH0_vect_num 6 ++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ ++#define DMA_CH1_vect_num 7 ++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ ++#define DMA_CH2_vect_num 8 ++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ ++#define DMA_CH3_vect_num 9 ++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* USARTC1 interrupt vectors */ ++#define USARTC1_RXC_vect_num 28 ++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ ++#define USARTC1_DRE_vect_num 29 ++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ ++#define USARTC1_TXC_vect_num 30 ++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ ++ ++/* AES interrupt vectors */ ++#define AES_INT_vect_num 31 ++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* TCE1 interrupt vectors */ ++#define TCE1_OVF_vect_num 53 ++#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ ++#define TCE1_ERR_vect_num 54 ++#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ ++#define TCE1_CCA_vect_num 55 ++#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ ++#define TCE1_CCB_vect_num 56 ++#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++#define ADCA_CH1_vect_num 72 ++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ ++#define ADCA_CH2_vect_num 73 ++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ ++#define ADCA_CH3_vect_num 74 ++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD1 interrupt vectors */ ++#define TCD1_OVF_vect_num 83 ++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ ++#define TCD1_ERR_vect_num 84 ++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ ++#define TCD1_CCA_vect_num 85 ++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ ++#define TCD1_CCB_vect_num 86 ++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* USARTD1 interrupt vectors */ ++#define USARTD1_RXC_vect_num 91 ++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ ++#define USARTD1_DRE_vect_num 92 ++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ ++#define USARTD1_TXC_vect_num 93 ++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ ++ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (94 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (36864) ++#define PROGMEM_PAGE_SIZE (256) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (32768) ++#define APP_SECTION_PAGE_SIZE (256) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x07000) ++#define APPTABLE_SECTION_SIZE (4096) ++#define APPTABLE_SECTION_PAGE_SIZE (256) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x8000) ++#define BOOT_SECTION_SIZE (4096) ++#define BOOT_SECTION_PAGE_SIZE (256) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (12288) ++#define DATAMEM_PAGE_SIZE (0) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (1024) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (4096) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (1024) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define FUSE_START (0x0000) ++#define FUSE_SIZE (6) ++#define FUSE_PAGE_SIZE (0) ++#define FUSE_END (FUSE_START + FUSE_SIZE - 1) ++ ++#define LOCKBIT_START (0x0000) ++#define LOCKBIT_SIZE (1) ++#define LOCKBIT_PAGE_SIZE (0) ++#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (256) ++#define USER_SIGNATURES_PAGE_SIZE (0) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (0) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE PROGMEM_PAGE_SIZE ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define XRAMSTART EXTERNAL_SRAM_START ++#define XRAMSIZE EXTERNAL_SRAM_SIZE ++#define XRAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 */ ++#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ ++#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ ++#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ ++#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ ++#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ ++#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ ++#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ ++#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ ++#define FUSE0_DEFAULT (0xFF) ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x41 ++ ++ ++#endif /* _AVR_ATxmega32A4_H_ */ ++ diff --git a/include/avr/iox32a4u.h b/include/avr/iox32a4u.h new file mode 100644 -index 0000000..240c189 +index 0000000..cdc655d --- /dev/null +++ b/include/avr/iox32a4u.h @@ -0,0 +1,7240 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox32a4u.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA32A4U_H_INCLUDED -+#define _AVR_ATXMEGA32A4U_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -+#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -+#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -+#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -+#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -+#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -+#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -+#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -+#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -+#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -+#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -+#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -+#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -+#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -+#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -+#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -+#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -+#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -+#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -+#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -+#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -+#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -+#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+VPORT - Virtual Ports -+-------------------------------------------------------------------------- -+*/ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t USBCTRL; /* USB Control Register */ -+} CLK_t; -+ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t PRPB; /* Power Reduction Port B */ -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t PRPD; /* Power Reduction Port D */ -+ register8_t PRPE; /* Power Reduction Port E */ -+ register8_t PRPF; /* Power Reduction Port F */ -+} PR_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+/* USB Prescaler Division Factor */ -+typedef enum CLK_USBPSDIV_enum -+{ -+ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ -+ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ -+ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ -+ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ -+ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ -+ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -+} CLK_USBPSDIV_t; -+ -+/* USB Clock Source */ -+typedef enum CLK_USBSRC_enum -+{ -+ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ -+ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -+} CLK_USBSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control Register */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+/* 2 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC2MCREF_enum -+{ -+ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC2MCREF_t; -+ -+/* 32 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC32MCREF_enum -+{ -+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -+} OSC_RC32MCREF_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t JTAGUID; /* JTAG User ID */ -+ register8_t reserved_0x05; -+ register8_t MCUCR; /* MCU Control */ -+ register8_t ANAINIT; /* Analog Startup Delay */ -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t AWEXLOCK; /* AWEX Lock */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORTCFG - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t VPCTRLA; /* Virtual Port Control Register A */ -+ register8_t VPCTRLB; /* Virtual Port Control Register B */ -+ register8_t CLKEVOUT; /* Clock and Event Out Register */ -+ register8_t EBIOUT; /* EBI Output register */ -+ register8_t EVOUTSEL; /* Event Output Select */ -+} PORTCFG_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP02MAP_enum -+{ -+ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ -+ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ -+ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ -+ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ -+ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ -+ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ -+ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ -+ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ -+ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ -+ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ -+ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ -+ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ -+ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ -+ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ -+ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ -+ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -+} PORTCFG_VP02MAP_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP13MAP_enum -+{ -+ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ -+ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ -+ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ -+ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ -+ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ -+ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ -+ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ -+ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ -+ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ -+ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ -+ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ -+ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ -+ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ -+ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ -+ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ -+ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -+} PORTCFG_VP13MAP_t; -+ -+/* System Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ -+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ -+ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -+} PORTCFG_CLKOUT_t; -+ -+/* Peripheral Clock Output Select */ -+typedef enum PORTCFG_CLKOUTSEL_enum -+{ -+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -+} PORTCFG_CLKOUTSEL_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ -+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ -+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -+} PORTCFG_EVOUT_t; -+ -+/* Clock and Event Output Port */ -+typedef enum PORTCFG_CLKEVPIN_enum -+{ -+ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ -+ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -+} PORTCFG_CLKEVPIN_t; -+ -+/* EBI Address Output Port */ -+typedef enum PORTCFG_EBIADROUT_enum -+{ -+ PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ -+ PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ -+ PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ -+ PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ -+} PORTCFG_EBIADROUT_t; -+ -+/* EBI Chip Select Output Port */ -+typedef enum PORTCFG_EBICSOUT_enum -+{ -+ PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ -+} PORTCFG_EBICSOUT_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -+ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ -+ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ -+ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ -+ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AES - AES Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* AES Module */ -+typedef struct AES_struct -+{ -+ register8_t CTRL; /* AES Control Register */ -+ register8_t STATUS; /* AES Status Register */ -+ register8_t STATE; /* AES State Register */ -+ register8_t KEY; /* AES Key Register */ -+ register8_t INTCTRL; /* AES Interrupt Control Register */ -+} AES_t; -+ -+/* Interrupt level */ -+typedef enum AES_INTLVL_enum -+{ -+ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} AES_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ -+ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ -+ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ -+ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DMA - DMA Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* DMA Channel */ -+typedef struct DMA_CH_struct -+{ -+ register8_t CTRLA; /* Channel Control */ -+ register8_t CTRLB; /* Channel Control */ -+ register8_t ADDRCTRL; /* Address Control */ -+ register8_t TRIGSRC; /* Channel Trigger Source */ -+ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ -+ register8_t REPCNT; /* Channel Repeat Count */ -+ register8_t reserved_0x07; -+ register8_t SRCADDR0; /* Channel Source Address 0 */ -+ register8_t SRCADDR1; /* Channel Source Address 1 */ -+ register8_t SRCADDR2; /* Channel Source Address 2 */ -+ register8_t reserved_0x0B; -+ register8_t DESTADDR0; /* Channel Destination Address 0 */ -+ register8_t DESTADDR1; /* Channel Destination Address 1 */ -+ register8_t DESTADDR2; /* Channel Destination Address 2 */ -+ register8_t reserved_0x0F; -+} DMA_CH_t; -+ -+ -+/* DMA Controller */ -+typedef struct DMA_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t reserved_0x01; -+ register8_t reserved_0x02; -+ register8_t INTFLAGS; /* Transfer Interrupt Status */ -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x05; -+ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ DMA_CH_t CH0; /* DMA Channel 0 */ -+ DMA_CH_t CH1; /* DMA Channel 1 */ -+ DMA_CH_t CH2; /* DMA Channel 2 */ -+ DMA_CH_t CH3; /* DMA Channel 3 */ -+} DMA_t; -+ -+/* Burst mode */ -+typedef enum DMA_CH_BURSTLEN_enum -+{ -+ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ -+ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ -+ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ -+ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -+} DMA_CH_BURSTLEN_t; -+ -+/* Source address reload mode */ -+typedef enum DMA_CH_SRCRELOAD_enum -+{ -+ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ -+ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ -+ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ -+ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -+} DMA_CH_SRCRELOAD_t; -+ -+/* Source addressing mode */ -+typedef enum DMA_CH_SRCDIR_enum -+{ -+ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ -+ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ -+ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -+} DMA_CH_SRCDIR_t; -+ -+/* Destination adress reload mode */ -+typedef enum DMA_CH_DESTRELOAD_enum -+{ -+ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ -+ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ -+ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ -+ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -+} DMA_CH_DESTRELOAD_t; -+ -+/* Destination adressing mode */ -+typedef enum DMA_CH_DESTDIR_enum -+{ -+ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ -+ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ -+ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -+} DMA_CH_DESTDIR_t; -+ -+/* Transfer trigger source */ -+typedef enum DMA_CH_TRIGSRC_enum -+{ -+ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ -+ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ -+ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ -+ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ -+ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ -+ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ -+ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ -+ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ -+ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ -+ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ -+ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ -+ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ -+ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ -+ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ -+ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ -+ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ -+ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ -+ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ -+ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ -+ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ -+ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ -+ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ -+ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ -+ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ -+ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ -+ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ -+ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ -+ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ -+ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ -+ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ -+ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ -+ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ -+ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ -+ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ -+ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -+} DMA_CH_TRIGSRC_t; -+ -+/* Double buffering mode */ -+typedef enum DMA_DBUFMODE_enum -+{ -+ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ -+ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ -+ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ -+ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -+} DMA_DBUFMODE_t; -+ -+/* Priority mode */ -+typedef enum DMA_PRIMODE_enum -+{ -+ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ -+ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ -+ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ -+ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -+} DMA_PRIMODE_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_ERRINTLVL_enum -+{ -+ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ -+ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ -+ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -+} DMA_CH_ERRINTLVL_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_TRNINTLVL_enum -+{ -+ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ -+ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -+} DMA_CH_TRNINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ -+ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ -+ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ -+ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t CH4CTRL; /* Channel 4 Control Register */ -+ register8_t CH5CTRL; /* Channel 5 Control Register */ -+ register8_t CH6CTRL; /* Channel 6 Control Register */ -+ register8_t CH7CTRL; /* Channel 7 Control Register */ -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+} EVSYS_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ -+ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ -+ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ -+ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ -+ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ -+ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ -+ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ -+ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ -+ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ -+ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ -+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ -+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ -+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ -+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ -+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ -+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ -+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ -+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ -+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ -+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ -+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ -+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ -+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ -+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ -+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ -+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ -+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ -+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ -+ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ -+ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ -+ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ -+ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ -+ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ -+ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ -+ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ -+ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ -+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ -+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ -+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ -+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ -+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ -+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ -+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ -+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ -+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ -+ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ -+ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ -+ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ -+ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ -+ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ -+ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ -+ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ -+ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ -+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ -+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ -+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ -+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -+ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ -+ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ -+ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ -+ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ -+ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ -+ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ -+ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ -+ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -+ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ -+ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ -+ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ -+ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -+} EVSYS_CHMUX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ -+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ -+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ -+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ -+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} NVM_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t reserved_0x07; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ _WORDREGISTER(CH1RES); /* Channel 1 Result */ -+ _WORDREGISTER(CH2RES); /* Channel 2 Result */ -+ _WORDREGISTER(CH3RES); /* Channel 3 Result */ -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+ ADC_CH_t CH1; /* ADC Channel 1 */ -+ ADC_CH_t CH2; /* ADC Channel 2 */ -+ ADC_CH_t CH3; /* ADC Channel 3 */ -+} ADC_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -+ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+ ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 3) */ -+ ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Groud (Input Mode = 3) */ -+ ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Groud (Input Mode = 4) */ -+ ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 4) */ -+} ADC_CH_MUXNEG_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Current Limitation Mode */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ -+} ADC_CURRLIMIT_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Channel sweep selection */ -+typedef enum ADC_SWEEP_enum -+{ -+ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ -+ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ -+ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ -+ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -+} ADC_SWEEP_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ -+ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ -+ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ -+ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ -+ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ -+ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ -+ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ -+ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -+ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ -+ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ -+ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ -+ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* DMA request selection */ -+typedef enum ADC_DMASEL_enum -+{ -+ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ -+ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ -+ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ -+ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -+} ADC_DMASEL_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DAC - Digital/Analog Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Digital-to-Analog Converter */ -+typedef struct DAC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t EVCTRL; /* Event Input Control */ -+ register8_t reserved_0x04; -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0GAINCAL; /* Gain Calibration */ -+ register8_t CH0OFFSETCAL; /* Offset Calibration */ -+ register8_t CH1GAINCAL; /* Gain Calibration */ -+ register8_t CH1OFFSETCAL; /* Offset Calibration */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ -+ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -+} DAC_t; -+ -+/* Output channel selection */ -+typedef enum DAC_CHSEL_enum -+{ -+ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ -+ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ -+ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -+} DAC_CHSEL_t; -+ -+/* Reference voltage selection */ -+typedef enum DAC_REFSEL_enum -+{ -+ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ -+ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ -+ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ -+ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -+} DAC_REFSEL_t; -+ -+/* Event channel selection */ -+typedef enum DAC_EVSEL_enum -+{ -+ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ -+ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ -+ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ -+ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ -+ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ -+ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ -+ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ -+ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -+} DAC_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC - Real-Time Counter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Real-Time Counter */ -+typedef struct RTC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary register */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ _WORDREGISTER(CNT); /* Count Register */ -+ _WORDREGISTER(PER); /* Period Register */ -+ _WORDREGISTER(COMP); /* Compare Register */ -+} RTC_t; -+ -+/* Prescaler Factor */ -+typedef enum RTC_PRESCALER_enum -+{ -+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ -+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ -+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ -+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ -+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ -+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ -+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ -+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -+} RTC_PRESCALER_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC_COMPINTLVL_enum -+{ -+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC_OVFINTLVL_enum -+{ -+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+} TWI_t; -+ -+/* SDA Hold Time */ -+typedef enum TWI_SDAHOLD_enum -+{ -+ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ -+ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ -+ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ -+ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -+} TWI_SDAHOLD_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USB - USB -+-------------------------------------------------------------------------- -+*/ -+ -+/* USB Endpoint */ -+typedef struct USB_EP_struct -+{ -+ register8_t STATUS; /* Endpoint Status */ -+ register8_t CTRL; /* Endpoint Control */ -+ _WORDREGISTER(CNT); /* USB Endpoint Counter */ -+ _WORDREGISTER(DATAPTR); /* Data Pointer */ -+ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -+} USB_EP_t; -+ -+ -+/* Universal Serial Bus */ -+typedef struct USB_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t FIFOWP; /* FIFO Write Pointer Register */ -+ register8_t FIFORP; /* FIFO Read Pointer Register */ -+ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ -+ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ -+ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ -+ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t reserved_0x20; -+ register8_t reserved_0x21; -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t CAL0; /* Calibration Byte 0 */ -+ register8_t CAL1; /* Calibration Byte 1 */ -+} USB_t; -+ -+ -+/* USB Endpoint Table */ -+typedef struct USB_EP_TABLE_struct -+{ -+ USB_EP_t EP0OUT; /* Endpoint 0 */ -+ USB_EP_t EP0IN; /* Endpoint 0 */ -+ USB_EP_t EP1OUT; /* Endpoint 1 */ -+ USB_EP_t EP1IN; /* Endpoint 1 */ -+ USB_EP_t EP2OUT; /* Endpoint 2 */ -+ USB_EP_t EP2IN; /* Endpoint 2 */ -+ USB_EP_t EP3OUT; /* Endpoint 3 */ -+ USB_EP_t EP3IN; /* Endpoint 3 */ -+ USB_EP_t EP4OUT; /* Endpoint 4 */ -+ USB_EP_t EP4IN; /* Endpoint 4 */ -+ USB_EP_t EP5OUT; /* Endpoint 5 */ -+ USB_EP_t EP5IN; /* Endpoint 5 */ -+ USB_EP_t EP6OUT; /* Endpoint 6 */ -+ USB_EP_t EP6IN; /* Endpoint 6 */ -+ USB_EP_t EP7OUT; /* Endpoint 7 */ -+ USB_EP_t EP7IN; /* Endpoint 7 */ -+ USB_EP_t EP8OUT; /* Endpoint 8 */ -+ USB_EP_t EP8IN; /* Endpoint 8 */ -+ USB_EP_t EP9OUT; /* Endpoint 9 */ -+ USB_EP_t EP9IN; /* Endpoint 9 */ -+ USB_EP_t EP10OUT; /* Endpoint 10 */ -+ USB_EP_t EP10IN; /* Endpoint 10 */ -+ USB_EP_t EP11OUT; /* Endpoint 11 */ -+ USB_EP_t EP11IN; /* Endpoint 11 */ -+ USB_EP_t EP12OUT; /* Endpoint 12 */ -+ USB_EP_t EP12IN; /* Endpoint 12 */ -+ USB_EP_t EP13OUT; /* Endpoint 13 */ -+ USB_EP_t EP13IN; /* Endpoint 13 */ -+ USB_EP_t EP14OUT; /* Endpoint 14 */ -+ USB_EP_t EP14IN; /* Endpoint 14 */ -+ USB_EP_t EP15OUT; /* Endpoint 15 */ -+ USB_EP_t EP15IN; /* Endpoint 15 */ -+ register8_t reserved_0x100; -+ register8_t reserved_0x101; -+ register8_t reserved_0x102; -+ register8_t reserved_0x103; -+ register8_t reserved_0x104; -+ register8_t reserved_0x105; -+ register8_t reserved_0x106; -+ register8_t reserved_0x107; -+ register8_t reserved_0x108; -+ register8_t reserved_0x109; -+ register8_t reserved_0x10A; -+ register8_t reserved_0x10B; -+ register8_t reserved_0x10C; -+ register8_t reserved_0x10D; -+ register8_t reserved_0x10E; -+ register8_t reserved_0x10F; -+ register8_t FRAMENUML; /* Frame Number Low Byte */ -+ register8_t FRAMENUMH; /* Frame Number High Byte */ -+} USB_EP_TABLE_t; -+ -+/* Interrupt level */ -+typedef enum USB_INTLVL_enum -+{ -+ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} USB_INTLVL_t; -+ -+/* USB Endpoint Type */ -+typedef enum USB_EP_TYPE_enum -+{ -+ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ -+ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ -+ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ -+ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -+} USB_EP_TYPE_t; -+ -+/* USB Endpoint Buffersize */ -+typedef enum USB_EP_BUFSIZE_enum -+{ -+ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ -+ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ -+ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ -+ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ -+ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ -+ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ -+ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ -+ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -+} USB_EP_BUFSIZE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - I/O Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INT0MASK; /* Port Interrupt 0 Mask */ -+ register8_t INT1MASK; /* Port Interrupt 1 Mask */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t REMAP; /* I/O Port Pin Remap Register */ -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Port Interrupt 0 Level */ -+typedef enum PORT_INT0LVL_enum -+{ -+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INT0LVL_t; -+ -+/* Port Interrupt 1 Level */ -+typedef enum PORT_INT1LVL_enum -+{ -+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ -+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ -+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -+} PORT_INT1LVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 0 */ -+typedef struct TC0_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC0_t; -+ -+ -+/* 16-bit Timer/Counter 1 */ -+typedef struct TC1_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+} TC1_t; -+ -+/* Clock Selection */ -+typedef enum TC_CLKSEL_enum -+{ -+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC_CLKSEL_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC_WGMODE_enum -+{ -+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC_WGMODE_t; -+ -+/* Byte Mode */ -+typedef enum TC_BYTEM_enum -+{ -+ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ -+ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -+} TC_BYTEM_t; -+ -+/* Event Action */ -+typedef enum TC_EVACT_enum -+{ -+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ -+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ -+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ -+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ -+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ -+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC_EVSEL_enum -+{ -+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC_EVSEL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC_ERRINTLVL_enum -+{ -+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC_OVFINTLVL_enum -+{ -+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_OVFINTLVL_t; -+ -+/* Compare or Capture D Interrupt Level */ -+typedef enum TC_CCDINTLVL_enum -+{ -+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC_CCDINTLVL_t; -+ -+/* Compare or Capture C Interrupt Level */ -+typedef enum TC_CCCINTLVL_enum -+{ -+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC_CCCINTLVL_t; -+ -+/* Compare or Capture B Interrupt Level */ -+typedef enum TC_CCBINTLVL_enum -+{ -+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_CCBINTLVL_t; -+ -+/* Compare or Capture A Interrupt Level */ -+typedef enum TC_CCAINTLVL_enum -+{ -+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_CCAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC_CMD_enum -+{ -+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC2 - 16-bit Timer/Counter type 2 -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter type 2 */ -+typedef struct TC2_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t reserved_0x03; -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t reserved_0x08; -+ register8_t CTRLF; /* Control Register F */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t LCNT; /* Low Byte Count */ -+ register8_t HCNT; /* High Byte Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t LPER; /* Low Byte Period */ -+ register8_t HPER; /* High Byte Period */ -+ register8_t LCMPA; /* Low Byte Compare A */ -+ register8_t HCMPA; /* High Byte Compare A */ -+ register8_t LCMPB; /* Low Byte Compare B */ -+ register8_t HCMPB; /* High Byte Compare B */ -+ register8_t LCMPC; /* Low Byte Compare C */ -+ register8_t HCMPC; /* High Byte Compare C */ -+ register8_t LCMPD; /* Low Byte Compare D */ -+ register8_t HCMPD; /* High Byte Compare D */ -+} TC2_t; -+ -+/* Clock Selection */ -+typedef enum TC2_CLKSEL_enum -+{ -+ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC2_CLKSEL_t; -+ -+/* Byte Mode */ -+typedef enum TC2_BYTEM_enum -+{ -+ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ -+ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -+} TC2_BYTEM_t; -+ -+/* High Byte Underflow Interrupt Level */ -+typedef enum TC2_HUNFINTLVL_enum -+{ -+ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_HUNFINTLVL_t; -+ -+/* Low Byte Underflow Interrupt Level */ -+typedef enum TC2_LUNFINTLVL_enum -+{ -+ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LUNFINTLVL_t; -+ -+/* Low Byte Compare D Interrupt Level */ -+typedef enum TC2_LCMPDINTLVL_enum -+{ -+ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC2_LCMPDINTLVL_t; -+ -+/* Low Byte Compare C Interrupt Level */ -+typedef enum TC2_LCMPCINTLVL_enum -+{ -+ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC2_LCMPCINTLVL_t; -+ -+/* Low Byte Compare B Interrupt Level */ -+typedef enum TC2_LCMPBINTLVL_enum -+{ -+ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_LCMPBINTLVL_t; -+ -+/* Low Byte Compare A Interrupt Level */ -+typedef enum TC2_LCMPAINTLVL_enum -+{ -+ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LCMPAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMD_enum -+{ -+ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC2_CMD_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMDEN_enum -+{ -+ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ -+ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ -+ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -+} TC2_CMDEN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AWEX - Timer/Counter Advanced Waveform Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Advanced Waveform Extension */ -+typedef struct AWEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t FDEMASK; /* Fault Detection Event Mask */ -+ register8_t FDCTRL; /* Fault Detection Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t STATUSSET; /* Status Set Register */ -+ register8_t DTBOTH; /* Dead Time Both Sides */ -+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ -+ register8_t DTLS; /* Dead Time Low Side */ -+ register8_t DTHS; /* Dead Time High Side */ -+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ -+ register8_t DTHSBUF; /* Dead Time High Side Buffer */ -+ register8_t OUTOVEN; /* Output Override Enable */ -+} AWEX_t; -+ -+/* Fault Detect Action */ -+typedef enum AWEX_FDACT_enum -+{ -+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ -+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -+} AWEX_FDACT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+HIRES - Timer/Counter High-Resolution Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register */ -+} HIRES_t; -+ -+/* High Resolution Enable */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ -+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ -+ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ -+ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ -+ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -+} IRDA_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t reserved_0x00; -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+} NVM_FUSES_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* Timer Oscillator pin location */ -+typedef enum TOSCSEL_enum -+{ -+ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ -+ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -+} TOSCSEL_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -+} BOD_t; -+ -+/* BOD operation */ -+typedef enum BODACT_enum -+{ -+ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BODACT_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WDP_enum -+{ -+ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ -+ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ -+ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ -+ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ -+ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ -+ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ -+ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ -+ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ -+ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ -+ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ -+ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -+} WDP_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LOCKBIT - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ -+ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t USBCAL0; /* USB Calibration Byte 0 */ -+ register8_t USBCAL1; /* USB Calibration Byte 1 */ -+ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ -+ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ -+ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ -+ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ -+ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ -+ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ -+ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ -+ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ -+ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ -+ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+ register8_t reserved_0x40; -+ register8_t reserved_0x41; -+ register8_t reserved_0x42; -+ register8_t reserved_0x43; -+ register8_t reserved_0x44; -+ register8_t reserved_0x45; -+ register8_t reserved_0x46; -+ register8_t reserved_0x47; -+} NVM_PROD_SIGNATURES_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define AES (*(AES_t *) 0x00C0) /* AES Module */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -+#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -+#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -+#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -+#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -+#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ -+#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ -+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -+#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -+#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ -+#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -+#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -+#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -+#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -+#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -+#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -+#define GPIO_GPIORA _SFR_MEM8(0x000A) -+#define GPIO_GPIORB _SFR_MEM8(0x000B) -+#define GPIO_GPIORC _SFR_MEM8(0x000C) -+#define GPIO_GPIORD _SFR_MEM8(0x000D) -+#define GPIO_GPIORE _SFR_MEM8(0x000E) -+#define GPIO_GPIORF _SFR_MEM8(0x000F) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+#define GPIO_GPIO4 _SFR_MEM8(0x0004) -+#define GPIO_GPIO5 _SFR_MEM8(0x0005) -+#define GPIO_GPIO6 _SFR_MEM8(0x0006) -+#define GPIO_GPIO7 _SFR_MEM8(0x0007) -+#define GPIO_GPIO8 _SFR_MEM8(0x0008) -+#define GPIO_GPIO9 _SFR_MEM8(0x0009) -+#define GPIO_GPIOA _SFR_MEM8(0x000A) -+#define GPIO_GPIOB _SFR_MEM8(0x000B) -+#define GPIO_GPIOC _SFR_MEM8(0x000C) -+#define GPIO_GPIOD _SFR_MEM8(0x000D) -+#define GPIO_GPIOE _SFR_MEM8(0x000E) -+#define GPIO_GPIOF _SFR_MEM8(0x000F) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -+#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -+#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -+#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -+#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -+#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -+#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) -+#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) -+#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -+#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) -+#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) -+#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+#define CLK_USBCTRL _SFR_MEM8(0x0044) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* DFLL - DFLL */ -+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -+#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -+#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPB _SFR_MEM8(0x0072) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPD _SFR_MEM8(0x0074) -+#define PR_PRPE _SFR_MEM8(0x0075) -+#define PR_PRPF _SFR_MEM8(0x0076) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_JTAGUID _SFR_MEM8(0x0094) -+#define MCU_MCUCR _SFR_MEM8(0x0096) -+#define MCU_ANAINIT _SFR_MEM8(0x0097) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_AWEXLOCK _SFR_MEM8(0x0099) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) -+#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) -+ -+/* AES - AES Module */ -+#define AES_CTRL _SFR_MEM8(0x00C0) -+#define AES_STATUS _SFR_MEM8(0x00C1) -+#define AES_STATE _SFR_MEM8(0x00C2) -+#define AES_KEY _SFR_MEM8(0x00C3) -+#define AES_INTCTRL _SFR_MEM8(0x00C4) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* DMA - DMA Controller */ -+#define DMA_CTRL _SFR_MEM8(0x0100) -+#define DMA_INTFLAGS _SFR_MEM8(0x0103) -+#define DMA_STATUS _SFR_MEM8(0x0104) -+#define DMA_TEMP _SFR_MEM16(0x0106) -+#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -+#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -+#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -+#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -+#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -+#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -+#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -+#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -+#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -+#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -+#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -+#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -+#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -+#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -+#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -+#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -+#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -+#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -+#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -+#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -+#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -+#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -+#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -+#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -+#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -+#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -+#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -+#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -+#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -+#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -+#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -+#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -+#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -+#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -+#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -+#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -+#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -+#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -+#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -+#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -+#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -+#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -+#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -+#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -+#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -+#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -+#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -+#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -+#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -+#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -+#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -+#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -+#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -+#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCA_CTRLA _SFR_MEM8(0x0200) -+#define ADCA_CTRLB _SFR_MEM8(0x0201) -+#define ADCA_REFCTRL _SFR_MEM8(0x0202) -+#define ADCA_EVCTRL _SFR_MEM8(0x0203) -+#define ADCA_PRESCALER _SFR_MEM8(0x0204) -+#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -+#define ADCA_TEMP _SFR_MEM8(0x0207) -+#define ADCA_CAL _SFR_MEM16(0x020C) -+#define ADCA_CH0RES _SFR_MEM16(0x0210) -+#define ADCA_CH1RES _SFR_MEM16(0x0212) -+#define ADCA_CH2RES _SFR_MEM16(0x0214) -+#define ADCA_CH3RES _SFR_MEM16(0x0216) -+#define ADCA_CMP _SFR_MEM16(0x0218) -+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -+#define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -+#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -+#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -+#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -+#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -+#define ADCA_CH1_RES _SFR_MEM16(0x022C) -+#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) -+#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -+#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -+#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -+#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -+#define ADCA_CH2_RES _SFR_MEM16(0x0234) -+#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) -+#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -+#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -+#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -+#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -+#define ADCA_CH3_RES _SFR_MEM16(0x023C) -+#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) -+ -+/* DAC - Digital-to-Analog Converter */ -+#define DACB_CTRLA _SFR_MEM8(0x0320) -+#define DACB_CTRLB _SFR_MEM8(0x0321) -+#define DACB_CTRLC _SFR_MEM8(0x0322) -+#define DACB_EVCTRL _SFR_MEM8(0x0323) -+#define DACB_STATUS _SFR_MEM8(0x0325) -+#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) -+#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) -+#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) -+#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) -+#define DACB_CH0DATA _SFR_MEM16(0x0338) -+#define DACB_CH1DATA _SFR_MEM16(0x033A) -+ -+/* AC - Analog Comparator */ -+#define ACA_AC0CTRL _SFR_MEM8(0x0380) -+#define ACA_AC1CTRL _SFR_MEM8(0x0381) -+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -+#define ACA_CTRLA _SFR_MEM8(0x0384) -+#define ACA_CTRLB _SFR_MEM8(0x0385) -+#define ACA_WINCTRL _SFR_MEM8(0x0386) -+#define ACA_STATUS _SFR_MEM8(0x0387) -+ -+/* RTC - Real-Time Counter */ -+#define RTC_CTRL _SFR_MEM8(0x0400) -+#define RTC_STATUS _SFR_MEM8(0x0401) -+#define RTC_INTCTRL _SFR_MEM8(0x0402) -+#define RTC_INTFLAGS _SFR_MEM8(0x0403) -+#define RTC_TEMP _SFR_MEM8(0x0404) -+#define RTC_CNT _SFR_MEM16(0x0408) -+#define RTC_PER _SFR_MEM16(0x040A) -+#define RTC_COMP _SFR_MEM16(0x040C) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIE_CTRL _SFR_MEM8(0x04A0) -+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -+ -+/* USB - Universal Serial Bus */ -+#define USB_CTRLA _SFR_MEM8(0x04C0) -+#define USB_CTRLB _SFR_MEM8(0x04C1) -+#define USB_STATUS _SFR_MEM8(0x04C2) -+#define USB_ADDR _SFR_MEM8(0x04C3) -+#define USB_FIFOWP _SFR_MEM8(0x04C4) -+#define USB_FIFORP _SFR_MEM8(0x04C5) -+#define USB_EPPTR _SFR_MEM16(0x04C6) -+#define USB_INTCTRLA _SFR_MEM8(0x04C8) -+#define USB_INTCTRLB _SFR_MEM8(0x04C9) -+#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -+#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -+#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -+#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -+#define USB_CAL0 _SFR_MEM8(0x04FA) -+#define USB_CAL1 _SFR_MEM8(0x04FB) -+ -+/* PORT - I/O Ports */ -+#define PORTA_DIR _SFR_MEM8(0x0600) -+#define PORTA_DIRSET _SFR_MEM8(0x0601) -+#define PORTA_DIRCLR _SFR_MEM8(0x0602) -+#define PORTA_DIRTGL _SFR_MEM8(0x0603) -+#define PORTA_OUT _SFR_MEM8(0x0604) -+#define PORTA_OUTSET _SFR_MEM8(0x0605) -+#define PORTA_OUTCLR _SFR_MEM8(0x0606) -+#define PORTA_OUTTGL _SFR_MEM8(0x0607) -+#define PORTA_IN _SFR_MEM8(0x0608) -+#define PORTA_INTCTRL _SFR_MEM8(0x0609) -+#define PORTA_INT0MASK _SFR_MEM8(0x060A) -+#define PORTA_INT1MASK _SFR_MEM8(0x060B) -+#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_REMAP _SFR_MEM8(0x060E) -+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -+ -+/* PORT - I/O Ports */ -+#define PORTB_DIR _SFR_MEM8(0x0620) -+#define PORTB_DIRSET _SFR_MEM8(0x0621) -+#define PORTB_DIRCLR _SFR_MEM8(0x0622) -+#define PORTB_DIRTGL _SFR_MEM8(0x0623) -+#define PORTB_OUT _SFR_MEM8(0x0624) -+#define PORTB_OUTSET _SFR_MEM8(0x0625) -+#define PORTB_OUTCLR _SFR_MEM8(0x0626) -+#define PORTB_OUTTGL _SFR_MEM8(0x0627) -+#define PORTB_IN _SFR_MEM8(0x0628) -+#define PORTB_INTCTRL _SFR_MEM8(0x0629) -+#define PORTB_INT0MASK _SFR_MEM8(0x062A) -+#define PORTB_INT1MASK _SFR_MEM8(0x062B) -+#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -+#define PORTB_REMAP _SFR_MEM8(0x062E) -+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INT0MASK _SFR_MEM8(0x064A) -+#define PORTC_INT1MASK _SFR_MEM8(0x064B) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INT0MASK _SFR_MEM8(0x066A) -+#define PORTD_INT1MASK _SFR_MEM8(0x066B) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTE_DIR _SFR_MEM8(0x0680) -+#define PORTE_DIRSET _SFR_MEM8(0x0681) -+#define PORTE_DIRCLR _SFR_MEM8(0x0682) -+#define PORTE_DIRTGL _SFR_MEM8(0x0683) -+#define PORTE_OUT _SFR_MEM8(0x0684) -+#define PORTE_OUTSET _SFR_MEM8(0x0685) -+#define PORTE_OUTCLR _SFR_MEM8(0x0686) -+#define PORTE_OUTTGL _SFR_MEM8(0x0687) -+#define PORTE_IN _SFR_MEM8(0x0688) -+#define PORTE_INTCTRL _SFR_MEM8(0x0689) -+#define PORTE_INT0MASK _SFR_MEM8(0x068A) -+#define PORTE_INT1MASK _SFR_MEM8(0x068B) -+#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -+#define PORTE_REMAP _SFR_MEM8(0x068E) -+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -+#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCC0_CTRLA _SFR_MEM8(0x0800) -+#define TCC0_CTRLB _SFR_MEM8(0x0801) -+#define TCC0_CTRLC _SFR_MEM8(0x0802) -+#define TCC0_CTRLD _SFR_MEM8(0x0803) -+#define TCC0_CTRLE _SFR_MEM8(0x0804) -+#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -+#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -+#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -+#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC0_TEMP _SFR_MEM8(0x080F) -+#define TCC0_CNT _SFR_MEM16(0x0820) -+#define TCC0_PER _SFR_MEM16(0x0826) -+#define TCC0_CCA _SFR_MEM16(0x0828) -+#define TCC0_CCB _SFR_MEM16(0x082A) -+#define TCC0_CCC _SFR_MEM16(0x082C) -+#define TCC0_CCD _SFR_MEM16(0x082E) -+#define TCC0_PERBUF _SFR_MEM16(0x0836) -+#define TCC0_CCABUF _SFR_MEM16(0x0838) -+#define TCC0_CCBBUF _SFR_MEM16(0x083A) -+#define TCC0_CCCBUF _SFR_MEM16(0x083C) -+#define TCC0_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCC2_CTRLA _SFR_MEM8(0x0800) -+#define TCC2_CTRLB _SFR_MEM8(0x0801) -+#define TCC2_CTRLC _SFR_MEM8(0x0802) -+#define TCC2_CTRLE _SFR_MEM8(0x0804) -+#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC2_CTRLF _SFR_MEM8(0x0809) -+#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC2_LCNT _SFR_MEM8(0x0820) -+#define TCC2_HCNT _SFR_MEM8(0x0821) -+#define TCC2_LPER _SFR_MEM8(0x0826) -+#define TCC2_HPER _SFR_MEM8(0x0827) -+#define TCC2_LCMPA _SFR_MEM8(0x0828) -+#define TCC2_HCMPA _SFR_MEM8(0x0829) -+#define TCC2_LCMPB _SFR_MEM8(0x082A) -+#define TCC2_HCMPB _SFR_MEM8(0x082B) -+#define TCC2_LCMPC _SFR_MEM8(0x082C) -+#define TCC2_HCMPC _SFR_MEM8(0x082D) -+#define TCC2_LCMPD _SFR_MEM8(0x082E) -+#define TCC2_HCMPD _SFR_MEM8(0x082F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCC1_CTRLA _SFR_MEM8(0x0840) -+#define TCC1_CTRLB _SFR_MEM8(0x0841) -+#define TCC1_CTRLC _SFR_MEM8(0x0842) -+#define TCC1_CTRLD _SFR_MEM8(0x0843) -+#define TCC1_CTRLE _SFR_MEM8(0x0844) -+#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -+#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -+#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -+#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC1_TEMP _SFR_MEM8(0x084F) -+#define TCC1_CNT _SFR_MEM16(0x0860) -+#define TCC1_PER _SFR_MEM16(0x0866) -+#define TCC1_CCA _SFR_MEM16(0x0868) -+#define TCC1_CCB _SFR_MEM16(0x086A) -+#define TCC1_PERBUF _SFR_MEM16(0x0876) -+#define TCC1_CCABUF _SFR_MEM16(0x0878) -+#define TCC1_CCBBUF _SFR_MEM16(0x087A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXC_CTRL _SFR_MEM8(0x0880) -+#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -+#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -+#define AWEXC_STATUS _SFR_MEM8(0x0884) -+#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -+#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -+#define AWEXC_DTLS _SFR_MEM8(0x0888) -+#define AWEXC_DTHS _SFR_MEM8(0x0889) -+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x0890) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08A0) -+#define USARTC0_STATUS _SFR_MEM8(0x08A1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -+#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -+#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC1_DATA _SFR_MEM8(0x08B0) -+#define USARTC1_STATUS _SFR_MEM8(0x08B1) -+#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -+#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -+#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -+#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -+#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIC_CTRL _SFR_MEM8(0x08C0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -+#define SPIC_STATUS _SFR_MEM8(0x08C2) -+#define SPIC_DATA _SFR_MEM8(0x08C3) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCD0_CTRLA _SFR_MEM8(0x0900) -+#define TCD0_CTRLB _SFR_MEM8(0x0901) -+#define TCD0_CTRLC _SFR_MEM8(0x0902) -+#define TCD0_CTRLD _SFR_MEM8(0x0903) -+#define TCD0_CTRLE _SFR_MEM8(0x0904) -+#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -+#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -+#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -+#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -+#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD0_TEMP _SFR_MEM8(0x090F) -+#define TCD0_CNT _SFR_MEM16(0x0920) -+#define TCD0_PER _SFR_MEM16(0x0926) -+#define TCD0_CCA _SFR_MEM16(0x0928) -+#define TCD0_CCB _SFR_MEM16(0x092A) -+#define TCD0_CCC _SFR_MEM16(0x092C) -+#define TCD0_CCD _SFR_MEM16(0x092E) -+#define TCD0_PERBUF _SFR_MEM16(0x0936) -+#define TCD0_CCABUF _SFR_MEM16(0x0938) -+#define TCD0_CCBBUF _SFR_MEM16(0x093A) -+#define TCD0_CCCBUF _SFR_MEM16(0x093C) -+#define TCD0_CCDBUF _SFR_MEM16(0x093E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCD2_CTRLA _SFR_MEM8(0x0900) -+#define TCD2_CTRLB _SFR_MEM8(0x0901) -+#define TCD2_CTRLC _SFR_MEM8(0x0902) -+#define TCD2_CTRLE _SFR_MEM8(0x0904) -+#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD2_CTRLF _SFR_MEM8(0x0909) -+#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD2_LCNT _SFR_MEM8(0x0920) -+#define TCD2_HCNT _SFR_MEM8(0x0921) -+#define TCD2_LPER _SFR_MEM8(0x0926) -+#define TCD2_HPER _SFR_MEM8(0x0927) -+#define TCD2_LCMPA _SFR_MEM8(0x0928) -+#define TCD2_HCMPA _SFR_MEM8(0x0929) -+#define TCD2_LCMPB _SFR_MEM8(0x092A) -+#define TCD2_HCMPB _SFR_MEM8(0x092B) -+#define TCD2_LCMPC _SFR_MEM8(0x092C) -+#define TCD2_HCMPC _SFR_MEM8(0x092D) -+#define TCD2_LCMPD _SFR_MEM8(0x092E) -+#define TCD2_HCMPD _SFR_MEM8(0x092F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCD1_CTRLA _SFR_MEM8(0x0940) -+#define TCD1_CTRLB _SFR_MEM8(0x0941) -+#define TCD1_CTRLC _SFR_MEM8(0x0942) -+#define TCD1_CTRLD _SFR_MEM8(0x0943) -+#define TCD1_CTRLE _SFR_MEM8(0x0944) -+#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -+#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -+#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -+#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -+#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -+#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -+#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -+#define TCD1_TEMP _SFR_MEM8(0x094F) -+#define TCD1_CNT _SFR_MEM16(0x0960) -+#define TCD1_PER _SFR_MEM16(0x0966) -+#define TCD1_CCA _SFR_MEM16(0x0968) -+#define TCD1_CCB _SFR_MEM16(0x096A) -+#define TCD1_PERBUF _SFR_MEM16(0x0976) -+#define TCD1_CCABUF _SFR_MEM16(0x0978) -+#define TCD1_CCBBUF _SFR_MEM16(0x097A) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESD_CTRLA _SFR_MEM8(0x0990) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD0_DATA _SFR_MEM8(0x09A0) -+#define USARTD0_STATUS _SFR_MEM8(0x09A1) -+#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -+#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -+#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD1_DATA _SFR_MEM8(0x09B0) -+#define USARTD1_STATUS _SFR_MEM8(0x09B1) -+#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -+#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -+#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -+#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -+#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPID_CTRL _SFR_MEM8(0x09C0) -+#define SPID_INTCTRL _SFR_MEM8(0x09C1) -+#define SPID_STATUS _SFR_MEM8(0x09C2) -+#define SPID_DATA _SFR_MEM8(0x09C3) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCE0_CTRLA _SFR_MEM8(0x0A00) -+#define TCE0_CTRLB _SFR_MEM8(0x0A01) -+#define TCE0_CTRLC _SFR_MEM8(0x0A02) -+#define TCE0_CTRLD _SFR_MEM8(0x0A03) -+#define TCE0_CTRLE _SFR_MEM8(0x0A04) -+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE0_TEMP _SFR_MEM8(0x0A0F) -+#define TCE0_CNT _SFR_MEM16(0x0A20) -+#define TCE0_PER _SFR_MEM16(0x0A26) -+#define TCE0_CCA _SFR_MEM16(0x0A28) -+#define TCE0_CCB _SFR_MEM16(0x0A2A) -+#define TCE0_CCC _SFR_MEM16(0x0A2C) -+#define TCE0_CCD _SFR_MEM16(0x0A2E) -+#define TCE0_PERBUF _SFR_MEM16(0x0A36) -+#define TCE0_CCABUF _SFR_MEM16(0x0A38) -+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESE_CTRLA _SFR_MEM8(0x0A90) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE0_DATA _SFR_MEM8(0x0AA0) -+#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -+#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -+#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -+#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -+#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -+#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* VPORT - Virtual Ports */ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* CLK.USBCTRL bit masks and bit positions */ -+#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -+#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -+#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -+#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -+#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -+#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -+#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -+#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ -+ -+#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -+#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -+#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ -+ -+#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_USB_bm 0x40 /* USB bit mask. */ -+#define PR_USB_bp 6 /* USB bit position. */ -+ -+#define PR_AES_bm 0x10 /* AES bit mask. */ -+#define PR_AES_bp 4 /* AES bit position. */ -+ -+#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -+#define PR_EBI_bp 3 /* External Bus Interface bit position. */ -+ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -+#define PR_DMA_bp 0 /* DMA-Controller bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -+#define PR_DAC_bp 2 /* Port A DAC bit position. */ -+ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPB bit masks and bit positions */ -+/* PR_DAC Predefined. */ -+/* PR_DAC Predefined. */ -+ -+/* PR_ADC Predefined. */ -+/* PR_ADC Predefined. */ -+ -+/* PR_AC Predefined. */ -+/* PR_AC Predefined. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -+#define PR_USART1_bp 5 /* Port C USART1 bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -+#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ -+ -+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -+ -+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ -+ -+/* PR.PRPD bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPE bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPF bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -+#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -+#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ -+ -+#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ -+ -+#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -+#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.MCUCR bit masks and bit positions */ -+#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -+#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ -+ -+/* MCU.ANAINIT bit masks and bit positions */ -+#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -+#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -+#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -+#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -+#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -+#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ -+ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -+#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ -+ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.AWEXLOCK bit masks and bit positions */ -+#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ -+#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ -+ -+#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -+#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ -+ -+#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ -+#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ -+ -+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* PORTCFG - Port Configuration */ -+/* PORTCFG.VPCTRLA bit masks and bit positions */ -+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ -+ -+/* PORTCFG.VPCTRLB bit masks and bit positions */ -+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ -+ -+/* PORTCFG.CLKEVOUT bit masks and bit positions */ -+#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ -+ -+#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -+#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -+#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -+#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -+#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -+#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ -+ -+#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -+#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ -+ -+#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -+#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ -+ -+/* PORTCFG.EBIOUT bit masks and bit positions */ -+#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ -+#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ -+#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ -+#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ -+#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ -+#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ -+ -+#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ -+#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ -+#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ -+#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ -+#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ -+#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ -+ -+/* PORTCFG.EVOUTSEL bit masks and bit positions */ -+#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -+#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -+#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -+#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -+#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -+#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -+#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -+#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ -+ -+/* AES - AES Module */ -+/* AES.CTRL bit masks and bit positions */ -+#define AES_START_bm 0x80 /* Start/Run bit mask. */ -+#define AES_START_bp 7 /* Start/Run bit position. */ -+ -+#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -+#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ -+ -+#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -+#define AES_RESET_bp 5 /* AES Software Reset bit position. */ -+ -+#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -+#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ -+ -+#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -+#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ -+ -+/* AES.STATUS bit masks and bit positions */ -+#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -+#define AES_ERROR_bp 7 /* AES Error bit position. */ -+ -+#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -+#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ -+ -+/* AES.INTCTRL bit masks and bit positions */ -+#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -+#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* DMA - DMA Controller */ -+/* DMA_CH.CTRLA bit masks and bit positions */ -+#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -+#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ -+ -+#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -+#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ -+ -+#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -+#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ -+ -+#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -+#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ -+ -+#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -+#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ -+ -+#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -+#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -+#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -+#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -+#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -+#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ -+ -+/* DMA_CH.CTRLB bit masks and bit positions */ -+#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -+#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ -+ -+#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -+#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ -+ -+#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -+#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ -+ -+#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -+#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -+#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -+#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -+#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -+#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ -+ -+#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -+#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -+#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -+#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -+#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -+#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ -+ -+/* DMA_CH.ADDRCTRL bit masks and bit positions */ -+#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -+#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -+#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -+#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -+#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -+#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ -+ -+#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -+#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -+#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -+#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -+#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -+#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ -+ -+#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -+#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -+#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -+#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -+#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -+#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ -+ -+#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -+#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -+#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -+#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -+#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -+#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ -+ -+/* DMA_CH.TRIGSRC bit masks and bit positions */ -+#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -+#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -+#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -+#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -+#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -+#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -+#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -+#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -+#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -+#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -+#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -+#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -+#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -+#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -+#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -+#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -+#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -+#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ -+ -+/* DMA.CTRL bit masks and bit positions */ -+#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -+#define DMA_ENABLE_bp 7 /* Enable bit position. */ -+ -+#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -+#define DMA_RESET_bp 6 /* Software Reset bit position. */ -+ -+#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -+#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -+#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -+#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -+#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -+#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ -+ -+#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -+#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -+#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -+#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -+#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -+#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ -+ -+/* DMA.INTFLAGS bit masks and bit positions */ -+#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ -+ -+/* DMA.STATUS bit masks and bit positions */ -+#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -+#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ -+ -+#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -+#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ -+ -+#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -+#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ -+ -+#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -+#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ -+ -+#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -+#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ -+ -+#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -+#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ -+ -+#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -+#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ -+ -+#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -+#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH4MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH5MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH6MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH7MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_QDIRM Predefined. */ -+/* EVSYS_QDIRM Predefined. */ -+ -+/* EVSYS_QDIEN Predefined. */ -+/* EVSYS_QDIEN Predefined. */ -+ -+/* EVSYS_QDEN Predefined. */ -+/* EVSYS_QDEN Predefined. */ -+ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH4CTRL bit masks and bit positions */ -+/* EVSYS_QDIRM Predefined. */ -+/* EVSYS_QDIRM Predefined. */ -+ -+/* EVSYS_QDIEN Predefined. */ -+/* EVSYS_QDIEN Predefined. */ -+ -+/* EVSYS_QDEN Predefined. */ -+/* EVSYS_QDEN Predefined. */ -+ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH5CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH6CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH7CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0x7F /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ -+ -+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ -+ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -+#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ -+#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -+#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -+#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -+#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -+#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -+#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -+#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -+#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -+#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -+#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ -+ -+#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -+#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -+#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -+#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -+#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -+#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -+#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -+#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -+#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -+#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -+#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -+#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -+#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -+#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -+#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ -+ -+#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -+#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ -+ -+#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -+#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ -+ -+#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -+#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ -+ -+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -+#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ -+#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ -+ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -+#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -+#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -+#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -+#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -+#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ -+ -+#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -+#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -+#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ -+ -+#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -+#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ -+ -+#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -+#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ -+ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* DAC - Digital/Analog Converter */ -+/* DAC.CTRLA bit masks and bit positions */ -+#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -+#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ -+ -+#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -+#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ -+ -+#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -+#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ -+ -+#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -+#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ -+ -+#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define DAC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* DAC.CTRLB bit masks and bit positions */ -+#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -+#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -+#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -+#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -+#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -+#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ -+ -+#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -+#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ -+ -+#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -+#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ -+ -+/* DAC.CTRLC bit masks and bit positions */ -+#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -+#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -+#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -+#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -+#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -+#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ -+ -+#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -+#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ -+ -+/* DAC.EVCTRL bit masks and bit positions */ -+#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -+#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ -+ -+#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -+#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -+#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -+#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -+#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -+#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -+#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -+#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ -+ -+/* DAC.STATUS bit masks and bit positions */ -+#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -+#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ -+ -+#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -+#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ -+ -+/* DAC.CH0GAINCAL bit masks and bit positions */ -+#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -+#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -+#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -+#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -+#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -+#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -+#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -+#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -+#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -+#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -+#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -+#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -+#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -+#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -+#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -+#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ -+ -+/* DAC.CH0OFFSETCAL bit masks and bit positions */ -+#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -+#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -+#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -+#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -+#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -+#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -+#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -+#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -+#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -+#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -+#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -+#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -+#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -+#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -+#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -+#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ -+ -+/* DAC.CH1GAINCAL bit masks and bit positions */ -+#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -+#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -+#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -+#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -+#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -+#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -+#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -+#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -+#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -+#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -+#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -+#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -+#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -+#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -+#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -+#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ -+ -+/* DAC.CH1OFFSETCAL bit masks and bit positions */ -+#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -+#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -+#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -+#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -+#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -+#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -+#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -+#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -+#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -+#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -+#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -+#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -+#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -+#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -+#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -+#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -+#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HSMODE Predefined. */ -+/* AC_HSMODE Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* RTC - Real-Time Counter */ -+/* RTC.CTRL bit masks and bit positions */ -+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ -+ -+/* RTC.STATUS bit masks and bit positions */ -+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC.INTCTRL bit masks and bit positions */ -+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC.INTFLAGS bit masks and bit positions */ -+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* USB - USB */ -+/* USB_EP.STATUS bit masks and bit positions */ -+#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -+#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ -+ -+#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -+#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ -+ -+#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -+#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ -+ -+#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -+#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ -+ -+#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -+#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ -+ -+#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -+#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ -+ -+#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -+#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ -+ -+#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -+#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ -+ -+#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ -+ -+#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ -+ -+#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -+#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ -+ -+/* USB_EP.CTRL bit masks and bit positions */ -+#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -+#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -+#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -+#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -+#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -+#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ -+ -+#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -+#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ -+ -+#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -+#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ -+ -+#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -+#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ -+ -+#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -+#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ -+ -+#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -+#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -+#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -+#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -+#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -+#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -+#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -+#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ -+ -+/* USB_EP.CNT bit masks and bit positions */ -+#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -+#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ -+ -+/* USB.CTRLA bit masks and bit positions */ -+#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -+#define USB_ENABLE_bp 7 /* USB Enable bit position. */ -+ -+#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -+#define USB_SPEED_bp 6 /* Speed Select bit position. */ -+ -+#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -+#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ -+ -+#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -+#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ -+ -+#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -+#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -+#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -+#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -+#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -+#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -+#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -+#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -+#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -+#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ -+ -+/* USB.CTRLB bit masks and bit positions */ -+#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -+#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ -+ -+#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -+#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ -+ -+#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -+#define USB_GNACK_bp 1 /* Global NACK bit position. */ -+ -+#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -+#define USB_ATTACH_bp 0 /* Attach bit position. */ -+ -+/* USB.STATUS bit masks and bit positions */ -+#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -+#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ -+ -+#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -+#define USB_RESUME_bp 2 /* Resume bit position. */ -+ -+#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -+#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ -+ -+#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -+#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ -+ -+/* USB.ADDR bit masks and bit positions */ -+#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -+#define USB_ADDR_gp 0 /* Device Address group position. */ -+#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -+#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -+#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -+#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -+#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -+#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -+#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -+#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -+#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -+#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -+#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -+#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -+#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -+#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ -+ -+/* USB.FIFOWP bit masks and bit positions */ -+#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -+#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -+#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -+#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -+#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -+#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -+#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -+#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -+#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -+#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -+#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -+#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ -+ -+/* USB.FIFORP bit masks and bit positions */ -+#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -+#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -+#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -+#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -+#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -+#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -+#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -+#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -+#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -+#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -+#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -+#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ -+ -+/* USB.INTCTRLA bit masks and bit positions */ -+#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -+#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ -+ -+#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -+#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ -+ -+#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -+#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ -+ -+#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -+#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ -+ -+#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* USB.INTCTRLB bit masks and bit positions */ -+#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -+#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ -+ -+#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -+#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ -+ -+/* USB.INTFLAGSACLR bit masks and bit positions */ -+#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -+#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ -+ -+#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -+#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ -+ -+#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -+#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ -+ -+#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -+#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ -+ -+#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -+#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ -+ -+#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -+#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ -+ -+#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -+#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ -+ -+#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -+#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSASET bit masks and bit positions */ -+/* USB_SOFIF Predefined. */ -+/* USB_SOFIF Predefined. */ -+ -+/* USB_SUSPENDIF Predefined. */ -+/* USB_SUSPENDIF Predefined. */ -+ -+/* USB_RESUMEIF Predefined. */ -+/* USB_RESUMEIF Predefined. */ -+ -+/* USB_RSTIF Predefined. */ -+/* USB_RSTIF Predefined. */ -+ -+/* USB_CRCIF Predefined. */ -+/* USB_CRCIF Predefined. */ -+ -+/* USB_UNFIF Predefined. */ -+/* USB_UNFIF Predefined. */ -+ -+/* USB_OVFIF Predefined. */ -+/* USB_OVFIF Predefined. */ -+ -+/* USB_STALLIF Predefined. */ -+/* USB_STALLIF Predefined. */ -+ -+/* USB.INTFLAGSBCLR bit masks and bit positions */ -+#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -+#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ -+ -+#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -+#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSBSET bit masks and bit positions */ -+/* USB_TRNIF Predefined. */ -+/* USB_TRNIF Predefined. */ -+ -+/* USB_SETUPIF Predefined. */ -+/* USB_SETUPIF Predefined. */ -+ -+/* PORT - I/O Port Configuration */ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ -+ -+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -+#define PORT_SPI_bp 5 /* SPI bit position. */ -+ -+#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -+#define PORT_USART0_bp 4 /* USART0 bit position. */ -+ -+#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -+#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ -+ -+#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -+#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ -+ -+#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -+#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ -+ -+#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -+#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ -+ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC0.CTRLA bit masks and bit positions */ -+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC0.CTRLB bit masks and bit positions */ -+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ -+ -+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ -+ -+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC0.CTRLC bit masks and bit positions */ -+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ -+ -+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ -+ -+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC0.CTRLD bit masks and bit positions */ -+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC0_EVACT_gp 5 /* Event Action group position. */ -+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC0.CTRLE bit masks and bit positions */ -+#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC0.INTCTRLA bit masks and bit positions */ -+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC0.INTCTRLB bit masks and bit positions */ -+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ -+ -+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ -+ -+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC0.CTRLFCLR bit masks and bit positions */ -+#define TC0_CMD_gm 0x0C /* Command group mask. */ -+#define TC0_CMD_gp 2 /* Command group position. */ -+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC0_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC0_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC0_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC0.CTRLFSET bit masks and bit positions */ -+/* TC0_CMD Predefined. */ -+/* TC0_CMD Predefined. */ -+ -+/* TC0_LUPD Predefined. */ -+/* TC0_LUPD Predefined. */ -+ -+/* TC0_DIR Predefined. */ -+/* TC0_DIR Predefined. */ -+ -+/* TC0.CTRLGCLR bit masks and bit positions */ -+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ -+ -+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ -+ -+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC0.CTRLGSET bit masks and bit positions */ -+/* TC0_CCDBV Predefined. */ -+/* TC0_CCDBV Predefined. */ -+ -+/* TC0_CCCBV Predefined. */ -+/* TC0_CCCBV Predefined. */ -+ -+/* TC0_CCBBV Predefined. */ -+/* TC0_CCBBV Predefined. */ -+ -+/* TC0_CCABV Predefined. */ -+/* TC0_CCABV Predefined. */ -+ -+/* TC0_PERBV Predefined. */ -+/* TC0_PERBV Predefined. */ -+ -+/* TC0.INTFLAGS bit masks and bit positions */ -+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ -+ -+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ -+ -+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC1.CTRLA bit masks and bit positions */ -+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC1.CTRLB bit masks and bit positions */ -+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC1.CTRLC bit masks and bit positions */ -+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC1.CTRLD bit masks and bit positions */ -+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC1_EVACT_gp 5 /* Event Action group position. */ -+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC1.CTRLE bit masks and bit positions */ -+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ -+ -+/* TC1.INTCTRLA bit masks and bit positions */ -+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC1.INTCTRLB bit masks and bit positions */ -+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC1.CTRLFCLR bit masks and bit positions */ -+#define TC1_CMD_gm 0x0C /* Command group mask. */ -+#define TC1_CMD_gp 2 /* Command group position. */ -+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC1_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC1_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC1_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC1.CTRLFSET bit masks and bit positions */ -+/* TC1_CMD Predefined. */ -+/* TC1_CMD Predefined. */ -+ -+/* TC1_LUPD Predefined. */ -+/* TC1_LUPD Predefined. */ -+ -+/* TC1_DIR Predefined. */ -+/* TC1_DIR Predefined. */ -+ -+/* TC1.CTRLGCLR bit masks and bit positions */ -+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC1.CTRLGSET bit masks and bit positions */ -+/* TC1_CCBBV Predefined. */ -+/* TC1_CCBBV Predefined. */ -+ -+/* TC1_CCABV Predefined. */ -+/* TC1_CCABV Predefined. */ -+ -+/* TC1_PERBV Predefined. */ -+/* TC1_PERBV Predefined. */ -+ -+/* TC1.INTFLAGS bit masks and bit positions */ -+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+/* TC2.CTRLA bit masks and bit positions */ -+#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC2.CTRLB bit masks and bit positions */ -+#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -+#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ -+ -+#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -+#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ -+ -+#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -+#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ -+ -+#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -+#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ -+ -+#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -+#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ -+ -+#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -+#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ -+ -+#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -+#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ -+ -+#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -+#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ -+ -+/* TC2.CTRLC bit masks and bit positions */ -+#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -+#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ -+ -+#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -+#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ -+ -+#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -+#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ -+ -+#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -+#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ -+ -+#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -+#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ -+ -+#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -+#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ -+ -+#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -+#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ -+ -+#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -+#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ -+ -+/* TC2.CTRLE bit masks and bit positions */ -+#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC2.INTCTRLA bit masks and bit positions */ -+#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -+#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -+#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -+#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -+#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -+#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ -+ -+#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -+#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -+#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -+#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -+#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -+#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ -+ -+/* TC2.INTCTRLB bit masks and bit positions */ -+#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -+#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -+#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -+#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -+#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -+#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -+#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -+#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -+#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -+#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -+#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -+#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -+#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -+#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -+#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -+#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -+#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -+#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -+#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -+#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -+#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ -+ -+/* TC2.CTRLF bit masks and bit positions */ -+#define TC2_CMD_gm 0x0C /* Command group mask. */ -+#define TC2_CMD_gp 2 /* Command group position. */ -+#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC2_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -+#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -+#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -+#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -+#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -+#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ -+ -+/* TC2.INTFLAGS bit masks and bit positions */ -+#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -+#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ -+ -+#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -+#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ -+ -+#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -+#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ -+ -+#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -+#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ -+ -+#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ -+ -+#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ -+ -+/* AWEX - Timer/Counter Advanced Waveform Extension */ -+/* AWEX.CTRL bit masks and bit positions */ -+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ -+ -+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ -+ -+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ -+ -+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ -+ -+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ -+ -+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ -+ -+/* AWEX.FDCTRL bit masks and bit positions */ -+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ -+ -+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ -+ -+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ -+ -+/* AWEX.STATUS bit masks and bit positions */ -+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ -+ -+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ -+ -+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ -+ -+/* AWEX.STATUSSET bit masks and bit positions */ -+/* AWEX_FDF Predefined. */ -+/* AWEX_FDF Predefined. */ -+ -+/* AWEX_DTHSBUFV Predefined. */ -+/* AWEX_DTHSBUFV Predefined. */ -+ -+/* AWEX_DTLSBUFV Predefined. */ -+/* AWEX_DTLSBUFV Predefined. */ -+ -+/* HIRES - Timer/Counter High-Resolution Extension */ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -+#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* LOCKBIT - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT0_vect_num 2 -+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -+#define PORTC_INT1_vect_num 3 -+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT0_vect_num 4 -+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -+#define PORTR_INT1_vect_num 5 -+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ -+ -+/* DMA interrupt vectors */ -+#define DMA_CH0_vect_num 6 -+#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -+#define DMA_CH1_vect_num 7 -+#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -+#define DMA_CH2_vect_num 8 -+#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -+#define DMA_CH3_vect_num 9 -+#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ -+ -+/* RTC interrupt vectors */ -+#define RTC_OVF_vect_num 10 -+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -+#define RTC_COMP_vect_num 11 -+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 12 -+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 13 -+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_OVF_vect_num 14 -+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LUNF_vect_num 14 -+#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_ERR_vect_num 15 -+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_HUNF_vect_num 15 -+#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCA_vect_num 16 -+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPA_vect_num 16 -+#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCB_vect_num 17 -+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPB_vect_num 17 -+#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCC_vect_num 18 -+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPC_vect_num 18 -+#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCD_vect_num 19 -+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPD_vect_num 19 -+#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ -+ -+/* TCC1 interrupt vectors */ -+#define TCC1_OVF_vect_num 20 -+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -+#define TCC1_ERR_vect_num 21 -+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -+#define TCC1_CCA_vect_num 22 -+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -+#define TCC1_CCB_vect_num 23 -+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 24 -+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 25 -+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 26 -+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 27 -+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ -+ -+/* USARTC1 interrupt vectors */ -+#define USARTC1_RXC_vect_num 28 -+#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -+#define USARTC1_DRE_vect_num 29 -+#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -+#define USARTC1_TXC_vect_num 30 -+#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ -+ -+/* AES interrupt vectors */ -+#define AES_INT_vect_num 31 -+#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 32 -+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -+#define NVM_SPM_vect_num 33 -+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ -+ -+/* PORTB interrupt vectors */ -+#define PORTB_INT0_vect_num 34 -+#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -+#define PORTB_INT1_vect_num 35 -+#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ -+ -+/* PORTE interrupt vectors */ -+#define PORTE_INT0_vect_num 43 -+#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -+#define PORTE_INT1_vect_num 44 -+#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ -+ -+/* TWIE interrupt vectors */ -+#define TWIE_TWIS_vect_num 45 -+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -+#define TWIE_TWIM_vect_num 46 -+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_OVF_vect_num 47 -+#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -+#define TCE0_ERR_vect_num 48 -+#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -+#define TCE0_CCA_vect_num 49 -+#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -+#define TCE0_CCB_vect_num 50 -+#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -+#define TCE0_CCC_vect_num 51 -+#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -+#define TCE0_CCD_vect_num 52 -+#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ -+ -+/* USARTE0 interrupt vectors */ -+#define USARTE0_RXC_vect_num 58 -+#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -+#define USARTE0_DRE_vect_num 59 -+#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -+#define USARTE0_TXC_vect_num 60 -+#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT0_vect_num 64 -+#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -+#define PORTD_INT1_vect_num 65 -+#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ -+ -+/* PORTA interrupt vectors */ -+#define PORTA_INT0_vect_num 66 -+#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -+#define PORTA_INT1_vect_num 67 -+#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ -+ -+/* ACA interrupt vectors */ -+#define ACA_AC0_vect_num 68 -+#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -+#define ACA_AC1_vect_num 69 -+#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -+#define ACA_ACW_vect_num 70 -+#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ -+ -+/* ADCA interrupt vectors */ -+#define ADCA_CH0_vect_num 71 -+#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -+#define ADCA_CH1_vect_num 72 -+#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -+#define ADCA_CH2_vect_num 73 -+#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -+#define ADCA_CH3_vect_num 74 -+#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_OVF_vect_num 77 -+#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LUNF_vect_num 77 -+#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_ERR_vect_num 78 -+#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_HUNF_vect_num 78 -+#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCA_vect_num 79 -+#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPA_vect_num 79 -+#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCB_vect_num 80 -+#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPB_vect_num 80 -+#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCC_vect_num 81 -+#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPC_vect_num 81 -+#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCD_vect_num 82 -+#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPD_vect_num 82 -+#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ -+ -+/* TCD1 interrupt vectors */ -+#define TCD1_OVF_vect_num 83 -+#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -+#define TCD1_ERR_vect_num 84 -+#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -+#define TCD1_CCA_vect_num 85 -+#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -+#define TCD1_CCB_vect_num 86 -+#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ -+ -+/* SPID interrupt vectors */ -+#define SPID_INT_vect_num 87 -+#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ -+ -+/* USARTD0 interrupt vectors */ -+#define USARTD0_RXC_vect_num 88 -+#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -+#define USARTD0_DRE_vect_num 89 -+#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -+#define USARTD0_TXC_vect_num 90 -+#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ -+ -+/* USARTD1 interrupt vectors */ -+#define USARTD1_RXC_vect_num 91 -+#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -+#define USARTD1_DRE_vect_num 92 -+#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -+#define USARTD1_TXC_vect_num 93 -+#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ -+ -+/* USB interrupt vectors */ -+#define USB_BUSEVENT_vect_num 125 -+#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -+#define USB_TRNCOMPL_vect_num 126 -+#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (127 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (36864) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (32768) -+#define APP_SECTION_PAGE_SIZE (256) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0x7000) -+#define APPTABLE_SECTION_SIZE (4096) -+#define APPTABLE_SECTION_PAGE_SIZE (256) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x8000) -+#define BOOT_SECTION_SIZE (4096) -+#define BOOT_SECTION_PAGE_SIZE (256) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (12288) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (1024) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (4096) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (1024) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (6) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (256) -+#define USER_SIGNATURES_PAGE_SIZE (256) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (52) -+#define PROD_SIGNATURES_PAGE_SIZE (256) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 256 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 6 -+ -+/* Fuse Byte 0 Reserved */ -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x95 -+#define SIGNATURE_2 0x41 -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA32A4U_H_INCLUDED */ -+ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox32a4u.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA32A4U_H_INCLUDED ++#define _AVR_ATXMEGA32A4U_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t USBCTRL; /* USB Control Register */ ++} CLK_t; ++ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t PRPB; /* Power Reduction Port B */ ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++/* USB Prescaler Division Factor */ ++typedef enum CLK_USBPSDIV_enum ++{ ++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ ++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ ++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ ++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ ++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ ++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ ++} CLK_USBPSDIV_t; ++ ++/* USB Clock Source */ ++typedef enum CLK_USBSRC_enum ++{ ++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ ++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ ++} CLK_USBSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 2 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC2MCREF_enum ++{ ++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC2MCREF_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++ register8_t EBIOUT; /* EBI Output register */ ++ register8_t EVOUTSEL; /* Event Output Select */ ++} PORTCFG_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP02MAP_enum ++{ ++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP02MAP_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP13MAP_enum ++{ ++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP13MAP_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Clock and Event Output Port */ ++typedef enum PORTCFG_CLKEVPIN_enum ++{ ++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ ++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ ++} PORTCFG_CLKEVPIN_t; ++ ++/* EBI Address Output Port */ ++typedef enum PORTCFG_EBIADROUT_enum ++{ ++ PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ ++ PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ ++ PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ ++ PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ ++} PORTCFG_EBIADROUT_t; ++ ++/* EBI Chip Select Output Port */ ++typedef enum PORTCFG_EBICSOUT_enum ++{ ++ PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ ++} PORTCFG_EBICSOUT_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ ++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ ++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ ++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ ++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AES - AES Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* AES Module */ ++typedef struct AES_struct ++{ ++ register8_t CTRL; /* AES Control Register */ ++ register8_t STATUS; /* AES Status Register */ ++ register8_t STATE; /* AES State Register */ ++ register8_t KEY; /* AES Key Register */ ++ register8_t INTCTRL; /* AES Interrupt Control Register */ ++} AES_t; ++ ++/* Interrupt level */ ++typedef enum AES_INTLVL_enum ++{ ++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} AES_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ ++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ ++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ ++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Channel */ ++typedef struct DMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Address Control */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ ++ register8_t REPCNT; /* Channel Repeat Count */ ++ register8_t reserved_0x07; ++ register8_t SRCADDR0; /* Channel Source Address 0 */ ++ register8_t SRCADDR1; /* Channel Source Address 1 */ ++ register8_t SRCADDR2; /* Channel Source Address 2 */ ++ register8_t reserved_0x0B; ++ register8_t DESTADDR0; /* Channel Destination Address 0 */ ++ register8_t DESTADDR1; /* Channel Destination Address 1 */ ++ register8_t DESTADDR2; /* Channel Destination Address 2 */ ++ register8_t reserved_0x0F; ++} DMA_CH_t; ++ ++ ++/* DMA Controller */ ++typedef struct DMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ DMA_CH_t CH0; /* DMA Channel 0 */ ++ DMA_CH_t CH1; /* DMA Channel 1 */ ++ DMA_CH_t CH2; /* DMA Channel 2 */ ++ DMA_CH_t CH3; /* DMA Channel 3 */ ++} DMA_t; ++ ++/* Burst mode */ ++typedef enum DMA_CH_BURSTLEN_enum ++{ ++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ ++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ ++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ ++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ ++} DMA_CH_BURSTLEN_t; ++ ++/* Source address reload mode */ ++typedef enum DMA_CH_SRCRELOAD_enum ++{ ++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ ++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ ++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ ++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ ++} DMA_CH_SRCRELOAD_t; ++ ++/* Source addressing mode */ ++typedef enum DMA_CH_SRCDIR_enum ++{ ++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ ++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ ++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ ++} DMA_CH_SRCDIR_t; ++ ++/* Destination adress reload mode */ ++typedef enum DMA_CH_DESTRELOAD_enum ++{ ++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ ++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ ++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ ++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ ++} DMA_CH_DESTRELOAD_t; ++ ++/* Destination adressing mode */ ++typedef enum DMA_CH_DESTDIR_enum ++{ ++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ ++} DMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum DMA_CH_TRIGSRC_enum ++{ ++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ ++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ ++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ ++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ ++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ ++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ ++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ ++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ ++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ ++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ ++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ ++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ ++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ ++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ ++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ ++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ ++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ ++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ ++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ ++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ ++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ ++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ ++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ ++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ ++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ ++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ ++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ ++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ ++} DMA_CH_TRIGSRC_t; ++ ++/* Double buffering mode */ ++typedef enum DMA_DBUFMODE_enum ++{ ++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ ++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ ++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ ++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ ++} DMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum DMA_PRIMODE_enum ++{ ++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ ++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ ++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ ++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ ++} DMA_PRIMODE_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_ERRINTLVL_enum ++{ ++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ ++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ ++} DMA_CH_ERRINTLVL_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_TRNINTLVL_enum ++{ ++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ ++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ ++} DMA_CH_TRNINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ ++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ ++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ ++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t CH4CTRL; /* Channel 4 Control Register */ ++ register8_t CH5CTRL; /* Channel 5 Control Register */ ++ register8_t CH6CTRL; /* Channel 6 Control Register */ ++ register8_t CH7CTRL; /* Channel 7 Control Register */ ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ ++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ ++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ ++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ ++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ ++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ ++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ ++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ ++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ ++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ ++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ ++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ ++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ ++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ ++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ ++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ ++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ ++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t reserved_0x07; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ _WORDREGISTER(CH1RES); /* Channel 1 Result */ ++ _WORDREGISTER(CH2RES); /* Channel 2 Result */ ++ _WORDREGISTER(CH3RES); /* Channel 3 Result */ ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++ ADC_CH_t CH1; /* ADC Channel 1 */ ++ ADC_CH_t CH2; /* ADC Channel 2 */ ++ ADC_CH_t CH3; /* ADC Channel 3 */ ++} ADC_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ ++ ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ ++ ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ ++ ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Current Limitation Mode */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ ++} ADC_CURRLIMIT_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Channel sweep selection */ ++typedef enum ADC_SWEEP_enum ++{ ++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ ++} ADC_SWEEP_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* DMA request selection */ ++typedef enum ADC_DMASEL_enum ++{ ++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ ++} ADC_DMASEL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DAC - Digital/Analog Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Digital-to-Analog Converter */ ++typedef struct DAC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t EVCTRL; /* Event Input Control */ ++ register8_t reserved_0x04; ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0GAINCAL; /* Gain Calibration */ ++ register8_t CH0OFFSETCAL; /* Offset Calibration */ ++ register8_t CH1GAINCAL; /* Gain Calibration */ ++ register8_t CH1OFFSETCAL; /* Offset Calibration */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ ++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ ++} DAC_t; ++ ++/* Output channel selection */ ++typedef enum DAC_CHSEL_enum ++{ ++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ ++ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ ++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ ++} DAC_CHSEL_t; ++ ++/* Reference voltage selection */ ++typedef enum DAC_REFSEL_enum ++{ ++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ ++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ ++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ ++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ ++} DAC_REFSEL_t; ++ ++/* Event channel selection */ ++typedef enum DAC_EVSEL_enum ++{ ++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ ++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ ++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ ++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ ++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ ++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ ++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ ++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ ++} DAC_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* SDA Hold Time */ ++typedef enum TWI_SDAHOLD_enum ++{ ++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ ++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ ++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ ++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ ++} TWI_SDAHOLD_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USB - USB ++-------------------------------------------------------------------------- ++*/ ++ ++/* USB Endpoint */ ++typedef struct USB_EP_struct ++{ ++ register8_t STATUS; /* Endpoint Status */ ++ register8_t CTRL; /* Endpoint Control */ ++ _WORDREGISTER(CNT); /* USB Endpoint Counter */ ++ _WORDREGISTER(DATAPTR); /* Data Pointer */ ++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ ++} USB_EP_t; ++ ++ ++/* Universal Serial Bus */ ++typedef struct USB_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t FIFOWP; /* FIFO Write Pointer Register */ ++ register8_t FIFORP; /* FIFO Read Pointer Register */ ++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ ++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ ++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ ++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t reserved_0x20; ++ register8_t reserved_0x21; ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t CAL0; /* Calibration Byte 0 */ ++ register8_t CAL1; /* Calibration Byte 1 */ ++} USB_t; ++ ++ ++/* USB Endpoint Table */ ++typedef struct USB_EP_TABLE_struct ++{ ++ USB_EP_t EP0OUT; /* Endpoint 0 */ ++ USB_EP_t EP0IN; /* Endpoint 0 */ ++ USB_EP_t EP1OUT; /* Endpoint 1 */ ++ USB_EP_t EP1IN; /* Endpoint 1 */ ++ USB_EP_t EP2OUT; /* Endpoint 2 */ ++ USB_EP_t EP2IN; /* Endpoint 2 */ ++ USB_EP_t EP3OUT; /* Endpoint 3 */ ++ USB_EP_t EP3IN; /* Endpoint 3 */ ++ USB_EP_t EP4OUT; /* Endpoint 4 */ ++ USB_EP_t EP4IN; /* Endpoint 4 */ ++ USB_EP_t EP5OUT; /* Endpoint 5 */ ++ USB_EP_t EP5IN; /* Endpoint 5 */ ++ USB_EP_t EP6OUT; /* Endpoint 6 */ ++ USB_EP_t EP6IN; /* Endpoint 6 */ ++ USB_EP_t EP7OUT; /* Endpoint 7 */ ++ USB_EP_t EP7IN; /* Endpoint 7 */ ++ USB_EP_t EP8OUT; /* Endpoint 8 */ ++ USB_EP_t EP8IN; /* Endpoint 8 */ ++ USB_EP_t EP9OUT; /* Endpoint 9 */ ++ USB_EP_t EP9IN; /* Endpoint 9 */ ++ USB_EP_t EP10OUT; /* Endpoint 10 */ ++ USB_EP_t EP10IN; /* Endpoint 10 */ ++ USB_EP_t EP11OUT; /* Endpoint 11 */ ++ USB_EP_t EP11IN; /* Endpoint 11 */ ++ USB_EP_t EP12OUT; /* Endpoint 12 */ ++ USB_EP_t EP12IN; /* Endpoint 12 */ ++ USB_EP_t EP13OUT; /* Endpoint 13 */ ++ USB_EP_t EP13IN; /* Endpoint 13 */ ++ USB_EP_t EP14OUT; /* Endpoint 14 */ ++ USB_EP_t EP14IN; /* Endpoint 14 */ ++ USB_EP_t EP15OUT; /* Endpoint 15 */ ++ USB_EP_t EP15IN; /* Endpoint 15 */ ++ register8_t reserved_0x100; ++ register8_t reserved_0x101; ++ register8_t reserved_0x102; ++ register8_t reserved_0x103; ++ register8_t reserved_0x104; ++ register8_t reserved_0x105; ++ register8_t reserved_0x106; ++ register8_t reserved_0x107; ++ register8_t reserved_0x108; ++ register8_t reserved_0x109; ++ register8_t reserved_0x10A; ++ register8_t reserved_0x10B; ++ register8_t reserved_0x10C; ++ register8_t reserved_0x10D; ++ register8_t reserved_0x10E; ++ register8_t reserved_0x10F; ++ register8_t FRAMENUML; /* Frame Number Low Byte */ ++ register8_t FRAMENUMH; /* Frame Number High Byte */ ++} USB_EP_TABLE_t; ++ ++/* Interrupt level */ ++typedef enum USB_INTLVL_enum ++{ ++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} USB_INTLVL_t; ++ ++/* USB Endpoint Type */ ++typedef enum USB_EP_TYPE_enum ++{ ++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ ++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ ++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ ++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ ++} USB_EP_TYPE_t; ++ ++/* USB Endpoint Buffersize */ ++typedef enum USB_EP_BUFSIZE_enum ++{ ++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ ++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ ++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ ++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ ++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ ++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ ++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ ++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ ++} USB_EP_BUFSIZE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - I/O Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* I/O Port Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Byte Mode */ ++typedef enum TC_BYTEM_enum ++{ ++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ ++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ ++} TC_BYTEM_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC2 - 16-bit Timer/Counter type 2 ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter type 2 */ ++typedef struct TC2_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t reserved_0x03; ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t reserved_0x08; ++ register8_t CTRLF; /* Control Register F */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t LCNT; /* Low Byte Count */ ++ register8_t HCNT; /* High Byte Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t LPER; /* Low Byte Period */ ++ register8_t HPER; /* High Byte Period */ ++ register8_t LCMPA; /* Low Byte Compare A */ ++ register8_t HCMPA; /* High Byte Compare A */ ++ register8_t LCMPB; /* Low Byte Compare B */ ++ register8_t HCMPB; /* High Byte Compare B */ ++ register8_t LCMPC; /* Low Byte Compare C */ ++ register8_t HCMPC; /* High Byte Compare C */ ++ register8_t LCMPD; /* Low Byte Compare D */ ++ register8_t HCMPD; /* High Byte Compare D */ ++} TC2_t; ++ ++/* Clock Selection */ ++typedef enum TC2_CLKSEL_enum ++{ ++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC2_CLKSEL_t; ++ ++/* Byte Mode */ ++typedef enum TC2_BYTEM_enum ++{ ++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ ++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ ++} TC2_BYTEM_t; ++ ++/* High Byte Underflow Interrupt Level */ ++typedef enum TC2_HUNFINTLVL_enum ++{ ++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_HUNFINTLVL_t; ++ ++/* Low Byte Underflow Interrupt Level */ ++typedef enum TC2_LUNFINTLVL_enum ++{ ++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LUNFINTLVL_t; ++ ++/* Low Byte Compare D Interrupt Level */ ++typedef enum TC2_LCMPDINTLVL_enum ++{ ++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC2_LCMPDINTLVL_t; ++ ++/* Low Byte Compare C Interrupt Level */ ++typedef enum TC2_LCMPCINTLVL_enum ++{ ++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC2_LCMPCINTLVL_t; ++ ++/* Low Byte Compare B Interrupt Level */ ++typedef enum TC2_LCMPBINTLVL_enum ++{ ++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_LCMPBINTLVL_t; ++ ++/* Low Byte Compare A Interrupt Level */ ++typedef enum TC2_LCMPAINTLVL_enum ++{ ++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LCMPAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMD_enum ++{ ++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC2_CMD_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMDEN_enum ++{ ++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ ++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ ++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ ++} TC2_CMDEN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AWEX - Timer/Counter Advanced Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - Timer/Counter High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t reserved_0x00; ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* Timer Oscillator pin location */ ++typedef enum TOSCSEL_enum ++{ ++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ ++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ ++} TOSCSEL_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* BOD operation */ ++typedef enum BODACT_enum ++{ ++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BODACT_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WDP_enum ++{ ++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ ++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ ++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ ++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ ++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ ++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ ++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ ++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ ++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ ++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ ++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ ++} WDP_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LOCKBIT - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ ++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t USBCAL0; /* USB Calibration Byte 0 */ ++ register8_t USBCAL1; /* USB Calibration Byte 1 */ ++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ ++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ ++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ ++ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ ++ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ ++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ ++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ ++ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ ++ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++ register8_t reserved_0x40; ++ register8_t reserved_0x41; ++ register8_t reserved_0x42; ++ register8_t reserved_0x43; ++ register8_t reserved_0x44; ++ register8_t reserved_0x45; ++ register8_t reserved_0x46; ++ register8_t reserved_0x47; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define AES (*(AES_t *) 0x00C0) /* AES Module */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ ++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ ++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ ++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ ++#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ ++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ ++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++#define GPIO_GPIOR4 _SFR_MEM8(0x0004) ++#define GPIO_GPIOR5 _SFR_MEM8(0x0005) ++#define GPIO_GPIOR6 _SFR_MEM8(0x0006) ++#define GPIO_GPIOR7 _SFR_MEM8(0x0007) ++#define GPIO_GPIOR8 _SFR_MEM8(0x0008) ++#define GPIO_GPIOR9 _SFR_MEM8(0x0009) ++#define GPIO_GPIORA _SFR_MEM8(0x000A) ++#define GPIO_GPIORB _SFR_MEM8(0x000B) ++#define GPIO_GPIORC _SFR_MEM8(0x000C) ++#define GPIO_GPIORD _SFR_MEM8(0x000D) ++#define GPIO_GPIORE _SFR_MEM8(0x000E) ++#define GPIO_GPIORF _SFR_MEM8(0x000F) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++#define GPIO_GPIO4 _SFR_MEM8(0x0004) ++#define GPIO_GPIO5 _SFR_MEM8(0x0005) ++#define GPIO_GPIO6 _SFR_MEM8(0x0006) ++#define GPIO_GPIO7 _SFR_MEM8(0x0007) ++#define GPIO_GPIO8 _SFR_MEM8(0x0008) ++#define GPIO_GPIO9 _SFR_MEM8(0x0009) ++#define GPIO_GPIOA _SFR_MEM8(0x000A) ++#define GPIO_GPIOB _SFR_MEM8(0x000B) ++#define GPIO_GPIOC _SFR_MEM8(0x000C) ++#define GPIO_GPIOD _SFR_MEM8(0x000D) ++#define GPIO_GPIOE _SFR_MEM8(0x000E) ++#define GPIO_GPIOF _SFR_MEM8(0x000F) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) ++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) ++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) ++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) ++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) ++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) ++#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) ++#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) ++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) ++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) ++#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) ++#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++#define CLK_USBCTRL _SFR_MEM8(0x0044) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLL - DFLL */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPB _SFR_MEM8(0x0072) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) ++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) ++ ++/* AES - AES Module */ ++#define AES_CTRL _SFR_MEM8(0x00C0) ++#define AES_STATUS _SFR_MEM8(0x00C1) ++#define AES_STATE _SFR_MEM8(0x00C2) ++#define AES_KEY _SFR_MEM8(0x00C3) ++#define AES_INTCTRL _SFR_MEM8(0x00C4) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* DMA - DMA Controller */ ++#define DMA_CTRL _SFR_MEM8(0x0100) ++#define DMA_INTFLAGS _SFR_MEM8(0x0103) ++#define DMA_STATUS _SFR_MEM8(0x0104) ++#define DMA_TEMP _SFR_MEM16(0x0106) ++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) ++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) ++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) ++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) ++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) ++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) ++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) ++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) ++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) ++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) ++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) ++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) ++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) ++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) ++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) ++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) ++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) ++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) ++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) ++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) ++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) ++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) ++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) ++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) ++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) ++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) ++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) ++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) ++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) ++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) ++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) ++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) ++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) ++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) ++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) ++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) ++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) ++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) ++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) ++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) ++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) ++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH4MUX _SFR_MEM8(0x0184) ++#define EVSYS_CH5MUX _SFR_MEM8(0x0185) ++#define EVSYS_CH6MUX _SFR_MEM8(0x0186) ++#define EVSYS_CH7MUX _SFR_MEM8(0x0187) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) ++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) ++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) ++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CH1RES _SFR_MEM16(0x0212) ++#define ADCA_CH2RES _SFR_MEM16(0x0214) ++#define ADCA_CH3RES _SFR_MEM16(0x0216) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) ++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) ++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) ++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) ++#define ADCA_CH1_RES _SFR_MEM16(0x022C) ++#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) ++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) ++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) ++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) ++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) ++#define ADCA_CH2_RES _SFR_MEM16(0x0234) ++#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) ++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) ++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) ++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) ++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) ++#define ADCA_CH3_RES _SFR_MEM16(0x023C) ++#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) ++ ++/* DAC - Digital-to-Analog Converter */ ++#define DACB_CTRLA _SFR_MEM8(0x0320) ++#define DACB_CTRLB _SFR_MEM8(0x0321) ++#define DACB_CTRLC _SFR_MEM8(0x0322) ++#define DACB_EVCTRL _SFR_MEM8(0x0323) ++#define DACB_STATUS _SFR_MEM8(0x0325) ++#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) ++#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) ++#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) ++#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) ++#define DACB_CH0DATA _SFR_MEM16(0x0338) ++#define DACB_CH1DATA _SFR_MEM16(0x033A) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* USB - Universal Serial Bus */ ++#define USB_CTRLA _SFR_MEM8(0x04C0) ++#define USB_CTRLB _SFR_MEM8(0x04C1) ++#define USB_STATUS _SFR_MEM8(0x04C2) ++#define USB_ADDR _SFR_MEM8(0x04C3) ++#define USB_FIFOWP _SFR_MEM8(0x04C4) ++#define USB_FIFORP _SFR_MEM8(0x04C5) ++#define USB_EPPTR _SFR_MEM16(0x04C6) ++#define USB_INTCTRLA _SFR_MEM8(0x04C8) ++#define USB_INTCTRLB _SFR_MEM8(0x04C9) ++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) ++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) ++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) ++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) ++#define USB_CAL0 _SFR_MEM8(0x04FA) ++#define USB_CAL1 _SFR_MEM8(0x04FB) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_REMAP _SFR_MEM8(0x060E) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_REMAP _SFR_MEM8(0x062E) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_REMAP _SFR_MEM8(0x068E) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCC2_CTRLA _SFR_MEM8(0x0800) ++#define TCC2_CTRLB _SFR_MEM8(0x0801) ++#define TCC2_CTRLC _SFR_MEM8(0x0802) ++#define TCC2_CTRLE _SFR_MEM8(0x0804) ++#define TCC2_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC2_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC2_CTRLF _SFR_MEM8(0x0809) ++#define TCC2_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC2_LCNT _SFR_MEM8(0x0820) ++#define TCC2_HCNT _SFR_MEM8(0x0821) ++#define TCC2_LPER _SFR_MEM8(0x0826) ++#define TCC2_HPER _SFR_MEM8(0x0827) ++#define TCC2_LCMPA _SFR_MEM8(0x0828) ++#define TCC2_HCMPA _SFR_MEM8(0x0829) ++#define TCC2_LCMPB _SFR_MEM8(0x082A) ++#define TCC2_HCMPB _SFR_MEM8(0x082B) ++#define TCC2_LCMPC _SFR_MEM8(0x082C) ++#define TCC2_HCMPC _SFR_MEM8(0x082D) ++#define TCC2_LCMPD _SFR_MEM8(0x082E) ++#define TCC2_HCMPD _SFR_MEM8(0x082F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_STATUSSET _SFR_MEM8(0x0885) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1_DATA _SFR_MEM8(0x08B0) ++#define USARTC1_STATUS _SFR_MEM8(0x08B1) ++#define USARTC1_CTRLA _SFR_MEM8(0x08B3) ++#define USARTC1_CTRLB _SFR_MEM8(0x08B4) ++#define USARTC1_CTRLC _SFR_MEM8(0x08B5) ++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) ++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCD2_CTRLA _SFR_MEM8(0x0900) ++#define TCD2_CTRLB _SFR_MEM8(0x0901) ++#define TCD2_CTRLC _SFR_MEM8(0x0902) ++#define TCD2_CTRLE _SFR_MEM8(0x0904) ++#define TCD2_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD2_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD2_CTRLF _SFR_MEM8(0x0909) ++#define TCD2_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD2_LCNT _SFR_MEM8(0x0920) ++#define TCD2_HCNT _SFR_MEM8(0x0921) ++#define TCD2_LPER _SFR_MEM8(0x0926) ++#define TCD2_HPER _SFR_MEM8(0x0927) ++#define TCD2_LCMPA _SFR_MEM8(0x0928) ++#define TCD2_HCMPA _SFR_MEM8(0x0929) ++#define TCD2_LCMPB _SFR_MEM8(0x092A) ++#define TCD2_HCMPB _SFR_MEM8(0x092B) ++#define TCD2_LCMPC _SFR_MEM8(0x092C) ++#define TCD2_HCMPC _SFR_MEM8(0x092D) ++#define TCD2_LCMPD _SFR_MEM8(0x092E) ++#define TCD2_HCMPD _SFR_MEM8(0x092F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCD1_CTRLA _SFR_MEM8(0x0940) ++#define TCD1_CTRLB _SFR_MEM8(0x0941) ++#define TCD1_CTRLC _SFR_MEM8(0x0942) ++#define TCD1_CTRLD _SFR_MEM8(0x0943) ++#define TCD1_CTRLE _SFR_MEM8(0x0944) ++#define TCD1_INTCTRLA _SFR_MEM8(0x0946) ++#define TCD1_INTCTRLB _SFR_MEM8(0x0947) ++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) ++#define TCD1_CTRLFSET _SFR_MEM8(0x0949) ++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) ++#define TCD1_CTRLGSET _SFR_MEM8(0x094B) ++#define TCD1_INTFLAGS _SFR_MEM8(0x094C) ++#define TCD1_TEMP _SFR_MEM8(0x094F) ++#define TCD1_CNT _SFR_MEM16(0x0960) ++#define TCD1_PER _SFR_MEM16(0x0966) ++#define TCD1_CCA _SFR_MEM16(0x0968) ++#define TCD1_CCB _SFR_MEM16(0x096A) ++#define TCD1_PERBUF _SFR_MEM16(0x0976) ++#define TCD1_CCABUF _SFR_MEM16(0x0978) ++#define TCD1_CCBBUF _SFR_MEM16(0x097A) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESD_CTRLA _SFR_MEM8(0x0990) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD1_DATA _SFR_MEM8(0x09B0) ++#define USARTD1_STATUS _SFR_MEM8(0x09B1) ++#define USARTD1_CTRLA _SFR_MEM8(0x09B3) ++#define USARTD1_CTRLB _SFR_MEM8(0x09B4) ++#define USARTD1_CTRLC _SFR_MEM8(0x09B5) ++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) ++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESE_CTRLA _SFR_MEM8(0x0A90) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* CLK.USBCTRL bit masks and bit positions */ ++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ ++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ ++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ ++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ ++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ ++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ ++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ ++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ ++ ++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ ++#define CLK_USBSRC_gp 1 /* Clock Source group position. */ ++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ ++ ++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_USB_bm 0x40 /* USB bit mask. */ ++#define PR_USB_bp 6 /* USB bit position. */ ++ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ ++#define PR_EBI_bp 3 /* External Bus Interface bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ ++#define PR_DAC_bp 2 /* Port A DAC bit position. */ ++ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPB bit masks and bit positions */ ++/* PR_DAC Predefined. */ ++/* PR_DAC Predefined. */ ++ ++/* PR_ADC Predefined. */ ++/* PR_ADC Predefined. */ ++ ++/* PR_AC Predefined. */ ++/* PR_AC Predefined. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ ++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ ++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ ++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ ++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ ++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ ++ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ ++#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ ++ ++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ ++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ ++ ++#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ ++#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ ++ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ ++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ ++ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ ++ ++/* PORTCFG.EBIOUT bit masks and bit positions */ ++#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ ++#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ ++#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ ++#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ ++#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ ++#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ ++ ++#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ ++#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ ++#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ ++#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ ++#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ ++#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ ++ ++/* PORTCFG.EVOUTSEL bit masks and bit positions */ ++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ ++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ ++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ ++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ ++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ ++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ ++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ ++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ ++ ++/* AES - AES Module */ ++/* AES.CTRL bit masks and bit positions */ ++#define AES_START_bm 0x80 /* Start/Run bit mask. */ ++#define AES_START_bp 7 /* Start/Run bit position. */ ++ ++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ ++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ ++ ++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ ++#define AES_RESET_bp 5 /* AES Software Reset bit position. */ ++ ++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ ++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ ++ ++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ ++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ ++ ++/* AES.STATUS bit masks and bit positions */ ++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ ++#define AES_ERROR_bp 7 /* AES Error bit position. */ ++ ++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ ++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ ++ ++/* AES.INTCTRL bit masks and bit positions */ ++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define AES_INTLVL_gp 0 /* Interrupt level group position. */ ++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* DMA - DMA Controller */ ++/* DMA_CH.CTRLA bit masks and bit positions */ ++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ ++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ ++ ++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ ++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ ++ ++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ ++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ ++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ ++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ ++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ ++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ ++ ++/* DMA_CH.CTRLB bit masks and bit positions */ ++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ ++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ ++ ++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ ++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ ++ ++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ ++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ ++ ++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ ++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ ++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ ++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ ++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ ++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ ++ ++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ ++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ ++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ ++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ ++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ ++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ ++ ++/* DMA_CH.ADDRCTRL bit masks and bit positions */ ++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ ++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ ++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ ++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ ++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ ++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ ++ ++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ ++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ ++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ ++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ ++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ ++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ ++ ++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ ++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ ++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ ++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ ++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ ++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ ++ ++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ ++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ ++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ ++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ ++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ ++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ ++ ++/* DMA_CH.TRIGSRC bit masks and bit positions */ ++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++/* DMA.CTRL bit masks and bit positions */ ++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define DMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define DMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ ++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ ++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ ++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ ++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ ++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ ++ ++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ ++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ ++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ ++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ ++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ ++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ ++ ++/* DMA.INTFLAGS bit masks and bit positions */ ++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++/* DMA.STATUS bit masks and bit positions */ ++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ ++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ ++ ++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ ++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ ++ ++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ ++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ ++ ++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ ++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ ++ ++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ ++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ ++ ++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ ++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ ++ ++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ ++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ ++ ++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ ++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH4MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH5MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH6MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH7MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM Predefined. */ ++/* EVSYS_QDIRM Predefined. */ ++ ++/* EVSYS_QDIEN Predefined. */ ++/* EVSYS_QDIEN Predefined. */ ++ ++/* EVSYS_QDEN Predefined. */ ++/* EVSYS_QDEN Predefined. */ ++ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH4CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM Predefined. */ ++/* EVSYS_QDIRM Predefined. */ ++ ++/* EVSYS_QDIEN Predefined. */ ++/* EVSYS_QDIEN Predefined. */ ++ ++/* EVSYS_QDEN Predefined. */ ++/* EVSYS_QDEN Predefined. */ ++ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH5CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH6CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH7CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ ++#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ ++#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ ++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ ++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ ++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ ++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ ++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ ++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ ++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ ++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ ++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ ++ ++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ ++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ ++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ ++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ ++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ ++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ ++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ ++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ ++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ ++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ ++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ ++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ ++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ ++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ ++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ ++ ++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ ++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ ++ ++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ ++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ ++ ++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ ++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ ++ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ ++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ ++#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ ++ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ ++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ ++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ ++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ ++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ ++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ ++ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ ++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ ++ ++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ ++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ ++ ++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ ++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ ++ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* DAC - Digital/Analog Converter */ ++/* DAC.CTRLA bit masks and bit positions */ ++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ ++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ ++ ++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ ++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ ++ ++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ ++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ ++ ++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ ++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ ++ ++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define DAC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* DAC.CTRLB bit masks and bit positions */ ++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ ++#define DAC_CHSEL_gp 5 /* Channel Select group position. */ ++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ ++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ ++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ ++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ ++ ++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ ++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ ++ ++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ ++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ ++ ++/* DAC.CTRLC bit masks and bit positions */ ++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ ++#define DAC_REFSEL_gp 3 /* Reference Select group position. */ ++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ ++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ ++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ ++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ ++ ++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ ++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ ++ ++/* DAC.EVCTRL bit masks and bit positions */ ++#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ ++#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ ++ ++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ ++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ ++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ ++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ ++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ ++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ ++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ ++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ ++ ++/* DAC.STATUS bit masks and bit positions */ ++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ ++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ ++ ++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ ++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ ++ ++/* DAC.CH0GAINCAL bit masks and bit positions */ ++#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH0OFFSETCAL bit masks and bit positions */ ++#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* DAC.CH1GAINCAL bit masks and bit positions */ ++#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH1OFFSETCAL bit masks and bit positions */ ++#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ ++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HSMODE Predefined. */ ++/* AC_HSMODE Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* RTC - Real-Time Counter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* USB - USB */ ++/* USB_EP.STATUS bit masks and bit positions */ ++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ ++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ ++ ++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ ++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ ++ ++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ ++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ ++ ++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ ++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ ++ ++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ ++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ ++ ++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ ++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ ++ ++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ ++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ ++ ++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ ++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ ++ ++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ ++ ++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ ++ ++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ ++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ ++ ++/* USB_EP.CTRL bit masks and bit positions */ ++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ ++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ ++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ ++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ ++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ ++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ ++ ++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ ++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ ++ ++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ ++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ ++ ++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ ++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ ++ ++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ ++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ ++ ++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ ++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ ++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ ++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ ++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ ++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ ++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ ++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ ++ ++/* USB_EP.CNT bit masks and bit positions */ ++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ ++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ ++ ++/* USB.CTRLA bit masks and bit positions */ ++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ ++#define USB_ENABLE_bp 7 /* USB Enable bit position. */ ++ ++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ ++#define USB_SPEED_bp 6 /* Speed Select bit position. */ ++ ++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ ++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ ++ ++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ ++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ ++ ++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ ++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ ++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ ++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ ++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ ++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ ++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ ++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ ++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ ++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ ++ ++/* USB.CTRLB bit masks and bit positions */ ++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ ++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ ++ ++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ ++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ ++ ++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ ++#define USB_GNACK_bp 1 /* Global NACK bit position. */ ++ ++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ ++#define USB_ATTACH_bp 0 /* Attach bit position. */ ++ ++/* USB.STATUS bit masks and bit positions */ ++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ ++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ ++ ++#define USB_RESUME_bm 0x04 /* Resume bit mask. */ ++#define USB_RESUME_bp 2 /* Resume bit position. */ ++ ++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ ++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ ++ ++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ ++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ ++ ++/* USB.ADDR bit masks and bit positions */ ++#define USB_ADDR_gm 0x7F /* Device Address group mask. */ ++#define USB_ADDR_gp 0 /* Device Address group position. */ ++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ ++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ ++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ ++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ ++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ ++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ ++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ ++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ ++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ ++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ ++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ ++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ ++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ ++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ ++ ++/* USB.FIFOWP bit masks and bit positions */ ++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ ++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ ++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ ++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ ++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ ++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ ++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ ++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ ++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ ++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ ++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ ++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ ++ ++/* USB.FIFORP bit masks and bit positions */ ++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ ++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ ++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ ++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ ++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ ++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ ++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ ++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ ++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ ++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ ++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ ++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ ++ ++/* USB.INTCTRLA bit masks and bit positions */ ++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ ++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ ++ ++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ ++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ ++ ++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ ++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ ++ ++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ ++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ ++ ++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* USB.INTCTRLB bit masks and bit positions */ ++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ ++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ ++ ++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ ++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ ++ ++/* USB.INTFLAGSACLR bit masks and bit positions */ ++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ ++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ ++ ++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ ++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ ++ ++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ ++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ ++ ++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ ++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ ++ ++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ ++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ ++ ++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ ++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ ++ ++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ ++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ ++ ++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ ++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSASET bit masks and bit positions */ ++/* USB_SOFIF Predefined. */ ++/* USB_SOFIF Predefined. */ ++ ++/* USB_SUSPENDIF Predefined. */ ++/* USB_SUSPENDIF Predefined. */ ++ ++/* USB_RESUMEIF Predefined. */ ++/* USB_RESUMEIF Predefined. */ ++ ++/* USB_RSTIF Predefined. */ ++/* USB_RSTIF Predefined. */ ++ ++/* USB_CRCIF Predefined. */ ++/* USB_CRCIF Predefined. */ ++ ++/* USB_UNFIF Predefined. */ ++/* USB_UNFIF Predefined. */ ++ ++/* USB_OVFIF Predefined. */ ++/* USB_OVFIF Predefined. */ ++ ++/* USB_STALLIF Predefined. */ ++/* USB_STALLIF Predefined. */ ++ ++/* USB.INTFLAGSBCLR bit masks and bit positions */ ++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ ++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ ++ ++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ ++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSBSET bit masks and bit positions */ ++/* USB_TRNIF Predefined. */ ++/* USB_TRNIF Predefined. */ ++ ++/* USB_SETUPIF Predefined. */ ++/* USB_SETUPIF Predefined. */ ++ ++/* PORT - I/O Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_SPI_bm 0x20 /* SPI bit mask. */ ++#define PORT_SPI_bp 5 /* SPI bit position. */ ++ ++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ ++#define PORT_USART0_bp 4 /* USART0 bit position. */ ++ ++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ ++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ ++ ++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ ++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ ++ ++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ ++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ ++ ++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ ++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD Predefined. */ ++/* TC0_CMD Predefined. */ ++ ++/* TC0_LUPD Predefined. */ ++/* TC0_LUPD Predefined. */ ++ ++/* TC0_DIR Predefined. */ ++/* TC0_DIR Predefined. */ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV Predefined. */ ++/* TC0_CCDBV Predefined. */ ++ ++/* TC0_CCCBV Predefined. */ ++/* TC0_CCCBV Predefined. */ ++ ++/* TC0_CCBBV Predefined. */ ++/* TC0_CCBBV Predefined. */ ++ ++/* TC0_CCABV Predefined. */ ++/* TC0_CCABV Predefined. */ ++ ++/* TC0_PERBV Predefined. */ ++/* TC0_PERBV Predefined. */ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD Predefined. */ ++/* TC1_CMD Predefined. */ ++ ++/* TC1_LUPD Predefined. */ ++/* TC1_LUPD Predefined. */ ++ ++/* TC1_DIR Predefined. */ ++/* TC1_DIR Predefined. */ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV Predefined. */ ++/* TC1_CCBBV Predefined. */ ++ ++/* TC1_CCABV Predefined. */ ++/* TC1_CCABV Predefined. */ ++ ++/* TC1_PERBV Predefined. */ ++/* TC1_PERBV Predefined. */ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++/* TC2.CTRLA bit masks and bit positions */ ++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC2.CTRLB bit masks and bit positions */ ++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ ++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ ++ ++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ ++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ ++ ++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ ++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ ++ ++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ ++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ ++ ++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ ++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ ++ ++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ ++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ ++ ++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ ++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ ++ ++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ ++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ ++ ++/* TC2.CTRLC bit masks and bit positions */ ++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ ++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ ++ ++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ ++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ ++ ++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ ++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ ++ ++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ ++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ ++ ++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ ++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ ++ ++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ ++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ ++ ++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ ++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ ++ ++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ ++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ ++ ++/* TC2.CTRLE bit masks and bit positions */ ++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC2.INTCTRLA bit masks and bit positions */ ++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ ++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ ++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ ++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ ++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ ++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ ++ ++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ ++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ ++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ ++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ ++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ ++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ ++ ++/* TC2.INTCTRLB bit masks and bit positions */ ++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ ++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ ++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ ++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ ++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ ++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ ++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ ++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ ++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ ++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ ++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ ++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ ++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ ++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ ++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ ++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ ++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ ++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ ++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ ++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ ++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ ++ ++/* TC2.CTRLF bit masks and bit positions */ ++#define TC2_CMD_gm 0x0C /* Command group mask. */ ++#define TC2_CMD_gp 2 /* Command group position. */ ++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC2_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC2_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ ++#define TC2_CMDEN_gp 0 /* Command Enable group position. */ ++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ ++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ ++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ ++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ ++ ++/* TC2.INTFLAGS bit masks and bit positions */ ++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ ++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ ++ ++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ ++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ ++ ++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ ++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ ++ ++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ ++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ ++ ++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ ++ ++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ ++ ++/* AWEX - Timer/Counter Advanced Waveform Extension */ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++/* AWEX.STATUSSET bit masks and bit positions */ ++/* AWEX_FDF Predefined. */ ++/* AWEX_FDF Predefined. */ ++ ++/* AWEX_DTHSBUFV Predefined. */ ++/* AWEX_DTHSBUFV Predefined. */ ++ ++/* AWEX_DTLSBUFV Predefined. */ ++/* AWEX_DTLSBUFV Predefined. */ ++ ++/* HIRES - Timer/Counter High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ ++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* LOCKBIT - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* DMA interrupt vectors */ ++#define DMA_CH0_vect_num 6 ++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ ++#define DMA_CH1_vect_num 7 ++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ ++#define DMA_CH2_vect_num 8 ++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ ++#define DMA_CH3_vect_num 9 ++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LUNF_vect_num 14 ++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_HUNF_vect_num 15 ++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPA_vect_num 16 ++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPB_vect_num 17 ++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPC_vect_num 18 ++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPD_vect_num 19 ++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* USARTC1 interrupt vectors */ ++#define USARTC1_RXC_vect_num 28 ++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ ++#define USARTC1_DRE_vect_num 29 ++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ ++#define USARTC1_TXC_vect_num 30 ++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ ++ ++/* AES interrupt vectors */ ++#define AES_INT_vect_num 31 ++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++#define ADCA_CH1_vect_num 72 ++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ ++#define ADCA_CH2_vect_num 73 ++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ ++#define ADCA_CH3_vect_num 74 ++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LUNF_vect_num 77 ++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_HUNF_vect_num 78 ++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPA_vect_num 79 ++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPB_vect_num 80 ++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPC_vect_num 81 ++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPD_vect_num 82 ++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ ++ ++/* TCD1 interrupt vectors */ ++#define TCD1_OVF_vect_num 83 ++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ ++#define TCD1_ERR_vect_num 84 ++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ ++#define TCD1_CCA_vect_num 85 ++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ ++#define TCD1_CCB_vect_num 86 ++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* USARTD1 interrupt vectors */ ++#define USARTD1_RXC_vect_num 91 ++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ ++#define USARTD1_DRE_vect_num 92 ++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ ++#define USARTD1_TXC_vect_num 93 ++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ ++ ++/* USB interrupt vectors */ ++#define USB_BUSEVENT_vect_num 125 ++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ ++#define USB_TRNCOMPL_vect_num 126 ++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (127 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (36864) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (32768) ++#define APP_SECTION_PAGE_SIZE (256) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x7000) ++#define APPTABLE_SECTION_SIZE (4096) ++#define APPTABLE_SECTION_PAGE_SIZE (256) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x8000) ++#define BOOT_SECTION_SIZE (4096) ++#define BOOT_SECTION_PAGE_SIZE (256) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (12288) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (1024) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (4096) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (1024) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (6) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (256) ++#define USER_SIGNATURES_PAGE_SIZE (256) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (256) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 256 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 Reserved */ ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x41 ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA32A4U_H_INCLUDED */ ++ diff --git a/include/avr/iox32c3.h b/include/avr/iox32c3.h new file mode 100644 -index 0000000..4bc551a +index 0000000..c832d3f --- /dev/null +++ b/include/avr/iox32c3.h @@ -0,0 +1,6216 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox32c3.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA32C3_H_INCLUDED -+#define _AVR_ATXMEGA32C3_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+VPORT - Virtual Ports -+-------------------------------------------------------------------------- -+*/ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t USBCTRL; /* USB Control Register */ -+} CLK_t; -+ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t reserved_0x02; -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t PRPD; /* Power Reduction Port D */ -+ register8_t PRPE; /* Power Reduction Port E */ -+ register8_t PRPF; /* Power Reduction Port F */ -+} PR_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+/* USB Prescaler Division Factor */ -+typedef enum CLK_USBPSDIV_enum -+{ -+ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ -+ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ -+ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ -+ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ -+ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ -+ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -+} CLK_USBPSDIV_t; -+ -+/* USB Clock Source */ -+typedef enum CLK_USBSRC_enum -+{ -+ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ -+ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -+} CLK_USBSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control Register */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+/* 2 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC2MCREF_enum -+{ -+ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC2MCREF_t; -+ -+/* 32 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC32MCREF_enum -+{ -+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -+} OSC_RC32MCREF_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t ANAINIT; /* Analog Startup Delay */ -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t AWEXLOCK; /* AWEX Lock */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORTCFG - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t VPCTRLA; /* Virtual Port Control Register A */ -+ register8_t VPCTRLB; /* Virtual Port Control Register B */ -+ register8_t CLKEVOUT; /* Clock and Event Out Register */ -+ register8_t reserved_0x05; -+ register8_t EVOUTSEL; /* Event Output Select */ -+} PORTCFG_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP02MAP_enum -+{ -+ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ -+ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ -+ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ -+ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ -+ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ -+ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ -+ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ -+ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ -+ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ -+ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ -+ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ -+ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ -+ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ -+ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ -+ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ -+ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -+} PORTCFG_VP02MAP_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP13MAP_enum -+{ -+ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ -+ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ -+ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ -+ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ -+ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ -+ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ -+ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ -+ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ -+ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ -+ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ -+ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ -+ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ -+ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ -+ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ -+ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ -+ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -+} PORTCFG_VP13MAP_t; -+ -+/* System Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ -+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ -+ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -+} PORTCFG_CLKOUT_t; -+ -+/* Peripheral Clock Output Select */ -+typedef enum PORTCFG_CLKOUTSEL_enum -+{ -+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -+} PORTCFG_CLKOUTSEL_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ -+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ -+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -+} PORTCFG_EVOUT_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+} EVSYS_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ -+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ -+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ -+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ -+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ -+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ -+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ -+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ -+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ -+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ -+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ -+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ -+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ -+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ -+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ -+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ -+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ -+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ -+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ -+ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ -+ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ -+ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ -+ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ -+ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ -+ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ -+ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ -+ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ -+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ -+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ -+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ -+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ -+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ -+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ -+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ -+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ -+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ -+ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ -+ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ -+ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ -+ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ -+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ -+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ -+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ -+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ -+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -+ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ -+ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ -+ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ -+ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ -+ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -+} EVSYS_CHMUX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ -+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ -+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ -+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ -+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} NVM_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t reserved_0x07; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+} ADC_t; -+ -+/* Current Limitation */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -+} ADC_CURRLIMIT_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+} ADC_CH_MUXNEG_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ -+ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ -+ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ -+ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC - Real-Time Counter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Real-Time Counter */ -+typedef struct RTC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary register */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ _WORDREGISTER(CNT); /* Count Register */ -+ _WORDREGISTER(PER); /* Period Register */ -+ _WORDREGISTER(COMP); /* Compare Register */ -+} RTC_t; -+ -+/* Prescaler Factor */ -+typedef enum RTC_PRESCALER_enum -+{ -+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ -+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ -+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ -+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ -+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ -+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ -+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ -+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -+} RTC_PRESCALER_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC_COMPINTLVL_enum -+{ -+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC_OVFINTLVL_enum -+{ -+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+} TWI_t; -+ -+/* SDA Hold Time */ -+typedef enum TWI_SDAHOLD_enum -+{ -+ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ -+ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ -+ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ -+ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -+} TWI_SDAHOLD_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USB - USB -+-------------------------------------------------------------------------- -+*/ -+ -+/* USB Endpoint */ -+typedef struct USB_EP_struct -+{ -+ register8_t STATUS; /* Endpoint Status */ -+ register8_t CTRL; /* Endpoint Control */ -+ _WORDREGISTER(CNT); /* USB Endpoint Counter */ -+ _WORDREGISTER(DATAPTR); /* Data Pointer */ -+ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -+} USB_EP_t; -+ -+ -+/* Universal Serial Bus */ -+typedef struct USB_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t FIFOWP; /* FIFO Write Pointer Register */ -+ register8_t FIFORP; /* FIFO Read Pointer Register */ -+ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ -+ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ -+ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ -+ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t reserved_0x20; -+ register8_t reserved_0x21; -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t CAL0; /* Calibration Byte 0 */ -+ register8_t CAL1; /* Calibration Byte 1 */ -+} USB_t; -+ -+ -+/* USB Endpoint Table */ -+typedef struct USB_EP_TABLE_struct -+{ -+ USB_EP_t EP0OUT; /* Endpoint 0 */ -+ USB_EP_t EP0IN; /* Endpoint 0 */ -+ USB_EP_t EP1OUT; /* Endpoint 1 */ -+ USB_EP_t EP1IN; /* Endpoint 1 */ -+ USB_EP_t EP2OUT; /* Endpoint 2 */ -+ USB_EP_t EP2IN; /* Endpoint 2 */ -+ USB_EP_t EP3OUT; /* Endpoint 3 */ -+ USB_EP_t EP3IN; /* Endpoint 3 */ -+ USB_EP_t EP4OUT; /* Endpoint 4 */ -+ USB_EP_t EP4IN; /* Endpoint 4 */ -+ USB_EP_t EP5OUT; /* Endpoint 5 */ -+ USB_EP_t EP5IN; /* Endpoint 5 */ -+ USB_EP_t EP6OUT; /* Endpoint 6 */ -+ USB_EP_t EP6IN; /* Endpoint 6 */ -+ USB_EP_t EP7OUT; /* Endpoint 7 */ -+ USB_EP_t EP7IN; /* Endpoint 7 */ -+ USB_EP_t EP8OUT; /* Endpoint 8 */ -+ USB_EP_t EP8IN; /* Endpoint 8 */ -+ USB_EP_t EP9OUT; /* Endpoint 9 */ -+ USB_EP_t EP9IN; /* Endpoint 9 */ -+ USB_EP_t EP10OUT; /* Endpoint 10 */ -+ USB_EP_t EP10IN; /* Endpoint 10 */ -+ USB_EP_t EP11OUT; /* Endpoint 11 */ -+ USB_EP_t EP11IN; /* Endpoint 11 */ -+ USB_EP_t EP12OUT; /* Endpoint 12 */ -+ USB_EP_t EP12IN; /* Endpoint 12 */ -+ USB_EP_t EP13OUT; /* Endpoint 13 */ -+ USB_EP_t EP13IN; /* Endpoint 13 */ -+ USB_EP_t EP14OUT; /* Endpoint 14 */ -+ USB_EP_t EP14IN; /* Endpoint 14 */ -+ USB_EP_t EP15OUT; /* Endpoint 15 */ -+ USB_EP_t EP15IN; /* Endpoint 15 */ -+ register8_t reserved_0x100; -+ register8_t reserved_0x101; -+ register8_t reserved_0x102; -+ register8_t reserved_0x103; -+ register8_t reserved_0x104; -+ register8_t reserved_0x105; -+ register8_t reserved_0x106; -+ register8_t reserved_0x107; -+ register8_t reserved_0x108; -+ register8_t reserved_0x109; -+ register8_t reserved_0x10A; -+ register8_t reserved_0x10B; -+ register8_t reserved_0x10C; -+ register8_t reserved_0x10D; -+ register8_t reserved_0x10E; -+ register8_t reserved_0x10F; -+ register8_t FRAMENUML; /* Frame Number Low Byte */ -+ register8_t FRAMENUMH; /* Frame Number High Byte */ -+} USB_EP_TABLE_t; -+ -+/* Interrupt level */ -+typedef enum USB_INTLVL_enum -+{ -+ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} USB_INTLVL_t; -+ -+/* USB Endpoint Type */ -+typedef enum USB_EP_TYPE_enum -+{ -+ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ -+ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ -+ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ -+ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -+} USB_EP_TYPE_t; -+ -+/* USB Endpoint Buffersize */ -+typedef enum USB_EP_BUFSIZE_enum -+{ -+ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ -+ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ -+ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ -+ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ -+ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ -+ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ -+ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ -+ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -+} USB_EP_BUFSIZE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - I/O Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INT0MASK; /* Port Interrupt 0 Mask */ -+ register8_t INT1MASK; /* Port Interrupt 1 Mask */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t REMAP; /* I/O Port Pin Remap Register */ -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Port Interrupt 0 Level */ -+typedef enum PORT_INT0LVL_enum -+{ -+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INT0LVL_t; -+ -+/* Port Interrupt 1 Level */ -+typedef enum PORT_INT1LVL_enum -+{ -+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ -+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ -+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -+} PORT_INT1LVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 0 */ -+typedef struct TC0_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC0_t; -+ -+ -+/* 16-bit Timer/Counter 1 */ -+typedef struct TC1_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+} TC1_t; -+ -+/* Clock Selection */ -+typedef enum TC_CLKSEL_enum -+{ -+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_CLKSEL_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC_WGMODE_enum -+{ -+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC_WGMODE_t; -+ -+/* Byte Mode */ -+typedef enum TC_BYTEM_enum -+{ -+ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ -+ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -+} TC_BYTEM_t; -+ -+/* Event Action */ -+typedef enum TC_EVACT_enum -+{ -+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ -+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ -+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ -+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ -+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ -+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC_EVSEL_enum -+{ -+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_EVSEL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC_ERRINTLVL_enum -+{ -+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC_OVFINTLVL_enum -+{ -+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_OVFINTLVL_t; -+ -+/* Compare or Capture D Interrupt Level */ -+typedef enum TC_CCDINTLVL_enum -+{ -+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC_CCDINTLVL_t; -+ -+/* Compare or Capture C Interrupt Level */ -+typedef enum TC_CCCINTLVL_enum -+{ -+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC_CCCINTLVL_t; -+ -+/* Compare or Capture B Interrupt Level */ -+typedef enum TC_CCBINTLVL_enum -+{ -+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_CCBINTLVL_t; -+ -+/* Compare or Capture A Interrupt Level */ -+typedef enum TC_CCAINTLVL_enum -+{ -+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_CCAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC_CMD_enum -+{ -+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC2 - 16-bit Timer/Counter type 2 -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter type 2 */ -+typedef struct TC2_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t reserved_0x03; -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t reserved_0x08; -+ register8_t CTRLF; /* Control Register F */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t LCNT; /* Low Byte Count */ -+ register8_t HCNT; /* High Byte Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t LPER; /* Low Byte Period */ -+ register8_t HPER; /* High Byte Period */ -+ register8_t LCMPA; /* Low Byte Compare A */ -+ register8_t HCMPA; /* High Byte Compare A */ -+ register8_t LCMPB; /* Low Byte Compare B */ -+ register8_t HCMPB; /* High Byte Compare B */ -+ register8_t LCMPC; /* Low Byte Compare C */ -+ register8_t HCMPC; /* High Byte Compare C */ -+ register8_t LCMPD; /* Low Byte Compare D */ -+ register8_t HCMPD; /* High Byte Compare D */ -+} TC2_t; -+ -+/* Clock Selection */ -+typedef enum TC2_CLKSEL_enum -+{ -+ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC2_CLKSEL_t; -+ -+/* Byte Mode */ -+typedef enum TC2_BYTEM_enum -+{ -+ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ -+ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -+} TC2_BYTEM_t; -+ -+/* High Byte Underflow Interrupt Level */ -+typedef enum TC2_HUNFINTLVL_enum -+{ -+ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_HUNFINTLVL_t; -+ -+/* Low Byte Underflow Interrupt Level */ -+typedef enum TC2_LUNFINTLVL_enum -+{ -+ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LUNFINTLVL_t; -+ -+/* Low Byte Compare D Interrupt Level */ -+typedef enum TC2_LCMPDINTLVL_enum -+{ -+ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC2_LCMPDINTLVL_t; -+ -+/* Low Byte Compare C Interrupt Level */ -+typedef enum TC2_LCMPCINTLVL_enum -+{ -+ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC2_LCMPCINTLVL_t; -+ -+/* Low Byte Compare B Interrupt Level */ -+typedef enum TC2_LCMPBINTLVL_enum -+{ -+ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_LCMPBINTLVL_t; -+ -+/* Low Byte Compare A Interrupt Level */ -+typedef enum TC2_LCMPAINTLVL_enum -+{ -+ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LCMPAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMD_enum -+{ -+ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC2_CMD_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMDEN_enum -+{ -+ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ -+ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ -+ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -+} TC2_CMDEN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AWEX - Timer/Counter Advanced Waveform Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Advanced Waveform Extension */ -+typedef struct AWEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t FDEMASK; /* Fault Detection Event Mask */ -+ register8_t FDCTRL; /* Fault Detection Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t STATUSSET; /* Status Set Register */ -+ register8_t DTBOTH; /* Dead Time Both Sides */ -+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ -+ register8_t DTLS; /* Dead Time Low Side */ -+ register8_t DTHS; /* Dead Time High Side */ -+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ -+ register8_t DTHSBUF; /* Dead Time High Side Buffer */ -+ register8_t OUTOVEN; /* Output Override Enable */ -+} AWEX_t; -+ -+/* Fault Detect Action */ -+typedef enum AWEX_FDACT_enum -+{ -+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ -+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -+} AWEX_FDACT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+HIRES - Timer/Counter High-Resolution Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register */ -+} HIRES_t; -+ -+/* High Resolution Enable */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ -+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+} IRDA_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t reserved_0x00; -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+} NVM_FUSES_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* Timer Oscillator pin location */ -+typedef enum TOSCSEL_enum -+{ -+ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ -+ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -+} TOSCSEL_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -+} BOD_t; -+ -+/* BOD operation */ -+typedef enum BODACT_enum -+{ -+ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BODACT_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WDP_enum -+{ -+ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ -+ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ -+ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ -+ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ -+ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ -+ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ -+ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ -+ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ -+ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ -+ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ -+ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -+} WDP_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LOCKBIT - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ -+ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t USBCAL0; /* USB Calibration Byte 0 */ -+ register8_t USBCAL1; /* USB Calibration Byte 1 */ -+ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ -+ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+} NVM_PROD_SIGNATURES_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -+#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -+#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -+#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -+#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -+#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -+#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -+#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -+#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -+#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -+#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -+#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -+#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+#define CLK_USBCTRL _SFR_MEM8(0x0044) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* DFLL - DFLL */ -+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -+#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -+#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPD _SFR_MEM8(0x0074) -+#define PR_PRPE _SFR_MEM8(0x0075) -+#define PR_PRPF _SFR_MEM8(0x0076) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_ANAINIT _SFR_MEM8(0x0097) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_AWEXLOCK _SFR_MEM8(0x0099) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCA_CTRLA _SFR_MEM8(0x0200) -+#define ADCA_CTRLB _SFR_MEM8(0x0201) -+#define ADCA_REFCTRL _SFR_MEM8(0x0202) -+#define ADCA_EVCTRL _SFR_MEM8(0x0203) -+#define ADCA_PRESCALER _SFR_MEM8(0x0204) -+#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -+#define ADCA_TEMP _SFR_MEM8(0x0207) -+#define ADCA_CAL _SFR_MEM16(0x020C) -+#define ADCA_CH0RES _SFR_MEM16(0x0210) -+#define ADCA_CMP _SFR_MEM16(0x0218) -+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -+#define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -+ -+/* AC - Analog Comparator */ -+#define ACA_AC0CTRL _SFR_MEM8(0x0380) -+#define ACA_AC1CTRL _SFR_MEM8(0x0381) -+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -+#define ACA_CTRLA _SFR_MEM8(0x0384) -+#define ACA_CTRLB _SFR_MEM8(0x0385) -+#define ACA_WINCTRL _SFR_MEM8(0x0386) -+#define ACA_STATUS _SFR_MEM8(0x0387) -+ -+/* RTC - Real-Time Counter */ -+#define RTC_CTRL _SFR_MEM8(0x0400) -+#define RTC_STATUS _SFR_MEM8(0x0401) -+#define RTC_INTCTRL _SFR_MEM8(0x0402) -+#define RTC_INTFLAGS _SFR_MEM8(0x0403) -+#define RTC_TEMP _SFR_MEM8(0x0404) -+#define RTC_CNT _SFR_MEM16(0x0408) -+#define RTC_PER _SFR_MEM16(0x040A) -+#define RTC_COMP _SFR_MEM16(0x040C) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIE_CTRL _SFR_MEM8(0x04A0) -+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -+ -+/* USB - Universal Serial Bus */ -+#define USB_CTRLA _SFR_MEM8(0x04C0) -+#define USB_CTRLB _SFR_MEM8(0x04C1) -+#define USB_STATUS _SFR_MEM8(0x04C2) -+#define USB_ADDR _SFR_MEM8(0x04C3) -+#define USB_FIFOWP _SFR_MEM8(0x04C4) -+#define USB_FIFORP _SFR_MEM8(0x04C5) -+#define USB_EPPTR _SFR_MEM16(0x04C6) -+#define USB_INTCTRLA _SFR_MEM8(0x04C8) -+#define USB_INTCTRLB _SFR_MEM8(0x04C9) -+#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -+#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -+#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -+#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -+#define USB_CAL0 _SFR_MEM8(0x04FA) -+#define USB_CAL1 _SFR_MEM8(0x04FB) -+ -+/* PORT - I/O Ports */ -+#define PORTA_DIR _SFR_MEM8(0x0600) -+#define PORTA_DIRSET _SFR_MEM8(0x0601) -+#define PORTA_DIRCLR _SFR_MEM8(0x0602) -+#define PORTA_DIRTGL _SFR_MEM8(0x0603) -+#define PORTA_OUT _SFR_MEM8(0x0604) -+#define PORTA_OUTSET _SFR_MEM8(0x0605) -+#define PORTA_OUTCLR _SFR_MEM8(0x0606) -+#define PORTA_OUTTGL _SFR_MEM8(0x0607) -+#define PORTA_IN _SFR_MEM8(0x0608) -+#define PORTA_INTCTRL _SFR_MEM8(0x0609) -+#define PORTA_INT0MASK _SFR_MEM8(0x060A) -+#define PORTA_INT1MASK _SFR_MEM8(0x060B) -+#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_REMAP _SFR_MEM8(0x060E) -+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -+ -+/* PORT - I/O Ports */ -+#define PORTB_DIR _SFR_MEM8(0x0620) -+#define PORTB_DIRSET _SFR_MEM8(0x0621) -+#define PORTB_DIRCLR _SFR_MEM8(0x0622) -+#define PORTB_DIRTGL _SFR_MEM8(0x0623) -+#define PORTB_OUT _SFR_MEM8(0x0624) -+#define PORTB_OUTSET _SFR_MEM8(0x0625) -+#define PORTB_OUTCLR _SFR_MEM8(0x0626) -+#define PORTB_OUTTGL _SFR_MEM8(0x0627) -+#define PORTB_IN _SFR_MEM8(0x0628) -+#define PORTB_INTCTRL _SFR_MEM8(0x0629) -+#define PORTB_INT0MASK _SFR_MEM8(0x062A) -+#define PORTB_INT1MASK _SFR_MEM8(0x062B) -+#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -+#define PORTB_REMAP _SFR_MEM8(0x062E) -+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INT0MASK _SFR_MEM8(0x064A) -+#define PORTC_INT1MASK _SFR_MEM8(0x064B) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INT0MASK _SFR_MEM8(0x066A) -+#define PORTD_INT1MASK _SFR_MEM8(0x066B) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTE_DIR _SFR_MEM8(0x0680) -+#define PORTE_DIRSET _SFR_MEM8(0x0681) -+#define PORTE_DIRCLR _SFR_MEM8(0x0682) -+#define PORTE_DIRTGL _SFR_MEM8(0x0683) -+#define PORTE_OUT _SFR_MEM8(0x0684) -+#define PORTE_OUTSET _SFR_MEM8(0x0685) -+#define PORTE_OUTCLR _SFR_MEM8(0x0686) -+#define PORTE_OUTTGL _SFR_MEM8(0x0687) -+#define PORTE_IN _SFR_MEM8(0x0688) -+#define PORTE_INTCTRL _SFR_MEM8(0x0689) -+#define PORTE_INT0MASK _SFR_MEM8(0x068A) -+#define PORTE_INT1MASK _SFR_MEM8(0x068B) -+#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -+#define PORTE_REMAP _SFR_MEM8(0x068E) -+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) -+ -+/* PORT - I/O Ports */ -+#define PORTF_DIR _SFR_MEM8(0x06A0) -+#define PORTF_DIRSET _SFR_MEM8(0x06A1) -+#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -+#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -+#define PORTF_OUT _SFR_MEM8(0x06A4) -+#define PORTF_OUTSET _SFR_MEM8(0x06A5) -+#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -+#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -+#define PORTF_IN _SFR_MEM8(0x06A8) -+#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -+#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -+#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -+#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -+#define PORTF_REMAP _SFR_MEM8(0x06AE) -+#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -+#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -+#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -+#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -+#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -+#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -+#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -+#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -+#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCC0_CTRLA _SFR_MEM8(0x0800) -+#define TCC0_CTRLB _SFR_MEM8(0x0801) -+#define TCC0_CTRLC _SFR_MEM8(0x0802) -+#define TCC0_CTRLD _SFR_MEM8(0x0803) -+#define TCC0_CTRLE _SFR_MEM8(0x0804) -+#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -+#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -+#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -+#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC0_TEMP _SFR_MEM8(0x080F) -+#define TCC0_CNT _SFR_MEM16(0x0820) -+#define TCC0_PER _SFR_MEM16(0x0826) -+#define TCC0_CCA _SFR_MEM16(0x0828) -+#define TCC0_CCB _SFR_MEM16(0x082A) -+#define TCC0_CCC _SFR_MEM16(0x082C) -+#define TCC0_CCD _SFR_MEM16(0x082E) -+#define TCC0_PERBUF _SFR_MEM16(0x0836) -+#define TCC0_CCABUF _SFR_MEM16(0x0838) -+#define TCC0_CCBBUF _SFR_MEM16(0x083A) -+#define TCC0_CCCBUF _SFR_MEM16(0x083C) -+#define TCC0_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCC2_CTRLA _SFR_MEM8(0x0800) -+#define TCC2_CTRLB _SFR_MEM8(0x0801) -+#define TCC2_CTRLC _SFR_MEM8(0x0802) -+#define TCC2_CTRLE _SFR_MEM8(0x0804) -+#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC2_CTRLF _SFR_MEM8(0x0809) -+#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC2_LCNT _SFR_MEM8(0x0820) -+#define TCC2_HCNT _SFR_MEM8(0x0821) -+#define TCC2_LPER _SFR_MEM8(0x0826) -+#define TCC2_HPER _SFR_MEM8(0x0827) -+#define TCC2_LCMPA _SFR_MEM8(0x0828) -+#define TCC2_HCMPA _SFR_MEM8(0x0829) -+#define TCC2_LCMPB _SFR_MEM8(0x082A) -+#define TCC2_HCMPB _SFR_MEM8(0x082B) -+#define TCC2_LCMPC _SFR_MEM8(0x082C) -+#define TCC2_HCMPC _SFR_MEM8(0x082D) -+#define TCC2_LCMPD _SFR_MEM8(0x082E) -+#define TCC2_HCMPD _SFR_MEM8(0x082F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCC1_CTRLA _SFR_MEM8(0x0840) -+#define TCC1_CTRLB _SFR_MEM8(0x0841) -+#define TCC1_CTRLC _SFR_MEM8(0x0842) -+#define TCC1_CTRLD _SFR_MEM8(0x0843) -+#define TCC1_CTRLE _SFR_MEM8(0x0844) -+#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -+#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -+#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -+#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC1_TEMP _SFR_MEM8(0x084F) -+#define TCC1_CNT _SFR_MEM16(0x0860) -+#define TCC1_PER _SFR_MEM16(0x0866) -+#define TCC1_CCA _SFR_MEM16(0x0868) -+#define TCC1_CCB _SFR_MEM16(0x086A) -+#define TCC1_PERBUF _SFR_MEM16(0x0876) -+#define TCC1_CCABUF _SFR_MEM16(0x0878) -+#define TCC1_CCBBUF _SFR_MEM16(0x087A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXC_CTRL _SFR_MEM8(0x0880) -+#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -+#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -+#define AWEXC_STATUS _SFR_MEM8(0x0884) -+#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -+#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -+#define AWEXC_DTLS _SFR_MEM8(0x0888) -+#define AWEXC_DTHS _SFR_MEM8(0x0889) -+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x0890) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08A0) -+#define USARTC0_STATUS _SFR_MEM8(0x08A1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -+#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -+#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIC_CTRL _SFR_MEM8(0x08C0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -+#define SPIC_STATUS _SFR_MEM8(0x08C2) -+#define SPIC_DATA _SFR_MEM8(0x08C3) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCD0_CTRLA _SFR_MEM8(0x0900) -+#define TCD0_CTRLB _SFR_MEM8(0x0901) -+#define TCD0_CTRLC _SFR_MEM8(0x0902) -+#define TCD0_CTRLD _SFR_MEM8(0x0903) -+#define TCD0_CTRLE _SFR_MEM8(0x0904) -+#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -+#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -+#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -+#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -+#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD0_TEMP _SFR_MEM8(0x090F) -+#define TCD0_CNT _SFR_MEM16(0x0920) -+#define TCD0_PER _SFR_MEM16(0x0926) -+#define TCD0_CCA _SFR_MEM16(0x0928) -+#define TCD0_CCB _SFR_MEM16(0x092A) -+#define TCD0_CCC _SFR_MEM16(0x092C) -+#define TCD0_CCD _SFR_MEM16(0x092E) -+#define TCD0_PERBUF _SFR_MEM16(0x0936) -+#define TCD0_CCABUF _SFR_MEM16(0x0938) -+#define TCD0_CCBBUF _SFR_MEM16(0x093A) -+#define TCD0_CCCBUF _SFR_MEM16(0x093C) -+#define TCD0_CCDBUF _SFR_MEM16(0x093E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCD2_CTRLA _SFR_MEM8(0x0900) -+#define TCD2_CTRLB _SFR_MEM8(0x0901) -+#define TCD2_CTRLC _SFR_MEM8(0x0902) -+#define TCD2_CTRLE _SFR_MEM8(0x0904) -+#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD2_CTRLF _SFR_MEM8(0x0909) -+#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD2_LCNT _SFR_MEM8(0x0920) -+#define TCD2_HCNT _SFR_MEM8(0x0921) -+#define TCD2_LPER _SFR_MEM8(0x0926) -+#define TCD2_HPER _SFR_MEM8(0x0927) -+#define TCD2_LCMPA _SFR_MEM8(0x0928) -+#define TCD2_HCMPA _SFR_MEM8(0x0929) -+#define TCD2_LCMPB _SFR_MEM8(0x092A) -+#define TCD2_HCMPB _SFR_MEM8(0x092B) -+#define TCD2_LCMPC _SFR_MEM8(0x092C) -+#define TCD2_HCMPC _SFR_MEM8(0x092D) -+#define TCD2_LCMPD _SFR_MEM8(0x092E) -+#define TCD2_HCMPD _SFR_MEM8(0x092F) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD0_DATA _SFR_MEM8(0x09A0) -+#define USARTD0_STATUS _SFR_MEM8(0x09A1) -+#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -+#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -+#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPID_CTRL _SFR_MEM8(0x09C0) -+#define SPID_INTCTRL _SFR_MEM8(0x09C1) -+#define SPID_STATUS _SFR_MEM8(0x09C2) -+#define SPID_DATA _SFR_MEM8(0x09C3) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCE0_CTRLA _SFR_MEM8(0x0A00) -+#define TCE0_CTRLB _SFR_MEM8(0x0A01) -+#define TCE0_CTRLC _SFR_MEM8(0x0A02) -+#define TCE0_CTRLD _SFR_MEM8(0x0A03) -+#define TCE0_CTRLE _SFR_MEM8(0x0A04) -+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE0_TEMP _SFR_MEM8(0x0A0F) -+#define TCE0_CNT _SFR_MEM16(0x0A20) -+#define TCE0_PER _SFR_MEM16(0x0A26) -+#define TCE0_CCA _SFR_MEM16(0x0A28) -+#define TCE0_CCB _SFR_MEM16(0x0A2A) -+#define TCE0_CCC _SFR_MEM16(0x0A2C) -+#define TCE0_CCD _SFR_MEM16(0x0A2E) -+#define TCE0_PERBUF _SFR_MEM16(0x0A36) -+#define TCE0_CCABUF _SFR_MEM16(0x0A38) -+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCE2_CTRLA _SFR_MEM8(0x0A00) -+#define TCE2_CTRLB _SFR_MEM8(0x0A01) -+#define TCE2_CTRLC _SFR_MEM8(0x0A02) -+#define TCE2_CTRLE _SFR_MEM8(0x0A04) -+#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE2_CTRLF _SFR_MEM8(0x0A09) -+#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE2_LCNT _SFR_MEM8(0x0A20) -+#define TCE2_HCNT _SFR_MEM8(0x0A21) -+#define TCE2_LPER _SFR_MEM8(0x0A26) -+#define TCE2_HPER _SFR_MEM8(0x0A27) -+#define TCE2_LCMPA _SFR_MEM8(0x0A28) -+#define TCE2_HCMPA _SFR_MEM8(0x0A29) -+#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -+#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -+#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -+#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -+#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -+#define TCE2_HCMPD _SFR_MEM8(0x0A2F) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE0_DATA _SFR_MEM8(0x0AA0) -+#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -+#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -+#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -+#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -+#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -+#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCF0_CTRLA _SFR_MEM8(0x0B00) -+#define TCF0_CTRLB _SFR_MEM8(0x0B01) -+#define TCF0_CTRLC _SFR_MEM8(0x0B02) -+#define TCF0_CTRLD _SFR_MEM8(0x0B03) -+#define TCF0_CTRLE _SFR_MEM8(0x0B04) -+#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -+#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -+#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -+#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -+#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -+#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -+#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -+#define TCF0_TEMP _SFR_MEM8(0x0B0F) -+#define TCF0_CNT _SFR_MEM16(0x0B20) -+#define TCF0_PER _SFR_MEM16(0x0B26) -+#define TCF0_CCA _SFR_MEM16(0x0B28) -+#define TCF0_CCB _SFR_MEM16(0x0B2A) -+#define TCF0_CCC _SFR_MEM16(0x0B2C) -+#define TCF0_CCD _SFR_MEM16(0x0B2E) -+#define TCF0_PERBUF _SFR_MEM16(0x0B36) -+#define TCF0_CCABUF _SFR_MEM16(0x0B38) -+#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -+#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -+#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCF2_CTRLA _SFR_MEM8(0x0B00) -+#define TCF2_CTRLB _SFR_MEM8(0x0B01) -+#define TCF2_CTRLC _SFR_MEM8(0x0B02) -+#define TCF2_CTRLE _SFR_MEM8(0x0B04) -+#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -+#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -+#define TCF2_CTRLF _SFR_MEM8(0x0B09) -+#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -+#define TCF2_LCNT _SFR_MEM8(0x0B20) -+#define TCF2_HCNT _SFR_MEM8(0x0B21) -+#define TCF2_LPER _SFR_MEM8(0x0B26) -+#define TCF2_HPER _SFR_MEM8(0x0B27) -+#define TCF2_LCMPA _SFR_MEM8(0x0B28) -+#define TCF2_HCMPA _SFR_MEM8(0x0B29) -+#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -+#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -+#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -+#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -+#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -+#define TCF2_HCMPD _SFR_MEM8(0x0B2F) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* VPORT - Virtual Ports */ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* CLK.USBCTRL bit masks and bit positions */ -+#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -+#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -+#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -+#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -+#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -+#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -+#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -+#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ -+ -+#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -+#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -+#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ -+ -+#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_USB_bm 0x40 /* USB bit mask. */ -+#define PR_USB_bp 6 /* USB bit position. */ -+ -+#define PR_AES_bm 0x10 /* AES bit mask. */ -+#define PR_AES_bp 4 /* AES bit position. */ -+ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -+#define PR_DMA_bp 0 /* DMA-Controller bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -+#define PR_USART1_bp 5 /* Port C USART1 bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -+#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ -+ -+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -+ -+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ -+ -+/* PR.PRPD bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPE bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPF bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -+#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -+#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ -+ -+#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ -+ -+#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -+#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.ANAINIT bit masks and bit positions */ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.AWEXLOCK bit masks and bit positions */ -+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* PORTCFG - Port Configuration */ -+/* PORTCFG.VPCTRLA bit masks and bit positions */ -+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ -+ -+/* PORTCFG.VPCTRLB bit masks and bit positions */ -+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ -+ -+/* PORTCFG.CLKEVOUT bit masks and bit positions */ -+#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ -+ -+#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -+#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -+#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -+#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -+#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -+#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ -+ -+#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -+#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ -+ -+#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -+#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ -+ -+/* PORTCFG.EVOUTSEL bit masks and bit positions */ -+#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -+#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -+#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -+#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -+#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -+#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -+#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -+#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0x7F /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ -+ -+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ -+ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -+#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -+#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -+#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -+#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -+#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -+#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -+#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -+#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -+#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ -+ -+#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -+#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -+#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -+#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -+#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -+#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -+#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -+#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -+#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -+#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -+#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* RTC - Real-Time Counter */ -+/* RTC.CTRL bit masks and bit positions */ -+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ -+ -+/* RTC.STATUS bit masks and bit positions */ -+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC.INTCTRL bit masks and bit positions */ -+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC.INTFLAGS bit masks and bit positions */ -+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* USB - USB */ -+/* USB_EP.STATUS bit masks and bit positions */ -+#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -+#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ -+ -+#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -+#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ -+ -+#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -+#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ -+ -+#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -+#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ -+ -+#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -+#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ -+ -+#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -+#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ -+ -+#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -+#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ -+ -+#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -+#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ -+ -+#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ -+ -+#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ -+ -+#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -+#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ -+ -+/* USB_EP.CTRL bit masks and bit positions */ -+#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -+#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -+#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -+#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -+#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -+#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ -+ -+#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -+#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ -+ -+#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -+#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ -+ -+#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -+#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ -+ -+#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -+#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ -+ -+#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -+#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -+#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -+#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -+#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -+#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -+#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -+#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ -+ -+/* USB_EP.CNT bit masks and bit positions */ -+#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -+#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ -+ -+/* USB.CTRLA bit masks and bit positions */ -+#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -+#define USB_ENABLE_bp 7 /* USB Enable bit position. */ -+ -+#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -+#define USB_SPEED_bp 6 /* Speed Select bit position. */ -+ -+#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -+#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ -+ -+#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -+#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ -+ -+#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -+#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -+#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -+#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -+#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -+#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -+#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -+#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -+#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -+#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ -+ -+/* USB.CTRLB bit masks and bit positions */ -+#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -+#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ -+ -+#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -+#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ -+ -+#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -+#define USB_GNACK_bp 1 /* Global NACK bit position. */ -+ -+#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -+#define USB_ATTACH_bp 0 /* Attach bit position. */ -+ -+/* USB.STATUS bit masks and bit positions */ -+#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -+#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ -+ -+#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -+#define USB_RESUME_bp 2 /* Resume bit position. */ -+ -+#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -+#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ -+ -+#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -+#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ -+ -+/* USB.ADDR bit masks and bit positions */ -+#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -+#define USB_ADDR_gp 0 /* Device Address group position. */ -+#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -+#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -+#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -+#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -+#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -+#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -+#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -+#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -+#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -+#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -+#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -+#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -+#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -+#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ -+ -+/* USB.FIFOWP bit masks and bit positions */ -+#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -+#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -+#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -+#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -+#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -+#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -+#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -+#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -+#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -+#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -+#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -+#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ -+ -+/* USB.FIFORP bit masks and bit positions */ -+#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -+#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -+#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -+#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -+#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -+#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -+#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -+#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -+#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -+#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -+#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -+#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ -+ -+/* USB.INTCTRLA bit masks and bit positions */ -+#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -+#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ -+ -+#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -+#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ -+ -+#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -+#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ -+ -+#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -+#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ -+ -+#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* USB.INTCTRLB bit masks and bit positions */ -+#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -+#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ -+ -+#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -+#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ -+ -+/* USB.INTFLAGSACLR bit masks and bit positions */ -+#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -+#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ -+ -+#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -+#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ -+ -+#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -+#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ -+ -+#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -+#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ -+ -+#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -+#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ -+ -+#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -+#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ -+ -+#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -+#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ -+ -+#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -+#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSASET bit masks and bit positions */ -+/* USB_SOFIF Predefined. */ -+/* USB_SOFIF Predefined. */ -+ -+/* USB_SUSPENDIF Predefined. */ -+/* USB_SUSPENDIF Predefined. */ -+ -+/* USB_RESUMEIF Predefined. */ -+/* USB_RESUMEIF Predefined. */ -+ -+/* USB_RSTIF Predefined. */ -+/* USB_RSTIF Predefined. */ -+ -+/* USB_CRCIF Predefined. */ -+/* USB_CRCIF Predefined. */ -+ -+/* USB_UNFIF Predefined. */ -+/* USB_UNFIF Predefined. */ -+ -+/* USB_OVFIF Predefined. */ -+/* USB_OVFIF Predefined. */ -+ -+/* USB_STALLIF Predefined. */ -+/* USB_STALLIF Predefined. */ -+ -+/* USB.INTFLAGSBCLR bit masks and bit positions */ -+#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -+#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ -+ -+#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -+#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSBSET bit masks and bit positions */ -+/* USB_TRNIF Predefined. */ -+/* USB_TRNIF Predefined. */ -+ -+/* USB_SETUPIF Predefined. */ -+/* USB_SETUPIF Predefined. */ -+ -+/* PORT - I/O Port Configuration */ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ -+ -+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -+#define PORT_SPI_bp 5 /* SPI bit position. */ -+ -+#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -+#define PORT_USART0_bp 4 /* USART0 bit position. */ -+ -+#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -+#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ -+ -+#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -+#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ -+ -+#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -+#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ -+ -+#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -+#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ -+ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC0.CTRLA bit masks and bit positions */ -+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC0.CTRLB bit masks and bit positions */ -+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ -+ -+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ -+ -+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC0.CTRLC bit masks and bit positions */ -+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ -+ -+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ -+ -+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC0.CTRLD bit masks and bit positions */ -+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC0_EVACT_gp 5 /* Event Action group position. */ -+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC0.CTRLE bit masks and bit positions */ -+#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC0.INTCTRLA bit masks and bit positions */ -+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC0.INTCTRLB bit masks and bit positions */ -+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ -+ -+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ -+ -+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC0.CTRLFCLR bit masks and bit positions */ -+#define TC0_CMD_gm 0x0C /* Command group mask. */ -+#define TC0_CMD_gp 2 /* Command group position. */ -+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC0_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC0_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC0_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC0.CTRLFSET bit masks and bit positions */ -+/* TC0_CMD Predefined. */ -+/* TC0_CMD Predefined. */ -+ -+/* TC0_LUPD Predefined. */ -+/* TC0_LUPD Predefined. */ -+ -+/* TC0_DIR Predefined. */ -+/* TC0_DIR Predefined. */ -+ -+/* TC0.CTRLGCLR bit masks and bit positions */ -+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ -+ -+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ -+ -+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC0.CTRLGSET bit masks and bit positions */ -+/* TC0_CCDBV Predefined. */ -+/* TC0_CCDBV Predefined. */ -+ -+/* TC0_CCCBV Predefined. */ -+/* TC0_CCCBV Predefined. */ -+ -+/* TC0_CCBBV Predefined. */ -+/* TC0_CCBBV Predefined. */ -+ -+/* TC0_CCABV Predefined. */ -+/* TC0_CCABV Predefined. */ -+ -+/* TC0_PERBV Predefined. */ -+/* TC0_PERBV Predefined. */ -+ -+/* TC0.INTFLAGS bit masks and bit positions */ -+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ -+ -+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ -+ -+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC1.CTRLA bit masks and bit positions */ -+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC1.CTRLB bit masks and bit positions */ -+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC1.CTRLC bit masks and bit positions */ -+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC1.CTRLD bit masks and bit positions */ -+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC1_EVACT_gp 5 /* Event Action group position. */ -+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC1.CTRLE bit masks and bit positions */ -+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ -+ -+/* TC1.INTCTRLA bit masks and bit positions */ -+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC1.INTCTRLB bit masks and bit positions */ -+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC1.CTRLFCLR bit masks and bit positions */ -+#define TC1_CMD_gm 0x0C /* Command group mask. */ -+#define TC1_CMD_gp 2 /* Command group position. */ -+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC1_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC1_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC1_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC1.CTRLFSET bit masks and bit positions */ -+/* TC1_CMD Predefined. */ -+/* TC1_CMD Predefined. */ -+ -+/* TC1_LUPD Predefined. */ -+/* TC1_LUPD Predefined. */ -+ -+/* TC1_DIR Predefined. */ -+/* TC1_DIR Predefined. */ -+ -+/* TC1.CTRLGCLR bit masks and bit positions */ -+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC1.CTRLGSET bit masks and bit positions */ -+/* TC1_CCBBV Predefined. */ -+/* TC1_CCBBV Predefined. */ -+ -+/* TC1_CCABV Predefined. */ -+/* TC1_CCABV Predefined. */ -+ -+/* TC1_PERBV Predefined. */ -+/* TC1_PERBV Predefined. */ -+ -+/* TC1.INTFLAGS bit masks and bit positions */ -+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+/* TC2.CTRLA bit masks and bit positions */ -+#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC2.CTRLB bit masks and bit positions */ -+#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -+#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ -+ -+#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -+#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ -+ -+#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -+#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ -+ -+#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -+#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ -+ -+#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -+#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ -+ -+#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -+#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ -+ -+#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -+#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ -+ -+#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -+#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ -+ -+/* TC2.CTRLC bit masks and bit positions */ -+#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -+#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ -+ -+#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -+#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ -+ -+#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -+#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ -+ -+#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -+#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ -+ -+#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -+#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ -+ -+#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -+#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ -+ -+#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -+#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ -+ -+#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -+#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ -+ -+/* TC2.CTRLE bit masks and bit positions */ -+#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC2.INTCTRLA bit masks and bit positions */ -+#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -+#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -+#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -+#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -+#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -+#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ -+ -+#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -+#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -+#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -+#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -+#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -+#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ -+ -+/* TC2.INTCTRLB bit masks and bit positions */ -+#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -+#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -+#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -+#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -+#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -+#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -+#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -+#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -+#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -+#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -+#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -+#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -+#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -+#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -+#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -+#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -+#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -+#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -+#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -+#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -+#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ -+ -+/* TC2.CTRLF bit masks and bit positions */ -+#define TC2_CMD_gm 0x0C /* Command group mask. */ -+#define TC2_CMD_gp 2 /* Command group position. */ -+#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC2_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -+#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -+#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -+#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -+#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -+#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ -+ -+/* TC2.INTFLAGS bit masks and bit positions */ -+#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -+#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ -+ -+#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -+#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ -+ -+#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -+#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ -+ -+#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -+#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ -+ -+#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ -+ -+#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ -+ -+/* AWEX - Timer/Counter Advanced Waveform Extension */ -+/* AWEX.CTRL bit masks and bit positions */ -+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ -+ -+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ -+ -+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ -+ -+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ -+ -+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ -+ -+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ -+ -+/* AWEX.FDCTRL bit masks and bit positions */ -+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ -+ -+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ -+ -+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ -+ -+/* AWEX.STATUS bit masks and bit positions */ -+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ -+ -+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ -+ -+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ -+ -+/* AWEX.STATUSSET bit masks and bit positions */ -+/* AWEX_FDF Predefined. */ -+/* AWEX_FDF Predefined. */ -+ -+/* AWEX_DTHSBUFV Predefined. */ -+/* AWEX_DTHSBUFV Predefined. */ -+ -+/* AWEX_DTLSBUFV Predefined. */ -+/* AWEX_DTLSBUFV Predefined. */ -+ -+/* HIRES - Timer/Counter High-Resolution Extension */ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -+#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* LOCKBIT - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT0_vect_num 2 -+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -+#define PORTC_INT1_vect_num 3 -+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT0_vect_num 4 -+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -+#define PORTR_INT1_vect_num 5 -+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ -+ -+/* RTC interrupt vectors */ -+#define RTC_OVF_vect_num 10 -+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -+#define RTC_COMP_vect_num 11 -+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 12 -+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 13 -+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_OVF_vect_num 14 -+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LUNF_vect_num 14 -+#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_ERR_vect_num 15 -+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_HUNF_vect_num 15 -+#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCA_vect_num 16 -+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPA_vect_num 16 -+#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCB_vect_num 17 -+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPB_vect_num 17 -+#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCC_vect_num 18 -+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPC_vect_num 18 -+#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCD_vect_num 19 -+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPD_vect_num 19 -+#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ -+ -+/* TCC1 interrupt vectors */ -+#define TCC1_OVF_vect_num 20 -+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -+#define TCC1_ERR_vect_num 21 -+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -+#define TCC1_CCA_vect_num 22 -+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -+#define TCC1_CCB_vect_num 23 -+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 24 -+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 25 -+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 26 -+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 27 -+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 32 -+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -+#define NVM_SPM_vect_num 33 -+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ -+ -+/* PORTB interrupt vectors */ -+#define PORTB_INT0_vect_num 34 -+#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -+#define PORTB_INT1_vect_num 35 -+#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ -+ -+/* PORTE interrupt vectors */ -+#define PORTE_INT0_vect_num 43 -+#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -+#define PORTE_INT1_vect_num 44 -+#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ -+ -+/* TWIE interrupt vectors */ -+#define TWIE_TWIS_vect_num 45 -+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -+#define TWIE_TWIM_vect_num 46 -+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_OVF_vect_num 47 -+#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LUNF_vect_num 47 -+#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_ERR_vect_num 48 -+#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_HUNF_vect_num 48 -+#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCA_vect_num 49 -+#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPA_vect_num 49 -+#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCB_vect_num 50 -+#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPB_vect_num 50 -+#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCC_vect_num 51 -+#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPC_vect_num 51 -+#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCD_vect_num 52 -+#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPD_vect_num 52 -+#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ -+ -+/* USARTE0 interrupt vectors */ -+#define USARTE0_RXC_vect_num 58 -+#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -+#define USARTE0_DRE_vect_num 59 -+#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -+#define USARTE0_TXC_vect_num 60 -+#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT0_vect_num 64 -+#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -+#define PORTD_INT1_vect_num 65 -+#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ -+ -+/* PORTA interrupt vectors */ -+#define PORTA_INT0_vect_num 66 -+#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -+#define PORTA_INT1_vect_num 67 -+#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ -+ -+/* ACA interrupt vectors */ -+#define ACA_AC0_vect_num 68 -+#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -+#define ACA_AC1_vect_num 69 -+#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -+#define ACA_ACW_vect_num 70 -+#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ -+ -+/* ADCA interrupt vectors */ -+#define ADCA_CH0_vect_num 71 -+#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_OVF_vect_num 77 -+#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LUNF_vect_num 77 -+#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_ERR_vect_num 78 -+#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_HUNF_vect_num 78 -+#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCA_vect_num 79 -+#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPA_vect_num 79 -+#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCB_vect_num 80 -+#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPB_vect_num 80 -+#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCC_vect_num 81 -+#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPC_vect_num 81 -+#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCD_vect_num 82 -+#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPD_vect_num 82 -+#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ -+ -+/* SPID interrupt vectors */ -+#define SPID_INT_vect_num 87 -+#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ -+ -+/* USARTD0 interrupt vectors */ -+#define USARTD0_RXC_vect_num 88 -+#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -+#define USARTD0_DRE_vect_num 89 -+#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -+#define USARTD0_TXC_vect_num 90 -+#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ -+ -+/* PORTF interrupt vectors */ -+#define PORTF_INT0_vect_num 104 -+#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -+#define PORTF_INT1_vect_num 105 -+#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_OVF_vect_num 108 -+#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LUNF_vect_num 108 -+#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_ERR_vect_num 109 -+#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_HUNF_vect_num 109 -+#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCA_vect_num 110 -+#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPA_vect_num 110 -+#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCB_vect_num 111 -+#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPB_vect_num 111 -+#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCC_vect_num 112 -+#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPC_vect_num 112 -+#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCD_vect_num 113 -+#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPD_vect_num 113 -+#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ -+ -+/* USB interrupt vectors */ -+#define USB_BUSEVENT_vect_num 125 -+#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -+#define USB_TRNCOMPL_vect_num 126 -+#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (127 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (36864) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (32768) -+#define APP_SECTION_PAGE_SIZE (256) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0x7000) -+#define APPTABLE_SECTION_SIZE (4096) -+#define APPTABLE_SECTION_PAGE_SIZE (256) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x8000) -+#define BOOT_SECTION_SIZE (4096) -+#define BOOT_SECTION_PAGE_SIZE (256) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (12288) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (1024) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (4096) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (1024) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (6) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (256) -+#define USER_SIGNATURES_PAGE_SIZE (256) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (64) -+#define PROD_SIGNATURES_PAGE_SIZE (256) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 256 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 6 -+ -+/* Fuse Byte 0 Reserved */ -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x95 -+#define SIGNATURE_2 0x49 -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA32C3_H_INCLUDED */ -+ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox32c3.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA32C3_H_INCLUDED ++#define _AVR_ATXMEGA32C3_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t USBCTRL; /* USB Control Register */ ++} CLK_t; ++ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t reserved_0x02; ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++/* USB Prescaler Division Factor */ ++typedef enum CLK_USBPSDIV_enum ++{ ++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ ++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ ++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ ++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ ++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ ++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ ++} CLK_USBPSDIV_t; ++ ++/* USB Clock Source */ ++typedef enum CLK_USBSRC_enum ++{ ++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ ++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ ++} CLK_USBSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 2 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC2MCREF_enum ++{ ++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC2MCREF_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++ register8_t reserved_0x05; ++ register8_t EVOUTSEL; /* Event Output Select */ ++} PORTCFG_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP02MAP_enum ++{ ++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP02MAP_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP13MAP_enum ++{ ++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP13MAP_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t reserved_0x07; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++} ADC_t; ++ ++/* Current Limitation */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ ++} ADC_CURRLIMIT_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ ++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ ++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ ++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* SDA Hold Time */ ++typedef enum TWI_SDAHOLD_enum ++{ ++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ ++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ ++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ ++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ ++} TWI_SDAHOLD_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USB - USB ++-------------------------------------------------------------------------- ++*/ ++ ++/* USB Endpoint */ ++typedef struct USB_EP_struct ++{ ++ register8_t STATUS; /* Endpoint Status */ ++ register8_t CTRL; /* Endpoint Control */ ++ _WORDREGISTER(CNT); /* USB Endpoint Counter */ ++ _WORDREGISTER(DATAPTR); /* Data Pointer */ ++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ ++} USB_EP_t; ++ ++ ++/* Universal Serial Bus */ ++typedef struct USB_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t FIFOWP; /* FIFO Write Pointer Register */ ++ register8_t FIFORP; /* FIFO Read Pointer Register */ ++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ ++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ ++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ ++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t reserved_0x20; ++ register8_t reserved_0x21; ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t CAL0; /* Calibration Byte 0 */ ++ register8_t CAL1; /* Calibration Byte 1 */ ++} USB_t; ++ ++ ++/* USB Endpoint Table */ ++typedef struct USB_EP_TABLE_struct ++{ ++ USB_EP_t EP0OUT; /* Endpoint 0 */ ++ USB_EP_t EP0IN; /* Endpoint 0 */ ++ USB_EP_t EP1OUT; /* Endpoint 1 */ ++ USB_EP_t EP1IN; /* Endpoint 1 */ ++ USB_EP_t EP2OUT; /* Endpoint 2 */ ++ USB_EP_t EP2IN; /* Endpoint 2 */ ++ USB_EP_t EP3OUT; /* Endpoint 3 */ ++ USB_EP_t EP3IN; /* Endpoint 3 */ ++ USB_EP_t EP4OUT; /* Endpoint 4 */ ++ USB_EP_t EP4IN; /* Endpoint 4 */ ++ USB_EP_t EP5OUT; /* Endpoint 5 */ ++ USB_EP_t EP5IN; /* Endpoint 5 */ ++ USB_EP_t EP6OUT; /* Endpoint 6 */ ++ USB_EP_t EP6IN; /* Endpoint 6 */ ++ USB_EP_t EP7OUT; /* Endpoint 7 */ ++ USB_EP_t EP7IN; /* Endpoint 7 */ ++ USB_EP_t EP8OUT; /* Endpoint 8 */ ++ USB_EP_t EP8IN; /* Endpoint 8 */ ++ USB_EP_t EP9OUT; /* Endpoint 9 */ ++ USB_EP_t EP9IN; /* Endpoint 9 */ ++ USB_EP_t EP10OUT; /* Endpoint 10 */ ++ USB_EP_t EP10IN; /* Endpoint 10 */ ++ USB_EP_t EP11OUT; /* Endpoint 11 */ ++ USB_EP_t EP11IN; /* Endpoint 11 */ ++ USB_EP_t EP12OUT; /* Endpoint 12 */ ++ USB_EP_t EP12IN; /* Endpoint 12 */ ++ USB_EP_t EP13OUT; /* Endpoint 13 */ ++ USB_EP_t EP13IN; /* Endpoint 13 */ ++ USB_EP_t EP14OUT; /* Endpoint 14 */ ++ USB_EP_t EP14IN; /* Endpoint 14 */ ++ USB_EP_t EP15OUT; /* Endpoint 15 */ ++ USB_EP_t EP15IN; /* Endpoint 15 */ ++ register8_t reserved_0x100; ++ register8_t reserved_0x101; ++ register8_t reserved_0x102; ++ register8_t reserved_0x103; ++ register8_t reserved_0x104; ++ register8_t reserved_0x105; ++ register8_t reserved_0x106; ++ register8_t reserved_0x107; ++ register8_t reserved_0x108; ++ register8_t reserved_0x109; ++ register8_t reserved_0x10A; ++ register8_t reserved_0x10B; ++ register8_t reserved_0x10C; ++ register8_t reserved_0x10D; ++ register8_t reserved_0x10E; ++ register8_t reserved_0x10F; ++ register8_t FRAMENUML; /* Frame Number Low Byte */ ++ register8_t FRAMENUMH; /* Frame Number High Byte */ ++} USB_EP_TABLE_t; ++ ++/* Interrupt level */ ++typedef enum USB_INTLVL_enum ++{ ++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} USB_INTLVL_t; ++ ++/* USB Endpoint Type */ ++typedef enum USB_EP_TYPE_enum ++{ ++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ ++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ ++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ ++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ ++} USB_EP_TYPE_t; ++ ++/* USB Endpoint Buffersize */ ++typedef enum USB_EP_BUFSIZE_enum ++{ ++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ ++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ ++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ ++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ ++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ ++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ ++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ ++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ ++} USB_EP_BUFSIZE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - I/O Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* I/O Port Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Byte Mode */ ++typedef enum TC_BYTEM_enum ++{ ++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ ++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ ++} TC_BYTEM_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC2 - 16-bit Timer/Counter type 2 ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter type 2 */ ++typedef struct TC2_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t reserved_0x03; ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t reserved_0x08; ++ register8_t CTRLF; /* Control Register F */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t LCNT; /* Low Byte Count */ ++ register8_t HCNT; /* High Byte Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t LPER; /* Low Byte Period */ ++ register8_t HPER; /* High Byte Period */ ++ register8_t LCMPA; /* Low Byte Compare A */ ++ register8_t HCMPA; /* High Byte Compare A */ ++ register8_t LCMPB; /* Low Byte Compare B */ ++ register8_t HCMPB; /* High Byte Compare B */ ++ register8_t LCMPC; /* Low Byte Compare C */ ++ register8_t HCMPC; /* High Byte Compare C */ ++ register8_t LCMPD; /* Low Byte Compare D */ ++ register8_t HCMPD; /* High Byte Compare D */ ++} TC2_t; ++ ++/* Clock Selection */ ++typedef enum TC2_CLKSEL_enum ++{ ++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC2_CLKSEL_t; ++ ++/* Byte Mode */ ++typedef enum TC2_BYTEM_enum ++{ ++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ ++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ ++} TC2_BYTEM_t; ++ ++/* High Byte Underflow Interrupt Level */ ++typedef enum TC2_HUNFINTLVL_enum ++{ ++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_HUNFINTLVL_t; ++ ++/* Low Byte Underflow Interrupt Level */ ++typedef enum TC2_LUNFINTLVL_enum ++{ ++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LUNFINTLVL_t; ++ ++/* Low Byte Compare D Interrupt Level */ ++typedef enum TC2_LCMPDINTLVL_enum ++{ ++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC2_LCMPDINTLVL_t; ++ ++/* Low Byte Compare C Interrupt Level */ ++typedef enum TC2_LCMPCINTLVL_enum ++{ ++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC2_LCMPCINTLVL_t; ++ ++/* Low Byte Compare B Interrupt Level */ ++typedef enum TC2_LCMPBINTLVL_enum ++{ ++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_LCMPBINTLVL_t; ++ ++/* Low Byte Compare A Interrupt Level */ ++typedef enum TC2_LCMPAINTLVL_enum ++{ ++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LCMPAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMD_enum ++{ ++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC2_CMD_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMDEN_enum ++{ ++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ ++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ ++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ ++} TC2_CMDEN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AWEX - Timer/Counter Advanced Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - Timer/Counter High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t reserved_0x00; ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* Timer Oscillator pin location */ ++typedef enum TOSCSEL_enum ++{ ++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ ++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ ++} TOSCSEL_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* BOD operation */ ++typedef enum BODACT_enum ++{ ++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BODACT_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WDP_enum ++{ ++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ ++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ ++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ ++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ ++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ ++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ ++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ ++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ ++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ ++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ ++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ ++} WDP_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LOCKBIT - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ ++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t USBCAL0; /* USB Calibration Byte 0 */ ++ register8_t USBCAL1; /* USB Calibration Byte 1 */ ++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ ++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ ++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ ++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ ++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ ++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ ++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ ++#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) ++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) ++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) ++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++#define CLK_USBCTRL _SFR_MEM8(0x0044) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLL - DFLL */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* USB - Universal Serial Bus */ ++#define USB_CTRLA _SFR_MEM8(0x04C0) ++#define USB_CTRLB _SFR_MEM8(0x04C1) ++#define USB_STATUS _SFR_MEM8(0x04C2) ++#define USB_ADDR _SFR_MEM8(0x04C3) ++#define USB_FIFOWP _SFR_MEM8(0x04C4) ++#define USB_FIFORP _SFR_MEM8(0x04C5) ++#define USB_EPPTR _SFR_MEM16(0x04C6) ++#define USB_INTCTRLA _SFR_MEM8(0x04C8) ++#define USB_INTCTRLB _SFR_MEM8(0x04C9) ++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) ++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) ++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) ++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) ++#define USB_CAL0 _SFR_MEM8(0x04FA) ++#define USB_CAL1 _SFR_MEM8(0x04FB) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_REMAP _SFR_MEM8(0x060E) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_REMAP _SFR_MEM8(0x062E) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_REMAP _SFR_MEM8(0x068E) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORT - I/O Ports */ ++#define PORTF_DIR _SFR_MEM8(0x06A0) ++#define PORTF_DIRSET _SFR_MEM8(0x06A1) ++#define PORTF_DIRCLR _SFR_MEM8(0x06A2) ++#define PORTF_DIRTGL _SFR_MEM8(0x06A3) ++#define PORTF_OUT _SFR_MEM8(0x06A4) ++#define PORTF_OUTSET _SFR_MEM8(0x06A5) ++#define PORTF_OUTCLR _SFR_MEM8(0x06A6) ++#define PORTF_OUTTGL _SFR_MEM8(0x06A7) ++#define PORTF_IN _SFR_MEM8(0x06A8) ++#define PORTF_INTCTRL _SFR_MEM8(0x06A9) ++#define PORTF_INT0MASK _SFR_MEM8(0x06AA) ++#define PORTF_INT1MASK _SFR_MEM8(0x06AB) ++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) ++#define PORTF_REMAP _SFR_MEM8(0x06AE) ++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) ++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) ++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) ++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) ++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) ++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) ++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) ++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCC2_CTRLA _SFR_MEM8(0x0800) ++#define TCC2_CTRLB _SFR_MEM8(0x0801) ++#define TCC2_CTRLC _SFR_MEM8(0x0802) ++#define TCC2_CTRLE _SFR_MEM8(0x0804) ++#define TCC2_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC2_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC2_CTRLF _SFR_MEM8(0x0809) ++#define TCC2_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC2_LCNT _SFR_MEM8(0x0820) ++#define TCC2_HCNT _SFR_MEM8(0x0821) ++#define TCC2_LPER _SFR_MEM8(0x0826) ++#define TCC2_HPER _SFR_MEM8(0x0827) ++#define TCC2_LCMPA _SFR_MEM8(0x0828) ++#define TCC2_HCMPA _SFR_MEM8(0x0829) ++#define TCC2_LCMPB _SFR_MEM8(0x082A) ++#define TCC2_HCMPB _SFR_MEM8(0x082B) ++#define TCC2_LCMPC _SFR_MEM8(0x082C) ++#define TCC2_HCMPC _SFR_MEM8(0x082D) ++#define TCC2_LCMPD _SFR_MEM8(0x082E) ++#define TCC2_HCMPD _SFR_MEM8(0x082F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_STATUSSET _SFR_MEM8(0x0885) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCD2_CTRLA _SFR_MEM8(0x0900) ++#define TCD2_CTRLB _SFR_MEM8(0x0901) ++#define TCD2_CTRLC _SFR_MEM8(0x0902) ++#define TCD2_CTRLE _SFR_MEM8(0x0904) ++#define TCD2_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD2_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD2_CTRLF _SFR_MEM8(0x0909) ++#define TCD2_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD2_LCNT _SFR_MEM8(0x0920) ++#define TCD2_HCNT _SFR_MEM8(0x0921) ++#define TCD2_LPER _SFR_MEM8(0x0926) ++#define TCD2_HPER _SFR_MEM8(0x0927) ++#define TCD2_LCMPA _SFR_MEM8(0x0928) ++#define TCD2_HCMPA _SFR_MEM8(0x0929) ++#define TCD2_LCMPB _SFR_MEM8(0x092A) ++#define TCD2_HCMPB _SFR_MEM8(0x092B) ++#define TCD2_LCMPC _SFR_MEM8(0x092C) ++#define TCD2_HCMPC _SFR_MEM8(0x092D) ++#define TCD2_LCMPD _SFR_MEM8(0x092E) ++#define TCD2_HCMPD _SFR_MEM8(0x092F) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCE2_CTRLA _SFR_MEM8(0x0A00) ++#define TCE2_CTRLB _SFR_MEM8(0x0A01) ++#define TCE2_CTRLC _SFR_MEM8(0x0A02) ++#define TCE2_CTRLE _SFR_MEM8(0x0A04) ++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE2_CTRLF _SFR_MEM8(0x0A09) ++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE2_LCNT _SFR_MEM8(0x0A20) ++#define TCE2_HCNT _SFR_MEM8(0x0A21) ++#define TCE2_LPER _SFR_MEM8(0x0A26) ++#define TCE2_HPER _SFR_MEM8(0x0A27) ++#define TCE2_LCMPA _SFR_MEM8(0x0A28) ++#define TCE2_HCMPA _SFR_MEM8(0x0A29) ++#define TCE2_LCMPB _SFR_MEM8(0x0A2A) ++#define TCE2_HCMPB _SFR_MEM8(0x0A2B) ++#define TCE2_LCMPC _SFR_MEM8(0x0A2C) ++#define TCE2_HCMPC _SFR_MEM8(0x0A2D) ++#define TCE2_LCMPD _SFR_MEM8(0x0A2E) ++#define TCE2_HCMPD _SFR_MEM8(0x0A2F) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCF0_CTRLA _SFR_MEM8(0x0B00) ++#define TCF0_CTRLB _SFR_MEM8(0x0B01) ++#define TCF0_CTRLC _SFR_MEM8(0x0B02) ++#define TCF0_CTRLD _SFR_MEM8(0x0B03) ++#define TCF0_CTRLE _SFR_MEM8(0x0B04) ++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) ++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) ++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) ++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) ++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF0_TEMP _SFR_MEM8(0x0B0F) ++#define TCF0_CNT _SFR_MEM16(0x0B20) ++#define TCF0_PER _SFR_MEM16(0x0B26) ++#define TCF0_CCA _SFR_MEM16(0x0B28) ++#define TCF0_CCB _SFR_MEM16(0x0B2A) ++#define TCF0_CCC _SFR_MEM16(0x0B2C) ++#define TCF0_CCD _SFR_MEM16(0x0B2E) ++#define TCF0_PERBUF _SFR_MEM16(0x0B36) ++#define TCF0_CCABUF _SFR_MEM16(0x0B38) ++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) ++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) ++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCF2_CTRLA _SFR_MEM8(0x0B00) ++#define TCF2_CTRLB _SFR_MEM8(0x0B01) ++#define TCF2_CTRLC _SFR_MEM8(0x0B02) ++#define TCF2_CTRLE _SFR_MEM8(0x0B04) ++#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF2_CTRLF _SFR_MEM8(0x0B09) ++#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF2_LCNT _SFR_MEM8(0x0B20) ++#define TCF2_HCNT _SFR_MEM8(0x0B21) ++#define TCF2_LPER _SFR_MEM8(0x0B26) ++#define TCF2_HPER _SFR_MEM8(0x0B27) ++#define TCF2_LCMPA _SFR_MEM8(0x0B28) ++#define TCF2_HCMPA _SFR_MEM8(0x0B29) ++#define TCF2_LCMPB _SFR_MEM8(0x0B2A) ++#define TCF2_HCMPB _SFR_MEM8(0x0B2B) ++#define TCF2_LCMPC _SFR_MEM8(0x0B2C) ++#define TCF2_HCMPC _SFR_MEM8(0x0B2D) ++#define TCF2_LCMPD _SFR_MEM8(0x0B2E) ++#define TCF2_HCMPD _SFR_MEM8(0x0B2F) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* CLK.USBCTRL bit masks and bit positions */ ++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ ++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ ++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ ++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ ++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ ++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ ++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ ++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ ++ ++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ ++#define CLK_USBSRC_gp 1 /* Clock Source group position. */ ++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ ++ ++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_USB_bm 0x40 /* USB bit mask. */ ++#define PR_USB_bp 6 /* USB bit position. */ ++ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ ++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ ++ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ ++ ++/* PORTCFG.EVOUTSEL bit masks and bit positions */ ++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ ++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ ++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ ++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ ++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ ++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ ++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ ++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ ++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ ++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ ++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ ++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ ++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ ++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ ++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ ++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ ++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ ++ ++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ ++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ ++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ ++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ ++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ ++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ ++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ ++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ ++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ ++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ ++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* RTC - Real-Time Counter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* USB - USB */ ++/* USB_EP.STATUS bit masks and bit positions */ ++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ ++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ ++ ++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ ++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ ++ ++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ ++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ ++ ++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ ++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ ++ ++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ ++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ ++ ++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ ++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ ++ ++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ ++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ ++ ++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ ++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ ++ ++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ ++ ++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ ++ ++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ ++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ ++ ++/* USB_EP.CTRL bit masks and bit positions */ ++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ ++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ ++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ ++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ ++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ ++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ ++ ++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ ++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ ++ ++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ ++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ ++ ++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ ++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ ++ ++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ ++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ ++ ++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ ++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ ++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ ++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ ++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ ++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ ++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ ++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ ++ ++/* USB_EP.CNT bit masks and bit positions */ ++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ ++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ ++ ++/* USB.CTRLA bit masks and bit positions */ ++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ ++#define USB_ENABLE_bp 7 /* USB Enable bit position. */ ++ ++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ ++#define USB_SPEED_bp 6 /* Speed Select bit position. */ ++ ++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ ++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ ++ ++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ ++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ ++ ++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ ++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ ++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ ++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ ++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ ++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ ++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ ++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ ++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ ++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ ++ ++/* USB.CTRLB bit masks and bit positions */ ++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ ++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ ++ ++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ ++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ ++ ++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ ++#define USB_GNACK_bp 1 /* Global NACK bit position. */ ++ ++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ ++#define USB_ATTACH_bp 0 /* Attach bit position. */ ++ ++/* USB.STATUS bit masks and bit positions */ ++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ ++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ ++ ++#define USB_RESUME_bm 0x04 /* Resume bit mask. */ ++#define USB_RESUME_bp 2 /* Resume bit position. */ ++ ++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ ++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ ++ ++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ ++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ ++ ++/* USB.ADDR bit masks and bit positions */ ++#define USB_ADDR_gm 0x7F /* Device Address group mask. */ ++#define USB_ADDR_gp 0 /* Device Address group position. */ ++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ ++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ ++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ ++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ ++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ ++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ ++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ ++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ ++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ ++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ ++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ ++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ ++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ ++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ ++ ++/* USB.FIFOWP bit masks and bit positions */ ++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ ++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ ++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ ++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ ++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ ++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ ++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ ++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ ++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ ++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ ++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ ++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ ++ ++/* USB.FIFORP bit masks and bit positions */ ++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ ++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ ++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ ++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ ++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ ++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ ++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ ++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ ++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ ++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ ++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ ++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ ++ ++/* USB.INTCTRLA bit masks and bit positions */ ++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ ++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ ++ ++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ ++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ ++ ++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ ++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ ++ ++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ ++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ ++ ++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* USB.INTCTRLB bit masks and bit positions */ ++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ ++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ ++ ++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ ++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ ++ ++/* USB.INTFLAGSACLR bit masks and bit positions */ ++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ ++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ ++ ++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ ++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ ++ ++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ ++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ ++ ++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ ++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ ++ ++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ ++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ ++ ++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ ++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ ++ ++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ ++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ ++ ++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ ++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSASET bit masks and bit positions */ ++/* USB_SOFIF Predefined. */ ++/* USB_SOFIF Predefined. */ ++ ++/* USB_SUSPENDIF Predefined. */ ++/* USB_SUSPENDIF Predefined. */ ++ ++/* USB_RESUMEIF Predefined. */ ++/* USB_RESUMEIF Predefined. */ ++ ++/* USB_RSTIF Predefined. */ ++/* USB_RSTIF Predefined. */ ++ ++/* USB_CRCIF Predefined. */ ++/* USB_CRCIF Predefined. */ ++ ++/* USB_UNFIF Predefined. */ ++/* USB_UNFIF Predefined. */ ++ ++/* USB_OVFIF Predefined. */ ++/* USB_OVFIF Predefined. */ ++ ++/* USB_STALLIF Predefined. */ ++/* USB_STALLIF Predefined. */ ++ ++/* USB.INTFLAGSBCLR bit masks and bit positions */ ++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ ++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ ++ ++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ ++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSBSET bit masks and bit positions */ ++/* USB_TRNIF Predefined. */ ++/* USB_TRNIF Predefined. */ ++ ++/* USB_SETUPIF Predefined. */ ++/* USB_SETUPIF Predefined. */ ++ ++/* PORT - I/O Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_SPI_bm 0x20 /* SPI bit mask. */ ++#define PORT_SPI_bp 5 /* SPI bit position. */ ++ ++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ ++#define PORT_USART0_bp 4 /* USART0 bit position. */ ++ ++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ ++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ ++ ++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ ++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ ++ ++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ ++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ ++ ++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ ++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD Predefined. */ ++/* TC0_CMD Predefined. */ ++ ++/* TC0_LUPD Predefined. */ ++/* TC0_LUPD Predefined. */ ++ ++/* TC0_DIR Predefined. */ ++/* TC0_DIR Predefined. */ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV Predefined. */ ++/* TC0_CCDBV Predefined. */ ++ ++/* TC0_CCCBV Predefined. */ ++/* TC0_CCCBV Predefined. */ ++ ++/* TC0_CCBBV Predefined. */ ++/* TC0_CCBBV Predefined. */ ++ ++/* TC0_CCABV Predefined. */ ++/* TC0_CCABV Predefined. */ ++ ++/* TC0_PERBV Predefined. */ ++/* TC0_PERBV Predefined. */ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD Predefined. */ ++/* TC1_CMD Predefined. */ ++ ++/* TC1_LUPD Predefined. */ ++/* TC1_LUPD Predefined. */ ++ ++/* TC1_DIR Predefined. */ ++/* TC1_DIR Predefined. */ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV Predefined. */ ++/* TC1_CCBBV Predefined. */ ++ ++/* TC1_CCABV Predefined. */ ++/* TC1_CCABV Predefined. */ ++ ++/* TC1_PERBV Predefined. */ ++/* TC1_PERBV Predefined. */ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++/* TC2.CTRLA bit masks and bit positions */ ++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC2.CTRLB bit masks and bit positions */ ++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ ++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ ++ ++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ ++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ ++ ++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ ++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ ++ ++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ ++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ ++ ++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ ++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ ++ ++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ ++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ ++ ++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ ++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ ++ ++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ ++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ ++ ++/* TC2.CTRLC bit masks and bit positions */ ++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ ++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ ++ ++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ ++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ ++ ++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ ++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ ++ ++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ ++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ ++ ++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ ++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ ++ ++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ ++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ ++ ++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ ++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ ++ ++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ ++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ ++ ++/* TC2.CTRLE bit masks and bit positions */ ++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC2.INTCTRLA bit masks and bit positions */ ++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ ++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ ++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ ++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ ++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ ++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ ++ ++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ ++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ ++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ ++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ ++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ ++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ ++ ++/* TC2.INTCTRLB bit masks and bit positions */ ++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ ++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ ++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ ++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ ++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ ++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ ++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ ++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ ++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ ++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ ++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ ++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ ++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ ++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ ++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ ++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ ++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ ++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ ++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ ++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ ++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ ++ ++/* TC2.CTRLF bit masks and bit positions */ ++#define TC2_CMD_gm 0x0C /* Command group mask. */ ++#define TC2_CMD_gp 2 /* Command group position. */ ++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC2_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC2_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ ++#define TC2_CMDEN_gp 0 /* Command Enable group position. */ ++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ ++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ ++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ ++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ ++ ++/* TC2.INTFLAGS bit masks and bit positions */ ++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ ++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ ++ ++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ ++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ ++ ++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ ++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ ++ ++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ ++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ ++ ++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ ++ ++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ ++ ++/* AWEX - Timer/Counter Advanced Waveform Extension */ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++/* AWEX.STATUSSET bit masks and bit positions */ ++/* AWEX_FDF Predefined. */ ++/* AWEX_FDF Predefined. */ ++ ++/* AWEX_DTHSBUFV Predefined. */ ++/* AWEX_DTHSBUFV Predefined. */ ++ ++/* AWEX_DTLSBUFV Predefined. */ ++/* AWEX_DTLSBUFV Predefined. */ ++ ++/* HIRES - Timer/Counter High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ ++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* LOCKBIT - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LUNF_vect_num 14 ++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_HUNF_vect_num 15 ++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPA_vect_num 16 ++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPB_vect_num 17 ++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPC_vect_num 18 ++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPD_vect_num 19 ++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LUNF_vect_num 47 ++#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_HUNF_vect_num 48 ++#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPA_vect_num 49 ++#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPB_vect_num 50 ++#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPC_vect_num 51 ++#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPD_vect_num 52 ++#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LUNF_vect_num 77 ++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_HUNF_vect_num 78 ++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPA_vect_num 79 ++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPB_vect_num 80 ++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPC_vect_num 81 ++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPD_vect_num 82 ++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* PORTF interrupt vectors */ ++#define PORTF_INT0_vect_num 104 ++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ ++#define PORTF_INT1_vect_num 105 ++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_OVF_vect_num 108 ++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LUNF_vect_num 108 ++#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_ERR_vect_num 109 ++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_HUNF_vect_num 109 ++#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCA_vect_num 110 ++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPA_vect_num 110 ++#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCB_vect_num 111 ++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPB_vect_num 111 ++#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCC_vect_num 112 ++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPC_vect_num 112 ++#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCD_vect_num 113 ++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPD_vect_num 113 ++#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ ++ ++/* USB interrupt vectors */ ++#define USB_BUSEVENT_vect_num 125 ++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ ++#define USB_TRNCOMPL_vect_num 126 ++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (127 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (36864) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (32768) ++#define APP_SECTION_PAGE_SIZE (256) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x7000) ++#define APPTABLE_SECTION_SIZE (4096) ++#define APPTABLE_SECTION_PAGE_SIZE (256) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x8000) ++#define BOOT_SECTION_SIZE (4096) ++#define BOOT_SECTION_PAGE_SIZE (256) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (12288) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (1024) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (4096) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (1024) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (6) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (256) ++#define USER_SIGNATURES_PAGE_SIZE (256) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (64) ++#define PROD_SIGNATURES_PAGE_SIZE (256) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 256 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 Reserved */ ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x49 ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA32C3_H_INCLUDED */ ++ diff --git a/include/avr/iox32c4.h b/include/avr/iox32c4.h new file mode 100644 -index 0000000..1156283 +index 0000000..0f133dd --- /dev/null +++ b/include/avr/iox32c4.h @@ -0,0 +1,6030 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox32c4.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA32C4_H_INCLUDED -+#define _AVR_ATXMEGA32C4_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+VPORT - Virtual Ports -+-------------------------------------------------------------------------- -+*/ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t USBCTRL; /* USB Control Register */ -+} CLK_t; -+ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t reserved_0x02; -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t PRPD; /* Power Reduction Port D */ -+ register8_t PRPE; /* Power Reduction Port E */ -+ register8_t PRPF; /* Power Reduction Port F */ -+} PR_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+/* USB Prescaler Division Factor */ -+typedef enum CLK_USBPSDIV_enum -+{ -+ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ -+ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ -+ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ -+ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ -+ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ -+ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -+} CLK_USBPSDIV_t; -+ -+/* USB Clock Source */ -+typedef enum CLK_USBSRC_enum -+{ -+ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ -+ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -+} CLK_USBSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control Register */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+/* 2 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC2MCREF_enum -+{ -+ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC2MCREF_t; -+ -+/* 32 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC32MCREF_enum -+{ -+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -+} OSC_RC32MCREF_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t ANAINIT; /* Analog Startup Delay */ -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t AWEXLOCK; /* AWEX Lock */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORTCFG - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t VPCTRLA; /* Virtual Port Control Register A */ -+ register8_t VPCTRLB; /* Virtual Port Control Register B */ -+ register8_t CLKEVOUT; /* Clock and Event Out Register */ -+ register8_t reserved_0x05; -+ register8_t EVOUTSEL; /* Event Output Select */ -+} PORTCFG_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP02MAP_enum -+{ -+ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ -+ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ -+ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ -+ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ -+ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ -+ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ -+ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ -+ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ -+ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ -+ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ -+ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ -+ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ -+ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ -+ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ -+ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ -+ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -+} PORTCFG_VP02MAP_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP13MAP_enum -+{ -+ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ -+ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ -+ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ -+ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ -+ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ -+ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ -+ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ -+ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ -+ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ -+ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ -+ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ -+ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ -+ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ -+ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ -+ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ -+ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -+} PORTCFG_VP13MAP_t; -+ -+/* System Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ -+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ -+ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -+} PORTCFG_CLKOUT_t; -+ -+/* Peripheral Clock Output Select */ -+typedef enum PORTCFG_CLKOUTSEL_enum -+{ -+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -+} PORTCFG_CLKOUTSEL_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ -+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ -+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -+} PORTCFG_EVOUT_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+} EVSYS_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ -+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ -+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ -+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ -+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ -+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ -+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ -+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ -+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ -+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ -+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ -+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ -+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ -+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ -+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ -+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ -+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ -+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ -+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ -+ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ -+ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ -+ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ -+ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ -+ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ -+ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ -+ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ -+ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ -+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ -+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ -+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ -+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ -+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ -+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ -+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ -+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ -+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ -+ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ -+ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ -+ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ -+ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ -+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ -+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ -+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ -+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ -+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -+ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ -+ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ -+ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ -+ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ -+ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -+} EVSYS_CHMUX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ -+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ -+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ -+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ -+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} NVM_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t reserved_0x07; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+} ADC_t; -+ -+/* Current Limitation */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -+} ADC_CURRLIMIT_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+} ADC_CH_MUXNEG_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ -+ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ -+ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ -+ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC - Real-Time Counter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Real-Time Counter */ -+typedef struct RTC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary register */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ _WORDREGISTER(CNT); /* Count Register */ -+ _WORDREGISTER(PER); /* Period Register */ -+ _WORDREGISTER(COMP); /* Compare Register */ -+} RTC_t; -+ -+/* Prescaler Factor */ -+typedef enum RTC_PRESCALER_enum -+{ -+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ -+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ -+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ -+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ -+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ -+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ -+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ -+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -+} RTC_PRESCALER_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC_COMPINTLVL_enum -+{ -+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC_OVFINTLVL_enum -+{ -+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+} TWI_t; -+ -+/* SDA Hold Time */ -+typedef enum TWI_SDAHOLD_enum -+{ -+ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ -+ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ -+ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ -+ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -+} TWI_SDAHOLD_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USB - USB -+-------------------------------------------------------------------------- -+*/ -+ -+/* USB Endpoint */ -+typedef struct USB_EP_struct -+{ -+ register8_t STATUS; /* Endpoint Status */ -+ register8_t CTRL; /* Endpoint Control */ -+ _WORDREGISTER(CNT); /* USB Endpoint Counter */ -+ _WORDREGISTER(DATAPTR); /* Data Pointer */ -+ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -+} USB_EP_t; -+ -+ -+/* Universal Serial Bus */ -+typedef struct USB_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t FIFOWP; /* FIFO Write Pointer Register */ -+ register8_t FIFORP; /* FIFO Read Pointer Register */ -+ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ -+ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ -+ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ -+ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t reserved_0x20; -+ register8_t reserved_0x21; -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t CAL0; /* Calibration Byte 0 */ -+ register8_t CAL1; /* Calibration Byte 1 */ -+} USB_t; -+ -+ -+/* USB Endpoint Table */ -+typedef struct USB_EP_TABLE_struct -+{ -+ USB_EP_t EP0OUT; /* Endpoint 0 */ -+ USB_EP_t EP0IN; /* Endpoint 0 */ -+ USB_EP_t EP1OUT; /* Endpoint 1 */ -+ USB_EP_t EP1IN; /* Endpoint 1 */ -+ USB_EP_t EP2OUT; /* Endpoint 2 */ -+ USB_EP_t EP2IN; /* Endpoint 2 */ -+ USB_EP_t EP3OUT; /* Endpoint 3 */ -+ USB_EP_t EP3IN; /* Endpoint 3 */ -+ USB_EP_t EP4OUT; /* Endpoint 4 */ -+ USB_EP_t EP4IN; /* Endpoint 4 */ -+ USB_EP_t EP5OUT; /* Endpoint 5 */ -+ USB_EP_t EP5IN; /* Endpoint 5 */ -+ USB_EP_t EP6OUT; /* Endpoint 6 */ -+ USB_EP_t EP6IN; /* Endpoint 6 */ -+ USB_EP_t EP7OUT; /* Endpoint 7 */ -+ USB_EP_t EP7IN; /* Endpoint 7 */ -+ USB_EP_t EP8OUT; /* Endpoint 8 */ -+ USB_EP_t EP8IN; /* Endpoint 8 */ -+ USB_EP_t EP9OUT; /* Endpoint 9 */ -+ USB_EP_t EP9IN; /* Endpoint 9 */ -+ USB_EP_t EP10OUT; /* Endpoint 10 */ -+ USB_EP_t EP10IN; /* Endpoint 10 */ -+ USB_EP_t EP11OUT; /* Endpoint 11 */ -+ USB_EP_t EP11IN; /* Endpoint 11 */ -+ USB_EP_t EP12OUT; /* Endpoint 12 */ -+ USB_EP_t EP12IN; /* Endpoint 12 */ -+ USB_EP_t EP13OUT; /* Endpoint 13 */ -+ USB_EP_t EP13IN; /* Endpoint 13 */ -+ USB_EP_t EP14OUT; /* Endpoint 14 */ -+ USB_EP_t EP14IN; /* Endpoint 14 */ -+ USB_EP_t EP15OUT; /* Endpoint 15 */ -+ USB_EP_t EP15IN; /* Endpoint 15 */ -+ register8_t reserved_0x100; -+ register8_t reserved_0x101; -+ register8_t reserved_0x102; -+ register8_t reserved_0x103; -+ register8_t reserved_0x104; -+ register8_t reserved_0x105; -+ register8_t reserved_0x106; -+ register8_t reserved_0x107; -+ register8_t reserved_0x108; -+ register8_t reserved_0x109; -+ register8_t reserved_0x10A; -+ register8_t reserved_0x10B; -+ register8_t reserved_0x10C; -+ register8_t reserved_0x10D; -+ register8_t reserved_0x10E; -+ register8_t reserved_0x10F; -+ register8_t FRAMENUML; /* Frame Number Low Byte */ -+ register8_t FRAMENUMH; /* Frame Number High Byte */ -+} USB_EP_TABLE_t; -+ -+/* Interrupt level */ -+typedef enum USB_INTLVL_enum -+{ -+ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} USB_INTLVL_t; -+ -+/* USB Endpoint Type */ -+typedef enum USB_EP_TYPE_enum -+{ -+ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ -+ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ -+ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ -+ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -+} USB_EP_TYPE_t; -+ -+/* USB Endpoint Buffersize */ -+typedef enum USB_EP_BUFSIZE_enum -+{ -+ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ -+ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ -+ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ -+ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ -+ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ -+ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ -+ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ -+ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -+} USB_EP_BUFSIZE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - I/O Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INT0MASK; /* Port Interrupt 0 Mask */ -+ register8_t INT1MASK; /* Port Interrupt 1 Mask */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t REMAP; /* I/O Port Pin Remap Register */ -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Port Interrupt 0 Level */ -+typedef enum PORT_INT0LVL_enum -+{ -+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INT0LVL_t; -+ -+/* Port Interrupt 1 Level */ -+typedef enum PORT_INT1LVL_enum -+{ -+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ -+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ -+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -+} PORT_INT1LVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 0 */ -+typedef struct TC0_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC0_t; -+ -+ -+/* 16-bit Timer/Counter 1 */ -+typedef struct TC1_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+} TC1_t; -+ -+/* Clock Selection */ -+typedef enum TC_CLKSEL_enum -+{ -+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_CLKSEL_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC_WGMODE_enum -+{ -+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC_WGMODE_t; -+ -+/* Byte Mode */ -+typedef enum TC_BYTEM_enum -+{ -+ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ -+ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -+} TC_BYTEM_t; -+ -+/* Event Action */ -+typedef enum TC_EVACT_enum -+{ -+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ -+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ -+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ -+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ -+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ -+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC_EVSEL_enum -+{ -+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_EVSEL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC_ERRINTLVL_enum -+{ -+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC_OVFINTLVL_enum -+{ -+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_OVFINTLVL_t; -+ -+/* Compare or Capture D Interrupt Level */ -+typedef enum TC_CCDINTLVL_enum -+{ -+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC_CCDINTLVL_t; -+ -+/* Compare or Capture C Interrupt Level */ -+typedef enum TC_CCCINTLVL_enum -+{ -+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC_CCCINTLVL_t; -+ -+/* Compare or Capture B Interrupt Level */ -+typedef enum TC_CCBINTLVL_enum -+{ -+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_CCBINTLVL_t; -+ -+/* Compare or Capture A Interrupt Level */ -+typedef enum TC_CCAINTLVL_enum -+{ -+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_CCAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC_CMD_enum -+{ -+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC2 - 16-bit Timer/Counter type 2 -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter type 2 */ -+typedef struct TC2_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t reserved_0x03; -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t reserved_0x08; -+ register8_t CTRLF; /* Control Register F */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t LCNT; /* Low Byte Count */ -+ register8_t HCNT; /* High Byte Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t LPER; /* Low Byte Period */ -+ register8_t HPER; /* High Byte Period */ -+ register8_t LCMPA; /* Low Byte Compare A */ -+ register8_t HCMPA; /* High Byte Compare A */ -+ register8_t LCMPB; /* Low Byte Compare B */ -+ register8_t HCMPB; /* High Byte Compare B */ -+ register8_t LCMPC; /* Low Byte Compare C */ -+ register8_t HCMPC; /* High Byte Compare C */ -+ register8_t LCMPD; /* Low Byte Compare D */ -+ register8_t HCMPD; /* High Byte Compare D */ -+} TC2_t; -+ -+/* Clock Selection */ -+typedef enum TC2_CLKSEL_enum -+{ -+ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC2_CLKSEL_t; -+ -+/* Byte Mode */ -+typedef enum TC2_BYTEM_enum -+{ -+ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ -+ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -+} TC2_BYTEM_t; -+ -+/* High Byte Underflow Interrupt Level */ -+typedef enum TC2_HUNFINTLVL_enum -+{ -+ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_HUNFINTLVL_t; -+ -+/* Low Byte Underflow Interrupt Level */ -+typedef enum TC2_LUNFINTLVL_enum -+{ -+ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LUNFINTLVL_t; -+ -+/* Low Byte Compare D Interrupt Level */ -+typedef enum TC2_LCMPDINTLVL_enum -+{ -+ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC2_LCMPDINTLVL_t; -+ -+/* Low Byte Compare C Interrupt Level */ -+typedef enum TC2_LCMPCINTLVL_enum -+{ -+ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC2_LCMPCINTLVL_t; -+ -+/* Low Byte Compare B Interrupt Level */ -+typedef enum TC2_LCMPBINTLVL_enum -+{ -+ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_LCMPBINTLVL_t; -+ -+/* Low Byte Compare A Interrupt Level */ -+typedef enum TC2_LCMPAINTLVL_enum -+{ -+ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LCMPAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMD_enum -+{ -+ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC2_CMD_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMDEN_enum -+{ -+ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ -+ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ -+ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -+} TC2_CMDEN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AWEX - Timer/Counter Advanced Waveform Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Advanced Waveform Extension */ -+typedef struct AWEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t FDEMASK; /* Fault Detection Event Mask */ -+ register8_t FDCTRL; /* Fault Detection Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t STATUSSET; /* Status Set Register */ -+ register8_t DTBOTH; /* Dead Time Both Sides */ -+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ -+ register8_t DTLS; /* Dead Time Low Side */ -+ register8_t DTHS; /* Dead Time High Side */ -+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ -+ register8_t DTHSBUF; /* Dead Time High Side Buffer */ -+ register8_t OUTOVEN; /* Output Override Enable */ -+} AWEX_t; -+ -+/* Fault Detect Action */ -+typedef enum AWEX_FDACT_enum -+{ -+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ -+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -+} AWEX_FDACT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+HIRES - Timer/Counter High-Resolution Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register */ -+} HIRES_t; -+ -+/* High Resolution Enable */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ -+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+} IRDA_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t reserved_0x00; -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+} NVM_FUSES_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* Timer Oscillator pin location */ -+typedef enum TOSCSEL_enum -+{ -+ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ -+ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -+} TOSCSEL_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -+} BOD_t; -+ -+/* BOD operation */ -+typedef enum BODACT_enum -+{ -+ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BODACT_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WDP_enum -+{ -+ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ -+ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ -+ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ -+ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ -+ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ -+ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ -+ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ -+ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ -+ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ -+ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ -+ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -+} WDP_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LOCKBIT - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ -+ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t USBCAL0; /* USB Calibration Byte 0 */ -+ register8_t USBCAL1; /* USB Calibration Byte 1 */ -+ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ -+ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+} NVM_PROD_SIGNATURES_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -+#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -+#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -+#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -+#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -+#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -+#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -+#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -+#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+#define CLK_USBCTRL _SFR_MEM8(0x0044) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* DFLL - DFLL */ -+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -+#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -+#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPD _SFR_MEM8(0x0074) -+#define PR_PRPE _SFR_MEM8(0x0075) -+#define PR_PRPF _SFR_MEM8(0x0076) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_ANAINIT _SFR_MEM8(0x0097) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_AWEXLOCK _SFR_MEM8(0x0099) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCA_CTRLA _SFR_MEM8(0x0200) -+#define ADCA_CTRLB _SFR_MEM8(0x0201) -+#define ADCA_REFCTRL _SFR_MEM8(0x0202) -+#define ADCA_EVCTRL _SFR_MEM8(0x0203) -+#define ADCA_PRESCALER _SFR_MEM8(0x0204) -+#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -+#define ADCA_TEMP _SFR_MEM8(0x0207) -+#define ADCA_CAL _SFR_MEM16(0x020C) -+#define ADCA_CH0RES _SFR_MEM16(0x0210) -+#define ADCA_CMP _SFR_MEM16(0x0218) -+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -+#define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -+ -+/* AC - Analog Comparator */ -+#define ACA_AC0CTRL _SFR_MEM8(0x0380) -+#define ACA_AC1CTRL _SFR_MEM8(0x0381) -+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -+#define ACA_CTRLA _SFR_MEM8(0x0384) -+#define ACA_CTRLB _SFR_MEM8(0x0385) -+#define ACA_WINCTRL _SFR_MEM8(0x0386) -+#define ACA_STATUS _SFR_MEM8(0x0387) -+ -+/* RTC - Real-Time Counter */ -+#define RTC_CTRL _SFR_MEM8(0x0400) -+#define RTC_STATUS _SFR_MEM8(0x0401) -+#define RTC_INTCTRL _SFR_MEM8(0x0402) -+#define RTC_INTFLAGS _SFR_MEM8(0x0403) -+#define RTC_TEMP _SFR_MEM8(0x0404) -+#define RTC_CNT _SFR_MEM16(0x0408) -+#define RTC_PER _SFR_MEM16(0x040A) -+#define RTC_COMP _SFR_MEM16(0x040C) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIE_CTRL _SFR_MEM8(0x04A0) -+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -+ -+/* USB - Universal Serial Bus */ -+#define USB_CTRLA _SFR_MEM8(0x04C0) -+#define USB_CTRLB _SFR_MEM8(0x04C1) -+#define USB_STATUS _SFR_MEM8(0x04C2) -+#define USB_ADDR _SFR_MEM8(0x04C3) -+#define USB_FIFOWP _SFR_MEM8(0x04C4) -+#define USB_FIFORP _SFR_MEM8(0x04C5) -+#define USB_EPPTR _SFR_MEM16(0x04C6) -+#define USB_INTCTRLA _SFR_MEM8(0x04C8) -+#define USB_INTCTRLB _SFR_MEM8(0x04C9) -+#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -+#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -+#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -+#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -+#define USB_CAL0 _SFR_MEM8(0x04FA) -+#define USB_CAL1 _SFR_MEM8(0x04FB) -+ -+/* PORT - I/O Ports */ -+#define PORTA_DIR _SFR_MEM8(0x0600) -+#define PORTA_DIRSET _SFR_MEM8(0x0601) -+#define PORTA_DIRCLR _SFR_MEM8(0x0602) -+#define PORTA_DIRTGL _SFR_MEM8(0x0603) -+#define PORTA_OUT _SFR_MEM8(0x0604) -+#define PORTA_OUTSET _SFR_MEM8(0x0605) -+#define PORTA_OUTCLR _SFR_MEM8(0x0606) -+#define PORTA_OUTTGL _SFR_MEM8(0x0607) -+#define PORTA_IN _SFR_MEM8(0x0608) -+#define PORTA_INTCTRL _SFR_MEM8(0x0609) -+#define PORTA_INT0MASK _SFR_MEM8(0x060A) -+#define PORTA_INT1MASK _SFR_MEM8(0x060B) -+#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_REMAP _SFR_MEM8(0x060E) -+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -+ -+/* PORT - I/O Ports */ -+#define PORTB_DIR _SFR_MEM8(0x0620) -+#define PORTB_DIRSET _SFR_MEM8(0x0621) -+#define PORTB_DIRCLR _SFR_MEM8(0x0622) -+#define PORTB_DIRTGL _SFR_MEM8(0x0623) -+#define PORTB_OUT _SFR_MEM8(0x0624) -+#define PORTB_OUTSET _SFR_MEM8(0x0625) -+#define PORTB_OUTCLR _SFR_MEM8(0x0626) -+#define PORTB_OUTTGL _SFR_MEM8(0x0627) -+#define PORTB_IN _SFR_MEM8(0x0628) -+#define PORTB_INTCTRL _SFR_MEM8(0x0629) -+#define PORTB_INT0MASK _SFR_MEM8(0x062A) -+#define PORTB_INT1MASK _SFR_MEM8(0x062B) -+#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -+#define PORTB_REMAP _SFR_MEM8(0x062E) -+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INT0MASK _SFR_MEM8(0x064A) -+#define PORTC_INT1MASK _SFR_MEM8(0x064B) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INT0MASK _SFR_MEM8(0x066A) -+#define PORTD_INT1MASK _SFR_MEM8(0x066B) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTE_DIR _SFR_MEM8(0x0680) -+#define PORTE_DIRSET _SFR_MEM8(0x0681) -+#define PORTE_DIRCLR _SFR_MEM8(0x0682) -+#define PORTE_DIRTGL _SFR_MEM8(0x0683) -+#define PORTE_OUT _SFR_MEM8(0x0684) -+#define PORTE_OUTSET _SFR_MEM8(0x0685) -+#define PORTE_OUTCLR _SFR_MEM8(0x0686) -+#define PORTE_OUTTGL _SFR_MEM8(0x0687) -+#define PORTE_IN _SFR_MEM8(0x0688) -+#define PORTE_INTCTRL _SFR_MEM8(0x0689) -+#define PORTE_INT0MASK _SFR_MEM8(0x068A) -+#define PORTE_INT1MASK _SFR_MEM8(0x068B) -+#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -+#define PORTE_REMAP _SFR_MEM8(0x068E) -+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -+#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCC0_CTRLA _SFR_MEM8(0x0800) -+#define TCC0_CTRLB _SFR_MEM8(0x0801) -+#define TCC0_CTRLC _SFR_MEM8(0x0802) -+#define TCC0_CTRLD _SFR_MEM8(0x0803) -+#define TCC0_CTRLE _SFR_MEM8(0x0804) -+#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -+#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -+#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -+#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC0_TEMP _SFR_MEM8(0x080F) -+#define TCC0_CNT _SFR_MEM16(0x0820) -+#define TCC0_PER _SFR_MEM16(0x0826) -+#define TCC0_CCA _SFR_MEM16(0x0828) -+#define TCC0_CCB _SFR_MEM16(0x082A) -+#define TCC0_CCC _SFR_MEM16(0x082C) -+#define TCC0_CCD _SFR_MEM16(0x082E) -+#define TCC0_PERBUF _SFR_MEM16(0x0836) -+#define TCC0_CCABUF _SFR_MEM16(0x0838) -+#define TCC0_CCBBUF _SFR_MEM16(0x083A) -+#define TCC0_CCCBUF _SFR_MEM16(0x083C) -+#define TCC0_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCC2_CTRLA _SFR_MEM8(0x0800) -+#define TCC2_CTRLB _SFR_MEM8(0x0801) -+#define TCC2_CTRLC _SFR_MEM8(0x0802) -+#define TCC2_CTRLE _SFR_MEM8(0x0804) -+#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC2_CTRLF _SFR_MEM8(0x0809) -+#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC2_LCNT _SFR_MEM8(0x0820) -+#define TCC2_HCNT _SFR_MEM8(0x0821) -+#define TCC2_LPER _SFR_MEM8(0x0826) -+#define TCC2_HPER _SFR_MEM8(0x0827) -+#define TCC2_LCMPA _SFR_MEM8(0x0828) -+#define TCC2_HCMPA _SFR_MEM8(0x0829) -+#define TCC2_LCMPB _SFR_MEM8(0x082A) -+#define TCC2_HCMPB _SFR_MEM8(0x082B) -+#define TCC2_LCMPC _SFR_MEM8(0x082C) -+#define TCC2_HCMPC _SFR_MEM8(0x082D) -+#define TCC2_LCMPD _SFR_MEM8(0x082E) -+#define TCC2_HCMPD _SFR_MEM8(0x082F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCC1_CTRLA _SFR_MEM8(0x0840) -+#define TCC1_CTRLB _SFR_MEM8(0x0841) -+#define TCC1_CTRLC _SFR_MEM8(0x0842) -+#define TCC1_CTRLD _SFR_MEM8(0x0843) -+#define TCC1_CTRLE _SFR_MEM8(0x0844) -+#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -+#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -+#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -+#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC1_TEMP _SFR_MEM8(0x084F) -+#define TCC1_CNT _SFR_MEM16(0x0860) -+#define TCC1_PER _SFR_MEM16(0x0866) -+#define TCC1_CCA _SFR_MEM16(0x0868) -+#define TCC1_CCB _SFR_MEM16(0x086A) -+#define TCC1_PERBUF _SFR_MEM16(0x0876) -+#define TCC1_CCABUF _SFR_MEM16(0x0878) -+#define TCC1_CCBBUF _SFR_MEM16(0x087A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXC_CTRL _SFR_MEM8(0x0880) -+#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -+#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -+#define AWEXC_STATUS _SFR_MEM8(0x0884) -+#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -+#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -+#define AWEXC_DTLS _SFR_MEM8(0x0888) -+#define AWEXC_DTHS _SFR_MEM8(0x0889) -+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x0890) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08A0) -+#define USARTC0_STATUS _SFR_MEM8(0x08A1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -+#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -+#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC1_DATA _SFR_MEM8(0x08B0) -+#define USARTC1_STATUS _SFR_MEM8(0x08B1) -+#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -+#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -+#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -+#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -+#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIC_CTRL _SFR_MEM8(0x08C0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -+#define SPIC_STATUS _SFR_MEM8(0x08C2) -+#define SPIC_DATA _SFR_MEM8(0x08C3) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCD0_CTRLA _SFR_MEM8(0x0900) -+#define TCD0_CTRLB _SFR_MEM8(0x0901) -+#define TCD0_CTRLC _SFR_MEM8(0x0902) -+#define TCD0_CTRLD _SFR_MEM8(0x0903) -+#define TCD0_CTRLE _SFR_MEM8(0x0904) -+#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -+#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -+#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -+#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -+#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD0_TEMP _SFR_MEM8(0x090F) -+#define TCD0_CNT _SFR_MEM16(0x0920) -+#define TCD0_PER _SFR_MEM16(0x0926) -+#define TCD0_CCA _SFR_MEM16(0x0928) -+#define TCD0_CCB _SFR_MEM16(0x092A) -+#define TCD0_CCC _SFR_MEM16(0x092C) -+#define TCD0_CCD _SFR_MEM16(0x092E) -+#define TCD0_PERBUF _SFR_MEM16(0x0936) -+#define TCD0_CCABUF _SFR_MEM16(0x0938) -+#define TCD0_CCBBUF _SFR_MEM16(0x093A) -+#define TCD0_CCCBUF _SFR_MEM16(0x093C) -+#define TCD0_CCDBUF _SFR_MEM16(0x093E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCD2_CTRLA _SFR_MEM8(0x0900) -+#define TCD2_CTRLB _SFR_MEM8(0x0901) -+#define TCD2_CTRLC _SFR_MEM8(0x0902) -+#define TCD2_CTRLE _SFR_MEM8(0x0904) -+#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD2_CTRLF _SFR_MEM8(0x0909) -+#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD2_LCNT _SFR_MEM8(0x0920) -+#define TCD2_HCNT _SFR_MEM8(0x0921) -+#define TCD2_LPER _SFR_MEM8(0x0926) -+#define TCD2_HPER _SFR_MEM8(0x0927) -+#define TCD2_LCMPA _SFR_MEM8(0x0928) -+#define TCD2_HCMPA _SFR_MEM8(0x0929) -+#define TCD2_LCMPB _SFR_MEM8(0x092A) -+#define TCD2_HCMPB _SFR_MEM8(0x092B) -+#define TCD2_LCMPC _SFR_MEM8(0x092C) -+#define TCD2_HCMPC _SFR_MEM8(0x092D) -+#define TCD2_LCMPD _SFR_MEM8(0x092E) -+#define TCD2_HCMPD _SFR_MEM8(0x092F) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD0_DATA _SFR_MEM8(0x09A0) -+#define USARTD0_STATUS _SFR_MEM8(0x09A1) -+#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -+#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -+#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPID_CTRL _SFR_MEM8(0x09C0) -+#define SPID_INTCTRL _SFR_MEM8(0x09C1) -+#define SPID_STATUS _SFR_MEM8(0x09C2) -+#define SPID_DATA _SFR_MEM8(0x09C3) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCE0_CTRLA _SFR_MEM8(0x0A00) -+#define TCE0_CTRLB _SFR_MEM8(0x0A01) -+#define TCE0_CTRLC _SFR_MEM8(0x0A02) -+#define TCE0_CTRLD _SFR_MEM8(0x0A03) -+#define TCE0_CTRLE _SFR_MEM8(0x0A04) -+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE0_TEMP _SFR_MEM8(0x0A0F) -+#define TCE0_CNT _SFR_MEM16(0x0A20) -+#define TCE0_PER _SFR_MEM16(0x0A26) -+#define TCE0_CCA _SFR_MEM16(0x0A28) -+#define TCE0_CCB _SFR_MEM16(0x0A2A) -+#define TCE0_CCC _SFR_MEM16(0x0A2C) -+#define TCE0_CCD _SFR_MEM16(0x0A2E) -+#define TCE0_PERBUF _SFR_MEM16(0x0A36) -+#define TCE0_CCABUF _SFR_MEM16(0x0A38) -+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* VPORT - Virtual Ports */ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* CLK.USBCTRL bit masks and bit positions */ -+#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -+#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -+#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -+#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -+#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -+#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -+#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -+#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ -+ -+#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -+#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -+#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ -+ -+#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_USB_bm 0x40 /* USB bit mask. */ -+#define PR_USB_bp 6 /* USB bit position. */ -+ -+#define PR_AES_bm 0x10 /* AES bit mask. */ -+#define PR_AES_bp 4 /* AES bit position. */ -+ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -+#define PR_DMA_bp 0 /* DMA-Controller bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -+#define PR_USART1_bp 5 /* Port C USART1 bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -+#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ -+ -+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -+ -+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ -+ -+/* PR.PRPD bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPE bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPF bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -+#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -+#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ -+ -+#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ -+ -+#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -+#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.ANAINIT bit masks and bit positions */ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.AWEXLOCK bit masks and bit positions */ -+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* PORTCFG - Port Configuration */ -+/* PORTCFG.VPCTRLA bit masks and bit positions */ -+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ -+ -+/* PORTCFG.VPCTRLB bit masks and bit positions */ -+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ -+ -+/* PORTCFG.CLKEVOUT bit masks and bit positions */ -+#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ -+ -+#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -+#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -+#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -+#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -+#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -+#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ -+ -+#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -+#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ -+ -+#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -+#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ -+ -+/* PORTCFG.EVOUTSEL bit masks and bit positions */ -+#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -+#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -+#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -+#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -+#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -+#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -+#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -+#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0x7F /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ -+ -+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ -+ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -+#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -+#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -+#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -+#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -+#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -+#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -+#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -+#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -+#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ -+ -+#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -+#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -+#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -+#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -+#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -+#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -+#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -+#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -+#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -+#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -+#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* RTC - Real-Time Counter */ -+/* RTC.CTRL bit masks and bit positions */ -+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ -+ -+/* RTC.STATUS bit masks and bit positions */ -+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC.INTCTRL bit masks and bit positions */ -+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC.INTFLAGS bit masks and bit positions */ -+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* USB - USB */ -+/* USB_EP.STATUS bit masks and bit positions */ -+#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -+#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ -+ -+#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -+#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ -+ -+#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -+#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ -+ -+#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -+#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ -+ -+#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -+#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ -+ -+#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -+#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ -+ -+#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -+#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ -+ -+#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -+#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ -+ -+#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ -+ -+#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ -+ -+#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -+#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ -+ -+/* USB_EP.CTRL bit masks and bit positions */ -+#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -+#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -+#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -+#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -+#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -+#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ -+ -+#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -+#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ -+ -+#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -+#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ -+ -+#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -+#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ -+ -+#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -+#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ -+ -+#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -+#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -+#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -+#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -+#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -+#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -+#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -+#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ -+ -+/* USB_EP.CNT bit masks and bit positions */ -+#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -+#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ -+ -+/* USB.CTRLA bit masks and bit positions */ -+#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -+#define USB_ENABLE_bp 7 /* USB Enable bit position. */ -+ -+#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -+#define USB_SPEED_bp 6 /* Speed Select bit position. */ -+ -+#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -+#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ -+ -+#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -+#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ -+ -+#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -+#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -+#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -+#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -+#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -+#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -+#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -+#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -+#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -+#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ -+ -+/* USB.CTRLB bit masks and bit positions */ -+#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -+#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ -+ -+#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -+#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ -+ -+#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -+#define USB_GNACK_bp 1 /* Global NACK bit position. */ -+ -+#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -+#define USB_ATTACH_bp 0 /* Attach bit position. */ -+ -+/* USB.STATUS bit masks and bit positions */ -+#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -+#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ -+ -+#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -+#define USB_RESUME_bp 2 /* Resume bit position. */ -+ -+#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -+#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ -+ -+#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -+#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ -+ -+/* USB.ADDR bit masks and bit positions */ -+#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -+#define USB_ADDR_gp 0 /* Device Address group position. */ -+#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -+#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -+#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -+#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -+#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -+#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -+#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -+#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -+#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -+#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -+#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -+#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -+#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -+#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ -+ -+/* USB.FIFOWP bit masks and bit positions */ -+#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -+#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -+#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -+#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -+#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -+#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -+#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -+#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -+#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -+#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -+#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -+#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ -+ -+/* USB.FIFORP bit masks and bit positions */ -+#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -+#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -+#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -+#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -+#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -+#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -+#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -+#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -+#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -+#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -+#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -+#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ -+ -+/* USB.INTCTRLA bit masks and bit positions */ -+#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -+#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ -+ -+#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -+#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ -+ -+#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -+#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ -+ -+#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -+#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ -+ -+#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* USB.INTCTRLB bit masks and bit positions */ -+#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -+#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ -+ -+#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -+#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ -+ -+/* USB.INTFLAGSACLR bit masks and bit positions */ -+#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -+#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ -+ -+#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -+#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ -+ -+#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -+#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ -+ -+#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -+#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ -+ -+#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -+#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ -+ -+#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -+#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ -+ -+#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -+#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ -+ -+#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -+#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSASET bit masks and bit positions */ -+/* USB_SOFIF Predefined. */ -+/* USB_SOFIF Predefined. */ -+ -+/* USB_SUSPENDIF Predefined. */ -+/* USB_SUSPENDIF Predefined. */ -+ -+/* USB_RESUMEIF Predefined. */ -+/* USB_RESUMEIF Predefined. */ -+ -+/* USB_RSTIF Predefined. */ -+/* USB_RSTIF Predefined. */ -+ -+/* USB_CRCIF Predefined. */ -+/* USB_CRCIF Predefined. */ -+ -+/* USB_UNFIF Predefined. */ -+/* USB_UNFIF Predefined. */ -+ -+/* USB_OVFIF Predefined. */ -+/* USB_OVFIF Predefined. */ -+ -+/* USB_STALLIF Predefined. */ -+/* USB_STALLIF Predefined. */ -+ -+/* USB.INTFLAGSBCLR bit masks and bit positions */ -+#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -+#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ -+ -+#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -+#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSBSET bit masks and bit positions */ -+/* USB_TRNIF Predefined. */ -+/* USB_TRNIF Predefined. */ -+ -+/* USB_SETUPIF Predefined. */ -+/* USB_SETUPIF Predefined. */ -+ -+/* PORT - I/O Port Configuration */ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ -+ -+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -+#define PORT_SPI_bp 5 /* SPI bit position. */ -+ -+#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -+#define PORT_USART0_bp 4 /* USART0 bit position. */ -+ -+#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -+#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ -+ -+#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -+#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ -+ -+#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -+#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ -+ -+#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -+#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ -+ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC0.CTRLA bit masks and bit positions */ -+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC0.CTRLB bit masks and bit positions */ -+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ -+ -+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ -+ -+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC0.CTRLC bit masks and bit positions */ -+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ -+ -+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ -+ -+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC0.CTRLD bit masks and bit positions */ -+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC0_EVACT_gp 5 /* Event Action group position. */ -+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC0.CTRLE bit masks and bit positions */ -+#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC0.INTCTRLA bit masks and bit positions */ -+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC0.INTCTRLB bit masks and bit positions */ -+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ -+ -+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ -+ -+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC0.CTRLFCLR bit masks and bit positions */ -+#define TC0_CMD_gm 0x0C /* Command group mask. */ -+#define TC0_CMD_gp 2 /* Command group position. */ -+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC0_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC0_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC0_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC0.CTRLFSET bit masks and bit positions */ -+/* TC0_CMD Predefined. */ -+/* TC0_CMD Predefined. */ -+ -+/* TC0_LUPD Predefined. */ -+/* TC0_LUPD Predefined. */ -+ -+/* TC0_DIR Predefined. */ -+/* TC0_DIR Predefined. */ -+ -+/* TC0.CTRLGCLR bit masks and bit positions */ -+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ -+ -+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ -+ -+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC0.CTRLGSET bit masks and bit positions */ -+/* TC0_CCDBV Predefined. */ -+/* TC0_CCDBV Predefined. */ -+ -+/* TC0_CCCBV Predefined. */ -+/* TC0_CCCBV Predefined. */ -+ -+/* TC0_CCBBV Predefined. */ -+/* TC0_CCBBV Predefined. */ -+ -+/* TC0_CCABV Predefined. */ -+/* TC0_CCABV Predefined. */ -+ -+/* TC0_PERBV Predefined. */ -+/* TC0_PERBV Predefined. */ -+ -+/* TC0.INTFLAGS bit masks and bit positions */ -+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ -+ -+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ -+ -+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC1.CTRLA bit masks and bit positions */ -+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC1.CTRLB bit masks and bit positions */ -+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC1.CTRLC bit masks and bit positions */ -+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC1.CTRLD bit masks and bit positions */ -+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC1_EVACT_gp 5 /* Event Action group position. */ -+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC1.CTRLE bit masks and bit positions */ -+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ -+ -+/* TC1.INTCTRLA bit masks and bit positions */ -+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC1.INTCTRLB bit masks and bit positions */ -+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC1.CTRLFCLR bit masks and bit positions */ -+#define TC1_CMD_gm 0x0C /* Command group mask. */ -+#define TC1_CMD_gp 2 /* Command group position. */ -+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC1_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC1_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC1_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC1.CTRLFSET bit masks and bit positions */ -+/* TC1_CMD Predefined. */ -+/* TC1_CMD Predefined. */ -+ -+/* TC1_LUPD Predefined. */ -+/* TC1_LUPD Predefined. */ -+ -+/* TC1_DIR Predefined. */ -+/* TC1_DIR Predefined. */ -+ -+/* TC1.CTRLGCLR bit masks and bit positions */ -+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC1.CTRLGSET bit masks and bit positions */ -+/* TC1_CCBBV Predefined. */ -+/* TC1_CCBBV Predefined. */ -+ -+/* TC1_CCABV Predefined. */ -+/* TC1_CCABV Predefined. */ -+ -+/* TC1_PERBV Predefined. */ -+/* TC1_PERBV Predefined. */ -+ -+/* TC1.INTFLAGS bit masks and bit positions */ -+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+/* TC2.CTRLA bit masks and bit positions */ -+#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC2.CTRLB bit masks and bit positions */ -+#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -+#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ -+ -+#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -+#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ -+ -+#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -+#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ -+ -+#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -+#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ -+ -+#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -+#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ -+ -+#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -+#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ -+ -+#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -+#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ -+ -+#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -+#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ -+ -+/* TC2.CTRLC bit masks and bit positions */ -+#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -+#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ -+ -+#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -+#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ -+ -+#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -+#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ -+ -+#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -+#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ -+ -+#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -+#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ -+ -+#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -+#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ -+ -+#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -+#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ -+ -+#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -+#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ -+ -+/* TC2.CTRLE bit masks and bit positions */ -+#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC2.INTCTRLA bit masks and bit positions */ -+#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -+#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -+#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -+#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -+#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -+#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ -+ -+#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -+#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -+#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -+#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -+#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -+#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ -+ -+/* TC2.INTCTRLB bit masks and bit positions */ -+#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -+#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -+#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -+#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -+#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -+#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -+#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -+#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -+#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -+#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -+#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -+#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -+#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -+#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -+#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -+#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -+#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -+#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -+#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -+#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -+#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ -+ -+/* TC2.CTRLF bit masks and bit positions */ -+#define TC2_CMD_gm 0x0C /* Command group mask. */ -+#define TC2_CMD_gp 2 /* Command group position. */ -+#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC2_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -+#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -+#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -+#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -+#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -+#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ -+ -+/* TC2.INTFLAGS bit masks and bit positions */ -+#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -+#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ -+ -+#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -+#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ -+ -+#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -+#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ -+ -+#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -+#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ -+ -+#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ -+ -+#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ -+ -+/* AWEX - Timer/Counter Advanced Waveform Extension */ -+/* AWEX.CTRL bit masks and bit positions */ -+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ -+ -+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ -+ -+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ -+ -+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ -+ -+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ -+ -+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ -+ -+/* AWEX.FDCTRL bit masks and bit positions */ -+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ -+ -+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ -+ -+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ -+ -+/* AWEX.STATUS bit masks and bit positions */ -+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ -+ -+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ -+ -+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ -+ -+/* AWEX.STATUSSET bit masks and bit positions */ -+/* AWEX_FDF Predefined. */ -+/* AWEX_FDF Predefined. */ -+ -+/* AWEX_DTHSBUFV Predefined. */ -+/* AWEX_DTHSBUFV Predefined. */ -+ -+/* AWEX_DTLSBUFV Predefined. */ -+/* AWEX_DTLSBUFV Predefined. */ -+ -+/* HIRES - Timer/Counter High-Resolution Extension */ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -+#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* LOCKBIT - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT0_vect_num 2 -+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -+#define PORTC_INT1_vect_num 3 -+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT0_vect_num 4 -+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -+#define PORTR_INT1_vect_num 5 -+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ -+ -+/* RTC interrupt vectors */ -+#define RTC_OVF_vect_num 10 -+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -+#define RTC_COMP_vect_num 11 -+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 12 -+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 13 -+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_OVF_vect_num 14 -+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LUNF_vect_num 14 -+#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_ERR_vect_num 15 -+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_HUNF_vect_num 15 -+#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCA_vect_num 16 -+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPA_vect_num 16 -+#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCB_vect_num 17 -+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPB_vect_num 17 -+#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCC_vect_num 18 -+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPC_vect_num 18 -+#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCD_vect_num 19 -+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPD_vect_num 19 -+#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ -+ -+/* TCC1 interrupt vectors */ -+#define TCC1_OVF_vect_num 20 -+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -+#define TCC1_ERR_vect_num 21 -+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -+#define TCC1_CCA_vect_num 22 -+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -+#define TCC1_CCB_vect_num 23 -+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 24 -+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 25 -+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 26 -+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 27 -+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ -+ -+/* USARTC1 interrupt vectors */ -+#define USARTC1_RXC_vect_num 28 -+#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -+#define USARTC1_DRE_vect_num 29 -+#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -+#define USARTC1_TXC_vect_num 30 -+#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 32 -+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -+#define NVM_SPM_vect_num 33 -+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ -+ -+/* PORTB interrupt vectors */ -+#define PORTB_INT0_vect_num 34 -+#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -+#define PORTB_INT1_vect_num 35 -+#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ -+ -+/* PORTE interrupt vectors */ -+#define PORTE_INT0_vect_num 43 -+#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -+#define PORTE_INT1_vect_num 44 -+#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ -+ -+/* TWIE interrupt vectors */ -+#define TWIE_TWIS_vect_num 45 -+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -+#define TWIE_TWIM_vect_num 46 -+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_OVF_vect_num 47 -+#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -+#define TCE0_ERR_vect_num 48 -+#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -+#define TCE0_CCA_vect_num 49 -+#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -+#define TCE0_CCB_vect_num 50 -+#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -+#define TCE0_CCC_vect_num 51 -+#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -+#define TCE0_CCD_vect_num 52 -+#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT0_vect_num 64 -+#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -+#define PORTD_INT1_vect_num 65 -+#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ -+ -+/* PORTA interrupt vectors */ -+#define PORTA_INT0_vect_num 66 -+#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -+#define PORTA_INT1_vect_num 67 -+#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ -+ -+/* ACA interrupt vectors */ -+#define ACA_AC0_vect_num 68 -+#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -+#define ACA_AC1_vect_num 69 -+#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -+#define ACA_ACW_vect_num 70 -+#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ -+ -+/* ADCA interrupt vectors */ -+#define ADCA_CH0_vect_num 71 -+#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_OVF_vect_num 77 -+#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LUNF_vect_num 77 -+#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_ERR_vect_num 78 -+#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_HUNF_vect_num 78 -+#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCA_vect_num 79 -+#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPA_vect_num 79 -+#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCB_vect_num 80 -+#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPB_vect_num 80 -+#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCC_vect_num 81 -+#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPC_vect_num 81 -+#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCD_vect_num 82 -+#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPD_vect_num 82 -+#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ -+ -+/* SPID interrupt vectors */ -+#define SPID_INT_vect_num 87 -+#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ -+ -+/* USARTD0 interrupt vectors */ -+#define USARTD0_RXC_vect_num 88 -+#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -+#define USARTD0_DRE_vect_num 89 -+#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -+#define USARTD0_TXC_vect_num 90 -+#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ -+ -+/* USB interrupt vectors */ -+#define USB_BUSEVENT_vect_num 125 -+#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -+#define USB_TRNCOMPL_vect_num 126 -+#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (127 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (36864) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (32768) -+#define APP_SECTION_PAGE_SIZE (256) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0x7000) -+#define APPTABLE_SECTION_SIZE (4096) -+#define APPTABLE_SECTION_PAGE_SIZE (256) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x8000) -+#define BOOT_SECTION_SIZE (4096) -+#define BOOT_SECTION_PAGE_SIZE (256) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (12288) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (1024) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (4096) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (1024) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (6) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (256) -+#define USER_SIGNATURES_PAGE_SIZE (256) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (64) -+#define PROD_SIGNATURES_PAGE_SIZE (256) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 256 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 6 -+ -+/* Fuse Byte 0 Reserved */ -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x95 -+#define SIGNATURE_2 0x44 -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA32C4_H_INCLUDED */ -+ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox32c4.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA32C4_H_INCLUDED ++#define _AVR_ATXMEGA32C4_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t USBCTRL; /* USB Control Register */ ++} CLK_t; ++ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t reserved_0x02; ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++/* USB Prescaler Division Factor */ ++typedef enum CLK_USBPSDIV_enum ++{ ++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ ++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ ++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ ++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ ++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ ++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ ++} CLK_USBPSDIV_t; ++ ++/* USB Clock Source */ ++typedef enum CLK_USBSRC_enum ++{ ++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ ++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ ++} CLK_USBSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 2 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC2MCREF_enum ++{ ++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC2MCREF_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++ register8_t reserved_0x05; ++ register8_t EVOUTSEL; /* Event Output Select */ ++} PORTCFG_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP02MAP_enum ++{ ++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP02MAP_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP13MAP_enum ++{ ++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP13MAP_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t reserved_0x07; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++} ADC_t; ++ ++/* Current Limitation */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ ++} ADC_CURRLIMIT_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ ++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ ++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ ++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* SDA Hold Time */ ++typedef enum TWI_SDAHOLD_enum ++{ ++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ ++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ ++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ ++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ ++} TWI_SDAHOLD_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USB - USB ++-------------------------------------------------------------------------- ++*/ ++ ++/* USB Endpoint */ ++typedef struct USB_EP_struct ++{ ++ register8_t STATUS; /* Endpoint Status */ ++ register8_t CTRL; /* Endpoint Control */ ++ _WORDREGISTER(CNT); /* USB Endpoint Counter */ ++ _WORDREGISTER(DATAPTR); /* Data Pointer */ ++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ ++} USB_EP_t; ++ ++ ++/* Universal Serial Bus */ ++typedef struct USB_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t FIFOWP; /* FIFO Write Pointer Register */ ++ register8_t FIFORP; /* FIFO Read Pointer Register */ ++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ ++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ ++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ ++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t reserved_0x20; ++ register8_t reserved_0x21; ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t CAL0; /* Calibration Byte 0 */ ++ register8_t CAL1; /* Calibration Byte 1 */ ++} USB_t; ++ ++ ++/* USB Endpoint Table */ ++typedef struct USB_EP_TABLE_struct ++{ ++ USB_EP_t EP0OUT; /* Endpoint 0 */ ++ USB_EP_t EP0IN; /* Endpoint 0 */ ++ USB_EP_t EP1OUT; /* Endpoint 1 */ ++ USB_EP_t EP1IN; /* Endpoint 1 */ ++ USB_EP_t EP2OUT; /* Endpoint 2 */ ++ USB_EP_t EP2IN; /* Endpoint 2 */ ++ USB_EP_t EP3OUT; /* Endpoint 3 */ ++ USB_EP_t EP3IN; /* Endpoint 3 */ ++ USB_EP_t EP4OUT; /* Endpoint 4 */ ++ USB_EP_t EP4IN; /* Endpoint 4 */ ++ USB_EP_t EP5OUT; /* Endpoint 5 */ ++ USB_EP_t EP5IN; /* Endpoint 5 */ ++ USB_EP_t EP6OUT; /* Endpoint 6 */ ++ USB_EP_t EP6IN; /* Endpoint 6 */ ++ USB_EP_t EP7OUT; /* Endpoint 7 */ ++ USB_EP_t EP7IN; /* Endpoint 7 */ ++ USB_EP_t EP8OUT; /* Endpoint 8 */ ++ USB_EP_t EP8IN; /* Endpoint 8 */ ++ USB_EP_t EP9OUT; /* Endpoint 9 */ ++ USB_EP_t EP9IN; /* Endpoint 9 */ ++ USB_EP_t EP10OUT; /* Endpoint 10 */ ++ USB_EP_t EP10IN; /* Endpoint 10 */ ++ USB_EP_t EP11OUT; /* Endpoint 11 */ ++ USB_EP_t EP11IN; /* Endpoint 11 */ ++ USB_EP_t EP12OUT; /* Endpoint 12 */ ++ USB_EP_t EP12IN; /* Endpoint 12 */ ++ USB_EP_t EP13OUT; /* Endpoint 13 */ ++ USB_EP_t EP13IN; /* Endpoint 13 */ ++ USB_EP_t EP14OUT; /* Endpoint 14 */ ++ USB_EP_t EP14IN; /* Endpoint 14 */ ++ USB_EP_t EP15OUT; /* Endpoint 15 */ ++ USB_EP_t EP15IN; /* Endpoint 15 */ ++ register8_t reserved_0x100; ++ register8_t reserved_0x101; ++ register8_t reserved_0x102; ++ register8_t reserved_0x103; ++ register8_t reserved_0x104; ++ register8_t reserved_0x105; ++ register8_t reserved_0x106; ++ register8_t reserved_0x107; ++ register8_t reserved_0x108; ++ register8_t reserved_0x109; ++ register8_t reserved_0x10A; ++ register8_t reserved_0x10B; ++ register8_t reserved_0x10C; ++ register8_t reserved_0x10D; ++ register8_t reserved_0x10E; ++ register8_t reserved_0x10F; ++ register8_t FRAMENUML; /* Frame Number Low Byte */ ++ register8_t FRAMENUMH; /* Frame Number High Byte */ ++} USB_EP_TABLE_t; ++ ++/* Interrupt level */ ++typedef enum USB_INTLVL_enum ++{ ++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} USB_INTLVL_t; ++ ++/* USB Endpoint Type */ ++typedef enum USB_EP_TYPE_enum ++{ ++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ ++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ ++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ ++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ ++} USB_EP_TYPE_t; ++ ++/* USB Endpoint Buffersize */ ++typedef enum USB_EP_BUFSIZE_enum ++{ ++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ ++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ ++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ ++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ ++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ ++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ ++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ ++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ ++} USB_EP_BUFSIZE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - I/O Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* I/O Port Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Byte Mode */ ++typedef enum TC_BYTEM_enum ++{ ++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ ++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ ++} TC_BYTEM_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC2 - 16-bit Timer/Counter type 2 ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter type 2 */ ++typedef struct TC2_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t reserved_0x03; ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t reserved_0x08; ++ register8_t CTRLF; /* Control Register F */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t LCNT; /* Low Byte Count */ ++ register8_t HCNT; /* High Byte Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t LPER; /* Low Byte Period */ ++ register8_t HPER; /* High Byte Period */ ++ register8_t LCMPA; /* Low Byte Compare A */ ++ register8_t HCMPA; /* High Byte Compare A */ ++ register8_t LCMPB; /* Low Byte Compare B */ ++ register8_t HCMPB; /* High Byte Compare B */ ++ register8_t LCMPC; /* Low Byte Compare C */ ++ register8_t HCMPC; /* High Byte Compare C */ ++ register8_t LCMPD; /* Low Byte Compare D */ ++ register8_t HCMPD; /* High Byte Compare D */ ++} TC2_t; ++ ++/* Clock Selection */ ++typedef enum TC2_CLKSEL_enum ++{ ++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC2_CLKSEL_t; ++ ++/* Byte Mode */ ++typedef enum TC2_BYTEM_enum ++{ ++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ ++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ ++} TC2_BYTEM_t; ++ ++/* High Byte Underflow Interrupt Level */ ++typedef enum TC2_HUNFINTLVL_enum ++{ ++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_HUNFINTLVL_t; ++ ++/* Low Byte Underflow Interrupt Level */ ++typedef enum TC2_LUNFINTLVL_enum ++{ ++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LUNFINTLVL_t; ++ ++/* Low Byte Compare D Interrupt Level */ ++typedef enum TC2_LCMPDINTLVL_enum ++{ ++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC2_LCMPDINTLVL_t; ++ ++/* Low Byte Compare C Interrupt Level */ ++typedef enum TC2_LCMPCINTLVL_enum ++{ ++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC2_LCMPCINTLVL_t; ++ ++/* Low Byte Compare B Interrupt Level */ ++typedef enum TC2_LCMPBINTLVL_enum ++{ ++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_LCMPBINTLVL_t; ++ ++/* Low Byte Compare A Interrupt Level */ ++typedef enum TC2_LCMPAINTLVL_enum ++{ ++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LCMPAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMD_enum ++{ ++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC2_CMD_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMDEN_enum ++{ ++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ ++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ ++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ ++} TC2_CMDEN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AWEX - Timer/Counter Advanced Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - Timer/Counter High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t reserved_0x00; ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* Timer Oscillator pin location */ ++typedef enum TOSCSEL_enum ++{ ++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ ++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ ++} TOSCSEL_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* BOD operation */ ++typedef enum BODACT_enum ++{ ++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BODACT_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WDP_enum ++{ ++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ ++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ ++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ ++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ ++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ ++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ ++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ ++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ ++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ ++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ ++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ ++} WDP_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LOCKBIT - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ ++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t USBCAL0; /* USB Calibration Byte 0 */ ++ register8_t USBCAL1; /* USB Calibration Byte 1 */ ++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ ++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ ++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ ++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ ++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) ++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) ++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) ++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++#define CLK_USBCTRL _SFR_MEM8(0x0044) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLL - DFLL */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* USB - Universal Serial Bus */ ++#define USB_CTRLA _SFR_MEM8(0x04C0) ++#define USB_CTRLB _SFR_MEM8(0x04C1) ++#define USB_STATUS _SFR_MEM8(0x04C2) ++#define USB_ADDR _SFR_MEM8(0x04C3) ++#define USB_FIFOWP _SFR_MEM8(0x04C4) ++#define USB_FIFORP _SFR_MEM8(0x04C5) ++#define USB_EPPTR _SFR_MEM16(0x04C6) ++#define USB_INTCTRLA _SFR_MEM8(0x04C8) ++#define USB_INTCTRLB _SFR_MEM8(0x04C9) ++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) ++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) ++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) ++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) ++#define USB_CAL0 _SFR_MEM8(0x04FA) ++#define USB_CAL1 _SFR_MEM8(0x04FB) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_REMAP _SFR_MEM8(0x060E) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_REMAP _SFR_MEM8(0x062E) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_REMAP _SFR_MEM8(0x068E) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCC2_CTRLA _SFR_MEM8(0x0800) ++#define TCC2_CTRLB _SFR_MEM8(0x0801) ++#define TCC2_CTRLC _SFR_MEM8(0x0802) ++#define TCC2_CTRLE _SFR_MEM8(0x0804) ++#define TCC2_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC2_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC2_CTRLF _SFR_MEM8(0x0809) ++#define TCC2_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC2_LCNT _SFR_MEM8(0x0820) ++#define TCC2_HCNT _SFR_MEM8(0x0821) ++#define TCC2_LPER _SFR_MEM8(0x0826) ++#define TCC2_HPER _SFR_MEM8(0x0827) ++#define TCC2_LCMPA _SFR_MEM8(0x0828) ++#define TCC2_HCMPA _SFR_MEM8(0x0829) ++#define TCC2_LCMPB _SFR_MEM8(0x082A) ++#define TCC2_HCMPB _SFR_MEM8(0x082B) ++#define TCC2_LCMPC _SFR_MEM8(0x082C) ++#define TCC2_HCMPC _SFR_MEM8(0x082D) ++#define TCC2_LCMPD _SFR_MEM8(0x082E) ++#define TCC2_HCMPD _SFR_MEM8(0x082F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_STATUSSET _SFR_MEM8(0x0885) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1_DATA _SFR_MEM8(0x08B0) ++#define USARTC1_STATUS _SFR_MEM8(0x08B1) ++#define USARTC1_CTRLA _SFR_MEM8(0x08B3) ++#define USARTC1_CTRLB _SFR_MEM8(0x08B4) ++#define USARTC1_CTRLC _SFR_MEM8(0x08B5) ++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) ++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCD2_CTRLA _SFR_MEM8(0x0900) ++#define TCD2_CTRLB _SFR_MEM8(0x0901) ++#define TCD2_CTRLC _SFR_MEM8(0x0902) ++#define TCD2_CTRLE _SFR_MEM8(0x0904) ++#define TCD2_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD2_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD2_CTRLF _SFR_MEM8(0x0909) ++#define TCD2_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD2_LCNT _SFR_MEM8(0x0920) ++#define TCD2_HCNT _SFR_MEM8(0x0921) ++#define TCD2_LPER _SFR_MEM8(0x0926) ++#define TCD2_HPER _SFR_MEM8(0x0927) ++#define TCD2_LCMPA _SFR_MEM8(0x0928) ++#define TCD2_HCMPA _SFR_MEM8(0x0929) ++#define TCD2_LCMPB _SFR_MEM8(0x092A) ++#define TCD2_HCMPB _SFR_MEM8(0x092B) ++#define TCD2_LCMPC _SFR_MEM8(0x092C) ++#define TCD2_HCMPC _SFR_MEM8(0x092D) ++#define TCD2_LCMPD _SFR_MEM8(0x092E) ++#define TCD2_HCMPD _SFR_MEM8(0x092F) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* CLK.USBCTRL bit masks and bit positions */ ++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ ++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ ++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ ++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ ++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ ++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ ++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ ++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ ++ ++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ ++#define CLK_USBSRC_gp 1 /* Clock Source group position. */ ++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ ++ ++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_USB_bm 0x40 /* USB bit mask. */ ++#define PR_USB_bp 6 /* USB bit position. */ ++ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ ++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ ++ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ ++ ++/* PORTCFG.EVOUTSEL bit masks and bit positions */ ++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ ++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ ++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ ++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ ++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ ++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ ++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ ++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ ++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ ++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ ++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ ++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ ++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ ++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ ++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ ++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ ++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ ++ ++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ ++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ ++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ ++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ ++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ ++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ ++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ ++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ ++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ ++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ ++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* RTC - Real-Time Counter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* USB - USB */ ++/* USB_EP.STATUS bit masks and bit positions */ ++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ ++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ ++ ++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ ++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ ++ ++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ ++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ ++ ++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ ++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ ++ ++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ ++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ ++ ++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ ++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ ++ ++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ ++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ ++ ++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ ++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ ++ ++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ ++ ++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ ++ ++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ ++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ ++ ++/* USB_EP.CTRL bit masks and bit positions */ ++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ ++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ ++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ ++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ ++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ ++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ ++ ++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ ++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ ++ ++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ ++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ ++ ++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ ++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ ++ ++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ ++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ ++ ++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ ++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ ++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ ++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ ++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ ++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ ++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ ++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ ++ ++/* USB_EP.CNT bit masks and bit positions */ ++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ ++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ ++ ++/* USB.CTRLA bit masks and bit positions */ ++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ ++#define USB_ENABLE_bp 7 /* USB Enable bit position. */ ++ ++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ ++#define USB_SPEED_bp 6 /* Speed Select bit position. */ ++ ++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ ++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ ++ ++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ ++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ ++ ++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ ++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ ++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ ++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ ++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ ++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ ++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ ++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ ++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ ++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ ++ ++/* USB.CTRLB bit masks and bit positions */ ++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ ++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ ++ ++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ ++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ ++ ++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ ++#define USB_GNACK_bp 1 /* Global NACK bit position. */ ++ ++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ ++#define USB_ATTACH_bp 0 /* Attach bit position. */ ++ ++/* USB.STATUS bit masks and bit positions */ ++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ ++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ ++ ++#define USB_RESUME_bm 0x04 /* Resume bit mask. */ ++#define USB_RESUME_bp 2 /* Resume bit position. */ ++ ++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ ++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ ++ ++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ ++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ ++ ++/* USB.ADDR bit masks and bit positions */ ++#define USB_ADDR_gm 0x7F /* Device Address group mask. */ ++#define USB_ADDR_gp 0 /* Device Address group position. */ ++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ ++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ ++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ ++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ ++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ ++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ ++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ ++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ ++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ ++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ ++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ ++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ ++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ ++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ ++ ++/* USB.FIFOWP bit masks and bit positions */ ++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ ++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ ++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ ++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ ++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ ++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ ++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ ++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ ++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ ++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ ++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ ++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ ++ ++/* USB.FIFORP bit masks and bit positions */ ++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ ++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ ++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ ++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ ++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ ++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ ++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ ++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ ++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ ++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ ++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ ++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ ++ ++/* USB.INTCTRLA bit masks and bit positions */ ++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ ++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ ++ ++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ ++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ ++ ++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ ++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ ++ ++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ ++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ ++ ++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* USB.INTCTRLB bit masks and bit positions */ ++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ ++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ ++ ++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ ++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ ++ ++/* USB.INTFLAGSACLR bit masks and bit positions */ ++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ ++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ ++ ++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ ++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ ++ ++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ ++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ ++ ++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ ++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ ++ ++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ ++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ ++ ++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ ++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ ++ ++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ ++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ ++ ++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ ++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSASET bit masks and bit positions */ ++/* USB_SOFIF Predefined. */ ++/* USB_SOFIF Predefined. */ ++ ++/* USB_SUSPENDIF Predefined. */ ++/* USB_SUSPENDIF Predefined. */ ++ ++/* USB_RESUMEIF Predefined. */ ++/* USB_RESUMEIF Predefined. */ ++ ++/* USB_RSTIF Predefined. */ ++/* USB_RSTIF Predefined. */ ++ ++/* USB_CRCIF Predefined. */ ++/* USB_CRCIF Predefined. */ ++ ++/* USB_UNFIF Predefined. */ ++/* USB_UNFIF Predefined. */ ++ ++/* USB_OVFIF Predefined. */ ++/* USB_OVFIF Predefined. */ ++ ++/* USB_STALLIF Predefined. */ ++/* USB_STALLIF Predefined. */ ++ ++/* USB.INTFLAGSBCLR bit masks and bit positions */ ++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ ++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ ++ ++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ ++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSBSET bit masks and bit positions */ ++/* USB_TRNIF Predefined. */ ++/* USB_TRNIF Predefined. */ ++ ++/* USB_SETUPIF Predefined. */ ++/* USB_SETUPIF Predefined. */ ++ ++/* PORT - I/O Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_SPI_bm 0x20 /* SPI bit mask. */ ++#define PORT_SPI_bp 5 /* SPI bit position. */ ++ ++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ ++#define PORT_USART0_bp 4 /* USART0 bit position. */ ++ ++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ ++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ ++ ++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ ++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ ++ ++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ ++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ ++ ++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ ++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD Predefined. */ ++/* TC0_CMD Predefined. */ ++ ++/* TC0_LUPD Predefined. */ ++/* TC0_LUPD Predefined. */ ++ ++/* TC0_DIR Predefined. */ ++/* TC0_DIR Predefined. */ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV Predefined. */ ++/* TC0_CCDBV Predefined. */ ++ ++/* TC0_CCCBV Predefined. */ ++/* TC0_CCCBV Predefined. */ ++ ++/* TC0_CCBBV Predefined. */ ++/* TC0_CCBBV Predefined. */ ++ ++/* TC0_CCABV Predefined. */ ++/* TC0_CCABV Predefined. */ ++ ++/* TC0_PERBV Predefined. */ ++/* TC0_PERBV Predefined. */ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD Predefined. */ ++/* TC1_CMD Predefined. */ ++ ++/* TC1_LUPD Predefined. */ ++/* TC1_LUPD Predefined. */ ++ ++/* TC1_DIR Predefined. */ ++/* TC1_DIR Predefined. */ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV Predefined. */ ++/* TC1_CCBBV Predefined. */ ++ ++/* TC1_CCABV Predefined. */ ++/* TC1_CCABV Predefined. */ ++ ++/* TC1_PERBV Predefined. */ ++/* TC1_PERBV Predefined. */ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++/* TC2.CTRLA bit masks and bit positions */ ++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC2.CTRLB bit masks and bit positions */ ++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ ++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ ++ ++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ ++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ ++ ++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ ++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ ++ ++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ ++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ ++ ++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ ++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ ++ ++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ ++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ ++ ++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ ++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ ++ ++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ ++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ ++ ++/* TC2.CTRLC bit masks and bit positions */ ++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ ++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ ++ ++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ ++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ ++ ++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ ++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ ++ ++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ ++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ ++ ++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ ++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ ++ ++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ ++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ ++ ++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ ++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ ++ ++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ ++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ ++ ++/* TC2.CTRLE bit masks and bit positions */ ++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC2.INTCTRLA bit masks and bit positions */ ++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ ++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ ++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ ++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ ++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ ++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ ++ ++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ ++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ ++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ ++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ ++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ ++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ ++ ++/* TC2.INTCTRLB bit masks and bit positions */ ++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ ++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ ++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ ++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ ++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ ++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ ++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ ++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ ++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ ++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ ++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ ++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ ++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ ++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ ++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ ++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ ++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ ++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ ++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ ++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ ++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ ++ ++/* TC2.CTRLF bit masks and bit positions */ ++#define TC2_CMD_gm 0x0C /* Command group mask. */ ++#define TC2_CMD_gp 2 /* Command group position. */ ++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC2_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC2_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ ++#define TC2_CMDEN_gp 0 /* Command Enable group position. */ ++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ ++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ ++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ ++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ ++ ++/* TC2.INTFLAGS bit masks and bit positions */ ++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ ++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ ++ ++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ ++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ ++ ++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ ++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ ++ ++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ ++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ ++ ++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ ++ ++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ ++ ++/* AWEX - Timer/Counter Advanced Waveform Extension */ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++/* AWEX.STATUSSET bit masks and bit positions */ ++/* AWEX_FDF Predefined. */ ++/* AWEX_FDF Predefined. */ ++ ++/* AWEX_DTHSBUFV Predefined. */ ++/* AWEX_DTHSBUFV Predefined. */ ++ ++/* AWEX_DTLSBUFV Predefined. */ ++/* AWEX_DTLSBUFV Predefined. */ ++ ++/* HIRES - Timer/Counter High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ ++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* LOCKBIT - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LUNF_vect_num 14 ++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_HUNF_vect_num 15 ++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPA_vect_num 16 ++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPB_vect_num 17 ++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPC_vect_num 18 ++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPD_vect_num 19 ++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* USARTC1 interrupt vectors */ ++#define USARTC1_RXC_vect_num 28 ++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ ++#define USARTC1_DRE_vect_num 29 ++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ ++#define USARTC1_TXC_vect_num 30 ++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LUNF_vect_num 77 ++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_HUNF_vect_num 78 ++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPA_vect_num 79 ++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPB_vect_num 80 ++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPC_vect_num 81 ++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPD_vect_num 82 ++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* USB interrupt vectors */ ++#define USB_BUSEVENT_vect_num 125 ++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ ++#define USB_TRNCOMPL_vect_num 126 ++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (127 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (36864) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (32768) ++#define APP_SECTION_PAGE_SIZE (256) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x7000) ++#define APPTABLE_SECTION_SIZE (4096) ++#define APPTABLE_SECTION_PAGE_SIZE (256) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x8000) ++#define BOOT_SECTION_SIZE (4096) ++#define BOOT_SECTION_PAGE_SIZE (256) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (12288) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (1024) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (4096) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (1024) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (6) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (256) ++#define USER_SIGNATURES_PAGE_SIZE (256) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (64) ++#define PROD_SIGNATURES_PAGE_SIZE (256) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 256 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 Reserved */ ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x44 ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA32C4_H_INCLUDED */ ++ diff --git a/include/avr/iox32d3.h b/include/avr/iox32d3.h new file mode 100644 -index 0000000..11f23bd +index 0000000..97a076e --- /dev/null +++ b/include/avr/iox32d3.h @@ -0,0 +1,5065 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox32d3.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA32D3_H_INCLUDED -+#define _AVR_ATXMEGA32D3_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t reserved_0x04; -+} CLK_t; -+ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t reserved_0x02; -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t PRPD; /* Power Reduction Port D */ -+ register8_t PRPE; /* Power Reduction Port E */ -+ register8_t PRPF; /* Power Reduction Port F */ -+} PR_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from 32.768 kHz internal oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from 32.768 kHz internal oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control REgister */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t JTAGUID; /* JTAG User ID */ -+ register8_t reserved_0x05; -+ register8_t MCUCR; /* MCU Control */ -+ register8_t reserved_0x07; -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t AWEXLOCK; /* AWEX Lock */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+} EVSYS_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ -+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ -+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ -+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ -+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ -+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ -+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ -+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ -+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ -+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ -+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ -+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ -+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ -+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ -+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ -+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ -+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ -+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ -+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ -+ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ -+ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ -+ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ -+ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ -+ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ -+ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ -+ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ -+ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ -+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ -+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ -+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ -+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ -+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ -+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ -+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ -+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ -+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ -+ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ -+ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ -+ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ -+ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ -+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ -+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ -+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ -+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ -+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -+ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ -+ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ -+ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ -+ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ -+ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -+} EVSYS_CHMUX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t FUSEBYTE0; /* User ID */ -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+} NVM_FUSES_t; -+ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ -+ register8_t reserved_0x01; -+ register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ -+ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+} NVM_PROD_SIGNATURES_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase and Write Flash page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+} NVM_LB_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* 32.768kHz Timer Oscillator Pin Selection */ -+typedef enum TOSCSEL_enum -+{ -+ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1/2 on separate pins */ -+ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1/2 shared with XTAL */ -+} TOSCSEL_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_INSAMPLEDMODE_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BOD_CONTINOUSLY_gc = (0x02<<4), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BOD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t reserved_0x07; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+} ADC_t; -+ -+/* Current Limitation */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -+} ADC_CURRLIMIT_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+} ADC_CH_MUXNEG_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ -+ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ -+ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ -+ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC - Real-Time Counter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Real-Time Counter */ -+typedef struct RTC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary register */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ _WORDREGISTER(CNT); /* Count Register */ -+ _WORDREGISTER(PER); /* Period Register */ -+ _WORDREGISTER(COMP); /* Compare Register */ -+} RTC_t; -+ -+/* Prescaler Factor */ -+typedef enum RTC_PRESCALER_enum -+{ -+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ -+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ -+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ -+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ -+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ -+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ -+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ -+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -+} RTC_PRESCALER_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC_COMPINTLVL_enum -+{ -+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC_OVFINTLVL_enum -+{ -+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+} TWI_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+/* SDA hold time */ -+typedef enum SDA_HOLD_TIME_enum -+{ -+ SDA_HOLD_TIME_OFF_gc = (0x00<<1), /* SDA hold time off */ -+ SDA_HOLD_TIME_50NS_gc = (0x01<<1), /* Typical 50ns hold time */ -+ SDA_HOLD_TIME_300NS_gc = (0x02<<1), /* Typical 300ns hold time */ -+ SDA_HOLD_TIME_400NS_gc = (0x03<<1), /* Typical 400ns hold time */ -+} SDA_HOLD_TIME_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t VPCTRLA; /* Virtual Port Control Register A */ -+ register8_t VPCTRLB; /* Virtual Port Control Register B */ -+ register8_t CLKEVOUT; /* Clock and Event Out Register */ -+} PORTCFG_t; -+ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INT0MASK; /* Port Interrupt 0 Mask */ -+ register8_t INT1MASK; /* Port Interrupt 1 Mask */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Virtual Port 0 Mapping */ -+typedef enum PORTCFG_VP0MAP_enum -+{ -+ PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ -+ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ -+ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ -+ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ -+ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ -+ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ -+ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ -+ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ -+ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ -+ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ -+ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ -+ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ -+ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ -+ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ -+ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ -+ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -+} PORTCFG_VP0MAP_t; -+ -+/* Virtual Port 1 Mapping */ -+typedef enum PORTCFG_VP1MAP_enum -+{ -+ PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ -+ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ -+ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ -+ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ -+ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ -+ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ -+ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ -+ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ -+ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ -+ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ -+ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ -+ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ -+ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ -+ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ -+ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ -+ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -+} PORTCFG_VP1MAP_t; -+ -+/* Virtual Port 2 Mapping */ -+typedef enum PORTCFG_VP2MAP_enum -+{ -+ PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ -+ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ -+ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ -+ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ -+ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ -+ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ -+ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ -+ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ -+ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ -+ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ -+ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ -+ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ -+ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ -+ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ -+ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ -+ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -+} PORTCFG_VP2MAP_t; -+ -+/* Virtual Port 3 Mapping */ -+typedef enum PORTCFG_VP3MAP_enum -+{ -+ PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ -+ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ -+ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ -+ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ -+ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ -+ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ -+ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ -+ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ -+ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ -+ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ -+ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ -+ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ -+ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ -+ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ -+ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ -+ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -+} PORTCFG_VP3MAP_t; -+ -+/* Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ -+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ -+ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ -+} PORTCFG_CLKOUT_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ -+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ -+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -+} PORTCFG_EVOUT_t; -+ -+/* Port Interrupt 0 Level */ -+typedef enum PORT_INT0LVL_enum -+{ -+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INT0LVL_t; -+ -+/* Port Interrupt 1 Level */ -+typedef enum PORT_INT1LVL_enum -+{ -+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ -+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ -+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -+} PORT_INT1LVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 0 */ -+typedef struct TC0_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC0_t; -+ -+ -+/* 16-bit Timer/Counter 1 */ -+typedef struct TC1_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+} TC1_t; -+ -+ -+/* Advanced Waveform Extension */ -+typedef struct AWEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t FDEMASK; /* Fault Detection Event Mask */ -+ register8_t FDCTRL; /* Fault Detection Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x05; -+ register8_t DTBOTH; /* Dead Time Both Sides */ -+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ -+ register8_t DTLS; /* Dead Time Low Side */ -+ register8_t DTHS; /* Dead Time High Side */ -+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ -+ register8_t DTHSBUF; /* Dead Time High Side Buffer */ -+ register8_t OUTOVEN; /* Output Override Enable */ -+} AWEX_t; -+ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register */ -+} HIRES_t; -+ -+/* Clock Selection */ -+typedef enum TC_CLKSEL_enum -+{ -+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC_CLKSEL_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC_WGMODE_enum -+{ -+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ -+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC_WGMODE_t; -+ -+/* Event Action */ -+typedef enum TC_EVACT_enum -+{ -+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ -+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ -+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ -+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ -+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ -+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC_EVSEL_enum -+{ -+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC_EVSEL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC_ERRINTLVL_enum -+{ -+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC_OVFINTLVL_enum -+{ -+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_OVFINTLVL_t; -+ -+/* Compare or Capture D Interrupt Level */ -+typedef enum TC_CCDINTLVL_enum -+{ -+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC_CCDINTLVL_t; -+ -+/* Compare or Capture C Interrupt Level */ -+typedef enum TC_CCCINTLVL_enum -+{ -+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC_CCCINTLVL_t; -+ -+/* Compare or Capture B Interrupt Level */ -+typedef enum TC_CCBINTLVL_enum -+{ -+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_CCBINTLVL_t; -+ -+/* Compare or Capture A Interrupt Level */ -+typedef enum TC_CCAINTLVL_enum -+{ -+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_CCAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC_CMD_enum -+{ -+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC_CMD_t; -+ -+/* Fault Detect Action */ -+typedef enum AWEX_FDACT_enum -+{ -+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ -+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -+} AWEX_FDACT_t; -+ -+/* High Resolution Enable */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ -+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ -+ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ -+ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ -+ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -+} IRDA_EVSEL_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -+#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -+#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -+#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -+#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ -+#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ -+#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -+#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* DFLL - DFLL */ -+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -+#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -+#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPD _SFR_MEM8(0x0074) -+#define PR_PRPE _SFR_MEM8(0x0075) -+#define PR_PRPF _SFR_MEM8(0x0076) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_JTAGUID _SFR_MEM8(0x0094) -+#define MCU_MCUCR _SFR_MEM8(0x0096) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_AWEXLOCK _SFR_MEM8(0x0099) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCA_CTRLA _SFR_MEM8(0x0200) -+#define ADCA_CTRLB _SFR_MEM8(0x0201) -+#define ADCA_REFCTRL _SFR_MEM8(0x0202) -+#define ADCA_EVCTRL _SFR_MEM8(0x0203) -+#define ADCA_PRESCALER _SFR_MEM8(0x0204) -+#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -+#define ADCA_TEMP _SFR_MEM8(0x0207) -+#define ADCA_CAL _SFR_MEM16(0x020C) -+#define ADCA_CH0RES _SFR_MEM16(0x0210) -+#define ADCA_CMP _SFR_MEM16(0x0218) -+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -+#define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -+ -+/* AC - Analog Comparator */ -+#define ACA_AC0CTRL _SFR_MEM8(0x0380) -+#define ACA_AC1CTRL _SFR_MEM8(0x0381) -+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -+#define ACA_CTRLA _SFR_MEM8(0x0384) -+#define ACA_CTRLB _SFR_MEM8(0x0385) -+#define ACA_WINCTRL _SFR_MEM8(0x0386) -+#define ACA_STATUS _SFR_MEM8(0x0387) -+ -+/* RTC - Real-Time Counter */ -+#define RTC_CTRL _SFR_MEM8(0x0400) -+#define RTC_STATUS _SFR_MEM8(0x0401) -+#define RTC_INTCTRL _SFR_MEM8(0x0402) -+#define RTC_INTFLAGS _SFR_MEM8(0x0403) -+#define RTC_TEMP _SFR_MEM8(0x0404) -+#define RTC_CNT _SFR_MEM16(0x0408) -+#define RTC_PER _SFR_MEM16(0x040A) -+#define RTC_COMP _SFR_MEM16(0x040C) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIE_CTRL _SFR_MEM8(0x04A0) -+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -+ -+/* PORT - I/O Ports */ -+#define PORTA_DIR _SFR_MEM8(0x0600) -+#define PORTA_DIRSET _SFR_MEM8(0x0601) -+#define PORTA_DIRCLR _SFR_MEM8(0x0602) -+#define PORTA_DIRTGL _SFR_MEM8(0x0603) -+#define PORTA_OUT _SFR_MEM8(0x0604) -+#define PORTA_OUTSET _SFR_MEM8(0x0605) -+#define PORTA_OUTCLR _SFR_MEM8(0x0606) -+#define PORTA_OUTTGL _SFR_MEM8(0x0607) -+#define PORTA_IN _SFR_MEM8(0x0608) -+#define PORTA_INTCTRL _SFR_MEM8(0x0609) -+#define PORTA_INT0MASK _SFR_MEM8(0x060A) -+#define PORTA_INT1MASK _SFR_MEM8(0x060B) -+#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -+ -+/* PORT - I/O Ports */ -+#define PORTB_DIR _SFR_MEM8(0x0620) -+#define PORTB_DIRSET _SFR_MEM8(0x0621) -+#define PORTB_DIRCLR _SFR_MEM8(0x0622) -+#define PORTB_DIRTGL _SFR_MEM8(0x0623) -+#define PORTB_OUT _SFR_MEM8(0x0624) -+#define PORTB_OUTSET _SFR_MEM8(0x0625) -+#define PORTB_OUTCLR _SFR_MEM8(0x0626) -+#define PORTB_OUTTGL _SFR_MEM8(0x0627) -+#define PORTB_IN _SFR_MEM8(0x0628) -+#define PORTB_INTCTRL _SFR_MEM8(0x0629) -+#define PORTB_INT0MASK _SFR_MEM8(0x062A) -+#define PORTB_INT1MASK _SFR_MEM8(0x062B) -+#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INT0MASK _SFR_MEM8(0x064A) -+#define PORTC_INT1MASK _SFR_MEM8(0x064B) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INT0MASK _SFR_MEM8(0x066A) -+#define PORTD_INT1MASK _SFR_MEM8(0x066B) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTE_DIR _SFR_MEM8(0x0680) -+#define PORTE_DIRSET _SFR_MEM8(0x0681) -+#define PORTE_DIRCLR _SFR_MEM8(0x0682) -+#define PORTE_DIRTGL _SFR_MEM8(0x0683) -+#define PORTE_OUT _SFR_MEM8(0x0684) -+#define PORTE_OUTSET _SFR_MEM8(0x0685) -+#define PORTE_OUTCLR _SFR_MEM8(0x0686) -+#define PORTE_OUTTGL _SFR_MEM8(0x0687) -+#define PORTE_IN _SFR_MEM8(0x0688) -+#define PORTE_INTCTRL _SFR_MEM8(0x0689) -+#define PORTE_INT0MASK _SFR_MEM8(0x068A) -+#define PORTE_INT1MASK _SFR_MEM8(0x068B) -+#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) -+ -+/* PORT - I/O Ports */ -+#define PORTF_DIR _SFR_MEM8(0x06A0) -+#define PORTF_DIRSET _SFR_MEM8(0x06A1) -+#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -+#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -+#define PORTF_OUT _SFR_MEM8(0x06A4) -+#define PORTF_OUTSET _SFR_MEM8(0x06A5) -+#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -+#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -+#define PORTF_IN _SFR_MEM8(0x06A8) -+#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -+#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -+#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -+#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -+#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -+#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -+#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -+#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -+#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -+#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -+#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -+#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -+#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCC0_CTRLA _SFR_MEM8(0x0800) -+#define TCC0_CTRLB _SFR_MEM8(0x0801) -+#define TCC0_CTRLC _SFR_MEM8(0x0802) -+#define TCC0_CTRLD _SFR_MEM8(0x0803) -+#define TCC0_CTRLE _SFR_MEM8(0x0804) -+#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -+#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -+#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -+#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC0_TEMP _SFR_MEM8(0x080F) -+#define TCC0_CNT _SFR_MEM16(0x0820) -+#define TCC0_PER _SFR_MEM16(0x0826) -+#define TCC0_CCA _SFR_MEM16(0x0828) -+#define TCC0_CCB _SFR_MEM16(0x082A) -+#define TCC0_CCC _SFR_MEM16(0x082C) -+#define TCC0_CCD _SFR_MEM16(0x082E) -+#define TCC0_PERBUF _SFR_MEM16(0x0836) -+#define TCC0_CCABUF _SFR_MEM16(0x0838) -+#define TCC0_CCBBUF _SFR_MEM16(0x083A) -+#define TCC0_CCCBUF _SFR_MEM16(0x083C) -+#define TCC0_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCC1_CTRLA _SFR_MEM8(0x0840) -+#define TCC1_CTRLB _SFR_MEM8(0x0841) -+#define TCC1_CTRLC _SFR_MEM8(0x0842) -+#define TCC1_CTRLD _SFR_MEM8(0x0843) -+#define TCC1_CTRLE _SFR_MEM8(0x0844) -+#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -+#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -+#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -+#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC1_TEMP _SFR_MEM8(0x084F) -+#define TCC1_CNT _SFR_MEM16(0x0860) -+#define TCC1_PER _SFR_MEM16(0x0866) -+#define TCC1_CCA _SFR_MEM16(0x0868) -+#define TCC1_CCB _SFR_MEM16(0x086A) -+#define TCC1_PERBUF _SFR_MEM16(0x0876) -+#define TCC1_CCABUF _SFR_MEM16(0x0878) -+#define TCC1_CCBBUF _SFR_MEM16(0x087A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXC_CTRL _SFR_MEM8(0x0880) -+#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -+#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -+#define AWEXC_STATUS _SFR_MEM8(0x0884) -+#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -+#define AWEXC_DTLS _SFR_MEM8(0x0888) -+#define AWEXC_DTHS _SFR_MEM8(0x0889) -+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x0890) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08A0) -+#define USARTC0_STATUS _SFR_MEM8(0x08A1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -+#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -+#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIC_CTRL _SFR_MEM8(0x08C0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -+#define SPIC_STATUS _SFR_MEM8(0x08C2) -+#define SPIC_DATA _SFR_MEM8(0x08C3) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCD0_CTRLA _SFR_MEM8(0x0900) -+#define TCD0_CTRLB _SFR_MEM8(0x0901) -+#define TCD0_CTRLC _SFR_MEM8(0x0902) -+#define TCD0_CTRLD _SFR_MEM8(0x0903) -+#define TCD0_CTRLE _SFR_MEM8(0x0904) -+#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -+#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -+#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -+#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -+#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD0_TEMP _SFR_MEM8(0x090F) -+#define TCD0_CNT _SFR_MEM16(0x0920) -+#define TCD0_PER _SFR_MEM16(0x0926) -+#define TCD0_CCA _SFR_MEM16(0x0928) -+#define TCD0_CCB _SFR_MEM16(0x092A) -+#define TCD0_CCC _SFR_MEM16(0x092C) -+#define TCD0_CCD _SFR_MEM16(0x092E) -+#define TCD0_PERBUF _SFR_MEM16(0x0936) -+#define TCD0_CCABUF _SFR_MEM16(0x0938) -+#define TCD0_CCBBUF _SFR_MEM16(0x093A) -+#define TCD0_CCCBUF _SFR_MEM16(0x093C) -+#define TCD0_CCDBUF _SFR_MEM16(0x093E) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD0_DATA _SFR_MEM8(0x09A0) -+#define USARTD0_STATUS _SFR_MEM8(0x09A1) -+#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -+#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -+#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPID_CTRL _SFR_MEM8(0x09C0) -+#define SPID_INTCTRL _SFR_MEM8(0x09C1) -+#define SPID_STATUS _SFR_MEM8(0x09C2) -+#define SPID_DATA _SFR_MEM8(0x09C3) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCE0_CTRLA _SFR_MEM8(0x0A00) -+#define TCE0_CTRLB _SFR_MEM8(0x0A01) -+#define TCE0_CTRLC _SFR_MEM8(0x0A02) -+#define TCE0_CTRLD _SFR_MEM8(0x0A03) -+#define TCE0_CTRLE _SFR_MEM8(0x0A04) -+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE0_TEMP _SFR_MEM8(0x0A0F) -+#define TCE0_CNT _SFR_MEM16(0x0A20) -+#define TCE0_PER _SFR_MEM16(0x0A26) -+#define TCE0_CCA _SFR_MEM16(0x0A28) -+#define TCE0_CCB _SFR_MEM16(0x0A2A) -+#define TCE0_CCC _SFR_MEM16(0x0A2C) -+#define TCE0_CCD _SFR_MEM16(0x0A2E) -+#define TCE0_PERBUF _SFR_MEM16(0x0A36) -+#define TCE0_CCABUF _SFR_MEM16(0x0A38) -+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXE_CTRL _SFR_MEM8(0x0A80) -+#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) -+#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) -+#define AWEXE_STATUS _SFR_MEM8(0x0A84) -+#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) -+#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) -+#define AWEXE_DTLS _SFR_MEM8(0x0A88) -+#define AWEXE_DTHS _SFR_MEM8(0x0A89) -+#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) -+#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) -+#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE0_DATA _SFR_MEM8(0x0AA0) -+#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -+#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -+#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -+#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -+#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -+#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIE_CTRL _SFR_MEM8(0x0AC0) -+#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) -+#define SPIE_STATUS _SFR_MEM8(0x0AC2) -+#define SPIE_DATA _SFR_MEM8(0x0AC3) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCF0_CTRLA _SFR_MEM8(0x0B00) -+#define TCF0_CTRLB _SFR_MEM8(0x0B01) -+#define TCF0_CTRLC _SFR_MEM8(0x0B02) -+#define TCF0_CTRLD _SFR_MEM8(0x0B03) -+#define TCF0_CTRLE _SFR_MEM8(0x0B04) -+#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -+#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -+#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -+#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -+#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -+#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -+#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -+#define TCF0_TEMP _SFR_MEM8(0x0B0F) -+#define TCF0_CNT _SFR_MEM16(0x0B20) -+#define TCF0_PER _SFR_MEM16(0x0B26) -+#define TCF0_CCA _SFR_MEM16(0x0B28) -+#define TCF0_CCB _SFR_MEM16(0x0B2A) -+#define TCF0_CCC _SFR_MEM16(0x0B2C) -+#define TCF0_CCD _SFR_MEM16(0x0B2E) -+#define TCF0_PERBUF _SFR_MEM16(0x0B36) -+#define TCF0_CCABUF _SFR_MEM16(0x0B38) -+#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -+#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -+#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ -+#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ -+ -+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -+ -+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ -+ -+/* PR.PRPD bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPE bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPF bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ -+#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ -+ -+#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ -+#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.MCUCR bit masks and bit positions */ -+#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -+#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -+#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ -+ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.AWEXLOCK bit masks and bit positions */ -+#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -+#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ -+ -+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0xFF /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ -+#define NVM_CMD7_bp 7 /* Command bit 7 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ -+ -+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ -+ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -+#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ -+#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ -+#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ -+#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ -+#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ -+#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ -+#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ -+#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ -+#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ -+#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ -+#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ -+#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ -+#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ -+#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ -+#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ -+#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ -+#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ -+#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ -+ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ -+#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ -+ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_TOSCSEL_bm 0x20 /* 32.768kHz Timer Oscillator Pin Selection bit mask. */ -+#define NVM_FUSES_TOSCSEL_bp 5 /* 32.768kHz Timer Oscillator Pin Selection bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -+#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HSMODE Predefined. */ -+/* AC_HSMODE Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -+#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -+#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -+#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -+#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -+#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -+#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -+#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -+#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -+#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ -+ -+#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -+#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -+#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -+#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -+#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -+#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -+#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -+#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -+#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -+#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -+#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* RTC - Real-Time Counter */ -+/* RTC.CTRL bit masks and bit positions */ -+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ -+ -+/* RTC.STATUS bit masks and bit positions */ -+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC.INTCTRL bit masks and bit positions */ -+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC.INTFLAGS bit masks and bit positions */ -+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Tisdahmeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Tisdahmeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Tisdahmeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Tisdahmeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Tisdahmeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Tisdahmeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* PORT - Port Configuration */ -+/* PORTCFG.VPCTRLA bit masks and bit positions */ -+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ -+ -+/* PORTCFG.VPCTRLB bit masks and bit positions */ -+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ -+ -+/* PORTCFG.CLKEVOUT bit masks and bit positions */ -+#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ -+ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ -+ -+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ -+ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC0.CTRLA bit masks and bit positions */ -+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC0.CTRLB bit masks and bit positions */ -+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ -+ -+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ -+ -+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC0.CTRLC bit masks and bit positions */ -+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ -+ -+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ -+ -+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC0.CTRLD bit masks and bit positions */ -+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC0_EVACT_gp 5 /* Event Action group position. */ -+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC0.CTRLE bit masks and bit positions */ -+#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -+#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ -+ -+/* TC0.INTCTRLA bit masks and bit positions */ -+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC0.INTCTRLB bit masks and bit positions */ -+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ -+ -+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ -+ -+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC0.CTRLFCLR bit masks and bit positions */ -+#define TC0_CMD_gm 0x0C /* Command group mask. */ -+#define TC0_CMD_gp 2 /* Command group position. */ -+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC0_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC0_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC0_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC0.CTRLFSET bit masks and bit positions */ -+/* TC0_CMD Predefined. */ -+/* TC0_CMD Predefined. */ -+ -+/* TC0_LUPD Predefined. */ -+/* TC0_LUPD Predefined. */ -+ -+/* TC0_DIR Predefined. */ -+/* TC0_DIR Predefined. */ -+ -+/* TC0.CTRLGCLR bit masks and bit positions */ -+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ -+ -+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ -+ -+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC0.CTRLGSET bit masks and bit positions */ -+/* TC0_CCDBV Predefined. */ -+/* TC0_CCDBV Predefined. */ -+ -+/* TC0_CCCBV Predefined. */ -+/* TC0_CCCBV Predefined. */ -+ -+/* TC0_CCBBV Predefined. */ -+/* TC0_CCBBV Predefined. */ -+ -+/* TC0_CCABV Predefined. */ -+/* TC0_CCABV Predefined. */ -+ -+/* TC0_PERBV Predefined. */ -+/* TC0_PERBV Predefined. */ -+ -+/* TC0.INTFLAGS bit masks and bit positions */ -+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ -+ -+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ -+ -+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC1.CTRLA bit masks and bit positions */ -+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC1.CTRLB bit masks and bit positions */ -+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC1.CTRLC bit masks and bit positions */ -+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC1.CTRLD bit masks and bit positions */ -+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC1_EVACT_gp 5 /* Event Action group position. */ -+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC1.CTRLE bit masks and bit positions */ -+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ -+ -+/* TC1.INTCTRLA bit masks and bit positions */ -+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC1.INTCTRLB bit masks and bit positions */ -+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC1.CTRLFCLR bit masks and bit positions */ -+#define TC1_CMD_gm 0x0C /* Command group mask. */ -+#define TC1_CMD_gp 2 /* Command group position. */ -+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC1_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC1_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC1_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC1.CTRLFSET bit masks and bit positions */ -+/* TC1_CMD Predefined. */ -+/* TC1_CMD Predefined. */ -+ -+/* TC1_LUPD Predefined. */ -+/* TC1_LUPD Predefined. */ -+ -+/* TC1_DIR Predefined. */ -+/* TC1_DIR Predefined. */ -+ -+/* TC1.CTRLGCLR bit masks and bit positions */ -+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC1.CTRLGSET bit masks and bit positions */ -+/* TC1_CCBBV Predefined. */ -+/* TC1_CCBBV Predefined. */ -+ -+/* TC1_CCABV Predefined. */ -+/* TC1_CCABV Predefined. */ -+ -+/* TC1_PERBV Predefined. */ -+/* TC1_PERBV Predefined. */ -+ -+/* TC1.INTFLAGS bit masks and bit positions */ -+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* AWEX.CTRL bit masks and bit positions */ -+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ -+ -+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ -+ -+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ -+ -+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ -+ -+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ -+ -+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ -+ -+/* AWEX.FDCTRL bit masks and bit positions */ -+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ -+ -+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ -+ -+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ -+ -+/* AWEX.STATUS bit masks and bit positions */ -+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ -+ -+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ -+ -+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ -+ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ -+#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ -+ -+#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ -+#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT0_vect_num 2 -+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -+#define PORTC_INT1_vect_num 3 -+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT0_vect_num 4 -+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -+#define PORTR_INT1_vect_num 5 -+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ -+ -+/* RTC interrupt vectors */ -+#define RTC_OVF_vect_num 10 -+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -+#define RTC_COMP_vect_num 11 -+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 12 -+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 13 -+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_OVF_vect_num 14 -+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -+#define TCC0_ERR_vect_num 15 -+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -+#define TCC0_CCA_vect_num 16 -+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -+#define TCC0_CCB_vect_num 17 -+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -+#define TCC0_CCC_vect_num 18 -+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -+#define TCC0_CCD_vect_num 19 -+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ -+ -+/* TCC1 interrupt vectors */ -+#define TCC1_OVF_vect_num 20 -+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -+#define TCC1_ERR_vect_num 21 -+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -+#define TCC1_CCA_vect_num 22 -+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -+#define TCC1_CCB_vect_num 23 -+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 24 -+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 25 -+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 26 -+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 27 -+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 32 -+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -+#define NVM_SPM_vect_num 33 -+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ -+ -+/* PORTB interrupt vectors */ -+#define PORTB_INT0_vect_num 34 -+#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -+#define PORTB_INT1_vect_num 35 -+#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ -+ -+/* PORTE interrupt vectors */ -+#define PORTE_INT0_vect_num 43 -+#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -+#define PORTE_INT1_vect_num 44 -+#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ -+ -+/* TWIE interrupt vectors */ -+#define TWIE_TWIS_vect_num 45 -+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -+#define TWIE_TWIM_vect_num 46 -+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_OVF_vect_num 47 -+#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -+#define TCE0_ERR_vect_num 48 -+#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -+#define TCE0_CCA_vect_num 49 -+#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -+#define TCE0_CCB_vect_num 50 -+#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -+#define TCE0_CCC_vect_num 51 -+#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -+#define TCE0_CCD_vect_num 52 -+#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ -+ -+/* USARTE0 interrupt vectors */ -+#define USARTE0_RXC_vect_num 58 -+#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -+#define USARTE0_DRE_vect_num 59 -+#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -+#define USARTE0_TXC_vect_num 60 -+#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT0_vect_num 64 -+#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -+#define PORTD_INT1_vect_num 65 -+#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ -+ -+/* PORTA interrupt vectors */ -+#define PORTA_INT0_vect_num 66 -+#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -+#define PORTA_INT1_vect_num 67 -+#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ -+ -+/* ACA interrupt vectors */ -+#define ACA_AC0_vect_num 68 -+#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -+#define ACA_AC1_vect_num 69 -+#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -+#define ACA_ACW_vect_num 70 -+#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ -+ -+/* ADCA interrupt vectors */ -+#define ADCA_CH0_vect_num 71 -+#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_OVF_vect_num 77 -+#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -+#define TCD0_ERR_vect_num 78 -+#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -+#define TCD0_CCA_vect_num 79 -+#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -+#define TCD0_CCB_vect_num 80 -+#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -+#define TCD0_CCC_vect_num 81 -+#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -+#define TCD0_CCD_vect_num 82 -+#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ -+ -+/* SPID interrupt vectors */ -+#define SPID_INT_vect_num 87 -+#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ -+ -+/* USARTD0 interrupt vectors */ -+#define USARTD0_RXC_vect_num 88 -+#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -+#define USARTD0_DRE_vect_num 89 -+#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -+#define USARTD0_TXC_vect_num 90 -+#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ -+ -+/* PORTF interrupt vectors */ -+#define PORTF_INT0_vect_num 104 -+#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -+#define PORTF_INT1_vect_num 105 -+#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_OVF_vect_num 108 -+#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -+#define TCF0_ERR_vect_num 109 -+#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -+#define TCF0_CCA_vect_num 110 -+#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -+#define TCF0_CCB_vect_num 111 -+#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -+#define TCF0_CCC_vect_num 112 -+#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -+#define TCF0_CCD_vect_num 113 -+#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (114 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (36864) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (32768) -+#define APP_SECTION_PAGE_SIZE (256) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0x7000) -+#define APPTABLE_SECTION_SIZE (4096) -+#define APPTABLE_SECTION_PAGE_SIZE (256) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x8000) -+#define BOOT_SECTION_SIZE (4096) -+#define BOOT_SECTION_PAGE_SIZE (256) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (12288) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (1024) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (4096) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (1024) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (6) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (256) -+#define USER_SIGNATURES_PAGE_SIZE (256) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (52) -+#define PROD_SIGNATURES_PAGE_SIZE (256) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 256 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 6 -+ -+/* Fuse Byte 0 */ -+#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ -+#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ -+#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ -+#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ -+#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ -+#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ -+#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ -+#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ -+#define FUSE0_DEFAULT (0xFF) -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* 32.768kHz Timer Oscillator Pin Selection */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x95 -+#define SIGNATURE_2 0x4A -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA32D3_H_INCLUDED */ -+ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox32d3.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA32D3_H_INCLUDED ++#define _AVR_ATXMEGA32D3_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t reserved_0x04; ++} CLK_t; ++ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t reserved_0x02; ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from 32.768 kHz internal oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from 32.768 kHz internal oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control REgister */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t reserved_0x07; ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t FUSEBYTE0; /* User ID */ ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ ++ register8_t reserved_0x01; ++ register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++} NVM_PROD_SIGNATURES_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase and Write Flash page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++} NVM_LB_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* 32.768kHz Timer Oscillator Pin Selection */ ++typedef enum TOSCSEL_enum ++{ ++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1/2 on separate pins */ ++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1/2 shared with XTAL */ ++} TOSCSEL_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_INSAMPLEDMODE_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BOD_CONTINOUSLY_gc = (0x02<<4), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BOD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t reserved_0x07; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++} ADC_t; ++ ++/* Current Limitation */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ ++} ADC_CURRLIMIT_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ ++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ ++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ ++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++/* SDA hold time */ ++typedef enum SDA_HOLD_TIME_enum ++{ ++ SDA_HOLD_TIME_OFF_gc = (0x00<<1), /* SDA hold time off */ ++ SDA_HOLD_TIME_50NS_gc = (0x01<<1), /* Typical 50ns hold time */ ++ SDA_HOLD_TIME_300NS_gc = (0x02<<1), /* Typical 300ns hold time */ ++ SDA_HOLD_TIME_400NS_gc = (0x03<<1), /* Typical 400ns hold time */ ++} SDA_HOLD_TIME_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++} PORTCFG_t; ++ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Virtual Port 0 Mapping */ ++typedef enum PORTCFG_VP0MAP_enum ++{ ++ PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP0MAP_t; ++ ++/* Virtual Port 1 Mapping */ ++typedef enum PORTCFG_VP1MAP_enum ++{ ++ PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP1MAP_t; ++ ++/* Virtual Port 2 Mapping */ ++typedef enum PORTCFG_VP2MAP_enum ++{ ++ PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP2MAP_t; ++ ++/* Virtual Port 3 Mapping */ ++typedef enum PORTCFG_VP3MAP_enum ++{ ++ PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP3MAP_t; ++ ++/* Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x05; ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ ++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ ++#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ ++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) ++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLL - DFLL */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORT - I/O Ports */ ++#define PORTF_DIR _SFR_MEM8(0x06A0) ++#define PORTF_DIRSET _SFR_MEM8(0x06A1) ++#define PORTF_DIRCLR _SFR_MEM8(0x06A2) ++#define PORTF_DIRTGL _SFR_MEM8(0x06A3) ++#define PORTF_OUT _SFR_MEM8(0x06A4) ++#define PORTF_OUTSET _SFR_MEM8(0x06A5) ++#define PORTF_OUTCLR _SFR_MEM8(0x06A6) ++#define PORTF_OUTTGL _SFR_MEM8(0x06A7) ++#define PORTF_IN _SFR_MEM8(0x06A8) ++#define PORTF_INTCTRL _SFR_MEM8(0x06A9) ++#define PORTF_INT0MASK _SFR_MEM8(0x06AA) ++#define PORTF_INT1MASK _SFR_MEM8(0x06AB) ++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) ++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) ++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) ++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) ++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) ++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) ++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) ++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) ++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXE_CTRL _SFR_MEM8(0x0A80) ++#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) ++#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) ++#define AWEXE_STATUS _SFR_MEM8(0x0A84) ++#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) ++#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) ++#define AWEXE_DTLS _SFR_MEM8(0x0A88) ++#define AWEXE_DTHS _SFR_MEM8(0x0A89) ++#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) ++#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) ++#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIE_CTRL _SFR_MEM8(0x0AC0) ++#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) ++#define SPIE_STATUS _SFR_MEM8(0x0AC2) ++#define SPIE_DATA _SFR_MEM8(0x0AC3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCF0_CTRLA _SFR_MEM8(0x0B00) ++#define TCF0_CTRLB _SFR_MEM8(0x0B01) ++#define TCF0_CTRLC _SFR_MEM8(0x0B02) ++#define TCF0_CTRLD _SFR_MEM8(0x0B03) ++#define TCF0_CTRLE _SFR_MEM8(0x0B04) ++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) ++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) ++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) ++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) ++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF0_TEMP _SFR_MEM8(0x0B0F) ++#define TCF0_CNT _SFR_MEM16(0x0B20) ++#define TCF0_PER _SFR_MEM16(0x0B26) ++#define TCF0_CCA _SFR_MEM16(0x0B28) ++#define TCF0_CCB _SFR_MEM16(0x0B2A) ++#define TCF0_CCC _SFR_MEM16(0x0B2C) ++#define TCF0_CCD _SFR_MEM16(0x0B2E) ++#define TCF0_PERBUF _SFR_MEM16(0x0B36) ++#define TCF0_CCABUF _SFR_MEM16(0x0B38) ++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) ++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) ++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ ++#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ ++#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ ++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ ++ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0xFF /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ ++#define NVM_CMD7_bp 7 /* Command bit 7 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ ++#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ ++#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ ++#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ ++#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ ++#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ ++#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ ++#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ ++#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ ++#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ ++#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ ++#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ ++#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ ++#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ ++#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ ++#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ ++#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ ++#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ ++#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ ++#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ ++ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_TOSCSEL_bm 0x20 /* 32.768kHz Timer Oscillator Pin Selection bit mask. */ ++#define NVM_FUSES_TOSCSEL_bp 5 /* 32.768kHz Timer Oscillator Pin Selection bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ ++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HSMODE Predefined. */ ++/* AC_HSMODE Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ ++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ ++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ ++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ ++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ ++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ ++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ ++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ ++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ ++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ ++ ++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ ++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ ++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ ++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ ++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ ++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ ++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ ++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ ++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ ++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ ++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* RTC - Real-Time Counter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Tisdahmeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Tisdahmeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Tisdahmeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Tisdahmeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Tisdahmeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Tisdahmeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* PORT - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD Predefined. */ ++/* TC0_CMD Predefined. */ ++ ++/* TC0_LUPD Predefined. */ ++/* TC0_LUPD Predefined. */ ++ ++/* TC0_DIR Predefined. */ ++/* TC0_DIR Predefined. */ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV Predefined. */ ++/* TC0_CCDBV Predefined. */ ++ ++/* TC0_CCCBV Predefined. */ ++/* TC0_CCCBV Predefined. */ ++ ++/* TC0_CCBBV Predefined. */ ++/* TC0_CCBBV Predefined. */ ++ ++/* TC0_CCABV Predefined. */ ++/* TC0_CCABV Predefined. */ ++ ++/* TC0_PERBV Predefined. */ ++/* TC0_PERBV Predefined. */ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD Predefined. */ ++/* TC1_CMD Predefined. */ ++ ++/* TC1_LUPD Predefined. */ ++/* TC1_LUPD Predefined. */ ++ ++/* TC1_DIR Predefined. */ ++/* TC1_DIR Predefined. */ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV Predefined. */ ++/* TC1_CCBBV Predefined. */ ++ ++/* TC1_CCABV Predefined. */ ++/* TC1_CCABV Predefined. */ ++ ++/* TC1_PERBV Predefined. */ ++/* TC1_PERBV Predefined. */ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++#define USART_UDORD_bm 0x04 /* SPI Master Mode, Data Order bit mask. */ ++#define USART_UDORD_bp 2 /* SPI Master Mode, Data Order bit position. */ ++ ++#define USART_UCPHA_bm 0x02 /* SPI Master Mode, Clock Phase bit mask. */ ++#define USART_UCPHA_bp 1 /* SPI Master Mode, Clock Phase bit position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* PORTF interrupt vectors */ ++#define PORTF_INT0_vect_num 104 ++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ ++#define PORTF_INT1_vect_num 105 ++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_OVF_vect_num 108 ++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ ++#define TCF0_ERR_vect_num 109 ++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ ++#define TCF0_CCA_vect_num 110 ++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ ++#define TCF0_CCB_vect_num 111 ++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ ++#define TCF0_CCC_vect_num 112 ++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ ++#define TCF0_CCD_vect_num 113 ++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (114 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (36864) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (32768) ++#define APP_SECTION_PAGE_SIZE (256) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x7000) ++#define APPTABLE_SECTION_SIZE (4096) ++#define APPTABLE_SECTION_PAGE_SIZE (256) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x8000) ++#define BOOT_SECTION_SIZE (4096) ++#define BOOT_SECTION_PAGE_SIZE (256) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (12288) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (1024) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (4096) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (1024) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (6) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (256) ++#define USER_SIGNATURES_PAGE_SIZE (256) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (256) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 256 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 */ ++#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ ++#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ ++#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ ++#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ ++#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ ++#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ ++#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ ++#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ ++#define FUSE0_DEFAULT (0xFF) ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* 32.768kHz Timer Oscillator Pin Selection */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x4A ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA32D3_H_INCLUDED */ ++ diff --git a/include/avr/iox32d4.h b/include/avr/iox32d4.h -index efc25b9..f25ba47 100644 +index efc25b9..1897317 100644 --- a/include/avr/iox32d4.h +++ b/include/avr/iox32d4.h -@@ -414,6 +414,43 @@ typedef struct PMIC_struct - } PMIC_t; - - -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+} CRC_SOURCE_t; -+ -+ - /* - -------------------------------------------------------------------------- - EVSYS - Event System -@@ -1059,6 +1096,7 @@ typedef enum ADC_CH_GAIN_enum - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ - } ADC_CH_GAIN_t; - - /* Conversion result resolution */ -@@ -1069,6 +1107,14 @@ typedef enum ADC_RESOLUTION_enum - ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ - } ADC_RESOLUTION_t; - -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ -+} ADC_CURRLIMIT_t; -+ - /* Voltage reference selection */ - typedef enum ADC_REFSEL_enum - { -@@ -2187,6 +2233,7 @@ IO Module Instances. Mapped to memory. - #define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ - #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ - #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ - #define PORTA (*(PORT_t *) 0x0600) /* Port A */ - #define PORTB (*(PORT_t *) 0x0620) /* Port B */ - #define PORTC (*(PORT_t *) 0x0640) /* Port C */ -@@ -2421,6 +2468,23 @@ IO Module Instances. Mapped to memory. - #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) - #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -+/* TWIE - Two-Wire Interface E */ -+#define TWIE_CTRL _SFR_MEM8(0x04A0) -+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -+ -+ - /* PORTA - Port A */ - #define PORTA_DIR _SFR_MEM8(0x0600) - #define PORTA_DIRSET _SFR_MEM8(0x0601) -@@ -3808,6 +3872,8 @@ IO Module Instances. Mapped to memory. - #define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ - #define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ - #define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ -+#define ADC_CH_MUXPOS4_bm (1<<7) /* Positive Input Select bit 3 mask. */ -+#define ADC_CH_MUXPOS4_bp 7 /* Positive Input Select bit 3 position. */ - - #define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ - #define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ -@@ -3861,6 +3927,13 @@ IO Module Instances. Mapped to memory. - - - /* ADC.CTRLB bit masks and bit positions */ -+#define ADC_IMPMODE_bm 0x80 /* Impedance Mode bit mask. */ -+#define ADC_IMPMODE_bp 7 /* Impedance Mode bit position. */ -+ -+#define ADC_CURRENT_bm 0x60 /* Current bit mask. */ -+#define ADC_CURRENT1_bp 6 /* Current bit position. */ -+#define ADC_CURRENT0_bp 5 /* Current bit position. */ -+ - #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ - #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -@@ -3876,12 +3949,14 @@ IO Module Instances. Mapped to memory. - - - /* ADC.REFCTRL bit masks and bit positions */ +@@ -1,5554 +1,5635 @@ +-/* Copyright (c) 2009-2010 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iox32d4.h 2200 2010-12-14 04:24:24Z arcanum $ */ +- +-/* avr/iox32d4.h - definitions for ATxmega32D4 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iox32d4.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATxmega32D4_H_ +-#define _AVR_ATxmega32D4_H_ 1 +- +- +-/* Ungrouped common registers */ +-#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +-#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +-#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +-#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +-#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +-#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +-#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +-#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +-#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +-#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +-#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +-#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +-#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +-#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +-#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +-#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +- +-#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +-#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +-#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +-#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +-#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +-#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +-#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +-#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +-#define SREG _SFR_MEM8(0x003F) /* Status Register */ +- +- +-/* C Language Only */ +-#if !defined (__ASSEMBLER__) +- +-#include +- +-typedef volatile uint8_t register8_t; +-typedef volatile uint16_t register16_t; +-typedef volatile uint32_t register32_t; +- +- +-#ifdef _WORDREGISTER +-#undef _WORDREGISTER +-#endif +-#define _WORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register16_t regname; \ +- struct \ +- { \ +- register8_t regname ## L; \ +- register8_t regname ## H; \ +- }; \ +- } +- +-#ifdef _DWORDREGISTER +-#undef _DWORDREGISTER +-#endif +-#define _DWORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register32_t regname; \ +- struct \ +- { \ +- register8_t regname ## 0; \ +- register8_t regname ## 1; \ +- register8_t regname ## 2; \ +- register8_t regname ## 3; \ +- }; \ +- } +- +- +-/* +-========================================================================== +-IO Module Structures +-========================================================================== +-*/ +- +- +-/* +--------------------------------------------------------------------------- +-XOCD - On-Chip Debug System +--------------------------------------------------------------------------- +-*/ +- +-/* On-Chip Debug System */ +-typedef struct OCD_struct +-{ +- register8_t OCDR0; /* OCD Register 0 */ +- register8_t OCDR1; /* OCD Register 1 */ +-} OCD_t; +- +- +-/* CCP signatures */ +-typedef enum CCP_enum +-{ +- CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ +- CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +-} CCP_t; +- +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Clock System */ +-typedef struct CLK_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t PSCTRL; /* Prescaler Control Register */ +- register8_t LOCK; /* Lock register */ +- register8_t RTCCTRL; /* RTC Control Register */ +-} CLK_t; +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Power Reduction */ +-typedef struct PR_struct +-{ +- register8_t PRGEN; /* General Power Reduction */ +- register8_t PRPA; /* Power Reduction Port A */ +- register8_t PRPB; /* Power Reduction Port B */ +- register8_t PRPC; /* Power Reduction Port C */ +- register8_t PRPD; /* Power Reduction Port D */ +- register8_t PRPE; /* Power Reduction Port E */ +- register8_t PRPF; /* Power Reduction Port F */ +-} PR_t; +- +-/* System Clock Selection */ +-typedef enum CLK_SCLKSEL_enum +-{ +- CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ +- CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ +- CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ +- CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ +- CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +-} CLK_SCLKSEL_t; +- +-/* Prescaler A Division Factor */ +-typedef enum CLK_PSADIV_enum +-{ +- CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ +- CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ +- CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ +- CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ +- CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ +- CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ +- CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ +- CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ +- CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ +- CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +-} CLK_PSADIV_t; +- +-/* Prescaler B and C Division Factor */ +-typedef enum CLK_PSBCDIV_enum +-{ +- CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ +- CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ +- CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ +- CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +-} CLK_PSBCDIV_t; +- +-/* RTC Clock Source */ +-typedef enum CLK_RTCSRC_enum +-{ +- CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ +- CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ +- CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ +- CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +-} CLK_RTCSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-SLEEP - Sleep Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Sleep Controller */ +-typedef struct SLEEP_struct +-{ +- register8_t CTRL; /* Control Register */ +-} SLEEP_t; +- +-/* Sleep Mode */ +-typedef enum SLEEP_SMODE_enum +-{ +- SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ +- SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +- SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ +- SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ +- SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +-} SLEEP_SMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-OSC - Oscillator +--------------------------------------------------------------------------- +-*/ +- +-/* Oscillator */ +-typedef struct OSC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t XOSCCTRL; /* External Oscillator Control Register */ +- register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ +- register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ +- register8_t PLLCTRL; /* PLL Control REgister */ +- register8_t DFLLCTRL; /* DFLL Control Register */ +-} OSC_t; +- +-/* Oscillator Frequency Range */ +-typedef enum OSC_FRQRANGE_enum +-{ +- OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ +- OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ +- OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ +- OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +-} OSC_FRQRANGE_t; +- +-/* External Oscillator Selection and Startup Time */ +-typedef enum OSC_XOSCSEL_enum +-{ +- OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ +- OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ +- OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ +- OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ +- OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +-} OSC_XOSCSEL_t; +- +-/* PLL Clock Source */ +-typedef enum OSC_PLLSRC_enum +-{ +- OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ +- OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ +- OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +-} OSC_PLLSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-DFLL - DFLL +--------------------------------------------------------------------------- +-*/ +- +-/* DFLL */ +-typedef struct DFLL_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t CALA; /* Calibration Register A */ +- register8_t CALB; /* Calibration Register B */ +- register8_t COMP0; /* Oscillator Compare Register 0 */ +- register8_t COMP1; /* Oscillator Compare Register 1 */ +- register8_t COMP2; /* Oscillator Compare Register 2 */ +- register8_t reserved_0x07; +-} DFLL_t; +- +- +-/* +--------------------------------------------------------------------------- +-RST - Reset +--------------------------------------------------------------------------- +-*/ +- +-/* Reset */ +-typedef struct RST_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t CTRL; /* Control Register */ +-} RST_t; +- +- +-/* +--------------------------------------------------------------------------- +-WDT - Watch-Dog Timer +--------------------------------------------------------------------------- +-*/ +- +-/* Watch-Dog Timer */ +-typedef struct WDT_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t WINCTRL; /* Windowed Mode Control */ +- register8_t STATUS; /* Status */ +-} WDT_t; +- +-/* Period setting */ +-typedef enum WDT_PER_enum +-{ +- WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ +- WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ +- WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ +- WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_PER_t; +- +-/* Closed window period */ +-typedef enum WDT_WPER_enum +-{ +- WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ +- WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ +- WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ +- WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_WPER_t; +- +- +-/* +--------------------------------------------------------------------------- +-MCU - MCU Control +--------------------------------------------------------------------------- +-*/ +- +-/* MCU Control */ +-typedef struct MCU_struct +-{ +- register8_t DEVID0; /* Device ID byte 0 */ +- register8_t DEVID1; /* Device ID byte 1 */ +- register8_t DEVID2; /* Device ID byte 2 */ +- register8_t REVID; /* Revision ID */ +- register8_t JTAGUID; /* JTAG User ID */ +- register8_t reserved_0x05; +- register8_t MCUCR; /* MCU Control */ +- register8_t reserved_0x07; +- register8_t EVSYSLOCK; /* Event System Lock */ +- register8_t AWEXLOCK; /* AWEX Lock */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +-} MCU_t; +- +- +-/* +--------------------------------------------------------------------------- +-PMIC - Programmable Multi-level Interrupt Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Programmable Multi-level Interrupt Controller */ +-typedef struct PMIC_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t INTPRI; /* Interrupt Priority */ +- register8_t CTRL; /* Control Register */ +-} PMIC_t; +- +- +-/* +--------------------------------------------------------------------------- +-EVSYS - Event System +--------------------------------------------------------------------------- +-*/ +- +-/* Event System */ +-typedef struct EVSYS_struct +-{ +- register8_t CH0MUX; /* Event Channel 0 Multiplexer */ +- register8_t CH1MUX; /* Event Channel 1 Multiplexer */ +- register8_t CH2MUX; /* Event Channel 2 Multiplexer */ +- register8_t CH3MUX; /* Event Channel 3 Multiplexer */ +- register8_t reserved_0x04; +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t CH0CTRL; /* Channel 0 Control Register */ +- register8_t CH1CTRL; /* Channel 1 Control Register */ +- register8_t CH2CTRL; /* Channel 2 Control Register */ +- register8_t CH3CTRL; /* Channel 3 Control Register */ +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t STROBE; /* Event Strobe */ +- register8_t DATA; /* Event Data */ +-} EVSYS_t; +- +-/* Quadrature Decoder Index Recognition Mode */ +-typedef enum EVSYS_QDIRM_enum +-{ +- EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ +- EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ +- EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ +- EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +-} EVSYS_QDIRM_t; +- +-/* Digital filter coefficient */ +-typedef enum EVSYS_DIGFILT_enum +-{ +- EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ +- EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ +- EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ +- EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ +- EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ +- EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ +- EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ +- EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +-} EVSYS_DIGFILT_t; +- +-/* Event Channel multiplexer input selection */ +-typedef enum EVSYS_CHMUX_enum +-{ +- EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ +- EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ +- EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ +- EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ +- EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ +- EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ +- EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ +- EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ +- EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ +- EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ +- EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ +- EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ +- EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ +- EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ +- EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ +- EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ +- EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ +- EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ +- EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ +- EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ +- EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ +- EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ +- EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ +- EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ +- EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ +- EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ +- EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ +- EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ +- EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ +- EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ +- EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ +- EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ +- EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ +- EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ +- EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ +- EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ +- EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ +- EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ +- EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ +- EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ +- EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ +- EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ +- EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ +- EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ +- EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ +- EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ +- EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ +- EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ +- EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ +- EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ +- EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ +- EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ +- EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ +- EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ +- EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ +- EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ +- EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ +- EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ +- EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ +- EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ +- EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ +- EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ +- EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ +- EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ +- EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ +- EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ +- EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ +- EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ +- EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ +- EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ +- EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ +- EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ +- EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ +- EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ +- EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ +- EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ +- EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ +- EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ +- EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ +- EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ +- EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ +- EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ +- EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ +- EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ +- EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ +- EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ +- EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ +- EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ +- EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ +- EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ +- EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ +- EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ +- EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ +- EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ +- EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ +- EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ +- EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ +- EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ +- EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ +- EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ +- EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +- EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ +- EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ +- EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ +- EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +-} EVSYS_CHMUX_t; +- +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Non-volatile Memory Controller */ +-typedef struct NVM_struct +-{ +- register8_t ADDR0; /* Address Register 0 */ +- register8_t ADDR1; /* Address Register 1 */ +- register8_t ADDR2; /* Address Register 2 */ +- register8_t reserved_0x03; +- register8_t DATA0; /* Data Register 0 */ +- register8_t DATA1; /* Data Register 1 */ +- register8_t DATA2; /* Data Register 2 */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t CMD; /* Command */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t INTCTRL; /* Interrupt Control */ +- register8_t reserved_0x0E; +- register8_t STATUS; /* Status */ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Lock Bits */ +-typedef struct NVM_LOCKBITS_struct +-{ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_LOCKBITS_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Fuses */ +-typedef struct NVM_FUSES_struct +-{ +- register8_t FUSEBYTE0; /* User ID */ +- register8_t FUSEBYTE1; /* Watchdog Configuration */ +- register8_t FUSEBYTE2; /* Reset Configuration */ +- register8_t reserved_0x03; +- register8_t FUSEBYTE4; /* Start-up Configuration */ +- register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +-} NVM_FUSES_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Production Signatures */ +-typedef struct NVM_PROD_SIGNATURES_struct +-{ +- register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ +- register8_t reserved_0x01; +- register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ +- register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ +- register8_t reserved_0x04; +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ +- register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ +- register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ +- register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ +- register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ +- register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t WAFNUM; /* Wafer Number */ +- register8_t reserved_0x11; +- register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ +- register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ +- register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ +- register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ +- register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ +- register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ +- register8_t reserved_0x26; +- register8_t reserved_0x27; +- register8_t reserved_0x28; +- register8_t reserved_0x29; +- register8_t reserved_0x2A; +- register8_t reserved_0x2B; +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ +- register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ +- register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ +- register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ +- register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ +- register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- register8_t reserved_0x36; +- register8_t reserved_0x37; +- register8_t reserved_0x38; +- register8_t reserved_0x39; +- register8_t reserved_0x3A; +- register8_t reserved_0x3B; +- register8_t reserved_0x3C; +- register8_t reserved_0x3D; +- register8_t reserved_0x3E; +-} NVM_PROD_SIGNATURES_t; +- +-/* NVM Command */ +-typedef enum NVM_CMD_enum +-{ +- NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ +- NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ +- NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ +- NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ +- NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ +- NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ +- NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ +- NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ +- NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ +- NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ +- NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ +- NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ +- NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ +- NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ +- NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ +- NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ +- NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ +- NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ +- NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ +- NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ +- NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ +- NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ +- NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ +- NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ +- NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ +- NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +-} NVM_CMD_t; +- +-/* SPM ready interrupt level */ +-typedef enum NVM_SPMLVL_enum +-{ +- NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ +- NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ +- NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +-} NVM_SPMLVL_t; +- +-/* EEPROM ready interrupt level */ +-typedef enum NVM_EELVL_enum +-{ +- NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ +- NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ +- NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +-} NVM_EELVL_t; +- +-/* Boot lock bits - boot setcion */ +-typedef enum NVM_BLBB_enum +-{ +- NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +- NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ +- NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ +- NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +-} NVM_BLBB_t; +- +-/* Boot lock bits - application section */ +-typedef enum NVM_BLBA_enum +-{ +- NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +- NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ +- NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ +- NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +-} NVM_BLBA_t; +- +-/* Boot lock bits - application table section */ +-typedef enum NVM_BLBAT_enum +-{ +- NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +- NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ +- NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ +- NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +-} NVM_BLBAT_t; +- +-/* Lock bits */ +-typedef enum NVM_LB_enum +-{ +- NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +- NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ +- NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +-} NVM_LB_t; +- +-/* Boot Loader Section Reset Vector */ +-typedef enum BOOTRST_enum +-{ +- BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ +- BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +-} BOOTRST_t; +- +-/* BOD operation */ +-typedef enum BOD_enum +-{ +- BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ +- BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ +- BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +-} BOD_t; +- +-/* Watchdog (Window) Timeout Period */ +-typedef enum WD_enum +-{ +- WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ +- WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ +- WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ +- WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ +- WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ +- WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ +- WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ +- WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ +- WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ +- WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ +- WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +-} WD_t; +- +-/* Start-up Time */ +-typedef enum SUT_enum +-{ +- SUT_0MS_gc = (0x03<<2), /* 0 ms */ +- SUT_4MS_gc = (0x01<<2), /* 4 ms */ +- SUT_64MS_gc = (0x00<<2), /* 64 ms */ +-} SUT_t; +- +-/* Brown Out Detection Voltage Level */ +-typedef enum BODLVL_enum +-{ +- BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ +- BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ +- BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ +- BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ +- BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ +- BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ +- BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ +-} BODLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-AC - Analog Comparator +--------------------------------------------------------------------------- +-*/ +- +-/* Analog Comparator */ +-typedef struct AC_struct +-{ +- register8_t AC0CTRL; /* Comparator 0 Control */ +- register8_t AC1CTRL; /* Comparator 1 Control */ +- register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ +- register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t WINCTRL; /* Window Mode Control */ +- register8_t STATUS; /* Status */ +-} AC_t; +- +-/* Interrupt mode */ +-typedef enum AC_INTMODE_enum +-{ +- AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ +- AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ +- AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +-} AC_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum AC_INTLVL_enum +-{ +- AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ +- AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ +- AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ +- AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +-} AC_INTLVL_t; +- +-/* Hysteresis mode selection */ +-typedef enum AC_HYSMODE_enum +-{ +- AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ +- AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ +- AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +-} AC_HYSMODE_t; +- +-/* Positive input multiplexer selection */ +-typedef enum AC_MUXPOS_enum +-{ +- AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ +- AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ +- AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ +- AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ +- AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ +- AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ +- AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +- AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +-} AC_MUXPOS_t; +- +-/* Negative input multiplexer selection */ +-typedef enum AC_MUXNEG_enum +-{ +- AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ +- AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ +- AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ +- AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ +- AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ +- AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ +- AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ +- AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +-} AC_MUXNEG_t; +- +-/* Windows interrupt mode */ +-typedef enum AC_WINTMODE_enum +-{ +- AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ +- AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ +- AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ +- AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +-} AC_WINTMODE_t; +- +-/* Window interrupt level */ +-typedef enum AC_WINTLVL_enum +-{ +- AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ +- AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ +- AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +-} AC_WINTLVL_t; +- +-/* Window mode state */ +-typedef enum AC_WSTATE_enum +-{ +- AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ +- AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ +- AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +-} AC_WSTATE_t; +- +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* ADC Channel */ +-typedef struct ADC_CH_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t MUXCTRL; /* MUX Control */ +- register8_t INTCTRL; /* Channel Interrupt Control */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- _WORDREGISTER(RES); /* Channel Result */ +- register8_t reserved_0x6; +- register8_t reserved_0x7; +-} ADC_CH_t; +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Analog-to-Digital Converter */ +-typedef struct ADC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t REFCTRL; /* Reference Control */ +- register8_t EVCTRL; /* Event Control */ +- register8_t PRESCALER; /* Clock Prescaler */ +- register8_t reserved_0x05; +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- _WORDREGISTER(CAL); /* Calibration Value */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- _WORDREGISTER(CH0RES); /* Channel 0 Result */ +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- _WORDREGISTER(CMP); /* Compare Value */ +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- ADC_CH_t CH0; /* ADC Channel 0 */ +-} ADC_t; +- +-/* Positive input multiplexer selection */ +-typedef enum ADC_CH_MUXPOS_enum +-{ +- ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ +- ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ +- ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ +- ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ +- ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ +- ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ +- ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ +- ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +-} ADC_CH_MUXPOS_t; +- +-/* Internal input multiplexer selections */ +-typedef enum ADC_CH_MUXINT_enum +-{ +- ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ +- ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ +- ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +- ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +-} ADC_CH_MUXINT_t; +- +-/* Negative input multiplexer selection */ +-typedef enum ADC_CH_MUXNEG_enum +-{ +- ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ +- ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ +- ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ +- ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ +- ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ +- ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ +- ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ +- ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +-} ADC_CH_MUXNEG_t; +- +-/* Input mode */ +-typedef enum ADC_CH_INPUTMODE_enum +-{ +- ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ +- ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ +- ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ +- ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +-} ADC_CH_INPUTMODE_t; +- +-/* Gain factor */ +-typedef enum ADC_CH_GAIN_enum +-{ +- ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ +- ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ +- ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ +- ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ +- ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ +- ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ +- ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ +-} ADC_CH_GAIN_t; +- +-/* Conversion result resolution */ +-typedef enum ADC_RESOLUTION_enum +-{ +- ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ +- ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ +- ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +-} ADC_RESOLUTION_t; +- +-/* Voltage reference selection */ +-typedef enum ADC_REFSEL_enum +-{ +- ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ +- ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ +- ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ +- ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +-} ADC_REFSEL_t; +- +-/* Channel sweep selection */ +-typedef enum ADC_SWEEP_enum +-{ +- ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ +-} ADC_SWEEP_t; +- +-/* Event channel input selection */ +-typedef enum ADC_EVSEL_enum +-{ +- ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ +- ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ +- ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ +- ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ +- ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ +- ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ +- ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ +- ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +-} ADC_EVSEL_t; +- +-/* Event action selection */ +-typedef enum ADC_EVACT_enum +-{ +- ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ +- ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ +-} ADC_EVACT_t; +- +-/* Interupt mode */ +-typedef enum ADC_CH_INTMODE_enum +-{ +- ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ +- ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ +- ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +-} ADC_CH_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum ADC_CH_INTLVL_enum +-{ +- ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ +- ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ +- ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +-} ADC_CH_INTLVL_t; +- +-/* Clock prescaler */ +-typedef enum ADC_PRESCALER_enum +-{ +- ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ +- ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ +- ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ +- ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ +- ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ +- ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ +- ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ +- ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +-} ADC_PRESCALER_t; +- +- +-/* +--------------------------------------------------------------------------- +-RTC - Real-Time Clounter +--------------------------------------------------------------------------- +-*/ +- +-/* Real-Time Counter */ +-typedef struct RTC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t TEMP; /* Temporary register */ +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- _WORDREGISTER(CNT); /* Count Register */ +- _WORDREGISTER(PER); /* Period Register */ +- _WORDREGISTER(COMP); /* Compare Register */ +-} RTC_t; +- +-/* Prescaler Factor */ +-typedef enum RTC_PRESCALER_enum +-{ +- RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ +- RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ +- RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ +- RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ +- RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ +- RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ +- RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ +- RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +-} RTC_PRESCALER_t; +- +-/* Compare Interrupt level */ +-typedef enum RTC_COMPINTLVL_enum +-{ +- RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} RTC_COMPINTLVL_t; +- +-/* Overflow Interrupt level */ +-typedef enum RTC_OVFINTLVL_enum +-{ +- RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} RTC_OVFINTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* EBI Chip Select Module */ +-typedef struct EBI_CS_struct +-{ +- register8_t CTRLA; /* Chip Select Control Register A */ +- register8_t CTRLB; /* Chip Select Control Register B */ +- _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +-} EBI_CS_t; +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* External Bus Interface */ +-typedef struct EBI_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t SDRAMCTRLA; /* SDRAM Control Register A */ +- register8_t reserved_0x02; +- register8_t reserved_0x03; +- _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ +- _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ +- register8_t SDRAMCTRLB; /* SDRAM Control Register B */ +- register8_t SDRAMCTRLC; /* SDRAM Control Register C */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- EBI_CS_t CS0; /* Chip Select 0 */ +- EBI_CS_t CS1; /* Chip Select 1 */ +- EBI_CS_t CS2; /* Chip Select 2 */ +- EBI_CS_t CS3; /* Chip Select 3 */ +-} EBI_t; +- +-/* Chip Select adress space */ +-typedef enum EBI_CS_ASIZE_enum +-{ +- EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ +- EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ +- EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ +- EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ +- EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ +- EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ +- EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ +- EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ +- EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ +- EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ +- EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ +- EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ +- EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ +- EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ +- EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ +- EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ +- EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +-} EBI_CS_ASIZE_t; +- +-/* */ +-typedef enum EBI_CS_SRWS_enum +-{ +- EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_CS_SRWS_t; +- +-/* Chip Select address mode */ +-typedef enum EBI_CS_MODE_enum +-{ +- EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ +- EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ +- EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ +- EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +-} EBI_CS_MODE_t; +- +-/* Chip Select SDRAM mode */ +-typedef enum EBI_CS_SDMODE_enum +-{ +- EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ +- EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +-} EBI_CS_SDMODE_t; +- +-/* */ +-typedef enum EBI_SDDATAW_enum +-{ +- EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ +- EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +-} EBI_SDDATAW_t; +- +-/* */ +-typedef enum EBI_LPCMODE_enum +-{ +- EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ +- EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +-} EBI_LPCMODE_t; +- +-/* */ +-typedef enum EBI_SRMODE_enum +-{ +- EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ +- EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ +- EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ +- EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +-} EBI_SRMODE_t; +- +-/* */ +-typedef enum EBI_IFMODE_enum +-{ +- EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ +- EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ +- EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ +- EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +-} EBI_IFMODE_t; +- +-/* */ +-typedef enum EBI_SDCOL_enum +-{ +- EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ +- EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ +- EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ +- EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +-} EBI_SDCOL_t; +- +-/* */ +-typedef enum EBI_MRDLY_enum +-{ +- EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_MRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCYCDLY_enum +-{ +- EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ROWCYCDLY_t; +- +-/* */ +-typedef enum EBI_RPDLY_enum +-{ +- EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_RPDLY_t; +- +-/* */ +-typedef enum EBI_WRDLY_enum +-{ +- EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_WRDLY_t; +- +-/* */ +-typedef enum EBI_ESRDLY_enum +-{ +- EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ESRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCOLDLY_enum +-{ +- EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_ROWCOLDLY_t; +- +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_MASTER_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t STATUS; /* Status Register */ +- register8_t BAUD; /* Baurd Rate Control Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +-} TWI_MASTER_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_SLAVE_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t STATUS; /* Status Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +- register8_t ADDRMASK; /* Address Mask Register */ +-} TWI_SLAVE_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Two-Wire Interface */ +-typedef struct TWI_struct +-{ +- register8_t CTRL; /* TWI Common Control Register */ +- TWI_MASTER_t MASTER; /* TWI master module */ +- TWI_SLAVE_t SLAVE; /* TWI slave module */ +-} TWI_t; +- +-/* Master Interrupt Level */ +-typedef enum TWI_MASTER_INTLVL_enum +-{ +- TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_MASTER_INTLVL_t; +- +-/* Inactive Timeout */ +-typedef enum TWI_MASTER_TIMEOUT_enum +-{ +- TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ +- TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ +- TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ +- TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +-} TWI_MASTER_TIMEOUT_t; +- +-/* Master Command */ +-typedef enum TWI_MASTER_CMD_enum +-{ +- TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ +- TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ +- TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +-} TWI_MASTER_CMD_t; +- +-/* Master Bus State */ +-typedef enum TWI_MASTER_BUSSTATE_enum +-{ +- TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ +- TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ +- TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ +- TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +-} TWI_MASTER_BUSSTATE_t; +- +-/* Slave Interrupt Level */ +-typedef enum TWI_SLAVE_INTLVL_enum +-{ +- TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_SLAVE_INTLVL_t; +- +-/* Slave Command */ +-typedef enum TWI_SLAVE_CMD_enum +-{ +- TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ +- TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +-} TWI_SLAVE_CMD_t; +- +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O port Configuration */ +-typedef struct PORTCFG_struct +-{ +- register8_t MPCMASK; /* Multi-pin Configuration Mask */ +- register8_t reserved_0x01; +- register8_t VPCTRLA; /* Virtual Port Control Register A */ +- register8_t VPCTRLB; /* Virtual Port Control Register B */ +- register8_t CLKEVOUT; /* Clock and Event Out Register */ +-} PORTCFG_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* Virtual Port */ +-typedef struct VPORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t OUT; /* I/O Port Output */ +- register8_t IN; /* I/O Port Input */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +-} VPORT_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O Ports */ +-typedef struct PORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t DIRSET; /* I/O Port Data Direction Set */ +- register8_t DIRCLR; /* I/O Port Data Direction Clear */ +- register8_t DIRTGL; /* I/O Port Data Direction Toggle */ +- register8_t OUT; /* I/O Port Output */ +- register8_t OUTSET; /* I/O Port Output Set */ +- register8_t OUTCLR; /* I/O Port Output Clear */ +- register8_t OUTTGL; /* I/O Port Output Toggle */ +- register8_t IN; /* I/O port Input */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INT0MASK; /* Port Interrupt 0 Mask */ +- register8_t INT1MASK; /* Port Interrupt 1 Mask */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t PIN0CTRL; /* Pin 0 Control Register */ +- register8_t PIN1CTRL; /* Pin 1 Control Register */ +- register8_t PIN2CTRL; /* Pin 2 Control Register */ +- register8_t PIN3CTRL; /* Pin 3 Control Register */ +- register8_t PIN4CTRL; /* Pin 4 Control Register */ +- register8_t PIN5CTRL; /* Pin 5 Control Register */ +- register8_t PIN6CTRL; /* Pin 6 Control Register */ +- register8_t PIN7CTRL; /* Pin 7 Control Register */ +-} PORT_t; +- +-/* Virtual Port 0 Mapping */ +-typedef enum PORTCFG_VP0MAP_enum +-{ +- PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP0MAP_t; +- +-/* Virtual Port 1 Mapping */ +-typedef enum PORTCFG_VP1MAP_enum +-{ +- PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP1MAP_t; +- +-/* Virtual Port 2 Mapping */ +-typedef enum PORTCFG_VP2MAP_enum +-{ +- PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP2MAP_t; +- +-/* Virtual Port 3 Mapping */ +-typedef enum PORTCFG_VP3MAP_enum +-{ +- PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP3MAP_t; +- +-/* Clock Output Port */ +-typedef enum PORTCFG_CLKOUT_enum +-{ +- PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ +- PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ +- PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ +- PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +-} PORTCFG_CLKOUT_t; +- +-/* Event Output Port */ +-typedef enum PORTCFG_EVOUT_enum +-{ +- PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ +- PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ +- PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ +- PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +-} PORTCFG_EVOUT_t; +- +-/* Port Interrupt 0 Level */ +-typedef enum PORT_INT0LVL_enum +-{ +- PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ +- PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ +- PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +-} PORT_INT0LVL_t; +- +-/* Port Interrupt 1 Level */ +-typedef enum PORT_INT1LVL_enum +-{ +- PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ +- PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ +- PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +-} PORT_INT1LVL_t; +- +-/* Output/Pull Configuration */ +-typedef enum PORT_OPC_enum +-{ +- PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ +- PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ +- PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ +- PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ +- PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ +- PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ +- PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ +- PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +-} PORT_OPC_t; +- +-/* Input/Sense Configuration */ +-typedef enum PORT_ISC_enum +-{ +- PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ +- PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ +- PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ +- PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ +- PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +-} PORT_ISC_t; +- +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 0 */ +-typedef struct TC0_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- _WORDREGISTER(CCC); /* Compare or Capture C */ +- _WORDREGISTER(CCD); /* Compare or Capture D */ +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +- _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ +- _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +-} TC0_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 1 */ +-typedef struct TC1_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t reserved_0x2E; +- register8_t reserved_0x2F; +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +-} TC1_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* Advanced Waveform Extension */ +-typedef struct AWEX_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t FDEMASK; /* Fault Detection Event Mask */ +- register8_t FDCTRL; /* Fault Detection Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x05; +- register8_t DTBOTH; /* Dead Time Both Sides */ +- register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ +- register8_t DTLS; /* Dead Time Low Side */ +- register8_t DTHS; /* Dead Time High Side */ +- register8_t DTLSBUF; /* Dead Time Low Side Buffer */ +- register8_t DTHSBUF; /* Dead Time High Side Buffer */ +- register8_t OUTOVEN; /* Output Override Enable */ +-} AWEX_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* High-Resolution Extension */ +-typedef struct HIRES_struct +-{ +- register8_t CTRLA; /* Control Register */ +-} HIRES_t; +- +-/* Clock Selection */ +-typedef enum TC_CLKSEL_enum +-{ +- TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ +- TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ +- TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ +- TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ +- TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ +- TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ +- TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ +- TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ +- TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_CLKSEL_t; +- +-/* Waveform Generation Mode */ +-typedef enum TC_WGMODE_enum +-{ +- TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ +- TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ +- TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ +- TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ +- TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ +- TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +-} TC_WGMODE_t; +- +-/* Event Action */ +-typedef enum TC_EVACT_enum +-{ +- TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ +- TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ +- TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ +- TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ +- TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ +- TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */ +- TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +-} TC_EVACT_t; +- +-/* Event Selection */ +-typedef enum TC_EVSEL_enum +-{ +- TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_EVSEL_t; +- +-/* Error Interrupt Level */ +-typedef enum TC_ERRINTLVL_enum +-{ +- TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_ERRINTLVL_t; +- +-/* Overflow Interrupt Level */ +-typedef enum TC_OVFINTLVL_enum +-{ +- TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_OVFINTLVL_t; +- +-/* Compare or Capture D Interrupt Level */ +-typedef enum TC_CCDINTLVL_enum +-{ +- TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TC_CCDINTLVL_t; +- +-/* Compare or Capture C Interrupt Level */ +-typedef enum TC_CCCINTLVL_enum +-{ +- TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} TC_CCCINTLVL_t; +- +-/* Compare or Capture B Interrupt Level */ +-typedef enum TC_CCBINTLVL_enum +-{ +- TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_CCBINTLVL_t; +- +-/* Compare or Capture A Interrupt Level */ +-typedef enum TC_CCAINTLVL_enum +-{ +- TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_CCAINTLVL_t; +- +-/* Timer/Counter Command */ +-typedef enum TC_CMD_enum +-{ +- TC_CMD_NONE_gc = (0x00<<2), /* No Command */ +- TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ +- TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ +- TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +-} TC_CMD_t; +- +-/* Fault Detect Action */ +-typedef enum AWEX_FDACT_enum +-{ +- AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ +- AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ +- AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +-} AWEX_FDACT_t; +- +-/* High Resolution Enable */ +-typedef enum HIRES_HREN_enum +-{ +- HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ +- HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ +- HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ +- HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +-} HIRES_HREN_t; +- +- +-/* +--------------------------------------------------------------------------- +-USART - Universal Asynchronous Receiver-Transmitter +--------------------------------------------------------------------------- +-*/ +- +-/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +-typedef struct USART_struct +-{ +- register8_t DATA; /* Data Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x02; +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t BAUDCTRLA; /* Baud Rate Control Register A */ +- register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +-} USART_t; +- +-/* Receive Complete Interrupt level */ +-typedef enum USART_RXCINTLVL_enum +-{ +- USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} USART_RXCINTLVL_t; +- +-/* Transmit Complete Interrupt level */ +-typedef enum USART_TXCINTLVL_enum +-{ +- USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} USART_TXCINTLVL_t; +- +-/* Data Register Empty Interrupt level */ +-typedef enum USART_DREINTLVL_enum +-{ +- USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} USART_DREINTLVL_t; +- +-/* Character Size */ +-typedef enum USART_CHSIZE_enum +-{ +- USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ +- USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ +- USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ +- USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ +- USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +-} USART_CHSIZE_t; +- +-/* Communication Mode */ +-typedef enum USART_CMODE_enum +-{ +- USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ +- USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ +- USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ +- USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +-} USART_CMODE_t; +- +-/* Parity Mode */ +-typedef enum USART_PMODE_enum +-{ +- USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ +- USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ +- USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +-} USART_PMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-SPI - Serial Peripheral Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Serial Peripheral Interface */ +-typedef struct SPI_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t DATA; /* Data Register */ +-} SPI_t; +- +-/* SPI Mode */ +-typedef enum SPI_MODE_enum +-{ +- SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ +- SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ +- SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ +- SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +-} SPI_MODE_t; +- +-/* Prescaler setting */ +-typedef enum SPI_PRESCALER_enum +-{ +- SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ +- SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ +- SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ +- SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +-} SPI_PRESCALER_t; +- +-/* Interrupt level */ +-typedef enum SPI_INTLVL_enum +-{ +- SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} SPI_INTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-IRCOM - IR Communication Module +--------------------------------------------------------------------------- +-*/ +- +-/* IR Communication Module */ +-typedef struct IRCOM_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ +- register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +-} IRCOM_t; +- +-/* Event channel selection */ +-typedef enum IRDA_EVSEL_enum +-{ +- IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ +- IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ +- IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ +- IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +- IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ +- IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ +- IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ +- IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +-} IRDA_EVSEL_t; +- +- +- +-/* +-========================================================================== +-IO Module Instances. Mapped to memory. +-========================================================================== +-*/ +- +-#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +-#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +-#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +-#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +-#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +-#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +-#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +-#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +-#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +-#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +-#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +-#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +-#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +-#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +-#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +-#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +-#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +-#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +-#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +-#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ +-#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +-#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +-#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +-#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +-#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +-#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +-#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +-#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +-#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +-#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +-#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +-#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +-#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +-#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +-#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +-#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +-#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +-#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +-#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +-#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +- +- +-#endif /* !defined (__ASSEMBLER__) */ +- +- +-/* ========== Flattened fully qualified IO register names ========== */ +- +-/* GPIO - General Purpose IO Registers */ +-#define GPIO_GPIO0 _SFR_MEM8(0x0000) +-#define GPIO_GPIO1 _SFR_MEM8(0x0001) +-#define GPIO_GPIO2 _SFR_MEM8(0x0002) +-#define GPIO_GPIO3 _SFR_MEM8(0x0003) +-#define GPIO_GPIO4 _SFR_MEM8(0x0004) +-#define GPIO_GPIO5 _SFR_MEM8(0x0005) +-#define GPIO_GPIO6 _SFR_MEM8(0x0006) +-#define GPIO_GPIO7 _SFR_MEM8(0x0007) +-#define GPIO_GPIO8 _SFR_MEM8(0x0008) +-#define GPIO_GPIO9 _SFR_MEM8(0x0009) +-#define GPIO_GPIOA _SFR_MEM8(0x000A) +-#define GPIO_GPIOB _SFR_MEM8(0x000B) +-#define GPIO_GPIOC _SFR_MEM8(0x000C) +-#define GPIO_GPIOD _SFR_MEM8(0x000D) +-#define GPIO_GPIOE _SFR_MEM8(0x000E) +-#define GPIO_GPIOF _SFR_MEM8(0x000F) +- +-/* VPORT0 - Virtual Port 0 */ +-#define VPORT0_DIR _SFR_MEM8(0x0010) +-#define VPORT0_OUT _SFR_MEM8(0x0011) +-#define VPORT0_IN _SFR_MEM8(0x0012) +-#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) +- +-/* VPORT1 - Virtual Port 1 */ +-#define VPORT1_DIR _SFR_MEM8(0x0014) +-#define VPORT1_OUT _SFR_MEM8(0x0015) +-#define VPORT1_IN _SFR_MEM8(0x0016) +-#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) +- +-/* VPORT2 - Virtual Port 2 */ +-#define VPORT2_DIR _SFR_MEM8(0x0018) +-#define VPORT2_OUT _SFR_MEM8(0x0019) +-#define VPORT2_IN _SFR_MEM8(0x001A) +-#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) +- +-/* VPORT3 - Virtual Port 3 */ +-#define VPORT3_DIR _SFR_MEM8(0x001C) +-#define VPORT3_OUT _SFR_MEM8(0x001D) +-#define VPORT3_IN _SFR_MEM8(0x001E) +-#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) +- +-/* OCD - On-Chip Debug System */ +-#define OCD_OCDR0 _SFR_MEM8(0x002E) +-#define OCD_OCDR1 _SFR_MEM8(0x002F) +- +-/* CPU - CPU Registers */ +-#define CPU_CCP _SFR_MEM8(0x0034) +-#define CPU_RAMPD _SFR_MEM8(0x0038) +-#define CPU_RAMPX _SFR_MEM8(0x0039) +-#define CPU_RAMPY _SFR_MEM8(0x003A) +-#define CPU_RAMPZ _SFR_MEM8(0x003B) +-#define CPU_EIND _SFR_MEM8(0x003C) +-#define CPU_SPL _SFR_MEM8(0x003D) +-#define CPU_SPH _SFR_MEM8(0x003E) +-#define CPU_SREG _SFR_MEM8(0x003F) +- +-/* CLK - Clock System */ +-#define CLK_CTRL _SFR_MEM8(0x0040) +-#define CLK_PSCTRL _SFR_MEM8(0x0041) +-#define CLK_LOCK _SFR_MEM8(0x0042) +-#define CLK_RTCCTRL _SFR_MEM8(0x0043) +- +-/* SLEEP - Sleep Controller */ +-#define SLEEP_CTRL _SFR_MEM8(0x0048) +- +-/* OSC - Oscillator Control */ +-#define OSC_CTRL _SFR_MEM8(0x0050) +-#define OSC_STATUS _SFR_MEM8(0x0051) +-#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +-#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +-#define OSC_RC32KCAL _SFR_MEM8(0x0054) +-#define OSC_PLLCTRL _SFR_MEM8(0x0055) +-#define OSC_DFLLCTRL _SFR_MEM8(0x0056) +- +-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +-#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +-#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +-#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +-#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +-#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +-#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) +- +-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +-#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +-#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +-#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +-#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +-#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +-#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) +- +-/* PR - Power Reduction */ +-#define PR_PRGEN _SFR_MEM8(0x0070) +-#define PR_PRPA _SFR_MEM8(0x0071) +-#define PR_PRPB _SFR_MEM8(0x0072) +-#define PR_PRPC _SFR_MEM8(0x0073) +-#define PR_PRPD _SFR_MEM8(0x0074) +-#define PR_PRPE _SFR_MEM8(0x0075) +-#define PR_PRPF _SFR_MEM8(0x0076) +- +-/* RST - Reset Controller */ +-#define RST_STATUS _SFR_MEM8(0x0078) +-#define RST_CTRL _SFR_MEM8(0x0079) +- +-/* WDT - Watch-Dog Timer */ +-#define WDT_CTRL _SFR_MEM8(0x0080) +-#define WDT_WINCTRL _SFR_MEM8(0x0081) +-#define WDT_STATUS _SFR_MEM8(0x0082) +- +-/* MCU - MCU Control */ +-#define MCU_DEVID0 _SFR_MEM8(0x0090) +-#define MCU_DEVID1 _SFR_MEM8(0x0091) +-#define MCU_DEVID2 _SFR_MEM8(0x0092) +-#define MCU_REVID _SFR_MEM8(0x0093) +-#define MCU_JTAGUID _SFR_MEM8(0x0094) +-#define MCU_MCUCR _SFR_MEM8(0x0096) +-#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +-#define MCU_AWEXLOCK _SFR_MEM8(0x0099) +- +-/* PMIC - Programmable Interrupt Controller */ +-#define PMIC_STATUS _SFR_MEM8(0x00A0) +-#define PMIC_INTPRI _SFR_MEM8(0x00A1) +-#define PMIC_CTRL _SFR_MEM8(0x00A2) +- +-/* PORTCFG - Port Configuration */ +-#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +-#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +-#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +-#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +- +-/* EVSYS - Event System */ +-#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +-#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +-#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +-#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +-#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +-#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +-#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +-#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +-#define EVSYS_STROBE _SFR_MEM8(0x0190) +-#define EVSYS_DATA _SFR_MEM8(0x0191) +- +-/* NVM - Non Volatile Memory Controller */ +-#define NVM_ADDR0 _SFR_MEM8(0x01C0) +-#define NVM_ADDR1 _SFR_MEM8(0x01C1) +-#define NVM_ADDR2 _SFR_MEM8(0x01C2) +-#define NVM_DATA0 _SFR_MEM8(0x01C4) +-#define NVM_DATA1 _SFR_MEM8(0x01C5) +-#define NVM_DATA2 _SFR_MEM8(0x01C6) +-#define NVM_CMD _SFR_MEM8(0x01CA) +-#define NVM_CTRLA _SFR_MEM8(0x01CB) +-#define NVM_CTRLB _SFR_MEM8(0x01CC) +-#define NVM_INTCTRL _SFR_MEM8(0x01CD) +-#define NVM_STATUS _SFR_MEM8(0x01CF) +-#define NVM_LOCKBITS _SFR_MEM8(0x01D0) +- +-/* ADCA - Analog to Digital Converter A */ +-#define ADCA_CTRLA _SFR_MEM8(0x0200) +-#define ADCA_CTRLB _SFR_MEM8(0x0201) +-#define ADCA_REFCTRL _SFR_MEM8(0x0202) +-#define ADCA_EVCTRL _SFR_MEM8(0x0203) +-#define ADCA_PRESCALER _SFR_MEM8(0x0204) +-#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +-#define ADCA_CAL _SFR_MEM16(0x020C) +-#define ADCA_CH0RES _SFR_MEM16(0x0210) +-#define ADCA_CMP _SFR_MEM16(0x0218) +-#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +-#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +-#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +-#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +-#define ADCA_CH0_RES _SFR_MEM16(0x0224) +- +-/* DACB - Digital to Analog Converter B */ +- +-/* ACA - Analog Comparator A */ +-#define ACA_AC0CTRL _SFR_MEM8(0x0380) +-#define ACA_AC1CTRL _SFR_MEM8(0x0381) +-#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +-#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +-#define ACA_CTRLA _SFR_MEM8(0x0384) +-#define ACA_CTRLB _SFR_MEM8(0x0385) +-#define ACA_WINCTRL _SFR_MEM8(0x0386) +-#define ACA_STATUS _SFR_MEM8(0x0387) +- +-/* RTC - Real-Time Counter */ +-#define RTC_CTRL _SFR_MEM8(0x0400) +-#define RTC_STATUS _SFR_MEM8(0x0401) +-#define RTC_INTCTRL _SFR_MEM8(0x0402) +-#define RTC_INTFLAGS _SFR_MEM8(0x0403) +-#define RTC_TEMP _SFR_MEM8(0x0404) +-#define RTC_CNT _SFR_MEM16(0x0408) +-#define RTC_PER _SFR_MEM16(0x040A) +-#define RTC_COMP _SFR_MEM16(0x040C) +- +-/* TWIC - Two-Wire Interface C */ +-#define TWIC_CTRL _SFR_MEM8(0x0480) +-#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +-#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +-#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +-#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +-#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +-#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +-#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +-#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +-#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +-#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +-#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +-#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +-#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) +- +-/* PORTA - Port A */ +-#define PORTA_DIR _SFR_MEM8(0x0600) +-#define PORTA_DIRSET _SFR_MEM8(0x0601) +-#define PORTA_DIRCLR _SFR_MEM8(0x0602) +-#define PORTA_DIRTGL _SFR_MEM8(0x0603) +-#define PORTA_OUT _SFR_MEM8(0x0604) +-#define PORTA_OUTSET _SFR_MEM8(0x0605) +-#define PORTA_OUTCLR _SFR_MEM8(0x0606) +-#define PORTA_OUTTGL _SFR_MEM8(0x0607) +-#define PORTA_IN _SFR_MEM8(0x0608) +-#define PORTA_INTCTRL _SFR_MEM8(0x0609) +-#define PORTA_INT0MASK _SFR_MEM8(0x060A) +-#define PORTA_INT1MASK _SFR_MEM8(0x060B) +-#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +-#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +-#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +-#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +-#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +-#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +-#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +-#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +-#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) +- +-/* PORTB - Port B */ +-#define PORTB_DIR _SFR_MEM8(0x0620) +-#define PORTB_DIRSET _SFR_MEM8(0x0621) +-#define PORTB_DIRCLR _SFR_MEM8(0x0622) +-#define PORTB_DIRTGL _SFR_MEM8(0x0623) +-#define PORTB_OUT _SFR_MEM8(0x0624) +-#define PORTB_OUTSET _SFR_MEM8(0x0625) +-#define PORTB_OUTCLR _SFR_MEM8(0x0626) +-#define PORTB_OUTTGL _SFR_MEM8(0x0627) +-#define PORTB_IN _SFR_MEM8(0x0628) +-#define PORTB_INTCTRL _SFR_MEM8(0x0629) +-#define PORTB_INT0MASK _SFR_MEM8(0x062A) +-#define PORTB_INT1MASK _SFR_MEM8(0x062B) +-#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +-#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +-#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +-#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +-#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +-#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +-#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +-#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +-#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) +- +-/* PORTC - Port C */ +-#define PORTC_DIR _SFR_MEM8(0x0640) +-#define PORTC_DIRSET _SFR_MEM8(0x0641) +-#define PORTC_DIRCLR _SFR_MEM8(0x0642) +-#define PORTC_DIRTGL _SFR_MEM8(0x0643) +-#define PORTC_OUT _SFR_MEM8(0x0644) +-#define PORTC_OUTSET _SFR_MEM8(0x0645) +-#define PORTC_OUTCLR _SFR_MEM8(0x0646) +-#define PORTC_OUTTGL _SFR_MEM8(0x0647) +-#define PORTC_IN _SFR_MEM8(0x0648) +-#define PORTC_INTCTRL _SFR_MEM8(0x0649) +-#define PORTC_INT0MASK _SFR_MEM8(0x064A) +-#define PORTC_INT1MASK _SFR_MEM8(0x064B) +-#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +-#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +-#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +-#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +-#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +-#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +-#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +-#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +-#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) +- +-/* PORTD - Port D */ +-#define PORTD_DIR _SFR_MEM8(0x0660) +-#define PORTD_DIRSET _SFR_MEM8(0x0661) +-#define PORTD_DIRCLR _SFR_MEM8(0x0662) +-#define PORTD_DIRTGL _SFR_MEM8(0x0663) +-#define PORTD_OUT _SFR_MEM8(0x0664) +-#define PORTD_OUTSET _SFR_MEM8(0x0665) +-#define PORTD_OUTCLR _SFR_MEM8(0x0666) +-#define PORTD_OUTTGL _SFR_MEM8(0x0667) +-#define PORTD_IN _SFR_MEM8(0x0668) +-#define PORTD_INTCTRL _SFR_MEM8(0x0669) +-#define PORTD_INT0MASK _SFR_MEM8(0x066A) +-#define PORTD_INT1MASK _SFR_MEM8(0x066B) +-#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +-#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +-#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +-#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +-#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +-#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +-#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +-#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +-#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) +- +-/* PORTE - Port E */ +-#define PORTE_DIR _SFR_MEM8(0x0680) +-#define PORTE_DIRSET _SFR_MEM8(0x0681) +-#define PORTE_DIRCLR _SFR_MEM8(0x0682) +-#define PORTE_DIRTGL _SFR_MEM8(0x0683) +-#define PORTE_OUT _SFR_MEM8(0x0684) +-#define PORTE_OUTSET _SFR_MEM8(0x0685) +-#define PORTE_OUTCLR _SFR_MEM8(0x0686) +-#define PORTE_OUTTGL _SFR_MEM8(0x0687) +-#define PORTE_IN _SFR_MEM8(0x0688) +-#define PORTE_INTCTRL _SFR_MEM8(0x0689) +-#define PORTE_INT0MASK _SFR_MEM8(0x068A) +-#define PORTE_INT1MASK _SFR_MEM8(0x068B) +-#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +-#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +-#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +-#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +-#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +-#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +-#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +-#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +-#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) +- +-/* PORTR - Port R */ +-#define PORTR_DIR _SFR_MEM8(0x07E0) +-#define PORTR_DIRSET _SFR_MEM8(0x07E1) +-#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +-#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +-#define PORTR_OUT _SFR_MEM8(0x07E4) +-#define PORTR_OUTSET _SFR_MEM8(0x07E5) +-#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +-#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +-#define PORTR_IN _SFR_MEM8(0x07E8) +-#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +-#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +-#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +-#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +-#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +-#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +-#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +-#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +-#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +-#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +-#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +-#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) +- +-/* TCC0 - Timer/Counter C0 */ +-#define TCC0_CTRLA _SFR_MEM8(0x0800) +-#define TCC0_CTRLB _SFR_MEM8(0x0801) +-#define TCC0_CTRLC _SFR_MEM8(0x0802) +-#define TCC0_CTRLD _SFR_MEM8(0x0803) +-#define TCC0_CTRLE _SFR_MEM8(0x0804) +-#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +-#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +-#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +-#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +-#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +-#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +-#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +-#define TCC0_TEMP _SFR_MEM8(0x080F) +-#define TCC0_CNT _SFR_MEM16(0x0820) +-#define TCC0_PER _SFR_MEM16(0x0826) +-#define TCC0_CCA _SFR_MEM16(0x0828) +-#define TCC0_CCB _SFR_MEM16(0x082A) +-#define TCC0_CCC _SFR_MEM16(0x082C) +-#define TCC0_CCD _SFR_MEM16(0x082E) +-#define TCC0_PERBUF _SFR_MEM16(0x0836) +-#define TCC0_CCABUF _SFR_MEM16(0x0838) +-#define TCC0_CCBBUF _SFR_MEM16(0x083A) +-#define TCC0_CCCBUF _SFR_MEM16(0x083C) +-#define TCC0_CCDBUF _SFR_MEM16(0x083E) +- +-/* TCC1 - Timer/Counter C1 */ +-#define TCC1_CTRLA _SFR_MEM8(0x0840) +-#define TCC1_CTRLB _SFR_MEM8(0x0841) +-#define TCC1_CTRLC _SFR_MEM8(0x0842) +-#define TCC1_CTRLD _SFR_MEM8(0x0843) +-#define TCC1_CTRLE _SFR_MEM8(0x0844) +-#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +-#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +-#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +-#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +-#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +-#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +-#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +-#define TCC1_TEMP _SFR_MEM8(0x084F) +-#define TCC1_CNT _SFR_MEM16(0x0860) +-#define TCC1_PER _SFR_MEM16(0x0866) +-#define TCC1_CCA _SFR_MEM16(0x0868) +-#define TCC1_CCB _SFR_MEM16(0x086A) +-#define TCC1_PERBUF _SFR_MEM16(0x0876) +-#define TCC1_CCABUF _SFR_MEM16(0x0878) +-#define TCC1_CCBBUF _SFR_MEM16(0x087A) +- +-/* AWEXC - Advanced Waveform Extension C */ +-#define AWEXC_CTRL _SFR_MEM8(0x0880) +-#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +-#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +-#define AWEXC_STATUS _SFR_MEM8(0x0884) +-#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +-#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +-#define AWEXC_DTLS _SFR_MEM8(0x0888) +-#define AWEXC_DTHS _SFR_MEM8(0x0889) +-#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +-#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +-#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) +- +-/* HIRESC - High-Resolution Extension C */ +-#define HIRESC_CTRLA _SFR_MEM8(0x0890) +- +-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +-#define USARTC0_DATA _SFR_MEM8(0x08A0) +-#define USARTC0_STATUS _SFR_MEM8(0x08A1) +-#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +-#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +-#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +-#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +-#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) +- +-/* SPIC - Serial Peripheral Interface C */ +-#define SPIC_CTRL _SFR_MEM8(0x08C0) +-#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +-#define SPIC_STATUS _SFR_MEM8(0x08C2) +-#define SPIC_DATA _SFR_MEM8(0x08C3) +- +-/* IRCOM - IR Communication Module */ +-#define IRCOM_CTRL _SFR_MEM8(0x08F8) +-#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +-#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) +- +-/* TCD0 - Timer/Counter D0 */ +-#define TCD0_CTRLA _SFR_MEM8(0x0900) +-#define TCD0_CTRLB _SFR_MEM8(0x0901) +-#define TCD0_CTRLC _SFR_MEM8(0x0902) +-#define TCD0_CTRLD _SFR_MEM8(0x0903) +-#define TCD0_CTRLE _SFR_MEM8(0x0904) +-#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +-#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +-#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +-#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +-#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +-#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +-#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +-#define TCD0_TEMP _SFR_MEM8(0x090F) +-#define TCD0_CNT _SFR_MEM16(0x0920) +-#define TCD0_PER _SFR_MEM16(0x0926) +-#define TCD0_CCA _SFR_MEM16(0x0928) +-#define TCD0_CCB _SFR_MEM16(0x092A) +-#define TCD0_CCC _SFR_MEM16(0x092C) +-#define TCD0_CCD _SFR_MEM16(0x092E) +-#define TCD0_PERBUF _SFR_MEM16(0x0936) +-#define TCD0_CCABUF _SFR_MEM16(0x0938) +-#define TCD0_CCBBUF _SFR_MEM16(0x093A) +-#define TCD0_CCCBUF _SFR_MEM16(0x093C) +-#define TCD0_CCDBUF _SFR_MEM16(0x093E) +- +-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +-#define USARTD0_DATA _SFR_MEM8(0x09A0) +-#define USARTD0_STATUS _SFR_MEM8(0x09A1) +-#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +-#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +-#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +-#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +-#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) +- +-/* SPID - Serial Peripheral Interface D */ +-#define SPID_CTRL _SFR_MEM8(0x09C0) +-#define SPID_INTCTRL _SFR_MEM8(0x09C1) +-#define SPID_STATUS _SFR_MEM8(0x09C2) +-#define SPID_DATA _SFR_MEM8(0x09C3) +- +-/* TCE0 - Timer/Counter E0 */ +-#define TCE0_CTRLA _SFR_MEM8(0x0A00) +-#define TCE0_CTRLB _SFR_MEM8(0x0A01) +-#define TCE0_CTRLC _SFR_MEM8(0x0A02) +-#define TCE0_CTRLD _SFR_MEM8(0x0A03) +-#define TCE0_CTRLE _SFR_MEM8(0x0A04) +-#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +-#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +-#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +-#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +-#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +-#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +-#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +-#define TCE0_TEMP _SFR_MEM8(0x0A0F) +-#define TCE0_CNT _SFR_MEM16(0x0A20) +-#define TCE0_PER _SFR_MEM16(0x0A26) +-#define TCE0_CCA _SFR_MEM16(0x0A28) +-#define TCE0_CCB _SFR_MEM16(0x0A2A) +-#define TCE0_CCC _SFR_MEM16(0x0A2C) +-#define TCE0_CCD _SFR_MEM16(0x0A2E) +-#define TCE0_PERBUF _SFR_MEM16(0x0A36) +-#define TCE0_CCABUF _SFR_MEM16(0x0A38) +-#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +-#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +-#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) +- +- +- +-/*================== Bitfield Definitions ================== */ +- +-/* XOCD - On-Chip Debug System */ +-/* OCD.OCDR1 bit masks and bit positions */ +-#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +-#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ +- +- +-/* CPU - CPU */ +-/* CPU.CCP bit masks and bit positions */ +-#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +-#define CPU_CCP_gp 0 /* CCP signature group position. */ +-#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +-#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +-#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +-#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +-#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +-#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +-#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +-#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +-#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +-#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +-#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +-#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +-#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +-#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +-#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +-#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ +- +- +-/* CPU.SREG bit masks and bit positions */ +-#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +-#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ +- +-#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +-#define CPU_T_bp 6 /* Transfer Bit bit position. */ +- +-#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +-#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +- +-#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +-#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +- +-#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +-#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +- +-#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +-#define CPU_N_bp 2 /* Negative Flag bit position. */ +- +-#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +-#define CPU_Z_bp 1 /* Zero Flag bit position. */ +- +-#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +-#define CPU_C_bp 0 /* Carry Flag bit position. */ +- +- +-/* CLK - Clock System */ +-/* CLK.CTRL bit masks and bit positions */ +-#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +-#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +-#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +-#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +-#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +-#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +-#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +-#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ +- +- +-/* CLK.PSCTRL bit masks and bit positions */ +-#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +-#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +-#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +-#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +-#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +-#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +-#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +-#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +-#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +-#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +-#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +-#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ +- +-#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +-#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +-#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +-#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +-#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +-#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ +- +- +-/* CLK.LOCK bit masks and bit positions */ +-#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +-#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ +- +- +-/* CLK.RTCCTRL bit masks and bit positions */ +-#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +-#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +-#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +-#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +-#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +-#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +-#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +-#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ +- +-#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +-#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ +- +- +-/* PR.PRGEN bit masks and bit positions */ +-#define PR_AES_bm 0x10 /* AES bit mask. */ +-#define PR_AES_bp 4 /* AES bit position. */ +- +-#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +-#define PR_EBI_bp 3 /* External Bus Interface bit position. */ +- +-#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +-#define PR_RTC_bp 2 /* Real-time Counter bit position. */ +- +-#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +-#define PR_EVSYS_bp 1 /* Event System bit position. */ +- +-#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +-#define PR_DMA_bp 0 /* DMA-Controller bit position. */ +- +- +-/* PR.PRPA bit masks and bit positions */ +-#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +-#define PR_DAC_bp 2 /* Port A DAC bit position. */ +- +-#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +-#define PR_ADC_bp 1 /* Port A ADC bit position. */ +- +-#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +-#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ +- +- +-/* PR.PRPB bit masks and bit positions */ +-/* PR_DAC_bm Predefined. */ +-/* PR_DAC_bp Predefined. */ +- +-/* PR_ADC_bm Predefined. */ +-/* PR_ADC_bp Predefined. */ +- +-/* PR_AC_bm Predefined. */ +-/* PR_AC_bp Predefined. */ +- +- +-/* PR.PRPC bit masks and bit positions */ +-#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +-#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ +- +-#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +-#define PR_USART1_bp 5 /* Port C USART1 bit position. */ +- +-#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +-#define PR_USART0_bp 4 /* Port C USART0 bit position. */ +- +-#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +-#define PR_SPI_bp 3 /* Port C SPI bit position. */ +- +-#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +-#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ +- +-#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +-#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ +- +-#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +-#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ +- +- +-/* PR.PRPD bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* PR.PRPE bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* PR.PRPF bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* SLEEP - Sleep Controller */ +-/* SLEEP.CTRL bit masks and bit positions */ +-#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +-#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +-#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +-#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +-#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +-#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +-#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +-#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ +- +-#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +-#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ +- +- +-/* OSC - Oscillator */ +-/* OSC.CTRL bit masks and bit positions */ +-#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +-#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ +- +-#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +-#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ +- +-#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ +- +- +-/* OSC.STATUS bit masks and bit positions */ +-#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +-#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ +- +-#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +-#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ +- +-#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ +- +- +-/* OSC.XOSCCTRL bit masks and bit positions */ +-#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +-#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +-#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +-#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +-#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +-#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ +- +-#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +-#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ +- +-#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +-#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +-#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +-#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +-#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +-#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +-#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +-#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +-#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +-#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +- +- +-/* OSC.XOSCFAIL bit masks and bit positions */ +-#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +-#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ +- +-#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +-#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ +- +- +-/* OSC.PLLCTRL bit masks and bit positions */ +-#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +-#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +-#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +-#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +-#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +-#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ +- +-#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +-#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +-#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +-#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +-#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +-#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +-#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +-#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +-#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +-#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +-#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +-#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ +- +- +-/* OSC.DFLLCTRL bit masks and bit positions */ +-#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +-#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ +- +-#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +-#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ +- +- +-/* DFLL - DFLL */ +-/* DFLL.CTRL bit masks and bit positions */ +-#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +-#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ +- +- +-/* DFLL.CALA bit masks and bit positions */ +-#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +-#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +-#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +-#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +-#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +-#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +-#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +-#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +-#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +-#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +-#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +-#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +-#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +-#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +-#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +-#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ +- +- +-/* DFLL.CALB bit masks and bit positions */ +-#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +-#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +-#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +-#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +-#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +-#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +-#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +-#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +-#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +-#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +-#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +-#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +-#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +-#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ +- +- +-/* RST - Reset */ +-/* RST.STATUS bit masks and bit positions */ +-#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +-#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ +- +-#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +-#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ +- +-#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +-#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ +- +-#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +-#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ +- +-#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +-#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ +- +-#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +-#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ +- +-#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +-#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ +- +- +-/* RST.CTRL bit masks and bit positions */ +-#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +-#define RST_SWRST_bp 0 /* Software Reset bit position. */ +- +- +-/* WDT - Watch-Dog Timer */ +-/* WDT.CTRL bit masks and bit positions */ +-#define WDT_PER_gm 0x3C /* Period group mask. */ +-#define WDT_PER_gp 2 /* Period group position. */ +-#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +-#define WDT_PER0_bp 2 /* Period bit 0 position. */ +-#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +-#define WDT_PER1_bp 3 /* Period bit 1 position. */ +-#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +-#define WDT_PER2_bp 4 /* Period bit 2 position. */ +-#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +-#define WDT_PER3_bp 5 /* Period bit 3 position. */ +- +-#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +-#define WDT_ENABLE_bp 1 /* Enable bit position. */ +- +-#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +-#define WDT_CEN_bp 0 /* Change Enable bit position. */ +- +- +-/* WDT.WINCTRL bit masks and bit positions */ +-#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +-#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +-#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +-#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +-#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +-#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +-#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +-#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +-#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +-#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ +- +-#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +-#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ +- +-#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +-#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ +- +- +-/* WDT.STATUS bit masks and bit positions */ +-#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +-#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +- +- +-/* MCU - MCU Control */ +-/* MCU.MCUCR bit masks and bit positions */ +-#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +-#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ +- +- +-/* MCU.EVSYSLOCK bit masks and bit positions */ +-#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +-#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ +- +-#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +-#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ +- +- +-/* MCU.AWEXLOCK bit masks and bit positions */ +-#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +-#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ +- +-#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +-#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ +- +- +-/* PMIC - Programmable Multi-level Interrupt Controller */ +-/* PMIC.STATUS bit masks and bit positions */ +-#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +-#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ +- +-#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +-#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ +- +-#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +-#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ +- +-#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +-#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ +- +- +-/* PMIC.CTRL bit masks and bit positions */ +-#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +-#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ +- +-#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +-#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ +- +-#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +-#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ +- +-#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +-#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ +- +-#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +-#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ +- +- +-/* EVSYS - Event System */ +-/* EVSYS.CH0MUX bit masks and bit positions */ +-#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +-#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +-#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +-#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +-#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +-#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +-#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +-#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +-#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +-#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +-#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +-#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +-#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +-#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +-#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +-#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +-#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +-#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ +- +- +-/* EVSYS.CH1MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH2MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH3MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH0CTRL bit masks and bit positions */ +-#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +-#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +-#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +-#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +-#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +-#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ +- +-#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +-#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ +- +-#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +-#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ +- +-#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +-#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +-#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +-#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +-#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +-#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +-#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +-#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ +- +- +-/* EVSYS.CH1CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH2CTRL bit masks and bit positions */ +-/* EVSYS_QDIRM_gm Predefined. */ +-/* EVSYS_QDIRM_gp Predefined. */ +-/* EVSYS_QDIRM0_bm Predefined. */ +-/* EVSYS_QDIRM0_bp Predefined. */ +-/* EVSYS_QDIRM1_bm Predefined. */ +-/* EVSYS_QDIRM1_bp Predefined. */ +- +-/* EVSYS_QDIEN_bm Predefined. */ +-/* EVSYS_QDIEN_bp Predefined. */ +- +-/* EVSYS_QDEN_bm Predefined. */ +-/* EVSYS_QDEN_bp Predefined. */ +- +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH3CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* NVM - Non Volatile Memory Controller */ +-/* NVM.CMD bit masks and bit positions */ +-#define NVM_CMD_gm 0xFF /* Command group mask. */ +-#define NVM_CMD_gp 0 /* Command group position. */ +-#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +-#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +-#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +-#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +-#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +-#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +-#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +-#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +-#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +-#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +-#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +-#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +-#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +-#define NVM_CMD7_bp 7 /* Command bit 7 position. */ +- +- +-/* NVM.CTRLA bit masks and bit positions */ +-#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +-#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ +- +- +-/* NVM.CTRLB bit masks and bit positions */ +-#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +-#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ +- +-#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +-#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ +- +-#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +-#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ +- +-#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +-#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ +- +- +-/* NVM.INTCTRL bit masks and bit positions */ +-#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +-#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +-#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +-#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +-#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +-#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ +- +-#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +-#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +-#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +-#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +-#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +-#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ +- +- +-/* NVM.STATUS bit masks and bit positions */ +-#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +-#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ +- +-#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +-#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ +- +-#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +-#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ +- +-#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +-#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ +- +- +-/* NVM.LOCKBITS bit masks and bit positions */ +-#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +-#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +-#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ +-#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ +-#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ +-#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ +-#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ +-#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ +-#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ +-#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ +-#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ +-#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ +-#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ +-#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ +-#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ +-#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ +-#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ +-#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ +-#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ +-#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +-#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +-#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +-#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ +- +-#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +-#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +-#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +-#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +-#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ +- +-#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +-#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ +- +-#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +-#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +-#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +-#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +-#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +-#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +-#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +-#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +-#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +-#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +-#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +-#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ +- +-#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +-#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ +- +- +-/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +-#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +-#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +-#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +-#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +-#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +-#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ +- +-#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +-#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ +- +-#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +-#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +-#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +-#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +-#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +-#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +-#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +-#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +- +- +-/* AC - Analog Comparator */ +-/* AC.AC0CTRL bit masks and bit positions */ +-#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +-#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +-#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +-#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +-#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +-#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ +- +-#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +-#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +-#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +-#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +-#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +-#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ +- +-#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +-#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ +- +-#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +-#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +-#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +-#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +-#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +-#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +- +-#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define AC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* AC.AC1CTRL bit masks and bit positions */ +-/* AC_INTMODE_gm Predefined. */ +-/* AC_INTMODE_gp Predefined. */ +-/* AC_INTMODE0_bm Predefined. */ +-/* AC_INTMODE0_bp Predefined. */ +-/* AC_INTMODE1_bm Predefined. */ +-/* AC_INTMODE1_bp Predefined. */ +- +-/* AC_INTLVL_gm Predefined. */ +-/* AC_INTLVL_gp Predefined. */ +-/* AC_INTLVL0_bm Predefined. */ +-/* AC_INTLVL0_bp Predefined. */ +-/* AC_INTLVL1_bm Predefined. */ +-/* AC_INTLVL1_bp Predefined. */ +- +-/* AC_HSMODE_bm Predefined. */ +-/* AC_HSMODE_bp Predefined. */ +- +-/* AC_HYSMODE_gm Predefined. */ +-/* AC_HYSMODE_gp Predefined. */ +-/* AC_HYSMODE0_bm Predefined. */ +-/* AC_HYSMODE0_bp Predefined. */ +-/* AC_HYSMODE1_bm Predefined. */ +-/* AC_HYSMODE1_bp Predefined. */ +- +-/* AC_ENABLE_bm Predefined. */ +-/* AC_ENABLE_bp Predefined. */ +- +- +-/* AC.AC0MUXCTRL bit masks and bit positions */ +-#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +-#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +-#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +-#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +-#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +-#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +-#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +-#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ +- +-#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +-#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +-#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +-#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +-#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +-#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +-#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +-#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ +- +- +-/* AC.AC1MUXCTRL bit masks and bit positions */ +-/* AC_MUXPOS_gm Predefined. */ +-/* AC_MUXPOS_gp Predefined. */ +-/* AC_MUXPOS0_bm Predefined. */ +-/* AC_MUXPOS0_bp Predefined. */ +-/* AC_MUXPOS1_bm Predefined. */ +-/* AC_MUXPOS1_bp Predefined. */ +-/* AC_MUXPOS2_bm Predefined. */ +-/* AC_MUXPOS2_bp Predefined. */ +- +-/* AC_MUXNEG_gm Predefined. */ +-/* AC_MUXNEG_gp Predefined. */ +-/* AC_MUXNEG0_bm Predefined. */ +-/* AC_MUXNEG0_bp Predefined. */ +-/* AC_MUXNEG1_bm Predefined. */ +-/* AC_MUXNEG1_bp Predefined. */ +-/* AC_MUXNEG2_bm Predefined. */ +-/* AC_MUXNEG2_bp Predefined. */ +- +- +-/* AC.CTRLA bit masks and bit positions */ +-#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +-#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ +- +- +-/* AC.CTRLB bit masks and bit positions */ +-#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +-#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +-#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +-#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +-#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +-#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +-#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +-#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +-#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +-#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +-#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +-#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +-#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +-#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ +- +- +-/* AC.WINCTRL bit masks and bit positions */ +-#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +-#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ +- +-#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +-#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +-#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +-#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +-#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +-#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ +- +-#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +-#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +-#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +-#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +-#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +-#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ +- +- +-/* AC.STATUS bit masks and bit positions */ +-#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +-#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +-#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +-#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +-#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +-#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ +- +-#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +-#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ +- +-#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +-#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ +- +-#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +-#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ +- +-#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +-#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ +- +-#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +-#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ +- +- +-/* ADC - Analog/Digital Converter */ +-/* ADC_CH.CTRL bit masks and bit positions */ +-#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +-#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ +- +-#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +-#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +-#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +-#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +-#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +-#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +-#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +-#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ +- +-#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +-#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +-#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +-#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +-#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +-#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ +- +- +-/* ADC_CH.MUXCTRL bit masks and bit positions */ +-#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +-#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +-#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +-#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +-#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +-#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +-#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +-#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +-#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +-#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ +- +-#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +-#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +-#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +-#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +-#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +-#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +-#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +-#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +-#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +-#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ +- +-#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +-#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +-#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +-#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +-#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +-#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ +- +- +-/* ADC_CH.INTCTRL bit masks and bit positions */ +-#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +-#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +-#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +-#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +-#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +-#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ +- +-#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +-#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +-#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +-#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +-#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +-#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ +- +- +-/* ADC_CH.INTFLAGS bit masks and bit positions */ +-#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +-#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ +- +- +-/* ADC.CTRLA bit masks and bit positions */ +-#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +-#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ +- +-#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +-#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ +- +-#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +-#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ +- +- +-/* ADC.CTRLB bit masks and bit positions */ +-#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +-#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ +- +-#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +-#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ +- +-#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +-#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +-#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +-#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +-#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +-#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ +- +- +-/* ADC.REFCTRL bit masks and bit positions */ -#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ - #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ - #define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ - #define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ - #define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ - #define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - - #define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ - #define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -@@ -5334,6 +5409,12 @@ IO Module Instances. Mapped to memory. - #define PORTE_INT1_vect_num 44 - #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -+/* TWIE interrupt vectors */ -+#define TWIE_TWIS_vect_num 45 -+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -+#define TWIE_TWIM_vect_num 46 -+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ -+ - /* TCE0 interrupt vectors */ - #define TCE0_OVF_vect_num 47 - #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +-#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +-#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +-#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +-#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +-#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +- +-#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +-#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ +- +-#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +-#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ +- +- +-/* ADC.EVCTRL bit masks and bit positions */ +-#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +-#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +-#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +-#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +-#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +-#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ +- +-#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +-#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +-#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +-#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +-#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +-#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +-#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +-#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ +- +-#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +-#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +-#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +-#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +-#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +-#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +-#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +-#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ +- +- +-/* ADC.PRESCALER bit masks and bit positions */ +-#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +-#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +-#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +-#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +-#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +-#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +-#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +-#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ +- +- +-/* ADC.INTFLAGS bit masks and bit positions */ +-#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +-#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ +- +- +-/* RTC - Real-Time Clounter */ +-/* RTC.CTRL bit masks and bit positions */ +-#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +-#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +-#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +-#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +-#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +-#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +-#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +-#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ +- +- +-/* RTC.STATUS bit masks and bit positions */ +-#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +-#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ +- +- +-/* RTC.INTCTRL bit masks and bit positions */ +-#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +-#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +-#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +-#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +-#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +-#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ +- +-#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +-#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +-#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +-#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +-#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +-#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ +- +- +-/* RTC.INTFLAGS bit masks and bit positions */ +-#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +-#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ +- +-#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* EBI - External Bus Interface */ +-/* EBI_CS.CTRLA bit masks and bit positions */ +-#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +-#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +-#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +-#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +-#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +-#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +-#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +-#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +-#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +-#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +-#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +-#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ +- +-#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +-#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +-#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +-#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +-#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +-#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ +- +- +-/* EBI_CS.CTRLB bit masks and bit positions */ +-#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +-#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +-#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +-#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +-#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +-#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +-#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +-#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ +- +-#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +-#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ +- +-#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +-#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ +- +-#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +-#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +-#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +-#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +-#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +-#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ +- +- +-/* EBI.CTRL bit masks and bit positions */ +-#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +-#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +-#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +-#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +-#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +-#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ +- +-#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +-#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +-#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +-#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +-#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +-#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ +- +-#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +-#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +-#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +-#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +-#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +-#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ +- +-#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +-#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +-#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +-#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +-#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +-#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLA bit masks and bit positions */ +-#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +-#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ +- +-#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +-#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ +- +-#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +-#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +-#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +-#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +-#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +-#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLB bit masks and bit positions */ +-#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +-#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +-#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +-#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +-#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +-#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ +- +-#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +-#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +-#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +-#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +-#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +-#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +-#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +-#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ +- +-#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +-#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +-#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +-#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +-#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +-#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +-#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +-#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ +- +- +-/* EBI.SDRAMCTRLC bit masks and bit positions */ +-#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +-#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +-#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +-#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +-#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +-#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ +- +-#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +-#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +-#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +-#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +-#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +-#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +-#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +-#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ +- +-#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +-#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +-#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +-#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +-#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +-#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +-#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +-#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ +- +- +-/* TWI - Two-Wire Interface */ +-/* TWI_MASTER.CTRLA bit masks and bit positions */ +-#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +-#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ +- +-#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +-#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ +- +-#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +-#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ +- +- +-/* TWI_MASTER.CTRLB bit masks and bit positions */ +-#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +-#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +-#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +-#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +-#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +-#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +- +-#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +-#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ +- +-#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_MASTER.CTRLC bit masks and bit positions */ +-#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +-#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_MASTER.STATUS bit masks and bit positions */ +-#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +-#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ +- +-#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +-#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ +- +-#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +-#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +- +-#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +-#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +-#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +-#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +-#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +-#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +- +- +-/* TWI_SLAVE.CTRLA bit masks and bit positions */ +-#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +-#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +-#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ +- +-#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +-#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ +- +-#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_SLAVE.CTRLB bit masks and bit positions */ +-#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +-#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_SLAVE.STATUS bit masks and bit positions */ +-#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +-#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +-#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +-#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ +- +-#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +-#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ +- +-#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +-#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ +- +- +-/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +-#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +-#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +-#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +-#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +-#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +-#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +-#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +-#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +-#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +-#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +-#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +-#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +-#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +-#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +-#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +-#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ +- +-#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +-#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ +- +- +-/* TWI.CTRL bit masks and bit positions */ +-#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +-#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ +- +-#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +-#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ +- +- +-/* PORT - Port Configuration */ +-/* PORTCFG.VPCTRLA bit masks and bit positions */ +-#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +-#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +-#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +-#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +-#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +-#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +-#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +-#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +-#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +-#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ +- +-#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +-#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +-#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +-#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +-#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +-#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +-#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +-#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +-#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +-#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ +- +- +-/* PORTCFG.VPCTRLB bit masks and bit positions */ +-#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +-#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +-#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +-#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +-#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +-#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +-#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +-#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +-#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +-#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ +- +-#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +-#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +-#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +-#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +-#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +-#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +-#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +-#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +-#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +-#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ +- +- +-/* PORTCFG.CLKEVOUT bit masks and bit positions */ +-#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +-#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +-#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +-#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +-#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +-#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ +- +-#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +-#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +-#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +-#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +-#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +-#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ +- +- +-/* VPORT.INTFLAGS bit masks and bit positions */ +-#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.INTCTRL bit masks and bit positions */ +-#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +-#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +-#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +-#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +-#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +-#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ +- +-#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +-#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +-#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +-#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +-#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +-#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ +- +- +-/* PORT.INTFLAGS bit masks and bit positions */ +-#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.PIN0CTRL bit masks and bit positions */ +-#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +-#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ +- +-#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +-#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ +- +-#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +-#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +-#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +-#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +-#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +-#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +-#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +-#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ +- +-#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +-#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +-#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +-#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +-#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +-#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +-#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +-#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +- +- +-/* PORT.PIN1CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN2CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN3CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN4CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN5CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN6CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN7CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* TC - 16-bit Timer/Counter With PWM */ +-/* TC0.CTRLA bit masks and bit positions */ +-#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC0.CTRLB bit masks and bit positions */ +-#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +-#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ +- +-#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +-#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ +- +-#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC0.CTRLC bit masks and bit positions */ +-#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +-#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ +- +-#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +-#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ +- +-#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC0.CTRLD bit masks and bit positions */ +-#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC0_EVACT_gp 5 /* Event Action group position. */ +-#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC0.CTRLE bit masks and bit positions */ +-#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +-#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ +- +-#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC0.INTCTRLA bit masks and bit positions */ +-#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC0.INTCTRLB bit masks and bit positions */ +-#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +-#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +-#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +-#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +-#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +-#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ +- +-#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +-#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +-#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +-#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +-#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +-#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ +- +-#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC0.CTRLFCLR bit masks and bit positions */ +-#define TC0_CMD_gm 0x0C /* Command group mask. */ +-#define TC0_CMD_gp 2 /* Command group position. */ +-#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC0_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC0_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC0_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC0.CTRLFSET bit masks and bit positions */ +-/* TC0_CMD_gm Predefined. */ +-/* TC0_CMD_gp Predefined. */ +-/* TC0_CMD0_bm Predefined. */ +-/* TC0_CMD0_bp Predefined. */ +-/* TC0_CMD1_bm Predefined. */ +-/* TC0_CMD1_bp Predefined. */ +- +-/* TC0_LUPD_bm Predefined. */ +-/* TC0_LUPD_bp Predefined. */ +- +-/* TC0_DIR_bm Predefined. */ +-/* TC0_DIR_bp Predefined. */ +- +- +-/* TC0.CTRLGCLR bit masks and bit positions */ +-#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +-#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ +- +-#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +-#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ +- +-#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC0.CTRLGSET bit masks and bit positions */ +-/* TC0_CCDBV_bm Predefined. */ +-/* TC0_CCDBV_bp Predefined. */ +- +-/* TC0_CCCBV_bm Predefined. */ +-/* TC0_CCCBV_bp Predefined. */ +- +-/* TC0_CCBBV_bm Predefined. */ +-/* TC0_CCBBV_bp Predefined. */ +- +-/* TC0_CCABV_bm Predefined. */ +-/* TC0_CCABV_bp Predefined. */ +- +-/* TC0_PERBV_bm Predefined. */ +-/* TC0_PERBV_bp Predefined. */ +- +- +-/* TC0.INTFLAGS bit masks and bit positions */ +-#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +-#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ +- +-#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +-#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ +- +-#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* TC1.CTRLA bit masks and bit positions */ +-#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC1.CTRLB bit masks and bit positions */ +-#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC1.CTRLC bit masks and bit positions */ +-#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC1.CTRLD bit masks and bit positions */ +-#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC1_EVACT_gp 5 /* Event Action group position. */ +-#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC1.CTRLE bit masks and bit positions */ +-#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +-#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ +- +-#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC1.INTCTRLA bit masks and bit positions */ +-#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC1.INTCTRLB bit masks and bit positions */ +-#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC1.CTRLFCLR bit masks and bit positions */ +-#define TC1_CMD_gm 0x0C /* Command group mask. */ +-#define TC1_CMD_gp 2 /* Command group position. */ +-#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC1_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC1_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC1_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC1.CTRLFSET bit masks and bit positions */ +-/* TC1_CMD_gm Predefined. */ +-/* TC1_CMD_gp Predefined. */ +-/* TC1_CMD0_bm Predefined. */ +-/* TC1_CMD0_bp Predefined. */ +-/* TC1_CMD1_bm Predefined. */ +-/* TC1_CMD1_bp Predefined. */ +- +-/* TC1_LUPD_bm Predefined. */ +-/* TC1_LUPD_bp Predefined. */ +- +-/* TC1_DIR_bm Predefined. */ +-/* TC1_DIR_bp Predefined. */ +- +- +-/* TC1.CTRLGCLR bit masks and bit positions */ +-#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC1.CTRLGSET bit masks and bit positions */ +-/* TC1_CCBBV_bm Predefined. */ +-/* TC1_CCBBV_bp Predefined. */ +- +-/* TC1_CCABV_bm Predefined. */ +-/* TC1_CCABV_bp Predefined. */ +- +-/* TC1_PERBV_bm Predefined. */ +-/* TC1_PERBV_bp Predefined. */ +- +- +-/* TC1.INTFLAGS bit masks and bit positions */ +-#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* AWEX.CTRL bit masks and bit positions */ +-#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +-#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ +- +-#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +-#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ +- +-#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +-#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ +- +-#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +-#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ +- +-#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +-#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ +- +-#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +-#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ +- +- +-/* AWEX.FDCTRL bit masks and bit positions */ +-#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +-#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ +- +-#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +-#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ +- +-#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +-#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +-#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +-#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +-#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +-#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ +- +- +-/* AWEX.STATUS bit masks and bit positions */ +-#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +-#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ +- +-#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +-#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ +- +-#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +-#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ +- +- +-/* HIRES.CTRL bit masks and bit positions */ +-#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +-#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +-#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +-#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +-#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +-#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ +- +- +-/* USART - Universal Asynchronous Receiver-Transmitter */ +-/* USART.STATUS bit masks and bit positions */ +-#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +-#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ +- +-#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +-#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +- +-#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +-#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +- +-#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +-#define USART_FERR_bp 4 /* Frame Error bit position. */ +- +-#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +-#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ +- +-#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +-#define USART_PERR_bp 2 /* Parity Error bit position. */ +- +-#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +-#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ +- +- +-/* USART.CTRLA bit masks and bit positions */ +-#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +-#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +-#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +-#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +-#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +-#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ +- +-#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +-#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +-#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +-#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +-#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +-#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ +- +-#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +-#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +-#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +-#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +-#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +-#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ +- +- +-/* USART.CTRLB bit masks and bit positions */ +-#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +-#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ +- +-#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +-#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ +- +-#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +-#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ +- +-#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +-#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ +- +-#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +-#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ +- +- +-/* USART.CTRLC bit masks and bit positions */ +-#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +-#define USART_CMODE_gp 6 /* Communication Mode group position. */ +-#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +-#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +-#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +-#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ +- +-#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +-#define USART_PMODE_gp 4 /* Parity Mode group position. */ +-#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +-#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +-#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +-#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +- +-#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +-#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +- +-#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +-#define USART_CHSIZE_gp 0 /* Character Size group position. */ +-#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +-#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +-#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +-#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +-#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +-#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +- +- +-/* USART.BAUDCTRLA bit masks and bit positions */ +-#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +-#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +-#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +-#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +-#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +-#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +-#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +-#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +-#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +-#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +-#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +-#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +-#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +-#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +-#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +-#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +-#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +-#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ +- +- +-/* USART.BAUDCTRLB bit masks and bit positions */ +-#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +-#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +-#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +-#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +-#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +-#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +-#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +-#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +-#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +-#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ +- +-/* USART_BSEL_gm Predefined. */ +-/* USART_BSEL_gp Predefined. */ +-/* USART_BSEL0_bm Predefined. */ +-/* USART_BSEL0_bp Predefined. */ +-/* USART_BSEL1_bm Predefined. */ +-/* USART_BSEL1_bp Predefined. */ +-/* USART_BSEL2_bm Predefined. */ +-/* USART_BSEL2_bp Predefined. */ +-/* USART_BSEL3_bm Predefined. */ +-/* USART_BSEL3_bp Predefined. */ +- +- +-/* SPI - Serial Peripheral Interface */ +-/* SPI.CTRL bit masks and bit positions */ +-#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +-#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ +- +-#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +-#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ +- +-#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +-#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ +- +-#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +-#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ +- +-#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +-#define SPI_MODE_gp 2 /* SPI Mode group position. */ +-#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +-#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +-#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +-#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ +- +-#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +-#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +-#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +-#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +-#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +-#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ +- +- +-/* SPI.INTCTRL bit masks and bit positions */ +-#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +-#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +-/* SPI.STATUS bit masks and bit positions */ +-#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +-#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ +- +-#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +-#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +- +- +-/* IRCOM - IR Communication Module */ +-/* IRCOM.CTRL bit masks and bit positions */ +-#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +-#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +-#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +-#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +-#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +-#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +-#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +-#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +-#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +-#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ +- +- +- +-// Generic Port Pins +- +-#define PIN0_bm 0x01 +-#define PIN0_bp 0 +-#define PIN1_bm 0x02 +-#define PIN1_bp 1 +-#define PIN2_bm 0x04 +-#define PIN2_bp 2 +-#define PIN3_bm 0x08 +-#define PIN3_bp 3 +-#define PIN4_bm 0x10 +-#define PIN4_bp 4 +-#define PIN5_bm 0x20 +-#define PIN5_bp 5 +-#define PIN6_bm 0x40 +-#define PIN6_bp 6 +-#define PIN7_bm 0x80 +-#define PIN7_bp 7 +- +- +-/* ========== Interrupt Vector Definitions ========== */ +-/* Vector 0 is the reset vector */ +- +-/* OSC interrupt vectors */ +-#define OSC_XOSCF_vect_num 1 +-#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ +- +-/* PORTC interrupt vectors */ +-#define PORTC_INT0_vect_num 2 +-#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +-#define PORTC_INT1_vect_num 3 +-#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ +- +-/* PORTR interrupt vectors */ +-#define PORTR_INT0_vect_num 4 +-#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +-#define PORTR_INT1_vect_num 5 +-#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ +- +-/* RTC interrupt vectors */ +-#define RTC_OVF_vect_num 10 +-#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +-#define RTC_COMP_vect_num 11 +-#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ +- +-/* TWIC interrupt vectors */ +-#define TWIC_TWIS_vect_num 12 +-#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +-#define TWIC_TWIM_vect_num 13 +-#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ +- +-/* TCC0 interrupt vectors */ +-#define TCC0_OVF_vect_num 14 +-#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +-#define TCC0_ERR_vect_num 15 +-#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +-#define TCC0_CCA_vect_num 16 +-#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +-#define TCC0_CCB_vect_num 17 +-#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +-#define TCC0_CCC_vect_num 18 +-#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +-#define TCC0_CCD_vect_num 19 +-#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ +- +-/* TCC1 interrupt vectors */ +-#define TCC1_OVF_vect_num 20 +-#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +-#define TCC1_ERR_vect_num 21 +-#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +-#define TCC1_CCA_vect_num 22 +-#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +-#define TCC1_CCB_vect_num 23 +-#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ +- +-/* SPIC interrupt vectors */ +-#define SPIC_INT_vect_num 24 +-#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ +- +-/* USARTC0 interrupt vectors */ +-#define USARTC0_RXC_vect_num 25 +-#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +-#define USARTC0_DRE_vect_num 26 +-#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +-#define USARTC0_TXC_vect_num 27 +-#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ +- +-/* NVM interrupt vectors */ +-#define NVM_EE_vect_num 32 +-#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +-#define NVM_SPM_vect_num 33 +-#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ +- +-/* PORTB interrupt vectors */ +-#define PORTB_INT0_vect_num 34 +-#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +-#define PORTB_INT1_vect_num 35 +-#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ +- +-/* PORTE interrupt vectors */ +-#define PORTE_INT0_vect_num 43 +-#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +-#define PORTE_INT1_vect_num 44 +-#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ +- +-/* TCE0 interrupt vectors */ +-#define TCE0_OVF_vect_num 47 +-#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +-#define TCE0_ERR_vect_num 48 +-#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +-#define TCE0_CCA_vect_num 49 +-#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +-#define TCE0_CCB_vect_num 50 +-#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +-#define TCE0_CCC_vect_num 51 +-#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +-#define TCE0_CCD_vect_num 52 +-#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ +- +-/* PORTD interrupt vectors */ +-#define PORTD_INT0_vect_num 64 +-#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +-#define PORTD_INT1_vect_num 65 +-#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ +- +-/* PORTA interrupt vectors */ +-#define PORTA_INT0_vect_num 66 +-#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +-#define PORTA_INT1_vect_num 67 +-#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ +- +-/* ACA interrupt vectors */ +-#define ACA_AC0_vect_num 68 +-#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +-#define ACA_AC1_vect_num 69 +-#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +-#define ACA_ACW_vect_num 70 +-#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ +- +-/* ADCA interrupt vectors */ +-#define ADCA_CH0_vect_num 71 +-#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +- +-/* TCD0 interrupt vectors */ +-#define TCD0_OVF_vect_num 77 +-#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +-#define TCD0_ERR_vect_num 78 +-#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +-#define TCD0_CCA_vect_num 79 +-#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +-#define TCD0_CCB_vect_num 80 +-#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +-#define TCD0_CCC_vect_num 81 +-#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +-#define TCD0_CCD_vect_num 82 +-#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ +- +-/* SPID interrupt vectors */ +-#define SPID_INT_vect_num 87 +-#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ +- +-/* USARTD0 interrupt vectors */ +-#define USARTD0_RXC_vect_num 88 +-#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +-#define USARTD0_DRE_vect_num 89 +-#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +-#define USARTD0_TXC_vect_num 90 +-#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ +- +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (91 * _VECTOR_SIZE) +- +- +-/* ========== Constants ========== */ +- +-#define PROGMEM_START (0x0000) +-#define PROGMEM_SIZE (36864) +-#define PROGMEM_PAGE_SIZE (256) +-#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) +- +-#define APP_SECTION_START (0x0000) +-#define APP_SECTION_SIZE (32768) +-#define APP_SECTION_PAGE_SIZE (256) +-#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) +- +-#define APPTABLE_SECTION_START (0x7000) +-#define APPTABLE_SECTION_SIZE (4096) +-#define APPTABLE_SECTION_PAGE_SIZE (256) +-#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) +- +-#define BOOT_SECTION_START (0x8000) +-#define BOOT_SECTION_SIZE (4096) +-#define BOOT_SECTION_PAGE_SIZE (256) +-#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) +- +-#define DATAMEM_START (0x0000) +-#define DATAMEM_SIZE (12288) +-#define DATAMEM_PAGE_SIZE (0) +-#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) +- +-#define IO_START (0x0000) +-#define IO_SIZE (4096) +-#define IO_PAGE_SIZE (0) +-#define IO_END (IO_START + IO_SIZE - 1) +- +-#define MAPPED_EEPROM_START (0x1000) +-#define MAPPED_EEPROM_SIZE (1024) +-#define MAPPED_EEPROM_PAGE_SIZE (0) +-#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) +- +-#define INTERNAL_SRAM_START (0x2000) +-#define INTERNAL_SRAM_SIZE (4096) +-#define INTERNAL_SRAM_PAGE_SIZE (0) +-#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) +- +-#define EEPROM_START (0x0000) +-#define EEPROM_SIZE (1024) +-#define EEPROM_PAGE_SIZE (32) +-#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) +- +-#define FUSE_START (0x0000) +-#define FUSE_SIZE (6) +-#define FUSE_PAGE_SIZE (0) +-#define FUSE_END (FUSE_START + FUSE_SIZE - 1) +- +-#define LOCKBIT_START (0x0000) +-#define LOCKBIT_SIZE (1) +-#define LOCKBIT_PAGE_SIZE (0) +-#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) +- +-#define SIGNATURES_START (0x0000) +-#define SIGNATURES_SIZE (3) +-#define SIGNATURES_PAGE_SIZE (0) +-#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) +- +-#define USER_SIGNATURES_START (0x0000) +-#define USER_SIGNATURES_SIZE (256) +-#define USER_SIGNATURES_PAGE_SIZE (0) +-#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) +- +-#define PROD_SIGNATURES_START (0x0000) +-#define PROD_SIGNATURES_SIZE (52) +-#define PROD_SIGNATURES_PAGE_SIZE (0) +-#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) +- +-#define FLASHEND PROGMEM_END +-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +-#define RAMSTART INTERNAL_SRAM_START +-#define RAMSIZE INTERNAL_SRAM_SIZE +-#define RAMEND INTERNAL_SRAM_END +-#define XRAMSTART EXTERNAL_SRAM_START +-#define XRAMSIZE EXTERNAL_SRAM_SIZE +-#define XRAMEND INTERNAL_SRAM_END +-#define E2END EEPROM_END +-#define E2PAGESIZE EEPROM_PAGE_SIZE +- +- +-/* ========== Fuses ========== */ +-#define FUSE_MEMORY_SIZE 6 +- +-/* Fuse Byte 0 */ +-#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ +-#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ +-#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ +-#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ +-#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ +-#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ +-#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ +-#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ +-#define FUSE0_DEFAULT (0xFF) +- +-/* Fuse Byte 1 */ +-#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +-#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +-#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +-#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +-#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +-#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +-#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +-#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +-#define FUSE1_DEFAULT (0xFF) +- +-/* Fuse Byte 2 */ +-#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +-#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +-#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +-#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +-#define FUSE2_DEFAULT (0xFF) +- +-/* Fuse Byte 3 Reserved */ +- +-/* Fuse Byte 4 */ +-#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +-#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +-#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +-#define FUSE4_DEFAULT (0xFF) +- +-/* Fuse Byte 5 */ +-#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +-#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +-#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +-#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +-#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +-#define FUSE5_DEFAULT (0xFF) +- +- +-/* ========== Lock Bits ========== */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_BITS_EXIST +-#define __BOOT_LOCK_BOOT_BITS_EXIST +- +- +-/* ========== Signature ========== */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x95 +-#define SIGNATURE_2 0x42 +- +- +-#endif /* _AVR_ATxmega32D4_H_ */ +- ++/* Copyright (c) 2009-2010 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iox32d4.h 2200 2010-12-14 04:24:24Z arcanum $ */ ++ ++/* avr/iox32d4.h - definitions for ATxmega32D4 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox32d4.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATxmega32D4_H_ ++#define _AVR_ATxmega32D4_H_ 1 ++ ++ ++/* Ungrouped common registers */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++} CLK_t; ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t PRPB; /* Power Reduction Port B */ ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ ++} CLK_RTCSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control REgister */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t reserved_0x07; ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++} PMIC_t; ++ ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ ++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ ++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ ++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ ++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ ++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ ++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ ++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ ++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ ++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t FUSEBYTE0; /* User ID */ ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ ++ register8_t reserved_0x01; ++ register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ ++ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ ++ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ ++ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++} NVM_PROD_SIGNATURES_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++} NVM_LB_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brown Out Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ ++ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Comparator 0 Control */ ++ register8_t AC1CTRL; /* Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t reserved_0x6; ++ register8_t reserved_0x7; ++} ADC_CH_t; ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++} ADC_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ ++} ADC_CURRLIMIT_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++} ADC_REFSEL_t; ++ ++/* Channel sweep selection */ ++typedef enum ADC_SWEEP_enum ++{ ++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ++} ADC_SWEEP_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Clounter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* EBI Chip Select Module */ ++typedef struct EBI_CS_struct ++{ ++ register8_t CTRLA; /* Chip Select Control Register A */ ++ register8_t CTRLB; /* Chip Select Control Register B */ ++ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ ++} EBI_CS_t; ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* External Bus Interface */ ++typedef struct EBI_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ ++ register8_t reserved_0x02; ++ register8_t reserved_0x03; ++ _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ ++ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ ++ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ ++ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ EBI_CS_t CS0; /* Chip Select 0 */ ++ EBI_CS_t CS1; /* Chip Select 1 */ ++ EBI_CS_t CS2; /* Chip Select 2 */ ++ EBI_CS_t CS3; /* Chip Select 3 */ ++} EBI_t; ++ ++/* Chip Select adress space */ ++typedef enum EBI_CS_ASIZE_enum ++{ ++ EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ ++ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ ++ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ ++ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ ++ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ ++ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ ++ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ ++ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ ++ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ ++ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ ++ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ ++ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ ++ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ ++ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ ++ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ ++ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ ++ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ ++} EBI_CS_ASIZE_t; ++ ++/* */ ++typedef enum EBI_CS_SRWS_enum ++{ ++ EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_CS_SRWS_t; ++ ++/* Chip Select address mode */ ++typedef enum EBI_CS_MODE_enum ++{ ++ EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ ++ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ ++ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ ++ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ ++} EBI_CS_MODE_t; ++ ++/* Chip Select SDRAM mode */ ++typedef enum EBI_CS_SDMODE_enum ++{ ++ EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ ++ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ ++} EBI_CS_SDMODE_t; ++ ++/* */ ++typedef enum EBI_SDDATAW_enum ++{ ++ EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ ++ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ ++} EBI_SDDATAW_t; ++ ++/* */ ++typedef enum EBI_LPCMODE_enum ++{ ++ EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ ++ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ ++} EBI_LPCMODE_t; ++ ++/* */ ++typedef enum EBI_SRMODE_enum ++{ ++ EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ ++ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ ++ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ ++ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ ++} EBI_SRMODE_t; ++ ++/* */ ++typedef enum EBI_IFMODE_enum ++{ ++ EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ ++ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ ++ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ ++ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ ++} EBI_IFMODE_t; ++ ++/* */ ++typedef enum EBI_SDCOL_enum ++{ ++ EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ ++ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ ++ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ ++ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ ++} EBI_SDCOL_t; ++ ++/* */ ++typedef enum EBI_MRDLY_enum ++{ ++ EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_MRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCYCDLY_enum ++{ ++ EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ROWCYCDLY_t; ++ ++/* */ ++typedef enum EBI_RPDLY_enum ++{ ++ EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_RPDLY_t; ++ ++/* */ ++typedef enum EBI_WRDLY_enum ++{ ++ EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_WRDLY_t; ++ ++/* */ ++typedef enum EBI_ESRDLY_enum ++{ ++ EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ESRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCOLDLY_enum ++{ ++ EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_ROWCOLDLY_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++} PORTCFG_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Virtual Port 0 Mapping */ ++typedef enum PORTCFG_VP0MAP_enum ++{ ++ PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP0MAP_t; ++ ++/* Virtual Port 1 Mapping */ ++typedef enum PORTCFG_VP1MAP_enum ++{ ++ PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP1MAP_t; ++ ++/* Virtual Port 2 Mapping */ ++typedef enum PORTCFG_VP2MAP_enum ++{ ++ PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP2MAP_t; ++ ++/* Virtual Port 3 Mapping */ ++typedef enum PORTCFG_VP3MAP_enum ++{ ++ PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP3MAP_t; ++ ++/* Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x05; ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset Controller */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ ++#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ ++#define PORTA (*(PORT_t *) 0x0600) /* Port A */ ++#define PORTB (*(PORT_t *) 0x0620) /* Port B */ ++#define PORTC (*(PORT_t *) 0x0640) /* Port C */ ++#define PORTD (*(PORT_t *) 0x0660) /* Port D */ ++#define PORTE (*(PORT_t *) 0x0680) /* Port E */ ++#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ ++#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++#define GPIO_GPIO4 _SFR_MEM8(0x0004) ++#define GPIO_GPIO5 _SFR_MEM8(0x0005) ++#define GPIO_GPIO6 _SFR_MEM8(0x0006) ++#define GPIO_GPIO7 _SFR_MEM8(0x0007) ++#define GPIO_GPIO8 _SFR_MEM8(0x0008) ++#define GPIO_GPIO9 _SFR_MEM8(0x0009) ++#define GPIO_GPIOA _SFR_MEM8(0x000A) ++#define GPIO_GPIOB _SFR_MEM8(0x000B) ++#define GPIO_GPIOC _SFR_MEM8(0x000C) ++#define GPIO_GPIOD _SFR_MEM8(0x000D) ++#define GPIO_GPIOE _SFR_MEM8(0x000E) ++#define GPIO_GPIOF _SFR_MEM8(0x000F) ++ ++/* VPORT0 - Virtual Port 0 */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT1 - Virtual Port 1 */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT2 - Virtual Port 2 */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT3 - Virtual Port 3 */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU Registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator Control */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPB _SFR_MEM8(0x0072) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset Controller */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - Port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non Volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADCA - Analog to Digital Converter A */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++ ++/* DACB - Digital to Analog Converter B */ ++ ++/* ACA - Analog Comparator A */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWIC - Two-Wire Interface C */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWIE - Two-Wire Interface E */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++ ++/* PORTA - Port A */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORTB - Port B */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORTC - Port C */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORTD - Port D */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORTE - Port E */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORTR - Port R */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TCC0 - Timer/Counter C0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TCC1 - Timer/Counter C1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEXC - Advanced Waveform Extension C */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRESC - High-Resolution Extension C */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* SPIC - Serial Peripheral Interface C */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TCD0 - Timer/Counter D0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* SPID - Serial Peripheral Interface D */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TCE0 - Timer/Counter E0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR1 bit masks and bit positions */ ++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ ++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ ++ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ ++ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ ++#define PR_EBI_bp 3 /* External Bus Interface bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ ++#define PR_DAC_bp 2 /* Port A DAC bit position. */ ++ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++ ++/* PR.PRPB bit masks and bit positions */ ++/* PR_DAC_bm Predefined. */ ++/* PR_DAC_bp Predefined. */ ++ ++/* PR_ADC_bm Predefined. */ ++/* PR_ADC_bp Predefined. */ ++ ++/* PR_AC_bm Predefined. */ ++/* PR_AC_bp Predefined. */ ++ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ ++ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ ++ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ ++ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ ++#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ ++ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ ++ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ ++ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ ++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ ++ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM_gm Predefined. */ ++/* EVSYS_QDIRM_gp Predefined. */ ++/* EVSYS_QDIRM0_bm Predefined. */ ++/* EVSYS_QDIRM0_bp Predefined. */ ++/* EVSYS_QDIRM1_bm Predefined. */ ++/* EVSYS_QDIRM1_bp Predefined. */ ++ ++/* EVSYS_QDIEN_bm Predefined. */ ++/* EVSYS_QDIEN_bp Predefined. */ ++ ++/* EVSYS_QDEN_bm Predefined. */ ++/* EVSYS_QDEN_bp Predefined. */ ++ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0xFF /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ ++#define NVM_CMD7_bp 7 /* Command bit 7 position. */ ++ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ ++#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ ++#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ ++#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ ++#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ ++#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ ++#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ ++#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ ++#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ ++#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ ++#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ ++#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ ++#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ ++#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ ++#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ ++#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ ++#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ ++#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ ++#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ ++#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ ++ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ ++ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ ++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE_gm Predefined. */ ++/* AC_INTMODE_gp Predefined. */ ++/* AC_INTMODE0_bm Predefined. */ ++/* AC_INTMODE0_bp Predefined. */ ++/* AC_INTMODE1_bm Predefined. */ ++/* AC_INTMODE1_bp Predefined. */ ++ ++/* AC_INTLVL_gm Predefined. */ ++/* AC_INTLVL_gp Predefined. */ ++/* AC_INTLVL0_bm Predefined. */ ++/* AC_INTLVL0_bp Predefined. */ ++/* AC_INTLVL1_bm Predefined. */ ++/* AC_INTLVL1_bp Predefined. */ ++ ++/* AC_HSMODE_bm Predefined. */ ++/* AC_HSMODE_bp Predefined. */ ++ ++/* AC_HYSMODE_gm Predefined. */ ++/* AC_HYSMODE_gp Predefined. */ ++/* AC_HYSMODE0_bm Predefined. */ ++/* AC_HYSMODE0_bp Predefined. */ ++/* AC_HYSMODE1_bm Predefined. */ ++/* AC_HYSMODE1_bp Predefined. */ ++ ++/* AC_ENABLE_bm Predefined. */ ++/* AC_ENABLE_bp Predefined. */ ++ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS_gm Predefined. */ ++/* AC_MUXPOS_gp Predefined. */ ++/* AC_MUXPOS0_bm Predefined. */ ++/* AC_MUXPOS0_bp Predefined. */ ++/* AC_MUXPOS1_bm Predefined. */ ++/* AC_MUXPOS1_bp Predefined. */ ++/* AC_MUXPOS2_bm Predefined. */ ++/* AC_MUXPOS2_bp Predefined. */ ++ ++/* AC_MUXNEG_gm Predefined. */ ++/* AC_MUXNEG_gp Predefined. */ ++/* AC_MUXNEG0_bm Predefined. */ ++/* AC_MUXNEG0_bp Predefined. */ ++/* AC_MUXNEG1_bm Predefined. */ ++/* AC_MUXNEG1_bp Predefined. */ ++/* AC_MUXNEG2_bm Predefined. */ ++/* AC_MUXNEG2_bp Predefined. */ ++ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ ++ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ ++ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ ++#define ADC_CH_MUXPOS4_bm (1<<7) /* Positive Input Select bit 3 mask. */ ++#define ADC_CH_MUXPOS4_bp 7 /* Positive Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ ++ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ ++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_IMPMODE_bm 0x80 /* Impedance Mode bit mask. */ ++#define ADC_IMPMODE_bp 7 /* Impedance Mode bit position. */ ++ ++#define ADC_CURRENT_bm 0x60 /* Current bit mask. */ ++#define ADC_CURRENT1_bp 6 /* Current bit position. */ ++#define ADC_CURRENT0_bp 5 /* Current bit position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ ++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ ++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ ++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ ++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ ++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ ++ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++ ++/* RTC - Real-Time Clounter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* EBI - External Bus Interface */ ++/* EBI_CS.CTRLA bit masks and bit positions */ ++#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ ++#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ ++#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ ++#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ ++#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ ++#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ ++#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ ++#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ ++#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ ++#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ ++#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ ++#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ ++ ++#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ ++#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ ++#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ ++#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ ++#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ ++#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ ++ ++ ++/* EBI_CS.CTRLB bit masks and bit positions */ ++#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ ++#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ ++#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ ++#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ ++#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ ++#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ ++#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ ++#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ ++ ++#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ ++#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ ++ ++#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ ++#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ ++ ++#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ ++#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ ++#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ ++#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ ++#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ ++#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ ++ ++ ++/* EBI.CTRL bit masks and bit positions */ ++#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ ++#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ ++#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ ++#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ ++#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ ++#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ ++ ++#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ ++#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ ++#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ ++#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ ++#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ ++#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ ++ ++#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ ++#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ ++#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ ++#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ ++#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ ++#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ ++ ++#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ ++#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ ++#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ ++#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ ++#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ ++#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLA bit masks and bit positions */ ++#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ ++#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ ++ ++#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ ++#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ ++ ++#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ ++#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ ++#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ ++#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ ++#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ ++#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLB bit masks and bit positions */ ++#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ ++#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ ++#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ ++#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ ++#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ ++#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ ++ ++#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ ++#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ ++#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ ++#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ ++#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ ++#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ ++#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ ++#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ ++ ++#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ ++#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ ++#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ ++#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ ++#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ ++#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ ++#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ ++#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ ++ ++ ++/* EBI.SDRAMCTRLC bit masks and bit positions */ ++#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ ++#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ ++#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ ++#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ ++#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ ++#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ ++ ++#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ ++#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ ++#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ ++#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ ++#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ ++#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ ++#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ ++#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ ++ ++#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ ++#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ ++#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ ++#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ ++#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ ++#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ ++#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ ++#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ ++ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ ++#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++ ++/* PORT - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ ++#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ ++ ++#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD_gm Predefined. */ ++/* TC0_CMD_gp Predefined. */ ++/* TC0_CMD0_bm Predefined. */ ++/* TC0_CMD0_bp Predefined. */ ++/* TC0_CMD1_bm Predefined. */ ++/* TC0_CMD1_bp Predefined. */ ++ ++/* TC0_LUPD_bm Predefined. */ ++/* TC0_LUPD_bp Predefined. */ ++ ++/* TC0_DIR_bm Predefined. */ ++/* TC0_DIR_bp Predefined. */ ++ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV_bm Predefined. */ ++/* TC0_CCDBV_bp Predefined. */ ++ ++/* TC0_CCCBV_bm Predefined. */ ++/* TC0_CCCBV_bp Predefined. */ ++ ++/* TC0_CCBBV_bm Predefined. */ ++/* TC0_CCBBV_bp Predefined. */ ++ ++/* TC0_CCABV_bm Predefined. */ ++/* TC0_CCABV_bp Predefined. */ ++ ++/* TC0_PERBV_bm Predefined. */ ++/* TC0_PERBV_bp Predefined. */ ++ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ ++#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ ++ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD_gm Predefined. */ ++/* TC1_CMD_gp Predefined. */ ++/* TC1_CMD0_bm Predefined. */ ++/* TC1_CMD0_bp Predefined. */ ++/* TC1_CMD1_bm Predefined. */ ++/* TC1_CMD1_bp Predefined. */ ++ ++/* TC1_LUPD_bm Predefined. */ ++/* TC1_LUPD_bp Predefined. */ ++ ++/* TC1_DIR_bm Predefined. */ ++/* TC1_DIR_bp Predefined. */ ++ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV_bm Predefined. */ ++/* TC1_CCBBV_bp Predefined. */ ++ ++/* TC1_CCABV_bm Predefined. */ ++/* TC1_CCABV_bp Predefined. */ ++ ++/* TC1_PERBV_bm Predefined. */ ++/* TC1_PERBV_bp Predefined. */ ++ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++ ++/* HIRES.CTRL bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL_gm Predefined. */ ++/* USART_BSEL_gp Predefined. */ ++/* USART_BSEL0_bm Predefined. */ ++/* USART_BSEL0_bp Predefined. */ ++/* USART_BSEL1_bm Predefined. */ ++/* USART_BSEL1_bp Predefined. */ ++/* USART_BSEL2_bm Predefined. */ ++/* USART_BSEL2_bp Predefined. */ ++/* USART_BSEL3_bm Predefined. */ ++/* USART_BSEL3_bp Predefined. */ ++ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_XOSCF_vect_num 1 ++#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (91 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (36864) ++#define PROGMEM_PAGE_SIZE (256) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (32768) ++#define APP_SECTION_PAGE_SIZE (256) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x7000) ++#define APPTABLE_SECTION_SIZE (4096) ++#define APPTABLE_SECTION_PAGE_SIZE (256) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x8000) ++#define BOOT_SECTION_SIZE (4096) ++#define BOOT_SECTION_PAGE_SIZE (256) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (12288) ++#define DATAMEM_PAGE_SIZE (0) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (1024) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (4096) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (1024) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define FUSE_START (0x0000) ++#define FUSE_SIZE (6) ++#define FUSE_PAGE_SIZE (0) ++#define FUSE_END (FUSE_START + FUSE_SIZE - 1) ++ ++#define LOCKBIT_START (0x0000) ++#define LOCKBIT_SIZE (1) ++#define LOCKBIT_PAGE_SIZE (0) ++#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (256) ++#define USER_SIGNATURES_PAGE_SIZE (0) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (0) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE PROGMEM_PAGE_SIZE ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define XRAMSTART EXTERNAL_SRAM_START ++#define XRAMSIZE EXTERNAL_SRAM_SIZE ++#define XRAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 */ ++#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ ++#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ ++#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ ++#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ ++#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ ++#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ ++#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ ++#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ ++#define FUSE0_DEFAULT (0xFF) ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x42 ++ ++ ++#endif /* _AVR_ATxmega32D4_H_ */ ++ diff --git a/include/avr/iox32e5.h b/include/avr/iox32e5.h new file mode 100644 -index 0000000..4bba425 +index 0000000..93f32b9 --- /dev/null +++ b/include/avr/iox32e5.h @@ -0,0 +1,7664 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox32e5.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA32E5_H_INCLUDED -+#define _AVR_ATXMEGA32E5_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+VPORT - Virtual Ports -+-------------------------------------------------------------------------- -+*/ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t reserved_0x04; -+} CLK_t; -+ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t reserved_0x02; -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t PRPD; /* Power Reduction Port D */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+} PR_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+ CLK_SCLKSEL_RC8M_gc = (0x05<<0), /* Internal 8 MHz RC Oscillator */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+ CLK_PSADIV_6_gc = (0x13<<2), /* Divide by 6 */ -+ CLK_PSADIV_10_gc = (0x15<<2), /* Divide by 10 */ -+ CLK_PSADIV_12_gc = (0x17<<2), /* Divide by 12 */ -+ CLK_PSADIV_24_gc = (0x19<<2), /* Divide by 24 */ -+ CLK_PSADIV_48_gc = (0x1B<<2), /* Divide by 48 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control Register */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+ register8_t RC8MCAL; /* Internal 8 MHz RC Oscillator Calibration Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -+ OSC_XOSCSEL_EXTCLK_C4_gc = (0x14<<0), /* External Clock on port C4 - 6 CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ -+ OSC_PLLSRC_RC8M_gc = (0x01<<6), /* Internal 8 MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+/* 32 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC32MCREF_enum -+{ -+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC32MCREF_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t ANAINIT; /* Analog Startup Delay */ -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t WEXLOCK; /* WEX Lock */ -+ register8_t FAULTLOCK; /* FAULT Lock */ -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORTCFG - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t reserved_0x02; -+ register8_t reserved_0x03; -+ register8_t CLKOUT; /* Clock Out Register */ -+ register8_t reserved_0x05; -+ register8_t ACEVOUT; /* Analog Comparator and Event Out Register */ -+ register8_t SRLCTRL; /* Slew Rate Limit Control Register */ -+} PORTCFG_t; -+ -+/* Clock and Event Output Port */ -+typedef enum PORTCFG_CLKEVPIN_enum -+{ -+ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ -+ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -+} PORTCFG_CLKEVPIN_t; -+ -+/* RTC Clock Output Port */ -+typedef enum PORTCFG_RTCCLKOUT_enum -+{ -+ PORTCFG_RTCCLKOUT_OFF_gc = (0x00<<5), /* System Clock Output Disabled */ -+ PORTCFG_RTCCLKOUT_PC6_gc = (0x01<<5), /* System Clock Output on Port C pin 6 */ -+ PORTCFG_RTCCLKOUT_PD6_gc = (0x02<<5), /* System Clock Output on Port D pin 6 */ -+ PORTCFG_RTCCLKOUT_PR0_gc = (0x03<<5), /* System Clock Output on Port R pin 0 */ -+} PORTCFG_RTCCLKOUT_t; -+ -+/* Peripheral Clock Output Select */ -+typedef enum PORTCFG_CLKOUTSEL_enum -+{ -+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -+} PORTCFG_CLKOUTSEL_t; -+ -+/* System Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ -+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ -+ PORTCFG_CLKOUT_PR0_gc = (0x03<<0), /* System Clock Output on Port R pin 0 */ -+} PORTCFG_CLKOUT_t; -+ -+/* Analog Comparator Output Port */ -+typedef enum PORTCFG_ACOUT_enum -+{ -+ PORTCFG_ACOUT_PA_gc = (0x00<<6), /* Analog Comparator Outputs on Port A, Pin 6-7 */ -+ PORTCFG_ACOUT_PC_gc = (0x01<<6), /* Analog Comparator Outputs on Port C, Pin 6-7 */ -+ PORTCFG_ACOUT_PD_gc = (0x02<<6), /* Analog Comparator Outputs on Port D, Pin 6-7 */ -+ PORTCFG_ACOUT_PR_gc = (0x03<<6), /* Analog Comparator Outputs on Port R, Pin 0-1 */ -+} PORTCFG_ACOUT_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel n Output on Port C pin 7 */ -+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel n Output on Port D pin 7 */ -+ PORTCFG_EVOUT_PR0_gc = (0x03<<4), /* Event Channel n Output on Port R pin 0 */ -+} PORTCFG_EVOUT_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -+ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ -+ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ -+ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ -+ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ -+ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ -+ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ -+ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EDMA - Enhanced DMA Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* EDMA Channel */ -+typedef struct EDMA_CH_struct -+{ -+ register8_t CTRLA; /* Channel Control A */ -+ register8_t CTRLB; /* Channel Control */ -+ register8_t ADDRCTRL; /* Memory Address Control for Peripheral Ch., or Source Address Control for Standard Ch. */ -+ register8_t DESTADDRCTRL; /* Destination Address Control for Standard Channels Only. */ -+ register8_t TRIGSRC; /* Channel Trigger Source */ -+ register8_t reserved_0x05; -+ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch. */ -+ _WORDREGISTER(ADDR); /* Channel Memory Address for Peripheral Ch., or Channel Source Address Low for Standard Ch. */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(DESTADDR); /* Channel Destination Address for Standard Channels Only. */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} EDMA_CH_t; -+ -+ -+/* Enhanced DMA Controller */ -+typedef struct EDMA_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t reserved_0x01; -+ register8_t reserved_0x02; -+ register8_t INTFLAGS; /* Transfer Interrupt Status */ -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x05; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ EDMA_CH_t CH0; /* EDMA Channel 0 */ -+ EDMA_CH_t CH1; /* EDMA Channel 1 */ -+ EDMA_CH_t CH2; /* EDMA Channel 2 */ -+ EDMA_CH_t CH3; /* EDMA Channel 3 */ -+} EDMA_t; -+ -+/* Channel mode */ -+typedef enum EDMA_CHMODE_enum -+{ -+ EDMA_CHMODE_PER0123_gc = (0x00<<4), /* Channels 0, 1, 2 and 3 in peripheal conf. */ -+ EDMA_CHMODE_STD0_gc = (0x01<<4), /* Channel 0 in standard conf.; channels 2 and 3 in peripheral conf. */ -+ EDMA_CHMODE_STD2_gc = (0x02<<4), /* Channel 2 in standard conf.; channels 0 and 1 in peripheral conf. */ -+ EDMA_CHMODE_STD02_gc = (0x03<<4), /* Channels 0 and 2 in standard conf. */ -+} EDMA_CHMODE_t; -+ -+/* Double buffer mode */ -+typedef enum EDMA_DBUFMODE_enum -+{ -+ EDMA_DBUFMODE_DISABLE_gc = (0x00<<2), /* No double buffer enabled */ -+ EDMA_DBUFMODE_BUF01_gc = (0x01<<2), /* Double buffer enabled on peripheral channels 0/1 (if exist) */ -+ EDMA_DBUFMODE_BUF23_gc = (0x02<<2), /* Double buffer enabled on peripheral channels 2/3 (if exist) */ -+ EDMA_DBUFMODE_BUF0123_gc = (0x03<<2), /* Double buffer enabled on peripheral channels 0/1 and 2/3 or standard channels 0/2 */ -+} EDMA_DBUFMODE_t; -+ -+/* Priority mode */ -+typedef enum EDMA_PRIMODE_enum -+{ -+ EDMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round robin on all channels */ -+ EDMA_PRIMODE_RR123_gc = (0x01<<0), /* Ch0 > round robin (Ch 1 ch2 Ch3) */ -+ EDMA_PRIMODE_RR23_gc = (0x02<<0), /* Ch0 > Ch 1 > round robin (Ch2 Ch3) */ -+ EDMA_PRIMODE_CH0123_gc = (0x03<<0), /* Ch0 > Ch1 > Ch2 > Ch3 */ -+} EDMA_PRIMODE_t; -+ -+/* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. */ -+typedef enum EDMA_CH_RELOAD_enum -+{ -+ EDMA_CH_RELOAD_NONE_gc = (0x00<<4), /* No reload */ -+ EDMA_CH_RELOAD_BLOCK_gc = (0x01<<4), /* Reload at end of each block transfer */ -+ EDMA_CH_RELOAD_BURST_gc = (0x02<<4), /* Reload at end of each burst transfer */ -+ EDMA_CH_RELOAD_TRANSACTION_gc = (0x03<<4), /* Reload at end of each transaction */ -+} EDMA_CH_RELOAD_t; -+ -+/* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. */ -+typedef enum EDMA_CH_DIR_enum -+{ -+ EDMA_CH_DIR_FIXED_gc = (0x00<<0), /* Fixed */ -+ EDMA_CH_DIR_INC_gc = (0x01<<0), /* Increment */ -+ EDMA_CH_DIR_MP1_gc = (0x04<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'mask-match' (data: ADDRL, mask: ADDRH), else reserved conf. */ -+ EDMA_CH_DIR_MP2_gc = (0x05<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH), else reserved conf. */ -+ EDMA_CH_DIR_MP3_gc = (0x06<<0), /* If Peripheral Ch. (Per ==> Mem), 2-byte 'match' (data-1: ADDRL followed by data-2: ADDRH), else reserved conf. */ -+} EDMA_CH_DIR_t; -+ -+/* Destination addressing mode */ -+typedef enum EDMA_CH_DESTDIR_enum -+{ -+ EDMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ -+ EDMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ -+ EDMA_CH_DESTDIR_MP1_gc = (0x04<<0), /* 1-byte 'mask-match' (data: ADDRL, mask: ADDRH) */ -+ EDMA_CH_DESTDIR_MP2_gc = (0x05<<0), /* 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH) */ -+ EDMA_CH_DESTDIR_MP3_gc = (0x06<<0), /* 2-byte 'match' (data1: ADDRL followed by data2: ADDRH) */ -+} EDMA_CH_DESTDIR_t; -+ -+/* Transfer trigger source */ -+typedef enum EDMA_CH_TRIGSRC_enum -+{ -+ EDMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Software triggers only */ -+ EDMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event CH0 as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event CH1 as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event CH2 as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA CH0 as trigger */ -+ EDMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA CH0 as trigger */ -+ EDMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA CH1 as trigger */ -+ EDMA_CH_TRIGSRC_TCC4_OVF_gc = (0x40<<0), /* TCC4 overflow/underflow as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCC4_ERR_gc = (0x41<<0), /* TCC4 error as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCC4_CCA_gc = (0x42<<0), /* TCC4 compare or capture channel A as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCC4_CCB_gc = (0x43<<0), /* TCC4 compare or capture channel B as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCC4_CCC_gc = (0x44<<0), /* TCC4 compare or capture channel C as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCC4_CCD_gc = (0x45<<0), /* TCC4 compare or capture channel D as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCC5_OVF_gc = (0x46<<0), /* TCC5 overflow/underflow as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCC5_ERR_gc = (0x47<<0), /* TCC5 error as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCC5_CCA_gc = (0x48<<0), /* TCC5 compare or capture channel A as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCC5_CCB_gc = (0x49<<0), /* TCC5 compare or capture channel B as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_SPIC_RXC_gc = (0x4A<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C receive complete as trigger (SPI Buffer Modes) */ -+ EDMA_CH_TRIGSRC_SPIC_DRE_gc = (0x4B<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C data register empty as trigger (SPI Buffer modes) */ -+ EDMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4C<<0), /* USART C0 receive complete as trigger */ -+ EDMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4D<<0), /* USART C0 data register empty as trigger */ -+ EDMA_CH_TRIGSRC_TCD5_OVF_gc = (0x66<<0), /* TCD5 overflow/underflow as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCD5_ERR_gc = (0x67<<0), /* TCD5 error as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCD5_CCA_gc = (0x68<<0), /* TCD5 compare or capture channel A as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCD5_CCB_gc = (0x69<<0), /* TCD5 compare or capture channel B as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6C<<0), /* USART D0 receive complete as trigger */ -+ EDMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6D<<0), /* USART D0 data register empty as trigger */ -+} EDMA_CH_TRIGSRC_t; -+ -+/* Interrupt level */ -+typedef enum EDMA_CH_INTLVL_enum -+{ -+ EDMA_CH_INTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ EDMA_CH_INTLVL_LO_gc = (0x01<<2), /* Low level */ -+ EDMA_CH_INTLVL_MED_gc = (0x02<<2), /* Medium level */ -+ EDMA_CH_INTLVL_HI_gc = (0x03<<2), /* High level */ -+} EDMA_CH_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ -+ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ -+ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ -+ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t CH4CTRL; /* Channel 4 Control Register */ -+ register8_t CH5CTRL; /* Channel 5 Control Register */ -+ register8_t CH6CTRL; /* Channel 6 Control Register */ -+ register8_t CH7CTRL; /* Channel 7 Control Register */ -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+ register8_t DFCTRL; /* Digital Filter Control Register */ -+} EVSYS_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ -+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ -+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ -+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ -+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_XCL_UNF0_gc = (0xB0<<0), /* XCL BTC0 underflow */ -+ EVSYS_CHMUX_XCL_UNF1_gc = (0xB1<<0), /* XCL BTC1 underflow */ -+ EVSYS_CHMUX_XCL_CC0_gc = (0xB2<<0), /* XCL BTC0 capture or compare */ -+ EVSYS_CHMUX_XCL_CC1_gc = (0xB3<<0), /* XCL BTC0 capture or compare */ -+ EVSYS_CHMUX_XCL_PEC0_gc = (0xB4<<0), /* XCL PEC0 restart */ -+ EVSYS_CHMUX_XCL_PEC1_gc = (0xB5<<0), /* XCL PEC1 restart */ -+ EVSYS_CHMUX_XCL_LUT0_gc = (0xB6<<0), /* XCL LUT0 output */ -+ EVSYS_CHMUX_XCL_LUT1_gc = (0xB7<<0), /* XCL LUT1 output */ -+ EVSYS_CHMUX_TCC4_OVF_gc = (0xC0<<0), /* Timer/Counter C4 Overflow */ -+ EVSYS_CHMUX_TCC4_ERR_gc = (0xC1<<0), /* Timer/Counter C4 Error */ -+ EVSYS_CHMUX_TCC4_CCA_gc = (0xC4<<0), /* Timer/Counter C4 Compare or Capture A */ -+ EVSYS_CHMUX_TCC4_CCB_gc = (0xC5<<0), /* Timer/Counter C4 Compare or Capture B */ -+ EVSYS_CHMUX_TCC4_CCC_gc = (0xC6<<0), /* Timer/Counter C4 Compare or Capture C */ -+ EVSYS_CHMUX_TCC4_CCD_gc = (0xC7<<0), /* Timer/Counter C4 Compare or Capture D */ -+ EVSYS_CHMUX_TCC5_OVF_gc = (0xC8<<0), /* Timer/Counter C5 Overflow */ -+ EVSYS_CHMUX_TCC5_ERR_gc = (0xC9<<0), /* Timer/Counter C5 Error */ -+ EVSYS_CHMUX_TCC5_CCA_gc = (0xCC<<0), /* Timer/Counter C5 Compare or Capture A */ -+ EVSYS_CHMUX_TCC5_CCB_gc = (0xCD<<0), /* Timer/Counter C5 Compare or Capture B */ -+ EVSYS_CHMUX_TCD5_OVF_gc = (0xD8<<0), /* Timer/Counter D5 Overflow */ -+ EVSYS_CHMUX_TCD5_ERR_gc = (0xD9<<0), /* Timer/Counter D5 Error */ -+ EVSYS_CHMUX_TCD5_CCA_gc = (0xDC<<0), /* Timer/Counter D5 Compare or Capture A */ -+ EVSYS_CHMUX_TCD5_CCB_gc = (0xDD<<0), /* Timer/Counter D5 Compare or Capture B */ -+} EVSYS_CHMUX_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Prescaler Filter */ -+typedef enum EVSYS_PRESCFILT_enum -+{ -+ EVSYS_PRESCFILT_CH04_gc = (0x01<<4), /* Enable prescaler filter for either channel 0 or 4 */ -+ EVSYS_PRESCFILT_CH15_gc = (0x02<<4), /* Enable prescaler filter for either channel 1 or 5 */ -+ EVSYS_PRESCFILT_CH26_gc = (0x04<<4), /* Enable prescaler filter for either channel 2 or 6 */ -+ EVSYS_PRESCFILT_CH37_gc = (0x08<<4), /* Enable prescaler filter for either channel 3 or 7 */ -+} EVSYS_PRESCFILT_t; -+ -+/* Prescaler */ -+typedef enum EVSYS_PRESCALER_enum -+{ -+ EVSYS_PRESCALER_CLKPER_8_gc = (0x00<<0), /* CLKPER, divide by 8 */ -+ EVSYS_PRESCALER_CLKPER_64_gc = (0x01<<0), /* CLKPER, divide by 64 */ -+ EVSYS_PRESCALER_CLKPER_512_gc = (0x02<<0), /* CLKPER, divide by 512 */ -+ EVSYS_PRESCALER_CLKPER_4096_gc = (0x03<<0), /* CLKPER, divide by 4096 */ -+ EVSYS_PRESCALER_CLKPER_32768_gc = (0x04<<0), /* CLKPER, divide by 32768 */ -+} EVSYS_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ -+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ -+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ -+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ -+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} NVM_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t CORRCTRL; /* Correction Control Register */ -+ register8_t OFFSETCORR0; /* Offset Correction Register 0 */ -+ register8_t OFFSETCORR1; /* Offset Correction Register 1 */ -+ register8_t GAINCORR0; /* Gain Correction Register 0 */ -+ register8_t GAINCORR1; /* Gain Correction Register 1 */ -+ register8_t AVGCTRL; /* Average Control Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+} ADC_t; -+ -+/* Current Limitation */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -+} ADC_CURRLIMIT_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_MT12BIT_gc = (0x01<<1), /* More than 12-bit (oversapling) right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFD_gc = (0x03<<4), /* External reference on PORT D */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ -+ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ -+ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ -+ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -+ ADC_EVSEL_4_gc = (0x04<<3), /* Event Channel 4 */ -+ ADC_EVSEL_5_gc = (0x05<<3), /* Event Channel 5 */ -+ ADC_EVSEL_6_gc = (0x06<<3), /* Event Channel 6 */ -+ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel conversion */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAINL_gc = (0x02<<0), /* Differential input, gain with 4 LSB pins selection */ -+ ADC_CH_INPUTMODE_DIFFWGAINH_gc = (0x03<<0), /* Differential input, gain with 4 MSB pins selection */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 Scaled VCC */ -+ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC Output */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection when gain on 4 LSB pins */ -+typedef enum ADC_CH_MUXNEGL_enum -+{ -+ ADC_CH_MUXNEGL_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEGL_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEGL_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEGL_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEGL_GND_gc = (0x05<<0), /* PAD ground */ -+ ADC_CH_MUXNEGL_INTGND_gc = (0x07<<0), /* Internal ground */ -+} ADC_CH_MUXNEGL_t; -+ -+/* Negative input multiplexer selection when gain on 4 MSB pins */ -+typedef enum ADC_CH_MUXNEGH_enum -+{ -+ ADC_CH_MUXNEGH_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEGH_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEGH_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEGH_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+ ADC_CH_MUXNEGH_GND_gc = (0x05<<0), /* PAD ground */ -+} ADC_CH_MUXNEGH_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+} ADC_CH_MUXNEG_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* Averaged Number of Samples */ -+typedef enum ADC_SAMPNUM_enum -+{ -+ ADC_SAMPNUM_1X_gc = (0x00<<0), /* 1 Sample */ -+ ADC_SAMPNUM_2X_gc = (0x01<<0), /* 2 Samples */ -+ ADC_SAMPNUM_4X_gc = (0x02<<0), /* 4 Samples */ -+ ADC_SAMPNUM_8X_gc = (0x03<<0), /* 8 Samples */ -+ ADC_SAMPNUM_16X_gc = (0x04<<0), /* 16 Samples */ -+ ADC_SAMPNUM_32X_gc = (0x05<<0), /* 32 Samples */ -+ ADC_SAMPNUM_64X_gc = (0x06<<0), /* 64 Samples */ -+ ADC_SAMPNUM_128X_gc = (0x07<<0), /* 128 Samples */ -+ ADC_SAMPNUM_256X_gc = (0x08<<0), /* 256 Samples */ -+ ADC_SAMPNUM_512X_gc = (0x09<<0), /* 512 Samples */ -+ ADC_SAMPNUM_1024X_gc = (0x0A<<0), /* 1024 Samples */ -+} ADC_SAMPNUM_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DAC - Digital/Analog Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Digital-to-Analog Converter */ -+typedef struct DAC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t EVCTRL; /* Event Input Control */ -+ register8_t reserved_0x04; -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0GAINCAL; /* Gain Calibration */ -+ register8_t CH0OFFSETCAL; /* Offset Calibration */ -+ register8_t CH1GAINCAL; /* Gain Calibration */ -+ register8_t CH1OFFSETCAL; /* Offset Calibration */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ -+ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -+} DAC_t; -+ -+/* Output channel selection */ -+typedef enum DAC_CHSEL_enum -+{ -+ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ -+ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ -+ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -+} DAC_CHSEL_t; -+ -+/* Reference voltage selection */ -+typedef enum DAC_REFSEL_enum -+{ -+ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ -+ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ -+ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ -+ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -+} DAC_REFSEL_t; -+ -+/* Event channel selection */ -+typedef enum DAC_EVSEL_enum -+{ -+ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ -+ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ -+ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ -+ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ -+ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ -+ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ -+ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ -+ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -+} DAC_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+ register8_t CURRCTRL; /* Current Source Control Register */ -+ register8_t CURRCALIB; /* Current Source Calibration Register */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC - Real-Time Clounter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Real-Time Counter */ -+typedef struct RTC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary register */ -+ register8_t reserved_0x05; -+ register8_t CALIB; /* Calibration Register */ -+ register8_t reserved_0x07; -+ _WORDREGISTER(CNT); /* Count Register */ -+ _WORDREGISTER(PER); /* Period Register */ -+ _WORDREGISTER(COMP); /* Compare Register */ -+} RTC_t; -+ -+/* Prescaler Factor */ -+typedef enum RTC_PRESCALER_enum -+{ -+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ -+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ -+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ -+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ -+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ -+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ -+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ -+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -+} RTC_PRESCALER_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC_COMPINTLVL_enum -+{ -+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC_OVFINTLVL_enum -+{ -+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XCL - XMEGA Custom Logic -+-------------------------------------------------------------------------- -+*/ -+ -+/* XMEGA Custom Logic */ -+typedef struct XCL_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t CTRLF; /* Control Register F */ -+ register8_t CTRLG; /* Control Register G */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t PLC; /* Peripheral Lenght Control Register */ -+ register8_t CNTL; /* Counter Register Low */ -+ register8_t CNTH; /* Counter Register High */ -+ register8_t CMPL; /* Compare Register Low */ -+ register8_t CMPH; /* Compare Register High */ -+ register8_t PERCAPTL; /* Period or Capture Register Low */ -+ register8_t PERCAPTH; /* Period or Capture Register High */ -+} XCL_t; -+ -+/* LUT0 Output Enable */ -+typedef enum XCL_LUTOUTEN_enum -+{ -+ XCL_LUTOUTEN_DISABLE_gc = (0x00<<6), /* LUT0 output disabled */ -+ XCL_LUTOUTEN_PIN0_gc = (0x01<<6), /* LUT0 Output to pin 0 */ -+ XCL_LUTOUTEN_PIN4_gc = (0x02<<6), /* LUT0 Output to pin 4 */ -+} XCL_LUTOUTEN_t; -+ -+/* Port Selection */ -+typedef enum XCL_PORTSEL_enum -+{ -+ XCL_PORTSEL_PC_gc = (0x00<<4), /* Port C for LUT or USARTC0 for PEC */ -+ XCL_PORTSEL_PD_gc = (0x01<<4), /* Port D for LUT or USARTD0 for PEC */ -+} XCL_PORTSEL_t; -+ -+/* LUT Configuration */ -+typedef enum XCL_LUTCONF_enum -+{ -+ XCL_LUTCONF_2LUT2IN_gc = (0x00<<0), /* 2-Input two LUT */ -+ XCL_LUTCONF_2LUT1IN_gc = (0x01<<0), /* Two LUT with duplicated input */ -+ XCL_LUTCONF_2LUT3IN_gc = (0x02<<0), /* Two LUT with one common input */ -+ XCL_LUTCONF_1LUT3IN_gc = (0x03<<0), /* 3-Input LUT */ -+ XCL_LUTCONF_MUX_gc = (0x04<<0), /* One LUT Mux */ -+ XCL_LUTCONF_DLATCH_gc = (0x05<<0), /* One D-Latch LUT */ -+ XCL_LUTCONF_RSLATCH_gc = (0x06<<0), /* One RS-Latch LUT */ -+ XCL_LUTCONF_DFF_gc = (0x07<<0), /* One DFF LUT */ -+} XCL_LUTCONF_t; -+ -+/* Input Selection */ -+typedef enum XCL_INSEL_enum -+{ -+ XCL_INSEL_EVSYS_gc = (0x00<<6), /* Event system selected as source */ -+ XCL_INSEL_XCL_gc = (0x01<<6), /* XCL selected as source */ -+ XCL_INSEL_PINL_gc = (0x02<<6), /* LSB port pin selected as source */ -+ XCL_INSEL_PINH_gc = (0x03<<6), /* MSB port pin selected as source */ -+} XCL_INSEL_t; -+ -+/* Delay Configuration on LUT */ -+typedef enum XCL_DLYCONF_enum -+{ -+ XCL_DLYCONF_DISABLE_gc = (0x00<<2), /* Delay element disabled */ -+ XCL_DLYCONF_IN_gc = (0x01<<2), /* Delay enabled on LUT input */ -+ XCL_DLYCONF_OUT_gc = (0x02<<2), /* Delay enabled on LUT output */ -+} XCL_DLYCONF_t; -+ -+/* Delay Selection */ -+typedef enum XCL_DLYSEL_enum -+{ -+ XCL_DLYSEL_DLY11_gc = (0x00<<4), /* One cycle delay for each LUT1 and LUT0 */ -+ XCL_DLYSEL_DLY12_gc = (0x01<<4), /* One cycle delay for LUT1 and two cycles for LUT0 */ -+ XCL_DLYSEL_DLY21_gc = (0x02<<4), /* Two cycles delay for LUT1 and one cycle for LUT0 */ -+ XCL_DLYSEL_DLY22_gc = (0x03<<4), /* Two cycle delays for each LUT1 and LUT0 */ -+} XCL_DLYSEL_t; -+ -+/* Clock Selection */ -+typedef enum XCL_CLKSEL_enum -+{ -+ XCL_CLKSEL_OFF_gc = (0x00<<0), /* OFF */ -+ XCL_CLKSEL_DIV1_gc = (0x01<<0), /* Prescaler clk */ -+ XCL_CLKSEL_DIV2_gc = (0x02<<0), /* Prescaler clk/2 */ -+ XCL_CLKSEL_DIV4_gc = (0x03<<0), /* Prescaler clk/4 */ -+ XCL_CLKSEL_DIV8_gc = (0x04<<0), /* Prescaler clk/8 */ -+ XCL_CLKSEL_DIV64_gc = (0x05<<0), /* Prescaler clk/64 */ -+ XCL_CLKSEL_DIV256_gc = (0x06<<0), /* Prescaler clk/256 */ -+ XCL_CLKSEL_DIV1024_gc = (0x07<<0), /* Prescaler clk/1024 */ -+ XCL_CLKSEL_EVCH0_gc = (0x08<<0), /* Event channel 0 */ -+ XCL_CLKSEL_EVCH1_gc = (0x09<<0), /* Event channel 1 */ -+ XCL_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event channel 2 */ -+ XCL_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event channel 3 */ -+ XCL_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event channel 4 */ -+ XCL_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event channel 5 */ -+ XCL_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event channel 6 */ -+ XCL_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event channel 7 */ -+} XCL_CLKSEL_t; -+ -+/* Timer/Counter Command Selection */ -+typedef enum XCL_CMDSEL_enum -+{ -+ XCL_CMDSEL_NONE_gc = (0x00<<7), /* None */ -+ XCL_CMDSEL_RESTART_gc = (0x01<<7), /* Force restart */ -+} XCL_CMDSEL_t; -+ -+/* Timer/Counter Selection */ -+typedef enum XCL_TCSEL_enum -+{ -+ XCL_TCSEL_TC16_gc = (0x00<<4), /* 16-bit timer/counter */ -+ XCL_TCSEL_BTC0_gc = (0x01<<4), /* One 8-bit timer/counter */ -+ XCL_TCSEL_BTC01_gc = (0x02<<4), /* Two 8-bit timer/counters */ -+ XCL_TCSEL_BTC0PEC1_gc = (0x03<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ -+ XCL_TCSEL_PEC0BTC1_gc = (0x04<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ -+ XCL_TCSEL_PEC01_gc = (0x05<<4), /* Two 8-bit peripheral counters */ -+ XCL_TCSEL_BTC0PEC2_gc = (0x06<<4), /* One 8-bit timer/counter and two 4-bit peripheral counters */ -+} XCL_TCSEL_t; -+ -+/* Timer/Counter Mode */ -+typedef enum XCL_TCMODE_enum -+{ -+ XCL_TCMODE_NORMAL_gc = (0x00<<0), /* Normal mode with compare/period */ -+ XCL_TCMODE_CAPT_gc = (0x01<<0), /* Capture mode */ -+ XCL_TCMODE_PWM_gc = (0x02<<0), /* Single Slope PWM */ -+} XCL_TCMODE_t; -+ -+/* Compare Output Value Timer */ -+typedef enum XCL_CMPEN_enum -+{ -+ XCL_CMPEN_CLEAR_gc = (0x00<<5), /* Clear WG Output */ -+ XCL_CMPEN_SET_gc = (0x01<<5), /* Set WG Output */ -+} XCL_CMPEN_t; -+ -+/* Command Enable */ -+typedef enum XCL_CMDEN_enum -+{ -+ XCL_CMDEN_DISABLE_gc = (0x00<<6), /* Command Ignored */ -+ XCL_CMDEN_CMD0_gc = (0x01<<6), /* Command valid for timer/counter 0 */ -+ XCL_CMDEN_CMD1_gc = (0x02<<6), /* Command valid for timer/counter 1 */ -+ XCL_CMDEN_CMD01_gc = (0x03<<6), /* Command valid for both timer/counter 0 and 1 */ -+} XCL_CMDEN_t; -+ -+/* Timer/Counter Event Source Selection */ -+typedef enum XCL_EVSRC_enum -+{ -+ XCL_EVSRC_EVCH0_gc = (0x00<<0), /* Event channel 0 */ -+ XCL_EVSRC_EVCH1_gc = (0x01<<0), /* Event channel 1 */ -+ XCL_EVSRC_EVCH2_gc = (0x02<<0), /* Event channel 2 */ -+ XCL_EVSRC_EVCH3_gc = (0x03<<0), /* Event channel 3 */ -+ XCL_EVSRC_EVCH4_gc = (0x04<<0), /* Event channel 4 */ -+ XCL_EVSRC_EVCH5_gc = (0x05<<0), /* Event channel 5 */ -+ XCL_EVSRC_EVCH6_gc = (0x06<<0), /* Event channel 6 */ -+ XCL_EVSRC_EVCH7_gc = (0x07<<0), /* Event channel 7 */ -+} XCL_EVSRC_t; -+ -+/* Timer/Counter Event Action Selection */ -+typedef enum XCL_EVACT_enum -+{ -+ XCL_EVACT_INPUT_gc = (0x00<<5), /* Input Capture */ -+ XCL_EVACT_FREQ_gc = (0x01<<5), /* Frequency Capture */ -+ XCL_EVACT_PW_gc = (0x02<<5), /* Pulse Width Capture */ -+ XCL_EVACT_RESTART_gc = (0x03<<5), /* Restart timer/counter */ -+} XCL_EVACT_t; -+ -+/* Underflow Interrupt level */ -+typedef enum XCL_UNF_INTLVL_enum -+{ -+ XCL_UNF_INTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ XCL_UNF_INTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ XCL_UNF_INTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ XCL_UNF_INTLVL_HI_gc = (0x03<<2), /* High Level */ -+} XCL_UNF_INTLVL_t; -+ -+/* Compare/Capture Interrupt level */ -+typedef enum XCL_CC_INTLVL_enum -+{ -+ XCL_CC_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ XCL_CC_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ XCL_CC_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ XCL_CC_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} XCL_CC_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* */ -+typedef struct TWI_TIMEOUT_struct -+{ -+ register8_t TOS; /* Timeout Status Register */ -+ register8_t TOCONF; /* Timeout Configuration Register */ -+} TWI_TIMEOUT_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+ TWI_TIMEOUT_t TIMEOUT; /* TWI SMBUS timeout module */ -+} TWI_t; -+ -+/* SDA Hold Time */ -+typedef enum TWI_SDAHOLD_enum -+{ -+ TWI_SDAHOLD_OFF_gc = (0x00<<4), /* SDA Hold Time off */ -+ TWI_SDAHOLD_50NS_gc = (0x01<<4), /* SDA Hold Time 50 ns */ -+ TWI_SDAHOLD_300NS_gc = (0x02<<4), /* SDA Hold Time 300 ns */ -+ TWI_SDAHOLD_400NS_gc = (0x03<<4), /* SDA Hold Time 400 ns */ -+} TWI_SDAHOLD_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+/* Master Timeout */ -+typedef enum TWI_MASTER_TTIMEOUT_enum -+{ -+ TWI_MASTER_TTIMEOUT_25MS_gc = (0x00<<0), /* 25 Milliseconds */ -+ TWI_MASTER_TTIMEOUT_24MS_gc = (0x01<<0), /* 24 Milliseconds */ -+ TWI_MASTER_TTIMEOUT_23MS_gc = (0x02<<0), /* 23 Milliseconds */ -+ TWI_MASTER_TTIMEOUT_22MS_gc = (0x03<<0), /* 22 Milliseconds */ -+ TWI_MASTER_TTIMEOUT_26MS_gc = (0x04<<0), /* 26 Milliseconds */ -+ TWI_MASTER_TTIMEOUT_27MS_gc = (0x05<<0), /* 27 Milliseconds */ -+ TWI_MASTER_TTIMEOUT_28MS_gc = (0x06<<0), /* 28 Milliseconds */ -+ TWI_MASTER_TTIMEOUT_29MS_gc = (0x07<<0), /* 29 Milliseconds */ -+} TWI_MASTER_TTIMEOUT_t; -+ -+/* Slave Ttimeout */ -+typedef enum TWI_SLAVE_TTIMEOUT_enum -+{ -+ TWI_SLAVE_TTIMEOUT_25MS_gc = (0x00<<5), /* 25 Milliseconds */ -+ TWI_SLAVE_TTIMEOUT_24MS_gc = (0x01<<5), /* 24 Milliseconds */ -+ TWI_SLAVE_TTIMEOUT_23MS_gc = (0x02<<5), /* 23 Milliseconds */ -+ TWI_SLAVE_TTIMEOUT_22MS_gc = (0x03<<5), /* 22 Milliseconds */ -+ TWI_SLAVE_TTIMEOUT_26MS_gc = (0x04<<5), /* 26 Milliseconds */ -+ TWI_SLAVE_TTIMEOUT_27MS_gc = (0x05<<5), /* 27 Milliseconds */ -+ TWI_SLAVE_TTIMEOUT_28MS_gc = (0x06<<5), /* 28 Milliseconds */ -+ TWI_SLAVE_TTIMEOUT_29MS_gc = (0x07<<5), /* 29 Milliseconds */ -+} TWI_SLAVE_TTIMEOUT_t; -+ -+/* Master/Slave Extend Timeout */ -+typedef enum TWI_MASTER_TMSEXT_enum -+{ -+ TWI_MASTER_TMSEXT_10MS25MS_gc = (0x00<<3), /* Tmext 10ms Tsext 25ms */ -+ TWI_MASTER_TMSEXT_9MS24MS_gc = (0x01<<3), /* Tmext 9ms Tsext 24ms */ -+ TWI_MASTER_TMSEXT_11MS26MS_gc = (0x02<<3), /* Tmext 11ms Tsext 26ms */ -+ TWI_MASTER_TMSEXT_12MS27MS_gc = (0x03<<3), /* Tmext 12ms Tsext 27ms */ -+} TWI_MASTER_TMSEXT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTMASK; /* Port Interrupt Mask */ -+ register8_t reserved_0x0B; -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t REMAP; /* Pin Remap Register */ -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Port Interrupt Level */ -+typedef enum PORT_INTLVL_enum -+{ -+ PORT_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INTLVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_FORCE_ENABLE_gc = (0x06<<0), /* Digital Input Buffer Forced Enable */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 4 */ -+typedef struct TC4_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t CTRLF; /* Control Register F */ -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t CTRLHCLR; /* Control Register H Clear */ -+ register8_t CTRLHSET; /* Control Register H Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC4_t; -+ -+ -+/* 16-bit Timer/Counter 5 */ -+typedef struct TC5_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t CTRLF; /* Control Register F */ -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t CTRLHCLR; /* Control Register H Clear */ -+ register8_t CTRLHSET; /* Control Register H Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+} TC5_t; -+ -+/* Clock Selection */ -+typedef enum TC45_CLKSEL_enum -+{ -+ TC45_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC45_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC45_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC45_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC45_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC45_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC45_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC45_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC45_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC45_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC45_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC45_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC45_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC45_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC45_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC45_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC45_CLKSEL_t; -+ -+/* Byte Mode */ -+typedef enum TC45_BYTEM_enum -+{ -+ TC45_BYTEM_NORMAL_gc = (0x00<<6), /* 16-bit mode */ -+ TC45_BYTEM_BYTEMODE_gc = (0x01<<6), /* Timer/Counter Operating in Byte Mode Only */ -+} TC45_BYTEM_t; -+ -+/* Circular Enable Mode */ -+typedef enum TC45_CIRCEN_enum -+{ -+ TC45_CIRCEN_DISABLE_gc = (0x00<<4), /* Circular Buffer Disabled */ -+ TC45_CIRCEN_PER_gc = (0x01<<4), /* Circular Buffer Enabled on PER/PERBUF */ -+ TC45_CIRCEN_CCA_gc = (0x02<<4), /* Circular Buffer Enabled on CCA/CCABUF */ -+ TC45_CIRCEN_BOTH_gc = (0x03<<4), /* Circular Buffer Enabled on All Buffered Registers */ -+} TC45_CIRCEN_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC45_WGMODE_enum -+{ -+ TC45_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC45_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC45_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ -+ TC45_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC45_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Both */ -+ TC45_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC45_WGMODE_t; -+ -+/* Event Action */ -+typedef enum TC45_EVACT_enum -+{ -+ TC45_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC45_EVACT_FMODE1_gc = (0x01<<5), /* Fault Mode 1 capture */ -+ TC45_EVACT_FMODE2_gc = (0x02<<5), /* Fault Mode 2 capture */ -+ TC45_EVACT_UPDOWN_gc = (0x03<<5), /* Up/down count */ -+ TC45_EVACT_QDEC_gc = (0x04<<5), /* Quadrature decode */ -+ TC45_EVACT_RESTART_gc = (0x05<<5), /* Restart */ -+ TC45_EVACT_PWF_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC45_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC45_EVSEL_enum -+{ -+ TC45_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC45_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC45_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC45_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC45_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC45_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC45_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC45_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC45_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC45_EVSEL_t; -+ -+/* Compare or Capture Channel A Mode */ -+typedef enum TC45_CCAMODE_enum -+{ -+ TC45_CCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ -+ TC45_CCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ -+ TC45_CCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ -+ TC45_CCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -+} TC45_CCAMODE_t; -+ -+/* Compare or Capture Channel B Mode */ -+typedef enum TC45_CCBMODE_enum -+{ -+ TC45_CCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ -+ TC45_CCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ -+ TC45_CCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ -+ TC45_CCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -+} TC45_CCBMODE_t; -+ -+/* Compare or Capture Channel C Mode */ -+typedef enum TC45_CCCMODE_enum -+{ -+ TC45_CCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ -+ TC45_CCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ -+ TC45_CCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ -+ TC45_CCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -+} TC45_CCCMODE_t; -+ -+/* Compare or Capture Channel D Mode */ -+typedef enum TC45_CCDMODE_enum -+{ -+ TC45_CCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ -+ TC45_CCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ -+ TC45_CCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ -+ TC45_CCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -+} TC45_CCDMODE_t; -+ -+/* Compare or Capture Low Channel A Mode */ -+typedef enum TC45_LCCAMODE_enum -+{ -+ TC45_LCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ -+ TC45_LCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ -+ TC45_LCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ -+ TC45_LCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -+} TC45_LCCAMODE_t; -+ -+/* Compare or Capture Low Channel B Mode */ -+typedef enum TC45_LCCBMODE_enum -+{ -+ TC45_LCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ -+ TC45_LCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ -+ TC45_LCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ -+ TC45_LCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -+} TC45_LCCBMODE_t; -+ -+/* Compare or Capture Low Channel C Mode */ -+typedef enum TC45_LCCCMODE_enum -+{ -+ TC45_LCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ -+ TC45_LCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ -+ TC45_LCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ -+ TC45_LCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -+} TC45_LCCCMODE_t; -+ -+/* Compare or Capture Low Channel D Mode */ -+typedef enum TC45_LCCDMODE_enum -+{ -+ TC45_LCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ -+ TC45_LCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ -+ TC45_LCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ -+ TC45_LCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -+} TC45_LCCDMODE_t; -+ -+/* Compare or Capture High Channel A Mode */ -+typedef enum TC45_HCCAMODE_enum -+{ -+ TC45_HCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ -+ TC45_HCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ -+ TC45_HCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ -+ TC45_HCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -+} TC45_HCCAMODE_t; -+ -+/* Compare or Capture High Channel B Mode */ -+typedef enum TC45_HCCBMODE_enum -+{ -+ TC45_HCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ -+ TC45_HCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ -+ TC45_HCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ -+ TC45_HCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -+} TC45_HCCBMODE_t; -+ -+/* Compare or Capture High Channel C Mode */ -+typedef enum TC45_HCCCMODE_enum -+{ -+ TC45_HCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ -+ TC45_HCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ -+ TC45_HCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ -+ TC45_HCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -+} TC45_HCCCMODE_t; -+ -+/* Compare or Capture High Channel D Mode */ -+typedef enum TC45_HCCDMODE_enum -+{ -+ TC45_HCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ -+ TC45_HCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ -+ TC45_HCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ -+ TC45_HCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -+} TC45_HCCDMODE_t; -+ -+/* Timer Trigger Restart Interrupt Level */ -+typedef enum TC45_TRGINTLVL_enum -+{ -+ TC45_TRGINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC45_TRGINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC45_TRGINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC45_TRGINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC45_TRGINTLVL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC45_ERRINTLVL_enum -+{ -+ TC45_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC45_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC45_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC45_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC45_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC45_OVFINTLVL_enum -+{ -+ TC45_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC45_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC45_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC45_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC45_OVFINTLVL_t; -+ -+/* Compare or Capture Channel A Interrupt Level */ -+typedef enum TC45_CCAINTLVL_enum -+{ -+ TC45_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC45_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC45_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC45_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC45_CCAINTLVL_t; -+ -+/* Compare or Capture Channel B Interrupt Level */ -+typedef enum TC45_CCBINTLVL_enum -+{ -+ TC45_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC45_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC45_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC45_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC45_CCBINTLVL_t; -+ -+/* Compare or Capture Channel C Interrupt Level */ -+typedef enum TC45_CCCINTLVL_enum -+{ -+ TC45_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC45_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC45_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC45_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC45_CCCINTLVL_t; -+ -+/* Compare or Capture Channel D Interrupt Level */ -+typedef enum TC45_CCDINTLVL_enum -+{ -+ TC45_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC45_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC45_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC45_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC45_CCDINTLVL_t; -+ -+/* Compare or Capture Low Channel A Interrupt Level */ -+typedef enum TC45_LCCAINTLVL_enum -+{ -+ TC45_LCCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC45_LCCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC45_LCCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC45_LCCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC45_LCCAINTLVL_t; -+ -+/* Compare or Capture Low Channel B Interrupt Level */ -+typedef enum TC45_LCCBINTLVL_enum -+{ -+ TC45_LCCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC45_LCCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC45_LCCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC45_LCCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC45_LCCBINTLVL_t; -+ -+/* Compare or Capture Low Channel C Interrupt Level */ -+typedef enum TC45_LCCCINTLVL_enum -+{ -+ TC45_LCCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC45_LCCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC45_LCCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC45_LCCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC45_LCCCINTLVL_t; -+ -+/* Compare or Capture Low Channel D Interrupt Level */ -+typedef enum TC45_LCCDINTLVL_enum -+{ -+ TC45_LCCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC45_LCCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC45_LCCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC45_LCCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC45_LCCDINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC45_CMD_enum -+{ -+ TC45_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC45_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC45_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC45_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC45_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FAULT - Fault Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fault Extension */ -+typedef struct FAULT_struct -+{ -+ register8_t CTRLA; /* Control A Register */ -+ register8_t CTRLB; /* Control B Register */ -+ register8_t CTRLC; /* Control C Register */ -+ register8_t CTRLD; /* Control D Register */ -+ register8_t CTRLE; /* Control E Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G set */ -+} FAULT_t; -+ -+/* Ramp Mode Selection */ -+typedef enum FAULT_RAMP_enum -+{ -+ FAULT_RAMP_RAMP1_gc = (0x00<<6), /* Normal Mode */ -+ FAULT_RAMP_RAMP2_gc = (0x02<<6), /* RAMP2 Mode */ -+} FAULT_RAMP_t; -+ -+/* Fault E Input Source Selection */ -+typedef enum FAULT_SRCE_enum -+{ -+ FAULT_SRCE_DISABLE_gc = (0x00<<0), /* Fault Protection Disabled */ -+ FAULT_SRCE_CHN_gc = (0x01<<0), /* Event Channel n */ -+ FAULT_SRCE_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ -+ FAULT_SRCE_CHN2_gc = (0x03<<0), /* Event Channel n+2 */ -+} FAULT_SRCE_t; -+ -+/* Fault A Halt Action Selection */ -+typedef enum FAULT_HALTA_enum -+{ -+ FAULT_HALTA_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ -+ FAULT_HALTA_HW_gc = (0x01<<5), /* Hardware Halt Action */ -+ FAULT_HALTA_SW_gc = (0x02<<5), /* Software Halt Action */ -+} FAULT_HALTA_t; -+ -+/* Fault A Source Selection */ -+typedef enum FAULT_SRCA_enum -+{ -+ FAULT_SRCA_DISABLE_gc = (0x00<<0), /* Fault A Disabled */ -+ FAULT_SRCA_CHN_gc = (0x01<<0), /* Event Channel n */ -+ FAULT_SRCA_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ -+ FAULT_SRCA_LINK_gc = (0x03<<0), /* Fault A linked to Fault B State from previous cycle */ -+} FAULT_SRCA_t; -+ -+/* Fault B Halt Action Selection */ -+typedef enum FAULT_HALTB_enum -+{ -+ FAULT_HALTB_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ -+ FAULT_HALTB_HW_gc = (0x01<<5), /* Hardware Halt Action */ -+ FAULT_HALTB_SW_gc = (0x02<<5), /* Software Halt Action */ -+} FAULT_HALTB_t; -+ -+/* Fault B Source Selection */ -+typedef enum FAULT_SRCB_enum -+{ -+ FAULT_SRCB_DISABLE_gc = (0x00<<0), /* Fault B disabled */ -+ FAULT_SRCB_CHN_gc = (0x01<<0), /* Event Channel n */ -+ FAULT_SRCB_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ -+ FAULT_SRCB_LINK_gc = (0x03<<0), /* Fault B linked to Fault A State from previous cycle */ -+} FAULT_SRCB_t; -+ -+/* Channel index Command */ -+typedef enum FAULT_IDXCMD_enum -+{ -+ FAULT_IDXCMD_DISABLE_gc = (0x00<<3), /* Command Disabled */ -+ FAULT_IDXCMD_SET_gc = (0x01<<3), /* Force Cycle B in Next Cycle */ -+ FAULT_IDXCMD_CLEAR_gc = (0x02<<3), /* Force Cycle A in Next Cycle */ -+ FAULT_IDXCMD_HOLD_gc = (0x03<<3), /* Hold Current Cycle Index in Next Cycle */ -+} FAULT_IDXCMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WEX - Waveform Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Waveform Extension */ -+typedef struct WEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t DTBOTH; /* Dead-time Concurrent Write to Both Sides Register */ -+ register8_t DTLS; /* Dead-time Low Side Register */ -+ register8_t DTHS; /* Dead-time High Side Register */ -+ register8_t STATUSCLR; /* Status Clear Register */ -+ register8_t STATUSSET; /* Status Set Register */ -+ register8_t SWAP; /* Swap Register */ -+ register8_t PGO; /* Pattern Generation Override Register */ -+ register8_t PGV; /* Pattern Generation Value Register */ -+ register8_t reserved_0x09; -+ register8_t SWAPBUF; /* Dead Time Low Side Buffer */ -+ register8_t PGOBUF; /* Pattern Generation Overwrite Buffer Register */ -+ register8_t PGVBUF; /* Pattern Generation Value Buffer Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t OUTOVDIS; /* Output Override Disable Register */ -+} WEX_t; -+ -+/* Output Matrix Mode */ -+typedef enum WEX_OTMX_enum -+{ -+ WEX_OTMX_DEFAULT_gc = (0x00<<4), /* Default Ouput Matrix Mode */ -+ WEX_OTMX_FIRST_gc = (0x01<<4), /* First Output matrix Mode */ -+ WEX_OTMX_SECOND_gc = (0x02<<4), /* Second Output matrix Mode */ -+ WEX_OTMX_THIRD_gc = (0x03<<4), /* Third Output matrix Mode */ -+ WEX_OTMX_FOURTH_gc = (0x04<<4), /* Fourth Output matrix Mode */ -+} WEX_OTMX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+HIRES - High-Resolution Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+} HIRES_t; -+ -+/* High Resolution Plus Mode */ -+typedef enum HIRES_HRPLUS_enum -+{ -+ HIRES_HRPLUS_NONE_gc = (0x00<<2), /* No Hi-Res Plus */ -+ HIRES_HRPLUS_HRP4_gc = (0x01<<2), /* Hi-Res Plus enabled on Timer 4 */ -+ HIRES_HRPLUS_HRP5_gc = (0x02<<2), /* Hi-Res Plus enabled on Timer 5 */ -+ HIRES_HRPLUS_BOTH_gc = (0x03<<2), /* Hi-Res Plus enabled on Timer 4 and 5 */ -+} HIRES_HRPLUS_t; -+ -+/* High Resolution Mode */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Hi-Res */ -+ HIRES_HREN_HRP4_gc = (0x01<<0), /* Hi-Res enabled on Timer 4 */ -+ HIRES_HREN_HRP5_gc = (0x02<<0), /* Hi-Res enabled on Timer 5 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Hi-Res enabled on Timer 4 and 5 */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Start Interrupt level */ -+typedef enum USART_RXSINTLVL_enum -+{ -+ USART_RXSINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_RXSINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_RXSINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_RXSINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_RXSINTLVL_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+/* Encoding and Decoding Type */ -+typedef enum USART_DECTYPE_enum -+{ -+ USART_DECTYPE_DATA_gc = (0x00<<4), /* DATA Field Encoding */ -+ USART_DECTYPE_SDATA_gc = (0x02<<4), /* Start and Data Fields Encoding */ -+ USART_DECTYPE_NOTSDATA_gc = (0x03<<4), /* Start and Data Fields Encoding, with invertion in START field */ -+} USART_DECTYPE_t; -+ -+/* XCL LUT Action */ -+typedef enum USART_LUTACT_enum -+{ -+ USART_LUTACT_OFF_gc = (0x00<<2), /* Standard Frame Configuration */ -+ USART_LUTACT_RX_gc = (0x01<<2), /* Receiver Decoding Enabled */ -+ USART_LUTACT_TX_gc = (0x02<<2), /* Transmitter Encoding Enabled */ -+ USART_LUTACT_BOTH_gc = (0x03<<2), /* Both Encoding and Decoding Enabled */ -+} USART_LUTACT_t; -+ -+/* XCL Peripheral Counter Action */ -+typedef enum USART_PECACT_enum -+{ -+ USART_PECACT_OFF_gc = (0x00<<0), /* Standard Mode */ -+ USART_PECACT_PEC0_gc = (0x01<<0), /* Variable Data Lenght in Reception */ -+ USART_PECACT_PEC1_gc = (0x02<<0), /* Variable Data Lenght in Transmission */ -+ USART_PECACT_PERC01_gc = (0x03<<0), /* Variable Data Lenght in both Reception and Transmission */ -+} USART_PECACT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface with Buffer Modes */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t CTRLB; /* Control Register B */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0, base clock at "0", sampling on leading edge (rising) & set-up on trailling edge (falling). */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1, base clock at "0", set-up on leading edge (rising) & sampling on trailling edge (falling). */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2, base clock at "1", sampling on leading edge (falling) & set-up on trailling edge (rising). */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3, base clock at "1", set-up on leading edge (falling) & sampling on trailling edge (rising). */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* If CLK2X=1 CLKper/2, else (CLK2X=0) CLKper/4. */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* If CLK2X=1 CLKper/8, else (CLK2X=0) CLKper/16. */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* If CLK2X=1 CLKper/32, else (CLK2X=0) CLKper/64. */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* If CLK2X=1 CLKper/64, else (CLK2X=0) CLKper/128. */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+/* Buffer Modes */ -+typedef enum SPI_BUFMODE_enum -+{ -+ SPI_BUFMODE_OFF_gc = (0x00<<6), /* SPI Unbuffered Mode */ -+ SPI_BUFMODE_BUFMODE1_gc = (0x02<<6), /* Buffer Mode 1 (with dummy byte) */ -+ SPI_BUFMODE_BUFMODE2_gc = (0x03<<6), /* Buffer Mode 2 (no dummy byte) */ -+} SPI_BUFMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ -+ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ -+ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ -+ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -+} IRDA_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t reserved_0x00; -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+ register8_t FUSEBYTE6; /* Fault State */ -+} NVM_FUSES_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BOD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC8M; /* RCOSC 8MHz Calibration Value */ -+ register8_t reserved_0x01; -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t ROOMTEMP; /* Temperature corresponds to TEMPSENSE3/2 */ -+ register8_t HOTTEMP; /* Temperature corresponds to TEMPSENSE1/0 */ -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t ACACURRCAL; /* ACA Current Calibration Byte */ -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t TEMPSENSE2; /* Temperature Sensor Calibration Byte 2 */ -+ register8_t TEMPSENSE3; /* Temperature Sensor Calibration Byte 3 */ -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ -+ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ -+ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+} NVM_PROD_SIGNATURES_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define EDMA (*(EDMA_t *) 0x0100) /* Enhanced DMA Controller */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -+#define XCL (*(XCL_t *) 0x0460) /* XMEGA Custom Logic */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC4 (*(TC4_t *) 0x0800) /* 16-bit Timer/Counter 4 */ -+#define TCC5 (*(TC5_t *) 0x0840) /* 16-bit Timer/Counter 5 */ -+#define FAULTC4 (*(FAULT_t *) 0x0880) /* Fault Extension */ -+#define FAULTC5 (*(FAULT_t *) 0x0890) /* Fault Extension */ -+#define WEXC (*(WEX_t *) 0x08A0) /* Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x08B0) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08E0) /* Serial Peripheral Interface with Buffer Modes */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define TCD5 (*(TC5_t *) 0x0940) /* 16-bit Timer/Counter 5 */ -+#define USARTD0 (*(USART_t *) 0x09C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+#define FUSE_FUSEBYTE6 _SFR_MEM8(0x0006) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC8M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_ROOMTEMP _SFR_MEM8(0x001E) -+#define PRODSIGNATURES_HOTTEMP _SFR_MEM8(0x001F) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_ACACURRCAL _SFR_MEM8(0x0028) -+#define PRODSIGNATURES_TEMPSENSE2 _SFR_MEM8(0x002C) -+#define PRODSIGNATURES_TEMPSENSE3 _SFR_MEM8(0x002D) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -+#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -+#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -+#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+#define OSC_RC8MCAL _SFR_MEM8(0x0057) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPD _SFR_MEM8(0x0074) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_ANAINIT _SFR_MEM8(0x0097) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_WEXLOCK _SFR_MEM8(0x0099) -+#define MCU_FAULTLOCK _SFR_MEM8(0x009A) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_CLKOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_ACEVOUT _SFR_MEM8(0x00B6) -+#define PORTCFG_SRLCTRL _SFR_MEM8(0x00B7) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* EDMA - Enhanced DMA Controller */ -+#define EDMA_CTRL _SFR_MEM8(0x0100) -+#define EDMA_INTFLAGS _SFR_MEM8(0x0103) -+#define EDMA_STATUS _SFR_MEM8(0x0104) -+#define EDMA_TEMP _SFR_MEM8(0x0106) -+#define EDMA_CH0_CTRLA _SFR_MEM8(0x0110) -+#define EDMA_CH0_CTRLB _SFR_MEM8(0x0111) -+#define EDMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -+#define EDMA_CH0_DESTADDRCTRL _SFR_MEM8(0x0113) -+#define EDMA_CH0_TRIGSRC _SFR_MEM8(0x0114) -+#define EDMA_CH0_TRFCNT _SFR_MEM16(0x0116) -+#define EDMA_CH0_ADDR _SFR_MEM16(0x0118) -+#define EDMA_CH0_DESTADDR _SFR_MEM16(0x011C) -+#define EDMA_CH1_CTRLA _SFR_MEM8(0x0120) -+#define EDMA_CH1_CTRLB _SFR_MEM8(0x0121) -+#define EDMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -+#define EDMA_CH1_DESTADDRCTRL _SFR_MEM8(0x0123) -+#define EDMA_CH1_TRIGSRC _SFR_MEM8(0x0124) -+#define EDMA_CH1_TRFCNT _SFR_MEM16(0x0126) -+#define EDMA_CH1_ADDR _SFR_MEM16(0x0128) -+#define EDMA_CH1_DESTADDR _SFR_MEM16(0x012C) -+#define EDMA_CH2_CTRLA _SFR_MEM8(0x0130) -+#define EDMA_CH2_CTRLB _SFR_MEM8(0x0131) -+#define EDMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -+#define EDMA_CH2_DESTADDRCTRL _SFR_MEM8(0x0133) -+#define EDMA_CH2_TRIGSRC _SFR_MEM8(0x0134) -+#define EDMA_CH2_TRFCNT _SFR_MEM16(0x0136) -+#define EDMA_CH2_ADDR _SFR_MEM16(0x0138) -+#define EDMA_CH2_DESTADDR _SFR_MEM16(0x013C) -+#define EDMA_CH3_CTRLA _SFR_MEM8(0x0140) -+#define EDMA_CH3_CTRLB _SFR_MEM8(0x0141) -+#define EDMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -+#define EDMA_CH3_DESTADDRCTRL _SFR_MEM8(0x0143) -+#define EDMA_CH3_TRIGSRC _SFR_MEM8(0x0144) -+#define EDMA_CH3_TRFCNT _SFR_MEM16(0x0146) -+#define EDMA_CH3_ADDR _SFR_MEM16(0x0148) -+#define EDMA_CH3_DESTADDR _SFR_MEM16(0x014C) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -+#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -+#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -+#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -+#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -+#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -+#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+#define EVSYS_DFCTRL _SFR_MEM8(0x0192) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCA_CTRLA _SFR_MEM8(0x0200) -+#define ADCA_CTRLB _SFR_MEM8(0x0201) -+#define ADCA_REFCTRL _SFR_MEM8(0x0202) -+#define ADCA_EVCTRL _SFR_MEM8(0x0203) -+#define ADCA_PRESCALER _SFR_MEM8(0x0204) -+#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -+#define ADCA_TEMP _SFR_MEM8(0x0207) -+#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) -+#define ADCA_CAL _SFR_MEM16(0x020C) -+#define ADCA_CH0RES _SFR_MEM16(0x0210) -+#define ADCA_CMP _SFR_MEM16(0x0218) -+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -+#define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -+#define ADCA_CH0_CORRCTRL _SFR_MEM8(0x0227) -+#define ADCA_CH0_OFFSETCORR0 _SFR_MEM8(0x0228) -+#define ADCA_CH0_OFFSETCORR1 _SFR_MEM8(0x0229) -+#define ADCA_CH0_GAINCORR0 _SFR_MEM8(0x022A) -+#define ADCA_CH0_GAINCORR1 _SFR_MEM8(0x022B) -+#define ADCA_CH0_AVGCTRL _SFR_MEM8(0x022C) -+ -+/* DAC - Digital-to-Analog Converter */ -+#define DACA_CTRLA _SFR_MEM8(0x0300) -+#define DACA_CTRLB _SFR_MEM8(0x0301) -+#define DACA_CTRLC _SFR_MEM8(0x0302) -+#define DACA_EVCTRL _SFR_MEM8(0x0303) -+#define DACA_STATUS _SFR_MEM8(0x0305) -+#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) -+#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) -+#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) -+#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) -+#define DACA_CH0DATA _SFR_MEM16(0x0318) -+#define DACA_CH1DATA _SFR_MEM16(0x031A) -+ -+/* AC - Analog Comparator */ -+#define ACA_AC0CTRL _SFR_MEM8(0x0380) -+#define ACA_AC1CTRL _SFR_MEM8(0x0381) -+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -+#define ACA_CTRLA _SFR_MEM8(0x0384) -+#define ACA_CTRLB _SFR_MEM8(0x0385) -+#define ACA_WINCTRL _SFR_MEM8(0x0386) -+#define ACA_STATUS _SFR_MEM8(0x0387) -+#define ACA_CURRCTRL _SFR_MEM8(0x0388) -+#define ACA_CURRCALIB _SFR_MEM8(0x0389) -+ -+/* RTC - Real-Time Counter */ -+#define RTC_CTRL _SFR_MEM8(0x0400) -+#define RTC_STATUS _SFR_MEM8(0x0401) -+#define RTC_INTCTRL _SFR_MEM8(0x0402) -+#define RTC_INTFLAGS _SFR_MEM8(0x0403) -+#define RTC_TEMP _SFR_MEM8(0x0404) -+#define RTC_CALIB _SFR_MEM8(0x0406) -+#define RTC_CNT _SFR_MEM16(0x0408) -+#define RTC_PER _SFR_MEM16(0x040A) -+#define RTC_COMP _SFR_MEM16(0x040C) -+ -+/* XCL - XMEGA Custom Logic */ -+#define XCL_CTRLA _SFR_MEM8(0x0460) -+#define XCL_CTRLB _SFR_MEM8(0x0461) -+#define XCL_CTRLC _SFR_MEM8(0x0462) -+#define XCL_CTRLD _SFR_MEM8(0x0463) -+#define XCL_CTRLE _SFR_MEM8(0x0464) -+#define XCL_CTRLF _SFR_MEM8(0x0465) -+#define XCL_CTRLG _SFR_MEM8(0x0466) -+#define XCL_INTCTRL _SFR_MEM8(0x0467) -+#define XCL_INTFLAGS _SFR_MEM8(0x0468) -+#define XCL_PLC _SFR_MEM8(0x0469) -+#define XCL_CNTL _SFR_MEM8(0x046A) -+#define XCL_CNTH _SFR_MEM8(0x046B) -+#define XCL_CMPL _SFR_MEM8(0x046C) -+#define XCL_CMPH _SFR_MEM8(0x046D) -+#define XCL_PERCAPTL _SFR_MEM8(0x046E) -+#define XCL_PERCAPTH _SFR_MEM8(0x046F) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+#define TWIC_TIMEOUT_TOS _SFR_MEM8(0x048E) -+#define TWIC_TIMEOUT_TOCONF _SFR_MEM8(0x048F) -+ -+/* PORT - I/O Ports */ -+#define PORTA_DIR _SFR_MEM8(0x0600) -+#define PORTA_DIRSET _SFR_MEM8(0x0601) -+#define PORTA_DIRCLR _SFR_MEM8(0x0602) -+#define PORTA_DIRTGL _SFR_MEM8(0x0603) -+#define PORTA_OUT _SFR_MEM8(0x0604) -+#define PORTA_OUTSET _SFR_MEM8(0x0605) -+#define PORTA_OUTCLR _SFR_MEM8(0x0606) -+#define PORTA_OUTTGL _SFR_MEM8(0x0607) -+#define PORTA_IN _SFR_MEM8(0x0608) -+#define PORTA_INTCTRL _SFR_MEM8(0x0609) -+#define PORTA_INTMASK _SFR_MEM8(0x060A) -+#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_REMAP _SFR_MEM8(0x060E) -+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INTMASK _SFR_MEM8(0x064A) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INTMASK _SFR_MEM8(0x066A) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INTMASK _SFR_MEM8(0x07EA) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC4 - 16-bit Timer/Counter 4 */ -+#define TCC4_CTRLA _SFR_MEM8(0x0800) -+#define TCC4_CTRLB _SFR_MEM8(0x0801) -+#define TCC4_CTRLC _SFR_MEM8(0x0802) -+#define TCC4_CTRLD _SFR_MEM8(0x0803) -+#define TCC4_CTRLE _SFR_MEM8(0x0804) -+#define TCC4_CTRLF _SFR_MEM8(0x0805) -+#define TCC4_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC4_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC4_CTRLGCLR _SFR_MEM8(0x0808) -+#define TCC4_CTRLGSET _SFR_MEM8(0x0809) -+#define TCC4_CTRLHCLR _SFR_MEM8(0x080A) -+#define TCC4_CTRLHSET _SFR_MEM8(0x080B) -+#define TCC4_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC4_TEMP _SFR_MEM8(0x080F) -+#define TCC4_CNT _SFR_MEM16(0x0820) -+#define TCC4_PER _SFR_MEM16(0x0826) -+#define TCC4_CCA _SFR_MEM16(0x0828) -+#define TCC4_CCB _SFR_MEM16(0x082A) -+#define TCC4_CCC _SFR_MEM16(0x082C) -+#define TCC4_CCD _SFR_MEM16(0x082E) -+#define TCC4_PERBUF _SFR_MEM16(0x0836) -+#define TCC4_CCABUF _SFR_MEM16(0x0838) -+#define TCC4_CCBBUF _SFR_MEM16(0x083A) -+#define TCC4_CCCBUF _SFR_MEM16(0x083C) -+#define TCC4_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC5 - 16-bit Timer/Counter 5 */ -+#define TCC5_CTRLA _SFR_MEM8(0x0840) -+#define TCC5_CTRLB _SFR_MEM8(0x0841) -+#define TCC5_CTRLC _SFR_MEM8(0x0842) -+#define TCC5_CTRLD _SFR_MEM8(0x0843) -+#define TCC5_CTRLE _SFR_MEM8(0x0844) -+#define TCC5_CTRLF _SFR_MEM8(0x0845) -+#define TCC5_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC5_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC5_CTRLGCLR _SFR_MEM8(0x0848) -+#define TCC5_CTRLGSET _SFR_MEM8(0x0849) -+#define TCC5_CTRLHCLR _SFR_MEM8(0x084A) -+#define TCC5_CTRLHSET _SFR_MEM8(0x084B) -+#define TCC5_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC5_TEMP _SFR_MEM8(0x084F) -+#define TCC5_CNT _SFR_MEM16(0x0860) -+#define TCC5_PER _SFR_MEM16(0x0866) -+#define TCC5_CCA _SFR_MEM16(0x0868) -+#define TCC5_CCB _SFR_MEM16(0x086A) -+#define TCC5_PERBUF _SFR_MEM16(0x0876) -+#define TCC5_CCABUF _SFR_MEM16(0x0878) -+#define TCC5_CCBBUF _SFR_MEM16(0x087A) -+ -+/* FAULT - Fault Extension */ -+#define FAULTC4_CTRLA _SFR_MEM8(0x0880) -+#define FAULTC4_CTRLB _SFR_MEM8(0x0881) -+#define FAULTC4_CTRLC _SFR_MEM8(0x0882) -+#define FAULTC4_CTRLD _SFR_MEM8(0x0883) -+#define FAULTC4_CTRLE _SFR_MEM8(0x0884) -+#define FAULTC4_STATUS _SFR_MEM8(0x0885) -+#define FAULTC4_CTRLGCLR _SFR_MEM8(0x0886) -+#define FAULTC4_CTRLGSET _SFR_MEM8(0x0887) -+ -+/* FAULT - Fault Extension */ -+#define FAULTC5_CTRLA _SFR_MEM8(0x0890) -+#define FAULTC5_CTRLB _SFR_MEM8(0x0891) -+#define FAULTC5_CTRLC _SFR_MEM8(0x0892) -+#define FAULTC5_CTRLD _SFR_MEM8(0x0893) -+#define FAULTC5_CTRLE _SFR_MEM8(0x0894) -+#define FAULTC5_STATUS _SFR_MEM8(0x0895) -+#define FAULTC5_CTRLGCLR _SFR_MEM8(0x0896) -+#define FAULTC5_CTRLGSET _SFR_MEM8(0x0897) -+ -+/* WEX - Waveform Extension */ -+#define WEXC_CTRL _SFR_MEM8(0x08A0) -+#define WEXC_DTBOTH _SFR_MEM8(0x08A1) -+#define WEXC_DTLS _SFR_MEM8(0x08A2) -+#define WEXC_DTHS _SFR_MEM8(0x08A3) -+#define WEXC_STATUSCLR _SFR_MEM8(0x08A4) -+#define WEXC_STATUSSET _SFR_MEM8(0x08A5) -+#define WEXC_SWAP _SFR_MEM8(0x08A6) -+#define WEXC_PGO _SFR_MEM8(0x08A7) -+#define WEXC_PGV _SFR_MEM8(0x08A8) -+#define WEXC_SWAPBUF _SFR_MEM8(0x08AA) -+#define WEXC_PGOBUF _SFR_MEM8(0x08AB) -+#define WEXC_PGVBUF _SFR_MEM8(0x08AC) -+#define WEXC_OUTOVDIS _SFR_MEM8(0x08AF) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x08B0) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08C0) -+#define USARTC0_STATUS _SFR_MEM8(0x08C1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08C2) -+#define USARTC0_CTRLB _SFR_MEM8(0x08C3) -+#define USARTC0_CTRLC _SFR_MEM8(0x08C4) -+#define USARTC0_CTRLD _SFR_MEM8(0x08C5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08C6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08C7) -+ -+/* SPI - Serial Peripheral Interface with Buffer Modes */ -+#define SPIC_CTRL _SFR_MEM8(0x08E0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08E1) -+#define SPIC_STATUS _SFR_MEM8(0x08E2) -+#define SPIC_DATA _SFR_MEM8(0x08E3) -+#define SPIC_CTRLB _SFR_MEM8(0x08E4) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* TC5 - 16-bit Timer/Counter 5 */ -+#define TCD5_CTRLA _SFR_MEM8(0x0940) -+#define TCD5_CTRLB _SFR_MEM8(0x0941) -+#define TCD5_CTRLC _SFR_MEM8(0x0942) -+#define TCD5_CTRLD _SFR_MEM8(0x0943) -+#define TCD5_CTRLE _SFR_MEM8(0x0944) -+#define TCD5_CTRLF _SFR_MEM8(0x0945) -+#define TCD5_INTCTRLA _SFR_MEM8(0x0946) -+#define TCD5_INTCTRLB _SFR_MEM8(0x0947) -+#define TCD5_CTRLGCLR _SFR_MEM8(0x0948) -+#define TCD5_CTRLGSET _SFR_MEM8(0x0949) -+#define TCD5_CTRLHCLR _SFR_MEM8(0x094A) -+#define TCD5_CTRLHSET _SFR_MEM8(0x094B) -+#define TCD5_INTFLAGS _SFR_MEM8(0x094C) -+#define TCD5_TEMP _SFR_MEM8(0x094F) -+#define TCD5_CNT _SFR_MEM16(0x0960) -+#define TCD5_PER _SFR_MEM16(0x0966) -+#define TCD5_CCA _SFR_MEM16(0x0968) -+#define TCD5_CCB _SFR_MEM16(0x096A) -+#define TCD5_PERBUF _SFR_MEM16(0x0976) -+#define TCD5_CCABUF _SFR_MEM16(0x0978) -+#define TCD5_CCBBUF _SFR_MEM16(0x097A) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD0_DATA _SFR_MEM8(0x09C0) -+#define USARTD0_STATUS _SFR_MEM8(0x09C1) -+#define USARTD0_CTRLA _SFR_MEM8(0x09C2) -+#define USARTD0_CTRLB _SFR_MEM8(0x09C3) -+#define USARTD0_CTRLC _SFR_MEM8(0x09C4) -+#define USARTD0_CTRLD _SFR_MEM8(0x09C5) -+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09C6) -+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09C7) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* VPORT - Virtual Ports */ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT7IF_bm 0x80 /* Interrupt Pin 7 Flag bit mask. */ -+#define VPORT_INT7IF_bp 7 /* Interrupt Pin 7 Flag bit position. */ -+ -+#define VPORT_INT6IF_bm 0x40 /* Interrupt Pin 6 Flag bit mask. */ -+#define VPORT_INT6IF_bp 6 /* Interrupt Pin 6 Flag bit position. */ -+ -+#define VPORT_INT5IF_bm 0x20 /* Interrupt Pin 5 Flag bit mask. */ -+#define VPORT_INT5IF_bp 5 /* Interrupt Pin 5 Flag bit position. */ -+ -+#define VPORT_INT4IF_bm 0x10 /* Interrupt Pin 4 Flag bit mask. */ -+#define VPORT_INT4IF_bp 4 /* Interrupt Pin 4 Flag bit position. */ -+ -+#define VPORT_INT3IF_bm 0x08 /* Interrupt Pin 3 Flag bit mask. */ -+#define VPORT_INT3IF_bp 3 /* Interrupt Pin 3 Flag bit position. */ -+ -+#define VPORT_INT2IF_bm 0x04 /* Interrupt Pin 2 Flag bit mask. */ -+#define VPORT_INT2IF_bp 2 /* Interrupt Pin 2 Flag bit position. */ -+ -+#define VPORT_INT1IF_bm 0x02 /* Interrupt Pin 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Interrupt Pin 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Interrupt Pin 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Interrupt Pin 0 Flag bit position. */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_XCL_bm 0x80 /* XMEGA Custom Logic bit mask. */ -+#define PR_XCL_bp 7 /* XMEGA Custom Logic bit position. */ -+ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+#define PR_EDMA_bm 0x01 /* Enhanced DMA-Controller bit mask. */ -+#define PR_EDMA_bp 0 /* Enhanced DMA-Controller bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -+#define PR_DAC_bp 2 /* Port A DAC bit position. */ -+ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C WEX bit mask. */ -+#define PR_HIRES_bp 2 /* Port C WEX bit position. */ -+ -+#define PR_TC5_bm 0x02 /* Port C Timer/Counter5 bit mask. */ -+#define PR_TC5_bp 1 /* Port C Timer/Counter5 bit position. */ -+ -+#define PR_TC4_bm 0x01 /* Port C Timer/Counter4 bit mask. */ -+#define PR_TC4_bp 0 /* Port C Timer/Counter4 bit position. */ -+ -+/* PR.PRPD bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC5 Predefined. */ -+/* PR_TC5 Predefined. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_RC8MLPM_bm 0x40 /* Internal 8 MHz RC Low Power Mode Enable bit mask. */ -+#define OSC_RC8MLPM_bp 6 /* Internal 8 MHz RC Low Power Mode Enable bit position. */ -+ -+#define OSC_RC8MEN_bm 0x20 /* Internal 8 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC8MEN_bp 5 /* Internal 8 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_RC8MRDY_bm 0x20 /* Internal 8 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC8MRDY_bp 5 /* Internal 8 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ -+#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -+#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -+#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ -+ -+#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ -+ -+/* OSC.RC8MCAL bit masks and bit positions */ -+#define OSC_RC8MCAL_gm 0xFF /* Calibration Bits group mask. */ -+#define OSC_RC8MCAL_gp 0 /* Calibration Bits group position. */ -+#define OSC_RC8MCAL0_bm (1<<0) /* Calibration Bits bit 0 mask. */ -+#define OSC_RC8MCAL0_bp 0 /* Calibration Bits bit 0 position. */ -+#define OSC_RC8MCAL1_bm (1<<1) /* Calibration Bits bit 1 mask. */ -+#define OSC_RC8MCAL1_bp 1 /* Calibration Bits bit 1 position. */ -+#define OSC_RC8MCAL2_bm (1<<2) /* Calibration Bits bit 2 mask. */ -+#define OSC_RC8MCAL2_bp 2 /* Calibration Bits bit 2 position. */ -+#define OSC_RC8MCAL3_bm (1<<3) /* Calibration Bits bit 3 mask. */ -+#define OSC_RC8MCAL3_bp 3 /* Calibration Bits bit 3 position. */ -+#define OSC_RC8MCAL4_bm (1<<4) /* Calibration Bits bit 4 mask. */ -+#define OSC_RC8MCAL4_bp 4 /* Calibration Bits bit 4 position. */ -+#define OSC_RC8MCAL5_bm (1<<5) /* Calibration Bits bit 5 mask. */ -+#define OSC_RC8MCAL5_bp 5 /* Calibration Bits bit 5 position. */ -+#define OSC_RC8MCAL6_bm (1<<6) /* Calibration Bits bit 6 mask. */ -+#define OSC_RC8MCAL6_bp 6 /* Calibration Bits bit 6 position. */ -+#define OSC_RC8MCAL7_bm (1<<7) /* Calibration Bits bit 7 mask. */ -+#define OSC_RC8MCAL7_bp 7 /* Calibration Bits bit 7 position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.ANAINIT bit masks and bit positions */ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -+#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ -+ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.WEXLOCK bit masks and bit positions */ -+#define MCU_WEXCLOCK_bm 0x01 /* WeX on T/C C4 Lock bit mask. */ -+#define MCU_WEXCLOCK_bp 0 /* WeX on T/C C4 Lock bit position. */ -+ -+/* MCU.FAULTLOCK bit masks and bit positions */ -+#define MCU_FAULTC5LOCK_bm 0x02 /* Fault on T/C C5 Lock bit mask. */ -+#define MCU_FAULTC5LOCK_bp 1 /* Fault on T/C C5 Lock bit position. */ -+ -+#define MCU_FAULTC4LOCK_bm 0x01 /* Fault on T/C C4 Lock bit mask. */ -+#define MCU_FAULTC4LOCK_bp 0 /* Fault on T/C C4 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* PORTCFG - Port Configuration */ -+/* PORTCFG.CLKOUT bit masks and bit positions */ -+#define PORTCFG_CLKEVPIN_bm 0x80 /* Clock and Event Output Pin Select bit mask. */ -+#define PORTCFG_CLKEVPIN_bp 7 /* Clock and Event Output Pin Select bit position. */ -+ -+#define PORTCFG_RTCOUT_gm 0x60 /* RTC Clock Output Enable group mask. */ -+#define PORTCFG_RTCOUT_gp 5 /* RTC Clock Output Enable group position. */ -+#define PORTCFG_RTCOUT0_bm (1<<5) /* RTC Clock Output Enable bit 0 mask. */ -+#define PORTCFG_RTCOUT0_bp 5 /* RTC Clock Output Enable bit 0 position. */ -+#define PORTCFG_RTCOUT1_bm (1<<6) /* RTC Clock Output Enable bit 1 mask. */ -+#define PORTCFG_RTCOUT1_bp 6 /* RTC Clock Output Enable bit 1 position. */ -+ -+#define PORTCFG_CLKOUTSEL_gm 0x0C /* Clock Output Select group mask. */ -+#define PORTCFG_CLKOUTSEL_gp 2 /* Clock Output Select group position. */ -+#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Clock Output Select bit 0 mask. */ -+#define PORTCFG_CLKOUTSEL0_bp 2 /* Clock Output Select bit 0 position. */ -+#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Clock Output Select bit 1 mask. */ -+#define PORTCFG_CLKOUTSEL1_bp 3 /* Clock Output Select bit 1 position. */ -+ -+#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ -+ -+/* PORTCFG.ACEVOUT bit masks and bit positions */ -+#define PORTCFG_ACOUT_gm 0xC0 /* Analog Comparator Output Port group mask. */ -+#define PORTCFG_ACOUT_gp 6 /* Analog Comparator Output Port group position. */ -+#define PORTCFG_ACOUT0_bm (1<<6) /* Analog Comparator Output Port bit 0 mask. */ -+#define PORTCFG_ACOUT0_bp 6 /* Analog Comparator Output Port bit 0 position. */ -+#define PORTCFG_ACOUT1_bm (1<<7) /* Analog Comparator Output Port bit 1 mask. */ -+#define PORTCFG_ACOUT1_bp 7 /* Analog Comparator Output Port bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Channel Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Channel Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Channel Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Channel Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Channel Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Channel Output Port bit 1 position. */ -+ -+#define PORTCFG_EVASYEN_bm 0x08 /* Asynchronous Event Enabled bit mask. */ -+#define PORTCFG_EVASYEN_bp 3 /* Asynchronous Event Enabled bit position. */ -+ -+#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Channel Output Selection group mask. */ -+#define PORTCFG_EVOUTSEL_gp 0 /* Event Channel Output Selection group position. */ -+#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Channel Output Selection bit 0 mask. */ -+#define PORTCFG_EVOUTSEL0_bp 0 /* Event Channel Output Selection bit 0 position. */ -+#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Channel Output Selection bit 1 mask. */ -+#define PORTCFG_EVOUTSEL1_bp 1 /* Event Channel Output Selection bit 1 position. */ -+#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Channel Output Selection bit 2 mask. */ -+#define PORTCFG_EVOUTSEL2_bp 2 /* Event Channel Output Selection bit 2 position. */ -+ -+/* PORTCFG.SRLCTRL bit masks and bit positions */ -+#define PORTCFG_SRLENRA_bm 0x01 /* Slew Rate Limit Enable on PORTA bit mask. */ -+#define PORTCFG_SRLENRA_bp 0 /* Slew Rate Limit Enable on PORTA bit position. */ -+ -+#define PORTCFG_SRLENRC_bm 0x04 /* Slew Rate Limit Enable on PORTC bit mask. */ -+#define PORTCFG_SRLENRC_bp 2 /* Slew Rate Limit Enable on PORTC bit position. */ -+ -+#define PORTCFG_SRLENRD_bm 0x08 /* Slew Rate Limit Enable on PORTD bit mask. */ -+#define PORTCFG_SRLENRD_bp 3 /* Slew Rate Limit Enable on PORTD bit position. */ -+ -+#define PORTCFG_SRLENRR_bm 0x80 /* Slew Rate Limit Enable on PORTR bit mask. */ -+#define PORTCFG_SRLENRR_bp 7 /* Slew Rate Limit Enable on PORTR bit position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* EDMA - Enhanced DMA Controller */ -+/* EDMA.CTRL bit masks and bit positions */ -+#define EDMA_ENABLE_bm 0x80 /* Enable bit mask. */ -+#define EDMA_ENABLE_bp 7 /* Enable bit position. */ -+ -+#define EDMA_RESET_bm 0x40 /* Software Reset bit mask. */ -+#define EDMA_RESET_bp 6 /* Software Reset bit position. */ -+ -+#define EDMA_CHMODE_gm 0x30 /* Channel Mode group mask. */ -+#define EDMA_CHMODE_gp 4 /* Channel Mode group position. */ -+#define EDMA_CHMODE0_bm (1<<4) /* Channel Mode bit 0 mask. */ -+#define EDMA_CHMODE0_bp 4 /* Channel Mode bit 0 position. */ -+#define EDMA_CHMODE1_bm (1<<5) /* Channel Mode bit 1 mask. */ -+#define EDMA_CHMODE1_bp 5 /* Channel Mode bit 1 position. */ -+ -+#define EDMA_DBUFMODE_gm 0x0C /* Double Buffer Mode group mask. */ -+#define EDMA_DBUFMODE_gp 2 /* Double Buffer Mode group position. */ -+#define EDMA_DBUFMODE0_bm (1<<2) /* Double Buffer Mode bit 0 mask. */ -+#define EDMA_DBUFMODE0_bp 2 /* Double Buffer Mode bit 0 position. */ -+#define EDMA_DBUFMODE1_bm (1<<3) /* Double Buffer Mode bit 1 mask. */ -+#define EDMA_DBUFMODE1_bp 3 /* Double Buffer Mode bit 1 position. */ -+ -+#define EDMA_PRIMODE_gm 0x03 /* Priority Mode group mask. */ -+#define EDMA_PRIMODE_gp 0 /* Priority Mode group position. */ -+#define EDMA_PRIMODE0_bm (1<<0) /* Priority Mode bit 0 mask. */ -+#define EDMA_PRIMODE0_bp 0 /* Priority Mode bit 0 position. */ -+#define EDMA_PRIMODE1_bm (1<<1) /* Priority Mode bit 1 mask. */ -+#define EDMA_PRIMODE1_bp 1 /* Priority Mode bit 1 position. */ -+ -+/* EDMA.INTFLAGS bit masks and bit positions */ -+#define EDMA_CH3ERRIF_bm 0x80 /* Channel 3 Transaction Error Interrupt Flag bit mask. */ -+#define EDMA_CH3ERRIF_bp 7 /* Channel 3 Transaction Error Interrupt Flag bit position. */ -+ -+#define EDMA_CH2ERRIF_bm 0x40 /* Channel 2 Transaction Error Interrupt Flag bit mask. */ -+#define EDMA_CH2ERRIF_bp 6 /* Channel 2 Transaction Error Interrupt Flag bit position. */ -+ -+#define EDMA_CH1ERRIF_bm 0x20 /* Channel 1 Transaction Error Interrupt Flag bit mask. */ -+#define EDMA_CH1ERRIF_bp 5 /* Channel 1 Transaction Error Interrupt Flag bit position. */ -+ -+#define EDMA_CH0ERRIF_bm 0x10 /* Channel 0 Transaction Error Interrupt Flag bit mask. */ -+#define EDMA_CH0ERRIF_bp 4 /* Channel 0 Transaction Error Interrupt Flag bit position. */ -+ -+#define EDMA_CH3TRNFIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -+#define EDMA_CH3TRNFIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ -+ -+#define EDMA_CH2TRNFIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -+#define EDMA_CH2TRNFIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ -+ -+#define EDMA_CH1TRNFIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -+#define EDMA_CH1TRNFIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ -+ -+#define EDMA_CH0TRNFIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -+#define EDMA_CH0TRNFIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ -+ -+/* EDMA.STATUS bit masks and bit positions */ -+#define EDMA_CH3BUSY_bm 0x80 /* Channel 3 Busy Flag bit mask. */ -+#define EDMA_CH3BUSY_bp 7 /* Channel 3 Busy Flag bit position. */ -+ -+#define EDMA_CH2BUSY_bm 0x40 /* Channel 2 Busy Flag bit mask. */ -+#define EDMA_CH2BUSY_bp 6 /* Channel 2 Busy Flag bit position. */ -+ -+#define EDMA_CH1BUSY_bm 0x20 /* Channel 1 Busy Flag bit mask. */ -+#define EDMA_CH1BUSY_bp 5 /* Channel 1 Busy Flag bit position. */ -+ -+#define EDMA_CH0BUSY_bm 0x10 /* Channel 0 Busy Flag bit mask. */ -+#define EDMA_CH0BUSY_bp 4 /* Channel 0 Busy Flag bit position. */ -+ -+#define EDMA_CH3PEND_bm 0x08 /* Channel 3 Pending Flag bit mask. */ -+#define EDMA_CH3PEND_bp 3 /* Channel 3 Pending Flag bit position. */ -+ -+#define EDMA_CH2PEND_bm 0x04 /* Channel 2 Pending Flag bit mask. */ -+#define EDMA_CH2PEND_bp 2 /* Channel 2 Pending Flag bit position. */ -+ -+#define EDMA_CH1PEND_bm 0x02 /* Channel 1 Pending Flag bit mask. */ -+#define EDMA_CH1PEND_bp 1 /* Channel 1 Pending Flag bit position. */ -+ -+#define EDMA_CH0PEND_bm 0x01 /* Channel 0 Pending Flag bit mask. */ -+#define EDMA_CH0PEND_bp 0 /* Channel 0 Pending Flag bit position. */ -+ -+/* EDMA_CH.CTRLA bit masks and bit positions */ -+#define EDMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -+#define EDMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ -+ -+#define EDMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -+#define EDMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ -+ -+#define EDMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -+#define EDMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ -+ -+#define EDMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -+#define EDMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ -+ -+#define EDMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -+#define EDMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ -+ -+#define EDMA_CH_BURSTLEN_bm 0x01 /* Channel 2-bytes Burst Length bit mask. */ -+#define EDMA_CH_BURSTLEN_bp 0 /* Channel 2-bytes Burst Length bit position. */ -+ -+/* EDMA_CH.CTRLB bit masks and bit positions */ -+#define EDMA_CH_CHBUSY_bm 0x80 /* Channel Block Transfer Busy bit mask. */ -+#define EDMA_CH_CHBUSY_bp 7 /* Channel Block Transfer Busy bit position. */ -+ -+#define EDMA_CH_CHPEND_bm 0x40 /* Channel Block Transfer Pending bit mask. */ -+#define EDMA_CH_CHPEND_bp 6 /* Channel Block Transfer Pending bit position. */ -+ -+#define EDMA_CH_ERRIF_bm 0x20 /* Channel Transaction Error Interrupt Flag bit mask. */ -+#define EDMA_CH_ERRIF_bp 5 /* Channel Transaction Error Interrupt Flag bit position. */ -+ -+#define EDMA_CH_TRNIF_bm 0x10 /* Channel Transaction Complete Interrup Flag bit mask. */ -+#define EDMA_CH_TRNIF_bp 4 /* Channel Transaction Complete Interrup Flag bit position. */ -+ -+#define EDMA_CH_ERRINTLVL_gm 0x0C /* Channel Transaction Error Interrupt Level group mask. */ -+#define EDMA_CH_ERRINTLVL_gp 2 /* Channel Transaction Error Interrupt Level group position. */ -+#define EDMA_CH_ERRINTLVL0_bm (1<<2) /* Channel Transaction Error Interrupt Level bit 0 mask. */ -+#define EDMA_CH_ERRINTLVL0_bp 2 /* Channel Transaction Error Interrupt Level bit 0 position. */ -+#define EDMA_CH_ERRINTLVL1_bm (1<<3) /* Channel Transaction Error Interrupt Level bit 1 mask. */ -+#define EDMA_CH_ERRINTLVL1_bp 3 /* Channel Transaction Error Interrupt Level bit 1 position. */ -+ -+#define EDMA_CH_TRNINTLVL_gm 0x03 /* Channel Transaction Complete Interrupt Level group mask. */ -+#define EDMA_CH_TRNINTLVL_gp 0 /* Channel Transaction Complete Interrupt Level group position. */ -+#define EDMA_CH_TRNINTLVL0_bm (1<<0) /* Channel Transaction Complete Interrupt Level bit 0 mask. */ -+#define EDMA_CH_TRNINTLVL0_bp 0 /* Channel Transaction Complete Interrupt Level bit 0 position. */ -+#define EDMA_CH_TRNINTLVL1_bm (1<<1) /* Channel Transaction Complete Interrupt Level bit 1 mask. */ -+#define EDMA_CH_TRNINTLVL1_bp 1 /* Channel Transaction Complete Interrupt Level bit 1 position. */ -+ -+/* EDMA_CH.ADDRCTRL bit masks and bit positions */ -+#define EDMA_CH_RELOAD_gm 0x30 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group mask. */ -+#define EDMA_CH_RELOAD_gp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group position. */ -+#define EDMA_CH_RELOAD0_bm (1<<4) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 mask. */ -+#define EDMA_CH_RELOAD0_bp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 position. */ -+#define EDMA_CH_RELOAD1_bm (1<<5) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 mask. */ -+#define EDMA_CH_RELOAD1_bp 5 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 position. */ -+ -+#define EDMA_CH_DIR_gm 0x07 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group mask. */ -+#define EDMA_CH_DIR_gp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group position. */ -+#define EDMA_CH_DIR0_bm (1<<0) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 mask. */ -+#define EDMA_CH_DIR0_bp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 position. */ -+#define EDMA_CH_DIR1_bm (1<<1) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 mask. */ -+#define EDMA_CH_DIR1_bp 1 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 position. */ -+#define EDMA_CH_DIR2_bm (1<<2) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 mask. */ -+#define EDMA_CH_DIR2_bp 2 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 position. */ -+ -+/* EDMA_CH.DESTADDRCTRL bit masks and bit positions */ -+#define EDMA_CH_DESTRELOAD_gm 0x30 /* Destination Address Reload for Standard Channels Only. group mask. */ -+#define EDMA_CH_DESTRELOAD_gp 4 /* Destination Address Reload for Standard Channels Only. group position. */ -+#define EDMA_CH_DESTRELOAD0_bm (1<<4) /* Destination Address Reload for Standard Channels Only. bit 0 mask. */ -+#define EDMA_CH_DESTRELOAD0_bp 4 /* Destination Address Reload for Standard Channels Only. bit 0 position. */ -+#define EDMA_CH_DESTRELOAD1_bm (1<<5) /* Destination Address Reload for Standard Channels Only. bit 1 mask. */ -+#define EDMA_CH_DESTRELOAD1_bp 5 /* Destination Address Reload for Standard Channels Only. bit 1 position. */ -+ -+#define EDMA_CH_DESTDIR_gm 0x07 /* Destination Address Mode for Standard Channels Only. group mask. */ -+#define EDMA_CH_DESTDIR_gp 0 /* Destination Address Mode for Standard Channels Only. group position. */ -+#define EDMA_CH_DESTDIR0_bm (1<<0) /* Destination Address Mode for Standard Channels Only. bit 0 mask. */ -+#define EDMA_CH_DESTDIR0_bp 0 /* Destination Address Mode for Standard Channels Only. bit 0 position. */ -+#define EDMA_CH_DESTDIR1_bm (1<<1) /* Destination Address Mode for Standard Channels Only. bit 1 mask. */ -+#define EDMA_CH_DESTDIR1_bp 1 /* Destination Address Mode for Standard Channels Only. bit 1 position. */ -+#define EDMA_CH_DESTDIR2_bm (1<<2) /* Destination Address Mode for Standard Channels Only. bit 2 mask. */ -+#define EDMA_CH_DESTDIR2_bp 2 /* Destination Address Mode for Standard Channels Only. bit 2 position. */ -+ -+/* EDMA_CH.TRIGSRC bit masks and bit positions */ -+#define EDMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -+#define EDMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -+#define EDMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -+#define EDMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -+#define EDMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -+#define EDMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -+#define EDMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -+#define EDMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -+#define EDMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -+#define EDMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -+#define EDMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -+#define EDMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -+#define EDMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -+#define EDMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -+#define EDMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -+#define EDMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -+#define EDMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -+#define EDMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH4MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH5MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH6MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH7MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_ROTARY_bm 0x80 /* Rotary Decoder Enable bit mask. */ -+#define EVSYS_ROTARY_bp 7 /* Rotary Decoder Enable bit position. */ -+ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH4CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH5CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH6CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH7CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.DFCTRL bit masks and bit positions */ -+#define EVSYS_PRESCFILT_gm 0xF0 /* Prescaler Filter group mask. */ -+#define EVSYS_PRESCFILT_gp 4 /* Prescaler Filter group position. */ -+#define EVSYS_PRESCFILT0_bm (1<<4) /* Prescaler Filter bit 0 mask. */ -+#define EVSYS_PRESCFILT0_bp 4 /* Prescaler Filter bit 0 position. */ -+#define EVSYS_PRESCFILT1_bm (1<<5) /* Prescaler Filter bit 1 mask. */ -+#define EVSYS_PRESCFILT1_bp 5 /* Prescaler Filter bit 1 position. */ -+#define EVSYS_PRESCFILT2_bm (1<<6) /* Prescaler Filter bit 2 mask. */ -+#define EVSYS_PRESCFILT2_bp 6 /* Prescaler Filter bit 2 position. */ -+#define EVSYS_PRESCFILT3_bm (1<<7) /* Prescaler Filter bit 3 mask. */ -+#define EVSYS_PRESCFILT3_bp 7 /* Prescaler Filter bit 3 position. */ -+ -+#define EVSYS_FILTSEL_bm 0x08 /* Prescaler Filter Select bit mask. */ -+#define EVSYS_FILTSEL_bp 3 /* Prescaler Filter Select bit position. */ -+ -+#define EVSYS_PRESC_gm 0x07 /* Prescaler group mask. */ -+#define EVSYS_PRESC_gp 0 /* Prescaler group position. */ -+#define EVSYS_PRESC0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define EVSYS_PRESC0_bp 0 /* Prescaler bit 0 position. */ -+#define EVSYS_PRESC1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define EVSYS_PRESC1_bp 1 /* Prescaler bit 1 position. */ -+#define EVSYS_PRESC2_bm (1<<2) /* Prescaler bit 2 mask. */ -+#define EVSYS_PRESC2_bp 2 /* Prescaler bit 2 position. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0x7F /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC Input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC Input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC Input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC Input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC Input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC Input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC Input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC Input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC Input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC Input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC Input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC Input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC Input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC Input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC Input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC Input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC Input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC Input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC Input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC Input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC Input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC Input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC Input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC Input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC Input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC Input bit 1 position. */ -+ -+#define ADC_CH_MUXNEGL_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group mask. */ -+#define ADC_CH_MUXNEGL_gp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group position. */ -+#define ADC_CH_MUXNEGL0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 mask. */ -+#define ADC_CH_MUXNEGL0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 position. */ -+#define ADC_CH_MUXNEGL1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 mask. */ -+#define ADC_CH_MUXNEGL1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 position. */ -+ -+#define ADC_CH_MUXNEGH_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group mask. */ -+#define ADC_CH_MUXNEGH_gp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group position. */ -+#define ADC_CH_MUXNEGH0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 mask. */ -+#define ADC_CH_MUXNEGH0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 position. */ -+#define ADC_CH_MUXNEGH1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 mask. */ -+#define ADC_CH_MUXNEGH1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_IF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_IF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_INPUTOFFSET_gm 0xF0 /* Positive MUX Setting Offset group mask. */ -+#define ADC_CH_INPUTOFFSET_gp 4 /* Positive MUX Setting Offset group position. */ -+#define ADC_CH_INPUTOFFSET0_bm (1<<4) /* Positive MUX Setting Offset bit 0 mask. */ -+#define ADC_CH_INPUTOFFSET0_bp 4 /* Positive MUX Setting Offset bit 0 position. */ -+#define ADC_CH_INPUTOFFSET1_bm (1<<5) /* Positive MUX Setting Offset bit 1 mask. */ -+#define ADC_CH_INPUTOFFSET1_bp 5 /* Positive MUX Setting Offset bit 1 position. */ -+#define ADC_CH_INPUTOFFSET2_bm (1<<6) /* Positive MUX Setting Offset bit 2 mask. */ -+#define ADC_CH_INPUTOFFSET2_bp 6 /* Positive MUX Setting Offset bit 2 position. */ -+#define ADC_CH_INPUTOFFSET3_bm (1<<7) /* Positive MUX Setting Offset bit 3 mask. */ -+#define ADC_CH_INPUTOFFSET3_bp 7 /* Positive MUX Setting Offset bit 3 position. */ -+ -+#define ADC_CH_INPUTSCAN_gm 0x0F /* Number of Channels Included in Scan group mask. */ -+#define ADC_CH_INPUTSCAN_gp 0 /* Number of Channels Included in Scan group position. */ -+#define ADC_CH_INPUTSCAN0_bm (1<<0) /* Number of Channels Included in Scan bit 0 mask. */ -+#define ADC_CH_INPUTSCAN0_bp 0 /* Number of Channels Included in Scan bit 0 position. */ -+#define ADC_CH_INPUTSCAN1_bm (1<<1) /* Number of Channels Included in Scan bit 1 mask. */ -+#define ADC_CH_INPUTSCAN1_bp 1 /* Number of Channels Included in Scan bit 1 position. */ -+#define ADC_CH_INPUTSCAN2_bm (1<<2) /* Number of Channels Included in Scan bit 2 mask. */ -+#define ADC_CH_INPUTSCAN2_bp 2 /* Number of Channels Included in Scan bit 2 position. */ -+#define ADC_CH_INPUTSCAN3_bm (1<<3) /* Number of Channels Included in Scan bit 3 mask. */ -+#define ADC_CH_INPUTSCAN3_bp 3 /* Number of Channels Included in Scan bit 3 position. */ -+ -+/* ADC_CH.CORRCTRL bit masks and bit positions */ -+#define ADC_CH_CORREN_bm 0x01 /* Correction Enable bit mask. */ -+#define ADC_CH_CORREN_bp 0 /* Correction Enable bit position. */ -+ -+/* ADC_CH.OFFSETCORR1 bit masks and bit positions */ -+#define ADC_CH_OFFSETCORR_gm 0x0F /* Offset Correction Byte 1 group mask. */ -+#define ADC_CH_OFFSETCORR_gp 0 /* Offset Correction Byte 1 group position. */ -+#define ADC_CH_OFFSETCORR0_bm (1<<0) /* Offset Correction Byte 1 bit 0 mask. */ -+#define ADC_CH_OFFSETCORR0_bp 0 /* Offset Correction Byte 1 bit 0 position. */ -+#define ADC_CH_OFFSETCORR1_bm (1<<1) /* Offset Correction Byte 1 bit 1 mask. */ -+#define ADC_CH_OFFSETCORR1_bp 1 /* Offset Correction Byte 1 bit 1 position. */ -+#define ADC_CH_OFFSETCORR2_bm (1<<2) /* Offset Correction Byte 1 bit 2 mask. */ -+#define ADC_CH_OFFSETCORR2_bp 2 /* Offset Correction Byte 1 bit 2 position. */ -+#define ADC_CH_OFFSETCORR3_bm (1<<3) /* Offset Correction Byte 1 bit 3 mask. */ -+#define ADC_CH_OFFSETCORR3_bp 3 /* Offset Correction Byte 1 bit 3 position. */ -+ -+/* ADC_CH.GAINCORR1 bit masks and bit positions */ -+#define ADC_CH_GAINCORR_gm 0x0F /* Gain Correction Byte 1 group mask. */ -+#define ADC_CH_GAINCORR_gp 0 /* Gain Correction Byte 1 group position. */ -+#define ADC_CH_GAINCORR0_bm (1<<0) /* Gain Correction Byte 1 bit 0 mask. */ -+#define ADC_CH_GAINCORR0_bp 0 /* Gain Correction Byte 1 bit 0 position. */ -+#define ADC_CH_GAINCORR1_bm (1<<1) /* Gain Correction Byte 1 bit 1 mask. */ -+#define ADC_CH_GAINCORR1_bp 1 /* Gain Correction Byte 1 bit 1 position. */ -+#define ADC_CH_GAINCORR2_bm (1<<2) /* Gain Correction Byte 1 bit 2 mask. */ -+#define ADC_CH_GAINCORR2_bp 2 /* Gain Correction Byte 1 bit 2 position. */ -+#define ADC_CH_GAINCORR3_bm (1<<3) /* Gain Correction Byte 1 bit 3 mask. */ -+#define ADC_CH_GAINCORR3_bp 3 /* Gain Correction Byte 1 bit 3 position. */ -+ -+/* ADC_CH.AVGCTRL bit masks and bit positions */ -+#define ADC_CH_RIGHTSHIFT_gm 0x70 /* Right Shift group mask. */ -+#define ADC_CH_RIGHTSHIFT_gp 4 /* Right Shift group position. */ -+#define ADC_CH_RIGHTSHIFT0_bm (1<<4) /* Right Shift bit 0 mask. */ -+#define ADC_CH_RIGHTSHIFT0_bp 4 /* Right Shift bit 0 position. */ -+#define ADC_CH_RIGHTSHIFT1_bm (1<<5) /* Right Shift bit 1 mask. */ -+#define ADC_CH_RIGHTSHIFT1_bp 5 /* Right Shift bit 1 position. */ -+#define ADC_CH_RIGHTSHIFT2_bm (1<<6) /* Right Shift bit 2 mask. */ -+#define ADC_CH_RIGHTSHIFT2_bp 6 /* Right Shift bit 2 position. */ -+ -+#define ADC_CH_SAMPNUM_gm 0x0F /* Averaged Number of Samples group mask. */ -+#define ADC_CH_SAMPNUM_gp 0 /* Averaged Number of Samples group position. */ -+#define ADC_CH_SAMPNUM0_bm (1<<0) /* Averaged Number of Samples bit 0 mask. */ -+#define ADC_CH_SAMPNUM0_bp 0 /* Averaged Number of Samples bit 0 position. */ -+#define ADC_CH_SAMPNUM1_bm (1<<1) /* Averaged Number of Samples bit 1 mask. */ -+#define ADC_CH_SAMPNUM1_bp 1 /* Averaged Number of Samples bit 1 position. */ -+#define ADC_CH_SAMPNUM2_bm (1<<2) /* Averaged Number of Samples bit 2 mask. */ -+#define ADC_CH_SAMPNUM2_bp 2 /* Averaged Number of Samples bit 2 position. */ -+#define ADC_CH_SAMPNUM3_bm (1<<3) /* Averaged Number of Samples bit 3 mask. */ -+#define ADC_CH_SAMPNUM3_bp 3 /* Averaged Number of Samples bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_START_bm 0x04 /* Start Conversion bit mask. */ -+#define ADC_START_bp 2 /* Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -+#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -+#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* ADC.SAMPCTRL bit masks and bit positions */ -+#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ -+#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ -+#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ -+#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ -+#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ -+#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ -+#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ -+#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ -+#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ -+#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ -+#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ -+#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ -+#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ -+#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ -+ -+/* DAC - Digital/Analog Converter */ -+/* DAC.CTRLA bit masks and bit positions */ -+#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -+#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ -+ -+#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -+#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ -+ -+#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -+#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ -+ -+#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -+#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ -+ -+#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define DAC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* DAC.CTRLB bit masks and bit positions */ -+#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -+#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -+#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -+#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -+#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -+#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ -+ -+#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -+#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ -+ -+#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -+#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ -+ -+/* DAC.CTRLC bit masks and bit positions */ -+#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -+#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -+#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -+#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -+#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -+#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ -+ -+#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -+#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ -+ -+/* DAC.EVCTRL bit masks and bit positions */ -+#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -+#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ -+ -+#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -+#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -+#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -+#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -+#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -+#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -+#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -+#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ -+ -+/* DAC.STATUS bit masks and bit positions */ -+#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -+#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ -+ -+#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -+#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ -+ -+/* DAC.CH0GAINCAL bit masks and bit positions */ -+#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -+#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -+#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -+#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -+#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -+#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -+#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -+#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -+#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -+#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -+#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -+#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -+#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -+#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -+#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -+#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ -+ -+/* DAC.CH0OFFSETCAL bit masks and bit positions */ -+#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -+#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -+#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -+#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -+#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -+#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -+#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -+#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -+#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -+#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -+#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -+#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -+#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -+#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -+#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -+#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ -+ -+/* DAC.CH1GAINCAL bit masks and bit positions */ -+#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -+#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -+#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -+#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -+#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -+#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -+#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -+#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -+#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -+#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -+#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -+#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -+#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -+#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -+#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -+#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ -+ -+/* DAC.CH1OFFSETCAL bit masks and bit positions */ -+#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -+#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -+#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -+#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -+#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -+#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -+#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -+#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -+#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -+#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -+#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -+#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -+#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -+#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -+#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -+#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1INVEN_bm 0x08 /* Analog Comparator 1 Output Invert Enable bit mask. */ -+#define AC_AC1INVEN_bp 3 /* Analog Comparator 1 Output Invert Enable bit position. */ -+ -+#define AC_AC0INVEN_bm 0x04 /* Analog Comparator 0 Output Invert Enable bit mask. */ -+#define AC_AC0INVEN_bp 2 /* Analog Comparator 0 Output Invert Enable bit position. */ -+ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* AC.CURRCTRL bit masks and bit positions */ -+#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ -+#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ -+ -+#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ -+#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ -+ -+#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ -+#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ -+ -+#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ -+#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ -+ -+/* AC.CURRCALIB bit masks and bit positions */ -+#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ -+#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ -+#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ -+#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ -+#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ -+#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ -+#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ -+#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ -+#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ -+#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ -+ -+/* RTC - Real-Time Clounter */ -+/* RTC.CTRL bit masks and bit positions */ -+#define RTC_CORREN_bm 0x08 /* Correction Enable bit mask. */ -+#define RTC_CORREN_bp 3 /* Correction Enable bit position. */ -+ -+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ -+ -+/* RTC.STATUS bit masks and bit positions */ -+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC.INTCTRL bit masks and bit positions */ -+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC.INTFLAGS bit masks and bit positions */ -+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* RTC.CALIB bit masks and bit positions */ -+#define RTC_SIGN_bm 0x80 /* Correction Sign bit mask. */ -+#define RTC_SIGN_bp 7 /* Correction Sign bit position. */ -+ -+#define RTC_ERROR_gm 0x7F /* Error Value group mask. */ -+#define RTC_ERROR_gp 0 /* Error Value group position. */ -+#define RTC_ERROR0_bm (1<<0) /* Error Value bit 0 mask. */ -+#define RTC_ERROR0_bp 0 /* Error Value bit 0 position. */ -+#define RTC_ERROR1_bm (1<<1) /* Error Value bit 1 mask. */ -+#define RTC_ERROR1_bp 1 /* Error Value bit 1 position. */ -+#define RTC_ERROR2_bm (1<<2) /* Error Value bit 2 mask. */ -+#define RTC_ERROR2_bp 2 /* Error Value bit 2 position. */ -+#define RTC_ERROR3_bm (1<<3) /* Error Value bit 3 mask. */ -+#define RTC_ERROR3_bp 3 /* Error Value bit 3 position. */ -+#define RTC_ERROR4_bm (1<<4) /* Error Value bit 4 mask. */ -+#define RTC_ERROR4_bp 4 /* Error Value bit 4 position. */ -+#define RTC_ERROR5_bm (1<<5) /* Error Value bit 5 mask. */ -+#define RTC_ERROR5_bp 5 /* Error Value bit 5 position. */ -+#define RTC_ERROR6_bm (1<<6) /* Error Value bit 6 mask. */ -+#define RTC_ERROR6_bp 6 /* Error Value bit 6 position. */ -+ -+/* XCL - XMEGA Custom Logic */ -+/* XCL.CTRLA bit masks and bit positions */ -+#define XCL_LUT0OUTEN_gm 0xC0 /* LUT0 Output Enable group mask. */ -+#define XCL_LUT0OUTEN_gp 6 /* LUT0 Output Enable group position. */ -+#define XCL_LUT0OUTEN0_bm (1<<6) /* LUT0 Output Enable bit 0 mask. */ -+#define XCL_LUT0OUTEN0_bp 6 /* LUT0 Output Enable bit 0 position. */ -+#define XCL_LUT0OUTEN1_bm (1<<7) /* LUT0 Output Enable bit 1 mask. */ -+#define XCL_LUT0OUTEN1_bp 7 /* LUT0 Output Enable bit 1 position. */ -+ -+#define XCL_PORTSEL_gm 0x30 /* Port Selection group mask. */ -+#define XCL_PORTSEL_gp 4 /* Port Selection group position. */ -+#define XCL_PORTSEL0_bm (1<<4) /* Port Selection bit 0 mask. */ -+#define XCL_PORTSEL0_bp 4 /* Port Selection bit 0 position. */ -+#define XCL_PORTSEL1_bm (1<<5) /* Port Selection bit 1 mask. */ -+#define XCL_PORTSEL1_bp 5 /* Port Selection bit 1 position. */ -+ -+#define XCL_LUTCONF_gm 0x07 /* LUT Configuration group mask. */ -+#define XCL_LUTCONF_gp 0 /* LUT Configuration group position. */ -+#define XCL_LUTCONF0_bm (1<<0) /* LUT Configuration bit 0 mask. */ -+#define XCL_LUTCONF0_bp 0 /* LUT Configuration bit 0 position. */ -+#define XCL_LUTCONF1_bm (1<<1) /* LUT Configuration bit 1 mask. */ -+#define XCL_LUTCONF1_bp 1 /* LUT Configuration bit 1 position. */ -+#define XCL_LUTCONF2_bm (1<<2) /* LUT Configuration bit 2 mask. */ -+#define XCL_LUTCONF2_bp 2 /* LUT Configuration bit 2 position. */ -+ -+/* XCL.CTRLB bit masks and bit positions */ -+#define XCL_IN3SEL_gm 0xC0 /* Input Selection 3 group mask. */ -+#define XCL_IN3SEL_gp 6 /* Input Selection 3 group position. */ -+#define XCL_IN3SEL0_bm (1<<6) /* Input Selection 3 bit 0 mask. */ -+#define XCL_IN3SEL0_bp 6 /* Input Selection 3 bit 0 position. */ -+#define XCL_IN3SEL1_bm (1<<7) /* Input Selection 3 bit 1 mask. */ -+#define XCL_IN3SEL1_bp 7 /* Input Selection 3 bit 1 position. */ -+ -+#define XCL_IN2SEL_gm 0x30 /* Input Selection 2 group mask. */ -+#define XCL_IN2SEL_gp 4 /* Input Selection 2 group position. */ -+#define XCL_IN2SEL0_bm (1<<4) /* Input Selection 2 bit 0 mask. */ -+#define XCL_IN2SEL0_bp 4 /* Input Selection 2 bit 0 position. */ -+#define XCL_IN2SEL1_bm (1<<5) /* Input Selection 2 bit 1 mask. */ -+#define XCL_IN2SEL1_bp 5 /* Input Selection 2 bit 1 position. */ -+ -+#define XCL_IN1SEL_gm 0x0C /* Input Selection 1 group mask. */ -+#define XCL_IN1SEL_gp 2 /* Input Selection 1 group position. */ -+#define XCL_IN1SEL0_bm (1<<2) /* Input Selection 1 bit 0 mask. */ -+#define XCL_IN1SEL0_bp 2 /* Input Selection 1 bit 0 position. */ -+#define XCL_IN1SEL1_bm (1<<3) /* Input Selection 1 bit 1 mask. */ -+#define XCL_IN1SEL1_bp 3 /* Input Selection 1 bit 1 position. */ -+ -+#define XCL_IN0SEL_gm 0x03 /* Input Selection 0 group mask. */ -+#define XCL_IN0SEL_gp 0 /* Input Selection 0 group position. */ -+#define XCL_IN0SEL0_bm (1<<0) /* Input Selection 0 bit 0 mask. */ -+#define XCL_IN0SEL0_bp 0 /* Input Selection 0 bit 0 position. */ -+#define XCL_IN0SEL1_bm (1<<1) /* Input Selection 0 bit 1 mask. */ -+#define XCL_IN0SEL1_bp 1 /* Input Selection 0 bit 1 position. */ -+ -+/* XCL.CTRLC bit masks and bit positions */ -+#define XCL_EVASYSEL1_bm 0x80 /* Asynchronous Event Line Selection for LUT1 bit mask. */ -+#define XCL_EVASYSEL1_bp 7 /* Asynchronous Event Line Selection for LUT1 bit position. */ -+ -+#define XCL_EVASYSEL0_bm 0x40 /* Asynchronous Event Line Selection for LUT0 bit mask. */ -+#define XCL_EVASYSEL0_bp 6 /* Asynchronous Event Line Selection for LUT0 bit position. */ -+ -+#define XCL_DLYSEL_gm 0x30 /* Delay Selection group mask. */ -+#define XCL_DLYSEL_gp 4 /* Delay Selection group position. */ -+#define XCL_DLYSEL0_bm (1<<4) /* Delay Selection bit 0 mask. */ -+#define XCL_DLYSEL0_bp 4 /* Delay Selection bit 0 position. */ -+#define XCL_DLYSEL1_bm (1<<5) /* Delay Selection bit 1 mask. */ -+#define XCL_DLYSEL1_bp 5 /* Delay Selection bit 1 position. */ -+ -+#define XCL_DLY1CONF_gm 0x0C /* Delay Configuration on LUT1 group mask. */ -+#define XCL_DLY1CONF_gp 2 /* Delay Configuration on LUT1 group position. */ -+#define XCL_DLY1CONF0_bm (1<<2) /* Delay Configuration on LUT1 bit 0 mask. */ -+#define XCL_DLY1CONF0_bp 2 /* Delay Configuration on LUT1 bit 0 position. */ -+#define XCL_DLY1CONF1_bm (1<<3) /* Delay Configuration on LUT1 bit 1 mask. */ -+#define XCL_DLY1CONF1_bp 3 /* Delay Configuration on LUT1 bit 1 position. */ -+ -+#define XCL_DLY0CONF_gm 0x03 /* Delay Configuration on LUT0 group mask. */ -+#define XCL_DLY0CONF_gp 0 /* Delay Configuration on LUT0 group position. */ -+#define XCL_DLY0CONF0_bm (1<<0) /* Delay Configuration on LUT0 bit 0 mask. */ -+#define XCL_DLY0CONF0_bp 0 /* Delay Configuration on LUT0 bit 0 position. */ -+#define XCL_DLY0CONF1_bm (1<<1) /* Delay Configuration on LUT0 bit 1 mask. */ -+#define XCL_DLY0CONF1_bp 1 /* Delay Configuration on LUT0 bit 1 position. */ -+ -+/* XCL.CTRLD bit masks and bit positions */ -+#define XCL_TRUTH1_gm 0xF0 /* Truth Table of LUT1 group mask. */ -+#define XCL_TRUTH1_gp 4 /* Truth Table of LUT1 group position. */ -+#define XCL_TRUTH10_bm (1<<4) /* Truth Table of LUT1 bit 0 mask. */ -+#define XCL_TRUTH10_bp 4 /* Truth Table of LUT1 bit 0 position. */ -+#define XCL_TRUTH11_bm (1<<5) /* Truth Table of LUT1 bit 1 mask. */ -+#define XCL_TRUTH11_bp 5 /* Truth Table of LUT1 bit 1 position. */ -+#define XCL_TRUTH12_bm (1<<6) /* Truth Table of LUT1 bit 2 mask. */ -+#define XCL_TRUTH12_bp 6 /* Truth Table of LUT1 bit 2 position. */ -+#define XCL_TRUTH13_bm (1<<7) /* Truth Table of LUT1 bit 3 mask. */ -+#define XCL_TRUTH13_bp 7 /* Truth Table of LUT1 bit 3 position. */ -+ -+#define XCL_TRUTH0_gm 0x0F /* Truth Table of LUT0 group mask. */ -+#define XCL_TRUTH0_gp 0 /* Truth Table of LUT0 group position. */ -+#define XCL_TRUTH00_bm (1<<0) /* Truth Table of LUT0 bit 0 mask. */ -+#define XCL_TRUTH00_bp 0 /* Truth Table of LUT0 bit 0 position. */ -+#define XCL_TRUTH01_bm (1<<1) /* Truth Table of LUT0 bit 1 mask. */ -+#define XCL_TRUTH01_bp 1 /* Truth Table of LUT0 bit 1 position. */ -+#define XCL_TRUTH02_bm (1<<2) /* Truth Table of LUT0 bit 2 mask. */ -+#define XCL_TRUTH02_bp 2 /* Truth Table of LUT0 bit 2 position. */ -+#define XCL_TRUTH03_bm (1<<3) /* Truth Table of LUT0 bit 3 mask. */ -+#define XCL_TRUTH03_bp 3 /* Truth Table of LUT0 bit 3 position. */ -+ -+/* XCL.CTRLE bit masks and bit positions */ -+#define XCL_CMDSEL_bm 0x80 /* Timer/Counter Command Selection bit mask. */ -+#define XCL_CMDSEL_bp 7 /* Timer/Counter Command Selection bit position. */ -+ -+#define XCL_TCSEL_gm 0x70 /* Timer/Counter Selection group mask. */ -+#define XCL_TCSEL_gp 4 /* Timer/Counter Selection group position. */ -+#define XCL_TCSEL0_bm (1<<4) /* Timer/Counter Selection bit 0 mask. */ -+#define XCL_TCSEL0_bp 4 /* Timer/Counter Selection bit 0 position. */ -+#define XCL_TCSEL1_bm (1<<5) /* Timer/Counter Selection bit 1 mask. */ -+#define XCL_TCSEL1_bp 5 /* Timer/Counter Selection bit 1 position. */ -+#define XCL_TCSEL2_bm (1<<6) /* Timer/Counter Selection bit 2 mask. */ -+#define XCL_TCSEL2_bp 6 /* Timer/Counter Selection bit 2 position. */ -+ -+#define XCL_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define XCL_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define XCL_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define XCL_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define XCL_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define XCL_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define XCL_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define XCL_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define XCL_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define XCL_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* XCL.CTRLF bit masks and bit positions */ -+#define XCL_CMDEN_gm 0xC0 /* Command Enable group mask. */ -+#define XCL_CMDEN_gp 6 /* Command Enable group position. */ -+#define XCL_CMDEN0_bm (1<<6) /* Command Enable bit 0 mask. */ -+#define XCL_CMDEN0_bp 6 /* Command Enable bit 0 position. */ -+#define XCL_CMDEN1_bm (1<<7) /* Command Enable bit 1 mask. */ -+#define XCL_CMDEN1_bp 7 /* Command Enable bit 1 position. */ -+ -+#define XCL_CMP1_bm 0x20 /* Compare Channel 1 Output Value bit mask. */ -+#define XCL_CMP1_bp 5 /* Compare Channel 1 Output Value bit position. */ -+ -+#define XCL_CMP0_bm 0x10 /* Compare Channel 0 Output Value bit mask. */ -+#define XCL_CMP0_bp 4 /* Compare Channel 0 Output Value bit position. */ -+ -+#define XCL_CCEN1_bm 0x08 /* Compare or Capture Channel 1 Enable bit mask. */ -+#define XCL_CCEN1_bp 3 /* Compare or Capture Channel 1 Enable bit position. */ -+ -+#define XCL_CCEN0_bm 0x04 /* Compare or Capture Channel 0 Enable bit mask. */ -+#define XCL_CCEN0_bp 2 /* Compare or Capture Channel 0 Enable bit position. */ -+ -+#define XCL_MODE_gm 0x03 /* Timer/Counter Mode group mask. */ -+#define XCL_MODE_gp 0 /* Timer/Counter Mode group position. */ -+#define XCL_MODE0_bm (1<<0) /* Timer/Counter Mode bit 0 mask. */ -+#define XCL_MODE0_bp 0 /* Timer/Counter Mode bit 0 position. */ -+#define XCL_MODE1_bm (1<<1) /* Timer/Counter Mode bit 1 mask. */ -+#define XCL_MODE1_bp 1 /* Timer/Counter Mode bit 1 position. */ -+ -+/* XCL.CTRLG bit masks and bit positions */ -+#define XCL_EVACTEN_bm 0x80 /* Event Action Enable bit mask. */ -+#define XCL_EVACTEN_bp 7 /* Event Action Enable bit position. */ -+ -+#define XCL_EVACT1_gm 0x60 /* Event Action Selection on Timer/Counter 1 group mask. */ -+#define XCL_EVACT1_gp 5 /* Event Action Selection on Timer/Counter 1 group position. */ -+#define XCL_EVACT10_bm (1<<5) /* Event Action Selection on Timer/Counter 1 bit 0 mask. */ -+#define XCL_EVACT10_bp 5 /* Event Action Selection on Timer/Counter 1 bit 0 position. */ -+#define XCL_EVACT11_bm (1<<6) /* Event Action Selection on Timer/Counter 1 bit 1 mask. */ -+#define XCL_EVACT11_bp 6 /* Event Action Selection on Timer/Counter 1 bit 1 position. */ -+ -+#define XCL_EVACT0_gm 0x18 /* Event Action Selection on Timer/Counter 0 group mask. */ -+#define XCL_EVACT0_gp 3 /* Event Action Selection on Timer/Counter 0 group position. */ -+#define XCL_EVACT00_bm (1<<3) /* Event Action Selection on Timer/Counter 0 bit 0 mask. */ -+#define XCL_EVACT00_bp 3 /* Event Action Selection on Timer/Counter 0 bit 0 position. */ -+#define XCL_EVACT01_bm (1<<4) /* Event Action Selection on Timer/Counter 0 bit 1 mask. */ -+#define XCL_EVACT01_bp 4 /* Event Action Selection on Timer/Counter 0 bit 1 position. */ -+ -+#define XCL_EVSRC_gm 0x07 /* Event Source Selection group mask. */ -+#define XCL_EVSRC_gp 0 /* Event Source Selection group position. */ -+#define XCL_EVSRC0_bm (1<<0) /* Event Source Selection bit 0 mask. */ -+#define XCL_EVSRC0_bp 0 /* Event Source Selection bit 0 position. */ -+#define XCL_EVSRC1_bm (1<<1) /* Event Source Selection bit 1 mask. */ -+#define XCL_EVSRC1_bp 1 /* Event Source Selection bit 1 position. */ -+#define XCL_EVSRC2_bm (1<<2) /* Event Source Selection bit 2 mask. */ -+#define XCL_EVSRC2_bp 2 /* Event Source Selection bit 2 position. */ -+ -+/* XCL.INTCTRL bit masks and bit positions */ -+#define XCL_UNF1IE_bm 0x80 /* Underflow 1 Interrupt Enable bit mask. */ -+#define XCL_UNF1IE_bp 7 /* Underflow 1 Interrupt Enable bit position. */ -+ -+#define XCL_PEC1IE_bm 0x80 /* Peripheral Counter 1 Interrupt Enable bit mask. */ -+#define XCL_PEC1IE_bp 7 /* Peripheral Counter 1 Interrupt Enable bit position. */ -+ -+#define XCL_PEC21IE_bm 0x80 /* Peripheral High Counter 2 Interrupt Enable bit mask. */ -+#define XCL_PEC21IE_bp 7 /* Peripheral High Counter 2 Interrupt Enable bit position. */ -+ -+#define XCL_UNF0IE_bm 0x40 /* Underflow 0 Interrupt Enable bit mask. */ -+#define XCL_UNF0IE_bp 6 /* Underflow 0 Interrupt Enable bit position. */ -+ -+#define XCL_PEC0IE_bm 0x40 /* Peripheral Counter 0 Interrupt Enable bit mask. */ -+#define XCL_PEC0IE_bp 6 /* Peripheral Counter 0 Interrupt Enable bit position. */ -+ -+#define XCL_CC1IE_bm 0x20 /* Compare Or Capture 1 Interrupt Enable bit mask. */ -+#define XCL_CC1IE_bp 5 /* Compare Or Capture 1 Interrupt Enable bit position. */ -+ -+#define XCL_PEC20IE_bm 0x20 /* Peripheral Low Counter 2 Interrupt Enable bit mask. */ -+#define XCL_PEC20IE_bp 5 /* Peripheral Low Counter 2 Interrupt Enable bit position. */ -+ -+#define XCL_CC0IE_bm 0x10 /* Compare Or Capture 0 Interrupt Enable bit mask. */ -+#define XCL_CC0IE_bp 4 /* Compare Or Capture 0 Interrupt Enable bit position. */ -+ -+#define XCL_UNFINTLVL_gm 0x0C /* Timer Underflow Interrupt Level group mask. */ -+#define XCL_UNFINTLVL_gp 2 /* Timer Underflow Interrupt Level group position. */ -+#define XCL_UNFINTLVL0_bm (1<<2) /* Timer Underflow Interrupt Level bit 0 mask. */ -+#define XCL_UNFINTLVL0_bp 2 /* Timer Underflow Interrupt Level bit 0 position. */ -+#define XCL_UNFINTLVL1_bm (1<<3) /* Timer Underflow Interrupt Level bit 1 mask. */ -+#define XCL_UNFINTLVL1_bp 3 /* Timer Underflow Interrupt Level bit 1 position. */ -+ -+#define XCL_CCINTLVL_gm 0x03 /* Timer Compare or Capture Interrupt Level group mask. */ -+#define XCL_CCINTLVL_gp 0 /* Timer Compare or Capture Interrupt Level group position. */ -+#define XCL_CCINTLVL0_bm (1<<0) /* Timer Compare or Capture Interrupt Level bit 0 mask. */ -+#define XCL_CCINTLVL0_bp 0 /* Timer Compare or Capture Interrupt Level bit 0 position. */ -+#define XCL_CCINTLVL1_bm (1<<1) /* Timer Compare or Capture Interrupt Level bit 1 mask. */ -+#define XCL_CCINTLVL1_bp 1 /* Timer Compare or Capture Interrupt Level bit 1 position. */ -+ -+/* XCL.INTFLAGS bit masks and bit positions */ -+#define XCL_UNF1IF_bm 0x80 /* Timer/Counter 1 Underflow Interrupt Flag bit mask. */ -+#define XCL_UNF1IF_bp 7 /* Timer/Counter 1 Underflow Interrupt Flag bit position. */ -+ -+#define XCL_PEC1IF_bm 0x80 /* Peripheral Counter 1 Interrupt Flag bit mask. */ -+#define XCL_PEC1IF_bp 7 /* Peripheral Counter 1 Interrupt Flag bit position. */ -+ -+#define XCL_PEC21IF_bm 0x80 /* Peripheral High Counter 2 Interrupt Flag bit mask. */ -+#define XCL_PEC21IF_bp 7 /* Peripheral High Counter 2 Interrupt Flag bit position. */ -+ -+#define XCL_UNF0IF_bm 0x40 /* Timer/Counter 0 Underflow Interrupt Flag bit mask. */ -+#define XCL_UNF0IF_bp 6 /* Timer/Counter 0 Underflow Interrupt Flag bit position. */ -+ -+#define XCL_PEC0IF_bm 0x40 /* Peripheral Counter 0 Interrupt Flag bit mask. */ -+#define XCL_PEC0IF_bp 6 /* Peripheral Counter 0 Interrupt Flag bit position. */ -+ -+#define XCL_CC1IF_bm 0x20 /* Compare or Capture Channel 1 Interrupt Flag bit mask. */ -+#define XCL_CC1IF_bp 5 /* Compare or Capture Channel 1 Interrupt Flag bit position. */ -+ -+#define XCL_PEC20IF_bm 0x20 /* Peripheral Low Counter 2 Interrupt Flag bit mask. */ -+#define XCL_PEC20IF_bp 5 /* Peripheral Low Counter 2 Interrupt Flag bit position. */ -+ -+#define XCL_CC0IF_bm 0x10 /* Compare or Capture Channel 0 Interrupt Flag bit mask. */ -+#define XCL_CC0IF_bp 4 /* Compare or Capture Channel 0 Interrupt Flag bit position. */ -+ -+/* XCL.PLC bit masks and bit positions */ -+#define XCL_PLC_gm 0xFF /* Peripheral Lenght Control Bits group mask. */ -+#define XCL_PLC_gp 0 /* Peripheral Lenght Control Bits group position. */ -+#define XCL_PLC0_bm (1<<0) /* Peripheral Lenght Control Bits bit 0 mask. */ -+#define XCL_PLC0_bp 0 /* Peripheral Lenght Control Bits bit 0 position. */ -+#define XCL_PLC1_bm (1<<1) /* Peripheral Lenght Control Bits bit 1 mask. */ -+#define XCL_PLC1_bp 1 /* Peripheral Lenght Control Bits bit 1 position. */ -+#define XCL_PLC2_bm (1<<2) /* Peripheral Lenght Control Bits bit 2 mask. */ -+#define XCL_PLC2_bp 2 /* Peripheral Lenght Control Bits bit 2 position. */ -+#define XCL_PLC3_bm (1<<3) /* Peripheral Lenght Control Bits bit 3 mask. */ -+#define XCL_PLC3_bp 3 /* Peripheral Lenght Control Bits bit 3 position. */ -+#define XCL_PLC4_bm (1<<4) /* Peripheral Lenght Control Bits bit 4 mask. */ -+#define XCL_PLC4_bp 4 /* Peripheral Lenght Control Bits bit 4 position. */ -+#define XCL_PLC5_bm (1<<5) /* Peripheral Lenght Control Bits bit 5 mask. */ -+#define XCL_PLC5_bp 5 /* Peripheral Lenght Control Bits bit 5 position. */ -+#define XCL_PLC6_bm (1<<6) /* Peripheral Lenght Control Bits bit 6 mask. */ -+#define XCL_PLC6_bp 6 /* Peripheral Lenght Control Bits bit 6 position. */ -+#define XCL_PLC7_bm (1<<7) /* Peripheral Lenght Control Bits bit 7 mask. */ -+#define XCL_PLC7_bp 7 /* Peripheral Lenght Control Bits bit 7 position. */ -+ -+/* XCL.CNTL bit masks and bit positions */ -+#define XCL_BCNTO_gm 0xFF /* BTC0 Counter Byte group mask. */ -+#define XCL_BCNTO_gp 0 /* BTC0 Counter Byte group position. */ -+#define XCL_BCNTO0_bm (1<<0) /* BTC0 Counter Byte bit 0 mask. */ -+#define XCL_BCNTO0_bp 0 /* BTC0 Counter Byte bit 0 position. */ -+#define XCL_BCNTO1_bm (1<<1) /* BTC0 Counter Byte bit 1 mask. */ -+#define XCL_BCNTO1_bp 1 /* BTC0 Counter Byte bit 1 position. */ -+#define XCL_BCNTO2_bm (1<<2) /* BTC0 Counter Byte bit 2 mask. */ -+#define XCL_BCNTO2_bp 2 /* BTC0 Counter Byte bit 2 position. */ -+#define XCL_BCNTO3_bm (1<<3) /* BTC0 Counter Byte bit 3 mask. */ -+#define XCL_BCNTO3_bp 3 /* BTC0 Counter Byte bit 3 position. */ -+#define XCL_BCNTO4_bm (1<<4) /* BTC0 Counter Byte bit 4 mask. */ -+#define XCL_BCNTO4_bp 4 /* BTC0 Counter Byte bit 4 position. */ -+#define XCL_BCNTO5_bm (1<<5) /* BTC0 Counter Byte bit 5 mask. */ -+#define XCL_BCNTO5_bp 5 /* BTC0 Counter Byte bit 5 position. */ -+#define XCL_BCNTO6_bm (1<<6) /* BTC0 Counter Byte bit 6 mask. */ -+#define XCL_BCNTO6_bp 6 /* BTC0 Counter Byte bit 6 position. */ -+#define XCL_BCNTO7_bm (1<<7) /* BTC0 Counter Byte bit 7 mask. */ -+#define XCL_BCNTO7_bp 7 /* BTC0 Counter Byte bit 7 position. */ -+ -+#define XCL_CNTL_gm 0xFF /* TC16 Counter Low Byte group mask. */ -+#define XCL_CNTL_gp 0 /* TC16 Counter Low Byte group position. */ -+#define XCL_CNTL0_bm (1<<0) /* TC16 Counter Low Byte bit 0 mask. */ -+#define XCL_CNTL0_bp 0 /* TC16 Counter Low Byte bit 0 position. */ -+#define XCL_CNTL1_bm (1<<1) /* TC16 Counter Low Byte bit 1 mask. */ -+#define XCL_CNTL1_bp 1 /* TC16 Counter Low Byte bit 1 position. */ -+#define XCL_CNTL2_bm (1<<2) /* TC16 Counter Low Byte bit 2 mask. */ -+#define XCL_CNTL2_bp 2 /* TC16 Counter Low Byte bit 2 position. */ -+#define XCL_CNTL3_bm (1<<3) /* TC16 Counter Low Byte bit 3 mask. */ -+#define XCL_CNTL3_bp 3 /* TC16 Counter Low Byte bit 3 position. */ -+#define XCL_CNTL4_bm (1<<4) /* TC16 Counter Low Byte bit 4 mask. */ -+#define XCL_CNTL4_bp 4 /* TC16 Counter Low Byte bit 4 position. */ -+#define XCL_CNTL5_bm (1<<5) /* TC16 Counter Low Byte bit 5 mask. */ -+#define XCL_CNTL5_bp 5 /* TC16 Counter Low Byte bit 5 position. */ -+#define XCL_CNTL6_bm (1<<6) /* TC16 Counter Low Byte bit 6 mask. */ -+#define XCL_CNTL6_bp 6 /* TC16 Counter Low Byte bit 6 position. */ -+#define XCL_CNTL7_bm (1<<7) /* TC16 Counter Low Byte bit 7 mask. */ -+#define XCL_CNTL7_bp 7 /* TC16 Counter Low Byte bit 7 position. */ -+ -+#define XCL_PCNTO_gm 0xFF /* Peripheral Counter 0 Byte group mask. */ -+#define XCL_PCNTO_gp 0 /* Peripheral Counter 0 Byte group position. */ -+#define XCL_PCNTO0_bm (1<<0) /* Peripheral Counter 0 Byte bit 0 mask. */ -+#define XCL_PCNTO0_bp 0 /* Peripheral Counter 0 Byte bit 0 position. */ -+#define XCL_PCNTO1_bm (1<<1) /* Peripheral Counter 0 Byte bit 1 mask. */ -+#define XCL_PCNTO1_bp 1 /* Peripheral Counter 0 Byte bit 1 position. */ -+#define XCL_PCNTO2_bm (1<<2) /* Peripheral Counter 0 Byte bit 2 mask. */ -+#define XCL_PCNTO2_bp 2 /* Peripheral Counter 0 Byte bit 2 position. */ -+#define XCL_PCNTO3_bm (1<<3) /* Peripheral Counter 0 Byte bit 3 mask. */ -+#define XCL_PCNTO3_bp 3 /* Peripheral Counter 0 Byte bit 3 position. */ -+#define XCL_PCNTO4_bm (1<<4) /* Peripheral Counter 0 Byte bit 4 mask. */ -+#define XCL_PCNTO4_bp 4 /* Peripheral Counter 0 Byte bit 4 position. */ -+#define XCL_PCNTO5_bm (1<<5) /* Peripheral Counter 0 Byte bit 5 mask. */ -+#define XCL_PCNTO5_bp 5 /* Peripheral Counter 0 Byte bit 5 position. */ -+#define XCL_PCNTO6_bm (1<<6) /* Peripheral Counter 0 Byte bit 6 mask. */ -+#define XCL_PCNTO6_bp 6 /* Peripheral Counter 0 Byte bit 6 position. */ -+#define XCL_PCNTO7_bm (1<<7) /* Peripheral Counter 0 Byte bit 7 mask. */ -+#define XCL_PCNTO7_bp 7 /* Peripheral Counter 0 Byte bit 7 position. */ -+ -+/* XCL.CNTH bit masks and bit positions */ -+#define XCL_BCNT1_gm 0xFF /* BTC1 Counter Byte group mask. */ -+#define XCL_BCNT1_gp 0 /* BTC1 Counter Byte group position. */ -+#define XCL_BCNT10_bm (1<<0) /* BTC1 Counter Byte bit 0 mask. */ -+#define XCL_BCNT10_bp 0 /* BTC1 Counter Byte bit 0 position. */ -+#define XCL_BCNT11_bm (1<<1) /* BTC1 Counter Byte bit 1 mask. */ -+#define XCL_BCNT11_bp 1 /* BTC1 Counter Byte bit 1 position. */ -+#define XCL_BCNT12_bm (1<<2) /* BTC1 Counter Byte bit 2 mask. */ -+#define XCL_BCNT12_bp 2 /* BTC1 Counter Byte bit 2 position. */ -+#define XCL_BCNT13_bm (1<<3) /* BTC1 Counter Byte bit 3 mask. */ -+#define XCL_BCNT13_bp 3 /* BTC1 Counter Byte bit 3 position. */ -+#define XCL_BCNT14_bm (1<<4) /* BTC1 Counter Byte bit 4 mask. */ -+#define XCL_BCNT14_bp 4 /* BTC1 Counter Byte bit 4 position. */ -+#define XCL_BCNT15_bm (1<<5) /* BTC1 Counter Byte bit 5 mask. */ -+#define XCL_BCNT15_bp 5 /* BTC1 Counter Byte bit 5 position. */ -+#define XCL_BCNT16_bm (1<<6) /* BTC1 Counter Byte bit 6 mask. */ -+#define XCL_BCNT16_bp 6 /* BTC1 Counter Byte bit 6 position. */ -+#define XCL_BCNT17_bm (1<<7) /* BTC1 Counter Byte bit 7 mask. */ -+#define XCL_BCNT17_bp 7 /* BTC1 Counter Byte bit 7 position. */ -+ -+#define XCL_CNTH_gm 0xFF /* TC16 Counter High Byte group mask. */ -+#define XCL_CNTH_gp 0 /* TC16 Counter High Byte group position. */ -+#define XCL_CNTH0_bm (1<<0) /* TC16 Counter High Byte bit 0 mask. */ -+#define XCL_CNTH0_bp 0 /* TC16 Counter High Byte bit 0 position. */ -+#define XCL_CNTH1_bm (1<<1) /* TC16 Counter High Byte bit 1 mask. */ -+#define XCL_CNTH1_bp 1 /* TC16 Counter High Byte bit 1 position. */ -+#define XCL_CNTH2_bm (1<<2) /* TC16 Counter High Byte bit 2 mask. */ -+#define XCL_CNTH2_bp 2 /* TC16 Counter High Byte bit 2 position. */ -+#define XCL_CNTH3_bm (1<<3) /* TC16 Counter High Byte bit 3 mask. */ -+#define XCL_CNTH3_bp 3 /* TC16 Counter High Byte bit 3 position. */ -+#define XCL_CNTH4_bm (1<<4) /* TC16 Counter High Byte bit 4 mask. */ -+#define XCL_CNTH4_bp 4 /* TC16 Counter High Byte bit 4 position. */ -+#define XCL_CNTH5_bm (1<<5) /* TC16 Counter High Byte bit 5 mask. */ -+#define XCL_CNTH5_bp 5 /* TC16 Counter High Byte bit 5 position. */ -+#define XCL_CNTH6_bm (1<<6) /* TC16 Counter High Byte bit 6 mask. */ -+#define XCL_CNTH6_bp 6 /* TC16 Counter High Byte bit 6 position. */ -+#define XCL_CNTH7_bm (1<<7) /* TC16 Counter High Byte bit 7 mask. */ -+#define XCL_CNTH7_bp 7 /* TC16 Counter High Byte bit 7 position. */ -+ -+#define XCL_PCNT1_gm 0xFF /* Peripheral Counter 1 Byte group mask. */ -+#define XCL_PCNT1_gp 0 /* Peripheral Counter 1 Byte group position. */ -+#define XCL_PCNT10_bm (1<<0) /* Peripheral Counter 1 Byte bit 0 mask. */ -+#define XCL_PCNT10_bp 0 /* Peripheral Counter 1 Byte bit 0 position. */ -+#define XCL_PCNT11_bm (1<<1) /* Peripheral Counter 1 Byte bit 1 mask. */ -+#define XCL_PCNT11_bp 1 /* Peripheral Counter 1 Byte bit 1 position. */ -+#define XCL_PCNT12_bm (1<<2) /* Peripheral Counter 1 Byte bit 2 mask. */ -+#define XCL_PCNT12_bp 2 /* Peripheral Counter 1 Byte bit 2 position. */ -+#define XCL_PCNT13_bm (1<<3) /* Peripheral Counter 1 Byte bit 3 mask. */ -+#define XCL_PCNT13_bp 3 /* Peripheral Counter 1 Byte bit 3 position. */ -+#define XCL_PCNT14_bm (1<<4) /* Peripheral Counter 1 Byte bit 4 mask. */ -+#define XCL_PCNT14_bp 4 /* Peripheral Counter 1 Byte bit 4 position. */ -+#define XCL_PCNT15_bm (1<<5) /* Peripheral Counter 1 Byte bit 5 mask. */ -+#define XCL_PCNT15_bp 5 /* Peripheral Counter 1 Byte bit 5 position. */ -+#define XCL_PCNT16_bm (1<<6) /* Peripheral Counter 1 Byte bit 6 mask. */ -+#define XCL_PCNT16_bp 6 /* Peripheral Counter 1 Byte bit 6 position. */ -+#define XCL_PCNT17_bm (1<<7) /* Peripheral Counter 1 Byte bit 7 mask. */ -+#define XCL_PCNT17_bp 7 /* Peripheral Counter 1 Byte bit 7 position. */ -+ -+#define XCL_PCNT21_gm 0xF0 /* Peripheral High Counter 2 Bits group mask. */ -+#define XCL_PCNT21_gp 4 /* Peripheral High Counter 2 Bits group position. */ -+#define XCL_PCNT210_bm (1<<4) /* Peripheral High Counter 2 Bits bit 0 mask. */ -+#define XCL_PCNT210_bp 4 /* Peripheral High Counter 2 Bits bit 0 position. */ -+#define XCL_PCNT211_bm (1<<5) /* Peripheral High Counter 2 Bits bit 1 mask. */ -+#define XCL_PCNT211_bp 5 /* Peripheral High Counter 2 Bits bit 1 position. */ -+#define XCL_PCNT212_bm (1<<6) /* Peripheral High Counter 2 Bits bit 2 mask. */ -+#define XCL_PCNT212_bp 6 /* Peripheral High Counter 2 Bits bit 2 position. */ -+#define XCL_PCNT213_bm (1<<7) /* Peripheral High Counter 2 Bits bit 3 mask. */ -+#define XCL_PCNT213_bp 7 /* Peripheral High Counter 2 Bits bit 3 position. */ -+ -+#define XCL_PCNT20_gm 0x0F /* Peripheral Low Counter 2 Bits group mask. */ -+#define XCL_PCNT20_gp 0 /* Peripheral Low Counter 2 Bits group position. */ -+#define XCL_PCNT200_bm (1<<0) /* Peripheral Low Counter 2 Bits bit 0 mask. */ -+#define XCL_PCNT200_bp 0 /* Peripheral Low Counter 2 Bits bit 0 position. */ -+#define XCL_PCNT201_bm (1<<1) /* Peripheral Low Counter 2 Bits bit 1 mask. */ -+#define XCL_PCNT201_bp 1 /* Peripheral Low Counter 2 Bits bit 1 position. */ -+#define XCL_PCNT202_bm (1<<2) /* Peripheral Low Counter 2 Bits bit 2 mask. */ -+#define XCL_PCNT202_bp 2 /* Peripheral Low Counter 2 Bits bit 2 position. */ -+#define XCL_PCNT203_bm (1<<3) /* Peripheral Low Counter 2 Bits bit 3 mask. */ -+#define XCL_PCNT203_bp 3 /* Peripheral Low Counter 2 Bits bit 3 position. */ -+ -+/* XCL.CMPL bit masks and bit positions */ -+#define XCL_CMPL_gm 0xFF /* TC16 Compare Low Byte group mask. */ -+#define XCL_CMPL_gp 0 /* TC16 Compare Low Byte group position. */ -+#define XCL_CMPL0_bm (1<<0) /* TC16 Compare Low Byte bit 0 mask. */ -+#define XCL_CMPL0_bp 0 /* TC16 Compare Low Byte bit 0 position. */ -+#define XCL_CMPL1_bm (1<<1) /* TC16 Compare Low Byte bit 1 mask. */ -+#define XCL_CMPL1_bp 1 /* TC16 Compare Low Byte bit 1 position. */ -+#define XCL_CMPL2_bm (1<<2) /* TC16 Compare Low Byte bit 2 mask. */ -+#define XCL_CMPL2_bp 2 /* TC16 Compare Low Byte bit 2 position. */ -+#define XCL_CMPL3_bm (1<<3) /* TC16 Compare Low Byte bit 3 mask. */ -+#define XCL_CMPL3_bp 3 /* TC16 Compare Low Byte bit 3 position. */ -+#define XCL_CMPL4_bm (1<<4) /* TC16 Compare Low Byte bit 4 mask. */ -+#define XCL_CMPL4_bp 4 /* TC16 Compare Low Byte bit 4 position. */ -+#define XCL_CMPL5_bm (1<<5) /* TC16 Compare Low Byte bit 5 mask. */ -+#define XCL_CMPL5_bp 5 /* TC16 Compare Low Byte bit 5 position. */ -+#define XCL_CMPL6_bm (1<<6) /* TC16 Compare Low Byte bit 6 mask. */ -+#define XCL_CMPL6_bp 6 /* TC16 Compare Low Byte bit 6 position. */ -+#define XCL_CMPL7_bm (1<<7) /* TC16 Compare Low Byte bit 7 mask. */ -+#define XCL_CMPL7_bp 7 /* TC16 Compare Low Byte bit 7 position. */ -+ -+#define XCL_BCMP0_gm 0xFF /* BTC0 Compare Byte group mask. */ -+#define XCL_BCMP0_gp 0 /* BTC0 Compare Byte group position. */ -+#define XCL_BCMP00_bm (1<<0) /* BTC0 Compare Byte bit 0 mask. */ -+#define XCL_BCMP00_bp 0 /* BTC0 Compare Byte bit 0 position. */ -+#define XCL_BCMP01_bm (1<<1) /* BTC0 Compare Byte bit 1 mask. */ -+#define XCL_BCMP01_bp 1 /* BTC0 Compare Byte bit 1 position. */ -+#define XCL_BCMP02_bm (1<<2) /* BTC0 Compare Byte bit 2 mask. */ -+#define XCL_BCMP02_bp 2 /* BTC0 Compare Byte bit 2 position. */ -+#define XCL_BCMP03_bm (1<<3) /* BTC0 Compare Byte bit 3 mask. */ -+#define XCL_BCMP03_bp 3 /* BTC0 Compare Byte bit 3 position. */ -+#define XCL_BCMP04_bm (1<<4) /* BTC0 Compare Byte bit 4 mask. */ -+#define XCL_BCMP04_bp 4 /* BTC0 Compare Byte bit 4 position. */ -+#define XCL_BCMP05_bm (1<<5) /* BTC0 Compare Byte bit 5 mask. */ -+#define XCL_BCMP05_bp 5 /* BTC0 Compare Byte bit 5 position. */ -+#define XCL_BCMP06_bm (1<<6) /* BTC0 Compare Byte bit 6 mask. */ -+#define XCL_BCMP06_bp 6 /* BTC0 Compare Byte bit 6 position. */ -+#define XCL_BCMP07_bm (1<<7) /* BTC0 Compare Byte bit 7 mask. */ -+#define XCL_BCMP07_bp 7 /* BTC0 Compare Byte bit 7 position. */ -+ -+/* XCL.CMPH bit masks and bit positions */ -+#define XCL_CMPH_gm 0xFF /* TC16 Compare High Byte group mask. */ -+#define XCL_CMPH_gp 0 /* TC16 Compare High Byte group position. */ -+#define XCL_CMPH0_bm (1<<0) /* TC16 Compare High Byte bit 0 mask. */ -+#define XCL_CMPH0_bp 0 /* TC16 Compare High Byte bit 0 position. */ -+#define XCL_CMPH1_bm (1<<1) /* TC16 Compare High Byte bit 1 mask. */ -+#define XCL_CMPH1_bp 1 /* TC16 Compare High Byte bit 1 position. */ -+#define XCL_CMPH2_bm (1<<2) /* TC16 Compare High Byte bit 2 mask. */ -+#define XCL_CMPH2_bp 2 /* TC16 Compare High Byte bit 2 position. */ -+#define XCL_CMPH3_bm (1<<3) /* TC16 Compare High Byte bit 3 mask. */ -+#define XCL_CMPH3_bp 3 /* TC16 Compare High Byte bit 3 position. */ -+#define XCL_CMPH4_bm (1<<4) /* TC16 Compare High Byte bit 4 mask. */ -+#define XCL_CMPH4_bp 4 /* TC16 Compare High Byte bit 4 position. */ -+#define XCL_CMPH5_bm (1<<5) /* TC16 Compare High Byte bit 5 mask. */ -+#define XCL_CMPH5_bp 5 /* TC16 Compare High Byte bit 5 position. */ -+#define XCL_CMPH6_bm (1<<6) /* TC16 Compare High Byte bit 6 mask. */ -+#define XCL_CMPH6_bp 6 /* TC16 Compare High Byte bit 6 position. */ -+#define XCL_CMPH7_bm (1<<7) /* TC16 Compare High Byte bit 7 mask. */ -+#define XCL_CMPH7_bp 7 /* TC16 Compare High Byte bit 7 position. */ -+ -+#define XCL_BCMP1_gm 0xFF /* BTC1 Compare Byte group mask. */ -+#define XCL_BCMP1_gp 0 /* BTC1 Compare Byte group position. */ -+#define XCL_BCMP10_bm (1<<0) /* BTC1 Compare Byte bit 0 mask. */ -+#define XCL_BCMP10_bp 0 /* BTC1 Compare Byte bit 0 position. */ -+#define XCL_BCMP11_bm (1<<1) /* BTC1 Compare Byte bit 1 mask. */ -+#define XCL_BCMP11_bp 1 /* BTC1 Compare Byte bit 1 position. */ -+#define XCL_BCMP12_bm (1<<2) /* BTC1 Compare Byte bit 2 mask. */ -+#define XCL_BCMP12_bp 2 /* BTC1 Compare Byte bit 2 position. */ -+#define XCL_BCMP13_bm (1<<3) /* BTC1 Compare Byte bit 3 mask. */ -+#define XCL_BCMP13_bp 3 /* BTC1 Compare Byte bit 3 position. */ -+#define XCL_BCMP14_bm (1<<4) /* BTC1 Compare Byte bit 4 mask. */ -+#define XCL_BCMP14_bp 4 /* BTC1 Compare Byte bit 4 position. */ -+#define XCL_BCMP15_bm (1<<5) /* BTC1 Compare Byte bit 5 mask. */ -+#define XCL_BCMP15_bp 5 /* BTC1 Compare Byte bit 5 position. */ -+#define XCL_BCMP16_bm (1<<6) /* BTC1 Compare Byte bit 6 mask. */ -+#define XCL_BCMP16_bp 6 /* BTC1 Compare Byte bit 6 position. */ -+#define XCL_BCMP17_bm (1<<7) /* BTC1 Compare Byte bit 7 mask. */ -+#define XCL_BCMP17_bp 7 /* BTC1 Compare Byte bit 7 position. */ -+ -+/* XCL.PERCAPTL bit masks and bit positions */ -+#define XCL_PERL_gm 0xFF /* TC16 Low Byte Period group mask. */ -+#define XCL_PERL_gp 0 /* TC16 Low Byte Period group position. */ -+#define XCL_PERL0_bm (1<<0) /* TC16 Low Byte Period bit 0 mask. */ -+#define XCL_PERL0_bp 0 /* TC16 Low Byte Period bit 0 position. */ -+#define XCL_PERL1_bm (1<<1) /* TC16 Low Byte Period bit 1 mask. */ -+#define XCL_PERL1_bp 1 /* TC16 Low Byte Period bit 1 position. */ -+#define XCL_PERL2_bm (1<<2) /* TC16 Low Byte Period bit 2 mask. */ -+#define XCL_PERL2_bp 2 /* TC16 Low Byte Period bit 2 position. */ -+#define XCL_PERL3_bm (1<<3) /* TC16 Low Byte Period bit 3 mask. */ -+#define XCL_PERL3_bp 3 /* TC16 Low Byte Period bit 3 position. */ -+#define XCL_PERL4_bm (1<<4) /* TC16 Low Byte Period bit 4 mask. */ -+#define XCL_PERL4_bp 4 /* TC16 Low Byte Period bit 4 position. */ -+#define XCL_PERL5_bm (1<<5) /* TC16 Low Byte Period bit 5 mask. */ -+#define XCL_PERL5_bp 5 /* TC16 Low Byte Period bit 5 position. */ -+#define XCL_PERL6_bm (1<<6) /* TC16 Low Byte Period bit 6 mask. */ -+#define XCL_PERL6_bp 6 /* TC16 Low Byte Period bit 6 position. */ -+#define XCL_PERL7_bm (1<<7) /* TC16 Low Byte Period bit 7 mask. */ -+#define XCL_PERL7_bp 7 /* TC16 Low Byte Period bit 7 position. */ -+ -+#define XCL_CAPTL_gm 0xFF /* TC16 Capture Value Low Byte group mask. */ -+#define XCL_CAPTL_gp 0 /* TC16 Capture Value Low Byte group position. */ -+#define XCL_CAPTL0_bm (1<<0) /* TC16 Capture Value Low Byte bit 0 mask. */ -+#define XCL_CAPTL0_bp 0 /* TC16 Capture Value Low Byte bit 0 position. */ -+#define XCL_CAPTL1_bm (1<<1) /* TC16 Capture Value Low Byte bit 1 mask. */ -+#define XCL_CAPTL1_bp 1 /* TC16 Capture Value Low Byte bit 1 position. */ -+#define XCL_CAPTL2_bm (1<<2) /* TC16 Capture Value Low Byte bit 2 mask. */ -+#define XCL_CAPTL2_bp 2 /* TC16 Capture Value Low Byte bit 2 position. */ -+#define XCL_CAPTL3_bm (1<<3) /* TC16 Capture Value Low Byte bit 3 mask. */ -+#define XCL_CAPTL3_bp 3 /* TC16 Capture Value Low Byte bit 3 position. */ -+#define XCL_CAPTL4_bm (1<<4) /* TC16 Capture Value Low Byte bit 4 mask. */ -+#define XCL_CAPTL4_bp 4 /* TC16 Capture Value Low Byte bit 4 position. */ -+#define XCL_CAPTL5_bm (1<<5) /* TC16 Capture Value Low Byte bit 5 mask. */ -+#define XCL_CAPTL5_bp 5 /* TC16 Capture Value Low Byte bit 5 position. */ -+#define XCL_CAPTL6_bm (1<<6) /* TC16 Capture Value Low Byte bit 6 mask. */ -+#define XCL_CAPTL6_bp 6 /* TC16 Capture Value Low Byte bit 6 position. */ -+#define XCL_CAPTL7_bm (1<<7) /* TC16 Capture Value Low Byte bit 7 mask. */ -+#define XCL_CAPTL7_bp 7 /* TC16 Capture Value Low Byte bit 7 position. */ -+ -+#define XCL_BPER0_gm 0xFF /* BTC0 Period group mask. */ -+#define XCL_BPER0_gp 0 /* BTC0 Period group position. */ -+#define XCL_BPER00_bm (1<<0) /* BTC0 Period bit 0 mask. */ -+#define XCL_BPER00_bp 0 /* BTC0 Period bit 0 position. */ -+#define XCL_BPER01_bm (1<<1) /* BTC0 Period bit 1 mask. */ -+#define XCL_BPER01_bp 1 /* BTC0 Period bit 1 position. */ -+#define XCL_BPER02_bm (1<<2) /* BTC0 Period bit 2 mask. */ -+#define XCL_BPER02_bp 2 /* BTC0 Period bit 2 position. */ -+#define XCL_BPER03_bm (1<<3) /* BTC0 Period bit 3 mask. */ -+#define XCL_BPER03_bp 3 /* BTC0 Period bit 3 position. */ -+#define XCL_BPER04_bm (1<<4) /* BTC0 Period bit 4 mask. */ -+#define XCL_BPER04_bp 4 /* BTC0 Period bit 4 position. */ -+#define XCL_BPER05_bm (1<<5) /* BTC0 Period bit 5 mask. */ -+#define XCL_BPER05_bp 5 /* BTC0 Period bit 5 position. */ -+#define XCL_BPER06_bm (1<<6) /* BTC0 Period bit 6 mask. */ -+#define XCL_BPER06_bp 6 /* BTC0 Period bit 6 position. */ -+#define XCL_BPER07_bm (1<<7) /* BTC0 Period bit 7 mask. */ -+#define XCL_BPER07_bp 7 /* BTC0 Period bit 7 position. */ -+ -+#define XCL_BCAPT0_gm 0xFF /* BTC0 Capture Value Byte group mask. */ -+#define XCL_BCAPT0_gp 0 /* BTC0 Capture Value Byte group position. */ -+#define XCL_BCAPT00_bm (1<<0) /* BTC0 Capture Value Byte bit 0 mask. */ -+#define XCL_BCAPT00_bp 0 /* BTC0 Capture Value Byte bit 0 position. */ -+#define XCL_BCAPT01_bm (1<<1) /* BTC0 Capture Value Byte bit 1 mask. */ -+#define XCL_BCAPT01_bp 1 /* BTC0 Capture Value Byte bit 1 position. */ -+#define XCL_BCAPT02_bm (1<<2) /* BTC0 Capture Value Byte bit 2 mask. */ -+#define XCL_BCAPT02_bp 2 /* BTC0 Capture Value Byte bit 2 position. */ -+#define XCL_BCAPT03_bm (1<<3) /* BTC0 Capture Value Byte bit 3 mask. */ -+#define XCL_BCAPT03_bp 3 /* BTC0 Capture Value Byte bit 3 position. */ -+#define XCL_BCAPT04_bm (1<<4) /* BTC0 Capture Value Byte bit 4 mask. */ -+#define XCL_BCAPT04_bp 4 /* BTC0 Capture Value Byte bit 4 position. */ -+#define XCL_BCAPT05_bm (1<<5) /* BTC0 Capture Value Byte bit 5 mask. */ -+#define XCL_BCAPT05_bp 5 /* BTC0 Capture Value Byte bit 5 position. */ -+#define XCL_BCAPT06_bm (1<<6) /* BTC0 Capture Value Byte bit 6 mask. */ -+#define XCL_BCAPT06_bp 6 /* BTC0 Capture Value Byte bit 6 position. */ -+#define XCL_BCAPT07_bm (1<<7) /* BTC0 Capture Value Byte bit 7 mask. */ -+#define XCL_BCAPT07_bp 7 /* BTC0 Capture Value Byte bit 7 position. */ -+ -+/* XCL.PERCAPTH bit masks and bit positions */ -+#define XCL_PERH_gm 0xFF /* TC16 High Byte Period group mask. */ -+#define XCL_PERH_gp 0 /* TC16 High Byte Period group position. */ -+#define XCL_PERH0_bm (1<<0) /* TC16 High Byte Period bit 0 mask. */ -+#define XCL_PERH0_bp 0 /* TC16 High Byte Period bit 0 position. */ -+#define XCL_PERH1_bm (1<<1) /* TC16 High Byte Period bit 1 mask. */ -+#define XCL_PERH1_bp 1 /* TC16 High Byte Period bit 1 position. */ -+#define XCL_PERH2_bm (1<<2) /* TC16 High Byte Period bit 2 mask. */ -+#define XCL_PERH2_bp 2 /* TC16 High Byte Period bit 2 position. */ -+#define XCL_PERH3_bm (1<<3) /* TC16 High Byte Period bit 3 mask. */ -+#define XCL_PERH3_bp 3 /* TC16 High Byte Period bit 3 position. */ -+#define XCL_PERH4_bm (1<<4) /* TC16 High Byte Period bit 4 mask. */ -+#define XCL_PERH4_bp 4 /* TC16 High Byte Period bit 4 position. */ -+#define XCL_PERH5_bm (1<<5) /* TC16 High Byte Period bit 5 mask. */ -+#define XCL_PERH5_bp 5 /* TC16 High Byte Period bit 5 position. */ -+#define XCL_PERH6_bm (1<<6) /* TC16 High Byte Period bit 6 mask. */ -+#define XCL_PERH6_bp 6 /* TC16 High Byte Period bit 6 position. */ -+#define XCL_PERH7_bm (1<<7) /* TC16 High Byte Period bit 7 mask. */ -+#define XCL_PERH7_bp 7 /* TC16 High Byte Period bit 7 position. */ -+ -+#define XCL_CAPTH_gm 0xFF /* TC16 Capture Value High Byte group mask. */ -+#define XCL_CAPTH_gp 0 /* TC16 Capture Value High Byte group position. */ -+#define XCL_CAPTH0_bm (1<<0) /* TC16 Capture Value High Byte bit 0 mask. */ -+#define XCL_CAPTH0_bp 0 /* TC16 Capture Value High Byte bit 0 position. */ -+#define XCL_CAPTH1_bm (1<<1) /* TC16 Capture Value High Byte bit 1 mask. */ -+#define XCL_CAPTH1_bp 1 /* TC16 Capture Value High Byte bit 1 position. */ -+#define XCL_CAPTH2_bm (1<<2) /* TC16 Capture Value High Byte bit 2 mask. */ -+#define XCL_CAPTH2_bp 2 /* TC16 Capture Value High Byte bit 2 position. */ -+#define XCL_CAPTH3_bm (1<<3) /* TC16 Capture Value High Byte bit 3 mask. */ -+#define XCL_CAPTH3_bp 3 /* TC16 Capture Value High Byte bit 3 position. */ -+#define XCL_CAPTH4_bm (1<<4) /* TC16 Capture Value High Byte bit 4 mask. */ -+#define XCL_CAPTH4_bp 4 /* TC16 Capture Value High Byte bit 4 position. */ -+#define XCL_CAPTH5_bm (1<<5) /* TC16 Capture Value High Byte bit 5 mask. */ -+#define XCL_CAPTH5_bp 5 /* TC16 Capture Value High Byte bit 5 position. */ -+#define XCL_CAPTH6_bm (1<<6) /* TC16 Capture Value High Byte bit 6 mask. */ -+#define XCL_CAPTH6_bp 6 /* TC16 Capture Value High Byte bit 6 position. */ -+#define XCL_CAPTH7_bm (1<<7) /* TC16 Capture Value High Byte bit 7 mask. */ -+#define XCL_CAPTH7_bp 7 /* TC16 Capture Value High Byte bit 7 position. */ -+ -+#define XCL_BPER1_gm 0xFF /* BTC1 Period group mask. */ -+#define XCL_BPER1_gp 0 /* BTC1 Period group position. */ -+#define XCL_BPER10_bm (1<<0) /* BTC1 Period bit 0 mask. */ -+#define XCL_BPER10_bp 0 /* BTC1 Period bit 0 position. */ -+#define XCL_BPER11_bm (1<<1) /* BTC1 Period bit 1 mask. */ -+#define XCL_BPER11_bp 1 /* BTC1 Period bit 1 position. */ -+#define XCL_BPER12_bm (1<<2) /* BTC1 Period bit 2 mask. */ -+#define XCL_BPER12_bp 2 /* BTC1 Period bit 2 position. */ -+#define XCL_BPER13_bm (1<<3) /* BTC1 Period bit 3 mask. */ -+#define XCL_BPER13_bp 3 /* BTC1 Period bit 3 position. */ -+#define XCL_BPER14_bm (1<<4) /* BTC1 Period bit 4 mask. */ -+#define XCL_BPER14_bp 4 /* BTC1 Period bit 4 position. */ -+#define XCL_BPER15_bm (1<<5) /* BTC1 Period bit 5 mask. */ -+#define XCL_BPER15_bp 5 /* BTC1 Period bit 5 position. */ -+#define XCL_BPER16_bm (1<<6) /* BTC1 Period bit 6 mask. */ -+#define XCL_BPER16_bp 6 /* BTC1 Period bit 6 position. */ -+#define XCL_BPER17_bm (1<<7) /* BTC1 Period bit 7 mask. */ -+#define XCL_BPER17_bp 7 /* BTC1 Period bit 7 position. */ -+ -+#define XCL_BCAPT1_gm 0xFF /* BTC1 Capture Value Byte group mask. */ -+#define XCL_BCAPT1_gp 0 /* BTC1 Capture Value Byte group position. */ -+#define XCL_BCAPT10_bm (1<<0) /* BTC1 Capture Value Byte bit 0 mask. */ -+#define XCL_BCAPT10_bp 0 /* BTC1 Capture Value Byte bit 0 position. */ -+#define XCL_BCAPT11_bm (1<<1) /* BTC1 Capture Value Byte bit 1 mask. */ -+#define XCL_BCAPT11_bp 1 /* BTC1 Capture Value Byte bit 1 position. */ -+#define XCL_BCAPT12_bm (1<<2) /* BTC1 Capture Value Byte bit 2 mask. */ -+#define XCL_BCAPT12_bp 2 /* BTC1 Capture Value Byte bit 2 position. */ -+#define XCL_BCAPT13_bm (1<<3) /* BTC1 Capture Value Byte bit 3 mask. */ -+#define XCL_BCAPT13_bp 3 /* BTC1 Capture Value Byte bit 3 position. */ -+#define XCL_BCAPT14_bm (1<<4) /* BTC1 Capture Value Byte bit 4 mask. */ -+#define XCL_BCAPT14_bp 4 /* BTC1 Capture Value Byte bit 4 position. */ -+#define XCL_BCAPT15_bm (1<<5) /* BTC1 Capture Value Byte bit 5 mask. */ -+#define XCL_BCAPT15_bp 5 /* BTC1 Capture Value Byte bit 5 position. */ -+#define XCL_BCAPT16_bm (1<<6) /* BTC1 Capture Value Byte bit 6 mask. */ -+#define XCL_BCAPT16_bp 6 /* BTC1 Capture Value Byte bit 6 position. */ -+#define XCL_BCAPT17_bm (1<<7) /* BTC1 Capture Value Byte bit 7 mask. */ -+#define XCL_BCAPT17_bp 7 /* BTC1 Capture Value Byte bit 7 position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_BRIDGEEN_bm 0x80 /* Bridge Enable bit mask. */ -+#define TWI_BRIDGEEN_bp 7 /* Bridge Enable bit position. */ -+ -+#define TWI_SFMPEN_bm 0x40 /* Slave Fast Mode Plus Enable bit mask. */ -+#define TWI_SFMPEN_bp 6 /* Slave Fast Mode Plus Enable bit position. */ -+ -+#define TWI_SSDAHOLD_gm 0x30 /* Slave SDA Hold Time Enable group mask. */ -+#define TWI_SSDAHOLD_gp 4 /* Slave SDA Hold Time Enable group position. */ -+#define TWI_SSDAHOLD0_bm (1<<4) /* Slave SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SSDAHOLD0_bp 4 /* Slave SDA Hold Time Enable bit 0 position. */ -+#define TWI_SSDAHOLD1_bm (1<<5) /* Slave SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SSDAHOLD1_bp 5 /* Slave SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_FMPEN_bm 0x08 /* FMPLUS Enable bit mask. */ -+#define TWI_FMPEN_bp 3 /* FMPLUS Enable bit position. */ -+ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+#define TWI_MASTER_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ -+#define TWI_MASTER_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ -+ -+#define TWI_MASTER_TSEXTEN_bm 0x20 /* Slave Extend Timeout Enable bit mask. */ -+#define TWI_MASTER_TSEXTEN_bp 5 /* Slave Extend Timeout Enable bit position. */ -+ -+#define TWI_MASTER_TMEXTEN_bm 0x40 /* Master Extend Timeout Enable bit mask. */ -+#define TWI_MASTER_TMEXTEN_bp 6 /* Master Extend Timeout Enable bit position. */ -+ -+#define TWI_MASTER_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ -+#define TWI_MASTER_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+#define TWI_SLAVE_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ -+#define TWI_SLAVE_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ -+ -+#define TWI_SLAVE_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ -+#define TWI_SLAVE_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI_TIMEOUT.TOS bit masks and bit positions */ -+#define TWI_TIMEOUT_TTOUTMIF_bm 0x01 /* Master Ttimeout Interrupt Flag bit mask. */ -+#define TWI_TIMEOUT_TTOUTMIF_bp 0 /* Master Ttimeout Interrupt Flag bit position. */ -+ -+#define TWI_TIMEOUT_TSEXTIF_bm 0x02 /* Slave Extend Interrupt Flag bit mask. */ -+#define TWI_TIMEOUT_TSEXTIF_bp 1 /* Slave Extend Interrupt Flag bit position. */ -+ -+#define TWI_TIMEOUT_TMEXTIF_bm 0x04 /* Master Extend Interrupt Flag bit mask. */ -+#define TWI_TIMEOUT_TMEXTIF_bp 2 /* Master Extend Interrupt Flag bit position. */ -+ -+#define TWI_TIMEOUT_TTOUTSIF_bm 0x10 /* Slave Ttimeout Interrupt Flag bit mask. */ -+#define TWI_TIMEOUT_TTOUTSIF_bp 4 /* Slave Ttimeout Interrupt Flag bit position. */ -+ -+/* TWI_TIMEOUT.TOCONF bit masks and bit positions */ -+#define TWI_TIMEOUT_TTOUTMSEL_gm 0x07 /* Master Ttimeout Select group mask. */ -+#define TWI_TIMEOUT_TTOUTMSEL_gp 0 /* Master Ttimeout Select group position. */ -+#define TWI_TIMEOUT_TTOUTMSEL0_bm (1<<0) /* Master Ttimeout Select bit 0 mask. */ -+#define TWI_TIMEOUT_TTOUTMSEL0_bp 0 /* Master Ttimeout Select bit 0 position. */ -+#define TWI_TIMEOUT_TTOUTMSEL1_bm (1<<1) /* Master Ttimeout Select bit 1 mask. */ -+#define TWI_TIMEOUT_TTOUTMSEL1_bp 1 /* Master Ttimeout Select bit 1 position. */ -+#define TWI_TIMEOUT_TTOUTMSEL2_bm (1<<2) /* Master Ttimeout Select bit 2 mask. */ -+#define TWI_TIMEOUT_TTOUTMSEL2_bp 2 /* Master Ttimeout Select bit 2 position. */ -+ -+#define TWI_TIMEOUT_TMSEXTSEL_gm 0x18 /* Master/Slave Timeout Select group mask. */ -+#define TWI_TIMEOUT_TMSEXTSEL_gp 3 /* Master/Slave Timeout Select group position. */ -+#define TWI_TIMEOUT_TMSEXTSEL0_bm (1<<3) /* Master/Slave Timeout Select bit 0 mask. */ -+#define TWI_TIMEOUT_TMSEXTSEL0_bp 3 /* Master/Slave Timeout Select bit 0 position. */ -+#define TWI_TIMEOUT_TMSEXTSEL1_bm (1<<4) /* Master/Slave Timeout Select bit 1 mask. */ -+#define TWI_TIMEOUT_TMSEXTSEL1_bp 4 /* Master/Slave Timeout Select bit 1 position. */ -+ -+#define TWI_TIMEOUT_TTOUTSSEL_gm 0xE0 /* Slave Ttimeout Select group mask. */ -+#define TWI_TIMEOUT_TTOUTSSEL_gp 5 /* Slave Ttimeout Select group position. */ -+#define TWI_TIMEOUT_TTOUTSSEL0_bm (1<<5) /* Slave Ttimeout Select bit 0 mask. */ -+#define TWI_TIMEOUT_TTOUTSSEL0_bp 5 /* Slave Ttimeout Select bit 0 position. */ -+#define TWI_TIMEOUT_TTOUTSSEL1_bm (1<<6) /* Slave Ttimeout Select bit 1 mask. */ -+#define TWI_TIMEOUT_TTOUTSSEL1_bp 6 /* Slave Ttimeout Select bit 1 position. */ -+#define TWI_TIMEOUT_TTOUTSSEL2_bm (1<<7) /* Slave Ttimeout Select bit 2 mask. */ -+#define TWI_TIMEOUT_TTOUTSSEL2_bp 7 /* Slave Ttimeout Select bit 2 position. */ -+ -+/* PORT - Port Configuration */ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INTLVL_gm 0x03 /* Port Interrupt Level group mask. */ -+#define PORT_INTLVL_gp 0 /* Port Interrupt Level group position. */ -+#define PORT_INTLVL0_bm (1<<0) /* Port Interrupt Level bit 0 mask. */ -+#define PORT_INTLVL0_bp 0 /* Port Interrupt Level bit 0 position. */ -+#define PORT_INTLVL1_bm (1<<1) /* Port Interrupt Level bit 1 mask. */ -+#define PORT_INTLVL1_bp 1 /* Port Interrupt Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT7IF_bm 0x80 /* Pin 7 Interrupt Flag bit mask. */ -+#define PORT_INT7IF_bp 7 /* Pin 7 Interrupt Flag bit position. */ -+ -+#define PORT_INT6IF_bm 0x40 /* Pin 6 Interrupt Flag bit mask. */ -+#define PORT_INT6IF_bp 6 /* Pin 6 Interrupt Flag bit position. */ -+ -+#define PORT_INT5IF_bm 0x20 /* Pin 5 Interrupt Flag bit mask. */ -+#define PORT_INT5IF_bp 5 /* Pin 5 Interrupt Flag bit position. */ -+ -+#define PORT_INT4IF_bm 0x10 /* Pin 4 Interrupt Flag bit mask. */ -+#define PORT_INT4IF_bp 4 /* Pin 4 Interrupt Flag bit position. */ -+ -+#define PORT_INT3IF_bm 0x08 /* Pin 3 Interrupt Flag bit mask. */ -+#define PORT_INT3IF_bp 3 /* Pin 3 Interrupt Flag bit position. */ -+ -+#define PORT_INT2IF_bm 0x04 /* Pin 2 Interrupt Flag bit mask. */ -+#define PORT_INT2IF_bp 2 /* Pin 2 Interrupt Flag bit position. */ -+ -+#define PORT_INT1IF_bm 0x02 /* Pin 1 Interrupt Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Pin 1 Interrupt Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Pin 0 Interrupt Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Pin 0 Interrupt Flag bit position. */ -+ -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_USART0_bm 0x10 /* Usart0 bit mask. */ -+#define PORT_USART0_bp 4 /* Usart0 bit position. */ -+ -+#define PORT_TC4D_bm 0x08 /* Timer/Counter 4 Output Compare D bit mask. */ -+#define PORT_TC4D_bp 3 /* Timer/Counter 4 Output Compare D bit position. */ -+ -+#define PORT_TC4C_bm 0x04 /* Timer/Counter 4 Output Compare C bit mask. */ -+#define PORT_TC4C_bp 2 /* Timer/Counter 4 Output Compare C bit position. */ -+ -+#define PORT_TC4B_bm 0x02 /* Timer/Counter 4 Output Compare B bit mask. */ -+#define PORT_TC4B_bp 1 /* Timer/Counter 4 Output Compare B bit position. */ -+ -+#define PORT_TC4A_bm 0x01 /* Timer/Counter 4 Output Compare A bit mask. */ -+#define PORT_TC4A_bp 0 /* Timer/Counter 4 Output Compare A bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC4.CTRLA bit masks and bit positions */ -+#define TC4_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ -+#define TC4_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ -+ -+#define TC4_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ -+#define TC4_EVSTART_bp 5 /* Start on Next Event bit position. */ -+ -+#define TC4_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ -+#define TC4_UPSTOP_bp 4 /* Stop on Next Update bit position. */ -+ -+#define TC4_CLKSEL_gm 0x0F /* Clock Select group mask. */ -+#define TC4_CLKSEL_gp 0 /* Clock Select group position. */ -+#define TC4_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ -+#define TC4_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ -+#define TC4_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ -+#define TC4_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ -+#define TC4_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ -+#define TC4_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ -+#define TC4_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ -+#define TC4_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ -+ -+/* TC4.CTRLB bit masks and bit positions */ -+#define TC4_BYTEM_gm 0xC0 /* Byte Mode group mask. */ -+#define TC4_BYTEM_gp 6 /* Byte Mode group position. */ -+#define TC4_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ -+#define TC4_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ -+#define TC4_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ -+#define TC4_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ -+ -+#define TC4_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ -+#define TC4_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ -+#define TC4_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ -+#define TC4_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ -+#define TC4_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ -+#define TC4_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ -+ -+#define TC4_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ -+#define TC4_WGMODE_gp 0 /* Waveform Generation Mode group position. */ -+#define TC4_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ -+#define TC4_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ -+#define TC4_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ -+#define TC4_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ -+#define TC4_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ -+#define TC4_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ -+ -+/* TC4.CTRLC bit masks and bit positions */ -+#define TC4_POLD_bm 0x80 /* Channel D Output Polarity bit mask. */ -+#define TC4_POLD_bp 7 /* Channel D Output Polarity bit position. */ -+ -+#define TC4_POLC_bm 0x40 /* Channel C Output Polarity bit mask. */ -+#define TC4_POLC_bp 6 /* Channel C Output Polarity bit position. */ -+ -+#define TC4_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ -+#define TC4_POLB_bp 5 /* Channel B Output Polarity bit position. */ -+ -+#define TC4_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ -+#define TC4_POLA_bp 4 /* Channel A Output Polarity bit position. */ -+ -+#define TC4_CMPD_bm 0x08 /* Channel D Compare Output Value bit mask. */ -+#define TC4_CMPD_bp 3 /* Channel D Compare Output Value bit position. */ -+ -+#define TC4_CMPC_bm 0x04 /* Channel C Compare Output Value bit mask. */ -+#define TC4_CMPC_bp 2 /* Channel C Compare Output Value bit position. */ -+ -+#define TC4_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ -+#define TC4_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ -+ -+#define TC4_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ -+#define TC4_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ -+ -+#define TC4_HCMPD_bm 0x80 /* High Channel D Compare Output Value bit mask. */ -+#define TC4_HCMPD_bp 7 /* High Channel D Compare Output Value bit position. */ -+ -+#define TC4_HCMPC_bm 0x40 /* High Channel C Compare Output Value bit mask. */ -+#define TC4_HCMPC_bp 6 /* High Channel C Compare Output Value bit position. */ -+ -+#define TC4_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ -+#define TC4_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ -+ -+#define TC4_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ -+#define TC4_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ -+ -+#define TC4_LCMPD_bm 0x08 /* Low Channel D Compare Output Value bit mask. */ -+#define TC4_LCMPD_bp 3 /* Low Channel D Compare Output Value bit position. */ -+ -+#define TC4_LCMPC_bm 0x04 /* Low Channel C Compare Output Value bit mask. */ -+#define TC4_LCMPC_bp 2 /* Low Channel C Compare Output Value bit position. */ -+ -+#define TC4_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ -+#define TC4_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ -+ -+#define TC4_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ -+#define TC4_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ -+ -+/* TC4.CTRLD bit masks and bit positions */ -+#define TC4_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC4_EVACT_gp 5 /* Event Action group position. */ -+#define TC4_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC4_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC4_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC4_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC4_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC4_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC4_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC4_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC4_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC4_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC4_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC4_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC4_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC4_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC4_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC4_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC4_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC4_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC4.CTRLE bit masks and bit positions */ -+#define TC4_CCDMODE_gm 0xC0 /* Channel D Compare or Capture Mode group mask. */ -+#define TC4_CCDMODE_gp 6 /* Channel D Compare or Capture Mode group position. */ -+#define TC4_CCDMODE0_bm (1<<6) /* Channel D Compare or Capture Mode bit 0 mask. */ -+#define TC4_CCDMODE0_bp 6 /* Channel D Compare or Capture Mode bit 0 position. */ -+#define TC4_CCDMODE1_bm (1<<7) /* Channel D Compare or Capture Mode bit 1 mask. */ -+#define TC4_CCDMODE1_bp 7 /* Channel D Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_CCCMODE_gm 0x30 /* Channel C Compare or Capture Mode group mask. */ -+#define TC4_CCCMODE_gp 4 /* Channel C Compare or Capture Mode group position. */ -+#define TC4_CCCMODE0_bm (1<<4) /* Channel C Compare or Capture Mode bit 0 mask. */ -+#define TC4_CCCMODE0_bp 4 /* Channel C Compare or Capture Mode bit 0 position. */ -+#define TC4_CCCMODE1_bm (1<<5) /* Channel C Compare or Capture Mode bit 1 mask. */ -+#define TC4_CCCMODE1_bp 5 /* Channel C Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ -+#define TC4_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ -+#define TC4_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ -+#define TC4_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ -+#define TC4_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ -+#define TC4_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ -+#define TC4_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ -+#define TC4_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ -+#define TC4_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ -+#define TC4_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ -+#define TC4_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_LCCDMODE_gm 0xC0 /* Channel Low D Compare or Capture Mode group mask. */ -+#define TC4_LCCDMODE_gp 6 /* Channel Low D Compare or Capture Mode group position. */ -+#define TC4_LCCDMODE0_bm (1<<6) /* Channel Low D Compare or Capture Mode bit 0 mask. */ -+#define TC4_LCCDMODE0_bp 6 /* Channel Low D Compare or Capture Mode bit 0 position. */ -+#define TC4_LCCDMODE1_bm (1<<7) /* Channel Low D Compare or Capture Mode bit 1 mask. */ -+#define TC4_LCCDMODE1_bp 7 /* Channel Low D Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_LCCCMODE_gm 0x30 /* Channel Low C Compare or Capture Mode group mask. */ -+#define TC4_LCCCMODE_gp 4 /* Channel Low C Compare or Capture Mode group position. */ -+#define TC4_LCCCMODE0_bm (1<<4) /* Channel Low C Compare or Capture Mode bit 0 mask. */ -+#define TC4_LCCCMODE0_bp 4 /* Channel Low C Compare or Capture Mode bit 0 position. */ -+#define TC4_LCCCMODE1_bm (1<<5) /* Channel Low C Compare or Capture Mode bit 1 mask. */ -+#define TC4_LCCCMODE1_bp 5 /* Channel Low C Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ -+#define TC4_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ -+#define TC4_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ -+#define TC4_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ -+#define TC4_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ -+#define TC4_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ -+#define TC4_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ -+#define TC4_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ -+#define TC4_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ -+#define TC4_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ -+#define TC4_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ -+ -+/* TC4.CTRLF bit masks and bit positions */ -+#define TC4_HCCDMODE_gm 0xC0 /* Channel High D Compare or Capture Mode group mask. */ -+#define TC4_HCCDMODE_gp 6 /* Channel High D Compare or Capture Mode group position. */ -+#define TC4_HCCDMODE0_bm (1<<6) /* Channel High D Compare or Capture Mode bit 0 mask. */ -+#define TC4_HCCDMODE0_bp 6 /* Channel High D Compare or Capture Mode bit 0 position. */ -+#define TC4_HCCDMODE1_bm (1<<7) /* Channel High D Compare or Capture Mode bit 1 mask. */ -+#define TC4_HCCDMODE1_bp 7 /* Channel High D Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_HCCCMODE_gm 0x30 /* Channel High C Compare or Capture Mode group mask. */ -+#define TC4_HCCCMODE_gp 4 /* Channel High C Compare or Capture Mode group position. */ -+#define TC4_HCCCMODE0_bm (1<<4) /* Channel High C Compare or Capture Mode bit 0 mask. */ -+#define TC4_HCCCMODE0_bp 4 /* Channel High C Compare or Capture Mode bit 0 position. */ -+#define TC4_HCCCMODE1_bm (1<<5) /* Channel High C Compare or Capture Mode bit 1 mask. */ -+#define TC4_HCCCMODE1_bp 5 /* Channel High C Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ -+#define TC4_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ -+#define TC4_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ -+#define TC4_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ -+#define TC4_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ -+#define TC4_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ -+#define TC4_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ -+#define TC4_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ -+#define TC4_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ -+#define TC4_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ -+#define TC4_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ -+ -+/* TC4.INTCTRLA bit masks and bit positions */ -+#define TC4_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ -+#define TC4_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ -+#define TC4_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ -+#define TC4_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ -+#define TC4_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ -+#define TC4_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ -+ -+#define TC4_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ -+#define TC4_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ -+#define TC4_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ -+#define TC4_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ -+#define TC4_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ -+#define TC4_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ -+ -+#define TC4_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ -+#define TC4_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ -+#define TC4_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ -+#define TC4_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ -+#define TC4_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ -+#define TC4_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ -+ -+/* TC4.INTCTRLB bit masks and bit positions */ -+#define TC4_CCDINTLVL_gm 0xC0 /* Channel D Compare or Capture Interrupt Level group mask. */ -+#define TC4_CCDINTLVL_gp 6 /* Channel D Compare or Capture Interrupt Level group position. */ -+#define TC4_CCDINTLVL0_bm (1<<6) /* Channel D Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC4_CCDINTLVL0_bp 6 /* Channel D Compare or Capture Interrupt Level bit 0 position. */ -+#define TC4_CCDINTLVL1_bm (1<<7) /* Channel D Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC4_CCDINTLVL1_bp 7 /* Channel D Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC4_CCCINTLVL_gm 0x30 /* Channel C Compare or Capture Interrupt Level group mask. */ -+#define TC4_CCCINTLVL_gp 4 /* Channel C Compare or Capture Interrupt Level group position. */ -+#define TC4_CCCINTLVL0_bm (1<<4) /* Channel C Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC4_CCCINTLVL0_bp 4 /* Channel C Compare or Capture Interrupt Level bit 0 position. */ -+#define TC4_CCCINTLVL1_bm (1<<5) /* Channel C Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC4_CCCINTLVL1_bp 5 /* Channel C Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC4_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ -+#define TC4_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ -+#define TC4_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC4_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ -+#define TC4_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC4_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC4_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ -+#define TC4_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ -+#define TC4_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC4_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ -+#define TC4_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC4_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC4_LCCDINTLVL_gm 0xC0 /* Channel Low D Compare or Capture Interrupt Level group mask. */ -+#define TC4_LCCDINTLVL_gp 6 /* Channel Low D Compare or Capture Interrupt Level group position. */ -+#define TC4_LCCDINTLVL0_bm (1<<6) /* Channel Low D Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC4_LCCDINTLVL0_bp 6 /* Channel Low D Compare or Capture Interrupt Level bit 0 position. */ -+#define TC4_LCCDINTLVL1_bm (1<<7) /* Channel Low D Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC4_LCCDINTLVL1_bp 7 /* Channel Low D Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC4_LCCCINTLVL_gm 0x30 /* Channel Low C Compare or Capture Interrupt Level group mask. */ -+#define TC4_LCCCINTLVL_gp 4 /* Channel Low C Compare or Capture Interrupt Level group position. */ -+#define TC4_LCCCINTLVL0_bm (1<<4) /* Channel Low C Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC4_LCCCINTLVL0_bp 4 /* Channel Low C Compare or Capture Interrupt Level bit 0 position. */ -+#define TC4_LCCCINTLVL1_bm (1<<5) /* Channel Low C Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC4_LCCCINTLVL1_bp 5 /* Channel Low C Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC4_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ -+#define TC4_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ -+#define TC4_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC4_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ -+#define TC4_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC4_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC4_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ -+#define TC4_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ -+#define TC4_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC4_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ -+#define TC4_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC4_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ -+ -+/* TC4.CTRLGCLR bit masks and bit positions */ -+#define TC4_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ -+#define TC4_STOP_bp 5 /* Timer/Counter Stop bit position. */ -+ -+#define TC4_CMD_gm 0x0C /* Command group mask. */ -+#define TC4_CMD_gp 2 /* Command group position. */ -+#define TC4_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC4_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC4_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC4_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC4_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC4_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC4_DIR_bm 0x01 /* Counter Direction bit mask. */ -+#define TC4_DIR_bp 0 /* Counter Direction bit position. */ -+ -+/* TC4.CTRLGSET bit masks and bit positions */ -+/* TC4_STOP Predefined. */ -+/* TC4_STOP Predefined. */ -+ -+/* TC4_CMD Predefined. */ -+/* TC4_CMD Predefined. */ -+ -+/* TC4_LUPD Predefined. */ -+/* TC4_LUPD Predefined. */ -+ -+/* TC4_DIR Predefined. */ -+/* TC4_DIR Predefined. */ -+ -+/* TC4.CTRLHCLR bit masks and bit positions */ -+#define TC4_CCDBV_bm 0x10 /* Channel D Compare or Capture Buffer Valid bit mask. */ -+#define TC4_CCDBV_bp 4 /* Channel D Compare or Capture Buffer Valid bit position. */ -+ -+#define TC4_CCCBV_bm 0x08 /* Channel C Compare or Capture Buffer Valid bit mask. */ -+#define TC4_CCCBV_bp 3 /* Channel C Compare or Capture Buffer Valid bit position. */ -+ -+#define TC4_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ -+#define TC4_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ -+ -+#define TC4_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ -+#define TC4_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ -+ -+#define TC4_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC4_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+#define TC4_LCCDBV_bm 0x10 /* Channel Low D Compare or Capture Buffer Valid bit mask. */ -+#define TC4_LCCDBV_bp 4 /* Channel Low D Compare or Capture Buffer Valid bit position. */ -+ -+#define TC4_LCCCBV_bm 0x08 /* Channel Low C Compare or Capture Buffer Valid bit mask. */ -+#define TC4_LCCCBV_bp 3 /* Channel Low C Compare or Capture Buffer Valid bit position. */ -+ -+#define TC4_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ -+#define TC4_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ -+ -+#define TC4_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ -+#define TC4_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ -+ -+#define TC4_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ -+#define TC4_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ -+ -+/* TC4.CTRLHSET bit masks and bit positions */ -+/* TC4_CCDBV Predefined. */ -+/* TC4_CCDBV Predefined. */ -+ -+/* TC4_CCCBV Predefined. */ -+/* TC4_CCCBV Predefined. */ -+ -+/* TC4_CCBBV Predefined. */ -+/* TC4_CCBBV Predefined. */ -+ -+/* TC4_CCABV Predefined. */ -+/* TC4_CCABV Predefined. */ -+ -+/* TC4_PERBV Predefined. */ -+/* TC4_PERBV Predefined. */ -+ -+/* TC4_LCCDBV Predefined. */ -+/* TC4_LCCDBV Predefined. */ -+ -+/* TC4_LCCCBV Predefined. */ -+/* TC4_LCCCBV Predefined. */ -+ -+/* TC4_LCCBBV Predefined. */ -+/* TC4_LCCBBV Predefined. */ -+ -+/* TC4_LCCABV Predefined. */ -+/* TC4_LCCABV Predefined. */ -+ -+/* TC4_LPERBV Predefined. */ -+/* TC4_LPERBV Predefined. */ -+ -+/* TC4.INTFLAGS bit masks and bit positions */ -+#define TC4_CCDIF_bm 0x80 /* Channel D Compare or Capture Interrupt Flag bit mask. */ -+#define TC4_CCDIF_bp 7 /* Channel D Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC4_CCCIF_bm 0x40 /* Channel C Compare or Capture Interrupt Flag bit mask. */ -+#define TC4_CCCIF_bp 6 /* Channel C Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC4_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ -+#define TC4_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC4_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ -+#define TC4_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC4_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ -+#define TC4_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ -+ -+#define TC4_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC4_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC4_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ -+#define TC4_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ -+ -+#define TC4_LCCDIF_bm 0x80 /* Channel Low D Compare or Capture Interrupt Flag bit mask. */ -+#define TC4_LCCDIF_bp 7 /* Channel Low D Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC4_LCCCIF_bm 0x40 /* Channel Low C Compare or Capture Interrupt Flag bit mask. */ -+#define TC4_LCCCIF_bp 6 /* Channel Low C Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC4_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ -+#define TC4_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC4_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ -+#define TC4_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ -+ -+/* TC5.CTRLA bit masks and bit positions */ -+#define TC5_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ -+#define TC5_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ -+ -+#define TC5_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ -+#define TC5_EVSTART_bp 5 /* Start on Next Event bit position. */ -+ -+#define TC5_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ -+#define TC5_UPSTOP_bp 4 /* Stop on Next Update bit position. */ -+ -+#define TC5_CLKSEL_gm 0x0F /* Clock Select group mask. */ -+#define TC5_CLKSEL_gp 0 /* Clock Select group position. */ -+#define TC5_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ -+#define TC5_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ -+#define TC5_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ -+#define TC5_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ -+#define TC5_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ -+#define TC5_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ -+#define TC5_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ -+#define TC5_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ -+ -+/* TC5.CTRLB bit masks and bit positions */ -+#define TC5_BYTEM_gm 0xC0 /* Byte Mode group mask. */ -+#define TC5_BYTEM_gp 6 /* Byte Mode group position. */ -+#define TC5_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ -+#define TC5_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ -+#define TC5_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ -+#define TC5_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ -+ -+#define TC5_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ -+#define TC5_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ -+#define TC5_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ -+#define TC5_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ -+#define TC5_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ -+#define TC5_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ -+ -+#define TC5_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ -+#define TC5_WGMODE_gp 0 /* Waveform Generation Mode group position. */ -+#define TC5_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ -+#define TC5_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ -+#define TC5_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ -+#define TC5_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ -+#define TC5_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ -+#define TC5_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ -+ -+/* TC5.CTRLC bit masks and bit positions */ -+#define TC5_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ -+#define TC5_POLB_bp 5 /* Channel B Output Polarity bit position. */ -+ -+#define TC5_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ -+#define TC5_POLA_bp 4 /* Channel A Output Polarity bit position. */ -+ -+#define TC5_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ -+#define TC5_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ -+ -+#define TC5_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ -+#define TC5_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ -+ -+#define TC5_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ -+#define TC5_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ -+ -+#define TC5_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ -+#define TC5_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ -+ -+#define TC5_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ -+#define TC5_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ -+ -+#define TC5_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ -+#define TC5_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ -+ -+/* TC5.CTRLD bit masks and bit positions */ -+#define TC5_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC5_EVACT_gp 5 /* Event Action group position. */ -+#define TC5_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC5_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC5_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC5_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC5_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC5_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC5_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC5_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC5_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC5_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC5_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC5_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC5_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC5_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC5_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC5_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC5_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC5_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC5.CTRLE bit masks and bit positions */ -+#define TC5_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ -+#define TC5_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ -+#define TC5_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ -+#define TC5_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ -+#define TC5_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ -+#define TC5_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ -+ -+#define TC5_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ -+#define TC5_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ -+#define TC5_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ -+#define TC5_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ -+#define TC5_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ -+#define TC5_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ -+ -+#define TC5_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ -+#define TC5_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ -+#define TC5_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ -+#define TC5_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ -+#define TC5_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ -+#define TC5_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ -+ -+#define TC5_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ -+#define TC5_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ -+#define TC5_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ -+#define TC5_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ -+#define TC5_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ -+#define TC5_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ -+ -+/* TC5.CTRLF bit masks and bit positions */ -+#define TC5_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ -+#define TC5_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ -+#define TC5_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ -+#define TC5_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ -+#define TC5_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ -+#define TC5_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ -+ -+#define TC5_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ -+#define TC5_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ -+#define TC5_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ -+#define TC5_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ -+#define TC5_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ -+#define TC5_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ -+ -+/* TC5.INTCTRLA bit masks and bit positions */ -+#define TC5_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ -+#define TC5_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ -+#define TC5_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ -+#define TC5_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ -+#define TC5_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ -+#define TC5_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ -+ -+#define TC5_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ -+#define TC5_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ -+#define TC5_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ -+#define TC5_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ -+#define TC5_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ -+#define TC5_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ -+ -+#define TC5_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ -+#define TC5_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ -+#define TC5_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ -+#define TC5_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ -+#define TC5_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ -+#define TC5_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ -+ -+/* TC5.INTCTRLB bit masks and bit positions */ -+#define TC5_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ -+#define TC5_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ -+#define TC5_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC5_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ -+#define TC5_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC5_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC5_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ -+#define TC5_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ -+#define TC5_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC5_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ -+#define TC5_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC5_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC5_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ -+#define TC5_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ -+#define TC5_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC5_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ -+#define TC5_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC5_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC5_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ -+#define TC5_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ -+#define TC5_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC5_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ -+#define TC5_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC5_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ -+ -+/* TC5.CTRLGCLR bit masks and bit positions */ -+#define TC5_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ -+#define TC5_STOP_bp 5 /* Timer/Counter Stop bit position. */ -+ -+#define TC5_CMD_gm 0x0C /* Command group mask. */ -+#define TC5_CMD_gp 2 /* Command group position. */ -+#define TC5_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC5_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC5_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC5_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC5_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC5_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC5_DIR_bm 0x01 /* Counter Direction bit mask. */ -+#define TC5_DIR_bp 0 /* Counter Direction bit position. */ -+ -+/* TC5.CTRLGSET bit masks and bit positions */ -+/* TC5_STOP Predefined. */ -+/* TC5_STOP Predefined. */ -+ -+/* TC5_CMD Predefined. */ -+/* TC5_CMD Predefined. */ -+ -+/* TC5_LUPD Predefined. */ -+/* TC5_LUPD Predefined. */ -+ -+/* TC5_DIR Predefined. */ -+/* TC5_DIR Predefined. */ -+ -+/* TC5.CTRLHCLR bit masks and bit positions */ -+#define TC5_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ -+#define TC5_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ -+ -+#define TC5_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ -+#define TC5_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ -+ -+#define TC5_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC5_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+#define TC5_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ -+#define TC5_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ -+ -+#define TC5_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ -+#define TC5_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ -+ -+#define TC5_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ -+#define TC5_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ -+ -+/* TC5.CTRLHSET bit masks and bit positions */ -+/* TC5_CCBBV Predefined. */ -+/* TC5_CCBBV Predefined. */ -+ -+/* TC5_CCABV Predefined. */ -+/* TC5_CCABV Predefined. */ -+ -+/* TC5_PERBV Predefined. */ -+/* TC5_PERBV Predefined. */ -+ -+/* TC5_LCCBBV Predefined. */ -+/* TC5_LCCBBV Predefined. */ -+ -+/* TC5_LCCABV Predefined. */ -+/* TC5_LCCABV Predefined. */ -+ -+/* TC5_LPERBV Predefined. */ -+/* TC5_LPERBV Predefined. */ -+ -+/* TC5.INTFLAGS bit masks and bit positions */ -+#define TC5_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ -+#define TC5_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC5_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ -+#define TC5_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC5_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ -+#define TC5_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ -+ -+#define TC5_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC5_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC5_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ -+#define TC5_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ -+ -+#define TC5_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ -+#define TC5_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC5_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ -+#define TC5_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ -+ -+/* FAULT - Fault Extension */ -+/* FAULT.CTRLA bit masks and bit positions */ -+#define FAULT_RAMP_gm 0xC0 /* Ramp Mode Selection group mask. */ -+#define FAULT_RAMP_gp 6 /* Ramp Mode Selection group position. */ -+#define FAULT_RAMP0_bm (1<<6) /* Ramp Mode Selection bit 0 mask. */ -+#define FAULT_RAMP0_bp 6 /* Ramp Mode Selection bit 0 position. */ -+#define FAULT_RAMP1_bm (1<<7) /* Ramp Mode Selection bit 1 mask. */ -+#define FAULT_RAMP1_bp 7 /* Ramp Mode Selection bit 1 position. */ -+ -+#define FAULT_FDDBD_bm 0x20 /* Fault on Debug Break Detection bit mask. */ -+#define FAULT_FDDBD_bp 5 /* Fault on Debug Break Detection bit position. */ -+ -+#define FAULT_PORTCTRL_bm 0x10 /* Port Control Mode bit mask. */ -+#define FAULT_PORTCTRL_bp 4 /* Port Control Mode bit position. */ -+ -+#define FAULT_FUSE_bm 0x08 /* Fuse State bit mask. */ -+#define FAULT_FUSE_bp 3 /* Fuse State bit position. */ -+ -+#define FAULT_FILTERE_bm 0x04 /* Fault E Digital Filter Selection bit mask. */ -+#define FAULT_FILTERE_bp 2 /* Fault E Digital Filter Selection bit position. */ -+ -+#define FAULT_SRCE_gm 0x03 /* Fault E Input selection group mask. */ -+#define FAULT_SRCE_gp 0 /* Fault E Input selection group position. */ -+#define FAULT_SRCE0_bm (1<<0) /* Fault E Input selection bit 0 mask. */ -+#define FAULT_SRCE0_bp 0 /* Fault E Input selection bit 0 position. */ -+#define FAULT_SRCE1_bm (1<<1) /* Fault E Input selection bit 1 mask. */ -+#define FAULT_SRCE1_bp 1 /* Fault E Input selection bit 1 position. */ -+ -+/* FAULT.CTRLB bit masks and bit positions */ -+#define FAULT_SOFTA_bm 0x80 /* Fault A Software Mode bit mask. */ -+#define FAULT_SOFTA_bp 7 /* Fault A Software Mode bit position. */ -+ -+#define FAULT_HALTA_gm 0x60 /* Fault A Halt Action group mask. */ -+#define FAULT_HALTA_gp 5 /* Fault A Halt Action group position. */ -+#define FAULT_HALTA0_bm (1<<5) /* Fault A Halt Action bit 0 mask. */ -+#define FAULT_HALTA0_bp 5 /* Fault A Halt Action bit 0 position. */ -+#define FAULT_HALTA1_bm (1<<6) /* Fault A Halt Action bit 1 mask. */ -+#define FAULT_HALTA1_bp 6 /* Fault A Halt Action bit 1 position. */ -+ -+#define FAULT_RESTARTA_bm 0x10 /* Fault A Restart Action bit mask. */ -+#define FAULT_RESTARTA_bp 4 /* Fault A Restart Action bit position. */ -+ -+#define FAULT_KEEPA_bm 0x08 /* Fault A Keep Action bit mask. */ -+#define FAULT_KEEPA_bp 3 /* Fault A Keep Action bit position. */ -+ -+#define FAULT_SRCA_gm 0x03 /* Fault A Source Selection group mask. */ -+#define FAULT_SRCA_gp 0 /* Fault A Source Selection group position. */ -+#define FAULT_SRCA0_bm (1<<0) /* Fault A Source Selection bit 0 mask. */ -+#define FAULT_SRCA0_bp 0 /* Fault A Source Selection bit 0 position. */ -+#define FAULT_SRCA1_bm (1<<1) /* Fault A Source Selection bit 1 mask. */ -+#define FAULT_SRCA1_bp 1 /* Fault A Source Selection bit 1 position. */ -+ -+/* FAULT.CTRLC bit masks and bit positions */ -+#define FAULT_CAPTA_bm 0x20 /* Fault A Capture bit mask. */ -+#define FAULT_CAPTA_bp 5 /* Fault A Capture bit position. */ -+ -+#define FAULT_FILTERA_bm 0x04 /* Fault A Digital Filter Selection bit mask. */ -+#define FAULT_FILTERA_bp 2 /* Fault A Digital Filter Selection bit position. */ -+ -+#define FAULT_BLANKA_bm 0x02 /* Fault A Blanking bit mask. */ -+#define FAULT_BLANKA_bp 1 /* Fault A Blanking bit position. */ -+ -+#define FAULT_QUALA_bm 0x01 /* Fault A Qualification bit mask. */ -+#define FAULT_QUALA_bp 0 /* Fault A Qualification bit position. */ -+ -+/* FAULT.CTRLD bit masks and bit positions */ -+#define FAULT_SOFTB_bm 0x80 /* Fault B Software Mode bit mask. */ -+#define FAULT_SOFTB_bp 7 /* Fault B Software Mode bit position. */ -+ -+#define FAULT_HALTB_gm 0x60 /* Fault B Halt Action group mask. */ -+#define FAULT_HALTB_gp 5 /* Fault B Halt Action group position. */ -+#define FAULT_HALTB0_bm (1<<5) /* Fault B Halt Action bit 0 mask. */ -+#define FAULT_HALTB0_bp 5 /* Fault B Halt Action bit 0 position. */ -+#define FAULT_HALTB1_bm (1<<6) /* Fault B Halt Action bit 1 mask. */ -+#define FAULT_HALTB1_bp 6 /* Fault B Halt Action bit 1 position. */ -+ -+#define FAULT_RESTARTB_bm 0x10 /* Fault B Restart Action bit mask. */ -+#define FAULT_RESTARTB_bp 4 /* Fault B Restart Action bit position. */ -+ -+#define FAULT_KEEPB_bm 0x08 /* Fault B Keep Action bit mask. */ -+#define FAULT_KEEPB_bp 3 /* Fault B Keep Action bit position. */ -+ -+#define FAULT_SRCB_gm 0x03 /* Fault B Source Selection group mask. */ -+#define FAULT_SRCB_gp 0 /* Fault B Source Selection group position. */ -+#define FAULT_SRCB0_bm (1<<0) /* Fault B Source Selection bit 0 mask. */ -+#define FAULT_SRCB0_bp 0 /* Fault B Source Selection bit 0 position. */ -+#define FAULT_SRCB1_bm (1<<1) /* Fault B Source Selection bit 1 mask. */ -+#define FAULT_SRCB1_bp 1 /* Fault B Source Selection bit 1 position. */ -+ -+/* FAULT.CTRLE bit masks and bit positions */ -+#define FAULT_CAPTB_bm 0x20 /* Fault B Capture bit mask. */ -+#define FAULT_CAPTB_bp 5 /* Fault B Capture bit position. */ -+ -+#define FAULT_FILTERB_bm 0x04 /* Fault B Digital Filter Selection bit mask. */ -+#define FAULT_FILTERB_bp 2 /* Fault B Digital Filter Selection bit position. */ -+ -+#define FAULT_BLANKB_bm 0x02 /* Fault B Blanking bit mask. */ -+#define FAULT_BLANKB_bp 1 /* Fault B Blanking bit position. */ -+ -+#define FAULT_QUALB_bm 0x01 /* Fault B Qualification bit mask. */ -+#define FAULT_QUALB_bp 0 /* Fault B Qualification bit position. */ -+ -+/* FAULT.STATUS bit masks and bit positions */ -+#define FAULT_STATEB_bm 0x80 /* Fault B State bit mask. */ -+#define FAULT_STATEB_bp 7 /* Fault B State bit position. */ -+ -+#define FAULT_STATEA_bm 0x40 /* Fault A State bit mask. */ -+#define FAULT_STATEA_bp 6 /* Fault A State bit position. */ -+ -+#define FAULT_STATEE_bm 0x20 /* Fault E State bit mask. */ -+#define FAULT_STATEE_bp 5 /* Fault E State bit position. */ -+ -+#define FAULT_IDX_bm 0x08 /* Channel Index Flag bit mask. */ -+#define FAULT_IDX_bp 3 /* Channel Index Flag bit position. */ -+ -+#define FAULT_FAULTBIN_bm 0x04 /* Fault B Flag bit mask. */ -+#define FAULT_FAULTBIN_bp 2 /* Fault B Flag bit position. */ -+ -+#define FAULT_FAULTAIN_bm 0x02 /* Fault A Flag bit mask. */ -+#define FAULT_FAULTAIN_bp 1 /* Fault A Flag bit position. */ -+ -+#define FAULT_FAULTEIN_bm 0x01 /* Fault E Flag bit mask. */ -+#define FAULT_FAULTEIN_bp 0 /* Fault E Flag bit position. */ -+ -+/* FAULT.CTRLGCLR bit masks and bit positions */ -+#define FAULT_HALTBCLR_bm 0x80 /* State B Clear bit mask. */ -+#define FAULT_HALTBCLR_bp 7 /* State B Clear bit position. */ -+ -+#define FAULT_HALTACLR_bm 0x40 /* State A Clear bit mask. */ -+#define FAULT_HALTACLR_bp 6 /* State A Clear bit position. */ -+ -+#define FAULT_STATEECLR_bm 0x20 /* State E Clear bit mask. */ -+#define FAULT_STATEECLR_bp 5 /* State E Clear bit position. */ -+ -+#define FAULT_FAULTB_bm 0x04 /* Fault B Flag bit mask. */ -+#define FAULT_FAULTB_bp 2 /* Fault B Flag bit position. */ -+ -+#define FAULT_FAULTA_bm 0x02 /* Fault A Flag bit mask. */ -+#define FAULT_FAULTA_bp 1 /* Fault A Flag bit position. */ -+ -+#define FAULT_FAULTE_bm 0x01 /* Fault E Flag bit mask. */ -+#define FAULT_FAULTE_bp 0 /* Fault E Flag bit position. */ -+ -+/* FAULT.CTRLGSET bit masks and bit positions */ -+#define FAULT_FAULTBSW_bm 0x80 /* Software Fault B bit mask. */ -+#define FAULT_FAULTBSW_bp 7 /* Software Fault B bit position. */ -+ -+#define FAULT_FAULTASW_bm 0x40 /* Software Fault A bit mask. */ -+#define FAULT_FAULTASW_bp 6 /* Software Fault A bit position. */ -+ -+#define FAULT_FAULTESW_bm 0x20 /* Software Fault E bit mask. */ -+#define FAULT_FAULTESW_bp 5 /* Software Fault E bit position. */ -+ -+#define FAULT_IDXCMD_gm 0x18 /* Channel index Command group mask. */ -+#define FAULT_IDXCMD_gp 3 /* Channel index Command group position. */ -+#define FAULT_IDXCMD0_bm (1<<3) /* Channel index Command bit 0 mask. */ -+#define FAULT_IDXCMD0_bp 3 /* Channel index Command bit 0 position. */ -+#define FAULT_IDXCMD1_bm (1<<4) /* Channel index Command bit 1 mask. */ -+#define FAULT_IDXCMD1_bp 4 /* Channel index Command bit 1 position. */ -+ -+/* WEX - Waveform Extension */ -+/* WEX.CTRL bit masks and bit positions */ -+#define WEX_UPSEL_bm 0x80 /* Update Source Selection bit mask. */ -+#define WEX_UPSEL_bp 7 /* Update Source Selection bit position. */ -+ -+#define WEX_OTMX_gm 0x70 /* Output Matrix group mask. */ -+#define WEX_OTMX_gp 4 /* Output Matrix group position. */ -+#define WEX_OTMX0_bm (1<<4) /* Output Matrix bit 0 mask. */ -+#define WEX_OTMX0_bp 4 /* Output Matrix bit 0 position. */ -+#define WEX_OTMX1_bm (1<<5) /* Output Matrix bit 1 mask. */ -+#define WEX_OTMX1_bp 5 /* Output Matrix bit 1 position. */ -+#define WEX_OTMX2_bm (1<<6) /* Output Matrix bit 2 mask. */ -+#define WEX_OTMX2_bp 6 /* Output Matrix bit 2 position. */ -+ -+#define WEX_DTI3EN_bm 0x08 /* Dead-Time Insertion Generator 3 Enable bit mask. */ -+#define WEX_DTI3EN_bp 3 /* Dead-Time Insertion Generator 3 Enable bit position. */ -+ -+#define WEX_DTI2EN_bm 0x04 /* Dead-Time Insertion Generator 2 Enable bit mask. */ -+#define WEX_DTI2EN_bp 2 /* Dead-Time Insertion Generator 2 Enable bit position. */ -+ -+#define WEX_DTI1EN_bm 0x02 /* Dead-Time Insertion Generator 1 Enable bit mask. */ -+#define WEX_DTI1EN_bp 1 /* Dead-Time Insertion Generator 1 Enable bit position. */ -+ -+#define WEX_DTI0EN_bm 0x01 /* Dead-Time Insertion Generator 0 Enable bit mask. */ -+#define WEX_DTI0EN_bp 0 /* Dead-Time Insertion Generator 0 Enable bit position. */ -+ -+/* WEX.STATUSCLR bit masks and bit positions */ -+#define WEX_SWAPBUF_bm 0x04 /* Swap Buffer Valid bit mask. */ -+#define WEX_SWAPBUF_bp 2 /* Swap Buffer Valid bit position. */ -+ -+#define WEX_PGVBUFV_bm 0x02 /* Pattern Generator Value Buffer Valid bit mask. */ -+#define WEX_PGVBUFV_bp 1 /* Pattern Generator Value Buffer Valid bit position. */ -+ -+#define WEX_PGOBUFV_bm 0x01 /* Pattern Generator Overwrite Buffer Valid bit mask. */ -+#define WEX_PGOBUFV_bp 0 /* Pattern Generator Overwrite Buffer Valid bit position. */ -+ -+/* WEX.STATUSSET bit masks and bit positions */ -+/* WEX_SWAPBUF Predefined. */ -+/* WEX_SWAPBUF Predefined. */ -+ -+/* WEX_PGVBUFV Predefined. */ -+/* WEX_PGVBUFV Predefined. */ -+ -+/* WEX_PGOBUFV Predefined. */ -+/* WEX_PGOBUFV Predefined. */ -+ -+/* WEX.SWAP bit masks and bit positions */ -+#define WEX_SWAP3_bm 0x08 /* Swap DTI output pair 3 bit mask. */ -+#define WEX_SWAP3_bp 3 /* Swap DTI output pair 3 bit position. */ -+ -+#define WEX_SWAP2_bm 0x04 /* Swap DTI output pair 2 bit mask. */ -+#define WEX_SWAP2_bp 2 /* Swap DTI output pair 2 bit position. */ -+ -+#define WEX_SWAP1_bm 0x02 /* Swap DTI output pair 1 bit mask. */ -+#define WEX_SWAP1_bp 1 /* Swap DTI output pair 1 bit position. */ -+ -+#define WEX_SWAP0_bm 0x01 /* Swap DTI output pair 0 bit mask. */ -+#define WEX_SWAP0_bp 0 /* Swap DTI output pair 0 bit position. */ -+ -+/* WEX.SWAPBUF bit masks and bit positions */ -+#define WEX_SWAP3BUF_bm 0x08 /* Swap DTI output pair 3 bit mask. */ -+#define WEX_SWAP3BUF_bp 3 /* Swap DTI output pair 3 bit position. */ -+ -+#define WEX_SWAP2BUF_bm 0x04 /* Swap DTI output pair 2 bit mask. */ -+#define WEX_SWAP2BUF_bp 2 /* Swap DTI output pair 2 bit position. */ -+ -+#define WEX_SWAP1BUF_bm 0x02 /* Swap DTI output pair 1 bit mask. */ -+#define WEX_SWAP1BUF_bp 1 /* Swap DTI output pair 1 bit position. */ -+ -+#define WEX_SWAP0BUF_bm 0x01 /* Swap DTI output pair 0 bit mask. */ -+#define WEX_SWAP0BUF_bp 0 /* Swap DTI output pair 0 bit position. */ -+ -+/* HIRES - High-Resolution Extension */ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HRPLUS_gm 0x0C /* High Resolution Plus group mask. */ -+#define HIRES_HRPLUS_gp 2 /* High Resolution Plus group position. */ -+#define HIRES_HRPLUS0_bm (1<<2) /* High Resolution Plus bit 0 mask. */ -+#define HIRES_HRPLUS0_bp 2 /* High Resolution Plus bit 0 position. */ -+#define HIRES_HRPLUS1_bm (1<<3) /* High Resolution Plus bit 1 mask. */ -+#define HIRES_HRPLUS1_bp 3 /* High Resolution Plus bit 1 position. */ -+ -+#define HIRES_HREN_gm 0x03 /* High Resolution Mode group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Mode group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Mode bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Mode bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Mode bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Mode bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXSIF_bm 0x02 /* Receive Start Bit Interrupt Flag bit mask. */ -+#define USART_RXSIF_bp 1 /* Receive Start Bit Interrupt Flag bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+#define USART_DRIF_bm 0x01 /* Data Reception Flag bit mask. */ -+#define USART_DRIF_bp 0 /* Data Reception Flag bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXSIE_bm 0x80 /* Receive Start Interrupt Enable bit mask. */ -+#define USART_RXSIE_bp 7 /* Receive Start Interrupt Enable bit position. */ -+ -+#define USART_DRIE_bm 0x40 /* Data Reception Interrupt Enable bit mask. */ -+#define USART_DRIE_bp 6 /* Data Reception Interrupt Enable bit position. */ -+ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_ONEWIRE_bm 0x80 /* One Wire Mode bit mask. */ -+#define USART_ONEWIRE_bp 7 /* One Wire Mode bit position. */ -+ -+#define USART_SFDEN_bm 0x40 /* Start Frame Detection Enable bit mask. */ -+#define USART_SFDEN_bp 6 /* Start Frame Detection Enable bit position. */ -+ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+/* USART.CTRLD bit masks and bit positions */ -+#define USART_DECTYPE_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_DECTYPE_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_DECTYPE0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_DECTYPE0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_DECTYPE1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_DECTYPE1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_LUTACT_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_LUTACT_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_LUTACT0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_LUTACT0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_LUTACT1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_LUTACT1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_PECACT_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_PECACT_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_PECACT0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_PECACT0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_PECACT1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_PECACT1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable SPI Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable SPI Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ -+#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit position. */ -+ -+#define SPI_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ -+#define SPI_TXCIE_bp 6 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit position. */ -+ -+#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit mask. */ -+#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit position. */ -+ -+#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit mask. */ -+#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit position. */ -+ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag (In Standard Mode Only). bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag (In Standard Mode Only). bit position. */ -+ -+#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ -+#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision Flag (In Standard Mode Only). bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision Flag (In Standard Mode Only). bit position. */ -+ -+#define SPI_TXCIF_bm 0x40 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ -+#define SPI_TXCIF_bp 6 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit position. */ -+ -+#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit mask. */ -+#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit position. */ -+ -+#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit mask. */ -+#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit position. */ -+ -+#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow (In Buffer Modes Only). bit mask. */ -+#define SPI_BUFOVF_bp 0 /* Buffer Overflow (In Buffer Modes Only). bit position. */ -+ -+/* SPI.CTRLB bit masks and bit positions */ -+#define SPI_BUFMODE_gm 0xC0 /* Buffer Modes group mask. */ -+#define SPI_BUFMODE_gp 6 /* Buffer Modes group position. */ -+#define SPI_BUFMODE0_bm (1<<6) /* Buffer Modes bit 0 mask. */ -+#define SPI_BUFMODE0_bp 6 /* Buffer Modes bit 0 position. */ -+#define SPI_BUFMODE1_bm (1<<7) /* Buffer Modes bit 1 mask. */ -+#define SPI_BUFMODE1_bp 7 /* Buffer Modes bit 1 position. */ -+ -+#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ -+#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* NVM_FUSES.FUSEBYTE6 bit masks and bit positions */ -+#define NVM_FUSES_FDACT5_bm 0x80 /* Fault Dectection Action on TC5 bit mask. */ -+#define NVM_FUSES_FDACT5_bp 7 /* Fault Dectection Action on TC5 bit position. */ -+ -+#define NVM_FUSES_FDACT4_bm 0x40 /* Fault Dectection Action on TC4 bit mask. */ -+#define NVM_FUSES_FDACT4_bp 6 /* Fault Dectection Action on TC4 bit position. */ -+ -+#define NVM_FUSES_VALUE_gm 0x3F /* Port Pin Value group mask. */ -+#define NVM_FUSES_VALUE_gp 0 /* Port Pin Value group position. */ -+#define NVM_FUSES_VALUE0_bm (1<<0) /* Port Pin Value bit 0 mask. */ -+#define NVM_FUSES_VALUE0_bp 0 /* Port Pin Value bit 0 position. */ -+#define NVM_FUSES_VALUE1_bm (1<<1) /* Port Pin Value bit 1 mask. */ -+#define NVM_FUSES_VALUE1_bp 1 /* Port Pin Value bit 1 position. */ -+#define NVM_FUSES_VALUE2_bm (1<<2) /* Port Pin Value bit 2 mask. */ -+#define NVM_FUSES_VALUE2_bp 2 /* Port Pin Value bit 2 position. */ -+#define NVM_FUSES_VALUE3_bm (1<<3) /* Port Pin Value bit 3 mask. */ -+#define NVM_FUSES_VALUE3_bp 3 /* Port Pin Value bit 3 position. */ -+#define NVM_FUSES_VALUE4_bm (1<<4) /* Port Pin Value bit 4 mask. */ -+#define NVM_FUSES_VALUE4_bp 4 /* Port Pin Value bit 4 position. */ -+#define NVM_FUSES_VALUE5_bm (1<<5) /* Port Pin Value bit 5 mask. */ -+#define NVM_FUSES_VALUE5_bp 5 /* Port Pin Value bit 5 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT_vect_num 2 -+#define PORTR_INT_vect _VECTOR(2) /* External Interrupt */ -+ -+/* EDMA interrupt vectors */ -+#define EDMA_CH0_vect_num 3 -+#define EDMA_CH0_vect _VECTOR(3) /* EDMA Channel 0 Interrupt */ -+#define EDMA_CH1_vect_num 4 -+#define EDMA_CH1_vect _VECTOR(4) /* EDMA Channel 1 Interrupt */ -+#define EDMA_CH2_vect_num 5 -+#define EDMA_CH2_vect _VECTOR(5) /* EDMA Channel 2 Interrupt */ -+#define EDMA_CH3_vect_num 6 -+#define EDMA_CH3_vect _VECTOR(6) /* EDMA Channel 3 Interrupt */ -+ -+/* RTC interrupt vectors */ -+#define RTC_OVF_vect_num 7 -+#define RTC_OVF_vect _VECTOR(7) /* Overflow Interrupt */ -+#define RTC_COMP_vect_num 8 -+#define RTC_COMP_vect _VECTOR(8) /* Compare Interrupt */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT_vect_num 9 -+#define PORTC_INT_vect _VECTOR(9) /* External Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 10 -+#define TWIC_TWIS_vect _VECTOR(10) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 11 -+#define TWIC_TWIM_vect _VECTOR(11) /* TWI Master Interrupt */ -+ -+/* TCC4 interrupt vectors */ -+#define TCC4_OVF_vect_num 12 -+#define TCC4_OVF_vect _VECTOR(12) /* Overflow Interrupt */ -+#define TCC4_ERR_vect_num 13 -+#define TCC4_ERR_vect _VECTOR(13) /* Error Interrupt */ -+#define TCC4_CCA_vect_num 14 -+#define TCC4_CCA_vect _VECTOR(14) /* Channel A Compare or Capture Interrupt */ -+#define TCC4_CCB_vect_num 15 -+#define TCC4_CCB_vect _VECTOR(15) /* Channel B Compare or Capture Interrupt */ -+#define TCC4_CCC_vect_num 16 -+#define TCC4_CCC_vect _VECTOR(16) /* Channel C Compare or Capture Interrupt */ -+#define TCC4_CCD_vect_num 17 -+#define TCC4_CCD_vect _VECTOR(17) /* Channel D Compare or Capture Interrupt */ -+ -+/* TCC5 interrupt vectors */ -+#define TCC5_OVF_vect_num 18 -+#define TCC5_OVF_vect _VECTOR(18) /* Overflow Interrupt */ -+#define TCC5_ERR_vect_num 19 -+#define TCC5_ERR_vect _VECTOR(19) /* Error Interrupt */ -+#define TCC5_CCA_vect_num 20 -+#define TCC5_CCA_vect _VECTOR(20) /* Channel A Compare or Capture Interrupt */ -+#define TCC5_CCB_vect_num 21 -+#define TCC5_CCB_vect _VECTOR(21) /* Channel B Compare or Capture Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 22 -+#define SPIC_INT_vect _VECTOR(22) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 23 -+#define USARTC0_RXC_vect _VECTOR(23) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 24 -+#define USARTC0_DRE_vect _VECTOR(24) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 25 -+#define USARTC0_TXC_vect _VECTOR(25) /* Transmission Complete Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 26 -+#define NVM_EE_vect _VECTOR(26) /* EE Interrupt */ -+#define NVM_SPM_vect_num 27 -+#define NVM_SPM_vect _VECTOR(27) /* SPM Interrupt */ -+ -+/* XCL interrupt vectors */ -+#define XCL_UNF_vect_num 28 -+#define XCL_UNF_vect _VECTOR(28) /* Timer/Counter Underflow Interrupt */ -+#define XCL_CC_vect_num 29 -+#define XCL_CC_vect _VECTOR(29) /* Timer/Counter Compare or Capture Interrupt */ -+ -+/* PORTA interrupt vectors */ -+#define PORTA_INT_vect_num 30 -+#define PORTA_INT_vect _VECTOR(30) /* External Interrupt */ -+ -+/* ACA interrupt vectors */ -+#define ACA_AC0_vect_num 31 -+#define ACA_AC0_vect _VECTOR(31) /* AC0 Interrupt */ -+#define ACA_AC1_vect_num 32 -+#define ACA_AC1_vect _VECTOR(32) /* AC1 Interrupt */ -+#define ACA_ACW_vect_num 33 -+#define ACA_ACW_vect _VECTOR(33) /* ACW Window Mode Interrupt */ -+ -+/* ADCA interrupt vectors */ -+#define ADCA_CH0_vect_num 34 -+#define ADCA_CH0_vect _VECTOR(34) /* ADC Channel Interrupt */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT_vect_num 35 -+#define PORTD_INT_vect _VECTOR(35) /* External Interrupt */ -+ -+/* TCD5 interrupt vectors */ -+#define TCD5_OVF_vect_num 36 -+#define TCD5_OVF_vect _VECTOR(36) /* Overflow Interrupt */ -+#define TCD5_ERR_vect_num 37 -+#define TCD5_ERR_vect _VECTOR(37) /* Error Interrupt */ -+#define TCD5_CCA_vect_num 38 -+#define TCD5_CCA_vect _VECTOR(38) /* Channel A Compare or Capture Interrupt */ -+#define TCD5_CCB_vect_num 39 -+#define TCD5_CCB_vect _VECTOR(39) /* Channel B Compare or Capture Interrupt */ -+ -+/* USARTD0 interrupt vectors */ -+#define USARTD0_RXC_vect_num 40 -+#define USARTD0_RXC_vect _VECTOR(40) /* Reception Complete Interrupt */ -+#define USARTD0_DRE_vect_num 41 -+#define USARTD0_DRE_vect _VECTOR(41) /* Data Register Empty Interrupt */ -+#define USARTD0_TXC_vect_num 42 -+#define USARTD0_TXC_vect _VECTOR(42) /* Transmission Complete Interrupt */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (43 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (36864) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (32768) -+#define APP_SECTION_PAGE_SIZE (128) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0x7000) -+#define APPTABLE_SECTION_SIZE (4096) -+#define APPTABLE_SECTION_PAGE_SIZE (128) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x8000) -+#define BOOT_SECTION_SIZE (4096) -+#define BOOT_SECTION_PAGE_SIZE (128) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (12288) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (1024) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (4096) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (1024) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (7) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (128) -+#define USER_SIGNATURES_PAGE_SIZE (128) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (52) -+#define PROD_SIGNATURES_PAGE_SIZE (128) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 128 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 7 -+ -+/* Fuse Byte 0 Reserved */ -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* Fuse Byte 6 */ -+#define FUSE_VALUE0 (unsigned char)~_BV(0) /* Port Pin Value Bit 0 */ -+#define FUSE_VALUE1 (unsigned char)~_BV(1) /* Port Pin Value Bit 1 */ -+#define FUSE_VALUE2 (unsigned char)~_BV(2) /* Port Pin Value Bit 2 */ -+#define FUSE_VALUE3 (unsigned char)~_BV(3) /* Port Pin Value Bit 3 */ -+#define FUSE_VALUE4 (unsigned char)~_BV(4) /* Port Pin Value Bit 4 */ -+#define FUSE_VALUE5 (unsigned char)~_BV(5) /* Port Pin Value Bit 5 */ -+#define FUSE_FDACT4 (unsigned char)~_BV(6) /* Fault Dectection Action on TC4 */ -+#define FUSE_FDACT5 (unsigned char)~_BV(7) /* Fault Dectection Action on TC5 */ -+#define FUSE6_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x95 -+#define SIGNATURE_2 0x4C -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA32E5_H_INCLUDED */ -+ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox32e5.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA32E5_H_INCLUDED ++#define _AVR_ATXMEGA32E5_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t reserved_0x04; ++} CLK_t; ++ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t reserved_0x02; ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++ CLK_SCLKSEL_RC8M_gc = (0x05<<0), /* Internal 8 MHz RC Oscillator */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++ CLK_PSADIV_6_gc = (0x13<<2), /* Divide by 6 */ ++ CLK_PSADIV_10_gc = (0x15<<2), /* Divide by 10 */ ++ CLK_PSADIV_12_gc = (0x17<<2), /* Divide by 12 */ ++ CLK_PSADIV_24_gc = (0x19<<2), /* Divide by 24 */ ++ CLK_PSADIV_48_gc = (0x1B<<2), /* Divide by 48 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++ register8_t RC8MCAL; /* Internal 8 MHz RC Oscillator Calibration Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ ++ OSC_XOSCSEL_EXTCLK_C4_gc = (0x14<<0), /* External Clock on port C4 - 6 CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC8M_gc = (0x01<<6), /* Internal 8 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t WEXLOCK; /* WEX Lock */ ++ register8_t FAULTLOCK; /* FAULT Lock */ ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t reserved_0x03; ++ register8_t CLKOUT; /* Clock Out Register */ ++ register8_t reserved_0x05; ++ register8_t ACEVOUT; /* Analog Comparator and Event Out Register */ ++ register8_t SRLCTRL; /* Slew Rate Limit Control Register */ ++} PORTCFG_t; ++ ++/* Clock and Event Output Port */ ++typedef enum PORTCFG_CLKEVPIN_enum ++{ ++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ ++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ ++} PORTCFG_CLKEVPIN_t; ++ ++/* RTC Clock Output Port */ ++typedef enum PORTCFG_RTCCLKOUT_enum ++{ ++ PORTCFG_RTCCLKOUT_OFF_gc = (0x00<<5), /* System Clock Output Disabled */ ++ PORTCFG_RTCCLKOUT_PC6_gc = (0x01<<5), /* System Clock Output on Port C pin 6 */ ++ PORTCFG_RTCCLKOUT_PD6_gc = (0x02<<5), /* System Clock Output on Port D pin 6 */ ++ PORTCFG_RTCCLKOUT_PR0_gc = (0x03<<5), /* System Clock Output on Port R pin 0 */ ++} PORTCFG_RTCCLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PR0_gc = (0x03<<0), /* System Clock Output on Port R pin 0 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Analog Comparator Output Port */ ++typedef enum PORTCFG_ACOUT_enum ++{ ++ PORTCFG_ACOUT_PA_gc = (0x00<<6), /* Analog Comparator Outputs on Port A, Pin 6-7 */ ++ PORTCFG_ACOUT_PC_gc = (0x01<<6), /* Analog Comparator Outputs on Port C, Pin 6-7 */ ++ PORTCFG_ACOUT_PD_gc = (0x02<<6), /* Analog Comparator Outputs on Port D, Pin 6-7 */ ++ PORTCFG_ACOUT_PR_gc = (0x03<<6), /* Analog Comparator Outputs on Port R, Pin 0-1 */ ++} PORTCFG_ACOUT_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel n Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel n Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PR0_gc = (0x03<<4), /* Event Channel n Output on Port R pin 0 */ ++} PORTCFG_EVOUT_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ ++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ ++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ ++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ ++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ ++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ ++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ ++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EDMA - Enhanced DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* EDMA Channel */ ++typedef struct EDMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control A */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Memory Address Control for Peripheral Ch., or Source Address Control for Standard Ch. */ ++ register8_t DESTADDRCTRL; /* Destination Address Control for Standard Channels Only. */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch. */ ++ _WORDREGISTER(ADDR); /* Channel Memory Address for Peripheral Ch., or Channel Source Address Low for Standard Ch. */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(DESTADDR); /* Channel Destination Address for Standard Channels Only. */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} EDMA_CH_t; ++ ++ ++/* Enhanced DMA Controller */ ++typedef struct EDMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ EDMA_CH_t CH0; /* EDMA Channel 0 */ ++ EDMA_CH_t CH1; /* EDMA Channel 1 */ ++ EDMA_CH_t CH2; /* EDMA Channel 2 */ ++ EDMA_CH_t CH3; /* EDMA Channel 3 */ ++} EDMA_t; ++ ++/* Channel mode */ ++typedef enum EDMA_CHMODE_enum ++{ ++ EDMA_CHMODE_PER0123_gc = (0x00<<4), /* Channels 0, 1, 2 and 3 in peripheal conf. */ ++ EDMA_CHMODE_STD0_gc = (0x01<<4), /* Channel 0 in standard conf.; channels 2 and 3 in peripheral conf. */ ++ EDMA_CHMODE_STD2_gc = (0x02<<4), /* Channel 2 in standard conf.; channels 0 and 1 in peripheral conf. */ ++ EDMA_CHMODE_STD02_gc = (0x03<<4), /* Channels 0 and 2 in standard conf. */ ++} EDMA_CHMODE_t; ++ ++/* Double buffer mode */ ++typedef enum EDMA_DBUFMODE_enum ++{ ++ EDMA_DBUFMODE_DISABLE_gc = (0x00<<2), /* No double buffer enabled */ ++ EDMA_DBUFMODE_BUF01_gc = (0x01<<2), /* Double buffer enabled on peripheral channels 0/1 (if exist) */ ++ EDMA_DBUFMODE_BUF23_gc = (0x02<<2), /* Double buffer enabled on peripheral channels 2/3 (if exist) */ ++ EDMA_DBUFMODE_BUF0123_gc = (0x03<<2), /* Double buffer enabled on peripheral channels 0/1 and 2/3 or standard channels 0/2 */ ++} EDMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum EDMA_PRIMODE_enum ++{ ++ EDMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round robin on all channels */ ++ EDMA_PRIMODE_RR123_gc = (0x01<<0), /* Ch0 > round robin (Ch 1 ch2 Ch3) */ ++ EDMA_PRIMODE_RR23_gc = (0x02<<0), /* Ch0 > Ch 1 > round robin (Ch2 Ch3) */ ++ EDMA_PRIMODE_CH0123_gc = (0x03<<0), /* Ch0 > Ch1 > Ch2 > Ch3 */ ++} EDMA_PRIMODE_t; ++ ++/* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. */ ++typedef enum EDMA_CH_RELOAD_enum ++{ ++ EDMA_CH_RELOAD_NONE_gc = (0x00<<4), /* No reload */ ++ EDMA_CH_RELOAD_BLOCK_gc = (0x01<<4), /* Reload at end of each block transfer */ ++ EDMA_CH_RELOAD_BURST_gc = (0x02<<4), /* Reload at end of each burst transfer */ ++ EDMA_CH_RELOAD_TRANSACTION_gc = (0x03<<4), /* Reload at end of each transaction */ ++} EDMA_CH_RELOAD_t; ++ ++/* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. */ ++typedef enum EDMA_CH_DIR_enum ++{ ++ EDMA_CH_DIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ EDMA_CH_DIR_INC_gc = (0x01<<0), /* Increment */ ++ EDMA_CH_DIR_MP1_gc = (0x04<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'mask-match' (data: ADDRL, mask: ADDRH), else reserved conf. */ ++ EDMA_CH_DIR_MP2_gc = (0x05<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH), else reserved conf. */ ++ EDMA_CH_DIR_MP3_gc = (0x06<<0), /* If Peripheral Ch. (Per ==> Mem), 2-byte 'match' (data-1: ADDRL followed by data-2: ADDRH), else reserved conf. */ ++} EDMA_CH_DIR_t; ++ ++/* Destination addressing mode */ ++typedef enum EDMA_CH_DESTDIR_enum ++{ ++ EDMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ EDMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ EDMA_CH_DESTDIR_MP1_gc = (0x04<<0), /* 1-byte 'mask-match' (data: ADDRL, mask: ADDRH) */ ++ EDMA_CH_DESTDIR_MP2_gc = (0x05<<0), /* 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH) */ ++ EDMA_CH_DESTDIR_MP3_gc = (0x06<<0), /* 2-byte 'match' (data1: ADDRL followed by data2: ADDRH) */ ++} EDMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum EDMA_CH_TRIGSRC_enum ++{ ++ EDMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Software triggers only */ ++ EDMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event CH0 as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event CH1 as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event CH2 as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA CH0 as trigger */ ++ EDMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA CH0 as trigger */ ++ EDMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA CH1 as trigger */ ++ EDMA_CH_TRIGSRC_TCC4_OVF_gc = (0x40<<0), /* TCC4 overflow/underflow as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCC4_ERR_gc = (0x41<<0), /* TCC4 error as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCC4_CCA_gc = (0x42<<0), /* TCC4 compare or capture channel A as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCC4_CCB_gc = (0x43<<0), /* TCC4 compare or capture channel B as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCC4_CCC_gc = (0x44<<0), /* TCC4 compare or capture channel C as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCC4_CCD_gc = (0x45<<0), /* TCC4 compare or capture channel D as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCC5_OVF_gc = (0x46<<0), /* TCC5 overflow/underflow as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCC5_ERR_gc = (0x47<<0), /* TCC5 error as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCC5_CCA_gc = (0x48<<0), /* TCC5 compare or capture channel A as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCC5_CCB_gc = (0x49<<0), /* TCC5 compare or capture channel B as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_SPIC_RXC_gc = (0x4A<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C receive complete as trigger (SPI Buffer Modes) */ ++ EDMA_CH_TRIGSRC_SPIC_DRE_gc = (0x4B<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C data register empty as trigger (SPI Buffer modes) */ ++ EDMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4C<<0), /* USART C0 receive complete as trigger */ ++ EDMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4D<<0), /* USART C0 data register empty as trigger */ ++ EDMA_CH_TRIGSRC_TCD5_OVF_gc = (0x66<<0), /* TCD5 overflow/underflow as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCD5_ERR_gc = (0x67<<0), /* TCD5 error as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCD5_CCA_gc = (0x68<<0), /* TCD5 compare or capture channel A as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCD5_CCB_gc = (0x69<<0), /* TCD5 compare or capture channel B as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6C<<0), /* USART D0 receive complete as trigger */ ++ EDMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6D<<0), /* USART D0 data register empty as trigger */ ++} EDMA_CH_TRIGSRC_t; ++ ++/* Interrupt level */ ++typedef enum EDMA_CH_INTLVL_enum ++{ ++ EDMA_CH_INTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ EDMA_CH_INTLVL_LO_gc = (0x01<<2), /* Low level */ ++ EDMA_CH_INTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ EDMA_CH_INTLVL_HI_gc = (0x03<<2), /* High level */ ++} EDMA_CH_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ ++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ ++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ ++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t CH4CTRL; /* Channel 4 Control Register */ ++ register8_t CH5CTRL; /* Channel 5 Control Register */ ++ register8_t CH6CTRL; /* Channel 6 Control Register */ ++ register8_t CH7CTRL; /* Channel 7 Control Register */ ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++ register8_t DFCTRL; /* Digital Filter Control Register */ ++} EVSYS_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_XCL_UNF0_gc = (0xB0<<0), /* XCL BTC0 underflow */ ++ EVSYS_CHMUX_XCL_UNF1_gc = (0xB1<<0), /* XCL BTC1 underflow */ ++ EVSYS_CHMUX_XCL_CC0_gc = (0xB2<<0), /* XCL BTC0 capture or compare */ ++ EVSYS_CHMUX_XCL_CC1_gc = (0xB3<<0), /* XCL BTC0 capture or compare */ ++ EVSYS_CHMUX_XCL_PEC0_gc = (0xB4<<0), /* XCL PEC0 restart */ ++ EVSYS_CHMUX_XCL_PEC1_gc = (0xB5<<0), /* XCL PEC1 restart */ ++ EVSYS_CHMUX_XCL_LUT0_gc = (0xB6<<0), /* XCL LUT0 output */ ++ EVSYS_CHMUX_XCL_LUT1_gc = (0xB7<<0), /* XCL LUT1 output */ ++ EVSYS_CHMUX_TCC4_OVF_gc = (0xC0<<0), /* Timer/Counter C4 Overflow */ ++ EVSYS_CHMUX_TCC4_ERR_gc = (0xC1<<0), /* Timer/Counter C4 Error */ ++ EVSYS_CHMUX_TCC4_CCA_gc = (0xC4<<0), /* Timer/Counter C4 Compare or Capture A */ ++ EVSYS_CHMUX_TCC4_CCB_gc = (0xC5<<0), /* Timer/Counter C4 Compare or Capture B */ ++ EVSYS_CHMUX_TCC4_CCC_gc = (0xC6<<0), /* Timer/Counter C4 Compare or Capture C */ ++ EVSYS_CHMUX_TCC4_CCD_gc = (0xC7<<0), /* Timer/Counter C4 Compare or Capture D */ ++ EVSYS_CHMUX_TCC5_OVF_gc = (0xC8<<0), /* Timer/Counter C5 Overflow */ ++ EVSYS_CHMUX_TCC5_ERR_gc = (0xC9<<0), /* Timer/Counter C5 Error */ ++ EVSYS_CHMUX_TCC5_CCA_gc = (0xCC<<0), /* Timer/Counter C5 Compare or Capture A */ ++ EVSYS_CHMUX_TCC5_CCB_gc = (0xCD<<0), /* Timer/Counter C5 Compare or Capture B */ ++ EVSYS_CHMUX_TCD5_OVF_gc = (0xD8<<0), /* Timer/Counter D5 Overflow */ ++ EVSYS_CHMUX_TCD5_ERR_gc = (0xD9<<0), /* Timer/Counter D5 Error */ ++ EVSYS_CHMUX_TCD5_CCA_gc = (0xDC<<0), /* Timer/Counter D5 Compare or Capture A */ ++ EVSYS_CHMUX_TCD5_CCB_gc = (0xDD<<0), /* Timer/Counter D5 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Prescaler Filter */ ++typedef enum EVSYS_PRESCFILT_enum ++{ ++ EVSYS_PRESCFILT_CH04_gc = (0x01<<4), /* Enable prescaler filter for either channel 0 or 4 */ ++ EVSYS_PRESCFILT_CH15_gc = (0x02<<4), /* Enable prescaler filter for either channel 1 or 5 */ ++ EVSYS_PRESCFILT_CH26_gc = (0x04<<4), /* Enable prescaler filter for either channel 2 or 6 */ ++ EVSYS_PRESCFILT_CH37_gc = (0x08<<4), /* Enable prescaler filter for either channel 3 or 7 */ ++} EVSYS_PRESCFILT_t; ++ ++/* Prescaler */ ++typedef enum EVSYS_PRESCALER_enum ++{ ++ EVSYS_PRESCALER_CLKPER_8_gc = (0x00<<0), /* CLKPER, divide by 8 */ ++ EVSYS_PRESCALER_CLKPER_64_gc = (0x01<<0), /* CLKPER, divide by 64 */ ++ EVSYS_PRESCALER_CLKPER_512_gc = (0x02<<0), /* CLKPER, divide by 512 */ ++ EVSYS_PRESCALER_CLKPER_4096_gc = (0x03<<0), /* CLKPER, divide by 4096 */ ++ EVSYS_PRESCALER_CLKPER_32768_gc = (0x04<<0), /* CLKPER, divide by 32768 */ ++} EVSYS_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t CORRCTRL; /* Correction Control Register */ ++ register8_t OFFSETCORR0; /* Offset Correction Register 0 */ ++ register8_t OFFSETCORR1; /* Offset Correction Register 1 */ ++ register8_t GAINCORR0; /* Gain Correction Register 0 */ ++ register8_t GAINCORR1; /* Gain Correction Register 1 */ ++ register8_t AVGCTRL; /* Average Control Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++} ADC_t; ++ ++/* Current Limitation */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ ++} ADC_CURRLIMIT_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_MT12BIT_gc = (0x01<<1), /* More than 12-bit (oversapling) right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFD_gc = (0x03<<4), /* External reference on PORT D */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ ++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ ++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ ++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ ++ ADC_EVSEL_4_gc = (0x04<<3), /* Event Channel 4 */ ++ ADC_EVSEL_5_gc = (0x05<<3), /* Event Channel 5 */ ++ ADC_EVSEL_6_gc = (0x06<<3), /* Event Channel 6 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel conversion */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAINL_gc = (0x02<<0), /* Differential input, gain with 4 LSB pins selection */ ++ ADC_CH_INPUTMODE_DIFFWGAINH_gc = (0x03<<0), /* Differential input, gain with 4 MSB pins selection */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 Scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC Output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection when gain on 4 LSB pins */ ++typedef enum ADC_CH_MUXNEGL_enum ++{ ++ ADC_CH_MUXNEGL_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEGL_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEGL_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEGL_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEGL_GND_gc = (0x05<<0), /* PAD ground */ ++ ADC_CH_MUXNEGL_INTGND_gc = (0x07<<0), /* Internal ground */ ++} ADC_CH_MUXNEGL_t; ++ ++/* Negative input multiplexer selection when gain on 4 MSB pins */ ++typedef enum ADC_CH_MUXNEGH_enum ++{ ++ ADC_CH_MUXNEGH_PIN4_gc = (0x00<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEGH_PIN5_gc = (0x01<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEGH_PIN6_gc = (0x02<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEGH_PIN7_gc = (0x03<<0), /* Input pin 7 */ ++ ADC_CH_MUXNEGH_GND_gc = (0x05<<0), /* PAD ground */ ++} ADC_CH_MUXNEGH_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* Averaged Number of Samples */ ++typedef enum ADC_SAMPNUM_enum ++{ ++ ADC_SAMPNUM_1X_gc = (0x00<<0), /* 1 Sample */ ++ ADC_SAMPNUM_2X_gc = (0x01<<0), /* 2 Samples */ ++ ADC_SAMPNUM_4X_gc = (0x02<<0), /* 4 Samples */ ++ ADC_SAMPNUM_8X_gc = (0x03<<0), /* 8 Samples */ ++ ADC_SAMPNUM_16X_gc = (0x04<<0), /* 16 Samples */ ++ ADC_SAMPNUM_32X_gc = (0x05<<0), /* 32 Samples */ ++ ADC_SAMPNUM_64X_gc = (0x06<<0), /* 64 Samples */ ++ ADC_SAMPNUM_128X_gc = (0x07<<0), /* 128 Samples */ ++ ADC_SAMPNUM_256X_gc = (0x08<<0), /* 256 Samples */ ++ ADC_SAMPNUM_512X_gc = (0x09<<0), /* 512 Samples */ ++ ADC_SAMPNUM_1024X_gc = (0x0A<<0), /* 1024 Samples */ ++} ADC_SAMPNUM_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DAC - Digital/Analog Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Digital-to-Analog Converter */ ++typedef struct DAC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t EVCTRL; /* Event Input Control */ ++ register8_t reserved_0x04; ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0GAINCAL; /* Gain Calibration */ ++ register8_t CH0OFFSETCAL; /* Offset Calibration */ ++ register8_t CH1GAINCAL; /* Gain Calibration */ ++ register8_t CH1OFFSETCAL; /* Offset Calibration */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ ++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ ++} DAC_t; ++ ++/* Output channel selection */ ++typedef enum DAC_CHSEL_enum ++{ ++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ ++ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ ++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ ++} DAC_CHSEL_t; ++ ++/* Reference voltage selection */ ++typedef enum DAC_REFSEL_enum ++{ ++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ ++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ ++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ ++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ ++} DAC_REFSEL_t; ++ ++/* Event channel selection */ ++typedef enum DAC_EVSEL_enum ++{ ++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ ++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ ++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ ++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ ++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ ++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ ++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ ++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ ++} DAC_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++ register8_t CURRCTRL; /* Current Source Control Register */ ++ register8_t CURRCALIB; /* Current Source Calibration Register */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Clounter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t CALIB; /* Calibration Register */ ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XCL - XMEGA Custom Logic ++-------------------------------------------------------------------------- ++*/ ++ ++/* XMEGA Custom Logic */ ++typedef struct XCL_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t CTRLF; /* Control Register F */ ++ register8_t CTRLG; /* Control Register G */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t PLC; /* Peripheral Lenght Control Register */ ++ register8_t CNTL; /* Counter Register Low */ ++ register8_t CNTH; /* Counter Register High */ ++ register8_t CMPL; /* Compare Register Low */ ++ register8_t CMPH; /* Compare Register High */ ++ register8_t PERCAPTL; /* Period or Capture Register Low */ ++ register8_t PERCAPTH; /* Period or Capture Register High */ ++} XCL_t; ++ ++/* LUT0 Output Enable */ ++typedef enum XCL_LUTOUTEN_enum ++{ ++ XCL_LUTOUTEN_DISABLE_gc = (0x00<<6), /* LUT0 output disabled */ ++ XCL_LUTOUTEN_PIN0_gc = (0x01<<6), /* LUT0 Output to pin 0 */ ++ XCL_LUTOUTEN_PIN4_gc = (0x02<<6), /* LUT0 Output to pin 4 */ ++} XCL_LUTOUTEN_t; ++ ++/* Port Selection */ ++typedef enum XCL_PORTSEL_enum ++{ ++ XCL_PORTSEL_PC_gc = (0x00<<4), /* Port C for LUT or USARTC0 for PEC */ ++ XCL_PORTSEL_PD_gc = (0x01<<4), /* Port D for LUT or USARTD0 for PEC */ ++} XCL_PORTSEL_t; ++ ++/* LUT Configuration */ ++typedef enum XCL_LUTCONF_enum ++{ ++ XCL_LUTCONF_2LUT2IN_gc = (0x00<<0), /* 2-Input two LUT */ ++ XCL_LUTCONF_2LUT1IN_gc = (0x01<<0), /* Two LUT with duplicated input */ ++ XCL_LUTCONF_2LUT3IN_gc = (0x02<<0), /* Two LUT with one common input */ ++ XCL_LUTCONF_1LUT3IN_gc = (0x03<<0), /* 3-Input LUT */ ++ XCL_LUTCONF_MUX_gc = (0x04<<0), /* One LUT Mux */ ++ XCL_LUTCONF_DLATCH_gc = (0x05<<0), /* One D-Latch LUT */ ++ XCL_LUTCONF_RSLATCH_gc = (0x06<<0), /* One RS-Latch LUT */ ++ XCL_LUTCONF_DFF_gc = (0x07<<0), /* One DFF LUT */ ++} XCL_LUTCONF_t; ++ ++/* Input Selection */ ++typedef enum XCL_INSEL_enum ++{ ++ XCL_INSEL_EVSYS_gc = (0x00<<6), /* Event system selected as source */ ++ XCL_INSEL_XCL_gc = (0x01<<6), /* XCL selected as source */ ++ XCL_INSEL_PINL_gc = (0x02<<6), /* LSB port pin selected as source */ ++ XCL_INSEL_PINH_gc = (0x03<<6), /* MSB port pin selected as source */ ++} XCL_INSEL_t; ++ ++/* Delay Configuration on LUT */ ++typedef enum XCL_DLYCONF_enum ++{ ++ XCL_DLYCONF_DISABLE_gc = (0x00<<2), /* Delay element disabled */ ++ XCL_DLYCONF_IN_gc = (0x01<<2), /* Delay enabled on LUT input */ ++ XCL_DLYCONF_OUT_gc = (0x02<<2), /* Delay enabled on LUT output */ ++} XCL_DLYCONF_t; ++ ++/* Delay Selection */ ++typedef enum XCL_DLYSEL_enum ++{ ++ XCL_DLYSEL_DLY11_gc = (0x00<<4), /* One cycle delay for each LUT1 and LUT0 */ ++ XCL_DLYSEL_DLY12_gc = (0x01<<4), /* One cycle delay for LUT1 and two cycles for LUT0 */ ++ XCL_DLYSEL_DLY21_gc = (0x02<<4), /* Two cycles delay for LUT1 and one cycle for LUT0 */ ++ XCL_DLYSEL_DLY22_gc = (0x03<<4), /* Two cycle delays for each LUT1 and LUT0 */ ++} XCL_DLYSEL_t; ++ ++/* Clock Selection */ ++typedef enum XCL_CLKSEL_enum ++{ ++ XCL_CLKSEL_OFF_gc = (0x00<<0), /* OFF */ ++ XCL_CLKSEL_DIV1_gc = (0x01<<0), /* Prescaler clk */ ++ XCL_CLKSEL_DIV2_gc = (0x02<<0), /* Prescaler clk/2 */ ++ XCL_CLKSEL_DIV4_gc = (0x03<<0), /* Prescaler clk/4 */ ++ XCL_CLKSEL_DIV8_gc = (0x04<<0), /* Prescaler clk/8 */ ++ XCL_CLKSEL_DIV64_gc = (0x05<<0), /* Prescaler clk/64 */ ++ XCL_CLKSEL_DIV256_gc = (0x06<<0), /* Prescaler clk/256 */ ++ XCL_CLKSEL_DIV1024_gc = (0x07<<0), /* Prescaler clk/1024 */ ++ XCL_CLKSEL_EVCH0_gc = (0x08<<0), /* Event channel 0 */ ++ XCL_CLKSEL_EVCH1_gc = (0x09<<0), /* Event channel 1 */ ++ XCL_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event channel 2 */ ++ XCL_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event channel 3 */ ++ XCL_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event channel 4 */ ++ XCL_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event channel 5 */ ++ XCL_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event channel 6 */ ++ XCL_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event channel 7 */ ++} XCL_CLKSEL_t; ++ ++/* Timer/Counter Command Selection */ ++typedef enum XCL_CMDSEL_enum ++{ ++ XCL_CMDSEL_NONE_gc = (0x00<<7), /* None */ ++ XCL_CMDSEL_RESTART_gc = (0x01<<7), /* Force restart */ ++} XCL_CMDSEL_t; ++ ++/* Timer/Counter Selection */ ++typedef enum XCL_TCSEL_enum ++{ ++ XCL_TCSEL_TC16_gc = (0x00<<4), /* 16-bit timer/counter */ ++ XCL_TCSEL_BTC0_gc = (0x01<<4), /* One 8-bit timer/counter */ ++ XCL_TCSEL_BTC01_gc = (0x02<<4), /* Two 8-bit timer/counters */ ++ XCL_TCSEL_BTC0PEC1_gc = (0x03<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ ++ XCL_TCSEL_PEC0BTC1_gc = (0x04<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ ++ XCL_TCSEL_PEC01_gc = (0x05<<4), /* Two 8-bit peripheral counters */ ++ XCL_TCSEL_BTC0PEC2_gc = (0x06<<4), /* One 8-bit timer/counter and two 4-bit peripheral counters */ ++} XCL_TCSEL_t; ++ ++/* Timer/Counter Mode */ ++typedef enum XCL_TCMODE_enum ++{ ++ XCL_TCMODE_NORMAL_gc = (0x00<<0), /* Normal mode with compare/period */ ++ XCL_TCMODE_CAPT_gc = (0x01<<0), /* Capture mode */ ++ XCL_TCMODE_PWM_gc = (0x02<<0), /* Single Slope PWM */ ++} XCL_TCMODE_t; ++ ++/* Compare Output Value Timer */ ++typedef enum XCL_CMPEN_enum ++{ ++ XCL_CMPEN_CLEAR_gc = (0x00<<5), /* Clear WG Output */ ++ XCL_CMPEN_SET_gc = (0x01<<5), /* Set WG Output */ ++} XCL_CMPEN_t; ++ ++/* Command Enable */ ++typedef enum XCL_CMDEN_enum ++{ ++ XCL_CMDEN_DISABLE_gc = (0x00<<6), /* Command Ignored */ ++ XCL_CMDEN_CMD0_gc = (0x01<<6), /* Command valid for timer/counter 0 */ ++ XCL_CMDEN_CMD1_gc = (0x02<<6), /* Command valid for timer/counter 1 */ ++ XCL_CMDEN_CMD01_gc = (0x03<<6), /* Command valid for both timer/counter 0 and 1 */ ++} XCL_CMDEN_t; ++ ++/* Timer/Counter Event Source Selection */ ++typedef enum XCL_EVSRC_enum ++{ ++ XCL_EVSRC_EVCH0_gc = (0x00<<0), /* Event channel 0 */ ++ XCL_EVSRC_EVCH1_gc = (0x01<<0), /* Event channel 1 */ ++ XCL_EVSRC_EVCH2_gc = (0x02<<0), /* Event channel 2 */ ++ XCL_EVSRC_EVCH3_gc = (0x03<<0), /* Event channel 3 */ ++ XCL_EVSRC_EVCH4_gc = (0x04<<0), /* Event channel 4 */ ++ XCL_EVSRC_EVCH5_gc = (0x05<<0), /* Event channel 5 */ ++ XCL_EVSRC_EVCH6_gc = (0x06<<0), /* Event channel 6 */ ++ XCL_EVSRC_EVCH7_gc = (0x07<<0), /* Event channel 7 */ ++} XCL_EVSRC_t; ++ ++/* Timer/Counter Event Action Selection */ ++typedef enum XCL_EVACT_enum ++{ ++ XCL_EVACT_INPUT_gc = (0x00<<5), /* Input Capture */ ++ XCL_EVACT_FREQ_gc = (0x01<<5), /* Frequency Capture */ ++ XCL_EVACT_PW_gc = (0x02<<5), /* Pulse Width Capture */ ++ XCL_EVACT_RESTART_gc = (0x03<<5), /* Restart timer/counter */ ++} XCL_EVACT_t; ++ ++/* Underflow Interrupt level */ ++typedef enum XCL_UNF_INTLVL_enum ++{ ++ XCL_UNF_INTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ XCL_UNF_INTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ XCL_UNF_INTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ XCL_UNF_INTLVL_HI_gc = (0x03<<2), /* High Level */ ++} XCL_UNF_INTLVL_t; ++ ++/* Compare/Capture Interrupt level */ ++typedef enum XCL_CC_INTLVL_enum ++{ ++ XCL_CC_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ XCL_CC_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ XCL_CC_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ XCL_CC_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} XCL_CC_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* */ ++typedef struct TWI_TIMEOUT_struct ++{ ++ register8_t TOS; /* Timeout Status Register */ ++ register8_t TOCONF; /* Timeout Configuration Register */ ++} TWI_TIMEOUT_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++ TWI_TIMEOUT_t TIMEOUT; /* TWI SMBUS timeout module */ ++} TWI_t; ++ ++/* SDA Hold Time */ ++typedef enum TWI_SDAHOLD_enum ++{ ++ TWI_SDAHOLD_OFF_gc = (0x00<<4), /* SDA Hold Time off */ ++ TWI_SDAHOLD_50NS_gc = (0x01<<4), /* SDA Hold Time 50 ns */ ++ TWI_SDAHOLD_300NS_gc = (0x02<<4), /* SDA Hold Time 300 ns */ ++ TWI_SDAHOLD_400NS_gc = (0x03<<4), /* SDA Hold Time 400 ns */ ++} TWI_SDAHOLD_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++/* Master Timeout */ ++typedef enum TWI_MASTER_TTIMEOUT_enum ++{ ++ TWI_MASTER_TTIMEOUT_25MS_gc = (0x00<<0), /* 25 Milliseconds */ ++ TWI_MASTER_TTIMEOUT_24MS_gc = (0x01<<0), /* 24 Milliseconds */ ++ TWI_MASTER_TTIMEOUT_23MS_gc = (0x02<<0), /* 23 Milliseconds */ ++ TWI_MASTER_TTIMEOUT_22MS_gc = (0x03<<0), /* 22 Milliseconds */ ++ TWI_MASTER_TTIMEOUT_26MS_gc = (0x04<<0), /* 26 Milliseconds */ ++ TWI_MASTER_TTIMEOUT_27MS_gc = (0x05<<0), /* 27 Milliseconds */ ++ TWI_MASTER_TTIMEOUT_28MS_gc = (0x06<<0), /* 28 Milliseconds */ ++ TWI_MASTER_TTIMEOUT_29MS_gc = (0x07<<0), /* 29 Milliseconds */ ++} TWI_MASTER_TTIMEOUT_t; ++ ++/* Slave Ttimeout */ ++typedef enum TWI_SLAVE_TTIMEOUT_enum ++{ ++ TWI_SLAVE_TTIMEOUT_25MS_gc = (0x00<<5), /* 25 Milliseconds */ ++ TWI_SLAVE_TTIMEOUT_24MS_gc = (0x01<<5), /* 24 Milliseconds */ ++ TWI_SLAVE_TTIMEOUT_23MS_gc = (0x02<<5), /* 23 Milliseconds */ ++ TWI_SLAVE_TTIMEOUT_22MS_gc = (0x03<<5), /* 22 Milliseconds */ ++ TWI_SLAVE_TTIMEOUT_26MS_gc = (0x04<<5), /* 26 Milliseconds */ ++ TWI_SLAVE_TTIMEOUT_27MS_gc = (0x05<<5), /* 27 Milliseconds */ ++ TWI_SLAVE_TTIMEOUT_28MS_gc = (0x06<<5), /* 28 Milliseconds */ ++ TWI_SLAVE_TTIMEOUT_29MS_gc = (0x07<<5), /* 29 Milliseconds */ ++} TWI_SLAVE_TTIMEOUT_t; ++ ++/* Master/Slave Extend Timeout */ ++typedef enum TWI_MASTER_TMSEXT_enum ++{ ++ TWI_MASTER_TMSEXT_10MS25MS_gc = (0x00<<3), /* Tmext 10ms Tsext 25ms */ ++ TWI_MASTER_TMSEXT_9MS24MS_gc = (0x01<<3), /* Tmext 9ms Tsext 24ms */ ++ TWI_MASTER_TMSEXT_11MS26MS_gc = (0x02<<3), /* Tmext 11ms Tsext 26ms */ ++ TWI_MASTER_TMSEXT_12MS27MS_gc = (0x03<<3), /* Tmext 12ms Tsext 27ms */ ++} TWI_MASTER_TMSEXT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTMASK; /* Port Interrupt Mask */ ++ register8_t reserved_0x0B; ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt Level */ ++typedef enum PORT_INTLVL_enum ++{ ++ PORT_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INTLVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_FORCE_ENABLE_gc = (0x06<<0), /* Digital Input Buffer Forced Enable */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 4 */ ++typedef struct TC4_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t CTRLF; /* Control Register F */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t CTRLHCLR; /* Control Register H Clear */ ++ register8_t CTRLHSET; /* Control Register H Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC4_t; ++ ++ ++/* 16-bit Timer/Counter 5 */ ++typedef struct TC5_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t CTRLF; /* Control Register F */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t CTRLHCLR; /* Control Register H Clear */ ++ register8_t CTRLHSET; /* Control Register H Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++} TC5_t; ++ ++/* Clock Selection */ ++typedef enum TC45_CLKSEL_enum ++{ ++ TC45_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC45_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC45_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC45_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC45_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC45_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC45_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC45_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC45_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC45_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC45_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC45_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC45_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC45_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC45_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC45_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC45_CLKSEL_t; ++ ++/* Byte Mode */ ++typedef enum TC45_BYTEM_enum ++{ ++ TC45_BYTEM_NORMAL_gc = (0x00<<6), /* 16-bit mode */ ++ TC45_BYTEM_BYTEMODE_gc = (0x01<<6), /* Timer/Counter Operating in Byte Mode Only */ ++} TC45_BYTEM_t; ++ ++/* Circular Enable Mode */ ++typedef enum TC45_CIRCEN_enum ++{ ++ TC45_CIRCEN_DISABLE_gc = (0x00<<4), /* Circular Buffer Disabled */ ++ TC45_CIRCEN_PER_gc = (0x01<<4), /* Circular Buffer Enabled on PER/PERBUF */ ++ TC45_CIRCEN_CCA_gc = (0x02<<4), /* Circular Buffer Enabled on CCA/CCABUF */ ++ TC45_CIRCEN_BOTH_gc = (0x03<<4), /* Circular Buffer Enabled on All Buffered Registers */ ++} TC45_CIRCEN_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC45_WGMODE_enum ++{ ++ TC45_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC45_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC45_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC45_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC45_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Both */ ++ TC45_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC45_WGMODE_t; ++ ++/* Event Action */ ++typedef enum TC45_EVACT_enum ++{ ++ TC45_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC45_EVACT_FMODE1_gc = (0x01<<5), /* Fault Mode 1 capture */ ++ TC45_EVACT_FMODE2_gc = (0x02<<5), /* Fault Mode 2 capture */ ++ TC45_EVACT_UPDOWN_gc = (0x03<<5), /* Up/down count */ ++ TC45_EVACT_QDEC_gc = (0x04<<5), /* Quadrature decode */ ++ TC45_EVACT_RESTART_gc = (0x05<<5), /* Restart */ ++ TC45_EVACT_PWF_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC45_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC45_EVSEL_enum ++{ ++ TC45_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC45_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC45_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC45_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC45_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC45_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC45_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC45_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC45_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC45_EVSEL_t; ++ ++/* Compare or Capture Channel A Mode */ ++typedef enum TC45_CCAMODE_enum ++{ ++ TC45_CCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ ++ TC45_CCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ ++ TC45_CCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ ++ TC45_CCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ ++} TC45_CCAMODE_t; ++ ++/* Compare or Capture Channel B Mode */ ++typedef enum TC45_CCBMODE_enum ++{ ++ TC45_CCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ ++ TC45_CCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ ++ TC45_CCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ ++ TC45_CCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ ++} TC45_CCBMODE_t; ++ ++/* Compare or Capture Channel C Mode */ ++typedef enum TC45_CCCMODE_enum ++{ ++ TC45_CCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ ++ TC45_CCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ ++ TC45_CCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ ++ TC45_CCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ ++} TC45_CCCMODE_t; ++ ++/* Compare or Capture Channel D Mode */ ++typedef enum TC45_CCDMODE_enum ++{ ++ TC45_CCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ ++ TC45_CCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ ++ TC45_CCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ ++ TC45_CCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ ++} TC45_CCDMODE_t; ++ ++/* Compare or Capture Low Channel A Mode */ ++typedef enum TC45_LCCAMODE_enum ++{ ++ TC45_LCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ ++ TC45_LCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ ++ TC45_LCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ ++ TC45_LCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ ++} TC45_LCCAMODE_t; ++ ++/* Compare or Capture Low Channel B Mode */ ++typedef enum TC45_LCCBMODE_enum ++{ ++ TC45_LCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ ++ TC45_LCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ ++ TC45_LCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ ++ TC45_LCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ ++} TC45_LCCBMODE_t; ++ ++/* Compare or Capture Low Channel C Mode */ ++typedef enum TC45_LCCCMODE_enum ++{ ++ TC45_LCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ ++ TC45_LCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ ++ TC45_LCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ ++ TC45_LCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ ++} TC45_LCCCMODE_t; ++ ++/* Compare or Capture Low Channel D Mode */ ++typedef enum TC45_LCCDMODE_enum ++{ ++ TC45_LCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ ++ TC45_LCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ ++ TC45_LCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ ++ TC45_LCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ ++} TC45_LCCDMODE_t; ++ ++/* Compare or Capture High Channel A Mode */ ++typedef enum TC45_HCCAMODE_enum ++{ ++ TC45_HCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ ++ TC45_HCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ ++ TC45_HCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ ++ TC45_HCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ ++} TC45_HCCAMODE_t; ++ ++/* Compare or Capture High Channel B Mode */ ++typedef enum TC45_HCCBMODE_enum ++{ ++ TC45_HCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ ++ TC45_HCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ ++ TC45_HCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ ++ TC45_HCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ ++} TC45_HCCBMODE_t; ++ ++/* Compare or Capture High Channel C Mode */ ++typedef enum TC45_HCCCMODE_enum ++{ ++ TC45_HCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ ++ TC45_HCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ ++ TC45_HCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ ++ TC45_HCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ ++} TC45_HCCCMODE_t; ++ ++/* Compare or Capture High Channel D Mode */ ++typedef enum TC45_HCCDMODE_enum ++{ ++ TC45_HCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ ++ TC45_HCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ ++ TC45_HCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ ++ TC45_HCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ ++} TC45_HCCDMODE_t; ++ ++/* Timer Trigger Restart Interrupt Level */ ++typedef enum TC45_TRGINTLVL_enum ++{ ++ TC45_TRGINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC45_TRGINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC45_TRGINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC45_TRGINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC45_TRGINTLVL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC45_ERRINTLVL_enum ++{ ++ TC45_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC45_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC45_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC45_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC45_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC45_OVFINTLVL_enum ++{ ++ TC45_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC45_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC45_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC45_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC45_OVFINTLVL_t; ++ ++/* Compare or Capture Channel A Interrupt Level */ ++typedef enum TC45_CCAINTLVL_enum ++{ ++ TC45_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC45_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC45_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC45_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC45_CCAINTLVL_t; ++ ++/* Compare or Capture Channel B Interrupt Level */ ++typedef enum TC45_CCBINTLVL_enum ++{ ++ TC45_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC45_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC45_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC45_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC45_CCBINTLVL_t; ++ ++/* Compare or Capture Channel C Interrupt Level */ ++typedef enum TC45_CCCINTLVL_enum ++{ ++ TC45_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC45_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC45_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC45_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC45_CCCINTLVL_t; ++ ++/* Compare or Capture Channel D Interrupt Level */ ++typedef enum TC45_CCDINTLVL_enum ++{ ++ TC45_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC45_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC45_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC45_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC45_CCDINTLVL_t; ++ ++/* Compare or Capture Low Channel A Interrupt Level */ ++typedef enum TC45_LCCAINTLVL_enum ++{ ++ TC45_LCCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC45_LCCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC45_LCCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC45_LCCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC45_LCCAINTLVL_t; ++ ++/* Compare or Capture Low Channel B Interrupt Level */ ++typedef enum TC45_LCCBINTLVL_enum ++{ ++ TC45_LCCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC45_LCCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC45_LCCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC45_LCCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC45_LCCBINTLVL_t; ++ ++/* Compare or Capture Low Channel C Interrupt Level */ ++typedef enum TC45_LCCCINTLVL_enum ++{ ++ TC45_LCCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC45_LCCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC45_LCCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC45_LCCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC45_LCCCINTLVL_t; ++ ++/* Compare or Capture Low Channel D Interrupt Level */ ++typedef enum TC45_LCCDINTLVL_enum ++{ ++ TC45_LCCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC45_LCCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC45_LCCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC45_LCCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC45_LCCDINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC45_CMD_enum ++{ ++ TC45_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC45_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC45_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC45_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC45_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FAULT - Fault Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fault Extension */ ++typedef struct FAULT_struct ++{ ++ register8_t CTRLA; /* Control A Register */ ++ register8_t CTRLB; /* Control B Register */ ++ register8_t CTRLC; /* Control C Register */ ++ register8_t CTRLD; /* Control D Register */ ++ register8_t CTRLE; /* Control E Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G set */ ++} FAULT_t; ++ ++/* Ramp Mode Selection */ ++typedef enum FAULT_RAMP_enum ++{ ++ FAULT_RAMP_RAMP1_gc = (0x00<<6), /* Normal Mode */ ++ FAULT_RAMP_RAMP2_gc = (0x02<<6), /* RAMP2 Mode */ ++} FAULT_RAMP_t; ++ ++/* Fault E Input Source Selection */ ++typedef enum FAULT_SRCE_enum ++{ ++ FAULT_SRCE_DISABLE_gc = (0x00<<0), /* Fault Protection Disabled */ ++ FAULT_SRCE_CHN_gc = (0x01<<0), /* Event Channel n */ ++ FAULT_SRCE_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ ++ FAULT_SRCE_CHN2_gc = (0x03<<0), /* Event Channel n+2 */ ++} FAULT_SRCE_t; ++ ++/* Fault A Halt Action Selection */ ++typedef enum FAULT_HALTA_enum ++{ ++ FAULT_HALTA_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ ++ FAULT_HALTA_HW_gc = (0x01<<5), /* Hardware Halt Action */ ++ FAULT_HALTA_SW_gc = (0x02<<5), /* Software Halt Action */ ++} FAULT_HALTA_t; ++ ++/* Fault A Source Selection */ ++typedef enum FAULT_SRCA_enum ++{ ++ FAULT_SRCA_DISABLE_gc = (0x00<<0), /* Fault A Disabled */ ++ FAULT_SRCA_CHN_gc = (0x01<<0), /* Event Channel n */ ++ FAULT_SRCA_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ ++ FAULT_SRCA_LINK_gc = (0x03<<0), /* Fault A linked to Fault B State from previous cycle */ ++} FAULT_SRCA_t; ++ ++/* Fault B Halt Action Selection */ ++typedef enum FAULT_HALTB_enum ++{ ++ FAULT_HALTB_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ ++ FAULT_HALTB_HW_gc = (0x01<<5), /* Hardware Halt Action */ ++ FAULT_HALTB_SW_gc = (0x02<<5), /* Software Halt Action */ ++} FAULT_HALTB_t; ++ ++/* Fault B Source Selection */ ++typedef enum FAULT_SRCB_enum ++{ ++ FAULT_SRCB_DISABLE_gc = (0x00<<0), /* Fault B disabled */ ++ FAULT_SRCB_CHN_gc = (0x01<<0), /* Event Channel n */ ++ FAULT_SRCB_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ ++ FAULT_SRCB_LINK_gc = (0x03<<0), /* Fault B linked to Fault A State from previous cycle */ ++} FAULT_SRCB_t; ++ ++/* Channel index Command */ ++typedef enum FAULT_IDXCMD_enum ++{ ++ FAULT_IDXCMD_DISABLE_gc = (0x00<<3), /* Command Disabled */ ++ FAULT_IDXCMD_SET_gc = (0x01<<3), /* Force Cycle B in Next Cycle */ ++ FAULT_IDXCMD_CLEAR_gc = (0x02<<3), /* Force Cycle A in Next Cycle */ ++ FAULT_IDXCMD_HOLD_gc = (0x03<<3), /* Hold Current Cycle Index in Next Cycle */ ++} FAULT_IDXCMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WEX - Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Waveform Extension */ ++typedef struct WEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t DTBOTH; /* Dead-time Concurrent Write to Both Sides Register */ ++ register8_t DTLS; /* Dead-time Low Side Register */ ++ register8_t DTHS; /* Dead-time High Side Register */ ++ register8_t STATUSCLR; /* Status Clear Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t SWAP; /* Swap Register */ ++ register8_t PGO; /* Pattern Generation Override Register */ ++ register8_t PGV; /* Pattern Generation Value Register */ ++ register8_t reserved_0x09; ++ register8_t SWAPBUF; /* Dead Time Low Side Buffer */ ++ register8_t PGOBUF; /* Pattern Generation Overwrite Buffer Register */ ++ register8_t PGVBUF; /* Pattern Generation Value Buffer Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t OUTOVDIS; /* Output Override Disable Register */ ++} WEX_t; ++ ++/* Output Matrix Mode */ ++typedef enum WEX_OTMX_enum ++{ ++ WEX_OTMX_DEFAULT_gc = (0x00<<4), /* Default Ouput Matrix Mode */ ++ WEX_OTMX_FIRST_gc = (0x01<<4), /* First Output matrix Mode */ ++ WEX_OTMX_SECOND_gc = (0x02<<4), /* Second Output matrix Mode */ ++ WEX_OTMX_THIRD_gc = (0x03<<4), /* Third Output matrix Mode */ ++ WEX_OTMX_FOURTH_gc = (0x04<<4), /* Fourth Output matrix Mode */ ++} WEX_OTMX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++} HIRES_t; ++ ++/* High Resolution Plus Mode */ ++typedef enum HIRES_HRPLUS_enum ++{ ++ HIRES_HRPLUS_NONE_gc = (0x00<<2), /* No Hi-Res Plus */ ++ HIRES_HRPLUS_HRP4_gc = (0x01<<2), /* Hi-Res Plus enabled on Timer 4 */ ++ HIRES_HRPLUS_HRP5_gc = (0x02<<2), /* Hi-Res Plus enabled on Timer 5 */ ++ HIRES_HRPLUS_BOTH_gc = (0x03<<2), /* Hi-Res Plus enabled on Timer 4 and 5 */ ++} HIRES_HRPLUS_t; ++ ++/* High Resolution Mode */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Hi-Res */ ++ HIRES_HREN_HRP4_gc = (0x01<<0), /* Hi-Res enabled on Timer 4 */ ++ HIRES_HREN_HRP5_gc = (0x02<<0), /* Hi-Res enabled on Timer 5 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Hi-Res enabled on Timer 4 and 5 */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Start Interrupt level */ ++typedef enum USART_RXSINTLVL_enum ++{ ++ USART_RXSINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_RXSINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_RXSINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_RXSINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_RXSINTLVL_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++/* Encoding and Decoding Type */ ++typedef enum USART_DECTYPE_enum ++{ ++ USART_DECTYPE_DATA_gc = (0x00<<4), /* DATA Field Encoding */ ++ USART_DECTYPE_SDATA_gc = (0x02<<4), /* Start and Data Fields Encoding */ ++ USART_DECTYPE_NOTSDATA_gc = (0x03<<4), /* Start and Data Fields Encoding, with invertion in START field */ ++} USART_DECTYPE_t; ++ ++/* XCL LUT Action */ ++typedef enum USART_LUTACT_enum ++{ ++ USART_LUTACT_OFF_gc = (0x00<<2), /* Standard Frame Configuration */ ++ USART_LUTACT_RX_gc = (0x01<<2), /* Receiver Decoding Enabled */ ++ USART_LUTACT_TX_gc = (0x02<<2), /* Transmitter Encoding Enabled */ ++ USART_LUTACT_BOTH_gc = (0x03<<2), /* Both Encoding and Decoding Enabled */ ++} USART_LUTACT_t; ++ ++/* XCL Peripheral Counter Action */ ++typedef enum USART_PECACT_enum ++{ ++ USART_PECACT_OFF_gc = (0x00<<0), /* Standard Mode */ ++ USART_PECACT_PEC0_gc = (0x01<<0), /* Variable Data Lenght in Reception */ ++ USART_PECACT_PEC1_gc = (0x02<<0), /* Variable Data Lenght in Transmission */ ++ USART_PECACT_PERC01_gc = (0x03<<0), /* Variable Data Lenght in both Reception and Transmission */ ++} USART_PECACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface with Buffer Modes */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t CTRLB; /* Control Register B */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0, base clock at "0", sampling on leading edge (rising) & set-up on trailling edge (falling). */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1, base clock at "0", set-up on leading edge (rising) & sampling on trailling edge (falling). */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2, base clock at "1", sampling on leading edge (falling) & set-up on trailling edge (rising). */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3, base clock at "1", set-up on leading edge (falling) & sampling on trailling edge (rising). */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* If CLK2X=1 CLKper/2, else (CLK2X=0) CLKper/4. */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* If CLK2X=1 CLKper/8, else (CLK2X=0) CLKper/16. */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* If CLK2X=1 CLKper/32, else (CLK2X=0) CLKper/64. */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* If CLK2X=1 CLKper/64, else (CLK2X=0) CLKper/128. */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++/* Buffer Modes */ ++typedef enum SPI_BUFMODE_enum ++{ ++ SPI_BUFMODE_OFF_gc = (0x00<<6), /* SPI Unbuffered Mode */ ++ SPI_BUFMODE_BUFMODE1_gc = (0x02<<6), /* Buffer Mode 1 (with dummy byte) */ ++ SPI_BUFMODE_BUFMODE2_gc = (0x03<<6), /* Buffer Mode 2 (no dummy byte) */ ++} SPI_BUFMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t reserved_0x00; ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++ register8_t FUSEBYTE6; /* Fault State */ ++} NVM_FUSES_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BOD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC8M; /* RCOSC 8MHz Calibration Value */ ++ register8_t reserved_0x01; ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t ROOMTEMP; /* Temperature corresponds to TEMPSENSE3/2 */ ++ register8_t HOTTEMP; /* Temperature corresponds to TEMPSENSE1/0 */ ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t ACACURRCAL; /* ACA Current Calibration Byte */ ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t TEMPSENSE2; /* Temperature Sensor Calibration Byte 2 */ ++ register8_t TEMPSENSE3; /* Temperature Sensor Calibration Byte 3 */ ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ ++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ ++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define EDMA (*(EDMA_t *) 0x0100) /* Enhanced DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define XCL (*(XCL_t *) 0x0460) /* XMEGA Custom Logic */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC4 (*(TC4_t *) 0x0800) /* 16-bit Timer/Counter 4 */ ++#define TCC5 (*(TC5_t *) 0x0840) /* 16-bit Timer/Counter 5 */ ++#define FAULTC4 (*(FAULT_t *) 0x0880) /* Fault Extension */ ++#define FAULTC5 (*(FAULT_t *) 0x0890) /* Fault Extension */ ++#define WEXC (*(WEX_t *) 0x08A0) /* Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x08B0) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08E0) /* Serial Peripheral Interface with Buffer Modes */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD5 (*(TC5_t *) 0x0940) /* 16-bit Timer/Counter 5 */ ++#define USARTD0 (*(USART_t *) 0x09C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++#define FUSE_FUSEBYTE6 _SFR_MEM8(0x0006) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC8M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_ROOMTEMP _SFR_MEM8(0x001E) ++#define PRODSIGNATURES_HOTTEMP _SFR_MEM8(0x001F) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_ACACURRCAL _SFR_MEM8(0x0028) ++#define PRODSIGNATURES_TEMPSENSE2 _SFR_MEM8(0x002C) ++#define PRODSIGNATURES_TEMPSENSE3 _SFR_MEM8(0x002D) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) ++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) ++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) ++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++#define OSC_RC8MCAL _SFR_MEM8(0x0057) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_WEXLOCK _SFR_MEM8(0x0099) ++#define MCU_FAULTLOCK _SFR_MEM8(0x009A) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_CLKOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_ACEVOUT _SFR_MEM8(0x00B6) ++#define PORTCFG_SRLCTRL _SFR_MEM8(0x00B7) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* EDMA - Enhanced DMA Controller */ ++#define EDMA_CTRL _SFR_MEM8(0x0100) ++#define EDMA_INTFLAGS _SFR_MEM8(0x0103) ++#define EDMA_STATUS _SFR_MEM8(0x0104) ++#define EDMA_TEMP _SFR_MEM8(0x0106) ++#define EDMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define EDMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define EDMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define EDMA_CH0_DESTADDRCTRL _SFR_MEM8(0x0113) ++#define EDMA_CH0_TRIGSRC _SFR_MEM8(0x0114) ++#define EDMA_CH0_TRFCNT _SFR_MEM16(0x0116) ++#define EDMA_CH0_ADDR _SFR_MEM16(0x0118) ++#define EDMA_CH0_DESTADDR _SFR_MEM16(0x011C) ++#define EDMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define EDMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define EDMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define EDMA_CH1_DESTADDRCTRL _SFR_MEM8(0x0123) ++#define EDMA_CH1_TRIGSRC _SFR_MEM8(0x0124) ++#define EDMA_CH1_TRFCNT _SFR_MEM16(0x0126) ++#define EDMA_CH1_ADDR _SFR_MEM16(0x0128) ++#define EDMA_CH1_DESTADDR _SFR_MEM16(0x012C) ++#define EDMA_CH2_CTRLA _SFR_MEM8(0x0130) ++#define EDMA_CH2_CTRLB _SFR_MEM8(0x0131) ++#define EDMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) ++#define EDMA_CH2_DESTADDRCTRL _SFR_MEM8(0x0133) ++#define EDMA_CH2_TRIGSRC _SFR_MEM8(0x0134) ++#define EDMA_CH2_TRFCNT _SFR_MEM16(0x0136) ++#define EDMA_CH2_ADDR _SFR_MEM16(0x0138) ++#define EDMA_CH2_DESTADDR _SFR_MEM16(0x013C) ++#define EDMA_CH3_CTRLA _SFR_MEM8(0x0140) ++#define EDMA_CH3_CTRLB _SFR_MEM8(0x0141) ++#define EDMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) ++#define EDMA_CH3_DESTADDRCTRL _SFR_MEM8(0x0143) ++#define EDMA_CH3_TRIGSRC _SFR_MEM8(0x0144) ++#define EDMA_CH3_TRFCNT _SFR_MEM16(0x0146) ++#define EDMA_CH3_ADDR _SFR_MEM16(0x0148) ++#define EDMA_CH3_DESTADDR _SFR_MEM16(0x014C) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH4MUX _SFR_MEM8(0x0184) ++#define EVSYS_CH5MUX _SFR_MEM8(0x0185) ++#define EVSYS_CH6MUX _SFR_MEM8(0x0186) ++#define EVSYS_CH7MUX _SFR_MEM8(0x0187) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) ++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) ++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) ++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++#define EVSYS_DFCTRL _SFR_MEM8(0x0192) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++#define ADCA_CH0_CORRCTRL _SFR_MEM8(0x0227) ++#define ADCA_CH0_OFFSETCORR0 _SFR_MEM8(0x0228) ++#define ADCA_CH0_OFFSETCORR1 _SFR_MEM8(0x0229) ++#define ADCA_CH0_GAINCORR0 _SFR_MEM8(0x022A) ++#define ADCA_CH0_GAINCORR1 _SFR_MEM8(0x022B) ++#define ADCA_CH0_AVGCTRL _SFR_MEM8(0x022C) ++ ++/* DAC - Digital-to-Analog Converter */ ++#define DACA_CTRLA _SFR_MEM8(0x0300) ++#define DACA_CTRLB _SFR_MEM8(0x0301) ++#define DACA_CTRLC _SFR_MEM8(0x0302) ++#define DACA_EVCTRL _SFR_MEM8(0x0303) ++#define DACA_STATUS _SFR_MEM8(0x0305) ++#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) ++#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) ++#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) ++#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) ++#define DACA_CH0DATA _SFR_MEM16(0x0318) ++#define DACA_CH1DATA _SFR_MEM16(0x031A) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++#define ACA_CURRCTRL _SFR_MEM8(0x0388) ++#define ACA_CURRCALIB _SFR_MEM8(0x0389) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CALIB _SFR_MEM8(0x0406) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* XCL - XMEGA Custom Logic */ ++#define XCL_CTRLA _SFR_MEM8(0x0460) ++#define XCL_CTRLB _SFR_MEM8(0x0461) ++#define XCL_CTRLC _SFR_MEM8(0x0462) ++#define XCL_CTRLD _SFR_MEM8(0x0463) ++#define XCL_CTRLE _SFR_MEM8(0x0464) ++#define XCL_CTRLF _SFR_MEM8(0x0465) ++#define XCL_CTRLG _SFR_MEM8(0x0466) ++#define XCL_INTCTRL _SFR_MEM8(0x0467) ++#define XCL_INTFLAGS _SFR_MEM8(0x0468) ++#define XCL_PLC _SFR_MEM8(0x0469) ++#define XCL_CNTL _SFR_MEM8(0x046A) ++#define XCL_CNTH _SFR_MEM8(0x046B) ++#define XCL_CMPL _SFR_MEM8(0x046C) ++#define XCL_CMPH _SFR_MEM8(0x046D) ++#define XCL_PERCAPTL _SFR_MEM8(0x046E) ++#define XCL_PERCAPTH _SFR_MEM8(0x046F) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++#define TWIC_TIMEOUT_TOS _SFR_MEM8(0x048E) ++#define TWIC_TIMEOUT_TOCONF _SFR_MEM8(0x048F) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INTMASK _SFR_MEM8(0x060A) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_REMAP _SFR_MEM8(0x060E) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INTMASK _SFR_MEM8(0x064A) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INTMASK _SFR_MEM8(0x066A) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INTMASK _SFR_MEM8(0x07EA) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC4 - 16-bit Timer/Counter 4 */ ++#define TCC4_CTRLA _SFR_MEM8(0x0800) ++#define TCC4_CTRLB _SFR_MEM8(0x0801) ++#define TCC4_CTRLC _SFR_MEM8(0x0802) ++#define TCC4_CTRLD _SFR_MEM8(0x0803) ++#define TCC4_CTRLE _SFR_MEM8(0x0804) ++#define TCC4_CTRLF _SFR_MEM8(0x0805) ++#define TCC4_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC4_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC4_CTRLGCLR _SFR_MEM8(0x0808) ++#define TCC4_CTRLGSET _SFR_MEM8(0x0809) ++#define TCC4_CTRLHCLR _SFR_MEM8(0x080A) ++#define TCC4_CTRLHSET _SFR_MEM8(0x080B) ++#define TCC4_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC4_TEMP _SFR_MEM8(0x080F) ++#define TCC4_CNT _SFR_MEM16(0x0820) ++#define TCC4_PER _SFR_MEM16(0x0826) ++#define TCC4_CCA _SFR_MEM16(0x0828) ++#define TCC4_CCB _SFR_MEM16(0x082A) ++#define TCC4_CCC _SFR_MEM16(0x082C) ++#define TCC4_CCD _SFR_MEM16(0x082E) ++#define TCC4_PERBUF _SFR_MEM16(0x0836) ++#define TCC4_CCABUF _SFR_MEM16(0x0838) ++#define TCC4_CCBBUF _SFR_MEM16(0x083A) ++#define TCC4_CCCBUF _SFR_MEM16(0x083C) ++#define TCC4_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC5 - 16-bit Timer/Counter 5 */ ++#define TCC5_CTRLA _SFR_MEM8(0x0840) ++#define TCC5_CTRLB _SFR_MEM8(0x0841) ++#define TCC5_CTRLC _SFR_MEM8(0x0842) ++#define TCC5_CTRLD _SFR_MEM8(0x0843) ++#define TCC5_CTRLE _SFR_MEM8(0x0844) ++#define TCC5_CTRLF _SFR_MEM8(0x0845) ++#define TCC5_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC5_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC5_CTRLGCLR _SFR_MEM8(0x0848) ++#define TCC5_CTRLGSET _SFR_MEM8(0x0849) ++#define TCC5_CTRLHCLR _SFR_MEM8(0x084A) ++#define TCC5_CTRLHSET _SFR_MEM8(0x084B) ++#define TCC5_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC5_TEMP _SFR_MEM8(0x084F) ++#define TCC5_CNT _SFR_MEM16(0x0860) ++#define TCC5_PER _SFR_MEM16(0x0866) ++#define TCC5_CCA _SFR_MEM16(0x0868) ++#define TCC5_CCB _SFR_MEM16(0x086A) ++#define TCC5_PERBUF _SFR_MEM16(0x0876) ++#define TCC5_CCABUF _SFR_MEM16(0x0878) ++#define TCC5_CCBBUF _SFR_MEM16(0x087A) ++ ++/* FAULT - Fault Extension */ ++#define FAULTC4_CTRLA _SFR_MEM8(0x0880) ++#define FAULTC4_CTRLB _SFR_MEM8(0x0881) ++#define FAULTC4_CTRLC _SFR_MEM8(0x0882) ++#define FAULTC4_CTRLD _SFR_MEM8(0x0883) ++#define FAULTC4_CTRLE _SFR_MEM8(0x0884) ++#define FAULTC4_STATUS _SFR_MEM8(0x0885) ++#define FAULTC4_CTRLGCLR _SFR_MEM8(0x0886) ++#define FAULTC4_CTRLGSET _SFR_MEM8(0x0887) ++ ++/* FAULT - Fault Extension */ ++#define FAULTC5_CTRLA _SFR_MEM8(0x0890) ++#define FAULTC5_CTRLB _SFR_MEM8(0x0891) ++#define FAULTC5_CTRLC _SFR_MEM8(0x0892) ++#define FAULTC5_CTRLD _SFR_MEM8(0x0893) ++#define FAULTC5_CTRLE _SFR_MEM8(0x0894) ++#define FAULTC5_STATUS _SFR_MEM8(0x0895) ++#define FAULTC5_CTRLGCLR _SFR_MEM8(0x0896) ++#define FAULTC5_CTRLGSET _SFR_MEM8(0x0897) ++ ++/* WEX - Waveform Extension */ ++#define WEXC_CTRL _SFR_MEM8(0x08A0) ++#define WEXC_DTBOTH _SFR_MEM8(0x08A1) ++#define WEXC_DTLS _SFR_MEM8(0x08A2) ++#define WEXC_DTHS _SFR_MEM8(0x08A3) ++#define WEXC_STATUSCLR _SFR_MEM8(0x08A4) ++#define WEXC_STATUSSET _SFR_MEM8(0x08A5) ++#define WEXC_SWAP _SFR_MEM8(0x08A6) ++#define WEXC_PGO _SFR_MEM8(0x08A7) ++#define WEXC_PGV _SFR_MEM8(0x08A8) ++#define WEXC_SWAPBUF _SFR_MEM8(0x08AA) ++#define WEXC_PGOBUF _SFR_MEM8(0x08AB) ++#define WEXC_PGVBUF _SFR_MEM8(0x08AC) ++#define WEXC_OUTOVDIS _SFR_MEM8(0x08AF) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x08B0) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08C0) ++#define USARTC0_STATUS _SFR_MEM8(0x08C1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08C2) ++#define USARTC0_CTRLB _SFR_MEM8(0x08C3) ++#define USARTC0_CTRLC _SFR_MEM8(0x08C4) ++#define USARTC0_CTRLD _SFR_MEM8(0x08C5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08C6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08C7) ++ ++/* SPI - Serial Peripheral Interface with Buffer Modes */ ++#define SPIC_CTRL _SFR_MEM8(0x08E0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08E1) ++#define SPIC_STATUS _SFR_MEM8(0x08E2) ++#define SPIC_DATA _SFR_MEM8(0x08E3) ++#define SPIC_CTRLB _SFR_MEM8(0x08E4) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC5 - 16-bit Timer/Counter 5 */ ++#define TCD5_CTRLA _SFR_MEM8(0x0940) ++#define TCD5_CTRLB _SFR_MEM8(0x0941) ++#define TCD5_CTRLC _SFR_MEM8(0x0942) ++#define TCD5_CTRLD _SFR_MEM8(0x0943) ++#define TCD5_CTRLE _SFR_MEM8(0x0944) ++#define TCD5_CTRLF _SFR_MEM8(0x0945) ++#define TCD5_INTCTRLA _SFR_MEM8(0x0946) ++#define TCD5_INTCTRLB _SFR_MEM8(0x0947) ++#define TCD5_CTRLGCLR _SFR_MEM8(0x0948) ++#define TCD5_CTRLGSET _SFR_MEM8(0x0949) ++#define TCD5_CTRLHCLR _SFR_MEM8(0x094A) ++#define TCD5_CTRLHSET _SFR_MEM8(0x094B) ++#define TCD5_INTFLAGS _SFR_MEM8(0x094C) ++#define TCD5_TEMP _SFR_MEM8(0x094F) ++#define TCD5_CNT _SFR_MEM16(0x0960) ++#define TCD5_PER _SFR_MEM16(0x0966) ++#define TCD5_CCA _SFR_MEM16(0x0968) ++#define TCD5_CCB _SFR_MEM16(0x096A) ++#define TCD5_PERBUF _SFR_MEM16(0x0976) ++#define TCD5_CCABUF _SFR_MEM16(0x0978) ++#define TCD5_CCBBUF _SFR_MEM16(0x097A) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD0_DATA _SFR_MEM8(0x09C0) ++#define USARTD0_STATUS _SFR_MEM8(0x09C1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09C2) ++#define USARTD0_CTRLB _SFR_MEM8(0x09C3) ++#define USARTD0_CTRLC _SFR_MEM8(0x09C4) ++#define USARTD0_CTRLD _SFR_MEM8(0x09C5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09C6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09C7) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT7IF_bm 0x80 /* Interrupt Pin 7 Flag bit mask. */ ++#define VPORT_INT7IF_bp 7 /* Interrupt Pin 7 Flag bit position. */ ++ ++#define VPORT_INT6IF_bm 0x40 /* Interrupt Pin 6 Flag bit mask. */ ++#define VPORT_INT6IF_bp 6 /* Interrupt Pin 6 Flag bit position. */ ++ ++#define VPORT_INT5IF_bm 0x20 /* Interrupt Pin 5 Flag bit mask. */ ++#define VPORT_INT5IF_bp 5 /* Interrupt Pin 5 Flag bit position. */ ++ ++#define VPORT_INT4IF_bm 0x10 /* Interrupt Pin 4 Flag bit mask. */ ++#define VPORT_INT4IF_bp 4 /* Interrupt Pin 4 Flag bit position. */ ++ ++#define VPORT_INT3IF_bm 0x08 /* Interrupt Pin 3 Flag bit mask. */ ++#define VPORT_INT3IF_bp 3 /* Interrupt Pin 3 Flag bit position. */ ++ ++#define VPORT_INT2IF_bm 0x04 /* Interrupt Pin 2 Flag bit mask. */ ++#define VPORT_INT2IF_bp 2 /* Interrupt Pin 2 Flag bit position. */ ++ ++#define VPORT_INT1IF_bm 0x02 /* Interrupt Pin 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Interrupt Pin 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Interrupt Pin 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Interrupt Pin 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_XCL_bm 0x80 /* XMEGA Custom Logic bit mask. */ ++#define PR_XCL_bp 7 /* XMEGA Custom Logic bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_EDMA_bm 0x01 /* Enhanced DMA-Controller bit mask. */ ++#define PR_EDMA_bp 0 /* Enhanced DMA-Controller bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ ++#define PR_DAC_bp 2 /* Port A DAC bit position. */ ++ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C WEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C WEX bit position. */ ++ ++#define PR_TC5_bm 0x02 /* Port C Timer/Counter5 bit mask. */ ++#define PR_TC5_bp 1 /* Port C Timer/Counter5 bit position. */ ++ ++#define PR_TC4_bm 0x01 /* Port C Timer/Counter4 bit mask. */ ++#define PR_TC4_bp 0 /* Port C Timer/Counter4 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC5 Predefined. */ ++/* PR_TC5 Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_RC8MLPM_bm 0x40 /* Internal 8 MHz RC Low Power Mode Enable bit mask. */ ++#define OSC_RC8MLPM_bp 6 /* Internal 8 MHz RC Low Power Mode Enable bit position. */ ++ ++#define OSC_RC8MEN_bm 0x20 /* Internal 8 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC8MEN_bp 5 /* Internal 8 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_RC8MRDY_bm 0x20 /* Internal 8 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC8MRDY_bp 5 /* Internal 8 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ ++#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++/* OSC.RC8MCAL bit masks and bit positions */ ++#define OSC_RC8MCAL_gm 0xFF /* Calibration Bits group mask. */ ++#define OSC_RC8MCAL_gp 0 /* Calibration Bits group position. */ ++#define OSC_RC8MCAL0_bm (1<<0) /* Calibration Bits bit 0 mask. */ ++#define OSC_RC8MCAL0_bp 0 /* Calibration Bits bit 0 position. */ ++#define OSC_RC8MCAL1_bm (1<<1) /* Calibration Bits bit 1 mask. */ ++#define OSC_RC8MCAL1_bp 1 /* Calibration Bits bit 1 position. */ ++#define OSC_RC8MCAL2_bm (1<<2) /* Calibration Bits bit 2 mask. */ ++#define OSC_RC8MCAL2_bp 2 /* Calibration Bits bit 2 position. */ ++#define OSC_RC8MCAL3_bm (1<<3) /* Calibration Bits bit 3 mask. */ ++#define OSC_RC8MCAL3_bp 3 /* Calibration Bits bit 3 position. */ ++#define OSC_RC8MCAL4_bm (1<<4) /* Calibration Bits bit 4 mask. */ ++#define OSC_RC8MCAL4_bp 4 /* Calibration Bits bit 4 position. */ ++#define OSC_RC8MCAL5_bm (1<<5) /* Calibration Bits bit 5 mask. */ ++#define OSC_RC8MCAL5_bp 5 /* Calibration Bits bit 5 position. */ ++#define OSC_RC8MCAL6_bm (1<<6) /* Calibration Bits bit 6 mask. */ ++#define OSC_RC8MCAL6_bp 6 /* Calibration Bits bit 6 position. */ ++#define OSC_RC8MCAL7_bm (1<<7) /* Calibration Bits bit 7 mask. */ ++#define OSC_RC8MCAL7_bp 7 /* Calibration Bits bit 7 position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.WEXLOCK bit masks and bit positions */ ++#define MCU_WEXCLOCK_bm 0x01 /* WeX on T/C C4 Lock bit mask. */ ++#define MCU_WEXCLOCK_bp 0 /* WeX on T/C C4 Lock bit position. */ ++ ++/* MCU.FAULTLOCK bit masks and bit positions */ ++#define MCU_FAULTC5LOCK_bm 0x02 /* Fault on T/C C5 Lock bit mask. */ ++#define MCU_FAULTC5LOCK_bp 1 /* Fault on T/C C5 Lock bit position. */ ++ ++#define MCU_FAULTC4LOCK_bm 0x01 /* Fault on T/C C4 Lock bit mask. */ ++#define MCU_FAULTC4LOCK_bp 0 /* Fault on T/C C4 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.CLKOUT bit masks and bit positions */ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Clock and Event Output Pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Clock and Event Output Pin Select bit position. */ ++ ++#define PORTCFG_RTCOUT_gm 0x60 /* RTC Clock Output Enable group mask. */ ++#define PORTCFG_RTCOUT_gp 5 /* RTC Clock Output Enable group position. */ ++#define PORTCFG_RTCOUT0_bm (1<<5) /* RTC Clock Output Enable bit 0 mask. */ ++#define PORTCFG_RTCOUT0_bp 5 /* RTC Clock Output Enable bit 0 position. */ ++#define PORTCFG_RTCOUT1_bm (1<<6) /* RTC Clock Output Enable bit 1 mask. */ ++#define PORTCFG_RTCOUT1_bp 6 /* RTC Clock Output Enable bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ ++ ++/* PORTCFG.ACEVOUT bit masks and bit positions */ ++#define PORTCFG_ACOUT_gm 0xC0 /* Analog Comparator Output Port group mask. */ ++#define PORTCFG_ACOUT_gp 6 /* Analog Comparator Output Port group position. */ ++#define PORTCFG_ACOUT0_bm (1<<6) /* Analog Comparator Output Port bit 0 mask. */ ++#define PORTCFG_ACOUT0_bp 6 /* Analog Comparator Output Port bit 0 position. */ ++#define PORTCFG_ACOUT1_bm (1<<7) /* Analog Comparator Output Port bit 1 mask. */ ++#define PORTCFG_ACOUT1_bp 7 /* Analog Comparator Output Port bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Channel Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Channel Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Channel Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Channel Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Channel Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Channel Output Port bit 1 position. */ ++ ++#define PORTCFG_EVASYEN_bm 0x08 /* Asynchronous Event Enabled bit mask. */ ++#define PORTCFG_EVASYEN_bp 3 /* Asynchronous Event Enabled bit position. */ ++ ++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Channel Output Selection group mask. */ ++#define PORTCFG_EVOUTSEL_gp 0 /* Event Channel Output Selection group position. */ ++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Channel Output Selection bit 0 mask. */ ++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Channel Output Selection bit 0 position. */ ++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Channel Output Selection bit 1 mask. */ ++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Channel Output Selection bit 1 position. */ ++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Channel Output Selection bit 2 mask. */ ++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Channel Output Selection bit 2 position. */ ++ ++/* PORTCFG.SRLCTRL bit masks and bit positions */ ++#define PORTCFG_SRLENRA_bm 0x01 /* Slew Rate Limit Enable on PORTA bit mask. */ ++#define PORTCFG_SRLENRA_bp 0 /* Slew Rate Limit Enable on PORTA bit position. */ ++ ++#define PORTCFG_SRLENRC_bm 0x04 /* Slew Rate Limit Enable on PORTC bit mask. */ ++#define PORTCFG_SRLENRC_bp 2 /* Slew Rate Limit Enable on PORTC bit position. */ ++ ++#define PORTCFG_SRLENRD_bm 0x08 /* Slew Rate Limit Enable on PORTD bit mask. */ ++#define PORTCFG_SRLENRD_bp 3 /* Slew Rate Limit Enable on PORTD bit position. */ ++ ++#define PORTCFG_SRLENRR_bm 0x80 /* Slew Rate Limit Enable on PORTR bit mask. */ ++#define PORTCFG_SRLENRR_bp 7 /* Slew Rate Limit Enable on PORTR bit position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* EDMA - Enhanced DMA Controller */ ++/* EDMA.CTRL bit masks and bit positions */ ++#define EDMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define EDMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define EDMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define EDMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define EDMA_CHMODE_gm 0x30 /* Channel Mode group mask. */ ++#define EDMA_CHMODE_gp 4 /* Channel Mode group position. */ ++#define EDMA_CHMODE0_bm (1<<4) /* Channel Mode bit 0 mask. */ ++#define EDMA_CHMODE0_bp 4 /* Channel Mode bit 0 position. */ ++#define EDMA_CHMODE1_bm (1<<5) /* Channel Mode bit 1 mask. */ ++#define EDMA_CHMODE1_bp 5 /* Channel Mode bit 1 position. */ ++ ++#define EDMA_DBUFMODE_gm 0x0C /* Double Buffer Mode group mask. */ ++#define EDMA_DBUFMODE_gp 2 /* Double Buffer Mode group position. */ ++#define EDMA_DBUFMODE0_bm (1<<2) /* Double Buffer Mode bit 0 mask. */ ++#define EDMA_DBUFMODE0_bp 2 /* Double Buffer Mode bit 0 position. */ ++#define EDMA_DBUFMODE1_bm (1<<3) /* Double Buffer Mode bit 1 mask. */ ++#define EDMA_DBUFMODE1_bp 3 /* Double Buffer Mode bit 1 position. */ ++ ++#define EDMA_PRIMODE_gm 0x03 /* Priority Mode group mask. */ ++#define EDMA_PRIMODE_gp 0 /* Priority Mode group position. */ ++#define EDMA_PRIMODE0_bm (1<<0) /* Priority Mode bit 0 mask. */ ++#define EDMA_PRIMODE0_bp 0 /* Priority Mode bit 0 position. */ ++#define EDMA_PRIMODE1_bm (1<<1) /* Priority Mode bit 1 mask. */ ++#define EDMA_PRIMODE1_bp 1 /* Priority Mode bit 1 position. */ ++ ++/* EDMA.INTFLAGS bit masks and bit positions */ ++#define EDMA_CH3ERRIF_bm 0x80 /* Channel 3 Transaction Error Interrupt Flag bit mask. */ ++#define EDMA_CH3ERRIF_bp 7 /* Channel 3 Transaction Error Interrupt Flag bit position. */ ++ ++#define EDMA_CH2ERRIF_bm 0x40 /* Channel 2 Transaction Error Interrupt Flag bit mask. */ ++#define EDMA_CH2ERRIF_bp 6 /* Channel 2 Transaction Error Interrupt Flag bit position. */ ++ ++#define EDMA_CH1ERRIF_bm 0x20 /* Channel 1 Transaction Error Interrupt Flag bit mask. */ ++#define EDMA_CH1ERRIF_bp 5 /* Channel 1 Transaction Error Interrupt Flag bit position. */ ++ ++#define EDMA_CH0ERRIF_bm 0x10 /* Channel 0 Transaction Error Interrupt Flag bit mask. */ ++#define EDMA_CH0ERRIF_bp 4 /* Channel 0 Transaction Error Interrupt Flag bit position. */ ++ ++#define EDMA_CH3TRNFIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ ++#define EDMA_CH3TRNFIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ ++ ++#define EDMA_CH2TRNFIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ ++#define EDMA_CH2TRNFIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ ++ ++#define EDMA_CH1TRNFIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define EDMA_CH1TRNFIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define EDMA_CH0TRNFIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define EDMA_CH0TRNFIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++/* EDMA.STATUS bit masks and bit positions */ ++#define EDMA_CH3BUSY_bm 0x80 /* Channel 3 Busy Flag bit mask. */ ++#define EDMA_CH3BUSY_bp 7 /* Channel 3 Busy Flag bit position. */ ++ ++#define EDMA_CH2BUSY_bm 0x40 /* Channel 2 Busy Flag bit mask. */ ++#define EDMA_CH2BUSY_bp 6 /* Channel 2 Busy Flag bit position. */ ++ ++#define EDMA_CH1BUSY_bm 0x20 /* Channel 1 Busy Flag bit mask. */ ++#define EDMA_CH1BUSY_bp 5 /* Channel 1 Busy Flag bit position. */ ++ ++#define EDMA_CH0BUSY_bm 0x10 /* Channel 0 Busy Flag bit mask. */ ++#define EDMA_CH0BUSY_bp 4 /* Channel 0 Busy Flag bit position. */ ++ ++#define EDMA_CH3PEND_bm 0x08 /* Channel 3 Pending Flag bit mask. */ ++#define EDMA_CH3PEND_bp 3 /* Channel 3 Pending Flag bit position. */ ++ ++#define EDMA_CH2PEND_bm 0x04 /* Channel 2 Pending Flag bit mask. */ ++#define EDMA_CH2PEND_bp 2 /* Channel 2 Pending Flag bit position. */ ++ ++#define EDMA_CH1PEND_bm 0x02 /* Channel 1 Pending Flag bit mask. */ ++#define EDMA_CH1PEND_bp 1 /* Channel 1 Pending Flag bit position. */ ++ ++#define EDMA_CH0PEND_bm 0x01 /* Channel 0 Pending Flag bit mask. */ ++#define EDMA_CH0PEND_bp 0 /* Channel 0 Pending Flag bit position. */ ++ ++/* EDMA_CH.CTRLA bit masks and bit positions */ ++#define EDMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ ++#define EDMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ ++ ++#define EDMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ ++#define EDMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ ++ ++#define EDMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define EDMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define EDMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define EDMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define EDMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define EDMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define EDMA_CH_BURSTLEN_bm 0x01 /* Channel 2-bytes Burst Length bit mask. */ ++#define EDMA_CH_BURSTLEN_bp 0 /* Channel 2-bytes Burst Length bit position. */ ++ ++/* EDMA_CH.CTRLB bit masks and bit positions */ ++#define EDMA_CH_CHBUSY_bm 0x80 /* Channel Block Transfer Busy bit mask. */ ++#define EDMA_CH_CHBUSY_bp 7 /* Channel Block Transfer Busy bit position. */ ++ ++#define EDMA_CH_CHPEND_bm 0x40 /* Channel Block Transfer Pending bit mask. */ ++#define EDMA_CH_CHPEND_bp 6 /* Channel Block Transfer Pending bit position. */ ++ ++#define EDMA_CH_ERRIF_bm 0x20 /* Channel Transaction Error Interrupt Flag bit mask. */ ++#define EDMA_CH_ERRIF_bp 5 /* Channel Transaction Error Interrupt Flag bit position. */ ++ ++#define EDMA_CH_TRNIF_bm 0x10 /* Channel Transaction Complete Interrup Flag bit mask. */ ++#define EDMA_CH_TRNIF_bp 4 /* Channel Transaction Complete Interrup Flag bit position. */ ++ ++#define EDMA_CH_ERRINTLVL_gm 0x0C /* Channel Transaction Error Interrupt Level group mask. */ ++#define EDMA_CH_ERRINTLVL_gp 2 /* Channel Transaction Error Interrupt Level group position. */ ++#define EDMA_CH_ERRINTLVL0_bm (1<<2) /* Channel Transaction Error Interrupt Level bit 0 mask. */ ++#define EDMA_CH_ERRINTLVL0_bp 2 /* Channel Transaction Error Interrupt Level bit 0 position. */ ++#define EDMA_CH_ERRINTLVL1_bm (1<<3) /* Channel Transaction Error Interrupt Level bit 1 mask. */ ++#define EDMA_CH_ERRINTLVL1_bp 3 /* Channel Transaction Error Interrupt Level bit 1 position. */ ++ ++#define EDMA_CH_TRNINTLVL_gm 0x03 /* Channel Transaction Complete Interrupt Level group mask. */ ++#define EDMA_CH_TRNINTLVL_gp 0 /* Channel Transaction Complete Interrupt Level group position. */ ++#define EDMA_CH_TRNINTLVL0_bm (1<<0) /* Channel Transaction Complete Interrupt Level bit 0 mask. */ ++#define EDMA_CH_TRNINTLVL0_bp 0 /* Channel Transaction Complete Interrupt Level bit 0 position. */ ++#define EDMA_CH_TRNINTLVL1_bm (1<<1) /* Channel Transaction Complete Interrupt Level bit 1 mask. */ ++#define EDMA_CH_TRNINTLVL1_bp 1 /* Channel Transaction Complete Interrupt Level bit 1 position. */ ++ ++/* EDMA_CH.ADDRCTRL bit masks and bit positions */ ++#define EDMA_CH_RELOAD_gm 0x30 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group mask. */ ++#define EDMA_CH_RELOAD_gp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group position. */ ++#define EDMA_CH_RELOAD0_bm (1<<4) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 mask. */ ++#define EDMA_CH_RELOAD0_bp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 position. */ ++#define EDMA_CH_RELOAD1_bm (1<<5) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 mask. */ ++#define EDMA_CH_RELOAD1_bp 5 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 position. */ ++ ++#define EDMA_CH_DIR_gm 0x07 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group mask. */ ++#define EDMA_CH_DIR_gp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group position. */ ++#define EDMA_CH_DIR0_bm (1<<0) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 mask. */ ++#define EDMA_CH_DIR0_bp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 position. */ ++#define EDMA_CH_DIR1_bm (1<<1) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 mask. */ ++#define EDMA_CH_DIR1_bp 1 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 position. */ ++#define EDMA_CH_DIR2_bm (1<<2) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 mask. */ ++#define EDMA_CH_DIR2_bp 2 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 position. */ ++ ++/* EDMA_CH.DESTADDRCTRL bit masks and bit positions */ ++#define EDMA_CH_DESTRELOAD_gm 0x30 /* Destination Address Reload for Standard Channels Only. group mask. */ ++#define EDMA_CH_DESTRELOAD_gp 4 /* Destination Address Reload for Standard Channels Only. group position. */ ++#define EDMA_CH_DESTRELOAD0_bm (1<<4) /* Destination Address Reload for Standard Channels Only. bit 0 mask. */ ++#define EDMA_CH_DESTRELOAD0_bp 4 /* Destination Address Reload for Standard Channels Only. bit 0 position. */ ++#define EDMA_CH_DESTRELOAD1_bm (1<<5) /* Destination Address Reload for Standard Channels Only. bit 1 mask. */ ++#define EDMA_CH_DESTRELOAD1_bp 5 /* Destination Address Reload for Standard Channels Only. bit 1 position. */ ++ ++#define EDMA_CH_DESTDIR_gm 0x07 /* Destination Address Mode for Standard Channels Only. group mask. */ ++#define EDMA_CH_DESTDIR_gp 0 /* Destination Address Mode for Standard Channels Only. group position. */ ++#define EDMA_CH_DESTDIR0_bm (1<<0) /* Destination Address Mode for Standard Channels Only. bit 0 mask. */ ++#define EDMA_CH_DESTDIR0_bp 0 /* Destination Address Mode for Standard Channels Only. bit 0 position. */ ++#define EDMA_CH_DESTDIR1_bm (1<<1) /* Destination Address Mode for Standard Channels Only. bit 1 mask. */ ++#define EDMA_CH_DESTDIR1_bp 1 /* Destination Address Mode for Standard Channels Only. bit 1 position. */ ++#define EDMA_CH_DESTDIR2_bm (1<<2) /* Destination Address Mode for Standard Channels Only. bit 2 mask. */ ++#define EDMA_CH_DESTDIR2_bp 2 /* Destination Address Mode for Standard Channels Only. bit 2 position. */ ++ ++/* EDMA_CH.TRIGSRC bit masks and bit positions */ ++#define EDMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define EDMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define EDMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define EDMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define EDMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define EDMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define EDMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define EDMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define EDMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define EDMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define EDMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define EDMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define EDMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define EDMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define EDMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define EDMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define EDMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define EDMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH4MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH5MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH6MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH7MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_ROTARY_bm 0x80 /* Rotary Decoder Enable bit mask. */ ++#define EVSYS_ROTARY_bp 7 /* Rotary Decoder Enable bit position. */ ++ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH4CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH5CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH6CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH7CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.DFCTRL bit masks and bit positions */ ++#define EVSYS_PRESCFILT_gm 0xF0 /* Prescaler Filter group mask. */ ++#define EVSYS_PRESCFILT_gp 4 /* Prescaler Filter group position. */ ++#define EVSYS_PRESCFILT0_bm (1<<4) /* Prescaler Filter bit 0 mask. */ ++#define EVSYS_PRESCFILT0_bp 4 /* Prescaler Filter bit 0 position. */ ++#define EVSYS_PRESCFILT1_bm (1<<5) /* Prescaler Filter bit 1 mask. */ ++#define EVSYS_PRESCFILT1_bp 5 /* Prescaler Filter bit 1 position. */ ++#define EVSYS_PRESCFILT2_bm (1<<6) /* Prescaler Filter bit 2 mask. */ ++#define EVSYS_PRESCFILT2_bp 6 /* Prescaler Filter bit 2 position. */ ++#define EVSYS_PRESCFILT3_bm (1<<7) /* Prescaler Filter bit 3 mask. */ ++#define EVSYS_PRESCFILT3_bp 7 /* Prescaler Filter bit 3 position. */ ++ ++#define EVSYS_FILTSEL_bm 0x08 /* Prescaler Filter Select bit mask. */ ++#define EVSYS_FILTSEL_bp 3 /* Prescaler Filter Select bit position. */ ++ ++#define EVSYS_PRESC_gm 0x07 /* Prescaler group mask. */ ++#define EVSYS_PRESC_gp 0 /* Prescaler group position. */ ++#define EVSYS_PRESC0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define EVSYS_PRESC0_bp 0 /* Prescaler bit 0 position. */ ++#define EVSYS_PRESC1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define EVSYS_PRESC1_bp 1 /* Prescaler bit 1 position. */ ++#define EVSYS_PRESC2_bm (1<<2) /* Prescaler bit 2 mask. */ ++#define EVSYS_PRESC2_bp 2 /* Prescaler bit 2 position. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC Input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC Input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC Input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC Input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC Input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC Input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC Input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC Input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC Input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC Input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC Input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC Input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC Input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC Input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC Input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC Input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC Input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC Input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC Input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC Input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC Input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC Input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC Input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC Input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC Input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC Input bit 1 position. */ ++ ++#define ADC_CH_MUXNEGL_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group mask. */ ++#define ADC_CH_MUXNEGL_gp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group position. */ ++#define ADC_CH_MUXNEGL0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 mask. */ ++#define ADC_CH_MUXNEGL0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 position. */ ++#define ADC_CH_MUXNEGL1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 mask. */ ++#define ADC_CH_MUXNEGL1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 position. */ ++ ++#define ADC_CH_MUXNEGH_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group mask. */ ++#define ADC_CH_MUXNEGH_gp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group position. */ ++#define ADC_CH_MUXNEGH0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 mask. */ ++#define ADC_CH_MUXNEGH0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 position. */ ++#define ADC_CH_MUXNEGH1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 mask. */ ++#define ADC_CH_MUXNEGH1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_IF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_IF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_INPUTOFFSET_gm 0xF0 /* Positive MUX Setting Offset group mask. */ ++#define ADC_CH_INPUTOFFSET_gp 4 /* Positive MUX Setting Offset group position. */ ++#define ADC_CH_INPUTOFFSET0_bm (1<<4) /* Positive MUX Setting Offset bit 0 mask. */ ++#define ADC_CH_INPUTOFFSET0_bp 4 /* Positive MUX Setting Offset bit 0 position. */ ++#define ADC_CH_INPUTOFFSET1_bm (1<<5) /* Positive MUX Setting Offset bit 1 mask. */ ++#define ADC_CH_INPUTOFFSET1_bp 5 /* Positive MUX Setting Offset bit 1 position. */ ++#define ADC_CH_INPUTOFFSET2_bm (1<<6) /* Positive MUX Setting Offset bit 2 mask. */ ++#define ADC_CH_INPUTOFFSET2_bp 6 /* Positive MUX Setting Offset bit 2 position. */ ++#define ADC_CH_INPUTOFFSET3_bm (1<<7) /* Positive MUX Setting Offset bit 3 mask. */ ++#define ADC_CH_INPUTOFFSET3_bp 7 /* Positive MUX Setting Offset bit 3 position. */ ++ ++#define ADC_CH_INPUTSCAN_gm 0x0F /* Number of Channels Included in Scan group mask. */ ++#define ADC_CH_INPUTSCAN_gp 0 /* Number of Channels Included in Scan group position. */ ++#define ADC_CH_INPUTSCAN0_bm (1<<0) /* Number of Channels Included in Scan bit 0 mask. */ ++#define ADC_CH_INPUTSCAN0_bp 0 /* Number of Channels Included in Scan bit 0 position. */ ++#define ADC_CH_INPUTSCAN1_bm (1<<1) /* Number of Channels Included in Scan bit 1 mask. */ ++#define ADC_CH_INPUTSCAN1_bp 1 /* Number of Channels Included in Scan bit 1 position. */ ++#define ADC_CH_INPUTSCAN2_bm (1<<2) /* Number of Channels Included in Scan bit 2 mask. */ ++#define ADC_CH_INPUTSCAN2_bp 2 /* Number of Channels Included in Scan bit 2 position. */ ++#define ADC_CH_INPUTSCAN3_bm (1<<3) /* Number of Channels Included in Scan bit 3 mask. */ ++#define ADC_CH_INPUTSCAN3_bp 3 /* Number of Channels Included in Scan bit 3 position. */ ++ ++/* ADC_CH.CORRCTRL bit masks and bit positions */ ++#define ADC_CH_CORREN_bm 0x01 /* Correction Enable bit mask. */ ++#define ADC_CH_CORREN_bp 0 /* Correction Enable bit position. */ ++ ++/* ADC_CH.OFFSETCORR1 bit masks and bit positions */ ++#define ADC_CH_OFFSETCORR_gm 0x0F /* Offset Correction Byte 1 group mask. */ ++#define ADC_CH_OFFSETCORR_gp 0 /* Offset Correction Byte 1 group position. */ ++#define ADC_CH_OFFSETCORR0_bm (1<<0) /* Offset Correction Byte 1 bit 0 mask. */ ++#define ADC_CH_OFFSETCORR0_bp 0 /* Offset Correction Byte 1 bit 0 position. */ ++#define ADC_CH_OFFSETCORR1_bm (1<<1) /* Offset Correction Byte 1 bit 1 mask. */ ++#define ADC_CH_OFFSETCORR1_bp 1 /* Offset Correction Byte 1 bit 1 position. */ ++#define ADC_CH_OFFSETCORR2_bm (1<<2) /* Offset Correction Byte 1 bit 2 mask. */ ++#define ADC_CH_OFFSETCORR2_bp 2 /* Offset Correction Byte 1 bit 2 position. */ ++#define ADC_CH_OFFSETCORR3_bm (1<<3) /* Offset Correction Byte 1 bit 3 mask. */ ++#define ADC_CH_OFFSETCORR3_bp 3 /* Offset Correction Byte 1 bit 3 position. */ ++ ++/* ADC_CH.GAINCORR1 bit masks and bit positions */ ++#define ADC_CH_GAINCORR_gm 0x0F /* Gain Correction Byte 1 group mask. */ ++#define ADC_CH_GAINCORR_gp 0 /* Gain Correction Byte 1 group position. */ ++#define ADC_CH_GAINCORR0_bm (1<<0) /* Gain Correction Byte 1 bit 0 mask. */ ++#define ADC_CH_GAINCORR0_bp 0 /* Gain Correction Byte 1 bit 0 position. */ ++#define ADC_CH_GAINCORR1_bm (1<<1) /* Gain Correction Byte 1 bit 1 mask. */ ++#define ADC_CH_GAINCORR1_bp 1 /* Gain Correction Byte 1 bit 1 position. */ ++#define ADC_CH_GAINCORR2_bm (1<<2) /* Gain Correction Byte 1 bit 2 mask. */ ++#define ADC_CH_GAINCORR2_bp 2 /* Gain Correction Byte 1 bit 2 position. */ ++#define ADC_CH_GAINCORR3_bm (1<<3) /* Gain Correction Byte 1 bit 3 mask. */ ++#define ADC_CH_GAINCORR3_bp 3 /* Gain Correction Byte 1 bit 3 position. */ ++ ++/* ADC_CH.AVGCTRL bit masks and bit positions */ ++#define ADC_CH_RIGHTSHIFT_gm 0x70 /* Right Shift group mask. */ ++#define ADC_CH_RIGHTSHIFT_gp 4 /* Right Shift group position. */ ++#define ADC_CH_RIGHTSHIFT0_bm (1<<4) /* Right Shift bit 0 mask. */ ++#define ADC_CH_RIGHTSHIFT0_bp 4 /* Right Shift bit 0 position. */ ++#define ADC_CH_RIGHTSHIFT1_bm (1<<5) /* Right Shift bit 1 mask. */ ++#define ADC_CH_RIGHTSHIFT1_bp 5 /* Right Shift bit 1 position. */ ++#define ADC_CH_RIGHTSHIFT2_bm (1<<6) /* Right Shift bit 2 mask. */ ++#define ADC_CH_RIGHTSHIFT2_bp 6 /* Right Shift bit 2 position. */ ++ ++#define ADC_CH_SAMPNUM_gm 0x0F /* Averaged Number of Samples group mask. */ ++#define ADC_CH_SAMPNUM_gp 0 /* Averaged Number of Samples group position. */ ++#define ADC_CH_SAMPNUM0_bm (1<<0) /* Averaged Number of Samples bit 0 mask. */ ++#define ADC_CH_SAMPNUM0_bp 0 /* Averaged Number of Samples bit 0 position. */ ++#define ADC_CH_SAMPNUM1_bm (1<<1) /* Averaged Number of Samples bit 1 mask. */ ++#define ADC_CH_SAMPNUM1_bp 1 /* Averaged Number of Samples bit 1 position. */ ++#define ADC_CH_SAMPNUM2_bm (1<<2) /* Averaged Number of Samples bit 2 mask. */ ++#define ADC_CH_SAMPNUM2_bp 2 /* Averaged Number of Samples bit 2 position. */ ++#define ADC_CH_SAMPNUM3_bm (1<<3) /* Averaged Number of Samples bit 3 mask. */ ++#define ADC_CH_SAMPNUM3_bp 3 /* Averaged Number of Samples bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_START_bm 0x04 /* Start Conversion bit mask. */ ++#define ADC_START_bp 2 /* Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ ++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* ADC.SAMPCTRL bit masks and bit positions */ ++#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ ++#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ ++#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ ++#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ ++#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ ++#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ ++#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ ++#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ ++#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ ++#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ ++#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ ++#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ ++#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ ++#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ ++ ++/* DAC - Digital/Analog Converter */ ++/* DAC.CTRLA bit masks and bit positions */ ++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ ++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ ++ ++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ ++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ ++ ++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ ++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ ++ ++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ ++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ ++ ++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define DAC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* DAC.CTRLB bit masks and bit positions */ ++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ ++#define DAC_CHSEL_gp 5 /* Channel Select group position. */ ++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ ++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ ++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ ++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ ++ ++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ ++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ ++ ++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ ++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ ++ ++/* DAC.CTRLC bit masks and bit positions */ ++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ ++#define DAC_REFSEL_gp 3 /* Reference Select group position. */ ++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ ++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ ++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ ++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ ++ ++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ ++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ ++ ++/* DAC.EVCTRL bit masks and bit positions */ ++#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ ++#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ ++ ++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ ++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ ++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ ++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ ++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ ++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ ++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ ++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ ++ ++/* DAC.STATUS bit masks and bit positions */ ++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ ++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ ++ ++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ ++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ ++ ++/* DAC.CH0GAINCAL bit masks and bit positions */ ++#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH0OFFSETCAL bit masks and bit positions */ ++#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* DAC.CH1GAINCAL bit masks and bit positions */ ++#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH1OFFSETCAL bit masks and bit positions */ ++#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1INVEN_bm 0x08 /* Analog Comparator 1 Output Invert Enable bit mask. */ ++#define AC_AC1INVEN_bp 3 /* Analog Comparator 1 Output Invert Enable bit position. */ ++ ++#define AC_AC0INVEN_bm 0x04 /* Analog Comparator 0 Output Invert Enable bit mask. */ ++#define AC_AC0INVEN_bp 2 /* Analog Comparator 0 Output Invert Enable bit position. */ ++ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* AC.CURRCTRL bit masks and bit positions */ ++#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ ++#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ ++ ++#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ ++#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ ++ ++#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ ++#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ ++ ++#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ ++#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ ++ ++/* AC.CURRCALIB bit masks and bit positions */ ++#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ ++#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ ++#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ ++#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ ++#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ ++#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ ++#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ ++#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ ++#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ ++#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ ++ ++/* RTC - Real-Time Clounter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_CORREN_bm 0x08 /* Correction Enable bit mask. */ ++#define RTC_CORREN_bp 3 /* Correction Enable bit position. */ ++ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* RTC.CALIB bit masks and bit positions */ ++#define RTC_SIGN_bm 0x80 /* Correction Sign bit mask. */ ++#define RTC_SIGN_bp 7 /* Correction Sign bit position. */ ++ ++#define RTC_ERROR_gm 0x7F /* Error Value group mask. */ ++#define RTC_ERROR_gp 0 /* Error Value group position. */ ++#define RTC_ERROR0_bm (1<<0) /* Error Value bit 0 mask. */ ++#define RTC_ERROR0_bp 0 /* Error Value bit 0 position. */ ++#define RTC_ERROR1_bm (1<<1) /* Error Value bit 1 mask. */ ++#define RTC_ERROR1_bp 1 /* Error Value bit 1 position. */ ++#define RTC_ERROR2_bm (1<<2) /* Error Value bit 2 mask. */ ++#define RTC_ERROR2_bp 2 /* Error Value bit 2 position. */ ++#define RTC_ERROR3_bm (1<<3) /* Error Value bit 3 mask. */ ++#define RTC_ERROR3_bp 3 /* Error Value bit 3 position. */ ++#define RTC_ERROR4_bm (1<<4) /* Error Value bit 4 mask. */ ++#define RTC_ERROR4_bp 4 /* Error Value bit 4 position. */ ++#define RTC_ERROR5_bm (1<<5) /* Error Value bit 5 mask. */ ++#define RTC_ERROR5_bp 5 /* Error Value bit 5 position. */ ++#define RTC_ERROR6_bm (1<<6) /* Error Value bit 6 mask. */ ++#define RTC_ERROR6_bp 6 /* Error Value bit 6 position. */ ++ ++/* XCL - XMEGA Custom Logic */ ++/* XCL.CTRLA bit masks and bit positions */ ++#define XCL_LUT0OUTEN_gm 0xC0 /* LUT0 Output Enable group mask. */ ++#define XCL_LUT0OUTEN_gp 6 /* LUT0 Output Enable group position. */ ++#define XCL_LUT0OUTEN0_bm (1<<6) /* LUT0 Output Enable bit 0 mask. */ ++#define XCL_LUT0OUTEN0_bp 6 /* LUT0 Output Enable bit 0 position. */ ++#define XCL_LUT0OUTEN1_bm (1<<7) /* LUT0 Output Enable bit 1 mask. */ ++#define XCL_LUT0OUTEN1_bp 7 /* LUT0 Output Enable bit 1 position. */ ++ ++#define XCL_PORTSEL_gm 0x30 /* Port Selection group mask. */ ++#define XCL_PORTSEL_gp 4 /* Port Selection group position. */ ++#define XCL_PORTSEL0_bm (1<<4) /* Port Selection bit 0 mask. */ ++#define XCL_PORTSEL0_bp 4 /* Port Selection bit 0 position. */ ++#define XCL_PORTSEL1_bm (1<<5) /* Port Selection bit 1 mask. */ ++#define XCL_PORTSEL1_bp 5 /* Port Selection bit 1 position. */ ++ ++#define XCL_LUTCONF_gm 0x07 /* LUT Configuration group mask. */ ++#define XCL_LUTCONF_gp 0 /* LUT Configuration group position. */ ++#define XCL_LUTCONF0_bm (1<<0) /* LUT Configuration bit 0 mask. */ ++#define XCL_LUTCONF0_bp 0 /* LUT Configuration bit 0 position. */ ++#define XCL_LUTCONF1_bm (1<<1) /* LUT Configuration bit 1 mask. */ ++#define XCL_LUTCONF1_bp 1 /* LUT Configuration bit 1 position. */ ++#define XCL_LUTCONF2_bm (1<<2) /* LUT Configuration bit 2 mask. */ ++#define XCL_LUTCONF2_bp 2 /* LUT Configuration bit 2 position. */ ++ ++/* XCL.CTRLB bit masks and bit positions */ ++#define XCL_IN3SEL_gm 0xC0 /* Input Selection 3 group mask. */ ++#define XCL_IN3SEL_gp 6 /* Input Selection 3 group position. */ ++#define XCL_IN3SEL0_bm (1<<6) /* Input Selection 3 bit 0 mask. */ ++#define XCL_IN3SEL0_bp 6 /* Input Selection 3 bit 0 position. */ ++#define XCL_IN3SEL1_bm (1<<7) /* Input Selection 3 bit 1 mask. */ ++#define XCL_IN3SEL1_bp 7 /* Input Selection 3 bit 1 position. */ ++ ++#define XCL_IN2SEL_gm 0x30 /* Input Selection 2 group mask. */ ++#define XCL_IN2SEL_gp 4 /* Input Selection 2 group position. */ ++#define XCL_IN2SEL0_bm (1<<4) /* Input Selection 2 bit 0 mask. */ ++#define XCL_IN2SEL0_bp 4 /* Input Selection 2 bit 0 position. */ ++#define XCL_IN2SEL1_bm (1<<5) /* Input Selection 2 bit 1 mask. */ ++#define XCL_IN2SEL1_bp 5 /* Input Selection 2 bit 1 position. */ ++ ++#define XCL_IN1SEL_gm 0x0C /* Input Selection 1 group mask. */ ++#define XCL_IN1SEL_gp 2 /* Input Selection 1 group position. */ ++#define XCL_IN1SEL0_bm (1<<2) /* Input Selection 1 bit 0 mask. */ ++#define XCL_IN1SEL0_bp 2 /* Input Selection 1 bit 0 position. */ ++#define XCL_IN1SEL1_bm (1<<3) /* Input Selection 1 bit 1 mask. */ ++#define XCL_IN1SEL1_bp 3 /* Input Selection 1 bit 1 position. */ ++ ++#define XCL_IN0SEL_gm 0x03 /* Input Selection 0 group mask. */ ++#define XCL_IN0SEL_gp 0 /* Input Selection 0 group position. */ ++#define XCL_IN0SEL0_bm (1<<0) /* Input Selection 0 bit 0 mask. */ ++#define XCL_IN0SEL0_bp 0 /* Input Selection 0 bit 0 position. */ ++#define XCL_IN0SEL1_bm (1<<1) /* Input Selection 0 bit 1 mask. */ ++#define XCL_IN0SEL1_bp 1 /* Input Selection 0 bit 1 position. */ ++ ++/* XCL.CTRLC bit masks and bit positions */ ++#define XCL_EVASYSEL1_bm 0x80 /* Asynchronous Event Line Selection for LUT1 bit mask. */ ++#define XCL_EVASYSEL1_bp 7 /* Asynchronous Event Line Selection for LUT1 bit position. */ ++ ++#define XCL_EVASYSEL0_bm 0x40 /* Asynchronous Event Line Selection for LUT0 bit mask. */ ++#define XCL_EVASYSEL0_bp 6 /* Asynchronous Event Line Selection for LUT0 bit position. */ ++ ++#define XCL_DLYSEL_gm 0x30 /* Delay Selection group mask. */ ++#define XCL_DLYSEL_gp 4 /* Delay Selection group position. */ ++#define XCL_DLYSEL0_bm (1<<4) /* Delay Selection bit 0 mask. */ ++#define XCL_DLYSEL0_bp 4 /* Delay Selection bit 0 position. */ ++#define XCL_DLYSEL1_bm (1<<5) /* Delay Selection bit 1 mask. */ ++#define XCL_DLYSEL1_bp 5 /* Delay Selection bit 1 position. */ ++ ++#define XCL_DLY1CONF_gm 0x0C /* Delay Configuration on LUT1 group mask. */ ++#define XCL_DLY1CONF_gp 2 /* Delay Configuration on LUT1 group position. */ ++#define XCL_DLY1CONF0_bm (1<<2) /* Delay Configuration on LUT1 bit 0 mask. */ ++#define XCL_DLY1CONF0_bp 2 /* Delay Configuration on LUT1 bit 0 position. */ ++#define XCL_DLY1CONF1_bm (1<<3) /* Delay Configuration on LUT1 bit 1 mask. */ ++#define XCL_DLY1CONF1_bp 3 /* Delay Configuration on LUT1 bit 1 position. */ ++ ++#define XCL_DLY0CONF_gm 0x03 /* Delay Configuration on LUT0 group mask. */ ++#define XCL_DLY0CONF_gp 0 /* Delay Configuration on LUT0 group position. */ ++#define XCL_DLY0CONF0_bm (1<<0) /* Delay Configuration on LUT0 bit 0 mask. */ ++#define XCL_DLY0CONF0_bp 0 /* Delay Configuration on LUT0 bit 0 position. */ ++#define XCL_DLY0CONF1_bm (1<<1) /* Delay Configuration on LUT0 bit 1 mask. */ ++#define XCL_DLY0CONF1_bp 1 /* Delay Configuration on LUT0 bit 1 position. */ ++ ++/* XCL.CTRLD bit masks and bit positions */ ++#define XCL_TRUTH1_gm 0xF0 /* Truth Table of LUT1 group mask. */ ++#define XCL_TRUTH1_gp 4 /* Truth Table of LUT1 group position. */ ++#define XCL_TRUTH10_bm (1<<4) /* Truth Table of LUT1 bit 0 mask. */ ++#define XCL_TRUTH10_bp 4 /* Truth Table of LUT1 bit 0 position. */ ++#define XCL_TRUTH11_bm (1<<5) /* Truth Table of LUT1 bit 1 mask. */ ++#define XCL_TRUTH11_bp 5 /* Truth Table of LUT1 bit 1 position. */ ++#define XCL_TRUTH12_bm (1<<6) /* Truth Table of LUT1 bit 2 mask. */ ++#define XCL_TRUTH12_bp 6 /* Truth Table of LUT1 bit 2 position. */ ++#define XCL_TRUTH13_bm (1<<7) /* Truth Table of LUT1 bit 3 mask. */ ++#define XCL_TRUTH13_bp 7 /* Truth Table of LUT1 bit 3 position. */ ++ ++#define XCL_TRUTH0_gm 0x0F /* Truth Table of LUT0 group mask. */ ++#define XCL_TRUTH0_gp 0 /* Truth Table of LUT0 group position. */ ++#define XCL_TRUTH00_bm (1<<0) /* Truth Table of LUT0 bit 0 mask. */ ++#define XCL_TRUTH00_bp 0 /* Truth Table of LUT0 bit 0 position. */ ++#define XCL_TRUTH01_bm (1<<1) /* Truth Table of LUT0 bit 1 mask. */ ++#define XCL_TRUTH01_bp 1 /* Truth Table of LUT0 bit 1 position. */ ++#define XCL_TRUTH02_bm (1<<2) /* Truth Table of LUT0 bit 2 mask. */ ++#define XCL_TRUTH02_bp 2 /* Truth Table of LUT0 bit 2 position. */ ++#define XCL_TRUTH03_bm (1<<3) /* Truth Table of LUT0 bit 3 mask. */ ++#define XCL_TRUTH03_bp 3 /* Truth Table of LUT0 bit 3 position. */ ++ ++/* XCL.CTRLE bit masks and bit positions */ ++#define XCL_CMDSEL_bm 0x80 /* Timer/Counter Command Selection bit mask. */ ++#define XCL_CMDSEL_bp 7 /* Timer/Counter Command Selection bit position. */ ++ ++#define XCL_TCSEL_gm 0x70 /* Timer/Counter Selection group mask. */ ++#define XCL_TCSEL_gp 4 /* Timer/Counter Selection group position. */ ++#define XCL_TCSEL0_bm (1<<4) /* Timer/Counter Selection bit 0 mask. */ ++#define XCL_TCSEL0_bp 4 /* Timer/Counter Selection bit 0 position. */ ++#define XCL_TCSEL1_bm (1<<5) /* Timer/Counter Selection bit 1 mask. */ ++#define XCL_TCSEL1_bp 5 /* Timer/Counter Selection bit 1 position. */ ++#define XCL_TCSEL2_bm (1<<6) /* Timer/Counter Selection bit 2 mask. */ ++#define XCL_TCSEL2_bp 6 /* Timer/Counter Selection bit 2 position. */ ++ ++#define XCL_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define XCL_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define XCL_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define XCL_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define XCL_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define XCL_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define XCL_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define XCL_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define XCL_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define XCL_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* XCL.CTRLF bit masks and bit positions */ ++#define XCL_CMDEN_gm 0xC0 /* Command Enable group mask. */ ++#define XCL_CMDEN_gp 6 /* Command Enable group position. */ ++#define XCL_CMDEN0_bm (1<<6) /* Command Enable bit 0 mask. */ ++#define XCL_CMDEN0_bp 6 /* Command Enable bit 0 position. */ ++#define XCL_CMDEN1_bm (1<<7) /* Command Enable bit 1 mask. */ ++#define XCL_CMDEN1_bp 7 /* Command Enable bit 1 position. */ ++ ++#define XCL_CMP1_bm 0x20 /* Compare Channel 1 Output Value bit mask. */ ++#define XCL_CMP1_bp 5 /* Compare Channel 1 Output Value bit position. */ ++ ++#define XCL_CMP0_bm 0x10 /* Compare Channel 0 Output Value bit mask. */ ++#define XCL_CMP0_bp 4 /* Compare Channel 0 Output Value bit position. */ ++ ++#define XCL_CCEN1_bm 0x08 /* Compare or Capture Channel 1 Enable bit mask. */ ++#define XCL_CCEN1_bp 3 /* Compare or Capture Channel 1 Enable bit position. */ ++ ++#define XCL_CCEN0_bm 0x04 /* Compare or Capture Channel 0 Enable bit mask. */ ++#define XCL_CCEN0_bp 2 /* Compare or Capture Channel 0 Enable bit position. */ ++ ++#define XCL_MODE_gm 0x03 /* Timer/Counter Mode group mask. */ ++#define XCL_MODE_gp 0 /* Timer/Counter Mode group position. */ ++#define XCL_MODE0_bm (1<<0) /* Timer/Counter Mode bit 0 mask. */ ++#define XCL_MODE0_bp 0 /* Timer/Counter Mode bit 0 position. */ ++#define XCL_MODE1_bm (1<<1) /* Timer/Counter Mode bit 1 mask. */ ++#define XCL_MODE1_bp 1 /* Timer/Counter Mode bit 1 position. */ ++ ++/* XCL.CTRLG bit masks and bit positions */ ++#define XCL_EVACTEN_bm 0x80 /* Event Action Enable bit mask. */ ++#define XCL_EVACTEN_bp 7 /* Event Action Enable bit position. */ ++ ++#define XCL_EVACT1_gm 0x60 /* Event Action Selection on Timer/Counter 1 group mask. */ ++#define XCL_EVACT1_gp 5 /* Event Action Selection on Timer/Counter 1 group position. */ ++#define XCL_EVACT10_bm (1<<5) /* Event Action Selection on Timer/Counter 1 bit 0 mask. */ ++#define XCL_EVACT10_bp 5 /* Event Action Selection on Timer/Counter 1 bit 0 position. */ ++#define XCL_EVACT11_bm (1<<6) /* Event Action Selection on Timer/Counter 1 bit 1 mask. */ ++#define XCL_EVACT11_bp 6 /* Event Action Selection on Timer/Counter 1 bit 1 position. */ ++ ++#define XCL_EVACT0_gm 0x18 /* Event Action Selection on Timer/Counter 0 group mask. */ ++#define XCL_EVACT0_gp 3 /* Event Action Selection on Timer/Counter 0 group position. */ ++#define XCL_EVACT00_bm (1<<3) /* Event Action Selection on Timer/Counter 0 bit 0 mask. */ ++#define XCL_EVACT00_bp 3 /* Event Action Selection on Timer/Counter 0 bit 0 position. */ ++#define XCL_EVACT01_bm (1<<4) /* Event Action Selection on Timer/Counter 0 bit 1 mask. */ ++#define XCL_EVACT01_bp 4 /* Event Action Selection on Timer/Counter 0 bit 1 position. */ ++ ++#define XCL_EVSRC_gm 0x07 /* Event Source Selection group mask. */ ++#define XCL_EVSRC_gp 0 /* Event Source Selection group position. */ ++#define XCL_EVSRC0_bm (1<<0) /* Event Source Selection bit 0 mask. */ ++#define XCL_EVSRC0_bp 0 /* Event Source Selection bit 0 position. */ ++#define XCL_EVSRC1_bm (1<<1) /* Event Source Selection bit 1 mask. */ ++#define XCL_EVSRC1_bp 1 /* Event Source Selection bit 1 position. */ ++#define XCL_EVSRC2_bm (1<<2) /* Event Source Selection bit 2 mask. */ ++#define XCL_EVSRC2_bp 2 /* Event Source Selection bit 2 position. */ ++ ++/* XCL.INTCTRL bit masks and bit positions */ ++#define XCL_UNF1IE_bm 0x80 /* Underflow 1 Interrupt Enable bit mask. */ ++#define XCL_UNF1IE_bp 7 /* Underflow 1 Interrupt Enable bit position. */ ++ ++#define XCL_PEC1IE_bm 0x80 /* Peripheral Counter 1 Interrupt Enable bit mask. */ ++#define XCL_PEC1IE_bp 7 /* Peripheral Counter 1 Interrupt Enable bit position. */ ++ ++#define XCL_PEC21IE_bm 0x80 /* Peripheral High Counter 2 Interrupt Enable bit mask. */ ++#define XCL_PEC21IE_bp 7 /* Peripheral High Counter 2 Interrupt Enable bit position. */ ++ ++#define XCL_UNF0IE_bm 0x40 /* Underflow 0 Interrupt Enable bit mask. */ ++#define XCL_UNF0IE_bp 6 /* Underflow 0 Interrupt Enable bit position. */ ++ ++#define XCL_PEC0IE_bm 0x40 /* Peripheral Counter 0 Interrupt Enable bit mask. */ ++#define XCL_PEC0IE_bp 6 /* Peripheral Counter 0 Interrupt Enable bit position. */ ++ ++#define XCL_CC1IE_bm 0x20 /* Compare Or Capture 1 Interrupt Enable bit mask. */ ++#define XCL_CC1IE_bp 5 /* Compare Or Capture 1 Interrupt Enable bit position. */ ++ ++#define XCL_PEC20IE_bm 0x20 /* Peripheral Low Counter 2 Interrupt Enable bit mask. */ ++#define XCL_PEC20IE_bp 5 /* Peripheral Low Counter 2 Interrupt Enable bit position. */ ++ ++#define XCL_CC0IE_bm 0x10 /* Compare Or Capture 0 Interrupt Enable bit mask. */ ++#define XCL_CC0IE_bp 4 /* Compare Or Capture 0 Interrupt Enable bit position. */ ++ ++#define XCL_UNFINTLVL_gm 0x0C /* Timer Underflow Interrupt Level group mask. */ ++#define XCL_UNFINTLVL_gp 2 /* Timer Underflow Interrupt Level group position. */ ++#define XCL_UNFINTLVL0_bm (1<<2) /* Timer Underflow Interrupt Level bit 0 mask. */ ++#define XCL_UNFINTLVL0_bp 2 /* Timer Underflow Interrupt Level bit 0 position. */ ++#define XCL_UNFINTLVL1_bm (1<<3) /* Timer Underflow Interrupt Level bit 1 mask. */ ++#define XCL_UNFINTLVL1_bp 3 /* Timer Underflow Interrupt Level bit 1 position. */ ++ ++#define XCL_CCINTLVL_gm 0x03 /* Timer Compare or Capture Interrupt Level group mask. */ ++#define XCL_CCINTLVL_gp 0 /* Timer Compare or Capture Interrupt Level group position. */ ++#define XCL_CCINTLVL0_bm (1<<0) /* Timer Compare or Capture Interrupt Level bit 0 mask. */ ++#define XCL_CCINTLVL0_bp 0 /* Timer Compare or Capture Interrupt Level bit 0 position. */ ++#define XCL_CCINTLVL1_bm (1<<1) /* Timer Compare or Capture Interrupt Level bit 1 mask. */ ++#define XCL_CCINTLVL1_bp 1 /* Timer Compare or Capture Interrupt Level bit 1 position. */ ++ ++/* XCL.INTFLAGS bit masks and bit positions */ ++#define XCL_UNF1IF_bm 0x80 /* Timer/Counter 1 Underflow Interrupt Flag bit mask. */ ++#define XCL_UNF1IF_bp 7 /* Timer/Counter 1 Underflow Interrupt Flag bit position. */ ++ ++#define XCL_PEC1IF_bm 0x80 /* Peripheral Counter 1 Interrupt Flag bit mask. */ ++#define XCL_PEC1IF_bp 7 /* Peripheral Counter 1 Interrupt Flag bit position. */ ++ ++#define XCL_PEC21IF_bm 0x80 /* Peripheral High Counter 2 Interrupt Flag bit mask. */ ++#define XCL_PEC21IF_bp 7 /* Peripheral High Counter 2 Interrupt Flag bit position. */ ++ ++#define XCL_UNF0IF_bm 0x40 /* Timer/Counter 0 Underflow Interrupt Flag bit mask. */ ++#define XCL_UNF0IF_bp 6 /* Timer/Counter 0 Underflow Interrupt Flag bit position. */ ++ ++#define XCL_PEC0IF_bm 0x40 /* Peripheral Counter 0 Interrupt Flag bit mask. */ ++#define XCL_PEC0IF_bp 6 /* Peripheral Counter 0 Interrupt Flag bit position. */ ++ ++#define XCL_CC1IF_bm 0x20 /* Compare or Capture Channel 1 Interrupt Flag bit mask. */ ++#define XCL_CC1IF_bp 5 /* Compare or Capture Channel 1 Interrupt Flag bit position. */ ++ ++#define XCL_PEC20IF_bm 0x20 /* Peripheral Low Counter 2 Interrupt Flag bit mask. */ ++#define XCL_PEC20IF_bp 5 /* Peripheral Low Counter 2 Interrupt Flag bit position. */ ++ ++#define XCL_CC0IF_bm 0x10 /* Compare or Capture Channel 0 Interrupt Flag bit mask. */ ++#define XCL_CC0IF_bp 4 /* Compare or Capture Channel 0 Interrupt Flag bit position. */ ++ ++/* XCL.PLC bit masks and bit positions */ ++#define XCL_PLC_gm 0xFF /* Peripheral Lenght Control Bits group mask. */ ++#define XCL_PLC_gp 0 /* Peripheral Lenght Control Bits group position. */ ++#define XCL_PLC0_bm (1<<0) /* Peripheral Lenght Control Bits bit 0 mask. */ ++#define XCL_PLC0_bp 0 /* Peripheral Lenght Control Bits bit 0 position. */ ++#define XCL_PLC1_bm (1<<1) /* Peripheral Lenght Control Bits bit 1 mask. */ ++#define XCL_PLC1_bp 1 /* Peripheral Lenght Control Bits bit 1 position. */ ++#define XCL_PLC2_bm (1<<2) /* Peripheral Lenght Control Bits bit 2 mask. */ ++#define XCL_PLC2_bp 2 /* Peripheral Lenght Control Bits bit 2 position. */ ++#define XCL_PLC3_bm (1<<3) /* Peripheral Lenght Control Bits bit 3 mask. */ ++#define XCL_PLC3_bp 3 /* Peripheral Lenght Control Bits bit 3 position. */ ++#define XCL_PLC4_bm (1<<4) /* Peripheral Lenght Control Bits bit 4 mask. */ ++#define XCL_PLC4_bp 4 /* Peripheral Lenght Control Bits bit 4 position. */ ++#define XCL_PLC5_bm (1<<5) /* Peripheral Lenght Control Bits bit 5 mask. */ ++#define XCL_PLC5_bp 5 /* Peripheral Lenght Control Bits bit 5 position. */ ++#define XCL_PLC6_bm (1<<6) /* Peripheral Lenght Control Bits bit 6 mask. */ ++#define XCL_PLC6_bp 6 /* Peripheral Lenght Control Bits bit 6 position. */ ++#define XCL_PLC7_bm (1<<7) /* Peripheral Lenght Control Bits bit 7 mask. */ ++#define XCL_PLC7_bp 7 /* Peripheral Lenght Control Bits bit 7 position. */ ++ ++/* XCL.CNTL bit masks and bit positions */ ++#define XCL_BCNTO_gm 0xFF /* BTC0 Counter Byte group mask. */ ++#define XCL_BCNTO_gp 0 /* BTC0 Counter Byte group position. */ ++#define XCL_BCNTO0_bm (1<<0) /* BTC0 Counter Byte bit 0 mask. */ ++#define XCL_BCNTO0_bp 0 /* BTC0 Counter Byte bit 0 position. */ ++#define XCL_BCNTO1_bm (1<<1) /* BTC0 Counter Byte bit 1 mask. */ ++#define XCL_BCNTO1_bp 1 /* BTC0 Counter Byte bit 1 position. */ ++#define XCL_BCNTO2_bm (1<<2) /* BTC0 Counter Byte bit 2 mask. */ ++#define XCL_BCNTO2_bp 2 /* BTC0 Counter Byte bit 2 position. */ ++#define XCL_BCNTO3_bm (1<<3) /* BTC0 Counter Byte bit 3 mask. */ ++#define XCL_BCNTO3_bp 3 /* BTC0 Counter Byte bit 3 position. */ ++#define XCL_BCNTO4_bm (1<<4) /* BTC0 Counter Byte bit 4 mask. */ ++#define XCL_BCNTO4_bp 4 /* BTC0 Counter Byte bit 4 position. */ ++#define XCL_BCNTO5_bm (1<<5) /* BTC0 Counter Byte bit 5 mask. */ ++#define XCL_BCNTO5_bp 5 /* BTC0 Counter Byte bit 5 position. */ ++#define XCL_BCNTO6_bm (1<<6) /* BTC0 Counter Byte bit 6 mask. */ ++#define XCL_BCNTO6_bp 6 /* BTC0 Counter Byte bit 6 position. */ ++#define XCL_BCNTO7_bm (1<<7) /* BTC0 Counter Byte bit 7 mask. */ ++#define XCL_BCNTO7_bp 7 /* BTC0 Counter Byte bit 7 position. */ ++ ++#define XCL_CNTL_gm 0xFF /* TC16 Counter Low Byte group mask. */ ++#define XCL_CNTL_gp 0 /* TC16 Counter Low Byte group position. */ ++#define XCL_CNTL0_bm (1<<0) /* TC16 Counter Low Byte bit 0 mask. */ ++#define XCL_CNTL0_bp 0 /* TC16 Counter Low Byte bit 0 position. */ ++#define XCL_CNTL1_bm (1<<1) /* TC16 Counter Low Byte bit 1 mask. */ ++#define XCL_CNTL1_bp 1 /* TC16 Counter Low Byte bit 1 position. */ ++#define XCL_CNTL2_bm (1<<2) /* TC16 Counter Low Byte bit 2 mask. */ ++#define XCL_CNTL2_bp 2 /* TC16 Counter Low Byte bit 2 position. */ ++#define XCL_CNTL3_bm (1<<3) /* TC16 Counter Low Byte bit 3 mask. */ ++#define XCL_CNTL3_bp 3 /* TC16 Counter Low Byte bit 3 position. */ ++#define XCL_CNTL4_bm (1<<4) /* TC16 Counter Low Byte bit 4 mask. */ ++#define XCL_CNTL4_bp 4 /* TC16 Counter Low Byte bit 4 position. */ ++#define XCL_CNTL5_bm (1<<5) /* TC16 Counter Low Byte bit 5 mask. */ ++#define XCL_CNTL5_bp 5 /* TC16 Counter Low Byte bit 5 position. */ ++#define XCL_CNTL6_bm (1<<6) /* TC16 Counter Low Byte bit 6 mask. */ ++#define XCL_CNTL6_bp 6 /* TC16 Counter Low Byte bit 6 position. */ ++#define XCL_CNTL7_bm (1<<7) /* TC16 Counter Low Byte bit 7 mask. */ ++#define XCL_CNTL7_bp 7 /* TC16 Counter Low Byte bit 7 position. */ ++ ++#define XCL_PCNTO_gm 0xFF /* Peripheral Counter 0 Byte group mask. */ ++#define XCL_PCNTO_gp 0 /* Peripheral Counter 0 Byte group position. */ ++#define XCL_PCNTO0_bm (1<<0) /* Peripheral Counter 0 Byte bit 0 mask. */ ++#define XCL_PCNTO0_bp 0 /* Peripheral Counter 0 Byte bit 0 position. */ ++#define XCL_PCNTO1_bm (1<<1) /* Peripheral Counter 0 Byte bit 1 mask. */ ++#define XCL_PCNTO1_bp 1 /* Peripheral Counter 0 Byte bit 1 position. */ ++#define XCL_PCNTO2_bm (1<<2) /* Peripheral Counter 0 Byte bit 2 mask. */ ++#define XCL_PCNTO2_bp 2 /* Peripheral Counter 0 Byte bit 2 position. */ ++#define XCL_PCNTO3_bm (1<<3) /* Peripheral Counter 0 Byte bit 3 mask. */ ++#define XCL_PCNTO3_bp 3 /* Peripheral Counter 0 Byte bit 3 position. */ ++#define XCL_PCNTO4_bm (1<<4) /* Peripheral Counter 0 Byte bit 4 mask. */ ++#define XCL_PCNTO4_bp 4 /* Peripheral Counter 0 Byte bit 4 position. */ ++#define XCL_PCNTO5_bm (1<<5) /* Peripheral Counter 0 Byte bit 5 mask. */ ++#define XCL_PCNTO5_bp 5 /* Peripheral Counter 0 Byte bit 5 position. */ ++#define XCL_PCNTO6_bm (1<<6) /* Peripheral Counter 0 Byte bit 6 mask. */ ++#define XCL_PCNTO6_bp 6 /* Peripheral Counter 0 Byte bit 6 position. */ ++#define XCL_PCNTO7_bm (1<<7) /* Peripheral Counter 0 Byte bit 7 mask. */ ++#define XCL_PCNTO7_bp 7 /* Peripheral Counter 0 Byte bit 7 position. */ ++ ++/* XCL.CNTH bit masks and bit positions */ ++#define XCL_BCNT1_gm 0xFF /* BTC1 Counter Byte group mask. */ ++#define XCL_BCNT1_gp 0 /* BTC1 Counter Byte group position. */ ++#define XCL_BCNT10_bm (1<<0) /* BTC1 Counter Byte bit 0 mask. */ ++#define XCL_BCNT10_bp 0 /* BTC1 Counter Byte bit 0 position. */ ++#define XCL_BCNT11_bm (1<<1) /* BTC1 Counter Byte bit 1 mask. */ ++#define XCL_BCNT11_bp 1 /* BTC1 Counter Byte bit 1 position. */ ++#define XCL_BCNT12_bm (1<<2) /* BTC1 Counter Byte bit 2 mask. */ ++#define XCL_BCNT12_bp 2 /* BTC1 Counter Byte bit 2 position. */ ++#define XCL_BCNT13_bm (1<<3) /* BTC1 Counter Byte bit 3 mask. */ ++#define XCL_BCNT13_bp 3 /* BTC1 Counter Byte bit 3 position. */ ++#define XCL_BCNT14_bm (1<<4) /* BTC1 Counter Byte bit 4 mask. */ ++#define XCL_BCNT14_bp 4 /* BTC1 Counter Byte bit 4 position. */ ++#define XCL_BCNT15_bm (1<<5) /* BTC1 Counter Byte bit 5 mask. */ ++#define XCL_BCNT15_bp 5 /* BTC1 Counter Byte bit 5 position. */ ++#define XCL_BCNT16_bm (1<<6) /* BTC1 Counter Byte bit 6 mask. */ ++#define XCL_BCNT16_bp 6 /* BTC1 Counter Byte bit 6 position. */ ++#define XCL_BCNT17_bm (1<<7) /* BTC1 Counter Byte bit 7 mask. */ ++#define XCL_BCNT17_bp 7 /* BTC1 Counter Byte bit 7 position. */ ++ ++#define XCL_CNTH_gm 0xFF /* TC16 Counter High Byte group mask. */ ++#define XCL_CNTH_gp 0 /* TC16 Counter High Byte group position. */ ++#define XCL_CNTH0_bm (1<<0) /* TC16 Counter High Byte bit 0 mask. */ ++#define XCL_CNTH0_bp 0 /* TC16 Counter High Byte bit 0 position. */ ++#define XCL_CNTH1_bm (1<<1) /* TC16 Counter High Byte bit 1 mask. */ ++#define XCL_CNTH1_bp 1 /* TC16 Counter High Byte bit 1 position. */ ++#define XCL_CNTH2_bm (1<<2) /* TC16 Counter High Byte bit 2 mask. */ ++#define XCL_CNTH2_bp 2 /* TC16 Counter High Byte bit 2 position. */ ++#define XCL_CNTH3_bm (1<<3) /* TC16 Counter High Byte bit 3 mask. */ ++#define XCL_CNTH3_bp 3 /* TC16 Counter High Byte bit 3 position. */ ++#define XCL_CNTH4_bm (1<<4) /* TC16 Counter High Byte bit 4 mask. */ ++#define XCL_CNTH4_bp 4 /* TC16 Counter High Byte bit 4 position. */ ++#define XCL_CNTH5_bm (1<<5) /* TC16 Counter High Byte bit 5 mask. */ ++#define XCL_CNTH5_bp 5 /* TC16 Counter High Byte bit 5 position. */ ++#define XCL_CNTH6_bm (1<<6) /* TC16 Counter High Byte bit 6 mask. */ ++#define XCL_CNTH6_bp 6 /* TC16 Counter High Byte bit 6 position. */ ++#define XCL_CNTH7_bm (1<<7) /* TC16 Counter High Byte bit 7 mask. */ ++#define XCL_CNTH7_bp 7 /* TC16 Counter High Byte bit 7 position. */ ++ ++#define XCL_PCNT1_gm 0xFF /* Peripheral Counter 1 Byte group mask. */ ++#define XCL_PCNT1_gp 0 /* Peripheral Counter 1 Byte group position. */ ++#define XCL_PCNT10_bm (1<<0) /* Peripheral Counter 1 Byte bit 0 mask. */ ++#define XCL_PCNT10_bp 0 /* Peripheral Counter 1 Byte bit 0 position. */ ++#define XCL_PCNT11_bm (1<<1) /* Peripheral Counter 1 Byte bit 1 mask. */ ++#define XCL_PCNT11_bp 1 /* Peripheral Counter 1 Byte bit 1 position. */ ++#define XCL_PCNT12_bm (1<<2) /* Peripheral Counter 1 Byte bit 2 mask. */ ++#define XCL_PCNT12_bp 2 /* Peripheral Counter 1 Byte bit 2 position. */ ++#define XCL_PCNT13_bm (1<<3) /* Peripheral Counter 1 Byte bit 3 mask. */ ++#define XCL_PCNT13_bp 3 /* Peripheral Counter 1 Byte bit 3 position. */ ++#define XCL_PCNT14_bm (1<<4) /* Peripheral Counter 1 Byte bit 4 mask. */ ++#define XCL_PCNT14_bp 4 /* Peripheral Counter 1 Byte bit 4 position. */ ++#define XCL_PCNT15_bm (1<<5) /* Peripheral Counter 1 Byte bit 5 mask. */ ++#define XCL_PCNT15_bp 5 /* Peripheral Counter 1 Byte bit 5 position. */ ++#define XCL_PCNT16_bm (1<<6) /* Peripheral Counter 1 Byte bit 6 mask. */ ++#define XCL_PCNT16_bp 6 /* Peripheral Counter 1 Byte bit 6 position. */ ++#define XCL_PCNT17_bm (1<<7) /* Peripheral Counter 1 Byte bit 7 mask. */ ++#define XCL_PCNT17_bp 7 /* Peripheral Counter 1 Byte bit 7 position. */ ++ ++#define XCL_PCNT21_gm 0xF0 /* Peripheral High Counter 2 Bits group mask. */ ++#define XCL_PCNT21_gp 4 /* Peripheral High Counter 2 Bits group position. */ ++#define XCL_PCNT210_bm (1<<4) /* Peripheral High Counter 2 Bits bit 0 mask. */ ++#define XCL_PCNT210_bp 4 /* Peripheral High Counter 2 Bits bit 0 position. */ ++#define XCL_PCNT211_bm (1<<5) /* Peripheral High Counter 2 Bits bit 1 mask. */ ++#define XCL_PCNT211_bp 5 /* Peripheral High Counter 2 Bits bit 1 position. */ ++#define XCL_PCNT212_bm (1<<6) /* Peripheral High Counter 2 Bits bit 2 mask. */ ++#define XCL_PCNT212_bp 6 /* Peripheral High Counter 2 Bits bit 2 position. */ ++#define XCL_PCNT213_bm (1<<7) /* Peripheral High Counter 2 Bits bit 3 mask. */ ++#define XCL_PCNT213_bp 7 /* Peripheral High Counter 2 Bits bit 3 position. */ ++ ++#define XCL_PCNT20_gm 0x0F /* Peripheral Low Counter 2 Bits group mask. */ ++#define XCL_PCNT20_gp 0 /* Peripheral Low Counter 2 Bits group position. */ ++#define XCL_PCNT200_bm (1<<0) /* Peripheral Low Counter 2 Bits bit 0 mask. */ ++#define XCL_PCNT200_bp 0 /* Peripheral Low Counter 2 Bits bit 0 position. */ ++#define XCL_PCNT201_bm (1<<1) /* Peripheral Low Counter 2 Bits bit 1 mask. */ ++#define XCL_PCNT201_bp 1 /* Peripheral Low Counter 2 Bits bit 1 position. */ ++#define XCL_PCNT202_bm (1<<2) /* Peripheral Low Counter 2 Bits bit 2 mask. */ ++#define XCL_PCNT202_bp 2 /* Peripheral Low Counter 2 Bits bit 2 position. */ ++#define XCL_PCNT203_bm (1<<3) /* Peripheral Low Counter 2 Bits bit 3 mask. */ ++#define XCL_PCNT203_bp 3 /* Peripheral Low Counter 2 Bits bit 3 position. */ ++ ++/* XCL.CMPL bit masks and bit positions */ ++#define XCL_CMPL_gm 0xFF /* TC16 Compare Low Byte group mask. */ ++#define XCL_CMPL_gp 0 /* TC16 Compare Low Byte group position. */ ++#define XCL_CMPL0_bm (1<<0) /* TC16 Compare Low Byte bit 0 mask. */ ++#define XCL_CMPL0_bp 0 /* TC16 Compare Low Byte bit 0 position. */ ++#define XCL_CMPL1_bm (1<<1) /* TC16 Compare Low Byte bit 1 mask. */ ++#define XCL_CMPL1_bp 1 /* TC16 Compare Low Byte bit 1 position. */ ++#define XCL_CMPL2_bm (1<<2) /* TC16 Compare Low Byte bit 2 mask. */ ++#define XCL_CMPL2_bp 2 /* TC16 Compare Low Byte bit 2 position. */ ++#define XCL_CMPL3_bm (1<<3) /* TC16 Compare Low Byte bit 3 mask. */ ++#define XCL_CMPL3_bp 3 /* TC16 Compare Low Byte bit 3 position. */ ++#define XCL_CMPL4_bm (1<<4) /* TC16 Compare Low Byte bit 4 mask. */ ++#define XCL_CMPL4_bp 4 /* TC16 Compare Low Byte bit 4 position. */ ++#define XCL_CMPL5_bm (1<<5) /* TC16 Compare Low Byte bit 5 mask. */ ++#define XCL_CMPL5_bp 5 /* TC16 Compare Low Byte bit 5 position. */ ++#define XCL_CMPL6_bm (1<<6) /* TC16 Compare Low Byte bit 6 mask. */ ++#define XCL_CMPL6_bp 6 /* TC16 Compare Low Byte bit 6 position. */ ++#define XCL_CMPL7_bm (1<<7) /* TC16 Compare Low Byte bit 7 mask. */ ++#define XCL_CMPL7_bp 7 /* TC16 Compare Low Byte bit 7 position. */ ++ ++#define XCL_BCMP0_gm 0xFF /* BTC0 Compare Byte group mask. */ ++#define XCL_BCMP0_gp 0 /* BTC0 Compare Byte group position. */ ++#define XCL_BCMP00_bm (1<<0) /* BTC0 Compare Byte bit 0 mask. */ ++#define XCL_BCMP00_bp 0 /* BTC0 Compare Byte bit 0 position. */ ++#define XCL_BCMP01_bm (1<<1) /* BTC0 Compare Byte bit 1 mask. */ ++#define XCL_BCMP01_bp 1 /* BTC0 Compare Byte bit 1 position. */ ++#define XCL_BCMP02_bm (1<<2) /* BTC0 Compare Byte bit 2 mask. */ ++#define XCL_BCMP02_bp 2 /* BTC0 Compare Byte bit 2 position. */ ++#define XCL_BCMP03_bm (1<<3) /* BTC0 Compare Byte bit 3 mask. */ ++#define XCL_BCMP03_bp 3 /* BTC0 Compare Byte bit 3 position. */ ++#define XCL_BCMP04_bm (1<<4) /* BTC0 Compare Byte bit 4 mask. */ ++#define XCL_BCMP04_bp 4 /* BTC0 Compare Byte bit 4 position. */ ++#define XCL_BCMP05_bm (1<<5) /* BTC0 Compare Byte bit 5 mask. */ ++#define XCL_BCMP05_bp 5 /* BTC0 Compare Byte bit 5 position. */ ++#define XCL_BCMP06_bm (1<<6) /* BTC0 Compare Byte bit 6 mask. */ ++#define XCL_BCMP06_bp 6 /* BTC0 Compare Byte bit 6 position. */ ++#define XCL_BCMP07_bm (1<<7) /* BTC0 Compare Byte bit 7 mask. */ ++#define XCL_BCMP07_bp 7 /* BTC0 Compare Byte bit 7 position. */ ++ ++/* XCL.CMPH bit masks and bit positions */ ++#define XCL_CMPH_gm 0xFF /* TC16 Compare High Byte group mask. */ ++#define XCL_CMPH_gp 0 /* TC16 Compare High Byte group position. */ ++#define XCL_CMPH0_bm (1<<0) /* TC16 Compare High Byte bit 0 mask. */ ++#define XCL_CMPH0_bp 0 /* TC16 Compare High Byte bit 0 position. */ ++#define XCL_CMPH1_bm (1<<1) /* TC16 Compare High Byte bit 1 mask. */ ++#define XCL_CMPH1_bp 1 /* TC16 Compare High Byte bit 1 position. */ ++#define XCL_CMPH2_bm (1<<2) /* TC16 Compare High Byte bit 2 mask. */ ++#define XCL_CMPH2_bp 2 /* TC16 Compare High Byte bit 2 position. */ ++#define XCL_CMPH3_bm (1<<3) /* TC16 Compare High Byte bit 3 mask. */ ++#define XCL_CMPH3_bp 3 /* TC16 Compare High Byte bit 3 position. */ ++#define XCL_CMPH4_bm (1<<4) /* TC16 Compare High Byte bit 4 mask. */ ++#define XCL_CMPH4_bp 4 /* TC16 Compare High Byte bit 4 position. */ ++#define XCL_CMPH5_bm (1<<5) /* TC16 Compare High Byte bit 5 mask. */ ++#define XCL_CMPH5_bp 5 /* TC16 Compare High Byte bit 5 position. */ ++#define XCL_CMPH6_bm (1<<6) /* TC16 Compare High Byte bit 6 mask. */ ++#define XCL_CMPH6_bp 6 /* TC16 Compare High Byte bit 6 position. */ ++#define XCL_CMPH7_bm (1<<7) /* TC16 Compare High Byte bit 7 mask. */ ++#define XCL_CMPH7_bp 7 /* TC16 Compare High Byte bit 7 position. */ ++ ++#define XCL_BCMP1_gm 0xFF /* BTC1 Compare Byte group mask. */ ++#define XCL_BCMP1_gp 0 /* BTC1 Compare Byte group position. */ ++#define XCL_BCMP10_bm (1<<0) /* BTC1 Compare Byte bit 0 mask. */ ++#define XCL_BCMP10_bp 0 /* BTC1 Compare Byte bit 0 position. */ ++#define XCL_BCMP11_bm (1<<1) /* BTC1 Compare Byte bit 1 mask. */ ++#define XCL_BCMP11_bp 1 /* BTC1 Compare Byte bit 1 position. */ ++#define XCL_BCMP12_bm (1<<2) /* BTC1 Compare Byte bit 2 mask. */ ++#define XCL_BCMP12_bp 2 /* BTC1 Compare Byte bit 2 position. */ ++#define XCL_BCMP13_bm (1<<3) /* BTC1 Compare Byte bit 3 mask. */ ++#define XCL_BCMP13_bp 3 /* BTC1 Compare Byte bit 3 position. */ ++#define XCL_BCMP14_bm (1<<4) /* BTC1 Compare Byte bit 4 mask. */ ++#define XCL_BCMP14_bp 4 /* BTC1 Compare Byte bit 4 position. */ ++#define XCL_BCMP15_bm (1<<5) /* BTC1 Compare Byte bit 5 mask. */ ++#define XCL_BCMP15_bp 5 /* BTC1 Compare Byte bit 5 position. */ ++#define XCL_BCMP16_bm (1<<6) /* BTC1 Compare Byte bit 6 mask. */ ++#define XCL_BCMP16_bp 6 /* BTC1 Compare Byte bit 6 position. */ ++#define XCL_BCMP17_bm (1<<7) /* BTC1 Compare Byte bit 7 mask. */ ++#define XCL_BCMP17_bp 7 /* BTC1 Compare Byte bit 7 position. */ ++ ++/* XCL.PERCAPTL bit masks and bit positions */ ++#define XCL_PERL_gm 0xFF /* TC16 Low Byte Period group mask. */ ++#define XCL_PERL_gp 0 /* TC16 Low Byte Period group position. */ ++#define XCL_PERL0_bm (1<<0) /* TC16 Low Byte Period bit 0 mask. */ ++#define XCL_PERL0_bp 0 /* TC16 Low Byte Period bit 0 position. */ ++#define XCL_PERL1_bm (1<<1) /* TC16 Low Byte Period bit 1 mask. */ ++#define XCL_PERL1_bp 1 /* TC16 Low Byte Period bit 1 position. */ ++#define XCL_PERL2_bm (1<<2) /* TC16 Low Byte Period bit 2 mask. */ ++#define XCL_PERL2_bp 2 /* TC16 Low Byte Period bit 2 position. */ ++#define XCL_PERL3_bm (1<<3) /* TC16 Low Byte Period bit 3 mask. */ ++#define XCL_PERL3_bp 3 /* TC16 Low Byte Period bit 3 position. */ ++#define XCL_PERL4_bm (1<<4) /* TC16 Low Byte Period bit 4 mask. */ ++#define XCL_PERL4_bp 4 /* TC16 Low Byte Period bit 4 position. */ ++#define XCL_PERL5_bm (1<<5) /* TC16 Low Byte Period bit 5 mask. */ ++#define XCL_PERL5_bp 5 /* TC16 Low Byte Period bit 5 position. */ ++#define XCL_PERL6_bm (1<<6) /* TC16 Low Byte Period bit 6 mask. */ ++#define XCL_PERL6_bp 6 /* TC16 Low Byte Period bit 6 position. */ ++#define XCL_PERL7_bm (1<<7) /* TC16 Low Byte Period bit 7 mask. */ ++#define XCL_PERL7_bp 7 /* TC16 Low Byte Period bit 7 position. */ ++ ++#define XCL_CAPTL_gm 0xFF /* TC16 Capture Value Low Byte group mask. */ ++#define XCL_CAPTL_gp 0 /* TC16 Capture Value Low Byte group position. */ ++#define XCL_CAPTL0_bm (1<<0) /* TC16 Capture Value Low Byte bit 0 mask. */ ++#define XCL_CAPTL0_bp 0 /* TC16 Capture Value Low Byte bit 0 position. */ ++#define XCL_CAPTL1_bm (1<<1) /* TC16 Capture Value Low Byte bit 1 mask. */ ++#define XCL_CAPTL1_bp 1 /* TC16 Capture Value Low Byte bit 1 position. */ ++#define XCL_CAPTL2_bm (1<<2) /* TC16 Capture Value Low Byte bit 2 mask. */ ++#define XCL_CAPTL2_bp 2 /* TC16 Capture Value Low Byte bit 2 position. */ ++#define XCL_CAPTL3_bm (1<<3) /* TC16 Capture Value Low Byte bit 3 mask. */ ++#define XCL_CAPTL3_bp 3 /* TC16 Capture Value Low Byte bit 3 position. */ ++#define XCL_CAPTL4_bm (1<<4) /* TC16 Capture Value Low Byte bit 4 mask. */ ++#define XCL_CAPTL4_bp 4 /* TC16 Capture Value Low Byte bit 4 position. */ ++#define XCL_CAPTL5_bm (1<<5) /* TC16 Capture Value Low Byte bit 5 mask. */ ++#define XCL_CAPTL5_bp 5 /* TC16 Capture Value Low Byte bit 5 position. */ ++#define XCL_CAPTL6_bm (1<<6) /* TC16 Capture Value Low Byte bit 6 mask. */ ++#define XCL_CAPTL6_bp 6 /* TC16 Capture Value Low Byte bit 6 position. */ ++#define XCL_CAPTL7_bm (1<<7) /* TC16 Capture Value Low Byte bit 7 mask. */ ++#define XCL_CAPTL7_bp 7 /* TC16 Capture Value Low Byte bit 7 position. */ ++ ++#define XCL_BPER0_gm 0xFF /* BTC0 Period group mask. */ ++#define XCL_BPER0_gp 0 /* BTC0 Period group position. */ ++#define XCL_BPER00_bm (1<<0) /* BTC0 Period bit 0 mask. */ ++#define XCL_BPER00_bp 0 /* BTC0 Period bit 0 position. */ ++#define XCL_BPER01_bm (1<<1) /* BTC0 Period bit 1 mask. */ ++#define XCL_BPER01_bp 1 /* BTC0 Period bit 1 position. */ ++#define XCL_BPER02_bm (1<<2) /* BTC0 Period bit 2 mask. */ ++#define XCL_BPER02_bp 2 /* BTC0 Period bit 2 position. */ ++#define XCL_BPER03_bm (1<<3) /* BTC0 Period bit 3 mask. */ ++#define XCL_BPER03_bp 3 /* BTC0 Period bit 3 position. */ ++#define XCL_BPER04_bm (1<<4) /* BTC0 Period bit 4 mask. */ ++#define XCL_BPER04_bp 4 /* BTC0 Period bit 4 position. */ ++#define XCL_BPER05_bm (1<<5) /* BTC0 Period bit 5 mask. */ ++#define XCL_BPER05_bp 5 /* BTC0 Period bit 5 position. */ ++#define XCL_BPER06_bm (1<<6) /* BTC0 Period bit 6 mask. */ ++#define XCL_BPER06_bp 6 /* BTC0 Period bit 6 position. */ ++#define XCL_BPER07_bm (1<<7) /* BTC0 Period bit 7 mask. */ ++#define XCL_BPER07_bp 7 /* BTC0 Period bit 7 position. */ ++ ++#define XCL_BCAPT0_gm 0xFF /* BTC0 Capture Value Byte group mask. */ ++#define XCL_BCAPT0_gp 0 /* BTC0 Capture Value Byte group position. */ ++#define XCL_BCAPT00_bm (1<<0) /* BTC0 Capture Value Byte bit 0 mask. */ ++#define XCL_BCAPT00_bp 0 /* BTC0 Capture Value Byte bit 0 position. */ ++#define XCL_BCAPT01_bm (1<<1) /* BTC0 Capture Value Byte bit 1 mask. */ ++#define XCL_BCAPT01_bp 1 /* BTC0 Capture Value Byte bit 1 position. */ ++#define XCL_BCAPT02_bm (1<<2) /* BTC0 Capture Value Byte bit 2 mask. */ ++#define XCL_BCAPT02_bp 2 /* BTC0 Capture Value Byte bit 2 position. */ ++#define XCL_BCAPT03_bm (1<<3) /* BTC0 Capture Value Byte bit 3 mask. */ ++#define XCL_BCAPT03_bp 3 /* BTC0 Capture Value Byte bit 3 position. */ ++#define XCL_BCAPT04_bm (1<<4) /* BTC0 Capture Value Byte bit 4 mask. */ ++#define XCL_BCAPT04_bp 4 /* BTC0 Capture Value Byte bit 4 position. */ ++#define XCL_BCAPT05_bm (1<<5) /* BTC0 Capture Value Byte bit 5 mask. */ ++#define XCL_BCAPT05_bp 5 /* BTC0 Capture Value Byte bit 5 position. */ ++#define XCL_BCAPT06_bm (1<<6) /* BTC0 Capture Value Byte bit 6 mask. */ ++#define XCL_BCAPT06_bp 6 /* BTC0 Capture Value Byte bit 6 position. */ ++#define XCL_BCAPT07_bm (1<<7) /* BTC0 Capture Value Byte bit 7 mask. */ ++#define XCL_BCAPT07_bp 7 /* BTC0 Capture Value Byte bit 7 position. */ ++ ++/* XCL.PERCAPTH bit masks and bit positions */ ++#define XCL_PERH_gm 0xFF /* TC16 High Byte Period group mask. */ ++#define XCL_PERH_gp 0 /* TC16 High Byte Period group position. */ ++#define XCL_PERH0_bm (1<<0) /* TC16 High Byte Period bit 0 mask. */ ++#define XCL_PERH0_bp 0 /* TC16 High Byte Period bit 0 position. */ ++#define XCL_PERH1_bm (1<<1) /* TC16 High Byte Period bit 1 mask. */ ++#define XCL_PERH1_bp 1 /* TC16 High Byte Period bit 1 position. */ ++#define XCL_PERH2_bm (1<<2) /* TC16 High Byte Period bit 2 mask. */ ++#define XCL_PERH2_bp 2 /* TC16 High Byte Period bit 2 position. */ ++#define XCL_PERH3_bm (1<<3) /* TC16 High Byte Period bit 3 mask. */ ++#define XCL_PERH3_bp 3 /* TC16 High Byte Period bit 3 position. */ ++#define XCL_PERH4_bm (1<<4) /* TC16 High Byte Period bit 4 mask. */ ++#define XCL_PERH4_bp 4 /* TC16 High Byte Period bit 4 position. */ ++#define XCL_PERH5_bm (1<<5) /* TC16 High Byte Period bit 5 mask. */ ++#define XCL_PERH5_bp 5 /* TC16 High Byte Period bit 5 position. */ ++#define XCL_PERH6_bm (1<<6) /* TC16 High Byte Period bit 6 mask. */ ++#define XCL_PERH6_bp 6 /* TC16 High Byte Period bit 6 position. */ ++#define XCL_PERH7_bm (1<<7) /* TC16 High Byte Period bit 7 mask. */ ++#define XCL_PERH7_bp 7 /* TC16 High Byte Period bit 7 position. */ ++ ++#define XCL_CAPTH_gm 0xFF /* TC16 Capture Value High Byte group mask. */ ++#define XCL_CAPTH_gp 0 /* TC16 Capture Value High Byte group position. */ ++#define XCL_CAPTH0_bm (1<<0) /* TC16 Capture Value High Byte bit 0 mask. */ ++#define XCL_CAPTH0_bp 0 /* TC16 Capture Value High Byte bit 0 position. */ ++#define XCL_CAPTH1_bm (1<<1) /* TC16 Capture Value High Byte bit 1 mask. */ ++#define XCL_CAPTH1_bp 1 /* TC16 Capture Value High Byte bit 1 position. */ ++#define XCL_CAPTH2_bm (1<<2) /* TC16 Capture Value High Byte bit 2 mask. */ ++#define XCL_CAPTH2_bp 2 /* TC16 Capture Value High Byte bit 2 position. */ ++#define XCL_CAPTH3_bm (1<<3) /* TC16 Capture Value High Byte bit 3 mask. */ ++#define XCL_CAPTH3_bp 3 /* TC16 Capture Value High Byte bit 3 position. */ ++#define XCL_CAPTH4_bm (1<<4) /* TC16 Capture Value High Byte bit 4 mask. */ ++#define XCL_CAPTH4_bp 4 /* TC16 Capture Value High Byte bit 4 position. */ ++#define XCL_CAPTH5_bm (1<<5) /* TC16 Capture Value High Byte bit 5 mask. */ ++#define XCL_CAPTH5_bp 5 /* TC16 Capture Value High Byte bit 5 position. */ ++#define XCL_CAPTH6_bm (1<<6) /* TC16 Capture Value High Byte bit 6 mask. */ ++#define XCL_CAPTH6_bp 6 /* TC16 Capture Value High Byte bit 6 position. */ ++#define XCL_CAPTH7_bm (1<<7) /* TC16 Capture Value High Byte bit 7 mask. */ ++#define XCL_CAPTH7_bp 7 /* TC16 Capture Value High Byte bit 7 position. */ ++ ++#define XCL_BPER1_gm 0xFF /* BTC1 Period group mask. */ ++#define XCL_BPER1_gp 0 /* BTC1 Period group position. */ ++#define XCL_BPER10_bm (1<<0) /* BTC1 Period bit 0 mask. */ ++#define XCL_BPER10_bp 0 /* BTC1 Period bit 0 position. */ ++#define XCL_BPER11_bm (1<<1) /* BTC1 Period bit 1 mask. */ ++#define XCL_BPER11_bp 1 /* BTC1 Period bit 1 position. */ ++#define XCL_BPER12_bm (1<<2) /* BTC1 Period bit 2 mask. */ ++#define XCL_BPER12_bp 2 /* BTC1 Period bit 2 position. */ ++#define XCL_BPER13_bm (1<<3) /* BTC1 Period bit 3 mask. */ ++#define XCL_BPER13_bp 3 /* BTC1 Period bit 3 position. */ ++#define XCL_BPER14_bm (1<<4) /* BTC1 Period bit 4 mask. */ ++#define XCL_BPER14_bp 4 /* BTC1 Period bit 4 position. */ ++#define XCL_BPER15_bm (1<<5) /* BTC1 Period bit 5 mask. */ ++#define XCL_BPER15_bp 5 /* BTC1 Period bit 5 position. */ ++#define XCL_BPER16_bm (1<<6) /* BTC1 Period bit 6 mask. */ ++#define XCL_BPER16_bp 6 /* BTC1 Period bit 6 position. */ ++#define XCL_BPER17_bm (1<<7) /* BTC1 Period bit 7 mask. */ ++#define XCL_BPER17_bp 7 /* BTC1 Period bit 7 position. */ ++ ++#define XCL_BCAPT1_gm 0xFF /* BTC1 Capture Value Byte group mask. */ ++#define XCL_BCAPT1_gp 0 /* BTC1 Capture Value Byte group position. */ ++#define XCL_BCAPT10_bm (1<<0) /* BTC1 Capture Value Byte bit 0 mask. */ ++#define XCL_BCAPT10_bp 0 /* BTC1 Capture Value Byte bit 0 position. */ ++#define XCL_BCAPT11_bm (1<<1) /* BTC1 Capture Value Byte bit 1 mask. */ ++#define XCL_BCAPT11_bp 1 /* BTC1 Capture Value Byte bit 1 position. */ ++#define XCL_BCAPT12_bm (1<<2) /* BTC1 Capture Value Byte bit 2 mask. */ ++#define XCL_BCAPT12_bp 2 /* BTC1 Capture Value Byte bit 2 position. */ ++#define XCL_BCAPT13_bm (1<<3) /* BTC1 Capture Value Byte bit 3 mask. */ ++#define XCL_BCAPT13_bp 3 /* BTC1 Capture Value Byte bit 3 position. */ ++#define XCL_BCAPT14_bm (1<<4) /* BTC1 Capture Value Byte bit 4 mask. */ ++#define XCL_BCAPT14_bp 4 /* BTC1 Capture Value Byte bit 4 position. */ ++#define XCL_BCAPT15_bm (1<<5) /* BTC1 Capture Value Byte bit 5 mask. */ ++#define XCL_BCAPT15_bp 5 /* BTC1 Capture Value Byte bit 5 position. */ ++#define XCL_BCAPT16_bm (1<<6) /* BTC1 Capture Value Byte bit 6 mask. */ ++#define XCL_BCAPT16_bp 6 /* BTC1 Capture Value Byte bit 6 position. */ ++#define XCL_BCAPT17_bm (1<<7) /* BTC1 Capture Value Byte bit 7 mask. */ ++#define XCL_BCAPT17_bp 7 /* BTC1 Capture Value Byte bit 7 position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_BRIDGEEN_bm 0x80 /* Bridge Enable bit mask. */ ++#define TWI_BRIDGEEN_bp 7 /* Bridge Enable bit position. */ ++ ++#define TWI_SFMPEN_bm 0x40 /* Slave Fast Mode Plus Enable bit mask. */ ++#define TWI_SFMPEN_bp 6 /* Slave Fast Mode Plus Enable bit position. */ ++ ++#define TWI_SSDAHOLD_gm 0x30 /* Slave SDA Hold Time Enable group mask. */ ++#define TWI_SSDAHOLD_gp 4 /* Slave SDA Hold Time Enable group position. */ ++#define TWI_SSDAHOLD0_bm (1<<4) /* Slave SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SSDAHOLD0_bp 4 /* Slave SDA Hold Time Enable bit 0 position. */ ++#define TWI_SSDAHOLD1_bm (1<<5) /* Slave SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SSDAHOLD1_bp 5 /* Slave SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_FMPEN_bm 0x08 /* FMPLUS Enable bit mask. */ ++#define TWI_FMPEN_bp 3 /* FMPLUS Enable bit position. */ ++ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++#define TWI_MASTER_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ ++#define TWI_MASTER_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ ++ ++#define TWI_MASTER_TSEXTEN_bm 0x20 /* Slave Extend Timeout Enable bit mask. */ ++#define TWI_MASTER_TSEXTEN_bp 5 /* Slave Extend Timeout Enable bit position. */ ++ ++#define TWI_MASTER_TMEXTEN_bm 0x40 /* Master Extend Timeout Enable bit mask. */ ++#define TWI_MASTER_TMEXTEN_bp 6 /* Master Extend Timeout Enable bit position. */ ++ ++#define TWI_MASTER_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ ++#define TWI_MASTER_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++#define TWI_SLAVE_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ ++#define TWI_SLAVE_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ ++ ++#define TWI_SLAVE_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ ++#define TWI_SLAVE_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI_TIMEOUT.TOS bit masks and bit positions */ ++#define TWI_TIMEOUT_TTOUTMIF_bm 0x01 /* Master Ttimeout Interrupt Flag bit mask. */ ++#define TWI_TIMEOUT_TTOUTMIF_bp 0 /* Master Ttimeout Interrupt Flag bit position. */ ++ ++#define TWI_TIMEOUT_TSEXTIF_bm 0x02 /* Slave Extend Interrupt Flag bit mask. */ ++#define TWI_TIMEOUT_TSEXTIF_bp 1 /* Slave Extend Interrupt Flag bit position. */ ++ ++#define TWI_TIMEOUT_TMEXTIF_bm 0x04 /* Master Extend Interrupt Flag bit mask. */ ++#define TWI_TIMEOUT_TMEXTIF_bp 2 /* Master Extend Interrupt Flag bit position. */ ++ ++#define TWI_TIMEOUT_TTOUTSIF_bm 0x10 /* Slave Ttimeout Interrupt Flag bit mask. */ ++#define TWI_TIMEOUT_TTOUTSIF_bp 4 /* Slave Ttimeout Interrupt Flag bit position. */ ++ ++/* TWI_TIMEOUT.TOCONF bit masks and bit positions */ ++#define TWI_TIMEOUT_TTOUTMSEL_gm 0x07 /* Master Ttimeout Select group mask. */ ++#define TWI_TIMEOUT_TTOUTMSEL_gp 0 /* Master Ttimeout Select group position. */ ++#define TWI_TIMEOUT_TTOUTMSEL0_bm (1<<0) /* Master Ttimeout Select bit 0 mask. */ ++#define TWI_TIMEOUT_TTOUTMSEL0_bp 0 /* Master Ttimeout Select bit 0 position. */ ++#define TWI_TIMEOUT_TTOUTMSEL1_bm (1<<1) /* Master Ttimeout Select bit 1 mask. */ ++#define TWI_TIMEOUT_TTOUTMSEL1_bp 1 /* Master Ttimeout Select bit 1 position. */ ++#define TWI_TIMEOUT_TTOUTMSEL2_bm (1<<2) /* Master Ttimeout Select bit 2 mask. */ ++#define TWI_TIMEOUT_TTOUTMSEL2_bp 2 /* Master Ttimeout Select bit 2 position. */ ++ ++#define TWI_TIMEOUT_TMSEXTSEL_gm 0x18 /* Master/Slave Timeout Select group mask. */ ++#define TWI_TIMEOUT_TMSEXTSEL_gp 3 /* Master/Slave Timeout Select group position. */ ++#define TWI_TIMEOUT_TMSEXTSEL0_bm (1<<3) /* Master/Slave Timeout Select bit 0 mask. */ ++#define TWI_TIMEOUT_TMSEXTSEL0_bp 3 /* Master/Slave Timeout Select bit 0 position. */ ++#define TWI_TIMEOUT_TMSEXTSEL1_bm (1<<4) /* Master/Slave Timeout Select bit 1 mask. */ ++#define TWI_TIMEOUT_TMSEXTSEL1_bp 4 /* Master/Slave Timeout Select bit 1 position. */ ++ ++#define TWI_TIMEOUT_TTOUTSSEL_gm 0xE0 /* Slave Ttimeout Select group mask. */ ++#define TWI_TIMEOUT_TTOUTSSEL_gp 5 /* Slave Ttimeout Select group position. */ ++#define TWI_TIMEOUT_TTOUTSSEL0_bm (1<<5) /* Slave Ttimeout Select bit 0 mask. */ ++#define TWI_TIMEOUT_TTOUTSSEL0_bp 5 /* Slave Ttimeout Select bit 0 position. */ ++#define TWI_TIMEOUT_TTOUTSSEL1_bm (1<<6) /* Slave Ttimeout Select bit 1 mask. */ ++#define TWI_TIMEOUT_TTOUTSSEL1_bp 6 /* Slave Ttimeout Select bit 1 position. */ ++#define TWI_TIMEOUT_TTOUTSSEL2_bm (1<<7) /* Slave Ttimeout Select bit 2 mask. */ ++#define TWI_TIMEOUT_TTOUTSSEL2_bp 7 /* Slave Ttimeout Select bit 2 position. */ ++ ++/* PORT - Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INTLVL_gm 0x03 /* Port Interrupt Level group mask. */ ++#define PORT_INTLVL_gp 0 /* Port Interrupt Level group position. */ ++#define PORT_INTLVL0_bm (1<<0) /* Port Interrupt Level bit 0 mask. */ ++#define PORT_INTLVL0_bp 0 /* Port Interrupt Level bit 0 position. */ ++#define PORT_INTLVL1_bm (1<<1) /* Port Interrupt Level bit 1 mask. */ ++#define PORT_INTLVL1_bp 1 /* Port Interrupt Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT7IF_bm 0x80 /* Pin 7 Interrupt Flag bit mask. */ ++#define PORT_INT7IF_bp 7 /* Pin 7 Interrupt Flag bit position. */ ++ ++#define PORT_INT6IF_bm 0x40 /* Pin 6 Interrupt Flag bit mask. */ ++#define PORT_INT6IF_bp 6 /* Pin 6 Interrupt Flag bit position. */ ++ ++#define PORT_INT5IF_bm 0x20 /* Pin 5 Interrupt Flag bit mask. */ ++#define PORT_INT5IF_bp 5 /* Pin 5 Interrupt Flag bit position. */ ++ ++#define PORT_INT4IF_bm 0x10 /* Pin 4 Interrupt Flag bit mask. */ ++#define PORT_INT4IF_bp 4 /* Pin 4 Interrupt Flag bit position. */ ++ ++#define PORT_INT3IF_bm 0x08 /* Pin 3 Interrupt Flag bit mask. */ ++#define PORT_INT3IF_bp 3 /* Pin 3 Interrupt Flag bit position. */ ++ ++#define PORT_INT2IF_bm 0x04 /* Pin 2 Interrupt Flag bit mask. */ ++#define PORT_INT2IF_bp 2 /* Pin 2 Interrupt Flag bit position. */ ++ ++#define PORT_INT1IF_bm 0x02 /* Pin 1 Interrupt Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Pin 1 Interrupt Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Pin 0 Interrupt Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Pin 0 Interrupt Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_USART0_bm 0x10 /* Usart0 bit mask. */ ++#define PORT_USART0_bp 4 /* Usart0 bit position. */ ++ ++#define PORT_TC4D_bm 0x08 /* Timer/Counter 4 Output Compare D bit mask. */ ++#define PORT_TC4D_bp 3 /* Timer/Counter 4 Output Compare D bit position. */ ++ ++#define PORT_TC4C_bm 0x04 /* Timer/Counter 4 Output Compare C bit mask. */ ++#define PORT_TC4C_bp 2 /* Timer/Counter 4 Output Compare C bit position. */ ++ ++#define PORT_TC4B_bm 0x02 /* Timer/Counter 4 Output Compare B bit mask. */ ++#define PORT_TC4B_bp 1 /* Timer/Counter 4 Output Compare B bit position. */ ++ ++#define PORT_TC4A_bm 0x01 /* Timer/Counter 4 Output Compare A bit mask. */ ++#define PORT_TC4A_bp 0 /* Timer/Counter 4 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC4.CTRLA bit masks and bit positions */ ++#define TC4_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ ++#define TC4_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ ++ ++#define TC4_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ ++#define TC4_EVSTART_bp 5 /* Start on Next Event bit position. */ ++ ++#define TC4_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ ++#define TC4_UPSTOP_bp 4 /* Stop on Next Update bit position. */ ++ ++#define TC4_CLKSEL_gm 0x0F /* Clock Select group mask. */ ++#define TC4_CLKSEL_gp 0 /* Clock Select group position. */ ++#define TC4_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ ++#define TC4_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ ++#define TC4_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ ++#define TC4_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ ++#define TC4_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ ++#define TC4_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ ++#define TC4_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ ++#define TC4_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ ++ ++/* TC4.CTRLB bit masks and bit positions */ ++#define TC4_BYTEM_gm 0xC0 /* Byte Mode group mask. */ ++#define TC4_BYTEM_gp 6 /* Byte Mode group position. */ ++#define TC4_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ ++#define TC4_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ ++#define TC4_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ ++#define TC4_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ ++ ++#define TC4_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ ++#define TC4_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ ++#define TC4_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ ++#define TC4_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ ++#define TC4_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ ++#define TC4_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ ++ ++#define TC4_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ ++#define TC4_WGMODE_gp 0 /* Waveform Generation Mode group position. */ ++#define TC4_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ ++#define TC4_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ ++#define TC4_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ ++#define TC4_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ ++#define TC4_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ ++#define TC4_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ ++ ++/* TC4.CTRLC bit masks and bit positions */ ++#define TC4_POLD_bm 0x80 /* Channel D Output Polarity bit mask. */ ++#define TC4_POLD_bp 7 /* Channel D Output Polarity bit position. */ ++ ++#define TC4_POLC_bm 0x40 /* Channel C Output Polarity bit mask. */ ++#define TC4_POLC_bp 6 /* Channel C Output Polarity bit position. */ ++ ++#define TC4_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ ++#define TC4_POLB_bp 5 /* Channel B Output Polarity bit position. */ ++ ++#define TC4_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ ++#define TC4_POLA_bp 4 /* Channel A Output Polarity bit position. */ ++ ++#define TC4_CMPD_bm 0x08 /* Channel D Compare Output Value bit mask. */ ++#define TC4_CMPD_bp 3 /* Channel D Compare Output Value bit position. */ ++ ++#define TC4_CMPC_bm 0x04 /* Channel C Compare Output Value bit mask. */ ++#define TC4_CMPC_bp 2 /* Channel C Compare Output Value bit position. */ ++ ++#define TC4_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ ++#define TC4_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ ++ ++#define TC4_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ ++#define TC4_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ ++ ++#define TC4_HCMPD_bm 0x80 /* High Channel D Compare Output Value bit mask. */ ++#define TC4_HCMPD_bp 7 /* High Channel D Compare Output Value bit position. */ ++ ++#define TC4_HCMPC_bm 0x40 /* High Channel C Compare Output Value bit mask. */ ++#define TC4_HCMPC_bp 6 /* High Channel C Compare Output Value bit position. */ ++ ++#define TC4_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ ++#define TC4_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ ++ ++#define TC4_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ ++#define TC4_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ ++ ++#define TC4_LCMPD_bm 0x08 /* Low Channel D Compare Output Value bit mask. */ ++#define TC4_LCMPD_bp 3 /* Low Channel D Compare Output Value bit position. */ ++ ++#define TC4_LCMPC_bm 0x04 /* Low Channel C Compare Output Value bit mask. */ ++#define TC4_LCMPC_bp 2 /* Low Channel C Compare Output Value bit position. */ ++ ++#define TC4_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ ++#define TC4_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ ++ ++#define TC4_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ ++#define TC4_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ ++ ++/* TC4.CTRLD bit masks and bit positions */ ++#define TC4_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC4_EVACT_gp 5 /* Event Action group position. */ ++#define TC4_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC4_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC4_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC4_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC4_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC4_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC4_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC4_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC4_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC4_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC4_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC4_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC4_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC4_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC4_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC4_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC4_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC4_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC4.CTRLE bit masks and bit positions */ ++#define TC4_CCDMODE_gm 0xC0 /* Channel D Compare or Capture Mode group mask. */ ++#define TC4_CCDMODE_gp 6 /* Channel D Compare or Capture Mode group position. */ ++#define TC4_CCDMODE0_bm (1<<6) /* Channel D Compare or Capture Mode bit 0 mask. */ ++#define TC4_CCDMODE0_bp 6 /* Channel D Compare or Capture Mode bit 0 position. */ ++#define TC4_CCDMODE1_bm (1<<7) /* Channel D Compare or Capture Mode bit 1 mask. */ ++#define TC4_CCDMODE1_bp 7 /* Channel D Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_CCCMODE_gm 0x30 /* Channel C Compare or Capture Mode group mask. */ ++#define TC4_CCCMODE_gp 4 /* Channel C Compare or Capture Mode group position. */ ++#define TC4_CCCMODE0_bm (1<<4) /* Channel C Compare or Capture Mode bit 0 mask. */ ++#define TC4_CCCMODE0_bp 4 /* Channel C Compare or Capture Mode bit 0 position. */ ++#define TC4_CCCMODE1_bm (1<<5) /* Channel C Compare or Capture Mode bit 1 mask. */ ++#define TC4_CCCMODE1_bp 5 /* Channel C Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ ++#define TC4_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ ++#define TC4_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ ++#define TC4_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ ++#define TC4_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ ++#define TC4_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ ++#define TC4_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ ++#define TC4_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ ++#define TC4_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ ++#define TC4_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ ++#define TC4_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_LCCDMODE_gm 0xC0 /* Channel Low D Compare or Capture Mode group mask. */ ++#define TC4_LCCDMODE_gp 6 /* Channel Low D Compare or Capture Mode group position. */ ++#define TC4_LCCDMODE0_bm (1<<6) /* Channel Low D Compare or Capture Mode bit 0 mask. */ ++#define TC4_LCCDMODE0_bp 6 /* Channel Low D Compare or Capture Mode bit 0 position. */ ++#define TC4_LCCDMODE1_bm (1<<7) /* Channel Low D Compare or Capture Mode bit 1 mask. */ ++#define TC4_LCCDMODE1_bp 7 /* Channel Low D Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_LCCCMODE_gm 0x30 /* Channel Low C Compare or Capture Mode group mask. */ ++#define TC4_LCCCMODE_gp 4 /* Channel Low C Compare or Capture Mode group position. */ ++#define TC4_LCCCMODE0_bm (1<<4) /* Channel Low C Compare or Capture Mode bit 0 mask. */ ++#define TC4_LCCCMODE0_bp 4 /* Channel Low C Compare or Capture Mode bit 0 position. */ ++#define TC4_LCCCMODE1_bm (1<<5) /* Channel Low C Compare or Capture Mode bit 1 mask. */ ++#define TC4_LCCCMODE1_bp 5 /* Channel Low C Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ ++#define TC4_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ ++#define TC4_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ ++#define TC4_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ ++#define TC4_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ ++#define TC4_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ ++#define TC4_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ ++#define TC4_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ ++#define TC4_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ ++#define TC4_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ ++#define TC4_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ ++ ++/* TC4.CTRLF bit masks and bit positions */ ++#define TC4_HCCDMODE_gm 0xC0 /* Channel High D Compare or Capture Mode group mask. */ ++#define TC4_HCCDMODE_gp 6 /* Channel High D Compare or Capture Mode group position. */ ++#define TC4_HCCDMODE0_bm (1<<6) /* Channel High D Compare or Capture Mode bit 0 mask. */ ++#define TC4_HCCDMODE0_bp 6 /* Channel High D Compare or Capture Mode bit 0 position. */ ++#define TC4_HCCDMODE1_bm (1<<7) /* Channel High D Compare or Capture Mode bit 1 mask. */ ++#define TC4_HCCDMODE1_bp 7 /* Channel High D Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_HCCCMODE_gm 0x30 /* Channel High C Compare or Capture Mode group mask. */ ++#define TC4_HCCCMODE_gp 4 /* Channel High C Compare or Capture Mode group position. */ ++#define TC4_HCCCMODE0_bm (1<<4) /* Channel High C Compare or Capture Mode bit 0 mask. */ ++#define TC4_HCCCMODE0_bp 4 /* Channel High C Compare or Capture Mode bit 0 position. */ ++#define TC4_HCCCMODE1_bm (1<<5) /* Channel High C Compare or Capture Mode bit 1 mask. */ ++#define TC4_HCCCMODE1_bp 5 /* Channel High C Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ ++#define TC4_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ ++#define TC4_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ ++#define TC4_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ ++#define TC4_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ ++#define TC4_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ ++#define TC4_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ ++#define TC4_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ ++#define TC4_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ ++#define TC4_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ ++#define TC4_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ ++ ++/* TC4.INTCTRLA bit masks and bit positions */ ++#define TC4_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ ++#define TC4_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ ++#define TC4_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ ++#define TC4_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ ++#define TC4_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ ++#define TC4_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ ++ ++#define TC4_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ ++#define TC4_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ ++#define TC4_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ ++#define TC4_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ ++#define TC4_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ ++#define TC4_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ ++ ++#define TC4_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ ++#define TC4_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ ++#define TC4_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ ++#define TC4_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ ++#define TC4_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ ++#define TC4_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ ++ ++/* TC4.INTCTRLB bit masks and bit positions */ ++#define TC4_CCDINTLVL_gm 0xC0 /* Channel D Compare or Capture Interrupt Level group mask. */ ++#define TC4_CCDINTLVL_gp 6 /* Channel D Compare or Capture Interrupt Level group position. */ ++#define TC4_CCDINTLVL0_bm (1<<6) /* Channel D Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC4_CCDINTLVL0_bp 6 /* Channel D Compare or Capture Interrupt Level bit 0 position. */ ++#define TC4_CCDINTLVL1_bm (1<<7) /* Channel D Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC4_CCDINTLVL1_bp 7 /* Channel D Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC4_CCCINTLVL_gm 0x30 /* Channel C Compare or Capture Interrupt Level group mask. */ ++#define TC4_CCCINTLVL_gp 4 /* Channel C Compare or Capture Interrupt Level group position. */ ++#define TC4_CCCINTLVL0_bm (1<<4) /* Channel C Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC4_CCCINTLVL0_bp 4 /* Channel C Compare or Capture Interrupt Level bit 0 position. */ ++#define TC4_CCCINTLVL1_bm (1<<5) /* Channel C Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC4_CCCINTLVL1_bp 5 /* Channel C Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC4_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ ++#define TC4_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ ++#define TC4_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC4_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ ++#define TC4_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC4_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC4_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ ++#define TC4_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ ++#define TC4_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC4_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ ++#define TC4_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC4_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC4_LCCDINTLVL_gm 0xC0 /* Channel Low D Compare or Capture Interrupt Level group mask. */ ++#define TC4_LCCDINTLVL_gp 6 /* Channel Low D Compare or Capture Interrupt Level group position. */ ++#define TC4_LCCDINTLVL0_bm (1<<6) /* Channel Low D Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC4_LCCDINTLVL0_bp 6 /* Channel Low D Compare or Capture Interrupt Level bit 0 position. */ ++#define TC4_LCCDINTLVL1_bm (1<<7) /* Channel Low D Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC4_LCCDINTLVL1_bp 7 /* Channel Low D Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC4_LCCCINTLVL_gm 0x30 /* Channel Low C Compare or Capture Interrupt Level group mask. */ ++#define TC4_LCCCINTLVL_gp 4 /* Channel Low C Compare or Capture Interrupt Level group position. */ ++#define TC4_LCCCINTLVL0_bm (1<<4) /* Channel Low C Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC4_LCCCINTLVL0_bp 4 /* Channel Low C Compare or Capture Interrupt Level bit 0 position. */ ++#define TC4_LCCCINTLVL1_bm (1<<5) /* Channel Low C Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC4_LCCCINTLVL1_bp 5 /* Channel Low C Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC4_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ ++#define TC4_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ ++#define TC4_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC4_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ ++#define TC4_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC4_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC4_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ ++#define TC4_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ ++#define TC4_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC4_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ ++#define TC4_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC4_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ ++ ++/* TC4.CTRLGCLR bit masks and bit positions */ ++#define TC4_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ ++#define TC4_STOP_bp 5 /* Timer/Counter Stop bit position. */ ++ ++#define TC4_CMD_gm 0x0C /* Command group mask. */ ++#define TC4_CMD_gp 2 /* Command group position. */ ++#define TC4_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC4_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC4_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC4_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC4_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC4_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC4_DIR_bm 0x01 /* Counter Direction bit mask. */ ++#define TC4_DIR_bp 0 /* Counter Direction bit position. */ ++ ++/* TC4.CTRLGSET bit masks and bit positions */ ++/* TC4_STOP Predefined. */ ++/* TC4_STOP Predefined. */ ++ ++/* TC4_CMD Predefined. */ ++/* TC4_CMD Predefined. */ ++ ++/* TC4_LUPD Predefined. */ ++/* TC4_LUPD Predefined. */ ++ ++/* TC4_DIR Predefined. */ ++/* TC4_DIR Predefined. */ ++ ++/* TC4.CTRLHCLR bit masks and bit positions */ ++#define TC4_CCDBV_bm 0x10 /* Channel D Compare or Capture Buffer Valid bit mask. */ ++#define TC4_CCDBV_bp 4 /* Channel D Compare or Capture Buffer Valid bit position. */ ++ ++#define TC4_CCCBV_bm 0x08 /* Channel C Compare or Capture Buffer Valid bit mask. */ ++#define TC4_CCCBV_bp 3 /* Channel C Compare or Capture Buffer Valid bit position. */ ++ ++#define TC4_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ ++#define TC4_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ ++ ++#define TC4_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ ++#define TC4_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ ++ ++#define TC4_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC4_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++#define TC4_LCCDBV_bm 0x10 /* Channel Low D Compare or Capture Buffer Valid bit mask. */ ++#define TC4_LCCDBV_bp 4 /* Channel Low D Compare or Capture Buffer Valid bit position. */ ++ ++#define TC4_LCCCBV_bm 0x08 /* Channel Low C Compare or Capture Buffer Valid bit mask. */ ++#define TC4_LCCCBV_bp 3 /* Channel Low C Compare or Capture Buffer Valid bit position. */ ++ ++#define TC4_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ ++#define TC4_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ ++ ++#define TC4_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ ++#define TC4_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ ++ ++#define TC4_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ ++#define TC4_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ ++ ++/* TC4.CTRLHSET bit masks and bit positions */ ++/* TC4_CCDBV Predefined. */ ++/* TC4_CCDBV Predefined. */ ++ ++/* TC4_CCCBV Predefined. */ ++/* TC4_CCCBV Predefined. */ ++ ++/* TC4_CCBBV Predefined. */ ++/* TC4_CCBBV Predefined. */ ++ ++/* TC4_CCABV Predefined. */ ++/* TC4_CCABV Predefined. */ ++ ++/* TC4_PERBV Predefined. */ ++/* TC4_PERBV Predefined. */ ++ ++/* TC4_LCCDBV Predefined. */ ++/* TC4_LCCDBV Predefined. */ ++ ++/* TC4_LCCCBV Predefined. */ ++/* TC4_LCCCBV Predefined. */ ++ ++/* TC4_LCCBBV Predefined. */ ++/* TC4_LCCBBV Predefined. */ ++ ++/* TC4_LCCABV Predefined. */ ++/* TC4_LCCABV Predefined. */ ++ ++/* TC4_LPERBV Predefined. */ ++/* TC4_LPERBV Predefined. */ ++ ++/* TC4.INTFLAGS bit masks and bit positions */ ++#define TC4_CCDIF_bm 0x80 /* Channel D Compare or Capture Interrupt Flag bit mask. */ ++#define TC4_CCDIF_bp 7 /* Channel D Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC4_CCCIF_bm 0x40 /* Channel C Compare or Capture Interrupt Flag bit mask. */ ++#define TC4_CCCIF_bp 6 /* Channel C Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC4_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ ++#define TC4_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC4_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ ++#define TC4_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC4_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ ++#define TC4_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ ++ ++#define TC4_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC4_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC4_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ ++#define TC4_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ ++ ++#define TC4_LCCDIF_bm 0x80 /* Channel Low D Compare or Capture Interrupt Flag bit mask. */ ++#define TC4_LCCDIF_bp 7 /* Channel Low D Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC4_LCCCIF_bm 0x40 /* Channel Low C Compare or Capture Interrupt Flag bit mask. */ ++#define TC4_LCCCIF_bp 6 /* Channel Low C Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC4_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ ++#define TC4_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC4_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ ++#define TC4_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ ++ ++/* TC5.CTRLA bit masks and bit positions */ ++#define TC5_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ ++#define TC5_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ ++ ++#define TC5_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ ++#define TC5_EVSTART_bp 5 /* Start on Next Event bit position. */ ++ ++#define TC5_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ ++#define TC5_UPSTOP_bp 4 /* Stop on Next Update bit position. */ ++ ++#define TC5_CLKSEL_gm 0x0F /* Clock Select group mask. */ ++#define TC5_CLKSEL_gp 0 /* Clock Select group position. */ ++#define TC5_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ ++#define TC5_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ ++#define TC5_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ ++#define TC5_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ ++#define TC5_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ ++#define TC5_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ ++#define TC5_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ ++#define TC5_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ ++ ++/* TC5.CTRLB bit masks and bit positions */ ++#define TC5_BYTEM_gm 0xC0 /* Byte Mode group mask. */ ++#define TC5_BYTEM_gp 6 /* Byte Mode group position. */ ++#define TC5_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ ++#define TC5_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ ++#define TC5_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ ++#define TC5_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ ++ ++#define TC5_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ ++#define TC5_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ ++#define TC5_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ ++#define TC5_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ ++#define TC5_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ ++#define TC5_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ ++ ++#define TC5_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ ++#define TC5_WGMODE_gp 0 /* Waveform Generation Mode group position. */ ++#define TC5_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ ++#define TC5_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ ++#define TC5_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ ++#define TC5_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ ++#define TC5_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ ++#define TC5_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ ++ ++/* TC5.CTRLC bit masks and bit positions */ ++#define TC5_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ ++#define TC5_POLB_bp 5 /* Channel B Output Polarity bit position. */ ++ ++#define TC5_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ ++#define TC5_POLA_bp 4 /* Channel A Output Polarity bit position. */ ++ ++#define TC5_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ ++#define TC5_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ ++ ++#define TC5_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ ++#define TC5_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ ++ ++#define TC5_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ ++#define TC5_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ ++ ++#define TC5_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ ++#define TC5_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ ++ ++#define TC5_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ ++#define TC5_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ ++ ++#define TC5_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ ++#define TC5_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ ++ ++/* TC5.CTRLD bit masks and bit positions */ ++#define TC5_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC5_EVACT_gp 5 /* Event Action group position. */ ++#define TC5_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC5_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC5_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC5_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC5_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC5_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC5_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC5_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC5_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC5_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC5_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC5_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC5_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC5_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC5_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC5_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC5_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC5_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC5.CTRLE bit masks and bit positions */ ++#define TC5_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ ++#define TC5_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ ++#define TC5_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ ++#define TC5_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ ++#define TC5_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ ++#define TC5_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ ++ ++#define TC5_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ ++#define TC5_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ ++#define TC5_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ ++#define TC5_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ ++#define TC5_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ ++#define TC5_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ ++ ++#define TC5_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ ++#define TC5_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ ++#define TC5_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ ++#define TC5_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ ++#define TC5_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ ++#define TC5_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ ++ ++#define TC5_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ ++#define TC5_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ ++#define TC5_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ ++#define TC5_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ ++#define TC5_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ ++#define TC5_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ ++ ++/* TC5.CTRLF bit masks and bit positions */ ++#define TC5_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ ++#define TC5_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ ++#define TC5_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ ++#define TC5_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ ++#define TC5_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ ++#define TC5_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ ++ ++#define TC5_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ ++#define TC5_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ ++#define TC5_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ ++#define TC5_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ ++#define TC5_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ ++#define TC5_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ ++ ++/* TC5.INTCTRLA bit masks and bit positions */ ++#define TC5_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ ++#define TC5_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ ++#define TC5_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ ++#define TC5_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ ++#define TC5_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ ++#define TC5_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ ++ ++#define TC5_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ ++#define TC5_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ ++#define TC5_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ ++#define TC5_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ ++#define TC5_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ ++#define TC5_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ ++ ++#define TC5_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ ++#define TC5_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ ++#define TC5_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ ++#define TC5_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ ++#define TC5_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ ++#define TC5_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ ++ ++/* TC5.INTCTRLB bit masks and bit positions */ ++#define TC5_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ ++#define TC5_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ ++#define TC5_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC5_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ ++#define TC5_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC5_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC5_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ ++#define TC5_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ ++#define TC5_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC5_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ ++#define TC5_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC5_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC5_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ ++#define TC5_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ ++#define TC5_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC5_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ ++#define TC5_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC5_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC5_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ ++#define TC5_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ ++#define TC5_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC5_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ ++#define TC5_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC5_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ ++ ++/* TC5.CTRLGCLR bit masks and bit positions */ ++#define TC5_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ ++#define TC5_STOP_bp 5 /* Timer/Counter Stop bit position. */ ++ ++#define TC5_CMD_gm 0x0C /* Command group mask. */ ++#define TC5_CMD_gp 2 /* Command group position. */ ++#define TC5_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC5_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC5_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC5_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC5_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC5_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC5_DIR_bm 0x01 /* Counter Direction bit mask. */ ++#define TC5_DIR_bp 0 /* Counter Direction bit position. */ ++ ++/* TC5.CTRLGSET bit masks and bit positions */ ++/* TC5_STOP Predefined. */ ++/* TC5_STOP Predefined. */ ++ ++/* TC5_CMD Predefined. */ ++/* TC5_CMD Predefined. */ ++ ++/* TC5_LUPD Predefined. */ ++/* TC5_LUPD Predefined. */ ++ ++/* TC5_DIR Predefined. */ ++/* TC5_DIR Predefined. */ ++ ++/* TC5.CTRLHCLR bit masks and bit positions */ ++#define TC5_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ ++#define TC5_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ ++ ++#define TC5_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ ++#define TC5_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ ++ ++#define TC5_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC5_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++#define TC5_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ ++#define TC5_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ ++ ++#define TC5_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ ++#define TC5_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ ++ ++#define TC5_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ ++#define TC5_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ ++ ++/* TC5.CTRLHSET bit masks and bit positions */ ++/* TC5_CCBBV Predefined. */ ++/* TC5_CCBBV Predefined. */ ++ ++/* TC5_CCABV Predefined. */ ++/* TC5_CCABV Predefined. */ ++ ++/* TC5_PERBV Predefined. */ ++/* TC5_PERBV Predefined. */ ++ ++/* TC5_LCCBBV Predefined. */ ++/* TC5_LCCBBV Predefined. */ ++ ++/* TC5_LCCABV Predefined. */ ++/* TC5_LCCABV Predefined. */ ++ ++/* TC5_LPERBV Predefined. */ ++/* TC5_LPERBV Predefined. */ ++ ++/* TC5.INTFLAGS bit masks and bit positions */ ++#define TC5_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ ++#define TC5_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC5_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ ++#define TC5_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC5_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ ++#define TC5_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ ++ ++#define TC5_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC5_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC5_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ ++#define TC5_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ ++ ++#define TC5_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ ++#define TC5_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC5_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ ++#define TC5_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ ++ ++/* FAULT - Fault Extension */ ++/* FAULT.CTRLA bit masks and bit positions */ ++#define FAULT_RAMP_gm 0xC0 /* Ramp Mode Selection group mask. */ ++#define FAULT_RAMP_gp 6 /* Ramp Mode Selection group position. */ ++#define FAULT_RAMP0_bm (1<<6) /* Ramp Mode Selection bit 0 mask. */ ++#define FAULT_RAMP0_bp 6 /* Ramp Mode Selection bit 0 position. */ ++#define FAULT_RAMP1_bm (1<<7) /* Ramp Mode Selection bit 1 mask. */ ++#define FAULT_RAMP1_bp 7 /* Ramp Mode Selection bit 1 position. */ ++ ++#define FAULT_FDDBD_bm 0x20 /* Fault on Debug Break Detection bit mask. */ ++#define FAULT_FDDBD_bp 5 /* Fault on Debug Break Detection bit position. */ ++ ++#define FAULT_PORTCTRL_bm 0x10 /* Port Control Mode bit mask. */ ++#define FAULT_PORTCTRL_bp 4 /* Port Control Mode bit position. */ ++ ++#define FAULT_FUSE_bm 0x08 /* Fuse State bit mask. */ ++#define FAULT_FUSE_bp 3 /* Fuse State bit position. */ ++ ++#define FAULT_FILTERE_bm 0x04 /* Fault E Digital Filter Selection bit mask. */ ++#define FAULT_FILTERE_bp 2 /* Fault E Digital Filter Selection bit position. */ ++ ++#define FAULT_SRCE_gm 0x03 /* Fault E Input selection group mask. */ ++#define FAULT_SRCE_gp 0 /* Fault E Input selection group position. */ ++#define FAULT_SRCE0_bm (1<<0) /* Fault E Input selection bit 0 mask. */ ++#define FAULT_SRCE0_bp 0 /* Fault E Input selection bit 0 position. */ ++#define FAULT_SRCE1_bm (1<<1) /* Fault E Input selection bit 1 mask. */ ++#define FAULT_SRCE1_bp 1 /* Fault E Input selection bit 1 position. */ ++ ++/* FAULT.CTRLB bit masks and bit positions */ ++#define FAULT_SOFTA_bm 0x80 /* Fault A Software Mode bit mask. */ ++#define FAULT_SOFTA_bp 7 /* Fault A Software Mode bit position. */ ++ ++#define FAULT_HALTA_gm 0x60 /* Fault A Halt Action group mask. */ ++#define FAULT_HALTA_gp 5 /* Fault A Halt Action group position. */ ++#define FAULT_HALTA0_bm (1<<5) /* Fault A Halt Action bit 0 mask. */ ++#define FAULT_HALTA0_bp 5 /* Fault A Halt Action bit 0 position. */ ++#define FAULT_HALTA1_bm (1<<6) /* Fault A Halt Action bit 1 mask. */ ++#define FAULT_HALTA1_bp 6 /* Fault A Halt Action bit 1 position. */ ++ ++#define FAULT_RESTARTA_bm 0x10 /* Fault A Restart Action bit mask. */ ++#define FAULT_RESTARTA_bp 4 /* Fault A Restart Action bit position. */ ++ ++#define FAULT_KEEPA_bm 0x08 /* Fault A Keep Action bit mask. */ ++#define FAULT_KEEPA_bp 3 /* Fault A Keep Action bit position. */ ++ ++#define FAULT_SRCA_gm 0x03 /* Fault A Source Selection group mask. */ ++#define FAULT_SRCA_gp 0 /* Fault A Source Selection group position. */ ++#define FAULT_SRCA0_bm (1<<0) /* Fault A Source Selection bit 0 mask. */ ++#define FAULT_SRCA0_bp 0 /* Fault A Source Selection bit 0 position. */ ++#define FAULT_SRCA1_bm (1<<1) /* Fault A Source Selection bit 1 mask. */ ++#define FAULT_SRCA1_bp 1 /* Fault A Source Selection bit 1 position. */ ++ ++/* FAULT.CTRLC bit masks and bit positions */ ++#define FAULT_CAPTA_bm 0x20 /* Fault A Capture bit mask. */ ++#define FAULT_CAPTA_bp 5 /* Fault A Capture bit position. */ ++ ++#define FAULT_FILTERA_bm 0x04 /* Fault A Digital Filter Selection bit mask. */ ++#define FAULT_FILTERA_bp 2 /* Fault A Digital Filter Selection bit position. */ ++ ++#define FAULT_BLANKA_bm 0x02 /* Fault A Blanking bit mask. */ ++#define FAULT_BLANKA_bp 1 /* Fault A Blanking bit position. */ ++ ++#define FAULT_QUALA_bm 0x01 /* Fault A Qualification bit mask. */ ++#define FAULT_QUALA_bp 0 /* Fault A Qualification bit position. */ ++ ++/* FAULT.CTRLD bit masks and bit positions */ ++#define FAULT_SOFTB_bm 0x80 /* Fault B Software Mode bit mask. */ ++#define FAULT_SOFTB_bp 7 /* Fault B Software Mode bit position. */ ++ ++#define FAULT_HALTB_gm 0x60 /* Fault B Halt Action group mask. */ ++#define FAULT_HALTB_gp 5 /* Fault B Halt Action group position. */ ++#define FAULT_HALTB0_bm (1<<5) /* Fault B Halt Action bit 0 mask. */ ++#define FAULT_HALTB0_bp 5 /* Fault B Halt Action bit 0 position. */ ++#define FAULT_HALTB1_bm (1<<6) /* Fault B Halt Action bit 1 mask. */ ++#define FAULT_HALTB1_bp 6 /* Fault B Halt Action bit 1 position. */ ++ ++#define FAULT_RESTARTB_bm 0x10 /* Fault B Restart Action bit mask. */ ++#define FAULT_RESTARTB_bp 4 /* Fault B Restart Action bit position. */ ++ ++#define FAULT_KEEPB_bm 0x08 /* Fault B Keep Action bit mask. */ ++#define FAULT_KEEPB_bp 3 /* Fault B Keep Action bit position. */ ++ ++#define FAULT_SRCB_gm 0x03 /* Fault B Source Selection group mask. */ ++#define FAULT_SRCB_gp 0 /* Fault B Source Selection group position. */ ++#define FAULT_SRCB0_bm (1<<0) /* Fault B Source Selection bit 0 mask. */ ++#define FAULT_SRCB0_bp 0 /* Fault B Source Selection bit 0 position. */ ++#define FAULT_SRCB1_bm (1<<1) /* Fault B Source Selection bit 1 mask. */ ++#define FAULT_SRCB1_bp 1 /* Fault B Source Selection bit 1 position. */ ++ ++/* FAULT.CTRLE bit masks and bit positions */ ++#define FAULT_CAPTB_bm 0x20 /* Fault B Capture bit mask. */ ++#define FAULT_CAPTB_bp 5 /* Fault B Capture bit position. */ ++ ++#define FAULT_FILTERB_bm 0x04 /* Fault B Digital Filter Selection bit mask. */ ++#define FAULT_FILTERB_bp 2 /* Fault B Digital Filter Selection bit position. */ ++ ++#define FAULT_BLANKB_bm 0x02 /* Fault B Blanking bit mask. */ ++#define FAULT_BLANKB_bp 1 /* Fault B Blanking bit position. */ ++ ++#define FAULT_QUALB_bm 0x01 /* Fault B Qualification bit mask. */ ++#define FAULT_QUALB_bp 0 /* Fault B Qualification bit position. */ ++ ++/* FAULT.STATUS bit masks and bit positions */ ++#define FAULT_STATEB_bm 0x80 /* Fault B State bit mask. */ ++#define FAULT_STATEB_bp 7 /* Fault B State bit position. */ ++ ++#define FAULT_STATEA_bm 0x40 /* Fault A State bit mask. */ ++#define FAULT_STATEA_bp 6 /* Fault A State bit position. */ ++ ++#define FAULT_STATEE_bm 0x20 /* Fault E State bit mask. */ ++#define FAULT_STATEE_bp 5 /* Fault E State bit position. */ ++ ++#define FAULT_IDX_bm 0x08 /* Channel Index Flag bit mask. */ ++#define FAULT_IDX_bp 3 /* Channel Index Flag bit position. */ ++ ++#define FAULT_FAULTBIN_bm 0x04 /* Fault B Flag bit mask. */ ++#define FAULT_FAULTBIN_bp 2 /* Fault B Flag bit position. */ ++ ++#define FAULT_FAULTAIN_bm 0x02 /* Fault A Flag bit mask. */ ++#define FAULT_FAULTAIN_bp 1 /* Fault A Flag bit position. */ ++ ++#define FAULT_FAULTEIN_bm 0x01 /* Fault E Flag bit mask. */ ++#define FAULT_FAULTEIN_bp 0 /* Fault E Flag bit position. */ ++ ++/* FAULT.CTRLGCLR bit masks and bit positions */ ++#define FAULT_HALTBCLR_bm 0x80 /* State B Clear bit mask. */ ++#define FAULT_HALTBCLR_bp 7 /* State B Clear bit position. */ ++ ++#define FAULT_HALTACLR_bm 0x40 /* State A Clear bit mask. */ ++#define FAULT_HALTACLR_bp 6 /* State A Clear bit position. */ ++ ++#define FAULT_STATEECLR_bm 0x20 /* State E Clear bit mask. */ ++#define FAULT_STATEECLR_bp 5 /* State E Clear bit position. */ ++ ++#define FAULT_FAULTB_bm 0x04 /* Fault B Flag bit mask. */ ++#define FAULT_FAULTB_bp 2 /* Fault B Flag bit position. */ ++ ++#define FAULT_FAULTA_bm 0x02 /* Fault A Flag bit mask. */ ++#define FAULT_FAULTA_bp 1 /* Fault A Flag bit position. */ ++ ++#define FAULT_FAULTE_bm 0x01 /* Fault E Flag bit mask. */ ++#define FAULT_FAULTE_bp 0 /* Fault E Flag bit position. */ ++ ++/* FAULT.CTRLGSET bit masks and bit positions */ ++#define FAULT_FAULTBSW_bm 0x80 /* Software Fault B bit mask. */ ++#define FAULT_FAULTBSW_bp 7 /* Software Fault B bit position. */ ++ ++#define FAULT_FAULTASW_bm 0x40 /* Software Fault A bit mask. */ ++#define FAULT_FAULTASW_bp 6 /* Software Fault A bit position. */ ++ ++#define FAULT_FAULTESW_bm 0x20 /* Software Fault E bit mask. */ ++#define FAULT_FAULTESW_bp 5 /* Software Fault E bit position. */ ++ ++#define FAULT_IDXCMD_gm 0x18 /* Channel index Command group mask. */ ++#define FAULT_IDXCMD_gp 3 /* Channel index Command group position. */ ++#define FAULT_IDXCMD0_bm (1<<3) /* Channel index Command bit 0 mask. */ ++#define FAULT_IDXCMD0_bp 3 /* Channel index Command bit 0 position. */ ++#define FAULT_IDXCMD1_bm (1<<4) /* Channel index Command bit 1 mask. */ ++#define FAULT_IDXCMD1_bp 4 /* Channel index Command bit 1 position. */ ++ ++/* WEX - Waveform Extension */ ++/* WEX.CTRL bit masks and bit positions */ ++#define WEX_UPSEL_bm 0x80 /* Update Source Selection bit mask. */ ++#define WEX_UPSEL_bp 7 /* Update Source Selection bit position. */ ++ ++#define WEX_OTMX_gm 0x70 /* Output Matrix group mask. */ ++#define WEX_OTMX_gp 4 /* Output Matrix group position. */ ++#define WEX_OTMX0_bm (1<<4) /* Output Matrix bit 0 mask. */ ++#define WEX_OTMX0_bp 4 /* Output Matrix bit 0 position. */ ++#define WEX_OTMX1_bm (1<<5) /* Output Matrix bit 1 mask. */ ++#define WEX_OTMX1_bp 5 /* Output Matrix bit 1 position. */ ++#define WEX_OTMX2_bm (1<<6) /* Output Matrix bit 2 mask. */ ++#define WEX_OTMX2_bp 6 /* Output Matrix bit 2 position. */ ++ ++#define WEX_DTI3EN_bm 0x08 /* Dead-Time Insertion Generator 3 Enable bit mask. */ ++#define WEX_DTI3EN_bp 3 /* Dead-Time Insertion Generator 3 Enable bit position. */ ++ ++#define WEX_DTI2EN_bm 0x04 /* Dead-Time Insertion Generator 2 Enable bit mask. */ ++#define WEX_DTI2EN_bp 2 /* Dead-Time Insertion Generator 2 Enable bit position. */ ++ ++#define WEX_DTI1EN_bm 0x02 /* Dead-Time Insertion Generator 1 Enable bit mask. */ ++#define WEX_DTI1EN_bp 1 /* Dead-Time Insertion Generator 1 Enable bit position. */ ++ ++#define WEX_DTI0EN_bm 0x01 /* Dead-Time Insertion Generator 0 Enable bit mask. */ ++#define WEX_DTI0EN_bp 0 /* Dead-Time Insertion Generator 0 Enable bit position. */ ++ ++/* WEX.STATUSCLR bit masks and bit positions */ ++#define WEX_SWAPBUF_bm 0x04 /* Swap Buffer Valid bit mask. */ ++#define WEX_SWAPBUF_bp 2 /* Swap Buffer Valid bit position. */ ++ ++#define WEX_PGVBUFV_bm 0x02 /* Pattern Generator Value Buffer Valid bit mask. */ ++#define WEX_PGVBUFV_bp 1 /* Pattern Generator Value Buffer Valid bit position. */ ++ ++#define WEX_PGOBUFV_bm 0x01 /* Pattern Generator Overwrite Buffer Valid bit mask. */ ++#define WEX_PGOBUFV_bp 0 /* Pattern Generator Overwrite Buffer Valid bit position. */ ++ ++/* WEX.STATUSSET bit masks and bit positions */ ++/* WEX_SWAPBUF Predefined. */ ++/* WEX_SWAPBUF Predefined. */ ++ ++/* WEX_PGVBUFV Predefined. */ ++/* WEX_PGVBUFV Predefined. */ ++ ++/* WEX_PGOBUFV Predefined. */ ++/* WEX_PGOBUFV Predefined. */ ++ ++/* WEX.SWAP bit masks and bit positions */ ++#define WEX_SWAP3_bm 0x08 /* Swap DTI output pair 3 bit mask. */ ++#define WEX_SWAP3_bp 3 /* Swap DTI output pair 3 bit position. */ ++ ++#define WEX_SWAP2_bm 0x04 /* Swap DTI output pair 2 bit mask. */ ++#define WEX_SWAP2_bp 2 /* Swap DTI output pair 2 bit position. */ ++ ++#define WEX_SWAP1_bm 0x02 /* Swap DTI output pair 1 bit mask. */ ++#define WEX_SWAP1_bp 1 /* Swap DTI output pair 1 bit position. */ ++ ++#define WEX_SWAP0_bm 0x01 /* Swap DTI output pair 0 bit mask. */ ++#define WEX_SWAP0_bp 0 /* Swap DTI output pair 0 bit position. */ ++ ++/* WEX.SWAPBUF bit masks and bit positions */ ++#define WEX_SWAP3BUF_bm 0x08 /* Swap DTI output pair 3 bit mask. */ ++#define WEX_SWAP3BUF_bp 3 /* Swap DTI output pair 3 bit position. */ ++ ++#define WEX_SWAP2BUF_bm 0x04 /* Swap DTI output pair 2 bit mask. */ ++#define WEX_SWAP2BUF_bp 2 /* Swap DTI output pair 2 bit position. */ ++ ++#define WEX_SWAP1BUF_bm 0x02 /* Swap DTI output pair 1 bit mask. */ ++#define WEX_SWAP1BUF_bp 1 /* Swap DTI output pair 1 bit position. */ ++ ++#define WEX_SWAP0BUF_bm 0x01 /* Swap DTI output pair 0 bit mask. */ ++#define WEX_SWAP0BUF_bp 0 /* Swap DTI output pair 0 bit position. */ ++ ++/* HIRES - High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HRPLUS_gm 0x0C /* High Resolution Plus group mask. */ ++#define HIRES_HRPLUS_gp 2 /* High Resolution Plus group position. */ ++#define HIRES_HRPLUS0_bm (1<<2) /* High Resolution Plus bit 0 mask. */ ++#define HIRES_HRPLUS0_bp 2 /* High Resolution Plus bit 0 position. */ ++#define HIRES_HRPLUS1_bm (1<<3) /* High Resolution Plus bit 1 mask. */ ++#define HIRES_HRPLUS1_bp 3 /* High Resolution Plus bit 1 position. */ ++ ++#define HIRES_HREN_gm 0x03 /* High Resolution Mode group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Mode group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Mode bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Mode bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Mode bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Mode bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXSIF_bm 0x02 /* Receive Start Bit Interrupt Flag bit mask. */ ++#define USART_RXSIF_bp 1 /* Receive Start Bit Interrupt Flag bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++#define USART_DRIF_bm 0x01 /* Data Reception Flag bit mask. */ ++#define USART_DRIF_bp 0 /* Data Reception Flag bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXSIE_bm 0x80 /* Receive Start Interrupt Enable bit mask. */ ++#define USART_RXSIE_bp 7 /* Receive Start Interrupt Enable bit position. */ ++ ++#define USART_DRIE_bm 0x40 /* Data Reception Interrupt Enable bit mask. */ ++#define USART_DRIE_bp 6 /* Data Reception Interrupt Enable bit position. */ ++ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_ONEWIRE_bm 0x80 /* One Wire Mode bit mask. */ ++#define USART_ONEWIRE_bp 7 /* One Wire Mode bit position. */ ++ ++#define USART_SFDEN_bm 0x40 /* Start Frame Detection Enable bit mask. */ ++#define USART_SFDEN_bp 6 /* Start Frame Detection Enable bit position. */ ++ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.CTRLD bit masks and bit positions */ ++#define USART_DECTYPE_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_DECTYPE_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_DECTYPE0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_DECTYPE0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_DECTYPE1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_DECTYPE1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_LUTACT_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_LUTACT_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_LUTACT0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_LUTACT0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_LUTACT1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_LUTACT1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_PECACT_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_PECACT_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_PECACT0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_PECACT0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_PECACT1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_PECACT1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable SPI Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable SPI Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ ++#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit position. */ ++ ++#define SPI_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ ++#define SPI_TXCIE_bp 6 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit position. */ ++ ++#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit mask. */ ++#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit position. */ ++ ++#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit mask. */ ++#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit position. */ ++ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag (In Standard Mode Only). bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag (In Standard Mode Only). bit position. */ ++ ++#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ ++#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision Flag (In Standard Mode Only). bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision Flag (In Standard Mode Only). bit position. */ ++ ++#define SPI_TXCIF_bm 0x40 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ ++#define SPI_TXCIF_bp 6 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit position. */ ++ ++#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit mask. */ ++#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit position. */ ++ ++#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit mask. */ ++#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit position. */ ++ ++#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow (In Buffer Modes Only). bit mask. */ ++#define SPI_BUFOVF_bp 0 /* Buffer Overflow (In Buffer Modes Only). bit position. */ ++ ++/* SPI.CTRLB bit masks and bit positions */ ++#define SPI_BUFMODE_gm 0xC0 /* Buffer Modes group mask. */ ++#define SPI_BUFMODE_gp 6 /* Buffer Modes group position. */ ++#define SPI_BUFMODE0_bm (1<<6) /* Buffer Modes bit 0 mask. */ ++#define SPI_BUFMODE0_bp 6 /* Buffer Modes bit 0 position. */ ++#define SPI_BUFMODE1_bm (1<<7) /* Buffer Modes bit 1 mask. */ ++#define SPI_BUFMODE1_bp 7 /* Buffer Modes bit 1 position. */ ++ ++#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ ++#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* NVM_FUSES.FUSEBYTE6 bit masks and bit positions */ ++#define NVM_FUSES_FDACT5_bm 0x80 /* Fault Dectection Action on TC5 bit mask. */ ++#define NVM_FUSES_FDACT5_bp 7 /* Fault Dectection Action on TC5 bit position. */ ++ ++#define NVM_FUSES_FDACT4_bm 0x40 /* Fault Dectection Action on TC4 bit mask. */ ++#define NVM_FUSES_FDACT4_bp 6 /* Fault Dectection Action on TC4 bit position. */ ++ ++#define NVM_FUSES_VALUE_gm 0x3F /* Port Pin Value group mask. */ ++#define NVM_FUSES_VALUE_gp 0 /* Port Pin Value group position. */ ++#define NVM_FUSES_VALUE0_bm (1<<0) /* Port Pin Value bit 0 mask. */ ++#define NVM_FUSES_VALUE0_bp 0 /* Port Pin Value bit 0 position. */ ++#define NVM_FUSES_VALUE1_bm (1<<1) /* Port Pin Value bit 1 mask. */ ++#define NVM_FUSES_VALUE1_bp 1 /* Port Pin Value bit 1 position. */ ++#define NVM_FUSES_VALUE2_bm (1<<2) /* Port Pin Value bit 2 mask. */ ++#define NVM_FUSES_VALUE2_bp 2 /* Port Pin Value bit 2 position. */ ++#define NVM_FUSES_VALUE3_bm (1<<3) /* Port Pin Value bit 3 mask. */ ++#define NVM_FUSES_VALUE3_bp 3 /* Port Pin Value bit 3 position. */ ++#define NVM_FUSES_VALUE4_bm (1<<4) /* Port Pin Value bit 4 mask. */ ++#define NVM_FUSES_VALUE4_bp 4 /* Port Pin Value bit 4 position. */ ++#define NVM_FUSES_VALUE5_bm (1<<5) /* Port Pin Value bit 5 mask. */ ++#define NVM_FUSES_VALUE5_bp 5 /* Port Pin Value bit 5 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT_vect_num 2 ++#define PORTR_INT_vect _VECTOR(2) /* External Interrupt */ ++ ++/* EDMA interrupt vectors */ ++#define EDMA_CH0_vect_num 3 ++#define EDMA_CH0_vect _VECTOR(3) /* EDMA Channel 0 Interrupt */ ++#define EDMA_CH1_vect_num 4 ++#define EDMA_CH1_vect _VECTOR(4) /* EDMA Channel 1 Interrupt */ ++#define EDMA_CH2_vect_num 5 ++#define EDMA_CH2_vect _VECTOR(5) /* EDMA Channel 2 Interrupt */ ++#define EDMA_CH3_vect_num 6 ++#define EDMA_CH3_vect _VECTOR(6) /* EDMA Channel 3 Interrupt */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 7 ++#define RTC_OVF_vect _VECTOR(7) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 8 ++#define RTC_COMP_vect _VECTOR(8) /* Compare Interrupt */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT_vect_num 9 ++#define PORTC_INT_vect _VECTOR(9) /* External Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 10 ++#define TWIC_TWIS_vect _VECTOR(10) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 11 ++#define TWIC_TWIM_vect _VECTOR(11) /* TWI Master Interrupt */ ++ ++/* TCC4 interrupt vectors */ ++#define TCC4_OVF_vect_num 12 ++#define TCC4_OVF_vect _VECTOR(12) /* Overflow Interrupt */ ++#define TCC4_ERR_vect_num 13 ++#define TCC4_ERR_vect _VECTOR(13) /* Error Interrupt */ ++#define TCC4_CCA_vect_num 14 ++#define TCC4_CCA_vect _VECTOR(14) /* Channel A Compare or Capture Interrupt */ ++#define TCC4_CCB_vect_num 15 ++#define TCC4_CCB_vect _VECTOR(15) /* Channel B Compare or Capture Interrupt */ ++#define TCC4_CCC_vect_num 16 ++#define TCC4_CCC_vect _VECTOR(16) /* Channel C Compare or Capture Interrupt */ ++#define TCC4_CCD_vect_num 17 ++#define TCC4_CCD_vect _VECTOR(17) /* Channel D Compare or Capture Interrupt */ ++ ++/* TCC5 interrupt vectors */ ++#define TCC5_OVF_vect_num 18 ++#define TCC5_OVF_vect _VECTOR(18) /* Overflow Interrupt */ ++#define TCC5_ERR_vect_num 19 ++#define TCC5_ERR_vect _VECTOR(19) /* Error Interrupt */ ++#define TCC5_CCA_vect_num 20 ++#define TCC5_CCA_vect _VECTOR(20) /* Channel A Compare or Capture Interrupt */ ++#define TCC5_CCB_vect_num 21 ++#define TCC5_CCB_vect _VECTOR(21) /* Channel B Compare or Capture Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 22 ++#define SPIC_INT_vect _VECTOR(22) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 23 ++#define USARTC0_RXC_vect _VECTOR(23) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 24 ++#define USARTC0_DRE_vect _VECTOR(24) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 25 ++#define USARTC0_TXC_vect _VECTOR(25) /* Transmission Complete Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 26 ++#define NVM_EE_vect _VECTOR(26) /* EE Interrupt */ ++#define NVM_SPM_vect_num 27 ++#define NVM_SPM_vect _VECTOR(27) /* SPM Interrupt */ ++ ++/* XCL interrupt vectors */ ++#define XCL_UNF_vect_num 28 ++#define XCL_UNF_vect _VECTOR(28) /* Timer/Counter Underflow Interrupt */ ++#define XCL_CC_vect_num 29 ++#define XCL_CC_vect _VECTOR(29) /* Timer/Counter Compare or Capture Interrupt */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT_vect_num 30 ++#define PORTA_INT_vect _VECTOR(30) /* External Interrupt */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 31 ++#define ACA_AC0_vect _VECTOR(31) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 32 ++#define ACA_AC1_vect _VECTOR(32) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 33 ++#define ACA_ACW_vect _VECTOR(33) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 34 ++#define ADCA_CH0_vect _VECTOR(34) /* ADC Channel Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT_vect_num 35 ++#define PORTD_INT_vect _VECTOR(35) /* External Interrupt */ ++ ++/* TCD5 interrupt vectors */ ++#define TCD5_OVF_vect_num 36 ++#define TCD5_OVF_vect _VECTOR(36) /* Overflow Interrupt */ ++#define TCD5_ERR_vect_num 37 ++#define TCD5_ERR_vect _VECTOR(37) /* Error Interrupt */ ++#define TCD5_CCA_vect_num 38 ++#define TCD5_CCA_vect _VECTOR(38) /* Channel A Compare or Capture Interrupt */ ++#define TCD5_CCB_vect_num 39 ++#define TCD5_CCB_vect _VECTOR(39) /* Channel B Compare or Capture Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 40 ++#define USARTD0_RXC_vect _VECTOR(40) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 41 ++#define USARTD0_DRE_vect _VECTOR(41) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 42 ++#define USARTD0_TXC_vect _VECTOR(42) /* Transmission Complete Interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (43 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (36864) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (32768) ++#define APP_SECTION_PAGE_SIZE (128) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x7000) ++#define APPTABLE_SECTION_SIZE (4096) ++#define APPTABLE_SECTION_PAGE_SIZE (128) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x8000) ++#define BOOT_SECTION_SIZE (4096) ++#define BOOT_SECTION_PAGE_SIZE (128) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (12288) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (1024) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (4096) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (1024) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (7) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (128) ++#define USER_SIGNATURES_PAGE_SIZE (128) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (128) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 128 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 7 ++ ++/* Fuse Byte 0 Reserved */ ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* Fuse Byte 6 */ ++#define FUSE_VALUE0 (unsigned char)~_BV(0) /* Port Pin Value Bit 0 */ ++#define FUSE_VALUE1 (unsigned char)~_BV(1) /* Port Pin Value Bit 1 */ ++#define FUSE_VALUE2 (unsigned char)~_BV(2) /* Port Pin Value Bit 2 */ ++#define FUSE_VALUE3 (unsigned char)~_BV(3) /* Port Pin Value Bit 3 */ ++#define FUSE_VALUE4 (unsigned char)~_BV(4) /* Port Pin Value Bit 4 */ ++#define FUSE_VALUE5 (unsigned char)~_BV(5) /* Port Pin Value Bit 5 */ ++#define FUSE_FDACT4 (unsigned char)~_BV(6) /* Fault Dectection Action on TC4 */ ++#define FUSE_FDACT5 (unsigned char)~_BV(7) /* Fault Dectection Action on TC5 */ ++#define FUSE6_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x95 ++#define SIGNATURE_2 0x4C ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA32E5_H_INCLUDED */ ++ diff --git a/include/avr/iox384c3.h b/include/avr/iox384c3.h new file mode 100644 -index 0000000..e36d7d7 +index 0000000..47e1f08 --- /dev/null +++ b/include/avr/iox384c3.h @@ -0,0 +1,6780 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox384c3.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA384C3_H_INCLUDED -+#define _AVR_ATXMEGA384C3_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+VPORT - Virtual Ports -+-------------------------------------------------------------------------- -+*/ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t USBCTRL; /* USB Control Register */ -+} CLK_t; -+ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t PRPB; /* Power Reduction Port B */ -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t PRPD; /* Power Reduction Port D */ -+ register8_t PRPE; /* Power Reduction Port E */ -+ register8_t PRPF; /* Power Reduction Port F */ -+} PR_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+/* USB Prescaler Division Factor */ -+typedef enum CLK_USBPSDIV_enum -+{ -+ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ -+ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ -+ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ -+ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ -+ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ -+ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -+} CLK_USBPSDIV_t; -+ -+/* USB Clock Source */ -+typedef enum CLK_USBSRC_enum -+{ -+ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ -+ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -+} CLK_USBSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control Register */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+/* 2 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC2MCREF_enum -+{ -+ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC2MCREF_t; -+ -+/* 32 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC32MCREF_enum -+{ -+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -+} OSC_RC32MCREF_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t ANAINIT; /* Analog Startup Delay */ -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t AWEXLOCK; /* AWEX Lock */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORTCFG - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t VPCTRLA; /* Virtual Port Control Register A */ -+ register8_t VPCTRLB; /* Virtual Port Control Register B */ -+ register8_t CLKEVOUT; /* Clock and Event Out Register */ -+ register8_t EBIOUT; /* EBI Output register */ -+ register8_t EVOUTSEL; /* Event Output Select */ -+} PORTCFG_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP02MAP_enum -+{ -+ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ -+ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ -+ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ -+ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ -+ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ -+ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ -+ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ -+ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ -+ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ -+ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ -+ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ -+ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ -+ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ -+ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ -+ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ -+ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -+} PORTCFG_VP02MAP_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP13MAP_enum -+{ -+ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ -+ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ -+ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ -+ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ -+ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ -+ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ -+ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ -+ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ -+ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ -+ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ -+ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ -+ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ -+ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ -+ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ -+ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ -+ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -+} PORTCFG_VP13MAP_t; -+ -+/* System Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ -+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ -+ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -+} PORTCFG_CLKOUT_t; -+ -+/* Peripheral Clock Output Select */ -+typedef enum PORTCFG_CLKOUTSEL_enum -+{ -+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -+} PORTCFG_CLKOUTSEL_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ -+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ -+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -+} PORTCFG_EVOUT_t; -+ -+/* Clock and Event Output Port */ -+typedef enum PORTCFG_CLKEVPIN_enum -+{ -+ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ -+ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -+} PORTCFG_CLKEVPIN_t; -+ -+/* EBI Address Output Port */ -+typedef enum PORTCFG_EBIADROUT_enum -+{ -+ PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ -+ PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ -+ PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ -+ PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ -+} PORTCFG_EBIADROUT_t; -+ -+/* EBI Chip Select Output Port */ -+typedef enum PORTCFG_EBICSOUT_enum -+{ -+ PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ -+} PORTCFG_EBICSOUT_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -+ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ -+ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ -+ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ -+ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AES - AES Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* AES Module */ -+typedef struct AES_struct -+{ -+ register8_t CTRL; /* AES Control Register */ -+ register8_t STATUS; /* AES Status Register */ -+ register8_t STATE; /* AES State Register */ -+ register8_t KEY; /* AES Key Register */ -+ register8_t INTCTRL; /* AES Interrupt Control Register */ -+} AES_t; -+ -+/* Interrupt level */ -+typedef enum AES_INTLVL_enum -+{ -+ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} AES_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ -+ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ -+ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ -+ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DMA - DMA Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* DMA Channel */ -+typedef struct DMA_CH_struct -+{ -+ register8_t CTRLA; /* Channel Control */ -+ register8_t CTRLB; /* Channel Control */ -+ register8_t ADDRCTRL; /* Address Control */ -+ register8_t TRIGSRC; /* Channel Trigger Source */ -+ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ -+ register8_t REPCNT; /* Channel Repeat Count */ -+ register8_t reserved_0x07; -+ register8_t SRCADDR0; /* Channel Source Address 0 */ -+ register8_t SRCADDR1; /* Channel Source Address 1 */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t DESTADDR0; /* Channel Destination Address 0 */ -+ register8_t DESTADDR1; /* Channel Destination Address 1 */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} DMA_CH_t; -+ -+ -+/* DMA Controller */ -+typedef struct DMA_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t reserved_0x01; -+ register8_t reserved_0x02; -+ register8_t INTFLAGS; /* Transfer Interrupt Status */ -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x05; -+ _WORDREGISTER(TEMP); /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ DMA_CH_t CH0; /* DMA Channel 0 */ -+ DMA_CH_t CH1; /* DMA Channel 1 */ -+} DMA_t; -+ -+/* Burst mode */ -+typedef enum DMA_CH_BURSTLEN_enum -+{ -+ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ -+ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ -+ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ -+ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -+} DMA_CH_BURSTLEN_t; -+ -+/* Source address reload mode */ -+typedef enum DMA_CH_SRCRELOAD_enum -+{ -+ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ -+ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ -+ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ -+ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -+} DMA_CH_SRCRELOAD_t; -+ -+/* Source addressing mode */ -+typedef enum DMA_CH_SRCDIR_enum -+{ -+ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ -+ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ -+ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -+} DMA_CH_SRCDIR_t; -+ -+/* Destination adress reload mode */ -+typedef enum DMA_CH_DESTRELOAD_enum -+{ -+ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ -+ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ -+ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ -+ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -+} DMA_CH_DESTRELOAD_t; -+ -+/* Destination adressing mode */ -+typedef enum DMA_CH_DESTDIR_enum -+{ -+ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ -+ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ -+ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -+} DMA_CH_DESTDIR_t; -+ -+/* Transfer trigger source */ -+typedef enum DMA_CH_TRIGSRC_enum -+{ -+ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ -+ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ -+ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ -+ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ -+ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ -+ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ -+ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ -+ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ -+ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ -+ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ -+ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ -+ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ -+ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ -+ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ -+ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ -+ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ -+ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ -+} DMA_CH_TRIGSRC_t; -+ -+/* Double buffering mode */ -+typedef enum DMA_DBUFMODE_enum -+{ -+ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ -+ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ -+} DMA_DBUFMODE_t; -+ -+/* Priority mode */ -+typedef enum DMA_PRIMODE_enum -+{ -+ DMA_PRIMODE_RR01_gc = (0x00<<0), /* Round Robin */ -+ DMA_PRIMODE_CH01_gc = (0x01<<0), /* Channel 0 > channel 1 */ -+} DMA_PRIMODE_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_ERRINTLVL_enum -+{ -+ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ -+ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ -+ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -+} DMA_CH_ERRINTLVL_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_TRNINTLVL_enum -+{ -+ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ -+ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -+} DMA_CH_TRNINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+} EVSYS_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ -+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ -+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ -+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ -+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ -+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ -+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ -+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ -+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ -+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ -+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ -+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ -+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ -+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ -+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ -+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ -+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ -+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ -+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ -+ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ -+ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ -+ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ -+ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ -+ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ -+ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ -+ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ -+ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ -+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ -+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ -+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ -+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ -+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ -+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ -+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ -+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ -+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ -+ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ -+ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ -+ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ -+ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ -+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ -+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ -+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ -+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ -+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -+ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ -+ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ -+ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ -+ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ -+ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -+} EVSYS_CHMUX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ -+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ -+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ -+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ -+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} NVM_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t reserved_0x07; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+} ADC_t; -+ -+/* Current Limitation */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -+} ADC_CURRLIMIT_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+} ADC_CH_MUXNEG_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ -+ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ -+ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ -+ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC - Real-Time Counter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Real-Time Counter */ -+typedef struct RTC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary register */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ _WORDREGISTER(CNT); /* Count Register */ -+ _WORDREGISTER(PER); /* Period Register */ -+ _WORDREGISTER(COMP); /* Compare Register */ -+} RTC_t; -+ -+/* Prescaler Factor */ -+typedef enum RTC_PRESCALER_enum -+{ -+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ -+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ -+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ -+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ -+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ -+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ -+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ -+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -+} RTC_PRESCALER_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC_COMPINTLVL_enum -+{ -+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC_OVFINTLVL_enum -+{ -+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+} TWI_t; -+ -+/* SDA Hold Time */ -+typedef enum TWI_SDAHOLD_enum -+{ -+ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ -+ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ -+ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ -+ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -+} TWI_SDAHOLD_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USB - USB -+-------------------------------------------------------------------------- -+*/ -+ -+/* USB Endpoint */ -+typedef struct USB_EP_struct -+{ -+ register8_t STATUS; /* Endpoint Status */ -+ register8_t CTRL; /* Endpoint Control */ -+ _WORDREGISTER(CNT); /* USB Endpoint Counter */ -+ _WORDREGISTER(DATAPTR); /* Data Pointer */ -+ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -+} USB_EP_t; -+ -+ -+/* Universal Serial Bus */ -+typedef struct USB_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t FIFOWP; /* FIFO Write Pointer Register */ -+ register8_t FIFORP; /* FIFO Read Pointer Register */ -+ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ -+ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ -+ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ -+ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t reserved_0x20; -+ register8_t reserved_0x21; -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t CAL0; /* Calibration Byte 0 */ -+ register8_t CAL1; /* Calibration Byte 1 */ -+} USB_t; -+ -+ -+/* USB Endpoint Table */ -+typedef struct USB_EP_TABLE_struct -+{ -+ USB_EP_t EP0OUT; /* Endpoint 0 */ -+ USB_EP_t EP0IN; /* Endpoint 0 */ -+ USB_EP_t EP1OUT; /* Endpoint 1 */ -+ USB_EP_t EP1IN; /* Endpoint 1 */ -+ USB_EP_t EP2OUT; /* Endpoint 2 */ -+ USB_EP_t EP2IN; /* Endpoint 2 */ -+ USB_EP_t EP3OUT; /* Endpoint 3 */ -+ USB_EP_t EP3IN; /* Endpoint 3 */ -+ USB_EP_t EP4OUT; /* Endpoint 4 */ -+ USB_EP_t EP4IN; /* Endpoint 4 */ -+ USB_EP_t EP5OUT; /* Endpoint 5 */ -+ USB_EP_t EP5IN; /* Endpoint 5 */ -+ USB_EP_t EP6OUT; /* Endpoint 6 */ -+ USB_EP_t EP6IN; /* Endpoint 6 */ -+ USB_EP_t EP7OUT; /* Endpoint 7 */ -+ USB_EP_t EP7IN; /* Endpoint 7 */ -+ USB_EP_t EP8OUT; /* Endpoint 8 */ -+ USB_EP_t EP8IN; /* Endpoint 8 */ -+ USB_EP_t EP9OUT; /* Endpoint 9 */ -+ USB_EP_t EP9IN; /* Endpoint 9 */ -+ USB_EP_t EP10OUT; /* Endpoint 10 */ -+ USB_EP_t EP10IN; /* Endpoint 10 */ -+ USB_EP_t EP11OUT; /* Endpoint 11 */ -+ USB_EP_t EP11IN; /* Endpoint 11 */ -+ USB_EP_t EP12OUT; /* Endpoint 12 */ -+ USB_EP_t EP12IN; /* Endpoint 12 */ -+ USB_EP_t EP13OUT; /* Endpoint 13 */ -+ USB_EP_t EP13IN; /* Endpoint 13 */ -+ USB_EP_t EP14OUT; /* Endpoint 14 */ -+ USB_EP_t EP14IN; /* Endpoint 14 */ -+ USB_EP_t EP15OUT; /* Endpoint 15 */ -+ USB_EP_t EP15IN; /* Endpoint 15 */ -+ register8_t reserved_0x100; -+ register8_t reserved_0x101; -+ register8_t reserved_0x102; -+ register8_t reserved_0x103; -+ register8_t reserved_0x104; -+ register8_t reserved_0x105; -+ register8_t reserved_0x106; -+ register8_t reserved_0x107; -+ register8_t reserved_0x108; -+ register8_t reserved_0x109; -+ register8_t reserved_0x10A; -+ register8_t reserved_0x10B; -+ register8_t reserved_0x10C; -+ register8_t reserved_0x10D; -+ register8_t reserved_0x10E; -+ register8_t reserved_0x10F; -+ register8_t FRAMENUML; /* Frame Number Low Byte */ -+ register8_t FRAMENUMH; /* Frame Number High Byte */ -+} USB_EP_TABLE_t; -+ -+/* Interrupt level */ -+typedef enum USB_INTLVL_enum -+{ -+ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} USB_INTLVL_t; -+ -+/* USB Endpoint Type */ -+typedef enum USB_EP_TYPE_enum -+{ -+ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ -+ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ -+ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ -+ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -+} USB_EP_TYPE_t; -+ -+/* USB Endpoint Buffersize */ -+typedef enum USB_EP_BUFSIZE_enum -+{ -+ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ -+ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ -+ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ -+ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ -+ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ -+ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ -+ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ -+ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -+} USB_EP_BUFSIZE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - I/O Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INT0MASK; /* Port Interrupt 0 Mask */ -+ register8_t INT1MASK; /* Port Interrupt 1 Mask */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t REMAP; /* I/O Port Pin Remap Register */ -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Port Interrupt 0 Level */ -+typedef enum PORT_INT0LVL_enum -+{ -+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INT0LVL_t; -+ -+/* Port Interrupt 1 Level */ -+typedef enum PORT_INT1LVL_enum -+{ -+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ -+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ -+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -+} PORT_INT1LVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 0 */ -+typedef struct TC0_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC0_t; -+ -+ -+/* 16-bit Timer/Counter 1 */ -+typedef struct TC1_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+} TC1_t; -+ -+/* Clock Selection */ -+typedef enum TC_CLKSEL_enum -+{ -+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_CLKSEL_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC_WGMODE_enum -+{ -+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC_WGMODE_t; -+ -+/* Byte Mode */ -+typedef enum TC_BYTEM_enum -+{ -+ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ -+ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -+} TC_BYTEM_t; -+ -+/* Event Action */ -+typedef enum TC_EVACT_enum -+{ -+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ -+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ -+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ -+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ -+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ -+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC_EVSEL_enum -+{ -+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_EVSEL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC_ERRINTLVL_enum -+{ -+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC_OVFINTLVL_enum -+{ -+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_OVFINTLVL_t; -+ -+/* Compare or Capture D Interrupt Level */ -+typedef enum TC_CCDINTLVL_enum -+{ -+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC_CCDINTLVL_t; -+ -+/* Compare or Capture C Interrupt Level */ -+typedef enum TC_CCCINTLVL_enum -+{ -+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC_CCCINTLVL_t; -+ -+/* Compare or Capture B Interrupt Level */ -+typedef enum TC_CCBINTLVL_enum -+{ -+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_CCBINTLVL_t; -+ -+/* Compare or Capture A Interrupt Level */ -+typedef enum TC_CCAINTLVL_enum -+{ -+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_CCAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC_CMD_enum -+{ -+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC2 - 16-bit Timer/Counter type 2 -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter type 2 */ -+typedef struct TC2_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t reserved_0x03; -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t reserved_0x08; -+ register8_t CTRLF; /* Control Register F */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t LCNT; /* Low Byte Count */ -+ register8_t HCNT; /* High Byte Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t LPER; /* Low Byte Period */ -+ register8_t HPER; /* High Byte Period */ -+ register8_t LCMPA; /* Low Byte Compare A */ -+ register8_t HCMPA; /* High Byte Compare A */ -+ register8_t LCMPB; /* Low Byte Compare B */ -+ register8_t HCMPB; /* High Byte Compare B */ -+ register8_t LCMPC; /* Low Byte Compare C */ -+ register8_t HCMPC; /* High Byte Compare C */ -+ register8_t LCMPD; /* Low Byte Compare D */ -+ register8_t HCMPD; /* High Byte Compare D */ -+} TC2_t; -+ -+/* Clock Selection */ -+typedef enum TC2_CLKSEL_enum -+{ -+ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC2_CLKSEL_t; -+ -+/* Byte Mode */ -+typedef enum TC2_BYTEM_enum -+{ -+ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ -+ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -+} TC2_BYTEM_t; -+ -+/* High Byte Underflow Interrupt Level */ -+typedef enum TC2_HUNFINTLVL_enum -+{ -+ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_HUNFINTLVL_t; -+ -+/* Low Byte Underflow Interrupt Level */ -+typedef enum TC2_LUNFINTLVL_enum -+{ -+ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LUNFINTLVL_t; -+ -+/* Low Byte Compare D Interrupt Level */ -+typedef enum TC2_LCMPDINTLVL_enum -+{ -+ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC2_LCMPDINTLVL_t; -+ -+/* Low Byte Compare C Interrupt Level */ -+typedef enum TC2_LCMPCINTLVL_enum -+{ -+ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC2_LCMPCINTLVL_t; -+ -+/* Low Byte Compare B Interrupt Level */ -+typedef enum TC2_LCMPBINTLVL_enum -+{ -+ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_LCMPBINTLVL_t; -+ -+/* Low Byte Compare A Interrupt Level */ -+typedef enum TC2_LCMPAINTLVL_enum -+{ -+ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LCMPAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMD_enum -+{ -+ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC2_CMD_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMDEN_enum -+{ -+ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ -+ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ -+ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -+} TC2_CMDEN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AWEX - Timer/Counter Advanced Waveform Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Advanced Waveform Extension */ -+typedef struct AWEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t FDEMASK; /* Fault Detection Event Mask */ -+ register8_t FDCTRL; /* Fault Detection Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t STATUSSET; /* Status Set Register */ -+ register8_t DTBOTH; /* Dead Time Both Sides */ -+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ -+ register8_t DTLS; /* Dead Time Low Side */ -+ register8_t DTHS; /* Dead Time High Side */ -+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ -+ register8_t DTHSBUF; /* Dead Time High Side Buffer */ -+ register8_t OUTOVEN; /* Output Override Enable */ -+} AWEX_t; -+ -+/* Fault Detect Action */ -+typedef enum AWEX_FDACT_enum -+{ -+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ -+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -+} AWEX_FDACT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+HIRES - Timer/Counter High-Resolution Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register */ -+} HIRES_t; -+ -+/* High Resolution Enable */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ -+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+} IRDA_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t reserved_0x00; -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+} NVM_FUSES_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* Timer Oscillator pin location */ -+typedef enum TOSCSEL_enum -+{ -+ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ -+ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -+} TOSCSEL_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -+} BOD_t; -+ -+/* BOD operation */ -+typedef enum BODACT_enum -+{ -+ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BODACT_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WDP_enum -+{ -+ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ -+ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ -+ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ -+ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ -+ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ -+ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ -+ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ -+ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ -+ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ -+ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ -+ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -+} WDP_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LOCKBIT - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ -+ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t USBCAL0; /* USB Calibration Byte 0 */ -+ register8_t USBCAL1; /* USB Calibration Byte 1 */ -+ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ -+ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+} NVM_PROD_SIGNATURES_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define AES (*(AES_t *) 0x00C0) /* AES Module */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -+#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -+#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -+#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -+#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -+#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -+#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -+#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -+#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -+#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ -+#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -+#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -+#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -+#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+#define CLK_USBCTRL _SFR_MEM8(0x0044) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* DFLL - DFLL */ -+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -+#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -+#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPB _SFR_MEM8(0x0072) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPD _SFR_MEM8(0x0074) -+#define PR_PRPE _SFR_MEM8(0x0075) -+#define PR_PRPF _SFR_MEM8(0x0076) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_ANAINIT _SFR_MEM8(0x0097) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_AWEXLOCK _SFR_MEM8(0x0099) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) -+#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) -+ -+/* AES - AES Module */ -+#define AES_CTRL _SFR_MEM8(0x00C0) -+#define AES_STATUS _SFR_MEM8(0x00C1) -+#define AES_STATE _SFR_MEM8(0x00C2) -+#define AES_KEY _SFR_MEM8(0x00C3) -+#define AES_INTCTRL _SFR_MEM8(0x00C4) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* DMA - DMA Controller */ -+#define DMA_CTRL _SFR_MEM8(0x0100) -+#define DMA_INTFLAGS _SFR_MEM8(0x0103) -+#define DMA_STATUS _SFR_MEM8(0x0104) -+#define DMA_TEMP _SFR_MEM16(0x0106) -+#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -+#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -+#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -+#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -+#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -+#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -+#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -+#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -+#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -+#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -+#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -+#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -+#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -+#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -+#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -+#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -+#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -+#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -+#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -+#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCA_CTRLA _SFR_MEM8(0x0200) -+#define ADCA_CTRLB _SFR_MEM8(0x0201) -+#define ADCA_REFCTRL _SFR_MEM8(0x0202) -+#define ADCA_EVCTRL _SFR_MEM8(0x0203) -+#define ADCA_PRESCALER _SFR_MEM8(0x0204) -+#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -+#define ADCA_TEMP _SFR_MEM8(0x0207) -+#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) -+#define ADCA_CAL _SFR_MEM16(0x020C) -+#define ADCA_CH0RES _SFR_MEM16(0x0210) -+#define ADCA_CMP _SFR_MEM16(0x0218) -+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -+#define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -+ -+/* AC - Analog Comparator */ -+#define ACA_AC0CTRL _SFR_MEM8(0x0380) -+#define ACA_AC1CTRL _SFR_MEM8(0x0381) -+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -+#define ACA_CTRLA _SFR_MEM8(0x0384) -+#define ACA_CTRLB _SFR_MEM8(0x0385) -+#define ACA_WINCTRL _SFR_MEM8(0x0386) -+#define ACA_STATUS _SFR_MEM8(0x0387) -+ -+/* RTC - Real-Time Counter */ -+#define RTC_CTRL _SFR_MEM8(0x0400) -+#define RTC_STATUS _SFR_MEM8(0x0401) -+#define RTC_INTCTRL _SFR_MEM8(0x0402) -+#define RTC_INTFLAGS _SFR_MEM8(0x0403) -+#define RTC_TEMP _SFR_MEM8(0x0404) -+#define RTC_CNT _SFR_MEM16(0x0408) -+#define RTC_PER _SFR_MEM16(0x040A) -+#define RTC_COMP _SFR_MEM16(0x040C) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIE_CTRL _SFR_MEM8(0x04A0) -+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -+ -+/* USB - Universal Serial Bus */ -+#define USB_CTRLA _SFR_MEM8(0x04C0) -+#define USB_CTRLB _SFR_MEM8(0x04C1) -+#define USB_STATUS _SFR_MEM8(0x04C2) -+#define USB_ADDR _SFR_MEM8(0x04C3) -+#define USB_FIFOWP _SFR_MEM8(0x04C4) -+#define USB_FIFORP _SFR_MEM8(0x04C5) -+#define USB_EPPTR _SFR_MEM16(0x04C6) -+#define USB_INTCTRLA _SFR_MEM8(0x04C8) -+#define USB_INTCTRLB _SFR_MEM8(0x04C9) -+#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -+#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -+#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -+#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -+#define USB_CAL0 _SFR_MEM8(0x04FA) -+#define USB_CAL1 _SFR_MEM8(0x04FB) -+ -+/* PORT - I/O Ports */ -+#define PORTA_DIR _SFR_MEM8(0x0600) -+#define PORTA_DIRSET _SFR_MEM8(0x0601) -+#define PORTA_DIRCLR _SFR_MEM8(0x0602) -+#define PORTA_DIRTGL _SFR_MEM8(0x0603) -+#define PORTA_OUT _SFR_MEM8(0x0604) -+#define PORTA_OUTSET _SFR_MEM8(0x0605) -+#define PORTA_OUTCLR _SFR_MEM8(0x0606) -+#define PORTA_OUTTGL _SFR_MEM8(0x0607) -+#define PORTA_IN _SFR_MEM8(0x0608) -+#define PORTA_INTCTRL _SFR_MEM8(0x0609) -+#define PORTA_INT0MASK _SFR_MEM8(0x060A) -+#define PORTA_INT1MASK _SFR_MEM8(0x060B) -+#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_REMAP _SFR_MEM8(0x060E) -+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -+ -+/* PORT - I/O Ports */ -+#define PORTB_DIR _SFR_MEM8(0x0620) -+#define PORTB_DIRSET _SFR_MEM8(0x0621) -+#define PORTB_DIRCLR _SFR_MEM8(0x0622) -+#define PORTB_DIRTGL _SFR_MEM8(0x0623) -+#define PORTB_OUT _SFR_MEM8(0x0624) -+#define PORTB_OUTSET _SFR_MEM8(0x0625) -+#define PORTB_OUTCLR _SFR_MEM8(0x0626) -+#define PORTB_OUTTGL _SFR_MEM8(0x0627) -+#define PORTB_IN _SFR_MEM8(0x0628) -+#define PORTB_INTCTRL _SFR_MEM8(0x0629) -+#define PORTB_INT0MASK _SFR_MEM8(0x062A) -+#define PORTB_INT1MASK _SFR_MEM8(0x062B) -+#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -+#define PORTB_REMAP _SFR_MEM8(0x062E) -+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INT0MASK _SFR_MEM8(0x064A) -+#define PORTC_INT1MASK _SFR_MEM8(0x064B) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INT0MASK _SFR_MEM8(0x066A) -+#define PORTD_INT1MASK _SFR_MEM8(0x066B) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTE_DIR _SFR_MEM8(0x0680) -+#define PORTE_DIRSET _SFR_MEM8(0x0681) -+#define PORTE_DIRCLR _SFR_MEM8(0x0682) -+#define PORTE_DIRTGL _SFR_MEM8(0x0683) -+#define PORTE_OUT _SFR_MEM8(0x0684) -+#define PORTE_OUTSET _SFR_MEM8(0x0685) -+#define PORTE_OUTCLR _SFR_MEM8(0x0686) -+#define PORTE_OUTTGL _SFR_MEM8(0x0687) -+#define PORTE_IN _SFR_MEM8(0x0688) -+#define PORTE_INTCTRL _SFR_MEM8(0x0689) -+#define PORTE_INT0MASK _SFR_MEM8(0x068A) -+#define PORTE_INT1MASK _SFR_MEM8(0x068B) -+#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -+#define PORTE_REMAP _SFR_MEM8(0x068E) -+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) -+ -+/* PORT - I/O Ports */ -+#define PORTF_DIR _SFR_MEM8(0x06A0) -+#define PORTF_DIRSET _SFR_MEM8(0x06A1) -+#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -+#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -+#define PORTF_OUT _SFR_MEM8(0x06A4) -+#define PORTF_OUTSET _SFR_MEM8(0x06A5) -+#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -+#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -+#define PORTF_IN _SFR_MEM8(0x06A8) -+#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -+#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -+#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -+#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -+#define PORTF_REMAP _SFR_MEM8(0x06AE) -+#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -+#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -+#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -+#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -+#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -+#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -+#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -+#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -+#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCC0_CTRLA _SFR_MEM8(0x0800) -+#define TCC0_CTRLB _SFR_MEM8(0x0801) -+#define TCC0_CTRLC _SFR_MEM8(0x0802) -+#define TCC0_CTRLD _SFR_MEM8(0x0803) -+#define TCC0_CTRLE _SFR_MEM8(0x0804) -+#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -+#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -+#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -+#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC0_TEMP _SFR_MEM8(0x080F) -+#define TCC0_CNT _SFR_MEM16(0x0820) -+#define TCC0_PER _SFR_MEM16(0x0826) -+#define TCC0_CCA _SFR_MEM16(0x0828) -+#define TCC0_CCB _SFR_MEM16(0x082A) -+#define TCC0_CCC _SFR_MEM16(0x082C) -+#define TCC0_CCD _SFR_MEM16(0x082E) -+#define TCC0_PERBUF _SFR_MEM16(0x0836) -+#define TCC0_CCABUF _SFR_MEM16(0x0838) -+#define TCC0_CCBBUF _SFR_MEM16(0x083A) -+#define TCC0_CCCBUF _SFR_MEM16(0x083C) -+#define TCC0_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCC2_CTRLA _SFR_MEM8(0x0800) -+#define TCC2_CTRLB _SFR_MEM8(0x0801) -+#define TCC2_CTRLC _SFR_MEM8(0x0802) -+#define TCC2_CTRLE _SFR_MEM8(0x0804) -+#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC2_CTRLF _SFR_MEM8(0x0809) -+#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC2_LCNT _SFR_MEM8(0x0820) -+#define TCC2_HCNT _SFR_MEM8(0x0821) -+#define TCC2_LPER _SFR_MEM8(0x0826) -+#define TCC2_HPER _SFR_MEM8(0x0827) -+#define TCC2_LCMPA _SFR_MEM8(0x0828) -+#define TCC2_HCMPA _SFR_MEM8(0x0829) -+#define TCC2_LCMPB _SFR_MEM8(0x082A) -+#define TCC2_HCMPB _SFR_MEM8(0x082B) -+#define TCC2_LCMPC _SFR_MEM8(0x082C) -+#define TCC2_HCMPC _SFR_MEM8(0x082D) -+#define TCC2_LCMPD _SFR_MEM8(0x082E) -+#define TCC2_HCMPD _SFR_MEM8(0x082F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCC1_CTRLA _SFR_MEM8(0x0840) -+#define TCC1_CTRLB _SFR_MEM8(0x0841) -+#define TCC1_CTRLC _SFR_MEM8(0x0842) -+#define TCC1_CTRLD _SFR_MEM8(0x0843) -+#define TCC1_CTRLE _SFR_MEM8(0x0844) -+#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -+#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -+#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -+#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC1_TEMP _SFR_MEM8(0x084F) -+#define TCC1_CNT _SFR_MEM16(0x0860) -+#define TCC1_PER _SFR_MEM16(0x0866) -+#define TCC1_CCA _SFR_MEM16(0x0868) -+#define TCC1_CCB _SFR_MEM16(0x086A) -+#define TCC1_PERBUF _SFR_MEM16(0x0876) -+#define TCC1_CCABUF _SFR_MEM16(0x0878) -+#define TCC1_CCBBUF _SFR_MEM16(0x087A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXC_CTRL _SFR_MEM8(0x0880) -+#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -+#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -+#define AWEXC_STATUS _SFR_MEM8(0x0884) -+#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -+#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -+#define AWEXC_DTLS _SFR_MEM8(0x0888) -+#define AWEXC_DTHS _SFR_MEM8(0x0889) -+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x0890) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08A0) -+#define USARTC0_STATUS _SFR_MEM8(0x08A1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -+#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -+#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC1_DATA _SFR_MEM8(0x08B0) -+#define USARTC1_STATUS _SFR_MEM8(0x08B1) -+#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -+#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -+#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -+#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -+#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIC_CTRL _SFR_MEM8(0x08C0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -+#define SPIC_STATUS _SFR_MEM8(0x08C2) -+#define SPIC_DATA _SFR_MEM8(0x08C3) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCD0_CTRLA _SFR_MEM8(0x0900) -+#define TCD0_CTRLB _SFR_MEM8(0x0901) -+#define TCD0_CTRLC _SFR_MEM8(0x0902) -+#define TCD0_CTRLD _SFR_MEM8(0x0903) -+#define TCD0_CTRLE _SFR_MEM8(0x0904) -+#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -+#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -+#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -+#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -+#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD0_TEMP _SFR_MEM8(0x090F) -+#define TCD0_CNT _SFR_MEM16(0x0920) -+#define TCD0_PER _SFR_MEM16(0x0926) -+#define TCD0_CCA _SFR_MEM16(0x0928) -+#define TCD0_CCB _SFR_MEM16(0x092A) -+#define TCD0_CCC _SFR_MEM16(0x092C) -+#define TCD0_CCD _SFR_MEM16(0x092E) -+#define TCD0_PERBUF _SFR_MEM16(0x0936) -+#define TCD0_CCABUF _SFR_MEM16(0x0938) -+#define TCD0_CCBBUF _SFR_MEM16(0x093A) -+#define TCD0_CCCBUF _SFR_MEM16(0x093C) -+#define TCD0_CCDBUF _SFR_MEM16(0x093E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCD2_CTRLA _SFR_MEM8(0x0900) -+#define TCD2_CTRLB _SFR_MEM8(0x0901) -+#define TCD2_CTRLC _SFR_MEM8(0x0902) -+#define TCD2_CTRLE _SFR_MEM8(0x0904) -+#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD2_CTRLF _SFR_MEM8(0x0909) -+#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD2_LCNT _SFR_MEM8(0x0920) -+#define TCD2_HCNT _SFR_MEM8(0x0921) -+#define TCD2_LPER _SFR_MEM8(0x0926) -+#define TCD2_HPER _SFR_MEM8(0x0927) -+#define TCD2_LCMPA _SFR_MEM8(0x0928) -+#define TCD2_HCMPA _SFR_MEM8(0x0929) -+#define TCD2_LCMPB _SFR_MEM8(0x092A) -+#define TCD2_HCMPB _SFR_MEM8(0x092B) -+#define TCD2_LCMPC _SFR_MEM8(0x092C) -+#define TCD2_HCMPC _SFR_MEM8(0x092D) -+#define TCD2_LCMPD _SFR_MEM8(0x092E) -+#define TCD2_HCMPD _SFR_MEM8(0x092F) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD0_DATA _SFR_MEM8(0x09A0) -+#define USARTD0_STATUS _SFR_MEM8(0x09A1) -+#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -+#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -+#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPID_CTRL _SFR_MEM8(0x09C0) -+#define SPID_INTCTRL _SFR_MEM8(0x09C1) -+#define SPID_STATUS _SFR_MEM8(0x09C2) -+#define SPID_DATA _SFR_MEM8(0x09C3) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCE0_CTRLA _SFR_MEM8(0x0A00) -+#define TCE0_CTRLB _SFR_MEM8(0x0A01) -+#define TCE0_CTRLC _SFR_MEM8(0x0A02) -+#define TCE0_CTRLD _SFR_MEM8(0x0A03) -+#define TCE0_CTRLE _SFR_MEM8(0x0A04) -+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE0_TEMP _SFR_MEM8(0x0A0F) -+#define TCE0_CNT _SFR_MEM16(0x0A20) -+#define TCE0_PER _SFR_MEM16(0x0A26) -+#define TCE0_CCA _SFR_MEM16(0x0A28) -+#define TCE0_CCB _SFR_MEM16(0x0A2A) -+#define TCE0_CCC _SFR_MEM16(0x0A2C) -+#define TCE0_CCD _SFR_MEM16(0x0A2E) -+#define TCE0_PERBUF _SFR_MEM16(0x0A36) -+#define TCE0_CCABUF _SFR_MEM16(0x0A38) -+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCE2_CTRLA _SFR_MEM8(0x0A00) -+#define TCE2_CTRLB _SFR_MEM8(0x0A01) -+#define TCE2_CTRLC _SFR_MEM8(0x0A02) -+#define TCE2_CTRLE _SFR_MEM8(0x0A04) -+#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE2_CTRLF _SFR_MEM8(0x0A09) -+#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE2_LCNT _SFR_MEM8(0x0A20) -+#define TCE2_HCNT _SFR_MEM8(0x0A21) -+#define TCE2_LPER _SFR_MEM8(0x0A26) -+#define TCE2_HPER _SFR_MEM8(0x0A27) -+#define TCE2_LCMPA _SFR_MEM8(0x0A28) -+#define TCE2_HCMPA _SFR_MEM8(0x0A29) -+#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -+#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -+#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -+#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -+#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -+#define TCE2_HCMPD _SFR_MEM8(0x0A2F) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE0_DATA _SFR_MEM8(0x0AA0) -+#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -+#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -+#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -+#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -+#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -+#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCF0_CTRLA _SFR_MEM8(0x0B00) -+#define TCF0_CTRLB _SFR_MEM8(0x0B01) -+#define TCF0_CTRLC _SFR_MEM8(0x0B02) -+#define TCF0_CTRLD _SFR_MEM8(0x0B03) -+#define TCF0_CTRLE _SFR_MEM8(0x0B04) -+#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -+#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -+#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -+#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -+#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -+#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -+#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -+#define TCF0_TEMP _SFR_MEM8(0x0B0F) -+#define TCF0_CNT _SFR_MEM16(0x0B20) -+#define TCF0_PER _SFR_MEM16(0x0B26) -+#define TCF0_CCA _SFR_MEM16(0x0B28) -+#define TCF0_CCB _SFR_MEM16(0x0B2A) -+#define TCF0_CCC _SFR_MEM16(0x0B2C) -+#define TCF0_CCD _SFR_MEM16(0x0B2E) -+#define TCF0_PERBUF _SFR_MEM16(0x0B36) -+#define TCF0_CCABUF _SFR_MEM16(0x0B38) -+#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -+#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -+#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCF2_CTRLA _SFR_MEM8(0x0B00) -+#define TCF2_CTRLB _SFR_MEM8(0x0B01) -+#define TCF2_CTRLC _SFR_MEM8(0x0B02) -+#define TCF2_CTRLE _SFR_MEM8(0x0B04) -+#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -+#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -+#define TCF2_CTRLF _SFR_MEM8(0x0B09) -+#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -+#define TCF2_LCNT _SFR_MEM8(0x0B20) -+#define TCF2_HCNT _SFR_MEM8(0x0B21) -+#define TCF2_LPER _SFR_MEM8(0x0B26) -+#define TCF2_HPER _SFR_MEM8(0x0B27) -+#define TCF2_LCMPA _SFR_MEM8(0x0B28) -+#define TCF2_HCMPA _SFR_MEM8(0x0B29) -+#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -+#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -+#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -+#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -+#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -+#define TCF2_HCMPD _SFR_MEM8(0x0B2F) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTF0_DATA _SFR_MEM8(0x0BA0) -+#define USARTF0_STATUS _SFR_MEM8(0x0BA1) -+#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) -+#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) -+#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) -+#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) -+#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* VPORT - Virtual Ports */ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* CLK.USBCTRL bit masks and bit positions */ -+#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -+#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -+#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -+#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -+#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -+#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -+#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -+#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ -+ -+#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -+#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -+#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ -+ -+#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_USB_bm 0x40 /* USB bit mask. */ -+#define PR_USB_bp 6 /* USB bit position. */ -+ -+#define PR_AES_bm 0x10 /* AES bit mask. */ -+#define PR_AES_bp 4 /* AES bit position. */ -+ -+#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -+#define PR_EBI_bp 3 /* External Bus Interface bit position. */ -+ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -+#define PR_DMA_bp 0 /* DMA-Controller bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -+#define PR_DAC_bp 2 /* Port A DAC bit position. */ -+ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPB bit masks and bit positions */ -+/* PR_DAC Predefined. */ -+/* PR_DAC Predefined. */ -+ -+/* PR_ADC Predefined. */ -+/* PR_ADC Predefined. */ -+ -+/* PR_AC Predefined. */ -+/* PR_AC Predefined. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -+#define PR_USART1_bp 5 /* Port C USART1 bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -+#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ -+ -+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -+ -+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ -+ -+/* PR.PRPD bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPE bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPF bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -+#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -+#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ -+ -+#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ -+ -+#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -+#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.ANAINIT bit masks and bit positions */ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.AWEXLOCK bit masks and bit positions */ -+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* PORTCFG - Port Configuration */ -+/* PORTCFG.VPCTRLA bit masks and bit positions */ -+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ -+ -+/* PORTCFG.VPCTRLB bit masks and bit positions */ -+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ -+ -+/* PORTCFG.CLKEVOUT bit masks and bit positions */ -+#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ -+ -+#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -+#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -+#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -+#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -+#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -+#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ -+ -+#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -+#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ -+ -+#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -+#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ -+ -+/* PORTCFG.EBIOUT bit masks and bit positions */ -+#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ -+#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ -+#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ -+#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ -+#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ -+#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ -+ -+#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ -+#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ -+#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ -+#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ -+#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ -+#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ -+ -+/* PORTCFG.EVOUTSEL bit masks and bit positions */ -+#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -+#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -+#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -+#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -+#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -+#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -+#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -+#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ -+ -+/* AES - AES Module */ -+/* AES.CTRL bit masks and bit positions */ -+#define AES_START_bm 0x80 /* Start/Run bit mask. */ -+#define AES_START_bp 7 /* Start/Run bit position. */ -+ -+#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -+#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ -+ -+#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -+#define AES_RESET_bp 5 /* AES Software Reset bit position. */ -+ -+#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -+#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ -+ -+#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -+#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ -+ -+/* AES.STATUS bit masks and bit positions */ -+#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -+#define AES_ERROR_bp 7 /* AES Error bit position. */ -+ -+#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -+#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ -+ -+/* AES.INTCTRL bit masks and bit positions */ -+#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -+#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* DMA - DMA Controller */ -+/* DMA_CH.CTRLA bit masks and bit positions */ -+#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -+#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ -+ -+#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -+#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ -+ -+#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -+#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ -+ -+#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -+#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ -+ -+#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -+#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ -+ -+#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -+#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -+#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -+#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -+#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -+#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ -+ -+/* DMA_CH.CTRLB bit masks and bit positions */ -+#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -+#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ -+ -+#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -+#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ -+ -+#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -+#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ -+ -+#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -+#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -+#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -+#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -+#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -+#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ -+ -+#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -+#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -+#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -+#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -+#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -+#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ -+ -+/* DMA_CH.ADDRCTRL bit masks and bit positions */ -+#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -+#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -+#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -+#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -+#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -+#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ -+ -+#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -+#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -+#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -+#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -+#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -+#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ -+ -+#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -+#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -+#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -+#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -+#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -+#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ -+ -+#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -+#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -+#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -+#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -+#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -+#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ -+ -+/* DMA_CH.TRIGSRC bit masks and bit positions */ -+#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -+#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -+#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -+#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -+#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -+#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -+#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -+#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -+#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -+#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -+#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -+#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -+#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -+#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -+#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -+#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -+#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -+#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ -+ -+/* DMA.CTRL bit masks and bit positions */ -+#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -+#define DMA_ENABLE_bp 7 /* Enable bit position. */ -+ -+#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -+#define DMA_RESET_bp 6 /* Software Reset bit position. */ -+ -+#define DMA_DBUFMODE_bm 0x04 /* Double Buffering Mode bit mask. */ -+#define DMA_DBUFMODE_bp 2 /* Double Buffering Mode bit position. */ -+ -+#define DMA_PRIMODE_bm 0x01 /* Channel Priority Mode bit mask. */ -+#define DMA_PRIMODE_bp 0 /* Channel Priority Mode bit position. */ -+ -+/* DMA.INTFLAGS bit masks and bit positions */ -+#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ -+ -+/* DMA.STATUS bit masks and bit positions */ -+#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -+#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ -+ -+#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -+#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ -+ -+#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -+#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ -+ -+#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -+#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0x7F /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ -+ -+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ -+ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -+#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -+#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -+#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -+#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -+#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -+#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -+#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -+#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -+#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ -+ -+#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */ -+#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */ -+#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -+#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */ -+#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -+#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */ -+#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -+#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */ -+#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -+#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -+#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* ADC.SAMPCTRL bit masks and bit positions */ -+#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ -+#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ -+#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ -+#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ -+#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ -+#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ -+#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ -+#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ -+#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ -+#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ -+#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ -+#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ -+#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ -+#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* RTC - Real-Time Counter */ -+/* RTC.CTRL bit masks and bit positions */ -+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ -+ -+/* RTC.STATUS bit masks and bit positions */ -+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC.INTCTRL bit masks and bit positions */ -+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC.INTFLAGS bit masks and bit positions */ -+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* USB - USB */ -+/* USB_EP.STATUS bit masks and bit positions */ -+#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -+#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ -+ -+#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -+#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ -+ -+#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -+#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ -+ -+#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -+#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ -+ -+#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -+#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ -+ -+#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -+#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ -+ -+#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -+#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ -+ -+#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -+#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ -+ -+#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ -+ -+#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ -+ -+#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -+#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ -+ -+/* USB_EP.CTRL bit masks and bit positions */ -+#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -+#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -+#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -+#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -+#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -+#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ -+ -+#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -+#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ -+ -+#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -+#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ -+ -+#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -+#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ -+ -+#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -+#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ -+ -+#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -+#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -+#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -+#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -+#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -+#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -+#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -+#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ -+ -+/* USB_EP.CNT bit masks and bit positions */ -+#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -+#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ -+ -+/* USB.CTRLA bit masks and bit positions */ -+#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -+#define USB_ENABLE_bp 7 /* USB Enable bit position. */ -+ -+#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -+#define USB_SPEED_bp 6 /* Speed Select bit position. */ -+ -+#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -+#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ -+ -+#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -+#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ -+ -+#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -+#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -+#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -+#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -+#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -+#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -+#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -+#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -+#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -+#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ -+ -+/* USB.CTRLB bit masks and bit positions */ -+#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -+#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ -+ -+#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -+#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ -+ -+#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -+#define USB_GNACK_bp 1 /* Global NACK bit position. */ -+ -+#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -+#define USB_ATTACH_bp 0 /* Attach bit position. */ -+ -+/* USB.STATUS bit masks and bit positions */ -+#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -+#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ -+ -+#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -+#define USB_RESUME_bp 2 /* Resume bit position. */ -+ -+#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -+#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ -+ -+#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -+#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ -+ -+/* USB.ADDR bit masks and bit positions */ -+#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -+#define USB_ADDR_gp 0 /* Device Address group position. */ -+#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -+#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -+#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -+#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -+#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -+#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -+#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -+#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -+#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -+#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -+#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -+#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -+#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -+#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ -+ -+/* USB.FIFOWP bit masks and bit positions */ -+#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -+#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -+#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -+#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -+#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -+#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -+#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -+#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -+#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -+#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -+#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -+#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ -+ -+/* USB.FIFORP bit masks and bit positions */ -+#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -+#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -+#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -+#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -+#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -+#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -+#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -+#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -+#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -+#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -+#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -+#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ -+ -+/* USB.INTCTRLA bit masks and bit positions */ -+#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -+#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ -+ -+#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -+#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ -+ -+#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -+#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ -+ -+#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -+#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ -+ -+#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* USB.INTCTRLB bit masks and bit positions */ -+#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -+#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ -+ -+#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -+#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ -+ -+/* USB.INTFLAGSACLR bit masks and bit positions */ -+#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -+#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ -+ -+#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -+#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ -+ -+#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -+#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ -+ -+#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -+#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ -+ -+#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -+#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ -+ -+#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -+#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ -+ -+#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -+#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ -+ -+#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -+#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSASET bit masks and bit positions */ -+/* USB_SOFIF Predefined. */ -+/* USB_SOFIF Predefined. */ -+ -+/* USB_SUSPENDIF Predefined. */ -+/* USB_SUSPENDIF Predefined. */ -+ -+/* USB_RESUMEIF Predefined. */ -+/* USB_RESUMEIF Predefined. */ -+ -+/* USB_RSTIF Predefined. */ -+/* USB_RSTIF Predefined. */ -+ -+/* USB_CRCIF Predefined. */ -+/* USB_CRCIF Predefined. */ -+ -+/* USB_UNFIF Predefined. */ -+/* USB_UNFIF Predefined. */ -+ -+/* USB_OVFIF Predefined. */ -+/* USB_OVFIF Predefined. */ -+ -+/* USB_STALLIF Predefined. */ -+/* USB_STALLIF Predefined. */ -+ -+/* USB.INTFLAGSBCLR bit masks and bit positions */ -+#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -+#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ -+ -+#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -+#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSBSET bit masks and bit positions */ -+/* USB_TRNIF Predefined. */ -+/* USB_TRNIF Predefined. */ -+ -+/* USB_SETUPIF Predefined. */ -+/* USB_SETUPIF Predefined. */ -+ -+/* PORT - I/O Port Configuration */ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ -+ -+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -+#define PORT_SPI_bp 5 /* SPI bit position. */ -+ -+#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -+#define PORT_USART0_bp 4 /* USART0 bit position. */ -+ -+#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -+#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ -+ -+#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -+#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ -+ -+#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -+#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ -+ -+#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -+#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ -+ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC0.CTRLA bit masks and bit positions */ -+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC0.CTRLB bit masks and bit positions */ -+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ -+ -+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ -+ -+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC0.CTRLC bit masks and bit positions */ -+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ -+ -+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ -+ -+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC0.CTRLD bit masks and bit positions */ -+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC0_EVACT_gp 5 /* Event Action group position. */ -+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC0.CTRLE bit masks and bit positions */ -+#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC0.INTCTRLA bit masks and bit positions */ -+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC0.INTCTRLB bit masks and bit positions */ -+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ -+ -+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ -+ -+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC0.CTRLFCLR bit masks and bit positions */ -+#define TC0_CMD_gm 0x0C /* Command group mask. */ -+#define TC0_CMD_gp 2 /* Command group position. */ -+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC0_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC0_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC0_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC0.CTRLFSET bit masks and bit positions */ -+/* TC0_CMD Predefined. */ -+/* TC0_CMD Predefined. */ -+ -+/* TC0_LUPD Predefined. */ -+/* TC0_LUPD Predefined. */ -+ -+/* TC0_DIR Predefined. */ -+/* TC0_DIR Predefined. */ -+ -+/* TC0.CTRLGCLR bit masks and bit positions */ -+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ -+ -+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ -+ -+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC0.CTRLGSET bit masks and bit positions */ -+/* TC0_CCDBV Predefined. */ -+/* TC0_CCDBV Predefined. */ -+ -+/* TC0_CCCBV Predefined. */ -+/* TC0_CCCBV Predefined. */ -+ -+/* TC0_CCBBV Predefined. */ -+/* TC0_CCBBV Predefined. */ -+ -+/* TC0_CCABV Predefined. */ -+/* TC0_CCABV Predefined. */ -+ -+/* TC0_PERBV Predefined. */ -+/* TC0_PERBV Predefined. */ -+ -+/* TC0.INTFLAGS bit masks and bit positions */ -+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ -+ -+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ -+ -+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC1.CTRLA bit masks and bit positions */ -+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC1.CTRLB bit masks and bit positions */ -+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC1.CTRLC bit masks and bit positions */ -+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC1.CTRLD bit masks and bit positions */ -+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC1_EVACT_gp 5 /* Event Action group position. */ -+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC1.CTRLE bit masks and bit positions */ -+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ -+ -+/* TC1.INTCTRLA bit masks and bit positions */ -+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC1.INTCTRLB bit masks and bit positions */ -+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC1.CTRLFCLR bit masks and bit positions */ -+#define TC1_CMD_gm 0x0C /* Command group mask. */ -+#define TC1_CMD_gp 2 /* Command group position. */ -+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC1_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC1_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC1_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC1.CTRLFSET bit masks and bit positions */ -+/* TC1_CMD Predefined. */ -+/* TC1_CMD Predefined. */ -+ -+/* TC1_LUPD Predefined. */ -+/* TC1_LUPD Predefined. */ -+ -+/* TC1_DIR Predefined. */ -+/* TC1_DIR Predefined. */ -+ -+/* TC1.CTRLGCLR bit masks and bit positions */ -+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC1.CTRLGSET bit masks and bit positions */ -+/* TC1_CCBBV Predefined. */ -+/* TC1_CCBBV Predefined. */ -+ -+/* TC1_CCABV Predefined. */ -+/* TC1_CCABV Predefined. */ -+ -+/* TC1_PERBV Predefined. */ -+/* TC1_PERBV Predefined. */ -+ -+/* TC1.INTFLAGS bit masks and bit positions */ -+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+/* TC2.CTRLA bit masks and bit positions */ -+#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC2.CTRLB bit masks and bit positions */ -+#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -+#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ -+ -+#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -+#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ -+ -+#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -+#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ -+ -+#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -+#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ -+ -+#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -+#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ -+ -+#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -+#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ -+ -+#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -+#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ -+ -+#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -+#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ -+ -+/* TC2.CTRLC bit masks and bit positions */ -+#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -+#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ -+ -+#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -+#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ -+ -+#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -+#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ -+ -+#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -+#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ -+ -+#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -+#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ -+ -+#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -+#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ -+ -+#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -+#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ -+ -+#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -+#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ -+ -+/* TC2.CTRLE bit masks and bit positions */ -+#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC2.INTCTRLA bit masks and bit positions */ -+#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -+#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -+#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -+#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -+#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -+#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ -+ -+#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -+#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -+#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -+#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -+#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -+#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ -+ -+/* TC2.INTCTRLB bit masks and bit positions */ -+#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -+#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -+#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -+#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -+#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -+#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -+#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -+#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -+#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -+#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -+#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -+#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -+#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -+#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -+#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -+#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -+#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -+#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -+#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -+#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -+#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ -+ -+/* TC2.CTRLF bit masks and bit positions */ -+#define TC2_CMD_gm 0x0C /* Command group mask. */ -+#define TC2_CMD_gp 2 /* Command group position. */ -+#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC2_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -+#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -+#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -+#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -+#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -+#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ -+ -+/* TC2.INTFLAGS bit masks and bit positions */ -+#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -+#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ -+ -+#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -+#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ -+ -+#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -+#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ -+ -+#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -+#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ -+ -+#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ -+ -+#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ -+ -+/* AWEX - Timer/Counter Advanced Waveform Extension */ -+/* AWEX.CTRL bit masks and bit positions */ -+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ -+ -+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ -+ -+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ -+ -+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ -+ -+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ -+ -+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ -+ -+/* AWEX.FDCTRL bit masks and bit positions */ -+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ -+ -+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ -+ -+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ -+ -+/* AWEX.STATUS bit masks and bit positions */ -+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ -+ -+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ -+ -+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ -+ -+/* AWEX.STATUSSET bit masks and bit positions */ -+/* AWEX_FDF Predefined. */ -+/* AWEX_FDF Predefined. */ -+ -+/* AWEX_DTHSBUFV Predefined. */ -+/* AWEX_DTHSBUFV Predefined. */ -+ -+/* AWEX_DTLSBUFV Predefined. */ -+/* AWEX_DTLSBUFV Predefined. */ -+ -+/* HIRES - Timer/Counter High-Resolution Extension */ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -+#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* LOCKBIT - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT0_vect_num 2 -+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -+#define PORTC_INT1_vect_num 3 -+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT0_vect_num 4 -+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -+#define PORTR_INT1_vect_num 5 -+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ -+ -+/* DMA interrupt vectors */ -+#define DMA_CH0_vect_num 6 -+#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -+#define DMA_CH1_vect_num 7 -+#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -+ -+/* RTC interrupt vectors */ -+#define RTC_OVF_vect_num 10 -+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -+#define RTC_COMP_vect_num 11 -+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 12 -+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 13 -+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_OVF_vect_num 14 -+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LUNF_vect_num 14 -+#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_ERR_vect_num 15 -+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_HUNF_vect_num 15 -+#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCA_vect_num 16 -+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPA_vect_num 16 -+#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCB_vect_num 17 -+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPB_vect_num 17 -+#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCC_vect_num 18 -+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPC_vect_num 18 -+#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCD_vect_num 19 -+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPD_vect_num 19 -+#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ -+ -+/* TCC1 interrupt vectors */ -+#define TCC1_OVF_vect_num 20 -+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -+#define TCC1_ERR_vect_num 21 -+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -+#define TCC1_CCA_vect_num 22 -+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -+#define TCC1_CCB_vect_num 23 -+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 24 -+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 25 -+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 26 -+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 27 -+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ -+ -+/* USARTC1 interrupt vectors */ -+#define USARTC1_RXC_vect_num 28 -+#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -+#define USARTC1_DRE_vect_num 29 -+#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -+#define USARTC1_TXC_vect_num 30 -+#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ -+ -+/* AES interrupt vectors */ -+#define AES_INT_vect_num 31 -+#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 32 -+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -+#define NVM_SPM_vect_num 33 -+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ -+ -+/* PORTB interrupt vectors */ -+#define PORTB_INT0_vect_num 34 -+#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -+#define PORTB_INT1_vect_num 35 -+#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ -+ -+/* PORTE interrupt vectors */ -+#define PORTE_INT0_vect_num 43 -+#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -+#define PORTE_INT1_vect_num 44 -+#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ -+ -+/* TWIE interrupt vectors */ -+#define TWIE_TWIS_vect_num 45 -+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -+#define TWIE_TWIM_vect_num 46 -+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_OVF_vect_num 47 -+#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LUNF_vect_num 47 -+#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_ERR_vect_num 48 -+#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_HUNF_vect_num 48 -+#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCA_vect_num 49 -+#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPA_vect_num 49 -+#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCB_vect_num 50 -+#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPB_vect_num 50 -+#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCC_vect_num 51 -+#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPC_vect_num 51 -+#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCD_vect_num 52 -+#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPD_vect_num 52 -+#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ -+ -+/* USARTE0 interrupt vectors */ -+#define USARTE0_RXC_vect_num 58 -+#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -+#define USARTE0_DRE_vect_num 59 -+#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -+#define USARTE0_TXC_vect_num 60 -+#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT0_vect_num 64 -+#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -+#define PORTD_INT1_vect_num 65 -+#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ -+ -+/* PORTA interrupt vectors */ -+#define PORTA_INT0_vect_num 66 -+#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -+#define PORTA_INT1_vect_num 67 -+#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ -+ -+/* ACA interrupt vectors */ -+#define ACA_AC0_vect_num 68 -+#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -+#define ACA_AC1_vect_num 69 -+#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -+#define ACA_ACW_vect_num 70 -+#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ -+ -+/* ADCA interrupt vectors */ -+#define ADCA_CH0_vect_num 71 -+#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_OVF_vect_num 77 -+#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LUNF_vect_num 77 -+#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_ERR_vect_num 78 -+#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_HUNF_vect_num 78 -+#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCA_vect_num 79 -+#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPA_vect_num 79 -+#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCB_vect_num 80 -+#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPB_vect_num 80 -+#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCC_vect_num 81 -+#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPC_vect_num 81 -+#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCD_vect_num 82 -+#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPD_vect_num 82 -+#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ -+ -+/* SPID interrupt vectors */ -+#define SPID_INT_vect_num 87 -+#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ -+ -+/* USARTD0 interrupt vectors */ -+#define USARTD0_RXC_vect_num 88 -+#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -+#define USARTD0_DRE_vect_num 89 -+#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -+#define USARTD0_TXC_vect_num 90 -+#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ -+ -+/* PORTF interrupt vectors */ -+#define PORTF_INT0_vect_num 104 -+#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -+#define PORTF_INT1_vect_num 105 -+#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_OVF_vect_num 108 -+#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LUNF_vect_num 108 -+#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_ERR_vect_num 109 -+#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_HUNF_vect_num 109 -+#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCA_vect_num 110 -+#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPA_vect_num 110 -+#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCB_vect_num 111 -+#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPB_vect_num 111 -+#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCC_vect_num 112 -+#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPC_vect_num 112 -+#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCD_vect_num 113 -+#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPD_vect_num 113 -+#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ -+ -+/* USB interrupt vectors */ -+#define USB_BUSEVENT_vect_num 125 -+#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -+#define USB_TRNCOMPL_vect_num 126 -+#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (127 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (401408) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (393216) -+#define APP_SECTION_PAGE_SIZE (512) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0x5E000) -+#define APPTABLE_SECTION_SIZE (8192) -+#define APPTABLE_SECTION_PAGE_SIZE (512) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x60000) -+#define BOOT_SECTION_SIZE (8192) -+#define BOOT_SECTION_PAGE_SIZE (512) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (40960) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (4096) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (32768) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (4096) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (6) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (512) -+#define USER_SIGNATURES_PAGE_SIZE (512) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (64) -+#define PROD_SIGNATURES_PAGE_SIZE (512) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 512 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 6 -+ -+/* Fuse Byte 0 Reserved */ -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x98 -+#define SIGNATURE_2 0x45 -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA384C3_H_INCLUDED */ -+ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox384c3.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA384C3_H_INCLUDED ++#define _AVR_ATXMEGA384C3_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t USBCTRL; /* USB Control Register */ ++} CLK_t; ++ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t PRPB; /* Power Reduction Port B */ ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++/* USB Prescaler Division Factor */ ++typedef enum CLK_USBPSDIV_enum ++{ ++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ ++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ ++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ ++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ ++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ ++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ ++} CLK_USBPSDIV_t; ++ ++/* USB Clock Source */ ++typedef enum CLK_USBSRC_enum ++{ ++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ ++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ ++} CLK_USBSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 2 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC2MCREF_enum ++{ ++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC2MCREF_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++ register8_t EBIOUT; /* EBI Output register */ ++ register8_t EVOUTSEL; /* Event Output Select */ ++} PORTCFG_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP02MAP_enum ++{ ++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP02MAP_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP13MAP_enum ++{ ++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP13MAP_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Clock and Event Output Port */ ++typedef enum PORTCFG_CLKEVPIN_enum ++{ ++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ ++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ ++} PORTCFG_CLKEVPIN_t; ++ ++/* EBI Address Output Port */ ++typedef enum PORTCFG_EBIADROUT_enum ++{ ++ PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ ++ PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ ++ PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ ++ PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ ++} PORTCFG_EBIADROUT_t; ++ ++/* EBI Chip Select Output Port */ ++typedef enum PORTCFG_EBICSOUT_enum ++{ ++ PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ ++} PORTCFG_EBICSOUT_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ ++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ ++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ ++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ ++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AES - AES Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* AES Module */ ++typedef struct AES_struct ++{ ++ register8_t CTRL; /* AES Control Register */ ++ register8_t STATUS; /* AES Status Register */ ++ register8_t STATE; /* AES State Register */ ++ register8_t KEY; /* AES Key Register */ ++ register8_t INTCTRL; /* AES Interrupt Control Register */ ++} AES_t; ++ ++/* Interrupt level */ ++typedef enum AES_INTLVL_enum ++{ ++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} AES_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ ++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ ++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ ++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Channel */ ++typedef struct DMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Address Control */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ ++ register8_t REPCNT; /* Channel Repeat Count */ ++ register8_t reserved_0x07; ++ register8_t SRCADDR0; /* Channel Source Address 0 */ ++ register8_t SRCADDR1; /* Channel Source Address 1 */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t DESTADDR0; /* Channel Destination Address 0 */ ++ register8_t DESTADDR1; /* Channel Destination Address 1 */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} DMA_CH_t; ++ ++ ++/* DMA Controller */ ++typedef struct DMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TEMP); /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ DMA_CH_t CH0; /* DMA Channel 0 */ ++ DMA_CH_t CH1; /* DMA Channel 1 */ ++} DMA_t; ++ ++/* Burst mode */ ++typedef enum DMA_CH_BURSTLEN_enum ++{ ++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ ++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ ++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ ++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ ++} DMA_CH_BURSTLEN_t; ++ ++/* Source address reload mode */ ++typedef enum DMA_CH_SRCRELOAD_enum ++{ ++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ ++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ ++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ ++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ ++} DMA_CH_SRCRELOAD_t; ++ ++/* Source addressing mode */ ++typedef enum DMA_CH_SRCDIR_enum ++{ ++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ ++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ ++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ ++} DMA_CH_SRCDIR_t; ++ ++/* Destination adress reload mode */ ++typedef enum DMA_CH_DESTRELOAD_enum ++{ ++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ ++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ ++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ ++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ ++} DMA_CH_DESTRELOAD_t; ++ ++/* Destination adressing mode */ ++typedef enum DMA_CH_DESTDIR_enum ++{ ++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ ++} DMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum DMA_CH_TRIGSRC_enum ++{ ++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ ++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ ++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ ++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ ++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ ++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ ++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ ++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ ++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ ++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ ++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ ++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ ++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ ++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ ++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ ++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ ++} DMA_CH_TRIGSRC_t; ++ ++/* Double buffering mode */ ++typedef enum DMA_DBUFMODE_enum ++{ ++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ ++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ ++} DMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum DMA_PRIMODE_enum ++{ ++ DMA_PRIMODE_RR01_gc = (0x00<<0), /* Round Robin */ ++ DMA_PRIMODE_CH01_gc = (0x01<<0), /* Channel 0 > channel 1 */ ++} DMA_PRIMODE_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_ERRINTLVL_enum ++{ ++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ ++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ ++} DMA_CH_ERRINTLVL_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_TRNINTLVL_enum ++{ ++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ ++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ ++} DMA_CH_TRNINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t reserved_0x07; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++} ADC_t; ++ ++/* Current Limitation */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ ++} ADC_CURRLIMIT_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ ++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ ++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ ++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* SDA Hold Time */ ++typedef enum TWI_SDAHOLD_enum ++{ ++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ ++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ ++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ ++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ ++} TWI_SDAHOLD_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USB - USB ++-------------------------------------------------------------------------- ++*/ ++ ++/* USB Endpoint */ ++typedef struct USB_EP_struct ++{ ++ register8_t STATUS; /* Endpoint Status */ ++ register8_t CTRL; /* Endpoint Control */ ++ _WORDREGISTER(CNT); /* USB Endpoint Counter */ ++ _WORDREGISTER(DATAPTR); /* Data Pointer */ ++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ ++} USB_EP_t; ++ ++ ++/* Universal Serial Bus */ ++typedef struct USB_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t FIFOWP; /* FIFO Write Pointer Register */ ++ register8_t FIFORP; /* FIFO Read Pointer Register */ ++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ ++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ ++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ ++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t reserved_0x20; ++ register8_t reserved_0x21; ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t CAL0; /* Calibration Byte 0 */ ++ register8_t CAL1; /* Calibration Byte 1 */ ++} USB_t; ++ ++ ++/* USB Endpoint Table */ ++typedef struct USB_EP_TABLE_struct ++{ ++ USB_EP_t EP0OUT; /* Endpoint 0 */ ++ USB_EP_t EP0IN; /* Endpoint 0 */ ++ USB_EP_t EP1OUT; /* Endpoint 1 */ ++ USB_EP_t EP1IN; /* Endpoint 1 */ ++ USB_EP_t EP2OUT; /* Endpoint 2 */ ++ USB_EP_t EP2IN; /* Endpoint 2 */ ++ USB_EP_t EP3OUT; /* Endpoint 3 */ ++ USB_EP_t EP3IN; /* Endpoint 3 */ ++ USB_EP_t EP4OUT; /* Endpoint 4 */ ++ USB_EP_t EP4IN; /* Endpoint 4 */ ++ USB_EP_t EP5OUT; /* Endpoint 5 */ ++ USB_EP_t EP5IN; /* Endpoint 5 */ ++ USB_EP_t EP6OUT; /* Endpoint 6 */ ++ USB_EP_t EP6IN; /* Endpoint 6 */ ++ USB_EP_t EP7OUT; /* Endpoint 7 */ ++ USB_EP_t EP7IN; /* Endpoint 7 */ ++ USB_EP_t EP8OUT; /* Endpoint 8 */ ++ USB_EP_t EP8IN; /* Endpoint 8 */ ++ USB_EP_t EP9OUT; /* Endpoint 9 */ ++ USB_EP_t EP9IN; /* Endpoint 9 */ ++ USB_EP_t EP10OUT; /* Endpoint 10 */ ++ USB_EP_t EP10IN; /* Endpoint 10 */ ++ USB_EP_t EP11OUT; /* Endpoint 11 */ ++ USB_EP_t EP11IN; /* Endpoint 11 */ ++ USB_EP_t EP12OUT; /* Endpoint 12 */ ++ USB_EP_t EP12IN; /* Endpoint 12 */ ++ USB_EP_t EP13OUT; /* Endpoint 13 */ ++ USB_EP_t EP13IN; /* Endpoint 13 */ ++ USB_EP_t EP14OUT; /* Endpoint 14 */ ++ USB_EP_t EP14IN; /* Endpoint 14 */ ++ USB_EP_t EP15OUT; /* Endpoint 15 */ ++ USB_EP_t EP15IN; /* Endpoint 15 */ ++ register8_t reserved_0x100; ++ register8_t reserved_0x101; ++ register8_t reserved_0x102; ++ register8_t reserved_0x103; ++ register8_t reserved_0x104; ++ register8_t reserved_0x105; ++ register8_t reserved_0x106; ++ register8_t reserved_0x107; ++ register8_t reserved_0x108; ++ register8_t reserved_0x109; ++ register8_t reserved_0x10A; ++ register8_t reserved_0x10B; ++ register8_t reserved_0x10C; ++ register8_t reserved_0x10D; ++ register8_t reserved_0x10E; ++ register8_t reserved_0x10F; ++ register8_t FRAMENUML; /* Frame Number Low Byte */ ++ register8_t FRAMENUMH; /* Frame Number High Byte */ ++} USB_EP_TABLE_t; ++ ++/* Interrupt level */ ++typedef enum USB_INTLVL_enum ++{ ++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} USB_INTLVL_t; ++ ++/* USB Endpoint Type */ ++typedef enum USB_EP_TYPE_enum ++{ ++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ ++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ ++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ ++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ ++} USB_EP_TYPE_t; ++ ++/* USB Endpoint Buffersize */ ++typedef enum USB_EP_BUFSIZE_enum ++{ ++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ ++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ ++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ ++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ ++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ ++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ ++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ ++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ ++} USB_EP_BUFSIZE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - I/O Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* I/O Port Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Byte Mode */ ++typedef enum TC_BYTEM_enum ++{ ++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ ++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ ++} TC_BYTEM_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC2 - 16-bit Timer/Counter type 2 ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter type 2 */ ++typedef struct TC2_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t reserved_0x03; ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t reserved_0x08; ++ register8_t CTRLF; /* Control Register F */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t LCNT; /* Low Byte Count */ ++ register8_t HCNT; /* High Byte Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t LPER; /* Low Byte Period */ ++ register8_t HPER; /* High Byte Period */ ++ register8_t LCMPA; /* Low Byte Compare A */ ++ register8_t HCMPA; /* High Byte Compare A */ ++ register8_t LCMPB; /* Low Byte Compare B */ ++ register8_t HCMPB; /* High Byte Compare B */ ++ register8_t LCMPC; /* Low Byte Compare C */ ++ register8_t HCMPC; /* High Byte Compare C */ ++ register8_t LCMPD; /* Low Byte Compare D */ ++ register8_t HCMPD; /* High Byte Compare D */ ++} TC2_t; ++ ++/* Clock Selection */ ++typedef enum TC2_CLKSEL_enum ++{ ++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC2_CLKSEL_t; ++ ++/* Byte Mode */ ++typedef enum TC2_BYTEM_enum ++{ ++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ ++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ ++} TC2_BYTEM_t; ++ ++/* High Byte Underflow Interrupt Level */ ++typedef enum TC2_HUNFINTLVL_enum ++{ ++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_HUNFINTLVL_t; ++ ++/* Low Byte Underflow Interrupt Level */ ++typedef enum TC2_LUNFINTLVL_enum ++{ ++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LUNFINTLVL_t; ++ ++/* Low Byte Compare D Interrupt Level */ ++typedef enum TC2_LCMPDINTLVL_enum ++{ ++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC2_LCMPDINTLVL_t; ++ ++/* Low Byte Compare C Interrupt Level */ ++typedef enum TC2_LCMPCINTLVL_enum ++{ ++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC2_LCMPCINTLVL_t; ++ ++/* Low Byte Compare B Interrupt Level */ ++typedef enum TC2_LCMPBINTLVL_enum ++{ ++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_LCMPBINTLVL_t; ++ ++/* Low Byte Compare A Interrupt Level */ ++typedef enum TC2_LCMPAINTLVL_enum ++{ ++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LCMPAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMD_enum ++{ ++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC2_CMD_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMDEN_enum ++{ ++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ ++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ ++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ ++} TC2_CMDEN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AWEX - Timer/Counter Advanced Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - Timer/Counter High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t reserved_0x00; ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* Timer Oscillator pin location */ ++typedef enum TOSCSEL_enum ++{ ++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ ++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ ++} TOSCSEL_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* BOD operation */ ++typedef enum BODACT_enum ++{ ++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BODACT_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WDP_enum ++{ ++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ ++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ ++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ ++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ ++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ ++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ ++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ ++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ ++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ ++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ ++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ ++} WDP_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LOCKBIT - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ ++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t USBCAL0; /* USB Calibration Byte 0 */ ++ register8_t USBCAL1; /* USB Calibration Byte 1 */ ++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ ++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define AES (*(AES_t *) 0x00C0) /* AES Module */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ ++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ ++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ ++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ ++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ ++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ ++#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ ++#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) ++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) ++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) ++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++#define CLK_USBCTRL _SFR_MEM8(0x0044) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLL - DFLL */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPB _SFR_MEM8(0x0072) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) ++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) ++ ++/* AES - AES Module */ ++#define AES_CTRL _SFR_MEM8(0x00C0) ++#define AES_STATUS _SFR_MEM8(0x00C1) ++#define AES_STATE _SFR_MEM8(0x00C2) ++#define AES_KEY _SFR_MEM8(0x00C3) ++#define AES_INTCTRL _SFR_MEM8(0x00C4) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* DMA - DMA Controller */ ++#define DMA_CTRL _SFR_MEM8(0x0100) ++#define DMA_INTFLAGS _SFR_MEM8(0x0103) ++#define DMA_STATUS _SFR_MEM8(0x0104) ++#define DMA_TEMP _SFR_MEM16(0x0106) ++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) ++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) ++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) ++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) ++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) ++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) ++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) ++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) ++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) ++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) ++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) ++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) ++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) ++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* USB - Universal Serial Bus */ ++#define USB_CTRLA _SFR_MEM8(0x04C0) ++#define USB_CTRLB _SFR_MEM8(0x04C1) ++#define USB_STATUS _SFR_MEM8(0x04C2) ++#define USB_ADDR _SFR_MEM8(0x04C3) ++#define USB_FIFOWP _SFR_MEM8(0x04C4) ++#define USB_FIFORP _SFR_MEM8(0x04C5) ++#define USB_EPPTR _SFR_MEM16(0x04C6) ++#define USB_INTCTRLA _SFR_MEM8(0x04C8) ++#define USB_INTCTRLB _SFR_MEM8(0x04C9) ++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) ++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) ++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) ++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) ++#define USB_CAL0 _SFR_MEM8(0x04FA) ++#define USB_CAL1 _SFR_MEM8(0x04FB) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_REMAP _SFR_MEM8(0x060E) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_REMAP _SFR_MEM8(0x062E) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_REMAP _SFR_MEM8(0x068E) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORT - I/O Ports */ ++#define PORTF_DIR _SFR_MEM8(0x06A0) ++#define PORTF_DIRSET _SFR_MEM8(0x06A1) ++#define PORTF_DIRCLR _SFR_MEM8(0x06A2) ++#define PORTF_DIRTGL _SFR_MEM8(0x06A3) ++#define PORTF_OUT _SFR_MEM8(0x06A4) ++#define PORTF_OUTSET _SFR_MEM8(0x06A5) ++#define PORTF_OUTCLR _SFR_MEM8(0x06A6) ++#define PORTF_OUTTGL _SFR_MEM8(0x06A7) ++#define PORTF_IN _SFR_MEM8(0x06A8) ++#define PORTF_INTCTRL _SFR_MEM8(0x06A9) ++#define PORTF_INT0MASK _SFR_MEM8(0x06AA) ++#define PORTF_INT1MASK _SFR_MEM8(0x06AB) ++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) ++#define PORTF_REMAP _SFR_MEM8(0x06AE) ++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) ++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) ++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) ++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) ++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) ++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) ++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) ++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCC2_CTRLA _SFR_MEM8(0x0800) ++#define TCC2_CTRLB _SFR_MEM8(0x0801) ++#define TCC2_CTRLC _SFR_MEM8(0x0802) ++#define TCC2_CTRLE _SFR_MEM8(0x0804) ++#define TCC2_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC2_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC2_CTRLF _SFR_MEM8(0x0809) ++#define TCC2_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC2_LCNT _SFR_MEM8(0x0820) ++#define TCC2_HCNT _SFR_MEM8(0x0821) ++#define TCC2_LPER _SFR_MEM8(0x0826) ++#define TCC2_HPER _SFR_MEM8(0x0827) ++#define TCC2_LCMPA _SFR_MEM8(0x0828) ++#define TCC2_HCMPA _SFR_MEM8(0x0829) ++#define TCC2_LCMPB _SFR_MEM8(0x082A) ++#define TCC2_HCMPB _SFR_MEM8(0x082B) ++#define TCC2_LCMPC _SFR_MEM8(0x082C) ++#define TCC2_HCMPC _SFR_MEM8(0x082D) ++#define TCC2_LCMPD _SFR_MEM8(0x082E) ++#define TCC2_HCMPD _SFR_MEM8(0x082F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_STATUSSET _SFR_MEM8(0x0885) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1_DATA _SFR_MEM8(0x08B0) ++#define USARTC1_STATUS _SFR_MEM8(0x08B1) ++#define USARTC1_CTRLA _SFR_MEM8(0x08B3) ++#define USARTC1_CTRLB _SFR_MEM8(0x08B4) ++#define USARTC1_CTRLC _SFR_MEM8(0x08B5) ++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) ++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCD2_CTRLA _SFR_MEM8(0x0900) ++#define TCD2_CTRLB _SFR_MEM8(0x0901) ++#define TCD2_CTRLC _SFR_MEM8(0x0902) ++#define TCD2_CTRLE _SFR_MEM8(0x0904) ++#define TCD2_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD2_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD2_CTRLF _SFR_MEM8(0x0909) ++#define TCD2_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD2_LCNT _SFR_MEM8(0x0920) ++#define TCD2_HCNT _SFR_MEM8(0x0921) ++#define TCD2_LPER _SFR_MEM8(0x0926) ++#define TCD2_HPER _SFR_MEM8(0x0927) ++#define TCD2_LCMPA _SFR_MEM8(0x0928) ++#define TCD2_HCMPA _SFR_MEM8(0x0929) ++#define TCD2_LCMPB _SFR_MEM8(0x092A) ++#define TCD2_HCMPB _SFR_MEM8(0x092B) ++#define TCD2_LCMPC _SFR_MEM8(0x092C) ++#define TCD2_HCMPC _SFR_MEM8(0x092D) ++#define TCD2_LCMPD _SFR_MEM8(0x092E) ++#define TCD2_HCMPD _SFR_MEM8(0x092F) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCE2_CTRLA _SFR_MEM8(0x0A00) ++#define TCE2_CTRLB _SFR_MEM8(0x0A01) ++#define TCE2_CTRLC _SFR_MEM8(0x0A02) ++#define TCE2_CTRLE _SFR_MEM8(0x0A04) ++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE2_CTRLF _SFR_MEM8(0x0A09) ++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE2_LCNT _SFR_MEM8(0x0A20) ++#define TCE2_HCNT _SFR_MEM8(0x0A21) ++#define TCE2_LPER _SFR_MEM8(0x0A26) ++#define TCE2_HPER _SFR_MEM8(0x0A27) ++#define TCE2_LCMPA _SFR_MEM8(0x0A28) ++#define TCE2_HCMPA _SFR_MEM8(0x0A29) ++#define TCE2_LCMPB _SFR_MEM8(0x0A2A) ++#define TCE2_HCMPB _SFR_MEM8(0x0A2B) ++#define TCE2_LCMPC _SFR_MEM8(0x0A2C) ++#define TCE2_HCMPC _SFR_MEM8(0x0A2D) ++#define TCE2_LCMPD _SFR_MEM8(0x0A2E) ++#define TCE2_HCMPD _SFR_MEM8(0x0A2F) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCF0_CTRLA _SFR_MEM8(0x0B00) ++#define TCF0_CTRLB _SFR_MEM8(0x0B01) ++#define TCF0_CTRLC _SFR_MEM8(0x0B02) ++#define TCF0_CTRLD _SFR_MEM8(0x0B03) ++#define TCF0_CTRLE _SFR_MEM8(0x0B04) ++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) ++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) ++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) ++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) ++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF0_TEMP _SFR_MEM8(0x0B0F) ++#define TCF0_CNT _SFR_MEM16(0x0B20) ++#define TCF0_PER _SFR_MEM16(0x0B26) ++#define TCF0_CCA _SFR_MEM16(0x0B28) ++#define TCF0_CCB _SFR_MEM16(0x0B2A) ++#define TCF0_CCC _SFR_MEM16(0x0B2C) ++#define TCF0_CCD _SFR_MEM16(0x0B2E) ++#define TCF0_PERBUF _SFR_MEM16(0x0B36) ++#define TCF0_CCABUF _SFR_MEM16(0x0B38) ++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) ++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) ++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCF2_CTRLA _SFR_MEM8(0x0B00) ++#define TCF2_CTRLB _SFR_MEM8(0x0B01) ++#define TCF2_CTRLC _SFR_MEM8(0x0B02) ++#define TCF2_CTRLE _SFR_MEM8(0x0B04) ++#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF2_CTRLF _SFR_MEM8(0x0B09) ++#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF2_LCNT _SFR_MEM8(0x0B20) ++#define TCF2_HCNT _SFR_MEM8(0x0B21) ++#define TCF2_LPER _SFR_MEM8(0x0B26) ++#define TCF2_HPER _SFR_MEM8(0x0B27) ++#define TCF2_LCMPA _SFR_MEM8(0x0B28) ++#define TCF2_HCMPA _SFR_MEM8(0x0B29) ++#define TCF2_LCMPB _SFR_MEM8(0x0B2A) ++#define TCF2_HCMPB _SFR_MEM8(0x0B2B) ++#define TCF2_LCMPC _SFR_MEM8(0x0B2C) ++#define TCF2_HCMPC _SFR_MEM8(0x0B2D) ++#define TCF2_LCMPD _SFR_MEM8(0x0B2E) ++#define TCF2_HCMPD _SFR_MEM8(0x0B2F) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTF0_DATA _SFR_MEM8(0x0BA0) ++#define USARTF0_STATUS _SFR_MEM8(0x0BA1) ++#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) ++#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) ++#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) ++#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) ++#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* CLK.USBCTRL bit masks and bit positions */ ++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ ++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ ++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ ++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ ++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ ++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ ++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ ++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ ++ ++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ ++#define CLK_USBSRC_gp 1 /* Clock Source group position. */ ++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ ++ ++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_USB_bm 0x40 /* USB bit mask. */ ++#define PR_USB_bp 6 /* USB bit position. */ ++ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ ++#define PR_EBI_bp 3 /* External Bus Interface bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ ++#define PR_DAC_bp 2 /* Port A DAC bit position. */ ++ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPB bit masks and bit positions */ ++/* PR_DAC Predefined. */ ++/* PR_DAC Predefined. */ ++ ++/* PR_ADC Predefined. */ ++/* PR_ADC Predefined. */ ++ ++/* PR_AC Predefined. */ ++/* PR_AC Predefined. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ ++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ ++ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ ++ ++/* PORTCFG.EBIOUT bit masks and bit positions */ ++#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ ++#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ ++#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ ++#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ ++#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ ++#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ ++ ++#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ ++#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ ++#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ ++#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ ++#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ ++#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ ++ ++/* PORTCFG.EVOUTSEL bit masks and bit positions */ ++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ ++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ ++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ ++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ ++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ ++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ ++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ ++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ ++ ++/* AES - AES Module */ ++/* AES.CTRL bit masks and bit positions */ ++#define AES_START_bm 0x80 /* Start/Run bit mask. */ ++#define AES_START_bp 7 /* Start/Run bit position. */ ++ ++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ ++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ ++ ++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ ++#define AES_RESET_bp 5 /* AES Software Reset bit position. */ ++ ++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ ++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ ++ ++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ ++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ ++ ++/* AES.STATUS bit masks and bit positions */ ++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ ++#define AES_ERROR_bp 7 /* AES Error bit position. */ ++ ++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ ++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ ++ ++/* AES.INTCTRL bit masks and bit positions */ ++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define AES_INTLVL_gp 0 /* Interrupt level group position. */ ++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* DMA - DMA Controller */ ++/* DMA_CH.CTRLA bit masks and bit positions */ ++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ ++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ ++ ++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ ++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ ++ ++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ ++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ ++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ ++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ ++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ ++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ ++ ++/* DMA_CH.CTRLB bit masks and bit positions */ ++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ ++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ ++ ++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ ++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ ++ ++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ ++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ ++ ++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ ++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ ++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ ++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ ++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ ++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ ++ ++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ ++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ ++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ ++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ ++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ ++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ ++ ++/* DMA_CH.ADDRCTRL bit masks and bit positions */ ++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ ++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ ++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ ++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ ++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ ++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ ++ ++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ ++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ ++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ ++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ ++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ ++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ ++ ++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ ++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ ++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ ++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ ++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ ++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ ++ ++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ ++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ ++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ ++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ ++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ ++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ ++ ++/* DMA_CH.TRIGSRC bit masks and bit positions */ ++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++/* DMA.CTRL bit masks and bit positions */ ++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define DMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define DMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define DMA_DBUFMODE_bm 0x04 /* Double Buffering Mode bit mask. */ ++#define DMA_DBUFMODE_bp 2 /* Double Buffering Mode bit position. */ ++ ++#define DMA_PRIMODE_bm 0x01 /* Channel Priority Mode bit mask. */ ++#define DMA_PRIMODE_bp 0 /* Channel Priority Mode bit position. */ ++ ++/* DMA.INTFLAGS bit masks and bit positions */ ++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++/* DMA.STATUS bit masks and bit positions */ ++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ ++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ ++ ++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ ++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ ++ ++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ ++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ ++ ++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ ++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ ++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ ++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ ++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ ++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ ++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ ++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ ++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ ++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ ++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ ++ ++#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */ ++#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */ ++#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ ++#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */ ++#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ ++#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */ ++#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ ++#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */ ++#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ ++#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ ++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* ADC.SAMPCTRL bit masks and bit positions */ ++#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ ++#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ ++#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ ++#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ ++#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ ++#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ ++#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ ++#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ ++#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ ++#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ ++#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ ++#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ ++#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ ++#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* RTC - Real-Time Counter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* USB - USB */ ++/* USB_EP.STATUS bit masks and bit positions */ ++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ ++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ ++ ++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ ++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ ++ ++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ ++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ ++ ++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ ++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ ++ ++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ ++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ ++ ++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ ++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ ++ ++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ ++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ ++ ++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ ++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ ++ ++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ ++ ++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ ++ ++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ ++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ ++ ++/* USB_EP.CTRL bit masks and bit positions */ ++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ ++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ ++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ ++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ ++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ ++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ ++ ++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ ++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ ++ ++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ ++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ ++ ++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ ++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ ++ ++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ ++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ ++ ++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ ++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ ++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ ++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ ++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ ++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ ++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ ++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ ++ ++/* USB_EP.CNT bit masks and bit positions */ ++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ ++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ ++ ++/* USB.CTRLA bit masks and bit positions */ ++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ ++#define USB_ENABLE_bp 7 /* USB Enable bit position. */ ++ ++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ ++#define USB_SPEED_bp 6 /* Speed Select bit position. */ ++ ++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ ++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ ++ ++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ ++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ ++ ++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ ++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ ++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ ++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ ++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ ++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ ++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ ++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ ++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ ++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ ++ ++/* USB.CTRLB bit masks and bit positions */ ++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ ++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ ++ ++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ ++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ ++ ++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ ++#define USB_GNACK_bp 1 /* Global NACK bit position. */ ++ ++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ ++#define USB_ATTACH_bp 0 /* Attach bit position. */ ++ ++/* USB.STATUS bit masks and bit positions */ ++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ ++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ ++ ++#define USB_RESUME_bm 0x04 /* Resume bit mask. */ ++#define USB_RESUME_bp 2 /* Resume bit position. */ ++ ++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ ++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ ++ ++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ ++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ ++ ++/* USB.ADDR bit masks and bit positions */ ++#define USB_ADDR_gm 0x7F /* Device Address group mask. */ ++#define USB_ADDR_gp 0 /* Device Address group position. */ ++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ ++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ ++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ ++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ ++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ ++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ ++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ ++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ ++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ ++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ ++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ ++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ ++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ ++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ ++ ++/* USB.FIFOWP bit masks and bit positions */ ++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ ++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ ++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ ++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ ++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ ++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ ++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ ++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ ++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ ++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ ++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ ++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ ++ ++/* USB.FIFORP bit masks and bit positions */ ++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ ++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ ++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ ++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ ++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ ++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ ++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ ++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ ++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ ++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ ++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ ++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ ++ ++/* USB.INTCTRLA bit masks and bit positions */ ++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ ++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ ++ ++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ ++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ ++ ++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ ++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ ++ ++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ ++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ ++ ++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* USB.INTCTRLB bit masks and bit positions */ ++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ ++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ ++ ++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ ++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ ++ ++/* USB.INTFLAGSACLR bit masks and bit positions */ ++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ ++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ ++ ++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ ++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ ++ ++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ ++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ ++ ++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ ++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ ++ ++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ ++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ ++ ++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ ++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ ++ ++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ ++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ ++ ++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ ++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSASET bit masks and bit positions */ ++/* USB_SOFIF Predefined. */ ++/* USB_SOFIF Predefined. */ ++ ++/* USB_SUSPENDIF Predefined. */ ++/* USB_SUSPENDIF Predefined. */ ++ ++/* USB_RESUMEIF Predefined. */ ++/* USB_RESUMEIF Predefined. */ ++ ++/* USB_RSTIF Predefined. */ ++/* USB_RSTIF Predefined. */ ++ ++/* USB_CRCIF Predefined. */ ++/* USB_CRCIF Predefined. */ ++ ++/* USB_UNFIF Predefined. */ ++/* USB_UNFIF Predefined. */ ++ ++/* USB_OVFIF Predefined. */ ++/* USB_OVFIF Predefined. */ ++ ++/* USB_STALLIF Predefined. */ ++/* USB_STALLIF Predefined. */ ++ ++/* USB.INTFLAGSBCLR bit masks and bit positions */ ++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ ++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ ++ ++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ ++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSBSET bit masks and bit positions */ ++/* USB_TRNIF Predefined. */ ++/* USB_TRNIF Predefined. */ ++ ++/* USB_SETUPIF Predefined. */ ++/* USB_SETUPIF Predefined. */ ++ ++/* PORT - I/O Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_SPI_bm 0x20 /* SPI bit mask. */ ++#define PORT_SPI_bp 5 /* SPI bit position. */ ++ ++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ ++#define PORT_USART0_bp 4 /* USART0 bit position. */ ++ ++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ ++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ ++ ++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ ++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ ++ ++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ ++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ ++ ++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ ++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD Predefined. */ ++/* TC0_CMD Predefined. */ ++ ++/* TC0_LUPD Predefined. */ ++/* TC0_LUPD Predefined. */ ++ ++/* TC0_DIR Predefined. */ ++/* TC0_DIR Predefined. */ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV Predefined. */ ++/* TC0_CCDBV Predefined. */ ++ ++/* TC0_CCCBV Predefined. */ ++/* TC0_CCCBV Predefined. */ ++ ++/* TC0_CCBBV Predefined. */ ++/* TC0_CCBBV Predefined. */ ++ ++/* TC0_CCABV Predefined. */ ++/* TC0_CCABV Predefined. */ ++ ++/* TC0_PERBV Predefined. */ ++/* TC0_PERBV Predefined. */ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD Predefined. */ ++/* TC1_CMD Predefined. */ ++ ++/* TC1_LUPD Predefined. */ ++/* TC1_LUPD Predefined. */ ++ ++/* TC1_DIR Predefined. */ ++/* TC1_DIR Predefined. */ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV Predefined. */ ++/* TC1_CCBBV Predefined. */ ++ ++/* TC1_CCABV Predefined. */ ++/* TC1_CCABV Predefined. */ ++ ++/* TC1_PERBV Predefined. */ ++/* TC1_PERBV Predefined. */ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++/* TC2.CTRLA bit masks and bit positions */ ++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC2.CTRLB bit masks and bit positions */ ++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ ++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ ++ ++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ ++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ ++ ++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ ++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ ++ ++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ ++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ ++ ++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ ++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ ++ ++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ ++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ ++ ++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ ++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ ++ ++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ ++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ ++ ++/* TC2.CTRLC bit masks and bit positions */ ++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ ++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ ++ ++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ ++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ ++ ++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ ++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ ++ ++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ ++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ ++ ++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ ++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ ++ ++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ ++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ ++ ++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ ++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ ++ ++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ ++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ ++ ++/* TC2.CTRLE bit masks and bit positions */ ++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC2.INTCTRLA bit masks and bit positions */ ++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ ++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ ++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ ++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ ++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ ++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ ++ ++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ ++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ ++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ ++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ ++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ ++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ ++ ++/* TC2.INTCTRLB bit masks and bit positions */ ++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ ++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ ++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ ++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ ++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ ++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ ++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ ++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ ++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ ++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ ++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ ++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ ++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ ++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ ++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ ++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ ++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ ++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ ++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ ++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ ++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ ++ ++/* TC2.CTRLF bit masks and bit positions */ ++#define TC2_CMD_gm 0x0C /* Command group mask. */ ++#define TC2_CMD_gp 2 /* Command group position. */ ++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC2_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC2_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ ++#define TC2_CMDEN_gp 0 /* Command Enable group position. */ ++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ ++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ ++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ ++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ ++ ++/* TC2.INTFLAGS bit masks and bit positions */ ++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ ++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ ++ ++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ ++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ ++ ++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ ++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ ++ ++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ ++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ ++ ++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ ++ ++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ ++ ++/* AWEX - Timer/Counter Advanced Waveform Extension */ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++/* AWEX.STATUSSET bit masks and bit positions */ ++/* AWEX_FDF Predefined. */ ++/* AWEX_FDF Predefined. */ ++ ++/* AWEX_DTHSBUFV Predefined. */ ++/* AWEX_DTHSBUFV Predefined. */ ++ ++/* AWEX_DTLSBUFV Predefined. */ ++/* AWEX_DTLSBUFV Predefined. */ ++ ++/* HIRES - Timer/Counter High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ ++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* LOCKBIT - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* DMA interrupt vectors */ ++#define DMA_CH0_vect_num 6 ++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ ++#define DMA_CH1_vect_num 7 ++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LUNF_vect_num 14 ++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_HUNF_vect_num 15 ++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPA_vect_num 16 ++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPB_vect_num 17 ++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPC_vect_num 18 ++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPD_vect_num 19 ++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* USARTC1 interrupt vectors */ ++#define USARTC1_RXC_vect_num 28 ++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ ++#define USARTC1_DRE_vect_num 29 ++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ ++#define USARTC1_TXC_vect_num 30 ++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ ++ ++/* AES interrupt vectors */ ++#define AES_INT_vect_num 31 ++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LUNF_vect_num 47 ++#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_HUNF_vect_num 48 ++#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPA_vect_num 49 ++#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPB_vect_num 50 ++#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPC_vect_num 51 ++#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPD_vect_num 52 ++#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LUNF_vect_num 77 ++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_HUNF_vect_num 78 ++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPA_vect_num 79 ++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPB_vect_num 80 ++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPC_vect_num 81 ++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPD_vect_num 82 ++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* PORTF interrupt vectors */ ++#define PORTF_INT0_vect_num 104 ++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ ++#define PORTF_INT1_vect_num 105 ++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_OVF_vect_num 108 ++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LUNF_vect_num 108 ++#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_ERR_vect_num 109 ++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_HUNF_vect_num 109 ++#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCA_vect_num 110 ++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPA_vect_num 110 ++#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCB_vect_num 111 ++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPB_vect_num 111 ++#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCC_vect_num 112 ++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPC_vect_num 112 ++#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCD_vect_num 113 ++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPD_vect_num 113 ++#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ ++ ++/* USB interrupt vectors */ ++#define USB_BUSEVENT_vect_num 125 ++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ ++#define USB_TRNCOMPL_vect_num 126 ++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (127 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (401408) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (393216) ++#define APP_SECTION_PAGE_SIZE (512) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x5E000) ++#define APPTABLE_SECTION_SIZE (8192) ++#define APPTABLE_SECTION_PAGE_SIZE (512) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x60000) ++#define BOOT_SECTION_SIZE (8192) ++#define BOOT_SECTION_PAGE_SIZE (512) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (40960) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (4096) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (32768) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (4096) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (6) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (512) ++#define USER_SIGNATURES_PAGE_SIZE (512) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (64) ++#define PROD_SIGNATURES_PAGE_SIZE (512) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 512 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 Reserved */ ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x98 ++#define SIGNATURE_2 0x45 ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA384C3_H_INCLUDED */ ++ diff --git a/include/avr/iox384d3.h b/include/avr/iox384d3.h new file mode 100644 -index 0000000..1cb162f +index 0000000..36b6faa --- /dev/null +++ b/include/avr/iox384d3.h @@ -0,0 +1,5789 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox384d3.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA384D3_H_INCLUDED -+#define _AVR_ATXMEGA384D3_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+VPORT - Virtual Ports -+-------------------------------------------------------------------------- -+*/ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t reserved_0x04; -+} CLK_t; -+ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t reserved_0x02; -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t PRPD; /* Power Reduction Port D */ -+ register8_t PRPE; /* Power Reduction Port E */ -+ register8_t PRPF; /* Power Reduction Port F */ -+} PR_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from 32.768 kHz internal oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from 32.768 kHz internal oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control Register */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+/* 2 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC2MCREF_enum -+{ -+ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC2MCREF_t; -+ -+/* 32 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC32MCREF_enum -+{ -+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -+} OSC_RC32MCREF_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t ANAINIT; /* Analog Startup Delay */ -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t AWEXLOCK; /* AWEX Lock */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORTCFG - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t VPCTRLA; /* Virtual Port Control Register A */ -+ register8_t VPCTRLB; /* Virtual Port Control Register B */ -+ register8_t CLKEVOUT; /* Clock and Event Out Register */ -+ register8_t EBIOUT; /* EBI Output register */ -+ register8_t EVOUTSEL; /* Event Output Select */ -+} PORTCFG_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP02MAP_enum -+{ -+ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ -+ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ -+ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ -+ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ -+ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ -+ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ -+ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ -+ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ -+ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ -+ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ -+ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ -+ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ -+ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ -+ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ -+ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ -+ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -+} PORTCFG_VP02MAP_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP13MAP_enum -+{ -+ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ -+ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ -+ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ -+ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ -+ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ -+ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ -+ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ -+ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ -+ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ -+ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ -+ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ -+ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ -+ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ -+ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ -+ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ -+ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -+} PORTCFG_VP13MAP_t; -+ -+/* System Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ -+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ -+ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -+} PORTCFG_CLKOUT_t; -+ -+/* Peripheral Clock Output Select */ -+typedef enum PORTCFG_CLKOUTSEL_enum -+{ -+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -+} PORTCFG_CLKOUTSEL_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ -+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ -+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -+} PORTCFG_EVOUT_t; -+ -+/* Clock and Event Output Port */ -+typedef enum PORTCFG_CLKEVPIN_enum -+{ -+ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ -+ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -+} PORTCFG_CLKEVPIN_t; -+ -+/* EBI Address Output Port */ -+typedef enum PORTCFG_EBIADROUT_enum -+{ -+ PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ -+ PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ -+ PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ -+ PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ -+} PORTCFG_EBIADROUT_t; -+ -+/* EBI Chip Select Output Port */ -+typedef enum PORTCFG_EBICSOUT_enum -+{ -+ PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ -+} PORTCFG_EBICSOUT_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -+ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ -+ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ -+ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ -+ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+} EVSYS_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ -+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ -+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ -+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ -+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ -+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ -+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ -+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ -+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ -+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ -+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ -+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ -+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ -+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ -+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ -+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ -+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ -+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ -+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ -+ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ -+ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ -+ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ -+ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ -+ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ -+ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ -+ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ -+ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ -+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ -+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ -+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ -+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ -+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ -+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ -+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ -+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ -+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ -+ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ -+ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ -+ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ -+ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ -+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ -+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ -+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ -+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ -+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -+ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ -+ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ -+ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ -+ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ -+ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -+} EVSYS_CHMUX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ -+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ -+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ -+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ -+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} NVM_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t reserved_0x07; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+} ADC_t; -+ -+/* Current Limitation */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -+} ADC_CURRLIMIT_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+} ADC_CH_MUXNEG_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ -+ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ -+ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ -+ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC - Real-Time Counter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Real-Time Counter */ -+typedef struct RTC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary register */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ _WORDREGISTER(CNT); /* Count Register */ -+ _WORDREGISTER(PER); /* Period Register */ -+ _WORDREGISTER(COMP); /* Compare Register */ -+} RTC_t; -+ -+/* Prescaler Factor */ -+typedef enum RTC_PRESCALER_enum -+{ -+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ -+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ -+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ -+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ -+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ -+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ -+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ -+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -+} RTC_PRESCALER_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC_COMPINTLVL_enum -+{ -+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC_OVFINTLVL_enum -+{ -+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+} TWI_t; -+ -+/* SDA Hold Time */ -+typedef enum TWI_SDAHOLD_enum -+{ -+ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ -+ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ -+ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ -+ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -+} TWI_SDAHOLD_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - I/O Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INT0MASK; /* Port Interrupt 0 Mask */ -+ register8_t INT1MASK; /* Port Interrupt 1 Mask */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t REMAP; /* I/O Port Pin Remap Register */ -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Port Interrupt 0 Level */ -+typedef enum PORT_INT0LVL_enum -+{ -+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INT0LVL_t; -+ -+/* Port Interrupt 1 Level */ -+typedef enum PORT_INT1LVL_enum -+{ -+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ -+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ -+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -+} PORT_INT1LVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 0 */ -+typedef struct TC0_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC0_t; -+ -+ -+/* 16-bit Timer/Counter 1 */ -+typedef struct TC1_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+} TC1_t; -+ -+/* Clock Selection */ -+typedef enum TC_CLKSEL_enum -+{ -+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_CLKSEL_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC_WGMODE_enum -+{ -+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC_WGMODE_t; -+ -+/* Byte Mode */ -+typedef enum TC_BYTEM_enum -+{ -+ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ -+ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -+} TC_BYTEM_t; -+ -+/* Event Action */ -+typedef enum TC_EVACT_enum -+{ -+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ -+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ -+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ -+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ -+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ -+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC_EVSEL_enum -+{ -+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_EVSEL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC_ERRINTLVL_enum -+{ -+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC_OVFINTLVL_enum -+{ -+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_OVFINTLVL_t; -+ -+/* Compare or Capture D Interrupt Level */ -+typedef enum TC_CCDINTLVL_enum -+{ -+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC_CCDINTLVL_t; -+ -+/* Compare or Capture C Interrupt Level */ -+typedef enum TC_CCCINTLVL_enum -+{ -+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC_CCCINTLVL_t; -+ -+/* Compare or Capture B Interrupt Level */ -+typedef enum TC_CCBINTLVL_enum -+{ -+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_CCBINTLVL_t; -+ -+/* Compare or Capture A Interrupt Level */ -+typedef enum TC_CCAINTLVL_enum -+{ -+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_CCAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC_CMD_enum -+{ -+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC2 - 16-bit Timer/Counter type 2 -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter type 2 */ -+typedef struct TC2_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t reserved_0x03; -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t reserved_0x08; -+ register8_t CTRLF; /* Control Register F */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t LCNT; /* Low Byte Count */ -+ register8_t HCNT; /* High Byte Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t LPER; /* Low Byte Period */ -+ register8_t HPER; /* High Byte Period */ -+ register8_t LCMPA; /* Low Byte Compare A */ -+ register8_t HCMPA; /* High Byte Compare A */ -+ register8_t LCMPB; /* Low Byte Compare B */ -+ register8_t HCMPB; /* High Byte Compare B */ -+ register8_t LCMPC; /* Low Byte Compare C */ -+ register8_t HCMPC; /* High Byte Compare C */ -+ register8_t LCMPD; /* Low Byte Compare D */ -+ register8_t HCMPD; /* High Byte Compare D */ -+} TC2_t; -+ -+/* Clock Selection */ -+typedef enum TC2_CLKSEL_enum -+{ -+ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC2_CLKSEL_t; -+ -+/* Byte Mode */ -+typedef enum TC2_BYTEM_enum -+{ -+ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ -+ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -+} TC2_BYTEM_t; -+ -+/* High Byte Underflow Interrupt Level */ -+typedef enum TC2_HUNFINTLVL_enum -+{ -+ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_HUNFINTLVL_t; -+ -+/* Low Byte Underflow Interrupt Level */ -+typedef enum TC2_LUNFINTLVL_enum -+{ -+ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LUNFINTLVL_t; -+ -+/* Low Byte Compare D Interrupt Level */ -+typedef enum TC2_LCMPDINTLVL_enum -+{ -+ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC2_LCMPDINTLVL_t; -+ -+/* Low Byte Compare C Interrupt Level */ -+typedef enum TC2_LCMPCINTLVL_enum -+{ -+ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC2_LCMPCINTLVL_t; -+ -+/* Low Byte Compare B Interrupt Level */ -+typedef enum TC2_LCMPBINTLVL_enum -+{ -+ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_LCMPBINTLVL_t; -+ -+/* Low Byte Compare A Interrupt Level */ -+typedef enum TC2_LCMPAINTLVL_enum -+{ -+ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LCMPAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMD_enum -+{ -+ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC2_CMD_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMDEN_enum -+{ -+ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ -+ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ -+ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -+} TC2_CMDEN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AWEX - Timer/Counter Advanced Waveform Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Advanced Waveform Extension */ -+typedef struct AWEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t FDEMASK; /* Fault Detection Event Mask */ -+ register8_t FDCTRL; /* Fault Detection Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t STATUSSET; /* Status Set Register */ -+ register8_t DTBOTH; /* Dead Time Both Sides */ -+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ -+ register8_t DTLS; /* Dead Time Low Side */ -+ register8_t DTHS; /* Dead Time High Side */ -+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ -+ register8_t DTHSBUF; /* Dead Time High Side Buffer */ -+ register8_t OUTOVEN; /* Output Override Enable */ -+} AWEX_t; -+ -+/* Fault Detect Action */ -+typedef enum AWEX_FDACT_enum -+{ -+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ -+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -+} AWEX_FDACT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+HIRES - Timer/Counter High-Resolution Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register */ -+} HIRES_t; -+ -+/* High Resolution Enable */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ -+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+} IRDA_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t reserved_0x00; -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+} NVM_FUSES_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* Timer Oscillator pin location */ -+typedef enum TOSCSEL_enum -+{ -+ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ -+ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -+} TOSCSEL_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -+} BOD_t; -+ -+/* BOD operation */ -+typedef enum BODACT_enum -+{ -+ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BODACT_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WDP_enum -+{ -+ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ -+ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ -+ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ -+ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ -+ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ -+ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ -+ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ -+ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ -+ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ -+ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ -+ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -+} WDP_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LOCKBIT - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ -+ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t USBCAL0; /* USB Calibration Byte 0 */ -+ register8_t USBCAL1; /* USB Calibration Byte 1 */ -+ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ -+ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+} NVM_PROD_SIGNATURES_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -+#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -+#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -+#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -+#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -+#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -+#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -+#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -+#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ -+#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -+#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -+#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -+#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* DFLL - DFLL */ -+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -+#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -+#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPD _SFR_MEM8(0x0074) -+#define PR_PRPE _SFR_MEM8(0x0075) -+#define PR_PRPF _SFR_MEM8(0x0076) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_ANAINIT _SFR_MEM8(0x0097) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_AWEXLOCK _SFR_MEM8(0x0099) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) -+#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCA_CTRLA _SFR_MEM8(0x0200) -+#define ADCA_CTRLB _SFR_MEM8(0x0201) -+#define ADCA_REFCTRL _SFR_MEM8(0x0202) -+#define ADCA_EVCTRL _SFR_MEM8(0x0203) -+#define ADCA_PRESCALER _SFR_MEM8(0x0204) -+#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -+#define ADCA_TEMP _SFR_MEM8(0x0207) -+#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) -+#define ADCA_CAL _SFR_MEM16(0x020C) -+#define ADCA_CH0RES _SFR_MEM16(0x0210) -+#define ADCA_CMP _SFR_MEM16(0x0218) -+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -+#define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -+ -+/* AC - Analog Comparator */ -+#define ACA_AC0CTRL _SFR_MEM8(0x0380) -+#define ACA_AC1CTRL _SFR_MEM8(0x0381) -+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -+#define ACA_CTRLA _SFR_MEM8(0x0384) -+#define ACA_CTRLB _SFR_MEM8(0x0385) -+#define ACA_WINCTRL _SFR_MEM8(0x0386) -+#define ACA_STATUS _SFR_MEM8(0x0387) -+ -+/* RTC - Real-Time Counter */ -+#define RTC_CTRL _SFR_MEM8(0x0400) -+#define RTC_STATUS _SFR_MEM8(0x0401) -+#define RTC_INTCTRL _SFR_MEM8(0x0402) -+#define RTC_INTFLAGS _SFR_MEM8(0x0403) -+#define RTC_TEMP _SFR_MEM8(0x0404) -+#define RTC_CNT _SFR_MEM16(0x0408) -+#define RTC_PER _SFR_MEM16(0x040A) -+#define RTC_COMP _SFR_MEM16(0x040C) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIE_CTRL _SFR_MEM8(0x04A0) -+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -+ -+/* PORT - I/O Ports */ -+#define PORTA_DIR _SFR_MEM8(0x0600) -+#define PORTA_DIRSET _SFR_MEM8(0x0601) -+#define PORTA_DIRCLR _SFR_MEM8(0x0602) -+#define PORTA_DIRTGL _SFR_MEM8(0x0603) -+#define PORTA_OUT _SFR_MEM8(0x0604) -+#define PORTA_OUTSET _SFR_MEM8(0x0605) -+#define PORTA_OUTCLR _SFR_MEM8(0x0606) -+#define PORTA_OUTTGL _SFR_MEM8(0x0607) -+#define PORTA_IN _SFR_MEM8(0x0608) -+#define PORTA_INTCTRL _SFR_MEM8(0x0609) -+#define PORTA_INT0MASK _SFR_MEM8(0x060A) -+#define PORTA_INT1MASK _SFR_MEM8(0x060B) -+#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_REMAP _SFR_MEM8(0x060E) -+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -+ -+/* PORT - I/O Ports */ -+#define PORTB_DIR _SFR_MEM8(0x0620) -+#define PORTB_DIRSET _SFR_MEM8(0x0621) -+#define PORTB_DIRCLR _SFR_MEM8(0x0622) -+#define PORTB_DIRTGL _SFR_MEM8(0x0623) -+#define PORTB_OUT _SFR_MEM8(0x0624) -+#define PORTB_OUTSET _SFR_MEM8(0x0625) -+#define PORTB_OUTCLR _SFR_MEM8(0x0626) -+#define PORTB_OUTTGL _SFR_MEM8(0x0627) -+#define PORTB_IN _SFR_MEM8(0x0628) -+#define PORTB_INTCTRL _SFR_MEM8(0x0629) -+#define PORTB_INT0MASK _SFR_MEM8(0x062A) -+#define PORTB_INT1MASK _SFR_MEM8(0x062B) -+#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -+#define PORTB_REMAP _SFR_MEM8(0x062E) -+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INT0MASK _SFR_MEM8(0x064A) -+#define PORTC_INT1MASK _SFR_MEM8(0x064B) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INT0MASK _SFR_MEM8(0x066A) -+#define PORTD_INT1MASK _SFR_MEM8(0x066B) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTE_DIR _SFR_MEM8(0x0680) -+#define PORTE_DIRSET _SFR_MEM8(0x0681) -+#define PORTE_DIRCLR _SFR_MEM8(0x0682) -+#define PORTE_DIRTGL _SFR_MEM8(0x0683) -+#define PORTE_OUT _SFR_MEM8(0x0684) -+#define PORTE_OUTSET _SFR_MEM8(0x0685) -+#define PORTE_OUTCLR _SFR_MEM8(0x0686) -+#define PORTE_OUTTGL _SFR_MEM8(0x0687) -+#define PORTE_IN _SFR_MEM8(0x0688) -+#define PORTE_INTCTRL _SFR_MEM8(0x0689) -+#define PORTE_INT0MASK _SFR_MEM8(0x068A) -+#define PORTE_INT1MASK _SFR_MEM8(0x068B) -+#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -+#define PORTE_REMAP _SFR_MEM8(0x068E) -+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) -+ -+/* PORT - I/O Ports */ -+#define PORTF_DIR _SFR_MEM8(0x06A0) -+#define PORTF_DIRSET _SFR_MEM8(0x06A1) -+#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -+#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -+#define PORTF_OUT _SFR_MEM8(0x06A4) -+#define PORTF_OUTSET _SFR_MEM8(0x06A5) -+#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -+#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -+#define PORTF_IN _SFR_MEM8(0x06A8) -+#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -+#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -+#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -+#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -+#define PORTF_REMAP _SFR_MEM8(0x06AE) -+#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -+#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -+#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -+#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -+#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -+#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -+#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -+#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -+#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCC0_CTRLA _SFR_MEM8(0x0800) -+#define TCC0_CTRLB _SFR_MEM8(0x0801) -+#define TCC0_CTRLC _SFR_MEM8(0x0802) -+#define TCC0_CTRLD _SFR_MEM8(0x0803) -+#define TCC0_CTRLE _SFR_MEM8(0x0804) -+#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -+#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -+#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -+#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC0_TEMP _SFR_MEM8(0x080F) -+#define TCC0_CNT _SFR_MEM16(0x0820) -+#define TCC0_PER _SFR_MEM16(0x0826) -+#define TCC0_CCA _SFR_MEM16(0x0828) -+#define TCC0_CCB _SFR_MEM16(0x082A) -+#define TCC0_CCC _SFR_MEM16(0x082C) -+#define TCC0_CCD _SFR_MEM16(0x082E) -+#define TCC0_PERBUF _SFR_MEM16(0x0836) -+#define TCC0_CCABUF _SFR_MEM16(0x0838) -+#define TCC0_CCBBUF _SFR_MEM16(0x083A) -+#define TCC0_CCCBUF _SFR_MEM16(0x083C) -+#define TCC0_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCC2_CTRLA _SFR_MEM8(0x0800) -+#define TCC2_CTRLB _SFR_MEM8(0x0801) -+#define TCC2_CTRLC _SFR_MEM8(0x0802) -+#define TCC2_CTRLE _SFR_MEM8(0x0804) -+#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC2_CTRLF _SFR_MEM8(0x0809) -+#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC2_LCNT _SFR_MEM8(0x0820) -+#define TCC2_HCNT _SFR_MEM8(0x0821) -+#define TCC2_LPER _SFR_MEM8(0x0826) -+#define TCC2_HPER _SFR_MEM8(0x0827) -+#define TCC2_LCMPA _SFR_MEM8(0x0828) -+#define TCC2_HCMPA _SFR_MEM8(0x0829) -+#define TCC2_LCMPB _SFR_MEM8(0x082A) -+#define TCC2_HCMPB _SFR_MEM8(0x082B) -+#define TCC2_LCMPC _SFR_MEM8(0x082C) -+#define TCC2_HCMPC _SFR_MEM8(0x082D) -+#define TCC2_LCMPD _SFR_MEM8(0x082E) -+#define TCC2_HCMPD _SFR_MEM8(0x082F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCC1_CTRLA _SFR_MEM8(0x0840) -+#define TCC1_CTRLB _SFR_MEM8(0x0841) -+#define TCC1_CTRLC _SFR_MEM8(0x0842) -+#define TCC1_CTRLD _SFR_MEM8(0x0843) -+#define TCC1_CTRLE _SFR_MEM8(0x0844) -+#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -+#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -+#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -+#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC1_TEMP _SFR_MEM8(0x084F) -+#define TCC1_CNT _SFR_MEM16(0x0860) -+#define TCC1_PER _SFR_MEM16(0x0866) -+#define TCC1_CCA _SFR_MEM16(0x0868) -+#define TCC1_CCB _SFR_MEM16(0x086A) -+#define TCC1_PERBUF _SFR_MEM16(0x0876) -+#define TCC1_CCABUF _SFR_MEM16(0x0878) -+#define TCC1_CCBBUF _SFR_MEM16(0x087A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXC_CTRL _SFR_MEM8(0x0880) -+#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -+#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -+#define AWEXC_STATUS _SFR_MEM8(0x0884) -+#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -+#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -+#define AWEXC_DTLS _SFR_MEM8(0x0888) -+#define AWEXC_DTHS _SFR_MEM8(0x0889) -+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x0890) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08A0) -+#define USARTC0_STATUS _SFR_MEM8(0x08A1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -+#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -+#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIC_CTRL _SFR_MEM8(0x08C0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -+#define SPIC_STATUS _SFR_MEM8(0x08C2) -+#define SPIC_DATA _SFR_MEM8(0x08C3) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCD0_CTRLA _SFR_MEM8(0x0900) -+#define TCD0_CTRLB _SFR_MEM8(0x0901) -+#define TCD0_CTRLC _SFR_MEM8(0x0902) -+#define TCD0_CTRLD _SFR_MEM8(0x0903) -+#define TCD0_CTRLE _SFR_MEM8(0x0904) -+#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -+#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -+#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -+#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -+#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD0_TEMP _SFR_MEM8(0x090F) -+#define TCD0_CNT _SFR_MEM16(0x0920) -+#define TCD0_PER _SFR_MEM16(0x0926) -+#define TCD0_CCA _SFR_MEM16(0x0928) -+#define TCD0_CCB _SFR_MEM16(0x092A) -+#define TCD0_CCC _SFR_MEM16(0x092C) -+#define TCD0_CCD _SFR_MEM16(0x092E) -+#define TCD0_PERBUF _SFR_MEM16(0x0936) -+#define TCD0_CCABUF _SFR_MEM16(0x0938) -+#define TCD0_CCBBUF _SFR_MEM16(0x093A) -+#define TCD0_CCCBUF _SFR_MEM16(0x093C) -+#define TCD0_CCDBUF _SFR_MEM16(0x093E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCD2_CTRLA _SFR_MEM8(0x0900) -+#define TCD2_CTRLB _SFR_MEM8(0x0901) -+#define TCD2_CTRLC _SFR_MEM8(0x0902) -+#define TCD2_CTRLE _SFR_MEM8(0x0904) -+#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD2_CTRLF _SFR_MEM8(0x0909) -+#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD2_LCNT _SFR_MEM8(0x0920) -+#define TCD2_HCNT _SFR_MEM8(0x0921) -+#define TCD2_LPER _SFR_MEM8(0x0926) -+#define TCD2_HPER _SFR_MEM8(0x0927) -+#define TCD2_LCMPA _SFR_MEM8(0x0928) -+#define TCD2_HCMPA _SFR_MEM8(0x0929) -+#define TCD2_LCMPB _SFR_MEM8(0x092A) -+#define TCD2_HCMPB _SFR_MEM8(0x092B) -+#define TCD2_LCMPC _SFR_MEM8(0x092C) -+#define TCD2_HCMPC _SFR_MEM8(0x092D) -+#define TCD2_LCMPD _SFR_MEM8(0x092E) -+#define TCD2_HCMPD _SFR_MEM8(0x092F) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD0_DATA _SFR_MEM8(0x09A0) -+#define USARTD0_STATUS _SFR_MEM8(0x09A1) -+#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -+#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -+#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPID_CTRL _SFR_MEM8(0x09C0) -+#define SPID_INTCTRL _SFR_MEM8(0x09C1) -+#define SPID_STATUS _SFR_MEM8(0x09C2) -+#define SPID_DATA _SFR_MEM8(0x09C3) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCE0_CTRLA _SFR_MEM8(0x0A00) -+#define TCE0_CTRLB _SFR_MEM8(0x0A01) -+#define TCE0_CTRLC _SFR_MEM8(0x0A02) -+#define TCE0_CTRLD _SFR_MEM8(0x0A03) -+#define TCE0_CTRLE _SFR_MEM8(0x0A04) -+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE0_TEMP _SFR_MEM8(0x0A0F) -+#define TCE0_CNT _SFR_MEM16(0x0A20) -+#define TCE0_PER _SFR_MEM16(0x0A26) -+#define TCE0_CCA _SFR_MEM16(0x0A28) -+#define TCE0_CCB _SFR_MEM16(0x0A2A) -+#define TCE0_CCC _SFR_MEM16(0x0A2C) -+#define TCE0_CCD _SFR_MEM16(0x0A2E) -+#define TCE0_PERBUF _SFR_MEM16(0x0A36) -+#define TCE0_CCABUF _SFR_MEM16(0x0A38) -+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCE2_CTRLA _SFR_MEM8(0x0A00) -+#define TCE2_CTRLB _SFR_MEM8(0x0A01) -+#define TCE2_CTRLC _SFR_MEM8(0x0A02) -+#define TCE2_CTRLE _SFR_MEM8(0x0A04) -+#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE2_CTRLF _SFR_MEM8(0x0A09) -+#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE2_LCNT _SFR_MEM8(0x0A20) -+#define TCE2_HCNT _SFR_MEM8(0x0A21) -+#define TCE2_LPER _SFR_MEM8(0x0A26) -+#define TCE2_HPER _SFR_MEM8(0x0A27) -+#define TCE2_LCMPA _SFR_MEM8(0x0A28) -+#define TCE2_HCMPA _SFR_MEM8(0x0A29) -+#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -+#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -+#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -+#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -+#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -+#define TCE2_HCMPD _SFR_MEM8(0x0A2F) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE0_DATA _SFR_MEM8(0x0AA0) -+#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -+#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -+#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -+#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -+#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -+#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCF0_CTRLA _SFR_MEM8(0x0B00) -+#define TCF0_CTRLB _SFR_MEM8(0x0B01) -+#define TCF0_CTRLC _SFR_MEM8(0x0B02) -+#define TCF0_CTRLD _SFR_MEM8(0x0B03) -+#define TCF0_CTRLE _SFR_MEM8(0x0B04) -+#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -+#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -+#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -+#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -+#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -+#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -+#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -+#define TCF0_TEMP _SFR_MEM8(0x0B0F) -+#define TCF0_CNT _SFR_MEM16(0x0B20) -+#define TCF0_PER _SFR_MEM16(0x0B26) -+#define TCF0_CCA _SFR_MEM16(0x0B28) -+#define TCF0_CCB _SFR_MEM16(0x0B2A) -+#define TCF0_CCC _SFR_MEM16(0x0B2C) -+#define TCF0_CCD _SFR_MEM16(0x0B2E) -+#define TCF0_PERBUF _SFR_MEM16(0x0B36) -+#define TCF0_CCABUF _SFR_MEM16(0x0B38) -+#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -+#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -+#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCF2_CTRLA _SFR_MEM8(0x0B00) -+#define TCF2_CTRLB _SFR_MEM8(0x0B01) -+#define TCF2_CTRLC _SFR_MEM8(0x0B02) -+#define TCF2_CTRLE _SFR_MEM8(0x0B04) -+#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -+#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -+#define TCF2_CTRLF _SFR_MEM8(0x0B09) -+#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -+#define TCF2_LCNT _SFR_MEM8(0x0B20) -+#define TCF2_HCNT _SFR_MEM8(0x0B21) -+#define TCF2_LPER _SFR_MEM8(0x0B26) -+#define TCF2_HPER _SFR_MEM8(0x0B27) -+#define TCF2_LCMPA _SFR_MEM8(0x0B28) -+#define TCF2_HCMPA _SFR_MEM8(0x0B29) -+#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -+#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -+#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -+#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -+#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -+#define TCF2_HCMPD _SFR_MEM8(0x0B2F) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTF0_DATA _SFR_MEM8(0x0BA0) -+#define USARTF0_STATUS _SFR_MEM8(0x0BA1) -+#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) -+#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) -+#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) -+#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) -+#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* VPORT - Virtual Ports */ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ -+#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ -+ -+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -+ -+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ -+ -+/* PR.PRPD bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPE bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPF bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -+#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -+#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ -+ -+#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ -+ -+#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -+#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.ANAINIT bit masks and bit positions */ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.AWEXLOCK bit masks and bit positions */ -+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* PORTCFG - Port Configuration */ -+/* PORTCFG.VPCTRLA bit masks and bit positions */ -+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ -+ -+/* PORTCFG.VPCTRLB bit masks and bit positions */ -+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ -+ -+/* PORTCFG.CLKEVOUT bit masks and bit positions */ -+#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ -+ -+#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -+#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -+#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -+#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -+#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -+#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ -+ -+#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -+#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ -+ -+#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -+#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ -+ -+/* PORTCFG.EBIOUT bit masks and bit positions */ -+#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ -+#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ -+#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ -+#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ -+#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ -+#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ -+ -+#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ -+#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ -+#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ -+#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ -+#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ -+#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ -+ -+/* PORTCFG.EVOUTSEL bit masks and bit positions */ -+#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -+#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -+#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -+#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -+#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -+#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -+#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -+#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0x7F /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ -+ -+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ -+ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -+#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -+#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -+#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -+#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -+#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -+#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -+#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -+#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -+#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ -+ -+#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */ -+#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */ -+#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -+#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */ -+#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -+#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */ -+#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -+#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */ -+#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -+#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -+#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* ADC.SAMPCTRL bit masks and bit positions */ -+#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ -+#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ -+#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ -+#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ -+#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ -+#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ -+#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ -+#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ -+#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ -+#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ -+#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ -+#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ -+#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ -+#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* RTC - Real-Time Counter */ -+/* RTC.CTRL bit masks and bit positions */ -+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ -+ -+/* RTC.STATUS bit masks and bit positions */ -+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC.INTCTRL bit masks and bit positions */ -+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC.INTFLAGS bit masks and bit positions */ -+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* PORT - I/O Port Configuration */ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ -+ -+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -+#define PORT_SPI_bp 5 /* SPI bit position. */ -+ -+#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -+#define PORT_USART0_bp 4 /* USART0 bit position. */ -+ -+#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -+#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ -+ -+#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -+#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ -+ -+#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -+#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ -+ -+#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -+#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ -+ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC0.CTRLA bit masks and bit positions */ -+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC0.CTRLB bit masks and bit positions */ -+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ -+ -+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ -+ -+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC0.CTRLC bit masks and bit positions */ -+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ -+ -+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ -+ -+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC0.CTRLD bit masks and bit positions */ -+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC0_EVACT_gp 5 /* Event Action group position. */ -+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC0.CTRLE bit masks and bit positions */ -+#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC0.INTCTRLA bit masks and bit positions */ -+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC0.INTCTRLB bit masks and bit positions */ -+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ -+ -+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ -+ -+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC0.CTRLFCLR bit masks and bit positions */ -+#define TC0_CMD_gm 0x0C /* Command group mask. */ -+#define TC0_CMD_gp 2 /* Command group position. */ -+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC0_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC0_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC0_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC0.CTRLFSET bit masks and bit positions */ -+/* TC0_CMD Predefined. */ -+/* TC0_CMD Predefined. */ -+ -+/* TC0_LUPD Predefined. */ -+/* TC0_LUPD Predefined. */ -+ -+/* TC0_DIR Predefined. */ -+/* TC0_DIR Predefined. */ -+ -+/* TC0.CTRLGCLR bit masks and bit positions */ -+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ -+ -+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ -+ -+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC0.CTRLGSET bit masks and bit positions */ -+/* TC0_CCDBV Predefined. */ -+/* TC0_CCDBV Predefined. */ -+ -+/* TC0_CCCBV Predefined. */ -+/* TC0_CCCBV Predefined. */ -+ -+/* TC0_CCBBV Predefined. */ -+/* TC0_CCBBV Predefined. */ -+ -+/* TC0_CCABV Predefined. */ -+/* TC0_CCABV Predefined. */ -+ -+/* TC0_PERBV Predefined. */ -+/* TC0_PERBV Predefined. */ -+ -+/* TC0.INTFLAGS bit masks and bit positions */ -+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ -+ -+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ -+ -+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC1.CTRLA bit masks and bit positions */ -+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC1.CTRLB bit masks and bit positions */ -+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC1.CTRLC bit masks and bit positions */ -+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC1.CTRLD bit masks and bit positions */ -+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC1_EVACT_gp 5 /* Event Action group position. */ -+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC1.CTRLE bit masks and bit positions */ -+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ -+ -+/* TC1.INTCTRLA bit masks and bit positions */ -+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC1.INTCTRLB bit masks and bit positions */ -+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC1.CTRLFCLR bit masks and bit positions */ -+#define TC1_CMD_gm 0x0C /* Command group mask. */ -+#define TC1_CMD_gp 2 /* Command group position. */ -+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC1_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC1_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC1_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC1.CTRLFSET bit masks and bit positions */ -+/* TC1_CMD Predefined. */ -+/* TC1_CMD Predefined. */ -+ -+/* TC1_LUPD Predefined. */ -+/* TC1_LUPD Predefined. */ -+ -+/* TC1_DIR Predefined. */ -+/* TC1_DIR Predefined. */ -+ -+/* TC1.CTRLGCLR bit masks and bit positions */ -+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC1.CTRLGSET bit masks and bit positions */ -+/* TC1_CCBBV Predefined. */ -+/* TC1_CCBBV Predefined. */ -+ -+/* TC1_CCABV Predefined. */ -+/* TC1_CCABV Predefined. */ -+ -+/* TC1_PERBV Predefined. */ -+/* TC1_PERBV Predefined. */ -+ -+/* TC1.INTFLAGS bit masks and bit positions */ -+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+/* TC2.CTRLA bit masks and bit positions */ -+#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC2.CTRLB bit masks and bit positions */ -+#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -+#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ -+ -+#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -+#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ -+ -+#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -+#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ -+ -+#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -+#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ -+ -+#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -+#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ -+ -+#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -+#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ -+ -+#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -+#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ -+ -+#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -+#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ -+ -+/* TC2.CTRLC bit masks and bit positions */ -+#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -+#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ -+ -+#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -+#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ -+ -+#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -+#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ -+ -+#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -+#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ -+ -+#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -+#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ -+ -+#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -+#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ -+ -+#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -+#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ -+ -+#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -+#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ -+ -+/* TC2.CTRLE bit masks and bit positions */ -+#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC2.INTCTRLA bit masks and bit positions */ -+#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -+#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -+#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -+#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -+#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -+#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ -+ -+#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -+#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -+#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -+#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -+#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -+#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ -+ -+/* TC2.INTCTRLB bit masks and bit positions */ -+#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -+#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -+#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -+#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -+#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -+#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -+#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -+#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -+#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -+#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -+#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -+#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -+#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -+#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -+#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -+#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -+#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -+#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -+#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -+#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -+#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ -+ -+/* TC2.CTRLF bit masks and bit positions */ -+#define TC2_CMD_gm 0x0C /* Command group mask. */ -+#define TC2_CMD_gp 2 /* Command group position. */ -+#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC2_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -+#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -+#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -+#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -+#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -+#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ -+ -+/* TC2.INTFLAGS bit masks and bit positions */ -+#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -+#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ -+ -+#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -+#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ -+ -+#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -+#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ -+ -+#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -+#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ -+ -+#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ -+ -+#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ -+ -+/* AWEX - Timer/Counter Advanced Waveform Extension */ -+/* AWEX.CTRL bit masks and bit positions */ -+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ -+ -+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ -+ -+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ -+ -+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ -+ -+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ -+ -+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ -+ -+/* AWEX.FDCTRL bit masks and bit positions */ -+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ -+ -+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ -+ -+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ -+ -+/* AWEX.STATUS bit masks and bit positions */ -+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ -+ -+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ -+ -+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ -+ -+/* AWEX.STATUSSET bit masks and bit positions */ -+/* AWEX_FDF Predefined. */ -+/* AWEX_FDF Predefined. */ -+ -+/* AWEX_DTHSBUFV Predefined. */ -+/* AWEX_DTHSBUFV Predefined. */ -+ -+/* AWEX_DTLSBUFV Predefined. */ -+/* AWEX_DTLSBUFV Predefined. */ -+ -+/* HIRES - Timer/Counter High-Resolution Extension */ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -+#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* LOCKBIT - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT0_vect_num 2 -+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -+#define PORTC_INT1_vect_num 3 -+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT0_vect_num 4 -+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -+#define PORTR_INT1_vect_num 5 -+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ -+ -+/* RTC interrupt vectors */ -+#define RTC_OVF_vect_num 10 -+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -+#define RTC_COMP_vect_num 11 -+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 12 -+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 13 -+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_OVF_vect_num 14 -+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LUNF_vect_num 14 -+#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_ERR_vect_num 15 -+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_HUNF_vect_num 15 -+#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCA_vect_num 16 -+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPA_vect_num 16 -+#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCB_vect_num 17 -+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPB_vect_num 17 -+#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCC_vect_num 18 -+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPC_vect_num 18 -+#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCD_vect_num 19 -+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPD_vect_num 19 -+#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ -+ -+/* TCC1 interrupt vectors */ -+#define TCC1_OVF_vect_num 20 -+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -+#define TCC1_ERR_vect_num 21 -+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -+#define TCC1_CCA_vect_num 22 -+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -+#define TCC1_CCB_vect_num 23 -+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 24 -+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 25 -+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 26 -+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 27 -+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 32 -+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -+#define NVM_SPM_vect_num 33 -+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ -+ -+/* PORTB interrupt vectors */ -+#define PORTB_INT0_vect_num 34 -+#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -+#define PORTB_INT1_vect_num 35 -+#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ -+ -+/* PORTE interrupt vectors */ -+#define PORTE_INT0_vect_num 43 -+#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -+#define PORTE_INT1_vect_num 44 -+#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ -+ -+/* TWIE interrupt vectors */ -+#define TWIE_TWIS_vect_num 45 -+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -+#define TWIE_TWIM_vect_num 46 -+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_OVF_vect_num 47 -+#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LUNF_vect_num 47 -+#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_ERR_vect_num 48 -+#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_HUNF_vect_num 48 -+#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCA_vect_num 49 -+#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPA_vect_num 49 -+#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCB_vect_num 50 -+#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPB_vect_num 50 -+#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCC_vect_num 51 -+#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPC_vect_num 51 -+#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCD_vect_num 52 -+#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPD_vect_num 52 -+#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ -+ -+/* USARTE0 interrupt vectors */ -+#define USARTE0_RXC_vect_num 58 -+#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -+#define USARTE0_DRE_vect_num 59 -+#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -+#define USARTE0_TXC_vect_num 60 -+#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT0_vect_num 64 -+#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -+#define PORTD_INT1_vect_num 65 -+#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ -+ -+/* PORTA interrupt vectors */ -+#define PORTA_INT0_vect_num 66 -+#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -+#define PORTA_INT1_vect_num 67 -+#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ -+ -+/* ACA interrupt vectors */ -+#define ACA_AC0_vect_num 68 -+#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -+#define ACA_AC1_vect_num 69 -+#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -+#define ACA_ACW_vect_num 70 -+#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ -+ -+/* ADCA interrupt vectors */ -+#define ADCA_CH0_vect_num 71 -+#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_OVF_vect_num 77 -+#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LUNF_vect_num 77 -+#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_ERR_vect_num 78 -+#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_HUNF_vect_num 78 -+#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCA_vect_num 79 -+#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPA_vect_num 79 -+#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCB_vect_num 80 -+#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPB_vect_num 80 -+#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCC_vect_num 81 -+#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPC_vect_num 81 -+#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCD_vect_num 82 -+#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPD_vect_num 82 -+#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ -+ -+/* SPID interrupt vectors */ -+#define SPID_INT_vect_num 87 -+#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ -+ -+/* USARTD0 interrupt vectors */ -+#define USARTD0_RXC_vect_num 88 -+#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -+#define USARTD0_DRE_vect_num 89 -+#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -+#define USARTD0_TXC_vect_num 90 -+#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ -+ -+/* PORTF interrupt vectors */ -+#define PORTF_INT0_vect_num 104 -+#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -+#define PORTF_INT1_vect_num 105 -+#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_OVF_vect_num 108 -+#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LUNF_vect_num 108 -+#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_ERR_vect_num 109 -+#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_HUNF_vect_num 109 -+#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCA_vect_num 110 -+#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPA_vect_num 110 -+#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCB_vect_num 111 -+#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPB_vect_num 111 -+#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCC_vect_num 112 -+#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPC_vect_num 112 -+#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCD_vect_num 113 -+#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPD_vect_num 113 -+#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (114 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (401408) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (393216) -+#define APP_SECTION_PAGE_SIZE (512) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0x5E000) -+#define APPTABLE_SECTION_SIZE (8192) -+#define APPTABLE_SECTION_PAGE_SIZE (512) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x60000) -+#define BOOT_SECTION_SIZE (8192) -+#define BOOT_SECTION_PAGE_SIZE (512) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (40960) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (4096) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (32768) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (4096) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (6) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (512) -+#define USER_SIGNATURES_PAGE_SIZE (512) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (64) -+#define PROD_SIGNATURES_PAGE_SIZE (512) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 512 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 6 -+ -+/* Fuse Byte 0 Reserved */ -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x98 -+#define SIGNATURE_2 0x47 -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA384D3_H_INCLUDED */ -+ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox384d3.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA384D3_H_INCLUDED ++#define _AVR_ATXMEGA384D3_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t reserved_0x04; ++} CLK_t; ++ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t reserved_0x02; ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from 32.768 kHz internal oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from 32.768 kHz internal oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 2 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC2MCREF_enum ++{ ++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC2MCREF_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++ register8_t EBIOUT; /* EBI Output register */ ++ register8_t EVOUTSEL; /* Event Output Select */ ++} PORTCFG_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP02MAP_enum ++{ ++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP02MAP_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP13MAP_enum ++{ ++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP13MAP_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Clock and Event Output Port */ ++typedef enum PORTCFG_CLKEVPIN_enum ++{ ++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ ++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ ++} PORTCFG_CLKEVPIN_t; ++ ++/* EBI Address Output Port */ ++typedef enum PORTCFG_EBIADROUT_enum ++{ ++ PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ ++ PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ ++ PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ ++ PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ ++} PORTCFG_EBIADROUT_t; ++ ++/* EBI Chip Select Output Port */ ++typedef enum PORTCFG_EBICSOUT_enum ++{ ++ PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ ++} PORTCFG_EBICSOUT_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ ++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ ++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ ++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ ++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t reserved_0x07; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++} ADC_t; ++ ++/* Current Limitation */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ ++} ADC_CURRLIMIT_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ ++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ ++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ ++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* SDA Hold Time */ ++typedef enum TWI_SDAHOLD_enum ++{ ++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ ++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ ++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ ++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ ++} TWI_SDAHOLD_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - I/O Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* I/O Port Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Byte Mode */ ++typedef enum TC_BYTEM_enum ++{ ++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ ++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ ++} TC_BYTEM_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC2 - 16-bit Timer/Counter type 2 ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter type 2 */ ++typedef struct TC2_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t reserved_0x03; ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t reserved_0x08; ++ register8_t CTRLF; /* Control Register F */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t LCNT; /* Low Byte Count */ ++ register8_t HCNT; /* High Byte Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t LPER; /* Low Byte Period */ ++ register8_t HPER; /* High Byte Period */ ++ register8_t LCMPA; /* Low Byte Compare A */ ++ register8_t HCMPA; /* High Byte Compare A */ ++ register8_t LCMPB; /* Low Byte Compare B */ ++ register8_t HCMPB; /* High Byte Compare B */ ++ register8_t LCMPC; /* Low Byte Compare C */ ++ register8_t HCMPC; /* High Byte Compare C */ ++ register8_t LCMPD; /* Low Byte Compare D */ ++ register8_t HCMPD; /* High Byte Compare D */ ++} TC2_t; ++ ++/* Clock Selection */ ++typedef enum TC2_CLKSEL_enum ++{ ++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC2_CLKSEL_t; ++ ++/* Byte Mode */ ++typedef enum TC2_BYTEM_enum ++{ ++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ ++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ ++} TC2_BYTEM_t; ++ ++/* High Byte Underflow Interrupt Level */ ++typedef enum TC2_HUNFINTLVL_enum ++{ ++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_HUNFINTLVL_t; ++ ++/* Low Byte Underflow Interrupt Level */ ++typedef enum TC2_LUNFINTLVL_enum ++{ ++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LUNFINTLVL_t; ++ ++/* Low Byte Compare D Interrupt Level */ ++typedef enum TC2_LCMPDINTLVL_enum ++{ ++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC2_LCMPDINTLVL_t; ++ ++/* Low Byte Compare C Interrupt Level */ ++typedef enum TC2_LCMPCINTLVL_enum ++{ ++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC2_LCMPCINTLVL_t; ++ ++/* Low Byte Compare B Interrupt Level */ ++typedef enum TC2_LCMPBINTLVL_enum ++{ ++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_LCMPBINTLVL_t; ++ ++/* Low Byte Compare A Interrupt Level */ ++typedef enum TC2_LCMPAINTLVL_enum ++{ ++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LCMPAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMD_enum ++{ ++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC2_CMD_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMDEN_enum ++{ ++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ ++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ ++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ ++} TC2_CMDEN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AWEX - Timer/Counter Advanced Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - Timer/Counter High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t reserved_0x00; ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* Timer Oscillator pin location */ ++typedef enum TOSCSEL_enum ++{ ++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ ++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ ++} TOSCSEL_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* BOD operation */ ++typedef enum BODACT_enum ++{ ++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BODACT_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WDP_enum ++{ ++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ ++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ ++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ ++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ ++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ ++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ ++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ ++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ ++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ ++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ ++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ ++} WDP_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LOCKBIT - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ ++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t USBCAL0; /* USB Calibration Byte 0 */ ++ register8_t USBCAL1; /* USB Calibration Byte 1 */ ++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ ++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ ++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ ++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ ++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ ++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ ++#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ ++#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) ++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) ++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) ++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLL - DFLL */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) ++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_REMAP _SFR_MEM8(0x060E) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_REMAP _SFR_MEM8(0x062E) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_REMAP _SFR_MEM8(0x068E) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORT - I/O Ports */ ++#define PORTF_DIR _SFR_MEM8(0x06A0) ++#define PORTF_DIRSET _SFR_MEM8(0x06A1) ++#define PORTF_DIRCLR _SFR_MEM8(0x06A2) ++#define PORTF_DIRTGL _SFR_MEM8(0x06A3) ++#define PORTF_OUT _SFR_MEM8(0x06A4) ++#define PORTF_OUTSET _SFR_MEM8(0x06A5) ++#define PORTF_OUTCLR _SFR_MEM8(0x06A6) ++#define PORTF_OUTTGL _SFR_MEM8(0x06A7) ++#define PORTF_IN _SFR_MEM8(0x06A8) ++#define PORTF_INTCTRL _SFR_MEM8(0x06A9) ++#define PORTF_INT0MASK _SFR_MEM8(0x06AA) ++#define PORTF_INT1MASK _SFR_MEM8(0x06AB) ++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) ++#define PORTF_REMAP _SFR_MEM8(0x06AE) ++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) ++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) ++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) ++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) ++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) ++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) ++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) ++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCC2_CTRLA _SFR_MEM8(0x0800) ++#define TCC2_CTRLB _SFR_MEM8(0x0801) ++#define TCC2_CTRLC _SFR_MEM8(0x0802) ++#define TCC2_CTRLE _SFR_MEM8(0x0804) ++#define TCC2_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC2_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC2_CTRLF _SFR_MEM8(0x0809) ++#define TCC2_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC2_LCNT _SFR_MEM8(0x0820) ++#define TCC2_HCNT _SFR_MEM8(0x0821) ++#define TCC2_LPER _SFR_MEM8(0x0826) ++#define TCC2_HPER _SFR_MEM8(0x0827) ++#define TCC2_LCMPA _SFR_MEM8(0x0828) ++#define TCC2_HCMPA _SFR_MEM8(0x0829) ++#define TCC2_LCMPB _SFR_MEM8(0x082A) ++#define TCC2_HCMPB _SFR_MEM8(0x082B) ++#define TCC2_LCMPC _SFR_MEM8(0x082C) ++#define TCC2_HCMPC _SFR_MEM8(0x082D) ++#define TCC2_LCMPD _SFR_MEM8(0x082E) ++#define TCC2_HCMPD _SFR_MEM8(0x082F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_STATUSSET _SFR_MEM8(0x0885) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCD2_CTRLA _SFR_MEM8(0x0900) ++#define TCD2_CTRLB _SFR_MEM8(0x0901) ++#define TCD2_CTRLC _SFR_MEM8(0x0902) ++#define TCD2_CTRLE _SFR_MEM8(0x0904) ++#define TCD2_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD2_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD2_CTRLF _SFR_MEM8(0x0909) ++#define TCD2_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD2_LCNT _SFR_MEM8(0x0920) ++#define TCD2_HCNT _SFR_MEM8(0x0921) ++#define TCD2_LPER _SFR_MEM8(0x0926) ++#define TCD2_HPER _SFR_MEM8(0x0927) ++#define TCD2_LCMPA _SFR_MEM8(0x0928) ++#define TCD2_HCMPA _SFR_MEM8(0x0929) ++#define TCD2_LCMPB _SFR_MEM8(0x092A) ++#define TCD2_HCMPB _SFR_MEM8(0x092B) ++#define TCD2_LCMPC _SFR_MEM8(0x092C) ++#define TCD2_HCMPC _SFR_MEM8(0x092D) ++#define TCD2_LCMPD _SFR_MEM8(0x092E) ++#define TCD2_HCMPD _SFR_MEM8(0x092F) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCE2_CTRLA _SFR_MEM8(0x0A00) ++#define TCE2_CTRLB _SFR_MEM8(0x0A01) ++#define TCE2_CTRLC _SFR_MEM8(0x0A02) ++#define TCE2_CTRLE _SFR_MEM8(0x0A04) ++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE2_CTRLF _SFR_MEM8(0x0A09) ++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE2_LCNT _SFR_MEM8(0x0A20) ++#define TCE2_HCNT _SFR_MEM8(0x0A21) ++#define TCE2_LPER _SFR_MEM8(0x0A26) ++#define TCE2_HPER _SFR_MEM8(0x0A27) ++#define TCE2_LCMPA _SFR_MEM8(0x0A28) ++#define TCE2_HCMPA _SFR_MEM8(0x0A29) ++#define TCE2_LCMPB _SFR_MEM8(0x0A2A) ++#define TCE2_HCMPB _SFR_MEM8(0x0A2B) ++#define TCE2_LCMPC _SFR_MEM8(0x0A2C) ++#define TCE2_HCMPC _SFR_MEM8(0x0A2D) ++#define TCE2_LCMPD _SFR_MEM8(0x0A2E) ++#define TCE2_HCMPD _SFR_MEM8(0x0A2F) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCF0_CTRLA _SFR_MEM8(0x0B00) ++#define TCF0_CTRLB _SFR_MEM8(0x0B01) ++#define TCF0_CTRLC _SFR_MEM8(0x0B02) ++#define TCF0_CTRLD _SFR_MEM8(0x0B03) ++#define TCF0_CTRLE _SFR_MEM8(0x0B04) ++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) ++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) ++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) ++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) ++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF0_TEMP _SFR_MEM8(0x0B0F) ++#define TCF0_CNT _SFR_MEM16(0x0B20) ++#define TCF0_PER _SFR_MEM16(0x0B26) ++#define TCF0_CCA _SFR_MEM16(0x0B28) ++#define TCF0_CCB _SFR_MEM16(0x0B2A) ++#define TCF0_CCC _SFR_MEM16(0x0B2C) ++#define TCF0_CCD _SFR_MEM16(0x0B2E) ++#define TCF0_PERBUF _SFR_MEM16(0x0B36) ++#define TCF0_CCABUF _SFR_MEM16(0x0B38) ++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) ++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) ++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCF2_CTRLA _SFR_MEM8(0x0B00) ++#define TCF2_CTRLB _SFR_MEM8(0x0B01) ++#define TCF2_CTRLC _SFR_MEM8(0x0B02) ++#define TCF2_CTRLE _SFR_MEM8(0x0B04) ++#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF2_CTRLF _SFR_MEM8(0x0B09) ++#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF2_LCNT _SFR_MEM8(0x0B20) ++#define TCF2_HCNT _SFR_MEM8(0x0B21) ++#define TCF2_LPER _SFR_MEM8(0x0B26) ++#define TCF2_HPER _SFR_MEM8(0x0B27) ++#define TCF2_LCMPA _SFR_MEM8(0x0B28) ++#define TCF2_HCMPA _SFR_MEM8(0x0B29) ++#define TCF2_LCMPB _SFR_MEM8(0x0B2A) ++#define TCF2_HCMPB _SFR_MEM8(0x0B2B) ++#define TCF2_LCMPC _SFR_MEM8(0x0B2C) ++#define TCF2_HCMPC _SFR_MEM8(0x0B2D) ++#define TCF2_LCMPD _SFR_MEM8(0x0B2E) ++#define TCF2_HCMPD _SFR_MEM8(0x0B2F) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTF0_DATA _SFR_MEM8(0x0BA0) ++#define USARTF0_STATUS _SFR_MEM8(0x0BA1) ++#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) ++#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) ++#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) ++#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) ++#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ ++#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ ++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ ++ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ ++ ++/* PORTCFG.EBIOUT bit masks and bit positions */ ++#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ ++#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ ++#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ ++#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ ++#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ ++#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ ++ ++#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ ++#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ ++#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ ++#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ ++#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ ++#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ ++ ++/* PORTCFG.EVOUTSEL bit masks and bit positions */ ++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ ++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ ++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ ++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ ++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ ++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ ++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ ++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ ++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ ++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ ++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ ++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ ++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ ++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ ++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ ++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ ++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ ++ ++#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */ ++#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */ ++#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ ++#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */ ++#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ ++#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */ ++#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ ++#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */ ++#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ ++#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ ++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* ADC.SAMPCTRL bit masks and bit positions */ ++#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ ++#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ ++#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ ++#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ ++#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ ++#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ ++#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ ++#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ ++#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ ++#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ ++#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ ++#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ ++#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ ++#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* RTC - Real-Time Counter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* PORT - I/O Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_SPI_bm 0x20 /* SPI bit mask. */ ++#define PORT_SPI_bp 5 /* SPI bit position. */ ++ ++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ ++#define PORT_USART0_bp 4 /* USART0 bit position. */ ++ ++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ ++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ ++ ++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ ++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ ++ ++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ ++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ ++ ++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ ++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD Predefined. */ ++/* TC0_CMD Predefined. */ ++ ++/* TC0_LUPD Predefined. */ ++/* TC0_LUPD Predefined. */ ++ ++/* TC0_DIR Predefined. */ ++/* TC0_DIR Predefined. */ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV Predefined. */ ++/* TC0_CCDBV Predefined. */ ++ ++/* TC0_CCCBV Predefined. */ ++/* TC0_CCCBV Predefined. */ ++ ++/* TC0_CCBBV Predefined. */ ++/* TC0_CCBBV Predefined. */ ++ ++/* TC0_CCABV Predefined. */ ++/* TC0_CCABV Predefined. */ ++ ++/* TC0_PERBV Predefined. */ ++/* TC0_PERBV Predefined. */ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD Predefined. */ ++/* TC1_CMD Predefined. */ ++ ++/* TC1_LUPD Predefined. */ ++/* TC1_LUPD Predefined. */ ++ ++/* TC1_DIR Predefined. */ ++/* TC1_DIR Predefined. */ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV Predefined. */ ++/* TC1_CCBBV Predefined. */ ++ ++/* TC1_CCABV Predefined. */ ++/* TC1_CCABV Predefined. */ ++ ++/* TC1_PERBV Predefined. */ ++/* TC1_PERBV Predefined. */ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++/* TC2.CTRLA bit masks and bit positions */ ++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC2.CTRLB bit masks and bit positions */ ++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ ++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ ++ ++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ ++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ ++ ++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ ++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ ++ ++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ ++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ ++ ++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ ++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ ++ ++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ ++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ ++ ++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ ++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ ++ ++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ ++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ ++ ++/* TC2.CTRLC bit masks and bit positions */ ++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ ++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ ++ ++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ ++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ ++ ++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ ++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ ++ ++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ ++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ ++ ++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ ++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ ++ ++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ ++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ ++ ++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ ++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ ++ ++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ ++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ ++ ++/* TC2.CTRLE bit masks and bit positions */ ++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC2.INTCTRLA bit masks and bit positions */ ++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ ++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ ++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ ++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ ++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ ++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ ++ ++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ ++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ ++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ ++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ ++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ ++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ ++ ++/* TC2.INTCTRLB bit masks and bit positions */ ++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ ++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ ++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ ++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ ++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ ++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ ++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ ++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ ++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ ++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ ++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ ++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ ++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ ++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ ++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ ++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ ++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ ++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ ++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ ++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ ++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ ++ ++/* TC2.CTRLF bit masks and bit positions */ ++#define TC2_CMD_gm 0x0C /* Command group mask. */ ++#define TC2_CMD_gp 2 /* Command group position. */ ++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC2_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC2_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ ++#define TC2_CMDEN_gp 0 /* Command Enable group position. */ ++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ ++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ ++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ ++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ ++ ++/* TC2.INTFLAGS bit masks and bit positions */ ++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ ++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ ++ ++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ ++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ ++ ++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ ++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ ++ ++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ ++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ ++ ++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ ++ ++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ ++ ++/* AWEX - Timer/Counter Advanced Waveform Extension */ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++/* AWEX.STATUSSET bit masks and bit positions */ ++/* AWEX_FDF Predefined. */ ++/* AWEX_FDF Predefined. */ ++ ++/* AWEX_DTHSBUFV Predefined. */ ++/* AWEX_DTHSBUFV Predefined. */ ++ ++/* AWEX_DTLSBUFV Predefined. */ ++/* AWEX_DTLSBUFV Predefined. */ ++ ++/* HIRES - Timer/Counter High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ ++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* LOCKBIT - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LUNF_vect_num 14 ++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_HUNF_vect_num 15 ++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPA_vect_num 16 ++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPB_vect_num 17 ++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPC_vect_num 18 ++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPD_vect_num 19 ++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LUNF_vect_num 47 ++#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_HUNF_vect_num 48 ++#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPA_vect_num 49 ++#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPB_vect_num 50 ++#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPC_vect_num 51 ++#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPD_vect_num 52 ++#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LUNF_vect_num 77 ++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_HUNF_vect_num 78 ++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPA_vect_num 79 ++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPB_vect_num 80 ++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPC_vect_num 81 ++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPD_vect_num 82 ++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* PORTF interrupt vectors */ ++#define PORTF_INT0_vect_num 104 ++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ ++#define PORTF_INT1_vect_num 105 ++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_OVF_vect_num 108 ++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LUNF_vect_num 108 ++#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_ERR_vect_num 109 ++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_HUNF_vect_num 109 ++#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCA_vect_num 110 ++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPA_vect_num 110 ++#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCB_vect_num 111 ++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPB_vect_num 111 ++#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCC_vect_num 112 ++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPC_vect_num 112 ++#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCD_vect_num 113 ++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPD_vect_num 113 ++#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (114 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (401408) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (393216) ++#define APP_SECTION_PAGE_SIZE (512) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x5E000) ++#define APPTABLE_SECTION_SIZE (8192) ++#define APPTABLE_SECTION_PAGE_SIZE (512) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x60000) ++#define BOOT_SECTION_SIZE (8192) ++#define BOOT_SECTION_PAGE_SIZE (512) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (40960) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (4096) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (32768) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (4096) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (6) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (512) ++#define USER_SIGNATURES_PAGE_SIZE (512) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (64) ++#define PROD_SIGNATURES_PAGE_SIZE (512) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 512 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 Reserved */ ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x98 ++#define SIGNATURE_2 0x47 ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA384D3_H_INCLUDED */ ++ +diff --git a/include/avr/iox64a1.h b/include/avr/iox64a1.h +index f0138e7..957fcfe 100644 +--- a/include/avr/iox64a1.h ++++ b/include/avr/iox64a1.h +@@ -1,7167 +1,7167 @@ +-/* Copyright (c) 2009-2010 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iox64a1.h 2260 2011-11-02 16:53:30Z arcanum $ */ +- +-/* avr/iox64a1.h - definitions for ATxmega64A1 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iox64a1.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATxmega64A1_H_ +-#define _AVR_ATxmega64A1_H_ 1 +- +- +-/* Ungrouped common registers */ +-#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +-#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +-#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +-#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +-#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +-#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +-#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +-#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +-#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +-#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +-#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +-#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +-#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +-#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +-#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +-#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +- +-/* Deprecated */ +-#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +-#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +-#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +-#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +-#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +-#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +-#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +-#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +-#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +-#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +-#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +-#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +-#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +-#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +-#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +-#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +- +-#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +-#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +-#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +-#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +-#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +-#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +-#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +-#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +-#define SREG _SFR_MEM8(0x003F) /* Status Register */ +- +- +-/* C Language Only */ +-#if !defined (__ASSEMBLER__) +- +-#include +- +-typedef volatile uint8_t register8_t; +-typedef volatile uint16_t register16_t; +-typedef volatile uint32_t register32_t; +- +- +-#ifdef _WORDREGISTER +-#undef _WORDREGISTER +-#endif +-#define _WORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register16_t regname; \ +- struct \ +- { \ +- register8_t regname ## L; \ +- register8_t regname ## H; \ +- }; \ +- } +- +-#ifdef _DWORDREGISTER +-#undef _DWORDREGISTER +-#endif +-#define _DWORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register32_t regname; \ +- struct \ +- { \ +- register8_t regname ## 0; \ +- register8_t regname ## 1; \ +- register8_t regname ## 2; \ +- register8_t regname ## 3; \ +- }; \ +- } +- +- +-/* +-========================================================================== +-IO Module Structures +-========================================================================== +-*/ +- +- +-/* +--------------------------------------------------------------------------- +-XOCD - On-Chip Debug System +--------------------------------------------------------------------------- +-*/ +- +-/* On-Chip Debug System */ +-typedef struct OCD_struct +-{ +- register8_t OCDR0; /* OCD Register 0 */ +- register8_t OCDR1; /* OCD Register 1 */ +-} OCD_t; +- +- +-/* CCP signatures */ +-typedef enum CCP_enum +-{ +- CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ +- CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +-} CCP_t; +- +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Clock System */ +-typedef struct CLK_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t PSCTRL; /* Prescaler Control Register */ +- register8_t LOCK; /* Lock register */ +- register8_t RTCCTRL; /* RTC Control Register */ +-} CLK_t; +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Power Reduction */ +-typedef struct PR_struct +-{ +- register8_t PRGEN; /* General Power Reduction */ +- register8_t PRPA; /* Power Reduction Port A */ +- register8_t PRPB; /* Power Reduction Port B */ +- register8_t PRPC; /* Power Reduction Port C */ +- register8_t PRPD; /* Power Reduction Port D */ +- register8_t PRPE; /* Power Reduction Port E */ +- register8_t PRPF; /* Power Reduction Port F */ +-} PR_t; +- +-/* System Clock Selection */ +-typedef enum CLK_SCLKSEL_enum +-{ +- CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ +- CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ +- CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ +- CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ +- CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +-} CLK_SCLKSEL_t; +- +-/* Prescaler A Division Factor */ +-typedef enum CLK_PSADIV_enum +-{ +- CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ +- CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ +- CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ +- CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ +- CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ +- CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ +- CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ +- CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ +- CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ +- CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +-} CLK_PSADIV_t; +- +-/* Prescaler B and C Division Factor */ +-typedef enum CLK_PSBCDIV_enum +-{ +- CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ +- CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ +- CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ +- CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +-} CLK_PSBCDIV_t; +- +-/* RTC Clock Source */ +-typedef enum CLK_RTCSRC_enum +-{ +- CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ +- CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ +- CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ +- CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +-} CLK_RTCSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-SLEEP - Sleep Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Sleep Controller */ +-typedef struct SLEEP_struct +-{ +- register8_t CTRL; /* Control Register */ +-} SLEEP_t; +- +-/* Sleep Mode */ +-typedef enum SLEEP_SMODE_enum +-{ +- SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ +- SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +- SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ +- SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ +- SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +-} SLEEP_SMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-OSC - Oscillator +--------------------------------------------------------------------------- +-*/ +- +-/* Oscillator */ +-typedef struct OSC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t XOSCCTRL; /* External Oscillator Control Register */ +- register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ +- register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ +- register8_t PLLCTRL; /* PLL Control REgister */ +- register8_t DFLLCTRL; /* DFLL Control Register */ +-} OSC_t; +- +-/* Oscillator Frequency Range */ +-typedef enum OSC_FRQRANGE_enum +-{ +- OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ +- OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ +- OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ +- OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +-} OSC_FRQRANGE_t; +- +-/* External Oscillator Selection and Startup Time */ +-typedef enum OSC_XOSCSEL_enum +-{ +- OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ +- OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ +- OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ +- OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ +- OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +-} OSC_XOSCSEL_t; +- +-/* PLL Clock Source */ +-typedef enum OSC_PLLSRC_enum +-{ +- OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ +- OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ +- OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +-} OSC_PLLSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-DFLL - DFLL +--------------------------------------------------------------------------- +-*/ +- +-/* DFLL */ +-typedef struct DFLL_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t CALA; /* Calibration Register A */ +- register8_t CALB; /* Calibration Register B */ +- register8_t COMP0; /* Oscillator Compare Register 0 */ +- register8_t COMP1; /* Oscillator Compare Register 1 */ +- register8_t COMP2; /* Oscillator Compare Register 2 */ +- register8_t reserved_0x07; +-} DFLL_t; +- +- +-/* +--------------------------------------------------------------------------- +-RST - Reset +--------------------------------------------------------------------------- +-*/ +- +-/* Reset */ +-typedef struct RST_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t CTRL; /* Control Register */ +-} RST_t; +- +- +-/* +--------------------------------------------------------------------------- +-WDT - Watch-Dog Timer +--------------------------------------------------------------------------- +-*/ +- +-/* Watch-Dog Timer */ +-typedef struct WDT_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t WINCTRL; /* Windowed Mode Control */ +- register8_t STATUS; /* Status */ +-} WDT_t; +- +-/* Period setting */ +-typedef enum WDT_PER_enum +-{ +- WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ +- WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ +- WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ +- WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_PER_t; +- +-/* Closed window period */ +-typedef enum WDT_WPER_enum +-{ +- WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ +- WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ +- WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ +- WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_WPER_t; +- +- +-/* +--------------------------------------------------------------------------- +-MCU - MCU Control +--------------------------------------------------------------------------- +-*/ +- +-/* MCU Control */ +-typedef struct MCU_struct +-{ +- register8_t DEVID0; /* Device ID byte 0 */ +- register8_t DEVID1; /* Device ID byte 1 */ +- register8_t DEVID2; /* Device ID byte 2 */ +- register8_t REVID; /* Revision ID */ +- register8_t JTAGUID; /* JTAG User ID */ +- register8_t reserved_0x05; +- register8_t MCUCR; /* MCU Control */ +- register8_t reserved_0x07; +- register8_t EVSYSLOCK; /* Event System Lock */ +- register8_t AWEXLOCK; /* AWEX Lock */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +-} MCU_t; +- +- +-/* +--------------------------------------------------------------------------- +-PMIC - Programmable Multi-level Interrupt Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Programmable Multi-level Interrupt Controller */ +-typedef struct PMIC_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t INTPRI; /* Interrupt Priority */ +- register8_t CTRL; /* Control Register */ +-} PMIC_t; +- +- +-/* +--------------------------------------------------------------------------- +-DMA - DMA Controller +--------------------------------------------------------------------------- +-*/ +- +-/* DMA Channel */ +-typedef struct DMA_CH_struct +-{ +- register8_t CTRLA; /* Channel Control */ +- register8_t CTRLB; /* Channel Control */ +- register8_t ADDRCTRL; /* Address Control */ +- register8_t TRIGSRC; /* Channel Trigger Source */ +- _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ +- register8_t REPCNT; /* Channel Repeat Count */ +- register8_t reserved_0x07; +- register8_t SRCADDR0; /* Channel Source Address 0 */ +- register8_t SRCADDR1; /* Channel Source Address 1 */ +- register8_t SRCADDR2; /* Channel Source Address 2 */ +- register8_t reserved_0x0B; +- register8_t DESTADDR0; /* Channel Destination Address 0 */ +- register8_t DESTADDR1; /* Channel Destination Address 1 */ +- register8_t DESTADDR2; /* Channel Destination Address 2 */ +- register8_t reserved_0x0F; +-} DMA_CH_t; +- +-/* +--------------------------------------------------------------------------- +-DMA - DMA Controller +--------------------------------------------------------------------------- +-*/ +- +-/* DMA Controller */ +-typedef struct DMA_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t reserved_0x01; +- register8_t reserved_0x02; +- register8_t INTFLAGS; /* Transfer Interrupt Status */ +- register8_t STATUS; /* Status */ +- register8_t reserved_0x05; +- _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- DMA_CH_t CH0; /* DMA Channel 0 */ +- DMA_CH_t CH1; /* DMA Channel 1 */ +- DMA_CH_t CH2; /* DMA Channel 2 */ +- DMA_CH_t CH3; /* DMA Channel 3 */ +-} DMA_t; +- +-/* Burst mode */ +-typedef enum DMA_CH_BURSTLEN_enum +-{ +- DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ +- DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ +- DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ +- DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +-} DMA_CH_BURSTLEN_t; +- +-/* Source address reload mode */ +-typedef enum DMA_CH_SRCRELOAD_enum +-{ +- DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ +- DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ +- DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ +- DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +-} DMA_CH_SRCRELOAD_t; +- +-/* Source addressing mode */ +-typedef enum DMA_CH_SRCDIR_enum +-{ +- DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ +- DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ +- DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +-} DMA_CH_SRCDIR_t; +- +-/* Destination adress reload mode */ +-typedef enum DMA_CH_DESTRELOAD_enum +-{ +- DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ +- DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ +- DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ +- DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +-} DMA_CH_DESTRELOAD_t; +- +-/* Destination adressing mode */ +-typedef enum DMA_CH_DESTDIR_enum +-{ +- DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ +- DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ +- DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +-} DMA_CH_DESTDIR_t; +- +-/* Transfer trigger source */ +-typedef enum DMA_CH_TRIGSRC_enum +-{ +- DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ +- DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ +- DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ +- DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ +- DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ +- DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ +- DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ +- DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ +- DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ +- DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ +- DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ +- DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ +- DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ +- DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ +- DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ +- DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ +- DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ +- DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ +- DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ +- DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ +- DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ +- DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ +- DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ +- DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ +- DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ +- DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ +- DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ +- DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ +- DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ +- DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ +- DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ +- DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ +- DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ +- DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ +- DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ +- DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ +- DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ +- DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ +- DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +-} DMA_CH_TRIGSRC_t; +- +-/* Double buffering mode */ +-typedef enum DMA_DBUFMODE_enum +-{ +- DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ +- DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ +- DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ +- DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +-} DMA_DBUFMODE_t; +- +-/* Priority mode */ +-typedef enum DMA_PRIMODE_enum +-{ +- DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ +- DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ +- DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ +- DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +-} DMA_PRIMODE_t; +- +-/* Interrupt level */ +-typedef enum DMA_CH_ERRINTLVL_enum +-{ +- DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ +- DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ +- DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +-} DMA_CH_ERRINTLVL_t; +- +-/* Interrupt level */ +-typedef enum DMA_CH_TRNINTLVL_enum +-{ +- DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ +- DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ +- DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +-} DMA_CH_TRNINTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-EVSYS - Event System +--------------------------------------------------------------------------- +-*/ +- +-/* Event System */ +-typedef struct EVSYS_struct +-{ +- register8_t CH0MUX; /* Event Channel 0 Multiplexer */ +- register8_t CH1MUX; /* Event Channel 1 Multiplexer */ +- register8_t CH2MUX; /* Event Channel 2 Multiplexer */ +- register8_t CH3MUX; /* Event Channel 3 Multiplexer */ +- register8_t CH4MUX; /* Event Channel 4 Multiplexer */ +- register8_t CH5MUX; /* Event Channel 5 Multiplexer */ +- register8_t CH6MUX; /* Event Channel 6 Multiplexer */ +- register8_t CH7MUX; /* Event Channel 7 Multiplexer */ +- register8_t CH0CTRL; /* Channel 0 Control Register */ +- register8_t CH1CTRL; /* Channel 1 Control Register */ +- register8_t CH2CTRL; /* Channel 2 Control Register */ +- register8_t CH3CTRL; /* Channel 3 Control Register */ +- register8_t CH4CTRL; /* Channel 4 Control Register */ +- register8_t CH5CTRL; /* Channel 5 Control Register */ +- register8_t CH6CTRL; /* Channel 6 Control Register */ +- register8_t CH7CTRL; /* Channel 7 Control Register */ +- register8_t STROBE; /* Event Strobe */ +- register8_t DATA; /* Event Data */ +-} EVSYS_t; +- +-/* Quadrature Decoder Index Recognition Mode */ +-typedef enum EVSYS_QDIRM_enum +-{ +- EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ +- EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ +- EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ +- EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +-} EVSYS_QDIRM_t; +- +-/* Digital filter coefficient */ +-typedef enum EVSYS_DIGFILT_enum +-{ +- EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ +- EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ +- EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ +- EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ +- EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ +- EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ +- EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ +- EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +-} EVSYS_DIGFILT_t; +- +-/* Event Channel multiplexer input selection */ +-typedef enum EVSYS_CHMUX_enum +-{ +- EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ +- EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ +- EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ +- EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ +- EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ +- EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ +- EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ +- EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ +- EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ +- EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ +- EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ +- EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ +- EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ +- EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ +- EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ +- EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ +- EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ +- EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ +- EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ +- EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ +- EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ +- EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ +- EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ +- EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ +- EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ +- EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ +- EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ +- EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ +- EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ +- EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ +- EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ +- EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ +- EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ +- EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ +- EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ +- EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ +- EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ +- EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ +- EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ +- EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ +- EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ +- EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ +- EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ +- EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ +- EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ +- EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ +- EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ +- EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ +- EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ +- EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ +- EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ +- EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ +- EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ +- EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ +- EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ +- EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ +- EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ +- EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ +- EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ +- EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ +- EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ +- EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ +- EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ +- EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ +- EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ +- EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ +- EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ +- EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ +- EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ +- EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ +- EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ +- EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ +- EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ +- EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ +- EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ +- EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ +- EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ +- EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ +- EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ +- EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ +- EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ +- EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ +- EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ +- EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ +- EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ +- EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ +- EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ +- EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ +- EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ +- EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ +- EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ +- EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ +- EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ +- EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ +- EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ +- EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ +- EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ +- EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ +- EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ +- EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ +- EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ +- EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ +- EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ +- EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ +- EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ +- EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ +- EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ +- EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ +- EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ +- EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ +- EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +- EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ +- EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ +- EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ +- EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +-} EVSYS_CHMUX_t; +- +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Non-volatile Memory Controller */ +-typedef struct NVM_struct +-{ +- register8_t ADDR0; /* Address Register 0 */ +- register8_t ADDR1; /* Address Register 1 */ +- register8_t ADDR2; /* Address Register 2 */ +- register8_t reserved_0x03; +- register8_t DATA0; /* Data Register 0 */ +- register8_t DATA1; /* Data Register 1 */ +- register8_t DATA2; /* Data Register 2 */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t CMD; /* Command */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t INTCTRL; /* Interrupt Control */ +- register8_t reserved_0x0E; +- register8_t STATUS; /* Status */ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Lock Bits */ +-typedef struct NVM_LOCKBITS_struct +-{ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_LOCKBITS_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Fuses */ +-typedef struct NVM_FUSES_struct +-{ +- register8_t FUSEBYTE0; /* JTAG User ID */ +- register8_t FUSEBYTE1; /* Watchdog Configuration */ +- register8_t FUSEBYTE2; /* Reset Configuration */ +- register8_t reserved_0x03; +- register8_t FUSEBYTE4; /* Start-up Configuration */ +- register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +-} NVM_FUSES_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Production Signatures */ +-typedef struct NVM_PROD_SIGNATURES_struct +-{ +- register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ +- register8_t reserved_0x01; +- register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ +- register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ +- register8_t reserved_0x04; +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ +- register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ +- register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ +- register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ +- register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ +- register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t WAFNUM; /* Wafer Number */ +- register8_t reserved_0x11; +- register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ +- register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ +- register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ +- register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ +- register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ +- register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ +- register8_t reserved_0x26; +- register8_t reserved_0x27; +- register8_t reserved_0x28; +- register8_t reserved_0x29; +- register8_t reserved_0x2A; +- register8_t reserved_0x2B; +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ +- register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ +- register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ +- register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ +- register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ +- register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- register8_t reserved_0x36; +- register8_t reserved_0x37; +- register8_t reserved_0x38; +- register8_t reserved_0x39; +- register8_t reserved_0x3A; +- register8_t reserved_0x3B; +- register8_t reserved_0x3C; +- register8_t reserved_0x3D; +- register8_t reserved_0x3E; +-} NVM_PROD_SIGNATURES_t; +- +-/* NVM Command */ +-typedef enum NVM_CMD_enum +-{ +- NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ +- NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ +- NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ +- NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ +- NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ +- NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ +- NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ +- NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ +- NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ +- NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ +- NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ +- NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ +- NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ +- NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ +- NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ +- NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ +- NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ +- NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ +- NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ +- NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ +- NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ +- NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ +- NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ +- NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ +- NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ +- NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +-} NVM_CMD_t; +- +-/* SPM ready interrupt level */ +-typedef enum NVM_SPMLVL_enum +-{ +- NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ +- NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ +- NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +-} NVM_SPMLVL_t; +- +-/* EEPROM ready interrupt level */ +-typedef enum NVM_EELVL_enum +-{ +- NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ +- NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ +- NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +-} NVM_EELVL_t; +- +-/* Boot lock bits - boot setcion */ +-typedef enum NVM_BLBB_enum +-{ +- NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +- NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ +- NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ +- NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +-} NVM_BLBB_t; +- +-/* Boot lock bits - application section */ +-typedef enum NVM_BLBA_enum +-{ +- NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +- NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ +- NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ +- NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +-} NVM_BLBA_t; +- +-/* Boot lock bits - application table section */ +-typedef enum NVM_BLBAT_enum +-{ +- NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +- NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ +- NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ +- NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +-} NVM_BLBAT_t; +- +-/* Lock bits */ +-typedef enum NVM_LB_enum +-{ +- NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +- NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ +- NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +-} NVM_LB_t; +- +-/* Boot Loader Section Reset Vector */ +-typedef enum BOOTRST_enum +-{ +- BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ +- BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +-} BOOTRST_t; +- +-/* BOD operation */ +-typedef enum BOD_enum +-{ +- BOD_INSAMPLEDMODE_gc = (0x01<<2), /* BOD enabled in sampled mode */ +- BOD_CONTINOUSLY_gc = (0x02<<2), /* BOD enabled continuously */ +- BOD_DISABLED_gc = (0x03<<2), /* BOD Disabled */ +-} BOD_t; +- +-/* Watchdog (Window) Timeout Period */ +-typedef enum WD_enum +-{ +- WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ +- WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ +- WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ +- WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ +- WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ +- WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ +- WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ +- WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ +- WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ +- WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ +- WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +-} WD_t; +- +-/* Start-up Time */ +-typedef enum SUT_enum +-{ +- SUT_0MS_gc = (0x03<<2), /* 0 ms */ +- SUT_4MS_gc = (0x01<<2), /* 4 ms */ +- SUT_64MS_gc = (0x00<<2), /* 64 ms */ +-} SUT_t; +- +-/* Brown Out Detection Voltage Level */ +-typedef enum BODLVL_enum +-{ +- BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ +- BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ +- BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ +- BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ +- BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ +- BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ +- BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ +-} BODLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-AC - Analog Comparator +--------------------------------------------------------------------------- +-*/ +- +-/* Analog Comparator */ +-typedef struct AC_struct +-{ +- register8_t AC0CTRL; /* Comparator 0 Control */ +- register8_t AC1CTRL; /* Comparator 1 Control */ +- register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ +- register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t WINCTRL; /* Window Mode Control */ +- register8_t STATUS; /* Status */ +-} AC_t; +- +-/* Interrupt mode */ +-typedef enum AC_INTMODE_enum +-{ +- AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ +- AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ +- AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +-} AC_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum AC_INTLVL_enum +-{ +- AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ +- AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ +- AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ +- AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +-} AC_INTLVL_t; +- +-/* Hysteresis mode selection */ +-typedef enum AC_HYSMODE_enum +-{ +- AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ +- AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ +- AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +-} AC_HYSMODE_t; +- +-/* Positive input multiplexer selection */ +-typedef enum AC_MUXPOS_enum +-{ +- AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ +- AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ +- AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ +- AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ +- AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ +- AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ +- AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +- AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +-} AC_MUXPOS_t; +- +-/* Negative input multiplexer selection */ +-typedef enum AC_MUXNEG_enum +-{ +- AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ +- AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ +- AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ +- AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ +- AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ +- AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ +- AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ +- AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +-} AC_MUXNEG_t; +- +-/* Windows interrupt mode */ +-typedef enum AC_WINTMODE_enum +-{ +- AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ +- AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ +- AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ +- AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +-} AC_WINTMODE_t; +- +-/* Window interrupt level */ +-typedef enum AC_WINTLVL_enum +-{ +- AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ +- AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ +- AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +-} AC_WINTLVL_t; +- +-/* Window mode state */ +-typedef enum AC_WSTATE_enum +-{ +- AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ +- AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ +- AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +-} AC_WSTATE_t; +- +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* ADC Channel */ +-typedef struct ADC_CH_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t MUXCTRL; /* MUX Control */ +- register8_t INTCTRL; /* Channel Interrupt Control */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- _WORDREGISTER(RES); /* Channel Result */ +- register8_t reserved_0x6; +- register8_t reserved_0x7; +-} ADC_CH_t; +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Analog-to-Digital Converter */ +-typedef struct ADC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t REFCTRL; /* Reference Control */ +- register8_t EVCTRL; /* Event Control */ +- register8_t PRESCALER; /* Clock Prescaler */ +- register8_t reserved_0x05; +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- _WORDREGISTER(CAL); /* Calibration Value */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- _WORDREGISTER(CH0RES); /* Channel 0 Result */ +- _WORDREGISTER(CH1RES); /* Channel 1 Result */ +- _WORDREGISTER(CH2RES); /* Channel 2 Result */ +- _WORDREGISTER(CH3RES); /* Channel 3 Result */ +- _WORDREGISTER(CMP); /* Compare Value */ +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- ADC_CH_t CH0; /* ADC Channel 0 */ +- ADC_CH_t CH1; /* ADC Channel 1 */ +- ADC_CH_t CH2; /* ADC Channel 2 */ +- ADC_CH_t CH3; /* ADC Channel 3 */ +-} ADC_t; +- +-/* Positive input multiplexer selection */ +-typedef enum ADC_CH_MUXPOS_enum +-{ +- ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ +- ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ +- ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ +- ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ +- ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ +- ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ +- ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ +- ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +-} ADC_CH_MUXPOS_t; +- +-/* Internal input multiplexer selections */ +-typedef enum ADC_CH_MUXINT_enum +-{ +- ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ +- ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ +- ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +- ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +-} ADC_CH_MUXINT_t; +- +-/* Negative input multiplexer selection */ +-typedef enum ADC_CH_MUXNEG_enum +-{ +- ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ +- ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ +- ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ +- ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ +- ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ +- ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ +- ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ +- ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +-} ADC_CH_MUXNEG_t; +- +-/* Input mode */ +-typedef enum ADC_CH_INPUTMODE_enum +-{ +- ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ +- ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ +- ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ +- ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +-} ADC_CH_INPUTMODE_t; +- +-/* Gain factor */ +-typedef enum ADC_CH_GAIN_enum +-{ +- ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ +- ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ +- ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ +- ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ +- ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ +- ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ +- ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ +-} ADC_CH_GAIN_t; +- +-/* Conversion result resolution */ +-typedef enum ADC_RESOLUTION_enum +-{ +- ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ +- ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ +- ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +-} ADC_RESOLUTION_t; +- +-/* Voltage reference selection */ +-typedef enum ADC_REFSEL_enum +-{ +- ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ +- ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ +- ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ +- ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +-} ADC_REFSEL_t; +- +-/* Channel sweep selection */ +-typedef enum ADC_SWEEP_enum +-{ +- ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ +- ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ +- ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ +- ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +-} ADC_SWEEP_t; +- +-/* Event channel input selection */ +-typedef enum ADC_EVSEL_enum +-{ +- ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ +- ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ +- ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ +- ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ +- ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ +- ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ +- ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ +- ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +-} ADC_EVSEL_t; +- +-/* Event action selection */ +-typedef enum ADC_EVACT_enum +-{ +- ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ +- ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ +- ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ +- ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ +- ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ +- ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ +- ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ +-} ADC_EVACT_t; +- +-/* Interupt mode */ +-typedef enum ADC_CH_INTMODE_enum +-{ +- ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ +- ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ +- ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +-} ADC_CH_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum ADC_CH_INTLVL_enum +-{ +- ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ +- ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ +- ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +-} ADC_CH_INTLVL_t; +- +-/* DMA request selection */ +-typedef enum ADC_DMASEL_enum +-{ +- ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ +- ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ +- ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ +- ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +-} ADC_DMASEL_t; +- +-/* Clock prescaler */ +-typedef enum ADC_PRESCALER_enum +-{ +- ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ +- ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ +- ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ +- ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ +- ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ +- ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ +- ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ +- ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +-} ADC_PRESCALER_t; +- +- +-/* +--------------------------------------------------------------------------- +-DAC - Digital/Analog Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Digital-to-Analog Converter */ +-typedef struct DAC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t EVCTRL; /* Event Input Control */ +- register8_t TIMCTRL; /* Timing Control */ +- register8_t STATUS; /* Status */ +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t GAINCAL; /* Gain Calibration */ +- register8_t OFFSETCAL; /* Offset Calibration */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- _WORDREGISTER(CH0DATA); /* Channel 0 Data */ +- _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +-} DAC_t; +- +-/* Output channel selection */ +-typedef enum DAC_CHSEL_enum +-{ +- DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ +- DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ +-} DAC_CHSEL_t; +- +-/* Reference voltage selection */ +-typedef enum DAC_REFSEL_enum +-{ +- DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ +- DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ +- DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ +- DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +-} DAC_REFSEL_t; +- +-/* Event channel selection */ +-typedef enum DAC_EVSEL_enum +-{ +- DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ +- DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ +- DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ +- DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ +- DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ +- DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ +- DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ +- DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +-} DAC_EVSEL_t; +- +-/* Conversion interval */ +-typedef enum DAC_CONINTVAL_enum +-{ +- DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ +- DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ +- DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ +- DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ +- DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ +- DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ +- DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ +- DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ +-} DAC_CONINTVAL_t; +- +-/* Refresh rate */ +-typedef enum DAC_REFRESH_enum +-{ +- DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ +- DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ +- DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ +- DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ +- DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ +- DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ +- DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ +- DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ +- DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ +- DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ +- DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ +- DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ +- DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ +- DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ +-} DAC_REFRESH_t; +- +- +-/* +--------------------------------------------------------------------------- +-RTC - Real-Time Clounter +--------------------------------------------------------------------------- +-*/ +- +-/* Real-Time Counter */ +-typedef struct RTC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t TEMP; /* Temporary register */ +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- _WORDREGISTER(CNT); /* Count Register */ +- _WORDREGISTER(PER); /* Period Register */ +- _WORDREGISTER(COMP); /* Compare Register */ +-} RTC_t; +- +-/* Prescaler Factor */ +-typedef enum RTC_PRESCALER_enum +-{ +- RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ +- RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ +- RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ +- RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ +- RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ +- RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ +- RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ +- RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +-} RTC_PRESCALER_t; +- +-/* Compare Interrupt level */ +-typedef enum RTC_COMPINTLVL_enum +-{ +- RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} RTC_COMPINTLVL_t; +- +-/* Overflow Interrupt level */ +-typedef enum RTC_OVFINTLVL_enum +-{ +- RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} RTC_OVFINTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* EBI Chip Select Module */ +-typedef struct EBI_CS_struct +-{ +- register8_t CTRLA; /* Chip Select Control Register A */ +- register8_t CTRLB; /* Chip Select Control Register B */ +- _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +-} EBI_CS_t; +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* External Bus Interface */ +-typedef struct EBI_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t SDRAMCTRLA; /* SDRAM Control Register A */ +- register8_t reserved_0x02; +- register8_t reserved_0x03; +- _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ +- _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ +- register8_t SDRAMCTRLB; /* SDRAM Control Register B */ +- register8_t SDRAMCTRLC; /* SDRAM Control Register C */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- EBI_CS_t CS0; /* Chip Select 0 */ +- EBI_CS_t CS1; /* Chip Select 1 */ +- EBI_CS_t CS2; /* Chip Select 2 */ +- EBI_CS_t CS3; /* Chip Select 3 */ +-} EBI_t; +- +-/* Chip Select adress space */ +-typedef enum EBI_CS_ASIZE_enum +-{ +- EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ +- EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ +- EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ +- EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ +- EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ +- EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ +- EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ +- EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ +- EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ +- EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ +- EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ +- EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ +- EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ +- EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ +- EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ +- EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ +- EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +-} EBI_CS_ASIZE_t; +- +-/* */ +-typedef enum EBI_CS_SRWS_enum +-{ +- EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_CS_SRWS_t; +- +-/* Chip Select address mode */ +-typedef enum EBI_CS_MODE_enum +-{ +- EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ +- EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ +- EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ +- EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +-} EBI_CS_MODE_t; +- +-/* Chip Select SDRAM mode */ +-typedef enum EBI_CS_SDMODE_enum +-{ +- EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ +- EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +-} EBI_CS_SDMODE_t; +- +-/* */ +-typedef enum EBI_SDDATAW_enum +-{ +- EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ +- EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +-} EBI_SDDATAW_t; +- +-/* */ +-typedef enum EBI_LPCMODE_enum +-{ +- EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ +- EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +-} EBI_LPCMODE_t; +- +-/* */ +-typedef enum EBI_SRMODE_enum +-{ +- EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ +- EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ +- EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ +- EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +-} EBI_SRMODE_t; +- +-/* */ +-typedef enum EBI_IFMODE_enum +-{ +- EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ +- EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ +- EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ +- EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +-} EBI_IFMODE_t; +- +-/* */ +-typedef enum EBI_SDCOL_enum +-{ +- EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ +- EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ +- EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ +- EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +-} EBI_SDCOL_t; +- +-/* */ +-typedef enum EBI_MRDLY_enum +-{ +- EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_MRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCYCDLY_enum +-{ +- EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ROWCYCDLY_t; +- +-/* */ +-typedef enum EBI_RPDLY_enum +-{ +- EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_RPDLY_t; +- +-/* */ +-typedef enum EBI_WRDLY_enum +-{ +- EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_WRDLY_t; +- +-/* */ +-typedef enum EBI_ESRDLY_enum +-{ +- EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ESRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCOLDLY_enum +-{ +- EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_ROWCOLDLY_t; +- +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_MASTER_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t STATUS; /* Status Register */ +- register8_t BAUD; /* Baurd Rate Control Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +-} TWI_MASTER_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_SLAVE_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t STATUS; /* Status Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +- register8_t ADDRMASK; /* Address Mask Register */ +-} TWI_SLAVE_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Two-Wire Interface */ +-typedef struct TWI_struct +-{ +- register8_t CTRL; /* TWI Common Control Register */ +- TWI_MASTER_t MASTER; /* TWI master module */ +- TWI_SLAVE_t SLAVE; /* TWI slave module */ +-} TWI_t; +- +-/* Master Interrupt Level */ +-typedef enum TWI_MASTER_INTLVL_enum +-{ +- TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_MASTER_INTLVL_t; +- +-/* Inactive Timeout */ +-typedef enum TWI_MASTER_TIMEOUT_enum +-{ +- TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ +- TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ +- TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ +- TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +-} TWI_MASTER_TIMEOUT_t; +- +-/* Master Command */ +-typedef enum TWI_MASTER_CMD_enum +-{ +- TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ +- TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ +- TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +-} TWI_MASTER_CMD_t; +- +-/* Master Bus State */ +-typedef enum TWI_MASTER_BUSSTATE_enum +-{ +- TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ +- TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ +- TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ +- TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +-} TWI_MASTER_BUSSTATE_t; +- +-/* Slave Interrupt Level */ +-typedef enum TWI_SLAVE_INTLVL_enum +-{ +- TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_SLAVE_INTLVL_t; +- +-/* Slave Command */ +-typedef enum TWI_SLAVE_CMD_enum +-{ +- TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ +- TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +-} TWI_SLAVE_CMD_t; +- +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O port Configuration */ +-typedef struct PORTCFG_struct +-{ +- register8_t MPCMASK; /* Multi-pin Configuration Mask */ +- register8_t reserved_0x01; +- register8_t VPCTRLA; /* Virtual Port Control Register A */ +- register8_t VPCTRLB; /* Virtual Port Control Register B */ +- register8_t CLKEVOUT; /* Clock and Event Out Register */ +-} PORTCFG_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* Virtual Port */ +-typedef struct VPORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t OUT; /* I/O Port Output */ +- register8_t IN; /* I/O Port Input */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +-} VPORT_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O Ports */ +-typedef struct PORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t DIRSET; /* I/O Port Data Direction Set */ +- register8_t DIRCLR; /* I/O Port Data Direction Clear */ +- register8_t DIRTGL; /* I/O Port Data Direction Toggle */ +- register8_t OUT; /* I/O Port Output */ +- register8_t OUTSET; /* I/O Port Output Set */ +- register8_t OUTCLR; /* I/O Port Output Clear */ +- register8_t OUTTGL; /* I/O Port Output Toggle */ +- register8_t IN; /* I/O port Input */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INT0MASK; /* Port Interrupt 0 Mask */ +- register8_t INT1MASK; /* Port Interrupt 1 Mask */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t PIN0CTRL; /* Pin 0 Control Register */ +- register8_t PIN1CTRL; /* Pin 1 Control Register */ +- register8_t PIN2CTRL; /* Pin 2 Control Register */ +- register8_t PIN3CTRL; /* Pin 3 Control Register */ +- register8_t PIN4CTRL; /* Pin 4 Control Register */ +- register8_t PIN5CTRL; /* Pin 5 Control Register */ +- register8_t PIN6CTRL; /* Pin 6 Control Register */ +- register8_t PIN7CTRL; /* Pin 7 Control Register */ +-} PORT_t; +- +-/* Virtual Port 0 Mapping */ +-typedef enum PORTCFG_VP0MAP_enum +-{ +- PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP0MAP_t; +- +-/* Virtual Port 1 Mapping */ +-typedef enum PORTCFG_VP1MAP_enum +-{ +- PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP1MAP_t; +- +-/* Virtual Port 2 Mapping */ +-typedef enum PORTCFG_VP2MAP_enum +-{ +- PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP2MAP_t; +- +-/* Virtual Port 3 Mapping */ +-typedef enum PORTCFG_VP3MAP_enum +-{ +- PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP3MAP_t; +- +-/* Clock Output Port */ +-typedef enum PORTCFG_CLKOUT_enum +-{ +- PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ +- PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ +- PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ +- PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +-} PORTCFG_CLKOUT_t; +- +-/* Event Output Port */ +-typedef enum PORTCFG_EVOUT_enum +-{ +- PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ +- PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ +- PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ +- PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +-} PORTCFG_EVOUT_t; +- +-/* Port Interrupt 0 Level */ +-typedef enum PORT_INT0LVL_enum +-{ +- PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ +- PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ +- PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +-} PORT_INT0LVL_t; +- +-/* Port Interrupt 1 Level */ +-typedef enum PORT_INT1LVL_enum +-{ +- PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ +- PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ +- PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +-} PORT_INT1LVL_t; +- +-/* Output/Pull Configuration */ +-typedef enum PORT_OPC_enum +-{ +- PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ +- PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ +- PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ +- PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ +- PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ +- PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ +- PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ +- PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +-} PORT_OPC_t; +- +-/* Input/Sense Configuration */ +-typedef enum PORT_ISC_enum +-{ +- PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ +- PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ +- PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ +- PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ +- PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +-} PORT_ISC_t; +- +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 0 */ +-typedef struct TC0_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- _WORDREGISTER(CCC); /* Compare or Capture C */ +- _WORDREGISTER(CCD); /* Compare or Capture D */ +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +- _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ +- _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +-} TC0_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 1 */ +-typedef struct TC1_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t reserved_0x2E; +- register8_t reserved_0x2F; +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +-} TC1_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* Advanced Waveform Extension */ +-typedef struct AWEX_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t FDEMASK; /* Fault Detection Event Mask */ +- register8_t FDCTRL; /* Fault Detection Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x05; +- register8_t DTBOTH; /* Dead Time Both Sides */ +- register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ +- register8_t DTLS; /* Dead Time Low Side */ +- register8_t DTHS; /* Dead Time High Side */ +- register8_t DTLSBUF; /* Dead Time Low Side Buffer */ +- register8_t DTHSBUF; /* Dead Time High Side Buffer */ +- register8_t OUTOVEN; /* Output Override Enable */ +-} AWEX_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* High-Resolution Extension */ +-typedef struct HIRES_struct +-{ +- register8_t CTRLA; /* Control Register */ +-} HIRES_t; +- +-/* Clock Selection */ +-typedef enum TC_CLKSEL_enum +-{ +- TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ +- TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ +- TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ +- TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ +- TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ +- TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ +- TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ +- TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ +- TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_CLKSEL_t; +- +-/* Waveform Generation Mode */ +-typedef enum TC_WGMODE_enum +-{ +- TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ +- TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ +- TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ +- TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ +- TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ +- TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +-} TC_WGMODE_t; +- +-/* Event Action */ +-typedef enum TC_EVACT_enum +-{ +- TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ +- TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ +- TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ +- TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ +- TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ +- TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ +- TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +-} TC_EVACT_t; +- +-/* Event Selection */ +-typedef enum TC_EVSEL_enum +-{ +- TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_EVSEL_t; +- +-/* Error Interrupt Level */ +-typedef enum TC_ERRINTLVL_enum +-{ +- TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_ERRINTLVL_t; +- +-/* Overflow Interrupt Level */ +-typedef enum TC_OVFINTLVL_enum +-{ +- TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_OVFINTLVL_t; +- +-/* Compare or Capture D Interrupt Level */ +-typedef enum TC_CCDINTLVL_enum +-{ +- TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TC_CCDINTLVL_t; +- +-/* Compare or Capture C Interrupt Level */ +-typedef enum TC_CCCINTLVL_enum +-{ +- TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} TC_CCCINTLVL_t; +- +-/* Compare or Capture B Interrupt Level */ +-typedef enum TC_CCBINTLVL_enum +-{ +- TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_CCBINTLVL_t; +- +-/* Compare or Capture A Interrupt Level */ +-typedef enum TC_CCAINTLVL_enum +-{ +- TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_CCAINTLVL_t; +- +-/* Timer/Counter Command */ +-typedef enum TC_CMD_enum +-{ +- TC_CMD_NONE_gc = (0x00<<2), /* No Command */ +- TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ +- TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ +- TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +-} TC_CMD_t; +- +-/* Fault Detect Action */ +-typedef enum AWEX_FDACT_enum +-{ +- AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ +- AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ +- AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +-} AWEX_FDACT_t; +- +-/* High Resolution Enable */ +-typedef enum HIRES_HREN_enum +-{ +- HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ +- HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ +- HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ +- HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +-} HIRES_HREN_t; +- +- +-/* +--------------------------------------------------------------------------- +-USART - Universal Asynchronous Receiver-Transmitter +--------------------------------------------------------------------------- +-*/ +- +-/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +-typedef struct USART_struct +-{ +- register8_t DATA; /* Data Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x02; +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t BAUDCTRLA; /* Baud Rate Control Register A */ +- register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +-} USART_t; +- +-/* Receive Complete Interrupt level */ +-typedef enum USART_RXCINTLVL_enum +-{ +- USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} USART_RXCINTLVL_t; +- +-/* Transmit Complete Interrupt level */ +-typedef enum USART_TXCINTLVL_enum +-{ +- USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} USART_TXCINTLVL_t; +- +-/* Data Register Empty Interrupt level */ +-typedef enum USART_DREINTLVL_enum +-{ +- USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} USART_DREINTLVL_t; +- +-/* Character Size */ +-typedef enum USART_CHSIZE_enum +-{ +- USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ +- USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ +- USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ +- USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ +- USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +-} USART_CHSIZE_t; +- +-/* Communication Mode */ +-typedef enum USART_CMODE_enum +-{ +- USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ +- USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ +- USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ +- USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +-} USART_CMODE_t; +- +-/* Parity Mode */ +-typedef enum USART_PMODE_enum +-{ +- USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ +- USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ +- USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +-} USART_PMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-SPI - Serial Peripheral Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Serial Peripheral Interface */ +-typedef struct SPI_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t DATA; /* Data Register */ +-} SPI_t; +- +-/* SPI Mode */ +-typedef enum SPI_MODE_enum +-{ +- SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ +- SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ +- SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ +- SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +-} SPI_MODE_t; +- +-/* Prescaler setting */ +-typedef enum SPI_PRESCALER_enum +-{ +- SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ +- SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ +- SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ +- SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +-} SPI_PRESCALER_t; +- +-/* Interrupt level */ +-typedef enum SPI_INTLVL_enum +-{ +- SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} SPI_INTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-IRCOM - IR Communication Module +--------------------------------------------------------------------------- +-*/ +- +-/* IR Communication Module */ +-typedef struct IRCOM_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ +- register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +-} IRCOM_t; +- +-/* Event channel selection */ +-typedef enum IRDA_EVSEL_enum +-{ +- IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ +- IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ +- IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ +- IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +- IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ +- IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ +- IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ +- IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +-} IRDA_EVSEL_t; +- +- +-/* +--------------------------------------------------------------------------- +-AES - AES Module +--------------------------------------------------------------------------- +-*/ +- +-/* AES Module */ +-typedef struct AES_struct +-{ +- register8_t CTRL; /* AES Control Register */ +- register8_t STATUS; /* AES Status Register */ +- register8_t STATE; /* AES State Register */ +- register8_t KEY; /* AES Key Register */ +- register8_t INTCTRL; /* AES Interrupt Control Register */ +-} AES_t; +- +-/* Interrupt level */ +-typedef enum AES_INTLVL_enum +-{ +- AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} AES_INTLVL_t; +- +- +- +-/* +-========================================================================== +-IO Module Instances. Mapped to memory. +-========================================================================== +-*/ +- +-#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +-#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +-#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +-#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +-#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +-#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +-#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +-#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +-#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +-#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +-#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +-#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +-#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +-#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +-#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +-#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +-#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ +-#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +-#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +-#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +-#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +-#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ +-#define DACA (*(DAC_t *) 0x0300) /* Digitalto Analog Converter A */ +-#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ +-#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +-#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ +-#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +-#define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */ +-#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +-#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface D */ +-#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ +-#define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface F */ +-#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +-#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +-#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +-#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +-#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +-#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ +-#define PORTH (*(PORT_t *) 0x06E0) /* Port H */ +-#define PORTJ (*(PORT_t *) 0x0700) /* Port J */ +-#define PORTK (*(PORT_t *) 0x0720) /* Port K */ +-#define PORTQ (*(PORT_t *) 0x07C0) /* Port Q */ +-#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +-#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +-#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +-#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +-#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +-#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +-#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ +-#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +-#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +-#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +-#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ +-#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ +-#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +-#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ +-#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +-#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +-#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ +-#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ +-#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ +-#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ +-#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ +-#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ +-#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ +-#define TCF1 (*(TC1_t *) 0x0B40) /* Timer/Counter F1 */ +-#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ +-#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ +-#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ +-#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ +- +- +-#endif /* !defined (__ASSEMBLER__) */ +- +- +-/* ========== Flattened fully qualified IO register names ========== */ +- +-/* GPIO - General Purpose IO Registers */ +-#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +-#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +-#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +-#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +-#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +-#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +-#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +-#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +-#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +-#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +-#define GPIO_GPIORA _SFR_MEM8(0x000A) +-#define GPIO_GPIORB _SFR_MEM8(0x000B) +-#define GPIO_GPIORC _SFR_MEM8(0x000C) +-#define GPIO_GPIORD _SFR_MEM8(0x000D) +-#define GPIO_GPIORE _SFR_MEM8(0x000E) +-#define GPIO_GPIORF _SFR_MEM8(0x000F) +- +-/* Deprecated */ +-#define GPIO_GPIO0 _SFR_MEM8(0x0000) +-#define GPIO_GPIO1 _SFR_MEM8(0x0001) +-#define GPIO_GPIO2 _SFR_MEM8(0x0002) +-#define GPIO_GPIO3 _SFR_MEM8(0x0003) +-#define GPIO_GPIO4 _SFR_MEM8(0x0004) +-#define GPIO_GPIO5 _SFR_MEM8(0x0005) +-#define GPIO_GPIO6 _SFR_MEM8(0x0006) +-#define GPIO_GPIO7 _SFR_MEM8(0x0007) +-#define GPIO_GPIO8 _SFR_MEM8(0x0008) +-#define GPIO_GPIO9 _SFR_MEM8(0x0009) +-#define GPIO_GPIOA _SFR_MEM8(0x000A) +-#define GPIO_GPIOB _SFR_MEM8(0x000B) +-#define GPIO_GPIOC _SFR_MEM8(0x000C) +-#define GPIO_GPIOD _SFR_MEM8(0x000D) +-#define GPIO_GPIOE _SFR_MEM8(0x000E) +-#define GPIO_GPIOF _SFR_MEM8(0x000F) +- +-/* VPORT0 - Virtual Port 0 */ +-#define VPORT0_DIR _SFR_MEM8(0x0010) +-#define VPORT0_OUT _SFR_MEM8(0x0011) +-#define VPORT0_IN _SFR_MEM8(0x0012) +-#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) +- +-/* VPORT1 - Virtual Port 1 */ +-#define VPORT1_DIR _SFR_MEM8(0x0014) +-#define VPORT1_OUT _SFR_MEM8(0x0015) +-#define VPORT1_IN _SFR_MEM8(0x0016) +-#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) +- +-/* VPORT2 - Virtual Port 2 */ +-#define VPORT2_DIR _SFR_MEM8(0x0018) +-#define VPORT2_OUT _SFR_MEM8(0x0019) +-#define VPORT2_IN _SFR_MEM8(0x001A) +-#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) +- +-/* VPORT3 - Virtual Port 3 */ +-#define VPORT3_DIR _SFR_MEM8(0x001C) +-#define VPORT3_OUT _SFR_MEM8(0x001D) +-#define VPORT3_IN _SFR_MEM8(0x001E) +-#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) +- +-/* OCD - On-Chip Debug System */ +-#define OCD_OCDR0 _SFR_MEM8(0x002E) +-#define OCD_OCDR1 _SFR_MEM8(0x002F) +- +-/* CPU - CPU Registers */ +-#define CPU_CCP _SFR_MEM8(0x0034) +-#define CPU_RAMPD _SFR_MEM8(0x0038) +-#define CPU_RAMPX _SFR_MEM8(0x0039) +-#define CPU_RAMPY _SFR_MEM8(0x003A) +-#define CPU_RAMPZ _SFR_MEM8(0x003B) +-#define CPU_EIND _SFR_MEM8(0x003C) +-#define CPU_SPL _SFR_MEM8(0x003D) +-#define CPU_SPH _SFR_MEM8(0x003E) +-#define CPU_SREG _SFR_MEM8(0x003F) +- +-/* CLK - Clock System */ +-#define CLK_CTRL _SFR_MEM8(0x0040) +-#define CLK_PSCTRL _SFR_MEM8(0x0041) +-#define CLK_LOCK _SFR_MEM8(0x0042) +-#define CLK_RTCCTRL _SFR_MEM8(0x0043) +- +-/* SLEEP - Sleep Controller */ +-#define SLEEP_CTRL _SFR_MEM8(0x0048) +- +-/* OSC - Oscillator Control */ +-#define OSC_CTRL _SFR_MEM8(0x0050) +-#define OSC_STATUS _SFR_MEM8(0x0051) +-#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +-#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +-#define OSC_RC32KCAL _SFR_MEM8(0x0054) +-#define OSC_PLLCTRL _SFR_MEM8(0x0055) +-#define OSC_DFLLCTRL _SFR_MEM8(0x0056) +- +-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +-#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +-#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +-#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +-#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +-#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +-#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) +- +-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +-#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +-#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +-#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +-#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +-#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +-#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) +- +-/* PR - Power Reduction */ +-#define PR_PRGEN _SFR_MEM8(0x0070) +-#define PR_PRPA _SFR_MEM8(0x0071) +-#define PR_PRPB _SFR_MEM8(0x0072) +-#define PR_PRPC _SFR_MEM8(0x0073) +-#define PR_PRPD _SFR_MEM8(0x0074) +-#define PR_PRPE _SFR_MEM8(0x0075) +-#define PR_PRPF _SFR_MEM8(0x0076) +- +-/* RST - Reset Controller */ +-#define RST_STATUS _SFR_MEM8(0x0078) +-#define RST_CTRL _SFR_MEM8(0x0079) +- +-/* WDT - Watch-Dog Timer */ +-#define WDT_CTRL _SFR_MEM8(0x0080) +-#define WDT_WINCTRL _SFR_MEM8(0x0081) +-#define WDT_STATUS _SFR_MEM8(0x0082) +- +-/* MCU - MCU Control */ +-#define MCU_DEVID0 _SFR_MEM8(0x0090) +-#define MCU_DEVID1 _SFR_MEM8(0x0091) +-#define MCU_DEVID2 _SFR_MEM8(0x0092) +-#define MCU_REVID _SFR_MEM8(0x0093) +-#define MCU_JTAGUID _SFR_MEM8(0x0094) +-#define MCU_MCUCR _SFR_MEM8(0x0096) +-#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +-#define MCU_AWEXLOCK _SFR_MEM8(0x0099) +- +-/* PMIC - Programmable Interrupt Controller */ +-#define PMIC_STATUS _SFR_MEM8(0x00A0) +-#define PMIC_INTPRI _SFR_MEM8(0x00A1) +-#define PMIC_CTRL _SFR_MEM8(0x00A2) +- +-/* PORTCFG - Port Configuration */ +-#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +-#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +-#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +-#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +- +-/* AES - AES Crypto Module */ +-#define AES_CTRL _SFR_MEM8(0x00C0) +-#define AES_STATUS _SFR_MEM8(0x00C1) +-#define AES_STATE _SFR_MEM8(0x00C2) +-#define AES_KEY _SFR_MEM8(0x00C3) +-#define AES_INTCTRL _SFR_MEM8(0x00C4) +- +-/* DMA - DMA Controller */ +-#define DMA_CTRL _SFR_MEM8(0x0100) +-#define DMA_INTFLAGS _SFR_MEM8(0x0103) +-#define DMA_STATUS _SFR_MEM8(0x0104) +-#define DMA_TEMP _SFR_MEM16(0x0106) +-#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +-#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +-#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +-#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +-#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +-#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +-#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +-#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +-#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +-#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +-#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +-#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +-#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +-#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +-#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +-#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +-#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +-#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +-#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +-#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +-#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +-#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +-#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +-#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +-#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +-#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +-#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +-#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +-#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +-#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +-#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +-#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +-#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +-#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +-#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +-#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +-#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +-#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +-#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +-#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +-#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +-#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +-#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +-#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +-#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +-#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +-#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +-#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) +- +-/* EVSYS - Event System */ +-#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +-#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +-#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +-#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +-#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +-#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +-#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +-#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +-#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +-#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +-#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +-#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +-#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +-#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +-#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +-#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +-#define EVSYS_STROBE _SFR_MEM8(0x0190) +-#define EVSYS_DATA _SFR_MEM8(0x0191) +- +-/* NVM - Non Volatile Memory Controller */ +-#define NVM_ADDR0 _SFR_MEM8(0x01C0) +-#define NVM_ADDR1 _SFR_MEM8(0x01C1) +-#define NVM_ADDR2 _SFR_MEM8(0x01C2) +-#define NVM_DATA0 _SFR_MEM8(0x01C4) +-#define NVM_DATA1 _SFR_MEM8(0x01C5) +-#define NVM_DATA2 _SFR_MEM8(0x01C6) +-#define NVM_CMD _SFR_MEM8(0x01CA) +-#define NVM_CTRLA _SFR_MEM8(0x01CB) +-#define NVM_CTRLB _SFR_MEM8(0x01CC) +-#define NVM_INTCTRL _SFR_MEM8(0x01CD) +-#define NVM_STATUS _SFR_MEM8(0x01CF) +-#define NVM_LOCKBITS _SFR_MEM8(0x01D0) +- +-/* ADCA - Analog to Digital Converter A */ +-#define ADCA_CTRLA _SFR_MEM8(0x0200) +-#define ADCA_CTRLB _SFR_MEM8(0x0201) +-#define ADCA_REFCTRL _SFR_MEM8(0x0202) +-#define ADCA_EVCTRL _SFR_MEM8(0x0203) +-#define ADCA_PRESCALER _SFR_MEM8(0x0204) +-#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +-#define ADCA_CAL _SFR_MEM16(0x020C) +-#define ADCA_CH0RES _SFR_MEM16(0x0210) +-#define ADCA_CH1RES _SFR_MEM16(0x0212) +-#define ADCA_CH2RES _SFR_MEM16(0x0214) +-#define ADCA_CH3RES _SFR_MEM16(0x0216) +-#define ADCA_CMP _SFR_MEM16(0x0218) +-#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +-#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +-#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +-#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +-#define ADCA_CH0_RES _SFR_MEM16(0x0224) +-#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +-#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +-#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +-#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +-#define ADCA_CH1_RES _SFR_MEM16(0x022C) +-#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +-#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +-#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +-#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +-#define ADCA_CH2_RES _SFR_MEM16(0x0234) +-#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +-#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +-#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +-#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +-#define ADCA_CH3_RES _SFR_MEM16(0x023C) +- +-/* ADCB - Analog to Digital Converter B */ +-#define ADCB_CTRLA _SFR_MEM8(0x0240) +-#define ADCB_CTRLB _SFR_MEM8(0x0241) +-#define ADCB_REFCTRL _SFR_MEM8(0x0242) +-#define ADCB_EVCTRL _SFR_MEM8(0x0243) +-#define ADCB_PRESCALER _SFR_MEM8(0x0244) +-#define ADCB_INTFLAGS _SFR_MEM8(0x0246) +-#define ADCB_CAL _SFR_MEM16(0x024C) +-#define ADCB_CH0RES _SFR_MEM16(0x0250) +-#define ADCB_CH1RES _SFR_MEM16(0x0252) +-#define ADCB_CH2RES _SFR_MEM16(0x0254) +-#define ADCB_CH3RES _SFR_MEM16(0x0256) +-#define ADCB_CMP _SFR_MEM16(0x0258) +-#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) +-#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) +-#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) +-#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) +-#define ADCB_CH0_RES _SFR_MEM16(0x0264) +-#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) +-#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) +-#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) +-#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) +-#define ADCB_CH1_RES _SFR_MEM16(0x026C) +-#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) +-#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) +-#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) +-#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) +-#define ADCB_CH2_RES _SFR_MEM16(0x0274) +-#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) +-#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) +-#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) +-#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) +-#define ADCB_CH3_RES _SFR_MEM16(0x027C) +- +-/* DACA - Digitalto Analog Converter A */ +-#define DACA_CTRLA _SFR_MEM8(0x0300) +-#define DACA_CTRLB _SFR_MEM8(0x0301) +-#define DACA_CTRLC _SFR_MEM8(0x0302) +-#define DACA_EVCTRL _SFR_MEM8(0x0303) +-#define DACA_TIMCTRL _SFR_MEM8(0x0304) +-#define DACA_STATUS _SFR_MEM8(0x0305) +-#define DACA_GAINCAL _SFR_MEM8(0x0308) +-#define DACA_OFFSETCAL _SFR_MEM8(0x0309) +-#define DACA_CH0DATA _SFR_MEM16(0x0318) +-#define DACA_CH1DATA _SFR_MEM16(0x031A) +- +-/* DACB - Digital to Analog Converter B */ +-#define DACB_CTRLA _SFR_MEM8(0x0320) +-#define DACB_CTRLB _SFR_MEM8(0x0321) +-#define DACB_CTRLC _SFR_MEM8(0x0322) +-#define DACB_EVCTRL _SFR_MEM8(0x0323) +-#define DACB_TIMCTRL _SFR_MEM8(0x0324) +-#define DACB_STATUS _SFR_MEM8(0x0325) +-#define DACB_GAINCAL _SFR_MEM8(0x0328) +-#define DACB_OFFSETCAL _SFR_MEM8(0x0329) +-#define DACB_CH0DATA _SFR_MEM16(0x0338) +-#define DACB_CH1DATA _SFR_MEM16(0x033A) +- +-/* ACA - Analog Comparator A */ +-#define ACA_AC0CTRL _SFR_MEM8(0x0380) +-#define ACA_AC1CTRL _SFR_MEM8(0x0381) +-#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +-#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +-#define ACA_CTRLA _SFR_MEM8(0x0384) +-#define ACA_CTRLB _SFR_MEM8(0x0385) +-#define ACA_WINCTRL _SFR_MEM8(0x0386) +-#define ACA_STATUS _SFR_MEM8(0x0387) +- +-/* ACB - Analog Comparator B */ +-#define ACB_AC0CTRL _SFR_MEM8(0x0390) +-#define ACB_AC1CTRL _SFR_MEM8(0x0391) +-#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +-#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +-#define ACB_CTRLA _SFR_MEM8(0x0394) +-#define ACB_CTRLB _SFR_MEM8(0x0395) +-#define ACB_WINCTRL _SFR_MEM8(0x0396) +-#define ACB_STATUS _SFR_MEM8(0x0397) +- +-/* RTC - Real-Time Counter */ +-#define RTC_CTRL _SFR_MEM8(0x0400) +-#define RTC_STATUS _SFR_MEM8(0x0401) +-#define RTC_INTCTRL _SFR_MEM8(0x0402) +-#define RTC_INTFLAGS _SFR_MEM8(0x0403) +-#define RTC_TEMP _SFR_MEM8(0x0404) +-#define RTC_CNT _SFR_MEM16(0x0408) +-#define RTC_PER _SFR_MEM16(0x040A) +-#define RTC_COMP _SFR_MEM16(0x040C) +- +-/* EBI - External Bus Interface */ +-#define EBI_CTRL _SFR_MEM8(0x0440) +-#define EBI_SDRAMCTRLA _SFR_MEM8(0x0441) +-#define EBI_REFRESH _SFR_MEM16(0x0444) +-#define EBI_INITDLY _SFR_MEM16(0x0446) +-#define EBI_SDRAMCTRLB _SFR_MEM8(0x0448) +-#define EBI_SDRAMCTRLC _SFR_MEM8(0x0449) +-#define EBI_CS0_CTRLA _SFR_MEM8(0x0450) +-#define EBI_CS0_CTRLB _SFR_MEM8(0x0451) +-#define EBI_CS0_BASEADDR _SFR_MEM16(0x0452) +-#define EBI_CS1_CTRLA _SFR_MEM8(0x0454) +-#define EBI_CS1_CTRLB _SFR_MEM8(0x0455) +-#define EBI_CS1_BASEADDR _SFR_MEM16(0x0456) +-#define EBI_CS2_CTRLA _SFR_MEM8(0x0458) +-#define EBI_CS2_CTRLB _SFR_MEM8(0x0459) +-#define EBI_CS2_BASEADDR _SFR_MEM16(0x045A) +-#define EBI_CS3_CTRLA _SFR_MEM8(0x045C) +-#define EBI_CS3_CTRLB _SFR_MEM8(0x045D) +-#define EBI_CS3_BASEADDR _SFR_MEM16(0x045E) +- +-/* TWIC - Two-Wire Interface C */ +-#define TWIC_CTRL _SFR_MEM8(0x0480) +-#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +-#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +-#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +-#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +-#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +-#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +-#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +-#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +-#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +-#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +-#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +-#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +-#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) +- +-/* TWID - Two-Wire Interface D */ +-#define TWID_CTRL _SFR_MEM8(0x0490) +-#define TWID_MASTER_CTRLA _SFR_MEM8(0x0491) +-#define TWID_MASTER_CTRLB _SFR_MEM8(0x0492) +-#define TWID_MASTER_CTRLC _SFR_MEM8(0x0493) +-#define TWID_MASTER_STATUS _SFR_MEM8(0x0494) +-#define TWID_MASTER_BAUD _SFR_MEM8(0x0495) +-#define TWID_MASTER_ADDR _SFR_MEM8(0x0496) +-#define TWID_MASTER_DATA _SFR_MEM8(0x0497) +-#define TWID_SLAVE_CTRLA _SFR_MEM8(0x0498) +-#define TWID_SLAVE_CTRLB _SFR_MEM8(0x0499) +-#define TWID_SLAVE_STATUS _SFR_MEM8(0x049A) +-#define TWID_SLAVE_ADDR _SFR_MEM8(0x049B) +-#define TWID_SLAVE_DATA _SFR_MEM8(0x049C) +-#define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D) +- +-/* TWIE - Two-Wire Interface E */ +-#define TWIE_CTRL _SFR_MEM8(0x04A0) +-#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +-#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +-#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +-#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +-#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +-#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +-#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +-#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +-#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +-#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +-#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +-#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +-#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) +- +-/* TWIF - Two-Wire Interface F */ +-#define TWIF_CTRL _SFR_MEM8(0x04B0) +-#define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1) +-#define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2) +-#define TWIF_MASTER_CTRLC _SFR_MEM8(0x04B3) +-#define TWIF_MASTER_STATUS _SFR_MEM8(0x04B4) +-#define TWIF_MASTER_BAUD _SFR_MEM8(0x04B5) +-#define TWIF_MASTER_ADDR _SFR_MEM8(0x04B6) +-#define TWIF_MASTER_DATA _SFR_MEM8(0x04B7) +-#define TWIF_SLAVE_CTRLA _SFR_MEM8(0x04B8) +-#define TWIF_SLAVE_CTRLB _SFR_MEM8(0x04B9) +-#define TWIF_SLAVE_STATUS _SFR_MEM8(0x04BA) +-#define TWIF_SLAVE_ADDR _SFR_MEM8(0x04BB) +-#define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC) +-#define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD) +- +-/* PORTA - Port A */ +-#define PORTA_DIR _SFR_MEM8(0x0600) +-#define PORTA_DIRSET _SFR_MEM8(0x0601) +-#define PORTA_DIRCLR _SFR_MEM8(0x0602) +-#define PORTA_DIRTGL _SFR_MEM8(0x0603) +-#define PORTA_OUT _SFR_MEM8(0x0604) +-#define PORTA_OUTSET _SFR_MEM8(0x0605) +-#define PORTA_OUTCLR _SFR_MEM8(0x0606) +-#define PORTA_OUTTGL _SFR_MEM8(0x0607) +-#define PORTA_IN _SFR_MEM8(0x0608) +-#define PORTA_INTCTRL _SFR_MEM8(0x0609) +-#define PORTA_INT0MASK _SFR_MEM8(0x060A) +-#define PORTA_INT1MASK _SFR_MEM8(0x060B) +-#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +-#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +-#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +-#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +-#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +-#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +-#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +-#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +-#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) +- +-/* PORTB - Port B */ +-#define PORTB_DIR _SFR_MEM8(0x0620) +-#define PORTB_DIRSET _SFR_MEM8(0x0621) +-#define PORTB_DIRCLR _SFR_MEM8(0x0622) +-#define PORTB_DIRTGL _SFR_MEM8(0x0623) +-#define PORTB_OUT _SFR_MEM8(0x0624) +-#define PORTB_OUTSET _SFR_MEM8(0x0625) +-#define PORTB_OUTCLR _SFR_MEM8(0x0626) +-#define PORTB_OUTTGL _SFR_MEM8(0x0627) +-#define PORTB_IN _SFR_MEM8(0x0628) +-#define PORTB_INTCTRL _SFR_MEM8(0x0629) +-#define PORTB_INT0MASK _SFR_MEM8(0x062A) +-#define PORTB_INT1MASK _SFR_MEM8(0x062B) +-#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +-#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +-#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +-#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +-#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +-#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +-#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +-#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +-#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) +- +-/* PORTC - Port C */ +-#define PORTC_DIR _SFR_MEM8(0x0640) +-#define PORTC_DIRSET _SFR_MEM8(0x0641) +-#define PORTC_DIRCLR _SFR_MEM8(0x0642) +-#define PORTC_DIRTGL _SFR_MEM8(0x0643) +-#define PORTC_OUT _SFR_MEM8(0x0644) +-#define PORTC_OUTSET _SFR_MEM8(0x0645) +-#define PORTC_OUTCLR _SFR_MEM8(0x0646) +-#define PORTC_OUTTGL _SFR_MEM8(0x0647) +-#define PORTC_IN _SFR_MEM8(0x0648) +-#define PORTC_INTCTRL _SFR_MEM8(0x0649) +-#define PORTC_INT0MASK _SFR_MEM8(0x064A) +-#define PORTC_INT1MASK _SFR_MEM8(0x064B) +-#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +-#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +-#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +-#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +-#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +-#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +-#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +-#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +-#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) +- +-/* PORTD - Port D */ +-#define PORTD_DIR _SFR_MEM8(0x0660) +-#define PORTD_DIRSET _SFR_MEM8(0x0661) +-#define PORTD_DIRCLR _SFR_MEM8(0x0662) +-#define PORTD_DIRTGL _SFR_MEM8(0x0663) +-#define PORTD_OUT _SFR_MEM8(0x0664) +-#define PORTD_OUTSET _SFR_MEM8(0x0665) +-#define PORTD_OUTCLR _SFR_MEM8(0x0666) +-#define PORTD_OUTTGL _SFR_MEM8(0x0667) +-#define PORTD_IN _SFR_MEM8(0x0668) +-#define PORTD_INTCTRL _SFR_MEM8(0x0669) +-#define PORTD_INT0MASK _SFR_MEM8(0x066A) +-#define PORTD_INT1MASK _SFR_MEM8(0x066B) +-#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +-#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +-#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +-#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +-#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +-#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +-#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +-#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +-#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) +- +-/* PORTE - Port E */ +-#define PORTE_DIR _SFR_MEM8(0x0680) +-#define PORTE_DIRSET _SFR_MEM8(0x0681) +-#define PORTE_DIRCLR _SFR_MEM8(0x0682) +-#define PORTE_DIRTGL _SFR_MEM8(0x0683) +-#define PORTE_OUT _SFR_MEM8(0x0684) +-#define PORTE_OUTSET _SFR_MEM8(0x0685) +-#define PORTE_OUTCLR _SFR_MEM8(0x0686) +-#define PORTE_OUTTGL _SFR_MEM8(0x0687) +-#define PORTE_IN _SFR_MEM8(0x0688) +-#define PORTE_INTCTRL _SFR_MEM8(0x0689) +-#define PORTE_INT0MASK _SFR_MEM8(0x068A) +-#define PORTE_INT1MASK _SFR_MEM8(0x068B) +-#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +-#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +-#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +-#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +-#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +-#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +-#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +-#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +-#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) +- +-/* PORTF - Port F */ +-#define PORTF_DIR _SFR_MEM8(0x06A0) +-#define PORTF_DIRSET _SFR_MEM8(0x06A1) +-#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +-#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +-#define PORTF_OUT _SFR_MEM8(0x06A4) +-#define PORTF_OUTSET _SFR_MEM8(0x06A5) +-#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +-#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +-#define PORTF_IN _SFR_MEM8(0x06A8) +-#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +-#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +-#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +-#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +-#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +-#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +-#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +-#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +-#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +-#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +-#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +-#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) +- +-/* PORTH - Port H */ +-#define PORTH_DIR _SFR_MEM8(0x06E0) +-#define PORTH_DIRSET _SFR_MEM8(0x06E1) +-#define PORTH_DIRCLR _SFR_MEM8(0x06E2) +-#define PORTH_DIRTGL _SFR_MEM8(0x06E3) +-#define PORTH_OUT _SFR_MEM8(0x06E4) +-#define PORTH_OUTSET _SFR_MEM8(0x06E5) +-#define PORTH_OUTCLR _SFR_MEM8(0x06E6) +-#define PORTH_OUTTGL _SFR_MEM8(0x06E7) +-#define PORTH_IN _SFR_MEM8(0x06E8) +-#define PORTH_INTCTRL _SFR_MEM8(0x06E9) +-#define PORTH_INT0MASK _SFR_MEM8(0x06EA) +-#define PORTH_INT1MASK _SFR_MEM8(0x06EB) +-#define PORTH_INTFLAGS _SFR_MEM8(0x06EC) +-#define PORTH_PIN0CTRL _SFR_MEM8(0x06F0) +-#define PORTH_PIN1CTRL _SFR_MEM8(0x06F1) +-#define PORTH_PIN2CTRL _SFR_MEM8(0x06F2) +-#define PORTH_PIN3CTRL _SFR_MEM8(0x06F3) +-#define PORTH_PIN4CTRL _SFR_MEM8(0x06F4) +-#define PORTH_PIN5CTRL _SFR_MEM8(0x06F5) +-#define PORTH_PIN6CTRL _SFR_MEM8(0x06F6) +-#define PORTH_PIN7CTRL _SFR_MEM8(0x06F7) +- +-/* PORTJ - Port J */ +-#define PORTJ_DIR _SFR_MEM8(0x0700) +-#define PORTJ_DIRSET _SFR_MEM8(0x0701) +-#define PORTJ_DIRCLR _SFR_MEM8(0x0702) +-#define PORTJ_DIRTGL _SFR_MEM8(0x0703) +-#define PORTJ_OUT _SFR_MEM8(0x0704) +-#define PORTJ_OUTSET _SFR_MEM8(0x0705) +-#define PORTJ_OUTCLR _SFR_MEM8(0x0706) +-#define PORTJ_OUTTGL _SFR_MEM8(0x0707) +-#define PORTJ_IN _SFR_MEM8(0x0708) +-#define PORTJ_INTCTRL _SFR_MEM8(0x0709) +-#define PORTJ_INT0MASK _SFR_MEM8(0x070A) +-#define PORTJ_INT1MASK _SFR_MEM8(0x070B) +-#define PORTJ_INTFLAGS _SFR_MEM8(0x070C) +-#define PORTJ_PIN0CTRL _SFR_MEM8(0x0710) +-#define PORTJ_PIN1CTRL _SFR_MEM8(0x0711) +-#define PORTJ_PIN2CTRL _SFR_MEM8(0x0712) +-#define PORTJ_PIN3CTRL _SFR_MEM8(0x0713) +-#define PORTJ_PIN4CTRL _SFR_MEM8(0x0714) +-#define PORTJ_PIN5CTRL _SFR_MEM8(0x0715) +-#define PORTJ_PIN6CTRL _SFR_MEM8(0x0716) +-#define PORTJ_PIN7CTRL _SFR_MEM8(0x0717) +- +-/* PORTK - Port K */ +-#define PORTK_DIR _SFR_MEM8(0x0720) +-#define PORTK_DIRSET _SFR_MEM8(0x0721) +-#define PORTK_DIRCLR _SFR_MEM8(0x0722) +-#define PORTK_DIRTGL _SFR_MEM8(0x0723) +-#define PORTK_OUT _SFR_MEM8(0x0724) +-#define PORTK_OUTSET _SFR_MEM8(0x0725) +-#define PORTK_OUTCLR _SFR_MEM8(0x0726) +-#define PORTK_OUTTGL _SFR_MEM8(0x0727) +-#define PORTK_IN _SFR_MEM8(0x0728) +-#define PORTK_INTCTRL _SFR_MEM8(0x0729) +-#define PORTK_INT0MASK _SFR_MEM8(0x072A) +-#define PORTK_INT1MASK _SFR_MEM8(0x072B) +-#define PORTK_INTFLAGS _SFR_MEM8(0x072C) +-#define PORTK_PIN0CTRL _SFR_MEM8(0x0730) +-#define PORTK_PIN1CTRL _SFR_MEM8(0x0731) +-#define PORTK_PIN2CTRL _SFR_MEM8(0x0732) +-#define PORTK_PIN3CTRL _SFR_MEM8(0x0733) +-#define PORTK_PIN4CTRL _SFR_MEM8(0x0734) +-#define PORTK_PIN5CTRL _SFR_MEM8(0x0735) +-#define PORTK_PIN6CTRL _SFR_MEM8(0x0736) +-#define PORTK_PIN7CTRL _SFR_MEM8(0x0737) +- +-/* PORTQ - Port Q */ +-#define PORTQ_DIR _SFR_MEM8(0x07C0) +-#define PORTQ_DIRSET _SFR_MEM8(0x07C1) +-#define PORTQ_DIRCLR _SFR_MEM8(0x07C2) +-#define PORTQ_DIRTGL _SFR_MEM8(0x07C3) +-#define PORTQ_OUT _SFR_MEM8(0x07C4) +-#define PORTQ_OUTSET _SFR_MEM8(0x07C5) +-#define PORTQ_OUTCLR _SFR_MEM8(0x07C6) +-#define PORTQ_OUTTGL _SFR_MEM8(0x07C7) +-#define PORTQ_IN _SFR_MEM8(0x07C8) +-#define PORTQ_INTCTRL _SFR_MEM8(0x07C9) +-#define PORTQ_INT0MASK _SFR_MEM8(0x07CA) +-#define PORTQ_INT1MASK _SFR_MEM8(0x07CB) +-#define PORTQ_INTFLAGS _SFR_MEM8(0x07CC) +-#define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0) +-#define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1) +-#define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2) +-#define PORTQ_PIN3CTRL _SFR_MEM8(0x07D3) +-#define PORTQ_PIN4CTRL _SFR_MEM8(0x07D4) +-#define PORTQ_PIN5CTRL _SFR_MEM8(0x07D5) +-#define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6) +-#define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7) +- +-/* PORTR - Port R */ +-#define PORTR_DIR _SFR_MEM8(0x07E0) +-#define PORTR_DIRSET _SFR_MEM8(0x07E1) +-#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +-#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +-#define PORTR_OUT _SFR_MEM8(0x07E4) +-#define PORTR_OUTSET _SFR_MEM8(0x07E5) +-#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +-#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +-#define PORTR_IN _SFR_MEM8(0x07E8) +-#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +-#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +-#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +-#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +-#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +-#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +-#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +-#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +-#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +-#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +-#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +-#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) +- +-/* TCC0 - Timer/Counter C0 */ +-#define TCC0_CTRLA _SFR_MEM8(0x0800) +-#define TCC0_CTRLB _SFR_MEM8(0x0801) +-#define TCC0_CTRLC _SFR_MEM8(0x0802) +-#define TCC0_CTRLD _SFR_MEM8(0x0803) +-#define TCC0_CTRLE _SFR_MEM8(0x0804) +-#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +-#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +-#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +-#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +-#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +-#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +-#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +-#define TCC0_TEMP _SFR_MEM8(0x080F) +-#define TCC0_CNT _SFR_MEM16(0x0820) +-#define TCC0_PER _SFR_MEM16(0x0826) +-#define TCC0_CCA _SFR_MEM16(0x0828) +-#define TCC0_CCB _SFR_MEM16(0x082A) +-#define TCC0_CCC _SFR_MEM16(0x082C) +-#define TCC0_CCD _SFR_MEM16(0x082E) +-#define TCC0_PERBUF _SFR_MEM16(0x0836) +-#define TCC0_CCABUF _SFR_MEM16(0x0838) +-#define TCC0_CCBBUF _SFR_MEM16(0x083A) +-#define TCC0_CCCBUF _SFR_MEM16(0x083C) +-#define TCC0_CCDBUF _SFR_MEM16(0x083E) +- +-/* TCC1 - Timer/Counter C1 */ +-#define TCC1_CTRLA _SFR_MEM8(0x0840) +-#define TCC1_CTRLB _SFR_MEM8(0x0841) +-#define TCC1_CTRLC _SFR_MEM8(0x0842) +-#define TCC1_CTRLD _SFR_MEM8(0x0843) +-#define TCC1_CTRLE _SFR_MEM8(0x0844) +-#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +-#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +-#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +-#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +-#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +-#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +-#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +-#define TCC1_TEMP _SFR_MEM8(0x084F) +-#define TCC1_CNT _SFR_MEM16(0x0860) +-#define TCC1_PER _SFR_MEM16(0x0866) +-#define TCC1_CCA _SFR_MEM16(0x0868) +-#define TCC1_CCB _SFR_MEM16(0x086A) +-#define TCC1_PERBUF _SFR_MEM16(0x0876) +-#define TCC1_CCABUF _SFR_MEM16(0x0878) +-#define TCC1_CCBBUF _SFR_MEM16(0x087A) +- +-/* AWEXC - Advanced Waveform Extension C */ +-#define AWEXC_CTRL _SFR_MEM8(0x0880) +-#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +-#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +-#define AWEXC_STATUS _SFR_MEM8(0x0884) +-#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +-#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +-#define AWEXC_DTLS _SFR_MEM8(0x0888) +-#define AWEXC_DTHS _SFR_MEM8(0x0889) +-#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +-#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +-#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) +- +-/* HIRESC - High-Resolution Extension C */ +-#define HIRESC_CTRLA _SFR_MEM8(0x0890) +- +-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +-#define USARTC0_DATA _SFR_MEM8(0x08A0) +-#define USARTC0_STATUS _SFR_MEM8(0x08A1) +-#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +-#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +-#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +-#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +-#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) +- +-/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ +-#define USARTC1_DATA _SFR_MEM8(0x08B0) +-#define USARTC1_STATUS _SFR_MEM8(0x08B1) +-#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +-#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +-#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +-#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +-#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) +- +-/* SPIC - Serial Peripheral Interface C */ +-#define SPIC_CTRL _SFR_MEM8(0x08C0) +-#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +-#define SPIC_STATUS _SFR_MEM8(0x08C2) +-#define SPIC_DATA _SFR_MEM8(0x08C3) +- +-/* IRCOM - IR Communication Module */ +-#define IRCOM_CTRL _SFR_MEM8(0x08F8) +-#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +-#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) +- +-/* TCD0 - Timer/Counter D0 */ +-#define TCD0_CTRLA _SFR_MEM8(0x0900) +-#define TCD0_CTRLB _SFR_MEM8(0x0901) +-#define TCD0_CTRLC _SFR_MEM8(0x0902) +-#define TCD0_CTRLD _SFR_MEM8(0x0903) +-#define TCD0_CTRLE _SFR_MEM8(0x0904) +-#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +-#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +-#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +-#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +-#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +-#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +-#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +-#define TCD0_TEMP _SFR_MEM8(0x090F) +-#define TCD0_CNT _SFR_MEM16(0x0920) +-#define TCD0_PER _SFR_MEM16(0x0926) +-#define TCD0_CCA _SFR_MEM16(0x0928) +-#define TCD0_CCB _SFR_MEM16(0x092A) +-#define TCD0_CCC _SFR_MEM16(0x092C) +-#define TCD0_CCD _SFR_MEM16(0x092E) +-#define TCD0_PERBUF _SFR_MEM16(0x0936) +-#define TCD0_CCABUF _SFR_MEM16(0x0938) +-#define TCD0_CCBBUF _SFR_MEM16(0x093A) +-#define TCD0_CCCBUF _SFR_MEM16(0x093C) +-#define TCD0_CCDBUF _SFR_MEM16(0x093E) +- +-/* TCD1 - Timer/Counter D1 */ +-#define TCD1_CTRLA _SFR_MEM8(0x0940) +-#define TCD1_CTRLB _SFR_MEM8(0x0941) +-#define TCD1_CTRLC _SFR_MEM8(0x0942) +-#define TCD1_CTRLD _SFR_MEM8(0x0943) +-#define TCD1_CTRLE _SFR_MEM8(0x0944) +-#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +-#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +-#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +-#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +-#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +-#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +-#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +-#define TCD1_TEMP _SFR_MEM8(0x094F) +-#define TCD1_CNT _SFR_MEM16(0x0960) +-#define TCD1_PER _SFR_MEM16(0x0966) +-#define TCD1_CCA _SFR_MEM16(0x0968) +-#define TCD1_CCB _SFR_MEM16(0x096A) +-#define TCD1_PERBUF _SFR_MEM16(0x0976) +-#define TCD1_CCABUF _SFR_MEM16(0x0978) +-#define TCD1_CCBBUF _SFR_MEM16(0x097A) +- +-/* HIRESD - High-Resolution Extension D */ +-#define HIRESD_CTRLA _SFR_MEM8(0x0990) +- +-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +-#define USARTD0_DATA _SFR_MEM8(0x09A0) +-#define USARTD0_STATUS _SFR_MEM8(0x09A1) +-#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +-#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +-#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +-#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +-#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) +- +-/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ +-#define USARTD1_DATA _SFR_MEM8(0x09B0) +-#define USARTD1_STATUS _SFR_MEM8(0x09B1) +-#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +-#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +-#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +-#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +-#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) +- +-/* SPID - Serial Peripheral Interface D */ +-#define SPID_CTRL _SFR_MEM8(0x09C0) +-#define SPID_INTCTRL _SFR_MEM8(0x09C1) +-#define SPID_STATUS _SFR_MEM8(0x09C2) +-#define SPID_DATA _SFR_MEM8(0x09C3) +- +-/* TCE0 - Timer/Counter E0 */ +-#define TCE0_CTRLA _SFR_MEM8(0x0A00) +-#define TCE0_CTRLB _SFR_MEM8(0x0A01) +-#define TCE0_CTRLC _SFR_MEM8(0x0A02) +-#define TCE0_CTRLD _SFR_MEM8(0x0A03) +-#define TCE0_CTRLE _SFR_MEM8(0x0A04) +-#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +-#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +-#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +-#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +-#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +-#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +-#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +-#define TCE0_TEMP _SFR_MEM8(0x0A0F) +-#define TCE0_CNT _SFR_MEM16(0x0A20) +-#define TCE0_PER _SFR_MEM16(0x0A26) +-#define TCE0_CCA _SFR_MEM16(0x0A28) +-#define TCE0_CCB _SFR_MEM16(0x0A2A) +-#define TCE0_CCC _SFR_MEM16(0x0A2C) +-#define TCE0_CCD _SFR_MEM16(0x0A2E) +-#define TCE0_PERBUF _SFR_MEM16(0x0A36) +-#define TCE0_CCABUF _SFR_MEM16(0x0A38) +-#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +-#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +-#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) +- +-/* TCE1 - Timer/Counter E1 */ +-#define TCE1_CTRLA _SFR_MEM8(0x0A40) +-#define TCE1_CTRLB _SFR_MEM8(0x0A41) +-#define TCE1_CTRLC _SFR_MEM8(0x0A42) +-#define TCE1_CTRLD _SFR_MEM8(0x0A43) +-#define TCE1_CTRLE _SFR_MEM8(0x0A44) +-#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) +-#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) +-#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) +-#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) +-#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) +-#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) +-#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) +-#define TCE1_TEMP _SFR_MEM8(0x0A4F) +-#define TCE1_CNT _SFR_MEM16(0x0A60) +-#define TCE1_PER _SFR_MEM16(0x0A66) +-#define TCE1_CCA _SFR_MEM16(0x0A68) +-#define TCE1_CCB _SFR_MEM16(0x0A6A) +-#define TCE1_PERBUF _SFR_MEM16(0x0A76) +-#define TCE1_CCABUF _SFR_MEM16(0x0A78) +-#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) +- +-/* AWEXE - Advanced Waveform Extension E */ +-#define AWEXE_CTRL _SFR_MEM8(0x0A80) +-#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +-#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +-#define AWEXE_STATUS _SFR_MEM8(0x0A84) +-#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +-#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +-#define AWEXE_DTLS _SFR_MEM8(0x0A88) +-#define AWEXE_DTHS _SFR_MEM8(0x0A89) +-#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +-#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +-#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) +- +-/* HIRESE - High-Resolution Extension E */ +-#define HIRESE_CTRLA _SFR_MEM8(0x0A90) +- +-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +-#define USARTE0_DATA _SFR_MEM8(0x0AA0) +-#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +-#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +-#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +-#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +-#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +-#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) +- +-/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ +-#define USARTE1_DATA _SFR_MEM8(0x0AB0) +-#define USARTE1_STATUS _SFR_MEM8(0x0AB1) +-#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) +-#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) +-#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) +-#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) +-#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) +- +-/* SPIE - Serial Peripheral Interface E */ +-#define SPIE_CTRL _SFR_MEM8(0x0AC0) +-#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +-#define SPIE_STATUS _SFR_MEM8(0x0AC2) +-#define SPIE_DATA _SFR_MEM8(0x0AC3) +- +-/* TCF0 - Timer/Counter F0 */ +-#define TCF0_CTRLA _SFR_MEM8(0x0B00) +-#define TCF0_CTRLB _SFR_MEM8(0x0B01) +-#define TCF0_CTRLC _SFR_MEM8(0x0B02) +-#define TCF0_CTRLD _SFR_MEM8(0x0B03) +-#define TCF0_CTRLE _SFR_MEM8(0x0B04) +-#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +-#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +-#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +-#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +-#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +-#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +-#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +-#define TCF0_TEMP _SFR_MEM8(0x0B0F) +-#define TCF0_CNT _SFR_MEM16(0x0B20) +-#define TCF0_PER _SFR_MEM16(0x0B26) +-#define TCF0_CCA _SFR_MEM16(0x0B28) +-#define TCF0_CCB _SFR_MEM16(0x0B2A) +-#define TCF0_CCC _SFR_MEM16(0x0B2C) +-#define TCF0_CCD _SFR_MEM16(0x0B2E) +-#define TCF0_PERBUF _SFR_MEM16(0x0B36) +-#define TCF0_CCABUF _SFR_MEM16(0x0B38) +-#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +-#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +-#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) +- +-/* TCF1 - Timer/Counter F1 */ +-#define TCF1_CTRLA _SFR_MEM8(0x0B40) +-#define TCF1_CTRLB _SFR_MEM8(0x0B41) +-#define TCF1_CTRLC _SFR_MEM8(0x0B42) +-#define TCF1_CTRLD _SFR_MEM8(0x0B43) +-#define TCF1_CTRLE _SFR_MEM8(0x0B44) +-#define TCF1_INTCTRLA _SFR_MEM8(0x0B46) +-#define TCF1_INTCTRLB _SFR_MEM8(0x0B47) +-#define TCF1_CTRLFCLR _SFR_MEM8(0x0B48) +-#define TCF1_CTRLFSET _SFR_MEM8(0x0B49) +-#define TCF1_CTRLGCLR _SFR_MEM8(0x0B4A) +-#define TCF1_CTRLGSET _SFR_MEM8(0x0B4B) +-#define TCF1_INTFLAGS _SFR_MEM8(0x0B4C) +-#define TCF1_TEMP _SFR_MEM8(0x0B4F) +-#define TCF1_CNT _SFR_MEM16(0x0B60) +-#define TCF1_PER _SFR_MEM16(0x0B66) +-#define TCF1_CCA _SFR_MEM16(0x0B68) +-#define TCF1_CCB _SFR_MEM16(0x0B6A) +-#define TCF1_PERBUF _SFR_MEM16(0x0B76) +-#define TCF1_CCABUF _SFR_MEM16(0x0B78) +-#define TCF1_CCBBUF _SFR_MEM16(0x0B7A) +- +-/* HIRESF - High-Resolution Extension F */ +-#define HIRESF_CTRLA _SFR_MEM8(0x0B90) +- +-/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ +-#define USARTF0_DATA _SFR_MEM8(0x0BA0) +-#define USARTF0_STATUS _SFR_MEM8(0x0BA1) +-#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) +-#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) +-#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) +-#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) +-#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) +- +-/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ +-#define USARTF1_DATA _SFR_MEM8(0x0BB0) +-#define USARTF1_STATUS _SFR_MEM8(0x0BB1) +-#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) +-#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) +-#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) +-#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) +-#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) +- +-/* SPIF - Serial Peripheral Interface F */ +-#define SPIF_CTRL _SFR_MEM8(0x0BC0) +-#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) +-#define SPIF_STATUS _SFR_MEM8(0x0BC2) +-#define SPIF_DATA _SFR_MEM8(0x0BC3) +- +- +- +-/*================== Bitfield Definitions ================== */ +- +-/* XOCD - On-Chip Debug System */ +-/* OCD.OCDR1 bit masks and bit positions */ +-#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +-#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ +- +- +-/* CPU - CPU */ +-/* CPU.CCP bit masks and bit positions */ +-#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +-#define CPU_CCP_gp 0 /* CCP signature group position. */ +-#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +-#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +-#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +-#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +-#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +-#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +-#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +-#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +-#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +-#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +-#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +-#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +-#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +-#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +-#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +-#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ +- +- +-/* CPU.SREG bit masks and bit positions */ +-#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +-#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ +- +-#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +-#define CPU_T_bp 6 /* Transfer Bit bit position. */ +- +-#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +-#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +- +-#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +-#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +- +-#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +-#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +- +-#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +-#define CPU_N_bp 2 /* Negative Flag bit position. */ +- +-#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +-#define CPU_Z_bp 1 /* Zero Flag bit position. */ +- +-#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +-#define CPU_C_bp 0 /* Carry Flag bit position. */ +- +- +-/* CLK - Clock System */ +-/* CLK.CTRL bit masks and bit positions */ +-#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +-#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +-#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +-#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +-#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +-#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +-#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +-#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ +- +- +-/* CLK.PSCTRL bit masks and bit positions */ +-#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +-#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +-#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +-#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +-#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +-#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +-#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +-#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +-#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +-#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +-#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +-#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ +- +-#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +-#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +-#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +-#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +-#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +-#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ +- +- +-/* CLK.LOCK bit masks and bit positions */ +-#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +-#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ +- +- +-/* CLK.RTCCTRL bit masks and bit positions */ +-#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +-#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +-#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +-#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +-#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +-#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +-#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +-#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ +- +-#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +-#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ +- +- +-/* PR.PRGEN bit masks and bit positions */ +-#define PR_AES_bm 0x10 /* AES bit mask. */ +-#define PR_AES_bp 4 /* AES bit position. */ +- +-#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +-#define PR_EBI_bp 3 /* External Bus Interface bit position. */ +- +-#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +-#define PR_RTC_bp 2 /* Real-time Counter bit position. */ +- +-#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +-#define PR_EVSYS_bp 1 /* Event System bit position. */ +- +-#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +-#define PR_DMA_bp 0 /* DMA-Controller bit position. */ +- +- +-/* PR.PRPA bit masks and bit positions */ +-#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +-#define PR_DAC_bp 2 /* Port A DAC bit position. */ +- +-#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +-#define PR_ADC_bp 1 /* Port A ADC bit position. */ +- +-#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +-#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ +- +- +-/* PR.PRPB bit masks and bit positions */ +-/* PR_DAC_bm Predefined. */ +-/* PR_DAC_bp Predefined. */ +- +-/* PR_ADC_bm Predefined. */ +-/* PR_ADC_bp Predefined. */ +- +-/* PR_AC_bm Predefined. */ +-/* PR_AC_bp Predefined. */ +- +- +-/* PR.PRPC bit masks and bit positions */ +-#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +-#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ +- +-#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +-#define PR_USART1_bp 5 /* Port C USART1 bit position. */ +- +-#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +-#define PR_USART0_bp 4 /* Port C USART0 bit position. */ +- +-#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +-#define PR_SPI_bp 3 /* Port C SPI bit position. */ +- +-#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +-#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ +- +-#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +-#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ +- +-#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +-#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ +- +- +-/* PR.PRPD bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* PR.PRPE bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* PR.PRPF bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* SLEEP - Sleep Controller */ +-/* SLEEP.CTRL bit masks and bit positions */ +-#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +-#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +-#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +-#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +-#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +-#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +-#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +-#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ +- +-#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +-#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ +- +- +-/* OSC - Oscillator */ +-/* OSC.CTRL bit masks and bit positions */ +-#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +-#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ +- +-#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +-#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ +- +-#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ +- +- +-/* OSC.STATUS bit masks and bit positions */ +-#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +-#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ +- +-#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +-#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ +- +-#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ +- +- +-/* OSC.XOSCCTRL bit masks and bit positions */ +-#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +-#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +-#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +-#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +-#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +-#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ +- +-#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +-#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ +- +-#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +-#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +-#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +-#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +-#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +-#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +-#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +-#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +-#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +-#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +- +- +-/* OSC.XOSCFAIL bit masks and bit positions */ +-#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +-#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ +- +-#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +-#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ +- +- +-/* OSC.PLLCTRL bit masks and bit positions */ +-#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +-#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +-#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +-#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +-#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +-#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ +- +-#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +-#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +-#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +-#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +-#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +-#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +-#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +-#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +-#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +-#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +-#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +-#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ +- +- +-/* OSC.DFLLCTRL bit masks and bit positions */ +-#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +-#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ +- +-#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +-#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ +- +- +-/* DFLL - DFLL */ +-/* DFLL.CTRL bit masks and bit positions */ +-#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +-#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ +- +- +-/* DFLL.CALA bit masks and bit positions */ +-#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +-#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +-#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +-#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +-#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +-#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +-#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +-#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +-#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +-#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +-#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +-#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +-#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +-#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +-#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +-#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ +- +- +-/* DFLL.CALB bit masks and bit positions */ +-#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +-#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +-#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +-#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +-#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +-#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +-#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +-#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +-#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +-#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +-#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +-#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +-#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +-#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ +- +- +-/* RST - Reset */ +-/* RST.STATUS bit masks and bit positions */ +-#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +-#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ +- +-#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +-#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ +- +-#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +-#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ +- +-#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +-#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ +- +-#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +-#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ +- +-#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +-#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ +- +-#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +-#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ +- +- +-/* RST.CTRL bit masks and bit positions */ +-#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +-#define RST_SWRST_bp 0 /* Software Reset bit position. */ +- +- +-/* WDT - Watch-Dog Timer */ +-/* WDT.CTRL bit masks and bit positions */ +-#define WDT_PER_gm 0x3C /* Period group mask. */ +-#define WDT_PER_gp 2 /* Period group position. */ +-#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +-#define WDT_PER0_bp 2 /* Period bit 0 position. */ +-#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +-#define WDT_PER1_bp 3 /* Period bit 1 position. */ +-#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +-#define WDT_PER2_bp 4 /* Period bit 2 position. */ +-#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +-#define WDT_PER3_bp 5 /* Period bit 3 position. */ +- +-#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +-#define WDT_ENABLE_bp 1 /* Enable bit position. */ +- +-#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +-#define WDT_CEN_bp 0 /* Change Enable bit position. */ +- +- +-/* WDT.WINCTRL bit masks and bit positions */ +-#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +-#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +-#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +-#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +-#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +-#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +-#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +-#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +-#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +-#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ +- +-#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +-#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ +- +-#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +-#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ +- +- +-/* WDT.STATUS bit masks and bit positions */ +-#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +-#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +- +- +-/* MCU - MCU Control */ +-/* MCU.MCUCR bit masks and bit positions */ +-#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +-#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ +- +- +-/* MCU.EVSYSLOCK bit masks and bit positions */ +-#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +-#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ +- +-#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +-#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ +- +- +-/* MCU.AWEXLOCK bit masks and bit positions */ +-#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +-#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ +- +-#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +-#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ +- +- +-/* PMIC - Programmable Multi-level Interrupt Controller */ +-/* PMIC.STATUS bit masks and bit positions */ +-#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +-#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ +- +-#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +-#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ +- +-#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +-#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ +- +-#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +-#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ +- +- +-/* PMIC.CTRL bit masks and bit positions */ +-#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +-#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ +- +-#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +-#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ +- +-#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +-#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ +- +-#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +-#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ +- +-#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +-#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ +- +- +-/* DMA - DMA Controller */ +-/* DMA_CH.CTRLA bit masks and bit positions */ +-#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +-#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ +- +-#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +-#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ +- +-#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +-#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ +- +-#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +-#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ +- +-#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +-#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ +- +-#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +-#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +-#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +-#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +-#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +-#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ +- +- +-/* DMA_CH.CTRLB bit masks and bit positions */ +-#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +-#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ +- +-#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +-#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ +- +-#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +-#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ +- +-#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +-#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +-#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +-#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +-#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +-#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ +- +-#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +-#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +-#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +-#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +-#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +-#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ +- +- +-/* DMA_CH.ADDRCTRL bit masks and bit positions */ +-#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +-#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +-#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +-#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +-#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +-#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ +- +-#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +-#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +-#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +-#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +-#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +-#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ +- +-#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +-#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +-#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +-#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +-#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +-#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ +- +-#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +-#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +-#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +-#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +-#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +-#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ +- +- +-/* DMA_CH.TRIGSRC bit masks and bit positions */ +-#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +-#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +-#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +-#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +-#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +-#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +-#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +-#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +-#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +-#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +-#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +-#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +-#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +-#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +-#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +-#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +-#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +-#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ +- +- +-/* DMA.CTRL bit masks and bit positions */ +-#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +-#define DMA_ENABLE_bp 7 /* Enable bit position. */ +- +-#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +-#define DMA_RESET_bp 6 /* Software Reset bit position. */ +- +-#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +-#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +-#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +-#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +-#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +-#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ +- +-#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +-#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +-#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +-#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +-#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +-#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ +- +- +-/* DMA.INTFLAGS bit masks and bit positions */ +-#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ +- +- +-/* DMA.STATUS bit masks and bit positions */ +-#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +-#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ +- +-#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +-#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ +- +-#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +-#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ +- +-#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +-#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ +- +-#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +-#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ +- +-#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +-#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ +- +-#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +-#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ +- +-#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +-#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ +- +- +-/* EVSYS - Event System */ +-/* EVSYS.CH0MUX bit masks and bit positions */ +-#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +-#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +-#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +-#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +-#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +-#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +-#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +-#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +-#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +-#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +-#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +-#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +-#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +-#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +-#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +-#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +-#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +-#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ +- +- +-/* EVSYS.CH1MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH2MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH3MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH4MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH5MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH6MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH7MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH0CTRL bit masks and bit positions */ +-#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +-#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +-#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +-#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +-#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +-#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ +- +-#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +-#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ +- +-#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +-#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ +- +-#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +-#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +-#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +-#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +-#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +-#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +-#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +-#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ +- +- +-/* EVSYS.CH1CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH2CTRL bit masks and bit positions */ +-/* EVSYS_QDIRM_gm Predefined. */ +-/* EVSYS_QDIRM_gp Predefined. */ +-/* EVSYS_QDIRM0_bm Predefined. */ +-/* EVSYS_QDIRM0_bp Predefined. */ +-/* EVSYS_QDIRM1_bm Predefined. */ +-/* EVSYS_QDIRM1_bp Predefined. */ +- +-/* EVSYS_QDIEN_bm Predefined. */ +-/* EVSYS_QDIEN_bp Predefined. */ +- +-/* EVSYS_QDEN_bm Predefined. */ +-/* EVSYS_QDEN_bp Predefined. */ +- +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH3CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH4CTRL bit masks and bit positions */ +-/* EVSYS_QDIRM_gm Predefined. */ +-/* EVSYS_QDIRM_gp Predefined. */ +-/* EVSYS_QDIRM0_bm Predefined. */ +-/* EVSYS_QDIRM0_bp Predefined. */ +-/* EVSYS_QDIRM1_bm Predefined. */ +-/* EVSYS_QDIRM1_bp Predefined. */ +- +-/* EVSYS_QDIEN_bm Predefined. */ +-/* EVSYS_QDIEN_bp Predefined. */ +- +-/* EVSYS_QDEN_bm Predefined. */ +-/* EVSYS_QDEN_bp Predefined. */ +- +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH5CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH6CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH7CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* NVM - Non Volatile Memory Controller */ +-/* NVM.CMD bit masks and bit positions */ +-#define NVM_CMD_gm 0xFF /* Command group mask. */ +-#define NVM_CMD_gp 0 /* Command group position. */ +-#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +-#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +-#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +-#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +-#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +-#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +-#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +-#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +-#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +-#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +-#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +-#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +-#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +-#define NVM_CMD7_bp 7 /* Command bit 7 position. */ +- +- +-/* NVM.CTRLA bit masks and bit positions */ +-#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +-#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ +- +- +-/* NVM.CTRLB bit masks and bit positions */ +-#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +-#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ +- +-#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +-#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ +- +-#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +-#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ +- +-#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +-#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ +- +- +-/* NVM.INTCTRL bit masks and bit positions */ +-#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +-#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +-#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +-#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +-#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +-#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ +- +-#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +-#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +-#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +-#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +-#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +-#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ +- +- +-/* NVM.STATUS bit masks and bit positions */ +-#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +-#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ +- +-#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +-#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ +- +-#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +-#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ +- +-#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +-#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ +- +- +-/* NVM.LOCKBITS bit masks and bit positions */ +-#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +-#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +-#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ +-#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ +-#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ +-#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ +-#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ +-#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ +-#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ +-#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ +-#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ +-#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ +-#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ +-#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ +-#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ +-#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ +-#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ +-#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ +-#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ +-#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +-#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +-#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +-#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ +- +-#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +-#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +-#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +-#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +-#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ +- +-#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +-#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ +- +-#define NVM_FUSES_BODACT_gm 0x0C /* BOD Operation in Active Mode group mask. */ +-#define NVM_FUSES_BODACT_gp 2 /* BOD Operation in Active Mode group position. */ +-#define NVM_FUSES_BODACT0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ +-#define NVM_FUSES_BODACT0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ +-#define NVM_FUSES_BODACT1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ +-#define NVM_FUSES_BODACT1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ +- +-#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +-#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +-#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +-#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +-#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +-#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +-#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +-#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +-#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +-#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +-#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +-#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ +- +-#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +-#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ +- +-#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ +-#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ +- +- +-/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +-#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +-#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ +- +-#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +-#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +-#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +-#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +-#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +-#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +-#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +-#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +- +- +-/* AC - Analog Comparator */ +-/* AC.AC0CTRL bit masks and bit positions */ +-#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +-#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +-#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +-#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +-#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +-#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ +- +-#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +-#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +-#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +-#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +-#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +-#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ +- +-#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +-#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ +- +-#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +-#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +-#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +-#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +-#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +-#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +- +-#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define AC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* AC.AC1CTRL bit masks and bit positions */ +-/* AC_INTMODE_gm Predefined. */ +-/* AC_INTMODE_gp Predefined. */ +-/* AC_INTMODE0_bm Predefined. */ +-/* AC_INTMODE0_bp Predefined. */ +-/* AC_INTMODE1_bm Predefined. */ +-/* AC_INTMODE1_bp Predefined. */ +- +-/* AC_INTLVL_gm Predefined. */ +-/* AC_INTLVL_gp Predefined. */ +-/* AC_INTLVL0_bm Predefined. */ +-/* AC_INTLVL0_bp Predefined. */ +-/* AC_INTLVL1_bm Predefined. */ +-/* AC_INTLVL1_bp Predefined. */ +- +-/* AC_HSMODE_bm Predefined. */ +-/* AC_HSMODE_bp Predefined. */ +- +-/* AC_HYSMODE_gm Predefined. */ +-/* AC_HYSMODE_gp Predefined. */ +-/* AC_HYSMODE0_bm Predefined. */ +-/* AC_HYSMODE0_bp Predefined. */ +-/* AC_HYSMODE1_bm Predefined. */ +-/* AC_HYSMODE1_bp Predefined. */ +- +-/* AC_ENABLE_bm Predefined. */ +-/* AC_ENABLE_bp Predefined. */ +- +- +-/* AC.AC0MUXCTRL bit masks and bit positions */ +-#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +-#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +-#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +-#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +-#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +-#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +-#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +-#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ +- +-#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +-#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +-#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +-#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +-#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +-#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +-#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +-#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ +- +- +-/* AC.AC1MUXCTRL bit masks and bit positions */ +-/* AC_MUXPOS_gm Predefined. */ +-/* AC_MUXPOS_gp Predefined. */ +-/* AC_MUXPOS0_bm Predefined. */ +-/* AC_MUXPOS0_bp Predefined. */ +-/* AC_MUXPOS1_bm Predefined. */ +-/* AC_MUXPOS1_bp Predefined. */ +-/* AC_MUXPOS2_bm Predefined. */ +-/* AC_MUXPOS2_bp Predefined. */ +- +-/* AC_MUXNEG_gm Predefined. */ +-/* AC_MUXNEG_gp Predefined. */ +-/* AC_MUXNEG0_bm Predefined. */ +-/* AC_MUXNEG0_bp Predefined. */ +-/* AC_MUXNEG1_bm Predefined. */ +-/* AC_MUXNEG1_bp Predefined. */ +-/* AC_MUXNEG2_bm Predefined. */ +-/* AC_MUXNEG2_bp Predefined. */ +- +- +-/* AC.CTRLA bit masks and bit positions */ +-#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +-#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ +- +- +-/* AC.CTRLB bit masks and bit positions */ +-#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +-#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +-#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +-#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +-#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +-#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +-#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +-#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +-#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +-#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +-#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +-#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +-#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +-#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ +- +- +-/* AC.WINCTRL bit masks and bit positions */ +-#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +-#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ +- +-#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +-#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +-#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +-#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +-#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +-#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ +- +-#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +-#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +-#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +-#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +-#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +-#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ +- +- +-/* AC.STATUS bit masks and bit positions */ +-#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +-#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +-#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +-#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +-#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +-#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ +- +-#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +-#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ +- +-#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +-#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ +- +-#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +-#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ +- +-#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +-#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ +- +-#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +-#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ +- +- +-/* ADC - Analog/Digital Converter */ +-/* ADC_CH.CTRL bit masks and bit positions */ +-#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +-#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ +- +-#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +-#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +-#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +-#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +-#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +-#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +-#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +-#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ +- +-#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +-#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +-#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +-#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +-#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +-#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ +- +- +-/* ADC_CH.MUXCTRL bit masks and bit positions */ +-#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +-#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +-#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +-#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +-#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +-#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +-#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +-#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +-#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +-#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ +- +-#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +-#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +-#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +-#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +-#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +-#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +-#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +-#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +-#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +-#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ +- +-#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +-#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +-#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +-#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +-#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +-#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ +- +- +-/* ADC_CH.INTCTRL bit masks and bit positions */ +-#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +-#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +-#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +-#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +-#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +-#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ +- +-#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +-#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +-#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +-#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +-#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +-#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ +- +- +-/* ADC_CH.INTFLAGS bit masks and bit positions */ +-#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +-#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ +- +- +-/* ADC.CTRLA bit masks and bit positions */ +-#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +-#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +-#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +-#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +-#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +-#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ +- +-#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +-#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ +- +-#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +-#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ +- +-#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +-#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ +- +-#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +-#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ +- +-#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +-#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ +- +-#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +-#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ +- +- +-/* ADC.CTRLB bit masks and bit positions */ +-#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +-#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ +- +-#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +-#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ +- +-#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +-#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +-#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +-#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +-#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +-#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ +- +- +-/* ADC.REFCTRL bit masks and bit positions */ +-#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +-#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +-#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +-#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +-#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +-#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +- +-#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +-#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ +- +-#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +-#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ +- +- +-/* ADC.EVCTRL bit masks and bit positions */ +-#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +-#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +-#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +-#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +-#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +-#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ +- +-#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +-#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +-#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +-#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +-#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +-#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +-#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +-#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ +- +-#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +-#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +-#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +-#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +-#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +-#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +-#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +-#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ +- +- +-/* ADC.PRESCALER bit masks and bit positions */ +-#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +-#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +-#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +-#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +-#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +-#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +-#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +-#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ +- +- +-/* ADC.INTFLAGS bit masks and bit positions */ +-#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +-#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ +- +-#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +-#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ +- +-#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +-#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ +- +-#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +-#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ +- +- +-/* DAC - Digital/Analog Converter */ +-/* DAC.CTRLA bit masks and bit positions */ +-#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +-#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ +- +-#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +-#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ +- +-#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +-#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ +- +-#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +-#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ +- +-#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define DAC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* DAC.CTRLB bit masks and bit positions */ +-#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +-#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +-#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +-#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +-#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +-#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ +- +-#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +-#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ +- +-#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +-#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ +- +- +-/* DAC.CTRLC bit masks and bit positions */ +-#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +-#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +-#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +-#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +-#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +-#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ +- +-#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +-#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ +- +- +-/* DAC.EVCTRL bit masks and bit positions */ +-#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +-#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +-#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +-#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +-#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +-#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +-#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +-#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ +- +- +-/* DAC.TIMCTRL bit masks and bit positions */ +-#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ +-#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ +-#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ +-#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ +-#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ +-#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ +-#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ +-#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ +- +-#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ +-#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ +-#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ +-#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ +-#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ +-#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ +-#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ +-#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ +-#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ +-#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ +- +- +-/* DAC.STATUS bit masks and bit positions */ +-#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +-#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ +- +-#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +-#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ +- +- +-/* RTC - Real-Time Clounter */ +-/* RTC.CTRL bit masks and bit positions */ +-#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +-#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +-#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +-#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +-#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +-#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +-#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +-#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ +- +- +-/* RTC.STATUS bit masks and bit positions */ +-#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +-#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ +- +- +-/* RTC.INTCTRL bit masks and bit positions */ +-#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +-#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +-#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +-#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +-#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +-#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ +- +-#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +-#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +-#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +-#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +-#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +-#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ +- +- +-/* RTC.INTFLAGS bit masks and bit positions */ +-#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +-#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ +- +-#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* EBI - External Bus Interface */ +-/* EBI_CS.CTRLA bit masks and bit positions */ +-#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +-#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +-#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +-#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +-#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +-#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +-#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +-#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +-#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +-#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +-#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +-#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ +- +-#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +-#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +-#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +-#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +-#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +-#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ +- +- +-/* EBI_CS.CTRLB bit masks and bit positions */ +-#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +-#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +-#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +-#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +-#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +-#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +-#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +-#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ +- +-#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +-#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ +- +-#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +-#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ +- +-#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +-#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +-#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +-#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +-#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +-#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ +- +- +-/* EBI.CTRL bit masks and bit positions */ +-#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +-#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +-#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +-#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +-#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +-#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ +- +-#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +-#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +-#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +-#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +-#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +-#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ +- +-#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +-#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +-#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +-#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +-#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +-#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ +- +-#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +-#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +-#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +-#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +-#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +-#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLA bit masks and bit positions */ +-#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +-#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ +- +-#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +-#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ +- +-#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +-#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +-#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +-#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +-#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +-#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLB bit masks and bit positions */ +-#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +-#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +-#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +-#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +-#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +-#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ +- +-#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +-#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +-#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +-#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +-#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +-#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +-#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +-#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ +- +-#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +-#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +-#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +-#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +-#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +-#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +-#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +-#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ +- +- +-/* EBI.SDRAMCTRLC bit masks and bit positions */ +-#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +-#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +-#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +-#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +-#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +-#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ +- +-#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +-#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +-#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +-#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +-#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +-#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +-#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +-#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ +- +-#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +-#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +-#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +-#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +-#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +-#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +-#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +-#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ +- +- +-/* TWI - Two-Wire Interface */ +-/* TWI_MASTER.CTRLA bit masks and bit positions */ +-#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +-#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ +- +-#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +-#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ +- +-#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +-#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ +- +- +-/* TWI_MASTER.CTRLB bit masks and bit positions */ +-#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +-#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +-#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +-#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +-#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +-#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +- +-#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +-#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ +- +-#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_MASTER.CTRLC bit masks and bit positions */ +-#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +-#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_MASTER.STATUS bit masks and bit positions */ +-#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +-#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ +- +-#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +-#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ +- +-#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +-#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +- +-#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +-#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +-#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +-#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +-#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +-#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +- +- +-/* TWI_SLAVE.CTRLA bit masks and bit positions */ +-#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +-#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +-#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ +- +-#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +-#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ +- +-#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_SLAVE.CTRLB bit masks and bit positions */ +-#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +-#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_SLAVE.STATUS bit masks and bit positions */ +-#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +-#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +-#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +-#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ +- +-#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +-#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ +- +-#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +-#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ +- +- +-/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +-#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +-#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +-#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +-#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +-#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +-#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +-#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +-#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +-#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +-#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +-#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +-#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +-#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +-#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +-#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +-#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ +- +-#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +-#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ +- +- +-/* TWI.CTRL bit masks and bit positions */ +-#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +-#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ +- +-#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +-#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ +- +- +-/* PORT - Port Configuration */ +-/* PORTCFG.VPCTRLA bit masks and bit positions */ +-#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +-#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +-#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +-#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +-#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +-#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +-#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +-#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +-#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +-#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ +- +-#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +-#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +-#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +-#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +-#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +-#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +-#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +-#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +-#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +-#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ +- +- +-/* PORTCFG.VPCTRLB bit masks and bit positions */ +-#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +-#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +-#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +-#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +-#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +-#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +-#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +-#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +-#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +-#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ +- +-#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +-#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +-#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +-#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +-#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +-#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +-#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +-#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +-#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +-#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ +- +- +-/* PORTCFG.CLKEVOUT bit masks and bit positions */ +-#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +-#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +-#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +-#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +-#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +-#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ +- +-#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +-#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +-#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +-#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +-#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +-#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ +- +- +-/* VPORT.INTFLAGS bit masks and bit positions */ +-#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.INTCTRL bit masks and bit positions */ +-#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +-#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +-#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +-#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +-#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +-#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ +- +-#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +-#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +-#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +-#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +-#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +-#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ +- +- +-/* PORT.INTFLAGS bit masks and bit positions */ +-#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.PIN0CTRL bit masks and bit positions */ +-#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +-#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ +- +-#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +-#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ +- +-#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +-#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +-#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +-#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +-#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +-#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +-#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +-#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ +- +-#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +-#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +-#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +-#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +-#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +-#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +-#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +-#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +- +- +-/* PORT.PIN1CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN2CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN3CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN4CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN5CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN6CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN7CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* TC - 16-bit Timer/Counter With PWM */ +-/* TC0.CTRLA bit masks and bit positions */ +-#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC0.CTRLB bit masks and bit positions */ +-#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +-#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ +- +-#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +-#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ +- +-#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC0.CTRLC bit masks and bit positions */ +-#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +-#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ +- +-#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +-#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ +- +-#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC0.CTRLD bit masks and bit positions */ +-#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC0_EVACT_gp 5 /* Event Action group position. */ +-#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC0.CTRLE bit masks and bit positions */ +-#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +-#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ +- +-#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC0.INTCTRLA bit masks and bit positions */ +-#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC0.INTCTRLB bit masks and bit positions */ +-#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +-#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +-#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +-#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +-#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +-#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ +- +-#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +-#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +-#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +-#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +-#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +-#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ +- +-#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC0.CTRLFCLR bit masks and bit positions */ +-#define TC0_CMD_gm 0x0C /* Command group mask. */ +-#define TC0_CMD_gp 2 /* Command group position. */ +-#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC0_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC0_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC0_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC0.CTRLFSET bit masks and bit positions */ +-/* TC0_CMD_gm Predefined. */ +-/* TC0_CMD_gp Predefined. */ +-/* TC0_CMD0_bm Predefined. */ +-/* TC0_CMD0_bp Predefined. */ +-/* TC0_CMD1_bm Predefined. */ +-/* TC0_CMD1_bp Predefined. */ +- +-/* TC0_LUPD_bm Predefined. */ +-/* TC0_LUPD_bp Predefined. */ +- +-/* TC0_DIR_bm Predefined. */ +-/* TC0_DIR_bp Predefined. */ +- +- +-/* TC0.CTRLGCLR bit masks and bit positions */ +-#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +-#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ +- +-#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +-#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ +- +-#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC0.CTRLGSET bit masks and bit positions */ +-/* TC0_CCDBV_bm Predefined. */ +-/* TC0_CCDBV_bp Predefined. */ +- +-/* TC0_CCCBV_bm Predefined. */ +-/* TC0_CCCBV_bp Predefined. */ +- +-/* TC0_CCBBV_bm Predefined. */ +-/* TC0_CCBBV_bp Predefined. */ +- +-/* TC0_CCABV_bm Predefined. */ +-/* TC0_CCABV_bp Predefined. */ +- +-/* TC0_PERBV_bm Predefined. */ +-/* TC0_PERBV_bp Predefined. */ +- +- +-/* TC0.INTFLAGS bit masks and bit positions */ +-#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +-#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ +- +-#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +-#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ +- +-#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* TC1.CTRLA bit masks and bit positions */ +-#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC1.CTRLB bit masks and bit positions */ +-#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC1.CTRLC bit masks and bit positions */ +-#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC1.CTRLD bit masks and bit positions */ +-#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC1_EVACT_gp 5 /* Event Action group position. */ +-#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC1.CTRLE bit masks and bit positions */ +-#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +-#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ +- +-#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC1.INTCTRLA bit masks and bit positions */ +-#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC1.INTCTRLB bit masks and bit positions */ +-#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC1.CTRLFCLR bit masks and bit positions */ +-#define TC1_CMD_gm 0x0C /* Command group mask. */ +-#define TC1_CMD_gp 2 /* Command group position. */ +-#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC1_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC1_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC1_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC1.CTRLFSET bit masks and bit positions */ +-/* TC1_CMD_gm Predefined. */ +-/* TC1_CMD_gp Predefined. */ +-/* TC1_CMD0_bm Predefined. */ +-/* TC1_CMD0_bp Predefined. */ +-/* TC1_CMD1_bm Predefined. */ +-/* TC1_CMD1_bp Predefined. */ +- +-/* TC1_LUPD_bm Predefined. */ +-/* TC1_LUPD_bp Predefined. */ +- +-/* TC1_DIR_bm Predefined. */ +-/* TC1_DIR_bp Predefined. */ +- +- +-/* TC1.CTRLGCLR bit masks and bit positions */ +-#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC1.CTRLGSET bit masks and bit positions */ +-/* TC1_CCBBV_bm Predefined. */ +-/* TC1_CCBBV_bp Predefined. */ +- +-/* TC1_CCABV_bm Predefined. */ +-/* TC1_CCABV_bp Predefined. */ +- +-/* TC1_PERBV_bm Predefined. */ +-/* TC1_PERBV_bp Predefined. */ +- +- +-/* TC1.INTFLAGS bit masks and bit positions */ +-#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* AWEX.CTRL bit masks and bit positions */ +-#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +-#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ +- +-#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +-#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ +- +-#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +-#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ +- +-#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +-#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ +- +-#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +-#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ +- +-#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +-#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ +- +- +-/* AWEX.FDCTRL bit masks and bit positions */ +-#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +-#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ +- +-#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +-#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ +- +-#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +-#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +-#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +-#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +-#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +-#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ +- +- +-/* AWEX.STATUS bit masks and bit positions */ +-#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +-#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ +- +-#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +-#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ +- +-#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +-#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ +- +- +-/* HIRES.CTRL bit masks and bit positions */ +-#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +-#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +-#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +-#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +-#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +-#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ +- +- +-/* USART - Universal Asynchronous Receiver-Transmitter */ +-/* USART.STATUS bit masks and bit positions */ +-#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +-#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ +- +-#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +-#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +- +-#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +-#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +- +-#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +-#define USART_FERR_bp 4 /* Frame Error bit position. */ +- +-#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +-#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ +- +-#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +-#define USART_PERR_bp 2 /* Parity Error bit position. */ +- +-#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +-#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ +- +- +-/* USART.CTRLA bit masks and bit positions */ +-#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +-#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +-#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +-#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +-#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +-#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ +- +-#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +-#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +-#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +-#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +-#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +-#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ +- +-#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +-#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +-#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +-#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +-#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +-#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ +- +- +-/* USART.CTRLB bit masks and bit positions */ +-#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +-#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ +- +-#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +-#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ +- +-#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +-#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ +- +-#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +-#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ +- +-#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +-#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ +- +- +-/* USART.CTRLC bit masks and bit positions */ +-#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +-#define USART_CMODE_gp 6 /* Communication Mode group position. */ +-#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +-#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +-#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +-#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ +- +-#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +-#define USART_PMODE_gp 4 /* Parity Mode group position. */ +-#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +-#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +-#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +-#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +- +-#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +-#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +- +-#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +-#define USART_CHSIZE_gp 0 /* Character Size group position. */ +-#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +-#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +-#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +-#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +-#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +-#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +- +- +-/* USART.BAUDCTRLA bit masks and bit positions */ +-#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +-#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +-#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +-#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +-#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +-#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +-#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +-#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +-#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +-#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +-#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +-#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +-#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +-#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +-#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +-#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +-#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +-#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ +- +- +-/* USART.BAUDCTRLB bit masks and bit positions */ +-#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +-#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +-#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +-#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +-#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +-#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +-#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +-#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +-#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +-#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ +- +-/* USART_BSEL_gm Predefined. */ +-/* USART_BSEL_gp Predefined. */ +-/* USART_BSEL0_bm Predefined. */ +-/* USART_BSEL0_bp Predefined. */ +-/* USART_BSEL1_bm Predefined. */ +-/* USART_BSEL1_bp Predefined. */ +-/* USART_BSEL2_bm Predefined. */ +-/* USART_BSEL2_bp Predefined. */ +-/* USART_BSEL3_bm Predefined. */ +-/* USART_BSEL3_bp Predefined. */ +- +- +-/* SPI - Serial Peripheral Interface */ +-/* SPI.CTRL bit masks and bit positions */ +-#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +-#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ +- +-#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +-#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ +- +-#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +-#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ +- +-#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +-#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ +- +-#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +-#define SPI_MODE_gp 2 /* SPI Mode group position. */ +-#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +-#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +-#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +-#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ +- +-#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +-#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +-#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +-#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +-#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +-#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ +- +- +-/* SPI.INTCTRL bit masks and bit positions */ +-#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +-#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +-/* SPI.STATUS bit masks and bit positions */ +-#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +-#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ +- +-#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +-#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +- +- +-/* IRCOM - IR Communication Module */ +-/* IRCOM.CTRL bit masks and bit positions */ +-#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +-#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +-#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +-#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +-#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +-#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +-#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +-#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +-#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +-#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ +- +- +-/* AES - AES Module */ +-/* AES.CTRL bit masks and bit positions */ +-#define AES_START_bm 0x80 /* Start/Run bit mask. */ +-#define AES_START_bp 7 /* Start/Run bit position. */ +- +-#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +-#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ +- +-#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +-#define AES_RESET_bp 5 /* AES Software Reset bit position. */ +- +-#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +-#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ +- +-#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +-#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ +- +- +-/* AES.STATUS bit masks and bit positions */ +-#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +-#define AES_ERROR_bp 7 /* AES Error bit position. */ +- +-#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +-#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ +- +- +-/* AES.INTCTRL bit masks and bit positions */ +-#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +-#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +- +-// Generic Port Pins +- +-#define PIN0_bm 0x01 +-#define PIN0_bp 0 +-#define PIN1_bm 0x02 +-#define PIN1_bp 1 +-#define PIN2_bm 0x04 +-#define PIN2_bp 2 +-#define PIN3_bm 0x08 +-#define PIN3_bp 3 +-#define PIN4_bm 0x10 +-#define PIN4_bp 4 +-#define PIN5_bm 0x20 +-#define PIN5_bp 5 +-#define PIN6_bm 0x40 +-#define PIN6_bp 6 +-#define PIN7_bm 0x80 +-#define PIN7_bp 7 +- +- +-/* ========== Interrupt Vector Definitions ========== */ +-/* Vector 0 is the reset vector */ +- +-/* OSC interrupt vectors */ +-#define OSC_XOSCF_vect_num 1 +-#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ +- +-/* PORTC interrupt vectors */ +-#define PORTC_INT0_vect_num 2 +-#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +-#define PORTC_INT1_vect_num 3 +-#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ +- +-/* PORTR interrupt vectors */ +-#define PORTR_INT0_vect_num 4 +-#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +-#define PORTR_INT1_vect_num 5 +-#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ +- +-/* DMA interrupt vectors */ +-#define DMA_CH0_vect_num 6 +-#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +-#define DMA_CH1_vect_num 7 +-#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +-#define DMA_CH2_vect_num 8 +-#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +-#define DMA_CH3_vect_num 9 +-#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ +- +-/* RTC interrupt vectors */ +-#define RTC_OVF_vect_num 10 +-#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +-#define RTC_COMP_vect_num 11 +-#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ +- +-/* TWIC interrupt vectors */ +-#define TWIC_TWIS_vect_num 12 +-#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +-#define TWIC_TWIM_vect_num 13 +-#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ +- +-/* TCC0 interrupt vectors */ +-#define TCC0_OVF_vect_num 14 +-#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +-#define TCC0_ERR_vect_num 15 +-#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +-#define TCC0_CCA_vect_num 16 +-#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +-#define TCC0_CCB_vect_num 17 +-#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +-#define TCC0_CCC_vect_num 18 +-#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +-#define TCC0_CCD_vect_num 19 +-#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ +- +-/* TCC1 interrupt vectors */ +-#define TCC1_OVF_vect_num 20 +-#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +-#define TCC1_ERR_vect_num 21 +-#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +-#define TCC1_CCA_vect_num 22 +-#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +-#define TCC1_CCB_vect_num 23 +-#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ +- +-/* SPIC interrupt vectors */ +-#define SPIC_INT_vect_num 24 +-#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ +- +-/* USARTC0 interrupt vectors */ +-#define USARTC0_RXC_vect_num 25 +-#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +-#define USARTC0_DRE_vect_num 26 +-#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +-#define USARTC0_TXC_vect_num 27 +-#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ +- +-/* USARTC1 interrupt vectors */ +-#define USARTC1_RXC_vect_num 28 +-#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +-#define USARTC1_DRE_vect_num 29 +-#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +-#define USARTC1_TXC_vect_num 30 +-#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ +- +-/* AES interrupt vectors */ +-#define AES_INT_vect_num 31 +-#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ +- +-/* NVM interrupt vectors */ +-#define NVM_EE_vect_num 32 +-#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +-#define NVM_SPM_vect_num 33 +-#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ +- +-/* PORTB interrupt vectors */ +-#define PORTB_INT0_vect_num 34 +-#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +-#define PORTB_INT1_vect_num 35 +-#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ +- +-/* ACB interrupt vectors */ +-#define ACB_AC0_vect_num 36 +-#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ +-#define ACB_AC1_vect_num 37 +-#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ +-#define ACB_ACW_vect_num 38 +-#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ +- +-/* ADCB interrupt vectors */ +-#define ADCB_CH0_vect_num 39 +-#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ +-#define ADCB_CH1_vect_num 40 +-#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ +-#define ADCB_CH2_vect_num 41 +-#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ +-#define ADCB_CH3_vect_num 42 +-#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ +- +-/* PORTE interrupt vectors */ +-#define PORTE_INT0_vect_num 43 +-#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +-#define PORTE_INT1_vect_num 44 +-#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ +- +-/* TWIE interrupt vectors */ +-#define TWIE_TWIS_vect_num 45 +-#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +-#define TWIE_TWIM_vect_num 46 +-#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ +- +-/* TCE0 interrupt vectors */ +-#define TCE0_OVF_vect_num 47 +-#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +-#define TCE0_ERR_vect_num 48 +-#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +-#define TCE0_CCA_vect_num 49 +-#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +-#define TCE0_CCB_vect_num 50 +-#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +-#define TCE0_CCC_vect_num 51 +-#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +-#define TCE0_CCD_vect_num 52 +-#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ +- +-/* TCE1 interrupt vectors */ +-#define TCE1_OVF_vect_num 53 +-#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ +-#define TCE1_ERR_vect_num 54 +-#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ +-#define TCE1_CCA_vect_num 55 +-#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ +-#define TCE1_CCB_vect_num 56 +-#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ +- +-/* SPIE interrupt vectors */ +-#define SPIE_INT_vect_num 57 +-#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ +- +-/* USARTE0 interrupt vectors */ +-#define USARTE0_RXC_vect_num 58 +-#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +-#define USARTE0_DRE_vect_num 59 +-#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +-#define USARTE0_TXC_vect_num 60 +-#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ +- +-/* USARTE1 interrupt vectors */ +-#define USARTE1_RXC_vect_num 61 +-#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ +-#define USARTE1_DRE_vect_num 62 +-#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ +-#define USARTE1_TXC_vect_num 63 +-#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ +- +-/* PORTD interrupt vectors */ +-#define PORTD_INT0_vect_num 64 +-#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +-#define PORTD_INT1_vect_num 65 +-#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ +- +-/* PORTA interrupt vectors */ +-#define PORTA_INT0_vect_num 66 +-#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +-#define PORTA_INT1_vect_num 67 +-#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ +- +-/* ACA interrupt vectors */ +-#define ACA_AC0_vect_num 68 +-#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +-#define ACA_AC1_vect_num 69 +-#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +-#define ACA_ACW_vect_num 70 +-#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ +- +-/* ADCA interrupt vectors */ +-#define ADCA_CH0_vect_num 71 +-#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +-#define ADCA_CH1_vect_num 72 +-#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +-#define ADCA_CH2_vect_num 73 +-#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +-#define ADCA_CH3_vect_num 74 +-#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ +- +-/* TWID interrupt vectors */ +-#define TWID_TWIS_vect_num 75 +-#define TWID_TWIS_vect _VECTOR(75) /* TWI Slave Interrupt */ +-#define TWID_TWIM_vect_num 76 +-#define TWID_TWIM_vect _VECTOR(76) /* TWI Master Interrupt */ +- +-/* TCD0 interrupt vectors */ +-#define TCD0_OVF_vect_num 77 +-#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +-#define TCD0_ERR_vect_num 78 +-#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +-#define TCD0_CCA_vect_num 79 +-#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +-#define TCD0_CCB_vect_num 80 +-#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +-#define TCD0_CCC_vect_num 81 +-#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +-#define TCD0_CCD_vect_num 82 +-#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ +- +-/* TCD1 interrupt vectors */ +-#define TCD1_OVF_vect_num 83 +-#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +-#define TCD1_ERR_vect_num 84 +-#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +-#define TCD1_CCA_vect_num 85 +-#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +-#define TCD1_CCB_vect_num 86 +-#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ +- +-/* SPID interrupt vectors */ +-#define SPID_INT_vect_num 87 +-#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ +- +-/* USARTD0 interrupt vectors */ +-#define USARTD0_RXC_vect_num 88 +-#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +-#define USARTD0_DRE_vect_num 89 +-#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +-#define USARTD0_TXC_vect_num 90 +-#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ +- +-/* USARTD1 interrupt vectors */ +-#define USARTD1_RXC_vect_num 91 +-#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +-#define USARTD1_DRE_vect_num 92 +-#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +-#define USARTD1_TXC_vect_num 93 +-#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ +- +-/* PORTQ interrupt vectors */ +-#define PORTQ_INT0_vect_num 94 +-#define PORTQ_INT0_vect _VECTOR(94) /* External Interrupt 0 */ +-#define PORTQ_INT1_vect_num 95 +-#define PORTQ_INT1_vect _VECTOR(95) /* External Interrupt 1 */ +- +-/* PORTH interrupt vectors */ +-#define PORTH_INT0_vect_num 96 +-#define PORTH_INT0_vect _VECTOR(96) /* External Interrupt 0 */ +-#define PORTH_INT1_vect_num 97 +-#define PORTH_INT1_vect _VECTOR(97) /* External Interrupt 1 */ +- +-/* PORTJ interrupt vectors */ +-#define PORTJ_INT0_vect_num 98 +-#define PORTJ_INT0_vect _VECTOR(98) /* External Interrupt 0 */ +-#define PORTJ_INT1_vect_num 99 +-#define PORTJ_INT1_vect _VECTOR(99) /* External Interrupt 1 */ +- +-/* PORTK interrupt vectors */ +-#define PORTK_INT0_vect_num 100 +-#define PORTK_INT0_vect _VECTOR(100) /* External Interrupt 0 */ +-#define PORTK_INT1_vect_num 101 +-#define PORTK_INT1_vect _VECTOR(101) /* External Interrupt 1 */ +- +-/* PORTF interrupt vectors */ +-#define PORTF_INT0_vect_num 104 +-#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +-#define PORTF_INT1_vect_num 105 +-#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ +- +-/* TWIF interrupt vectors */ +-#define TWIF_TWIS_vect_num 106 +-#define TWIF_TWIS_vect _VECTOR(106) /* TWI Slave Interrupt */ +-#define TWIF_TWIM_vect_num 107 +-#define TWIF_TWIM_vect _VECTOR(107) /* TWI Master Interrupt */ +- +-/* TCF0 interrupt vectors */ +-#define TCF0_OVF_vect_num 108 +-#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ +-#define TCF0_ERR_vect_num 109 +-#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ +-#define TCF0_CCA_vect_num 110 +-#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ +-#define TCF0_CCB_vect_num 111 +-#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ +-#define TCF0_CCC_vect_num 112 +-#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ +-#define TCF0_CCD_vect_num 113 +-#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ +- +-/* TCF1 interrupt vectors */ +-#define TCF1_OVF_vect_num 114 +-#define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */ +-#define TCF1_ERR_vect_num 115 +-#define TCF1_ERR_vect _VECTOR(115) /* Error Interrupt */ +-#define TCF1_CCA_vect_num 116 +-#define TCF1_CCA_vect _VECTOR(116) /* Compare or Capture A Interrupt */ +-#define TCF1_CCB_vect_num 117 +-#define TCF1_CCB_vect _VECTOR(117) /* Compare or Capture B Interrupt */ +- +-/* SPIF interrupt vectors */ +-#define SPIF_INT_vect_num 118 +-#define SPIF_INT_vect _VECTOR(118) /* SPI Interrupt */ +- +-/* USARTF0 interrupt vectors */ +-#define USARTF0_RXC_vect_num 119 +-#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ +-#define USARTF0_DRE_vect_num 120 +-#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ +-#define USARTF0_TXC_vect_num 121 +-#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ +- +-/* USARTF1 interrupt vectors */ +-#define USARTF1_RXC_vect_num 122 +-#define USARTF1_RXC_vect _VECTOR(122) /* Reception Complete Interrupt */ +-#define USARTF1_DRE_vect_num 123 +-#define USARTF1_DRE_vect _VECTOR(123) /* Data Register Empty Interrupt */ +-#define USARTF1_TXC_vect_num 124 +-#define USARTF1_TXC_vect _VECTOR(124) /* Transmission Complete Interrupt */ +- +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (125 * _VECTOR_SIZE) +- +- +-/* ========== Constants ========== */ +- +-#define PROGMEM_START (0x0000) +-#define PROGMEM_SIZE (69632) +-#define PROGMEM_PAGE_SIZE (256) +-#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) +- +-#define APP_SECTION_START (0x0000) +-#define APP_SECTION_SIZE (65536) +-#define APP_SECTION_PAGE_SIZE (256) +-#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) +- +-#define APPTABLE_SECTION_START (0x0F000) +-#define APPTABLE_SECTION_SIZE (4096) +-#define APPTABLE_SECTION_PAGE_SIZE (256) +-#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) +- +-#define BOOT_SECTION_START (0x10000) +-#define BOOT_SECTION_SIZE (4096) +-#define BOOT_SECTION_PAGE_SIZE (256) +-#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) +- +-#define DATAMEM_START (0x0000) +-#define DATAMEM_SIZE (16777216) +-#define DATAMEM_PAGE_SIZE (0) +-#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) +- +-#define IO_START (0x0000) +-#define IO_SIZE (4096) +-#define IO_PAGE_SIZE (0) +-#define IO_END (IO_START + IO_SIZE - 1) +- +-#define MAPPED_EEPROM_START (0x1000) +-#define MAPPED_EEPROM_SIZE (2048) +-#define MAPPED_EEPROM_PAGE_SIZE (0) +-#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) +- +-#define INTERNAL_SRAM_START (0x2000) +-#define INTERNAL_SRAM_SIZE (4096) +-#define INTERNAL_SRAM_PAGE_SIZE (0) +-#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) +- +-#define EXTERNAL_SRAM_START (0x3000) +-#define EXTERNAL_SRAM_SIZE (16764928) +-#define EXTERNAL_SRAM_PAGE_SIZE (0) +-#define EXTERNAL_SRAM_END (EXTERNAL_SRAM_START + EXTERNAL_SRAM_SIZE - 1) +- +-#define EEPROM_START (0x0000) +-#define EEPROM_SIZE (2048) +-#define EEPROM_PAGE_SIZE (32) +-#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) +- +-#define FUSE_START (0x0000) +-#define FUSE_SIZE (6) +-#define FUSE_PAGE_SIZE (0) +-#define FUSE_END (FUSE_START + FUSE_SIZE - 1) +- +-#define LOCKBIT_START (0x0000) +-#define LOCKBIT_SIZE (1) +-#define LOCKBIT_PAGE_SIZE (0) +-#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) +- +-#define SIGNATURES_START (0x0000) +-#define SIGNATURES_SIZE (3) +-#define SIGNATURES_PAGE_SIZE (0) +-#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) +- +-#define USER_SIGNATURES_START (0x0000) +-#define USER_SIGNATURES_SIZE (256) +-#define USER_SIGNATURES_PAGE_SIZE (0) +-#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) +- +-#define PROD_SIGNATURES_START (0x0000) +-#define PROD_SIGNATURES_SIZE (52) +-#define PROD_SIGNATURES_PAGE_SIZE (0) +-#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) +- +-#define FLASHEND PROGMEM_END +-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +-#define RAMSTART INTERNAL_SRAM_START +-#define RAMSIZE INTERNAL_SRAM_SIZE +-#define RAMEND INTERNAL_SRAM_END +-#define XRAMSTART EXTERNAL_SRAM_START +-#define XRAMSIZE EXTERNAL_SRAM_SIZE +-#define XRAMEND EXTERNAL_SRAM_END +-#define E2END EEPROM_END +-#define E2PAGESIZE EEPROM_PAGE_SIZE +- +- +-/* ========== Fuses ========== */ +-#define FUSE_MEMORY_SIZE 6 +- +-/* Fuse Byte 0 */ +-#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ +-#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ +-#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ +-#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ +-#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ +-#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ +-#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ +-#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ +-#define FUSE0_DEFAULT (0xFF) +- +-/* Fuse Byte 1 */ +-#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +-#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +-#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +-#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +-#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +-#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +-#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +-#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +-#define FUSE1_DEFAULT (0xFF) +- +-/* Fuse Byte 2 */ +-#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +-#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +-#define FUSE_BODACT0 (unsigned char)~_BV(2) /* BOD Operation in Active Mode Bit 0 */ +-#define FUSE_BODACT1 (unsigned char)~_BV(3) /* BOD Operation in Active Mode Bit 1 */ +-#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +-#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +-#define FUSE2_DEFAULT (0xFF) +- +-/* Fuse Byte 3 Reserved */ +- +-/* Fuse Byte 4 */ +-#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ +-#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +-#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +-#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +-#define FUSE4_DEFAULT (0xFF) +- +-/* Fuse Byte 5 */ +-#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +-#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +-#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +-#define FUSE5_DEFAULT (0xFF) +- +- +-/* ========== Lock Bits ========== */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_BITS_EXIST +-#define __BOOT_LOCK_BOOT_BITS_EXIST +- +- +-/* ========== Signature ========== */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x96 +-#define SIGNATURE_2 0x4E +- +- +-#endif /* _AVR_ATxmega64A1_H_ */ +- ++/* Copyright (c) 2009-2010 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iox64a1.h 2260 2011-11-02 16:53:30Z arcanum $ */ ++ ++/* avr/iox64a1.h - definitions for ATxmega64A1 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox64a1.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATxmega64A1_H_ ++#define _AVR_ATxmega64A1_H_ 1 ++ ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++} CLK_t; ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t PRPB; /* Power Reduction Port B */ ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ ++} CLK_RTCSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control REgister */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t reserved_0x07; ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Channel */ ++typedef struct DMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Address Control */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ ++ register8_t REPCNT; /* Channel Repeat Count */ ++ register8_t reserved_0x07; ++ register8_t SRCADDR0; /* Channel Source Address 0 */ ++ register8_t SRCADDR1; /* Channel Source Address 1 */ ++ register8_t SRCADDR2; /* Channel Source Address 2 */ ++ register8_t reserved_0x0B; ++ register8_t DESTADDR0; /* Channel Destination Address 0 */ ++ register8_t DESTADDR1; /* Channel Destination Address 1 */ ++ register8_t DESTADDR2; /* Channel Destination Address 2 */ ++ register8_t reserved_0x0F; ++} DMA_CH_t; ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Controller */ ++typedef struct DMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ DMA_CH_t CH0; /* DMA Channel 0 */ ++ DMA_CH_t CH1; /* DMA Channel 1 */ ++ DMA_CH_t CH2; /* DMA Channel 2 */ ++ DMA_CH_t CH3; /* DMA Channel 3 */ ++} DMA_t; ++ ++/* Burst mode */ ++typedef enum DMA_CH_BURSTLEN_enum ++{ ++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ ++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ ++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ ++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ ++} DMA_CH_BURSTLEN_t; ++ ++/* Source address reload mode */ ++typedef enum DMA_CH_SRCRELOAD_enum ++{ ++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ ++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ ++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ ++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ ++} DMA_CH_SRCRELOAD_t; ++ ++/* Source addressing mode */ ++typedef enum DMA_CH_SRCDIR_enum ++{ ++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ ++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ ++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ ++} DMA_CH_SRCDIR_t; ++ ++/* Destination adress reload mode */ ++typedef enum DMA_CH_DESTRELOAD_enum ++{ ++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ ++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ ++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ ++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ ++} DMA_CH_DESTRELOAD_t; ++ ++/* Destination adressing mode */ ++typedef enum DMA_CH_DESTDIR_enum ++{ ++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ ++} DMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum DMA_CH_TRIGSRC_enum ++{ ++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ ++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ ++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ ++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ ++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ ++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ ++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ ++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ ++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ ++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ ++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ ++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ ++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ ++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ ++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ ++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ ++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ ++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ ++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ ++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ ++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ ++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ ++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ ++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ ++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ ++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ ++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ ++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ ++} DMA_CH_TRIGSRC_t; ++ ++/* Double buffering mode */ ++typedef enum DMA_DBUFMODE_enum ++{ ++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ ++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ ++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ ++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ ++} DMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum DMA_PRIMODE_enum ++{ ++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ ++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ ++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ ++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ ++} DMA_PRIMODE_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_ERRINTLVL_enum ++{ ++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ ++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ ++} DMA_CH_ERRINTLVL_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_TRNINTLVL_enum ++{ ++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ ++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ ++} DMA_CH_TRNINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ ++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ ++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ ++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t CH4CTRL; /* Channel 4 Control Register */ ++ register8_t CH5CTRL; /* Channel 5 Control Register */ ++ register8_t CH6CTRL; /* Channel 6 Control Register */ ++ register8_t CH7CTRL; /* Channel 7 Control Register */ ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ ++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ ++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ ++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ ++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ ++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ ++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ ++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ ++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ ++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ ++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ ++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ ++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ ++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ ++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ ++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ ++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ ++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t FUSEBYTE0; /* JTAG User ID */ ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ ++ register8_t reserved_0x01; ++ register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ ++ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ ++ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ ++ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++} NVM_PROD_SIGNATURES_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++} NVM_LB_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_INSAMPLEDMODE_gc = (0x01<<2), /* BOD enabled in sampled mode */ ++ BOD_CONTINOUSLY_gc = (0x02<<2), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<2), /* BOD Disabled */ ++} BOD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brown Out Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ ++ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Comparator 0 Control */ ++ register8_t AC1CTRL; /* Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t reserved_0x6; ++ register8_t reserved_0x7; ++} ADC_CH_t; ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ _WORDREGISTER(CH1RES); /* Channel 1 Result */ ++ _WORDREGISTER(CH2RES); /* Channel 2 Result */ ++ _WORDREGISTER(CH3RES); /* Channel 3 Result */ ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++ ADC_CH_t CH1; /* ADC Channel 1 */ ++ ADC_CH_t CH2; /* ADC Channel 2 */ ++ ADC_CH_t CH3; /* ADC Channel 3 */ ++} ADC_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++} ADC_REFSEL_t; ++ ++/* Channel sweep selection */ ++typedef enum ADC_SWEEP_enum ++{ ++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ ++} ADC_SWEEP_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ++ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* DMA request selection */ ++typedef enum ADC_DMASEL_enum ++{ ++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ ++} ADC_DMASEL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DAC - Digital/Analog Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Digital-to-Analog Converter */ ++typedef struct DAC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t EVCTRL; /* Event Input Control */ ++ register8_t TIMCTRL; /* Timing Control */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t GAINCAL; /* Gain Calibration */ ++ register8_t OFFSETCAL; /* Offset Calibration */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ ++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ ++} DAC_t; ++ ++/* Output channel selection */ ++typedef enum DAC_CHSEL_enum ++{ ++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ ++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ ++} DAC_CHSEL_t; ++ ++/* Reference voltage selection */ ++typedef enum DAC_REFSEL_enum ++{ ++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ ++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ ++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ ++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ ++} DAC_REFSEL_t; ++ ++/* Event channel selection */ ++typedef enum DAC_EVSEL_enum ++{ ++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ ++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ ++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ ++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ ++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ ++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ ++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ ++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ ++} DAC_EVSEL_t; ++ ++/* Conversion interval */ ++typedef enum DAC_CONINTVAL_enum ++{ ++ DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ ++ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ ++ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ ++ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ ++ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ ++ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ ++ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ ++ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ ++} DAC_CONINTVAL_t; ++ ++/* Refresh rate */ ++typedef enum DAC_REFRESH_enum ++{ ++ DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ ++ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ ++ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ ++ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ ++ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ ++ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ ++ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ ++ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ ++ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ ++ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ ++ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ ++ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ ++ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ ++ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ ++} DAC_REFRESH_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Clounter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* EBI Chip Select Module */ ++typedef struct EBI_CS_struct ++{ ++ register8_t CTRLA; /* Chip Select Control Register A */ ++ register8_t CTRLB; /* Chip Select Control Register B */ ++ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ ++} EBI_CS_t; ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* External Bus Interface */ ++typedef struct EBI_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ ++ register8_t reserved_0x02; ++ register8_t reserved_0x03; ++ _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ ++ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ ++ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ ++ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ EBI_CS_t CS0; /* Chip Select 0 */ ++ EBI_CS_t CS1; /* Chip Select 1 */ ++ EBI_CS_t CS2; /* Chip Select 2 */ ++ EBI_CS_t CS3; /* Chip Select 3 */ ++} EBI_t; ++ ++/* Chip Select adress space */ ++typedef enum EBI_CS_ASIZE_enum ++{ ++ EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ ++ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ ++ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ ++ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ ++ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ ++ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ ++ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ ++ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ ++ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ ++ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ ++ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ ++ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ ++ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ ++ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ ++ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ ++ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ ++ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ ++} EBI_CS_ASIZE_t; ++ ++/* */ ++typedef enum EBI_CS_SRWS_enum ++{ ++ EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_CS_SRWS_t; ++ ++/* Chip Select address mode */ ++typedef enum EBI_CS_MODE_enum ++{ ++ EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ ++ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ ++ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ ++ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ ++} EBI_CS_MODE_t; ++ ++/* Chip Select SDRAM mode */ ++typedef enum EBI_CS_SDMODE_enum ++{ ++ EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ ++ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ ++} EBI_CS_SDMODE_t; ++ ++/* */ ++typedef enum EBI_SDDATAW_enum ++{ ++ EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ ++ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ ++} EBI_SDDATAW_t; ++ ++/* */ ++typedef enum EBI_LPCMODE_enum ++{ ++ EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ ++ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ ++} EBI_LPCMODE_t; ++ ++/* */ ++typedef enum EBI_SRMODE_enum ++{ ++ EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ ++ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ ++ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ ++ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ ++} EBI_SRMODE_t; ++ ++/* */ ++typedef enum EBI_IFMODE_enum ++{ ++ EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ ++ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ ++ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ ++ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ ++} EBI_IFMODE_t; ++ ++/* */ ++typedef enum EBI_SDCOL_enum ++{ ++ EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ ++ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ ++ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ ++ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ ++} EBI_SDCOL_t; ++ ++/* */ ++typedef enum EBI_MRDLY_enum ++{ ++ EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_MRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCYCDLY_enum ++{ ++ EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ROWCYCDLY_t; ++ ++/* */ ++typedef enum EBI_RPDLY_enum ++{ ++ EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_RPDLY_t; ++ ++/* */ ++typedef enum EBI_WRDLY_enum ++{ ++ EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_WRDLY_t; ++ ++/* */ ++typedef enum EBI_ESRDLY_enum ++{ ++ EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ESRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCOLDLY_enum ++{ ++ EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_ROWCOLDLY_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++} PORTCFG_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Virtual Port 0 Mapping */ ++typedef enum PORTCFG_VP0MAP_enum ++{ ++ PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP0MAP_t; ++ ++/* Virtual Port 1 Mapping */ ++typedef enum PORTCFG_VP1MAP_enum ++{ ++ PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP1MAP_t; ++ ++/* Virtual Port 2 Mapping */ ++typedef enum PORTCFG_VP2MAP_enum ++{ ++ PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP2MAP_t; ++ ++/* Virtual Port 3 Mapping */ ++typedef enum PORTCFG_VP3MAP_enum ++{ ++ PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP3MAP_t; ++ ++/* Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x05; ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AES - AES Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* AES Module */ ++typedef struct AES_struct ++{ ++ register8_t CTRL; /* AES Control Register */ ++ register8_t STATUS; /* AES Status Register */ ++ register8_t STATE; /* AES State Register */ ++ register8_t KEY; /* AES Key Register */ ++ register8_t INTCTRL; /* AES Interrupt Control Register */ ++} AES_t; ++ ++/* Interrupt level */ ++typedef enum AES_INTLVL_enum ++{ ++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} AES_INTLVL_t; ++ ++ ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset Controller */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ ++#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ ++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ ++#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ ++#define DACA (*(DAC_t *) 0x0300) /* Digitalto Analog Converter A */ ++#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ ++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ ++#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface D */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ ++#define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface F */ ++#define PORTA (*(PORT_t *) 0x0600) /* Port A */ ++#define PORTB (*(PORT_t *) 0x0620) /* Port B */ ++#define PORTC (*(PORT_t *) 0x0640) /* Port C */ ++#define PORTD (*(PORT_t *) 0x0660) /* Port D */ ++#define PORTE (*(PORT_t *) 0x0680) /* Port E */ ++#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ ++#define PORTH (*(PORT_t *) 0x06E0) /* Port H */ ++#define PORTJ (*(PORT_t *) 0x0700) /* Port J */ ++#define PORTK (*(PORT_t *) 0x0720) /* Port K */ ++#define PORTQ (*(PORT_t *) 0x07C0) /* Port Q */ ++#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ ++#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ ++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ ++#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ ++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ ++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ ++#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ ++#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ ++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ ++#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ ++#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ ++#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ ++#define TCF1 (*(TC1_t *) 0x0B40) /* Timer/Counter F1 */ ++#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ ++#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ ++#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ ++#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++#define GPIO_GPIOR4 _SFR_MEM8(0x0004) ++#define GPIO_GPIOR5 _SFR_MEM8(0x0005) ++#define GPIO_GPIOR6 _SFR_MEM8(0x0006) ++#define GPIO_GPIOR7 _SFR_MEM8(0x0007) ++#define GPIO_GPIOR8 _SFR_MEM8(0x0008) ++#define GPIO_GPIOR9 _SFR_MEM8(0x0009) ++#define GPIO_GPIORA _SFR_MEM8(0x000A) ++#define GPIO_GPIORB _SFR_MEM8(0x000B) ++#define GPIO_GPIORC _SFR_MEM8(0x000C) ++#define GPIO_GPIORD _SFR_MEM8(0x000D) ++#define GPIO_GPIORE _SFR_MEM8(0x000E) ++#define GPIO_GPIORF _SFR_MEM8(0x000F) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++#define GPIO_GPIO4 _SFR_MEM8(0x0004) ++#define GPIO_GPIO5 _SFR_MEM8(0x0005) ++#define GPIO_GPIO6 _SFR_MEM8(0x0006) ++#define GPIO_GPIO7 _SFR_MEM8(0x0007) ++#define GPIO_GPIO8 _SFR_MEM8(0x0008) ++#define GPIO_GPIO9 _SFR_MEM8(0x0009) ++#define GPIO_GPIOA _SFR_MEM8(0x000A) ++#define GPIO_GPIOB _SFR_MEM8(0x000B) ++#define GPIO_GPIOC _SFR_MEM8(0x000C) ++#define GPIO_GPIOD _SFR_MEM8(0x000D) ++#define GPIO_GPIOE _SFR_MEM8(0x000E) ++#define GPIO_GPIOF _SFR_MEM8(0x000F) ++ ++/* VPORT0 - Virtual Port 0 */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT1 - Virtual Port 1 */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT2 - Virtual Port 2 */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT3 - Virtual Port 3 */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU Registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator Control */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPB _SFR_MEM8(0x0072) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset Controller */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - Port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++ ++/* AES - AES Crypto Module */ ++#define AES_CTRL _SFR_MEM8(0x00C0) ++#define AES_STATUS _SFR_MEM8(0x00C1) ++#define AES_STATE _SFR_MEM8(0x00C2) ++#define AES_KEY _SFR_MEM8(0x00C3) ++#define AES_INTCTRL _SFR_MEM8(0x00C4) ++ ++/* DMA - DMA Controller */ ++#define DMA_CTRL _SFR_MEM8(0x0100) ++#define DMA_INTFLAGS _SFR_MEM8(0x0103) ++#define DMA_STATUS _SFR_MEM8(0x0104) ++#define DMA_TEMP _SFR_MEM16(0x0106) ++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) ++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) ++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) ++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) ++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) ++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) ++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) ++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) ++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) ++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) ++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) ++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) ++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) ++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) ++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) ++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) ++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) ++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) ++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) ++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) ++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) ++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) ++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) ++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) ++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) ++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) ++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) ++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) ++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) ++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) ++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) ++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) ++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) ++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) ++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) ++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) ++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) ++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) ++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) ++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) ++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) ++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH4MUX _SFR_MEM8(0x0184) ++#define EVSYS_CH5MUX _SFR_MEM8(0x0185) ++#define EVSYS_CH6MUX _SFR_MEM8(0x0186) ++#define EVSYS_CH7MUX _SFR_MEM8(0x0187) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) ++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) ++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) ++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non Volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADCA - Analog to Digital Converter A */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CH1RES _SFR_MEM16(0x0212) ++#define ADCA_CH2RES _SFR_MEM16(0x0214) ++#define ADCA_CH3RES _SFR_MEM16(0x0216) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) ++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) ++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) ++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) ++#define ADCA_CH1_RES _SFR_MEM16(0x022C) ++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) ++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) ++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) ++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) ++#define ADCA_CH2_RES _SFR_MEM16(0x0234) ++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) ++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) ++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) ++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) ++#define ADCA_CH3_RES _SFR_MEM16(0x023C) ++ ++/* ADCB - Analog to Digital Converter B */ ++#define ADCB_CTRLA _SFR_MEM8(0x0240) ++#define ADCB_CTRLB _SFR_MEM8(0x0241) ++#define ADCB_REFCTRL _SFR_MEM8(0x0242) ++#define ADCB_EVCTRL _SFR_MEM8(0x0243) ++#define ADCB_PRESCALER _SFR_MEM8(0x0244) ++#define ADCB_INTFLAGS _SFR_MEM8(0x0246) ++#define ADCB_CAL _SFR_MEM16(0x024C) ++#define ADCB_CH0RES _SFR_MEM16(0x0250) ++#define ADCB_CH1RES _SFR_MEM16(0x0252) ++#define ADCB_CH2RES _SFR_MEM16(0x0254) ++#define ADCB_CH3RES _SFR_MEM16(0x0256) ++#define ADCB_CMP _SFR_MEM16(0x0258) ++#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) ++#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) ++#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) ++#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) ++#define ADCB_CH0_RES _SFR_MEM16(0x0264) ++#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) ++#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) ++#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) ++#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) ++#define ADCB_CH1_RES _SFR_MEM16(0x026C) ++#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) ++#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) ++#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) ++#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) ++#define ADCB_CH2_RES _SFR_MEM16(0x0274) ++#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) ++#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) ++#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) ++#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) ++#define ADCB_CH3_RES _SFR_MEM16(0x027C) ++ ++/* DACA - Digitalto Analog Converter A */ ++#define DACA_CTRLA _SFR_MEM8(0x0300) ++#define DACA_CTRLB _SFR_MEM8(0x0301) ++#define DACA_CTRLC _SFR_MEM8(0x0302) ++#define DACA_EVCTRL _SFR_MEM8(0x0303) ++#define DACA_TIMCTRL _SFR_MEM8(0x0304) ++#define DACA_STATUS _SFR_MEM8(0x0305) ++#define DACA_GAINCAL _SFR_MEM8(0x0308) ++#define DACA_OFFSETCAL _SFR_MEM8(0x0309) ++#define DACA_CH0DATA _SFR_MEM16(0x0318) ++#define DACA_CH1DATA _SFR_MEM16(0x031A) ++ ++/* DACB - Digital to Analog Converter B */ ++#define DACB_CTRLA _SFR_MEM8(0x0320) ++#define DACB_CTRLB _SFR_MEM8(0x0321) ++#define DACB_CTRLC _SFR_MEM8(0x0322) ++#define DACB_EVCTRL _SFR_MEM8(0x0323) ++#define DACB_TIMCTRL _SFR_MEM8(0x0324) ++#define DACB_STATUS _SFR_MEM8(0x0325) ++#define DACB_GAINCAL _SFR_MEM8(0x0328) ++#define DACB_OFFSETCAL _SFR_MEM8(0x0329) ++#define DACB_CH0DATA _SFR_MEM16(0x0338) ++#define DACB_CH1DATA _SFR_MEM16(0x033A) ++ ++/* ACA - Analog Comparator A */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* ACB - Analog Comparator B */ ++#define ACB_AC0CTRL _SFR_MEM8(0x0390) ++#define ACB_AC1CTRL _SFR_MEM8(0x0391) ++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) ++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) ++#define ACB_CTRLA _SFR_MEM8(0x0394) ++#define ACB_CTRLB _SFR_MEM8(0x0395) ++#define ACB_WINCTRL _SFR_MEM8(0x0396) ++#define ACB_STATUS _SFR_MEM8(0x0397) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* EBI - External Bus Interface */ ++#define EBI_CTRL _SFR_MEM8(0x0440) ++#define EBI_SDRAMCTRLA _SFR_MEM8(0x0441) ++#define EBI_REFRESH _SFR_MEM16(0x0444) ++#define EBI_INITDLY _SFR_MEM16(0x0446) ++#define EBI_SDRAMCTRLB _SFR_MEM8(0x0448) ++#define EBI_SDRAMCTRLC _SFR_MEM8(0x0449) ++#define EBI_CS0_CTRLA _SFR_MEM8(0x0450) ++#define EBI_CS0_CTRLB _SFR_MEM8(0x0451) ++#define EBI_CS0_BASEADDR _SFR_MEM16(0x0452) ++#define EBI_CS1_CTRLA _SFR_MEM8(0x0454) ++#define EBI_CS1_CTRLB _SFR_MEM8(0x0455) ++#define EBI_CS1_BASEADDR _SFR_MEM16(0x0456) ++#define EBI_CS2_CTRLA _SFR_MEM8(0x0458) ++#define EBI_CS2_CTRLB _SFR_MEM8(0x0459) ++#define EBI_CS2_BASEADDR _SFR_MEM16(0x045A) ++#define EBI_CS3_CTRLA _SFR_MEM8(0x045C) ++#define EBI_CS3_CTRLB _SFR_MEM8(0x045D) ++#define EBI_CS3_BASEADDR _SFR_MEM16(0x045E) ++ ++/* TWIC - Two-Wire Interface C */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWID - Two-Wire Interface D */ ++#define TWID_CTRL _SFR_MEM8(0x0490) ++#define TWID_MASTER_CTRLA _SFR_MEM8(0x0491) ++#define TWID_MASTER_CTRLB _SFR_MEM8(0x0492) ++#define TWID_MASTER_CTRLC _SFR_MEM8(0x0493) ++#define TWID_MASTER_STATUS _SFR_MEM8(0x0494) ++#define TWID_MASTER_BAUD _SFR_MEM8(0x0495) ++#define TWID_MASTER_ADDR _SFR_MEM8(0x0496) ++#define TWID_MASTER_DATA _SFR_MEM8(0x0497) ++#define TWID_SLAVE_CTRLA _SFR_MEM8(0x0498) ++#define TWID_SLAVE_CTRLB _SFR_MEM8(0x0499) ++#define TWID_SLAVE_STATUS _SFR_MEM8(0x049A) ++#define TWID_SLAVE_ADDR _SFR_MEM8(0x049B) ++#define TWID_SLAVE_DATA _SFR_MEM8(0x049C) ++#define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D) ++ ++/* TWIE - Two-Wire Interface E */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* TWIF - Two-Wire Interface F */ ++#define TWIF_CTRL _SFR_MEM8(0x04B0) ++#define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1) ++#define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2) ++#define TWIF_MASTER_CTRLC _SFR_MEM8(0x04B3) ++#define TWIF_MASTER_STATUS _SFR_MEM8(0x04B4) ++#define TWIF_MASTER_BAUD _SFR_MEM8(0x04B5) ++#define TWIF_MASTER_ADDR _SFR_MEM8(0x04B6) ++#define TWIF_MASTER_DATA _SFR_MEM8(0x04B7) ++#define TWIF_SLAVE_CTRLA _SFR_MEM8(0x04B8) ++#define TWIF_SLAVE_CTRLB _SFR_MEM8(0x04B9) ++#define TWIF_SLAVE_STATUS _SFR_MEM8(0x04BA) ++#define TWIF_SLAVE_ADDR _SFR_MEM8(0x04BB) ++#define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC) ++#define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD) ++ ++/* PORTA - Port A */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORTB - Port B */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORTC - Port C */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORTD - Port D */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORTE - Port E */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORTF - Port F */ ++#define PORTF_DIR _SFR_MEM8(0x06A0) ++#define PORTF_DIRSET _SFR_MEM8(0x06A1) ++#define PORTF_DIRCLR _SFR_MEM8(0x06A2) ++#define PORTF_DIRTGL _SFR_MEM8(0x06A3) ++#define PORTF_OUT _SFR_MEM8(0x06A4) ++#define PORTF_OUTSET _SFR_MEM8(0x06A5) ++#define PORTF_OUTCLR _SFR_MEM8(0x06A6) ++#define PORTF_OUTTGL _SFR_MEM8(0x06A7) ++#define PORTF_IN _SFR_MEM8(0x06A8) ++#define PORTF_INTCTRL _SFR_MEM8(0x06A9) ++#define PORTF_INT0MASK _SFR_MEM8(0x06AA) ++#define PORTF_INT1MASK _SFR_MEM8(0x06AB) ++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) ++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) ++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) ++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) ++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) ++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) ++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) ++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) ++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) ++ ++/* PORTH - Port H */ ++#define PORTH_DIR _SFR_MEM8(0x06E0) ++#define PORTH_DIRSET _SFR_MEM8(0x06E1) ++#define PORTH_DIRCLR _SFR_MEM8(0x06E2) ++#define PORTH_DIRTGL _SFR_MEM8(0x06E3) ++#define PORTH_OUT _SFR_MEM8(0x06E4) ++#define PORTH_OUTSET _SFR_MEM8(0x06E5) ++#define PORTH_OUTCLR _SFR_MEM8(0x06E6) ++#define PORTH_OUTTGL _SFR_MEM8(0x06E7) ++#define PORTH_IN _SFR_MEM8(0x06E8) ++#define PORTH_INTCTRL _SFR_MEM8(0x06E9) ++#define PORTH_INT0MASK _SFR_MEM8(0x06EA) ++#define PORTH_INT1MASK _SFR_MEM8(0x06EB) ++#define PORTH_INTFLAGS _SFR_MEM8(0x06EC) ++#define PORTH_PIN0CTRL _SFR_MEM8(0x06F0) ++#define PORTH_PIN1CTRL _SFR_MEM8(0x06F1) ++#define PORTH_PIN2CTRL _SFR_MEM8(0x06F2) ++#define PORTH_PIN3CTRL _SFR_MEM8(0x06F3) ++#define PORTH_PIN4CTRL _SFR_MEM8(0x06F4) ++#define PORTH_PIN5CTRL _SFR_MEM8(0x06F5) ++#define PORTH_PIN6CTRL _SFR_MEM8(0x06F6) ++#define PORTH_PIN7CTRL _SFR_MEM8(0x06F7) ++ ++/* PORTJ - Port J */ ++#define PORTJ_DIR _SFR_MEM8(0x0700) ++#define PORTJ_DIRSET _SFR_MEM8(0x0701) ++#define PORTJ_DIRCLR _SFR_MEM8(0x0702) ++#define PORTJ_DIRTGL _SFR_MEM8(0x0703) ++#define PORTJ_OUT _SFR_MEM8(0x0704) ++#define PORTJ_OUTSET _SFR_MEM8(0x0705) ++#define PORTJ_OUTCLR _SFR_MEM8(0x0706) ++#define PORTJ_OUTTGL _SFR_MEM8(0x0707) ++#define PORTJ_IN _SFR_MEM8(0x0708) ++#define PORTJ_INTCTRL _SFR_MEM8(0x0709) ++#define PORTJ_INT0MASK _SFR_MEM8(0x070A) ++#define PORTJ_INT1MASK _SFR_MEM8(0x070B) ++#define PORTJ_INTFLAGS _SFR_MEM8(0x070C) ++#define PORTJ_PIN0CTRL _SFR_MEM8(0x0710) ++#define PORTJ_PIN1CTRL _SFR_MEM8(0x0711) ++#define PORTJ_PIN2CTRL _SFR_MEM8(0x0712) ++#define PORTJ_PIN3CTRL _SFR_MEM8(0x0713) ++#define PORTJ_PIN4CTRL _SFR_MEM8(0x0714) ++#define PORTJ_PIN5CTRL _SFR_MEM8(0x0715) ++#define PORTJ_PIN6CTRL _SFR_MEM8(0x0716) ++#define PORTJ_PIN7CTRL _SFR_MEM8(0x0717) ++ ++/* PORTK - Port K */ ++#define PORTK_DIR _SFR_MEM8(0x0720) ++#define PORTK_DIRSET _SFR_MEM8(0x0721) ++#define PORTK_DIRCLR _SFR_MEM8(0x0722) ++#define PORTK_DIRTGL _SFR_MEM8(0x0723) ++#define PORTK_OUT _SFR_MEM8(0x0724) ++#define PORTK_OUTSET _SFR_MEM8(0x0725) ++#define PORTK_OUTCLR _SFR_MEM8(0x0726) ++#define PORTK_OUTTGL _SFR_MEM8(0x0727) ++#define PORTK_IN _SFR_MEM8(0x0728) ++#define PORTK_INTCTRL _SFR_MEM8(0x0729) ++#define PORTK_INT0MASK _SFR_MEM8(0x072A) ++#define PORTK_INT1MASK _SFR_MEM8(0x072B) ++#define PORTK_INTFLAGS _SFR_MEM8(0x072C) ++#define PORTK_PIN0CTRL _SFR_MEM8(0x0730) ++#define PORTK_PIN1CTRL _SFR_MEM8(0x0731) ++#define PORTK_PIN2CTRL _SFR_MEM8(0x0732) ++#define PORTK_PIN3CTRL _SFR_MEM8(0x0733) ++#define PORTK_PIN4CTRL _SFR_MEM8(0x0734) ++#define PORTK_PIN5CTRL _SFR_MEM8(0x0735) ++#define PORTK_PIN6CTRL _SFR_MEM8(0x0736) ++#define PORTK_PIN7CTRL _SFR_MEM8(0x0737) ++ ++/* PORTQ - Port Q */ ++#define PORTQ_DIR _SFR_MEM8(0x07C0) ++#define PORTQ_DIRSET _SFR_MEM8(0x07C1) ++#define PORTQ_DIRCLR _SFR_MEM8(0x07C2) ++#define PORTQ_DIRTGL _SFR_MEM8(0x07C3) ++#define PORTQ_OUT _SFR_MEM8(0x07C4) ++#define PORTQ_OUTSET _SFR_MEM8(0x07C5) ++#define PORTQ_OUTCLR _SFR_MEM8(0x07C6) ++#define PORTQ_OUTTGL _SFR_MEM8(0x07C7) ++#define PORTQ_IN _SFR_MEM8(0x07C8) ++#define PORTQ_INTCTRL _SFR_MEM8(0x07C9) ++#define PORTQ_INT0MASK _SFR_MEM8(0x07CA) ++#define PORTQ_INT1MASK _SFR_MEM8(0x07CB) ++#define PORTQ_INTFLAGS _SFR_MEM8(0x07CC) ++#define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0) ++#define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1) ++#define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2) ++#define PORTQ_PIN3CTRL _SFR_MEM8(0x07D3) ++#define PORTQ_PIN4CTRL _SFR_MEM8(0x07D4) ++#define PORTQ_PIN5CTRL _SFR_MEM8(0x07D5) ++#define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6) ++#define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7) ++ ++/* PORTR - Port R */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TCC0 - Timer/Counter C0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TCC1 - Timer/Counter C1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEXC - Advanced Waveform Extension C */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRESC - High-Resolution Extension C */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ ++#define USARTC1_DATA _SFR_MEM8(0x08B0) ++#define USARTC1_STATUS _SFR_MEM8(0x08B1) ++#define USARTC1_CTRLA _SFR_MEM8(0x08B3) ++#define USARTC1_CTRLB _SFR_MEM8(0x08B4) ++#define USARTC1_CTRLC _SFR_MEM8(0x08B5) ++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) ++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) ++ ++/* SPIC - Serial Peripheral Interface C */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TCD0 - Timer/Counter D0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TCD1 - Timer/Counter D1 */ ++#define TCD1_CTRLA _SFR_MEM8(0x0940) ++#define TCD1_CTRLB _SFR_MEM8(0x0941) ++#define TCD1_CTRLC _SFR_MEM8(0x0942) ++#define TCD1_CTRLD _SFR_MEM8(0x0943) ++#define TCD1_CTRLE _SFR_MEM8(0x0944) ++#define TCD1_INTCTRLA _SFR_MEM8(0x0946) ++#define TCD1_INTCTRLB _SFR_MEM8(0x0947) ++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) ++#define TCD1_CTRLFSET _SFR_MEM8(0x0949) ++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) ++#define TCD1_CTRLGSET _SFR_MEM8(0x094B) ++#define TCD1_INTFLAGS _SFR_MEM8(0x094C) ++#define TCD1_TEMP _SFR_MEM8(0x094F) ++#define TCD1_CNT _SFR_MEM16(0x0960) ++#define TCD1_PER _SFR_MEM16(0x0966) ++#define TCD1_CCA _SFR_MEM16(0x0968) ++#define TCD1_CCB _SFR_MEM16(0x096A) ++#define TCD1_PERBUF _SFR_MEM16(0x0976) ++#define TCD1_CCABUF _SFR_MEM16(0x0978) ++#define TCD1_CCBBUF _SFR_MEM16(0x097A) ++ ++/* HIRESD - High-Resolution Extension D */ ++#define HIRESD_CTRLA _SFR_MEM8(0x0990) ++ ++/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ ++#define USARTD1_DATA _SFR_MEM8(0x09B0) ++#define USARTD1_STATUS _SFR_MEM8(0x09B1) ++#define USARTD1_CTRLA _SFR_MEM8(0x09B3) ++#define USARTD1_CTRLB _SFR_MEM8(0x09B4) ++#define USARTD1_CTRLC _SFR_MEM8(0x09B5) ++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) ++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) ++ ++/* SPID - Serial Peripheral Interface D */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TCE0 - Timer/Counter E0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* TCE1 - Timer/Counter E1 */ ++#define TCE1_CTRLA _SFR_MEM8(0x0A40) ++#define TCE1_CTRLB _SFR_MEM8(0x0A41) ++#define TCE1_CTRLC _SFR_MEM8(0x0A42) ++#define TCE1_CTRLD _SFR_MEM8(0x0A43) ++#define TCE1_CTRLE _SFR_MEM8(0x0A44) ++#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) ++#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) ++#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) ++#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) ++#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) ++#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) ++#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) ++#define TCE1_TEMP _SFR_MEM8(0x0A4F) ++#define TCE1_CNT _SFR_MEM16(0x0A60) ++#define TCE1_PER _SFR_MEM16(0x0A66) ++#define TCE1_CCA _SFR_MEM16(0x0A68) ++#define TCE1_CCB _SFR_MEM16(0x0A6A) ++#define TCE1_PERBUF _SFR_MEM16(0x0A76) ++#define TCE1_CCABUF _SFR_MEM16(0x0A78) ++#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) ++ ++/* AWEXE - Advanced Waveform Extension E */ ++#define AWEXE_CTRL _SFR_MEM8(0x0A80) ++#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) ++#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) ++#define AWEXE_STATUS _SFR_MEM8(0x0A84) ++#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) ++#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) ++#define AWEXE_DTLS _SFR_MEM8(0x0A88) ++#define AWEXE_DTHS _SFR_MEM8(0x0A89) ++#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) ++#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) ++#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) ++ ++/* HIRESE - High-Resolution Extension E */ ++#define HIRESE_CTRLA _SFR_MEM8(0x0A90) ++ ++/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ ++#define USARTE1_DATA _SFR_MEM8(0x0AB0) ++#define USARTE1_STATUS _SFR_MEM8(0x0AB1) ++#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) ++#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) ++#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) ++#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) ++#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) ++ ++/* SPIE - Serial Peripheral Interface E */ ++#define SPIE_CTRL _SFR_MEM8(0x0AC0) ++#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) ++#define SPIE_STATUS _SFR_MEM8(0x0AC2) ++#define SPIE_DATA _SFR_MEM8(0x0AC3) ++ ++/* TCF0 - Timer/Counter F0 */ ++#define TCF0_CTRLA _SFR_MEM8(0x0B00) ++#define TCF0_CTRLB _SFR_MEM8(0x0B01) ++#define TCF0_CTRLC _SFR_MEM8(0x0B02) ++#define TCF0_CTRLD _SFR_MEM8(0x0B03) ++#define TCF0_CTRLE _SFR_MEM8(0x0B04) ++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) ++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) ++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) ++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) ++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF0_TEMP _SFR_MEM8(0x0B0F) ++#define TCF0_CNT _SFR_MEM16(0x0B20) ++#define TCF0_PER _SFR_MEM16(0x0B26) ++#define TCF0_CCA _SFR_MEM16(0x0B28) ++#define TCF0_CCB _SFR_MEM16(0x0B2A) ++#define TCF0_CCC _SFR_MEM16(0x0B2C) ++#define TCF0_CCD _SFR_MEM16(0x0B2E) ++#define TCF0_PERBUF _SFR_MEM16(0x0B36) ++#define TCF0_CCABUF _SFR_MEM16(0x0B38) ++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) ++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) ++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) ++ ++/* TCF1 - Timer/Counter F1 */ ++#define TCF1_CTRLA _SFR_MEM8(0x0B40) ++#define TCF1_CTRLB _SFR_MEM8(0x0B41) ++#define TCF1_CTRLC _SFR_MEM8(0x0B42) ++#define TCF1_CTRLD _SFR_MEM8(0x0B43) ++#define TCF1_CTRLE _SFR_MEM8(0x0B44) ++#define TCF1_INTCTRLA _SFR_MEM8(0x0B46) ++#define TCF1_INTCTRLB _SFR_MEM8(0x0B47) ++#define TCF1_CTRLFCLR _SFR_MEM8(0x0B48) ++#define TCF1_CTRLFSET _SFR_MEM8(0x0B49) ++#define TCF1_CTRLGCLR _SFR_MEM8(0x0B4A) ++#define TCF1_CTRLGSET _SFR_MEM8(0x0B4B) ++#define TCF1_INTFLAGS _SFR_MEM8(0x0B4C) ++#define TCF1_TEMP _SFR_MEM8(0x0B4F) ++#define TCF1_CNT _SFR_MEM16(0x0B60) ++#define TCF1_PER _SFR_MEM16(0x0B66) ++#define TCF1_CCA _SFR_MEM16(0x0B68) ++#define TCF1_CCB _SFR_MEM16(0x0B6A) ++#define TCF1_PERBUF _SFR_MEM16(0x0B76) ++#define TCF1_CCABUF _SFR_MEM16(0x0B78) ++#define TCF1_CCBBUF _SFR_MEM16(0x0B7A) ++ ++/* HIRESF - High-Resolution Extension F */ ++#define HIRESF_CTRLA _SFR_MEM8(0x0B90) ++ ++/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ ++#define USARTF0_DATA _SFR_MEM8(0x0BA0) ++#define USARTF0_STATUS _SFR_MEM8(0x0BA1) ++#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) ++#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) ++#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) ++#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) ++#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) ++ ++/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ ++#define USARTF1_DATA _SFR_MEM8(0x0BB0) ++#define USARTF1_STATUS _SFR_MEM8(0x0BB1) ++#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) ++#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) ++#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) ++#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) ++#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) ++ ++/* SPIF - Serial Peripheral Interface F */ ++#define SPIF_CTRL _SFR_MEM8(0x0BC0) ++#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) ++#define SPIF_STATUS _SFR_MEM8(0x0BC2) ++#define SPIF_DATA _SFR_MEM8(0x0BC3) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR1 bit masks and bit positions */ ++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ ++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ ++ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ ++ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ ++#define PR_EBI_bp 3 /* External Bus Interface bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ ++#define PR_DAC_bp 2 /* Port A DAC bit position. */ ++ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++ ++/* PR.PRPB bit masks and bit positions */ ++/* PR_DAC_bm Predefined. */ ++/* PR_DAC_bp Predefined. */ ++ ++/* PR_ADC_bm Predefined. */ ++/* PR_ADC_bp Predefined. */ ++ ++/* PR_AC_bm Predefined. */ ++/* PR_AC_bp Predefined. */ ++ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ ++ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ ++ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ ++ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ ++#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ ++ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ ++ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ ++ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ ++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ ++ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++ ++/* DMA - DMA Controller */ ++/* DMA_CH.CTRLA bit masks and bit positions */ ++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ ++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ ++ ++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ ++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ ++ ++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ ++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ ++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ ++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ ++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ ++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ ++ ++ ++/* DMA_CH.CTRLB bit masks and bit positions */ ++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ ++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ ++ ++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ ++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ ++ ++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ ++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ ++ ++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ ++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ ++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ ++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ ++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ ++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ ++ ++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ ++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ ++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ ++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ ++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ ++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ ++ ++ ++/* DMA_CH.ADDRCTRL bit masks and bit positions */ ++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ ++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ ++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ ++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ ++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ ++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ ++ ++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ ++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ ++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ ++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ ++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ ++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ ++ ++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ ++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ ++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ ++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ ++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ ++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ ++ ++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ ++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ ++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ ++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ ++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ ++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ ++ ++ ++/* DMA_CH.TRIGSRC bit masks and bit positions */ ++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++ ++/* DMA.CTRL bit masks and bit positions */ ++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define DMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define DMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ ++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ ++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ ++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ ++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ ++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ ++ ++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ ++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ ++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ ++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ ++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ ++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ ++ ++ ++/* DMA.INTFLAGS bit masks and bit positions */ ++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++ ++/* DMA.STATUS bit masks and bit positions */ ++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ ++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ ++ ++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ ++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ ++ ++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ ++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ ++ ++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ ++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ ++ ++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ ++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ ++ ++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ ++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ ++ ++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ ++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ ++ ++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ ++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ ++ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH4MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH5MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH6MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH7MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM_gm Predefined. */ ++/* EVSYS_QDIRM_gp Predefined. */ ++/* EVSYS_QDIRM0_bm Predefined. */ ++/* EVSYS_QDIRM0_bp Predefined. */ ++/* EVSYS_QDIRM1_bm Predefined. */ ++/* EVSYS_QDIRM1_bp Predefined. */ ++ ++/* EVSYS_QDIEN_bm Predefined. */ ++/* EVSYS_QDIEN_bp Predefined. */ ++ ++/* EVSYS_QDEN_bm Predefined. */ ++/* EVSYS_QDEN_bp Predefined. */ ++ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH4CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM_gm Predefined. */ ++/* EVSYS_QDIRM_gp Predefined. */ ++/* EVSYS_QDIRM0_bm Predefined. */ ++/* EVSYS_QDIRM0_bp Predefined. */ ++/* EVSYS_QDIRM1_bm Predefined. */ ++/* EVSYS_QDIRM1_bp Predefined. */ ++ ++/* EVSYS_QDIEN_bm Predefined. */ ++/* EVSYS_QDIEN_bp Predefined. */ ++ ++/* EVSYS_QDEN_bm Predefined. */ ++/* EVSYS_QDEN_bp Predefined. */ ++ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH5CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH6CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH7CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0xFF /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ ++#define NVM_CMD7_bp 7 /* Command bit 7 position. */ ++ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ ++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ ++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ ++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ ++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ ++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ ++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ ++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ ++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ ++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ ++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ ++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ ++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ ++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ ++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ ++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ ++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ ++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ ++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ ++#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ ++ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_BODACT_gm 0x0C /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 2 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<2) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 2 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<3) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 3 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ ++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ ++ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ ++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE_gm Predefined. */ ++/* AC_INTMODE_gp Predefined. */ ++/* AC_INTMODE0_bm Predefined. */ ++/* AC_INTMODE0_bp Predefined. */ ++/* AC_INTMODE1_bm Predefined. */ ++/* AC_INTMODE1_bp Predefined. */ ++ ++/* AC_INTLVL_gm Predefined. */ ++/* AC_INTLVL_gp Predefined. */ ++/* AC_INTLVL0_bm Predefined. */ ++/* AC_INTLVL0_bp Predefined. */ ++/* AC_INTLVL1_bm Predefined. */ ++/* AC_INTLVL1_bp Predefined. */ ++ ++/* AC_HSMODE_bm Predefined. */ ++/* AC_HSMODE_bp Predefined. */ ++ ++/* AC_HYSMODE_gm Predefined. */ ++/* AC_HYSMODE_gp Predefined. */ ++/* AC_HYSMODE0_bm Predefined. */ ++/* AC_HYSMODE0_bp Predefined. */ ++/* AC_HYSMODE1_bm Predefined. */ ++/* AC_HYSMODE1_bp Predefined. */ ++ ++/* AC_ENABLE_bm Predefined. */ ++/* AC_ENABLE_bp Predefined. */ ++ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS_gm Predefined. */ ++/* AC_MUXPOS_gp Predefined. */ ++/* AC_MUXPOS0_bm Predefined. */ ++/* AC_MUXPOS0_bp Predefined. */ ++/* AC_MUXPOS1_bm Predefined. */ ++/* AC_MUXPOS1_bp Predefined. */ ++/* AC_MUXPOS2_bm Predefined. */ ++/* AC_MUXPOS2_bp Predefined. */ ++ ++/* AC_MUXNEG_gm Predefined. */ ++/* AC_MUXNEG_gp Predefined. */ ++/* AC_MUXNEG0_bm Predefined. */ ++/* AC_MUXNEG0_bp Predefined. */ ++/* AC_MUXNEG1_bm Predefined. */ ++/* AC_MUXNEG1_bp Predefined. */ ++/* AC_MUXNEG2_bm Predefined. */ ++/* AC_MUXNEG2_bp Predefined. */ ++ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ ++ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ ++ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ ++ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ ++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ ++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ ++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ ++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ ++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ ++ ++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ ++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ ++ ++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ ++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ ++ ++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ ++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ ++ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ ++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ ++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ ++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ ++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ ++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ ++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ ++ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ ++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ ++ ++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ ++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ ++ ++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ ++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ ++ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++ ++/* DAC - Digital/Analog Converter */ ++/* DAC.CTRLA bit masks and bit positions */ ++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ ++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ ++ ++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ ++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ ++ ++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ ++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ ++ ++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ ++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ ++ ++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define DAC_ENABLE_bp 0 /* Enable bit position. */ ++ ++ ++/* DAC.CTRLB bit masks and bit positions */ ++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ ++#define DAC_CHSEL_gp 5 /* Channel Select group position. */ ++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ ++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ ++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ ++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ ++ ++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ ++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ ++ ++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ ++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ ++ ++ ++/* DAC.CTRLC bit masks and bit positions */ ++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ ++#define DAC_REFSEL_gp 3 /* Reference Select group position. */ ++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ ++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ ++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ ++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ ++ ++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ ++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ ++ ++ ++/* DAC.EVCTRL bit masks and bit positions */ ++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ ++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ ++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ ++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ ++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ ++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ ++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ ++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ ++ ++ ++/* DAC.TIMCTRL bit masks and bit positions */ ++#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ ++#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ ++#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ ++#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ ++#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ ++#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ ++#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ ++#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ ++ ++#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ ++#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ ++#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ ++#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ ++#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ ++#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ ++#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ ++#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ ++#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ ++#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ ++ ++ ++/* DAC.STATUS bit masks and bit positions */ ++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ ++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ ++ ++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ ++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ ++ ++ ++/* RTC - Real-Time Clounter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* EBI - External Bus Interface */ ++/* EBI_CS.CTRLA bit masks and bit positions */ ++#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ ++#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ ++#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ ++#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ ++#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ ++#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ ++#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ ++#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ ++#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ ++#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ ++#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ ++#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ ++ ++#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ ++#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ ++#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ ++#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ ++#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ ++#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ ++ ++ ++/* EBI_CS.CTRLB bit masks and bit positions */ ++#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ ++#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ ++#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ ++#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ ++#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ ++#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ ++#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ ++#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ ++ ++#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ ++#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ ++ ++#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ ++#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ ++ ++#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ ++#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ ++#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ ++#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ ++#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ ++#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ ++ ++ ++/* EBI.CTRL bit masks and bit positions */ ++#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ ++#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ ++#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ ++#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ ++#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ ++#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ ++ ++#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ ++#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ ++#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ ++#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ ++#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ ++#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ ++ ++#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ ++#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ ++#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ ++#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ ++#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ ++#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ ++ ++#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ ++#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ ++#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ ++#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ ++#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ ++#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLA bit masks and bit positions */ ++#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ ++#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ ++ ++#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ ++#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ ++ ++#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ ++#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ ++#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ ++#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ ++#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ ++#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLB bit masks and bit positions */ ++#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ ++#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ ++#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ ++#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ ++#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ ++#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ ++ ++#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ ++#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ ++#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ ++#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ ++#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ ++#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ ++#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ ++#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ ++ ++#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ ++#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ ++#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ ++#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ ++#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ ++#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ ++#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ ++#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ ++ ++ ++/* EBI.SDRAMCTRLC bit masks and bit positions */ ++#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ ++#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ ++#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ ++#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ ++#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ ++#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ ++ ++#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ ++#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ ++#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ ++#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ ++#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ ++#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ ++#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ ++#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ ++ ++#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ ++#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ ++#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ ++#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ ++#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ ++#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ ++#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ ++#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ ++ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ ++#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++ ++/* PORT - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ ++#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ ++ ++#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD_gm Predefined. */ ++/* TC0_CMD_gp Predefined. */ ++/* TC0_CMD0_bm Predefined. */ ++/* TC0_CMD0_bp Predefined. */ ++/* TC0_CMD1_bm Predefined. */ ++/* TC0_CMD1_bp Predefined. */ ++ ++/* TC0_LUPD_bm Predefined. */ ++/* TC0_LUPD_bp Predefined. */ ++ ++/* TC0_DIR_bm Predefined. */ ++/* TC0_DIR_bp Predefined. */ ++ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV_bm Predefined. */ ++/* TC0_CCDBV_bp Predefined. */ ++ ++/* TC0_CCCBV_bm Predefined. */ ++/* TC0_CCCBV_bp Predefined. */ ++ ++/* TC0_CCBBV_bm Predefined. */ ++/* TC0_CCBBV_bp Predefined. */ ++ ++/* TC0_CCABV_bm Predefined. */ ++/* TC0_CCABV_bp Predefined. */ ++ ++/* TC0_PERBV_bm Predefined. */ ++/* TC0_PERBV_bp Predefined. */ ++ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ ++#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ ++ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD_gm Predefined. */ ++/* TC1_CMD_gp Predefined. */ ++/* TC1_CMD0_bm Predefined. */ ++/* TC1_CMD0_bp Predefined. */ ++/* TC1_CMD1_bm Predefined. */ ++/* TC1_CMD1_bp Predefined. */ ++ ++/* TC1_LUPD_bm Predefined. */ ++/* TC1_LUPD_bp Predefined. */ ++ ++/* TC1_DIR_bm Predefined. */ ++/* TC1_DIR_bp Predefined. */ ++ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV_bm Predefined. */ ++/* TC1_CCBBV_bp Predefined. */ ++ ++/* TC1_CCABV_bm Predefined. */ ++/* TC1_CCABV_bp Predefined. */ ++ ++/* TC1_PERBV_bm Predefined. */ ++/* TC1_PERBV_bp Predefined. */ ++ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++ ++/* HIRES.CTRL bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL_gm Predefined. */ ++/* USART_BSEL_gp Predefined. */ ++/* USART_BSEL0_bm Predefined. */ ++/* USART_BSEL0_bp Predefined. */ ++/* USART_BSEL1_bm Predefined. */ ++/* USART_BSEL1_bp Predefined. */ ++/* USART_BSEL2_bm Predefined. */ ++/* USART_BSEL2_bp Predefined. */ ++/* USART_BSEL3_bm Predefined. */ ++/* USART_BSEL3_bp Predefined. */ ++ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++ ++/* AES - AES Module */ ++/* AES.CTRL bit masks and bit positions */ ++#define AES_START_bm 0x80 /* Start/Run bit mask. */ ++#define AES_START_bp 7 /* Start/Run bit position. */ ++ ++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ ++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ ++ ++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ ++#define AES_RESET_bp 5 /* AES Software Reset bit position. */ ++ ++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ ++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ ++ ++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ ++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ ++ ++ ++/* AES.STATUS bit masks and bit positions */ ++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ ++#define AES_ERROR_bp 7 /* AES Error bit position. */ ++ ++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ ++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ ++ ++ ++/* AES.INTCTRL bit masks and bit positions */ ++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define AES_INTLVL_gp 0 /* Interrupt level group position. */ ++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_XOSCF_vect_num 1 ++#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* DMA interrupt vectors */ ++#define DMA_CH0_vect_num 6 ++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ ++#define DMA_CH1_vect_num 7 ++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ ++#define DMA_CH2_vect_num 8 ++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ ++#define DMA_CH3_vect_num 9 ++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* USARTC1 interrupt vectors */ ++#define USARTC1_RXC_vect_num 28 ++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ ++#define USARTC1_DRE_vect_num 29 ++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ ++#define USARTC1_TXC_vect_num 30 ++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ ++ ++/* AES interrupt vectors */ ++#define AES_INT_vect_num 31 ++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* ACB interrupt vectors */ ++#define ACB_AC0_vect_num 36 ++#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ ++#define ACB_AC1_vect_num 37 ++#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ ++#define ACB_ACW_vect_num 38 ++#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ ++ ++/* ADCB interrupt vectors */ ++#define ADCB_CH0_vect_num 39 ++#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ ++#define ADCB_CH1_vect_num 40 ++#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ ++#define ADCB_CH2_vect_num 41 ++#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ ++#define ADCB_CH3_vect_num 42 ++#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* TCE1 interrupt vectors */ ++#define TCE1_OVF_vect_num 53 ++#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ ++#define TCE1_ERR_vect_num 54 ++#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ ++#define TCE1_CCA_vect_num 55 ++#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ ++#define TCE1_CCB_vect_num 56 ++#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ ++ ++/* SPIE interrupt vectors */ ++#define SPIE_INT_vect_num 57 ++#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* USARTE1 interrupt vectors */ ++#define USARTE1_RXC_vect_num 61 ++#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ ++#define USARTE1_DRE_vect_num 62 ++#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ ++#define USARTE1_TXC_vect_num 63 ++#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++#define ADCA_CH1_vect_num 72 ++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ ++#define ADCA_CH2_vect_num 73 ++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ ++#define ADCA_CH3_vect_num 74 ++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ ++ ++/* TWID interrupt vectors */ ++#define TWID_TWIS_vect_num 75 ++#define TWID_TWIS_vect _VECTOR(75) /* TWI Slave Interrupt */ ++#define TWID_TWIM_vect_num 76 ++#define TWID_TWIM_vect _VECTOR(76) /* TWI Master Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD1 interrupt vectors */ ++#define TCD1_OVF_vect_num 83 ++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ ++#define TCD1_ERR_vect_num 84 ++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ ++#define TCD1_CCA_vect_num 85 ++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ ++#define TCD1_CCB_vect_num 86 ++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* USARTD1 interrupt vectors */ ++#define USARTD1_RXC_vect_num 91 ++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ ++#define USARTD1_DRE_vect_num 92 ++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ ++#define USARTD1_TXC_vect_num 93 ++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ ++ ++/* PORTQ interrupt vectors */ ++#define PORTQ_INT0_vect_num 94 ++#define PORTQ_INT0_vect _VECTOR(94) /* External Interrupt 0 */ ++#define PORTQ_INT1_vect_num 95 ++#define PORTQ_INT1_vect _VECTOR(95) /* External Interrupt 1 */ ++ ++/* PORTH interrupt vectors */ ++#define PORTH_INT0_vect_num 96 ++#define PORTH_INT0_vect _VECTOR(96) /* External Interrupt 0 */ ++#define PORTH_INT1_vect_num 97 ++#define PORTH_INT1_vect _VECTOR(97) /* External Interrupt 1 */ ++ ++/* PORTJ interrupt vectors */ ++#define PORTJ_INT0_vect_num 98 ++#define PORTJ_INT0_vect _VECTOR(98) /* External Interrupt 0 */ ++#define PORTJ_INT1_vect_num 99 ++#define PORTJ_INT1_vect _VECTOR(99) /* External Interrupt 1 */ ++ ++/* PORTK interrupt vectors */ ++#define PORTK_INT0_vect_num 100 ++#define PORTK_INT0_vect _VECTOR(100) /* External Interrupt 0 */ ++#define PORTK_INT1_vect_num 101 ++#define PORTK_INT1_vect _VECTOR(101) /* External Interrupt 1 */ ++ ++/* PORTF interrupt vectors */ ++#define PORTF_INT0_vect_num 104 ++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ ++#define PORTF_INT1_vect_num 105 ++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ ++ ++/* TWIF interrupt vectors */ ++#define TWIF_TWIS_vect_num 106 ++#define TWIF_TWIS_vect _VECTOR(106) /* TWI Slave Interrupt */ ++#define TWIF_TWIM_vect_num 107 ++#define TWIF_TWIM_vect _VECTOR(107) /* TWI Master Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_OVF_vect_num 108 ++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ ++#define TCF0_ERR_vect_num 109 ++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ ++#define TCF0_CCA_vect_num 110 ++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ ++#define TCF0_CCB_vect_num 111 ++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ ++#define TCF0_CCC_vect_num 112 ++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ ++#define TCF0_CCD_vect_num 113 ++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ ++ ++/* TCF1 interrupt vectors */ ++#define TCF1_OVF_vect_num 114 ++#define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */ ++#define TCF1_ERR_vect_num 115 ++#define TCF1_ERR_vect _VECTOR(115) /* Error Interrupt */ ++#define TCF1_CCA_vect_num 116 ++#define TCF1_CCA_vect _VECTOR(116) /* Compare or Capture A Interrupt */ ++#define TCF1_CCB_vect_num 117 ++#define TCF1_CCB_vect _VECTOR(117) /* Compare or Capture B Interrupt */ ++ ++/* SPIF interrupt vectors */ ++#define SPIF_INT_vect_num 118 ++#define SPIF_INT_vect _VECTOR(118) /* SPI Interrupt */ ++ ++/* USARTF0 interrupt vectors */ ++#define USARTF0_RXC_vect_num 119 ++#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ ++#define USARTF0_DRE_vect_num 120 ++#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ ++#define USARTF0_TXC_vect_num 121 ++#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ ++ ++/* USARTF1 interrupt vectors */ ++#define USARTF1_RXC_vect_num 122 ++#define USARTF1_RXC_vect _VECTOR(122) /* Reception Complete Interrupt */ ++#define USARTF1_DRE_vect_num 123 ++#define USARTF1_DRE_vect _VECTOR(123) /* Data Register Empty Interrupt */ ++#define USARTF1_TXC_vect_num 124 ++#define USARTF1_TXC_vect _VECTOR(124) /* Transmission Complete Interrupt */ ++ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (125 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (69632) ++#define PROGMEM_PAGE_SIZE (256) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (65536) ++#define APP_SECTION_PAGE_SIZE (256) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x0F000) ++#define APPTABLE_SECTION_SIZE (4096) ++#define APPTABLE_SECTION_PAGE_SIZE (256) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x10000) ++#define BOOT_SECTION_SIZE (4096) ++#define BOOT_SECTION_PAGE_SIZE (256) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (16777216) ++#define DATAMEM_PAGE_SIZE (0) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (2048) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (4096) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EXTERNAL_SRAM_START (0x3000) ++#define EXTERNAL_SRAM_SIZE (16764928) ++#define EXTERNAL_SRAM_PAGE_SIZE (0) ++#define EXTERNAL_SRAM_END (EXTERNAL_SRAM_START + EXTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (2048) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define FUSE_START (0x0000) ++#define FUSE_SIZE (6) ++#define FUSE_PAGE_SIZE (0) ++#define FUSE_END (FUSE_START + FUSE_SIZE - 1) ++ ++#define LOCKBIT_START (0x0000) ++#define LOCKBIT_SIZE (1) ++#define LOCKBIT_PAGE_SIZE (0) ++#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (256) ++#define USER_SIGNATURES_PAGE_SIZE (0) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (0) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE PROGMEM_PAGE_SIZE ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define XRAMSTART EXTERNAL_SRAM_START ++#define XRAMSIZE EXTERNAL_SRAM_SIZE ++#define XRAMEND EXTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 */ ++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ ++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ ++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ ++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ ++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ ++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ ++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ ++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ ++#define FUSE0_DEFAULT (0xFF) ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_BODACT0 (unsigned char)~_BV(2) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(3) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE5_DEFAULT (0xFF) ++ ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x4E ++ ++ ++#endif /* _AVR_ATxmega64A1_H_ */ ++ diff --git a/include/avr/iox64a1u.h b/include/avr/iox64a1u.h -index 646e316..e53146b 100644 +index 646e316..0b4ecb6 100644 --- a/include/avr/iox64a1u.h +++ b/include/avr/iox64a1u.h -@@ -1,38 +1,36 @@ +@@ -1,7549 +1,8236 @@ -/* Copyright (c) 2010 Atmel Corporation - All rights reserved. -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ - +- - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - @@ -213128,226 +612241,550 @@ index 646e316..e53146b 100644 -/* avr/iox64a1u.h - definitions for ATxmega64A1U */ - -/* This file should only be included from , never directly. */ - - #ifndef _AVR_IO_H_ - # error "Include instead of this file." -@@ -42,12 +40,10 @@ - # define _AVR_IOXXX_H_ "iox64a1u.h" - #else - # error "Attempt to include more than one file." +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iox64a1u.h" +-#else +-# error "Attempt to include more than one file." -#endif - - -#ifndef _AVR_ATxmega64A1U_H_ -#define _AVR_ATxmega64A1U_H_ 1 -+#endif - -+#ifndef _AVR_ATXMEGA64A1U_H_INCLUDED -+#define _AVR_ATXMEGA64A1U_H_INCLUDED - - /* Ungrouped common registers */ - #define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -@@ -67,6 +63,24 @@ - #define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ - #define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ - -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -+#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -+#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -+#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -+#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -+#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -+#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -+#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -+#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -+#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -+#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -+#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ -+ - #define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ - #define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ - #define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -@@ -77,7 +91,6 @@ - #define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ - #define SREG _SFR_MEM8(0x003F) /* Status Register */ - - - /* C Language Only */ - #if !defined (__ASSEMBLER__) - -@@ -156,6 +169,12 @@ typedef struct OCD_struct - } OCD_t; - - -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ - /* CCP signatures */ - typedef enum CCP_enum - { -@@ -180,11 +199,6 @@ typedef struct CLK_struct - register8_t USBCTRL; /* USB Control Register */ - } CLK_t; - +- +-/* Ungrouped common registers */ +-#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +-#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +-#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +-#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +-#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +-#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +-#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +-#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +-#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +-#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +-#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +-#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +-#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +-#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +-#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +-#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +- +-#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +-#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +-#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +-#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +-#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +-#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +-#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +-#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +-#define SREG _SFR_MEM8(0x003F) /* Status Register */ +- +- +-/* C Language Only */ +-#if !defined (__ASSEMBLER__) +- +-#include +- +-typedef volatile uint8_t register8_t; +-typedef volatile uint16_t register16_t; +-typedef volatile uint32_t register32_t; +- +- +-#ifdef _WORDREGISTER +-#undef _WORDREGISTER +-#endif +-#define _WORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register16_t regname; \ +- struct \ +- { \ +- register8_t regname ## L; \ +- register8_t regname ## H; \ +- }; \ +- } +- +-#ifdef _DWORDREGISTER +-#undef _DWORDREGISTER +-#endif +-#define _DWORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register32_t regname; \ +- struct \ +- { \ +- register8_t regname ## 0; \ +- register8_t regname ## 1; \ +- register8_t regname ## 2; \ +- register8_t regname ## 3; \ +- }; \ +- } +- +- +-/* +-========================================================================== +-IO Module Structures +-========================================================================== +-*/ +- +- +-/* +--------------------------------------------------------------------------- +-VPORT - Virtual Ports +--------------------------------------------------------------------------- +-*/ +- +-/* Virtual Port */ +-typedef struct VPORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t OUT; /* I/O Port Output */ +- register8_t IN; /* I/O Port Input */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +-} VPORT_t; +- +- +-/* +--------------------------------------------------------------------------- +-XOCD - On-Chip Debug System +--------------------------------------------------------------------------- +-*/ +- +-/* On-Chip Debug System */ +-typedef struct OCD_struct +-{ +- register8_t OCDR0; /* OCD Register 0 */ +- register8_t OCDR1; /* OCD Register 1 */ +-} OCD_t; +- +- +-/* CCP signatures */ +-typedef enum CCP_enum +-{ +- CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ +- CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +-} CCP_t; +- +- -/* --------------------------------------------------------------------------- -CLK - Clock System --------------------------------------------------------------------------- -*/ - - /* Power Reduction */ - typedef struct PR_struct -@@ -258,6 +272,7 @@ typedef enum CLK_USBPSDIV_enum - typedef enum CLK_USBSRC_enum - { - CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ -+ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ - } CLK_USBSRC_t; - - -@@ -298,7 +313,7 @@ typedef struct OSC_struct - register8_t XOSCCTRL; /* External Oscillator Control Register */ - register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ - register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ +- +-/* Clock System */ +-typedef struct CLK_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t PSCTRL; /* Prescaler Control Register */ +- register8_t LOCK; /* Lock register */ +- register8_t RTCCTRL; /* RTC Control Register */ +- register8_t USBCTRL; /* USB Control Register */ +-} CLK_t; +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Power Reduction */ +-typedef struct PR_struct +-{ +- register8_t PRGEN; /* General Power Reduction */ +- register8_t PRPA; /* Power Reduction Port A */ +- register8_t PRPB; /* Power Reduction Port B */ +- register8_t PRPC; /* Power Reduction Port C */ +- register8_t PRPD; /* Power Reduction Port D */ +- register8_t PRPE; /* Power Reduction Port E */ +- register8_t PRPF; /* Power Reduction Port F */ +-} PR_t; +- +-/* System Clock Selection */ +-typedef enum CLK_SCLKSEL_enum +-{ +- CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ +- CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ +- CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ +- CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ +- CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +-} CLK_SCLKSEL_t; +- +-/* Prescaler A Division Factor */ +-typedef enum CLK_PSADIV_enum +-{ +- CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ +- CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ +- CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ +- CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ +- CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ +- CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ +- CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ +- CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ +- CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ +- CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +-} CLK_PSADIV_t; +- +-/* Prescaler B and C Division Factor */ +-typedef enum CLK_PSBCDIV_enum +-{ +- CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ +- CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ +- CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ +- CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +-} CLK_PSBCDIV_t; +- +-/* RTC Clock Source */ +-typedef enum CLK_RTCSRC_enum +-{ +- CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ +- CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ +- CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ +- CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ +- CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ +- CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ +-} CLK_RTCSRC_t; +- +-/* USB Prescaler Division Factor */ +-typedef enum CLK_USBPSDIV_enum +-{ +- CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ +- CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ +- CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ +- CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ +- CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ +- CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ +-} CLK_USBPSDIV_t; +- +-/* USB Clock Source */ +-typedef enum CLK_USBSRC_enum +-{ +- CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ +-} CLK_USBSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-SLEEP - Sleep Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Sleep Controller */ +-typedef struct SLEEP_struct +-{ +- register8_t CTRL; /* Control Register */ +-} SLEEP_t; +- +-/* Sleep Mode */ +-typedef enum SLEEP_SMODE_enum +-{ +- SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ +- SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +- SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ +- SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ +- SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +-} SLEEP_SMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-OSC - Oscillator +--------------------------------------------------------------------------- +-*/ +- +-/* Oscillator */ +-typedef struct OSC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t XOSCCTRL; /* External Oscillator Control Register */ +- register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ +- register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ - register8_t PLLCTRL; /* PLL Control REgister */ -+ register8_t PLLCTRL; /* PLL Control Register */ - register8_t DFLLCTRL; /* DFLL Control Register */ - } OSC_t; - -@@ -329,11 +344,19 @@ typedef enum OSC_PLLSRC_enum - OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ - } OSC_PLLSRC_t; - +- register8_t DFLLCTRL; /* DFLL Control Register */ +-} OSC_t; +- +-/* Oscillator Frequency Range */ +-typedef enum OSC_FRQRANGE_enum +-{ +- OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ +- OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ +- OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ +- OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +-} OSC_FRQRANGE_t; +- +-/* External Oscillator Selection and Startup Time */ +-typedef enum OSC_XOSCSEL_enum +-{ +- OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ +- OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ +- OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ +- OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ +- OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ +-} OSC_XOSCSEL_t; +- +-/* PLL Clock Source */ +-typedef enum OSC_PLLSRC_enum +-{ +- OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ +- OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ +- OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +-} OSC_PLLSRC_t; +- -/* 32 MHz Calibration Reference */ -+/* 2 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC2MCREF_enum -+{ -+ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC2MCREF_t; -+ -+/* 32 MHz DFLL Calibration Reference */ - typedef enum OSC_RC32MCREF_enum - { - OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ +-typedef enum OSC_RC32MCREF_enum +-{ +- OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ - OSC_RC32MCREF_XOSC32_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ - } OSC_RC32MCREF_t; - - -@@ -392,9 +415,9 @@ typedef enum WDT_PER_enum - WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +-} OSC_RC32MCREF_t; +- +- +-/* +--------------------------------------------------------------------------- +-DFLL - DFLL +--------------------------------------------------------------------------- +-*/ +- +-/* DFLL */ +-typedef struct DFLL_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t CALA; /* Calibration Register A */ +- register8_t CALB; /* Calibration Register B */ +- register8_t COMP0; /* Oscillator Compare Register 0 */ +- register8_t COMP1; /* Oscillator Compare Register 1 */ +- register8_t COMP2; /* Oscillator Compare Register 2 */ +- register8_t reserved_0x07; +-} DFLL_t; +- +- +-/* +--------------------------------------------------------------------------- +-RST - Reset +--------------------------------------------------------------------------- +-*/ +- +-/* Reset */ +-typedef struct RST_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t CTRL; /* Control Register */ +-} RST_t; +- +- +-/* +--------------------------------------------------------------------------- +-WDT - Watch-Dog Timer +--------------------------------------------------------------------------- +-*/ +- +-/* Watch-Dog Timer */ +-typedef struct WDT_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t WINCTRL; /* Windowed Mode Control */ +- register8_t STATUS; /* Status */ +-} WDT_t; +- +-/* Period setting */ +-typedef enum WDT_PER_enum +-{ +- WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ - WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ - WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -@@ -408,9 +431,9 @@ typedef enum WDT_WPER_enum - WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ - WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ - WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_PER_t; +- +-/* Closed window period */ +-typedef enum WDT_WPER_enum +-{ +- WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ - WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ - WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ - WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ - WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ - WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ - WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -@@ -454,6 +477,19 @@ typedef struct PMIC_struct - register8_t STATUS; /* Status Register */ - register8_t INTPRI; /* Interrupt Priority */ - register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; - } PMIC_t; - - -@@ -471,6 +507,8 @@ typedef struct PORTCFG_struct - register8_t VPCTRLA; /* Virtual Port Control Register A */ - register8_t VPCTRLB; /* Virtual Port Control Register B */ - register8_t CLKEVOUT; /* Clock and Event Out Register */ -+ register8_t EBIOUT; /* EBI Output register */ -+ register8_t EVOUTSEL; /* Event Output Select */ - } PORTCFG_t; - - /* Virtual Port Mapping */ -@@ -541,6 +579,44 @@ typedef enum PORTCFG_EVOUT_enum - PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ - } PORTCFG_EVOUT_t; - -+/* Clock and Event Output Port */ -+typedef enum PORTCFG_CLKEVPIN_enum -+{ -+ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ -+ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -+} PORTCFG_CLKEVPIN_t; -+ -+/* EBI Address Output Port */ -+typedef enum PORTCFG_EBIADROUT_enum -+{ -+ PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ -+ PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ -+ PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ -+ PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ -+} PORTCFG_EBIADROUT_t; -+ -+/* EBI Chip Select Output Port */ -+typedef enum PORTCFG_EBICSOUT_enum -+{ -+ PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ -+} PORTCFG_EBICSOUT_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -+ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ -+ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ -+ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ -+ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ - - /* - -------------------------------------------------------------------------- -@@ -577,16 +653,17 @@ CRC - Cyclic Redundancy Checker - /* Cyclic Redundancy Checker */ - typedef struct CRC_struct - { +- WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_WPER_t; +- +- +-/* +--------------------------------------------------------------------------- +-MCU - MCU Control +--------------------------------------------------------------------------- +-*/ +- +-/* MCU Control */ +-typedef struct MCU_struct +-{ +- register8_t DEVID0; /* Device ID byte 0 */ +- register8_t DEVID1; /* Device ID byte 1 */ +- register8_t DEVID2; /* Device ID byte 2 */ +- register8_t REVID; /* Revision ID */ +- register8_t JTAGUID; /* JTAG User ID */ +- register8_t reserved_0x05; +- register8_t MCUCR; /* MCU Control */ +- register8_t ANAINIT; /* Analog Startup Delay */ +- register8_t EVSYSLOCK; /* Event System Lock */ +- register8_t AWEXLOCK; /* AWEX Lock */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +-} MCU_t; +- +- +-/* +--------------------------------------------------------------------------- +-PMIC - Programmable Multi-level Interrupt Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Programmable Multi-level Interrupt Controller */ +-typedef struct PMIC_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t INTPRI; /* Interrupt Priority */ +- register8_t CTRL; /* Control Register */ +-} PMIC_t; +- +- +-/* +--------------------------------------------------------------------------- +-PORTCFG - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O port Configuration */ +-typedef struct PORTCFG_struct +-{ +- register8_t MPCMASK; /* Multi-pin Configuration Mask */ +- register8_t reserved_0x01; +- register8_t VPCTRLA; /* Virtual Port Control Register A */ +- register8_t VPCTRLB; /* Virtual Port Control Register B */ +- register8_t CLKEVOUT; /* Clock and Event Out Register */ +-} PORTCFG_t; +- +-/* Virtual Port Mapping */ +-typedef enum PORTCFG_VP02MAP_enum +-{ +- PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP02MAP_t; +- +-/* Virtual Port Mapping */ +-typedef enum PORTCFG_VP13MAP_enum +-{ +- PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP13MAP_t; +- +-/* System Clock Output Port */ +-typedef enum PORTCFG_CLKOUT_enum +-{ +- PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ +- PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ +- PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ +- PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ +-} PORTCFG_CLKOUT_t; +- +-/* Peripheral Clock Output Select */ +-typedef enum PORTCFG_CLKOUTSEL_enum +-{ +- PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ +- PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ +- PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ +-} PORTCFG_CLKOUTSEL_t; +- +-/* Event Output Port */ +-typedef enum PORTCFG_EVOUT_enum +-{ +- PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ +- PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ +- PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ +- PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +-} PORTCFG_EVOUT_t; +- +- +-/* +--------------------------------------------------------------------------- +-AES - AES Module +--------------------------------------------------------------------------- +-*/ +- +-/* AES Module */ +-typedef struct AES_struct +-{ +- register8_t CTRL; /* AES Control Register */ +- register8_t STATUS; /* AES Status Register */ +- register8_t STATE; /* AES State Register */ +- register8_t KEY; /* AES Key Register */ +- register8_t INTCTRL; /* AES Interrupt Control Register */ +-} AES_t; +- +-/* Interrupt level */ +-typedef enum AES_INTLVL_enum +-{ +- AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} AES_INTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-CRC - Cyclic Redundancy Checker +--------------------------------------------------------------------------- +-*/ +- +-/* Cyclic Redundancy Checker */ +-typedef struct CRC_struct +-{ - register8_t CTRL; /* CRC Control Register */ - register8_t STATUS; /* CRC Status Register */ - register8_t DATAIN; /* CRC Data Input */ @@ -213355,225 +612792,838 @@ index 646e316..e53146b 100644 - register8_t CHECKSUM1; /* CRC Checksum byte 1 */ - register8_t CHECKSUM2; /* CRC Checksum byte 2 */ - register8_t CHECKSUM3; /* CRC Checksum byte 3 */ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ - } CRC_t; - +-} CRC_t; +- -/* CRC Reset */ -+/* Reset */ - typedef enum CRC_RESET_enum - { - CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -@@ -594,10 +671,10 @@ typedef enum CRC_RESET_enum - CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ - } CRC_RESET_t; - +-typedef enum CRC_RESET_enum +-{ +- CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ +- CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ +- CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ +-} CRC_RESET_t; +- -/* CRC Input Source */ -+/* Input Source */ - typedef enum CRC_SOURCE_enum - { +-typedef enum CRC_SOURCE_enum +-{ - CRC_SOURCE_DISABLE_gc = (0x00<<0), /* CRC Disabled */ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ - CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ - CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ - CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ -@@ -633,11 +710,6 @@ typedef struct DMA_CH_struct - register8_t reserved_0x0F; - } DMA_CH_t; - +- CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ +- CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ +- CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ +- CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ +- CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ +- CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ +-} CRC_SOURCE_t; +- +- -/* --------------------------------------------------------------------------- -DMA - DMA Controller --------------------------------------------------------------------------- -*/ - - /* DMA Controller */ - typedef struct DMA_struct -@@ -1037,8 +1109,8 @@ typedef struct NVM_struct - typedef enum NVM_CMD_enum - { - NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ - NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ +- +-/* DMA Channel */ +-typedef struct DMA_CH_struct +-{ +- register8_t CTRLA; /* Channel Control */ +- register8_t CTRLB; /* Channel Control */ +- register8_t ADDRCTRL; /* Address Control */ +- register8_t TRIGSRC; /* Channel Trigger Source */ +- _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ +- register8_t REPCNT; /* Channel Repeat Count */ +- register8_t reserved_0x07; +- register8_t SRCADDR0; /* Channel Source Address 0 */ +- register8_t SRCADDR1; /* Channel Source Address 1 */ +- register8_t SRCADDR2; /* Channel Source Address 2 */ +- register8_t reserved_0x0B; +- register8_t DESTADDR0; /* Channel Destination Address 0 */ +- register8_t DESTADDR1; /* Channel Destination Address 1 */ +- register8_t DESTADDR2; /* Channel Destination Address 2 */ +- register8_t reserved_0x0F; +-} DMA_CH_t; +- +-/* +--------------------------------------------------------------------------- +-DMA - DMA Controller +--------------------------------------------------------------------------- +-*/ +- +-/* DMA Controller */ +-typedef struct DMA_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t reserved_0x01; +- register8_t reserved_0x02; +- register8_t INTFLAGS; /* Transfer Interrupt Status */ +- register8_t STATUS; /* Status */ +- register8_t reserved_0x05; +- _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- DMA_CH_t CH0; /* DMA Channel 0 */ +- DMA_CH_t CH1; /* DMA Channel 1 */ +- DMA_CH_t CH2; /* DMA Channel 2 */ +- DMA_CH_t CH3; /* DMA Channel 3 */ +-} DMA_t; +- +-/* Burst mode */ +-typedef enum DMA_CH_BURSTLEN_enum +-{ +- DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ +- DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ +- DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ +- DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +-} DMA_CH_BURSTLEN_t; +- +-/* Source address reload mode */ +-typedef enum DMA_CH_SRCRELOAD_enum +-{ +- DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ +- DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ +- DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ +- DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +-} DMA_CH_SRCRELOAD_t; +- +-/* Source addressing mode */ +-typedef enum DMA_CH_SRCDIR_enum +-{ +- DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ +- DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ +- DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +-} DMA_CH_SRCDIR_t; +- +-/* Destination adress reload mode */ +-typedef enum DMA_CH_DESTRELOAD_enum +-{ +- DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ +- DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ +- DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ +- DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +-} DMA_CH_DESTRELOAD_t; +- +-/* Destination adressing mode */ +-typedef enum DMA_CH_DESTDIR_enum +-{ +- DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ +- DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ +- DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +-} DMA_CH_DESTDIR_t; +- +-/* Transfer trigger source */ +-typedef enum DMA_CH_TRIGSRC_enum +-{ +- DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ +- DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ +- DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ +- DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ +- DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ +- DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ +- DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ +- DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ +- DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ +- DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ +- DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ +- DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ +- DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ +- DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ +- DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ +- DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ +- DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ +- DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ +- DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ +- DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ +- DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ +- DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ +- DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ +- DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ +- DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ +- DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ +- DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ +- DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ +- DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ +- DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ +- DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ +- DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ +- DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ +- DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ +- DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ +- DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ +- DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ +- DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ +- DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +-} DMA_CH_TRIGSRC_t; +- +-/* Double buffering mode */ +-typedef enum DMA_DBUFMODE_enum +-{ +- DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ +- DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ +- DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ +- DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +-} DMA_DBUFMODE_t; +- +-/* Priority mode */ +-typedef enum DMA_PRIMODE_enum +-{ +- DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ +- DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ +- DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ +- DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +-} DMA_PRIMODE_t; +- +-/* Interrupt level */ +-typedef enum DMA_CH_ERRINTLVL_enum +-{ +- DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ +- DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ +- DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +-} DMA_CH_ERRINTLVL_t; +- +-/* Interrupt level */ +-typedef enum DMA_CH_TRNINTLVL_enum +-{ +- DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ +- DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ +- DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +-} DMA_CH_TRNINTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-EVSYS - Event System +--------------------------------------------------------------------------- +-*/ +- +-/* Event System */ +-typedef struct EVSYS_struct +-{ +- register8_t CH0MUX; /* Event Channel 0 Multiplexer */ +- register8_t CH1MUX; /* Event Channel 1 Multiplexer */ +- register8_t CH2MUX; /* Event Channel 2 Multiplexer */ +- register8_t CH3MUX; /* Event Channel 3 Multiplexer */ +- register8_t CH4MUX; /* Event Channel 4 Multiplexer */ +- register8_t CH5MUX; /* Event Channel 5 Multiplexer */ +- register8_t CH6MUX; /* Event Channel 6 Multiplexer */ +- register8_t CH7MUX; /* Event Channel 7 Multiplexer */ +- register8_t CH0CTRL; /* Channel 0 Control Register */ +- register8_t CH1CTRL; /* Channel 1 Control Register */ +- register8_t CH2CTRL; /* Channel 2 Control Register */ +- register8_t CH3CTRL; /* Channel 3 Control Register */ +- register8_t CH4CTRL; /* Channel 4 Control Register */ +- register8_t CH5CTRL; /* Channel 5 Control Register */ +- register8_t CH6CTRL; /* Channel 6 Control Register */ +- register8_t CH7CTRL; /* Channel 7 Control Register */ +- register8_t STROBE; /* Event Strobe */ +- register8_t DATA; /* Event Data */ +-} EVSYS_t; +- +-/* Quadrature Decoder Index Recognition Mode */ +-typedef enum EVSYS_QDIRM_enum +-{ +- EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ +- EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ +- EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ +- EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +-} EVSYS_QDIRM_t; +- +-/* Digital filter coefficient */ +-typedef enum EVSYS_DIGFILT_enum +-{ +- EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ +- EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ +- EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ +- EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ +- EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ +- EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ +- EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ +- EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +-} EVSYS_DIGFILT_t; +- +-/* Event Channel multiplexer input selection */ +-typedef enum EVSYS_CHMUX_enum +-{ +- EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ +- EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ +- EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ +- EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ +- EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ +- EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ +- EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ +- EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ +- EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ +- EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ +- EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ +- EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ +- EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ +- EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ +- EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ +- EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ +- EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ +- EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ +- EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ +- EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ +- EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ +- EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ +- EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ +- EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ +- EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ +- EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ +- EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ +- EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ +- EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ +- EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ +- EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ +- EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ +- EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ +- EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ +- EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ +- EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ +- EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ +- EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ +- EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ +- EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ +- EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ +- EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ +- EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ +- EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ +- EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ +- EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ +- EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ +- EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ +- EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ +- EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ +- EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ +- EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ +- EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ +- EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ +- EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ +- EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ +- EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ +- EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ +- EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ +- EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ +- EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ +- EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ +- EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ +- EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ +- EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ +- EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ +- EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ +- EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ +- EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ +- EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ +- EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ +- EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ +- EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ +- EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ +- EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ +- EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ +- EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ +- EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ +- EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ +- EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ +- EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ +- EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ +- EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ +- EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ +- EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ +- EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ +- EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ +- EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ +- EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ +- EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ +- EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ +- EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ +- EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ +- EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ +- EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ +- EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ +- EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ +- EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ +- EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ +- EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ +- EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ +- EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ +- EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ +- EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ +- EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ +- EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ +- EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ +- EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ +- EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ +- EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ +- EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ +- EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +- EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ +- EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ +- EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ +- EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +-} EVSYS_CHMUX_t; +- +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Non-volatile Memory Controller */ +-typedef struct NVM_struct +-{ +- register8_t ADDR0; /* Address Register 0 */ +- register8_t ADDR1; /* Address Register 1 */ +- register8_t ADDR2; /* Address Register 2 */ +- register8_t reserved_0x03; +- register8_t DATA0; /* Data Register 0 */ +- register8_t DATA1; /* Data Register 1 */ +- register8_t DATA2; /* Data Register 2 */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t CMD; /* Command */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t INTCTRL; /* Interrupt Control */ +- register8_t reserved_0x0E; +- register8_t STATUS; /* Status */ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_t; +- +-/* NVM Command */ +-typedef enum NVM_CMD_enum +-{ +- NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ +- NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ - NVM_CMD_READ_USER_SIG_ROW_gc = (0x03<<0), /* Read user signature row */ - NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ - NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ - NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -@@ -1062,13 +1134,14 @@ typedef enum NVM_CMD_enum - NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ - NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ - NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ +- NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ +- NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ +- NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ +- NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ +- NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ +- NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ +- NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ +- NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ +- NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ +- NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ +- NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ +- NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ +- NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ +- NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ +- NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ +- NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ +- NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ +- NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ +- NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ +- NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ +- NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ +- NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ +- NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ - NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ - NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ - NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ - NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ - NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ - NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ +- NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ +- NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ +- NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ +- NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ - NVM_CMD_FLASH_RANGE_CRC_gc = (0x78<<0), /* Generate Flash Range CRC */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ - } NVM_CMD_t; - - /* SPM ready interrupt level */ -@@ -1092,36 +1165,36 @@ typedef enum NVM_EELVL_enum - /* Boot lock bits - boot setcion */ - typedef enum NVM_BLBB_enum - { +-} NVM_CMD_t; +- +-/* SPM ready interrupt level */ +-typedef enum NVM_SPMLVL_enum +-{ +- NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ +- NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ +- NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +-} NVM_SPMLVL_t; +- +-/* EEPROM ready interrupt level */ +-typedef enum NVM_EELVL_enum +-{ +- NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ +- NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ +- NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +-} NVM_EELVL_t; +- +-/* Boot lock bits - boot setcion */ +-typedef enum NVM_BLBB_enum +-{ - NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ - NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ - NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ - NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ - } NVM_BLBB_t; - - /* Boot lock bits - application section */ - typedef enum NVM_BLBA_enum - { +- NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +-} NVM_BLBB_t; +- +-/* Boot lock bits - application section */ +-typedef enum NVM_BLBA_enum +-{ - NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ - NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ - NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ - NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ - } NVM_BLBA_t; - - /* Boot lock bits - application table section */ - typedef enum NVM_BLBAT_enum - { +- NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +-} NVM_BLBA_t; +- +-/* Boot lock bits - application table section */ +-typedef enum NVM_BLBAT_enum +-{ - NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ - NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ - NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ - NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ - } NVM_BLBAT_t; - - /* Lock bits */ - typedef enum NVM_LB_enum - { +- NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +-} NVM_BLBAT_t; +- +-/* Lock bits */ +-typedef enum NVM_LB_enum +-{ - NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ - NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ - NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ - } NVM_LB_t; - - -@@ -1136,17 +1209,13 @@ typedef struct ADC_CH_struct - { - register8_t CTRL; /* Control Register */ - register8_t MUXCTRL; /* MUX Control */ -- register8_t INTCTRL; /* Channel Interrupt Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ - register8_t INTFLAGS; /* Interrupt Flags */ - _WORDREGISTER(RES); /* Channel Result */ -- register8_t reserved_0x7; -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t reserved_0x07; - } ADC_CH_t; - +- NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +-} NVM_LB_t; +- +- -/* --------------------------------------------------------------------------- -ADC - Analog/Digital Converter --------------------------------------------------------------------------- -*/ - - /* Analog-to-Digital Converter */ - typedef struct ADC_struct -@@ -1158,7 +1227,7 @@ typedef struct ADC_struct - register8_t PRESCALER; /* Clock Prescaler */ - register8_t reserved_0x05; - register8_t INTFLAGS; /* Interrupt Flags */ +- +-/* ADC Channel */ +-typedef struct ADC_CH_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t MUXCTRL; /* MUX Control */ +- register8_t INTCTRL; /* Channel Interrupt Control */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- _WORDREGISTER(RES); /* Channel Result */ +- register8_t reserved_0x7; +-} ADC_CH_t; +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Analog-to-Digital Converter */ +-typedef struct ADC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t REFCTRL; /* Reference Control */ +- register8_t EVCTRL; /* Event Control */ +- register8_t PRESCALER; /* Clock Prescaler */ +- register8_t reserved_0x05; +- register8_t INTFLAGS; /* Interrupt Flags */ - register8_t TEMP; /* Temporary register */ -+ register8_t TEMP; /* Temporary Register */ - register8_t reserved_0x08; - register8_t reserved_0x09; - register8_t reserved_0x0A; -@@ -1224,6 +1293,10 @@ typedef enum ADC_CH_MUXNEG_enum - ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ - ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ - ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+ ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 3) */ -+ ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Groud (Input Mode = 3) */ -+ ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Groud (Input Mode = 4) */ -+ ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 4) */ - } ADC_CH_MUXNEG_t; - - /* Input mode */ -@@ -1245,7 +1318,7 @@ typedef enum ADC_CH_GAIN_enum - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- _WORDREGISTER(CAL); /* Calibration Value */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- _WORDREGISTER(CH0RES); /* Channel 0 Result */ +- _WORDREGISTER(CH1RES); /* Channel 1 Result */ +- _WORDREGISTER(CH2RES); /* Channel 2 Result */ +- _WORDREGISTER(CH3RES); /* Channel 3 Result */ +- _WORDREGISTER(CMP); /* Compare Value */ +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- ADC_CH_t CH0; /* ADC Channel 0 */ +- ADC_CH_t CH1; /* ADC Channel 1 */ +- ADC_CH_t CH2; /* ADC Channel 2 */ +- ADC_CH_t CH3; /* ADC Channel 3 */ +-} ADC_t; +- +-/* Positive input multiplexer selection */ +-typedef enum ADC_CH_MUXPOS_enum +-{ +- ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ +- ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ +- ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ +- ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ +- ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ +- ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ +- ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ +- ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +- ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ +- ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ +- ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ +- ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ +- ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ +- ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ +- ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ +- ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ +-} ADC_CH_MUXPOS_t; +- +-/* Internal input multiplexer selections */ +-typedef enum ADC_CH_MUXINT_enum +-{ +- ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ +- ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ +- ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +- ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +-} ADC_CH_MUXINT_t; +- +-/* Negative input multiplexer selection */ +-typedef enum ADC_CH_MUXNEG_enum +-{ +- ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ +- ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ +- ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ +- ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ +- ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ +- ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ +- ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ +- ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ +-} ADC_CH_MUXNEG_t; +- +-/* Input mode */ +-typedef enum ADC_CH_INPUTMODE_enum +-{ +- ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ +- ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ +- ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ +- ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +-} ADC_CH_INPUTMODE_t; +- +-/* Gain factor */ +-typedef enum ADC_CH_GAIN_enum +-{ +- ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ +- ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ +- ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ +- ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ +- ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ +- ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ +- ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ - ADC_CH_GAIN_128X_gc = (0x07<<2), /* 128x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ - } ADC_CH_GAIN_t; - - /* Conversion result resolution */ -@@ -1257,22 +1330,22 @@ typedef enum ADC_RESOLUTION_enum - } ADC_RESOLUTION_t; - - /* Current Limitation Mode */ +-} ADC_CH_GAIN_t; +- +-/* Conversion result resolution */ +-typedef enum ADC_RESOLUTION_enum +-{ +- ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ +- ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ +- ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +-} ADC_RESOLUTION_t; +- +-/* Current Limitation Mode */ -typedef enum ADC_CURRENT_enum -+typedef enum ADC_CURRLIMIT_enum - { +-{ - ADC_CURRENT_NO_gc = (0x00<<5), /* No Current Reduction */ - ADC_CURRENT_SMALL_gc = (0x01<<5), /* 10% current reduction */ - ADC_CURRENT_MEDIUM_gc = (0x02<<5), /* 20% current reduction */ - ADC_CURRENT_LARGE_gc = (0x03<<5), /* 30% current reduction */ -} ADC_CURRENT_t; -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ -+} ADC_CURRLIMIT_t; - - /* Voltage reference selection */ - typedef enum ADC_REFSEL_enum - { - ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ +- +-/* Voltage reference selection */ +-typedef enum ADC_REFSEL_enum +-{ +- ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ - ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ - ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ - ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +- ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ +- ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ - ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ - } ADC_REFSEL_t; - - /* Channel sweep selection */ -@@ -1306,7 +1379,7 @@ typedef enum ADC_EVACT_enum - ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ - ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ - ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ +-} ADC_REFSEL_t; +- +-/* Channel sweep selection */ +-typedef enum ADC_SWEEP_enum +-{ +- ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ +- ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ +- ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ +- ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +-} ADC_SWEEP_t; +- +-/* Event channel input selection */ +-typedef enum ADC_EVSEL_enum +-{ +- ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ +- ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ +- ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ +- ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ +- ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ +- ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ +- ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ +- ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +-} ADC_EVSEL_t; +- +-/* Event action selection */ +-typedef enum ADC_EVACT_enum +-{ +- ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ +- ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ +- ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ +- ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ +- ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ +- ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ - ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ - } ADC_EVACT_t; - - /* Interupt mode */ -@@ -1362,7 +1435,7 @@ typedef struct DAC_struct - register8_t CTRLB; /* Control Register B */ - register8_t CTRLC; /* Control Register C */ - register8_t EVCTRL; /* Event Input Control */ +-} ADC_EVACT_t; +- +-/* Interupt mode */ +-typedef enum ADC_CH_INTMODE_enum +-{ +- ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ +- ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ +- ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +-} ADC_CH_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum ADC_CH_INTLVL_enum +-{ +- ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ +- ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ +- ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +-} ADC_CH_INTLVL_t; +- +-/* DMA request selection */ +-typedef enum ADC_DMASEL_enum +-{ +- ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ +- ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ +- ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ +- ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +-} ADC_DMASEL_t; +- +-/* Clock prescaler */ +-typedef enum ADC_PRESCALER_enum +-{ +- ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ +- ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ +- ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ +- ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ +- ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ +- ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ +- ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ +- ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +-} ADC_PRESCALER_t; +- +- +-/* +--------------------------------------------------------------------------- +-DAC - Digital/Analog Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Digital-to-Analog Converter */ +-typedef struct DAC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t EVCTRL; /* Event Input Control */ - register8_t TIMCTRL; /* Timing Control */ -+ register8_t reserved_0x04; - register8_t STATUS; /* Status */ - register8_t reserved_0x06; - register8_t reserved_0x07; -@@ -1416,38 +1489,6 @@ typedef enum DAC_EVSEL_enum - DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ - } DAC_EVSEL_t; - +- register8_t STATUS; /* Status */ +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t CH0GAINCAL; /* Gain Calibration */ +- register8_t CH0OFFSETCAL; /* Offset Calibration */ +- register8_t CH1GAINCAL; /* Gain Calibration */ +- register8_t CH1OFFSETCAL; /* Offset Calibration */ +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- _WORDREGISTER(CH0DATA); /* Channel 0 Data */ +- _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +-} DAC_t; +- +-/* Output channel selection */ +-typedef enum DAC_CHSEL_enum +-{ +- DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ +- DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ +- DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ +-} DAC_CHSEL_t; +- +-/* Reference voltage selection */ +-typedef enum DAC_REFSEL_enum +-{ +- DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ +- DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ +- DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ +- DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +-} DAC_REFSEL_t; +- +-/* Event channel selection */ +-typedef enum DAC_EVSEL_enum +-{ +- DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ +- DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ +- DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ +- DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ +- DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ +- DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ +- DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ +- DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +-} DAC_EVSEL_t; +- -/* Conversion interval */ -typedef enum DAC_CONINTVAL_enum -{ @@ -213606,34 +613656,202 @@ index 646e316..e53146b 100644 - DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ -} DAC_REFRESH_t; - - - /* - -------------------------------------------------------------------------- -@@ -1548,7 +1589,7 @@ typedef enum AC_WSTATE_enum - - /* - -------------------------------------------------------------------------- +- +-/* +--------------------------------------------------------------------------- +-AC - Analog Comparator +--------------------------------------------------------------------------- +-*/ +- +-/* Analog Comparator */ +-typedef struct AC_struct +-{ +- register8_t AC0CTRL; /* Analog Comparator 0 Control */ +- register8_t AC1CTRL; /* Analog Comparator 1 Control */ +- register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ +- register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t WINCTRL; /* Window Mode Control */ +- register8_t STATUS; /* Status */ +-} AC_t; +- +-/* Interrupt mode */ +-typedef enum AC_INTMODE_enum +-{ +- AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ +- AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ +- AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +-} AC_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum AC_INTLVL_enum +-{ +- AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ +- AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ +- AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ +- AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +-} AC_INTLVL_t; +- +-/* Hysteresis mode selection */ +-typedef enum AC_HYSMODE_enum +-{ +- AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ +- AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ +- AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +-} AC_HYSMODE_t; +- +-/* Positive input multiplexer selection */ +-typedef enum AC_MUXPOS_enum +-{ +- AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ +- AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ +- AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ +- AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ +- AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ +- AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ +- AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +- AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +-} AC_MUXPOS_t; +- +-/* Negative input multiplexer selection */ +-typedef enum AC_MUXNEG_enum +-{ +- AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ +- AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ +- AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ +- AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ +- AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ +- AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ +- AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ +- AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +-} AC_MUXNEG_t; +- +-/* Windows interrupt mode */ +-typedef enum AC_WINTMODE_enum +-{ +- AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ +- AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ +- AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ +- AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +-} AC_WINTMODE_t; +- +-/* Window interrupt level */ +-typedef enum AC_WINTLVL_enum +-{ +- AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ +- AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ +- AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +-} AC_WINTLVL_t; +- +-/* Window mode state */ +-typedef enum AC_WSTATE_enum +-{ +- AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ +- AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ +- AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +-} AC_WSTATE_t; +- +- +-/* +--------------------------------------------------------------------------- -RTC - Real-Time Clounter -+RTC - Real-Time Counter - -------------------------------------------------------------------------- - */ - -@@ -1614,11 +1655,6 @@ typedef struct EBI_CS_struct - _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ - } EBI_CS_t; - +--------------------------------------------------------------------------- +-*/ +- +-/* Real-Time Counter */ +-typedef struct RTC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t TEMP; /* Temporary register */ +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- _WORDREGISTER(CNT); /* Count Register */ +- _WORDREGISTER(PER); /* Period Register */ +- _WORDREGISTER(COMP); /* Compare Register */ +-} RTC_t; +- +-/* Prescaler Factor */ +-typedef enum RTC_PRESCALER_enum +-{ +- RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ +- RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ +- RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ +- RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ +- RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ +- RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ +- RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ +- RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +-} RTC_PRESCALER_t; +- +-/* Compare Interrupt level */ +-typedef enum RTC_COMPINTLVL_enum +-{ +- RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} RTC_COMPINTLVL_t; +- +-/* Overflow Interrupt level */ +-typedef enum RTC_OVFINTLVL_enum +-{ +- RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} RTC_OVFINTLVL_t; +- +- -/* --------------------------------------------------------------------------- -EBI - External Bus Interface --------------------------------------------------------------------------- -*/ - - /* External Bus Interface */ - typedef struct EBI_struct -@@ -1644,28 +1680,28 @@ typedef struct EBI_struct - } EBI_t; - - /* Chip Select adress space */ +- +-/* EBI Chip Select Module */ +-typedef struct EBI_CS_struct +-{ +- register8_t CTRLA; /* Chip Select Control Register A */ +- register8_t CTRLB; /* Chip Select Control Register B */ +- _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +-} EBI_CS_t; +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* External Bus Interface */ +-typedef struct EBI_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t SDRAMCTRLA; /* SDRAM Control Register A */ +- register8_t reserved_0x02; +- register8_t reserved_0x03; +- _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ +- _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ +- register8_t SDRAMCTRLB; /* SDRAM Control Register B */ +- register8_t SDRAMCTRLC; /* SDRAM Control Register C */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- EBI_CS_t CS0; /* Chip Select 0 */ +- EBI_CS_t CS1; /* Chip Select 1 */ +- EBI_CS_t CS2; /* Chip Select 2 */ +- EBI_CS_t CS3; /* Chip Select 3 */ +-} EBI_t; +- +-/* Chip Select adress space */ -typedef enum EBI_CS_ASIZE_enum -{ - EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ @@ -213656,187 +613874,274 @@ index 646e316..e53146b 100644 -} EBI_CS_ASIZE_t; - -/* */ -+typedef enum EBI_CS_ASPACE_enum -+{ -+ EBI_CS_ASPACE_256B_gc = (0x00<<2), /* 256 bytes */ -+ EBI_CS_ASPACE_512B_gc = (0x01<<2), /* 512 bytes */ -+ EBI_CS_ASPACE_1KB_gc = (0x02<<2), /* 1K bytes */ -+ EBI_CS_ASPACE_2KB_gc = (0x03<<2), /* 2K bytes */ -+ EBI_CS_ASPACE_4KB_gc = (0x04<<2), /* 4K bytes */ -+ EBI_CS_ASPACE_8KB_gc = (0x05<<2), /* 8K bytes */ -+ EBI_CS_ASPACE_16KB_gc = (0x06<<2), /* 16K bytes */ -+ EBI_CS_ASPACE_32KB_gc = (0x07<<2), /* 32K bytes */ -+ EBI_CS_ASPACE_64KB_gc = (0x08<<2), /* 64K bytes */ -+ EBI_CS_ASPACE_128KB_gc = (0x09<<2), /* 128K bytes */ -+ EBI_CS_ASPACE_256KB_gc = (0x0A<<2), /* 256K bytes */ -+ EBI_CS_ASPACE_512KB_gc = (0x0B<<2), /* 512K bytes */ -+ EBI_CS_ASPACE_1MB_gc = (0x0C<<2), /* 1M bytes */ -+ EBI_CS_ASPACE_2MB_gc = (0x0D<<2), /* 2M bytes */ -+ EBI_CS_ASPACE_4MB_gc = (0x0E<<2), /* 4M bytes */ -+ EBI_CS_ASPACE_8MB_gc = (0x0F<<2), /* 8M bytes */ -+ EBI_CS_ASPACE_16M_gc = (0x10<<2), /* 16M bytes */ -+} EBI_CS_ASPACE_t; -+ -+/* SRAM Wait State Selection */ - typedef enum EBI_CS_SRWS_enum - { - EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ -@@ -1673,7 +1709,7 @@ typedef enum EBI_CS_SRWS_enum - EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ +-typedef enum EBI_CS_SRWS_enum +-{ +- EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ -+ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycles */ - EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ - } EBI_CS_SRWS_t; -@@ -1735,7 +1771,7 @@ typedef enum EBI_SDCOL_enum - EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ - } EBI_SDCOL_t; - +- EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_CS_SRWS_t; +- +-/* Chip Select address mode */ +-typedef enum EBI_CS_MODE_enum +-{ +- EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ +- EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ +- EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ +- EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +-} EBI_CS_MODE_t; +- +-/* Chip Select SDRAM mode */ +-typedef enum EBI_CS_SDMODE_enum +-{ +- EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ +- EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +-} EBI_CS_SDMODE_t; +- -/* */ -+/* SDRAM Load Mode to Active delay */ - typedef enum EBI_MRDLY_enum - { - EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ -@@ -1744,7 +1780,7 @@ typedef enum EBI_MRDLY_enum - EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ - } EBI_MRDLY_t; - +-typedef enum EBI_SDDATAW_enum +-{ +- EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ +- EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +-} EBI_SDDATAW_t; +- -/* */ -+/* SDRAM Row Cycle Delay */ - typedef enum EBI_ROWCYCDLY_enum - { - EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ -@@ -1752,12 +1788,12 @@ typedef enum EBI_ROWCYCDLY_enum - EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +-typedef enum EBI_LPCMODE_enum +-{ +- EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ +- EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +-} EBI_LPCMODE_t; +- +-/* */ +-typedef enum EBI_SRMODE_enum +-{ +- EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ +- EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ +- EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ +- EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +-} EBI_SRMODE_t; +- +-/* */ +-typedef enum EBI_IFMODE_enum +-{ +- EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ +- EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ +- EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ +- EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +-} EBI_IFMODE_t; +- +-/* */ +-typedef enum EBI_SDCOL_enum +-{ +- EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ +- EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ +- EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ +- EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +-} EBI_SDCOL_t; +- +-/* */ +-typedef enum EBI_MRDLY_enum +-{ +- EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_MRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCYCDLY_enum +-{ +- EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ -+ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycles */ - EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ - } EBI_ROWCYCDLY_t; - +- EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ROWCYCDLY_t; +- -/* */ -+/* SDRAM Row to Precharge Delay */ - typedef enum EBI_RPDLY_enum - { - EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ -@@ -1765,12 +1801,12 @@ typedef enum EBI_RPDLY_enum - EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +-typedef enum EBI_RPDLY_enum +-{ +- EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ -+ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycles */ - EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ - } EBI_RPDLY_t; - +- EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_RPDLY_t; +- -/* */ -+/* SDRAM Write Recovery Delay */ - typedef enum EBI_WRDLY_enum - { - EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ -@@ -1779,7 +1815,7 @@ typedef enum EBI_WRDLY_enum - EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ - } EBI_WRDLY_t; - +-typedef enum EBI_WRDLY_enum +-{ +- EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_WRDLY_t; +- -/* */ -+/* SDRAM Exit Self Refresh to Active Delay */ - typedef enum EBI_ESRDLY_enum - { - EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ -@@ -1787,12 +1823,12 @@ typedef enum EBI_ESRDLY_enum - EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ - EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ - EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +-typedef enum EBI_ESRDLY_enum +-{ +- EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ - EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ -+ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycles */ - EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ - EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ - } EBI_ESRDLY_t; - +- EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ESRDLY_t; +- -/* */ -+/* SDRAM Row to Column Delay */ - typedef enum EBI_ROWCOLDLY_enum - { - EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ -@@ -1800,7 +1836,7 @@ typedef enum EBI_ROWCOLDLY_enum - EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ - EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ - EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +-typedef enum EBI_ROWCOLDLY_enum +-{ +- EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ - EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ -+ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycles */ - EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ - EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ - } EBI_ROWCOLDLY_t; -@@ -1824,11 +1860,6 @@ typedef struct TWI_MASTER_struct - register8_t DATA; /* Data Register */ - } TWI_MASTER_t; - +- EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_ROWCOLDLY_t; +- +- -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - - /* */ - typedef struct TWI_SLAVE_struct -@@ -1841,11 +1872,6 @@ typedef struct TWI_SLAVE_struct - register8_t ADDRMASK; /* Address Mask Register */ - } TWI_SLAVE_t; - +- +-/* */ +-typedef struct TWI_MASTER_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t STATUS; /* Status Register */ +- register8_t BAUD; /* Baurd Rate Control Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +-} TWI_MASTER_t; +- -/* --------------------------------------------------------------------------- -TWI - Two-Wire Interface --------------------------------------------------------------------------- -*/ - - /* Two-Wire Interface */ - typedef struct TWI_struct -@@ -1908,10 +1934,19 @@ typedef enum TWI_SLAVE_CMD_enum - TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ - } TWI_SLAVE_CMD_t; - -+/* SDA hold time */ -+typedef enum SDA_HOLD_TIME_enum -+{ -+ SDA_HOLD_TIME_OFF_gc = (0x00<<1), /* SDA hold time off */ -+ SDA_HOLD_TIME_50NS_gc = (0x01<<1), /* Typical 50ns hold time */ -+ SDA_HOLD_TIME_300NS_gc = (0x02<<1), /* Typical 300ns hold time */ -+ SDA_HOLD_TIME_400NS_gc = (0x03<<1), /* Typical 400ns hold time */ -+} SDA_HOLD_TIME_t; -+ - - /* - -------------------------------------------------------------------------- +- +-/* */ +-typedef struct TWI_SLAVE_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t STATUS; /* Status Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +- register8_t ADDRMASK; /* Address Mask Register */ +-} TWI_SLAVE_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Two-Wire Interface */ +-typedef struct TWI_struct +-{ +- register8_t CTRL; /* TWI Common Control Register */ +- TWI_MASTER_t MASTER; /* TWI master module */ +- TWI_SLAVE_t SLAVE; /* TWI slave module */ +-} TWI_t; +- +-/* Master Interrupt Level */ +-typedef enum TWI_MASTER_INTLVL_enum +-{ +- TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_MASTER_INTLVL_t; +- +-/* Inactive Timeout */ +-typedef enum TWI_MASTER_TIMEOUT_enum +-{ +- TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ +- TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ +- TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ +- TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +-} TWI_MASTER_TIMEOUT_t; +- +-/* Master Command */ +-typedef enum TWI_MASTER_CMD_enum +-{ +- TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ +- TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ +- TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +-} TWI_MASTER_CMD_t; +- +-/* Master Bus State */ +-typedef enum TWI_MASTER_BUSSTATE_enum +-{ +- TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ +- TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ +- TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ +- TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +-} TWI_MASTER_BUSSTATE_t; +- +-/* Slave Interrupt Level */ +-typedef enum TWI_SLAVE_INTLVL_enum +-{ +- TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_SLAVE_INTLVL_t; +- +-/* Slave Command */ +-typedef enum TWI_SLAVE_CMD_enum +-{ +- TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ +- TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +-} TWI_SLAVE_CMD_t; +- +- +-/* +--------------------------------------------------------------------------- -USB - USB Module -+USB - USB - -------------------------------------------------------------------------- - */ - -@@ -1920,66 +1955,13 @@ typedef struct USB_EP_struct - { - register8_t STATUS; /* Endpoint Status */ - register8_t CTRL; /* Endpoint Control */ +--------------------------------------------------------------------------- +-*/ +- +-/* USB Endpoint */ +-typedef struct USB_EP_struct +-{ +- register8_t STATUS; /* Endpoint Status */ +- register8_t CTRL; /* Endpoint Control */ - register8_t CNTL; /* USB Endpoint Counter Low Byte */ - register8_t CNTH; /* USB Endpoint Counter High Byte */ - register8_t DATAPTRL; /* Data Pointer Low Byte */ - register8_t DATAPTRH; /* Data Pointer High Byte */ - register8_t AUXDATAL; /* Auxiliary Data Low Byte */ - register8_t AUXDATAH; /* Auxiliary Data High Byte */ -+ _WORDREGISTER(CNT); /* USB Endpoint Counter */ -+ _WORDREGISTER(DATAPTR); /* Data Pointer */ -+ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ - } USB_EP_t; - +-} USB_EP_t; +- -/* --------------------------------------------------------------------------- -USB - USB Module --------------------------------------------------------------------------- -*/ - +- -/* USB Endpoint table */ -typedef struct USB_EP_TABLE_struct -{ @@ -213883,91 +614188,81 @@ index 646e316..e53146b 100644 -*/ - -/* USB Module */ -+/* Universal Serial Bus */ - typedef struct USB_struct - { - register8_t CTRLA; /* Control Register A */ -@@ -2043,6 +2025,71 @@ typedef struct USB_struct - register8_t CAL1; /* Calibration Byte 1 */ - } USB_t; - -+ -+/* USB Endpoint Table */ -+typedef struct USB_EP_TABLE_struct -+{ -+ USB_EP_t EP0OUT; /* Endpoint 0 */ -+ USB_EP_t EP0IN; /* Endpoint 0 */ -+ USB_EP_t EP1OUT; /* Endpoint 1 */ -+ USB_EP_t EP1IN; /* Endpoint 1 */ -+ USB_EP_t EP2OUT; /* Endpoint 2 */ -+ USB_EP_t EP2IN; /* Endpoint 2 */ -+ USB_EP_t EP3OUT; /* Endpoint 3 */ -+ USB_EP_t EP3IN; /* Endpoint 3 */ -+ USB_EP_t EP4OUT; /* Endpoint 4 */ -+ USB_EP_t EP4IN; /* Endpoint 4 */ -+ USB_EP_t EP5OUT; /* Endpoint 5 */ -+ USB_EP_t EP5IN; /* Endpoint 5 */ -+ USB_EP_t EP6OUT; /* Endpoint 6 */ -+ USB_EP_t EP6IN; /* Endpoint 6 */ -+ USB_EP_t EP7OUT; /* Endpoint 7 */ -+ USB_EP_t EP7IN; /* Endpoint 7 */ -+ USB_EP_t EP8OUT; /* Endpoint 8 */ -+ USB_EP_t EP8IN; /* Endpoint 8 */ -+ USB_EP_t EP9OUT; /* Endpoint 9 */ -+ USB_EP_t EP9IN; /* Endpoint 9 */ -+ USB_EP_t EP10OUT; /* Endpoint 10 */ -+ USB_EP_t EP10IN; /* Endpoint 10 */ -+ USB_EP_t EP11OUT; /* Endpoint 11 */ -+ USB_EP_t EP11IN; /* Endpoint 11 */ -+ USB_EP_t EP12OUT; /* Endpoint 12 */ -+ USB_EP_t EP12IN; /* Endpoint 12 */ -+ USB_EP_t EP13OUT; /* Endpoint 13 */ -+ USB_EP_t EP13IN; /* Endpoint 13 */ -+ USB_EP_t EP14OUT; /* Endpoint 14 */ -+ USB_EP_t EP14IN; /* Endpoint 14 */ -+ USB_EP_t EP15OUT; /* Endpoint 15 */ -+ USB_EP_t EP15IN; /* Endpoint 15 */ -+ register8_t reserved_0x100; -+ register8_t reserved_0x101; -+ register8_t reserved_0x102; -+ register8_t reserved_0x103; -+ register8_t reserved_0x104; -+ register8_t reserved_0x105; -+ register8_t reserved_0x106; -+ register8_t reserved_0x107; -+ register8_t reserved_0x108; -+ register8_t reserved_0x109; -+ register8_t reserved_0x10A; -+ register8_t reserved_0x10B; -+ register8_t reserved_0x10C; -+ register8_t reserved_0x10D; -+ register8_t reserved_0x10E; -+ register8_t reserved_0x10F; -+ register8_t FRAMENUML; /* Frame Number Low Byte */ -+ register8_t FRAMENUMH; /* Frame Number High Byte */ -+} USB_EP_TABLE_t; -+ -+/* Interrupt level */ -+typedef enum USB_INTLVL_enum -+{ -+ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} USB_INTLVL_t; -+ - /* USB Endpoint Type */ - typedef enum USB_EP_TYPE_enum - { -@@ -2052,27 +2099,18 @@ typedef enum USB_EP_TYPE_enum - USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ - } USB_EP_TYPE_t; - +-typedef struct USB_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t STATUS; /* Status Register */ +- register8_t ADDR; /* Address Register */ +- register8_t FIFOWP; /* FIFO Write Pointer Register */ +- register8_t FIFORP; /* FIFO Read Pointer Register */ +- _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ +- register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ +- register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ +- register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- register8_t reserved_0x20; +- register8_t reserved_0x21; +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- register8_t reserved_0x26; +- register8_t reserved_0x27; +- register8_t reserved_0x28; +- register8_t reserved_0x29; +- register8_t reserved_0x2A; +- register8_t reserved_0x2B; +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t reserved_0x2E; +- register8_t reserved_0x2F; +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- register8_t reserved_0x36; +- register8_t reserved_0x37; +- register8_t reserved_0x38; +- register8_t reserved_0x39; +- register8_t CAL0; /* Calibration Byte 0 */ +- register8_t CAL1; /* Calibration Byte 1 */ +-} USB_t; +- +-/* USB Endpoint Type */ +-typedef enum USB_EP_TYPE_enum +-{ +- USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ +- USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ +- USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ +- USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ +-} USB_EP_TYPE_t; +- -/* USB Endpoint Buffer Size */ -typedef enum USB_EP_SIZE_enum -+/* USB Endpoint Buffersize */ -+typedef enum USB_EP_BUFSIZE_enum - { +-{ - USB_EP_SIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ - USB_EP_SIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ - USB_EP_SIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ @@ -213986,516 +614281,575 @@ index 646e316..e53146b 100644 - USB_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ - USB_INTLVL_HI_gc = (0x03<<0), /* High Level */ -} USB_INTLVL_t; -+ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ -+ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ -+ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ -+ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ -+ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ -+ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ -+ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ -+ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -+} USB_EP_BUFSIZE_t; - - - /* -@@ -2098,6 +2136,7 @@ typedef struct PORT_struct - register8_t INT1MASK; /* Port Interrupt 1 Mask */ - register8_t INTFLAGS; /* Interrupt Flag Register */ - register8_t reserved_0x0D; -+ register8_t REMAP; /* I/O Port Pin Remap Register */ - register8_t reserved_0x0F; - register8_t PIN0CTRL; /* Pin 0 Control Register */ - register8_t PIN1CTRL; /* Pin 1 Control Register */ -@@ -2215,11 +2254,6 @@ typedef struct TC0_struct - _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ - } TC0_t; - +- +- +-/* +--------------------------------------------------------------------------- +-PORT - I/O Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O Ports */ +-typedef struct PORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t DIRSET; /* I/O Port Data Direction Set */ +- register8_t DIRCLR; /* I/O Port Data Direction Clear */ +- register8_t DIRTGL; /* I/O Port Data Direction Toggle */ +- register8_t OUT; /* I/O Port Output */ +- register8_t OUTSET; /* I/O Port Output Set */ +- register8_t OUTCLR; /* I/O Port Output Clear */ +- register8_t OUTTGL; /* I/O Port Output Toggle */ +- register8_t IN; /* I/O port Input */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INT0MASK; /* Port Interrupt 0 Mask */ +- register8_t INT1MASK; /* Port Interrupt 1 Mask */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0F; +- register8_t PIN0CTRL; /* Pin 0 Control Register */ +- register8_t PIN1CTRL; /* Pin 1 Control Register */ +- register8_t PIN2CTRL; /* Pin 2 Control Register */ +- register8_t PIN3CTRL; /* Pin 3 Control Register */ +- register8_t PIN4CTRL; /* Pin 4 Control Register */ +- register8_t PIN5CTRL; /* Pin 5 Control Register */ +- register8_t PIN6CTRL; /* Pin 6 Control Register */ +- register8_t PIN7CTRL; /* Pin 7 Control Register */ +-} PORT_t; +- +-/* Port Interrupt 0 Level */ +-typedef enum PORT_INT0LVL_enum +-{ +- PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ +- PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ +- PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +-} PORT_INT0LVL_t; +- +-/* Port Interrupt 1 Level */ +-typedef enum PORT_INT1LVL_enum +-{ +- PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ +- PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ +- PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +-} PORT_INT1LVL_t; +- +-/* Output/Pull Configuration */ +-typedef enum PORT_OPC_enum +-{ +- PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ +- PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ +- PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ +- PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ +- PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ +- PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ +- PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ +- PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +-} PORT_OPC_t; +- +-/* Input/Sense Configuration */ +-typedef enum PORT_ISC_enum +-{ +- PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ +- PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ +- PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ +- PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ +- PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +-} PORT_ISC_t; +- +- -/* --------------------------------------------------------------------------- -TC - 16-bit Timer/Counter With PWM --------------------------------------------------------------------------- -*/ - - /* 16-bit Timer/Counter 1 */ - typedef struct TC1_struct -@@ -2305,12 +2339,24 @@ typedef enum TC_WGMODE_enum - { - TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ - TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ - TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ - TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -- TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ -+ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ - } TC_WGMODE_t; - -+/* Byte Mode */ -+typedef enum TC_BYTEM_enum -+{ -+ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ -+ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -+} TC_BYTEM_t; -+ - /* Event Action */ - typedef enum TC_EVACT_enum - { -@@ -2403,6 +2449,165 @@ typedef enum TC_CMD_enum - - /* - -------------------------------------------------------------------------- -+TC2 - 16-bit Timer/Counter type 2 -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter type 2 */ -+typedef struct TC2_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t reserved_0x03; -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t reserved_0x08; -+ register8_t CTRLF; /* Control Register F */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t LCNT; /* Low Byte Count */ -+ register8_t HCNT; /* High Byte Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t LPER; /* Low Byte Period */ -+ register8_t HPER; /* High Byte Period */ -+ register8_t LCMPA; /* Low Byte Compare A */ -+ register8_t HCMPA; /* High Byte Compare A */ -+ register8_t LCMPB; /* Low Byte Compare B */ -+ register8_t HCMPB; /* High Byte Compare B */ -+ register8_t LCMPC; /* Low Byte Compare C */ -+ register8_t HCMPC; /* High Byte Compare C */ -+ register8_t LCMPD; /* Low Byte Compare D */ -+ register8_t HCMPD; /* High Byte Compare D */ -+} TC2_t; -+ -+/* Clock Selection */ -+typedef enum TC2_CLKSEL_enum -+{ -+ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC2_CLKSEL_t; -+ -+/* Byte Mode */ -+typedef enum TC2_BYTEM_enum -+{ -+ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ -+ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -+} TC2_BYTEM_t; -+ -+/* High Byte Underflow Interrupt Level */ -+typedef enum TC2_HUNFINTLVL_enum -+{ -+ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_HUNFINTLVL_t; -+ -+/* Low Byte Underflow Interrupt Level */ -+typedef enum TC2_LUNFINTLVL_enum -+{ -+ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LUNFINTLVL_t; -+ -+/* Low Byte Compare D Interrupt Level */ -+typedef enum TC2_LCMPDINTLVL_enum -+{ -+ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC2_LCMPDINTLVL_t; -+ -+/* Low Byte Compare C Interrupt Level */ -+typedef enum TC2_LCMPCINTLVL_enum -+{ -+ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC2_LCMPCINTLVL_t; -+ -+/* Low Byte Compare B Interrupt Level */ -+typedef enum TC2_LCMPBINTLVL_enum -+{ -+ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_LCMPBINTLVL_t; -+ -+/* Low Byte Compare A Interrupt Level */ -+typedef enum TC2_LCMPAINTLVL_enum -+{ -+ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LCMPAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMD_enum -+{ -+ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC2_CMD_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMDEN_enum -+{ -+ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ -+ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ -+ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -+} TC2_CMDEN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- - AWEX - Timer/Counter Advanced Waveform Extension - -------------------------------------------------------------------------- - */ -@@ -2415,7 +2620,7 @@ typedef struct AWEX_struct - register8_t FDEMASK; /* Fault Detection Event Mask */ - register8_t FDCTRL; /* Fault Detection Control Register */ - register8_t STATUS; /* Status Register */ +- +-/* 16-bit Timer/Counter 0 */ +-typedef struct TC0_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ - register8_t reserved_0x05; -+ register8_t STATUSSET; /* Status Set Register */ - register8_t DTBOTH; /* Dead Time Both Sides */ - register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ - register8_t DTLS; /* Dead Time Low Side */ -@@ -2604,17 +2809,235 @@ typedef enum IRDA_EVSEL_enum - - /* - -------------------------------------------------------------------------- +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- _WORDREGISTER(CCC); /* Compare or Capture C */ +- _WORDREGISTER(CCD); /* Compare or Capture D */ +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +- _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ +- _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +-} TC0_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 1 */ +-typedef struct TC1_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t reserved_0x2E; +- register8_t reserved_0x2F; +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +-} TC1_t; +- +-/* Clock Selection */ +-typedef enum TC_CLKSEL_enum +-{ +- TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ +- TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ +- TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ +- TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ +- TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ +- TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ +- TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ +- TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ +- TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_CLKSEL_t; +- +-/* Waveform Generation Mode */ +-typedef enum TC_WGMODE_enum +-{ +- TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ +- TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ +- TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ +- TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ +- TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ +- TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +-} TC_WGMODE_t; +- +-/* Event Action */ +-typedef enum TC_EVACT_enum +-{ +- TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ +- TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ +- TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ +- TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ +- TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ +- TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ +- TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +-} TC_EVACT_t; +- +-/* Event Selection */ +-typedef enum TC_EVSEL_enum +-{ +- TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_EVSEL_t; +- +-/* Error Interrupt Level */ +-typedef enum TC_ERRINTLVL_enum +-{ +- TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_ERRINTLVL_t; +- +-/* Overflow Interrupt Level */ +-typedef enum TC_OVFINTLVL_enum +-{ +- TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_OVFINTLVL_t; +- +-/* Compare or Capture D Interrupt Level */ +-typedef enum TC_CCDINTLVL_enum +-{ +- TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TC_CCDINTLVL_t; +- +-/* Compare or Capture C Interrupt Level */ +-typedef enum TC_CCCINTLVL_enum +-{ +- TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} TC_CCCINTLVL_t; +- +-/* Compare or Capture B Interrupt Level */ +-typedef enum TC_CCBINTLVL_enum +-{ +- TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_CCBINTLVL_t; +- +-/* Compare or Capture A Interrupt Level */ +-typedef enum TC_CCAINTLVL_enum +-{ +- TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_CCAINTLVL_t; +- +-/* Timer/Counter Command */ +-typedef enum TC_CMD_enum +-{ +- TC_CMD_NONE_gc = (0x00<<2), /* No Command */ +- TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ +- TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ +- TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +-} TC_CMD_t; +- +- +-/* +--------------------------------------------------------------------------- +-AWEX - Timer/Counter Advanced Waveform Extension +--------------------------------------------------------------------------- +-*/ +- +-/* Advanced Waveform Extension */ +-typedef struct AWEX_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t FDEMASK; /* Fault Detection Event Mask */ +- register8_t FDCTRL; /* Fault Detection Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x05; +- register8_t DTBOTH; /* Dead Time Both Sides */ +- register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ +- register8_t DTLS; /* Dead Time Low Side */ +- register8_t DTHS; /* Dead Time High Side */ +- register8_t DTLSBUF; /* Dead Time Low Side Buffer */ +- register8_t DTHSBUF; /* Dead Time High Side Buffer */ +- register8_t OUTOVEN; /* Output Override Enable */ +-} AWEX_t; +- +-/* Fault Detect Action */ +-typedef enum AWEX_FDACT_enum +-{ +- AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ +- AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ +- AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +-} AWEX_FDACT_t; +- +- +-/* +--------------------------------------------------------------------------- +-HIRES - Timer/Counter High-Resolution Extension +--------------------------------------------------------------------------- +-*/ +- +-/* High-Resolution Extension */ +-typedef struct HIRES_struct +-{ +- register8_t CTRLA; /* Control Register */ +-} HIRES_t; +- +-/* High Resolution Enable */ +-typedef enum HIRES_HREN_enum +-{ +- HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ +- HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ +- HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ +- HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +-} HIRES_HREN_t; +- +- +-/* +--------------------------------------------------------------------------- +-USART - Universal Asynchronous Receiver-Transmitter +--------------------------------------------------------------------------- +-*/ +- +-/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +-typedef struct USART_struct +-{ +- register8_t DATA; /* Data Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x02; +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t BAUDCTRLA; /* Baud Rate Control Register A */ +- register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +-} USART_t; +- +-/* Receive Complete Interrupt level */ +-typedef enum USART_RXCINTLVL_enum +-{ +- USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} USART_RXCINTLVL_t; +- +-/* Transmit Complete Interrupt level */ +-typedef enum USART_TXCINTLVL_enum +-{ +- USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} USART_TXCINTLVL_t; +- +-/* Data Register Empty Interrupt level */ +-typedef enum USART_DREINTLVL_enum +-{ +- USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} USART_DREINTLVL_t; +- +-/* Character Size */ +-typedef enum USART_CHSIZE_enum +-{ +- USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ +- USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ +- USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ +- USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ +- USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +-} USART_CHSIZE_t; +- +-/* Communication Mode */ +-typedef enum USART_CMODE_enum +-{ +- USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ +- USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ +- USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ +- USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +-} USART_CMODE_t; +- +-/* Parity Mode */ +-typedef enum USART_PMODE_enum +-{ +- USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ +- USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ +- USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +-} USART_PMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-SPI - Serial Peripheral Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Serial Peripheral Interface */ +-typedef struct SPI_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t DATA; /* Data Register */ +-} SPI_t; +- +-/* SPI Mode */ +-typedef enum SPI_MODE_enum +-{ +- SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ +- SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ +- SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ +- SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +-} SPI_MODE_t; +- +-/* Prescaler setting */ +-typedef enum SPI_PRESCALER_enum +-{ +- SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ +- SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ +- SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ +- SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +-} SPI_PRESCALER_t; +- +-/* Interrupt level */ +-typedef enum SPI_INTLVL_enum +-{ +- SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} SPI_INTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-IRCOM - IR Communication Module +--------------------------------------------------------------------------- +-*/ +- +-/* IR Communication Module */ +-typedef struct IRCOM_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ +- register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +-} IRCOM_t; +- +-/* Event channel selection */ +-typedef enum IRDA_EVSEL_enum +-{ +- IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ +- IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ +- IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ +- IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +- IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ +- IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ +- IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ +- IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +-} IRDA_EVSEL_t; +- +- +-/* +--------------------------------------------------------------------------- -PRESC - Prescaler -+FUSE - Fuses and Lockbits - -------------------------------------------------------------------------- - */ - +--------------------------------------------------------------------------- +-*/ +- -/* Prescaler */ -typedef struct PRESC_struct -+/* Fuses */ -+typedef struct NVM_FUSES_struct - { +-{ - register8_t PRESCALER; /* Control Register */ -} PRESC_t; -+ register8_t FUSEBYTE0; /* JTAG User ID */ -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+} NVM_FUSES_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* Timer Oscillator pin location */ -+typedef enum TOSCSEL_enum -+{ -+ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ -+ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -+} TOSCSEL_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -+} BOD_t; -+ -+/* BOD operation */ -+typedef enum BODACT_enum -+{ -+ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BODACT_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WDP_enum -+{ -+ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ -+ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ -+ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ -+ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ -+ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ -+ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ -+ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ -+ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ -+ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ -+ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ -+ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -+} WDP_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LOCKBIT - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ - -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ - -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ -+ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t USBCAL0; /* USB Calibration Byte 0 */ -+ register8_t USBCAL1; /* USB Calibration Byte 1 */ -+ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ -+ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ -+ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ -+ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ -+ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ -+ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ -+ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ -+ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ -+ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ -+ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+ register8_t reserved_0x40; -+ register8_t reserved_0x41; -+ register8_t reserved_0x42; -+ register8_t reserved_0x43; -+ register8_t reserved_0x44; -+ register8_t reserved_0x45; -+ register8_t reserved_0x46; -+ register8_t reserved_0x47; -+} NVM_PROD_SIGNATURES_t; - - /* - ========================================================================== -@@ -2622,78 +3045,82 @@ IO Module Instances. Mapped to memory. - ========================================================================== - */ - +- +- +- +-/* +-========================================================================== +-IO Module Instances. Mapped to memory. +-========================================================================== +-*/ +- -#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ -#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ -#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ -#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ - #define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ - #define CLK (*(CLK_t *) 0x0040) /* Clock System */ - #define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +-#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +-#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +-#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ -#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ -#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ - #define PR (*(PR_t *) 0x0070) /* Power Reduction */ +-#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -#define RST (*(RST_t *) 0x0078) /* Reset Controller */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ - #define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ - #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +-#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +-#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ -#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ -#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ -#define CRC (*(CRC_t *) 0x00D0) /* CRC Module */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define AES (*(AES_t *) 0x00C0) /* AES Module */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ - #define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ - #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +-#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +-#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ -#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ -#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ @@ -214503,15 +614857,8 @@ index 646e316..e53146b 100644 -#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ -#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ -#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ -+#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ -+#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ - #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ - #define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */ +-#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +-#define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */ -#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ -#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface D */ -#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ @@ -214535,31 +614882,7 @@ index 646e316..e53146b 100644 -#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ -#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ -#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -+#define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface */ -+#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -+#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -+#define PORTH (*(PORT_t *) 0x06E0) /* I/O Ports */ -+#define PORTJ (*(PORT_t *) 0x0700) /* I/O Ports */ -+#define PORTK (*(PORT_t *) 0x0720) /* I/O Ports */ -+#define PORTQ (*(PORT_t *) 0x07C0) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -+#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -+#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ - #define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +-#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ -#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ -#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ @@ -214579,1165 +614902,1447 @@ index 646e316..e53146b 100644 -#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ -#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ -#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ -+#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -+#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -+#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ -+#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ -+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -+#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -+#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -+#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ -+#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ -+#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ -+#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ -+#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -+#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ -+#define TCF1 (*(TC1_t *) 0x0B40) /* 16-bit Timer/Counter 1 */ -+#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ -+#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface */ - - - #endif /* !defined (__ASSEMBLER__) */ -@@ -2719,25 +3146,89 @@ IO Module Instances. Mapped to memory. - #define GPIO_GPIORE _SFR_MEM8(0x000E) - #define GPIO_GPIORF _SFR_MEM8(0x000F) - --/* VPORT0 - Virtual Port 0 */ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+#define GPIO_GPIO4 _SFR_MEM8(0x0004) -+#define GPIO_GPIO5 _SFR_MEM8(0x0005) -+#define GPIO_GPIO6 _SFR_MEM8(0x0006) -+#define GPIO_GPIO7 _SFR_MEM8(0x0007) -+#define GPIO_GPIO8 _SFR_MEM8(0x0008) -+#define GPIO_GPIO9 _SFR_MEM8(0x0009) -+#define GPIO_GPIOA _SFR_MEM8(0x000A) -+#define GPIO_GPIOB _SFR_MEM8(0x000B) -+#define GPIO_GPIOC _SFR_MEM8(0x000C) -+#define GPIO_GPIOD _SFR_MEM8(0x000D) -+#define GPIO_GPIOE _SFR_MEM8(0x000E) -+#define GPIO_GPIOF _SFR_MEM8(0x000F) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -+#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -+#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -+#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -+#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -+#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -+#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) -+#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) -+#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -+#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) -+#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) -+#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) -+ -+/* VPORT - Virtual Port */ - #define VPORT0_DIR _SFR_MEM8(0x0010) - #define VPORT0_OUT _SFR_MEM8(0x0011) - #define VPORT0_IN _SFR_MEM8(0x0012) - #define VPORT0_INTFLAGS _SFR_MEM8(0x0013) - --/* VPORT1 - Virtual Port 1 */ -+/* VPORT - Virtual Port */ - #define VPORT1_DIR _SFR_MEM8(0x0014) - #define VPORT1_OUT _SFR_MEM8(0x0015) - #define VPORT1_IN _SFR_MEM8(0x0016) - #define VPORT1_INTFLAGS _SFR_MEM8(0x0017) - --/* VPORT2 - Virtual Port 2 */ -+/* VPORT - Virtual Port */ - #define VPORT2_DIR _SFR_MEM8(0x0018) - #define VPORT2_OUT _SFR_MEM8(0x0019) - #define VPORT2_IN _SFR_MEM8(0x001A) - #define VPORT2_INTFLAGS _SFR_MEM8(0x001B) - --/* VPORT3 - Virtual Port 3 */ -+/* VPORT - Virtual Port */ - #define VPORT3_DIR _SFR_MEM8(0x001C) - #define VPORT3_OUT _SFR_MEM8(0x001D) - #define VPORT3_IN _SFR_MEM8(0x001E) -@@ -2747,7 +3238,7 @@ IO Module Instances. Mapped to memory. - #define OCD_OCDR0 _SFR_MEM8(0x002E) - #define OCD_OCDR1 _SFR_MEM8(0x002F) - --/* CPU - CPU Registers */ -+/* CPU - CPU registers */ - #define CPU_CCP _SFR_MEM8(0x0034) - #define CPU_RAMPD _SFR_MEM8(0x0038) - #define CPU_RAMPX _SFR_MEM8(0x0039) -@@ -2768,16 +3259,16 @@ IO Module Instances. Mapped to memory. - /* SLEEP - Sleep Controller */ - #define SLEEP_CTRL _SFR_MEM8(0x0048) - --/* OSC - Oscillator Control */ -+/* OSC - Oscillator */ - #define OSC_CTRL _SFR_MEM8(0x0050) - #define OSC_STATUS _SFR_MEM8(0x0051) - #define OSC_XOSCCTRL _SFR_MEM8(0x0052) --#define OSC_XOSCFAIL _SFR_MEM8(0x005F) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) - #define OSC_RC32KCAL _SFR_MEM8(0x0054) - #define OSC_PLLCTRL _SFR_MEM8(0x0055) - #define OSC_DFLLCTRL _SFR_MEM8(0x0056) - --/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ -+/* DFLL - DFLL */ - #define DFLLRC32M_CTRL _SFR_MEM8(0x0060) - #define DFLLRC32M_CALA _SFR_MEM8(0x0062) - #define DFLLRC32M_CALB _SFR_MEM8(0x0063) -@@ -2785,7 +3276,7 @@ IO Module Instances. Mapped to memory. - #define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) - #define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) - --/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ -+/* DFLL - DFLL */ - #define DFLLRC2M_CTRL _SFR_MEM8(0x0068) - #define DFLLRC2M_CALA _SFR_MEM8(0x006A) - #define DFLLRC2M_CALB _SFR_MEM8(0x006B) -@@ -2802,7 +3293,7 @@ IO Module Instances. Mapped to memory. - #define PR_PRPE _SFR_MEM8(0x0075) - #define PR_PRPF _SFR_MEM8(0x0076) - --/* RST - Reset Controller */ -+/* RST - Reset */ - #define RST_STATUS _SFR_MEM8(0x0078) - #define RST_CTRL _SFR_MEM8(0x0079) - -@@ -2822,25 +3313,27 @@ IO Module Instances. Mapped to memory. - #define MCU_EVSYSLOCK _SFR_MEM8(0x0098) - #define MCU_AWEXLOCK _SFR_MEM8(0x0099) - --/* PMIC - Programmable Interrupt Controller */ -+/* PMIC - Programmable Multi-level Interrupt Controller */ - #define PMIC_STATUS _SFR_MEM8(0x00A0) - #define PMIC_INTPRI _SFR_MEM8(0x00A1) - #define PMIC_CTRL _SFR_MEM8(0x00A2) - --/* PORTCFG - Port Configuration */ -+/* PORTCFG - I/O port Configuration */ - #define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) - #define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) - #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) - #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) -+#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) - --/* AES - AES Crypto Module */ -+/* AES - AES Module */ - #define AES_CTRL _SFR_MEM8(0x00C0) - #define AES_STATUS _SFR_MEM8(0x00C1) - #define AES_STATE _SFR_MEM8(0x00C2) - #define AES_KEY _SFR_MEM8(0x00C3) - #define AES_INTCTRL _SFR_MEM8(0x00C4) - --/* CRC - CRC Module */ -+/* CRC - Cyclic Redundancy Checker */ - #define CRC_CTRL _SFR_MEM8(0x00D0) - #define CRC_STATUS _SFR_MEM8(0x00D1) - #define CRC_DATAIN _SFR_MEM8(0x00D3) -@@ -2923,7 +3416,7 @@ IO Module Instances. Mapped to memory. - #define EVSYS_STROBE _SFR_MEM8(0x0190) - #define EVSYS_DATA _SFR_MEM8(0x0191) - --/* NVM - Non Volatile Memory Controller */ -+/* NVM - Non-volatile Memory Controller */ - #define NVM_ADDR0 _SFR_MEM8(0x01C0) - #define NVM_ADDR1 _SFR_MEM8(0x01C1) - #define NVM_ADDR2 _SFR_MEM8(0x01C2) -@@ -2937,7 +3430,7 @@ IO Module Instances. Mapped to memory. - #define NVM_STATUS _SFR_MEM8(0x01CF) - #define NVM_LOCKBITS _SFR_MEM8(0x01D0) - --/* ADCA - Analog to Digital Converter A */ -+/* ADC - Analog-to-Digital Converter */ - #define ADCA_CTRLA _SFR_MEM8(0x0200) - #define ADCA_CTRLB _SFR_MEM8(0x0201) - #define ADCA_REFCTRL _SFR_MEM8(0x0202) -@@ -2956,23 +3449,27 @@ IO Module Instances. Mapped to memory. - #define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) - #define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) - #define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) - #define ADCA_CH1_CTRL _SFR_MEM8(0x0228) - #define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) - #define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) - #define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) - #define ADCA_CH1_RES _SFR_MEM16(0x022C) -+#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) - #define ADCA_CH2_CTRL _SFR_MEM8(0x0230) - #define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) - #define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) - #define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) - #define ADCA_CH2_RES _SFR_MEM16(0x0234) -+#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) - #define ADCA_CH3_CTRL _SFR_MEM8(0x0238) - #define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) - #define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) - #define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) - #define ADCA_CH3_RES _SFR_MEM16(0x023C) -+#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) - --/* ADCB - Analog to Digital Converter B */ -+/* ADC - Analog-to-Digital Converter */ - #define ADCB_CTRLA _SFR_MEM8(0x0240) - #define ADCB_CTRLB _SFR_MEM8(0x0241) - #define ADCB_REFCTRL _SFR_MEM8(0x0242) -@@ -2991,28 +3488,31 @@ IO Module Instances. Mapped to memory. - #define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) - #define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) - #define ADCB_CH0_RES _SFR_MEM16(0x0264) -+#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) - #define ADCB_CH1_CTRL _SFR_MEM8(0x0268) - #define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) - #define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) - #define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) - #define ADCB_CH1_RES _SFR_MEM16(0x026C) -+#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) - #define ADCB_CH2_CTRL _SFR_MEM8(0x0270) - #define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) - #define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) - #define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) - #define ADCB_CH2_RES _SFR_MEM16(0x0274) -+#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) - #define ADCB_CH3_CTRL _SFR_MEM8(0x0278) - #define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) - #define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) - #define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) - #define ADCB_CH3_RES _SFR_MEM16(0x027C) -+#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) - --/* DACA - Digital to Analog Converter A */ -+/* DAC - Digital-to-Analog Converter */ - #define DACA_CTRLA _SFR_MEM8(0x0300) - #define DACA_CTRLB _SFR_MEM8(0x0301) - #define DACA_CTRLC _SFR_MEM8(0x0302) - #define DACA_EVCTRL _SFR_MEM8(0x0303) --#define DACA_TIMCTRL _SFR_MEM8(0x0304) - #define DACA_STATUS _SFR_MEM8(0x0305) - #define DACA_CH0GAINCAL _SFR_MEM8(0x0308) - #define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) -@@ -3021,12 +3521,11 @@ IO Module Instances. Mapped to memory. - #define DACA_CH0DATA _SFR_MEM16(0x0318) - #define DACA_CH1DATA _SFR_MEM16(0x031A) - --/* DACB - Digital to Analog Converter B */ -+/* DAC - Digital-to-Analog Converter */ - #define DACB_CTRLA _SFR_MEM8(0x0320) - #define DACB_CTRLB _SFR_MEM8(0x0321) - #define DACB_CTRLC _SFR_MEM8(0x0322) - #define DACB_EVCTRL _SFR_MEM8(0x0323) --#define DACB_TIMCTRL _SFR_MEM8(0x0324) - #define DACB_STATUS _SFR_MEM8(0x0325) - #define DACB_CH0GAINCAL _SFR_MEM8(0x0328) - #define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) -@@ -3035,7 +3534,7 @@ IO Module Instances. Mapped to memory. - #define DACB_CH0DATA _SFR_MEM16(0x0338) - #define DACB_CH1DATA _SFR_MEM16(0x033A) - --/* ACA - Analog Comparator A */ -+/* AC - Analog Comparator */ - #define ACA_AC0CTRL _SFR_MEM8(0x0380) - #define ACA_AC1CTRL _SFR_MEM8(0x0381) - #define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -@@ -3045,7 +3544,7 @@ IO Module Instances. Mapped to memory. - #define ACA_WINCTRL _SFR_MEM8(0x0386) - #define ACA_STATUS _SFR_MEM8(0x0387) - --/* ACB - Analog Comparator B */ -+/* AC - Analog Comparator */ - #define ACB_AC0CTRL _SFR_MEM8(0x0390) - #define ACB_AC1CTRL _SFR_MEM8(0x0391) - #define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -@@ -3085,7 +3584,7 @@ IO Module Instances. Mapped to memory. - #define EBI_CS3_CTRLB _SFR_MEM8(0x045D) - #define EBI_CS3_BASEADDR _SFR_MEM16(0x045E) - --/* TWIC - Two-Wire Interface C */ -+/* TWI - Two-Wire Interface */ - #define TWIC_CTRL _SFR_MEM8(0x0480) - #define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) - #define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -@@ -3101,7 +3600,7 @@ IO Module Instances. Mapped to memory. - #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) - #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - --/* TWID - Two-Wire Interface D */ -+/* TWI - Two-Wire Interface */ - #define TWID_CTRL _SFR_MEM8(0x0490) - #define TWID_MASTER_CTRLA _SFR_MEM8(0x0491) - #define TWID_MASTER_CTRLB _SFR_MEM8(0x0492) -@@ -3117,7 +3616,7 @@ IO Module Instances. Mapped to memory. - #define TWID_SLAVE_DATA _SFR_MEM8(0x049C) - #define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D) - --/* TWIE - Two-Wire Interface E */ -+/* TWI - Two-Wire Interface */ - #define TWIE_CTRL _SFR_MEM8(0x04A0) - #define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) - #define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -@@ -3133,7 +3632,7 @@ IO Module Instances. Mapped to memory. - #define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) - #define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) - --/* TWIF - Two-Wire Interface F */ -+/* TWI - Two-Wire Interface */ - #define TWIF_CTRL _SFR_MEM8(0x04B0) - #define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1) - #define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2) -@@ -3149,7 +3648,7 @@ IO Module Instances. Mapped to memory. - #define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC) - #define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD) - --/* USB - Universal Serial Bus Module */ -+/* USB - Universal Serial Bus */ - #define USB_CTRLA _SFR_MEM8(0x04C0) - #define USB_CTRLB _SFR_MEM8(0x04C1) - #define USB_STATUS _SFR_MEM8(0x04C2) -@@ -3166,7 +3665,7 @@ IO Module Instances. Mapped to memory. - #define USB_CAL0 _SFR_MEM8(0x04FA) - #define USB_CAL1 _SFR_MEM8(0x04FB) - --/* PORTA - Port A */ -+/* PORT - I/O Ports */ - #define PORTA_DIR _SFR_MEM8(0x0600) - #define PORTA_DIRSET _SFR_MEM8(0x0601) - #define PORTA_DIRCLR _SFR_MEM8(0x0602) -@@ -3180,6 +3679,7 @@ IO Module Instances. Mapped to memory. - #define PORTA_INT0MASK _SFR_MEM8(0x060A) - #define PORTA_INT1MASK _SFR_MEM8(0x060B) - #define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_REMAP _SFR_MEM8(0x060E) - #define PORTA_PIN0CTRL _SFR_MEM8(0x0610) - #define PORTA_PIN1CTRL _SFR_MEM8(0x0611) - #define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -@@ -3189,7 +3689,7 @@ IO Module Instances. Mapped to memory. - #define PORTA_PIN6CTRL _SFR_MEM8(0x0616) - #define PORTA_PIN7CTRL _SFR_MEM8(0x0617) - --/* PORTB - Port B */ -+/* PORT - I/O Ports */ - #define PORTB_DIR _SFR_MEM8(0x0620) - #define PORTB_DIRSET _SFR_MEM8(0x0621) - #define PORTB_DIRCLR _SFR_MEM8(0x0622) -@@ -3203,6 +3703,7 @@ IO Module Instances. Mapped to memory. - #define PORTB_INT0MASK _SFR_MEM8(0x062A) - #define PORTB_INT1MASK _SFR_MEM8(0x062B) - #define PORTB_INTFLAGS _SFR_MEM8(0x062C) -+#define PORTB_REMAP _SFR_MEM8(0x062E) - #define PORTB_PIN0CTRL _SFR_MEM8(0x0630) - #define PORTB_PIN1CTRL _SFR_MEM8(0x0631) - #define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -@@ -3212,7 +3713,7 @@ IO Module Instances. Mapped to memory. - #define PORTB_PIN6CTRL _SFR_MEM8(0x0636) - #define PORTB_PIN7CTRL _SFR_MEM8(0x0637) - --/* PORTC - Port C */ -+/* PORT - I/O Ports */ - #define PORTC_DIR _SFR_MEM8(0x0640) - #define PORTC_DIRSET _SFR_MEM8(0x0641) - #define PORTC_DIRCLR _SFR_MEM8(0x0642) -@@ -3226,6 +3727,7 @@ IO Module Instances. Mapped to memory. - #define PORTC_INT0MASK _SFR_MEM8(0x064A) - #define PORTC_INT1MASK _SFR_MEM8(0x064B) - #define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) - #define PORTC_PIN0CTRL _SFR_MEM8(0x0650) - #define PORTC_PIN1CTRL _SFR_MEM8(0x0651) - #define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -@@ -3235,7 +3737,7 @@ IO Module Instances. Mapped to memory. - #define PORTC_PIN6CTRL _SFR_MEM8(0x0656) - #define PORTC_PIN7CTRL _SFR_MEM8(0x0657) - --/* PORTD - Port D */ -+/* PORT - I/O Ports */ - #define PORTD_DIR _SFR_MEM8(0x0660) - #define PORTD_DIRSET _SFR_MEM8(0x0661) - #define PORTD_DIRCLR _SFR_MEM8(0x0662) -@@ -3249,6 +3751,7 @@ IO Module Instances. Mapped to memory. - #define PORTD_INT0MASK _SFR_MEM8(0x066A) - #define PORTD_INT1MASK _SFR_MEM8(0x066B) - #define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) - #define PORTD_PIN0CTRL _SFR_MEM8(0x0670) - #define PORTD_PIN1CTRL _SFR_MEM8(0x0671) - #define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -@@ -3258,7 +3761,7 @@ IO Module Instances. Mapped to memory. - #define PORTD_PIN6CTRL _SFR_MEM8(0x0676) - #define PORTD_PIN7CTRL _SFR_MEM8(0x0677) - --/* PORTE - Port E */ -+/* PORT - I/O Ports */ - #define PORTE_DIR _SFR_MEM8(0x0680) - #define PORTE_DIRSET _SFR_MEM8(0x0681) - #define PORTE_DIRCLR _SFR_MEM8(0x0682) -@@ -3272,6 +3775,7 @@ IO Module Instances. Mapped to memory. - #define PORTE_INT0MASK _SFR_MEM8(0x068A) - #define PORTE_INT1MASK _SFR_MEM8(0x068B) - #define PORTE_INTFLAGS _SFR_MEM8(0x068C) -+#define PORTE_REMAP _SFR_MEM8(0x068E) - #define PORTE_PIN0CTRL _SFR_MEM8(0x0690) - #define PORTE_PIN1CTRL _SFR_MEM8(0x0691) - #define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -@@ -3281,7 +3785,7 @@ IO Module Instances. Mapped to memory. - #define PORTE_PIN6CTRL _SFR_MEM8(0x0696) - #define PORTE_PIN7CTRL _SFR_MEM8(0x0697) - --/* PORTF - Port F */ -+/* PORT - I/O Ports */ - #define PORTF_DIR _SFR_MEM8(0x06A0) - #define PORTF_DIRSET _SFR_MEM8(0x06A1) - #define PORTF_DIRCLR _SFR_MEM8(0x06A2) -@@ -3295,6 +3799,7 @@ IO Module Instances. Mapped to memory. - #define PORTF_INT0MASK _SFR_MEM8(0x06AA) - #define PORTF_INT1MASK _SFR_MEM8(0x06AB) - #define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -+#define PORTF_REMAP _SFR_MEM8(0x06AE) - #define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) - #define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) - #define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -@@ -3304,7 +3809,7 @@ IO Module Instances. Mapped to memory. - #define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) - #define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) - --/* PORTH - Port H */ -+/* PORT - I/O Ports */ - #define PORTH_DIR _SFR_MEM8(0x06E0) - #define PORTH_DIRSET _SFR_MEM8(0x06E1) - #define PORTH_DIRCLR _SFR_MEM8(0x06E2) -@@ -3318,6 +3823,7 @@ IO Module Instances. Mapped to memory. - #define PORTH_INT0MASK _SFR_MEM8(0x06EA) - #define PORTH_INT1MASK _SFR_MEM8(0x06EB) - #define PORTH_INTFLAGS _SFR_MEM8(0x06EC) -+#define PORTH_REMAP _SFR_MEM8(0x06EE) - #define PORTH_PIN0CTRL _SFR_MEM8(0x06F0) - #define PORTH_PIN1CTRL _SFR_MEM8(0x06F1) - #define PORTH_PIN2CTRL _SFR_MEM8(0x06F2) -@@ -3327,7 +3833,7 @@ IO Module Instances. Mapped to memory. - #define PORTH_PIN6CTRL _SFR_MEM8(0x06F6) - #define PORTH_PIN7CTRL _SFR_MEM8(0x06F7) - --/* PORTJ - Port J */ -+/* PORT - I/O Ports */ - #define PORTJ_DIR _SFR_MEM8(0x0700) - #define PORTJ_DIRSET _SFR_MEM8(0x0701) - #define PORTJ_DIRCLR _SFR_MEM8(0x0702) -@@ -3341,6 +3847,7 @@ IO Module Instances. Mapped to memory. - #define PORTJ_INT0MASK _SFR_MEM8(0x070A) - #define PORTJ_INT1MASK _SFR_MEM8(0x070B) - #define PORTJ_INTFLAGS _SFR_MEM8(0x070C) -+#define PORTJ_REMAP _SFR_MEM8(0x070E) - #define PORTJ_PIN0CTRL _SFR_MEM8(0x0710) - #define PORTJ_PIN1CTRL _SFR_MEM8(0x0711) - #define PORTJ_PIN2CTRL _SFR_MEM8(0x0712) -@@ -3350,7 +3857,7 @@ IO Module Instances. Mapped to memory. - #define PORTJ_PIN6CTRL _SFR_MEM8(0x0716) - #define PORTJ_PIN7CTRL _SFR_MEM8(0x0717) - --/* PORTK - Port K */ -+/* PORT - I/O Ports */ - #define PORTK_DIR _SFR_MEM8(0x0720) - #define PORTK_DIRSET _SFR_MEM8(0x0721) - #define PORTK_DIRCLR _SFR_MEM8(0x0722) -@@ -3364,6 +3871,7 @@ IO Module Instances. Mapped to memory. - #define PORTK_INT0MASK _SFR_MEM8(0x072A) - #define PORTK_INT1MASK _SFR_MEM8(0x072B) - #define PORTK_INTFLAGS _SFR_MEM8(0x072C) -+#define PORTK_REMAP _SFR_MEM8(0x072E) - #define PORTK_PIN0CTRL _SFR_MEM8(0x0730) - #define PORTK_PIN1CTRL _SFR_MEM8(0x0731) - #define PORTK_PIN2CTRL _SFR_MEM8(0x0732) -@@ -3373,7 +3881,7 @@ IO Module Instances. Mapped to memory. - #define PORTK_PIN6CTRL _SFR_MEM8(0x0736) - #define PORTK_PIN7CTRL _SFR_MEM8(0x0737) - --/* PORTQ - Port Q */ -+/* PORT - I/O Ports */ - #define PORTQ_DIR _SFR_MEM8(0x07C0) - #define PORTQ_DIRSET _SFR_MEM8(0x07C1) - #define PORTQ_DIRCLR _SFR_MEM8(0x07C2) -@@ -3387,6 +3895,7 @@ IO Module Instances. Mapped to memory. - #define PORTQ_INT0MASK _SFR_MEM8(0x07CA) - #define PORTQ_INT1MASK _SFR_MEM8(0x07CB) - #define PORTQ_INTFLAGS _SFR_MEM8(0x07CC) -+#define PORTQ_REMAP _SFR_MEM8(0x07CE) - #define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0) - #define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1) - #define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2) -@@ -3396,7 +3905,7 @@ IO Module Instances. Mapped to memory. - #define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6) - #define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7) - --/* PORTR - Port R */ -+/* PORT - I/O Ports */ - #define PORTR_DIR _SFR_MEM8(0x07E0) - #define PORTR_DIRSET _SFR_MEM8(0x07E1) - #define PORTR_DIRCLR _SFR_MEM8(0x07E2) -@@ -3410,6 +3919,7 @@ IO Module Instances. Mapped to memory. - #define PORTR_INT0MASK _SFR_MEM8(0x07EA) - #define PORTR_INT1MASK _SFR_MEM8(0x07EB) - #define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) - #define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) - #define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) - #define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -@@ -3419,7 +3929,7 @@ IO Module Instances. Mapped to memory. - #define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) - #define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) - --/* TCC0 - Timer/Counter C0 */ -+/* TC0 - 16-bit Timer/Counter 0 */ - #define TCC0_CTRLA _SFR_MEM8(0x0800) - #define TCC0_CTRLB _SFR_MEM8(0x0801) - #define TCC0_CTRLC _SFR_MEM8(0x0802) -@@ -3445,7 +3955,29 @@ IO Module Instances. Mapped to memory. - #define TCC0_CCCBUF _SFR_MEM16(0x083C) - #define TCC0_CCDBUF _SFR_MEM16(0x083E) - --/* TCC1 - Timer/Counter C1 */ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCC2_CTRLA _SFR_MEM8(0x0800) -+#define TCC2_CTRLB _SFR_MEM8(0x0801) -+#define TCC2_CTRLC _SFR_MEM8(0x0802) -+#define TCC2_CTRLE _SFR_MEM8(0x0804) -+#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC2_CTRLF _SFR_MEM8(0x0809) -+#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC2_LCNT _SFR_MEM8(0x0820) -+#define TCC2_HCNT _SFR_MEM8(0x0821) -+#define TCC2_LPER _SFR_MEM8(0x0826) -+#define TCC2_HPER _SFR_MEM8(0x0827) -+#define TCC2_LCMPA _SFR_MEM8(0x0828) -+#define TCC2_HCMPA _SFR_MEM8(0x0829) -+#define TCC2_LCMPB _SFR_MEM8(0x082A) -+#define TCC2_HCMPB _SFR_MEM8(0x082B) -+#define TCC2_LCMPC _SFR_MEM8(0x082C) -+#define TCC2_HCMPC _SFR_MEM8(0x082D) -+#define TCC2_LCMPD _SFR_MEM8(0x082E) -+#define TCC2_HCMPD _SFR_MEM8(0x082F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ - #define TCC1_CTRLA _SFR_MEM8(0x0840) - #define TCC1_CTRLB _SFR_MEM8(0x0841) - #define TCC1_CTRLC _SFR_MEM8(0x0842) -@@ -3467,11 +3999,12 @@ IO Module Instances. Mapped to memory. - #define TCC1_CCABUF _SFR_MEM16(0x0878) - #define TCC1_CCBBUF _SFR_MEM16(0x087A) - --/* AWEXC - Advanced Waveform Extension C */ -+/* AWEX - Advanced Waveform Extension */ - #define AWEXC_CTRL _SFR_MEM8(0x0880) - #define AWEXC_FDEMASK _SFR_MEM8(0x0882) - #define AWEXC_FDCTRL _SFR_MEM8(0x0883) - #define AWEXC_STATUS _SFR_MEM8(0x0884) -+#define AWEXC_STATUSSET _SFR_MEM8(0x0885) - #define AWEXC_DTBOTH _SFR_MEM8(0x0886) - #define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) - #define AWEXC_DTLS _SFR_MEM8(0x0888) -@@ -3480,10 +4013,10 @@ IO Module Instances. Mapped to memory. - #define AWEXC_DTHSBUF _SFR_MEM8(0x088B) - #define AWEXC_OUTOVEN _SFR_MEM8(0x088C) - --/* HIRESC - High-Resolution Extension C */ -+/* HIRES - High-Resolution Extension */ - #define HIRESC_CTRLA _SFR_MEM8(0x0890) - --/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ - #define USARTC0_DATA _SFR_MEM8(0x08A0) - #define USARTC0_STATUS _SFR_MEM8(0x08A1) - #define USARTC0_CTRLA _SFR_MEM8(0x08A3) -@@ -3492,7 +4025,7 @@ IO Module Instances. Mapped to memory. - #define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) - #define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) - --/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ - #define USARTC1_DATA _SFR_MEM8(0x08B0) - #define USARTC1_STATUS _SFR_MEM8(0x08B1) - #define USARTC1_CTRLA _SFR_MEM8(0x08B3) -@@ -3501,7 +4034,7 @@ IO Module Instances. Mapped to memory. - #define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) - #define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) - --/* SPIC - Serial Peripheral Interface C */ -+/* SPI - Serial Peripheral Interface */ - #define SPIC_CTRL _SFR_MEM8(0x08C0) - #define SPIC_INTCTRL _SFR_MEM8(0x08C1) - #define SPIC_STATUS _SFR_MEM8(0x08C2) -@@ -3512,7 +4045,7 @@ IO Module Instances. Mapped to memory. - #define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) - #define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) - --/* TCD0 - Timer/Counter D0 */ -+/* TC0 - 16-bit Timer/Counter 0 */ - #define TCD0_CTRLA _SFR_MEM8(0x0900) - #define TCD0_CTRLB _SFR_MEM8(0x0901) - #define TCD0_CTRLC _SFR_MEM8(0x0902) -@@ -3538,7 +4071,29 @@ IO Module Instances. Mapped to memory. - #define TCD0_CCCBUF _SFR_MEM16(0x093C) - #define TCD0_CCDBUF _SFR_MEM16(0x093E) - --/* TCD1 - Timer/Counter D1 */ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCD2_CTRLA _SFR_MEM8(0x0900) -+#define TCD2_CTRLB _SFR_MEM8(0x0901) -+#define TCD2_CTRLC _SFR_MEM8(0x0902) -+#define TCD2_CTRLE _SFR_MEM8(0x0904) -+#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD2_CTRLF _SFR_MEM8(0x0909) -+#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD2_LCNT _SFR_MEM8(0x0920) -+#define TCD2_HCNT _SFR_MEM8(0x0921) -+#define TCD2_LPER _SFR_MEM8(0x0926) -+#define TCD2_HPER _SFR_MEM8(0x0927) -+#define TCD2_LCMPA _SFR_MEM8(0x0928) -+#define TCD2_HCMPA _SFR_MEM8(0x0929) -+#define TCD2_LCMPB _SFR_MEM8(0x092A) -+#define TCD2_HCMPB _SFR_MEM8(0x092B) -+#define TCD2_LCMPC _SFR_MEM8(0x092C) -+#define TCD2_HCMPC _SFR_MEM8(0x092D) -+#define TCD2_LCMPD _SFR_MEM8(0x092E) -+#define TCD2_HCMPD _SFR_MEM8(0x092F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ - #define TCD1_CTRLA _SFR_MEM8(0x0940) - #define TCD1_CTRLB _SFR_MEM8(0x0941) - #define TCD1_CTRLC _SFR_MEM8(0x0942) -@@ -3560,10 +4115,10 @@ IO Module Instances. Mapped to memory. - #define TCD1_CCABUF _SFR_MEM16(0x0978) - #define TCD1_CCBBUF _SFR_MEM16(0x097A) - --/* HIRESD - High-Resolution Extension D */ -+/* HIRES - High-Resolution Extension */ - #define HIRESD_CTRLA _SFR_MEM8(0x0990) - --/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ - #define USARTD0_DATA _SFR_MEM8(0x09A0) - #define USARTD0_STATUS _SFR_MEM8(0x09A1) - #define USARTD0_CTRLA _SFR_MEM8(0x09A3) -@@ -3572,7 +4127,7 @@ IO Module Instances. Mapped to memory. - #define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) - #define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) - --/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ - #define USARTD1_DATA _SFR_MEM8(0x09B0) - #define USARTD1_STATUS _SFR_MEM8(0x09B1) - #define USARTD1_CTRLA _SFR_MEM8(0x09B3) -@@ -3581,13 +4136,13 @@ IO Module Instances. Mapped to memory. - #define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) - #define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) - --/* SPID - Serial Peripheral Interface D */ -+/* SPI - Serial Peripheral Interface */ - #define SPID_CTRL _SFR_MEM8(0x09C0) - #define SPID_INTCTRL _SFR_MEM8(0x09C1) - #define SPID_STATUS _SFR_MEM8(0x09C2) - #define SPID_DATA _SFR_MEM8(0x09C3) - --/* TCE0 - Timer/Counter E0 */ -+/* TC0 - 16-bit Timer/Counter 0 */ - #define TCE0_CTRLA _SFR_MEM8(0x0A00) - #define TCE0_CTRLB _SFR_MEM8(0x0A01) - #define TCE0_CTRLC _SFR_MEM8(0x0A02) -@@ -3613,7 +4168,29 @@ IO Module Instances. Mapped to memory. - #define TCE0_CCCBUF _SFR_MEM16(0x0A3C) - #define TCE0_CCDBUF _SFR_MEM16(0x0A3E) - --/* TCE1 - Timer/Counter E1 */ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCE2_CTRLA _SFR_MEM8(0x0A00) -+#define TCE2_CTRLB _SFR_MEM8(0x0A01) -+#define TCE2_CTRLC _SFR_MEM8(0x0A02) -+#define TCE2_CTRLE _SFR_MEM8(0x0A04) -+#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE2_CTRLF _SFR_MEM8(0x0A09) -+#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE2_LCNT _SFR_MEM8(0x0A20) -+#define TCE2_HCNT _SFR_MEM8(0x0A21) -+#define TCE2_LPER _SFR_MEM8(0x0A26) -+#define TCE2_HPER _SFR_MEM8(0x0A27) -+#define TCE2_LCMPA _SFR_MEM8(0x0A28) -+#define TCE2_HCMPA _SFR_MEM8(0x0A29) -+#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -+#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -+#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -+#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -+#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -+#define TCE2_HCMPD _SFR_MEM8(0x0A2F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ - #define TCE1_CTRLA _SFR_MEM8(0x0A40) - #define TCE1_CTRLB _SFR_MEM8(0x0A41) - #define TCE1_CTRLC _SFR_MEM8(0x0A42) -@@ -3635,11 +4212,12 @@ IO Module Instances. Mapped to memory. - #define TCE1_CCABUF _SFR_MEM16(0x0A78) - #define TCE1_CCBBUF _SFR_MEM16(0x0A7A) - --/* AWEXE - Advanced Waveform Extension E */ -+/* AWEX - Advanced Waveform Extension */ - #define AWEXE_CTRL _SFR_MEM8(0x0A80) - #define AWEXE_FDEMASK _SFR_MEM8(0x0A82) - #define AWEXE_FDCTRL _SFR_MEM8(0x0A83) - #define AWEXE_STATUS _SFR_MEM8(0x0A84) -+#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) - #define AWEXE_DTBOTH _SFR_MEM8(0x0A86) - #define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) - #define AWEXE_DTLS _SFR_MEM8(0x0A88) -@@ -3648,10 +4226,10 @@ IO Module Instances. Mapped to memory. - #define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) - #define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) - --/* HIRESE - High-Resolution Extension E */ -+/* HIRES - High-Resolution Extension */ - #define HIRESE_CTRLA _SFR_MEM8(0x0A90) - --/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ - #define USARTE0_DATA _SFR_MEM8(0x0AA0) - #define USARTE0_STATUS _SFR_MEM8(0x0AA1) - #define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -@@ -3660,7 +4238,7 @@ IO Module Instances. Mapped to memory. - #define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) - #define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) - --/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ - #define USARTE1_DATA _SFR_MEM8(0x0AB0) - #define USARTE1_STATUS _SFR_MEM8(0x0AB1) - #define USARTE1_CTRLA _SFR_MEM8(0x0AB3) -@@ -3669,13 +4247,13 @@ IO Module Instances. Mapped to memory. - #define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) - #define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) - --/* SPIE - Serial Peripheral Interface E */ -+/* SPI - Serial Peripheral Interface */ - #define SPIE_CTRL _SFR_MEM8(0x0AC0) - #define SPIE_INTCTRL _SFR_MEM8(0x0AC1) - #define SPIE_STATUS _SFR_MEM8(0x0AC2) - #define SPIE_DATA _SFR_MEM8(0x0AC3) - --/* TCF0 - Timer/Counter F0 */ -+/* TC0 - 16-bit Timer/Counter 0 */ - #define TCF0_CTRLA _SFR_MEM8(0x0B00) - #define TCF0_CTRLB _SFR_MEM8(0x0B01) - #define TCF0_CTRLC _SFR_MEM8(0x0B02) -@@ -3701,7 +4279,29 @@ IO Module Instances. Mapped to memory. - #define TCF0_CCCBUF _SFR_MEM16(0x0B3C) - #define TCF0_CCDBUF _SFR_MEM16(0x0B3E) - --/* TCF1 - Timer/Counter F1 */ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCF2_CTRLA _SFR_MEM8(0x0B00) -+#define TCF2_CTRLB _SFR_MEM8(0x0B01) -+#define TCF2_CTRLC _SFR_MEM8(0x0B02) -+#define TCF2_CTRLE _SFR_MEM8(0x0B04) -+#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -+#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -+#define TCF2_CTRLF _SFR_MEM8(0x0B09) -+#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -+#define TCF2_LCNT _SFR_MEM8(0x0B20) -+#define TCF2_HCNT _SFR_MEM8(0x0B21) -+#define TCF2_LPER _SFR_MEM8(0x0B26) -+#define TCF2_HPER _SFR_MEM8(0x0B27) -+#define TCF2_LCMPA _SFR_MEM8(0x0B28) -+#define TCF2_HCMPA _SFR_MEM8(0x0B29) -+#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -+#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -+#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -+#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -+#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -+#define TCF2_HCMPD _SFR_MEM8(0x0B2F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ - #define TCF1_CTRLA _SFR_MEM8(0x0B40) - #define TCF1_CTRLB _SFR_MEM8(0x0B41) - #define TCF1_CTRLC _SFR_MEM8(0x0B42) -@@ -3723,10 +4323,10 @@ IO Module Instances. Mapped to memory. - #define TCF1_CCABUF _SFR_MEM16(0x0B78) - #define TCF1_CCBBUF _SFR_MEM16(0x0B7A) - --/* HIRESF - High-Resolution Extension F */ -+/* HIRES - High-Resolution Extension */ - #define HIRESF_CTRLA _SFR_MEM8(0x0B90) - --/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ - #define USARTF0_DATA _SFR_MEM8(0x0BA0) - #define USARTF0_STATUS _SFR_MEM8(0x0BA1) - #define USARTF0_CTRLA _SFR_MEM8(0x0BA3) -@@ -3735,7 +4335,7 @@ IO Module Instances. Mapped to memory. - #define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) - #define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) - --/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ - #define USARTF1_DATA _SFR_MEM8(0x0BB0) - #define USARTF1_STATUS _SFR_MEM8(0x0BB1) - #define USARTF1_CTRLA _SFR_MEM8(0x0BB3) -@@ -3744,7 +4344,7 @@ IO Module Instances. Mapped to memory. - #define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) - #define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) - --/* SPIF - Serial Peripheral Interface F */ -+/* SPI - Serial Peripheral Interface */ - #define SPIF_CTRL _SFR_MEM8(0x0BC0) - #define SPIF_INTCTRL _SFR_MEM8(0x0BC1) - #define SPIF_STATUS _SFR_MEM8(0x0BC2) -@@ -3762,12 +4362,30 @@ IO Module Instances. Mapped to memory. - #define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ - #define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - - - /* XOCD - On-Chip Debug System */ +- +-#endif /* !defined (__ASSEMBLER__) */ +- +- +-/* ========== Flattened fully qualified IO register names ========== */ +- +-/* GPIO - General Purpose IO Registers */ +-#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +-#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +-#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +-#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +-#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +-#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +-#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +-#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +-#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +-#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +-#define GPIO_GPIORA _SFR_MEM8(0x000A) +-#define GPIO_GPIORB _SFR_MEM8(0x000B) +-#define GPIO_GPIORC _SFR_MEM8(0x000C) +-#define GPIO_GPIORD _SFR_MEM8(0x000D) +-#define GPIO_GPIORE _SFR_MEM8(0x000E) +-#define GPIO_GPIORF _SFR_MEM8(0x000F) +- +-/* VPORT0 - Virtual Port 0 */ +-#define VPORT0_DIR _SFR_MEM8(0x0010) +-#define VPORT0_OUT _SFR_MEM8(0x0011) +-#define VPORT0_IN _SFR_MEM8(0x0012) +-#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) +- +-/* VPORT1 - Virtual Port 1 */ +-#define VPORT1_DIR _SFR_MEM8(0x0014) +-#define VPORT1_OUT _SFR_MEM8(0x0015) +-#define VPORT1_IN _SFR_MEM8(0x0016) +-#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) +- +-/* VPORT2 - Virtual Port 2 */ +-#define VPORT2_DIR _SFR_MEM8(0x0018) +-#define VPORT2_OUT _SFR_MEM8(0x0019) +-#define VPORT2_IN _SFR_MEM8(0x001A) +-#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) +- +-/* VPORT3 - Virtual Port 3 */ +-#define VPORT3_DIR _SFR_MEM8(0x001C) +-#define VPORT3_OUT _SFR_MEM8(0x001D) +-#define VPORT3_IN _SFR_MEM8(0x001E) +-#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) +- +-/* OCD - On-Chip Debug System */ +-#define OCD_OCDR0 _SFR_MEM8(0x002E) +-#define OCD_OCDR1 _SFR_MEM8(0x002F) +- +-/* CPU - CPU Registers */ +-#define CPU_CCP _SFR_MEM8(0x0034) +-#define CPU_RAMPD _SFR_MEM8(0x0038) +-#define CPU_RAMPX _SFR_MEM8(0x0039) +-#define CPU_RAMPY _SFR_MEM8(0x003A) +-#define CPU_RAMPZ _SFR_MEM8(0x003B) +-#define CPU_EIND _SFR_MEM8(0x003C) +-#define CPU_SPL _SFR_MEM8(0x003D) +-#define CPU_SPH _SFR_MEM8(0x003E) +-#define CPU_SREG _SFR_MEM8(0x003F) +- +-/* CLK - Clock System */ +-#define CLK_CTRL _SFR_MEM8(0x0040) +-#define CLK_PSCTRL _SFR_MEM8(0x0041) +-#define CLK_LOCK _SFR_MEM8(0x0042) +-#define CLK_RTCCTRL _SFR_MEM8(0x0043) +-#define CLK_USBCTRL _SFR_MEM8(0x0044) +- +-/* SLEEP - Sleep Controller */ +-#define SLEEP_CTRL _SFR_MEM8(0x0048) +- +-/* OSC - Oscillator Control */ +-#define OSC_CTRL _SFR_MEM8(0x0050) +-#define OSC_STATUS _SFR_MEM8(0x0051) +-#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +-#define OSC_XOSCFAIL _SFR_MEM8(0x005F) +-#define OSC_RC32KCAL _SFR_MEM8(0x0054) +-#define OSC_PLLCTRL _SFR_MEM8(0x0055) +-#define OSC_DFLLCTRL _SFR_MEM8(0x0056) +- +-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +-#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +-#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +-#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +-#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +-#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +-#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) +- +-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +-#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +-#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +-#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +-#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +-#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +-#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) +- +-/* PR - Power Reduction */ +-#define PR_PRGEN _SFR_MEM8(0x0070) +-#define PR_PRPA _SFR_MEM8(0x0071) +-#define PR_PRPB _SFR_MEM8(0x0072) +-#define PR_PRPC _SFR_MEM8(0x0073) +-#define PR_PRPD _SFR_MEM8(0x0074) +-#define PR_PRPE _SFR_MEM8(0x0075) +-#define PR_PRPF _SFR_MEM8(0x0076) +- +-/* RST - Reset Controller */ +-#define RST_STATUS _SFR_MEM8(0x0078) +-#define RST_CTRL _SFR_MEM8(0x0079) +- +-/* WDT - Watch-Dog Timer */ +-#define WDT_CTRL _SFR_MEM8(0x0080) +-#define WDT_WINCTRL _SFR_MEM8(0x0081) +-#define WDT_STATUS _SFR_MEM8(0x0082) +- +-/* MCU - MCU Control */ +-#define MCU_DEVID0 _SFR_MEM8(0x0090) +-#define MCU_DEVID1 _SFR_MEM8(0x0091) +-#define MCU_DEVID2 _SFR_MEM8(0x0092) +-#define MCU_REVID _SFR_MEM8(0x0093) +-#define MCU_JTAGUID _SFR_MEM8(0x0094) +-#define MCU_MCUCR _SFR_MEM8(0x0096) +-#define MCU_ANAINIT _SFR_MEM8(0x0097) +-#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +-#define MCU_AWEXLOCK _SFR_MEM8(0x0099) +- +-/* PMIC - Programmable Interrupt Controller */ +-#define PMIC_STATUS _SFR_MEM8(0x00A0) +-#define PMIC_INTPRI _SFR_MEM8(0x00A1) +-#define PMIC_CTRL _SFR_MEM8(0x00A2) +- +-/* PORTCFG - Port Configuration */ +-#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +-#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +-#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +-#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +- +-/* AES - AES Crypto Module */ +-#define AES_CTRL _SFR_MEM8(0x00C0) +-#define AES_STATUS _SFR_MEM8(0x00C1) +-#define AES_STATE _SFR_MEM8(0x00C2) +-#define AES_KEY _SFR_MEM8(0x00C3) +-#define AES_INTCTRL _SFR_MEM8(0x00C4) +- +-/* CRC - CRC Module */ +-#define CRC_CTRL _SFR_MEM8(0x00D0) +-#define CRC_STATUS _SFR_MEM8(0x00D1) +-#define CRC_DATAIN _SFR_MEM8(0x00D3) +-#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) +-#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) +-#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) +-#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) +- +-/* DMA - DMA Controller */ +-#define DMA_CTRL _SFR_MEM8(0x0100) +-#define DMA_INTFLAGS _SFR_MEM8(0x0103) +-#define DMA_STATUS _SFR_MEM8(0x0104) +-#define DMA_TEMP _SFR_MEM16(0x0106) +-#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +-#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +-#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +-#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +-#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +-#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +-#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +-#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +-#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +-#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +-#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +-#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +-#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +-#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +-#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +-#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +-#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +-#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +-#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +-#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +-#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +-#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +-#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +-#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +-#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +-#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +-#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +-#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +-#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +-#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +-#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +-#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +-#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +-#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +-#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +-#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +-#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +-#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +-#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +-#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +-#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +-#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +-#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +-#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +-#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +-#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +-#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +-#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) +- +-/* EVSYS - Event System */ +-#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +-#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +-#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +-#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +-#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +-#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +-#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +-#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +-#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +-#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +-#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +-#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +-#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +-#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +-#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +-#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +-#define EVSYS_STROBE _SFR_MEM8(0x0190) +-#define EVSYS_DATA _SFR_MEM8(0x0191) +- +-/* NVM - Non Volatile Memory Controller */ +-#define NVM_ADDR0 _SFR_MEM8(0x01C0) +-#define NVM_ADDR1 _SFR_MEM8(0x01C1) +-#define NVM_ADDR2 _SFR_MEM8(0x01C2) +-#define NVM_DATA0 _SFR_MEM8(0x01C4) +-#define NVM_DATA1 _SFR_MEM8(0x01C5) +-#define NVM_DATA2 _SFR_MEM8(0x01C6) +-#define NVM_CMD _SFR_MEM8(0x01CA) +-#define NVM_CTRLA _SFR_MEM8(0x01CB) +-#define NVM_CTRLB _SFR_MEM8(0x01CC) +-#define NVM_INTCTRL _SFR_MEM8(0x01CD) +-#define NVM_STATUS _SFR_MEM8(0x01CF) +-#define NVM_LOCKBITS _SFR_MEM8(0x01D0) +- +-/* ADCA - Analog to Digital Converter A */ +-#define ADCA_CTRLA _SFR_MEM8(0x0200) +-#define ADCA_CTRLB _SFR_MEM8(0x0201) +-#define ADCA_REFCTRL _SFR_MEM8(0x0202) +-#define ADCA_EVCTRL _SFR_MEM8(0x0203) +-#define ADCA_PRESCALER _SFR_MEM8(0x0204) +-#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +-#define ADCA_TEMP _SFR_MEM8(0x0207) +-#define ADCA_CAL _SFR_MEM16(0x020C) +-#define ADCA_CH0RES _SFR_MEM16(0x0210) +-#define ADCA_CH1RES _SFR_MEM16(0x0212) +-#define ADCA_CH2RES _SFR_MEM16(0x0214) +-#define ADCA_CH3RES _SFR_MEM16(0x0216) +-#define ADCA_CMP _SFR_MEM16(0x0218) +-#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +-#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +-#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +-#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +-#define ADCA_CH0_RES _SFR_MEM16(0x0224) +-#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +-#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +-#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +-#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +-#define ADCA_CH1_RES _SFR_MEM16(0x022C) +-#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +-#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +-#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +-#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +-#define ADCA_CH2_RES _SFR_MEM16(0x0234) +-#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +-#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +-#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +-#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +-#define ADCA_CH3_RES _SFR_MEM16(0x023C) +- +-/* ADCB - Analog to Digital Converter B */ +-#define ADCB_CTRLA _SFR_MEM8(0x0240) +-#define ADCB_CTRLB _SFR_MEM8(0x0241) +-#define ADCB_REFCTRL _SFR_MEM8(0x0242) +-#define ADCB_EVCTRL _SFR_MEM8(0x0243) +-#define ADCB_PRESCALER _SFR_MEM8(0x0244) +-#define ADCB_INTFLAGS _SFR_MEM8(0x0246) +-#define ADCB_TEMP _SFR_MEM8(0x0247) +-#define ADCB_CAL _SFR_MEM16(0x024C) +-#define ADCB_CH0RES _SFR_MEM16(0x0250) +-#define ADCB_CH1RES _SFR_MEM16(0x0252) +-#define ADCB_CH2RES _SFR_MEM16(0x0254) +-#define ADCB_CH3RES _SFR_MEM16(0x0256) +-#define ADCB_CMP _SFR_MEM16(0x0258) +-#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) +-#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) +-#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) +-#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) +-#define ADCB_CH0_RES _SFR_MEM16(0x0264) +-#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) +-#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) +-#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) +-#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) +-#define ADCB_CH1_RES _SFR_MEM16(0x026C) +-#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) +-#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) +-#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) +-#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) +-#define ADCB_CH2_RES _SFR_MEM16(0x0274) +-#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) +-#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) +-#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) +-#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) +-#define ADCB_CH3_RES _SFR_MEM16(0x027C) +- +-/* DACA - Digital to Analog Converter A */ +-#define DACA_CTRLA _SFR_MEM8(0x0300) +-#define DACA_CTRLB _SFR_MEM8(0x0301) +-#define DACA_CTRLC _SFR_MEM8(0x0302) +-#define DACA_EVCTRL _SFR_MEM8(0x0303) +-#define DACA_TIMCTRL _SFR_MEM8(0x0304) +-#define DACA_STATUS _SFR_MEM8(0x0305) +-#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) +-#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) +-#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) +-#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) +-#define DACA_CH0DATA _SFR_MEM16(0x0318) +-#define DACA_CH1DATA _SFR_MEM16(0x031A) +- +-/* DACB - Digital to Analog Converter B */ +-#define DACB_CTRLA _SFR_MEM8(0x0320) +-#define DACB_CTRLB _SFR_MEM8(0x0321) +-#define DACB_CTRLC _SFR_MEM8(0x0322) +-#define DACB_EVCTRL _SFR_MEM8(0x0323) +-#define DACB_TIMCTRL _SFR_MEM8(0x0324) +-#define DACB_STATUS _SFR_MEM8(0x0325) +-#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) +-#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) +-#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) +-#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) +-#define DACB_CH0DATA _SFR_MEM16(0x0338) +-#define DACB_CH1DATA _SFR_MEM16(0x033A) +- +-/* ACA - Analog Comparator A */ +-#define ACA_AC0CTRL _SFR_MEM8(0x0380) +-#define ACA_AC1CTRL _SFR_MEM8(0x0381) +-#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +-#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +-#define ACA_CTRLA _SFR_MEM8(0x0384) +-#define ACA_CTRLB _SFR_MEM8(0x0385) +-#define ACA_WINCTRL _SFR_MEM8(0x0386) +-#define ACA_STATUS _SFR_MEM8(0x0387) +- +-/* ACB - Analog Comparator B */ +-#define ACB_AC0CTRL _SFR_MEM8(0x0390) +-#define ACB_AC1CTRL _SFR_MEM8(0x0391) +-#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +-#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +-#define ACB_CTRLA _SFR_MEM8(0x0394) +-#define ACB_CTRLB _SFR_MEM8(0x0395) +-#define ACB_WINCTRL _SFR_MEM8(0x0396) +-#define ACB_STATUS _SFR_MEM8(0x0397) +- +-/* RTC - Real-Time Counter */ +-#define RTC_CTRL _SFR_MEM8(0x0400) +-#define RTC_STATUS _SFR_MEM8(0x0401) +-#define RTC_INTCTRL _SFR_MEM8(0x0402) +-#define RTC_INTFLAGS _SFR_MEM8(0x0403) +-#define RTC_TEMP _SFR_MEM8(0x0404) +-#define RTC_CNT _SFR_MEM16(0x0408) +-#define RTC_PER _SFR_MEM16(0x040A) +-#define RTC_COMP _SFR_MEM16(0x040C) +- +-/* EBI - External Bus Interface */ +-#define EBI_CTRL _SFR_MEM8(0x0440) +-#define EBI_SDRAMCTRLA _SFR_MEM8(0x0441) +-#define EBI_REFRESH _SFR_MEM16(0x0444) +-#define EBI_INITDLY _SFR_MEM16(0x0446) +-#define EBI_SDRAMCTRLB _SFR_MEM8(0x0448) +-#define EBI_SDRAMCTRLC _SFR_MEM8(0x0449) +-#define EBI_CS0_CTRLA _SFR_MEM8(0x0450) +-#define EBI_CS0_CTRLB _SFR_MEM8(0x0451) +-#define EBI_CS0_BASEADDR _SFR_MEM16(0x0452) +-#define EBI_CS1_CTRLA _SFR_MEM8(0x0454) +-#define EBI_CS1_CTRLB _SFR_MEM8(0x0455) +-#define EBI_CS1_BASEADDR _SFR_MEM16(0x0456) +-#define EBI_CS2_CTRLA _SFR_MEM8(0x0458) +-#define EBI_CS2_CTRLB _SFR_MEM8(0x0459) +-#define EBI_CS2_BASEADDR _SFR_MEM16(0x045A) +-#define EBI_CS3_CTRLA _SFR_MEM8(0x045C) +-#define EBI_CS3_CTRLB _SFR_MEM8(0x045D) +-#define EBI_CS3_BASEADDR _SFR_MEM16(0x045E) +- +-/* TWIC - Two-Wire Interface C */ +-#define TWIC_CTRL _SFR_MEM8(0x0480) +-#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +-#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +-#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +-#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +-#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +-#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +-#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +-#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +-#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +-#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +-#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +-#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +-#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) +- +-/* TWID - Two-Wire Interface D */ +-#define TWID_CTRL _SFR_MEM8(0x0490) +-#define TWID_MASTER_CTRLA _SFR_MEM8(0x0491) +-#define TWID_MASTER_CTRLB _SFR_MEM8(0x0492) +-#define TWID_MASTER_CTRLC _SFR_MEM8(0x0493) +-#define TWID_MASTER_STATUS _SFR_MEM8(0x0494) +-#define TWID_MASTER_BAUD _SFR_MEM8(0x0495) +-#define TWID_MASTER_ADDR _SFR_MEM8(0x0496) +-#define TWID_MASTER_DATA _SFR_MEM8(0x0497) +-#define TWID_SLAVE_CTRLA _SFR_MEM8(0x0498) +-#define TWID_SLAVE_CTRLB _SFR_MEM8(0x0499) +-#define TWID_SLAVE_STATUS _SFR_MEM8(0x049A) +-#define TWID_SLAVE_ADDR _SFR_MEM8(0x049B) +-#define TWID_SLAVE_DATA _SFR_MEM8(0x049C) +-#define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D) +- +-/* TWIE - Two-Wire Interface E */ +-#define TWIE_CTRL _SFR_MEM8(0x04A0) +-#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +-#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +-#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +-#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +-#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +-#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +-#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +-#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +-#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +-#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +-#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +-#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +-#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) +- +-/* TWIF - Two-Wire Interface F */ +-#define TWIF_CTRL _SFR_MEM8(0x04B0) +-#define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1) +-#define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2) +-#define TWIF_MASTER_CTRLC _SFR_MEM8(0x04B3) +-#define TWIF_MASTER_STATUS _SFR_MEM8(0x04B4) +-#define TWIF_MASTER_BAUD _SFR_MEM8(0x04B5) +-#define TWIF_MASTER_ADDR _SFR_MEM8(0x04B6) +-#define TWIF_MASTER_DATA _SFR_MEM8(0x04B7) +-#define TWIF_SLAVE_CTRLA _SFR_MEM8(0x04B8) +-#define TWIF_SLAVE_CTRLB _SFR_MEM8(0x04B9) +-#define TWIF_SLAVE_STATUS _SFR_MEM8(0x04BA) +-#define TWIF_SLAVE_ADDR _SFR_MEM8(0x04BB) +-#define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC) +-#define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD) +- +-/* USB - Universal Serial Bus Module */ +-#define USB_CTRLA _SFR_MEM8(0x04C0) +-#define USB_CTRLB _SFR_MEM8(0x04C1) +-#define USB_STATUS _SFR_MEM8(0x04C2) +-#define USB_ADDR _SFR_MEM8(0x04C3) +-#define USB_FIFOWP _SFR_MEM8(0x04C4) +-#define USB_FIFORP _SFR_MEM8(0x04C5) +-#define USB_EPPTR _SFR_MEM16(0x04C6) +-#define USB_INTCTRLA _SFR_MEM8(0x04C8) +-#define USB_INTCTRLB _SFR_MEM8(0x04C9) +-#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) +-#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) +-#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) +-#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) +-#define USB_CAL0 _SFR_MEM8(0x04FA) +-#define USB_CAL1 _SFR_MEM8(0x04FB) +- +-/* PORTA - Port A */ +-#define PORTA_DIR _SFR_MEM8(0x0600) +-#define PORTA_DIRSET _SFR_MEM8(0x0601) +-#define PORTA_DIRCLR _SFR_MEM8(0x0602) +-#define PORTA_DIRTGL _SFR_MEM8(0x0603) +-#define PORTA_OUT _SFR_MEM8(0x0604) +-#define PORTA_OUTSET _SFR_MEM8(0x0605) +-#define PORTA_OUTCLR _SFR_MEM8(0x0606) +-#define PORTA_OUTTGL _SFR_MEM8(0x0607) +-#define PORTA_IN _SFR_MEM8(0x0608) +-#define PORTA_INTCTRL _SFR_MEM8(0x0609) +-#define PORTA_INT0MASK _SFR_MEM8(0x060A) +-#define PORTA_INT1MASK _SFR_MEM8(0x060B) +-#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +-#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +-#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +-#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +-#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +-#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +-#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +-#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +-#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) +- +-/* PORTB - Port B */ +-#define PORTB_DIR _SFR_MEM8(0x0620) +-#define PORTB_DIRSET _SFR_MEM8(0x0621) +-#define PORTB_DIRCLR _SFR_MEM8(0x0622) +-#define PORTB_DIRTGL _SFR_MEM8(0x0623) +-#define PORTB_OUT _SFR_MEM8(0x0624) +-#define PORTB_OUTSET _SFR_MEM8(0x0625) +-#define PORTB_OUTCLR _SFR_MEM8(0x0626) +-#define PORTB_OUTTGL _SFR_MEM8(0x0627) +-#define PORTB_IN _SFR_MEM8(0x0628) +-#define PORTB_INTCTRL _SFR_MEM8(0x0629) +-#define PORTB_INT0MASK _SFR_MEM8(0x062A) +-#define PORTB_INT1MASK _SFR_MEM8(0x062B) +-#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +-#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +-#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +-#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +-#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +-#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +-#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +-#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +-#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) +- +-/* PORTC - Port C */ +-#define PORTC_DIR _SFR_MEM8(0x0640) +-#define PORTC_DIRSET _SFR_MEM8(0x0641) +-#define PORTC_DIRCLR _SFR_MEM8(0x0642) +-#define PORTC_DIRTGL _SFR_MEM8(0x0643) +-#define PORTC_OUT _SFR_MEM8(0x0644) +-#define PORTC_OUTSET _SFR_MEM8(0x0645) +-#define PORTC_OUTCLR _SFR_MEM8(0x0646) +-#define PORTC_OUTTGL _SFR_MEM8(0x0647) +-#define PORTC_IN _SFR_MEM8(0x0648) +-#define PORTC_INTCTRL _SFR_MEM8(0x0649) +-#define PORTC_INT0MASK _SFR_MEM8(0x064A) +-#define PORTC_INT1MASK _SFR_MEM8(0x064B) +-#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +-#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +-#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +-#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +-#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +-#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +-#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +-#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +-#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) +- +-/* PORTD - Port D */ +-#define PORTD_DIR _SFR_MEM8(0x0660) +-#define PORTD_DIRSET _SFR_MEM8(0x0661) +-#define PORTD_DIRCLR _SFR_MEM8(0x0662) +-#define PORTD_DIRTGL _SFR_MEM8(0x0663) +-#define PORTD_OUT _SFR_MEM8(0x0664) +-#define PORTD_OUTSET _SFR_MEM8(0x0665) +-#define PORTD_OUTCLR _SFR_MEM8(0x0666) +-#define PORTD_OUTTGL _SFR_MEM8(0x0667) +-#define PORTD_IN _SFR_MEM8(0x0668) +-#define PORTD_INTCTRL _SFR_MEM8(0x0669) +-#define PORTD_INT0MASK _SFR_MEM8(0x066A) +-#define PORTD_INT1MASK _SFR_MEM8(0x066B) +-#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +-#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +-#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +-#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +-#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +-#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +-#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +-#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +-#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) +- +-/* PORTE - Port E */ +-#define PORTE_DIR _SFR_MEM8(0x0680) +-#define PORTE_DIRSET _SFR_MEM8(0x0681) +-#define PORTE_DIRCLR _SFR_MEM8(0x0682) +-#define PORTE_DIRTGL _SFR_MEM8(0x0683) +-#define PORTE_OUT _SFR_MEM8(0x0684) +-#define PORTE_OUTSET _SFR_MEM8(0x0685) +-#define PORTE_OUTCLR _SFR_MEM8(0x0686) +-#define PORTE_OUTTGL _SFR_MEM8(0x0687) +-#define PORTE_IN _SFR_MEM8(0x0688) +-#define PORTE_INTCTRL _SFR_MEM8(0x0689) +-#define PORTE_INT0MASK _SFR_MEM8(0x068A) +-#define PORTE_INT1MASK _SFR_MEM8(0x068B) +-#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +-#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +-#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +-#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +-#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +-#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +-#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +-#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +-#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) +- +-/* PORTF - Port F */ +-#define PORTF_DIR _SFR_MEM8(0x06A0) +-#define PORTF_DIRSET _SFR_MEM8(0x06A1) +-#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +-#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +-#define PORTF_OUT _SFR_MEM8(0x06A4) +-#define PORTF_OUTSET _SFR_MEM8(0x06A5) +-#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +-#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +-#define PORTF_IN _SFR_MEM8(0x06A8) +-#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +-#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +-#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +-#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +-#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +-#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +-#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +-#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +-#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +-#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +-#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +-#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) +- +-/* PORTH - Port H */ +-#define PORTH_DIR _SFR_MEM8(0x06E0) +-#define PORTH_DIRSET _SFR_MEM8(0x06E1) +-#define PORTH_DIRCLR _SFR_MEM8(0x06E2) +-#define PORTH_DIRTGL _SFR_MEM8(0x06E3) +-#define PORTH_OUT _SFR_MEM8(0x06E4) +-#define PORTH_OUTSET _SFR_MEM8(0x06E5) +-#define PORTH_OUTCLR _SFR_MEM8(0x06E6) +-#define PORTH_OUTTGL _SFR_MEM8(0x06E7) +-#define PORTH_IN _SFR_MEM8(0x06E8) +-#define PORTH_INTCTRL _SFR_MEM8(0x06E9) +-#define PORTH_INT0MASK _SFR_MEM8(0x06EA) +-#define PORTH_INT1MASK _SFR_MEM8(0x06EB) +-#define PORTH_INTFLAGS _SFR_MEM8(0x06EC) +-#define PORTH_PIN0CTRL _SFR_MEM8(0x06F0) +-#define PORTH_PIN1CTRL _SFR_MEM8(0x06F1) +-#define PORTH_PIN2CTRL _SFR_MEM8(0x06F2) +-#define PORTH_PIN3CTRL _SFR_MEM8(0x06F3) +-#define PORTH_PIN4CTRL _SFR_MEM8(0x06F4) +-#define PORTH_PIN5CTRL _SFR_MEM8(0x06F5) +-#define PORTH_PIN6CTRL _SFR_MEM8(0x06F6) +-#define PORTH_PIN7CTRL _SFR_MEM8(0x06F7) +- +-/* PORTJ - Port J */ +-#define PORTJ_DIR _SFR_MEM8(0x0700) +-#define PORTJ_DIRSET _SFR_MEM8(0x0701) +-#define PORTJ_DIRCLR _SFR_MEM8(0x0702) +-#define PORTJ_DIRTGL _SFR_MEM8(0x0703) +-#define PORTJ_OUT _SFR_MEM8(0x0704) +-#define PORTJ_OUTSET _SFR_MEM8(0x0705) +-#define PORTJ_OUTCLR _SFR_MEM8(0x0706) +-#define PORTJ_OUTTGL _SFR_MEM8(0x0707) +-#define PORTJ_IN _SFR_MEM8(0x0708) +-#define PORTJ_INTCTRL _SFR_MEM8(0x0709) +-#define PORTJ_INT0MASK _SFR_MEM8(0x070A) +-#define PORTJ_INT1MASK _SFR_MEM8(0x070B) +-#define PORTJ_INTFLAGS _SFR_MEM8(0x070C) +-#define PORTJ_PIN0CTRL _SFR_MEM8(0x0710) +-#define PORTJ_PIN1CTRL _SFR_MEM8(0x0711) +-#define PORTJ_PIN2CTRL _SFR_MEM8(0x0712) +-#define PORTJ_PIN3CTRL _SFR_MEM8(0x0713) +-#define PORTJ_PIN4CTRL _SFR_MEM8(0x0714) +-#define PORTJ_PIN5CTRL _SFR_MEM8(0x0715) +-#define PORTJ_PIN6CTRL _SFR_MEM8(0x0716) +-#define PORTJ_PIN7CTRL _SFR_MEM8(0x0717) +- +-/* PORTK - Port K */ +-#define PORTK_DIR _SFR_MEM8(0x0720) +-#define PORTK_DIRSET _SFR_MEM8(0x0721) +-#define PORTK_DIRCLR _SFR_MEM8(0x0722) +-#define PORTK_DIRTGL _SFR_MEM8(0x0723) +-#define PORTK_OUT _SFR_MEM8(0x0724) +-#define PORTK_OUTSET _SFR_MEM8(0x0725) +-#define PORTK_OUTCLR _SFR_MEM8(0x0726) +-#define PORTK_OUTTGL _SFR_MEM8(0x0727) +-#define PORTK_IN _SFR_MEM8(0x0728) +-#define PORTK_INTCTRL _SFR_MEM8(0x0729) +-#define PORTK_INT0MASK _SFR_MEM8(0x072A) +-#define PORTK_INT1MASK _SFR_MEM8(0x072B) +-#define PORTK_INTFLAGS _SFR_MEM8(0x072C) +-#define PORTK_PIN0CTRL _SFR_MEM8(0x0730) +-#define PORTK_PIN1CTRL _SFR_MEM8(0x0731) +-#define PORTK_PIN2CTRL _SFR_MEM8(0x0732) +-#define PORTK_PIN3CTRL _SFR_MEM8(0x0733) +-#define PORTK_PIN4CTRL _SFR_MEM8(0x0734) +-#define PORTK_PIN5CTRL _SFR_MEM8(0x0735) +-#define PORTK_PIN6CTRL _SFR_MEM8(0x0736) +-#define PORTK_PIN7CTRL _SFR_MEM8(0x0737) +- +-/* PORTQ - Port Q */ +-#define PORTQ_DIR _SFR_MEM8(0x07C0) +-#define PORTQ_DIRSET _SFR_MEM8(0x07C1) +-#define PORTQ_DIRCLR _SFR_MEM8(0x07C2) +-#define PORTQ_DIRTGL _SFR_MEM8(0x07C3) +-#define PORTQ_OUT _SFR_MEM8(0x07C4) +-#define PORTQ_OUTSET _SFR_MEM8(0x07C5) +-#define PORTQ_OUTCLR _SFR_MEM8(0x07C6) +-#define PORTQ_OUTTGL _SFR_MEM8(0x07C7) +-#define PORTQ_IN _SFR_MEM8(0x07C8) +-#define PORTQ_INTCTRL _SFR_MEM8(0x07C9) +-#define PORTQ_INT0MASK _SFR_MEM8(0x07CA) +-#define PORTQ_INT1MASK _SFR_MEM8(0x07CB) +-#define PORTQ_INTFLAGS _SFR_MEM8(0x07CC) +-#define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0) +-#define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1) +-#define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2) +-#define PORTQ_PIN3CTRL _SFR_MEM8(0x07D3) +-#define PORTQ_PIN4CTRL _SFR_MEM8(0x07D4) +-#define PORTQ_PIN5CTRL _SFR_MEM8(0x07D5) +-#define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6) +-#define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7) +- +-/* PORTR - Port R */ +-#define PORTR_DIR _SFR_MEM8(0x07E0) +-#define PORTR_DIRSET _SFR_MEM8(0x07E1) +-#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +-#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +-#define PORTR_OUT _SFR_MEM8(0x07E4) +-#define PORTR_OUTSET _SFR_MEM8(0x07E5) +-#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +-#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +-#define PORTR_IN _SFR_MEM8(0x07E8) +-#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +-#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +-#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +-#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +-#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +-#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +-#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +-#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +-#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +-#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +-#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +-#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) +- +-/* TCC0 - Timer/Counter C0 */ +-#define TCC0_CTRLA _SFR_MEM8(0x0800) +-#define TCC0_CTRLB _SFR_MEM8(0x0801) +-#define TCC0_CTRLC _SFR_MEM8(0x0802) +-#define TCC0_CTRLD _SFR_MEM8(0x0803) +-#define TCC0_CTRLE _SFR_MEM8(0x0804) +-#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +-#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +-#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +-#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +-#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +-#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +-#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +-#define TCC0_TEMP _SFR_MEM8(0x080F) +-#define TCC0_CNT _SFR_MEM16(0x0820) +-#define TCC0_PER _SFR_MEM16(0x0826) +-#define TCC0_CCA _SFR_MEM16(0x0828) +-#define TCC0_CCB _SFR_MEM16(0x082A) +-#define TCC0_CCC _SFR_MEM16(0x082C) +-#define TCC0_CCD _SFR_MEM16(0x082E) +-#define TCC0_PERBUF _SFR_MEM16(0x0836) +-#define TCC0_CCABUF _SFR_MEM16(0x0838) +-#define TCC0_CCBBUF _SFR_MEM16(0x083A) +-#define TCC0_CCCBUF _SFR_MEM16(0x083C) +-#define TCC0_CCDBUF _SFR_MEM16(0x083E) +- +-/* TCC1 - Timer/Counter C1 */ +-#define TCC1_CTRLA _SFR_MEM8(0x0840) +-#define TCC1_CTRLB _SFR_MEM8(0x0841) +-#define TCC1_CTRLC _SFR_MEM8(0x0842) +-#define TCC1_CTRLD _SFR_MEM8(0x0843) +-#define TCC1_CTRLE _SFR_MEM8(0x0844) +-#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +-#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +-#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +-#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +-#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +-#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +-#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +-#define TCC1_TEMP _SFR_MEM8(0x084F) +-#define TCC1_CNT _SFR_MEM16(0x0860) +-#define TCC1_PER _SFR_MEM16(0x0866) +-#define TCC1_CCA _SFR_MEM16(0x0868) +-#define TCC1_CCB _SFR_MEM16(0x086A) +-#define TCC1_PERBUF _SFR_MEM16(0x0876) +-#define TCC1_CCABUF _SFR_MEM16(0x0878) +-#define TCC1_CCBBUF _SFR_MEM16(0x087A) +- +-/* AWEXC - Advanced Waveform Extension C */ +-#define AWEXC_CTRL _SFR_MEM8(0x0880) +-#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +-#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +-#define AWEXC_STATUS _SFR_MEM8(0x0884) +-#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +-#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +-#define AWEXC_DTLS _SFR_MEM8(0x0888) +-#define AWEXC_DTHS _SFR_MEM8(0x0889) +-#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +-#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +-#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) +- +-/* HIRESC - High-Resolution Extension C */ +-#define HIRESC_CTRLA _SFR_MEM8(0x0890) +- +-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +-#define USARTC0_DATA _SFR_MEM8(0x08A0) +-#define USARTC0_STATUS _SFR_MEM8(0x08A1) +-#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +-#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +-#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +-#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +-#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) +- +-/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ +-#define USARTC1_DATA _SFR_MEM8(0x08B0) +-#define USARTC1_STATUS _SFR_MEM8(0x08B1) +-#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +-#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +-#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +-#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +-#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) +- +-/* SPIC - Serial Peripheral Interface C */ +-#define SPIC_CTRL _SFR_MEM8(0x08C0) +-#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +-#define SPIC_STATUS _SFR_MEM8(0x08C2) +-#define SPIC_DATA _SFR_MEM8(0x08C3) +- +-/* IRCOM - IR Communication Module */ +-#define IRCOM_CTRL _SFR_MEM8(0x08F8) +-#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +-#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) +- +-/* TCD0 - Timer/Counter D0 */ +-#define TCD0_CTRLA _SFR_MEM8(0x0900) +-#define TCD0_CTRLB _SFR_MEM8(0x0901) +-#define TCD0_CTRLC _SFR_MEM8(0x0902) +-#define TCD0_CTRLD _SFR_MEM8(0x0903) +-#define TCD0_CTRLE _SFR_MEM8(0x0904) +-#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +-#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +-#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +-#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +-#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +-#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +-#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +-#define TCD0_TEMP _SFR_MEM8(0x090F) +-#define TCD0_CNT _SFR_MEM16(0x0920) +-#define TCD0_PER _SFR_MEM16(0x0926) +-#define TCD0_CCA _SFR_MEM16(0x0928) +-#define TCD0_CCB _SFR_MEM16(0x092A) +-#define TCD0_CCC _SFR_MEM16(0x092C) +-#define TCD0_CCD _SFR_MEM16(0x092E) +-#define TCD0_PERBUF _SFR_MEM16(0x0936) +-#define TCD0_CCABUF _SFR_MEM16(0x0938) +-#define TCD0_CCBBUF _SFR_MEM16(0x093A) +-#define TCD0_CCCBUF _SFR_MEM16(0x093C) +-#define TCD0_CCDBUF _SFR_MEM16(0x093E) +- +-/* TCD1 - Timer/Counter D1 */ +-#define TCD1_CTRLA _SFR_MEM8(0x0940) +-#define TCD1_CTRLB _SFR_MEM8(0x0941) +-#define TCD1_CTRLC _SFR_MEM8(0x0942) +-#define TCD1_CTRLD _SFR_MEM8(0x0943) +-#define TCD1_CTRLE _SFR_MEM8(0x0944) +-#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +-#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +-#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +-#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +-#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +-#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +-#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +-#define TCD1_TEMP _SFR_MEM8(0x094F) +-#define TCD1_CNT _SFR_MEM16(0x0960) +-#define TCD1_PER _SFR_MEM16(0x0966) +-#define TCD1_CCA _SFR_MEM16(0x0968) +-#define TCD1_CCB _SFR_MEM16(0x096A) +-#define TCD1_PERBUF _SFR_MEM16(0x0976) +-#define TCD1_CCABUF _SFR_MEM16(0x0978) +-#define TCD1_CCBBUF _SFR_MEM16(0x097A) +- +-/* HIRESD - High-Resolution Extension D */ +-#define HIRESD_CTRLA _SFR_MEM8(0x0990) +- +-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +-#define USARTD0_DATA _SFR_MEM8(0x09A0) +-#define USARTD0_STATUS _SFR_MEM8(0x09A1) +-#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +-#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +-#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +-#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +-#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) +- +-/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ +-#define USARTD1_DATA _SFR_MEM8(0x09B0) +-#define USARTD1_STATUS _SFR_MEM8(0x09B1) +-#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +-#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +-#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +-#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +-#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) +- +-/* SPID - Serial Peripheral Interface D */ +-#define SPID_CTRL _SFR_MEM8(0x09C0) +-#define SPID_INTCTRL _SFR_MEM8(0x09C1) +-#define SPID_STATUS _SFR_MEM8(0x09C2) +-#define SPID_DATA _SFR_MEM8(0x09C3) +- +-/* TCE0 - Timer/Counter E0 */ +-#define TCE0_CTRLA _SFR_MEM8(0x0A00) +-#define TCE0_CTRLB _SFR_MEM8(0x0A01) +-#define TCE0_CTRLC _SFR_MEM8(0x0A02) +-#define TCE0_CTRLD _SFR_MEM8(0x0A03) +-#define TCE0_CTRLE _SFR_MEM8(0x0A04) +-#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +-#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +-#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +-#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +-#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +-#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +-#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +-#define TCE0_TEMP _SFR_MEM8(0x0A0F) +-#define TCE0_CNT _SFR_MEM16(0x0A20) +-#define TCE0_PER _SFR_MEM16(0x0A26) +-#define TCE0_CCA _SFR_MEM16(0x0A28) +-#define TCE0_CCB _SFR_MEM16(0x0A2A) +-#define TCE0_CCC _SFR_MEM16(0x0A2C) +-#define TCE0_CCD _SFR_MEM16(0x0A2E) +-#define TCE0_PERBUF _SFR_MEM16(0x0A36) +-#define TCE0_CCABUF _SFR_MEM16(0x0A38) +-#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +-#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +-#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) +- +-/* TCE1 - Timer/Counter E1 */ +-#define TCE1_CTRLA _SFR_MEM8(0x0A40) +-#define TCE1_CTRLB _SFR_MEM8(0x0A41) +-#define TCE1_CTRLC _SFR_MEM8(0x0A42) +-#define TCE1_CTRLD _SFR_MEM8(0x0A43) +-#define TCE1_CTRLE _SFR_MEM8(0x0A44) +-#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) +-#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) +-#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) +-#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) +-#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) +-#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) +-#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) +-#define TCE1_TEMP _SFR_MEM8(0x0A4F) +-#define TCE1_CNT _SFR_MEM16(0x0A60) +-#define TCE1_PER _SFR_MEM16(0x0A66) +-#define TCE1_CCA _SFR_MEM16(0x0A68) +-#define TCE1_CCB _SFR_MEM16(0x0A6A) +-#define TCE1_PERBUF _SFR_MEM16(0x0A76) +-#define TCE1_CCABUF _SFR_MEM16(0x0A78) +-#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) +- +-/* AWEXE - Advanced Waveform Extension E */ +-#define AWEXE_CTRL _SFR_MEM8(0x0A80) +-#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +-#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +-#define AWEXE_STATUS _SFR_MEM8(0x0A84) +-#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +-#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +-#define AWEXE_DTLS _SFR_MEM8(0x0A88) +-#define AWEXE_DTHS _SFR_MEM8(0x0A89) +-#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +-#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +-#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) +- +-/* HIRESE - High-Resolution Extension E */ +-#define HIRESE_CTRLA _SFR_MEM8(0x0A90) +- +-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +-#define USARTE0_DATA _SFR_MEM8(0x0AA0) +-#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +-#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +-#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +-#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +-#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +-#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) +- +-/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ +-#define USARTE1_DATA _SFR_MEM8(0x0AB0) +-#define USARTE1_STATUS _SFR_MEM8(0x0AB1) +-#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) +-#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) +-#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) +-#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) +-#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) +- +-/* SPIE - Serial Peripheral Interface E */ +-#define SPIE_CTRL _SFR_MEM8(0x0AC0) +-#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +-#define SPIE_STATUS _SFR_MEM8(0x0AC2) +-#define SPIE_DATA _SFR_MEM8(0x0AC3) +- +-/* TCF0 - Timer/Counter F0 */ +-#define TCF0_CTRLA _SFR_MEM8(0x0B00) +-#define TCF0_CTRLB _SFR_MEM8(0x0B01) +-#define TCF0_CTRLC _SFR_MEM8(0x0B02) +-#define TCF0_CTRLD _SFR_MEM8(0x0B03) +-#define TCF0_CTRLE _SFR_MEM8(0x0B04) +-#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +-#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +-#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +-#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +-#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +-#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +-#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +-#define TCF0_TEMP _SFR_MEM8(0x0B0F) +-#define TCF0_CNT _SFR_MEM16(0x0B20) +-#define TCF0_PER _SFR_MEM16(0x0B26) +-#define TCF0_CCA _SFR_MEM16(0x0B28) +-#define TCF0_CCB _SFR_MEM16(0x0B2A) +-#define TCF0_CCC _SFR_MEM16(0x0B2C) +-#define TCF0_CCD _SFR_MEM16(0x0B2E) +-#define TCF0_PERBUF _SFR_MEM16(0x0B36) +-#define TCF0_CCABUF _SFR_MEM16(0x0B38) +-#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +-#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +-#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) +- +-/* TCF1 - Timer/Counter F1 */ +-#define TCF1_CTRLA _SFR_MEM8(0x0B40) +-#define TCF1_CTRLB _SFR_MEM8(0x0B41) +-#define TCF1_CTRLC _SFR_MEM8(0x0B42) +-#define TCF1_CTRLD _SFR_MEM8(0x0B43) +-#define TCF1_CTRLE _SFR_MEM8(0x0B44) +-#define TCF1_INTCTRLA _SFR_MEM8(0x0B46) +-#define TCF1_INTCTRLB _SFR_MEM8(0x0B47) +-#define TCF1_CTRLFCLR _SFR_MEM8(0x0B48) +-#define TCF1_CTRLFSET _SFR_MEM8(0x0B49) +-#define TCF1_CTRLGCLR _SFR_MEM8(0x0B4A) +-#define TCF1_CTRLGSET _SFR_MEM8(0x0B4B) +-#define TCF1_INTFLAGS _SFR_MEM8(0x0B4C) +-#define TCF1_TEMP _SFR_MEM8(0x0B4F) +-#define TCF1_CNT _SFR_MEM16(0x0B60) +-#define TCF1_PER _SFR_MEM16(0x0B66) +-#define TCF1_CCA _SFR_MEM16(0x0B68) +-#define TCF1_CCB _SFR_MEM16(0x0B6A) +-#define TCF1_PERBUF _SFR_MEM16(0x0B76) +-#define TCF1_CCABUF _SFR_MEM16(0x0B78) +-#define TCF1_CCBBUF _SFR_MEM16(0x0B7A) +- +-/* HIRESF - High-Resolution Extension F */ +-#define HIRESF_CTRLA _SFR_MEM8(0x0B90) +- +-/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ +-#define USARTF0_DATA _SFR_MEM8(0x0BA0) +-#define USARTF0_STATUS _SFR_MEM8(0x0BA1) +-#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) +-#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) +-#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) +-#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) +-#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) +- +-/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ +-#define USARTF1_DATA _SFR_MEM8(0x0BB0) +-#define USARTF1_STATUS _SFR_MEM8(0x0BB1) +-#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) +-#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) +-#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) +-#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) +-#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) +- +-/* SPIF - Serial Peripheral Interface F */ +-#define SPIF_CTRL _SFR_MEM8(0x0BC0) +-#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) +-#define SPIF_STATUS _SFR_MEM8(0x0BC2) +-#define SPIF_DATA _SFR_MEM8(0x0BC3) +- +- +- +-/*================== Bitfield Definitions ================== */ +- +-/* VPORT - Virtual Ports */ +-/* VPORT.INTFLAGS bit masks and bit positions */ +-#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* XOCD - On-Chip Debug System */ -/* OCD.OCDR1 bit masks and bit positions */ -#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ -#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ - -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ - - /* CPU - CPU */ - /* CPU.CCP bit masks and bit positions */ -@@ -3790,7 +4408,6 @@ IO Module Instances. Mapped to memory. - #define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ - #define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - - - /* CPU.SREG bit masks and bit positions */ - #define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ - #define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -@@ -3816,7 +4433,6 @@ IO Module Instances. Mapped to memory. - #define CPU_C_bm 0x01 /* Carry Flag bit mask. */ - #define CPU_C_bp 0 /* Carry Flag bit position. */ - - - /* CLK - Clock System */ - /* CLK.CTRL bit masks and bit positions */ - #define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -@@ -3828,7 +4444,6 @@ IO Module Instances. Mapped to memory. - #define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ - #define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ - +-/* CPU - CPU */ +-/* CPU.CCP bit masks and bit positions */ +-#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +-#define CPU_CCP_gp 0 /* CCP signature group position. */ +-#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +-#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +-#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +-#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +-#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +-#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +-#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +-#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +-#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +-#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +-#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +-#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +-#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +-#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +-#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +-#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ - - /* CLK.PSCTRL bit masks and bit positions */ - #define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ - #define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -@@ -3850,12 +4465,10 @@ IO Module Instances. Mapped to memory. - #define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ - #define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ - - - /* CLK.LOCK bit masks and bit positions */ - #define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ - #define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ - +-/* CPU.SREG bit masks and bit positions */ +-#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +-#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ - - /* CLK.RTCCTRL bit masks and bit positions */ - #define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ - #define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -@@ -3869,7 +4482,6 @@ IO Module Instances. Mapped to memory. - #define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ - #define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ - +-#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +-#define CPU_T_bp 6 /* Transfer Bit bit position. */ +- +-#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +-#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +- +-#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +-#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +- +-#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +-#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +- +-#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +-#define CPU_N_bp 2 /* Negative Flag bit position. */ +- +-#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +-#define CPU_Z_bp 1 /* Zero Flag bit position. */ +- +-#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +-#define CPU_C_bp 0 /* Carry Flag bit position. */ +- +- +-/* CLK - Clock System */ +-/* CLK.CTRL bit masks and bit positions */ +-#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +-#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +-#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +-#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +-#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +-#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +-#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +-#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ +- +- +-/* CLK.PSCTRL bit masks and bit positions */ +-#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +-#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +-#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +-#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +-#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +-#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +-#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +-#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +-#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +-#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +-#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +-#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ +- +-#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +-#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +-#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +-#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +-#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +-#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ +- +- +-/* CLK.LOCK bit masks and bit positions */ +-#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +-#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ +- +- +-/* CLK.RTCCTRL bit masks and bit positions */ +-#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +-#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +-#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +-#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +-#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +-#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +-#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +-#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ +- +-#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ +-#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ +- +- +-/* CLK.USBCTRL bit masks and bit positions */ +-#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ +-#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ +-#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ +-#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ +-#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ +-#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ +-#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ +-#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ +- +-#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ +-#define CLK_USBSRC_gp 1 /* Clock Source group position. */ +-#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +-#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ +-#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +-#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - - /* CLK.USBCTRL bit masks and bit positions */ - #define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ - #define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -@@ -3887,9 +4499,8 @@ IO Module Instances. Mapped to memory. - #define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ - #define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ - -#define CLK_USBEN_bm 0x01 /* Clock Source Enable bit mask. */ -#define CLK_USBEN_bp 0 /* Clock Source Enable bit position. */ - -+#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ - - /* PR.PRGEN bit masks and bit positions */ - #define PR_USB_bm 0x40 /* USB bit mask. */ -@@ -3910,7 +4521,6 @@ IO Module Instances. Mapped to memory. - #define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ - #define PR_DMA_bp 0 /* DMA-Controller bit position. */ - - - /* PR.PRPA bit masks and bit positions */ - #define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ - #define PR_DAC_bp 2 /* Port A DAC bit position. */ -@@ -3921,17 +4531,15 @@ IO Module Instances. Mapped to memory. - #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ - #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - +-/* PR.PRGEN bit masks and bit positions */ +-#define PR_USB_bm 0x40 /* USB bit mask. */ +-#define PR_USB_bp 6 /* USB bit position. */ - - /* PR.PRPB bit masks and bit positions */ +-#define PR_AES_bm 0x10 /* AES bit mask. */ +-#define PR_AES_bp 4 /* AES bit position. */ +- +-#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +-#define PR_EBI_bp 3 /* External Bus Interface bit position. */ +- +-#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +-#define PR_RTC_bp 2 /* Real-time Counter bit position. */ +- +-#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +-#define PR_EVSYS_bp 1 /* Event System bit position. */ +- +-#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +-#define PR_DMA_bp 0 /* DMA-Controller bit position. */ +- +- +-/* PR.PRPA bit masks and bit positions */ +-#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +-#define PR_DAC_bp 2 /* Port A DAC bit position. */ +- +-#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +-#define PR_ADC_bp 1 /* Port A ADC bit position. */ +- +-#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +-#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ +- +- +-/* PR.PRPB bit masks and bit positions */ -/* PR_DAC_bm Predefined. */ -/* PR_DAC_bp Predefined. */ - -/* PR_ADC_bm Predefined. */ -/* PR_ADC_bp Predefined. */ -+/* PR_DAC Predefined. */ -+/* PR_DAC Predefined. */ - +- -/* PR_AC_bm Predefined. */ -/* PR_AC_bp Predefined. */ -+/* PR_ADC Predefined. */ -+/* PR_ADC Predefined. */ - -+/* PR_AC Predefined. */ -+/* PR_AC Predefined. */ - - /* PR.PRPC bit masks and bit positions */ - #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -@@ -3955,75 +4563,71 @@ IO Module Instances. Mapped to memory. - #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ - #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - - - /* PR.PRPD bit masks and bit positions */ --/* PR_TWI_bm Predefined. */ --/* PR_TWI_bp Predefined. */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ - --/* PR_USART1_bm Predefined. */ --/* PR_USART1_bp Predefined. */ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ - --/* PR_USART0_bm Predefined. */ --/* PR_USART0_bp Predefined. */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ - --/* PR_SPI_bm Predefined. */ --/* PR_SPI_bp Predefined. */ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ - --/* PR_HIRES_bm Predefined. */ --/* PR_HIRES_bp Predefined. */ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ - --/* PR_TC1_bm Predefined. */ --/* PR_TC1_bp Predefined. */ - --/* PR_TC0_bm Predefined. */ --/* PR_TC0_bp Predefined. */ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ - -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ - - /* PR.PRPE bit masks and bit positions */ +-/* PR.PRPC bit masks and bit positions */ +-#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +-#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ +- +-#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +-#define PR_USART1_bp 5 /* Port C USART1 bit position. */ +- +-#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +-#define PR_USART0_bp 4 /* Port C USART0 bit position. */ +- +-#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +-#define PR_SPI_bp 3 /* Port C SPI bit position. */ +- +-#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +-#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ +- +-#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +-#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ +- +-#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +-#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ +- +- +-/* PR.PRPD bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ - +- -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ - +- -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ - +- -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ - +- -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ - +- -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ - -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ - - /* PR.PRPF bit masks and bit positions */ +- +- +-/* PR.PRPE bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ - +- -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ - +- -/* PR_USART0_bm Predefined. */ -/* PR_USART0_bp Predefined. */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ - +- -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ - +- -/* PR_HIRES_bm Predefined. */ -/* PR_HIRES_bp Predefined. */ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ - +- -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - -/* PR_TC0_bm Predefined. */ -/* PR_TC0_bp Predefined. */ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ - -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ - - /* SLEEP - Sleep Controller */ - /* SLEEP.CTRL bit masks and bit positions */ -@@ -4039,7 +4643,6 @@ IO Module Instances. Mapped to memory. - #define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ - #define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ - - - /* OSC - Oscillator */ - /* OSC.CTRL bit masks and bit positions */ - #define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -@@ -4057,7 +4660,6 @@ IO Module Instances. Mapped to memory. - #define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ - #define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ - - - /* OSC.STATUS bit masks and bit positions */ - #define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ - #define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -@@ -4074,7 +4676,6 @@ IO Module Instances. Mapped to memory. - #define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ - #define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ - +-/* PR.PRPF bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ - - /* OSC.XOSCCTRL bit masks and bit positions */ - #define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ - #define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -@@ -4086,6 +4687,9 @@ IO Module Instances. Mapped to memory. - #define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ - #define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ - -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ - #define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ - #define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ - #define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -@@ -4097,7 +4701,6 @@ IO Module Instances. Mapped to memory. - #define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ - #define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ - +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ - - /* OSC.XOSCFAIL bit masks and bit positions */ - #define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ - #define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -@@ -4111,7 +4714,6 @@ IO Module Instances. Mapped to memory. - #define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ - #define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ - +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ - - /* OSC.PLLCTRL bit masks and bit positions */ - #define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ - #define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -@@ -4120,6 +4722,9 @@ IO Module Instances. Mapped to memory. - #define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ - #define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ - -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ - #define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ - #define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ - #define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -@@ -4133,25 +4738,22 @@ IO Module Instances. Mapped to memory. - #define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ - #define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ - +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ - - /* OSC.DFLLCTRL bit masks and bit positions */ +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* SLEEP - Sleep Controller */ +-/* SLEEP.CTRL bit masks and bit positions */ +-#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +-#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +-#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +-#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +-#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +-#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +-#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +-#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ +- +-#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +-#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ +- +- +-/* OSC - Oscillator */ +-/* OSC.CTRL bit masks and bit positions */ +-#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +-#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ +- +-#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +-#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ +- +-#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ +- +- +-/* OSC.STATUS bit masks and bit positions */ +-#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +-#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ +- +-#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +-#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ +- +-#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ +- +- +-/* OSC.XOSCCTRL bit masks and bit positions */ +-#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +-#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +-#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +-#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +-#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +-#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ +- +-#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ +-#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ +- +-#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +-#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +-#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +-#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +-#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +-#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +-#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +-#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +-#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +-#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +- +- +-/* OSC.XOSCFAIL bit masks and bit positions */ +-#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ +-#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ +- +-#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ +-#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ +- +-#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ +-#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ +- +-#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ +-#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ +- +- +-/* OSC.PLLCTRL bit masks and bit positions */ +-#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +-#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +-#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +-#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +-#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +-#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ +- +-#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +-#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +-#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +-#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +-#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +-#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +-#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +-#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +-#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +-#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +-#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +-#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ +- +- +-/* OSC.DFLLCTRL bit masks and bit positions */ -#define OSC_RC32MCREF_gm 0x06 /* 32 MHz Calibration Reference group mask. */ -#define OSC_RC32MCREF_gp 1 /* 32 MHz Calibration Reference group position. */ -#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz Calibration Reference bit 0 mask. */ @@ -215747,79 +616352,130 @@ index 646e316..e53146b 100644 - -#define OSC_RC2MCREF_bm 0x01 /* 2 MHz Calibration Reference bit mask. */ -#define OSC_RC2MCREF_bp 0 /* 2 MHz Calibration Reference bit position. */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ - -+#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -+#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ - - /* DFLL - DFLL */ - /* DFLL.CTRL bit masks and bit positions */ - #define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ - #define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - - - /* DFLL.CALA bit masks and bit positions */ - #define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ - #define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -@@ -4170,7 +4772,6 @@ IO Module Instances. Mapped to memory. - #define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ - #define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - - - /* DFLL.CALB bit masks and bit positions */ - #define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ - #define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -@@ -4187,7 +4788,6 @@ IO Module Instances. Mapped to memory. - #define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ - #define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - +-/* DFLL - DFLL */ +-/* DFLL.CTRL bit masks and bit positions */ +-#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +-#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ - - /* RST - Reset */ - /* RST.STATUS bit masks and bit positions */ - #define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -@@ -4211,12 +4811,10 @@ IO Module Instances. Mapped to memory. - #define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ - #define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ - - - /* RST.CTRL bit masks and bit positions */ - #define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ - #define RST_SWRST_bp 0 /* Software Reset bit position. */ - +-/* DFLL.CALA bit masks and bit positions */ +-#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ +-#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ +-#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ +-#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ +-#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ +-#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ +-#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ +-#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ +-#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ +-#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ +-#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ +-#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ +-#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ +-#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ +-#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ +-#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ - - /* WDT - Watch-Dog Timer */ - /* WDT.CTRL bit masks and bit positions */ - #define WDT_PER_gm 0x3C /* Period group mask. */ -@@ -4236,7 +4834,6 @@ IO Module Instances. Mapped to memory. - #define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ - #define WDT_CEN_bp 0 /* Change Enable bit position. */ - - - /* WDT.WINCTRL bit masks and bit positions */ - #define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ - #define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -@@ -4255,33 +4852,29 @@ IO Module Instances. Mapped to memory. - #define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ - #define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ - +-/* DFLL.CALB bit masks and bit positions */ +-#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ +-#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ +-#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ +-#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ +-#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ +-#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ +-#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ +-#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ +-#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ +-#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ +-#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ +-#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ +-#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ +-#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ - - /* WDT.STATUS bit masks and bit positions */ - #define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ - #define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ - - - /* MCU - MCU Control */ - /* MCU.MCUCR bit masks and bit positions */ - #define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ - #define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ - +-/* RST - Reset */ +-/* RST.STATUS bit masks and bit positions */ +-#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +-#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ - - /* MCU.ANAINIT bit masks and bit positions */ +-#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +-#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ +- +-#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +-#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ +- +-#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +-#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ +- +-#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +-#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ +- +-#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +-#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ +- +-#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +-#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ +- +- +-/* RST.CTRL bit masks and bit positions */ +-#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +-#define RST_SWRST_bp 0 /* Software Reset bit position. */ +- +- +-/* WDT - Watch-Dog Timer */ +-/* WDT.CTRL bit masks and bit positions */ +-#define WDT_PER_gm 0x3C /* Period group mask. */ +-#define WDT_PER_gp 2 /* Period group position. */ +-#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +-#define WDT_PER0_bp 2 /* Period bit 0 position. */ +-#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +-#define WDT_PER1_bp 3 /* Period bit 1 position. */ +-#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +-#define WDT_PER2_bp 4 /* Period bit 2 position. */ +-#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +-#define WDT_PER3_bp 5 /* Period bit 3 position. */ +- +-#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +-#define WDT_ENABLE_bp 1 /* Enable bit position. */ +- +-#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +-#define WDT_CEN_bp 0 /* Change Enable bit position. */ +- +- +-/* WDT.WINCTRL bit masks and bit positions */ +-#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +-#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +-#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +-#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +-#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +-#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +-#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +-#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +-#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +-#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ +- +-#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +-#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ +- +-#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +-#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ +- +- +-/* WDT.STATUS bit masks and bit positions */ +-#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +-#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +- +- +-/* MCU - MCU Control */ +-/* MCU.MCUCR bit masks and bit positions */ +-#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +-#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ +- +- +-/* MCU.ANAINIT bit masks and bit positions */ -#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port A group mask. */ -#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port A group position. */ -#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port A bit 0 mask. */ @@ -215834,164 +616490,180 @@ index 646e316..e53146b 100644 -#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port B bit 1 mask. */ -#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port B bit 1 position. */ - -+#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -+#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -+#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -+#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -+#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -+#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ -+ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ - - /* MCU.EVSYSLOCK bit masks and bit positions */ - #define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -@@ -4290,15 +4883,19 @@ IO Module Instances. Mapped to memory. - #define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ - #define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - - - /* MCU.AWEXLOCK bit masks and bit positions */ -+#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ -+#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ -+ - #define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ - #define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - -+#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ -+#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ -+ - #define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ - #define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - +-/* MCU.EVSYSLOCK bit masks and bit positions */ +-#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +-#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ - - /* PMIC - Programmable Multi-level Interrupt Controller */ - /* PMIC.STATUS bit masks and bit positions */ - #define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -@@ -4313,6 +4910,25 @@ IO Module Instances. Mapped to memory. - #define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ - #define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ - -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ - - /* PMIC.CTRL bit masks and bit positions */ - #define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -@@ -4330,7 +4946,6 @@ IO Module Instances. Mapped to memory. - #define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ - #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - +-#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +-#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ - - /* PORTCFG - Port Configuration */ - /* PORTCFG.VPCTRLA bit masks and bit positions */ - #define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -@@ -4355,7 +4970,6 @@ IO Module Instances. Mapped to memory. - #define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ - #define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ - - - /* PORTCFG.VPCTRLB bit masks and bit positions */ - #define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ - #define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -@@ -4379,7 +4993,6 @@ IO Module Instances. Mapped to memory. - #define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ - #define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ - +-/* MCU.AWEXLOCK bit masks and bit positions */ +-#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +-#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ - - /* PORTCFG.CLKEVOUT bit masks and bit positions */ - #define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ - #define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -@@ -4408,6 +5021,30 @@ IO Module Instances. Mapped to memory. - #define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ - #define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ - -+/* PORTCFG.EBIOUT bit masks and bit positions */ -+#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ -+#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ -+#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ -+#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ -+#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ -+#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ -+ -+#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ -+#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ -+#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ -+#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ -+#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ -+#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ -+ -+/* PORTCFG.EVOUTSEL bit masks and bit positions */ -+#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -+#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -+#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -+#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -+#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -+#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -+#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -+#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ - - /* AES - AES Module */ - /* AES.CTRL bit masks and bit positions */ -@@ -4426,7 +5063,6 @@ IO Module Instances. Mapped to memory. - #define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ - #define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ - +-#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +-#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ - - /* AES.STATUS bit masks and bit positions */ - #define AES_ERROR_bm 0x80 /* AES Error bit mask. */ - #define AES_ERROR_bp 7 /* AES Error bit position. */ -@@ -4434,7 +5070,6 @@ IO Module Instances. Mapped to memory. - #define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ - #define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ - - - /* AES.INTCTRL bit masks and bit positions */ - #define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ - #define AES_INTLVL_gp 0 /* Interrupt level group position. */ -@@ -4443,38 +5078,35 @@ IO Module Instances. Mapped to memory. - #define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ - #define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - +-/* PMIC - Programmable Multi-level Interrupt Controller */ +-/* PMIC.STATUS bit masks and bit positions */ +-#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +-#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ - - /* CRC - Cyclic Redundancy Checker */ - /* CRC.CTRL bit masks and bit positions */ +-#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +-#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ +- +-#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +-#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ +- +-#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +-#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ +- +- +-/* PMIC.CTRL bit masks and bit positions */ +-#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +-#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ +- +-#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +-#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ +- +-#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +-#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ +- +-#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +-#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ +- +-#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +-#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ +- +- +-/* PORTCFG - Port Configuration */ +-/* PORTCFG.VPCTRLA bit masks and bit positions */ +-#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +-#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +-#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +-#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +-#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +-#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +-#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +-#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +-#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +-#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ +- +-#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +-#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +-#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +-#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +-#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +-#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +-#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +-#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +-#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +-#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ +- +- +-/* PORTCFG.VPCTRLB bit masks and bit positions */ +-#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +-#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +-#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +-#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +-#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +-#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +-#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +-#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +-#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +-#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ +- +-#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +-#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +-#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +-#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +-#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +-#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +-#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +-#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +-#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +-#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ +- +- +-/* PORTCFG.CLKEVOUT bit masks and bit positions */ +-#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ +-#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ +-#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ +-#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ +-#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ +-#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ +- +-#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ +-#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ +-#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ +-#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ +-#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ +-#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ +- +-#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +-#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +-#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +-#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +-#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +-#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ +- +-#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ +-#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ +- +-#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ +-#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ +- +- +-/* AES - AES Module */ +-/* AES.CTRL bit masks and bit positions */ +-#define AES_START_bm 0x80 /* Start/Run bit mask. */ +-#define AES_START_bp 7 /* Start/Run bit position. */ +- +-#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +-#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ +- +-#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +-#define AES_RESET_bp 5 /* AES Software Reset bit position. */ +- +-#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +-#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ +- +-#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +-#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ +- +- +-/* AES.STATUS bit masks and bit positions */ +-#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +-#define AES_ERROR_bp 7 /* AES Error bit position. */ +- +-#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +-#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ +- +- +-/* AES.INTCTRL bit masks and bit positions */ +-#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +-#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +-/* CRC - Cyclic Redundancy Checker */ +-/* CRC.CTRL bit masks and bit positions */ -#define CRC_RESET_gm 0xC0 /* CRC Reset group mask. */ -#define CRC_RESET_gp 6 /* CRC Reset group position. */ -#define CRC_RESET0_bm (1<<6) /* CRC Reset bit 0 mask. */ -#define CRC_RESET0_bp 6 /* CRC Reset bit 0 position. */ -#define CRC_RESET1_bm (1<<7) /* CRC Reset bit 1 mask. */ -#define CRC_RESET1_bp 7 /* CRC Reset bit 1 position. */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ - - #define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ - #define CRC_CRC32_bp 5 /* CRC Mode bit position. */ - +- +-#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ +-#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ +- -#define CRC_SOURCE_gm 0x0F /* CRC Input Source group mask. */ -#define CRC_SOURCE_gp 0 /* CRC Input Source group position. */ -#define CRC_SOURCE0_bm (1<<0) /* CRC Input Source bit 0 mask. */ @@ -216003,93 +616675,216 @@ index 646e316..e53146b 100644 -#define CRC_SOURCE3_bm (1<<3) /* CRC Input Source bit 3 mask. */ -#define CRC_SOURCE3_bp 3 /* CRC Input Source bit 3 position. */ - -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ - - /* CRC.STATUS bit masks and bit positions */ +- +-/* CRC.STATUS bit masks and bit positions */ -#define CRC_ZERO_bm 0x02 /* Zero CRC detection bit mask. */ -#define CRC_ZERO_bp 1 /* Zero CRC detection bit position. */ - -#define CRC_BUSY_bm 0x01 /* Enable bit mask. */ -#define CRC_BUSY_bp 0 /* Enable bit position. */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ - -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ - - /* DMA - DMA Controller */ - /* DMA_CH.CTRLA bit masks and bit positions */ -@@ -4500,7 +5132,6 @@ IO Module Instances. Mapped to memory. - #define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ - #define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - - - /* DMA_CH.CTRLB bit masks and bit positions */ - #define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ - #define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ -@@ -4528,7 +5159,6 @@ IO Module Instances. Mapped to memory. - #define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ - #define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ - - - /* DMA_CH.ADDRCTRL bit masks and bit positions */ - #define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ - #define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -@@ -4558,7 +5188,6 @@ IO Module Instances. Mapped to memory. - #define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ - #define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ - +-/* DMA - DMA Controller */ +-/* DMA_CH.CTRLA bit masks and bit positions */ +-#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +-#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ - - /* DMA_CH.TRIGSRC bit masks and bit positions */ - #define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ - #define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -@@ -4579,7 +5208,6 @@ IO Module Instances. Mapped to memory. - #define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ - #define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ - +-#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +-#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ - - /* DMA.CTRL bit masks and bit positions */ - #define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ - #define DMA_ENABLE_bp 7 /* Enable bit position. */ -@@ -4601,7 +5229,6 @@ IO Module Instances. Mapped to memory. - #define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ - #define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ - +-#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +-#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ - - /* DMA.INTFLAGS bit masks and bit positions */ - #define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ - #define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ -@@ -4627,7 +5254,6 @@ IO Module Instances. Mapped to memory. - #define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ - #define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ - +-#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +-#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ - - /* DMA.STATUS bit masks and bit positions */ - #define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ - #define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ -@@ -4653,7 +5279,6 @@ IO Module Instances. Mapped to memory. - #define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ - #define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ - +-#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +-#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ - - /* EVSYS - Event System */ - /* EVSYS.CH0MUX bit masks and bit positions */ - #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -@@ -4675,153 +5300,33 @@ IO Module Instances. Mapped to memory. - #define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ - #define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ - +-#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +-#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +-#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +-#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +-#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +-#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ - - /* EVSYS.CH1MUX bit masks and bit positions */ +- +-/* DMA_CH.CTRLB bit masks and bit positions */ +-#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +-#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ +- +-#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +-#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ +- +-#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +-#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ +- +-#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +-#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +-#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +-#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +-#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +-#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ +- +-#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +-#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +-#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +-#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +-#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +-#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ +- +- +-/* DMA_CH.ADDRCTRL bit masks and bit positions */ +-#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +-#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +-#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +-#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +-#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +-#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ +- +-#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +-#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +-#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +-#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +-#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +-#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ +- +-#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +-#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +-#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +-#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +-#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +-#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ +- +-#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +-#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +-#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +-#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +-#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +-#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ +- +- +-/* DMA_CH.TRIGSRC bit masks and bit positions */ +-#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +-#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +-#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +-#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +-#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +-#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +-#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +-#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +-#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +-#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +-#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +-#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +-#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +-#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +-#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +-#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +-#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +-#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ +- +- +-/* DMA.CTRL bit masks and bit positions */ +-#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +-#define DMA_ENABLE_bp 7 /* Enable bit position. */ +- +-#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +-#define DMA_RESET_bp 6 /* Software Reset bit position. */ +- +-#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +-#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +-#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +-#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +-#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +-#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ +- +-#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +-#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +-#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +-#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +-#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +-#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ +- +- +-/* DMA.INTFLAGS bit masks and bit positions */ +-#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ +- +- +-/* DMA.STATUS bit masks and bit positions */ +-#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +-#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ +- +-#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +-#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ +- +-#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +-#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ +- +-#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +-#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ +- +-#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +-#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ +- +-#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +-#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ +- +-#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +-#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ +- +-#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +-#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ +- +- +-/* EVSYS - Event System */ +-/* EVSYS.CH0MUX bit masks and bit positions */ +-#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +-#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +-#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +-#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +-#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +-#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +-#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +-#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +-#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +-#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +-#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +-#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +-#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +-#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +-#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +-#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +-#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +-#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ +- +- +-/* EVSYS.CH1MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ @@ -216109,10 +616904,8 @@ index 646e316..e53146b 100644 -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ - - /* EVSYS.CH2MUX bit masks and bit positions */ +- +-/* EVSYS.CH2MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ @@ -216132,10 +616925,8 @@ index 646e316..e53146b 100644 -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ - - /* EVSYS.CH3MUX bit masks and bit positions */ +- +-/* EVSYS.CH3MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ @@ -216155,10 +616946,8 @@ index 646e316..e53146b 100644 -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ - - /* EVSYS.CH4MUX bit masks and bit positions */ +- +-/* EVSYS.CH4MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ @@ -216178,10 +616967,8 @@ index 646e316..e53146b 100644 -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ - - /* EVSYS.CH5MUX bit masks and bit positions */ +- +-/* EVSYS.CH5MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ @@ -216201,10 +616988,8 @@ index 646e316..e53146b 100644 -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ - - /* EVSYS.CH6MUX bit masks and bit positions */ +- +-/* EVSYS.CH6MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ @@ -216224,10 +617009,8 @@ index 646e316..e53146b 100644 -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ - - /* EVSYS.CH7MUX bit masks and bit positions */ +- +-/* EVSYS.CH7MUX bit masks and bit positions */ -/* EVSYS_CHMUX_gm Predefined. */ -/* EVSYS_CHMUX_gp Predefined. */ -/* EVSYS_CHMUX0_bm Predefined. */ @@ -216247,17 +617030,32 @@ index 646e316..e53146b 100644 -/* EVSYS_CHMUX7_bm Predefined. */ -/* EVSYS_CHMUX7_bp Predefined. */ - -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ - - /* EVSYS.CH0CTRL bit masks and bit positions */ - #define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -@@ -4846,109 +5351,51 @@ IO Module Instances. Mapped to memory. - #define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ - #define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ - - - /* EVSYS.CH1CTRL bit masks and bit positions */ +-/* EVSYS.CH0CTRL bit masks and bit positions */ +-#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +-#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +-#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +-#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +-#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +-#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ +- +-#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +-#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ +- +-#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +-#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ +- +-#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +-#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +-#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +-#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +-#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +-#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +-#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +-#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ +- +- +-/* EVSYS.CH1CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ @@ -216267,10 +617065,8 @@ index 646e316..e53146b 100644 -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ - - /* EVSYS.CH2CTRL bit masks and bit positions */ +- +-/* EVSYS.CH2CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ @@ -216280,29 +617076,10 @@ index 646e316..e53146b 100644 - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ -+/* EVSYS_QDIRM Predefined. */ -+/* EVSYS_QDIRM Predefined. */ - +- -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ -+/* EVSYS_QDIEN Predefined. */ -+/* EVSYS_QDIEN Predefined. */ - --/* EVSYS_DIGFILT_gm Predefined. */ --/* EVSYS_DIGFILT_gp Predefined. */ --/* EVSYS_DIGFILT0_bm Predefined. */ --/* EVSYS_DIGFILT0_bp Predefined. */ --/* EVSYS_DIGFILT1_bm Predefined. */ --/* EVSYS_DIGFILT1_bp Predefined. */ --/* EVSYS_DIGFILT2_bm Predefined. */ --/* EVSYS_DIGFILT2_bp Predefined. */ -+/* EVSYS_QDEN Predefined. */ -+/* EVSYS_QDEN Predefined. */ - -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ - - /* EVSYS.CH3CTRL bit masks and bit positions */ +- -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ @@ -216312,10 +617089,19 @@ index 646e316..e53146b 100644 -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ - - /* EVSYS.CH4CTRL bit masks and bit positions */ +- +-/* EVSYS.CH3CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH4CTRL bit masks and bit positions */ -/* EVSYS_QDIRM_gm Predefined. */ -/* EVSYS_QDIRM_gp Predefined. */ -/* EVSYS_QDIRM0_bm Predefined. */ @@ -216325,29 +617111,10 @@ index 646e316..e53146b 100644 - -/* EVSYS_QDIEN_bm Predefined. */ -/* EVSYS_QDIEN_bp Predefined. */ -+/* EVSYS_QDIRM Predefined. */ -+/* EVSYS_QDIRM Predefined. */ - +- -/* EVSYS_QDEN_bm Predefined. */ -/* EVSYS_QDEN_bp Predefined. */ -+/* EVSYS_QDIEN Predefined. */ -+/* EVSYS_QDIEN Predefined. */ - --/* EVSYS_DIGFILT_gm Predefined. */ --/* EVSYS_DIGFILT_gp Predefined. */ --/* EVSYS_DIGFILT0_bm Predefined. */ --/* EVSYS_DIGFILT0_bp Predefined. */ --/* EVSYS_DIGFILT1_bm Predefined. */ --/* EVSYS_DIGFILT1_bp Predefined. */ --/* EVSYS_DIGFILT2_bm Predefined. */ --/* EVSYS_DIGFILT2_bp Predefined. */ -+/* EVSYS_QDEN Predefined. */ -+/* EVSYS_QDEN Predefined. */ - -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ - - /* EVSYS.CH5CTRL bit masks and bit positions */ +- -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ @@ -216357,10 +617124,8 @@ index 646e316..e53146b 100644 -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ - - /* EVSYS.CH6CTRL bit masks and bit positions */ +- +-/* EVSYS.CH5CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ @@ -216370,10 +617135,8 @@ index 646e316..e53146b 100644 -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ - - /* EVSYS.CH7CTRL bit masks and bit positions */ +- +-/* EVSYS.CH6CTRL bit masks and bit positions */ -/* EVSYS_DIGFILT_gm Predefined. */ -/* EVSYS_DIGFILT_gp Predefined. */ -/* EVSYS_DIGFILT0_bm Predefined. */ @@ -216383,207 +617146,370 @@ index 646e316..e53146b 100644 -/* EVSYS_DIGFILT2_bm Predefined. */ -/* EVSYS_DIGFILT2_bp Predefined. */ - -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ - - /* NVM - Non Volatile Memory Controller */ - /* NVM.CMD bit masks and bit positions */ -@@ -4969,12 +5416,10 @@ IO Module Instances. Mapped to memory. - #define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ - #define NVM_CMD6_bp 6 /* Command bit 6 position. */ - - - /* NVM.CTRLA bit masks and bit positions */ - #define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ - #define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - +-/* EVSYS.CH7CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ - - /* NVM.CTRLB bit masks and bit positions */ - #define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ - #define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ -@@ -4988,7 +5433,6 @@ IO Module Instances. Mapped to memory. - #define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ - #define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ - - - /* NVM.INTCTRL bit masks and bit positions */ - #define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ - #define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -@@ -5004,7 +5448,6 @@ IO Module Instances. Mapped to memory. - #define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ - #define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ - +-/* NVM - Non Volatile Memory Controller */ +-/* NVM.CMD bit masks and bit positions */ +-#define NVM_CMD_gm 0x7F /* Command group mask. */ +-#define NVM_CMD_gp 0 /* Command group position. */ +-#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +-#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +-#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +-#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +-#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +-#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +-#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +-#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +-#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +-#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +-#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +-#define NVM_CMD6_bp 6 /* Command bit 6 position. */ - - /* NVM.STATUS bit masks and bit positions */ - #define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ - #define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -@@ -5018,7 +5461,6 @@ IO Module Instances. Mapped to memory. - #define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ - #define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ - - - /* NVM.LOCKBITS bit masks and bit positions */ - #define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ - #define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -@@ -5048,7 +5490,6 @@ IO Module Instances. Mapped to memory. - #define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ - #define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ - +-/* NVM.CTRLA bit masks and bit positions */ +-#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +-#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ - - /* ADC - Analog/Digital Converter */ - /* ADC_CH.CTRL bit masks and bit positions */ - #define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -@@ -5070,7 +5511,6 @@ IO Module Instances. Mapped to memory. - #define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ - #define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ - - - /* ADC_CH.MUXCTRL bit masks and bit positions */ - #define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ - #define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -@@ -5094,13 +5534,14 @@ IO Module Instances. Mapped to memory. - #define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ - #define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ - +-/* NVM.CTRLB bit masks and bit positions */ +-#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +-#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ +- +-#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +-#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ +- +-#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +-#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ +- +-#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +-#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ +- +- +-/* NVM.INTCTRL bit masks and bit positions */ +-#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +-#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +-#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +-#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +-#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +-#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ +- +-#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +-#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +-#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +-#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +-#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +-#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ +- +- +-/* NVM.STATUS bit masks and bit positions */ +-#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +-#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ +- +-#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +-#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ +- +-#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +-#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ +- +-#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +-#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ +- +- +-/* NVM.LOCKBITS bit masks and bit positions */ +-#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* ADC - Analog/Digital Converter */ +-/* ADC_CH.CTRL bit masks and bit positions */ +-#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +-#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ +- +-#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ +-#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ +-#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ +-#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ +-#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ +-#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ +-#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ +-#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ +- +-#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +-#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +-#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +-#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +-#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +-#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ +- +- +-/* ADC_CH.MUXCTRL bit masks and bit positions */ +-#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ +-#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ +-#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ +-#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ +-#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ +-#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ +-#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ +-#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ +-#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ +-#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ +- +-#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ +-#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ +-#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ +-#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ +-#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ +-#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ +-#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ +-#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ +-#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ +-#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ +- -#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -+#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ - #define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ - #define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ - #define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ - #define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ - #define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ +-#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ +-#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ +-#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ +-#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ +-#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ - -+#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ -+#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ - - /* ADC_CH.INTCTRL bit masks and bit positions */ - #define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -@@ -5117,11 +5558,32 @@ IO Module Instances. Mapped to memory. - #define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ - #define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - - - /* ADC_CH.INTFLAGS bit masks and bit positions */ - #define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ - #define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ - -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -+#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -+#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -+#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -+#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -+#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -+#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -+#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -+#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -+#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ -+ -+#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -+#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -+#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -+#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -+#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -+#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -+#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -+#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -+#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -+#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ - - /* ADC.CTRLA bit masks and bit positions */ - #define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -@@ -5149,17 +5611,16 @@ IO Module Instances. Mapped to memory. - #define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ - #define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ - +-/* ADC_CH.INTCTRL bit masks and bit positions */ +-#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +-#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +-#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +-#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +-#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +-#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ +- +-#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +-#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +-#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +-#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +-#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +-#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ +- +- +-/* ADC_CH.INTFLAGS bit masks and bit positions */ +-#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +-#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ +- +- +-/* ADC.CTRLA bit masks and bit positions */ +-#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +-#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +-#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +-#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +-#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +-#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ +- +-#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +-#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ +- +-#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +-#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ +- +-#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +-#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ +- +-#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +-#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ +- +-#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +-#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ +- +-#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +-#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ +- +- +-/* ADC.CTRLB bit masks and bit positions */ +-#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ +-#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ - - /* ADC.CTRLB bit masks and bit positions */ - #define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ - #define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ - -#define ADC_CURRENT_gm 0x60 /* Current Limitation group mask. */ -#define ADC_CURRENT_gp 5 /* Current Limitation group position. */ -#define ADC_CURRENT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -#define ADC_CURRENT0_bp 5 /* Current Limitation bit 0 position. */ -#define ADC_CURRENT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -#define ADC_CURRENT1_bp 6 /* Current Limitation bit 1 position. */ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ - - #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ - #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -@@ -5174,7 +5635,6 @@ IO Module Instances. Mapped to memory. - #define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ - #define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - - - /* ADC.REFCTRL bit masks and bit positions */ - #define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ - #define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -@@ -5191,7 +5651,6 @@ IO Module Instances. Mapped to memory. - #define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ - #define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ - +-#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +-#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - - /* ADC.EVCTRL bit masks and bit positions */ - #define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ - #define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -@@ -5218,7 +5677,6 @@ IO Module Instances. Mapped to memory. - #define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ - #define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ - +-#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +-#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ - - /* ADC.PRESCALER bit masks and bit positions */ - #define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ - #define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -@@ -5229,7 +5687,6 @@ IO Module Instances. Mapped to memory. - #define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ - #define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ - +-#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +-#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +-#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +-#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +-#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +-#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ - - /* ADC.INTFLAGS bit masks and bit positions */ - #define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ - #define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ -@@ -5243,7 +5700,6 @@ IO Module Instances. Mapped to memory. - #define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ - #define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ - - - /* DAC - Digital/Analog Converter */ - /* DAC.CTRLA bit masks and bit positions */ - #define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -@@ -5261,7 +5717,6 @@ IO Module Instances. Mapped to memory. - #define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ - #define DAC_ENABLE_bp 0 /* Enable bit position. */ - +-/* ADC.REFCTRL bit masks and bit positions */ +-#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ +-#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +-#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +-#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +-#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +-#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +-#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ +-#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ - - /* DAC.CTRLB bit masks and bit positions */ - #define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ - #define DAC_CHSEL_gp 5 /* Channel Select group position. */ -@@ -5276,7 +5731,6 @@ IO Module Instances. Mapped to memory. - #define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ - #define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ - +-#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +-#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ - - /* DAC.CTRLC bit masks and bit positions */ - #define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ - #define DAC_REFSEL_gp 3 /* Reference Select group position. */ -@@ -5288,7 +5742,6 @@ IO Module Instances. Mapped to memory. - #define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ - #define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ - +-#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +-#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ +- +- +-/* ADC.EVCTRL bit masks and bit positions */ +-#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +-#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +-#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +-#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +-#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +-#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ +- +-#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +-#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +-#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +-#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +-#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +-#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +-#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +-#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ +- +-#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +-#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +-#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +-#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +-#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +-#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +-#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +-#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ +- +- +-/* ADC.PRESCALER bit masks and bit positions */ +-#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +-#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +-#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +-#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +-#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +-#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +-#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +-#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ +- +- +-/* ADC.INTFLAGS bit masks and bit positions */ +-#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +-#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ +- +-#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +-#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ +- +-#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +-#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ +- +-#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +-#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ +- +- +-/* DAC - Digital/Analog Converter */ +-/* DAC.CTRLA bit masks and bit positions */ +-#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +-#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ +- +-#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +-#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ +- +-#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +-#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ +- +-#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +-#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ +- +-#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define DAC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* DAC.CTRLB bit masks and bit positions */ +-#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +-#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +-#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +-#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +-#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +-#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ +- +-#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +-#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ +- +-#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +-#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ +- +- +-/* DAC.CTRLC bit masks and bit positions */ +-#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +-#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +-#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +-#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +-#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +-#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ +- +-#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +-#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ +- +- +-/* DAC.EVCTRL bit masks and bit positions */ +-#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ +-#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ +- +-#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +-#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +-#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +-#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +-#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +-#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +-#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +-#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - - /* DAC.EVCTRL bit masks and bit positions */ - #define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ - #define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ -@@ -5302,29 +5755,6 @@ IO Module Instances. Mapped to memory. - #define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ - #define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ - - -/* DAC.TIMCTRL bit masks and bit positions */ -#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ @@ -216607,55 +617533,121 @@ index 646e316..e53146b 100644 -#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ - - - /* DAC.STATUS bit masks and bit positions */ - #define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ - #define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ -@@ -5332,7 +5762,6 @@ IO Module Instances. Mapped to memory. - #define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ - #define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - +-/* DAC.STATUS bit masks and bit positions */ +-#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +-#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ - - /* DAC.CH0GAINCAL bit masks and bit positions */ - #define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ - #define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -@@ -5351,7 +5780,6 @@ IO Module Instances. Mapped to memory. - #define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ - #define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - +-#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +-#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ - - /* DAC.CH0OFFSETCAL bit masks and bit positions */ - #define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ - #define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -@@ -5370,7 +5798,6 @@ IO Module Instances. Mapped to memory. - #define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ - #define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - - - /* DAC.CH1GAINCAL bit masks and bit positions */ - #define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ - #define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -@@ -5389,7 +5816,6 @@ IO Module Instances. Mapped to memory. - #define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ - #define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - +-/* DAC.CH0GAINCAL bit masks and bit positions */ +-#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +-#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ +-#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +-#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +-#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +-#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +-#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +-#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +-#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +-#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +-#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +-#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +-#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +-#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +-#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +-#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ - - /* DAC.CH1OFFSETCAL bit masks and bit positions */ - #define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ - #define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -@@ -5408,7 +5834,6 @@ IO Module Instances. Mapped to memory. - #define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ - #define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - - - /* AC - Analog Comparator */ - /* AC.AC0CTRL bit masks and bit positions */ - #define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -@@ -5438,35 +5863,21 @@ IO Module Instances. Mapped to memory. - #define AC_ENABLE_bm 0x01 /* Enable bit mask. */ - #define AC_ENABLE_bp 0 /* Enable bit position. */ - +-/* DAC.CH0OFFSETCAL bit masks and bit positions */ +-#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +-#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ +-#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +-#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +-#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +-#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +-#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +-#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +-#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +-#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +-#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +-#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +-#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +-#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +-#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +-#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ - - /* AC.AC1CTRL bit masks and bit positions */ +- +-/* DAC.CH1GAINCAL bit masks and bit positions */ +-#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ +-#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ +-#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ +-#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ +-#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ +-#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ +-#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ +-#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ +-#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ +-#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ +-#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ +-#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ +-#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ +-#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ +-#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ +-#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ +- +- +-/* DAC.CH1OFFSETCAL bit masks and bit positions */ +-#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ +-#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ +-#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ +-#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ +-#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ +-#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ +-#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ +-#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ +-#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ +-#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ +-#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ +-#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ +-#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ +-#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ +-#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ +-#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ +- +- +-/* AC - Analog Comparator */ +-/* AC.AC0CTRL bit masks and bit positions */ +-#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +-#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +-#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +-#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +-#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +-#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ +- +-#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +-#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +-#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +-#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +-#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +-#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ +- +-#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +-#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ +- +-#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +-#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +-#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +-#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +-#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +-#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +- +-#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define AC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* AC.AC1CTRL bit masks and bit positions */ -/* AC_INTMODE_gm Predefined. */ -/* AC_INTMODE_gp Predefined. */ -/* AC_INTMODE0_bm Predefined. */ @@ -216682,29 +617674,29 @@ index 646e316..e53146b 100644 - -/* AC_ENABLE_bm Predefined. */ -/* AC_ENABLE_bp Predefined. */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HSMODE Predefined. */ -+/* AC_HSMODE Predefined. */ - -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ - - /* AC.AC0MUXCTRL bit masks and bit positions */ - #define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -@@ -5487,32 +5898,20 @@ IO Module Instances. Mapped to memory. - #define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ - #define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ - - - /* AC.AC1MUXCTRL bit masks and bit positions */ +- +-/* AC.AC0MUXCTRL bit masks and bit positions */ +-#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +-#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +-#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +-#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +-#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +-#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +-#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +-#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ +- +-#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +-#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +-#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +-#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +-#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +-#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +-#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +-#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ +- +- +-/* AC.AC1MUXCTRL bit masks and bit positions */ -/* AC_MUXPOS_gm Predefined. */ -/* AC_MUXPOS_gp Predefined. */ -/* AC_MUXPOS0_bm Predefined. */ @@ -216722,77 +617714,116 @@ index 646e316..e53146b 100644 -/* AC_MUXNEG1_bp Predefined. */ -/* AC_MUXNEG2_bm Predefined. */ -/* AC_MUXNEG2_bp Predefined. */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ - -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ - - /* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ - #define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ - #define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ - - - /* AC.CTRLB bit masks and bit positions */ - #define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ - #define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -@@ -5529,7 +5928,6 @@ IO Module Instances. Mapped to memory. - #define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ - #define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ - - - /* AC.WINCTRL bit masks and bit positions */ - #define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ - #define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -@@ -5548,7 +5946,6 @@ IO Module Instances. Mapped to memory. - #define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ - #define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ - +-/* AC.CTRLA bit masks and bit positions */ +-#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ +-#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ +- +- +-/* AC.CTRLB bit masks and bit positions */ +-#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +-#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +-#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +-#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +-#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +-#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +-#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +-#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +-#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +-#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +-#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +-#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +-#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +-#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ +- +- +-/* AC.WINCTRL bit masks and bit positions */ +-#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +-#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ +- +-#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +-#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +-#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +-#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +-#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +-#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ +- +-#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +-#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +-#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +-#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +-#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +-#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ +- +- +-/* AC.STATUS bit masks and bit positions */ +-#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +-#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +-#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +-#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +-#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +-#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ +- +-#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ +-#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ +- +-#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ +-#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ +- +-#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +-#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ +- +-#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ +-#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ +- +-#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ +-#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - - /* AC.STATUS bit masks and bit positions */ - #define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ - #define AC_WSTATE_gp 6 /* Window Mode State group position. */ -@@ -5572,8 +5969,7 @@ IO Module Instances. Mapped to memory. - #define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ - #define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ - - -/* RTC - Real-Time Clounter */ -+/* RTC - Real-Time Counter */ - /* RTC.CTRL bit masks and bit positions */ - #define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ - #define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -@@ -5584,12 +5980,10 @@ IO Module Instances. Mapped to memory. - #define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ - #define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - +-/* RTC.CTRL bit masks and bit positions */ +-#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +-#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +-#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +-#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +-#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +-#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +-#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +-#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ - - /* RTC.STATUS bit masks and bit positions */ - #define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ - #define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - - - /* RTC.INTCTRL bit masks and bit positions */ - #define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ - #define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -@@ -5605,7 +5999,6 @@ IO Module Instances. Mapped to memory. - #define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ - #define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ - +-/* RTC.STATUS bit masks and bit positions */ +-#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +-#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ - - /* RTC.INTFLAGS bit masks and bit positions */ - #define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ - #define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -@@ -5613,21 +6006,20 @@ IO Module Instances. Mapped to memory. - #define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ - #define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - - /* EBI - External Bus Interface */ - /* EBI_CS.CTRLA bit masks and bit positions */ +-/* RTC.INTCTRL bit masks and bit positions */ +-#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +-#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +-#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +-#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +-#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +-#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ +- +-#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +-#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +-#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +-#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +-#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +-#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ +- +- +-/* RTC.INTFLAGS bit masks and bit positions */ +-#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +-#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ +- +-#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* EBI - External Bus Interface */ +-/* EBI_CS.CTRLA bit masks and bit positions */ -#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ -#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ -#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ @@ -216805,202 +617836,356 @@ index 646e316..e53146b 100644 -#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ -#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ -#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ -+#define EBI_CS_ASPACE_gm 0x7C /* Address Space group mask. */ -+#define EBI_CS_ASPACE_gp 2 /* Address Space group position. */ -+#define EBI_CS_ASPACE0_bm (1<<2) /* Address Space bit 0 mask. */ -+#define EBI_CS_ASPACE0_bp 2 /* Address Space bit 0 position. */ -+#define EBI_CS_ASPACE1_bm (1<<3) /* Address Space bit 1 mask. */ -+#define EBI_CS_ASPACE1_bp 3 /* Address Space bit 1 position. */ -+#define EBI_CS_ASPACE2_bm (1<<4) /* Address Space bit 2 mask. */ -+#define EBI_CS_ASPACE2_bp 4 /* Address Space bit 2 position. */ -+#define EBI_CS_ASPACE3_bm (1<<5) /* Address Space bit 3 mask. */ -+#define EBI_CS_ASPACE3_bp 5 /* Address Space bit 3 position. */ -+#define EBI_CS_ASPACE4_bm (1<<6) /* Address Space bit 4 mask. */ -+#define EBI_CS_ASPACE4_bp 6 /* Address Space bit 4 position. */ - - #define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ - #define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ -@@ -5636,7 +6028,6 @@ IO Module Instances. Mapped to memory. - #define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ - #define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ - - - /* EBI_CS.CTRLB bit masks and bit positions */ - #define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ - #define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ -@@ -5660,7 +6051,6 @@ IO Module Instances. Mapped to memory. - #define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ - #define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ - +-#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +-#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +-#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +-#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +-#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +-#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ - - /* EBI.CTRL bit masks and bit positions */ - #define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ - #define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ -@@ -5690,7 +6080,6 @@ IO Module Instances. Mapped to memory. - #define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ - #define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ - - - /* EBI.SDRAMCTRLA bit masks and bit positions */ - #define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ - #define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ -@@ -5705,7 +6094,6 @@ IO Module Instances. Mapped to memory. - #define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ - #define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ - +-/* EBI_CS.CTRLB bit masks and bit positions */ +-#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +-#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +-#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +-#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +-#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +-#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +-#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +-#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ - - /* EBI.SDRAMCTRLB bit masks and bit positions */ - #define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ - #define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ -@@ -5732,7 +6120,6 @@ IO Module Instances. Mapped to memory. - #define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ - #define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ - +-#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +-#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ - - /* EBI.SDRAMCTRLC bit masks and bit positions */ - #define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ - #define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ -@@ -5759,7 +6146,6 @@ IO Module Instances. Mapped to memory. - #define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ - #define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ - +-#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +-#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ - - /* TWI - Two-Wire Interface */ - /* TWI_MASTER.CTRLA bit masks and bit positions */ - #define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -@@ -5778,14 +6164,13 @@ IO Module Instances. Mapped to memory. - #define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ - #define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ - +-#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +-#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +-#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +-#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +-#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +-#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ - - /* TWI_MASTER.CTRLB bit masks and bit positions */ +- +-/* EBI.CTRL bit masks and bit positions */ +-#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +-#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +-#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +-#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +-#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +-#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ +- +-#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +-#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +-#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +-#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +-#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +-#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ +- +-#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +-#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +-#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +-#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +-#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +-#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ +- +-#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +-#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +-#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +-#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +-#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +-#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLA bit masks and bit positions */ +-#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +-#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ +- +-#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +-#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ +- +-#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +-#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +-#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +-#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +-#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +-#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLB bit masks and bit positions */ +-#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +-#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +-#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +-#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +-#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +-#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ +- +-#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +-#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +-#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +-#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +-#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +-#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +-#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +-#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ +- +-#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +-#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +-#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +-#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +-#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +-#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +-#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +-#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ +- +- +-/* EBI.SDRAMCTRLC bit masks and bit positions */ +-#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +-#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +-#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +-#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +-#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +-#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ +- +-#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +-#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +-#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +-#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +-#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +-#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +-#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +-#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ +- +-#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +-#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +-#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +-#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +-#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +-#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +-#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +-#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ +- +- +-/* TWI - Two-Wire Interface */ +-/* TWI_MASTER.CTRLA bit masks and bit positions */ +-#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +-#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ +- +-#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +-#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ +- +-#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +-#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ +- +- +-/* TWI_MASTER.CTRLB bit masks and bit positions */ -#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Tisdahmeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Tisdahmeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Tisdahmeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Tisdahmeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Tisdahmeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Tisdahmeout bit 1 position. */ - - #define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ - #define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -@@ -5793,7 +6178,6 @@ IO Module Instances. Mapped to memory. - #define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ - #define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - - /* TWI_MASTER.CTRLC bit masks and bit positions */ - #define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ - #define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -@@ -5805,7 +6189,6 @@ IO Module Instances. Mapped to memory. - #define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ - #define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - +-#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +-#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ - - /* TWI_MASTER.STATUS bit masks and bit positions */ - #define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ - #define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -@@ -5832,7 +6215,6 @@ IO Module Instances. Mapped to memory. - #define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ - #define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ - +-#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - /* TWI_SLAVE.CTRLA bit masks and bit positions */ - #define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ - #define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -@@ -5859,7 +6241,6 @@ IO Module Instances. Mapped to memory. - #define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ - #define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ - - - /* TWI_SLAVE.CTRLB bit masks and bit positions */ - #define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ - #define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -@@ -5871,7 +6252,6 @@ IO Module Instances. Mapped to memory. - #define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ - #define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ - +-/* TWI_MASTER.CTRLC bit masks and bit positions */ +-#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ - - /* TWI_SLAVE.STATUS bit masks and bit positions */ - #define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ - #define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -@@ -5897,7 +6277,6 @@ IO Module Instances. Mapped to memory. - #define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ - #define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ - +-#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +-#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ - - /* TWI_SLAVE.ADDRMASK bit masks and bit positions */ - #define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ - #define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -@@ -5919,31 +6298,36 @@ IO Module Instances. Mapped to memory. - #define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ - #define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ - - - /* TWI.CTRL bit masks and bit positions */ +-/* TWI_MASTER.STATUS bit masks and bit positions */ +-#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +-#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ +- +-#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +-#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ +- +-#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +-#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +- +-#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +-#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +-#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +-#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +-#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +-#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +- +- +-/* TWI_SLAVE.CTRLA bit masks and bit positions */ +-#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +-#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +-#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ +- +-#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +-#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ +- +-#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_SLAVE.CTRLB bit masks and bit positions */ +-#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +-#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_SLAVE.STATUS bit masks and bit positions */ +-#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +-#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +-#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +-#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ +- +-#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +-#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ +- +-#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +-#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ +- +- +-/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +-#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +-#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +-#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +-#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +-#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +-#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +-#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +-#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +-#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +-#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +-#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +-#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +-#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +-#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +-#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +-#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ +- +-#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +-#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ +- +- +-/* TWI.CTRL bit masks and bit positions */ -#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ -#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ - - #define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ - #define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ - +- +-#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +-#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ +- - -/* USB - USB Module */ -+/* USB - USB */ - /* USB_EP.STATUS bit masks and bit positions */ +-/* USB_EP.STATUS bit masks and bit positions */ -#define USB_EP_STALL_bm 0x80 /* Endpoint Stall Flag bit mask. */ -#define USB_EP_STALL_bp 7 /* Endpoint Stall Flag bit position. */ -+#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -+#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ -+ -+#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -+#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ - +- -#define USB_EP_CRC_bm 0x80 /* CRC Error Flag for Isochronous Out Endpoints bit mask. */ -#define USB_EP_CRC_bp 7 /* CRC Error Flag for Isochronous Out Endpoints bit position. */ -+#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -+#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ - +- -#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint Flag for Input Endpoints bit mask. */ -#define USB_EP_UNF_bp 6 /* Underflow Enpoint Flag for Input Endpoints bit position. */ -+#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -+#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ - +- -#define USB_EP_OVF_bm 0x40 /* Underflow/Overflow Enpoint Flag for Output Endpoints bit mask. */ -#define USB_EP_OVF_bp 6 /* Underflow/Overflow Enpoint Flag for Output Endpoints bit position. */ -+#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -+#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ - +- -#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete Flag bit mask. */ -#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete Flag bit position. */ -+#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -+#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ - - #define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ - #define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ -@@ -5960,7 +6344,6 @@ IO Module Instances. Mapped to memory. - #define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ - #define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ - - - /* USB_EP.CTRL bit masks and bit positions */ - #define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ - #define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -@@ -5978,30 +6361,21 @@ IO Module Instances. Mapped to memory. - #define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ - #define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ - +-#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ +-#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ +- +-#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ +-#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ +- +-#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ +-#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ +- +-#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ +-#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ +- +-#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ +-#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ +- +- +-/* USB_EP.CTRL bit masks and bit positions */ +-#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ +-#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ +-#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ +-#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ +-#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ +-#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ +- +-#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ +-#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ +- +-#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ +-#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ +- +-#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ +-#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ +- -/* USB_EP_STALL_bm Predefined. */ -/* USB_EP_STALL_bp Predefined. */ - @@ -217017,201 +618202,266 @@ index 646e316..e53146b 100644 -/* USB_EP.CNTH bit masks and bit positions */ -#define USB_EP_ZLP_bm 0x80 /* Zero Length Packet bit mask. */ -#define USB_EP_ZLP_bp 7 /* Zero Length Packet bit position. */ -+#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -+#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ - +- -#define USB_EP_CNT_gm 0x03 /* Endpoint Byte Counter group mask. */ -#define USB_EP_CNT_gp 0 /* Endpoint Byte Counter group position. */ -#define USB_EP_CNT0_bm (1<<0) /* Endpoint Byte Counter bit 0 mask. */ -#define USB_EP_CNT0_bp 0 /* Endpoint Byte Counter bit 0 position. */ -#define USB_EP_CNT1_bm (1<<1) /* Endpoint Byte Counter bit 1 mask. */ -#define USB_EP_CNT1_bp 1 /* Endpoint Byte Counter bit 1 position. */ -+#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -+#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -+#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -+#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -+#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -+#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -+#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -+#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ - -+/* USB_EP.CNT bit masks and bit positions */ -+#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -+#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ - - /* USB.CTRLA bit masks and bit positions */ - #define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -@@ -6027,7 +6401,6 @@ IO Module Instances. Mapped to memory. - #define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ - #define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - - - /* USB.CTRLB bit masks and bit positions */ - #define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ - #define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ -@@ -6041,7 +6414,6 @@ IO Module Instances. Mapped to memory. - #define USB_ATTACH_bm 0x01 /* Attach bit mask. */ - #define USB_ATTACH_bp 0 /* Attach bit position. */ - - - /* USB.STATUS bit masks and bit positions */ - #define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ - #define USB_URESUME_bp 3 /* Upstream Resume bit position. */ -@@ -6055,7 +6427,6 @@ IO Module Instances. Mapped to memory. - #define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ - #define USB_BUSRST_bp 0 /* Bus Reset bit position. */ - +-/* USB.CTRLA bit masks and bit positions */ +-#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ +-#define USB_ENABLE_bp 7 /* USB Enable bit position. */ - - /* USB.ADDR bit masks and bit positions */ - #define USB_ADDR_gm 0x7F /* Device Address group mask. */ - #define USB_ADDR_gp 0 /* Device Address group position. */ -@@ -6074,7 +6445,6 @@ IO Module Instances. Mapped to memory. - #define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ - #define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ - +-#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ +-#define USB_SPEED_bp 6 /* Speed Select bit position. */ - - /* USB.FIFOWP bit masks and bit positions */ - #define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ - #define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -@@ -6089,7 +6459,6 @@ IO Module Instances. Mapped to memory. - #define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ - #define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ - +-#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ +-#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ - - /* USB.FIFORP bit masks and bit positions */ - #define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ - #define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -@@ -6104,7 +6473,6 @@ IO Module Instances. Mapped to memory. - #define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ - #define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ - +-#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ +-#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ - - /* USB.INTCTRLA bit masks and bit positions */ - #define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ - #define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ -@@ -6125,7 +6493,6 @@ IO Module Instances. Mapped to memory. - #define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ - #define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ - +-#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ +-#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ +-#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ +-#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ +-#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ +-#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ +-#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ +-#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ +-#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ +-#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ - - /* USB.INTCTRLB bit masks and bit positions */ - #define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ - #define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ -@@ -6133,7 +6500,6 @@ IO Module Instances. Mapped to memory. - #define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ - #define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ - - - /* USB.INTFLAGSACLR bit masks and bit positions */ - #define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ - #define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ -@@ -6159,32 +6525,30 @@ IO Module Instances. Mapped to memory. - #define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ - #define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ - +-/* USB.CTRLB bit masks and bit positions */ +-#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ +-#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ - - /* USB.INTFLAGSASET bit masks and bit positions */ +-#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ +-#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ +- +-#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ +-#define USB_GNACK_bp 1 /* Global NACK bit position. */ +- +-#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ +-#define USB_ATTACH_bp 0 /* Attach bit position. */ +- +- +-/* USB.STATUS bit masks and bit positions */ +-#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ +-#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ +- +-#define USB_RESUME_bm 0x04 /* Resume bit mask. */ +-#define USB_RESUME_bp 2 /* Resume bit position. */ +- +-#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ +-#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ +- +-#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ +-#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ +- +- +-/* USB.ADDR bit masks and bit positions */ +-#define USB_ADDR_gm 0x7F /* Device Address group mask. */ +-#define USB_ADDR_gp 0 /* Device Address group position. */ +-#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ +-#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ +-#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ +-#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ +-#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ +-#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ +-#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ +-#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ +-#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ +-#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ +-#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ +-#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ +-#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ +-#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ +- +- +-/* USB.FIFOWP bit masks and bit positions */ +-#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ +-#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ +-#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ +-#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ +-#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ +-#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ +-#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ +-#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ +-#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ +-#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ +-#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ +-#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ +- +- +-/* USB.FIFORP bit masks and bit positions */ +-#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ +-#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ +-#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ +-#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ +-#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ +-#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ +-#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ +-#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ +-#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ +-#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ +-#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ +-#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ +- +- +-/* USB.INTCTRLA bit masks and bit positions */ +-#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ +-#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ +- +-#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ +-#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ +- +-#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ +-#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ +- +-#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ +-#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ +- +-#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +-#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ +-#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +-#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +-#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +-#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ +- +- +-/* USB.INTCTRLB bit masks and bit positions */ +-#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ +-#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ +- +-#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ +-#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ +- +- +-/* USB.INTFLAGSACLR bit masks and bit positions */ +-#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ +-#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ +- +-#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ +-#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ +- +-#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ +-#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ +- +-#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ +-#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ +- +-#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ +-#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ +- +-#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ +-#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ +- +-#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ +-#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ +- +-#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ +-#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ +- +- +-/* USB.INTFLAGSASET bit masks and bit positions */ -/* USB_SOFIF_bm Predefined. */ -/* USB_SOFIF_bp Predefined. */ - -/* USB_SUSPENDIF_bm Predefined. */ -/* USB_SUSPENDIF_bp Predefined. */ -+/* USB_SOFIF Predefined. */ -+/* USB_SOFIF Predefined. */ - +- -/* USB_RESUMEIF_bm Predefined. */ -/* USB_RESUMEIF_bp Predefined. */ -+/* USB_SUSPENDIF Predefined. */ -+/* USB_SUSPENDIF Predefined. */ - +- -/* USB_RSTIF_bm Predefined. */ -/* USB_RSTIF_bp Predefined. */ -+/* USB_RESUMEIF Predefined. */ -+/* USB_RESUMEIF Predefined. */ - +- -/* USB_CRCIF_bm Predefined. */ -/* USB_CRCIF_bp Predefined. */ -+/* USB_RSTIF Predefined. */ -+/* USB_RSTIF Predefined. */ - +- -/* USB_UNFIF_bm Predefined. */ -/* USB_UNFIF_bp Predefined. */ -+/* USB_CRCIF Predefined. */ -+/* USB_CRCIF Predefined. */ - +- -/* USB_OVFIF_bm Predefined. */ -/* USB_OVFIF_bp Predefined. */ -+/* USB_UNFIF Predefined. */ -+/* USB_UNFIF Predefined. */ - +- -/* USB_STALLIF_bm Predefined. */ -/* USB_STALLIF_bp Predefined. */ -+/* USB_OVFIF Predefined. */ -+/* USB_OVFIF Predefined. */ - -+/* USB_STALLIF Predefined. */ -+/* USB_STALLIF Predefined. */ - - /* USB.INTFLAGSBCLR bit masks and bit positions */ - #define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -@@ -6193,14 +6557,12 @@ IO Module Instances. Mapped to memory. - #define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ - #define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ - - - /* USB.INTFLAGSBSET bit masks and bit positions */ +- +-/* USB.INTFLAGSBCLR bit masks and bit positions */ +-#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ +-#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ +- +-#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ +-#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ +- +- +-/* USB.INTFLAGSBSET bit masks and bit positions */ -/* USB_TRNIF_bm Predefined. */ -/* USB_TRNIF_bp Predefined. */ - -/* USB_SETUPIF_bm Predefined. */ -/* USB_SETUPIF_bp Predefined. */ -+/* USB_TRNIF Predefined. */ -+/* USB_TRNIF Predefined. */ - -+/* USB_SETUPIF Predefined. */ -+/* USB_SETUPIF Predefined. */ - - /* PORT - I/O Port Configuration */ - /* PORT.INTCTRL bit masks and bit positions */ -@@ -6218,7 +6580,6 @@ IO Module Instances. Mapped to memory. - #define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ - #define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ - - - /* PORT.INTFLAGS bit masks and bit positions */ - #define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ - #define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -@@ -6226,6 +6587,24 @@ IO Module Instances. Mapped to memory. - #define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ - #define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ - -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -+#define PORT_SPI_bp 5 /* SPI bit position. */ -+ -+#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -+#define PORT_USART0_bp 4 /* USART0 bit position. */ -+ -+#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -+#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ -+ -+#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -+#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ -+ -+#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -+#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ -+ -+#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -+#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ - - /* PORT.PIN0CTRL bit masks and bit positions */ - #define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -@@ -6252,188 +6631,96 @@ IO Module Instances. Mapped to memory. - #define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ - #define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ - - - /* PORT.PIN1CTRL bit masks and bit positions */ +-/* PORT - I/O Port Configuration */ +-/* PORT.INTCTRL bit masks and bit positions */ +-#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +-#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +-#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +-#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +-#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +-#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ +- +-#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +-#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +-#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +-#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +-#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +-#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ +- +- +-/* PORT.INTFLAGS bit masks and bit positions */ +-#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.PIN0CTRL bit masks and bit positions */ +-#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +-#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ +- +-#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +-#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ +- +-#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +-#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +-#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +-#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +-#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +-#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +-#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +-#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ +- +-#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +-#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +-#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +-#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +-#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +-#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +-#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +-#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +- +- +-/* PORT.PIN1CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - @@ -217235,19 +618485,9 @@ index 646e316..e53146b 100644 -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ - -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ - - /* PORT.PIN2CTRL bit masks and bit positions */ +- +- +-/* PORT.PIN2CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - @@ -217271,19 +618511,9 @@ index 646e316..e53146b 100644 -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ - -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ - - /* PORT.PIN3CTRL bit masks and bit positions */ +- +- +-/* PORT.PIN3CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - @@ -217307,19 +618537,9 @@ index 646e316..e53146b 100644 -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ - -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ - - /* PORT.PIN4CTRL bit masks and bit positions */ +- +- +-/* PORT.PIN4CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - @@ -217343,19 +618563,9 @@ index 646e316..e53146b 100644 -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ - -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ - - /* PORT.PIN5CTRL bit masks and bit positions */ +- +- +-/* PORT.PIN5CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - @@ -217379,19 +618589,9 @@ index 646e316..e53146b 100644 -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ - -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ - - /* PORT.PIN6CTRL bit masks and bit positions */ +- +- +-/* PORT.PIN6CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - @@ -217415,19 +618615,9 @@ index 646e316..e53146b 100644 -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ - -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ - - /* PORT.PIN7CTRL bit masks and bit positions */ +- +- +-/* PORT.PIN7CTRL bit masks and bit positions */ -/* PORT_SRLEN_bm Predefined. */ -/* PORT_SRLEN_bp Predefined. */ - @@ -217451,84 +618641,151 @@ index 646e316..e53146b 100644 -/* PORT_ISC1_bp Predefined. */ -/* PORT_ISC2_bm Predefined. */ -/* PORT_ISC2_bp Predefined. */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ - -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ - - /* TC - 16-bit Timer/Counter With PWM */ - /* TC0.CTRLA bit masks and bit positions */ -@@ -6448,7 +6735,6 @@ IO Module Instances. Mapped to memory. - #define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ - #define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - - /* TC0.CTRLB bit masks and bit positions */ - #define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ - #define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ -@@ -6471,7 +6757,6 @@ IO Module Instances. Mapped to memory. - #define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ - #define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - - - /* TC0.CTRLC bit masks and bit positions */ - #define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ - #define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ -@@ -6485,7 +6770,6 @@ IO Module Instances. Mapped to memory. - #define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ - #define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ - +-/* TC - 16-bit Timer/Counter With PWM */ +-/* TC0.CTRLA bit masks and bit positions */ +-#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - /* TC0.CTRLD bit masks and bit positions */ - #define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ - #define TC0_EVACT_gp 5 /* Event Action group position. */ -@@ -6510,11 +6794,13 @@ IO Module Instances. Mapped to memory. - #define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ - #define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - - - /* TC0.CTRLE bit masks and bit positions */ +-/* TC0.CTRLB bit masks and bit positions */ +-#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +-#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ +- +-#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +-#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ +- +-#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC0.CTRLC bit masks and bit positions */ +-#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +-#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ +- +-#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +-#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ +- +-#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC0.CTRLD bit masks and bit positions */ +-#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC0_EVACT_gp 5 /* Event Action group position. */ +-#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC0.CTRLE bit masks and bit positions */ -#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ - -+#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ - - /* TC0.INTCTRLA bit masks and bit positions */ - #define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -@@ -6531,7 +6817,6 @@ IO Module Instances. Mapped to memory. - #define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ - #define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - - /* TC0.INTCTRLB bit masks and bit positions */ - #define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ - #define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -@@ -6561,7 +6846,6 @@ IO Module Instances. Mapped to memory. - #define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ - #define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - +-/* TC0.INTCTRLA bit masks and bit positions */ +-#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ - - /* TC0.CTRLFCLR bit masks and bit positions */ - #define TC0_CMD_gm 0x0C /* Command group mask. */ - #define TC0_CMD_gp 2 /* Command group position. */ -@@ -6576,21 +6860,15 @@ IO Module Instances. Mapped to memory. - #define TC0_DIR_bm 0x01 /* Direction bit mask. */ - #define TC0_DIR_bp 0 /* Direction bit position. */ - +-#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - - /* TC0.CTRLFSET bit masks and bit positions */ +- +-/* TC0.INTCTRLB bit masks and bit positions */ +-#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +-#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +-#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +-#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +-#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +-#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ +- +-#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +-#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +-#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +-#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +-#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +-#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ +- +-#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC0.CTRLFCLR bit masks and bit positions */ +-#define TC0_CMD_gm 0x0C /* Command group mask. */ +-#define TC0_CMD_gp 2 /* Command group position. */ +-#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC0_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC0_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC0_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC0.CTRLFSET bit masks and bit positions */ -/* TC0_CMD_gm Predefined. */ -/* TC0_CMD_gp Predefined. */ -/* TC0_CMD0_bm Predefined. */ @@ -217538,120 +618795,181 @@ index 646e316..e53146b 100644 - -/* TC0_LUPD_bm Predefined. */ -/* TC0_LUPD_bp Predefined. */ -+/* TC0_CMD Predefined. */ -+/* TC0_CMD Predefined. */ - +- -/* TC0_DIR_bm Predefined. */ -/* TC0_DIR_bp Predefined. */ -+/* TC0_LUPD Predefined. */ -+/* TC0_LUPD Predefined. */ - -+/* TC0_DIR Predefined. */ -+/* TC0_DIR Predefined. */ - - /* TC0.CTRLGCLR bit masks and bit positions */ - #define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -@@ -6608,23 +6886,21 @@ IO Module Instances. Mapped to memory. - #define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ - #define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - - /* TC0.CTRLGSET bit masks and bit positions */ +- +-/* TC0.CTRLGCLR bit masks and bit positions */ +-#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +-#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ +- +-#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +-#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ +- +-#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC0.CTRLGSET bit masks and bit positions */ -/* TC0_CCDBV_bm Predefined. */ -/* TC0_CCDBV_bp Predefined. */ - -/* TC0_CCCBV_bm Predefined. */ -/* TC0_CCCBV_bp Predefined. */ -+/* TC0_CCDBV Predefined. */ -+/* TC0_CCDBV Predefined. */ - +- -/* TC0_CCBBV_bm Predefined. */ -/* TC0_CCBBV_bp Predefined. */ -+/* TC0_CCCBV Predefined. */ -+/* TC0_CCCBV Predefined. */ - +- -/* TC0_CCABV_bm Predefined. */ -/* TC0_CCABV_bp Predefined. */ -+/* TC0_CCBBV Predefined. */ -+/* TC0_CCBBV Predefined. */ - +- -/* TC0_PERBV_bm Predefined. */ -/* TC0_PERBV_bp Predefined. */ -+/* TC0_CCABV Predefined. */ -+/* TC0_CCABV Predefined. */ - -+/* TC0_PERBV Predefined. */ -+/* TC0_PERBV Predefined. */ - - /* TC0.INTFLAGS bit masks and bit positions */ - #define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -@@ -6645,7 +6921,6 @@ IO Module Instances. Mapped to memory. - #define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ - #define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - - /* TC1.CTRLA bit masks and bit positions */ - #define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ - #define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -@@ -6658,7 +6933,6 @@ IO Module Instances. Mapped to memory. - #define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ - #define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ - - - /* TC1.CTRLB bit masks and bit positions */ - #define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ - #define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -@@ -6675,7 +6949,6 @@ IO Module Instances. Mapped to memory. - #define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ - #define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ - +-/* TC0.INTFLAGS bit masks and bit positions */ +-#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +-#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ - - /* TC1.CTRLC bit masks and bit positions */ - #define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ - #define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ -@@ -6683,7 +6956,6 @@ IO Module Instances. Mapped to memory. - #define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ - #define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ - +-#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +-#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ - - /* TC1.CTRLD bit masks and bit positions */ - #define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ - #define TC1_EVACT_gp 5 /* Event Action group position. */ -@@ -6708,12 +6980,10 @@ IO Module Instances. Mapped to memory. - #define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ - #define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ - +-#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - - /* TC1.CTRLE bit masks and bit positions */ - #define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ - #define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ - +-#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - - /* TC1.INTCTRLA bit masks and bit positions */ - #define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ - #define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -@@ -6729,7 +6999,6 @@ IO Module Instances. Mapped to memory. - #define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ - #define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ - +-#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - - /* TC1.INTCTRLB bit masks and bit positions */ - #define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ - #define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -@@ -6745,7 +7014,6 @@ IO Module Instances. Mapped to memory. - #define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ - #define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ - +-#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - /* TC1.CTRLFCLR bit masks and bit positions */ - #define TC1_CMD_gm 0x0C /* Command group mask. */ - #define TC1_CMD_gp 2 /* Command group position. */ -@@ -6760,21 +7028,15 @@ IO Module Instances. Mapped to memory. - #define TC1_DIR_bm 0x01 /* Direction bit mask. */ - #define TC1_DIR_bp 0 /* Direction bit position. */ - - - /* TC1.CTRLFSET bit masks and bit positions */ +-/* TC1.CTRLA bit masks and bit positions */ +-#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC1.CTRLB bit masks and bit positions */ +-#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC1.CTRLC bit masks and bit positions */ +-#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC1.CTRLD bit masks and bit positions */ +-#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC1_EVACT_gp 5 /* Event Action group position. */ +-#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC1.CTRLE bit masks and bit positions */ +-#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC1.INTCTRLA bit masks and bit positions */ +-#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC1.INTCTRLB bit masks and bit positions */ +-#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC1.CTRLFCLR bit masks and bit positions */ +-#define TC1_CMD_gm 0x0C /* Command group mask. */ +-#define TC1_CMD_gp 2 /* Command group position. */ +-#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC1_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC1_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC1_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC1.CTRLFSET bit masks and bit positions */ -/* TC1_CMD_gm Predefined. */ -/* TC1_CMD_gp Predefined. */ -/* TC1_CMD0_bm Predefined. */ @@ -217661,282 +618979,229 @@ index 646e316..e53146b 100644 - -/* TC1_LUPD_bm Predefined. */ -/* TC1_LUPD_bp Predefined. */ -+/* TC1_CMD Predefined. */ -+/* TC1_CMD Predefined. */ - +- -/* TC1_DIR_bm Predefined. */ -/* TC1_DIR_bp Predefined. */ -+/* TC1_LUPD Predefined. */ -+/* TC1_LUPD Predefined. */ - -+/* TC1_DIR Predefined. */ -+/* TC1_DIR Predefined. */ - - /* TC1.CTRLGCLR bit masks and bit positions */ - #define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -@@ -6786,17 +7048,15 @@ IO Module Instances. Mapped to memory. - #define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ - #define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ - - - /* TC1.CTRLGSET bit masks and bit positions */ +- +-/* TC1.CTRLGCLR bit masks and bit positions */ +-#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC1.CTRLGSET bit masks and bit positions */ -/* TC1_CCBBV_bm Predefined. */ -/* TC1_CCBBV_bp Predefined. */ - -/* TC1_CCABV_bm Predefined. */ -/* TC1_CCABV_bp Predefined. */ -+/* TC1_CCBBV Predefined. */ -+/* TC1_CCBBV Predefined. */ - +- -/* TC1_PERBV_bm Predefined. */ -/* TC1_PERBV_bp Predefined. */ -+/* TC1_CCABV Predefined. */ -+/* TC1_CCABV Predefined. */ - -+/* TC1_PERBV Predefined. */ -+/* TC1_PERBV Predefined. */ - - /* TC1.INTFLAGS bit masks and bit positions */ - #define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -@@ -6811,6 +7071,154 @@ IO Module Instances. Mapped to memory. - #define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ - #define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - -+/* TC2 - 16-bit Timer/Counter type 2 */ -+/* TC2.CTRLA bit masks and bit positions */ -+#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC2.CTRLB bit masks and bit positions */ -+#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -+#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ -+ -+#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -+#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ -+ -+#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -+#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ -+ -+#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -+#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ -+ -+#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -+#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ -+ -+#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -+#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ -+ -+#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -+#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ -+ -+#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -+#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ -+ -+/* TC2.CTRLC bit masks and bit positions */ -+#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -+#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ -+ -+#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -+#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ -+ -+#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -+#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ -+ -+#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -+#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ -+ -+#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -+#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ -+ -+#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -+#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ -+ -+#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -+#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ -+ -+#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -+#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ -+ -+/* TC2.CTRLE bit masks and bit positions */ -+#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC2.INTCTRLA bit masks and bit positions */ -+#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -+#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -+#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -+#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -+#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -+#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ -+ -+#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -+#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -+#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -+#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -+#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -+#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ -+ -+/* TC2.INTCTRLB bit masks and bit positions */ -+#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -+#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -+#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -+#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -+#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -+#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -+#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -+#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -+#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -+#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -+#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -+#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -+#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -+#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -+#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -+#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -+#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -+#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -+#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -+#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -+#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ -+ -+/* TC2.CTRLF bit masks and bit positions */ -+#define TC2_CMD_gm 0x0C /* Command group mask. */ -+#define TC2_CMD_gp 2 /* Command group position. */ -+#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC2_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -+#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -+#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -+#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -+#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -+#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ -+ -+/* TC2.INTFLAGS bit masks and bit positions */ -+#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -+#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ -+ -+#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -+#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ -+ -+#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -+#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ -+ -+#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -+#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ -+ -+#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ -+ -+#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ - - /* AWEX - Timer/Counter Advanced Waveform Extension */ - /* AWEX.CTRL bit masks and bit positions */ -@@ -6832,7 +7240,6 @@ IO Module Instances. Mapped to memory. - #define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ - #define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ - - - /* AWEX.FDCTRL bit masks and bit positions */ - #define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ - #define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ -@@ -6847,7 +7254,6 @@ IO Module Instances. Mapped to memory. - #define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ - #define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ - - - /* AWEX.STATUS bit masks and bit positions */ - #define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ - #define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ -@@ -6858,6 +7264,15 @@ IO Module Instances. Mapped to memory. - #define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ - #define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ - -+/* AWEX.STATUSSET bit masks and bit positions */ -+/* AWEX_FDF Predefined. */ -+/* AWEX_FDF Predefined. */ -+ -+/* AWEX_DTHSBUFV Predefined. */ -+/* AWEX_DTHSBUFV Predefined. */ -+ -+/* AWEX_DTLSBUFV Predefined. */ -+/* AWEX_DTLSBUFV Predefined. */ - - /* HIRES - Timer/Counter High-Resolution Extension */ - /* HIRES.CTRLA bit masks and bit positions */ -@@ -6868,7 +7283,6 @@ IO Module Instances. Mapped to memory. - #define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ - #define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ - +-/* TC1.INTFLAGS bit masks and bit positions */ +-#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ - - /* USART - Universal Asynchronous Receiver-Transmitter */ - /* USART.STATUS bit masks and bit positions */ - #define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -@@ -6892,7 +7306,6 @@ IO Module Instances. Mapped to memory. - #define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ - #define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ - +-#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ - - /* USART.CTRLA bit masks and bit positions */ - #define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ - #define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -@@ -6915,7 +7328,6 @@ IO Module Instances. Mapped to memory. - #define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ - #define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ - +-#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ - - /* USART.CTRLB bit masks and bit positions */ - #define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ - #define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -@@ -6932,7 +7344,6 @@ IO Module Instances. Mapped to memory. - #define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ - #define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ - +-#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ - - /* USART.CTRLC bit masks and bit positions */ - #define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ - #define USART_CMODE_gp 6 /* Communication Mode group position. */ -@@ -6960,7 +7371,6 @@ IO Module Instances. Mapped to memory. - #define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ - #define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ - - - /* USART.BAUDCTRLA bit masks and bit positions */ - #define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ - #define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -@@ -6981,7 +7391,6 @@ IO Module Instances. Mapped to memory. - #define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ - #define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ - +-/* AWEX - Timer/Counter Advanced Waveform Extension */ +-/* AWEX.CTRL bit masks and bit positions */ +-#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +-#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ +- +-#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +-#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ +- +-#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +-#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ +- +-#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +-#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ +- +-#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +-#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ +- +-#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +-#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ +- +- +-/* AWEX.FDCTRL bit masks and bit positions */ +-#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +-#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ +- +-#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +-#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ +- +-#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +-#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +-#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +-#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +-#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +-#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ +- +- +-/* AWEX.STATUS bit masks and bit positions */ +-#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +-#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ +- +-#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +-#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ +- +-#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +-#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ +- +- +-/* HIRES - Timer/Counter High-Resolution Extension */ +-/* HIRES.CTRLA bit masks and bit positions */ +-#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +-#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +-#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +-#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +-#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +-#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ +- +- +-/* USART - Universal Asynchronous Receiver-Transmitter */ +-/* USART.STATUS bit masks and bit positions */ +-#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +-#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ +- +-#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +-#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +- +-#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +-#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +- +-#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +-#define USART_FERR_bp 4 /* Frame Error bit position. */ +- +-#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +-#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ +- +-#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +-#define USART_PERR_bp 2 /* Parity Error bit position. */ +- +-#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +-#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ +- +- +-/* USART.CTRLA bit masks and bit positions */ +-#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +-#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +-#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +-#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +-#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +-#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ +- +-#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +-#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +-#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +-#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +-#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +-#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ +- +-#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +-#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +-#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +-#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +-#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +-#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ +- +- +-/* USART.CTRLB bit masks and bit positions */ +-#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +-#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ +- +-#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +-#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ +- +-#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +-#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ +- +-#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +-#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ +- +-#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +-#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ +- +- +-/* USART.CTRLC bit masks and bit positions */ +-#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +-#define USART_CMODE_gp 6 /* Communication Mode group position. */ +-#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +-#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +-#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +-#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ +- +-#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +-#define USART_PMODE_gp 4 /* Parity Mode group position. */ +-#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +-#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +-#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +-#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +- +-#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +-#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +- +-#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +-#define USART_CHSIZE_gp 0 /* Character Size group position. */ +-#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +-#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +-#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +-#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +-#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +-#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +- +- +-/* USART.BAUDCTRLA bit masks and bit positions */ +-#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +-#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +-#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +-#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +-#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +-#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +-#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +-#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +-#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +-#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +-#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +-#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +-#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +-#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +-#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +-#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +-#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +-#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ +- +- +-/* USART.BAUDCTRLB bit masks and bit positions */ +-#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +-#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +-#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +-#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +-#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +-#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +-#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +-#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +-#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +-#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - - /* USART.BAUDCTRLB bit masks and bit positions */ - #define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ - #define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -@@ -6994,17 +7403,8 @@ IO Module Instances. Mapped to memory. - #define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ - #define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ - -/* USART_BSEL_gm Predefined. */ -/* USART_BSEL_gp Predefined. */ -/* USART_BSEL0_bm Predefined. */ @@ -217948,485 +619213,487 @@ index 646e316..e53146b 100644 -/* USART_BSEL3_bm Predefined. */ -/* USART_BSEL3_bp Predefined. */ - -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ - - /* SPI - Serial Peripheral Interface */ - /* SPI.CTRL bit masks and bit positions */ -@@ -7034,7 +7434,6 @@ IO Module Instances. Mapped to memory. - #define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ - #define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ - - - /* SPI.INTCTRL bit masks and bit positions */ - #define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ - #define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -@@ -7043,7 +7442,6 @@ IO Module Instances. Mapped to memory. - #define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ - #define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ - +-/* SPI - Serial Peripheral Interface */ +-/* SPI.CTRL bit masks and bit positions */ +-#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +-#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ - - /* SPI.STATUS bit masks and bit positions */ - #define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ - #define SPI_IF_bp 7 /* Interrupt Flag bit position. */ -@@ -7051,7 +7449,6 @@ IO Module Instances. Mapped to memory. - #define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ - #define SPI_WRCOL_bp 6 /* Write Collision bit position. */ - +-#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +-#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ +- +-#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +-#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ +- +-#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +-#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ +- +-#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +-#define SPI_MODE_gp 2 /* SPI Mode group position. */ +-#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +-#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +-#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +-#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ +- +-#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +-#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +-#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +-#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +-#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +-#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ +- +- +-/* SPI.INTCTRL bit masks and bit positions */ +-#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +-#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +-/* SPI.STATUS bit masks and bit positions */ +-#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +-#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ +- +-#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +-#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +- +- +-/* IRCOM - IR Communication Module */ +-/* IRCOM.CTRL bit masks and bit positions */ +-#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +-#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +-#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +-#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +-#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +-#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +-#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +-#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +-#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +-#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - - /* IRCOM - IR Communication Module */ - /* IRCOM.CTRL bit masks and bit positions */ - #define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -@@ -7065,34 +7462,152 @@ IO Module Instances. Mapped to memory. - #define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ - #define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ - - -/* PRESC - Prescaler */ -/* PRESC.PRESCALER bit masks and bit positions */ -#define PRESC_RESET_bm 0x01 /* Reset bit mask. */ -#define PRESC_RESET_bp 0 /* Reset bit position. */ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -+#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -+#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -+#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -+#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -+#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -+#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -+#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -+#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -+#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -+#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -+#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -+#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -+#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -+#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -+#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -+#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -+#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -+#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ -+ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -+#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -+#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* LOCKBIT - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ - - - - // Generic Port Pins - --#define PIN0_bm 0x01 -+#define PIN0_bm 0x01 - #define PIN0_bp 0 - #define PIN1_bm 0x02 - #define PIN1_bp 1 --#define PIN2_bm 0x04 -+#define PIN2_bm 0x04 - #define PIN2_bp 2 --#define PIN3_bm 0x08 -+#define PIN3_bm 0x08 - #define PIN3_bp 3 --#define PIN4_bm 0x10 -+#define PIN4_bm 0x10 - #define PIN4_bp 4 --#define PIN5_bm 0x20 -+#define PIN5_bm 0x20 - #define PIN5_bp 5 --#define PIN6_bm 0x40 -+#define PIN6_bm 0x40 - #define PIN6_bp 6 --#define PIN7_bm 0x80 -+#define PIN7_bm 0x80 - #define PIN7_bp 7 - - - /* ========== Interrupt Vector Definitions ========== */ - /* Vector 0 is the reset vector */ - -@@ -7137,17 +7652,51 @@ IO Module Instances. Mapped to memory. - /* TCC0 interrupt vectors */ - #define TCC0_OVF_vect_num 14 - #define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LUNF_vect_num 14 -+#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ - #define TCC0_ERR_vect_num 15 - #define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_HUNF_vect_num 15 -+#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ - #define TCC0_CCA_vect_num 16 - #define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPA_vect_num 16 -+#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ -+ -+/* TCC0 interrupt vectors */ - #define TCC0_CCB_vect_num 17 - #define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPB_vect_num 17 -+#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ -+ -+/* TCC0 interrupt vectors */ - #define TCC0_CCC_vect_num 18 - #define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPC_vect_num 18 -+#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ -+ -+/* TCC0 interrupt vectors */ - #define TCC0_CCD_vect_num 19 - #define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ - -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPD_vect_num 19 -+#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ -+ - /* TCC1 interrupt vectors */ - #define TCC1_OVF_vect_num 20 - #define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -@@ -7183,10 +7732,10 @@ IO Module Instances. Mapped to memory. - #define AES_INT_vect _VECTOR(31) /* AES Interrupt */ - - /* NVM interrupt vectors */ +- +- +-// Generic Port Pins +- +-#define PIN0_bm 0x01 +-#define PIN0_bp 0 +-#define PIN1_bm 0x02 +-#define PIN1_bp 1 +-#define PIN2_bm 0x04 +-#define PIN2_bp 2 +-#define PIN3_bm 0x08 +-#define PIN3_bp 3 +-#define PIN4_bm 0x10 +-#define PIN4_bp 4 +-#define PIN5_bm 0x20 +-#define PIN5_bp 5 +-#define PIN6_bm 0x40 +-#define PIN6_bp 6 +-#define PIN7_bm 0x80 +-#define PIN7_bp 7 +- +- +-/* ========== Interrupt Vector Definitions ========== */ +-/* Vector 0 is the reset vector */ +- +-/* OSC interrupt vectors */ +-#define OSC_OSCF_vect_num 1 +-#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ +- +-/* PORTC interrupt vectors */ +-#define PORTC_INT0_vect_num 2 +-#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +-#define PORTC_INT1_vect_num 3 +-#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ +- +-/* PORTR interrupt vectors */ +-#define PORTR_INT0_vect_num 4 +-#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +-#define PORTR_INT1_vect_num 5 +-#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ +- +-/* DMA interrupt vectors */ +-#define DMA_CH0_vect_num 6 +-#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +-#define DMA_CH1_vect_num 7 +-#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +-#define DMA_CH2_vect_num 8 +-#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +-#define DMA_CH3_vect_num 9 +-#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ +- +-/* RTC interrupt vectors */ +-#define RTC_OVF_vect_num 10 +-#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +-#define RTC_COMP_vect_num 11 +-#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ +- +-/* TWIC interrupt vectors */ +-#define TWIC_TWIS_vect_num 12 +-#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +-#define TWIC_TWIM_vect_num 13 +-#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ +- +-/* TCC0 interrupt vectors */ +-#define TCC0_OVF_vect_num 14 +-#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +-#define TCC0_ERR_vect_num 15 +-#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +-#define TCC0_CCA_vect_num 16 +-#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +-#define TCC0_CCB_vect_num 17 +-#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +-#define TCC0_CCC_vect_num 18 +-#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +-#define TCC0_CCD_vect_num 19 +-#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ +- +-/* TCC1 interrupt vectors */ +-#define TCC1_OVF_vect_num 20 +-#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +-#define TCC1_ERR_vect_num 21 +-#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +-#define TCC1_CCA_vect_num 22 +-#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +-#define TCC1_CCB_vect_num 23 +-#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ +- +-/* SPIC interrupt vectors */ +-#define SPIC_INT_vect_num 24 +-#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ +- +-/* USARTC0 interrupt vectors */ +-#define USARTC0_RXC_vect_num 25 +-#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +-#define USARTC0_DRE_vect_num 26 +-#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +-#define USARTC0_TXC_vect_num 27 +-#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ +- +-/* USARTC1 interrupt vectors */ +-#define USARTC1_RXC_vect_num 28 +-#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +-#define USARTC1_DRE_vect_num 29 +-#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +-#define USARTC1_TXC_vect_num 30 +-#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ +- +-/* AES interrupt vectors */ +-#define AES_INT_vect_num 31 +-#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ +- +-/* NVM interrupt vectors */ -#define NVM_SPM_vect_num 32 -#define NVM_SPM_vect _VECTOR(32) /* SPM Interrupt */ -#define NVM_EE_vect_num 33 -#define NVM_EE_vect _VECTOR(33) /* EE Interrupt */ -+#define NVM_EE_vect_num 32 -+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -+#define NVM_SPM_vect_num 33 -+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ - - /* PORTB interrupt vectors */ - #define PORTB_INT0_vect_num 34 -@@ -7227,17 +7776,51 @@ IO Module Instances. Mapped to memory. - /* TCE0 interrupt vectors */ - #define TCE0_OVF_vect_num 47 - #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LUNF_vect_num 47 -+#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ - #define TCE0_ERR_vect_num 48 - #define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_HUNF_vect_num 48 -+#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ - #define TCE0_CCA_vect_num 49 - #define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPA_vect_num 49 -+#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ -+ -+/* TCE0 interrupt vectors */ - #define TCE0_CCB_vect_num 50 - #define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPB_vect_num 50 -+#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ -+ -+/* TCE0 interrupt vectors */ - #define TCE0_CCC_vect_num 51 - #define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPC_vect_num 51 -+#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ -+ -+/* TCE0 interrupt vectors */ - #define TCE0_CCD_vect_num 52 - #define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ - -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPD_vect_num 52 -+#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ -+ - /* TCE1 interrupt vectors */ - #define TCE1_OVF_vect_num 53 - #define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ -@@ -7307,17 +7890,51 @@ IO Module Instances. Mapped to memory. - /* TCD0 interrupt vectors */ - #define TCD0_OVF_vect_num 77 - #define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LUNF_vect_num 77 -+#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ - #define TCD0_ERR_vect_num 78 - #define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_HUNF_vect_num 78 -+#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ - #define TCD0_CCA_vect_num 79 - #define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPA_vect_num 79 -+#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ -+ -+/* TCD0 interrupt vectors */ - #define TCD0_CCB_vect_num 80 - #define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPB_vect_num 80 -+#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ -+ -+/* TCD0 interrupt vectors */ - #define TCD0_CCC_vect_num 81 - #define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPC_vect_num 81 -+#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ -+ -+/* TCD0 interrupt vectors */ - #define TCD0_CCD_vect_num 82 - #define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ - -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPD_vect_num 82 -+#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ -+ - /* TCD1 interrupt vectors */ - #define TCD1_OVF_vect_num 83 - #define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -@@ -7387,17 +8004,51 @@ IO Module Instances. Mapped to memory. - /* TCF0 interrupt vectors */ - #define TCF0_OVF_vect_num 108 - #define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LUNF_vect_num 108 -+#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ - #define TCF0_ERR_vect_num 109 - #define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_HUNF_vect_num 109 -+#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ - #define TCF0_CCA_vect_num 110 - #define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPA_vect_num 110 -+#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ -+ -+/* TCF0 interrupt vectors */ - #define TCF0_CCB_vect_num 111 - #define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPB_vect_num 111 -+#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ -+ -+/* TCF0 interrupt vectors */ - #define TCF0_CCC_vect_num 112 - #define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPC_vect_num 112 -+#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ -+ -+/* TCF0 interrupt vectors */ - #define TCF0_CCD_vect_num 113 - #define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ - -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPD_vect_num 113 -+#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ -+ - /* TCF1 interrupt vectors */ - #define TCF1_OVF_vect_num 114 - #define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */ -@@ -7430,45 +8081,37 @@ IO Module Instances. Mapped to memory. - - /* USB interrupt vectors */ - #define USB_BUSEVENT_vect_num 125 +- +-/* PORTB interrupt vectors */ +-#define PORTB_INT0_vect_num 34 +-#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +-#define PORTB_INT1_vect_num 35 +-#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ +- +-/* ACB interrupt vectors */ +-#define ACB_AC0_vect_num 36 +-#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ +-#define ACB_AC1_vect_num 37 +-#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ +-#define ACB_ACW_vect_num 38 +-#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ +- +-/* ADCB interrupt vectors */ +-#define ADCB_CH0_vect_num 39 +-#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ +-#define ADCB_CH1_vect_num 40 +-#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ +-#define ADCB_CH2_vect_num 41 +-#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ +-#define ADCB_CH3_vect_num 42 +-#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ +- +-/* PORTE interrupt vectors */ +-#define PORTE_INT0_vect_num 43 +-#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +-#define PORTE_INT1_vect_num 44 +-#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ +- +-/* TWIE interrupt vectors */ +-#define TWIE_TWIS_vect_num 45 +-#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +-#define TWIE_TWIM_vect_num 46 +-#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ +- +-/* TCE0 interrupt vectors */ +-#define TCE0_OVF_vect_num 47 +-#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +-#define TCE0_ERR_vect_num 48 +-#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +-#define TCE0_CCA_vect_num 49 +-#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +-#define TCE0_CCB_vect_num 50 +-#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +-#define TCE0_CCC_vect_num 51 +-#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +-#define TCE0_CCD_vect_num 52 +-#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ +- +-/* TCE1 interrupt vectors */ +-#define TCE1_OVF_vect_num 53 +-#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ +-#define TCE1_ERR_vect_num 54 +-#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ +-#define TCE1_CCA_vect_num 55 +-#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ +-#define TCE1_CCB_vect_num 56 +-#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ +- +-/* SPIE interrupt vectors */ +-#define SPIE_INT_vect_num 57 +-#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ +- +-/* USARTE0 interrupt vectors */ +-#define USARTE0_RXC_vect_num 58 +-#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +-#define USARTE0_DRE_vect_num 59 +-#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +-#define USARTE0_TXC_vect_num 60 +-#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ +- +-/* USARTE1 interrupt vectors */ +-#define USARTE1_RXC_vect_num 61 +-#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ +-#define USARTE1_DRE_vect_num 62 +-#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ +-#define USARTE1_TXC_vect_num 63 +-#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ +- +-/* PORTD interrupt vectors */ +-#define PORTD_INT0_vect_num 64 +-#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +-#define PORTD_INT1_vect_num 65 +-#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ +- +-/* PORTA interrupt vectors */ +-#define PORTA_INT0_vect_num 66 +-#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +-#define PORTA_INT1_vect_num 67 +-#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ +- +-/* ACA interrupt vectors */ +-#define ACA_AC0_vect_num 68 +-#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +-#define ACA_AC1_vect_num 69 +-#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +-#define ACA_ACW_vect_num 70 +-#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ +- +-/* ADCA interrupt vectors */ +-#define ADCA_CH0_vect_num 71 +-#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +-#define ADCA_CH1_vect_num 72 +-#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +-#define ADCA_CH2_vect_num 73 +-#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +-#define ADCA_CH3_vect_num 74 +-#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ +- +-/* TWID interrupt vectors */ +-#define TWID_TWIS_vect_num 75 +-#define TWID_TWIS_vect _VECTOR(75) /* TWI Slave Interrupt */ +-#define TWID_TWIM_vect_num 76 +-#define TWID_TWIM_vect _VECTOR(76) /* TWI Master Interrupt */ +- +-/* TCD0 interrupt vectors */ +-#define TCD0_OVF_vect_num 77 +-#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +-#define TCD0_ERR_vect_num 78 +-#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +-#define TCD0_CCA_vect_num 79 +-#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +-#define TCD0_CCB_vect_num 80 +-#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +-#define TCD0_CCC_vect_num 81 +-#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +-#define TCD0_CCD_vect_num 82 +-#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ +- +-/* TCD1 interrupt vectors */ +-#define TCD1_OVF_vect_num 83 +-#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +-#define TCD1_ERR_vect_num 84 +-#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +-#define TCD1_CCA_vect_num 85 +-#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +-#define TCD1_CCB_vect_num 86 +-#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ +- +-/* SPID interrupt vectors */ +-#define SPID_INT_vect_num 87 +-#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ +- +-/* USARTD0 interrupt vectors */ +-#define USARTD0_RXC_vect_num 88 +-#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +-#define USARTD0_DRE_vect_num 89 +-#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +-#define USARTD0_TXC_vect_num 90 +-#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ +- +-/* USARTD1 interrupt vectors */ +-#define USARTD1_RXC_vect_num 91 +-#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +-#define USARTD1_DRE_vect_num 92 +-#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +-#define USARTD1_TXC_vect_num 93 +-#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ +- +-/* PORTQ interrupt vectors */ +-#define PORTQ_INT0_vect_num 94 +-#define PORTQ_INT0_vect _VECTOR(94) /* External Interrupt 0 */ +-#define PORTQ_INT1_vect_num 95 +-#define PORTQ_INT1_vect _VECTOR(95) /* External Interrupt 1 */ +- +-/* PORTH interrupt vectors */ +-#define PORTH_INT0_vect_num 96 +-#define PORTH_INT0_vect _VECTOR(96) /* External Interrupt 0 */ +-#define PORTH_INT1_vect_num 97 +-#define PORTH_INT1_vect _VECTOR(97) /* External Interrupt 1 */ +- +-/* PORTJ interrupt vectors */ +-#define PORTJ_INT0_vect_num 98 +-#define PORTJ_INT0_vect _VECTOR(98) /* External Interrupt 0 */ +-#define PORTJ_INT1_vect_num 99 +-#define PORTJ_INT1_vect _VECTOR(99) /* External Interrupt 1 */ +- +-/* PORTK interrupt vectors */ +-#define PORTK_INT0_vect_num 100 +-#define PORTK_INT0_vect _VECTOR(100) /* External Interrupt 0 */ +-#define PORTK_INT1_vect_num 101 +-#define PORTK_INT1_vect _VECTOR(101) /* External Interrupt 1 */ +- +-/* PORTF interrupt vectors */ +-#define PORTF_INT0_vect_num 104 +-#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +-#define PORTF_INT1_vect_num 105 +-#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ +- +-/* TWIF interrupt vectors */ +-#define TWIF_TWIS_vect_num 106 +-#define TWIF_TWIS_vect _VECTOR(106) /* TWI Slave Interrupt */ +-#define TWIF_TWIM_vect_num 107 +-#define TWIF_TWIM_vect _VECTOR(107) /* TWI Master Interrupt */ +- +-/* TCF0 interrupt vectors */ +-#define TCF0_OVF_vect_num 108 +-#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ +-#define TCF0_ERR_vect_num 109 +-#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ +-#define TCF0_CCA_vect_num 110 +-#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ +-#define TCF0_CCB_vect_num 111 +-#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ +-#define TCF0_CCC_vect_num 112 +-#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ +-#define TCF0_CCD_vect_num 113 +-#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ +- +-/* TCF1 interrupt vectors */ +-#define TCF1_OVF_vect_num 114 +-#define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */ +-#define TCF1_ERR_vect_num 115 +-#define TCF1_ERR_vect _VECTOR(115) /* Error Interrupt */ +-#define TCF1_CCA_vect_num 116 +-#define TCF1_CCA_vect _VECTOR(116) /* Compare or Capture A Interrupt */ +-#define TCF1_CCB_vect_num 117 +-#define TCF1_CCB_vect _VECTOR(117) /* Compare or Capture B Interrupt */ +- +-/* SPIF interrupt vectors */ +-#define SPIF_INT_vect_num 118 +-#define SPIF_INT_vect _VECTOR(118) /* SPI Interrupt */ +- +-/* USARTF0 interrupt vectors */ +-#define USARTF0_RXC_vect_num 119 +-#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ +-#define USARTF0_DRE_vect_num 120 +-#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ +-#define USARTF0_TXC_vect_num 121 +-#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ +- +-/* USARTF1 interrupt vectors */ +-#define USARTF1_RXC_vect_num 122 +-#define USARTF1_RXC_vect _VECTOR(122) /* Reception Complete Interrupt */ +-#define USARTF1_DRE_vect_num 123 +-#define USARTF1_DRE_vect _VECTOR(123) /* Data Register Empty Interrupt */ +-#define USARTF1_TXC_vect_num 124 +-#define USARTF1_TXC_vect _VECTOR(124) /* Transmission Complete Interrupt */ +- +-/* USB interrupt vectors */ +-#define USB_BUSEVENT_vect_num 125 -#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts and crc, underflow, overflow and stall error interrupts */ -#define USB_TRNCOMPL_vect_num 127 -#define USB_TRNCOMPL_vect _VECTOR(127) /* Transaction complete interrupt */ - -+#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -+#define USB_TRNCOMPL_vect_num 126 -+#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ - - #define _VECTOR_SIZE 4 /* Size of individual vector. */ +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ -#define _VECTORS_SIZE (128 * _VECTOR_SIZE) -+#define _VECTORS_SIZE (127 * _VECTOR_SIZE) - - - /* ========== Constants ========== */ - +- +- +-/* ========== Constants ========== */ +- -#define PROGMEM_START (0x00000) -+#define PROGMEM_START (0x0000) - #define PROGMEM_SIZE (69632) +-#define PROGMEM_SIZE (69632) -#define PROGMEM_PAGE_SIZE (512) - #define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) - +-#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) +- -#define APP_SECTION_START (0x00000) -+#define APP_SECTION_START (0x0000) - #define APP_SECTION_SIZE (65536) +-#define APP_SECTION_SIZE (65536) -#define APP_SECTION_PAGE_SIZE (512) -+#define APP_SECTION_PAGE_SIZE (256) - #define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) - +-#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) +- -#define APPTABLE_SECTION_START (0x1E000) -+#define APPTABLE_SECTION_START (0xF000) - #define APPTABLE_SECTION_SIZE (4096) +-#define APPTABLE_SECTION_SIZE (4096) -#define APPTABLE_SECTION_PAGE_SIZE (512) -+#define APPTABLE_SECTION_PAGE_SIZE (256) - #define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) - +-#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) +- -#define BOOT_SECTION_START (0x20000) -+#define BOOT_SECTION_START (0x10000) - #define BOOT_SECTION_SIZE (4096) +-#define BOOT_SECTION_SIZE (4096) -#define BOOT_SECTION_PAGE_SIZE (512) -+#define BOOT_SECTION_PAGE_SIZE (256) - #define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) - +-#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) +- -#define EEPROM_START (0x0000) -#define EEPROM_SIZE (2048) -#define EEPROM_PAGE_SIZE (32) -#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - - #define DATAMEM_START (0x0000) - #define DATAMEM_SIZE (16777216) +-#define DATAMEM_START (0x0000) +-#define DATAMEM_SIZE (16777216) -#define DATAMEM_PAGE_SIZE (0) - #define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) - - #define IO_START (0x0000) -@@ -7486,51 +8129,96 @@ IO Module Instances. Mapped to memory. - #define INTERNAL_SRAM_PAGE_SIZE (0) - #define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) - +-#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) +- +-#define IO_START (0x0000) +-#define IO_SIZE (4096) +-#define IO_PAGE_SIZE (0) +-#define IO_END (IO_START + IO_SIZE - 1) +- +-#define MAPPED_EEPROM_START (0x1000) +-#define MAPPED_EEPROM_SIZE (2048) +-#define MAPPED_EEPROM_PAGE_SIZE (0) +-#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) +- +-#define INTERNAL_SRAM_START (0x2000) +-#define INTERNAL_SRAM_SIZE (4096) +-#define INTERNAL_SRAM_PAGE_SIZE (0) +-#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) +- -#define EXTERNAL_SRAM_START (0x4000) -#define EXTERNAL_SRAM_SIZE (16760832) -#define EXTERNAL_SRAM_PAGE_SIZE (0) @@ -218441,34074 +619708,11910 @@ index 646e316..e53146b 100644 -#define LOCKBIT_SIZE (1) -#define LOCKBIT_PAGE_SIZE (0) -#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (2048) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) - - #define SIGNATURES_START (0x0000) - #define SIGNATURES_SIZE (3) - #define SIGNATURES_PAGE_SIZE (0) - #define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) - -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (6) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ - #define USER_SIGNATURES_START (0x0000) +- +-#define SIGNATURES_START (0x0000) +-#define SIGNATURES_SIZE (3) +-#define SIGNATURES_PAGE_SIZE (0) +-#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) +- +-#define USER_SIGNATURES_START (0x0000) -#define USER_SIGNATURES_SIZE (512) -#define USER_SIGNATURES_PAGE_SIZE (0) -+#define USER_SIGNATURES_SIZE (256) -+#define USER_SIGNATURES_PAGE_SIZE (256) - #define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) - - #define PROD_SIGNATURES_START (0x0000) +-#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) +- +-#define PROD_SIGNATURES_START (0x0000) -#define PROD_SIGNATURES_SIZE (52) -#define PROD_SIGNATURES_PAGE_SIZE (0) -+#define PROD_SIGNATURES_SIZE (64) -+#define PROD_SIGNATURES_PAGE_SIZE (256) - #define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) - -+#define FLASHSTART PROGMEM_START - #define FLASHEND PROGMEM_END +-#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) +- +-#define FLASHEND PROGMEM_END -#define SPM_PAGESIZE PROGMEM_PAGE_SIZE -+#define SPM_PAGESIZE 256 - #define RAMSTART INTERNAL_SRAM_START - #define RAMSIZE INTERNAL_SRAM_SIZE - #define RAMEND INTERNAL_SRAM_END +-#define RAMSTART INTERNAL_SRAM_START +-#define RAMSIZE INTERNAL_SRAM_SIZE +-#define RAMEND INTERNAL_SRAM_END -#define XRAMSTART EXTERNAL_SRAM_START -#define XRAMSIZE EXTERNAL_SRAM_SIZE -#define XRAMEND EXTERNAL_SRAM_END - #define E2END EEPROM_END - #define E2PAGESIZE EEPROM_PAGE_SIZE - - - /* ========== Fuses ========== */ +-#define E2END EEPROM_END +-#define E2PAGESIZE EEPROM_PAGE_SIZE +- +- +-/* ========== Fuses ========== */ -#define FUSE_MEMORY_SIZE 0 - -+#define FUSE_MEMORY_SIZE 6 -+ -+/* Fuse Byte 0 */ -+#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -+#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -+#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -+#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -+#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -+#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -+#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -+#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -+#define FUSE0_DEFAULT (0xFF) -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) - - /* ========== Lock Bits ========== */ - #define __LOCK_BITS_EXIST -@@ -7538,12 +8226,11 @@ IO Module Instances. Mapped to memory. - #define __BOOT_LOCK_APPLICATION_BITS_EXIST - #define __BOOT_LOCK_BOOT_BITS_EXIST - - - /* ========== Signature ========== */ - #define SIGNATURE_0 0x1E - #define SIGNATURE_1 0x96 - #define SIGNATURE_2 0x4E - - +-/* ========== Lock Bits ========== */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_BITS_EXIST +-#define __BOOT_LOCK_BOOT_BITS_EXIST +- +- +-/* ========== Signature ========== */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x96 +-#define SIGNATURE_2 0x4E +- +- -#endif /* _AVR_ATxmega64A1U_H_ */ -+#endif /* #ifdef _AVR_ATXMEGA64A1U_H_INCLUDED */ - -diff --git a/include/avr/iox64a3u.h b/include/avr/iox64a3u.h -new file mode 100644 -index 0000000..574086f ---- /dev/null -+++ b/include/avr/iox64a3u.h -@@ -0,0 +1,7628 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox64a3u.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA64A3U_H_INCLUDED -+#define _AVR_ATXMEGA64A3U_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -+#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -+#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -+#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -+#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -+#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -+#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -+#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -+#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -+#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -+#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -+#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -+#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -+#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -+#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -+#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -+#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -+#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -+#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -+#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -+#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -+#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -+#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+VPORT - Virtual Ports -+-------------------------------------------------------------------------- -+*/ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t USBCTRL; /* USB Control Register */ -+} CLK_t; -+ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t PRPB; /* Power Reduction Port B */ -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t PRPD; /* Power Reduction Port D */ -+ register8_t PRPE; /* Power Reduction Port E */ -+ register8_t PRPF; /* Power Reduction Port F */ -+} PR_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+/* USB Prescaler Division Factor */ -+typedef enum CLK_USBPSDIV_enum -+{ -+ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ -+ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ -+ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ -+ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ -+ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ -+ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -+} CLK_USBPSDIV_t; -+ -+/* USB Clock Source */ -+typedef enum CLK_USBSRC_enum -+{ -+ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ -+ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -+} CLK_USBSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control Register */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+/* 2 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC2MCREF_enum -+{ -+ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC2MCREF_t; -+ -+/* 32 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC32MCREF_enum -+{ -+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -+} OSC_RC32MCREF_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t JTAGUID; /* JTAG User ID */ -+ register8_t reserved_0x05; -+ register8_t MCUCR; /* MCU Control */ -+ register8_t ANAINIT; /* Analog Startup Delay */ -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t AWEXLOCK; /* AWEX Lock */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORTCFG - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t VPCTRLA; /* Virtual Port Control Register A */ -+ register8_t VPCTRLB; /* Virtual Port Control Register B */ -+ register8_t CLKEVOUT; /* Clock and Event Out Register */ -+ register8_t EBIOUT; /* EBI Output register */ -+ register8_t EVOUTSEL; /* Event Output Select */ -+} PORTCFG_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP02MAP_enum -+{ -+ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ -+ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ -+ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ -+ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ -+ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ -+ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ -+ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ -+ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ -+ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ -+ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ -+ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ -+ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ -+ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ -+ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ -+ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ -+ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -+} PORTCFG_VP02MAP_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP13MAP_enum -+{ -+ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ -+ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ -+ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ -+ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ -+ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ -+ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ -+ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ -+ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ -+ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ -+ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ -+ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ -+ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ -+ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ -+ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ -+ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ -+ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -+} PORTCFG_VP13MAP_t; -+ -+/* System Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ -+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ -+ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -+} PORTCFG_CLKOUT_t; -+ -+/* Peripheral Clock Output Select */ -+typedef enum PORTCFG_CLKOUTSEL_enum -+{ -+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -+} PORTCFG_CLKOUTSEL_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ -+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ -+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -+} PORTCFG_EVOUT_t; -+ -+/* Clock and Event Output Port */ -+typedef enum PORTCFG_CLKEVPIN_enum -+{ -+ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ -+ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -+} PORTCFG_CLKEVPIN_t; -+ -+/* EBI Address Output Port */ -+typedef enum PORTCFG_EBIADROUT_enum -+{ -+ PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ -+ PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ -+ PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ -+ PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ -+} PORTCFG_EBIADROUT_t; -+ -+/* EBI Chip Select Output Port */ -+typedef enum PORTCFG_EBICSOUT_enum -+{ -+ PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ -+} PORTCFG_EBICSOUT_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -+ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ -+ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ -+ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ -+ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AES - AES Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* AES Module */ -+typedef struct AES_struct -+{ -+ register8_t CTRL; /* AES Control Register */ -+ register8_t STATUS; /* AES Status Register */ -+ register8_t STATE; /* AES State Register */ -+ register8_t KEY; /* AES Key Register */ -+ register8_t INTCTRL; /* AES Interrupt Control Register */ -+} AES_t; -+ -+/* Interrupt level */ -+typedef enum AES_INTLVL_enum -+{ -+ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} AES_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ -+ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ -+ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ -+ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DMA - DMA Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* DMA Channel */ -+typedef struct DMA_CH_struct -+{ -+ register8_t CTRLA; /* Channel Control */ -+ register8_t CTRLB; /* Channel Control */ -+ register8_t ADDRCTRL; /* Address Control */ -+ register8_t TRIGSRC; /* Channel Trigger Source */ -+ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ -+ register8_t REPCNT; /* Channel Repeat Count */ -+ register8_t reserved_0x07; -+ register8_t SRCADDR0; /* Channel Source Address 0 */ -+ register8_t SRCADDR1; /* Channel Source Address 1 */ -+ register8_t SRCADDR2; /* Channel Source Address 2 */ -+ register8_t reserved_0x0B; -+ register8_t DESTADDR0; /* Channel Destination Address 0 */ -+ register8_t DESTADDR1; /* Channel Destination Address 1 */ -+ register8_t DESTADDR2; /* Channel Destination Address 2 */ -+ register8_t reserved_0x0F; -+} DMA_CH_t; -+ -+ -+/* DMA Controller */ -+typedef struct DMA_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t reserved_0x01; -+ register8_t reserved_0x02; -+ register8_t INTFLAGS; /* Transfer Interrupt Status */ -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x05; -+ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ DMA_CH_t CH0; /* DMA Channel 0 */ -+ DMA_CH_t CH1; /* DMA Channel 1 */ -+ DMA_CH_t CH2; /* DMA Channel 2 */ -+ DMA_CH_t CH3; /* DMA Channel 3 */ -+} DMA_t; -+ -+/* Burst mode */ -+typedef enum DMA_CH_BURSTLEN_enum -+{ -+ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ -+ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ -+ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ -+ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -+} DMA_CH_BURSTLEN_t; -+ -+/* Source address reload mode */ -+typedef enum DMA_CH_SRCRELOAD_enum -+{ -+ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ -+ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ -+ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ -+ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -+} DMA_CH_SRCRELOAD_t; -+ -+/* Source addressing mode */ -+typedef enum DMA_CH_SRCDIR_enum -+{ -+ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ -+ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ -+ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -+} DMA_CH_SRCDIR_t; -+ -+/* Destination adress reload mode */ -+typedef enum DMA_CH_DESTRELOAD_enum -+{ -+ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ -+ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ -+ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ -+ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -+} DMA_CH_DESTRELOAD_t; -+ -+/* Destination adressing mode */ -+typedef enum DMA_CH_DESTDIR_enum -+{ -+ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ -+ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ -+ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -+} DMA_CH_DESTDIR_t; -+ -+/* Transfer trigger source */ -+typedef enum DMA_CH_TRIGSRC_enum -+{ -+ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ -+ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ -+ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ -+ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ -+ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ -+ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ -+ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ -+ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ -+ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ -+ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ -+ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ -+ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ -+ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ -+ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ -+ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ -+ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ -+ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ -+ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ -+ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ -+ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ -+ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ -+ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ -+ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ -+ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ -+ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ -+ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ -+ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ -+ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ -+ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ -+ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ -+ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ -+ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ -+ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ -+ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ -+ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -+} DMA_CH_TRIGSRC_t; -+ -+/* Double buffering mode */ -+typedef enum DMA_DBUFMODE_enum -+{ -+ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ -+ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ -+ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ -+ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -+} DMA_DBUFMODE_t; -+ -+/* Priority mode */ -+typedef enum DMA_PRIMODE_enum -+{ -+ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ -+ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ -+ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ -+ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -+} DMA_PRIMODE_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_ERRINTLVL_enum -+{ -+ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ -+ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ -+ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -+} DMA_CH_ERRINTLVL_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_TRNINTLVL_enum -+{ -+ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ -+ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -+} DMA_CH_TRNINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ -+ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ -+ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ -+ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t CH4CTRL; /* Channel 4 Control Register */ -+ register8_t CH5CTRL; /* Channel 5 Control Register */ -+ register8_t CH6CTRL; /* Channel 6 Control Register */ -+ register8_t CH7CTRL; /* Channel 7 Control Register */ -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+} EVSYS_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ -+ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ -+ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ -+ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ -+ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ -+ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ -+ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ -+ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ -+ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ -+ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ -+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ -+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ -+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ -+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ -+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ -+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ -+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ -+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ -+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ -+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ -+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ -+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ -+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ -+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ -+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ -+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ -+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ -+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ -+ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ -+ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ -+ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ -+ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ -+ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ -+ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ -+ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ -+ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ -+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ -+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ -+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ -+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ -+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ -+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ -+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ -+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ -+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ -+ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ -+ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ -+ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ -+ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ -+ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ -+ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ -+ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ -+ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ -+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ -+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ -+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ -+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -+ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ -+ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ -+ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ -+ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ -+ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ -+ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ -+ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ -+ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -+ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ -+ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ -+ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ -+ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -+} EVSYS_CHMUX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ -+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ -+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ -+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ -+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} NVM_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t reserved_0x07; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ _WORDREGISTER(CH1RES); /* Channel 1 Result */ -+ _WORDREGISTER(CH2RES); /* Channel 2 Result */ -+ _WORDREGISTER(CH3RES); /* Channel 3 Result */ -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+ ADC_CH_t CH1; /* ADC Channel 1 */ -+ ADC_CH_t CH2; /* ADC Channel 2 */ -+ ADC_CH_t CH3; /* ADC Channel 3 */ -+} ADC_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -+ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+ ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 3) */ -+ ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Groud (Input Mode = 3) */ -+ ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Groud (Input Mode = 4) */ -+ ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 4) */ -+} ADC_CH_MUXNEG_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Current Limitation Mode */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ -+} ADC_CURRLIMIT_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Channel sweep selection */ -+typedef enum ADC_SWEEP_enum -+{ -+ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ -+ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ -+ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ -+ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -+} ADC_SWEEP_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ -+ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ -+ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ -+ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ -+ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ -+ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ -+ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ -+ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -+ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ -+ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ -+ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ -+ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* DMA request selection */ -+typedef enum ADC_DMASEL_enum -+{ -+ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ -+ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ -+ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ -+ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -+} ADC_DMASEL_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DAC - Digital/Analog Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Digital-to-Analog Converter */ -+typedef struct DAC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t EVCTRL; /* Event Input Control */ -+ register8_t reserved_0x04; -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0GAINCAL; /* Gain Calibration */ -+ register8_t CH0OFFSETCAL; /* Offset Calibration */ -+ register8_t CH1GAINCAL; /* Gain Calibration */ -+ register8_t CH1OFFSETCAL; /* Offset Calibration */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ -+ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -+} DAC_t; -+ -+/* Output channel selection */ -+typedef enum DAC_CHSEL_enum -+{ -+ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ -+ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ -+ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -+} DAC_CHSEL_t; -+ -+/* Reference voltage selection */ -+typedef enum DAC_REFSEL_enum -+{ -+ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ -+ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ -+ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ -+ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -+} DAC_REFSEL_t; -+ -+/* Event channel selection */ -+typedef enum DAC_EVSEL_enum -+{ -+ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ -+ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ -+ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ -+ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ -+ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ -+ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ -+ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ -+ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -+} DAC_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC - Real-Time Counter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Real-Time Counter */ -+typedef struct RTC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary register */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ _WORDREGISTER(CNT); /* Count Register */ -+ _WORDREGISTER(PER); /* Period Register */ -+ _WORDREGISTER(COMP); /* Compare Register */ -+} RTC_t; -+ -+/* Prescaler Factor */ -+typedef enum RTC_PRESCALER_enum -+{ -+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ -+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ -+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ -+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ -+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ -+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ -+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ -+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -+} RTC_PRESCALER_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC_COMPINTLVL_enum -+{ -+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC_OVFINTLVL_enum -+{ -+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+} TWI_t; -+ -+/* SDA Hold Time */ -+typedef enum TWI_SDAHOLD_enum -+{ -+ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ -+ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ -+ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ -+ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -+} TWI_SDAHOLD_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USB - USB -+-------------------------------------------------------------------------- -+*/ -+ -+/* USB Endpoint */ -+typedef struct USB_EP_struct -+{ -+ register8_t STATUS; /* Endpoint Status */ -+ register8_t CTRL; /* Endpoint Control */ -+ _WORDREGISTER(CNT); /* USB Endpoint Counter */ -+ _WORDREGISTER(DATAPTR); /* Data Pointer */ -+ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -+} USB_EP_t; -+ -+ -+/* Universal Serial Bus */ -+typedef struct USB_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t FIFOWP; /* FIFO Write Pointer Register */ -+ register8_t FIFORP; /* FIFO Read Pointer Register */ -+ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ -+ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ -+ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ -+ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t reserved_0x20; -+ register8_t reserved_0x21; -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t CAL0; /* Calibration Byte 0 */ -+ register8_t CAL1; /* Calibration Byte 1 */ -+} USB_t; -+ -+ -+/* USB Endpoint Table */ -+typedef struct USB_EP_TABLE_struct -+{ -+ USB_EP_t EP0OUT; /* Endpoint 0 */ -+ USB_EP_t EP0IN; /* Endpoint 0 */ -+ USB_EP_t EP1OUT; /* Endpoint 1 */ -+ USB_EP_t EP1IN; /* Endpoint 1 */ -+ USB_EP_t EP2OUT; /* Endpoint 2 */ -+ USB_EP_t EP2IN; /* Endpoint 2 */ -+ USB_EP_t EP3OUT; /* Endpoint 3 */ -+ USB_EP_t EP3IN; /* Endpoint 3 */ -+ USB_EP_t EP4OUT; /* Endpoint 4 */ -+ USB_EP_t EP4IN; /* Endpoint 4 */ -+ USB_EP_t EP5OUT; /* Endpoint 5 */ -+ USB_EP_t EP5IN; /* Endpoint 5 */ -+ USB_EP_t EP6OUT; /* Endpoint 6 */ -+ USB_EP_t EP6IN; /* Endpoint 6 */ -+ USB_EP_t EP7OUT; /* Endpoint 7 */ -+ USB_EP_t EP7IN; /* Endpoint 7 */ -+ USB_EP_t EP8OUT; /* Endpoint 8 */ -+ USB_EP_t EP8IN; /* Endpoint 8 */ -+ USB_EP_t EP9OUT; /* Endpoint 9 */ -+ USB_EP_t EP9IN; /* Endpoint 9 */ -+ USB_EP_t EP10OUT; /* Endpoint 10 */ -+ USB_EP_t EP10IN; /* Endpoint 10 */ -+ USB_EP_t EP11OUT; /* Endpoint 11 */ -+ USB_EP_t EP11IN; /* Endpoint 11 */ -+ USB_EP_t EP12OUT; /* Endpoint 12 */ -+ USB_EP_t EP12IN; /* Endpoint 12 */ -+ USB_EP_t EP13OUT; /* Endpoint 13 */ -+ USB_EP_t EP13IN; /* Endpoint 13 */ -+ USB_EP_t EP14OUT; /* Endpoint 14 */ -+ USB_EP_t EP14IN; /* Endpoint 14 */ -+ USB_EP_t EP15OUT; /* Endpoint 15 */ -+ USB_EP_t EP15IN; /* Endpoint 15 */ -+ register8_t reserved_0x100; -+ register8_t reserved_0x101; -+ register8_t reserved_0x102; -+ register8_t reserved_0x103; -+ register8_t reserved_0x104; -+ register8_t reserved_0x105; -+ register8_t reserved_0x106; -+ register8_t reserved_0x107; -+ register8_t reserved_0x108; -+ register8_t reserved_0x109; -+ register8_t reserved_0x10A; -+ register8_t reserved_0x10B; -+ register8_t reserved_0x10C; -+ register8_t reserved_0x10D; -+ register8_t reserved_0x10E; -+ register8_t reserved_0x10F; -+ register8_t FRAMENUML; /* Frame Number Low Byte */ -+ register8_t FRAMENUMH; /* Frame Number High Byte */ -+} USB_EP_TABLE_t; -+ -+/* Interrupt level */ -+typedef enum USB_INTLVL_enum -+{ -+ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} USB_INTLVL_t; -+ -+/* USB Endpoint Type */ -+typedef enum USB_EP_TYPE_enum -+{ -+ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ -+ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ -+ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ -+ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -+} USB_EP_TYPE_t; -+ -+/* USB Endpoint Buffersize */ -+typedef enum USB_EP_BUFSIZE_enum -+{ -+ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ -+ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ -+ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ -+ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ -+ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ -+ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ -+ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ -+ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -+} USB_EP_BUFSIZE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - I/O Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INT0MASK; /* Port Interrupt 0 Mask */ -+ register8_t INT1MASK; /* Port Interrupt 1 Mask */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t REMAP; /* I/O Port Pin Remap Register */ -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Port Interrupt 0 Level */ -+typedef enum PORT_INT0LVL_enum -+{ -+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INT0LVL_t; -+ -+/* Port Interrupt 1 Level */ -+typedef enum PORT_INT1LVL_enum -+{ -+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ -+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ -+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -+} PORT_INT1LVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 0 */ -+typedef struct TC0_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC0_t; -+ -+ -+/* 16-bit Timer/Counter 1 */ -+typedef struct TC1_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+} TC1_t; -+ -+/* Clock Selection */ -+typedef enum TC_CLKSEL_enum -+{ -+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC_CLKSEL_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC_WGMODE_enum -+{ -+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC_WGMODE_t; -+ -+/* Byte Mode */ -+typedef enum TC_BYTEM_enum -+{ -+ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ -+ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -+} TC_BYTEM_t; -+ -+/* Event Action */ -+typedef enum TC_EVACT_enum -+{ -+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ -+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ -+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ -+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ -+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ -+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC_EVSEL_enum -+{ -+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC_EVSEL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC_ERRINTLVL_enum -+{ -+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC_OVFINTLVL_enum -+{ -+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_OVFINTLVL_t; -+ -+/* Compare or Capture D Interrupt Level */ -+typedef enum TC_CCDINTLVL_enum -+{ -+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC_CCDINTLVL_t; -+ -+/* Compare or Capture C Interrupt Level */ -+typedef enum TC_CCCINTLVL_enum -+{ -+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC_CCCINTLVL_t; -+ -+/* Compare or Capture B Interrupt Level */ -+typedef enum TC_CCBINTLVL_enum -+{ -+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_CCBINTLVL_t; -+ -+/* Compare or Capture A Interrupt Level */ -+typedef enum TC_CCAINTLVL_enum -+{ -+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_CCAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC_CMD_enum -+{ -+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC2 - 16-bit Timer/Counter type 2 -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter type 2 */ -+typedef struct TC2_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t reserved_0x03; -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t reserved_0x08; -+ register8_t CTRLF; /* Control Register F */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t LCNT; /* Low Byte Count */ -+ register8_t HCNT; /* High Byte Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t LPER; /* Low Byte Period */ -+ register8_t HPER; /* High Byte Period */ -+ register8_t LCMPA; /* Low Byte Compare A */ -+ register8_t HCMPA; /* High Byte Compare A */ -+ register8_t LCMPB; /* Low Byte Compare B */ -+ register8_t HCMPB; /* High Byte Compare B */ -+ register8_t LCMPC; /* Low Byte Compare C */ -+ register8_t HCMPC; /* High Byte Compare C */ -+ register8_t LCMPD; /* Low Byte Compare D */ -+ register8_t HCMPD; /* High Byte Compare D */ -+} TC2_t; -+ -+/* Clock Selection */ -+typedef enum TC2_CLKSEL_enum -+{ -+ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC2_CLKSEL_t; -+ -+/* Byte Mode */ -+typedef enum TC2_BYTEM_enum -+{ -+ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ -+ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -+} TC2_BYTEM_t; -+ -+/* High Byte Underflow Interrupt Level */ -+typedef enum TC2_HUNFINTLVL_enum -+{ -+ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_HUNFINTLVL_t; -+ -+/* Low Byte Underflow Interrupt Level */ -+typedef enum TC2_LUNFINTLVL_enum -+{ -+ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LUNFINTLVL_t; -+ -+/* Low Byte Compare D Interrupt Level */ -+typedef enum TC2_LCMPDINTLVL_enum -+{ -+ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC2_LCMPDINTLVL_t; -+ -+/* Low Byte Compare C Interrupt Level */ -+typedef enum TC2_LCMPCINTLVL_enum -+{ -+ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC2_LCMPCINTLVL_t; -+ -+/* Low Byte Compare B Interrupt Level */ -+typedef enum TC2_LCMPBINTLVL_enum -+{ -+ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_LCMPBINTLVL_t; -+ -+/* Low Byte Compare A Interrupt Level */ -+typedef enum TC2_LCMPAINTLVL_enum -+{ -+ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LCMPAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMD_enum -+{ -+ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC2_CMD_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMDEN_enum -+{ -+ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ -+ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ -+ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -+} TC2_CMDEN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AWEX - Timer/Counter Advanced Waveform Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Advanced Waveform Extension */ -+typedef struct AWEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t FDEMASK; /* Fault Detection Event Mask */ -+ register8_t FDCTRL; /* Fault Detection Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t STATUSSET; /* Status Set Register */ -+ register8_t DTBOTH; /* Dead Time Both Sides */ -+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ -+ register8_t DTLS; /* Dead Time Low Side */ -+ register8_t DTHS; /* Dead Time High Side */ -+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ -+ register8_t DTHSBUF; /* Dead Time High Side Buffer */ -+ register8_t OUTOVEN; /* Output Override Enable */ -+} AWEX_t; -+ -+/* Fault Detect Action */ -+typedef enum AWEX_FDACT_enum -+{ -+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ -+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -+} AWEX_FDACT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+HIRES - Timer/Counter High-Resolution Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register */ -+} HIRES_t; -+ -+/* High Resolution Enable */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ -+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ -+ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ -+ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ -+ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -+} IRDA_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t FUSEBYTE0; /* JTAG User ID */ -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+} NVM_FUSES_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* Timer Oscillator pin location */ -+typedef enum TOSCSEL_enum -+{ -+ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ -+ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -+} TOSCSEL_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -+} BOD_t; -+ -+/* BOD operation */ -+typedef enum BODACT_enum -+{ -+ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BODACT_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WDP_enum -+{ -+ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ -+ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ -+ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ -+ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ -+ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ -+ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ -+ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ -+ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ -+ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ -+ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ -+ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -+} WDP_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LOCKBIT - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ -+ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t USBCAL0; /* USB Calibration Byte 0 */ -+ register8_t USBCAL1; /* USB Calibration Byte 1 */ -+ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ -+ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ -+ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ -+ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ -+ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ -+ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ -+ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ -+ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ -+ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ -+ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+ register8_t reserved_0x40; -+ register8_t reserved_0x41; -+ register8_t reserved_0x42; -+ register8_t reserved_0x43; -+ register8_t reserved_0x44; -+ register8_t reserved_0x45; -+ register8_t reserved_0x46; -+ register8_t reserved_0x47; -+} NVM_PROD_SIGNATURES_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define AES (*(AES_t *) 0x00C0) /* AES Module */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ -+#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ -+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -+#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -+#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -+#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -+#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -+#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -+#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ -+#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ -+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -+#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -+#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -+#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ -+#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ -+#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ -+#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ -+#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -+#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ -+#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ -+#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -+#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -+#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -+#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -+#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -+#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -+#define GPIO_GPIORA _SFR_MEM8(0x000A) -+#define GPIO_GPIORB _SFR_MEM8(0x000B) -+#define GPIO_GPIORC _SFR_MEM8(0x000C) -+#define GPIO_GPIORD _SFR_MEM8(0x000D) -+#define GPIO_GPIORE _SFR_MEM8(0x000E) -+#define GPIO_GPIORF _SFR_MEM8(0x000F) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+#define GPIO_GPIO4 _SFR_MEM8(0x0004) -+#define GPIO_GPIO5 _SFR_MEM8(0x0005) -+#define GPIO_GPIO6 _SFR_MEM8(0x0006) -+#define GPIO_GPIO7 _SFR_MEM8(0x0007) -+#define GPIO_GPIO8 _SFR_MEM8(0x0008) -+#define GPIO_GPIO9 _SFR_MEM8(0x0009) -+#define GPIO_GPIOA _SFR_MEM8(0x000A) -+#define GPIO_GPIOB _SFR_MEM8(0x000B) -+#define GPIO_GPIOC _SFR_MEM8(0x000C) -+#define GPIO_GPIOD _SFR_MEM8(0x000D) -+#define GPIO_GPIOE _SFR_MEM8(0x000E) -+#define GPIO_GPIOF _SFR_MEM8(0x000F) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -+#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -+#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -+#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -+#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -+#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -+#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) -+#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) -+#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -+#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) -+#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) -+#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+#define CLK_USBCTRL _SFR_MEM8(0x0044) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* DFLL - DFLL */ -+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -+#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -+#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPB _SFR_MEM8(0x0072) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPD _SFR_MEM8(0x0074) -+#define PR_PRPE _SFR_MEM8(0x0075) -+#define PR_PRPF _SFR_MEM8(0x0076) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_JTAGUID _SFR_MEM8(0x0094) -+#define MCU_MCUCR _SFR_MEM8(0x0096) -+#define MCU_ANAINIT _SFR_MEM8(0x0097) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_AWEXLOCK _SFR_MEM8(0x0099) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) -+#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) -+ -+/* AES - AES Module */ -+#define AES_CTRL _SFR_MEM8(0x00C0) -+#define AES_STATUS _SFR_MEM8(0x00C1) -+#define AES_STATE _SFR_MEM8(0x00C2) -+#define AES_KEY _SFR_MEM8(0x00C3) -+#define AES_INTCTRL _SFR_MEM8(0x00C4) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* DMA - DMA Controller */ -+#define DMA_CTRL _SFR_MEM8(0x0100) -+#define DMA_INTFLAGS _SFR_MEM8(0x0103) -+#define DMA_STATUS _SFR_MEM8(0x0104) -+#define DMA_TEMP _SFR_MEM16(0x0106) -+#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -+#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -+#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -+#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -+#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -+#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -+#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -+#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -+#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -+#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -+#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -+#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -+#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -+#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -+#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -+#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -+#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -+#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -+#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -+#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -+#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -+#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -+#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -+#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -+#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -+#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -+#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -+#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -+#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -+#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -+#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -+#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -+#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -+#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -+#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -+#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -+#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -+#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -+#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -+#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -+#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -+#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -+#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -+#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -+#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -+#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -+#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -+#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -+#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -+#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -+#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -+#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -+#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -+#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCA_CTRLA _SFR_MEM8(0x0200) -+#define ADCA_CTRLB _SFR_MEM8(0x0201) -+#define ADCA_REFCTRL _SFR_MEM8(0x0202) -+#define ADCA_EVCTRL _SFR_MEM8(0x0203) -+#define ADCA_PRESCALER _SFR_MEM8(0x0204) -+#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -+#define ADCA_TEMP _SFR_MEM8(0x0207) -+#define ADCA_CAL _SFR_MEM16(0x020C) -+#define ADCA_CH0RES _SFR_MEM16(0x0210) -+#define ADCA_CH1RES _SFR_MEM16(0x0212) -+#define ADCA_CH2RES _SFR_MEM16(0x0214) -+#define ADCA_CH3RES _SFR_MEM16(0x0216) -+#define ADCA_CMP _SFR_MEM16(0x0218) -+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -+#define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -+#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -+#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -+#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -+#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -+#define ADCA_CH1_RES _SFR_MEM16(0x022C) -+#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) -+#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -+#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -+#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -+#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -+#define ADCA_CH2_RES _SFR_MEM16(0x0234) -+#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) -+#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -+#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -+#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -+#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -+#define ADCA_CH3_RES _SFR_MEM16(0x023C) -+#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCB_CTRLA _SFR_MEM8(0x0240) -+#define ADCB_CTRLB _SFR_MEM8(0x0241) -+#define ADCB_REFCTRL _SFR_MEM8(0x0242) -+#define ADCB_EVCTRL _SFR_MEM8(0x0243) -+#define ADCB_PRESCALER _SFR_MEM8(0x0244) -+#define ADCB_INTFLAGS _SFR_MEM8(0x0246) -+#define ADCB_TEMP _SFR_MEM8(0x0247) -+#define ADCB_CAL _SFR_MEM16(0x024C) -+#define ADCB_CH0RES _SFR_MEM16(0x0250) -+#define ADCB_CH1RES _SFR_MEM16(0x0252) -+#define ADCB_CH2RES _SFR_MEM16(0x0254) -+#define ADCB_CH3RES _SFR_MEM16(0x0256) -+#define ADCB_CMP _SFR_MEM16(0x0258) -+#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) -+#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) -+#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) -+#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) -+#define ADCB_CH0_RES _SFR_MEM16(0x0264) -+#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) -+#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) -+#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) -+#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) -+#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) -+#define ADCB_CH1_RES _SFR_MEM16(0x026C) -+#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) -+#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) -+#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) -+#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) -+#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) -+#define ADCB_CH2_RES _SFR_MEM16(0x0274) -+#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) -+#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) -+#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) -+#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) -+#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) -+#define ADCB_CH3_RES _SFR_MEM16(0x027C) -+#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) -+ -+/* DAC - Digital-to-Analog Converter */ -+#define DACB_CTRLA _SFR_MEM8(0x0320) -+#define DACB_CTRLB _SFR_MEM8(0x0321) -+#define DACB_CTRLC _SFR_MEM8(0x0322) -+#define DACB_EVCTRL _SFR_MEM8(0x0323) -+#define DACB_STATUS _SFR_MEM8(0x0325) -+#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) -+#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) -+#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) -+#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) -+#define DACB_CH0DATA _SFR_MEM16(0x0338) -+#define DACB_CH1DATA _SFR_MEM16(0x033A) -+ -+/* AC - Analog Comparator */ -+#define ACA_AC0CTRL _SFR_MEM8(0x0380) -+#define ACA_AC1CTRL _SFR_MEM8(0x0381) -+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -+#define ACA_CTRLA _SFR_MEM8(0x0384) -+#define ACA_CTRLB _SFR_MEM8(0x0385) -+#define ACA_WINCTRL _SFR_MEM8(0x0386) -+#define ACA_STATUS _SFR_MEM8(0x0387) -+ -+/* AC - Analog Comparator */ -+#define ACB_AC0CTRL _SFR_MEM8(0x0390) -+#define ACB_AC1CTRL _SFR_MEM8(0x0391) -+#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -+#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -+#define ACB_CTRLA _SFR_MEM8(0x0394) -+#define ACB_CTRLB _SFR_MEM8(0x0395) -+#define ACB_WINCTRL _SFR_MEM8(0x0396) -+#define ACB_STATUS _SFR_MEM8(0x0397) -+ -+/* RTC - Real-Time Counter */ -+#define RTC_CTRL _SFR_MEM8(0x0400) -+#define RTC_STATUS _SFR_MEM8(0x0401) -+#define RTC_INTCTRL _SFR_MEM8(0x0402) -+#define RTC_INTFLAGS _SFR_MEM8(0x0403) -+#define RTC_TEMP _SFR_MEM8(0x0404) -+#define RTC_CNT _SFR_MEM16(0x0408) -+#define RTC_PER _SFR_MEM16(0x040A) -+#define RTC_COMP _SFR_MEM16(0x040C) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIE_CTRL _SFR_MEM8(0x04A0) -+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -+ -+/* USB - Universal Serial Bus */ -+#define USB_CTRLA _SFR_MEM8(0x04C0) -+#define USB_CTRLB _SFR_MEM8(0x04C1) -+#define USB_STATUS _SFR_MEM8(0x04C2) -+#define USB_ADDR _SFR_MEM8(0x04C3) -+#define USB_FIFOWP _SFR_MEM8(0x04C4) -+#define USB_FIFORP _SFR_MEM8(0x04C5) -+#define USB_EPPTR _SFR_MEM16(0x04C6) -+#define USB_INTCTRLA _SFR_MEM8(0x04C8) -+#define USB_INTCTRLB _SFR_MEM8(0x04C9) -+#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -+#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -+#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -+#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -+#define USB_CAL0 _SFR_MEM8(0x04FA) -+#define USB_CAL1 _SFR_MEM8(0x04FB) -+ -+/* PORT - I/O Ports */ -+#define PORTA_DIR _SFR_MEM8(0x0600) -+#define PORTA_DIRSET _SFR_MEM8(0x0601) -+#define PORTA_DIRCLR _SFR_MEM8(0x0602) -+#define PORTA_DIRTGL _SFR_MEM8(0x0603) -+#define PORTA_OUT _SFR_MEM8(0x0604) -+#define PORTA_OUTSET _SFR_MEM8(0x0605) -+#define PORTA_OUTCLR _SFR_MEM8(0x0606) -+#define PORTA_OUTTGL _SFR_MEM8(0x0607) -+#define PORTA_IN _SFR_MEM8(0x0608) -+#define PORTA_INTCTRL _SFR_MEM8(0x0609) -+#define PORTA_INT0MASK _SFR_MEM8(0x060A) -+#define PORTA_INT1MASK _SFR_MEM8(0x060B) -+#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_REMAP _SFR_MEM8(0x060E) -+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -+ -+/* PORT - I/O Ports */ -+#define PORTB_DIR _SFR_MEM8(0x0620) -+#define PORTB_DIRSET _SFR_MEM8(0x0621) -+#define PORTB_DIRCLR _SFR_MEM8(0x0622) -+#define PORTB_DIRTGL _SFR_MEM8(0x0623) -+#define PORTB_OUT _SFR_MEM8(0x0624) -+#define PORTB_OUTSET _SFR_MEM8(0x0625) -+#define PORTB_OUTCLR _SFR_MEM8(0x0626) -+#define PORTB_OUTTGL _SFR_MEM8(0x0627) -+#define PORTB_IN _SFR_MEM8(0x0628) -+#define PORTB_INTCTRL _SFR_MEM8(0x0629) -+#define PORTB_INT0MASK _SFR_MEM8(0x062A) -+#define PORTB_INT1MASK _SFR_MEM8(0x062B) -+#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -+#define PORTB_REMAP _SFR_MEM8(0x062E) -+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INT0MASK _SFR_MEM8(0x064A) -+#define PORTC_INT1MASK _SFR_MEM8(0x064B) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INT0MASK _SFR_MEM8(0x066A) -+#define PORTD_INT1MASK _SFR_MEM8(0x066B) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTE_DIR _SFR_MEM8(0x0680) -+#define PORTE_DIRSET _SFR_MEM8(0x0681) -+#define PORTE_DIRCLR _SFR_MEM8(0x0682) -+#define PORTE_DIRTGL _SFR_MEM8(0x0683) -+#define PORTE_OUT _SFR_MEM8(0x0684) -+#define PORTE_OUTSET _SFR_MEM8(0x0685) -+#define PORTE_OUTCLR _SFR_MEM8(0x0686) -+#define PORTE_OUTTGL _SFR_MEM8(0x0687) -+#define PORTE_IN _SFR_MEM8(0x0688) -+#define PORTE_INTCTRL _SFR_MEM8(0x0689) -+#define PORTE_INT0MASK _SFR_MEM8(0x068A) -+#define PORTE_INT1MASK _SFR_MEM8(0x068B) -+#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -+#define PORTE_REMAP _SFR_MEM8(0x068E) -+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) -+ -+/* PORT - I/O Ports */ -+#define PORTF_DIR _SFR_MEM8(0x06A0) -+#define PORTF_DIRSET _SFR_MEM8(0x06A1) -+#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -+#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -+#define PORTF_OUT _SFR_MEM8(0x06A4) -+#define PORTF_OUTSET _SFR_MEM8(0x06A5) -+#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -+#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -+#define PORTF_IN _SFR_MEM8(0x06A8) -+#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -+#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -+#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -+#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -+#define PORTF_REMAP _SFR_MEM8(0x06AE) -+#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -+#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -+#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -+#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -+#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -+#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -+#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -+#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -+#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCC0_CTRLA _SFR_MEM8(0x0800) -+#define TCC0_CTRLB _SFR_MEM8(0x0801) -+#define TCC0_CTRLC _SFR_MEM8(0x0802) -+#define TCC0_CTRLD _SFR_MEM8(0x0803) -+#define TCC0_CTRLE _SFR_MEM8(0x0804) -+#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -+#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -+#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -+#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC0_TEMP _SFR_MEM8(0x080F) -+#define TCC0_CNT _SFR_MEM16(0x0820) -+#define TCC0_PER _SFR_MEM16(0x0826) -+#define TCC0_CCA _SFR_MEM16(0x0828) -+#define TCC0_CCB _SFR_MEM16(0x082A) -+#define TCC0_CCC _SFR_MEM16(0x082C) -+#define TCC0_CCD _SFR_MEM16(0x082E) -+#define TCC0_PERBUF _SFR_MEM16(0x0836) -+#define TCC0_CCABUF _SFR_MEM16(0x0838) -+#define TCC0_CCBBUF _SFR_MEM16(0x083A) -+#define TCC0_CCCBUF _SFR_MEM16(0x083C) -+#define TCC0_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCC2_CTRLA _SFR_MEM8(0x0800) -+#define TCC2_CTRLB _SFR_MEM8(0x0801) -+#define TCC2_CTRLC _SFR_MEM8(0x0802) -+#define TCC2_CTRLE _SFR_MEM8(0x0804) -+#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC2_CTRLF _SFR_MEM8(0x0809) -+#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC2_LCNT _SFR_MEM8(0x0820) -+#define TCC2_HCNT _SFR_MEM8(0x0821) -+#define TCC2_LPER _SFR_MEM8(0x0826) -+#define TCC2_HPER _SFR_MEM8(0x0827) -+#define TCC2_LCMPA _SFR_MEM8(0x0828) -+#define TCC2_HCMPA _SFR_MEM8(0x0829) -+#define TCC2_LCMPB _SFR_MEM8(0x082A) -+#define TCC2_HCMPB _SFR_MEM8(0x082B) -+#define TCC2_LCMPC _SFR_MEM8(0x082C) -+#define TCC2_HCMPC _SFR_MEM8(0x082D) -+#define TCC2_LCMPD _SFR_MEM8(0x082E) -+#define TCC2_HCMPD _SFR_MEM8(0x082F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCC1_CTRLA _SFR_MEM8(0x0840) -+#define TCC1_CTRLB _SFR_MEM8(0x0841) -+#define TCC1_CTRLC _SFR_MEM8(0x0842) -+#define TCC1_CTRLD _SFR_MEM8(0x0843) -+#define TCC1_CTRLE _SFR_MEM8(0x0844) -+#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -+#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -+#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -+#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC1_TEMP _SFR_MEM8(0x084F) -+#define TCC1_CNT _SFR_MEM16(0x0860) -+#define TCC1_PER _SFR_MEM16(0x0866) -+#define TCC1_CCA _SFR_MEM16(0x0868) -+#define TCC1_CCB _SFR_MEM16(0x086A) -+#define TCC1_PERBUF _SFR_MEM16(0x0876) -+#define TCC1_CCABUF _SFR_MEM16(0x0878) -+#define TCC1_CCBBUF _SFR_MEM16(0x087A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXC_CTRL _SFR_MEM8(0x0880) -+#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -+#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -+#define AWEXC_STATUS _SFR_MEM8(0x0884) -+#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -+#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -+#define AWEXC_DTLS _SFR_MEM8(0x0888) -+#define AWEXC_DTHS _SFR_MEM8(0x0889) -+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x0890) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08A0) -+#define USARTC0_STATUS _SFR_MEM8(0x08A1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -+#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -+#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC1_DATA _SFR_MEM8(0x08B0) -+#define USARTC1_STATUS _SFR_MEM8(0x08B1) -+#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -+#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -+#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -+#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -+#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIC_CTRL _SFR_MEM8(0x08C0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -+#define SPIC_STATUS _SFR_MEM8(0x08C2) -+#define SPIC_DATA _SFR_MEM8(0x08C3) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCD0_CTRLA _SFR_MEM8(0x0900) -+#define TCD0_CTRLB _SFR_MEM8(0x0901) -+#define TCD0_CTRLC _SFR_MEM8(0x0902) -+#define TCD0_CTRLD _SFR_MEM8(0x0903) -+#define TCD0_CTRLE _SFR_MEM8(0x0904) -+#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -+#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -+#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -+#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -+#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD0_TEMP _SFR_MEM8(0x090F) -+#define TCD0_CNT _SFR_MEM16(0x0920) -+#define TCD0_PER _SFR_MEM16(0x0926) -+#define TCD0_CCA _SFR_MEM16(0x0928) -+#define TCD0_CCB _SFR_MEM16(0x092A) -+#define TCD0_CCC _SFR_MEM16(0x092C) -+#define TCD0_CCD _SFR_MEM16(0x092E) -+#define TCD0_PERBUF _SFR_MEM16(0x0936) -+#define TCD0_CCABUF _SFR_MEM16(0x0938) -+#define TCD0_CCBBUF _SFR_MEM16(0x093A) -+#define TCD0_CCCBUF _SFR_MEM16(0x093C) -+#define TCD0_CCDBUF _SFR_MEM16(0x093E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCD2_CTRLA _SFR_MEM8(0x0900) -+#define TCD2_CTRLB _SFR_MEM8(0x0901) -+#define TCD2_CTRLC _SFR_MEM8(0x0902) -+#define TCD2_CTRLE _SFR_MEM8(0x0904) -+#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD2_CTRLF _SFR_MEM8(0x0909) -+#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD2_LCNT _SFR_MEM8(0x0920) -+#define TCD2_HCNT _SFR_MEM8(0x0921) -+#define TCD2_LPER _SFR_MEM8(0x0926) -+#define TCD2_HPER _SFR_MEM8(0x0927) -+#define TCD2_LCMPA _SFR_MEM8(0x0928) -+#define TCD2_HCMPA _SFR_MEM8(0x0929) -+#define TCD2_LCMPB _SFR_MEM8(0x092A) -+#define TCD2_HCMPB _SFR_MEM8(0x092B) -+#define TCD2_LCMPC _SFR_MEM8(0x092C) -+#define TCD2_HCMPC _SFR_MEM8(0x092D) -+#define TCD2_LCMPD _SFR_MEM8(0x092E) -+#define TCD2_HCMPD _SFR_MEM8(0x092F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCD1_CTRLA _SFR_MEM8(0x0940) -+#define TCD1_CTRLB _SFR_MEM8(0x0941) -+#define TCD1_CTRLC _SFR_MEM8(0x0942) -+#define TCD1_CTRLD _SFR_MEM8(0x0943) -+#define TCD1_CTRLE _SFR_MEM8(0x0944) -+#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -+#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -+#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -+#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -+#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -+#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -+#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -+#define TCD1_TEMP _SFR_MEM8(0x094F) -+#define TCD1_CNT _SFR_MEM16(0x0960) -+#define TCD1_PER _SFR_MEM16(0x0966) -+#define TCD1_CCA _SFR_MEM16(0x0968) -+#define TCD1_CCB _SFR_MEM16(0x096A) -+#define TCD1_PERBUF _SFR_MEM16(0x0976) -+#define TCD1_CCABUF _SFR_MEM16(0x0978) -+#define TCD1_CCBBUF _SFR_MEM16(0x097A) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESD_CTRLA _SFR_MEM8(0x0990) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD0_DATA _SFR_MEM8(0x09A0) -+#define USARTD0_STATUS _SFR_MEM8(0x09A1) -+#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -+#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -+#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD1_DATA _SFR_MEM8(0x09B0) -+#define USARTD1_STATUS _SFR_MEM8(0x09B1) -+#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -+#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -+#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -+#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -+#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPID_CTRL _SFR_MEM8(0x09C0) -+#define SPID_INTCTRL _SFR_MEM8(0x09C1) -+#define SPID_STATUS _SFR_MEM8(0x09C2) -+#define SPID_DATA _SFR_MEM8(0x09C3) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCE0_CTRLA _SFR_MEM8(0x0A00) -+#define TCE0_CTRLB _SFR_MEM8(0x0A01) -+#define TCE0_CTRLC _SFR_MEM8(0x0A02) -+#define TCE0_CTRLD _SFR_MEM8(0x0A03) -+#define TCE0_CTRLE _SFR_MEM8(0x0A04) -+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE0_TEMP _SFR_MEM8(0x0A0F) -+#define TCE0_CNT _SFR_MEM16(0x0A20) -+#define TCE0_PER _SFR_MEM16(0x0A26) -+#define TCE0_CCA _SFR_MEM16(0x0A28) -+#define TCE0_CCB _SFR_MEM16(0x0A2A) -+#define TCE0_CCC _SFR_MEM16(0x0A2C) -+#define TCE0_CCD _SFR_MEM16(0x0A2E) -+#define TCE0_PERBUF _SFR_MEM16(0x0A36) -+#define TCE0_CCABUF _SFR_MEM16(0x0A38) -+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCE2_CTRLA _SFR_MEM8(0x0A00) -+#define TCE2_CTRLB _SFR_MEM8(0x0A01) -+#define TCE2_CTRLC _SFR_MEM8(0x0A02) -+#define TCE2_CTRLE _SFR_MEM8(0x0A04) -+#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE2_CTRLF _SFR_MEM8(0x0A09) -+#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE2_LCNT _SFR_MEM8(0x0A20) -+#define TCE2_HCNT _SFR_MEM8(0x0A21) -+#define TCE2_LPER _SFR_MEM8(0x0A26) -+#define TCE2_HPER _SFR_MEM8(0x0A27) -+#define TCE2_LCMPA _SFR_MEM8(0x0A28) -+#define TCE2_HCMPA _SFR_MEM8(0x0A29) -+#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -+#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -+#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -+#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -+#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -+#define TCE2_HCMPD _SFR_MEM8(0x0A2F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCE1_CTRLA _SFR_MEM8(0x0A40) -+#define TCE1_CTRLB _SFR_MEM8(0x0A41) -+#define TCE1_CTRLC _SFR_MEM8(0x0A42) -+#define TCE1_CTRLD _SFR_MEM8(0x0A43) -+#define TCE1_CTRLE _SFR_MEM8(0x0A44) -+#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) -+#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) -+#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) -+#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) -+#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) -+#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) -+#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) -+#define TCE1_TEMP _SFR_MEM8(0x0A4F) -+#define TCE1_CNT _SFR_MEM16(0x0A60) -+#define TCE1_PER _SFR_MEM16(0x0A66) -+#define TCE1_CCA _SFR_MEM16(0x0A68) -+#define TCE1_CCB _SFR_MEM16(0x0A6A) -+#define TCE1_PERBUF _SFR_MEM16(0x0A76) -+#define TCE1_CCABUF _SFR_MEM16(0x0A78) -+#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXE_CTRL _SFR_MEM8(0x0A80) -+#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) -+#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) -+#define AWEXE_STATUS _SFR_MEM8(0x0A84) -+#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) -+#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) -+#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) -+#define AWEXE_DTLS _SFR_MEM8(0x0A88) -+#define AWEXE_DTHS _SFR_MEM8(0x0A89) -+#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) -+#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) -+#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESE_CTRLA _SFR_MEM8(0x0A90) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE0_DATA _SFR_MEM8(0x0AA0) -+#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -+#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -+#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -+#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -+#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -+#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE1_DATA _SFR_MEM8(0x0AB0) -+#define USARTE1_STATUS _SFR_MEM8(0x0AB1) -+#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) -+#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) -+#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) -+#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) -+#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIE_CTRL _SFR_MEM8(0x0AC0) -+#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) -+#define SPIE_STATUS _SFR_MEM8(0x0AC2) -+#define SPIE_DATA _SFR_MEM8(0x0AC3) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCF0_CTRLA _SFR_MEM8(0x0B00) -+#define TCF0_CTRLB _SFR_MEM8(0x0B01) -+#define TCF0_CTRLC _SFR_MEM8(0x0B02) -+#define TCF0_CTRLD _SFR_MEM8(0x0B03) -+#define TCF0_CTRLE _SFR_MEM8(0x0B04) -+#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -+#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -+#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -+#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -+#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -+#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -+#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -+#define TCF0_TEMP _SFR_MEM8(0x0B0F) -+#define TCF0_CNT _SFR_MEM16(0x0B20) -+#define TCF0_PER _SFR_MEM16(0x0B26) -+#define TCF0_CCA _SFR_MEM16(0x0B28) -+#define TCF0_CCB _SFR_MEM16(0x0B2A) -+#define TCF0_CCC _SFR_MEM16(0x0B2C) -+#define TCF0_CCD _SFR_MEM16(0x0B2E) -+#define TCF0_PERBUF _SFR_MEM16(0x0B36) -+#define TCF0_CCABUF _SFR_MEM16(0x0B38) -+#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -+#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -+#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCF2_CTRLA _SFR_MEM8(0x0B00) -+#define TCF2_CTRLB _SFR_MEM8(0x0B01) -+#define TCF2_CTRLC _SFR_MEM8(0x0B02) -+#define TCF2_CTRLE _SFR_MEM8(0x0B04) -+#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -+#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -+#define TCF2_CTRLF _SFR_MEM8(0x0B09) -+#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -+#define TCF2_LCNT _SFR_MEM8(0x0B20) -+#define TCF2_HCNT _SFR_MEM8(0x0B21) -+#define TCF2_LPER _SFR_MEM8(0x0B26) -+#define TCF2_HPER _SFR_MEM8(0x0B27) -+#define TCF2_LCMPA _SFR_MEM8(0x0B28) -+#define TCF2_HCMPA _SFR_MEM8(0x0B29) -+#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -+#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -+#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -+#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -+#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -+#define TCF2_HCMPD _SFR_MEM8(0x0B2F) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESF_CTRLA _SFR_MEM8(0x0B90) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTF0_DATA _SFR_MEM8(0x0BA0) -+#define USARTF0_STATUS _SFR_MEM8(0x0BA1) -+#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) -+#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) -+#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) -+#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) -+#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* VPORT - Virtual Ports */ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* CLK.USBCTRL bit masks and bit positions */ -+#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -+#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -+#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -+#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -+#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -+#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -+#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -+#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ -+ -+#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -+#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -+#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ -+ -+#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_USB_bm 0x40 /* USB bit mask. */ -+#define PR_USB_bp 6 /* USB bit position. */ -+ -+#define PR_AES_bm 0x10 /* AES bit mask. */ -+#define PR_AES_bp 4 /* AES bit position. */ -+ -+#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -+#define PR_EBI_bp 3 /* External Bus Interface bit position. */ -+ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -+#define PR_DMA_bp 0 /* DMA-Controller bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -+#define PR_DAC_bp 2 /* Port A DAC bit position. */ -+ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPB bit masks and bit positions */ -+/* PR_DAC Predefined. */ -+/* PR_DAC Predefined. */ -+ -+/* PR_ADC Predefined. */ -+/* PR_ADC Predefined. */ -+ -+/* PR_AC Predefined. */ -+/* PR_AC Predefined. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -+#define PR_USART1_bp 5 /* Port C USART1 bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -+#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ -+ -+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -+ -+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ -+ -+/* PR.PRPD bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPE bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPF bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -+#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -+#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ -+ -+#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ -+ -+#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -+#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.MCUCR bit masks and bit positions */ -+#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -+#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ -+ -+/* MCU.ANAINIT bit masks and bit positions */ -+#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -+#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -+#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -+#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -+#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -+#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ -+ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -+#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ -+ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.AWEXLOCK bit masks and bit positions */ -+#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ -+#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ -+ -+#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -+#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ -+ -+#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ -+#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ -+ -+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* PORTCFG - Port Configuration */ -+/* PORTCFG.VPCTRLA bit masks and bit positions */ -+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ -+ -+/* PORTCFG.VPCTRLB bit masks and bit positions */ -+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ -+ -+/* PORTCFG.CLKEVOUT bit masks and bit positions */ -+#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ -+ -+#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -+#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -+#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -+#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -+#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -+#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ -+ -+#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -+#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ -+ -+#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -+#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ -+ -+/* PORTCFG.EBIOUT bit masks and bit positions */ -+#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ -+#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ -+#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ -+#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ -+#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ -+#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ -+ -+#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ -+#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ -+#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ -+#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ -+#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ -+#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ -+ -+/* PORTCFG.EVOUTSEL bit masks and bit positions */ -+#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -+#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -+#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -+#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -+#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -+#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -+#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -+#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ -+ -+/* AES - AES Module */ -+/* AES.CTRL bit masks and bit positions */ -+#define AES_START_bm 0x80 /* Start/Run bit mask. */ -+#define AES_START_bp 7 /* Start/Run bit position. */ -+ -+#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -+#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ -+ -+#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -+#define AES_RESET_bp 5 /* AES Software Reset bit position. */ -+ -+#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -+#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ -+ -+#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -+#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ -+ -+/* AES.STATUS bit masks and bit positions */ -+#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -+#define AES_ERROR_bp 7 /* AES Error bit position. */ -+ -+#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -+#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ -+ -+/* AES.INTCTRL bit masks and bit positions */ -+#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -+#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* DMA - DMA Controller */ -+/* DMA_CH.CTRLA bit masks and bit positions */ -+#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -+#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ -+ -+#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -+#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ -+ -+#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -+#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ -+ -+#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -+#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ -+ -+#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -+#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ -+ -+#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -+#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -+#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -+#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -+#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -+#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ -+ -+/* DMA_CH.CTRLB bit masks and bit positions */ -+#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -+#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ -+ -+#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -+#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ -+ -+#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -+#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ -+ -+#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -+#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -+#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -+#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -+#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -+#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ -+ -+#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -+#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -+#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -+#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -+#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -+#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ -+ -+/* DMA_CH.ADDRCTRL bit masks and bit positions */ -+#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -+#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -+#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -+#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -+#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -+#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ -+ -+#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -+#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -+#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -+#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -+#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -+#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ -+ -+#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -+#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -+#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -+#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -+#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -+#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ -+ -+#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -+#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -+#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -+#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -+#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -+#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ -+ -+/* DMA_CH.TRIGSRC bit masks and bit positions */ -+#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -+#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -+#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -+#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -+#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -+#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -+#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -+#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -+#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -+#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -+#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -+#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -+#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -+#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -+#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -+#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -+#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -+#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ -+ -+/* DMA.CTRL bit masks and bit positions */ -+#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -+#define DMA_ENABLE_bp 7 /* Enable bit position. */ -+ -+#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -+#define DMA_RESET_bp 6 /* Software Reset bit position. */ -+ -+#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -+#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -+#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -+#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -+#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -+#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ -+ -+#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -+#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -+#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -+#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -+#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -+#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ -+ -+/* DMA.INTFLAGS bit masks and bit positions */ -+#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ -+ -+/* DMA.STATUS bit masks and bit positions */ -+#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -+#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ -+ -+#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -+#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ -+ -+#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -+#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ -+ -+#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -+#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ -+ -+#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -+#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ -+ -+#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -+#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ -+ -+#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -+#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ -+ -+#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -+#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH4MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH5MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH6MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH7MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_QDIRM Predefined. */ -+/* EVSYS_QDIRM Predefined. */ -+ -+/* EVSYS_QDIEN Predefined. */ -+/* EVSYS_QDIEN Predefined. */ -+ -+/* EVSYS_QDEN Predefined. */ -+/* EVSYS_QDEN Predefined. */ -+ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH4CTRL bit masks and bit positions */ -+/* EVSYS_QDIRM Predefined. */ -+/* EVSYS_QDIRM Predefined. */ -+ -+/* EVSYS_QDIEN Predefined. */ -+/* EVSYS_QDIEN Predefined. */ -+ -+/* EVSYS_QDEN Predefined. */ -+/* EVSYS_QDEN Predefined. */ -+ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH5CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH6CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH7CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0x7F /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ -+ -+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ -+ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -+#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ -+#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -+#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -+#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -+#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -+#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -+#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -+#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -+#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -+#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -+#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ -+ -+#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -+#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -+#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -+#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -+#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -+#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -+#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -+#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -+#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -+#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -+#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -+#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -+#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -+#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -+#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ -+ -+#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -+#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ -+ -+#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -+#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ -+ -+#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -+#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ -+ -+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -+#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ -+#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ -+ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -+#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -+#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -+#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -+#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -+#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ -+ -+#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -+#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -+#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ -+ -+#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -+#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ -+ -+#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -+#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ -+ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* DAC - Digital/Analog Converter */ -+/* DAC.CTRLA bit masks and bit positions */ -+#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -+#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ -+ -+#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -+#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ -+ -+#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -+#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ -+ -+#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -+#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ -+ -+#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define DAC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* DAC.CTRLB bit masks and bit positions */ -+#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -+#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -+#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -+#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -+#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -+#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ -+ -+#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -+#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ -+ -+#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -+#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ -+ -+/* DAC.CTRLC bit masks and bit positions */ -+#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -+#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -+#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -+#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -+#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -+#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ -+ -+#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -+#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ -+ -+/* DAC.EVCTRL bit masks and bit positions */ -+#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -+#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ -+ -+#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -+#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -+#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -+#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -+#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -+#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -+#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -+#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ -+ -+/* DAC.STATUS bit masks and bit positions */ -+#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -+#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ -+ -+#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -+#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ -+ -+/* DAC.CH0GAINCAL bit masks and bit positions */ -+#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -+#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -+#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -+#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -+#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -+#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -+#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -+#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -+#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -+#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -+#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -+#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -+#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -+#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -+#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -+#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ -+ -+/* DAC.CH0OFFSETCAL bit masks and bit positions */ -+#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -+#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -+#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -+#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -+#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -+#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -+#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -+#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -+#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -+#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -+#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -+#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -+#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -+#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -+#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -+#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ -+ -+/* DAC.CH1GAINCAL bit masks and bit positions */ -+#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -+#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -+#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -+#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -+#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -+#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -+#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -+#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -+#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -+#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -+#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -+#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -+#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -+#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -+#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -+#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ -+ -+/* DAC.CH1OFFSETCAL bit masks and bit positions */ -+#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -+#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -+#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -+#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -+#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -+#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -+#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -+#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -+#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -+#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -+#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -+#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -+#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -+#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -+#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -+#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -+#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HSMODE Predefined. */ -+/* AC_HSMODE Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* RTC - Real-Time Counter */ -+/* RTC.CTRL bit masks and bit positions */ -+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ -+ -+/* RTC.STATUS bit masks and bit positions */ -+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC.INTCTRL bit masks and bit positions */ -+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC.INTFLAGS bit masks and bit positions */ -+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* USB - USB */ -+/* USB_EP.STATUS bit masks and bit positions */ -+#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -+#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ -+ -+#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -+#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ -+ -+#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -+#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ -+ -+#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -+#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ -+ -+#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -+#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ -+ -+#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -+#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ -+ -+#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -+#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ -+ -+#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -+#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ -+ -+#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ -+ -+#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ -+ -+#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -+#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ -+ -+/* USB_EP.CTRL bit masks and bit positions */ -+#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -+#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -+#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -+#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -+#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -+#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ -+ -+#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -+#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ -+ -+#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -+#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ -+ -+#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -+#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ -+ -+#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -+#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ -+ -+#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -+#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -+#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -+#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -+#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -+#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -+#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -+#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ -+ -+/* USB_EP.CNT bit masks and bit positions */ -+#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -+#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ -+ -+/* USB.CTRLA bit masks and bit positions */ -+#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -+#define USB_ENABLE_bp 7 /* USB Enable bit position. */ -+ -+#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -+#define USB_SPEED_bp 6 /* Speed Select bit position. */ -+ -+#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -+#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ -+ -+#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -+#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ -+ -+#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -+#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -+#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -+#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -+#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -+#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -+#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -+#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -+#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -+#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ -+ -+/* USB.CTRLB bit masks and bit positions */ -+#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -+#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ -+ -+#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -+#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ -+ -+#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -+#define USB_GNACK_bp 1 /* Global NACK bit position. */ -+ -+#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -+#define USB_ATTACH_bp 0 /* Attach bit position. */ -+ -+/* USB.STATUS bit masks and bit positions */ -+#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -+#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ -+ -+#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -+#define USB_RESUME_bp 2 /* Resume bit position. */ -+ -+#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -+#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ -+ -+#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -+#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ -+ -+/* USB.ADDR bit masks and bit positions */ -+#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -+#define USB_ADDR_gp 0 /* Device Address group position. */ -+#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -+#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -+#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -+#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -+#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -+#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -+#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -+#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -+#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -+#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -+#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -+#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -+#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -+#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ -+ -+/* USB.FIFOWP bit masks and bit positions */ -+#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -+#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -+#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -+#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -+#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -+#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -+#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -+#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -+#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -+#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -+#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -+#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ -+ -+/* USB.FIFORP bit masks and bit positions */ -+#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -+#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -+#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -+#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -+#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -+#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -+#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -+#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -+#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -+#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -+#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -+#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ -+ -+/* USB.INTCTRLA bit masks and bit positions */ -+#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -+#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ -+ -+#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -+#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ -+ -+#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -+#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ -+ -+#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -+#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ -+ -+#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* USB.INTCTRLB bit masks and bit positions */ -+#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -+#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ -+ -+#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -+#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ -+ -+/* USB.INTFLAGSACLR bit masks and bit positions */ -+#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -+#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ -+ -+#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -+#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ -+ -+#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -+#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ -+ -+#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -+#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ -+ -+#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -+#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ -+ -+#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -+#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ -+ -+#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -+#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ -+ -+#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -+#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSASET bit masks and bit positions */ -+/* USB_SOFIF Predefined. */ -+/* USB_SOFIF Predefined. */ -+ -+/* USB_SUSPENDIF Predefined. */ -+/* USB_SUSPENDIF Predefined. */ -+ -+/* USB_RESUMEIF Predefined. */ -+/* USB_RESUMEIF Predefined. */ -+ -+/* USB_RSTIF Predefined. */ -+/* USB_RSTIF Predefined. */ -+ -+/* USB_CRCIF Predefined. */ -+/* USB_CRCIF Predefined. */ -+ -+/* USB_UNFIF Predefined. */ -+/* USB_UNFIF Predefined. */ -+ -+/* USB_OVFIF Predefined. */ -+/* USB_OVFIF Predefined. */ -+ -+/* USB_STALLIF Predefined. */ -+/* USB_STALLIF Predefined. */ -+ -+/* USB.INTFLAGSBCLR bit masks and bit positions */ -+#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -+#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ -+ -+#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -+#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSBSET bit masks and bit positions */ -+/* USB_TRNIF Predefined. */ -+/* USB_TRNIF Predefined. */ -+ -+/* USB_SETUPIF Predefined. */ -+/* USB_SETUPIF Predefined. */ -+ -+/* PORT - I/O Port Configuration */ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ -+ -+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -+#define PORT_SPI_bp 5 /* SPI bit position. */ -+ -+#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -+#define PORT_USART0_bp 4 /* USART0 bit position. */ -+ -+#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -+#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ -+ -+#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -+#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ -+ -+#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -+#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ -+ -+#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -+#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ -+ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC0.CTRLA bit masks and bit positions */ -+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC0.CTRLB bit masks and bit positions */ -+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ -+ -+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ -+ -+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC0.CTRLC bit masks and bit positions */ -+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ -+ -+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ -+ -+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC0.CTRLD bit masks and bit positions */ -+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC0_EVACT_gp 5 /* Event Action group position. */ -+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC0.CTRLE bit masks and bit positions */ -+#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC0.INTCTRLA bit masks and bit positions */ -+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC0.INTCTRLB bit masks and bit positions */ -+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ -+ -+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ -+ -+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC0.CTRLFCLR bit masks and bit positions */ -+#define TC0_CMD_gm 0x0C /* Command group mask. */ -+#define TC0_CMD_gp 2 /* Command group position. */ -+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC0_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC0_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC0_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC0.CTRLFSET bit masks and bit positions */ -+/* TC0_CMD Predefined. */ -+/* TC0_CMD Predefined. */ -+ -+/* TC0_LUPD Predefined. */ -+/* TC0_LUPD Predefined. */ -+ -+/* TC0_DIR Predefined. */ -+/* TC0_DIR Predefined. */ -+ -+/* TC0.CTRLGCLR bit masks and bit positions */ -+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ -+ -+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ -+ -+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC0.CTRLGSET bit masks and bit positions */ -+/* TC0_CCDBV Predefined. */ -+/* TC0_CCDBV Predefined. */ -+ -+/* TC0_CCCBV Predefined. */ -+/* TC0_CCCBV Predefined. */ -+ -+/* TC0_CCBBV Predefined. */ -+/* TC0_CCBBV Predefined. */ -+ -+/* TC0_CCABV Predefined. */ -+/* TC0_CCABV Predefined. */ -+ -+/* TC0_PERBV Predefined. */ -+/* TC0_PERBV Predefined. */ -+ -+/* TC0.INTFLAGS bit masks and bit positions */ -+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ -+ -+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ -+ -+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC1.CTRLA bit masks and bit positions */ -+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC1.CTRLB bit masks and bit positions */ -+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC1.CTRLC bit masks and bit positions */ -+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC1.CTRLD bit masks and bit positions */ -+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC1_EVACT_gp 5 /* Event Action group position. */ -+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC1.CTRLE bit masks and bit positions */ -+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ -+ -+/* TC1.INTCTRLA bit masks and bit positions */ -+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC1.INTCTRLB bit masks and bit positions */ -+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC1.CTRLFCLR bit masks and bit positions */ -+#define TC1_CMD_gm 0x0C /* Command group mask. */ -+#define TC1_CMD_gp 2 /* Command group position. */ -+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC1_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC1_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC1_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC1.CTRLFSET bit masks and bit positions */ -+/* TC1_CMD Predefined. */ -+/* TC1_CMD Predefined. */ -+ -+/* TC1_LUPD Predefined. */ -+/* TC1_LUPD Predefined. */ -+ -+/* TC1_DIR Predefined. */ -+/* TC1_DIR Predefined. */ -+ -+/* TC1.CTRLGCLR bit masks and bit positions */ -+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC1.CTRLGSET bit masks and bit positions */ -+/* TC1_CCBBV Predefined. */ -+/* TC1_CCBBV Predefined. */ -+ -+/* TC1_CCABV Predefined. */ -+/* TC1_CCABV Predefined. */ -+ -+/* TC1_PERBV Predefined. */ -+/* TC1_PERBV Predefined. */ -+ -+/* TC1.INTFLAGS bit masks and bit positions */ -+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+/* TC2.CTRLA bit masks and bit positions */ -+#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC2.CTRLB bit masks and bit positions */ -+#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -+#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ -+ -+#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -+#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ -+ -+#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -+#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ -+ -+#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -+#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ -+ -+#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -+#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ -+ -+#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -+#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ -+ -+#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -+#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ -+ -+#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -+#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ -+ -+/* TC2.CTRLC bit masks and bit positions */ -+#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -+#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ -+ -+#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -+#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ -+ -+#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -+#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ -+ -+#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -+#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ -+ -+#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -+#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ -+ -+#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -+#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ -+ -+#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -+#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ -+ -+#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -+#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ -+ -+/* TC2.CTRLE bit masks and bit positions */ -+#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC2.INTCTRLA bit masks and bit positions */ -+#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -+#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -+#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -+#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -+#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -+#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ -+ -+#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -+#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -+#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -+#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -+#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -+#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ -+ -+/* TC2.INTCTRLB bit masks and bit positions */ -+#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -+#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -+#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -+#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -+#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -+#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -+#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -+#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -+#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -+#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -+#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -+#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -+#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -+#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -+#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -+#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -+#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -+#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -+#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -+#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -+#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ -+ -+/* TC2.CTRLF bit masks and bit positions */ -+#define TC2_CMD_gm 0x0C /* Command group mask. */ -+#define TC2_CMD_gp 2 /* Command group position. */ -+#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC2_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -+#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -+#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -+#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -+#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -+#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ -+ -+/* TC2.INTFLAGS bit masks and bit positions */ -+#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -+#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ -+ -+#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -+#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ -+ -+#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -+#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ -+ -+#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -+#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ -+ -+#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ -+ -+#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ -+ -+/* AWEX - Timer/Counter Advanced Waveform Extension */ -+/* AWEX.CTRL bit masks and bit positions */ -+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ -+ -+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ -+ -+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ -+ -+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ -+ -+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ -+ -+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ -+ -+/* AWEX.FDCTRL bit masks and bit positions */ -+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ -+ -+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ -+ -+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ -+ -+/* AWEX.STATUS bit masks and bit positions */ -+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ -+ -+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ -+ -+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ -+ -+/* AWEX.STATUSSET bit masks and bit positions */ -+/* AWEX_FDF Predefined. */ -+/* AWEX_FDF Predefined. */ -+ -+/* AWEX_DTHSBUFV Predefined. */ -+/* AWEX_DTHSBUFV Predefined. */ -+ -+/* AWEX_DTLSBUFV Predefined. */ -+/* AWEX_DTLSBUFV Predefined. */ -+ -+/* HIRES - Timer/Counter High-Resolution Extension */ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -+#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -+#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -+#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -+#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -+#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -+#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -+#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -+#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -+#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -+#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -+#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -+#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -+#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -+#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -+#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -+#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -+#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -+#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ -+ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -+#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -+#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* LOCKBIT - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT0_vect_num 2 -+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -+#define PORTC_INT1_vect_num 3 -+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT0_vect_num 4 -+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -+#define PORTR_INT1_vect_num 5 -+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ -+ -+/* DMA interrupt vectors */ -+#define DMA_CH0_vect_num 6 -+#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -+#define DMA_CH1_vect_num 7 -+#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -+#define DMA_CH2_vect_num 8 -+#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -+#define DMA_CH3_vect_num 9 -+#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ -+ -+/* RTC interrupt vectors */ -+#define RTC_OVF_vect_num 10 -+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -+#define RTC_COMP_vect_num 11 -+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 12 -+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 13 -+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_OVF_vect_num 14 -+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LUNF_vect_num 14 -+#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_ERR_vect_num 15 -+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_HUNF_vect_num 15 -+#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCA_vect_num 16 -+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPA_vect_num 16 -+#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCB_vect_num 17 -+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPB_vect_num 17 -+#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCC_vect_num 18 -+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPC_vect_num 18 -+#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCD_vect_num 19 -+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPD_vect_num 19 -+#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ -+ -+/* TCC1 interrupt vectors */ -+#define TCC1_OVF_vect_num 20 -+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -+#define TCC1_ERR_vect_num 21 -+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -+#define TCC1_CCA_vect_num 22 -+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -+#define TCC1_CCB_vect_num 23 -+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 24 -+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 25 -+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 26 -+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 27 -+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ -+ -+/* USARTC1 interrupt vectors */ -+#define USARTC1_RXC_vect_num 28 -+#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -+#define USARTC1_DRE_vect_num 29 -+#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -+#define USARTC1_TXC_vect_num 30 -+#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ -+ -+/* AES interrupt vectors */ -+#define AES_INT_vect_num 31 -+#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 32 -+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -+#define NVM_SPM_vect_num 33 -+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ -+ -+/* PORTB interrupt vectors */ -+#define PORTB_INT0_vect_num 34 -+#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -+#define PORTB_INT1_vect_num 35 -+#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ -+ -+/* ACB interrupt vectors */ -+#define ACB_AC0_vect_num 36 -+#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ -+#define ACB_AC1_vect_num 37 -+#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ -+#define ACB_ACW_vect_num 38 -+#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ -+ -+/* ADCB interrupt vectors */ -+#define ADCB_CH0_vect_num 39 -+#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ -+#define ADCB_CH1_vect_num 40 -+#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ -+#define ADCB_CH2_vect_num 41 -+#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ -+#define ADCB_CH3_vect_num 42 -+#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ -+ -+/* PORTE interrupt vectors */ -+#define PORTE_INT0_vect_num 43 -+#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -+#define PORTE_INT1_vect_num 44 -+#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ -+ -+/* TWIE interrupt vectors */ -+#define TWIE_TWIS_vect_num 45 -+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -+#define TWIE_TWIM_vect_num 46 -+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_OVF_vect_num 47 -+#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LUNF_vect_num 47 -+#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_ERR_vect_num 48 -+#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_HUNF_vect_num 48 -+#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCA_vect_num 49 -+#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPA_vect_num 49 -+#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCB_vect_num 50 -+#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPB_vect_num 50 -+#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCC_vect_num 51 -+#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPC_vect_num 51 -+#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCD_vect_num 52 -+#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPD_vect_num 52 -+#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ -+ -+/* TCE1 interrupt vectors */ -+#define TCE1_OVF_vect_num 53 -+#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ -+#define TCE1_ERR_vect_num 54 -+#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ -+#define TCE1_CCA_vect_num 55 -+#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ -+#define TCE1_CCB_vect_num 56 -+#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ -+ -+/* SPIE interrupt vectors */ -+#define SPIE_INT_vect_num 57 -+#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ -+ -+/* USARTE0 interrupt vectors */ -+#define USARTE0_RXC_vect_num 58 -+#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -+#define USARTE0_DRE_vect_num 59 -+#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -+#define USARTE0_TXC_vect_num 60 -+#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ -+ -+/* USARTE1 interrupt vectors */ -+#define USARTE1_RXC_vect_num 61 -+#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ -+#define USARTE1_DRE_vect_num 62 -+#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ -+#define USARTE1_TXC_vect_num 63 -+#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT0_vect_num 64 -+#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -+#define PORTD_INT1_vect_num 65 -+#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ -+ -+/* PORTA interrupt vectors */ -+#define PORTA_INT0_vect_num 66 -+#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -+#define PORTA_INT1_vect_num 67 -+#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ -+ -+/* ACA interrupt vectors */ -+#define ACA_AC0_vect_num 68 -+#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -+#define ACA_AC1_vect_num 69 -+#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -+#define ACA_ACW_vect_num 70 -+#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ -+ -+/* ADCA interrupt vectors */ -+#define ADCA_CH0_vect_num 71 -+#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -+#define ADCA_CH1_vect_num 72 -+#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -+#define ADCA_CH2_vect_num 73 -+#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -+#define ADCA_CH3_vect_num 74 -+#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_OVF_vect_num 77 -+#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LUNF_vect_num 77 -+#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_ERR_vect_num 78 -+#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_HUNF_vect_num 78 -+#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCA_vect_num 79 -+#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPA_vect_num 79 -+#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCB_vect_num 80 -+#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPB_vect_num 80 -+#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCC_vect_num 81 -+#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPC_vect_num 81 -+#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCD_vect_num 82 -+#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPD_vect_num 82 -+#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ -+ -+/* TCD1 interrupt vectors */ -+#define TCD1_OVF_vect_num 83 -+#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -+#define TCD1_ERR_vect_num 84 -+#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -+#define TCD1_CCA_vect_num 85 -+#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -+#define TCD1_CCB_vect_num 86 -+#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ -+ -+/* SPID interrupt vectors */ -+#define SPID_INT_vect_num 87 -+#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ -+ -+/* USARTD0 interrupt vectors */ -+#define USARTD0_RXC_vect_num 88 -+#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -+#define USARTD0_DRE_vect_num 89 -+#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -+#define USARTD0_TXC_vect_num 90 -+#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ -+ -+/* USARTD1 interrupt vectors */ -+#define USARTD1_RXC_vect_num 91 -+#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -+#define USARTD1_DRE_vect_num 92 -+#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -+#define USARTD1_TXC_vect_num 93 -+#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ -+ -+/* PORTF interrupt vectors */ -+#define PORTF_INT0_vect_num 104 -+#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -+#define PORTF_INT1_vect_num 105 -+#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_OVF_vect_num 108 -+#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LUNF_vect_num 108 -+#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_ERR_vect_num 109 -+#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_HUNF_vect_num 109 -+#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCA_vect_num 110 -+#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPA_vect_num 110 -+#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCB_vect_num 111 -+#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPB_vect_num 111 -+#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCC_vect_num 112 -+#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPC_vect_num 112 -+#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCD_vect_num 113 -+#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPD_vect_num 113 -+#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ -+ -+/* USARTF0 interrupt vectors */ -+#define USARTF0_RXC_vect_num 119 -+#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ -+#define USARTF0_DRE_vect_num 120 -+#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ -+#define USARTF0_TXC_vect_num 121 -+#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ -+ -+/* USB interrupt vectors */ -+#define USB_BUSEVENT_vect_num 125 -+#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -+#define USB_TRNCOMPL_vect_num 126 -+#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (127 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (69632) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (65536) -+#define APP_SECTION_PAGE_SIZE (256) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0xF000) -+#define APPTABLE_SECTION_SIZE (4096) -+#define APPTABLE_SECTION_PAGE_SIZE (256) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x10000) -+#define BOOT_SECTION_SIZE (4096) -+#define BOOT_SECTION_PAGE_SIZE (256) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (12288) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (2048) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (4096) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (2048) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (6) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (256) -+#define USER_SIGNATURES_PAGE_SIZE (256) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (52) -+#define PROD_SIGNATURES_PAGE_SIZE (256) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 256 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 6 -+ -+/* Fuse Byte 0 */ -+#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -+#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -+#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -+#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -+#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -+#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -+#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -+#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -+#define FUSE0_DEFAULT (0xFF) -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x96 -+#define SIGNATURE_2 0x42 -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA64A3U_H_INCLUDED */ -+ -diff --git a/include/avr/iox64a4u.h b/include/avr/iox64a4u.h -new file mode 100644 -index 0000000..6401ec8 ---- /dev/null -+++ b/include/avr/iox64a4u.h -@@ -0,0 +1,7240 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox64a4u.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA64A4U_H_INCLUDED -+#define _AVR_ATXMEGA64A4U_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -+#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -+#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -+#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -+#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -+#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -+#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -+#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -+#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -+#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -+#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -+#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ -+#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ -+#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ -+#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ -+#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ -+#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ -+#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ -+#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ -+#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ -+#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ -+#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ -+#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+VPORT - Virtual Ports -+-------------------------------------------------------------------------- -+*/ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t USBCTRL; /* USB Control Register */ -+} CLK_t; -+ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t PRPB; /* Power Reduction Port B */ -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t PRPD; /* Power Reduction Port D */ -+ register8_t PRPE; /* Power Reduction Port E */ -+ register8_t PRPF; /* Power Reduction Port F */ -+} PR_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+/* USB Prescaler Division Factor */ -+typedef enum CLK_USBPSDIV_enum -+{ -+ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ -+ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ -+ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ -+ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ -+ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ -+ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -+} CLK_USBPSDIV_t; -+ -+/* USB Clock Source */ -+typedef enum CLK_USBSRC_enum -+{ -+ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ -+ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -+} CLK_USBSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control Register */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+/* 2 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC2MCREF_enum -+{ -+ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC2MCREF_t; -+ -+/* 32 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC32MCREF_enum -+{ -+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -+} OSC_RC32MCREF_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t JTAGUID; /* JTAG User ID */ -+ register8_t reserved_0x05; -+ register8_t MCUCR; /* MCU Control */ -+ register8_t ANAINIT; /* Analog Startup Delay */ -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t AWEXLOCK; /* AWEX Lock */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORTCFG - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t VPCTRLA; /* Virtual Port Control Register A */ -+ register8_t VPCTRLB; /* Virtual Port Control Register B */ -+ register8_t CLKEVOUT; /* Clock and Event Out Register */ -+ register8_t EBIOUT; /* EBI Output register */ -+ register8_t EVOUTSEL; /* Event Output Select */ -+} PORTCFG_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP02MAP_enum -+{ -+ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ -+ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ -+ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ -+ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ -+ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ -+ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ -+ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ -+ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ -+ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ -+ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ -+ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ -+ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ -+ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ -+ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ -+ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ -+ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -+} PORTCFG_VP02MAP_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP13MAP_enum -+{ -+ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ -+ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ -+ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ -+ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ -+ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ -+ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ -+ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ -+ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ -+ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ -+ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ -+ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ -+ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ -+ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ -+ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ -+ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ -+ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -+} PORTCFG_VP13MAP_t; -+ -+/* System Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ -+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ -+ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -+} PORTCFG_CLKOUT_t; -+ -+/* Peripheral Clock Output Select */ -+typedef enum PORTCFG_CLKOUTSEL_enum -+{ -+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -+} PORTCFG_CLKOUTSEL_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ -+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ -+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -+} PORTCFG_EVOUT_t; -+ -+/* Clock and Event Output Port */ -+typedef enum PORTCFG_CLKEVPIN_enum -+{ -+ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ -+ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -+} PORTCFG_CLKEVPIN_t; -+ -+/* EBI Address Output Port */ -+typedef enum PORTCFG_EBIADROUT_enum -+{ -+ PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ -+ PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ -+ PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ -+ PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ -+} PORTCFG_EBIADROUT_t; -+ -+/* EBI Chip Select Output Port */ -+typedef enum PORTCFG_EBICSOUT_enum -+{ -+ PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ -+ PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ -+} PORTCFG_EBICSOUT_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -+ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ -+ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ -+ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ -+ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AES - AES Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* AES Module */ -+typedef struct AES_struct -+{ -+ register8_t CTRL; /* AES Control Register */ -+ register8_t STATUS; /* AES Status Register */ -+ register8_t STATE; /* AES State Register */ -+ register8_t KEY; /* AES Key Register */ -+ register8_t INTCTRL; /* AES Interrupt Control Register */ -+} AES_t; -+ -+/* Interrupt level */ -+typedef enum AES_INTLVL_enum -+{ -+ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} AES_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ -+ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ -+ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ -+ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DMA - DMA Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* DMA Channel */ -+typedef struct DMA_CH_struct -+{ -+ register8_t CTRLA; /* Channel Control */ -+ register8_t CTRLB; /* Channel Control */ -+ register8_t ADDRCTRL; /* Address Control */ -+ register8_t TRIGSRC; /* Channel Trigger Source */ -+ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ -+ register8_t REPCNT; /* Channel Repeat Count */ -+ register8_t reserved_0x07; -+ register8_t SRCADDR0; /* Channel Source Address 0 */ -+ register8_t SRCADDR1; /* Channel Source Address 1 */ -+ register8_t SRCADDR2; /* Channel Source Address 2 */ -+ register8_t reserved_0x0B; -+ register8_t DESTADDR0; /* Channel Destination Address 0 */ -+ register8_t DESTADDR1; /* Channel Destination Address 1 */ -+ register8_t DESTADDR2; /* Channel Destination Address 2 */ -+ register8_t reserved_0x0F; -+} DMA_CH_t; -+ -+ -+/* DMA Controller */ -+typedef struct DMA_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t reserved_0x01; -+ register8_t reserved_0x02; -+ register8_t INTFLAGS; /* Transfer Interrupt Status */ -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x05; -+ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ DMA_CH_t CH0; /* DMA Channel 0 */ -+ DMA_CH_t CH1; /* DMA Channel 1 */ -+ DMA_CH_t CH2; /* DMA Channel 2 */ -+ DMA_CH_t CH3; /* DMA Channel 3 */ -+} DMA_t; -+ -+/* Burst mode */ -+typedef enum DMA_CH_BURSTLEN_enum -+{ -+ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ -+ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ -+ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ -+ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -+} DMA_CH_BURSTLEN_t; -+ -+/* Source address reload mode */ -+typedef enum DMA_CH_SRCRELOAD_enum -+{ -+ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ -+ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ -+ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ -+ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -+} DMA_CH_SRCRELOAD_t; -+ -+/* Source addressing mode */ -+typedef enum DMA_CH_SRCDIR_enum -+{ -+ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ -+ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ -+ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -+} DMA_CH_SRCDIR_t; -+ -+/* Destination adress reload mode */ -+typedef enum DMA_CH_DESTRELOAD_enum -+{ -+ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ -+ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ -+ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ -+ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -+} DMA_CH_DESTRELOAD_t; -+ -+/* Destination adressing mode */ -+typedef enum DMA_CH_DESTDIR_enum -+{ -+ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ -+ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ -+ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -+} DMA_CH_DESTDIR_t; -+ -+/* Transfer trigger source */ -+typedef enum DMA_CH_TRIGSRC_enum -+{ -+ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ -+ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ -+ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ -+ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ -+ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ -+ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ -+ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ -+ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ -+ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ -+ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ -+ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ -+ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ -+ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ -+ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ -+ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ -+ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ -+ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ -+ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ -+ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ -+ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ -+ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ -+ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ -+ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ -+ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ -+ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ -+ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ -+ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ -+ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ -+ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ -+ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ -+ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ -+ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ -+ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ -+ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ -+ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ -+ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ -+} DMA_CH_TRIGSRC_t; -+ -+/* Double buffering mode */ -+typedef enum DMA_DBUFMODE_enum -+{ -+ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ -+ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ -+ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ -+ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ -+} DMA_DBUFMODE_t; -+ -+/* Priority mode */ -+typedef enum DMA_PRIMODE_enum -+{ -+ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ -+ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ -+ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ -+ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ -+} DMA_PRIMODE_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_ERRINTLVL_enum -+{ -+ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ -+ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ -+ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -+} DMA_CH_ERRINTLVL_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_TRNINTLVL_enum -+{ -+ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ -+ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -+} DMA_CH_TRNINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ -+ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ -+ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ -+ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t CH4CTRL; /* Channel 4 Control Register */ -+ register8_t CH5CTRL; /* Channel 5 Control Register */ -+ register8_t CH6CTRL; /* Channel 6 Control Register */ -+ register8_t CH7CTRL; /* Channel 7 Control Register */ -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+} EVSYS_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ -+ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ -+ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ -+ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ -+ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ -+ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ -+ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ -+ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ -+ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ -+ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ -+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ -+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ -+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ -+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ -+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ -+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ -+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ -+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ -+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ -+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ -+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ -+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ -+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ -+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ -+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ -+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ -+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ -+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ -+ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ -+ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ -+ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ -+ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ -+ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ -+ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ -+ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ -+ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ -+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ -+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ -+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ -+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ -+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ -+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ -+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ -+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ -+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ -+ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ -+ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ -+ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ -+ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ -+ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ -+ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ -+ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ -+ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ -+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ -+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ -+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ -+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -+ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ -+ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ -+ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ -+ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ -+ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ -+ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ -+ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ -+ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -+ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ -+ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ -+ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ -+ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ -+} EVSYS_CHMUX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ -+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ -+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ -+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ -+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} NVM_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t reserved_0x07; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ _WORDREGISTER(CH1RES); /* Channel 1 Result */ -+ _WORDREGISTER(CH2RES); /* Channel 2 Result */ -+ _WORDREGISTER(CH3RES); /* Channel 3 Result */ -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+ ADC_CH_t CH1; /* ADC Channel 1 */ -+ ADC_CH_t CH2; /* ADC Channel 2 */ -+ ADC_CH_t CH3; /* ADC Channel 3 */ -+} ADC_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -+ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+ ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 3) */ -+ ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Groud (Input Mode = 3) */ -+ ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Groud (Input Mode = 4) */ -+ ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 4) */ -+} ADC_CH_MUXNEG_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Current Limitation Mode */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ -+} ADC_CURRLIMIT_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Channel sweep selection */ -+typedef enum ADC_SWEEP_enum -+{ -+ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ -+ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ -+ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ -+ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ -+} ADC_SWEEP_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ -+ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ -+ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ -+ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ -+ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ -+ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ -+ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ -+ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -+ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ -+ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ -+ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ -+ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* DMA request selection */ -+typedef enum ADC_DMASEL_enum -+{ -+ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ -+ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ -+ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ -+ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ -+} ADC_DMASEL_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DAC - Digital/Analog Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Digital-to-Analog Converter */ -+typedef struct DAC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t EVCTRL; /* Event Input Control */ -+ register8_t reserved_0x04; -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0GAINCAL; /* Gain Calibration */ -+ register8_t CH0OFFSETCAL; /* Offset Calibration */ -+ register8_t CH1GAINCAL; /* Gain Calibration */ -+ register8_t CH1OFFSETCAL; /* Offset Calibration */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ -+ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -+} DAC_t; -+ -+/* Output channel selection */ -+typedef enum DAC_CHSEL_enum -+{ -+ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ -+ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ -+ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -+} DAC_CHSEL_t; -+ -+/* Reference voltage selection */ -+typedef enum DAC_REFSEL_enum -+{ -+ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ -+ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ -+ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ -+ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -+} DAC_REFSEL_t; -+ -+/* Event channel selection */ -+typedef enum DAC_EVSEL_enum -+{ -+ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ -+ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ -+ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ -+ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ -+ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ -+ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ -+ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ -+ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -+} DAC_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC - Real-Time Counter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Real-Time Counter */ -+typedef struct RTC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary register */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ _WORDREGISTER(CNT); /* Count Register */ -+ _WORDREGISTER(PER); /* Period Register */ -+ _WORDREGISTER(COMP); /* Compare Register */ -+} RTC_t; -+ -+/* Prescaler Factor */ -+typedef enum RTC_PRESCALER_enum -+{ -+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ -+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ -+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ -+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ -+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ -+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ -+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ -+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -+} RTC_PRESCALER_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC_COMPINTLVL_enum -+{ -+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC_OVFINTLVL_enum -+{ -+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+} TWI_t; -+ -+/* SDA Hold Time */ -+typedef enum TWI_SDAHOLD_enum -+{ -+ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ -+ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ -+ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ -+ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -+} TWI_SDAHOLD_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USB - USB -+-------------------------------------------------------------------------- -+*/ -+ -+/* USB Endpoint */ -+typedef struct USB_EP_struct -+{ -+ register8_t STATUS; /* Endpoint Status */ -+ register8_t CTRL; /* Endpoint Control */ -+ _WORDREGISTER(CNT); /* USB Endpoint Counter */ -+ _WORDREGISTER(DATAPTR); /* Data Pointer */ -+ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -+} USB_EP_t; -+ -+ -+/* Universal Serial Bus */ -+typedef struct USB_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t FIFOWP; /* FIFO Write Pointer Register */ -+ register8_t FIFORP; /* FIFO Read Pointer Register */ -+ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ -+ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ -+ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ -+ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t reserved_0x20; -+ register8_t reserved_0x21; -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t CAL0; /* Calibration Byte 0 */ -+ register8_t CAL1; /* Calibration Byte 1 */ -+} USB_t; -+ -+ -+/* USB Endpoint Table */ -+typedef struct USB_EP_TABLE_struct -+{ -+ USB_EP_t EP0OUT; /* Endpoint 0 */ -+ USB_EP_t EP0IN; /* Endpoint 0 */ -+ USB_EP_t EP1OUT; /* Endpoint 1 */ -+ USB_EP_t EP1IN; /* Endpoint 1 */ -+ USB_EP_t EP2OUT; /* Endpoint 2 */ -+ USB_EP_t EP2IN; /* Endpoint 2 */ -+ USB_EP_t EP3OUT; /* Endpoint 3 */ -+ USB_EP_t EP3IN; /* Endpoint 3 */ -+ USB_EP_t EP4OUT; /* Endpoint 4 */ -+ USB_EP_t EP4IN; /* Endpoint 4 */ -+ USB_EP_t EP5OUT; /* Endpoint 5 */ -+ USB_EP_t EP5IN; /* Endpoint 5 */ -+ USB_EP_t EP6OUT; /* Endpoint 6 */ -+ USB_EP_t EP6IN; /* Endpoint 6 */ -+ USB_EP_t EP7OUT; /* Endpoint 7 */ -+ USB_EP_t EP7IN; /* Endpoint 7 */ -+ USB_EP_t EP8OUT; /* Endpoint 8 */ -+ USB_EP_t EP8IN; /* Endpoint 8 */ -+ USB_EP_t EP9OUT; /* Endpoint 9 */ -+ USB_EP_t EP9IN; /* Endpoint 9 */ -+ USB_EP_t EP10OUT; /* Endpoint 10 */ -+ USB_EP_t EP10IN; /* Endpoint 10 */ -+ USB_EP_t EP11OUT; /* Endpoint 11 */ -+ USB_EP_t EP11IN; /* Endpoint 11 */ -+ USB_EP_t EP12OUT; /* Endpoint 12 */ -+ USB_EP_t EP12IN; /* Endpoint 12 */ -+ USB_EP_t EP13OUT; /* Endpoint 13 */ -+ USB_EP_t EP13IN; /* Endpoint 13 */ -+ USB_EP_t EP14OUT; /* Endpoint 14 */ -+ USB_EP_t EP14IN; /* Endpoint 14 */ -+ USB_EP_t EP15OUT; /* Endpoint 15 */ -+ USB_EP_t EP15IN; /* Endpoint 15 */ -+ register8_t reserved_0x100; -+ register8_t reserved_0x101; -+ register8_t reserved_0x102; -+ register8_t reserved_0x103; -+ register8_t reserved_0x104; -+ register8_t reserved_0x105; -+ register8_t reserved_0x106; -+ register8_t reserved_0x107; -+ register8_t reserved_0x108; -+ register8_t reserved_0x109; -+ register8_t reserved_0x10A; -+ register8_t reserved_0x10B; -+ register8_t reserved_0x10C; -+ register8_t reserved_0x10D; -+ register8_t reserved_0x10E; -+ register8_t reserved_0x10F; -+ register8_t FRAMENUML; /* Frame Number Low Byte */ -+ register8_t FRAMENUMH; /* Frame Number High Byte */ -+} USB_EP_TABLE_t; -+ -+/* Interrupt level */ -+typedef enum USB_INTLVL_enum -+{ -+ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} USB_INTLVL_t; -+ -+/* USB Endpoint Type */ -+typedef enum USB_EP_TYPE_enum -+{ -+ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ -+ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ -+ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ -+ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -+} USB_EP_TYPE_t; -+ -+/* USB Endpoint Buffersize */ -+typedef enum USB_EP_BUFSIZE_enum -+{ -+ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ -+ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ -+ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ -+ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ -+ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ -+ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ -+ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ -+ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -+} USB_EP_BUFSIZE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - I/O Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INT0MASK; /* Port Interrupt 0 Mask */ -+ register8_t INT1MASK; /* Port Interrupt 1 Mask */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t REMAP; /* I/O Port Pin Remap Register */ -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Port Interrupt 0 Level */ -+typedef enum PORT_INT0LVL_enum -+{ -+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INT0LVL_t; -+ -+/* Port Interrupt 1 Level */ -+typedef enum PORT_INT1LVL_enum -+{ -+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ -+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ -+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -+} PORT_INT1LVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 0 */ -+typedef struct TC0_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC0_t; -+ -+ -+/* 16-bit Timer/Counter 1 */ -+typedef struct TC1_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+} TC1_t; -+ -+/* Clock Selection */ -+typedef enum TC_CLKSEL_enum -+{ -+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC_CLKSEL_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC_WGMODE_enum -+{ -+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC_WGMODE_t; -+ -+/* Byte Mode */ -+typedef enum TC_BYTEM_enum -+{ -+ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ -+ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -+} TC_BYTEM_t; -+ -+/* Event Action */ -+typedef enum TC_EVACT_enum -+{ -+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ -+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ -+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ -+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ -+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ -+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC_EVSEL_enum -+{ -+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC_EVSEL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC_ERRINTLVL_enum -+{ -+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC_OVFINTLVL_enum -+{ -+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_OVFINTLVL_t; -+ -+/* Compare or Capture D Interrupt Level */ -+typedef enum TC_CCDINTLVL_enum -+{ -+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC_CCDINTLVL_t; -+ -+/* Compare or Capture C Interrupt Level */ -+typedef enum TC_CCCINTLVL_enum -+{ -+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC_CCCINTLVL_t; -+ -+/* Compare or Capture B Interrupt Level */ -+typedef enum TC_CCBINTLVL_enum -+{ -+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_CCBINTLVL_t; -+ -+/* Compare or Capture A Interrupt Level */ -+typedef enum TC_CCAINTLVL_enum -+{ -+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_CCAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC_CMD_enum -+{ -+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC2 - 16-bit Timer/Counter type 2 -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter type 2 */ -+typedef struct TC2_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t reserved_0x03; -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t reserved_0x08; -+ register8_t CTRLF; /* Control Register F */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t LCNT; /* Low Byte Count */ -+ register8_t HCNT; /* High Byte Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t LPER; /* Low Byte Period */ -+ register8_t HPER; /* High Byte Period */ -+ register8_t LCMPA; /* Low Byte Compare A */ -+ register8_t HCMPA; /* High Byte Compare A */ -+ register8_t LCMPB; /* Low Byte Compare B */ -+ register8_t HCMPB; /* High Byte Compare B */ -+ register8_t LCMPC; /* Low Byte Compare C */ -+ register8_t HCMPC; /* High Byte Compare C */ -+ register8_t LCMPD; /* Low Byte Compare D */ -+ register8_t HCMPD; /* High Byte Compare D */ -+} TC2_t; -+ -+/* Clock Selection */ -+typedef enum TC2_CLKSEL_enum -+{ -+ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC2_CLKSEL_t; -+ -+/* Byte Mode */ -+typedef enum TC2_BYTEM_enum -+{ -+ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ -+ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -+} TC2_BYTEM_t; -+ -+/* High Byte Underflow Interrupt Level */ -+typedef enum TC2_HUNFINTLVL_enum -+{ -+ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_HUNFINTLVL_t; -+ -+/* Low Byte Underflow Interrupt Level */ -+typedef enum TC2_LUNFINTLVL_enum -+{ -+ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LUNFINTLVL_t; -+ -+/* Low Byte Compare D Interrupt Level */ -+typedef enum TC2_LCMPDINTLVL_enum -+{ -+ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC2_LCMPDINTLVL_t; -+ -+/* Low Byte Compare C Interrupt Level */ -+typedef enum TC2_LCMPCINTLVL_enum -+{ -+ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC2_LCMPCINTLVL_t; -+ -+/* Low Byte Compare B Interrupt Level */ -+typedef enum TC2_LCMPBINTLVL_enum -+{ -+ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_LCMPBINTLVL_t; -+ -+/* Low Byte Compare A Interrupt Level */ -+typedef enum TC2_LCMPAINTLVL_enum -+{ -+ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LCMPAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMD_enum -+{ -+ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC2_CMD_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMDEN_enum -+{ -+ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ -+ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ -+ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -+} TC2_CMDEN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AWEX - Timer/Counter Advanced Waveform Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Advanced Waveform Extension */ -+typedef struct AWEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t FDEMASK; /* Fault Detection Event Mask */ -+ register8_t FDCTRL; /* Fault Detection Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t STATUSSET; /* Status Set Register */ -+ register8_t DTBOTH; /* Dead Time Both Sides */ -+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ -+ register8_t DTLS; /* Dead Time Low Side */ -+ register8_t DTHS; /* Dead Time High Side */ -+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ -+ register8_t DTHSBUF; /* Dead Time High Side Buffer */ -+ register8_t OUTOVEN; /* Output Override Enable */ -+} AWEX_t; -+ -+/* Fault Detect Action */ -+typedef enum AWEX_FDACT_enum -+{ -+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ -+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -+} AWEX_FDACT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+HIRES - Timer/Counter High-Resolution Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register */ -+} HIRES_t; -+ -+/* High Resolution Enable */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ -+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ -+ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ -+ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ -+ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -+} IRDA_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t reserved_0x00; -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+} NVM_FUSES_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* Timer Oscillator pin location */ -+typedef enum TOSCSEL_enum -+{ -+ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ -+ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -+} TOSCSEL_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -+} BOD_t; -+ -+/* BOD operation */ -+typedef enum BODACT_enum -+{ -+ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BODACT_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WDP_enum -+{ -+ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ -+ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ -+ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ -+ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ -+ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ -+ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ -+ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ -+ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ -+ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ -+ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ -+ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -+} WDP_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LOCKBIT - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ -+ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t USBCAL0; /* USB Calibration Byte 0 */ -+ register8_t USBCAL1; /* USB Calibration Byte 1 */ -+ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ -+ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ -+ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ -+ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ -+ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ -+ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ -+ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ -+ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ -+ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ -+ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+ register8_t reserved_0x40; -+ register8_t reserved_0x41; -+ register8_t reserved_0x42; -+ register8_t reserved_0x43; -+ register8_t reserved_0x44; -+ register8_t reserved_0x45; -+ register8_t reserved_0x46; -+ register8_t reserved_0x47; -+} NVM_PROD_SIGNATURES_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define AES (*(AES_t *) 0x00C0) /* AES Module */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -+#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -+#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -+#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -+#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -+#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ -+#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ -+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -+#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -+#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ -+#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+#define GPIO_GPIOR4 _SFR_MEM8(0x0004) -+#define GPIO_GPIOR5 _SFR_MEM8(0x0005) -+#define GPIO_GPIOR6 _SFR_MEM8(0x0006) -+#define GPIO_GPIOR7 _SFR_MEM8(0x0007) -+#define GPIO_GPIOR8 _SFR_MEM8(0x0008) -+#define GPIO_GPIOR9 _SFR_MEM8(0x0009) -+#define GPIO_GPIORA _SFR_MEM8(0x000A) -+#define GPIO_GPIORB _SFR_MEM8(0x000B) -+#define GPIO_GPIORC _SFR_MEM8(0x000C) -+#define GPIO_GPIORD _SFR_MEM8(0x000D) -+#define GPIO_GPIORE _SFR_MEM8(0x000E) -+#define GPIO_GPIORF _SFR_MEM8(0x000F) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+#define GPIO_GPIO4 _SFR_MEM8(0x0004) -+#define GPIO_GPIO5 _SFR_MEM8(0x0005) -+#define GPIO_GPIO6 _SFR_MEM8(0x0006) -+#define GPIO_GPIO7 _SFR_MEM8(0x0007) -+#define GPIO_GPIO8 _SFR_MEM8(0x0008) -+#define GPIO_GPIO9 _SFR_MEM8(0x0009) -+#define GPIO_GPIOA _SFR_MEM8(0x000A) -+#define GPIO_GPIOB _SFR_MEM8(0x000B) -+#define GPIO_GPIOC _SFR_MEM8(0x000C) -+#define GPIO_GPIOD _SFR_MEM8(0x000D) -+#define GPIO_GPIOE _SFR_MEM8(0x000E) -+#define GPIO_GPIOF _SFR_MEM8(0x000F) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -+#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -+#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -+#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -+#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -+#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -+#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) -+#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) -+#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -+#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) -+#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) -+#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+#define CLK_USBCTRL _SFR_MEM8(0x0044) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* DFLL - DFLL */ -+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -+#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -+#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPB _SFR_MEM8(0x0072) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPD _SFR_MEM8(0x0074) -+#define PR_PRPE _SFR_MEM8(0x0075) -+#define PR_PRPF _SFR_MEM8(0x0076) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_JTAGUID _SFR_MEM8(0x0094) -+#define MCU_MCUCR _SFR_MEM8(0x0096) -+#define MCU_ANAINIT _SFR_MEM8(0x0097) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_AWEXLOCK _SFR_MEM8(0x0099) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) -+#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) -+ -+/* AES - AES Module */ -+#define AES_CTRL _SFR_MEM8(0x00C0) -+#define AES_STATUS _SFR_MEM8(0x00C1) -+#define AES_STATE _SFR_MEM8(0x00C2) -+#define AES_KEY _SFR_MEM8(0x00C3) -+#define AES_INTCTRL _SFR_MEM8(0x00C4) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* DMA - DMA Controller */ -+#define DMA_CTRL _SFR_MEM8(0x0100) -+#define DMA_INTFLAGS _SFR_MEM8(0x0103) -+#define DMA_STATUS _SFR_MEM8(0x0104) -+#define DMA_TEMP _SFR_MEM16(0x0106) -+#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -+#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -+#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -+#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -+#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -+#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -+#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -+#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -+#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) -+#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -+#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -+#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) -+#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -+#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -+#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -+#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -+#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -+#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -+#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -+#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -+#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) -+#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -+#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -+#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) -+#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) -+#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) -+#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -+#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) -+#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) -+#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) -+#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) -+#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) -+#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) -+#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) -+#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) -+#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) -+#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) -+#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) -+#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -+#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) -+#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) -+#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) -+#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) -+#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) -+#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) -+#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) -+#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) -+#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -+#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -+#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -+#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -+#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -+#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -+#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCA_CTRLA _SFR_MEM8(0x0200) -+#define ADCA_CTRLB _SFR_MEM8(0x0201) -+#define ADCA_REFCTRL _SFR_MEM8(0x0202) -+#define ADCA_EVCTRL _SFR_MEM8(0x0203) -+#define ADCA_PRESCALER _SFR_MEM8(0x0204) -+#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -+#define ADCA_TEMP _SFR_MEM8(0x0207) -+#define ADCA_CAL _SFR_MEM16(0x020C) -+#define ADCA_CH0RES _SFR_MEM16(0x0210) -+#define ADCA_CH1RES _SFR_MEM16(0x0212) -+#define ADCA_CH2RES _SFR_MEM16(0x0214) -+#define ADCA_CH3RES _SFR_MEM16(0x0216) -+#define ADCA_CMP _SFR_MEM16(0x0218) -+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -+#define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -+#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) -+#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) -+#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) -+#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) -+#define ADCA_CH1_RES _SFR_MEM16(0x022C) -+#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) -+#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) -+#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) -+#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) -+#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) -+#define ADCA_CH2_RES _SFR_MEM16(0x0234) -+#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) -+#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) -+#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) -+#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) -+#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) -+#define ADCA_CH3_RES _SFR_MEM16(0x023C) -+#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) -+ -+/* DAC - Digital-to-Analog Converter */ -+#define DACB_CTRLA _SFR_MEM8(0x0320) -+#define DACB_CTRLB _SFR_MEM8(0x0321) -+#define DACB_CTRLC _SFR_MEM8(0x0322) -+#define DACB_EVCTRL _SFR_MEM8(0x0323) -+#define DACB_STATUS _SFR_MEM8(0x0325) -+#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) -+#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) -+#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) -+#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) -+#define DACB_CH0DATA _SFR_MEM16(0x0338) -+#define DACB_CH1DATA _SFR_MEM16(0x033A) -+ -+/* AC - Analog Comparator */ -+#define ACA_AC0CTRL _SFR_MEM8(0x0380) -+#define ACA_AC1CTRL _SFR_MEM8(0x0381) -+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -+#define ACA_CTRLA _SFR_MEM8(0x0384) -+#define ACA_CTRLB _SFR_MEM8(0x0385) -+#define ACA_WINCTRL _SFR_MEM8(0x0386) -+#define ACA_STATUS _SFR_MEM8(0x0387) -+ -+/* RTC - Real-Time Counter */ -+#define RTC_CTRL _SFR_MEM8(0x0400) -+#define RTC_STATUS _SFR_MEM8(0x0401) -+#define RTC_INTCTRL _SFR_MEM8(0x0402) -+#define RTC_INTFLAGS _SFR_MEM8(0x0403) -+#define RTC_TEMP _SFR_MEM8(0x0404) -+#define RTC_CNT _SFR_MEM16(0x0408) -+#define RTC_PER _SFR_MEM16(0x040A) -+#define RTC_COMP _SFR_MEM16(0x040C) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIE_CTRL _SFR_MEM8(0x04A0) -+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -+ -+/* USB - Universal Serial Bus */ -+#define USB_CTRLA _SFR_MEM8(0x04C0) -+#define USB_CTRLB _SFR_MEM8(0x04C1) -+#define USB_STATUS _SFR_MEM8(0x04C2) -+#define USB_ADDR _SFR_MEM8(0x04C3) -+#define USB_FIFOWP _SFR_MEM8(0x04C4) -+#define USB_FIFORP _SFR_MEM8(0x04C5) -+#define USB_EPPTR _SFR_MEM16(0x04C6) -+#define USB_INTCTRLA _SFR_MEM8(0x04C8) -+#define USB_INTCTRLB _SFR_MEM8(0x04C9) -+#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -+#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -+#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -+#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -+#define USB_CAL0 _SFR_MEM8(0x04FA) -+#define USB_CAL1 _SFR_MEM8(0x04FB) -+ -+/* PORT - I/O Ports */ -+#define PORTA_DIR _SFR_MEM8(0x0600) -+#define PORTA_DIRSET _SFR_MEM8(0x0601) -+#define PORTA_DIRCLR _SFR_MEM8(0x0602) -+#define PORTA_DIRTGL _SFR_MEM8(0x0603) -+#define PORTA_OUT _SFR_MEM8(0x0604) -+#define PORTA_OUTSET _SFR_MEM8(0x0605) -+#define PORTA_OUTCLR _SFR_MEM8(0x0606) -+#define PORTA_OUTTGL _SFR_MEM8(0x0607) -+#define PORTA_IN _SFR_MEM8(0x0608) -+#define PORTA_INTCTRL _SFR_MEM8(0x0609) -+#define PORTA_INT0MASK _SFR_MEM8(0x060A) -+#define PORTA_INT1MASK _SFR_MEM8(0x060B) -+#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_REMAP _SFR_MEM8(0x060E) -+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -+ -+/* PORT - I/O Ports */ -+#define PORTB_DIR _SFR_MEM8(0x0620) -+#define PORTB_DIRSET _SFR_MEM8(0x0621) -+#define PORTB_DIRCLR _SFR_MEM8(0x0622) -+#define PORTB_DIRTGL _SFR_MEM8(0x0623) -+#define PORTB_OUT _SFR_MEM8(0x0624) -+#define PORTB_OUTSET _SFR_MEM8(0x0625) -+#define PORTB_OUTCLR _SFR_MEM8(0x0626) -+#define PORTB_OUTTGL _SFR_MEM8(0x0627) -+#define PORTB_IN _SFR_MEM8(0x0628) -+#define PORTB_INTCTRL _SFR_MEM8(0x0629) -+#define PORTB_INT0MASK _SFR_MEM8(0x062A) -+#define PORTB_INT1MASK _SFR_MEM8(0x062B) -+#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -+#define PORTB_REMAP _SFR_MEM8(0x062E) -+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INT0MASK _SFR_MEM8(0x064A) -+#define PORTC_INT1MASK _SFR_MEM8(0x064B) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INT0MASK _SFR_MEM8(0x066A) -+#define PORTD_INT1MASK _SFR_MEM8(0x066B) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTE_DIR _SFR_MEM8(0x0680) -+#define PORTE_DIRSET _SFR_MEM8(0x0681) -+#define PORTE_DIRCLR _SFR_MEM8(0x0682) -+#define PORTE_DIRTGL _SFR_MEM8(0x0683) -+#define PORTE_OUT _SFR_MEM8(0x0684) -+#define PORTE_OUTSET _SFR_MEM8(0x0685) -+#define PORTE_OUTCLR _SFR_MEM8(0x0686) -+#define PORTE_OUTTGL _SFR_MEM8(0x0687) -+#define PORTE_IN _SFR_MEM8(0x0688) -+#define PORTE_INTCTRL _SFR_MEM8(0x0689) -+#define PORTE_INT0MASK _SFR_MEM8(0x068A) -+#define PORTE_INT1MASK _SFR_MEM8(0x068B) -+#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -+#define PORTE_REMAP _SFR_MEM8(0x068E) -+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -+#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCC0_CTRLA _SFR_MEM8(0x0800) -+#define TCC0_CTRLB _SFR_MEM8(0x0801) -+#define TCC0_CTRLC _SFR_MEM8(0x0802) -+#define TCC0_CTRLD _SFR_MEM8(0x0803) -+#define TCC0_CTRLE _SFR_MEM8(0x0804) -+#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -+#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -+#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -+#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC0_TEMP _SFR_MEM8(0x080F) -+#define TCC0_CNT _SFR_MEM16(0x0820) -+#define TCC0_PER _SFR_MEM16(0x0826) -+#define TCC0_CCA _SFR_MEM16(0x0828) -+#define TCC0_CCB _SFR_MEM16(0x082A) -+#define TCC0_CCC _SFR_MEM16(0x082C) -+#define TCC0_CCD _SFR_MEM16(0x082E) -+#define TCC0_PERBUF _SFR_MEM16(0x0836) -+#define TCC0_CCABUF _SFR_MEM16(0x0838) -+#define TCC0_CCBBUF _SFR_MEM16(0x083A) -+#define TCC0_CCCBUF _SFR_MEM16(0x083C) -+#define TCC0_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCC2_CTRLA _SFR_MEM8(0x0800) -+#define TCC2_CTRLB _SFR_MEM8(0x0801) -+#define TCC2_CTRLC _SFR_MEM8(0x0802) -+#define TCC2_CTRLE _SFR_MEM8(0x0804) -+#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC2_CTRLF _SFR_MEM8(0x0809) -+#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC2_LCNT _SFR_MEM8(0x0820) -+#define TCC2_HCNT _SFR_MEM8(0x0821) -+#define TCC2_LPER _SFR_MEM8(0x0826) -+#define TCC2_HPER _SFR_MEM8(0x0827) -+#define TCC2_LCMPA _SFR_MEM8(0x0828) -+#define TCC2_HCMPA _SFR_MEM8(0x0829) -+#define TCC2_LCMPB _SFR_MEM8(0x082A) -+#define TCC2_HCMPB _SFR_MEM8(0x082B) -+#define TCC2_LCMPC _SFR_MEM8(0x082C) -+#define TCC2_HCMPC _SFR_MEM8(0x082D) -+#define TCC2_LCMPD _SFR_MEM8(0x082E) -+#define TCC2_HCMPD _SFR_MEM8(0x082F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCC1_CTRLA _SFR_MEM8(0x0840) -+#define TCC1_CTRLB _SFR_MEM8(0x0841) -+#define TCC1_CTRLC _SFR_MEM8(0x0842) -+#define TCC1_CTRLD _SFR_MEM8(0x0843) -+#define TCC1_CTRLE _SFR_MEM8(0x0844) -+#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -+#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -+#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -+#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC1_TEMP _SFR_MEM8(0x084F) -+#define TCC1_CNT _SFR_MEM16(0x0860) -+#define TCC1_PER _SFR_MEM16(0x0866) -+#define TCC1_CCA _SFR_MEM16(0x0868) -+#define TCC1_CCB _SFR_MEM16(0x086A) -+#define TCC1_PERBUF _SFR_MEM16(0x0876) -+#define TCC1_CCABUF _SFR_MEM16(0x0878) -+#define TCC1_CCBBUF _SFR_MEM16(0x087A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXC_CTRL _SFR_MEM8(0x0880) -+#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -+#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -+#define AWEXC_STATUS _SFR_MEM8(0x0884) -+#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -+#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -+#define AWEXC_DTLS _SFR_MEM8(0x0888) -+#define AWEXC_DTHS _SFR_MEM8(0x0889) -+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x0890) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08A0) -+#define USARTC0_STATUS _SFR_MEM8(0x08A1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -+#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -+#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC1_DATA _SFR_MEM8(0x08B0) -+#define USARTC1_STATUS _SFR_MEM8(0x08B1) -+#define USARTC1_CTRLA _SFR_MEM8(0x08B3) -+#define USARTC1_CTRLB _SFR_MEM8(0x08B4) -+#define USARTC1_CTRLC _SFR_MEM8(0x08B5) -+#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) -+#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIC_CTRL _SFR_MEM8(0x08C0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -+#define SPIC_STATUS _SFR_MEM8(0x08C2) -+#define SPIC_DATA _SFR_MEM8(0x08C3) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCD0_CTRLA _SFR_MEM8(0x0900) -+#define TCD0_CTRLB _SFR_MEM8(0x0901) -+#define TCD0_CTRLC _SFR_MEM8(0x0902) -+#define TCD0_CTRLD _SFR_MEM8(0x0903) -+#define TCD0_CTRLE _SFR_MEM8(0x0904) -+#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -+#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -+#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -+#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -+#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD0_TEMP _SFR_MEM8(0x090F) -+#define TCD0_CNT _SFR_MEM16(0x0920) -+#define TCD0_PER _SFR_MEM16(0x0926) -+#define TCD0_CCA _SFR_MEM16(0x0928) -+#define TCD0_CCB _SFR_MEM16(0x092A) -+#define TCD0_CCC _SFR_MEM16(0x092C) -+#define TCD0_CCD _SFR_MEM16(0x092E) -+#define TCD0_PERBUF _SFR_MEM16(0x0936) -+#define TCD0_CCABUF _SFR_MEM16(0x0938) -+#define TCD0_CCBBUF _SFR_MEM16(0x093A) -+#define TCD0_CCCBUF _SFR_MEM16(0x093C) -+#define TCD0_CCDBUF _SFR_MEM16(0x093E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCD2_CTRLA _SFR_MEM8(0x0900) -+#define TCD2_CTRLB _SFR_MEM8(0x0901) -+#define TCD2_CTRLC _SFR_MEM8(0x0902) -+#define TCD2_CTRLE _SFR_MEM8(0x0904) -+#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD2_CTRLF _SFR_MEM8(0x0909) -+#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD2_LCNT _SFR_MEM8(0x0920) -+#define TCD2_HCNT _SFR_MEM8(0x0921) -+#define TCD2_LPER _SFR_MEM8(0x0926) -+#define TCD2_HPER _SFR_MEM8(0x0927) -+#define TCD2_LCMPA _SFR_MEM8(0x0928) -+#define TCD2_HCMPA _SFR_MEM8(0x0929) -+#define TCD2_LCMPB _SFR_MEM8(0x092A) -+#define TCD2_HCMPB _SFR_MEM8(0x092B) -+#define TCD2_LCMPC _SFR_MEM8(0x092C) -+#define TCD2_HCMPC _SFR_MEM8(0x092D) -+#define TCD2_LCMPD _SFR_MEM8(0x092E) -+#define TCD2_HCMPD _SFR_MEM8(0x092F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCD1_CTRLA _SFR_MEM8(0x0940) -+#define TCD1_CTRLB _SFR_MEM8(0x0941) -+#define TCD1_CTRLC _SFR_MEM8(0x0942) -+#define TCD1_CTRLD _SFR_MEM8(0x0943) -+#define TCD1_CTRLE _SFR_MEM8(0x0944) -+#define TCD1_INTCTRLA _SFR_MEM8(0x0946) -+#define TCD1_INTCTRLB _SFR_MEM8(0x0947) -+#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) -+#define TCD1_CTRLFSET _SFR_MEM8(0x0949) -+#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) -+#define TCD1_CTRLGSET _SFR_MEM8(0x094B) -+#define TCD1_INTFLAGS _SFR_MEM8(0x094C) -+#define TCD1_TEMP _SFR_MEM8(0x094F) -+#define TCD1_CNT _SFR_MEM16(0x0960) -+#define TCD1_PER _SFR_MEM16(0x0966) -+#define TCD1_CCA _SFR_MEM16(0x0968) -+#define TCD1_CCB _SFR_MEM16(0x096A) -+#define TCD1_PERBUF _SFR_MEM16(0x0976) -+#define TCD1_CCABUF _SFR_MEM16(0x0978) -+#define TCD1_CCBBUF _SFR_MEM16(0x097A) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESD_CTRLA _SFR_MEM8(0x0990) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD0_DATA _SFR_MEM8(0x09A0) -+#define USARTD0_STATUS _SFR_MEM8(0x09A1) -+#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -+#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -+#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD1_DATA _SFR_MEM8(0x09B0) -+#define USARTD1_STATUS _SFR_MEM8(0x09B1) -+#define USARTD1_CTRLA _SFR_MEM8(0x09B3) -+#define USARTD1_CTRLB _SFR_MEM8(0x09B4) -+#define USARTD1_CTRLC _SFR_MEM8(0x09B5) -+#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) -+#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPID_CTRL _SFR_MEM8(0x09C0) -+#define SPID_INTCTRL _SFR_MEM8(0x09C1) -+#define SPID_STATUS _SFR_MEM8(0x09C2) -+#define SPID_DATA _SFR_MEM8(0x09C3) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCE0_CTRLA _SFR_MEM8(0x0A00) -+#define TCE0_CTRLB _SFR_MEM8(0x0A01) -+#define TCE0_CTRLC _SFR_MEM8(0x0A02) -+#define TCE0_CTRLD _SFR_MEM8(0x0A03) -+#define TCE0_CTRLE _SFR_MEM8(0x0A04) -+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE0_TEMP _SFR_MEM8(0x0A0F) -+#define TCE0_CNT _SFR_MEM16(0x0A20) -+#define TCE0_PER _SFR_MEM16(0x0A26) -+#define TCE0_CCA _SFR_MEM16(0x0A28) -+#define TCE0_CCB _SFR_MEM16(0x0A2A) -+#define TCE0_CCC _SFR_MEM16(0x0A2C) -+#define TCE0_CCD _SFR_MEM16(0x0A2E) -+#define TCE0_PERBUF _SFR_MEM16(0x0A36) -+#define TCE0_CCABUF _SFR_MEM16(0x0A38) -+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESE_CTRLA _SFR_MEM8(0x0A90) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE0_DATA _SFR_MEM8(0x0AA0) -+#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -+#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -+#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -+#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -+#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -+#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* VPORT - Virtual Ports */ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* CLK.USBCTRL bit masks and bit positions */ -+#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -+#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -+#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -+#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -+#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -+#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -+#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -+#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ -+ -+#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -+#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -+#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ -+ -+#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_USB_bm 0x40 /* USB bit mask. */ -+#define PR_USB_bp 6 /* USB bit position. */ -+ -+#define PR_AES_bm 0x10 /* AES bit mask. */ -+#define PR_AES_bp 4 /* AES bit position. */ -+ -+#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -+#define PR_EBI_bp 3 /* External Bus Interface bit position. */ -+ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -+#define PR_DMA_bp 0 /* DMA-Controller bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -+#define PR_DAC_bp 2 /* Port A DAC bit position. */ -+ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPB bit masks and bit positions */ -+/* PR_DAC Predefined. */ -+/* PR_DAC Predefined. */ -+ -+/* PR_ADC Predefined. */ -+/* PR_ADC Predefined. */ -+ -+/* PR_AC Predefined. */ -+/* PR_AC Predefined. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -+#define PR_USART1_bp 5 /* Port C USART1 bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -+#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ -+ -+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -+ -+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ -+ -+/* PR.PRPD bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPE bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPF bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART1 Predefined. */ -+/* PR_USART1 Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_HIRES Predefined. */ -+/* PR_HIRES Predefined. */ -+ -+/* PR_TC1 Predefined. */ -+/* PR_TC1 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -+#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -+#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ -+ -+#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ -+ -+#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -+#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.MCUCR bit masks and bit positions */ -+#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -+#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ -+ -+/* MCU.ANAINIT bit masks and bit positions */ -+#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -+#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -+#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -+#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -+#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -+#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ -+ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -+#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ -+ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.AWEXLOCK bit masks and bit positions */ -+#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ -+#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ -+ -+#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ -+#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ -+ -+#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ -+#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ -+ -+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* PORTCFG - Port Configuration */ -+/* PORTCFG.VPCTRLA bit masks and bit positions */ -+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ -+ -+/* PORTCFG.VPCTRLB bit masks and bit positions */ -+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ -+ -+/* PORTCFG.CLKEVOUT bit masks and bit positions */ -+#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ -+ -+#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -+#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -+#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -+#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -+#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -+#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ -+ -+#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -+#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ -+ -+#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -+#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ -+ -+/* PORTCFG.EBIOUT bit masks and bit positions */ -+#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ -+#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ -+#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ -+#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ -+#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ -+#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ -+ -+#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ -+#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ -+#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ -+#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ -+#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ -+#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ -+ -+/* PORTCFG.EVOUTSEL bit masks and bit positions */ -+#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -+#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -+#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -+#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -+#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -+#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -+#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -+#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ -+ -+/* AES - AES Module */ -+/* AES.CTRL bit masks and bit positions */ -+#define AES_START_bm 0x80 /* Start/Run bit mask. */ -+#define AES_START_bp 7 /* Start/Run bit position. */ -+ -+#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -+#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ -+ -+#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -+#define AES_RESET_bp 5 /* AES Software Reset bit position. */ -+ -+#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -+#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ -+ -+#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -+#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ -+ -+/* AES.STATUS bit masks and bit positions */ -+#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -+#define AES_ERROR_bp 7 /* AES Error bit position. */ -+ -+#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -+#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ -+ -+/* AES.INTCTRL bit masks and bit positions */ -+#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -+#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* DMA - DMA Controller */ -+/* DMA_CH.CTRLA bit masks and bit positions */ -+#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -+#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ -+ -+#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -+#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ -+ -+#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -+#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ -+ -+#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -+#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ -+ -+#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -+#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ -+ -+#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -+#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -+#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -+#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -+#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -+#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ -+ -+/* DMA_CH.CTRLB bit masks and bit positions */ -+#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -+#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ -+ -+#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -+#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ -+ -+#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -+#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ -+ -+#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -+#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -+#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -+#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -+#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -+#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ -+ -+#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -+#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -+#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -+#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -+#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -+#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ -+ -+/* DMA_CH.ADDRCTRL bit masks and bit positions */ -+#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -+#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -+#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -+#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -+#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -+#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ -+ -+#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -+#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -+#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -+#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -+#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -+#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ -+ -+#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -+#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -+#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -+#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -+#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -+#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ -+ -+#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -+#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -+#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -+#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -+#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -+#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ -+ -+/* DMA_CH.TRIGSRC bit masks and bit positions */ -+#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -+#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -+#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -+#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -+#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -+#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -+#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -+#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -+#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -+#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -+#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -+#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -+#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -+#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -+#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -+#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -+#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -+#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ -+ -+/* DMA.CTRL bit masks and bit positions */ -+#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -+#define DMA_ENABLE_bp 7 /* Enable bit position. */ -+ -+#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -+#define DMA_RESET_bp 6 /* Software Reset bit position. */ -+ -+#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ -+#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ -+#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ -+#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ -+#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ -+#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ -+ -+#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ -+#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ -+#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ -+#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ -+#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ -+#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ -+ -+/* DMA.INTFLAGS bit masks and bit positions */ -+#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ -+ -+/* DMA.STATUS bit masks and bit positions */ -+#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ -+#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ -+ -+#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ -+#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ -+ -+#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -+#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ -+ -+#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -+#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ -+ -+#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ -+#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ -+ -+#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ -+#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ -+ -+#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -+#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ -+ -+#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -+#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH4MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH5MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH6MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH7MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_QDIRM Predefined. */ -+/* EVSYS_QDIRM Predefined. */ -+ -+/* EVSYS_QDIEN Predefined. */ -+/* EVSYS_QDIEN Predefined. */ -+ -+/* EVSYS_QDEN Predefined. */ -+/* EVSYS_QDEN Predefined. */ -+ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH4CTRL bit masks and bit positions */ -+/* EVSYS_QDIRM Predefined. */ -+/* EVSYS_QDIRM Predefined. */ -+ -+/* EVSYS_QDIEN Predefined. */ -+/* EVSYS_QDIEN Predefined. */ -+ -+/* EVSYS_QDEN Predefined. */ -+/* EVSYS_QDEN Predefined. */ -+ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH5CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH6CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH7CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0x7F /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ -+ -+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ -+ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -+#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ -+#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -+#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -+#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -+#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -+#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -+#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -+#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -+#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -+#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -+#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ -+ -+#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -+#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -+#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -+#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -+#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -+#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -+#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -+#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -+#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -+#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ -+#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ -+#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ -+#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ -+#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ -+#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ -+ -+#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ -+#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ -+ -+#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ -+#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ -+ -+#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ -+#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ -+ -+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ -+#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ -+#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ -+ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ -+#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ -+#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ -+#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ -+#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ -+#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ -+ -+#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -+#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ -+#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ -+ -+#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ -+#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ -+ -+#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ -+#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ -+ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* DAC - Digital/Analog Converter */ -+/* DAC.CTRLA bit masks and bit positions */ -+#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -+#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ -+ -+#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -+#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ -+ -+#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -+#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ -+ -+#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -+#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ -+ -+#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define DAC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* DAC.CTRLB bit masks and bit positions */ -+#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -+#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -+#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -+#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -+#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -+#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ -+ -+#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -+#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ -+ -+#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -+#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ -+ -+/* DAC.CTRLC bit masks and bit positions */ -+#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -+#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -+#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -+#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -+#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -+#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ -+ -+#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -+#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ -+ -+/* DAC.EVCTRL bit masks and bit positions */ -+#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -+#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ -+ -+#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -+#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -+#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -+#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -+#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -+#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -+#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -+#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ -+ -+/* DAC.STATUS bit masks and bit positions */ -+#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -+#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ -+ -+#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -+#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ -+ -+/* DAC.CH0GAINCAL bit masks and bit positions */ -+#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -+#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -+#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -+#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -+#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -+#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -+#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -+#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -+#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -+#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -+#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -+#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -+#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -+#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -+#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -+#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ -+ -+/* DAC.CH0OFFSETCAL bit masks and bit positions */ -+#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -+#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -+#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -+#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -+#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -+#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -+#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -+#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -+#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -+#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -+#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -+#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -+#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -+#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -+#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -+#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ -+ -+/* DAC.CH1GAINCAL bit masks and bit positions */ -+#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -+#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -+#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -+#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -+#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -+#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -+#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -+#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -+#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -+#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -+#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -+#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -+#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -+#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -+#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -+#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ -+ -+/* DAC.CH1OFFSETCAL bit masks and bit positions */ -+#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -+#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -+#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -+#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -+#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -+#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -+#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -+#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -+#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -+#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -+#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -+#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -+#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -+#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -+#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -+#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ -+#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HSMODE Predefined. */ -+/* AC_HSMODE Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* RTC - Real-Time Counter */ -+/* RTC.CTRL bit masks and bit positions */ -+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ -+ -+/* RTC.STATUS bit masks and bit positions */ -+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC.INTCTRL bit masks and bit positions */ -+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC.INTFLAGS bit masks and bit positions */ -+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* USB - USB */ -+/* USB_EP.STATUS bit masks and bit positions */ -+#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -+#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ -+ -+#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -+#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ -+ -+#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -+#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ -+ -+#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -+#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ -+ -+#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -+#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ -+ -+#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -+#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ -+ -+#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -+#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ -+ -+#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -+#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ -+ -+#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ -+ -+#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ -+ -+#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -+#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ -+ -+/* USB_EP.CTRL bit masks and bit positions */ -+#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -+#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -+#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -+#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -+#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -+#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ -+ -+#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -+#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ -+ -+#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -+#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ -+ -+#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -+#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ -+ -+#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -+#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ -+ -+#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -+#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -+#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -+#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -+#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -+#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -+#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -+#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ -+ -+/* USB_EP.CNT bit masks and bit positions */ -+#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -+#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ -+ -+/* USB.CTRLA bit masks and bit positions */ -+#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -+#define USB_ENABLE_bp 7 /* USB Enable bit position. */ -+ -+#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -+#define USB_SPEED_bp 6 /* Speed Select bit position. */ -+ -+#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -+#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ -+ -+#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -+#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ -+ -+#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -+#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -+#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -+#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -+#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -+#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -+#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -+#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -+#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -+#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ -+ -+/* USB.CTRLB bit masks and bit positions */ -+#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -+#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ -+ -+#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -+#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ -+ -+#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -+#define USB_GNACK_bp 1 /* Global NACK bit position. */ -+ -+#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -+#define USB_ATTACH_bp 0 /* Attach bit position. */ -+ -+/* USB.STATUS bit masks and bit positions */ -+#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -+#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ -+ -+#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -+#define USB_RESUME_bp 2 /* Resume bit position. */ -+ -+#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -+#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ -+ -+#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -+#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ -+ -+/* USB.ADDR bit masks and bit positions */ -+#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -+#define USB_ADDR_gp 0 /* Device Address group position. */ -+#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -+#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -+#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -+#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -+#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -+#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -+#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -+#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -+#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -+#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -+#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -+#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -+#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -+#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ -+ -+/* USB.FIFOWP bit masks and bit positions */ -+#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -+#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -+#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -+#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -+#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -+#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -+#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -+#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -+#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -+#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -+#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -+#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ -+ -+/* USB.FIFORP bit masks and bit positions */ -+#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -+#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -+#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -+#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -+#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -+#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -+#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -+#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -+#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -+#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -+#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -+#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ -+ -+/* USB.INTCTRLA bit masks and bit positions */ -+#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -+#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ -+ -+#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -+#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ -+ -+#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -+#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ -+ -+#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -+#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ -+ -+#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* USB.INTCTRLB bit masks and bit positions */ -+#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -+#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ -+ -+#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -+#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ -+ -+/* USB.INTFLAGSACLR bit masks and bit positions */ -+#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -+#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ -+ -+#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -+#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ -+ -+#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -+#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ -+ -+#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -+#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ -+ -+#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -+#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ -+ -+#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -+#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ -+ -+#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -+#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ -+ -+#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -+#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSASET bit masks and bit positions */ -+/* USB_SOFIF Predefined. */ -+/* USB_SOFIF Predefined. */ -+ -+/* USB_SUSPENDIF Predefined. */ -+/* USB_SUSPENDIF Predefined. */ -+ -+/* USB_RESUMEIF Predefined. */ -+/* USB_RESUMEIF Predefined. */ -+ -+/* USB_RSTIF Predefined. */ -+/* USB_RSTIF Predefined. */ -+ -+/* USB_CRCIF Predefined. */ -+/* USB_CRCIF Predefined. */ -+ -+/* USB_UNFIF Predefined. */ -+/* USB_UNFIF Predefined. */ -+ -+/* USB_OVFIF Predefined. */ -+/* USB_OVFIF Predefined. */ -+ -+/* USB_STALLIF Predefined. */ -+/* USB_STALLIF Predefined. */ -+ -+/* USB.INTFLAGSBCLR bit masks and bit positions */ -+#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -+#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ -+ -+#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -+#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSBSET bit masks and bit positions */ -+/* USB_TRNIF Predefined. */ -+/* USB_TRNIF Predefined. */ -+ -+/* USB_SETUPIF Predefined. */ -+/* USB_SETUPIF Predefined. */ -+ -+/* PORT - I/O Port Configuration */ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ -+ -+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -+#define PORT_SPI_bp 5 /* SPI bit position. */ -+ -+#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -+#define PORT_USART0_bp 4 /* USART0 bit position. */ -+ -+#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -+#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ -+ -+#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -+#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ -+ -+#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -+#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ -+ -+#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -+#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ -+ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC0.CTRLA bit masks and bit positions */ -+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC0.CTRLB bit masks and bit positions */ -+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ -+ -+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ -+ -+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC0.CTRLC bit masks and bit positions */ -+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ -+ -+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ -+ -+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC0.CTRLD bit masks and bit positions */ -+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC0_EVACT_gp 5 /* Event Action group position. */ -+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC0.CTRLE bit masks and bit positions */ -+#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC0.INTCTRLA bit masks and bit positions */ -+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC0.INTCTRLB bit masks and bit positions */ -+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ -+ -+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ -+ -+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC0.CTRLFCLR bit masks and bit positions */ -+#define TC0_CMD_gm 0x0C /* Command group mask. */ -+#define TC0_CMD_gp 2 /* Command group position. */ -+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC0_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC0_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC0_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC0.CTRLFSET bit masks and bit positions */ -+/* TC0_CMD Predefined. */ -+/* TC0_CMD Predefined. */ -+ -+/* TC0_LUPD Predefined. */ -+/* TC0_LUPD Predefined. */ -+ -+/* TC0_DIR Predefined. */ -+/* TC0_DIR Predefined. */ -+ -+/* TC0.CTRLGCLR bit masks and bit positions */ -+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ -+ -+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ -+ -+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC0.CTRLGSET bit masks and bit positions */ -+/* TC0_CCDBV Predefined. */ -+/* TC0_CCDBV Predefined. */ -+ -+/* TC0_CCCBV Predefined. */ -+/* TC0_CCCBV Predefined. */ -+ -+/* TC0_CCBBV Predefined. */ -+/* TC0_CCBBV Predefined. */ -+ -+/* TC0_CCABV Predefined. */ -+/* TC0_CCABV Predefined. */ -+ -+/* TC0_PERBV Predefined. */ -+/* TC0_PERBV Predefined. */ -+ -+/* TC0.INTFLAGS bit masks and bit positions */ -+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ -+ -+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ -+ -+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC1.CTRLA bit masks and bit positions */ -+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC1.CTRLB bit masks and bit positions */ -+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC1.CTRLC bit masks and bit positions */ -+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC1.CTRLD bit masks and bit positions */ -+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC1_EVACT_gp 5 /* Event Action group position. */ -+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC1.CTRLE bit masks and bit positions */ -+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ -+ -+/* TC1.INTCTRLA bit masks and bit positions */ -+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC1.INTCTRLB bit masks and bit positions */ -+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC1.CTRLFCLR bit masks and bit positions */ -+#define TC1_CMD_gm 0x0C /* Command group mask. */ -+#define TC1_CMD_gp 2 /* Command group position. */ -+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC1_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC1_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC1_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC1.CTRLFSET bit masks and bit positions */ -+/* TC1_CMD Predefined. */ -+/* TC1_CMD Predefined. */ -+ -+/* TC1_LUPD Predefined. */ -+/* TC1_LUPD Predefined. */ -+ -+/* TC1_DIR Predefined. */ -+/* TC1_DIR Predefined. */ -+ -+/* TC1.CTRLGCLR bit masks and bit positions */ -+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC1.CTRLGSET bit masks and bit positions */ -+/* TC1_CCBBV Predefined. */ -+/* TC1_CCBBV Predefined. */ -+ -+/* TC1_CCABV Predefined. */ -+/* TC1_CCABV Predefined. */ -+ -+/* TC1_PERBV Predefined. */ -+/* TC1_PERBV Predefined. */ -+ -+/* TC1.INTFLAGS bit masks and bit positions */ -+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+/* TC2.CTRLA bit masks and bit positions */ -+#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC2.CTRLB bit masks and bit positions */ -+#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -+#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ -+ -+#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -+#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ -+ -+#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -+#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ -+ -+#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -+#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ -+ -+#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -+#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ -+ -+#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -+#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ -+ -+#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -+#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ -+ -+#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -+#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ -+ -+/* TC2.CTRLC bit masks and bit positions */ -+#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -+#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ -+ -+#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -+#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ -+ -+#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -+#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ -+ -+#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -+#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ -+ -+#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -+#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ -+ -+#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -+#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ -+ -+#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -+#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ -+ -+#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -+#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ -+ -+/* TC2.CTRLE bit masks and bit positions */ -+#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC2.INTCTRLA bit masks and bit positions */ -+#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -+#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -+#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -+#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -+#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -+#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ -+ -+#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -+#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -+#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -+#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -+#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -+#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ -+ -+/* TC2.INTCTRLB bit masks and bit positions */ -+#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -+#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -+#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -+#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -+#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -+#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -+#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -+#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -+#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -+#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -+#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -+#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -+#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -+#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -+#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -+#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -+#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -+#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -+#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -+#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -+#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ -+ -+/* TC2.CTRLF bit masks and bit positions */ -+#define TC2_CMD_gm 0x0C /* Command group mask. */ -+#define TC2_CMD_gp 2 /* Command group position. */ -+#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC2_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -+#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -+#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -+#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -+#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -+#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ -+ -+/* TC2.INTFLAGS bit masks and bit positions */ -+#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -+#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ -+ -+#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -+#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ -+ -+#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -+#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ -+ -+#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -+#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ -+ -+#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ -+ -+#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ -+ -+/* AWEX - Timer/Counter Advanced Waveform Extension */ -+/* AWEX.CTRL bit masks and bit positions */ -+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ -+ -+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ -+ -+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ -+ -+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ -+ -+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ -+ -+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ -+ -+/* AWEX.FDCTRL bit masks and bit positions */ -+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ -+ -+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ -+ -+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ -+ -+/* AWEX.STATUS bit masks and bit positions */ -+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ -+ -+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ -+ -+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ -+ -+/* AWEX.STATUSSET bit masks and bit positions */ -+/* AWEX_FDF Predefined. */ -+/* AWEX_FDF Predefined. */ -+ -+/* AWEX_DTHSBUFV Predefined. */ -+/* AWEX_DTHSBUFV Predefined. */ -+ -+/* AWEX_DTLSBUFV Predefined. */ -+/* AWEX_DTLSBUFV Predefined. */ -+ -+/* HIRES - Timer/Counter High-Resolution Extension */ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -+#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* LOCKBIT - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT0_vect_num 2 -+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -+#define PORTC_INT1_vect_num 3 -+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT0_vect_num 4 -+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -+#define PORTR_INT1_vect_num 5 -+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ -+ -+/* DMA interrupt vectors */ -+#define DMA_CH0_vect_num 6 -+#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -+#define DMA_CH1_vect_num 7 -+#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -+#define DMA_CH2_vect_num 8 -+#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ -+#define DMA_CH3_vect_num 9 -+#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ -+ -+/* RTC interrupt vectors */ -+#define RTC_OVF_vect_num 10 -+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -+#define RTC_COMP_vect_num 11 -+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 12 -+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 13 -+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_OVF_vect_num 14 -+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LUNF_vect_num 14 -+#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_ERR_vect_num 15 -+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_HUNF_vect_num 15 -+#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCA_vect_num 16 -+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPA_vect_num 16 -+#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCB_vect_num 17 -+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPB_vect_num 17 -+#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCC_vect_num 18 -+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPC_vect_num 18 -+#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCD_vect_num 19 -+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPD_vect_num 19 -+#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ -+ -+/* TCC1 interrupt vectors */ -+#define TCC1_OVF_vect_num 20 -+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -+#define TCC1_ERR_vect_num 21 -+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -+#define TCC1_CCA_vect_num 22 -+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -+#define TCC1_CCB_vect_num 23 -+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 24 -+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 25 -+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 26 -+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 27 -+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ -+ -+/* USARTC1 interrupt vectors */ -+#define USARTC1_RXC_vect_num 28 -+#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ -+#define USARTC1_DRE_vect_num 29 -+#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ -+#define USARTC1_TXC_vect_num 30 -+#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ -+ -+/* AES interrupt vectors */ -+#define AES_INT_vect_num 31 -+#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 32 -+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -+#define NVM_SPM_vect_num 33 -+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ -+ -+/* PORTB interrupt vectors */ -+#define PORTB_INT0_vect_num 34 -+#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -+#define PORTB_INT1_vect_num 35 -+#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ -+ -+/* PORTE interrupt vectors */ -+#define PORTE_INT0_vect_num 43 -+#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -+#define PORTE_INT1_vect_num 44 -+#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ -+ -+/* TWIE interrupt vectors */ -+#define TWIE_TWIS_vect_num 45 -+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -+#define TWIE_TWIM_vect_num 46 -+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_OVF_vect_num 47 -+#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -+#define TCE0_ERR_vect_num 48 -+#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -+#define TCE0_CCA_vect_num 49 -+#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -+#define TCE0_CCB_vect_num 50 -+#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -+#define TCE0_CCC_vect_num 51 -+#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -+#define TCE0_CCD_vect_num 52 -+#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ -+ -+/* USARTE0 interrupt vectors */ -+#define USARTE0_RXC_vect_num 58 -+#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -+#define USARTE0_DRE_vect_num 59 -+#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -+#define USARTE0_TXC_vect_num 60 -+#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT0_vect_num 64 -+#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -+#define PORTD_INT1_vect_num 65 -+#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ -+ -+/* PORTA interrupt vectors */ -+#define PORTA_INT0_vect_num 66 -+#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -+#define PORTA_INT1_vect_num 67 -+#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ -+ -+/* ACA interrupt vectors */ -+#define ACA_AC0_vect_num 68 -+#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -+#define ACA_AC1_vect_num 69 -+#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -+#define ACA_ACW_vect_num 70 -+#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ -+ -+/* ADCA interrupt vectors */ -+#define ADCA_CH0_vect_num 71 -+#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -+#define ADCA_CH1_vect_num 72 -+#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ -+#define ADCA_CH2_vect_num 73 -+#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ -+#define ADCA_CH3_vect_num 74 -+#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_OVF_vect_num 77 -+#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LUNF_vect_num 77 -+#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_ERR_vect_num 78 -+#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_HUNF_vect_num 78 -+#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCA_vect_num 79 -+#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPA_vect_num 79 -+#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCB_vect_num 80 -+#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPB_vect_num 80 -+#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCC_vect_num 81 -+#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPC_vect_num 81 -+#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCD_vect_num 82 -+#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPD_vect_num 82 -+#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ -+ -+/* TCD1 interrupt vectors */ -+#define TCD1_OVF_vect_num 83 -+#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ -+#define TCD1_ERR_vect_num 84 -+#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ -+#define TCD1_CCA_vect_num 85 -+#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ -+#define TCD1_CCB_vect_num 86 -+#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ -+ -+/* SPID interrupt vectors */ -+#define SPID_INT_vect_num 87 -+#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ -+ -+/* USARTD0 interrupt vectors */ -+#define USARTD0_RXC_vect_num 88 -+#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -+#define USARTD0_DRE_vect_num 89 -+#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -+#define USARTD0_TXC_vect_num 90 -+#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ -+ -+/* USARTD1 interrupt vectors */ -+#define USARTD1_RXC_vect_num 91 -+#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ -+#define USARTD1_DRE_vect_num 92 -+#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ -+#define USARTD1_TXC_vect_num 93 -+#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ -+ -+/* USB interrupt vectors */ -+#define USB_BUSEVENT_vect_num 125 -+#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -+#define USB_TRNCOMPL_vect_num 126 -+#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (127 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (69632) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (65536) -+#define APP_SECTION_PAGE_SIZE (256) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0xF000) -+#define APPTABLE_SECTION_SIZE (4096) -+#define APPTABLE_SECTION_PAGE_SIZE (256) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x10000) -+#define BOOT_SECTION_SIZE (4096) -+#define BOOT_SECTION_PAGE_SIZE (256) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (12288) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (2048) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (4096) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (2048) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (6) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (256) -+#define USER_SIGNATURES_PAGE_SIZE (256) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (64) -+#define PROD_SIGNATURES_PAGE_SIZE (256) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 256 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 6 -+ -+/* Fuse Byte 0 Reserved */ -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x96 -+#define SIGNATURE_2 0x46 -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA64A4U_H_INCLUDED */ -+ -diff --git a/include/avr/iox64b1.h b/include/avr/iox64b1.h -new file mode 100644 -index 0000000..1eb283b ---- /dev/null -+++ b/include/avr/iox64b1.h -@@ -0,0 +1,6413 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox64b1.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA64B1_H_INCLUDED -+#define _AVR_ATXMEGA64B1_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+VPORT - Virtual Ports -+-------------------------------------------------------------------------- -+*/ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t USBCTRL; /* USB Control Register */ -+} CLK_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+/* USB Prescaler Division Factor */ -+typedef enum CLK_USBPSDIV_enum -+{ -+ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ -+ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ -+ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ -+ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ -+ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ -+ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -+} CLK_USBPSDIV_t; -+ -+/* USB Clock Source */ -+typedef enum CLK_USBSRC_enum -+{ -+ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ -+ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -+} CLK_USBSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control Register */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C0_gc = (0x01<<0), /* External Clock on port C0 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C1_gc = (0x05<<0), /* External Clock on port C1 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C2_gc = (0x09<<0), /* External Clock on port C2 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C3_gc = (0x0D<<0), /* External Clock on port C3 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C4_gc = (0x11<<0), /* External Clock on port C4 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C5_gc = (0x15<<0), /* External Clock on port C5 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C6_gc = (0x19<<0), /* External Clock on port C6 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C7_gc = (0x1D<<0), /* External Clock on port C7 - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+/* 2 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC2MCREF_enum -+{ -+ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC2MCREF_t; -+ -+/* 32 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC32MCREF_enum -+{ -+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -+} OSC_RC32MCREF_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PR - Power Reduction -+-------------------------------------------------------------------------- -+*/ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t PRPB; /* Power Reduction Port B */ -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t reserved_0x04; -+ register8_t PRPE; /* Power Reduction Port E */ -+} PR_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t JTAGUID; /* JTAG User ID */ -+ register8_t reserved_0x05; -+ register8_t MCUCR; /* MCU Control */ -+ register8_t ANAINIT; /* Analog Startup Delay */ -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t AWEXLOCK; /* AWEX Lock */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORTCFG - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t VPCTRLA; /* Virtual Port Control Register A */ -+ register8_t VPCTRLB; /* Virtual Port Control Register B */ -+ register8_t CLKEVOUT; /* Clock and Event Out Register */ -+ register8_t reserved_0x05; -+ register8_t EVOUTSEL; /* Event Output Select */ -+} PORTCFG_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP02MAP_enum -+{ -+ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ -+ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ -+ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ -+ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ -+ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ -+ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ -+ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ -+ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -+} PORTCFG_VP02MAP_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP13MAP_enum -+{ -+ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ -+ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ -+ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ -+ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ -+ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ -+ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ -+ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ -+ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -+} PORTCFG_VP13MAP_t; -+ -+/* System Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC_gc = (0x01<<0), /* System Clock Output on Port C */ -+ PORTCFG_CLKOUT_PE_gc = (0x03<<0), /* System Clock Output on Port E */ -+} PORTCFG_CLKOUT_t; -+ -+/* Peripheral Clock Output Select */ -+typedef enum PORTCFG_CLKOUTSEL_enum -+{ -+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -+} PORTCFG_CLKOUTSEL_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC_gc = (0x01<<4), /* Event Channel 0 Output on Port C */ -+ PORTCFG_EVOUT_PE_gc = (0x03<<4), /* Event Channel 0 Output on Port E */ -+} PORTCFG_EVOUT_t; -+ -+/* Clock and Event Output Port */ -+typedef enum PORTCFG_CLKEVPIN_enum -+{ -+ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ -+ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -+} PORTCFG_CLKEVPIN_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<2), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<2), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<2), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<2), /* Event Channel 3 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AES - AES Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* AES Module */ -+typedef struct AES_struct -+{ -+ register8_t CTRL; /* AES Control Register */ -+ register8_t STATUS; /* AES Status Register */ -+ register8_t STATE; /* AES State Register */ -+ register8_t KEY; /* AES Key Register */ -+ register8_t INTCTRL; /* AES Interrupt Control Register */ -+} AES_t; -+ -+/* Interrupt level */ -+typedef enum AES_INTLVL_enum -+{ -+ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} AES_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ -+ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DMA - DMA Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* DMA Channel */ -+typedef struct DMA_CH_struct -+{ -+ register8_t CTRLA; /* Channel Control */ -+ register8_t CTRLB; /* Channel Control */ -+ register8_t ADDRCTRL; /* Address Control */ -+ register8_t TRIGSRC; /* Channel Trigger Source */ -+ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ -+ register8_t REPCNT; /* Channel Repeat Count */ -+ register8_t reserved_0x07; -+ register8_t SRCADDR0; /* Channel Source Address 0 */ -+ register8_t SRCADDR1; /* Channel Source Address 1 */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t DESTADDR0; /* Channel Destination Address 0 */ -+ register8_t DESTADDR1; /* Channel Destination Address 1 */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} DMA_CH_t; -+ -+ -+/* DMA Controller */ -+typedef struct DMA_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t reserved_0x01; -+ register8_t reserved_0x02; -+ register8_t INTFLAGS; /* Transfer Interrupt Status */ -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x05; -+ _WORDREGISTER(TEMP); /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ DMA_CH_t CH0; /* DMA Channel 0 */ -+ DMA_CH_t CH1; /* DMA Channel 1 */ -+} DMA_t; -+ -+/* Burst mode */ -+typedef enum DMA_CH_BURSTLEN_enum -+{ -+ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ -+ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ -+ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ -+ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -+} DMA_CH_BURSTLEN_t; -+ -+/* Source address reload mode */ -+typedef enum DMA_CH_SRCRELOAD_enum -+{ -+ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ -+ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ -+ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ -+ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -+} DMA_CH_SRCRELOAD_t; -+ -+/* Source addressing mode */ -+typedef enum DMA_CH_SRCDIR_enum -+{ -+ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ -+ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ -+ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -+} DMA_CH_SRCDIR_t; -+ -+/* Destination adress reload mode */ -+typedef enum DMA_CH_DESTRELOAD_enum -+{ -+ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ -+ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ -+ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ -+ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -+} DMA_CH_DESTRELOAD_t; -+ -+/* Destination adressing mode */ -+typedef enum DMA_CH_DESTDIR_enum -+{ -+ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ -+ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ -+ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -+} DMA_CH_DESTDIR_t; -+ -+/* Transfer trigger source */ -+typedef enum DMA_CH_TRIGSRC_enum -+{ -+ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ -+ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ -+ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ -+ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ -+ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ -+ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ -+ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ -+ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ -+ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ -+ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ -+ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ -+ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ -+ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ -+} DMA_CH_TRIGSRC_t; -+ -+/* Double buffering mode */ -+typedef enum DMA_DBUFMODE_enum -+{ -+ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ -+ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ -+} DMA_DBUFMODE_t; -+ -+/* Priority mode */ -+typedef enum DMA_PRIMODE_enum -+{ -+ DMA_PRIMODE_RR01_gc = (0x00<<0), /* Round Robin */ -+ DMA_PRIMODE_CH0RR1_gc = (0x01<<0), /* Channel 0 > channel 1 */ -+} DMA_PRIMODE_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_ERRINTLVL_enum -+{ -+ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ -+ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ -+ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -+} DMA_CH_ERRINTLVL_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_TRNINTLVL_enum -+{ -+ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ -+ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -+} DMA_CH_TRNINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+} EVSYS_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ -+ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ -+ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ -+ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ -+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ -+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ -+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ -+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ -+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ -+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ -+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ -+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ -+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ -+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ -+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ -+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ -+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ -+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ -+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ -+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ -+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ -+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ -+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ -+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ -+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ -+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ -+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ -+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ -+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ -+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -+} EVSYS_CHMUX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ -+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ -+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ -+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ -+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} NVM_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t reserved_0x07; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+} ADC_t; -+ -+/* Current Limitation */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -+} ADC_CURRLIMIT_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+} ADC_CH_MUXNEG_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ -+ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ -+ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ -+ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+ register8_t CURRCTRL; /* Current Source Control Register */ -+ register8_t CURRCALIB; /* Current Source Calibration Register */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC - Real-Time Counter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Real-Time Counter */ -+typedef struct RTC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary register */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ _WORDREGISTER(CNT); /* Count Register */ -+ _WORDREGISTER(PER); /* Period Register */ -+ _WORDREGISTER(COMP); /* Compare Register */ -+} RTC_t; -+ -+/* Prescaler Factor */ -+typedef enum RTC_PRESCALER_enum -+{ -+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ -+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ -+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ -+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ -+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ -+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ -+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ -+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -+} RTC_PRESCALER_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC_COMPINTLVL_enum -+{ -+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC_OVFINTLVL_enum -+{ -+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+} TWI_t; -+ -+/* SDA Hold Time */ -+typedef enum TWI_SDAHOLD_enum -+{ -+ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ -+ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ -+ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ -+ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -+} TWI_SDAHOLD_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USB - USB -+-------------------------------------------------------------------------- -+*/ -+ -+/* USB Endpoint */ -+typedef struct USB_EP_struct -+{ -+ register8_t STATUS; /* Endpoint Status */ -+ register8_t CTRL; /* Endpoint Control */ -+ _WORDREGISTER(CNT); /* USB Endpoint Counter */ -+ _WORDREGISTER(DATAPTR); /* Data Pointer */ -+ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -+} USB_EP_t; -+ -+ -+/* Universal Serial Bus */ -+typedef struct USB_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t FIFOWP; /* FIFO Write Pointer Register */ -+ register8_t FIFORP; /* FIFO Read Pointer Register */ -+ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ -+ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ -+ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ -+ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t reserved_0x20; -+ register8_t reserved_0x21; -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t CAL0; /* Calibration Byte 0 */ -+ register8_t CAL1; /* Calibration Byte 1 */ -+} USB_t; -+ -+ -+/* USB Endpoint Table */ -+typedef struct USB_EP_TABLE_struct -+{ -+ USB_EP_t EP0OUT; /* Endpoint 0 */ -+ USB_EP_t EP0IN; /* Endpoint 0 */ -+ USB_EP_t EP1OUT; /* Endpoint 1 */ -+ USB_EP_t EP1IN; /* Endpoint 1 */ -+ USB_EP_t EP2OUT; /* Endpoint 2 */ -+ USB_EP_t EP2IN; /* Endpoint 2 */ -+ USB_EP_t EP3OUT; /* Endpoint 3 */ -+ USB_EP_t EP3IN; /* Endpoint 3 */ -+ USB_EP_t EP4OUT; /* Endpoint 4 */ -+ USB_EP_t EP4IN; /* Endpoint 4 */ -+ USB_EP_t EP5OUT; /* Endpoint 5 */ -+ USB_EP_t EP5IN; /* Endpoint 5 */ -+ USB_EP_t EP6OUT; /* Endpoint 6 */ -+ USB_EP_t EP6IN; /* Endpoint 6 */ -+ USB_EP_t EP7OUT; /* Endpoint 7 */ -+ USB_EP_t EP7IN; /* Endpoint 7 */ -+ USB_EP_t EP8OUT; /* Endpoint 8 */ -+ USB_EP_t EP8IN; /* Endpoint 8 */ -+ USB_EP_t EP9OUT; /* Endpoint 9 */ -+ USB_EP_t EP9IN; /* Endpoint 9 */ -+ USB_EP_t EP10OUT; /* Endpoint 10 */ -+ USB_EP_t EP10IN; /* Endpoint 10 */ -+ USB_EP_t EP11OUT; /* Endpoint 11 */ -+ USB_EP_t EP11IN; /* Endpoint 11 */ -+ USB_EP_t EP12OUT; /* Endpoint 12 */ -+ USB_EP_t EP12IN; /* Endpoint 12 */ -+ USB_EP_t EP13OUT; /* Endpoint 13 */ -+ USB_EP_t EP13IN; /* Endpoint 13 */ -+ USB_EP_t EP14OUT; /* Endpoint 14 */ -+ USB_EP_t EP14IN; /* Endpoint 14 */ -+ USB_EP_t EP15OUT; /* Endpoint 15 */ -+ USB_EP_t EP15IN; /* Endpoint 15 */ -+ register8_t reserved_0x100; -+ register8_t reserved_0x101; -+ register8_t reserved_0x102; -+ register8_t reserved_0x103; -+ register8_t reserved_0x104; -+ register8_t reserved_0x105; -+ register8_t reserved_0x106; -+ register8_t reserved_0x107; -+ register8_t reserved_0x108; -+ register8_t reserved_0x109; -+ register8_t reserved_0x10A; -+ register8_t reserved_0x10B; -+ register8_t reserved_0x10C; -+ register8_t reserved_0x10D; -+ register8_t reserved_0x10E; -+ register8_t reserved_0x10F; -+ register8_t FRAMENUML; /* Frame Number Low Byte */ -+ register8_t FRAMENUMH; /* Frame Number High Byte */ -+} USB_EP_TABLE_t; -+ -+/* Interrupt level */ -+typedef enum USB_INTLVL_enum -+{ -+ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} USB_INTLVL_t; -+ -+/* USB Endpoint Type */ -+typedef enum USB_EP_TYPE_enum -+{ -+ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ -+ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ -+ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ -+ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -+} USB_EP_TYPE_t; -+ -+/* USB Endpoint Buffersize */ -+typedef enum USB_EP_BUFSIZE_enum -+{ -+ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ -+ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ -+ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ -+ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ -+ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ -+ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ -+ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ -+ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -+} USB_EP_BUFSIZE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - I/O Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INT0MASK; /* Port Interrupt 0 Mask */ -+ register8_t INT1MASK; /* Port Interrupt 1 Mask */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t REMAP; /* I/O Port Pin Remap Register */ -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Port Interrupt 0 Level */ -+typedef enum PORT_INT0LVL_enum -+{ -+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INT0LVL_t; -+ -+/* Port Interrupt 1 Level */ -+typedef enum PORT_INT1LVL_enum -+{ -+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ -+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ -+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -+} PORT_INT1LVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 0 */ -+typedef struct TC0_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC0_t; -+ -+ -+/* 16-bit Timer/Counter 1 */ -+typedef struct TC1_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+} TC1_t; -+ -+/* Clock Selection */ -+typedef enum TC_CLKSEL_enum -+{ -+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_CLKSEL_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC_WGMODE_enum -+{ -+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC_WGMODE_t; -+ -+/* Byte Mode */ -+typedef enum TC_BYTEM_enum -+{ -+ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ -+ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -+} TC_BYTEM_t; -+ -+/* Event Action */ -+typedef enum TC_EVACT_enum -+{ -+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ -+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ -+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ -+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ -+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ -+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC_EVSEL_enum -+{ -+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_EVSEL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC_ERRINTLVL_enum -+{ -+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC_OVFINTLVL_enum -+{ -+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_OVFINTLVL_t; -+ -+/* Compare or Capture D Interrupt Level */ -+typedef enum TC_CCDINTLVL_enum -+{ -+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC_CCDINTLVL_t; -+ -+/* Compare or Capture C Interrupt Level */ -+typedef enum TC_CCCINTLVL_enum -+{ -+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC_CCCINTLVL_t; -+ -+/* Compare or Capture B Interrupt Level */ -+typedef enum TC_CCBINTLVL_enum -+{ -+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_CCBINTLVL_t; -+ -+/* Compare or Capture A Interrupt Level */ -+typedef enum TC_CCAINTLVL_enum -+{ -+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_CCAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC_CMD_enum -+{ -+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AWEX - Timer/Counter Advanced Waveform Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Advanced Waveform Extension */ -+typedef struct AWEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t FDEMASK; /* Fault Detection Event Mask */ -+ register8_t FDCTRL; /* Fault Detection Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t STATUSSET; /* Status Set Register */ -+ register8_t DTBOTH; /* Dead Time Both Sides */ -+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ -+ register8_t DTLS; /* Dead Time Low Side */ -+ register8_t DTHS; /* Dead Time High Side */ -+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ -+ register8_t DTHSBUF; /* Dead Time High Side Buffer */ -+ register8_t OUTOVEN; /* Output Override Enable */ -+} AWEX_t; -+ -+/* Fault Detect Action */ -+typedef enum AWEX_FDACT_enum -+{ -+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ -+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -+} AWEX_FDACT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+HIRES - Timer/Counter High-Resolution Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register */ -+} HIRES_t; -+ -+/* High Resolution Enable */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ -+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+} IRDA_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LCD - LCD Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* LCD Controller */ -+typedef struct LCD_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t INTCTRL; /* Interrupt Enable Register */ -+ register8_t INTFLAG; /* Interrupt Flag Register */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t CTRLF; /* Control Register F */ -+ register8_t CTRLG; /* Control Register G */ -+ register8_t CTRLH; /* Control Register H */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t DATA0; /* LCD Data Register 0 */ -+ register8_t DATA1; /* LCD Data Register 1 */ -+ register8_t DATA2; /* LCD Data Register 2 */ -+ register8_t DATA3; /* LCD Data Register 3 */ -+ register8_t DATA4; /* LCD Data Register 4 */ -+ register8_t DATA5; /* LCD Data Register 5 */ -+ register8_t DATA6; /* LCD Data Register 6 */ -+ register8_t DATA7; /* LCD Data Register 7 */ -+ register8_t DATA8; /* LCD Data Register 8 */ -+ register8_t DATA9; /* LCD Data Register 9 */ -+ register8_t DATA10; /* LCD Data Register 10 */ -+ register8_t DATA11; /* LCD Data Register 11 */ -+ register8_t DATA12; /* LCD Data Register 12 */ -+ register8_t DATA13; /* LCD Data Register 13 */ -+ register8_t DATA14; /* LCD Data Register 14 */ -+ register8_t DATA15; /* LCD Data Register 15 */ -+ register8_t DATA16; /* LCD Data Register 16 */ -+ register8_t DATA17; /* LCD Data Register 17 */ -+ register8_t DATA18; /* LCD Data Register 18 */ -+ register8_t DATA19; /* LCD Data Register 19 */ -+} LCD_t; -+ -+/* LCD Blink Rate */ -+typedef enum LCD_BLINKRATE_enum -+{ -+ LCD_BLINKRATE_4Hz_gc = (0x00<<0), /* 4Hz Blink Rate */ -+ LCD_BLINKRATE_2Hz_gc = (0x01<<0), /* 2Hz Blink Rate */ -+ LCD_BLINKRATE_1Hz_gc = (0x02<<0), /* 1Hz Blink Rate */ -+ LCD_BLINKRATE_0Hz5_gc = (0x03<<0), /* 0.5Hz Blink Rate */ -+} LCD_BLINKRATE_t; -+ -+/* LCD Clock Divide */ -+typedef enum LCD_CLKDIV_enum -+{ -+ LCD_CLKDIV_DivBy1_gc = (0x00<<4), /* frame rate of 256 Hz */ -+ LCD_CLKDIV_DivBy2_gc = (0x01<<4), /* frame rate of 128 Hz */ -+ LCD_CLKDIV_DivBy3_gc = (0x02<<4), /* frame rate of 83.5 Hz */ -+ LCD_CLKDIV_DivBy4_gc = (0x03<<4), /* frame rate of 64 Hz */ -+ LCD_CLKDIV_DivBy5_gc = (0x04<<4), /* frame rate of 51.2 Hz */ -+ LCD_CLKDIV_DivBy6_gc = (0x05<<4), /* frame rate of 42.7 Hz */ -+ LCD_CLKDIV_DivBy7_gc = (0x06<<4), /* frame rate of 36.6 Hz */ -+ LCD_CLKDIV_DivBy8_gc = (0x07<<4), /* frame rate of 32 Hz */ -+} LCD_CLKDIV_t; -+ -+/* Duty Select */ -+typedef enum LCD_DUTY_enum -+{ -+ LCD_DUTY_1_4_gc = (0x00<<0), /* Duty=1/4, Bias=1/3, COM0:3 */ -+ LCD_DUTY_Static_gc = (0x01<<0), /* Duty=Static, Bias=Static, COM0 */ -+ LCD_DUTY_1_2_gc = (0x02<<0), /* Duty=1/2, Bias=1/3, COM0:1 */ -+ LCD_DUTY_1_3_gc = (0x03<<0), /* Duty=1/3, Bias=1/3, COM0:2 */ -+} LCD_DUTY_t; -+ -+/* LCD Prescaler Select */ -+typedef enum LCD_PRESC_enum -+{ -+ LCD_PRESC_8_gc = (0x00<<7), /* clk_lcd/8 */ -+ LCD_PRESC_16_gc = (0x01<<7), /* clk_lcd/16 */ -+} LCD_PRESC_t; -+ -+/* Type of Digit */ -+typedef enum LCD_TDG_enum -+{ -+ LCD_TDG_7S_3C_gc = (0x00<<6), /* 7-segment with 3 COMs */ -+ LCD_TDG_7S_4C_gc = (0x01<<6), /* 7-segment with 4 COMs */ -+ LCD_TDG_14S_4C_gc = (0x02<<6), /* 14-segment with 4 COMs */ -+ LCD_TDG_16S_3C_gc = (0x03<<6), /* 16-segment with 3 COMs */ -+} LCD_TDG_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t FUSEBYTE0; /* JTAG User ID */ -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+} NVM_FUSES_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* Timer Oscillator pin location */ -+typedef enum TOSCSEL_enum -+{ -+ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ -+ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -+} TOSCSEL_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -+} BOD_t; -+ -+/* BOD operation */ -+typedef enum BODACT_enum -+{ -+ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BODACT_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WDP_enum -+{ -+ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ -+ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ -+ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ -+ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ -+ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ -+ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ -+ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ -+ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ -+ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ -+ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ -+ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -+} WDP_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LOCKBIT - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ -+ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t USBCAL0; /* USB Calibration Byte 0 */ -+ register8_t USBCAL1; /* USB Calibration Byte 1 */ -+ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ -+ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ -+ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+ register8_t reserved_0x40; -+ register8_t reserved_0x41; -+ register8_t reserved_0x42; -+ register8_t reserved_0x43; -+ register8_t reserved_0x44; -+ register8_t reserved_0x45; -+ register8_t reserved_0x46; -+ register8_t reserved_0x47; -+} NVM_PROD_SIGNATURES_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define AES (*(AES_t *) 0x00C0) /* AES Module */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ -+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -+#define PORTG (*(PORT_t *) 0x06C0) /* I/O Ports */ -+#define PORTM (*(PORT_t *) 0x0760) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -+#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -+#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define LCD (*(LCD_t *) 0x0D00) /* LCD Controller */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -+#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -+#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -+#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -+#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+#define CLK_USBCTRL _SFR_MEM8(0x0044) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* DFLL - DFLL */ -+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -+#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -+#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPB _SFR_MEM8(0x0072) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPE _SFR_MEM8(0x0075) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_JTAGUID _SFR_MEM8(0x0094) -+#define MCU_MCUCR _SFR_MEM8(0x0096) -+#define MCU_ANAINIT _SFR_MEM8(0x0097) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_AWEXLOCK _SFR_MEM8(0x0099) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) -+ -+/* AES - AES Module */ -+#define AES_CTRL _SFR_MEM8(0x00C0) -+#define AES_STATUS _SFR_MEM8(0x00C1) -+#define AES_STATE _SFR_MEM8(0x00C2) -+#define AES_KEY _SFR_MEM8(0x00C3) -+#define AES_INTCTRL _SFR_MEM8(0x00C4) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* DMA - DMA Controller */ -+#define DMA_CTRL _SFR_MEM8(0x0100) -+#define DMA_INTFLAGS _SFR_MEM8(0x0103) -+#define DMA_STATUS _SFR_MEM8(0x0104) -+#define DMA_TEMP _SFR_MEM16(0x0106) -+#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -+#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -+#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -+#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -+#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -+#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -+#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -+#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -+#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -+#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -+#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -+#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -+#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -+#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -+#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -+#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -+#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -+#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -+#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -+#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCA_CTRLA _SFR_MEM8(0x0200) -+#define ADCA_CTRLB _SFR_MEM8(0x0201) -+#define ADCA_REFCTRL _SFR_MEM8(0x0202) -+#define ADCA_EVCTRL _SFR_MEM8(0x0203) -+#define ADCA_PRESCALER _SFR_MEM8(0x0204) -+#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -+#define ADCA_TEMP _SFR_MEM8(0x0207) -+#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) -+#define ADCA_CAL _SFR_MEM16(0x020C) -+#define ADCA_CH0RES _SFR_MEM16(0x0210) -+#define ADCA_CMP _SFR_MEM16(0x0218) -+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -+#define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCB_CTRLA _SFR_MEM8(0x0240) -+#define ADCB_CTRLB _SFR_MEM8(0x0241) -+#define ADCB_REFCTRL _SFR_MEM8(0x0242) -+#define ADCB_EVCTRL _SFR_MEM8(0x0243) -+#define ADCB_PRESCALER _SFR_MEM8(0x0244) -+#define ADCB_INTFLAGS _SFR_MEM8(0x0246) -+#define ADCB_TEMP _SFR_MEM8(0x0247) -+#define ADCB_SAMPCTRL _SFR_MEM8(0x0248) -+#define ADCB_CAL _SFR_MEM16(0x024C) -+#define ADCB_CH0RES _SFR_MEM16(0x0250) -+#define ADCB_CMP _SFR_MEM16(0x0258) -+#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) -+#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) -+#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) -+#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) -+#define ADCB_CH0_RES _SFR_MEM16(0x0264) -+#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) -+ -+/* AC - Analog Comparator */ -+#define ACA_AC0CTRL _SFR_MEM8(0x0380) -+#define ACA_AC1CTRL _SFR_MEM8(0x0381) -+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -+#define ACA_CTRLA _SFR_MEM8(0x0384) -+#define ACA_CTRLB _SFR_MEM8(0x0385) -+#define ACA_WINCTRL _SFR_MEM8(0x0386) -+#define ACA_STATUS _SFR_MEM8(0x0387) -+#define ACA_CURRCTRL _SFR_MEM8(0x0388) -+#define ACA_CURRCALIB _SFR_MEM8(0x0389) -+ -+/* AC - Analog Comparator */ -+#define ACB_AC0CTRL _SFR_MEM8(0x0390) -+#define ACB_AC1CTRL _SFR_MEM8(0x0391) -+#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -+#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -+#define ACB_CTRLA _SFR_MEM8(0x0394) -+#define ACB_CTRLB _SFR_MEM8(0x0395) -+#define ACB_WINCTRL _SFR_MEM8(0x0396) -+#define ACB_STATUS _SFR_MEM8(0x0397) -+#define ACB_CURRCTRL _SFR_MEM8(0x0398) -+#define ACB_CURRCALIB _SFR_MEM8(0x0399) -+ -+/* RTC - Real-Time Counter */ -+#define RTC_CTRL _SFR_MEM8(0x0400) -+#define RTC_STATUS _SFR_MEM8(0x0401) -+#define RTC_INTCTRL _SFR_MEM8(0x0402) -+#define RTC_INTFLAGS _SFR_MEM8(0x0403) -+#define RTC_TEMP _SFR_MEM8(0x0404) -+#define RTC_CNT _SFR_MEM16(0x0408) -+#define RTC_PER _SFR_MEM16(0x040A) -+#define RTC_COMP _SFR_MEM16(0x040C) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+ -+/* USB - Universal Serial Bus */ -+#define USB_CTRLA _SFR_MEM8(0x04C0) -+#define USB_CTRLB _SFR_MEM8(0x04C1) -+#define USB_STATUS _SFR_MEM8(0x04C2) -+#define USB_ADDR _SFR_MEM8(0x04C3) -+#define USB_FIFOWP _SFR_MEM8(0x04C4) -+#define USB_FIFORP _SFR_MEM8(0x04C5) -+#define USB_EPPTR _SFR_MEM16(0x04C6) -+#define USB_INTCTRLA _SFR_MEM8(0x04C8) -+#define USB_INTCTRLB _SFR_MEM8(0x04C9) -+#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -+#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -+#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -+#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -+#define USB_CAL0 _SFR_MEM8(0x04FA) -+#define USB_CAL1 _SFR_MEM8(0x04FB) -+ -+/* PORT - I/O Ports */ -+#define PORTA_DIR _SFR_MEM8(0x0600) -+#define PORTA_DIRSET _SFR_MEM8(0x0601) -+#define PORTA_DIRCLR _SFR_MEM8(0x0602) -+#define PORTA_DIRTGL _SFR_MEM8(0x0603) -+#define PORTA_OUT _SFR_MEM8(0x0604) -+#define PORTA_OUTSET _SFR_MEM8(0x0605) -+#define PORTA_OUTCLR _SFR_MEM8(0x0606) -+#define PORTA_OUTTGL _SFR_MEM8(0x0607) -+#define PORTA_IN _SFR_MEM8(0x0608) -+#define PORTA_INTCTRL _SFR_MEM8(0x0609) -+#define PORTA_INT0MASK _SFR_MEM8(0x060A) -+#define PORTA_INT1MASK _SFR_MEM8(0x060B) -+#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_REMAP _SFR_MEM8(0x060E) -+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -+ -+/* PORT - I/O Ports */ -+#define PORTB_DIR _SFR_MEM8(0x0620) -+#define PORTB_DIRSET _SFR_MEM8(0x0621) -+#define PORTB_DIRCLR _SFR_MEM8(0x0622) -+#define PORTB_DIRTGL _SFR_MEM8(0x0623) -+#define PORTB_OUT _SFR_MEM8(0x0624) -+#define PORTB_OUTSET _SFR_MEM8(0x0625) -+#define PORTB_OUTCLR _SFR_MEM8(0x0626) -+#define PORTB_OUTTGL _SFR_MEM8(0x0627) -+#define PORTB_IN _SFR_MEM8(0x0628) -+#define PORTB_INTCTRL _SFR_MEM8(0x0629) -+#define PORTB_INT0MASK _SFR_MEM8(0x062A) -+#define PORTB_INT1MASK _SFR_MEM8(0x062B) -+#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -+#define PORTB_REMAP _SFR_MEM8(0x062E) -+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INT0MASK _SFR_MEM8(0x064A) -+#define PORTC_INT1MASK _SFR_MEM8(0x064B) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INT0MASK _SFR_MEM8(0x066A) -+#define PORTD_INT1MASK _SFR_MEM8(0x066B) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTE_DIR _SFR_MEM8(0x0680) -+#define PORTE_DIRSET _SFR_MEM8(0x0681) -+#define PORTE_DIRCLR _SFR_MEM8(0x0682) -+#define PORTE_DIRTGL _SFR_MEM8(0x0683) -+#define PORTE_OUT _SFR_MEM8(0x0684) -+#define PORTE_OUTSET _SFR_MEM8(0x0685) -+#define PORTE_OUTCLR _SFR_MEM8(0x0686) -+#define PORTE_OUTTGL _SFR_MEM8(0x0687) -+#define PORTE_IN _SFR_MEM8(0x0688) -+#define PORTE_INTCTRL _SFR_MEM8(0x0689) -+#define PORTE_INT0MASK _SFR_MEM8(0x068A) -+#define PORTE_INT1MASK _SFR_MEM8(0x068B) -+#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -+#define PORTE_REMAP _SFR_MEM8(0x068E) -+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) -+ -+/* PORT - I/O Ports */ -+#define PORTG_DIR _SFR_MEM8(0x06C0) -+#define PORTG_DIRSET _SFR_MEM8(0x06C1) -+#define PORTG_DIRCLR _SFR_MEM8(0x06C2) -+#define PORTG_DIRTGL _SFR_MEM8(0x06C3) -+#define PORTG_OUT _SFR_MEM8(0x06C4) -+#define PORTG_OUTSET _SFR_MEM8(0x06C5) -+#define PORTG_OUTCLR _SFR_MEM8(0x06C6) -+#define PORTG_OUTTGL _SFR_MEM8(0x06C7) -+#define PORTG_IN _SFR_MEM8(0x06C8) -+#define PORTG_INTCTRL _SFR_MEM8(0x06C9) -+#define PORTG_INT0MASK _SFR_MEM8(0x06CA) -+#define PORTG_INT1MASK _SFR_MEM8(0x06CB) -+#define PORTG_INTFLAGS _SFR_MEM8(0x06CC) -+#define PORTG_REMAP _SFR_MEM8(0x06CE) -+#define PORTG_PIN0CTRL _SFR_MEM8(0x06D0) -+#define PORTG_PIN1CTRL _SFR_MEM8(0x06D1) -+#define PORTG_PIN2CTRL _SFR_MEM8(0x06D2) -+#define PORTG_PIN3CTRL _SFR_MEM8(0x06D3) -+#define PORTG_PIN4CTRL _SFR_MEM8(0x06D4) -+#define PORTG_PIN5CTRL _SFR_MEM8(0x06D5) -+#define PORTG_PIN6CTRL _SFR_MEM8(0x06D6) -+#define PORTG_PIN7CTRL _SFR_MEM8(0x06D7) -+ -+/* PORT - I/O Ports */ -+#define PORTM_DIR _SFR_MEM8(0x0760) -+#define PORTM_DIRSET _SFR_MEM8(0x0761) -+#define PORTM_DIRCLR _SFR_MEM8(0x0762) -+#define PORTM_DIRTGL _SFR_MEM8(0x0763) -+#define PORTM_OUT _SFR_MEM8(0x0764) -+#define PORTM_OUTSET _SFR_MEM8(0x0765) -+#define PORTM_OUTCLR _SFR_MEM8(0x0766) -+#define PORTM_OUTTGL _SFR_MEM8(0x0767) -+#define PORTM_IN _SFR_MEM8(0x0768) -+#define PORTM_INTCTRL _SFR_MEM8(0x0769) -+#define PORTM_INT0MASK _SFR_MEM8(0x076A) -+#define PORTM_INT1MASK _SFR_MEM8(0x076B) -+#define PORTM_INTFLAGS _SFR_MEM8(0x076C) -+#define PORTM_REMAP _SFR_MEM8(0x076E) -+#define PORTM_PIN0CTRL _SFR_MEM8(0x0770) -+#define PORTM_PIN1CTRL _SFR_MEM8(0x0771) -+#define PORTM_PIN2CTRL _SFR_MEM8(0x0772) -+#define PORTM_PIN3CTRL _SFR_MEM8(0x0773) -+#define PORTM_PIN4CTRL _SFR_MEM8(0x0774) -+#define PORTM_PIN5CTRL _SFR_MEM8(0x0775) -+#define PORTM_PIN6CTRL _SFR_MEM8(0x0776) -+#define PORTM_PIN7CTRL _SFR_MEM8(0x0777) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -+#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCC0_CTRLA _SFR_MEM8(0x0800) -+#define TCC0_CTRLB _SFR_MEM8(0x0801) -+#define TCC0_CTRLC _SFR_MEM8(0x0802) -+#define TCC0_CTRLD _SFR_MEM8(0x0803) -+#define TCC0_CTRLE _SFR_MEM8(0x0804) -+#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -+#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -+#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -+#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC0_TEMP _SFR_MEM8(0x080F) -+#define TCC0_CNT _SFR_MEM16(0x0820) -+#define TCC0_PER _SFR_MEM16(0x0826) -+#define TCC0_CCA _SFR_MEM16(0x0828) -+#define TCC0_CCB _SFR_MEM16(0x082A) -+#define TCC0_CCC _SFR_MEM16(0x082C) -+#define TCC0_CCD _SFR_MEM16(0x082E) -+#define TCC0_PERBUF _SFR_MEM16(0x0836) -+#define TCC0_CCABUF _SFR_MEM16(0x0838) -+#define TCC0_CCBBUF _SFR_MEM16(0x083A) -+#define TCC0_CCCBUF _SFR_MEM16(0x083C) -+#define TCC0_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCC1_CTRLA _SFR_MEM8(0x0840) -+#define TCC1_CTRLB _SFR_MEM8(0x0841) -+#define TCC1_CTRLC _SFR_MEM8(0x0842) -+#define TCC1_CTRLD _SFR_MEM8(0x0843) -+#define TCC1_CTRLE _SFR_MEM8(0x0844) -+#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -+#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -+#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -+#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC1_TEMP _SFR_MEM8(0x084F) -+#define TCC1_CNT _SFR_MEM16(0x0860) -+#define TCC1_PER _SFR_MEM16(0x0866) -+#define TCC1_CCA _SFR_MEM16(0x0868) -+#define TCC1_CCB _SFR_MEM16(0x086A) -+#define TCC1_PERBUF _SFR_MEM16(0x0876) -+#define TCC1_CCABUF _SFR_MEM16(0x0878) -+#define TCC1_CCBBUF _SFR_MEM16(0x087A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXC_CTRL _SFR_MEM8(0x0880) -+#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -+#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -+#define AWEXC_STATUS _SFR_MEM8(0x0884) -+#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -+#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -+#define AWEXC_DTLS _SFR_MEM8(0x0888) -+#define AWEXC_DTHS _SFR_MEM8(0x0889) -+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x0890) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08A0) -+#define USARTC0_STATUS _SFR_MEM8(0x08A1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -+#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -+#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIC_CTRL _SFR_MEM8(0x08C0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -+#define SPIC_STATUS _SFR_MEM8(0x08C2) -+#define SPIC_DATA _SFR_MEM8(0x08C3) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCE0_CTRLA _SFR_MEM8(0x0A00) -+#define TCE0_CTRLB _SFR_MEM8(0x0A01) -+#define TCE0_CTRLC _SFR_MEM8(0x0A02) -+#define TCE0_CTRLD _SFR_MEM8(0x0A03) -+#define TCE0_CTRLE _SFR_MEM8(0x0A04) -+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE0_TEMP _SFR_MEM8(0x0A0F) -+#define TCE0_CNT _SFR_MEM16(0x0A20) -+#define TCE0_PER _SFR_MEM16(0x0A26) -+#define TCE0_CCA _SFR_MEM16(0x0A28) -+#define TCE0_CCB _SFR_MEM16(0x0A2A) -+#define TCE0_CCC _SFR_MEM16(0x0A2C) -+#define TCE0_CCD _SFR_MEM16(0x0A2E) -+#define TCE0_PERBUF _SFR_MEM16(0x0A36) -+#define TCE0_CCABUF _SFR_MEM16(0x0A38) -+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE0_DATA _SFR_MEM8(0x0AA0) -+#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -+#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -+#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -+#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -+#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -+#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) -+ -+/* LCD - LCD Controller */ -+#define LCD_CTRLA _SFR_MEM8(0x0D00) -+#define LCD_CTRLB _SFR_MEM8(0x0D01) -+#define LCD_CTRLC _SFR_MEM8(0x0D02) -+#define LCD_INTCTRL _SFR_MEM8(0x0D03) -+#define LCD_INTFLAG _SFR_MEM8(0x0D04) -+#define LCD_CTRLD _SFR_MEM8(0x0D05) -+#define LCD_CTRLE _SFR_MEM8(0x0D06) -+#define LCD_CTRLF _SFR_MEM8(0x0D07) -+#define LCD_CTRLG _SFR_MEM8(0x0D08) -+#define LCD_CTRLH _SFR_MEM8(0x0D09) -+#define LCD_DATA0 _SFR_MEM8(0x0D10) -+#define LCD_DATA1 _SFR_MEM8(0x0D11) -+#define LCD_DATA2 _SFR_MEM8(0x0D12) -+#define LCD_DATA3 _SFR_MEM8(0x0D13) -+#define LCD_DATA4 _SFR_MEM8(0x0D14) -+#define LCD_DATA5 _SFR_MEM8(0x0D15) -+#define LCD_DATA6 _SFR_MEM8(0x0D16) -+#define LCD_DATA7 _SFR_MEM8(0x0D17) -+#define LCD_DATA8 _SFR_MEM8(0x0D18) -+#define LCD_DATA9 _SFR_MEM8(0x0D19) -+#define LCD_DATA10 _SFR_MEM8(0x0D1A) -+#define LCD_DATA11 _SFR_MEM8(0x0D1B) -+#define LCD_DATA12 _SFR_MEM8(0x0D1C) -+#define LCD_DATA13 _SFR_MEM8(0x0D1D) -+#define LCD_DATA14 _SFR_MEM8(0x0D1E) -+#define LCD_DATA15 _SFR_MEM8(0x0D1F) -+#define LCD_DATA16 _SFR_MEM8(0x0D20) -+#define LCD_DATA17 _SFR_MEM8(0x0D21) -+#define LCD_DATA18 _SFR_MEM8(0x0D22) -+#define LCD_DATA19 _SFR_MEM8(0x0D23) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* VPORT - Virtual Ports */ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* CLK.USBCTRL bit masks and bit positions */ -+#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -+#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -+#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -+#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -+#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -+#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -+#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -+#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ -+ -+#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -+#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -+#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ -+ -+#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ -+#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -+#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -+#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ -+ -+#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ -+ -+#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -+#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ -+ -+/* PR - Power Reduction */ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_LCD_bm 0x80 /* LCD Module bit mask. */ -+#define PR_LCD_bp 7 /* LCD Module bit position. */ -+ -+#define PR_USB_bm 0x40 /* USB bit mask. */ -+#define PR_USB_bp 6 /* USB bit position. */ -+ -+#define PR_AES_bm 0x10 /* AES bit mask. */ -+#define PR_AES_bp 4 /* AES bit position. */ -+ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -+#define PR_DMA_bp 0 /* DMA-Controller bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPB bit masks and bit positions */ -+/* PR_ADC Predefined. */ -+/* PR_ADC Predefined. */ -+ -+/* PR_AC Predefined. */ -+/* PR_AC Predefined. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -+#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ -+ -+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -+ -+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ -+ -+/* PR.PRPE bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.MCUCR bit masks and bit positions */ -+#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -+#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ -+ -+/* MCU.ANAINIT bit masks and bit positions */ -+#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -+#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -+#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -+#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -+#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -+#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ -+ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -+#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ -+ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.AWEXLOCK bit masks and bit positions */ -+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* PORTCFG - Port Configuration */ -+/* PORTCFG.VPCTRLA bit masks and bit positions */ -+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ -+ -+/* PORTCFG.VPCTRLB bit masks and bit positions */ -+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ -+ -+/* PORTCFG.CLKEVOUT bit masks and bit positions */ -+#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ -+ -+#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -+#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -+#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -+#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -+#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -+#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ -+ -+#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -+#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ -+ -+#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -+#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ -+ -+/* PORTCFG.EVOUTSEL bit masks and bit positions */ -+#define PORTCFG_EVOUTSEL_bm 0x04 /* Event Output Select bit mask. */ -+#define PORTCFG_EVOUTSEL_bp 2 /* Event Output Select bit position. */ -+ -+/* AES - AES Module */ -+/* AES.CTRL bit masks and bit positions */ -+#define AES_START_bm 0x80 /* Start/Run bit mask. */ -+#define AES_START_bp 7 /* Start/Run bit position. */ -+ -+#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -+#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ -+ -+#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -+#define AES_RESET_bp 5 /* AES Software Reset bit position. */ -+ -+#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -+#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ -+ -+#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -+#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ -+ -+/* AES.STATUS bit masks and bit positions */ -+#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -+#define AES_ERROR_bp 7 /* AES Error bit position. */ -+ -+#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -+#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ -+ -+/* AES.INTCTRL bit masks and bit positions */ -+#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -+#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* DMA - DMA Controller */ -+/* DMA_CH.CTRLA bit masks and bit positions */ -+#define DMA_CH_CHEN_bm 0x80 /* Channel Enable bit mask. */ -+#define DMA_CH_CHEN_bp 7 /* Channel Enable bit position. */ -+ -+#define DMA_CH_CHRST_bm 0x40 /* Channel Software Reset bit mask. */ -+#define DMA_CH_CHRST_bp 6 /* Channel Software Reset bit position. */ -+ -+#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -+#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ -+ -+#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -+#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ -+ -+#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -+#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ -+ -+#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -+#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -+#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -+#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -+#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -+#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ -+ -+/* DMA_CH.CTRLB bit masks and bit positions */ -+#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -+#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ -+ -+#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -+#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ -+ -+#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -+#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ -+ -+#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -+#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -+#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -+#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -+#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -+#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ -+ -+#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -+#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -+#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -+#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -+#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -+#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ -+ -+/* DMA_CH.ADDRCTRL bit masks and bit positions */ -+#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -+#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -+#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -+#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -+#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -+#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ -+ -+#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -+#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -+#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -+#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -+#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -+#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ -+ -+#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -+#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -+#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -+#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -+#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -+#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ -+ -+#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -+#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -+#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -+#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -+#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -+#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ -+ -+/* DMA_CH.TRIGSRC bit masks and bit positions */ -+#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -+#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -+#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -+#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -+#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -+#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -+#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -+#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -+#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -+#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -+#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -+#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -+#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -+#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -+#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -+#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -+#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -+#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ -+ -+/* DMA.CTRL bit masks and bit positions */ -+#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -+#define DMA_ENABLE_bp 7 /* Enable bit position. */ -+ -+#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -+#define DMA_RESET_bp 6 /* Software Reset bit position. */ -+ -+#define DMA_DBUFMODE_bm 0x04 /* Double Buffering Mode bit mask. */ -+#define DMA_DBUFMODE_bp 2 /* Double Buffering Mode bit position. */ -+ -+#define DMA_PRIMODE_bm 0x01 /* Channel Priority Mode bit mask. */ -+#define DMA_PRIMODE_bp 0 /* Channel Priority Mode bit position. */ -+ -+/* DMA.INTFLAGS bit masks and bit positions */ -+#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ -+ -+/* DMA.STATUS bit masks and bit positions */ -+#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -+#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ -+ -+#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -+#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ -+ -+#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -+#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ -+ -+#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -+#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0x7F /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ -+ -+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ -+ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -+#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -+#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -+#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -+#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -+#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -+#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -+#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -+#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -+#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ -+ -+#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */ -+#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */ -+#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -+#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */ -+#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -+#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */ -+#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -+#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */ -+#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -+#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -+#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* ADC.SAMPCTRL bit masks and bit positions */ -+#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ -+#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ -+#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ -+#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ -+#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ -+#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ -+#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ -+#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ -+#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ -+#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ -+#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ -+#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ -+#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ -+#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* AC.CURRCTRL bit masks and bit positions */ -+#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ -+#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ -+ -+#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ -+#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ -+ -+#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ -+#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ -+ -+#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ -+#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ -+ -+/* AC.CURRCALIB bit masks and bit positions */ -+#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ -+#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ -+#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ -+#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ -+#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ -+#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ -+#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ -+#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ -+#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ -+#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ -+ -+/* RTC - Real-Time Counter */ -+/* RTC.CTRL bit masks and bit positions */ -+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ -+ -+/* RTC.STATUS bit masks and bit positions */ -+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC.INTCTRL bit masks and bit positions */ -+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC.INTFLAGS bit masks and bit positions */ -+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* USB - USB */ -+/* USB_EP.STATUS bit masks and bit positions */ -+#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -+#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ -+ -+#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -+#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ -+ -+#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -+#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ -+ -+#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -+#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ -+ -+#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -+#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ -+ -+#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -+#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ -+ -+#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -+#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ -+ -+#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -+#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ -+ -+#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ -+ -+#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ -+ -+#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -+#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ -+ -+/* USB_EP.CTRL bit masks and bit positions */ -+#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -+#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -+#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -+#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -+#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -+#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ -+ -+#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -+#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ -+ -+#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -+#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ -+ -+#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -+#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ -+ -+#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -+#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ -+ -+#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -+#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -+#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -+#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -+#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -+#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -+#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -+#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ -+ -+/* USB_EP.CNT bit masks and bit positions */ -+#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -+#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ -+ -+/* USB.CTRLA bit masks and bit positions */ -+#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -+#define USB_ENABLE_bp 7 /* USB Enable bit position. */ -+ -+#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -+#define USB_SPEED_bp 6 /* Speed Select bit position. */ -+ -+#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -+#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ -+ -+#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -+#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ -+ -+#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -+#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -+#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -+#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -+#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -+#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -+#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -+#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -+#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -+#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ -+ -+/* USB.CTRLB bit masks and bit positions */ -+#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -+#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ -+ -+#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -+#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ -+ -+#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -+#define USB_GNACK_bp 1 /* Global NACK bit position. */ -+ -+#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -+#define USB_ATTACH_bp 0 /* Attach bit position. */ -+ -+/* USB.STATUS bit masks and bit positions */ -+#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -+#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ -+ -+#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -+#define USB_RESUME_bp 2 /* Resume bit position. */ -+ -+#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -+#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ -+ -+#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -+#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ -+ -+/* USB.ADDR bit masks and bit positions */ -+#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -+#define USB_ADDR_gp 0 /* Device Address group position. */ -+#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -+#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -+#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -+#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -+#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -+#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -+#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -+#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -+#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -+#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -+#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -+#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -+#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -+#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ -+ -+/* USB.FIFOWP bit masks and bit positions */ -+#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -+#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -+#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -+#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -+#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -+#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -+#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -+#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -+#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -+#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -+#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -+#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ -+ -+/* USB.FIFORP bit masks and bit positions */ -+#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -+#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -+#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -+#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -+#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -+#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -+#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -+#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -+#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -+#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -+#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -+#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ -+ -+/* USB.INTCTRLA bit masks and bit positions */ -+#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -+#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ -+ -+#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -+#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ -+ -+#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -+#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ -+ -+#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -+#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ -+ -+#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* USB.INTCTRLB bit masks and bit positions */ -+#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -+#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ -+ -+#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -+#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ -+ -+/* USB.INTFLAGSACLR bit masks and bit positions */ -+#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -+#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ -+ -+#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -+#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ -+ -+#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -+#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ -+ -+#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -+#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ -+ -+#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -+#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ -+ -+#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -+#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ -+ -+#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -+#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ -+ -+#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -+#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSASET bit masks and bit positions */ -+/* USB_SOFIF Predefined. */ -+/* USB_SOFIF Predefined. */ -+ -+/* USB_SUSPENDIF Predefined. */ -+/* USB_SUSPENDIF Predefined. */ -+ -+/* USB_RESUMEIF Predefined. */ -+/* USB_RESUMEIF Predefined. */ -+ -+/* USB_RSTIF Predefined. */ -+/* USB_RSTIF Predefined. */ -+ -+/* USB_CRCIF Predefined. */ -+/* USB_CRCIF Predefined. */ -+ -+/* USB_UNFIF Predefined. */ -+/* USB_UNFIF Predefined. */ -+ -+/* USB_OVFIF Predefined. */ -+/* USB_OVFIF Predefined. */ -+ -+/* USB_STALLIF Predefined. */ -+/* USB_STALLIF Predefined. */ -+ -+/* USB.INTFLAGSBCLR bit masks and bit positions */ -+#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -+#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ -+ -+#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -+#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSBSET bit masks and bit positions */ -+/* USB_TRNIF Predefined. */ -+/* USB_TRNIF Predefined. */ -+ -+/* USB_SETUPIF Predefined. */ -+/* USB_SETUPIF Predefined. */ -+ -+/* PORT - I/O Port Configuration */ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ -+ -+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -+#define PORT_SPI_bp 5 /* SPI bit position. */ -+ -+#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -+#define PORT_USART0_bp 4 /* USART0 bit position. */ -+ -+#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -+#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ -+ -+#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -+#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ -+ -+#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -+#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ -+ -+#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -+#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ -+ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC0.CTRLA bit masks and bit positions */ -+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC0.CTRLB bit masks and bit positions */ -+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ -+ -+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ -+ -+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC0.CTRLC bit masks and bit positions */ -+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ -+ -+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ -+ -+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC0.CTRLD bit masks and bit positions */ -+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC0_EVACT_gp 5 /* Event Action group position. */ -+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC0.CTRLE bit masks and bit positions */ -+#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC0.INTCTRLA bit masks and bit positions */ -+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC0.INTCTRLB bit masks and bit positions */ -+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ -+ -+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ -+ -+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC0.CTRLFCLR bit masks and bit positions */ -+#define TC0_CMD_gm 0x0C /* Command group mask. */ -+#define TC0_CMD_gp 2 /* Command group position. */ -+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC0_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC0_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC0_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC0.CTRLFSET bit masks and bit positions */ -+/* TC0_CMD Predefined. */ -+/* TC0_CMD Predefined. */ -+ -+/* TC0_LUPD Predefined. */ -+/* TC0_LUPD Predefined. */ -+ -+/* TC0_DIR Predefined. */ -+/* TC0_DIR Predefined. */ -+ -+/* TC0.CTRLGCLR bit masks and bit positions */ -+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ -+ -+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ -+ -+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC0.CTRLGSET bit masks and bit positions */ -+/* TC0_CCDBV Predefined. */ -+/* TC0_CCDBV Predefined. */ -+ -+/* TC0_CCCBV Predefined. */ -+/* TC0_CCCBV Predefined. */ -+ -+/* TC0_CCBBV Predefined. */ -+/* TC0_CCBBV Predefined. */ -+ -+/* TC0_CCABV Predefined. */ -+/* TC0_CCABV Predefined. */ -+ -+/* TC0_PERBV Predefined. */ -+/* TC0_PERBV Predefined. */ -+ -+/* TC0.INTFLAGS bit masks and bit positions */ -+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ -+ -+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ -+ -+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC1.CTRLA bit masks and bit positions */ -+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC1.CTRLB bit masks and bit positions */ -+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC1.CTRLC bit masks and bit positions */ -+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC1.CTRLD bit masks and bit positions */ -+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC1_EVACT_gp 5 /* Event Action group position. */ -+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC1.CTRLE bit masks and bit positions */ -+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ -+ -+/* TC1.INTCTRLA bit masks and bit positions */ -+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC1.INTCTRLB bit masks and bit positions */ -+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC1.CTRLFCLR bit masks and bit positions */ -+#define TC1_CMD_gm 0x0C /* Command group mask. */ -+#define TC1_CMD_gp 2 /* Command group position. */ -+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC1_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC1_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC1_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC1.CTRLFSET bit masks and bit positions */ -+/* TC1_CMD Predefined. */ -+/* TC1_CMD Predefined. */ -+ -+/* TC1_LUPD Predefined. */ -+/* TC1_LUPD Predefined. */ -+ -+/* TC1_DIR Predefined. */ -+/* TC1_DIR Predefined. */ -+ -+/* TC1.CTRLGCLR bit masks and bit positions */ -+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC1.CTRLGSET bit masks and bit positions */ -+/* TC1_CCBBV Predefined. */ -+/* TC1_CCBBV Predefined. */ -+ -+/* TC1_CCABV Predefined. */ -+/* TC1_CCABV Predefined. */ -+ -+/* TC1_PERBV Predefined. */ -+/* TC1_PERBV Predefined. */ -+ -+/* TC1.INTFLAGS bit masks and bit positions */ -+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* AWEX - Timer/Counter Advanced Waveform Extension */ -+/* AWEX.CTRL bit masks and bit positions */ -+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ -+ -+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ -+ -+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ -+ -+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ -+ -+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ -+ -+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ -+ -+/* AWEX.FDCTRL bit masks and bit positions */ -+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ -+ -+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ -+ -+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ -+ -+/* AWEX.STATUS bit masks and bit positions */ -+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ -+ -+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ -+ -+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ -+ -+/* AWEX.STATUSSET bit masks and bit positions */ -+/* AWEX_FDF Predefined. */ -+/* AWEX_FDF Predefined. */ -+ -+/* AWEX_DTHSBUFV Predefined. */ -+/* AWEX_DTHSBUFV Predefined. */ -+ -+/* AWEX_DTLSBUFV Predefined. */ -+/* AWEX_DTLSBUFV Predefined. */ -+ -+/* HIRES - Timer/Counter High-Resolution Extension */ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+/* LCD - LCD Controller */ -+/* LCD.CTRLA bit masks and bit positions */ -+#define LCD_ENABLE_bm 0x80 /* LCD Enable bit mask. */ -+#define LCD_ENABLE_bp 7 /* LCD Enable bit position. */ -+ -+#define LCD_XBIAS_bm 0x40 /* External Register Bias Generation bit mask. */ -+#define LCD_XBIAS_bp 6 /* External Register Bias Generation bit position. */ -+ -+#define LCD_DATCLK_bm 0x20 /* Data Register Lock bit mask. */ -+#define LCD_DATCLK_bp 5 /* Data Register Lock bit position. */ -+ -+#define LCD_COMSWP_bm 0x10 /* Common Bus Swap bit mask. */ -+#define LCD_COMSWP_bp 4 /* Common Bus Swap bit position. */ -+ -+#define LCD_SEGSWP_bm 0x08 /* Segment Bus Swap bit mask. */ -+#define LCD_SEGSWP_bp 3 /* Segment Bus Swap bit position. */ -+ -+#define LCD_CLRDT_bm 0x04 /* Clear Data Register bit mask. */ -+#define LCD_CLRDT_bp 2 /* Clear Data Register bit position. */ -+ -+#define LCD_SEGON_bm 0x02 /* Segments On bit mask. */ -+#define LCD_SEGON_bp 1 /* Segments On bit position. */ -+ -+#define LCD_BLANK_bm 0x01 /* Blanking Display Mode bit mask. */ -+#define LCD_BLANK_bp 0 /* Blanking Display Mode bit position. */ -+ -+/* LCD.CTRLB bit masks and bit positions */ -+#define LCD_PRESC_bm 0x80 /* LCD Prescaler Select bit mask. */ -+#define LCD_PRESC_bp 7 /* LCD Prescaler Select bit position. */ -+ -+#define LCD_CLKDIV_gm 0x70 /* LCD Clock Divide group mask. */ -+#define LCD_CLKDIV_gp 4 /* LCD Clock Divide group position. */ -+#define LCD_CLKDIV0_bm (1<<4) /* LCD Clock Divide bit 0 mask. */ -+#define LCD_CLKDIV0_bp 4 /* LCD Clock Divide bit 0 position. */ -+#define LCD_CLKDIV1_bm (1<<5) /* LCD Clock Divide bit 1 mask. */ -+#define LCD_CLKDIV1_bp 5 /* LCD Clock Divide bit 1 position. */ -+#define LCD_CLKDIV2_bm (1<<6) /* LCD Clock Divide bit 2 mask. */ -+#define LCD_CLKDIV2_bp 6 /* LCD Clock Divide bit 2 position. */ -+ -+#define LCD_LPWAV_bm 0x08 /* Low Power Waveform bit mask. */ -+#define LCD_LPWAV_bp 3 /* Low Power Waveform bit position. */ -+ -+#define LCD_DUTY_gm 0x03 /* Duty Select group mask. */ -+#define LCD_DUTY_gp 0 /* Duty Select group position. */ -+#define LCD_DUTY0_bm (1<<0) /* Duty Select bit 0 mask. */ -+#define LCD_DUTY0_bp 0 /* Duty Select bit 0 position. */ -+#define LCD_DUTY1_bm (1<<1) /* Duty Select bit 1 mask. */ -+#define LCD_DUTY1_bp 1 /* Duty Select bit 1 position. */ -+ -+/* LCD.CTRLC bit masks and bit positions */ -+#define LCD_PMSK_gm 0x3F /* LCD Port Mask group mask. */ -+#define LCD_PMSK_gp 0 /* LCD Port Mask group position. */ -+#define LCD_PMSK0_bm (1<<0) /* LCD Port Mask bit 0 mask. */ -+#define LCD_PMSK0_bp 0 /* LCD Port Mask bit 0 position. */ -+#define LCD_PMSK1_bm (1<<1) /* LCD Port Mask bit 1 mask. */ -+#define LCD_PMSK1_bp 1 /* LCD Port Mask bit 1 position. */ -+#define LCD_PMSK2_bm (1<<2) /* LCD Port Mask bit 2 mask. */ -+#define LCD_PMSK2_bp 2 /* LCD Port Mask bit 2 position. */ -+#define LCD_PMSK3_bm (1<<3) /* LCD Port Mask bit 3 mask. */ -+#define LCD_PMSK3_bp 3 /* LCD Port Mask bit 3 position. */ -+#define LCD_PMSK4_bm (1<<4) /* LCD Port Mask bit 4 mask. */ -+#define LCD_PMSK4_bp 4 /* LCD Port Mask bit 4 position. */ -+#define LCD_PMSK5_bm (1<<5) /* LCD Port Mask bit 5 mask. */ -+#define LCD_PMSK5_bp 5 /* LCD Port Mask bit 5 position. */ -+ -+/* LCD.INTCTRL bit masks and bit positions */ -+#define LCD_XIME_gm 0xF8 /* eXtended Interrupt Mode Enable group mask. */ -+#define LCD_XIME_gp 3 /* eXtended Interrupt Mode Enable group position. */ -+#define LCD_XIME0_bm (1<<3) /* eXtended Interrupt Mode Enable bit 0 mask. */ -+#define LCD_XIME0_bp 3 /* eXtended Interrupt Mode Enable bit 0 position. */ -+#define LCD_XIME1_bm (1<<4) /* eXtended Interrupt Mode Enable bit 1 mask. */ -+#define LCD_XIME1_bp 4 /* eXtended Interrupt Mode Enable bit 1 position. */ -+#define LCD_XIME2_bm (1<<5) /* eXtended Interrupt Mode Enable bit 2 mask. */ -+#define LCD_XIME2_bp 5 /* eXtended Interrupt Mode Enable bit 2 position. */ -+#define LCD_XIME3_bm (1<<6) /* eXtended Interrupt Mode Enable bit 3 mask. */ -+#define LCD_XIME3_bp 6 /* eXtended Interrupt Mode Enable bit 3 position. */ -+#define LCD_XIME4_bm (1<<7) /* eXtended Interrupt Mode Enable bit 4 mask. */ -+#define LCD_XIME4_bp 7 /* eXtended Interrupt Mode Enable bit 4 position. */ -+ -+#define LCD_FCINTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define LCD_FCINTLVL_gp 0 /* Interrupt Level group position. */ -+#define LCD_FCINTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define LCD_FCINTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define LCD_FCINTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define LCD_FCINTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* LCD.INTFLAG bit masks and bit positions */ -+#define LCD_FCIF_bm 0x01 /* LCD Frame Completed Interrupt Flag bit mask. */ -+#define LCD_FCIF_bp 0 /* LCD Frame Completed Interrupt Flag bit position. */ -+ -+/* LCD.CTRLD bit masks and bit positions */ -+#define LCD_BLINKEN_bm 0x08 /* Blink Enable bit mask. */ -+#define LCD_BLINKEN_bp 3 /* Blink Enable bit position. */ -+ -+#define LCD_BLINKRATE_gm 0x03 /* LCD Blink Rate group mask. */ -+#define LCD_BLINKRATE_gp 0 /* LCD Blink Rate group position. */ -+#define LCD_BLINKRATE0_bm (1<<0) /* LCD Blink Rate bit 0 mask. */ -+#define LCD_BLINKRATE0_bp 0 /* LCD Blink Rate bit 0 position. */ -+#define LCD_BLINKRATE1_bm (1<<1) /* LCD Blink Rate bit 1 mask. */ -+#define LCD_BLINKRATE1_bp 1 /* LCD Blink Rate bit 1 position. */ -+ -+/* LCD.CTRLE bit masks and bit positions */ -+#define LCD_BPS1_gm 0xF0 /* Blink Pixel Selection 1 group mask. */ -+#define LCD_BPS1_gp 4 /* Blink Pixel Selection 1 group position. */ -+#define LCD_BPS10_bm (1<<4) /* Blink Pixel Selection 1 bit 0 mask. */ -+#define LCD_BPS10_bp 4 /* Blink Pixel Selection 1 bit 0 position. */ -+#define LCD_BPS11_bm (1<<5) /* Blink Pixel Selection 1 bit 1 mask. */ -+#define LCD_BPS11_bp 5 /* Blink Pixel Selection 1 bit 1 position. */ -+#define LCD_BPS12_bm (1<<6) /* Blink Pixel Selection 1 bit 2 mask. */ -+#define LCD_BPS12_bp 6 /* Blink Pixel Selection 1 bit 2 position. */ -+#define LCD_BPS13_bm (1<<7) /* Blink Pixel Selection 1 bit 3 mask. */ -+#define LCD_BPS13_bp 7 /* Blink Pixel Selection 1 bit 3 position. */ -+ -+#define LCD_BPS0_gm 0x0F /* Blink Pixel Selection 0 group mask. */ -+#define LCD_BPS0_gp 0 /* Blink Pixel Selection 0 group position. */ -+#define LCD_BPS00_bm (1<<0) /* Blink Pixel Selection 0 bit 0 mask. */ -+#define LCD_BPS00_bp 0 /* Blink Pixel Selection 0 bit 0 position. */ -+#define LCD_BPS01_bm (1<<1) /* Blink Pixel Selection 0 bit 1 mask. */ -+#define LCD_BPS01_bp 1 /* Blink Pixel Selection 0 bit 1 position. */ -+#define LCD_BPS02_bm (1<<2) /* Blink Pixel Selection 0 bit 2 mask. */ -+#define LCD_BPS02_bp 2 /* Blink Pixel Selection 0 bit 2 position. */ -+#define LCD_BPS03_bm (1<<3) /* Blink Pixel Selection 0 bit 3 mask. */ -+#define LCD_BPS03_bp 3 /* Blink Pixel Selection 0 bit 3 position. */ -+ -+/* LCD.CTRLF bit masks and bit positions */ -+#define LCD_FCONT_gm 0x3F /* Fine Contrast group mask. */ -+#define LCD_FCONT_gp 0 /* Fine Contrast group position. */ -+#define LCD_FCONT0_bm (1<<0) /* Fine Contrast bit 0 mask. */ -+#define LCD_FCONT0_bp 0 /* Fine Contrast bit 0 position. */ -+#define LCD_FCONT1_bm (1<<1) /* Fine Contrast bit 1 mask. */ -+#define LCD_FCONT1_bp 1 /* Fine Contrast bit 1 position. */ -+#define LCD_FCONT2_bm (1<<2) /* Fine Contrast bit 2 mask. */ -+#define LCD_FCONT2_bp 2 /* Fine Contrast bit 2 position. */ -+#define LCD_FCONT3_bm (1<<3) /* Fine Contrast bit 3 mask. */ -+#define LCD_FCONT3_bp 3 /* Fine Contrast bit 3 position. */ -+#define LCD_FCONT4_bm (1<<4) /* Fine Contrast bit 4 mask. */ -+#define LCD_FCONT4_bp 4 /* Fine Contrast bit 4 position. */ -+#define LCD_FCONT5_bm (1<<5) /* Fine Contrast bit 5 mask. */ -+#define LCD_FCONT5_bp 5 /* Fine Contrast bit 5 position. */ -+ -+/* LCD.CTRLG bit masks and bit positions */ -+#define LCD_TDG_gm 0xC0 /* Type of Digit group mask. */ -+#define LCD_TDG_gp 6 /* Type of Digit group position. */ -+#define LCD_TDG0_bm (1<<6) /* Type of Digit bit 0 mask. */ -+#define LCD_TDG0_bp 6 /* Type of Digit bit 0 position. */ -+#define LCD_TDG1_bm (1<<7) /* Type of Digit bit 1 mask. */ -+#define LCD_TDG1_bp 7 /* Type of Digit bit 1 position. */ -+ -+#define LCD_STSEG_gm 0x3F /* Start Segment group mask. */ -+#define LCD_STSEG_gp 0 /* Start Segment group position. */ -+#define LCD_STSEG0_bm (1<<0) /* Start Segment bit 0 mask. */ -+#define LCD_STSEG0_bp 0 /* Start Segment bit 0 position. */ -+#define LCD_STSEG1_bm (1<<1) /* Start Segment bit 1 mask. */ -+#define LCD_STSEG1_bp 1 /* Start Segment bit 1 position. */ -+#define LCD_STSEG2_bm (1<<2) /* Start Segment bit 2 mask. */ -+#define LCD_STSEG2_bp 2 /* Start Segment bit 2 position. */ -+#define LCD_STSEG3_bm (1<<3) /* Start Segment bit 3 mask. */ -+#define LCD_STSEG3_bp 3 /* Start Segment bit 3 position. */ -+#define LCD_STSEG4_bm (1<<4) /* Start Segment bit 4 mask. */ -+#define LCD_STSEG4_bp 4 /* Start Segment bit 4 position. */ -+#define LCD_STSEG5_bm (1<<5) /* Start Segment bit 5 mask. */ -+#define LCD_STSEG5_bp 5 /* Start Segment bit 5 position. */ -+ -+/* LCD.CTRLH bit masks and bit positions */ -+#define LCD_DEC_bm 0x80 /* Decrement of Start Segment bit mask. */ -+#define LCD_DEC_bp 7 /* Decrement of Start Segment bit position. */ -+ -+#define LCD_DCODE_gm 0x7F /* Display Code group mask. */ -+#define LCD_DCODE_gp 0 /* Display Code group position. */ -+#define LCD_DCODE0_bm (1<<0) /* Display Code bit 0 mask. */ -+#define LCD_DCODE0_bp 0 /* Display Code bit 0 position. */ -+#define LCD_DCODE1_bm (1<<1) /* Display Code bit 1 mask. */ -+#define LCD_DCODE1_bp 1 /* Display Code bit 1 position. */ -+#define LCD_DCODE2_bm (1<<2) /* Display Code bit 2 mask. */ -+#define LCD_DCODE2_bp 2 /* Display Code bit 2 position. */ -+#define LCD_DCODE3_bm (1<<3) /* Display Code bit 3 mask. */ -+#define LCD_DCODE3_bp 3 /* Display Code bit 3 position. */ -+#define LCD_DCODE4_bm (1<<4) /* Display Code bit 4 mask. */ -+#define LCD_DCODE4_bp 4 /* Display Code bit 4 position. */ -+#define LCD_DCODE5_bm (1<<5) /* Display Code bit 5 mask. */ -+#define LCD_DCODE5_bp 5 /* Display Code bit 5 position. */ -+#define LCD_DCODE6_bm (1<<6) /* Display Code bit 6 mask. */ -+#define LCD_DCODE6_bp 6 /* Display Code bit 6 position. */ -+ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -+#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -+#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -+#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -+#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -+#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -+#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -+#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -+#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -+#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -+#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -+#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -+#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -+#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -+#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -+#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -+#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -+#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -+#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ -+ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -+#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -+#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* LOCKBIT - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT0_vect_num 2 -+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -+#define PORTC_INT1_vect_num 3 -+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT0_vect_num 4 -+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -+#define PORTR_INT1_vect_num 5 -+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ -+ -+/* DMA interrupt vectors */ -+#define DMA_CH0_vect_num 6 -+#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -+#define DMA_CH1_vect_num 7 -+#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -+ -+/* RTC interrupt vectors */ -+#define RTC_OVF_vect_num 10 -+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -+#define RTC_COMP_vect_num 11 -+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 12 -+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 13 -+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_OVF_vect_num 14 -+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -+#define TCC0_ERR_vect_num 15 -+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -+#define TCC0_CCA_vect_num 16 -+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -+#define TCC0_CCB_vect_num 17 -+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -+#define TCC0_CCC_vect_num 18 -+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -+#define TCC0_CCD_vect_num 19 -+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ -+ -+/* TCC1 interrupt vectors */ -+#define TCC1_OVF_vect_num 20 -+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -+#define TCC1_ERR_vect_num 21 -+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -+#define TCC1_CCA_vect_num 22 -+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -+#define TCC1_CCB_vect_num 23 -+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 24 -+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 25 -+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 26 -+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 27 -+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ -+ -+/* USB interrupt vectors */ -+#define USB_BUSEVENT_vect_num 31 -+#define USB_BUSEVENT_vect _VECTOR(31) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -+#define USB_TRNCOMPL_vect_num 32 -+#define USB_TRNCOMPL_vect _VECTOR(32) /* Transaction complete interrupt */ -+ -+/* LCD interrupt vectors */ -+#define LCD_INT_vect_num 35 -+#define LCD_INT_vect _VECTOR(35) /* LCD Interrupt */ -+ -+/* AES interrupt vectors */ -+#define AES_INT_vect_num 36 -+#define AES_INT_vect _VECTOR(36) /* AES Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 37 -+#define NVM_EE_vect _VECTOR(37) /* EE Interrupt */ -+#define NVM_SPM_vect_num 38 -+#define NVM_SPM_vect _VECTOR(38) /* SPM Interrupt */ -+ -+/* PORTB interrupt vectors */ -+#define PORTB_INT0_vect_num 39 -+#define PORTB_INT0_vect _VECTOR(39) /* External Interrupt 0 */ -+#define PORTB_INT1_vect_num 40 -+#define PORTB_INT1_vect _VECTOR(40) /* External Interrupt 1 */ -+ -+/* ACB interrupt vectors */ -+#define ACB_AC0_vect_num 41 -+#define ACB_AC0_vect _VECTOR(41) /* AC0 Interrupt */ -+#define ACB_AC1_vect_num 42 -+#define ACB_AC1_vect _VECTOR(42) /* AC1 Interrupt */ -+#define ACB_ACW_vect_num 43 -+#define ACB_ACW_vect _VECTOR(43) /* ACW Window Mode Interrupt */ -+ -+/* ADCB interrupt vectors */ -+#define ADCB_CH0_vect_num 44 -+#define ADCB_CH0_vect _VECTOR(44) /* Interrupt 0 */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT0_vect_num 48 -+#define PORTD_INT0_vect _VECTOR(48) /* External Interrupt 0 */ -+#define PORTD_INT1_vect_num 49 -+#define PORTD_INT1_vect _VECTOR(49) /* External Interrupt 1 */ -+ -+/* PORTG interrupt vectors */ -+#define PORTG_INT0_vect_num 50 -+#define PORTG_INT0_vect _VECTOR(50) /* External Interrupt 0 */ -+#define PORTG_INT1_vect_num 51 -+#define PORTG_INT1_vect _VECTOR(51) /* External Interrupt 1 */ -+ -+/* PORTM interrupt vectors */ -+#define PORTM_INT0_vect_num 52 -+#define PORTM_INT0_vect _VECTOR(52) /* External Interrupt 0 */ -+#define PORTM_INT1_vect_num 53 -+#define PORTM_INT1_vect _VECTOR(53) /* External Interrupt 1 */ -+ -+/* PORTE interrupt vectors */ -+#define PORTE_INT0_vect_num 54 -+#define PORTE_INT0_vect _VECTOR(54) /* External Interrupt 0 */ -+#define PORTE_INT1_vect_num 55 -+#define PORTE_INT1_vect _VECTOR(55) /* External Interrupt 1 */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_OVF_vect_num 58 -+#define TCE0_OVF_vect _VECTOR(58) /* Overflow Interrupt */ -+#define TCE0_ERR_vect_num 59 -+#define TCE0_ERR_vect _VECTOR(59) /* Error Interrupt */ -+#define TCE0_CCA_vect_num 60 -+#define TCE0_CCA_vect _VECTOR(60) /* Compare or Capture A Interrupt */ -+#define TCE0_CCB_vect_num 61 -+#define TCE0_CCB_vect _VECTOR(61) /* Compare or Capture B Interrupt */ -+#define TCE0_CCC_vect_num 62 -+#define TCE0_CCC_vect _VECTOR(62) /* Compare or Capture C Interrupt */ -+#define TCE0_CCD_vect_num 63 -+#define TCE0_CCD_vect _VECTOR(63) /* Compare or Capture D Interrupt */ -+ -+/* USARTE0 interrupt vectors */ -+#define USARTE0_RXC_vect_num 69 -+#define USARTE0_RXC_vect _VECTOR(69) /* Reception Complete Interrupt */ -+#define USARTE0_DRE_vect_num 70 -+#define USARTE0_DRE_vect _VECTOR(70) /* Data Register Empty Interrupt */ -+#define USARTE0_TXC_vect_num 71 -+#define USARTE0_TXC_vect _VECTOR(71) /* Transmission Complete Interrupt */ -+ -+/* PORTA interrupt vectors */ -+#define PORTA_INT0_vect_num 75 -+#define PORTA_INT0_vect _VECTOR(75) /* External Interrupt 0 */ -+#define PORTA_INT1_vect_num 76 -+#define PORTA_INT1_vect _VECTOR(76) /* External Interrupt 1 */ -+ -+/* ACA interrupt vectors */ -+#define ACA_AC0_vect_num 77 -+#define ACA_AC0_vect _VECTOR(77) /* AC0 Interrupt */ -+#define ACA_AC1_vect_num 78 -+#define ACA_AC1_vect _VECTOR(78) /* AC1 Interrupt */ -+#define ACA_ACW_vect_num 79 -+#define ACA_ACW_vect _VECTOR(79) /* ACW Window Mode Interrupt */ -+ -+/* ADCA interrupt vectors */ -+#define ADCA_CH0_vect_num 80 -+#define ADCA_CH0_vect _VECTOR(80) /* Interrupt 0 */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (81 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (69632) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (65536) -+#define APP_SECTION_PAGE_SIZE (256) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0xF000) -+#define APPTABLE_SECTION_SIZE (4096) -+#define APPTABLE_SECTION_PAGE_SIZE (256) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x10000) -+#define BOOT_SECTION_SIZE (4096) -+#define BOOT_SECTION_PAGE_SIZE (256) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (12288) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (2048) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (4096) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (2048) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (6) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (256) -+#define USER_SIGNATURES_PAGE_SIZE (256) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (52) -+#define PROD_SIGNATURES_PAGE_SIZE (256) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 256 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 6 -+ -+/* Fuse Byte 0 */ -+#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -+#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -+#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -+#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -+#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -+#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -+#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -+#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -+#define FUSE0_DEFAULT (0xFF) -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x96 -+#define SIGNATURE_2 0x52 -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA64B1_H_INCLUDED */ -+ -diff --git a/include/avr/iox64b3.h b/include/avr/iox64b3.h -new file mode 100644 -index 0000000..af51a13 ---- /dev/null -+++ b/include/avr/iox64b3.h -@@ -0,0 +1,6247 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox64b3.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA64B3_H_INCLUDED -+#define _AVR_ATXMEGA64B3_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+VPORT - Virtual Ports -+-------------------------------------------------------------------------- -+*/ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t USBCTRL; /* USB Control Register */ -+} CLK_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+/* USB Prescaler Division Factor */ -+typedef enum CLK_USBPSDIV_enum -+{ -+ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ -+ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ -+ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ -+ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ -+ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ -+ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -+} CLK_USBPSDIV_t; -+ -+/* USB Clock Source */ -+typedef enum CLK_USBSRC_enum -+{ -+ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ -+ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -+} CLK_USBSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control Register */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C0_gc = (0x01<<0), /* External Clock on port C0 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C1_gc = (0x05<<0), /* External Clock on port C1 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C2_gc = (0x09<<0), /* External Clock on port C2 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C3_gc = (0x0D<<0), /* External Clock on port C3 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C4_gc = (0x11<<0), /* External Clock on port C4 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C5_gc = (0x15<<0), /* External Clock on port C5 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C6_gc = (0x19<<0), /* External Clock on port C6 - 6 CLK */ -+ OSC_XOSCSEL_EXTCLK_C7_gc = (0x1D<<0), /* External Clock on port C7 - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+/* 2 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC2MCREF_enum -+{ -+ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC2MCREF_t; -+ -+/* 32 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC32MCREF_enum -+{ -+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -+} OSC_RC32MCREF_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PR - Power Reduction -+-------------------------------------------------------------------------- -+*/ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t PRPB; /* Power Reduction Port B */ -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t reserved_0x04; -+ register8_t PRPE; /* Power Reduction Port E */ -+} PR_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t JTAGUID; /* JTAG User ID */ -+ register8_t reserved_0x05; -+ register8_t MCUCR; /* MCU Control */ -+ register8_t ANAINIT; /* Analog Startup Delay */ -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t AWEXLOCK; /* AWEX Lock */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORTCFG - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t VPCTRLA; /* Virtual Port Control Register A */ -+ register8_t VPCTRLB; /* Virtual Port Control Register B */ -+ register8_t CLKEVOUT; /* Clock and Event Out Register */ -+ register8_t reserved_0x05; -+ register8_t EVOUTSEL; /* Event Output Select */ -+} PORTCFG_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP02MAP_enum -+{ -+ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ -+ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ -+ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ -+ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ -+ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ -+ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ -+ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ -+ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -+} PORTCFG_VP02MAP_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP13MAP_enum -+{ -+ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ -+ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ -+ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ -+ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ -+ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ -+ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ -+ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ -+ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -+} PORTCFG_VP13MAP_t; -+ -+/* System Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC_gc = (0x01<<0), /* System Clock Output on Port C */ -+ PORTCFG_CLKOUT_PE_gc = (0x03<<0), /* System Clock Output on Port E */ -+} PORTCFG_CLKOUT_t; -+ -+/* Peripheral Clock Output Select */ -+typedef enum PORTCFG_CLKOUTSEL_enum -+{ -+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -+} PORTCFG_CLKOUTSEL_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC_gc = (0x01<<4), /* Event Channel 0 Output on Port C */ -+ PORTCFG_EVOUT_PE_gc = (0x03<<4), /* Event Channel 0 Output on Port E */ -+} PORTCFG_EVOUT_t; -+ -+/* Clock and Event Output Port */ -+typedef enum PORTCFG_CLKEVPIN_enum -+{ -+ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ -+ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -+} PORTCFG_CLKEVPIN_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<2), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<2), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<2), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<2), /* Event Channel 3 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AES - AES Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* AES Module */ -+typedef struct AES_struct -+{ -+ register8_t CTRL; /* AES Control Register */ -+ register8_t STATUS; /* AES Status Register */ -+ register8_t STATE; /* AES State Register */ -+ register8_t KEY; /* AES Key Register */ -+ register8_t INTCTRL; /* AES Interrupt Control Register */ -+} AES_t; -+ -+/* Interrupt level */ -+typedef enum AES_INTLVL_enum -+{ -+ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} AES_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ -+ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DMA - DMA Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* DMA Channel */ -+typedef struct DMA_CH_struct -+{ -+ register8_t CTRLA; /* Channel Control */ -+ register8_t CTRLB; /* Channel Control */ -+ register8_t ADDRCTRL; /* Address Control */ -+ register8_t TRIGSRC; /* Channel Trigger Source */ -+ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ -+ register8_t REPCNT; /* Channel Repeat Count */ -+ register8_t reserved_0x07; -+ register8_t SRCADDR0; /* Channel Source Address 0 */ -+ register8_t SRCADDR1; /* Channel Source Address 1 */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t DESTADDR0; /* Channel Destination Address 0 */ -+ register8_t DESTADDR1; /* Channel Destination Address 1 */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} DMA_CH_t; -+ -+ -+/* DMA Controller */ -+typedef struct DMA_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t reserved_0x01; -+ register8_t reserved_0x02; -+ register8_t INTFLAGS; /* Transfer Interrupt Status */ -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x05; -+ _WORDREGISTER(TEMP); /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ DMA_CH_t CH0; /* DMA Channel 0 */ -+ DMA_CH_t CH1; /* DMA Channel 1 */ -+} DMA_t; -+ -+/* Burst mode */ -+typedef enum DMA_CH_BURSTLEN_enum -+{ -+ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ -+ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ -+ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ -+ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ -+} DMA_CH_BURSTLEN_t; -+ -+/* Source address reload mode */ -+typedef enum DMA_CH_SRCRELOAD_enum -+{ -+ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ -+ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ -+ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ -+ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ -+} DMA_CH_SRCRELOAD_t; -+ -+/* Source addressing mode */ -+typedef enum DMA_CH_SRCDIR_enum -+{ -+ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ -+ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ -+ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ -+} DMA_CH_SRCDIR_t; -+ -+/* Destination adress reload mode */ -+typedef enum DMA_CH_DESTRELOAD_enum -+{ -+ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ -+ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ -+ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ -+ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ -+} DMA_CH_DESTRELOAD_t; -+ -+/* Destination adressing mode */ -+typedef enum DMA_CH_DESTDIR_enum -+{ -+ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ -+ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ -+ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ -+} DMA_CH_DESTDIR_t; -+ -+/* Transfer trigger source */ -+typedef enum DMA_CH_TRIGSRC_enum -+{ -+ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ -+ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ -+ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ -+ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ -+ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ -+ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ -+ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ -+ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ -+ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ -+ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ -+ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ -+ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ -+ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ -+ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ -+ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ -+ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ -+ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ -+ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ -+ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ -+ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ -+ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ -+} DMA_CH_TRIGSRC_t; -+ -+/* Double buffering mode */ -+typedef enum DMA_DBUFMODE_enum -+{ -+ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ -+ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ -+} DMA_DBUFMODE_t; -+ -+/* Priority mode */ -+typedef enum DMA_PRIMODE_enum -+{ -+ DMA_PRIMODE_RR01_gc = (0x00<<0), /* Round Robin */ -+ DMA_PRIMODE_CH0RR1_gc = (0x01<<0), /* Channel 0 > channel 1 */ -+} DMA_PRIMODE_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_ERRINTLVL_enum -+{ -+ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ -+ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ -+ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ -+} DMA_CH_ERRINTLVL_t; -+ -+/* Interrupt level */ -+typedef enum DMA_CH_TRNINTLVL_enum -+{ -+ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ -+ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ -+} DMA_CH_TRNINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+} EVSYS_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ -+ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ -+ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ -+ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ -+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ -+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ -+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ -+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ -+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ -+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ -+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ -+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ -+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ -+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ -+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ -+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ -+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ -+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ -+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ -+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ -+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ -+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ -+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ -+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ -+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ -+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ -+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ -+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ -+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ -+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -+} EVSYS_CHMUX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ -+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ -+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ -+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ -+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} NVM_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t reserved_0x07; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+} ADC_t; -+ -+/* Current Limitation */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -+} ADC_CURRLIMIT_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+} ADC_CH_MUXNEG_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ -+ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ -+ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ -+ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+ register8_t CURRCTRL; /* Current Source Control Register */ -+ register8_t CURRCALIB; /* Current Source Calibration Register */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC - Real-Time Counter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Real-Time Counter */ -+typedef struct RTC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary register */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ _WORDREGISTER(CNT); /* Count Register */ -+ _WORDREGISTER(PER); /* Period Register */ -+ _WORDREGISTER(COMP); /* Compare Register */ -+} RTC_t; -+ -+/* Prescaler Factor */ -+typedef enum RTC_PRESCALER_enum -+{ -+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ -+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ -+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ -+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ -+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ -+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ -+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ -+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -+} RTC_PRESCALER_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC_COMPINTLVL_enum -+{ -+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC_OVFINTLVL_enum -+{ -+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+} TWI_t; -+ -+/* SDA Hold Time */ -+typedef enum TWI_SDAHOLD_enum -+{ -+ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ -+ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ -+ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ -+ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -+} TWI_SDAHOLD_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USB - USB -+-------------------------------------------------------------------------- -+*/ -+ -+/* USB Endpoint */ -+typedef struct USB_EP_struct -+{ -+ register8_t STATUS; /* Endpoint Status */ -+ register8_t CTRL; /* Endpoint Control */ -+ _WORDREGISTER(CNT); /* USB Endpoint Counter */ -+ _WORDREGISTER(DATAPTR); /* Data Pointer */ -+ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -+} USB_EP_t; -+ -+ -+/* Universal Serial Bus */ -+typedef struct USB_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t FIFOWP; /* FIFO Write Pointer Register */ -+ register8_t FIFORP; /* FIFO Read Pointer Register */ -+ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ -+ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ -+ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ -+ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t reserved_0x20; -+ register8_t reserved_0x21; -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t CAL0; /* Calibration Byte 0 */ -+ register8_t CAL1; /* Calibration Byte 1 */ -+} USB_t; -+ -+ -+/* USB Endpoint Table */ -+typedef struct USB_EP_TABLE_struct -+{ -+ USB_EP_t EP0OUT; /* Endpoint 0 */ -+ USB_EP_t EP0IN; /* Endpoint 0 */ -+ USB_EP_t EP1OUT; /* Endpoint 1 */ -+ USB_EP_t EP1IN; /* Endpoint 1 */ -+ USB_EP_t EP2OUT; /* Endpoint 2 */ -+ USB_EP_t EP2IN; /* Endpoint 2 */ -+ USB_EP_t EP3OUT; /* Endpoint 3 */ -+ USB_EP_t EP3IN; /* Endpoint 3 */ -+ USB_EP_t EP4OUT; /* Endpoint 4 */ -+ USB_EP_t EP4IN; /* Endpoint 4 */ -+ USB_EP_t EP5OUT; /* Endpoint 5 */ -+ USB_EP_t EP5IN; /* Endpoint 5 */ -+ USB_EP_t EP6OUT; /* Endpoint 6 */ -+ USB_EP_t EP6IN; /* Endpoint 6 */ -+ USB_EP_t EP7OUT; /* Endpoint 7 */ -+ USB_EP_t EP7IN; /* Endpoint 7 */ -+ USB_EP_t EP8OUT; /* Endpoint 8 */ -+ USB_EP_t EP8IN; /* Endpoint 8 */ -+ USB_EP_t EP9OUT; /* Endpoint 9 */ -+ USB_EP_t EP9IN; /* Endpoint 9 */ -+ USB_EP_t EP10OUT; /* Endpoint 10 */ -+ USB_EP_t EP10IN; /* Endpoint 10 */ -+ USB_EP_t EP11OUT; /* Endpoint 11 */ -+ USB_EP_t EP11IN; /* Endpoint 11 */ -+ USB_EP_t EP12OUT; /* Endpoint 12 */ -+ USB_EP_t EP12IN; /* Endpoint 12 */ -+ USB_EP_t EP13OUT; /* Endpoint 13 */ -+ USB_EP_t EP13IN; /* Endpoint 13 */ -+ USB_EP_t EP14OUT; /* Endpoint 14 */ -+ USB_EP_t EP14IN; /* Endpoint 14 */ -+ USB_EP_t EP15OUT; /* Endpoint 15 */ -+ USB_EP_t EP15IN; /* Endpoint 15 */ -+ register8_t reserved_0x100; -+ register8_t reserved_0x101; -+ register8_t reserved_0x102; -+ register8_t reserved_0x103; -+ register8_t reserved_0x104; -+ register8_t reserved_0x105; -+ register8_t reserved_0x106; -+ register8_t reserved_0x107; -+ register8_t reserved_0x108; -+ register8_t reserved_0x109; -+ register8_t reserved_0x10A; -+ register8_t reserved_0x10B; -+ register8_t reserved_0x10C; -+ register8_t reserved_0x10D; -+ register8_t reserved_0x10E; -+ register8_t reserved_0x10F; -+ register8_t FRAMENUML; /* Frame Number Low Byte */ -+ register8_t FRAMENUMH; /* Frame Number High Byte */ -+} USB_EP_TABLE_t; -+ -+/* Interrupt level */ -+typedef enum USB_INTLVL_enum -+{ -+ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} USB_INTLVL_t; -+ -+/* USB Endpoint Type */ -+typedef enum USB_EP_TYPE_enum -+{ -+ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ -+ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ -+ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ -+ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -+} USB_EP_TYPE_t; -+ -+/* USB Endpoint Buffersize */ -+typedef enum USB_EP_BUFSIZE_enum -+{ -+ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ -+ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ -+ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ -+ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ -+ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ -+ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ -+ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ -+ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -+} USB_EP_BUFSIZE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - I/O Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INT0MASK; /* Port Interrupt 0 Mask */ -+ register8_t INT1MASK; /* Port Interrupt 1 Mask */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t REMAP; /* I/O Port Pin Remap Register */ -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Port Interrupt 0 Level */ -+typedef enum PORT_INT0LVL_enum -+{ -+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INT0LVL_t; -+ -+/* Port Interrupt 1 Level */ -+typedef enum PORT_INT1LVL_enum -+{ -+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ -+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ -+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -+} PORT_INT1LVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 0 */ -+typedef struct TC0_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC0_t; -+ -+ -+/* 16-bit Timer/Counter 1 */ -+typedef struct TC1_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+} TC1_t; -+ -+/* Clock Selection */ -+typedef enum TC_CLKSEL_enum -+{ -+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_CLKSEL_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC_WGMODE_enum -+{ -+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC_WGMODE_t; -+ -+/* Byte Mode */ -+typedef enum TC_BYTEM_enum -+{ -+ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ -+ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -+} TC_BYTEM_t; -+ -+/* Event Action */ -+typedef enum TC_EVACT_enum -+{ -+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ -+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ -+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ -+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ -+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ -+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC_EVSEL_enum -+{ -+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_EVSEL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC_ERRINTLVL_enum -+{ -+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC_OVFINTLVL_enum -+{ -+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_OVFINTLVL_t; -+ -+/* Compare or Capture D Interrupt Level */ -+typedef enum TC_CCDINTLVL_enum -+{ -+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC_CCDINTLVL_t; -+ -+/* Compare or Capture C Interrupt Level */ -+typedef enum TC_CCCINTLVL_enum -+{ -+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC_CCCINTLVL_t; -+ -+/* Compare or Capture B Interrupt Level */ -+typedef enum TC_CCBINTLVL_enum -+{ -+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_CCBINTLVL_t; -+ -+/* Compare or Capture A Interrupt Level */ -+typedef enum TC_CCAINTLVL_enum -+{ -+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_CCAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC_CMD_enum -+{ -+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AWEX - Timer/Counter Advanced Waveform Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Advanced Waveform Extension */ -+typedef struct AWEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t FDEMASK; /* Fault Detection Event Mask */ -+ register8_t FDCTRL; /* Fault Detection Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t STATUSSET; /* Status Set Register */ -+ register8_t DTBOTH; /* Dead Time Both Sides */ -+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ -+ register8_t DTLS; /* Dead Time Low Side */ -+ register8_t DTHS; /* Dead Time High Side */ -+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ -+ register8_t DTHSBUF; /* Dead Time High Side Buffer */ -+ register8_t OUTOVEN; /* Output Override Enable */ -+} AWEX_t; -+ -+/* Fault Detect Action */ -+typedef enum AWEX_FDACT_enum -+{ -+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ -+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -+} AWEX_FDACT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+HIRES - Timer/Counter High-Resolution Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register */ -+} HIRES_t; -+ -+/* High Resolution Enable */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ -+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+} IRDA_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LCD - LCD Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* LCD Controller */ -+typedef struct LCD_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t INTCTRL; /* Interrupt Enable Register */ -+ register8_t INTFLAG; /* Interrupt Flag Register */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t CTRLF; /* Control Register F */ -+ register8_t CTRLG; /* Control Register G */ -+ register8_t CTRLH; /* Control Register H */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t DATA0; /* LCD Data Register 0 */ -+ register8_t DATA1; /* LCD Data Register 1 */ -+ register8_t DATA2; /* LCD Data Register 2 */ -+ register8_t DATA3; /* LCD Data Register 3 */ -+ register8_t DATA4; /* LCD Data Register 4 */ -+ register8_t DATA5; /* LCD Data Register 5 */ -+ register8_t DATA6; /* LCD Data Register 6 */ -+ register8_t DATA7; /* LCD Data Register 7 */ -+ register8_t DATA8; /* LCD Data Register 8 */ -+ register8_t DATA9; /* LCD Data Register 9 */ -+ register8_t DATA10; /* LCD Data Register 10 */ -+ register8_t DATA11; /* LCD Data Register 11 */ -+ register8_t DATA12; /* LCD Data Register 12 */ -+ register8_t DATA13; /* LCD Data Register 13 */ -+ register8_t DATA14; /* LCD Data Register 14 */ -+ register8_t DATA15; /* LCD Data Register 15 */ -+ register8_t DATA16; /* LCD Data Register 16 */ -+ register8_t DATA17; /* LCD Data Register 17 */ -+ register8_t DATA18; /* LCD Data Register 18 */ -+ register8_t DATA19; /* LCD Data Register 19 */ -+} LCD_t; -+ -+/* LCD Blink Rate */ -+typedef enum LCD_BLINKRATE_enum -+{ -+ LCD_BLINKRATE_4Hz_gc = (0x00<<0), /* 4Hz Blink Rate */ -+ LCD_BLINKRATE_2Hz_gc = (0x01<<0), /* 2Hz Blink Rate */ -+ LCD_BLINKRATE_1Hz_gc = (0x02<<0), /* 1Hz Blink Rate */ -+ LCD_BLINKRATE_0Hz5_gc = (0x03<<0), /* 0.5Hz Blink Rate */ -+} LCD_BLINKRATE_t; -+ -+/* LCD Clock Divide */ -+typedef enum LCD_CLKDIV_enum -+{ -+ LCD_CLKDIV_DivBy1_gc = (0x00<<4), /* frame rate of 256 Hz */ -+ LCD_CLKDIV_DivBy2_gc = (0x01<<4), /* frame rate of 128 Hz */ -+ LCD_CLKDIV_DivBy3_gc = (0x02<<4), /* frame rate of 83.5 Hz */ -+ LCD_CLKDIV_DivBy4_gc = (0x03<<4), /* frame rate of 64 Hz */ -+ LCD_CLKDIV_DivBy5_gc = (0x04<<4), /* frame rate of 51.2 Hz */ -+ LCD_CLKDIV_DivBy6_gc = (0x05<<4), /* frame rate of 42.7 Hz */ -+ LCD_CLKDIV_DivBy7_gc = (0x06<<4), /* frame rate of 36.6 Hz */ -+ LCD_CLKDIV_DivBy8_gc = (0x07<<4), /* frame rate of 32 Hz */ -+} LCD_CLKDIV_t; -+ -+/* Duty Select */ -+typedef enum LCD_DUTY_enum -+{ -+ LCD_DUTY_1_4_gc = (0x00<<0), /* Duty=1/4, Bias=1/3, COM0:3 */ -+ LCD_DUTY_Static_gc = (0x01<<0), /* Duty=Static, Bias=Static, COM0 */ -+ LCD_DUTY_1_2_gc = (0x02<<0), /* Duty=1/2, Bias=1/3, COM0:1 */ -+ LCD_DUTY_1_3_gc = (0x03<<0), /* Duty=1/3, Bias=1/3, COM0:2 */ -+} LCD_DUTY_t; -+ -+/* LCD Prescaler Select */ -+typedef enum LCD_PRESC_enum -+{ -+ LCD_PRESC_8_gc = (0x00<<7), /* clk_lcd/8 */ -+ LCD_PRESC_16_gc = (0x01<<7), /* clk_lcd/16 */ -+} LCD_PRESC_t; -+ -+/* Type of Digit */ -+typedef enum LCD_TDG_enum -+{ -+ LCD_TDG_7S_3C_gc = (0x00<<6), /* 7-segment with 3 COMs */ -+ LCD_TDG_7S_4C_gc = (0x01<<6), /* 7-segment with 4 COMs */ -+ LCD_TDG_14S_4C_gc = (0x02<<6), /* 14-segment with 4 COMs */ -+ LCD_TDG_16S_3C_gc = (0x03<<6), /* 16-segment with 3 COMs */ -+} LCD_TDG_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t FUSEBYTE0; /* JTAG User ID */ -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+} NVM_FUSES_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* Timer Oscillator pin location */ -+typedef enum TOSCSEL_enum -+{ -+ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ -+ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -+} TOSCSEL_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -+} BOD_t; -+ -+/* BOD operation */ -+typedef enum BODACT_enum -+{ -+ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BODACT_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WDP_enum -+{ -+ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ -+ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ -+ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ -+ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ -+ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ -+ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ -+ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ -+ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ -+ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ -+ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ -+ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -+} WDP_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LOCKBIT - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ -+ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t USBCAL0; /* USB Calibration Byte 0 */ -+ register8_t USBCAL1; /* USB Calibration Byte 1 */ -+ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ -+ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ -+ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+ register8_t reserved_0x40; -+ register8_t reserved_0x41; -+ register8_t reserved_0x42; -+ register8_t reserved_0x43; -+ register8_t reserved_0x44; -+ register8_t reserved_0x45; -+ register8_t reserved_0x46; -+ register8_t reserved_0x47; -+} NVM_PROD_SIGNATURES_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define AES (*(AES_t *) 0x00C0) /* AES Module */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ -+#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ -+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -+#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTG (*(PORT_t *) 0x06C0) /* I/O Ports */ -+#define PORTM (*(PORT_t *) 0x0760) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -+#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define LCD (*(LCD_t *) 0x0D00) /* LCD Controller */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -+#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -+#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -+#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) -+#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+#define CLK_USBCTRL _SFR_MEM8(0x0044) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* DFLL - DFLL */ -+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -+#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -+#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPB _SFR_MEM8(0x0072) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPE _SFR_MEM8(0x0075) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_JTAGUID _SFR_MEM8(0x0094) -+#define MCU_MCUCR _SFR_MEM8(0x0096) -+#define MCU_ANAINIT _SFR_MEM8(0x0097) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_AWEXLOCK _SFR_MEM8(0x0099) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) -+ -+/* AES - AES Module */ -+#define AES_CTRL _SFR_MEM8(0x00C0) -+#define AES_STATUS _SFR_MEM8(0x00C1) -+#define AES_STATE _SFR_MEM8(0x00C2) -+#define AES_KEY _SFR_MEM8(0x00C3) -+#define AES_INTCTRL _SFR_MEM8(0x00C4) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* DMA - DMA Controller */ -+#define DMA_CTRL _SFR_MEM8(0x0100) -+#define DMA_INTFLAGS _SFR_MEM8(0x0103) -+#define DMA_STATUS _SFR_MEM8(0x0104) -+#define DMA_TEMP _SFR_MEM16(0x0106) -+#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) -+#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) -+#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -+#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) -+#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) -+#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) -+#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) -+#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) -+#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) -+#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) -+#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) -+#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) -+#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -+#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) -+#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) -+#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) -+#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) -+#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) -+#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) -+#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCB_CTRLA _SFR_MEM8(0x0240) -+#define ADCB_CTRLB _SFR_MEM8(0x0241) -+#define ADCB_REFCTRL _SFR_MEM8(0x0242) -+#define ADCB_EVCTRL _SFR_MEM8(0x0243) -+#define ADCB_PRESCALER _SFR_MEM8(0x0244) -+#define ADCB_INTFLAGS _SFR_MEM8(0x0246) -+#define ADCB_TEMP _SFR_MEM8(0x0247) -+#define ADCB_SAMPCTRL _SFR_MEM8(0x0248) -+#define ADCB_CAL _SFR_MEM16(0x024C) -+#define ADCB_CH0RES _SFR_MEM16(0x0250) -+#define ADCB_CMP _SFR_MEM16(0x0258) -+#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) -+#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) -+#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) -+#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) -+#define ADCB_CH0_RES _SFR_MEM16(0x0264) -+#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) -+ -+/* AC - Analog Comparator */ -+#define ACB_AC0CTRL _SFR_MEM8(0x0390) -+#define ACB_AC1CTRL _SFR_MEM8(0x0391) -+#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) -+#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) -+#define ACB_CTRLA _SFR_MEM8(0x0394) -+#define ACB_CTRLB _SFR_MEM8(0x0395) -+#define ACB_WINCTRL _SFR_MEM8(0x0396) -+#define ACB_STATUS _SFR_MEM8(0x0397) -+#define ACB_CURRCTRL _SFR_MEM8(0x0398) -+#define ACB_CURRCALIB _SFR_MEM8(0x0399) -+ -+/* RTC - Real-Time Counter */ -+#define RTC_CTRL _SFR_MEM8(0x0400) -+#define RTC_STATUS _SFR_MEM8(0x0401) -+#define RTC_INTCTRL _SFR_MEM8(0x0402) -+#define RTC_INTFLAGS _SFR_MEM8(0x0403) -+#define RTC_TEMP _SFR_MEM8(0x0404) -+#define RTC_CNT _SFR_MEM16(0x0408) -+#define RTC_PER _SFR_MEM16(0x040A) -+#define RTC_COMP _SFR_MEM16(0x040C) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+ -+/* USB - Universal Serial Bus */ -+#define USB_CTRLA _SFR_MEM8(0x04C0) -+#define USB_CTRLB _SFR_MEM8(0x04C1) -+#define USB_STATUS _SFR_MEM8(0x04C2) -+#define USB_ADDR _SFR_MEM8(0x04C3) -+#define USB_FIFOWP _SFR_MEM8(0x04C4) -+#define USB_FIFORP _SFR_MEM8(0x04C5) -+#define USB_EPPTR _SFR_MEM16(0x04C6) -+#define USB_INTCTRLA _SFR_MEM8(0x04C8) -+#define USB_INTCTRLB _SFR_MEM8(0x04C9) -+#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -+#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -+#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -+#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -+#define USB_CAL0 _SFR_MEM8(0x04FA) -+#define USB_CAL1 _SFR_MEM8(0x04FB) -+ -+/* PORT - I/O Ports */ -+#define PORTB_DIR _SFR_MEM8(0x0620) -+#define PORTB_DIRSET _SFR_MEM8(0x0621) -+#define PORTB_DIRCLR _SFR_MEM8(0x0622) -+#define PORTB_DIRTGL _SFR_MEM8(0x0623) -+#define PORTB_OUT _SFR_MEM8(0x0624) -+#define PORTB_OUTSET _SFR_MEM8(0x0625) -+#define PORTB_OUTCLR _SFR_MEM8(0x0626) -+#define PORTB_OUTTGL _SFR_MEM8(0x0627) -+#define PORTB_IN _SFR_MEM8(0x0628) -+#define PORTB_INTCTRL _SFR_MEM8(0x0629) -+#define PORTB_INT0MASK _SFR_MEM8(0x062A) -+#define PORTB_INT1MASK _SFR_MEM8(0x062B) -+#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -+#define PORTB_REMAP _SFR_MEM8(0x062E) -+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INT0MASK _SFR_MEM8(0x064A) -+#define PORTC_INT1MASK _SFR_MEM8(0x064B) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INT0MASK _SFR_MEM8(0x066A) -+#define PORTD_INT1MASK _SFR_MEM8(0x066B) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTG_DIR _SFR_MEM8(0x06C0) -+#define PORTG_DIRSET _SFR_MEM8(0x06C1) -+#define PORTG_DIRCLR _SFR_MEM8(0x06C2) -+#define PORTG_DIRTGL _SFR_MEM8(0x06C3) -+#define PORTG_OUT _SFR_MEM8(0x06C4) -+#define PORTG_OUTSET _SFR_MEM8(0x06C5) -+#define PORTG_OUTCLR _SFR_MEM8(0x06C6) -+#define PORTG_OUTTGL _SFR_MEM8(0x06C7) -+#define PORTG_IN _SFR_MEM8(0x06C8) -+#define PORTG_INTCTRL _SFR_MEM8(0x06C9) -+#define PORTG_INT0MASK _SFR_MEM8(0x06CA) -+#define PORTG_INT1MASK _SFR_MEM8(0x06CB) -+#define PORTG_INTFLAGS _SFR_MEM8(0x06CC) -+#define PORTG_REMAP _SFR_MEM8(0x06CE) -+#define PORTG_PIN0CTRL _SFR_MEM8(0x06D0) -+#define PORTG_PIN1CTRL _SFR_MEM8(0x06D1) -+#define PORTG_PIN2CTRL _SFR_MEM8(0x06D2) -+#define PORTG_PIN3CTRL _SFR_MEM8(0x06D3) -+#define PORTG_PIN4CTRL _SFR_MEM8(0x06D4) -+#define PORTG_PIN5CTRL _SFR_MEM8(0x06D5) -+#define PORTG_PIN6CTRL _SFR_MEM8(0x06D6) -+#define PORTG_PIN7CTRL _SFR_MEM8(0x06D7) -+ -+/* PORT - I/O Ports */ -+#define PORTM_DIR _SFR_MEM8(0x0760) -+#define PORTM_DIRSET _SFR_MEM8(0x0761) -+#define PORTM_DIRCLR _SFR_MEM8(0x0762) -+#define PORTM_DIRTGL _SFR_MEM8(0x0763) -+#define PORTM_OUT _SFR_MEM8(0x0764) -+#define PORTM_OUTSET _SFR_MEM8(0x0765) -+#define PORTM_OUTCLR _SFR_MEM8(0x0766) -+#define PORTM_OUTTGL _SFR_MEM8(0x0767) -+#define PORTM_IN _SFR_MEM8(0x0768) -+#define PORTM_INTCTRL _SFR_MEM8(0x0769) -+#define PORTM_INT0MASK _SFR_MEM8(0x076A) -+#define PORTM_INT1MASK _SFR_MEM8(0x076B) -+#define PORTM_INTFLAGS _SFR_MEM8(0x076C) -+#define PORTM_REMAP _SFR_MEM8(0x076E) -+#define PORTM_PIN0CTRL _SFR_MEM8(0x0770) -+#define PORTM_PIN1CTRL _SFR_MEM8(0x0771) -+#define PORTM_PIN2CTRL _SFR_MEM8(0x0772) -+#define PORTM_PIN3CTRL _SFR_MEM8(0x0773) -+#define PORTM_PIN4CTRL _SFR_MEM8(0x0774) -+#define PORTM_PIN5CTRL _SFR_MEM8(0x0775) -+#define PORTM_PIN6CTRL _SFR_MEM8(0x0776) -+#define PORTM_PIN7CTRL _SFR_MEM8(0x0777) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -+#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCC0_CTRLA _SFR_MEM8(0x0800) -+#define TCC0_CTRLB _SFR_MEM8(0x0801) -+#define TCC0_CTRLC _SFR_MEM8(0x0802) -+#define TCC0_CTRLD _SFR_MEM8(0x0803) -+#define TCC0_CTRLE _SFR_MEM8(0x0804) -+#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -+#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -+#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -+#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC0_TEMP _SFR_MEM8(0x080F) -+#define TCC0_CNT _SFR_MEM16(0x0820) -+#define TCC0_PER _SFR_MEM16(0x0826) -+#define TCC0_CCA _SFR_MEM16(0x0828) -+#define TCC0_CCB _SFR_MEM16(0x082A) -+#define TCC0_CCC _SFR_MEM16(0x082C) -+#define TCC0_CCD _SFR_MEM16(0x082E) -+#define TCC0_PERBUF _SFR_MEM16(0x0836) -+#define TCC0_CCABUF _SFR_MEM16(0x0838) -+#define TCC0_CCBBUF _SFR_MEM16(0x083A) -+#define TCC0_CCCBUF _SFR_MEM16(0x083C) -+#define TCC0_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCC1_CTRLA _SFR_MEM8(0x0840) -+#define TCC1_CTRLB _SFR_MEM8(0x0841) -+#define TCC1_CTRLC _SFR_MEM8(0x0842) -+#define TCC1_CTRLD _SFR_MEM8(0x0843) -+#define TCC1_CTRLE _SFR_MEM8(0x0844) -+#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -+#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -+#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -+#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC1_TEMP _SFR_MEM8(0x084F) -+#define TCC1_CNT _SFR_MEM16(0x0860) -+#define TCC1_PER _SFR_MEM16(0x0866) -+#define TCC1_CCA _SFR_MEM16(0x0868) -+#define TCC1_CCB _SFR_MEM16(0x086A) -+#define TCC1_PERBUF _SFR_MEM16(0x0876) -+#define TCC1_CCABUF _SFR_MEM16(0x0878) -+#define TCC1_CCBBUF _SFR_MEM16(0x087A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXC_CTRL _SFR_MEM8(0x0880) -+#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -+#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -+#define AWEXC_STATUS _SFR_MEM8(0x0884) -+#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -+#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -+#define AWEXC_DTLS _SFR_MEM8(0x0888) -+#define AWEXC_DTHS _SFR_MEM8(0x0889) -+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x0890) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08A0) -+#define USARTC0_STATUS _SFR_MEM8(0x08A1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -+#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -+#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIC_CTRL _SFR_MEM8(0x08C0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -+#define SPIC_STATUS _SFR_MEM8(0x08C2) -+#define SPIC_DATA _SFR_MEM8(0x08C3) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* LCD - LCD Controller */ -+#define LCD_CTRLA _SFR_MEM8(0x0D00) -+#define LCD_CTRLB _SFR_MEM8(0x0D01) -+#define LCD_CTRLC _SFR_MEM8(0x0D02) -+#define LCD_INTCTRL _SFR_MEM8(0x0D03) -+#define LCD_INTFLAG _SFR_MEM8(0x0D04) -+#define LCD_CTRLD _SFR_MEM8(0x0D05) -+#define LCD_CTRLE _SFR_MEM8(0x0D06) -+#define LCD_CTRLF _SFR_MEM8(0x0D07) -+#define LCD_CTRLG _SFR_MEM8(0x0D08) -+#define LCD_CTRLH _SFR_MEM8(0x0D09) -+#define LCD_DATA0 _SFR_MEM8(0x0D10) -+#define LCD_DATA1 _SFR_MEM8(0x0D11) -+#define LCD_DATA2 _SFR_MEM8(0x0D12) -+#define LCD_DATA3 _SFR_MEM8(0x0D13) -+#define LCD_DATA4 _SFR_MEM8(0x0D14) -+#define LCD_DATA5 _SFR_MEM8(0x0D15) -+#define LCD_DATA6 _SFR_MEM8(0x0D16) -+#define LCD_DATA7 _SFR_MEM8(0x0D17) -+#define LCD_DATA8 _SFR_MEM8(0x0D18) -+#define LCD_DATA9 _SFR_MEM8(0x0D19) -+#define LCD_DATA10 _SFR_MEM8(0x0D1A) -+#define LCD_DATA11 _SFR_MEM8(0x0D1B) -+#define LCD_DATA12 _SFR_MEM8(0x0D1C) -+#define LCD_DATA13 _SFR_MEM8(0x0D1D) -+#define LCD_DATA14 _SFR_MEM8(0x0D1E) -+#define LCD_DATA15 _SFR_MEM8(0x0D1F) -+#define LCD_DATA16 _SFR_MEM8(0x0D20) -+#define LCD_DATA17 _SFR_MEM8(0x0D21) -+#define LCD_DATA18 _SFR_MEM8(0x0D22) -+#define LCD_DATA19 _SFR_MEM8(0x0D23) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* VPORT - Virtual Ports */ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* CLK.USBCTRL bit masks and bit positions */ -+#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -+#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -+#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -+#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -+#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -+#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -+#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -+#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ -+ -+#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -+#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -+#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ -+ -+#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ -+#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -+#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -+#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ -+ -+#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ -+ -+#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -+#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ -+ -+/* PR - Power Reduction */ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_LCD_bm 0x80 /* LCD Module bit mask. */ -+#define PR_LCD_bp 7 /* LCD Module bit position. */ -+ -+#define PR_USB_bm 0x40 /* USB bit mask. */ -+#define PR_USB_bp 6 /* USB bit position. */ -+ -+#define PR_AES_bm 0x10 /* AES bit mask. */ -+#define PR_AES_bp 4 /* AES bit position. */ -+ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -+#define PR_DMA_bp 0 /* DMA-Controller bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPB bit masks and bit positions */ -+/* PR_ADC Predefined. */ -+/* PR_ADC Predefined. */ -+ -+/* PR_AC Predefined. */ -+/* PR_AC Predefined. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -+#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ -+ -+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -+ -+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ -+ -+/* PR.PRPE bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.MCUCR bit masks and bit positions */ -+#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ -+#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ -+ -+/* MCU.ANAINIT bit masks and bit positions */ -+#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ -+#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ -+#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ -+#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ -+#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ -+#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ -+ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -+#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ -+ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.AWEXLOCK bit masks and bit positions */ -+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* PORTCFG - Port Configuration */ -+/* PORTCFG.VPCTRLA bit masks and bit positions */ -+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ -+ -+/* PORTCFG.VPCTRLB bit masks and bit positions */ -+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ -+ -+/* PORTCFG.CLKEVOUT bit masks and bit positions */ -+#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ -+ -+#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -+#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -+#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -+#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -+#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -+#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ -+ -+#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -+#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ -+ -+#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -+#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ -+ -+/* PORTCFG.EVOUTSEL bit masks and bit positions */ -+#define PORTCFG_EVOUTSEL_bm 0x04 /* Event Output Select bit mask. */ -+#define PORTCFG_EVOUTSEL_bp 2 /* Event Output Select bit position. */ -+ -+/* AES - AES Module */ -+/* AES.CTRL bit masks and bit positions */ -+#define AES_START_bm 0x80 /* Start/Run bit mask. */ -+#define AES_START_bp 7 /* Start/Run bit position. */ -+ -+#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ -+#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ -+ -+#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ -+#define AES_RESET_bp 5 /* AES Software Reset bit position. */ -+ -+#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ -+#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ -+ -+#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ -+#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ -+ -+/* AES.STATUS bit masks and bit positions */ -+#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ -+#define AES_ERROR_bp 7 /* AES Error bit position. */ -+ -+#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ -+#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ -+ -+/* AES.INTCTRL bit masks and bit positions */ -+#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define AES_INTLVL_gp 0 /* Interrupt level group position. */ -+#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* DMA - DMA Controller */ -+/* DMA_CH.CTRLA bit masks and bit positions */ -+#define DMA_CH_CHEN_bm 0x80 /* Channel Enable bit mask. */ -+#define DMA_CH_CHEN_bp 7 /* Channel Enable bit position. */ -+ -+#define DMA_CH_CHRST_bm 0x40 /* Channel Software Reset bit mask. */ -+#define DMA_CH_CHRST_bp 6 /* Channel Software Reset bit position. */ -+ -+#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -+#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ -+ -+#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -+#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ -+ -+#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -+#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ -+ -+#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ -+#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ -+#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ -+#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ -+#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ -+#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ -+ -+/* DMA_CH.CTRLB bit masks and bit positions */ -+#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ -+#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ -+ -+#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ -+#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ -+ -+#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ -+#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ -+ -+#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ -+#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ -+#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ -+#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ -+#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ -+#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ -+ -+#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ -+#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ -+#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ -+#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ -+#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ -+#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ -+ -+/* DMA_CH.ADDRCTRL bit masks and bit positions */ -+#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ -+#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ -+#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ -+#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ -+#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ -+#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ -+ -+#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ -+#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ -+#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ -+#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ -+#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ -+#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ -+ -+#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ -+#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ -+#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ -+#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ -+#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ -+#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ -+ -+#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ -+#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ -+#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ -+#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ -+#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ -+#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ -+ -+/* DMA_CH.TRIGSRC bit masks and bit positions */ -+#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -+#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -+#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -+#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -+#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -+#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -+#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -+#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -+#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -+#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -+#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -+#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -+#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -+#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -+#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -+#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -+#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -+#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ -+ -+/* DMA.CTRL bit masks and bit positions */ -+#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ -+#define DMA_ENABLE_bp 7 /* Enable bit position. */ -+ -+#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ -+#define DMA_RESET_bp 6 /* Software Reset bit position. */ -+ -+#define DMA_DBUFMODE_bm 0x04 /* Double Buffering Mode bit mask. */ -+#define DMA_DBUFMODE_bp 2 /* Double Buffering Mode bit position. */ -+ -+#define DMA_PRIMODE_bm 0x01 /* Channel Priority Mode bit mask. */ -+#define DMA_PRIMODE_bp 0 /* Channel Priority Mode bit position. */ -+ -+/* DMA.INTFLAGS bit masks and bit positions */ -+#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ -+#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ -+ -+#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ -+ -+#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -+#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ -+ -+/* DMA.STATUS bit masks and bit positions */ -+#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ -+#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ -+ -+#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ -+#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ -+ -+#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ -+#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ -+ -+#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ -+#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0x7F /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ -+ -+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ -+ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -+#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -+#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -+#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -+#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -+#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -+#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -+#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -+#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -+#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ -+ -+#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */ -+#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */ -+#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -+#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */ -+#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -+#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */ -+#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -+#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */ -+#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -+#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -+#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* ADC.SAMPCTRL bit masks and bit positions */ -+#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ -+#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ -+#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ -+#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ -+#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ -+#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ -+#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ -+#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ -+#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ -+#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ -+#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ -+#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ -+#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ -+#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* AC.CURRCTRL bit masks and bit positions */ -+#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ -+#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ -+ -+#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ -+#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ -+ -+#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ -+#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ -+ -+#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ -+#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ -+ -+/* AC.CURRCALIB bit masks and bit positions */ -+#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ -+#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ -+#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ -+#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ -+#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ -+#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ -+#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ -+#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ -+#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ -+#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ -+ -+/* RTC - Real-Time Counter */ -+/* RTC.CTRL bit masks and bit positions */ -+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ -+ -+/* RTC.STATUS bit masks and bit positions */ -+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC.INTCTRL bit masks and bit positions */ -+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC.INTFLAGS bit masks and bit positions */ -+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* USB - USB */ -+/* USB_EP.STATUS bit masks and bit positions */ -+#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -+#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ -+ -+#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -+#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ -+ -+#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -+#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ -+ -+#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -+#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ -+ -+#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -+#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ -+ -+#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -+#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ -+ -+#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -+#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ -+ -+#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -+#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ -+ -+#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ -+ -+#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ -+ -+#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -+#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ -+ -+/* USB_EP.CTRL bit masks and bit positions */ -+#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -+#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -+#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -+#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -+#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -+#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ -+ -+#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -+#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ -+ -+#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -+#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ -+ -+#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -+#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ -+ -+#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -+#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ -+ -+#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -+#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -+#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -+#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -+#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -+#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -+#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -+#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ -+ -+/* USB_EP.CNT bit masks and bit positions */ -+#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -+#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ -+ -+/* USB.CTRLA bit masks and bit positions */ -+#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -+#define USB_ENABLE_bp 7 /* USB Enable bit position. */ -+ -+#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -+#define USB_SPEED_bp 6 /* Speed Select bit position. */ -+ -+#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -+#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ -+ -+#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -+#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ -+ -+#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -+#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -+#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -+#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -+#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -+#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -+#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -+#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -+#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -+#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ -+ -+/* USB.CTRLB bit masks and bit positions */ -+#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -+#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ -+ -+#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -+#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ -+ -+#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -+#define USB_GNACK_bp 1 /* Global NACK bit position. */ -+ -+#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -+#define USB_ATTACH_bp 0 /* Attach bit position. */ -+ -+/* USB.STATUS bit masks and bit positions */ -+#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -+#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ -+ -+#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -+#define USB_RESUME_bp 2 /* Resume bit position. */ -+ -+#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -+#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ -+ -+#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -+#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ -+ -+/* USB.ADDR bit masks and bit positions */ -+#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -+#define USB_ADDR_gp 0 /* Device Address group position. */ -+#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -+#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -+#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -+#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -+#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -+#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -+#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -+#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -+#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -+#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -+#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -+#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -+#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -+#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ -+ -+/* USB.FIFOWP bit masks and bit positions */ -+#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -+#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -+#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -+#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -+#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -+#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -+#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -+#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -+#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -+#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -+#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -+#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ -+ -+/* USB.FIFORP bit masks and bit positions */ -+#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -+#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -+#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -+#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -+#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -+#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -+#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -+#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -+#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -+#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -+#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -+#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ -+ -+/* USB.INTCTRLA bit masks and bit positions */ -+#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -+#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ -+ -+#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -+#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ -+ -+#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -+#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ -+ -+#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -+#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ -+ -+#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* USB.INTCTRLB bit masks and bit positions */ -+#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -+#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ -+ -+#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -+#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ -+ -+/* USB.INTFLAGSACLR bit masks and bit positions */ -+#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -+#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ -+ -+#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -+#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ -+ -+#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -+#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ -+ -+#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -+#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ -+ -+#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -+#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ -+ -+#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -+#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ -+ -+#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -+#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ -+ -+#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -+#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSASET bit masks and bit positions */ -+/* USB_SOFIF Predefined. */ -+/* USB_SOFIF Predefined. */ -+ -+/* USB_SUSPENDIF Predefined. */ -+/* USB_SUSPENDIF Predefined. */ -+ -+/* USB_RESUMEIF Predefined. */ -+/* USB_RESUMEIF Predefined. */ -+ -+/* USB_RSTIF Predefined. */ -+/* USB_RSTIF Predefined. */ -+ -+/* USB_CRCIF Predefined. */ -+/* USB_CRCIF Predefined. */ -+ -+/* USB_UNFIF Predefined. */ -+/* USB_UNFIF Predefined. */ -+ -+/* USB_OVFIF Predefined. */ -+/* USB_OVFIF Predefined. */ -+ -+/* USB_STALLIF Predefined. */ -+/* USB_STALLIF Predefined. */ -+ -+/* USB.INTFLAGSBCLR bit masks and bit positions */ -+#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -+#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ -+ -+#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -+#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSBSET bit masks and bit positions */ -+/* USB_TRNIF Predefined. */ -+/* USB_TRNIF Predefined. */ -+ -+/* USB_SETUPIF Predefined. */ -+/* USB_SETUPIF Predefined. */ -+ -+/* PORT - I/O Port Configuration */ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ -+ -+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -+#define PORT_SPI_bp 5 /* SPI bit position. */ -+ -+#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -+#define PORT_USART0_bp 4 /* USART0 bit position. */ -+ -+#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -+#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ -+ -+#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -+#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ -+ -+#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -+#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ -+ -+#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -+#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ -+ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC0.CTRLA bit masks and bit positions */ -+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC0.CTRLB bit masks and bit positions */ -+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ -+ -+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ -+ -+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC0.CTRLC bit masks and bit positions */ -+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ -+ -+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ -+ -+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC0.CTRLD bit masks and bit positions */ -+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC0_EVACT_gp 5 /* Event Action group position. */ -+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC0.CTRLE bit masks and bit positions */ -+#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC0.INTCTRLA bit masks and bit positions */ -+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC0.INTCTRLB bit masks and bit positions */ -+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ -+ -+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ -+ -+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC0.CTRLFCLR bit masks and bit positions */ -+#define TC0_CMD_gm 0x0C /* Command group mask. */ -+#define TC0_CMD_gp 2 /* Command group position. */ -+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC0_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC0_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC0_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC0.CTRLFSET bit masks and bit positions */ -+/* TC0_CMD Predefined. */ -+/* TC0_CMD Predefined. */ -+ -+/* TC0_LUPD Predefined. */ -+/* TC0_LUPD Predefined. */ -+ -+/* TC0_DIR Predefined. */ -+/* TC0_DIR Predefined. */ -+ -+/* TC0.CTRLGCLR bit masks and bit positions */ -+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ -+ -+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ -+ -+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC0.CTRLGSET bit masks and bit positions */ -+/* TC0_CCDBV Predefined. */ -+/* TC0_CCDBV Predefined. */ -+ -+/* TC0_CCCBV Predefined. */ -+/* TC0_CCCBV Predefined. */ -+ -+/* TC0_CCBBV Predefined. */ -+/* TC0_CCBBV Predefined. */ -+ -+/* TC0_CCABV Predefined. */ -+/* TC0_CCABV Predefined. */ -+ -+/* TC0_PERBV Predefined. */ -+/* TC0_PERBV Predefined. */ -+ -+/* TC0.INTFLAGS bit masks and bit positions */ -+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ -+ -+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ -+ -+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC1.CTRLA bit masks and bit positions */ -+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC1.CTRLB bit masks and bit positions */ -+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC1.CTRLC bit masks and bit positions */ -+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC1.CTRLD bit masks and bit positions */ -+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC1_EVACT_gp 5 /* Event Action group position. */ -+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC1.CTRLE bit masks and bit positions */ -+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ -+ -+/* TC1.INTCTRLA bit masks and bit positions */ -+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC1.INTCTRLB bit masks and bit positions */ -+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC1.CTRLFCLR bit masks and bit positions */ -+#define TC1_CMD_gm 0x0C /* Command group mask. */ -+#define TC1_CMD_gp 2 /* Command group position. */ -+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC1_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC1_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC1_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC1.CTRLFSET bit masks and bit positions */ -+/* TC1_CMD Predefined. */ -+/* TC1_CMD Predefined. */ -+ -+/* TC1_LUPD Predefined. */ -+/* TC1_LUPD Predefined. */ -+ -+/* TC1_DIR Predefined. */ -+/* TC1_DIR Predefined. */ -+ -+/* TC1.CTRLGCLR bit masks and bit positions */ -+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC1.CTRLGSET bit masks and bit positions */ -+/* TC1_CCBBV Predefined. */ -+/* TC1_CCBBV Predefined. */ -+ -+/* TC1_CCABV Predefined. */ -+/* TC1_CCABV Predefined. */ -+ -+/* TC1_PERBV Predefined. */ -+/* TC1_PERBV Predefined. */ -+ -+/* TC1.INTFLAGS bit masks and bit positions */ -+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* AWEX - Timer/Counter Advanced Waveform Extension */ -+/* AWEX.CTRL bit masks and bit positions */ -+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ -+ -+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ -+ -+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ -+ -+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ -+ -+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ -+ -+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ -+ -+/* AWEX.FDCTRL bit masks and bit positions */ -+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ -+ -+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ -+ -+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ -+ -+/* AWEX.STATUS bit masks and bit positions */ -+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ -+ -+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ -+ -+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ -+ -+/* AWEX.STATUSSET bit masks and bit positions */ -+/* AWEX_FDF Predefined. */ -+/* AWEX_FDF Predefined. */ -+ -+/* AWEX_DTHSBUFV Predefined. */ -+/* AWEX_DTHSBUFV Predefined. */ -+ -+/* AWEX_DTLSBUFV Predefined. */ -+/* AWEX_DTLSBUFV Predefined. */ -+ -+/* HIRES - Timer/Counter High-Resolution Extension */ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+/* LCD - LCD Controller */ -+/* LCD.CTRLA bit masks and bit positions */ -+#define LCD_ENABLE_bm 0x80 /* LCD Enable bit mask. */ -+#define LCD_ENABLE_bp 7 /* LCD Enable bit position. */ -+ -+#define LCD_XBIAS_bm 0x40 /* External Register Bias Generation bit mask. */ -+#define LCD_XBIAS_bp 6 /* External Register Bias Generation bit position. */ -+ -+#define LCD_DATCLK_bm 0x20 /* Data Register Lock bit mask. */ -+#define LCD_DATCLK_bp 5 /* Data Register Lock bit position. */ -+ -+#define LCD_COMSWP_bm 0x10 /* Common Bus Swap bit mask. */ -+#define LCD_COMSWP_bp 4 /* Common Bus Swap bit position. */ -+ -+#define LCD_SEGSWP_bm 0x08 /* Segment Bus Swap bit mask. */ -+#define LCD_SEGSWP_bp 3 /* Segment Bus Swap bit position. */ -+ -+#define LCD_CLRDT_bm 0x04 /* Clear Data Register bit mask. */ -+#define LCD_CLRDT_bp 2 /* Clear Data Register bit position. */ -+ -+#define LCD_SEGON_bm 0x02 /* Segments On bit mask. */ -+#define LCD_SEGON_bp 1 /* Segments On bit position. */ -+ -+#define LCD_BLANK_bm 0x01 /* Blanking Display Mode bit mask. */ -+#define LCD_BLANK_bp 0 /* Blanking Display Mode bit position. */ -+ -+/* LCD.CTRLB bit masks and bit positions */ -+#define LCD_PRESC_bm 0x80 /* LCD Prescaler Select bit mask. */ -+#define LCD_PRESC_bp 7 /* LCD Prescaler Select bit position. */ -+ -+#define LCD_CLKDIV_gm 0x70 /* LCD Clock Divide group mask. */ -+#define LCD_CLKDIV_gp 4 /* LCD Clock Divide group position. */ -+#define LCD_CLKDIV0_bm (1<<4) /* LCD Clock Divide bit 0 mask. */ -+#define LCD_CLKDIV0_bp 4 /* LCD Clock Divide bit 0 position. */ -+#define LCD_CLKDIV1_bm (1<<5) /* LCD Clock Divide bit 1 mask. */ -+#define LCD_CLKDIV1_bp 5 /* LCD Clock Divide bit 1 position. */ -+#define LCD_CLKDIV2_bm (1<<6) /* LCD Clock Divide bit 2 mask. */ -+#define LCD_CLKDIV2_bp 6 /* LCD Clock Divide bit 2 position. */ -+ -+#define LCD_LPWAV_bm 0x08 /* Low Power Waveform bit mask. */ -+#define LCD_LPWAV_bp 3 /* Low Power Waveform bit position. */ -+ -+#define LCD_DUTY_gm 0x03 /* Duty Select group mask. */ -+#define LCD_DUTY_gp 0 /* Duty Select group position. */ -+#define LCD_DUTY0_bm (1<<0) /* Duty Select bit 0 mask. */ -+#define LCD_DUTY0_bp 0 /* Duty Select bit 0 position. */ -+#define LCD_DUTY1_bm (1<<1) /* Duty Select bit 1 mask. */ -+#define LCD_DUTY1_bp 1 /* Duty Select bit 1 position. */ -+ -+/* LCD.CTRLC bit masks and bit positions */ -+#define LCD_PMSK_gm 0x3F /* LCD Port Mask group mask. */ -+#define LCD_PMSK_gp 0 /* LCD Port Mask group position. */ -+#define LCD_PMSK0_bm (1<<0) /* LCD Port Mask bit 0 mask. */ -+#define LCD_PMSK0_bp 0 /* LCD Port Mask bit 0 position. */ -+#define LCD_PMSK1_bm (1<<1) /* LCD Port Mask bit 1 mask. */ -+#define LCD_PMSK1_bp 1 /* LCD Port Mask bit 1 position. */ -+#define LCD_PMSK2_bm (1<<2) /* LCD Port Mask bit 2 mask. */ -+#define LCD_PMSK2_bp 2 /* LCD Port Mask bit 2 position. */ -+#define LCD_PMSK3_bm (1<<3) /* LCD Port Mask bit 3 mask. */ -+#define LCD_PMSK3_bp 3 /* LCD Port Mask bit 3 position. */ -+#define LCD_PMSK4_bm (1<<4) /* LCD Port Mask bit 4 mask. */ -+#define LCD_PMSK4_bp 4 /* LCD Port Mask bit 4 position. */ -+#define LCD_PMSK5_bm (1<<5) /* LCD Port Mask bit 5 mask. */ -+#define LCD_PMSK5_bp 5 /* LCD Port Mask bit 5 position. */ -+ -+/* LCD.INTCTRL bit masks and bit positions */ -+#define LCD_XIME_gm 0xF8 /* eXtended Interrupt Mode Enable group mask. */ -+#define LCD_XIME_gp 3 /* eXtended Interrupt Mode Enable group position. */ -+#define LCD_XIME0_bm (1<<3) /* eXtended Interrupt Mode Enable bit 0 mask. */ -+#define LCD_XIME0_bp 3 /* eXtended Interrupt Mode Enable bit 0 position. */ -+#define LCD_XIME1_bm (1<<4) /* eXtended Interrupt Mode Enable bit 1 mask. */ -+#define LCD_XIME1_bp 4 /* eXtended Interrupt Mode Enable bit 1 position. */ -+#define LCD_XIME2_bm (1<<5) /* eXtended Interrupt Mode Enable bit 2 mask. */ -+#define LCD_XIME2_bp 5 /* eXtended Interrupt Mode Enable bit 2 position. */ -+#define LCD_XIME3_bm (1<<6) /* eXtended Interrupt Mode Enable bit 3 mask. */ -+#define LCD_XIME3_bp 6 /* eXtended Interrupt Mode Enable bit 3 position. */ -+#define LCD_XIME4_bm (1<<7) /* eXtended Interrupt Mode Enable bit 4 mask. */ -+#define LCD_XIME4_bp 7 /* eXtended Interrupt Mode Enable bit 4 position. */ -+ -+#define LCD_FCINTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define LCD_FCINTLVL_gp 0 /* Interrupt Level group position. */ -+#define LCD_FCINTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define LCD_FCINTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define LCD_FCINTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define LCD_FCINTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* LCD.INTFLAG bit masks and bit positions */ -+#define LCD_FCIF_bm 0x01 /* LCD Frame Completed Interrupt Flag bit mask. */ -+#define LCD_FCIF_bp 0 /* LCD Frame Completed Interrupt Flag bit position. */ -+ -+/* LCD.CTRLD bit masks and bit positions */ -+#define LCD_BLINKEN_bm 0x08 /* Blink Enable bit mask. */ -+#define LCD_BLINKEN_bp 3 /* Blink Enable bit position. */ -+ -+#define LCD_BLINKRATE_gm 0x03 /* LCD Blink Rate group mask. */ -+#define LCD_BLINKRATE_gp 0 /* LCD Blink Rate group position. */ -+#define LCD_BLINKRATE0_bm (1<<0) /* LCD Blink Rate bit 0 mask. */ -+#define LCD_BLINKRATE0_bp 0 /* LCD Blink Rate bit 0 position. */ -+#define LCD_BLINKRATE1_bm (1<<1) /* LCD Blink Rate bit 1 mask. */ -+#define LCD_BLINKRATE1_bp 1 /* LCD Blink Rate bit 1 position. */ -+ -+/* LCD.CTRLE bit masks and bit positions */ -+#define LCD_BPS1_gm 0xF0 /* Blink Pixel Selection 1 group mask. */ -+#define LCD_BPS1_gp 4 /* Blink Pixel Selection 1 group position. */ -+#define LCD_BPS10_bm (1<<4) /* Blink Pixel Selection 1 bit 0 mask. */ -+#define LCD_BPS10_bp 4 /* Blink Pixel Selection 1 bit 0 position. */ -+#define LCD_BPS11_bm (1<<5) /* Blink Pixel Selection 1 bit 1 mask. */ -+#define LCD_BPS11_bp 5 /* Blink Pixel Selection 1 bit 1 position. */ -+#define LCD_BPS12_bm (1<<6) /* Blink Pixel Selection 1 bit 2 mask. */ -+#define LCD_BPS12_bp 6 /* Blink Pixel Selection 1 bit 2 position. */ -+#define LCD_BPS13_bm (1<<7) /* Blink Pixel Selection 1 bit 3 mask. */ -+#define LCD_BPS13_bp 7 /* Blink Pixel Selection 1 bit 3 position. */ -+ -+#define LCD_BPS0_gm 0x0F /* Blink Pixel Selection 0 group mask. */ -+#define LCD_BPS0_gp 0 /* Blink Pixel Selection 0 group position. */ -+#define LCD_BPS00_bm (1<<0) /* Blink Pixel Selection 0 bit 0 mask. */ -+#define LCD_BPS00_bp 0 /* Blink Pixel Selection 0 bit 0 position. */ -+#define LCD_BPS01_bm (1<<1) /* Blink Pixel Selection 0 bit 1 mask. */ -+#define LCD_BPS01_bp 1 /* Blink Pixel Selection 0 bit 1 position. */ -+#define LCD_BPS02_bm (1<<2) /* Blink Pixel Selection 0 bit 2 mask. */ -+#define LCD_BPS02_bp 2 /* Blink Pixel Selection 0 bit 2 position. */ -+#define LCD_BPS03_bm (1<<3) /* Blink Pixel Selection 0 bit 3 mask. */ -+#define LCD_BPS03_bp 3 /* Blink Pixel Selection 0 bit 3 position. */ -+ -+/* LCD.CTRLF bit masks and bit positions */ -+#define LCD_FCONT_gm 0x3F /* Fine Contrast group mask. */ -+#define LCD_FCONT_gp 0 /* Fine Contrast group position. */ -+#define LCD_FCONT0_bm (1<<0) /* Fine Contrast bit 0 mask. */ -+#define LCD_FCONT0_bp 0 /* Fine Contrast bit 0 position. */ -+#define LCD_FCONT1_bm (1<<1) /* Fine Contrast bit 1 mask. */ -+#define LCD_FCONT1_bp 1 /* Fine Contrast bit 1 position. */ -+#define LCD_FCONT2_bm (1<<2) /* Fine Contrast bit 2 mask. */ -+#define LCD_FCONT2_bp 2 /* Fine Contrast bit 2 position. */ -+#define LCD_FCONT3_bm (1<<3) /* Fine Contrast bit 3 mask. */ -+#define LCD_FCONT3_bp 3 /* Fine Contrast bit 3 position. */ -+#define LCD_FCONT4_bm (1<<4) /* Fine Contrast bit 4 mask. */ -+#define LCD_FCONT4_bp 4 /* Fine Contrast bit 4 position. */ -+#define LCD_FCONT5_bm (1<<5) /* Fine Contrast bit 5 mask. */ -+#define LCD_FCONT5_bp 5 /* Fine Contrast bit 5 position. */ -+ -+/* LCD.CTRLG bit masks and bit positions */ -+#define LCD_TDG_gm 0xC0 /* Type of Digit group mask. */ -+#define LCD_TDG_gp 6 /* Type of Digit group position. */ -+#define LCD_TDG0_bm (1<<6) /* Type of Digit bit 0 mask. */ -+#define LCD_TDG0_bp 6 /* Type of Digit bit 0 position. */ -+#define LCD_TDG1_bm (1<<7) /* Type of Digit bit 1 mask. */ -+#define LCD_TDG1_bp 7 /* Type of Digit bit 1 position. */ -+ -+#define LCD_STSEG_gm 0x3F /* Start Segment group mask. */ -+#define LCD_STSEG_gp 0 /* Start Segment group position. */ -+#define LCD_STSEG0_bm (1<<0) /* Start Segment bit 0 mask. */ -+#define LCD_STSEG0_bp 0 /* Start Segment bit 0 position. */ -+#define LCD_STSEG1_bm (1<<1) /* Start Segment bit 1 mask. */ -+#define LCD_STSEG1_bp 1 /* Start Segment bit 1 position. */ -+#define LCD_STSEG2_bm (1<<2) /* Start Segment bit 2 mask. */ -+#define LCD_STSEG2_bp 2 /* Start Segment bit 2 position. */ -+#define LCD_STSEG3_bm (1<<3) /* Start Segment bit 3 mask. */ -+#define LCD_STSEG3_bp 3 /* Start Segment bit 3 position. */ -+#define LCD_STSEG4_bm (1<<4) /* Start Segment bit 4 mask. */ -+#define LCD_STSEG4_bp 4 /* Start Segment bit 4 position. */ -+#define LCD_STSEG5_bm (1<<5) /* Start Segment bit 5 mask. */ -+#define LCD_STSEG5_bp 5 /* Start Segment bit 5 position. */ -+ -+/* LCD.CTRLH bit masks and bit positions */ -+#define LCD_DEC_bm 0x80 /* Decrement of Start Segment bit mask. */ -+#define LCD_DEC_bp 7 /* Decrement of Start Segment bit position. */ -+ -+#define LCD_DCODE_gm 0x7F /* Display Code group mask. */ -+#define LCD_DCODE_gp 0 /* Display Code group position. */ -+#define LCD_DCODE0_bm (1<<0) /* Display Code bit 0 mask. */ -+#define LCD_DCODE0_bp 0 /* Display Code bit 0 position. */ -+#define LCD_DCODE1_bm (1<<1) /* Display Code bit 1 mask. */ -+#define LCD_DCODE1_bp 1 /* Display Code bit 1 position. */ -+#define LCD_DCODE2_bm (1<<2) /* Display Code bit 2 mask. */ -+#define LCD_DCODE2_bp 2 /* Display Code bit 2 position. */ -+#define LCD_DCODE3_bm (1<<3) /* Display Code bit 3 mask. */ -+#define LCD_DCODE3_bp 3 /* Display Code bit 3 position. */ -+#define LCD_DCODE4_bm (1<<4) /* Display Code bit 4 mask. */ -+#define LCD_DCODE4_bp 4 /* Display Code bit 4 position. */ -+#define LCD_DCODE5_bm (1<<5) /* Display Code bit 5 mask. */ -+#define LCD_DCODE5_bp 5 /* Display Code bit 5 position. */ -+#define LCD_DCODE6_bm (1<<6) /* Display Code bit 6 mask. */ -+#define LCD_DCODE6_bp 6 /* Display Code bit 6 position. */ -+ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ -+#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ -+#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ -+#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ -+#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ -+#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ -+#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ -+#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ -+#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ -+#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ -+#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ -+#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ -+#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ -+#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ -+#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ -+#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ -+#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ -+#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ -+#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ -+ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -+#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ -+#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* LOCKBIT - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT0_vect_num 2 -+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -+#define PORTC_INT1_vect_num 3 -+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT0_vect_num 4 -+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -+#define PORTR_INT1_vect_num 5 -+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ -+ -+/* DMA interrupt vectors */ -+#define DMA_CH0_vect_num 6 -+#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ -+#define DMA_CH1_vect_num 7 -+#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ -+ -+/* RTC interrupt vectors */ -+#define RTC_OVF_vect_num 10 -+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -+#define RTC_COMP_vect_num 11 -+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 12 -+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 13 -+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_OVF_vect_num 14 -+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -+#define TCC0_ERR_vect_num 15 -+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -+#define TCC0_CCA_vect_num 16 -+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -+#define TCC0_CCB_vect_num 17 -+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -+#define TCC0_CCC_vect_num 18 -+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -+#define TCC0_CCD_vect_num 19 -+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ -+ -+/* TCC1 interrupt vectors */ -+#define TCC1_OVF_vect_num 20 -+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -+#define TCC1_ERR_vect_num 21 -+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -+#define TCC1_CCA_vect_num 22 -+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -+#define TCC1_CCB_vect_num 23 -+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 24 -+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 25 -+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 26 -+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 27 -+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ -+ -+/* USB interrupt vectors */ -+#define USB_BUSEVENT_vect_num 31 -+#define USB_BUSEVENT_vect _VECTOR(31) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -+#define USB_TRNCOMPL_vect_num 32 -+#define USB_TRNCOMPL_vect _VECTOR(32) /* Transaction complete interrupt */ -+ -+/* LCD interrupt vectors */ -+#define LCD_INT_vect_num 35 -+#define LCD_INT_vect _VECTOR(35) /* LCD Interrupt */ -+ -+/* AES interrupt vectors */ -+#define AES_INT_vect_num 36 -+#define AES_INT_vect _VECTOR(36) /* AES Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 37 -+#define NVM_EE_vect _VECTOR(37) /* EE Interrupt */ -+#define NVM_SPM_vect_num 38 -+#define NVM_SPM_vect _VECTOR(38) /* SPM Interrupt */ -+ -+/* PORTB interrupt vectors */ -+#define PORTB_INT0_vect_num 39 -+#define PORTB_INT0_vect _VECTOR(39) /* External Interrupt 0 */ -+#define PORTB_INT1_vect_num 40 -+#define PORTB_INT1_vect _VECTOR(40) /* External Interrupt 1 */ -+ -+/* ACB interrupt vectors */ -+#define ACB_AC0_vect_num 41 -+#define ACB_AC0_vect _VECTOR(41) /* AC0 Interrupt */ -+#define ACB_AC1_vect_num 42 -+#define ACB_AC1_vect _VECTOR(42) /* AC1 Interrupt */ -+#define ACB_ACW_vect_num 43 -+#define ACB_ACW_vect _VECTOR(43) /* ACW Window Mode Interrupt */ -+ -+/* ADCB interrupt vectors */ -+#define ADCB_CH0_vect_num 44 -+#define ADCB_CH0_vect _VECTOR(44) /* Interrupt 0 */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT0_vect_num 48 -+#define PORTD_INT0_vect _VECTOR(48) /* External Interrupt 0 */ -+#define PORTD_INT1_vect_num 49 -+#define PORTD_INT1_vect _VECTOR(49) /* External Interrupt 1 */ -+ -+/* PORTG interrupt vectors */ -+#define PORTG_INT0_vect_num 50 -+#define PORTG_INT0_vect _VECTOR(50) /* External Interrupt 0 */ -+#define PORTG_INT1_vect_num 51 -+#define PORTG_INT1_vect _VECTOR(51) /* External Interrupt 1 */ -+ -+/* PORTM interrupt vectors */ -+#define PORTM_INT0_vect_num 52 -+#define PORTM_INT0_vect _VECTOR(52) /* External Interrupt 0 */ -+#define PORTM_INT1_vect_num 53 -+#define PORTM_INT1_vect _VECTOR(53) /* External Interrupt 1 */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (54 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (69632) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (65536) -+#define APP_SECTION_PAGE_SIZE (256) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0xF000) -+#define APPTABLE_SECTION_SIZE (4096) -+#define APPTABLE_SECTION_PAGE_SIZE (256) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x10000) -+#define BOOT_SECTION_SIZE (4096) -+#define BOOT_SECTION_PAGE_SIZE (256) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (12288) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (2048) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (4096) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (2048) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (6) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (256) -+#define USER_SIGNATURES_PAGE_SIZE (256) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (52) -+#define PROD_SIGNATURES_PAGE_SIZE (256) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 256 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 6 -+ -+/* Fuse Byte 0 */ -+#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ -+#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ -+#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ -+#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ -+#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ -+#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ -+#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ -+#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ -+#define FUSE0_DEFAULT (0xFF) -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x96 -+#define SIGNATURE_2 0x51 -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA64B3_H_INCLUDED */ -+ -diff --git a/include/avr/iox64c3.h b/include/avr/iox64c3.h -new file mode 100644 -index 0000000..7454246 ---- /dev/null -+++ b/include/avr/iox64c3.h -@@ -0,0 +1,6216 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox64c3.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA64C3_H_INCLUDED -+#define _AVR_ATXMEGA64C3_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+VPORT - Virtual Ports -+-------------------------------------------------------------------------- -+*/ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t USBCTRL; /* USB Control Register */ -+} CLK_t; -+ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t reserved_0x02; -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t PRPD; /* Power Reduction Port D */ -+ register8_t PRPE; /* Power Reduction Port E */ -+ register8_t PRPF; /* Power Reduction Port F */ -+} PR_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+/* USB Prescaler Division Factor */ -+typedef enum CLK_USBPSDIV_enum -+{ -+ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ -+ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ -+ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ -+ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ -+ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ -+ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ -+} CLK_USBPSDIV_t; -+ -+/* USB Clock Source */ -+typedef enum CLK_USBSRC_enum -+{ -+ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ -+ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ -+} CLK_USBSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control Register */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+/* 2 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC2MCREF_enum -+{ -+ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC2MCREF_t; -+ -+/* 32 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC32MCREF_enum -+{ -+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ -+} OSC_RC32MCREF_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t ANAINIT; /* Analog Startup Delay */ -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t AWEXLOCK; /* AWEX Lock */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORTCFG - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t VPCTRLA; /* Virtual Port Control Register A */ -+ register8_t VPCTRLB; /* Virtual Port Control Register B */ -+ register8_t CLKEVOUT; /* Clock and Event Out Register */ -+ register8_t reserved_0x05; -+ register8_t EVOUTSEL; /* Event Output Select */ -+} PORTCFG_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP02MAP_enum -+{ -+ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ -+ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ -+ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ -+ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ -+ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ -+ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ -+ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ -+ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ -+ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ -+ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ -+ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ -+ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ -+ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ -+ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ -+ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ -+ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -+} PORTCFG_VP02MAP_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP13MAP_enum -+{ -+ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ -+ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ -+ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ -+ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ -+ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ -+ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ -+ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ -+ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ -+ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ -+ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ -+ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ -+ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ -+ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ -+ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ -+ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ -+ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -+} PORTCFG_VP13MAP_t; -+ -+/* System Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ -+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ -+ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -+} PORTCFG_CLKOUT_t; -+ -+/* Peripheral Clock Output Select */ -+typedef enum PORTCFG_CLKOUTSEL_enum -+{ -+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -+} PORTCFG_CLKOUTSEL_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ -+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ -+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -+} PORTCFG_EVOUT_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+} EVSYS_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ -+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ -+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ -+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ -+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ -+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ -+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ -+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ -+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ -+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ -+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ -+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ -+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ -+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ -+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ -+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ -+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ -+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ -+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ -+ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ -+ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ -+ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ -+ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ -+ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ -+ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ -+ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ -+ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ -+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ -+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ -+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ -+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ -+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ -+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ -+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ -+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ -+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ -+ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ -+ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ -+ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ -+ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ -+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ -+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ -+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ -+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ -+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -+ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ -+ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ -+ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ -+ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ -+ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -+} EVSYS_CHMUX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ -+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ -+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ -+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ -+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} NVM_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t reserved_0x07; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+} ADC_t; -+ -+/* Current Limitation */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -+} ADC_CURRLIMIT_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+} ADC_CH_MUXNEG_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ -+ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ -+ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ -+ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC - Real-Time Counter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Real-Time Counter */ -+typedef struct RTC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary register */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ _WORDREGISTER(CNT); /* Count Register */ -+ _WORDREGISTER(PER); /* Period Register */ -+ _WORDREGISTER(COMP); /* Compare Register */ -+} RTC_t; -+ -+/* Prescaler Factor */ -+typedef enum RTC_PRESCALER_enum -+{ -+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ -+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ -+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ -+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ -+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ -+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ -+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ -+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -+} RTC_PRESCALER_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC_COMPINTLVL_enum -+{ -+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC_OVFINTLVL_enum -+{ -+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+} TWI_t; -+ -+/* SDA Hold Time */ -+typedef enum TWI_SDAHOLD_enum -+{ -+ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ -+ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ -+ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ -+ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -+} TWI_SDAHOLD_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USB - USB -+-------------------------------------------------------------------------- -+*/ -+ -+/* USB Endpoint */ -+typedef struct USB_EP_struct -+{ -+ register8_t STATUS; /* Endpoint Status */ -+ register8_t CTRL; /* Endpoint Control */ -+ _WORDREGISTER(CNT); /* USB Endpoint Counter */ -+ _WORDREGISTER(DATAPTR); /* Data Pointer */ -+ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ -+} USB_EP_t; -+ -+ -+/* Universal Serial Bus */ -+typedef struct USB_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t FIFOWP; /* FIFO Write Pointer Register */ -+ register8_t FIFORP; /* FIFO Read Pointer Register */ -+ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ -+ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ -+ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ -+ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t reserved_0x20; -+ register8_t reserved_0x21; -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t CAL0; /* Calibration Byte 0 */ -+ register8_t CAL1; /* Calibration Byte 1 */ -+} USB_t; -+ -+ -+/* USB Endpoint Table */ -+typedef struct USB_EP_TABLE_struct -+{ -+ USB_EP_t EP0OUT; /* Endpoint 0 */ -+ USB_EP_t EP0IN; /* Endpoint 0 */ -+ USB_EP_t EP1OUT; /* Endpoint 1 */ -+ USB_EP_t EP1IN; /* Endpoint 1 */ -+ USB_EP_t EP2OUT; /* Endpoint 2 */ -+ USB_EP_t EP2IN; /* Endpoint 2 */ -+ USB_EP_t EP3OUT; /* Endpoint 3 */ -+ USB_EP_t EP3IN; /* Endpoint 3 */ -+ USB_EP_t EP4OUT; /* Endpoint 4 */ -+ USB_EP_t EP4IN; /* Endpoint 4 */ -+ USB_EP_t EP5OUT; /* Endpoint 5 */ -+ USB_EP_t EP5IN; /* Endpoint 5 */ -+ USB_EP_t EP6OUT; /* Endpoint 6 */ -+ USB_EP_t EP6IN; /* Endpoint 6 */ -+ USB_EP_t EP7OUT; /* Endpoint 7 */ -+ USB_EP_t EP7IN; /* Endpoint 7 */ -+ USB_EP_t EP8OUT; /* Endpoint 8 */ -+ USB_EP_t EP8IN; /* Endpoint 8 */ -+ USB_EP_t EP9OUT; /* Endpoint 9 */ -+ USB_EP_t EP9IN; /* Endpoint 9 */ -+ USB_EP_t EP10OUT; /* Endpoint 10 */ -+ USB_EP_t EP10IN; /* Endpoint 10 */ -+ USB_EP_t EP11OUT; /* Endpoint 11 */ -+ USB_EP_t EP11IN; /* Endpoint 11 */ -+ USB_EP_t EP12OUT; /* Endpoint 12 */ -+ USB_EP_t EP12IN; /* Endpoint 12 */ -+ USB_EP_t EP13OUT; /* Endpoint 13 */ -+ USB_EP_t EP13IN; /* Endpoint 13 */ -+ USB_EP_t EP14OUT; /* Endpoint 14 */ -+ USB_EP_t EP14IN; /* Endpoint 14 */ -+ USB_EP_t EP15OUT; /* Endpoint 15 */ -+ USB_EP_t EP15IN; /* Endpoint 15 */ -+ register8_t reserved_0x100; -+ register8_t reserved_0x101; -+ register8_t reserved_0x102; -+ register8_t reserved_0x103; -+ register8_t reserved_0x104; -+ register8_t reserved_0x105; -+ register8_t reserved_0x106; -+ register8_t reserved_0x107; -+ register8_t reserved_0x108; -+ register8_t reserved_0x109; -+ register8_t reserved_0x10A; -+ register8_t reserved_0x10B; -+ register8_t reserved_0x10C; -+ register8_t reserved_0x10D; -+ register8_t reserved_0x10E; -+ register8_t reserved_0x10F; -+ register8_t FRAMENUML; /* Frame Number Low Byte */ -+ register8_t FRAMENUMH; /* Frame Number High Byte */ -+} USB_EP_TABLE_t; -+ -+/* Interrupt level */ -+typedef enum USB_INTLVL_enum -+{ -+ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} USB_INTLVL_t; -+ -+/* USB Endpoint Type */ -+typedef enum USB_EP_TYPE_enum -+{ -+ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ -+ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ -+ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ -+ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ -+} USB_EP_TYPE_t; -+ -+/* USB Endpoint Buffersize */ -+typedef enum USB_EP_BUFSIZE_enum -+{ -+ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ -+ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ -+ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ -+ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ -+ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ -+ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ -+ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ -+ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ -+} USB_EP_BUFSIZE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - I/O Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INT0MASK; /* Port Interrupt 0 Mask */ -+ register8_t INT1MASK; /* Port Interrupt 1 Mask */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t REMAP; /* I/O Port Pin Remap Register */ -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Port Interrupt 0 Level */ -+typedef enum PORT_INT0LVL_enum -+{ -+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INT0LVL_t; -+ -+/* Port Interrupt 1 Level */ -+typedef enum PORT_INT1LVL_enum -+{ -+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ -+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ -+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -+} PORT_INT1LVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 0 */ -+typedef struct TC0_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC0_t; -+ -+ -+/* 16-bit Timer/Counter 1 */ -+typedef struct TC1_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+} TC1_t; -+ -+/* Clock Selection */ -+typedef enum TC_CLKSEL_enum -+{ -+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_CLKSEL_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC_WGMODE_enum -+{ -+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC_WGMODE_t; -+ -+/* Byte Mode */ -+typedef enum TC_BYTEM_enum -+{ -+ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ -+ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -+} TC_BYTEM_t; -+ -+/* Event Action */ -+typedef enum TC_EVACT_enum -+{ -+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ -+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ -+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ -+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ -+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ -+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC_EVSEL_enum -+{ -+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_EVSEL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC_ERRINTLVL_enum -+{ -+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC_OVFINTLVL_enum -+{ -+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_OVFINTLVL_t; -+ -+/* Compare or Capture D Interrupt Level */ -+typedef enum TC_CCDINTLVL_enum -+{ -+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC_CCDINTLVL_t; -+ -+/* Compare or Capture C Interrupt Level */ -+typedef enum TC_CCCINTLVL_enum -+{ -+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC_CCCINTLVL_t; -+ -+/* Compare or Capture B Interrupt Level */ -+typedef enum TC_CCBINTLVL_enum -+{ -+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_CCBINTLVL_t; -+ -+/* Compare or Capture A Interrupt Level */ -+typedef enum TC_CCAINTLVL_enum -+{ -+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_CCAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC_CMD_enum -+{ -+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC2 - 16-bit Timer/Counter type 2 -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter type 2 */ -+typedef struct TC2_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t reserved_0x03; -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t reserved_0x08; -+ register8_t CTRLF; /* Control Register F */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t LCNT; /* Low Byte Count */ -+ register8_t HCNT; /* High Byte Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t LPER; /* Low Byte Period */ -+ register8_t HPER; /* High Byte Period */ -+ register8_t LCMPA; /* Low Byte Compare A */ -+ register8_t HCMPA; /* High Byte Compare A */ -+ register8_t LCMPB; /* Low Byte Compare B */ -+ register8_t HCMPB; /* High Byte Compare B */ -+ register8_t LCMPC; /* Low Byte Compare C */ -+ register8_t HCMPC; /* High Byte Compare C */ -+ register8_t LCMPD; /* Low Byte Compare D */ -+ register8_t HCMPD; /* High Byte Compare D */ -+} TC2_t; -+ -+/* Clock Selection */ -+typedef enum TC2_CLKSEL_enum -+{ -+ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC2_CLKSEL_t; -+ -+/* Byte Mode */ -+typedef enum TC2_BYTEM_enum -+{ -+ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ -+ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -+} TC2_BYTEM_t; -+ -+/* High Byte Underflow Interrupt Level */ -+typedef enum TC2_HUNFINTLVL_enum -+{ -+ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_HUNFINTLVL_t; -+ -+/* Low Byte Underflow Interrupt Level */ -+typedef enum TC2_LUNFINTLVL_enum -+{ -+ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LUNFINTLVL_t; -+ -+/* Low Byte Compare D Interrupt Level */ -+typedef enum TC2_LCMPDINTLVL_enum -+{ -+ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC2_LCMPDINTLVL_t; -+ -+/* Low Byte Compare C Interrupt Level */ -+typedef enum TC2_LCMPCINTLVL_enum -+{ -+ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC2_LCMPCINTLVL_t; -+ -+/* Low Byte Compare B Interrupt Level */ -+typedef enum TC2_LCMPBINTLVL_enum -+{ -+ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_LCMPBINTLVL_t; -+ -+/* Low Byte Compare A Interrupt Level */ -+typedef enum TC2_LCMPAINTLVL_enum -+{ -+ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LCMPAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMD_enum -+{ -+ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC2_CMD_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMDEN_enum -+{ -+ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ -+ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ -+ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -+} TC2_CMDEN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AWEX - Timer/Counter Advanced Waveform Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Advanced Waveform Extension */ -+typedef struct AWEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t FDEMASK; /* Fault Detection Event Mask */ -+ register8_t FDCTRL; /* Fault Detection Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t STATUSSET; /* Status Set Register */ -+ register8_t DTBOTH; /* Dead Time Both Sides */ -+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ -+ register8_t DTLS; /* Dead Time Low Side */ -+ register8_t DTHS; /* Dead Time High Side */ -+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ -+ register8_t DTHSBUF; /* Dead Time High Side Buffer */ -+ register8_t OUTOVEN; /* Output Override Enable */ -+} AWEX_t; -+ -+/* Fault Detect Action */ -+typedef enum AWEX_FDACT_enum -+{ -+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ -+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -+} AWEX_FDACT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+HIRES - Timer/Counter High-Resolution Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register */ -+} HIRES_t; -+ -+/* High Resolution Enable */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ -+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+} IRDA_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t reserved_0x00; -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+} NVM_FUSES_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* Timer Oscillator pin location */ -+typedef enum TOSCSEL_enum -+{ -+ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ -+ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -+} TOSCSEL_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -+} BOD_t; -+ -+/* BOD operation */ -+typedef enum BODACT_enum -+{ -+ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BODACT_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WDP_enum -+{ -+ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ -+ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ -+ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ -+ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ -+ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ -+ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ -+ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ -+ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ -+ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ -+ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ -+ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -+} WDP_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LOCKBIT - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ -+ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t USBCAL0; /* USB Calibration Byte 0 */ -+ register8_t USBCAL1; /* USB Calibration Byte 1 */ -+ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ -+ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+} NVM_PROD_SIGNATURES_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -+#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -+#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -+#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -+#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -+#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -+#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -+#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ -+#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ -+#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) -+#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) -+#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) -+#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+#define CLK_USBCTRL _SFR_MEM8(0x0044) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* DFLL - DFLL */ -+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -+#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -+#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPD _SFR_MEM8(0x0074) -+#define PR_PRPE _SFR_MEM8(0x0075) -+#define PR_PRPF _SFR_MEM8(0x0076) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_ANAINIT _SFR_MEM8(0x0097) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_AWEXLOCK _SFR_MEM8(0x0099) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCA_CTRLA _SFR_MEM8(0x0200) -+#define ADCA_CTRLB _SFR_MEM8(0x0201) -+#define ADCA_REFCTRL _SFR_MEM8(0x0202) -+#define ADCA_EVCTRL _SFR_MEM8(0x0203) -+#define ADCA_PRESCALER _SFR_MEM8(0x0204) -+#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -+#define ADCA_TEMP _SFR_MEM8(0x0207) -+#define ADCA_CAL _SFR_MEM16(0x020C) -+#define ADCA_CH0RES _SFR_MEM16(0x0210) -+#define ADCA_CMP _SFR_MEM16(0x0218) -+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -+#define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -+ -+/* AC - Analog Comparator */ -+#define ACA_AC0CTRL _SFR_MEM8(0x0380) -+#define ACA_AC1CTRL _SFR_MEM8(0x0381) -+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -+#define ACA_CTRLA _SFR_MEM8(0x0384) -+#define ACA_CTRLB _SFR_MEM8(0x0385) -+#define ACA_WINCTRL _SFR_MEM8(0x0386) -+#define ACA_STATUS _SFR_MEM8(0x0387) -+ -+/* RTC - Real-Time Counter */ -+#define RTC_CTRL _SFR_MEM8(0x0400) -+#define RTC_STATUS _SFR_MEM8(0x0401) -+#define RTC_INTCTRL _SFR_MEM8(0x0402) -+#define RTC_INTFLAGS _SFR_MEM8(0x0403) -+#define RTC_TEMP _SFR_MEM8(0x0404) -+#define RTC_CNT _SFR_MEM16(0x0408) -+#define RTC_PER _SFR_MEM16(0x040A) -+#define RTC_COMP _SFR_MEM16(0x040C) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIE_CTRL _SFR_MEM8(0x04A0) -+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -+ -+/* USB - Universal Serial Bus */ -+#define USB_CTRLA _SFR_MEM8(0x04C0) -+#define USB_CTRLB _SFR_MEM8(0x04C1) -+#define USB_STATUS _SFR_MEM8(0x04C2) -+#define USB_ADDR _SFR_MEM8(0x04C3) -+#define USB_FIFOWP _SFR_MEM8(0x04C4) -+#define USB_FIFORP _SFR_MEM8(0x04C5) -+#define USB_EPPTR _SFR_MEM16(0x04C6) -+#define USB_INTCTRLA _SFR_MEM8(0x04C8) -+#define USB_INTCTRLB _SFR_MEM8(0x04C9) -+#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) -+#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) -+#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) -+#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) -+#define USB_CAL0 _SFR_MEM8(0x04FA) -+#define USB_CAL1 _SFR_MEM8(0x04FB) -+ -+/* PORT - I/O Ports */ -+#define PORTA_DIR _SFR_MEM8(0x0600) -+#define PORTA_DIRSET _SFR_MEM8(0x0601) -+#define PORTA_DIRCLR _SFR_MEM8(0x0602) -+#define PORTA_DIRTGL _SFR_MEM8(0x0603) -+#define PORTA_OUT _SFR_MEM8(0x0604) -+#define PORTA_OUTSET _SFR_MEM8(0x0605) -+#define PORTA_OUTCLR _SFR_MEM8(0x0606) -+#define PORTA_OUTTGL _SFR_MEM8(0x0607) -+#define PORTA_IN _SFR_MEM8(0x0608) -+#define PORTA_INTCTRL _SFR_MEM8(0x0609) -+#define PORTA_INT0MASK _SFR_MEM8(0x060A) -+#define PORTA_INT1MASK _SFR_MEM8(0x060B) -+#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_REMAP _SFR_MEM8(0x060E) -+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -+ -+/* PORT - I/O Ports */ -+#define PORTB_DIR _SFR_MEM8(0x0620) -+#define PORTB_DIRSET _SFR_MEM8(0x0621) -+#define PORTB_DIRCLR _SFR_MEM8(0x0622) -+#define PORTB_DIRTGL _SFR_MEM8(0x0623) -+#define PORTB_OUT _SFR_MEM8(0x0624) -+#define PORTB_OUTSET _SFR_MEM8(0x0625) -+#define PORTB_OUTCLR _SFR_MEM8(0x0626) -+#define PORTB_OUTTGL _SFR_MEM8(0x0627) -+#define PORTB_IN _SFR_MEM8(0x0628) -+#define PORTB_INTCTRL _SFR_MEM8(0x0629) -+#define PORTB_INT0MASK _SFR_MEM8(0x062A) -+#define PORTB_INT1MASK _SFR_MEM8(0x062B) -+#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -+#define PORTB_REMAP _SFR_MEM8(0x062E) -+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INT0MASK _SFR_MEM8(0x064A) -+#define PORTC_INT1MASK _SFR_MEM8(0x064B) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INT0MASK _SFR_MEM8(0x066A) -+#define PORTD_INT1MASK _SFR_MEM8(0x066B) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTE_DIR _SFR_MEM8(0x0680) -+#define PORTE_DIRSET _SFR_MEM8(0x0681) -+#define PORTE_DIRCLR _SFR_MEM8(0x0682) -+#define PORTE_DIRTGL _SFR_MEM8(0x0683) -+#define PORTE_OUT _SFR_MEM8(0x0684) -+#define PORTE_OUTSET _SFR_MEM8(0x0685) -+#define PORTE_OUTCLR _SFR_MEM8(0x0686) -+#define PORTE_OUTTGL _SFR_MEM8(0x0687) -+#define PORTE_IN _SFR_MEM8(0x0688) -+#define PORTE_INTCTRL _SFR_MEM8(0x0689) -+#define PORTE_INT0MASK _SFR_MEM8(0x068A) -+#define PORTE_INT1MASK _SFR_MEM8(0x068B) -+#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -+#define PORTE_REMAP _SFR_MEM8(0x068E) -+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) -+ -+/* PORT - I/O Ports */ -+#define PORTF_DIR _SFR_MEM8(0x06A0) -+#define PORTF_DIRSET _SFR_MEM8(0x06A1) -+#define PORTF_DIRCLR _SFR_MEM8(0x06A2) -+#define PORTF_DIRTGL _SFR_MEM8(0x06A3) -+#define PORTF_OUT _SFR_MEM8(0x06A4) -+#define PORTF_OUTSET _SFR_MEM8(0x06A5) -+#define PORTF_OUTCLR _SFR_MEM8(0x06A6) -+#define PORTF_OUTTGL _SFR_MEM8(0x06A7) -+#define PORTF_IN _SFR_MEM8(0x06A8) -+#define PORTF_INTCTRL _SFR_MEM8(0x06A9) -+#define PORTF_INT0MASK _SFR_MEM8(0x06AA) -+#define PORTF_INT1MASK _SFR_MEM8(0x06AB) -+#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) -+#define PORTF_REMAP _SFR_MEM8(0x06AE) -+#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) -+#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) -+#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) -+#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) -+#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) -+#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) -+#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) -+#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -+#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCC0_CTRLA _SFR_MEM8(0x0800) -+#define TCC0_CTRLB _SFR_MEM8(0x0801) -+#define TCC0_CTRLC _SFR_MEM8(0x0802) -+#define TCC0_CTRLD _SFR_MEM8(0x0803) -+#define TCC0_CTRLE _SFR_MEM8(0x0804) -+#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -+#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -+#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -+#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC0_TEMP _SFR_MEM8(0x080F) -+#define TCC0_CNT _SFR_MEM16(0x0820) -+#define TCC0_PER _SFR_MEM16(0x0826) -+#define TCC0_CCA _SFR_MEM16(0x0828) -+#define TCC0_CCB _SFR_MEM16(0x082A) -+#define TCC0_CCC _SFR_MEM16(0x082C) -+#define TCC0_CCD _SFR_MEM16(0x082E) -+#define TCC0_PERBUF _SFR_MEM16(0x0836) -+#define TCC0_CCABUF _SFR_MEM16(0x0838) -+#define TCC0_CCBBUF _SFR_MEM16(0x083A) -+#define TCC0_CCCBUF _SFR_MEM16(0x083C) -+#define TCC0_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCC2_CTRLA _SFR_MEM8(0x0800) -+#define TCC2_CTRLB _SFR_MEM8(0x0801) -+#define TCC2_CTRLC _SFR_MEM8(0x0802) -+#define TCC2_CTRLE _SFR_MEM8(0x0804) -+#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC2_CTRLF _SFR_MEM8(0x0809) -+#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC2_LCNT _SFR_MEM8(0x0820) -+#define TCC2_HCNT _SFR_MEM8(0x0821) -+#define TCC2_LPER _SFR_MEM8(0x0826) -+#define TCC2_HPER _SFR_MEM8(0x0827) -+#define TCC2_LCMPA _SFR_MEM8(0x0828) -+#define TCC2_HCMPA _SFR_MEM8(0x0829) -+#define TCC2_LCMPB _SFR_MEM8(0x082A) -+#define TCC2_HCMPB _SFR_MEM8(0x082B) -+#define TCC2_LCMPC _SFR_MEM8(0x082C) -+#define TCC2_HCMPC _SFR_MEM8(0x082D) -+#define TCC2_LCMPD _SFR_MEM8(0x082E) -+#define TCC2_HCMPD _SFR_MEM8(0x082F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCC1_CTRLA _SFR_MEM8(0x0840) -+#define TCC1_CTRLB _SFR_MEM8(0x0841) -+#define TCC1_CTRLC _SFR_MEM8(0x0842) -+#define TCC1_CTRLD _SFR_MEM8(0x0843) -+#define TCC1_CTRLE _SFR_MEM8(0x0844) -+#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -+#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -+#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -+#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC1_TEMP _SFR_MEM8(0x084F) -+#define TCC1_CNT _SFR_MEM16(0x0860) -+#define TCC1_PER _SFR_MEM16(0x0866) -+#define TCC1_CCA _SFR_MEM16(0x0868) -+#define TCC1_CCB _SFR_MEM16(0x086A) -+#define TCC1_PERBUF _SFR_MEM16(0x0876) -+#define TCC1_CCABUF _SFR_MEM16(0x0878) -+#define TCC1_CCBBUF _SFR_MEM16(0x087A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXC_CTRL _SFR_MEM8(0x0880) -+#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -+#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -+#define AWEXC_STATUS _SFR_MEM8(0x0884) -+#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -+#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -+#define AWEXC_DTLS _SFR_MEM8(0x0888) -+#define AWEXC_DTHS _SFR_MEM8(0x0889) -+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x0890) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08A0) -+#define USARTC0_STATUS _SFR_MEM8(0x08A1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -+#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -+#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIC_CTRL _SFR_MEM8(0x08C0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -+#define SPIC_STATUS _SFR_MEM8(0x08C2) -+#define SPIC_DATA _SFR_MEM8(0x08C3) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCD0_CTRLA _SFR_MEM8(0x0900) -+#define TCD0_CTRLB _SFR_MEM8(0x0901) -+#define TCD0_CTRLC _SFR_MEM8(0x0902) -+#define TCD0_CTRLD _SFR_MEM8(0x0903) -+#define TCD0_CTRLE _SFR_MEM8(0x0904) -+#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -+#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -+#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -+#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -+#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD0_TEMP _SFR_MEM8(0x090F) -+#define TCD0_CNT _SFR_MEM16(0x0920) -+#define TCD0_PER _SFR_MEM16(0x0926) -+#define TCD0_CCA _SFR_MEM16(0x0928) -+#define TCD0_CCB _SFR_MEM16(0x092A) -+#define TCD0_CCC _SFR_MEM16(0x092C) -+#define TCD0_CCD _SFR_MEM16(0x092E) -+#define TCD0_PERBUF _SFR_MEM16(0x0936) -+#define TCD0_CCABUF _SFR_MEM16(0x0938) -+#define TCD0_CCBBUF _SFR_MEM16(0x093A) -+#define TCD0_CCCBUF _SFR_MEM16(0x093C) -+#define TCD0_CCDBUF _SFR_MEM16(0x093E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCD2_CTRLA _SFR_MEM8(0x0900) -+#define TCD2_CTRLB _SFR_MEM8(0x0901) -+#define TCD2_CTRLC _SFR_MEM8(0x0902) -+#define TCD2_CTRLE _SFR_MEM8(0x0904) -+#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD2_CTRLF _SFR_MEM8(0x0909) -+#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD2_LCNT _SFR_MEM8(0x0920) -+#define TCD2_HCNT _SFR_MEM8(0x0921) -+#define TCD2_LPER _SFR_MEM8(0x0926) -+#define TCD2_HPER _SFR_MEM8(0x0927) -+#define TCD2_LCMPA _SFR_MEM8(0x0928) -+#define TCD2_HCMPA _SFR_MEM8(0x0929) -+#define TCD2_LCMPB _SFR_MEM8(0x092A) -+#define TCD2_HCMPB _SFR_MEM8(0x092B) -+#define TCD2_LCMPC _SFR_MEM8(0x092C) -+#define TCD2_HCMPC _SFR_MEM8(0x092D) -+#define TCD2_LCMPD _SFR_MEM8(0x092E) -+#define TCD2_HCMPD _SFR_MEM8(0x092F) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD0_DATA _SFR_MEM8(0x09A0) -+#define USARTD0_STATUS _SFR_MEM8(0x09A1) -+#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -+#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -+#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPID_CTRL _SFR_MEM8(0x09C0) -+#define SPID_INTCTRL _SFR_MEM8(0x09C1) -+#define SPID_STATUS _SFR_MEM8(0x09C2) -+#define SPID_DATA _SFR_MEM8(0x09C3) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCE0_CTRLA _SFR_MEM8(0x0A00) -+#define TCE0_CTRLB _SFR_MEM8(0x0A01) -+#define TCE0_CTRLC _SFR_MEM8(0x0A02) -+#define TCE0_CTRLD _SFR_MEM8(0x0A03) -+#define TCE0_CTRLE _SFR_MEM8(0x0A04) -+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE0_TEMP _SFR_MEM8(0x0A0F) -+#define TCE0_CNT _SFR_MEM16(0x0A20) -+#define TCE0_PER _SFR_MEM16(0x0A26) -+#define TCE0_CCA _SFR_MEM16(0x0A28) -+#define TCE0_CCB _SFR_MEM16(0x0A2A) -+#define TCE0_CCC _SFR_MEM16(0x0A2C) -+#define TCE0_CCD _SFR_MEM16(0x0A2E) -+#define TCE0_PERBUF _SFR_MEM16(0x0A36) -+#define TCE0_CCABUF _SFR_MEM16(0x0A38) -+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCE2_CTRLA _SFR_MEM8(0x0A00) -+#define TCE2_CTRLB _SFR_MEM8(0x0A01) -+#define TCE2_CTRLC _SFR_MEM8(0x0A02) -+#define TCE2_CTRLE _SFR_MEM8(0x0A04) -+#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE2_CTRLF _SFR_MEM8(0x0A09) -+#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE2_LCNT _SFR_MEM8(0x0A20) -+#define TCE2_HCNT _SFR_MEM8(0x0A21) -+#define TCE2_LPER _SFR_MEM8(0x0A26) -+#define TCE2_HPER _SFR_MEM8(0x0A27) -+#define TCE2_LCMPA _SFR_MEM8(0x0A28) -+#define TCE2_HCMPA _SFR_MEM8(0x0A29) -+#define TCE2_LCMPB _SFR_MEM8(0x0A2A) -+#define TCE2_HCMPB _SFR_MEM8(0x0A2B) -+#define TCE2_LCMPC _SFR_MEM8(0x0A2C) -+#define TCE2_HCMPC _SFR_MEM8(0x0A2D) -+#define TCE2_LCMPD _SFR_MEM8(0x0A2E) -+#define TCE2_HCMPD _SFR_MEM8(0x0A2F) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTE0_DATA _SFR_MEM8(0x0AA0) -+#define USARTE0_STATUS _SFR_MEM8(0x0AA1) -+#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) -+#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) -+#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) -+#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) -+#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCF0_CTRLA _SFR_MEM8(0x0B00) -+#define TCF0_CTRLB _SFR_MEM8(0x0B01) -+#define TCF0_CTRLC _SFR_MEM8(0x0B02) -+#define TCF0_CTRLD _SFR_MEM8(0x0B03) -+#define TCF0_CTRLE _SFR_MEM8(0x0B04) -+#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) -+#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) -+#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) -+#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) -+#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) -+#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) -+#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) -+#define TCF0_TEMP _SFR_MEM8(0x0B0F) -+#define TCF0_CNT _SFR_MEM16(0x0B20) -+#define TCF0_PER _SFR_MEM16(0x0B26) -+#define TCF0_CCA _SFR_MEM16(0x0B28) -+#define TCF0_CCB _SFR_MEM16(0x0B2A) -+#define TCF0_CCC _SFR_MEM16(0x0B2C) -+#define TCF0_CCD _SFR_MEM16(0x0B2E) -+#define TCF0_PERBUF _SFR_MEM16(0x0B36) -+#define TCF0_CCABUF _SFR_MEM16(0x0B38) -+#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) -+#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) -+#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCF2_CTRLA _SFR_MEM8(0x0B00) -+#define TCF2_CTRLB _SFR_MEM8(0x0B01) -+#define TCF2_CTRLC _SFR_MEM8(0x0B02) -+#define TCF2_CTRLE _SFR_MEM8(0x0B04) -+#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) -+#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) -+#define TCF2_CTRLF _SFR_MEM8(0x0B09) -+#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) -+#define TCF2_LCNT _SFR_MEM8(0x0B20) -+#define TCF2_HCNT _SFR_MEM8(0x0B21) -+#define TCF2_LPER _SFR_MEM8(0x0B26) -+#define TCF2_HPER _SFR_MEM8(0x0B27) -+#define TCF2_LCMPA _SFR_MEM8(0x0B28) -+#define TCF2_HCMPA _SFR_MEM8(0x0B29) -+#define TCF2_LCMPB _SFR_MEM8(0x0B2A) -+#define TCF2_HCMPB _SFR_MEM8(0x0B2B) -+#define TCF2_LCMPC _SFR_MEM8(0x0B2C) -+#define TCF2_HCMPC _SFR_MEM8(0x0B2D) -+#define TCF2_LCMPD _SFR_MEM8(0x0B2E) -+#define TCF2_HCMPD _SFR_MEM8(0x0B2F) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* VPORT - Virtual Ports */ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* CLK.USBCTRL bit masks and bit positions */ -+#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ -+#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ -+#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ -+#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ -+#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ -+#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ -+#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ -+#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ -+ -+#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ -+#define CLK_USBSRC_gp 1 /* Clock Source group position. */ -+#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ -+ -+#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_USB_bm 0x40 /* USB bit mask. */ -+#define PR_USB_bp 6 /* USB bit position. */ -+ -+#define PR_AES_bm 0x10 /* AES bit mask. */ -+#define PR_AES_bp 4 /* AES bit position. */ -+ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -+#define PR_DMA_bp 0 /* DMA-Controller bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -+#define PR_USART1_bp 5 /* Port C USART1 bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -+#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ -+ -+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -+ -+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ -+ -+/* PR.PRPD bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPE bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPF bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -+#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -+#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ -+ -+#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ -+ -+#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -+#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.ANAINIT bit masks and bit positions */ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.AWEXLOCK bit masks and bit positions */ -+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* PORTCFG - Port Configuration */ -+/* PORTCFG.VPCTRLA bit masks and bit positions */ -+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ -+ -+/* PORTCFG.VPCTRLB bit masks and bit positions */ -+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ -+ -+/* PORTCFG.CLKEVOUT bit masks and bit positions */ -+#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ -+ -+#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -+#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -+#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -+#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -+#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -+#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ -+ -+#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -+#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ -+ -+#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -+#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ -+ -+/* PORTCFG.EVOUTSEL bit masks and bit positions */ -+#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -+#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -+#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -+#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -+#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -+#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -+#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -+#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0x7F /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ -+ -+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ -+ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -+#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -+#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -+#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -+#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -+#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -+#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -+#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -+#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -+#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ -+ -+#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -+#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -+#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -+#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -+#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -+#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -+#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -+#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -+#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -+#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -+#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* RTC - Real-Time Counter */ -+/* RTC.CTRL bit masks and bit positions */ -+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ -+ -+/* RTC.STATUS bit masks and bit positions */ -+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC.INTCTRL bit masks and bit positions */ -+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC.INTFLAGS bit masks and bit positions */ -+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* USB - USB */ -+/* USB_EP.STATUS bit masks and bit positions */ -+#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ -+#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ -+ -+#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ -+#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ -+ -+#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ -+#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ -+ -+#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ -+#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ -+ -+#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ -+#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ -+ -+#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ -+#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ -+ -+#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ -+#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ -+ -+#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ -+#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ -+ -+#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ -+ -+#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ -+#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ -+ -+#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ -+#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ -+ -+/* USB_EP.CTRL bit masks and bit positions */ -+#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ -+#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ -+#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ -+#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ -+#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ -+#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ -+ -+#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ -+#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ -+ -+#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ -+#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ -+ -+#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ -+#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ -+ -+#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ -+#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ -+ -+#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ -+#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ -+#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ -+#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ -+#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ -+#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ -+#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ -+#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ -+ -+/* USB_EP.CNT bit masks and bit positions */ -+#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ -+#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ -+ -+/* USB.CTRLA bit masks and bit positions */ -+#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ -+#define USB_ENABLE_bp 7 /* USB Enable bit position. */ -+ -+#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ -+#define USB_SPEED_bp 6 /* Speed Select bit position. */ -+ -+#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ -+#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ -+ -+#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ -+#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ -+ -+#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ -+#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ -+#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ -+#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ -+#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ -+#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ -+#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ -+#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ -+#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ -+#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ -+ -+/* USB.CTRLB bit masks and bit positions */ -+#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ -+#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ -+ -+#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ -+#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ -+ -+#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ -+#define USB_GNACK_bp 1 /* Global NACK bit position. */ -+ -+#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ -+#define USB_ATTACH_bp 0 /* Attach bit position. */ -+ -+/* USB.STATUS bit masks and bit positions */ -+#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ -+#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ -+ -+#define USB_RESUME_bm 0x04 /* Resume bit mask. */ -+#define USB_RESUME_bp 2 /* Resume bit position. */ -+ -+#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ -+#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ -+ -+#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ -+#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ -+ -+/* USB.ADDR bit masks and bit positions */ -+#define USB_ADDR_gm 0x7F /* Device Address group mask. */ -+#define USB_ADDR_gp 0 /* Device Address group position. */ -+#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ -+#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ -+#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ -+#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ -+#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ -+#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ -+#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ -+#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ -+#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ -+#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ -+#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ -+#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ -+#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ -+#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ -+ -+/* USB.FIFOWP bit masks and bit positions */ -+#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ -+#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ -+#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ -+#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ -+#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ -+#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ -+#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ -+#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ -+#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ -+#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ -+#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ -+#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ -+ -+/* USB.FIFORP bit masks and bit positions */ -+#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ -+#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ -+#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ -+#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ -+#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ -+#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ -+#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ -+#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ -+#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ -+#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ -+#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ -+#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ -+ -+/* USB.INTCTRLA bit masks and bit positions */ -+#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ -+#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ -+ -+#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ -+#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ -+ -+#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ -+#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ -+ -+#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ -+#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ -+ -+#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* USB.INTCTRLB bit masks and bit positions */ -+#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ -+#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ -+ -+#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ -+#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ -+ -+/* USB.INTFLAGSACLR bit masks and bit positions */ -+#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ -+#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ -+ -+#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ -+#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ -+ -+#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ -+#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ -+ -+#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ -+#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ -+ -+#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ -+#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ -+ -+#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ -+#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ -+ -+#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ -+#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ -+ -+#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ -+#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSASET bit masks and bit positions */ -+/* USB_SOFIF Predefined. */ -+/* USB_SOFIF Predefined. */ -+ -+/* USB_SUSPENDIF Predefined. */ -+/* USB_SUSPENDIF Predefined. */ -+ -+/* USB_RESUMEIF Predefined. */ -+/* USB_RESUMEIF Predefined. */ -+ -+/* USB_RSTIF Predefined. */ -+/* USB_RSTIF Predefined. */ -+ -+/* USB_CRCIF Predefined. */ -+/* USB_CRCIF Predefined. */ -+ -+/* USB_UNFIF Predefined. */ -+/* USB_UNFIF Predefined. */ -+ -+/* USB_OVFIF Predefined. */ -+/* USB_OVFIF Predefined. */ -+ -+/* USB_STALLIF Predefined. */ -+/* USB_STALLIF Predefined. */ -+ -+/* USB.INTFLAGSBCLR bit masks and bit positions */ -+#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ -+#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ -+ -+#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ -+#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ -+ -+/* USB.INTFLAGSBSET bit masks and bit positions */ -+/* USB_TRNIF Predefined. */ -+/* USB_TRNIF Predefined. */ -+ -+/* USB_SETUPIF Predefined. */ -+/* USB_SETUPIF Predefined. */ -+ -+/* PORT - I/O Port Configuration */ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ -+ -+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -+#define PORT_SPI_bp 5 /* SPI bit position. */ -+ -+#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -+#define PORT_USART0_bp 4 /* USART0 bit position. */ -+ -+#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -+#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ -+ -+#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -+#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ -+ -+#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -+#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ -+ -+#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -+#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ -+ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC0.CTRLA bit masks and bit positions */ -+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC0.CTRLB bit masks and bit positions */ -+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ -+ -+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ -+ -+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC0.CTRLC bit masks and bit positions */ -+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ -+ -+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ -+ -+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC0.CTRLD bit masks and bit positions */ -+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC0_EVACT_gp 5 /* Event Action group position. */ -+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC0.CTRLE bit masks and bit positions */ -+#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC0.INTCTRLA bit masks and bit positions */ -+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC0.INTCTRLB bit masks and bit positions */ -+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ -+ -+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ -+ -+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC0.CTRLFCLR bit masks and bit positions */ -+#define TC0_CMD_gm 0x0C /* Command group mask. */ -+#define TC0_CMD_gp 2 /* Command group position. */ -+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC0_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC0_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC0_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC0.CTRLFSET bit masks and bit positions */ -+/* TC0_CMD Predefined. */ -+/* TC0_CMD Predefined. */ -+ -+/* TC0_LUPD Predefined. */ -+/* TC0_LUPD Predefined. */ -+ -+/* TC0_DIR Predefined. */ -+/* TC0_DIR Predefined. */ -+ -+/* TC0.CTRLGCLR bit masks and bit positions */ -+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ -+ -+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ -+ -+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC0.CTRLGSET bit masks and bit positions */ -+/* TC0_CCDBV Predefined. */ -+/* TC0_CCDBV Predefined. */ -+ -+/* TC0_CCCBV Predefined. */ -+/* TC0_CCCBV Predefined. */ -+ -+/* TC0_CCBBV Predefined. */ -+/* TC0_CCBBV Predefined. */ -+ -+/* TC0_CCABV Predefined. */ -+/* TC0_CCABV Predefined. */ -+ -+/* TC0_PERBV Predefined. */ -+/* TC0_PERBV Predefined. */ -+ -+/* TC0.INTFLAGS bit masks and bit positions */ -+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ -+ -+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ -+ -+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC1.CTRLA bit masks and bit positions */ -+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC1.CTRLB bit masks and bit positions */ -+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC1.CTRLC bit masks and bit positions */ -+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC1.CTRLD bit masks and bit positions */ -+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC1_EVACT_gp 5 /* Event Action group position. */ -+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC1.CTRLE bit masks and bit positions */ -+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ -+ -+/* TC1.INTCTRLA bit masks and bit positions */ -+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC1.INTCTRLB bit masks and bit positions */ -+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC1.CTRLFCLR bit masks and bit positions */ -+#define TC1_CMD_gm 0x0C /* Command group mask. */ -+#define TC1_CMD_gp 2 /* Command group position. */ -+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC1_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC1_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC1_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC1.CTRLFSET bit masks and bit positions */ -+/* TC1_CMD Predefined. */ -+/* TC1_CMD Predefined. */ -+ -+/* TC1_LUPD Predefined. */ -+/* TC1_LUPD Predefined. */ -+ -+/* TC1_DIR Predefined. */ -+/* TC1_DIR Predefined. */ -+ -+/* TC1.CTRLGCLR bit masks and bit positions */ -+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC1.CTRLGSET bit masks and bit positions */ -+/* TC1_CCBBV Predefined. */ -+/* TC1_CCBBV Predefined. */ -+ -+/* TC1_CCABV Predefined. */ -+/* TC1_CCABV Predefined. */ -+ -+/* TC1_PERBV Predefined. */ -+/* TC1_PERBV Predefined. */ -+ -+/* TC1.INTFLAGS bit masks and bit positions */ -+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+/* TC2.CTRLA bit masks and bit positions */ -+#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC2.CTRLB bit masks and bit positions */ -+#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -+#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ -+ -+#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -+#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ -+ -+#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -+#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ -+ -+#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -+#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ -+ -+#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -+#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ -+ -+#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -+#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ -+ -+#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -+#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ -+ -+#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -+#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ -+ -+/* TC2.CTRLC bit masks and bit positions */ -+#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -+#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ -+ -+#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -+#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ -+ -+#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -+#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ -+ -+#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -+#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ -+ -+#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -+#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ -+ -+#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -+#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ -+ -+#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -+#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ -+ -+#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -+#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ -+ -+/* TC2.CTRLE bit masks and bit positions */ -+#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC2.INTCTRLA bit masks and bit positions */ -+#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -+#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -+#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -+#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -+#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -+#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ -+ -+#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -+#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -+#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -+#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -+#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -+#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ -+ -+/* TC2.INTCTRLB bit masks and bit positions */ -+#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -+#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -+#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -+#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -+#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -+#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -+#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -+#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -+#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -+#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -+#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -+#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -+#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -+#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -+#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -+#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -+#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -+#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -+#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -+#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -+#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ -+ -+/* TC2.CTRLF bit masks and bit positions */ -+#define TC2_CMD_gm 0x0C /* Command group mask. */ -+#define TC2_CMD_gp 2 /* Command group position. */ -+#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC2_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -+#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -+#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -+#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -+#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -+#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ -+ -+/* TC2.INTFLAGS bit masks and bit positions */ -+#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -+#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ -+ -+#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -+#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ -+ -+#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -+#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ -+ -+#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -+#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ -+ -+#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ -+ -+#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ -+ -+/* AWEX - Timer/Counter Advanced Waveform Extension */ -+/* AWEX.CTRL bit masks and bit positions */ -+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ -+ -+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ -+ -+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ -+ -+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ -+ -+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ -+ -+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ -+ -+/* AWEX.FDCTRL bit masks and bit positions */ -+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ -+ -+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ -+ -+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ -+ -+/* AWEX.STATUS bit masks and bit positions */ -+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ -+ -+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ -+ -+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ -+ -+/* AWEX.STATUSSET bit masks and bit positions */ -+/* AWEX_FDF Predefined. */ -+/* AWEX_FDF Predefined. */ -+ -+/* AWEX_DTHSBUFV Predefined. */ -+/* AWEX_DTHSBUFV Predefined. */ -+ -+/* AWEX_DTLSBUFV Predefined. */ -+/* AWEX_DTLSBUFV Predefined. */ -+ -+/* HIRES - Timer/Counter High-Resolution Extension */ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -+#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* LOCKBIT - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT0_vect_num 2 -+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -+#define PORTC_INT1_vect_num 3 -+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT0_vect_num 4 -+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -+#define PORTR_INT1_vect_num 5 -+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ -+ -+/* RTC interrupt vectors */ -+#define RTC_OVF_vect_num 10 -+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -+#define RTC_COMP_vect_num 11 -+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 12 -+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 13 -+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_OVF_vect_num 14 -+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LUNF_vect_num 14 -+#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_ERR_vect_num 15 -+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_HUNF_vect_num 15 -+#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCA_vect_num 16 -+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPA_vect_num 16 -+#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCB_vect_num 17 -+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPB_vect_num 17 -+#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCC_vect_num 18 -+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPC_vect_num 18 -+#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCD_vect_num 19 -+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPD_vect_num 19 -+#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ -+ -+/* TCC1 interrupt vectors */ -+#define TCC1_OVF_vect_num 20 -+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -+#define TCC1_ERR_vect_num 21 -+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -+#define TCC1_CCA_vect_num 22 -+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -+#define TCC1_CCB_vect_num 23 -+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 24 -+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 25 -+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 26 -+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 27 -+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 32 -+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -+#define NVM_SPM_vect_num 33 -+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ -+ -+/* PORTB interrupt vectors */ -+#define PORTB_INT0_vect_num 34 -+#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -+#define PORTB_INT1_vect_num 35 -+#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ -+ -+/* PORTE interrupt vectors */ -+#define PORTE_INT0_vect_num 43 -+#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -+#define PORTE_INT1_vect_num 44 -+#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ -+ -+/* TWIE interrupt vectors */ -+#define TWIE_TWIS_vect_num 45 -+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -+#define TWIE_TWIM_vect_num 46 -+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_OVF_vect_num 47 -+#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LUNF_vect_num 47 -+#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_ERR_vect_num 48 -+#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_HUNF_vect_num 48 -+#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCA_vect_num 49 -+#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPA_vect_num 49 -+#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCB_vect_num 50 -+#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPB_vect_num 50 -+#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCC_vect_num 51 -+#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPC_vect_num 51 -+#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_CCD_vect_num 52 -+#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ -+ -+/* TCE2 interrupt vectors */ -+#define TCE2_LCMPD_vect_num 52 -+#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ -+ -+/* USARTE0 interrupt vectors */ -+#define USARTE0_RXC_vect_num 58 -+#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -+#define USARTE0_DRE_vect_num 59 -+#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -+#define USARTE0_TXC_vect_num 60 -+#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT0_vect_num 64 -+#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -+#define PORTD_INT1_vect_num 65 -+#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ -+ -+/* PORTA interrupt vectors */ -+#define PORTA_INT0_vect_num 66 -+#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -+#define PORTA_INT1_vect_num 67 -+#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ -+ -+/* ACA interrupt vectors */ -+#define ACA_AC0_vect_num 68 -+#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -+#define ACA_AC1_vect_num 69 -+#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -+#define ACA_ACW_vect_num 70 -+#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ -+ -+/* ADCA interrupt vectors */ -+#define ADCA_CH0_vect_num 71 -+#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_OVF_vect_num 77 -+#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LUNF_vect_num 77 -+#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_ERR_vect_num 78 -+#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_HUNF_vect_num 78 -+#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCA_vect_num 79 -+#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPA_vect_num 79 -+#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCB_vect_num 80 -+#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPB_vect_num 80 -+#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCC_vect_num 81 -+#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPC_vect_num 81 -+#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCD_vect_num 82 -+#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPD_vect_num 82 -+#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ -+ -+/* SPID interrupt vectors */ -+#define SPID_INT_vect_num 87 -+#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ -+ -+/* USARTD0 interrupt vectors */ -+#define USARTD0_RXC_vect_num 88 -+#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -+#define USARTD0_DRE_vect_num 89 -+#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -+#define USARTD0_TXC_vect_num 90 -+#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ -+ -+/* PORTF interrupt vectors */ -+#define PORTF_INT0_vect_num 104 -+#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ -+#define PORTF_INT1_vect_num 105 -+#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_OVF_vect_num 108 -+#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LUNF_vect_num 108 -+#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_ERR_vect_num 109 -+#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_HUNF_vect_num 109 -+#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCA_vect_num 110 -+#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPA_vect_num 110 -+#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCB_vect_num 111 -+#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPB_vect_num 111 -+#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCC_vect_num 112 -+#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPC_vect_num 112 -+#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ -+ -+/* TCF0 interrupt vectors */ -+#define TCF0_CCD_vect_num 113 -+#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ -+ -+/* TCF2 interrupt vectors */ -+#define TCF2_LCMPD_vect_num 113 -+#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ -+ -+/* USB interrupt vectors */ -+#define USB_BUSEVENT_vect_num 125 -+#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ -+#define USB_TRNCOMPL_vect_num 126 -+#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (127 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (69632) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (65536) -+#define APP_SECTION_PAGE_SIZE (256) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0xE000) -+#define APPTABLE_SECTION_SIZE (4096) -+#define APPTABLE_SECTION_PAGE_SIZE (256) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x10000) -+#define BOOT_SECTION_SIZE (4096) -+#define BOOT_SECTION_PAGE_SIZE (256) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (12288) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (2048) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (4096) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (2048) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (6) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (256) -+#define USER_SIGNATURES_PAGE_SIZE (256) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (64) -+#define PROD_SIGNATURES_PAGE_SIZE (256) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 256 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 6 -+ -+/* Fuse Byte 0 Reserved */ -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x96 -+#define SIGNATURE_2 0x49 -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA64C3_H_INCLUDED */ -+ -diff --git a/include/avr/iox64d3.h b/include/avr/iox64d3.h -index df6b35e..8b84da5 100644 ---- a/include/avr/iox64d3.h -+++ b/include/avr/iox64d3.h -@@ -174,7 +174,7 @@ typedef struct PR_struct - { - register8_t PRGEN; /* General Power Reduction */ - register8_t PRPA; /* Power Reduction Port A */ +- ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox64a1u.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA64A1U_H_INCLUDED ++#define _AVR_ATXMEGA64A1U_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t USBCTRL; /* USB Control Register */ ++} CLK_t; ++ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t PRPB; /* Power Reduction Port B */ ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++/* USB Prescaler Division Factor */ ++typedef enum CLK_USBPSDIV_enum ++{ ++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ ++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ ++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ ++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ ++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ ++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ ++} CLK_USBPSDIV_t; ++ ++/* USB Clock Source */ ++typedef enum CLK_USBSRC_enum ++{ ++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ ++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ ++} CLK_USBSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 2 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC2MCREF_enum ++{ ++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC2MCREF_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++ register8_t EBIOUT; /* EBI Output register */ ++ register8_t EVOUTSEL; /* Event Output Select */ ++} PORTCFG_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP02MAP_enum ++{ ++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP02MAP_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP13MAP_enum ++{ ++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP13MAP_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Clock and Event Output Port */ ++typedef enum PORTCFG_CLKEVPIN_enum ++{ ++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ ++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ ++} PORTCFG_CLKEVPIN_t; ++ ++/* EBI Address Output Port */ ++typedef enum PORTCFG_EBIADROUT_enum ++{ ++ PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ ++ PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ ++ PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ ++ PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ ++} PORTCFG_EBIADROUT_t; ++ ++/* EBI Chip Select Output Port */ ++typedef enum PORTCFG_EBICSOUT_enum ++{ ++ PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ ++} PORTCFG_EBICSOUT_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ ++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ ++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ ++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ ++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AES - AES Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* AES Module */ ++typedef struct AES_struct ++{ ++ register8_t CTRL; /* AES Control Register */ ++ register8_t STATUS; /* AES Status Register */ ++ register8_t STATE; /* AES State Register */ ++ register8_t KEY; /* AES Key Register */ ++ register8_t INTCTRL; /* AES Interrupt Control Register */ ++} AES_t; ++ ++/* Interrupt level */ ++typedef enum AES_INTLVL_enum ++{ ++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} AES_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ ++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ ++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ ++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Channel */ ++typedef struct DMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Address Control */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ ++ register8_t REPCNT; /* Channel Repeat Count */ ++ register8_t reserved_0x07; ++ register8_t SRCADDR0; /* Channel Source Address 0 */ ++ register8_t SRCADDR1; /* Channel Source Address 1 */ ++ register8_t SRCADDR2; /* Channel Source Address 2 */ ++ register8_t reserved_0x0B; ++ register8_t DESTADDR0; /* Channel Destination Address 0 */ ++ register8_t DESTADDR1; /* Channel Destination Address 1 */ ++ register8_t DESTADDR2; /* Channel Destination Address 2 */ ++ register8_t reserved_0x0F; ++} DMA_CH_t; ++ ++ ++/* DMA Controller */ ++typedef struct DMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ DMA_CH_t CH0; /* DMA Channel 0 */ ++ DMA_CH_t CH1; /* DMA Channel 1 */ ++ DMA_CH_t CH2; /* DMA Channel 2 */ ++ DMA_CH_t CH3; /* DMA Channel 3 */ ++} DMA_t; ++ ++/* Burst mode */ ++typedef enum DMA_CH_BURSTLEN_enum ++{ ++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ ++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ ++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ ++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ ++} DMA_CH_BURSTLEN_t; ++ ++/* Source address reload mode */ ++typedef enum DMA_CH_SRCRELOAD_enum ++{ ++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ ++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ ++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ ++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ ++} DMA_CH_SRCRELOAD_t; ++ ++/* Source addressing mode */ ++typedef enum DMA_CH_SRCDIR_enum ++{ ++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ ++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ ++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ ++} DMA_CH_SRCDIR_t; ++ ++/* Destination adress reload mode */ ++typedef enum DMA_CH_DESTRELOAD_enum ++{ ++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ ++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ ++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ ++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ ++} DMA_CH_DESTRELOAD_t; ++ ++/* Destination adressing mode */ ++typedef enum DMA_CH_DESTDIR_enum ++{ ++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ ++} DMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum DMA_CH_TRIGSRC_enum ++{ ++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ ++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ ++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ ++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ ++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ ++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ ++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ ++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ ++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ ++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ ++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ ++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ ++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ ++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ ++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ ++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ ++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ ++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ ++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ ++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ ++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ ++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ ++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ ++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ ++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ ++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ ++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ ++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ ++} DMA_CH_TRIGSRC_t; ++ ++/* Double buffering mode */ ++typedef enum DMA_DBUFMODE_enum ++{ ++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ ++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ ++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ ++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ ++} DMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum DMA_PRIMODE_enum ++{ ++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ ++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ ++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ ++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ ++} DMA_PRIMODE_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_ERRINTLVL_enum ++{ ++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ ++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ ++} DMA_CH_ERRINTLVL_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_TRNINTLVL_enum ++{ ++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ ++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ ++} DMA_CH_TRNINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ ++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ ++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ ++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t CH4CTRL; /* Channel 4 Control Register */ ++ register8_t CH5CTRL; /* Channel 5 Control Register */ ++ register8_t CH6CTRL; /* Channel 6 Control Register */ ++ register8_t CH7CTRL; /* Channel 7 Control Register */ ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ ++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ ++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ ++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ ++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ ++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ ++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ ++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ ++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ ++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ ++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ ++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ ++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ ++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ ++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ ++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ ++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ ++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t reserved_0x07; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ _WORDREGISTER(CH1RES); /* Channel 1 Result */ ++ _WORDREGISTER(CH2RES); /* Channel 2 Result */ ++ _WORDREGISTER(CH3RES); /* Channel 3 Result */ ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++ ADC_CH_t CH1; /* ADC Channel 1 */ ++ ADC_CH_t CH2; /* ADC Channel 2 */ ++ ADC_CH_t CH3; /* ADC Channel 3 */ ++} ADC_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ ++ ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ ++ ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ ++ ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Current Limitation Mode */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ ++} ADC_CURRLIMIT_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Channel sweep selection */ ++typedef enum ADC_SWEEP_enum ++{ ++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ ++} ADC_SWEEP_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* DMA request selection */ ++typedef enum ADC_DMASEL_enum ++{ ++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ ++} ADC_DMASEL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DAC - Digital/Analog Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Digital-to-Analog Converter */ ++typedef struct DAC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t EVCTRL; /* Event Input Control */ ++ register8_t reserved_0x04; ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0GAINCAL; /* Gain Calibration */ ++ register8_t CH0OFFSETCAL; /* Offset Calibration */ ++ register8_t CH1GAINCAL; /* Gain Calibration */ ++ register8_t CH1OFFSETCAL; /* Offset Calibration */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ ++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ ++} DAC_t; ++ ++/* Output channel selection */ ++typedef enum DAC_CHSEL_enum ++{ ++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ ++ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ ++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ ++} DAC_CHSEL_t; ++ ++/* Reference voltage selection */ ++typedef enum DAC_REFSEL_enum ++{ ++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ ++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ ++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ ++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ ++} DAC_REFSEL_t; ++ ++/* Event channel selection */ ++typedef enum DAC_EVSEL_enum ++{ ++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ ++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ ++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ ++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ ++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ ++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ ++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ ++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ ++} DAC_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* EBI Chip Select Module */ ++typedef struct EBI_CS_struct ++{ ++ register8_t CTRLA; /* Chip Select Control Register A */ ++ register8_t CTRLB; /* Chip Select Control Register B */ ++ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ ++} EBI_CS_t; ++ ++ ++/* External Bus Interface */ ++typedef struct EBI_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ ++ register8_t reserved_0x02; ++ register8_t reserved_0x03; ++ _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ ++ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ ++ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ ++ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ EBI_CS_t CS0; /* Chip Select 0 */ ++ EBI_CS_t CS1; /* Chip Select 1 */ ++ EBI_CS_t CS2; /* Chip Select 2 */ ++ EBI_CS_t CS3; /* Chip Select 3 */ ++} EBI_t; ++ ++/* Chip Select adress space */ ++typedef enum EBI_CS_ASPACE_enum ++{ ++ EBI_CS_ASPACE_256B_gc = (0x00<<2), /* 256 bytes */ ++ EBI_CS_ASPACE_512B_gc = (0x01<<2), /* 512 bytes */ ++ EBI_CS_ASPACE_1KB_gc = (0x02<<2), /* 1K bytes */ ++ EBI_CS_ASPACE_2KB_gc = (0x03<<2), /* 2K bytes */ ++ EBI_CS_ASPACE_4KB_gc = (0x04<<2), /* 4K bytes */ ++ EBI_CS_ASPACE_8KB_gc = (0x05<<2), /* 8K bytes */ ++ EBI_CS_ASPACE_16KB_gc = (0x06<<2), /* 16K bytes */ ++ EBI_CS_ASPACE_32KB_gc = (0x07<<2), /* 32K bytes */ ++ EBI_CS_ASPACE_64KB_gc = (0x08<<2), /* 64K bytes */ ++ EBI_CS_ASPACE_128KB_gc = (0x09<<2), /* 128K bytes */ ++ EBI_CS_ASPACE_256KB_gc = (0x0A<<2), /* 256K bytes */ ++ EBI_CS_ASPACE_512KB_gc = (0x0B<<2), /* 512K bytes */ ++ EBI_CS_ASPACE_1MB_gc = (0x0C<<2), /* 1M bytes */ ++ EBI_CS_ASPACE_2MB_gc = (0x0D<<2), /* 2M bytes */ ++ EBI_CS_ASPACE_4MB_gc = (0x0E<<2), /* 4M bytes */ ++ EBI_CS_ASPACE_8MB_gc = (0x0F<<2), /* 8M bytes */ ++ EBI_CS_ASPACE_16M_gc = (0x10<<2), /* 16M bytes */ ++} EBI_CS_ASPACE_t; ++ ++/* SRAM Wait State Selection */ ++typedef enum EBI_CS_SRWS_enum ++{ ++ EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycles */ ++ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_CS_SRWS_t; ++ ++/* Chip Select address mode */ ++typedef enum EBI_CS_MODE_enum ++{ ++ EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ ++ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ ++ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ ++ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ ++} EBI_CS_MODE_t; ++ ++/* Chip Select SDRAM mode */ ++typedef enum EBI_CS_SDMODE_enum ++{ ++ EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ ++ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ ++} EBI_CS_SDMODE_t; ++ ++/* */ ++typedef enum EBI_SDDATAW_enum ++{ ++ EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ ++ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ ++} EBI_SDDATAW_t; ++ ++/* */ ++typedef enum EBI_LPCMODE_enum ++{ ++ EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ ++ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ ++} EBI_LPCMODE_t; ++ ++/* */ ++typedef enum EBI_SRMODE_enum ++{ ++ EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ ++ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ ++ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ ++ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ ++} EBI_SRMODE_t; ++ ++/* */ ++typedef enum EBI_IFMODE_enum ++{ ++ EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ ++ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ ++ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ ++ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ ++} EBI_IFMODE_t; ++ ++/* */ ++typedef enum EBI_SDCOL_enum ++{ ++ EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ ++ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ ++ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ ++ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ ++} EBI_SDCOL_t; ++ ++/* SDRAM Load Mode to Active delay */ ++typedef enum EBI_MRDLY_enum ++{ ++ EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_MRDLY_t; ++ ++/* SDRAM Row Cycle Delay */ ++typedef enum EBI_ROWCYCDLY_enum ++{ ++ EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycles */ ++ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ROWCYCDLY_t; ++ ++/* SDRAM Row to Precharge Delay */ ++typedef enum EBI_RPDLY_enum ++{ ++ EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycles */ ++ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_RPDLY_t; ++ ++/* SDRAM Write Recovery Delay */ ++typedef enum EBI_WRDLY_enum ++{ ++ EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_WRDLY_t; ++ ++/* SDRAM Exit Self Refresh to Active Delay */ ++typedef enum EBI_ESRDLY_enum ++{ ++ EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycles */ ++ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ESRDLY_t; ++ ++/* SDRAM Row to Column Delay */ ++typedef enum EBI_ROWCOLDLY_enum ++{ ++ EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycles */ ++ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_ROWCOLDLY_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++/* SDA hold time */ ++typedef enum SDA_HOLD_TIME_enum ++{ ++ SDA_HOLD_TIME_OFF_gc = (0x00<<1), /* SDA hold time off */ ++ SDA_HOLD_TIME_50NS_gc = (0x01<<1), /* Typical 50ns hold time */ ++ SDA_HOLD_TIME_300NS_gc = (0x02<<1), /* Typical 300ns hold time */ ++ SDA_HOLD_TIME_400NS_gc = (0x03<<1), /* Typical 400ns hold time */ ++} SDA_HOLD_TIME_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USB - USB ++-------------------------------------------------------------------------- ++*/ ++ ++/* USB Endpoint */ ++typedef struct USB_EP_struct ++{ ++ register8_t STATUS; /* Endpoint Status */ ++ register8_t CTRL; /* Endpoint Control */ ++ _WORDREGISTER(CNT); /* USB Endpoint Counter */ ++ _WORDREGISTER(DATAPTR); /* Data Pointer */ ++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ ++} USB_EP_t; ++ ++ ++/* Universal Serial Bus */ ++typedef struct USB_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t FIFOWP; /* FIFO Write Pointer Register */ ++ register8_t FIFORP; /* FIFO Read Pointer Register */ ++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ ++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ ++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ ++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t reserved_0x20; ++ register8_t reserved_0x21; ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t CAL0; /* Calibration Byte 0 */ ++ register8_t CAL1; /* Calibration Byte 1 */ ++} USB_t; ++ ++ ++/* USB Endpoint Table */ ++typedef struct USB_EP_TABLE_struct ++{ ++ USB_EP_t EP0OUT; /* Endpoint 0 */ ++ USB_EP_t EP0IN; /* Endpoint 0 */ ++ USB_EP_t EP1OUT; /* Endpoint 1 */ ++ USB_EP_t EP1IN; /* Endpoint 1 */ ++ USB_EP_t EP2OUT; /* Endpoint 2 */ ++ USB_EP_t EP2IN; /* Endpoint 2 */ ++ USB_EP_t EP3OUT; /* Endpoint 3 */ ++ USB_EP_t EP3IN; /* Endpoint 3 */ ++ USB_EP_t EP4OUT; /* Endpoint 4 */ ++ USB_EP_t EP4IN; /* Endpoint 4 */ ++ USB_EP_t EP5OUT; /* Endpoint 5 */ ++ USB_EP_t EP5IN; /* Endpoint 5 */ ++ USB_EP_t EP6OUT; /* Endpoint 6 */ ++ USB_EP_t EP6IN; /* Endpoint 6 */ ++ USB_EP_t EP7OUT; /* Endpoint 7 */ ++ USB_EP_t EP7IN; /* Endpoint 7 */ ++ USB_EP_t EP8OUT; /* Endpoint 8 */ ++ USB_EP_t EP8IN; /* Endpoint 8 */ ++ USB_EP_t EP9OUT; /* Endpoint 9 */ ++ USB_EP_t EP9IN; /* Endpoint 9 */ ++ USB_EP_t EP10OUT; /* Endpoint 10 */ ++ USB_EP_t EP10IN; /* Endpoint 10 */ ++ USB_EP_t EP11OUT; /* Endpoint 11 */ ++ USB_EP_t EP11IN; /* Endpoint 11 */ ++ USB_EP_t EP12OUT; /* Endpoint 12 */ ++ USB_EP_t EP12IN; /* Endpoint 12 */ ++ USB_EP_t EP13OUT; /* Endpoint 13 */ ++ USB_EP_t EP13IN; /* Endpoint 13 */ ++ USB_EP_t EP14OUT; /* Endpoint 14 */ ++ USB_EP_t EP14IN; /* Endpoint 14 */ ++ USB_EP_t EP15OUT; /* Endpoint 15 */ ++ USB_EP_t EP15IN; /* Endpoint 15 */ ++ register8_t reserved_0x100; ++ register8_t reserved_0x101; ++ register8_t reserved_0x102; ++ register8_t reserved_0x103; ++ register8_t reserved_0x104; ++ register8_t reserved_0x105; ++ register8_t reserved_0x106; ++ register8_t reserved_0x107; ++ register8_t reserved_0x108; ++ register8_t reserved_0x109; ++ register8_t reserved_0x10A; ++ register8_t reserved_0x10B; ++ register8_t reserved_0x10C; ++ register8_t reserved_0x10D; ++ register8_t reserved_0x10E; ++ register8_t reserved_0x10F; ++ register8_t FRAMENUML; /* Frame Number Low Byte */ ++ register8_t FRAMENUMH; /* Frame Number High Byte */ ++} USB_EP_TABLE_t; ++ ++/* Interrupt level */ ++typedef enum USB_INTLVL_enum ++{ ++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} USB_INTLVL_t; ++ ++/* USB Endpoint Type */ ++typedef enum USB_EP_TYPE_enum ++{ ++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ ++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ ++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ ++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ ++} USB_EP_TYPE_t; ++ ++/* USB Endpoint Buffersize */ ++typedef enum USB_EP_BUFSIZE_enum ++{ ++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ ++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ ++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ ++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ ++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ ++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ ++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ ++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ ++} USB_EP_BUFSIZE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - I/O Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* I/O Port Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Byte Mode */ ++typedef enum TC_BYTEM_enum ++{ ++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ ++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ ++} TC_BYTEM_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC2 - 16-bit Timer/Counter type 2 ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter type 2 */ ++typedef struct TC2_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t reserved_0x03; ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t reserved_0x08; ++ register8_t CTRLF; /* Control Register F */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t LCNT; /* Low Byte Count */ ++ register8_t HCNT; /* High Byte Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t LPER; /* Low Byte Period */ ++ register8_t HPER; /* High Byte Period */ ++ register8_t LCMPA; /* Low Byte Compare A */ ++ register8_t HCMPA; /* High Byte Compare A */ ++ register8_t LCMPB; /* Low Byte Compare B */ ++ register8_t HCMPB; /* High Byte Compare B */ ++ register8_t LCMPC; /* Low Byte Compare C */ ++ register8_t HCMPC; /* High Byte Compare C */ ++ register8_t LCMPD; /* Low Byte Compare D */ ++ register8_t HCMPD; /* High Byte Compare D */ ++} TC2_t; ++ ++/* Clock Selection */ ++typedef enum TC2_CLKSEL_enum ++{ ++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC2_CLKSEL_t; ++ ++/* Byte Mode */ ++typedef enum TC2_BYTEM_enum ++{ ++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ ++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ ++} TC2_BYTEM_t; ++ ++/* High Byte Underflow Interrupt Level */ ++typedef enum TC2_HUNFINTLVL_enum ++{ ++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_HUNFINTLVL_t; ++ ++/* Low Byte Underflow Interrupt Level */ ++typedef enum TC2_LUNFINTLVL_enum ++{ ++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LUNFINTLVL_t; ++ ++/* Low Byte Compare D Interrupt Level */ ++typedef enum TC2_LCMPDINTLVL_enum ++{ ++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC2_LCMPDINTLVL_t; ++ ++/* Low Byte Compare C Interrupt Level */ ++typedef enum TC2_LCMPCINTLVL_enum ++{ ++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC2_LCMPCINTLVL_t; ++ ++/* Low Byte Compare B Interrupt Level */ ++typedef enum TC2_LCMPBINTLVL_enum ++{ ++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_LCMPBINTLVL_t; ++ ++/* Low Byte Compare A Interrupt Level */ ++typedef enum TC2_LCMPAINTLVL_enum ++{ ++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LCMPAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMD_enum ++{ ++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC2_CMD_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMDEN_enum ++{ ++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ ++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ ++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ ++} TC2_CMDEN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AWEX - Timer/Counter Advanced Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - Timer/Counter High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t FUSEBYTE0; /* JTAG User ID */ ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* Timer Oscillator pin location */ ++typedef enum TOSCSEL_enum ++{ ++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ ++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ ++} TOSCSEL_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* BOD operation */ ++typedef enum BODACT_enum ++{ ++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BODACT_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WDP_enum ++{ ++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ ++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ ++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ ++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ ++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ ++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ ++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ ++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ ++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ ++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ ++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ ++} WDP_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LOCKBIT - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ ++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t USBCAL0; /* USB Calibration Byte 0 */ ++ register8_t USBCAL1; /* USB Calibration Byte 1 */ ++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ ++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ ++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ ++ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ ++ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ ++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ ++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ ++ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ ++ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++ register8_t reserved_0x40; ++ register8_t reserved_0x41; ++ register8_t reserved_0x42; ++ register8_t reserved_0x43; ++ register8_t reserved_0x44; ++ register8_t reserved_0x45; ++ register8_t reserved_0x46; ++ register8_t reserved_0x47; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define AES (*(AES_t *) 0x00C0) /* AES Module */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ ++#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ ++#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ ++#define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface */ ++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ ++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ ++#define PORTH (*(PORT_t *) 0x06E0) /* I/O Ports */ ++#define PORTJ (*(PORT_t *) 0x0700) /* I/O Ports */ ++#define PORTK (*(PORT_t *) 0x0720) /* I/O Ports */ ++#define PORTQ (*(PORT_t *) 0x07C0) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ ++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ ++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ ++#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ ++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ ++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ ++#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ ++#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ ++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ ++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ ++#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ ++#define TCF1 (*(TC1_t *) 0x0B40) /* 16-bit Timer/Counter 1 */ ++#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ ++#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++#define GPIO_GPIOR4 _SFR_MEM8(0x0004) ++#define GPIO_GPIOR5 _SFR_MEM8(0x0005) ++#define GPIO_GPIOR6 _SFR_MEM8(0x0006) ++#define GPIO_GPIOR7 _SFR_MEM8(0x0007) ++#define GPIO_GPIOR8 _SFR_MEM8(0x0008) ++#define GPIO_GPIOR9 _SFR_MEM8(0x0009) ++#define GPIO_GPIORA _SFR_MEM8(0x000A) ++#define GPIO_GPIORB _SFR_MEM8(0x000B) ++#define GPIO_GPIORC _SFR_MEM8(0x000C) ++#define GPIO_GPIORD _SFR_MEM8(0x000D) ++#define GPIO_GPIORE _SFR_MEM8(0x000E) ++#define GPIO_GPIORF _SFR_MEM8(0x000F) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++#define GPIO_GPIO4 _SFR_MEM8(0x0004) ++#define GPIO_GPIO5 _SFR_MEM8(0x0005) ++#define GPIO_GPIO6 _SFR_MEM8(0x0006) ++#define GPIO_GPIO7 _SFR_MEM8(0x0007) ++#define GPIO_GPIO8 _SFR_MEM8(0x0008) ++#define GPIO_GPIO9 _SFR_MEM8(0x0009) ++#define GPIO_GPIOA _SFR_MEM8(0x000A) ++#define GPIO_GPIOB _SFR_MEM8(0x000B) ++#define GPIO_GPIOC _SFR_MEM8(0x000C) ++#define GPIO_GPIOD _SFR_MEM8(0x000D) ++#define GPIO_GPIOE _SFR_MEM8(0x000E) ++#define GPIO_GPIOF _SFR_MEM8(0x000F) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) ++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) ++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) ++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) ++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) ++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) ++#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) ++#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) ++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) ++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) ++#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) ++#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++#define CLK_USBCTRL _SFR_MEM8(0x0044) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLL - DFLL */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPB _SFR_MEM8(0x0072) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) ++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) ++ ++/* AES - AES Module */ ++#define AES_CTRL _SFR_MEM8(0x00C0) ++#define AES_STATUS _SFR_MEM8(0x00C1) ++#define AES_STATE _SFR_MEM8(0x00C2) ++#define AES_KEY _SFR_MEM8(0x00C3) ++#define AES_INTCTRL _SFR_MEM8(0x00C4) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* DMA - DMA Controller */ ++#define DMA_CTRL _SFR_MEM8(0x0100) ++#define DMA_INTFLAGS _SFR_MEM8(0x0103) ++#define DMA_STATUS _SFR_MEM8(0x0104) ++#define DMA_TEMP _SFR_MEM16(0x0106) ++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) ++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) ++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) ++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) ++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) ++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) ++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) ++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) ++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) ++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) ++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) ++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) ++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) ++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) ++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) ++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) ++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) ++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) ++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) ++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) ++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) ++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) ++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) ++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) ++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) ++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) ++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) ++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) ++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) ++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) ++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) ++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) ++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) ++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) ++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) ++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) ++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) ++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) ++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) ++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) ++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) ++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH4MUX _SFR_MEM8(0x0184) ++#define EVSYS_CH5MUX _SFR_MEM8(0x0185) ++#define EVSYS_CH6MUX _SFR_MEM8(0x0186) ++#define EVSYS_CH7MUX _SFR_MEM8(0x0187) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) ++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) ++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) ++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CH1RES _SFR_MEM16(0x0212) ++#define ADCA_CH2RES _SFR_MEM16(0x0214) ++#define ADCA_CH3RES _SFR_MEM16(0x0216) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) ++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) ++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) ++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) ++#define ADCA_CH1_RES _SFR_MEM16(0x022C) ++#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) ++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) ++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) ++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) ++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) ++#define ADCA_CH2_RES _SFR_MEM16(0x0234) ++#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) ++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) ++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) ++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) ++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) ++#define ADCA_CH3_RES _SFR_MEM16(0x023C) ++#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCB_CTRLA _SFR_MEM8(0x0240) ++#define ADCB_CTRLB _SFR_MEM8(0x0241) ++#define ADCB_REFCTRL _SFR_MEM8(0x0242) ++#define ADCB_EVCTRL _SFR_MEM8(0x0243) ++#define ADCB_PRESCALER _SFR_MEM8(0x0244) ++#define ADCB_INTFLAGS _SFR_MEM8(0x0246) ++#define ADCB_TEMP _SFR_MEM8(0x0247) ++#define ADCB_CAL _SFR_MEM16(0x024C) ++#define ADCB_CH0RES _SFR_MEM16(0x0250) ++#define ADCB_CH1RES _SFR_MEM16(0x0252) ++#define ADCB_CH2RES _SFR_MEM16(0x0254) ++#define ADCB_CH3RES _SFR_MEM16(0x0256) ++#define ADCB_CMP _SFR_MEM16(0x0258) ++#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) ++#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) ++#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) ++#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) ++#define ADCB_CH0_RES _SFR_MEM16(0x0264) ++#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) ++#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) ++#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) ++#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) ++#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) ++#define ADCB_CH1_RES _SFR_MEM16(0x026C) ++#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) ++#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) ++#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) ++#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) ++#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) ++#define ADCB_CH2_RES _SFR_MEM16(0x0274) ++#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) ++#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) ++#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) ++#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) ++#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) ++#define ADCB_CH3_RES _SFR_MEM16(0x027C) ++#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) ++ ++/* DAC - Digital-to-Analog Converter */ ++#define DACA_CTRLA _SFR_MEM8(0x0300) ++#define DACA_CTRLB _SFR_MEM8(0x0301) ++#define DACA_CTRLC _SFR_MEM8(0x0302) ++#define DACA_EVCTRL _SFR_MEM8(0x0303) ++#define DACA_STATUS _SFR_MEM8(0x0305) ++#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) ++#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) ++#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) ++#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) ++#define DACA_CH0DATA _SFR_MEM16(0x0318) ++#define DACA_CH1DATA _SFR_MEM16(0x031A) ++ ++/* DAC - Digital-to-Analog Converter */ ++#define DACB_CTRLA _SFR_MEM8(0x0320) ++#define DACB_CTRLB _SFR_MEM8(0x0321) ++#define DACB_CTRLC _SFR_MEM8(0x0322) ++#define DACB_EVCTRL _SFR_MEM8(0x0323) ++#define DACB_STATUS _SFR_MEM8(0x0325) ++#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) ++#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) ++#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) ++#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) ++#define DACB_CH0DATA _SFR_MEM16(0x0338) ++#define DACB_CH1DATA _SFR_MEM16(0x033A) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* AC - Analog Comparator */ ++#define ACB_AC0CTRL _SFR_MEM8(0x0390) ++#define ACB_AC1CTRL _SFR_MEM8(0x0391) ++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) ++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) ++#define ACB_CTRLA _SFR_MEM8(0x0394) ++#define ACB_CTRLB _SFR_MEM8(0x0395) ++#define ACB_WINCTRL _SFR_MEM8(0x0396) ++#define ACB_STATUS _SFR_MEM8(0x0397) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* EBI - External Bus Interface */ ++#define EBI_CTRL _SFR_MEM8(0x0440) ++#define EBI_SDRAMCTRLA _SFR_MEM8(0x0441) ++#define EBI_REFRESH _SFR_MEM16(0x0444) ++#define EBI_INITDLY _SFR_MEM16(0x0446) ++#define EBI_SDRAMCTRLB _SFR_MEM8(0x0448) ++#define EBI_SDRAMCTRLC _SFR_MEM8(0x0449) ++#define EBI_CS0_CTRLA _SFR_MEM8(0x0450) ++#define EBI_CS0_CTRLB _SFR_MEM8(0x0451) ++#define EBI_CS0_BASEADDR _SFR_MEM16(0x0452) ++#define EBI_CS1_CTRLA _SFR_MEM8(0x0454) ++#define EBI_CS1_CTRLB _SFR_MEM8(0x0455) ++#define EBI_CS1_BASEADDR _SFR_MEM16(0x0456) ++#define EBI_CS2_CTRLA _SFR_MEM8(0x0458) ++#define EBI_CS2_CTRLB _SFR_MEM8(0x0459) ++#define EBI_CS2_BASEADDR _SFR_MEM16(0x045A) ++#define EBI_CS3_CTRLA _SFR_MEM8(0x045C) ++#define EBI_CS3_CTRLB _SFR_MEM8(0x045D) ++#define EBI_CS3_BASEADDR _SFR_MEM16(0x045E) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWI - Two-Wire Interface */ ++#define TWID_CTRL _SFR_MEM8(0x0490) ++#define TWID_MASTER_CTRLA _SFR_MEM8(0x0491) ++#define TWID_MASTER_CTRLB _SFR_MEM8(0x0492) ++#define TWID_MASTER_CTRLC _SFR_MEM8(0x0493) ++#define TWID_MASTER_STATUS _SFR_MEM8(0x0494) ++#define TWID_MASTER_BAUD _SFR_MEM8(0x0495) ++#define TWID_MASTER_ADDR _SFR_MEM8(0x0496) ++#define TWID_MASTER_DATA _SFR_MEM8(0x0497) ++#define TWID_SLAVE_CTRLA _SFR_MEM8(0x0498) ++#define TWID_SLAVE_CTRLB _SFR_MEM8(0x0499) ++#define TWID_SLAVE_STATUS _SFR_MEM8(0x049A) ++#define TWID_SLAVE_ADDR _SFR_MEM8(0x049B) ++#define TWID_SLAVE_DATA _SFR_MEM8(0x049C) ++#define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIF_CTRL _SFR_MEM8(0x04B0) ++#define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1) ++#define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2) ++#define TWIF_MASTER_CTRLC _SFR_MEM8(0x04B3) ++#define TWIF_MASTER_STATUS _SFR_MEM8(0x04B4) ++#define TWIF_MASTER_BAUD _SFR_MEM8(0x04B5) ++#define TWIF_MASTER_ADDR _SFR_MEM8(0x04B6) ++#define TWIF_MASTER_DATA _SFR_MEM8(0x04B7) ++#define TWIF_SLAVE_CTRLA _SFR_MEM8(0x04B8) ++#define TWIF_SLAVE_CTRLB _SFR_MEM8(0x04B9) ++#define TWIF_SLAVE_STATUS _SFR_MEM8(0x04BA) ++#define TWIF_SLAVE_ADDR _SFR_MEM8(0x04BB) ++#define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC) ++#define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD) ++ ++/* USB - Universal Serial Bus */ ++#define USB_CTRLA _SFR_MEM8(0x04C0) ++#define USB_CTRLB _SFR_MEM8(0x04C1) ++#define USB_STATUS _SFR_MEM8(0x04C2) ++#define USB_ADDR _SFR_MEM8(0x04C3) ++#define USB_FIFOWP _SFR_MEM8(0x04C4) ++#define USB_FIFORP _SFR_MEM8(0x04C5) ++#define USB_EPPTR _SFR_MEM16(0x04C6) ++#define USB_INTCTRLA _SFR_MEM8(0x04C8) ++#define USB_INTCTRLB _SFR_MEM8(0x04C9) ++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) ++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) ++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) ++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) ++#define USB_CAL0 _SFR_MEM8(0x04FA) ++#define USB_CAL1 _SFR_MEM8(0x04FB) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_REMAP _SFR_MEM8(0x060E) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_REMAP _SFR_MEM8(0x062E) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_REMAP _SFR_MEM8(0x068E) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORT - I/O Ports */ ++#define PORTF_DIR _SFR_MEM8(0x06A0) ++#define PORTF_DIRSET _SFR_MEM8(0x06A1) ++#define PORTF_DIRCLR _SFR_MEM8(0x06A2) ++#define PORTF_DIRTGL _SFR_MEM8(0x06A3) ++#define PORTF_OUT _SFR_MEM8(0x06A4) ++#define PORTF_OUTSET _SFR_MEM8(0x06A5) ++#define PORTF_OUTCLR _SFR_MEM8(0x06A6) ++#define PORTF_OUTTGL _SFR_MEM8(0x06A7) ++#define PORTF_IN _SFR_MEM8(0x06A8) ++#define PORTF_INTCTRL _SFR_MEM8(0x06A9) ++#define PORTF_INT0MASK _SFR_MEM8(0x06AA) ++#define PORTF_INT1MASK _SFR_MEM8(0x06AB) ++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) ++#define PORTF_REMAP _SFR_MEM8(0x06AE) ++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) ++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) ++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) ++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) ++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) ++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) ++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) ++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) ++ ++/* PORT - I/O Ports */ ++#define PORTH_DIR _SFR_MEM8(0x06E0) ++#define PORTH_DIRSET _SFR_MEM8(0x06E1) ++#define PORTH_DIRCLR _SFR_MEM8(0x06E2) ++#define PORTH_DIRTGL _SFR_MEM8(0x06E3) ++#define PORTH_OUT _SFR_MEM8(0x06E4) ++#define PORTH_OUTSET _SFR_MEM8(0x06E5) ++#define PORTH_OUTCLR _SFR_MEM8(0x06E6) ++#define PORTH_OUTTGL _SFR_MEM8(0x06E7) ++#define PORTH_IN _SFR_MEM8(0x06E8) ++#define PORTH_INTCTRL _SFR_MEM8(0x06E9) ++#define PORTH_INT0MASK _SFR_MEM8(0x06EA) ++#define PORTH_INT1MASK _SFR_MEM8(0x06EB) ++#define PORTH_INTFLAGS _SFR_MEM8(0x06EC) ++#define PORTH_REMAP _SFR_MEM8(0x06EE) ++#define PORTH_PIN0CTRL _SFR_MEM8(0x06F0) ++#define PORTH_PIN1CTRL _SFR_MEM8(0x06F1) ++#define PORTH_PIN2CTRL _SFR_MEM8(0x06F2) ++#define PORTH_PIN3CTRL _SFR_MEM8(0x06F3) ++#define PORTH_PIN4CTRL _SFR_MEM8(0x06F4) ++#define PORTH_PIN5CTRL _SFR_MEM8(0x06F5) ++#define PORTH_PIN6CTRL _SFR_MEM8(0x06F6) ++#define PORTH_PIN7CTRL _SFR_MEM8(0x06F7) ++ ++/* PORT - I/O Ports */ ++#define PORTJ_DIR _SFR_MEM8(0x0700) ++#define PORTJ_DIRSET _SFR_MEM8(0x0701) ++#define PORTJ_DIRCLR _SFR_MEM8(0x0702) ++#define PORTJ_DIRTGL _SFR_MEM8(0x0703) ++#define PORTJ_OUT _SFR_MEM8(0x0704) ++#define PORTJ_OUTSET _SFR_MEM8(0x0705) ++#define PORTJ_OUTCLR _SFR_MEM8(0x0706) ++#define PORTJ_OUTTGL _SFR_MEM8(0x0707) ++#define PORTJ_IN _SFR_MEM8(0x0708) ++#define PORTJ_INTCTRL _SFR_MEM8(0x0709) ++#define PORTJ_INT0MASK _SFR_MEM8(0x070A) ++#define PORTJ_INT1MASK _SFR_MEM8(0x070B) ++#define PORTJ_INTFLAGS _SFR_MEM8(0x070C) ++#define PORTJ_REMAP _SFR_MEM8(0x070E) ++#define PORTJ_PIN0CTRL _SFR_MEM8(0x0710) ++#define PORTJ_PIN1CTRL _SFR_MEM8(0x0711) ++#define PORTJ_PIN2CTRL _SFR_MEM8(0x0712) ++#define PORTJ_PIN3CTRL _SFR_MEM8(0x0713) ++#define PORTJ_PIN4CTRL _SFR_MEM8(0x0714) ++#define PORTJ_PIN5CTRL _SFR_MEM8(0x0715) ++#define PORTJ_PIN6CTRL _SFR_MEM8(0x0716) ++#define PORTJ_PIN7CTRL _SFR_MEM8(0x0717) ++ ++/* PORT - I/O Ports */ ++#define PORTK_DIR _SFR_MEM8(0x0720) ++#define PORTK_DIRSET _SFR_MEM8(0x0721) ++#define PORTK_DIRCLR _SFR_MEM8(0x0722) ++#define PORTK_DIRTGL _SFR_MEM8(0x0723) ++#define PORTK_OUT _SFR_MEM8(0x0724) ++#define PORTK_OUTSET _SFR_MEM8(0x0725) ++#define PORTK_OUTCLR _SFR_MEM8(0x0726) ++#define PORTK_OUTTGL _SFR_MEM8(0x0727) ++#define PORTK_IN _SFR_MEM8(0x0728) ++#define PORTK_INTCTRL _SFR_MEM8(0x0729) ++#define PORTK_INT0MASK _SFR_MEM8(0x072A) ++#define PORTK_INT1MASK _SFR_MEM8(0x072B) ++#define PORTK_INTFLAGS _SFR_MEM8(0x072C) ++#define PORTK_REMAP _SFR_MEM8(0x072E) ++#define PORTK_PIN0CTRL _SFR_MEM8(0x0730) ++#define PORTK_PIN1CTRL _SFR_MEM8(0x0731) ++#define PORTK_PIN2CTRL _SFR_MEM8(0x0732) ++#define PORTK_PIN3CTRL _SFR_MEM8(0x0733) ++#define PORTK_PIN4CTRL _SFR_MEM8(0x0734) ++#define PORTK_PIN5CTRL _SFR_MEM8(0x0735) ++#define PORTK_PIN6CTRL _SFR_MEM8(0x0736) ++#define PORTK_PIN7CTRL _SFR_MEM8(0x0737) ++ ++/* PORT - I/O Ports */ ++#define PORTQ_DIR _SFR_MEM8(0x07C0) ++#define PORTQ_DIRSET _SFR_MEM8(0x07C1) ++#define PORTQ_DIRCLR _SFR_MEM8(0x07C2) ++#define PORTQ_DIRTGL _SFR_MEM8(0x07C3) ++#define PORTQ_OUT _SFR_MEM8(0x07C4) ++#define PORTQ_OUTSET _SFR_MEM8(0x07C5) ++#define PORTQ_OUTCLR _SFR_MEM8(0x07C6) ++#define PORTQ_OUTTGL _SFR_MEM8(0x07C7) ++#define PORTQ_IN _SFR_MEM8(0x07C8) ++#define PORTQ_INTCTRL _SFR_MEM8(0x07C9) ++#define PORTQ_INT0MASK _SFR_MEM8(0x07CA) ++#define PORTQ_INT1MASK _SFR_MEM8(0x07CB) ++#define PORTQ_INTFLAGS _SFR_MEM8(0x07CC) ++#define PORTQ_REMAP _SFR_MEM8(0x07CE) ++#define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0) ++#define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1) ++#define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2) ++#define PORTQ_PIN3CTRL _SFR_MEM8(0x07D3) ++#define PORTQ_PIN4CTRL _SFR_MEM8(0x07D4) ++#define PORTQ_PIN5CTRL _SFR_MEM8(0x07D5) ++#define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6) ++#define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCC2_CTRLA _SFR_MEM8(0x0800) ++#define TCC2_CTRLB _SFR_MEM8(0x0801) ++#define TCC2_CTRLC _SFR_MEM8(0x0802) ++#define TCC2_CTRLE _SFR_MEM8(0x0804) ++#define TCC2_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC2_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC2_CTRLF _SFR_MEM8(0x0809) ++#define TCC2_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC2_LCNT _SFR_MEM8(0x0820) ++#define TCC2_HCNT _SFR_MEM8(0x0821) ++#define TCC2_LPER _SFR_MEM8(0x0826) ++#define TCC2_HPER _SFR_MEM8(0x0827) ++#define TCC2_LCMPA _SFR_MEM8(0x0828) ++#define TCC2_HCMPA _SFR_MEM8(0x0829) ++#define TCC2_LCMPB _SFR_MEM8(0x082A) ++#define TCC2_HCMPB _SFR_MEM8(0x082B) ++#define TCC2_LCMPC _SFR_MEM8(0x082C) ++#define TCC2_HCMPC _SFR_MEM8(0x082D) ++#define TCC2_LCMPD _SFR_MEM8(0x082E) ++#define TCC2_HCMPD _SFR_MEM8(0x082F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_STATUSSET _SFR_MEM8(0x0885) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1_DATA _SFR_MEM8(0x08B0) ++#define USARTC1_STATUS _SFR_MEM8(0x08B1) ++#define USARTC1_CTRLA _SFR_MEM8(0x08B3) ++#define USARTC1_CTRLB _SFR_MEM8(0x08B4) ++#define USARTC1_CTRLC _SFR_MEM8(0x08B5) ++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) ++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCD2_CTRLA _SFR_MEM8(0x0900) ++#define TCD2_CTRLB _SFR_MEM8(0x0901) ++#define TCD2_CTRLC _SFR_MEM8(0x0902) ++#define TCD2_CTRLE _SFR_MEM8(0x0904) ++#define TCD2_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD2_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD2_CTRLF _SFR_MEM8(0x0909) ++#define TCD2_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD2_LCNT _SFR_MEM8(0x0920) ++#define TCD2_HCNT _SFR_MEM8(0x0921) ++#define TCD2_LPER _SFR_MEM8(0x0926) ++#define TCD2_HPER _SFR_MEM8(0x0927) ++#define TCD2_LCMPA _SFR_MEM8(0x0928) ++#define TCD2_HCMPA _SFR_MEM8(0x0929) ++#define TCD2_LCMPB _SFR_MEM8(0x092A) ++#define TCD2_HCMPB _SFR_MEM8(0x092B) ++#define TCD2_LCMPC _SFR_MEM8(0x092C) ++#define TCD2_HCMPC _SFR_MEM8(0x092D) ++#define TCD2_LCMPD _SFR_MEM8(0x092E) ++#define TCD2_HCMPD _SFR_MEM8(0x092F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCD1_CTRLA _SFR_MEM8(0x0940) ++#define TCD1_CTRLB _SFR_MEM8(0x0941) ++#define TCD1_CTRLC _SFR_MEM8(0x0942) ++#define TCD1_CTRLD _SFR_MEM8(0x0943) ++#define TCD1_CTRLE _SFR_MEM8(0x0944) ++#define TCD1_INTCTRLA _SFR_MEM8(0x0946) ++#define TCD1_INTCTRLB _SFR_MEM8(0x0947) ++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) ++#define TCD1_CTRLFSET _SFR_MEM8(0x0949) ++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) ++#define TCD1_CTRLGSET _SFR_MEM8(0x094B) ++#define TCD1_INTFLAGS _SFR_MEM8(0x094C) ++#define TCD1_TEMP _SFR_MEM8(0x094F) ++#define TCD1_CNT _SFR_MEM16(0x0960) ++#define TCD1_PER _SFR_MEM16(0x0966) ++#define TCD1_CCA _SFR_MEM16(0x0968) ++#define TCD1_CCB _SFR_MEM16(0x096A) ++#define TCD1_PERBUF _SFR_MEM16(0x0976) ++#define TCD1_CCABUF _SFR_MEM16(0x0978) ++#define TCD1_CCBBUF _SFR_MEM16(0x097A) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESD_CTRLA _SFR_MEM8(0x0990) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD1_DATA _SFR_MEM8(0x09B0) ++#define USARTD1_STATUS _SFR_MEM8(0x09B1) ++#define USARTD1_CTRLA _SFR_MEM8(0x09B3) ++#define USARTD1_CTRLB _SFR_MEM8(0x09B4) ++#define USARTD1_CTRLC _SFR_MEM8(0x09B5) ++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) ++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCE2_CTRLA _SFR_MEM8(0x0A00) ++#define TCE2_CTRLB _SFR_MEM8(0x0A01) ++#define TCE2_CTRLC _SFR_MEM8(0x0A02) ++#define TCE2_CTRLE _SFR_MEM8(0x0A04) ++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE2_CTRLF _SFR_MEM8(0x0A09) ++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE2_LCNT _SFR_MEM8(0x0A20) ++#define TCE2_HCNT _SFR_MEM8(0x0A21) ++#define TCE2_LPER _SFR_MEM8(0x0A26) ++#define TCE2_HPER _SFR_MEM8(0x0A27) ++#define TCE2_LCMPA _SFR_MEM8(0x0A28) ++#define TCE2_HCMPA _SFR_MEM8(0x0A29) ++#define TCE2_LCMPB _SFR_MEM8(0x0A2A) ++#define TCE2_HCMPB _SFR_MEM8(0x0A2B) ++#define TCE2_LCMPC _SFR_MEM8(0x0A2C) ++#define TCE2_HCMPC _SFR_MEM8(0x0A2D) ++#define TCE2_LCMPD _SFR_MEM8(0x0A2E) ++#define TCE2_HCMPD _SFR_MEM8(0x0A2F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCE1_CTRLA _SFR_MEM8(0x0A40) ++#define TCE1_CTRLB _SFR_MEM8(0x0A41) ++#define TCE1_CTRLC _SFR_MEM8(0x0A42) ++#define TCE1_CTRLD _SFR_MEM8(0x0A43) ++#define TCE1_CTRLE _SFR_MEM8(0x0A44) ++#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) ++#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) ++#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) ++#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) ++#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) ++#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) ++#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) ++#define TCE1_TEMP _SFR_MEM8(0x0A4F) ++#define TCE1_CNT _SFR_MEM16(0x0A60) ++#define TCE1_PER _SFR_MEM16(0x0A66) ++#define TCE1_CCA _SFR_MEM16(0x0A68) ++#define TCE1_CCB _SFR_MEM16(0x0A6A) ++#define TCE1_PERBUF _SFR_MEM16(0x0A76) ++#define TCE1_CCABUF _SFR_MEM16(0x0A78) ++#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXE_CTRL _SFR_MEM8(0x0A80) ++#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) ++#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) ++#define AWEXE_STATUS _SFR_MEM8(0x0A84) ++#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) ++#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) ++#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) ++#define AWEXE_DTLS _SFR_MEM8(0x0A88) ++#define AWEXE_DTHS _SFR_MEM8(0x0A89) ++#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) ++#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) ++#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESE_CTRLA _SFR_MEM8(0x0A90) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE1_DATA _SFR_MEM8(0x0AB0) ++#define USARTE1_STATUS _SFR_MEM8(0x0AB1) ++#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) ++#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) ++#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) ++#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) ++#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIE_CTRL _SFR_MEM8(0x0AC0) ++#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) ++#define SPIE_STATUS _SFR_MEM8(0x0AC2) ++#define SPIE_DATA _SFR_MEM8(0x0AC3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCF0_CTRLA _SFR_MEM8(0x0B00) ++#define TCF0_CTRLB _SFR_MEM8(0x0B01) ++#define TCF0_CTRLC _SFR_MEM8(0x0B02) ++#define TCF0_CTRLD _SFR_MEM8(0x0B03) ++#define TCF0_CTRLE _SFR_MEM8(0x0B04) ++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) ++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) ++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) ++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) ++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF0_TEMP _SFR_MEM8(0x0B0F) ++#define TCF0_CNT _SFR_MEM16(0x0B20) ++#define TCF0_PER _SFR_MEM16(0x0B26) ++#define TCF0_CCA _SFR_MEM16(0x0B28) ++#define TCF0_CCB _SFR_MEM16(0x0B2A) ++#define TCF0_CCC _SFR_MEM16(0x0B2C) ++#define TCF0_CCD _SFR_MEM16(0x0B2E) ++#define TCF0_PERBUF _SFR_MEM16(0x0B36) ++#define TCF0_CCABUF _SFR_MEM16(0x0B38) ++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) ++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) ++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCF2_CTRLA _SFR_MEM8(0x0B00) ++#define TCF2_CTRLB _SFR_MEM8(0x0B01) ++#define TCF2_CTRLC _SFR_MEM8(0x0B02) ++#define TCF2_CTRLE _SFR_MEM8(0x0B04) ++#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF2_CTRLF _SFR_MEM8(0x0B09) ++#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF2_LCNT _SFR_MEM8(0x0B20) ++#define TCF2_HCNT _SFR_MEM8(0x0B21) ++#define TCF2_LPER _SFR_MEM8(0x0B26) ++#define TCF2_HPER _SFR_MEM8(0x0B27) ++#define TCF2_LCMPA _SFR_MEM8(0x0B28) ++#define TCF2_HCMPA _SFR_MEM8(0x0B29) ++#define TCF2_LCMPB _SFR_MEM8(0x0B2A) ++#define TCF2_HCMPB _SFR_MEM8(0x0B2B) ++#define TCF2_LCMPC _SFR_MEM8(0x0B2C) ++#define TCF2_HCMPC _SFR_MEM8(0x0B2D) ++#define TCF2_LCMPD _SFR_MEM8(0x0B2E) ++#define TCF2_HCMPD _SFR_MEM8(0x0B2F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCF1_CTRLA _SFR_MEM8(0x0B40) ++#define TCF1_CTRLB _SFR_MEM8(0x0B41) ++#define TCF1_CTRLC _SFR_MEM8(0x0B42) ++#define TCF1_CTRLD _SFR_MEM8(0x0B43) ++#define TCF1_CTRLE _SFR_MEM8(0x0B44) ++#define TCF1_INTCTRLA _SFR_MEM8(0x0B46) ++#define TCF1_INTCTRLB _SFR_MEM8(0x0B47) ++#define TCF1_CTRLFCLR _SFR_MEM8(0x0B48) ++#define TCF1_CTRLFSET _SFR_MEM8(0x0B49) ++#define TCF1_CTRLGCLR _SFR_MEM8(0x0B4A) ++#define TCF1_CTRLGSET _SFR_MEM8(0x0B4B) ++#define TCF1_INTFLAGS _SFR_MEM8(0x0B4C) ++#define TCF1_TEMP _SFR_MEM8(0x0B4F) ++#define TCF1_CNT _SFR_MEM16(0x0B60) ++#define TCF1_PER _SFR_MEM16(0x0B66) ++#define TCF1_CCA _SFR_MEM16(0x0B68) ++#define TCF1_CCB _SFR_MEM16(0x0B6A) ++#define TCF1_PERBUF _SFR_MEM16(0x0B76) ++#define TCF1_CCABUF _SFR_MEM16(0x0B78) ++#define TCF1_CCBBUF _SFR_MEM16(0x0B7A) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESF_CTRLA _SFR_MEM8(0x0B90) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTF0_DATA _SFR_MEM8(0x0BA0) ++#define USARTF0_STATUS _SFR_MEM8(0x0BA1) ++#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) ++#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) ++#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) ++#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) ++#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTF1_DATA _SFR_MEM8(0x0BB0) ++#define USARTF1_STATUS _SFR_MEM8(0x0BB1) ++#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) ++#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) ++#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) ++#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) ++#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIF_CTRL _SFR_MEM8(0x0BC0) ++#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) ++#define SPIF_STATUS _SFR_MEM8(0x0BC2) ++#define SPIF_DATA _SFR_MEM8(0x0BC3) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* CLK.USBCTRL bit masks and bit positions */ ++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ ++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ ++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ ++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ ++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ ++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ ++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ ++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ ++ ++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ ++#define CLK_USBSRC_gp 1 /* Clock Source group position. */ ++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ ++ ++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_USB_bm 0x40 /* USB bit mask. */ ++#define PR_USB_bp 6 /* USB bit position. */ ++ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ ++#define PR_EBI_bp 3 /* External Bus Interface bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ ++#define PR_DAC_bp 2 /* Port A DAC bit position. */ ++ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPB bit masks and bit positions */ ++/* PR_DAC Predefined. */ ++/* PR_DAC Predefined. */ ++ ++/* PR_ADC Predefined. */ ++/* PR_ADC Predefined. */ ++ ++/* PR_AC Predefined. */ ++/* PR_AC Predefined. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ ++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ ++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ ++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ ++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ ++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ ++ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ ++#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ ++ ++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ ++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ ++ ++#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ ++#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ ++ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ ++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ ++ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ ++ ++/* PORTCFG.EBIOUT bit masks and bit positions */ ++#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ ++#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ ++#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ ++#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ ++#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ ++#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ ++ ++#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ ++#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ ++#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ ++#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ ++#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ ++#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ ++ ++/* PORTCFG.EVOUTSEL bit masks and bit positions */ ++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ ++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ ++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ ++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ ++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ ++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ ++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ ++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ ++ ++/* AES - AES Module */ ++/* AES.CTRL bit masks and bit positions */ ++#define AES_START_bm 0x80 /* Start/Run bit mask. */ ++#define AES_START_bp 7 /* Start/Run bit position. */ ++ ++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ ++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ ++ ++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ ++#define AES_RESET_bp 5 /* AES Software Reset bit position. */ ++ ++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ ++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ ++ ++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ ++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ ++ ++/* AES.STATUS bit masks and bit positions */ ++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ ++#define AES_ERROR_bp 7 /* AES Error bit position. */ ++ ++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ ++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ ++ ++/* AES.INTCTRL bit masks and bit positions */ ++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define AES_INTLVL_gp 0 /* Interrupt level group position. */ ++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* DMA - DMA Controller */ ++/* DMA_CH.CTRLA bit masks and bit positions */ ++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ ++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ ++ ++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ ++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ ++ ++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ ++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ ++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ ++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ ++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ ++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ ++ ++/* DMA_CH.CTRLB bit masks and bit positions */ ++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ ++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ ++ ++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ ++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ ++ ++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ ++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ ++ ++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ ++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ ++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ ++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ ++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ ++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ ++ ++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ ++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ ++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ ++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ ++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ ++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ ++ ++/* DMA_CH.ADDRCTRL bit masks and bit positions */ ++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ ++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ ++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ ++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ ++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ ++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ ++ ++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ ++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ ++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ ++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ ++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ ++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ ++ ++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ ++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ ++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ ++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ ++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ ++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ ++ ++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ ++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ ++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ ++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ ++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ ++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ ++ ++/* DMA_CH.TRIGSRC bit masks and bit positions */ ++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++/* DMA.CTRL bit masks and bit positions */ ++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define DMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define DMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ ++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ ++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ ++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ ++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ ++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ ++ ++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ ++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ ++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ ++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ ++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ ++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ ++ ++/* DMA.INTFLAGS bit masks and bit positions */ ++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++/* DMA.STATUS bit masks and bit positions */ ++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ ++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ ++ ++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ ++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ ++ ++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ ++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ ++ ++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ ++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ ++ ++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ ++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ ++ ++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ ++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ ++ ++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ ++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ ++ ++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ ++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH4MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH5MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH6MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH7MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM Predefined. */ ++/* EVSYS_QDIRM Predefined. */ ++ ++/* EVSYS_QDIEN Predefined. */ ++/* EVSYS_QDIEN Predefined. */ ++ ++/* EVSYS_QDEN Predefined. */ ++/* EVSYS_QDEN Predefined. */ ++ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH4CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM Predefined. */ ++/* EVSYS_QDIRM Predefined. */ ++ ++/* EVSYS_QDIEN Predefined. */ ++/* EVSYS_QDIEN Predefined. */ ++ ++/* EVSYS_QDEN Predefined. */ ++/* EVSYS_QDEN Predefined. */ ++ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH5CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH6CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH7CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ ++#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ ++#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ ++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ ++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ ++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ ++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ ++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ ++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ ++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ ++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ ++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ ++ ++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ ++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ ++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ ++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ ++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ ++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ ++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ ++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ ++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ ++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ ++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ ++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ ++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ ++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ ++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ ++ ++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ ++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ ++ ++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ ++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ ++ ++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ ++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ ++ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ ++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ ++#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ ++ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ ++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ ++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ ++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ ++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ ++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ ++ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ ++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ ++ ++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ ++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ ++ ++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ ++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ ++ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* DAC - Digital/Analog Converter */ ++/* DAC.CTRLA bit masks and bit positions */ ++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ ++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ ++ ++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ ++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ ++ ++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ ++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ ++ ++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ ++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ ++ ++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define DAC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* DAC.CTRLB bit masks and bit positions */ ++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ ++#define DAC_CHSEL_gp 5 /* Channel Select group position. */ ++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ ++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ ++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ ++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ ++ ++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ ++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ ++ ++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ ++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ ++ ++/* DAC.CTRLC bit masks and bit positions */ ++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ ++#define DAC_REFSEL_gp 3 /* Reference Select group position. */ ++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ ++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ ++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ ++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ ++ ++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ ++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ ++ ++/* DAC.EVCTRL bit masks and bit positions */ ++#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ ++#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ ++ ++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ ++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ ++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ ++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ ++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ ++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ ++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ ++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ ++ ++/* DAC.STATUS bit masks and bit positions */ ++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ ++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ ++ ++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ ++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ ++ ++/* DAC.CH0GAINCAL bit masks and bit positions */ ++#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH0OFFSETCAL bit masks and bit positions */ ++#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* DAC.CH1GAINCAL bit masks and bit positions */ ++#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH1OFFSETCAL bit masks and bit positions */ ++#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ ++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HSMODE Predefined. */ ++/* AC_HSMODE Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* RTC - Real-Time Counter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* EBI - External Bus Interface */ ++/* EBI_CS.CTRLA bit masks and bit positions */ ++#define EBI_CS_ASPACE_gm 0x7C /* Address Space group mask. */ ++#define EBI_CS_ASPACE_gp 2 /* Address Space group position. */ ++#define EBI_CS_ASPACE0_bm (1<<2) /* Address Space bit 0 mask. */ ++#define EBI_CS_ASPACE0_bp 2 /* Address Space bit 0 position. */ ++#define EBI_CS_ASPACE1_bm (1<<3) /* Address Space bit 1 mask. */ ++#define EBI_CS_ASPACE1_bp 3 /* Address Space bit 1 position. */ ++#define EBI_CS_ASPACE2_bm (1<<4) /* Address Space bit 2 mask. */ ++#define EBI_CS_ASPACE2_bp 4 /* Address Space bit 2 position. */ ++#define EBI_CS_ASPACE3_bm (1<<5) /* Address Space bit 3 mask. */ ++#define EBI_CS_ASPACE3_bp 5 /* Address Space bit 3 position. */ ++#define EBI_CS_ASPACE4_bm (1<<6) /* Address Space bit 4 mask. */ ++#define EBI_CS_ASPACE4_bp 6 /* Address Space bit 4 position. */ ++ ++#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ ++#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ ++#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ ++#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ ++#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ ++#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ ++ ++/* EBI_CS.CTRLB bit masks and bit positions */ ++#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ ++#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ ++#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ ++#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ ++#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ ++#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ ++#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ ++#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ ++ ++#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ ++#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ ++ ++#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ ++#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ ++ ++#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ ++#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ ++#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ ++#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ ++#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ ++#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ ++ ++/* EBI.CTRL bit masks and bit positions */ ++#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ ++#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ ++#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ ++#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ ++#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ ++#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ ++ ++#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ ++#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ ++#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ ++#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ ++#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ ++#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ ++ ++#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ ++#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ ++#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ ++#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ ++#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ ++#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ ++ ++#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ ++#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ ++#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ ++#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ ++#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ ++#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ ++ ++/* EBI.SDRAMCTRLA bit masks and bit positions */ ++#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ ++#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ ++ ++#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ ++#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ ++ ++#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ ++#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ ++#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ ++#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ ++#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ ++#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ ++ ++/* EBI.SDRAMCTRLB bit masks and bit positions */ ++#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ ++#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ ++#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ ++#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ ++#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ ++#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ ++ ++#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ ++#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ ++#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ ++#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ ++#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ ++#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ ++#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ ++#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ ++ ++#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ ++#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ ++#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ ++#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ ++#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ ++#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ ++#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ ++#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ ++ ++/* EBI.SDRAMCTRLC bit masks and bit positions */ ++#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ ++#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ ++#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ ++#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ ++#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ ++#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ ++ ++#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ ++#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ ++#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ ++#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ ++#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ ++#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ ++#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ ++#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ ++ ++#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ ++#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ ++#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ ++#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ ++#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ ++#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ ++#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ ++#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Tisdahmeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Tisdahmeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Tisdahmeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Tisdahmeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Tisdahmeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Tisdahmeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* USB - USB */ ++/* USB_EP.STATUS bit masks and bit positions */ ++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ ++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ ++ ++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ ++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ ++ ++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ ++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ ++ ++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ ++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ ++ ++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ ++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ ++ ++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ ++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ ++ ++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ ++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ ++ ++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ ++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ ++ ++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ ++ ++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ ++ ++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ ++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ ++ ++/* USB_EP.CTRL bit masks and bit positions */ ++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ ++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ ++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ ++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ ++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ ++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ ++ ++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ ++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ ++ ++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ ++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ ++ ++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ ++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ ++ ++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ ++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ ++ ++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ ++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ ++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ ++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ ++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ ++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ ++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ ++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ ++ ++/* USB_EP.CNT bit masks and bit positions */ ++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ ++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ ++ ++/* USB.CTRLA bit masks and bit positions */ ++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ ++#define USB_ENABLE_bp 7 /* USB Enable bit position. */ ++ ++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ ++#define USB_SPEED_bp 6 /* Speed Select bit position. */ ++ ++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ ++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ ++ ++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ ++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ ++ ++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ ++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ ++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ ++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ ++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ ++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ ++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ ++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ ++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ ++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ ++ ++/* USB.CTRLB bit masks and bit positions */ ++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ ++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ ++ ++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ ++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ ++ ++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ ++#define USB_GNACK_bp 1 /* Global NACK bit position. */ ++ ++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ ++#define USB_ATTACH_bp 0 /* Attach bit position. */ ++ ++/* USB.STATUS bit masks and bit positions */ ++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ ++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ ++ ++#define USB_RESUME_bm 0x04 /* Resume bit mask. */ ++#define USB_RESUME_bp 2 /* Resume bit position. */ ++ ++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ ++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ ++ ++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ ++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ ++ ++/* USB.ADDR bit masks and bit positions */ ++#define USB_ADDR_gm 0x7F /* Device Address group mask. */ ++#define USB_ADDR_gp 0 /* Device Address group position. */ ++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ ++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ ++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ ++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ ++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ ++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ ++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ ++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ ++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ ++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ ++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ ++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ ++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ ++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ ++ ++/* USB.FIFOWP bit masks and bit positions */ ++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ ++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ ++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ ++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ ++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ ++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ ++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ ++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ ++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ ++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ ++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ ++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ ++ ++/* USB.FIFORP bit masks and bit positions */ ++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ ++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ ++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ ++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ ++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ ++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ ++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ ++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ ++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ ++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ ++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ ++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ ++ ++/* USB.INTCTRLA bit masks and bit positions */ ++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ ++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ ++ ++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ ++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ ++ ++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ ++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ ++ ++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ ++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ ++ ++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* USB.INTCTRLB bit masks and bit positions */ ++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ ++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ ++ ++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ ++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ ++ ++/* USB.INTFLAGSACLR bit masks and bit positions */ ++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ ++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ ++ ++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ ++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ ++ ++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ ++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ ++ ++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ ++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ ++ ++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ ++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ ++ ++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ ++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ ++ ++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ ++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ ++ ++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ ++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSASET bit masks and bit positions */ ++/* USB_SOFIF Predefined. */ ++/* USB_SOFIF Predefined. */ ++ ++/* USB_SUSPENDIF Predefined. */ ++/* USB_SUSPENDIF Predefined. */ ++ ++/* USB_RESUMEIF Predefined. */ ++/* USB_RESUMEIF Predefined. */ ++ ++/* USB_RSTIF Predefined. */ ++/* USB_RSTIF Predefined. */ ++ ++/* USB_CRCIF Predefined. */ ++/* USB_CRCIF Predefined. */ ++ ++/* USB_UNFIF Predefined. */ ++/* USB_UNFIF Predefined. */ ++ ++/* USB_OVFIF Predefined. */ ++/* USB_OVFIF Predefined. */ ++ ++/* USB_STALLIF Predefined. */ ++/* USB_STALLIF Predefined. */ ++ ++/* USB.INTFLAGSBCLR bit masks and bit positions */ ++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ ++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ ++ ++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ ++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSBSET bit masks and bit positions */ ++/* USB_TRNIF Predefined. */ ++/* USB_TRNIF Predefined. */ ++ ++/* USB_SETUPIF Predefined. */ ++/* USB_SETUPIF Predefined. */ ++ ++/* PORT - I/O Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_SPI_bm 0x20 /* SPI bit mask. */ ++#define PORT_SPI_bp 5 /* SPI bit position. */ ++ ++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ ++#define PORT_USART0_bp 4 /* USART0 bit position. */ ++ ++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ ++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ ++ ++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ ++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ ++ ++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ ++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ ++ ++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ ++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD Predefined. */ ++/* TC0_CMD Predefined. */ ++ ++/* TC0_LUPD Predefined. */ ++/* TC0_LUPD Predefined. */ ++ ++/* TC0_DIR Predefined. */ ++/* TC0_DIR Predefined. */ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV Predefined. */ ++/* TC0_CCDBV Predefined. */ ++ ++/* TC0_CCCBV Predefined. */ ++/* TC0_CCCBV Predefined. */ ++ ++/* TC0_CCBBV Predefined. */ ++/* TC0_CCBBV Predefined. */ ++ ++/* TC0_CCABV Predefined. */ ++/* TC0_CCABV Predefined. */ ++ ++/* TC0_PERBV Predefined. */ ++/* TC0_PERBV Predefined. */ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD Predefined. */ ++/* TC1_CMD Predefined. */ ++ ++/* TC1_LUPD Predefined. */ ++/* TC1_LUPD Predefined. */ ++ ++/* TC1_DIR Predefined. */ ++/* TC1_DIR Predefined. */ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV Predefined. */ ++/* TC1_CCBBV Predefined. */ ++ ++/* TC1_CCABV Predefined. */ ++/* TC1_CCABV Predefined. */ ++ ++/* TC1_PERBV Predefined. */ ++/* TC1_PERBV Predefined. */ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++/* TC2.CTRLA bit masks and bit positions */ ++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC2.CTRLB bit masks and bit positions */ ++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ ++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ ++ ++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ ++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ ++ ++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ ++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ ++ ++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ ++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ ++ ++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ ++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ ++ ++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ ++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ ++ ++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ ++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ ++ ++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ ++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ ++ ++/* TC2.CTRLC bit masks and bit positions */ ++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ ++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ ++ ++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ ++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ ++ ++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ ++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ ++ ++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ ++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ ++ ++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ ++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ ++ ++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ ++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ ++ ++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ ++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ ++ ++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ ++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ ++ ++/* TC2.CTRLE bit masks and bit positions */ ++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC2.INTCTRLA bit masks and bit positions */ ++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ ++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ ++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ ++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ ++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ ++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ ++ ++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ ++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ ++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ ++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ ++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ ++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ ++ ++/* TC2.INTCTRLB bit masks and bit positions */ ++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ ++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ ++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ ++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ ++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ ++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ ++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ ++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ ++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ ++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ ++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ ++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ ++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ ++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ ++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ ++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ ++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ ++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ ++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ ++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ ++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ ++ ++/* TC2.CTRLF bit masks and bit positions */ ++#define TC2_CMD_gm 0x0C /* Command group mask. */ ++#define TC2_CMD_gp 2 /* Command group position. */ ++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC2_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC2_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ ++#define TC2_CMDEN_gp 0 /* Command Enable group position. */ ++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ ++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ ++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ ++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ ++ ++/* TC2.INTFLAGS bit masks and bit positions */ ++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ ++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ ++ ++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ ++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ ++ ++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ ++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ ++ ++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ ++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ ++ ++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ ++ ++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ ++ ++/* AWEX - Timer/Counter Advanced Waveform Extension */ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++/* AWEX.STATUSSET bit masks and bit positions */ ++/* AWEX_FDF Predefined. */ ++/* AWEX_FDF Predefined. */ ++ ++/* AWEX_DTHSBUFV Predefined. */ ++/* AWEX_DTHSBUFV Predefined. */ ++ ++/* AWEX_DTLSBUFV Predefined. */ ++/* AWEX_DTLSBUFV Predefined. */ ++ ++/* HIRES - Timer/Counter High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ ++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ ++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ ++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ ++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ ++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ ++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ ++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ ++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ ++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ ++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ ++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ ++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ ++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ ++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ ++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ ++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ ++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ ++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ ++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ ++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* LOCKBIT - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* DMA interrupt vectors */ ++#define DMA_CH0_vect_num 6 ++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ ++#define DMA_CH1_vect_num 7 ++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ ++#define DMA_CH2_vect_num 8 ++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ ++#define DMA_CH3_vect_num 9 ++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LUNF_vect_num 14 ++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_HUNF_vect_num 15 ++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPA_vect_num 16 ++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPB_vect_num 17 ++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPC_vect_num 18 ++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPD_vect_num 19 ++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* USARTC1 interrupt vectors */ ++#define USARTC1_RXC_vect_num 28 ++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ ++#define USARTC1_DRE_vect_num 29 ++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ ++#define USARTC1_TXC_vect_num 30 ++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ ++ ++/* AES interrupt vectors */ ++#define AES_INT_vect_num 31 ++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* ACB interrupt vectors */ ++#define ACB_AC0_vect_num 36 ++#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ ++#define ACB_AC1_vect_num 37 ++#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ ++#define ACB_ACW_vect_num 38 ++#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ ++ ++/* ADCB interrupt vectors */ ++#define ADCB_CH0_vect_num 39 ++#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ ++#define ADCB_CH1_vect_num 40 ++#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ ++#define ADCB_CH2_vect_num 41 ++#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ ++#define ADCB_CH3_vect_num 42 ++#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LUNF_vect_num 47 ++#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_HUNF_vect_num 48 ++#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPA_vect_num 49 ++#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPB_vect_num 50 ++#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPC_vect_num 51 ++#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPD_vect_num 52 ++#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ ++ ++/* TCE1 interrupt vectors */ ++#define TCE1_OVF_vect_num 53 ++#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ ++#define TCE1_ERR_vect_num 54 ++#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ ++#define TCE1_CCA_vect_num 55 ++#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ ++#define TCE1_CCB_vect_num 56 ++#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ ++ ++/* SPIE interrupt vectors */ ++#define SPIE_INT_vect_num 57 ++#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* USARTE1 interrupt vectors */ ++#define USARTE1_RXC_vect_num 61 ++#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ ++#define USARTE1_DRE_vect_num 62 ++#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ ++#define USARTE1_TXC_vect_num 63 ++#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++#define ADCA_CH1_vect_num 72 ++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ ++#define ADCA_CH2_vect_num 73 ++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ ++#define ADCA_CH3_vect_num 74 ++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ ++ ++/* TWID interrupt vectors */ ++#define TWID_TWIS_vect_num 75 ++#define TWID_TWIS_vect _VECTOR(75) /* TWI Slave Interrupt */ ++#define TWID_TWIM_vect_num 76 ++#define TWID_TWIM_vect _VECTOR(76) /* TWI Master Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LUNF_vect_num 77 ++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_HUNF_vect_num 78 ++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPA_vect_num 79 ++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPB_vect_num 80 ++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPC_vect_num 81 ++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPD_vect_num 82 ++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ ++ ++/* TCD1 interrupt vectors */ ++#define TCD1_OVF_vect_num 83 ++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ ++#define TCD1_ERR_vect_num 84 ++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ ++#define TCD1_CCA_vect_num 85 ++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ ++#define TCD1_CCB_vect_num 86 ++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* USARTD1 interrupt vectors */ ++#define USARTD1_RXC_vect_num 91 ++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ ++#define USARTD1_DRE_vect_num 92 ++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ ++#define USARTD1_TXC_vect_num 93 ++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ ++ ++/* PORTQ interrupt vectors */ ++#define PORTQ_INT0_vect_num 94 ++#define PORTQ_INT0_vect _VECTOR(94) /* External Interrupt 0 */ ++#define PORTQ_INT1_vect_num 95 ++#define PORTQ_INT1_vect _VECTOR(95) /* External Interrupt 1 */ ++ ++/* PORTH interrupt vectors */ ++#define PORTH_INT0_vect_num 96 ++#define PORTH_INT0_vect _VECTOR(96) /* External Interrupt 0 */ ++#define PORTH_INT1_vect_num 97 ++#define PORTH_INT1_vect _VECTOR(97) /* External Interrupt 1 */ ++ ++/* PORTJ interrupt vectors */ ++#define PORTJ_INT0_vect_num 98 ++#define PORTJ_INT0_vect _VECTOR(98) /* External Interrupt 0 */ ++#define PORTJ_INT1_vect_num 99 ++#define PORTJ_INT1_vect _VECTOR(99) /* External Interrupt 1 */ ++ ++/* PORTK interrupt vectors */ ++#define PORTK_INT0_vect_num 100 ++#define PORTK_INT0_vect _VECTOR(100) /* External Interrupt 0 */ ++#define PORTK_INT1_vect_num 101 ++#define PORTK_INT1_vect _VECTOR(101) /* External Interrupt 1 */ ++ ++/* PORTF interrupt vectors */ ++#define PORTF_INT0_vect_num 104 ++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ ++#define PORTF_INT1_vect_num 105 ++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ ++ ++/* TWIF interrupt vectors */ ++#define TWIF_TWIS_vect_num 106 ++#define TWIF_TWIS_vect _VECTOR(106) /* TWI Slave Interrupt */ ++#define TWIF_TWIM_vect_num 107 ++#define TWIF_TWIM_vect _VECTOR(107) /* TWI Master Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_OVF_vect_num 108 ++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LUNF_vect_num 108 ++#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_ERR_vect_num 109 ++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_HUNF_vect_num 109 ++#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCA_vect_num 110 ++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPA_vect_num 110 ++#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCB_vect_num 111 ++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPB_vect_num 111 ++#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCC_vect_num 112 ++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPC_vect_num 112 ++#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCD_vect_num 113 ++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPD_vect_num 113 ++#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ ++ ++/* TCF1 interrupt vectors */ ++#define TCF1_OVF_vect_num 114 ++#define TCF1_OVF_vect _VECTOR(114) /* Overflow Interrupt */ ++#define TCF1_ERR_vect_num 115 ++#define TCF1_ERR_vect _VECTOR(115) /* Error Interrupt */ ++#define TCF1_CCA_vect_num 116 ++#define TCF1_CCA_vect _VECTOR(116) /* Compare or Capture A Interrupt */ ++#define TCF1_CCB_vect_num 117 ++#define TCF1_CCB_vect _VECTOR(117) /* Compare or Capture B Interrupt */ ++ ++/* SPIF interrupt vectors */ ++#define SPIF_INT_vect_num 118 ++#define SPIF_INT_vect _VECTOR(118) /* SPI Interrupt */ ++ ++/* USARTF0 interrupt vectors */ ++#define USARTF0_RXC_vect_num 119 ++#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ ++#define USARTF0_DRE_vect_num 120 ++#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ ++#define USARTF0_TXC_vect_num 121 ++#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ ++ ++/* USARTF1 interrupt vectors */ ++#define USARTF1_RXC_vect_num 122 ++#define USARTF1_RXC_vect _VECTOR(122) /* Reception Complete Interrupt */ ++#define USARTF1_DRE_vect_num 123 ++#define USARTF1_DRE_vect _VECTOR(123) /* Data Register Empty Interrupt */ ++#define USARTF1_TXC_vect_num 124 ++#define USARTF1_TXC_vect _VECTOR(124) /* Transmission Complete Interrupt */ ++ ++/* USB interrupt vectors */ ++#define USB_BUSEVENT_vect_num 125 ++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ ++#define USB_TRNCOMPL_vect_num 126 ++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (127 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (69632) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (65536) ++#define APP_SECTION_PAGE_SIZE (256) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0xF000) ++#define APPTABLE_SECTION_SIZE (4096) ++#define APPTABLE_SECTION_PAGE_SIZE (256) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x10000) ++#define BOOT_SECTION_SIZE (4096) ++#define BOOT_SECTION_PAGE_SIZE (256) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (16777216) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (2048) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (4096) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (2048) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (6) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (256) ++#define USER_SIGNATURES_PAGE_SIZE (256) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (64) ++#define PROD_SIGNATURES_PAGE_SIZE (256) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 256 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 */ ++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ ++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ ++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ ++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ ++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ ++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ ++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ ++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ ++#define FUSE0_DEFAULT (0xFF) ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x4E ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA64A1U_H_INCLUDED */ ++ +diff --git a/include/avr/iox64a3.h b/include/avr/iox64a3.h +index 336fe76..3a24466 100644 +--- a/include/avr/iox64a3.h ++++ b/include/avr/iox64a3.h +@@ -1,6917 +1,6917 @@ +-/* Copyright (c) 2009-2010 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iox64a3.h 2200 2010-12-14 04:24:24Z arcanum $ */ +- +-/* avr/iox64a3.h - definitions for ATxmega64A3 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iox64a3.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATxmega64A3_H_ +-#define _AVR_ATxmega64A3_H_ 1 +- +- +-/* Ungrouped common registers */ +-#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +-#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +-#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +-#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +-#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +-#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +-#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +-#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +-#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +-#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +-#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +-#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +-#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +-#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +-#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +-#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +- +-/* Deprecated */ +-#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +-#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +-#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +-#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +-#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +-#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +-#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +-#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +-#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +-#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +-#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +-#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +-#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +-#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +-#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +-#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +- +-#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +-#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +-#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +-#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +-#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +-#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +-#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +-#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +-#define SREG _SFR_MEM8(0x003F) /* Status Register */ +- +- +-/* C Language Only */ +-#if !defined (__ASSEMBLER__) +- +-#include +- +-typedef volatile uint8_t register8_t; +-typedef volatile uint16_t register16_t; +-typedef volatile uint32_t register32_t; +- +- +-#ifdef _WORDREGISTER +-#undef _WORDREGISTER +-#endif +-#define _WORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register16_t regname; \ +- struct \ +- { \ +- register8_t regname ## L; \ +- register8_t regname ## H; \ +- }; \ +- } +- +-#ifdef _DWORDREGISTER +-#undef _DWORDREGISTER +-#endif +-#define _DWORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register32_t regname; \ +- struct \ +- { \ +- register8_t regname ## 0; \ +- register8_t regname ## 1; \ +- register8_t regname ## 2; \ +- register8_t regname ## 3; \ +- }; \ +- } +- +- +-/* +-========================================================================== +-IO Module Structures +-========================================================================== +-*/ +- +- +-/* +--------------------------------------------------------------------------- +-XOCD - On-Chip Debug System +--------------------------------------------------------------------------- +-*/ +- +-/* On-Chip Debug System */ +-typedef struct OCD_struct +-{ +- register8_t OCDR0; /* OCD Register 0 */ +- register8_t OCDR1; /* OCD Register 1 */ +-} OCD_t; +- +- +-/* CCP signatures */ +-typedef enum CCP_enum +-{ +- CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ +- CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +-} CCP_t; +- +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Clock System */ +-typedef struct CLK_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t PSCTRL; /* Prescaler Control Register */ +- register8_t LOCK; /* Lock register */ +- register8_t RTCCTRL; /* RTC Control Register */ +-} CLK_t; +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Power Reduction */ +-typedef struct PR_struct +-{ +- register8_t PRGEN; /* General Power Reduction */ +- register8_t PRPA; /* Power Reduction Port A */ - register8_t PRPB; /* Power Reduction Port B */ -+ register8_t reserved_0x02; - register8_t PRPC; /* Power Reduction Port C */ - register8_t PRPD; /* Power Reduction Port D */ - register8_t PRPE; /* Power Reduction Port E */ -@@ -416,6 +416,46 @@ typedef struct PMIC_struct - - /* - -------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ -+ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ -+ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ -+ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- - EVSYS - Event System - -------------------------------------------------------------------------- - */ -@@ -1005,6 +1045,15 @@ typedef struct ADC_struct - ADC_CH_t CH0; /* ADC Channel 0 */ - } ADC_t; - -+/* Current Limitation */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 225ksps max sampling rate */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 75ksps max sampling rate */ -+} ADC_CURRLIMIT_t; -+ - /* Positive input multiplexer selection */ - typedef enum ADC_CH_MUXPOS_enum - { -@@ -1059,6 +1108,7 @@ typedef enum ADC_CH_GAIN_enum - ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ - ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ - ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ - } ADC_CH_GAIN_t; - - /* Conversion result resolution */ -@@ -2180,6 +2230,7 @@ IO Module Instances. Mapped to memory. - #define MCU (*(MCU_t *) 0x0090) /* MCU Control */ - #define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ - #define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ - #define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ - #define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ - #define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ -@@ -2188,6 +2239,7 @@ IO Module Instances. Mapped to memory. - #define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ - #define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ - #define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ - #define PORTA (*(PORT_t *) 0x0600) /* Port A */ - #define PORTB (*(PORT_t *) 0x0620) /* Port B */ - #define PORTC (*(PORT_t *) 0x0640) /* Port C */ -@@ -2311,7 +2363,6 @@ IO Module Instances. Mapped to memory. - /* PR - Power Reduction */ - #define PR_PRGEN _SFR_MEM8(0x0070) - #define PR_PRPA _SFR_MEM8(0x0071) +- register8_t PRPC; /* Power Reduction Port C */ +- register8_t PRPD; /* Power Reduction Port D */ +- register8_t PRPE; /* Power Reduction Port E */ +- register8_t PRPF; /* Power Reduction Port F */ +-} PR_t; +- +-/* System Clock Selection */ +-typedef enum CLK_SCLKSEL_enum +-{ +- CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ +- CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ +- CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ +- CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ +- CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +-} CLK_SCLKSEL_t; +- +-/* Prescaler A Division Factor */ +-typedef enum CLK_PSADIV_enum +-{ +- CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ +- CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ +- CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ +- CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ +- CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ +- CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ +- CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ +- CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ +- CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ +- CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +-} CLK_PSADIV_t; +- +-/* Prescaler B and C Division Factor */ +-typedef enum CLK_PSBCDIV_enum +-{ +- CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ +- CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ +- CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ +- CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +-} CLK_PSBCDIV_t; +- +-/* RTC Clock Source */ +-typedef enum CLK_RTCSRC_enum +-{ +- CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ +- CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ +- CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ +- CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +-} CLK_RTCSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-SLEEP - Sleep Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Sleep Controller */ +-typedef struct SLEEP_struct +-{ +- register8_t CTRL; /* Control Register */ +-} SLEEP_t; +- +-/* Sleep Mode */ +-typedef enum SLEEP_SMODE_enum +-{ +- SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ +- SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +- SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ +- SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ +- SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +-} SLEEP_SMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-OSC - Oscillator +--------------------------------------------------------------------------- +-*/ +- +-/* Oscillator */ +-typedef struct OSC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t XOSCCTRL; /* External Oscillator Control Register */ +- register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ +- register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ +- register8_t PLLCTRL; /* PLL Control REgister */ +- register8_t DFLLCTRL; /* DFLL Control Register */ +-} OSC_t; +- +-/* Oscillator Frequency Range */ +-typedef enum OSC_FRQRANGE_enum +-{ +- OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ +- OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ +- OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ +- OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +-} OSC_FRQRANGE_t; +- +-/* External Oscillator Selection and Startup Time */ +-typedef enum OSC_XOSCSEL_enum +-{ +- OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ +- OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ +- OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ +- OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ +- OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +-} OSC_XOSCSEL_t; +- +-/* PLL Clock Source */ +-typedef enum OSC_PLLSRC_enum +-{ +- OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ +- OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ +- OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +-} OSC_PLLSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-DFLL - DFLL +--------------------------------------------------------------------------- +-*/ +- +-/* DFLL */ +-typedef struct DFLL_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t CALA; /* Calibration Register A */ +- register8_t CALB; /* Calibration Register B */ +- register8_t COMP0; /* Oscillator Compare Register 0 */ +- register8_t COMP1; /* Oscillator Compare Register 1 */ +- register8_t COMP2; /* Oscillator Compare Register 2 */ +- register8_t reserved_0x07; +-} DFLL_t; +- +- +-/* +--------------------------------------------------------------------------- +-RST - Reset +--------------------------------------------------------------------------- +-*/ +- +-/* Reset */ +-typedef struct RST_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t CTRL; /* Control Register */ +-} RST_t; +- +- +-/* +--------------------------------------------------------------------------- +-WDT - Watch-Dog Timer +--------------------------------------------------------------------------- +-*/ +- +-/* Watch-Dog Timer */ +-typedef struct WDT_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t WINCTRL; /* Windowed Mode Control */ +- register8_t STATUS; /* Status */ +-} WDT_t; +- +-/* Period setting */ +-typedef enum WDT_PER_enum +-{ +- WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ +- WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ +- WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ +- WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_PER_t; +- +-/* Closed window period */ +-typedef enum WDT_WPER_enum +-{ +- WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ +- WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ +- WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ +- WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_WPER_t; +- +- +-/* +--------------------------------------------------------------------------- +-MCU - MCU Control +--------------------------------------------------------------------------- +-*/ +- +-/* MCU Control */ +-typedef struct MCU_struct +-{ +- register8_t DEVID0; /* Device ID byte 0 */ +- register8_t DEVID1; /* Device ID byte 1 */ +- register8_t DEVID2; /* Device ID byte 2 */ +- register8_t REVID; /* Revision ID */ +- register8_t JTAGUID; /* JTAG User ID */ +- register8_t reserved_0x05; +- register8_t MCUCR; /* MCU Control */ +- register8_t reserved_0x07; +- register8_t EVSYSLOCK; /* Event System Lock */ +- register8_t AWEXLOCK; /* AWEX Lock */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +-} MCU_t; +- +- +-/* +--------------------------------------------------------------------------- +-PMIC - Programmable Multi-level Interrupt Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Programmable Multi-level Interrupt Controller */ +-typedef struct PMIC_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t INTPRI; /* Interrupt Priority */ +- register8_t CTRL; /* Control Register */ +-} PMIC_t; +- +- +-/* +--------------------------------------------------------------------------- +-DMA - DMA Controller +--------------------------------------------------------------------------- +-*/ +- +-/* DMA Channel */ +-typedef struct DMA_CH_struct +-{ +- register8_t CTRLA; /* Channel Control */ +- register8_t CTRLB; /* Channel Control */ +- register8_t ADDRCTRL; /* Address Control */ +- register8_t TRIGSRC; /* Channel Trigger Source */ +- _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ +- register8_t REPCNT; /* Channel Repeat Count */ +- register8_t reserved_0x07; +- register8_t SRCADDR0; /* Channel Source Address 0 */ +- register8_t SRCADDR1; /* Channel Source Address 1 */ +- register8_t SRCADDR2; /* Channel Source Address 2 */ +- register8_t reserved_0x0B; +- register8_t DESTADDR0; /* Channel Destination Address 0 */ +- register8_t DESTADDR1; /* Channel Destination Address 1 */ +- register8_t DESTADDR2; /* Channel Destination Address 2 */ +- register8_t reserved_0x0F; +-} DMA_CH_t; +- +-/* +--------------------------------------------------------------------------- +-DMA - DMA Controller +--------------------------------------------------------------------------- +-*/ +- +-/* DMA Controller */ +-typedef struct DMA_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t reserved_0x01; +- register8_t reserved_0x02; +- register8_t INTFLAGS; /* Transfer Interrupt Status */ +- register8_t STATUS; /* Status */ +- register8_t reserved_0x05; +- _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- DMA_CH_t CH0; /* DMA Channel 0 */ +- DMA_CH_t CH1; /* DMA Channel 1 */ +- DMA_CH_t CH2; /* DMA Channel 2 */ +- DMA_CH_t CH3; /* DMA Channel 3 */ +-} DMA_t; +- +-/* Burst mode */ +-typedef enum DMA_CH_BURSTLEN_enum +-{ +- DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ +- DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ +- DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ +- DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ +-} DMA_CH_BURSTLEN_t; +- +-/* Source address reload mode */ +-typedef enum DMA_CH_SRCRELOAD_enum +-{ +- DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ +- DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ +- DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ +- DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ +-} DMA_CH_SRCRELOAD_t; +- +-/* Source addressing mode */ +-typedef enum DMA_CH_SRCDIR_enum +-{ +- DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ +- DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ +- DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ +-} DMA_CH_SRCDIR_t; +- +-/* Destination adress reload mode */ +-typedef enum DMA_CH_DESTRELOAD_enum +-{ +- DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ +- DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ +- DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ +- DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ +-} DMA_CH_DESTRELOAD_t; +- +-/* Destination adressing mode */ +-typedef enum DMA_CH_DESTDIR_enum +-{ +- DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ +- DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ +- DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ +-} DMA_CH_DESTDIR_t; +- +-/* Transfer trigger source */ +-typedef enum DMA_CH_TRIGSRC_enum +-{ +- DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ +- DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ +- DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ +- DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ +- DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ +- DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ +- DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ +- DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ +- DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ +- DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ +- DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ +- DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ +- DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ +- DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ +- DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ +- DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ +- DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ +- DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ +- DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ +- DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ +- DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ +- DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ +- DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ +- DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ +- DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ +- DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ +- DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ +- DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ +- DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ +- DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ +- DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ +- DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ +- DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ +- DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ +- DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ +- DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ +- DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ +- DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ +- DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ +- DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ +- DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ +- DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ +- DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ +- DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ +- DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ +- DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ +- DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ +- DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ +-} DMA_CH_TRIGSRC_t; +- +-/* Double buffering mode */ +-typedef enum DMA_DBUFMODE_enum +-{ +- DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ +- DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ +- DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ +- DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ +-} DMA_DBUFMODE_t; +- +-/* Priority mode */ +-typedef enum DMA_PRIMODE_enum +-{ +- DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ +- DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ +- DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ +- DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ +-} DMA_PRIMODE_t; +- +-/* Interrupt level */ +-typedef enum DMA_CH_ERRINTLVL_enum +-{ +- DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ +- DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ +- DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ +-} DMA_CH_ERRINTLVL_t; +- +-/* Interrupt level */ +-typedef enum DMA_CH_TRNINTLVL_enum +-{ +- DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ +- DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ +- DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ +-} DMA_CH_TRNINTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-EVSYS - Event System +--------------------------------------------------------------------------- +-*/ +- +-/* Event System */ +-typedef struct EVSYS_struct +-{ +- register8_t CH0MUX; /* Event Channel 0 Multiplexer */ +- register8_t CH1MUX; /* Event Channel 1 Multiplexer */ +- register8_t CH2MUX; /* Event Channel 2 Multiplexer */ +- register8_t CH3MUX; /* Event Channel 3 Multiplexer */ +- register8_t CH4MUX; /* Event Channel 4 Multiplexer */ +- register8_t CH5MUX; /* Event Channel 5 Multiplexer */ +- register8_t CH6MUX; /* Event Channel 6 Multiplexer */ +- register8_t CH7MUX; /* Event Channel 7 Multiplexer */ +- register8_t CH0CTRL; /* Channel 0 Control Register */ +- register8_t CH1CTRL; /* Channel 1 Control Register */ +- register8_t CH2CTRL; /* Channel 2 Control Register */ +- register8_t CH3CTRL; /* Channel 3 Control Register */ +- register8_t CH4CTRL; /* Channel 4 Control Register */ +- register8_t CH5CTRL; /* Channel 5 Control Register */ +- register8_t CH6CTRL; /* Channel 6 Control Register */ +- register8_t CH7CTRL; /* Channel 7 Control Register */ +- register8_t STROBE; /* Event Strobe */ +- register8_t DATA; /* Event Data */ +-} EVSYS_t; +- +-/* Quadrature Decoder Index Recognition Mode */ +-typedef enum EVSYS_QDIRM_enum +-{ +- EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ +- EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ +- EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ +- EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +-} EVSYS_QDIRM_t; +- +-/* Digital filter coefficient */ +-typedef enum EVSYS_DIGFILT_enum +-{ +- EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ +- EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ +- EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ +- EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ +- EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ +- EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ +- EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ +- EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +-} EVSYS_DIGFILT_t; +- +-/* Event Channel multiplexer input selection */ +-typedef enum EVSYS_CHMUX_enum +-{ +- EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ +- EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ +- EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ +- EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ +- EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ +- EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ +- EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ +- EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ +- EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ +- EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ +- EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ +- EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ +- EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ +- EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ +- EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ +- EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ +- EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ +- EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ +- EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ +- EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ +- EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ +- EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ +- EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ +- EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ +- EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ +- EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ +- EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ +- EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ +- EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ +- EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ +- EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ +- EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ +- EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ +- EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ +- EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ +- EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ +- EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ +- EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ +- EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ +- EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ +- EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ +- EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ +- EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ +- EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ +- EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ +- EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ +- EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ +- EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ +- EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ +- EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ +- EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ +- EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ +- EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ +- EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ +- EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ +- EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ +- EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ +- EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ +- EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ +- EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ +- EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ +- EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ +- EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ +- EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ +- EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ +- EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ +- EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ +- EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ +- EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ +- EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ +- EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ +- EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ +- EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ +- EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ +- EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ +- EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ +- EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ +- EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ +- EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ +- EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ +- EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ +- EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ +- EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ +- EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ +- EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ +- EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ +- EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ +- EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ +- EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ +- EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ +- EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ +- EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ +- EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ +- EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ +- EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ +- EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ +- EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ +- EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ +- EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ +- EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ +- EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ +- EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ +- EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ +- EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ +- EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ +- EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ +- EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ +- EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ +- EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ +- EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ +- EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +- EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ +- EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ +- EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ +- EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +-} EVSYS_CHMUX_t; +- +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Non-volatile Memory Controller */ +-typedef struct NVM_struct +-{ +- register8_t ADDR0; /* Address Register 0 */ +- register8_t ADDR1; /* Address Register 1 */ +- register8_t ADDR2; /* Address Register 2 */ +- register8_t reserved_0x03; +- register8_t DATA0; /* Data Register 0 */ +- register8_t DATA1; /* Data Register 1 */ +- register8_t DATA2; /* Data Register 2 */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t CMD; /* Command */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t INTCTRL; /* Interrupt Control */ +- register8_t reserved_0x0E; +- register8_t STATUS; /* Status */ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Lock Bits */ +-typedef struct NVM_LOCKBITS_struct +-{ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_LOCKBITS_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Fuses */ +-typedef struct NVM_FUSES_struct +-{ +- register8_t FUSEBYTE0; /* JTAG User ID */ +- register8_t FUSEBYTE1; /* Watchdog Configuration */ +- register8_t FUSEBYTE2; /* Reset Configuration */ +- register8_t reserved_0x03; +- register8_t FUSEBYTE4; /* Start-up Configuration */ +- register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +-} NVM_FUSES_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Production Signatures */ +-typedef struct NVM_PROD_SIGNATURES_struct +-{ +- register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ +- register8_t reserved_0x01; +- register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ +- register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ +- register8_t reserved_0x04; +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ +- register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ +- register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ +- register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ +- register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ +- register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t WAFNUM; /* Wafer Number */ +- register8_t reserved_0x11; +- register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ +- register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ +- register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ +- register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ +- register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ +- register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ +- register8_t reserved_0x26; +- register8_t reserved_0x27; +- register8_t reserved_0x28; +- register8_t reserved_0x29; +- register8_t reserved_0x2A; +- register8_t reserved_0x2B; +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ +- register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ +- register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ +- register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ +- register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ +- register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- register8_t reserved_0x36; +- register8_t reserved_0x37; +- register8_t reserved_0x38; +- register8_t reserved_0x39; +- register8_t reserved_0x3A; +- register8_t reserved_0x3B; +- register8_t reserved_0x3C; +- register8_t reserved_0x3D; +- register8_t reserved_0x3E; +-} NVM_PROD_SIGNATURES_t; +- +-/* NVM Command */ +-typedef enum NVM_CMD_enum +-{ +- NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ +- NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ +- NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ +- NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ +- NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ +- NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ +- NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ +- NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ +- NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ +- NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ +- NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ +- NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ +- NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ +- NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ +- NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ +- NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ +- NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ +- NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ +- NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ +- NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ +- NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ +- NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ +- NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ +- NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ +- NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ +- NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +-} NVM_CMD_t; +- +-/* SPM ready interrupt level */ +-typedef enum NVM_SPMLVL_enum +-{ +- NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ +- NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ +- NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +-} NVM_SPMLVL_t; +- +-/* EEPROM ready interrupt level */ +-typedef enum NVM_EELVL_enum +-{ +- NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ +- NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ +- NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +-} NVM_EELVL_t; +- +-/* Boot lock bits - boot setcion */ +-typedef enum NVM_BLBB_enum +-{ +- NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +- NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ +- NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ +- NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +-} NVM_BLBB_t; +- +-/* Boot lock bits - application section */ +-typedef enum NVM_BLBA_enum +-{ +- NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +- NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ +- NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ +- NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +-} NVM_BLBA_t; +- +-/* Boot lock bits - application table section */ +-typedef enum NVM_BLBAT_enum +-{ +- NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +- NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ +- NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ +- NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +-} NVM_BLBAT_t; +- +-/* Lock bits */ +-typedef enum NVM_LB_enum +-{ +- NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +- NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ +- NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +-} NVM_LB_t; +- +-/* Boot Loader Section Reset Vector */ +-typedef enum BOOTRST_enum +-{ +- BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ +- BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +-} BOOTRST_t; +- +-/* BOD operation */ +-typedef enum BOD_enum +-{ +- BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ +- BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ +- BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +-} BOD_t; +- +-/* Watchdog (Window) Timeout Period */ +-typedef enum WD_enum +-{ +- WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ +- WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ +- WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ +- WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ +- WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ +- WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ +- WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ +- WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ +- WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ +- WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ +- WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +-} WD_t; +- +-/* Start-up Time */ +-typedef enum SUT_enum +-{ +- SUT_0MS_gc = (0x03<<2), /* 0 ms */ +- SUT_4MS_gc = (0x01<<2), /* 4 ms */ +- SUT_64MS_gc = (0x00<<2), /* 64 ms */ +-} SUT_t; +- +-/* Brown Out Detection Voltage Level */ +-typedef enum BODLVL_enum +-{ +- BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ +- BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ +- BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ +- BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ +- BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ +- BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ +- BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ +-} BODLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-AC - Analog Comparator +--------------------------------------------------------------------------- +-*/ +- +-/* Analog Comparator */ +-typedef struct AC_struct +-{ +- register8_t AC0CTRL; /* Comparator 0 Control */ +- register8_t AC1CTRL; /* Comparator 1 Control */ +- register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ +- register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t WINCTRL; /* Window Mode Control */ +- register8_t STATUS; /* Status */ +-} AC_t; +- +-/* Interrupt mode */ +-typedef enum AC_INTMODE_enum +-{ +- AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ +- AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ +- AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +-} AC_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum AC_INTLVL_enum +-{ +- AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ +- AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ +- AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ +- AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +-} AC_INTLVL_t; +- +-/* Hysteresis mode selection */ +-typedef enum AC_HYSMODE_enum +-{ +- AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ +- AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ +- AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +-} AC_HYSMODE_t; +- +-/* Positive input multiplexer selection */ +-typedef enum AC_MUXPOS_enum +-{ +- AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ +- AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ +- AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ +- AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ +- AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ +- AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ +- AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +- AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +-} AC_MUXPOS_t; +- +-/* Negative input multiplexer selection */ +-typedef enum AC_MUXNEG_enum +-{ +- AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ +- AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ +- AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ +- AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ +- AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ +- AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ +- AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ +- AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +-} AC_MUXNEG_t; +- +-/* Windows interrupt mode */ +-typedef enum AC_WINTMODE_enum +-{ +- AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ +- AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ +- AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ +- AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +-} AC_WINTMODE_t; +- +-/* Window interrupt level */ +-typedef enum AC_WINTLVL_enum +-{ +- AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ +- AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ +- AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +-} AC_WINTLVL_t; +- +-/* Window mode state */ +-typedef enum AC_WSTATE_enum +-{ +- AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ +- AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ +- AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +-} AC_WSTATE_t; +- +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* ADC Channel */ +-typedef struct ADC_CH_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t MUXCTRL; /* MUX Control */ +- register8_t INTCTRL; /* Channel Interrupt Control */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- _WORDREGISTER(RES); /* Channel Result */ +- register8_t reserved_0x6; +- register8_t reserved_0x7; +-} ADC_CH_t; +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Analog-to-Digital Converter */ +-typedef struct ADC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t REFCTRL; /* Reference Control */ +- register8_t EVCTRL; /* Event Control */ +- register8_t PRESCALER; /* Clock Prescaler */ +- register8_t reserved_0x05; +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- _WORDREGISTER(CAL); /* Calibration Value */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- _WORDREGISTER(CH0RES); /* Channel 0 Result */ +- _WORDREGISTER(CH1RES); /* Channel 1 Result */ +- _WORDREGISTER(CH2RES); /* Channel 2 Result */ +- _WORDREGISTER(CH3RES); /* Channel 3 Result */ +- _WORDREGISTER(CMP); /* Compare Value */ +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- ADC_CH_t CH0; /* ADC Channel 0 */ +- ADC_CH_t CH1; /* ADC Channel 1 */ +- ADC_CH_t CH2; /* ADC Channel 2 */ +- ADC_CH_t CH3; /* ADC Channel 3 */ +-} ADC_t; +- +-/* Positive input multiplexer selection */ +-typedef enum ADC_CH_MUXPOS_enum +-{ +- ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ +- ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ +- ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ +- ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ +- ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ +- ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ +- ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ +- ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +-} ADC_CH_MUXPOS_t; +- +-/* Internal input multiplexer selections */ +-typedef enum ADC_CH_MUXINT_enum +-{ +- ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ +- ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ +- ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +- ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +-} ADC_CH_MUXINT_t; +- +-/* Negative input multiplexer selection */ +-typedef enum ADC_CH_MUXNEG_enum +-{ +- ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ +- ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ +- ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ +- ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ +- ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ +- ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ +- ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ +- ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +-} ADC_CH_MUXNEG_t; +- +-/* Input mode */ +-typedef enum ADC_CH_INPUTMODE_enum +-{ +- ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ +- ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ +- ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ +- ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +-} ADC_CH_INPUTMODE_t; +- +-/* Gain factor */ +-typedef enum ADC_CH_GAIN_enum +-{ +- ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ +- ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ +- ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ +- ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ +- ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ +- ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ +- ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ +-} ADC_CH_GAIN_t; +- +-/* Conversion result resolution */ +-typedef enum ADC_RESOLUTION_enum +-{ +- ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ +- ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ +- ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +-} ADC_RESOLUTION_t; +- +-/* Voltage reference selection */ +-typedef enum ADC_REFSEL_enum +-{ +- ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ +- ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ +- ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ +- ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +-} ADC_REFSEL_t; +- +-/* Channel sweep selection */ +-typedef enum ADC_SWEEP_enum +-{ +- ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ +- ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ +- ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ +- ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ +-} ADC_SWEEP_t; +- +-/* Event channel input selection */ +-typedef enum ADC_EVSEL_enum +-{ +- ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ +- ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ +- ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ +- ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ +- ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ +- ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ +- ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ +- ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +-} ADC_EVSEL_t; +- +-/* Event action selection */ +-typedef enum ADC_EVACT_enum +-{ +- ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ +- ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ +- ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ +- ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ +- ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ +- ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ +- ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ +-} ADC_EVACT_t; +- +-/* Interupt mode */ +-typedef enum ADC_CH_INTMODE_enum +-{ +- ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ +- ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ +- ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +-} ADC_CH_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum ADC_CH_INTLVL_enum +-{ +- ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ +- ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ +- ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +-} ADC_CH_INTLVL_t; +- +-/* DMA request selection */ +-typedef enum ADC_DMASEL_enum +-{ +- ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ +- ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ +- ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ +- ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ +-} ADC_DMASEL_t; +- +-/* Clock prescaler */ +-typedef enum ADC_PRESCALER_enum +-{ +- ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ +- ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ +- ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ +- ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ +- ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ +- ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ +- ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ +- ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +-} ADC_PRESCALER_t; +- +- +-/* +--------------------------------------------------------------------------- +-DAC - Digital/Analog Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Digital-to-Analog Converter */ +-typedef struct DAC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t EVCTRL; /* Event Input Control */ +- register8_t TIMCTRL; /* Timing Control */ +- register8_t STATUS; /* Status */ +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t GAINCAL; /* Gain Calibration */ +- register8_t OFFSETCAL; /* Offset Calibration */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- _WORDREGISTER(CH0DATA); /* Channel 0 Data */ +- _WORDREGISTER(CH1DATA); /* Channel 1 Data */ +-} DAC_t; +- +-/* Output channel selection */ +-typedef enum DAC_CHSEL_enum +-{ +- DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ +- DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ +-} DAC_CHSEL_t; +- +-/* Reference voltage selection */ +-typedef enum DAC_REFSEL_enum +-{ +- DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ +- DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ +- DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ +- DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ +-} DAC_REFSEL_t; +- +-/* Event channel selection */ +-typedef enum DAC_EVSEL_enum +-{ +- DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ +- DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ +- DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ +- DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ +- DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ +- DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ +- DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ +- DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ +-} DAC_EVSEL_t; +- +-/* Conversion interval */ +-typedef enum DAC_CONINTVAL_enum +-{ +- DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ +- DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ +- DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ +- DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ +- DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ +- DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ +- DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ +- DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ +-} DAC_CONINTVAL_t; +- +-/* Refresh rate */ +-typedef enum DAC_REFRESH_enum +-{ +- DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ +- DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ +- DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ +- DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ +- DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ +- DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ +- DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ +- DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ +- DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ +- DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ +- DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ +- DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ +- DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ +- DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ +-} DAC_REFRESH_t; +- +- +-/* +--------------------------------------------------------------------------- +-RTC - Real-Time Clounter +--------------------------------------------------------------------------- +-*/ +- +-/* Real-Time Counter */ +-typedef struct RTC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t TEMP; /* Temporary register */ +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- _WORDREGISTER(CNT); /* Count Register */ +- _WORDREGISTER(PER); /* Period Register */ +- _WORDREGISTER(COMP); /* Compare Register */ +-} RTC_t; +- +-/* Prescaler Factor */ +-typedef enum RTC_PRESCALER_enum +-{ +- RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ +- RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ +- RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ +- RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ +- RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ +- RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ +- RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ +- RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +-} RTC_PRESCALER_t; +- +-/* Compare Interrupt level */ +-typedef enum RTC_COMPINTLVL_enum +-{ +- RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} RTC_COMPINTLVL_t; +- +-/* Overflow Interrupt level */ +-typedef enum RTC_OVFINTLVL_enum +-{ +- RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} RTC_OVFINTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* EBI Chip Select Module */ +-typedef struct EBI_CS_struct +-{ +- register8_t CTRLA; /* Chip Select Control Register A */ +- register8_t CTRLB; /* Chip Select Control Register B */ +- _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +-} EBI_CS_t; +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* External Bus Interface */ +-typedef struct EBI_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t SDRAMCTRLA; /* SDRAM Control Register A */ +- register8_t reserved_0x02; +- register8_t reserved_0x03; +- _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ +- _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ +- register8_t SDRAMCTRLB; /* SDRAM Control Register B */ +- register8_t SDRAMCTRLC; /* SDRAM Control Register C */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- EBI_CS_t CS0; /* Chip Select 0 */ +- EBI_CS_t CS1; /* Chip Select 1 */ +- EBI_CS_t CS2; /* Chip Select 2 */ +- EBI_CS_t CS3; /* Chip Select 3 */ +-} EBI_t; +- +-/* Chip Select adress space */ +-typedef enum EBI_CS_ASIZE_enum +-{ +- EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ +- EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ +- EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ +- EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ +- EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ +- EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ +- EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ +- EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ +- EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ +- EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ +- EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ +- EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ +- EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ +- EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ +- EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ +- EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ +- EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +-} EBI_CS_ASIZE_t; +- +-/* */ +-typedef enum EBI_CS_SRWS_enum +-{ +- EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_CS_SRWS_t; +- +-/* Chip Select address mode */ +-typedef enum EBI_CS_MODE_enum +-{ +- EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ +- EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ +- EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ +- EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +-} EBI_CS_MODE_t; +- +-/* Chip Select SDRAM mode */ +-typedef enum EBI_CS_SDMODE_enum +-{ +- EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ +- EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +-} EBI_CS_SDMODE_t; +- +-/* */ +-typedef enum EBI_SDDATAW_enum +-{ +- EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ +- EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +-} EBI_SDDATAW_t; +- +-/* */ +-typedef enum EBI_LPCMODE_enum +-{ +- EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ +- EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +-} EBI_LPCMODE_t; +- +-/* */ +-typedef enum EBI_SRMODE_enum +-{ +- EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ +- EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ +- EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ +- EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +-} EBI_SRMODE_t; +- +-/* */ +-typedef enum EBI_IFMODE_enum +-{ +- EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ +- EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ +- EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ +- EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +-} EBI_IFMODE_t; +- +-/* */ +-typedef enum EBI_SDCOL_enum +-{ +- EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ +- EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ +- EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ +- EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +-} EBI_SDCOL_t; +- +-/* */ +-typedef enum EBI_MRDLY_enum +-{ +- EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_MRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCYCDLY_enum +-{ +- EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ROWCYCDLY_t; +- +-/* */ +-typedef enum EBI_RPDLY_enum +-{ +- EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_RPDLY_t; +- +-/* */ +-typedef enum EBI_WRDLY_enum +-{ +- EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_WRDLY_t; +- +-/* */ +-typedef enum EBI_ESRDLY_enum +-{ +- EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ESRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCOLDLY_enum +-{ +- EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_ROWCOLDLY_t; +- +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_MASTER_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t STATUS; /* Status Register */ +- register8_t BAUD; /* Baurd Rate Control Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +-} TWI_MASTER_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_SLAVE_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t STATUS; /* Status Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +- register8_t ADDRMASK; /* Address Mask Register */ +-} TWI_SLAVE_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Two-Wire Interface */ +-typedef struct TWI_struct +-{ +- register8_t CTRL; /* TWI Common Control Register */ +- TWI_MASTER_t MASTER; /* TWI master module */ +- TWI_SLAVE_t SLAVE; /* TWI slave module */ +-} TWI_t; +- +-/* Master Interrupt Level */ +-typedef enum TWI_MASTER_INTLVL_enum +-{ +- TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_MASTER_INTLVL_t; +- +-/* Inactive Timeout */ +-typedef enum TWI_MASTER_TIMEOUT_enum +-{ +- TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ +- TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ +- TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ +- TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +-} TWI_MASTER_TIMEOUT_t; +- +-/* Master Command */ +-typedef enum TWI_MASTER_CMD_enum +-{ +- TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ +- TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ +- TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +-} TWI_MASTER_CMD_t; +- +-/* Master Bus State */ +-typedef enum TWI_MASTER_BUSSTATE_enum +-{ +- TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ +- TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ +- TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ +- TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +-} TWI_MASTER_BUSSTATE_t; +- +-/* Slave Interrupt Level */ +-typedef enum TWI_SLAVE_INTLVL_enum +-{ +- TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_SLAVE_INTLVL_t; +- +-/* Slave Command */ +-typedef enum TWI_SLAVE_CMD_enum +-{ +- TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ +- TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +-} TWI_SLAVE_CMD_t; +- +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O port Configuration */ +-typedef struct PORTCFG_struct +-{ +- register8_t MPCMASK; /* Multi-pin Configuration Mask */ +- register8_t reserved_0x01; +- register8_t VPCTRLA; /* Virtual Port Control Register A */ +- register8_t VPCTRLB; /* Virtual Port Control Register B */ +- register8_t CLKEVOUT; /* Clock and Event Out Register */ +-} PORTCFG_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* Virtual Port */ +-typedef struct VPORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t OUT; /* I/O Port Output */ +- register8_t IN; /* I/O Port Input */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +-} VPORT_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O Ports */ +-typedef struct PORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t DIRSET; /* I/O Port Data Direction Set */ +- register8_t DIRCLR; /* I/O Port Data Direction Clear */ +- register8_t DIRTGL; /* I/O Port Data Direction Toggle */ +- register8_t OUT; /* I/O Port Output */ +- register8_t OUTSET; /* I/O Port Output Set */ +- register8_t OUTCLR; /* I/O Port Output Clear */ +- register8_t OUTTGL; /* I/O Port Output Toggle */ +- register8_t IN; /* I/O port Input */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INT0MASK; /* Port Interrupt 0 Mask */ +- register8_t INT1MASK; /* Port Interrupt 1 Mask */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t PIN0CTRL; /* Pin 0 Control Register */ +- register8_t PIN1CTRL; /* Pin 1 Control Register */ +- register8_t PIN2CTRL; /* Pin 2 Control Register */ +- register8_t PIN3CTRL; /* Pin 3 Control Register */ +- register8_t PIN4CTRL; /* Pin 4 Control Register */ +- register8_t PIN5CTRL; /* Pin 5 Control Register */ +- register8_t PIN6CTRL; /* Pin 6 Control Register */ +- register8_t PIN7CTRL; /* Pin 7 Control Register */ +-} PORT_t; +- +-/* Virtual Port 0 Mapping */ +-typedef enum PORTCFG_VP0MAP_enum +-{ +- PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP0MAP_t; +- +-/* Virtual Port 1 Mapping */ +-typedef enum PORTCFG_VP1MAP_enum +-{ +- PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP1MAP_t; +- +-/* Virtual Port 2 Mapping */ +-typedef enum PORTCFG_VP2MAP_enum +-{ +- PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP2MAP_t; +- +-/* Virtual Port 3 Mapping */ +-typedef enum PORTCFG_VP3MAP_enum +-{ +- PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP3MAP_t; +- +-/* Clock Output Port */ +-typedef enum PORTCFG_CLKOUT_enum +-{ +- PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ +- PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ +- PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ +- PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +-} PORTCFG_CLKOUT_t; +- +-/* Event Output Port */ +-typedef enum PORTCFG_EVOUT_enum +-{ +- PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ +- PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ +- PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ +- PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +-} PORTCFG_EVOUT_t; +- +-/* Port Interrupt 0 Level */ +-typedef enum PORT_INT0LVL_enum +-{ +- PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ +- PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ +- PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +-} PORT_INT0LVL_t; +- +-/* Port Interrupt 1 Level */ +-typedef enum PORT_INT1LVL_enum +-{ +- PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ +- PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ +- PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +-} PORT_INT1LVL_t; +- +-/* Output/Pull Configuration */ +-typedef enum PORT_OPC_enum +-{ +- PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ +- PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ +- PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ +- PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ +- PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ +- PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ +- PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ +- PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +-} PORT_OPC_t; +- +-/* Input/Sense Configuration */ +-typedef enum PORT_ISC_enum +-{ +- PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ +- PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ +- PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ +- PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ +- PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +-} PORT_ISC_t; +- +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 0 */ +-typedef struct TC0_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- _WORDREGISTER(CCC); /* Compare or Capture C */ +- _WORDREGISTER(CCD); /* Compare or Capture D */ +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +- _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ +- _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +-} TC0_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 1 */ +-typedef struct TC1_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t reserved_0x2E; +- register8_t reserved_0x2F; +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +-} TC1_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* Advanced Waveform Extension */ +-typedef struct AWEX_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t FDEMASK; /* Fault Detection Event Mask */ +- register8_t FDCTRL; /* Fault Detection Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x05; +- register8_t DTBOTH; /* Dead Time Both Sides */ +- register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ +- register8_t DTLS; /* Dead Time Low Side */ +- register8_t DTHS; /* Dead Time High Side */ +- register8_t DTLSBUF; /* Dead Time Low Side Buffer */ +- register8_t DTHSBUF; /* Dead Time High Side Buffer */ +- register8_t OUTOVEN; /* Output Override Enable */ +-} AWEX_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* High-Resolution Extension */ +-typedef struct HIRES_struct +-{ +- register8_t CTRLA; /* Control Register */ +-} HIRES_t; +- +-/* Clock Selection */ +-typedef enum TC_CLKSEL_enum +-{ +- TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ +- TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ +- TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ +- TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ +- TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ +- TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ +- TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ +- TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ +- TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_CLKSEL_t; +- +-/* Waveform Generation Mode */ +-typedef enum TC_WGMODE_enum +-{ +- TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ +- TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ +- TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ +- TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ +- TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ +- TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +-} TC_WGMODE_t; +- +-/* Event Action */ +-typedef enum TC_EVACT_enum +-{ +- TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ +- TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ +- TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ +- TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ +- TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ +- TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */ +- TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +-} TC_EVACT_t; +- +-/* Event Selection */ +-typedef enum TC_EVSEL_enum +-{ +- TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_EVSEL_t; +- +-/* Error Interrupt Level */ +-typedef enum TC_ERRINTLVL_enum +-{ +- TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_ERRINTLVL_t; +- +-/* Overflow Interrupt Level */ +-typedef enum TC_OVFINTLVL_enum +-{ +- TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_OVFINTLVL_t; +- +-/* Compare or Capture D Interrupt Level */ +-typedef enum TC_CCDINTLVL_enum +-{ +- TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TC_CCDINTLVL_t; +- +-/* Compare or Capture C Interrupt Level */ +-typedef enum TC_CCCINTLVL_enum +-{ +- TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} TC_CCCINTLVL_t; +- +-/* Compare or Capture B Interrupt Level */ +-typedef enum TC_CCBINTLVL_enum +-{ +- TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_CCBINTLVL_t; +- +-/* Compare or Capture A Interrupt Level */ +-typedef enum TC_CCAINTLVL_enum +-{ +- TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_CCAINTLVL_t; +- +-/* Timer/Counter Command */ +-typedef enum TC_CMD_enum +-{ +- TC_CMD_NONE_gc = (0x00<<2), /* No Command */ +- TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ +- TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ +- TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +-} TC_CMD_t; +- +-/* Fault Detect Action */ +-typedef enum AWEX_FDACT_enum +-{ +- AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ +- AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ +- AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +-} AWEX_FDACT_t; +- +-/* High Resolution Enable */ +-typedef enum HIRES_HREN_enum +-{ +- HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ +- HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ +- HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ +- HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +-} HIRES_HREN_t; +- +- +-/* +--------------------------------------------------------------------------- +-USART - Universal Asynchronous Receiver-Transmitter +--------------------------------------------------------------------------- +-*/ +- +-/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +-typedef struct USART_struct +-{ +- register8_t DATA; /* Data Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x02; +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t BAUDCTRLA; /* Baud Rate Control Register A */ +- register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +-} USART_t; +- +-/* Receive Complete Interrupt level */ +-typedef enum USART_RXCINTLVL_enum +-{ +- USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} USART_RXCINTLVL_t; +- +-/* Transmit Complete Interrupt level */ +-typedef enum USART_TXCINTLVL_enum +-{ +- USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} USART_TXCINTLVL_t; +- +-/* Data Register Empty Interrupt level */ +-typedef enum USART_DREINTLVL_enum +-{ +- USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} USART_DREINTLVL_t; +- +-/* Character Size */ +-typedef enum USART_CHSIZE_enum +-{ +- USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ +- USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ +- USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ +- USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ +- USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +-} USART_CHSIZE_t; +- +-/* Communication Mode */ +-typedef enum USART_CMODE_enum +-{ +- USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ +- USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ +- USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ +- USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +-} USART_CMODE_t; +- +-/* Parity Mode */ +-typedef enum USART_PMODE_enum +-{ +- USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ +- USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ +- USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +-} USART_PMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-SPI - Serial Peripheral Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Serial Peripheral Interface */ +-typedef struct SPI_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t DATA; /* Data Register */ +-} SPI_t; +- +-/* SPI Mode */ +-typedef enum SPI_MODE_enum +-{ +- SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ +- SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ +- SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ +- SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +-} SPI_MODE_t; +- +-/* Prescaler setting */ +-typedef enum SPI_PRESCALER_enum +-{ +- SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ +- SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ +- SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ +- SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +-} SPI_PRESCALER_t; +- +-/* Interrupt level */ +-typedef enum SPI_INTLVL_enum +-{ +- SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} SPI_INTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-IRCOM - IR Communication Module +--------------------------------------------------------------------------- +-*/ +- +-/* IR Communication Module */ +-typedef struct IRCOM_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ +- register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +-} IRCOM_t; +- +-/* Event channel selection */ +-typedef enum IRDA_EVSEL_enum +-{ +- IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ +- IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ +- IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ +- IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +- IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ +- IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ +- IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ +- IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +-} IRDA_EVSEL_t; +- +- +-/* +--------------------------------------------------------------------------- +-AES - AES Module +--------------------------------------------------------------------------- +-*/ +- +-/* AES Module */ +-typedef struct AES_struct +-{ +- register8_t CTRL; /* AES Control Register */ +- register8_t STATUS; /* AES Status Register */ +- register8_t STATE; /* AES State Register */ +- register8_t KEY; /* AES Key Register */ +- register8_t INTCTRL; /* AES Interrupt Control Register */ +-} AES_t; +- +-/* Interrupt level */ +-typedef enum AES_INTLVL_enum +-{ +- AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} AES_INTLVL_t; +- +- +- +-/* +-========================================================================== +-IO Module Instances. Mapped to memory. +-========================================================================== +-*/ +- +-#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +-#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +-#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +-#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +-#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +-#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +-#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +-#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +-#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +-#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +-#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +-#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +-#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +-#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +-#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +-#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +-#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ +-#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ +-#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +-#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +-#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +-#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ +-#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ +-#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +-#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ +-#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +-#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +-#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ +-#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +-#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +-#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +-#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +-#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +-#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ +-#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +-#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +-#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +-#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +-#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +-#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +-#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ +-#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +-#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +-#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +-#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ +-#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ +-#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +-#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ +-#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +-#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +-#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ +-#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ +-#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ +-#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ +-#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ +-#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ +-#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ +-#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ +-#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ +-#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ +-#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ +- +- +-#endif /* !defined (__ASSEMBLER__) */ +- +- +-/* ========== Flattened fully qualified IO register names ========== */ +- +-/* GPIO - General Purpose IO Registers */ +-#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +-#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +-#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +-#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +-#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +-#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +-#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +-#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +-#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +-#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +-#define GPIO_GPIORA _SFR_MEM8(0x000A) +-#define GPIO_GPIORB _SFR_MEM8(0x000B) +-#define GPIO_GPIORC _SFR_MEM8(0x000C) +-#define GPIO_GPIORD _SFR_MEM8(0x000D) +-#define GPIO_GPIORE _SFR_MEM8(0x000E) +-#define GPIO_GPIORF _SFR_MEM8(0x000F) +- +-/* Deprecated */ +-#define GPIO_GPIO0 _SFR_MEM8(0x0000) +-#define GPIO_GPIO1 _SFR_MEM8(0x0001) +-#define GPIO_GPIO2 _SFR_MEM8(0x0002) +-#define GPIO_GPIO3 _SFR_MEM8(0x0003) +-#define GPIO_GPIO4 _SFR_MEM8(0x0004) +-#define GPIO_GPIO5 _SFR_MEM8(0x0005) +-#define GPIO_GPIO6 _SFR_MEM8(0x0006) +-#define GPIO_GPIO7 _SFR_MEM8(0x0007) +-#define GPIO_GPIO8 _SFR_MEM8(0x0008) +-#define GPIO_GPIO9 _SFR_MEM8(0x0009) +-#define GPIO_GPIOA _SFR_MEM8(0x000A) +-#define GPIO_GPIOB _SFR_MEM8(0x000B) +-#define GPIO_GPIOC _SFR_MEM8(0x000C) +-#define GPIO_GPIOD _SFR_MEM8(0x000D) +-#define GPIO_GPIOE _SFR_MEM8(0x000E) +-#define GPIO_GPIOF _SFR_MEM8(0x000F) +- +-/* VPORT0 - Virtual Port 0 */ +-#define VPORT0_DIR _SFR_MEM8(0x0010) +-#define VPORT0_OUT _SFR_MEM8(0x0011) +-#define VPORT0_IN _SFR_MEM8(0x0012) +-#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) +- +-/* VPORT1 - Virtual Port 1 */ +-#define VPORT1_DIR _SFR_MEM8(0x0014) +-#define VPORT1_OUT _SFR_MEM8(0x0015) +-#define VPORT1_IN _SFR_MEM8(0x0016) +-#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) +- +-/* VPORT2 - Virtual Port 2 */ +-#define VPORT2_DIR _SFR_MEM8(0x0018) +-#define VPORT2_OUT _SFR_MEM8(0x0019) +-#define VPORT2_IN _SFR_MEM8(0x001A) +-#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) +- +-/* VPORT3 - Virtual Port 3 */ +-#define VPORT3_DIR _SFR_MEM8(0x001C) +-#define VPORT3_OUT _SFR_MEM8(0x001D) +-#define VPORT3_IN _SFR_MEM8(0x001E) +-#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) +- +-/* OCD - On-Chip Debug System */ +-#define OCD_OCDR0 _SFR_MEM8(0x002E) +-#define OCD_OCDR1 _SFR_MEM8(0x002F) +- +-/* CPU - CPU Registers */ +-#define CPU_CCP _SFR_MEM8(0x0034) +-#define CPU_RAMPD _SFR_MEM8(0x0038) +-#define CPU_RAMPX _SFR_MEM8(0x0039) +-#define CPU_RAMPY _SFR_MEM8(0x003A) +-#define CPU_RAMPZ _SFR_MEM8(0x003B) +-#define CPU_EIND _SFR_MEM8(0x003C) +-#define CPU_SPL _SFR_MEM8(0x003D) +-#define CPU_SPH _SFR_MEM8(0x003E) +-#define CPU_SREG _SFR_MEM8(0x003F) +- +-/* CLK - Clock System */ +-#define CLK_CTRL _SFR_MEM8(0x0040) +-#define CLK_PSCTRL _SFR_MEM8(0x0041) +-#define CLK_LOCK _SFR_MEM8(0x0042) +-#define CLK_RTCCTRL _SFR_MEM8(0x0043) +- +-/* SLEEP - Sleep Controller */ +-#define SLEEP_CTRL _SFR_MEM8(0x0048) +- +-/* OSC - Oscillator Control */ +-#define OSC_CTRL _SFR_MEM8(0x0050) +-#define OSC_STATUS _SFR_MEM8(0x0051) +-#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +-#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +-#define OSC_RC32KCAL _SFR_MEM8(0x0054) +-#define OSC_PLLCTRL _SFR_MEM8(0x0055) +-#define OSC_DFLLCTRL _SFR_MEM8(0x0056) +- +-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +-#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +-#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +-#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +-#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +-#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +-#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) +- +-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +-#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +-#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +-#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +-#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +-#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +-#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) +- +-/* PR - Power Reduction */ +-#define PR_PRGEN _SFR_MEM8(0x0070) +-#define PR_PRPA _SFR_MEM8(0x0071) -#define PR_PRPB _SFR_MEM8(0x0072) - #define PR_PRPC _SFR_MEM8(0x0073) - #define PR_PRPD _SFR_MEM8(0x0074) - #define PR_PRPE _SFR_MEM8(0x0075) -@@ -2347,6 +2398,15 @@ IO Module Instances. Mapped to memory. - #define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) - #define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) - -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ - /* EVSYS - Event System */ - #define EVSYS_CH0MUX _SFR_MEM8(0x0180) - #define EVSYS_CH1MUX _SFR_MEM8(0x0181) -@@ -2437,6 +2497,22 @@ IO Module Instances. Mapped to memory. - #define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) - #define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) - -+/* TWIE - Two-Wire Interface E */ -+#define TWIE_CTRL _SFR_MEM8(0x04A0) -+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -+ - /* PORTA - Port A */ - #define PORTA_DIR _SFR_MEM8(0x0600) - #define PORTA_DIRSET _SFR_MEM8(0x0601) -@@ -2915,59 +2991,31 @@ IO Module Instances. Mapped to memory. - - - /* PR.PRGEN bit masks and bit positions */ +-#define PR_PRPC _SFR_MEM8(0x0073) +-#define PR_PRPD _SFR_MEM8(0x0074) +-#define PR_PRPE _SFR_MEM8(0x0075) +-#define PR_PRPF _SFR_MEM8(0x0076) +- +-/* RST - Reset Controller */ +-#define RST_STATUS _SFR_MEM8(0x0078) +-#define RST_CTRL _SFR_MEM8(0x0079) +- +-/* WDT - Watch-Dog Timer */ +-#define WDT_CTRL _SFR_MEM8(0x0080) +-#define WDT_WINCTRL _SFR_MEM8(0x0081) +-#define WDT_STATUS _SFR_MEM8(0x0082) +- +-/* MCU - MCU Control */ +-#define MCU_DEVID0 _SFR_MEM8(0x0090) +-#define MCU_DEVID1 _SFR_MEM8(0x0091) +-#define MCU_DEVID2 _SFR_MEM8(0x0092) +-#define MCU_REVID _SFR_MEM8(0x0093) +-#define MCU_JTAGUID _SFR_MEM8(0x0094) +-#define MCU_MCUCR _SFR_MEM8(0x0096) +-#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +-#define MCU_AWEXLOCK _SFR_MEM8(0x0099) +- +-/* PMIC - Programmable Interrupt Controller */ +-#define PMIC_STATUS _SFR_MEM8(0x00A0) +-#define PMIC_INTPRI _SFR_MEM8(0x00A1) +-#define PMIC_CTRL _SFR_MEM8(0x00A2) +- +-/* PORTCFG - Port Configuration */ +-#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +-#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +-#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +-#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +- +-/* AES - AES Crypto Module */ +-#define AES_CTRL _SFR_MEM8(0x00C0) +-#define AES_STATUS _SFR_MEM8(0x00C1) +-#define AES_STATE _SFR_MEM8(0x00C2) +-#define AES_KEY _SFR_MEM8(0x00C3) +-#define AES_INTCTRL _SFR_MEM8(0x00C4) +- +-/* DMA - DMA Controller */ +-#define DMA_CTRL _SFR_MEM8(0x0100) +-#define DMA_INTFLAGS _SFR_MEM8(0x0103) +-#define DMA_STATUS _SFR_MEM8(0x0104) +-#define DMA_TEMP _SFR_MEM16(0x0106) +-#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) +-#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) +-#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) +-#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) +-#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) +-#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) +-#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) +-#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) +-#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) +-#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) +-#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) +-#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) +-#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) +-#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) +-#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) +-#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) +-#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) +-#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) +-#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) +-#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) +-#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) +-#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) +-#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) +-#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) +-#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) +-#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) +-#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) +-#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) +-#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) +-#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) +-#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) +-#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) +-#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) +-#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) +-#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) +-#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) +-#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) +-#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) +-#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) +-#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) +-#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) +-#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) +-#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) +-#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) +-#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) +-#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) +-#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) +-#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) +- +-/* EVSYS - Event System */ +-#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +-#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +-#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +-#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +-#define EVSYS_CH4MUX _SFR_MEM8(0x0184) +-#define EVSYS_CH5MUX _SFR_MEM8(0x0185) +-#define EVSYS_CH6MUX _SFR_MEM8(0x0186) +-#define EVSYS_CH7MUX _SFR_MEM8(0x0187) +-#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +-#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +-#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +-#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +-#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) +-#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) +-#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) +-#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) +-#define EVSYS_STROBE _SFR_MEM8(0x0190) +-#define EVSYS_DATA _SFR_MEM8(0x0191) +- +-/* NVM - Non Volatile Memory Controller */ +-#define NVM_ADDR0 _SFR_MEM8(0x01C0) +-#define NVM_ADDR1 _SFR_MEM8(0x01C1) +-#define NVM_ADDR2 _SFR_MEM8(0x01C2) +-#define NVM_DATA0 _SFR_MEM8(0x01C4) +-#define NVM_DATA1 _SFR_MEM8(0x01C5) +-#define NVM_DATA2 _SFR_MEM8(0x01C6) +-#define NVM_CMD _SFR_MEM8(0x01CA) +-#define NVM_CTRLA _SFR_MEM8(0x01CB) +-#define NVM_CTRLB _SFR_MEM8(0x01CC) +-#define NVM_INTCTRL _SFR_MEM8(0x01CD) +-#define NVM_STATUS _SFR_MEM8(0x01CF) +-#define NVM_LOCKBITS _SFR_MEM8(0x01D0) +- +-/* ADCA - Analog to Digital Converter A */ +-#define ADCA_CTRLA _SFR_MEM8(0x0200) +-#define ADCA_CTRLB _SFR_MEM8(0x0201) +-#define ADCA_REFCTRL _SFR_MEM8(0x0202) +-#define ADCA_EVCTRL _SFR_MEM8(0x0203) +-#define ADCA_PRESCALER _SFR_MEM8(0x0204) +-#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +-#define ADCA_CAL _SFR_MEM16(0x020C) +-#define ADCA_CH0RES _SFR_MEM16(0x0210) +-#define ADCA_CH1RES _SFR_MEM16(0x0212) +-#define ADCA_CH2RES _SFR_MEM16(0x0214) +-#define ADCA_CH3RES _SFR_MEM16(0x0216) +-#define ADCA_CMP _SFR_MEM16(0x0218) +-#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +-#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +-#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +-#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +-#define ADCA_CH0_RES _SFR_MEM16(0x0224) +-#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) +-#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) +-#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) +-#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) +-#define ADCA_CH1_RES _SFR_MEM16(0x022C) +-#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) +-#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) +-#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) +-#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) +-#define ADCA_CH2_RES _SFR_MEM16(0x0234) +-#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) +-#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) +-#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) +-#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) +-#define ADCA_CH3_RES _SFR_MEM16(0x023C) +- +-/* ADCB - Analog to Digital Converter B */ +-#define ADCB_CTRLA _SFR_MEM8(0x0240) +-#define ADCB_CTRLB _SFR_MEM8(0x0241) +-#define ADCB_REFCTRL _SFR_MEM8(0x0242) +-#define ADCB_EVCTRL _SFR_MEM8(0x0243) +-#define ADCB_PRESCALER _SFR_MEM8(0x0244) +-#define ADCB_INTFLAGS _SFR_MEM8(0x0246) +-#define ADCB_CAL _SFR_MEM16(0x024C) +-#define ADCB_CH0RES _SFR_MEM16(0x0250) +-#define ADCB_CH1RES _SFR_MEM16(0x0252) +-#define ADCB_CH2RES _SFR_MEM16(0x0254) +-#define ADCB_CH3RES _SFR_MEM16(0x0256) +-#define ADCB_CMP _SFR_MEM16(0x0258) +-#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) +-#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) +-#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) +-#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) +-#define ADCB_CH0_RES _SFR_MEM16(0x0264) +-#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) +-#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) +-#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) +-#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) +-#define ADCB_CH1_RES _SFR_MEM16(0x026C) +-#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) +-#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) +-#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) +-#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) +-#define ADCB_CH2_RES _SFR_MEM16(0x0274) +-#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) +-#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) +-#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) +-#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) +-#define ADCB_CH3_RES _SFR_MEM16(0x027C) +- +-/* DACB - Digital to Analog Converter B */ +-#define DACB_CTRLA _SFR_MEM8(0x0320) +-#define DACB_CTRLB _SFR_MEM8(0x0321) +-#define DACB_CTRLC _SFR_MEM8(0x0322) +-#define DACB_EVCTRL _SFR_MEM8(0x0323) +-#define DACB_TIMCTRL _SFR_MEM8(0x0324) +-#define DACB_STATUS _SFR_MEM8(0x0325) +-#define DACB_GAINCAL _SFR_MEM8(0x0328) +-#define DACB_OFFSETCAL _SFR_MEM8(0x0329) +-#define DACB_CH0DATA _SFR_MEM16(0x0338) +-#define DACB_CH1DATA _SFR_MEM16(0x033A) +- +-/* ACA - Analog Comparator A */ +-#define ACA_AC0CTRL _SFR_MEM8(0x0380) +-#define ACA_AC1CTRL _SFR_MEM8(0x0381) +-#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +-#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +-#define ACA_CTRLA _SFR_MEM8(0x0384) +-#define ACA_CTRLB _SFR_MEM8(0x0385) +-#define ACA_WINCTRL _SFR_MEM8(0x0386) +-#define ACA_STATUS _SFR_MEM8(0x0387) +- +-/* ACB - Analog Comparator B */ +-#define ACB_AC0CTRL _SFR_MEM8(0x0390) +-#define ACB_AC1CTRL _SFR_MEM8(0x0391) +-#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +-#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +-#define ACB_CTRLA _SFR_MEM8(0x0394) +-#define ACB_CTRLB _SFR_MEM8(0x0395) +-#define ACB_WINCTRL _SFR_MEM8(0x0396) +-#define ACB_STATUS _SFR_MEM8(0x0397) +- +-/* RTC - Real-Time Counter */ +-#define RTC_CTRL _SFR_MEM8(0x0400) +-#define RTC_STATUS _SFR_MEM8(0x0401) +-#define RTC_INTCTRL _SFR_MEM8(0x0402) +-#define RTC_INTFLAGS _SFR_MEM8(0x0403) +-#define RTC_TEMP _SFR_MEM8(0x0404) +-#define RTC_CNT _SFR_MEM16(0x0408) +-#define RTC_PER _SFR_MEM16(0x040A) +-#define RTC_COMP _SFR_MEM16(0x040C) +- +-/* TWIC - Two-Wire Interface C */ +-#define TWIC_CTRL _SFR_MEM8(0x0480) +-#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) +-#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) +-#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) +-#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) +-#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) +-#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) +-#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) +-#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +-#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +-#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +-#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +-#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +-#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) +- +-/* TWIE - Two-Wire Interface E */ +-#define TWIE_CTRL _SFR_MEM8(0x04A0) +-#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) +-#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) +-#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) +-#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) +-#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) +-#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) +-#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) +-#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) +-#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) +-#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) +-#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) +-#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) +-#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) +- +-/* PORTA - Port A */ +-#define PORTA_DIR _SFR_MEM8(0x0600) +-#define PORTA_DIRSET _SFR_MEM8(0x0601) +-#define PORTA_DIRCLR _SFR_MEM8(0x0602) +-#define PORTA_DIRTGL _SFR_MEM8(0x0603) +-#define PORTA_OUT _SFR_MEM8(0x0604) +-#define PORTA_OUTSET _SFR_MEM8(0x0605) +-#define PORTA_OUTCLR _SFR_MEM8(0x0606) +-#define PORTA_OUTTGL _SFR_MEM8(0x0607) +-#define PORTA_IN _SFR_MEM8(0x0608) +-#define PORTA_INTCTRL _SFR_MEM8(0x0609) +-#define PORTA_INT0MASK _SFR_MEM8(0x060A) +-#define PORTA_INT1MASK _SFR_MEM8(0x060B) +-#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +-#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +-#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +-#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +-#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +-#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +-#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +-#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +-#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) +- +-/* PORTB - Port B */ +-#define PORTB_DIR _SFR_MEM8(0x0620) +-#define PORTB_DIRSET _SFR_MEM8(0x0621) +-#define PORTB_DIRCLR _SFR_MEM8(0x0622) +-#define PORTB_DIRTGL _SFR_MEM8(0x0623) +-#define PORTB_OUT _SFR_MEM8(0x0624) +-#define PORTB_OUTSET _SFR_MEM8(0x0625) +-#define PORTB_OUTCLR _SFR_MEM8(0x0626) +-#define PORTB_OUTTGL _SFR_MEM8(0x0627) +-#define PORTB_IN _SFR_MEM8(0x0628) +-#define PORTB_INTCTRL _SFR_MEM8(0x0629) +-#define PORTB_INT0MASK _SFR_MEM8(0x062A) +-#define PORTB_INT1MASK _SFR_MEM8(0x062B) +-#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +-#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +-#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +-#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +-#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +-#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +-#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +-#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +-#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) +- +-/* PORTC - Port C */ +-#define PORTC_DIR _SFR_MEM8(0x0640) +-#define PORTC_DIRSET _SFR_MEM8(0x0641) +-#define PORTC_DIRCLR _SFR_MEM8(0x0642) +-#define PORTC_DIRTGL _SFR_MEM8(0x0643) +-#define PORTC_OUT _SFR_MEM8(0x0644) +-#define PORTC_OUTSET _SFR_MEM8(0x0645) +-#define PORTC_OUTCLR _SFR_MEM8(0x0646) +-#define PORTC_OUTTGL _SFR_MEM8(0x0647) +-#define PORTC_IN _SFR_MEM8(0x0648) +-#define PORTC_INTCTRL _SFR_MEM8(0x0649) +-#define PORTC_INT0MASK _SFR_MEM8(0x064A) +-#define PORTC_INT1MASK _SFR_MEM8(0x064B) +-#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +-#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +-#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +-#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +-#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +-#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +-#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +-#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +-#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) +- +-/* PORTD - Port D */ +-#define PORTD_DIR _SFR_MEM8(0x0660) +-#define PORTD_DIRSET _SFR_MEM8(0x0661) +-#define PORTD_DIRCLR _SFR_MEM8(0x0662) +-#define PORTD_DIRTGL _SFR_MEM8(0x0663) +-#define PORTD_OUT _SFR_MEM8(0x0664) +-#define PORTD_OUTSET _SFR_MEM8(0x0665) +-#define PORTD_OUTCLR _SFR_MEM8(0x0666) +-#define PORTD_OUTTGL _SFR_MEM8(0x0667) +-#define PORTD_IN _SFR_MEM8(0x0668) +-#define PORTD_INTCTRL _SFR_MEM8(0x0669) +-#define PORTD_INT0MASK _SFR_MEM8(0x066A) +-#define PORTD_INT1MASK _SFR_MEM8(0x066B) +-#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +-#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +-#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +-#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +-#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +-#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +-#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +-#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +-#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) +- +-/* PORTE - Port E */ +-#define PORTE_DIR _SFR_MEM8(0x0680) +-#define PORTE_DIRSET _SFR_MEM8(0x0681) +-#define PORTE_DIRCLR _SFR_MEM8(0x0682) +-#define PORTE_DIRTGL _SFR_MEM8(0x0683) +-#define PORTE_OUT _SFR_MEM8(0x0684) +-#define PORTE_OUTSET _SFR_MEM8(0x0685) +-#define PORTE_OUTCLR _SFR_MEM8(0x0686) +-#define PORTE_OUTTGL _SFR_MEM8(0x0687) +-#define PORTE_IN _SFR_MEM8(0x0688) +-#define PORTE_INTCTRL _SFR_MEM8(0x0689) +-#define PORTE_INT0MASK _SFR_MEM8(0x068A) +-#define PORTE_INT1MASK _SFR_MEM8(0x068B) +-#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +-#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +-#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +-#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +-#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +-#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +-#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +-#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +-#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) +- +-/* PORTF - Port F */ +-#define PORTF_DIR _SFR_MEM8(0x06A0) +-#define PORTF_DIRSET _SFR_MEM8(0x06A1) +-#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +-#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +-#define PORTF_OUT _SFR_MEM8(0x06A4) +-#define PORTF_OUTSET _SFR_MEM8(0x06A5) +-#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +-#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +-#define PORTF_IN _SFR_MEM8(0x06A8) +-#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +-#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +-#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +-#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +-#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +-#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +-#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +-#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +-#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +-#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +-#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +-#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) +- +-/* PORTR - Port R */ +-#define PORTR_DIR _SFR_MEM8(0x07E0) +-#define PORTR_DIRSET _SFR_MEM8(0x07E1) +-#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +-#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +-#define PORTR_OUT _SFR_MEM8(0x07E4) +-#define PORTR_OUTSET _SFR_MEM8(0x07E5) +-#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +-#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +-#define PORTR_IN _SFR_MEM8(0x07E8) +-#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +-#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +-#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +-#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +-#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +-#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +-#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +-#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +-#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +-#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +-#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +-#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) +- +-/* TCC0 - Timer/Counter C0 */ +-#define TCC0_CTRLA _SFR_MEM8(0x0800) +-#define TCC0_CTRLB _SFR_MEM8(0x0801) +-#define TCC0_CTRLC _SFR_MEM8(0x0802) +-#define TCC0_CTRLD _SFR_MEM8(0x0803) +-#define TCC0_CTRLE _SFR_MEM8(0x0804) +-#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +-#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +-#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +-#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +-#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +-#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +-#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +-#define TCC0_TEMP _SFR_MEM8(0x080F) +-#define TCC0_CNT _SFR_MEM16(0x0820) +-#define TCC0_PER _SFR_MEM16(0x0826) +-#define TCC0_CCA _SFR_MEM16(0x0828) +-#define TCC0_CCB _SFR_MEM16(0x082A) +-#define TCC0_CCC _SFR_MEM16(0x082C) +-#define TCC0_CCD _SFR_MEM16(0x082E) +-#define TCC0_PERBUF _SFR_MEM16(0x0836) +-#define TCC0_CCABUF _SFR_MEM16(0x0838) +-#define TCC0_CCBBUF _SFR_MEM16(0x083A) +-#define TCC0_CCCBUF _SFR_MEM16(0x083C) +-#define TCC0_CCDBUF _SFR_MEM16(0x083E) +- +-/* TCC1 - Timer/Counter C1 */ +-#define TCC1_CTRLA _SFR_MEM8(0x0840) +-#define TCC1_CTRLB _SFR_MEM8(0x0841) +-#define TCC1_CTRLC _SFR_MEM8(0x0842) +-#define TCC1_CTRLD _SFR_MEM8(0x0843) +-#define TCC1_CTRLE _SFR_MEM8(0x0844) +-#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +-#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +-#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +-#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +-#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +-#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +-#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +-#define TCC1_TEMP _SFR_MEM8(0x084F) +-#define TCC1_CNT _SFR_MEM16(0x0860) +-#define TCC1_PER _SFR_MEM16(0x0866) +-#define TCC1_CCA _SFR_MEM16(0x0868) +-#define TCC1_CCB _SFR_MEM16(0x086A) +-#define TCC1_PERBUF _SFR_MEM16(0x0876) +-#define TCC1_CCABUF _SFR_MEM16(0x0878) +-#define TCC1_CCBBUF _SFR_MEM16(0x087A) +- +-/* AWEXC - Advanced Waveform Extension C */ +-#define AWEXC_CTRL _SFR_MEM8(0x0880) +-#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +-#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +-#define AWEXC_STATUS _SFR_MEM8(0x0884) +-#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +-#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +-#define AWEXC_DTLS _SFR_MEM8(0x0888) +-#define AWEXC_DTHS _SFR_MEM8(0x0889) +-#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +-#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +-#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) +- +-/* HIRESC - High-Resolution Extension C */ +-#define HIRESC_CTRLA _SFR_MEM8(0x0890) +- +-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +-#define USARTC0_DATA _SFR_MEM8(0x08A0) +-#define USARTC0_STATUS _SFR_MEM8(0x08A1) +-#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +-#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +-#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +-#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +-#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) +- +-/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ +-#define USARTC1_DATA _SFR_MEM8(0x08B0) +-#define USARTC1_STATUS _SFR_MEM8(0x08B1) +-#define USARTC1_CTRLA _SFR_MEM8(0x08B3) +-#define USARTC1_CTRLB _SFR_MEM8(0x08B4) +-#define USARTC1_CTRLC _SFR_MEM8(0x08B5) +-#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) +-#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) +- +-/* SPIC - Serial Peripheral Interface C */ +-#define SPIC_CTRL _SFR_MEM8(0x08C0) +-#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +-#define SPIC_STATUS _SFR_MEM8(0x08C2) +-#define SPIC_DATA _SFR_MEM8(0x08C3) +- +-/* IRCOM - IR Communication Module */ +-#define IRCOM_CTRL _SFR_MEM8(0x08F8) +-#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) +-#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) +- +-/* TCD0 - Timer/Counter D0 */ +-#define TCD0_CTRLA _SFR_MEM8(0x0900) +-#define TCD0_CTRLB _SFR_MEM8(0x0901) +-#define TCD0_CTRLC _SFR_MEM8(0x0902) +-#define TCD0_CTRLD _SFR_MEM8(0x0903) +-#define TCD0_CTRLE _SFR_MEM8(0x0904) +-#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +-#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +-#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +-#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +-#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +-#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +-#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +-#define TCD0_TEMP _SFR_MEM8(0x090F) +-#define TCD0_CNT _SFR_MEM16(0x0920) +-#define TCD0_PER _SFR_MEM16(0x0926) +-#define TCD0_CCA _SFR_MEM16(0x0928) +-#define TCD0_CCB _SFR_MEM16(0x092A) +-#define TCD0_CCC _SFR_MEM16(0x092C) +-#define TCD0_CCD _SFR_MEM16(0x092E) +-#define TCD0_PERBUF _SFR_MEM16(0x0936) +-#define TCD0_CCABUF _SFR_MEM16(0x0938) +-#define TCD0_CCBBUF _SFR_MEM16(0x093A) +-#define TCD0_CCCBUF _SFR_MEM16(0x093C) +-#define TCD0_CCDBUF _SFR_MEM16(0x093E) +- +-/* TCD1 - Timer/Counter D1 */ +-#define TCD1_CTRLA _SFR_MEM8(0x0940) +-#define TCD1_CTRLB _SFR_MEM8(0x0941) +-#define TCD1_CTRLC _SFR_MEM8(0x0942) +-#define TCD1_CTRLD _SFR_MEM8(0x0943) +-#define TCD1_CTRLE _SFR_MEM8(0x0944) +-#define TCD1_INTCTRLA _SFR_MEM8(0x0946) +-#define TCD1_INTCTRLB _SFR_MEM8(0x0947) +-#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) +-#define TCD1_CTRLFSET _SFR_MEM8(0x0949) +-#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) +-#define TCD1_CTRLGSET _SFR_MEM8(0x094B) +-#define TCD1_INTFLAGS _SFR_MEM8(0x094C) +-#define TCD1_TEMP _SFR_MEM8(0x094F) +-#define TCD1_CNT _SFR_MEM16(0x0960) +-#define TCD1_PER _SFR_MEM16(0x0966) +-#define TCD1_CCA _SFR_MEM16(0x0968) +-#define TCD1_CCB _SFR_MEM16(0x096A) +-#define TCD1_PERBUF _SFR_MEM16(0x0976) +-#define TCD1_CCABUF _SFR_MEM16(0x0978) +-#define TCD1_CCBBUF _SFR_MEM16(0x097A) +- +-/* HIRESD - High-Resolution Extension D */ +-#define HIRESD_CTRLA _SFR_MEM8(0x0990) +- +-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +-#define USARTD0_DATA _SFR_MEM8(0x09A0) +-#define USARTD0_STATUS _SFR_MEM8(0x09A1) +-#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +-#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +-#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +-#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +-#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) +- +-/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ +-#define USARTD1_DATA _SFR_MEM8(0x09B0) +-#define USARTD1_STATUS _SFR_MEM8(0x09B1) +-#define USARTD1_CTRLA _SFR_MEM8(0x09B3) +-#define USARTD1_CTRLB _SFR_MEM8(0x09B4) +-#define USARTD1_CTRLC _SFR_MEM8(0x09B5) +-#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) +-#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) +- +-/* SPID - Serial Peripheral Interface D */ +-#define SPID_CTRL _SFR_MEM8(0x09C0) +-#define SPID_INTCTRL _SFR_MEM8(0x09C1) +-#define SPID_STATUS _SFR_MEM8(0x09C2) +-#define SPID_DATA _SFR_MEM8(0x09C3) +- +-/* TCE0 - Timer/Counter E0 */ +-#define TCE0_CTRLA _SFR_MEM8(0x0A00) +-#define TCE0_CTRLB _SFR_MEM8(0x0A01) +-#define TCE0_CTRLC _SFR_MEM8(0x0A02) +-#define TCE0_CTRLD _SFR_MEM8(0x0A03) +-#define TCE0_CTRLE _SFR_MEM8(0x0A04) +-#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +-#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +-#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +-#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +-#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +-#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +-#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +-#define TCE0_TEMP _SFR_MEM8(0x0A0F) +-#define TCE0_CNT _SFR_MEM16(0x0A20) +-#define TCE0_PER _SFR_MEM16(0x0A26) +-#define TCE0_CCA _SFR_MEM16(0x0A28) +-#define TCE0_CCB _SFR_MEM16(0x0A2A) +-#define TCE0_CCC _SFR_MEM16(0x0A2C) +-#define TCE0_CCD _SFR_MEM16(0x0A2E) +-#define TCE0_PERBUF _SFR_MEM16(0x0A36) +-#define TCE0_CCABUF _SFR_MEM16(0x0A38) +-#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +-#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +-#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) +- +-/* TCE1 - Timer/Counter E1 */ +-#define TCE1_CTRLA _SFR_MEM8(0x0A40) +-#define TCE1_CTRLB _SFR_MEM8(0x0A41) +-#define TCE1_CTRLC _SFR_MEM8(0x0A42) +-#define TCE1_CTRLD _SFR_MEM8(0x0A43) +-#define TCE1_CTRLE _SFR_MEM8(0x0A44) +-#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) +-#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) +-#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) +-#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) +-#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) +-#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) +-#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) +-#define TCE1_TEMP _SFR_MEM8(0x0A4F) +-#define TCE1_CNT _SFR_MEM16(0x0A60) +-#define TCE1_PER _SFR_MEM16(0x0A66) +-#define TCE1_CCA _SFR_MEM16(0x0A68) +-#define TCE1_CCB _SFR_MEM16(0x0A6A) +-#define TCE1_PERBUF _SFR_MEM16(0x0A76) +-#define TCE1_CCABUF _SFR_MEM16(0x0A78) +-#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) +- +-/* AWEXE - Advanced Waveform Extension E */ +-#define AWEXE_CTRL _SFR_MEM8(0x0A80) +-#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +-#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +-#define AWEXE_STATUS _SFR_MEM8(0x0A84) +-#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +-#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +-#define AWEXE_DTLS _SFR_MEM8(0x0A88) +-#define AWEXE_DTHS _SFR_MEM8(0x0A89) +-#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +-#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +-#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) +- +-/* HIRESE - High-Resolution Extension E */ +-#define HIRESE_CTRLA _SFR_MEM8(0x0A90) +- +-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +-#define USARTE0_DATA _SFR_MEM8(0x0AA0) +-#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +-#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +-#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +-#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +-#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +-#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) +- +-/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ +-#define USARTE1_DATA _SFR_MEM8(0x0AB0) +-#define USARTE1_STATUS _SFR_MEM8(0x0AB1) +-#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) +-#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) +-#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) +-#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) +-#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) +- +-/* SPIE - Serial Peripheral Interface E */ +-#define SPIE_CTRL _SFR_MEM8(0x0AC0) +-#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +-#define SPIE_STATUS _SFR_MEM8(0x0AC2) +-#define SPIE_DATA _SFR_MEM8(0x0AC3) +- +-/* TCF0 - Timer/Counter F0 */ +-#define TCF0_CTRLA _SFR_MEM8(0x0B00) +-#define TCF0_CTRLB _SFR_MEM8(0x0B01) +-#define TCF0_CTRLC _SFR_MEM8(0x0B02) +-#define TCF0_CTRLD _SFR_MEM8(0x0B03) +-#define TCF0_CTRLE _SFR_MEM8(0x0B04) +-#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +-#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +-#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +-#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +-#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +-#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +-#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +-#define TCF0_TEMP _SFR_MEM8(0x0B0F) +-#define TCF0_CNT _SFR_MEM16(0x0B20) +-#define TCF0_PER _SFR_MEM16(0x0B26) +-#define TCF0_CCA _SFR_MEM16(0x0B28) +-#define TCF0_CCB _SFR_MEM16(0x0B2A) +-#define TCF0_CCC _SFR_MEM16(0x0B2C) +-#define TCF0_CCD _SFR_MEM16(0x0B2E) +-#define TCF0_PERBUF _SFR_MEM16(0x0B36) +-#define TCF0_CCABUF _SFR_MEM16(0x0B38) +-#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +-#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +-#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) +- +-/* HIRESF - High-Resolution Extension F */ +-#define HIRESF_CTRLA _SFR_MEM8(0x0B90) +- +-/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ +-#define USARTF0_DATA _SFR_MEM8(0x0BA0) +-#define USARTF0_STATUS _SFR_MEM8(0x0BA1) +-#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) +-#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) +-#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) +-#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) +-#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) +- +-/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ +-#define USARTF1_DATA _SFR_MEM8(0x0BB0) +-#define USARTF1_STATUS _SFR_MEM8(0x0BB1) +-#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) +-#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) +-#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) +-#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) +-#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) +- +-/* SPIF - Serial Peripheral Interface F */ +-#define SPIF_CTRL _SFR_MEM8(0x0BC0) +-#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) +-#define SPIF_STATUS _SFR_MEM8(0x0BC2) +-#define SPIF_DATA _SFR_MEM8(0x0BC3) +- +- +- +-/*================== Bitfield Definitions ================== */ +- +-/* XOCD - On-Chip Debug System */ +-/* OCD.OCDR1 bit masks and bit positions */ +-#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +-#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ +- +- +-/* CPU - CPU */ +-/* CPU.CCP bit masks and bit positions */ +-#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +-#define CPU_CCP_gp 0 /* CCP signature group position. */ +-#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +-#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +-#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +-#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +-#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +-#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +-#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +-#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +-#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +-#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +-#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +-#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +-#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +-#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +-#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +-#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ +- +- +-/* CPU.SREG bit masks and bit positions */ +-#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +-#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ +- +-#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +-#define CPU_T_bp 6 /* Transfer Bit bit position. */ +- +-#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +-#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +- +-#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +-#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +- +-#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +-#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +- +-#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +-#define CPU_N_bp 2 /* Negative Flag bit position. */ +- +-#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +-#define CPU_Z_bp 1 /* Zero Flag bit position. */ +- +-#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +-#define CPU_C_bp 0 /* Carry Flag bit position. */ +- +- +-/* CLK - Clock System */ +-/* CLK.CTRL bit masks and bit positions */ +-#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +-#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +-#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +-#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +-#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +-#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +-#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +-#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ +- +- +-/* CLK.PSCTRL bit masks and bit positions */ +-#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +-#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +-#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +-#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +-#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +-#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +-#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +-#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +-#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +-#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +-#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +-#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ +- +-#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +-#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +-#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +-#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +-#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +-#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ +- +- +-/* CLK.LOCK bit masks and bit positions */ +-#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +-#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ +- +- +-/* CLK.RTCCTRL bit masks and bit positions */ +-#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +-#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +-#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +-#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +-#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +-#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +-#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +-#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ +- +-#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +-#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ +- +- +-/* PR.PRGEN bit masks and bit positions */ -#define PR_AES_bm 0x10 /* AES bit mask. */ -#define PR_AES_bp 4 /* AES bit position. */ - -#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ -#define PR_EBI_bp 3 /* External Bus Interface bit position. */ - - #define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ - #define PR_RTC_bp 2 /* Real-time Counter bit position. */ - - #define PR_EVSYS_bm 0x02 /* Event System bit mask. */ - #define PR_EVSYS_bp 1 /* Event System bit position. */ - +-#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +-#define PR_RTC_bp 2 /* Real-time Counter bit position. */ +- +-#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +-#define PR_EVSYS_bp 1 /* Event System bit position. */ +- -#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ -#define PR_DMA_bp 0 /* DMA-Controller bit position. */ - - - /* PR.PRPA bit masks and bit positions */ +-/* PR.PRPA bit masks and bit positions */ -#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -#define PR_DAC_bp 2 /* Port A DAC bit position. */ - - #define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ - #define PR_ADC_bp 1 /* Port A ADC bit position. */ - - #define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ - #define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ - +-#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +-#define PR_ADC_bp 1 /* Port A ADC bit position. */ +- +-#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +-#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ +- - -/* PR.PRPB bit masks and bit positions */ -/* PR_DAC_bm Predefined. */ @@ -252521,64 +631624,39 @@ index df6b35e..8b84da5 100644 -/* PR_AC_bp Predefined. */ - - - /* PR.PRPC bit masks and bit positions */ - #define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ - #define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ - +-/* PR.PRPC bit masks and bit positions */ +-#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +-#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ +- -#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ -#define PR_USART1_bp 5 /* Port C USART1 bit position. */ - - #define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ - #define PR_USART0_bp 4 /* Port C USART0 bit position. */ - - #define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ - #define PR_SPI_bp 3 /* Port C SPI bit position. */ - +-#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +-#define PR_USART0_bp 4 /* Port C USART0 bit position. */ +- +-#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +-#define PR_SPI_bp 3 /* Port C SPI bit position. */ +- -#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ -#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ -+#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ -+#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ - - #define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ - #define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -@@ -2975,76 +3023,33 @@ IO Module Instances. Mapped to memory. - #define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ - #define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ - - - /* PR.PRPD bit masks and bit positions */ +-#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +-#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ +- +-#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +-#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ +- +- +-/* PR.PRPD bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - - /* PR_USART0_bm Predefined. */ - /* PR_USART0_bp Predefined. */ - - /* PR_SPI_bm Predefined. */ - /* PR_SPI_bp Predefined. */ - --/* PR_HIRES_bm Predefined. */ --/* PR_HIRES_bp Predefined. */ +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ - --/* PR_TC1_bm Predefined. */ --/* PR_TC1_bp Predefined. */ -- - /* PR_TC0_bm Predefined. */ - /* PR_TC0_bp Predefined. */ - -- - /* PR.PRPE bit masks and bit positions */ - /* PR_TWI_bm Predefined. */ - /* PR_TWI_bp Predefined. */ - --/* PR_USART1_bm Predefined. */ --/* PR_USART1_bp Predefined. */ -- - /* PR_USART0_bm Predefined. */ - /* PR_USART0_bp Predefined. */ - -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - @@ -252588,20 +631666,20 @@ index df6b35e..8b84da5 100644 -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - - /* PR_TC0_bm Predefined. */ - /* PR_TC0_bp Predefined. */ - +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ - - /* PR.PRPF bit masks and bit positions */ +- +-/* PR.PRPE bit masks and bit positions */ -/* PR_TWI_bm Predefined. */ -/* PR_TWI_bp Predefined. */ - -/* PR_USART1_bm Predefined. */ -/* PR_USART1_bp Predefined. */ - - /* PR_USART0_bm Predefined. */ - /* PR_USART0_bp Predefined. */ - +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- -/* PR_SPI_bm Predefined. */ -/* PR_SPI_bp Predefined. */ - @@ -252611,13269 +631689,68500 @@ index df6b35e..8b84da5 100644 -/* PR_TC1_bm Predefined. */ -/* PR_TC1_bp Predefined. */ - - /* PR_TC0_bm Predefined. */ - /* PR_TC0_bp Predefined. */ - +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ - - /* SLEEP - Sleep Controller */ - /* SLEEP.CTRL bit masks and bit positions */ - #define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -@@ -3325,6 +3330,37 @@ IO Module Instances. Mapped to memory. - #define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ - - -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+ - /* EVSYS - Event System */ - /* EVSYS.CH0MUX bit masks and bit positions */ - #define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -@@ -3954,6 +3990,13 @@ IO Module Instances. Mapped to memory. - - - /* ADC.CTRLB bit masks and bit positions */ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ -+ - #define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ - #define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ - -@@ -5421,6 +5464,12 @@ IO Module Instances. Mapped to memory. - #define PORTE_INT1_vect_num 44 - #define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ - -+/* TWIE interrupt vectors */ -+#define TWIE_TWIS_vect_num 45 -+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -+#define TWIE_TWIM_vect_num 46 -+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ -+ - /* TCE0 interrupt vectors */ - #define TCE0_OVF_vect_num 47 - #define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +- +-/* PR.PRPF bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* SLEEP - Sleep Controller */ +-/* SLEEP.CTRL bit masks and bit positions */ +-#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +-#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +-#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +-#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +-#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +-#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +-#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +-#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ +- +-#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +-#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ +- +- +-/* OSC - Oscillator */ +-/* OSC.CTRL bit masks and bit positions */ +-#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +-#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ +- +-#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +-#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ +- +-#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ +- +- +-/* OSC.STATUS bit masks and bit positions */ +-#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +-#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ +- +-#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +-#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ +- +-#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ +- +- +-/* OSC.XOSCCTRL bit masks and bit positions */ +-#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +-#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +-#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +-#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +-#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +-#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ +- +-#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +-#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ +- +-#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +-#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +-#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +-#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +-#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +-#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +-#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +-#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +-#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +-#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +- +- +-/* OSC.XOSCFAIL bit masks and bit positions */ +-#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +-#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ +- +-#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +-#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ +- +- +-/* OSC.PLLCTRL bit masks and bit positions */ +-#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +-#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +-#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +-#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +-#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +-#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ +- +-#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +-#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +-#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +-#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +-#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +-#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +-#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +-#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +-#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +-#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +-#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +-#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ +- +- +-/* OSC.DFLLCTRL bit masks and bit positions */ +-#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +-#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ +- +-#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +-#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ +- +- +-/* DFLL - DFLL */ +-/* DFLL.CTRL bit masks and bit positions */ +-#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +-#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ +- +- +-/* DFLL.CALA bit masks and bit positions */ +-#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +-#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +-#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +-#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +-#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +-#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +-#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +-#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +-#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +-#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +-#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +-#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +-#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +-#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +-#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +-#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ +- +- +-/* DFLL.CALB bit masks and bit positions */ +-#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +-#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +-#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +-#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +-#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +-#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +-#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +-#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +-#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +-#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +-#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +-#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +-#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +-#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ +- +- +-/* RST - Reset */ +-/* RST.STATUS bit masks and bit positions */ +-#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +-#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ +- +-#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +-#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ +- +-#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +-#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ +- +-#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +-#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ +- +-#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +-#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ +- +-#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +-#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ +- +-#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +-#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ +- +- +-/* RST.CTRL bit masks and bit positions */ +-#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +-#define RST_SWRST_bp 0 /* Software Reset bit position. */ +- +- +-/* WDT - Watch-Dog Timer */ +-/* WDT.CTRL bit masks and bit positions */ +-#define WDT_PER_gm 0x3C /* Period group mask. */ +-#define WDT_PER_gp 2 /* Period group position. */ +-#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +-#define WDT_PER0_bp 2 /* Period bit 0 position. */ +-#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +-#define WDT_PER1_bp 3 /* Period bit 1 position. */ +-#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +-#define WDT_PER2_bp 4 /* Period bit 2 position. */ +-#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +-#define WDT_PER3_bp 5 /* Period bit 3 position. */ +- +-#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +-#define WDT_ENABLE_bp 1 /* Enable bit position. */ +- +-#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +-#define WDT_CEN_bp 0 /* Change Enable bit position. */ +- +- +-/* WDT.WINCTRL bit masks and bit positions */ +-#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +-#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +-#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +-#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +-#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +-#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +-#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +-#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +-#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +-#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ +- +-#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +-#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ +- +-#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +-#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ +- +- +-/* WDT.STATUS bit masks and bit positions */ +-#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +-#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +- +- +-/* MCU - MCU Control */ +-/* MCU.MCUCR bit masks and bit positions */ +-#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +-#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ +- +- +-/* MCU.EVSYSLOCK bit masks and bit positions */ +-#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +-#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ +- +-#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +-#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ +- +- +-/* MCU.AWEXLOCK bit masks and bit positions */ +-#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +-#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ +- +-#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +-#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ +- +- +-/* PMIC - Programmable Multi-level Interrupt Controller */ +-/* PMIC.STATUS bit masks and bit positions */ +-#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +-#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ +- +-#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +-#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ +- +-#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +-#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ +- +-#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +-#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ +- +- +-/* PMIC.CTRL bit masks and bit positions */ +-#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +-#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ +- +-#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +-#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ +- +-#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +-#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ +- +-#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +-#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ +- +-#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +-#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ +- +- +-/* DMA - DMA Controller */ +-/* DMA_CH.CTRLA bit masks and bit positions */ +-#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ +-#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ +- +-#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ +-#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ +- +-#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ +-#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ +- +-#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ +-#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ +- +-#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ +-#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ +- +-#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ +-#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ +-#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ +-#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ +-#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ +-#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ +- +- +-/* DMA_CH.CTRLB bit masks and bit positions */ +-#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ +-#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ +- +-#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ +-#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ +- +-#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ +-#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ +- +-#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ +-#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ +-#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ +-#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ +-#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ +-#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ +- +-#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ +-#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ +-#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ +-#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ +-#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ +-#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ +- +- +-/* DMA_CH.ADDRCTRL bit masks and bit positions */ +-#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ +-#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ +-#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ +-#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ +-#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ +-#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ +- +-#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ +-#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ +-#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ +-#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ +-#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ +-#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ +- +-#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ +-#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ +-#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ +-#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ +-#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ +-#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ +- +-#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ +-#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ +-#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ +-#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ +-#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ +-#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ +- +- +-/* DMA_CH.TRIGSRC bit masks and bit positions */ +-#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ +-#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ +-#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ +-#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ +-#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ +-#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ +-#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ +-#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ +-#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ +-#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ +-#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ +-#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ +-#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ +-#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ +-#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ +-#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ +-#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ +-#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ +- +- +-/* DMA.CTRL bit masks and bit positions */ +-#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ +-#define DMA_ENABLE_bp 7 /* Enable bit position. */ +- +-#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ +-#define DMA_RESET_bp 6 /* Software Reset bit position. */ +- +-#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ +-#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ +-#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ +-#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ +-#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ +-#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ +- +-#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ +-#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ +-#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ +-#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ +-#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ +-#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ +- +- +-/* DMA.INTFLAGS bit masks and bit positions */ +-#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ +-#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ +- +-#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ +- +-#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ +-#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ +- +- +-/* DMA.STATUS bit masks and bit positions */ +-#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ +-#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ +- +-#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ +-#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ +- +-#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ +-#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ +- +-#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ +-#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ +- +-#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ +-#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ +- +-#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ +-#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ +- +-#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ +-#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ +- +-#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ +-#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ +- +- +-/* EVSYS - Event System */ +-/* EVSYS.CH0MUX bit masks and bit positions */ +-#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +-#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +-#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +-#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +-#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +-#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +-#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +-#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +-#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +-#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +-#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +-#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +-#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +-#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +-#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +-#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +-#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +-#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ +- +- +-/* EVSYS.CH1MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH2MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH3MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH4MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH5MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH6MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH7MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH0CTRL bit masks and bit positions */ +-#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +-#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +-#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +-#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +-#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +-#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ +- +-#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +-#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ +- +-#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +-#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ +- +-#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +-#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +-#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +-#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +-#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +-#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +-#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +-#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ +- +- +-/* EVSYS.CH1CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH2CTRL bit masks and bit positions */ +-/* EVSYS_QDIRM_gm Predefined. */ +-/* EVSYS_QDIRM_gp Predefined. */ +-/* EVSYS_QDIRM0_bm Predefined. */ +-/* EVSYS_QDIRM0_bp Predefined. */ +-/* EVSYS_QDIRM1_bm Predefined. */ +-/* EVSYS_QDIRM1_bp Predefined. */ +- +-/* EVSYS_QDIEN_bm Predefined. */ +-/* EVSYS_QDIEN_bp Predefined. */ +- +-/* EVSYS_QDEN_bm Predefined. */ +-/* EVSYS_QDEN_bp Predefined. */ +- +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH3CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH4CTRL bit masks and bit positions */ +-/* EVSYS_QDIRM_gm Predefined. */ +-/* EVSYS_QDIRM_gp Predefined. */ +-/* EVSYS_QDIRM0_bm Predefined. */ +-/* EVSYS_QDIRM0_bp Predefined. */ +-/* EVSYS_QDIRM1_bm Predefined. */ +-/* EVSYS_QDIRM1_bp Predefined. */ +- +-/* EVSYS_QDIEN_bm Predefined. */ +-/* EVSYS_QDIEN_bp Predefined. */ +- +-/* EVSYS_QDEN_bm Predefined. */ +-/* EVSYS_QDEN_bp Predefined. */ +- +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH5CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH6CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH7CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* NVM - Non Volatile Memory Controller */ +-/* NVM.CMD bit masks and bit positions */ +-#define NVM_CMD_gm 0xFF /* Command group mask. */ +-#define NVM_CMD_gp 0 /* Command group position. */ +-#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +-#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +-#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +-#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +-#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +-#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +-#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +-#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +-#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +-#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +-#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +-#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +-#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +-#define NVM_CMD7_bp 7 /* Command bit 7 position. */ +- +- +-/* NVM.CTRLA bit masks and bit positions */ +-#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +-#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ +- +- +-/* NVM.CTRLB bit masks and bit positions */ +-#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +-#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ +- +-#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +-#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ +- +-#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +-#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ +- +-#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +-#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ +- +- +-/* NVM.INTCTRL bit masks and bit positions */ +-#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +-#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +-#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +-#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +-#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +-#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ +- +-#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +-#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +-#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +-#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +-#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +-#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ +- +- +-/* NVM.STATUS bit masks and bit positions */ +-#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +-#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ +- +-#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +-#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ +- +-#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +-#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ +- +-#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +-#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ +- +- +-/* NVM.LOCKBITS bit masks and bit positions */ +-#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +-#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +-#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ +-#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ +-#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ +-#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ +-#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ +-#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ +-#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ +-#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ +-#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ +-#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ +-#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ +-#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ +-#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ +-#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ +-#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ +-#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ +-#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ +-#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +-#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +-#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +-#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ +- +-#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +-#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +-#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +-#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +-#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ +- +-#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +-#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ +- +-#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +-#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +-#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +-#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +-#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +-#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +-#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +-#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +-#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +-#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +-#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +-#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ +- +-#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +-#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ +- +-#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ +-#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ +- +- +-/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +-#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +-#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +-#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +-#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +-#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +-#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ +- +-#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +-#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ +- +-#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +-#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +-#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +-#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +-#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +-#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +-#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +-#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +- +- +-/* AC - Analog Comparator */ +-/* AC.AC0CTRL bit masks and bit positions */ +-#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +-#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +-#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +-#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +-#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +-#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ +- +-#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +-#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +-#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +-#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +-#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +-#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ +- +-#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +-#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ +- +-#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +-#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +-#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +-#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +-#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +-#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +- +-#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define AC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* AC.AC1CTRL bit masks and bit positions */ +-/* AC_INTMODE_gm Predefined. */ +-/* AC_INTMODE_gp Predefined. */ +-/* AC_INTMODE0_bm Predefined. */ +-/* AC_INTMODE0_bp Predefined. */ +-/* AC_INTMODE1_bm Predefined. */ +-/* AC_INTMODE1_bp Predefined. */ +- +-/* AC_INTLVL_gm Predefined. */ +-/* AC_INTLVL_gp Predefined. */ +-/* AC_INTLVL0_bm Predefined. */ +-/* AC_INTLVL0_bp Predefined. */ +-/* AC_INTLVL1_bm Predefined. */ +-/* AC_INTLVL1_bp Predefined. */ +- +-/* AC_HSMODE_bm Predefined. */ +-/* AC_HSMODE_bp Predefined. */ +- +-/* AC_HYSMODE_gm Predefined. */ +-/* AC_HYSMODE_gp Predefined. */ +-/* AC_HYSMODE0_bm Predefined. */ +-/* AC_HYSMODE0_bp Predefined. */ +-/* AC_HYSMODE1_bm Predefined. */ +-/* AC_HYSMODE1_bp Predefined. */ +- +-/* AC_ENABLE_bm Predefined. */ +-/* AC_ENABLE_bp Predefined. */ +- +- +-/* AC.AC0MUXCTRL bit masks and bit positions */ +-#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +-#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +-#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +-#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +-#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +-#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +-#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +-#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ +- +-#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +-#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +-#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +-#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +-#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +-#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +-#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +-#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ +- +- +-/* AC.AC1MUXCTRL bit masks and bit positions */ +-/* AC_MUXPOS_gm Predefined. */ +-/* AC_MUXPOS_gp Predefined. */ +-/* AC_MUXPOS0_bm Predefined. */ +-/* AC_MUXPOS0_bp Predefined. */ +-/* AC_MUXPOS1_bm Predefined. */ +-/* AC_MUXPOS1_bp Predefined. */ +-/* AC_MUXPOS2_bm Predefined. */ +-/* AC_MUXPOS2_bp Predefined. */ +- +-/* AC_MUXNEG_gm Predefined. */ +-/* AC_MUXNEG_gp Predefined. */ +-/* AC_MUXNEG0_bm Predefined. */ +-/* AC_MUXNEG0_bp Predefined. */ +-/* AC_MUXNEG1_bm Predefined. */ +-/* AC_MUXNEG1_bp Predefined. */ +-/* AC_MUXNEG2_bm Predefined. */ +-/* AC_MUXNEG2_bp Predefined. */ +- +- +-/* AC.CTRLA bit masks and bit positions */ +-#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +-#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ +- +- +-/* AC.CTRLB bit masks and bit positions */ +-#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +-#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +-#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +-#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +-#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +-#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +-#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +-#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +-#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +-#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +-#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +-#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +-#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +-#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ +- +- +-/* AC.WINCTRL bit masks and bit positions */ +-#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +-#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ +- +-#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +-#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +-#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +-#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +-#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +-#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ +- +-#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +-#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +-#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +-#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +-#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +-#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ +- +- +-/* AC.STATUS bit masks and bit positions */ +-#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +-#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +-#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +-#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +-#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +-#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ +- +-#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +-#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ +- +-#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +-#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ +- +-#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +-#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ +- +-#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +-#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ +- +-#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +-#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ +- +- +-/* ADC - Analog/Digital Converter */ +-/* ADC_CH.CTRL bit masks and bit positions */ +-#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +-#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ +- +-#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +-#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +-#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +-#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +-#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +-#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +-#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +-#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ +- +-#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +-#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +-#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +-#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +-#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +-#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ +- +- +-/* ADC_CH.MUXCTRL bit masks and bit positions */ +-#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +-#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +-#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +-#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +-#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +-#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +-#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +-#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +-#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +-#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ +- +-#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +-#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +-#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +-#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +-#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +-#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +-#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +-#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +-#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +-#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ +- +-#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +-#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +-#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +-#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +-#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +-#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ +- +- +-/* ADC_CH.INTCTRL bit masks and bit positions */ +-#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +-#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +-#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +-#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +-#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +-#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ +- +-#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +-#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +-#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +-#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +-#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +-#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ +- +- +-/* ADC_CH.INTFLAGS bit masks and bit positions */ +-#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +-#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ +- +- +-/* ADC.CTRLA bit masks and bit positions */ +-#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ +-#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ +-#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ +-#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ +-#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ +-#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ +- +-#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ +-#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ +- +-#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ +-#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ +- +-#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ +-#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ +- +-#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +-#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ +- +-#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ +-#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ +- +-#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +-#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ +- +- +-/* ADC.CTRLB bit masks and bit positions */ +-#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +-#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ +- +-#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +-#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ +- +-#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +-#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +-#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +-#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +-#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +-#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ +- +- +-/* ADC.REFCTRL bit masks and bit positions */ +-#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +-#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +-#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +-#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +-#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +-#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +- +-#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +-#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ +- +-#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +-#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ +- +- +-/* ADC.EVCTRL bit masks and bit positions */ +-#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +-#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +-#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +-#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +-#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +-#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ +- +-#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +-#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +-#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +-#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +-#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +-#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +-#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +-#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ +- +-#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +-#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +-#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +-#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +-#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +-#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +-#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +-#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ +- +- +-/* ADC.PRESCALER bit masks and bit positions */ +-#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +-#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +-#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +-#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +-#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +-#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +-#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +-#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ +- +- +-/* ADC.INTFLAGS bit masks and bit positions */ +-#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ +-#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ +- +-#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ +-#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ +- +-#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ +-#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ +- +-#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +-#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ +- +- +-/* DAC - Digital/Analog Converter */ +-/* DAC.CTRLA bit masks and bit positions */ +-#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ +-#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ +- +-#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ +-#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ +- +-#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ +-#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ +- +-#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ +-#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ +- +-#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define DAC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* DAC.CTRLB bit masks and bit positions */ +-#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ +-#define DAC_CHSEL_gp 5 /* Channel Select group position. */ +-#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ +-#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ +-#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ +-#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ +- +-#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ +-#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ +- +-#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ +-#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ +- +- +-/* DAC.CTRLC bit masks and bit positions */ +-#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ +-#define DAC_REFSEL_gp 3 /* Reference Select group position. */ +-#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ +-#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ +-#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ +-#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ +- +-#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ +-#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ +- +- +-/* DAC.EVCTRL bit masks and bit positions */ +-#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ +-#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ +-#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ +-#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ +-#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ +-#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ +-#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ +-#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ +- +- +-/* DAC.TIMCTRL bit masks and bit positions */ +-#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ +-#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ +-#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ +-#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ +-#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ +-#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ +-#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ +-#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ +- +-#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ +-#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ +-#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ +-#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ +-#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ +-#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ +-#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ +-#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ +-#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ +-#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ +- +- +-/* DAC.STATUS bit masks and bit positions */ +-#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ +-#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ +- +-#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ +-#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ +- +- +-/* RTC - Real-Time Clounter */ +-/* RTC.CTRL bit masks and bit positions */ +-#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +-#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +-#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +-#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +-#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +-#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +-#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +-#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ +- +- +-/* RTC.STATUS bit masks and bit positions */ +-#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +-#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ +- +- +-/* RTC.INTCTRL bit masks and bit positions */ +-#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +-#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +-#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +-#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +-#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +-#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ +- +-#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +-#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +-#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +-#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +-#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +-#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ +- +- +-/* RTC.INTFLAGS bit masks and bit positions */ +-#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +-#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ +- +-#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* EBI - External Bus Interface */ +-/* EBI_CS.CTRLA bit masks and bit positions */ +-#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +-#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +-#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +-#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +-#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +-#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +-#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +-#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +-#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +-#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +-#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +-#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ +- +-#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +-#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +-#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +-#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +-#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +-#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ +- +- +-/* EBI_CS.CTRLB bit masks and bit positions */ +-#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +-#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +-#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +-#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +-#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +-#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +-#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +-#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ +- +-#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +-#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ +- +-#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +-#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ +- +-#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +-#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +-#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +-#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +-#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +-#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ +- +- +-/* EBI.CTRL bit masks and bit positions */ +-#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +-#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +-#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +-#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +-#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +-#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ +- +-#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +-#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +-#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +-#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +-#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +-#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ +- +-#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +-#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +-#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +-#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +-#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +-#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ +- +-#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +-#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +-#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +-#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +-#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +-#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLA bit masks and bit positions */ +-#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +-#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ +- +-#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +-#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ +- +-#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +-#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +-#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +-#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +-#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +-#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLB bit masks and bit positions */ +-#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +-#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +-#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +-#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +-#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +-#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ +- +-#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +-#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +-#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +-#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +-#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +-#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +-#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +-#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ +- +-#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +-#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +-#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +-#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +-#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +-#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +-#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +-#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ +- +- +-/* EBI.SDRAMCTRLC bit masks and bit positions */ +-#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +-#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +-#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +-#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +-#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +-#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ +- +-#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +-#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +-#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +-#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +-#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +-#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +-#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +-#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ +- +-#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +-#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +-#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +-#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +-#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +-#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +-#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +-#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ +- +- +-/* TWI - Two-Wire Interface */ +-/* TWI_MASTER.CTRLA bit masks and bit positions */ +-#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +-#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ +- +-#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +-#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ +- +-#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +-#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ +- +- +-/* TWI_MASTER.CTRLB bit masks and bit positions */ +-#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +-#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +-#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +-#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +-#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +-#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +- +-#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +-#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ +- +-#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_MASTER.CTRLC bit masks and bit positions */ +-#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +-#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_MASTER.STATUS bit masks and bit positions */ +-#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +-#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ +- +-#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +-#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ +- +-#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +-#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +- +-#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +-#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +-#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +-#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +-#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +-#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +- +- +-/* TWI_SLAVE.CTRLA bit masks and bit positions */ +-#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +-#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +-#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ +- +-#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +-#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ +- +-#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_SLAVE.CTRLB bit masks and bit positions */ +-#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +-#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_SLAVE.STATUS bit masks and bit positions */ +-#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +-#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +-#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +-#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ +- +-#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +-#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ +- +-#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +-#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ +- +- +-/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +-#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +-#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +-#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +-#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +-#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +-#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +-#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +-#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +-#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +-#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +-#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +-#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +-#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +-#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +-#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +-#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ +- +-#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +-#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ +- +- +-/* TWI.CTRL bit masks and bit positions */ +-#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +-#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ +- +-#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +-#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ +- +- +-/* PORT - Port Configuration */ +-/* PORTCFG.VPCTRLA bit masks and bit positions */ +-#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +-#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +-#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +-#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +-#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +-#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +-#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +-#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +-#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +-#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ +- +-#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +-#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +-#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +-#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +-#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +-#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +-#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +-#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +-#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +-#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ +- +- +-/* PORTCFG.VPCTRLB bit masks and bit positions */ +-#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +-#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +-#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +-#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +-#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +-#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +-#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +-#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +-#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +-#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ +- +-#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +-#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +-#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +-#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +-#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +-#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +-#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +-#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +-#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +-#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ +- +- +-/* PORTCFG.CLKEVOUT bit masks and bit positions */ +-#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +-#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +-#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +-#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +-#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +-#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ +- +-#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +-#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +-#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +-#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +-#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +-#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ +- +- +-/* VPORT.INTFLAGS bit masks and bit positions */ +-#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.INTCTRL bit masks and bit positions */ +-#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +-#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +-#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +-#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +-#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +-#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ +- +-#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +-#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +-#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +-#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +-#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +-#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ +- +- +-/* PORT.INTFLAGS bit masks and bit positions */ +-#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.PIN0CTRL bit masks and bit positions */ +-#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +-#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ +- +-#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +-#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ +- +-#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +-#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +-#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +-#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +-#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +-#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +-#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +-#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ +- +-#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +-#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +-#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +-#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +-#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +-#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +-#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +-#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +- +- +-/* PORT.PIN1CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN2CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN3CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN4CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN5CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN6CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN7CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* TC - 16-bit Timer/Counter With PWM */ +-/* TC0.CTRLA bit masks and bit positions */ +-#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC0.CTRLB bit masks and bit positions */ +-#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +-#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ +- +-#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +-#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ +- +-#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC0.CTRLC bit masks and bit positions */ +-#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +-#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ +- +-#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +-#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ +- +-#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC0.CTRLD bit masks and bit positions */ +-#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC0_EVACT_gp 5 /* Event Action group position. */ +-#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC0.CTRLE bit masks and bit positions */ +-#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +-#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ +- +-#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC0.INTCTRLA bit masks and bit positions */ +-#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC0.INTCTRLB bit masks and bit positions */ +-#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +-#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +-#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +-#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +-#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +-#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ +- +-#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +-#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +-#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +-#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +-#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +-#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ +- +-#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC0.CTRLFCLR bit masks and bit positions */ +-#define TC0_CMD_gm 0x0C /* Command group mask. */ +-#define TC0_CMD_gp 2 /* Command group position. */ +-#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC0_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC0_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC0_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC0.CTRLFSET bit masks and bit positions */ +-/* TC0_CMD_gm Predefined. */ +-/* TC0_CMD_gp Predefined. */ +-/* TC0_CMD0_bm Predefined. */ +-/* TC0_CMD0_bp Predefined. */ +-/* TC0_CMD1_bm Predefined. */ +-/* TC0_CMD1_bp Predefined. */ +- +-/* TC0_LUPD_bm Predefined. */ +-/* TC0_LUPD_bp Predefined. */ +- +-/* TC0_DIR_bm Predefined. */ +-/* TC0_DIR_bp Predefined. */ +- +- +-/* TC0.CTRLGCLR bit masks and bit positions */ +-#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +-#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ +- +-#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +-#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ +- +-#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC0.CTRLGSET bit masks and bit positions */ +-/* TC0_CCDBV_bm Predefined. */ +-/* TC0_CCDBV_bp Predefined. */ +- +-/* TC0_CCCBV_bm Predefined. */ +-/* TC0_CCCBV_bp Predefined. */ +- +-/* TC0_CCBBV_bm Predefined. */ +-/* TC0_CCBBV_bp Predefined. */ +- +-/* TC0_CCABV_bm Predefined. */ +-/* TC0_CCABV_bp Predefined. */ +- +-/* TC0_PERBV_bm Predefined. */ +-/* TC0_PERBV_bp Predefined. */ +- +- +-/* TC0.INTFLAGS bit masks and bit positions */ +-#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +-#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ +- +-#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +-#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ +- +-#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* TC1.CTRLA bit masks and bit positions */ +-#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC1.CTRLB bit masks and bit positions */ +-#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC1.CTRLC bit masks and bit positions */ +-#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC1.CTRLD bit masks and bit positions */ +-#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC1_EVACT_gp 5 /* Event Action group position. */ +-#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC1.CTRLE bit masks and bit positions */ +-#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ +-#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ +- +-#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC1.INTCTRLA bit masks and bit positions */ +-#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC1.INTCTRLB bit masks and bit positions */ +-#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC1.CTRLFCLR bit masks and bit positions */ +-#define TC1_CMD_gm 0x0C /* Command group mask. */ +-#define TC1_CMD_gp 2 /* Command group position. */ +-#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC1_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC1_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC1_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC1.CTRLFSET bit masks and bit positions */ +-/* TC1_CMD_gm Predefined. */ +-/* TC1_CMD_gp Predefined. */ +-/* TC1_CMD0_bm Predefined. */ +-/* TC1_CMD0_bp Predefined. */ +-/* TC1_CMD1_bm Predefined. */ +-/* TC1_CMD1_bp Predefined. */ +- +-/* TC1_LUPD_bm Predefined. */ +-/* TC1_LUPD_bp Predefined. */ +- +-/* TC1_DIR_bm Predefined. */ +-/* TC1_DIR_bp Predefined. */ +- +- +-/* TC1.CTRLGCLR bit masks and bit positions */ +-#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC1.CTRLGSET bit masks and bit positions */ +-/* TC1_CCBBV_bm Predefined. */ +-/* TC1_CCBBV_bp Predefined. */ +- +-/* TC1_CCABV_bm Predefined. */ +-/* TC1_CCABV_bp Predefined. */ +- +-/* TC1_PERBV_bm Predefined. */ +-/* TC1_PERBV_bp Predefined. */ +- +- +-/* TC1.INTFLAGS bit masks and bit positions */ +-#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* AWEX.CTRL bit masks and bit positions */ +-#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +-#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ +- +-#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +-#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ +- +-#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +-#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ +- +-#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +-#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ +- +-#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +-#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ +- +-#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +-#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ +- +- +-/* AWEX.FDCTRL bit masks and bit positions */ +-#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +-#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ +- +-#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +-#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ +- +-#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +-#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +-#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +-#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +-#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +-#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ +- +- +-/* AWEX.STATUS bit masks and bit positions */ +-#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +-#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ +- +-#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +-#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ +- +-#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +-#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ +- +- +-/* HIRES.CTRL bit masks and bit positions */ +-#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +-#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +-#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +-#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +-#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +-#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ +- +- +-/* USART - Universal Asynchronous Receiver-Transmitter */ +-/* USART.STATUS bit masks and bit positions */ +-#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +-#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ +- +-#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +-#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +- +-#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +-#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +- +-#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +-#define USART_FERR_bp 4 /* Frame Error bit position. */ +- +-#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +-#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ +- +-#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +-#define USART_PERR_bp 2 /* Parity Error bit position. */ +- +-#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +-#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ +- +- +-/* USART.CTRLA bit masks and bit positions */ +-#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +-#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +-#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +-#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +-#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +-#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ +- +-#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +-#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +-#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +-#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +-#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +-#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ +- +-#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +-#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +-#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +-#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +-#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +-#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ +- +- +-/* USART.CTRLB bit masks and bit positions */ +-#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +-#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ +- +-#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +-#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ +- +-#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +-#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ +- +-#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +-#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ +- +-#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +-#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ +- +- +-/* USART.CTRLC bit masks and bit positions */ +-#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +-#define USART_CMODE_gp 6 /* Communication Mode group position. */ +-#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +-#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +-#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +-#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ +- +-#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +-#define USART_PMODE_gp 4 /* Parity Mode group position. */ +-#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +-#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +-#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +-#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +- +-#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +-#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +- +-#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +-#define USART_CHSIZE_gp 0 /* Character Size group position. */ +-#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +-#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +-#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +-#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +-#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +-#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +- +- +-/* USART.BAUDCTRLA bit masks and bit positions */ +-#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +-#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +-#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +-#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +-#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +-#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +-#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +-#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +-#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +-#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +-#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +-#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +-#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +-#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +-#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +-#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +-#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +-#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ +- +- +-/* USART.BAUDCTRLB bit masks and bit positions */ +-#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +-#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +-#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +-#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +-#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +-#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +-#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +-#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +-#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +-#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ +- +-/* USART_BSEL_gm Predefined. */ +-/* USART_BSEL_gp Predefined. */ +-/* USART_BSEL0_bm Predefined. */ +-/* USART_BSEL0_bp Predefined. */ +-/* USART_BSEL1_bm Predefined. */ +-/* USART_BSEL1_bp Predefined. */ +-/* USART_BSEL2_bm Predefined. */ +-/* USART_BSEL2_bp Predefined. */ +-/* USART_BSEL3_bm Predefined. */ +-/* USART_BSEL3_bp Predefined. */ +- +- +-/* SPI - Serial Peripheral Interface */ +-/* SPI.CTRL bit masks and bit positions */ +-#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +-#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ +- +-#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +-#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ +- +-#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +-#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ +- +-#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +-#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ +- +-#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +-#define SPI_MODE_gp 2 /* SPI Mode group position. */ +-#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +-#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +-#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +-#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ +- +-#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +-#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +-#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +-#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +-#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +-#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ +- +- +-/* SPI.INTCTRL bit masks and bit positions */ +-#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +-#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +-/* SPI.STATUS bit masks and bit positions */ +-#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +-#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ +- +-#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +-#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +- +- +-/* IRCOM - IR Communication Module */ +-/* IRCOM.CTRL bit masks and bit positions */ +-#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +-#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +-#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +-#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +-#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +-#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +-#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +-#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +-#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +-#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ +- +- +-/* AES - AES Module */ +-/* AES.CTRL bit masks and bit positions */ +-#define AES_START_bm 0x80 /* Start/Run bit mask. */ +-#define AES_START_bp 7 /* Start/Run bit position. */ +- +-#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ +-#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ +- +-#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ +-#define AES_RESET_bp 5 /* AES Software Reset bit position. */ +- +-#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ +-#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ +- +-#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ +-#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ +- +- +-/* AES.STATUS bit masks and bit positions */ +-#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ +-#define AES_ERROR_bp 7 /* AES Error bit position. */ +- +-#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ +-#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ +- +- +-/* AES.INTCTRL bit masks and bit positions */ +-#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define AES_INTLVL_gp 0 /* Interrupt level group position. */ +-#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +- +-// Generic Port Pins +- +-#define PIN0_bm 0x01 +-#define PIN0_bp 0 +-#define PIN1_bm 0x02 +-#define PIN1_bp 1 +-#define PIN2_bm 0x04 +-#define PIN2_bp 2 +-#define PIN3_bm 0x08 +-#define PIN3_bp 3 +-#define PIN4_bm 0x10 +-#define PIN4_bp 4 +-#define PIN5_bm 0x20 +-#define PIN5_bp 5 +-#define PIN6_bm 0x40 +-#define PIN6_bp 6 +-#define PIN7_bm 0x80 +-#define PIN7_bp 7 +- +- +-/* ========== Interrupt Vector Definitions ========== */ +-/* Vector 0 is the reset vector */ +- +-/* OSC interrupt vectors */ +-#define OSC_XOSCF_vect_num 1 +-#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ +- +-/* PORTC interrupt vectors */ +-#define PORTC_INT0_vect_num 2 +-#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +-#define PORTC_INT1_vect_num 3 +-#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ +- +-/* PORTR interrupt vectors */ +-#define PORTR_INT0_vect_num 4 +-#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +-#define PORTR_INT1_vect_num 5 +-#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ +- +-/* DMA interrupt vectors */ +-#define DMA_CH0_vect_num 6 +-#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ +-#define DMA_CH1_vect_num 7 +-#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ +-#define DMA_CH2_vect_num 8 +-#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ +-#define DMA_CH3_vect_num 9 +-#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ +- +-/* RTC interrupt vectors */ +-#define RTC_OVF_vect_num 10 +-#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +-#define RTC_COMP_vect_num 11 +-#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ +- +-/* TWIC interrupt vectors */ +-#define TWIC_TWIS_vect_num 12 +-#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +-#define TWIC_TWIM_vect_num 13 +-#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ +- +-/* TCC0 interrupt vectors */ +-#define TCC0_OVF_vect_num 14 +-#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +-#define TCC0_ERR_vect_num 15 +-#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +-#define TCC0_CCA_vect_num 16 +-#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +-#define TCC0_CCB_vect_num 17 +-#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +-#define TCC0_CCC_vect_num 18 +-#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +-#define TCC0_CCD_vect_num 19 +-#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ +- +-/* TCC1 interrupt vectors */ +-#define TCC1_OVF_vect_num 20 +-#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +-#define TCC1_ERR_vect_num 21 +-#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +-#define TCC1_CCA_vect_num 22 +-#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +-#define TCC1_CCB_vect_num 23 +-#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ +- +-/* SPIC interrupt vectors */ +-#define SPIC_INT_vect_num 24 +-#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ +- +-/* USARTC0 interrupt vectors */ +-#define USARTC0_RXC_vect_num 25 +-#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +-#define USARTC0_DRE_vect_num 26 +-#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +-#define USARTC0_TXC_vect_num 27 +-#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ +- +-/* USARTC1 interrupt vectors */ +-#define USARTC1_RXC_vect_num 28 +-#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ +-#define USARTC1_DRE_vect_num 29 +-#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ +-#define USARTC1_TXC_vect_num 30 +-#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ +- +-/* AES interrupt vectors */ +-#define AES_INT_vect_num 31 +-#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ +- +-/* NVM interrupt vectors */ +-#define NVM_EE_vect_num 32 +-#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +-#define NVM_SPM_vect_num 33 +-#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ +- +-/* PORTB interrupt vectors */ +-#define PORTB_INT0_vect_num 34 +-#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +-#define PORTB_INT1_vect_num 35 +-#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ +- +-/* ACB interrupt vectors */ +-#define ACB_AC0_vect_num 36 +-#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ +-#define ACB_AC1_vect_num 37 +-#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ +-#define ACB_ACW_vect_num 38 +-#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ +- +-/* ADCB interrupt vectors */ +-#define ADCB_CH0_vect_num 39 +-#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ +-#define ADCB_CH1_vect_num 40 +-#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ +-#define ADCB_CH2_vect_num 41 +-#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ +-#define ADCB_CH3_vect_num 42 +-#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ +- +-/* PORTE interrupt vectors */ +-#define PORTE_INT0_vect_num 43 +-#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +-#define PORTE_INT1_vect_num 44 +-#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ +- +-/* TWIE interrupt vectors */ +-#define TWIE_TWIS_vect_num 45 +-#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ +-#define TWIE_TWIM_vect_num 46 +-#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ +- +-/* TCE0 interrupt vectors */ +-#define TCE0_OVF_vect_num 47 +-#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +-#define TCE0_ERR_vect_num 48 +-#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +-#define TCE0_CCA_vect_num 49 +-#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +-#define TCE0_CCB_vect_num 50 +-#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +-#define TCE0_CCC_vect_num 51 +-#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +-#define TCE0_CCD_vect_num 52 +-#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ +- +-/* TCE1 interrupt vectors */ +-#define TCE1_OVF_vect_num 53 +-#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ +-#define TCE1_ERR_vect_num 54 +-#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ +-#define TCE1_CCA_vect_num 55 +-#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ +-#define TCE1_CCB_vect_num 56 +-#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ +- +-/* SPIE interrupt vectors */ +-#define SPIE_INT_vect_num 57 +-#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ +- +-/* USARTE0 interrupt vectors */ +-#define USARTE0_RXC_vect_num 58 +-#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +-#define USARTE0_DRE_vect_num 59 +-#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +-#define USARTE0_TXC_vect_num 60 +-#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ +- +-/* USARTE1 interrupt vectors */ +-#define USARTE1_RXC_vect_num 61 +-#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ +-#define USARTE1_DRE_vect_num 62 +-#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ +-#define USARTE1_TXC_vect_num 63 +-#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ +- +-/* PORTD interrupt vectors */ +-#define PORTD_INT0_vect_num 64 +-#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +-#define PORTD_INT1_vect_num 65 +-#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ +- +-/* PORTA interrupt vectors */ +-#define PORTA_INT0_vect_num 66 +-#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +-#define PORTA_INT1_vect_num 67 +-#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ +- +-/* ACA interrupt vectors */ +-#define ACA_AC0_vect_num 68 +-#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +-#define ACA_AC1_vect_num 69 +-#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +-#define ACA_ACW_vect_num 70 +-#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ +- +-/* ADCA interrupt vectors */ +-#define ADCA_CH0_vect_num 71 +-#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +-#define ADCA_CH1_vect_num 72 +-#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ +-#define ADCA_CH2_vect_num 73 +-#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ +-#define ADCA_CH3_vect_num 74 +-#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ +- +-/* TCD0 interrupt vectors */ +-#define TCD0_OVF_vect_num 77 +-#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +-#define TCD0_ERR_vect_num 78 +-#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +-#define TCD0_CCA_vect_num 79 +-#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +-#define TCD0_CCB_vect_num 80 +-#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +-#define TCD0_CCC_vect_num 81 +-#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +-#define TCD0_CCD_vect_num 82 +-#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ +- +-/* TCD1 interrupt vectors */ +-#define TCD1_OVF_vect_num 83 +-#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ +-#define TCD1_ERR_vect_num 84 +-#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ +-#define TCD1_CCA_vect_num 85 +-#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ +-#define TCD1_CCB_vect_num 86 +-#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ +- +-/* SPID interrupt vectors */ +-#define SPID_INT_vect_num 87 +-#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ +- +-/* USARTD0 interrupt vectors */ +-#define USARTD0_RXC_vect_num 88 +-#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +-#define USARTD0_DRE_vect_num 89 +-#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +-#define USARTD0_TXC_vect_num 90 +-#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ +- +-/* USARTD1 interrupt vectors */ +-#define USARTD1_RXC_vect_num 91 +-#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ +-#define USARTD1_DRE_vect_num 92 +-#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ +-#define USARTD1_TXC_vect_num 93 +-#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ +- +-/* PORTF interrupt vectors */ +-#define PORTF_INT0_vect_num 104 +-#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +-#define PORTF_INT1_vect_num 105 +-#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ +- +-/* TCF0 interrupt vectors */ +-#define TCF0_OVF_vect_num 108 +-#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ +-#define TCF0_ERR_vect_num 109 +-#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ +-#define TCF0_CCA_vect_num 110 +-#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ +-#define TCF0_CCB_vect_num 111 +-#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ +-#define TCF0_CCC_vect_num 112 +-#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ +-#define TCF0_CCD_vect_num 113 +-#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ +- +-/* USARTF0 interrupt vectors */ +-#define USARTF0_RXC_vect_num 119 +-#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ +-#define USARTF0_DRE_vect_num 120 +-#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ +-#define USARTF0_TXC_vect_num 121 +-#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ +- +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (122 * _VECTOR_SIZE) +- +- +-/* ========== Constants ========== */ +- +-#define PROGMEM_START (0x0000) +-#define PROGMEM_SIZE (69632) +-#define PROGMEM_PAGE_SIZE (256) +-#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) +- +-#define APP_SECTION_START (0x0000) +-#define APP_SECTION_SIZE (65536) +-#define APP_SECTION_PAGE_SIZE (256) +-#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) +- +-#define APPTABLE_SECTION_START (0x0F000) +-#define APPTABLE_SECTION_SIZE (4096) +-#define APPTABLE_SECTION_PAGE_SIZE (256) +-#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) +- +-#define BOOT_SECTION_START (0x10000) +-#define BOOT_SECTION_SIZE (4096) +-#define BOOT_SECTION_PAGE_SIZE (256) +-#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) +- +-#define DATAMEM_START (0x0000) +-#define DATAMEM_SIZE (12288) +-#define DATAMEM_PAGE_SIZE (0) +-#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) +- +-#define IO_START (0x0000) +-#define IO_SIZE (4096) +-#define IO_PAGE_SIZE (0) +-#define IO_END (IO_START + IO_SIZE - 1) +- +-#define MAPPED_EEPROM_START (0x1000) +-#define MAPPED_EEPROM_SIZE (2048) +-#define MAPPED_EEPROM_PAGE_SIZE (0) +-#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) +- +-#define INTERNAL_SRAM_START (0x2000) +-#define INTERNAL_SRAM_SIZE (4096) +-#define INTERNAL_SRAM_PAGE_SIZE (0) +-#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) +- +-#define EEPROM_START (0x0000) +-#define EEPROM_SIZE (2048) +-#define EEPROM_PAGE_SIZE (32) +-#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) +- +-#define FUSE_START (0x0000) +-#define FUSE_SIZE (6) +-#define FUSE_PAGE_SIZE (0) +-#define FUSE_END (FUSE_START + FUSE_SIZE - 1) +- +-#define LOCKBIT_START (0x0000) +-#define LOCKBIT_SIZE (1) +-#define LOCKBIT_PAGE_SIZE (0) +-#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) +- +-#define SIGNATURES_START (0x0000) +-#define SIGNATURES_SIZE (3) +-#define SIGNATURES_PAGE_SIZE (0) +-#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) +- +-#define USER_SIGNATURES_START (0x0000) +-#define USER_SIGNATURES_SIZE (256) +-#define USER_SIGNATURES_PAGE_SIZE (0) +-#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) +- +-#define PROD_SIGNATURES_START (0x0000) +-#define PROD_SIGNATURES_SIZE (52) +-#define PROD_SIGNATURES_PAGE_SIZE (0) +-#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) +- +-#define FLASHEND PROGMEM_END +-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +-#define RAMSTART INTERNAL_SRAM_START +-#define RAMSIZE INTERNAL_SRAM_SIZE +-#define RAMEND INTERNAL_SRAM_END +-#define XRAMSTART EXTERNAL_SRAM_START +-#define XRAMSIZE EXTERNAL_SRAM_SIZE +-#define XRAMEND INTERNAL_SRAM_END +-#define E2END EEPROM_END +-#define E2PAGESIZE EEPROM_PAGE_SIZE +- +- +-/* ========== Fuses ========== */ +-#define FUSE_MEMORY_SIZE 6 +- +-/* Fuse Byte 0 */ +-#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ +-#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ +-#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ +-#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ +-#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ +-#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ +-#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ +-#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ +-#define FUSE0_DEFAULT (0xFF) +- +-/* Fuse Byte 1 */ +-#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +-#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +-#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +-#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +-#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +-#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +-#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +-#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +-#define FUSE1_DEFAULT (0xFF) +- +-/* Fuse Byte 2 */ +-#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +-#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +-#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +-#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +-#define FUSE2_DEFAULT (0xFF) +- +-/* Fuse Byte 3 Reserved */ +- +-/* Fuse Byte 4 */ +-#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ +-#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +-#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +-#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +-#define FUSE4_DEFAULT (0xFF) +- +-/* Fuse Byte 5 */ +-#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +-#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +-#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +-#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +-#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +-#define FUSE5_DEFAULT (0xFF) +- +- +-/* ========== Lock Bits ========== */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_BITS_EXIST +-#define __BOOT_LOCK_BOOT_BITS_EXIST +- +- +-/* ========== Signature ========== */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x96 +-#define SIGNATURE_2 0x42 +- +- +-#endif /* _AVR_ATxmega64A3_H_ */ +- ++/* Copyright (c) 2009-2010 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iox64a3.h 2200 2010-12-14 04:24:24Z arcanum $ */ ++ ++/* avr/iox64a3.h - definitions for ATxmega64A3 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox64a3.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATxmega64A3_H_ ++#define _AVR_ATxmega64A3_H_ 1 ++ ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++} CLK_t; ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t PRPB; /* Power Reduction Port B */ ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ ++} CLK_RTCSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control REgister */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.125s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.25s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.5s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t reserved_0x07; ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Channel */ ++typedef struct DMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Address Control */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ ++ register8_t REPCNT; /* Channel Repeat Count */ ++ register8_t reserved_0x07; ++ register8_t SRCADDR0; /* Channel Source Address 0 */ ++ register8_t SRCADDR1; /* Channel Source Address 1 */ ++ register8_t SRCADDR2; /* Channel Source Address 2 */ ++ register8_t reserved_0x0B; ++ register8_t DESTADDR0; /* Channel Destination Address 0 */ ++ register8_t DESTADDR1; /* Channel Destination Address 1 */ ++ register8_t DESTADDR2; /* Channel Destination Address 2 */ ++ register8_t reserved_0x0F; ++} DMA_CH_t; ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Controller */ ++typedef struct DMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ DMA_CH_t CH0; /* DMA Channel 0 */ ++ DMA_CH_t CH1; /* DMA Channel 1 */ ++ DMA_CH_t CH2; /* DMA Channel 2 */ ++ DMA_CH_t CH3; /* DMA Channel 3 */ ++} DMA_t; ++ ++/* Burst mode */ ++typedef enum DMA_CH_BURSTLEN_enum ++{ ++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ ++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ ++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ ++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ ++} DMA_CH_BURSTLEN_t; ++ ++/* Source address reload mode */ ++typedef enum DMA_CH_SRCRELOAD_enum ++{ ++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ ++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ ++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ ++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ ++} DMA_CH_SRCRELOAD_t; ++ ++/* Source addressing mode */ ++typedef enum DMA_CH_SRCDIR_enum ++{ ++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ ++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ ++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ ++} DMA_CH_SRCDIR_t; ++ ++/* Destination adress reload mode */ ++typedef enum DMA_CH_DESTRELOAD_enum ++{ ++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ ++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ ++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ ++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ ++} DMA_CH_DESTRELOAD_t; ++ ++/* Destination adressing mode */ ++typedef enum DMA_CH_DESTDIR_enum ++{ ++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ ++} DMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum DMA_CH_TRIGSRC_enum ++{ ++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ ++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ ++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ ++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ ++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ ++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ ++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ ++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ ++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ ++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ ++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ ++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ ++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ ++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ ++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ ++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ ++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ ++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ ++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ ++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ ++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ ++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ ++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ ++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ ++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ ++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ ++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ ++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ ++} DMA_CH_TRIGSRC_t; ++ ++/* Double buffering mode */ ++typedef enum DMA_DBUFMODE_enum ++{ ++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ ++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ ++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ ++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ ++} DMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum DMA_PRIMODE_enum ++{ ++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ ++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ ++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ ++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ ++} DMA_PRIMODE_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_ERRINTLVL_enum ++{ ++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ ++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ ++} DMA_CH_ERRINTLVL_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_TRNINTLVL_enum ++{ ++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ ++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ ++} DMA_CH_TRNINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ ++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ ++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ ++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t CH4CTRL; /* Channel 4 Control Register */ ++ register8_t CH5CTRL; /* Channel 5 Control Register */ ++ register8_t CH6CTRL; /* Channel 6 Control Register */ ++ register8_t CH7CTRL; /* Channel 7 Control Register */ ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ ++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ ++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ ++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ ++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ ++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ ++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ ++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ ++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ ++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ ++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ ++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ ++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ ++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ ++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ ++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ ++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ ++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t FUSEBYTE0; /* JTAG User ID */ ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ ++ register8_t reserved_0x01; ++ register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ ++ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ ++ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ ++ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++} NVM_PROD_SIGNATURES_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++} NVM_LB_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brown Out Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ ++ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Comparator 0 Control */ ++ register8_t AC1CTRL; /* Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t reserved_0x6; ++ register8_t reserved_0x7; ++} ADC_CH_t; ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ _WORDREGISTER(CH1RES); /* Channel 1 Result */ ++ _WORDREGISTER(CH2RES); /* Channel 2 Result */ ++ _WORDREGISTER(CH3RES); /* Channel 3 Result */ ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++ ADC_CH_t CH1; /* ADC Channel 1 */ ++ ADC_CH_t CH2; /* ADC Channel 2 */ ++ ADC_CH_t CH3; /* ADC Channel 3 */ ++} ADC_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6V */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++} ADC_REFSEL_t; ++ ++/* Channel sweep selection */ ++typedef enum ADC_SWEEP_enum ++{ ++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ ++} ADC_SWEEP_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ++ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized sweep */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* DMA request selection */ ++typedef enum ADC_DMASEL_enum ++{ ++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ ++} ADC_DMASEL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DAC - Digital/Analog Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Digital-to-Analog Converter */ ++typedef struct DAC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t EVCTRL; /* Event Input Control */ ++ register8_t TIMCTRL; /* Timing Control */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t GAINCAL; /* Gain Calibration */ ++ register8_t OFFSETCAL; /* Offset Calibration */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ ++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ ++} DAC_t; ++ ++/* Output channel selection */ ++typedef enum DAC_CHSEL_enum ++{ ++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel A only) */ ++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (S/H on both channels) */ ++} DAC_CHSEL_t; ++ ++/* Reference voltage selection */ ++typedef enum DAC_REFSEL_enum ++{ ++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ ++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ ++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ ++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ ++} DAC_REFSEL_t; ++ ++/* Event channel selection */ ++typedef enum DAC_EVSEL_enum ++{ ++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ ++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ ++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ ++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ ++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ ++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ ++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ ++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ ++} DAC_EVSEL_t; ++ ++/* Conversion interval */ ++typedef enum DAC_CONINTVAL_enum ++{ ++ DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */ ++ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */ ++ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */ ++ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */ ++ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */ ++ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */ ++ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */ ++ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */ ++} DAC_CONINTVAL_t; ++ ++/* Refresh rate */ ++typedef enum DAC_REFRESH_enum ++{ ++ DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */ ++ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */ ++ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */ ++ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */ ++ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */ ++ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */ ++ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */ ++ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */ ++ DAC_REFRESH_4096CLK_gc = (0x08<<0), /* 4096 CLK */ ++ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */ ++ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */ ++ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */ ++ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */ ++ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */ ++} DAC_REFRESH_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Clounter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* EBI Chip Select Module */ ++typedef struct EBI_CS_struct ++{ ++ register8_t CTRLA; /* Chip Select Control Register A */ ++ register8_t CTRLB; /* Chip Select Control Register B */ ++ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ ++} EBI_CS_t; ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* External Bus Interface */ ++typedef struct EBI_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ ++ register8_t reserved_0x02; ++ register8_t reserved_0x03; ++ _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ ++ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ ++ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ ++ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ EBI_CS_t CS0; /* Chip Select 0 */ ++ EBI_CS_t CS1; /* Chip Select 1 */ ++ EBI_CS_t CS2; /* Chip Select 2 */ ++ EBI_CS_t CS3; /* Chip Select 3 */ ++} EBI_t; ++ ++/* Chip Select adress space */ ++typedef enum EBI_CS_ASIZE_enum ++{ ++ EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ ++ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ ++ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ ++ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ ++ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ ++ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ ++ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ ++ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ ++ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ ++ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ ++ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ ++ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ ++ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ ++ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ ++ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ ++ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ ++ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ ++} EBI_CS_ASIZE_t; ++ ++/* */ ++typedef enum EBI_CS_SRWS_enum ++{ ++ EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_CS_SRWS_t; ++ ++/* Chip Select address mode */ ++typedef enum EBI_CS_MODE_enum ++{ ++ EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ ++ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ ++ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ ++ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ ++} EBI_CS_MODE_t; ++ ++/* Chip Select SDRAM mode */ ++typedef enum EBI_CS_SDMODE_enum ++{ ++ EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ ++ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ ++} EBI_CS_SDMODE_t; ++ ++/* */ ++typedef enum EBI_SDDATAW_enum ++{ ++ EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ ++ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ ++} EBI_SDDATAW_t; ++ ++/* */ ++typedef enum EBI_LPCMODE_enum ++{ ++ EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ ++ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ ++} EBI_LPCMODE_t; ++ ++/* */ ++typedef enum EBI_SRMODE_enum ++{ ++ EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ ++ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ ++ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ ++ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ ++} EBI_SRMODE_t; ++ ++/* */ ++typedef enum EBI_IFMODE_enum ++{ ++ EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ ++ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ ++ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ ++ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ ++} EBI_IFMODE_t; ++ ++/* */ ++typedef enum EBI_SDCOL_enum ++{ ++ EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ ++ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ ++ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ ++ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ ++} EBI_SDCOL_t; ++ ++/* */ ++typedef enum EBI_MRDLY_enum ++{ ++ EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_MRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCYCDLY_enum ++{ ++ EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ROWCYCDLY_t; ++ ++/* */ ++typedef enum EBI_RPDLY_enum ++{ ++ EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_RPDLY_t; ++ ++/* */ ++typedef enum EBI_WRDLY_enum ++{ ++ EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_WRDLY_t; ++ ++/* */ ++typedef enum EBI_ESRDLY_enum ++{ ++ EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ESRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCOLDLY_enum ++{ ++ EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_ROWCOLDLY_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++} PORTCFG_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Virtual Port 0 Mapping */ ++typedef enum PORTCFG_VP0MAP_enum ++{ ++ PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP0MAP_t; ++ ++/* Virtual Port 1 Mapping */ ++typedef enum PORTCFG_VP1MAP_enum ++{ ++ PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP1MAP_t; ++ ++/* Virtual Port 2 Mapping */ ++typedef enum PORTCFG_VP2MAP_enum ++{ ++ PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP2MAP_t; ++ ++/* Virtual Port 3 Mapping */ ++typedef enum PORTCFG_VP3MAP_enum ++{ ++ PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP3MAP_t; ++ ++/* Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x05; ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRW_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AES - AES Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* AES Module */ ++typedef struct AES_struct ++{ ++ register8_t CTRL; /* AES Control Register */ ++ register8_t STATUS; /* AES Status Register */ ++ register8_t STATE; /* AES State Register */ ++ register8_t KEY; /* AES Key Register */ ++ register8_t INTCTRL; /* AES Interrupt Control Register */ ++} AES_t; ++ ++/* Interrupt level */ ++typedef enum AES_INTLVL_enum ++{ ++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} AES_INTLVL_t; ++ ++ ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset Controller */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ ++#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */ ++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ ++#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */ ++#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ ++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */ ++#define PORTA (*(PORT_t *) 0x0600) /* Port A */ ++#define PORTB (*(PORT_t *) 0x0620) /* Port B */ ++#define PORTC (*(PORT_t *) 0x0640) /* Port C */ ++#define PORTD (*(PORT_t *) 0x0660) /* Port D */ ++#define PORTE (*(PORT_t *) 0x0680) /* Port E */ ++#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ ++#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ ++#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ ++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous Receiver-Transmitter C1 */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ ++#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */ ++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ ++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous Receiver-Transmitter D1 */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ ++#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */ ++#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ ++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ ++#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous Receiver-Transmitter E1 */ ++#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ ++#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ ++#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */ ++#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous Receiver-Transmitter F0 */ ++#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous Receiver-Transmitter F1 */ ++#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++#define GPIO_GPIOR4 _SFR_MEM8(0x0004) ++#define GPIO_GPIOR5 _SFR_MEM8(0x0005) ++#define GPIO_GPIOR6 _SFR_MEM8(0x0006) ++#define GPIO_GPIOR7 _SFR_MEM8(0x0007) ++#define GPIO_GPIOR8 _SFR_MEM8(0x0008) ++#define GPIO_GPIOR9 _SFR_MEM8(0x0009) ++#define GPIO_GPIORA _SFR_MEM8(0x000A) ++#define GPIO_GPIORB _SFR_MEM8(0x000B) ++#define GPIO_GPIORC _SFR_MEM8(0x000C) ++#define GPIO_GPIORD _SFR_MEM8(0x000D) ++#define GPIO_GPIORE _SFR_MEM8(0x000E) ++#define GPIO_GPIORF _SFR_MEM8(0x000F) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++#define GPIO_GPIO4 _SFR_MEM8(0x0004) ++#define GPIO_GPIO5 _SFR_MEM8(0x0005) ++#define GPIO_GPIO6 _SFR_MEM8(0x0006) ++#define GPIO_GPIO7 _SFR_MEM8(0x0007) ++#define GPIO_GPIO8 _SFR_MEM8(0x0008) ++#define GPIO_GPIO9 _SFR_MEM8(0x0009) ++#define GPIO_GPIOA _SFR_MEM8(0x000A) ++#define GPIO_GPIOB _SFR_MEM8(0x000B) ++#define GPIO_GPIOC _SFR_MEM8(0x000C) ++#define GPIO_GPIOD _SFR_MEM8(0x000D) ++#define GPIO_GPIOE _SFR_MEM8(0x000E) ++#define GPIO_GPIOF _SFR_MEM8(0x000F) ++ ++/* VPORT0 - Virtual Port 0 */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT1 - Virtual Port 1 */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT2 - Virtual Port 2 */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT3 - Virtual Port 3 */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU Registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator Control */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPB _SFR_MEM8(0x0072) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset Controller */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - Port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++ ++/* AES - AES Crypto Module */ ++#define AES_CTRL _SFR_MEM8(0x00C0) ++#define AES_STATUS _SFR_MEM8(0x00C1) ++#define AES_STATE _SFR_MEM8(0x00C2) ++#define AES_KEY _SFR_MEM8(0x00C3) ++#define AES_INTCTRL _SFR_MEM8(0x00C4) ++ ++/* DMA - DMA Controller */ ++#define DMA_CTRL _SFR_MEM8(0x0100) ++#define DMA_INTFLAGS _SFR_MEM8(0x0103) ++#define DMA_STATUS _SFR_MEM8(0x0104) ++#define DMA_TEMP _SFR_MEM16(0x0106) ++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) ++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) ++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) ++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) ++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) ++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) ++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) ++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) ++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) ++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) ++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) ++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) ++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) ++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) ++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) ++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) ++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) ++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) ++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) ++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) ++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) ++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) ++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) ++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) ++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) ++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) ++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) ++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) ++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) ++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) ++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) ++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) ++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) ++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) ++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) ++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) ++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) ++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) ++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) ++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) ++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) ++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH4MUX _SFR_MEM8(0x0184) ++#define EVSYS_CH5MUX _SFR_MEM8(0x0185) ++#define EVSYS_CH6MUX _SFR_MEM8(0x0186) ++#define EVSYS_CH7MUX _SFR_MEM8(0x0187) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) ++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) ++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) ++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non Volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADCA - Analog to Digital Converter A */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CH1RES _SFR_MEM16(0x0212) ++#define ADCA_CH2RES _SFR_MEM16(0x0214) ++#define ADCA_CH3RES _SFR_MEM16(0x0216) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) ++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) ++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) ++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) ++#define ADCA_CH1_RES _SFR_MEM16(0x022C) ++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) ++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) ++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) ++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) ++#define ADCA_CH2_RES _SFR_MEM16(0x0234) ++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) ++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) ++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) ++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) ++#define ADCA_CH3_RES _SFR_MEM16(0x023C) ++ ++/* ADCB - Analog to Digital Converter B */ ++#define ADCB_CTRLA _SFR_MEM8(0x0240) ++#define ADCB_CTRLB _SFR_MEM8(0x0241) ++#define ADCB_REFCTRL _SFR_MEM8(0x0242) ++#define ADCB_EVCTRL _SFR_MEM8(0x0243) ++#define ADCB_PRESCALER _SFR_MEM8(0x0244) ++#define ADCB_INTFLAGS _SFR_MEM8(0x0246) ++#define ADCB_CAL _SFR_MEM16(0x024C) ++#define ADCB_CH0RES _SFR_MEM16(0x0250) ++#define ADCB_CH1RES _SFR_MEM16(0x0252) ++#define ADCB_CH2RES _SFR_MEM16(0x0254) ++#define ADCB_CH3RES _SFR_MEM16(0x0256) ++#define ADCB_CMP _SFR_MEM16(0x0258) ++#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) ++#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) ++#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) ++#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) ++#define ADCB_CH0_RES _SFR_MEM16(0x0264) ++#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) ++#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) ++#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) ++#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) ++#define ADCB_CH1_RES _SFR_MEM16(0x026C) ++#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) ++#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) ++#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) ++#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) ++#define ADCB_CH2_RES _SFR_MEM16(0x0274) ++#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) ++#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) ++#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) ++#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) ++#define ADCB_CH3_RES _SFR_MEM16(0x027C) ++ ++/* DACB - Digital to Analog Converter B */ ++#define DACB_CTRLA _SFR_MEM8(0x0320) ++#define DACB_CTRLB _SFR_MEM8(0x0321) ++#define DACB_CTRLC _SFR_MEM8(0x0322) ++#define DACB_EVCTRL _SFR_MEM8(0x0323) ++#define DACB_TIMCTRL _SFR_MEM8(0x0324) ++#define DACB_STATUS _SFR_MEM8(0x0325) ++#define DACB_GAINCAL _SFR_MEM8(0x0328) ++#define DACB_OFFSETCAL _SFR_MEM8(0x0329) ++#define DACB_CH0DATA _SFR_MEM16(0x0338) ++#define DACB_CH1DATA _SFR_MEM16(0x033A) ++ ++/* ACA - Analog Comparator A */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* ACB - Analog Comparator B */ ++#define ACB_AC0CTRL _SFR_MEM8(0x0390) ++#define ACB_AC1CTRL _SFR_MEM8(0x0391) ++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) ++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) ++#define ACB_CTRLA _SFR_MEM8(0x0394) ++#define ACB_CTRLB _SFR_MEM8(0x0395) ++#define ACB_WINCTRL _SFR_MEM8(0x0396) ++#define ACB_STATUS _SFR_MEM8(0x0397) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWIC - Two-Wire Interface C */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWIE - Two-Wire Interface E */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* PORTA - Port A */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORTB - Port B */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORTC - Port C */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORTD - Port D */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORTE - Port E */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORTF - Port F */ ++#define PORTF_DIR _SFR_MEM8(0x06A0) ++#define PORTF_DIRSET _SFR_MEM8(0x06A1) ++#define PORTF_DIRCLR _SFR_MEM8(0x06A2) ++#define PORTF_DIRTGL _SFR_MEM8(0x06A3) ++#define PORTF_OUT _SFR_MEM8(0x06A4) ++#define PORTF_OUTSET _SFR_MEM8(0x06A5) ++#define PORTF_OUTCLR _SFR_MEM8(0x06A6) ++#define PORTF_OUTTGL _SFR_MEM8(0x06A7) ++#define PORTF_IN _SFR_MEM8(0x06A8) ++#define PORTF_INTCTRL _SFR_MEM8(0x06A9) ++#define PORTF_INT0MASK _SFR_MEM8(0x06AA) ++#define PORTF_INT1MASK _SFR_MEM8(0x06AB) ++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) ++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) ++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) ++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) ++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) ++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) ++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) ++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) ++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) ++ ++/* PORTR - Port R */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TCC0 - Timer/Counter C0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TCC1 - Timer/Counter C1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEXC - Advanced Waveform Extension C */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRESC - High-Resolution Extension C */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */ ++#define USARTC1_DATA _SFR_MEM8(0x08B0) ++#define USARTC1_STATUS _SFR_MEM8(0x08B1) ++#define USARTC1_CTRLA _SFR_MEM8(0x08B3) ++#define USARTC1_CTRLB _SFR_MEM8(0x08B4) ++#define USARTC1_CTRLC _SFR_MEM8(0x08B5) ++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) ++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) ++ ++/* SPIC - Serial Peripheral Interface C */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TCD0 - Timer/Counter D0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TCD1 - Timer/Counter D1 */ ++#define TCD1_CTRLA _SFR_MEM8(0x0940) ++#define TCD1_CTRLB _SFR_MEM8(0x0941) ++#define TCD1_CTRLC _SFR_MEM8(0x0942) ++#define TCD1_CTRLD _SFR_MEM8(0x0943) ++#define TCD1_CTRLE _SFR_MEM8(0x0944) ++#define TCD1_INTCTRLA _SFR_MEM8(0x0946) ++#define TCD1_INTCTRLB _SFR_MEM8(0x0947) ++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) ++#define TCD1_CTRLFSET _SFR_MEM8(0x0949) ++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) ++#define TCD1_CTRLGSET _SFR_MEM8(0x094B) ++#define TCD1_INTFLAGS _SFR_MEM8(0x094C) ++#define TCD1_TEMP _SFR_MEM8(0x094F) ++#define TCD1_CNT _SFR_MEM16(0x0960) ++#define TCD1_PER _SFR_MEM16(0x0966) ++#define TCD1_CCA _SFR_MEM16(0x0968) ++#define TCD1_CCB _SFR_MEM16(0x096A) ++#define TCD1_PERBUF _SFR_MEM16(0x0976) ++#define TCD1_CCABUF _SFR_MEM16(0x0978) ++#define TCD1_CCBBUF _SFR_MEM16(0x097A) ++ ++/* HIRESD - High-Resolution Extension D */ ++#define HIRESD_CTRLA _SFR_MEM8(0x0990) ++ ++/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */ ++#define USARTD1_DATA _SFR_MEM8(0x09B0) ++#define USARTD1_STATUS _SFR_MEM8(0x09B1) ++#define USARTD1_CTRLA _SFR_MEM8(0x09B3) ++#define USARTD1_CTRLB _SFR_MEM8(0x09B4) ++#define USARTD1_CTRLC _SFR_MEM8(0x09B5) ++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) ++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) ++ ++/* SPID - Serial Peripheral Interface D */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TCE0 - Timer/Counter E0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* TCE1 - Timer/Counter E1 */ ++#define TCE1_CTRLA _SFR_MEM8(0x0A40) ++#define TCE1_CTRLB _SFR_MEM8(0x0A41) ++#define TCE1_CTRLC _SFR_MEM8(0x0A42) ++#define TCE1_CTRLD _SFR_MEM8(0x0A43) ++#define TCE1_CTRLE _SFR_MEM8(0x0A44) ++#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) ++#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) ++#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) ++#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) ++#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) ++#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) ++#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) ++#define TCE1_TEMP _SFR_MEM8(0x0A4F) ++#define TCE1_CNT _SFR_MEM16(0x0A60) ++#define TCE1_PER _SFR_MEM16(0x0A66) ++#define TCE1_CCA _SFR_MEM16(0x0A68) ++#define TCE1_CCB _SFR_MEM16(0x0A6A) ++#define TCE1_PERBUF _SFR_MEM16(0x0A76) ++#define TCE1_CCABUF _SFR_MEM16(0x0A78) ++#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) ++ ++/* AWEXE - Advanced Waveform Extension E */ ++#define AWEXE_CTRL _SFR_MEM8(0x0A80) ++#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) ++#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) ++#define AWEXE_STATUS _SFR_MEM8(0x0A84) ++#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) ++#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) ++#define AWEXE_DTLS _SFR_MEM8(0x0A88) ++#define AWEXE_DTHS _SFR_MEM8(0x0A89) ++#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) ++#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) ++#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) ++ ++/* HIRESE - High-Resolution Extension E */ ++#define HIRESE_CTRLA _SFR_MEM8(0x0A90) ++ ++/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */ ++#define USARTE1_DATA _SFR_MEM8(0x0AB0) ++#define USARTE1_STATUS _SFR_MEM8(0x0AB1) ++#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) ++#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) ++#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) ++#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) ++#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) ++ ++/* SPIE - Serial Peripheral Interface E */ ++#define SPIE_CTRL _SFR_MEM8(0x0AC0) ++#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) ++#define SPIE_STATUS _SFR_MEM8(0x0AC2) ++#define SPIE_DATA _SFR_MEM8(0x0AC3) ++ ++/* TCF0 - Timer/Counter F0 */ ++#define TCF0_CTRLA _SFR_MEM8(0x0B00) ++#define TCF0_CTRLB _SFR_MEM8(0x0B01) ++#define TCF0_CTRLC _SFR_MEM8(0x0B02) ++#define TCF0_CTRLD _SFR_MEM8(0x0B03) ++#define TCF0_CTRLE _SFR_MEM8(0x0B04) ++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) ++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) ++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) ++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) ++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF0_TEMP _SFR_MEM8(0x0B0F) ++#define TCF0_CNT _SFR_MEM16(0x0B20) ++#define TCF0_PER _SFR_MEM16(0x0B26) ++#define TCF0_CCA _SFR_MEM16(0x0B28) ++#define TCF0_CCB _SFR_MEM16(0x0B2A) ++#define TCF0_CCC _SFR_MEM16(0x0B2C) ++#define TCF0_CCD _SFR_MEM16(0x0B2E) ++#define TCF0_PERBUF _SFR_MEM16(0x0B36) ++#define TCF0_CCABUF _SFR_MEM16(0x0B38) ++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) ++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) ++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) ++ ++/* HIRESF - High-Resolution Extension F */ ++#define HIRESF_CTRLA _SFR_MEM8(0x0B90) ++ ++/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */ ++#define USARTF0_DATA _SFR_MEM8(0x0BA0) ++#define USARTF0_STATUS _SFR_MEM8(0x0BA1) ++#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) ++#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) ++#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) ++#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) ++#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) ++ ++/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */ ++#define USARTF1_DATA _SFR_MEM8(0x0BB0) ++#define USARTF1_STATUS _SFR_MEM8(0x0BB1) ++#define USARTF1_CTRLA _SFR_MEM8(0x0BB3) ++#define USARTF1_CTRLB _SFR_MEM8(0x0BB4) ++#define USARTF1_CTRLC _SFR_MEM8(0x0BB5) ++#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6) ++#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7) ++ ++/* SPIF - Serial Peripheral Interface F */ ++#define SPIF_CTRL _SFR_MEM8(0x0BC0) ++#define SPIF_INTCTRL _SFR_MEM8(0x0BC1) ++#define SPIF_STATUS _SFR_MEM8(0x0BC2) ++#define SPIF_DATA _SFR_MEM8(0x0BC3) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR1 bit masks and bit positions */ ++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ ++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ ++ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ ++ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ ++#define PR_EBI_bp 3 /* External Bus Interface bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ ++#define PR_DAC_bp 2 /* Port A DAC bit position. */ ++ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++ ++/* PR.PRPB bit masks and bit positions */ ++/* PR_DAC_bm Predefined. */ ++/* PR_DAC_bp Predefined. */ ++ ++/* PR_ADC_bm Predefined. */ ++/* PR_ADC_bp Predefined. */ ++ ++/* PR_AC_bm Predefined. */ ++/* PR_AC_bp Predefined. */ ++ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART1_bm Predefined. */ ++/* PR_USART1_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_HIRES_bm Predefined. */ ++/* PR_HIRES_bp Predefined. */ ++ ++/* PR_TC1_bm Predefined. */ ++/* PR_TC1_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ ++ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ ++ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ ++ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ ++#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ ++ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ ++ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ ++ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ ++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ ++ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++ ++/* DMA - DMA Controller */ ++/* DMA_CH.CTRLA bit masks and bit positions */ ++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ ++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ ++ ++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ ++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ ++ ++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ ++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ ++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ ++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ ++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ ++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ ++ ++ ++/* DMA_CH.CTRLB bit masks and bit positions */ ++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ ++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ ++ ++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ ++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ ++ ++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ ++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ ++ ++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ ++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ ++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ ++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ ++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ ++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ ++ ++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ ++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ ++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ ++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ ++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ ++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ ++ ++ ++/* DMA_CH.ADDRCTRL bit masks and bit positions */ ++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ ++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ ++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ ++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ ++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ ++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ ++ ++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ ++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ ++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ ++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ ++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ ++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ ++ ++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ ++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ ++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ ++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ ++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ ++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ ++ ++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ ++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ ++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ ++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ ++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ ++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ ++ ++ ++/* DMA_CH.TRIGSRC bit masks and bit positions */ ++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++ ++/* DMA.CTRL bit masks and bit positions */ ++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define DMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define DMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ ++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ ++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ ++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ ++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ ++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ ++ ++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ ++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ ++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ ++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ ++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ ++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ ++ ++ ++/* DMA.INTFLAGS bit masks and bit positions */ ++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++ ++/* DMA.STATUS bit masks and bit positions */ ++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ ++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ ++ ++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ ++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ ++ ++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ ++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ ++ ++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ ++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ ++ ++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ ++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ ++ ++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ ++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ ++ ++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ ++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ ++ ++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ ++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ ++ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH4MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH5MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH6MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH7MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM_gm Predefined. */ ++/* EVSYS_QDIRM_gp Predefined. */ ++/* EVSYS_QDIRM0_bm Predefined. */ ++/* EVSYS_QDIRM0_bp Predefined. */ ++/* EVSYS_QDIRM1_bm Predefined. */ ++/* EVSYS_QDIRM1_bp Predefined. */ ++ ++/* EVSYS_QDIEN_bm Predefined. */ ++/* EVSYS_QDIEN_bp Predefined. */ ++ ++/* EVSYS_QDEN_bm Predefined. */ ++/* EVSYS_QDEN_bp Predefined. */ ++ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH4CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM_gm Predefined. */ ++/* EVSYS_QDIRM_gp Predefined. */ ++/* EVSYS_QDIRM0_bm Predefined. */ ++/* EVSYS_QDIRM0_bp Predefined. */ ++/* EVSYS_QDIRM1_bm Predefined. */ ++/* EVSYS_QDIRM1_bp Predefined. */ ++ ++/* EVSYS_QDIEN_bm Predefined. */ ++/* EVSYS_QDIEN_bp Predefined. */ ++ ++/* EVSYS_QDEN_bm Predefined. */ ++/* EVSYS_QDEN_bp Predefined. */ ++ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH5CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH6CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH7CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0xFF /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ ++#define NVM_CMD7_bp 7 /* Command bit 7 position. */ ++ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ ++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ ++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ ++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ ++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ ++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ ++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ ++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ ++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ ++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ ++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ ++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ ++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ ++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ ++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ ++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ ++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ ++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ ++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ ++#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ ++ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ ++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ ++ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ ++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE_gm Predefined. */ ++/* AC_INTMODE_gp Predefined. */ ++/* AC_INTMODE0_bm Predefined. */ ++/* AC_INTMODE0_bp Predefined. */ ++/* AC_INTMODE1_bm Predefined. */ ++/* AC_INTMODE1_bp Predefined. */ ++ ++/* AC_INTLVL_gm Predefined. */ ++/* AC_INTLVL_gp Predefined. */ ++/* AC_INTLVL0_bm Predefined. */ ++/* AC_INTLVL0_bp Predefined. */ ++/* AC_INTLVL1_bm Predefined. */ ++/* AC_INTLVL1_bp Predefined. */ ++ ++/* AC_HSMODE_bm Predefined. */ ++/* AC_HSMODE_bp Predefined. */ ++ ++/* AC_HYSMODE_gm Predefined. */ ++/* AC_HYSMODE_gp Predefined. */ ++/* AC_HYSMODE0_bm Predefined. */ ++/* AC_HYSMODE0_bp Predefined. */ ++/* AC_HYSMODE1_bm Predefined. */ ++/* AC_HYSMODE1_bp Predefined. */ ++ ++/* AC_ENABLE_bm Predefined. */ ++/* AC_ENABLE_bp Predefined. */ ++ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS_gm Predefined. */ ++/* AC_MUXPOS_gp Predefined. */ ++/* AC_MUXPOS0_bm Predefined. */ ++/* AC_MUXPOS0_bp Predefined. */ ++/* AC_MUXPOS1_bm Predefined. */ ++/* AC_MUXPOS1_bp Predefined. */ ++/* AC_MUXPOS2_bm Predefined. */ ++/* AC_MUXPOS2_bp Predefined. */ ++ ++/* AC_MUXNEG_gm Predefined. */ ++/* AC_MUXNEG_gp Predefined. */ ++/* AC_MUXNEG0_bm Predefined. */ ++/* AC_MUXNEG0_bp Predefined. */ ++/* AC_MUXNEG1_bm Predefined. */ ++/* AC_MUXNEG1_bp Predefined. */ ++/* AC_MUXNEG2_bm Predefined. */ ++/* AC_MUXNEG2_bp Predefined. */ ++ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ ++ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ ++ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ ++ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ ++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ ++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ ++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ ++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ ++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ ++ ++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ ++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ ++ ++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ ++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ ++ ++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ ++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ ++ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ ++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ ++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ ++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ ++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ ++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ ++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ ++ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ ++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ ++ ++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ ++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ ++ ++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ ++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ ++ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++ ++/* DAC - Digital/Analog Converter */ ++/* DAC.CTRLA bit masks and bit positions */ ++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ ++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ ++ ++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ ++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ ++ ++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ ++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ ++ ++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ ++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ ++ ++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define DAC_ENABLE_bp 0 /* Enable bit position. */ ++ ++ ++/* DAC.CTRLB bit masks and bit positions */ ++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ ++#define DAC_CHSEL_gp 5 /* Channel Select group position. */ ++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ ++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ ++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ ++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ ++ ++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ ++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ ++ ++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ ++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ ++ ++ ++/* DAC.CTRLC bit masks and bit positions */ ++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ ++#define DAC_REFSEL_gp 3 /* Reference Select group position. */ ++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ ++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ ++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ ++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ ++ ++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ ++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ ++ ++ ++/* DAC.EVCTRL bit masks and bit positions */ ++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ ++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ ++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ ++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ ++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ ++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ ++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ ++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ ++ ++ ++/* DAC.TIMCTRL bit masks and bit positions */ ++#define DAC_CONINTVAL_gm 0x70 /* Conversion Intercal group mask. */ ++#define DAC_CONINTVAL_gp 4 /* Conversion Intercal group position. */ ++#define DAC_CONINTVAL0_bm (1<<4) /* Conversion Intercal bit 0 mask. */ ++#define DAC_CONINTVAL0_bp 4 /* Conversion Intercal bit 0 position. */ ++#define DAC_CONINTVAL1_bm (1<<5) /* Conversion Intercal bit 1 mask. */ ++#define DAC_CONINTVAL1_bp 5 /* Conversion Intercal bit 1 position. */ ++#define DAC_CONINTVAL2_bm (1<<6) /* Conversion Intercal bit 2 mask. */ ++#define DAC_CONINTVAL2_bp 6 /* Conversion Intercal bit 2 position. */ ++ ++#define DAC_REFRESH_gm 0x0F /* Refresh Timing Control group mask. */ ++#define DAC_REFRESH_gp 0 /* Refresh Timing Control group position. */ ++#define DAC_REFRESH0_bm (1<<0) /* Refresh Timing Control bit 0 mask. */ ++#define DAC_REFRESH0_bp 0 /* Refresh Timing Control bit 0 position. */ ++#define DAC_REFRESH1_bm (1<<1) /* Refresh Timing Control bit 1 mask. */ ++#define DAC_REFRESH1_bp 1 /* Refresh Timing Control bit 1 position. */ ++#define DAC_REFRESH2_bm (1<<2) /* Refresh Timing Control bit 2 mask. */ ++#define DAC_REFRESH2_bp 2 /* Refresh Timing Control bit 2 position. */ ++#define DAC_REFRESH3_bm (1<<3) /* Refresh Timing Control bit 3 mask. */ ++#define DAC_REFRESH3_bp 3 /* Refresh Timing Control bit 3 position. */ ++ ++ ++/* DAC.STATUS bit masks and bit positions */ ++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ ++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ ++ ++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ ++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ ++ ++ ++/* RTC - Real-Time Clounter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* EBI - External Bus Interface */ ++/* EBI_CS.CTRLA bit masks and bit positions */ ++#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ ++#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ ++#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ ++#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ ++#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ ++#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ ++#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ ++#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ ++#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ ++#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ ++#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ ++#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ ++ ++#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ ++#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ ++#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ ++#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ ++#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ ++#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ ++ ++ ++/* EBI_CS.CTRLB bit masks and bit positions */ ++#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ ++#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ ++#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ ++#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ ++#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ ++#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ ++#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ ++#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ ++ ++#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ ++#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ ++ ++#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ ++#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ ++ ++#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ ++#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ ++#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ ++#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ ++#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ ++#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ ++ ++ ++/* EBI.CTRL bit masks and bit positions */ ++#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ ++#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ ++#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ ++#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ ++#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ ++#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ ++ ++#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ ++#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ ++#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ ++#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ ++#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ ++#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ ++ ++#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ ++#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ ++#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ ++#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ ++#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ ++#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ ++ ++#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ ++#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ ++#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ ++#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ ++#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ ++#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLA bit masks and bit positions */ ++#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ ++#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ ++ ++#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ ++#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ ++ ++#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ ++#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ ++#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ ++#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ ++#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ ++#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLB bit masks and bit positions */ ++#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ ++#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ ++#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ ++#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ ++#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ ++#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ ++ ++#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ ++#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ ++#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ ++#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ ++#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ ++#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ ++#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ ++#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ ++ ++#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ ++#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ ++#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ ++#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ ++#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ ++#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ ++#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ ++#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ ++ ++ ++/* EBI.SDRAMCTRLC bit masks and bit positions */ ++#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ ++#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ ++#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ ++#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ ++#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ ++#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ ++ ++#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ ++#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ ++#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ ++#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ ++#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ ++#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ ++#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ ++#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ ++ ++#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ ++#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ ++#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ ++#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ ++#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ ++#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ ++#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ ++#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ ++ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ ++#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++ ++/* PORT - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ ++#define TC0_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ ++ ++#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD_gm Predefined. */ ++/* TC0_CMD_gp Predefined. */ ++/* TC0_CMD0_bm Predefined. */ ++/* TC0_CMD0_bp Predefined. */ ++/* TC0_CMD1_bm Predefined. */ ++/* TC0_CMD1_bp Predefined. */ ++ ++/* TC0_LUPD_bm Predefined. */ ++/* TC0_LUPD_bp Predefined. */ ++ ++/* TC0_DIR_bm Predefined. */ ++/* TC0_DIR_bp Predefined. */ ++ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV_bm Predefined. */ ++/* TC0_CCDBV_bp Predefined. */ ++ ++/* TC0_CCCBV_bm Predefined. */ ++/* TC0_CCCBV_bp Predefined. */ ++ ++/* TC0_CCBBV_bm Predefined. */ ++/* TC0_CCBBV_bp Predefined. */ ++ ++/* TC0_CCABV_bm Predefined. */ ++/* TC0_CCABV_bp Predefined. */ ++ ++/* TC0_PERBV_bm Predefined. */ ++/* TC0_PERBV_bp Predefined. */ ++ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_DTHM_bm 0x02 /* Dead Time Hold Mode bit mask. */ ++#define TC1_DTHM_bp 1 /* Dead Time Hold Mode bit position. */ ++ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD_gm Predefined. */ ++/* TC1_CMD_gp Predefined. */ ++/* TC1_CMD0_bm Predefined. */ ++/* TC1_CMD0_bp Predefined. */ ++/* TC1_CMD1_bm Predefined. */ ++/* TC1_CMD1_bp Predefined. */ ++ ++/* TC1_LUPD_bm Predefined. */ ++/* TC1_LUPD_bp Predefined. */ ++ ++/* TC1_DIR_bm Predefined. */ ++/* TC1_DIR_bp Predefined. */ ++ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV_bm Predefined. */ ++/* TC1_CCBBV_bp Predefined. */ ++ ++/* TC1_CCABV_bm Predefined. */ ++/* TC1_CCABV_bp Predefined. */ ++ ++/* TC1_PERBV_bm Predefined. */ ++/* TC1_PERBV_bp Predefined. */ ++ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++ ++/* HIRES.CTRL bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL_gm Predefined. */ ++/* USART_BSEL_gp Predefined. */ ++/* USART_BSEL0_bm Predefined. */ ++/* USART_BSEL0_bp Predefined. */ ++/* USART_BSEL1_bm Predefined. */ ++/* USART_BSEL1_bp Predefined. */ ++/* USART_BSEL2_bm Predefined. */ ++/* USART_BSEL2_bp Predefined. */ ++/* USART_BSEL3_bm Predefined. */ ++/* USART_BSEL3_bp Predefined. */ ++ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++ ++/* AES - AES Module */ ++/* AES.CTRL bit masks and bit positions */ ++#define AES_START_bm 0x80 /* Start/Run bit mask. */ ++#define AES_START_bp 7 /* Start/Run bit position. */ ++ ++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ ++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ ++ ++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ ++#define AES_RESET_bp 5 /* AES Software Reset bit position. */ ++ ++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ ++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ ++ ++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ ++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ ++ ++ ++/* AES.STATUS bit masks and bit positions */ ++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ ++#define AES_ERROR_bp 7 /* AES Error bit position. */ ++ ++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ ++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ ++ ++ ++/* AES.INTCTRL bit masks and bit positions */ ++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define AES_INTLVL_gp 0 /* Interrupt level group position. */ ++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_XOSCF_vect_num 1 ++#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* DMA interrupt vectors */ ++#define DMA_CH0_vect_num 6 ++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ ++#define DMA_CH1_vect_num 7 ++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ ++#define DMA_CH2_vect_num 8 ++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ ++#define DMA_CH3_vect_num 9 ++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* USARTC1 interrupt vectors */ ++#define USARTC1_RXC_vect_num 28 ++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ ++#define USARTC1_DRE_vect_num 29 ++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ ++#define USARTC1_TXC_vect_num 30 ++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ ++ ++/* AES interrupt vectors */ ++#define AES_INT_vect_num 31 ++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* ACB interrupt vectors */ ++#define ACB_AC0_vect_num 36 ++#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ ++#define ACB_AC1_vect_num 37 ++#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ ++#define ACB_ACW_vect_num 38 ++#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ ++ ++/* ADCB interrupt vectors */ ++#define ADCB_CH0_vect_num 39 ++#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ ++#define ADCB_CH1_vect_num 40 ++#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ ++#define ADCB_CH2_vect_num 41 ++#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ ++#define ADCB_CH3_vect_num 42 ++#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* TCE1 interrupt vectors */ ++#define TCE1_OVF_vect_num 53 ++#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ ++#define TCE1_ERR_vect_num 54 ++#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ ++#define TCE1_CCA_vect_num 55 ++#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ ++#define TCE1_CCB_vect_num 56 ++#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ ++ ++/* SPIE interrupt vectors */ ++#define SPIE_INT_vect_num 57 ++#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* USARTE1 interrupt vectors */ ++#define USARTE1_RXC_vect_num 61 ++#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ ++#define USARTE1_DRE_vect_num 62 ++#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ ++#define USARTE1_TXC_vect_num 63 ++#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++#define ADCA_CH1_vect_num 72 ++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ ++#define ADCA_CH2_vect_num 73 ++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ ++#define ADCA_CH3_vect_num 74 ++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD1 interrupt vectors */ ++#define TCD1_OVF_vect_num 83 ++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ ++#define TCD1_ERR_vect_num 84 ++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ ++#define TCD1_CCA_vect_num 85 ++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ ++#define TCD1_CCB_vect_num 86 ++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* USARTD1 interrupt vectors */ ++#define USARTD1_RXC_vect_num 91 ++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ ++#define USARTD1_DRE_vect_num 92 ++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ ++#define USARTD1_TXC_vect_num 93 ++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ ++ ++/* PORTF interrupt vectors */ ++#define PORTF_INT0_vect_num 104 ++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ ++#define PORTF_INT1_vect_num 105 ++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_OVF_vect_num 108 ++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ ++#define TCF0_ERR_vect_num 109 ++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ ++#define TCF0_CCA_vect_num 110 ++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ ++#define TCF0_CCB_vect_num 111 ++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ ++#define TCF0_CCC_vect_num 112 ++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ ++#define TCF0_CCD_vect_num 113 ++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ ++ ++/* USARTF0 interrupt vectors */ ++#define USARTF0_RXC_vect_num 119 ++#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ ++#define USARTF0_DRE_vect_num 120 ++#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ ++#define USARTF0_TXC_vect_num 121 ++#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ ++ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (122 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (69632) ++#define PROGMEM_PAGE_SIZE (256) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (65536) ++#define APP_SECTION_PAGE_SIZE (256) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x0F000) ++#define APPTABLE_SECTION_SIZE (4096) ++#define APPTABLE_SECTION_PAGE_SIZE (256) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x10000) ++#define BOOT_SECTION_SIZE (4096) ++#define BOOT_SECTION_PAGE_SIZE (256) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (12288) ++#define DATAMEM_PAGE_SIZE (0) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (2048) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (4096) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (2048) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define FUSE_START (0x0000) ++#define FUSE_SIZE (6) ++#define FUSE_PAGE_SIZE (0) ++#define FUSE_END (FUSE_START + FUSE_SIZE - 1) ++ ++#define LOCKBIT_START (0x0000) ++#define LOCKBIT_SIZE (1) ++#define LOCKBIT_PAGE_SIZE (0) ++#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (256) ++#define USER_SIGNATURES_PAGE_SIZE (0) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (0) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE PROGMEM_PAGE_SIZE ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define XRAMSTART EXTERNAL_SRAM_START ++#define XRAMSIZE EXTERNAL_SRAM_SIZE ++#define XRAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 */ ++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ ++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ ++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ ++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ ++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ ++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ ++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ ++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ ++#define FUSE0_DEFAULT (0xFF) ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x42 ++ ++ ++#endif /* _AVR_ATxmega64A3_H_ */ ++ +diff --git a/include/avr/iox64a3u.h b/include/avr/iox64a3u.h +new file mode 100644 +index 0000000..1f74e5a +--- /dev/null ++++ b/include/avr/iox64a3u.h +@@ -0,0 +1,7628 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox64a3u.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA64A3U_H_INCLUDED ++#define _AVR_ATXMEGA64A3U_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t USBCTRL; /* USB Control Register */ ++} CLK_t; ++ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t PRPB; /* Power Reduction Port B */ ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++/* USB Prescaler Division Factor */ ++typedef enum CLK_USBPSDIV_enum ++{ ++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ ++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ ++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ ++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ ++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ ++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ ++} CLK_USBPSDIV_t; ++ ++/* USB Clock Source */ ++typedef enum CLK_USBSRC_enum ++{ ++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ ++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ ++} CLK_USBSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 2 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC2MCREF_enum ++{ ++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC2MCREF_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++ register8_t EBIOUT; /* EBI Output register */ ++ register8_t EVOUTSEL; /* Event Output Select */ ++} PORTCFG_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP02MAP_enum ++{ ++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP02MAP_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP13MAP_enum ++{ ++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP13MAP_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Clock and Event Output Port */ ++typedef enum PORTCFG_CLKEVPIN_enum ++{ ++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ ++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ ++} PORTCFG_CLKEVPIN_t; ++ ++/* EBI Address Output Port */ ++typedef enum PORTCFG_EBIADROUT_enum ++{ ++ PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ ++ PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ ++ PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ ++ PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ ++} PORTCFG_EBIADROUT_t; ++ ++/* EBI Chip Select Output Port */ ++typedef enum PORTCFG_EBICSOUT_enum ++{ ++ PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ ++} PORTCFG_EBICSOUT_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ ++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ ++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ ++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ ++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AES - AES Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* AES Module */ ++typedef struct AES_struct ++{ ++ register8_t CTRL; /* AES Control Register */ ++ register8_t STATUS; /* AES Status Register */ ++ register8_t STATE; /* AES State Register */ ++ register8_t KEY; /* AES Key Register */ ++ register8_t INTCTRL; /* AES Interrupt Control Register */ ++} AES_t; ++ ++/* Interrupt level */ ++typedef enum AES_INTLVL_enum ++{ ++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} AES_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ ++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ ++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ ++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Channel */ ++typedef struct DMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Address Control */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ ++ register8_t REPCNT; /* Channel Repeat Count */ ++ register8_t reserved_0x07; ++ register8_t SRCADDR0; /* Channel Source Address 0 */ ++ register8_t SRCADDR1; /* Channel Source Address 1 */ ++ register8_t SRCADDR2; /* Channel Source Address 2 */ ++ register8_t reserved_0x0B; ++ register8_t DESTADDR0; /* Channel Destination Address 0 */ ++ register8_t DESTADDR1; /* Channel Destination Address 1 */ ++ register8_t DESTADDR2; /* Channel Destination Address 2 */ ++ register8_t reserved_0x0F; ++} DMA_CH_t; ++ ++ ++/* DMA Controller */ ++typedef struct DMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ DMA_CH_t CH0; /* DMA Channel 0 */ ++ DMA_CH_t CH1; /* DMA Channel 1 */ ++ DMA_CH_t CH2; /* DMA Channel 2 */ ++ DMA_CH_t CH3; /* DMA Channel 3 */ ++} DMA_t; ++ ++/* Burst mode */ ++typedef enum DMA_CH_BURSTLEN_enum ++{ ++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ ++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ ++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ ++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ ++} DMA_CH_BURSTLEN_t; ++ ++/* Source address reload mode */ ++typedef enum DMA_CH_SRCRELOAD_enum ++{ ++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ ++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ ++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ ++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ ++} DMA_CH_SRCRELOAD_t; ++ ++/* Source addressing mode */ ++typedef enum DMA_CH_SRCDIR_enum ++{ ++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ ++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ ++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ ++} DMA_CH_SRCDIR_t; ++ ++/* Destination adress reload mode */ ++typedef enum DMA_CH_DESTRELOAD_enum ++{ ++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ ++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ ++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ ++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ ++} DMA_CH_DESTRELOAD_t; ++ ++/* Destination adressing mode */ ++typedef enum DMA_CH_DESTDIR_enum ++{ ++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ ++} DMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum DMA_CH_TRIGSRC_enum ++{ ++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ ++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ ++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ ++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ ++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ ++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ ++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ ++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ ++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ ++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ ++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ ++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ ++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ ++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ ++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ ++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ ++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ ++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ ++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ ++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ ++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ ++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ ++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ ++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ ++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ ++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ ++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ ++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ ++} DMA_CH_TRIGSRC_t; ++ ++/* Double buffering mode */ ++typedef enum DMA_DBUFMODE_enum ++{ ++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ ++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ ++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ ++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ ++} DMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum DMA_PRIMODE_enum ++{ ++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ ++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ ++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ ++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ ++} DMA_PRIMODE_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_ERRINTLVL_enum ++{ ++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ ++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ ++} DMA_CH_ERRINTLVL_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_TRNINTLVL_enum ++{ ++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ ++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ ++} DMA_CH_TRNINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ ++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ ++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ ++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t CH4CTRL; /* Channel 4 Control Register */ ++ register8_t CH5CTRL; /* Channel 5 Control Register */ ++ register8_t CH6CTRL; /* Channel 6 Control Register */ ++ register8_t CH7CTRL; /* Channel 7 Control Register */ ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ ++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ ++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ ++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ ++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ ++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ ++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ ++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ ++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ ++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ ++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ ++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ ++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ ++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ ++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ ++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ ++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ ++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t reserved_0x07; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ _WORDREGISTER(CH1RES); /* Channel 1 Result */ ++ _WORDREGISTER(CH2RES); /* Channel 2 Result */ ++ _WORDREGISTER(CH3RES); /* Channel 3 Result */ ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++ ADC_CH_t CH1; /* ADC Channel 1 */ ++ ADC_CH_t CH2; /* ADC Channel 2 */ ++ ADC_CH_t CH3; /* ADC Channel 3 */ ++} ADC_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ ++ ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ ++ ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ ++ ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Current Limitation Mode */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ ++} ADC_CURRLIMIT_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Channel sweep selection */ ++typedef enum ADC_SWEEP_enum ++{ ++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ ++} ADC_SWEEP_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* DMA request selection */ ++typedef enum ADC_DMASEL_enum ++{ ++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ ++} ADC_DMASEL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DAC - Digital/Analog Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Digital-to-Analog Converter */ ++typedef struct DAC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t EVCTRL; /* Event Input Control */ ++ register8_t reserved_0x04; ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0GAINCAL; /* Gain Calibration */ ++ register8_t CH0OFFSETCAL; /* Offset Calibration */ ++ register8_t CH1GAINCAL; /* Gain Calibration */ ++ register8_t CH1OFFSETCAL; /* Offset Calibration */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ ++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ ++} DAC_t; ++ ++/* Output channel selection */ ++typedef enum DAC_CHSEL_enum ++{ ++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ ++ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ ++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ ++} DAC_CHSEL_t; ++ ++/* Reference voltage selection */ ++typedef enum DAC_REFSEL_enum ++{ ++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ ++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ ++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ ++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ ++} DAC_REFSEL_t; ++ ++/* Event channel selection */ ++typedef enum DAC_EVSEL_enum ++{ ++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ ++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ ++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ ++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ ++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ ++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ ++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ ++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ ++} DAC_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* SDA Hold Time */ ++typedef enum TWI_SDAHOLD_enum ++{ ++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ ++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ ++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ ++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ ++} TWI_SDAHOLD_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USB - USB ++-------------------------------------------------------------------------- ++*/ ++ ++/* USB Endpoint */ ++typedef struct USB_EP_struct ++{ ++ register8_t STATUS; /* Endpoint Status */ ++ register8_t CTRL; /* Endpoint Control */ ++ _WORDREGISTER(CNT); /* USB Endpoint Counter */ ++ _WORDREGISTER(DATAPTR); /* Data Pointer */ ++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ ++} USB_EP_t; ++ ++ ++/* Universal Serial Bus */ ++typedef struct USB_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t FIFOWP; /* FIFO Write Pointer Register */ ++ register8_t FIFORP; /* FIFO Read Pointer Register */ ++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ ++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ ++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ ++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t reserved_0x20; ++ register8_t reserved_0x21; ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t CAL0; /* Calibration Byte 0 */ ++ register8_t CAL1; /* Calibration Byte 1 */ ++} USB_t; ++ ++ ++/* USB Endpoint Table */ ++typedef struct USB_EP_TABLE_struct ++{ ++ USB_EP_t EP0OUT; /* Endpoint 0 */ ++ USB_EP_t EP0IN; /* Endpoint 0 */ ++ USB_EP_t EP1OUT; /* Endpoint 1 */ ++ USB_EP_t EP1IN; /* Endpoint 1 */ ++ USB_EP_t EP2OUT; /* Endpoint 2 */ ++ USB_EP_t EP2IN; /* Endpoint 2 */ ++ USB_EP_t EP3OUT; /* Endpoint 3 */ ++ USB_EP_t EP3IN; /* Endpoint 3 */ ++ USB_EP_t EP4OUT; /* Endpoint 4 */ ++ USB_EP_t EP4IN; /* Endpoint 4 */ ++ USB_EP_t EP5OUT; /* Endpoint 5 */ ++ USB_EP_t EP5IN; /* Endpoint 5 */ ++ USB_EP_t EP6OUT; /* Endpoint 6 */ ++ USB_EP_t EP6IN; /* Endpoint 6 */ ++ USB_EP_t EP7OUT; /* Endpoint 7 */ ++ USB_EP_t EP7IN; /* Endpoint 7 */ ++ USB_EP_t EP8OUT; /* Endpoint 8 */ ++ USB_EP_t EP8IN; /* Endpoint 8 */ ++ USB_EP_t EP9OUT; /* Endpoint 9 */ ++ USB_EP_t EP9IN; /* Endpoint 9 */ ++ USB_EP_t EP10OUT; /* Endpoint 10 */ ++ USB_EP_t EP10IN; /* Endpoint 10 */ ++ USB_EP_t EP11OUT; /* Endpoint 11 */ ++ USB_EP_t EP11IN; /* Endpoint 11 */ ++ USB_EP_t EP12OUT; /* Endpoint 12 */ ++ USB_EP_t EP12IN; /* Endpoint 12 */ ++ USB_EP_t EP13OUT; /* Endpoint 13 */ ++ USB_EP_t EP13IN; /* Endpoint 13 */ ++ USB_EP_t EP14OUT; /* Endpoint 14 */ ++ USB_EP_t EP14IN; /* Endpoint 14 */ ++ USB_EP_t EP15OUT; /* Endpoint 15 */ ++ USB_EP_t EP15IN; /* Endpoint 15 */ ++ register8_t reserved_0x100; ++ register8_t reserved_0x101; ++ register8_t reserved_0x102; ++ register8_t reserved_0x103; ++ register8_t reserved_0x104; ++ register8_t reserved_0x105; ++ register8_t reserved_0x106; ++ register8_t reserved_0x107; ++ register8_t reserved_0x108; ++ register8_t reserved_0x109; ++ register8_t reserved_0x10A; ++ register8_t reserved_0x10B; ++ register8_t reserved_0x10C; ++ register8_t reserved_0x10D; ++ register8_t reserved_0x10E; ++ register8_t reserved_0x10F; ++ register8_t FRAMENUML; /* Frame Number Low Byte */ ++ register8_t FRAMENUMH; /* Frame Number High Byte */ ++} USB_EP_TABLE_t; ++ ++/* Interrupt level */ ++typedef enum USB_INTLVL_enum ++{ ++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} USB_INTLVL_t; ++ ++/* USB Endpoint Type */ ++typedef enum USB_EP_TYPE_enum ++{ ++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ ++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ ++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ ++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ ++} USB_EP_TYPE_t; ++ ++/* USB Endpoint Buffersize */ ++typedef enum USB_EP_BUFSIZE_enum ++{ ++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ ++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ ++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ ++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ ++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ ++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ ++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ ++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ ++} USB_EP_BUFSIZE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - I/O Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* I/O Port Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Byte Mode */ ++typedef enum TC_BYTEM_enum ++{ ++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ ++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ ++} TC_BYTEM_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC2 - 16-bit Timer/Counter type 2 ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter type 2 */ ++typedef struct TC2_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t reserved_0x03; ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t reserved_0x08; ++ register8_t CTRLF; /* Control Register F */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t LCNT; /* Low Byte Count */ ++ register8_t HCNT; /* High Byte Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t LPER; /* Low Byte Period */ ++ register8_t HPER; /* High Byte Period */ ++ register8_t LCMPA; /* Low Byte Compare A */ ++ register8_t HCMPA; /* High Byte Compare A */ ++ register8_t LCMPB; /* Low Byte Compare B */ ++ register8_t HCMPB; /* High Byte Compare B */ ++ register8_t LCMPC; /* Low Byte Compare C */ ++ register8_t HCMPC; /* High Byte Compare C */ ++ register8_t LCMPD; /* Low Byte Compare D */ ++ register8_t HCMPD; /* High Byte Compare D */ ++} TC2_t; ++ ++/* Clock Selection */ ++typedef enum TC2_CLKSEL_enum ++{ ++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC2_CLKSEL_t; ++ ++/* Byte Mode */ ++typedef enum TC2_BYTEM_enum ++{ ++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ ++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ ++} TC2_BYTEM_t; ++ ++/* High Byte Underflow Interrupt Level */ ++typedef enum TC2_HUNFINTLVL_enum ++{ ++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_HUNFINTLVL_t; ++ ++/* Low Byte Underflow Interrupt Level */ ++typedef enum TC2_LUNFINTLVL_enum ++{ ++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LUNFINTLVL_t; ++ ++/* Low Byte Compare D Interrupt Level */ ++typedef enum TC2_LCMPDINTLVL_enum ++{ ++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC2_LCMPDINTLVL_t; ++ ++/* Low Byte Compare C Interrupt Level */ ++typedef enum TC2_LCMPCINTLVL_enum ++{ ++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC2_LCMPCINTLVL_t; ++ ++/* Low Byte Compare B Interrupt Level */ ++typedef enum TC2_LCMPBINTLVL_enum ++{ ++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_LCMPBINTLVL_t; ++ ++/* Low Byte Compare A Interrupt Level */ ++typedef enum TC2_LCMPAINTLVL_enum ++{ ++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LCMPAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMD_enum ++{ ++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC2_CMD_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMDEN_enum ++{ ++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ ++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ ++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ ++} TC2_CMDEN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AWEX - Timer/Counter Advanced Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - Timer/Counter High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t FUSEBYTE0; /* JTAG User ID */ ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* Timer Oscillator pin location */ ++typedef enum TOSCSEL_enum ++{ ++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ ++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ ++} TOSCSEL_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* BOD operation */ ++typedef enum BODACT_enum ++{ ++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BODACT_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WDP_enum ++{ ++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ ++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ ++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ ++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ ++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ ++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ ++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ ++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ ++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ ++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ ++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ ++} WDP_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LOCKBIT - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ ++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t USBCAL0; /* USB Calibration Byte 0 */ ++ register8_t USBCAL1; /* USB Calibration Byte 1 */ ++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ ++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ ++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ ++ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ ++ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ ++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ ++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ ++ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ ++ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++ register8_t reserved_0x40; ++ register8_t reserved_0x41; ++ register8_t reserved_0x42; ++ register8_t reserved_0x43; ++ register8_t reserved_0x44; ++ register8_t reserved_0x45; ++ register8_t reserved_0x46; ++ register8_t reserved_0x47; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define AES (*(AES_t *) 0x00C0) /* AES Module */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ ++#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ ++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ ++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ ++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ ++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ ++#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ ++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ ++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ ++#define TCE1 (*(TC1_t *) 0x0A40) /* 16-bit Timer/Counter 1 */ ++#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension */ ++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface */ ++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ ++#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ ++#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension */ ++#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++#define GPIO_GPIOR4 _SFR_MEM8(0x0004) ++#define GPIO_GPIOR5 _SFR_MEM8(0x0005) ++#define GPIO_GPIOR6 _SFR_MEM8(0x0006) ++#define GPIO_GPIOR7 _SFR_MEM8(0x0007) ++#define GPIO_GPIOR8 _SFR_MEM8(0x0008) ++#define GPIO_GPIOR9 _SFR_MEM8(0x0009) ++#define GPIO_GPIORA _SFR_MEM8(0x000A) ++#define GPIO_GPIORB _SFR_MEM8(0x000B) ++#define GPIO_GPIORC _SFR_MEM8(0x000C) ++#define GPIO_GPIORD _SFR_MEM8(0x000D) ++#define GPIO_GPIORE _SFR_MEM8(0x000E) ++#define GPIO_GPIORF _SFR_MEM8(0x000F) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++#define GPIO_GPIO4 _SFR_MEM8(0x0004) ++#define GPIO_GPIO5 _SFR_MEM8(0x0005) ++#define GPIO_GPIO6 _SFR_MEM8(0x0006) ++#define GPIO_GPIO7 _SFR_MEM8(0x0007) ++#define GPIO_GPIO8 _SFR_MEM8(0x0008) ++#define GPIO_GPIO9 _SFR_MEM8(0x0009) ++#define GPIO_GPIOA _SFR_MEM8(0x000A) ++#define GPIO_GPIOB _SFR_MEM8(0x000B) ++#define GPIO_GPIOC _SFR_MEM8(0x000C) ++#define GPIO_GPIOD _SFR_MEM8(0x000D) ++#define GPIO_GPIOE _SFR_MEM8(0x000E) ++#define GPIO_GPIOF _SFR_MEM8(0x000F) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) ++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) ++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) ++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) ++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) ++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) ++#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) ++#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) ++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) ++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) ++#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) ++#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++#define CLK_USBCTRL _SFR_MEM8(0x0044) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLL - DFLL */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPB _SFR_MEM8(0x0072) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) ++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) ++ ++/* AES - AES Module */ ++#define AES_CTRL _SFR_MEM8(0x00C0) ++#define AES_STATUS _SFR_MEM8(0x00C1) ++#define AES_STATE _SFR_MEM8(0x00C2) ++#define AES_KEY _SFR_MEM8(0x00C3) ++#define AES_INTCTRL _SFR_MEM8(0x00C4) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* DMA - DMA Controller */ ++#define DMA_CTRL _SFR_MEM8(0x0100) ++#define DMA_INTFLAGS _SFR_MEM8(0x0103) ++#define DMA_STATUS _SFR_MEM8(0x0104) ++#define DMA_TEMP _SFR_MEM16(0x0106) ++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) ++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) ++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) ++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) ++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) ++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) ++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) ++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) ++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) ++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) ++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) ++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) ++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) ++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) ++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) ++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) ++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) ++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) ++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) ++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) ++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) ++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) ++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) ++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) ++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) ++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) ++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) ++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) ++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) ++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) ++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) ++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) ++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) ++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) ++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) ++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) ++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) ++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) ++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) ++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) ++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) ++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH4MUX _SFR_MEM8(0x0184) ++#define EVSYS_CH5MUX _SFR_MEM8(0x0185) ++#define EVSYS_CH6MUX _SFR_MEM8(0x0186) ++#define EVSYS_CH7MUX _SFR_MEM8(0x0187) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) ++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) ++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) ++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CH1RES _SFR_MEM16(0x0212) ++#define ADCA_CH2RES _SFR_MEM16(0x0214) ++#define ADCA_CH3RES _SFR_MEM16(0x0216) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) ++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) ++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) ++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) ++#define ADCA_CH1_RES _SFR_MEM16(0x022C) ++#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) ++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) ++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) ++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) ++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) ++#define ADCA_CH2_RES _SFR_MEM16(0x0234) ++#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) ++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) ++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) ++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) ++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) ++#define ADCA_CH3_RES _SFR_MEM16(0x023C) ++#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCB_CTRLA _SFR_MEM8(0x0240) ++#define ADCB_CTRLB _SFR_MEM8(0x0241) ++#define ADCB_REFCTRL _SFR_MEM8(0x0242) ++#define ADCB_EVCTRL _SFR_MEM8(0x0243) ++#define ADCB_PRESCALER _SFR_MEM8(0x0244) ++#define ADCB_INTFLAGS _SFR_MEM8(0x0246) ++#define ADCB_TEMP _SFR_MEM8(0x0247) ++#define ADCB_CAL _SFR_MEM16(0x024C) ++#define ADCB_CH0RES _SFR_MEM16(0x0250) ++#define ADCB_CH1RES _SFR_MEM16(0x0252) ++#define ADCB_CH2RES _SFR_MEM16(0x0254) ++#define ADCB_CH3RES _SFR_MEM16(0x0256) ++#define ADCB_CMP _SFR_MEM16(0x0258) ++#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) ++#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) ++#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) ++#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) ++#define ADCB_CH0_RES _SFR_MEM16(0x0264) ++#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) ++#define ADCB_CH1_CTRL _SFR_MEM8(0x0268) ++#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269) ++#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A) ++#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B) ++#define ADCB_CH1_RES _SFR_MEM16(0x026C) ++#define ADCB_CH1_SCAN _SFR_MEM8(0x026E) ++#define ADCB_CH2_CTRL _SFR_MEM8(0x0270) ++#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271) ++#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272) ++#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273) ++#define ADCB_CH2_RES _SFR_MEM16(0x0274) ++#define ADCB_CH2_SCAN _SFR_MEM8(0x0276) ++#define ADCB_CH3_CTRL _SFR_MEM8(0x0278) ++#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279) ++#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A) ++#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B) ++#define ADCB_CH3_RES _SFR_MEM16(0x027C) ++#define ADCB_CH3_SCAN _SFR_MEM8(0x027E) ++ ++/* DAC - Digital-to-Analog Converter */ ++#define DACB_CTRLA _SFR_MEM8(0x0320) ++#define DACB_CTRLB _SFR_MEM8(0x0321) ++#define DACB_CTRLC _SFR_MEM8(0x0322) ++#define DACB_EVCTRL _SFR_MEM8(0x0323) ++#define DACB_STATUS _SFR_MEM8(0x0325) ++#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) ++#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) ++#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) ++#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) ++#define DACB_CH0DATA _SFR_MEM16(0x0338) ++#define DACB_CH1DATA _SFR_MEM16(0x033A) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* AC - Analog Comparator */ ++#define ACB_AC0CTRL _SFR_MEM8(0x0390) ++#define ACB_AC1CTRL _SFR_MEM8(0x0391) ++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) ++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) ++#define ACB_CTRLA _SFR_MEM8(0x0394) ++#define ACB_CTRLB _SFR_MEM8(0x0395) ++#define ACB_WINCTRL _SFR_MEM8(0x0396) ++#define ACB_STATUS _SFR_MEM8(0x0397) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* USB - Universal Serial Bus */ ++#define USB_CTRLA _SFR_MEM8(0x04C0) ++#define USB_CTRLB _SFR_MEM8(0x04C1) ++#define USB_STATUS _SFR_MEM8(0x04C2) ++#define USB_ADDR _SFR_MEM8(0x04C3) ++#define USB_FIFOWP _SFR_MEM8(0x04C4) ++#define USB_FIFORP _SFR_MEM8(0x04C5) ++#define USB_EPPTR _SFR_MEM16(0x04C6) ++#define USB_INTCTRLA _SFR_MEM8(0x04C8) ++#define USB_INTCTRLB _SFR_MEM8(0x04C9) ++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) ++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) ++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) ++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) ++#define USB_CAL0 _SFR_MEM8(0x04FA) ++#define USB_CAL1 _SFR_MEM8(0x04FB) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_REMAP _SFR_MEM8(0x060E) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_REMAP _SFR_MEM8(0x062E) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_REMAP _SFR_MEM8(0x068E) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORT - I/O Ports */ ++#define PORTF_DIR _SFR_MEM8(0x06A0) ++#define PORTF_DIRSET _SFR_MEM8(0x06A1) ++#define PORTF_DIRCLR _SFR_MEM8(0x06A2) ++#define PORTF_DIRTGL _SFR_MEM8(0x06A3) ++#define PORTF_OUT _SFR_MEM8(0x06A4) ++#define PORTF_OUTSET _SFR_MEM8(0x06A5) ++#define PORTF_OUTCLR _SFR_MEM8(0x06A6) ++#define PORTF_OUTTGL _SFR_MEM8(0x06A7) ++#define PORTF_IN _SFR_MEM8(0x06A8) ++#define PORTF_INTCTRL _SFR_MEM8(0x06A9) ++#define PORTF_INT0MASK _SFR_MEM8(0x06AA) ++#define PORTF_INT1MASK _SFR_MEM8(0x06AB) ++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) ++#define PORTF_REMAP _SFR_MEM8(0x06AE) ++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) ++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) ++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) ++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) ++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) ++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) ++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) ++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCC2_CTRLA _SFR_MEM8(0x0800) ++#define TCC2_CTRLB _SFR_MEM8(0x0801) ++#define TCC2_CTRLC _SFR_MEM8(0x0802) ++#define TCC2_CTRLE _SFR_MEM8(0x0804) ++#define TCC2_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC2_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC2_CTRLF _SFR_MEM8(0x0809) ++#define TCC2_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC2_LCNT _SFR_MEM8(0x0820) ++#define TCC2_HCNT _SFR_MEM8(0x0821) ++#define TCC2_LPER _SFR_MEM8(0x0826) ++#define TCC2_HPER _SFR_MEM8(0x0827) ++#define TCC2_LCMPA _SFR_MEM8(0x0828) ++#define TCC2_HCMPA _SFR_MEM8(0x0829) ++#define TCC2_LCMPB _SFR_MEM8(0x082A) ++#define TCC2_HCMPB _SFR_MEM8(0x082B) ++#define TCC2_LCMPC _SFR_MEM8(0x082C) ++#define TCC2_HCMPC _SFR_MEM8(0x082D) ++#define TCC2_LCMPD _SFR_MEM8(0x082E) ++#define TCC2_HCMPD _SFR_MEM8(0x082F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_STATUSSET _SFR_MEM8(0x0885) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1_DATA _SFR_MEM8(0x08B0) ++#define USARTC1_STATUS _SFR_MEM8(0x08B1) ++#define USARTC1_CTRLA _SFR_MEM8(0x08B3) ++#define USARTC1_CTRLB _SFR_MEM8(0x08B4) ++#define USARTC1_CTRLC _SFR_MEM8(0x08B5) ++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) ++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCD2_CTRLA _SFR_MEM8(0x0900) ++#define TCD2_CTRLB _SFR_MEM8(0x0901) ++#define TCD2_CTRLC _SFR_MEM8(0x0902) ++#define TCD2_CTRLE _SFR_MEM8(0x0904) ++#define TCD2_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD2_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD2_CTRLF _SFR_MEM8(0x0909) ++#define TCD2_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD2_LCNT _SFR_MEM8(0x0920) ++#define TCD2_HCNT _SFR_MEM8(0x0921) ++#define TCD2_LPER _SFR_MEM8(0x0926) ++#define TCD2_HPER _SFR_MEM8(0x0927) ++#define TCD2_LCMPA _SFR_MEM8(0x0928) ++#define TCD2_HCMPA _SFR_MEM8(0x0929) ++#define TCD2_LCMPB _SFR_MEM8(0x092A) ++#define TCD2_HCMPB _SFR_MEM8(0x092B) ++#define TCD2_LCMPC _SFR_MEM8(0x092C) ++#define TCD2_HCMPC _SFR_MEM8(0x092D) ++#define TCD2_LCMPD _SFR_MEM8(0x092E) ++#define TCD2_HCMPD _SFR_MEM8(0x092F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCD1_CTRLA _SFR_MEM8(0x0940) ++#define TCD1_CTRLB _SFR_MEM8(0x0941) ++#define TCD1_CTRLC _SFR_MEM8(0x0942) ++#define TCD1_CTRLD _SFR_MEM8(0x0943) ++#define TCD1_CTRLE _SFR_MEM8(0x0944) ++#define TCD1_INTCTRLA _SFR_MEM8(0x0946) ++#define TCD1_INTCTRLB _SFR_MEM8(0x0947) ++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) ++#define TCD1_CTRLFSET _SFR_MEM8(0x0949) ++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) ++#define TCD1_CTRLGSET _SFR_MEM8(0x094B) ++#define TCD1_INTFLAGS _SFR_MEM8(0x094C) ++#define TCD1_TEMP _SFR_MEM8(0x094F) ++#define TCD1_CNT _SFR_MEM16(0x0960) ++#define TCD1_PER _SFR_MEM16(0x0966) ++#define TCD1_CCA _SFR_MEM16(0x0968) ++#define TCD1_CCB _SFR_MEM16(0x096A) ++#define TCD1_PERBUF _SFR_MEM16(0x0976) ++#define TCD1_CCABUF _SFR_MEM16(0x0978) ++#define TCD1_CCBBUF _SFR_MEM16(0x097A) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESD_CTRLA _SFR_MEM8(0x0990) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD1_DATA _SFR_MEM8(0x09B0) ++#define USARTD1_STATUS _SFR_MEM8(0x09B1) ++#define USARTD1_CTRLA _SFR_MEM8(0x09B3) ++#define USARTD1_CTRLB _SFR_MEM8(0x09B4) ++#define USARTD1_CTRLC _SFR_MEM8(0x09B5) ++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) ++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCE2_CTRLA _SFR_MEM8(0x0A00) ++#define TCE2_CTRLB _SFR_MEM8(0x0A01) ++#define TCE2_CTRLC _SFR_MEM8(0x0A02) ++#define TCE2_CTRLE _SFR_MEM8(0x0A04) ++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE2_CTRLF _SFR_MEM8(0x0A09) ++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE2_LCNT _SFR_MEM8(0x0A20) ++#define TCE2_HCNT _SFR_MEM8(0x0A21) ++#define TCE2_LPER _SFR_MEM8(0x0A26) ++#define TCE2_HPER _SFR_MEM8(0x0A27) ++#define TCE2_LCMPA _SFR_MEM8(0x0A28) ++#define TCE2_HCMPA _SFR_MEM8(0x0A29) ++#define TCE2_LCMPB _SFR_MEM8(0x0A2A) ++#define TCE2_HCMPB _SFR_MEM8(0x0A2B) ++#define TCE2_LCMPC _SFR_MEM8(0x0A2C) ++#define TCE2_HCMPC _SFR_MEM8(0x0A2D) ++#define TCE2_LCMPD _SFR_MEM8(0x0A2E) ++#define TCE2_HCMPD _SFR_MEM8(0x0A2F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCE1_CTRLA _SFR_MEM8(0x0A40) ++#define TCE1_CTRLB _SFR_MEM8(0x0A41) ++#define TCE1_CTRLC _SFR_MEM8(0x0A42) ++#define TCE1_CTRLD _SFR_MEM8(0x0A43) ++#define TCE1_CTRLE _SFR_MEM8(0x0A44) ++#define TCE1_INTCTRLA _SFR_MEM8(0x0A46) ++#define TCE1_INTCTRLB _SFR_MEM8(0x0A47) ++#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48) ++#define TCE1_CTRLFSET _SFR_MEM8(0x0A49) ++#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A) ++#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B) ++#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C) ++#define TCE1_TEMP _SFR_MEM8(0x0A4F) ++#define TCE1_CNT _SFR_MEM16(0x0A60) ++#define TCE1_PER _SFR_MEM16(0x0A66) ++#define TCE1_CCA _SFR_MEM16(0x0A68) ++#define TCE1_CCB _SFR_MEM16(0x0A6A) ++#define TCE1_PERBUF _SFR_MEM16(0x0A76) ++#define TCE1_CCABUF _SFR_MEM16(0x0A78) ++#define TCE1_CCBBUF _SFR_MEM16(0x0A7A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXE_CTRL _SFR_MEM8(0x0A80) ++#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) ++#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) ++#define AWEXE_STATUS _SFR_MEM8(0x0A84) ++#define AWEXE_STATUSSET _SFR_MEM8(0x0A85) ++#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) ++#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) ++#define AWEXE_DTLS _SFR_MEM8(0x0A88) ++#define AWEXE_DTHS _SFR_MEM8(0x0A89) ++#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) ++#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) ++#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESE_CTRLA _SFR_MEM8(0x0A90) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE1_DATA _SFR_MEM8(0x0AB0) ++#define USARTE1_STATUS _SFR_MEM8(0x0AB1) ++#define USARTE1_CTRLA _SFR_MEM8(0x0AB3) ++#define USARTE1_CTRLB _SFR_MEM8(0x0AB4) ++#define USARTE1_CTRLC _SFR_MEM8(0x0AB5) ++#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6) ++#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIE_CTRL _SFR_MEM8(0x0AC0) ++#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) ++#define SPIE_STATUS _SFR_MEM8(0x0AC2) ++#define SPIE_DATA _SFR_MEM8(0x0AC3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCF0_CTRLA _SFR_MEM8(0x0B00) ++#define TCF0_CTRLB _SFR_MEM8(0x0B01) ++#define TCF0_CTRLC _SFR_MEM8(0x0B02) ++#define TCF0_CTRLD _SFR_MEM8(0x0B03) ++#define TCF0_CTRLE _SFR_MEM8(0x0B04) ++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) ++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) ++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) ++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) ++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF0_TEMP _SFR_MEM8(0x0B0F) ++#define TCF0_CNT _SFR_MEM16(0x0B20) ++#define TCF0_PER _SFR_MEM16(0x0B26) ++#define TCF0_CCA _SFR_MEM16(0x0B28) ++#define TCF0_CCB _SFR_MEM16(0x0B2A) ++#define TCF0_CCC _SFR_MEM16(0x0B2C) ++#define TCF0_CCD _SFR_MEM16(0x0B2E) ++#define TCF0_PERBUF _SFR_MEM16(0x0B36) ++#define TCF0_CCABUF _SFR_MEM16(0x0B38) ++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) ++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) ++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCF2_CTRLA _SFR_MEM8(0x0B00) ++#define TCF2_CTRLB _SFR_MEM8(0x0B01) ++#define TCF2_CTRLC _SFR_MEM8(0x0B02) ++#define TCF2_CTRLE _SFR_MEM8(0x0B04) ++#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF2_CTRLF _SFR_MEM8(0x0B09) ++#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF2_LCNT _SFR_MEM8(0x0B20) ++#define TCF2_HCNT _SFR_MEM8(0x0B21) ++#define TCF2_LPER _SFR_MEM8(0x0B26) ++#define TCF2_HPER _SFR_MEM8(0x0B27) ++#define TCF2_LCMPA _SFR_MEM8(0x0B28) ++#define TCF2_HCMPA _SFR_MEM8(0x0B29) ++#define TCF2_LCMPB _SFR_MEM8(0x0B2A) ++#define TCF2_HCMPB _SFR_MEM8(0x0B2B) ++#define TCF2_LCMPC _SFR_MEM8(0x0B2C) ++#define TCF2_HCMPC _SFR_MEM8(0x0B2D) ++#define TCF2_LCMPD _SFR_MEM8(0x0B2E) ++#define TCF2_HCMPD _SFR_MEM8(0x0B2F) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESF_CTRLA _SFR_MEM8(0x0B90) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTF0_DATA _SFR_MEM8(0x0BA0) ++#define USARTF0_STATUS _SFR_MEM8(0x0BA1) ++#define USARTF0_CTRLA _SFR_MEM8(0x0BA3) ++#define USARTF0_CTRLB _SFR_MEM8(0x0BA4) ++#define USARTF0_CTRLC _SFR_MEM8(0x0BA5) ++#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6) ++#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* CLK.USBCTRL bit masks and bit positions */ ++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ ++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ ++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ ++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ ++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ ++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ ++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ ++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ ++ ++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ ++#define CLK_USBSRC_gp 1 /* Clock Source group position. */ ++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ ++ ++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_USB_bm 0x40 /* USB bit mask. */ ++#define PR_USB_bp 6 /* USB bit position. */ ++ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ ++#define PR_EBI_bp 3 /* External Bus Interface bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ ++#define PR_DAC_bp 2 /* Port A DAC bit position. */ ++ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPB bit masks and bit positions */ ++/* PR_DAC Predefined. */ ++/* PR_DAC Predefined. */ ++ ++/* PR_ADC Predefined. */ ++/* PR_ADC Predefined. */ ++ ++/* PR_AC Predefined. */ ++/* PR_AC Predefined. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ ++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ ++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ ++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ ++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ ++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ ++ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ ++#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ ++ ++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ ++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ ++ ++#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ ++#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ ++ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ ++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ ++ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ ++ ++/* PORTCFG.EBIOUT bit masks and bit positions */ ++#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ ++#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ ++#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ ++#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ ++#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ ++#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ ++ ++#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ ++#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ ++#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ ++#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ ++#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ ++#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ ++ ++/* PORTCFG.EVOUTSEL bit masks and bit positions */ ++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ ++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ ++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ ++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ ++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ ++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ ++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ ++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ ++ ++/* AES - AES Module */ ++/* AES.CTRL bit masks and bit positions */ ++#define AES_START_bm 0x80 /* Start/Run bit mask. */ ++#define AES_START_bp 7 /* Start/Run bit position. */ ++ ++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ ++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ ++ ++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ ++#define AES_RESET_bp 5 /* AES Software Reset bit position. */ ++ ++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ ++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ ++ ++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ ++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ ++ ++/* AES.STATUS bit masks and bit positions */ ++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ ++#define AES_ERROR_bp 7 /* AES Error bit position. */ ++ ++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ ++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ ++ ++/* AES.INTCTRL bit masks and bit positions */ ++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define AES_INTLVL_gp 0 /* Interrupt level group position. */ ++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* DMA - DMA Controller */ ++/* DMA_CH.CTRLA bit masks and bit positions */ ++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ ++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ ++ ++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ ++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ ++ ++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ ++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ ++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ ++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ ++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ ++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ ++ ++/* DMA_CH.CTRLB bit masks and bit positions */ ++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ ++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ ++ ++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ ++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ ++ ++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ ++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ ++ ++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ ++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ ++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ ++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ ++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ ++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ ++ ++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ ++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ ++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ ++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ ++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ ++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ ++ ++/* DMA_CH.ADDRCTRL bit masks and bit positions */ ++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ ++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ ++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ ++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ ++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ ++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ ++ ++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ ++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ ++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ ++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ ++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ ++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ ++ ++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ ++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ ++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ ++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ ++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ ++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ ++ ++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ ++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ ++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ ++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ ++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ ++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ ++ ++/* DMA_CH.TRIGSRC bit masks and bit positions */ ++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++/* DMA.CTRL bit masks and bit positions */ ++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define DMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define DMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ ++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ ++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ ++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ ++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ ++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ ++ ++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ ++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ ++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ ++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ ++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ ++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ ++ ++/* DMA.INTFLAGS bit masks and bit positions */ ++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++/* DMA.STATUS bit masks and bit positions */ ++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ ++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ ++ ++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ ++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ ++ ++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ ++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ ++ ++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ ++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ ++ ++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ ++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ ++ ++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ ++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ ++ ++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ ++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ ++ ++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ ++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH4MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH5MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH6MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH7MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM Predefined. */ ++/* EVSYS_QDIRM Predefined. */ ++ ++/* EVSYS_QDIEN Predefined. */ ++/* EVSYS_QDIEN Predefined. */ ++ ++/* EVSYS_QDEN Predefined. */ ++/* EVSYS_QDEN Predefined. */ ++ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH4CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM Predefined. */ ++/* EVSYS_QDIRM Predefined. */ ++ ++/* EVSYS_QDIEN Predefined. */ ++/* EVSYS_QDIEN Predefined. */ ++ ++/* EVSYS_QDEN Predefined. */ ++/* EVSYS_QDEN Predefined. */ ++ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH5CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH6CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH7CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ ++#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ ++#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ ++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ ++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ ++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ ++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ ++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ ++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ ++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ ++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ ++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ ++ ++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ ++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ ++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ ++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ ++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ ++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ ++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ ++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ ++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ ++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ ++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ ++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ ++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ ++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ ++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ ++ ++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ ++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ ++ ++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ ++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ ++ ++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ ++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ ++ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ ++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ ++#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ ++ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ ++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ ++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ ++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ ++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ ++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ ++ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ ++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ ++ ++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ ++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ ++ ++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ ++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ ++ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* DAC - Digital/Analog Converter */ ++/* DAC.CTRLA bit masks and bit positions */ ++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ ++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ ++ ++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ ++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ ++ ++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ ++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ ++ ++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ ++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ ++ ++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define DAC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* DAC.CTRLB bit masks and bit positions */ ++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ ++#define DAC_CHSEL_gp 5 /* Channel Select group position. */ ++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ ++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ ++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ ++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ ++ ++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ ++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ ++ ++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ ++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ ++ ++/* DAC.CTRLC bit masks and bit positions */ ++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ ++#define DAC_REFSEL_gp 3 /* Reference Select group position. */ ++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ ++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ ++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ ++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ ++ ++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ ++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ ++ ++/* DAC.EVCTRL bit masks and bit positions */ ++#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ ++#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ ++ ++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ ++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ ++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ ++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ ++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ ++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ ++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ ++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ ++ ++/* DAC.STATUS bit masks and bit positions */ ++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ ++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ ++ ++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ ++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ ++ ++/* DAC.CH0GAINCAL bit masks and bit positions */ ++#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH0OFFSETCAL bit masks and bit positions */ ++#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* DAC.CH1GAINCAL bit masks and bit positions */ ++#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH1OFFSETCAL bit masks and bit positions */ ++#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ ++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HSMODE Predefined. */ ++/* AC_HSMODE Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* RTC - Real-Time Counter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* USB - USB */ ++/* USB_EP.STATUS bit masks and bit positions */ ++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ ++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ ++ ++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ ++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ ++ ++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ ++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ ++ ++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ ++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ ++ ++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ ++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ ++ ++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ ++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ ++ ++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ ++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ ++ ++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ ++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ ++ ++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ ++ ++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ ++ ++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ ++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ ++ ++/* USB_EP.CTRL bit masks and bit positions */ ++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ ++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ ++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ ++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ ++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ ++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ ++ ++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ ++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ ++ ++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ ++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ ++ ++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ ++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ ++ ++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ ++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ ++ ++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ ++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ ++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ ++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ ++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ ++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ ++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ ++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ ++ ++/* USB_EP.CNT bit masks and bit positions */ ++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ ++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ ++ ++/* USB.CTRLA bit masks and bit positions */ ++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ ++#define USB_ENABLE_bp 7 /* USB Enable bit position. */ ++ ++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ ++#define USB_SPEED_bp 6 /* Speed Select bit position. */ ++ ++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ ++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ ++ ++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ ++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ ++ ++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ ++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ ++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ ++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ ++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ ++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ ++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ ++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ ++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ ++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ ++ ++/* USB.CTRLB bit masks and bit positions */ ++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ ++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ ++ ++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ ++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ ++ ++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ ++#define USB_GNACK_bp 1 /* Global NACK bit position. */ ++ ++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ ++#define USB_ATTACH_bp 0 /* Attach bit position. */ ++ ++/* USB.STATUS bit masks and bit positions */ ++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ ++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ ++ ++#define USB_RESUME_bm 0x04 /* Resume bit mask. */ ++#define USB_RESUME_bp 2 /* Resume bit position. */ ++ ++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ ++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ ++ ++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ ++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ ++ ++/* USB.ADDR bit masks and bit positions */ ++#define USB_ADDR_gm 0x7F /* Device Address group mask. */ ++#define USB_ADDR_gp 0 /* Device Address group position. */ ++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ ++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ ++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ ++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ ++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ ++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ ++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ ++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ ++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ ++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ ++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ ++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ ++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ ++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ ++ ++/* USB.FIFOWP bit masks and bit positions */ ++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ ++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ ++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ ++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ ++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ ++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ ++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ ++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ ++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ ++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ ++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ ++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ ++ ++/* USB.FIFORP bit masks and bit positions */ ++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ ++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ ++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ ++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ ++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ ++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ ++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ ++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ ++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ ++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ ++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ ++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ ++ ++/* USB.INTCTRLA bit masks and bit positions */ ++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ ++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ ++ ++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ ++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ ++ ++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ ++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ ++ ++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ ++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ ++ ++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* USB.INTCTRLB bit masks and bit positions */ ++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ ++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ ++ ++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ ++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ ++ ++/* USB.INTFLAGSACLR bit masks and bit positions */ ++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ ++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ ++ ++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ ++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ ++ ++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ ++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ ++ ++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ ++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ ++ ++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ ++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ ++ ++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ ++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ ++ ++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ ++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ ++ ++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ ++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSASET bit masks and bit positions */ ++/* USB_SOFIF Predefined. */ ++/* USB_SOFIF Predefined. */ ++ ++/* USB_SUSPENDIF Predefined. */ ++/* USB_SUSPENDIF Predefined. */ ++ ++/* USB_RESUMEIF Predefined. */ ++/* USB_RESUMEIF Predefined. */ ++ ++/* USB_RSTIF Predefined. */ ++/* USB_RSTIF Predefined. */ ++ ++/* USB_CRCIF Predefined. */ ++/* USB_CRCIF Predefined. */ ++ ++/* USB_UNFIF Predefined. */ ++/* USB_UNFIF Predefined. */ ++ ++/* USB_OVFIF Predefined. */ ++/* USB_OVFIF Predefined. */ ++ ++/* USB_STALLIF Predefined. */ ++/* USB_STALLIF Predefined. */ ++ ++/* USB.INTFLAGSBCLR bit masks and bit positions */ ++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ ++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ ++ ++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ ++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSBSET bit masks and bit positions */ ++/* USB_TRNIF Predefined. */ ++/* USB_TRNIF Predefined. */ ++ ++/* USB_SETUPIF Predefined. */ ++/* USB_SETUPIF Predefined. */ ++ ++/* PORT - I/O Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_SPI_bm 0x20 /* SPI bit mask. */ ++#define PORT_SPI_bp 5 /* SPI bit position. */ ++ ++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ ++#define PORT_USART0_bp 4 /* USART0 bit position. */ ++ ++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ ++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ ++ ++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ ++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ ++ ++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ ++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ ++ ++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ ++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD Predefined. */ ++/* TC0_CMD Predefined. */ ++ ++/* TC0_LUPD Predefined. */ ++/* TC0_LUPD Predefined. */ ++ ++/* TC0_DIR Predefined. */ ++/* TC0_DIR Predefined. */ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV Predefined. */ ++/* TC0_CCDBV Predefined. */ ++ ++/* TC0_CCCBV Predefined. */ ++/* TC0_CCCBV Predefined. */ ++ ++/* TC0_CCBBV Predefined. */ ++/* TC0_CCBBV Predefined. */ ++ ++/* TC0_CCABV Predefined. */ ++/* TC0_CCABV Predefined. */ ++ ++/* TC0_PERBV Predefined. */ ++/* TC0_PERBV Predefined. */ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD Predefined. */ ++/* TC1_CMD Predefined. */ ++ ++/* TC1_LUPD Predefined. */ ++/* TC1_LUPD Predefined. */ ++ ++/* TC1_DIR Predefined. */ ++/* TC1_DIR Predefined. */ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV Predefined. */ ++/* TC1_CCBBV Predefined. */ ++ ++/* TC1_CCABV Predefined. */ ++/* TC1_CCABV Predefined. */ ++ ++/* TC1_PERBV Predefined. */ ++/* TC1_PERBV Predefined. */ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++/* TC2.CTRLA bit masks and bit positions */ ++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC2.CTRLB bit masks and bit positions */ ++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ ++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ ++ ++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ ++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ ++ ++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ ++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ ++ ++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ ++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ ++ ++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ ++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ ++ ++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ ++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ ++ ++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ ++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ ++ ++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ ++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ ++ ++/* TC2.CTRLC bit masks and bit positions */ ++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ ++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ ++ ++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ ++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ ++ ++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ ++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ ++ ++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ ++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ ++ ++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ ++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ ++ ++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ ++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ ++ ++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ ++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ ++ ++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ ++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ ++ ++/* TC2.CTRLE bit masks and bit positions */ ++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC2.INTCTRLA bit masks and bit positions */ ++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ ++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ ++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ ++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ ++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ ++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ ++ ++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ ++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ ++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ ++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ ++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ ++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ ++ ++/* TC2.INTCTRLB bit masks and bit positions */ ++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ ++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ ++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ ++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ ++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ ++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ ++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ ++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ ++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ ++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ ++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ ++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ ++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ ++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ ++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ ++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ ++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ ++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ ++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ ++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ ++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ ++ ++/* TC2.CTRLF bit masks and bit positions */ ++#define TC2_CMD_gm 0x0C /* Command group mask. */ ++#define TC2_CMD_gp 2 /* Command group position. */ ++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC2_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC2_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ ++#define TC2_CMDEN_gp 0 /* Command Enable group position. */ ++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ ++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ ++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ ++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ ++ ++/* TC2.INTFLAGS bit masks and bit positions */ ++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ ++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ ++ ++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ ++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ ++ ++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ ++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ ++ ++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ ++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ ++ ++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ ++ ++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ ++ ++/* AWEX - Timer/Counter Advanced Waveform Extension */ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++/* AWEX.STATUSSET bit masks and bit positions */ ++/* AWEX_FDF Predefined. */ ++/* AWEX_FDF Predefined. */ ++ ++/* AWEX_DTHSBUFV Predefined. */ ++/* AWEX_DTHSBUFV Predefined. */ ++ ++/* AWEX_DTLSBUFV Predefined. */ ++/* AWEX_DTLSBUFV Predefined. */ ++ ++/* HIRES - Timer/Counter High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ ++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ ++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ ++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ ++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ ++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ ++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ ++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ ++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ ++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ ++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ ++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ ++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ ++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ ++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ ++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ ++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ ++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ ++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ ++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ ++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* LOCKBIT - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* DMA interrupt vectors */ ++#define DMA_CH0_vect_num 6 ++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ ++#define DMA_CH1_vect_num 7 ++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ ++#define DMA_CH2_vect_num 8 ++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ ++#define DMA_CH3_vect_num 9 ++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LUNF_vect_num 14 ++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_HUNF_vect_num 15 ++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPA_vect_num 16 ++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPB_vect_num 17 ++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPC_vect_num 18 ++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPD_vect_num 19 ++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* USARTC1 interrupt vectors */ ++#define USARTC1_RXC_vect_num 28 ++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ ++#define USARTC1_DRE_vect_num 29 ++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ ++#define USARTC1_TXC_vect_num 30 ++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ ++ ++/* AES interrupt vectors */ ++#define AES_INT_vect_num 31 ++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* ACB interrupt vectors */ ++#define ACB_AC0_vect_num 36 ++#define ACB_AC0_vect _VECTOR(36) /* AC0 Interrupt */ ++#define ACB_AC1_vect_num 37 ++#define ACB_AC1_vect _VECTOR(37) /* AC1 Interrupt */ ++#define ACB_ACW_vect_num 38 ++#define ACB_ACW_vect _VECTOR(38) /* ACW Window Mode Interrupt */ ++ ++/* ADCB interrupt vectors */ ++#define ADCB_CH0_vect_num 39 ++#define ADCB_CH0_vect _VECTOR(39) /* Interrupt 0 */ ++#define ADCB_CH1_vect_num 40 ++#define ADCB_CH1_vect _VECTOR(40) /* Interrupt 1 */ ++#define ADCB_CH2_vect_num 41 ++#define ADCB_CH2_vect _VECTOR(41) /* Interrupt 2 */ ++#define ADCB_CH3_vect_num 42 ++#define ADCB_CH3_vect _VECTOR(42) /* Interrupt 3 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LUNF_vect_num 47 ++#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_HUNF_vect_num 48 ++#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPA_vect_num 49 ++#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPB_vect_num 50 ++#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPC_vect_num 51 ++#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPD_vect_num 52 ++#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ ++ ++/* TCE1 interrupt vectors */ ++#define TCE1_OVF_vect_num 53 ++#define TCE1_OVF_vect _VECTOR(53) /* Overflow Interrupt */ ++#define TCE1_ERR_vect_num 54 ++#define TCE1_ERR_vect _VECTOR(54) /* Error Interrupt */ ++#define TCE1_CCA_vect_num 55 ++#define TCE1_CCA_vect _VECTOR(55) /* Compare or Capture A Interrupt */ ++#define TCE1_CCB_vect_num 56 ++#define TCE1_CCB_vect _VECTOR(56) /* Compare or Capture B Interrupt */ ++ ++/* SPIE interrupt vectors */ ++#define SPIE_INT_vect_num 57 ++#define SPIE_INT_vect _VECTOR(57) /* SPI Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* USARTE1 interrupt vectors */ ++#define USARTE1_RXC_vect_num 61 ++#define USARTE1_RXC_vect _VECTOR(61) /* Reception Complete Interrupt */ ++#define USARTE1_DRE_vect_num 62 ++#define USARTE1_DRE_vect _VECTOR(62) /* Data Register Empty Interrupt */ ++#define USARTE1_TXC_vect_num 63 ++#define USARTE1_TXC_vect _VECTOR(63) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++#define ADCA_CH1_vect_num 72 ++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ ++#define ADCA_CH2_vect_num 73 ++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ ++#define ADCA_CH3_vect_num 74 ++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LUNF_vect_num 77 ++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_HUNF_vect_num 78 ++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPA_vect_num 79 ++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPB_vect_num 80 ++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPC_vect_num 81 ++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPD_vect_num 82 ++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ ++ ++/* TCD1 interrupt vectors */ ++#define TCD1_OVF_vect_num 83 ++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ ++#define TCD1_ERR_vect_num 84 ++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ ++#define TCD1_CCA_vect_num 85 ++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ ++#define TCD1_CCB_vect_num 86 ++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* USARTD1 interrupt vectors */ ++#define USARTD1_RXC_vect_num 91 ++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ ++#define USARTD1_DRE_vect_num 92 ++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ ++#define USARTD1_TXC_vect_num 93 ++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ ++ ++/* PORTF interrupt vectors */ ++#define PORTF_INT0_vect_num 104 ++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ ++#define PORTF_INT1_vect_num 105 ++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_OVF_vect_num 108 ++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LUNF_vect_num 108 ++#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_ERR_vect_num 109 ++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_HUNF_vect_num 109 ++#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCA_vect_num 110 ++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPA_vect_num 110 ++#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCB_vect_num 111 ++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPB_vect_num 111 ++#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCC_vect_num 112 ++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPC_vect_num 112 ++#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCD_vect_num 113 ++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPD_vect_num 113 ++#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ ++ ++/* USARTF0 interrupt vectors */ ++#define USARTF0_RXC_vect_num 119 ++#define USARTF0_RXC_vect _VECTOR(119) /* Reception Complete Interrupt */ ++#define USARTF0_DRE_vect_num 120 ++#define USARTF0_DRE_vect _VECTOR(120) /* Data Register Empty Interrupt */ ++#define USARTF0_TXC_vect_num 121 ++#define USARTF0_TXC_vect _VECTOR(121) /* Transmission Complete Interrupt */ ++ ++/* USB interrupt vectors */ ++#define USB_BUSEVENT_vect_num 125 ++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ ++#define USB_TRNCOMPL_vect_num 126 ++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (127 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (69632) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (65536) ++#define APP_SECTION_PAGE_SIZE (256) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0xF000) ++#define APPTABLE_SECTION_SIZE (4096) ++#define APPTABLE_SECTION_PAGE_SIZE (256) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x10000) ++#define BOOT_SECTION_SIZE (4096) ++#define BOOT_SECTION_PAGE_SIZE (256) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (12288) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (2048) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (4096) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (2048) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (6) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (256) ++#define USER_SIGNATURES_PAGE_SIZE (256) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (256) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 256 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 */ ++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ ++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ ++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ ++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ ++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ ++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ ++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ ++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ ++#define FUSE0_DEFAULT (0xFF) ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x42 ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA64A3U_H_INCLUDED */ ++ +diff --git a/include/avr/iox64a4u.h b/include/avr/iox64a4u.h +new file mode 100644 +index 0000000..7551571 +--- /dev/null ++++ b/include/avr/iox64a4u.h +@@ -0,0 +1,7240 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox64a4u.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA64A4U_H_INCLUDED ++#define _AVR_ATXMEGA64A4U_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIO4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIO5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIO6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIO7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIO8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIO9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIOA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIOB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIOC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIOD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIOE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIOF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t USBCTRL; /* USB Control Register */ ++} CLK_t; ++ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t PRPB; /* Power Reduction Port B */ ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++/* USB Prescaler Division Factor */ ++typedef enum CLK_USBPSDIV_enum ++{ ++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ ++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ ++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ ++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ ++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ ++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ ++} CLK_USBPSDIV_t; ++ ++/* USB Clock Source */ ++typedef enum CLK_USBSRC_enum ++{ ++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ ++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ ++} CLK_USBSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 2 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC2MCREF_enum ++{ ++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC2MCREF_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++ register8_t EBIOUT; /* EBI Output register */ ++ register8_t EVOUTSEL; /* Event Output Select */ ++} PORTCFG_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP02MAP_enum ++{ ++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP02MAP_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP13MAP_enum ++{ ++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP13MAP_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Clock and Event Output Port */ ++typedef enum PORTCFG_CLKEVPIN_enum ++{ ++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ ++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ ++} PORTCFG_CLKEVPIN_t; ++ ++/* EBI Address Output Port */ ++typedef enum PORTCFG_EBIADROUT_enum ++{ ++ PORTCFG_EBIADROUT_PF_gc = (0x00<<2), /* EBI port 3 address output on PORTF pins 0 to 7 */ ++ PORTCFG_EBIADROUT_PE_gc = (0x01<<2), /* EBI port 3 address output on PORTE pins 0 to 7 */ ++ PORTCFG_EBIADROUT_PFH_gc = (0x02<<2), /* EBI port 3 address output on PORTF pins 4 to 7 */ ++ PORTCFG_EBIADROUT_PEH_gc = (0x03<<2), /* EBI port 3 address output on PORTE pins 4 to 7 */ ++} PORTCFG_EBIADROUT_t; ++ ++/* EBI Chip Select Output Port */ ++typedef enum PORTCFG_EBICSOUT_enum ++{ ++ PORTCFG_EBICSOUT_PH_gc = (0x00<<0), /* EBI chip select output to PORTH pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PL_gc = (0x01<<0), /* EBI chip select output to PORTL pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PF_gc = (0x02<<0), /* EBI chip select output to PORTF pin 4 to 7 */ ++ PORTCFG_EBICSOUT_PE_gc = (0x03<<0), /* EBI chip select output to PORTE pin 4 to 7 */ ++} PORTCFG_EBICSOUT_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ ++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ ++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ ++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ ++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AES - AES Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* AES Module */ ++typedef struct AES_struct ++{ ++ register8_t CTRL; /* AES Control Register */ ++ register8_t STATUS; /* AES Status Register */ ++ register8_t STATE; /* AES State Register */ ++ register8_t KEY; /* AES Key Register */ ++ register8_t INTCTRL; /* AES Interrupt Control Register */ ++} AES_t; ++ ++/* Interrupt level */ ++typedef enum AES_INTLVL_enum ++{ ++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} AES_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ ++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ ++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ ++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Channel */ ++typedef struct DMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Address Control */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ ++ register8_t REPCNT; /* Channel Repeat Count */ ++ register8_t reserved_0x07; ++ register8_t SRCADDR0; /* Channel Source Address 0 */ ++ register8_t SRCADDR1; /* Channel Source Address 1 */ ++ register8_t SRCADDR2; /* Channel Source Address 2 */ ++ register8_t reserved_0x0B; ++ register8_t DESTADDR0; /* Channel Destination Address 0 */ ++ register8_t DESTADDR1; /* Channel Destination Address 1 */ ++ register8_t DESTADDR2; /* Channel Destination Address 2 */ ++ register8_t reserved_0x0F; ++} DMA_CH_t; ++ ++ ++/* DMA Controller */ ++typedef struct DMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ DMA_CH_t CH0; /* DMA Channel 0 */ ++ DMA_CH_t CH1; /* DMA Channel 1 */ ++ DMA_CH_t CH2; /* DMA Channel 2 */ ++ DMA_CH_t CH3; /* DMA Channel 3 */ ++} DMA_t; ++ ++/* Burst mode */ ++typedef enum DMA_CH_BURSTLEN_enum ++{ ++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ ++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ ++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ ++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ ++} DMA_CH_BURSTLEN_t; ++ ++/* Source address reload mode */ ++typedef enum DMA_CH_SRCRELOAD_enum ++{ ++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ ++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ ++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ ++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ ++} DMA_CH_SRCRELOAD_t; ++ ++/* Source addressing mode */ ++typedef enum DMA_CH_SRCDIR_enum ++{ ++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ ++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ ++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ ++} DMA_CH_SRCDIR_t; ++ ++/* Destination adress reload mode */ ++typedef enum DMA_CH_DESTRELOAD_enum ++{ ++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ ++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ ++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ ++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ ++} DMA_CH_DESTRELOAD_t; ++ ++/* Destination adressing mode */ ++typedef enum DMA_CH_DESTDIR_enum ++{ ++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ ++} DMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum DMA_CH_TRIGSRC_enum ++{ ++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ ++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ ++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ ++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ ++ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */ ++ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */ ++ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ ++ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */ ++ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */ ++ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */ ++ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined */ ++ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */ ++ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */ ++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ ++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ ++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ ++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ ++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */ ++ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */ ++ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */ ++ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */ ++ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ ++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ ++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */ ++ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */ ++ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */ ++ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */ ++ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */ ++ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */ ++ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register Empty */ ++ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register Empty */ ++} DMA_CH_TRIGSRC_t; ++ ++/* Double buffering mode */ ++typedef enum DMA_DBUFMODE_enum ++{ ++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ ++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ ++ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel 2/3 */ ++ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch. 0/1 and ch. 2/3 */ ++} DMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum DMA_PRIMODE_enum ++{ ++ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */ ++ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on channel 1/2/3 */ ++ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round Robin on channel 2/3 */ ++ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 > channel 3 */ ++} DMA_PRIMODE_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_ERRINTLVL_enum ++{ ++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ ++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ ++} DMA_CH_ERRINTLVL_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_TRNINTLVL_enum ++{ ++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ ++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ ++} DMA_CH_TRNINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ ++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ ++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ ++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t CH4CTRL; /* Channel 4 Control Register */ ++ register8_t CH5CTRL; /* Channel 5 Control Register */ ++ register8_t CH6CTRL; /* Channel 6 Control Register */ ++ register8_t CH7CTRL; /* Channel 7 Control Register */ ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ ++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ ++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */ ++ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */ ++ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */ ++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */ ++ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */ ++ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */ ++ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ ++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ ++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ ++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ ++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ ++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ ++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ ++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ ++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ ++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t reserved_0x07; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ _WORDREGISTER(CH1RES); /* Channel 1 Result */ ++ _WORDREGISTER(CH2RES); /* Channel 2 Result */ ++ _WORDREGISTER(CH3RES); /* Channel 3 Result */ ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++ ADC_CH_t CH1; /* ADC Channel 1 */ ++ ADC_CH_t CH2; /* ADC Channel 2 */ ++ ADC_CH_t CH3; /* ADC Channel 3 */ ++} ADC_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 (Input Mode = 2) */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 (Input Mode = 3) */ ++ ADC_CH_MUXNEG_GND_MODE3_gc = (0x05<<0), /* PAD Ground (Input Mode = 2) */ ++ ADC_CH_MUXNEG_INTGND_MODE3_gc = (0x07<<0), /* Internal Ground (Input Mode = 2) */ ++ ADC_CH_MUXNEG_INTGND_MODE4_gc = (0x04<<0), /* Internal Ground (Input Mode = 3) */ ++ ADC_CH_MUXNEG_GND_MODE4_gc = (0x07<<0), /* PAD Ground (Input Mode = 3) */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Current Limitation Mode */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No limit */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, max. sampling rate 1.5MSPS */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, max. sampling rate 1MSPS */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, max. sampling rate 0.5MSPS */ ++} ADC_CURRLIMIT_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Channel sweep selection */ ++typedef enum ADC_SWEEP_enum ++{ ++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ++ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */ ++ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */ ++ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */ ++} ADC_SWEEP_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */ ++ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel 0,1,2 */ ++ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */ ++ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* DMA request selection */ ++typedef enum ADC_DMASEL_enum ++{ ++ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */ ++ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */ ++ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */ ++ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */ ++} ADC_DMASEL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DAC - Digital/Analog Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Digital-to-Analog Converter */ ++typedef struct DAC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t EVCTRL; /* Event Input Control */ ++ register8_t reserved_0x04; ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0GAINCAL; /* Gain Calibration */ ++ register8_t CH0OFFSETCAL; /* Offset Calibration */ ++ register8_t CH1GAINCAL; /* Gain Calibration */ ++ register8_t CH1OFFSETCAL; /* Offset Calibration */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ ++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ ++} DAC_t; ++ ++/* Output channel selection */ ++typedef enum DAC_CHSEL_enum ++{ ++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ ++ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ ++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ ++} DAC_CHSEL_t; ++ ++/* Reference voltage selection */ ++typedef enum DAC_REFSEL_enum ++{ ++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ ++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ ++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ ++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ ++} DAC_REFSEL_t; ++ ++/* Event channel selection */ ++typedef enum DAC_EVSEL_enum ++{ ++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ ++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ ++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ ++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ ++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ ++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ ++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ ++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ ++} DAC_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* SDA Hold Time */ ++typedef enum TWI_SDAHOLD_enum ++{ ++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ ++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ ++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ ++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ ++} TWI_SDAHOLD_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USB - USB ++-------------------------------------------------------------------------- ++*/ ++ ++/* USB Endpoint */ ++typedef struct USB_EP_struct ++{ ++ register8_t STATUS; /* Endpoint Status */ ++ register8_t CTRL; /* Endpoint Control */ ++ _WORDREGISTER(CNT); /* USB Endpoint Counter */ ++ _WORDREGISTER(DATAPTR); /* Data Pointer */ ++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ ++} USB_EP_t; ++ ++ ++/* Universal Serial Bus */ ++typedef struct USB_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t FIFOWP; /* FIFO Write Pointer Register */ ++ register8_t FIFORP; /* FIFO Read Pointer Register */ ++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ ++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ ++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ ++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t reserved_0x20; ++ register8_t reserved_0x21; ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t CAL0; /* Calibration Byte 0 */ ++ register8_t CAL1; /* Calibration Byte 1 */ ++} USB_t; ++ ++ ++/* USB Endpoint Table */ ++typedef struct USB_EP_TABLE_struct ++{ ++ USB_EP_t EP0OUT; /* Endpoint 0 */ ++ USB_EP_t EP0IN; /* Endpoint 0 */ ++ USB_EP_t EP1OUT; /* Endpoint 1 */ ++ USB_EP_t EP1IN; /* Endpoint 1 */ ++ USB_EP_t EP2OUT; /* Endpoint 2 */ ++ USB_EP_t EP2IN; /* Endpoint 2 */ ++ USB_EP_t EP3OUT; /* Endpoint 3 */ ++ USB_EP_t EP3IN; /* Endpoint 3 */ ++ USB_EP_t EP4OUT; /* Endpoint 4 */ ++ USB_EP_t EP4IN; /* Endpoint 4 */ ++ USB_EP_t EP5OUT; /* Endpoint 5 */ ++ USB_EP_t EP5IN; /* Endpoint 5 */ ++ USB_EP_t EP6OUT; /* Endpoint 6 */ ++ USB_EP_t EP6IN; /* Endpoint 6 */ ++ USB_EP_t EP7OUT; /* Endpoint 7 */ ++ USB_EP_t EP7IN; /* Endpoint 7 */ ++ USB_EP_t EP8OUT; /* Endpoint 8 */ ++ USB_EP_t EP8IN; /* Endpoint 8 */ ++ USB_EP_t EP9OUT; /* Endpoint 9 */ ++ USB_EP_t EP9IN; /* Endpoint 9 */ ++ USB_EP_t EP10OUT; /* Endpoint 10 */ ++ USB_EP_t EP10IN; /* Endpoint 10 */ ++ USB_EP_t EP11OUT; /* Endpoint 11 */ ++ USB_EP_t EP11IN; /* Endpoint 11 */ ++ USB_EP_t EP12OUT; /* Endpoint 12 */ ++ USB_EP_t EP12IN; /* Endpoint 12 */ ++ USB_EP_t EP13OUT; /* Endpoint 13 */ ++ USB_EP_t EP13IN; /* Endpoint 13 */ ++ USB_EP_t EP14OUT; /* Endpoint 14 */ ++ USB_EP_t EP14IN; /* Endpoint 14 */ ++ USB_EP_t EP15OUT; /* Endpoint 15 */ ++ USB_EP_t EP15IN; /* Endpoint 15 */ ++ register8_t reserved_0x100; ++ register8_t reserved_0x101; ++ register8_t reserved_0x102; ++ register8_t reserved_0x103; ++ register8_t reserved_0x104; ++ register8_t reserved_0x105; ++ register8_t reserved_0x106; ++ register8_t reserved_0x107; ++ register8_t reserved_0x108; ++ register8_t reserved_0x109; ++ register8_t reserved_0x10A; ++ register8_t reserved_0x10B; ++ register8_t reserved_0x10C; ++ register8_t reserved_0x10D; ++ register8_t reserved_0x10E; ++ register8_t reserved_0x10F; ++ register8_t FRAMENUML; /* Frame Number Low Byte */ ++ register8_t FRAMENUMH; /* Frame Number High Byte */ ++} USB_EP_TABLE_t; ++ ++/* Interrupt level */ ++typedef enum USB_INTLVL_enum ++{ ++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} USB_INTLVL_t; ++ ++/* USB Endpoint Type */ ++typedef enum USB_EP_TYPE_enum ++{ ++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ ++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ ++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ ++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ ++} USB_EP_TYPE_t; ++ ++/* USB Endpoint Buffersize */ ++typedef enum USB_EP_BUFSIZE_enum ++{ ++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ ++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ ++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ ++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ ++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ ++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ ++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ ++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ ++} USB_EP_BUFSIZE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - I/O Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* I/O Port Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Byte Mode */ ++typedef enum TC_BYTEM_enum ++{ ++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ ++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ ++} TC_BYTEM_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC2 - 16-bit Timer/Counter type 2 ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter type 2 */ ++typedef struct TC2_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t reserved_0x03; ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t reserved_0x08; ++ register8_t CTRLF; /* Control Register F */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t LCNT; /* Low Byte Count */ ++ register8_t HCNT; /* High Byte Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t LPER; /* Low Byte Period */ ++ register8_t HPER; /* High Byte Period */ ++ register8_t LCMPA; /* Low Byte Compare A */ ++ register8_t HCMPA; /* High Byte Compare A */ ++ register8_t LCMPB; /* Low Byte Compare B */ ++ register8_t HCMPB; /* High Byte Compare B */ ++ register8_t LCMPC; /* Low Byte Compare C */ ++ register8_t HCMPC; /* High Byte Compare C */ ++ register8_t LCMPD; /* Low Byte Compare D */ ++ register8_t HCMPD; /* High Byte Compare D */ ++} TC2_t; ++ ++/* Clock Selection */ ++typedef enum TC2_CLKSEL_enum ++{ ++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC2_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC2_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC2_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC2_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC2_CLKSEL_t; ++ ++/* Byte Mode */ ++typedef enum TC2_BYTEM_enum ++{ ++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ ++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ ++} TC2_BYTEM_t; ++ ++/* High Byte Underflow Interrupt Level */ ++typedef enum TC2_HUNFINTLVL_enum ++{ ++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_HUNFINTLVL_t; ++ ++/* Low Byte Underflow Interrupt Level */ ++typedef enum TC2_LUNFINTLVL_enum ++{ ++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LUNFINTLVL_t; ++ ++/* Low Byte Compare D Interrupt Level */ ++typedef enum TC2_LCMPDINTLVL_enum ++{ ++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC2_LCMPDINTLVL_t; ++ ++/* Low Byte Compare C Interrupt Level */ ++typedef enum TC2_LCMPCINTLVL_enum ++{ ++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC2_LCMPCINTLVL_t; ++ ++/* Low Byte Compare B Interrupt Level */ ++typedef enum TC2_LCMPBINTLVL_enum ++{ ++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_LCMPBINTLVL_t; ++ ++/* Low Byte Compare A Interrupt Level */ ++typedef enum TC2_LCMPAINTLVL_enum ++{ ++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LCMPAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMD_enum ++{ ++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC2_CMD_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMDEN_enum ++{ ++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ ++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ ++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ ++} TC2_CMDEN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AWEX - Timer/Counter Advanced Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - Timer/Counter High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t reserved_0x00; ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* Timer Oscillator pin location */ ++typedef enum TOSCSEL_enum ++{ ++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ ++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ ++} TOSCSEL_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* BOD operation */ ++typedef enum BODACT_enum ++{ ++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BODACT_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WDP_enum ++{ ++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ ++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ ++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ ++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ ++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ ++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ ++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ ++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ ++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ ++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ ++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ ++} WDP_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LOCKBIT - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ ++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t USBCAL0; /* USB Calibration Byte 0 */ ++ register8_t USBCAL1; /* USB Calibration Byte 1 */ ++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ ++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ ++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ ++ register8_t DACB0OFFCAL; /* DACB0 Calibration Byte 0 */ ++ register8_t DACB0GAINCAL; /* DACB0 Calibration Byte 1 */ ++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ ++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ ++ register8_t DACB1OFFCAL; /* DACB1 Calibration Byte 0 */ ++ register8_t DACB1GAINCAL; /* DACB1 Calibration Byte 1 */ ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++ register8_t reserved_0x40; ++ register8_t reserved_0x41; ++ register8_t reserved_0x42; ++ register8_t reserved_0x43; ++ register8_t reserved_0x44; ++ register8_t reserved_0x45; ++ register8_t reserved_0x46; ++ register8_t reserved_0x47; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define AES (*(AES_t *) 0x00C0) /* AES Module */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define DACB (*(DAC_t *) 0x0320) /* Digital-to-Analog Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ ++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ ++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ ++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ ++#define TCD1 (*(TC1_t *) 0x0940) /* 16-bit Timer/Counter 1 */ ++#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ ++#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++#define GPIO_GPIOR4 _SFR_MEM8(0x0004) ++#define GPIO_GPIOR5 _SFR_MEM8(0x0005) ++#define GPIO_GPIOR6 _SFR_MEM8(0x0006) ++#define GPIO_GPIOR7 _SFR_MEM8(0x0007) ++#define GPIO_GPIOR8 _SFR_MEM8(0x0008) ++#define GPIO_GPIOR9 _SFR_MEM8(0x0009) ++#define GPIO_GPIORA _SFR_MEM8(0x000A) ++#define GPIO_GPIORB _SFR_MEM8(0x000B) ++#define GPIO_GPIORC _SFR_MEM8(0x000C) ++#define GPIO_GPIORD _SFR_MEM8(0x000D) ++#define GPIO_GPIORE _SFR_MEM8(0x000E) ++#define GPIO_GPIORF _SFR_MEM8(0x000F) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++#define GPIO_GPIO4 _SFR_MEM8(0x0004) ++#define GPIO_GPIO5 _SFR_MEM8(0x0005) ++#define GPIO_GPIO6 _SFR_MEM8(0x0006) ++#define GPIO_GPIO7 _SFR_MEM8(0x0007) ++#define GPIO_GPIO8 _SFR_MEM8(0x0008) ++#define GPIO_GPIO9 _SFR_MEM8(0x0009) ++#define GPIO_GPIOA _SFR_MEM8(0x000A) ++#define GPIO_GPIOB _SFR_MEM8(0x000B) ++#define GPIO_GPIOC _SFR_MEM8(0x000C) ++#define GPIO_GPIOD _SFR_MEM8(0x000D) ++#define GPIO_GPIOE _SFR_MEM8(0x000E) ++#define GPIO_GPIOF _SFR_MEM8(0x000F) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) ++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) ++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) ++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) ++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) ++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) ++#define PRODSIGNATURES_DACB0OFFCAL _SFR_MEM8(0x0032) ++#define PRODSIGNATURES_DACB0GAINCAL _SFR_MEM8(0x0033) ++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) ++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) ++#define PRODSIGNATURES_DACB1OFFCAL _SFR_MEM8(0x0036) ++#define PRODSIGNATURES_DACB1GAINCAL _SFR_MEM8(0x0037) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++#define CLK_USBCTRL _SFR_MEM8(0x0044) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLL - DFLL */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPB _SFR_MEM8(0x0072) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_EBIOUT _SFR_MEM8(0x00B5) ++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) ++ ++/* AES - AES Module */ ++#define AES_CTRL _SFR_MEM8(0x00C0) ++#define AES_STATUS _SFR_MEM8(0x00C1) ++#define AES_STATE _SFR_MEM8(0x00C2) ++#define AES_KEY _SFR_MEM8(0x00C3) ++#define AES_INTCTRL _SFR_MEM8(0x00C4) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* DMA - DMA Controller */ ++#define DMA_CTRL _SFR_MEM8(0x0100) ++#define DMA_INTFLAGS _SFR_MEM8(0x0103) ++#define DMA_STATUS _SFR_MEM8(0x0104) ++#define DMA_TEMP _SFR_MEM16(0x0106) ++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) ++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) ++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) ++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) ++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) ++#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A) ++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) ++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) ++#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E) ++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) ++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) ++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) ++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) ++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) ++#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A) ++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) ++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) ++#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E) ++#define DMA_CH2_CTRLA _SFR_MEM8(0x0130) ++#define DMA_CH2_CTRLB _SFR_MEM8(0x0131) ++#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) ++#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133) ++#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134) ++#define DMA_CH2_REPCNT _SFR_MEM8(0x0136) ++#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138) ++#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139) ++#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A) ++#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C) ++#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D) ++#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E) ++#define DMA_CH3_CTRLA _SFR_MEM8(0x0140) ++#define DMA_CH3_CTRLB _SFR_MEM8(0x0141) ++#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) ++#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143) ++#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144) ++#define DMA_CH3_REPCNT _SFR_MEM8(0x0146) ++#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148) ++#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149) ++#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A) ++#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C) ++#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D) ++#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH4MUX _SFR_MEM8(0x0184) ++#define EVSYS_CH5MUX _SFR_MEM8(0x0185) ++#define EVSYS_CH6MUX _SFR_MEM8(0x0186) ++#define EVSYS_CH7MUX _SFR_MEM8(0x0187) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) ++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) ++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) ++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CH1RES _SFR_MEM16(0x0212) ++#define ADCA_CH2RES _SFR_MEM16(0x0214) ++#define ADCA_CH3RES _SFR_MEM16(0x0216) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++#define ADCA_CH1_CTRL _SFR_MEM8(0x0228) ++#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229) ++#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A) ++#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B) ++#define ADCA_CH1_RES _SFR_MEM16(0x022C) ++#define ADCA_CH1_SCAN _SFR_MEM8(0x022E) ++#define ADCA_CH2_CTRL _SFR_MEM8(0x0230) ++#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231) ++#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232) ++#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233) ++#define ADCA_CH2_RES _SFR_MEM16(0x0234) ++#define ADCA_CH2_SCAN _SFR_MEM8(0x0236) ++#define ADCA_CH3_CTRL _SFR_MEM8(0x0238) ++#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239) ++#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A) ++#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B) ++#define ADCA_CH3_RES _SFR_MEM16(0x023C) ++#define ADCA_CH3_SCAN _SFR_MEM8(0x023E) ++ ++/* DAC - Digital-to-Analog Converter */ ++#define DACB_CTRLA _SFR_MEM8(0x0320) ++#define DACB_CTRLB _SFR_MEM8(0x0321) ++#define DACB_CTRLC _SFR_MEM8(0x0322) ++#define DACB_EVCTRL _SFR_MEM8(0x0323) ++#define DACB_STATUS _SFR_MEM8(0x0325) ++#define DACB_CH0GAINCAL _SFR_MEM8(0x0328) ++#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329) ++#define DACB_CH1GAINCAL _SFR_MEM8(0x032A) ++#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B) ++#define DACB_CH0DATA _SFR_MEM16(0x0338) ++#define DACB_CH1DATA _SFR_MEM16(0x033A) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* USB - Universal Serial Bus */ ++#define USB_CTRLA _SFR_MEM8(0x04C0) ++#define USB_CTRLB _SFR_MEM8(0x04C1) ++#define USB_STATUS _SFR_MEM8(0x04C2) ++#define USB_ADDR _SFR_MEM8(0x04C3) ++#define USB_FIFOWP _SFR_MEM8(0x04C4) ++#define USB_FIFORP _SFR_MEM8(0x04C5) ++#define USB_EPPTR _SFR_MEM16(0x04C6) ++#define USB_INTCTRLA _SFR_MEM8(0x04C8) ++#define USB_INTCTRLB _SFR_MEM8(0x04C9) ++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) ++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) ++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) ++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) ++#define USB_CAL0 _SFR_MEM8(0x04FA) ++#define USB_CAL1 _SFR_MEM8(0x04FB) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_REMAP _SFR_MEM8(0x060E) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_REMAP _SFR_MEM8(0x062E) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_REMAP _SFR_MEM8(0x068E) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCC2_CTRLA _SFR_MEM8(0x0800) ++#define TCC2_CTRLB _SFR_MEM8(0x0801) ++#define TCC2_CTRLC _SFR_MEM8(0x0802) ++#define TCC2_CTRLE _SFR_MEM8(0x0804) ++#define TCC2_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC2_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC2_CTRLF _SFR_MEM8(0x0809) ++#define TCC2_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC2_LCNT _SFR_MEM8(0x0820) ++#define TCC2_HCNT _SFR_MEM8(0x0821) ++#define TCC2_LPER _SFR_MEM8(0x0826) ++#define TCC2_HPER _SFR_MEM8(0x0827) ++#define TCC2_LCMPA _SFR_MEM8(0x0828) ++#define TCC2_HCMPA _SFR_MEM8(0x0829) ++#define TCC2_LCMPB _SFR_MEM8(0x082A) ++#define TCC2_HCMPB _SFR_MEM8(0x082B) ++#define TCC2_LCMPC _SFR_MEM8(0x082C) ++#define TCC2_HCMPC _SFR_MEM8(0x082D) ++#define TCC2_LCMPD _SFR_MEM8(0x082E) ++#define TCC2_HCMPD _SFR_MEM8(0x082F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_STATUSSET _SFR_MEM8(0x0885) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC1_DATA _SFR_MEM8(0x08B0) ++#define USARTC1_STATUS _SFR_MEM8(0x08B1) ++#define USARTC1_CTRLA _SFR_MEM8(0x08B3) ++#define USARTC1_CTRLB _SFR_MEM8(0x08B4) ++#define USARTC1_CTRLC _SFR_MEM8(0x08B5) ++#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6) ++#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCD2_CTRLA _SFR_MEM8(0x0900) ++#define TCD2_CTRLB _SFR_MEM8(0x0901) ++#define TCD2_CTRLC _SFR_MEM8(0x0902) ++#define TCD2_CTRLE _SFR_MEM8(0x0904) ++#define TCD2_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD2_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD2_CTRLF _SFR_MEM8(0x0909) ++#define TCD2_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD2_LCNT _SFR_MEM8(0x0920) ++#define TCD2_HCNT _SFR_MEM8(0x0921) ++#define TCD2_LPER _SFR_MEM8(0x0926) ++#define TCD2_HPER _SFR_MEM8(0x0927) ++#define TCD2_LCMPA _SFR_MEM8(0x0928) ++#define TCD2_HCMPA _SFR_MEM8(0x0929) ++#define TCD2_LCMPB _SFR_MEM8(0x092A) ++#define TCD2_HCMPB _SFR_MEM8(0x092B) ++#define TCD2_LCMPC _SFR_MEM8(0x092C) ++#define TCD2_HCMPC _SFR_MEM8(0x092D) ++#define TCD2_LCMPD _SFR_MEM8(0x092E) ++#define TCD2_HCMPD _SFR_MEM8(0x092F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCD1_CTRLA _SFR_MEM8(0x0940) ++#define TCD1_CTRLB _SFR_MEM8(0x0941) ++#define TCD1_CTRLC _SFR_MEM8(0x0942) ++#define TCD1_CTRLD _SFR_MEM8(0x0943) ++#define TCD1_CTRLE _SFR_MEM8(0x0944) ++#define TCD1_INTCTRLA _SFR_MEM8(0x0946) ++#define TCD1_INTCTRLB _SFR_MEM8(0x0947) ++#define TCD1_CTRLFCLR _SFR_MEM8(0x0948) ++#define TCD1_CTRLFSET _SFR_MEM8(0x0949) ++#define TCD1_CTRLGCLR _SFR_MEM8(0x094A) ++#define TCD1_CTRLGSET _SFR_MEM8(0x094B) ++#define TCD1_INTFLAGS _SFR_MEM8(0x094C) ++#define TCD1_TEMP _SFR_MEM8(0x094F) ++#define TCD1_CNT _SFR_MEM16(0x0960) ++#define TCD1_PER _SFR_MEM16(0x0966) ++#define TCD1_CCA _SFR_MEM16(0x0968) ++#define TCD1_CCB _SFR_MEM16(0x096A) ++#define TCD1_PERBUF _SFR_MEM16(0x0976) ++#define TCD1_CCABUF _SFR_MEM16(0x0978) ++#define TCD1_CCBBUF _SFR_MEM16(0x097A) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESD_CTRLA _SFR_MEM8(0x0990) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD1_DATA _SFR_MEM8(0x09B0) ++#define USARTD1_STATUS _SFR_MEM8(0x09B1) ++#define USARTD1_CTRLA _SFR_MEM8(0x09B3) ++#define USARTD1_CTRLB _SFR_MEM8(0x09B4) ++#define USARTD1_CTRLC _SFR_MEM8(0x09B5) ++#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6) ++#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESE_CTRLA _SFR_MEM8(0x0A90) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* CLK.USBCTRL bit masks and bit positions */ ++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ ++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ ++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ ++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ ++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ ++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ ++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ ++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ ++ ++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ ++#define CLK_USBSRC_gp 1 /* Clock Source group position. */ ++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ ++ ++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_USB_bm 0x40 /* USB bit mask. */ ++#define PR_USB_bp 6 /* USB bit position. */ ++ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ ++#define PR_EBI_bp 3 /* External Bus Interface bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ ++#define PR_DAC_bp 2 /* Port A DAC bit position. */ ++ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPB bit masks and bit positions */ ++/* PR_DAC Predefined. */ ++/* PR_DAC Predefined. */ ++ ++/* PR_ADC Predefined. */ ++/* PR_ADC Predefined. */ ++ ++/* PR_AC Predefined. */ ++/* PR_AC Predefined. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART1 Predefined. */ ++/* PR_USART1 Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_HIRES Predefined. */ ++/* PR_HIRES Predefined. */ ++ ++/* PR_TC1 Predefined. */ ++/* PR_TC1 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ ++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ ++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ ++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ ++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ ++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ ++ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXFLOCK_bm 0x08 /* AWeX on T/C F0 Lock bit mask. */ ++#define MCU_AWEXFLOCK_bp 3 /* AWeX on T/C F0 Lock bit position. */ ++ ++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ ++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ ++ ++#define MCU_AWEXDLOCK_bm 0x02 /* AWeX on T/C D0 Lock bit mask. */ ++#define MCU_AWEXDLOCK_bp 1 /* AWeX on T/C D0 Lock bit position. */ ++ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ ++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ ++ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ ++ ++/* PORTCFG.EBIOUT bit masks and bit positions */ ++#define PORTCFG_EBICSOUT_gm 0x03 /* EBI Chip Select Output group mask. */ ++#define PORTCFG_EBICSOUT_gp 0 /* EBI Chip Select Output group position. */ ++#define PORTCFG_EBICSOUT0_bm (1<<0) /* EBI Chip Select Output bit 0 mask. */ ++#define PORTCFG_EBICSOUT0_bp 0 /* EBI Chip Select Output bit 0 position. */ ++#define PORTCFG_EBICSOUT1_bm (1<<1) /* EBI Chip Select Output bit 1 mask. */ ++#define PORTCFG_EBICSOUT1_bp 1 /* EBI Chip Select Output bit 1 position. */ ++ ++#define PORTCFG_EBIADROUT_gm 0x0C /* EBI Address Output group mask. */ ++#define PORTCFG_EBIADROUT_gp 2 /* EBI Address Output group position. */ ++#define PORTCFG_EBIADROUT0_bm (1<<2) /* EBI Address Output bit 0 mask. */ ++#define PORTCFG_EBIADROUT0_bp 2 /* EBI Address Output bit 0 position. */ ++#define PORTCFG_EBIADROUT1_bm (1<<3) /* EBI Address Output bit 1 mask. */ ++#define PORTCFG_EBIADROUT1_bp 3 /* EBI Address Output bit 1 position. */ ++ ++/* PORTCFG.EVOUTSEL bit masks and bit positions */ ++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ ++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ ++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ ++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ ++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ ++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ ++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ ++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ ++ ++/* AES - AES Module */ ++/* AES.CTRL bit masks and bit positions */ ++#define AES_START_bm 0x80 /* Start/Run bit mask. */ ++#define AES_START_bp 7 /* Start/Run bit position. */ ++ ++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ ++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ ++ ++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ ++#define AES_RESET_bp 5 /* AES Software Reset bit position. */ ++ ++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ ++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ ++ ++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ ++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ ++ ++/* AES.STATUS bit masks and bit positions */ ++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ ++#define AES_ERROR_bp 7 /* AES Error bit position. */ ++ ++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ ++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ ++ ++/* AES.INTCTRL bit masks and bit positions */ ++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define AES_INTLVL_gp 0 /* Interrupt level group position. */ ++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* DMA - DMA Controller */ ++/* DMA_CH.CTRLA bit masks and bit positions */ ++#define DMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ ++#define DMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ ++ ++#define DMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ ++#define DMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ ++ ++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ ++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ ++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ ++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ ++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ ++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ ++ ++/* DMA_CH.CTRLB bit masks and bit positions */ ++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ ++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ ++ ++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ ++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ ++ ++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ ++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ ++ ++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ ++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ ++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ ++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ ++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ ++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ ++ ++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ ++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ ++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ ++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ ++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ ++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ ++ ++/* DMA_CH.ADDRCTRL bit masks and bit positions */ ++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ ++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ ++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ ++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ ++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ ++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ ++ ++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ ++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ ++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ ++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ ++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ ++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ ++ ++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ ++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ ++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ ++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ ++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ ++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ ++ ++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ ++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ ++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ ++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ ++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ ++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ ++ ++/* DMA_CH.TRIGSRC bit masks and bit positions */ ++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++/* DMA.CTRL bit masks and bit positions */ ++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define DMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define DMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define DMA_DBUFMODE_gm 0x0C /* Double Buffering Mode group mask. */ ++#define DMA_DBUFMODE_gp 2 /* Double Buffering Mode group position. */ ++#define DMA_DBUFMODE0_bm (1<<2) /* Double Buffering Mode bit 0 mask. */ ++#define DMA_DBUFMODE0_bp 2 /* Double Buffering Mode bit 0 position. */ ++#define DMA_DBUFMODE1_bm (1<<3) /* Double Buffering Mode bit 1 mask. */ ++#define DMA_DBUFMODE1_bp 3 /* Double Buffering Mode bit 1 position. */ ++ ++#define DMA_PRIMODE_gm 0x03 /* Channel Priority Mode group mask. */ ++#define DMA_PRIMODE_gp 0 /* Channel Priority Mode group position. */ ++#define DMA_PRIMODE0_bm (1<<0) /* Channel Priority Mode bit 0 mask. */ ++#define DMA_PRIMODE0_bp 0 /* Channel Priority Mode bit 0 position. */ ++#define DMA_PRIMODE1_bm (1<<1) /* Channel Priority Mode bit 1 mask. */ ++#define DMA_PRIMODE1_bp 1 /* Channel Priority Mode bit 1 position. */ ++ ++/* DMA.INTFLAGS bit masks and bit positions */ ++#define DMA_CH3ERRIF_bm 0x80 /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH3ERRIF_bp 7 /* Channel 3 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH2ERRIF_bm 0x40 /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH2ERRIF_bp 6 /* Channel 2 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH3TRNIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH3TRNIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH2TRNIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH2TRNIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++/* DMA.STATUS bit masks and bit positions */ ++#define DMA_CH3BUSY_bm 0x80 /* Channel 3 Block Transfer Busy bit mask. */ ++#define DMA_CH3BUSY_bp 7 /* Channel 3 Block Transfer Busy bit position. */ ++ ++#define DMA_CH2BUSY_bm 0x40 /* Channel 2 Block Transfer Busy bit mask. */ ++#define DMA_CH2BUSY_bp 6 /* Channel 2 Block Transfer Busy bit position. */ ++ ++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ ++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ ++ ++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ ++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ ++ ++#define DMA_CH3PEND_bm 0x08 /* Channel 3 Block Transfer Pending bit mask. */ ++#define DMA_CH3PEND_bp 3 /* Channel 3 Block Transfer Pending bit position. */ ++ ++#define DMA_CH2PEND_bm 0x04 /* Channel 2 Block Transfer Pending bit mask. */ ++#define DMA_CH2PEND_bp 2 /* Channel 2 Block Transfer Pending bit position. */ ++ ++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ ++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ ++ ++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ ++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH4MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH5MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH6MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH7MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM Predefined. */ ++/* EVSYS_QDIRM Predefined. */ ++ ++/* EVSYS_QDIEN Predefined. */ ++/* EVSYS_QDIEN Predefined. */ ++ ++/* EVSYS_QDEN Predefined. */ ++/* EVSYS_QDEN Predefined. */ ++ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH4CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM Predefined. */ ++/* EVSYS_QDIRM Predefined. */ ++ ++/* EVSYS_QDIEN Predefined. */ ++/* EVSYS_QDIEN Predefined. */ ++ ++/* EVSYS_QDEN Predefined. */ ++/* EVSYS_QDEN Predefined. */ ++ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH5CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH6CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH7CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x07 /* MUX selection on Negative ADC input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ ++#define ADC_CH_MUXNEG2_bm (1<<2) /* MUX selection on Negative ADC input bit 2 mask. */ ++#define ADC_CH_MUXNEG2_bp 2 /* MUX selection on Negative ADC input bit 2 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ ++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ ++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ ++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ ++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ ++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ ++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ ++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ ++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ ++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ ++ ++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ ++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ ++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ ++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ ++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ ++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ ++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ ++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ ++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ ++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_DMASEL_gm 0xC0 /* DMA Selection group mask. */ ++#define ADC_DMASEL_gp 6 /* DMA Selection group position. */ ++#define ADC_DMASEL0_bm (1<<6) /* DMA Selection bit 0 mask. */ ++#define ADC_DMASEL0_bp 6 /* DMA Selection bit 0 position. */ ++#define ADC_DMASEL1_bm (1<<7) /* DMA Selection bit 1 mask. */ ++#define ADC_DMASEL1_bp 7 /* DMA Selection bit 1 position. */ ++ ++#define ADC_CH3START_bm 0x20 /* Channel 3 Start Conversion bit mask. */ ++#define ADC_CH3START_bp 5 /* Channel 3 Start Conversion bit position. */ ++ ++#define ADC_CH2START_bm 0x10 /* Channel 2 Start Conversion bit mask. */ ++#define ADC_CH2START_bp 4 /* Channel 2 Start Conversion bit position. */ ++ ++#define ADC_CH1START_bm 0x08 /* Channel 1 Start Conversion bit mask. */ ++#define ADC_CH1START_bp 3 /* Channel 1 Start Conversion bit position. */ ++ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* Flush Pipeline bit mask. */ ++#define ADC_FLUSH_bp 1 /* Flush Pipeline bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_IMPMODE_bm 0x80 /* Gain Stage Impedance Mode bit mask. */ ++#define ADC_IMPMODE_bp 7 /* Gain Stage Impedance Mode bit position. */ ++ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ ++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ ++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ ++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ ++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ ++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ ++ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH3IF_bm 0x08 /* Channel 3 Interrupt Flag bit mask. */ ++#define ADC_CH3IF_bp 3 /* Channel 3 Interrupt Flag bit position. */ ++ ++#define ADC_CH2IF_bm 0x04 /* Channel 2 Interrupt Flag bit mask. */ ++#define ADC_CH2IF_bp 2 /* Channel 2 Interrupt Flag bit position. */ ++ ++#define ADC_CH1IF_bm 0x02 /* Channel 1 Interrupt Flag bit mask. */ ++#define ADC_CH1IF_bp 1 /* Channel 1 Interrupt Flag bit position. */ ++ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* DAC - Digital/Analog Converter */ ++/* DAC.CTRLA bit masks and bit positions */ ++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ ++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ ++ ++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ ++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ ++ ++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ ++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ ++ ++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ ++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ ++ ++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define DAC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* DAC.CTRLB bit masks and bit positions */ ++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ ++#define DAC_CHSEL_gp 5 /* Channel Select group position. */ ++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ ++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ ++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ ++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ ++ ++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ ++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ ++ ++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ ++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ ++ ++/* DAC.CTRLC bit masks and bit positions */ ++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ ++#define DAC_REFSEL_gp 3 /* Reference Select group position. */ ++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ ++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ ++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ ++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ ++ ++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ ++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ ++ ++/* DAC.EVCTRL bit masks and bit positions */ ++#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ ++#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ ++ ++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ ++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ ++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ ++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ ++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ ++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ ++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ ++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ ++ ++/* DAC.STATUS bit masks and bit positions */ ++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ ++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ ++ ++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ ++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ ++ ++/* DAC.CH0GAINCAL bit masks and bit positions */ ++#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH0OFFSETCAL bit masks and bit positions */ ++#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* DAC.CH1GAINCAL bit masks and bit positions */ ++#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH1OFFSETCAL bit masks and bit positions */ ++#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ ++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HSMODE Predefined. */ ++/* AC_HSMODE Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* RTC - Real-Time Counter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* USB - USB */ ++/* USB_EP.STATUS bit masks and bit positions */ ++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ ++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ ++ ++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ ++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ ++ ++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ ++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ ++ ++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ ++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ ++ ++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ ++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ ++ ++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ ++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ ++ ++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ ++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ ++ ++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ ++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ ++ ++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ ++ ++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ ++ ++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ ++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ ++ ++/* USB_EP.CTRL bit masks and bit positions */ ++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ ++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ ++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ ++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ ++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ ++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ ++ ++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ ++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ ++ ++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ ++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ ++ ++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ ++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ ++ ++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ ++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ ++ ++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ ++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ ++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ ++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ ++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ ++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ ++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ ++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ ++ ++/* USB_EP.CNT bit masks and bit positions */ ++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ ++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ ++ ++/* USB.CTRLA bit masks and bit positions */ ++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ ++#define USB_ENABLE_bp 7 /* USB Enable bit position. */ ++ ++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ ++#define USB_SPEED_bp 6 /* Speed Select bit position. */ ++ ++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ ++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ ++ ++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ ++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ ++ ++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ ++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ ++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ ++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ ++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ ++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ ++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ ++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ ++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ ++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ ++ ++/* USB.CTRLB bit masks and bit positions */ ++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ ++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ ++ ++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ ++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ ++ ++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ ++#define USB_GNACK_bp 1 /* Global NACK bit position. */ ++ ++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ ++#define USB_ATTACH_bp 0 /* Attach bit position. */ ++ ++/* USB.STATUS bit masks and bit positions */ ++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ ++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ ++ ++#define USB_RESUME_bm 0x04 /* Resume bit mask. */ ++#define USB_RESUME_bp 2 /* Resume bit position. */ ++ ++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ ++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ ++ ++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ ++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ ++ ++/* USB.ADDR bit masks and bit positions */ ++#define USB_ADDR_gm 0x7F /* Device Address group mask. */ ++#define USB_ADDR_gp 0 /* Device Address group position. */ ++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ ++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ ++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ ++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ ++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ ++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ ++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ ++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ ++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ ++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ ++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ ++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ ++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ ++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ ++ ++/* USB.FIFOWP bit masks and bit positions */ ++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ ++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ ++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ ++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ ++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ ++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ ++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ ++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ ++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ ++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ ++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ ++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ ++ ++/* USB.FIFORP bit masks and bit positions */ ++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ ++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ ++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ ++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ ++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ ++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ ++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ ++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ ++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ ++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ ++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ ++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ ++ ++/* USB.INTCTRLA bit masks and bit positions */ ++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ ++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ ++ ++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ ++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ ++ ++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ ++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ ++ ++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ ++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ ++ ++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* USB.INTCTRLB bit masks and bit positions */ ++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ ++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ ++ ++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ ++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ ++ ++/* USB.INTFLAGSACLR bit masks and bit positions */ ++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ ++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ ++ ++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ ++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ ++ ++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ ++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ ++ ++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ ++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ ++ ++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ ++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ ++ ++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ ++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ ++ ++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ ++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ ++ ++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ ++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSASET bit masks and bit positions */ ++/* USB_SOFIF Predefined. */ ++/* USB_SOFIF Predefined. */ ++ ++/* USB_SUSPENDIF Predefined. */ ++/* USB_SUSPENDIF Predefined. */ ++ ++/* USB_RESUMEIF Predefined. */ ++/* USB_RESUMEIF Predefined. */ ++ ++/* USB_RSTIF Predefined. */ ++/* USB_RSTIF Predefined. */ ++ ++/* USB_CRCIF Predefined. */ ++/* USB_CRCIF Predefined. */ ++ ++/* USB_UNFIF Predefined. */ ++/* USB_UNFIF Predefined. */ ++ ++/* USB_OVFIF Predefined. */ ++/* USB_OVFIF Predefined. */ ++ ++/* USB_STALLIF Predefined. */ ++/* USB_STALLIF Predefined. */ ++ ++/* USB.INTFLAGSBCLR bit masks and bit positions */ ++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ ++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ ++ ++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ ++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSBSET bit masks and bit positions */ ++/* USB_TRNIF Predefined. */ ++/* USB_TRNIF Predefined. */ ++ ++/* USB_SETUPIF Predefined. */ ++/* USB_SETUPIF Predefined. */ ++ ++/* PORT - I/O Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_SPI_bm 0x20 /* SPI bit mask. */ ++#define PORT_SPI_bp 5 /* SPI bit position. */ ++ ++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ ++#define PORT_USART0_bp 4 /* USART0 bit position. */ ++ ++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ ++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ ++ ++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ ++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ ++ ++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ ++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ ++ ++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ ++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD Predefined. */ ++/* TC0_CMD Predefined. */ ++ ++/* TC0_LUPD Predefined. */ ++/* TC0_LUPD Predefined. */ ++ ++/* TC0_DIR Predefined. */ ++/* TC0_DIR Predefined. */ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV Predefined. */ ++/* TC0_CCDBV Predefined. */ ++ ++/* TC0_CCCBV Predefined. */ ++/* TC0_CCCBV Predefined. */ ++ ++/* TC0_CCBBV Predefined. */ ++/* TC0_CCBBV Predefined. */ ++ ++/* TC0_CCABV Predefined. */ ++/* TC0_CCABV Predefined. */ ++ ++/* TC0_PERBV Predefined. */ ++/* TC0_PERBV Predefined. */ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD Predefined. */ ++/* TC1_CMD Predefined. */ ++ ++/* TC1_LUPD Predefined. */ ++/* TC1_LUPD Predefined. */ ++ ++/* TC1_DIR Predefined. */ ++/* TC1_DIR Predefined. */ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV Predefined. */ ++/* TC1_CCBBV Predefined. */ ++ ++/* TC1_CCABV Predefined. */ ++/* TC1_CCABV Predefined. */ ++ ++/* TC1_PERBV Predefined. */ ++/* TC1_PERBV Predefined. */ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++/* TC2.CTRLA bit masks and bit positions */ ++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC2.CTRLB bit masks and bit positions */ ++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ ++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ ++ ++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ ++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ ++ ++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ ++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ ++ ++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ ++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ ++ ++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ ++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ ++ ++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ ++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ ++ ++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ ++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ ++ ++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ ++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ ++ ++/* TC2.CTRLC bit masks and bit positions */ ++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ ++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ ++ ++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ ++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ ++ ++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ ++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ ++ ++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ ++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ ++ ++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ ++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ ++ ++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ ++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ ++ ++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ ++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ ++ ++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ ++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ ++ ++/* TC2.CTRLE bit masks and bit positions */ ++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC2.INTCTRLA bit masks and bit positions */ ++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ ++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ ++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ ++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ ++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ ++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ ++ ++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ ++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ ++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ ++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ ++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ ++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ ++ ++/* TC2.INTCTRLB bit masks and bit positions */ ++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ ++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ ++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ ++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ ++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ ++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ ++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ ++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ ++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ ++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ ++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ ++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ ++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ ++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ ++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ ++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ ++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ ++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ ++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ ++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ ++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ ++ ++/* TC2.CTRLF bit masks and bit positions */ ++#define TC2_CMD_gm 0x0C /* Command group mask. */ ++#define TC2_CMD_gp 2 /* Command group position. */ ++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC2_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC2_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ ++#define TC2_CMDEN_gp 0 /* Command Enable group position. */ ++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ ++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ ++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ ++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ ++ ++/* TC2.INTFLAGS bit masks and bit positions */ ++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ ++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ ++ ++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ ++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ ++ ++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ ++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ ++ ++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ ++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ ++ ++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ ++ ++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ ++ ++/* AWEX - Timer/Counter Advanced Waveform Extension */ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++/* AWEX.STATUSSET bit masks and bit positions */ ++/* AWEX_FDF Predefined. */ ++/* AWEX_FDF Predefined. */ ++ ++/* AWEX_DTHSBUFV Predefined. */ ++/* AWEX_DTHSBUFV Predefined. */ ++ ++/* AWEX_DTLSBUFV Predefined. */ ++/* AWEX_DTLSBUFV Predefined. */ ++ ++/* HIRES - Timer/Counter High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ ++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* LOCKBIT - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* DMA interrupt vectors */ ++#define DMA_CH0_vect_num 6 ++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ ++#define DMA_CH1_vect_num 7 ++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ ++#define DMA_CH2_vect_num 8 ++#define DMA_CH2_vect _VECTOR(8) /* Channel 2 Interrupt */ ++#define DMA_CH3_vect_num 9 ++#define DMA_CH3_vect _VECTOR(9) /* Channel 3 Interrupt */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LUNF_vect_num 14 ++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_HUNF_vect_num 15 ++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPA_vect_num 16 ++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPB_vect_num 17 ++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPC_vect_num 18 ++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPD_vect_num 19 ++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* USARTC1 interrupt vectors */ ++#define USARTC1_RXC_vect_num 28 ++#define USARTC1_RXC_vect _VECTOR(28) /* Reception Complete Interrupt */ ++#define USARTC1_DRE_vect_num 29 ++#define USARTC1_DRE_vect _VECTOR(29) /* Data Register Empty Interrupt */ ++#define USARTC1_TXC_vect_num 30 ++#define USARTC1_TXC_vect _VECTOR(30) /* Transmission Complete Interrupt */ ++ ++/* AES interrupt vectors */ ++#define AES_INT_vect_num 31 ++#define AES_INT_vect _VECTOR(31) /* AES Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++#define ADCA_CH1_vect_num 72 ++#define ADCA_CH1_vect _VECTOR(72) /* Interrupt 1 */ ++#define ADCA_CH2_vect_num 73 ++#define ADCA_CH2_vect _VECTOR(73) /* Interrupt 2 */ ++#define ADCA_CH3_vect_num 74 ++#define ADCA_CH3_vect _VECTOR(74) /* Interrupt 3 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LUNF_vect_num 77 ++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_HUNF_vect_num 78 ++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPA_vect_num 79 ++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPB_vect_num 80 ++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPC_vect_num 81 ++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPD_vect_num 82 ++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ ++ ++/* TCD1 interrupt vectors */ ++#define TCD1_OVF_vect_num 83 ++#define TCD1_OVF_vect _VECTOR(83) /* Overflow Interrupt */ ++#define TCD1_ERR_vect_num 84 ++#define TCD1_ERR_vect _VECTOR(84) /* Error Interrupt */ ++#define TCD1_CCA_vect_num 85 ++#define TCD1_CCA_vect _VECTOR(85) /* Compare or Capture A Interrupt */ ++#define TCD1_CCB_vect_num 86 ++#define TCD1_CCB_vect _VECTOR(86) /* Compare or Capture B Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* USARTD1 interrupt vectors */ ++#define USARTD1_RXC_vect_num 91 ++#define USARTD1_RXC_vect _VECTOR(91) /* Reception Complete Interrupt */ ++#define USARTD1_DRE_vect_num 92 ++#define USARTD1_DRE_vect _VECTOR(92) /* Data Register Empty Interrupt */ ++#define USARTD1_TXC_vect_num 93 ++#define USARTD1_TXC_vect _VECTOR(93) /* Transmission Complete Interrupt */ ++ ++/* USB interrupt vectors */ ++#define USB_BUSEVENT_vect_num 125 ++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ ++#define USB_TRNCOMPL_vect_num 126 ++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (127 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (69632) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (65536) ++#define APP_SECTION_PAGE_SIZE (256) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0xF000) ++#define APPTABLE_SECTION_SIZE (4096) ++#define APPTABLE_SECTION_PAGE_SIZE (256) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x10000) ++#define BOOT_SECTION_SIZE (4096) ++#define BOOT_SECTION_PAGE_SIZE (256) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (12288) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (2048) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (4096) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (2048) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (6) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (256) ++#define USER_SIGNATURES_PAGE_SIZE (256) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (64) ++#define PROD_SIGNATURES_PAGE_SIZE (256) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 256 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 Reserved */ ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x46 ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA64A4U_H_INCLUDED */ ++ +diff --git a/include/avr/iox64b1.h b/include/avr/iox64b1.h +new file mode 100644 +index 0000000..eac5252 +--- /dev/null ++++ b/include/avr/iox64b1.h +@@ -0,0 +1,6413 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox64b1.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA64B1_H_INCLUDED ++#define _AVR_ATXMEGA64B1_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t USBCTRL; /* USB Control Register */ ++} CLK_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++/* USB Prescaler Division Factor */ ++typedef enum CLK_USBPSDIV_enum ++{ ++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ ++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ ++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ ++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ ++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ ++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ ++} CLK_USBPSDIV_t; ++ ++/* USB Clock Source */ ++typedef enum CLK_USBSRC_enum ++{ ++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ ++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ ++} CLK_USBSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C0_gc = (0x01<<0), /* External Clock on port C0 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C1_gc = (0x05<<0), /* External Clock on port C1 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C2_gc = (0x09<<0), /* External Clock on port C2 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C3_gc = (0x0D<<0), /* External Clock on port C3 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C4_gc = (0x11<<0), /* External Clock on port C4 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C5_gc = (0x15<<0), /* External Clock on port C5 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C6_gc = (0x19<<0), /* External Clock on port C6 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C7_gc = (0x1D<<0), /* External Clock on port C7 - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 2 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC2MCREF_enum ++{ ++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC2MCREF_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PR - Power Reduction ++-------------------------------------------------------------------------- ++*/ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t PRPB; /* Power Reduction Port B */ ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t reserved_0x04; ++ register8_t PRPE; /* Power Reduction Port E */ ++} PR_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++ register8_t reserved_0x05; ++ register8_t EVOUTSEL; /* Event Output Select */ ++} PORTCFG_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP02MAP_enum ++{ ++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP02MAP_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP13MAP_enum ++{ ++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP13MAP_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC_gc = (0x01<<0), /* System Clock Output on Port C */ ++ PORTCFG_CLKOUT_PE_gc = (0x03<<0), /* System Clock Output on Port E */ ++} PORTCFG_CLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC_gc = (0x01<<4), /* Event Channel 0 Output on Port C */ ++ PORTCFG_EVOUT_PE_gc = (0x03<<4), /* Event Channel 0 Output on Port E */ ++} PORTCFG_EVOUT_t; ++ ++/* Clock and Event Output Port */ ++typedef enum PORTCFG_CLKEVPIN_enum ++{ ++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ ++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ ++} PORTCFG_CLKEVPIN_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<2), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<2), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<2), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<2), /* Event Channel 3 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AES - AES Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* AES Module */ ++typedef struct AES_struct ++{ ++ register8_t CTRL; /* AES Control Register */ ++ register8_t STATUS; /* AES Status Register */ ++ register8_t STATE; /* AES State Register */ ++ register8_t KEY; /* AES Key Register */ ++ register8_t INTCTRL; /* AES Interrupt Control Register */ ++} AES_t; ++ ++/* Interrupt level */ ++typedef enum AES_INTLVL_enum ++{ ++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} AES_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ ++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Channel */ ++typedef struct DMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Address Control */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ ++ register8_t REPCNT; /* Channel Repeat Count */ ++ register8_t reserved_0x07; ++ register8_t SRCADDR0; /* Channel Source Address 0 */ ++ register8_t SRCADDR1; /* Channel Source Address 1 */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t DESTADDR0; /* Channel Destination Address 0 */ ++ register8_t DESTADDR1; /* Channel Destination Address 1 */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} DMA_CH_t; ++ ++ ++/* DMA Controller */ ++typedef struct DMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TEMP); /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ DMA_CH_t CH0; /* DMA Channel 0 */ ++ DMA_CH_t CH1; /* DMA Channel 1 */ ++} DMA_t; ++ ++/* Burst mode */ ++typedef enum DMA_CH_BURSTLEN_enum ++{ ++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ ++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ ++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ ++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ ++} DMA_CH_BURSTLEN_t; ++ ++/* Source address reload mode */ ++typedef enum DMA_CH_SRCRELOAD_enum ++{ ++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ ++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ ++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ ++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ ++} DMA_CH_SRCRELOAD_t; ++ ++/* Source addressing mode */ ++typedef enum DMA_CH_SRCDIR_enum ++{ ++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ ++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ ++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ ++} DMA_CH_SRCDIR_t; ++ ++/* Destination adress reload mode */ ++typedef enum DMA_CH_DESTRELOAD_enum ++{ ++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ ++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ ++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ ++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ ++} DMA_CH_DESTRELOAD_t; ++ ++/* Destination adressing mode */ ++typedef enum DMA_CH_DESTDIR_enum ++{ ++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ ++} DMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum DMA_CH_TRIGSRC_enum ++{ ++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ ++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ ++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ ++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ ++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ ++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ ++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ ++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ ++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ ++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ ++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ ++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ ++} DMA_CH_TRIGSRC_t; ++ ++/* Double buffering mode */ ++typedef enum DMA_DBUFMODE_enum ++{ ++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ ++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ ++} DMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum DMA_PRIMODE_enum ++{ ++ DMA_PRIMODE_RR01_gc = (0x00<<0), /* Round Robin */ ++ DMA_PRIMODE_CH0RR1_gc = (0x01<<0), /* Channel 0 > channel 1 */ ++} DMA_PRIMODE_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_ERRINTLVL_enum ++{ ++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ ++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ ++} DMA_CH_ERRINTLVL_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_TRNINTLVL_enum ++{ ++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ ++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ ++} DMA_CH_TRNINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ ++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ ++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ ++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t reserved_0x07; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++} ADC_t; ++ ++/* Current Limitation */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ ++} ADC_CURRLIMIT_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ ++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ ++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ ++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++ register8_t CURRCTRL; /* Current Source Control Register */ ++ register8_t CURRCALIB; /* Current Source Calibration Register */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* SDA Hold Time */ ++typedef enum TWI_SDAHOLD_enum ++{ ++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ ++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ ++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ ++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ ++} TWI_SDAHOLD_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USB - USB ++-------------------------------------------------------------------------- ++*/ ++ ++/* USB Endpoint */ ++typedef struct USB_EP_struct ++{ ++ register8_t STATUS; /* Endpoint Status */ ++ register8_t CTRL; /* Endpoint Control */ ++ _WORDREGISTER(CNT); /* USB Endpoint Counter */ ++ _WORDREGISTER(DATAPTR); /* Data Pointer */ ++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ ++} USB_EP_t; ++ ++ ++/* Universal Serial Bus */ ++typedef struct USB_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t FIFOWP; /* FIFO Write Pointer Register */ ++ register8_t FIFORP; /* FIFO Read Pointer Register */ ++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ ++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ ++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ ++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t reserved_0x20; ++ register8_t reserved_0x21; ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t CAL0; /* Calibration Byte 0 */ ++ register8_t CAL1; /* Calibration Byte 1 */ ++} USB_t; ++ ++ ++/* USB Endpoint Table */ ++typedef struct USB_EP_TABLE_struct ++{ ++ USB_EP_t EP0OUT; /* Endpoint 0 */ ++ USB_EP_t EP0IN; /* Endpoint 0 */ ++ USB_EP_t EP1OUT; /* Endpoint 1 */ ++ USB_EP_t EP1IN; /* Endpoint 1 */ ++ USB_EP_t EP2OUT; /* Endpoint 2 */ ++ USB_EP_t EP2IN; /* Endpoint 2 */ ++ USB_EP_t EP3OUT; /* Endpoint 3 */ ++ USB_EP_t EP3IN; /* Endpoint 3 */ ++ USB_EP_t EP4OUT; /* Endpoint 4 */ ++ USB_EP_t EP4IN; /* Endpoint 4 */ ++ USB_EP_t EP5OUT; /* Endpoint 5 */ ++ USB_EP_t EP5IN; /* Endpoint 5 */ ++ USB_EP_t EP6OUT; /* Endpoint 6 */ ++ USB_EP_t EP6IN; /* Endpoint 6 */ ++ USB_EP_t EP7OUT; /* Endpoint 7 */ ++ USB_EP_t EP7IN; /* Endpoint 7 */ ++ USB_EP_t EP8OUT; /* Endpoint 8 */ ++ USB_EP_t EP8IN; /* Endpoint 8 */ ++ USB_EP_t EP9OUT; /* Endpoint 9 */ ++ USB_EP_t EP9IN; /* Endpoint 9 */ ++ USB_EP_t EP10OUT; /* Endpoint 10 */ ++ USB_EP_t EP10IN; /* Endpoint 10 */ ++ USB_EP_t EP11OUT; /* Endpoint 11 */ ++ USB_EP_t EP11IN; /* Endpoint 11 */ ++ USB_EP_t EP12OUT; /* Endpoint 12 */ ++ USB_EP_t EP12IN; /* Endpoint 12 */ ++ USB_EP_t EP13OUT; /* Endpoint 13 */ ++ USB_EP_t EP13IN; /* Endpoint 13 */ ++ USB_EP_t EP14OUT; /* Endpoint 14 */ ++ USB_EP_t EP14IN; /* Endpoint 14 */ ++ USB_EP_t EP15OUT; /* Endpoint 15 */ ++ USB_EP_t EP15IN; /* Endpoint 15 */ ++ register8_t reserved_0x100; ++ register8_t reserved_0x101; ++ register8_t reserved_0x102; ++ register8_t reserved_0x103; ++ register8_t reserved_0x104; ++ register8_t reserved_0x105; ++ register8_t reserved_0x106; ++ register8_t reserved_0x107; ++ register8_t reserved_0x108; ++ register8_t reserved_0x109; ++ register8_t reserved_0x10A; ++ register8_t reserved_0x10B; ++ register8_t reserved_0x10C; ++ register8_t reserved_0x10D; ++ register8_t reserved_0x10E; ++ register8_t reserved_0x10F; ++ register8_t FRAMENUML; /* Frame Number Low Byte */ ++ register8_t FRAMENUMH; /* Frame Number High Byte */ ++} USB_EP_TABLE_t; ++ ++/* Interrupt level */ ++typedef enum USB_INTLVL_enum ++{ ++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} USB_INTLVL_t; ++ ++/* USB Endpoint Type */ ++typedef enum USB_EP_TYPE_enum ++{ ++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ ++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ ++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ ++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ ++} USB_EP_TYPE_t; ++ ++/* USB Endpoint Buffersize */ ++typedef enum USB_EP_BUFSIZE_enum ++{ ++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ ++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ ++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ ++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ ++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ ++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ ++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ ++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ ++} USB_EP_BUFSIZE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - I/O Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* I/O Port Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Byte Mode */ ++typedef enum TC_BYTEM_enum ++{ ++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ ++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ ++} TC_BYTEM_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AWEX - Timer/Counter Advanced Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - Timer/Counter High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LCD - LCD Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* LCD Controller */ ++typedef struct LCD_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t INTCTRL; /* Interrupt Enable Register */ ++ register8_t INTFLAG; /* Interrupt Flag Register */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t CTRLF; /* Control Register F */ ++ register8_t CTRLG; /* Control Register G */ ++ register8_t CTRLH; /* Control Register H */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t DATA0; /* LCD Data Register 0 */ ++ register8_t DATA1; /* LCD Data Register 1 */ ++ register8_t DATA2; /* LCD Data Register 2 */ ++ register8_t DATA3; /* LCD Data Register 3 */ ++ register8_t DATA4; /* LCD Data Register 4 */ ++ register8_t DATA5; /* LCD Data Register 5 */ ++ register8_t DATA6; /* LCD Data Register 6 */ ++ register8_t DATA7; /* LCD Data Register 7 */ ++ register8_t DATA8; /* LCD Data Register 8 */ ++ register8_t DATA9; /* LCD Data Register 9 */ ++ register8_t DATA10; /* LCD Data Register 10 */ ++ register8_t DATA11; /* LCD Data Register 11 */ ++ register8_t DATA12; /* LCD Data Register 12 */ ++ register8_t DATA13; /* LCD Data Register 13 */ ++ register8_t DATA14; /* LCD Data Register 14 */ ++ register8_t DATA15; /* LCD Data Register 15 */ ++ register8_t DATA16; /* LCD Data Register 16 */ ++ register8_t DATA17; /* LCD Data Register 17 */ ++ register8_t DATA18; /* LCD Data Register 18 */ ++ register8_t DATA19; /* LCD Data Register 19 */ ++} LCD_t; ++ ++/* LCD Blink Rate */ ++typedef enum LCD_BLINKRATE_enum ++{ ++ LCD_BLINKRATE_4Hz_gc = (0x00<<0), /* 4Hz Blink Rate */ ++ LCD_BLINKRATE_2Hz_gc = (0x01<<0), /* 2Hz Blink Rate */ ++ LCD_BLINKRATE_1Hz_gc = (0x02<<0), /* 1Hz Blink Rate */ ++ LCD_BLINKRATE_0Hz5_gc = (0x03<<0), /* 0.5Hz Blink Rate */ ++} LCD_BLINKRATE_t; ++ ++/* LCD Clock Divide */ ++typedef enum LCD_CLKDIV_enum ++{ ++ LCD_CLKDIV_DivBy1_gc = (0x00<<4), /* frame rate of 256 Hz */ ++ LCD_CLKDIV_DivBy2_gc = (0x01<<4), /* frame rate of 128 Hz */ ++ LCD_CLKDIV_DivBy3_gc = (0x02<<4), /* frame rate of 83.5 Hz */ ++ LCD_CLKDIV_DivBy4_gc = (0x03<<4), /* frame rate of 64 Hz */ ++ LCD_CLKDIV_DivBy5_gc = (0x04<<4), /* frame rate of 51.2 Hz */ ++ LCD_CLKDIV_DivBy6_gc = (0x05<<4), /* frame rate of 42.7 Hz */ ++ LCD_CLKDIV_DivBy7_gc = (0x06<<4), /* frame rate of 36.6 Hz */ ++ LCD_CLKDIV_DivBy8_gc = (0x07<<4), /* frame rate of 32 Hz */ ++} LCD_CLKDIV_t; ++ ++/* Duty Select */ ++typedef enum LCD_DUTY_enum ++{ ++ LCD_DUTY_1_4_gc = (0x00<<0), /* Duty=1/4, Bias=1/3, COM0:3 */ ++ LCD_DUTY_Static_gc = (0x01<<0), /* Duty=Static, Bias=Static, COM0 */ ++ LCD_DUTY_1_2_gc = (0x02<<0), /* Duty=1/2, Bias=1/3, COM0:1 */ ++ LCD_DUTY_1_3_gc = (0x03<<0), /* Duty=1/3, Bias=1/3, COM0:2 */ ++} LCD_DUTY_t; ++ ++/* LCD Prescaler Select */ ++typedef enum LCD_PRESC_enum ++{ ++ LCD_PRESC_8_gc = (0x00<<7), /* clk_lcd/8 */ ++ LCD_PRESC_16_gc = (0x01<<7), /* clk_lcd/16 */ ++} LCD_PRESC_t; ++ ++/* Type of Digit */ ++typedef enum LCD_TDG_enum ++{ ++ LCD_TDG_7S_3C_gc = (0x00<<6), /* 7-segment with 3 COMs */ ++ LCD_TDG_7S_4C_gc = (0x01<<6), /* 7-segment with 4 COMs */ ++ LCD_TDG_14S_4C_gc = (0x02<<6), /* 14-segment with 4 COMs */ ++ LCD_TDG_16S_3C_gc = (0x03<<6), /* 16-segment with 3 COMs */ ++} LCD_TDG_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t FUSEBYTE0; /* JTAG User ID */ ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* Timer Oscillator pin location */ ++typedef enum TOSCSEL_enum ++{ ++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ ++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ ++} TOSCSEL_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* BOD operation */ ++typedef enum BODACT_enum ++{ ++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BODACT_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WDP_enum ++{ ++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ ++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ ++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ ++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ ++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ ++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ ++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ ++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ ++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ ++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ ++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ ++} WDP_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LOCKBIT - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ ++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t USBCAL0; /* USB Calibration Byte 0 */ ++ register8_t USBCAL1; /* USB Calibration Byte 1 */ ++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ ++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++ register8_t reserved_0x40; ++ register8_t reserved_0x41; ++ register8_t reserved_0x42; ++ register8_t reserved_0x43; ++ register8_t reserved_0x44; ++ register8_t reserved_0x45; ++ register8_t reserved_0x46; ++ register8_t reserved_0x47; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define AES (*(AES_t *) 0x00C0) /* AES Module */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ ++#define PORTG (*(PORT_t *) 0x06C0) /* I/O Ports */ ++#define PORTM (*(PORT_t *) 0x0760) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define LCD (*(LCD_t *) 0x0D00) /* LCD Controller */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) ++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) ++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) ++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) ++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++#define CLK_USBCTRL _SFR_MEM8(0x0044) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLL - DFLL */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPB _SFR_MEM8(0x0072) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPE _SFR_MEM8(0x0075) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) ++ ++/* AES - AES Module */ ++#define AES_CTRL _SFR_MEM8(0x00C0) ++#define AES_STATUS _SFR_MEM8(0x00C1) ++#define AES_STATE _SFR_MEM8(0x00C2) ++#define AES_KEY _SFR_MEM8(0x00C3) ++#define AES_INTCTRL _SFR_MEM8(0x00C4) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* DMA - DMA Controller */ ++#define DMA_CTRL _SFR_MEM8(0x0100) ++#define DMA_INTFLAGS _SFR_MEM8(0x0103) ++#define DMA_STATUS _SFR_MEM8(0x0104) ++#define DMA_TEMP _SFR_MEM16(0x0106) ++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) ++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) ++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) ++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) ++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) ++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) ++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) ++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) ++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) ++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) ++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) ++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) ++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) ++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCB_CTRLA _SFR_MEM8(0x0240) ++#define ADCB_CTRLB _SFR_MEM8(0x0241) ++#define ADCB_REFCTRL _SFR_MEM8(0x0242) ++#define ADCB_EVCTRL _SFR_MEM8(0x0243) ++#define ADCB_PRESCALER _SFR_MEM8(0x0244) ++#define ADCB_INTFLAGS _SFR_MEM8(0x0246) ++#define ADCB_TEMP _SFR_MEM8(0x0247) ++#define ADCB_SAMPCTRL _SFR_MEM8(0x0248) ++#define ADCB_CAL _SFR_MEM16(0x024C) ++#define ADCB_CH0RES _SFR_MEM16(0x0250) ++#define ADCB_CMP _SFR_MEM16(0x0258) ++#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) ++#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) ++#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) ++#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) ++#define ADCB_CH0_RES _SFR_MEM16(0x0264) ++#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++#define ACA_CURRCTRL _SFR_MEM8(0x0388) ++#define ACA_CURRCALIB _SFR_MEM8(0x0389) ++ ++/* AC - Analog Comparator */ ++#define ACB_AC0CTRL _SFR_MEM8(0x0390) ++#define ACB_AC1CTRL _SFR_MEM8(0x0391) ++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) ++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) ++#define ACB_CTRLA _SFR_MEM8(0x0394) ++#define ACB_CTRLB _SFR_MEM8(0x0395) ++#define ACB_WINCTRL _SFR_MEM8(0x0396) ++#define ACB_STATUS _SFR_MEM8(0x0397) ++#define ACB_CURRCTRL _SFR_MEM8(0x0398) ++#define ACB_CURRCALIB _SFR_MEM8(0x0399) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* USB - Universal Serial Bus */ ++#define USB_CTRLA _SFR_MEM8(0x04C0) ++#define USB_CTRLB _SFR_MEM8(0x04C1) ++#define USB_STATUS _SFR_MEM8(0x04C2) ++#define USB_ADDR _SFR_MEM8(0x04C3) ++#define USB_FIFOWP _SFR_MEM8(0x04C4) ++#define USB_FIFORP _SFR_MEM8(0x04C5) ++#define USB_EPPTR _SFR_MEM16(0x04C6) ++#define USB_INTCTRLA _SFR_MEM8(0x04C8) ++#define USB_INTCTRLB _SFR_MEM8(0x04C9) ++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) ++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) ++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) ++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) ++#define USB_CAL0 _SFR_MEM8(0x04FA) ++#define USB_CAL1 _SFR_MEM8(0x04FB) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_REMAP _SFR_MEM8(0x060E) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_REMAP _SFR_MEM8(0x062E) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_REMAP _SFR_MEM8(0x068E) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORT - I/O Ports */ ++#define PORTG_DIR _SFR_MEM8(0x06C0) ++#define PORTG_DIRSET _SFR_MEM8(0x06C1) ++#define PORTG_DIRCLR _SFR_MEM8(0x06C2) ++#define PORTG_DIRTGL _SFR_MEM8(0x06C3) ++#define PORTG_OUT _SFR_MEM8(0x06C4) ++#define PORTG_OUTSET _SFR_MEM8(0x06C5) ++#define PORTG_OUTCLR _SFR_MEM8(0x06C6) ++#define PORTG_OUTTGL _SFR_MEM8(0x06C7) ++#define PORTG_IN _SFR_MEM8(0x06C8) ++#define PORTG_INTCTRL _SFR_MEM8(0x06C9) ++#define PORTG_INT0MASK _SFR_MEM8(0x06CA) ++#define PORTG_INT1MASK _SFR_MEM8(0x06CB) ++#define PORTG_INTFLAGS _SFR_MEM8(0x06CC) ++#define PORTG_REMAP _SFR_MEM8(0x06CE) ++#define PORTG_PIN0CTRL _SFR_MEM8(0x06D0) ++#define PORTG_PIN1CTRL _SFR_MEM8(0x06D1) ++#define PORTG_PIN2CTRL _SFR_MEM8(0x06D2) ++#define PORTG_PIN3CTRL _SFR_MEM8(0x06D3) ++#define PORTG_PIN4CTRL _SFR_MEM8(0x06D4) ++#define PORTG_PIN5CTRL _SFR_MEM8(0x06D5) ++#define PORTG_PIN6CTRL _SFR_MEM8(0x06D6) ++#define PORTG_PIN7CTRL _SFR_MEM8(0x06D7) ++ ++/* PORT - I/O Ports */ ++#define PORTM_DIR _SFR_MEM8(0x0760) ++#define PORTM_DIRSET _SFR_MEM8(0x0761) ++#define PORTM_DIRCLR _SFR_MEM8(0x0762) ++#define PORTM_DIRTGL _SFR_MEM8(0x0763) ++#define PORTM_OUT _SFR_MEM8(0x0764) ++#define PORTM_OUTSET _SFR_MEM8(0x0765) ++#define PORTM_OUTCLR _SFR_MEM8(0x0766) ++#define PORTM_OUTTGL _SFR_MEM8(0x0767) ++#define PORTM_IN _SFR_MEM8(0x0768) ++#define PORTM_INTCTRL _SFR_MEM8(0x0769) ++#define PORTM_INT0MASK _SFR_MEM8(0x076A) ++#define PORTM_INT1MASK _SFR_MEM8(0x076B) ++#define PORTM_INTFLAGS _SFR_MEM8(0x076C) ++#define PORTM_REMAP _SFR_MEM8(0x076E) ++#define PORTM_PIN0CTRL _SFR_MEM8(0x0770) ++#define PORTM_PIN1CTRL _SFR_MEM8(0x0771) ++#define PORTM_PIN2CTRL _SFR_MEM8(0x0772) ++#define PORTM_PIN3CTRL _SFR_MEM8(0x0773) ++#define PORTM_PIN4CTRL _SFR_MEM8(0x0774) ++#define PORTM_PIN5CTRL _SFR_MEM8(0x0775) ++#define PORTM_PIN6CTRL _SFR_MEM8(0x0776) ++#define PORTM_PIN7CTRL _SFR_MEM8(0x0777) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_STATUSSET _SFR_MEM8(0x0885) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* LCD - LCD Controller */ ++#define LCD_CTRLA _SFR_MEM8(0x0D00) ++#define LCD_CTRLB _SFR_MEM8(0x0D01) ++#define LCD_CTRLC _SFR_MEM8(0x0D02) ++#define LCD_INTCTRL _SFR_MEM8(0x0D03) ++#define LCD_INTFLAG _SFR_MEM8(0x0D04) ++#define LCD_CTRLD _SFR_MEM8(0x0D05) ++#define LCD_CTRLE _SFR_MEM8(0x0D06) ++#define LCD_CTRLF _SFR_MEM8(0x0D07) ++#define LCD_CTRLG _SFR_MEM8(0x0D08) ++#define LCD_CTRLH _SFR_MEM8(0x0D09) ++#define LCD_DATA0 _SFR_MEM8(0x0D10) ++#define LCD_DATA1 _SFR_MEM8(0x0D11) ++#define LCD_DATA2 _SFR_MEM8(0x0D12) ++#define LCD_DATA3 _SFR_MEM8(0x0D13) ++#define LCD_DATA4 _SFR_MEM8(0x0D14) ++#define LCD_DATA5 _SFR_MEM8(0x0D15) ++#define LCD_DATA6 _SFR_MEM8(0x0D16) ++#define LCD_DATA7 _SFR_MEM8(0x0D17) ++#define LCD_DATA8 _SFR_MEM8(0x0D18) ++#define LCD_DATA9 _SFR_MEM8(0x0D19) ++#define LCD_DATA10 _SFR_MEM8(0x0D1A) ++#define LCD_DATA11 _SFR_MEM8(0x0D1B) ++#define LCD_DATA12 _SFR_MEM8(0x0D1C) ++#define LCD_DATA13 _SFR_MEM8(0x0D1D) ++#define LCD_DATA14 _SFR_MEM8(0x0D1E) ++#define LCD_DATA15 _SFR_MEM8(0x0D1F) ++#define LCD_DATA16 _SFR_MEM8(0x0D20) ++#define LCD_DATA17 _SFR_MEM8(0x0D21) ++#define LCD_DATA18 _SFR_MEM8(0x0D22) ++#define LCD_DATA19 _SFR_MEM8(0x0D23) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* CLK.USBCTRL bit masks and bit positions */ ++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ ++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ ++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ ++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ ++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ ++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ ++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ ++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ ++ ++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ ++#define CLK_USBSRC_gp 1 /* Clock Source group position. */ ++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ ++ ++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ ++#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* PR - Power Reduction */ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_LCD_bm 0x80 /* LCD Module bit mask. */ ++#define PR_LCD_bp 7 /* LCD Module bit position. */ ++ ++#define PR_USB_bm 0x40 /* USB bit mask. */ ++#define PR_USB_bp 6 /* USB bit position. */ ++ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPB bit masks and bit positions */ ++/* PR_ADC Predefined. */ ++/* PR_ADC Predefined. */ ++ ++/* PR_AC Predefined. */ ++/* PR_AC Predefined. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ ++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ ++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ ++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ ++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ ++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ ++ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ ++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ ++ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ ++ ++/* PORTCFG.EVOUTSEL bit masks and bit positions */ ++#define PORTCFG_EVOUTSEL_bm 0x04 /* Event Output Select bit mask. */ ++#define PORTCFG_EVOUTSEL_bp 2 /* Event Output Select bit position. */ ++ ++/* AES - AES Module */ ++/* AES.CTRL bit masks and bit positions */ ++#define AES_START_bm 0x80 /* Start/Run bit mask. */ ++#define AES_START_bp 7 /* Start/Run bit position. */ ++ ++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ ++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ ++ ++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ ++#define AES_RESET_bp 5 /* AES Software Reset bit position. */ ++ ++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ ++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ ++ ++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ ++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ ++ ++/* AES.STATUS bit masks and bit positions */ ++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ ++#define AES_ERROR_bp 7 /* AES Error bit position. */ ++ ++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ ++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ ++ ++/* AES.INTCTRL bit masks and bit positions */ ++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define AES_INTLVL_gp 0 /* Interrupt level group position. */ ++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* DMA - DMA Controller */ ++/* DMA_CH.CTRLA bit masks and bit positions */ ++#define DMA_CH_CHEN_bm 0x80 /* Channel Enable bit mask. */ ++#define DMA_CH_CHEN_bp 7 /* Channel Enable bit position. */ ++ ++#define DMA_CH_CHRST_bm 0x40 /* Channel Software Reset bit mask. */ ++#define DMA_CH_CHRST_bp 6 /* Channel Software Reset bit position. */ ++ ++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ ++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ ++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ ++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ ++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ ++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ ++ ++/* DMA_CH.CTRLB bit masks and bit positions */ ++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ ++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ ++ ++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ ++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ ++ ++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ ++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ ++ ++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ ++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ ++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ ++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ ++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ ++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ ++ ++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ ++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ ++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ ++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ ++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ ++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ ++ ++/* DMA_CH.ADDRCTRL bit masks and bit positions */ ++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ ++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ ++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ ++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ ++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ ++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ ++ ++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ ++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ ++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ ++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ ++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ ++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ ++ ++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ ++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ ++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ ++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ ++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ ++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ ++ ++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ ++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ ++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ ++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ ++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ ++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ ++ ++/* DMA_CH.TRIGSRC bit masks and bit positions */ ++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++/* DMA.CTRL bit masks and bit positions */ ++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define DMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define DMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define DMA_DBUFMODE_bm 0x04 /* Double Buffering Mode bit mask. */ ++#define DMA_DBUFMODE_bp 2 /* Double Buffering Mode bit position. */ ++ ++#define DMA_PRIMODE_bm 0x01 /* Channel Priority Mode bit mask. */ ++#define DMA_PRIMODE_bp 0 /* Channel Priority Mode bit position. */ ++ ++/* DMA.INTFLAGS bit masks and bit positions */ ++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++/* DMA.STATUS bit masks and bit positions */ ++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ ++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ ++ ++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ ++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ ++ ++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ ++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ ++ ++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ ++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ ++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ ++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ ++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ ++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ ++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ ++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ ++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ ++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ ++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ ++ ++#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */ ++#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */ ++#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ ++#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */ ++#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ ++#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */ ++#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ ++#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */ ++#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ ++#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ ++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* ADC.SAMPCTRL bit masks and bit positions */ ++#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ ++#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ ++#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ ++#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ ++#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ ++#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ ++#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ ++#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ ++#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ ++#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ ++#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ ++#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ ++#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ ++#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* AC.CURRCTRL bit masks and bit positions */ ++#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ ++#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ ++ ++#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ ++#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ ++ ++#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ ++#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ ++ ++#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ ++#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ ++ ++/* AC.CURRCALIB bit masks and bit positions */ ++#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ ++#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ ++#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ ++#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ ++#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ ++#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ ++#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ ++#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ ++#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ ++#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ ++ ++/* RTC - Real-Time Counter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* USB - USB */ ++/* USB_EP.STATUS bit masks and bit positions */ ++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ ++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ ++ ++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ ++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ ++ ++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ ++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ ++ ++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ ++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ ++ ++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ ++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ ++ ++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ ++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ ++ ++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ ++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ ++ ++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ ++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ ++ ++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ ++ ++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ ++ ++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ ++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ ++ ++/* USB_EP.CTRL bit masks and bit positions */ ++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ ++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ ++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ ++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ ++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ ++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ ++ ++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ ++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ ++ ++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ ++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ ++ ++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ ++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ ++ ++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ ++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ ++ ++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ ++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ ++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ ++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ ++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ ++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ ++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ ++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ ++ ++/* USB_EP.CNT bit masks and bit positions */ ++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ ++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ ++ ++/* USB.CTRLA bit masks and bit positions */ ++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ ++#define USB_ENABLE_bp 7 /* USB Enable bit position. */ ++ ++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ ++#define USB_SPEED_bp 6 /* Speed Select bit position. */ ++ ++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ ++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ ++ ++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ ++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ ++ ++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ ++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ ++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ ++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ ++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ ++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ ++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ ++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ ++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ ++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ ++ ++/* USB.CTRLB bit masks and bit positions */ ++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ ++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ ++ ++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ ++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ ++ ++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ ++#define USB_GNACK_bp 1 /* Global NACK bit position. */ ++ ++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ ++#define USB_ATTACH_bp 0 /* Attach bit position. */ ++ ++/* USB.STATUS bit masks and bit positions */ ++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ ++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ ++ ++#define USB_RESUME_bm 0x04 /* Resume bit mask. */ ++#define USB_RESUME_bp 2 /* Resume bit position. */ ++ ++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ ++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ ++ ++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ ++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ ++ ++/* USB.ADDR bit masks and bit positions */ ++#define USB_ADDR_gm 0x7F /* Device Address group mask. */ ++#define USB_ADDR_gp 0 /* Device Address group position. */ ++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ ++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ ++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ ++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ ++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ ++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ ++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ ++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ ++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ ++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ ++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ ++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ ++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ ++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ ++ ++/* USB.FIFOWP bit masks and bit positions */ ++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ ++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ ++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ ++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ ++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ ++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ ++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ ++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ ++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ ++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ ++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ ++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ ++ ++/* USB.FIFORP bit masks and bit positions */ ++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ ++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ ++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ ++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ ++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ ++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ ++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ ++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ ++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ ++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ ++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ ++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ ++ ++/* USB.INTCTRLA bit masks and bit positions */ ++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ ++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ ++ ++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ ++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ ++ ++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ ++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ ++ ++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ ++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ ++ ++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* USB.INTCTRLB bit masks and bit positions */ ++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ ++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ ++ ++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ ++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ ++ ++/* USB.INTFLAGSACLR bit masks and bit positions */ ++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ ++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ ++ ++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ ++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ ++ ++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ ++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ ++ ++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ ++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ ++ ++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ ++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ ++ ++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ ++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ ++ ++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ ++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ ++ ++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ ++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSASET bit masks and bit positions */ ++/* USB_SOFIF Predefined. */ ++/* USB_SOFIF Predefined. */ ++ ++/* USB_SUSPENDIF Predefined. */ ++/* USB_SUSPENDIF Predefined. */ ++ ++/* USB_RESUMEIF Predefined. */ ++/* USB_RESUMEIF Predefined. */ ++ ++/* USB_RSTIF Predefined. */ ++/* USB_RSTIF Predefined. */ ++ ++/* USB_CRCIF Predefined. */ ++/* USB_CRCIF Predefined. */ ++ ++/* USB_UNFIF Predefined. */ ++/* USB_UNFIF Predefined. */ ++ ++/* USB_OVFIF Predefined. */ ++/* USB_OVFIF Predefined. */ ++ ++/* USB_STALLIF Predefined. */ ++/* USB_STALLIF Predefined. */ ++ ++/* USB.INTFLAGSBCLR bit masks and bit positions */ ++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ ++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ ++ ++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ ++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSBSET bit masks and bit positions */ ++/* USB_TRNIF Predefined. */ ++/* USB_TRNIF Predefined. */ ++ ++/* USB_SETUPIF Predefined. */ ++/* USB_SETUPIF Predefined. */ ++ ++/* PORT - I/O Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_SPI_bm 0x20 /* SPI bit mask. */ ++#define PORT_SPI_bp 5 /* SPI bit position. */ ++ ++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ ++#define PORT_USART0_bp 4 /* USART0 bit position. */ ++ ++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ ++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ ++ ++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ ++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ ++ ++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ ++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ ++ ++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ ++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD Predefined. */ ++/* TC0_CMD Predefined. */ ++ ++/* TC0_LUPD Predefined. */ ++/* TC0_LUPD Predefined. */ ++ ++/* TC0_DIR Predefined. */ ++/* TC0_DIR Predefined. */ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV Predefined. */ ++/* TC0_CCDBV Predefined. */ ++ ++/* TC0_CCCBV Predefined. */ ++/* TC0_CCCBV Predefined. */ ++ ++/* TC0_CCBBV Predefined. */ ++/* TC0_CCBBV Predefined. */ ++ ++/* TC0_CCABV Predefined. */ ++/* TC0_CCABV Predefined. */ ++ ++/* TC0_PERBV Predefined. */ ++/* TC0_PERBV Predefined. */ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD Predefined. */ ++/* TC1_CMD Predefined. */ ++ ++/* TC1_LUPD Predefined. */ ++/* TC1_LUPD Predefined. */ ++ ++/* TC1_DIR Predefined. */ ++/* TC1_DIR Predefined. */ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV Predefined. */ ++/* TC1_CCBBV Predefined. */ ++ ++/* TC1_CCABV Predefined. */ ++/* TC1_CCABV Predefined. */ ++ ++/* TC1_PERBV Predefined. */ ++/* TC1_PERBV Predefined. */ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* AWEX - Timer/Counter Advanced Waveform Extension */ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++/* AWEX.STATUSSET bit masks and bit positions */ ++/* AWEX_FDF Predefined. */ ++/* AWEX_FDF Predefined. */ ++ ++/* AWEX_DTHSBUFV Predefined. */ ++/* AWEX_DTHSBUFV Predefined. */ ++ ++/* AWEX_DTLSBUFV Predefined. */ ++/* AWEX_DTLSBUFV Predefined. */ ++ ++/* HIRES - Timer/Counter High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* LCD - LCD Controller */ ++/* LCD.CTRLA bit masks and bit positions */ ++#define LCD_ENABLE_bm 0x80 /* LCD Enable bit mask. */ ++#define LCD_ENABLE_bp 7 /* LCD Enable bit position. */ ++ ++#define LCD_XBIAS_bm 0x40 /* External Register Bias Generation bit mask. */ ++#define LCD_XBIAS_bp 6 /* External Register Bias Generation bit position. */ ++ ++#define LCD_DATCLK_bm 0x20 /* Data Register Lock bit mask. */ ++#define LCD_DATCLK_bp 5 /* Data Register Lock bit position. */ ++ ++#define LCD_COMSWP_bm 0x10 /* Common Bus Swap bit mask. */ ++#define LCD_COMSWP_bp 4 /* Common Bus Swap bit position. */ ++ ++#define LCD_SEGSWP_bm 0x08 /* Segment Bus Swap bit mask. */ ++#define LCD_SEGSWP_bp 3 /* Segment Bus Swap bit position. */ ++ ++#define LCD_CLRDT_bm 0x04 /* Clear Data Register bit mask. */ ++#define LCD_CLRDT_bp 2 /* Clear Data Register bit position. */ ++ ++#define LCD_SEGON_bm 0x02 /* Segments On bit mask. */ ++#define LCD_SEGON_bp 1 /* Segments On bit position. */ ++ ++#define LCD_BLANK_bm 0x01 /* Blanking Display Mode bit mask. */ ++#define LCD_BLANK_bp 0 /* Blanking Display Mode bit position. */ ++ ++/* LCD.CTRLB bit masks and bit positions */ ++#define LCD_PRESC_bm 0x80 /* LCD Prescaler Select bit mask. */ ++#define LCD_PRESC_bp 7 /* LCD Prescaler Select bit position. */ ++ ++#define LCD_CLKDIV_gm 0x70 /* LCD Clock Divide group mask. */ ++#define LCD_CLKDIV_gp 4 /* LCD Clock Divide group position. */ ++#define LCD_CLKDIV0_bm (1<<4) /* LCD Clock Divide bit 0 mask. */ ++#define LCD_CLKDIV0_bp 4 /* LCD Clock Divide bit 0 position. */ ++#define LCD_CLKDIV1_bm (1<<5) /* LCD Clock Divide bit 1 mask. */ ++#define LCD_CLKDIV1_bp 5 /* LCD Clock Divide bit 1 position. */ ++#define LCD_CLKDIV2_bm (1<<6) /* LCD Clock Divide bit 2 mask. */ ++#define LCD_CLKDIV2_bp 6 /* LCD Clock Divide bit 2 position. */ ++ ++#define LCD_LPWAV_bm 0x08 /* Low Power Waveform bit mask. */ ++#define LCD_LPWAV_bp 3 /* Low Power Waveform bit position. */ ++ ++#define LCD_DUTY_gm 0x03 /* Duty Select group mask. */ ++#define LCD_DUTY_gp 0 /* Duty Select group position. */ ++#define LCD_DUTY0_bm (1<<0) /* Duty Select bit 0 mask. */ ++#define LCD_DUTY0_bp 0 /* Duty Select bit 0 position. */ ++#define LCD_DUTY1_bm (1<<1) /* Duty Select bit 1 mask. */ ++#define LCD_DUTY1_bp 1 /* Duty Select bit 1 position. */ ++ ++/* LCD.CTRLC bit masks and bit positions */ ++#define LCD_PMSK_gm 0x3F /* LCD Port Mask group mask. */ ++#define LCD_PMSK_gp 0 /* LCD Port Mask group position. */ ++#define LCD_PMSK0_bm (1<<0) /* LCD Port Mask bit 0 mask. */ ++#define LCD_PMSK0_bp 0 /* LCD Port Mask bit 0 position. */ ++#define LCD_PMSK1_bm (1<<1) /* LCD Port Mask bit 1 mask. */ ++#define LCD_PMSK1_bp 1 /* LCD Port Mask bit 1 position. */ ++#define LCD_PMSK2_bm (1<<2) /* LCD Port Mask bit 2 mask. */ ++#define LCD_PMSK2_bp 2 /* LCD Port Mask bit 2 position. */ ++#define LCD_PMSK3_bm (1<<3) /* LCD Port Mask bit 3 mask. */ ++#define LCD_PMSK3_bp 3 /* LCD Port Mask bit 3 position. */ ++#define LCD_PMSK4_bm (1<<4) /* LCD Port Mask bit 4 mask. */ ++#define LCD_PMSK4_bp 4 /* LCD Port Mask bit 4 position. */ ++#define LCD_PMSK5_bm (1<<5) /* LCD Port Mask bit 5 mask. */ ++#define LCD_PMSK5_bp 5 /* LCD Port Mask bit 5 position. */ ++ ++/* LCD.INTCTRL bit masks and bit positions */ ++#define LCD_XIME_gm 0xF8 /* eXtended Interrupt Mode Enable group mask. */ ++#define LCD_XIME_gp 3 /* eXtended Interrupt Mode Enable group position. */ ++#define LCD_XIME0_bm (1<<3) /* eXtended Interrupt Mode Enable bit 0 mask. */ ++#define LCD_XIME0_bp 3 /* eXtended Interrupt Mode Enable bit 0 position. */ ++#define LCD_XIME1_bm (1<<4) /* eXtended Interrupt Mode Enable bit 1 mask. */ ++#define LCD_XIME1_bp 4 /* eXtended Interrupt Mode Enable bit 1 position. */ ++#define LCD_XIME2_bm (1<<5) /* eXtended Interrupt Mode Enable bit 2 mask. */ ++#define LCD_XIME2_bp 5 /* eXtended Interrupt Mode Enable bit 2 position. */ ++#define LCD_XIME3_bm (1<<6) /* eXtended Interrupt Mode Enable bit 3 mask. */ ++#define LCD_XIME3_bp 6 /* eXtended Interrupt Mode Enable bit 3 position. */ ++#define LCD_XIME4_bm (1<<7) /* eXtended Interrupt Mode Enable bit 4 mask. */ ++#define LCD_XIME4_bp 7 /* eXtended Interrupt Mode Enable bit 4 position. */ ++ ++#define LCD_FCINTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define LCD_FCINTLVL_gp 0 /* Interrupt Level group position. */ ++#define LCD_FCINTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define LCD_FCINTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define LCD_FCINTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define LCD_FCINTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* LCD.INTFLAG bit masks and bit positions */ ++#define LCD_FCIF_bm 0x01 /* LCD Frame Completed Interrupt Flag bit mask. */ ++#define LCD_FCIF_bp 0 /* LCD Frame Completed Interrupt Flag bit position. */ ++ ++/* LCD.CTRLD bit masks and bit positions */ ++#define LCD_BLINKEN_bm 0x08 /* Blink Enable bit mask. */ ++#define LCD_BLINKEN_bp 3 /* Blink Enable bit position. */ ++ ++#define LCD_BLINKRATE_gm 0x03 /* LCD Blink Rate group mask. */ ++#define LCD_BLINKRATE_gp 0 /* LCD Blink Rate group position. */ ++#define LCD_BLINKRATE0_bm (1<<0) /* LCD Blink Rate bit 0 mask. */ ++#define LCD_BLINKRATE0_bp 0 /* LCD Blink Rate bit 0 position. */ ++#define LCD_BLINKRATE1_bm (1<<1) /* LCD Blink Rate bit 1 mask. */ ++#define LCD_BLINKRATE1_bp 1 /* LCD Blink Rate bit 1 position. */ ++ ++/* LCD.CTRLE bit masks and bit positions */ ++#define LCD_BPS1_gm 0xF0 /* Blink Pixel Selection 1 group mask. */ ++#define LCD_BPS1_gp 4 /* Blink Pixel Selection 1 group position. */ ++#define LCD_BPS10_bm (1<<4) /* Blink Pixel Selection 1 bit 0 mask. */ ++#define LCD_BPS10_bp 4 /* Blink Pixel Selection 1 bit 0 position. */ ++#define LCD_BPS11_bm (1<<5) /* Blink Pixel Selection 1 bit 1 mask. */ ++#define LCD_BPS11_bp 5 /* Blink Pixel Selection 1 bit 1 position. */ ++#define LCD_BPS12_bm (1<<6) /* Blink Pixel Selection 1 bit 2 mask. */ ++#define LCD_BPS12_bp 6 /* Blink Pixel Selection 1 bit 2 position. */ ++#define LCD_BPS13_bm (1<<7) /* Blink Pixel Selection 1 bit 3 mask. */ ++#define LCD_BPS13_bp 7 /* Blink Pixel Selection 1 bit 3 position. */ ++ ++#define LCD_BPS0_gm 0x0F /* Blink Pixel Selection 0 group mask. */ ++#define LCD_BPS0_gp 0 /* Blink Pixel Selection 0 group position. */ ++#define LCD_BPS00_bm (1<<0) /* Blink Pixel Selection 0 bit 0 mask. */ ++#define LCD_BPS00_bp 0 /* Blink Pixel Selection 0 bit 0 position. */ ++#define LCD_BPS01_bm (1<<1) /* Blink Pixel Selection 0 bit 1 mask. */ ++#define LCD_BPS01_bp 1 /* Blink Pixel Selection 0 bit 1 position. */ ++#define LCD_BPS02_bm (1<<2) /* Blink Pixel Selection 0 bit 2 mask. */ ++#define LCD_BPS02_bp 2 /* Blink Pixel Selection 0 bit 2 position. */ ++#define LCD_BPS03_bm (1<<3) /* Blink Pixel Selection 0 bit 3 mask. */ ++#define LCD_BPS03_bp 3 /* Blink Pixel Selection 0 bit 3 position. */ ++ ++/* LCD.CTRLF bit masks and bit positions */ ++#define LCD_FCONT_gm 0x3F /* Fine Contrast group mask. */ ++#define LCD_FCONT_gp 0 /* Fine Contrast group position. */ ++#define LCD_FCONT0_bm (1<<0) /* Fine Contrast bit 0 mask. */ ++#define LCD_FCONT0_bp 0 /* Fine Contrast bit 0 position. */ ++#define LCD_FCONT1_bm (1<<1) /* Fine Contrast bit 1 mask. */ ++#define LCD_FCONT1_bp 1 /* Fine Contrast bit 1 position. */ ++#define LCD_FCONT2_bm (1<<2) /* Fine Contrast bit 2 mask. */ ++#define LCD_FCONT2_bp 2 /* Fine Contrast bit 2 position. */ ++#define LCD_FCONT3_bm (1<<3) /* Fine Contrast bit 3 mask. */ ++#define LCD_FCONT3_bp 3 /* Fine Contrast bit 3 position. */ ++#define LCD_FCONT4_bm (1<<4) /* Fine Contrast bit 4 mask. */ ++#define LCD_FCONT4_bp 4 /* Fine Contrast bit 4 position. */ ++#define LCD_FCONT5_bm (1<<5) /* Fine Contrast bit 5 mask. */ ++#define LCD_FCONT5_bp 5 /* Fine Contrast bit 5 position. */ ++ ++/* LCD.CTRLG bit masks and bit positions */ ++#define LCD_TDG_gm 0xC0 /* Type of Digit group mask. */ ++#define LCD_TDG_gp 6 /* Type of Digit group position. */ ++#define LCD_TDG0_bm (1<<6) /* Type of Digit bit 0 mask. */ ++#define LCD_TDG0_bp 6 /* Type of Digit bit 0 position. */ ++#define LCD_TDG1_bm (1<<7) /* Type of Digit bit 1 mask. */ ++#define LCD_TDG1_bp 7 /* Type of Digit bit 1 position. */ ++ ++#define LCD_STSEG_gm 0x3F /* Start Segment group mask. */ ++#define LCD_STSEG_gp 0 /* Start Segment group position. */ ++#define LCD_STSEG0_bm (1<<0) /* Start Segment bit 0 mask. */ ++#define LCD_STSEG0_bp 0 /* Start Segment bit 0 position. */ ++#define LCD_STSEG1_bm (1<<1) /* Start Segment bit 1 mask. */ ++#define LCD_STSEG1_bp 1 /* Start Segment bit 1 position. */ ++#define LCD_STSEG2_bm (1<<2) /* Start Segment bit 2 mask. */ ++#define LCD_STSEG2_bp 2 /* Start Segment bit 2 position. */ ++#define LCD_STSEG3_bm (1<<3) /* Start Segment bit 3 mask. */ ++#define LCD_STSEG3_bp 3 /* Start Segment bit 3 position. */ ++#define LCD_STSEG4_bm (1<<4) /* Start Segment bit 4 mask. */ ++#define LCD_STSEG4_bp 4 /* Start Segment bit 4 position. */ ++#define LCD_STSEG5_bm (1<<5) /* Start Segment bit 5 mask. */ ++#define LCD_STSEG5_bp 5 /* Start Segment bit 5 position. */ ++ ++/* LCD.CTRLH bit masks and bit positions */ ++#define LCD_DEC_bm 0x80 /* Decrement of Start Segment bit mask. */ ++#define LCD_DEC_bp 7 /* Decrement of Start Segment bit position. */ ++ ++#define LCD_DCODE_gm 0x7F /* Display Code group mask. */ ++#define LCD_DCODE_gp 0 /* Display Code group position. */ ++#define LCD_DCODE0_bm (1<<0) /* Display Code bit 0 mask. */ ++#define LCD_DCODE0_bp 0 /* Display Code bit 0 position. */ ++#define LCD_DCODE1_bm (1<<1) /* Display Code bit 1 mask. */ ++#define LCD_DCODE1_bp 1 /* Display Code bit 1 position. */ ++#define LCD_DCODE2_bm (1<<2) /* Display Code bit 2 mask. */ ++#define LCD_DCODE2_bp 2 /* Display Code bit 2 position. */ ++#define LCD_DCODE3_bm (1<<3) /* Display Code bit 3 mask. */ ++#define LCD_DCODE3_bp 3 /* Display Code bit 3 position. */ ++#define LCD_DCODE4_bm (1<<4) /* Display Code bit 4 mask. */ ++#define LCD_DCODE4_bp 4 /* Display Code bit 4 position. */ ++#define LCD_DCODE5_bm (1<<5) /* Display Code bit 5 mask. */ ++#define LCD_DCODE5_bp 5 /* Display Code bit 5 position. */ ++#define LCD_DCODE6_bm (1<<6) /* Display Code bit 6 mask. */ ++#define LCD_DCODE6_bp 6 /* Display Code bit 6 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ ++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ ++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ ++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ ++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ ++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ ++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ ++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ ++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ ++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ ++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ ++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ ++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ ++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ ++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ ++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ ++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ ++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ ++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ ++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ ++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* LOCKBIT - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* DMA interrupt vectors */ ++#define DMA_CH0_vect_num 6 ++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ ++#define DMA_CH1_vect_num 7 ++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* USB interrupt vectors */ ++#define USB_BUSEVENT_vect_num 31 ++#define USB_BUSEVENT_vect _VECTOR(31) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ ++#define USB_TRNCOMPL_vect_num 32 ++#define USB_TRNCOMPL_vect _VECTOR(32) /* Transaction complete interrupt */ ++ ++/* LCD interrupt vectors */ ++#define LCD_INT_vect_num 35 ++#define LCD_INT_vect _VECTOR(35) /* LCD Interrupt */ ++ ++/* AES interrupt vectors */ ++#define AES_INT_vect_num 36 ++#define AES_INT_vect _VECTOR(36) /* AES Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 37 ++#define NVM_EE_vect _VECTOR(37) /* EE Interrupt */ ++#define NVM_SPM_vect_num 38 ++#define NVM_SPM_vect _VECTOR(38) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 39 ++#define PORTB_INT0_vect _VECTOR(39) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 40 ++#define PORTB_INT1_vect _VECTOR(40) /* External Interrupt 1 */ ++ ++/* ACB interrupt vectors */ ++#define ACB_AC0_vect_num 41 ++#define ACB_AC0_vect _VECTOR(41) /* AC0 Interrupt */ ++#define ACB_AC1_vect_num 42 ++#define ACB_AC1_vect _VECTOR(42) /* AC1 Interrupt */ ++#define ACB_ACW_vect_num 43 ++#define ACB_ACW_vect _VECTOR(43) /* ACW Window Mode Interrupt */ ++ ++/* ADCB interrupt vectors */ ++#define ADCB_CH0_vect_num 44 ++#define ADCB_CH0_vect _VECTOR(44) /* Interrupt 0 */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 48 ++#define PORTD_INT0_vect _VECTOR(48) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 49 ++#define PORTD_INT1_vect _VECTOR(49) /* External Interrupt 1 */ ++ ++/* PORTG interrupt vectors */ ++#define PORTG_INT0_vect_num 50 ++#define PORTG_INT0_vect _VECTOR(50) /* External Interrupt 0 */ ++#define PORTG_INT1_vect_num 51 ++#define PORTG_INT1_vect _VECTOR(51) /* External Interrupt 1 */ ++ ++/* PORTM interrupt vectors */ ++#define PORTM_INT0_vect_num 52 ++#define PORTM_INT0_vect _VECTOR(52) /* External Interrupt 0 */ ++#define PORTM_INT1_vect_num 53 ++#define PORTM_INT1_vect _VECTOR(53) /* External Interrupt 1 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 54 ++#define PORTE_INT0_vect _VECTOR(54) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 55 ++#define PORTE_INT1_vect _VECTOR(55) /* External Interrupt 1 */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 58 ++#define TCE0_OVF_vect _VECTOR(58) /* Overflow Interrupt */ ++#define TCE0_ERR_vect_num 59 ++#define TCE0_ERR_vect _VECTOR(59) /* Error Interrupt */ ++#define TCE0_CCA_vect_num 60 ++#define TCE0_CCA_vect _VECTOR(60) /* Compare or Capture A Interrupt */ ++#define TCE0_CCB_vect_num 61 ++#define TCE0_CCB_vect _VECTOR(61) /* Compare or Capture B Interrupt */ ++#define TCE0_CCC_vect_num 62 ++#define TCE0_CCC_vect _VECTOR(62) /* Compare or Capture C Interrupt */ ++#define TCE0_CCD_vect_num 63 ++#define TCE0_CCD_vect _VECTOR(63) /* Compare or Capture D Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 69 ++#define USARTE0_RXC_vect _VECTOR(69) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 70 ++#define USARTE0_DRE_vect _VECTOR(70) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 71 ++#define USARTE0_TXC_vect _VECTOR(71) /* Transmission Complete Interrupt */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 75 ++#define PORTA_INT0_vect _VECTOR(75) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 76 ++#define PORTA_INT1_vect _VECTOR(76) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 77 ++#define ACA_AC0_vect _VECTOR(77) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 78 ++#define ACA_AC1_vect _VECTOR(78) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 79 ++#define ACA_ACW_vect _VECTOR(79) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 80 ++#define ADCA_CH0_vect _VECTOR(80) /* Interrupt 0 */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (81 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (69632) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (65536) ++#define APP_SECTION_PAGE_SIZE (256) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0xF000) ++#define APPTABLE_SECTION_SIZE (4096) ++#define APPTABLE_SECTION_PAGE_SIZE (256) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x10000) ++#define BOOT_SECTION_SIZE (4096) ++#define BOOT_SECTION_PAGE_SIZE (256) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (12288) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (2048) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (4096) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (2048) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (6) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (256) ++#define USER_SIGNATURES_PAGE_SIZE (256) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (256) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 256 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 */ ++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ ++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ ++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ ++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ ++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ ++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ ++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ ++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ ++#define FUSE0_DEFAULT (0xFF) ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x52 ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA64B1_H_INCLUDED */ ++ +diff --git a/include/avr/iox64b3.h b/include/avr/iox64b3.h +new file mode 100644 +index 0000000..0e0e904 +--- /dev/null ++++ b/include/avr/iox64b3.h +@@ -0,0 +1,6247 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox64b3.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA64B3_H_INCLUDED ++#define _AVR_ATXMEGA64B3_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t USBCTRL; /* USB Control Register */ ++} CLK_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++/* USB Prescaler Division Factor */ ++typedef enum CLK_USBPSDIV_enum ++{ ++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ ++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ ++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ ++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ ++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ ++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ ++} CLK_USBPSDIV_t; ++ ++/* USB Clock Source */ ++typedef enum CLK_USBSRC_enum ++{ ++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ ++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ ++} CLK_USBSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C0_gc = (0x01<<0), /* External Clock on port C0 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C1_gc = (0x05<<0), /* External Clock on port C1 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C2_gc = (0x09<<0), /* External Clock on port C2 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C3_gc = (0x0D<<0), /* External Clock on port C3 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C4_gc = (0x11<<0), /* External Clock on port C4 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C5_gc = (0x15<<0), /* External Clock on port C5 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C6_gc = (0x19<<0), /* External Clock on port C6 - 6 CLK */ ++ OSC_XOSCSEL_EXTCLK_C7_gc = (0x1D<<0), /* External Clock on port C7 - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 2 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC2MCREF_enum ++{ ++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC2MCREF_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PR - Power Reduction ++-------------------------------------------------------------------------- ++*/ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t PRPB; /* Power Reduction Port B */ ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t reserved_0x04; ++ register8_t PRPE; /* Power Reduction Port E */ ++} PR_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++ register8_t reserved_0x05; ++ register8_t EVOUTSEL; /* Event Output Select */ ++} PORTCFG_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP02MAP_enum ++{ ++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP02MAP_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP13MAP_enum ++{ ++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP13MAP_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC_gc = (0x01<<0), /* System Clock Output on Port C */ ++ PORTCFG_CLKOUT_PE_gc = (0x03<<0), /* System Clock Output on Port E */ ++} PORTCFG_CLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC_gc = (0x01<<4), /* Event Channel 0 Output on Port C */ ++ PORTCFG_EVOUT_PE_gc = (0x03<<4), /* Event Channel 0 Output on Port E */ ++} PORTCFG_EVOUT_t; ++ ++/* Clock and Event Output Port */ ++typedef enum PORTCFG_CLKEVPIN_enum ++{ ++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ ++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ ++} PORTCFG_CLKEVPIN_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<2), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<2), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<2), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<2), /* Event Channel 3 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AES - AES Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* AES Module */ ++typedef struct AES_struct ++{ ++ register8_t CTRL; /* AES Control Register */ ++ register8_t STATUS; /* AES Status Register */ ++ register8_t STATE; /* AES State Register */ ++ register8_t KEY; /* AES Key Register */ ++ register8_t INTCTRL; /* AES Interrupt Control Register */ ++} AES_t; ++ ++/* Interrupt level */ ++typedef enum AES_INTLVL_enum ++{ ++ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} AES_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ ++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DMA - DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* DMA Channel */ ++typedef struct DMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Address Control */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */ ++ register8_t REPCNT; /* Channel Repeat Count */ ++ register8_t reserved_0x07; ++ register8_t SRCADDR0; /* Channel Source Address 0 */ ++ register8_t SRCADDR1; /* Channel Source Address 1 */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t DESTADDR0; /* Channel Destination Address 0 */ ++ register8_t DESTADDR1; /* Channel Destination Address 1 */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} DMA_CH_t; ++ ++ ++/* DMA Controller */ ++typedef struct DMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TEMP); /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ DMA_CH_t CH0; /* DMA Channel 0 */ ++ DMA_CH_t CH1; /* DMA Channel 1 */ ++} DMA_t; ++ ++/* Burst mode */ ++typedef enum DMA_CH_BURSTLEN_enum ++{ ++ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */ ++ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */ ++ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */ ++ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */ ++} DMA_CH_BURSTLEN_t; ++ ++/* Source address reload mode */ ++typedef enum DMA_CH_SRCRELOAD_enum ++{ ++ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */ ++ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */ ++ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */ ++ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of transaction */ ++} DMA_CH_SRCRELOAD_t; ++ ++/* Source addressing mode */ ++typedef enum DMA_CH_SRCDIR_enum ++{ ++ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */ ++ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */ ++ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */ ++} DMA_CH_SRCDIR_t; ++ ++/* Destination adress reload mode */ ++typedef enum DMA_CH_DESTRELOAD_enum ++{ ++ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */ ++ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */ ++ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */ ++ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of transaction */ ++} DMA_CH_DESTRELOAD_t; ++ ++/* Destination adressing mode */ ++typedef enum DMA_CH_DESTDIR_enum ++{ ++ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */ ++} DMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum DMA_CH_TRIGSRC_enum ++{ ++ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */ ++ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */ ++ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */ ++ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */ ++ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */ ++ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */ ++ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */ ++ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */ ++ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */ ++ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */ ++ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or Capture B */ ++ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */ ++ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register Empty */ ++ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */ ++ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */ ++ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or Capture A */ ++ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or Capture B */ ++ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or Capture C */ ++ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or Capture D */ ++ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */ ++ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register Empty */ ++} DMA_CH_TRIGSRC_t; ++ ++/* Double buffering mode */ ++typedef enum DMA_DBUFMODE_enum ++{ ++ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */ ++ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel 0/1 */ ++} DMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum DMA_PRIMODE_enum ++{ ++ DMA_PRIMODE_RR01_gc = (0x00<<0), /* Round Robin */ ++ DMA_PRIMODE_CH0RR1_gc = (0x01<<0), /* Channel 0 > channel 1 */ ++} DMA_PRIMODE_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_ERRINTLVL_enum ++{ ++ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */ ++ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */ ++} DMA_CH_ERRINTLVL_t; ++ ++/* Interrupt level */ ++typedef enum DMA_CH_TRNINTLVL_enum ++{ ++ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */ ++ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */ ++} DMA_CH_TRNINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */ ++ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */ ++ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ ++ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t reserved_0x07; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++} ADC_t; ++ ++/* Current Limitation */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ ++} ADC_CURRLIMIT_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ ++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ ++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ ++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++ register8_t CURRCTRL; /* Current Source Control Register */ ++ register8_t CURRCALIB; /* Current Source Calibration Register */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* SDA Hold Time */ ++typedef enum TWI_SDAHOLD_enum ++{ ++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ ++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ ++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ ++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ ++} TWI_SDAHOLD_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USB - USB ++-------------------------------------------------------------------------- ++*/ ++ ++/* USB Endpoint */ ++typedef struct USB_EP_struct ++{ ++ register8_t STATUS; /* Endpoint Status */ ++ register8_t CTRL; /* Endpoint Control */ ++ _WORDREGISTER(CNT); /* USB Endpoint Counter */ ++ _WORDREGISTER(DATAPTR); /* Data Pointer */ ++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ ++} USB_EP_t; ++ ++ ++/* Universal Serial Bus */ ++typedef struct USB_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t FIFOWP; /* FIFO Write Pointer Register */ ++ register8_t FIFORP; /* FIFO Read Pointer Register */ ++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ ++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ ++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ ++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t reserved_0x20; ++ register8_t reserved_0x21; ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t CAL0; /* Calibration Byte 0 */ ++ register8_t CAL1; /* Calibration Byte 1 */ ++} USB_t; ++ ++ ++/* USB Endpoint Table */ ++typedef struct USB_EP_TABLE_struct ++{ ++ USB_EP_t EP0OUT; /* Endpoint 0 */ ++ USB_EP_t EP0IN; /* Endpoint 0 */ ++ USB_EP_t EP1OUT; /* Endpoint 1 */ ++ USB_EP_t EP1IN; /* Endpoint 1 */ ++ USB_EP_t EP2OUT; /* Endpoint 2 */ ++ USB_EP_t EP2IN; /* Endpoint 2 */ ++ USB_EP_t EP3OUT; /* Endpoint 3 */ ++ USB_EP_t EP3IN; /* Endpoint 3 */ ++ USB_EP_t EP4OUT; /* Endpoint 4 */ ++ USB_EP_t EP4IN; /* Endpoint 4 */ ++ USB_EP_t EP5OUT; /* Endpoint 5 */ ++ USB_EP_t EP5IN; /* Endpoint 5 */ ++ USB_EP_t EP6OUT; /* Endpoint 6 */ ++ USB_EP_t EP6IN; /* Endpoint 6 */ ++ USB_EP_t EP7OUT; /* Endpoint 7 */ ++ USB_EP_t EP7IN; /* Endpoint 7 */ ++ USB_EP_t EP8OUT; /* Endpoint 8 */ ++ USB_EP_t EP8IN; /* Endpoint 8 */ ++ USB_EP_t EP9OUT; /* Endpoint 9 */ ++ USB_EP_t EP9IN; /* Endpoint 9 */ ++ USB_EP_t EP10OUT; /* Endpoint 10 */ ++ USB_EP_t EP10IN; /* Endpoint 10 */ ++ USB_EP_t EP11OUT; /* Endpoint 11 */ ++ USB_EP_t EP11IN; /* Endpoint 11 */ ++ USB_EP_t EP12OUT; /* Endpoint 12 */ ++ USB_EP_t EP12IN; /* Endpoint 12 */ ++ USB_EP_t EP13OUT; /* Endpoint 13 */ ++ USB_EP_t EP13IN; /* Endpoint 13 */ ++ USB_EP_t EP14OUT; /* Endpoint 14 */ ++ USB_EP_t EP14IN; /* Endpoint 14 */ ++ USB_EP_t EP15OUT; /* Endpoint 15 */ ++ USB_EP_t EP15IN; /* Endpoint 15 */ ++ register8_t reserved_0x100; ++ register8_t reserved_0x101; ++ register8_t reserved_0x102; ++ register8_t reserved_0x103; ++ register8_t reserved_0x104; ++ register8_t reserved_0x105; ++ register8_t reserved_0x106; ++ register8_t reserved_0x107; ++ register8_t reserved_0x108; ++ register8_t reserved_0x109; ++ register8_t reserved_0x10A; ++ register8_t reserved_0x10B; ++ register8_t reserved_0x10C; ++ register8_t reserved_0x10D; ++ register8_t reserved_0x10E; ++ register8_t reserved_0x10F; ++ register8_t FRAMENUML; /* Frame Number Low Byte */ ++ register8_t FRAMENUMH; /* Frame Number High Byte */ ++} USB_EP_TABLE_t; ++ ++/* Interrupt level */ ++typedef enum USB_INTLVL_enum ++{ ++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} USB_INTLVL_t; ++ ++/* USB Endpoint Type */ ++typedef enum USB_EP_TYPE_enum ++{ ++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ ++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ ++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ ++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ ++} USB_EP_TYPE_t; ++ ++/* USB Endpoint Buffersize */ ++typedef enum USB_EP_BUFSIZE_enum ++{ ++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ ++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ ++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ ++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ ++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ ++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ ++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ ++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ ++} USB_EP_BUFSIZE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - I/O Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* I/O Port Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Byte Mode */ ++typedef enum TC_BYTEM_enum ++{ ++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ ++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ ++} TC_BYTEM_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AWEX - Timer/Counter Advanced Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - Timer/Counter High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LCD - LCD Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* LCD Controller */ ++typedef struct LCD_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t INTCTRL; /* Interrupt Enable Register */ ++ register8_t INTFLAG; /* Interrupt Flag Register */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t CTRLF; /* Control Register F */ ++ register8_t CTRLG; /* Control Register G */ ++ register8_t CTRLH; /* Control Register H */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t DATA0; /* LCD Data Register 0 */ ++ register8_t DATA1; /* LCD Data Register 1 */ ++ register8_t DATA2; /* LCD Data Register 2 */ ++ register8_t DATA3; /* LCD Data Register 3 */ ++ register8_t DATA4; /* LCD Data Register 4 */ ++ register8_t DATA5; /* LCD Data Register 5 */ ++ register8_t DATA6; /* LCD Data Register 6 */ ++ register8_t DATA7; /* LCD Data Register 7 */ ++ register8_t DATA8; /* LCD Data Register 8 */ ++ register8_t DATA9; /* LCD Data Register 9 */ ++ register8_t DATA10; /* LCD Data Register 10 */ ++ register8_t DATA11; /* LCD Data Register 11 */ ++ register8_t DATA12; /* LCD Data Register 12 */ ++ register8_t DATA13; /* LCD Data Register 13 */ ++ register8_t DATA14; /* LCD Data Register 14 */ ++ register8_t DATA15; /* LCD Data Register 15 */ ++ register8_t DATA16; /* LCD Data Register 16 */ ++ register8_t DATA17; /* LCD Data Register 17 */ ++ register8_t DATA18; /* LCD Data Register 18 */ ++ register8_t DATA19; /* LCD Data Register 19 */ ++} LCD_t; ++ ++/* LCD Blink Rate */ ++typedef enum LCD_BLINKRATE_enum ++{ ++ LCD_BLINKRATE_4Hz_gc = (0x00<<0), /* 4Hz Blink Rate */ ++ LCD_BLINKRATE_2Hz_gc = (0x01<<0), /* 2Hz Blink Rate */ ++ LCD_BLINKRATE_1Hz_gc = (0x02<<0), /* 1Hz Blink Rate */ ++ LCD_BLINKRATE_0Hz5_gc = (0x03<<0), /* 0.5Hz Blink Rate */ ++} LCD_BLINKRATE_t; ++ ++/* LCD Clock Divide */ ++typedef enum LCD_CLKDIV_enum ++{ ++ LCD_CLKDIV_DivBy1_gc = (0x00<<4), /* frame rate of 256 Hz */ ++ LCD_CLKDIV_DivBy2_gc = (0x01<<4), /* frame rate of 128 Hz */ ++ LCD_CLKDIV_DivBy3_gc = (0x02<<4), /* frame rate of 83.5 Hz */ ++ LCD_CLKDIV_DivBy4_gc = (0x03<<4), /* frame rate of 64 Hz */ ++ LCD_CLKDIV_DivBy5_gc = (0x04<<4), /* frame rate of 51.2 Hz */ ++ LCD_CLKDIV_DivBy6_gc = (0x05<<4), /* frame rate of 42.7 Hz */ ++ LCD_CLKDIV_DivBy7_gc = (0x06<<4), /* frame rate of 36.6 Hz */ ++ LCD_CLKDIV_DivBy8_gc = (0x07<<4), /* frame rate of 32 Hz */ ++} LCD_CLKDIV_t; ++ ++/* Duty Select */ ++typedef enum LCD_DUTY_enum ++{ ++ LCD_DUTY_1_4_gc = (0x00<<0), /* Duty=1/4, Bias=1/3, COM0:3 */ ++ LCD_DUTY_Static_gc = (0x01<<0), /* Duty=Static, Bias=Static, COM0 */ ++ LCD_DUTY_1_2_gc = (0x02<<0), /* Duty=1/2, Bias=1/3, COM0:1 */ ++ LCD_DUTY_1_3_gc = (0x03<<0), /* Duty=1/3, Bias=1/3, COM0:2 */ ++} LCD_DUTY_t; ++ ++/* LCD Prescaler Select */ ++typedef enum LCD_PRESC_enum ++{ ++ LCD_PRESC_8_gc = (0x00<<7), /* clk_lcd/8 */ ++ LCD_PRESC_16_gc = (0x01<<7), /* clk_lcd/16 */ ++} LCD_PRESC_t; ++ ++/* Type of Digit */ ++typedef enum LCD_TDG_enum ++{ ++ LCD_TDG_7S_3C_gc = (0x00<<6), /* 7-segment with 3 COMs */ ++ LCD_TDG_7S_4C_gc = (0x01<<6), /* 7-segment with 4 COMs */ ++ LCD_TDG_14S_4C_gc = (0x02<<6), /* 14-segment with 4 COMs */ ++ LCD_TDG_16S_3C_gc = (0x03<<6), /* 16-segment with 3 COMs */ ++} LCD_TDG_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t FUSEBYTE0; /* JTAG User ID */ ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* Timer Oscillator pin location */ ++typedef enum TOSCSEL_enum ++{ ++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ ++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ ++} TOSCSEL_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* BOD operation */ ++typedef enum BODACT_enum ++{ ++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BODACT_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WDP_enum ++{ ++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ ++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ ++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ ++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ ++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ ++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ ++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ ++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ ++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ ++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ ++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ ++} WDP_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LOCKBIT - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ ++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t USBCAL0; /* USB Calibration Byte 0 */ ++ register8_t USBCAL1; /* USB Calibration Byte 1 */ ++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ ++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++ register8_t reserved_0x40; ++ register8_t reserved_0x41; ++ register8_t reserved_0x42; ++ register8_t reserved_0x43; ++ register8_t reserved_0x44; ++ register8_t reserved_0x45; ++ register8_t reserved_0x46; ++ register8_t reserved_0x47; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define AES (*(AES_t *) 0x00C0) /* AES Module */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCB (*(ADC_t *) 0x0240) /* Analog-to-Digital Converter */ ++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ ++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTG (*(PORT_t *) 0x06C0) /* I/O Ports */ ++#define PORTM (*(PORT_t *) 0x0760) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define LCD (*(LCD_t *) 0x0D00) /* LCD Controller */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE0 _SFR_MEM8(0x0000) ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) ++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) ++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) ++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_ADCBCAL0 _SFR_MEM8(0x0024) ++#define PRODSIGNATURES_ADCBCAL1 _SFR_MEM8(0x0025) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++#define CLK_USBCTRL _SFR_MEM8(0x0044) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLL - DFLL */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPB _SFR_MEM8(0x0072) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPE _SFR_MEM8(0x0075) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) ++ ++/* AES - AES Module */ ++#define AES_CTRL _SFR_MEM8(0x00C0) ++#define AES_STATUS _SFR_MEM8(0x00C1) ++#define AES_STATE _SFR_MEM8(0x00C2) ++#define AES_KEY _SFR_MEM8(0x00C3) ++#define AES_INTCTRL _SFR_MEM8(0x00C4) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* DMA - DMA Controller */ ++#define DMA_CTRL _SFR_MEM8(0x0100) ++#define DMA_INTFLAGS _SFR_MEM8(0x0103) ++#define DMA_STATUS _SFR_MEM8(0x0104) ++#define DMA_TEMP _SFR_MEM16(0x0106) ++#define DMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define DMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113) ++#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114) ++#define DMA_CH0_REPCNT _SFR_MEM8(0x0116) ++#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118) ++#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119) ++#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C) ++#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D) ++#define DMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define DMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123) ++#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124) ++#define DMA_CH1_REPCNT _SFR_MEM8(0x0126) ++#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128) ++#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129) ++#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C) ++#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCB_CTRLA _SFR_MEM8(0x0240) ++#define ADCB_CTRLB _SFR_MEM8(0x0241) ++#define ADCB_REFCTRL _SFR_MEM8(0x0242) ++#define ADCB_EVCTRL _SFR_MEM8(0x0243) ++#define ADCB_PRESCALER _SFR_MEM8(0x0244) ++#define ADCB_INTFLAGS _SFR_MEM8(0x0246) ++#define ADCB_TEMP _SFR_MEM8(0x0247) ++#define ADCB_SAMPCTRL _SFR_MEM8(0x0248) ++#define ADCB_CAL _SFR_MEM16(0x024C) ++#define ADCB_CH0RES _SFR_MEM16(0x0250) ++#define ADCB_CMP _SFR_MEM16(0x0258) ++#define ADCB_CH0_CTRL _SFR_MEM8(0x0260) ++#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261) ++#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262) ++#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263) ++#define ADCB_CH0_RES _SFR_MEM16(0x0264) ++#define ADCB_CH0_SCAN _SFR_MEM8(0x0266) ++ ++/* AC - Analog Comparator */ ++#define ACB_AC0CTRL _SFR_MEM8(0x0390) ++#define ACB_AC1CTRL _SFR_MEM8(0x0391) ++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) ++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) ++#define ACB_CTRLA _SFR_MEM8(0x0394) ++#define ACB_CTRLB _SFR_MEM8(0x0395) ++#define ACB_WINCTRL _SFR_MEM8(0x0396) ++#define ACB_STATUS _SFR_MEM8(0x0397) ++#define ACB_CURRCTRL _SFR_MEM8(0x0398) ++#define ACB_CURRCALIB _SFR_MEM8(0x0399) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* USB - Universal Serial Bus */ ++#define USB_CTRLA _SFR_MEM8(0x04C0) ++#define USB_CTRLB _SFR_MEM8(0x04C1) ++#define USB_STATUS _SFR_MEM8(0x04C2) ++#define USB_ADDR _SFR_MEM8(0x04C3) ++#define USB_FIFOWP _SFR_MEM8(0x04C4) ++#define USB_FIFORP _SFR_MEM8(0x04C5) ++#define USB_EPPTR _SFR_MEM16(0x04C6) ++#define USB_INTCTRLA _SFR_MEM8(0x04C8) ++#define USB_INTCTRLB _SFR_MEM8(0x04C9) ++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) ++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) ++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) ++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) ++#define USB_CAL0 _SFR_MEM8(0x04FA) ++#define USB_CAL1 _SFR_MEM8(0x04FB) ++ ++/* PORT - I/O Ports */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_REMAP _SFR_MEM8(0x062E) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTG_DIR _SFR_MEM8(0x06C0) ++#define PORTG_DIRSET _SFR_MEM8(0x06C1) ++#define PORTG_DIRCLR _SFR_MEM8(0x06C2) ++#define PORTG_DIRTGL _SFR_MEM8(0x06C3) ++#define PORTG_OUT _SFR_MEM8(0x06C4) ++#define PORTG_OUTSET _SFR_MEM8(0x06C5) ++#define PORTG_OUTCLR _SFR_MEM8(0x06C6) ++#define PORTG_OUTTGL _SFR_MEM8(0x06C7) ++#define PORTG_IN _SFR_MEM8(0x06C8) ++#define PORTG_INTCTRL _SFR_MEM8(0x06C9) ++#define PORTG_INT0MASK _SFR_MEM8(0x06CA) ++#define PORTG_INT1MASK _SFR_MEM8(0x06CB) ++#define PORTG_INTFLAGS _SFR_MEM8(0x06CC) ++#define PORTG_REMAP _SFR_MEM8(0x06CE) ++#define PORTG_PIN0CTRL _SFR_MEM8(0x06D0) ++#define PORTG_PIN1CTRL _SFR_MEM8(0x06D1) ++#define PORTG_PIN2CTRL _SFR_MEM8(0x06D2) ++#define PORTG_PIN3CTRL _SFR_MEM8(0x06D3) ++#define PORTG_PIN4CTRL _SFR_MEM8(0x06D4) ++#define PORTG_PIN5CTRL _SFR_MEM8(0x06D5) ++#define PORTG_PIN6CTRL _SFR_MEM8(0x06D6) ++#define PORTG_PIN7CTRL _SFR_MEM8(0x06D7) ++ ++/* PORT - I/O Ports */ ++#define PORTM_DIR _SFR_MEM8(0x0760) ++#define PORTM_DIRSET _SFR_MEM8(0x0761) ++#define PORTM_DIRCLR _SFR_MEM8(0x0762) ++#define PORTM_DIRTGL _SFR_MEM8(0x0763) ++#define PORTM_OUT _SFR_MEM8(0x0764) ++#define PORTM_OUTSET _SFR_MEM8(0x0765) ++#define PORTM_OUTCLR _SFR_MEM8(0x0766) ++#define PORTM_OUTTGL _SFR_MEM8(0x0767) ++#define PORTM_IN _SFR_MEM8(0x0768) ++#define PORTM_INTCTRL _SFR_MEM8(0x0769) ++#define PORTM_INT0MASK _SFR_MEM8(0x076A) ++#define PORTM_INT1MASK _SFR_MEM8(0x076B) ++#define PORTM_INTFLAGS _SFR_MEM8(0x076C) ++#define PORTM_REMAP _SFR_MEM8(0x076E) ++#define PORTM_PIN0CTRL _SFR_MEM8(0x0770) ++#define PORTM_PIN1CTRL _SFR_MEM8(0x0771) ++#define PORTM_PIN2CTRL _SFR_MEM8(0x0772) ++#define PORTM_PIN3CTRL _SFR_MEM8(0x0773) ++#define PORTM_PIN4CTRL _SFR_MEM8(0x0774) ++#define PORTM_PIN5CTRL _SFR_MEM8(0x0775) ++#define PORTM_PIN6CTRL _SFR_MEM8(0x0776) ++#define PORTM_PIN7CTRL _SFR_MEM8(0x0777) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_STATUSSET _SFR_MEM8(0x0885) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* LCD - LCD Controller */ ++#define LCD_CTRLA _SFR_MEM8(0x0D00) ++#define LCD_CTRLB _SFR_MEM8(0x0D01) ++#define LCD_CTRLC _SFR_MEM8(0x0D02) ++#define LCD_INTCTRL _SFR_MEM8(0x0D03) ++#define LCD_INTFLAG _SFR_MEM8(0x0D04) ++#define LCD_CTRLD _SFR_MEM8(0x0D05) ++#define LCD_CTRLE _SFR_MEM8(0x0D06) ++#define LCD_CTRLF _SFR_MEM8(0x0D07) ++#define LCD_CTRLG _SFR_MEM8(0x0D08) ++#define LCD_CTRLH _SFR_MEM8(0x0D09) ++#define LCD_DATA0 _SFR_MEM8(0x0D10) ++#define LCD_DATA1 _SFR_MEM8(0x0D11) ++#define LCD_DATA2 _SFR_MEM8(0x0D12) ++#define LCD_DATA3 _SFR_MEM8(0x0D13) ++#define LCD_DATA4 _SFR_MEM8(0x0D14) ++#define LCD_DATA5 _SFR_MEM8(0x0D15) ++#define LCD_DATA6 _SFR_MEM8(0x0D16) ++#define LCD_DATA7 _SFR_MEM8(0x0D17) ++#define LCD_DATA8 _SFR_MEM8(0x0D18) ++#define LCD_DATA9 _SFR_MEM8(0x0D19) ++#define LCD_DATA10 _SFR_MEM8(0x0D1A) ++#define LCD_DATA11 _SFR_MEM8(0x0D1B) ++#define LCD_DATA12 _SFR_MEM8(0x0D1C) ++#define LCD_DATA13 _SFR_MEM8(0x0D1D) ++#define LCD_DATA14 _SFR_MEM8(0x0D1E) ++#define LCD_DATA15 _SFR_MEM8(0x0D1F) ++#define LCD_DATA16 _SFR_MEM8(0x0D20) ++#define LCD_DATA17 _SFR_MEM8(0x0D21) ++#define LCD_DATA18 _SFR_MEM8(0x0D22) ++#define LCD_DATA19 _SFR_MEM8(0x0D23) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* CLK.USBCTRL bit masks and bit positions */ ++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ ++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ ++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ ++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ ++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ ++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ ++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ ++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ ++ ++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ ++#define CLK_USBSRC_gp 1 /* Clock Source group position. */ ++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ ++ ++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ ++#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* PR - Power Reduction */ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_LCD_bm 0x80 /* LCD Module bit mask. */ ++#define PR_LCD_bp 7 /* LCD Module bit position. */ ++ ++#define PR_USB_bm 0x40 /* USB bit mask. */ ++#define PR_USB_bp 6 /* USB bit position. */ ++ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPB bit masks and bit positions */ ++/* PR_ADC Predefined. */ ++/* PR_ADC Predefined. */ ++ ++/* PR_AC Predefined. */ ++/* PR_AC Predefined. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYB_gm 0x0C /* Analog startup delay Port B group mask. */ ++#define MCU_STARTUPDLYB_gp 2 /* Analog startup delay Port B group position. */ ++#define MCU_STARTUPDLYB0_bm (1<<2) /* Analog startup delay Port B bit 0 mask. */ ++#define MCU_STARTUPDLYB0_bp 2 /* Analog startup delay Port B bit 0 position. */ ++#define MCU_STARTUPDLYB1_bm (1<<3) /* Analog startup delay Port B bit 1 mask. */ ++#define MCU_STARTUPDLYB1_bp 3 /* Analog startup delay Port B bit 1 position. */ ++ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ ++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ ++ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ ++ ++/* PORTCFG.EVOUTSEL bit masks and bit positions */ ++#define PORTCFG_EVOUTSEL_bm 0x04 /* Event Output Select bit mask. */ ++#define PORTCFG_EVOUTSEL_bp 2 /* Event Output Select bit position. */ ++ ++/* AES - AES Module */ ++/* AES.CTRL bit masks and bit positions */ ++#define AES_START_bm 0x80 /* Start/Run bit mask. */ ++#define AES_START_bp 7 /* Start/Run bit position. */ ++ ++#define AES_AUTO_bm 0x40 /* Auto Start Trigger bit mask. */ ++#define AES_AUTO_bp 6 /* Auto Start Trigger bit position. */ ++ ++#define AES_RESET_bm 0x20 /* AES Software Reset bit mask. */ ++#define AES_RESET_bp 5 /* AES Software Reset bit position. */ ++ ++#define AES_DECRYPT_bm 0x10 /* Decryption / Direction bit mask. */ ++#define AES_DECRYPT_bp 4 /* Decryption / Direction bit position. */ ++ ++#define AES_XOR_bm 0x04 /* State XOR Load Enable bit mask. */ ++#define AES_XOR_bp 2 /* State XOR Load Enable bit position. */ ++ ++/* AES.STATUS bit masks and bit positions */ ++#define AES_ERROR_bm 0x80 /* AES Error bit mask. */ ++#define AES_ERROR_bp 7 /* AES Error bit position. */ ++ ++#define AES_SRIF_bm 0x01 /* State Ready Interrupt Flag bit mask. */ ++#define AES_SRIF_bp 0 /* State Ready Interrupt Flag bit position. */ ++ ++/* AES.INTCTRL bit masks and bit positions */ ++#define AES_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define AES_INTLVL_gp 0 /* Interrupt level group position. */ ++#define AES_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define AES_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define AES_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define AES_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* DMA - DMA Controller */ ++/* DMA_CH.CTRLA bit masks and bit positions */ ++#define DMA_CH_CHEN_bm 0x80 /* Channel Enable bit mask. */ ++#define DMA_CH_CHEN_bp 7 /* Channel Enable bit position. */ ++ ++#define DMA_CH_CHRST_bm 0x40 /* Channel Software Reset bit mask. */ ++#define DMA_CH_CHRST_bp 6 /* Channel Software Reset bit position. */ ++ ++#define DMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define DMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define DMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define DMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define DMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define DMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define DMA_CH_BURSTLEN_gm 0x03 /* Channel Transfer Mode group mask. */ ++#define DMA_CH_BURSTLEN_gp 0 /* Channel Transfer Mode group position. */ ++#define DMA_CH_BURSTLEN0_bm (1<<0) /* Channel Transfer Mode bit 0 mask. */ ++#define DMA_CH_BURSTLEN0_bp 0 /* Channel Transfer Mode bit 0 position. */ ++#define DMA_CH_BURSTLEN1_bm (1<<1) /* Channel Transfer Mode bit 1 mask. */ ++#define DMA_CH_BURSTLEN1_bp 1 /* Channel Transfer Mode bit 1 position. */ ++ ++/* DMA_CH.CTRLB bit masks and bit positions */ ++#define DMA_CH_CHBUSY_bm 0x80 /* Block Transfer Busy bit mask. */ ++#define DMA_CH_CHBUSY_bp 7 /* Block Transfer Busy bit position. */ ++ ++#define DMA_CH_CHPEND_bm 0x40 /* Block Transfer Pending bit mask. */ ++#define DMA_CH_CHPEND_bp 6 /* Block Transfer Pending bit position. */ ++ ++#define DMA_CH_ERRIF_bm 0x20 /* Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH_ERRIF_bp 5 /* Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH_TRNIF_bm 0x10 /* Transaction Complete Interrup Flag bit mask. */ ++#define DMA_CH_TRNIF_bp 4 /* Transaction Complete Interrup Flag bit position. */ ++ ++#define DMA_CH_ERRINTLVL_gm 0x0C /* Transfer Error Interrupt Level group mask. */ ++#define DMA_CH_ERRINTLVL_gp 2 /* Transfer Error Interrupt Level group position. */ ++#define DMA_CH_ERRINTLVL0_bm (1<<2) /* Transfer Error Interrupt Level bit 0 mask. */ ++#define DMA_CH_ERRINTLVL0_bp 2 /* Transfer Error Interrupt Level bit 0 position. */ ++#define DMA_CH_ERRINTLVL1_bm (1<<3) /* Transfer Error Interrupt Level bit 1 mask. */ ++#define DMA_CH_ERRINTLVL1_bp 3 /* Transfer Error Interrupt Level bit 1 position. */ ++ ++#define DMA_CH_TRNINTLVL_gm 0x03 /* Transaction Complete Interrupt Level group mask. */ ++#define DMA_CH_TRNINTLVL_gp 0 /* Transaction Complete Interrupt Level group position. */ ++#define DMA_CH_TRNINTLVL0_bm (1<<0) /* Transaction Complete Interrupt Level bit 0 mask. */ ++#define DMA_CH_TRNINTLVL0_bp 0 /* Transaction Complete Interrupt Level bit 0 position. */ ++#define DMA_CH_TRNINTLVL1_bm (1<<1) /* Transaction Complete Interrupt Level bit 1 mask. */ ++#define DMA_CH_TRNINTLVL1_bp 1 /* Transaction Complete Interrupt Level bit 1 position. */ ++ ++/* DMA_CH.ADDRCTRL bit masks and bit positions */ ++#define DMA_CH_SRCRELOAD_gm 0xC0 /* Channel Source Address Reload group mask. */ ++#define DMA_CH_SRCRELOAD_gp 6 /* Channel Source Address Reload group position. */ ++#define DMA_CH_SRCRELOAD0_bm (1<<6) /* Channel Source Address Reload bit 0 mask. */ ++#define DMA_CH_SRCRELOAD0_bp 6 /* Channel Source Address Reload bit 0 position. */ ++#define DMA_CH_SRCRELOAD1_bm (1<<7) /* Channel Source Address Reload bit 1 mask. */ ++#define DMA_CH_SRCRELOAD1_bp 7 /* Channel Source Address Reload bit 1 position. */ ++ ++#define DMA_CH_SRCDIR_gm 0x30 /* Channel Source Address Mode group mask. */ ++#define DMA_CH_SRCDIR_gp 4 /* Channel Source Address Mode group position. */ ++#define DMA_CH_SRCDIR0_bm (1<<4) /* Channel Source Address Mode bit 0 mask. */ ++#define DMA_CH_SRCDIR0_bp 4 /* Channel Source Address Mode bit 0 position. */ ++#define DMA_CH_SRCDIR1_bm (1<<5) /* Channel Source Address Mode bit 1 mask. */ ++#define DMA_CH_SRCDIR1_bp 5 /* Channel Source Address Mode bit 1 position. */ ++ ++#define DMA_CH_DESTRELOAD_gm 0x0C /* Channel Destination Address Reload group mask. */ ++#define DMA_CH_DESTRELOAD_gp 2 /* Channel Destination Address Reload group position. */ ++#define DMA_CH_DESTRELOAD0_bm (1<<2) /* Channel Destination Address Reload bit 0 mask. */ ++#define DMA_CH_DESTRELOAD0_bp 2 /* Channel Destination Address Reload bit 0 position. */ ++#define DMA_CH_DESTRELOAD1_bm (1<<3) /* Channel Destination Address Reload bit 1 mask. */ ++#define DMA_CH_DESTRELOAD1_bp 3 /* Channel Destination Address Reload bit 1 position. */ ++ ++#define DMA_CH_DESTDIR_gm 0x03 /* Channel Destination Address Mode group mask. */ ++#define DMA_CH_DESTDIR_gp 0 /* Channel Destination Address Mode group position. */ ++#define DMA_CH_DESTDIR0_bm (1<<0) /* Channel Destination Address Mode bit 0 mask. */ ++#define DMA_CH_DESTDIR0_bp 0 /* Channel Destination Address Mode bit 0 position. */ ++#define DMA_CH_DESTDIR1_bm (1<<1) /* Channel Destination Address Mode bit 1 mask. */ ++#define DMA_CH_DESTDIR1_bp 1 /* Channel Destination Address Mode bit 1 position. */ ++ ++/* DMA_CH.TRIGSRC bit masks and bit positions */ ++#define DMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define DMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define DMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define DMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define DMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define DMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define DMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define DMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define DMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define DMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define DMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define DMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define DMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define DMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define DMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define DMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define DMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define DMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++/* DMA.CTRL bit masks and bit positions */ ++#define DMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define DMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define DMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define DMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define DMA_DBUFMODE_bm 0x04 /* Double Buffering Mode bit mask. */ ++#define DMA_DBUFMODE_bp 2 /* Double Buffering Mode bit position. */ ++ ++#define DMA_PRIMODE_bm 0x01 /* Channel Priority Mode bit mask. */ ++#define DMA_PRIMODE_bp 0 /* Channel Priority Mode bit position. */ ++ ++/* DMA.INTFLAGS bit masks and bit positions */ ++#define DMA_CH1ERRIF_bm 0x20 /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH1ERRIF_bp 5 /* Channel 1 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH0ERRIF_bm 0x10 /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */ ++#define DMA_CH0ERRIF_bp 4 /* Channel 0 Block Transfer Error Interrupt Flag bit position. */ ++ ++#define DMA_CH1TRNIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH1TRNIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define DMA_CH0TRNIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define DMA_CH0TRNIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++/* DMA.STATUS bit masks and bit positions */ ++#define DMA_CH1BUSY_bm 0x20 /* Channel 1 Block Transfer Busy bit mask. */ ++#define DMA_CH1BUSY_bp 5 /* Channel 1 Block Transfer Busy bit position. */ ++ ++#define DMA_CH0BUSY_bm 0x10 /* Channel 0 Block Transfer Busy bit mask. */ ++#define DMA_CH0BUSY_bp 4 /* Channel 0 Block Transfer Busy bit position. */ ++ ++#define DMA_CH1PEND_bm 0x02 /* Channel 1 Block Transfer Pending bit mask. */ ++#define DMA_CH1PEND_bp 1 /* Channel 1 Block Transfer Pending bit position. */ ++ ++#define DMA_CH0PEND_bm 0x01 /* Channel 0 Block Transfer Pending bit mask. */ ++#define DMA_CH0PEND_bp 0 /* Channel 0 Block Transfer Pending bit position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ ++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ ++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ ++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ ++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ ++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ ++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ ++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ ++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ ++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ ++ ++#define ADC_CH_COUNT_gm 0x0F /* Number of Channels included in scan group mask. */ ++#define ADC_CH_COUNT_gp 0 /* Number of Channels included in scan group position. */ ++#define ADC_CH_COUNT0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ ++#define ADC_CH_COUNT0_bp 0 /* Number of Channels included in scan bit 0 position. */ ++#define ADC_CH_COUNT1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ ++#define ADC_CH_COUNT1_bp 1 /* Number of Channels included in scan bit 1 position. */ ++#define ADC_CH_COUNT2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ ++#define ADC_CH_COUNT2_bp 2 /* Number of Channels included in scan bit 2 position. */ ++#define ADC_CH_COUNT3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ ++#define ADC_CH_COUNT3_bp 3 /* Number of Channels included in scan bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ ++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CURRLIMIT_gm 0x60 /* Current limit group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current limit group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current limit bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current limit bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current limit bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current limit bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* ADC.SAMPCTRL bit masks and bit positions */ ++#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ ++#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ ++#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ ++#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ ++#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ ++#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ ++#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ ++#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ ++#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ ++#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ ++#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ ++#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ ++#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ ++#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* AC.CURRCTRL bit masks and bit positions */ ++#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ ++#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ ++ ++#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ ++#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ ++ ++#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ ++#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ ++ ++#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ ++#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ ++ ++/* AC.CURRCALIB bit masks and bit positions */ ++#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ ++#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ ++#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ ++#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ ++#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ ++#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ ++#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ ++#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ ++#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ ++#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ ++ ++/* RTC - Real-Time Counter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* USB - USB */ ++/* USB_EP.STATUS bit masks and bit positions */ ++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ ++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ ++ ++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ ++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ ++ ++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ ++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ ++ ++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ ++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ ++ ++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ ++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ ++ ++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ ++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ ++ ++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ ++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ ++ ++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ ++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ ++ ++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ ++ ++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ ++ ++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ ++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ ++ ++/* USB_EP.CTRL bit masks and bit positions */ ++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ ++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ ++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ ++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ ++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ ++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ ++ ++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ ++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ ++ ++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ ++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ ++ ++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ ++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ ++ ++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ ++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ ++ ++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ ++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ ++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ ++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ ++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ ++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ ++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ ++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ ++ ++/* USB_EP.CNT bit masks and bit positions */ ++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ ++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ ++ ++/* USB.CTRLA bit masks and bit positions */ ++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ ++#define USB_ENABLE_bp 7 /* USB Enable bit position. */ ++ ++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ ++#define USB_SPEED_bp 6 /* Speed Select bit position. */ ++ ++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ ++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ ++ ++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ ++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ ++ ++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ ++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ ++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ ++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ ++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ ++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ ++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ ++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ ++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ ++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ ++ ++/* USB.CTRLB bit masks and bit positions */ ++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ ++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ ++ ++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ ++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ ++ ++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ ++#define USB_GNACK_bp 1 /* Global NACK bit position. */ ++ ++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ ++#define USB_ATTACH_bp 0 /* Attach bit position. */ ++ ++/* USB.STATUS bit masks and bit positions */ ++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ ++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ ++ ++#define USB_RESUME_bm 0x04 /* Resume bit mask. */ ++#define USB_RESUME_bp 2 /* Resume bit position. */ ++ ++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ ++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ ++ ++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ ++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ ++ ++/* USB.ADDR bit masks and bit positions */ ++#define USB_ADDR_gm 0x7F /* Device Address group mask. */ ++#define USB_ADDR_gp 0 /* Device Address group position. */ ++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ ++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ ++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ ++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ ++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ ++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ ++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ ++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ ++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ ++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ ++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ ++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ ++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ ++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ ++ ++/* USB.FIFOWP bit masks and bit positions */ ++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ ++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ ++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ ++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ ++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ ++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ ++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ ++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ ++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ ++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ ++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ ++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ ++ ++/* USB.FIFORP bit masks and bit positions */ ++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ ++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ ++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ ++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ ++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ ++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ ++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ ++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ ++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ ++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ ++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ ++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ ++ ++/* USB.INTCTRLA bit masks and bit positions */ ++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ ++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ ++ ++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ ++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ ++ ++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ ++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ ++ ++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ ++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ ++ ++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* USB.INTCTRLB bit masks and bit positions */ ++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ ++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ ++ ++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ ++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ ++ ++/* USB.INTFLAGSACLR bit masks and bit positions */ ++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ ++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ ++ ++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ ++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ ++ ++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ ++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ ++ ++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ ++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ ++ ++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ ++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ ++ ++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ ++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ ++ ++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ ++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ ++ ++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ ++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSASET bit masks and bit positions */ ++/* USB_SOFIF Predefined. */ ++/* USB_SOFIF Predefined. */ ++ ++/* USB_SUSPENDIF Predefined. */ ++/* USB_SUSPENDIF Predefined. */ ++ ++/* USB_RESUMEIF Predefined. */ ++/* USB_RESUMEIF Predefined. */ ++ ++/* USB_RSTIF Predefined. */ ++/* USB_RSTIF Predefined. */ ++ ++/* USB_CRCIF Predefined. */ ++/* USB_CRCIF Predefined. */ ++ ++/* USB_UNFIF Predefined. */ ++/* USB_UNFIF Predefined. */ ++ ++/* USB_OVFIF Predefined. */ ++/* USB_OVFIF Predefined. */ ++ ++/* USB_STALLIF Predefined. */ ++/* USB_STALLIF Predefined. */ ++ ++/* USB.INTFLAGSBCLR bit masks and bit positions */ ++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ ++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ ++ ++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ ++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSBSET bit masks and bit positions */ ++/* USB_TRNIF Predefined. */ ++/* USB_TRNIF Predefined. */ ++ ++/* USB_SETUPIF Predefined. */ ++/* USB_SETUPIF Predefined. */ ++ ++/* PORT - I/O Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_SPI_bm 0x20 /* SPI bit mask. */ ++#define PORT_SPI_bp 5 /* SPI bit position. */ ++ ++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ ++#define PORT_USART0_bp 4 /* USART0 bit position. */ ++ ++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ ++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ ++ ++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ ++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ ++ ++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ ++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ ++ ++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ ++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD Predefined. */ ++/* TC0_CMD Predefined. */ ++ ++/* TC0_LUPD Predefined. */ ++/* TC0_LUPD Predefined. */ ++ ++/* TC0_DIR Predefined. */ ++/* TC0_DIR Predefined. */ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV Predefined. */ ++/* TC0_CCDBV Predefined. */ ++ ++/* TC0_CCCBV Predefined. */ ++/* TC0_CCCBV Predefined. */ ++ ++/* TC0_CCBBV Predefined. */ ++/* TC0_CCBBV Predefined. */ ++ ++/* TC0_CCABV Predefined. */ ++/* TC0_CCABV Predefined. */ ++ ++/* TC0_PERBV Predefined. */ ++/* TC0_PERBV Predefined. */ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD Predefined. */ ++/* TC1_CMD Predefined. */ ++ ++/* TC1_LUPD Predefined. */ ++/* TC1_LUPD Predefined. */ ++ ++/* TC1_DIR Predefined. */ ++/* TC1_DIR Predefined. */ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV Predefined. */ ++/* TC1_CCBBV Predefined. */ ++ ++/* TC1_CCABV Predefined. */ ++/* TC1_CCABV Predefined. */ ++ ++/* TC1_PERBV Predefined. */ ++/* TC1_PERBV Predefined. */ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* AWEX - Timer/Counter Advanced Waveform Extension */ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++/* AWEX.STATUSSET bit masks and bit positions */ ++/* AWEX_FDF Predefined. */ ++/* AWEX_FDF Predefined. */ ++ ++/* AWEX_DTHSBUFV Predefined. */ ++/* AWEX_DTHSBUFV Predefined. */ ++ ++/* AWEX_DTLSBUFV Predefined. */ ++/* AWEX_DTLSBUFV Predefined. */ ++ ++/* HIRES - Timer/Counter High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* LCD - LCD Controller */ ++/* LCD.CTRLA bit masks and bit positions */ ++#define LCD_ENABLE_bm 0x80 /* LCD Enable bit mask. */ ++#define LCD_ENABLE_bp 7 /* LCD Enable bit position. */ ++ ++#define LCD_XBIAS_bm 0x40 /* External Register Bias Generation bit mask. */ ++#define LCD_XBIAS_bp 6 /* External Register Bias Generation bit position. */ ++ ++#define LCD_DATCLK_bm 0x20 /* Data Register Lock bit mask. */ ++#define LCD_DATCLK_bp 5 /* Data Register Lock bit position. */ ++ ++#define LCD_COMSWP_bm 0x10 /* Common Bus Swap bit mask. */ ++#define LCD_COMSWP_bp 4 /* Common Bus Swap bit position. */ ++ ++#define LCD_SEGSWP_bm 0x08 /* Segment Bus Swap bit mask. */ ++#define LCD_SEGSWP_bp 3 /* Segment Bus Swap bit position. */ ++ ++#define LCD_CLRDT_bm 0x04 /* Clear Data Register bit mask. */ ++#define LCD_CLRDT_bp 2 /* Clear Data Register bit position. */ ++ ++#define LCD_SEGON_bm 0x02 /* Segments On bit mask. */ ++#define LCD_SEGON_bp 1 /* Segments On bit position. */ ++ ++#define LCD_BLANK_bm 0x01 /* Blanking Display Mode bit mask. */ ++#define LCD_BLANK_bp 0 /* Blanking Display Mode bit position. */ ++ ++/* LCD.CTRLB bit masks and bit positions */ ++#define LCD_PRESC_bm 0x80 /* LCD Prescaler Select bit mask. */ ++#define LCD_PRESC_bp 7 /* LCD Prescaler Select bit position. */ ++ ++#define LCD_CLKDIV_gm 0x70 /* LCD Clock Divide group mask. */ ++#define LCD_CLKDIV_gp 4 /* LCD Clock Divide group position. */ ++#define LCD_CLKDIV0_bm (1<<4) /* LCD Clock Divide bit 0 mask. */ ++#define LCD_CLKDIV0_bp 4 /* LCD Clock Divide bit 0 position. */ ++#define LCD_CLKDIV1_bm (1<<5) /* LCD Clock Divide bit 1 mask. */ ++#define LCD_CLKDIV1_bp 5 /* LCD Clock Divide bit 1 position. */ ++#define LCD_CLKDIV2_bm (1<<6) /* LCD Clock Divide bit 2 mask. */ ++#define LCD_CLKDIV2_bp 6 /* LCD Clock Divide bit 2 position. */ ++ ++#define LCD_LPWAV_bm 0x08 /* Low Power Waveform bit mask. */ ++#define LCD_LPWAV_bp 3 /* Low Power Waveform bit position. */ ++ ++#define LCD_DUTY_gm 0x03 /* Duty Select group mask. */ ++#define LCD_DUTY_gp 0 /* Duty Select group position. */ ++#define LCD_DUTY0_bm (1<<0) /* Duty Select bit 0 mask. */ ++#define LCD_DUTY0_bp 0 /* Duty Select bit 0 position. */ ++#define LCD_DUTY1_bm (1<<1) /* Duty Select bit 1 mask. */ ++#define LCD_DUTY1_bp 1 /* Duty Select bit 1 position. */ ++ ++/* LCD.CTRLC bit masks and bit positions */ ++#define LCD_PMSK_gm 0x3F /* LCD Port Mask group mask. */ ++#define LCD_PMSK_gp 0 /* LCD Port Mask group position. */ ++#define LCD_PMSK0_bm (1<<0) /* LCD Port Mask bit 0 mask. */ ++#define LCD_PMSK0_bp 0 /* LCD Port Mask bit 0 position. */ ++#define LCD_PMSK1_bm (1<<1) /* LCD Port Mask bit 1 mask. */ ++#define LCD_PMSK1_bp 1 /* LCD Port Mask bit 1 position. */ ++#define LCD_PMSK2_bm (1<<2) /* LCD Port Mask bit 2 mask. */ ++#define LCD_PMSK2_bp 2 /* LCD Port Mask bit 2 position. */ ++#define LCD_PMSK3_bm (1<<3) /* LCD Port Mask bit 3 mask. */ ++#define LCD_PMSK3_bp 3 /* LCD Port Mask bit 3 position. */ ++#define LCD_PMSK4_bm (1<<4) /* LCD Port Mask bit 4 mask. */ ++#define LCD_PMSK4_bp 4 /* LCD Port Mask bit 4 position. */ ++#define LCD_PMSK5_bm (1<<5) /* LCD Port Mask bit 5 mask. */ ++#define LCD_PMSK5_bp 5 /* LCD Port Mask bit 5 position. */ ++ ++/* LCD.INTCTRL bit masks and bit positions */ ++#define LCD_XIME_gm 0xF8 /* eXtended Interrupt Mode Enable group mask. */ ++#define LCD_XIME_gp 3 /* eXtended Interrupt Mode Enable group position. */ ++#define LCD_XIME0_bm (1<<3) /* eXtended Interrupt Mode Enable bit 0 mask. */ ++#define LCD_XIME0_bp 3 /* eXtended Interrupt Mode Enable bit 0 position. */ ++#define LCD_XIME1_bm (1<<4) /* eXtended Interrupt Mode Enable bit 1 mask. */ ++#define LCD_XIME1_bp 4 /* eXtended Interrupt Mode Enable bit 1 position. */ ++#define LCD_XIME2_bm (1<<5) /* eXtended Interrupt Mode Enable bit 2 mask. */ ++#define LCD_XIME2_bp 5 /* eXtended Interrupt Mode Enable bit 2 position. */ ++#define LCD_XIME3_bm (1<<6) /* eXtended Interrupt Mode Enable bit 3 mask. */ ++#define LCD_XIME3_bp 6 /* eXtended Interrupt Mode Enable bit 3 position. */ ++#define LCD_XIME4_bm (1<<7) /* eXtended Interrupt Mode Enable bit 4 mask. */ ++#define LCD_XIME4_bp 7 /* eXtended Interrupt Mode Enable bit 4 position. */ ++ ++#define LCD_FCINTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define LCD_FCINTLVL_gp 0 /* Interrupt Level group position. */ ++#define LCD_FCINTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define LCD_FCINTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define LCD_FCINTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define LCD_FCINTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* LCD.INTFLAG bit masks and bit positions */ ++#define LCD_FCIF_bm 0x01 /* LCD Frame Completed Interrupt Flag bit mask. */ ++#define LCD_FCIF_bp 0 /* LCD Frame Completed Interrupt Flag bit position. */ ++ ++/* LCD.CTRLD bit masks and bit positions */ ++#define LCD_BLINKEN_bm 0x08 /* Blink Enable bit mask. */ ++#define LCD_BLINKEN_bp 3 /* Blink Enable bit position. */ ++ ++#define LCD_BLINKRATE_gm 0x03 /* LCD Blink Rate group mask. */ ++#define LCD_BLINKRATE_gp 0 /* LCD Blink Rate group position. */ ++#define LCD_BLINKRATE0_bm (1<<0) /* LCD Blink Rate bit 0 mask. */ ++#define LCD_BLINKRATE0_bp 0 /* LCD Blink Rate bit 0 position. */ ++#define LCD_BLINKRATE1_bm (1<<1) /* LCD Blink Rate bit 1 mask. */ ++#define LCD_BLINKRATE1_bp 1 /* LCD Blink Rate bit 1 position. */ ++ ++/* LCD.CTRLE bit masks and bit positions */ ++#define LCD_BPS1_gm 0xF0 /* Blink Pixel Selection 1 group mask. */ ++#define LCD_BPS1_gp 4 /* Blink Pixel Selection 1 group position. */ ++#define LCD_BPS10_bm (1<<4) /* Blink Pixel Selection 1 bit 0 mask. */ ++#define LCD_BPS10_bp 4 /* Blink Pixel Selection 1 bit 0 position. */ ++#define LCD_BPS11_bm (1<<5) /* Blink Pixel Selection 1 bit 1 mask. */ ++#define LCD_BPS11_bp 5 /* Blink Pixel Selection 1 bit 1 position. */ ++#define LCD_BPS12_bm (1<<6) /* Blink Pixel Selection 1 bit 2 mask. */ ++#define LCD_BPS12_bp 6 /* Blink Pixel Selection 1 bit 2 position. */ ++#define LCD_BPS13_bm (1<<7) /* Blink Pixel Selection 1 bit 3 mask. */ ++#define LCD_BPS13_bp 7 /* Blink Pixel Selection 1 bit 3 position. */ ++ ++#define LCD_BPS0_gm 0x0F /* Blink Pixel Selection 0 group mask. */ ++#define LCD_BPS0_gp 0 /* Blink Pixel Selection 0 group position. */ ++#define LCD_BPS00_bm (1<<0) /* Blink Pixel Selection 0 bit 0 mask. */ ++#define LCD_BPS00_bp 0 /* Blink Pixel Selection 0 bit 0 position. */ ++#define LCD_BPS01_bm (1<<1) /* Blink Pixel Selection 0 bit 1 mask. */ ++#define LCD_BPS01_bp 1 /* Blink Pixel Selection 0 bit 1 position. */ ++#define LCD_BPS02_bm (1<<2) /* Blink Pixel Selection 0 bit 2 mask. */ ++#define LCD_BPS02_bp 2 /* Blink Pixel Selection 0 bit 2 position. */ ++#define LCD_BPS03_bm (1<<3) /* Blink Pixel Selection 0 bit 3 mask. */ ++#define LCD_BPS03_bp 3 /* Blink Pixel Selection 0 bit 3 position. */ ++ ++/* LCD.CTRLF bit masks and bit positions */ ++#define LCD_FCONT_gm 0x3F /* Fine Contrast group mask. */ ++#define LCD_FCONT_gp 0 /* Fine Contrast group position. */ ++#define LCD_FCONT0_bm (1<<0) /* Fine Contrast bit 0 mask. */ ++#define LCD_FCONT0_bp 0 /* Fine Contrast bit 0 position. */ ++#define LCD_FCONT1_bm (1<<1) /* Fine Contrast bit 1 mask. */ ++#define LCD_FCONT1_bp 1 /* Fine Contrast bit 1 position. */ ++#define LCD_FCONT2_bm (1<<2) /* Fine Contrast bit 2 mask. */ ++#define LCD_FCONT2_bp 2 /* Fine Contrast bit 2 position. */ ++#define LCD_FCONT3_bm (1<<3) /* Fine Contrast bit 3 mask. */ ++#define LCD_FCONT3_bp 3 /* Fine Contrast bit 3 position. */ ++#define LCD_FCONT4_bm (1<<4) /* Fine Contrast bit 4 mask. */ ++#define LCD_FCONT4_bp 4 /* Fine Contrast bit 4 position. */ ++#define LCD_FCONT5_bm (1<<5) /* Fine Contrast bit 5 mask. */ ++#define LCD_FCONT5_bp 5 /* Fine Contrast bit 5 position. */ ++ ++/* LCD.CTRLG bit masks and bit positions */ ++#define LCD_TDG_gm 0xC0 /* Type of Digit group mask. */ ++#define LCD_TDG_gp 6 /* Type of Digit group position. */ ++#define LCD_TDG0_bm (1<<6) /* Type of Digit bit 0 mask. */ ++#define LCD_TDG0_bp 6 /* Type of Digit bit 0 position. */ ++#define LCD_TDG1_bm (1<<7) /* Type of Digit bit 1 mask. */ ++#define LCD_TDG1_bp 7 /* Type of Digit bit 1 position. */ ++ ++#define LCD_STSEG_gm 0x3F /* Start Segment group mask. */ ++#define LCD_STSEG_gp 0 /* Start Segment group position. */ ++#define LCD_STSEG0_bm (1<<0) /* Start Segment bit 0 mask. */ ++#define LCD_STSEG0_bp 0 /* Start Segment bit 0 position. */ ++#define LCD_STSEG1_bm (1<<1) /* Start Segment bit 1 mask. */ ++#define LCD_STSEG1_bp 1 /* Start Segment bit 1 position. */ ++#define LCD_STSEG2_bm (1<<2) /* Start Segment bit 2 mask. */ ++#define LCD_STSEG2_bp 2 /* Start Segment bit 2 position. */ ++#define LCD_STSEG3_bm (1<<3) /* Start Segment bit 3 mask. */ ++#define LCD_STSEG3_bp 3 /* Start Segment bit 3 position. */ ++#define LCD_STSEG4_bm (1<<4) /* Start Segment bit 4 mask. */ ++#define LCD_STSEG4_bp 4 /* Start Segment bit 4 position. */ ++#define LCD_STSEG5_bm (1<<5) /* Start Segment bit 5 mask. */ ++#define LCD_STSEG5_bp 5 /* Start Segment bit 5 position. */ ++ ++/* LCD.CTRLH bit masks and bit positions */ ++#define LCD_DEC_bm 0x80 /* Decrement of Start Segment bit mask. */ ++#define LCD_DEC_bp 7 /* Decrement of Start Segment bit position. */ ++ ++#define LCD_DCODE_gm 0x7F /* Display Code group mask. */ ++#define LCD_DCODE_gp 0 /* Display Code group position. */ ++#define LCD_DCODE0_bm (1<<0) /* Display Code bit 0 mask. */ ++#define LCD_DCODE0_bp 0 /* Display Code bit 0 position. */ ++#define LCD_DCODE1_bm (1<<1) /* Display Code bit 1 mask. */ ++#define LCD_DCODE1_bp 1 /* Display Code bit 1 position. */ ++#define LCD_DCODE2_bm (1<<2) /* Display Code bit 2 mask. */ ++#define LCD_DCODE2_bp 2 /* Display Code bit 2 position. */ ++#define LCD_DCODE3_bm (1<<3) /* Display Code bit 3 mask. */ ++#define LCD_DCODE3_bp 3 /* Display Code bit 3 position. */ ++#define LCD_DCODE4_bm (1<<4) /* Display Code bit 4 mask. */ ++#define LCD_DCODE4_bp 4 /* Display Code bit 4 position. */ ++#define LCD_DCODE5_bm (1<<5) /* Display Code bit 5 mask. */ ++#define LCD_DCODE5_bp 5 /* Display Code bit 5 position. */ ++#define LCD_DCODE6_bm (1<<6) /* Display Code bit 6 mask. */ ++#define LCD_DCODE6_bp 6 /* Display Code bit 6 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ ++#define NVM_FUSES_JTAGUSERID_gm 0xFF /* JTAG User ID group mask. */ ++#define NVM_FUSES_JTAGUSERID_gp 0 /* JTAG User ID group position. */ ++#define NVM_FUSES_JTAGUSERID0_bm (1<<0) /* JTAG User ID bit 0 mask. */ ++#define NVM_FUSES_JTAGUSERID0_bp 0 /* JTAG User ID bit 0 position. */ ++#define NVM_FUSES_JTAGUSERID1_bm (1<<1) /* JTAG User ID bit 1 mask. */ ++#define NVM_FUSES_JTAGUSERID1_bp 1 /* JTAG User ID bit 1 position. */ ++#define NVM_FUSES_JTAGUSERID2_bm (1<<2) /* JTAG User ID bit 2 mask. */ ++#define NVM_FUSES_JTAGUSERID2_bp 2 /* JTAG User ID bit 2 position. */ ++#define NVM_FUSES_JTAGUSERID3_bm (1<<3) /* JTAG User ID bit 3 mask. */ ++#define NVM_FUSES_JTAGUSERID3_bp 3 /* JTAG User ID bit 3 position. */ ++#define NVM_FUSES_JTAGUSERID4_bm (1<<4) /* JTAG User ID bit 4 mask. */ ++#define NVM_FUSES_JTAGUSERID4_bp 4 /* JTAG User ID bit 4 position. */ ++#define NVM_FUSES_JTAGUSERID5_bm (1<<5) /* JTAG User ID bit 5 mask. */ ++#define NVM_FUSES_JTAGUSERID5_bp 5 /* JTAG User ID bit 5 position. */ ++#define NVM_FUSES_JTAGUSERID6_bm (1<<6) /* JTAG User ID bit 6 mask. */ ++#define NVM_FUSES_JTAGUSERID6_bp 6 /* JTAG User ID bit 6 position. */ ++#define NVM_FUSES_JTAGUSERID7_bm (1<<7) /* JTAG User ID bit 7 mask. */ ++#define NVM_FUSES_JTAGUSERID7_bp 7 /* JTAG User ID bit 7 position. */ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ ++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++#define NVM_FUSES_JTAGEN_bm 0x01 /* JTAG Interface Enable bit mask. */ ++#define NVM_FUSES_JTAGEN_bp 0 /* JTAG Interface Enable bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* LOCKBIT - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* DMA interrupt vectors */ ++#define DMA_CH0_vect_num 6 ++#define DMA_CH0_vect _VECTOR(6) /* Channel 0 Interrupt */ ++#define DMA_CH1_vect_num 7 ++#define DMA_CH1_vect _VECTOR(7) /* Channel 1 Interrupt */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* USB interrupt vectors */ ++#define USB_BUSEVENT_vect_num 31 ++#define USB_BUSEVENT_vect _VECTOR(31) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ ++#define USB_TRNCOMPL_vect_num 32 ++#define USB_TRNCOMPL_vect _VECTOR(32) /* Transaction complete interrupt */ ++ ++/* LCD interrupt vectors */ ++#define LCD_INT_vect_num 35 ++#define LCD_INT_vect _VECTOR(35) /* LCD Interrupt */ ++ ++/* AES interrupt vectors */ ++#define AES_INT_vect_num 36 ++#define AES_INT_vect _VECTOR(36) /* AES Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 37 ++#define NVM_EE_vect _VECTOR(37) /* EE Interrupt */ ++#define NVM_SPM_vect_num 38 ++#define NVM_SPM_vect _VECTOR(38) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 39 ++#define PORTB_INT0_vect _VECTOR(39) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 40 ++#define PORTB_INT1_vect _VECTOR(40) /* External Interrupt 1 */ ++ ++/* ACB interrupt vectors */ ++#define ACB_AC0_vect_num 41 ++#define ACB_AC0_vect _VECTOR(41) /* AC0 Interrupt */ ++#define ACB_AC1_vect_num 42 ++#define ACB_AC1_vect _VECTOR(42) /* AC1 Interrupt */ ++#define ACB_ACW_vect_num 43 ++#define ACB_ACW_vect _VECTOR(43) /* ACW Window Mode Interrupt */ ++ ++/* ADCB interrupt vectors */ ++#define ADCB_CH0_vect_num 44 ++#define ADCB_CH0_vect _VECTOR(44) /* Interrupt 0 */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 48 ++#define PORTD_INT0_vect _VECTOR(48) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 49 ++#define PORTD_INT1_vect _VECTOR(49) /* External Interrupt 1 */ ++ ++/* PORTG interrupt vectors */ ++#define PORTG_INT0_vect_num 50 ++#define PORTG_INT0_vect _VECTOR(50) /* External Interrupt 0 */ ++#define PORTG_INT1_vect_num 51 ++#define PORTG_INT1_vect _VECTOR(51) /* External Interrupt 1 */ ++ ++/* PORTM interrupt vectors */ ++#define PORTM_INT0_vect_num 52 ++#define PORTM_INT0_vect _VECTOR(52) /* External Interrupt 0 */ ++#define PORTM_INT1_vect_num 53 ++#define PORTM_INT1_vect _VECTOR(53) /* External Interrupt 1 */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (54 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (69632) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (65536) ++#define APP_SECTION_PAGE_SIZE (256) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0xF000) ++#define APPTABLE_SECTION_SIZE (4096) ++#define APPTABLE_SECTION_PAGE_SIZE (256) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x10000) ++#define BOOT_SECTION_SIZE (4096) ++#define BOOT_SECTION_PAGE_SIZE (256) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (12288) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (2048) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (4096) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (2048) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (6) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (256) ++#define USER_SIGNATURES_PAGE_SIZE (256) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (256) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 256 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 */ ++#define FUSE_JTAGUSERID0 (unsigned char)~_BV(0) /* JTAG User ID Bit 0 */ ++#define FUSE_JTAGUSERID1 (unsigned char)~_BV(1) /* JTAG User ID Bit 1 */ ++#define FUSE_JTAGUSERID2 (unsigned char)~_BV(2) /* JTAG User ID Bit 2 */ ++#define FUSE_JTAGUSERID3 (unsigned char)~_BV(3) /* JTAG User ID Bit 3 */ ++#define FUSE_JTAGUSERID4 (unsigned char)~_BV(4) /* JTAG User ID Bit 4 */ ++#define FUSE_JTAGUSERID5 (unsigned char)~_BV(5) /* JTAG User ID Bit 5 */ ++#define FUSE_JTAGUSERID6 (unsigned char)~_BV(6) /* JTAG User ID Bit 6 */ ++#define FUSE_JTAGUSERID7 (unsigned char)~_BV(7) /* JTAG User ID Bit 7 */ ++#define FUSE0_DEFAULT (0xFF) ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_JTAGEN (unsigned char)~_BV(0) /* JTAG Interface Enable */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x51 ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA64B3_H_INCLUDED */ ++ +diff --git a/include/avr/iox64c3.h b/include/avr/iox64c3.h +new file mode 100644 +index 0000000..ee56f70 +--- /dev/null ++++ b/include/avr/iox64c3.h +@@ -0,0 +1,6216 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox64c3.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA64C3_H_INCLUDED ++#define _AVR_ATXMEGA64C3_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t USBCTRL; /* USB Control Register */ ++} CLK_t; ++ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t reserved_0x02; ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++/* USB Prescaler Division Factor */ ++typedef enum CLK_USBPSDIV_enum ++{ ++ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */ ++ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */ ++ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */ ++ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */ ++ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */ ++ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */ ++} CLK_USBPSDIV_t; ++ ++/* USB Clock Source */ ++typedef enum CLK_USBSRC_enum ++{ ++ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */ ++ CLK_USBSRC_RC32M_gc = (0x01<<1), /* Internal 32 MHz RC Oscillator */ ++} CLK_USBSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 2 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC2MCREF_enum ++{ ++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC2MCREF_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++ OSC_RC32MCREF_USBSOF_gc = (0x02<<1), /* USB Start of Frame */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++ register8_t reserved_0x05; ++ register8_t EVOUTSEL; /* Event Output Select */ ++} PORTCFG_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP02MAP_enum ++{ ++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP02MAP_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP13MAP_enum ++{ ++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP13MAP_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t reserved_0x07; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++} ADC_t; ++ ++/* Current Limitation */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ ++} ADC_CURRLIMIT_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ ++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ ++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ ++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* SDA Hold Time */ ++typedef enum TWI_SDAHOLD_enum ++{ ++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ ++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ ++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ ++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ ++} TWI_SDAHOLD_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USB - USB ++-------------------------------------------------------------------------- ++*/ ++ ++/* USB Endpoint */ ++typedef struct USB_EP_struct ++{ ++ register8_t STATUS; /* Endpoint Status */ ++ register8_t CTRL; /* Endpoint Control */ ++ _WORDREGISTER(CNT); /* USB Endpoint Counter */ ++ _WORDREGISTER(DATAPTR); /* Data Pointer */ ++ _WORDREGISTER(AUXDATA); /* Auxiliary Data */ ++} USB_EP_t; ++ ++ ++/* Universal Serial Bus */ ++typedef struct USB_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t FIFOWP; /* FIFO Write Pointer Register */ ++ register8_t FIFORP; /* FIFO Read Pointer Register */ ++ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */ ++ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */ ++ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */ ++ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t reserved_0x20; ++ register8_t reserved_0x21; ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t CAL0; /* Calibration Byte 0 */ ++ register8_t CAL1; /* Calibration Byte 1 */ ++} USB_t; ++ ++ ++/* USB Endpoint Table */ ++typedef struct USB_EP_TABLE_struct ++{ ++ USB_EP_t EP0OUT; /* Endpoint 0 */ ++ USB_EP_t EP0IN; /* Endpoint 0 */ ++ USB_EP_t EP1OUT; /* Endpoint 1 */ ++ USB_EP_t EP1IN; /* Endpoint 1 */ ++ USB_EP_t EP2OUT; /* Endpoint 2 */ ++ USB_EP_t EP2IN; /* Endpoint 2 */ ++ USB_EP_t EP3OUT; /* Endpoint 3 */ ++ USB_EP_t EP3IN; /* Endpoint 3 */ ++ USB_EP_t EP4OUT; /* Endpoint 4 */ ++ USB_EP_t EP4IN; /* Endpoint 4 */ ++ USB_EP_t EP5OUT; /* Endpoint 5 */ ++ USB_EP_t EP5IN; /* Endpoint 5 */ ++ USB_EP_t EP6OUT; /* Endpoint 6 */ ++ USB_EP_t EP6IN; /* Endpoint 6 */ ++ USB_EP_t EP7OUT; /* Endpoint 7 */ ++ USB_EP_t EP7IN; /* Endpoint 7 */ ++ USB_EP_t EP8OUT; /* Endpoint 8 */ ++ USB_EP_t EP8IN; /* Endpoint 8 */ ++ USB_EP_t EP9OUT; /* Endpoint 9 */ ++ USB_EP_t EP9IN; /* Endpoint 9 */ ++ USB_EP_t EP10OUT; /* Endpoint 10 */ ++ USB_EP_t EP10IN; /* Endpoint 10 */ ++ USB_EP_t EP11OUT; /* Endpoint 11 */ ++ USB_EP_t EP11IN; /* Endpoint 11 */ ++ USB_EP_t EP12OUT; /* Endpoint 12 */ ++ USB_EP_t EP12IN; /* Endpoint 12 */ ++ USB_EP_t EP13OUT; /* Endpoint 13 */ ++ USB_EP_t EP13IN; /* Endpoint 13 */ ++ USB_EP_t EP14OUT; /* Endpoint 14 */ ++ USB_EP_t EP14IN; /* Endpoint 14 */ ++ USB_EP_t EP15OUT; /* Endpoint 15 */ ++ USB_EP_t EP15IN; /* Endpoint 15 */ ++ register8_t reserved_0x100; ++ register8_t reserved_0x101; ++ register8_t reserved_0x102; ++ register8_t reserved_0x103; ++ register8_t reserved_0x104; ++ register8_t reserved_0x105; ++ register8_t reserved_0x106; ++ register8_t reserved_0x107; ++ register8_t reserved_0x108; ++ register8_t reserved_0x109; ++ register8_t reserved_0x10A; ++ register8_t reserved_0x10B; ++ register8_t reserved_0x10C; ++ register8_t reserved_0x10D; ++ register8_t reserved_0x10E; ++ register8_t reserved_0x10F; ++ register8_t FRAMENUML; /* Frame Number Low Byte */ ++ register8_t FRAMENUMH; /* Frame Number High Byte */ ++} USB_EP_TABLE_t; ++ ++/* Interrupt level */ ++typedef enum USB_INTLVL_enum ++{ ++ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ USB_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ USB_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ USB_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} USB_INTLVL_t; ++ ++/* USB Endpoint Type */ ++typedef enum USB_EP_TYPE_enum ++{ ++ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */ ++ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */ ++ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */ ++ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */ ++} USB_EP_TYPE_t; ++ ++/* USB Endpoint Buffersize */ ++typedef enum USB_EP_BUFSIZE_enum ++{ ++ USB_EP_BUFSIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */ ++ USB_EP_BUFSIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */ ++ USB_EP_BUFSIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */ ++ USB_EP_BUFSIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */ ++ USB_EP_BUFSIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */ ++ USB_EP_BUFSIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */ ++ USB_EP_BUFSIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */ ++ USB_EP_BUFSIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */ ++} USB_EP_BUFSIZE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - I/O Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* I/O Port Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Byte Mode */ ++typedef enum TC_BYTEM_enum ++{ ++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ ++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ ++} TC_BYTEM_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC2 - 16-bit Timer/Counter type 2 ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter type 2 */ ++typedef struct TC2_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t reserved_0x03; ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t reserved_0x08; ++ register8_t CTRLF; /* Control Register F */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t LCNT; /* Low Byte Count */ ++ register8_t HCNT; /* High Byte Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t LPER; /* Low Byte Period */ ++ register8_t HPER; /* High Byte Period */ ++ register8_t LCMPA; /* Low Byte Compare A */ ++ register8_t HCMPA; /* High Byte Compare A */ ++ register8_t LCMPB; /* Low Byte Compare B */ ++ register8_t HCMPB; /* High Byte Compare B */ ++ register8_t LCMPC; /* Low Byte Compare C */ ++ register8_t HCMPC; /* High Byte Compare C */ ++ register8_t LCMPD; /* Low Byte Compare D */ ++ register8_t HCMPD; /* High Byte Compare D */ ++} TC2_t; ++ ++/* Clock Selection */ ++typedef enum TC2_CLKSEL_enum ++{ ++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC2_CLKSEL_t; ++ ++/* Byte Mode */ ++typedef enum TC2_BYTEM_enum ++{ ++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ ++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ ++} TC2_BYTEM_t; ++ ++/* High Byte Underflow Interrupt Level */ ++typedef enum TC2_HUNFINTLVL_enum ++{ ++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_HUNFINTLVL_t; ++ ++/* Low Byte Underflow Interrupt Level */ ++typedef enum TC2_LUNFINTLVL_enum ++{ ++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LUNFINTLVL_t; ++ ++/* Low Byte Compare D Interrupt Level */ ++typedef enum TC2_LCMPDINTLVL_enum ++{ ++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC2_LCMPDINTLVL_t; ++ ++/* Low Byte Compare C Interrupt Level */ ++typedef enum TC2_LCMPCINTLVL_enum ++{ ++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC2_LCMPCINTLVL_t; ++ ++/* Low Byte Compare B Interrupt Level */ ++typedef enum TC2_LCMPBINTLVL_enum ++{ ++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_LCMPBINTLVL_t; ++ ++/* Low Byte Compare A Interrupt Level */ ++typedef enum TC2_LCMPAINTLVL_enum ++{ ++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LCMPAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMD_enum ++{ ++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC2_CMD_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMDEN_enum ++{ ++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ ++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ ++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ ++} TC2_CMDEN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AWEX - Timer/Counter Advanced Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - Timer/Counter High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t reserved_0x00; ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* Timer Oscillator pin location */ ++typedef enum TOSCSEL_enum ++{ ++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ ++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ ++} TOSCSEL_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* BOD operation */ ++typedef enum BODACT_enum ++{ ++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BODACT_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WDP_enum ++{ ++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ ++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ ++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ ++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ ++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ ++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ ++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ ++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ ++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ ++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ ++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ ++} WDP_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LOCKBIT - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ ++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t USBCAL0; /* USB Calibration Byte 0 */ ++ register8_t USBCAL1; /* USB Calibration Byte 1 */ ++ register8_t USBRCOSC; /* USB RCOSC Calibration Value B */ ++ register8_t USBRCOSCA; /* USB RCOSC Calibration Value A */ ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ ++#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ ++#define PORTF (*(PORT_t *) 0x06A0) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ ++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ ++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ ++#define TCE2 (*(TC2_t *) 0x0A00) /* 16-bit Timer/Counter type 2 */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define TCF0 (*(TC0_t *) 0x0B00) /* 16-bit Timer/Counter 0 */ ++#define TCF2 (*(TC2_t *) 0x0B00) /* 16-bit Timer/Counter type 2 */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_USBCAL0 _SFR_MEM8(0x001A) ++#define PRODSIGNATURES_USBCAL1 _SFR_MEM8(0x001B) ++#define PRODSIGNATURES_USBRCOSC _SFR_MEM8(0x001C) ++#define PRODSIGNATURES_USBRCOSCA _SFR_MEM8(0x001D) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++#define CLK_USBCTRL _SFR_MEM8(0x0044) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLL - DFLL */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* USB - Universal Serial Bus */ ++#define USB_CTRLA _SFR_MEM8(0x04C0) ++#define USB_CTRLB _SFR_MEM8(0x04C1) ++#define USB_STATUS _SFR_MEM8(0x04C2) ++#define USB_ADDR _SFR_MEM8(0x04C3) ++#define USB_FIFOWP _SFR_MEM8(0x04C4) ++#define USB_FIFORP _SFR_MEM8(0x04C5) ++#define USB_EPPTR _SFR_MEM16(0x04C6) ++#define USB_INTCTRLA _SFR_MEM8(0x04C8) ++#define USB_INTCTRLB _SFR_MEM8(0x04C9) ++#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA) ++#define USB_INTFLAGSASET _SFR_MEM8(0x04CB) ++#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC) ++#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD) ++#define USB_CAL0 _SFR_MEM8(0x04FA) ++#define USB_CAL1 _SFR_MEM8(0x04FB) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_REMAP _SFR_MEM8(0x060E) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_REMAP _SFR_MEM8(0x062E) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_REMAP _SFR_MEM8(0x068E) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORT - I/O Ports */ ++#define PORTF_DIR _SFR_MEM8(0x06A0) ++#define PORTF_DIRSET _SFR_MEM8(0x06A1) ++#define PORTF_DIRCLR _SFR_MEM8(0x06A2) ++#define PORTF_DIRTGL _SFR_MEM8(0x06A3) ++#define PORTF_OUT _SFR_MEM8(0x06A4) ++#define PORTF_OUTSET _SFR_MEM8(0x06A5) ++#define PORTF_OUTCLR _SFR_MEM8(0x06A6) ++#define PORTF_OUTTGL _SFR_MEM8(0x06A7) ++#define PORTF_IN _SFR_MEM8(0x06A8) ++#define PORTF_INTCTRL _SFR_MEM8(0x06A9) ++#define PORTF_INT0MASK _SFR_MEM8(0x06AA) ++#define PORTF_INT1MASK _SFR_MEM8(0x06AB) ++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) ++#define PORTF_REMAP _SFR_MEM8(0x06AE) ++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) ++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) ++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) ++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) ++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) ++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) ++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) ++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCC2_CTRLA _SFR_MEM8(0x0800) ++#define TCC2_CTRLB _SFR_MEM8(0x0801) ++#define TCC2_CTRLC _SFR_MEM8(0x0802) ++#define TCC2_CTRLE _SFR_MEM8(0x0804) ++#define TCC2_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC2_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC2_CTRLF _SFR_MEM8(0x0809) ++#define TCC2_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC2_LCNT _SFR_MEM8(0x0820) ++#define TCC2_HCNT _SFR_MEM8(0x0821) ++#define TCC2_LPER _SFR_MEM8(0x0826) ++#define TCC2_HPER _SFR_MEM8(0x0827) ++#define TCC2_LCMPA _SFR_MEM8(0x0828) ++#define TCC2_HCMPA _SFR_MEM8(0x0829) ++#define TCC2_LCMPB _SFR_MEM8(0x082A) ++#define TCC2_HCMPB _SFR_MEM8(0x082B) ++#define TCC2_LCMPC _SFR_MEM8(0x082C) ++#define TCC2_HCMPC _SFR_MEM8(0x082D) ++#define TCC2_LCMPD _SFR_MEM8(0x082E) ++#define TCC2_HCMPD _SFR_MEM8(0x082F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_STATUSSET _SFR_MEM8(0x0885) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCD2_CTRLA _SFR_MEM8(0x0900) ++#define TCD2_CTRLB _SFR_MEM8(0x0901) ++#define TCD2_CTRLC _SFR_MEM8(0x0902) ++#define TCD2_CTRLE _SFR_MEM8(0x0904) ++#define TCD2_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD2_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD2_CTRLF _SFR_MEM8(0x0909) ++#define TCD2_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD2_LCNT _SFR_MEM8(0x0920) ++#define TCD2_HCNT _SFR_MEM8(0x0921) ++#define TCD2_LPER _SFR_MEM8(0x0926) ++#define TCD2_HPER _SFR_MEM8(0x0927) ++#define TCD2_LCMPA _SFR_MEM8(0x0928) ++#define TCD2_HCMPA _SFR_MEM8(0x0929) ++#define TCD2_LCMPB _SFR_MEM8(0x092A) ++#define TCD2_HCMPB _SFR_MEM8(0x092B) ++#define TCD2_LCMPC _SFR_MEM8(0x092C) ++#define TCD2_HCMPC _SFR_MEM8(0x092D) ++#define TCD2_LCMPD _SFR_MEM8(0x092E) ++#define TCD2_HCMPD _SFR_MEM8(0x092F) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCE2_CTRLA _SFR_MEM8(0x0A00) ++#define TCE2_CTRLB _SFR_MEM8(0x0A01) ++#define TCE2_CTRLC _SFR_MEM8(0x0A02) ++#define TCE2_CTRLE _SFR_MEM8(0x0A04) ++#define TCE2_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE2_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE2_CTRLF _SFR_MEM8(0x0A09) ++#define TCE2_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE2_LCNT _SFR_MEM8(0x0A20) ++#define TCE2_HCNT _SFR_MEM8(0x0A21) ++#define TCE2_LPER _SFR_MEM8(0x0A26) ++#define TCE2_HPER _SFR_MEM8(0x0A27) ++#define TCE2_LCMPA _SFR_MEM8(0x0A28) ++#define TCE2_HCMPA _SFR_MEM8(0x0A29) ++#define TCE2_LCMPB _SFR_MEM8(0x0A2A) ++#define TCE2_HCMPB _SFR_MEM8(0x0A2B) ++#define TCE2_LCMPC _SFR_MEM8(0x0A2C) ++#define TCE2_HCMPC _SFR_MEM8(0x0A2D) ++#define TCE2_LCMPD _SFR_MEM8(0x0A2E) ++#define TCE2_HCMPD _SFR_MEM8(0x0A2F) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCF0_CTRLA _SFR_MEM8(0x0B00) ++#define TCF0_CTRLB _SFR_MEM8(0x0B01) ++#define TCF0_CTRLC _SFR_MEM8(0x0B02) ++#define TCF0_CTRLD _SFR_MEM8(0x0B03) ++#define TCF0_CTRLE _SFR_MEM8(0x0B04) ++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) ++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) ++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) ++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) ++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF0_TEMP _SFR_MEM8(0x0B0F) ++#define TCF0_CNT _SFR_MEM16(0x0B20) ++#define TCF0_PER _SFR_MEM16(0x0B26) ++#define TCF0_CCA _SFR_MEM16(0x0B28) ++#define TCF0_CCB _SFR_MEM16(0x0B2A) ++#define TCF0_CCC _SFR_MEM16(0x0B2C) ++#define TCF0_CCD _SFR_MEM16(0x0B2E) ++#define TCF0_PERBUF _SFR_MEM16(0x0B36) ++#define TCF0_CCABUF _SFR_MEM16(0x0B38) ++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) ++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) ++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCF2_CTRLA _SFR_MEM8(0x0B00) ++#define TCF2_CTRLB _SFR_MEM8(0x0B01) ++#define TCF2_CTRLC _SFR_MEM8(0x0B02) ++#define TCF2_CTRLE _SFR_MEM8(0x0B04) ++#define TCF2_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF2_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF2_CTRLF _SFR_MEM8(0x0B09) ++#define TCF2_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF2_LCNT _SFR_MEM8(0x0B20) ++#define TCF2_HCNT _SFR_MEM8(0x0B21) ++#define TCF2_LPER _SFR_MEM8(0x0B26) ++#define TCF2_HPER _SFR_MEM8(0x0B27) ++#define TCF2_LCMPA _SFR_MEM8(0x0B28) ++#define TCF2_HCMPA _SFR_MEM8(0x0B29) ++#define TCF2_LCMPB _SFR_MEM8(0x0B2A) ++#define TCF2_HCMPB _SFR_MEM8(0x0B2B) ++#define TCF2_LCMPC _SFR_MEM8(0x0B2C) ++#define TCF2_HCMPC _SFR_MEM8(0x0B2D) ++#define TCF2_LCMPD _SFR_MEM8(0x0B2E) ++#define TCF2_HCMPD _SFR_MEM8(0x0B2F) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* CLK.USBCTRL bit masks and bit positions */ ++#define CLK_USBPSDIV_gm 0x38 /* Prescaler Division Factor group mask. */ ++#define CLK_USBPSDIV_gp 3 /* Prescaler Division Factor group position. */ ++#define CLK_USBPSDIV0_bm (1<<3) /* Prescaler Division Factor bit 0 mask. */ ++#define CLK_USBPSDIV0_bp 3 /* Prescaler Division Factor bit 0 position. */ ++#define CLK_USBPSDIV1_bm (1<<4) /* Prescaler Division Factor bit 1 mask. */ ++#define CLK_USBPSDIV1_bp 4 /* Prescaler Division Factor bit 1 position. */ ++#define CLK_USBPSDIV2_bm (1<<5) /* Prescaler Division Factor bit 2 mask. */ ++#define CLK_USBPSDIV2_bp 5 /* Prescaler Division Factor bit 2 position. */ ++ ++#define CLK_USBSRC_gm 0x06 /* Clock Source group mask. */ ++#define CLK_USBSRC_gp 1 /* Clock Source group position. */ ++#define CLK_USBSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_USBSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_USBSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_USBSRC1_bp 2 /* Clock Source bit 1 position. */ ++ ++#define CLK_USBSEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_USBSEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_USB_bm 0x40 /* USB bit mask. */ ++#define PR_USB_bp 6 /* USB bit position. */ ++ ++#define PR_AES_bm 0x10 /* AES bit mask. */ ++#define PR_AES_bp 4 /* AES bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ ++#define PR_DMA_bp 0 /* DMA-Controller bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ ++#define PR_USART1_bp 5 /* Port C USART1 bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ ++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ ++ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ ++ ++/* PORTCFG.EVOUTSEL bit masks and bit positions */ ++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ ++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ ++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ ++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ ++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ ++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ ++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ ++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ ++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ ++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ ++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ ++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ ++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ ++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ ++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ ++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ ++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ ++ ++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ ++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ ++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ ++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ ++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ ++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ ++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ ++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ ++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ ++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ ++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* RTC - Real-Time Counter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* USB - USB */ ++/* USB_EP.STATUS bit masks and bit positions */ ++#define USB_EP_STALLF_bm 0x80 /* Endpoint Stall Flag bit mask. */ ++#define USB_EP_STALLF_bp 7 /* Endpoint Stall Flag bit position. */ ++ ++#define USB_EP_CRC_bm 0x80 /* CRC Error Flag bit mask. */ ++#define USB_EP_CRC_bp 7 /* CRC Error Flag bit position. */ ++ ++#define USB_EP_UNF_bm 0x40 /* Underflow Enpoint FLag bit mask. */ ++#define USB_EP_UNF_bp 6 /* Underflow Enpoint FLag bit position. */ ++ ++#define USB_EP_OVF_bm 0x40 /* Overflow Enpoint Flag for Output Endpoints bit mask. */ ++#define USB_EP_OVF_bp 6 /* Overflow Enpoint Flag for Output Endpoints bit position. */ ++ ++#define USB_EP_TRNCOMPL0_bm 0x20 /* Transaction Complete 0 Flag bit mask. */ ++#define USB_EP_TRNCOMPL0_bp 5 /* Transaction Complete 0 Flag bit position. */ ++ ++#define USB_EP_TRNCOMPL1_bm 0x10 /* Transaction Complete 1 Flag bit mask. */ ++#define USB_EP_TRNCOMPL1_bp 4 /* Transaction Complete 1 Flag bit position. */ ++ ++#define USB_EP_SETUP_bm 0x10 /* SETUP Transaction Complete Flag bit mask. */ ++#define USB_EP_SETUP_bp 4 /* SETUP Transaction Complete Flag bit position. */ ++ ++#define USB_EP_BANK_bm 0x08 /* Bank Select bit mask. */ ++#define USB_EP_BANK_bp 3 /* Bank Select bit position. */ ++ ++#define USB_EP_BUSNACK1_bm 0x04 /* Data Buffer 1 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK1_bp 2 /* Data Buffer 1 Not Acknowledge bit position. */ ++ ++#define USB_EP_BUSNACK0_bm 0x02 /* Data Buffer 0 Not Acknowledge bit mask. */ ++#define USB_EP_BUSNACK0_bp 1 /* Data Buffer 0 Not Acknowledge bit position. */ ++ ++#define USB_EP_TOGGLE_bm 0x01 /* Data Toggle bit mask. */ ++#define USB_EP_TOGGLE_bp 0 /* Data Toggle bit position. */ ++ ++/* USB_EP.CTRL bit masks and bit positions */ ++#define USB_EP_TYPE_gm 0xC0 /* Endpoint Type group mask. */ ++#define USB_EP_TYPE_gp 6 /* Endpoint Type group position. */ ++#define USB_EP_TYPE0_bm (1<<6) /* Endpoint Type bit 0 mask. */ ++#define USB_EP_TYPE0_bp 6 /* Endpoint Type bit 0 position. */ ++#define USB_EP_TYPE1_bm (1<<7) /* Endpoint Type bit 1 mask. */ ++#define USB_EP_TYPE1_bp 7 /* Endpoint Type bit 1 position. */ ++ ++#define USB_EP_MULTIPKT_bm 0x20 /* Multi Packet Transfer Enable bit mask. */ ++#define USB_EP_MULTIPKT_bp 5 /* Multi Packet Transfer Enable bit position. */ ++ ++#define USB_EP_PINGPONG_bm 0x10 /* Ping-Pong Enable bit mask. */ ++#define USB_EP_PINGPONG_bp 4 /* Ping-Pong Enable bit position. */ ++ ++#define USB_EP_INTDSBL_bm 0x08 /* Interrupt Disable bit mask. */ ++#define USB_EP_INTDSBL_bp 3 /* Interrupt Disable bit position. */ ++ ++#define USB_EP_STALL_bm 0x04 /* Data Stall bit mask. */ ++#define USB_EP_STALL_bp 2 /* Data Stall bit position. */ ++ ++#define USB_EP_BUFSIZE_gm 0x07 /* Data Buffer Size group mask. */ ++#define USB_EP_BUFSIZE_gp 0 /* Data Buffer Size group position. */ ++#define USB_EP_BUFSIZE0_bm (1<<0) /* Data Buffer Size bit 0 mask. */ ++#define USB_EP_BUFSIZE0_bp 0 /* Data Buffer Size bit 0 position. */ ++#define USB_EP_BUFSIZE1_bm (1<<1) /* Data Buffer Size bit 1 mask. */ ++#define USB_EP_BUFSIZE1_bp 1 /* Data Buffer Size bit 1 position. */ ++#define USB_EP_BUFSIZE2_bm (1<<2) /* Data Buffer Size bit 2 mask. */ ++#define USB_EP_BUFSIZE2_bp 2 /* Data Buffer Size bit 2 position. */ ++ ++/* USB_EP.CNT bit masks and bit positions */ ++#define USB_EP_ZLP_bm 0x8000 /* Zero Length Packet bit mask. */ ++#define USB_EP_ZLP_bp 15 /* Zero Length Packet bit position. */ ++ ++/* USB.CTRLA bit masks and bit positions */ ++#define USB_ENABLE_bm 0x80 /* USB Enable bit mask. */ ++#define USB_ENABLE_bp 7 /* USB Enable bit position. */ ++ ++#define USB_SPEED_bm 0x40 /* Speed Select bit mask. */ ++#define USB_SPEED_bp 6 /* Speed Select bit position. */ ++ ++#define USB_FIFOEN_bm 0x20 /* USB FIFO Enable bit mask. */ ++#define USB_FIFOEN_bp 5 /* USB FIFO Enable bit position. */ ++ ++#define USB_STFRNUM_bm 0x10 /* Store Frame Number Enable bit mask. */ ++#define USB_STFRNUM_bp 4 /* Store Frame Number Enable bit position. */ ++ ++#define USB_MAXEP_gm 0x0F /* Maximum Endpoint Addresses group mask. */ ++#define USB_MAXEP_gp 0 /* Maximum Endpoint Addresses group position. */ ++#define USB_MAXEP0_bm (1<<0) /* Maximum Endpoint Addresses bit 0 mask. */ ++#define USB_MAXEP0_bp 0 /* Maximum Endpoint Addresses bit 0 position. */ ++#define USB_MAXEP1_bm (1<<1) /* Maximum Endpoint Addresses bit 1 mask. */ ++#define USB_MAXEP1_bp 1 /* Maximum Endpoint Addresses bit 1 position. */ ++#define USB_MAXEP2_bm (1<<2) /* Maximum Endpoint Addresses bit 2 mask. */ ++#define USB_MAXEP2_bp 2 /* Maximum Endpoint Addresses bit 2 position. */ ++#define USB_MAXEP3_bm (1<<3) /* Maximum Endpoint Addresses bit 3 mask. */ ++#define USB_MAXEP3_bp 3 /* Maximum Endpoint Addresses bit 3 position. */ ++ ++/* USB.CTRLB bit masks and bit positions */ ++#define USB_PULLRST_bm 0x10 /* Pull during Reset bit mask. */ ++#define USB_PULLRST_bp 4 /* Pull during Reset bit position. */ ++ ++#define USB_RWAKEUP_bm 0x04 /* Remote Wake-up bit mask. */ ++#define USB_RWAKEUP_bp 2 /* Remote Wake-up bit position. */ ++ ++#define USB_GNACK_bm 0x02 /* Global NACK bit mask. */ ++#define USB_GNACK_bp 1 /* Global NACK bit position. */ ++ ++#define USB_ATTACH_bm 0x01 /* Attach bit mask. */ ++#define USB_ATTACH_bp 0 /* Attach bit position. */ ++ ++/* USB.STATUS bit masks and bit positions */ ++#define USB_URESUME_bm 0x08 /* Upstream Resume bit mask. */ ++#define USB_URESUME_bp 3 /* Upstream Resume bit position. */ ++ ++#define USB_RESUME_bm 0x04 /* Resume bit mask. */ ++#define USB_RESUME_bp 2 /* Resume bit position. */ ++ ++#define USB_SUSPEND_bm 0x02 /* Bus Suspended bit mask. */ ++#define USB_SUSPEND_bp 1 /* Bus Suspended bit position. */ ++ ++#define USB_BUSRST_bm 0x01 /* Bus Reset bit mask. */ ++#define USB_BUSRST_bp 0 /* Bus Reset bit position. */ ++ ++/* USB.ADDR bit masks and bit positions */ ++#define USB_ADDR_gm 0x7F /* Device Address group mask. */ ++#define USB_ADDR_gp 0 /* Device Address group position. */ ++#define USB_ADDR0_bm (1<<0) /* Device Address bit 0 mask. */ ++#define USB_ADDR0_bp 0 /* Device Address bit 0 position. */ ++#define USB_ADDR1_bm (1<<1) /* Device Address bit 1 mask. */ ++#define USB_ADDR1_bp 1 /* Device Address bit 1 position. */ ++#define USB_ADDR2_bm (1<<2) /* Device Address bit 2 mask. */ ++#define USB_ADDR2_bp 2 /* Device Address bit 2 position. */ ++#define USB_ADDR3_bm (1<<3) /* Device Address bit 3 mask. */ ++#define USB_ADDR3_bp 3 /* Device Address bit 3 position. */ ++#define USB_ADDR4_bm (1<<4) /* Device Address bit 4 mask. */ ++#define USB_ADDR4_bp 4 /* Device Address bit 4 position. */ ++#define USB_ADDR5_bm (1<<5) /* Device Address bit 5 mask. */ ++#define USB_ADDR5_bp 5 /* Device Address bit 5 position. */ ++#define USB_ADDR6_bm (1<<6) /* Device Address bit 6 mask. */ ++#define USB_ADDR6_bp 6 /* Device Address bit 6 position. */ ++ ++/* USB.FIFOWP bit masks and bit positions */ ++#define USB_FIFOWP_gm 0x1F /* FIFO Write Pointer group mask. */ ++#define USB_FIFOWP_gp 0 /* FIFO Write Pointer group position. */ ++#define USB_FIFOWP0_bm (1<<0) /* FIFO Write Pointer bit 0 mask. */ ++#define USB_FIFOWP0_bp 0 /* FIFO Write Pointer bit 0 position. */ ++#define USB_FIFOWP1_bm (1<<1) /* FIFO Write Pointer bit 1 mask. */ ++#define USB_FIFOWP1_bp 1 /* FIFO Write Pointer bit 1 position. */ ++#define USB_FIFOWP2_bm (1<<2) /* FIFO Write Pointer bit 2 mask. */ ++#define USB_FIFOWP2_bp 2 /* FIFO Write Pointer bit 2 position. */ ++#define USB_FIFOWP3_bm (1<<3) /* FIFO Write Pointer bit 3 mask. */ ++#define USB_FIFOWP3_bp 3 /* FIFO Write Pointer bit 3 position. */ ++#define USB_FIFOWP4_bm (1<<4) /* FIFO Write Pointer bit 4 mask. */ ++#define USB_FIFOWP4_bp 4 /* FIFO Write Pointer bit 4 position. */ ++ ++/* USB.FIFORP bit masks and bit positions */ ++#define USB_FIFORP_gm 0x1F /* FIFO Read Pointer group mask. */ ++#define USB_FIFORP_gp 0 /* FIFO Read Pointer group position. */ ++#define USB_FIFORP0_bm (1<<0) /* FIFO Read Pointer bit 0 mask. */ ++#define USB_FIFORP0_bp 0 /* FIFO Read Pointer bit 0 position. */ ++#define USB_FIFORP1_bm (1<<1) /* FIFO Read Pointer bit 1 mask. */ ++#define USB_FIFORP1_bp 1 /* FIFO Read Pointer bit 1 position. */ ++#define USB_FIFORP2_bm (1<<2) /* FIFO Read Pointer bit 2 mask. */ ++#define USB_FIFORP2_bp 2 /* FIFO Read Pointer bit 2 position. */ ++#define USB_FIFORP3_bm (1<<3) /* FIFO Read Pointer bit 3 mask. */ ++#define USB_FIFORP3_bp 3 /* FIFO Read Pointer bit 3 position. */ ++#define USB_FIFORP4_bm (1<<4) /* FIFO Read Pointer bit 4 mask. */ ++#define USB_FIFORP4_bp 4 /* FIFO Read Pointer bit 4 position. */ ++ ++/* USB.INTCTRLA bit masks and bit positions */ ++#define USB_SOFIE_bm 0x80 /* Start Of Frame Interrupt Enable bit mask. */ ++#define USB_SOFIE_bp 7 /* Start Of Frame Interrupt Enable bit position. */ ++ ++#define USB_BUSEVIE_bm 0x40 /* Bus Event Interrupt Enable bit mask. */ ++#define USB_BUSEVIE_bp 6 /* Bus Event Interrupt Enable bit position. */ ++ ++#define USB_BUSERRIE_bm 0x20 /* Bus Error Interrupt Enable bit mask. */ ++#define USB_BUSERRIE_bp 5 /* Bus Error Interrupt Enable bit position. */ ++ ++#define USB_STALLIE_bm 0x10 /* STALL Interrupt Enable bit mask. */ ++#define USB_STALLIE_bp 4 /* STALL Interrupt Enable bit position. */ ++ ++#define USB_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define USB_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define USB_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define USB_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define USB_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define USB_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* USB.INTCTRLB bit masks and bit positions */ ++#define USB_TRNIE_bm 0x02 /* Transaction Complete Interrupt Enable bit mask. */ ++#define USB_TRNIE_bp 1 /* Transaction Complete Interrupt Enable bit position. */ ++ ++#define USB_SETUPIE_bm 0x01 /* SETUP Transaction Complete Interrupt Enable bit mask. */ ++#define USB_SETUPIE_bp 0 /* SETUP Transaction Complete Interrupt Enable bit position. */ ++ ++/* USB.INTFLAGSACLR bit masks and bit positions */ ++#define USB_SOFIF_bm 0x80 /* Start Of Frame Interrupt Flag bit mask. */ ++#define USB_SOFIF_bp 7 /* Start Of Frame Interrupt Flag bit position. */ ++ ++#define USB_SUSPENDIF_bm 0x40 /* Suspend Interrupt Flag bit mask. */ ++#define USB_SUSPENDIF_bp 6 /* Suspend Interrupt Flag bit position. */ ++ ++#define USB_RESUMEIF_bm 0x20 /* Resume Interrupt Flag bit mask. */ ++#define USB_RESUMEIF_bp 5 /* Resume Interrupt Flag bit position. */ ++ ++#define USB_RSTIF_bm 0x10 /* Reset Interrupt Flag bit mask. */ ++#define USB_RSTIF_bp 4 /* Reset Interrupt Flag bit position. */ ++ ++#define USB_CRCIF_bm 0x08 /* Isochronous CRC Error Interrupt Flag bit mask. */ ++#define USB_CRCIF_bp 3 /* Isochronous CRC Error Interrupt Flag bit position. */ ++ ++#define USB_UNFIF_bm 0x04 /* Underflow Interrupt Flag bit mask. */ ++#define USB_UNFIF_bp 2 /* Underflow Interrupt Flag bit position. */ ++ ++#define USB_OVFIF_bm 0x02 /* Overflow Interrupt Flag bit mask. */ ++#define USB_OVFIF_bp 1 /* Overflow Interrupt Flag bit position. */ ++ ++#define USB_STALLIF_bm 0x01 /* STALL Interrupt Flag bit mask. */ ++#define USB_STALLIF_bp 0 /* STALL Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSASET bit masks and bit positions */ ++/* USB_SOFIF Predefined. */ ++/* USB_SOFIF Predefined. */ ++ ++/* USB_SUSPENDIF Predefined. */ ++/* USB_SUSPENDIF Predefined. */ ++ ++/* USB_RESUMEIF Predefined. */ ++/* USB_RESUMEIF Predefined. */ ++ ++/* USB_RSTIF Predefined. */ ++/* USB_RSTIF Predefined. */ ++ ++/* USB_CRCIF Predefined. */ ++/* USB_CRCIF Predefined. */ ++ ++/* USB_UNFIF Predefined. */ ++/* USB_UNFIF Predefined. */ ++ ++/* USB_OVFIF Predefined. */ ++/* USB_OVFIF Predefined. */ ++ ++/* USB_STALLIF Predefined. */ ++/* USB_STALLIF Predefined. */ ++ ++/* USB.INTFLAGSBCLR bit masks and bit positions */ ++#define USB_TRNIF_bm 0x02 /* Transaction Complete Interrupt Flag bit mask. */ ++#define USB_TRNIF_bp 1 /* Transaction Complete Interrupt Flag bit position. */ ++ ++#define USB_SETUPIF_bm 0x01 /* SETUP Transaction Complete Interrupt Flag bit mask. */ ++#define USB_SETUPIF_bp 0 /* SETUP Transaction Complete Interrupt Flag bit position. */ ++ ++/* USB.INTFLAGSBSET bit masks and bit positions */ ++/* USB_TRNIF Predefined. */ ++/* USB_TRNIF Predefined. */ ++ ++/* USB_SETUPIF Predefined. */ ++/* USB_SETUPIF Predefined. */ ++ ++/* PORT - I/O Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_SPI_bm 0x20 /* SPI bit mask. */ ++#define PORT_SPI_bp 5 /* SPI bit position. */ ++ ++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ ++#define PORT_USART0_bp 4 /* USART0 bit position. */ ++ ++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ ++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ ++ ++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ ++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ ++ ++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ ++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ ++ ++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ ++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD Predefined. */ ++/* TC0_CMD Predefined. */ ++ ++/* TC0_LUPD Predefined. */ ++/* TC0_LUPD Predefined. */ ++ ++/* TC0_DIR Predefined. */ ++/* TC0_DIR Predefined. */ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV Predefined. */ ++/* TC0_CCDBV Predefined. */ ++ ++/* TC0_CCCBV Predefined. */ ++/* TC0_CCCBV Predefined. */ ++ ++/* TC0_CCBBV Predefined. */ ++/* TC0_CCBBV Predefined. */ ++ ++/* TC0_CCABV Predefined. */ ++/* TC0_CCABV Predefined. */ ++ ++/* TC0_PERBV Predefined. */ ++/* TC0_PERBV Predefined. */ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD Predefined. */ ++/* TC1_CMD Predefined. */ ++ ++/* TC1_LUPD Predefined. */ ++/* TC1_LUPD Predefined. */ ++ ++/* TC1_DIR Predefined. */ ++/* TC1_DIR Predefined. */ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV Predefined. */ ++/* TC1_CCBBV Predefined. */ ++ ++/* TC1_CCABV Predefined. */ ++/* TC1_CCABV Predefined. */ ++ ++/* TC1_PERBV Predefined. */ ++/* TC1_PERBV Predefined. */ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++/* TC2.CTRLA bit masks and bit positions */ ++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC2.CTRLB bit masks and bit positions */ ++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ ++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ ++ ++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ ++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ ++ ++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ ++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ ++ ++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ ++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ ++ ++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ ++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ ++ ++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ ++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ ++ ++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ ++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ ++ ++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ ++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ ++ ++/* TC2.CTRLC bit masks and bit positions */ ++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ ++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ ++ ++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ ++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ ++ ++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ ++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ ++ ++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ ++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ ++ ++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ ++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ ++ ++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ ++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ ++ ++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ ++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ ++ ++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ ++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ ++ ++/* TC2.CTRLE bit masks and bit positions */ ++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC2.INTCTRLA bit masks and bit positions */ ++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ ++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ ++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ ++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ ++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ ++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ ++ ++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ ++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ ++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ ++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ ++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ ++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ ++ ++/* TC2.INTCTRLB bit masks and bit positions */ ++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ ++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ ++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ ++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ ++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ ++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ ++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ ++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ ++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ ++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ ++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ ++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ ++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ ++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ ++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ ++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ ++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ ++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ ++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ ++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ ++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ ++ ++/* TC2.CTRLF bit masks and bit positions */ ++#define TC2_CMD_gm 0x0C /* Command group mask. */ ++#define TC2_CMD_gp 2 /* Command group position. */ ++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC2_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC2_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ ++#define TC2_CMDEN_gp 0 /* Command Enable group position. */ ++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ ++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ ++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ ++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ ++ ++/* TC2.INTFLAGS bit masks and bit positions */ ++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ ++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ ++ ++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ ++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ ++ ++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ ++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ ++ ++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ ++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ ++ ++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ ++ ++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ ++ ++/* AWEX - Timer/Counter Advanced Waveform Extension */ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++/* AWEX.STATUSSET bit masks and bit positions */ ++/* AWEX_FDF Predefined. */ ++/* AWEX_FDF Predefined. */ ++ ++/* AWEX_DTHSBUFV Predefined. */ ++/* AWEX_DTHSBUFV Predefined. */ ++ ++/* AWEX_DTLSBUFV Predefined. */ ++/* AWEX_DTLSBUFV Predefined. */ ++ ++/* HIRES - Timer/Counter High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ ++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* LOCKBIT - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LUNF_vect_num 14 ++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_HUNF_vect_num 15 ++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPA_vect_num 16 ++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPB_vect_num 17 ++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPC_vect_num 18 ++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPD_vect_num 19 ++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LUNF_vect_num 47 ++#define TCE2_LUNF_vect _VECTOR(47) /* Low Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_HUNF_vect_num 48 ++#define TCE2_HUNF_vect _VECTOR(48) /* High Byte Underflow Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPA_vect_num 49 ++#define TCE2_LCMPA_vect _VECTOR(49) /* Low Byte Compare A Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPB_vect_num 50 ++#define TCE2_LCMPB_vect _VECTOR(50) /* Low Byte Compare B Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPC_vect_num 51 ++#define TCE2_LCMPC_vect _VECTOR(51) /* Low Byte Compare C Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* TCE2 interrupt vectors */ ++#define TCE2_LCMPD_vect_num 52 ++#define TCE2_LCMPD_vect _VECTOR(52) /* Low Byte Compare D Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LUNF_vect_num 77 ++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_HUNF_vect_num 78 ++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPA_vect_num 79 ++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPB_vect_num 80 ++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPC_vect_num 81 ++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPD_vect_num 82 ++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* PORTF interrupt vectors */ ++#define PORTF_INT0_vect_num 104 ++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ ++#define PORTF_INT1_vect_num 105 ++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_OVF_vect_num 108 ++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LUNF_vect_num 108 ++#define TCF2_LUNF_vect _VECTOR(108) /* Low Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_ERR_vect_num 109 ++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_HUNF_vect_num 109 ++#define TCF2_HUNF_vect _VECTOR(109) /* High Byte Underflow Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCA_vect_num 110 ++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPA_vect_num 110 ++#define TCF2_LCMPA_vect _VECTOR(110) /* Low Byte Compare A Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCB_vect_num 111 ++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPB_vect_num 111 ++#define TCF2_LCMPB_vect _VECTOR(111) /* Low Byte Compare B Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCC_vect_num 112 ++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPC_vect_num 112 ++#define TCF2_LCMPC_vect _VECTOR(112) /* Low Byte Compare C Interrupt */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_CCD_vect_num 113 ++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ ++ ++/* TCF2 interrupt vectors */ ++#define TCF2_LCMPD_vect_num 113 ++#define TCF2_LCMPD_vect _VECTOR(113) /* Low Byte Compare D Interrupt */ ++ ++/* USB interrupt vectors */ ++#define USB_BUSEVENT_vect_num 125 ++#define USB_BUSEVENT_vect _VECTOR(125) /* SOF, suspend, resume, reset bus event interrupts, crc, underflow, overflow and stall error interrupts */ ++#define USB_TRNCOMPL_vect_num 126 ++#define USB_TRNCOMPL_vect _VECTOR(126) /* Transaction complete interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (127 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (69632) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (65536) ++#define APP_SECTION_PAGE_SIZE (256) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0xE000) ++#define APPTABLE_SECTION_SIZE (4096) ++#define APPTABLE_SECTION_PAGE_SIZE (256) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x10000) ++#define BOOT_SECTION_SIZE (4096) ++#define BOOT_SECTION_PAGE_SIZE (256) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (12288) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (2048) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (4096) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (2048) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (6) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (256) ++#define USER_SIGNATURES_PAGE_SIZE (256) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (64) ++#define PROD_SIGNATURES_PAGE_SIZE (256) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 256 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 Reserved */ ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x49 ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA64C3_H_INCLUDED */ ++ +diff --git a/include/avr/iox64d3.h b/include/avr/iox64d3.h +index df6b35e..c19a349 100644 +--- a/include/avr/iox64d3.h ++++ b/include/avr/iox64d3.h +@@ -1,5669 +1,5718 @@ +-/* Copyright (c) 2009-2010 Atmel Corporation +- All rights reserved. +- +- Redistribution and use in source and binary forms, with or without +- modification, are permitted provided that the following conditions are met: +- +- * Redistributions of source code must retain the above copyright +- notice, this list of conditions and the following disclaimer. +- +- * Redistributions in binary form must reproduce the above copyright +- notice, this list of conditions and the following disclaimer in +- the documentation and/or other materials provided with the +- distribution. +- +- * Neither the name of the copyright holders nor the names of +- contributors may be used to endorse or promote products derived +- from this software without specific prior written permission. +- +- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE +- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +- POSSIBILITY OF SUCH DAMAGE. */ +- +-/* $Id: iox64d3.h 2194 2010-11-16 15:10:51Z arcanum $ */ +- +-/* avr/iox64d3.h - definitions for ATxmega64D3 */ +- +-/* This file should only be included from , never directly. */ +- +-#ifndef _AVR_IO_H_ +-# error "Include instead of this file." +-#endif +- +-#ifndef _AVR_IOXXX_H_ +-# define _AVR_IOXXX_H_ "iox64d3.h" +-#else +-# error "Attempt to include more than one file." +-#endif +- +- +-#ifndef _AVR_ATxmega64D3_H_ +-#define _AVR_ATxmega64D3_H_ 1 +- +- +-/* Ungrouped common registers */ +-#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ +-#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ +-#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ +-#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ +-#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ +-#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ +-#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ +-#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ +-#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ +-#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ +-#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ +-#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ +-#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ +-#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ +-#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ +-#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ +- +-#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ +-#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ +-#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ +-#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ +-#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ +-#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ +-#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ +-#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ +-#define SREG _SFR_MEM8(0x003F) /* Status Register */ +- +- +-/* C Language Only */ +-#if !defined (__ASSEMBLER__) +- +-#include +- +-typedef volatile uint8_t register8_t; +-typedef volatile uint16_t register16_t; +-typedef volatile uint32_t register32_t; +- +- +-#ifdef _WORDREGISTER +-#undef _WORDREGISTER +-#endif +-#define _WORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register16_t regname; \ +- struct \ +- { \ +- register8_t regname ## L; \ +- register8_t regname ## H; \ +- }; \ +- } +- +-#ifdef _DWORDREGISTER +-#undef _DWORDREGISTER +-#endif +-#define _DWORDREGISTER(regname) \ +- __extension__ union \ +- { \ +- register32_t regname; \ +- struct \ +- { \ +- register8_t regname ## 0; \ +- register8_t regname ## 1; \ +- register8_t regname ## 2; \ +- register8_t regname ## 3; \ +- }; \ +- } +- +- +-/* +-========================================================================== +-IO Module Structures +-========================================================================== +-*/ +- +- +-/* +--------------------------------------------------------------------------- +-XOCD - On-Chip Debug System +--------------------------------------------------------------------------- +-*/ +- +-/* On-Chip Debug System */ +-typedef struct OCD_struct +-{ +- register8_t OCDR0; /* OCD Register 0 */ +- register8_t OCDR1; /* OCD Register 1 */ +-} OCD_t; +- +- +-/* CCP signatures */ +-typedef enum CCP_enum +-{ +- CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ +- CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ +-} CCP_t; +- +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Clock System */ +-typedef struct CLK_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t PSCTRL; /* Prescaler Control Register */ +- register8_t LOCK; /* Lock register */ +- register8_t RTCCTRL; /* RTC Control Register */ +-} CLK_t; +- +-/* +--------------------------------------------------------------------------- +-CLK - Clock System +--------------------------------------------------------------------------- +-*/ +- +-/* Power Reduction */ +-typedef struct PR_struct +-{ +- register8_t PRGEN; /* General Power Reduction */ +- register8_t PRPA; /* Power Reduction Port A */ +- register8_t PRPB; /* Power Reduction Port B */ +- register8_t PRPC; /* Power Reduction Port C */ +- register8_t PRPD; /* Power Reduction Port D */ +- register8_t PRPE; /* Power Reduction Port E */ +- register8_t PRPF; /* Power Reduction Port F */ +-} PR_t; +- +-/* System Clock Selection */ +-typedef enum CLK_SCLKSEL_enum +-{ +- CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ +- CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ +- CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ +- CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ +- CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ +-} CLK_SCLKSEL_t; +- +-/* Prescaler A Division Factor */ +-typedef enum CLK_PSADIV_enum +-{ +- CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ +- CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ +- CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ +- CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ +- CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ +- CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ +- CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ +- CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ +- CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ +- CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ +-} CLK_PSADIV_t; +- +-/* Prescaler B and C Division Factor */ +-typedef enum CLK_PSBCDIV_enum +-{ +- CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ +- CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ +- CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ +- CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ +-} CLK_PSBCDIV_t; +- +-/* RTC Clock Source */ +-typedef enum CLK_RTCSRC_enum +-{ +- CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ +- CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ +- CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ +- CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ +-} CLK_RTCSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-SLEEP - Sleep Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Sleep Controller */ +-typedef struct SLEEP_struct +-{ +- register8_t CTRL; /* Control Register */ +-} SLEEP_t; +- +-/* Sleep Mode */ +-typedef enum SLEEP_SMODE_enum +-{ +- SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ +- SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ +- SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ +- SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ +- SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ +-} SLEEP_SMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-OSC - Oscillator +--------------------------------------------------------------------------- +-*/ +- +-/* Oscillator */ +-typedef struct OSC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t XOSCCTRL; /* External Oscillator Control Register */ +- register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ +- register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ +- register8_t PLLCTRL; /* PLL Control REgister */ +- register8_t DFLLCTRL; /* DFLL Control Register */ +-} OSC_t; +- +-/* Oscillator Frequency Range */ +-typedef enum OSC_FRQRANGE_enum +-{ +- OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ +- OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ +- OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ +- OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ +-} OSC_FRQRANGE_t; +- +-/* External Oscillator Selection and Startup Time */ +-typedef enum OSC_XOSCSEL_enum +-{ +- OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ +- OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ +- OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ +- OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ +- OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ +-} OSC_XOSCSEL_t; +- +-/* PLL Clock Source */ +-typedef enum OSC_PLLSRC_enum +-{ +- OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ +- OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ +- OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ +-} OSC_PLLSRC_t; +- +- +-/* +--------------------------------------------------------------------------- +-DFLL - DFLL +--------------------------------------------------------------------------- +-*/ +- +-/* DFLL */ +-typedef struct DFLL_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t CALA; /* Calibration Register A */ +- register8_t CALB; /* Calibration Register B */ +- register8_t COMP0; /* Oscillator Compare Register 0 */ +- register8_t COMP1; /* Oscillator Compare Register 1 */ +- register8_t COMP2; /* Oscillator Compare Register 2 */ +- register8_t reserved_0x07; +-} DFLL_t; +- +- +-/* +--------------------------------------------------------------------------- +-RST - Reset +--------------------------------------------------------------------------- +-*/ +- +-/* Reset */ +-typedef struct RST_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t CTRL; /* Control Register */ +-} RST_t; +- +- +-/* +--------------------------------------------------------------------------- +-WDT - Watch-Dog Timer +--------------------------------------------------------------------------- +-*/ +- +-/* Watch-Dog Timer */ +-typedef struct WDT_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t WINCTRL; /* Windowed Mode Control */ +- register8_t STATUS; /* Status */ +-} WDT_t; +- +-/* Period setting */ +-typedef enum WDT_PER_enum +-{ +- WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ +- WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ +- WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ +- WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_PER_t; +- +-/* Closed window period */ +-typedef enum WDT_WPER_enum +-{ +- WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ +- WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ +- WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ +- WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ +- WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ +- WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ +- WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ +- WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ +- WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ +- WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ +- WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ +-} WDT_WPER_t; +- +- +-/* +--------------------------------------------------------------------------- +-MCU - MCU Control +--------------------------------------------------------------------------- +-*/ +- +-/* MCU Control */ +-typedef struct MCU_struct +-{ +- register8_t DEVID0; /* Device ID byte 0 */ +- register8_t DEVID1; /* Device ID byte 1 */ +- register8_t DEVID2; /* Device ID byte 2 */ +- register8_t REVID; /* Revision ID */ +- register8_t JTAGUID; /* JTAG User ID */ +- register8_t reserved_0x05; +- register8_t MCUCR; /* MCU Control */ +- register8_t reserved_0x07; +- register8_t EVSYSLOCK; /* Event System Lock */ +- register8_t AWEXLOCK; /* AWEX Lock */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +-} MCU_t; +- +- +-/* +--------------------------------------------------------------------------- +-PMIC - Programmable Multi-level Interrupt Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Programmable Multi-level Interrupt Controller */ +-typedef struct PMIC_struct +-{ +- register8_t STATUS; /* Status Register */ +- register8_t INTPRI; /* Interrupt Priority */ +- register8_t CTRL; /* Control Register */ +-} PMIC_t; +- +- +-/* +--------------------------------------------------------------------------- +-EVSYS - Event System +--------------------------------------------------------------------------- +-*/ +- +-/* Event System */ +-typedef struct EVSYS_struct +-{ +- register8_t CH0MUX; /* Event Channel 0 Multiplexer */ +- register8_t CH1MUX; /* Event Channel 1 Multiplexer */ +- register8_t CH2MUX; /* Event Channel 2 Multiplexer */ +- register8_t CH3MUX; /* Event Channel 3 Multiplexer */ +- register8_t reserved_0x04; +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t CH0CTRL; /* Channel 0 Control Register */ +- register8_t CH1CTRL; /* Channel 1 Control Register */ +- register8_t CH2CTRL; /* Channel 2 Control Register */ +- register8_t CH3CTRL; /* Channel 3 Control Register */ +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t STROBE; /* Event Strobe */ +- register8_t DATA; /* Event Data */ +-} EVSYS_t; +- +-/* Quadrature Decoder Index Recognition Mode */ +-typedef enum EVSYS_QDIRM_enum +-{ +- EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ +- EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ +- EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ +- EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ +-} EVSYS_QDIRM_t; +- +-/* Digital filter coefficient */ +-typedef enum EVSYS_DIGFILT_enum +-{ +- EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ +- EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ +- EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ +- EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ +- EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ +- EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ +- EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ +- EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ +-} EVSYS_DIGFILT_t; +- +-/* Event Channel multiplexer input selection */ +-typedef enum EVSYS_CHMUX_enum +-{ +- EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ +- EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ +- EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ +- EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ +- EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ +- EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ +- EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ +- EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ +- EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ +- EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ +- EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ +- EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ +- EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ +- EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ +- EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ +- EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ +- EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ +- EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ +- EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ +- EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ +- EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ +- EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ +- EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ +- EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ +- EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ +- EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ +- EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ +- EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ +- EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ +- EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ +- EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ +- EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ +- EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ +- EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ +- EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ +- EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ +- EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ +- EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ +- EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ +- EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ +- EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ +- EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ +- EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ +- EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ +- EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ +- EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ +- EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ +- EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ +- EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ +- EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ +- EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ +- EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ +- EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ +- EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ +- EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ +- EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ +- EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ +- EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ +- EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ +- EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ +- EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ +- EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ +- EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ +- EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ +- EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ +- EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ +- EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ +- EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ +- EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ +- EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ +- EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ +- EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ +- EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ +- EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ +- EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ +- EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ +- EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ +- EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ +- EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ +- EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ +- EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ +- EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ +- EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ +- EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ +- EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ +- EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ +- EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ +- EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ +- EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ +- EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ +- EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ +- EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ +- EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ +- EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ +- EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ +- EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ +- EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ +- EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ +- EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ +- EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ +- EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ +- EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ +- EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ +- EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ +- EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ +- EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ +- EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ +- EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ +-} EVSYS_CHMUX_t; +- +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Non-volatile Memory Controller */ +-typedef struct NVM_struct +-{ +- register8_t ADDR0; /* Address Register 0 */ +- register8_t ADDR1; /* Address Register 1 */ +- register8_t ADDR2; /* Address Register 2 */ +- register8_t reserved_0x03; +- register8_t DATA0; /* Data Register 0 */ +- register8_t DATA1; /* Data Register 1 */ +- register8_t DATA2; /* Data Register 2 */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t CMD; /* Command */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t INTCTRL; /* Interrupt Control */ +- register8_t reserved_0x0E; +- register8_t STATUS; /* Status */ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Lock Bits */ +-typedef struct NVM_LOCKBITS_struct +-{ +- register8_t LOCKBITS; /* Lock Bits */ +-} NVM_LOCKBITS_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Fuses */ +-typedef struct NVM_FUSES_struct +-{ +- register8_t FUSEBYTE0; /* User ID */ +- register8_t FUSEBYTE1; /* Watchdog Configuration */ +- register8_t FUSEBYTE2; /* Reset Configuration */ +- register8_t reserved_0x03; +- register8_t FUSEBYTE4; /* Start-up Configuration */ +- register8_t FUSEBYTE5; /* EESAVE and BOD Level */ +-} NVM_FUSES_t; +- +-/* +--------------------------------------------------------------------------- +-NVM - Non Volatile Memory Controller +--------------------------------------------------------------------------- +-*/ +- +-/* Production Signatures */ +-typedef struct NVM_PROD_SIGNATURES_struct +-{ +- register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ +- register8_t reserved_0x01; +- register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ +- register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ +- register8_t reserved_0x04; +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ +- register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ +- register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ +- register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ +- register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ +- register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t WAFNUM; /* Wafer Number */ +- register8_t reserved_0x11; +- register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ +- register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ +- register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ +- register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ +- register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ +- register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ +- register8_t reserved_0x26; +- register8_t reserved_0x27; +- register8_t reserved_0x28; +- register8_t reserved_0x29; +- register8_t reserved_0x2A; +- register8_t reserved_0x2B; +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ +- register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ +- register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ +- register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ +- register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ +- register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- register8_t reserved_0x36; +- register8_t reserved_0x37; +- register8_t reserved_0x38; +- register8_t reserved_0x39; +- register8_t reserved_0x3A; +- register8_t reserved_0x3B; +- register8_t reserved_0x3C; +- register8_t reserved_0x3D; +- register8_t reserved_0x3E; +-} NVM_PROD_SIGNATURES_t; +- +-/* NVM Command */ +-typedef enum NVM_CMD_enum +-{ +- NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ +- NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ +- NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ +- NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ +- NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ +- NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ +- NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ +- NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ +- NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ +- NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ +- NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ +- NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ +- NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ +- NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ +- NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ +- NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ +- NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ +- NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ +- NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ +- NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ +- NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ +- NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ +- NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ +- NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ +- NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ +- NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ +-} NVM_CMD_t; +- +-/* SPM ready interrupt level */ +-typedef enum NVM_SPMLVL_enum +-{ +- NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ +- NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ +- NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ +- NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ +-} NVM_SPMLVL_t; +- +-/* EEPROM ready interrupt level */ +-typedef enum NVM_EELVL_enum +-{ +- NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ +- NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ +- NVM_EELVL_HI_gc = (0x03<<0), /* High level */ +-} NVM_EELVL_t; +- +-/* Boot lock bits - boot setcion */ +-typedef enum NVM_BLBB_enum +-{ +- NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ +- NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ +- NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ +- NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ +-} NVM_BLBB_t; +- +-/* Boot lock bits - application section */ +-typedef enum NVM_BLBA_enum +-{ +- NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ +- NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ +- NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ +- NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ +-} NVM_BLBA_t; +- +-/* Boot lock bits - application table section */ +-typedef enum NVM_BLBAT_enum +-{ +- NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ +- NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ +- NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ +- NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ +-} NVM_BLBAT_t; +- +-/* Lock bits */ +-typedef enum NVM_LB_enum +-{ +- NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ +- NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ +- NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ +-} NVM_LB_t; +- +-/* Boot Loader Section Reset Vector */ +-typedef enum BOOTRST_enum +-{ +- BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ +- BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ +-} BOOTRST_t; +- +-/* BOD operation */ +-typedef enum BOD_enum +-{ +- BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ +- BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ +- BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ +-} BOD_t; +- +-/* Watchdog (Window) Timeout Period */ +-typedef enum WD_enum +-{ +- WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ +- WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ +- WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ +- WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ +- WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ +- WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ +- WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ +- WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ +- WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ +- WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ +- WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ +-} WD_t; +- +-/* Start-up Time */ +-typedef enum SUT_enum +-{ +- SUT_0MS_gc = (0x03<<2), /* 0 ms */ +- SUT_4MS_gc = (0x01<<2), /* 4 ms */ +- SUT_64MS_gc = (0x00<<2), /* 64 ms */ +-} SUT_t; +- +-/* Brown Out Detection Voltage Level */ +-typedef enum BODLVL_enum +-{ +- BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ +- BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ +- BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ +- BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ +- BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ +- BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ +- BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ +-} BODLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-AC - Analog Comparator +--------------------------------------------------------------------------- +-*/ +- +-/* Analog Comparator */ +-typedef struct AC_struct +-{ +- register8_t AC0CTRL; /* Comparator 0 Control */ +- register8_t AC1CTRL; /* Comparator 1 Control */ +- register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ +- register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t WINCTRL; /* Window Mode Control */ +- register8_t STATUS; /* Status */ +-} AC_t; +- +-/* Interrupt mode */ +-typedef enum AC_INTMODE_enum +-{ +- AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ +- AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ +- AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ +-} AC_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum AC_INTLVL_enum +-{ +- AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ +- AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ +- AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ +- AC_INTLVL_HI_gc = (0x03<<4), /* High level */ +-} AC_INTLVL_t; +- +-/* Hysteresis mode selection */ +-typedef enum AC_HYSMODE_enum +-{ +- AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ +- AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ +- AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ +-} AC_HYSMODE_t; +- +-/* Positive input multiplexer selection */ +-typedef enum AC_MUXPOS_enum +-{ +- AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ +- AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ +- AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ +- AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ +- AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ +- AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ +- AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ +- AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ +-} AC_MUXPOS_t; +- +-/* Negative input multiplexer selection */ +-typedef enum AC_MUXNEG_enum +-{ +- AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ +- AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ +- AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ +- AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ +- AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ +- AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ +- AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ +- AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ +-} AC_MUXNEG_t; +- +-/* Windows interrupt mode */ +-typedef enum AC_WINTMODE_enum +-{ +- AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ +- AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ +- AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ +- AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ +-} AC_WINTMODE_t; +- +-/* Window interrupt level */ +-typedef enum AC_WINTLVL_enum +-{ +- AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ +- AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ +- AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ +-} AC_WINTLVL_t; +- +-/* Window mode state */ +-typedef enum AC_WSTATE_enum +-{ +- AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ +- AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ +- AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ +-} AC_WSTATE_t; +- +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* ADC Channel */ +-typedef struct ADC_CH_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t MUXCTRL; /* MUX Control */ +- register8_t INTCTRL; /* Channel Interrupt Control */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- _WORDREGISTER(RES); /* Channel Result */ +- register8_t reserved_0x6; +- register8_t reserved_0x7; +-} ADC_CH_t; +- +-/* +--------------------------------------------------------------------------- +-ADC - Analog/Digital Converter +--------------------------------------------------------------------------- +-*/ +- +-/* Analog-to-Digital Converter */ +-typedef struct ADC_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t REFCTRL; /* Reference Control */ +- register8_t EVCTRL; /* Event Control */ +- register8_t PRESCALER; /* Clock Prescaler */ +- register8_t reserved_0x05; +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t reserved_0x07; +- register8_t reserved_0x08; +- register8_t reserved_0x09; +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- _WORDREGISTER(CAL); /* Calibration Value */ +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- _WORDREGISTER(CH0RES); /* Channel 0 Result */ +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- _WORDREGISTER(CMP); /* Compare Value */ +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- ADC_CH_t CH0; /* ADC Channel 0 */ +-} ADC_t; +- +-/* Positive input multiplexer selection */ +-typedef enum ADC_CH_MUXPOS_enum +-{ +- ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ +- ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ +- ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ +- ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ +- ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ +- ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ +- ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ +- ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ +-} ADC_CH_MUXPOS_t; +- +-/* Internal input multiplexer selections */ +-typedef enum ADC_CH_MUXINT_enum +-{ +- ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ +- ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ +- ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ +- ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ +-} ADC_CH_MUXINT_t; +- +-/* Negative input multiplexer selection */ +-typedef enum ADC_CH_MUXNEG_enum +-{ +- ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ +- ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ +- ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ +- ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ +- ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ +- ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ +- ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ +- ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ +-} ADC_CH_MUXNEG_t; +- +-/* Input mode */ +-typedef enum ADC_CH_INPUTMODE_enum +-{ +- ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ +- ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ +- ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ +- ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ +-} ADC_CH_INPUTMODE_t; +- +-/* Gain factor */ +-typedef enum ADC_CH_GAIN_enum +-{ +- ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ +- ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ +- ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ +- ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ +- ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ +- ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ +- ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ +-} ADC_CH_GAIN_t; +- +-/* Conversion result resolution */ +-typedef enum ADC_RESOLUTION_enum +-{ +- ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ +- ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ +- ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ +-} ADC_RESOLUTION_t; +- +-/* Voltage reference selection */ +-typedef enum ADC_REFSEL_enum +-{ +- ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ +- ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ +- ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ +- ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ +-} ADC_REFSEL_t; +- +-/* Channel sweep selection */ +-typedef enum ADC_SWEEP_enum +-{ +- ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ +-} ADC_SWEEP_t; +- +-/* Event channel input selection */ +-typedef enum ADC_EVSEL_enum +-{ +- ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ +- ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ +- ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ +- ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ +- ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ +- ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ +- ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ +- ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ +-} ADC_EVSEL_t; +- +-/* Event action selection */ +-typedef enum ADC_EVACT_enum +-{ +- ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ +- ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ +-} ADC_EVACT_t; +- +-/* Interupt mode */ +-typedef enum ADC_CH_INTMODE_enum +-{ +- ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ +- ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ +- ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ +-} ADC_CH_INTMODE_t; +- +-/* Interrupt level */ +-typedef enum ADC_CH_INTLVL_enum +-{ +- ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ +- ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ +- ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ +- ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ +-} ADC_CH_INTLVL_t; +- +-/* Clock prescaler */ +-typedef enum ADC_PRESCALER_enum +-{ +- ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ +- ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ +- ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ +- ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ +- ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ +- ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ +- ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ +- ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ +-} ADC_PRESCALER_t; +- +- +-/* +--------------------------------------------------------------------------- +-RTC - Real-Time Clounter +--------------------------------------------------------------------------- +-*/ +- +-/* Real-Time Counter */ +-typedef struct RTC_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INTFLAGS; /* Interrupt Flags */ +- register8_t TEMP; /* Temporary register */ +- register8_t reserved_0x05; +- register8_t reserved_0x06; +- register8_t reserved_0x07; +- _WORDREGISTER(CNT); /* Count Register */ +- _WORDREGISTER(PER); /* Period Register */ +- _WORDREGISTER(COMP); /* Compare Register */ +-} RTC_t; +- +-/* Prescaler Factor */ +-typedef enum RTC_PRESCALER_enum +-{ +- RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ +- RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ +- RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ +- RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ +- RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ +- RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ +- RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ +- RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ +-} RTC_PRESCALER_t; +- +-/* Compare Interrupt level */ +-typedef enum RTC_COMPINTLVL_enum +-{ +- RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} RTC_COMPINTLVL_t; +- +-/* Overflow Interrupt level */ +-typedef enum RTC_OVFINTLVL_enum +-{ +- RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} RTC_OVFINTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* EBI Chip Select Module */ +-typedef struct EBI_CS_struct +-{ +- register8_t CTRLA; /* Chip Select Control Register A */ +- register8_t CTRLB; /* Chip Select Control Register B */ +- _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ +-} EBI_CS_t; +- +-/* +--------------------------------------------------------------------------- +-EBI - External Bus Interface +--------------------------------------------------------------------------- +-*/ +- +-/* External Bus Interface */ +-typedef struct EBI_struct +-{ +- register8_t CTRL; /* Control */ +- register8_t SDRAMCTRLA; /* SDRAM Control Register A */ +- register8_t reserved_0x02; +- register8_t reserved_0x03; +- _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ +- _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ +- register8_t SDRAMCTRLB; /* SDRAM Control Register B */ +- register8_t SDRAMCTRLC; /* SDRAM Control Register C */ +- register8_t reserved_0x0A; +- register8_t reserved_0x0B; +- register8_t reserved_0x0C; +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- EBI_CS_t CS0; /* Chip Select 0 */ +- EBI_CS_t CS1; /* Chip Select 1 */ +- EBI_CS_t CS2; /* Chip Select 2 */ +- EBI_CS_t CS3; /* Chip Select 3 */ +-} EBI_t; +- +-/* Chip Select adress space */ +-typedef enum EBI_CS_ASIZE_enum +-{ +- EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ +- EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ +- EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ +- EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ +- EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ +- EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ +- EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ +- EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ +- EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ +- EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ +- EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ +- EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ +- EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ +- EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ +- EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ +- EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ +- EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ +-} EBI_CS_ASIZE_t; +- +-/* */ +-typedef enum EBI_CS_SRWS_enum +-{ +- EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_CS_SRWS_t; +- +-/* Chip Select address mode */ +-typedef enum EBI_CS_MODE_enum +-{ +- EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ +- EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ +- EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ +- EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ +-} EBI_CS_MODE_t; +- +-/* Chip Select SDRAM mode */ +-typedef enum EBI_CS_SDMODE_enum +-{ +- EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ +- EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ +-} EBI_CS_SDMODE_t; +- +-/* */ +-typedef enum EBI_SDDATAW_enum +-{ +- EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ +- EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ +-} EBI_SDDATAW_t; +- +-/* */ +-typedef enum EBI_LPCMODE_enum +-{ +- EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ +- EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ +-} EBI_LPCMODE_t; +- +-/* */ +-typedef enum EBI_SRMODE_enum +-{ +- EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ +- EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ +- EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ +- EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ +-} EBI_SRMODE_t; +- +-/* */ +-typedef enum EBI_IFMODE_enum +-{ +- EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ +- EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ +- EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ +- EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ +-} EBI_IFMODE_t; +- +-/* */ +-typedef enum EBI_SDCOL_enum +-{ +- EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ +- EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ +- EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ +- EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ +-} EBI_SDCOL_t; +- +-/* */ +-typedef enum EBI_MRDLY_enum +-{ +- EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_MRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCYCDLY_enum +-{ +- EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ROWCYCDLY_t; +- +-/* */ +-typedef enum EBI_RPDLY_enum +-{ +- EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_RPDLY_t; +- +-/* */ +-typedef enum EBI_WRDLY_enum +-{ +- EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ +- EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ +- EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ +- EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ +-} EBI_WRDLY_t; +- +-/* */ +-typedef enum EBI_ESRDLY_enum +-{ +- EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ +- EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ +- EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ +- EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ +- EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ +- EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ +- EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ +- EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ +-} EBI_ESRDLY_t; +- +-/* */ +-typedef enum EBI_ROWCOLDLY_enum +-{ +- EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ +- EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ +- EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ +- EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ +- EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ +- EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ +- EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ +- EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ +-} EBI_ROWCOLDLY_t; +- +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_MASTER_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t STATUS; /* Status Register */ +- register8_t BAUD; /* Baurd Rate Control Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +-} TWI_MASTER_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* */ +-typedef struct TWI_SLAVE_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t STATUS; /* Status Register */ +- register8_t ADDR; /* Address Register */ +- register8_t DATA; /* Data Register */ +- register8_t ADDRMASK; /* Address Mask Register */ +-} TWI_SLAVE_t; +- +-/* +--------------------------------------------------------------------------- +-TWI - Two-Wire Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Two-Wire Interface */ +-typedef struct TWI_struct +-{ +- register8_t CTRL; /* TWI Common Control Register */ +- TWI_MASTER_t MASTER; /* TWI master module */ +- TWI_SLAVE_t SLAVE; /* TWI slave module */ +-} TWI_t; +- +-/* Master Interrupt Level */ +-typedef enum TWI_MASTER_INTLVL_enum +-{ +- TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_MASTER_INTLVL_t; +- +-/* Inactive Timeout */ +-typedef enum TWI_MASTER_TIMEOUT_enum +-{ +- TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ +- TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ +- TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ +- TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ +-} TWI_MASTER_TIMEOUT_t; +- +-/* Master Command */ +-typedef enum TWI_MASTER_CMD_enum +-{ +- TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ +- TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ +- TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ +-} TWI_MASTER_CMD_t; +- +-/* Master Bus State */ +-typedef enum TWI_MASTER_BUSSTATE_enum +-{ +- TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ +- TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ +- TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ +- TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ +-} TWI_MASTER_BUSSTATE_t; +- +-/* Slave Interrupt Level */ +-typedef enum TWI_SLAVE_INTLVL_enum +-{ +- TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TWI_SLAVE_INTLVL_t; +- +-/* Slave Command */ +-typedef enum TWI_SLAVE_CMD_enum +-{ +- TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ +- TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ +- TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ +-} TWI_SLAVE_CMD_t; +- +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O port Configuration */ +-typedef struct PORTCFG_struct +-{ +- register8_t MPCMASK; /* Multi-pin Configuration Mask */ +- register8_t reserved_0x01; +- register8_t VPCTRLA; /* Virtual Port Control Register A */ +- register8_t VPCTRLB; /* Virtual Port Control Register B */ +- register8_t CLKEVOUT; /* Clock and Event Out Register */ +-} PORTCFG_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* Virtual Port */ +-typedef struct VPORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t OUT; /* I/O Port Output */ +- register8_t IN; /* I/O Port Input */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +-} VPORT_t; +- +-/* +--------------------------------------------------------------------------- +-PORT - Port Configuration +--------------------------------------------------------------------------- +-*/ +- +-/* I/O Ports */ +-typedef struct PORT_struct +-{ +- register8_t DIR; /* I/O Port Data Direction */ +- register8_t DIRSET; /* I/O Port Data Direction Set */ +- register8_t DIRCLR; /* I/O Port Data Direction Clear */ +- register8_t DIRTGL; /* I/O Port Data Direction Toggle */ +- register8_t OUT; /* I/O Port Output */ +- register8_t OUTSET; /* I/O Port Output Set */ +- register8_t OUTCLR; /* I/O Port Output Clear */ +- register8_t OUTTGL; /* I/O Port Output Toggle */ +- register8_t IN; /* I/O port Input */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t INT0MASK; /* Port Interrupt 0 Mask */ +- register8_t INT1MASK; /* Port Interrupt 1 Mask */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t reserved_0x0F; +- register8_t PIN0CTRL; /* Pin 0 Control Register */ +- register8_t PIN1CTRL; /* Pin 1 Control Register */ +- register8_t PIN2CTRL; /* Pin 2 Control Register */ +- register8_t PIN3CTRL; /* Pin 3 Control Register */ +- register8_t PIN4CTRL; /* Pin 4 Control Register */ +- register8_t PIN5CTRL; /* Pin 5 Control Register */ +- register8_t PIN6CTRL; /* Pin 6 Control Register */ +- register8_t PIN7CTRL; /* Pin 7 Control Register */ +-} PORT_t; +- +-/* Virtual Port 0 Mapping */ +-typedef enum PORTCFG_VP0MAP_enum +-{ +- PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP0MAP_t; +- +-/* Virtual Port 1 Mapping */ +-typedef enum PORTCFG_VP1MAP_enum +-{ +- PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP1MAP_t; +- +-/* Virtual Port 2 Mapping */ +-typedef enum PORTCFG_VP2MAP_enum +-{ +- PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ +- PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ +- PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ +- PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ +- PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ +- PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ +- PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ +- PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ +- PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ +- PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ +- PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ +- PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ +- PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ +- PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ +- PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ +- PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ +-} PORTCFG_VP2MAP_t; +- +-/* Virtual Port 3 Mapping */ +-typedef enum PORTCFG_VP3MAP_enum +-{ +- PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ +- PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ +- PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ +- PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ +- PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ +- PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ +- PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ +- PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ +- PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ +- PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ +- PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ +- PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ +- PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ +- PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ +- PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ +- PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ +-} PORTCFG_VP3MAP_t; +- +-/* Clock Output Port */ +-typedef enum PORTCFG_CLKOUT_enum +-{ +- PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ +- PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ +- PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ +- PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ +-} PORTCFG_CLKOUT_t; +- +-/* Event Output Port */ +-typedef enum PORTCFG_EVOUT_enum +-{ +- PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ +- PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ +- PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ +- PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ +-} PORTCFG_EVOUT_t; +- +-/* Port Interrupt 0 Level */ +-typedef enum PORT_INT0LVL_enum +-{ +- PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ +- PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ +- PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ +-} PORT_INT0LVL_t; +- +-/* Port Interrupt 1 Level */ +-typedef enum PORT_INT1LVL_enum +-{ +- PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ +- PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ +- PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ +-} PORT_INT1LVL_t; +- +-/* Output/Pull Configuration */ +-typedef enum PORT_OPC_enum +-{ +- PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ +- PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ +- PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ +- PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ +- PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ +- PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ +- PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ +- PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ +-} PORT_OPC_t; +- +-/* Input/Sense Configuration */ +-typedef enum PORT_ISC_enum +-{ +- PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ +- PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ +- PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ +- PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ +- PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ +-} PORT_ISC_t; +- +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 0 */ +-typedef struct TC0_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- _WORDREGISTER(CCC); /* Compare or Capture C */ +- _WORDREGISTER(CCD); /* Compare or Capture D */ +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +- _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ +- _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ +-} TC0_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* 16-bit Timer/Counter 1 */ +-typedef struct TC1_struct +-{ +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control register C */ +- register8_t CTRLD; /* Control Register D */ +- register8_t CTRLE; /* Control Register E */ +- register8_t reserved_0x05; +- register8_t INTCTRLA; /* Interrupt Control Register A */ +- register8_t INTCTRLB; /* Interrupt Control Register B */ +- register8_t CTRLFCLR; /* Control Register F Clear */ +- register8_t CTRLFSET; /* Control Register F Set */ +- register8_t CTRLGCLR; /* Control Register G Clear */ +- register8_t CTRLGSET; /* Control Register G Set */ +- register8_t INTFLAGS; /* Interrupt Flag Register */ +- register8_t reserved_0x0D; +- register8_t reserved_0x0E; +- register8_t TEMP; /* Temporary Register For 16-bit Access */ +- register8_t reserved_0x10; +- register8_t reserved_0x11; +- register8_t reserved_0x12; +- register8_t reserved_0x13; +- register8_t reserved_0x14; +- register8_t reserved_0x15; +- register8_t reserved_0x16; +- register8_t reserved_0x17; +- register8_t reserved_0x18; +- register8_t reserved_0x19; +- register8_t reserved_0x1A; +- register8_t reserved_0x1B; +- register8_t reserved_0x1C; +- register8_t reserved_0x1D; +- register8_t reserved_0x1E; +- register8_t reserved_0x1F; +- _WORDREGISTER(CNT); /* Count */ +- register8_t reserved_0x22; +- register8_t reserved_0x23; +- register8_t reserved_0x24; +- register8_t reserved_0x25; +- _WORDREGISTER(PER); /* Period */ +- _WORDREGISTER(CCA); /* Compare or Capture A */ +- _WORDREGISTER(CCB); /* Compare or Capture B */ +- register8_t reserved_0x2C; +- register8_t reserved_0x2D; +- register8_t reserved_0x2E; +- register8_t reserved_0x2F; +- register8_t reserved_0x30; +- register8_t reserved_0x31; +- register8_t reserved_0x32; +- register8_t reserved_0x33; +- register8_t reserved_0x34; +- register8_t reserved_0x35; +- _WORDREGISTER(PERBUF); /* Period Buffer */ +- _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ +- _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ +-} TC1_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* Advanced Waveform Extension */ +-typedef struct AWEX_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t reserved_0x01; +- register8_t FDEMASK; /* Fault Detection Event Mask */ +- register8_t FDCTRL; /* Fault Detection Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x05; +- register8_t DTBOTH; /* Dead Time Both Sides */ +- register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ +- register8_t DTLS; /* Dead Time Low Side */ +- register8_t DTHS; /* Dead Time High Side */ +- register8_t DTLSBUF; /* Dead Time Low Side Buffer */ +- register8_t DTHSBUF; /* Dead Time High Side Buffer */ +- register8_t OUTOVEN; /* Output Override Enable */ +-} AWEX_t; +- +-/* +--------------------------------------------------------------------------- +-TC - 16-bit Timer/Counter With PWM +--------------------------------------------------------------------------- +-*/ +- +-/* High-Resolution Extension */ +-typedef struct HIRES_struct +-{ +- register8_t CTRLA; /* Control Register */ +-} HIRES_t; +- +-/* Clock Selection */ +-typedef enum TC_CLKSEL_enum +-{ +- TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ +- TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ +- TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ +- TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ +- TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ +- TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ +- TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ +- TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ +- TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_CLKSEL_t; +- +-/* Waveform Generation Mode */ +-typedef enum TC_WGMODE_enum +-{ +- TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ +- TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ +- TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ +- TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ +- TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ +- TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ +-} TC_WGMODE_t; +- +-/* Event Action */ +-typedef enum TC_EVACT_enum +-{ +- TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ +- TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ +- TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ +- TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ +- TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ +- TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ +- TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ +-} TC_EVACT_t; +- +-/* Event Selection */ +-typedef enum TC_EVSEL_enum +-{ +- TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ +- TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ +- TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ +- TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ +- TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ +- TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ +- TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ +- TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ +-} TC_EVSEL_t; +- +-/* Error Interrupt Level */ +-typedef enum TC_ERRINTLVL_enum +-{ +- TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_ERRINTLVL_t; +- +-/* Overflow Interrupt Level */ +-typedef enum TC_OVFINTLVL_enum +-{ +- TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_OVFINTLVL_t; +- +-/* Compare or Capture D Interrupt Level */ +-typedef enum TC_CCDINTLVL_enum +-{ +- TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ +- TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ +- TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ +- TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ +-} TC_CCDINTLVL_t; +- +-/* Compare or Capture C Interrupt Level */ +-typedef enum TC_CCCINTLVL_enum +-{ +- TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} TC_CCCINTLVL_t; +- +-/* Compare or Capture B Interrupt Level */ +-typedef enum TC_CCBINTLVL_enum +-{ +- TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} TC_CCBINTLVL_t; +- +-/* Compare or Capture A Interrupt Level */ +-typedef enum TC_CCAINTLVL_enum +-{ +- TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} TC_CCAINTLVL_t; +- +-/* Timer/Counter Command */ +-typedef enum TC_CMD_enum +-{ +- TC_CMD_NONE_gc = (0x00<<2), /* No Command */ +- TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ +- TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ +- TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ +-} TC_CMD_t; +- +-/* Fault Detect Action */ +-typedef enum AWEX_FDACT_enum +-{ +- AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ +- AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ +- AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ +-} AWEX_FDACT_t; +- +-/* High Resolution Enable */ +-typedef enum HIRES_HREN_enum +-{ +- HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ +- HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ +- HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ +- HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ +-} HIRES_HREN_t; +- +- +-/* +--------------------------------------------------------------------------- +-USART - Universal Asynchronous Receiver-Transmitter +--------------------------------------------------------------------------- +-*/ +- +-/* Universal Synchronous/Asynchronous Receiver/Transmitter */ +-typedef struct USART_struct +-{ +- register8_t DATA; /* Data Register */ +- register8_t STATUS; /* Status Register */ +- register8_t reserved_0x02; +- register8_t CTRLA; /* Control Register A */ +- register8_t CTRLB; /* Control Register B */ +- register8_t CTRLC; /* Control Register C */ +- register8_t BAUDCTRLA; /* Baud Rate Control Register A */ +- register8_t BAUDCTRLB; /* Baud Rate Control Register B */ +-} USART_t; +- +-/* Receive Complete Interrupt level */ +-typedef enum USART_RXCINTLVL_enum +-{ +- USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ +- USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ +- USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ +- USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ +-} USART_RXCINTLVL_t; +- +-/* Transmit Complete Interrupt level */ +-typedef enum USART_TXCINTLVL_enum +-{ +- USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ +- USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ +- USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ +- USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ +-} USART_TXCINTLVL_t; +- +-/* Data Register Empty Interrupt level */ +-typedef enum USART_DREINTLVL_enum +-{ +- USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ +- USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ +-} USART_DREINTLVL_t; +- +-/* Character Size */ +-typedef enum USART_CHSIZE_enum +-{ +- USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ +- USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ +- USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ +- USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ +- USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ +-} USART_CHSIZE_t; +- +-/* Communication Mode */ +-typedef enum USART_CMODE_enum +-{ +- USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ +- USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ +- USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ +- USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ +-} USART_CMODE_t; +- +-/* Parity Mode */ +-typedef enum USART_PMODE_enum +-{ +- USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ +- USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ +- USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ +-} USART_PMODE_t; +- +- +-/* +--------------------------------------------------------------------------- +-SPI - Serial Peripheral Interface +--------------------------------------------------------------------------- +-*/ +- +-/* Serial Peripheral Interface */ +-typedef struct SPI_struct +-{ +- register8_t CTRL; /* Control Register */ +- register8_t INTCTRL; /* Interrupt Control Register */ +- register8_t STATUS; /* Status Register */ +- register8_t DATA; /* Data Register */ +-} SPI_t; +- +-/* SPI Mode */ +-typedef enum SPI_MODE_enum +-{ +- SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ +- SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ +- SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ +- SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ +-} SPI_MODE_t; +- +-/* Prescaler setting */ +-typedef enum SPI_PRESCALER_enum +-{ +- SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ +- SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ +- SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ +- SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ +-} SPI_PRESCALER_t; +- +-/* Interrupt level */ +-typedef enum SPI_INTLVL_enum +-{ +- SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ +- SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ +- SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ +- SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ +-} SPI_INTLVL_t; +- +- +-/* +--------------------------------------------------------------------------- +-IRCOM - IR Communication Module +--------------------------------------------------------------------------- +-*/ +- +-/* IR Communication Module */ +-typedef struct IRCOM_struct +-{ +- register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ +- register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ +- register8_t CTRL; /* Control Register */ +-} IRCOM_t; +- +-/* Event channel selection */ +-typedef enum IRDA_EVSEL_enum +-{ +- IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ +- IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ +- IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ +- IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ +- IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ +- IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ +- IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ +- IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ +- IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ +-} IRDA_EVSEL_t; +- +- +- +-/* +-========================================================================== +-IO Module Instances. Mapped to memory. +-========================================================================== +-*/ +- +-#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ +-#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ +-#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ +-#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ +-#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ +-#define CLK (*(CLK_t *) 0x0040) /* Clock System */ +-#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ +-#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ +-#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ +-#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ +-#define PR (*(PR_t *) 0x0070) /* Power Reduction */ +-#define RST (*(RST_t *) 0x0078) /* Reset Controller */ +-#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ +-#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ +-#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ +-#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ +-#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ +-#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ +-#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ +-#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ +-#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ +-#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ +-#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ +-#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ +-#define PORTA (*(PORT_t *) 0x0600) /* Port A */ +-#define PORTB (*(PORT_t *) 0x0620) /* Port B */ +-#define PORTC (*(PORT_t *) 0x0640) /* Port C */ +-#define PORTD (*(PORT_t *) 0x0660) /* Port D */ +-#define PORTE (*(PORT_t *) 0x0680) /* Port E */ +-#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ +-#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ +-#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ +-#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ +-#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ +-#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ +-#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ +-#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ +-#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ +-#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ +-#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ +-#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ +-#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ +-#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ +-#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ +-#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ +-#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ +- +- +-#endif /* !defined (__ASSEMBLER__) */ +- +- +-/* ========== Flattened fully qualified IO register names ========== */ +- +-/* GPIO - General Purpose IO Registers */ +-#define GPIO_GPIOR0 _SFR_MEM8(0x0000) +-#define GPIO_GPIOR1 _SFR_MEM8(0x0001) +-#define GPIO_GPIOR2 _SFR_MEM8(0x0002) +-#define GPIO_GPIOR3 _SFR_MEM8(0x0003) +-#define GPIO_GPIOR4 _SFR_MEM8(0x0004) +-#define GPIO_GPIOR5 _SFR_MEM8(0x0005) +-#define GPIO_GPIOR6 _SFR_MEM8(0x0006) +-#define GPIO_GPIOR7 _SFR_MEM8(0x0007) +-#define GPIO_GPIOR8 _SFR_MEM8(0x0008) +-#define GPIO_GPIOR9 _SFR_MEM8(0x0009) +-#define GPIO_GPIORA _SFR_MEM8(0x000A) +-#define GPIO_GPIORB _SFR_MEM8(0x000B) +-#define GPIO_GPIORC _SFR_MEM8(0x000C) +-#define GPIO_GPIORD _SFR_MEM8(0x000D) +-#define GPIO_GPIORE _SFR_MEM8(0x000E) +-#define GPIO_GPIORF _SFR_MEM8(0x000F) +- +-/* VPORT0 - Virtual Port 0 */ +-#define VPORT0_DIR _SFR_MEM8(0x0010) +-#define VPORT0_OUT _SFR_MEM8(0x0011) +-#define VPORT0_IN _SFR_MEM8(0x0012) +-#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) +- +-/* VPORT1 - Virtual Port 1 */ +-#define VPORT1_DIR _SFR_MEM8(0x0014) +-#define VPORT1_OUT _SFR_MEM8(0x0015) +-#define VPORT1_IN _SFR_MEM8(0x0016) +-#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) +- +-/* VPORT2 - Virtual Port 2 */ +-#define VPORT2_DIR _SFR_MEM8(0x0018) +-#define VPORT2_OUT _SFR_MEM8(0x0019) +-#define VPORT2_IN _SFR_MEM8(0x001A) +-#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) +- +-/* VPORT3 - Virtual Port 3 */ +-#define VPORT3_DIR _SFR_MEM8(0x001C) +-#define VPORT3_OUT _SFR_MEM8(0x001D) +-#define VPORT3_IN _SFR_MEM8(0x001E) +-#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) +- +-/* OCD - On-Chip Debug System */ +-#define OCD_OCDR0 _SFR_MEM8(0x002E) +-#define OCD_OCDR1 _SFR_MEM8(0x002F) +- +-/* CPU - CPU Registers */ +-#define CPU_CCP _SFR_MEM8(0x0034) +-#define CPU_RAMPD _SFR_MEM8(0x0038) +-#define CPU_RAMPX _SFR_MEM8(0x0039) +-#define CPU_RAMPY _SFR_MEM8(0x003A) +-#define CPU_RAMPZ _SFR_MEM8(0x003B) +-#define CPU_EIND _SFR_MEM8(0x003C) +-#define CPU_SPL _SFR_MEM8(0x003D) +-#define CPU_SPH _SFR_MEM8(0x003E) +-#define CPU_SREG _SFR_MEM8(0x003F) +- +-/* CLK - Clock System */ +-#define CLK_CTRL _SFR_MEM8(0x0040) +-#define CLK_PSCTRL _SFR_MEM8(0x0041) +-#define CLK_LOCK _SFR_MEM8(0x0042) +-#define CLK_RTCCTRL _SFR_MEM8(0x0043) +- +-/* SLEEP - Sleep Controller */ +-#define SLEEP_CTRL _SFR_MEM8(0x0048) +- +-/* OSC - Oscillator Control */ +-#define OSC_CTRL _SFR_MEM8(0x0050) +-#define OSC_STATUS _SFR_MEM8(0x0051) +-#define OSC_XOSCCTRL _SFR_MEM8(0x0052) +-#define OSC_XOSCFAIL _SFR_MEM8(0x0053) +-#define OSC_RC32KCAL _SFR_MEM8(0x0054) +-#define OSC_PLLCTRL _SFR_MEM8(0x0055) +-#define OSC_DFLLCTRL _SFR_MEM8(0x0056) +- +-/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ +-#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) +-#define DFLLRC32M_CALA _SFR_MEM8(0x0062) +-#define DFLLRC32M_CALB _SFR_MEM8(0x0063) +-#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) +-#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) +-#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) +- +-/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ +-#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) +-#define DFLLRC2M_CALA _SFR_MEM8(0x006A) +-#define DFLLRC2M_CALB _SFR_MEM8(0x006B) +-#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) +-#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) +-#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) +- +-/* PR - Power Reduction */ +-#define PR_PRGEN _SFR_MEM8(0x0070) +-#define PR_PRPA _SFR_MEM8(0x0071) +-#define PR_PRPB _SFR_MEM8(0x0072) +-#define PR_PRPC _SFR_MEM8(0x0073) +-#define PR_PRPD _SFR_MEM8(0x0074) +-#define PR_PRPE _SFR_MEM8(0x0075) +-#define PR_PRPF _SFR_MEM8(0x0076) +- +-/* RST - Reset Controller */ +-#define RST_STATUS _SFR_MEM8(0x0078) +-#define RST_CTRL _SFR_MEM8(0x0079) +- +-/* WDT - Watch-Dog Timer */ +-#define WDT_CTRL _SFR_MEM8(0x0080) +-#define WDT_WINCTRL _SFR_MEM8(0x0081) +-#define WDT_STATUS _SFR_MEM8(0x0082) +- +-/* MCU - MCU Control */ +-#define MCU_DEVID0 _SFR_MEM8(0x0090) +-#define MCU_DEVID1 _SFR_MEM8(0x0091) +-#define MCU_DEVID2 _SFR_MEM8(0x0092) +-#define MCU_REVID _SFR_MEM8(0x0093) +-#define MCU_JTAGUID _SFR_MEM8(0x0094) +-#define MCU_MCUCR _SFR_MEM8(0x0096) +-#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) +-#define MCU_AWEXLOCK _SFR_MEM8(0x0099) +- +-/* PMIC - Programmable Interrupt Controller */ +-#define PMIC_STATUS _SFR_MEM8(0x00A0) +-#define PMIC_INTPRI _SFR_MEM8(0x00A1) +-#define PMIC_CTRL _SFR_MEM8(0x00A2) +- +-/* PORTCFG - Port Configuration */ +-#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) +-#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) +-#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) +-#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) +- +-/* EVSYS - Event System */ +-#define EVSYS_CH0MUX _SFR_MEM8(0x0180) +-#define EVSYS_CH1MUX _SFR_MEM8(0x0181) +-#define EVSYS_CH2MUX _SFR_MEM8(0x0182) +-#define EVSYS_CH3MUX _SFR_MEM8(0x0183) +-#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) +-#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) +-#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) +-#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) +-#define EVSYS_STROBE _SFR_MEM8(0x0190) +-#define EVSYS_DATA _SFR_MEM8(0x0191) +- +-/* NVM - Non Volatile Memory Controller */ +-#define NVM_ADDR0 _SFR_MEM8(0x01C0) +-#define NVM_ADDR1 _SFR_MEM8(0x01C1) +-#define NVM_ADDR2 _SFR_MEM8(0x01C2) +-#define NVM_DATA0 _SFR_MEM8(0x01C4) +-#define NVM_DATA1 _SFR_MEM8(0x01C5) +-#define NVM_DATA2 _SFR_MEM8(0x01C6) +-#define NVM_CMD _SFR_MEM8(0x01CA) +-#define NVM_CTRLA _SFR_MEM8(0x01CB) +-#define NVM_CTRLB _SFR_MEM8(0x01CC) +-#define NVM_INTCTRL _SFR_MEM8(0x01CD) +-#define NVM_STATUS _SFR_MEM8(0x01CF) +-#define NVM_LOCKBITS _SFR_MEM8(0x01D0) +- +-/* ADCA - Analog to Digital Converter A */ +-#define ADCA_CTRLA _SFR_MEM8(0x0200) +-#define ADCA_CTRLB _SFR_MEM8(0x0201) +-#define ADCA_REFCTRL _SFR_MEM8(0x0202) +-#define ADCA_EVCTRL _SFR_MEM8(0x0203) +-#define ADCA_PRESCALER _SFR_MEM8(0x0204) +-#define ADCA_INTFLAGS _SFR_MEM8(0x0206) +-#define ADCA_CAL _SFR_MEM16(0x020C) +-#define ADCA_CH0RES _SFR_MEM16(0x0210) +-#define ADCA_CMP _SFR_MEM16(0x0218) +-#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) +-#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) +-#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) +-#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) +-#define ADCA_CH0_RES _SFR_MEM16(0x0224) +- +-/* DACB - Digital to Analog Converter B */ +- +-/* ACA - Analog Comparator A */ +-#define ACA_AC0CTRL _SFR_MEM8(0x0380) +-#define ACA_AC1CTRL _SFR_MEM8(0x0381) +-#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) +-#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) +-#define ACA_CTRLA _SFR_MEM8(0x0384) +-#define ACA_CTRLB _SFR_MEM8(0x0385) +-#define ACA_WINCTRL _SFR_MEM8(0x0386) +-#define ACA_STATUS _SFR_MEM8(0x0387) +- +-/* ACB - Analog Comparator B */ +-#define ACB_AC0CTRL _SFR_MEM8(0x0390) +-#define ACB_AC1CTRL _SFR_MEM8(0x0391) +-#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) +-#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) +-#define ACB_CTRLA _SFR_MEM8(0x0394) +-#define ACB_CTRLB _SFR_MEM8(0x0395) +-#define ACB_WINCTRL _SFR_MEM8(0x0396) +-#define ACB_STATUS _SFR_MEM8(0x0397) +- +-/* RTC - Real-Time Counter */ +-#define RTC_CTRL _SFR_MEM8(0x0400) +-#define RTC_STATUS _SFR_MEM8(0x0401) +-#define RTC_INTCTRL _SFR_MEM8(0x0402) +-#define RTC_INTFLAGS _SFR_MEM8(0x0403) +-#define RTC_TEMP _SFR_MEM8(0x0404) +-#define RTC_CNT _SFR_MEM16(0x0408) +-#define RTC_PER _SFR_MEM16(0x040A) +-#define RTC_COMP _SFR_MEM16(0x040C) +- +-/* TWIC - Two-Wire Interface C */ +-#define TWIC_CTRL _SFR_MEM8(0x0480) +-#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0482) +-#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0483) +-#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0484) +-#define TWIC_MASTER_STATUS _SFR_MEM8(0x0485) +-#define TWIC_MASTER_BAUD _SFR_MEM8(0x0486) +-#define TWIC_MASTER_ADDR _SFR_MEM8(0x0487) +-#define TWIC_MASTER_DATA _SFR_MEM8(0x0488) +-#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) +-#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) +-#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) +-#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) +-#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) +-#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) +- +-/* PORTA - Port A */ +-#define PORTA_DIR _SFR_MEM8(0x0600) +-#define PORTA_DIRSET _SFR_MEM8(0x0601) +-#define PORTA_DIRCLR _SFR_MEM8(0x0602) +-#define PORTA_DIRTGL _SFR_MEM8(0x0603) +-#define PORTA_OUT _SFR_MEM8(0x0604) +-#define PORTA_OUTSET _SFR_MEM8(0x0605) +-#define PORTA_OUTCLR _SFR_MEM8(0x0606) +-#define PORTA_OUTTGL _SFR_MEM8(0x0607) +-#define PORTA_IN _SFR_MEM8(0x0608) +-#define PORTA_INTCTRL _SFR_MEM8(0x0609) +-#define PORTA_INT0MASK _SFR_MEM8(0x060A) +-#define PORTA_INT1MASK _SFR_MEM8(0x060B) +-#define PORTA_INTFLAGS _SFR_MEM8(0x060C) +-#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) +-#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) +-#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) +-#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) +-#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) +-#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) +-#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) +-#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) +- +-/* PORTB - Port B */ +-#define PORTB_DIR _SFR_MEM8(0x0620) +-#define PORTB_DIRSET _SFR_MEM8(0x0621) +-#define PORTB_DIRCLR _SFR_MEM8(0x0622) +-#define PORTB_DIRTGL _SFR_MEM8(0x0623) +-#define PORTB_OUT _SFR_MEM8(0x0624) +-#define PORTB_OUTSET _SFR_MEM8(0x0625) +-#define PORTB_OUTCLR _SFR_MEM8(0x0626) +-#define PORTB_OUTTGL _SFR_MEM8(0x0627) +-#define PORTB_IN _SFR_MEM8(0x0628) +-#define PORTB_INTCTRL _SFR_MEM8(0x0629) +-#define PORTB_INT0MASK _SFR_MEM8(0x062A) +-#define PORTB_INT1MASK _SFR_MEM8(0x062B) +-#define PORTB_INTFLAGS _SFR_MEM8(0x062C) +-#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) +-#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) +-#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) +-#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) +-#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) +-#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) +-#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) +-#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) +- +-/* PORTC - Port C */ +-#define PORTC_DIR _SFR_MEM8(0x0640) +-#define PORTC_DIRSET _SFR_MEM8(0x0641) +-#define PORTC_DIRCLR _SFR_MEM8(0x0642) +-#define PORTC_DIRTGL _SFR_MEM8(0x0643) +-#define PORTC_OUT _SFR_MEM8(0x0644) +-#define PORTC_OUTSET _SFR_MEM8(0x0645) +-#define PORTC_OUTCLR _SFR_MEM8(0x0646) +-#define PORTC_OUTTGL _SFR_MEM8(0x0647) +-#define PORTC_IN _SFR_MEM8(0x0648) +-#define PORTC_INTCTRL _SFR_MEM8(0x0649) +-#define PORTC_INT0MASK _SFR_MEM8(0x064A) +-#define PORTC_INT1MASK _SFR_MEM8(0x064B) +-#define PORTC_INTFLAGS _SFR_MEM8(0x064C) +-#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) +-#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) +-#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) +-#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) +-#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) +-#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) +-#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) +-#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) +- +-/* PORTD - Port D */ +-#define PORTD_DIR _SFR_MEM8(0x0660) +-#define PORTD_DIRSET _SFR_MEM8(0x0661) +-#define PORTD_DIRCLR _SFR_MEM8(0x0662) +-#define PORTD_DIRTGL _SFR_MEM8(0x0663) +-#define PORTD_OUT _SFR_MEM8(0x0664) +-#define PORTD_OUTSET _SFR_MEM8(0x0665) +-#define PORTD_OUTCLR _SFR_MEM8(0x0666) +-#define PORTD_OUTTGL _SFR_MEM8(0x0667) +-#define PORTD_IN _SFR_MEM8(0x0668) +-#define PORTD_INTCTRL _SFR_MEM8(0x0669) +-#define PORTD_INT0MASK _SFR_MEM8(0x066A) +-#define PORTD_INT1MASK _SFR_MEM8(0x066B) +-#define PORTD_INTFLAGS _SFR_MEM8(0x066C) +-#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) +-#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) +-#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) +-#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) +-#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) +-#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) +-#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) +-#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) +- +-/* PORTE - Port E */ +-#define PORTE_DIR _SFR_MEM8(0x0680) +-#define PORTE_DIRSET _SFR_MEM8(0x0681) +-#define PORTE_DIRCLR _SFR_MEM8(0x0682) +-#define PORTE_DIRTGL _SFR_MEM8(0x0683) +-#define PORTE_OUT _SFR_MEM8(0x0684) +-#define PORTE_OUTSET _SFR_MEM8(0x0685) +-#define PORTE_OUTCLR _SFR_MEM8(0x0686) +-#define PORTE_OUTTGL _SFR_MEM8(0x0687) +-#define PORTE_IN _SFR_MEM8(0x0688) +-#define PORTE_INTCTRL _SFR_MEM8(0x0689) +-#define PORTE_INT0MASK _SFR_MEM8(0x068A) +-#define PORTE_INT1MASK _SFR_MEM8(0x068B) +-#define PORTE_INTFLAGS _SFR_MEM8(0x068C) +-#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) +-#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) +-#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) +-#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) +-#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) +-#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) +-#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) +-#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) +- +-/* PORTF - Port F */ +-#define PORTF_DIR _SFR_MEM8(0x06A0) +-#define PORTF_DIRSET _SFR_MEM8(0x06A1) +-#define PORTF_DIRCLR _SFR_MEM8(0x06A2) +-#define PORTF_DIRTGL _SFR_MEM8(0x06A3) +-#define PORTF_OUT _SFR_MEM8(0x06A4) +-#define PORTF_OUTSET _SFR_MEM8(0x06A5) +-#define PORTF_OUTCLR _SFR_MEM8(0x06A6) +-#define PORTF_OUTTGL _SFR_MEM8(0x06A7) +-#define PORTF_IN _SFR_MEM8(0x06A8) +-#define PORTF_INTCTRL _SFR_MEM8(0x06A9) +-#define PORTF_INT0MASK _SFR_MEM8(0x06AA) +-#define PORTF_INT1MASK _SFR_MEM8(0x06AB) +-#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) +-#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) +-#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) +-#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) +-#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) +-#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) +-#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) +-#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) +-#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) +- +-/* PORTR - Port R */ +-#define PORTR_DIR _SFR_MEM8(0x07E0) +-#define PORTR_DIRSET _SFR_MEM8(0x07E1) +-#define PORTR_DIRCLR _SFR_MEM8(0x07E2) +-#define PORTR_DIRTGL _SFR_MEM8(0x07E3) +-#define PORTR_OUT _SFR_MEM8(0x07E4) +-#define PORTR_OUTSET _SFR_MEM8(0x07E5) +-#define PORTR_OUTCLR _SFR_MEM8(0x07E6) +-#define PORTR_OUTTGL _SFR_MEM8(0x07E7) +-#define PORTR_IN _SFR_MEM8(0x07E8) +-#define PORTR_INTCTRL _SFR_MEM8(0x07E9) +-#define PORTR_INT0MASK _SFR_MEM8(0x07EA) +-#define PORTR_INT1MASK _SFR_MEM8(0x07EB) +-#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) +-#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) +-#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) +-#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) +-#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) +-#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) +-#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) +-#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) +-#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) +- +-/* TCC0 - Timer/Counter C0 */ +-#define TCC0_CTRLA _SFR_MEM8(0x0800) +-#define TCC0_CTRLB _SFR_MEM8(0x0801) +-#define TCC0_CTRLC _SFR_MEM8(0x0802) +-#define TCC0_CTRLD _SFR_MEM8(0x0803) +-#define TCC0_CTRLE _SFR_MEM8(0x0804) +-#define TCC0_INTCTRLA _SFR_MEM8(0x0806) +-#define TCC0_INTCTRLB _SFR_MEM8(0x0807) +-#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) +-#define TCC0_CTRLFSET _SFR_MEM8(0x0809) +-#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) +-#define TCC0_CTRLGSET _SFR_MEM8(0x080B) +-#define TCC0_INTFLAGS _SFR_MEM8(0x080C) +-#define TCC0_TEMP _SFR_MEM8(0x080F) +-#define TCC0_CNT _SFR_MEM16(0x0820) +-#define TCC0_PER _SFR_MEM16(0x0826) +-#define TCC0_CCA _SFR_MEM16(0x0828) +-#define TCC0_CCB _SFR_MEM16(0x082A) +-#define TCC0_CCC _SFR_MEM16(0x082C) +-#define TCC0_CCD _SFR_MEM16(0x082E) +-#define TCC0_PERBUF _SFR_MEM16(0x0836) +-#define TCC0_CCABUF _SFR_MEM16(0x0838) +-#define TCC0_CCBBUF _SFR_MEM16(0x083A) +-#define TCC0_CCCBUF _SFR_MEM16(0x083C) +-#define TCC0_CCDBUF _SFR_MEM16(0x083E) +- +-/* TCC1 - Timer/Counter C1 */ +-#define TCC1_CTRLA _SFR_MEM8(0x0840) +-#define TCC1_CTRLB _SFR_MEM8(0x0841) +-#define TCC1_CTRLC _SFR_MEM8(0x0842) +-#define TCC1_CTRLD _SFR_MEM8(0x0843) +-#define TCC1_CTRLE _SFR_MEM8(0x0844) +-#define TCC1_INTCTRLA _SFR_MEM8(0x0846) +-#define TCC1_INTCTRLB _SFR_MEM8(0x0847) +-#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) +-#define TCC1_CTRLFSET _SFR_MEM8(0x0849) +-#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) +-#define TCC1_CTRLGSET _SFR_MEM8(0x084B) +-#define TCC1_INTFLAGS _SFR_MEM8(0x084C) +-#define TCC1_TEMP _SFR_MEM8(0x084F) +-#define TCC1_CNT _SFR_MEM16(0x0860) +-#define TCC1_PER _SFR_MEM16(0x0866) +-#define TCC1_CCA _SFR_MEM16(0x0868) +-#define TCC1_CCB _SFR_MEM16(0x086A) +-#define TCC1_PERBUF _SFR_MEM16(0x0876) +-#define TCC1_CCABUF _SFR_MEM16(0x0878) +-#define TCC1_CCBBUF _SFR_MEM16(0x087A) +- +-/* AWEXC - Advanced Waveform Extension C */ +-#define AWEXC_CTRL _SFR_MEM8(0x0880) +-#define AWEXC_FDEMASK _SFR_MEM8(0x0882) +-#define AWEXC_FDCTRL _SFR_MEM8(0x0883) +-#define AWEXC_STATUS _SFR_MEM8(0x0884) +-#define AWEXC_DTBOTH _SFR_MEM8(0x0886) +-#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) +-#define AWEXC_DTLS _SFR_MEM8(0x0888) +-#define AWEXC_DTHS _SFR_MEM8(0x0889) +-#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) +-#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) +-#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) +- +-/* HIRESC - High-Resolution Extension C */ +-#define HIRESC_CTRLA _SFR_MEM8(0x0890) +- +-/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ +-#define USARTC0_DATA _SFR_MEM8(0x08A0) +-#define USARTC0_STATUS _SFR_MEM8(0x08A1) +-#define USARTC0_CTRLA _SFR_MEM8(0x08A3) +-#define USARTC0_CTRLB _SFR_MEM8(0x08A4) +-#define USARTC0_CTRLC _SFR_MEM8(0x08A5) +-#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) +-#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) +- +-/* SPIC - Serial Peripheral Interface C */ +-#define SPIC_CTRL _SFR_MEM8(0x08C0) +-#define SPIC_INTCTRL _SFR_MEM8(0x08C1) +-#define SPIC_STATUS _SFR_MEM8(0x08C2) +-#define SPIC_DATA _SFR_MEM8(0x08C3) +- +-/* IRCOM - IR Communication Module */ +-#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F8) +-#define IRCOM_RXPLCTRL _SFR_MEM8(0x08F9) +-#define IRCOM_CTRL _SFR_MEM8(0x08FA) +- +-/* TCD0 - Timer/Counter D0 */ +-#define TCD0_CTRLA _SFR_MEM8(0x0900) +-#define TCD0_CTRLB _SFR_MEM8(0x0901) +-#define TCD0_CTRLC _SFR_MEM8(0x0902) +-#define TCD0_CTRLD _SFR_MEM8(0x0903) +-#define TCD0_CTRLE _SFR_MEM8(0x0904) +-#define TCD0_INTCTRLA _SFR_MEM8(0x0906) +-#define TCD0_INTCTRLB _SFR_MEM8(0x0907) +-#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) +-#define TCD0_CTRLFSET _SFR_MEM8(0x0909) +-#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) +-#define TCD0_CTRLGSET _SFR_MEM8(0x090B) +-#define TCD0_INTFLAGS _SFR_MEM8(0x090C) +-#define TCD0_TEMP _SFR_MEM8(0x090F) +-#define TCD0_CNT _SFR_MEM16(0x0920) +-#define TCD0_PER _SFR_MEM16(0x0926) +-#define TCD0_CCA _SFR_MEM16(0x0928) +-#define TCD0_CCB _SFR_MEM16(0x092A) +-#define TCD0_CCC _SFR_MEM16(0x092C) +-#define TCD0_CCD _SFR_MEM16(0x092E) +-#define TCD0_PERBUF _SFR_MEM16(0x0936) +-#define TCD0_CCABUF _SFR_MEM16(0x0938) +-#define TCD0_CCBBUF _SFR_MEM16(0x093A) +-#define TCD0_CCCBUF _SFR_MEM16(0x093C) +-#define TCD0_CCDBUF _SFR_MEM16(0x093E) +- +-/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ +-#define USARTD0_DATA _SFR_MEM8(0x09A0) +-#define USARTD0_STATUS _SFR_MEM8(0x09A1) +-#define USARTD0_CTRLA _SFR_MEM8(0x09A3) +-#define USARTD0_CTRLB _SFR_MEM8(0x09A4) +-#define USARTD0_CTRLC _SFR_MEM8(0x09A5) +-#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) +-#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) +- +-/* SPID - Serial Peripheral Interface D */ +-#define SPID_CTRL _SFR_MEM8(0x09C0) +-#define SPID_INTCTRL _SFR_MEM8(0x09C1) +-#define SPID_STATUS _SFR_MEM8(0x09C2) +-#define SPID_DATA _SFR_MEM8(0x09C3) +- +-/* TCE0 - Timer/Counter E0 */ +-#define TCE0_CTRLA _SFR_MEM8(0x0A00) +-#define TCE0_CTRLB _SFR_MEM8(0x0A01) +-#define TCE0_CTRLC _SFR_MEM8(0x0A02) +-#define TCE0_CTRLD _SFR_MEM8(0x0A03) +-#define TCE0_CTRLE _SFR_MEM8(0x0A04) +-#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) +-#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) +-#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) +-#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) +-#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) +-#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) +-#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) +-#define TCE0_TEMP _SFR_MEM8(0x0A0F) +-#define TCE0_CNT _SFR_MEM16(0x0A20) +-#define TCE0_PER _SFR_MEM16(0x0A26) +-#define TCE0_CCA _SFR_MEM16(0x0A28) +-#define TCE0_CCB _SFR_MEM16(0x0A2A) +-#define TCE0_CCC _SFR_MEM16(0x0A2C) +-#define TCE0_CCD _SFR_MEM16(0x0A2E) +-#define TCE0_PERBUF _SFR_MEM16(0x0A36) +-#define TCE0_CCABUF _SFR_MEM16(0x0A38) +-#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) +-#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) +-#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) +- +-/* AWEXE - Advanced Waveform Extension E */ +-#define AWEXE_CTRL _SFR_MEM8(0x0A80) +-#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) +-#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) +-#define AWEXE_STATUS _SFR_MEM8(0x0A84) +-#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) +-#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) +-#define AWEXE_DTLS _SFR_MEM8(0x0A88) +-#define AWEXE_DTHS _SFR_MEM8(0x0A89) +-#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) +-#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) +-#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) +- +-/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ +-#define USARTE0_DATA _SFR_MEM8(0x0AA0) +-#define USARTE0_STATUS _SFR_MEM8(0x0AA1) +-#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) +-#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) +-#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) +-#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) +-#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) +- +-/* SPIE - Serial Peripheral Interface E */ +-#define SPIE_CTRL _SFR_MEM8(0x0AC0) +-#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) +-#define SPIE_STATUS _SFR_MEM8(0x0AC2) +-#define SPIE_DATA _SFR_MEM8(0x0AC3) +- +-/* TCF0 - Timer/Counter F0 */ +-#define TCF0_CTRLA _SFR_MEM8(0x0B00) +-#define TCF0_CTRLB _SFR_MEM8(0x0B01) +-#define TCF0_CTRLC _SFR_MEM8(0x0B02) +-#define TCF0_CTRLD _SFR_MEM8(0x0B03) +-#define TCF0_CTRLE _SFR_MEM8(0x0B04) +-#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) +-#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) +-#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) +-#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) +-#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) +-#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) +-#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) +-#define TCF0_TEMP _SFR_MEM8(0x0B0F) +-#define TCF0_CNT _SFR_MEM16(0x0B20) +-#define TCF0_PER _SFR_MEM16(0x0B26) +-#define TCF0_CCA _SFR_MEM16(0x0B28) +-#define TCF0_CCB _SFR_MEM16(0x0B2A) +-#define TCF0_CCC _SFR_MEM16(0x0B2C) +-#define TCF0_CCD _SFR_MEM16(0x0B2E) +-#define TCF0_PERBUF _SFR_MEM16(0x0B36) +-#define TCF0_CCABUF _SFR_MEM16(0x0B38) +-#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) +-#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) +-#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) +- +- +- +-/*================== Bitfield Definitions ================== */ +- +-/* XOCD - On-Chip Debug System */ +-/* OCD.OCDR1 bit masks and bit positions */ +-#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ +-#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ +- +- +-/* CPU - CPU */ +-/* CPU.CCP bit masks and bit positions */ +-#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ +-#define CPU_CCP_gp 0 /* CCP signature group position. */ +-#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ +-#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ +-#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ +-#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ +-#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ +-#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ +-#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ +-#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ +-#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ +-#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ +-#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ +-#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ +-#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ +-#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ +-#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ +-#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ +- +- +-/* CPU.SREG bit masks and bit positions */ +-#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ +-#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ +- +-#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ +-#define CPU_T_bp 6 /* Transfer Bit bit position. */ +- +-#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ +-#define CPU_H_bp 5 /* Half Carry Flag bit position. */ +- +-#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ +-#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ +- +-#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ +-#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ +- +-#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ +-#define CPU_N_bp 2 /* Negative Flag bit position. */ +- +-#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ +-#define CPU_Z_bp 1 /* Zero Flag bit position. */ +- +-#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ +-#define CPU_C_bp 0 /* Carry Flag bit position. */ +- +- +-/* CLK - Clock System */ +-/* CLK.CTRL bit masks and bit positions */ +-#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ +-#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ +-#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ +-#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ +-#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ +-#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ +-#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ +-#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ +- +- +-/* CLK.PSCTRL bit masks and bit positions */ +-#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ +-#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ +-#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ +-#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ +-#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ +-#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ +-#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ +-#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ +-#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ +-#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ +-#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ +-#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ +- +-#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ +-#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ +-#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ +-#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ +-#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ +-#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ +- +- +-/* CLK.LOCK bit masks and bit positions */ +-#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ +-#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ +- +- +-/* CLK.RTCCTRL bit masks and bit positions */ +-#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ +-#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ +-#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ +-#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ +-#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ +-#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ +-#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ +-#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ +- +-#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ +-#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ +- +- +-/* PR.PRGEN bit masks and bit positions */ +-#define PR_AES_bm 0x10 /* AES bit mask. */ +-#define PR_AES_bp 4 /* AES bit position. */ +- +-#define PR_EBI_bm 0x08 /* External Bus Interface bit mask. */ +-#define PR_EBI_bp 3 /* External Bus Interface bit position. */ +- +-#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ +-#define PR_RTC_bp 2 /* Real-time Counter bit position. */ +- +-#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ +-#define PR_EVSYS_bp 1 /* Event System bit position. */ +- +-#define PR_DMA_bm 0x01 /* DMA-Controller bit mask. */ +-#define PR_DMA_bp 0 /* DMA-Controller bit position. */ +- +- +-/* PR.PRPA bit masks and bit positions */ +-#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ +-#define PR_DAC_bp 2 /* Port A DAC bit position. */ +- +-#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ +-#define PR_ADC_bp 1 /* Port A ADC bit position. */ +- +-#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ +-#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ +- +- +-/* PR.PRPB bit masks and bit positions */ +-/* PR_DAC_bm Predefined. */ +-/* PR_DAC_bp Predefined. */ +- +-/* PR_ADC_bm Predefined. */ +-/* PR_ADC_bp Predefined. */ +- +-/* PR_AC_bm Predefined. */ +-/* PR_AC_bp Predefined. */ +- +- +-/* PR.PRPC bit masks and bit positions */ +-#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ +-#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ +- +-#define PR_USART1_bm 0x20 /* Port C USART1 bit mask. */ +-#define PR_USART1_bp 5 /* Port C USART1 bit position. */ +- +-#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ +-#define PR_USART0_bp 4 /* Port C USART0 bit position. */ +- +-#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ +-#define PR_SPI_bp 3 /* Port C SPI bit position. */ +- +-#define PR_HIRES_bm 0x04 /* Port C AWEX bit mask. */ +-#define PR_HIRES_bp 2 /* Port C AWEX bit position. */ +- +-#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ +-#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ +- +-#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ +-#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ +- +- +-/* PR.PRPD bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* PR.PRPE bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* PR.PRPF bit masks and bit positions */ +-/* PR_TWI_bm Predefined. */ +-/* PR_TWI_bp Predefined. */ +- +-/* PR_USART1_bm Predefined. */ +-/* PR_USART1_bp Predefined. */ +- +-/* PR_USART0_bm Predefined. */ +-/* PR_USART0_bp Predefined. */ +- +-/* PR_SPI_bm Predefined. */ +-/* PR_SPI_bp Predefined. */ +- +-/* PR_HIRES_bm Predefined. */ +-/* PR_HIRES_bp Predefined. */ +- +-/* PR_TC1_bm Predefined. */ +-/* PR_TC1_bp Predefined. */ +- +-/* PR_TC0_bm Predefined. */ +-/* PR_TC0_bp Predefined. */ +- +- +-/* SLEEP - Sleep Controller */ +-/* SLEEP.CTRL bit masks and bit positions */ +-#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ +-#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ +-#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ +-#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ +-#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ +-#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ +-#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ +-#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ +- +-#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ +-#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ +- +- +-/* OSC - Oscillator */ +-/* OSC.CTRL bit masks and bit positions */ +-#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ +-#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ +- +-#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ +-#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ +- +-#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ +- +-#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ +-#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ +- +- +-/* OSC.STATUS bit masks and bit positions */ +-#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ +-#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ +- +-#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ +-#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ +- +-#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ +- +-#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ +-#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ +- +- +-/* OSC.XOSCCTRL bit masks and bit positions */ +-#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ +-#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ +-#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ +-#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ +-#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ +-#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ +- +-#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ +-#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ +- +-#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ +-#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ +-#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ +-#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ +-#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ +-#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ +-#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ +-#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ +-#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ +-#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ +- +- +-/* OSC.XOSCFAIL bit masks and bit positions */ +-#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ +-#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ +- +-#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ +-#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ +- +- +-/* OSC.PLLCTRL bit masks and bit positions */ +-#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ +-#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ +-#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ +-#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ +-#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ +-#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ +- +-#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ +-#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ +-#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ +-#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ +-#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ +-#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ +-#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ +-#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ +-#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ +-#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ +-#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ +-#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ +- +- +-/* OSC.DFLLCTRL bit masks and bit positions */ +-#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ +-#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ +- +-#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ +-#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ +- +- +-/* DFLL - DFLL */ +-/* DFLL.CTRL bit masks and bit positions */ +-#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ +-#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ +- +- +-/* DFLL.CALA bit masks and bit positions */ +-#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ +-#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ +-#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ +-#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ +-#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ +-#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ +-#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ +-#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ +-#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ +-#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ +-#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ +-#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ +-#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ +-#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ +-#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ +-#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ +- +- +-/* DFLL.CALB bit masks and bit positions */ +-#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ +-#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ +-#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ +-#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ +-#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ +-#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ +-#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ +-#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ +-#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ +-#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ +-#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ +-#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ +-#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ +-#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ +- +- +-/* RST - Reset */ +-/* RST.STATUS bit masks and bit positions */ +-#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ +-#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ +- +-#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ +-#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ +- +-#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ +-#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ +- +-#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ +-#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ +- +-#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ +-#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ +- +-#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ +-#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ +- +-#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ +-#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ +- +- +-/* RST.CTRL bit masks and bit positions */ +-#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ +-#define RST_SWRST_bp 0 /* Software Reset bit position. */ +- +- +-/* WDT - Watch-Dog Timer */ +-/* WDT.CTRL bit masks and bit positions */ +-#define WDT_PER_gm 0x3C /* Period group mask. */ +-#define WDT_PER_gp 2 /* Period group position. */ +-#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ +-#define WDT_PER0_bp 2 /* Period bit 0 position. */ +-#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ +-#define WDT_PER1_bp 3 /* Period bit 1 position. */ +-#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ +-#define WDT_PER2_bp 4 /* Period bit 2 position. */ +-#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ +-#define WDT_PER3_bp 5 /* Period bit 3 position. */ +- +-#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ +-#define WDT_ENABLE_bp 1 /* Enable bit position. */ +- +-#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ +-#define WDT_CEN_bp 0 /* Change Enable bit position. */ +- +- +-/* WDT.WINCTRL bit masks and bit positions */ +-#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ +-#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ +-#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ +-#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ +-#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ +-#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ +-#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ +-#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ +-#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ +-#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ +- +-#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ +-#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ +- +-#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ +-#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ +- +- +-/* WDT.STATUS bit masks and bit positions */ +-#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ +-#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ +- +- +-/* MCU - MCU Control */ +-/* MCU.MCUCR bit masks and bit positions */ +-#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ +-#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ +- +- +-/* MCU.EVSYSLOCK bit masks and bit positions */ +-#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ +-#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ +- +-#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ +-#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ +- +- +-/* MCU.AWEXLOCK bit masks and bit positions */ +-#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ +-#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ +- +-#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ +-#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ +- +- +-/* PMIC - Programmable Multi-level Interrupt Controller */ +-/* PMIC.STATUS bit masks and bit positions */ +-#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ +-#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ +- +-#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ +-#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ +- +-#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ +-#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ +- +-#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ +-#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ +- +- +-/* PMIC.CTRL bit masks and bit positions */ +-#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ +-#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ +- +-#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ +-#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ +- +-#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ +-#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ +- +-#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ +-#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ +- +-#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ +-#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ +- +- +-/* EVSYS - Event System */ +-/* EVSYS.CH0MUX bit masks and bit positions */ +-#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ +-#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ +-#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ +-#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ +-#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ +-#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ +-#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ +-#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ +-#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ +-#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ +-#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ +-#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ +-#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ +-#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ +-#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ +-#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ +-#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ +-#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ +- +- +-/* EVSYS.CH1MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH2MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH3MUX bit masks and bit positions */ +-/* EVSYS_CHMUX_gm Predefined. */ +-/* EVSYS_CHMUX_gp Predefined. */ +-/* EVSYS_CHMUX0_bm Predefined. */ +-/* EVSYS_CHMUX0_bp Predefined. */ +-/* EVSYS_CHMUX1_bm Predefined. */ +-/* EVSYS_CHMUX1_bp Predefined. */ +-/* EVSYS_CHMUX2_bm Predefined. */ +-/* EVSYS_CHMUX2_bp Predefined. */ +-/* EVSYS_CHMUX3_bm Predefined. */ +-/* EVSYS_CHMUX3_bp Predefined. */ +-/* EVSYS_CHMUX4_bm Predefined. */ +-/* EVSYS_CHMUX4_bp Predefined. */ +-/* EVSYS_CHMUX5_bm Predefined. */ +-/* EVSYS_CHMUX5_bp Predefined. */ +-/* EVSYS_CHMUX6_bm Predefined. */ +-/* EVSYS_CHMUX6_bp Predefined. */ +-/* EVSYS_CHMUX7_bm Predefined. */ +-/* EVSYS_CHMUX7_bp Predefined. */ +- +- +-/* EVSYS.CH0CTRL bit masks and bit positions */ +-#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ +-#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ +-#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ +-#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ +-#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ +-#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ +- +-#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ +-#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ +- +-#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ +-#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ +- +-#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ +-#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ +-#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ +-#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ +-#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ +-#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ +-#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ +-#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ +- +- +-/* EVSYS.CH1CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH2CTRL bit masks and bit positions */ +-/* EVSYS_QDIRM_gm Predefined. */ +-/* EVSYS_QDIRM_gp Predefined. */ +-/* EVSYS_QDIRM0_bm Predefined. */ +-/* EVSYS_QDIRM0_bp Predefined. */ +-/* EVSYS_QDIRM1_bm Predefined. */ +-/* EVSYS_QDIRM1_bp Predefined. */ +- +-/* EVSYS_QDIEN_bm Predefined. */ +-/* EVSYS_QDIEN_bp Predefined. */ +- +-/* EVSYS_QDEN_bm Predefined. */ +-/* EVSYS_QDEN_bp Predefined. */ +- +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* EVSYS.CH3CTRL bit masks and bit positions */ +-/* EVSYS_DIGFILT_gm Predefined. */ +-/* EVSYS_DIGFILT_gp Predefined. */ +-/* EVSYS_DIGFILT0_bm Predefined. */ +-/* EVSYS_DIGFILT0_bp Predefined. */ +-/* EVSYS_DIGFILT1_bm Predefined. */ +-/* EVSYS_DIGFILT1_bp Predefined. */ +-/* EVSYS_DIGFILT2_bm Predefined. */ +-/* EVSYS_DIGFILT2_bp Predefined. */ +- +- +-/* NVM - Non Volatile Memory Controller */ +-/* NVM.CMD bit masks and bit positions */ +-#define NVM_CMD_gm 0xFF /* Command group mask. */ +-#define NVM_CMD_gp 0 /* Command group position. */ +-#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define NVM_CMD0_bp 0 /* Command bit 0 position. */ +-#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define NVM_CMD1_bp 1 /* Command bit 1 position. */ +-#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ +-#define NVM_CMD2_bp 2 /* Command bit 2 position. */ +-#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ +-#define NVM_CMD3_bp 3 /* Command bit 3 position. */ +-#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ +-#define NVM_CMD4_bp 4 /* Command bit 4 position. */ +-#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ +-#define NVM_CMD5_bp 5 /* Command bit 5 position. */ +-#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ +-#define NVM_CMD6_bp 6 /* Command bit 6 position. */ +-#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ +-#define NVM_CMD7_bp 7 /* Command bit 7 position. */ +- +- +-/* NVM.CTRLA bit masks and bit positions */ +-#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ +-#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ +- +- +-/* NVM.CTRLB bit masks and bit positions */ +-#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ +-#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ +- +-#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ +-#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ +- +-#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ +-#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ +- +-#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ +-#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ +- +- +-/* NVM.INTCTRL bit masks and bit positions */ +-#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ +-#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ +-#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ +-#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ +-#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ +-#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ +- +-#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ +-#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ +-#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ +-#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ +-#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ +-#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ +- +- +-/* NVM.STATUS bit masks and bit positions */ +-#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ +-#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ +- +-#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ +-#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ +- +-#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ +-#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ +- +-#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ +-#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ +- +- +-/* NVM.LOCKBITS bit masks and bit positions */ +-#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ +-#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ +-#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ +-#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ +-#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ +-#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ +-#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ +-#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ +-#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ +- +-#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ +-#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ +-#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ +-#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ +-#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ +-#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ +- +-#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ +-#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ +-#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ +-#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ +-#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ +-#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ +-#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ +-#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ +-#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ +-#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ +-#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ +-#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ +-#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ +-#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ +-#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ +-#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ +-#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ +-#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ +-#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ +-#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ +-#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ +-#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ +-#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ +-#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ +-#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ +-#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ +-#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ +- +-#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ +-#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ +-#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ +-#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ +-#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ +-#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ +-#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ +-#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ +-#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ +-#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ +-#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ +-#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ +- +-#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ +-#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ +- +-#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ +-#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ +-#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ +-#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ +-#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ +-#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ +- +- +-/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ +-#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ +-#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ +-#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ +-#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ +-#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ +-#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ +- +-#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ +-#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ +- +- +-/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ +-#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ +-#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ +-#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ +-#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ +-#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ +-#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ +- +-#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ +-#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ +- +-#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ +-#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ +-#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ +-#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ +-#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ +-#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ +-#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ +-#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ +- +- +-/* AC - Analog Comparator */ +-/* AC.AC0CTRL bit masks and bit positions */ +-#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ +-#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ +-#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ +-#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ +-#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ +-#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ +- +-#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ +-#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ +-#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ +-#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ +-#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ +-#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ +- +-#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ +-#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ +- +-#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ +-#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ +-#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ +-#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ +-#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ +-#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ +- +-#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ +-#define AC_ENABLE_bp 0 /* Enable bit position. */ +- +- +-/* AC.AC1CTRL bit masks and bit positions */ +-/* AC_INTMODE_gm Predefined. */ +-/* AC_INTMODE_gp Predefined. */ +-/* AC_INTMODE0_bm Predefined. */ +-/* AC_INTMODE0_bp Predefined. */ +-/* AC_INTMODE1_bm Predefined. */ +-/* AC_INTMODE1_bp Predefined. */ +- +-/* AC_INTLVL_gm Predefined. */ +-/* AC_INTLVL_gp Predefined. */ +-/* AC_INTLVL0_bm Predefined. */ +-/* AC_INTLVL0_bp Predefined. */ +-/* AC_INTLVL1_bm Predefined. */ +-/* AC_INTLVL1_bp Predefined. */ +- +-/* AC_HSMODE_bm Predefined. */ +-/* AC_HSMODE_bp Predefined. */ +- +-/* AC_HYSMODE_gm Predefined. */ +-/* AC_HYSMODE_gp Predefined. */ +-/* AC_HYSMODE0_bm Predefined. */ +-/* AC_HYSMODE0_bp Predefined. */ +-/* AC_HYSMODE1_bm Predefined. */ +-/* AC_HYSMODE1_bp Predefined. */ +- +-/* AC_ENABLE_bm Predefined. */ +-/* AC_ENABLE_bp Predefined. */ +- +- +-/* AC.AC0MUXCTRL bit masks and bit positions */ +-#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ +-#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ +-#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ +-#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ +-#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ +-#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ +-#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ +-#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ +- +-#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ +-#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ +-#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ +-#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ +-#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ +-#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ +-#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ +-#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ +- +- +-/* AC.AC1MUXCTRL bit masks and bit positions */ +-/* AC_MUXPOS_gm Predefined. */ +-/* AC_MUXPOS_gp Predefined. */ +-/* AC_MUXPOS0_bm Predefined. */ +-/* AC_MUXPOS0_bp Predefined. */ +-/* AC_MUXPOS1_bm Predefined. */ +-/* AC_MUXPOS1_bp Predefined. */ +-/* AC_MUXPOS2_bm Predefined. */ +-/* AC_MUXPOS2_bp Predefined. */ +- +-/* AC_MUXNEG_gm Predefined. */ +-/* AC_MUXNEG_gp Predefined. */ +-/* AC_MUXNEG0_bm Predefined. */ +-/* AC_MUXNEG0_bp Predefined. */ +-/* AC_MUXNEG1_bm Predefined. */ +-/* AC_MUXNEG1_bp Predefined. */ +-/* AC_MUXNEG2_bm Predefined. */ +-/* AC_MUXNEG2_bp Predefined. */ +- +- +-/* AC.CTRLA bit masks and bit positions */ +-#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ +-#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ +- +- +-/* AC.CTRLB bit masks and bit positions */ +-#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ +-#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ +-#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ +-#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ +-#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ +-#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ +-#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ +-#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ +-#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ +-#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ +-#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ +-#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ +-#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ +-#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ +- +- +-/* AC.WINCTRL bit masks and bit positions */ +-#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ +-#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ +- +-#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ +-#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ +-#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ +-#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ +-#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ +-#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ +- +-#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ +-#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ +-#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ +-#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ +-#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ +-#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ +- +- +-/* AC.STATUS bit masks and bit positions */ +-#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ +-#define AC_WSTATE_gp 6 /* Window Mode State group position. */ +-#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ +-#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ +-#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ +-#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ +- +-#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ +-#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ +- +-#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ +-#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ +- +-#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ +-#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ +- +-#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ +-#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ +- +-#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ +-#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ +- +- +-/* ADC - Analog/Digital Converter */ +-/* ADC_CH.CTRL bit masks and bit positions */ +-#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ +-#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ +- +-#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ +-#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ +-#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ +-#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ +-#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ +-#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ +-#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ +-#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ +- +-#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ +-#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ +-#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ +-#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ +-#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ +-#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ +- +- +-/* ADC_CH.MUXCTRL bit masks and bit positions */ +-#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ +-#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ +-#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ +-#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ +-#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ +-#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ +-#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ +-#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ +-#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ +-#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ +- +-#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ +-#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ +-#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ +-#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ +-#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ +-#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ +-#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ +-#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ +-#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ +-#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ +- +-#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ +-#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ +-#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ +-#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ +-#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ +-#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ +- +- +-/* ADC_CH.INTCTRL bit masks and bit positions */ +-#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ +-#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ +-#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ +-#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ +-#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ +-#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ +- +-#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ +-#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ +-#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ +-#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ +-#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ +-#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ +- +- +-/* ADC_CH.INTFLAGS bit masks and bit positions */ +-#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ +-#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ +- +- +-/* ADC.CTRLA bit masks and bit positions */ +-#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ +-#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ +- +-#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ +-#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ +- +-#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ +-#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ +- +- +-/* ADC.CTRLB bit masks and bit positions */ +-#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ +-#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ +- +-#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ +-#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ +- +-#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ +-#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ +-#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ +-#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ +-#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ +-#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ +- +- +-/* ADC.REFCTRL bit masks and bit positions */ +-#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ +-#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ +-#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ +-#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ +-#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ +-#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ +- +-#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ +-#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ +- +-#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ +-#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ +- +- +-/* ADC.EVCTRL bit masks and bit positions */ +-#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ +-#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ +-#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ +-#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ +-#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ +-#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ +- +-#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ +-#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ +-#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ +-#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ +-#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ +-#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ +-#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ +-#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ +- +-#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ +-#define ADC_EVACT_gp 0 /* Event Action Select group position. */ +-#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ +-#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ +-#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ +-#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ +-#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ +-#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ +- +- +-/* ADC.PRESCALER bit masks and bit positions */ +-#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ +-#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ +-#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ +-#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ +-#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ +-#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ +-#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ +-#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ +- +- +-/* ADC.INTFLAGS bit masks and bit positions */ +-#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ +-#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ +- +- +-/* RTC - Real-Time Clounter */ +-/* RTC.CTRL bit masks and bit positions */ +-#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ +-#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ +-#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ +-#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ +-#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ +-#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ +-#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ +-#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ +- +- +-/* RTC.STATUS bit masks and bit positions */ +-#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ +-#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ +- +- +-/* RTC.INTCTRL bit masks and bit positions */ +-#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ +-#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ +-#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ +-#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ +-#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ +-#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ +- +-#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ +-#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ +-#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ +-#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ +-#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ +-#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ +- +- +-/* RTC.INTFLAGS bit masks and bit positions */ +-#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ +-#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ +- +-#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* EBI - External Bus Interface */ +-/* EBI_CS.CTRLA bit masks and bit positions */ +-#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ +-#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ +-#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ +-#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ +-#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ +-#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ +-#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ +-#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ +-#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ +-#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ +-#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ +-#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ +- +-#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ +-#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ +-#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ +-#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ +-#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ +-#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ +- +- +-/* EBI_CS.CTRLB bit masks and bit positions */ +-#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ +-#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ +-#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ +-#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ +-#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ +-#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ +-#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ +-#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ +- +-#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ +-#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ +- +-#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ +-#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ +- +-#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ +-#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ +-#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ +-#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ +-#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ +-#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ +- +- +-/* EBI.CTRL bit masks and bit positions */ +-#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ +-#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ +-#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ +-#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ +-#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ +-#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ +- +-#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ +-#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ +-#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ +-#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ +-#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ +-#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ +- +-#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ +-#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ +-#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ +-#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ +-#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ +-#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ +- +-#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ +-#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ +-#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ +-#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ +-#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ +-#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLA bit masks and bit positions */ +-#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ +-#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ +- +-#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ +-#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ +- +-#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ +-#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ +-#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ +-#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ +-#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ +-#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ +- +- +-/* EBI.SDRAMCTRLB bit masks and bit positions */ +-#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ +-#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ +-#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ +-#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ +-#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ +-#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ +- +-#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ +-#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ +-#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ +-#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ +-#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ +-#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ +-#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ +-#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ +- +-#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ +-#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ +-#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ +-#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ +-#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ +-#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ +-#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ +-#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ +- +- +-/* EBI.SDRAMCTRLC bit masks and bit positions */ +-#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ +-#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ +-#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ +-#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ +-#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ +-#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ +- +-#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ +-#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ +-#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ +-#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ +-#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ +-#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ +-#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ +-#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ +- +-#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ +-#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ +-#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ +-#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ +-#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ +-#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ +-#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ +-#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ +- +- +-/* TWI - Two-Wire Interface */ +-/* TWI_MASTER.CTRLA bit masks and bit positions */ +-#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ +-#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ +- +-#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ +-#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ +- +-#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ +-#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ +- +- +-/* TWI_MASTER.CTRLB bit masks and bit positions */ +-#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ +-#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ +-#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ +-#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ +-#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ +-#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ +- +-#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ +-#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ +- +-#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_MASTER.CTRLC bit masks and bit positions */ +-#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_MASTER_CMD_gp 0 /* Command group position. */ +-#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_MASTER.STATUS bit masks and bit positions */ +-#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ +-#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ +- +-#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ +-#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ +- +-#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ +-#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ +- +-#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ +-#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ +-#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ +-#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ +-#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ +-#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ +- +- +-/* TWI_SLAVE.CTRLA bit masks and bit positions */ +-#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ +-#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ +-#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ +-#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ +-#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ +-#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ +- +-#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ +-#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ +-#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ +- +-#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ +-#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ +- +-#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ +-#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ +- +-#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ +-#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ +- +- +-/* TWI_SLAVE.CTRLB bit masks and bit positions */ +-#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ +-#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ +- +-#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ +-#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ +-#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ +-#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ +-#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ +-#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ +- +- +-/* TWI_SLAVE.STATUS bit masks and bit positions */ +-#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ +-#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ +-#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ +- +-#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ +-#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ +- +-#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ +-#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ +- +-#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ +-#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ +- +-#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ +-#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ +- +-#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ +-#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ +- +-#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ +-#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ +- +- +-/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ +-#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ +-#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ +-#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ +-#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ +-#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ +-#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ +-#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ +-#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ +-#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ +-#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ +-#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ +-#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ +-#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ +-#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ +-#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ +-#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ +- +-#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ +-#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ +- +- +-/* TWI.CTRL bit masks and bit positions */ +-#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ +-#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ +- +-#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ +-#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ +- +- +-/* PORT - Port Configuration */ +-/* PORTCFG.VPCTRLA bit masks and bit positions */ +-#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ +-#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ +-#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ +-#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ +-#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ +-#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ +-#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ +-#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ +-#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ +-#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ +- +-#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ +-#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ +-#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ +-#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ +-#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ +-#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ +-#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ +-#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ +-#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ +-#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ +- +- +-/* PORTCFG.VPCTRLB bit masks and bit positions */ +-#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ +-#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ +-#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ +-#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ +-#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ +-#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ +-#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ +-#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ +-#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ +-#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ +- +-#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ +-#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ +-#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ +-#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ +-#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ +-#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ +-#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ +-#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ +-#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ +-#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ +- +- +-/* PORTCFG.CLKEVOUT bit masks and bit positions */ +-#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ +-#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ +-#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ +-#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ +-#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ +-#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ +- +-#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ +-#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ +-#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ +-#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ +-#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ +-#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ +- +- +-/* VPORT.INTFLAGS bit masks and bit positions */ +-#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.INTCTRL bit masks and bit positions */ +-#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ +-#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ +-#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ +-#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ +-#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ +-#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ +- +-#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ +-#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ +-#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ +-#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ +-#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ +-#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ +- +- +-/* PORT.INTFLAGS bit masks and bit positions */ +-#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ +-#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ +- +-#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ +-#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ +- +- +-/* PORT.PIN0CTRL bit masks and bit positions */ +-#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ +-#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ +- +-#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ +-#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ +- +-#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ +-#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ +-#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ +-#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ +-#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ +-#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ +-#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ +-#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ +- +-#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ +-#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ +-#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ +-#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ +-#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ +-#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ +-#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ +-#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ +- +- +-/* PORT.PIN1CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN2CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN3CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN4CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN5CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN6CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* PORT.PIN7CTRL bit masks and bit positions */ +-/* PORT_SRLEN_bm Predefined. */ +-/* PORT_SRLEN_bp Predefined. */ +- +-/* PORT_INVEN_bm Predefined. */ +-/* PORT_INVEN_bp Predefined. */ +- +-/* PORT_OPC_gm Predefined. */ +-/* PORT_OPC_gp Predefined. */ +-/* PORT_OPC0_bm Predefined. */ +-/* PORT_OPC0_bp Predefined. */ +-/* PORT_OPC1_bm Predefined. */ +-/* PORT_OPC1_bp Predefined. */ +-/* PORT_OPC2_bm Predefined. */ +-/* PORT_OPC2_bp Predefined. */ +- +-/* PORT_ISC_gm Predefined. */ +-/* PORT_ISC_gp Predefined. */ +-/* PORT_ISC0_bm Predefined. */ +-/* PORT_ISC0_bp Predefined. */ +-/* PORT_ISC1_bm Predefined. */ +-/* PORT_ISC1_bp Predefined. */ +-/* PORT_ISC2_bm Predefined. */ +-/* PORT_ISC2_bp Predefined. */ +- +- +-/* TC - 16-bit Timer/Counter With PWM */ +-/* TC0.CTRLA bit masks and bit positions */ +-#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC0.CTRLB bit masks and bit positions */ +-#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ +-#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ +- +-#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ +-#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ +- +-#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC0.CTRLC bit masks and bit positions */ +-#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ +-#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ +- +-#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ +-#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ +- +-#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC0.CTRLD bit masks and bit positions */ +-#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC0_EVACT_gp 5 /* Event Action group position. */ +-#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC0.CTRLE bit masks and bit positions */ +-#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC0.INTCTRLA bit masks and bit positions */ +-#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC0.INTCTRLB bit masks and bit positions */ +-#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ +-#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ +-#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ +-#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ +-#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ +-#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ +- +-#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ +-#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ +-#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ +-#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ +-#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ +-#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ +- +-#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC0.CTRLFCLR bit masks and bit positions */ +-#define TC0_CMD_gm 0x0C /* Command group mask. */ +-#define TC0_CMD_gp 2 /* Command group position. */ +-#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC0_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC0_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC0_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC0_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC0_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC0.CTRLFSET bit masks and bit positions */ +-/* TC0_CMD_gm Predefined. */ +-/* TC0_CMD_gp Predefined. */ +-/* TC0_CMD0_bm Predefined. */ +-/* TC0_CMD0_bp Predefined. */ +-/* TC0_CMD1_bm Predefined. */ +-/* TC0_CMD1_bp Predefined. */ +- +-/* TC0_LUPD_bm Predefined. */ +-/* TC0_LUPD_bp Predefined. */ +- +-/* TC0_DIR_bm Predefined. */ +-/* TC0_DIR_bp Predefined. */ +- +- +-/* TC0.CTRLGCLR bit masks and bit positions */ +-#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ +-#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ +- +-#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ +-#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ +- +-#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC0.CTRLGSET bit masks and bit positions */ +-/* TC0_CCDBV_bm Predefined. */ +-/* TC0_CCDBV_bp Predefined. */ +- +-/* TC0_CCCBV_bm Predefined. */ +-/* TC0_CCCBV_bp Predefined. */ +- +-/* TC0_CCBBV_bm Predefined. */ +-/* TC0_CCBBV_bp Predefined. */ +- +-/* TC0_CCABV_bm Predefined. */ +-/* TC0_CCABV_bp Predefined. */ +- +-/* TC0_PERBV_bm Predefined. */ +-/* TC0_PERBV_bp Predefined. */ +- +- +-/* TC0.INTFLAGS bit masks and bit positions */ +-#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ +-#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ +- +-#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ +-#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ +- +-#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* TC1.CTRLA bit masks and bit positions */ +-#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ +-#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ +-#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ +-#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ +-#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ +-#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ +-#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ +-#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ +-#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ +-#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ +- +- +-/* TC1.CTRLB bit masks and bit positions */ +-#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ +-#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ +- +-#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ +-#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ +- +-#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ +-#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ +-#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ +-#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ +-#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ +-#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ +-#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ +-#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ +- +- +-/* TC1.CTRLC bit masks and bit positions */ +-#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ +-#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ +- +-#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ +-#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ +- +- +-/* TC1.CTRLD bit masks and bit positions */ +-#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ +-#define TC1_EVACT_gp 5 /* Event Action group position. */ +-#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ +-#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ +-#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ +-#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ +-#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ +-#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ +- +-#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ +-#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ +- +-#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ +-#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ +-#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ +-#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ +-#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ +-#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ +-#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ +-#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ +-#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ +-#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ +- +- +-/* TC1.CTRLE bit masks and bit positions */ +-#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ +-#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ +- +- +-/* TC1.INTCTRLA bit masks and bit positions */ +-#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ +-#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ +-#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ +-#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ +-#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ +-#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ +- +-#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ +-#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ +-#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ +-#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ +-#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ +-#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ +- +- +-/* TC1.INTCTRLB bit masks and bit positions */ +-#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ +-#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ +-#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ +-#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ +-#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ +-#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ +- +-#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ +-#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ +-#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ +-#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ +-#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ +-#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ +- +- +-/* TC1.CTRLFCLR bit masks and bit positions */ +-#define TC1_CMD_gm 0x0C /* Command group mask. */ +-#define TC1_CMD_gp 2 /* Command group position. */ +-#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ +-#define TC1_CMD0_bp 2 /* Command bit 0 position. */ +-#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ +-#define TC1_CMD1_bp 3 /* Command bit 1 position. */ +- +-#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ +-#define TC1_LUPD_bp 1 /* Lock Update bit position. */ +- +-#define TC1_DIR_bm 0x01 /* Direction bit mask. */ +-#define TC1_DIR_bp 0 /* Direction bit position. */ +- +- +-/* TC1.CTRLFSET bit masks and bit positions */ +-/* TC1_CMD_gm Predefined. */ +-/* TC1_CMD_gp Predefined. */ +-/* TC1_CMD0_bm Predefined. */ +-/* TC1_CMD0_bp Predefined. */ +-/* TC1_CMD1_bm Predefined. */ +-/* TC1_CMD1_bp Predefined. */ +- +-/* TC1_LUPD_bm Predefined. */ +-/* TC1_LUPD_bp Predefined. */ +- +-/* TC1_DIR_bm Predefined. */ +-/* TC1_DIR_bp Predefined. */ +- +- +-/* TC1.CTRLGCLR bit masks and bit positions */ +-#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ +-#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ +- +-#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ +-#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ +- +-#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ +-#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ +- +- +-/* TC1.CTRLGSET bit masks and bit positions */ +-/* TC1_CCBBV_bm Predefined. */ +-/* TC1_CCBBV_bp Predefined. */ +- +-/* TC1_CCABV_bm Predefined. */ +-/* TC1_CCABV_bp Predefined. */ +- +-/* TC1_PERBV_bm Predefined. */ +-/* TC1_PERBV_bp Predefined. */ +- +- +-/* TC1.INTFLAGS bit masks and bit positions */ +-#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ +-#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ +- +-#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ +-#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ +- +-#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ +-#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ +- +-#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ +-#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ +- +- +-/* AWEX.CTRL bit masks and bit positions */ +-#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ +-#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ +- +-#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ +-#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ +- +-#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ +-#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ +- +-#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ +-#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ +- +-#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ +-#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ +- +-#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ +-#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ +- +- +-/* AWEX.FDCTRL bit masks and bit positions */ +-#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ +-#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ +- +-#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ +-#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ +- +-#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ +-#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ +-#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ +-#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ +-#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ +-#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ +- +- +-/* AWEX.STATUS bit masks and bit positions */ +-#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ +-#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ +- +-#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ +-#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ +- +-#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ +-#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ +- +- +-/* HIRES.CTRLA bit masks and bit positions */ +-#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ +-#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ +-#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ +-#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ +-#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ +-#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ +- +- +-/* USART - Universal Asynchronous Receiver-Transmitter */ +-/* USART.STATUS bit masks and bit positions */ +-#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ +-#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ +- +-#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ +-#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ +- +-#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ +-#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ +- +-#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ +-#define USART_FERR_bp 4 /* Frame Error bit position. */ +- +-#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ +-#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ +- +-#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ +-#define USART_PERR_bp 2 /* Parity Error bit position. */ +- +-#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ +-#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ +- +- +-/* USART.CTRLA bit masks and bit positions */ +-#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ +-#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ +-#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ +-#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ +-#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ +-#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ +- +-#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ +-#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ +-#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ +-#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ +-#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ +-#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ +- +-#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ +-#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ +-#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ +-#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ +-#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ +-#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ +- +- +-/* USART.CTRLB bit masks and bit positions */ +-#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ +-#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ +- +-#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ +-#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ +- +-#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ +-#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ +- +-#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ +-#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ +- +-#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ +-#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ +- +- +-/* USART.CTRLC bit masks and bit positions */ +-#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ +-#define USART_CMODE_gp 6 /* Communication Mode group position. */ +-#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ +-#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ +-#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ +-#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ +- +-#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ +-#define USART_PMODE_gp 4 /* Parity Mode group position. */ +-#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ +-#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ +-#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ +-#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ +- +-#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ +-#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ +- +-#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ +-#define USART_CHSIZE_gp 0 /* Character Size group position. */ +-#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ +-#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ +-#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ +-#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ +-#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ +-#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ +- +- +-/* USART.BAUDCTRLA bit masks and bit positions */ +-#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ +-#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ +-#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ +-#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ +-#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ +-#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ +-#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ +-#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ +-#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ +-#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ +-#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ +-#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ +-#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ +-#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ +-#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ +-#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ +-#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ +-#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ +- +- +-/* USART.BAUDCTRLB bit masks and bit positions */ +-#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ +-#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ +-#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ +-#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ +-#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ +-#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ +-#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ +-#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ +-#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ +-#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ +- +-/* USART_BSEL_gm Predefined. */ +-/* USART_BSEL_gp Predefined. */ +-/* USART_BSEL0_bm Predefined. */ +-/* USART_BSEL0_bp Predefined. */ +-/* USART_BSEL1_bm Predefined. */ +-/* USART_BSEL1_bp Predefined. */ +-/* USART_BSEL2_bm Predefined. */ +-/* USART_BSEL2_bp Predefined. */ +-/* USART_BSEL3_bm Predefined. */ +-/* USART_BSEL3_bp Predefined. */ +- +- +-/* SPI - Serial Peripheral Interface */ +-/* SPI.CTRL bit masks and bit positions */ +-#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ +-#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ +- +-#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ +-#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ +- +-#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ +-#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ +- +-#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ +-#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ +- +-#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ +-#define SPI_MODE_gp 2 /* SPI Mode group position. */ +-#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ +-#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ +-#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ +-#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ +- +-#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ +-#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ +-#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ +-#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ +-#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ +-#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ +- +- +-/* SPI.INTCTRL bit masks and bit positions */ +-#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ +-#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ +-#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ +-#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ +-#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ +-#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ +- +- +-/* SPI.STATUS bit masks and bit positions */ +-#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ +-#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ +- +-#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ +-#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ +- +- +-/* IRCOM - IR Communication Module */ +-/* IRCOM.CTRL bit masks and bit positions */ +-#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ +-#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ +-#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ +-#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ +-#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ +-#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ +-#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ +-#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ +-#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ +-#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ +- +- +- +-// Generic Port Pins +- +-#define PIN0_bm 0x01 +-#define PIN0_bp 0 +-#define PIN1_bm 0x02 +-#define PIN1_bp 1 +-#define PIN2_bm 0x04 +-#define PIN2_bp 2 +-#define PIN3_bm 0x08 +-#define PIN3_bp 3 +-#define PIN4_bm 0x10 +-#define PIN4_bp 4 +-#define PIN5_bm 0x20 +-#define PIN5_bp 5 +-#define PIN6_bm 0x40 +-#define PIN6_bp 6 +-#define PIN7_bm 0x80 +-#define PIN7_bp 7 +- +- +-/* ========== Interrupt Vector Definitions ========== */ +-/* Vector 0 is the reset vector */ +- +-/* OSC interrupt vectors */ +-#define OSC_XOSCF_vect_num 1 +-#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ +- +-/* PORTC interrupt vectors */ +-#define PORTC_INT0_vect_num 2 +-#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ +-#define PORTC_INT1_vect_num 3 +-#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ +- +-/* PORTR interrupt vectors */ +-#define PORTR_INT0_vect_num 4 +-#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ +-#define PORTR_INT1_vect_num 5 +-#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ +- +-/* RTC interrupt vectors */ +-#define RTC_OVF_vect_num 10 +-#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ +-#define RTC_COMP_vect_num 11 +-#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ +- +-/* TWIC interrupt vectors */ +-#define TWIC_TWIS_vect_num 12 +-#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ +-#define TWIC_TWIM_vect_num 13 +-#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ +- +-/* TCC0 interrupt vectors */ +-#define TCC0_OVF_vect_num 14 +-#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ +-#define TCC0_ERR_vect_num 15 +-#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ +-#define TCC0_CCA_vect_num 16 +-#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ +-#define TCC0_CCB_vect_num 17 +-#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ +-#define TCC0_CCC_vect_num 18 +-#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ +-#define TCC0_CCD_vect_num 19 +-#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ +- +-/* TCC1 interrupt vectors */ +-#define TCC1_OVF_vect_num 20 +-#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ +-#define TCC1_ERR_vect_num 21 +-#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ +-#define TCC1_CCA_vect_num 22 +-#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ +-#define TCC1_CCB_vect_num 23 +-#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ +- +-/* SPIC interrupt vectors */ +-#define SPIC_INT_vect_num 24 +-#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ +- +-/* USARTC0 interrupt vectors */ +-#define USARTC0_RXC_vect_num 25 +-#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ +-#define USARTC0_DRE_vect_num 26 +-#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ +-#define USARTC0_TXC_vect_num 27 +-#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ +- +-/* NVM interrupt vectors */ +-#define NVM_EE_vect_num 32 +-#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ +-#define NVM_SPM_vect_num 33 +-#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ +- +-/* PORTB interrupt vectors */ +-#define PORTB_INT0_vect_num 34 +-#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ +-#define PORTB_INT1_vect_num 35 +-#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ +- +-/* PORTE interrupt vectors */ +-#define PORTE_INT0_vect_num 43 +-#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ +-#define PORTE_INT1_vect_num 44 +-#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ +- +-/* TCE0 interrupt vectors */ +-#define TCE0_OVF_vect_num 47 +-#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ +-#define TCE0_ERR_vect_num 48 +-#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ +-#define TCE0_CCA_vect_num 49 +-#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ +-#define TCE0_CCB_vect_num 50 +-#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ +-#define TCE0_CCC_vect_num 51 +-#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ +-#define TCE0_CCD_vect_num 52 +-#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ +- +-/* USARTE0 interrupt vectors */ +-#define USARTE0_RXC_vect_num 58 +-#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ +-#define USARTE0_DRE_vect_num 59 +-#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ +-#define USARTE0_TXC_vect_num 60 +-#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ +- +-/* PORTD interrupt vectors */ +-#define PORTD_INT0_vect_num 64 +-#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ +-#define PORTD_INT1_vect_num 65 +-#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ +- +-/* PORTA interrupt vectors */ +-#define PORTA_INT0_vect_num 66 +-#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ +-#define PORTA_INT1_vect_num 67 +-#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ +- +-/* ACA interrupt vectors */ +-#define ACA_AC0_vect_num 68 +-#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ +-#define ACA_AC1_vect_num 69 +-#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ +-#define ACA_ACW_vect_num 70 +-#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ +- +-/* ADCA interrupt vectors */ +-#define ADCA_CH0_vect_num 71 +-#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ +- +-/* TCD0 interrupt vectors */ +-#define TCD0_OVF_vect_num 77 +-#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ +-#define TCD0_ERR_vect_num 78 +-#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ +-#define TCD0_CCA_vect_num 79 +-#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ +-#define TCD0_CCB_vect_num 80 +-#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ +-#define TCD0_CCC_vect_num 81 +-#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ +-#define TCD0_CCD_vect_num 82 +-#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ +- +-/* SPID interrupt vectors */ +-#define SPID_INT_vect_num 87 +-#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ +- +-/* USARTD0 interrupt vectors */ +-#define USARTD0_RXC_vect_num 88 +-#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ +-#define USARTD0_DRE_vect_num 89 +-#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ +-#define USARTD0_TXC_vect_num 90 +-#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ +- +-/* PORTF interrupt vectors */ +-#define PORTF_INT0_vect_num 104 +-#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ +-#define PORTF_INT1_vect_num 105 +-#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ +- +-/* TCF0 interrupt vectors */ +-#define TCF0_OVF_vect_num 108 +-#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ +-#define TCF0_ERR_vect_num 109 +-#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ +-#define TCF0_CCA_vect_num 110 +-#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ +-#define TCF0_CCB_vect_num 111 +-#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ +-#define TCF0_CCC_vect_num 112 +-#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ +-#define TCF0_CCD_vect_num 113 +-#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ +- +- +-#define _VECTOR_SIZE 4 /* Size of individual vector. */ +-#define _VECTORS_SIZE (114 * _VECTOR_SIZE) +- +- +-/* ========== Constants ========== */ +- +-#define PROGMEM_START (0x0000) +-#define PROGMEM_SIZE (69632) +-#define PROGMEM_PAGE_SIZE (256) +-#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) +- +-#define APP_SECTION_START (0x0000) +-#define APP_SECTION_SIZE (65536) +-#define APP_SECTION_PAGE_SIZE (256) +-#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) +- +-#define APPTABLE_SECTION_START (0x0F000) +-#define APPTABLE_SECTION_SIZE (4096) +-#define APPTABLE_SECTION_PAGE_SIZE (256) +-#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) +- +-#define BOOT_SECTION_START (0x10000) +-#define BOOT_SECTION_SIZE (4096) +-#define BOOT_SECTION_PAGE_SIZE (256) +-#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) +- +-#define DATAMEM_START (0x0000) +-#define DATAMEM_SIZE (12288) +-#define DATAMEM_PAGE_SIZE (0) +-#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) +- +-#define IO_START (0x0000) +-#define IO_SIZE (4096) +-#define IO_PAGE_SIZE (0) +-#define IO_END (IO_START + IO_SIZE - 1) +- +-#define MAPPED_EEPROM_START (0x1000) +-#define MAPPED_EEPROM_SIZE (2048) +-#define MAPPED_EEPROM_PAGE_SIZE (0) +-#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) +- +-#define INTERNAL_SRAM_START (0x2000) +-#define INTERNAL_SRAM_SIZE (4096) +-#define INTERNAL_SRAM_PAGE_SIZE (0) +-#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) +- +-#define EEPROM_START (0x0000) +-#define EEPROM_SIZE (2048) +-#define EEPROM_PAGE_SIZE (32) +-#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) +- +-#define FUSE_START (0x0000) +-#define FUSE_SIZE (6) +-#define FUSE_PAGE_SIZE (0) +-#define FUSE_END (FUSE_START + FUSE_SIZE - 1) +- +-#define LOCKBIT_START (0x0000) +-#define LOCKBIT_SIZE (1) +-#define LOCKBIT_PAGE_SIZE (0) +-#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) +- +-#define SIGNATURES_START (0x0000) +-#define SIGNATURES_SIZE (3) +-#define SIGNATURES_PAGE_SIZE (0) +-#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) +- +-#define USER_SIGNATURES_START (0x0000) +-#define USER_SIGNATURES_SIZE (256) +-#define USER_SIGNATURES_PAGE_SIZE (0) +-#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) +- +-#define PROD_SIGNATURES_START (0x0000) +-#define PROD_SIGNATURES_SIZE (52) +-#define PROD_SIGNATURES_PAGE_SIZE (0) +-#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) +- +-#define FLASHEND PROGMEM_END +-#define SPM_PAGESIZE PROGMEM_PAGE_SIZE +-#define RAMSTART INTERNAL_SRAM_START +-#define RAMSIZE INTERNAL_SRAM_SIZE +-#define RAMEND INTERNAL_SRAM_END +-#define XRAMSTART EXTERNAL_SRAM_START +-#define XRAMSIZE EXTERNAL_SRAM_SIZE +-#define XRAMEND INTERNAL_SRAM_END +-#define E2END EEPROM_END +-#define E2PAGESIZE EEPROM_PAGE_SIZE +- +- +-/* ========== Fuses ========== */ +-#define FUSE_MEMORY_SIZE 6 +- +-/* Fuse Byte 0 */ +-#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ +-#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ +-#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ +-#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ +-#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ +-#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ +-#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ +-#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ +-#define FUSE0_DEFAULT (0xFF) +- +-/* Fuse Byte 1 */ +-#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ +-#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ +-#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ +-#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ +-#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ +-#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ +-#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ +-#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ +-#define FUSE1_DEFAULT (0xFF) +- +-/* Fuse Byte 2 */ +-#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ +-#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ +-#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ +-#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ +-#define FUSE2_DEFAULT (0xFF) +- +-/* Fuse Byte 3 Reserved */ +- +-/* Fuse Byte 4 */ +-#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ +-#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ +-#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ +-#define FUSE4_DEFAULT (0xFF) +- +-/* Fuse Byte 5 */ +-#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ +-#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ +-#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ +-#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ +-#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ +-#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ +-#define FUSE5_DEFAULT (0xFF) +- +- +-/* ========== Lock Bits ========== */ +-#define __LOCK_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST +-#define __BOOT_LOCK_APPLICATION_BITS_EXIST +-#define __BOOT_LOCK_BOOT_BITS_EXIST +- +- +-/* ========== Signature ========== */ +-#define SIGNATURE_0 0x1E +-#define SIGNATURE_1 0x96 +-#define SIGNATURE_2 0x4A +- +- +-#endif /* _AVR_ATxmega64D3_H_ */ +- ++/* Copyright (c) 2009-2010 Atmel Corporation ++ All rights reserved. ++ ++ Redistribution and use in source and binary forms, with or without ++ modification, are permitted provided that the following conditions are met: ++ ++ * Redistributions of source code must retain the above copyright ++ notice, this list of conditions and the following disclaimer. ++ ++ * Redistributions in binary form must reproduce the above copyright ++ notice, this list of conditions and the following disclaimer in ++ the documentation and/or other materials provided with the ++ distribution. ++ ++ * Neither the name of the copyright holders nor the names of ++ contributors may be used to endorse or promote products derived ++ from this software without specific prior written permission. ++ ++ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ POSSIBILITY OF SUCH DAMAGE. */ ++ ++/* $Id: iox64d3.h 2194 2010-11-16 15:10:51Z arcanum $ */ ++ ++/* avr/iox64d3.h - definitions for ATxmega64D3 */ ++ ++/* This file should only be included from , never directly. */ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox64d3.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++ ++#ifndef _AVR_ATxmega64D3_H_ ++#define _AVR_ATxmega64D3_H_ 1 ++ ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */ ++#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */ ++#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */ ++#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */ ++#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */ ++#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */ ++#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */ ++#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */ ++#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */ ++#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */ ++#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */ ++#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++} CLK_t; ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t reserved_0x02; ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1kHz from 32kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1kHz from internal 32kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32kHz from 32kHz crystal oscillator on TOSC */ ++} CLK_RTCSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* External Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control REgister */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ ++ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ ++ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */ ++ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */ ++ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t JTAGUID; /* JTAG User ID */ ++ register8_t reserved_0x05; ++ register8_t MCUCR; /* MCU Control */ ++ register8_t reserved_0x07; ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ ++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ ++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ ++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */ ++ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */ ++ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or Capture A */ ++ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */ ++ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */ ++ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or Capture A */ ++ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */ ++ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */ ++ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or Capture A */ ++ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t FUSEBYTE0; /* User ID */ ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2MHz Calibration Value */ ++ register8_t reserved_0x01; ++ register8_t RCOSC32K; /* RCOSC 32kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32MHz Calibration Value */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t ADCBCAL0; /* ADCB Calibration Byte 0 */ ++ register8_t ADCBCAL1; /* ADCB Calibration Byte 1 */ ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t DACAOFFCAL; /* DACA Calibration Byte 0 */ ++ register8_t DACAGAINCAL; /* DACA Calibration Byte 1 */ ++ register8_t DACBOFFCAL; /* DACB Calibration Byte 0 */ ++ register8_t DACBGAINCAL; /* DACB Calibration Byte 1 */ ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++} NVM_PROD_SIGNATURES_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Generate Flash Range CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++} NVM_LB_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_INSAMPLEDMODE_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINOUSLY_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brown Out Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V9_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V1_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V4_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V6_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V9_gc = (0x02<<0), /* 2.7 V */ ++ BODLVL_3V2_gc = (0x01<<0), /* 2.9 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Comparator 0 Control */ ++ register8_t AC1CTRL; /* Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t reserved_0x6; ++ register8_t reserved_0x7; ++} ADC_CH_t; ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++} ADC_t; ++ ++/* Current Limitation */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 225ksps max sampling rate */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 75ksps max sampling rate */ ++} ADC_CURRLIMIT_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x04<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x05<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x06<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x07<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC/1.6V */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++} ADC_REFSEL_t; ++ ++/* Channel sweep selection */ ++typedef enum ADC_SWEEP_enum ++{ ++ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */ ++} ADC_SWEEP_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */ ++ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */ ++ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */ ++ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */ ++ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */ ++ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */ ++ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Clounter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* EBI Chip Select Module */ ++typedef struct EBI_CS_struct ++{ ++ register8_t CTRLA; /* Chip Select Control Register A */ ++ register8_t CTRLB; /* Chip Select Control Register B */ ++ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */ ++} EBI_CS_t; ++ ++/* ++-------------------------------------------------------------------------- ++EBI - External Bus Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* External Bus Interface */ ++typedef struct EBI_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t SDRAMCTRLA; /* SDRAM Control Register A */ ++ register8_t reserved_0x02; ++ register8_t reserved_0x03; ++ _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */ ++ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */ ++ register8_t SDRAMCTRLB; /* SDRAM Control Register B */ ++ register8_t SDRAMCTRLC; /* SDRAM Control Register C */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ EBI_CS_t CS0; /* Chip Select 0 */ ++ EBI_CS_t CS1; /* Chip Select 1 */ ++ EBI_CS_t CS2; /* Chip Select 2 */ ++ EBI_CS_t CS3; /* Chip Select 3 */ ++} EBI_t; ++ ++/* Chip Select adress space */ ++typedef enum EBI_CS_ASIZE_enum ++{ ++ EBI_CS_ASIZE_256B_gc = (0x00<<2), /* 256 bytes */ ++ EBI_CS_ASIZE_512B_gc = (0x01<<2), /* 512 bytes */ ++ EBI_CS_ASIZE_1KB_gc = (0x02<<2), /* 1K bytes */ ++ EBI_CS_ASIZE_2KB_gc = (0x03<<2), /* 2K bytes */ ++ EBI_CS_ASIZE_4KB_gc = (0x04<<2), /* 4K bytes */ ++ EBI_CS_ASIZE_8KB_gc = (0x05<<2), /* 8K bytes */ ++ EBI_CS_ASIZE_16KB_gc = (0x06<<2), /* 16K bytes */ ++ EBI_CS_ASIZE_32KB_gc = (0x07<<2), /* 32K bytes */ ++ EBI_CS_ASIZE_64KB_gc = (0x08<<2), /* 64K bytes */ ++ EBI_CS_ASIZE_128KB_gc = (0x09<<2), /* 128K bytes */ ++ EBI_CS_ASIZE_256KB_gc = (0x0A<<2), /* 256K bytes */ ++ EBI_CS_ASIZE_512KB_gc = (0x0B<<2), /* 512K bytes */ ++ EBI_CS_ASIZE_1MB_gc = (0x0C<<2), /* 1M bytes */ ++ EBI_CS_ASIZE_2MB_gc = (0x0D<<2), /* 2M bytes */ ++ EBI_CS_ASIZE_4MB_gc = (0x0E<<2), /* 4M bytes */ ++ EBI_CS_ASIZE_8MB_gc = (0x0F<<2), /* 8M bytes */ ++ EBI_CS_ASIZE_16M_gc = (0x10<<2), /* 16M bytes */ ++} EBI_CS_ASIZE_t; ++ ++/* */ ++typedef enum EBI_CS_SRWS_enum ++{ ++ EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_CS_SRWS_t; ++ ++/* Chip Select address mode */ ++typedef enum EBI_CS_MODE_enum ++{ ++ EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */ ++ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */ ++ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */ ++ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */ ++} EBI_CS_MODE_t; ++ ++/* Chip Select SDRAM mode */ ++typedef enum EBI_CS_SDMODE_enum ++{ ++ EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */ ++ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */ ++} EBI_CS_SDMODE_t; ++ ++/* */ ++typedef enum EBI_SDDATAW_enum ++{ ++ EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */ ++ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */ ++} EBI_SDDATAW_t; ++ ++/* */ ++typedef enum EBI_LPCMODE_enum ++{ ++ EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */ ++ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */ ++} EBI_LPCMODE_t; ++ ++/* */ ++typedef enum EBI_SRMODE_enum ++{ ++ EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */ ++ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */ ++ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */ ++ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */ ++} EBI_SRMODE_t; ++ ++/* */ ++typedef enum EBI_IFMODE_enum ++{ ++ EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */ ++ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */ ++ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */ ++ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */ ++} EBI_IFMODE_t; ++ ++/* */ ++typedef enum EBI_SDCOL_enum ++{ ++ EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */ ++ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */ ++ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */ ++ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */ ++} EBI_SDCOL_t; ++ ++/* */ ++typedef enum EBI_MRDLY_enum ++{ ++ EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_MRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCYCDLY_enum ++{ ++ EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ROWCYCDLY_t; ++ ++/* */ ++typedef enum EBI_RPDLY_enum ++{ ++ EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_RPDLY_t; ++ ++/* */ ++typedef enum EBI_WRDLY_enum ++{ ++ EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */ ++ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */ ++ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */ ++ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */ ++} EBI_WRDLY_t; ++ ++/* */ ++typedef enum EBI_ESRDLY_enum ++{ ++ EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */ ++ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */ ++ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */ ++ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */ ++ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */ ++ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */ ++ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */ ++ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */ ++} EBI_ESRDLY_t; ++ ++/* */ ++typedef enum EBI_ROWCOLDLY_enum ++{ ++ EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */ ++ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */ ++ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */ ++ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */ ++ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */ ++ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */ ++ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */ ++ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */ ++} EBI_ROWCOLDLY_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++} PORTCFG_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Virtual Port 0 Mapping */ ++typedef enum PORTCFG_VP0MAP_enum ++{ ++ PORTCFG_VP0MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP0MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP0MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP0MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP0MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP0MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP0MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP0MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP0MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP0MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP0MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP0MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP0MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP0MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP0MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP0MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP0MAP_t; ++ ++/* Virtual Port 1 Mapping */ ++typedef enum PORTCFG_VP1MAP_enum ++{ ++ PORTCFG_VP1MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP1MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP1MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP1MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP1MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP1MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP1MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP1MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP1MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP1MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP1MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP1MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP1MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP1MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP1MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP1MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP1MAP_t; ++ ++/* Virtual Port 2 Mapping */ ++typedef enum PORTCFG_VP2MAP_enum ++{ ++ PORTCFG_VP2MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP2MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP2MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP2MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP2MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP2MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP2MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP2MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP2MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP2MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP2MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP2MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP2MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP2MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP2MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP2MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP2MAP_t; ++ ++/* Virtual Port 3 Mapping */ ++typedef enum PORTCFG_VP3MAP_enum ++{ ++ PORTCFG_VP3MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP3MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP3MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP3MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP3MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP3MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP3MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP3MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP3MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP3MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP3MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP3MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP3MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP3MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP3MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP3MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP3MAP_t; ++ ++/* Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x05; ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++ register8_t CTRL; /* Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset Controller */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */ ++#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */ ++#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ ++#define PORTA (*(PORT_t *) 0x0600) /* Port A */ ++#define PORTB (*(PORT_t *) 0x0620) /* Port B */ ++#define PORTC (*(PORT_t *) 0x0640) /* Port C */ ++#define PORTD (*(PORT_t *) 0x0660) /* Port D */ ++#define PORTE (*(PORT_t *) 0x0680) /* Port E */ ++#define PORTF (*(PORT_t *) 0x06A0) /* Port F */ ++#define PORTR (*(PORT_t *) 0x07E0) /* Port R */ ++#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous Receiver-Transmitter C0 */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous Receiver-Transmitter D0 */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */ ++#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */ ++#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous Receiver-Transmitter E0 */ ++#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */ ++#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++#define GPIO_GPIOR4 _SFR_MEM8(0x0004) ++#define GPIO_GPIOR5 _SFR_MEM8(0x0005) ++#define GPIO_GPIOR6 _SFR_MEM8(0x0006) ++#define GPIO_GPIOR7 _SFR_MEM8(0x0007) ++#define GPIO_GPIOR8 _SFR_MEM8(0x0008) ++#define GPIO_GPIOR9 _SFR_MEM8(0x0009) ++#define GPIO_GPIORA _SFR_MEM8(0x000A) ++#define GPIO_GPIORB _SFR_MEM8(0x000B) ++#define GPIO_GPIORC _SFR_MEM8(0x000C) ++#define GPIO_GPIORD _SFR_MEM8(0x000D) ++#define GPIO_GPIORE _SFR_MEM8(0x000E) ++#define GPIO_GPIORF _SFR_MEM8(0x000F) ++ ++/* VPORT0 - Virtual Port 0 */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT1 - Virtual Port 1 */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT2 - Virtual Port 2 */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT3 - Virtual Port 3 */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU Registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator Control */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLLRC32M - DFLL for 32MHz RC Oscillator */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLLRC2M - DFLL for 2MHz RC Oscillator */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset Controller */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_JTAGUID _SFR_MEM8(0x0094) ++#define MCU_MCUCR _SFR_MEM8(0x0096) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - Port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non Volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADCA - Analog to Digital Converter A */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++ ++/* DACB - Digital to Analog Converter B */ ++ ++/* ACA - Analog Comparator A */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* ACB - Analog Comparator B */ ++#define ACB_AC0CTRL _SFR_MEM8(0x0390) ++#define ACB_AC1CTRL _SFR_MEM8(0x0391) ++#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392) ++#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393) ++#define ACB_CTRLA _SFR_MEM8(0x0394) ++#define ACB_CTRLB _SFR_MEM8(0x0395) ++#define ACB_WINCTRL _SFR_MEM8(0x0396) ++#define ACB_STATUS _SFR_MEM8(0x0397) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWIC - Two-Wire Interface C */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0483) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0484) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0485) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0486) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0487) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWIE - Two-Wire Interface E */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* PORTA - Port A */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORTB - Port B */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORTC - Port C */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORTD - Port D */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORTE - Port E */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORTF - Port F */ ++#define PORTF_DIR _SFR_MEM8(0x06A0) ++#define PORTF_DIRSET _SFR_MEM8(0x06A1) ++#define PORTF_DIRCLR _SFR_MEM8(0x06A2) ++#define PORTF_DIRTGL _SFR_MEM8(0x06A3) ++#define PORTF_OUT _SFR_MEM8(0x06A4) ++#define PORTF_OUTSET _SFR_MEM8(0x06A5) ++#define PORTF_OUTCLR _SFR_MEM8(0x06A6) ++#define PORTF_OUTTGL _SFR_MEM8(0x06A7) ++#define PORTF_IN _SFR_MEM8(0x06A8) ++#define PORTF_INTCTRL _SFR_MEM8(0x06A9) ++#define PORTF_INT0MASK _SFR_MEM8(0x06AA) ++#define PORTF_INT1MASK _SFR_MEM8(0x06AB) ++#define PORTF_INTFLAGS _SFR_MEM8(0x06AC) ++#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0) ++#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1) ++#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2) ++#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3) ++#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4) ++#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5) ++#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6) ++#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7) ++ ++/* PORTR - Port R */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TCC0 - Timer/Counter C0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TCC1 - Timer/Counter C1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEXC - Advanced Waveform Extension C */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRESC - High-Resolution Extension C */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* SPIC - Serial Peripheral Interface C */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F8) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_CTRL _SFR_MEM8(0x08FA) ++ ++/* TCD0 - Timer/Counter D0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* SPID - Serial Peripheral Interface D */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TCE0 - Timer/Counter E0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++/* AWEXE - Advanced Waveform Extension E */ ++#define AWEXE_CTRL _SFR_MEM8(0x0A80) ++#define AWEXE_FDEMASK _SFR_MEM8(0x0A82) ++#define AWEXE_FDCTRL _SFR_MEM8(0x0A83) ++#define AWEXE_STATUS _SFR_MEM8(0x0A84) ++#define AWEXE_DTBOTH _SFR_MEM8(0x0A86) ++#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87) ++#define AWEXE_DTLS _SFR_MEM8(0x0A88) ++#define AWEXE_DTHS _SFR_MEM8(0x0A89) ++#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A) ++#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B) ++#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C) ++ ++/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */ ++#define USARTE0_DATA _SFR_MEM8(0x0AA0) ++#define USARTE0_STATUS _SFR_MEM8(0x0AA1) ++#define USARTE0_CTRLA _SFR_MEM8(0x0AA3) ++#define USARTE0_CTRLB _SFR_MEM8(0x0AA4) ++#define USARTE0_CTRLC _SFR_MEM8(0x0AA5) ++#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6) ++#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7) ++ ++/* SPIE - Serial Peripheral Interface E */ ++#define SPIE_CTRL _SFR_MEM8(0x0AC0) ++#define SPIE_INTCTRL _SFR_MEM8(0x0AC1) ++#define SPIE_STATUS _SFR_MEM8(0x0AC2) ++#define SPIE_DATA _SFR_MEM8(0x0AC3) ++ ++/* TCF0 - Timer/Counter F0 */ ++#define TCF0_CTRLA _SFR_MEM8(0x0B00) ++#define TCF0_CTRLB _SFR_MEM8(0x0B01) ++#define TCF0_CTRLC _SFR_MEM8(0x0B02) ++#define TCF0_CTRLD _SFR_MEM8(0x0B03) ++#define TCF0_CTRLE _SFR_MEM8(0x0B04) ++#define TCF0_INTCTRLA _SFR_MEM8(0x0B06) ++#define TCF0_INTCTRLB _SFR_MEM8(0x0B07) ++#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08) ++#define TCF0_CTRLFSET _SFR_MEM8(0x0B09) ++#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A) ++#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B) ++#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C) ++#define TCF0_TEMP _SFR_MEM8(0x0B0F) ++#define TCF0_CNT _SFR_MEM16(0x0B20) ++#define TCF0_PER _SFR_MEM16(0x0B26) ++#define TCF0_CCA _SFR_MEM16(0x0B28) ++#define TCF0_CCB _SFR_MEM16(0x0B2A) ++#define TCF0_CCC _SFR_MEM16(0x0B2C) ++#define TCF0_CCD _SFR_MEM16(0x0B2E) ++#define TCF0_PERBUF _SFR_MEM16(0x0B36) ++#define TCF0_CCABUF _SFR_MEM16(0x0B38) ++#define TCF0_CCBBUF _SFR_MEM16(0x0B3A) ++#define TCF0_CCCBUF _SFR_MEM16(0x0B3C) ++#define TCF0_CCDBUF _SFR_MEM16(0x0B3E) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR1 bit masks and bit positions */ ++#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */ ++#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */ ++ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* RTC Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* RTC Clock Source Enable bit position. */ ++ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ ++#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_SPI_bm Predefined. */ ++/* PR_SPI_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI_bm Predefined. */ ++/* PR_TWI_bp Predefined. */ ++ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_USART0_bm Predefined. */ ++/* PR_USART0_bp Predefined. */ ++ ++/* PR_TC0_bm Predefined. */ ++/* PR_TC0_bp Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2MHz RC Oscillator Enable bit position. */ ++ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2MHz RC Oscillator Ready bit position. */ ++ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_XOSCFDIF_bm 0x02 /* Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* Failure Detection Enable bit position. */ ++ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_bm 0x02 /* 32MHz Calibration Reference bit mask. */ ++#define OSC_RC32MCREF_bp 1 /* 32MHz Calibration Reference bit position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2MHz Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2MHz Calibration Reference bit position. */ ++ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration bits [6:0] group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration bits [6:0] group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration bits [6:0] bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration bits [6:0] bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration bits [6:0] bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration bits [6:0] bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration bits [6:0] bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration bits [6:0] bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration bits [6:0] bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration bits [6:0] bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration bits [6:0] bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration bits [6:0] bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration bits [6:0] bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration bits [6:0] bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration bits [6:0] bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration bits [6:0] bit 6 position. */ ++ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration bits [12:7] group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration bits [12:7] group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration bits [12:7] bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration bits [12:7] bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration bits [12:7] bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration bits [12:7] bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration bits [12:7] bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration bits [12:7] bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration bits [12:7] bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration bits [12:7] bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration bits [12:7] bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration bits [12:7] bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration bits [12:7] bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration bits [12:7] bit 5 position. */ ++ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++ ++/* MCU - MCU Control */ ++/* MCU.MCUCR bit masks and bit positions */ ++#define MCU_JTAGD_bm 0x01 /* JTAG Disable bit mask. */ ++#define MCU_JTAGD_bp 0 /* JTAG Disable bit position. */ ++ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXELOCK_bm 0x04 /* AWeX on T/C E0 Lock bit mask. */ ++#define MCU_AWEXELOCK_bp 2 /* AWeX on T/C E0 Lock bit position. */ ++ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX_gm Predefined. */ ++/* EVSYS_CHMUX_gp Predefined. */ ++/* EVSYS_CHMUX0_bm Predefined. */ ++/* EVSYS_CHMUX0_bp Predefined. */ ++/* EVSYS_CHMUX1_bm Predefined. */ ++/* EVSYS_CHMUX1_bp Predefined. */ ++/* EVSYS_CHMUX2_bm Predefined. */ ++/* EVSYS_CHMUX2_bp Predefined. */ ++/* EVSYS_CHMUX3_bm Predefined. */ ++/* EVSYS_CHMUX3_bp Predefined. */ ++/* EVSYS_CHMUX4_bm Predefined. */ ++/* EVSYS_CHMUX4_bp Predefined. */ ++/* EVSYS_CHMUX5_bm Predefined. */ ++/* EVSYS_CHMUX5_bp Predefined. */ ++/* EVSYS_CHMUX6_bm Predefined. */ ++/* EVSYS_CHMUX6_bp Predefined. */ ++/* EVSYS_CHMUX7_bm Predefined. */ ++/* EVSYS_CHMUX7_bp Predefined. */ ++ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_QDIRM_gm Predefined. */ ++/* EVSYS_QDIRM_gp Predefined. */ ++/* EVSYS_QDIRM0_bm Predefined. */ ++/* EVSYS_QDIRM0_bp Predefined. */ ++/* EVSYS_QDIRM1_bm Predefined. */ ++/* EVSYS_QDIRM1_bp Predefined. */ ++ ++/* EVSYS_QDIEN_bm Predefined. */ ++/* EVSYS_QDIEN_bp Predefined. */ ++ ++/* EVSYS_QDEN_bm Predefined. */ ++/* EVSYS_QDEN_bp Predefined. */ ++ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT_gm Predefined. */ ++/* EVSYS_DIGFILT_gp Predefined. */ ++/* EVSYS_DIGFILT0_bm Predefined. */ ++/* EVSYS_DIGFILT0_bp Predefined. */ ++/* EVSYS_DIGFILT1_bm Predefined. */ ++/* EVSYS_DIGFILT1_bp Predefined. */ ++/* EVSYS_DIGFILT2_bm Predefined. */ ++/* EVSYS_DIGFILT2_bp Predefined. */ ++ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0xFF /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++#define NVM_CMD7_bm (1<<7) /* Command bit 7 mask. */ ++#define NVM_CMD7_bp 7 /* Command bit 7 position. */ ++ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE0 bit masks and bit positions */ ++#define NVM_FUSES_USERID_gm 0xFF /* User ID group mask. */ ++#define NVM_FUSES_USERID_gp 0 /* User ID group position. */ ++#define NVM_FUSES_USERID0_bm (1<<0) /* User ID bit 0 mask. */ ++#define NVM_FUSES_USERID0_bp 0 /* User ID bit 0 position. */ ++#define NVM_FUSES_USERID1_bm (1<<1) /* User ID bit 1 mask. */ ++#define NVM_FUSES_USERID1_bp 1 /* User ID bit 1 position. */ ++#define NVM_FUSES_USERID2_bm (1<<2) /* User ID bit 2 mask. */ ++#define NVM_FUSES_USERID2_bp 2 /* User ID bit 2 position. */ ++#define NVM_FUSES_USERID3_bm (1<<3) /* User ID bit 3 mask. */ ++#define NVM_FUSES_USERID3_bp 3 /* User ID bit 3 position. */ ++#define NVM_FUSES_USERID4_bm (1<<4) /* User ID bit 4 mask. */ ++#define NVM_FUSES_USERID4_bp 4 /* User ID bit 4 position. */ ++#define NVM_FUSES_USERID5_bm (1<<5) /* User ID bit 5 mask. */ ++#define NVM_FUSES_USERID5_bp 5 /* User ID bit 5 position. */ ++#define NVM_FUSES_USERID6_bm (1<<6) /* User ID bit 6 mask. */ ++#define NVM_FUSES_USERID6_bp 6 /* User ID bit 6 position. */ ++#define NVM_FUSES_USERID7_bm (1<<7) /* User ID bit 7 mask. */ ++#define NVM_FUSES_USERID7_bp 7 /* User ID bit 7 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_DVSDON_bm 0x80 /* Spike Detector Enable bit mask. */ ++#define NVM_FUSES_DVSDON_bp 7 /* Spike Detector Enable bit position. */ ++ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ ++ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HSMODE_bm 0x08 /* High-speed Mode bit mask. */ ++#define AC_HSMODE_bp 3 /* High-speed Mode bit position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE_gm Predefined. */ ++/* AC_INTMODE_gp Predefined. */ ++/* AC_INTMODE0_bm Predefined. */ ++/* AC_INTMODE0_bp Predefined. */ ++/* AC_INTMODE1_bm Predefined. */ ++/* AC_INTMODE1_bp Predefined. */ ++ ++/* AC_INTLVL_gm Predefined. */ ++/* AC_INTLVL_gp Predefined. */ ++/* AC_INTLVL0_bm Predefined. */ ++/* AC_INTLVL0_bp Predefined. */ ++/* AC_INTLVL1_bm Predefined. */ ++/* AC_INTLVL1_bp Predefined. */ ++ ++/* AC_HSMODE_bm Predefined. */ ++/* AC_HSMODE_bp Predefined. */ ++ ++/* AC_HYSMODE_gm Predefined. */ ++/* AC_HYSMODE_gp Predefined. */ ++/* AC_HYSMODE0_bm Predefined. */ ++/* AC_HYSMODE0_bp Predefined. */ ++/* AC_HYSMODE1_bm Predefined. */ ++/* AC_HYSMODE1_bp Predefined. */ ++ ++/* AC_ENABLE_bm Predefined. */ ++/* AC_ENABLE_bp Predefined. */ ++ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS_gm Predefined. */ ++/* AC_MUXPOS_gp Predefined. */ ++/* AC_MUXPOS0_bm Predefined. */ ++/* AC_MUXPOS0_bp Predefined. */ ++/* AC_MUXPOS1_bm Predefined. */ ++/* AC_MUXPOS1_bp Predefined. */ ++/* AC_MUXPOS2_bm Predefined. */ ++/* AC_MUXPOS2_bp Predefined. */ ++ ++/* AC_MUXNEG_gm Predefined. */ ++/* AC_MUXNEG_gp Predefined. */ ++/* AC_MUXNEG0_bm Predefined. */ ++/* AC_MUXNEG0_bp Predefined. */ ++/* AC_MUXNEG1_bm Predefined. */ ++/* AC_MUXNEG1_bp Predefined. */ ++/* AC_MUXNEG2_bm Predefined. */ ++/* AC_MUXNEG2_bp Predefined. */ ++ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC0OUT_bm 0x01 /* Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Comparator 0 Output Enable bit position. */ ++ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Comparator 0 Interrupt Flag bit position. */ ++ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAINFAC_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAINFAC_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAINFAC0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAINFAC0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAINFAC1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAINFAC1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAINFAC2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAINFAC2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* Positive Input Select group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* Positive Input Select group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* Positive Input Select bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* Positive Input Select bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* Positive Input Select bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* Positive Input Select bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* Positive Input Select bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* Positive Input Select bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* Positive Input Select bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* Positive Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* Internal Input Select group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* Internal Input Select group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* Internal Input Select bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* Internal Input Select bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* Internal Input Select bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* Internal Input Select bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* Internal Input Select bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* Internal Input Select bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* Internal Input Select bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* Internal Input Select bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* Negative Input Select group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* Negative Input Select group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* Negative Input Select bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* Negative Input Select bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* Negative Input Select bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* Negative Input Select bit 1 position. */ ++ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ ++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x30 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_SWEEP_gm 0xC0 /* Channel Sweep Selection group mask. */ ++#define ADC_SWEEP_gp 6 /* Channel Sweep Selection group position. */ ++#define ADC_SWEEP0_bm (1<<6) /* Channel Sweep Selection bit 0 mask. */ ++#define ADC_SWEEP0_bp 6 /* Channel Sweep Selection bit 0 position. */ ++#define ADC_SWEEP1_bm (1<<7) /* Channel Sweep Selection bit 1 mask. */ ++#define ADC_SWEEP1_bp 7 /* Channel Sweep Selection bit 1 position. */ ++ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++ ++/* RTC - Real-Time Clounter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* EBI - External Bus Interface */ ++/* EBI_CS.CTRLA bit masks and bit positions */ ++#define EBI_CS_ASIZE_gm 0x7C /* Address Size group mask. */ ++#define EBI_CS_ASIZE_gp 2 /* Address Size group position. */ ++#define EBI_CS_ASIZE0_bm (1<<2) /* Address Size bit 0 mask. */ ++#define EBI_CS_ASIZE0_bp 2 /* Address Size bit 0 position. */ ++#define EBI_CS_ASIZE1_bm (1<<3) /* Address Size bit 1 mask. */ ++#define EBI_CS_ASIZE1_bp 3 /* Address Size bit 1 position. */ ++#define EBI_CS_ASIZE2_bm (1<<4) /* Address Size bit 2 mask. */ ++#define EBI_CS_ASIZE2_bp 4 /* Address Size bit 2 position. */ ++#define EBI_CS_ASIZE3_bm (1<<5) /* Address Size bit 3 mask. */ ++#define EBI_CS_ASIZE3_bp 5 /* Address Size bit 3 position. */ ++#define EBI_CS_ASIZE4_bm (1<<6) /* Address Size bit 4 mask. */ ++#define EBI_CS_ASIZE4_bp 6 /* Address Size bit 4 position. */ ++ ++#define EBI_CS_MODE_gm 0x03 /* Memory Mode group mask. */ ++#define EBI_CS_MODE_gp 0 /* Memory Mode group position. */ ++#define EBI_CS_MODE0_bm (1<<0) /* Memory Mode bit 0 mask. */ ++#define EBI_CS_MODE0_bp 0 /* Memory Mode bit 0 position. */ ++#define EBI_CS_MODE1_bm (1<<1) /* Memory Mode bit 1 mask. */ ++#define EBI_CS_MODE1_bp 1 /* Memory Mode bit 1 position. */ ++ ++ ++/* EBI_CS.CTRLB bit masks and bit positions */ ++#define EBI_CS_SRWS_gm 0x07 /* SRAM Wait State Cycles group mask. */ ++#define EBI_CS_SRWS_gp 0 /* SRAM Wait State Cycles group position. */ ++#define EBI_CS_SRWS0_bm (1<<0) /* SRAM Wait State Cycles bit 0 mask. */ ++#define EBI_CS_SRWS0_bp 0 /* SRAM Wait State Cycles bit 0 position. */ ++#define EBI_CS_SRWS1_bm (1<<1) /* SRAM Wait State Cycles bit 1 mask. */ ++#define EBI_CS_SRWS1_bp 1 /* SRAM Wait State Cycles bit 1 position. */ ++#define EBI_CS_SRWS2_bm (1<<2) /* SRAM Wait State Cycles bit 2 mask. */ ++#define EBI_CS_SRWS2_bp 2 /* SRAM Wait State Cycles bit 2 position. */ ++ ++#define EBI_CS_SDINITDONE_bm 0x80 /* SDRAM Initialization Done bit mask. */ ++#define EBI_CS_SDINITDONE_bp 7 /* SDRAM Initialization Done bit position. */ ++ ++#define EBI_CS_SDSREN_bm 0x04 /* SDRAM Self-refresh Enable bit mask. */ ++#define EBI_CS_SDSREN_bp 2 /* SDRAM Self-refresh Enable bit position. */ ++ ++#define EBI_CS_SDMODE_gm 0x03 /* SDRAM Mode group mask. */ ++#define EBI_CS_SDMODE_gp 0 /* SDRAM Mode group position. */ ++#define EBI_CS_SDMODE0_bm (1<<0) /* SDRAM Mode bit 0 mask. */ ++#define EBI_CS_SDMODE0_bp 0 /* SDRAM Mode bit 0 position. */ ++#define EBI_CS_SDMODE1_bm (1<<1) /* SDRAM Mode bit 1 mask. */ ++#define EBI_CS_SDMODE1_bp 1 /* SDRAM Mode bit 1 position. */ ++ ++ ++/* EBI.CTRL bit masks and bit positions */ ++#define EBI_SDDATAW_gm 0xC0 /* SDRAM Data Width Setting group mask. */ ++#define EBI_SDDATAW_gp 6 /* SDRAM Data Width Setting group position. */ ++#define EBI_SDDATAW0_bm (1<<6) /* SDRAM Data Width Setting bit 0 mask. */ ++#define EBI_SDDATAW0_bp 6 /* SDRAM Data Width Setting bit 0 position. */ ++#define EBI_SDDATAW1_bm (1<<7) /* SDRAM Data Width Setting bit 1 mask. */ ++#define EBI_SDDATAW1_bp 7 /* SDRAM Data Width Setting bit 1 position. */ ++ ++#define EBI_LPCMODE_gm 0x30 /* SRAM LPC Mode group mask. */ ++#define EBI_LPCMODE_gp 4 /* SRAM LPC Mode group position. */ ++#define EBI_LPCMODE0_bm (1<<4) /* SRAM LPC Mode bit 0 mask. */ ++#define EBI_LPCMODE0_bp 4 /* SRAM LPC Mode bit 0 position. */ ++#define EBI_LPCMODE1_bm (1<<5) /* SRAM LPC Mode bit 1 mask. */ ++#define EBI_LPCMODE1_bp 5 /* SRAM LPC Mode bit 1 position. */ ++ ++#define EBI_SRMODE_gm 0x0C /* SRAM Mode group mask. */ ++#define EBI_SRMODE_gp 2 /* SRAM Mode group position. */ ++#define EBI_SRMODE0_bm (1<<2) /* SRAM Mode bit 0 mask. */ ++#define EBI_SRMODE0_bp 2 /* SRAM Mode bit 0 position. */ ++#define EBI_SRMODE1_bm (1<<3) /* SRAM Mode bit 1 mask. */ ++#define EBI_SRMODE1_bp 3 /* SRAM Mode bit 1 position. */ ++ ++#define EBI_IFMODE_gm 0x03 /* Interface Mode group mask. */ ++#define EBI_IFMODE_gp 0 /* Interface Mode group position. */ ++#define EBI_IFMODE0_bm (1<<0) /* Interface Mode bit 0 mask. */ ++#define EBI_IFMODE0_bp 0 /* Interface Mode bit 0 position. */ ++#define EBI_IFMODE1_bm (1<<1) /* Interface Mode bit 1 mask. */ ++#define EBI_IFMODE1_bp 1 /* Interface Mode bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLA bit masks and bit positions */ ++#define EBI_SDCAS_bm 0x08 /* SDRAM CAS Latency Setting bit mask. */ ++#define EBI_SDCAS_bp 3 /* SDRAM CAS Latency Setting bit position. */ ++ ++#define EBI_SDROW_bm 0x04 /* SDRAM ROW Bits Setting bit mask. */ ++#define EBI_SDROW_bp 2 /* SDRAM ROW Bits Setting bit position. */ ++ ++#define EBI_SDCOL_gm 0x03 /* SDRAM Column Bits Setting group mask. */ ++#define EBI_SDCOL_gp 0 /* SDRAM Column Bits Setting group position. */ ++#define EBI_SDCOL0_bm (1<<0) /* SDRAM Column Bits Setting bit 0 mask. */ ++#define EBI_SDCOL0_bp 0 /* SDRAM Column Bits Setting bit 0 position. */ ++#define EBI_SDCOL1_bm (1<<1) /* SDRAM Column Bits Setting bit 1 mask. */ ++#define EBI_SDCOL1_bp 1 /* SDRAM Column Bits Setting bit 1 position. */ ++ ++ ++/* EBI.SDRAMCTRLB bit masks and bit positions */ ++#define EBI_MRDLY_gm 0xC0 /* SDRAM Mode Register Delay group mask. */ ++#define EBI_MRDLY_gp 6 /* SDRAM Mode Register Delay group position. */ ++#define EBI_MRDLY0_bm (1<<6) /* SDRAM Mode Register Delay bit 0 mask. */ ++#define EBI_MRDLY0_bp 6 /* SDRAM Mode Register Delay bit 0 position. */ ++#define EBI_MRDLY1_bm (1<<7) /* SDRAM Mode Register Delay bit 1 mask. */ ++#define EBI_MRDLY1_bp 7 /* SDRAM Mode Register Delay bit 1 position. */ ++ ++#define EBI_ROWCYCDLY_gm 0x38 /* SDRAM Row Cycle Delay group mask. */ ++#define EBI_ROWCYCDLY_gp 3 /* SDRAM Row Cycle Delay group position. */ ++#define EBI_ROWCYCDLY0_bm (1<<3) /* SDRAM Row Cycle Delay bit 0 mask. */ ++#define EBI_ROWCYCDLY0_bp 3 /* SDRAM Row Cycle Delay bit 0 position. */ ++#define EBI_ROWCYCDLY1_bm (1<<4) /* SDRAM Row Cycle Delay bit 1 mask. */ ++#define EBI_ROWCYCDLY1_bp 4 /* SDRAM Row Cycle Delay bit 1 position. */ ++#define EBI_ROWCYCDLY2_bm (1<<5) /* SDRAM Row Cycle Delay bit 2 mask. */ ++#define EBI_ROWCYCDLY2_bp 5 /* SDRAM Row Cycle Delay bit 2 position. */ ++ ++#define EBI_RPDLY_gm 0x07 /* SDRAM Row-to-Precharge Delay group mask. */ ++#define EBI_RPDLY_gp 0 /* SDRAM Row-to-Precharge Delay group position. */ ++#define EBI_RPDLY0_bm (1<<0) /* SDRAM Row-to-Precharge Delay bit 0 mask. */ ++#define EBI_RPDLY0_bp 0 /* SDRAM Row-to-Precharge Delay bit 0 position. */ ++#define EBI_RPDLY1_bm (1<<1) /* SDRAM Row-to-Precharge Delay bit 1 mask. */ ++#define EBI_RPDLY1_bp 1 /* SDRAM Row-to-Precharge Delay bit 1 position. */ ++#define EBI_RPDLY2_bm (1<<2) /* SDRAM Row-to-Precharge Delay bit 2 mask. */ ++#define EBI_RPDLY2_bp 2 /* SDRAM Row-to-Precharge Delay bit 2 position. */ ++ ++ ++/* EBI.SDRAMCTRLC bit masks and bit positions */ ++#define EBI_WRDLY_gm 0xC0 /* SDRAM Write Recovery Delay group mask. */ ++#define EBI_WRDLY_gp 6 /* SDRAM Write Recovery Delay group position. */ ++#define EBI_WRDLY0_bm (1<<6) /* SDRAM Write Recovery Delay bit 0 mask. */ ++#define EBI_WRDLY0_bp 6 /* SDRAM Write Recovery Delay bit 0 position. */ ++#define EBI_WRDLY1_bm (1<<7) /* SDRAM Write Recovery Delay bit 1 mask. */ ++#define EBI_WRDLY1_bp 7 /* SDRAM Write Recovery Delay bit 1 position. */ ++ ++#define EBI_ESRDLY_gm 0x38 /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */ ++#define EBI_ESRDLY_gp 3 /* SDRAM Exit-Self-refresh-to-Active Delay group position. */ ++#define EBI_ESRDLY0_bm (1<<3) /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */ ++#define EBI_ESRDLY0_bp 3 /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */ ++#define EBI_ESRDLY1_bm (1<<4) /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */ ++#define EBI_ESRDLY1_bp 4 /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */ ++#define EBI_ESRDLY2_bm (1<<5) /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */ ++#define EBI_ESRDLY2_bp 5 /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */ ++ ++#define EBI_ROWCOLDLY_gm 0x07 /* SDRAM Row-to-Column Delay group mask. */ ++#define EBI_ROWCOLDLY_gp 0 /* SDRAM Row-to-Column Delay group position. */ ++#define EBI_ROWCOLDLY0_bm (1<<0) /* SDRAM Row-to-Column Delay bit 0 mask. */ ++#define EBI_ROWCOLDLY0_bp 0 /* SDRAM Row-to-Column Delay bit 0 position. */ ++#define EBI_ROWCOLDLY1_bm (1<<1) /* SDRAM Row-to-Column Delay bit 1 mask. */ ++#define EBI_ROWCOLDLY1_bp 1 /* SDRAM Row-to-Column Delay bit 1 position. */ ++#define EBI_ROWCOLDLY2_bm (1<<2) /* SDRAM Row-to-Column Delay bit 2 mask. */ ++#define EBI_ROWCOLDLY2_bp 2 /* SDRAM Row-to-Column Delay bit 2 position. */ ++ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_bm 0x02 /* SDA Hold Time Enable bit mask. */ ++#define TWI_SDAHOLD_bp 1 /* SDA Hold Time Enable bit position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++ ++/* PORT - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN_bm Predefined. */ ++/* PORT_SRLEN_bp Predefined. */ ++ ++/* PORT_INVEN_bm Predefined. */ ++/* PORT_INVEN_bp Predefined. */ ++ ++/* PORT_OPC_gm Predefined. */ ++/* PORT_OPC_gp Predefined. */ ++/* PORT_OPC0_bm Predefined. */ ++/* PORT_OPC0_bp Predefined. */ ++/* PORT_OPC1_bm Predefined. */ ++/* PORT_OPC1_bp Predefined. */ ++/* PORT_OPC2_bm Predefined. */ ++/* PORT_OPC2_bp Predefined. */ ++ ++/* PORT_ISC_gm Predefined. */ ++/* PORT_ISC_gp Predefined. */ ++/* PORT_ISC0_bm Predefined. */ ++/* PORT_ISC0_bp Predefined. */ ++/* PORT_ISC1_bm Predefined. */ ++/* PORT_ISC1_bp Predefined. */ ++/* PORT_ISC2_bm Predefined. */ ++/* PORT_ISC2_bp Predefined. */ ++ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC0_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD_gm Predefined. */ ++/* TC0_CMD_gp Predefined. */ ++/* TC0_CMD0_bm Predefined. */ ++/* TC0_CMD0_bp Predefined. */ ++/* TC0_CMD1_bm Predefined. */ ++/* TC0_CMD1_bp Predefined. */ ++ ++/* TC0_LUPD_bm Predefined. */ ++/* TC0_LUPD_bp Predefined. */ ++ ++/* TC0_DIR_bm Predefined. */ ++/* TC0_DIR_bp Predefined. */ ++ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV_bm Predefined. */ ++/* TC0_CCDBV_bp Predefined. */ ++ ++/* TC0_CCCBV_bm Predefined. */ ++/* TC0_CCCBV_bp Predefined. */ ++ ++/* TC0_CCBBV_bm Predefined. */ ++/* TC0_CCBBV_bp Predefined. */ ++ ++/* TC0_CCABV_bm Predefined. */ ++/* TC0_CCABV_bp Predefined. */ ++ ++/* TC0_PERBV_bm Predefined. */ ++/* TC0_PERBV_bp Predefined. */ ++ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD_gm Predefined. */ ++/* TC1_CMD_gp Predefined. */ ++/* TC1_CMD0_bm Predefined. */ ++/* TC1_CMD0_bp Predefined. */ ++/* TC1_CMD1_bm Predefined. */ ++/* TC1_CMD1_bp Predefined. */ ++ ++/* TC1_LUPD_bm Predefined. */ ++/* TC1_LUPD_bp Predefined. */ ++ ++/* TC1_DIR_bm Predefined. */ ++/* TC1_DIR_bp Predefined. */ ++ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV_bm Predefined. */ ++/* TC1_CCBBV_bp Predefined. */ ++ ++/* TC1_CCABV_bm Predefined. */ ++/* TC1_CCABV_bp Predefined. */ ++ ++/* TC1_PERBV_bm Predefined. */ ++/* TC1_PERBV_bp Predefined. */ ++ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL_gm Predefined. */ ++/* USART_BSEL_gp Predefined. */ ++/* USART_BSEL0_bm Predefined. */ ++/* USART_BSEL0_bp Predefined. */ ++/* USART_BSEL1_bm Predefined. */ ++/* USART_BSEL1_bp Predefined. */ ++/* USART_BSEL2_bm Predefined. */ ++/* USART_BSEL2_bp Predefined. */ ++/* USART_BSEL3_bm Predefined. */ ++/* USART_BSEL3_bp Predefined. */ ++ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_XOSCF_vect_num 1 ++#define OSC_XOSCF_vect _VECTOR(1) /* External Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++/* PORTF interrupt vectors */ ++#define PORTF_INT0_vect_num 104 ++#define PORTF_INT0_vect _VECTOR(104) /* External Interrupt 0 */ ++#define PORTF_INT1_vect_num 105 ++#define PORTF_INT1_vect _VECTOR(105) /* External Interrupt 1 */ ++ ++/* TCF0 interrupt vectors */ ++#define TCF0_OVF_vect_num 108 ++#define TCF0_OVF_vect _VECTOR(108) /* Overflow Interrupt */ ++#define TCF0_ERR_vect_num 109 ++#define TCF0_ERR_vect _VECTOR(109) /* Error Interrupt */ ++#define TCF0_CCA_vect_num 110 ++#define TCF0_CCA_vect _VECTOR(110) /* Compare or Capture A Interrupt */ ++#define TCF0_CCB_vect_num 111 ++#define TCF0_CCB_vect _VECTOR(111) /* Compare or Capture B Interrupt */ ++#define TCF0_CCC_vect_num 112 ++#define TCF0_CCC_vect _VECTOR(112) /* Compare or Capture C Interrupt */ ++#define TCF0_CCD_vect_num 113 ++#define TCF0_CCD_vect _VECTOR(113) /* Compare or Capture D Interrupt */ ++ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (114 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (69632) ++#define PROGMEM_PAGE_SIZE (256) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (65536) ++#define APP_SECTION_PAGE_SIZE (256) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x0F000) ++#define APPTABLE_SECTION_SIZE (4096) ++#define APPTABLE_SECTION_PAGE_SIZE (256) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x10000) ++#define BOOT_SECTION_SIZE (4096) ++#define BOOT_SECTION_PAGE_SIZE (256) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (12288) ++#define DATAMEM_PAGE_SIZE (0) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (2048) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (4096) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (2048) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define FUSE_START (0x0000) ++#define FUSE_SIZE (6) ++#define FUSE_PAGE_SIZE (0) ++#define FUSE_END (FUSE_START + FUSE_SIZE - 1) ++ ++#define LOCKBIT_START (0x0000) ++#define LOCKBIT_SIZE (1) ++#define LOCKBIT_PAGE_SIZE (0) ++#define LOCKBIT_END (LOCKBIT_START + LOCKBIT_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (256) ++#define USER_SIGNATURES_PAGE_SIZE (0) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (0) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE PROGMEM_PAGE_SIZE ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define XRAMSTART EXTERNAL_SRAM_START ++#define XRAMSIZE EXTERNAL_SRAM_SIZE ++#define XRAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 */ ++#define FUSE_USERID0 (unsigned char)~_BV(0) /* User ID Bit 0 */ ++#define FUSE_USERID1 (unsigned char)~_BV(1) /* User ID Bit 1 */ ++#define FUSE_USERID2 (unsigned char)~_BV(2) /* User ID Bit 2 */ ++#define FUSE_USERID3 (unsigned char)~_BV(3) /* User ID Bit 3 */ ++#define FUSE_USERID4 (unsigned char)~_BV(4) /* User ID Bit 4 */ ++#define FUSE_USERID5 (unsigned char)~_BV(5) /* User ID Bit 5 */ ++#define FUSE_USERID6 (unsigned char)~_BV(6) /* User ID Bit 6 */ ++#define FUSE_USERID7 (unsigned char)~_BV(7) /* User ID Bit 7 */ ++#define FUSE0_DEFAULT (0xFF) ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE_DVSDON (unsigned char)~_BV(7) /* Spike Detector Enable */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x4A ++ ++ ++#endif /* _AVR_ATxmega64D3_H_ */ ++ diff --git a/include/avr/iox64d4.h b/include/avr/iox64d4.h new file mode 100644 -index 0000000..1d24dd8 +index 0000000..1516983 --- /dev/null +++ b/include/avr/iox64d4.h -@@ -0,0 +1,5515 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox64d4.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA64D4_H_INCLUDED -+#define _AVR_ATXMEGA64D4_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+VPORT - Virtual Ports -+-------------------------------------------------------------------------- -+*/ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t reserved_0x04; -+} CLK_t; -+ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t reserved_0x02; -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t PRPD; /* Power Reduction Port D */ -+ register8_t PRPE; /* Power Reduction Port E */ -+ register8_t PRPF; /* Power Reduction Port F */ -+} PR_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from 32.768 kHz internal oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from 32.768 kHz internal oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control Register */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+/* 2 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC2MCREF_enum -+{ -+ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC2MCREF_t; -+ -+/* 32 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC32MCREF_enum -+{ -+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC32MCREF_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t ANAINIT; /* Analog Startup Delay */ -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t AWEXLOCK; /* AWEX Lock */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORTCFG - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t VPCTRLA; /* Virtual Port Control Register A */ -+ register8_t VPCTRLB; /* Virtual Port Control Register B */ -+ register8_t CLKEVOUT; /* Clock and Event Out Register */ -+ register8_t reserved_0x05; -+ register8_t EVOUTSEL; /* Event Output Select */ -+} PORTCFG_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP02MAP_enum -+{ -+ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ -+ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ -+ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ -+ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ -+ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ -+ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ -+ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ -+ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ -+ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ -+ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ -+ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ -+ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ -+ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ -+ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ -+ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ -+ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ -+} PORTCFG_VP02MAP_t; -+ -+/* Virtual Port Mapping */ -+typedef enum PORTCFG_VP13MAP_enum -+{ -+ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ -+ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ -+ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ -+ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ -+ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ -+ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ -+ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ -+ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ -+ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ -+ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ -+ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ -+ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ -+ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ -+ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ -+ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ -+ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ -+} PORTCFG_VP13MAP_t; -+ -+/* System Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ -+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ -+ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ -+} PORTCFG_CLKOUT_t; -+ -+/* Peripheral Clock Output Select */ -+typedef enum PORTCFG_CLKOUTSEL_enum -+{ -+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -+} PORTCFG_CLKOUTSEL_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ -+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ -+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ -+} PORTCFG_EVOUT_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+} EVSYS_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ -+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ -+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ -+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ -+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ -+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ -+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ -+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ -+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ -+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ -+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ -+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ -+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ -+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ -+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ -+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ -+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ -+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ -+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ -+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ -+ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ -+ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ -+ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ -+ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ -+ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ -+ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ -+ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ -+ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ -+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ -+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ -+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ -+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ -+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ -+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ -+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ -+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ -+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ -+ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ -+ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ -+ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ -+ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ -+ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ -+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ -+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ -+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ -+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ -+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ -+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ -+ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ -+ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ -+ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ -+ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ -+ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ -+ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ -+} EVSYS_CHMUX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ -+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ -+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ -+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ -+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} NVM_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t reserved_0x07; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+} ADC_t; -+ -+/* Current Limitation */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -+} ADC_CURRLIMIT_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+} ADC_CH_MUXNEG_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ -+ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ -+ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ -+ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC - Real-Time Counter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Real-Time Counter */ -+typedef struct RTC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary register */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ _WORDREGISTER(CNT); /* Count Register */ -+ _WORDREGISTER(PER); /* Period Register */ -+ _WORDREGISTER(COMP); /* Compare Register */ -+} RTC_t; -+ -+/* Prescaler Factor */ -+typedef enum RTC_PRESCALER_enum -+{ -+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ -+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ -+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ -+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ -+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ -+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ -+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ -+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -+} RTC_PRESCALER_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC_COMPINTLVL_enum -+{ -+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC_OVFINTLVL_enum -+{ -+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+} TWI_t; -+ -+/* SDA Hold Time */ -+typedef enum TWI_SDAHOLD_enum -+{ -+ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ -+ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ -+ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ -+ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ -+} TWI_SDAHOLD_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - I/O Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INT0MASK; /* Port Interrupt 0 Mask */ -+ register8_t INT1MASK; /* Port Interrupt 1 Mask */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t REMAP; /* I/O Port Pin Remap Register */ -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Port Interrupt 0 Level */ -+typedef enum PORT_INT0LVL_enum -+{ -+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INT0LVL_t; -+ -+/* Port Interrupt 1 Level */ -+typedef enum PORT_INT1LVL_enum -+{ -+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ -+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ -+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ -+} PORT_INT1LVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 0 */ -+typedef struct TC0_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC0_t; -+ -+ -+/* 16-bit Timer/Counter 1 */ -+typedef struct TC1_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLFCLR; /* Control Register F Clear */ -+ register8_t CTRLFSET; /* Control Register F Set */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+} TC1_t; -+ -+/* Clock Selection */ -+typedef enum TC_CLKSEL_enum -+{ -+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_CLKSEL_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC_WGMODE_enum -+{ -+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ -+ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ -+ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC_WGMODE_t; -+ -+/* Byte Mode */ -+typedef enum TC_BYTEM_enum -+{ -+ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ -+ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ -+} TC_BYTEM_t; -+ -+/* Event Action */ -+typedef enum TC_EVACT_enum -+{ -+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ -+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ -+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ -+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ -+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ -+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC_EVSEL_enum -+{ -+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC_EVSEL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC_ERRINTLVL_enum -+{ -+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC_OVFINTLVL_enum -+{ -+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_OVFINTLVL_t; -+ -+/* Compare or Capture D Interrupt Level */ -+typedef enum TC_CCDINTLVL_enum -+{ -+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC_CCDINTLVL_t; -+ -+/* Compare or Capture C Interrupt Level */ -+typedef enum TC_CCCINTLVL_enum -+{ -+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC_CCCINTLVL_t; -+ -+/* Compare or Capture B Interrupt Level */ -+typedef enum TC_CCBINTLVL_enum -+{ -+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC_CCBINTLVL_t; -+ -+/* Compare or Capture A Interrupt Level */ -+typedef enum TC_CCAINTLVL_enum -+{ -+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC_CCAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC_CMD_enum -+{ -+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC2 - 16-bit Timer/Counter type 2 -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter type 2 */ -+typedef struct TC2_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t reserved_0x03; -+ register8_t CTRLE; /* Control Register E */ -+ register8_t reserved_0x05; -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t reserved_0x08; -+ register8_t CTRLF; /* Control Register F */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t LCNT; /* Low Byte Count */ -+ register8_t HCNT; /* High Byte Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t LPER; /* Low Byte Period */ -+ register8_t HPER; /* High Byte Period */ -+ register8_t LCMPA; /* Low Byte Compare A */ -+ register8_t HCMPA; /* High Byte Compare A */ -+ register8_t LCMPB; /* Low Byte Compare B */ -+ register8_t HCMPB; /* High Byte Compare B */ -+ register8_t LCMPC; /* Low Byte Compare C */ -+ register8_t HCMPC; /* High Byte Compare C */ -+ register8_t LCMPD; /* Low Byte Compare D */ -+ register8_t HCMPD; /* High Byte Compare D */ -+} TC2_t; -+ -+/* Clock Selection */ -+typedef enum TC2_CLKSEL_enum -+{ -+ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+} TC2_CLKSEL_t; -+ -+/* Byte Mode */ -+typedef enum TC2_BYTEM_enum -+{ -+ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ -+ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ -+ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ -+} TC2_BYTEM_t; -+ -+/* High Byte Underflow Interrupt Level */ -+typedef enum TC2_HUNFINTLVL_enum -+{ -+ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_HUNFINTLVL_t; -+ -+/* Low Byte Underflow Interrupt Level */ -+typedef enum TC2_LUNFINTLVL_enum -+{ -+ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LUNFINTLVL_t; -+ -+/* Low Byte Compare D Interrupt Level */ -+typedef enum TC2_LCMPDINTLVL_enum -+{ -+ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC2_LCMPDINTLVL_t; -+ -+/* Low Byte Compare C Interrupt Level */ -+typedef enum TC2_LCMPCINTLVL_enum -+{ -+ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC2_LCMPCINTLVL_t; -+ -+/* Low Byte Compare B Interrupt Level */ -+typedef enum TC2_LCMPBINTLVL_enum -+{ -+ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC2_LCMPBINTLVL_t; -+ -+/* Low Byte Compare A Interrupt Level */ -+typedef enum TC2_LCMPAINTLVL_enum -+{ -+ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC2_LCMPAINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMD_enum -+{ -+ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC2_CMD_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC2_CMDEN_enum -+{ -+ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ -+ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ -+ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ -+} TC2_CMDEN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AWEX - Timer/Counter Advanced Waveform Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Advanced Waveform Extension */ -+typedef struct AWEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t FDEMASK; /* Fault Detection Event Mask */ -+ register8_t FDCTRL; /* Fault Detection Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t STATUSSET; /* Status Set Register */ -+ register8_t DTBOTH; /* Dead Time Both Sides */ -+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ -+ register8_t DTLS; /* Dead Time Low Side */ -+ register8_t DTHS; /* Dead Time High Side */ -+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ -+ register8_t DTHSBUF; /* Dead Time High Side Buffer */ -+ register8_t OUTOVEN; /* Output Override Enable */ -+} AWEX_t; -+ -+/* Fault Detect Action */ -+typedef enum AWEX_FDACT_enum -+{ -+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ -+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ -+} AWEX_FDACT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+HIRES - Timer/Counter High-Resolution Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register */ -+} HIRES_t; -+ -+/* High Resolution Enable */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ -+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ -+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+} IRDA_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t reserved_0x00; -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+} NVM_FUSES_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* Timer Oscillator pin location */ -+typedef enum TOSCSEL_enum -+{ -+ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ -+ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ -+} TOSCSEL_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ -+} BOD_t; -+ -+/* BOD operation */ -+typedef enum BODACT_enum -+{ -+ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BODACT_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WDP_enum -+{ -+ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ -+ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ -+ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ -+ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ -+ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ -+ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ -+ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ -+ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ -+ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ -+ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ -+ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ -+} WDP_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+LOCKBIT - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ -+ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t reserved_0x28; -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+} NVM_PROD_SIGNATURES_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ -+#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ -+#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ -+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ -+#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ -+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ -+#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* DFLL - DFLL */ -+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) -+#define DFLLRC2M_CALA _SFR_MEM8(0x006A) -+#define DFLLRC2M_CALB _SFR_MEM8(0x006B) -+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) -+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) -+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPD _SFR_MEM8(0x0074) -+#define PR_PRPE _SFR_MEM8(0x0075) -+#define PR_PRPF _SFR_MEM8(0x0076) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_ANAINIT _SFR_MEM8(0x0097) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_AWEXLOCK _SFR_MEM8(0x0099) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) -+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) -+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCA_CTRLA _SFR_MEM8(0x0200) -+#define ADCA_CTRLB _SFR_MEM8(0x0201) -+#define ADCA_REFCTRL _SFR_MEM8(0x0202) -+#define ADCA_EVCTRL _SFR_MEM8(0x0203) -+#define ADCA_PRESCALER _SFR_MEM8(0x0204) -+#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -+#define ADCA_TEMP _SFR_MEM8(0x0207) -+#define ADCA_CAL _SFR_MEM16(0x020C) -+#define ADCA_CH0RES _SFR_MEM16(0x0210) -+#define ADCA_CMP _SFR_MEM16(0x0218) -+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -+#define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -+ -+/* AC - Analog Comparator */ -+#define ACA_AC0CTRL _SFR_MEM8(0x0380) -+#define ACA_AC1CTRL _SFR_MEM8(0x0381) -+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -+#define ACA_CTRLA _SFR_MEM8(0x0384) -+#define ACA_CTRLB _SFR_MEM8(0x0385) -+#define ACA_WINCTRL _SFR_MEM8(0x0386) -+#define ACA_STATUS _SFR_MEM8(0x0387) -+ -+/* RTC - Real-Time Counter */ -+#define RTC_CTRL _SFR_MEM8(0x0400) -+#define RTC_STATUS _SFR_MEM8(0x0401) -+#define RTC_INTCTRL _SFR_MEM8(0x0402) -+#define RTC_INTFLAGS _SFR_MEM8(0x0403) -+#define RTC_TEMP _SFR_MEM8(0x0404) -+#define RTC_CNT _SFR_MEM16(0x0408) -+#define RTC_PER _SFR_MEM16(0x040A) -+#define RTC_COMP _SFR_MEM16(0x040C) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIE_CTRL _SFR_MEM8(0x04A0) -+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) -+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) -+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) -+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) -+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) -+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) -+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) -+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) -+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) -+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) -+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) -+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) -+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) -+ -+/* PORT - I/O Ports */ -+#define PORTA_DIR _SFR_MEM8(0x0600) -+#define PORTA_DIRSET _SFR_MEM8(0x0601) -+#define PORTA_DIRCLR _SFR_MEM8(0x0602) -+#define PORTA_DIRTGL _SFR_MEM8(0x0603) -+#define PORTA_OUT _SFR_MEM8(0x0604) -+#define PORTA_OUTSET _SFR_MEM8(0x0605) -+#define PORTA_OUTCLR _SFR_MEM8(0x0606) -+#define PORTA_OUTTGL _SFR_MEM8(0x0607) -+#define PORTA_IN _SFR_MEM8(0x0608) -+#define PORTA_INTCTRL _SFR_MEM8(0x0609) -+#define PORTA_INT0MASK _SFR_MEM8(0x060A) -+#define PORTA_INT1MASK _SFR_MEM8(0x060B) -+#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_REMAP _SFR_MEM8(0x060E) -+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -+ -+/* PORT - I/O Ports */ -+#define PORTB_DIR _SFR_MEM8(0x0620) -+#define PORTB_DIRSET _SFR_MEM8(0x0621) -+#define PORTB_DIRCLR _SFR_MEM8(0x0622) -+#define PORTB_DIRTGL _SFR_MEM8(0x0623) -+#define PORTB_OUT _SFR_MEM8(0x0624) -+#define PORTB_OUTSET _SFR_MEM8(0x0625) -+#define PORTB_OUTCLR _SFR_MEM8(0x0626) -+#define PORTB_OUTTGL _SFR_MEM8(0x0627) -+#define PORTB_IN _SFR_MEM8(0x0628) -+#define PORTB_INTCTRL _SFR_MEM8(0x0629) -+#define PORTB_INT0MASK _SFR_MEM8(0x062A) -+#define PORTB_INT1MASK _SFR_MEM8(0x062B) -+#define PORTB_INTFLAGS _SFR_MEM8(0x062C) -+#define PORTB_REMAP _SFR_MEM8(0x062E) -+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) -+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) -+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) -+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) -+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) -+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) -+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) -+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INT0MASK _SFR_MEM8(0x064A) -+#define PORTC_INT1MASK _SFR_MEM8(0x064B) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INT0MASK _SFR_MEM8(0x066A) -+#define PORTD_INT1MASK _SFR_MEM8(0x066B) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTE_DIR _SFR_MEM8(0x0680) -+#define PORTE_DIRSET _SFR_MEM8(0x0681) -+#define PORTE_DIRCLR _SFR_MEM8(0x0682) -+#define PORTE_DIRTGL _SFR_MEM8(0x0683) -+#define PORTE_OUT _SFR_MEM8(0x0684) -+#define PORTE_OUTSET _SFR_MEM8(0x0685) -+#define PORTE_OUTCLR _SFR_MEM8(0x0686) -+#define PORTE_OUTTGL _SFR_MEM8(0x0687) -+#define PORTE_IN _SFR_MEM8(0x0688) -+#define PORTE_INTCTRL _SFR_MEM8(0x0689) -+#define PORTE_INT0MASK _SFR_MEM8(0x068A) -+#define PORTE_INT1MASK _SFR_MEM8(0x068B) -+#define PORTE_INTFLAGS _SFR_MEM8(0x068C) -+#define PORTE_REMAP _SFR_MEM8(0x068E) -+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) -+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) -+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) -+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) -+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) -+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) -+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) -+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INT0MASK _SFR_MEM8(0x07EA) -+#define PORTR_INT1MASK _SFR_MEM8(0x07EB) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCC0_CTRLA _SFR_MEM8(0x0800) -+#define TCC0_CTRLB _SFR_MEM8(0x0801) -+#define TCC0_CTRLC _SFR_MEM8(0x0802) -+#define TCC0_CTRLD _SFR_MEM8(0x0803) -+#define TCC0_CTRLE _SFR_MEM8(0x0804) -+#define TCC0_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC0_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) -+#define TCC0_CTRLFSET _SFR_MEM8(0x0809) -+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) -+#define TCC0_CTRLGSET _SFR_MEM8(0x080B) -+#define TCC0_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC0_TEMP _SFR_MEM8(0x080F) -+#define TCC0_CNT _SFR_MEM16(0x0820) -+#define TCC0_PER _SFR_MEM16(0x0826) -+#define TCC0_CCA _SFR_MEM16(0x0828) -+#define TCC0_CCB _SFR_MEM16(0x082A) -+#define TCC0_CCC _SFR_MEM16(0x082C) -+#define TCC0_CCD _SFR_MEM16(0x082E) -+#define TCC0_PERBUF _SFR_MEM16(0x0836) -+#define TCC0_CCABUF _SFR_MEM16(0x0838) -+#define TCC0_CCBBUF _SFR_MEM16(0x083A) -+#define TCC0_CCCBUF _SFR_MEM16(0x083C) -+#define TCC0_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCC2_CTRLA _SFR_MEM8(0x0800) -+#define TCC2_CTRLB _SFR_MEM8(0x0801) -+#define TCC2_CTRLC _SFR_MEM8(0x0802) -+#define TCC2_CTRLE _SFR_MEM8(0x0804) -+#define TCC2_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC2_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC2_CTRLF _SFR_MEM8(0x0809) -+#define TCC2_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC2_LCNT _SFR_MEM8(0x0820) -+#define TCC2_HCNT _SFR_MEM8(0x0821) -+#define TCC2_LPER _SFR_MEM8(0x0826) -+#define TCC2_HPER _SFR_MEM8(0x0827) -+#define TCC2_LCMPA _SFR_MEM8(0x0828) -+#define TCC2_HCMPA _SFR_MEM8(0x0829) -+#define TCC2_LCMPB _SFR_MEM8(0x082A) -+#define TCC2_HCMPB _SFR_MEM8(0x082B) -+#define TCC2_LCMPC _SFR_MEM8(0x082C) -+#define TCC2_HCMPC _SFR_MEM8(0x082D) -+#define TCC2_LCMPD _SFR_MEM8(0x082E) -+#define TCC2_HCMPD _SFR_MEM8(0x082F) -+ -+/* TC1 - 16-bit Timer/Counter 1 */ -+#define TCC1_CTRLA _SFR_MEM8(0x0840) -+#define TCC1_CTRLB _SFR_MEM8(0x0841) -+#define TCC1_CTRLC _SFR_MEM8(0x0842) -+#define TCC1_CTRLD _SFR_MEM8(0x0843) -+#define TCC1_CTRLE _SFR_MEM8(0x0844) -+#define TCC1_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC1_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) -+#define TCC1_CTRLFSET _SFR_MEM8(0x0849) -+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) -+#define TCC1_CTRLGSET _SFR_MEM8(0x084B) -+#define TCC1_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC1_TEMP _SFR_MEM8(0x084F) -+#define TCC1_CNT _SFR_MEM16(0x0860) -+#define TCC1_PER _SFR_MEM16(0x0866) -+#define TCC1_CCA _SFR_MEM16(0x0868) -+#define TCC1_CCB _SFR_MEM16(0x086A) -+#define TCC1_PERBUF _SFR_MEM16(0x0876) -+#define TCC1_CCABUF _SFR_MEM16(0x0878) -+#define TCC1_CCBBUF _SFR_MEM16(0x087A) -+ -+/* AWEX - Advanced Waveform Extension */ -+#define AWEXC_CTRL _SFR_MEM8(0x0880) -+#define AWEXC_FDEMASK _SFR_MEM8(0x0882) -+#define AWEXC_FDCTRL _SFR_MEM8(0x0883) -+#define AWEXC_STATUS _SFR_MEM8(0x0884) -+#define AWEXC_STATUSSET _SFR_MEM8(0x0885) -+#define AWEXC_DTBOTH _SFR_MEM8(0x0886) -+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) -+#define AWEXC_DTLS _SFR_MEM8(0x0888) -+#define AWEXC_DTHS _SFR_MEM8(0x0889) -+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) -+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) -+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x0890) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08A0) -+#define USARTC0_STATUS _SFR_MEM8(0x08A1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08A3) -+#define USARTC0_CTRLB _SFR_MEM8(0x08A4) -+#define USARTC0_CTRLC _SFR_MEM8(0x08A5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPIC_CTRL _SFR_MEM8(0x08C0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08C1) -+#define SPIC_STATUS _SFR_MEM8(0x08C2) -+#define SPIC_DATA _SFR_MEM8(0x08C3) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCD0_CTRLA _SFR_MEM8(0x0900) -+#define TCD0_CTRLB _SFR_MEM8(0x0901) -+#define TCD0_CTRLC _SFR_MEM8(0x0902) -+#define TCD0_CTRLD _SFR_MEM8(0x0903) -+#define TCD0_CTRLE _SFR_MEM8(0x0904) -+#define TCD0_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD0_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) -+#define TCD0_CTRLFSET _SFR_MEM8(0x0909) -+#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) -+#define TCD0_CTRLGSET _SFR_MEM8(0x090B) -+#define TCD0_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD0_TEMP _SFR_MEM8(0x090F) -+#define TCD0_CNT _SFR_MEM16(0x0920) -+#define TCD0_PER _SFR_MEM16(0x0926) -+#define TCD0_CCA _SFR_MEM16(0x0928) -+#define TCD0_CCB _SFR_MEM16(0x092A) -+#define TCD0_CCC _SFR_MEM16(0x092C) -+#define TCD0_CCD _SFR_MEM16(0x092E) -+#define TCD0_PERBUF _SFR_MEM16(0x0936) -+#define TCD0_CCABUF _SFR_MEM16(0x0938) -+#define TCD0_CCBBUF _SFR_MEM16(0x093A) -+#define TCD0_CCCBUF _SFR_MEM16(0x093C) -+#define TCD0_CCDBUF _SFR_MEM16(0x093E) -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+#define TCD2_CTRLA _SFR_MEM8(0x0900) -+#define TCD2_CTRLB _SFR_MEM8(0x0901) -+#define TCD2_CTRLC _SFR_MEM8(0x0902) -+#define TCD2_CTRLE _SFR_MEM8(0x0904) -+#define TCD2_INTCTRLA _SFR_MEM8(0x0906) -+#define TCD2_INTCTRLB _SFR_MEM8(0x0907) -+#define TCD2_CTRLF _SFR_MEM8(0x0909) -+#define TCD2_INTFLAGS _SFR_MEM8(0x090C) -+#define TCD2_LCNT _SFR_MEM8(0x0920) -+#define TCD2_HCNT _SFR_MEM8(0x0921) -+#define TCD2_LPER _SFR_MEM8(0x0926) -+#define TCD2_HPER _SFR_MEM8(0x0927) -+#define TCD2_LCMPA _SFR_MEM8(0x0928) -+#define TCD2_HCMPA _SFR_MEM8(0x0929) -+#define TCD2_LCMPB _SFR_MEM8(0x092A) -+#define TCD2_HCMPB _SFR_MEM8(0x092B) -+#define TCD2_LCMPC _SFR_MEM8(0x092C) -+#define TCD2_HCMPC _SFR_MEM8(0x092D) -+#define TCD2_LCMPD _SFR_MEM8(0x092E) -+#define TCD2_HCMPD _SFR_MEM8(0x092F) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD0_DATA _SFR_MEM8(0x09A0) -+#define USARTD0_STATUS _SFR_MEM8(0x09A1) -+#define USARTD0_CTRLA _SFR_MEM8(0x09A3) -+#define USARTD0_CTRLB _SFR_MEM8(0x09A4) -+#define USARTD0_CTRLC _SFR_MEM8(0x09A5) -+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) -+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) -+ -+/* SPI - Serial Peripheral Interface */ -+#define SPID_CTRL _SFR_MEM8(0x09C0) -+#define SPID_INTCTRL _SFR_MEM8(0x09C1) -+#define SPID_STATUS _SFR_MEM8(0x09C2) -+#define SPID_DATA _SFR_MEM8(0x09C3) -+ -+/* TC0 - 16-bit Timer/Counter 0 */ -+#define TCE0_CTRLA _SFR_MEM8(0x0A00) -+#define TCE0_CTRLB _SFR_MEM8(0x0A01) -+#define TCE0_CTRLC _SFR_MEM8(0x0A02) -+#define TCE0_CTRLD _SFR_MEM8(0x0A03) -+#define TCE0_CTRLE _SFR_MEM8(0x0A04) -+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) -+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) -+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) -+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) -+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) -+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) -+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) -+#define TCE0_TEMP _SFR_MEM8(0x0A0F) -+#define TCE0_CNT _SFR_MEM16(0x0A20) -+#define TCE0_PER _SFR_MEM16(0x0A26) -+#define TCE0_CCA _SFR_MEM16(0x0A28) -+#define TCE0_CCB _SFR_MEM16(0x0A2A) -+#define TCE0_CCC _SFR_MEM16(0x0A2C) -+#define TCE0_CCD _SFR_MEM16(0x0A2E) -+#define TCE0_PERBUF _SFR_MEM16(0x0A36) -+#define TCE0_CCABUF _SFR_MEM16(0x0A38) -+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) -+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) -+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* VPORT - Virtual Ports */ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ -+#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ -+ -+#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ -+#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ -+ -+#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ -+#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ -+ -+/* PR.PRPD bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_SPI Predefined. */ -+/* PR_SPI Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPE bit masks and bit positions */ -+/* PR_TWI Predefined. */ -+/* PR_TWI Predefined. */ -+ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* PR.PRPF bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC0 Predefined. */ -+/* PR_TC0 Predefined. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -+#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -+#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ -+ -+#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ -+ -+#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ -+#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.ANAINIT bit masks and bit positions */ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.AWEXLOCK bit masks and bit positions */ -+#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ -+#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* PORTCFG - Port Configuration */ -+/* PORTCFG.VPCTRLA bit masks and bit positions */ -+#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ -+#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ -+#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ -+#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ -+#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ -+#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ -+#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ -+#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ -+#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ -+#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ -+#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ -+#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ -+#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ -+#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ -+#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ -+#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ -+#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ -+#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ -+#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ -+ -+/* PORTCFG.VPCTRLB bit masks and bit positions */ -+#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ -+#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ -+#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ -+#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ -+#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ -+#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ -+#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ -+#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ -+#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ -+#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ -+ -+#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ -+#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ -+#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ -+#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ -+#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ -+#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ -+#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ -+#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ -+#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ -+#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ -+ -+/* PORTCFG.CLKEVOUT bit masks and bit positions */ -+#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ -+ -+#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ -+#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ -+#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ -+#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ -+#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ -+#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ -+ -+#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ -+#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ -+ -+#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ -+#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ -+ -+/* PORTCFG.EVOUTSEL bit masks and bit positions */ -+#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ -+#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ -+#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ -+#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ -+#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ -+#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ -+#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ -+#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0x7F /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ -+#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ -+ -+#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ -+#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ -+ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ -+#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ -+#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ -+#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ -+#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ -+#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ -+#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ -+#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ -+#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ -+#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ -+ -+#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ -+#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ -+#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ -+#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ -+#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ -+#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ -+#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ -+#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ -+#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ -+#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ -+#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -+#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* RTC - Real-Time Counter */ -+/* RTC.CTRL bit masks and bit positions */ -+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ -+ -+/* RTC.STATUS bit masks and bit positions */ -+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC.INTCTRL bit masks and bit positions */ -+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC.INTFLAGS bit masks and bit positions */ -+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* PORT - I/O Port Configuration */ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ -+#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ -+#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ -+#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ -+#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ -+#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ -+ -+#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ -+#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ -+#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ -+#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ -+#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ -+#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ -+ -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_SPI_bm 0x20 /* SPI bit mask. */ -+#define PORT_SPI_bp 5 /* SPI bit position. */ -+ -+#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ -+#define PORT_USART0_bp 4 /* USART0 bit position. */ -+ -+#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ -+#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ -+ -+#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ -+#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ -+ -+#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ -+#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ -+ -+#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ -+#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ -+#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ -+ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_SRLEN Predefined. */ -+/* PORT_SRLEN Predefined. */ -+ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC0.CTRLA bit masks and bit positions */ -+#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC0.CTRLB bit masks and bit positions */ -+#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ -+#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ -+ -+#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ -+#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ -+ -+#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC0.CTRLC bit masks and bit positions */ -+#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ -+#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ -+ -+#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ -+#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ -+ -+#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC0.CTRLD bit masks and bit positions */ -+#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC0_EVACT_gp 5 /* Event Action group position. */ -+#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC0.CTRLE bit masks and bit positions */ -+#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC0.INTCTRLA bit masks and bit positions */ -+#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC0.INTCTRLB bit masks and bit positions */ -+#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ -+#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ -+#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ -+#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ -+#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ -+#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ -+ -+#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ -+#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ -+#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ -+#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ -+#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ -+#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ -+ -+#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC0.CTRLFCLR bit masks and bit positions */ -+#define TC0_CMD_gm 0x0C /* Command group mask. */ -+#define TC0_CMD_gp 2 /* Command group position. */ -+#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC0_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC0_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC0_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC0_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC0_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC0.CTRLFSET bit masks and bit positions */ -+/* TC0_CMD Predefined. */ -+/* TC0_CMD Predefined. */ -+ -+/* TC0_LUPD Predefined. */ -+/* TC0_LUPD Predefined. */ -+ -+/* TC0_DIR Predefined. */ -+/* TC0_DIR Predefined. */ -+ -+/* TC0.CTRLGCLR bit masks and bit positions */ -+#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ -+#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ -+ -+#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ -+#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ -+ -+#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC0.CTRLGSET bit masks and bit positions */ -+/* TC0_CCDBV Predefined. */ -+/* TC0_CCDBV Predefined. */ -+ -+/* TC0_CCCBV Predefined. */ -+/* TC0_CCCBV Predefined. */ -+ -+/* TC0_CCBBV Predefined. */ -+/* TC0_CCBBV Predefined. */ -+ -+/* TC0_CCABV Predefined. */ -+/* TC0_CCABV Predefined. */ -+ -+/* TC0_PERBV Predefined. */ -+/* TC0_PERBV Predefined. */ -+ -+/* TC0.INTFLAGS bit masks and bit positions */ -+#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ -+#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ -+ -+#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ -+#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ -+ -+#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC1.CTRLA bit masks and bit positions */ -+#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC1.CTRLB bit masks and bit positions */ -+#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ -+#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ -+ -+#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ -+#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ -+ -+#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ -+#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ -+#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ -+#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ -+#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ -+#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ -+#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ -+#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ -+ -+/* TC1.CTRLC bit masks and bit positions */ -+#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ -+#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ -+ -+#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ -+#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ -+ -+/* TC1.CTRLD bit masks and bit positions */ -+#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC1_EVACT_gp 5 /* Event Action group position. */ -+#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC1.CTRLE bit masks and bit positions */ -+#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ -+#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ -+ -+/* TC1.INTCTRLA bit masks and bit positions */ -+#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ -+#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ -+#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ -+#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ -+#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ -+#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ -+ -+#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ -+#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ -+#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ -+#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ -+#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ -+#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ -+ -+/* TC1.INTCTRLB bit masks and bit positions */ -+#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ -+#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ -+#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ -+#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ -+#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ -+#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ -+ -+#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ -+#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ -+#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ -+#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ -+#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ -+#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ -+ -+/* TC1.CTRLFCLR bit masks and bit positions */ -+#define TC1_CMD_gm 0x0C /* Command group mask. */ -+#define TC1_CMD_gp 2 /* Command group position. */ -+#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC1_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC1_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC1_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC1_DIR_bm 0x01 /* Direction bit mask. */ -+#define TC1_DIR_bp 0 /* Direction bit position. */ -+ -+/* TC1.CTRLFSET bit masks and bit positions */ -+/* TC1_CMD Predefined. */ -+/* TC1_CMD Predefined. */ -+ -+/* TC1_LUPD Predefined. */ -+/* TC1_LUPD Predefined. */ -+ -+/* TC1_DIR Predefined. */ -+/* TC1_DIR Predefined. */ -+ -+/* TC1.CTRLGCLR bit masks and bit positions */ -+#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ -+#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ -+ -+#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ -+#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ -+ -+#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+/* TC1.CTRLGSET bit masks and bit positions */ -+/* TC1_CCBBV Predefined. */ -+/* TC1_CCBBV Predefined. */ -+ -+/* TC1_CCABV Predefined. */ -+/* TC1_CCABV Predefined. */ -+ -+/* TC1_PERBV Predefined. */ -+/* TC1_PERBV Predefined. */ -+ -+/* TC1.INTFLAGS bit masks and bit positions */ -+#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ -+#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ -+ -+#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ -+#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ -+ -+#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* TC2 - 16-bit Timer/Counter type 2 */ -+/* TC2.CTRLA bit masks and bit positions */ -+#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* TC2.CTRLB bit masks and bit positions */ -+#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ -+#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ -+ -+#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ -+#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ -+ -+#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ -+#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ -+ -+#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ -+#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ -+ -+#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ -+#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ -+ -+#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ -+#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ -+ -+#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ -+#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ -+ -+#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ -+#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ -+ -+/* TC2.CTRLC bit masks and bit positions */ -+#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ -+#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ -+ -+#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ -+#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ -+ -+#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ -+#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ -+ -+#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ -+#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ -+ -+#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ -+#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ -+ -+#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ -+#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ -+ -+#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ -+#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ -+ -+#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ -+#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ -+ -+/* TC2.CTRLE bit masks and bit positions */ -+#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ -+#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ -+#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ -+#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ -+#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ -+#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ -+ -+/* TC2.INTCTRLA bit masks and bit positions */ -+#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ -+#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ -+#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ -+#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ -+#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ -+#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ -+ -+#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ -+#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ -+#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ -+#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ -+#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ -+#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ -+ -+/* TC2.INTCTRLB bit masks and bit positions */ -+#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ -+#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ -+#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ -+#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ -+#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ -+#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ -+#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ -+#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ -+#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ -+#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ -+#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ -+#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ -+#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ -+#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ -+#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ -+#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ -+ -+#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ -+#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ -+#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ -+#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ -+#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ -+#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ -+ -+/* TC2.CTRLF bit masks and bit positions */ -+#define TC2_CMD_gm 0x0C /* Command group mask. */ -+#define TC2_CMD_gp 2 /* Command group position. */ -+#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC2_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC2_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ -+#define TC2_CMDEN_gp 0 /* Command Enable group position. */ -+#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ -+#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ -+#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ -+#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ -+ -+/* TC2.INTFLAGS bit masks and bit positions */ -+#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ -+#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ -+ -+#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ -+#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ -+ -+#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ -+#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ -+ -+#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ -+#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ -+ -+#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ -+ -+#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ -+#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ -+ -+/* AWEX - Timer/Counter Advanced Waveform Extension */ -+/* AWEX.CTRL bit masks and bit positions */ -+#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ -+#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ -+ -+#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ -+#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ -+ -+#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ -+#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ -+ -+#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ -+#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ -+ -+#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ -+#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ -+ -+#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ -+#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ -+ -+/* AWEX.FDCTRL bit masks and bit positions */ -+#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ -+#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ -+ -+#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ -+#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ -+ -+#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ -+#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ -+#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ -+#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ -+#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ -+#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ -+ -+/* AWEX.STATUS bit masks and bit positions */ -+#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ -+#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ -+ -+#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ -+#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ -+ -+#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ -+#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ -+ -+/* AWEX.STATUSSET bit masks and bit positions */ -+/* AWEX_FDF Predefined. */ -+/* AWEX_FDF Predefined. */ -+ -+/* AWEX_DTHSBUFV Predefined. */ -+/* AWEX_DTHSBUFV Predefined. */ -+ -+/* AWEX_DTLSBUFV Predefined. */ -+/* AWEX_DTLSBUFV Predefined. */ -+ -+/* HIRES - Timer/Counter High-Resolution Extension */ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ -+#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* LOCKBIT - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT0_vect_num 2 -+#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ -+#define PORTC_INT1_vect_num 3 -+#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT0_vect_num 4 -+#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ -+#define PORTR_INT1_vect_num 5 -+#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ -+ -+/* RTC interrupt vectors */ -+#define RTC_OVF_vect_num 10 -+#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ -+#define RTC_COMP_vect_num 11 -+#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 12 -+#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 13 -+#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_OVF_vect_num 14 -+#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LUNF_vect_num 14 -+#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_ERR_vect_num 15 -+#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_HUNF_vect_num 15 -+#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCA_vect_num 16 -+#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPA_vect_num 16 -+#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCB_vect_num 17 -+#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPB_vect_num 17 -+#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCC_vect_num 18 -+#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPC_vect_num 18 -+#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ -+ -+/* TCC0 interrupt vectors */ -+#define TCC0_CCD_vect_num 19 -+#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ -+ -+/* TCC2 interrupt vectors */ -+#define TCC2_LCMPD_vect_num 19 -+#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ -+ -+/* TCC1 interrupt vectors */ -+#define TCC1_OVF_vect_num 20 -+#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ -+#define TCC1_ERR_vect_num 21 -+#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ -+#define TCC1_CCA_vect_num 22 -+#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ -+#define TCC1_CCB_vect_num 23 -+#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 24 -+#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 25 -+#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 26 -+#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 27 -+#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 32 -+#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ -+#define NVM_SPM_vect_num 33 -+#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ -+ -+/* PORTB interrupt vectors */ -+#define PORTB_INT0_vect_num 34 -+#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ -+#define PORTB_INT1_vect_num 35 -+#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ -+ -+/* PORTE interrupt vectors */ -+#define PORTE_INT0_vect_num 43 -+#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ -+#define PORTE_INT1_vect_num 44 -+#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ -+ -+/* TWIE interrupt vectors */ -+#define TWIE_TWIS_vect_num 45 -+#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ -+#define TWIE_TWIM_vect_num 46 -+#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ -+ -+/* TCE0 interrupt vectors */ -+#define TCE0_OVF_vect_num 47 -+#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ -+#define TCE0_ERR_vect_num 48 -+#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ -+#define TCE0_CCA_vect_num 49 -+#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ -+#define TCE0_CCB_vect_num 50 -+#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ -+#define TCE0_CCC_vect_num 51 -+#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ -+#define TCE0_CCD_vect_num 52 -+#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ -+ -+/* USARTE0 interrupt vectors */ -+#define USARTE0_RXC_vect_num 58 -+#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ -+#define USARTE0_DRE_vect_num 59 -+#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ -+#define USARTE0_TXC_vect_num 60 -+#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT0_vect_num 64 -+#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ -+#define PORTD_INT1_vect_num 65 -+#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ -+ -+/* PORTA interrupt vectors */ -+#define PORTA_INT0_vect_num 66 -+#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ -+#define PORTA_INT1_vect_num 67 -+#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ -+ -+/* ACA interrupt vectors */ -+#define ACA_AC0_vect_num 68 -+#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ -+#define ACA_AC1_vect_num 69 -+#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ -+#define ACA_ACW_vect_num 70 -+#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ -+ -+/* ADCA interrupt vectors */ -+#define ADCA_CH0_vect_num 71 -+#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_OVF_vect_num 77 -+#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LUNF_vect_num 77 -+#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_ERR_vect_num 78 -+#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_HUNF_vect_num 78 -+#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCA_vect_num 79 -+#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPA_vect_num 79 -+#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCB_vect_num 80 -+#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPB_vect_num 80 -+#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCC_vect_num 81 -+#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPC_vect_num 81 -+#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ -+ -+/* TCD0 interrupt vectors */ -+#define TCD0_CCD_vect_num 82 -+#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ -+ -+/* TCD2 interrupt vectors */ -+#define TCD2_LCMPD_vect_num 82 -+#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ -+ -+/* SPID interrupt vectors */ -+#define SPID_INT_vect_num 87 -+#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ -+ -+/* USARTD0 interrupt vectors */ -+#define USARTD0_RXC_vect_num 88 -+#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ -+#define USARTD0_DRE_vect_num 89 -+#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ -+#define USARTD0_TXC_vect_num 90 -+#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (91 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (69632) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (65536) -+#define APP_SECTION_PAGE_SIZE (256) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0xF000) -+#define APPTABLE_SECTION_SIZE (4096) -+#define APPTABLE_SECTION_PAGE_SIZE (256) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x10000) -+#define BOOT_SECTION_SIZE (4096) -+#define BOOT_SECTION_PAGE_SIZE (256) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (12288) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (2048) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (4096) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (2048) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (6) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (256) -+#define USER_SIGNATURES_PAGE_SIZE (256) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (64) -+#define PROD_SIGNATURES_PAGE_SIZE (256) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 256 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 6 -+ -+/* Fuse Byte 0 Reserved */ -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x96 -+#define SIGNATURE_2 0x47 -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA64D4_H_INCLUDED */ -+ +@@ -0,0 +1,5511 @@ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox64d4.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA64D4_H_INCLUDED ++#define _AVR_ATXMEGA64D4_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t reserved_0x04; ++} CLK_t; ++ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t reserved_0x02; ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t PRPE; /* Power Reduction Port E */ ++ register8_t PRPF; /* Power Reduction Port F */ ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from 32.768 kHz internal oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from 32.768 kHz internal oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 2 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC2MCREF_enum ++{ ++ OSC_RC2MCREF_RC32K_gc = (0x00<<0), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC2MCREF_XOSC32K_gc = (0x01<<0), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC2MCREF_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t AWEXLOCK; /* AWEX Lock */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t VPCTRLA; /* Virtual Port Control Register A */ ++ register8_t VPCTRLB; /* Virtual Port Control Register B */ ++ register8_t CLKEVOUT; /* Clock and Event Out Register */ ++ register8_t reserved_0x05; ++ register8_t EVOUTSEL; /* Event Output Select */ ++} PORTCFG_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP02MAP_enum ++{ ++ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */ ++ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */ ++ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */ ++ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */ ++ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */ ++ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */ ++ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */ ++ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */ ++ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */ ++ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */ ++ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */ ++ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */ ++ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */ ++ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */ ++ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */ ++ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */ ++} PORTCFG_VP02MAP_t; ++ ++/* Virtual Port Mapping */ ++typedef enum PORTCFG_VP13MAP_enum ++{ ++ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */ ++ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */ ++ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */ ++ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */ ++ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */ ++ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */ ++ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */ ++ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */ ++ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */ ++ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */ ++ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */ ++ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */ ++ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */ ++ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */ ++ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */ ++ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */ ++} PORTCFG_VP13MAP_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin 7 */ ++} PORTCFG_EVOUT_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++} EVSYS_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */ ++ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */ ++ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */ ++ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */ ++ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */ ++ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */ ++ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */ ++ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */ ++ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */ ++ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */ ++ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */ ++ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */ ++ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */ ++ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */ ++ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */ ++ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */ ++ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */ ++ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */ ++ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */ ++ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */ ++ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */ ++ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */ ++ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */ ++ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */ ++ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or Capture A */ ++ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or Capture B */ ++ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or Capture C */ ++ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or Capture D */ ++ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */ ++ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */ ++ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or Capture A */ ++ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */ ++ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */ ++ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or Capture A */ ++ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or Capture B */ ++ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or Capture C */ ++ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or Capture D */ ++ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */ ++ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */ ++ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or Capture A */ ++ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or Capture B */ ++ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or Capture C */ ++ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or Capture D */ ++ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */ ++ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */ ++ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or Capture A */ ++ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or Capture B */ ++ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or Capture C */ ++ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or Capture D */ ++} EVSYS_CHMUX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t reserved_0x07; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++} ADC_t; ++ ++/* Current Limitation */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ ++} ADC_CURRLIMIT_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with gain */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ ++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ ++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ ++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Counter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++} TWI_t; ++ ++/* SDA Hold Time */ ++typedef enum TWI_SDAHOLD_enum ++{ ++ TWI_SDAHOLD_OFF_gc = (0x00<<1), /* SDA Hold Time off */ ++ TWI_SDAHOLD_50NS_gc = (0x01<<1), /* SDA Hold Time 50 ns */ ++ TWI_SDAHOLD_300NS_gc = (0x02<<1), /* SDA Hold Time 300 ns */ ++ TWI_SDAHOLD_400NS_gc = (0x03<<1), /* SDA Hold Time 400 ns */ ++} TWI_SDAHOLD_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - I/O Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INT0MASK; /* Port Interrupt 0 Mask */ ++ register8_t INT1MASK; /* Port Interrupt 1 Mask */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* I/O Port Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt 0 Level */ ++typedef enum PORT_INT0LVL_enum ++{ ++ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INT0LVL_t; ++ ++/* Port Interrupt 1 Level */ ++typedef enum PORT_INT1LVL_enum ++{ ++ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */ ++ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */ ++ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */ ++} PORT_INT1LVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 0 */ ++typedef struct TC0_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC0_t; ++ ++ ++/* 16-bit Timer/Counter 1 */ ++typedef struct TC1_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLFCLR; /* Control Register F Clear */ ++ register8_t CTRLFSET; /* Control Register F Set */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++} TC1_t; ++ ++/* Clock Selection */ ++typedef enum TC_CLKSEL_enum ++{ ++ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_CLKSEL_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC_WGMODE_enum ++{ ++ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */ ++ TC_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on both TOP and BOTTOM */ ++ TC_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC_WGMODE_t; ++ ++/* Byte Mode */ ++typedef enum TC_BYTEM_enum ++{ ++ TC_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only */ ++ TC_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters (TC2) */ ++} TC_BYTEM_t; ++ ++/* Event Action */ ++typedef enum TC_EVACT_enum ++{ ++ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */ ++ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */ ++ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */ ++ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */ ++ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */ ++ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC_EVSEL_enum ++{ ++ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC_EVSEL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC_ERRINTLVL_enum ++{ ++ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC_OVFINTLVL_enum ++{ ++ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_OVFINTLVL_t; ++ ++/* Compare or Capture D Interrupt Level */ ++typedef enum TC_CCDINTLVL_enum ++{ ++ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC_CCDINTLVL_t; ++ ++/* Compare or Capture C Interrupt Level */ ++typedef enum TC_CCCINTLVL_enum ++{ ++ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC_CCCINTLVL_t; ++ ++/* Compare or Capture B Interrupt Level */ ++typedef enum TC_CCBINTLVL_enum ++{ ++ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC_CCBINTLVL_t; ++ ++/* Compare or Capture A Interrupt Level */ ++typedef enum TC_CCAINTLVL_enum ++{ ++ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC_CCAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC_CMD_enum ++{ ++ TC_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC2 - 16-bit Timer/Counter type 2 ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter type 2 */ ++typedef struct TC2_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t reserved_0x03; ++ register8_t CTRLE; /* Control Register E */ ++ register8_t reserved_0x05; ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t reserved_0x08; ++ register8_t CTRLF; /* Control Register F */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t LCNT; /* Low Byte Count */ ++ register8_t HCNT; /* High Byte Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t LPER; /* Low Byte Period */ ++ register8_t HPER; /* High Byte Period */ ++ register8_t LCMPA; /* Low Byte Compare A */ ++ register8_t HCMPA; /* High Byte Compare A */ ++ register8_t LCMPB; /* Low Byte Compare B */ ++ register8_t HCMPB; /* High Byte Compare B */ ++ register8_t LCMPC; /* Low Byte Compare C */ ++ register8_t HCMPC; /* High Byte Compare C */ ++ register8_t LCMPD; /* Low Byte Compare D */ ++ register8_t HCMPD; /* High Byte Compare D */ ++} TC2_t; ++ ++/* Clock Selection */ ++typedef enum TC2_CLKSEL_enum ++{ ++ TC2_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC2_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC2_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC2_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC2_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC2_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC2_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC2_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC2_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC2_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC2_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC2_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++} TC2_CLKSEL_t; ++ ++/* Byte Mode */ ++typedef enum TC2_BYTEM_enum ++{ ++ TC2_BYTEM_NORMAL_gc = (0x00<<0), /* 16-bit mode */ ++ TC2_BYTEM_BYTEMODE_gc = (0x01<<0), /* Timer/Counter operating in byte mode only (TC2) */ ++ TC2_BYTEM_SPLITMODE_gc = (0x02<<0), /* Timer/Counter split into two 8-bit Counters */ ++} TC2_BYTEM_t; ++ ++/* High Byte Underflow Interrupt Level */ ++typedef enum TC2_HUNFINTLVL_enum ++{ ++ TC2_HUNFINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_HUNFINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_HUNFINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_HUNFINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_HUNFINTLVL_t; ++ ++/* Low Byte Underflow Interrupt Level */ ++typedef enum TC2_LUNFINTLVL_enum ++{ ++ TC2_LUNFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LUNFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LUNFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LUNFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LUNFINTLVL_t; ++ ++/* Low Byte Compare D Interrupt Level */ ++typedef enum TC2_LCMPDINTLVL_enum ++{ ++ TC2_LCMPDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC2_LCMPDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC2_LCMPDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC2_LCMPDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC2_LCMPDINTLVL_t; ++ ++/* Low Byte Compare C Interrupt Level */ ++typedef enum TC2_LCMPCINTLVL_enum ++{ ++ TC2_LCMPCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC2_LCMPCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC2_LCMPCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC2_LCMPCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC2_LCMPCINTLVL_t; ++ ++/* Low Byte Compare B Interrupt Level */ ++typedef enum TC2_LCMPBINTLVL_enum ++{ ++ TC2_LCMPBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC2_LCMPBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC2_LCMPBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC2_LCMPBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC2_LCMPBINTLVL_t; ++ ++/* Low Byte Compare A Interrupt Level */ ++typedef enum TC2_LCMPAINTLVL_enum ++{ ++ TC2_LCMPAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC2_LCMPAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC2_LCMPAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC2_LCMPAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC2_LCMPAINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMD_enum ++{ ++ TC2_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC2_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC2_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC2_CMD_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC2_CMDEN_enum ++{ ++ TC2_CMDEN_LOW_gc = (0x01<<0), /* Low Byte Timer/Counter */ ++ TC2_CMDEN_HIGH_gc = (0x02<<0), /* High Byte Timer/Counter */ ++ TC2_CMDEN_BOTH_gc = (0x03<<0), /* Both Low Byte and High Byte Timer/Counters */ ++} TC2_CMDEN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AWEX - Timer/Counter Advanced Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Advanced Waveform Extension */ ++typedef struct AWEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t FDEMASK; /* Fault Detection Event Mask */ ++ register8_t FDCTRL; /* Fault Detection Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t DTBOTH; /* Dead Time Both Sides */ ++ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */ ++ register8_t DTLS; /* Dead Time Low Side */ ++ register8_t DTHS; /* Dead Time High Side */ ++ register8_t DTLSBUF; /* Dead Time Low Side Buffer */ ++ register8_t DTHSBUF; /* Dead Time High Side Buffer */ ++ register8_t OUTOVEN; /* Output Override Enable */ ++} AWEX_t; ++ ++/* Fault Detect Action */ ++typedef enum AWEX_FDACT_enum ++{ ++ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */ ++ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */ ++} AWEX_FDACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - Timer/Counter High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register */ ++} HIRES_t; ++ ++/* High Resolution Enable */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */ ++ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter 0 */ ++ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter 1 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both Timer/Counters */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t reserved_0x00; ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++} NVM_FUSES_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* Timer Oscillator pin location */ ++typedef enum TOSCSEL_enum ++{ ++ TOSCSEL_ALTERNATE_gc = (0x00<<5), /* TOSC1 / TOSC2 on separate pins */ ++ TOSCSEL_XTAL_gc = (0x01<<5), /* TOSC1 / TOSC2 shared with XTAL1 / XTAL2 */ ++} TOSCSEL_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<0), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<0), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<0), /* BOD Disabled */ ++} BOD_t; ++ ++/* BOD operation */ ++typedef enum BODACT_enum ++{ ++ BODACT_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BODACT_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BODACT_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BODACT_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WDP_enum ++{ ++ WDP_8CLK_gc = (0x00<<0), /* 8 cycles (8ms @ 3.3V) */ ++ WDP_16CLK_gc = (0x01<<0), /* 16 cycles (16ms @ 3.3V) */ ++ WDP_32CLK_gc = (0x02<<0), /* 32 cycles (32ms @ 3.3V) */ ++ WDP_64CLK_gc = (0x03<<0), /* 64 cycles (64ms @ 3.3V) */ ++ WDP_128CLK_gc = (0x04<<0), /* 128 cycles (0.125s @ 3.3V) */ ++ WDP_256CLK_gc = (0x05<<0), /* 256 cycles (0.25s @ 3.3V) */ ++ WDP_512CLK_gc = (0x06<<0), /* 512 cycles (0.5s @ 3.3V) */ ++ WDP_1KCLK_gc = (0x07<<0), /* 1K cycles (1s @ 3.3V) */ ++ WDP_2KCLK_gc = (0x08<<0), /* 2K cycles (2s @ 3.3V) */ ++ WDP_4KCLK_gc = (0x09<<0), /* 4K cycles (4s @ 3.3V) */ ++ WDP_8KCLK_gc = (0x0A<<0), /* 8K cycles (8s @ 3.3V) */ ++} WDP_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++LOCKBIT - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC2M; /* RCOSC 2 MHz Calibration Value B */ ++ register8_t RCOSC2MA; /* RCOSC 2 MHz Calibration Value A */ ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t reserved_0x28; ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTB (*(PORT_t *) 0x0620) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTE (*(PORT_t *) 0x0680) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC0 (*(TC0_t *) 0x0800) /* 16-bit Timer/Counter 0 */ ++#define TCC2 (*(TC2_t *) 0x0800) /* 16-bit Timer/Counter type 2 */ ++#define TCC1 (*(TC1_t *) 0x0840) /* 16-bit Timer/Counter 1 */ ++#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD0 (*(TC0_t *) 0x0900) /* 16-bit Timer/Counter 0 */ ++#define TCD2 (*(TC2_t *) 0x0900) /* 16-bit Timer/Counter type 2 */ ++#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface */ ++#define TCE0 (*(TC0_t *) 0x0A00) /* 16-bit Timer/Counter 0 */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC2M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC2MA _SFR_MEM8(0x0001) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* DFLL - DFLL */ ++#define DFLLRC2M_CTRL _SFR_MEM8(0x0068) ++#define DFLLRC2M_CALA _SFR_MEM8(0x006A) ++#define DFLLRC2M_CALB _SFR_MEM8(0x006B) ++#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C) ++#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D) ++#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++#define PR_PRPE _SFR_MEM8(0x0075) ++#define PR_PRPF _SFR_MEM8(0x0076) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_AWEXLOCK _SFR_MEM8(0x0099) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2) ++#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3) ++#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_EVOUTSEL _SFR_MEM8(0x00B6) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIE_CTRL _SFR_MEM8(0x04A0) ++#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1) ++#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2) ++#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3) ++#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4) ++#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5) ++#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6) ++#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7) ++#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8) ++#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9) ++#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA) ++#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB) ++#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC) ++#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INT0MASK _SFR_MEM8(0x060A) ++#define PORTA_INT1MASK _SFR_MEM8(0x060B) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_REMAP _SFR_MEM8(0x060E) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTB_DIR _SFR_MEM8(0x0620) ++#define PORTB_DIRSET _SFR_MEM8(0x0621) ++#define PORTB_DIRCLR _SFR_MEM8(0x0622) ++#define PORTB_DIRTGL _SFR_MEM8(0x0623) ++#define PORTB_OUT _SFR_MEM8(0x0624) ++#define PORTB_OUTSET _SFR_MEM8(0x0625) ++#define PORTB_OUTCLR _SFR_MEM8(0x0626) ++#define PORTB_OUTTGL _SFR_MEM8(0x0627) ++#define PORTB_IN _SFR_MEM8(0x0628) ++#define PORTB_INTCTRL _SFR_MEM8(0x0629) ++#define PORTB_INT0MASK _SFR_MEM8(0x062A) ++#define PORTB_INT1MASK _SFR_MEM8(0x062B) ++#define PORTB_INTFLAGS _SFR_MEM8(0x062C) ++#define PORTB_REMAP _SFR_MEM8(0x062E) ++#define PORTB_PIN0CTRL _SFR_MEM8(0x0630) ++#define PORTB_PIN1CTRL _SFR_MEM8(0x0631) ++#define PORTB_PIN2CTRL _SFR_MEM8(0x0632) ++#define PORTB_PIN3CTRL _SFR_MEM8(0x0633) ++#define PORTB_PIN4CTRL _SFR_MEM8(0x0634) ++#define PORTB_PIN5CTRL _SFR_MEM8(0x0635) ++#define PORTB_PIN6CTRL _SFR_MEM8(0x0636) ++#define PORTB_PIN7CTRL _SFR_MEM8(0x0637) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INT0MASK _SFR_MEM8(0x064A) ++#define PORTC_INT1MASK _SFR_MEM8(0x064B) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INT0MASK _SFR_MEM8(0x066A) ++#define PORTD_INT1MASK _SFR_MEM8(0x066B) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTE_DIR _SFR_MEM8(0x0680) ++#define PORTE_DIRSET _SFR_MEM8(0x0681) ++#define PORTE_DIRCLR _SFR_MEM8(0x0682) ++#define PORTE_DIRTGL _SFR_MEM8(0x0683) ++#define PORTE_OUT _SFR_MEM8(0x0684) ++#define PORTE_OUTSET _SFR_MEM8(0x0685) ++#define PORTE_OUTCLR _SFR_MEM8(0x0686) ++#define PORTE_OUTTGL _SFR_MEM8(0x0687) ++#define PORTE_IN _SFR_MEM8(0x0688) ++#define PORTE_INTCTRL _SFR_MEM8(0x0689) ++#define PORTE_INT0MASK _SFR_MEM8(0x068A) ++#define PORTE_INT1MASK _SFR_MEM8(0x068B) ++#define PORTE_INTFLAGS _SFR_MEM8(0x068C) ++#define PORTE_REMAP _SFR_MEM8(0x068E) ++#define PORTE_PIN0CTRL _SFR_MEM8(0x0690) ++#define PORTE_PIN1CTRL _SFR_MEM8(0x0691) ++#define PORTE_PIN2CTRL _SFR_MEM8(0x0692) ++#define PORTE_PIN3CTRL _SFR_MEM8(0x0693) ++#define PORTE_PIN4CTRL _SFR_MEM8(0x0694) ++#define PORTE_PIN5CTRL _SFR_MEM8(0x0695) ++#define PORTE_PIN6CTRL _SFR_MEM8(0x0696) ++#define PORTE_PIN7CTRL _SFR_MEM8(0x0697) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INT0MASK _SFR_MEM8(0x07EA) ++#define PORTR_INT1MASK _SFR_MEM8(0x07EB) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCC0_CTRLA _SFR_MEM8(0x0800) ++#define TCC0_CTRLB _SFR_MEM8(0x0801) ++#define TCC0_CTRLC _SFR_MEM8(0x0802) ++#define TCC0_CTRLD _SFR_MEM8(0x0803) ++#define TCC0_CTRLE _SFR_MEM8(0x0804) ++#define TCC0_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC0_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC0_CTRLFCLR _SFR_MEM8(0x0808) ++#define TCC0_CTRLFSET _SFR_MEM8(0x0809) ++#define TCC0_CTRLGCLR _SFR_MEM8(0x080A) ++#define TCC0_CTRLGSET _SFR_MEM8(0x080B) ++#define TCC0_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC0_TEMP _SFR_MEM8(0x080F) ++#define TCC0_CNT _SFR_MEM16(0x0820) ++#define TCC0_PER _SFR_MEM16(0x0826) ++#define TCC0_CCA _SFR_MEM16(0x0828) ++#define TCC0_CCB _SFR_MEM16(0x082A) ++#define TCC0_CCC _SFR_MEM16(0x082C) ++#define TCC0_CCD _SFR_MEM16(0x082E) ++#define TCC0_PERBUF _SFR_MEM16(0x0836) ++#define TCC0_CCABUF _SFR_MEM16(0x0838) ++#define TCC0_CCBBUF _SFR_MEM16(0x083A) ++#define TCC0_CCCBUF _SFR_MEM16(0x083C) ++#define TCC0_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCC2_CTRLA _SFR_MEM8(0x0800) ++#define TCC2_CTRLB _SFR_MEM8(0x0801) ++#define TCC2_CTRLC _SFR_MEM8(0x0802) ++#define TCC2_CTRLE _SFR_MEM8(0x0804) ++#define TCC2_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC2_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC2_CTRLF _SFR_MEM8(0x0809) ++#define TCC2_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC2_LCNT _SFR_MEM8(0x0820) ++#define TCC2_HCNT _SFR_MEM8(0x0821) ++#define TCC2_LPER _SFR_MEM8(0x0826) ++#define TCC2_HPER _SFR_MEM8(0x0827) ++#define TCC2_LCMPA _SFR_MEM8(0x0828) ++#define TCC2_HCMPA _SFR_MEM8(0x0829) ++#define TCC2_LCMPB _SFR_MEM8(0x082A) ++#define TCC2_HCMPB _SFR_MEM8(0x082B) ++#define TCC2_LCMPC _SFR_MEM8(0x082C) ++#define TCC2_HCMPC _SFR_MEM8(0x082D) ++#define TCC2_LCMPD _SFR_MEM8(0x082E) ++#define TCC2_HCMPD _SFR_MEM8(0x082F) ++ ++/* TC1 - 16-bit Timer/Counter 1 */ ++#define TCC1_CTRLA _SFR_MEM8(0x0840) ++#define TCC1_CTRLB _SFR_MEM8(0x0841) ++#define TCC1_CTRLC _SFR_MEM8(0x0842) ++#define TCC1_CTRLD _SFR_MEM8(0x0843) ++#define TCC1_CTRLE _SFR_MEM8(0x0844) ++#define TCC1_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC1_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC1_CTRLFCLR _SFR_MEM8(0x0848) ++#define TCC1_CTRLFSET _SFR_MEM8(0x0849) ++#define TCC1_CTRLGCLR _SFR_MEM8(0x084A) ++#define TCC1_CTRLGSET _SFR_MEM8(0x084B) ++#define TCC1_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC1_TEMP _SFR_MEM8(0x084F) ++#define TCC1_CNT _SFR_MEM16(0x0860) ++#define TCC1_PER _SFR_MEM16(0x0866) ++#define TCC1_CCA _SFR_MEM16(0x0868) ++#define TCC1_CCB _SFR_MEM16(0x086A) ++#define TCC1_PERBUF _SFR_MEM16(0x0876) ++#define TCC1_CCABUF _SFR_MEM16(0x0878) ++#define TCC1_CCBBUF _SFR_MEM16(0x087A) ++ ++/* AWEX - Advanced Waveform Extension */ ++#define AWEXC_CTRL _SFR_MEM8(0x0880) ++#define AWEXC_FDEMASK _SFR_MEM8(0x0882) ++#define AWEXC_FDCTRL _SFR_MEM8(0x0883) ++#define AWEXC_STATUS _SFR_MEM8(0x0884) ++#define AWEXC_STATUSSET _SFR_MEM8(0x0885) ++#define AWEXC_DTBOTH _SFR_MEM8(0x0886) ++#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887) ++#define AWEXC_DTLS _SFR_MEM8(0x0888) ++#define AWEXC_DTHS _SFR_MEM8(0x0889) ++#define AWEXC_DTLSBUF _SFR_MEM8(0x088A) ++#define AWEXC_DTHSBUF _SFR_MEM8(0x088B) ++#define AWEXC_OUTOVEN _SFR_MEM8(0x088C) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x0890) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08A0) ++#define USARTC0_STATUS _SFR_MEM8(0x08A1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08A3) ++#define USARTC0_CTRLB _SFR_MEM8(0x08A4) ++#define USARTC0_CTRLC _SFR_MEM8(0x08A5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPIC_CTRL _SFR_MEM8(0x08C0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08C1) ++#define SPIC_STATUS _SFR_MEM8(0x08C2) ++#define SPIC_DATA _SFR_MEM8(0x08C3) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCD0_CTRLA _SFR_MEM8(0x0900) ++#define TCD0_CTRLB _SFR_MEM8(0x0901) ++#define TCD0_CTRLC _SFR_MEM8(0x0902) ++#define TCD0_CTRLD _SFR_MEM8(0x0903) ++#define TCD0_CTRLE _SFR_MEM8(0x0904) ++#define TCD0_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD0_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD0_CTRLFCLR _SFR_MEM8(0x0908) ++#define TCD0_CTRLFSET _SFR_MEM8(0x0909) ++#define TCD0_CTRLGCLR _SFR_MEM8(0x090A) ++#define TCD0_CTRLGSET _SFR_MEM8(0x090B) ++#define TCD0_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD0_TEMP _SFR_MEM8(0x090F) ++#define TCD0_CNT _SFR_MEM16(0x0920) ++#define TCD0_PER _SFR_MEM16(0x0926) ++#define TCD0_CCA _SFR_MEM16(0x0928) ++#define TCD0_CCB _SFR_MEM16(0x092A) ++#define TCD0_CCC _SFR_MEM16(0x092C) ++#define TCD0_CCD _SFR_MEM16(0x092E) ++#define TCD0_PERBUF _SFR_MEM16(0x0936) ++#define TCD0_CCABUF _SFR_MEM16(0x0938) ++#define TCD0_CCBBUF _SFR_MEM16(0x093A) ++#define TCD0_CCCBUF _SFR_MEM16(0x093C) ++#define TCD0_CCDBUF _SFR_MEM16(0x093E) ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++#define TCD2_CTRLA _SFR_MEM8(0x0900) ++#define TCD2_CTRLB _SFR_MEM8(0x0901) ++#define TCD2_CTRLC _SFR_MEM8(0x0902) ++#define TCD2_CTRLE _SFR_MEM8(0x0904) ++#define TCD2_INTCTRLA _SFR_MEM8(0x0906) ++#define TCD2_INTCTRLB _SFR_MEM8(0x0907) ++#define TCD2_CTRLF _SFR_MEM8(0x0909) ++#define TCD2_INTFLAGS _SFR_MEM8(0x090C) ++#define TCD2_LCNT _SFR_MEM8(0x0920) ++#define TCD2_HCNT _SFR_MEM8(0x0921) ++#define TCD2_LPER _SFR_MEM8(0x0926) ++#define TCD2_HPER _SFR_MEM8(0x0927) ++#define TCD2_LCMPA _SFR_MEM8(0x0928) ++#define TCD2_HCMPA _SFR_MEM8(0x0929) ++#define TCD2_LCMPB _SFR_MEM8(0x092A) ++#define TCD2_HCMPB _SFR_MEM8(0x092B) ++#define TCD2_LCMPC _SFR_MEM8(0x092C) ++#define TCD2_HCMPC _SFR_MEM8(0x092D) ++#define TCD2_LCMPD _SFR_MEM8(0x092E) ++#define TCD2_HCMPD _SFR_MEM8(0x092F) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD0_DATA _SFR_MEM8(0x09A0) ++#define USARTD0_STATUS _SFR_MEM8(0x09A1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09A3) ++#define USARTD0_CTRLB _SFR_MEM8(0x09A4) ++#define USARTD0_CTRLC _SFR_MEM8(0x09A5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7) ++ ++/* SPI - Serial Peripheral Interface */ ++#define SPID_CTRL _SFR_MEM8(0x09C0) ++#define SPID_INTCTRL _SFR_MEM8(0x09C1) ++#define SPID_STATUS _SFR_MEM8(0x09C2) ++#define SPID_DATA _SFR_MEM8(0x09C3) ++ ++/* TC0 - 16-bit Timer/Counter 0 */ ++#define TCE0_CTRLA _SFR_MEM8(0x0A00) ++#define TCE0_CTRLB _SFR_MEM8(0x0A01) ++#define TCE0_CTRLC _SFR_MEM8(0x0A02) ++#define TCE0_CTRLD _SFR_MEM8(0x0A03) ++#define TCE0_CTRLE _SFR_MEM8(0x0A04) ++#define TCE0_INTCTRLA _SFR_MEM8(0x0A06) ++#define TCE0_INTCTRLB _SFR_MEM8(0x0A07) ++#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08) ++#define TCE0_CTRLFSET _SFR_MEM8(0x0A09) ++#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A) ++#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B) ++#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C) ++#define TCE0_TEMP _SFR_MEM8(0x0A0F) ++#define TCE0_CNT _SFR_MEM16(0x0A20) ++#define TCE0_PER _SFR_MEM16(0x0A26) ++#define TCE0_CCA _SFR_MEM16(0x0A28) ++#define TCE0_CCB _SFR_MEM16(0x0A2A) ++#define TCE0_CCC _SFR_MEM16(0x0A2C) ++#define TCE0_CCD _SFR_MEM16(0x0A2E) ++#define TCE0_PERBUF _SFR_MEM16(0x0A36) ++#define TCE0_CCABUF _SFR_MEM16(0x0A38) ++#define TCE0_CCBBUF _SFR_MEM16(0x0A3A) ++#define TCE0_CCCBUF _SFR_MEM16(0x0A3C) ++#define TCE0_CCDBUF _SFR_MEM16(0x0A3E) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C HIRES bit mask. */ ++#define PR_HIRES_bp 2 /* Port C HIRES bit position. */ ++ ++#define PR_TC1_bm 0x02 /* Port C Timer/Counter1 bit mask. */ ++#define PR_TC1_bp 1 /* Port C Timer/Counter1 bit position. */ ++ ++#define PR_TC0_bm 0x01 /* Port C Timer/Counter0 bit mask. */ ++#define PR_TC0_bp 0 /* Port C Timer/Counter0 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_SPI Predefined. */ ++/* PR_SPI Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPE bit masks and bit positions */ ++/* PR_TWI Predefined. */ ++/* PR_TWI Predefined. */ ++ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* PR.PRPF bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC0 Predefined. */ ++/* PR_TC0 Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x0F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++#define OSC_RC2MCREF_bm 0x01 /* 2 MHz DFLL Calibration Reference bit mask. */ ++#define OSC_RC2MCREF_bp 0 /* 2 MHz DFLL Calibration Reference bit position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.AWEXLOCK bit masks and bit positions */ ++#define MCU_AWEXCLOCK_bm 0x01 /* AWeX on T/C C0 Lock bit mask. */ ++#define MCU_AWEXCLOCK_bp 0 /* AWeX on T/C C0 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.VPCTRLA bit masks and bit positions */ ++#define PORTCFG_VP1MAP_gm 0xF0 /* Virtual Port 1 Mapping group mask. */ ++#define PORTCFG_VP1MAP_gp 4 /* Virtual Port 1 Mapping group position. */ ++#define PORTCFG_VP1MAP0_bm (1<<4) /* Virtual Port 1 Mapping bit 0 mask. */ ++#define PORTCFG_VP1MAP0_bp 4 /* Virtual Port 1 Mapping bit 0 position. */ ++#define PORTCFG_VP1MAP1_bm (1<<5) /* Virtual Port 1 Mapping bit 1 mask. */ ++#define PORTCFG_VP1MAP1_bp 5 /* Virtual Port 1 Mapping bit 1 position. */ ++#define PORTCFG_VP1MAP2_bm (1<<6) /* Virtual Port 1 Mapping bit 2 mask. */ ++#define PORTCFG_VP1MAP2_bp 6 /* Virtual Port 1 Mapping bit 2 position. */ ++#define PORTCFG_VP1MAP3_bm (1<<7) /* Virtual Port 1 Mapping bit 3 mask. */ ++#define PORTCFG_VP1MAP3_bp 7 /* Virtual Port 1 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP0MAP_gm 0x0F /* Virtual Port 0 Mapping group mask. */ ++#define PORTCFG_VP0MAP_gp 0 /* Virtual Port 0 Mapping group position. */ ++#define PORTCFG_VP0MAP0_bm (1<<0) /* Virtual Port 0 Mapping bit 0 mask. */ ++#define PORTCFG_VP0MAP0_bp 0 /* Virtual Port 0 Mapping bit 0 position. */ ++#define PORTCFG_VP0MAP1_bm (1<<1) /* Virtual Port 0 Mapping bit 1 mask. */ ++#define PORTCFG_VP0MAP1_bp 1 /* Virtual Port 0 Mapping bit 1 position. */ ++#define PORTCFG_VP0MAP2_bm (1<<2) /* Virtual Port 0 Mapping bit 2 mask. */ ++#define PORTCFG_VP0MAP2_bp 2 /* Virtual Port 0 Mapping bit 2 position. */ ++#define PORTCFG_VP0MAP3_bm (1<<3) /* Virtual Port 0 Mapping bit 3 mask. */ ++#define PORTCFG_VP0MAP3_bp 3 /* Virtual Port 0 Mapping bit 3 position. */ ++ ++/* PORTCFG.VPCTRLB bit masks and bit positions */ ++#define PORTCFG_VP3MAP_gm 0xF0 /* Virtual Port 3 Mapping group mask. */ ++#define PORTCFG_VP3MAP_gp 4 /* Virtual Port 3 Mapping group position. */ ++#define PORTCFG_VP3MAP0_bm (1<<4) /* Virtual Port 3 Mapping bit 0 mask. */ ++#define PORTCFG_VP3MAP0_bp 4 /* Virtual Port 3 Mapping bit 0 position. */ ++#define PORTCFG_VP3MAP1_bm (1<<5) /* Virtual Port 3 Mapping bit 1 mask. */ ++#define PORTCFG_VP3MAP1_bp 5 /* Virtual Port 3 Mapping bit 1 position. */ ++#define PORTCFG_VP3MAP2_bm (1<<6) /* Virtual Port 3 Mapping bit 2 mask. */ ++#define PORTCFG_VP3MAP2_bp 6 /* Virtual Port 3 Mapping bit 2 position. */ ++#define PORTCFG_VP3MAP3_bm (1<<7) /* Virtual Port 3 Mapping bit 3 mask. */ ++#define PORTCFG_VP3MAP3_bp 7 /* Virtual Port 3 Mapping bit 3 position. */ ++ ++#define PORTCFG_VP2MAP_gm 0x0F /* Virtual Port 2 Mapping group mask. */ ++#define PORTCFG_VP2MAP_gp 0 /* Virtual Port 2 Mapping group position. */ ++#define PORTCFG_VP2MAP0_bm (1<<0) /* Virtual Port 2 Mapping bit 0 mask. */ ++#define PORTCFG_VP2MAP0_bp 0 /* Virtual Port 2 Mapping bit 0 position. */ ++#define PORTCFG_VP2MAP1_bm (1<<1) /* Virtual Port 2 Mapping bit 1 mask. */ ++#define PORTCFG_VP2MAP1_bp 1 /* Virtual Port 2 Mapping bit 1 position. */ ++#define PORTCFG_VP2MAP2_bm (1<<2) /* Virtual Port 2 Mapping bit 2 mask. */ ++#define PORTCFG_VP2MAP2_bp 2 /* Virtual Port 2 Mapping bit 2 position. */ ++#define PORTCFG_VP2MAP3_bm (1<<3) /* Virtual Port 2 Mapping bit 3 mask. */ ++#define PORTCFG_VP2MAP3_bp 3 /* Virtual Port 2 Mapping bit 3 position. */ ++ ++/* PORTCFG.CLKEVOUT bit masks and bit positions */ ++#define PORTCFG_CLKOUT_gm 0x03 /* Peripheral Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Peripheral Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Peripheral Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Peripheral Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Peripheral Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Peripheral Clock Output Port bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Peripheral Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Peripheral Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Peripheral Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Peripheral Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Peripheral Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Peripheral Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Output Port bit 1 position. */ ++ ++#define PORTCFG_RTCOUT_bm 0x40 /* RTC Clock Output bit mask. */ ++#define PORTCFG_RTCOUT_bp 6 /* RTC Clock Output bit position. */ ++ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Peripheral Clock and Event Output pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Peripheral Clock and Event Output pin Select bit position. */ ++ ++/* PORTCFG.EVOUTSEL bit masks and bit positions */ ++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Output Select group mask. */ ++#define PORTCFG_EVOUTSEL_gp 0 /* Event Output Select group position. */ ++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Output Select bit 0 mask. */ ++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Output Select bit 0 position. */ ++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Output Select bit 1 mask. */ ++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Output Select bit 1 position. */ ++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Output Select bit 2 mask. */ ++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Output Select bit 2 position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EEMAPEN_bm 0x08 /* EEPROM Mapping Enable bit mask. */ ++#define NVM_EEMAPEN_bp 3 /* EEPROM Mapping Enable bit position. */ ++ ++#define NVM_FPRM_bm 0x04 /* Flash Power Reduction Enable bit mask. */ ++#define NVM_FPRM_bp 2 /* Flash Power Reduction Enable bit position. */ ++ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC input bit 1 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_CHIF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_CHIF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_OFFSET_gm 0xF0 /* Positive MUX setting offset group mask. */ ++#define ADC_CH_OFFSET_gp 4 /* Positive MUX setting offset group position. */ ++#define ADC_CH_OFFSET0_bm (1<<4) /* Positive MUX setting offset bit 0 mask. */ ++#define ADC_CH_OFFSET0_bp 4 /* Positive MUX setting offset bit 0 position. */ ++#define ADC_CH_OFFSET1_bm (1<<5) /* Positive MUX setting offset bit 1 mask. */ ++#define ADC_CH_OFFSET1_bp 5 /* Positive MUX setting offset bit 1 position. */ ++#define ADC_CH_OFFSET2_bm (1<<6) /* Positive MUX setting offset bit 2 mask. */ ++#define ADC_CH_OFFSET2_bp 6 /* Positive MUX setting offset bit 2 position. */ ++#define ADC_CH_OFFSET3_bm (1<<7) /* Positive MUX setting offset bit 3 mask. */ ++#define ADC_CH_OFFSET3_bp 7 /* Positive MUX setting offset bit 3 position. */ ++ ++#define ADC_CH_SCANNUM_gm 0x0F /* Number of Channels included in scan group mask. */ ++#define ADC_CH_SCANNUM_gp 0 /* Number of Channels included in scan group position. */ ++#define ADC_CH_SCANNUM0_bm (1<<0) /* Number of Channels included in scan bit 0 mask. */ ++#define ADC_CH_SCANNUM0_bp 0 /* Number of Channels included in scan bit 0 position. */ ++#define ADC_CH_SCANNUM1_bm (1<<1) /* Number of Channels included in scan bit 1 mask. */ ++#define ADC_CH_SCANNUM1_bp 1 /* Number of Channels included in scan bit 1 position. */ ++#define ADC_CH_SCANNUM2_bm (1<<2) /* Number of Channels included in scan bit 2 mask. */ ++#define ADC_CH_SCANNUM2_bp 2 /* Number of Channels included in scan bit 2 position. */ ++#define ADC_CH_SCANNUM3_bm (1<<3) /* Number of Channels included in scan bit 3 mask. */ ++#define ADC_CH_SCANNUM3_bp 3 /* Number of Channels included in scan bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_CH0START_bm 0x04 /* Channel 0 Start Conversion bit mask. */ ++#define ADC_CH0START_bp 2 /* Channel 0 Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ ++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_EVSEL_gm 0x18 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* RTC - Real-Time Counter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* PORT - I/O Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INT1LVL_gm 0x0C /* Port Interrupt 1 Level group mask. */ ++#define PORT_INT1LVL_gp 2 /* Port Interrupt 1 Level group position. */ ++#define PORT_INT1LVL0_bm (1<<2) /* Port Interrupt 1 Level bit 0 mask. */ ++#define PORT_INT1LVL0_bp 2 /* Port Interrupt 1 Level bit 0 position. */ ++#define PORT_INT1LVL1_bm (1<<3) /* Port Interrupt 1 Level bit 1 mask. */ ++#define PORT_INT1LVL1_bp 3 /* Port Interrupt 1 Level bit 1 position. */ ++ ++#define PORT_INT0LVL_gm 0x03 /* Port Interrupt 0 Level group mask. */ ++#define PORT_INT0LVL_gp 0 /* Port Interrupt 0 Level group position. */ ++#define PORT_INT0LVL0_bm (1<<0) /* Port Interrupt 0 Level bit 0 mask. */ ++#define PORT_INT0LVL0_bp 0 /* Port Interrupt 0 Level bit 0 position. */ ++#define PORT_INT0LVL1_bm (1<<1) /* Port Interrupt 0 Level bit 1 mask. */ ++#define PORT_INT0LVL1_bp 1 /* Port Interrupt 0 Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_SPI_bm 0x20 /* SPI bit mask. */ ++#define PORT_SPI_bp 5 /* SPI bit position. */ ++ ++#define PORT_USART0_bm 0x10 /* USART0 bit mask. */ ++#define PORT_USART0_bp 4 /* USART0 bit position. */ ++ ++#define PORT_TC0D_bm 0x08 /* Timer/Counter 0 Output Compare D bit mask. */ ++#define PORT_TC0D_bp 3 /* Timer/Counter 0 Output Compare D bit position. */ ++ ++#define PORT_TC0C_bm 0x04 /* Timer/Counter 0 Output Compare C bit mask. */ ++#define PORT_TC0C_bp 2 /* Timer/Counter 0 Output Compare C bit position. */ ++ ++#define PORT_TC0B_bm 0x02 /* Timer/Counter 0 Output Compare B bit mask. */ ++#define PORT_TC0B_bp 1 /* Timer/Counter 0 Output Compare B bit position. */ ++ ++#define PORT_TC0A_bm 0x01 /* Timer/Counter 0 Output Compare A bit mask. */ ++#define PORT_TC0A_bp 0 /* Timer/Counter 0 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_SRLEN_bm 0x80 /* Slew Rate Enable bit mask. */ ++#define PORT_SRLEN_bp 7 /* Slew Rate Enable bit position. */ ++ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_SRLEN Predefined. */ ++/* PORT_SRLEN Predefined. */ ++ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC0.CTRLA bit masks and bit positions */ ++#define TC0_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC0_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC0_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC0_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC0_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC0_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC0_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC0_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC0_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC0_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC0.CTRLB bit masks and bit positions */ ++#define TC0_CCDEN_bm 0x80 /* Compare or Capture D Enable bit mask. */ ++#define TC0_CCDEN_bp 7 /* Compare or Capture D Enable bit position. */ ++ ++#define TC0_CCCEN_bm 0x40 /* Compare or Capture C Enable bit mask. */ ++#define TC0_CCCEN_bp 6 /* Compare or Capture C Enable bit position. */ ++ ++#define TC0_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC0_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC0_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC0_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC0_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC0_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC0_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC0_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC0_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC0_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC0_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC0_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC0.CTRLC bit masks and bit positions */ ++#define TC0_CMPD_bm 0x08 /* Compare D Output Value bit mask. */ ++#define TC0_CMPD_bp 3 /* Compare D Output Value bit position. */ ++ ++#define TC0_CMPC_bm 0x04 /* Compare C Output Value bit mask. */ ++#define TC0_CMPC_bp 2 /* Compare C Output Value bit position. */ ++ ++#define TC0_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC0_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC0_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC0_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC0.CTRLD bit masks and bit positions */ ++#define TC0_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC0_EVACT_gp 5 /* Event Action group position. */ ++#define TC0_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC0_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC0_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC0_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC0_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC0_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC0_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC0_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC0_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC0_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC0_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC0_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC0_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC0_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC0_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC0_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC0_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC0_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC0.CTRLE bit masks and bit positions */ ++#define TC0_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC0_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC0_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC0_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC0_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC0_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC0.INTCTRLA bit masks and bit positions */ ++#define TC0_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC0_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC0_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC0_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC0_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC0_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC0_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC0_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC0_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC0_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC0_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC0_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC0.INTCTRLB bit masks and bit positions */ ++#define TC0_CCDINTLVL_gm 0xC0 /* Compare or Capture D Interrupt Level group mask. */ ++#define TC0_CCDINTLVL_gp 6 /* Compare or Capture D Interrupt Level group position. */ ++#define TC0_CCDINTLVL0_bm (1<<6) /* Compare or Capture D Interrupt Level bit 0 mask. */ ++#define TC0_CCDINTLVL0_bp 6 /* Compare or Capture D Interrupt Level bit 0 position. */ ++#define TC0_CCDINTLVL1_bm (1<<7) /* Compare or Capture D Interrupt Level bit 1 mask. */ ++#define TC0_CCDINTLVL1_bp 7 /* Compare or Capture D Interrupt Level bit 1 position. */ ++ ++#define TC0_CCCINTLVL_gm 0x30 /* Compare or Capture C Interrupt Level group mask. */ ++#define TC0_CCCINTLVL_gp 4 /* Compare or Capture C Interrupt Level group position. */ ++#define TC0_CCCINTLVL0_bm (1<<4) /* Compare or Capture C Interrupt Level bit 0 mask. */ ++#define TC0_CCCINTLVL0_bp 4 /* Compare or Capture C Interrupt Level bit 0 position. */ ++#define TC0_CCCINTLVL1_bm (1<<5) /* Compare or Capture C Interrupt Level bit 1 mask. */ ++#define TC0_CCCINTLVL1_bp 5 /* Compare or Capture C Interrupt Level bit 1 position. */ ++ ++#define TC0_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC0_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC0_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC0_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC0_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC0_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC0_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC0_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC0_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC0_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC0_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC0_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC0.CTRLFCLR bit masks and bit positions */ ++#define TC0_CMD_gm 0x0C /* Command group mask. */ ++#define TC0_CMD_gp 2 /* Command group position. */ ++#define TC0_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC0_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC0_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC0_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC0_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC0_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC0_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC0_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC0.CTRLFSET bit masks and bit positions */ ++/* TC0_CMD Predefined. */ ++/* TC0_CMD Predefined. */ ++ ++/* TC0_LUPD Predefined. */ ++/* TC0_LUPD Predefined. */ ++ ++/* TC0_DIR Predefined. */ ++/* TC0_DIR Predefined. */ ++ ++/* TC0.CTRLGCLR bit masks and bit positions */ ++#define TC0_CCDBV_bm 0x10 /* Compare or Capture D Buffer Valid bit mask. */ ++#define TC0_CCDBV_bp 4 /* Compare or Capture D Buffer Valid bit position. */ ++ ++#define TC0_CCCBV_bm 0x08 /* Compare or Capture C Buffer Valid bit mask. */ ++#define TC0_CCCBV_bp 3 /* Compare or Capture C Buffer Valid bit position. */ ++ ++#define TC0_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC0_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC0_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC0_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC0_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC0_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC0.CTRLGSET bit masks and bit positions */ ++/* TC0_CCDBV Predefined. */ ++/* TC0_CCDBV Predefined. */ ++ ++/* TC0_CCCBV Predefined. */ ++/* TC0_CCCBV Predefined. */ ++ ++/* TC0_CCBBV Predefined. */ ++/* TC0_CCBBV Predefined. */ ++ ++/* TC0_CCABV Predefined. */ ++/* TC0_CCABV Predefined. */ ++ ++/* TC0_PERBV Predefined. */ ++/* TC0_PERBV Predefined. */ ++ ++/* TC0.INTFLAGS bit masks and bit positions */ ++#define TC0_CCDIF_bm 0x80 /* Compare or Capture D Interrupt Flag bit mask. */ ++#define TC0_CCDIF_bp 7 /* Compare or Capture D Interrupt Flag bit position. */ ++ ++#define TC0_CCCIF_bm 0x40 /* Compare or Capture C Interrupt Flag bit mask. */ ++#define TC0_CCCIF_bp 6 /* Compare or Capture C Interrupt Flag bit position. */ ++ ++#define TC0_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC0_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC0_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC0_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC0_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC0_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC0_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC0_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC1.CTRLA bit masks and bit positions */ ++#define TC1_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC1_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC1_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC1_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC1_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC1_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC1_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC1_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC1_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC1_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC1.CTRLB bit masks and bit positions */ ++#define TC1_CCBEN_bm 0x20 /* Compare or Capture B Enable bit mask. */ ++#define TC1_CCBEN_bp 5 /* Compare or Capture B Enable bit position. */ ++ ++#define TC1_CCAEN_bm 0x10 /* Compare or Capture A Enable bit mask. */ ++#define TC1_CCAEN_bp 4 /* Compare or Capture A Enable bit position. */ ++ ++#define TC1_WGMODE_gm 0x07 /* Waveform generation mode group mask. */ ++#define TC1_WGMODE_gp 0 /* Waveform generation mode group position. */ ++#define TC1_WGMODE0_bm (1<<0) /* Waveform generation mode bit 0 mask. */ ++#define TC1_WGMODE0_bp 0 /* Waveform generation mode bit 0 position. */ ++#define TC1_WGMODE1_bm (1<<1) /* Waveform generation mode bit 1 mask. */ ++#define TC1_WGMODE1_bp 1 /* Waveform generation mode bit 1 position. */ ++#define TC1_WGMODE2_bm (1<<2) /* Waveform generation mode bit 2 mask. */ ++#define TC1_WGMODE2_bp 2 /* Waveform generation mode bit 2 position. */ ++ ++/* TC1.CTRLC bit masks and bit positions */ ++#define TC1_CMPB_bm 0x02 /* Compare B Output Value bit mask. */ ++#define TC1_CMPB_bp 1 /* Compare B Output Value bit position. */ ++ ++#define TC1_CMPA_bm 0x01 /* Compare A Output Value bit mask. */ ++#define TC1_CMPA_bp 0 /* Compare A Output Value bit position. */ ++ ++/* TC1.CTRLD bit masks and bit positions */ ++#define TC1_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC1_EVACT_gp 5 /* Event Action group position. */ ++#define TC1_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC1_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC1_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC1_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC1_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC1_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC1_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC1_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC1_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC1_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC1_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC1_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC1_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC1_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC1_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC1_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC1_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC1_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC1.CTRLE bit masks and bit positions */ ++#define TC1_BYTEM_bm 0x01 /* Byte Mode bit mask. */ ++#define TC1_BYTEM_bp 0 /* Byte Mode bit position. */ ++ ++/* TC1.INTCTRLA bit masks and bit positions */ ++#define TC1_ERRINTLVL_gm 0x0C /* Error Interrupt Level group mask. */ ++#define TC1_ERRINTLVL_gp 2 /* Error Interrupt Level group position. */ ++#define TC1_ERRINTLVL0_bm (1<<2) /* Error Interrupt Level bit 0 mask. */ ++#define TC1_ERRINTLVL0_bp 2 /* Error Interrupt Level bit 0 position. */ ++#define TC1_ERRINTLVL1_bm (1<<3) /* Error Interrupt Level bit 1 mask. */ ++#define TC1_ERRINTLVL1_bp 3 /* Error Interrupt Level bit 1 position. */ ++ ++#define TC1_OVFINTLVL_gm 0x03 /* Overflow interrupt level group mask. */ ++#define TC1_OVFINTLVL_gp 0 /* Overflow interrupt level group position. */ ++#define TC1_OVFINTLVL0_bm (1<<0) /* Overflow interrupt level bit 0 mask. */ ++#define TC1_OVFINTLVL0_bp 0 /* Overflow interrupt level bit 0 position. */ ++#define TC1_OVFINTLVL1_bm (1<<1) /* Overflow interrupt level bit 1 mask. */ ++#define TC1_OVFINTLVL1_bp 1 /* Overflow interrupt level bit 1 position. */ ++ ++/* TC1.INTCTRLB bit masks and bit positions */ ++#define TC1_CCBINTLVL_gm 0x0C /* Compare or Capture B Interrupt Level group mask. */ ++#define TC1_CCBINTLVL_gp 2 /* Compare or Capture B Interrupt Level group position. */ ++#define TC1_CCBINTLVL0_bm (1<<2) /* Compare or Capture B Interrupt Level bit 0 mask. */ ++#define TC1_CCBINTLVL0_bp 2 /* Compare or Capture B Interrupt Level bit 0 position. */ ++#define TC1_CCBINTLVL1_bm (1<<3) /* Compare or Capture B Interrupt Level bit 1 mask. */ ++#define TC1_CCBINTLVL1_bp 3 /* Compare or Capture B Interrupt Level bit 1 position. */ ++ ++#define TC1_CCAINTLVL_gm 0x03 /* Compare or Capture A Interrupt Level group mask. */ ++#define TC1_CCAINTLVL_gp 0 /* Compare or Capture A Interrupt Level group position. */ ++#define TC1_CCAINTLVL0_bm (1<<0) /* Compare or Capture A Interrupt Level bit 0 mask. */ ++#define TC1_CCAINTLVL0_bp 0 /* Compare or Capture A Interrupt Level bit 0 position. */ ++#define TC1_CCAINTLVL1_bm (1<<1) /* Compare or Capture A Interrupt Level bit 1 mask. */ ++#define TC1_CCAINTLVL1_bp 1 /* Compare or Capture A Interrupt Level bit 1 position. */ ++ ++/* TC1.CTRLFCLR bit masks and bit positions */ ++#define TC1_CMD_gm 0x0C /* Command group mask. */ ++#define TC1_CMD_gp 2 /* Command group position. */ ++#define TC1_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC1_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC1_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC1_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC1_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC1_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC1_DIR_bm 0x01 /* Direction bit mask. */ ++#define TC1_DIR_bp 0 /* Direction bit position. */ ++ ++/* TC1.CTRLFSET bit masks and bit positions */ ++/* TC1_CMD Predefined. */ ++/* TC1_CMD Predefined. */ ++ ++/* TC1_LUPD Predefined. */ ++/* TC1_LUPD Predefined. */ ++ ++/* TC1_DIR Predefined. */ ++/* TC1_DIR Predefined. */ ++ ++/* TC1.CTRLGCLR bit masks and bit positions */ ++#define TC1_CCBBV_bm 0x04 /* Compare or Capture B Buffer Valid bit mask. */ ++#define TC1_CCBBV_bp 2 /* Compare or Capture B Buffer Valid bit position. */ ++ ++#define TC1_CCABV_bm 0x02 /* Compare or Capture A Buffer Valid bit mask. */ ++#define TC1_CCABV_bp 1 /* Compare or Capture A Buffer Valid bit position. */ ++ ++#define TC1_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC1_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++/* TC1.CTRLGSET bit masks and bit positions */ ++/* TC1_CCBBV Predefined. */ ++/* TC1_CCBBV Predefined. */ ++ ++/* TC1_CCABV Predefined. */ ++/* TC1_CCABV Predefined. */ ++ ++/* TC1_PERBV Predefined. */ ++/* TC1_PERBV Predefined. */ ++ ++/* TC1.INTFLAGS bit masks and bit positions */ ++#define TC1_CCBIF_bm 0x20 /* Compare or Capture B Interrupt Flag bit mask. */ ++#define TC1_CCBIF_bp 5 /* Compare or Capture B Interrupt Flag bit position. */ ++ ++#define TC1_CCAIF_bm 0x10 /* Compare or Capture A Interrupt Flag bit mask. */ ++#define TC1_CCAIF_bp 4 /* Compare or Capture A Interrupt Flag bit position. */ ++ ++#define TC1_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC1_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC1_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define TC1_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* TC2 - 16-bit Timer/Counter type 2 */ ++/* TC2.CTRLA bit masks and bit positions */ ++#define TC2_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define TC2_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define TC2_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define TC2_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define TC2_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define TC2_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define TC2_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define TC2_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define TC2_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define TC2_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* TC2.CTRLB bit masks and bit positions */ ++#define TC2_HCMPDEN_bm 0x80 /* High Byte Compare D Enable bit mask. */ ++#define TC2_HCMPDEN_bp 7 /* High Byte Compare D Enable bit position. */ ++ ++#define TC2_HCMPCEN_bm 0x40 /* High Byte Compare C Enable bit mask. */ ++#define TC2_HCMPCEN_bp 6 /* High Byte Compare C Enable bit position. */ ++ ++#define TC2_HCMPBEN_bm 0x20 /* High Byte Compare B Enable bit mask. */ ++#define TC2_HCMPBEN_bp 5 /* High Byte Compare B Enable bit position. */ ++ ++#define TC2_HCMPAEN_bm 0x10 /* High Byte Compare A Enable bit mask. */ ++#define TC2_HCMPAEN_bp 4 /* High Byte Compare A Enable bit position. */ ++ ++#define TC2_LCMPDEN_bm 0x08 /* Low Byte Compare D Enable bit mask. */ ++#define TC2_LCMPDEN_bp 3 /* Low Byte Compare D Enable bit position. */ ++ ++#define TC2_LCMPCEN_bm 0x04 /* Low Byte Compare C Enable bit mask. */ ++#define TC2_LCMPCEN_bp 2 /* Low Byte Compare C Enable bit position. */ ++ ++#define TC2_LCMPBEN_bm 0x02 /* Low Byte Compare B Enable bit mask. */ ++#define TC2_LCMPBEN_bp 1 /* Low Byte Compare B Enable bit position. */ ++ ++#define TC2_LCMPAEN_bm 0x01 /* Low Byte Compare A Enable bit mask. */ ++#define TC2_LCMPAEN_bp 0 /* Low Byte Compare A Enable bit position. */ ++ ++/* TC2.CTRLC bit masks and bit positions */ ++#define TC2_HCMPD_bm 0x80 /* High Byte Compare D Output Value bit mask. */ ++#define TC2_HCMPD_bp 7 /* High Byte Compare D Output Value bit position. */ ++ ++#define TC2_HCMPC_bm 0x40 /* High Byte Compare C Output Value bit mask. */ ++#define TC2_HCMPC_bp 6 /* High Byte Compare C Output Value bit position. */ ++ ++#define TC2_HCMPB_bm 0x20 /* High Byte Compare B Output Value bit mask. */ ++#define TC2_HCMPB_bp 5 /* High Byte Compare B Output Value bit position. */ ++ ++#define TC2_HCMPA_bm 0x10 /* High Byte Compare A Output Value bit mask. */ ++#define TC2_HCMPA_bp 4 /* High Byte Compare A Output Value bit position. */ ++ ++#define TC2_LCMPD_bm 0x08 /* Low Byte Compare D Output Value bit mask. */ ++#define TC2_LCMPD_bp 3 /* Low Byte Compare D Output Value bit position. */ ++ ++#define TC2_LCMPC_bm 0x04 /* Low Byte Compare C Output Value bit mask. */ ++#define TC2_LCMPC_bp 2 /* Low Byte Compare C Output Value bit position. */ ++ ++#define TC2_LCMPB_bm 0x02 /* Low Byte Compare B Output Value bit mask. */ ++#define TC2_LCMPB_bp 1 /* Low Byte Compare B Output Value bit position. */ ++ ++#define TC2_LCMPA_bm 0x01 /* Low Byte Compare A Output Value bit mask. */ ++#define TC2_LCMPA_bp 0 /* Low Byte Compare A Output Value bit position. */ ++ ++/* TC2.CTRLE bit masks and bit positions */ ++#define TC2_BYTEM_gm 0x03 /* Byte Mode group mask. */ ++#define TC2_BYTEM_gp 0 /* Byte Mode group position. */ ++#define TC2_BYTEM0_bm (1<<0) /* Byte Mode bit 0 mask. */ ++#define TC2_BYTEM0_bp 0 /* Byte Mode bit 0 position. */ ++#define TC2_BYTEM1_bm (1<<1) /* Byte Mode bit 1 mask. */ ++#define TC2_BYTEM1_bp 1 /* Byte Mode bit 1 position. */ ++ ++/* TC2.INTCTRLA bit masks and bit positions */ ++#define TC2_HUNFINTLVL_gm 0x0C /* High Byte Underflow Interrupt Level group mask. */ ++#define TC2_HUNFINTLVL_gp 2 /* High Byte Underflow Interrupt Level group position. */ ++#define TC2_HUNFINTLVL0_bm (1<<2) /* High Byte Underflow Interrupt Level bit 0 mask. */ ++#define TC2_HUNFINTLVL0_bp 2 /* High Byte Underflow Interrupt Level bit 0 position. */ ++#define TC2_HUNFINTLVL1_bm (1<<3) /* High Byte Underflow Interrupt Level bit 1 mask. */ ++#define TC2_HUNFINTLVL1_bp 3 /* High Byte Underflow Interrupt Level bit 1 position. */ ++ ++#define TC2_LUNFINTLVL_gm 0x03 /* Low Byte Underflow interrupt level group mask. */ ++#define TC2_LUNFINTLVL_gp 0 /* Low Byte Underflow interrupt level group position. */ ++#define TC2_LUNFINTLVL0_bm (1<<0) /* Low Byte Underflow interrupt level bit 0 mask. */ ++#define TC2_LUNFINTLVL0_bp 0 /* Low Byte Underflow interrupt level bit 0 position. */ ++#define TC2_LUNFINTLVL1_bm (1<<1) /* Low Byte Underflow interrupt level bit 1 mask. */ ++#define TC2_LUNFINTLVL1_bp 1 /* Low Byte Underflow interrupt level bit 1 position. */ ++ ++/* TC2.INTCTRLB bit masks and bit positions */ ++#define TC2_LCMPDINTLVL_gm 0xC0 /* Low Byte Compare D Interrupt Level group mask. */ ++#define TC2_LCMPDINTLVL_gp 6 /* Low Byte Compare D Interrupt Level group position. */ ++#define TC2_LCMPDINTLVL0_bm (1<<6) /* Low Byte Compare D Interrupt Level bit 0 mask. */ ++#define TC2_LCMPDINTLVL0_bp 6 /* Low Byte Compare D Interrupt Level bit 0 position. */ ++#define TC2_LCMPDINTLVL1_bm (1<<7) /* Low Byte Compare D Interrupt Level bit 1 mask. */ ++#define TC2_LCMPDINTLVL1_bp 7 /* Low Byte Compare D Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPCINTLVL_gm 0x30 /* Low Byte Compare C Interrupt Level group mask. */ ++#define TC2_LCMPCINTLVL_gp 4 /* Low Byte Compare C Interrupt Level group position. */ ++#define TC2_LCMPCINTLVL0_bm (1<<4) /* Low Byte Compare C Interrupt Level bit 0 mask. */ ++#define TC2_LCMPCINTLVL0_bp 4 /* Low Byte Compare C Interrupt Level bit 0 position. */ ++#define TC2_LCMPCINTLVL1_bm (1<<5) /* Low Byte Compare C Interrupt Level bit 1 mask. */ ++#define TC2_LCMPCINTLVL1_bp 5 /* Low Byte Compare C Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPBINTLVL_gm 0x0C /* Low Byte Compare B Interrupt Level group mask. */ ++#define TC2_LCMPBINTLVL_gp 2 /* Low Byte Compare B Interrupt Level group position. */ ++#define TC2_LCMPBINTLVL0_bm (1<<2) /* Low Byte Compare B Interrupt Level bit 0 mask. */ ++#define TC2_LCMPBINTLVL0_bp 2 /* Low Byte Compare B Interrupt Level bit 0 position. */ ++#define TC2_LCMPBINTLVL1_bm (1<<3) /* Low Byte Compare B Interrupt Level bit 1 mask. */ ++#define TC2_LCMPBINTLVL1_bp 3 /* Low Byte Compare B Interrupt Level bit 1 position. */ ++ ++#define TC2_LCMPAINTLVL_gm 0x03 /* Low Byte Compare A Interrupt Level group mask. */ ++#define TC2_LCMPAINTLVL_gp 0 /* Low Byte Compare A Interrupt Level group position. */ ++#define TC2_LCMPAINTLVL0_bm (1<<0) /* Low Byte Compare A Interrupt Level bit 0 mask. */ ++#define TC2_LCMPAINTLVL0_bp 0 /* Low Byte Compare A Interrupt Level bit 0 position. */ ++#define TC2_LCMPAINTLVL1_bm (1<<1) /* Low Byte Compare A Interrupt Level bit 1 mask. */ ++#define TC2_LCMPAINTLVL1_bp 1 /* Low Byte Compare A Interrupt Level bit 1 position. */ ++ ++/* TC2.CTRLF bit masks and bit positions */ ++#define TC2_CMD_gm 0x0C /* Command group mask. */ ++#define TC2_CMD_gp 2 /* Command group position. */ ++#define TC2_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC2_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC2_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC2_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC2_CMDEN_gm 0x03 /* Command Enable group mask. */ ++#define TC2_CMDEN_gp 0 /* Command Enable group position. */ ++#define TC2_CMDEN0_bm (1<<0) /* Command Enable bit 0 mask. */ ++#define TC2_CMDEN0_bp 0 /* Command Enable bit 0 position. */ ++#define TC2_CMDEN1_bm (1<<1) /* Command Enable bit 1 mask. */ ++#define TC2_CMDEN1_bp 1 /* Command Enable bit 1 position. */ ++ ++/* TC2.INTFLAGS bit masks and bit positions */ ++#define TC2_LCMPDIF_bm 0x80 /* Low Byte Compare D Interrupt Flag bit mask. */ ++#define TC2_LCMPDIF_bp 7 /* Low Byte Compare D Interrupt Flag bit position. */ ++ ++#define TC2_LCMPCIF_bm 0x40 /* Low Byte Compare C Interrupt Flag bit mask. */ ++#define TC2_LCMPCIF_bp 6 /* Low Byte Compare C Interrupt Flag bit position. */ ++ ++#define TC2_LCMPBIF_bm 0x20 /* Low Byte Compare B Interrupt Flag bit mask. */ ++#define TC2_LCMPBIF_bp 5 /* Low Byte Compare B Interrupt Flag bit position. */ ++ ++#define TC2_LCMPAIF_bm 0x10 /* Low Byte Compare A Interrupt Flag bit mask. */ ++#define TC2_LCMPAIF_bp 4 /* Low Byte Compare A Interrupt Flag bit position. */ ++ ++#define TC2_HUNFIF_bm 0x02 /* High Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_HUNFIF_bp 1 /* High Byte Underflow Interrupt Flag bit position. */ ++ ++#define TC2_LUNFIF_bm 0x01 /* Low Byte Underflow Interrupt Flag bit mask. */ ++#define TC2_LUNFIF_bp 0 /* Low Byte Underflow Interrupt Flag bit position. */ ++ ++/* AWEX - Timer/Counter Advanced Waveform Extension */ ++/* AWEX.CTRL bit masks and bit positions */ ++#define AWEX_PGM_bm 0x20 /* Pattern Generation Mode bit mask. */ ++#define AWEX_PGM_bp 5 /* Pattern Generation Mode bit position. */ ++ ++#define AWEX_CWCM_bm 0x10 /* Common Waveform Channel Mode bit mask. */ ++#define AWEX_CWCM_bp 4 /* Common Waveform Channel Mode bit position. */ ++ ++#define AWEX_DTICCDEN_bm 0x08 /* Dead Time Insertion Compare Channel D Enable bit mask. */ ++#define AWEX_DTICCDEN_bp 3 /* Dead Time Insertion Compare Channel D Enable bit position. */ ++ ++#define AWEX_DTICCCEN_bm 0x04 /* Dead Time Insertion Compare Channel C Enable bit mask. */ ++#define AWEX_DTICCCEN_bp 2 /* Dead Time Insertion Compare Channel C Enable bit position. */ ++ ++#define AWEX_DTICCBEN_bm 0x02 /* Dead Time Insertion Compare Channel B Enable bit mask. */ ++#define AWEX_DTICCBEN_bp 1 /* Dead Time Insertion Compare Channel B Enable bit position. */ ++ ++#define AWEX_DTICCAEN_bm 0x01 /* Dead Time Insertion Compare Channel A Enable bit mask. */ ++#define AWEX_DTICCAEN_bp 0 /* Dead Time Insertion Compare Channel A Enable bit position. */ ++ ++/* AWEX.FDCTRL bit masks and bit positions */ ++#define AWEX_FDDBD_bm 0x10 /* Fault Detect on Disable Break Disable bit mask. */ ++#define AWEX_FDDBD_bp 4 /* Fault Detect on Disable Break Disable bit position. */ ++ ++#define AWEX_FDMODE_bm 0x04 /* Fault Detect Mode bit mask. */ ++#define AWEX_FDMODE_bp 2 /* Fault Detect Mode bit position. */ ++ ++#define AWEX_FDACT_gm 0x03 /* Fault Detect Action group mask. */ ++#define AWEX_FDACT_gp 0 /* Fault Detect Action group position. */ ++#define AWEX_FDACT0_bm (1<<0) /* Fault Detect Action bit 0 mask. */ ++#define AWEX_FDACT0_bp 0 /* Fault Detect Action bit 0 position. */ ++#define AWEX_FDACT1_bm (1<<1) /* Fault Detect Action bit 1 mask. */ ++#define AWEX_FDACT1_bp 1 /* Fault Detect Action bit 1 position. */ ++ ++/* AWEX.STATUS bit masks and bit positions */ ++#define AWEX_FDF_bm 0x04 /* Fault Detect Flag bit mask. */ ++#define AWEX_FDF_bp 2 /* Fault Detect Flag bit position. */ ++ ++#define AWEX_DTHSBUFV_bm 0x02 /* Dead Time High Side Buffer Valid bit mask. */ ++#define AWEX_DTHSBUFV_bp 1 /* Dead Time High Side Buffer Valid bit position. */ ++ ++#define AWEX_DTLSBUFV_bm 0x01 /* Dead Time Low Side Buffer Valid bit mask. */ ++#define AWEX_DTLSBUFV_bp 0 /* Dead Time Low Side Buffer Valid bit position. */ ++ ++/* AWEX.STATUSSET bit masks and bit positions */ ++/* AWEX_FDF Predefined. */ ++/* AWEX_FDF Predefined. */ ++ ++/* AWEX_DTHSBUFV Predefined. */ ++/* AWEX_DTHSBUFV Predefined. */ ++ ++/* AWEX_DTLSBUFV Predefined. */ ++/* AWEX_DTLSBUFV Predefined. */ ++ ++/* HIRES - Timer/Counter High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HREN_gm 0x03 /* High Resolution Enable group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Enable group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Enable bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Enable bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Enable bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Enable bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_TOSCSEL_bm 0x20 /* Timer Oscillator pin location bit mask. */ ++#define NVM_FUSES_TOSCSEL_bp 5 /* Timer Oscillator pin location bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* LOCKBIT - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT0_vect_num 2 ++#define PORTC_INT0_vect _VECTOR(2) /* External Interrupt 0 */ ++#define PORTC_INT1_vect_num 3 ++#define PORTC_INT1_vect _VECTOR(3) /* External Interrupt 1 */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT0_vect_num 4 ++#define PORTR_INT0_vect _VECTOR(4) /* External Interrupt 0 */ ++#define PORTR_INT1_vect_num 5 ++#define PORTR_INT1_vect _VECTOR(5) /* External Interrupt 1 */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 10 ++#define RTC_OVF_vect _VECTOR(10) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 11 ++#define RTC_COMP_vect _VECTOR(11) /* Compare Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 12 ++#define TWIC_TWIS_vect _VECTOR(12) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 13 ++#define TWIC_TWIM_vect _VECTOR(13) /* TWI Master Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_OVF_vect_num 14 ++#define TCC0_OVF_vect _VECTOR(14) /* Overflow Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LUNF_vect_num 14 ++#define TCC2_LUNF_vect _VECTOR(14) /* Low Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_ERR_vect_num 15 ++#define TCC0_ERR_vect _VECTOR(15) /* Error Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_HUNF_vect_num 15 ++#define TCC2_HUNF_vect _VECTOR(15) /* High Byte Underflow Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCA_vect_num 16 ++#define TCC0_CCA_vect _VECTOR(16) /* Compare or Capture A Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPA_vect_num 16 ++#define TCC2_LCMPA_vect _VECTOR(16) /* Low Byte Compare A Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCB_vect_num 17 ++#define TCC0_CCB_vect _VECTOR(17) /* Compare or Capture B Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPB_vect_num 17 ++#define TCC2_LCMPB_vect _VECTOR(17) /* Low Byte Compare B Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCC_vect_num 18 ++#define TCC0_CCC_vect _VECTOR(18) /* Compare or Capture C Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPC_vect_num 18 ++#define TCC2_LCMPC_vect _VECTOR(18) /* Low Byte Compare C Interrupt */ ++ ++/* TCC0 interrupt vectors */ ++#define TCC0_CCD_vect_num 19 ++#define TCC0_CCD_vect _VECTOR(19) /* Compare or Capture D Interrupt */ ++ ++/* TCC2 interrupt vectors */ ++#define TCC2_LCMPD_vect_num 19 ++#define TCC2_LCMPD_vect _VECTOR(19) /* Low Byte Compare D Interrupt */ ++ ++/* TCC1 interrupt vectors */ ++#define TCC1_OVF_vect_num 20 ++#define TCC1_OVF_vect _VECTOR(20) /* Overflow Interrupt */ ++#define TCC1_ERR_vect_num 21 ++#define TCC1_ERR_vect _VECTOR(21) /* Error Interrupt */ ++#define TCC1_CCA_vect_num 22 ++#define TCC1_CCA_vect _VECTOR(22) /* Compare or Capture A Interrupt */ ++#define TCC1_CCB_vect_num 23 ++#define TCC1_CCB_vect _VECTOR(23) /* Compare or Capture B Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 24 ++#define SPIC_INT_vect _VECTOR(24) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 25 ++#define USARTC0_RXC_vect _VECTOR(25) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 26 ++#define USARTC0_DRE_vect _VECTOR(26) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 27 ++#define USARTC0_TXC_vect _VECTOR(27) /* Transmission Complete Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 32 ++#define NVM_EE_vect _VECTOR(32) /* EE Interrupt */ ++#define NVM_SPM_vect_num 33 ++#define NVM_SPM_vect _VECTOR(33) /* SPM Interrupt */ ++ ++/* PORTB interrupt vectors */ ++#define PORTB_INT0_vect_num 34 ++#define PORTB_INT0_vect _VECTOR(34) /* External Interrupt 0 */ ++#define PORTB_INT1_vect_num 35 ++#define PORTB_INT1_vect _VECTOR(35) /* External Interrupt 1 */ ++ ++/* PORTE interrupt vectors */ ++#define PORTE_INT0_vect_num 43 ++#define PORTE_INT0_vect _VECTOR(43) /* External Interrupt 0 */ ++#define PORTE_INT1_vect_num 44 ++#define PORTE_INT1_vect _VECTOR(44) /* External Interrupt 1 */ ++ ++/* TWIE interrupt vectors */ ++#define TWIE_TWIS_vect_num 45 ++#define TWIE_TWIS_vect _VECTOR(45) /* TWI Slave Interrupt */ ++#define TWIE_TWIM_vect_num 46 ++#define TWIE_TWIM_vect _VECTOR(46) /* TWI Master Interrupt */ ++ ++/* TCE0 interrupt vectors */ ++#define TCE0_OVF_vect_num 47 ++#define TCE0_OVF_vect _VECTOR(47) /* Overflow Interrupt */ ++#define TCE0_ERR_vect_num 48 ++#define TCE0_ERR_vect _VECTOR(48) /* Error Interrupt */ ++#define TCE0_CCA_vect_num 49 ++#define TCE0_CCA_vect _VECTOR(49) /* Compare or Capture A Interrupt */ ++#define TCE0_CCB_vect_num 50 ++#define TCE0_CCB_vect _VECTOR(50) /* Compare or Capture B Interrupt */ ++#define TCE0_CCC_vect_num 51 ++#define TCE0_CCC_vect _VECTOR(51) /* Compare or Capture C Interrupt */ ++#define TCE0_CCD_vect_num 52 ++#define TCE0_CCD_vect _VECTOR(52) /* Compare or Capture D Interrupt */ ++ ++/* USARTE0 interrupt vectors */ ++#define USARTE0_RXC_vect_num 58 ++#define USARTE0_RXC_vect _VECTOR(58) /* Reception Complete Interrupt */ ++#define USARTE0_DRE_vect_num 59 ++#define USARTE0_DRE_vect _VECTOR(59) /* Data Register Empty Interrupt */ ++#define USARTE0_TXC_vect_num 60 ++#define USARTE0_TXC_vect _VECTOR(60) /* Transmission Complete Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT0_vect_num 64 ++#define PORTD_INT0_vect _VECTOR(64) /* External Interrupt 0 */ ++#define PORTD_INT1_vect_num 65 ++#define PORTD_INT1_vect _VECTOR(65) /* External Interrupt 1 */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT0_vect_num 66 ++#define PORTA_INT0_vect _VECTOR(66) /* External Interrupt 0 */ ++#define PORTA_INT1_vect_num 67 ++#define PORTA_INT1_vect _VECTOR(67) /* External Interrupt 1 */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 68 ++#define ACA_AC0_vect _VECTOR(68) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 69 ++#define ACA_AC1_vect _VECTOR(69) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 70 ++#define ACA_ACW_vect _VECTOR(70) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 71 ++#define ADCA_CH0_vect _VECTOR(71) /* Interrupt 0 */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_OVF_vect_num 77 ++#define TCD0_OVF_vect _VECTOR(77) /* Overflow Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LUNF_vect_num 77 ++#define TCD2_LUNF_vect _VECTOR(77) /* Low Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_ERR_vect_num 78 ++#define TCD0_ERR_vect _VECTOR(78) /* Error Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_HUNF_vect_num 78 ++#define TCD2_HUNF_vect _VECTOR(78) /* High Byte Underflow Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCA_vect_num 79 ++#define TCD0_CCA_vect _VECTOR(79) /* Compare or Capture A Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPA_vect_num 79 ++#define TCD2_LCMPA_vect _VECTOR(79) /* Low Byte Compare A Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCB_vect_num 80 ++#define TCD0_CCB_vect _VECTOR(80) /* Compare or Capture B Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPB_vect_num 80 ++#define TCD2_LCMPB_vect _VECTOR(80) /* Low Byte Compare B Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCC_vect_num 81 ++#define TCD0_CCC_vect _VECTOR(81) /* Compare or Capture C Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPC_vect_num 81 ++#define TCD2_LCMPC_vect _VECTOR(81) /* Low Byte Compare C Interrupt */ ++ ++/* TCD0 interrupt vectors */ ++#define TCD0_CCD_vect_num 82 ++#define TCD0_CCD_vect _VECTOR(82) /* Compare or Capture D Interrupt */ ++ ++/* TCD2 interrupt vectors */ ++#define TCD2_LCMPD_vect_num 82 ++#define TCD2_LCMPD_vect _VECTOR(82) /* Low Byte Compare D Interrupt */ ++ ++/* SPID interrupt vectors */ ++#define SPID_INT_vect_num 87 ++#define SPID_INT_vect _VECTOR(87) /* SPI Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 88 ++#define USARTD0_RXC_vect _VECTOR(88) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 89 ++#define USARTD0_DRE_vect _VECTOR(89) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 90 ++#define USARTD0_TXC_vect _VECTOR(90) /* Transmission Complete Interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (91 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (69632) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (65536) ++#define APP_SECTION_PAGE_SIZE (256) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0xF000) ++#define APPTABLE_SECTION_SIZE (4096) ++#define APPTABLE_SECTION_PAGE_SIZE (256) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x10000) ++#define BOOT_SECTION_SIZE (4096) ++#define BOOT_SECTION_PAGE_SIZE (256) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (12288) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (2048) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (4096) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (2048) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (6) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (256) ++#define USER_SIGNATURES_PAGE_SIZE (256) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (64) ++#define PROD_SIGNATURES_PAGE_SIZE (256) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 256 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 6 ++ ++/* Fuse Byte 0 Reserved */ ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_TOSCSEL (unsigned char)~_BV(5) /* Timer Oscillator pin location */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x96 ++#define SIGNATURE_2 0x47 ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA64D4_H_INCLUDED */ ++ diff --git a/include/avr/iox8e5.h b/include/avr/iox8e5.h new file mode 100644 -index 0000000..9175001 +index 0000000..4e9d7e1 --- /dev/null +++ b/include/avr/iox8e5.h @@ -0,0 +1,7664 @@ -+/***************************************************************************** -+ * -+ * Copyright (C) 2014 Atmel Corporation -+ * All rights reserved. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in -+ * the documentation and/or other materials provided with the -+ * distribution. -+ * -+ * * Neither the name of the copyright holders nor the names of -+ * contributors may be used to endorse or promote products derived -+ * from this software without specific prior written permission. -+ * -+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE -+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -+ * POSSIBILITY OF SUCH DAMAGE. -+ ****************************************************************************/ -+ -+ -+#ifndef _AVR_IO_H_ -+# error "Include instead of this file." -+#endif -+ -+#ifndef _AVR_IOXXX_H_ -+# define _AVR_IOXXX_H_ "iox8e5.h" -+#else -+# error "Attempt to include more than one file." -+#endif -+ -+#ifndef _AVR_ATXMEGA8E5_H_INCLUDED -+#define _AVR_ATXMEGA8E5_H_INCLUDED -+ -+/* Ungrouped common registers */ -+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+/* Deprecated */ -+#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ -+#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ -+#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ -+#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ -+ -+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ -+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ -+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ -+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ -+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ -+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ -+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ -+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ -+#define SREG _SFR_MEM8(0x003F) /* Status Register */ -+ -+/* C Language Only */ -+#if !defined (__ASSEMBLER__) -+ -+#include -+ -+typedef volatile uint8_t register8_t; -+typedef volatile uint16_t register16_t; -+typedef volatile uint32_t register32_t; -+ -+ -+#ifdef _WORDREGISTER -+#undef _WORDREGISTER -+#endif -+#define _WORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register16_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## L; \ -+ register8_t regname ## H; \ -+ }; \ -+ } -+ -+#ifdef _DWORDREGISTER -+#undef _DWORDREGISTER -+#endif -+#define _DWORDREGISTER(regname) \ -+ __extension__ union \ -+ { \ -+ register32_t regname; \ -+ struct \ -+ { \ -+ register8_t regname ## 0; \ -+ register8_t regname ## 1; \ -+ register8_t regname ## 2; \ -+ register8_t regname ## 3; \ -+ }; \ -+ } -+ -+ -+/* -+========================================================================== -+IO Module Structures -+========================================================================== -+*/ -+ -+ -+/* -+-------------------------------------------------------------------------- -+VPORT - Virtual Ports -+-------------------------------------------------------------------------- -+*/ -+ -+/* Virtual Port */ -+typedef struct VPORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t IN; /* I/O Port Input */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+} VPORT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XOCD - On-Chip Debug System -+-------------------------------------------------------------------------- -+*/ -+ -+/* On-Chip Debug System */ -+typedef struct OCD_struct -+{ -+ register8_t OCDR0; /* OCD Register 0 */ -+ register8_t OCDR1; /* OCD Register 1 */ -+} OCD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CPU - CPU -+-------------------------------------------------------------------------- -+*/ -+ -+/* CCP signatures */ -+typedef enum CCP_enum -+{ -+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ -+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ -+} CCP_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CLK - Clock System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Clock System */ -+typedef struct CLK_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t PSCTRL; /* Prescaler Control Register */ -+ register8_t LOCK; /* Lock register */ -+ register8_t RTCCTRL; /* RTC Control Register */ -+ register8_t reserved_0x04; -+} CLK_t; -+ -+ -+/* Power Reduction */ -+typedef struct PR_struct -+{ -+ register8_t PRGEN; /* General Power Reduction */ -+ register8_t PRPA; /* Power Reduction Port A */ -+ register8_t reserved_0x02; -+ register8_t PRPC; /* Power Reduction Port C */ -+ register8_t PRPD; /* Power Reduction Port D */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+} PR_t; -+ -+/* System Clock Selection */ -+typedef enum CLK_SCLKSEL_enum -+{ -+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ -+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ -+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ -+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ -+ CLK_SCLKSEL_RC8M_gc = (0x05<<0), /* Internal 8 MHz RC Oscillator */ -+} CLK_SCLKSEL_t; -+ -+/* Prescaler A Division Factor */ -+typedef enum CLK_PSADIV_enum -+{ -+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ -+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ -+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ -+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ -+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ -+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ -+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ -+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ -+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ -+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ -+ CLK_PSADIV_6_gc = (0x13<<2), /* Divide by 6 */ -+ CLK_PSADIV_10_gc = (0x15<<2), /* Divide by 10 */ -+ CLK_PSADIV_12_gc = (0x17<<2), /* Divide by 12 */ -+ CLK_PSADIV_24_gc = (0x19<<2), /* Divide by 24 */ -+ CLK_PSADIV_48_gc = (0x1B<<2), /* Divide by 48 */ -+} CLK_PSADIV_t; -+ -+/* Prescaler B and C Division Factor */ -+typedef enum CLK_PSBCDIV_enum -+{ -+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ -+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ -+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ -+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ -+} CLK_PSBCDIV_t; -+ -+/* RTC Clock Source */ -+typedef enum CLK_RTCSRC_enum -+{ -+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ -+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ -+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ -+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ -+} CLK_RTCSRC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SLEEP - Sleep Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Sleep Controller */ -+typedef struct SLEEP_struct -+{ -+ register8_t CTRL; /* Control Register */ -+} SLEEP_t; -+ -+/* Sleep Mode */ -+typedef enum SLEEP_SMODE_enum -+{ -+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ -+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ -+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ -+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ -+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ -+} SLEEP_SMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+OSC - Oscillator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Oscillator */ -+typedef struct OSC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t XOSCCTRL; /* External Oscillator Control Register */ -+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ -+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ -+ register8_t PLLCTRL; /* PLL Control Register */ -+ register8_t DFLLCTRL; /* DFLL Control Register */ -+ register8_t RC8MCAL; /* Internal 8 MHz RC Oscillator Calibration Register */ -+} OSC_t; -+ -+/* Oscillator Frequency Range */ -+typedef enum OSC_FRQRANGE_enum -+{ -+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ -+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ -+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ -+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ -+} OSC_FRQRANGE_t; -+ -+/* External Oscillator Selection and Startup Time */ -+typedef enum OSC_XOSCSEL_enum -+{ -+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ -+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ -+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ -+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ -+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ -+ OSC_XOSCSEL_EXTCLK_C4_gc = (0x14<<0), /* External Clock on port C4 - 6 CLK */ -+} OSC_XOSCSEL_t; -+ -+/* PLL Clock Source */ -+typedef enum OSC_PLLSRC_enum -+{ -+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ -+ OSC_PLLSRC_RC8M_gc = (0x01<<6), /* Internal 8 MHz RC Oscillator */ -+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ -+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ -+} OSC_PLLSRC_t; -+ -+/* 32 MHz DFLL Calibration Reference */ -+typedef enum OSC_RC32MCREF_enum -+{ -+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ -+ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ -+} OSC_RC32MCREF_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DFLL - DFLL -+-------------------------------------------------------------------------- -+*/ -+ -+/* DFLL */ -+typedef struct DFLL_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x01; -+ register8_t CALA; /* Calibration Register A */ -+ register8_t CALB; /* Calibration Register B */ -+ register8_t COMP0; /* Oscillator Compare Register 0 */ -+ register8_t COMP1; /* Oscillator Compare Register 1 */ -+ register8_t COMP2; /* Oscillator Compare Register 2 */ -+ register8_t reserved_0x07; -+} DFLL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RST - Reset -+-------------------------------------------------------------------------- -+*/ -+ -+/* Reset */ -+typedef struct RST_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRL; /* Control Register */ -+} RST_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WDT - Watch-Dog Timer -+-------------------------------------------------------------------------- -+*/ -+ -+/* Watch-Dog Timer */ -+typedef struct WDT_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t WINCTRL; /* Windowed Mode Control */ -+ register8_t STATUS; /* Status */ -+} WDT_t; -+ -+/* Period setting */ -+typedef enum WDT_PER_enum -+{ -+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_PER_t; -+ -+/* Closed window period */ -+typedef enum WDT_WPER_enum -+{ -+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ -+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ -+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ -+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ -+ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ -+ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ -+ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ -+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ -+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ -+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ -+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ -+} WDT_WPER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+MCU - MCU Control -+-------------------------------------------------------------------------- -+*/ -+ -+/* MCU Control */ -+typedef struct MCU_struct -+{ -+ register8_t DEVID0; /* Device ID byte 0 */ -+ register8_t DEVID1; /* Device ID byte 1 */ -+ register8_t DEVID2; /* Device ID byte 2 */ -+ register8_t REVID; /* Revision ID */ -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t ANAINIT; /* Analog Startup Delay */ -+ register8_t EVSYSLOCK; /* Event System Lock */ -+ register8_t WEXLOCK; /* WEX Lock */ -+ register8_t FAULTLOCK; /* FAULT Lock */ -+ register8_t reserved_0x0B; -+} MCU_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PMIC - Programmable Multi-level Interrupt Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Programmable Multi-level Interrupt Controller */ -+typedef struct PMIC_struct -+{ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTPRI; /* Interrupt Priority */ -+ register8_t CTRL; /* Control Register */ -+ register8_t reserved_0x03; -+ register8_t reserved_0x04; -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} PMIC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORTCFG - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O port Configuration */ -+typedef struct PORTCFG_struct -+{ -+ register8_t MPCMASK; /* Multi-pin Configuration Mask */ -+ register8_t reserved_0x01; -+ register8_t reserved_0x02; -+ register8_t reserved_0x03; -+ register8_t CLKOUT; /* Clock Out Register */ -+ register8_t reserved_0x05; -+ register8_t ACEVOUT; /* Analog Comparator and Event Out Register */ -+ register8_t SRLCTRL; /* Slew Rate Limit Control Register */ -+} PORTCFG_t; -+ -+/* Clock and Event Output Port */ -+typedef enum PORTCFG_CLKEVPIN_enum -+{ -+ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ -+ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ -+} PORTCFG_CLKEVPIN_t; -+ -+/* RTC Clock Output Port */ -+typedef enum PORTCFG_RTCCLKOUT_enum -+{ -+ PORTCFG_RTCCLKOUT_OFF_gc = (0x00<<5), /* System Clock Output Disabled */ -+ PORTCFG_RTCCLKOUT_PC6_gc = (0x01<<5), /* System Clock Output on Port C pin 6 */ -+ PORTCFG_RTCCLKOUT_PD6_gc = (0x02<<5), /* System Clock Output on Port D pin 6 */ -+ PORTCFG_RTCCLKOUT_PR0_gc = (0x03<<5), /* System Clock Output on Port R pin 0 */ -+} PORTCFG_RTCCLKOUT_t; -+ -+/* Peripheral Clock Output Select */ -+typedef enum PORTCFG_CLKOUTSEL_enum -+{ -+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ -+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ -+} PORTCFG_CLKOUTSEL_t; -+ -+/* System Clock Output Port */ -+typedef enum PORTCFG_CLKOUT_enum -+{ -+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ -+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ -+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ -+ PORTCFG_CLKOUT_PR0_gc = (0x03<<0), /* System Clock Output on Port R pin 0 */ -+} PORTCFG_CLKOUT_t; -+ -+/* Analog Comparator Output Port */ -+typedef enum PORTCFG_ACOUT_enum -+{ -+ PORTCFG_ACOUT_PA_gc = (0x00<<6), /* Analog Comparator Outputs on Port A, Pin 6-7 */ -+ PORTCFG_ACOUT_PC_gc = (0x01<<6), /* Analog Comparator Outputs on Port C, Pin 6-7 */ -+ PORTCFG_ACOUT_PD_gc = (0x02<<6), /* Analog Comparator Outputs on Port D, Pin 6-7 */ -+ PORTCFG_ACOUT_PR_gc = (0x03<<6), /* Analog Comparator Outputs on Port R, Pin 0-1 */ -+} PORTCFG_ACOUT_t; -+ -+/* Event Output Port */ -+typedef enum PORTCFG_EVOUT_enum -+{ -+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ -+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel n Output on Port C pin 7 */ -+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel n Output on Port D pin 7 */ -+ PORTCFG_EVOUT_PR0_gc = (0x03<<4), /* Event Channel n Output on Port R pin 0 */ -+} PORTCFG_EVOUT_t; -+ -+/* Event Output Select */ -+typedef enum PORTCFG_EVOUTSEL_enum -+{ -+ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ -+ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ -+ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ -+ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ -+ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ -+ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ -+ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ -+ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ -+} PORTCFG_EVOUTSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+CRC - Cyclic Redundancy Checker -+-------------------------------------------------------------------------- -+*/ -+ -+/* Cyclic Redundancy Checker */ -+typedef struct CRC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t reserved_0x02; -+ register8_t DATAIN; /* Data Input */ -+ register8_t CHECKSUM0; /* Checksum byte 0 */ -+ register8_t CHECKSUM1; /* Checksum byte 1 */ -+ register8_t CHECKSUM2; /* Checksum byte 2 */ -+ register8_t CHECKSUM3; /* Checksum byte 3 */ -+} CRC_t; -+ -+/* Reset */ -+typedef enum CRC_RESET_enum -+{ -+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ -+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ -+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ -+} CRC_RESET_t; -+ -+/* Input Source */ -+typedef enum CRC_SOURCE_enum -+{ -+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ -+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ -+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ -+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ -+ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ -+ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ -+ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ -+} CRC_SOURCE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EDMA - Enhanced DMA Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* EDMA Channel */ -+typedef struct EDMA_CH_struct -+{ -+ register8_t CTRLA; /* Channel Control A */ -+ register8_t CTRLB; /* Channel Control */ -+ register8_t ADDRCTRL; /* Memory Address Control for Peripheral Ch., or Source Address Control for Standard Ch. */ -+ register8_t DESTADDRCTRL; /* Destination Address Control for Standard Channels Only. */ -+ register8_t TRIGSRC; /* Channel Trigger Source */ -+ register8_t reserved_0x05; -+ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch. */ -+ _WORDREGISTER(ADDR); /* Channel Memory Address for Peripheral Ch., or Channel Source Address Low for Standard Ch. */ -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(DESTADDR); /* Channel Destination Address for Standard Channels Only. */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} EDMA_CH_t; -+ -+ -+/* Enhanced DMA Controller */ -+typedef struct EDMA_struct -+{ -+ register8_t CTRL; /* Control */ -+ register8_t reserved_0x01; -+ register8_t reserved_0x02; -+ register8_t INTFLAGS; /* Transfer Interrupt Status */ -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x05; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ EDMA_CH_t CH0; /* EDMA Channel 0 */ -+ EDMA_CH_t CH1; /* EDMA Channel 1 */ -+ EDMA_CH_t CH2; /* EDMA Channel 2 */ -+ EDMA_CH_t CH3; /* EDMA Channel 3 */ -+} EDMA_t; -+ -+/* Channel mode */ -+typedef enum EDMA_CHMODE_enum -+{ -+ EDMA_CHMODE_PER0123_gc = (0x00<<4), /* Channels 0, 1, 2 and 3 in peripheal conf. */ -+ EDMA_CHMODE_STD0_gc = (0x01<<4), /* Channel 0 in standard conf.; channels 2 and 3 in peripheral conf. */ -+ EDMA_CHMODE_STD2_gc = (0x02<<4), /* Channel 2 in standard conf.; channels 0 and 1 in peripheral conf. */ -+ EDMA_CHMODE_STD02_gc = (0x03<<4), /* Channels 0 and 2 in standard conf. */ -+} EDMA_CHMODE_t; -+ -+/* Double buffer mode */ -+typedef enum EDMA_DBUFMODE_enum -+{ -+ EDMA_DBUFMODE_DISABLE_gc = (0x00<<2), /* No double buffer enabled */ -+ EDMA_DBUFMODE_BUF01_gc = (0x01<<2), /* Double buffer enabled on peripheral channels 0/1 (if exist) */ -+ EDMA_DBUFMODE_BUF23_gc = (0x02<<2), /* Double buffer enabled on peripheral channels 2/3 (if exist) */ -+ EDMA_DBUFMODE_BUF0123_gc = (0x03<<2), /* Double buffer enabled on peripheral channels 0/1 and 2/3 or standard channels 0/2 */ -+} EDMA_DBUFMODE_t; -+ -+/* Priority mode */ -+typedef enum EDMA_PRIMODE_enum -+{ -+ EDMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round robin on all channels */ -+ EDMA_PRIMODE_RR123_gc = (0x01<<0), /* Ch0 > round robin (Ch 1 ch2 Ch3) */ -+ EDMA_PRIMODE_RR23_gc = (0x02<<0), /* Ch0 > Ch 1 > round robin (Ch2 Ch3) */ -+ EDMA_PRIMODE_CH0123_gc = (0x03<<0), /* Ch0 > Ch1 > Ch2 > Ch3 */ -+} EDMA_PRIMODE_t; -+ -+/* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. */ -+typedef enum EDMA_CH_RELOAD_enum -+{ -+ EDMA_CH_RELOAD_NONE_gc = (0x00<<4), /* No reload */ -+ EDMA_CH_RELOAD_BLOCK_gc = (0x01<<4), /* Reload at end of each block transfer */ -+ EDMA_CH_RELOAD_BURST_gc = (0x02<<4), /* Reload at end of each burst transfer */ -+ EDMA_CH_RELOAD_TRANSACTION_gc = (0x03<<4), /* Reload at end of each transaction */ -+} EDMA_CH_RELOAD_t; -+ -+/* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. */ -+typedef enum EDMA_CH_DIR_enum -+{ -+ EDMA_CH_DIR_FIXED_gc = (0x00<<0), /* Fixed */ -+ EDMA_CH_DIR_INC_gc = (0x01<<0), /* Increment */ -+ EDMA_CH_DIR_MP1_gc = (0x04<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'mask-match' (data: ADDRL, mask: ADDRH), else reserved conf. */ -+ EDMA_CH_DIR_MP2_gc = (0x05<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH), else reserved conf. */ -+ EDMA_CH_DIR_MP3_gc = (0x06<<0), /* If Peripheral Ch. (Per ==> Mem), 2-byte 'match' (data-1: ADDRL followed by data-2: ADDRH), else reserved conf. */ -+} EDMA_CH_DIR_t; -+ -+/* Destination addressing mode */ -+typedef enum EDMA_CH_DESTDIR_enum -+{ -+ EDMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ -+ EDMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ -+ EDMA_CH_DESTDIR_MP1_gc = (0x04<<0), /* 1-byte 'mask-match' (data: ADDRL, mask: ADDRH) */ -+ EDMA_CH_DESTDIR_MP2_gc = (0x05<<0), /* 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH) */ -+ EDMA_CH_DESTDIR_MP3_gc = (0x06<<0), /* 2-byte 'match' (data1: ADDRL followed by data2: ADDRH) */ -+} EDMA_CH_DESTDIR_t; -+ -+/* Transfer trigger source */ -+typedef enum EDMA_CH_TRIGSRC_enum -+{ -+ EDMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Software triggers only */ -+ EDMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event CH0 as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event CH1 as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event CH2 as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA CH0 as trigger */ -+ EDMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA CH0 as trigger */ -+ EDMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA CH1 as trigger */ -+ EDMA_CH_TRIGSRC_TCC4_OVF_gc = (0x40<<0), /* TCC4 overflow/underflow as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCC4_ERR_gc = (0x41<<0), /* TCC4 error as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCC4_CCA_gc = (0x42<<0), /* TCC4 compare or capture channel A as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCC4_CCB_gc = (0x43<<0), /* TCC4 compare or capture channel B as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCC4_CCC_gc = (0x44<<0), /* TCC4 compare or capture channel C as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCC4_CCD_gc = (0x45<<0), /* TCC4 compare or capture channel D as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCC5_OVF_gc = (0x46<<0), /* TCC5 overflow/underflow as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCC5_ERR_gc = (0x47<<0), /* TCC5 error as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCC5_CCA_gc = (0x48<<0), /* TCC5 compare or capture channel A as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCC5_CCB_gc = (0x49<<0), /* TCC5 compare or capture channel B as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_SPIC_RXC_gc = (0x4A<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C receive complete as trigger (SPI Buffer Modes) */ -+ EDMA_CH_TRIGSRC_SPIC_DRE_gc = (0x4B<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C data register empty as trigger (SPI Buffer modes) */ -+ EDMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4C<<0), /* USART C0 receive complete as trigger */ -+ EDMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4D<<0), /* USART C0 data register empty as trigger */ -+ EDMA_CH_TRIGSRC_TCD5_OVF_gc = (0x66<<0), /* TCD5 overflow/underflow as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCD5_ERR_gc = (0x67<<0), /* TCD5 error as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCD5_CCA_gc = (0x68<<0), /* TCD5 compare or capture channel A as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_TCD5_CCB_gc = (0x69<<0), /* TCD5 compare or capture channel B as trigger (Standard Channels Only) */ -+ EDMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6C<<0), /* USART D0 receive complete as trigger */ -+ EDMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6D<<0), /* USART D0 data register empty as trigger */ -+} EDMA_CH_TRIGSRC_t; -+ -+/* Interrupt level */ -+typedef enum EDMA_CH_INTLVL_enum -+{ -+ EDMA_CH_INTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ EDMA_CH_INTLVL_LO_gc = (0x01<<2), /* Low level */ -+ EDMA_CH_INTLVL_MED_gc = (0x02<<2), /* Medium level */ -+ EDMA_CH_INTLVL_HI_gc = (0x03<<2), /* High level */ -+} EDMA_CH_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+EVSYS - Event System -+-------------------------------------------------------------------------- -+*/ -+ -+/* Event System */ -+typedef struct EVSYS_struct -+{ -+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ -+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ -+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ -+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ -+ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ -+ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ -+ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ -+ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ -+ register8_t CH0CTRL; /* Channel 0 Control Register */ -+ register8_t CH1CTRL; /* Channel 1 Control Register */ -+ register8_t CH2CTRL; /* Channel 2 Control Register */ -+ register8_t CH3CTRL; /* Channel 3 Control Register */ -+ register8_t CH4CTRL; /* Channel 4 Control Register */ -+ register8_t CH5CTRL; /* Channel 5 Control Register */ -+ register8_t CH6CTRL; /* Channel 6 Control Register */ -+ register8_t CH7CTRL; /* Channel 7 Control Register */ -+ register8_t STROBE; /* Event Strobe */ -+ register8_t DATA; /* Event Data */ -+ register8_t DFCTRL; /* Digital Filter Control Register */ -+} EVSYS_t; -+ -+/* Event Channel multiplexer input selection */ -+typedef enum EVSYS_CHMUX_enum -+{ -+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ -+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ -+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ -+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ -+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ -+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ -+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ -+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ -+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ -+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ -+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ -+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ -+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ -+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ -+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ -+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ -+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ -+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ -+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ -+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ -+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ -+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ -+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ -+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ -+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ -+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ -+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ -+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ -+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ -+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ -+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ -+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ -+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ -+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ -+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ -+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ -+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ -+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ -+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ -+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ -+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ -+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ -+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ -+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ -+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ -+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ -+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ -+ EVSYS_CHMUX_XCL_UNF0_gc = (0xB0<<0), /* XCL BTC0 underflow */ -+ EVSYS_CHMUX_XCL_UNF1_gc = (0xB1<<0), /* XCL BTC1 underflow */ -+ EVSYS_CHMUX_XCL_CC0_gc = (0xB2<<0), /* XCL BTC0 capture or compare */ -+ EVSYS_CHMUX_XCL_CC1_gc = (0xB3<<0), /* XCL BTC0 capture or compare */ -+ EVSYS_CHMUX_XCL_PEC0_gc = (0xB4<<0), /* XCL PEC0 restart */ -+ EVSYS_CHMUX_XCL_PEC1_gc = (0xB5<<0), /* XCL PEC1 restart */ -+ EVSYS_CHMUX_XCL_LUT0_gc = (0xB6<<0), /* XCL LUT0 output */ -+ EVSYS_CHMUX_XCL_LUT1_gc = (0xB7<<0), /* XCL LUT1 output */ -+ EVSYS_CHMUX_TCC4_OVF_gc = (0xC0<<0), /* Timer/Counter C4 Overflow */ -+ EVSYS_CHMUX_TCC4_ERR_gc = (0xC1<<0), /* Timer/Counter C4 Error */ -+ EVSYS_CHMUX_TCC4_CCA_gc = (0xC4<<0), /* Timer/Counter C4 Compare or Capture A */ -+ EVSYS_CHMUX_TCC4_CCB_gc = (0xC5<<0), /* Timer/Counter C4 Compare or Capture B */ -+ EVSYS_CHMUX_TCC4_CCC_gc = (0xC6<<0), /* Timer/Counter C4 Compare or Capture C */ -+ EVSYS_CHMUX_TCC4_CCD_gc = (0xC7<<0), /* Timer/Counter C4 Compare or Capture D */ -+ EVSYS_CHMUX_TCC5_OVF_gc = (0xC8<<0), /* Timer/Counter C5 Overflow */ -+ EVSYS_CHMUX_TCC5_ERR_gc = (0xC9<<0), /* Timer/Counter C5 Error */ -+ EVSYS_CHMUX_TCC5_CCA_gc = (0xCC<<0), /* Timer/Counter C5 Compare or Capture A */ -+ EVSYS_CHMUX_TCC5_CCB_gc = (0xCD<<0), /* Timer/Counter C5 Compare or Capture B */ -+ EVSYS_CHMUX_TCD5_OVF_gc = (0xD8<<0), /* Timer/Counter D5 Overflow */ -+ EVSYS_CHMUX_TCD5_ERR_gc = (0xD9<<0), /* Timer/Counter D5 Error */ -+ EVSYS_CHMUX_TCD5_CCA_gc = (0xDC<<0), /* Timer/Counter D5 Compare or Capture A */ -+ EVSYS_CHMUX_TCD5_CCB_gc = (0xDD<<0), /* Timer/Counter D5 Compare or Capture B */ -+} EVSYS_CHMUX_t; -+ -+/* Quadrature Decoder Index Recognition Mode */ -+typedef enum EVSYS_QDIRM_enum -+{ -+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ -+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ -+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ -+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ -+} EVSYS_QDIRM_t; -+ -+/* Digital filter coefficient */ -+typedef enum EVSYS_DIGFILT_enum -+{ -+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ -+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ -+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ -+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ -+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ -+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ -+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ -+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ -+} EVSYS_DIGFILT_t; -+ -+/* Prescaler Filter */ -+typedef enum EVSYS_PRESCFILT_enum -+{ -+ EVSYS_PRESCFILT_CH04_gc = (0x01<<4), /* Enable prescaler filter for either channel 0 or 4 */ -+ EVSYS_PRESCFILT_CH15_gc = (0x02<<4), /* Enable prescaler filter for either channel 1 or 5 */ -+ EVSYS_PRESCFILT_CH26_gc = (0x04<<4), /* Enable prescaler filter for either channel 2 or 6 */ -+ EVSYS_PRESCFILT_CH37_gc = (0x08<<4), /* Enable prescaler filter for either channel 3 or 7 */ -+} EVSYS_PRESCFILT_t; -+ -+/* Prescaler */ -+typedef enum EVSYS_PRESCALER_enum -+{ -+ EVSYS_PRESCALER_CLKPER_8_gc = (0x00<<0), /* CLKPER, divide by 8 */ -+ EVSYS_PRESCALER_CLKPER_64_gc = (0x01<<0), /* CLKPER, divide by 64 */ -+ EVSYS_PRESCALER_CLKPER_512_gc = (0x02<<0), /* CLKPER, divide by 512 */ -+ EVSYS_PRESCALER_CLKPER_4096_gc = (0x03<<0), /* CLKPER, divide by 4096 */ -+ EVSYS_PRESCALER_CLKPER_32768_gc = (0x04<<0), /* CLKPER, divide by 32768 */ -+} EVSYS_PRESCALER_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+NVM - Non Volatile Memory Controller -+-------------------------------------------------------------------------- -+*/ -+ -+/* Non-volatile Memory Controller */ -+typedef struct NVM_struct -+{ -+ register8_t ADDR0; /* Address Register 0 */ -+ register8_t ADDR1; /* Address Register 1 */ -+ register8_t ADDR2; /* Address Register 2 */ -+ register8_t reserved_0x03; -+ register8_t DATA0; /* Data Register 0 */ -+ register8_t DATA1; /* Data Register 1 */ -+ register8_t DATA2; /* Data Register 2 */ -+ register8_t reserved_0x07; -+ register8_t reserved_0x08; -+ register8_t reserved_0x09; -+ register8_t CMD; /* Command */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t INTCTRL; /* Interrupt Control */ -+ register8_t reserved_0x0E; -+ register8_t STATUS; /* Status */ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_t; -+ -+/* NVM Command */ -+typedef enum NVM_CMD_enum -+{ -+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ -+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ -+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ -+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ -+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ -+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ -+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ -+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ -+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ -+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ -+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ -+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ -+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ -+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ -+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ -+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ -+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ -+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ -+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ -+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ -+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ -+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ -+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ -+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ -+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ -+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ -+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ -+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ -+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ -+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ -+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ -+ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ -+} NVM_CMD_t; -+ -+/* SPM ready interrupt level */ -+typedef enum NVM_SPMLVL_enum -+{ -+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ -+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ -+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ -+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ -+} NVM_SPMLVL_t; -+ -+/* EEPROM ready interrupt level */ -+typedef enum NVM_EELVL_enum -+{ -+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ -+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ -+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ -+} NVM_EELVL_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum NVM_BLBB_enum -+{ -+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} NVM_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum NVM_BLBA_enum -+{ -+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} NVM_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum NVM_BLBAT_enum -+{ -+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} NVM_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum NVM_LB_enum -+{ -+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} NVM_LB_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+ADC - Analog/Digital Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* ADC Channel */ -+typedef struct ADC_CH_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t MUXCTRL; /* MUX Control */ -+ register8_t INTCTRL; /* Channel Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ _WORDREGISTER(RES); /* Channel Result */ -+ register8_t SCAN; /* Input Channel Scan */ -+ register8_t CORRCTRL; /* Correction Control Register */ -+ register8_t OFFSETCORR0; /* Offset Correction Register 0 */ -+ register8_t OFFSETCORR1; /* Offset Correction Register 1 */ -+ register8_t GAINCORR0; /* Gain Correction Register 0 */ -+ register8_t GAINCORR1; /* Gain Correction Register 1 */ -+ register8_t AVGCTRL; /* Average Control Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+} ADC_CH_t; -+ -+ -+/* Analog-to-Digital Converter */ -+typedef struct ADC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t REFCTRL; /* Reference Control */ -+ register8_t EVCTRL; /* Event Control */ -+ register8_t PRESCALER; /* Clock Prescaler */ -+ register8_t reserved_0x05; -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary Register */ -+ register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ -+ register8_t reserved_0x09; -+ register8_t reserved_0x0A; -+ register8_t reserved_0x0B; -+ _WORDREGISTER(CAL); /* Calibration Value */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ _WORDREGISTER(CH0RES); /* Channel 0 Result */ -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CMP); /* Compare Value */ -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ ADC_CH_t CH0; /* ADC Channel 0 */ -+} ADC_t; -+ -+/* Current Limitation */ -+typedef enum ADC_CURRLIMIT_enum -+{ -+ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ -+ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ -+ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ -+ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ -+} ADC_CURRLIMIT_t; -+ -+/* Conversion result resolution */ -+typedef enum ADC_RESOLUTION_enum -+{ -+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ -+ ADC_RESOLUTION_MT12BIT_gc = (0x01<<1), /* More than 12-bit (oversapling) right-adjusted result */ -+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ -+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ -+} ADC_RESOLUTION_t; -+ -+/* Voltage reference selection */ -+typedef enum ADC_REFSEL_enum -+{ -+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ -+ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ -+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ -+ ADC_REFSEL_AREFD_gc = (0x03<<4), /* External reference on PORT D */ -+ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ -+} ADC_REFSEL_t; -+ -+/* Event channel input selection */ -+typedef enum ADC_EVSEL_enum -+{ -+ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ -+ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ -+ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ -+ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ -+ ADC_EVSEL_4_gc = (0x04<<3), /* Event Channel 4 */ -+ ADC_EVSEL_5_gc = (0x05<<3), /* Event Channel 5 */ -+ ADC_EVSEL_6_gc = (0x06<<3), /* Event Channel 6 */ -+ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ -+} ADC_EVSEL_t; -+ -+/* Event action selection */ -+typedef enum ADC_EVACT_enum -+{ -+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ -+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel conversion */ -+ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ -+} ADC_EVACT_t; -+ -+/* Clock prescaler */ -+typedef enum ADC_PRESCALER_enum -+{ -+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ -+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ -+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ -+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ -+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ -+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ -+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ -+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ -+} ADC_PRESCALER_t; -+ -+/* Gain factor */ -+typedef enum ADC_CH_GAIN_enum -+{ -+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ -+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ -+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ -+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ -+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ -+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ -+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ -+ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ -+} ADC_CH_GAIN_t; -+ -+/* Input mode */ -+typedef enum ADC_CH_INPUTMODE_enum -+{ -+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ -+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ -+ ADC_CH_INPUTMODE_DIFFWGAINL_gc = (0x02<<0), /* Differential input, gain with 4 LSB pins selection */ -+ ADC_CH_INPUTMODE_DIFFWGAINH_gc = (0x03<<0), /* Differential input, gain with 4 MSB pins selection */ -+} ADC_CH_INPUTMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum ADC_CH_MUXPOS_enum -+{ -+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ -+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ -+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ -+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ -+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ -+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ -+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ -+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ -+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ -+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ -+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ -+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ -+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ -+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ -+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ -+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ -+} ADC_CH_MUXPOS_t; -+ -+/* Internal input multiplexer selections */ -+typedef enum ADC_CH_MUXINT_enum -+{ -+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ -+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ -+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 Scaled VCC */ -+ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC Output */ -+} ADC_CH_MUXINT_t; -+ -+/* Negative input multiplexer selection when gain on 4 LSB pins */ -+typedef enum ADC_CH_MUXNEGL_enum -+{ -+ ADC_CH_MUXNEGL_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+ ADC_CH_MUXNEGL_PIN1_gc = (0x01<<0), /* Input pin 1 */ -+ ADC_CH_MUXNEGL_PIN2_gc = (0x02<<0), /* Input pin 2 */ -+ ADC_CH_MUXNEGL_PIN3_gc = (0x03<<0), /* Input pin 3 */ -+ ADC_CH_MUXNEGL_GND_gc = (0x05<<0), /* PAD ground */ -+ ADC_CH_MUXNEGL_INTGND_gc = (0x07<<0), /* Internal ground */ -+} ADC_CH_MUXNEGL_t; -+ -+/* Negative input multiplexer selection when gain on 4 MSB pins */ -+typedef enum ADC_CH_MUXNEGH_enum -+{ -+ ADC_CH_MUXNEGH_PIN4_gc = (0x00<<0), /* Input pin 4 */ -+ ADC_CH_MUXNEGH_PIN5_gc = (0x01<<0), /* Input pin 5 */ -+ ADC_CH_MUXNEGH_PIN6_gc = (0x02<<0), /* Input pin 6 */ -+ ADC_CH_MUXNEGH_PIN7_gc = (0x03<<0), /* Input pin 7 */ -+ ADC_CH_MUXNEGH_GND_gc = (0x05<<0), /* PAD ground */ -+} ADC_CH_MUXNEGH_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum ADC_CH_MUXNEG_enum -+{ -+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ -+} ADC_CH_MUXNEG_t; -+ -+/* Interupt mode */ -+typedef enum ADC_CH_INTMODE_enum -+{ -+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ -+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ -+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ -+} ADC_CH_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum ADC_CH_INTLVL_enum -+{ -+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ -+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ -+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ -+} ADC_CH_INTLVL_t; -+ -+/* Averaged Number of Samples */ -+typedef enum ADC_SAMPNUM_enum -+{ -+ ADC_SAMPNUM_1X_gc = (0x00<<0), /* 1 Sample */ -+ ADC_SAMPNUM_2X_gc = (0x01<<0), /* 2 Samples */ -+ ADC_SAMPNUM_4X_gc = (0x02<<0), /* 4 Samples */ -+ ADC_SAMPNUM_8X_gc = (0x03<<0), /* 8 Samples */ -+ ADC_SAMPNUM_16X_gc = (0x04<<0), /* 16 Samples */ -+ ADC_SAMPNUM_32X_gc = (0x05<<0), /* 32 Samples */ -+ ADC_SAMPNUM_64X_gc = (0x06<<0), /* 64 Samples */ -+ ADC_SAMPNUM_128X_gc = (0x07<<0), /* 128 Samples */ -+ ADC_SAMPNUM_256X_gc = (0x08<<0), /* 256 Samples */ -+ ADC_SAMPNUM_512X_gc = (0x09<<0), /* 512 Samples */ -+ ADC_SAMPNUM_1024X_gc = (0x0A<<0), /* 1024 Samples */ -+} ADC_SAMPNUM_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+DAC - Digital/Analog Converter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Digital-to-Analog Converter */ -+typedef struct DAC_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t EVCTRL; /* Event Input Control */ -+ register8_t reserved_0x04; -+ register8_t STATUS; /* Status */ -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t CH0GAINCAL; /* Gain Calibration */ -+ register8_t CH0OFFSETCAL; /* Offset Calibration */ -+ register8_t CH1GAINCAL; /* Gain Calibration */ -+ register8_t CH1OFFSETCAL; /* Offset Calibration */ -+ register8_t reserved_0x0C; -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ -+ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ -+} DAC_t; -+ -+/* Output channel selection */ -+typedef enum DAC_CHSEL_enum -+{ -+ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ -+ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ -+ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ -+} DAC_CHSEL_t; -+ -+/* Reference voltage selection */ -+typedef enum DAC_REFSEL_enum -+{ -+ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ -+ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ -+ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ -+ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ -+} DAC_REFSEL_t; -+ -+/* Event channel selection */ -+typedef enum DAC_EVSEL_enum -+{ -+ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ -+ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ -+ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ -+ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ -+ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ -+ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ -+ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ -+ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ -+} DAC_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+AC - Analog Comparator -+-------------------------------------------------------------------------- -+*/ -+ -+/* Analog Comparator */ -+typedef struct AC_struct -+{ -+ register8_t AC0CTRL; /* Analog Comparator 0 Control */ -+ register8_t AC1CTRL; /* Analog Comparator 1 Control */ -+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ -+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t WINCTRL; /* Window Mode Control */ -+ register8_t STATUS; /* Status */ -+ register8_t CURRCTRL; /* Current Source Control Register */ -+ register8_t CURRCALIB; /* Current Source Calibration Register */ -+} AC_t; -+ -+/* Interrupt mode */ -+typedef enum AC_INTMODE_enum -+{ -+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ -+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ -+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ -+} AC_INTMODE_t; -+ -+/* Interrupt level */ -+typedef enum AC_INTLVL_enum -+{ -+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ -+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ -+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ -+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ -+} AC_INTLVL_t; -+ -+/* Hysteresis mode selection */ -+typedef enum AC_HYSMODE_enum -+{ -+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ -+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ -+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ -+} AC_HYSMODE_t; -+ -+/* Positive input multiplexer selection */ -+typedef enum AC_MUXPOS_enum -+{ -+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ -+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ -+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ -+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ -+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ -+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ -+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ -+ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ -+} AC_MUXPOS_t; -+ -+/* Negative input multiplexer selection */ -+typedef enum AC_MUXNEG_enum -+{ -+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ -+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ -+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ -+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ -+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ -+ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ -+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ -+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ -+} AC_MUXNEG_t; -+ -+/* Windows interrupt mode */ -+typedef enum AC_WINTMODE_enum -+{ -+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ -+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ -+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ -+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ -+} AC_WINTMODE_t; -+ -+/* Window interrupt level */ -+typedef enum AC_WINTLVL_enum -+{ -+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ -+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ -+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ -+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ -+} AC_WINTLVL_t; -+ -+/* Window mode state */ -+typedef enum AC_WSTATE_enum -+{ -+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ -+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ -+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ -+} AC_WSTATE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+RTC - Real-Time Clounter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Real-Time Counter */ -+typedef struct RTC_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flags */ -+ register8_t TEMP; /* Temporary register */ -+ register8_t reserved_0x05; -+ register8_t CALIB; /* Calibration Register */ -+ register8_t reserved_0x07; -+ _WORDREGISTER(CNT); /* Count Register */ -+ _WORDREGISTER(PER); /* Period Register */ -+ _WORDREGISTER(COMP); /* Compare Register */ -+} RTC_t; -+ -+/* Prescaler Factor */ -+typedef enum RTC_PRESCALER_enum -+{ -+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ -+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ -+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ -+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ -+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ -+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ -+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ -+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ -+} RTC_PRESCALER_t; -+ -+/* Compare Interrupt level */ -+typedef enum RTC_COMPINTLVL_enum -+{ -+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} RTC_COMPINTLVL_t; -+ -+/* Overflow Interrupt level */ -+typedef enum RTC_OVFINTLVL_enum -+{ -+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} RTC_OVFINTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+XCL - XMEGA Custom Logic -+-------------------------------------------------------------------------- -+*/ -+ -+/* XMEGA Custom Logic */ -+typedef struct XCL_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t CTRLF; /* Control Register F */ -+ register8_t CTRLG; /* Control Register G */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t PLC; /* Peripheral Lenght Control Register */ -+ register8_t CNTL; /* Counter Register Low */ -+ register8_t CNTH; /* Counter Register High */ -+ register8_t CMPL; /* Compare Register Low */ -+ register8_t CMPH; /* Compare Register High */ -+ register8_t PERCAPTL; /* Period or Capture Register Low */ -+ register8_t PERCAPTH; /* Period or Capture Register High */ -+} XCL_t; -+ -+/* LUT0 Output Enable */ -+typedef enum XCL_LUTOUTEN_enum -+{ -+ XCL_LUTOUTEN_DISABLE_gc = (0x00<<6), /* LUT0 output disabled */ -+ XCL_LUTOUTEN_PIN0_gc = (0x01<<6), /* LUT0 Output to pin 0 */ -+ XCL_LUTOUTEN_PIN4_gc = (0x02<<6), /* LUT0 Output to pin 4 */ -+} XCL_LUTOUTEN_t; -+ -+/* Port Selection */ -+typedef enum XCL_PORTSEL_enum -+{ -+ XCL_PORTSEL_PC_gc = (0x00<<4), /* Port C for LUT or USARTC0 for PEC */ -+ XCL_PORTSEL_PD_gc = (0x01<<4), /* Port D for LUT or USARTD0 for PEC */ -+} XCL_PORTSEL_t; -+ -+/* LUT Configuration */ -+typedef enum XCL_LUTCONF_enum -+{ -+ XCL_LUTCONF_2LUT2IN_gc = (0x00<<0), /* 2-Input two LUT */ -+ XCL_LUTCONF_2LUT1IN_gc = (0x01<<0), /* Two LUT with duplicated input */ -+ XCL_LUTCONF_2LUT3IN_gc = (0x02<<0), /* Two LUT with one common input */ -+ XCL_LUTCONF_1LUT3IN_gc = (0x03<<0), /* 3-Input LUT */ -+ XCL_LUTCONF_MUX_gc = (0x04<<0), /* One LUT Mux */ -+ XCL_LUTCONF_DLATCH_gc = (0x05<<0), /* One D-Latch LUT */ -+ XCL_LUTCONF_RSLATCH_gc = (0x06<<0), /* One RS-Latch LUT */ -+ XCL_LUTCONF_DFF_gc = (0x07<<0), /* One DFF LUT */ -+} XCL_LUTCONF_t; -+ -+/* Input Selection */ -+typedef enum XCL_INSEL_enum -+{ -+ XCL_INSEL_EVSYS_gc = (0x00<<6), /* Event system selected as source */ -+ XCL_INSEL_XCL_gc = (0x01<<6), /* XCL selected as source */ -+ XCL_INSEL_PINL_gc = (0x02<<6), /* LSB port pin selected as source */ -+ XCL_INSEL_PINH_gc = (0x03<<6), /* MSB port pin selected as source */ -+} XCL_INSEL_t; -+ -+/* Delay Configuration on LUT */ -+typedef enum XCL_DLYCONF_enum -+{ -+ XCL_DLYCONF_DISABLE_gc = (0x00<<2), /* Delay element disabled */ -+ XCL_DLYCONF_IN_gc = (0x01<<2), /* Delay enabled on LUT input */ -+ XCL_DLYCONF_OUT_gc = (0x02<<2), /* Delay enabled on LUT output */ -+} XCL_DLYCONF_t; -+ -+/* Delay Selection */ -+typedef enum XCL_DLYSEL_enum -+{ -+ XCL_DLYSEL_DLY11_gc = (0x00<<4), /* One cycle delay for each LUT1 and LUT0 */ -+ XCL_DLYSEL_DLY12_gc = (0x01<<4), /* One cycle delay for LUT1 and two cycles for LUT0 */ -+ XCL_DLYSEL_DLY21_gc = (0x02<<4), /* Two cycles delay for LUT1 and one cycle for LUT0 */ -+ XCL_DLYSEL_DLY22_gc = (0x03<<4), /* Two cycle delays for each LUT1 and LUT0 */ -+} XCL_DLYSEL_t; -+ -+/* Clock Selection */ -+typedef enum XCL_CLKSEL_enum -+{ -+ XCL_CLKSEL_OFF_gc = (0x00<<0), /* OFF */ -+ XCL_CLKSEL_DIV1_gc = (0x01<<0), /* Prescaler clk */ -+ XCL_CLKSEL_DIV2_gc = (0x02<<0), /* Prescaler clk/2 */ -+ XCL_CLKSEL_DIV4_gc = (0x03<<0), /* Prescaler clk/4 */ -+ XCL_CLKSEL_DIV8_gc = (0x04<<0), /* Prescaler clk/8 */ -+ XCL_CLKSEL_DIV64_gc = (0x05<<0), /* Prescaler clk/64 */ -+ XCL_CLKSEL_DIV256_gc = (0x06<<0), /* Prescaler clk/256 */ -+ XCL_CLKSEL_DIV1024_gc = (0x07<<0), /* Prescaler clk/1024 */ -+ XCL_CLKSEL_EVCH0_gc = (0x08<<0), /* Event channel 0 */ -+ XCL_CLKSEL_EVCH1_gc = (0x09<<0), /* Event channel 1 */ -+ XCL_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event channel 2 */ -+ XCL_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event channel 3 */ -+ XCL_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event channel 4 */ -+ XCL_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event channel 5 */ -+ XCL_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event channel 6 */ -+ XCL_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event channel 7 */ -+} XCL_CLKSEL_t; -+ -+/* Timer/Counter Command Selection */ -+typedef enum XCL_CMDSEL_enum -+{ -+ XCL_CMDSEL_NONE_gc = (0x00<<7), /* None */ -+ XCL_CMDSEL_RESTART_gc = (0x01<<7), /* Force restart */ -+} XCL_CMDSEL_t; -+ -+/* Timer/Counter Selection */ -+typedef enum XCL_TCSEL_enum -+{ -+ XCL_TCSEL_TC16_gc = (0x00<<4), /* 16-bit timer/counter */ -+ XCL_TCSEL_BTC0_gc = (0x01<<4), /* One 8-bit timer/counter */ -+ XCL_TCSEL_BTC01_gc = (0x02<<4), /* Two 8-bit timer/counters */ -+ XCL_TCSEL_BTC0PEC1_gc = (0x03<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ -+ XCL_TCSEL_PEC0BTC1_gc = (0x04<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ -+ XCL_TCSEL_PEC01_gc = (0x05<<4), /* Two 8-bit peripheral counters */ -+ XCL_TCSEL_BTC0PEC2_gc = (0x06<<4), /* One 8-bit timer/counter and two 4-bit peripheral counters */ -+} XCL_TCSEL_t; -+ -+/* Timer/Counter Mode */ -+typedef enum XCL_TCMODE_enum -+{ -+ XCL_TCMODE_NORMAL_gc = (0x00<<0), /* Normal mode with compare/period */ -+ XCL_TCMODE_CAPT_gc = (0x01<<0), /* Capture mode */ -+ XCL_TCMODE_PWM_gc = (0x02<<0), /* Single Slope PWM */ -+} XCL_TCMODE_t; -+ -+/* Compare Output Value Timer */ -+typedef enum XCL_CMPEN_enum -+{ -+ XCL_CMPEN_CLEAR_gc = (0x00<<5), /* Clear WG Output */ -+ XCL_CMPEN_SET_gc = (0x01<<5), /* Set WG Output */ -+} XCL_CMPEN_t; -+ -+/* Command Enable */ -+typedef enum XCL_CMDEN_enum -+{ -+ XCL_CMDEN_DISABLE_gc = (0x00<<6), /* Command Ignored */ -+ XCL_CMDEN_CMD0_gc = (0x01<<6), /* Command valid for timer/counter 0 */ -+ XCL_CMDEN_CMD1_gc = (0x02<<6), /* Command valid for timer/counter 1 */ -+ XCL_CMDEN_CMD01_gc = (0x03<<6), /* Command valid for both timer/counter 0 and 1 */ -+} XCL_CMDEN_t; -+ -+/* Timer/Counter Event Source Selection */ -+typedef enum XCL_EVSRC_enum -+{ -+ XCL_EVSRC_EVCH0_gc = (0x00<<0), /* Event channel 0 */ -+ XCL_EVSRC_EVCH1_gc = (0x01<<0), /* Event channel 1 */ -+ XCL_EVSRC_EVCH2_gc = (0x02<<0), /* Event channel 2 */ -+ XCL_EVSRC_EVCH3_gc = (0x03<<0), /* Event channel 3 */ -+ XCL_EVSRC_EVCH4_gc = (0x04<<0), /* Event channel 4 */ -+ XCL_EVSRC_EVCH5_gc = (0x05<<0), /* Event channel 5 */ -+ XCL_EVSRC_EVCH6_gc = (0x06<<0), /* Event channel 6 */ -+ XCL_EVSRC_EVCH7_gc = (0x07<<0), /* Event channel 7 */ -+} XCL_EVSRC_t; -+ -+/* Timer/Counter Event Action Selection */ -+typedef enum XCL_EVACT_enum -+{ -+ XCL_EVACT_INPUT_gc = (0x00<<5), /* Input Capture */ -+ XCL_EVACT_FREQ_gc = (0x01<<5), /* Frequency Capture */ -+ XCL_EVACT_PW_gc = (0x02<<5), /* Pulse Width Capture */ -+ XCL_EVACT_RESTART_gc = (0x03<<5), /* Restart timer/counter */ -+} XCL_EVACT_t; -+ -+/* Underflow Interrupt level */ -+typedef enum XCL_UNF_INTLVL_enum -+{ -+ XCL_UNF_INTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ XCL_UNF_INTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ XCL_UNF_INTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ XCL_UNF_INTLVL_HI_gc = (0x03<<2), /* High Level */ -+} XCL_UNF_INTLVL_t; -+ -+/* Compare/Capture Interrupt level */ -+typedef enum XCL_CC_INTLVL_enum -+{ -+ XCL_CC_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ XCL_CC_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ XCL_CC_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ XCL_CC_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} XCL_CC_INTLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TWI - Two-Wire Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* */ -+typedef struct TWI_MASTER_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t STATUS; /* Status Register */ -+ register8_t BAUD; /* Baurd Rate Control Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+} TWI_MASTER_t; -+ -+ -+/* */ -+typedef struct TWI_SLAVE_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t STATUS; /* Status Register */ -+ register8_t ADDR; /* Address Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t ADDRMASK; /* Address Mask Register */ -+} TWI_SLAVE_t; -+ -+ -+/* */ -+typedef struct TWI_TIMEOUT_struct -+{ -+ register8_t TOS; /* Timeout Status Register */ -+ register8_t TOCONF; /* Timeout Configuration Register */ -+} TWI_TIMEOUT_t; -+ -+ -+/* Two-Wire Interface */ -+typedef struct TWI_struct -+{ -+ register8_t CTRL; /* TWI Common Control Register */ -+ TWI_MASTER_t MASTER; /* TWI master module */ -+ TWI_SLAVE_t SLAVE; /* TWI slave module */ -+ TWI_TIMEOUT_t TIMEOUT; /* TWI SMBUS timeout module */ -+} TWI_t; -+ -+/* SDA Hold Time */ -+typedef enum TWI_SDAHOLD_enum -+{ -+ TWI_SDAHOLD_OFF_gc = (0x00<<4), /* SDA Hold Time off */ -+ TWI_SDAHOLD_50NS_gc = (0x01<<4), /* SDA Hold Time 50 ns */ -+ TWI_SDAHOLD_300NS_gc = (0x02<<4), /* SDA Hold Time 300 ns */ -+ TWI_SDAHOLD_400NS_gc = (0x03<<4), /* SDA Hold Time 400 ns */ -+} TWI_SDAHOLD_t; -+ -+/* Master Interrupt Level */ -+typedef enum TWI_MASTER_INTLVL_enum -+{ -+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_MASTER_INTLVL_t; -+ -+/* Inactive Timeout */ -+typedef enum TWI_MASTER_TIMEOUT_enum -+{ -+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ -+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ -+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ -+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ -+} TWI_MASTER_TIMEOUT_t; -+ -+/* Master Command */ -+typedef enum TWI_MASTER_CMD_enum -+{ -+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ -+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ -+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ -+} TWI_MASTER_CMD_t; -+ -+/* Master Bus State */ -+typedef enum TWI_MASTER_BUSSTATE_enum -+{ -+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ -+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ -+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ -+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ -+} TWI_MASTER_BUSSTATE_t; -+ -+/* Slave Interrupt Level */ -+typedef enum TWI_SLAVE_INTLVL_enum -+{ -+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TWI_SLAVE_INTLVL_t; -+ -+/* Slave Command */ -+typedef enum TWI_SLAVE_CMD_enum -+{ -+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ -+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ -+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ -+} TWI_SLAVE_CMD_t; -+ -+/* Master Timeout */ -+typedef enum TWI_MASTER_TTIMEOUT_enum -+{ -+ TWI_MASTER_TTIMEOUT_25MS_gc = (0x00<<0), /* 25 Milliseconds */ -+ TWI_MASTER_TTIMEOUT_24MS_gc = (0x01<<0), /* 24 Milliseconds */ -+ TWI_MASTER_TTIMEOUT_23MS_gc = (0x02<<0), /* 23 Milliseconds */ -+ TWI_MASTER_TTIMEOUT_22MS_gc = (0x03<<0), /* 22 Milliseconds */ -+ TWI_MASTER_TTIMEOUT_26MS_gc = (0x04<<0), /* 26 Milliseconds */ -+ TWI_MASTER_TTIMEOUT_27MS_gc = (0x05<<0), /* 27 Milliseconds */ -+ TWI_MASTER_TTIMEOUT_28MS_gc = (0x06<<0), /* 28 Milliseconds */ -+ TWI_MASTER_TTIMEOUT_29MS_gc = (0x07<<0), /* 29 Milliseconds */ -+} TWI_MASTER_TTIMEOUT_t; -+ -+/* Slave Ttimeout */ -+typedef enum TWI_SLAVE_TTIMEOUT_enum -+{ -+ TWI_SLAVE_TTIMEOUT_25MS_gc = (0x00<<5), /* 25 Milliseconds */ -+ TWI_SLAVE_TTIMEOUT_24MS_gc = (0x01<<5), /* 24 Milliseconds */ -+ TWI_SLAVE_TTIMEOUT_23MS_gc = (0x02<<5), /* 23 Milliseconds */ -+ TWI_SLAVE_TTIMEOUT_22MS_gc = (0x03<<5), /* 22 Milliseconds */ -+ TWI_SLAVE_TTIMEOUT_26MS_gc = (0x04<<5), /* 26 Milliseconds */ -+ TWI_SLAVE_TTIMEOUT_27MS_gc = (0x05<<5), /* 27 Milliseconds */ -+ TWI_SLAVE_TTIMEOUT_28MS_gc = (0x06<<5), /* 28 Milliseconds */ -+ TWI_SLAVE_TTIMEOUT_29MS_gc = (0x07<<5), /* 29 Milliseconds */ -+} TWI_SLAVE_TTIMEOUT_t; -+ -+/* Master/Slave Extend Timeout */ -+typedef enum TWI_MASTER_TMSEXT_enum -+{ -+ TWI_MASTER_TMSEXT_10MS25MS_gc = (0x00<<3), /* Tmext 10ms Tsext 25ms */ -+ TWI_MASTER_TMSEXT_9MS24MS_gc = (0x01<<3), /* Tmext 9ms Tsext 24ms */ -+ TWI_MASTER_TMSEXT_11MS26MS_gc = (0x02<<3), /* Tmext 11ms Tsext 26ms */ -+ TWI_MASTER_TMSEXT_12MS27MS_gc = (0x03<<3), /* Tmext 12ms Tsext 27ms */ -+} TWI_MASTER_TMSEXT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+PORT - Port Configuration -+-------------------------------------------------------------------------- -+*/ -+ -+/* I/O Ports */ -+typedef struct PORT_struct -+{ -+ register8_t DIR; /* I/O Port Data Direction */ -+ register8_t DIRSET; /* I/O Port Data Direction Set */ -+ register8_t DIRCLR; /* I/O Port Data Direction Clear */ -+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ -+ register8_t OUT; /* I/O Port Output */ -+ register8_t OUTSET; /* I/O Port Output Set */ -+ register8_t OUTCLR; /* I/O Port Output Clear */ -+ register8_t OUTTGL; /* I/O Port Output Toggle */ -+ register8_t IN; /* I/O port Input */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t INTMASK; /* Port Interrupt Mask */ -+ register8_t reserved_0x0B; -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t REMAP; /* Pin Remap Register */ -+ register8_t reserved_0x0F; -+ register8_t PIN0CTRL; /* Pin 0 Control Register */ -+ register8_t PIN1CTRL; /* Pin 1 Control Register */ -+ register8_t PIN2CTRL; /* Pin 2 Control Register */ -+ register8_t PIN3CTRL; /* Pin 3 Control Register */ -+ register8_t PIN4CTRL; /* Pin 4 Control Register */ -+ register8_t PIN5CTRL; /* Pin 5 Control Register */ -+ register8_t PIN6CTRL; /* Pin 6 Control Register */ -+ register8_t PIN7CTRL; /* Pin 7 Control Register */ -+} PORT_t; -+ -+/* Port Interrupt Level */ -+typedef enum PORT_INTLVL_enum -+{ -+ PORT_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ PORT_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ PORT_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ PORT_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} PORT_INTLVL_t; -+ -+/* Output/Pull Configuration */ -+typedef enum PORT_OPC_enum -+{ -+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ -+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ -+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ -+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ -+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ -+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ -+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ -+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ -+} PORT_OPC_t; -+ -+/* Input/Sense Configuration */ -+typedef enum PORT_ISC_enum -+{ -+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ -+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ -+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ -+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ -+ PORT_ISC_FORCE_ENABLE_gc = (0x06<<0), /* Digital Input Buffer Forced Enable */ -+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ -+} PORT_ISC_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+TC - 16-bit Timer/Counter With PWM -+-------------------------------------------------------------------------- -+*/ -+ -+/* 16-bit Timer/Counter 4 */ -+typedef struct TC4_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t CTRLF; /* Control Register F */ -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t CTRLHCLR; /* Control Register H Clear */ -+ register8_t CTRLHSET; /* Control Register H Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ _WORDREGISTER(CCC); /* Compare or Capture C */ -+ _WORDREGISTER(CCD); /* Compare or Capture D */ -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ -+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ -+} TC4_t; -+ -+ -+/* 16-bit Timer/Counter 5 */ -+typedef struct TC5_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t CTRLE; /* Control Register E */ -+ register8_t CTRLF; /* Control Register F */ -+ register8_t INTCTRLA; /* Interrupt Control Register A */ -+ register8_t INTCTRLB; /* Interrupt Control Register B */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G Set */ -+ register8_t CTRLHCLR; /* Control Register H Clear */ -+ register8_t CTRLHSET; /* Control Register H Set */ -+ register8_t INTFLAGS; /* Interrupt Flag Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t TEMP; /* Temporary Register For 16-bit Access */ -+ register8_t reserved_0x10; -+ register8_t reserved_0x11; -+ register8_t reserved_0x12; -+ register8_t reserved_0x13; -+ register8_t reserved_0x14; -+ register8_t reserved_0x15; -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t reserved_0x1E; -+ register8_t reserved_0x1F; -+ _WORDREGISTER(CNT); /* Count */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ _WORDREGISTER(PER); /* Period */ -+ _WORDREGISTER(CCA); /* Compare or Capture A */ -+ _WORDREGISTER(CCB); /* Compare or Capture B */ -+ register8_t reserved_0x2C; -+ register8_t reserved_0x2D; -+ register8_t reserved_0x2E; -+ register8_t reserved_0x2F; -+ register8_t reserved_0x30; -+ register8_t reserved_0x31; -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t reserved_0x34; -+ register8_t reserved_0x35; -+ _WORDREGISTER(PERBUF); /* Period Buffer */ -+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ -+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+} TC5_t; -+ -+/* Clock Selection */ -+typedef enum TC45_CLKSEL_enum -+{ -+ TC45_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ -+ TC45_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ -+ TC45_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ -+ TC45_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ -+ TC45_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ -+ TC45_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ -+ TC45_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ -+ TC45_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ -+ TC45_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC45_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC45_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC45_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC45_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC45_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC45_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC45_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC45_CLKSEL_t; -+ -+/* Byte Mode */ -+typedef enum TC45_BYTEM_enum -+{ -+ TC45_BYTEM_NORMAL_gc = (0x00<<6), /* 16-bit mode */ -+ TC45_BYTEM_BYTEMODE_gc = (0x01<<6), /* Timer/Counter Operating in Byte Mode Only */ -+} TC45_BYTEM_t; -+ -+/* Circular Enable Mode */ -+typedef enum TC45_CIRCEN_enum -+{ -+ TC45_CIRCEN_DISABLE_gc = (0x00<<4), /* Circular Buffer Disabled */ -+ TC45_CIRCEN_PER_gc = (0x01<<4), /* Circular Buffer Enabled on PER/PERBUF */ -+ TC45_CIRCEN_CCA_gc = (0x02<<4), /* Circular Buffer Enabled on CCA/CCABUF */ -+ TC45_CIRCEN_BOTH_gc = (0x03<<4), /* Circular Buffer Enabled on All Buffered Registers */ -+} TC45_CIRCEN_t; -+ -+/* Waveform Generation Mode */ -+typedef enum TC45_WGMODE_enum -+{ -+ TC45_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ -+ TC45_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ -+ TC45_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ -+ TC45_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ -+ TC45_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Both */ -+ TC45_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ -+} TC45_WGMODE_t; -+ -+/* Event Action */ -+typedef enum TC45_EVACT_enum -+{ -+ TC45_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ -+ TC45_EVACT_FMODE1_gc = (0x01<<5), /* Fault Mode 1 capture */ -+ TC45_EVACT_FMODE2_gc = (0x02<<5), /* Fault Mode 2 capture */ -+ TC45_EVACT_UPDOWN_gc = (0x03<<5), /* Up/down count */ -+ TC45_EVACT_QDEC_gc = (0x04<<5), /* Quadrature decode */ -+ TC45_EVACT_RESTART_gc = (0x05<<5), /* Restart */ -+ TC45_EVACT_PWF_gc = (0x06<<5), /* Pulse-width Capture */ -+} TC45_EVACT_t; -+ -+/* Event Selection */ -+typedef enum TC45_EVSEL_enum -+{ -+ TC45_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ TC45_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ -+ TC45_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ -+ TC45_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ -+ TC45_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ -+ TC45_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ -+ TC45_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ -+ TC45_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ -+ TC45_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ -+} TC45_EVSEL_t; -+ -+/* Compare or Capture Channel A Mode */ -+typedef enum TC45_CCAMODE_enum -+{ -+ TC45_CCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ -+ TC45_CCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ -+ TC45_CCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ -+ TC45_CCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -+} TC45_CCAMODE_t; -+ -+/* Compare or Capture Channel B Mode */ -+typedef enum TC45_CCBMODE_enum -+{ -+ TC45_CCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ -+ TC45_CCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ -+ TC45_CCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ -+ TC45_CCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -+} TC45_CCBMODE_t; -+ -+/* Compare or Capture Channel C Mode */ -+typedef enum TC45_CCCMODE_enum -+{ -+ TC45_CCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ -+ TC45_CCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ -+ TC45_CCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ -+ TC45_CCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -+} TC45_CCCMODE_t; -+ -+/* Compare or Capture Channel D Mode */ -+typedef enum TC45_CCDMODE_enum -+{ -+ TC45_CCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ -+ TC45_CCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ -+ TC45_CCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ -+ TC45_CCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -+} TC45_CCDMODE_t; -+ -+/* Compare or Capture Low Channel A Mode */ -+typedef enum TC45_LCCAMODE_enum -+{ -+ TC45_LCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ -+ TC45_LCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ -+ TC45_LCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ -+ TC45_LCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -+} TC45_LCCAMODE_t; -+ -+/* Compare or Capture Low Channel B Mode */ -+typedef enum TC45_LCCBMODE_enum -+{ -+ TC45_LCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ -+ TC45_LCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ -+ TC45_LCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ -+ TC45_LCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -+} TC45_LCCBMODE_t; -+ -+/* Compare or Capture Low Channel C Mode */ -+typedef enum TC45_LCCCMODE_enum -+{ -+ TC45_LCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ -+ TC45_LCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ -+ TC45_LCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ -+ TC45_LCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -+} TC45_LCCCMODE_t; -+ -+/* Compare or Capture Low Channel D Mode */ -+typedef enum TC45_LCCDMODE_enum -+{ -+ TC45_LCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ -+ TC45_LCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ -+ TC45_LCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ -+ TC45_LCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -+} TC45_LCCDMODE_t; -+ -+/* Compare or Capture High Channel A Mode */ -+typedef enum TC45_HCCAMODE_enum -+{ -+ TC45_HCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ -+ TC45_HCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ -+ TC45_HCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ -+ TC45_HCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ -+} TC45_HCCAMODE_t; -+ -+/* Compare or Capture High Channel B Mode */ -+typedef enum TC45_HCCBMODE_enum -+{ -+ TC45_HCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ -+ TC45_HCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ -+ TC45_HCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ -+ TC45_HCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ -+} TC45_HCCBMODE_t; -+ -+/* Compare or Capture High Channel C Mode */ -+typedef enum TC45_HCCCMODE_enum -+{ -+ TC45_HCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ -+ TC45_HCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ -+ TC45_HCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ -+ TC45_HCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ -+} TC45_HCCCMODE_t; -+ -+/* Compare or Capture High Channel D Mode */ -+typedef enum TC45_HCCDMODE_enum -+{ -+ TC45_HCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ -+ TC45_HCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ -+ TC45_HCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ -+ TC45_HCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ -+} TC45_HCCDMODE_t; -+ -+/* Timer Trigger Restart Interrupt Level */ -+typedef enum TC45_TRGINTLVL_enum -+{ -+ TC45_TRGINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC45_TRGINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC45_TRGINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC45_TRGINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC45_TRGINTLVL_t; -+ -+/* Error Interrupt Level */ -+typedef enum TC45_ERRINTLVL_enum -+{ -+ TC45_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC45_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC45_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC45_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC45_ERRINTLVL_t; -+ -+/* Overflow Interrupt Level */ -+typedef enum TC45_OVFINTLVL_enum -+{ -+ TC45_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC45_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC45_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC45_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC45_OVFINTLVL_t; -+ -+/* Compare or Capture Channel A Interrupt Level */ -+typedef enum TC45_CCAINTLVL_enum -+{ -+ TC45_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC45_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC45_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC45_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC45_CCAINTLVL_t; -+ -+/* Compare or Capture Channel B Interrupt Level */ -+typedef enum TC45_CCBINTLVL_enum -+{ -+ TC45_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC45_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC45_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC45_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC45_CCBINTLVL_t; -+ -+/* Compare or Capture Channel C Interrupt Level */ -+typedef enum TC45_CCCINTLVL_enum -+{ -+ TC45_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC45_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC45_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC45_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC45_CCCINTLVL_t; -+ -+/* Compare or Capture Channel D Interrupt Level */ -+typedef enum TC45_CCDINTLVL_enum -+{ -+ TC45_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC45_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC45_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC45_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC45_CCDINTLVL_t; -+ -+/* Compare or Capture Low Channel A Interrupt Level */ -+typedef enum TC45_LCCAINTLVL_enum -+{ -+ TC45_LCCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ TC45_LCCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ TC45_LCCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ TC45_LCCAINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} TC45_LCCAINTLVL_t; -+ -+/* Compare or Capture Low Channel B Interrupt Level */ -+typedef enum TC45_LCCBINTLVL_enum -+{ -+ TC45_LCCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ TC45_LCCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ TC45_LCCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ TC45_LCCBINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} TC45_LCCBINTLVL_t; -+ -+/* Compare or Capture Low Channel C Interrupt Level */ -+typedef enum TC45_LCCCINTLVL_enum -+{ -+ TC45_LCCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ TC45_LCCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ TC45_LCCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ TC45_LCCCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} TC45_LCCCINTLVL_t; -+ -+/* Compare or Capture Low Channel D Interrupt Level */ -+typedef enum TC45_LCCDINTLVL_enum -+{ -+ TC45_LCCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ -+ TC45_LCCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ -+ TC45_LCCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ -+ TC45_LCCDINTLVL_HI_gc = (0x03<<6), /* High Level */ -+} TC45_LCCDINTLVL_t; -+ -+/* Timer/Counter Command */ -+typedef enum TC45_CMD_enum -+{ -+ TC45_CMD_NONE_gc = (0x00<<2), /* No Command */ -+ TC45_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ -+ TC45_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ -+ TC45_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ -+} TC45_CMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FAULT - Fault Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Fault Extension */ -+typedef struct FAULT_struct -+{ -+ register8_t CTRLA; /* Control A Register */ -+ register8_t CTRLB; /* Control B Register */ -+ register8_t CTRLC; /* Control C Register */ -+ register8_t CTRLD; /* Control D Register */ -+ register8_t CTRLE; /* Control E Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRLGCLR; /* Control Register G Clear */ -+ register8_t CTRLGSET; /* Control Register G set */ -+} FAULT_t; -+ -+/* Ramp Mode Selection */ -+typedef enum FAULT_RAMP_enum -+{ -+ FAULT_RAMP_RAMP1_gc = (0x00<<6), /* Normal Mode */ -+ FAULT_RAMP_RAMP2_gc = (0x02<<6), /* RAMP2 Mode */ -+} FAULT_RAMP_t; -+ -+/* Fault E Input Source Selection */ -+typedef enum FAULT_SRCE_enum -+{ -+ FAULT_SRCE_DISABLE_gc = (0x00<<0), /* Fault Protection Disabled */ -+ FAULT_SRCE_CHN_gc = (0x01<<0), /* Event Channel n */ -+ FAULT_SRCE_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ -+ FAULT_SRCE_CHN2_gc = (0x03<<0), /* Event Channel n+2 */ -+} FAULT_SRCE_t; -+ -+/* Fault A Halt Action Selection */ -+typedef enum FAULT_HALTA_enum -+{ -+ FAULT_HALTA_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ -+ FAULT_HALTA_HW_gc = (0x01<<5), /* Hardware Halt Action */ -+ FAULT_HALTA_SW_gc = (0x02<<5), /* Software Halt Action */ -+} FAULT_HALTA_t; -+ -+/* Fault A Source Selection */ -+typedef enum FAULT_SRCA_enum -+{ -+ FAULT_SRCA_DISABLE_gc = (0x00<<0), /* Fault A Disabled */ -+ FAULT_SRCA_CHN_gc = (0x01<<0), /* Event Channel n */ -+ FAULT_SRCA_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ -+ FAULT_SRCA_LINK_gc = (0x03<<0), /* Fault A linked to Fault B State from previous cycle */ -+} FAULT_SRCA_t; -+ -+/* Fault B Halt Action Selection */ -+typedef enum FAULT_HALTB_enum -+{ -+ FAULT_HALTB_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ -+ FAULT_HALTB_HW_gc = (0x01<<5), /* Hardware Halt Action */ -+ FAULT_HALTB_SW_gc = (0x02<<5), /* Software Halt Action */ -+} FAULT_HALTB_t; -+ -+/* Fault B Source Selection */ -+typedef enum FAULT_SRCB_enum -+{ -+ FAULT_SRCB_DISABLE_gc = (0x00<<0), /* Fault B disabled */ -+ FAULT_SRCB_CHN_gc = (0x01<<0), /* Event Channel n */ -+ FAULT_SRCB_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ -+ FAULT_SRCB_LINK_gc = (0x03<<0), /* Fault B linked to Fault A State from previous cycle */ -+} FAULT_SRCB_t; -+ -+/* Channel index Command */ -+typedef enum FAULT_IDXCMD_enum -+{ -+ FAULT_IDXCMD_DISABLE_gc = (0x00<<3), /* Command Disabled */ -+ FAULT_IDXCMD_SET_gc = (0x01<<3), /* Force Cycle B in Next Cycle */ -+ FAULT_IDXCMD_CLEAR_gc = (0x02<<3), /* Force Cycle A in Next Cycle */ -+ FAULT_IDXCMD_HOLD_gc = (0x03<<3), /* Hold Current Cycle Index in Next Cycle */ -+} FAULT_IDXCMD_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+WEX - Waveform Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* Waveform Extension */ -+typedef struct WEX_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t DTBOTH; /* Dead-time Concurrent Write to Both Sides Register */ -+ register8_t DTLS; /* Dead-time Low Side Register */ -+ register8_t DTHS; /* Dead-time High Side Register */ -+ register8_t STATUSCLR; /* Status Clear Register */ -+ register8_t STATUSSET; /* Status Set Register */ -+ register8_t SWAP; /* Swap Register */ -+ register8_t PGO; /* Pattern Generation Override Register */ -+ register8_t PGV; /* Pattern Generation Value Register */ -+ register8_t reserved_0x09; -+ register8_t SWAPBUF; /* Dead Time Low Side Buffer */ -+ register8_t PGOBUF; /* Pattern Generation Overwrite Buffer Register */ -+ register8_t PGVBUF; /* Pattern Generation Value Buffer Register */ -+ register8_t reserved_0x0D; -+ register8_t reserved_0x0E; -+ register8_t OUTOVDIS; /* Output Override Disable Register */ -+} WEX_t; -+ -+/* Output Matrix Mode */ -+typedef enum WEX_OTMX_enum -+{ -+ WEX_OTMX_DEFAULT_gc = (0x00<<4), /* Default Ouput Matrix Mode */ -+ WEX_OTMX_FIRST_gc = (0x01<<4), /* First Output matrix Mode */ -+ WEX_OTMX_SECOND_gc = (0x02<<4), /* Second Output matrix Mode */ -+ WEX_OTMX_THIRD_gc = (0x03<<4), /* Third Output matrix Mode */ -+ WEX_OTMX_FOURTH_gc = (0x04<<4), /* Fourth Output matrix Mode */ -+} WEX_OTMX_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+HIRES - High-Resolution Extension -+-------------------------------------------------------------------------- -+*/ -+ -+/* High-Resolution Extension */ -+typedef struct HIRES_struct -+{ -+ register8_t CTRLA; /* Control Register A */ -+} HIRES_t; -+ -+/* High Resolution Plus Mode */ -+typedef enum HIRES_HRPLUS_enum -+{ -+ HIRES_HRPLUS_NONE_gc = (0x00<<2), /* No Hi-Res Plus */ -+ HIRES_HRPLUS_HRP4_gc = (0x01<<2), /* Hi-Res Plus enabled on Timer 4 */ -+ HIRES_HRPLUS_HRP5_gc = (0x02<<2), /* Hi-Res Plus enabled on Timer 5 */ -+ HIRES_HRPLUS_BOTH_gc = (0x03<<2), /* Hi-Res Plus enabled on Timer 4 and 5 */ -+} HIRES_HRPLUS_t; -+ -+/* High Resolution Mode */ -+typedef enum HIRES_HREN_enum -+{ -+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Hi-Res */ -+ HIRES_HREN_HRP4_gc = (0x01<<0), /* Hi-Res enabled on Timer 4 */ -+ HIRES_HREN_HRP5_gc = (0x02<<0), /* Hi-Res enabled on Timer 5 */ -+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Hi-Res enabled on Timer 4 and 5 */ -+} HIRES_HREN_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+USART - Universal Asynchronous Receiver-Transmitter -+-------------------------------------------------------------------------- -+*/ -+ -+/* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+typedef struct USART_struct -+{ -+ register8_t DATA; /* Data Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t CTRLA; /* Control Register A */ -+ register8_t CTRLB; /* Control Register B */ -+ register8_t CTRLC; /* Control Register C */ -+ register8_t CTRLD; /* Control Register D */ -+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ -+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ -+} USART_t; -+ -+/* Receive Start Interrupt level */ -+typedef enum USART_RXSINTLVL_enum -+{ -+ USART_RXSINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_RXSINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_RXSINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_RXSINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_RXSINTLVL_t; -+ -+/* Receive Complete Interrupt level */ -+typedef enum USART_RXCINTLVL_enum -+{ -+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ -+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ -+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ -+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ -+} USART_RXCINTLVL_t; -+ -+/* Transmit Complete Interrupt level */ -+typedef enum USART_TXCINTLVL_enum -+{ -+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ -+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ -+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ -+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ -+} USART_TXCINTLVL_t; -+ -+/* Data Register Empty Interrupt level */ -+typedef enum USART_DREINTLVL_enum -+{ -+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ -+} USART_DREINTLVL_t; -+ -+/* Character Size */ -+typedef enum USART_CHSIZE_enum -+{ -+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ -+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ -+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ -+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ -+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ -+} USART_CHSIZE_t; -+ -+/* Communication Mode */ -+typedef enum USART_CMODE_enum -+{ -+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ -+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ -+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ -+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ -+} USART_CMODE_t; -+ -+/* Parity Mode */ -+typedef enum USART_PMODE_enum -+{ -+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ -+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ -+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ -+} USART_PMODE_t; -+ -+/* Encoding and Decoding Type */ -+typedef enum USART_DECTYPE_enum -+{ -+ USART_DECTYPE_DATA_gc = (0x00<<4), /* DATA Field Encoding */ -+ USART_DECTYPE_SDATA_gc = (0x02<<4), /* Start and Data Fields Encoding */ -+ USART_DECTYPE_NOTSDATA_gc = (0x03<<4), /* Start and Data Fields Encoding, with invertion in START field */ -+} USART_DECTYPE_t; -+ -+/* XCL LUT Action */ -+typedef enum USART_LUTACT_enum -+{ -+ USART_LUTACT_OFF_gc = (0x00<<2), /* Standard Frame Configuration */ -+ USART_LUTACT_RX_gc = (0x01<<2), /* Receiver Decoding Enabled */ -+ USART_LUTACT_TX_gc = (0x02<<2), /* Transmitter Encoding Enabled */ -+ USART_LUTACT_BOTH_gc = (0x03<<2), /* Both Encoding and Decoding Enabled */ -+} USART_LUTACT_t; -+ -+/* XCL Peripheral Counter Action */ -+typedef enum USART_PECACT_enum -+{ -+ USART_PECACT_OFF_gc = (0x00<<0), /* Standard Mode */ -+ USART_PECACT_PEC0_gc = (0x01<<0), /* Variable Data Lenght in Reception */ -+ USART_PECACT_PEC1_gc = (0x02<<0), /* Variable Data Lenght in Transmission */ -+ USART_PECACT_PERC01_gc = (0x03<<0), /* Variable Data Lenght in both Reception and Transmission */ -+} USART_PECACT_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SPI - Serial Peripheral Interface -+-------------------------------------------------------------------------- -+*/ -+ -+/* Serial Peripheral Interface with Buffer Modes */ -+typedef struct SPI_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t INTCTRL; /* Interrupt Control Register */ -+ register8_t STATUS; /* Status Register */ -+ register8_t DATA; /* Data Register */ -+ register8_t CTRLB; /* Control Register B */ -+} SPI_t; -+ -+/* SPI Mode */ -+typedef enum SPI_MODE_enum -+{ -+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0, base clock at "0", sampling on leading edge (rising) & set-up on trailling edge (falling). */ -+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1, base clock at "0", set-up on leading edge (rising) & sampling on trailling edge (falling). */ -+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2, base clock at "1", sampling on leading edge (falling) & set-up on trailling edge (rising). */ -+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3, base clock at "1", set-up on leading edge (falling) & sampling on trailling edge (rising). */ -+} SPI_MODE_t; -+ -+/* Prescaler setting */ -+typedef enum SPI_PRESCALER_enum -+{ -+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* If CLK2X=1 CLKper/2, else (CLK2X=0) CLKper/4. */ -+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* If CLK2X=1 CLKper/8, else (CLK2X=0) CLKper/16. */ -+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* If CLK2X=1 CLKper/32, else (CLK2X=0) CLKper/64. */ -+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* If CLK2X=1 CLKper/64, else (CLK2X=0) CLKper/128. */ -+} SPI_PRESCALER_t; -+ -+/* Interrupt level */ -+typedef enum SPI_INTLVL_enum -+{ -+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ -+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ -+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ -+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ -+} SPI_INTLVL_t; -+ -+/* Buffer Modes */ -+typedef enum SPI_BUFMODE_enum -+{ -+ SPI_BUFMODE_OFF_gc = (0x00<<6), /* SPI Unbuffered Mode */ -+ SPI_BUFMODE_BUFMODE1_gc = (0x02<<6), /* Buffer Mode 1 (with dummy byte) */ -+ SPI_BUFMODE_BUFMODE2_gc = (0x03<<6), /* Buffer Mode 2 (no dummy byte) */ -+} SPI_BUFMODE_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+IRCOM - IR Communication Module -+-------------------------------------------------------------------------- -+*/ -+ -+/* IR Communication Module */ -+typedef struct IRCOM_struct -+{ -+ register8_t CTRL; /* Control Register */ -+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ -+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ -+} IRCOM_t; -+ -+/* Event channel selection */ -+typedef enum IRDA_EVSEL_enum -+{ -+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ -+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ -+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ -+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ -+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ -+ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ -+ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ -+ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ -+ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ -+} IRDA_EVSEL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+FUSE - Fuses and Lockbits -+-------------------------------------------------------------------------- -+*/ -+ -+/* Lock Bits */ -+typedef struct NVM_LOCKBITS_struct -+{ -+ register8_t LOCKBITS; /* Lock Bits */ -+} NVM_LOCKBITS_t; -+ -+ -+/* Fuses */ -+typedef struct NVM_FUSES_struct -+{ -+ register8_t reserved_0x00; -+ register8_t FUSEBYTE1; /* Watchdog Configuration */ -+ register8_t FUSEBYTE2; /* Reset Configuration */ -+ register8_t reserved_0x03; -+ register8_t FUSEBYTE4; /* Start-up Configuration */ -+ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ -+ register8_t FUSEBYTE6; /* Fault State */ -+} NVM_FUSES_t; -+ -+/* Boot lock bits - boot setcion */ -+typedef enum FUSE_BLBB_enum -+{ -+ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ -+ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ -+ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ -+ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ -+} FUSE_BLBB_t; -+ -+/* Boot lock bits - application section */ -+typedef enum FUSE_BLBA_enum -+{ -+ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ -+ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ -+ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ -+ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ -+} FUSE_BLBA_t; -+ -+/* Boot lock bits - application table section */ -+typedef enum FUSE_BLBAT_enum -+{ -+ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ -+ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ -+ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ -+ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ -+} FUSE_BLBAT_t; -+ -+/* Lock bits */ -+typedef enum FUSE_LB_enum -+{ -+ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ -+ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ -+ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ -+} FUSE_LB_t; -+ -+/* Boot Loader Section Reset Vector */ -+typedef enum BOOTRST_enum -+{ -+ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ -+ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ -+} BOOTRST_t; -+ -+/* BOD operation */ -+typedef enum BOD_enum -+{ -+ BOD_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ -+ BOD_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ -+ BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ -+} BOD_t; -+ -+/* Watchdog (Window) Timeout Period */ -+typedef enum WD_enum -+{ -+ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ -+ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ -+ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ -+ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ -+ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ -+ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ -+ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ -+ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ -+ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ -+ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ -+ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ -+} WD_t; -+ -+/* Start-up Time */ -+typedef enum SUT_enum -+{ -+ SUT_0MS_gc = (0x03<<2), /* 0 ms */ -+ SUT_4MS_gc = (0x01<<2), /* 4 ms */ -+ SUT_64MS_gc = (0x00<<2), /* 64 ms */ -+} SUT_t; -+ -+/* Brown Out Detection Voltage Level */ -+typedef enum BODLVL_enum -+{ -+ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ -+ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ -+ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ -+ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ -+ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ -+ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ -+ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ -+ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ -+} BODLVL_t; -+ -+ -+/* -+-------------------------------------------------------------------------- -+SIGROW - Signature Row -+-------------------------------------------------------------------------- -+*/ -+ -+/* Production Signatures */ -+typedef struct NVM_PROD_SIGNATURES_struct -+{ -+ register8_t RCOSC8M; /* RCOSC 8MHz Calibration Value */ -+ register8_t reserved_0x01; -+ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ -+ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ -+ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ -+ register8_t reserved_0x05; -+ register8_t reserved_0x06; -+ register8_t reserved_0x07; -+ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ -+ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ -+ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ -+ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ -+ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ -+ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ -+ register8_t reserved_0x0E; -+ register8_t reserved_0x0F; -+ register8_t WAFNUM; /* Wafer Number */ -+ register8_t reserved_0x11; -+ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ -+ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ -+ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ -+ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ -+ register8_t reserved_0x16; -+ register8_t reserved_0x17; -+ register8_t reserved_0x18; -+ register8_t reserved_0x19; -+ register8_t reserved_0x1A; -+ register8_t reserved_0x1B; -+ register8_t reserved_0x1C; -+ register8_t reserved_0x1D; -+ register8_t ROOMTEMP; /* Temperature corresponds to TEMPSENSE3/2 */ -+ register8_t HOTTEMP; /* Temperature corresponds to TEMPSENSE1/0 */ -+ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ -+ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ -+ register8_t reserved_0x22; -+ register8_t reserved_0x23; -+ register8_t reserved_0x24; -+ register8_t reserved_0x25; -+ register8_t reserved_0x26; -+ register8_t reserved_0x27; -+ register8_t ACACURRCAL; /* ACA Current Calibration Byte */ -+ register8_t reserved_0x29; -+ register8_t reserved_0x2A; -+ register8_t reserved_0x2B; -+ register8_t TEMPSENSE2; /* Temperature Sensor Calibration Byte 2 */ -+ register8_t TEMPSENSE3; /* Temperature Sensor Calibration Byte 3 */ -+ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ -+ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ -+ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ -+ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ -+ register8_t reserved_0x32; -+ register8_t reserved_0x33; -+ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ -+ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ -+ register8_t reserved_0x36; -+ register8_t reserved_0x37; -+ register8_t reserved_0x38; -+ register8_t reserved_0x39; -+ register8_t reserved_0x3A; -+ register8_t reserved_0x3B; -+ register8_t reserved_0x3C; -+ register8_t reserved_0x3D; -+ register8_t reserved_0x3E; -+ register8_t reserved_0x3F; -+} NVM_PROD_SIGNATURES_t; -+ -+/* -+========================================================================== -+IO Module Instances. Mapped to memory. -+========================================================================== -+*/ -+ -+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ -+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ -+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ -+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ -+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ -+#define CLK (*(CLK_t *) 0x0040) /* Clock System */ -+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ -+#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ -+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ -+#define PR (*(PR_t *) 0x0070) /* Power Reduction */ -+#define RST (*(RST_t *) 0x0078) /* Reset */ -+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ -+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ -+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ -+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ -+#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ -+#define EDMA (*(EDMA_t *) 0x0100) /* Enhanced DMA Controller */ -+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ -+#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ -+#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ -+#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ -+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ -+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ -+#define XCL (*(XCL_t *) 0x0460) /* XMEGA Custom Logic */ -+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ -+#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ -+#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ -+#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ -+#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ -+#define TCC4 (*(TC4_t *) 0x0800) /* 16-bit Timer/Counter 4 */ -+#define TCC5 (*(TC5_t *) 0x0840) /* 16-bit Timer/Counter 5 */ -+#define FAULTC4 (*(FAULT_t *) 0x0880) /* Fault Extension */ -+#define FAULTC5 (*(FAULT_t *) 0x0890) /* Fault Extension */ -+#define WEXC (*(WEX_t *) 0x08A0) /* Waveform Extension */ -+#define HIRESC (*(HIRES_t *) 0x08B0) /* High-Resolution Extension */ -+#define USARTC0 (*(USART_t *) 0x08C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define SPIC (*(SPI_t *) 0x08E0) /* Serial Peripheral Interface with Buffer Modes */ -+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ -+#define TCD5 (*(TC5_t *) 0x0940) /* 16-bit Timer/Counter 5 */ -+#define USARTD0 (*(USART_t *) 0x09C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ -+ -+ -+#endif /* !defined (__ASSEMBLER__) */ -+ -+ -+/* ========== Flattened fully qualified IO register names ========== */ -+ -+/* GPIO - General Purpose IO Registers */ -+#define GPIO_GPIOR0 _SFR_MEM8(0x0000) -+#define GPIO_GPIOR1 _SFR_MEM8(0x0001) -+#define GPIO_GPIOR2 _SFR_MEM8(0x0002) -+#define GPIO_GPIOR3 _SFR_MEM8(0x0003) -+ -+/* Deprecated */ -+#define GPIO_GPIO0 _SFR_MEM8(0x0000) -+#define GPIO_GPIO1 _SFR_MEM8(0x0001) -+#define GPIO_GPIO2 _SFR_MEM8(0x0002) -+#define GPIO_GPIO3 _SFR_MEM8(0x0003) -+ -+/* NVM_FUSES - Fuses */ -+#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) -+#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) -+#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) -+#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) -+#define FUSE_FUSEBYTE6 _SFR_MEM8(0x0006) -+ -+/* NVM_LOCKBITS - Lock Bits */ -+#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) -+ -+/* NVM_PROD_SIGNATURES - Production Signatures */ -+#define PRODSIGNATURES_RCOSC8M _SFR_MEM8(0x0000) -+#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) -+#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) -+#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) -+#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) -+#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) -+#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) -+#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) -+#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) -+#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) -+#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) -+#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) -+#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) -+#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) -+#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) -+#define PRODSIGNATURES_ROOMTEMP _SFR_MEM8(0x001E) -+#define PRODSIGNATURES_HOTTEMP _SFR_MEM8(0x001F) -+#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) -+#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) -+#define PRODSIGNATURES_ACACURRCAL _SFR_MEM8(0x0028) -+#define PRODSIGNATURES_TEMPSENSE2 _SFR_MEM8(0x002C) -+#define PRODSIGNATURES_TEMPSENSE3 _SFR_MEM8(0x002D) -+#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) -+#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) -+#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) -+#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) -+#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) -+#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) -+ -+/* VPORT - Virtual Port */ -+#define VPORT0_DIR _SFR_MEM8(0x0010) -+#define VPORT0_OUT _SFR_MEM8(0x0011) -+#define VPORT0_IN _SFR_MEM8(0x0012) -+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) -+ -+/* VPORT - Virtual Port */ -+#define VPORT1_DIR _SFR_MEM8(0x0014) -+#define VPORT1_OUT _SFR_MEM8(0x0015) -+#define VPORT1_IN _SFR_MEM8(0x0016) -+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) -+ -+/* VPORT - Virtual Port */ -+#define VPORT2_DIR _SFR_MEM8(0x0018) -+#define VPORT2_OUT _SFR_MEM8(0x0019) -+#define VPORT2_IN _SFR_MEM8(0x001A) -+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) -+ -+/* VPORT - Virtual Port */ -+#define VPORT3_DIR _SFR_MEM8(0x001C) -+#define VPORT3_OUT _SFR_MEM8(0x001D) -+#define VPORT3_IN _SFR_MEM8(0x001E) -+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) -+ -+/* OCD - On-Chip Debug System */ -+#define OCD_OCDR0 _SFR_MEM8(0x002E) -+#define OCD_OCDR1 _SFR_MEM8(0x002F) -+ -+/* CPU - CPU registers */ -+#define CPU_CCP _SFR_MEM8(0x0034) -+#define CPU_RAMPD _SFR_MEM8(0x0038) -+#define CPU_RAMPX _SFR_MEM8(0x0039) -+#define CPU_RAMPY _SFR_MEM8(0x003A) -+#define CPU_RAMPZ _SFR_MEM8(0x003B) -+#define CPU_EIND _SFR_MEM8(0x003C) -+#define CPU_SPL _SFR_MEM8(0x003D) -+#define CPU_SPH _SFR_MEM8(0x003E) -+#define CPU_SREG _SFR_MEM8(0x003F) -+ -+/* CLK - Clock System */ -+#define CLK_CTRL _SFR_MEM8(0x0040) -+#define CLK_PSCTRL _SFR_MEM8(0x0041) -+#define CLK_LOCK _SFR_MEM8(0x0042) -+#define CLK_RTCCTRL _SFR_MEM8(0x0043) -+ -+/* SLEEP - Sleep Controller */ -+#define SLEEP_CTRL _SFR_MEM8(0x0048) -+ -+/* OSC - Oscillator */ -+#define OSC_CTRL _SFR_MEM8(0x0050) -+#define OSC_STATUS _SFR_MEM8(0x0051) -+#define OSC_XOSCCTRL _SFR_MEM8(0x0052) -+#define OSC_XOSCFAIL _SFR_MEM8(0x0053) -+#define OSC_RC32KCAL _SFR_MEM8(0x0054) -+#define OSC_PLLCTRL _SFR_MEM8(0x0055) -+#define OSC_DFLLCTRL _SFR_MEM8(0x0056) -+#define OSC_RC8MCAL _SFR_MEM8(0x0057) -+ -+/* DFLL - DFLL */ -+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) -+#define DFLLRC32M_CALA _SFR_MEM8(0x0062) -+#define DFLLRC32M_CALB _SFR_MEM8(0x0063) -+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) -+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) -+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) -+ -+/* PR - Power Reduction */ -+#define PR_PRGEN _SFR_MEM8(0x0070) -+#define PR_PRPA _SFR_MEM8(0x0071) -+#define PR_PRPC _SFR_MEM8(0x0073) -+#define PR_PRPD _SFR_MEM8(0x0074) -+ -+/* RST - Reset */ -+#define RST_STATUS _SFR_MEM8(0x0078) -+#define RST_CTRL _SFR_MEM8(0x0079) -+ -+/* WDT - Watch-Dog Timer */ -+#define WDT_CTRL _SFR_MEM8(0x0080) -+#define WDT_WINCTRL _SFR_MEM8(0x0081) -+#define WDT_STATUS _SFR_MEM8(0x0082) -+ -+/* MCU - MCU Control */ -+#define MCU_DEVID0 _SFR_MEM8(0x0090) -+#define MCU_DEVID1 _SFR_MEM8(0x0091) -+#define MCU_DEVID2 _SFR_MEM8(0x0092) -+#define MCU_REVID _SFR_MEM8(0x0093) -+#define MCU_ANAINIT _SFR_MEM8(0x0097) -+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) -+#define MCU_WEXLOCK _SFR_MEM8(0x0099) -+#define MCU_FAULTLOCK _SFR_MEM8(0x009A) -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+#define PMIC_STATUS _SFR_MEM8(0x00A0) -+#define PMIC_INTPRI _SFR_MEM8(0x00A1) -+#define PMIC_CTRL _SFR_MEM8(0x00A2) -+ -+/* PORTCFG - I/O port Configuration */ -+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) -+#define PORTCFG_CLKOUT _SFR_MEM8(0x00B4) -+#define PORTCFG_ACEVOUT _SFR_MEM8(0x00B6) -+#define PORTCFG_SRLCTRL _SFR_MEM8(0x00B7) -+ -+/* CRC - Cyclic Redundancy Checker */ -+#define CRC_CTRL _SFR_MEM8(0x00D0) -+#define CRC_STATUS _SFR_MEM8(0x00D1) -+#define CRC_DATAIN _SFR_MEM8(0x00D3) -+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) -+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) -+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) -+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) -+ -+/* EDMA - Enhanced DMA Controller */ -+#define EDMA_CTRL _SFR_MEM8(0x0100) -+#define EDMA_INTFLAGS _SFR_MEM8(0x0103) -+#define EDMA_STATUS _SFR_MEM8(0x0104) -+#define EDMA_TEMP _SFR_MEM8(0x0106) -+#define EDMA_CH0_CTRLA _SFR_MEM8(0x0110) -+#define EDMA_CH0_CTRLB _SFR_MEM8(0x0111) -+#define EDMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) -+#define EDMA_CH0_DESTADDRCTRL _SFR_MEM8(0x0113) -+#define EDMA_CH0_TRIGSRC _SFR_MEM8(0x0114) -+#define EDMA_CH0_TRFCNT _SFR_MEM16(0x0116) -+#define EDMA_CH0_ADDR _SFR_MEM16(0x0118) -+#define EDMA_CH0_DESTADDR _SFR_MEM16(0x011C) -+#define EDMA_CH1_CTRLA _SFR_MEM8(0x0120) -+#define EDMA_CH1_CTRLB _SFR_MEM8(0x0121) -+#define EDMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) -+#define EDMA_CH1_DESTADDRCTRL _SFR_MEM8(0x0123) -+#define EDMA_CH1_TRIGSRC _SFR_MEM8(0x0124) -+#define EDMA_CH1_TRFCNT _SFR_MEM16(0x0126) -+#define EDMA_CH1_ADDR _SFR_MEM16(0x0128) -+#define EDMA_CH1_DESTADDR _SFR_MEM16(0x012C) -+#define EDMA_CH2_CTRLA _SFR_MEM8(0x0130) -+#define EDMA_CH2_CTRLB _SFR_MEM8(0x0131) -+#define EDMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) -+#define EDMA_CH2_DESTADDRCTRL _SFR_MEM8(0x0133) -+#define EDMA_CH2_TRIGSRC _SFR_MEM8(0x0134) -+#define EDMA_CH2_TRFCNT _SFR_MEM16(0x0136) -+#define EDMA_CH2_ADDR _SFR_MEM16(0x0138) -+#define EDMA_CH2_DESTADDR _SFR_MEM16(0x013C) -+#define EDMA_CH3_CTRLA _SFR_MEM8(0x0140) -+#define EDMA_CH3_CTRLB _SFR_MEM8(0x0141) -+#define EDMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) -+#define EDMA_CH3_DESTADDRCTRL _SFR_MEM8(0x0143) -+#define EDMA_CH3_TRIGSRC _SFR_MEM8(0x0144) -+#define EDMA_CH3_TRFCNT _SFR_MEM16(0x0146) -+#define EDMA_CH3_ADDR _SFR_MEM16(0x0148) -+#define EDMA_CH3_DESTADDR _SFR_MEM16(0x014C) -+ -+/* EVSYS - Event System */ -+#define EVSYS_CH0MUX _SFR_MEM8(0x0180) -+#define EVSYS_CH1MUX _SFR_MEM8(0x0181) -+#define EVSYS_CH2MUX _SFR_MEM8(0x0182) -+#define EVSYS_CH3MUX _SFR_MEM8(0x0183) -+#define EVSYS_CH4MUX _SFR_MEM8(0x0184) -+#define EVSYS_CH5MUX _SFR_MEM8(0x0185) -+#define EVSYS_CH6MUX _SFR_MEM8(0x0186) -+#define EVSYS_CH7MUX _SFR_MEM8(0x0187) -+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) -+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) -+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) -+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) -+#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) -+#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) -+#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) -+#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) -+#define EVSYS_STROBE _SFR_MEM8(0x0190) -+#define EVSYS_DATA _SFR_MEM8(0x0191) -+#define EVSYS_DFCTRL _SFR_MEM8(0x0192) -+ -+/* NVM - Non-volatile Memory Controller */ -+#define NVM_ADDR0 _SFR_MEM8(0x01C0) -+#define NVM_ADDR1 _SFR_MEM8(0x01C1) -+#define NVM_ADDR2 _SFR_MEM8(0x01C2) -+#define NVM_DATA0 _SFR_MEM8(0x01C4) -+#define NVM_DATA1 _SFR_MEM8(0x01C5) -+#define NVM_DATA2 _SFR_MEM8(0x01C6) -+#define NVM_CMD _SFR_MEM8(0x01CA) -+#define NVM_CTRLA _SFR_MEM8(0x01CB) -+#define NVM_CTRLB _SFR_MEM8(0x01CC) -+#define NVM_INTCTRL _SFR_MEM8(0x01CD) -+#define NVM_STATUS _SFR_MEM8(0x01CF) -+#define NVM_LOCKBITS _SFR_MEM8(0x01D0) -+ -+/* ADC - Analog-to-Digital Converter */ -+#define ADCA_CTRLA _SFR_MEM8(0x0200) -+#define ADCA_CTRLB _SFR_MEM8(0x0201) -+#define ADCA_REFCTRL _SFR_MEM8(0x0202) -+#define ADCA_EVCTRL _SFR_MEM8(0x0203) -+#define ADCA_PRESCALER _SFR_MEM8(0x0204) -+#define ADCA_INTFLAGS _SFR_MEM8(0x0206) -+#define ADCA_TEMP _SFR_MEM8(0x0207) -+#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) -+#define ADCA_CAL _SFR_MEM16(0x020C) -+#define ADCA_CH0RES _SFR_MEM16(0x0210) -+#define ADCA_CMP _SFR_MEM16(0x0218) -+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) -+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) -+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) -+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) -+#define ADCA_CH0_RES _SFR_MEM16(0x0224) -+#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) -+#define ADCA_CH0_CORRCTRL _SFR_MEM8(0x0227) -+#define ADCA_CH0_OFFSETCORR0 _SFR_MEM8(0x0228) -+#define ADCA_CH0_OFFSETCORR1 _SFR_MEM8(0x0229) -+#define ADCA_CH0_GAINCORR0 _SFR_MEM8(0x022A) -+#define ADCA_CH0_GAINCORR1 _SFR_MEM8(0x022B) -+#define ADCA_CH0_AVGCTRL _SFR_MEM8(0x022C) -+ -+/* DAC - Digital-to-Analog Converter */ -+#define DACA_CTRLA _SFR_MEM8(0x0300) -+#define DACA_CTRLB _SFR_MEM8(0x0301) -+#define DACA_CTRLC _SFR_MEM8(0x0302) -+#define DACA_EVCTRL _SFR_MEM8(0x0303) -+#define DACA_STATUS _SFR_MEM8(0x0305) -+#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) -+#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) -+#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) -+#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) -+#define DACA_CH0DATA _SFR_MEM16(0x0318) -+#define DACA_CH1DATA _SFR_MEM16(0x031A) -+ -+/* AC - Analog Comparator */ -+#define ACA_AC0CTRL _SFR_MEM8(0x0380) -+#define ACA_AC1CTRL _SFR_MEM8(0x0381) -+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) -+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) -+#define ACA_CTRLA _SFR_MEM8(0x0384) -+#define ACA_CTRLB _SFR_MEM8(0x0385) -+#define ACA_WINCTRL _SFR_MEM8(0x0386) -+#define ACA_STATUS _SFR_MEM8(0x0387) -+#define ACA_CURRCTRL _SFR_MEM8(0x0388) -+#define ACA_CURRCALIB _SFR_MEM8(0x0389) -+ -+/* RTC - Real-Time Counter */ -+#define RTC_CTRL _SFR_MEM8(0x0400) -+#define RTC_STATUS _SFR_MEM8(0x0401) -+#define RTC_INTCTRL _SFR_MEM8(0x0402) -+#define RTC_INTFLAGS _SFR_MEM8(0x0403) -+#define RTC_TEMP _SFR_MEM8(0x0404) -+#define RTC_CALIB _SFR_MEM8(0x0406) -+#define RTC_CNT _SFR_MEM16(0x0408) -+#define RTC_PER _SFR_MEM16(0x040A) -+#define RTC_COMP _SFR_MEM16(0x040C) -+ -+/* XCL - XMEGA Custom Logic */ -+#define XCL_CTRLA _SFR_MEM8(0x0460) -+#define XCL_CTRLB _SFR_MEM8(0x0461) -+#define XCL_CTRLC _SFR_MEM8(0x0462) -+#define XCL_CTRLD _SFR_MEM8(0x0463) -+#define XCL_CTRLE _SFR_MEM8(0x0464) -+#define XCL_CTRLF _SFR_MEM8(0x0465) -+#define XCL_CTRLG _SFR_MEM8(0x0466) -+#define XCL_INTCTRL _SFR_MEM8(0x0467) -+#define XCL_INTFLAGS _SFR_MEM8(0x0468) -+#define XCL_PLC _SFR_MEM8(0x0469) -+#define XCL_CNTL _SFR_MEM8(0x046A) -+#define XCL_CNTH _SFR_MEM8(0x046B) -+#define XCL_CMPL _SFR_MEM8(0x046C) -+#define XCL_CMPH _SFR_MEM8(0x046D) -+#define XCL_PERCAPTL _SFR_MEM8(0x046E) -+#define XCL_PERCAPTH _SFR_MEM8(0x046F) -+ -+/* TWI - Two-Wire Interface */ -+#define TWIC_CTRL _SFR_MEM8(0x0480) -+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) -+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) -+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) -+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) -+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) -+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) -+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) -+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) -+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) -+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) -+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) -+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) -+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) -+#define TWIC_TIMEOUT_TOS _SFR_MEM8(0x048E) -+#define TWIC_TIMEOUT_TOCONF _SFR_MEM8(0x048F) -+ -+/* PORT - I/O Ports */ -+#define PORTA_DIR _SFR_MEM8(0x0600) -+#define PORTA_DIRSET _SFR_MEM8(0x0601) -+#define PORTA_DIRCLR _SFR_MEM8(0x0602) -+#define PORTA_DIRTGL _SFR_MEM8(0x0603) -+#define PORTA_OUT _SFR_MEM8(0x0604) -+#define PORTA_OUTSET _SFR_MEM8(0x0605) -+#define PORTA_OUTCLR _SFR_MEM8(0x0606) -+#define PORTA_OUTTGL _SFR_MEM8(0x0607) -+#define PORTA_IN _SFR_MEM8(0x0608) -+#define PORTA_INTCTRL _SFR_MEM8(0x0609) -+#define PORTA_INTMASK _SFR_MEM8(0x060A) -+#define PORTA_INTFLAGS _SFR_MEM8(0x060C) -+#define PORTA_REMAP _SFR_MEM8(0x060E) -+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) -+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) -+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) -+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) -+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) -+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) -+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) -+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) -+ -+/* PORT - I/O Ports */ -+#define PORTC_DIR _SFR_MEM8(0x0640) -+#define PORTC_DIRSET _SFR_MEM8(0x0641) -+#define PORTC_DIRCLR _SFR_MEM8(0x0642) -+#define PORTC_DIRTGL _SFR_MEM8(0x0643) -+#define PORTC_OUT _SFR_MEM8(0x0644) -+#define PORTC_OUTSET _SFR_MEM8(0x0645) -+#define PORTC_OUTCLR _SFR_MEM8(0x0646) -+#define PORTC_OUTTGL _SFR_MEM8(0x0647) -+#define PORTC_IN _SFR_MEM8(0x0648) -+#define PORTC_INTCTRL _SFR_MEM8(0x0649) -+#define PORTC_INTMASK _SFR_MEM8(0x064A) -+#define PORTC_INTFLAGS _SFR_MEM8(0x064C) -+#define PORTC_REMAP _SFR_MEM8(0x064E) -+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) -+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) -+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) -+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) -+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) -+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) -+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) -+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) -+ -+/* PORT - I/O Ports */ -+#define PORTD_DIR _SFR_MEM8(0x0660) -+#define PORTD_DIRSET _SFR_MEM8(0x0661) -+#define PORTD_DIRCLR _SFR_MEM8(0x0662) -+#define PORTD_DIRTGL _SFR_MEM8(0x0663) -+#define PORTD_OUT _SFR_MEM8(0x0664) -+#define PORTD_OUTSET _SFR_MEM8(0x0665) -+#define PORTD_OUTCLR _SFR_MEM8(0x0666) -+#define PORTD_OUTTGL _SFR_MEM8(0x0667) -+#define PORTD_IN _SFR_MEM8(0x0668) -+#define PORTD_INTCTRL _SFR_MEM8(0x0669) -+#define PORTD_INTMASK _SFR_MEM8(0x066A) -+#define PORTD_INTFLAGS _SFR_MEM8(0x066C) -+#define PORTD_REMAP _SFR_MEM8(0x066E) -+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) -+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) -+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) -+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) -+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) -+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) -+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) -+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) -+ -+/* PORT - I/O Ports */ -+#define PORTR_DIR _SFR_MEM8(0x07E0) -+#define PORTR_DIRSET _SFR_MEM8(0x07E1) -+#define PORTR_DIRCLR _SFR_MEM8(0x07E2) -+#define PORTR_DIRTGL _SFR_MEM8(0x07E3) -+#define PORTR_OUT _SFR_MEM8(0x07E4) -+#define PORTR_OUTSET _SFR_MEM8(0x07E5) -+#define PORTR_OUTCLR _SFR_MEM8(0x07E6) -+#define PORTR_OUTTGL _SFR_MEM8(0x07E7) -+#define PORTR_IN _SFR_MEM8(0x07E8) -+#define PORTR_INTCTRL _SFR_MEM8(0x07E9) -+#define PORTR_INTMASK _SFR_MEM8(0x07EA) -+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) -+#define PORTR_REMAP _SFR_MEM8(0x07EE) -+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) -+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) -+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) -+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) -+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) -+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) -+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) -+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) -+ -+/* TC4 - 16-bit Timer/Counter 4 */ -+#define TCC4_CTRLA _SFR_MEM8(0x0800) -+#define TCC4_CTRLB _SFR_MEM8(0x0801) -+#define TCC4_CTRLC _SFR_MEM8(0x0802) -+#define TCC4_CTRLD _SFR_MEM8(0x0803) -+#define TCC4_CTRLE _SFR_MEM8(0x0804) -+#define TCC4_CTRLF _SFR_MEM8(0x0805) -+#define TCC4_INTCTRLA _SFR_MEM8(0x0806) -+#define TCC4_INTCTRLB _SFR_MEM8(0x0807) -+#define TCC4_CTRLGCLR _SFR_MEM8(0x0808) -+#define TCC4_CTRLGSET _SFR_MEM8(0x0809) -+#define TCC4_CTRLHCLR _SFR_MEM8(0x080A) -+#define TCC4_CTRLHSET _SFR_MEM8(0x080B) -+#define TCC4_INTFLAGS _SFR_MEM8(0x080C) -+#define TCC4_TEMP _SFR_MEM8(0x080F) -+#define TCC4_CNT _SFR_MEM16(0x0820) -+#define TCC4_PER _SFR_MEM16(0x0826) -+#define TCC4_CCA _SFR_MEM16(0x0828) -+#define TCC4_CCB _SFR_MEM16(0x082A) -+#define TCC4_CCC _SFR_MEM16(0x082C) -+#define TCC4_CCD _SFR_MEM16(0x082E) -+#define TCC4_PERBUF _SFR_MEM16(0x0836) -+#define TCC4_CCABUF _SFR_MEM16(0x0838) -+#define TCC4_CCBBUF _SFR_MEM16(0x083A) -+#define TCC4_CCCBUF _SFR_MEM16(0x083C) -+#define TCC4_CCDBUF _SFR_MEM16(0x083E) -+ -+/* TC5 - 16-bit Timer/Counter 5 */ -+#define TCC5_CTRLA _SFR_MEM8(0x0840) -+#define TCC5_CTRLB _SFR_MEM8(0x0841) -+#define TCC5_CTRLC _SFR_MEM8(0x0842) -+#define TCC5_CTRLD _SFR_MEM8(0x0843) -+#define TCC5_CTRLE _SFR_MEM8(0x0844) -+#define TCC5_CTRLF _SFR_MEM8(0x0845) -+#define TCC5_INTCTRLA _SFR_MEM8(0x0846) -+#define TCC5_INTCTRLB _SFR_MEM8(0x0847) -+#define TCC5_CTRLGCLR _SFR_MEM8(0x0848) -+#define TCC5_CTRLGSET _SFR_MEM8(0x0849) -+#define TCC5_CTRLHCLR _SFR_MEM8(0x084A) -+#define TCC5_CTRLHSET _SFR_MEM8(0x084B) -+#define TCC5_INTFLAGS _SFR_MEM8(0x084C) -+#define TCC5_TEMP _SFR_MEM8(0x084F) -+#define TCC5_CNT _SFR_MEM16(0x0860) -+#define TCC5_PER _SFR_MEM16(0x0866) -+#define TCC5_CCA _SFR_MEM16(0x0868) -+#define TCC5_CCB _SFR_MEM16(0x086A) -+#define TCC5_PERBUF _SFR_MEM16(0x0876) -+#define TCC5_CCABUF _SFR_MEM16(0x0878) -+#define TCC5_CCBBUF _SFR_MEM16(0x087A) -+ -+/* FAULT - Fault Extension */ -+#define FAULTC4_CTRLA _SFR_MEM8(0x0880) -+#define FAULTC4_CTRLB _SFR_MEM8(0x0881) -+#define FAULTC4_CTRLC _SFR_MEM8(0x0882) -+#define FAULTC4_CTRLD _SFR_MEM8(0x0883) -+#define FAULTC4_CTRLE _SFR_MEM8(0x0884) -+#define FAULTC4_STATUS _SFR_MEM8(0x0885) -+#define FAULTC4_CTRLGCLR _SFR_MEM8(0x0886) -+#define FAULTC4_CTRLGSET _SFR_MEM8(0x0887) -+ -+/* FAULT - Fault Extension */ -+#define FAULTC5_CTRLA _SFR_MEM8(0x0890) -+#define FAULTC5_CTRLB _SFR_MEM8(0x0891) -+#define FAULTC5_CTRLC _SFR_MEM8(0x0892) -+#define FAULTC5_CTRLD _SFR_MEM8(0x0893) -+#define FAULTC5_CTRLE _SFR_MEM8(0x0894) -+#define FAULTC5_STATUS _SFR_MEM8(0x0895) -+#define FAULTC5_CTRLGCLR _SFR_MEM8(0x0896) -+#define FAULTC5_CTRLGSET _SFR_MEM8(0x0897) -+ -+/* WEX - Waveform Extension */ -+#define WEXC_CTRL _SFR_MEM8(0x08A0) -+#define WEXC_DTBOTH _SFR_MEM8(0x08A1) -+#define WEXC_DTLS _SFR_MEM8(0x08A2) -+#define WEXC_DTHS _SFR_MEM8(0x08A3) -+#define WEXC_STATUSCLR _SFR_MEM8(0x08A4) -+#define WEXC_STATUSSET _SFR_MEM8(0x08A5) -+#define WEXC_SWAP _SFR_MEM8(0x08A6) -+#define WEXC_PGO _SFR_MEM8(0x08A7) -+#define WEXC_PGV _SFR_MEM8(0x08A8) -+#define WEXC_SWAPBUF _SFR_MEM8(0x08AA) -+#define WEXC_PGOBUF _SFR_MEM8(0x08AB) -+#define WEXC_PGVBUF _SFR_MEM8(0x08AC) -+#define WEXC_OUTOVDIS _SFR_MEM8(0x08AF) -+ -+/* HIRES - High-Resolution Extension */ -+#define HIRESC_CTRLA _SFR_MEM8(0x08B0) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTC0_DATA _SFR_MEM8(0x08C0) -+#define USARTC0_STATUS _SFR_MEM8(0x08C1) -+#define USARTC0_CTRLA _SFR_MEM8(0x08C2) -+#define USARTC0_CTRLB _SFR_MEM8(0x08C3) -+#define USARTC0_CTRLC _SFR_MEM8(0x08C4) -+#define USARTC0_CTRLD _SFR_MEM8(0x08C5) -+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08C6) -+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08C7) -+ -+/* SPI - Serial Peripheral Interface with Buffer Modes */ -+#define SPIC_CTRL _SFR_MEM8(0x08E0) -+#define SPIC_INTCTRL _SFR_MEM8(0x08E1) -+#define SPIC_STATUS _SFR_MEM8(0x08E2) -+#define SPIC_DATA _SFR_MEM8(0x08E3) -+#define SPIC_CTRLB _SFR_MEM8(0x08E4) -+ -+/* IRCOM - IR Communication Module */ -+#define IRCOM_CTRL _SFR_MEM8(0x08F8) -+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) -+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) -+ -+/* TC5 - 16-bit Timer/Counter 5 */ -+#define TCD5_CTRLA _SFR_MEM8(0x0940) -+#define TCD5_CTRLB _SFR_MEM8(0x0941) -+#define TCD5_CTRLC _SFR_MEM8(0x0942) -+#define TCD5_CTRLD _SFR_MEM8(0x0943) -+#define TCD5_CTRLE _SFR_MEM8(0x0944) -+#define TCD5_CTRLF _SFR_MEM8(0x0945) -+#define TCD5_INTCTRLA _SFR_MEM8(0x0946) -+#define TCD5_INTCTRLB _SFR_MEM8(0x0947) -+#define TCD5_CTRLGCLR _SFR_MEM8(0x0948) -+#define TCD5_CTRLGSET _SFR_MEM8(0x0949) -+#define TCD5_CTRLHCLR _SFR_MEM8(0x094A) -+#define TCD5_CTRLHSET _SFR_MEM8(0x094B) -+#define TCD5_INTFLAGS _SFR_MEM8(0x094C) -+#define TCD5_TEMP _SFR_MEM8(0x094F) -+#define TCD5_CNT _SFR_MEM16(0x0960) -+#define TCD5_PER _SFR_MEM16(0x0966) -+#define TCD5_CCA _SFR_MEM16(0x0968) -+#define TCD5_CCB _SFR_MEM16(0x096A) -+#define TCD5_PERBUF _SFR_MEM16(0x0976) -+#define TCD5_CCABUF _SFR_MEM16(0x0978) -+#define TCD5_CCBBUF _SFR_MEM16(0x097A) -+ -+/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ -+#define USARTD0_DATA _SFR_MEM8(0x09C0) -+#define USARTD0_STATUS _SFR_MEM8(0x09C1) -+#define USARTD0_CTRLA _SFR_MEM8(0x09C2) -+#define USARTD0_CTRLB _SFR_MEM8(0x09C3) -+#define USARTD0_CTRLC _SFR_MEM8(0x09C4) -+#define USARTD0_CTRLD _SFR_MEM8(0x09C5) -+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09C6) -+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09C7) -+ -+ -+ -+/*================== Bitfield Definitions ================== */ -+ -+/* VPORT - Virtual Ports */ -+/* VPORT.INTFLAGS bit masks and bit positions */ -+#define VPORT_INT7IF_bm 0x80 /* Interrupt Pin 7 Flag bit mask. */ -+#define VPORT_INT7IF_bp 7 /* Interrupt Pin 7 Flag bit position. */ -+ -+#define VPORT_INT6IF_bm 0x40 /* Interrupt Pin 6 Flag bit mask. */ -+#define VPORT_INT6IF_bp 6 /* Interrupt Pin 6 Flag bit position. */ -+ -+#define VPORT_INT5IF_bm 0x20 /* Interrupt Pin 5 Flag bit mask. */ -+#define VPORT_INT5IF_bp 5 /* Interrupt Pin 5 Flag bit position. */ -+ -+#define VPORT_INT4IF_bm 0x10 /* Interrupt Pin 4 Flag bit mask. */ -+#define VPORT_INT4IF_bp 4 /* Interrupt Pin 4 Flag bit position. */ -+ -+#define VPORT_INT3IF_bm 0x08 /* Interrupt Pin 3 Flag bit mask. */ -+#define VPORT_INT3IF_bp 3 /* Interrupt Pin 3 Flag bit position. */ -+ -+#define VPORT_INT2IF_bm 0x04 /* Interrupt Pin 2 Flag bit mask. */ -+#define VPORT_INT2IF_bp 2 /* Interrupt Pin 2 Flag bit position. */ -+ -+#define VPORT_INT1IF_bm 0x02 /* Interrupt Pin 1 Flag bit mask. */ -+#define VPORT_INT1IF_bp 1 /* Interrupt Pin 1 Flag bit position. */ -+ -+#define VPORT_INT0IF_bm 0x01 /* Interrupt Pin 0 Flag bit mask. */ -+#define VPORT_INT0IF_bp 0 /* Interrupt Pin 0 Flag bit position. */ -+ -+/* XOCD - On-Chip Debug System */ -+/* OCD.OCDR0 bit masks and bit positions */ -+#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ -+#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ -+#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ -+#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ -+#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ -+#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ -+#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ -+#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ -+#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ -+#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ -+#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ -+#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ -+#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ -+#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ -+#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ -+#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ -+#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ -+#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ -+ -+/* OCD.OCDR1 bit masks and bit positions */ -+/* OCD_OCDRD Predefined. */ -+/* OCD_OCDRD Predefined. */ -+ -+/* CPU - CPU */ -+/* CPU.CCP bit masks and bit positions */ -+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ -+#define CPU_CCP_gp 0 /* CCP signature group position. */ -+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ -+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ -+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ -+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ -+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ -+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ -+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ -+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ -+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ -+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ -+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ -+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ -+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ -+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ -+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ -+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ -+ -+/* CPU.SREG bit masks and bit positions */ -+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ -+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ -+ -+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ -+#define CPU_T_bp 6 /* Transfer Bit bit position. */ -+ -+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ -+#define CPU_H_bp 5 /* Half Carry Flag bit position. */ -+ -+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ -+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ -+ -+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ -+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ -+ -+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ -+#define CPU_N_bp 2 /* Negative Flag bit position. */ -+ -+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ -+#define CPU_Z_bp 1 /* Zero Flag bit position. */ -+ -+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ -+#define CPU_C_bp 0 /* Carry Flag bit position. */ -+ -+/* CLK - Clock System */ -+/* CLK.CTRL bit masks and bit positions */ -+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ -+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ -+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ -+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ -+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ -+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ -+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ -+#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ -+ -+/* CLK.PSCTRL bit masks and bit positions */ -+#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ -+#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ -+#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ -+#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ -+#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ -+#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ -+#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ -+#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ -+#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ -+#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ -+#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ -+#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ -+ -+#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ -+#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ -+#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ -+#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ -+#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ -+#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ -+ -+/* CLK.LOCK bit masks and bit positions */ -+#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ -+#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ -+ -+/* CLK.RTCCTRL bit masks and bit positions */ -+#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ -+#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ -+#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ -+#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ -+#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ -+#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ -+#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ -+#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ -+ -+#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ -+#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ -+ -+/* PR.PRGEN bit masks and bit positions */ -+#define PR_XCL_bm 0x80 /* XMEGA Custom Logic bit mask. */ -+#define PR_XCL_bp 7 /* XMEGA Custom Logic bit position. */ -+ -+#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ -+#define PR_RTC_bp 2 /* Real-time Counter bit position. */ -+ -+#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ -+#define PR_EVSYS_bp 1 /* Event System bit position. */ -+ -+#define PR_EDMA_bm 0x01 /* Enhanced DMA-Controller bit mask. */ -+#define PR_EDMA_bp 0 /* Enhanced DMA-Controller bit position. */ -+ -+/* PR.PRPA bit masks and bit positions */ -+#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ -+#define PR_DAC_bp 2 /* Port A DAC bit position. */ -+ -+#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ -+#define PR_ADC_bp 1 /* Port A ADC bit position. */ -+ -+#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ -+#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ -+ -+/* PR.PRPC bit masks and bit positions */ -+#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ -+#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ -+ -+#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ -+#define PR_USART0_bp 4 /* Port C USART0 bit position. */ -+ -+#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ -+#define PR_SPI_bp 3 /* Port C SPI bit position. */ -+ -+#define PR_HIRES_bm 0x04 /* Port C WEX bit mask. */ -+#define PR_HIRES_bp 2 /* Port C WEX bit position. */ -+ -+#define PR_TC5_bm 0x02 /* Port C Timer/Counter5 bit mask. */ -+#define PR_TC5_bp 1 /* Port C Timer/Counter5 bit position. */ -+ -+#define PR_TC4_bm 0x01 /* Port C Timer/Counter4 bit mask. */ -+#define PR_TC4_bp 0 /* Port C Timer/Counter4 bit position. */ -+ -+/* PR.PRPD bit masks and bit positions */ -+/* PR_USART0 Predefined. */ -+/* PR_USART0 Predefined. */ -+ -+/* PR_TC5 Predefined. */ -+/* PR_TC5 Predefined. */ -+ -+/* SLEEP - Sleep Controller */ -+/* SLEEP.CTRL bit masks and bit positions */ -+#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ -+#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ -+#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ -+#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ -+#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ -+#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ -+#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ -+#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ -+ -+#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ -+#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ -+ -+/* OSC - Oscillator */ -+/* OSC.CTRL bit masks and bit positions */ -+#define OSC_RC8MLPM_bm 0x40 /* Internal 8 MHz RC Low Power Mode Enable bit mask. */ -+#define OSC_RC8MLPM_bp 6 /* Internal 8 MHz RC Low Power Mode Enable bit position. */ -+ -+#define OSC_RC8MEN_bm 0x20 /* Internal 8 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC8MEN_bp 5 /* Internal 8 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ -+#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ -+ -+#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ -+#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ -+ -+#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ -+ -+#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ -+#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ -+ -+/* OSC.STATUS bit masks and bit positions */ -+#define OSC_RC8MRDY_bm 0x20 /* Internal 8 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC8MRDY_bp 5 /* Internal 8 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ -+#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ -+ -+#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ -+#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ -+ -+#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ -+ -+#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ -+#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ -+ -+/* OSC.XOSCCTRL bit masks and bit positions */ -+#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ -+#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ -+#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ -+#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ -+#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ -+#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ -+ -+#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ -+#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ -+ -+#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ -+#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ -+ -+#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ -+#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ -+#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ -+#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ -+#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ -+#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ -+#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ -+#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ -+#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ -+#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ -+#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ -+#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ -+ -+/* OSC.XOSCFAIL bit masks and bit positions */ -+#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ -+#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ -+#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ -+ -+#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ -+#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ -+ -+#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ -+#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ -+ -+/* OSC.PLLCTRL bit masks and bit positions */ -+#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ -+#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ -+#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ -+#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ -+#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ -+#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ -+ -+#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ -+#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ -+ -+#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ -+#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ -+#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ -+#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ -+#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ -+#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ -+#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ -+#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ -+#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ -+#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ -+#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ -+#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ -+ -+/* OSC.DFLLCTRL bit masks and bit positions */ -+#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ -+#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ -+#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ -+#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ -+#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ -+#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ -+ -+/* OSC.RC8MCAL bit masks and bit positions */ -+#define OSC_RC8MCAL_gm 0xFF /* Calibration Bits group mask. */ -+#define OSC_RC8MCAL_gp 0 /* Calibration Bits group position. */ -+#define OSC_RC8MCAL0_bm (1<<0) /* Calibration Bits bit 0 mask. */ -+#define OSC_RC8MCAL0_bp 0 /* Calibration Bits bit 0 position. */ -+#define OSC_RC8MCAL1_bm (1<<1) /* Calibration Bits bit 1 mask. */ -+#define OSC_RC8MCAL1_bp 1 /* Calibration Bits bit 1 position. */ -+#define OSC_RC8MCAL2_bm (1<<2) /* Calibration Bits bit 2 mask. */ -+#define OSC_RC8MCAL2_bp 2 /* Calibration Bits bit 2 position. */ -+#define OSC_RC8MCAL3_bm (1<<3) /* Calibration Bits bit 3 mask. */ -+#define OSC_RC8MCAL3_bp 3 /* Calibration Bits bit 3 position. */ -+#define OSC_RC8MCAL4_bm (1<<4) /* Calibration Bits bit 4 mask. */ -+#define OSC_RC8MCAL4_bp 4 /* Calibration Bits bit 4 position. */ -+#define OSC_RC8MCAL5_bm (1<<5) /* Calibration Bits bit 5 mask. */ -+#define OSC_RC8MCAL5_bp 5 /* Calibration Bits bit 5 position. */ -+#define OSC_RC8MCAL6_bm (1<<6) /* Calibration Bits bit 6 mask. */ -+#define OSC_RC8MCAL6_bp 6 /* Calibration Bits bit 6 position. */ -+#define OSC_RC8MCAL7_bm (1<<7) /* Calibration Bits bit 7 mask. */ -+#define OSC_RC8MCAL7_bp 7 /* Calibration Bits bit 7 position. */ -+ -+/* DFLL - DFLL */ -+/* DFLL.CTRL bit masks and bit positions */ -+#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ -+#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ -+ -+/* DFLL.CALA bit masks and bit positions */ -+#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ -+#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ -+#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ -+#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ -+#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ -+#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ -+#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ -+#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ -+#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ -+#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ -+#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ -+#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ -+#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ -+#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ -+#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ -+#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ -+ -+/* DFLL.CALB bit masks and bit positions */ -+#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ -+#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ -+#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ -+#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ -+#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ -+#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ -+#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ -+#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ -+#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ -+#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ -+#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ -+#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ -+#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ -+#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ -+ -+/* RST - Reset */ -+/* RST.STATUS bit masks and bit positions */ -+#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ -+#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ -+ -+#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ -+#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ -+ -+#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ -+#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ -+ -+#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ -+#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ -+ -+#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ -+#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ -+ -+#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ -+#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ -+ -+#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ -+#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ -+ -+/* RST.CTRL bit masks and bit positions */ -+#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ -+#define RST_SWRST_bp 0 /* Software Reset bit position. */ -+ -+/* WDT - Watch-Dog Timer */ -+/* WDT.CTRL bit masks and bit positions */ -+#define WDT_PER_gm 0x3C /* Period group mask. */ -+#define WDT_PER_gp 2 /* Period group position. */ -+#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ -+#define WDT_PER0_bp 2 /* Period bit 0 position. */ -+#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ -+#define WDT_PER1_bp 3 /* Period bit 1 position. */ -+#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ -+#define WDT_PER2_bp 4 /* Period bit 2 position. */ -+#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ -+#define WDT_PER3_bp 5 /* Period bit 3 position. */ -+ -+#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ -+#define WDT_ENABLE_bp 1 /* Enable bit position. */ -+ -+#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ -+#define WDT_CEN_bp 0 /* Change Enable bit position. */ -+ -+/* WDT.WINCTRL bit masks and bit positions */ -+#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ -+#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ -+#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ -+#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ -+#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ -+#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ -+#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ -+#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ -+#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ -+#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ -+ -+#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ -+#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ -+ -+#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ -+#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ -+ -+/* WDT.STATUS bit masks and bit positions */ -+#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ -+#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ -+ -+/* MCU - MCU Control */ -+/* MCU.ANAINIT bit masks and bit positions */ -+#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ -+#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ -+#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ -+#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ -+#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ -+#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ -+ -+/* MCU.EVSYSLOCK bit masks and bit positions */ -+#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ -+#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ -+ -+#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ -+#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ -+ -+/* MCU.WEXLOCK bit masks and bit positions */ -+#define MCU_WEXCLOCK_bm 0x01 /* WeX on T/C C4 Lock bit mask. */ -+#define MCU_WEXCLOCK_bp 0 /* WeX on T/C C4 Lock bit position. */ -+ -+/* MCU.FAULTLOCK bit masks and bit positions */ -+#define MCU_FAULTC5LOCK_bm 0x02 /* Fault on T/C C5 Lock bit mask. */ -+#define MCU_FAULTC5LOCK_bp 1 /* Fault on T/C C5 Lock bit position. */ -+ -+#define MCU_FAULTC4LOCK_bm 0x01 /* Fault on T/C C4 Lock bit mask. */ -+#define MCU_FAULTC4LOCK_bp 0 /* Fault on T/C C4 Lock bit position. */ -+ -+/* PMIC - Programmable Multi-level Interrupt Controller */ -+/* PMIC.STATUS bit masks and bit positions */ -+#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ -+#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ -+ -+#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ -+#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ -+ -+#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ -+#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ -+ -+#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ -+#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ -+ -+/* PMIC.INTPRI bit masks and bit positions */ -+#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ -+#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ -+#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ -+#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ -+#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ -+#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ -+#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ -+#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ -+#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ -+#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ -+#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ -+#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ -+#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ -+#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ -+#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ -+#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ -+#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ -+#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ -+ -+/* PMIC.CTRL bit masks and bit positions */ -+#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ -+#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ -+ -+#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ -+#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ -+ -+#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ -+#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ -+ -+#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ -+#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ -+ -+#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ -+#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ -+ -+/* PORTCFG - Port Configuration */ -+/* PORTCFG.CLKOUT bit masks and bit positions */ -+#define PORTCFG_CLKEVPIN_bm 0x80 /* Clock and Event Output Pin Select bit mask. */ -+#define PORTCFG_CLKEVPIN_bp 7 /* Clock and Event Output Pin Select bit position. */ -+ -+#define PORTCFG_RTCOUT_gm 0x60 /* RTC Clock Output Enable group mask. */ -+#define PORTCFG_RTCOUT_gp 5 /* RTC Clock Output Enable group position. */ -+#define PORTCFG_RTCOUT0_bm (1<<5) /* RTC Clock Output Enable bit 0 mask. */ -+#define PORTCFG_RTCOUT0_bp 5 /* RTC Clock Output Enable bit 0 position. */ -+#define PORTCFG_RTCOUT1_bm (1<<6) /* RTC Clock Output Enable bit 1 mask. */ -+#define PORTCFG_RTCOUT1_bp 6 /* RTC Clock Output Enable bit 1 position. */ -+ -+#define PORTCFG_CLKOUTSEL_gm 0x0C /* Clock Output Select group mask. */ -+#define PORTCFG_CLKOUTSEL_gp 2 /* Clock Output Select group position. */ -+#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Clock Output Select bit 0 mask. */ -+#define PORTCFG_CLKOUTSEL0_bp 2 /* Clock Output Select bit 0 position. */ -+#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Clock Output Select bit 1 mask. */ -+#define PORTCFG_CLKOUTSEL1_bp 3 /* Clock Output Select bit 1 position. */ -+ -+#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ -+#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ -+#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ -+#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ -+#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ -+#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ -+ -+/* PORTCFG.ACEVOUT bit masks and bit positions */ -+#define PORTCFG_ACOUT_gm 0xC0 /* Analog Comparator Output Port group mask. */ -+#define PORTCFG_ACOUT_gp 6 /* Analog Comparator Output Port group position. */ -+#define PORTCFG_ACOUT0_bm (1<<6) /* Analog Comparator Output Port bit 0 mask. */ -+#define PORTCFG_ACOUT0_bp 6 /* Analog Comparator Output Port bit 0 position. */ -+#define PORTCFG_ACOUT1_bm (1<<7) /* Analog Comparator Output Port bit 1 mask. */ -+#define PORTCFG_ACOUT1_bp 7 /* Analog Comparator Output Port bit 1 position. */ -+ -+#define PORTCFG_EVOUT_gm 0x30 /* Event Channel Output Port group mask. */ -+#define PORTCFG_EVOUT_gp 4 /* Event Channel Output Port group position. */ -+#define PORTCFG_EVOUT0_bm (1<<4) /* Event Channel Output Port bit 0 mask. */ -+#define PORTCFG_EVOUT0_bp 4 /* Event Channel Output Port bit 0 position. */ -+#define PORTCFG_EVOUT1_bm (1<<5) /* Event Channel Output Port bit 1 mask. */ -+#define PORTCFG_EVOUT1_bp 5 /* Event Channel Output Port bit 1 position. */ -+ -+#define PORTCFG_EVASYEN_bm 0x08 /* Asynchronous Event Enabled bit mask. */ -+#define PORTCFG_EVASYEN_bp 3 /* Asynchronous Event Enabled bit position. */ -+ -+#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Channel Output Selection group mask. */ -+#define PORTCFG_EVOUTSEL_gp 0 /* Event Channel Output Selection group position. */ -+#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Channel Output Selection bit 0 mask. */ -+#define PORTCFG_EVOUTSEL0_bp 0 /* Event Channel Output Selection bit 0 position. */ -+#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Channel Output Selection bit 1 mask. */ -+#define PORTCFG_EVOUTSEL1_bp 1 /* Event Channel Output Selection bit 1 position. */ -+#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Channel Output Selection bit 2 mask. */ -+#define PORTCFG_EVOUTSEL2_bp 2 /* Event Channel Output Selection bit 2 position. */ -+ -+/* PORTCFG.SRLCTRL bit masks and bit positions */ -+#define PORTCFG_SRLENRA_bm 0x01 /* Slew Rate Limit Enable on PORTA bit mask. */ -+#define PORTCFG_SRLENRA_bp 0 /* Slew Rate Limit Enable on PORTA bit position. */ -+ -+#define PORTCFG_SRLENRC_bm 0x04 /* Slew Rate Limit Enable on PORTC bit mask. */ -+#define PORTCFG_SRLENRC_bp 2 /* Slew Rate Limit Enable on PORTC bit position. */ -+ -+#define PORTCFG_SRLENRD_bm 0x08 /* Slew Rate Limit Enable on PORTD bit mask. */ -+#define PORTCFG_SRLENRD_bp 3 /* Slew Rate Limit Enable on PORTD bit position. */ -+ -+#define PORTCFG_SRLENRR_bm 0x80 /* Slew Rate Limit Enable on PORTR bit mask. */ -+#define PORTCFG_SRLENRR_bp 7 /* Slew Rate Limit Enable on PORTR bit position. */ -+ -+/* CRC - Cyclic Redundancy Checker */ -+/* CRC.CTRL bit masks and bit positions */ -+#define CRC_RESET_gm 0xC0 /* Reset group mask. */ -+#define CRC_RESET_gp 6 /* Reset group position. */ -+#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ -+#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ -+#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ -+#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ -+ -+#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ -+#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ -+ -+#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ -+#define CRC_SOURCE_gp 0 /* Input Source group position. */ -+#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ -+#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ -+#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ -+#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ -+#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ -+#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ -+#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ -+#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ -+ -+/* CRC.STATUS bit masks and bit positions */ -+#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ -+#define CRC_ZERO_bp 1 /* Zero detection bit position. */ -+ -+#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ -+#define CRC_BUSY_bp 0 /* Busy bit position. */ -+ -+/* EDMA - Enhanced DMA Controller */ -+/* EDMA.CTRL bit masks and bit positions */ -+#define EDMA_ENABLE_bm 0x80 /* Enable bit mask. */ -+#define EDMA_ENABLE_bp 7 /* Enable bit position. */ -+ -+#define EDMA_RESET_bm 0x40 /* Software Reset bit mask. */ -+#define EDMA_RESET_bp 6 /* Software Reset bit position. */ -+ -+#define EDMA_CHMODE_gm 0x30 /* Channel Mode group mask. */ -+#define EDMA_CHMODE_gp 4 /* Channel Mode group position. */ -+#define EDMA_CHMODE0_bm (1<<4) /* Channel Mode bit 0 mask. */ -+#define EDMA_CHMODE0_bp 4 /* Channel Mode bit 0 position. */ -+#define EDMA_CHMODE1_bm (1<<5) /* Channel Mode bit 1 mask. */ -+#define EDMA_CHMODE1_bp 5 /* Channel Mode bit 1 position. */ -+ -+#define EDMA_DBUFMODE_gm 0x0C /* Double Buffer Mode group mask. */ -+#define EDMA_DBUFMODE_gp 2 /* Double Buffer Mode group position. */ -+#define EDMA_DBUFMODE0_bm (1<<2) /* Double Buffer Mode bit 0 mask. */ -+#define EDMA_DBUFMODE0_bp 2 /* Double Buffer Mode bit 0 position. */ -+#define EDMA_DBUFMODE1_bm (1<<3) /* Double Buffer Mode bit 1 mask. */ -+#define EDMA_DBUFMODE1_bp 3 /* Double Buffer Mode bit 1 position. */ -+ -+#define EDMA_PRIMODE_gm 0x03 /* Priority Mode group mask. */ -+#define EDMA_PRIMODE_gp 0 /* Priority Mode group position. */ -+#define EDMA_PRIMODE0_bm (1<<0) /* Priority Mode bit 0 mask. */ -+#define EDMA_PRIMODE0_bp 0 /* Priority Mode bit 0 position. */ -+#define EDMA_PRIMODE1_bm (1<<1) /* Priority Mode bit 1 mask. */ -+#define EDMA_PRIMODE1_bp 1 /* Priority Mode bit 1 position. */ -+ -+/* EDMA.INTFLAGS bit masks and bit positions */ -+#define EDMA_CH3ERRIF_bm 0x80 /* Channel 3 Transaction Error Interrupt Flag bit mask. */ -+#define EDMA_CH3ERRIF_bp 7 /* Channel 3 Transaction Error Interrupt Flag bit position. */ -+ -+#define EDMA_CH2ERRIF_bm 0x40 /* Channel 2 Transaction Error Interrupt Flag bit mask. */ -+#define EDMA_CH2ERRIF_bp 6 /* Channel 2 Transaction Error Interrupt Flag bit position. */ -+ -+#define EDMA_CH1ERRIF_bm 0x20 /* Channel 1 Transaction Error Interrupt Flag bit mask. */ -+#define EDMA_CH1ERRIF_bp 5 /* Channel 1 Transaction Error Interrupt Flag bit position. */ -+ -+#define EDMA_CH0ERRIF_bm 0x10 /* Channel 0 Transaction Error Interrupt Flag bit mask. */ -+#define EDMA_CH0ERRIF_bp 4 /* Channel 0 Transaction Error Interrupt Flag bit position. */ -+ -+#define EDMA_CH3TRNFIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ -+#define EDMA_CH3TRNFIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ -+ -+#define EDMA_CH2TRNFIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ -+#define EDMA_CH2TRNFIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ -+ -+#define EDMA_CH1TRNFIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ -+#define EDMA_CH1TRNFIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ -+ -+#define EDMA_CH0TRNFIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ -+#define EDMA_CH0TRNFIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ -+ -+/* EDMA.STATUS bit masks and bit positions */ -+#define EDMA_CH3BUSY_bm 0x80 /* Channel 3 Busy Flag bit mask. */ -+#define EDMA_CH3BUSY_bp 7 /* Channel 3 Busy Flag bit position. */ -+ -+#define EDMA_CH2BUSY_bm 0x40 /* Channel 2 Busy Flag bit mask. */ -+#define EDMA_CH2BUSY_bp 6 /* Channel 2 Busy Flag bit position. */ -+ -+#define EDMA_CH1BUSY_bm 0x20 /* Channel 1 Busy Flag bit mask. */ -+#define EDMA_CH1BUSY_bp 5 /* Channel 1 Busy Flag bit position. */ -+ -+#define EDMA_CH0BUSY_bm 0x10 /* Channel 0 Busy Flag bit mask. */ -+#define EDMA_CH0BUSY_bp 4 /* Channel 0 Busy Flag bit position. */ -+ -+#define EDMA_CH3PEND_bm 0x08 /* Channel 3 Pending Flag bit mask. */ -+#define EDMA_CH3PEND_bp 3 /* Channel 3 Pending Flag bit position. */ -+ -+#define EDMA_CH2PEND_bm 0x04 /* Channel 2 Pending Flag bit mask. */ -+#define EDMA_CH2PEND_bp 2 /* Channel 2 Pending Flag bit position. */ -+ -+#define EDMA_CH1PEND_bm 0x02 /* Channel 1 Pending Flag bit mask. */ -+#define EDMA_CH1PEND_bp 1 /* Channel 1 Pending Flag bit position. */ -+ -+#define EDMA_CH0PEND_bm 0x01 /* Channel 0 Pending Flag bit mask. */ -+#define EDMA_CH0PEND_bp 0 /* Channel 0 Pending Flag bit position. */ -+ -+/* EDMA_CH.CTRLA bit masks and bit positions */ -+#define EDMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ -+#define EDMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ -+ -+#define EDMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ -+#define EDMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ -+ -+#define EDMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ -+#define EDMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ -+ -+#define EDMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ -+#define EDMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ -+ -+#define EDMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ -+#define EDMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ -+ -+#define EDMA_CH_BURSTLEN_bm 0x01 /* Channel 2-bytes Burst Length bit mask. */ -+#define EDMA_CH_BURSTLEN_bp 0 /* Channel 2-bytes Burst Length bit position. */ -+ -+/* EDMA_CH.CTRLB bit masks and bit positions */ -+#define EDMA_CH_CHBUSY_bm 0x80 /* Channel Block Transfer Busy bit mask. */ -+#define EDMA_CH_CHBUSY_bp 7 /* Channel Block Transfer Busy bit position. */ -+ -+#define EDMA_CH_CHPEND_bm 0x40 /* Channel Block Transfer Pending bit mask. */ -+#define EDMA_CH_CHPEND_bp 6 /* Channel Block Transfer Pending bit position. */ -+ -+#define EDMA_CH_ERRIF_bm 0x20 /* Channel Transaction Error Interrupt Flag bit mask. */ -+#define EDMA_CH_ERRIF_bp 5 /* Channel Transaction Error Interrupt Flag bit position. */ -+ -+#define EDMA_CH_TRNIF_bm 0x10 /* Channel Transaction Complete Interrup Flag bit mask. */ -+#define EDMA_CH_TRNIF_bp 4 /* Channel Transaction Complete Interrup Flag bit position. */ -+ -+#define EDMA_CH_ERRINTLVL_gm 0x0C /* Channel Transaction Error Interrupt Level group mask. */ -+#define EDMA_CH_ERRINTLVL_gp 2 /* Channel Transaction Error Interrupt Level group position. */ -+#define EDMA_CH_ERRINTLVL0_bm (1<<2) /* Channel Transaction Error Interrupt Level bit 0 mask. */ -+#define EDMA_CH_ERRINTLVL0_bp 2 /* Channel Transaction Error Interrupt Level bit 0 position. */ -+#define EDMA_CH_ERRINTLVL1_bm (1<<3) /* Channel Transaction Error Interrupt Level bit 1 mask. */ -+#define EDMA_CH_ERRINTLVL1_bp 3 /* Channel Transaction Error Interrupt Level bit 1 position. */ -+ -+#define EDMA_CH_TRNINTLVL_gm 0x03 /* Channel Transaction Complete Interrupt Level group mask. */ -+#define EDMA_CH_TRNINTLVL_gp 0 /* Channel Transaction Complete Interrupt Level group position. */ -+#define EDMA_CH_TRNINTLVL0_bm (1<<0) /* Channel Transaction Complete Interrupt Level bit 0 mask. */ -+#define EDMA_CH_TRNINTLVL0_bp 0 /* Channel Transaction Complete Interrupt Level bit 0 position. */ -+#define EDMA_CH_TRNINTLVL1_bm (1<<1) /* Channel Transaction Complete Interrupt Level bit 1 mask. */ -+#define EDMA_CH_TRNINTLVL1_bp 1 /* Channel Transaction Complete Interrupt Level bit 1 position. */ -+ -+/* EDMA_CH.ADDRCTRL bit masks and bit positions */ -+#define EDMA_CH_RELOAD_gm 0x30 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group mask. */ -+#define EDMA_CH_RELOAD_gp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group position. */ -+#define EDMA_CH_RELOAD0_bm (1<<4) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 mask. */ -+#define EDMA_CH_RELOAD0_bp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 position. */ -+#define EDMA_CH_RELOAD1_bm (1<<5) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 mask. */ -+#define EDMA_CH_RELOAD1_bp 5 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 position. */ -+ -+#define EDMA_CH_DIR_gm 0x07 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group mask. */ -+#define EDMA_CH_DIR_gp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group position. */ -+#define EDMA_CH_DIR0_bm (1<<0) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 mask. */ -+#define EDMA_CH_DIR0_bp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 position. */ -+#define EDMA_CH_DIR1_bm (1<<1) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 mask. */ -+#define EDMA_CH_DIR1_bp 1 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 position. */ -+#define EDMA_CH_DIR2_bm (1<<2) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 mask. */ -+#define EDMA_CH_DIR2_bp 2 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 position. */ -+ -+/* EDMA_CH.DESTADDRCTRL bit masks and bit positions */ -+#define EDMA_CH_DESTRELOAD_gm 0x30 /* Destination Address Reload for Standard Channels Only. group mask. */ -+#define EDMA_CH_DESTRELOAD_gp 4 /* Destination Address Reload for Standard Channels Only. group position. */ -+#define EDMA_CH_DESTRELOAD0_bm (1<<4) /* Destination Address Reload for Standard Channels Only. bit 0 mask. */ -+#define EDMA_CH_DESTRELOAD0_bp 4 /* Destination Address Reload for Standard Channels Only. bit 0 position. */ -+#define EDMA_CH_DESTRELOAD1_bm (1<<5) /* Destination Address Reload for Standard Channels Only. bit 1 mask. */ -+#define EDMA_CH_DESTRELOAD1_bp 5 /* Destination Address Reload for Standard Channels Only. bit 1 position. */ -+ -+#define EDMA_CH_DESTDIR_gm 0x07 /* Destination Address Mode for Standard Channels Only. group mask. */ -+#define EDMA_CH_DESTDIR_gp 0 /* Destination Address Mode for Standard Channels Only. group position. */ -+#define EDMA_CH_DESTDIR0_bm (1<<0) /* Destination Address Mode for Standard Channels Only. bit 0 mask. */ -+#define EDMA_CH_DESTDIR0_bp 0 /* Destination Address Mode for Standard Channels Only. bit 0 position. */ -+#define EDMA_CH_DESTDIR1_bm (1<<1) /* Destination Address Mode for Standard Channels Only. bit 1 mask. */ -+#define EDMA_CH_DESTDIR1_bp 1 /* Destination Address Mode for Standard Channels Only. bit 1 position. */ -+#define EDMA_CH_DESTDIR2_bm (1<<2) /* Destination Address Mode for Standard Channels Only. bit 2 mask. */ -+#define EDMA_CH_DESTDIR2_bp 2 /* Destination Address Mode for Standard Channels Only. bit 2 position. */ -+ -+/* EDMA_CH.TRIGSRC bit masks and bit positions */ -+#define EDMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ -+#define EDMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ -+#define EDMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ -+#define EDMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ -+#define EDMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ -+#define EDMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ -+#define EDMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ -+#define EDMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ -+#define EDMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ -+#define EDMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ -+#define EDMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ -+#define EDMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ -+#define EDMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ -+#define EDMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ -+#define EDMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ -+#define EDMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ -+#define EDMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ -+#define EDMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ -+ -+/* EVSYS - Event System */ -+/* EVSYS.CH0MUX bit masks and bit positions */ -+#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ -+#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ -+#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ -+#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ -+#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ -+#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ -+#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ -+#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ -+#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ -+#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ -+#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ -+#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ -+#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ -+#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ -+#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ -+#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ -+#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ -+#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ -+ -+/* EVSYS.CH1MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH2MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH3MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH4MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH5MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH6MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH7MUX bit masks and bit positions */ -+/* EVSYS_CHMUX Predefined. */ -+/* EVSYS_CHMUX Predefined. */ -+ -+/* EVSYS.CH0CTRL bit masks and bit positions */ -+#define EVSYS_ROTARY_bm 0x80 /* Rotary Decoder Enable bit mask. */ -+#define EVSYS_ROTARY_bp 7 /* Rotary Decoder Enable bit position. */ -+ -+#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ -+#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ -+#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ -+#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ -+#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ -+#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ -+ -+#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ -+#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ -+ -+#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ -+#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ -+ -+#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ -+#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ -+#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ -+#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ -+#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ -+#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ -+#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ -+#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ -+ -+/* EVSYS.CH1CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH2CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH3CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH4CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH5CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH6CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.CH7CTRL bit masks and bit positions */ -+/* EVSYS_DIGFILT Predefined. */ -+/* EVSYS_DIGFILT Predefined. */ -+ -+/* EVSYS.DFCTRL bit masks and bit positions */ -+#define EVSYS_PRESCFILT_gm 0xF0 /* Prescaler Filter group mask. */ -+#define EVSYS_PRESCFILT_gp 4 /* Prescaler Filter group position. */ -+#define EVSYS_PRESCFILT0_bm (1<<4) /* Prescaler Filter bit 0 mask. */ -+#define EVSYS_PRESCFILT0_bp 4 /* Prescaler Filter bit 0 position. */ -+#define EVSYS_PRESCFILT1_bm (1<<5) /* Prescaler Filter bit 1 mask. */ -+#define EVSYS_PRESCFILT1_bp 5 /* Prescaler Filter bit 1 position. */ -+#define EVSYS_PRESCFILT2_bm (1<<6) /* Prescaler Filter bit 2 mask. */ -+#define EVSYS_PRESCFILT2_bp 6 /* Prescaler Filter bit 2 position. */ -+#define EVSYS_PRESCFILT3_bm (1<<7) /* Prescaler Filter bit 3 mask. */ -+#define EVSYS_PRESCFILT3_bp 7 /* Prescaler Filter bit 3 position. */ -+ -+#define EVSYS_FILTSEL_bm 0x08 /* Prescaler Filter Select bit mask. */ -+#define EVSYS_FILTSEL_bp 3 /* Prescaler Filter Select bit position. */ -+ -+#define EVSYS_PRESC_gm 0x07 /* Prescaler group mask. */ -+#define EVSYS_PRESC_gp 0 /* Prescaler group position. */ -+#define EVSYS_PRESC0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define EVSYS_PRESC0_bp 0 /* Prescaler bit 0 position. */ -+#define EVSYS_PRESC1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define EVSYS_PRESC1_bp 1 /* Prescaler bit 1 position. */ -+#define EVSYS_PRESC2_bm (1<<2) /* Prescaler bit 2 mask. */ -+#define EVSYS_PRESC2_bp 2 /* Prescaler bit 2 position. */ -+ -+/* NVM - Non Volatile Memory Controller */ -+/* NVM.CMD bit masks and bit positions */ -+#define NVM_CMD_gm 0x7F /* Command group mask. */ -+#define NVM_CMD_gp 0 /* Command group position. */ -+#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define NVM_CMD0_bp 0 /* Command bit 0 position. */ -+#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define NVM_CMD1_bp 1 /* Command bit 1 position. */ -+#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ -+#define NVM_CMD2_bp 2 /* Command bit 2 position. */ -+#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ -+#define NVM_CMD3_bp 3 /* Command bit 3 position. */ -+#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ -+#define NVM_CMD4_bp 4 /* Command bit 4 position. */ -+#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ -+#define NVM_CMD5_bp 5 /* Command bit 5 position. */ -+#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ -+#define NVM_CMD6_bp 6 /* Command bit 6 position. */ -+ -+/* NVM.CTRLA bit masks and bit positions */ -+#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ -+#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ -+ -+/* NVM.CTRLB bit masks and bit positions */ -+#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ -+#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ -+ -+#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ -+#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ -+ -+/* NVM.INTCTRL bit masks and bit positions */ -+#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ -+#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ -+#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ -+#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ -+#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ -+#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ -+ -+#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ -+#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ -+#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ -+#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ -+#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ -+#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ -+ -+/* NVM.STATUS bit masks and bit positions */ -+#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ -+#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ -+ -+#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ -+#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ -+ -+#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ -+#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ -+ -+#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ -+#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ -+ -+/* NVM.LOCKBITS bit masks and bit positions */ -+#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* ADC - Analog/Digital Converter */ -+/* ADC_CH.CTRL bit masks and bit positions */ -+#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ -+#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ -+ -+#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ -+#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ -+#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ -+#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ -+#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ -+#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ -+#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ -+#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ -+ -+#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ -+#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ -+#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ -+#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ -+#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ -+#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ -+ -+/* ADC_CH.MUXCTRL bit masks and bit positions */ -+#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC Input group mask. */ -+#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC Input group position. */ -+#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC Input bit 0 mask. */ -+#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC Input bit 0 position. */ -+#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC Input bit 1 mask. */ -+#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC Input bit 1 position. */ -+#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC Input bit 2 mask. */ -+#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC Input bit 2 position. */ -+#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC Input bit 3 mask. */ -+#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC Input bit 3 position. */ -+ -+#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC Input group mask. */ -+#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC Input group position. */ -+#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC Input bit 0 mask. */ -+#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC Input bit 0 position. */ -+#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC Input bit 1 mask. */ -+#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC Input bit 1 position. */ -+#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC Input bit 2 mask. */ -+#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC Input bit 2 position. */ -+#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC Input bit 3 mask. */ -+#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC Input bit 3 position. */ -+ -+#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC Input group mask. */ -+#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC Input group position. */ -+#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC Input bit 0 mask. */ -+#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC Input bit 0 position. */ -+#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC Input bit 1 mask. */ -+#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC Input bit 1 position. */ -+ -+#define ADC_CH_MUXNEGL_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group mask. */ -+#define ADC_CH_MUXNEGL_gp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group position. */ -+#define ADC_CH_MUXNEGL0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 mask. */ -+#define ADC_CH_MUXNEGL0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 position. */ -+#define ADC_CH_MUXNEGL1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 mask. */ -+#define ADC_CH_MUXNEGL1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 position. */ -+ -+#define ADC_CH_MUXNEGH_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group mask. */ -+#define ADC_CH_MUXNEGH_gp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group position. */ -+#define ADC_CH_MUXNEGH0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 mask. */ -+#define ADC_CH_MUXNEGH0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 position. */ -+#define ADC_CH_MUXNEGH1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 mask. */ -+#define ADC_CH_MUXNEGH1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 position. */ -+ -+/* ADC_CH.INTCTRL bit masks and bit positions */ -+#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ -+#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ -+#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ -+#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ -+#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ -+#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ -+ -+#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ -+#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ -+#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ -+#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ -+#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ -+#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ -+ -+/* ADC_CH.INTFLAGS bit masks and bit positions */ -+#define ADC_CH_IF_bm 0x01 /* Channel Interrupt Flag bit mask. */ -+#define ADC_CH_IF_bp 0 /* Channel Interrupt Flag bit position. */ -+ -+/* ADC_CH.SCAN bit masks and bit positions */ -+#define ADC_CH_INPUTOFFSET_gm 0xF0 /* Positive MUX Setting Offset group mask. */ -+#define ADC_CH_INPUTOFFSET_gp 4 /* Positive MUX Setting Offset group position. */ -+#define ADC_CH_INPUTOFFSET0_bm (1<<4) /* Positive MUX Setting Offset bit 0 mask. */ -+#define ADC_CH_INPUTOFFSET0_bp 4 /* Positive MUX Setting Offset bit 0 position. */ -+#define ADC_CH_INPUTOFFSET1_bm (1<<5) /* Positive MUX Setting Offset bit 1 mask. */ -+#define ADC_CH_INPUTOFFSET1_bp 5 /* Positive MUX Setting Offset bit 1 position. */ -+#define ADC_CH_INPUTOFFSET2_bm (1<<6) /* Positive MUX Setting Offset bit 2 mask. */ -+#define ADC_CH_INPUTOFFSET2_bp 6 /* Positive MUX Setting Offset bit 2 position. */ -+#define ADC_CH_INPUTOFFSET3_bm (1<<7) /* Positive MUX Setting Offset bit 3 mask. */ -+#define ADC_CH_INPUTOFFSET3_bp 7 /* Positive MUX Setting Offset bit 3 position. */ -+ -+#define ADC_CH_INPUTSCAN_gm 0x0F /* Number of Channels Included in Scan group mask. */ -+#define ADC_CH_INPUTSCAN_gp 0 /* Number of Channels Included in Scan group position. */ -+#define ADC_CH_INPUTSCAN0_bm (1<<0) /* Number of Channels Included in Scan bit 0 mask. */ -+#define ADC_CH_INPUTSCAN0_bp 0 /* Number of Channels Included in Scan bit 0 position. */ -+#define ADC_CH_INPUTSCAN1_bm (1<<1) /* Number of Channels Included in Scan bit 1 mask. */ -+#define ADC_CH_INPUTSCAN1_bp 1 /* Number of Channels Included in Scan bit 1 position. */ -+#define ADC_CH_INPUTSCAN2_bm (1<<2) /* Number of Channels Included in Scan bit 2 mask. */ -+#define ADC_CH_INPUTSCAN2_bp 2 /* Number of Channels Included in Scan bit 2 position. */ -+#define ADC_CH_INPUTSCAN3_bm (1<<3) /* Number of Channels Included in Scan bit 3 mask. */ -+#define ADC_CH_INPUTSCAN3_bp 3 /* Number of Channels Included in Scan bit 3 position. */ -+ -+/* ADC_CH.CORRCTRL bit masks and bit positions */ -+#define ADC_CH_CORREN_bm 0x01 /* Correction Enable bit mask. */ -+#define ADC_CH_CORREN_bp 0 /* Correction Enable bit position. */ -+ -+/* ADC_CH.OFFSETCORR1 bit masks and bit positions */ -+#define ADC_CH_OFFSETCORR_gm 0x0F /* Offset Correction Byte 1 group mask. */ -+#define ADC_CH_OFFSETCORR_gp 0 /* Offset Correction Byte 1 group position. */ -+#define ADC_CH_OFFSETCORR0_bm (1<<0) /* Offset Correction Byte 1 bit 0 mask. */ -+#define ADC_CH_OFFSETCORR0_bp 0 /* Offset Correction Byte 1 bit 0 position. */ -+#define ADC_CH_OFFSETCORR1_bm (1<<1) /* Offset Correction Byte 1 bit 1 mask. */ -+#define ADC_CH_OFFSETCORR1_bp 1 /* Offset Correction Byte 1 bit 1 position. */ -+#define ADC_CH_OFFSETCORR2_bm (1<<2) /* Offset Correction Byte 1 bit 2 mask. */ -+#define ADC_CH_OFFSETCORR2_bp 2 /* Offset Correction Byte 1 bit 2 position. */ -+#define ADC_CH_OFFSETCORR3_bm (1<<3) /* Offset Correction Byte 1 bit 3 mask. */ -+#define ADC_CH_OFFSETCORR3_bp 3 /* Offset Correction Byte 1 bit 3 position. */ -+ -+/* ADC_CH.GAINCORR1 bit masks and bit positions */ -+#define ADC_CH_GAINCORR_gm 0x0F /* Gain Correction Byte 1 group mask. */ -+#define ADC_CH_GAINCORR_gp 0 /* Gain Correction Byte 1 group position. */ -+#define ADC_CH_GAINCORR0_bm (1<<0) /* Gain Correction Byte 1 bit 0 mask. */ -+#define ADC_CH_GAINCORR0_bp 0 /* Gain Correction Byte 1 bit 0 position. */ -+#define ADC_CH_GAINCORR1_bm (1<<1) /* Gain Correction Byte 1 bit 1 mask. */ -+#define ADC_CH_GAINCORR1_bp 1 /* Gain Correction Byte 1 bit 1 position. */ -+#define ADC_CH_GAINCORR2_bm (1<<2) /* Gain Correction Byte 1 bit 2 mask. */ -+#define ADC_CH_GAINCORR2_bp 2 /* Gain Correction Byte 1 bit 2 position. */ -+#define ADC_CH_GAINCORR3_bm (1<<3) /* Gain Correction Byte 1 bit 3 mask. */ -+#define ADC_CH_GAINCORR3_bp 3 /* Gain Correction Byte 1 bit 3 position. */ -+ -+/* ADC_CH.AVGCTRL bit masks and bit positions */ -+#define ADC_CH_RIGHTSHIFT_gm 0x70 /* Right Shift group mask. */ -+#define ADC_CH_RIGHTSHIFT_gp 4 /* Right Shift group position. */ -+#define ADC_CH_RIGHTSHIFT0_bm (1<<4) /* Right Shift bit 0 mask. */ -+#define ADC_CH_RIGHTSHIFT0_bp 4 /* Right Shift bit 0 position. */ -+#define ADC_CH_RIGHTSHIFT1_bm (1<<5) /* Right Shift bit 1 mask. */ -+#define ADC_CH_RIGHTSHIFT1_bp 5 /* Right Shift bit 1 position. */ -+#define ADC_CH_RIGHTSHIFT2_bm (1<<6) /* Right Shift bit 2 mask. */ -+#define ADC_CH_RIGHTSHIFT2_bp 6 /* Right Shift bit 2 position. */ -+ -+#define ADC_CH_SAMPNUM_gm 0x0F /* Averaged Number of Samples group mask. */ -+#define ADC_CH_SAMPNUM_gp 0 /* Averaged Number of Samples group position. */ -+#define ADC_CH_SAMPNUM0_bm (1<<0) /* Averaged Number of Samples bit 0 mask. */ -+#define ADC_CH_SAMPNUM0_bp 0 /* Averaged Number of Samples bit 0 position. */ -+#define ADC_CH_SAMPNUM1_bm (1<<1) /* Averaged Number of Samples bit 1 mask. */ -+#define ADC_CH_SAMPNUM1_bp 1 /* Averaged Number of Samples bit 1 position. */ -+#define ADC_CH_SAMPNUM2_bm (1<<2) /* Averaged Number of Samples bit 2 mask. */ -+#define ADC_CH_SAMPNUM2_bp 2 /* Averaged Number of Samples bit 2 position. */ -+#define ADC_CH_SAMPNUM3_bm (1<<3) /* Averaged Number of Samples bit 3 mask. */ -+#define ADC_CH_SAMPNUM3_bp 3 /* Averaged Number of Samples bit 3 position. */ -+ -+/* ADC.CTRLA bit masks and bit positions */ -+#define ADC_START_bm 0x04 /* Start Conversion bit mask. */ -+#define ADC_START_bp 2 /* Start Conversion bit position. */ -+ -+#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ -+#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ -+ -+#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ -+#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ -+ -+/* ADC.CTRLB bit masks and bit positions */ -+#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ -+#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ -+#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ -+#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ -+#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ -+#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ -+ -+#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ -+#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ -+ -+#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ -+#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ -+ -+#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ -+#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ -+#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ -+#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ -+#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ -+#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ -+ -+/* ADC.REFCTRL bit masks and bit positions */ -+#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ -+#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ -+#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ -+#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ -+#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ -+#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ -+#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ -+#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ -+ -+#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ -+#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ -+ -+#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ -+#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ -+ -+/* ADC.EVCTRL bit masks and bit positions */ -+#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ -+#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ -+#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ -+#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ -+#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ -+#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ -+#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ -+#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ -+ -+#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ -+#define ADC_EVACT_gp 0 /* Event Action Select group position. */ -+#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ -+#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ -+#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ -+#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ -+#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ -+#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ -+ -+/* ADC.PRESCALER bit masks and bit positions */ -+#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ -+#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ -+#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ -+#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ -+#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ -+#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ -+#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ -+#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ -+ -+/* ADC.INTFLAGS bit masks and bit positions */ -+#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ -+#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ -+ -+/* ADC.SAMPCTRL bit masks and bit positions */ -+#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ -+#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ -+#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ -+#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ -+#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ -+#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ -+#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ -+#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ -+#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ -+#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ -+#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ -+#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ -+#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ -+#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ -+ -+/* DAC - Digital/Analog Converter */ -+/* DAC.CTRLA bit masks and bit positions */ -+#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ -+#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ -+ -+#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ -+#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ -+ -+#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ -+#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ -+ -+#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ -+#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ -+ -+#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define DAC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* DAC.CTRLB bit masks and bit positions */ -+#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ -+#define DAC_CHSEL_gp 5 /* Channel Select group position. */ -+#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ -+#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ -+#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ -+#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ -+ -+#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ -+#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ -+ -+#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ -+#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ -+ -+/* DAC.CTRLC bit masks and bit positions */ -+#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ -+#define DAC_REFSEL_gp 3 /* Reference Select group position. */ -+#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ -+#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ -+#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ -+#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ -+ -+#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ -+#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ -+ -+/* DAC.EVCTRL bit masks and bit positions */ -+#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ -+#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ -+ -+#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ -+#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ -+#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ -+#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ -+#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ -+#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ -+#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ -+#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ -+ -+/* DAC.STATUS bit masks and bit positions */ -+#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ -+#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ -+ -+#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ -+#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ -+ -+/* DAC.CH0GAINCAL bit masks and bit positions */ -+#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -+#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ -+#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -+#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -+#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -+#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -+#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -+#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -+#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -+#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -+#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -+#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -+#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -+#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -+#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -+#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ -+ -+/* DAC.CH0OFFSETCAL bit masks and bit positions */ -+#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -+#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ -+#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -+#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -+#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -+#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -+#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -+#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -+#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -+#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -+#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -+#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -+#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -+#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -+#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -+#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ -+ -+/* DAC.CH1GAINCAL bit masks and bit positions */ -+#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ -+#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ -+#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ -+#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ -+#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ -+#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ -+#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ -+#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ -+#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ -+#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ -+#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ -+#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ -+#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ -+#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ -+#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ -+#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ -+ -+/* DAC.CH1OFFSETCAL bit masks and bit positions */ -+#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ -+#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ -+#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ -+#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ -+#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ -+#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ -+#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ -+#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ -+#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ -+#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ -+#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ -+#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ -+#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ -+#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ -+#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ -+#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ -+ -+/* AC - Analog Comparator */ -+/* AC.AC0CTRL bit masks and bit positions */ -+#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ -+#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ -+#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ -+#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ -+#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ -+#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ -+ -+#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ -+#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ -+#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ -+#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ -+#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ -+#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ -+ -+#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ -+#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ -+#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ -+#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ -+#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ -+#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ -+ -+#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ -+#define AC_ENABLE_bp 0 /* Enable bit position. */ -+ -+/* AC.AC1CTRL bit masks and bit positions */ -+/* AC_INTMODE Predefined. */ -+/* AC_INTMODE Predefined. */ -+ -+/* AC_INTLVL Predefined. */ -+/* AC_INTLVL Predefined. */ -+ -+/* AC_HYSMODE Predefined. */ -+/* AC_HYSMODE Predefined. */ -+ -+/* AC_ENABLE Predefined. */ -+/* AC_ENABLE Predefined. */ -+ -+/* AC.AC0MUXCTRL bit masks and bit positions */ -+#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ -+#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ -+#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ -+#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ -+#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ -+#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ -+#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ -+#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ -+ -+#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ -+#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ -+#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ -+#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ -+#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ -+#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ -+#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ -+#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ -+ -+/* AC.AC1MUXCTRL bit masks and bit positions */ -+/* AC_MUXPOS Predefined. */ -+/* AC_MUXPOS Predefined. */ -+ -+/* AC_MUXNEG Predefined. */ -+/* AC_MUXNEG Predefined. */ -+ -+/* AC.CTRLA bit masks and bit positions */ -+#define AC_AC1INVEN_bm 0x08 /* Analog Comparator 1 Output Invert Enable bit mask. */ -+#define AC_AC1INVEN_bp 3 /* Analog Comparator 1 Output Invert Enable bit position. */ -+ -+#define AC_AC0INVEN_bm 0x04 /* Analog Comparator 0 Output Invert Enable bit mask. */ -+#define AC_AC0INVEN_bp 2 /* Analog Comparator 0 Output Invert Enable bit position. */ -+ -+#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ -+#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ -+ -+#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ -+#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ -+ -+/* AC.CTRLB bit masks and bit positions */ -+#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ -+#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ -+#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ -+#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ -+#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ -+#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ -+#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ -+#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ -+#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ -+#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ -+#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ -+#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ -+#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ -+#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ -+ -+/* AC.WINCTRL bit masks and bit positions */ -+#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ -+#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ -+ -+#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ -+#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ -+#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ -+#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ -+#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ -+#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ -+ -+#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ -+#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ -+#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ -+#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ -+#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ -+#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ -+ -+/* AC.STATUS bit masks and bit positions */ -+#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ -+#define AC_WSTATE_gp 6 /* Window Mode State group position. */ -+#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ -+#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ -+#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ -+#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ -+ -+#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ -+#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ -+ -+#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ -+#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ -+ -+#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ -+#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ -+ -+#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ -+#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ -+ -+#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ -+#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ -+ -+/* AC.CURRCTRL bit masks and bit positions */ -+#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ -+#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ -+ -+#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ -+#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ -+ -+#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ -+#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ -+ -+#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ -+#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ -+ -+/* AC.CURRCALIB bit masks and bit positions */ -+#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ -+#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ -+#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ -+#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ -+#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ -+#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ -+#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ -+#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ -+#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ -+#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ -+ -+/* RTC - Real-Time Clounter */ -+/* RTC.CTRL bit masks and bit positions */ -+#define RTC_CORREN_bm 0x08 /* Correction Enable bit mask. */ -+#define RTC_CORREN_bp 3 /* Correction Enable bit position. */ -+ -+#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ -+#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ -+#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ -+#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ -+#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ -+#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ -+#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ -+#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ -+ -+/* RTC.STATUS bit masks and bit positions */ -+#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ -+#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ -+ -+/* RTC.INTCTRL bit masks and bit positions */ -+#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ -+#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ -+#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ -+#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ -+#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ -+#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ -+ -+#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ -+#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ -+#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ -+#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ -+#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ -+#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ -+ -+/* RTC.INTFLAGS bit masks and bit positions */ -+#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ -+#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ -+ -+#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ -+#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ -+ -+/* RTC.CALIB bit masks and bit positions */ -+#define RTC_SIGN_bm 0x80 /* Correction Sign bit mask. */ -+#define RTC_SIGN_bp 7 /* Correction Sign bit position. */ -+ -+#define RTC_ERROR_gm 0x7F /* Error Value group mask. */ -+#define RTC_ERROR_gp 0 /* Error Value group position. */ -+#define RTC_ERROR0_bm (1<<0) /* Error Value bit 0 mask. */ -+#define RTC_ERROR0_bp 0 /* Error Value bit 0 position. */ -+#define RTC_ERROR1_bm (1<<1) /* Error Value bit 1 mask. */ -+#define RTC_ERROR1_bp 1 /* Error Value bit 1 position. */ -+#define RTC_ERROR2_bm (1<<2) /* Error Value bit 2 mask. */ -+#define RTC_ERROR2_bp 2 /* Error Value bit 2 position. */ -+#define RTC_ERROR3_bm (1<<3) /* Error Value bit 3 mask. */ -+#define RTC_ERROR3_bp 3 /* Error Value bit 3 position. */ -+#define RTC_ERROR4_bm (1<<4) /* Error Value bit 4 mask. */ -+#define RTC_ERROR4_bp 4 /* Error Value bit 4 position. */ -+#define RTC_ERROR5_bm (1<<5) /* Error Value bit 5 mask. */ -+#define RTC_ERROR5_bp 5 /* Error Value bit 5 position. */ -+#define RTC_ERROR6_bm (1<<6) /* Error Value bit 6 mask. */ -+#define RTC_ERROR6_bp 6 /* Error Value bit 6 position. */ -+ -+/* XCL - XMEGA Custom Logic */ -+/* XCL.CTRLA bit masks and bit positions */ -+#define XCL_LUT0OUTEN_gm 0xC0 /* LUT0 Output Enable group mask. */ -+#define XCL_LUT0OUTEN_gp 6 /* LUT0 Output Enable group position. */ -+#define XCL_LUT0OUTEN0_bm (1<<6) /* LUT0 Output Enable bit 0 mask. */ -+#define XCL_LUT0OUTEN0_bp 6 /* LUT0 Output Enable bit 0 position. */ -+#define XCL_LUT0OUTEN1_bm (1<<7) /* LUT0 Output Enable bit 1 mask. */ -+#define XCL_LUT0OUTEN1_bp 7 /* LUT0 Output Enable bit 1 position. */ -+ -+#define XCL_PORTSEL_gm 0x30 /* Port Selection group mask. */ -+#define XCL_PORTSEL_gp 4 /* Port Selection group position. */ -+#define XCL_PORTSEL0_bm (1<<4) /* Port Selection bit 0 mask. */ -+#define XCL_PORTSEL0_bp 4 /* Port Selection bit 0 position. */ -+#define XCL_PORTSEL1_bm (1<<5) /* Port Selection bit 1 mask. */ -+#define XCL_PORTSEL1_bp 5 /* Port Selection bit 1 position. */ -+ -+#define XCL_LUTCONF_gm 0x07 /* LUT Configuration group mask. */ -+#define XCL_LUTCONF_gp 0 /* LUT Configuration group position. */ -+#define XCL_LUTCONF0_bm (1<<0) /* LUT Configuration bit 0 mask. */ -+#define XCL_LUTCONF0_bp 0 /* LUT Configuration bit 0 position. */ -+#define XCL_LUTCONF1_bm (1<<1) /* LUT Configuration bit 1 mask. */ -+#define XCL_LUTCONF1_bp 1 /* LUT Configuration bit 1 position. */ -+#define XCL_LUTCONF2_bm (1<<2) /* LUT Configuration bit 2 mask. */ -+#define XCL_LUTCONF2_bp 2 /* LUT Configuration bit 2 position. */ -+ -+/* XCL.CTRLB bit masks and bit positions */ -+#define XCL_IN3SEL_gm 0xC0 /* Input Selection 3 group mask. */ -+#define XCL_IN3SEL_gp 6 /* Input Selection 3 group position. */ -+#define XCL_IN3SEL0_bm (1<<6) /* Input Selection 3 bit 0 mask. */ -+#define XCL_IN3SEL0_bp 6 /* Input Selection 3 bit 0 position. */ -+#define XCL_IN3SEL1_bm (1<<7) /* Input Selection 3 bit 1 mask. */ -+#define XCL_IN3SEL1_bp 7 /* Input Selection 3 bit 1 position. */ -+ -+#define XCL_IN2SEL_gm 0x30 /* Input Selection 2 group mask. */ -+#define XCL_IN2SEL_gp 4 /* Input Selection 2 group position. */ -+#define XCL_IN2SEL0_bm (1<<4) /* Input Selection 2 bit 0 mask. */ -+#define XCL_IN2SEL0_bp 4 /* Input Selection 2 bit 0 position. */ -+#define XCL_IN2SEL1_bm (1<<5) /* Input Selection 2 bit 1 mask. */ -+#define XCL_IN2SEL1_bp 5 /* Input Selection 2 bit 1 position. */ -+ -+#define XCL_IN1SEL_gm 0x0C /* Input Selection 1 group mask. */ -+#define XCL_IN1SEL_gp 2 /* Input Selection 1 group position. */ -+#define XCL_IN1SEL0_bm (1<<2) /* Input Selection 1 bit 0 mask. */ -+#define XCL_IN1SEL0_bp 2 /* Input Selection 1 bit 0 position. */ -+#define XCL_IN1SEL1_bm (1<<3) /* Input Selection 1 bit 1 mask. */ -+#define XCL_IN1SEL1_bp 3 /* Input Selection 1 bit 1 position. */ -+ -+#define XCL_IN0SEL_gm 0x03 /* Input Selection 0 group mask. */ -+#define XCL_IN0SEL_gp 0 /* Input Selection 0 group position. */ -+#define XCL_IN0SEL0_bm (1<<0) /* Input Selection 0 bit 0 mask. */ -+#define XCL_IN0SEL0_bp 0 /* Input Selection 0 bit 0 position. */ -+#define XCL_IN0SEL1_bm (1<<1) /* Input Selection 0 bit 1 mask. */ -+#define XCL_IN0SEL1_bp 1 /* Input Selection 0 bit 1 position. */ -+ -+/* XCL.CTRLC bit masks and bit positions */ -+#define XCL_EVASYSEL1_bm 0x80 /* Asynchronous Event Line Selection for LUT1 bit mask. */ -+#define XCL_EVASYSEL1_bp 7 /* Asynchronous Event Line Selection for LUT1 bit position. */ -+ -+#define XCL_EVASYSEL0_bm 0x40 /* Asynchronous Event Line Selection for LUT0 bit mask. */ -+#define XCL_EVASYSEL0_bp 6 /* Asynchronous Event Line Selection for LUT0 bit position. */ -+ -+#define XCL_DLYSEL_gm 0x30 /* Delay Selection group mask. */ -+#define XCL_DLYSEL_gp 4 /* Delay Selection group position. */ -+#define XCL_DLYSEL0_bm (1<<4) /* Delay Selection bit 0 mask. */ -+#define XCL_DLYSEL0_bp 4 /* Delay Selection bit 0 position. */ -+#define XCL_DLYSEL1_bm (1<<5) /* Delay Selection bit 1 mask. */ -+#define XCL_DLYSEL1_bp 5 /* Delay Selection bit 1 position. */ -+ -+#define XCL_DLY1CONF_gm 0x0C /* Delay Configuration on LUT1 group mask. */ -+#define XCL_DLY1CONF_gp 2 /* Delay Configuration on LUT1 group position. */ -+#define XCL_DLY1CONF0_bm (1<<2) /* Delay Configuration on LUT1 bit 0 mask. */ -+#define XCL_DLY1CONF0_bp 2 /* Delay Configuration on LUT1 bit 0 position. */ -+#define XCL_DLY1CONF1_bm (1<<3) /* Delay Configuration on LUT1 bit 1 mask. */ -+#define XCL_DLY1CONF1_bp 3 /* Delay Configuration on LUT1 bit 1 position. */ -+ -+#define XCL_DLY0CONF_gm 0x03 /* Delay Configuration on LUT0 group mask. */ -+#define XCL_DLY0CONF_gp 0 /* Delay Configuration on LUT0 group position. */ -+#define XCL_DLY0CONF0_bm (1<<0) /* Delay Configuration on LUT0 bit 0 mask. */ -+#define XCL_DLY0CONF0_bp 0 /* Delay Configuration on LUT0 bit 0 position. */ -+#define XCL_DLY0CONF1_bm (1<<1) /* Delay Configuration on LUT0 bit 1 mask. */ -+#define XCL_DLY0CONF1_bp 1 /* Delay Configuration on LUT0 bit 1 position. */ -+ -+/* XCL.CTRLD bit masks and bit positions */ -+#define XCL_TRUTH1_gm 0xF0 /* Truth Table of LUT1 group mask. */ -+#define XCL_TRUTH1_gp 4 /* Truth Table of LUT1 group position. */ -+#define XCL_TRUTH10_bm (1<<4) /* Truth Table of LUT1 bit 0 mask. */ -+#define XCL_TRUTH10_bp 4 /* Truth Table of LUT1 bit 0 position. */ -+#define XCL_TRUTH11_bm (1<<5) /* Truth Table of LUT1 bit 1 mask. */ -+#define XCL_TRUTH11_bp 5 /* Truth Table of LUT1 bit 1 position. */ -+#define XCL_TRUTH12_bm (1<<6) /* Truth Table of LUT1 bit 2 mask. */ -+#define XCL_TRUTH12_bp 6 /* Truth Table of LUT1 bit 2 position. */ -+#define XCL_TRUTH13_bm (1<<7) /* Truth Table of LUT1 bit 3 mask. */ -+#define XCL_TRUTH13_bp 7 /* Truth Table of LUT1 bit 3 position. */ -+ -+#define XCL_TRUTH0_gm 0x0F /* Truth Table of LUT0 group mask. */ -+#define XCL_TRUTH0_gp 0 /* Truth Table of LUT0 group position. */ -+#define XCL_TRUTH00_bm (1<<0) /* Truth Table of LUT0 bit 0 mask. */ -+#define XCL_TRUTH00_bp 0 /* Truth Table of LUT0 bit 0 position. */ -+#define XCL_TRUTH01_bm (1<<1) /* Truth Table of LUT0 bit 1 mask. */ -+#define XCL_TRUTH01_bp 1 /* Truth Table of LUT0 bit 1 position. */ -+#define XCL_TRUTH02_bm (1<<2) /* Truth Table of LUT0 bit 2 mask. */ -+#define XCL_TRUTH02_bp 2 /* Truth Table of LUT0 bit 2 position. */ -+#define XCL_TRUTH03_bm (1<<3) /* Truth Table of LUT0 bit 3 mask. */ -+#define XCL_TRUTH03_bp 3 /* Truth Table of LUT0 bit 3 position. */ -+ -+/* XCL.CTRLE bit masks and bit positions */ -+#define XCL_CMDSEL_bm 0x80 /* Timer/Counter Command Selection bit mask. */ -+#define XCL_CMDSEL_bp 7 /* Timer/Counter Command Selection bit position. */ -+ -+#define XCL_TCSEL_gm 0x70 /* Timer/Counter Selection group mask. */ -+#define XCL_TCSEL_gp 4 /* Timer/Counter Selection group position. */ -+#define XCL_TCSEL0_bm (1<<4) /* Timer/Counter Selection bit 0 mask. */ -+#define XCL_TCSEL0_bp 4 /* Timer/Counter Selection bit 0 position. */ -+#define XCL_TCSEL1_bm (1<<5) /* Timer/Counter Selection bit 1 mask. */ -+#define XCL_TCSEL1_bp 5 /* Timer/Counter Selection bit 1 position. */ -+#define XCL_TCSEL2_bm (1<<6) /* Timer/Counter Selection bit 2 mask. */ -+#define XCL_TCSEL2_bp 6 /* Timer/Counter Selection bit 2 position. */ -+ -+#define XCL_CLKSEL_gm 0x0F /* Clock Selection group mask. */ -+#define XCL_CLKSEL_gp 0 /* Clock Selection group position. */ -+#define XCL_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ -+#define XCL_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ -+#define XCL_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ -+#define XCL_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ -+#define XCL_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ -+#define XCL_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ -+#define XCL_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ -+#define XCL_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ -+ -+/* XCL.CTRLF bit masks and bit positions */ -+#define XCL_CMDEN_gm 0xC0 /* Command Enable group mask. */ -+#define XCL_CMDEN_gp 6 /* Command Enable group position. */ -+#define XCL_CMDEN0_bm (1<<6) /* Command Enable bit 0 mask. */ -+#define XCL_CMDEN0_bp 6 /* Command Enable bit 0 position. */ -+#define XCL_CMDEN1_bm (1<<7) /* Command Enable bit 1 mask. */ -+#define XCL_CMDEN1_bp 7 /* Command Enable bit 1 position. */ -+ -+#define XCL_CMP1_bm 0x20 /* Compare Channel 1 Output Value bit mask. */ -+#define XCL_CMP1_bp 5 /* Compare Channel 1 Output Value bit position. */ -+ -+#define XCL_CMP0_bm 0x10 /* Compare Channel 0 Output Value bit mask. */ -+#define XCL_CMP0_bp 4 /* Compare Channel 0 Output Value bit position. */ -+ -+#define XCL_CCEN1_bm 0x08 /* Compare or Capture Channel 1 Enable bit mask. */ -+#define XCL_CCEN1_bp 3 /* Compare or Capture Channel 1 Enable bit position. */ -+ -+#define XCL_CCEN0_bm 0x04 /* Compare or Capture Channel 0 Enable bit mask. */ -+#define XCL_CCEN0_bp 2 /* Compare or Capture Channel 0 Enable bit position. */ -+ -+#define XCL_MODE_gm 0x03 /* Timer/Counter Mode group mask. */ -+#define XCL_MODE_gp 0 /* Timer/Counter Mode group position. */ -+#define XCL_MODE0_bm (1<<0) /* Timer/Counter Mode bit 0 mask. */ -+#define XCL_MODE0_bp 0 /* Timer/Counter Mode bit 0 position. */ -+#define XCL_MODE1_bm (1<<1) /* Timer/Counter Mode bit 1 mask. */ -+#define XCL_MODE1_bp 1 /* Timer/Counter Mode bit 1 position. */ -+ -+/* XCL.CTRLG bit masks and bit positions */ -+#define XCL_EVACTEN_bm 0x80 /* Event Action Enable bit mask. */ -+#define XCL_EVACTEN_bp 7 /* Event Action Enable bit position. */ -+ -+#define XCL_EVACT1_gm 0x60 /* Event Action Selection on Timer/Counter 1 group mask. */ -+#define XCL_EVACT1_gp 5 /* Event Action Selection on Timer/Counter 1 group position. */ -+#define XCL_EVACT10_bm (1<<5) /* Event Action Selection on Timer/Counter 1 bit 0 mask. */ -+#define XCL_EVACT10_bp 5 /* Event Action Selection on Timer/Counter 1 bit 0 position. */ -+#define XCL_EVACT11_bm (1<<6) /* Event Action Selection on Timer/Counter 1 bit 1 mask. */ -+#define XCL_EVACT11_bp 6 /* Event Action Selection on Timer/Counter 1 bit 1 position. */ -+ -+#define XCL_EVACT0_gm 0x18 /* Event Action Selection on Timer/Counter 0 group mask. */ -+#define XCL_EVACT0_gp 3 /* Event Action Selection on Timer/Counter 0 group position. */ -+#define XCL_EVACT00_bm (1<<3) /* Event Action Selection on Timer/Counter 0 bit 0 mask. */ -+#define XCL_EVACT00_bp 3 /* Event Action Selection on Timer/Counter 0 bit 0 position. */ -+#define XCL_EVACT01_bm (1<<4) /* Event Action Selection on Timer/Counter 0 bit 1 mask. */ -+#define XCL_EVACT01_bp 4 /* Event Action Selection on Timer/Counter 0 bit 1 position. */ -+ -+#define XCL_EVSRC_gm 0x07 /* Event Source Selection group mask. */ -+#define XCL_EVSRC_gp 0 /* Event Source Selection group position. */ -+#define XCL_EVSRC0_bm (1<<0) /* Event Source Selection bit 0 mask. */ -+#define XCL_EVSRC0_bp 0 /* Event Source Selection bit 0 position. */ -+#define XCL_EVSRC1_bm (1<<1) /* Event Source Selection bit 1 mask. */ -+#define XCL_EVSRC1_bp 1 /* Event Source Selection bit 1 position. */ -+#define XCL_EVSRC2_bm (1<<2) /* Event Source Selection bit 2 mask. */ -+#define XCL_EVSRC2_bp 2 /* Event Source Selection bit 2 position. */ -+ -+/* XCL.INTCTRL bit masks and bit positions */ -+#define XCL_UNF1IE_bm 0x80 /* Underflow 1 Interrupt Enable bit mask. */ -+#define XCL_UNF1IE_bp 7 /* Underflow 1 Interrupt Enable bit position. */ -+ -+#define XCL_PEC1IE_bm 0x80 /* Peripheral Counter 1 Interrupt Enable bit mask. */ -+#define XCL_PEC1IE_bp 7 /* Peripheral Counter 1 Interrupt Enable bit position. */ -+ -+#define XCL_PEC21IE_bm 0x80 /* Peripheral High Counter 2 Interrupt Enable bit mask. */ -+#define XCL_PEC21IE_bp 7 /* Peripheral High Counter 2 Interrupt Enable bit position. */ -+ -+#define XCL_UNF0IE_bm 0x40 /* Underflow 0 Interrupt Enable bit mask. */ -+#define XCL_UNF0IE_bp 6 /* Underflow 0 Interrupt Enable bit position. */ -+ -+#define XCL_PEC0IE_bm 0x40 /* Peripheral Counter 0 Interrupt Enable bit mask. */ -+#define XCL_PEC0IE_bp 6 /* Peripheral Counter 0 Interrupt Enable bit position. */ -+ -+#define XCL_CC1IE_bm 0x20 /* Compare Or Capture 1 Interrupt Enable bit mask. */ -+#define XCL_CC1IE_bp 5 /* Compare Or Capture 1 Interrupt Enable bit position. */ -+ -+#define XCL_PEC20IE_bm 0x20 /* Peripheral Low Counter 2 Interrupt Enable bit mask. */ -+#define XCL_PEC20IE_bp 5 /* Peripheral Low Counter 2 Interrupt Enable bit position. */ -+ -+#define XCL_CC0IE_bm 0x10 /* Compare Or Capture 0 Interrupt Enable bit mask. */ -+#define XCL_CC0IE_bp 4 /* Compare Or Capture 0 Interrupt Enable bit position. */ -+ -+#define XCL_UNFINTLVL_gm 0x0C /* Timer Underflow Interrupt Level group mask. */ -+#define XCL_UNFINTLVL_gp 2 /* Timer Underflow Interrupt Level group position. */ -+#define XCL_UNFINTLVL0_bm (1<<2) /* Timer Underflow Interrupt Level bit 0 mask. */ -+#define XCL_UNFINTLVL0_bp 2 /* Timer Underflow Interrupt Level bit 0 position. */ -+#define XCL_UNFINTLVL1_bm (1<<3) /* Timer Underflow Interrupt Level bit 1 mask. */ -+#define XCL_UNFINTLVL1_bp 3 /* Timer Underflow Interrupt Level bit 1 position. */ -+ -+#define XCL_CCINTLVL_gm 0x03 /* Timer Compare or Capture Interrupt Level group mask. */ -+#define XCL_CCINTLVL_gp 0 /* Timer Compare or Capture Interrupt Level group position. */ -+#define XCL_CCINTLVL0_bm (1<<0) /* Timer Compare or Capture Interrupt Level bit 0 mask. */ -+#define XCL_CCINTLVL0_bp 0 /* Timer Compare or Capture Interrupt Level bit 0 position. */ -+#define XCL_CCINTLVL1_bm (1<<1) /* Timer Compare or Capture Interrupt Level bit 1 mask. */ -+#define XCL_CCINTLVL1_bp 1 /* Timer Compare or Capture Interrupt Level bit 1 position. */ -+ -+/* XCL.INTFLAGS bit masks and bit positions */ -+#define XCL_UNF1IF_bm 0x80 /* Timer/Counter 1 Underflow Interrupt Flag bit mask. */ -+#define XCL_UNF1IF_bp 7 /* Timer/Counter 1 Underflow Interrupt Flag bit position. */ -+ -+#define XCL_PEC1IF_bm 0x80 /* Peripheral Counter 1 Interrupt Flag bit mask. */ -+#define XCL_PEC1IF_bp 7 /* Peripheral Counter 1 Interrupt Flag bit position. */ -+ -+#define XCL_PEC21IF_bm 0x80 /* Peripheral High Counter 2 Interrupt Flag bit mask. */ -+#define XCL_PEC21IF_bp 7 /* Peripheral High Counter 2 Interrupt Flag bit position. */ -+ -+#define XCL_UNF0IF_bm 0x40 /* Timer/Counter 0 Underflow Interrupt Flag bit mask. */ -+#define XCL_UNF0IF_bp 6 /* Timer/Counter 0 Underflow Interrupt Flag bit position. */ -+ -+#define XCL_PEC0IF_bm 0x40 /* Peripheral Counter 0 Interrupt Flag bit mask. */ -+#define XCL_PEC0IF_bp 6 /* Peripheral Counter 0 Interrupt Flag bit position. */ -+ -+#define XCL_CC1IF_bm 0x20 /* Compare or Capture Channel 1 Interrupt Flag bit mask. */ -+#define XCL_CC1IF_bp 5 /* Compare or Capture Channel 1 Interrupt Flag bit position. */ -+ -+#define XCL_PEC20IF_bm 0x20 /* Peripheral Low Counter 2 Interrupt Flag bit mask. */ -+#define XCL_PEC20IF_bp 5 /* Peripheral Low Counter 2 Interrupt Flag bit position. */ -+ -+#define XCL_CC0IF_bm 0x10 /* Compare or Capture Channel 0 Interrupt Flag bit mask. */ -+#define XCL_CC0IF_bp 4 /* Compare or Capture Channel 0 Interrupt Flag bit position. */ -+ -+/* XCL.PLC bit masks and bit positions */ -+#define XCL_PLC_gm 0xFF /* Peripheral Lenght Control Bits group mask. */ -+#define XCL_PLC_gp 0 /* Peripheral Lenght Control Bits group position. */ -+#define XCL_PLC0_bm (1<<0) /* Peripheral Lenght Control Bits bit 0 mask. */ -+#define XCL_PLC0_bp 0 /* Peripheral Lenght Control Bits bit 0 position. */ -+#define XCL_PLC1_bm (1<<1) /* Peripheral Lenght Control Bits bit 1 mask. */ -+#define XCL_PLC1_bp 1 /* Peripheral Lenght Control Bits bit 1 position. */ -+#define XCL_PLC2_bm (1<<2) /* Peripheral Lenght Control Bits bit 2 mask. */ -+#define XCL_PLC2_bp 2 /* Peripheral Lenght Control Bits bit 2 position. */ -+#define XCL_PLC3_bm (1<<3) /* Peripheral Lenght Control Bits bit 3 mask. */ -+#define XCL_PLC3_bp 3 /* Peripheral Lenght Control Bits bit 3 position. */ -+#define XCL_PLC4_bm (1<<4) /* Peripheral Lenght Control Bits bit 4 mask. */ -+#define XCL_PLC4_bp 4 /* Peripheral Lenght Control Bits bit 4 position. */ -+#define XCL_PLC5_bm (1<<5) /* Peripheral Lenght Control Bits bit 5 mask. */ -+#define XCL_PLC5_bp 5 /* Peripheral Lenght Control Bits bit 5 position. */ -+#define XCL_PLC6_bm (1<<6) /* Peripheral Lenght Control Bits bit 6 mask. */ -+#define XCL_PLC6_bp 6 /* Peripheral Lenght Control Bits bit 6 position. */ -+#define XCL_PLC7_bm (1<<7) /* Peripheral Lenght Control Bits bit 7 mask. */ -+#define XCL_PLC7_bp 7 /* Peripheral Lenght Control Bits bit 7 position. */ -+ -+/* XCL.CNTL bit masks and bit positions */ -+#define XCL_BCNTO_gm 0xFF /* BTC0 Counter Byte group mask. */ -+#define XCL_BCNTO_gp 0 /* BTC0 Counter Byte group position. */ -+#define XCL_BCNTO0_bm (1<<0) /* BTC0 Counter Byte bit 0 mask. */ -+#define XCL_BCNTO0_bp 0 /* BTC0 Counter Byte bit 0 position. */ -+#define XCL_BCNTO1_bm (1<<1) /* BTC0 Counter Byte bit 1 mask. */ -+#define XCL_BCNTO1_bp 1 /* BTC0 Counter Byte bit 1 position. */ -+#define XCL_BCNTO2_bm (1<<2) /* BTC0 Counter Byte bit 2 mask. */ -+#define XCL_BCNTO2_bp 2 /* BTC0 Counter Byte bit 2 position. */ -+#define XCL_BCNTO3_bm (1<<3) /* BTC0 Counter Byte bit 3 mask. */ -+#define XCL_BCNTO3_bp 3 /* BTC0 Counter Byte bit 3 position. */ -+#define XCL_BCNTO4_bm (1<<4) /* BTC0 Counter Byte bit 4 mask. */ -+#define XCL_BCNTO4_bp 4 /* BTC0 Counter Byte bit 4 position. */ -+#define XCL_BCNTO5_bm (1<<5) /* BTC0 Counter Byte bit 5 mask. */ -+#define XCL_BCNTO5_bp 5 /* BTC0 Counter Byte bit 5 position. */ -+#define XCL_BCNTO6_bm (1<<6) /* BTC0 Counter Byte bit 6 mask. */ -+#define XCL_BCNTO6_bp 6 /* BTC0 Counter Byte bit 6 position. */ -+#define XCL_BCNTO7_bm (1<<7) /* BTC0 Counter Byte bit 7 mask. */ -+#define XCL_BCNTO7_bp 7 /* BTC0 Counter Byte bit 7 position. */ -+ -+#define XCL_CNTL_gm 0xFF /* TC16 Counter Low Byte group mask. */ -+#define XCL_CNTL_gp 0 /* TC16 Counter Low Byte group position. */ -+#define XCL_CNTL0_bm (1<<0) /* TC16 Counter Low Byte bit 0 mask. */ -+#define XCL_CNTL0_bp 0 /* TC16 Counter Low Byte bit 0 position. */ -+#define XCL_CNTL1_bm (1<<1) /* TC16 Counter Low Byte bit 1 mask. */ -+#define XCL_CNTL1_bp 1 /* TC16 Counter Low Byte bit 1 position. */ -+#define XCL_CNTL2_bm (1<<2) /* TC16 Counter Low Byte bit 2 mask. */ -+#define XCL_CNTL2_bp 2 /* TC16 Counter Low Byte bit 2 position. */ -+#define XCL_CNTL3_bm (1<<3) /* TC16 Counter Low Byte bit 3 mask. */ -+#define XCL_CNTL3_bp 3 /* TC16 Counter Low Byte bit 3 position. */ -+#define XCL_CNTL4_bm (1<<4) /* TC16 Counter Low Byte bit 4 mask. */ -+#define XCL_CNTL4_bp 4 /* TC16 Counter Low Byte bit 4 position. */ -+#define XCL_CNTL5_bm (1<<5) /* TC16 Counter Low Byte bit 5 mask. */ -+#define XCL_CNTL5_bp 5 /* TC16 Counter Low Byte bit 5 position. */ -+#define XCL_CNTL6_bm (1<<6) /* TC16 Counter Low Byte bit 6 mask. */ -+#define XCL_CNTL6_bp 6 /* TC16 Counter Low Byte bit 6 position. */ -+#define XCL_CNTL7_bm (1<<7) /* TC16 Counter Low Byte bit 7 mask. */ -+#define XCL_CNTL7_bp 7 /* TC16 Counter Low Byte bit 7 position. */ -+ -+#define XCL_PCNTO_gm 0xFF /* Peripheral Counter 0 Byte group mask. */ -+#define XCL_PCNTO_gp 0 /* Peripheral Counter 0 Byte group position. */ -+#define XCL_PCNTO0_bm (1<<0) /* Peripheral Counter 0 Byte bit 0 mask. */ -+#define XCL_PCNTO0_bp 0 /* Peripheral Counter 0 Byte bit 0 position. */ -+#define XCL_PCNTO1_bm (1<<1) /* Peripheral Counter 0 Byte bit 1 mask. */ -+#define XCL_PCNTO1_bp 1 /* Peripheral Counter 0 Byte bit 1 position. */ -+#define XCL_PCNTO2_bm (1<<2) /* Peripheral Counter 0 Byte bit 2 mask. */ -+#define XCL_PCNTO2_bp 2 /* Peripheral Counter 0 Byte bit 2 position. */ -+#define XCL_PCNTO3_bm (1<<3) /* Peripheral Counter 0 Byte bit 3 mask. */ -+#define XCL_PCNTO3_bp 3 /* Peripheral Counter 0 Byte bit 3 position. */ -+#define XCL_PCNTO4_bm (1<<4) /* Peripheral Counter 0 Byte bit 4 mask. */ -+#define XCL_PCNTO4_bp 4 /* Peripheral Counter 0 Byte bit 4 position. */ -+#define XCL_PCNTO5_bm (1<<5) /* Peripheral Counter 0 Byte bit 5 mask. */ -+#define XCL_PCNTO5_bp 5 /* Peripheral Counter 0 Byte bit 5 position. */ -+#define XCL_PCNTO6_bm (1<<6) /* Peripheral Counter 0 Byte bit 6 mask. */ -+#define XCL_PCNTO6_bp 6 /* Peripheral Counter 0 Byte bit 6 position. */ -+#define XCL_PCNTO7_bm (1<<7) /* Peripheral Counter 0 Byte bit 7 mask. */ -+#define XCL_PCNTO7_bp 7 /* Peripheral Counter 0 Byte bit 7 position. */ -+ -+/* XCL.CNTH bit masks and bit positions */ -+#define XCL_BCNT1_gm 0xFF /* BTC1 Counter Byte group mask. */ -+#define XCL_BCNT1_gp 0 /* BTC1 Counter Byte group position. */ -+#define XCL_BCNT10_bm (1<<0) /* BTC1 Counter Byte bit 0 mask. */ -+#define XCL_BCNT10_bp 0 /* BTC1 Counter Byte bit 0 position. */ -+#define XCL_BCNT11_bm (1<<1) /* BTC1 Counter Byte bit 1 mask. */ -+#define XCL_BCNT11_bp 1 /* BTC1 Counter Byte bit 1 position. */ -+#define XCL_BCNT12_bm (1<<2) /* BTC1 Counter Byte bit 2 mask. */ -+#define XCL_BCNT12_bp 2 /* BTC1 Counter Byte bit 2 position. */ -+#define XCL_BCNT13_bm (1<<3) /* BTC1 Counter Byte bit 3 mask. */ -+#define XCL_BCNT13_bp 3 /* BTC1 Counter Byte bit 3 position. */ -+#define XCL_BCNT14_bm (1<<4) /* BTC1 Counter Byte bit 4 mask. */ -+#define XCL_BCNT14_bp 4 /* BTC1 Counter Byte bit 4 position. */ -+#define XCL_BCNT15_bm (1<<5) /* BTC1 Counter Byte bit 5 mask. */ -+#define XCL_BCNT15_bp 5 /* BTC1 Counter Byte bit 5 position. */ -+#define XCL_BCNT16_bm (1<<6) /* BTC1 Counter Byte bit 6 mask. */ -+#define XCL_BCNT16_bp 6 /* BTC1 Counter Byte bit 6 position. */ -+#define XCL_BCNT17_bm (1<<7) /* BTC1 Counter Byte bit 7 mask. */ -+#define XCL_BCNT17_bp 7 /* BTC1 Counter Byte bit 7 position. */ -+ -+#define XCL_CNTH_gm 0xFF /* TC16 Counter High Byte group mask. */ -+#define XCL_CNTH_gp 0 /* TC16 Counter High Byte group position. */ -+#define XCL_CNTH0_bm (1<<0) /* TC16 Counter High Byte bit 0 mask. */ -+#define XCL_CNTH0_bp 0 /* TC16 Counter High Byte bit 0 position. */ -+#define XCL_CNTH1_bm (1<<1) /* TC16 Counter High Byte bit 1 mask. */ -+#define XCL_CNTH1_bp 1 /* TC16 Counter High Byte bit 1 position. */ -+#define XCL_CNTH2_bm (1<<2) /* TC16 Counter High Byte bit 2 mask. */ -+#define XCL_CNTH2_bp 2 /* TC16 Counter High Byte bit 2 position. */ -+#define XCL_CNTH3_bm (1<<3) /* TC16 Counter High Byte bit 3 mask. */ -+#define XCL_CNTH3_bp 3 /* TC16 Counter High Byte bit 3 position. */ -+#define XCL_CNTH4_bm (1<<4) /* TC16 Counter High Byte bit 4 mask. */ -+#define XCL_CNTH4_bp 4 /* TC16 Counter High Byte bit 4 position. */ -+#define XCL_CNTH5_bm (1<<5) /* TC16 Counter High Byte bit 5 mask. */ -+#define XCL_CNTH5_bp 5 /* TC16 Counter High Byte bit 5 position. */ -+#define XCL_CNTH6_bm (1<<6) /* TC16 Counter High Byte bit 6 mask. */ -+#define XCL_CNTH6_bp 6 /* TC16 Counter High Byte bit 6 position. */ -+#define XCL_CNTH7_bm (1<<7) /* TC16 Counter High Byte bit 7 mask. */ -+#define XCL_CNTH7_bp 7 /* TC16 Counter High Byte bit 7 position. */ -+ -+#define XCL_PCNT1_gm 0xFF /* Peripheral Counter 1 Byte group mask. */ -+#define XCL_PCNT1_gp 0 /* Peripheral Counter 1 Byte group position. */ -+#define XCL_PCNT10_bm (1<<0) /* Peripheral Counter 1 Byte bit 0 mask. */ -+#define XCL_PCNT10_bp 0 /* Peripheral Counter 1 Byte bit 0 position. */ -+#define XCL_PCNT11_bm (1<<1) /* Peripheral Counter 1 Byte bit 1 mask. */ -+#define XCL_PCNT11_bp 1 /* Peripheral Counter 1 Byte bit 1 position. */ -+#define XCL_PCNT12_bm (1<<2) /* Peripheral Counter 1 Byte bit 2 mask. */ -+#define XCL_PCNT12_bp 2 /* Peripheral Counter 1 Byte bit 2 position. */ -+#define XCL_PCNT13_bm (1<<3) /* Peripheral Counter 1 Byte bit 3 mask. */ -+#define XCL_PCNT13_bp 3 /* Peripheral Counter 1 Byte bit 3 position. */ -+#define XCL_PCNT14_bm (1<<4) /* Peripheral Counter 1 Byte bit 4 mask. */ -+#define XCL_PCNT14_bp 4 /* Peripheral Counter 1 Byte bit 4 position. */ -+#define XCL_PCNT15_bm (1<<5) /* Peripheral Counter 1 Byte bit 5 mask. */ -+#define XCL_PCNT15_bp 5 /* Peripheral Counter 1 Byte bit 5 position. */ -+#define XCL_PCNT16_bm (1<<6) /* Peripheral Counter 1 Byte bit 6 mask. */ -+#define XCL_PCNT16_bp 6 /* Peripheral Counter 1 Byte bit 6 position. */ -+#define XCL_PCNT17_bm (1<<7) /* Peripheral Counter 1 Byte bit 7 mask. */ -+#define XCL_PCNT17_bp 7 /* Peripheral Counter 1 Byte bit 7 position. */ -+ -+#define XCL_PCNT21_gm 0xF0 /* Peripheral High Counter 2 Bits group mask. */ -+#define XCL_PCNT21_gp 4 /* Peripheral High Counter 2 Bits group position. */ -+#define XCL_PCNT210_bm (1<<4) /* Peripheral High Counter 2 Bits bit 0 mask. */ -+#define XCL_PCNT210_bp 4 /* Peripheral High Counter 2 Bits bit 0 position. */ -+#define XCL_PCNT211_bm (1<<5) /* Peripheral High Counter 2 Bits bit 1 mask. */ -+#define XCL_PCNT211_bp 5 /* Peripheral High Counter 2 Bits bit 1 position. */ -+#define XCL_PCNT212_bm (1<<6) /* Peripheral High Counter 2 Bits bit 2 mask. */ -+#define XCL_PCNT212_bp 6 /* Peripheral High Counter 2 Bits bit 2 position. */ -+#define XCL_PCNT213_bm (1<<7) /* Peripheral High Counter 2 Bits bit 3 mask. */ -+#define XCL_PCNT213_bp 7 /* Peripheral High Counter 2 Bits bit 3 position. */ -+ -+#define XCL_PCNT20_gm 0x0F /* Peripheral Low Counter 2 Bits group mask. */ -+#define XCL_PCNT20_gp 0 /* Peripheral Low Counter 2 Bits group position. */ -+#define XCL_PCNT200_bm (1<<0) /* Peripheral Low Counter 2 Bits bit 0 mask. */ -+#define XCL_PCNT200_bp 0 /* Peripheral Low Counter 2 Bits bit 0 position. */ -+#define XCL_PCNT201_bm (1<<1) /* Peripheral Low Counter 2 Bits bit 1 mask. */ -+#define XCL_PCNT201_bp 1 /* Peripheral Low Counter 2 Bits bit 1 position. */ -+#define XCL_PCNT202_bm (1<<2) /* Peripheral Low Counter 2 Bits bit 2 mask. */ -+#define XCL_PCNT202_bp 2 /* Peripheral Low Counter 2 Bits bit 2 position. */ -+#define XCL_PCNT203_bm (1<<3) /* Peripheral Low Counter 2 Bits bit 3 mask. */ -+#define XCL_PCNT203_bp 3 /* Peripheral Low Counter 2 Bits bit 3 position. */ -+ -+/* XCL.CMPL bit masks and bit positions */ -+#define XCL_CMPL_gm 0xFF /* TC16 Compare Low Byte group mask. */ -+#define XCL_CMPL_gp 0 /* TC16 Compare Low Byte group position. */ -+#define XCL_CMPL0_bm (1<<0) /* TC16 Compare Low Byte bit 0 mask. */ -+#define XCL_CMPL0_bp 0 /* TC16 Compare Low Byte bit 0 position. */ -+#define XCL_CMPL1_bm (1<<1) /* TC16 Compare Low Byte bit 1 mask. */ -+#define XCL_CMPL1_bp 1 /* TC16 Compare Low Byte bit 1 position. */ -+#define XCL_CMPL2_bm (1<<2) /* TC16 Compare Low Byte bit 2 mask. */ -+#define XCL_CMPL2_bp 2 /* TC16 Compare Low Byte bit 2 position. */ -+#define XCL_CMPL3_bm (1<<3) /* TC16 Compare Low Byte bit 3 mask. */ -+#define XCL_CMPL3_bp 3 /* TC16 Compare Low Byte bit 3 position. */ -+#define XCL_CMPL4_bm (1<<4) /* TC16 Compare Low Byte bit 4 mask. */ -+#define XCL_CMPL4_bp 4 /* TC16 Compare Low Byte bit 4 position. */ -+#define XCL_CMPL5_bm (1<<5) /* TC16 Compare Low Byte bit 5 mask. */ -+#define XCL_CMPL5_bp 5 /* TC16 Compare Low Byte bit 5 position. */ -+#define XCL_CMPL6_bm (1<<6) /* TC16 Compare Low Byte bit 6 mask. */ -+#define XCL_CMPL6_bp 6 /* TC16 Compare Low Byte bit 6 position. */ -+#define XCL_CMPL7_bm (1<<7) /* TC16 Compare Low Byte bit 7 mask. */ -+#define XCL_CMPL7_bp 7 /* TC16 Compare Low Byte bit 7 position. */ -+ -+#define XCL_BCMP0_gm 0xFF /* BTC0 Compare Byte group mask. */ -+#define XCL_BCMP0_gp 0 /* BTC0 Compare Byte group position. */ -+#define XCL_BCMP00_bm (1<<0) /* BTC0 Compare Byte bit 0 mask. */ -+#define XCL_BCMP00_bp 0 /* BTC0 Compare Byte bit 0 position. */ -+#define XCL_BCMP01_bm (1<<1) /* BTC0 Compare Byte bit 1 mask. */ -+#define XCL_BCMP01_bp 1 /* BTC0 Compare Byte bit 1 position. */ -+#define XCL_BCMP02_bm (1<<2) /* BTC0 Compare Byte bit 2 mask. */ -+#define XCL_BCMP02_bp 2 /* BTC0 Compare Byte bit 2 position. */ -+#define XCL_BCMP03_bm (1<<3) /* BTC0 Compare Byte bit 3 mask. */ -+#define XCL_BCMP03_bp 3 /* BTC0 Compare Byte bit 3 position. */ -+#define XCL_BCMP04_bm (1<<4) /* BTC0 Compare Byte bit 4 mask. */ -+#define XCL_BCMP04_bp 4 /* BTC0 Compare Byte bit 4 position. */ -+#define XCL_BCMP05_bm (1<<5) /* BTC0 Compare Byte bit 5 mask. */ -+#define XCL_BCMP05_bp 5 /* BTC0 Compare Byte bit 5 position. */ -+#define XCL_BCMP06_bm (1<<6) /* BTC0 Compare Byte bit 6 mask. */ -+#define XCL_BCMP06_bp 6 /* BTC0 Compare Byte bit 6 position. */ -+#define XCL_BCMP07_bm (1<<7) /* BTC0 Compare Byte bit 7 mask. */ -+#define XCL_BCMP07_bp 7 /* BTC0 Compare Byte bit 7 position. */ -+ -+/* XCL.CMPH bit masks and bit positions */ -+#define XCL_CMPH_gm 0xFF /* TC16 Compare High Byte group mask. */ -+#define XCL_CMPH_gp 0 /* TC16 Compare High Byte group position. */ -+#define XCL_CMPH0_bm (1<<0) /* TC16 Compare High Byte bit 0 mask. */ -+#define XCL_CMPH0_bp 0 /* TC16 Compare High Byte bit 0 position. */ -+#define XCL_CMPH1_bm (1<<1) /* TC16 Compare High Byte bit 1 mask. */ -+#define XCL_CMPH1_bp 1 /* TC16 Compare High Byte bit 1 position. */ -+#define XCL_CMPH2_bm (1<<2) /* TC16 Compare High Byte bit 2 mask. */ -+#define XCL_CMPH2_bp 2 /* TC16 Compare High Byte bit 2 position. */ -+#define XCL_CMPH3_bm (1<<3) /* TC16 Compare High Byte bit 3 mask. */ -+#define XCL_CMPH3_bp 3 /* TC16 Compare High Byte bit 3 position. */ -+#define XCL_CMPH4_bm (1<<4) /* TC16 Compare High Byte bit 4 mask. */ -+#define XCL_CMPH4_bp 4 /* TC16 Compare High Byte bit 4 position. */ -+#define XCL_CMPH5_bm (1<<5) /* TC16 Compare High Byte bit 5 mask. */ -+#define XCL_CMPH5_bp 5 /* TC16 Compare High Byte bit 5 position. */ -+#define XCL_CMPH6_bm (1<<6) /* TC16 Compare High Byte bit 6 mask. */ -+#define XCL_CMPH6_bp 6 /* TC16 Compare High Byte bit 6 position. */ -+#define XCL_CMPH7_bm (1<<7) /* TC16 Compare High Byte bit 7 mask. */ -+#define XCL_CMPH7_bp 7 /* TC16 Compare High Byte bit 7 position. */ -+ -+#define XCL_BCMP1_gm 0xFF /* BTC1 Compare Byte group mask. */ -+#define XCL_BCMP1_gp 0 /* BTC1 Compare Byte group position. */ -+#define XCL_BCMP10_bm (1<<0) /* BTC1 Compare Byte bit 0 mask. */ -+#define XCL_BCMP10_bp 0 /* BTC1 Compare Byte bit 0 position. */ -+#define XCL_BCMP11_bm (1<<1) /* BTC1 Compare Byte bit 1 mask. */ -+#define XCL_BCMP11_bp 1 /* BTC1 Compare Byte bit 1 position. */ -+#define XCL_BCMP12_bm (1<<2) /* BTC1 Compare Byte bit 2 mask. */ -+#define XCL_BCMP12_bp 2 /* BTC1 Compare Byte bit 2 position. */ -+#define XCL_BCMP13_bm (1<<3) /* BTC1 Compare Byte bit 3 mask. */ -+#define XCL_BCMP13_bp 3 /* BTC1 Compare Byte bit 3 position. */ -+#define XCL_BCMP14_bm (1<<4) /* BTC1 Compare Byte bit 4 mask. */ -+#define XCL_BCMP14_bp 4 /* BTC1 Compare Byte bit 4 position. */ -+#define XCL_BCMP15_bm (1<<5) /* BTC1 Compare Byte bit 5 mask. */ -+#define XCL_BCMP15_bp 5 /* BTC1 Compare Byte bit 5 position. */ -+#define XCL_BCMP16_bm (1<<6) /* BTC1 Compare Byte bit 6 mask. */ -+#define XCL_BCMP16_bp 6 /* BTC1 Compare Byte bit 6 position. */ -+#define XCL_BCMP17_bm (1<<7) /* BTC1 Compare Byte bit 7 mask. */ -+#define XCL_BCMP17_bp 7 /* BTC1 Compare Byte bit 7 position. */ -+ -+/* XCL.PERCAPTL bit masks and bit positions */ -+#define XCL_PERL_gm 0xFF /* TC16 Low Byte Period group mask. */ -+#define XCL_PERL_gp 0 /* TC16 Low Byte Period group position. */ -+#define XCL_PERL0_bm (1<<0) /* TC16 Low Byte Period bit 0 mask. */ -+#define XCL_PERL0_bp 0 /* TC16 Low Byte Period bit 0 position. */ -+#define XCL_PERL1_bm (1<<1) /* TC16 Low Byte Period bit 1 mask. */ -+#define XCL_PERL1_bp 1 /* TC16 Low Byte Period bit 1 position. */ -+#define XCL_PERL2_bm (1<<2) /* TC16 Low Byte Period bit 2 mask. */ -+#define XCL_PERL2_bp 2 /* TC16 Low Byte Period bit 2 position. */ -+#define XCL_PERL3_bm (1<<3) /* TC16 Low Byte Period bit 3 mask. */ -+#define XCL_PERL3_bp 3 /* TC16 Low Byte Period bit 3 position. */ -+#define XCL_PERL4_bm (1<<4) /* TC16 Low Byte Period bit 4 mask. */ -+#define XCL_PERL4_bp 4 /* TC16 Low Byte Period bit 4 position. */ -+#define XCL_PERL5_bm (1<<5) /* TC16 Low Byte Period bit 5 mask. */ -+#define XCL_PERL5_bp 5 /* TC16 Low Byte Period bit 5 position. */ -+#define XCL_PERL6_bm (1<<6) /* TC16 Low Byte Period bit 6 mask. */ -+#define XCL_PERL6_bp 6 /* TC16 Low Byte Period bit 6 position. */ -+#define XCL_PERL7_bm (1<<7) /* TC16 Low Byte Period bit 7 mask. */ -+#define XCL_PERL7_bp 7 /* TC16 Low Byte Period bit 7 position. */ -+ -+#define XCL_CAPTL_gm 0xFF /* TC16 Capture Value Low Byte group mask. */ -+#define XCL_CAPTL_gp 0 /* TC16 Capture Value Low Byte group position. */ -+#define XCL_CAPTL0_bm (1<<0) /* TC16 Capture Value Low Byte bit 0 mask. */ -+#define XCL_CAPTL0_bp 0 /* TC16 Capture Value Low Byte bit 0 position. */ -+#define XCL_CAPTL1_bm (1<<1) /* TC16 Capture Value Low Byte bit 1 mask. */ -+#define XCL_CAPTL1_bp 1 /* TC16 Capture Value Low Byte bit 1 position. */ -+#define XCL_CAPTL2_bm (1<<2) /* TC16 Capture Value Low Byte bit 2 mask. */ -+#define XCL_CAPTL2_bp 2 /* TC16 Capture Value Low Byte bit 2 position. */ -+#define XCL_CAPTL3_bm (1<<3) /* TC16 Capture Value Low Byte bit 3 mask. */ -+#define XCL_CAPTL3_bp 3 /* TC16 Capture Value Low Byte bit 3 position. */ -+#define XCL_CAPTL4_bm (1<<4) /* TC16 Capture Value Low Byte bit 4 mask. */ -+#define XCL_CAPTL4_bp 4 /* TC16 Capture Value Low Byte bit 4 position. */ -+#define XCL_CAPTL5_bm (1<<5) /* TC16 Capture Value Low Byte bit 5 mask. */ -+#define XCL_CAPTL5_bp 5 /* TC16 Capture Value Low Byte bit 5 position. */ -+#define XCL_CAPTL6_bm (1<<6) /* TC16 Capture Value Low Byte bit 6 mask. */ -+#define XCL_CAPTL6_bp 6 /* TC16 Capture Value Low Byte bit 6 position. */ -+#define XCL_CAPTL7_bm (1<<7) /* TC16 Capture Value Low Byte bit 7 mask. */ -+#define XCL_CAPTL7_bp 7 /* TC16 Capture Value Low Byte bit 7 position. */ -+ -+#define XCL_BPER0_gm 0xFF /* BTC0 Period group mask. */ -+#define XCL_BPER0_gp 0 /* BTC0 Period group position. */ -+#define XCL_BPER00_bm (1<<0) /* BTC0 Period bit 0 mask. */ -+#define XCL_BPER00_bp 0 /* BTC0 Period bit 0 position. */ -+#define XCL_BPER01_bm (1<<1) /* BTC0 Period bit 1 mask. */ -+#define XCL_BPER01_bp 1 /* BTC0 Period bit 1 position. */ -+#define XCL_BPER02_bm (1<<2) /* BTC0 Period bit 2 mask. */ -+#define XCL_BPER02_bp 2 /* BTC0 Period bit 2 position. */ -+#define XCL_BPER03_bm (1<<3) /* BTC0 Period bit 3 mask. */ -+#define XCL_BPER03_bp 3 /* BTC0 Period bit 3 position. */ -+#define XCL_BPER04_bm (1<<4) /* BTC0 Period bit 4 mask. */ -+#define XCL_BPER04_bp 4 /* BTC0 Period bit 4 position. */ -+#define XCL_BPER05_bm (1<<5) /* BTC0 Period bit 5 mask. */ -+#define XCL_BPER05_bp 5 /* BTC0 Period bit 5 position. */ -+#define XCL_BPER06_bm (1<<6) /* BTC0 Period bit 6 mask. */ -+#define XCL_BPER06_bp 6 /* BTC0 Period bit 6 position. */ -+#define XCL_BPER07_bm (1<<7) /* BTC0 Period bit 7 mask. */ -+#define XCL_BPER07_bp 7 /* BTC0 Period bit 7 position. */ -+ -+#define XCL_BCAPT0_gm 0xFF /* BTC0 Capture Value Byte group mask. */ -+#define XCL_BCAPT0_gp 0 /* BTC0 Capture Value Byte group position. */ -+#define XCL_BCAPT00_bm (1<<0) /* BTC0 Capture Value Byte bit 0 mask. */ -+#define XCL_BCAPT00_bp 0 /* BTC0 Capture Value Byte bit 0 position. */ -+#define XCL_BCAPT01_bm (1<<1) /* BTC0 Capture Value Byte bit 1 mask. */ -+#define XCL_BCAPT01_bp 1 /* BTC0 Capture Value Byte bit 1 position. */ -+#define XCL_BCAPT02_bm (1<<2) /* BTC0 Capture Value Byte bit 2 mask. */ -+#define XCL_BCAPT02_bp 2 /* BTC0 Capture Value Byte bit 2 position. */ -+#define XCL_BCAPT03_bm (1<<3) /* BTC0 Capture Value Byte bit 3 mask. */ -+#define XCL_BCAPT03_bp 3 /* BTC0 Capture Value Byte bit 3 position. */ -+#define XCL_BCAPT04_bm (1<<4) /* BTC0 Capture Value Byte bit 4 mask. */ -+#define XCL_BCAPT04_bp 4 /* BTC0 Capture Value Byte bit 4 position. */ -+#define XCL_BCAPT05_bm (1<<5) /* BTC0 Capture Value Byte bit 5 mask. */ -+#define XCL_BCAPT05_bp 5 /* BTC0 Capture Value Byte bit 5 position. */ -+#define XCL_BCAPT06_bm (1<<6) /* BTC0 Capture Value Byte bit 6 mask. */ -+#define XCL_BCAPT06_bp 6 /* BTC0 Capture Value Byte bit 6 position. */ -+#define XCL_BCAPT07_bm (1<<7) /* BTC0 Capture Value Byte bit 7 mask. */ -+#define XCL_BCAPT07_bp 7 /* BTC0 Capture Value Byte bit 7 position. */ -+ -+/* XCL.PERCAPTH bit masks and bit positions */ -+#define XCL_PERH_gm 0xFF /* TC16 High Byte Period group mask. */ -+#define XCL_PERH_gp 0 /* TC16 High Byte Period group position. */ -+#define XCL_PERH0_bm (1<<0) /* TC16 High Byte Period bit 0 mask. */ -+#define XCL_PERH0_bp 0 /* TC16 High Byte Period bit 0 position. */ -+#define XCL_PERH1_bm (1<<1) /* TC16 High Byte Period bit 1 mask. */ -+#define XCL_PERH1_bp 1 /* TC16 High Byte Period bit 1 position. */ -+#define XCL_PERH2_bm (1<<2) /* TC16 High Byte Period bit 2 mask. */ -+#define XCL_PERH2_bp 2 /* TC16 High Byte Period bit 2 position. */ -+#define XCL_PERH3_bm (1<<3) /* TC16 High Byte Period bit 3 mask. */ -+#define XCL_PERH3_bp 3 /* TC16 High Byte Period bit 3 position. */ -+#define XCL_PERH4_bm (1<<4) /* TC16 High Byte Period bit 4 mask. */ -+#define XCL_PERH4_bp 4 /* TC16 High Byte Period bit 4 position. */ -+#define XCL_PERH5_bm (1<<5) /* TC16 High Byte Period bit 5 mask. */ -+#define XCL_PERH5_bp 5 /* TC16 High Byte Period bit 5 position. */ -+#define XCL_PERH6_bm (1<<6) /* TC16 High Byte Period bit 6 mask. */ -+#define XCL_PERH6_bp 6 /* TC16 High Byte Period bit 6 position. */ -+#define XCL_PERH7_bm (1<<7) /* TC16 High Byte Period bit 7 mask. */ -+#define XCL_PERH7_bp 7 /* TC16 High Byte Period bit 7 position. */ -+ -+#define XCL_CAPTH_gm 0xFF /* TC16 Capture Value High Byte group mask. */ -+#define XCL_CAPTH_gp 0 /* TC16 Capture Value High Byte group position. */ -+#define XCL_CAPTH0_bm (1<<0) /* TC16 Capture Value High Byte bit 0 mask. */ -+#define XCL_CAPTH0_bp 0 /* TC16 Capture Value High Byte bit 0 position. */ -+#define XCL_CAPTH1_bm (1<<1) /* TC16 Capture Value High Byte bit 1 mask. */ -+#define XCL_CAPTH1_bp 1 /* TC16 Capture Value High Byte bit 1 position. */ -+#define XCL_CAPTH2_bm (1<<2) /* TC16 Capture Value High Byte bit 2 mask. */ -+#define XCL_CAPTH2_bp 2 /* TC16 Capture Value High Byte bit 2 position. */ -+#define XCL_CAPTH3_bm (1<<3) /* TC16 Capture Value High Byte bit 3 mask. */ -+#define XCL_CAPTH3_bp 3 /* TC16 Capture Value High Byte bit 3 position. */ -+#define XCL_CAPTH4_bm (1<<4) /* TC16 Capture Value High Byte bit 4 mask. */ -+#define XCL_CAPTH4_bp 4 /* TC16 Capture Value High Byte bit 4 position. */ -+#define XCL_CAPTH5_bm (1<<5) /* TC16 Capture Value High Byte bit 5 mask. */ -+#define XCL_CAPTH5_bp 5 /* TC16 Capture Value High Byte bit 5 position. */ -+#define XCL_CAPTH6_bm (1<<6) /* TC16 Capture Value High Byte bit 6 mask. */ -+#define XCL_CAPTH6_bp 6 /* TC16 Capture Value High Byte bit 6 position. */ -+#define XCL_CAPTH7_bm (1<<7) /* TC16 Capture Value High Byte bit 7 mask. */ -+#define XCL_CAPTH7_bp 7 /* TC16 Capture Value High Byte bit 7 position. */ -+ -+#define XCL_BPER1_gm 0xFF /* BTC1 Period group mask. */ -+#define XCL_BPER1_gp 0 /* BTC1 Period group position. */ -+#define XCL_BPER10_bm (1<<0) /* BTC1 Period bit 0 mask. */ -+#define XCL_BPER10_bp 0 /* BTC1 Period bit 0 position. */ -+#define XCL_BPER11_bm (1<<1) /* BTC1 Period bit 1 mask. */ -+#define XCL_BPER11_bp 1 /* BTC1 Period bit 1 position. */ -+#define XCL_BPER12_bm (1<<2) /* BTC1 Period bit 2 mask. */ -+#define XCL_BPER12_bp 2 /* BTC1 Period bit 2 position. */ -+#define XCL_BPER13_bm (1<<3) /* BTC1 Period bit 3 mask. */ -+#define XCL_BPER13_bp 3 /* BTC1 Period bit 3 position. */ -+#define XCL_BPER14_bm (1<<4) /* BTC1 Period bit 4 mask. */ -+#define XCL_BPER14_bp 4 /* BTC1 Period bit 4 position. */ -+#define XCL_BPER15_bm (1<<5) /* BTC1 Period bit 5 mask. */ -+#define XCL_BPER15_bp 5 /* BTC1 Period bit 5 position. */ -+#define XCL_BPER16_bm (1<<6) /* BTC1 Period bit 6 mask. */ -+#define XCL_BPER16_bp 6 /* BTC1 Period bit 6 position. */ -+#define XCL_BPER17_bm (1<<7) /* BTC1 Period bit 7 mask. */ -+#define XCL_BPER17_bp 7 /* BTC1 Period bit 7 position. */ -+ -+#define XCL_BCAPT1_gm 0xFF /* BTC1 Capture Value Byte group mask. */ -+#define XCL_BCAPT1_gp 0 /* BTC1 Capture Value Byte group position. */ -+#define XCL_BCAPT10_bm (1<<0) /* BTC1 Capture Value Byte bit 0 mask. */ -+#define XCL_BCAPT10_bp 0 /* BTC1 Capture Value Byte bit 0 position. */ -+#define XCL_BCAPT11_bm (1<<1) /* BTC1 Capture Value Byte bit 1 mask. */ -+#define XCL_BCAPT11_bp 1 /* BTC1 Capture Value Byte bit 1 position. */ -+#define XCL_BCAPT12_bm (1<<2) /* BTC1 Capture Value Byte bit 2 mask. */ -+#define XCL_BCAPT12_bp 2 /* BTC1 Capture Value Byte bit 2 position. */ -+#define XCL_BCAPT13_bm (1<<3) /* BTC1 Capture Value Byte bit 3 mask. */ -+#define XCL_BCAPT13_bp 3 /* BTC1 Capture Value Byte bit 3 position. */ -+#define XCL_BCAPT14_bm (1<<4) /* BTC1 Capture Value Byte bit 4 mask. */ -+#define XCL_BCAPT14_bp 4 /* BTC1 Capture Value Byte bit 4 position. */ -+#define XCL_BCAPT15_bm (1<<5) /* BTC1 Capture Value Byte bit 5 mask. */ -+#define XCL_BCAPT15_bp 5 /* BTC1 Capture Value Byte bit 5 position. */ -+#define XCL_BCAPT16_bm (1<<6) /* BTC1 Capture Value Byte bit 6 mask. */ -+#define XCL_BCAPT16_bp 6 /* BTC1 Capture Value Byte bit 6 position. */ -+#define XCL_BCAPT17_bm (1<<7) /* BTC1 Capture Value Byte bit 7 mask. */ -+#define XCL_BCAPT17_bp 7 /* BTC1 Capture Value Byte bit 7 position. */ -+ -+/* TWI - Two-Wire Interface */ -+/* TWI.CTRL bit masks and bit positions */ -+#define TWI_BRIDGEEN_bm 0x80 /* Bridge Enable bit mask. */ -+#define TWI_BRIDGEEN_bp 7 /* Bridge Enable bit position. */ -+ -+#define TWI_SFMPEN_bm 0x40 /* Slave Fast Mode Plus Enable bit mask. */ -+#define TWI_SFMPEN_bp 6 /* Slave Fast Mode Plus Enable bit position. */ -+ -+#define TWI_SSDAHOLD_gm 0x30 /* Slave SDA Hold Time Enable group mask. */ -+#define TWI_SSDAHOLD_gp 4 /* Slave SDA Hold Time Enable group position. */ -+#define TWI_SSDAHOLD0_bm (1<<4) /* Slave SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SSDAHOLD0_bp 4 /* Slave SDA Hold Time Enable bit 0 position. */ -+#define TWI_SSDAHOLD1_bm (1<<5) /* Slave SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SSDAHOLD1_bp 5 /* Slave SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_FMPEN_bm 0x08 /* FMPLUS Enable bit mask. */ -+#define TWI_FMPEN_bp 3 /* FMPLUS Enable bit position. */ -+ -+#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ -+#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ -+#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ -+#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ -+#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ -+#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ -+ -+#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ -+#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ -+ -+/* TWI_MASTER.CTRLA bit masks and bit positions */ -+#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ -+#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ -+#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ -+ -+#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ -+#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ -+ -+/* TWI_MASTER.CTRLB bit masks and bit positions */ -+#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ -+#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ -+#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ -+#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ -+#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ -+#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ -+ -+#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ -+#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ -+ -+#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+#define TWI_MASTER_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ -+#define TWI_MASTER_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ -+ -+#define TWI_MASTER_TSEXTEN_bm 0x20 /* Slave Extend Timeout Enable bit mask. */ -+#define TWI_MASTER_TSEXTEN_bp 5 /* Slave Extend Timeout Enable bit position. */ -+ -+#define TWI_MASTER_TMEXTEN_bm 0x40 /* Master Extend Timeout Enable bit mask. */ -+#define TWI_MASTER_TMEXTEN_bp 6 /* Master Extend Timeout Enable bit position. */ -+ -+#define TWI_MASTER_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ -+#define TWI_MASTER_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ -+ -+/* TWI_MASTER.CTRLC bit masks and bit positions */ -+#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_MASTER_CMD_gp 0 /* Command group position. */ -+#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ -+ -+/* TWI_MASTER.STATUS bit masks and bit positions */ -+#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ -+#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ -+#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ -+ -+#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ -+#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ -+ -+#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ -+#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ -+#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ -+#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ -+#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ -+#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ -+ -+/* TWI_SLAVE.CTRLA bit masks and bit positions */ -+#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ -+#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ -+#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ -+#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ -+#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ -+#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ -+ -+#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ -+#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ -+#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ -+ -+#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ -+#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ -+ -+#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ -+#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ -+ -+#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ -+#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ -+ -+/* TWI_SLAVE.CTRLB bit masks and bit positions */ -+#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ -+#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ -+ -+#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ -+#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ -+#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ -+#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ -+#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ -+#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ -+ -+#define TWI_SLAVE_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ -+#define TWI_SLAVE_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ -+ -+#define TWI_SLAVE_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ -+#define TWI_SLAVE_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ -+ -+/* TWI_SLAVE.STATUS bit masks and bit positions */ -+#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ -+#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ -+#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ -+ -+#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ -+#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ -+ -+#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ -+#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ -+ -+#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ -+#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ -+ -+#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ -+#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ -+ -+#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ -+#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ -+ -+#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ -+#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ -+ -+/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ -+#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ -+#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ -+#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ -+#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ -+#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ -+#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ -+#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ -+#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ -+#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ -+#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ -+#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ -+#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ -+#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ -+#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ -+#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ -+#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ -+ -+#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ -+#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ -+ -+/* TWI_TIMEOUT.TOS bit masks and bit positions */ -+#define TWI_TIMEOUT_TTOUTMIF_bm 0x01 /* Master Ttimeout Interrupt Flag bit mask. */ -+#define TWI_TIMEOUT_TTOUTMIF_bp 0 /* Master Ttimeout Interrupt Flag bit position. */ -+ -+#define TWI_TIMEOUT_TSEXTIF_bm 0x02 /* Slave Extend Interrupt Flag bit mask. */ -+#define TWI_TIMEOUT_TSEXTIF_bp 1 /* Slave Extend Interrupt Flag bit position. */ -+ -+#define TWI_TIMEOUT_TMEXTIF_bm 0x04 /* Master Extend Interrupt Flag bit mask. */ -+#define TWI_TIMEOUT_TMEXTIF_bp 2 /* Master Extend Interrupt Flag bit position. */ -+ -+#define TWI_TIMEOUT_TTOUTSIF_bm 0x10 /* Slave Ttimeout Interrupt Flag bit mask. */ -+#define TWI_TIMEOUT_TTOUTSIF_bp 4 /* Slave Ttimeout Interrupt Flag bit position. */ -+ -+/* TWI_TIMEOUT.TOCONF bit masks and bit positions */ -+#define TWI_TIMEOUT_TTOUTMSEL_gm 0x07 /* Master Ttimeout Select group mask. */ -+#define TWI_TIMEOUT_TTOUTMSEL_gp 0 /* Master Ttimeout Select group position. */ -+#define TWI_TIMEOUT_TTOUTMSEL0_bm (1<<0) /* Master Ttimeout Select bit 0 mask. */ -+#define TWI_TIMEOUT_TTOUTMSEL0_bp 0 /* Master Ttimeout Select bit 0 position. */ -+#define TWI_TIMEOUT_TTOUTMSEL1_bm (1<<1) /* Master Ttimeout Select bit 1 mask. */ -+#define TWI_TIMEOUT_TTOUTMSEL1_bp 1 /* Master Ttimeout Select bit 1 position. */ -+#define TWI_TIMEOUT_TTOUTMSEL2_bm (1<<2) /* Master Ttimeout Select bit 2 mask. */ -+#define TWI_TIMEOUT_TTOUTMSEL2_bp 2 /* Master Ttimeout Select bit 2 position. */ -+ -+#define TWI_TIMEOUT_TMSEXTSEL_gm 0x18 /* Master/Slave Timeout Select group mask. */ -+#define TWI_TIMEOUT_TMSEXTSEL_gp 3 /* Master/Slave Timeout Select group position. */ -+#define TWI_TIMEOUT_TMSEXTSEL0_bm (1<<3) /* Master/Slave Timeout Select bit 0 mask. */ -+#define TWI_TIMEOUT_TMSEXTSEL0_bp 3 /* Master/Slave Timeout Select bit 0 position. */ -+#define TWI_TIMEOUT_TMSEXTSEL1_bm (1<<4) /* Master/Slave Timeout Select bit 1 mask. */ -+#define TWI_TIMEOUT_TMSEXTSEL1_bp 4 /* Master/Slave Timeout Select bit 1 position. */ -+ -+#define TWI_TIMEOUT_TTOUTSSEL_gm 0xE0 /* Slave Ttimeout Select group mask. */ -+#define TWI_TIMEOUT_TTOUTSSEL_gp 5 /* Slave Ttimeout Select group position. */ -+#define TWI_TIMEOUT_TTOUTSSEL0_bm (1<<5) /* Slave Ttimeout Select bit 0 mask. */ -+#define TWI_TIMEOUT_TTOUTSSEL0_bp 5 /* Slave Ttimeout Select bit 0 position. */ -+#define TWI_TIMEOUT_TTOUTSSEL1_bm (1<<6) /* Slave Ttimeout Select bit 1 mask. */ -+#define TWI_TIMEOUT_TTOUTSSEL1_bp 6 /* Slave Ttimeout Select bit 1 position. */ -+#define TWI_TIMEOUT_TTOUTSSEL2_bm (1<<7) /* Slave Ttimeout Select bit 2 mask. */ -+#define TWI_TIMEOUT_TTOUTSSEL2_bp 7 /* Slave Ttimeout Select bit 2 position. */ -+ -+/* PORT - Port Configuration */ -+/* PORT.INTCTRL bit masks and bit positions */ -+#define PORT_INTLVL_gm 0x03 /* Port Interrupt Level group mask. */ -+#define PORT_INTLVL_gp 0 /* Port Interrupt Level group position. */ -+#define PORT_INTLVL0_bm (1<<0) /* Port Interrupt Level bit 0 mask. */ -+#define PORT_INTLVL0_bp 0 /* Port Interrupt Level bit 0 position. */ -+#define PORT_INTLVL1_bm (1<<1) /* Port Interrupt Level bit 1 mask. */ -+#define PORT_INTLVL1_bp 1 /* Port Interrupt Level bit 1 position. */ -+ -+/* PORT.INTFLAGS bit masks and bit positions */ -+#define PORT_INT7IF_bm 0x80 /* Pin 7 Interrupt Flag bit mask. */ -+#define PORT_INT7IF_bp 7 /* Pin 7 Interrupt Flag bit position. */ -+ -+#define PORT_INT6IF_bm 0x40 /* Pin 6 Interrupt Flag bit mask. */ -+#define PORT_INT6IF_bp 6 /* Pin 6 Interrupt Flag bit position. */ -+ -+#define PORT_INT5IF_bm 0x20 /* Pin 5 Interrupt Flag bit mask. */ -+#define PORT_INT5IF_bp 5 /* Pin 5 Interrupt Flag bit position. */ -+ -+#define PORT_INT4IF_bm 0x10 /* Pin 4 Interrupt Flag bit mask. */ -+#define PORT_INT4IF_bp 4 /* Pin 4 Interrupt Flag bit position. */ -+ -+#define PORT_INT3IF_bm 0x08 /* Pin 3 Interrupt Flag bit mask. */ -+#define PORT_INT3IF_bp 3 /* Pin 3 Interrupt Flag bit position. */ -+ -+#define PORT_INT2IF_bm 0x04 /* Pin 2 Interrupt Flag bit mask. */ -+#define PORT_INT2IF_bp 2 /* Pin 2 Interrupt Flag bit position. */ -+ -+#define PORT_INT1IF_bm 0x02 /* Pin 1 Interrupt Flag bit mask. */ -+#define PORT_INT1IF_bp 1 /* Pin 1 Interrupt Flag bit position. */ -+ -+#define PORT_INT0IF_bm 0x01 /* Pin 0 Interrupt Flag bit mask. */ -+#define PORT_INT0IF_bp 0 /* Pin 0 Interrupt Flag bit position. */ -+ -+/* PORT.REMAP bit masks and bit positions */ -+#define PORT_USART0_bm 0x10 /* Usart0 bit mask. */ -+#define PORT_USART0_bp 4 /* Usart0 bit position. */ -+ -+#define PORT_TC4D_bm 0x08 /* Timer/Counter 4 Output Compare D bit mask. */ -+#define PORT_TC4D_bp 3 /* Timer/Counter 4 Output Compare D bit position. */ -+ -+#define PORT_TC4C_bm 0x04 /* Timer/Counter 4 Output Compare C bit mask. */ -+#define PORT_TC4C_bp 2 /* Timer/Counter 4 Output Compare C bit position. */ -+ -+#define PORT_TC4B_bm 0x02 /* Timer/Counter 4 Output Compare B bit mask. */ -+#define PORT_TC4B_bp 1 /* Timer/Counter 4 Output Compare B bit position. */ -+ -+#define PORT_TC4A_bm 0x01 /* Timer/Counter 4 Output Compare A bit mask. */ -+#define PORT_TC4A_bp 0 /* Timer/Counter 4 Output Compare A bit position. */ -+ -+/* PORT.PIN0CTRL bit masks and bit positions */ -+#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ -+#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ -+ -+#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ -+#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ -+#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ -+#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ -+#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ -+#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ -+#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ -+#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ -+ -+#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ -+#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ -+#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ -+#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ -+#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ -+#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ -+#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ -+#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ -+ -+/* PORT.PIN1CTRL bit masks and bit positions */ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN2CTRL bit masks and bit positions */ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN3CTRL bit masks and bit positions */ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN4CTRL bit masks and bit positions */ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN5CTRL bit masks and bit positions */ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN6CTRL bit masks and bit positions */ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* PORT.PIN7CTRL bit masks and bit positions */ -+/* PORT_INVEN Predefined. */ -+/* PORT_INVEN Predefined. */ -+ -+/* PORT_OPC Predefined. */ -+/* PORT_OPC Predefined. */ -+ -+/* PORT_ISC Predefined. */ -+/* PORT_ISC Predefined. */ -+ -+/* TC - 16-bit Timer/Counter With PWM */ -+/* TC4.CTRLA bit masks and bit positions */ -+#define TC4_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ -+#define TC4_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ -+ -+#define TC4_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ -+#define TC4_EVSTART_bp 5 /* Start on Next Event bit position. */ -+ -+#define TC4_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ -+#define TC4_UPSTOP_bp 4 /* Stop on Next Update bit position. */ -+ -+#define TC4_CLKSEL_gm 0x0F /* Clock Select group mask. */ -+#define TC4_CLKSEL_gp 0 /* Clock Select group position. */ -+#define TC4_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ -+#define TC4_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ -+#define TC4_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ -+#define TC4_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ -+#define TC4_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ -+#define TC4_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ -+#define TC4_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ -+#define TC4_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ -+ -+/* TC4.CTRLB bit masks and bit positions */ -+#define TC4_BYTEM_gm 0xC0 /* Byte Mode group mask. */ -+#define TC4_BYTEM_gp 6 /* Byte Mode group position. */ -+#define TC4_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ -+#define TC4_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ -+#define TC4_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ -+#define TC4_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ -+ -+#define TC4_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ -+#define TC4_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ -+#define TC4_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ -+#define TC4_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ -+#define TC4_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ -+#define TC4_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ -+ -+#define TC4_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ -+#define TC4_WGMODE_gp 0 /* Waveform Generation Mode group position. */ -+#define TC4_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ -+#define TC4_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ -+#define TC4_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ -+#define TC4_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ -+#define TC4_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ -+#define TC4_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ -+ -+/* TC4.CTRLC bit masks and bit positions */ -+#define TC4_POLD_bm 0x80 /* Channel D Output Polarity bit mask. */ -+#define TC4_POLD_bp 7 /* Channel D Output Polarity bit position. */ -+ -+#define TC4_POLC_bm 0x40 /* Channel C Output Polarity bit mask. */ -+#define TC4_POLC_bp 6 /* Channel C Output Polarity bit position. */ -+ -+#define TC4_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ -+#define TC4_POLB_bp 5 /* Channel B Output Polarity bit position. */ -+ -+#define TC4_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ -+#define TC4_POLA_bp 4 /* Channel A Output Polarity bit position. */ -+ -+#define TC4_CMPD_bm 0x08 /* Channel D Compare Output Value bit mask. */ -+#define TC4_CMPD_bp 3 /* Channel D Compare Output Value bit position. */ -+ -+#define TC4_CMPC_bm 0x04 /* Channel C Compare Output Value bit mask. */ -+#define TC4_CMPC_bp 2 /* Channel C Compare Output Value bit position. */ -+ -+#define TC4_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ -+#define TC4_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ -+ -+#define TC4_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ -+#define TC4_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ -+ -+#define TC4_HCMPD_bm 0x80 /* High Channel D Compare Output Value bit mask. */ -+#define TC4_HCMPD_bp 7 /* High Channel D Compare Output Value bit position. */ -+ -+#define TC4_HCMPC_bm 0x40 /* High Channel C Compare Output Value bit mask. */ -+#define TC4_HCMPC_bp 6 /* High Channel C Compare Output Value bit position. */ -+ -+#define TC4_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ -+#define TC4_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ -+ -+#define TC4_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ -+#define TC4_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ -+ -+#define TC4_LCMPD_bm 0x08 /* Low Channel D Compare Output Value bit mask. */ -+#define TC4_LCMPD_bp 3 /* Low Channel D Compare Output Value bit position. */ -+ -+#define TC4_LCMPC_bm 0x04 /* Low Channel C Compare Output Value bit mask. */ -+#define TC4_LCMPC_bp 2 /* Low Channel C Compare Output Value bit position. */ -+ -+#define TC4_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ -+#define TC4_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ -+ -+#define TC4_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ -+#define TC4_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ -+ -+/* TC4.CTRLD bit masks and bit positions */ -+#define TC4_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC4_EVACT_gp 5 /* Event Action group position. */ -+#define TC4_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC4_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC4_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC4_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC4_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC4_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC4_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC4_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC4_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC4_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC4_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC4_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC4_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC4_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC4_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC4_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC4_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC4_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC4.CTRLE bit masks and bit positions */ -+#define TC4_CCDMODE_gm 0xC0 /* Channel D Compare or Capture Mode group mask. */ -+#define TC4_CCDMODE_gp 6 /* Channel D Compare or Capture Mode group position. */ -+#define TC4_CCDMODE0_bm (1<<6) /* Channel D Compare or Capture Mode bit 0 mask. */ -+#define TC4_CCDMODE0_bp 6 /* Channel D Compare or Capture Mode bit 0 position. */ -+#define TC4_CCDMODE1_bm (1<<7) /* Channel D Compare or Capture Mode bit 1 mask. */ -+#define TC4_CCDMODE1_bp 7 /* Channel D Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_CCCMODE_gm 0x30 /* Channel C Compare or Capture Mode group mask. */ -+#define TC4_CCCMODE_gp 4 /* Channel C Compare or Capture Mode group position. */ -+#define TC4_CCCMODE0_bm (1<<4) /* Channel C Compare or Capture Mode bit 0 mask. */ -+#define TC4_CCCMODE0_bp 4 /* Channel C Compare or Capture Mode bit 0 position. */ -+#define TC4_CCCMODE1_bm (1<<5) /* Channel C Compare or Capture Mode bit 1 mask. */ -+#define TC4_CCCMODE1_bp 5 /* Channel C Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ -+#define TC4_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ -+#define TC4_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ -+#define TC4_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ -+#define TC4_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ -+#define TC4_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ -+#define TC4_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ -+#define TC4_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ -+#define TC4_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ -+#define TC4_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ -+#define TC4_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_LCCDMODE_gm 0xC0 /* Channel Low D Compare or Capture Mode group mask. */ -+#define TC4_LCCDMODE_gp 6 /* Channel Low D Compare or Capture Mode group position. */ -+#define TC4_LCCDMODE0_bm (1<<6) /* Channel Low D Compare or Capture Mode bit 0 mask. */ -+#define TC4_LCCDMODE0_bp 6 /* Channel Low D Compare or Capture Mode bit 0 position. */ -+#define TC4_LCCDMODE1_bm (1<<7) /* Channel Low D Compare or Capture Mode bit 1 mask. */ -+#define TC4_LCCDMODE1_bp 7 /* Channel Low D Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_LCCCMODE_gm 0x30 /* Channel Low C Compare or Capture Mode group mask. */ -+#define TC4_LCCCMODE_gp 4 /* Channel Low C Compare or Capture Mode group position. */ -+#define TC4_LCCCMODE0_bm (1<<4) /* Channel Low C Compare or Capture Mode bit 0 mask. */ -+#define TC4_LCCCMODE0_bp 4 /* Channel Low C Compare or Capture Mode bit 0 position. */ -+#define TC4_LCCCMODE1_bm (1<<5) /* Channel Low C Compare or Capture Mode bit 1 mask. */ -+#define TC4_LCCCMODE1_bp 5 /* Channel Low C Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ -+#define TC4_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ -+#define TC4_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ -+#define TC4_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ -+#define TC4_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ -+#define TC4_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ -+#define TC4_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ -+#define TC4_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ -+#define TC4_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ -+#define TC4_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ -+#define TC4_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ -+ -+/* TC4.CTRLF bit masks and bit positions */ -+#define TC4_HCCDMODE_gm 0xC0 /* Channel High D Compare or Capture Mode group mask. */ -+#define TC4_HCCDMODE_gp 6 /* Channel High D Compare or Capture Mode group position. */ -+#define TC4_HCCDMODE0_bm (1<<6) /* Channel High D Compare or Capture Mode bit 0 mask. */ -+#define TC4_HCCDMODE0_bp 6 /* Channel High D Compare or Capture Mode bit 0 position. */ -+#define TC4_HCCDMODE1_bm (1<<7) /* Channel High D Compare or Capture Mode bit 1 mask. */ -+#define TC4_HCCDMODE1_bp 7 /* Channel High D Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_HCCCMODE_gm 0x30 /* Channel High C Compare or Capture Mode group mask. */ -+#define TC4_HCCCMODE_gp 4 /* Channel High C Compare or Capture Mode group position. */ -+#define TC4_HCCCMODE0_bm (1<<4) /* Channel High C Compare or Capture Mode bit 0 mask. */ -+#define TC4_HCCCMODE0_bp 4 /* Channel High C Compare or Capture Mode bit 0 position. */ -+#define TC4_HCCCMODE1_bm (1<<5) /* Channel High C Compare or Capture Mode bit 1 mask. */ -+#define TC4_HCCCMODE1_bp 5 /* Channel High C Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ -+#define TC4_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ -+#define TC4_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ -+#define TC4_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ -+#define TC4_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ -+#define TC4_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ -+ -+#define TC4_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ -+#define TC4_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ -+#define TC4_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ -+#define TC4_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ -+#define TC4_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ -+#define TC4_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ -+ -+/* TC4.INTCTRLA bit masks and bit positions */ -+#define TC4_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ -+#define TC4_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ -+#define TC4_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ -+#define TC4_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ -+#define TC4_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ -+#define TC4_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ -+ -+#define TC4_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ -+#define TC4_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ -+#define TC4_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ -+#define TC4_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ -+#define TC4_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ -+#define TC4_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ -+ -+#define TC4_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ -+#define TC4_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ -+#define TC4_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ -+#define TC4_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ -+#define TC4_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ -+#define TC4_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ -+ -+/* TC4.INTCTRLB bit masks and bit positions */ -+#define TC4_CCDINTLVL_gm 0xC0 /* Channel D Compare or Capture Interrupt Level group mask. */ -+#define TC4_CCDINTLVL_gp 6 /* Channel D Compare or Capture Interrupt Level group position. */ -+#define TC4_CCDINTLVL0_bm (1<<6) /* Channel D Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC4_CCDINTLVL0_bp 6 /* Channel D Compare or Capture Interrupt Level bit 0 position. */ -+#define TC4_CCDINTLVL1_bm (1<<7) /* Channel D Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC4_CCDINTLVL1_bp 7 /* Channel D Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC4_CCCINTLVL_gm 0x30 /* Channel C Compare or Capture Interrupt Level group mask. */ -+#define TC4_CCCINTLVL_gp 4 /* Channel C Compare or Capture Interrupt Level group position. */ -+#define TC4_CCCINTLVL0_bm (1<<4) /* Channel C Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC4_CCCINTLVL0_bp 4 /* Channel C Compare or Capture Interrupt Level bit 0 position. */ -+#define TC4_CCCINTLVL1_bm (1<<5) /* Channel C Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC4_CCCINTLVL1_bp 5 /* Channel C Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC4_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ -+#define TC4_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ -+#define TC4_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC4_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ -+#define TC4_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC4_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC4_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ -+#define TC4_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ -+#define TC4_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC4_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ -+#define TC4_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC4_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC4_LCCDINTLVL_gm 0xC0 /* Channel Low D Compare or Capture Interrupt Level group mask. */ -+#define TC4_LCCDINTLVL_gp 6 /* Channel Low D Compare or Capture Interrupt Level group position. */ -+#define TC4_LCCDINTLVL0_bm (1<<6) /* Channel Low D Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC4_LCCDINTLVL0_bp 6 /* Channel Low D Compare or Capture Interrupt Level bit 0 position. */ -+#define TC4_LCCDINTLVL1_bm (1<<7) /* Channel Low D Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC4_LCCDINTLVL1_bp 7 /* Channel Low D Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC4_LCCCINTLVL_gm 0x30 /* Channel Low C Compare or Capture Interrupt Level group mask. */ -+#define TC4_LCCCINTLVL_gp 4 /* Channel Low C Compare or Capture Interrupt Level group position. */ -+#define TC4_LCCCINTLVL0_bm (1<<4) /* Channel Low C Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC4_LCCCINTLVL0_bp 4 /* Channel Low C Compare or Capture Interrupt Level bit 0 position. */ -+#define TC4_LCCCINTLVL1_bm (1<<5) /* Channel Low C Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC4_LCCCINTLVL1_bp 5 /* Channel Low C Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC4_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ -+#define TC4_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ -+#define TC4_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC4_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ -+#define TC4_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC4_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC4_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ -+#define TC4_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ -+#define TC4_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC4_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ -+#define TC4_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC4_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ -+ -+/* TC4.CTRLGCLR bit masks and bit positions */ -+#define TC4_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ -+#define TC4_STOP_bp 5 /* Timer/Counter Stop bit position. */ -+ -+#define TC4_CMD_gm 0x0C /* Command group mask. */ -+#define TC4_CMD_gp 2 /* Command group position. */ -+#define TC4_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC4_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC4_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC4_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC4_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC4_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC4_DIR_bm 0x01 /* Counter Direction bit mask. */ -+#define TC4_DIR_bp 0 /* Counter Direction bit position. */ -+ -+/* TC4.CTRLGSET bit masks and bit positions */ -+/* TC4_STOP Predefined. */ -+/* TC4_STOP Predefined. */ -+ -+/* TC4_CMD Predefined. */ -+/* TC4_CMD Predefined. */ -+ -+/* TC4_LUPD Predefined. */ -+/* TC4_LUPD Predefined. */ -+ -+/* TC4_DIR Predefined. */ -+/* TC4_DIR Predefined. */ -+ -+/* TC4.CTRLHCLR bit masks and bit positions */ -+#define TC4_CCDBV_bm 0x10 /* Channel D Compare or Capture Buffer Valid bit mask. */ -+#define TC4_CCDBV_bp 4 /* Channel D Compare or Capture Buffer Valid bit position. */ -+ -+#define TC4_CCCBV_bm 0x08 /* Channel C Compare or Capture Buffer Valid bit mask. */ -+#define TC4_CCCBV_bp 3 /* Channel C Compare or Capture Buffer Valid bit position. */ -+ -+#define TC4_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ -+#define TC4_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ -+ -+#define TC4_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ -+#define TC4_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ -+ -+#define TC4_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC4_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+#define TC4_LCCDBV_bm 0x10 /* Channel Low D Compare or Capture Buffer Valid bit mask. */ -+#define TC4_LCCDBV_bp 4 /* Channel Low D Compare or Capture Buffer Valid bit position. */ -+ -+#define TC4_LCCCBV_bm 0x08 /* Channel Low C Compare or Capture Buffer Valid bit mask. */ -+#define TC4_LCCCBV_bp 3 /* Channel Low C Compare or Capture Buffer Valid bit position. */ -+ -+#define TC4_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ -+#define TC4_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ -+ -+#define TC4_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ -+#define TC4_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ -+ -+#define TC4_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ -+#define TC4_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ -+ -+/* TC4.CTRLHSET bit masks and bit positions */ -+/* TC4_CCDBV Predefined. */ -+/* TC4_CCDBV Predefined. */ -+ -+/* TC4_CCCBV Predefined. */ -+/* TC4_CCCBV Predefined. */ -+ -+/* TC4_CCBBV Predefined. */ -+/* TC4_CCBBV Predefined. */ -+ -+/* TC4_CCABV Predefined. */ -+/* TC4_CCABV Predefined. */ -+ -+/* TC4_PERBV Predefined. */ -+/* TC4_PERBV Predefined. */ -+ -+/* TC4_LCCDBV Predefined. */ -+/* TC4_LCCDBV Predefined. */ -+ -+/* TC4_LCCCBV Predefined. */ -+/* TC4_LCCCBV Predefined. */ -+ -+/* TC4_LCCBBV Predefined. */ -+/* TC4_LCCBBV Predefined. */ -+ -+/* TC4_LCCABV Predefined. */ -+/* TC4_LCCABV Predefined. */ -+ -+/* TC4_LPERBV Predefined. */ -+/* TC4_LPERBV Predefined. */ -+ -+/* TC4.INTFLAGS bit masks and bit positions */ -+#define TC4_CCDIF_bm 0x80 /* Channel D Compare or Capture Interrupt Flag bit mask. */ -+#define TC4_CCDIF_bp 7 /* Channel D Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC4_CCCIF_bm 0x40 /* Channel C Compare or Capture Interrupt Flag bit mask. */ -+#define TC4_CCCIF_bp 6 /* Channel C Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC4_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ -+#define TC4_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC4_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ -+#define TC4_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC4_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ -+#define TC4_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ -+ -+#define TC4_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC4_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC4_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ -+#define TC4_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ -+ -+#define TC4_LCCDIF_bm 0x80 /* Channel Low D Compare or Capture Interrupt Flag bit mask. */ -+#define TC4_LCCDIF_bp 7 /* Channel Low D Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC4_LCCCIF_bm 0x40 /* Channel Low C Compare or Capture Interrupt Flag bit mask. */ -+#define TC4_LCCCIF_bp 6 /* Channel Low C Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC4_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ -+#define TC4_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC4_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ -+#define TC4_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ -+ -+/* TC5.CTRLA bit masks and bit positions */ -+#define TC5_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ -+#define TC5_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ -+ -+#define TC5_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ -+#define TC5_EVSTART_bp 5 /* Start on Next Event bit position. */ -+ -+#define TC5_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ -+#define TC5_UPSTOP_bp 4 /* Stop on Next Update bit position. */ -+ -+#define TC5_CLKSEL_gm 0x0F /* Clock Select group mask. */ -+#define TC5_CLKSEL_gp 0 /* Clock Select group position. */ -+#define TC5_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ -+#define TC5_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ -+#define TC5_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ -+#define TC5_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ -+#define TC5_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ -+#define TC5_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ -+#define TC5_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ -+#define TC5_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ -+ -+/* TC5.CTRLB bit masks and bit positions */ -+#define TC5_BYTEM_gm 0xC0 /* Byte Mode group mask. */ -+#define TC5_BYTEM_gp 6 /* Byte Mode group position. */ -+#define TC5_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ -+#define TC5_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ -+#define TC5_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ -+#define TC5_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ -+ -+#define TC5_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ -+#define TC5_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ -+#define TC5_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ -+#define TC5_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ -+#define TC5_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ -+#define TC5_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ -+ -+#define TC5_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ -+#define TC5_WGMODE_gp 0 /* Waveform Generation Mode group position. */ -+#define TC5_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ -+#define TC5_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ -+#define TC5_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ -+#define TC5_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ -+#define TC5_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ -+#define TC5_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ -+ -+/* TC5.CTRLC bit masks and bit positions */ -+#define TC5_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ -+#define TC5_POLB_bp 5 /* Channel B Output Polarity bit position. */ -+ -+#define TC5_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ -+#define TC5_POLA_bp 4 /* Channel A Output Polarity bit position. */ -+ -+#define TC5_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ -+#define TC5_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ -+ -+#define TC5_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ -+#define TC5_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ -+ -+#define TC5_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ -+#define TC5_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ -+ -+#define TC5_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ -+#define TC5_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ -+ -+#define TC5_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ -+#define TC5_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ -+ -+#define TC5_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ -+#define TC5_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ -+ -+/* TC5.CTRLD bit masks and bit positions */ -+#define TC5_EVACT_gm 0xE0 /* Event Action group mask. */ -+#define TC5_EVACT_gp 5 /* Event Action group position. */ -+#define TC5_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ -+#define TC5_EVACT0_bp 5 /* Event Action bit 0 position. */ -+#define TC5_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ -+#define TC5_EVACT1_bp 6 /* Event Action bit 1 position. */ -+#define TC5_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ -+#define TC5_EVACT2_bp 7 /* Event Action bit 2 position. */ -+ -+#define TC5_EVDLY_bm 0x10 /* Event Delay bit mask. */ -+#define TC5_EVDLY_bp 4 /* Event Delay bit position. */ -+ -+#define TC5_EVSEL_gm 0x0F /* Event Source Select group mask. */ -+#define TC5_EVSEL_gp 0 /* Event Source Select group position. */ -+#define TC5_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ -+#define TC5_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ -+#define TC5_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ -+#define TC5_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ -+#define TC5_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ -+#define TC5_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ -+#define TC5_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ -+#define TC5_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ -+ -+/* TC5.CTRLE bit masks and bit positions */ -+#define TC5_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ -+#define TC5_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ -+#define TC5_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ -+#define TC5_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ -+#define TC5_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ -+#define TC5_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ -+ -+#define TC5_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ -+#define TC5_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ -+#define TC5_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ -+#define TC5_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ -+#define TC5_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ -+#define TC5_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ -+ -+#define TC5_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ -+#define TC5_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ -+#define TC5_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ -+#define TC5_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ -+#define TC5_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ -+#define TC5_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ -+ -+#define TC5_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ -+#define TC5_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ -+#define TC5_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ -+#define TC5_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ -+#define TC5_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ -+#define TC5_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ -+ -+/* TC5.CTRLF bit masks and bit positions */ -+#define TC5_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ -+#define TC5_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ -+#define TC5_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ -+#define TC5_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ -+#define TC5_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ -+#define TC5_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ -+ -+#define TC5_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ -+#define TC5_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ -+#define TC5_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ -+#define TC5_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ -+#define TC5_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ -+#define TC5_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ -+ -+/* TC5.INTCTRLA bit masks and bit positions */ -+#define TC5_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ -+#define TC5_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ -+#define TC5_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ -+#define TC5_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ -+#define TC5_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ -+#define TC5_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ -+ -+#define TC5_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ -+#define TC5_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ -+#define TC5_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ -+#define TC5_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ -+#define TC5_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ -+#define TC5_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ -+ -+#define TC5_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ -+#define TC5_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ -+#define TC5_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ -+#define TC5_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ -+#define TC5_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ -+#define TC5_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ -+ -+/* TC5.INTCTRLB bit masks and bit positions */ -+#define TC5_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ -+#define TC5_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ -+#define TC5_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC5_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ -+#define TC5_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC5_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC5_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ -+#define TC5_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ -+#define TC5_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC5_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ -+#define TC5_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC5_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC5_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ -+#define TC5_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ -+#define TC5_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC5_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ -+#define TC5_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC5_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ -+ -+#define TC5_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ -+#define TC5_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ -+#define TC5_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ -+#define TC5_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ -+#define TC5_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ -+#define TC5_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ -+ -+/* TC5.CTRLGCLR bit masks and bit positions */ -+#define TC5_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ -+#define TC5_STOP_bp 5 /* Timer/Counter Stop bit position. */ -+ -+#define TC5_CMD_gm 0x0C /* Command group mask. */ -+#define TC5_CMD_gp 2 /* Command group position. */ -+#define TC5_CMD0_bm (1<<2) /* Command bit 0 mask. */ -+#define TC5_CMD0_bp 2 /* Command bit 0 position. */ -+#define TC5_CMD1_bm (1<<3) /* Command bit 1 mask. */ -+#define TC5_CMD1_bp 3 /* Command bit 1 position. */ -+ -+#define TC5_LUPD_bm 0x02 /* Lock Update bit mask. */ -+#define TC5_LUPD_bp 1 /* Lock Update bit position. */ -+ -+#define TC5_DIR_bm 0x01 /* Counter Direction bit mask. */ -+#define TC5_DIR_bp 0 /* Counter Direction bit position. */ -+ -+/* TC5.CTRLGSET bit masks and bit positions */ -+/* TC5_STOP Predefined. */ -+/* TC5_STOP Predefined. */ -+ -+/* TC5_CMD Predefined. */ -+/* TC5_CMD Predefined. */ -+ -+/* TC5_LUPD Predefined. */ -+/* TC5_LUPD Predefined. */ -+ -+/* TC5_DIR Predefined. */ -+/* TC5_DIR Predefined. */ -+ -+/* TC5.CTRLHCLR bit masks and bit positions */ -+#define TC5_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ -+#define TC5_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ -+ -+#define TC5_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ -+#define TC5_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ -+ -+#define TC5_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ -+#define TC5_PERBV_bp 0 /* Period Buffer Valid bit position. */ -+ -+#define TC5_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ -+#define TC5_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ -+ -+#define TC5_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ -+#define TC5_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ -+ -+#define TC5_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ -+#define TC5_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ -+ -+/* TC5.CTRLHSET bit masks and bit positions */ -+/* TC5_CCBBV Predefined. */ -+/* TC5_CCBBV Predefined. */ -+ -+/* TC5_CCABV Predefined. */ -+/* TC5_CCABV Predefined. */ -+ -+/* TC5_PERBV Predefined. */ -+/* TC5_PERBV Predefined. */ -+ -+/* TC5_LCCBBV Predefined. */ -+/* TC5_LCCBBV Predefined. */ -+ -+/* TC5_LCCABV Predefined. */ -+/* TC5_LCCABV Predefined. */ -+ -+/* TC5_LPERBV Predefined. */ -+/* TC5_LPERBV Predefined. */ -+ -+/* TC5.INTFLAGS bit masks and bit positions */ -+#define TC5_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ -+#define TC5_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC5_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ -+#define TC5_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC5_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ -+#define TC5_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ -+ -+#define TC5_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ -+#define TC5_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ -+ -+#define TC5_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ -+#define TC5_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ -+ -+#define TC5_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ -+#define TC5_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ -+ -+#define TC5_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ -+#define TC5_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ -+ -+/* FAULT - Fault Extension */ -+/* FAULT.CTRLA bit masks and bit positions */ -+#define FAULT_RAMP_gm 0xC0 /* Ramp Mode Selection group mask. */ -+#define FAULT_RAMP_gp 6 /* Ramp Mode Selection group position. */ -+#define FAULT_RAMP0_bm (1<<6) /* Ramp Mode Selection bit 0 mask. */ -+#define FAULT_RAMP0_bp 6 /* Ramp Mode Selection bit 0 position. */ -+#define FAULT_RAMP1_bm (1<<7) /* Ramp Mode Selection bit 1 mask. */ -+#define FAULT_RAMP1_bp 7 /* Ramp Mode Selection bit 1 position. */ -+ -+#define FAULT_FDDBD_bm 0x20 /* Fault on Debug Break Detection bit mask. */ -+#define FAULT_FDDBD_bp 5 /* Fault on Debug Break Detection bit position. */ -+ -+#define FAULT_PORTCTRL_bm 0x10 /* Port Control Mode bit mask. */ -+#define FAULT_PORTCTRL_bp 4 /* Port Control Mode bit position. */ -+ -+#define FAULT_FUSE_bm 0x08 /* Fuse State bit mask. */ -+#define FAULT_FUSE_bp 3 /* Fuse State bit position. */ -+ -+#define FAULT_FILTERE_bm 0x04 /* Fault E Digital Filter Selection bit mask. */ -+#define FAULT_FILTERE_bp 2 /* Fault E Digital Filter Selection bit position. */ -+ -+#define FAULT_SRCE_gm 0x03 /* Fault E Input selection group mask. */ -+#define FAULT_SRCE_gp 0 /* Fault E Input selection group position. */ -+#define FAULT_SRCE0_bm (1<<0) /* Fault E Input selection bit 0 mask. */ -+#define FAULT_SRCE0_bp 0 /* Fault E Input selection bit 0 position. */ -+#define FAULT_SRCE1_bm (1<<1) /* Fault E Input selection bit 1 mask. */ -+#define FAULT_SRCE1_bp 1 /* Fault E Input selection bit 1 position. */ -+ -+/* FAULT.CTRLB bit masks and bit positions */ -+#define FAULT_SOFTA_bm 0x80 /* Fault A Software Mode bit mask. */ -+#define FAULT_SOFTA_bp 7 /* Fault A Software Mode bit position. */ -+ -+#define FAULT_HALTA_gm 0x60 /* Fault A Halt Action group mask. */ -+#define FAULT_HALTA_gp 5 /* Fault A Halt Action group position. */ -+#define FAULT_HALTA0_bm (1<<5) /* Fault A Halt Action bit 0 mask. */ -+#define FAULT_HALTA0_bp 5 /* Fault A Halt Action bit 0 position. */ -+#define FAULT_HALTA1_bm (1<<6) /* Fault A Halt Action bit 1 mask. */ -+#define FAULT_HALTA1_bp 6 /* Fault A Halt Action bit 1 position. */ -+ -+#define FAULT_RESTARTA_bm 0x10 /* Fault A Restart Action bit mask. */ -+#define FAULT_RESTARTA_bp 4 /* Fault A Restart Action bit position. */ -+ -+#define FAULT_KEEPA_bm 0x08 /* Fault A Keep Action bit mask. */ -+#define FAULT_KEEPA_bp 3 /* Fault A Keep Action bit position. */ -+ -+#define FAULT_SRCA_gm 0x03 /* Fault A Source Selection group mask. */ -+#define FAULT_SRCA_gp 0 /* Fault A Source Selection group position. */ -+#define FAULT_SRCA0_bm (1<<0) /* Fault A Source Selection bit 0 mask. */ -+#define FAULT_SRCA0_bp 0 /* Fault A Source Selection bit 0 position. */ -+#define FAULT_SRCA1_bm (1<<1) /* Fault A Source Selection bit 1 mask. */ -+#define FAULT_SRCA1_bp 1 /* Fault A Source Selection bit 1 position. */ -+ -+/* FAULT.CTRLC bit masks and bit positions */ -+#define FAULT_CAPTA_bm 0x20 /* Fault A Capture bit mask. */ -+#define FAULT_CAPTA_bp 5 /* Fault A Capture bit position. */ -+ -+#define FAULT_FILTERA_bm 0x04 /* Fault A Digital Filter Selection bit mask. */ -+#define FAULT_FILTERA_bp 2 /* Fault A Digital Filter Selection bit position. */ -+ -+#define FAULT_BLANKA_bm 0x02 /* Fault A Blanking bit mask. */ -+#define FAULT_BLANKA_bp 1 /* Fault A Blanking bit position. */ -+ -+#define FAULT_QUALA_bm 0x01 /* Fault A Qualification bit mask. */ -+#define FAULT_QUALA_bp 0 /* Fault A Qualification bit position. */ -+ -+/* FAULT.CTRLD bit masks and bit positions */ -+#define FAULT_SOFTB_bm 0x80 /* Fault B Software Mode bit mask. */ -+#define FAULT_SOFTB_bp 7 /* Fault B Software Mode bit position. */ -+ -+#define FAULT_HALTB_gm 0x60 /* Fault B Halt Action group mask. */ -+#define FAULT_HALTB_gp 5 /* Fault B Halt Action group position. */ -+#define FAULT_HALTB0_bm (1<<5) /* Fault B Halt Action bit 0 mask. */ -+#define FAULT_HALTB0_bp 5 /* Fault B Halt Action bit 0 position. */ -+#define FAULT_HALTB1_bm (1<<6) /* Fault B Halt Action bit 1 mask. */ -+#define FAULT_HALTB1_bp 6 /* Fault B Halt Action bit 1 position. */ -+ -+#define FAULT_RESTARTB_bm 0x10 /* Fault B Restart Action bit mask. */ -+#define FAULT_RESTARTB_bp 4 /* Fault B Restart Action bit position. */ -+ -+#define FAULT_KEEPB_bm 0x08 /* Fault B Keep Action bit mask. */ -+#define FAULT_KEEPB_bp 3 /* Fault B Keep Action bit position. */ -+ -+#define FAULT_SRCB_gm 0x03 /* Fault B Source Selection group mask. */ -+#define FAULT_SRCB_gp 0 /* Fault B Source Selection group position. */ -+#define FAULT_SRCB0_bm (1<<0) /* Fault B Source Selection bit 0 mask. */ -+#define FAULT_SRCB0_bp 0 /* Fault B Source Selection bit 0 position. */ -+#define FAULT_SRCB1_bm (1<<1) /* Fault B Source Selection bit 1 mask. */ -+#define FAULT_SRCB1_bp 1 /* Fault B Source Selection bit 1 position. */ -+ -+/* FAULT.CTRLE bit masks and bit positions */ -+#define FAULT_CAPTB_bm 0x20 /* Fault B Capture bit mask. */ -+#define FAULT_CAPTB_bp 5 /* Fault B Capture bit position. */ -+ -+#define FAULT_FILTERB_bm 0x04 /* Fault B Digital Filter Selection bit mask. */ -+#define FAULT_FILTERB_bp 2 /* Fault B Digital Filter Selection bit position. */ -+ -+#define FAULT_BLANKB_bm 0x02 /* Fault B Blanking bit mask. */ -+#define FAULT_BLANKB_bp 1 /* Fault B Blanking bit position. */ -+ -+#define FAULT_QUALB_bm 0x01 /* Fault B Qualification bit mask. */ -+#define FAULT_QUALB_bp 0 /* Fault B Qualification bit position. */ -+ -+/* FAULT.STATUS bit masks and bit positions */ -+#define FAULT_STATEB_bm 0x80 /* Fault B State bit mask. */ -+#define FAULT_STATEB_bp 7 /* Fault B State bit position. */ -+ -+#define FAULT_STATEA_bm 0x40 /* Fault A State bit mask. */ -+#define FAULT_STATEA_bp 6 /* Fault A State bit position. */ -+ -+#define FAULT_STATEE_bm 0x20 /* Fault E State bit mask. */ -+#define FAULT_STATEE_bp 5 /* Fault E State bit position. */ -+ -+#define FAULT_IDX_bm 0x08 /* Channel Index Flag bit mask. */ -+#define FAULT_IDX_bp 3 /* Channel Index Flag bit position. */ -+ -+#define FAULT_FAULTBIN_bm 0x04 /* Fault B Flag bit mask. */ -+#define FAULT_FAULTBIN_bp 2 /* Fault B Flag bit position. */ -+ -+#define FAULT_FAULTAIN_bm 0x02 /* Fault A Flag bit mask. */ -+#define FAULT_FAULTAIN_bp 1 /* Fault A Flag bit position. */ -+ -+#define FAULT_FAULTEIN_bm 0x01 /* Fault E Flag bit mask. */ -+#define FAULT_FAULTEIN_bp 0 /* Fault E Flag bit position. */ -+ -+/* FAULT.CTRLGCLR bit masks and bit positions */ -+#define FAULT_HALTBCLR_bm 0x80 /* State B Clear bit mask. */ -+#define FAULT_HALTBCLR_bp 7 /* State B Clear bit position. */ -+ -+#define FAULT_HALTACLR_bm 0x40 /* State A Clear bit mask. */ -+#define FAULT_HALTACLR_bp 6 /* State A Clear bit position. */ -+ -+#define FAULT_STATEECLR_bm 0x20 /* State E Clear bit mask. */ -+#define FAULT_STATEECLR_bp 5 /* State E Clear bit position. */ -+ -+#define FAULT_FAULTB_bm 0x04 /* Fault B Flag bit mask. */ -+#define FAULT_FAULTB_bp 2 /* Fault B Flag bit position. */ -+ -+#define FAULT_FAULTA_bm 0x02 /* Fault A Flag bit mask. */ -+#define FAULT_FAULTA_bp 1 /* Fault A Flag bit position. */ -+ -+#define FAULT_FAULTE_bm 0x01 /* Fault E Flag bit mask. */ -+#define FAULT_FAULTE_bp 0 /* Fault E Flag bit position. */ -+ -+/* FAULT.CTRLGSET bit masks and bit positions */ -+#define FAULT_FAULTBSW_bm 0x80 /* Software Fault B bit mask. */ -+#define FAULT_FAULTBSW_bp 7 /* Software Fault B bit position. */ -+ -+#define FAULT_FAULTASW_bm 0x40 /* Software Fault A bit mask. */ -+#define FAULT_FAULTASW_bp 6 /* Software Fault A bit position. */ -+ -+#define FAULT_FAULTESW_bm 0x20 /* Software Fault E bit mask. */ -+#define FAULT_FAULTESW_bp 5 /* Software Fault E bit position. */ -+ -+#define FAULT_IDXCMD_gm 0x18 /* Channel index Command group mask. */ -+#define FAULT_IDXCMD_gp 3 /* Channel index Command group position. */ -+#define FAULT_IDXCMD0_bm (1<<3) /* Channel index Command bit 0 mask. */ -+#define FAULT_IDXCMD0_bp 3 /* Channel index Command bit 0 position. */ -+#define FAULT_IDXCMD1_bm (1<<4) /* Channel index Command bit 1 mask. */ -+#define FAULT_IDXCMD1_bp 4 /* Channel index Command bit 1 position. */ -+ -+/* WEX - Waveform Extension */ -+/* WEX.CTRL bit masks and bit positions */ -+#define WEX_UPSEL_bm 0x80 /* Update Source Selection bit mask. */ -+#define WEX_UPSEL_bp 7 /* Update Source Selection bit position. */ -+ -+#define WEX_OTMX_gm 0x70 /* Output Matrix group mask. */ -+#define WEX_OTMX_gp 4 /* Output Matrix group position. */ -+#define WEX_OTMX0_bm (1<<4) /* Output Matrix bit 0 mask. */ -+#define WEX_OTMX0_bp 4 /* Output Matrix bit 0 position. */ -+#define WEX_OTMX1_bm (1<<5) /* Output Matrix bit 1 mask. */ -+#define WEX_OTMX1_bp 5 /* Output Matrix bit 1 position. */ -+#define WEX_OTMX2_bm (1<<6) /* Output Matrix bit 2 mask. */ -+#define WEX_OTMX2_bp 6 /* Output Matrix bit 2 position. */ -+ -+#define WEX_DTI3EN_bm 0x08 /* Dead-Time Insertion Generator 3 Enable bit mask. */ -+#define WEX_DTI3EN_bp 3 /* Dead-Time Insertion Generator 3 Enable bit position. */ -+ -+#define WEX_DTI2EN_bm 0x04 /* Dead-Time Insertion Generator 2 Enable bit mask. */ -+#define WEX_DTI2EN_bp 2 /* Dead-Time Insertion Generator 2 Enable bit position. */ -+ -+#define WEX_DTI1EN_bm 0x02 /* Dead-Time Insertion Generator 1 Enable bit mask. */ -+#define WEX_DTI1EN_bp 1 /* Dead-Time Insertion Generator 1 Enable bit position. */ -+ -+#define WEX_DTI0EN_bm 0x01 /* Dead-Time Insertion Generator 0 Enable bit mask. */ -+#define WEX_DTI0EN_bp 0 /* Dead-Time Insertion Generator 0 Enable bit position. */ -+ -+/* WEX.STATUSCLR bit masks and bit positions */ -+#define WEX_SWAPBUF_bm 0x04 /* Swap Buffer Valid bit mask. */ -+#define WEX_SWAPBUF_bp 2 /* Swap Buffer Valid bit position. */ -+ -+#define WEX_PGVBUFV_bm 0x02 /* Pattern Generator Value Buffer Valid bit mask. */ -+#define WEX_PGVBUFV_bp 1 /* Pattern Generator Value Buffer Valid bit position. */ -+ -+#define WEX_PGOBUFV_bm 0x01 /* Pattern Generator Overwrite Buffer Valid bit mask. */ -+#define WEX_PGOBUFV_bp 0 /* Pattern Generator Overwrite Buffer Valid bit position. */ -+ -+/* WEX.STATUSSET bit masks and bit positions */ -+/* WEX_SWAPBUF Predefined. */ -+/* WEX_SWAPBUF Predefined. */ -+ -+/* WEX_PGVBUFV Predefined. */ -+/* WEX_PGVBUFV Predefined. */ -+ -+/* WEX_PGOBUFV Predefined. */ -+/* WEX_PGOBUFV Predefined. */ -+ -+/* WEX.SWAP bit masks and bit positions */ -+#define WEX_SWAP3_bm 0x08 /* Swap DTI output pair 3 bit mask. */ -+#define WEX_SWAP3_bp 3 /* Swap DTI output pair 3 bit position. */ -+ -+#define WEX_SWAP2_bm 0x04 /* Swap DTI output pair 2 bit mask. */ -+#define WEX_SWAP2_bp 2 /* Swap DTI output pair 2 bit position. */ -+ -+#define WEX_SWAP1_bm 0x02 /* Swap DTI output pair 1 bit mask. */ -+#define WEX_SWAP1_bp 1 /* Swap DTI output pair 1 bit position. */ -+ -+#define WEX_SWAP0_bm 0x01 /* Swap DTI output pair 0 bit mask. */ -+#define WEX_SWAP0_bp 0 /* Swap DTI output pair 0 bit position. */ -+ -+/* WEX.SWAPBUF bit masks and bit positions */ -+#define WEX_SWAP3BUF_bm 0x08 /* Swap DTI output pair 3 bit mask. */ -+#define WEX_SWAP3BUF_bp 3 /* Swap DTI output pair 3 bit position. */ -+ -+#define WEX_SWAP2BUF_bm 0x04 /* Swap DTI output pair 2 bit mask. */ -+#define WEX_SWAP2BUF_bp 2 /* Swap DTI output pair 2 bit position. */ -+ -+#define WEX_SWAP1BUF_bm 0x02 /* Swap DTI output pair 1 bit mask. */ -+#define WEX_SWAP1BUF_bp 1 /* Swap DTI output pair 1 bit position. */ -+ -+#define WEX_SWAP0BUF_bm 0x01 /* Swap DTI output pair 0 bit mask. */ -+#define WEX_SWAP0BUF_bp 0 /* Swap DTI output pair 0 bit position. */ -+ -+/* HIRES - High-Resolution Extension */ -+/* HIRES.CTRLA bit masks and bit positions */ -+#define HIRES_HRPLUS_gm 0x0C /* High Resolution Plus group mask. */ -+#define HIRES_HRPLUS_gp 2 /* High Resolution Plus group position. */ -+#define HIRES_HRPLUS0_bm (1<<2) /* High Resolution Plus bit 0 mask. */ -+#define HIRES_HRPLUS0_bp 2 /* High Resolution Plus bit 0 position. */ -+#define HIRES_HRPLUS1_bm (1<<3) /* High Resolution Plus bit 1 mask. */ -+#define HIRES_HRPLUS1_bp 3 /* High Resolution Plus bit 1 position. */ -+ -+#define HIRES_HREN_gm 0x03 /* High Resolution Mode group mask. */ -+#define HIRES_HREN_gp 0 /* High Resolution Mode group position. */ -+#define HIRES_HREN0_bm (1<<0) /* High Resolution Mode bit 0 mask. */ -+#define HIRES_HREN0_bp 0 /* High Resolution Mode bit 0 position. */ -+#define HIRES_HREN1_bm (1<<1) /* High Resolution Mode bit 1 mask. */ -+#define HIRES_HREN1_bp 1 /* High Resolution Mode bit 1 position. */ -+ -+/* USART - Universal Asynchronous Receiver-Transmitter */ -+/* USART.STATUS bit masks and bit positions */ -+#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ -+#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ -+ -+#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ -+#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ -+ -+#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ -+#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ -+ -+#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ -+#define USART_FERR_bp 4 /* Frame Error bit position. */ -+ -+#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ -+#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ -+ -+#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ -+#define USART_PERR_bp 2 /* Parity Error bit position. */ -+ -+#define USART_RXSIF_bm 0x02 /* Receive Start Bit Interrupt Flag bit mask. */ -+#define USART_RXSIF_bp 1 /* Receive Start Bit Interrupt Flag bit position. */ -+ -+#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ -+#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ -+ -+#define USART_DRIF_bm 0x01 /* Data Reception Flag bit mask. */ -+#define USART_DRIF_bp 0 /* Data Reception Flag bit position. */ -+ -+/* USART.CTRLA bit masks and bit positions */ -+#define USART_RXSIE_bm 0x80 /* Receive Start Interrupt Enable bit mask. */ -+#define USART_RXSIE_bp 7 /* Receive Start Interrupt Enable bit position. */ -+ -+#define USART_DRIE_bm 0x40 /* Data Reception Interrupt Enable bit mask. */ -+#define USART_DRIE_bp 6 /* Data Reception Interrupt Enable bit position. */ -+ -+#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.CTRLB bit masks and bit positions */ -+#define USART_ONEWIRE_bm 0x80 /* One Wire Mode bit mask. */ -+#define USART_ONEWIRE_bp 7 /* One Wire Mode bit position. */ -+ -+#define USART_SFDEN_bm 0x40 /* Start Frame Detection Enable bit mask. */ -+#define USART_SFDEN_bp 6 /* Start Frame Detection Enable bit position. */ -+ -+#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ -+#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ -+ -+#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ -+#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ -+ -+#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ -+#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ -+ -+#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ -+#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ -+ -+#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ -+#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ -+ -+/* USART.CTRLC bit masks and bit positions */ -+#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ -+#define USART_CMODE_gp 6 /* Communication Mode group position. */ -+#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ -+#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ -+#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ -+#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ -+ -+#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ -+#define USART_PMODE_gp 4 /* Parity Mode group position. */ -+#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ -+#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ -+#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ -+#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ -+ -+#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ -+#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ -+ -+#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ -+#define USART_CHSIZE_gp 0 /* Character Size group position. */ -+#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ -+#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ -+#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ -+#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ -+#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ -+#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ -+ -+/* USART.CTRLD bit masks and bit positions */ -+#define USART_DECTYPE_gm 0x30 /* Receive Interrupt Level group mask. */ -+#define USART_DECTYPE_gp 4 /* Receive Interrupt Level group position. */ -+#define USART_DECTYPE0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ -+#define USART_DECTYPE0_bp 4 /* Receive Interrupt Level bit 0 position. */ -+#define USART_DECTYPE1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ -+#define USART_DECTYPE1_bp 5 /* Receive Interrupt Level bit 1 position. */ -+ -+#define USART_LUTACT_gm 0x0C /* Transmit Interrupt Level group mask. */ -+#define USART_LUTACT_gp 2 /* Transmit Interrupt Level group position. */ -+#define USART_LUTACT0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ -+#define USART_LUTACT0_bp 2 /* Transmit Interrupt Level bit 0 position. */ -+#define USART_LUTACT1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ -+#define USART_LUTACT1_bp 3 /* Transmit Interrupt Level bit 1 position. */ -+ -+#define USART_PECACT_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ -+#define USART_PECACT_gp 0 /* Data Register Empty Interrupt Level group position. */ -+#define USART_PECACT0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ -+#define USART_PECACT0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ -+#define USART_PECACT1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ -+#define USART_PECACT1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ -+ -+/* USART.BAUDCTRLA bit masks and bit positions */ -+#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ -+#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ -+#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ -+#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ -+#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ -+#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ -+#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ -+#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ -+#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ -+#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ -+#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ -+#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ -+#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ -+#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ -+#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ -+#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ -+#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ -+#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ -+ -+/* USART.BAUDCTRLB bit masks and bit positions */ -+#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ -+#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ -+#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ -+#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ -+#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ -+#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ -+#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ -+#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ -+#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ -+#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ -+ -+/* USART_BSEL Predefined. */ -+/* USART_BSEL Predefined. */ -+ -+/* SPI - Serial Peripheral Interface */ -+/* SPI.CTRL bit masks and bit positions */ -+#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ -+#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ -+ -+#define SPI_ENABLE_bm 0x40 /* Enable SPI Module bit mask. */ -+#define SPI_ENABLE_bp 6 /* Enable SPI Module bit position. */ -+ -+#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ -+#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ -+ -+#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ -+#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ -+ -+#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ -+#define SPI_MODE_gp 2 /* SPI Mode group position. */ -+#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ -+#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ -+#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ -+#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ -+ -+#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ -+#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ -+#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ -+#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ -+#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ -+#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ -+ -+/* SPI.INTCTRL bit masks and bit positions */ -+#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ -+#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit position. */ -+ -+#define SPI_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ -+#define SPI_TXCIE_bp 6 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit position. */ -+ -+#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit mask. */ -+#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit position. */ -+ -+#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit mask. */ -+#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit position. */ -+ -+#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ -+#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ -+#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ -+#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ -+#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ -+#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ -+ -+/* SPI.STATUS bit masks and bit positions */ -+#define SPI_IF_bm 0x80 /* Interrupt Flag (In Standard Mode Only). bit mask. */ -+#define SPI_IF_bp 7 /* Interrupt Flag (In Standard Mode Only). bit position. */ -+ -+#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ -+#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit position. */ -+ -+#define SPI_WRCOL_bm 0x40 /* Write Collision Flag (In Standard Mode Only). bit mask. */ -+#define SPI_WRCOL_bp 6 /* Write Collision Flag (In Standard Mode Only). bit position. */ -+ -+#define SPI_TXCIF_bm 0x40 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ -+#define SPI_TXCIF_bp 6 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit position. */ -+ -+#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit mask. */ -+#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit position. */ -+ -+#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit mask. */ -+#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit position. */ -+ -+#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow (In Buffer Modes Only). bit mask. */ -+#define SPI_BUFOVF_bp 0 /* Buffer Overflow (In Buffer Modes Only). bit position. */ -+ -+/* SPI.CTRLB bit masks and bit positions */ -+#define SPI_BUFMODE_gm 0xC0 /* Buffer Modes group mask. */ -+#define SPI_BUFMODE_gp 6 /* Buffer Modes group position. */ -+#define SPI_BUFMODE0_bm (1<<6) /* Buffer Modes bit 0 mask. */ -+#define SPI_BUFMODE0_bp 6 /* Buffer Modes bit 0 position. */ -+#define SPI_BUFMODE1_bm (1<<7) /* Buffer Modes bit 1 mask. */ -+#define SPI_BUFMODE1_bp 7 /* Buffer Modes bit 1 position. */ -+ -+#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ -+#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ -+ -+/* IRCOM - IR Communication Module */ -+/* IRCOM.CTRL bit masks and bit positions */ -+#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ -+#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ -+#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ -+#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ -+#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ -+#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ -+#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ -+#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ -+#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ -+#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ -+ -+/* FUSE - Fuses and Lockbits */ -+/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ -+#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ -+#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ -+#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ -+#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ -+#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ -+#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ -+#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ -+#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ -+ -+#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ -+#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ -+#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ -+#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ -+#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ -+#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ -+ -+#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ -+#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ -+#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ -+#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ -+#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ -+#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ -+#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ -+#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ -+#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ -+ -+#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ -+#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ -+#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ -+#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ -+#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ -+#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ -+#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ -+#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ -+#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ -+#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ -+ -+/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ -+#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ -+#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ -+ -+#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ -+#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ -+#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ -+#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ -+#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ -+#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ -+ -+/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ -+#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ -+#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ -+ -+#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ -+#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ -+#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ -+#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ -+#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ -+#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ -+ -+#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ -+#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ -+ -+/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ -+#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ -+#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ -+#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ -+#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ -+#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ -+#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ -+ -+#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ -+#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ -+ -+#define NVM_FUSES_BODLVL_gm 0x07 /* Brown Out Detection Voltage Level group mask. */ -+#define NVM_FUSES_BODLVL_gp 0 /* Brown Out Detection Voltage Level group position. */ -+#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brown Out Detection Voltage Level bit 0 mask. */ -+#define NVM_FUSES_BODLVL0_bp 0 /* Brown Out Detection Voltage Level bit 0 position. */ -+#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brown Out Detection Voltage Level bit 1 mask. */ -+#define NVM_FUSES_BODLVL1_bp 1 /* Brown Out Detection Voltage Level bit 1 position. */ -+#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brown Out Detection Voltage Level bit 2 mask. */ -+#define NVM_FUSES_BODLVL2_bp 2 /* Brown Out Detection Voltage Level bit 2 position. */ -+ -+/* NVM_FUSES.FUSEBYTE6 bit masks and bit positions */ -+#define NVM_FUSES_FDACT5_bm 0x80 /* Fault Dectection Action on TC5 bit mask. */ -+#define NVM_FUSES_FDACT5_bp 7 /* Fault Dectection Action on TC5 bit position. */ -+ -+#define NVM_FUSES_FDACT4_bm 0x40 /* Fault Dectection Action on TC4 bit mask. */ -+#define NVM_FUSES_FDACT4_bp 6 /* Fault Dectection Action on TC4 bit position. */ -+ -+#define NVM_FUSES_VALUE_gm 0x3F /* Port Pin Value group mask. */ -+#define NVM_FUSES_VALUE_gp 0 /* Port Pin Value group position. */ -+#define NVM_FUSES_VALUE0_bm (1<<0) /* Port Pin Value bit 0 mask. */ -+#define NVM_FUSES_VALUE0_bp 0 /* Port Pin Value bit 0 position. */ -+#define NVM_FUSES_VALUE1_bm (1<<1) /* Port Pin Value bit 1 mask. */ -+#define NVM_FUSES_VALUE1_bp 1 /* Port Pin Value bit 1 position. */ -+#define NVM_FUSES_VALUE2_bm (1<<2) /* Port Pin Value bit 2 mask. */ -+#define NVM_FUSES_VALUE2_bp 2 /* Port Pin Value bit 2 position. */ -+#define NVM_FUSES_VALUE3_bm (1<<3) /* Port Pin Value bit 3 mask. */ -+#define NVM_FUSES_VALUE3_bp 3 /* Port Pin Value bit 3 position. */ -+#define NVM_FUSES_VALUE4_bm (1<<4) /* Port Pin Value bit 4 mask. */ -+#define NVM_FUSES_VALUE4_bp 4 /* Port Pin Value bit 4 position. */ -+#define NVM_FUSES_VALUE5_bm (1<<5) /* Port Pin Value bit 5 mask. */ -+#define NVM_FUSES_VALUE5_bp 5 /* Port Pin Value bit 5 position. */ -+ -+ -+ -+// Generic Port Pins -+ -+#define PIN0_bm 0x01 -+#define PIN0_bp 0 -+#define PIN1_bm 0x02 -+#define PIN1_bp 1 -+#define PIN2_bm 0x04 -+#define PIN2_bp 2 -+#define PIN3_bm 0x08 -+#define PIN3_bp 3 -+#define PIN4_bm 0x10 -+#define PIN4_bp 4 -+#define PIN5_bm 0x20 -+#define PIN5_bp 5 -+#define PIN6_bm 0x40 -+#define PIN6_bp 6 -+#define PIN7_bm 0x80 -+#define PIN7_bp 7 -+ -+/* ========== Interrupt Vector Definitions ========== */ -+/* Vector 0 is the reset vector */ -+ -+/* OSC interrupt vectors */ -+#define OSC_OSCF_vect_num 1 -+#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ -+ -+/* PORTR interrupt vectors */ -+#define PORTR_INT_vect_num 2 -+#define PORTR_INT_vect _VECTOR(2) /* External Interrupt */ -+ -+/* EDMA interrupt vectors */ -+#define EDMA_CH0_vect_num 3 -+#define EDMA_CH0_vect _VECTOR(3) /* EDMA Channel 0 Interrupt */ -+#define EDMA_CH1_vect_num 4 -+#define EDMA_CH1_vect _VECTOR(4) /* EDMA Channel 1 Interrupt */ -+#define EDMA_CH2_vect_num 5 -+#define EDMA_CH2_vect _VECTOR(5) /* EDMA Channel 2 Interrupt */ -+#define EDMA_CH3_vect_num 6 -+#define EDMA_CH3_vect _VECTOR(6) /* EDMA Channel 3 Interrupt */ -+ -+/* RTC interrupt vectors */ -+#define RTC_OVF_vect_num 7 -+#define RTC_OVF_vect _VECTOR(7) /* Overflow Interrupt */ -+#define RTC_COMP_vect_num 8 -+#define RTC_COMP_vect _VECTOR(8) /* Compare Interrupt */ -+ -+/* PORTC interrupt vectors */ -+#define PORTC_INT_vect_num 9 -+#define PORTC_INT_vect _VECTOR(9) /* External Interrupt */ -+ -+/* TWIC interrupt vectors */ -+#define TWIC_TWIS_vect_num 10 -+#define TWIC_TWIS_vect _VECTOR(10) /* TWI Slave Interrupt */ -+#define TWIC_TWIM_vect_num 11 -+#define TWIC_TWIM_vect _VECTOR(11) /* TWI Master Interrupt */ -+ -+/* TCC4 interrupt vectors */ -+#define TCC4_OVF_vect_num 12 -+#define TCC4_OVF_vect _VECTOR(12) /* Overflow Interrupt */ -+#define TCC4_ERR_vect_num 13 -+#define TCC4_ERR_vect _VECTOR(13) /* Error Interrupt */ -+#define TCC4_CCA_vect_num 14 -+#define TCC4_CCA_vect _VECTOR(14) /* Channel A Compare or Capture Interrupt */ -+#define TCC4_CCB_vect_num 15 -+#define TCC4_CCB_vect _VECTOR(15) /* Channel B Compare or Capture Interrupt */ -+#define TCC4_CCC_vect_num 16 -+#define TCC4_CCC_vect _VECTOR(16) /* Channel C Compare or Capture Interrupt */ -+#define TCC4_CCD_vect_num 17 -+#define TCC4_CCD_vect _VECTOR(17) /* Channel D Compare or Capture Interrupt */ -+ -+/* TCC5 interrupt vectors */ -+#define TCC5_OVF_vect_num 18 -+#define TCC5_OVF_vect _VECTOR(18) /* Overflow Interrupt */ -+#define TCC5_ERR_vect_num 19 -+#define TCC5_ERR_vect _VECTOR(19) /* Error Interrupt */ -+#define TCC5_CCA_vect_num 20 -+#define TCC5_CCA_vect _VECTOR(20) /* Channel A Compare or Capture Interrupt */ -+#define TCC5_CCB_vect_num 21 -+#define TCC5_CCB_vect _VECTOR(21) /* Channel B Compare or Capture Interrupt */ -+ -+/* SPIC interrupt vectors */ -+#define SPIC_INT_vect_num 22 -+#define SPIC_INT_vect _VECTOR(22) /* SPI Interrupt */ -+ -+/* USARTC0 interrupt vectors */ -+#define USARTC0_RXC_vect_num 23 -+#define USARTC0_RXC_vect _VECTOR(23) /* Reception Complete Interrupt */ -+#define USARTC0_DRE_vect_num 24 -+#define USARTC0_DRE_vect _VECTOR(24) /* Data Register Empty Interrupt */ -+#define USARTC0_TXC_vect_num 25 -+#define USARTC0_TXC_vect _VECTOR(25) /* Transmission Complete Interrupt */ -+ -+/* NVM interrupt vectors */ -+#define NVM_EE_vect_num 26 -+#define NVM_EE_vect _VECTOR(26) /* EE Interrupt */ -+#define NVM_SPM_vect_num 27 -+#define NVM_SPM_vect _VECTOR(27) /* SPM Interrupt */ -+ -+/* XCL interrupt vectors */ -+#define XCL_UNF_vect_num 28 -+#define XCL_UNF_vect _VECTOR(28) /* Timer/Counter Underflow Interrupt */ -+#define XCL_CC_vect_num 29 -+#define XCL_CC_vect _VECTOR(29) /* Timer/Counter Compare or Capture Interrupt */ -+ -+/* PORTA interrupt vectors */ -+#define PORTA_INT_vect_num 30 -+#define PORTA_INT_vect _VECTOR(30) /* External Interrupt */ -+ -+/* ACA interrupt vectors */ -+#define ACA_AC0_vect_num 31 -+#define ACA_AC0_vect _VECTOR(31) /* AC0 Interrupt */ -+#define ACA_AC1_vect_num 32 -+#define ACA_AC1_vect _VECTOR(32) /* AC1 Interrupt */ -+#define ACA_ACW_vect_num 33 -+#define ACA_ACW_vect _VECTOR(33) /* ACW Window Mode Interrupt */ -+ -+/* ADCA interrupt vectors */ -+#define ADCA_CH0_vect_num 34 -+#define ADCA_CH0_vect _VECTOR(34) /* ADC Channel Interrupt */ -+ -+/* PORTD interrupt vectors */ -+#define PORTD_INT_vect_num 35 -+#define PORTD_INT_vect _VECTOR(35) /* External Interrupt */ -+ -+/* TCD5 interrupt vectors */ -+#define TCD5_OVF_vect_num 36 -+#define TCD5_OVF_vect _VECTOR(36) /* Overflow Interrupt */ -+#define TCD5_ERR_vect_num 37 -+#define TCD5_ERR_vect _VECTOR(37) /* Error Interrupt */ -+#define TCD5_CCA_vect_num 38 -+#define TCD5_CCA_vect _VECTOR(38) /* Channel A Compare or Capture Interrupt */ -+#define TCD5_CCB_vect_num 39 -+#define TCD5_CCB_vect _VECTOR(39) /* Channel B Compare or Capture Interrupt */ -+ -+/* USARTD0 interrupt vectors */ -+#define USARTD0_RXC_vect_num 40 -+#define USARTD0_RXC_vect _VECTOR(40) /* Reception Complete Interrupt */ -+#define USARTD0_DRE_vect_num 41 -+#define USARTD0_DRE_vect _VECTOR(41) /* Data Register Empty Interrupt */ -+#define USARTD0_TXC_vect_num 42 -+#define USARTD0_TXC_vect _VECTOR(42) /* Transmission Complete Interrupt */ -+ -+#define _VECTOR_SIZE 4 /* Size of individual vector. */ -+#define _VECTORS_SIZE (43 * _VECTOR_SIZE) -+ -+ -+/* ========== Constants ========== */ -+ -+#define PROGMEM_START (0x0000) -+#define PROGMEM_SIZE (10240) -+#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) -+ -+#define APP_SECTION_START (0x0000) -+#define APP_SECTION_SIZE (8192) -+#define APP_SECTION_PAGE_SIZE (128) -+#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) -+ -+#define APPTABLE_SECTION_START (0x1800) -+#define APPTABLE_SECTION_SIZE (2048) -+#define APPTABLE_SECTION_PAGE_SIZE (128) -+#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) -+ -+#define BOOT_SECTION_START (0x2000) -+#define BOOT_SECTION_SIZE (2048) -+#define BOOT_SECTION_PAGE_SIZE (128) -+#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) -+ -+#define DATAMEM_START (0x0000) -+#define DATAMEM_SIZE (9216) -+#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) -+ -+#define IO_START (0x0000) -+#define IO_SIZE (4096) -+#define IO_PAGE_SIZE (0) -+#define IO_END (IO_START + IO_SIZE - 1) -+ -+#define MAPPED_EEPROM_START (0x1000) -+#define MAPPED_EEPROM_SIZE (512) -+#define MAPPED_EEPROM_PAGE_SIZE (0) -+#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) -+ -+#define INTERNAL_SRAM_START (0x2000) -+#define INTERNAL_SRAM_SIZE (1024) -+#define INTERNAL_SRAM_PAGE_SIZE (0) -+#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) -+ -+#define EEPROM_START (0x0000) -+#define EEPROM_SIZE (512) -+#define EEPROM_PAGE_SIZE (32) -+#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) -+ -+#define SIGNATURES_START (0x0000) -+#define SIGNATURES_SIZE (3) -+#define SIGNATURES_PAGE_SIZE (0) -+#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) -+ -+#define FUSES_START (0x0000) -+#define FUSES_SIZE (7) -+#define FUSES_PAGE_SIZE (0) -+#define FUSES_END (FUSES_START + FUSES_SIZE - 1) -+ -+#define LOCKBITS_START (0x0000) -+#define LOCKBITS_SIZE (1) -+#define LOCKBITS_PAGE_SIZE (0) -+#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) -+ -+#define USER_SIGNATURES_START (0x0000) -+#define USER_SIGNATURES_SIZE (128) -+#define USER_SIGNATURES_PAGE_SIZE (128) -+#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) -+ -+#define PROD_SIGNATURES_START (0x0000) -+#define PROD_SIGNATURES_SIZE (52) -+#define PROD_SIGNATURES_PAGE_SIZE (128) -+#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) -+ -+#define FLASHSTART PROGMEM_START -+#define FLASHEND PROGMEM_END -+#define SPM_PAGESIZE 128 -+#define RAMSTART INTERNAL_SRAM_START -+#define RAMSIZE INTERNAL_SRAM_SIZE -+#define RAMEND INTERNAL_SRAM_END -+#define E2END EEPROM_END -+#define E2PAGESIZE EEPROM_PAGE_SIZE -+ -+ -+/* ========== Fuses ========== */ -+#define FUSE_MEMORY_SIZE 7 -+ -+/* Fuse Byte 0 Reserved */ -+ -+/* Fuse Byte 1 */ -+#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ -+#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ -+#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ -+#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ -+#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ -+#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ -+#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ -+#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ -+#define FUSE1_DEFAULT (0xFF) -+ -+/* Fuse Byte 2 */ -+#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ -+#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ -+#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ -+#define FUSE2_DEFAULT (0xFF) -+ -+/* Fuse Byte 3 Reserved */ -+ -+/* Fuse Byte 4 */ -+#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ -+#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ -+#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ -+#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ -+#define FUSE4_DEFAULT (0xFF) -+ -+/* Fuse Byte 5 */ -+#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brown Out Detection Voltage Level Bit 0 */ -+#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brown Out Detection Voltage Level Bit 1 */ -+#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brown Out Detection Voltage Level Bit 2 */ -+#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ -+#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ -+#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ -+#define FUSE5_DEFAULT (0xFF) -+ -+/* Fuse Byte 6 */ -+#define FUSE_VALUE0 (unsigned char)~_BV(0) /* Port Pin Value Bit 0 */ -+#define FUSE_VALUE1 (unsigned char)~_BV(1) /* Port Pin Value Bit 1 */ -+#define FUSE_VALUE2 (unsigned char)~_BV(2) /* Port Pin Value Bit 2 */ -+#define FUSE_VALUE3 (unsigned char)~_BV(3) /* Port Pin Value Bit 3 */ -+#define FUSE_VALUE4 (unsigned char)~_BV(4) /* Port Pin Value Bit 4 */ -+#define FUSE_VALUE5 (unsigned char)~_BV(5) /* Port Pin Value Bit 5 */ -+#define FUSE_FDACT4 (unsigned char)~_BV(6) /* Fault Dectection Action on TC4 */ -+#define FUSE_FDACT5 (unsigned char)~_BV(7) /* Fault Dectection Action on TC5 */ -+#define FUSE6_DEFAULT (0xFF) -+ -+/* ========== Lock Bits ========== */ -+#define __LOCK_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST -+#define __BOOT_LOCK_APPLICATION_BITS_EXIST -+#define __BOOT_LOCK_BOOT_BITS_EXIST -+ -+/* ========== Signature ========== */ -+#define SIGNATURE_0 0x1E -+#define SIGNATURE_1 0x93 -+#define SIGNATURE_2 0x41 -+ -+ -+#endif /* #ifdef _AVR_ATXMEGA8E5_H_INCLUDED */ -+ ++/***************************************************************************** ++ * ++ * Copyright (C) 2014 Atmel Corporation ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions are met: ++ * ++ * * Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * ++ * * Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in ++ * the documentation and/or other materials provided with the ++ * distribution. ++ * ++ * * Neither the name of the copyright holders nor the names of ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE ++ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ ****************************************************************************/ ++ ++ ++#ifndef _AVR_IO_H_ ++# error "Include instead of this file." ++#endif ++ ++#ifndef _AVR_IOXXX_H_ ++# define _AVR_IOXXX_H_ "iox8e5.h" ++#else ++# error "Attempt to include more than one file." ++#endif ++ ++#ifndef _AVR_ATXMEGA8E5_H_INCLUDED ++#define _AVR_ATXMEGA8E5_H_INCLUDED ++ ++/* Ungrouped common registers */ ++#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++/* Deprecated */ ++#define GPIO0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */ ++#define GPIO1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */ ++#define GPIO2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */ ++#define GPIO3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */ ++ ++#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */ ++#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */ ++#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */ ++#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */ ++#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */ ++#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */ ++#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */ ++#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */ ++#define SREG _SFR_MEM8(0x003F) /* Status Register */ ++ ++/* C Language Only */ ++#if !defined (__ASSEMBLER__) ++ ++#include ++ ++typedef volatile uint8_t register8_t; ++typedef volatile uint16_t register16_t; ++typedef volatile uint32_t register32_t; ++ ++ ++#ifdef _WORDREGISTER ++#undef _WORDREGISTER ++#endif ++#define _WORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register16_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## L; \ ++ register8_t regname ## H; \ ++ }; \ ++ } ++ ++#ifdef _DWORDREGISTER ++#undef _DWORDREGISTER ++#endif ++#define _DWORDREGISTER(regname) \ ++ __extension__ union \ ++ { \ ++ register32_t regname; \ ++ struct \ ++ { \ ++ register8_t regname ## 0; \ ++ register8_t regname ## 1; \ ++ register8_t regname ## 2; \ ++ register8_t regname ## 3; \ ++ }; \ ++ } ++ ++ ++/* ++========================================================================== ++IO Module Structures ++========================================================================== ++*/ ++ ++ ++/* ++-------------------------------------------------------------------------- ++VPORT - Virtual Ports ++-------------------------------------------------------------------------- ++*/ ++ ++/* Virtual Port */ ++typedef struct VPORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t IN; /* I/O Port Input */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++} VPORT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XOCD - On-Chip Debug System ++-------------------------------------------------------------------------- ++*/ ++ ++/* On-Chip Debug System */ ++typedef struct OCD_struct ++{ ++ register8_t OCDR0; /* OCD Register 0 */ ++ register8_t OCDR1; /* OCD Register 1 */ ++} OCD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CPU - CPU ++-------------------------------------------------------------------------- ++*/ ++ ++/* CCP signatures */ ++typedef enum CCP_enum ++{ ++ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */ ++ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */ ++} CCP_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CLK - Clock System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Clock System */ ++typedef struct CLK_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t PSCTRL; /* Prescaler Control Register */ ++ register8_t LOCK; /* Lock register */ ++ register8_t RTCCTRL; /* RTC Control Register */ ++ register8_t reserved_0x04; ++} CLK_t; ++ ++ ++/* Power Reduction */ ++typedef struct PR_struct ++{ ++ register8_t PRGEN; /* General Power Reduction */ ++ register8_t PRPA; /* Power Reduction Port A */ ++ register8_t reserved_0x02; ++ register8_t PRPC; /* Power Reduction Port C */ ++ register8_t PRPD; /* Power Reduction Port D */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++} PR_t; ++ ++/* System Clock Selection */ ++typedef enum CLK_SCLKSEL_enum ++{ ++ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */ ++ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */ ++ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock */ ++ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */ ++ CLK_SCLKSEL_RC8M_gc = (0x05<<0), /* Internal 8 MHz RC Oscillator */ ++} CLK_SCLKSEL_t; ++ ++/* Prescaler A Division Factor */ ++typedef enum CLK_PSADIV_enum ++{ ++ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */ ++ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */ ++ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */ ++ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */ ++ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */ ++ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */ ++ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */ ++ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */ ++ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */ ++ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */ ++ CLK_PSADIV_6_gc = (0x13<<2), /* Divide by 6 */ ++ CLK_PSADIV_10_gc = (0x15<<2), /* Divide by 10 */ ++ CLK_PSADIV_12_gc = (0x17<<2), /* Divide by 12 */ ++ CLK_PSADIV_24_gc = (0x19<<2), /* Divide by 24 */ ++ CLK_PSADIV_48_gc = (0x1B<<2), /* Divide by 48 */ ++} CLK_PSADIV_t; ++ ++/* Prescaler B and C Division Factor */ ++typedef enum CLK_PSBCDIV_enum ++{ ++ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */ ++ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */ ++ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */ ++ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */ ++} CLK_PSBCDIV_t; ++ ++/* RTC Clock Source */ ++typedef enum CLK_RTCSRC_enum ++{ ++ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */ ++ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal oscillator on TOSC */ ++ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz RC oscillator */ ++ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */ ++} CLK_RTCSRC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SLEEP - Sleep Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Sleep Controller */ ++typedef struct SLEEP_struct ++{ ++ register8_t CTRL; /* Control Register */ ++} SLEEP_t; ++ ++/* Sleep Mode */ ++typedef enum SLEEP_SMODE_enum ++{ ++ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */ ++ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */ ++ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */ ++ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */ ++ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */ ++} SLEEP_SMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++OSC - Oscillator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Oscillator */ ++typedef struct OSC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t XOSCCTRL; /* External Oscillator Control Register */ ++ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */ ++ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration Register */ ++ register8_t PLLCTRL; /* PLL Control Register */ ++ register8_t DFLLCTRL; /* DFLL Control Register */ ++ register8_t RC8MCAL; /* Internal 8 MHz RC Oscillator Calibration Register */ ++} OSC_t; ++ ++/* Oscillator Frequency Range */ ++typedef enum OSC_FRQRANGE_enum ++{ ++ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */ ++ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */ ++ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */ ++ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */ ++} OSC_FRQRANGE_t; ++ ++/* External Oscillator Selection and Startup Time */ ++typedef enum OSC_XOSCSEL_enum ++{ ++ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock on port R1 - 6 CLK */ ++ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */ ++ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */ ++ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */ ++ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */ ++ OSC_XOSCSEL_EXTCLK_C4_gc = (0x14<<0), /* External Clock on port C4 - 6 CLK */ ++} OSC_XOSCSEL_t; ++ ++/* PLL Clock Source */ ++typedef enum OSC_PLLSRC_enum ++{ ++ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */ ++ OSC_PLLSRC_RC8M_gc = (0x01<<6), /* Internal 8 MHz RC Oscillator */ ++ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */ ++ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */ ++} OSC_PLLSRC_t; ++ ++/* 32 MHz DFLL Calibration Reference */ ++typedef enum OSC_RC32MCREF_enum ++{ ++ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator */ ++ OSC_RC32MCREF_XOSC32K_gc = (0x01<<1), /* External 32.768 kHz Crystal Oscillator */ ++} OSC_RC32MCREF_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DFLL - DFLL ++-------------------------------------------------------------------------- ++*/ ++ ++/* DFLL */ ++typedef struct DFLL_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x01; ++ register8_t CALA; /* Calibration Register A */ ++ register8_t CALB; /* Calibration Register B */ ++ register8_t COMP0; /* Oscillator Compare Register 0 */ ++ register8_t COMP1; /* Oscillator Compare Register 1 */ ++ register8_t COMP2; /* Oscillator Compare Register 2 */ ++ register8_t reserved_0x07; ++} DFLL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RST - Reset ++-------------------------------------------------------------------------- ++*/ ++ ++/* Reset */ ++typedef struct RST_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRL; /* Control Register */ ++} RST_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WDT - Watch-Dog Timer ++-------------------------------------------------------------------------- ++*/ ++ ++/* Watch-Dog Timer */ ++typedef struct WDT_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t WINCTRL; /* Windowed Mode Control */ ++ register8_t STATUS; /* Status */ ++} WDT_t; ++ ++/* Period setting */ ++typedef enum WDT_PER_enum ++{ ++ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_PER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_PER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_PER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_PER_t; ++ ++/* Closed window period */ ++typedef enum WDT_WPER_enum ++{ ++ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */ ++ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */ ++ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */ ++ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */ ++ WDT_WPER_128CLK_gc = (0x04<<2), /* 128 cycles (0.128s @ 3.3V) */ ++ WDT_WPER_256CLK_gc = (0x05<<2), /* 256 cycles (0.256s @ 3.3V) */ ++ WDT_WPER_512CLK_gc = (0x06<<2), /* 512 cycles (0.512s @ 3.3V) */ ++ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */ ++ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */ ++ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */ ++ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */ ++} WDT_WPER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++MCU - MCU Control ++-------------------------------------------------------------------------- ++*/ ++ ++/* MCU Control */ ++typedef struct MCU_struct ++{ ++ register8_t DEVID0; /* Device ID byte 0 */ ++ register8_t DEVID1; /* Device ID byte 1 */ ++ register8_t DEVID2; /* Device ID byte 2 */ ++ register8_t REVID; /* Revision ID */ ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t ANAINIT; /* Analog Startup Delay */ ++ register8_t EVSYSLOCK; /* Event System Lock */ ++ register8_t WEXLOCK; /* WEX Lock */ ++ register8_t FAULTLOCK; /* FAULT Lock */ ++ register8_t reserved_0x0B; ++} MCU_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PMIC - Programmable Multi-level Interrupt Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Programmable Multi-level Interrupt Controller */ ++typedef struct PMIC_struct ++{ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTPRI; /* Interrupt Priority */ ++ register8_t CTRL; /* Control Register */ ++ register8_t reserved_0x03; ++ register8_t reserved_0x04; ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} PMIC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORTCFG - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O port Configuration */ ++typedef struct PORTCFG_struct ++{ ++ register8_t MPCMASK; /* Multi-pin Configuration Mask */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t reserved_0x03; ++ register8_t CLKOUT; /* Clock Out Register */ ++ register8_t reserved_0x05; ++ register8_t ACEVOUT; /* Analog Comparator and Event Out Register */ ++ register8_t SRLCTRL; /* Slew Rate Limit Control Register */ ++} PORTCFG_t; ++ ++/* Clock and Event Output Port */ ++typedef enum PORTCFG_CLKEVPIN_enum ++{ ++ PORTCFG_CLKEVPIN_PIN7_gc = (0x00<<7), /* Clock and Event Ouput on PIN 7 */ ++ PORTCFG_CLKEVPIN_PIN4_gc = (0x01<<7), /* Clock and Event Ouput on PIN 4 */ ++} PORTCFG_CLKEVPIN_t; ++ ++/* RTC Clock Output Port */ ++typedef enum PORTCFG_RTCCLKOUT_enum ++{ ++ PORTCFG_RTCCLKOUT_OFF_gc = (0x00<<5), /* System Clock Output Disabled */ ++ PORTCFG_RTCCLKOUT_PC6_gc = (0x01<<5), /* System Clock Output on Port C pin 6 */ ++ PORTCFG_RTCCLKOUT_PD6_gc = (0x02<<5), /* System Clock Output on Port D pin 6 */ ++ PORTCFG_RTCCLKOUT_PR0_gc = (0x03<<5), /* System Clock Output on Port R pin 0 */ ++} PORTCFG_RTCCLKOUT_t; ++ ++/* Peripheral Clock Output Select */ ++typedef enum PORTCFG_CLKOUTSEL_enum ++{ ++ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to pin */ ++ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to pin */ ++} PORTCFG_CLKOUTSEL_t; ++ ++/* System Clock Output Port */ ++typedef enum PORTCFG_CLKOUT_enum ++{ ++ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */ ++ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7 */ ++ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7 */ ++ PORTCFG_CLKOUT_PR0_gc = (0x03<<0), /* System Clock Output on Port R pin 0 */ ++} PORTCFG_CLKOUT_t; ++ ++/* Analog Comparator Output Port */ ++typedef enum PORTCFG_ACOUT_enum ++{ ++ PORTCFG_ACOUT_PA_gc = (0x00<<6), /* Analog Comparator Outputs on Port A, Pin 6-7 */ ++ PORTCFG_ACOUT_PC_gc = (0x01<<6), /* Analog Comparator Outputs on Port C, Pin 6-7 */ ++ PORTCFG_ACOUT_PD_gc = (0x02<<6), /* Analog Comparator Outputs on Port D, Pin 6-7 */ ++ PORTCFG_ACOUT_PR_gc = (0x03<<6), /* Analog Comparator Outputs on Port R, Pin 0-1 */ ++} PORTCFG_ACOUT_t; ++ ++/* Event Output Port */ ++typedef enum PORTCFG_EVOUT_enum ++{ ++ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */ ++ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel n Output on Port C pin 7 */ ++ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel n Output on Port D pin 7 */ ++ PORTCFG_EVOUT_PR0_gc = (0x03<<4), /* Event Channel n Output on Port R pin 0 */ ++} PORTCFG_EVOUT_t; ++ ++/* Event Output Select */ ++typedef enum PORTCFG_EVOUTSEL_enum ++{ ++ PORTCFG_EVOUTSEL_0_gc = (0x00<<0), /* Event Channel 0 output to pin */ ++ PORTCFG_EVOUTSEL_1_gc = (0x01<<0), /* Event Channel 1 output to pin */ ++ PORTCFG_EVOUTSEL_2_gc = (0x02<<0), /* Event Channel 2 output to pin */ ++ PORTCFG_EVOUTSEL_3_gc = (0x03<<0), /* Event Channel 3 output to pin */ ++ PORTCFG_EVOUTSEL_4_gc = (0x04<<0), /* Event Channel 4 output to pin */ ++ PORTCFG_EVOUTSEL_5_gc = (0x05<<0), /* Event Channel 5 output to pin */ ++ PORTCFG_EVOUTSEL_6_gc = (0x06<<0), /* Event Channel 6 output to pin */ ++ PORTCFG_EVOUTSEL_7_gc = (0x07<<0), /* Event Channel 7 output to pin */ ++} PORTCFG_EVOUTSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++CRC - Cyclic Redundancy Checker ++-------------------------------------------------------------------------- ++*/ ++ ++/* Cyclic Redundancy Checker */ ++typedef struct CRC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t reserved_0x02; ++ register8_t DATAIN; /* Data Input */ ++ register8_t CHECKSUM0; /* Checksum byte 0 */ ++ register8_t CHECKSUM1; /* Checksum byte 1 */ ++ register8_t CHECKSUM2; /* Checksum byte 2 */ ++ register8_t CHECKSUM3; /* Checksum byte 3 */ ++} CRC_t; ++ ++/* Reset */ ++typedef enum CRC_RESET_enum ++{ ++ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */ ++ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros */ ++ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */ ++} CRC_RESET_t; ++ ++/* Input Source */ ++typedef enum CRC_SOURCE_enum ++{ ++ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* Disabled */ ++ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */ ++ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */ ++ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */ ++ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */ ++ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */ ++ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */ ++} CRC_SOURCE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EDMA - Enhanced DMA Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* EDMA Channel */ ++typedef struct EDMA_CH_struct ++{ ++ register8_t CTRLA; /* Channel Control A */ ++ register8_t CTRLB; /* Channel Control */ ++ register8_t ADDRCTRL; /* Memory Address Control for Peripheral Ch., or Source Address Control for Standard Ch. */ ++ register8_t DESTADDRCTRL; /* Destination Address Control for Standard Channels Only. */ ++ register8_t TRIGSRC; /* Channel Trigger Source */ ++ register8_t reserved_0x05; ++ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch. */ ++ _WORDREGISTER(ADDR); /* Channel Memory Address for Peripheral Ch., or Channel Source Address Low for Standard Ch. */ ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(DESTADDR); /* Channel Destination Address for Standard Channels Only. */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} EDMA_CH_t; ++ ++ ++/* Enhanced DMA Controller */ ++typedef struct EDMA_struct ++{ ++ register8_t CTRL; /* Control */ ++ register8_t reserved_0x01; ++ register8_t reserved_0x02; ++ register8_t INTFLAGS; /* Transfer Interrupt Status */ ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x05; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ EDMA_CH_t CH0; /* EDMA Channel 0 */ ++ EDMA_CH_t CH1; /* EDMA Channel 1 */ ++ EDMA_CH_t CH2; /* EDMA Channel 2 */ ++ EDMA_CH_t CH3; /* EDMA Channel 3 */ ++} EDMA_t; ++ ++/* Channel mode */ ++typedef enum EDMA_CHMODE_enum ++{ ++ EDMA_CHMODE_PER0123_gc = (0x00<<4), /* Channels 0, 1, 2 and 3 in peripheal conf. */ ++ EDMA_CHMODE_STD0_gc = (0x01<<4), /* Channel 0 in standard conf.; channels 2 and 3 in peripheral conf. */ ++ EDMA_CHMODE_STD2_gc = (0x02<<4), /* Channel 2 in standard conf.; channels 0 and 1 in peripheral conf. */ ++ EDMA_CHMODE_STD02_gc = (0x03<<4), /* Channels 0 and 2 in standard conf. */ ++} EDMA_CHMODE_t; ++ ++/* Double buffer mode */ ++typedef enum EDMA_DBUFMODE_enum ++{ ++ EDMA_DBUFMODE_DISABLE_gc = (0x00<<2), /* No double buffer enabled */ ++ EDMA_DBUFMODE_BUF01_gc = (0x01<<2), /* Double buffer enabled on peripheral channels 0/1 (if exist) */ ++ EDMA_DBUFMODE_BUF23_gc = (0x02<<2), /* Double buffer enabled on peripheral channels 2/3 (if exist) */ ++ EDMA_DBUFMODE_BUF0123_gc = (0x03<<2), /* Double buffer enabled on peripheral channels 0/1 and 2/3 or standard channels 0/2 */ ++} EDMA_DBUFMODE_t; ++ ++/* Priority mode */ ++typedef enum EDMA_PRIMODE_enum ++{ ++ EDMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round robin on all channels */ ++ EDMA_PRIMODE_RR123_gc = (0x01<<0), /* Ch0 > round robin (Ch 1 ch2 Ch3) */ ++ EDMA_PRIMODE_RR23_gc = (0x02<<0), /* Ch0 > Ch 1 > round robin (Ch2 Ch3) */ ++ EDMA_PRIMODE_CH0123_gc = (0x03<<0), /* Ch0 > Ch1 > Ch2 > Ch3 */ ++} EDMA_PRIMODE_t; ++ ++/* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. */ ++typedef enum EDMA_CH_RELOAD_enum ++{ ++ EDMA_CH_RELOAD_NONE_gc = (0x00<<4), /* No reload */ ++ EDMA_CH_RELOAD_BLOCK_gc = (0x01<<4), /* Reload at end of each block transfer */ ++ EDMA_CH_RELOAD_BURST_gc = (0x02<<4), /* Reload at end of each burst transfer */ ++ EDMA_CH_RELOAD_TRANSACTION_gc = (0x03<<4), /* Reload at end of each transaction */ ++} EDMA_CH_RELOAD_t; ++ ++/* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. */ ++typedef enum EDMA_CH_DIR_enum ++{ ++ EDMA_CH_DIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ EDMA_CH_DIR_INC_gc = (0x01<<0), /* Increment */ ++ EDMA_CH_DIR_MP1_gc = (0x04<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'mask-match' (data: ADDRL, mask: ADDRH), else reserved conf. */ ++ EDMA_CH_DIR_MP2_gc = (0x05<<0), /* If Peripheral Ch. (Per ==> Mem), 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH), else reserved conf. */ ++ EDMA_CH_DIR_MP3_gc = (0x06<<0), /* If Peripheral Ch. (Per ==> Mem), 2-byte 'match' (data-1: ADDRL followed by data-2: ADDRH), else reserved conf. */ ++} EDMA_CH_DIR_t; ++ ++/* Destination addressing mode */ ++typedef enum EDMA_CH_DESTDIR_enum ++{ ++ EDMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */ ++ EDMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */ ++ EDMA_CH_DESTDIR_MP1_gc = (0x04<<0), /* 1-byte 'mask-match' (data: ADDRL, mask: ADDRH) */ ++ EDMA_CH_DESTDIR_MP2_gc = (0x05<<0), /* 1-byte 'OR-match' (data-1: ADDRL OR data-2: ADDRH) */ ++ EDMA_CH_DESTDIR_MP3_gc = (0x06<<0), /* 2-byte 'match' (data1: ADDRL followed by data2: ADDRH) */ ++} EDMA_CH_DESTDIR_t; ++ ++/* Transfer trigger source */ ++typedef enum EDMA_CH_TRIGSRC_enum ++{ ++ EDMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Software triggers only */ ++ EDMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event CH0 as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event CH1 as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event CH2 as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA CH0 as trigger */ ++ EDMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA CH0 as trigger */ ++ EDMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA CH1 as trigger */ ++ EDMA_CH_TRIGSRC_TCC4_OVF_gc = (0x40<<0), /* TCC4 overflow/underflow as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCC4_ERR_gc = (0x41<<0), /* TCC4 error as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCC4_CCA_gc = (0x42<<0), /* TCC4 compare or capture channel A as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCC4_CCB_gc = (0x43<<0), /* TCC4 compare or capture channel B as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCC4_CCC_gc = (0x44<<0), /* TCC4 compare or capture channel C as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCC4_CCD_gc = (0x45<<0), /* TCC4 compare or capture channel D as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCC5_OVF_gc = (0x46<<0), /* TCC5 overflow/underflow as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCC5_ERR_gc = (0x47<<0), /* TCC5 error as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCC5_CCA_gc = (0x48<<0), /* TCC5 compare or capture channel A as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCC5_CCB_gc = (0x49<<0), /* TCC5 compare or capture channel B as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_SPIC_RXC_gc = (0x4A<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C receive complete as trigger (SPI Buffer Modes) */ ++ EDMA_CH_TRIGSRC_SPIC_DRE_gc = (0x4B<<0), /* SPI C transfer complete (SPI Standard Mode) or SPI C data register empty as trigger (SPI Buffer modes) */ ++ EDMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4C<<0), /* USART C0 receive complete as trigger */ ++ EDMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4D<<0), /* USART C0 data register empty as trigger */ ++ EDMA_CH_TRIGSRC_TCD5_OVF_gc = (0x66<<0), /* TCD5 overflow/underflow as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCD5_ERR_gc = (0x67<<0), /* TCD5 error as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCD5_CCA_gc = (0x68<<0), /* TCD5 compare or capture channel A as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_TCD5_CCB_gc = (0x69<<0), /* TCD5 compare or capture channel B as trigger (Standard Channels Only) */ ++ EDMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6C<<0), /* USART D0 receive complete as trigger */ ++ EDMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6D<<0), /* USART D0 data register empty as trigger */ ++} EDMA_CH_TRIGSRC_t; ++ ++/* Interrupt level */ ++typedef enum EDMA_CH_INTLVL_enum ++{ ++ EDMA_CH_INTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ EDMA_CH_INTLVL_LO_gc = (0x01<<2), /* Low level */ ++ EDMA_CH_INTLVL_MED_gc = (0x02<<2), /* Medium level */ ++ EDMA_CH_INTLVL_HI_gc = (0x03<<2), /* High level */ ++} EDMA_CH_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++EVSYS - Event System ++-------------------------------------------------------------------------- ++*/ ++ ++/* Event System */ ++typedef struct EVSYS_struct ++{ ++ register8_t CH0MUX; /* Event Channel 0 Multiplexer */ ++ register8_t CH1MUX; /* Event Channel 1 Multiplexer */ ++ register8_t CH2MUX; /* Event Channel 2 Multiplexer */ ++ register8_t CH3MUX; /* Event Channel 3 Multiplexer */ ++ register8_t CH4MUX; /* Event Channel 4 Multiplexer */ ++ register8_t CH5MUX; /* Event Channel 5 Multiplexer */ ++ register8_t CH6MUX; /* Event Channel 6 Multiplexer */ ++ register8_t CH7MUX; /* Event Channel 7 Multiplexer */ ++ register8_t CH0CTRL; /* Channel 0 Control Register */ ++ register8_t CH1CTRL; /* Channel 1 Control Register */ ++ register8_t CH2CTRL; /* Channel 2 Control Register */ ++ register8_t CH3CTRL; /* Channel 3 Control Register */ ++ register8_t CH4CTRL; /* Channel 4 Control Register */ ++ register8_t CH5CTRL; /* Channel 5 Control Register */ ++ register8_t CH6CTRL; /* Channel 6 Control Register */ ++ register8_t CH7CTRL; /* Channel 7 Control Register */ ++ register8_t STROBE; /* Event Strobe */ ++ register8_t DATA; /* Event Data */ ++ register8_t DFCTRL; /* Digital Filter Control Register */ ++} EVSYS_t; ++ ++/* Event Channel multiplexer input selection */ ++typedef enum EVSYS_CHMUX_enum ++{ ++ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */ ++ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */ ++ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */ ++ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */ ++ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */ ++ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */ ++ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */ ++ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */ ++ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */ ++ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */ ++ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */ ++ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */ ++ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */ ++ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */ ++ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */ ++ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */ ++ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */ ++ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */ ++ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */ ++ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */ ++ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */ ++ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */ ++ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */ ++ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */ ++ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */ ++ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */ ++ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */ ++ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */ ++ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */ ++ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */ ++ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */ ++ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */ ++ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */ ++ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */ ++ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */ ++ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */ ++ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */ ++ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */ ++ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */ ++ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */ ++ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */ ++ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */ ++ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */ ++ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */ ++ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */ ++ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384 */ ++ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768 */ ++ EVSYS_CHMUX_XCL_UNF0_gc = (0xB0<<0), /* XCL BTC0 underflow */ ++ EVSYS_CHMUX_XCL_UNF1_gc = (0xB1<<0), /* XCL BTC1 underflow */ ++ EVSYS_CHMUX_XCL_CC0_gc = (0xB2<<0), /* XCL BTC0 capture or compare */ ++ EVSYS_CHMUX_XCL_CC1_gc = (0xB3<<0), /* XCL BTC0 capture or compare */ ++ EVSYS_CHMUX_XCL_PEC0_gc = (0xB4<<0), /* XCL PEC0 restart */ ++ EVSYS_CHMUX_XCL_PEC1_gc = (0xB5<<0), /* XCL PEC1 restart */ ++ EVSYS_CHMUX_XCL_LUT0_gc = (0xB6<<0), /* XCL LUT0 output */ ++ EVSYS_CHMUX_XCL_LUT1_gc = (0xB7<<0), /* XCL LUT1 output */ ++ EVSYS_CHMUX_TCC4_OVF_gc = (0xC0<<0), /* Timer/Counter C4 Overflow */ ++ EVSYS_CHMUX_TCC4_ERR_gc = (0xC1<<0), /* Timer/Counter C4 Error */ ++ EVSYS_CHMUX_TCC4_CCA_gc = (0xC4<<0), /* Timer/Counter C4 Compare or Capture A */ ++ EVSYS_CHMUX_TCC4_CCB_gc = (0xC5<<0), /* Timer/Counter C4 Compare or Capture B */ ++ EVSYS_CHMUX_TCC4_CCC_gc = (0xC6<<0), /* Timer/Counter C4 Compare or Capture C */ ++ EVSYS_CHMUX_TCC4_CCD_gc = (0xC7<<0), /* Timer/Counter C4 Compare or Capture D */ ++ EVSYS_CHMUX_TCC5_OVF_gc = (0xC8<<0), /* Timer/Counter C5 Overflow */ ++ EVSYS_CHMUX_TCC5_ERR_gc = (0xC9<<0), /* Timer/Counter C5 Error */ ++ EVSYS_CHMUX_TCC5_CCA_gc = (0xCC<<0), /* Timer/Counter C5 Compare or Capture A */ ++ EVSYS_CHMUX_TCC5_CCB_gc = (0xCD<<0), /* Timer/Counter C5 Compare or Capture B */ ++ EVSYS_CHMUX_TCD5_OVF_gc = (0xD8<<0), /* Timer/Counter D5 Overflow */ ++ EVSYS_CHMUX_TCD5_ERR_gc = (0xD9<<0), /* Timer/Counter D5 Error */ ++ EVSYS_CHMUX_TCD5_CCA_gc = (0xDC<<0), /* Timer/Counter D5 Compare or Capture A */ ++ EVSYS_CHMUX_TCD5_CCB_gc = (0xDD<<0), /* Timer/Counter D5 Compare or Capture B */ ++} EVSYS_CHMUX_t; ++ ++/* Quadrature Decoder Index Recognition Mode */ ++typedef enum EVSYS_QDIRM_enum ++{ ++ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */ ++ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */ ++ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */ ++ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */ ++} EVSYS_QDIRM_t; ++ ++/* Digital filter coefficient */ ++typedef enum EVSYS_DIGFILT_enum ++{ ++ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */ ++ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */ ++ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */ ++ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */ ++ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */ ++ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */ ++ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */ ++ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */ ++} EVSYS_DIGFILT_t; ++ ++/* Prescaler Filter */ ++typedef enum EVSYS_PRESCFILT_enum ++{ ++ EVSYS_PRESCFILT_CH04_gc = (0x01<<4), /* Enable prescaler filter for either channel 0 or 4 */ ++ EVSYS_PRESCFILT_CH15_gc = (0x02<<4), /* Enable prescaler filter for either channel 1 or 5 */ ++ EVSYS_PRESCFILT_CH26_gc = (0x04<<4), /* Enable prescaler filter for either channel 2 or 6 */ ++ EVSYS_PRESCFILT_CH37_gc = (0x08<<4), /* Enable prescaler filter for either channel 3 or 7 */ ++} EVSYS_PRESCFILT_t; ++ ++/* Prescaler */ ++typedef enum EVSYS_PRESCALER_enum ++{ ++ EVSYS_PRESCALER_CLKPER_8_gc = (0x00<<0), /* CLKPER, divide by 8 */ ++ EVSYS_PRESCALER_CLKPER_64_gc = (0x01<<0), /* CLKPER, divide by 64 */ ++ EVSYS_PRESCALER_CLKPER_512_gc = (0x02<<0), /* CLKPER, divide by 512 */ ++ EVSYS_PRESCALER_CLKPER_4096_gc = (0x03<<0), /* CLKPER, divide by 4096 */ ++ EVSYS_PRESCALER_CLKPER_32768_gc = (0x04<<0), /* CLKPER, divide by 32768 */ ++} EVSYS_PRESCALER_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++NVM - Non Volatile Memory Controller ++-------------------------------------------------------------------------- ++*/ ++ ++/* Non-volatile Memory Controller */ ++typedef struct NVM_struct ++{ ++ register8_t ADDR0; /* Address Register 0 */ ++ register8_t ADDR1; /* Address Register 1 */ ++ register8_t ADDR2; /* Address Register 2 */ ++ register8_t reserved_0x03; ++ register8_t DATA0; /* Data Register 0 */ ++ register8_t DATA1; /* Data Register 1 */ ++ register8_t DATA2; /* Data Register 2 */ ++ register8_t reserved_0x07; ++ register8_t reserved_0x08; ++ register8_t reserved_0x09; ++ register8_t CMD; /* Command */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t INTCTRL; /* Interrupt Control */ ++ register8_t reserved_0x0E; ++ register8_t STATUS; /* Status */ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_t; ++ ++/* NVM Command */ ++typedef enum NVM_CMD_enum ++{ ++ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */ ++ NVM_CMD_READ_USER_SIG_ROW_gc = (0x01<<0), /* Read user signature row */ ++ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */ ++ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */ ++ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */ ++ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */ ++ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */ ++ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */ ++ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page */ ++ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */ ++ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page */ ++ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write Application Section page */ ++ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page buffer */ ++ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */ ++ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */ ++ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */ ++ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot Section page */ ++ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */ ++ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash Page */ ++ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */ ++ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */ ++ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */ ++ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM page */ ++ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page buffer */ ++ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Application section CRC */ ++ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Boot Section CRC */ ++ NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0), /* Flash Range CRC */ ++ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */ ++ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */ ++ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */ ++ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */ ++ NVM_CMD_FLASH_CRC_gc = (0x78<<0), /* Flash CRC */ ++} NVM_CMD_t; ++ ++/* SPM ready interrupt level */ ++typedef enum NVM_SPMLVL_enum ++{ ++ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */ ++ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */ ++ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */ ++ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */ ++} NVM_SPMLVL_t; ++ ++/* EEPROM ready interrupt level */ ++typedef enum NVM_EELVL_enum ++{ ++ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */ ++ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */ ++ NVM_EELVL_HI_gc = (0x03<<0), /* High level */ ++} NVM_EELVL_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum NVM_BLBB_enum ++{ ++ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} NVM_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum NVM_BLBA_enum ++{ ++ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} NVM_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum NVM_BLBAT_enum ++{ ++ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} NVM_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum NVM_LB_enum ++{ ++ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} NVM_LB_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++ADC - Analog/Digital Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* ADC Channel */ ++typedef struct ADC_CH_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t MUXCTRL; /* MUX Control */ ++ register8_t INTCTRL; /* Channel Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ _WORDREGISTER(RES); /* Channel Result */ ++ register8_t SCAN; /* Input Channel Scan */ ++ register8_t CORRCTRL; /* Correction Control Register */ ++ register8_t OFFSETCORR0; /* Offset Correction Register 0 */ ++ register8_t OFFSETCORR1; /* Offset Correction Register 1 */ ++ register8_t GAINCORR0; /* Gain Correction Register 0 */ ++ register8_t GAINCORR1; /* Gain Correction Register 1 */ ++ register8_t AVGCTRL; /* Average Control Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++} ADC_CH_t; ++ ++ ++/* Analog-to-Digital Converter */ ++typedef struct ADC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t REFCTRL; /* Reference Control */ ++ register8_t EVCTRL; /* Event Control */ ++ register8_t PRESCALER; /* Clock Prescaler */ ++ register8_t reserved_0x05; ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary Register */ ++ register8_t SAMPCTRL; /* ADC Sampling Time Control Register */ ++ register8_t reserved_0x09; ++ register8_t reserved_0x0A; ++ register8_t reserved_0x0B; ++ _WORDREGISTER(CAL); /* Calibration Value */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ _WORDREGISTER(CH0RES); /* Channel 0 Result */ ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CMP); /* Compare Value */ ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ ADC_CH_t CH0; /* ADC Channel 0 */ ++} ADC_t; ++ ++/* Current Limitation */ ++typedef enum ADC_CURRLIMIT_enum ++{ ++ ADC_CURRLIMIT_NO_gc = (0x00<<5), /* No current limit, 300ksps max sampling rate */ ++ ADC_CURRLIMIT_LOW_gc = (0x01<<5), /* Low current limit, 250ksps max sampling rate */ ++ ADC_CURRLIMIT_MED_gc = (0x02<<5), /* Medium current limit, 150ksps max sampling rate */ ++ ADC_CURRLIMIT_HIGH_gc = (0x03<<5), /* High current limit, 50ksps max sampling rate */ ++} ADC_CURRLIMIT_t; ++ ++/* Conversion result resolution */ ++typedef enum ADC_RESOLUTION_enum ++{ ++ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */ ++ ADC_RESOLUTION_MT12BIT_gc = (0x01<<1), /* More than 12-bit (oversapling) right-adjusted result */ ++ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */ ++ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */ ++} ADC_RESOLUTION_t; ++ ++/* Voltage reference selection */ ++typedef enum ADC_REFSEL_enum ++{ ++ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */ ++ ADC_REFSEL_INTVCC_gc = (0x01<<4), /* Internal VCC / 1.6 */ ++ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */ ++ ADC_REFSEL_AREFD_gc = (0x03<<4), /* External reference on PORT D */ ++ ADC_REFSEL_INTVCC2_gc = (0x04<<4), /* Internal VCC / 2 */ ++} ADC_REFSEL_t; ++ ++/* Event channel input selection */ ++typedef enum ADC_EVSEL_enum ++{ ++ ADC_EVSEL_0_gc = (0x00<<3), /* Event Channel 0 */ ++ ADC_EVSEL_1_gc = (0x01<<3), /* Event Channel 1 */ ++ ADC_EVSEL_2_gc = (0x02<<3), /* Event Channel 2 */ ++ ADC_EVSEL_3_gc = (0x03<<3), /* Event Channel 3 */ ++ ADC_EVSEL_4_gc = (0x04<<3), /* Event Channel 4 */ ++ ADC_EVSEL_5_gc = (0x05<<3), /* Event Channel 5 */ ++ ADC_EVSEL_6_gc = (0x06<<3), /* Event Channel 6 */ ++ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */ ++} ADC_EVSEL_t; ++ ++/* Event action selection */ ++typedef enum ADC_EVACT_enum ++{ ++ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */ ++ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel conversion */ ++ ADC_EVACT_SYNCSWEEP_gc = (0x06<<0), /* The ADC is flushed and restarted for accurate timing */ ++} ADC_EVACT_t; ++ ++/* Clock prescaler */ ++typedef enum ADC_PRESCALER_enum ++{ ++ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */ ++ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */ ++ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */ ++ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */ ++ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */ ++ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */ ++ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */ ++ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */ ++} ADC_PRESCALER_t; ++ ++/* Gain factor */ ++typedef enum ADC_CH_GAIN_enum ++{ ++ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */ ++ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */ ++ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */ ++ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */ ++ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */ ++ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */ ++ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */ ++ ADC_CH_GAIN_DIV2_gc = (0x07<<2), /* x/2 gain */ ++} ADC_CH_GAIN_t; ++ ++/* Input mode */ ++typedef enum ADC_CH_INPUTMODE_enum ++{ ++ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */ ++ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no gain */ ++ ADC_CH_INPUTMODE_DIFFWGAINL_gc = (0x02<<0), /* Differential input, gain with 4 LSB pins selection */ ++ ADC_CH_INPUTMODE_DIFFWGAINH_gc = (0x03<<0), /* Differential input, gain with 4 MSB pins selection */ ++} ADC_CH_INPUTMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum ADC_CH_MUXPOS_enum ++{ ++ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */ ++ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */ ++ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */ ++ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */ ++ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */ ++ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */ ++ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */ ++ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */ ++ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */ ++ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */ ++ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */ ++ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */ ++ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */ ++ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */ ++ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */ ++ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */ ++} ADC_CH_MUXPOS_t; ++ ++/* Internal input multiplexer selections */ ++typedef enum ADC_CH_MUXINT_enum ++{ ++ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */ ++ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */ ++ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 Scaled VCC */ ++ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC Output */ ++} ADC_CH_MUXINT_t; ++ ++/* Negative input multiplexer selection when gain on 4 LSB pins */ ++typedef enum ADC_CH_MUXNEGL_enum ++{ ++ ADC_CH_MUXNEGL_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++ ADC_CH_MUXNEGL_PIN1_gc = (0x01<<0), /* Input pin 1 */ ++ ADC_CH_MUXNEGL_PIN2_gc = (0x02<<0), /* Input pin 2 */ ++ ADC_CH_MUXNEGL_PIN3_gc = (0x03<<0), /* Input pin 3 */ ++ ADC_CH_MUXNEGL_GND_gc = (0x05<<0), /* PAD ground */ ++ ADC_CH_MUXNEGL_INTGND_gc = (0x07<<0), /* Internal ground */ ++} ADC_CH_MUXNEGL_t; ++ ++/* Negative input multiplexer selection when gain on 4 MSB pins */ ++typedef enum ADC_CH_MUXNEGH_enum ++{ ++ ADC_CH_MUXNEGH_PIN4_gc = (0x00<<0), /* Input pin 4 */ ++ ADC_CH_MUXNEGH_PIN5_gc = (0x01<<0), /* Input pin 5 */ ++ ADC_CH_MUXNEGH_PIN6_gc = (0x02<<0), /* Input pin 6 */ ++ ADC_CH_MUXNEGH_PIN7_gc = (0x03<<0), /* Input pin 7 */ ++ ADC_CH_MUXNEGH_GND_gc = (0x05<<0), /* PAD ground */ ++} ADC_CH_MUXNEGH_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum ADC_CH_MUXNEG_enum ++{ ++ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */ ++} ADC_CH_MUXNEG_t; ++ ++/* Interupt mode */ ++typedef enum ADC_CH_INTMODE_enum ++{ ++ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion complete */ ++ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare value */ ++ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare value */ ++} ADC_CH_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum ADC_CH_INTLVL_enum ++{ ++ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */ ++ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */ ++ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */ ++} ADC_CH_INTLVL_t; ++ ++/* Averaged Number of Samples */ ++typedef enum ADC_SAMPNUM_enum ++{ ++ ADC_SAMPNUM_1X_gc = (0x00<<0), /* 1 Sample */ ++ ADC_SAMPNUM_2X_gc = (0x01<<0), /* 2 Samples */ ++ ADC_SAMPNUM_4X_gc = (0x02<<0), /* 4 Samples */ ++ ADC_SAMPNUM_8X_gc = (0x03<<0), /* 8 Samples */ ++ ADC_SAMPNUM_16X_gc = (0x04<<0), /* 16 Samples */ ++ ADC_SAMPNUM_32X_gc = (0x05<<0), /* 32 Samples */ ++ ADC_SAMPNUM_64X_gc = (0x06<<0), /* 64 Samples */ ++ ADC_SAMPNUM_128X_gc = (0x07<<0), /* 128 Samples */ ++ ADC_SAMPNUM_256X_gc = (0x08<<0), /* 256 Samples */ ++ ADC_SAMPNUM_512X_gc = (0x09<<0), /* 512 Samples */ ++ ADC_SAMPNUM_1024X_gc = (0x0A<<0), /* 1024 Samples */ ++} ADC_SAMPNUM_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++DAC - Digital/Analog Converter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Digital-to-Analog Converter */ ++typedef struct DAC_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t EVCTRL; /* Event Input Control */ ++ register8_t reserved_0x04; ++ register8_t STATUS; /* Status */ ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t CH0GAINCAL; /* Gain Calibration */ ++ register8_t CH0OFFSETCAL; /* Offset Calibration */ ++ register8_t CH1GAINCAL; /* Gain Calibration */ ++ register8_t CH1OFFSETCAL; /* Offset Calibration */ ++ register8_t reserved_0x0C; ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ _WORDREGISTER(CH0DATA); /* Channel 0 Data */ ++ _WORDREGISTER(CH1DATA); /* Channel 1 Data */ ++} DAC_t; ++ ++/* Output channel selection */ ++typedef enum DAC_CHSEL_enum ++{ ++ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0 only) */ ++ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1 only) */ ++ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and channel 1) */ ++} DAC_CHSEL_t; ++ ++/* Reference voltage selection */ ++typedef enum DAC_REFSEL_enum ++{ ++ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */ ++ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */ ++ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */ ++ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */ ++} DAC_REFSEL_t; ++ ++/* Event channel selection */ ++typedef enum DAC_EVSEL_enum ++{ ++ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */ ++ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */ ++ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */ ++ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */ ++ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */ ++ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */ ++ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */ ++ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */ ++} DAC_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++AC - Analog Comparator ++-------------------------------------------------------------------------- ++*/ ++ ++/* Analog Comparator */ ++typedef struct AC_struct ++{ ++ register8_t AC0CTRL; /* Analog Comparator 0 Control */ ++ register8_t AC1CTRL; /* Analog Comparator 1 Control */ ++ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */ ++ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t WINCTRL; /* Window Mode Control */ ++ register8_t STATUS; /* Status */ ++ register8_t CURRCTRL; /* Current Source Control Register */ ++ register8_t CURRCALIB; /* Current Source Calibration Register */ ++} AC_t; ++ ++/* Interrupt mode */ ++typedef enum AC_INTMODE_enum ++{ ++ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */ ++ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */ ++ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */ ++} AC_INTMODE_t; ++ ++/* Interrupt level */ ++typedef enum AC_INTLVL_enum ++{ ++ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */ ++ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */ ++ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */ ++ AC_INTLVL_HI_gc = (0x03<<4), /* High level */ ++} AC_INTLVL_t; ++ ++/* Hysteresis mode selection */ ++typedef enum AC_HYSMODE_enum ++{ ++ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */ ++ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */ ++ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */ ++} AC_HYSMODE_t; ++ ++/* Positive input multiplexer selection */ ++typedef enum AC_MUXPOS_enum ++{ ++ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */ ++ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */ ++ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */ ++ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */ ++ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */ ++ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */ ++ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */ ++ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */ ++} AC_MUXPOS_t; ++ ++/* Negative input multiplexer selection */ ++typedef enum AC_MUXNEG_enum ++{ ++ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */ ++ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */ ++ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */ ++ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */ ++ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */ ++ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */ ++ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */ ++ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */ ++} AC_MUXNEG_t; ++ ++/* Windows interrupt mode */ ++typedef enum AC_WINTMODE_enum ++{ ++ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */ ++ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */ ++ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */ ++ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */ ++} AC_WINTMODE_t; ++ ++/* Window interrupt level */ ++typedef enum AC_WINTLVL_enum ++{ ++ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */ ++ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */ ++ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */ ++ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */ ++} AC_WINTLVL_t; ++ ++/* Window mode state */ ++typedef enum AC_WSTATE_enum ++{ ++ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */ ++ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */ ++ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */ ++} AC_WSTATE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++RTC - Real-Time Clounter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Real-Time Counter */ ++typedef struct RTC_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flags */ ++ register8_t TEMP; /* Temporary register */ ++ register8_t reserved_0x05; ++ register8_t CALIB; /* Calibration Register */ ++ register8_t reserved_0x07; ++ _WORDREGISTER(CNT); /* Count Register */ ++ _WORDREGISTER(PER); /* Period Register */ ++ _WORDREGISTER(COMP); /* Compare Register */ ++} RTC_t; ++ ++/* Prescaler Factor */ ++typedef enum RTC_PRESCALER_enum ++{ ++ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */ ++ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */ ++ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */ ++ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */ ++ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */ ++ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */ ++ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */ ++ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */ ++} RTC_PRESCALER_t; ++ ++/* Compare Interrupt level */ ++typedef enum RTC_COMPINTLVL_enum ++{ ++ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} RTC_COMPINTLVL_t; ++ ++/* Overflow Interrupt level */ ++typedef enum RTC_OVFINTLVL_enum ++{ ++ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} RTC_OVFINTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++XCL - XMEGA Custom Logic ++-------------------------------------------------------------------------- ++*/ ++ ++/* XMEGA Custom Logic */ ++typedef struct XCL_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t CTRLF; /* Control Register F */ ++ register8_t CTRLG; /* Control Register G */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t PLC; /* Peripheral Lenght Control Register */ ++ register8_t CNTL; /* Counter Register Low */ ++ register8_t CNTH; /* Counter Register High */ ++ register8_t CMPL; /* Compare Register Low */ ++ register8_t CMPH; /* Compare Register High */ ++ register8_t PERCAPTL; /* Period or Capture Register Low */ ++ register8_t PERCAPTH; /* Period or Capture Register High */ ++} XCL_t; ++ ++/* LUT0 Output Enable */ ++typedef enum XCL_LUTOUTEN_enum ++{ ++ XCL_LUTOUTEN_DISABLE_gc = (0x00<<6), /* LUT0 output disabled */ ++ XCL_LUTOUTEN_PIN0_gc = (0x01<<6), /* LUT0 Output to pin 0 */ ++ XCL_LUTOUTEN_PIN4_gc = (0x02<<6), /* LUT0 Output to pin 4 */ ++} XCL_LUTOUTEN_t; ++ ++/* Port Selection */ ++typedef enum XCL_PORTSEL_enum ++{ ++ XCL_PORTSEL_PC_gc = (0x00<<4), /* Port C for LUT or USARTC0 for PEC */ ++ XCL_PORTSEL_PD_gc = (0x01<<4), /* Port D for LUT or USARTD0 for PEC */ ++} XCL_PORTSEL_t; ++ ++/* LUT Configuration */ ++typedef enum XCL_LUTCONF_enum ++{ ++ XCL_LUTCONF_2LUT2IN_gc = (0x00<<0), /* 2-Input two LUT */ ++ XCL_LUTCONF_2LUT1IN_gc = (0x01<<0), /* Two LUT with duplicated input */ ++ XCL_LUTCONF_2LUT3IN_gc = (0x02<<0), /* Two LUT with one common input */ ++ XCL_LUTCONF_1LUT3IN_gc = (0x03<<0), /* 3-Input LUT */ ++ XCL_LUTCONF_MUX_gc = (0x04<<0), /* One LUT Mux */ ++ XCL_LUTCONF_DLATCH_gc = (0x05<<0), /* One D-Latch LUT */ ++ XCL_LUTCONF_RSLATCH_gc = (0x06<<0), /* One RS-Latch LUT */ ++ XCL_LUTCONF_DFF_gc = (0x07<<0), /* One DFF LUT */ ++} XCL_LUTCONF_t; ++ ++/* Input Selection */ ++typedef enum XCL_INSEL_enum ++{ ++ XCL_INSEL_EVSYS_gc = (0x00<<6), /* Event system selected as source */ ++ XCL_INSEL_XCL_gc = (0x01<<6), /* XCL selected as source */ ++ XCL_INSEL_PINL_gc = (0x02<<6), /* LSB port pin selected as source */ ++ XCL_INSEL_PINH_gc = (0x03<<6), /* MSB port pin selected as source */ ++} XCL_INSEL_t; ++ ++/* Delay Configuration on LUT */ ++typedef enum XCL_DLYCONF_enum ++{ ++ XCL_DLYCONF_DISABLE_gc = (0x00<<2), /* Delay element disabled */ ++ XCL_DLYCONF_IN_gc = (0x01<<2), /* Delay enabled on LUT input */ ++ XCL_DLYCONF_OUT_gc = (0x02<<2), /* Delay enabled on LUT output */ ++} XCL_DLYCONF_t; ++ ++/* Delay Selection */ ++typedef enum XCL_DLYSEL_enum ++{ ++ XCL_DLYSEL_DLY11_gc = (0x00<<4), /* One cycle delay for each LUT1 and LUT0 */ ++ XCL_DLYSEL_DLY12_gc = (0x01<<4), /* One cycle delay for LUT1 and two cycles for LUT0 */ ++ XCL_DLYSEL_DLY21_gc = (0x02<<4), /* Two cycles delay for LUT1 and one cycle for LUT0 */ ++ XCL_DLYSEL_DLY22_gc = (0x03<<4), /* Two cycle delays for each LUT1 and LUT0 */ ++} XCL_DLYSEL_t; ++ ++/* Clock Selection */ ++typedef enum XCL_CLKSEL_enum ++{ ++ XCL_CLKSEL_OFF_gc = (0x00<<0), /* OFF */ ++ XCL_CLKSEL_DIV1_gc = (0x01<<0), /* Prescaler clk */ ++ XCL_CLKSEL_DIV2_gc = (0x02<<0), /* Prescaler clk/2 */ ++ XCL_CLKSEL_DIV4_gc = (0x03<<0), /* Prescaler clk/4 */ ++ XCL_CLKSEL_DIV8_gc = (0x04<<0), /* Prescaler clk/8 */ ++ XCL_CLKSEL_DIV64_gc = (0x05<<0), /* Prescaler clk/64 */ ++ XCL_CLKSEL_DIV256_gc = (0x06<<0), /* Prescaler clk/256 */ ++ XCL_CLKSEL_DIV1024_gc = (0x07<<0), /* Prescaler clk/1024 */ ++ XCL_CLKSEL_EVCH0_gc = (0x08<<0), /* Event channel 0 */ ++ XCL_CLKSEL_EVCH1_gc = (0x09<<0), /* Event channel 1 */ ++ XCL_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event channel 2 */ ++ XCL_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event channel 3 */ ++ XCL_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event channel 4 */ ++ XCL_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event channel 5 */ ++ XCL_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event channel 6 */ ++ XCL_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event channel 7 */ ++} XCL_CLKSEL_t; ++ ++/* Timer/Counter Command Selection */ ++typedef enum XCL_CMDSEL_enum ++{ ++ XCL_CMDSEL_NONE_gc = (0x00<<7), /* None */ ++ XCL_CMDSEL_RESTART_gc = (0x01<<7), /* Force restart */ ++} XCL_CMDSEL_t; ++ ++/* Timer/Counter Selection */ ++typedef enum XCL_TCSEL_enum ++{ ++ XCL_TCSEL_TC16_gc = (0x00<<4), /* 16-bit timer/counter */ ++ XCL_TCSEL_BTC0_gc = (0x01<<4), /* One 8-bit timer/counter */ ++ XCL_TCSEL_BTC01_gc = (0x02<<4), /* Two 8-bit timer/counters */ ++ XCL_TCSEL_BTC0PEC1_gc = (0x03<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ ++ XCL_TCSEL_PEC0BTC1_gc = (0x04<<4), /* One 8-bit timer/counter and one 8-bit peripheral counter */ ++ XCL_TCSEL_PEC01_gc = (0x05<<4), /* Two 8-bit peripheral counters */ ++ XCL_TCSEL_BTC0PEC2_gc = (0x06<<4), /* One 8-bit timer/counter and two 4-bit peripheral counters */ ++} XCL_TCSEL_t; ++ ++/* Timer/Counter Mode */ ++typedef enum XCL_TCMODE_enum ++{ ++ XCL_TCMODE_NORMAL_gc = (0x00<<0), /* Normal mode with compare/period */ ++ XCL_TCMODE_CAPT_gc = (0x01<<0), /* Capture mode */ ++ XCL_TCMODE_PWM_gc = (0x02<<0), /* Single Slope PWM */ ++} XCL_TCMODE_t; ++ ++/* Compare Output Value Timer */ ++typedef enum XCL_CMPEN_enum ++{ ++ XCL_CMPEN_CLEAR_gc = (0x00<<5), /* Clear WG Output */ ++ XCL_CMPEN_SET_gc = (0x01<<5), /* Set WG Output */ ++} XCL_CMPEN_t; ++ ++/* Command Enable */ ++typedef enum XCL_CMDEN_enum ++{ ++ XCL_CMDEN_DISABLE_gc = (0x00<<6), /* Command Ignored */ ++ XCL_CMDEN_CMD0_gc = (0x01<<6), /* Command valid for timer/counter 0 */ ++ XCL_CMDEN_CMD1_gc = (0x02<<6), /* Command valid for timer/counter 1 */ ++ XCL_CMDEN_CMD01_gc = (0x03<<6), /* Command valid for both timer/counter 0 and 1 */ ++} XCL_CMDEN_t; ++ ++/* Timer/Counter Event Source Selection */ ++typedef enum XCL_EVSRC_enum ++{ ++ XCL_EVSRC_EVCH0_gc = (0x00<<0), /* Event channel 0 */ ++ XCL_EVSRC_EVCH1_gc = (0x01<<0), /* Event channel 1 */ ++ XCL_EVSRC_EVCH2_gc = (0x02<<0), /* Event channel 2 */ ++ XCL_EVSRC_EVCH3_gc = (0x03<<0), /* Event channel 3 */ ++ XCL_EVSRC_EVCH4_gc = (0x04<<0), /* Event channel 4 */ ++ XCL_EVSRC_EVCH5_gc = (0x05<<0), /* Event channel 5 */ ++ XCL_EVSRC_EVCH6_gc = (0x06<<0), /* Event channel 6 */ ++ XCL_EVSRC_EVCH7_gc = (0x07<<0), /* Event channel 7 */ ++} XCL_EVSRC_t; ++ ++/* Timer/Counter Event Action Selection */ ++typedef enum XCL_EVACT_enum ++{ ++ XCL_EVACT_INPUT_gc = (0x00<<5), /* Input Capture */ ++ XCL_EVACT_FREQ_gc = (0x01<<5), /* Frequency Capture */ ++ XCL_EVACT_PW_gc = (0x02<<5), /* Pulse Width Capture */ ++ XCL_EVACT_RESTART_gc = (0x03<<5), /* Restart timer/counter */ ++} XCL_EVACT_t; ++ ++/* Underflow Interrupt level */ ++typedef enum XCL_UNF_INTLVL_enum ++{ ++ XCL_UNF_INTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ XCL_UNF_INTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ XCL_UNF_INTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ XCL_UNF_INTLVL_HI_gc = (0x03<<2), /* High Level */ ++} XCL_UNF_INTLVL_t; ++ ++/* Compare/Capture Interrupt level */ ++typedef enum XCL_CC_INTLVL_enum ++{ ++ XCL_CC_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ XCL_CC_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ XCL_CC_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ XCL_CC_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} XCL_CC_INTLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TWI - Two-Wire Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* */ ++typedef struct TWI_MASTER_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t STATUS; /* Status Register */ ++ register8_t BAUD; /* Baurd Rate Control Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++} TWI_MASTER_t; ++ ++ ++/* */ ++typedef struct TWI_SLAVE_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t STATUS; /* Status Register */ ++ register8_t ADDR; /* Address Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t ADDRMASK; /* Address Mask Register */ ++} TWI_SLAVE_t; ++ ++ ++/* */ ++typedef struct TWI_TIMEOUT_struct ++{ ++ register8_t TOS; /* Timeout Status Register */ ++ register8_t TOCONF; /* Timeout Configuration Register */ ++} TWI_TIMEOUT_t; ++ ++ ++/* Two-Wire Interface */ ++typedef struct TWI_struct ++{ ++ register8_t CTRL; /* TWI Common Control Register */ ++ TWI_MASTER_t MASTER; /* TWI master module */ ++ TWI_SLAVE_t SLAVE; /* TWI slave module */ ++ TWI_TIMEOUT_t TIMEOUT; /* TWI SMBUS timeout module */ ++} TWI_t; ++ ++/* SDA Hold Time */ ++typedef enum TWI_SDAHOLD_enum ++{ ++ TWI_SDAHOLD_OFF_gc = (0x00<<4), /* SDA Hold Time off */ ++ TWI_SDAHOLD_50NS_gc = (0x01<<4), /* SDA Hold Time 50 ns */ ++ TWI_SDAHOLD_300NS_gc = (0x02<<4), /* SDA Hold Time 300 ns */ ++ TWI_SDAHOLD_400NS_gc = (0x03<<4), /* SDA Hold Time 400 ns */ ++} TWI_SDAHOLD_t; ++ ++/* Master Interrupt Level */ ++typedef enum TWI_MASTER_INTLVL_enum ++{ ++ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_MASTER_INTLVL_t; ++ ++/* Inactive Timeout */ ++typedef enum TWI_MASTER_TIMEOUT_enum ++{ ++ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */ ++ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */ ++ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */ ++ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */ ++} TWI_MASTER_TIMEOUT_t; ++ ++/* Master Command */ ++typedef enum TWI_MASTER_CMD_enum ++{ ++ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition */ ++ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */ ++ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */ ++} TWI_MASTER_CMD_t; ++ ++/* Master Bus State */ ++typedef enum TWI_MASTER_BUSSTATE_enum ++{ ++ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */ ++ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */ ++ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus */ ++ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */ ++} TWI_MASTER_BUSSTATE_t; ++ ++/* Slave Interrupt Level */ ++typedef enum TWI_SLAVE_INTLVL_enum ++{ ++ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TWI_SLAVE_INTLVL_t; ++ ++/* Slave Command */ ++typedef enum TWI_SLAVE_CMD_enum ++{ ++ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */ ++ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction */ ++ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to Address/Data Interrupt */ ++} TWI_SLAVE_CMD_t; ++ ++/* Master Timeout */ ++typedef enum TWI_MASTER_TTIMEOUT_enum ++{ ++ TWI_MASTER_TTIMEOUT_25MS_gc = (0x00<<0), /* 25 Milliseconds */ ++ TWI_MASTER_TTIMEOUT_24MS_gc = (0x01<<0), /* 24 Milliseconds */ ++ TWI_MASTER_TTIMEOUT_23MS_gc = (0x02<<0), /* 23 Milliseconds */ ++ TWI_MASTER_TTIMEOUT_22MS_gc = (0x03<<0), /* 22 Milliseconds */ ++ TWI_MASTER_TTIMEOUT_26MS_gc = (0x04<<0), /* 26 Milliseconds */ ++ TWI_MASTER_TTIMEOUT_27MS_gc = (0x05<<0), /* 27 Milliseconds */ ++ TWI_MASTER_TTIMEOUT_28MS_gc = (0x06<<0), /* 28 Milliseconds */ ++ TWI_MASTER_TTIMEOUT_29MS_gc = (0x07<<0), /* 29 Milliseconds */ ++} TWI_MASTER_TTIMEOUT_t; ++ ++/* Slave Ttimeout */ ++typedef enum TWI_SLAVE_TTIMEOUT_enum ++{ ++ TWI_SLAVE_TTIMEOUT_25MS_gc = (0x00<<5), /* 25 Milliseconds */ ++ TWI_SLAVE_TTIMEOUT_24MS_gc = (0x01<<5), /* 24 Milliseconds */ ++ TWI_SLAVE_TTIMEOUT_23MS_gc = (0x02<<5), /* 23 Milliseconds */ ++ TWI_SLAVE_TTIMEOUT_22MS_gc = (0x03<<5), /* 22 Milliseconds */ ++ TWI_SLAVE_TTIMEOUT_26MS_gc = (0x04<<5), /* 26 Milliseconds */ ++ TWI_SLAVE_TTIMEOUT_27MS_gc = (0x05<<5), /* 27 Milliseconds */ ++ TWI_SLAVE_TTIMEOUT_28MS_gc = (0x06<<5), /* 28 Milliseconds */ ++ TWI_SLAVE_TTIMEOUT_29MS_gc = (0x07<<5), /* 29 Milliseconds */ ++} TWI_SLAVE_TTIMEOUT_t; ++ ++/* Master/Slave Extend Timeout */ ++typedef enum TWI_MASTER_TMSEXT_enum ++{ ++ TWI_MASTER_TMSEXT_10MS25MS_gc = (0x00<<3), /* Tmext 10ms Tsext 25ms */ ++ TWI_MASTER_TMSEXT_9MS24MS_gc = (0x01<<3), /* Tmext 9ms Tsext 24ms */ ++ TWI_MASTER_TMSEXT_11MS26MS_gc = (0x02<<3), /* Tmext 11ms Tsext 26ms */ ++ TWI_MASTER_TMSEXT_12MS27MS_gc = (0x03<<3), /* Tmext 12ms Tsext 27ms */ ++} TWI_MASTER_TMSEXT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++PORT - Port Configuration ++-------------------------------------------------------------------------- ++*/ ++ ++/* I/O Ports */ ++typedef struct PORT_struct ++{ ++ register8_t DIR; /* I/O Port Data Direction */ ++ register8_t DIRSET; /* I/O Port Data Direction Set */ ++ register8_t DIRCLR; /* I/O Port Data Direction Clear */ ++ register8_t DIRTGL; /* I/O Port Data Direction Toggle */ ++ register8_t OUT; /* I/O Port Output */ ++ register8_t OUTSET; /* I/O Port Output Set */ ++ register8_t OUTCLR; /* I/O Port Output Clear */ ++ register8_t OUTTGL; /* I/O Port Output Toggle */ ++ register8_t IN; /* I/O port Input */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t INTMASK; /* Port Interrupt Mask */ ++ register8_t reserved_0x0B; ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t REMAP; /* Pin Remap Register */ ++ register8_t reserved_0x0F; ++ register8_t PIN0CTRL; /* Pin 0 Control Register */ ++ register8_t PIN1CTRL; /* Pin 1 Control Register */ ++ register8_t PIN2CTRL; /* Pin 2 Control Register */ ++ register8_t PIN3CTRL; /* Pin 3 Control Register */ ++ register8_t PIN4CTRL; /* Pin 4 Control Register */ ++ register8_t PIN5CTRL; /* Pin 5 Control Register */ ++ register8_t PIN6CTRL; /* Pin 6 Control Register */ ++ register8_t PIN7CTRL; /* Pin 7 Control Register */ ++} PORT_t; ++ ++/* Port Interrupt Level */ ++typedef enum PORT_INTLVL_enum ++{ ++ PORT_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ PORT_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ PORT_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ PORT_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} PORT_INTLVL_t; ++ ++/* Output/Pull Configuration */ ++typedef enum PORT_OPC_enum ++{ ++ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */ ++ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input and Output */ ++ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */ ++ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */ ++ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */ ++ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */ ++ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */ ++ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */ ++} PORT_OPC_t; ++ ++/* Input/Sense Configuration */ ++typedef enum PORT_ISC_enum ++{ ++ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */ ++ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */ ++ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */ ++ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */ ++ PORT_ISC_FORCE_ENABLE_gc = (0x06<<0), /* Digital Input Buffer Forced Enable */ ++ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */ ++} PORT_ISC_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++TC - 16-bit Timer/Counter With PWM ++-------------------------------------------------------------------------- ++*/ ++ ++/* 16-bit Timer/Counter 4 */ ++typedef struct TC4_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t CTRLF; /* Control Register F */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t CTRLHCLR; /* Control Register H Clear */ ++ register8_t CTRLHSET; /* Control Register H Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ _WORDREGISTER(CCC); /* Compare or Capture C */ ++ _WORDREGISTER(CCD); /* Compare or Capture D */ ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */ ++ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */ ++} TC4_t; ++ ++ ++/* 16-bit Timer/Counter 5 */ ++typedef struct TC5_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t CTRLE; /* Control Register E */ ++ register8_t CTRLF; /* Control Register F */ ++ register8_t INTCTRLA; /* Interrupt Control Register A */ ++ register8_t INTCTRLB; /* Interrupt Control Register B */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G Set */ ++ register8_t CTRLHCLR; /* Control Register H Clear */ ++ register8_t CTRLHSET; /* Control Register H Set */ ++ register8_t INTFLAGS; /* Interrupt Flag Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t TEMP; /* Temporary Register For 16-bit Access */ ++ register8_t reserved_0x10; ++ register8_t reserved_0x11; ++ register8_t reserved_0x12; ++ register8_t reserved_0x13; ++ register8_t reserved_0x14; ++ register8_t reserved_0x15; ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t reserved_0x1E; ++ register8_t reserved_0x1F; ++ _WORDREGISTER(CNT); /* Count */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ _WORDREGISTER(PER); /* Period */ ++ _WORDREGISTER(CCA); /* Compare or Capture A */ ++ _WORDREGISTER(CCB); /* Compare or Capture B */ ++ register8_t reserved_0x2C; ++ register8_t reserved_0x2D; ++ register8_t reserved_0x2E; ++ register8_t reserved_0x2F; ++ register8_t reserved_0x30; ++ register8_t reserved_0x31; ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t reserved_0x34; ++ register8_t reserved_0x35; ++ _WORDREGISTER(PERBUF); /* Period Buffer */ ++ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */ ++ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */ ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++} TC5_t; ++ ++/* Clock Selection */ ++typedef enum TC45_CLKSEL_enum ++{ ++ TC45_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */ ++ TC45_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */ ++ TC45_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */ ++ TC45_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */ ++ TC45_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */ ++ TC45_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */ ++ TC45_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */ ++ TC45_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */ ++ TC45_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC45_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC45_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC45_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC45_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC45_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC45_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC45_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC45_CLKSEL_t; ++ ++/* Byte Mode */ ++typedef enum TC45_BYTEM_enum ++{ ++ TC45_BYTEM_NORMAL_gc = (0x00<<6), /* 16-bit mode */ ++ TC45_BYTEM_BYTEMODE_gc = (0x01<<6), /* Timer/Counter Operating in Byte Mode Only */ ++} TC45_BYTEM_t; ++ ++/* Circular Enable Mode */ ++typedef enum TC45_CIRCEN_enum ++{ ++ TC45_CIRCEN_DISABLE_gc = (0x00<<4), /* Circular Buffer Disabled */ ++ TC45_CIRCEN_PER_gc = (0x01<<4), /* Circular Buffer Enabled on PER/PERBUF */ ++ TC45_CIRCEN_CCA_gc = (0x02<<4), /* Circular Buffer Enabled on CCA/CCABUF */ ++ TC45_CIRCEN_BOTH_gc = (0x03<<4), /* Circular Buffer Enabled on All Buffered Registers */ ++} TC45_CIRCEN_t; ++ ++/* Waveform Generation Mode */ ++typedef enum TC45_WGMODE_enum ++{ ++ TC45_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */ ++ TC45_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */ ++ TC45_WGMODE_SINGLESLOPE_gc = (0x03<<0), /* Single Slope */ ++ TC45_WGMODE_DSTOP_gc = (0x05<<0), /* Dual Slope, Update on TOP */ ++ TC45_WGMODE_DSBOTH_gc = (0x06<<0), /* Dual Slope, Both */ ++ TC45_WGMODE_DSBOTTOM_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */ ++} TC45_WGMODE_t; ++ ++/* Event Action */ ++typedef enum TC45_EVACT_enum ++{ ++ TC45_EVACT_OFF_gc = (0x00<<5), /* No Event Action */ ++ TC45_EVACT_FMODE1_gc = (0x01<<5), /* Fault Mode 1 capture */ ++ TC45_EVACT_FMODE2_gc = (0x02<<5), /* Fault Mode 2 capture */ ++ TC45_EVACT_UPDOWN_gc = (0x03<<5), /* Up/down count */ ++ TC45_EVACT_QDEC_gc = (0x04<<5), /* Quadrature decode */ ++ TC45_EVACT_RESTART_gc = (0x05<<5), /* Restart */ ++ TC45_EVACT_PWF_gc = (0x06<<5), /* Pulse-width Capture */ ++} TC45_EVACT_t; ++ ++/* Event Selection */ ++typedef enum TC45_EVSEL_enum ++{ ++ TC45_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ TC45_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */ ++ TC45_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */ ++ TC45_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */ ++ TC45_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */ ++ TC45_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */ ++ TC45_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */ ++ TC45_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */ ++ TC45_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */ ++} TC45_EVSEL_t; ++ ++/* Compare or Capture Channel A Mode */ ++typedef enum TC45_CCAMODE_enum ++{ ++ TC45_CCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ ++ TC45_CCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ ++ TC45_CCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ ++ TC45_CCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ ++} TC45_CCAMODE_t; ++ ++/* Compare or Capture Channel B Mode */ ++typedef enum TC45_CCBMODE_enum ++{ ++ TC45_CCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ ++ TC45_CCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ ++ TC45_CCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ ++ TC45_CCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ ++} TC45_CCBMODE_t; ++ ++/* Compare or Capture Channel C Mode */ ++typedef enum TC45_CCCMODE_enum ++{ ++ TC45_CCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ ++ TC45_CCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ ++ TC45_CCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ ++ TC45_CCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ ++} TC45_CCCMODE_t; ++ ++/* Compare or Capture Channel D Mode */ ++typedef enum TC45_CCDMODE_enum ++{ ++ TC45_CCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ ++ TC45_CCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ ++ TC45_CCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ ++ TC45_CCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ ++} TC45_CCDMODE_t; ++ ++/* Compare or Capture Low Channel A Mode */ ++typedef enum TC45_LCCAMODE_enum ++{ ++ TC45_LCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ ++ TC45_LCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ ++ TC45_LCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ ++ TC45_LCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ ++} TC45_LCCAMODE_t; ++ ++/* Compare or Capture Low Channel B Mode */ ++typedef enum TC45_LCCBMODE_enum ++{ ++ TC45_LCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ ++ TC45_LCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ ++ TC45_LCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ ++ TC45_LCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ ++} TC45_LCCBMODE_t; ++ ++/* Compare or Capture Low Channel C Mode */ ++typedef enum TC45_LCCCMODE_enum ++{ ++ TC45_LCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ ++ TC45_LCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ ++ TC45_LCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ ++ TC45_LCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ ++} TC45_LCCCMODE_t; ++ ++/* Compare or Capture Low Channel D Mode */ ++typedef enum TC45_LCCDMODE_enum ++{ ++ TC45_LCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ ++ TC45_LCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ ++ TC45_LCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ ++ TC45_LCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ ++} TC45_LCCDMODE_t; ++ ++/* Compare or Capture High Channel A Mode */ ++typedef enum TC45_HCCAMODE_enum ++{ ++ TC45_HCCAMODE_DISABLE_gc = (0x00<<0), /* Channel Disabled */ ++ TC45_HCCAMODE_COMP_gc = (0x01<<0), /* Ouput Compare enabled */ ++ TC45_HCCAMODE_CAPT_gc = (0x02<<0), /* Input Capture enabled */ ++ TC45_HCCAMODE_BOTHCC_gc = (0x03<<0), /* Both Compare and Capture enabled */ ++} TC45_HCCAMODE_t; ++ ++/* Compare or Capture High Channel B Mode */ ++typedef enum TC45_HCCBMODE_enum ++{ ++ TC45_HCCBMODE_DISABLE_gc = (0x00<<2), /* Channel Disabled */ ++ TC45_HCCBMODE_COMP_gc = (0x01<<2), /* Ouput Compare enabled */ ++ TC45_HCCBMODE_CAPT_gc = (0x02<<2), /* Input Capture enabled */ ++ TC45_HCCBMODE_BOTHCC_gc = (0x03<<2), /* Both Compare and Capture enabled */ ++} TC45_HCCBMODE_t; ++ ++/* Compare or Capture High Channel C Mode */ ++typedef enum TC45_HCCCMODE_enum ++{ ++ TC45_HCCCMODE_DISABLE_gc = (0x00<<4), /* Channel Disabled */ ++ TC45_HCCCMODE_COMP_gc = (0x01<<4), /* Ouput Compare enabled */ ++ TC45_HCCCMODE_CAPT_gc = (0x02<<4), /* Input Capture enabled */ ++ TC45_HCCCMODE_BOTHCC_gc = (0x03<<4), /* Both Compare and Capture enabled */ ++} TC45_HCCCMODE_t; ++ ++/* Compare or Capture High Channel D Mode */ ++typedef enum TC45_HCCDMODE_enum ++{ ++ TC45_HCCDMODE_DISABLE_gc = (0x00<<6), /* Channel Disabled */ ++ TC45_HCCDMODE_COMP_gc = (0x01<<6), /* Ouput Compare enabled */ ++ TC45_HCCDMODE_CAPT_gc = (0x02<<6), /* Input Capture enabled */ ++ TC45_HCCDMODE_BOTHCC_gc = (0x03<<6), /* Both Compare and Capture enabled */ ++} TC45_HCCDMODE_t; ++ ++/* Timer Trigger Restart Interrupt Level */ ++typedef enum TC45_TRGINTLVL_enum ++{ ++ TC45_TRGINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC45_TRGINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC45_TRGINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC45_TRGINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC45_TRGINTLVL_t; ++ ++/* Error Interrupt Level */ ++typedef enum TC45_ERRINTLVL_enum ++{ ++ TC45_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC45_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC45_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC45_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC45_ERRINTLVL_t; ++ ++/* Overflow Interrupt Level */ ++typedef enum TC45_OVFINTLVL_enum ++{ ++ TC45_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC45_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC45_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC45_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC45_OVFINTLVL_t; ++ ++/* Compare or Capture Channel A Interrupt Level */ ++typedef enum TC45_CCAINTLVL_enum ++{ ++ TC45_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC45_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC45_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC45_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC45_CCAINTLVL_t; ++ ++/* Compare or Capture Channel B Interrupt Level */ ++typedef enum TC45_CCBINTLVL_enum ++{ ++ TC45_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC45_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC45_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC45_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC45_CCBINTLVL_t; ++ ++/* Compare or Capture Channel C Interrupt Level */ ++typedef enum TC45_CCCINTLVL_enum ++{ ++ TC45_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC45_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC45_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC45_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC45_CCCINTLVL_t; ++ ++/* Compare or Capture Channel D Interrupt Level */ ++typedef enum TC45_CCDINTLVL_enum ++{ ++ TC45_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC45_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC45_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC45_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC45_CCDINTLVL_t; ++ ++/* Compare or Capture Low Channel A Interrupt Level */ ++typedef enum TC45_LCCAINTLVL_enum ++{ ++ TC45_LCCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ TC45_LCCAINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ TC45_LCCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ TC45_LCCAINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} TC45_LCCAINTLVL_t; ++ ++/* Compare or Capture Low Channel B Interrupt Level */ ++typedef enum TC45_LCCBINTLVL_enum ++{ ++ TC45_LCCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ TC45_LCCBINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ TC45_LCCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ TC45_LCCBINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} TC45_LCCBINTLVL_t; ++ ++/* Compare or Capture Low Channel C Interrupt Level */ ++typedef enum TC45_LCCCINTLVL_enum ++{ ++ TC45_LCCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ TC45_LCCCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ TC45_LCCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ TC45_LCCCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} TC45_LCCCINTLVL_t; ++ ++/* Compare or Capture Low Channel D Interrupt Level */ ++typedef enum TC45_LCCDINTLVL_enum ++{ ++ TC45_LCCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */ ++ TC45_LCCDINTLVL_LO_gc = (0x01<<6), /* Low Level */ ++ TC45_LCCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */ ++ TC45_LCCDINTLVL_HI_gc = (0x03<<6), /* High Level */ ++} TC45_LCCDINTLVL_t; ++ ++/* Timer/Counter Command */ ++typedef enum TC45_CMD_enum ++{ ++ TC45_CMD_NONE_gc = (0x00<<2), /* No Command */ ++ TC45_CMD_UPDATE_gc = (0x01<<2), /* Force Update */ ++ TC45_CMD_RESTART_gc = (0x02<<2), /* Force Restart */ ++ TC45_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */ ++} TC45_CMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FAULT - Fault Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Fault Extension */ ++typedef struct FAULT_struct ++{ ++ register8_t CTRLA; /* Control A Register */ ++ register8_t CTRLB; /* Control B Register */ ++ register8_t CTRLC; /* Control C Register */ ++ register8_t CTRLD; /* Control D Register */ ++ register8_t CTRLE; /* Control E Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRLGCLR; /* Control Register G Clear */ ++ register8_t CTRLGSET; /* Control Register G set */ ++} FAULT_t; ++ ++/* Ramp Mode Selection */ ++typedef enum FAULT_RAMP_enum ++{ ++ FAULT_RAMP_RAMP1_gc = (0x00<<6), /* Normal Mode */ ++ FAULT_RAMP_RAMP2_gc = (0x02<<6), /* RAMP2 Mode */ ++} FAULT_RAMP_t; ++ ++/* Fault E Input Source Selection */ ++typedef enum FAULT_SRCE_enum ++{ ++ FAULT_SRCE_DISABLE_gc = (0x00<<0), /* Fault Protection Disabled */ ++ FAULT_SRCE_CHN_gc = (0x01<<0), /* Event Channel n */ ++ FAULT_SRCE_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ ++ FAULT_SRCE_CHN2_gc = (0x03<<0), /* Event Channel n+2 */ ++} FAULT_SRCE_t; ++ ++/* Fault A Halt Action Selection */ ++typedef enum FAULT_HALTA_enum ++{ ++ FAULT_HALTA_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ ++ FAULT_HALTA_HW_gc = (0x01<<5), /* Hardware Halt Action */ ++ FAULT_HALTA_SW_gc = (0x02<<5), /* Software Halt Action */ ++} FAULT_HALTA_t; ++ ++/* Fault A Source Selection */ ++typedef enum FAULT_SRCA_enum ++{ ++ FAULT_SRCA_DISABLE_gc = (0x00<<0), /* Fault A Disabled */ ++ FAULT_SRCA_CHN_gc = (0x01<<0), /* Event Channel n */ ++ FAULT_SRCA_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ ++ FAULT_SRCA_LINK_gc = (0x03<<0), /* Fault A linked to Fault B State from previous cycle */ ++} FAULT_SRCA_t; ++ ++/* Fault B Halt Action Selection */ ++typedef enum FAULT_HALTB_enum ++{ ++ FAULT_HALTB_DISABLE_gc = (0x00<<5), /* Halt Action Disabled */ ++ FAULT_HALTB_HW_gc = (0x01<<5), /* Hardware Halt Action */ ++ FAULT_HALTB_SW_gc = (0x02<<5), /* Software Halt Action */ ++} FAULT_HALTB_t; ++ ++/* Fault B Source Selection */ ++typedef enum FAULT_SRCB_enum ++{ ++ FAULT_SRCB_DISABLE_gc = (0x00<<0), /* Fault B disabled */ ++ FAULT_SRCB_CHN_gc = (0x01<<0), /* Event Channel n */ ++ FAULT_SRCB_CHN1_gc = (0x02<<0), /* Event Channel n+1 */ ++ FAULT_SRCB_LINK_gc = (0x03<<0), /* Fault B linked to Fault A State from previous cycle */ ++} FAULT_SRCB_t; ++ ++/* Channel index Command */ ++typedef enum FAULT_IDXCMD_enum ++{ ++ FAULT_IDXCMD_DISABLE_gc = (0x00<<3), /* Command Disabled */ ++ FAULT_IDXCMD_SET_gc = (0x01<<3), /* Force Cycle B in Next Cycle */ ++ FAULT_IDXCMD_CLEAR_gc = (0x02<<3), /* Force Cycle A in Next Cycle */ ++ FAULT_IDXCMD_HOLD_gc = (0x03<<3), /* Hold Current Cycle Index in Next Cycle */ ++} FAULT_IDXCMD_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++WEX - Waveform Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* Waveform Extension */ ++typedef struct WEX_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t DTBOTH; /* Dead-time Concurrent Write to Both Sides Register */ ++ register8_t DTLS; /* Dead-time Low Side Register */ ++ register8_t DTHS; /* Dead-time High Side Register */ ++ register8_t STATUSCLR; /* Status Clear Register */ ++ register8_t STATUSSET; /* Status Set Register */ ++ register8_t SWAP; /* Swap Register */ ++ register8_t PGO; /* Pattern Generation Override Register */ ++ register8_t PGV; /* Pattern Generation Value Register */ ++ register8_t reserved_0x09; ++ register8_t SWAPBUF; /* Dead Time Low Side Buffer */ ++ register8_t PGOBUF; /* Pattern Generation Overwrite Buffer Register */ ++ register8_t PGVBUF; /* Pattern Generation Value Buffer Register */ ++ register8_t reserved_0x0D; ++ register8_t reserved_0x0E; ++ register8_t OUTOVDIS; /* Output Override Disable Register */ ++} WEX_t; ++ ++/* Output Matrix Mode */ ++typedef enum WEX_OTMX_enum ++{ ++ WEX_OTMX_DEFAULT_gc = (0x00<<4), /* Default Ouput Matrix Mode */ ++ WEX_OTMX_FIRST_gc = (0x01<<4), /* First Output matrix Mode */ ++ WEX_OTMX_SECOND_gc = (0x02<<4), /* Second Output matrix Mode */ ++ WEX_OTMX_THIRD_gc = (0x03<<4), /* Third Output matrix Mode */ ++ WEX_OTMX_FOURTH_gc = (0x04<<4), /* Fourth Output matrix Mode */ ++} WEX_OTMX_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++HIRES - High-Resolution Extension ++-------------------------------------------------------------------------- ++*/ ++ ++/* High-Resolution Extension */ ++typedef struct HIRES_struct ++{ ++ register8_t CTRLA; /* Control Register A */ ++} HIRES_t; ++ ++/* High Resolution Plus Mode */ ++typedef enum HIRES_HRPLUS_enum ++{ ++ HIRES_HRPLUS_NONE_gc = (0x00<<2), /* No Hi-Res Plus */ ++ HIRES_HRPLUS_HRP4_gc = (0x01<<2), /* Hi-Res Plus enabled on Timer 4 */ ++ HIRES_HRPLUS_HRP5_gc = (0x02<<2), /* Hi-Res Plus enabled on Timer 5 */ ++ HIRES_HRPLUS_BOTH_gc = (0x03<<2), /* Hi-Res Plus enabled on Timer 4 and 5 */ ++} HIRES_HRPLUS_t; ++ ++/* High Resolution Mode */ ++typedef enum HIRES_HREN_enum ++{ ++ HIRES_HREN_NONE_gc = (0x00<<0), /* No Hi-Res */ ++ HIRES_HREN_HRP4_gc = (0x01<<0), /* Hi-Res enabled on Timer 4 */ ++ HIRES_HREN_HRP5_gc = (0x02<<0), /* Hi-Res enabled on Timer 5 */ ++ HIRES_HREN_BOTH_gc = (0x03<<0), /* Hi-Res enabled on Timer 4 and 5 */ ++} HIRES_HREN_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++USART - Universal Asynchronous Receiver-Transmitter ++-------------------------------------------------------------------------- ++*/ ++ ++/* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++typedef struct USART_struct ++{ ++ register8_t DATA; /* Data Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t CTRLA; /* Control Register A */ ++ register8_t CTRLB; /* Control Register B */ ++ register8_t CTRLC; /* Control Register C */ ++ register8_t CTRLD; /* Control Register D */ ++ register8_t BAUDCTRLA; /* Baud Rate Control Register A */ ++ register8_t BAUDCTRLB; /* Baud Rate Control Register B */ ++} USART_t; ++ ++/* Receive Start Interrupt level */ ++typedef enum USART_RXSINTLVL_enum ++{ ++ USART_RXSINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_RXSINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_RXSINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_RXSINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_RXSINTLVL_t; ++ ++/* Receive Complete Interrupt level */ ++typedef enum USART_RXCINTLVL_enum ++{ ++ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */ ++ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */ ++ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */ ++ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */ ++} USART_RXCINTLVL_t; ++ ++/* Transmit Complete Interrupt level */ ++typedef enum USART_TXCINTLVL_enum ++{ ++ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */ ++ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */ ++ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */ ++ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */ ++} USART_TXCINTLVL_t; ++ ++/* Data Register Empty Interrupt level */ ++typedef enum USART_DREINTLVL_enum ++{ ++ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */ ++} USART_DREINTLVL_t; ++ ++/* Character Size */ ++typedef enum USART_CHSIZE_enum ++{ ++ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */ ++ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */ ++ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */ ++ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */ ++ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */ ++} USART_CHSIZE_t; ++ ++/* Communication Mode */ ++typedef enum USART_CMODE_enum ++{ ++ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */ ++ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */ ++ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */ ++ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */ ++} USART_CMODE_t; ++ ++/* Parity Mode */ ++typedef enum USART_PMODE_enum ++{ ++ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */ ++ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */ ++ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */ ++} USART_PMODE_t; ++ ++/* Encoding and Decoding Type */ ++typedef enum USART_DECTYPE_enum ++{ ++ USART_DECTYPE_DATA_gc = (0x00<<4), /* DATA Field Encoding */ ++ USART_DECTYPE_SDATA_gc = (0x02<<4), /* Start and Data Fields Encoding */ ++ USART_DECTYPE_NOTSDATA_gc = (0x03<<4), /* Start and Data Fields Encoding, with invertion in START field */ ++} USART_DECTYPE_t; ++ ++/* XCL LUT Action */ ++typedef enum USART_LUTACT_enum ++{ ++ USART_LUTACT_OFF_gc = (0x00<<2), /* Standard Frame Configuration */ ++ USART_LUTACT_RX_gc = (0x01<<2), /* Receiver Decoding Enabled */ ++ USART_LUTACT_TX_gc = (0x02<<2), /* Transmitter Encoding Enabled */ ++ USART_LUTACT_BOTH_gc = (0x03<<2), /* Both Encoding and Decoding Enabled */ ++} USART_LUTACT_t; ++ ++/* XCL Peripheral Counter Action */ ++typedef enum USART_PECACT_enum ++{ ++ USART_PECACT_OFF_gc = (0x00<<0), /* Standard Mode */ ++ USART_PECACT_PEC0_gc = (0x01<<0), /* Variable Data Lenght in Reception */ ++ USART_PECACT_PEC1_gc = (0x02<<0), /* Variable Data Lenght in Transmission */ ++ USART_PECACT_PERC01_gc = (0x03<<0), /* Variable Data Lenght in both Reception and Transmission */ ++} USART_PECACT_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SPI - Serial Peripheral Interface ++-------------------------------------------------------------------------- ++*/ ++ ++/* Serial Peripheral Interface with Buffer Modes */ ++typedef struct SPI_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t INTCTRL; /* Interrupt Control Register */ ++ register8_t STATUS; /* Status Register */ ++ register8_t DATA; /* Data Register */ ++ register8_t CTRLB; /* Control Register B */ ++} SPI_t; ++ ++/* SPI Mode */ ++typedef enum SPI_MODE_enum ++{ ++ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0, base clock at "0", sampling on leading edge (rising) & set-up on trailling edge (falling). */ ++ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1, base clock at "0", set-up on leading edge (rising) & sampling on trailling edge (falling). */ ++ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2, base clock at "1", sampling on leading edge (falling) & set-up on trailling edge (rising). */ ++ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3, base clock at "1", set-up on leading edge (falling) & sampling on trailling edge (rising). */ ++} SPI_MODE_t; ++ ++/* Prescaler setting */ ++typedef enum SPI_PRESCALER_enum ++{ ++ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* If CLK2X=1 CLKper/2, else (CLK2X=0) CLKper/4. */ ++ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* If CLK2X=1 CLKper/8, else (CLK2X=0) CLKper/16. */ ++ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* If CLK2X=1 CLKper/32, else (CLK2X=0) CLKper/64. */ ++ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* If CLK2X=1 CLKper/64, else (CLK2X=0) CLKper/128. */ ++} SPI_PRESCALER_t; ++ ++/* Interrupt level */ ++typedef enum SPI_INTLVL_enum ++{ ++ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */ ++ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */ ++ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */ ++ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */ ++} SPI_INTLVL_t; ++ ++/* Buffer Modes */ ++typedef enum SPI_BUFMODE_enum ++{ ++ SPI_BUFMODE_OFF_gc = (0x00<<6), /* SPI Unbuffered Mode */ ++ SPI_BUFMODE_BUFMODE1_gc = (0x02<<6), /* Buffer Mode 1 (with dummy byte) */ ++ SPI_BUFMODE_BUFMODE2_gc = (0x03<<6), /* Buffer Mode 2 (no dummy byte) */ ++} SPI_BUFMODE_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++IRCOM - IR Communication Module ++-------------------------------------------------------------------------- ++*/ ++ ++/* IR Communication Module */ ++typedef struct IRCOM_struct ++{ ++ register8_t CTRL; /* Control Register */ ++ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */ ++ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */ ++} IRCOM_t; ++ ++/* Event channel selection */ ++typedef enum IRDA_EVSEL_enum ++{ ++ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */ ++ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */ ++ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */ ++ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */ ++ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */ ++ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */ ++ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */ ++ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */ ++ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */ ++} IRDA_EVSEL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++FUSE - Fuses and Lockbits ++-------------------------------------------------------------------------- ++*/ ++ ++/* Lock Bits */ ++typedef struct NVM_LOCKBITS_struct ++{ ++ register8_t LOCKBITS; /* Lock Bits */ ++} NVM_LOCKBITS_t; ++ ++ ++/* Fuses */ ++typedef struct NVM_FUSES_struct ++{ ++ register8_t reserved_0x00; ++ register8_t FUSEBYTE1; /* Watchdog Configuration */ ++ register8_t FUSEBYTE2; /* Reset Configuration */ ++ register8_t reserved_0x03; ++ register8_t FUSEBYTE4; /* Start-up Configuration */ ++ register8_t FUSEBYTE5; /* EESAVE and BOD Level */ ++ register8_t FUSEBYTE6; /* Fault State */ ++} NVM_FUSES_t; ++ ++/* Boot lock bits - boot setcion */ ++typedef enum FUSE_BLBB_enum ++{ ++ FUSE_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */ ++ FUSE_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */ ++ FUSE_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */ ++ FUSE_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */ ++} FUSE_BLBB_t; ++ ++/* Boot lock bits - application section */ ++typedef enum FUSE_BLBA_enum ++{ ++ FUSE_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */ ++ FUSE_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */ ++ FUSE_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */ ++ FUSE_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */ ++} FUSE_BLBA_t; ++ ++/* Boot lock bits - application table section */ ++typedef enum FUSE_BLBAT_enum ++{ ++ FUSE_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */ ++ FUSE_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */ ++ FUSE_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */ ++ FUSE_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */ ++} FUSE_BLBAT_t; ++ ++/* Lock bits */ ++typedef enum FUSE_LB_enum ++{ ++ FUSE_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */ ++ FUSE_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */ ++ FUSE_LB_NOLOCK_gc = (0x03<<0), /* No locks */ ++} FUSE_LB_t; ++ ++/* Boot Loader Section Reset Vector */ ++typedef enum BOOTRST_enum ++{ ++ BOOTRST_BOOTLDR_gc = (0x00<<6), /* Boot Loader Reset */ ++ BOOTRST_APPLICATION_gc = (0x01<<6), /* Application Reset */ ++} BOOTRST_t; ++ ++/* BOD operation */ ++typedef enum BOD_enum ++{ ++ BOD_SAMPLED_gc = (0x01<<4), /* BOD enabled in sampled mode */ ++ BOD_CONTINUOUS_gc = (0x02<<4), /* BOD enabled continuously */ ++ BOD_DISABLED_gc = (0x03<<4), /* BOD Disabled */ ++} BOD_t; ++ ++/* Watchdog (Window) Timeout Period */ ++typedef enum WD_enum ++{ ++ WD_8CLK_gc = (0x00<<4), /* 8 cycles (8ms @ 3.3V) */ ++ WD_16CLK_gc = (0x01<<4), /* 16 cycles (16ms @ 3.3V) */ ++ WD_32CLK_gc = (0x02<<4), /* 32 cycles (32ms @ 3.3V) */ ++ WD_64CLK_gc = (0x03<<4), /* 64 cycles (64ms @ 3.3V) */ ++ WD_128CLK_gc = (0x04<<4), /* 128 cycles (0.125s @ 3.3V) */ ++ WD_256CLK_gc = (0x05<<4), /* 256 cycles (0.25s @ 3.3V) */ ++ WD_512CLK_gc = (0x06<<4), /* 512 cycles (0.5s @ 3.3V) */ ++ WD_1KCLK_gc = (0x07<<4), /* 1K cycles (1s @ 3.3V) */ ++ WD_2KCLK_gc = (0x08<<4), /* 2K cycles (2s @ 3.3V) */ ++ WD_4KCLK_gc = (0x09<<4), /* 4K cycles (4s @ 3.3V) */ ++ WD_8KCLK_gc = (0x0A<<4), /* 8K cycles (8s @ 3.3V) */ ++} WD_t; ++ ++/* Start-up Time */ ++typedef enum SUT_enum ++{ ++ SUT_0MS_gc = (0x03<<2), /* 0 ms */ ++ SUT_4MS_gc = (0x01<<2), /* 4 ms */ ++ SUT_64MS_gc = (0x00<<2), /* 64 ms */ ++} SUT_t; ++ ++/* Brownout Detection Voltage Level */ ++typedef enum BODLVL_enum ++{ ++ BODLVL_1V6_gc = (0x07<<0), /* 1.6 V */ ++ BODLVL_1V8_gc = (0x06<<0), /* 1.8 V */ ++ BODLVL_2V0_gc = (0x05<<0), /* 2.0 V */ ++ BODLVL_2V2_gc = (0x04<<0), /* 2.2 V */ ++ BODLVL_2V4_gc = (0x03<<0), /* 2.4 V */ ++ BODLVL_2V6_gc = (0x02<<0), /* 2.6 V */ ++ BODLVL_2V8_gc = (0x01<<0), /* 2.8 V */ ++ BODLVL_3V0_gc = (0x00<<0), /* 3.0 V */ ++} BODLVL_t; ++ ++ ++/* ++-------------------------------------------------------------------------- ++SIGROW - Signature Row ++-------------------------------------------------------------------------- ++*/ ++ ++/* Production Signatures */ ++typedef struct NVM_PROD_SIGNATURES_struct ++{ ++ register8_t RCOSC8M; /* RCOSC 8MHz Calibration Value */ ++ register8_t reserved_0x01; ++ register8_t RCOSC32K; /* RCOSC 32.768 kHz Calibration Value */ ++ register8_t RCOSC32M; /* RCOSC 32 MHz Calibration Value B */ ++ register8_t RCOSC32MA; /* RCOSC 32 MHz Calibration Value A */ ++ register8_t reserved_0x05; ++ register8_t reserved_0x06; ++ register8_t reserved_0x07; ++ register8_t LOTNUM0; /* Lot Number Byte 0, ASCII */ ++ register8_t LOTNUM1; /* Lot Number Byte 1, ASCII */ ++ register8_t LOTNUM2; /* Lot Number Byte 2, ASCII */ ++ register8_t LOTNUM3; /* Lot Number Byte 3, ASCII */ ++ register8_t LOTNUM4; /* Lot Number Byte 4, ASCII */ ++ register8_t LOTNUM5; /* Lot Number Byte 5, ASCII */ ++ register8_t reserved_0x0E; ++ register8_t reserved_0x0F; ++ register8_t WAFNUM; /* Wafer Number */ ++ register8_t reserved_0x11; ++ register8_t COORDX0; /* Wafer Coordinate X Byte 0 */ ++ register8_t COORDX1; /* Wafer Coordinate X Byte 1 */ ++ register8_t COORDY0; /* Wafer Coordinate Y Byte 0 */ ++ register8_t COORDY1; /* Wafer Coordinate Y Byte 1 */ ++ register8_t reserved_0x16; ++ register8_t reserved_0x17; ++ register8_t reserved_0x18; ++ register8_t reserved_0x19; ++ register8_t reserved_0x1A; ++ register8_t reserved_0x1B; ++ register8_t reserved_0x1C; ++ register8_t reserved_0x1D; ++ register8_t ROOMTEMP; /* Temperature corresponds to TEMPSENSE3/2 */ ++ register8_t HOTTEMP; /* Temperature corresponds to TEMPSENSE1/0 */ ++ register8_t ADCACAL0; /* ADCA Calibration Byte 0 */ ++ register8_t ADCACAL1; /* ADCA Calibration Byte 1 */ ++ register8_t reserved_0x22; ++ register8_t reserved_0x23; ++ register8_t reserved_0x24; ++ register8_t reserved_0x25; ++ register8_t reserved_0x26; ++ register8_t reserved_0x27; ++ register8_t ACACURRCAL; /* ACA Current Calibration Byte */ ++ register8_t reserved_0x29; ++ register8_t reserved_0x2A; ++ register8_t reserved_0x2B; ++ register8_t TEMPSENSE2; /* Temperature Sensor Calibration Byte 2 */ ++ register8_t TEMPSENSE3; /* Temperature Sensor Calibration Byte 3 */ ++ register8_t TEMPSENSE0; /* Temperature Sensor Calibration Byte 0 */ ++ register8_t TEMPSENSE1; /* Temperature Sensor Calibration Byte 1 */ ++ register8_t DACA0OFFCAL; /* DACA0 Calibration Byte 0 */ ++ register8_t DACA0GAINCAL; /* DACA0 Calibration Byte 1 */ ++ register8_t reserved_0x32; ++ register8_t reserved_0x33; ++ register8_t DACA1OFFCAL; /* DACA1 Calibration Byte 0 */ ++ register8_t DACA1GAINCAL; /* DACA1 Calibration Byte 1 */ ++ register8_t reserved_0x36; ++ register8_t reserved_0x37; ++ register8_t reserved_0x38; ++ register8_t reserved_0x39; ++ register8_t reserved_0x3A; ++ register8_t reserved_0x3B; ++ register8_t reserved_0x3C; ++ register8_t reserved_0x3D; ++ register8_t reserved_0x3E; ++ register8_t reserved_0x3F; ++} NVM_PROD_SIGNATURES_t; ++ ++/* ++========================================================================== ++IO Module Instances. Mapped to memory. ++========================================================================== ++*/ ++ ++#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port */ ++#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port */ ++#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port */ ++#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port */ ++#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */ ++#define CLK (*(CLK_t *) 0x0040) /* Clock System */ ++#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */ ++#define OSC (*(OSC_t *) 0x0050) /* Oscillator */ ++#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL */ ++#define PR (*(PR_t *) 0x0070) /* Power Reduction */ ++#define RST (*(RST_t *) 0x0078) /* Reset */ ++#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */ ++#define MCU (*(MCU_t *) 0x0090) /* MCU Control */ ++#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Multi-level Interrupt Controller */ ++#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* I/O port Configuration */ ++#define CRC (*(CRC_t *) 0x00D0) /* Cyclic Redundancy Checker */ ++#define EDMA (*(EDMA_t *) 0x0100) /* Enhanced DMA Controller */ ++#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */ ++#define NVM (*(NVM_t *) 0x01C0) /* Non-volatile Memory Controller */ ++#define ADCA (*(ADC_t *) 0x0200) /* Analog-to-Digital Converter */ ++#define DACA (*(DAC_t *) 0x0300) /* Digital-to-Analog Converter */ ++#define ACA (*(AC_t *) 0x0380) /* Analog Comparator */ ++#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */ ++#define XCL (*(XCL_t *) 0x0460) /* XMEGA Custom Logic */ ++#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface */ ++#define PORTA (*(PORT_t *) 0x0600) /* I/O Ports */ ++#define PORTC (*(PORT_t *) 0x0640) /* I/O Ports */ ++#define PORTD (*(PORT_t *) 0x0660) /* I/O Ports */ ++#define PORTR (*(PORT_t *) 0x07E0) /* I/O Ports */ ++#define TCC4 (*(TC4_t *) 0x0800) /* 16-bit Timer/Counter 4 */ ++#define TCC5 (*(TC5_t *) 0x0840) /* 16-bit Timer/Counter 5 */ ++#define FAULTC4 (*(FAULT_t *) 0x0880) /* Fault Extension */ ++#define FAULTC5 (*(FAULT_t *) 0x0890) /* Fault Extension */ ++#define WEXC (*(WEX_t *) 0x08A0) /* Waveform Extension */ ++#define HIRESC (*(HIRES_t *) 0x08B0) /* High-Resolution Extension */ ++#define USARTC0 (*(USART_t *) 0x08C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define SPIC (*(SPI_t *) 0x08E0) /* Serial Peripheral Interface with Buffer Modes */ ++#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */ ++#define TCD5 (*(TC5_t *) 0x0940) /* 16-bit Timer/Counter 5 */ ++#define USARTD0 (*(USART_t *) 0x09C0) /* Universal Synchronous/Asynchronous Receiver/Transmitter */ ++ ++ ++#endif /* !defined (__ASSEMBLER__) */ ++ ++ ++/* ========== Flattened fully qualified IO register names ========== */ ++ ++/* GPIO - General Purpose IO Registers */ ++#define GPIO_GPIOR0 _SFR_MEM8(0x0000) ++#define GPIO_GPIOR1 _SFR_MEM8(0x0001) ++#define GPIO_GPIOR2 _SFR_MEM8(0x0002) ++#define GPIO_GPIOR3 _SFR_MEM8(0x0003) ++ ++/* Deprecated */ ++#define GPIO_GPIO0 _SFR_MEM8(0x0000) ++#define GPIO_GPIO1 _SFR_MEM8(0x0001) ++#define GPIO_GPIO2 _SFR_MEM8(0x0002) ++#define GPIO_GPIO3 _SFR_MEM8(0x0003) ++ ++/* NVM_FUSES - Fuses */ ++#define FUSE_FUSEBYTE1 _SFR_MEM8(0x0001) ++#define FUSE_FUSEBYTE2 _SFR_MEM8(0x0002) ++#define FUSE_FUSEBYTE4 _SFR_MEM8(0x0004) ++#define FUSE_FUSEBYTE5 _SFR_MEM8(0x0005) ++#define FUSE_FUSEBYTE6 _SFR_MEM8(0x0006) ++ ++/* NVM_LOCKBITS - Lock Bits */ ++#define LOCKBIT_LOCKBITS _SFR_MEM8(0x0000) ++ ++/* NVM_PROD_SIGNATURES - Production Signatures */ ++#define PRODSIGNATURES_RCOSC8M _SFR_MEM8(0x0000) ++#define PRODSIGNATURES_RCOSC32K _SFR_MEM8(0x0002) ++#define PRODSIGNATURES_RCOSC32M _SFR_MEM8(0x0003) ++#define PRODSIGNATURES_RCOSC32MA _SFR_MEM8(0x0004) ++#define PRODSIGNATURES_LOTNUM0 _SFR_MEM8(0x0008) ++#define PRODSIGNATURES_LOTNUM1 _SFR_MEM8(0x0009) ++#define PRODSIGNATURES_LOTNUM2 _SFR_MEM8(0x000A) ++#define PRODSIGNATURES_LOTNUM3 _SFR_MEM8(0x000B) ++#define PRODSIGNATURES_LOTNUM4 _SFR_MEM8(0x000C) ++#define PRODSIGNATURES_LOTNUM5 _SFR_MEM8(0x000D) ++#define PRODSIGNATURES_WAFNUM _SFR_MEM8(0x0010) ++#define PRODSIGNATURES_COORDX0 _SFR_MEM8(0x0012) ++#define PRODSIGNATURES_COORDX1 _SFR_MEM8(0x0013) ++#define PRODSIGNATURES_COORDY0 _SFR_MEM8(0x0014) ++#define PRODSIGNATURES_COORDY1 _SFR_MEM8(0x0015) ++#define PRODSIGNATURES_ROOMTEMP _SFR_MEM8(0x001E) ++#define PRODSIGNATURES_HOTTEMP _SFR_MEM8(0x001F) ++#define PRODSIGNATURES_ADCACAL0 _SFR_MEM8(0x0020) ++#define PRODSIGNATURES_ADCACAL1 _SFR_MEM8(0x0021) ++#define PRODSIGNATURES_ACACURRCAL _SFR_MEM8(0x0028) ++#define PRODSIGNATURES_TEMPSENSE2 _SFR_MEM8(0x002C) ++#define PRODSIGNATURES_TEMPSENSE3 _SFR_MEM8(0x002D) ++#define PRODSIGNATURES_TEMPSENSE0 _SFR_MEM8(0x002E) ++#define PRODSIGNATURES_TEMPSENSE1 _SFR_MEM8(0x002F) ++#define PRODSIGNATURES_DACA0OFFCAL _SFR_MEM8(0x0030) ++#define PRODSIGNATURES_DACA0GAINCAL _SFR_MEM8(0x0031) ++#define PRODSIGNATURES_DACA1OFFCAL _SFR_MEM8(0x0034) ++#define PRODSIGNATURES_DACA1GAINCAL _SFR_MEM8(0x0035) ++ ++/* VPORT - Virtual Port */ ++#define VPORT0_DIR _SFR_MEM8(0x0010) ++#define VPORT0_OUT _SFR_MEM8(0x0011) ++#define VPORT0_IN _SFR_MEM8(0x0012) ++#define VPORT0_INTFLAGS _SFR_MEM8(0x0013) ++ ++/* VPORT - Virtual Port */ ++#define VPORT1_DIR _SFR_MEM8(0x0014) ++#define VPORT1_OUT _SFR_MEM8(0x0015) ++#define VPORT1_IN _SFR_MEM8(0x0016) ++#define VPORT1_INTFLAGS _SFR_MEM8(0x0017) ++ ++/* VPORT - Virtual Port */ ++#define VPORT2_DIR _SFR_MEM8(0x0018) ++#define VPORT2_OUT _SFR_MEM8(0x0019) ++#define VPORT2_IN _SFR_MEM8(0x001A) ++#define VPORT2_INTFLAGS _SFR_MEM8(0x001B) ++ ++/* VPORT - Virtual Port */ ++#define VPORT3_DIR _SFR_MEM8(0x001C) ++#define VPORT3_OUT _SFR_MEM8(0x001D) ++#define VPORT3_IN _SFR_MEM8(0x001E) ++#define VPORT3_INTFLAGS _SFR_MEM8(0x001F) ++ ++/* OCD - On-Chip Debug System */ ++#define OCD_OCDR0 _SFR_MEM8(0x002E) ++#define OCD_OCDR1 _SFR_MEM8(0x002F) ++ ++/* CPU - CPU registers */ ++#define CPU_CCP _SFR_MEM8(0x0034) ++#define CPU_RAMPD _SFR_MEM8(0x0038) ++#define CPU_RAMPX _SFR_MEM8(0x0039) ++#define CPU_RAMPY _SFR_MEM8(0x003A) ++#define CPU_RAMPZ _SFR_MEM8(0x003B) ++#define CPU_EIND _SFR_MEM8(0x003C) ++#define CPU_SPL _SFR_MEM8(0x003D) ++#define CPU_SPH _SFR_MEM8(0x003E) ++#define CPU_SREG _SFR_MEM8(0x003F) ++ ++/* CLK - Clock System */ ++#define CLK_CTRL _SFR_MEM8(0x0040) ++#define CLK_PSCTRL _SFR_MEM8(0x0041) ++#define CLK_LOCK _SFR_MEM8(0x0042) ++#define CLK_RTCCTRL _SFR_MEM8(0x0043) ++ ++/* SLEEP - Sleep Controller */ ++#define SLEEP_CTRL _SFR_MEM8(0x0048) ++ ++/* OSC - Oscillator */ ++#define OSC_CTRL _SFR_MEM8(0x0050) ++#define OSC_STATUS _SFR_MEM8(0x0051) ++#define OSC_XOSCCTRL _SFR_MEM8(0x0052) ++#define OSC_XOSCFAIL _SFR_MEM8(0x0053) ++#define OSC_RC32KCAL _SFR_MEM8(0x0054) ++#define OSC_PLLCTRL _SFR_MEM8(0x0055) ++#define OSC_DFLLCTRL _SFR_MEM8(0x0056) ++#define OSC_RC8MCAL _SFR_MEM8(0x0057) ++ ++/* DFLL - DFLL */ ++#define DFLLRC32M_CTRL _SFR_MEM8(0x0060) ++#define DFLLRC32M_CALA _SFR_MEM8(0x0062) ++#define DFLLRC32M_CALB _SFR_MEM8(0x0063) ++#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064) ++#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065) ++#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066) ++ ++/* PR - Power Reduction */ ++#define PR_PRGEN _SFR_MEM8(0x0070) ++#define PR_PRPA _SFR_MEM8(0x0071) ++#define PR_PRPC _SFR_MEM8(0x0073) ++#define PR_PRPD _SFR_MEM8(0x0074) ++ ++/* RST - Reset */ ++#define RST_STATUS _SFR_MEM8(0x0078) ++#define RST_CTRL _SFR_MEM8(0x0079) ++ ++/* WDT - Watch-Dog Timer */ ++#define WDT_CTRL _SFR_MEM8(0x0080) ++#define WDT_WINCTRL _SFR_MEM8(0x0081) ++#define WDT_STATUS _SFR_MEM8(0x0082) ++ ++/* MCU - MCU Control */ ++#define MCU_DEVID0 _SFR_MEM8(0x0090) ++#define MCU_DEVID1 _SFR_MEM8(0x0091) ++#define MCU_DEVID2 _SFR_MEM8(0x0092) ++#define MCU_REVID _SFR_MEM8(0x0093) ++#define MCU_ANAINIT _SFR_MEM8(0x0097) ++#define MCU_EVSYSLOCK _SFR_MEM8(0x0098) ++#define MCU_WEXLOCK _SFR_MEM8(0x0099) ++#define MCU_FAULTLOCK _SFR_MEM8(0x009A) ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++#define PMIC_STATUS _SFR_MEM8(0x00A0) ++#define PMIC_INTPRI _SFR_MEM8(0x00A1) ++#define PMIC_CTRL _SFR_MEM8(0x00A2) ++ ++/* PORTCFG - I/O port Configuration */ ++#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0) ++#define PORTCFG_CLKOUT _SFR_MEM8(0x00B4) ++#define PORTCFG_ACEVOUT _SFR_MEM8(0x00B6) ++#define PORTCFG_SRLCTRL _SFR_MEM8(0x00B7) ++ ++/* CRC - Cyclic Redundancy Checker */ ++#define CRC_CTRL _SFR_MEM8(0x00D0) ++#define CRC_STATUS _SFR_MEM8(0x00D1) ++#define CRC_DATAIN _SFR_MEM8(0x00D3) ++#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4) ++#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5) ++#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6) ++#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7) ++ ++/* EDMA - Enhanced DMA Controller */ ++#define EDMA_CTRL _SFR_MEM8(0x0100) ++#define EDMA_INTFLAGS _SFR_MEM8(0x0103) ++#define EDMA_STATUS _SFR_MEM8(0x0104) ++#define EDMA_TEMP _SFR_MEM8(0x0106) ++#define EDMA_CH0_CTRLA _SFR_MEM8(0x0110) ++#define EDMA_CH0_CTRLB _SFR_MEM8(0x0111) ++#define EDMA_CH0_ADDRCTRL _SFR_MEM8(0x0112) ++#define EDMA_CH0_DESTADDRCTRL _SFR_MEM8(0x0113) ++#define EDMA_CH0_TRIGSRC _SFR_MEM8(0x0114) ++#define EDMA_CH0_TRFCNT _SFR_MEM16(0x0116) ++#define EDMA_CH0_ADDR _SFR_MEM16(0x0118) ++#define EDMA_CH0_DESTADDR _SFR_MEM16(0x011C) ++#define EDMA_CH1_CTRLA _SFR_MEM8(0x0120) ++#define EDMA_CH1_CTRLB _SFR_MEM8(0x0121) ++#define EDMA_CH1_ADDRCTRL _SFR_MEM8(0x0122) ++#define EDMA_CH1_DESTADDRCTRL _SFR_MEM8(0x0123) ++#define EDMA_CH1_TRIGSRC _SFR_MEM8(0x0124) ++#define EDMA_CH1_TRFCNT _SFR_MEM16(0x0126) ++#define EDMA_CH1_ADDR _SFR_MEM16(0x0128) ++#define EDMA_CH1_DESTADDR _SFR_MEM16(0x012C) ++#define EDMA_CH2_CTRLA _SFR_MEM8(0x0130) ++#define EDMA_CH2_CTRLB _SFR_MEM8(0x0131) ++#define EDMA_CH2_ADDRCTRL _SFR_MEM8(0x0132) ++#define EDMA_CH2_DESTADDRCTRL _SFR_MEM8(0x0133) ++#define EDMA_CH2_TRIGSRC _SFR_MEM8(0x0134) ++#define EDMA_CH2_TRFCNT _SFR_MEM16(0x0136) ++#define EDMA_CH2_ADDR _SFR_MEM16(0x0138) ++#define EDMA_CH2_DESTADDR _SFR_MEM16(0x013C) ++#define EDMA_CH3_CTRLA _SFR_MEM8(0x0140) ++#define EDMA_CH3_CTRLB _SFR_MEM8(0x0141) ++#define EDMA_CH3_ADDRCTRL _SFR_MEM8(0x0142) ++#define EDMA_CH3_DESTADDRCTRL _SFR_MEM8(0x0143) ++#define EDMA_CH3_TRIGSRC _SFR_MEM8(0x0144) ++#define EDMA_CH3_TRFCNT _SFR_MEM16(0x0146) ++#define EDMA_CH3_ADDR _SFR_MEM16(0x0148) ++#define EDMA_CH3_DESTADDR _SFR_MEM16(0x014C) ++ ++/* EVSYS - Event System */ ++#define EVSYS_CH0MUX _SFR_MEM8(0x0180) ++#define EVSYS_CH1MUX _SFR_MEM8(0x0181) ++#define EVSYS_CH2MUX _SFR_MEM8(0x0182) ++#define EVSYS_CH3MUX _SFR_MEM8(0x0183) ++#define EVSYS_CH4MUX _SFR_MEM8(0x0184) ++#define EVSYS_CH5MUX _SFR_MEM8(0x0185) ++#define EVSYS_CH6MUX _SFR_MEM8(0x0186) ++#define EVSYS_CH7MUX _SFR_MEM8(0x0187) ++#define EVSYS_CH0CTRL _SFR_MEM8(0x0188) ++#define EVSYS_CH1CTRL _SFR_MEM8(0x0189) ++#define EVSYS_CH2CTRL _SFR_MEM8(0x018A) ++#define EVSYS_CH3CTRL _SFR_MEM8(0x018B) ++#define EVSYS_CH4CTRL _SFR_MEM8(0x018C) ++#define EVSYS_CH5CTRL _SFR_MEM8(0x018D) ++#define EVSYS_CH6CTRL _SFR_MEM8(0x018E) ++#define EVSYS_CH7CTRL _SFR_MEM8(0x018F) ++#define EVSYS_STROBE _SFR_MEM8(0x0190) ++#define EVSYS_DATA _SFR_MEM8(0x0191) ++#define EVSYS_DFCTRL _SFR_MEM8(0x0192) ++ ++/* NVM - Non-volatile Memory Controller */ ++#define NVM_ADDR0 _SFR_MEM8(0x01C0) ++#define NVM_ADDR1 _SFR_MEM8(0x01C1) ++#define NVM_ADDR2 _SFR_MEM8(0x01C2) ++#define NVM_DATA0 _SFR_MEM8(0x01C4) ++#define NVM_DATA1 _SFR_MEM8(0x01C5) ++#define NVM_DATA2 _SFR_MEM8(0x01C6) ++#define NVM_CMD _SFR_MEM8(0x01CA) ++#define NVM_CTRLA _SFR_MEM8(0x01CB) ++#define NVM_CTRLB _SFR_MEM8(0x01CC) ++#define NVM_INTCTRL _SFR_MEM8(0x01CD) ++#define NVM_STATUS _SFR_MEM8(0x01CF) ++#define NVM_LOCKBITS _SFR_MEM8(0x01D0) ++ ++/* ADC - Analog-to-Digital Converter */ ++#define ADCA_CTRLA _SFR_MEM8(0x0200) ++#define ADCA_CTRLB _SFR_MEM8(0x0201) ++#define ADCA_REFCTRL _SFR_MEM8(0x0202) ++#define ADCA_EVCTRL _SFR_MEM8(0x0203) ++#define ADCA_PRESCALER _SFR_MEM8(0x0204) ++#define ADCA_INTFLAGS _SFR_MEM8(0x0206) ++#define ADCA_TEMP _SFR_MEM8(0x0207) ++#define ADCA_SAMPCTRL _SFR_MEM8(0x0208) ++#define ADCA_CAL _SFR_MEM16(0x020C) ++#define ADCA_CH0RES _SFR_MEM16(0x0210) ++#define ADCA_CMP _SFR_MEM16(0x0218) ++#define ADCA_CH0_CTRL _SFR_MEM8(0x0220) ++#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221) ++#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222) ++#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223) ++#define ADCA_CH0_RES _SFR_MEM16(0x0224) ++#define ADCA_CH0_SCAN _SFR_MEM8(0x0226) ++#define ADCA_CH0_CORRCTRL _SFR_MEM8(0x0227) ++#define ADCA_CH0_OFFSETCORR0 _SFR_MEM8(0x0228) ++#define ADCA_CH0_OFFSETCORR1 _SFR_MEM8(0x0229) ++#define ADCA_CH0_GAINCORR0 _SFR_MEM8(0x022A) ++#define ADCA_CH0_GAINCORR1 _SFR_MEM8(0x022B) ++#define ADCA_CH0_AVGCTRL _SFR_MEM8(0x022C) ++ ++/* DAC - Digital-to-Analog Converter */ ++#define DACA_CTRLA _SFR_MEM8(0x0300) ++#define DACA_CTRLB _SFR_MEM8(0x0301) ++#define DACA_CTRLC _SFR_MEM8(0x0302) ++#define DACA_EVCTRL _SFR_MEM8(0x0303) ++#define DACA_STATUS _SFR_MEM8(0x0305) ++#define DACA_CH0GAINCAL _SFR_MEM8(0x0308) ++#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309) ++#define DACA_CH1GAINCAL _SFR_MEM8(0x030A) ++#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B) ++#define DACA_CH0DATA _SFR_MEM16(0x0318) ++#define DACA_CH1DATA _SFR_MEM16(0x031A) ++ ++/* AC - Analog Comparator */ ++#define ACA_AC0CTRL _SFR_MEM8(0x0380) ++#define ACA_AC1CTRL _SFR_MEM8(0x0381) ++#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382) ++#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383) ++#define ACA_CTRLA _SFR_MEM8(0x0384) ++#define ACA_CTRLB _SFR_MEM8(0x0385) ++#define ACA_WINCTRL _SFR_MEM8(0x0386) ++#define ACA_STATUS _SFR_MEM8(0x0387) ++#define ACA_CURRCTRL _SFR_MEM8(0x0388) ++#define ACA_CURRCALIB _SFR_MEM8(0x0389) ++ ++/* RTC - Real-Time Counter */ ++#define RTC_CTRL _SFR_MEM8(0x0400) ++#define RTC_STATUS _SFR_MEM8(0x0401) ++#define RTC_INTCTRL _SFR_MEM8(0x0402) ++#define RTC_INTFLAGS _SFR_MEM8(0x0403) ++#define RTC_TEMP _SFR_MEM8(0x0404) ++#define RTC_CALIB _SFR_MEM8(0x0406) ++#define RTC_CNT _SFR_MEM16(0x0408) ++#define RTC_PER _SFR_MEM16(0x040A) ++#define RTC_COMP _SFR_MEM16(0x040C) ++ ++/* XCL - XMEGA Custom Logic */ ++#define XCL_CTRLA _SFR_MEM8(0x0460) ++#define XCL_CTRLB _SFR_MEM8(0x0461) ++#define XCL_CTRLC _SFR_MEM8(0x0462) ++#define XCL_CTRLD _SFR_MEM8(0x0463) ++#define XCL_CTRLE _SFR_MEM8(0x0464) ++#define XCL_CTRLF _SFR_MEM8(0x0465) ++#define XCL_CTRLG _SFR_MEM8(0x0466) ++#define XCL_INTCTRL _SFR_MEM8(0x0467) ++#define XCL_INTFLAGS _SFR_MEM8(0x0468) ++#define XCL_PLC _SFR_MEM8(0x0469) ++#define XCL_CNTL _SFR_MEM8(0x046A) ++#define XCL_CNTH _SFR_MEM8(0x046B) ++#define XCL_CMPL _SFR_MEM8(0x046C) ++#define XCL_CMPH _SFR_MEM8(0x046D) ++#define XCL_PERCAPTL _SFR_MEM8(0x046E) ++#define XCL_PERCAPTH _SFR_MEM8(0x046F) ++ ++/* TWI - Two-Wire Interface */ ++#define TWIC_CTRL _SFR_MEM8(0x0480) ++#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481) ++#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482) ++#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483) ++#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484) ++#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485) ++#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486) ++#define TWIC_MASTER_DATA _SFR_MEM8(0x0487) ++#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488) ++#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489) ++#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A) ++#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B) ++#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C) ++#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D) ++#define TWIC_TIMEOUT_TOS _SFR_MEM8(0x048E) ++#define TWIC_TIMEOUT_TOCONF _SFR_MEM8(0x048F) ++ ++/* PORT - I/O Ports */ ++#define PORTA_DIR _SFR_MEM8(0x0600) ++#define PORTA_DIRSET _SFR_MEM8(0x0601) ++#define PORTA_DIRCLR _SFR_MEM8(0x0602) ++#define PORTA_DIRTGL _SFR_MEM8(0x0603) ++#define PORTA_OUT _SFR_MEM8(0x0604) ++#define PORTA_OUTSET _SFR_MEM8(0x0605) ++#define PORTA_OUTCLR _SFR_MEM8(0x0606) ++#define PORTA_OUTTGL _SFR_MEM8(0x0607) ++#define PORTA_IN _SFR_MEM8(0x0608) ++#define PORTA_INTCTRL _SFR_MEM8(0x0609) ++#define PORTA_INTMASK _SFR_MEM8(0x060A) ++#define PORTA_INTFLAGS _SFR_MEM8(0x060C) ++#define PORTA_REMAP _SFR_MEM8(0x060E) ++#define PORTA_PIN0CTRL _SFR_MEM8(0x0610) ++#define PORTA_PIN1CTRL _SFR_MEM8(0x0611) ++#define PORTA_PIN2CTRL _SFR_MEM8(0x0612) ++#define PORTA_PIN3CTRL _SFR_MEM8(0x0613) ++#define PORTA_PIN4CTRL _SFR_MEM8(0x0614) ++#define PORTA_PIN5CTRL _SFR_MEM8(0x0615) ++#define PORTA_PIN6CTRL _SFR_MEM8(0x0616) ++#define PORTA_PIN7CTRL _SFR_MEM8(0x0617) ++ ++/* PORT - I/O Ports */ ++#define PORTC_DIR _SFR_MEM8(0x0640) ++#define PORTC_DIRSET _SFR_MEM8(0x0641) ++#define PORTC_DIRCLR _SFR_MEM8(0x0642) ++#define PORTC_DIRTGL _SFR_MEM8(0x0643) ++#define PORTC_OUT _SFR_MEM8(0x0644) ++#define PORTC_OUTSET _SFR_MEM8(0x0645) ++#define PORTC_OUTCLR _SFR_MEM8(0x0646) ++#define PORTC_OUTTGL _SFR_MEM8(0x0647) ++#define PORTC_IN _SFR_MEM8(0x0648) ++#define PORTC_INTCTRL _SFR_MEM8(0x0649) ++#define PORTC_INTMASK _SFR_MEM8(0x064A) ++#define PORTC_INTFLAGS _SFR_MEM8(0x064C) ++#define PORTC_REMAP _SFR_MEM8(0x064E) ++#define PORTC_PIN0CTRL _SFR_MEM8(0x0650) ++#define PORTC_PIN1CTRL _SFR_MEM8(0x0651) ++#define PORTC_PIN2CTRL _SFR_MEM8(0x0652) ++#define PORTC_PIN3CTRL _SFR_MEM8(0x0653) ++#define PORTC_PIN4CTRL _SFR_MEM8(0x0654) ++#define PORTC_PIN5CTRL _SFR_MEM8(0x0655) ++#define PORTC_PIN6CTRL _SFR_MEM8(0x0656) ++#define PORTC_PIN7CTRL _SFR_MEM8(0x0657) ++ ++/* PORT - I/O Ports */ ++#define PORTD_DIR _SFR_MEM8(0x0660) ++#define PORTD_DIRSET _SFR_MEM8(0x0661) ++#define PORTD_DIRCLR _SFR_MEM8(0x0662) ++#define PORTD_DIRTGL _SFR_MEM8(0x0663) ++#define PORTD_OUT _SFR_MEM8(0x0664) ++#define PORTD_OUTSET _SFR_MEM8(0x0665) ++#define PORTD_OUTCLR _SFR_MEM8(0x0666) ++#define PORTD_OUTTGL _SFR_MEM8(0x0667) ++#define PORTD_IN _SFR_MEM8(0x0668) ++#define PORTD_INTCTRL _SFR_MEM8(0x0669) ++#define PORTD_INTMASK _SFR_MEM8(0x066A) ++#define PORTD_INTFLAGS _SFR_MEM8(0x066C) ++#define PORTD_REMAP _SFR_MEM8(0x066E) ++#define PORTD_PIN0CTRL _SFR_MEM8(0x0670) ++#define PORTD_PIN1CTRL _SFR_MEM8(0x0671) ++#define PORTD_PIN2CTRL _SFR_MEM8(0x0672) ++#define PORTD_PIN3CTRL _SFR_MEM8(0x0673) ++#define PORTD_PIN4CTRL _SFR_MEM8(0x0674) ++#define PORTD_PIN5CTRL _SFR_MEM8(0x0675) ++#define PORTD_PIN6CTRL _SFR_MEM8(0x0676) ++#define PORTD_PIN7CTRL _SFR_MEM8(0x0677) ++ ++/* PORT - I/O Ports */ ++#define PORTR_DIR _SFR_MEM8(0x07E0) ++#define PORTR_DIRSET _SFR_MEM8(0x07E1) ++#define PORTR_DIRCLR _SFR_MEM8(0x07E2) ++#define PORTR_DIRTGL _SFR_MEM8(0x07E3) ++#define PORTR_OUT _SFR_MEM8(0x07E4) ++#define PORTR_OUTSET _SFR_MEM8(0x07E5) ++#define PORTR_OUTCLR _SFR_MEM8(0x07E6) ++#define PORTR_OUTTGL _SFR_MEM8(0x07E7) ++#define PORTR_IN _SFR_MEM8(0x07E8) ++#define PORTR_INTCTRL _SFR_MEM8(0x07E9) ++#define PORTR_INTMASK _SFR_MEM8(0x07EA) ++#define PORTR_INTFLAGS _SFR_MEM8(0x07EC) ++#define PORTR_REMAP _SFR_MEM8(0x07EE) ++#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0) ++#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1) ++#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2) ++#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3) ++#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4) ++#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5) ++#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6) ++#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7) ++ ++/* TC4 - 16-bit Timer/Counter 4 */ ++#define TCC4_CTRLA _SFR_MEM8(0x0800) ++#define TCC4_CTRLB _SFR_MEM8(0x0801) ++#define TCC4_CTRLC _SFR_MEM8(0x0802) ++#define TCC4_CTRLD _SFR_MEM8(0x0803) ++#define TCC4_CTRLE _SFR_MEM8(0x0804) ++#define TCC4_CTRLF _SFR_MEM8(0x0805) ++#define TCC4_INTCTRLA _SFR_MEM8(0x0806) ++#define TCC4_INTCTRLB _SFR_MEM8(0x0807) ++#define TCC4_CTRLGCLR _SFR_MEM8(0x0808) ++#define TCC4_CTRLGSET _SFR_MEM8(0x0809) ++#define TCC4_CTRLHCLR _SFR_MEM8(0x080A) ++#define TCC4_CTRLHSET _SFR_MEM8(0x080B) ++#define TCC4_INTFLAGS _SFR_MEM8(0x080C) ++#define TCC4_TEMP _SFR_MEM8(0x080F) ++#define TCC4_CNT _SFR_MEM16(0x0820) ++#define TCC4_PER _SFR_MEM16(0x0826) ++#define TCC4_CCA _SFR_MEM16(0x0828) ++#define TCC4_CCB _SFR_MEM16(0x082A) ++#define TCC4_CCC _SFR_MEM16(0x082C) ++#define TCC4_CCD _SFR_MEM16(0x082E) ++#define TCC4_PERBUF _SFR_MEM16(0x0836) ++#define TCC4_CCABUF _SFR_MEM16(0x0838) ++#define TCC4_CCBBUF _SFR_MEM16(0x083A) ++#define TCC4_CCCBUF _SFR_MEM16(0x083C) ++#define TCC4_CCDBUF _SFR_MEM16(0x083E) ++ ++/* TC5 - 16-bit Timer/Counter 5 */ ++#define TCC5_CTRLA _SFR_MEM8(0x0840) ++#define TCC5_CTRLB _SFR_MEM8(0x0841) ++#define TCC5_CTRLC _SFR_MEM8(0x0842) ++#define TCC5_CTRLD _SFR_MEM8(0x0843) ++#define TCC5_CTRLE _SFR_MEM8(0x0844) ++#define TCC5_CTRLF _SFR_MEM8(0x0845) ++#define TCC5_INTCTRLA _SFR_MEM8(0x0846) ++#define TCC5_INTCTRLB _SFR_MEM8(0x0847) ++#define TCC5_CTRLGCLR _SFR_MEM8(0x0848) ++#define TCC5_CTRLGSET _SFR_MEM8(0x0849) ++#define TCC5_CTRLHCLR _SFR_MEM8(0x084A) ++#define TCC5_CTRLHSET _SFR_MEM8(0x084B) ++#define TCC5_INTFLAGS _SFR_MEM8(0x084C) ++#define TCC5_TEMP _SFR_MEM8(0x084F) ++#define TCC5_CNT _SFR_MEM16(0x0860) ++#define TCC5_PER _SFR_MEM16(0x0866) ++#define TCC5_CCA _SFR_MEM16(0x0868) ++#define TCC5_CCB _SFR_MEM16(0x086A) ++#define TCC5_PERBUF _SFR_MEM16(0x0876) ++#define TCC5_CCABUF _SFR_MEM16(0x0878) ++#define TCC5_CCBBUF _SFR_MEM16(0x087A) ++ ++/* FAULT - Fault Extension */ ++#define FAULTC4_CTRLA _SFR_MEM8(0x0880) ++#define FAULTC4_CTRLB _SFR_MEM8(0x0881) ++#define FAULTC4_CTRLC _SFR_MEM8(0x0882) ++#define FAULTC4_CTRLD _SFR_MEM8(0x0883) ++#define FAULTC4_CTRLE _SFR_MEM8(0x0884) ++#define FAULTC4_STATUS _SFR_MEM8(0x0885) ++#define FAULTC4_CTRLGCLR _SFR_MEM8(0x0886) ++#define FAULTC4_CTRLGSET _SFR_MEM8(0x0887) ++ ++/* FAULT - Fault Extension */ ++#define FAULTC5_CTRLA _SFR_MEM8(0x0890) ++#define FAULTC5_CTRLB _SFR_MEM8(0x0891) ++#define FAULTC5_CTRLC _SFR_MEM8(0x0892) ++#define FAULTC5_CTRLD _SFR_MEM8(0x0893) ++#define FAULTC5_CTRLE _SFR_MEM8(0x0894) ++#define FAULTC5_STATUS _SFR_MEM8(0x0895) ++#define FAULTC5_CTRLGCLR _SFR_MEM8(0x0896) ++#define FAULTC5_CTRLGSET _SFR_MEM8(0x0897) ++ ++/* WEX - Waveform Extension */ ++#define WEXC_CTRL _SFR_MEM8(0x08A0) ++#define WEXC_DTBOTH _SFR_MEM8(0x08A1) ++#define WEXC_DTLS _SFR_MEM8(0x08A2) ++#define WEXC_DTHS _SFR_MEM8(0x08A3) ++#define WEXC_STATUSCLR _SFR_MEM8(0x08A4) ++#define WEXC_STATUSSET _SFR_MEM8(0x08A5) ++#define WEXC_SWAP _SFR_MEM8(0x08A6) ++#define WEXC_PGO _SFR_MEM8(0x08A7) ++#define WEXC_PGV _SFR_MEM8(0x08A8) ++#define WEXC_SWAPBUF _SFR_MEM8(0x08AA) ++#define WEXC_PGOBUF _SFR_MEM8(0x08AB) ++#define WEXC_PGVBUF _SFR_MEM8(0x08AC) ++#define WEXC_OUTOVDIS _SFR_MEM8(0x08AF) ++ ++/* HIRES - High-Resolution Extension */ ++#define HIRESC_CTRLA _SFR_MEM8(0x08B0) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTC0_DATA _SFR_MEM8(0x08C0) ++#define USARTC0_STATUS _SFR_MEM8(0x08C1) ++#define USARTC0_CTRLA _SFR_MEM8(0x08C2) ++#define USARTC0_CTRLB _SFR_MEM8(0x08C3) ++#define USARTC0_CTRLC _SFR_MEM8(0x08C4) ++#define USARTC0_CTRLD _SFR_MEM8(0x08C5) ++#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08C6) ++#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08C7) ++ ++/* SPI - Serial Peripheral Interface with Buffer Modes */ ++#define SPIC_CTRL _SFR_MEM8(0x08E0) ++#define SPIC_INTCTRL _SFR_MEM8(0x08E1) ++#define SPIC_STATUS _SFR_MEM8(0x08E2) ++#define SPIC_DATA _SFR_MEM8(0x08E3) ++#define SPIC_CTRLB _SFR_MEM8(0x08E4) ++ ++/* IRCOM - IR Communication Module */ ++#define IRCOM_CTRL _SFR_MEM8(0x08F8) ++#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9) ++#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA) ++ ++/* TC5 - 16-bit Timer/Counter 5 */ ++#define TCD5_CTRLA _SFR_MEM8(0x0940) ++#define TCD5_CTRLB _SFR_MEM8(0x0941) ++#define TCD5_CTRLC _SFR_MEM8(0x0942) ++#define TCD5_CTRLD _SFR_MEM8(0x0943) ++#define TCD5_CTRLE _SFR_MEM8(0x0944) ++#define TCD5_CTRLF _SFR_MEM8(0x0945) ++#define TCD5_INTCTRLA _SFR_MEM8(0x0946) ++#define TCD5_INTCTRLB _SFR_MEM8(0x0947) ++#define TCD5_CTRLGCLR _SFR_MEM8(0x0948) ++#define TCD5_CTRLGSET _SFR_MEM8(0x0949) ++#define TCD5_CTRLHCLR _SFR_MEM8(0x094A) ++#define TCD5_CTRLHSET _SFR_MEM8(0x094B) ++#define TCD5_INTFLAGS _SFR_MEM8(0x094C) ++#define TCD5_TEMP _SFR_MEM8(0x094F) ++#define TCD5_CNT _SFR_MEM16(0x0960) ++#define TCD5_PER _SFR_MEM16(0x0966) ++#define TCD5_CCA _SFR_MEM16(0x0968) ++#define TCD5_CCB _SFR_MEM16(0x096A) ++#define TCD5_PERBUF _SFR_MEM16(0x0976) ++#define TCD5_CCABUF _SFR_MEM16(0x0978) ++#define TCD5_CCBBUF _SFR_MEM16(0x097A) ++ ++/* USART - Universal Synchronous/Asynchronous Receiver/Transmitter */ ++#define USARTD0_DATA _SFR_MEM8(0x09C0) ++#define USARTD0_STATUS _SFR_MEM8(0x09C1) ++#define USARTD0_CTRLA _SFR_MEM8(0x09C2) ++#define USARTD0_CTRLB _SFR_MEM8(0x09C3) ++#define USARTD0_CTRLC _SFR_MEM8(0x09C4) ++#define USARTD0_CTRLD _SFR_MEM8(0x09C5) ++#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09C6) ++#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09C7) ++ ++ ++ ++/*================== Bitfield Definitions ================== */ ++ ++/* VPORT - Virtual Ports */ ++/* VPORT.INTFLAGS bit masks and bit positions */ ++#define VPORT_INT7IF_bm 0x80 /* Interrupt Pin 7 Flag bit mask. */ ++#define VPORT_INT7IF_bp 7 /* Interrupt Pin 7 Flag bit position. */ ++ ++#define VPORT_INT6IF_bm 0x40 /* Interrupt Pin 6 Flag bit mask. */ ++#define VPORT_INT6IF_bp 6 /* Interrupt Pin 6 Flag bit position. */ ++ ++#define VPORT_INT5IF_bm 0x20 /* Interrupt Pin 5 Flag bit mask. */ ++#define VPORT_INT5IF_bp 5 /* Interrupt Pin 5 Flag bit position. */ ++ ++#define VPORT_INT4IF_bm 0x10 /* Interrupt Pin 4 Flag bit mask. */ ++#define VPORT_INT4IF_bp 4 /* Interrupt Pin 4 Flag bit position. */ ++ ++#define VPORT_INT3IF_bm 0x08 /* Interrupt Pin 3 Flag bit mask. */ ++#define VPORT_INT3IF_bp 3 /* Interrupt Pin 3 Flag bit position. */ ++ ++#define VPORT_INT2IF_bm 0x04 /* Interrupt Pin 2 Flag bit mask. */ ++#define VPORT_INT2IF_bp 2 /* Interrupt Pin 2 Flag bit position. */ ++ ++#define VPORT_INT1IF_bm 0x02 /* Interrupt Pin 1 Flag bit mask. */ ++#define VPORT_INT1IF_bp 1 /* Interrupt Pin 1 Flag bit position. */ ++ ++#define VPORT_INT0IF_bm 0x01 /* Interrupt Pin 0 Flag bit mask. */ ++#define VPORT_INT0IF_bp 0 /* Interrupt Pin 0 Flag bit position. */ ++ ++/* XOCD - On-Chip Debug System */ ++/* OCD.OCDR0 bit masks and bit positions */ ++#define OCD_OCDRD_gm 0xFF /* OCDR Dirty group mask. */ ++#define OCD_OCDRD_gp 0 /* OCDR Dirty group position. */ ++#define OCD_OCDRD0_bm (1<<0) /* OCDR Dirty bit 0 mask. */ ++#define OCD_OCDRD0_bp 0 /* OCDR Dirty bit 0 position. */ ++#define OCD_OCDRD1_bm (1<<1) /* OCDR Dirty bit 1 mask. */ ++#define OCD_OCDRD1_bp 1 /* OCDR Dirty bit 1 position. */ ++#define OCD_OCDRD2_bm (1<<2) /* OCDR Dirty bit 2 mask. */ ++#define OCD_OCDRD2_bp 2 /* OCDR Dirty bit 2 position. */ ++#define OCD_OCDRD3_bm (1<<3) /* OCDR Dirty bit 3 mask. */ ++#define OCD_OCDRD3_bp 3 /* OCDR Dirty bit 3 position. */ ++#define OCD_OCDRD4_bm (1<<4) /* OCDR Dirty bit 4 mask. */ ++#define OCD_OCDRD4_bp 4 /* OCDR Dirty bit 4 position. */ ++#define OCD_OCDRD5_bm (1<<5) /* OCDR Dirty bit 5 mask. */ ++#define OCD_OCDRD5_bp 5 /* OCDR Dirty bit 5 position. */ ++#define OCD_OCDRD6_bm (1<<6) /* OCDR Dirty bit 6 mask. */ ++#define OCD_OCDRD6_bp 6 /* OCDR Dirty bit 6 position. */ ++#define OCD_OCDRD7_bm (1<<7) /* OCDR Dirty bit 7 mask. */ ++#define OCD_OCDRD7_bp 7 /* OCDR Dirty bit 7 position. */ ++ ++/* OCD.OCDR1 bit masks and bit positions */ ++/* OCD_OCDRD Predefined. */ ++/* OCD_OCDRD Predefined. */ ++ ++/* CPU - CPU */ ++/* CPU.CCP bit masks and bit positions */ ++#define CPU_CCP_gm 0xFF /* CCP signature group mask. */ ++#define CPU_CCP_gp 0 /* CCP signature group position. */ ++#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */ ++#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */ ++#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */ ++#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */ ++#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */ ++#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */ ++#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */ ++#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */ ++#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */ ++#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */ ++#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */ ++#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */ ++#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */ ++#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */ ++#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */ ++#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */ ++ ++/* CPU.SREG bit masks and bit positions */ ++#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */ ++#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */ ++ ++#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */ ++#define CPU_T_bp 6 /* Transfer Bit bit position. */ ++ ++#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */ ++#define CPU_H_bp 5 /* Half Carry Flag bit position. */ ++ ++#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */ ++#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */ ++ ++#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */ ++#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */ ++ ++#define CPU_N_bm 0x04 /* Negative Flag bit mask. */ ++#define CPU_N_bp 2 /* Negative Flag bit position. */ ++ ++#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */ ++#define CPU_Z_bp 1 /* Zero Flag bit position. */ ++ ++#define CPU_C_bm 0x01 /* Carry Flag bit mask. */ ++#define CPU_C_bp 0 /* Carry Flag bit position. */ ++ ++/* CLK - Clock System */ ++/* CLK.CTRL bit masks and bit positions */ ++#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */ ++#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */ ++#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */ ++#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */ ++#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */ ++#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */ ++#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */ ++#define CLK_SCLKSEL2_bp 2 /* System Clock Selection bit 2 position. */ ++ ++/* CLK.PSCTRL bit masks and bit positions */ ++#define CLK_PSADIV_gm 0x7C /* Prescaler A Division Factor group mask. */ ++#define CLK_PSADIV_gp 2 /* Prescaler A Division Factor group position. */ ++#define CLK_PSADIV0_bm (1<<2) /* Prescaler A Division Factor bit 0 mask. */ ++#define CLK_PSADIV0_bp 2 /* Prescaler A Division Factor bit 0 position. */ ++#define CLK_PSADIV1_bm (1<<3) /* Prescaler A Division Factor bit 1 mask. */ ++#define CLK_PSADIV1_bp 3 /* Prescaler A Division Factor bit 1 position. */ ++#define CLK_PSADIV2_bm (1<<4) /* Prescaler A Division Factor bit 2 mask. */ ++#define CLK_PSADIV2_bp 4 /* Prescaler A Division Factor bit 2 position. */ ++#define CLK_PSADIV3_bm (1<<5) /* Prescaler A Division Factor bit 3 mask. */ ++#define CLK_PSADIV3_bp 5 /* Prescaler A Division Factor bit 3 position. */ ++#define CLK_PSADIV4_bm (1<<6) /* Prescaler A Division Factor bit 4 mask. */ ++#define CLK_PSADIV4_bp 6 /* Prescaler A Division Factor bit 4 position. */ ++ ++#define CLK_PSBCDIV_gm 0x03 /* Prescaler B and C Division factor group mask. */ ++#define CLK_PSBCDIV_gp 0 /* Prescaler B and C Division factor group position. */ ++#define CLK_PSBCDIV0_bm (1<<0) /* Prescaler B and C Division factor bit 0 mask. */ ++#define CLK_PSBCDIV0_bp 0 /* Prescaler B and C Division factor bit 0 position. */ ++#define CLK_PSBCDIV1_bm (1<<1) /* Prescaler B and C Division factor bit 1 mask. */ ++#define CLK_PSBCDIV1_bp 1 /* Prescaler B and C Division factor bit 1 position. */ ++ ++/* CLK.LOCK bit masks and bit positions */ ++#define CLK_LOCK_bm 0x01 /* Clock System Lock bit mask. */ ++#define CLK_LOCK_bp 0 /* Clock System Lock bit position. */ ++ ++/* CLK.RTCCTRL bit masks and bit positions */ ++#define CLK_RTCSRC_gm 0x0E /* Clock Source group mask. */ ++#define CLK_RTCSRC_gp 1 /* Clock Source group position. */ ++#define CLK_RTCSRC0_bm (1<<1) /* Clock Source bit 0 mask. */ ++#define CLK_RTCSRC0_bp 1 /* Clock Source bit 0 position. */ ++#define CLK_RTCSRC1_bm (1<<2) /* Clock Source bit 1 mask. */ ++#define CLK_RTCSRC1_bp 2 /* Clock Source bit 1 position. */ ++#define CLK_RTCSRC2_bm (1<<3) /* Clock Source bit 2 mask. */ ++#define CLK_RTCSRC2_bp 3 /* Clock Source bit 2 position. */ ++ ++#define CLK_RTCEN_bm 0x01 /* Clock Source Enable bit mask. */ ++#define CLK_RTCEN_bp 0 /* Clock Source Enable bit position. */ ++ ++/* PR.PRGEN bit masks and bit positions */ ++#define PR_XCL_bm 0x80 /* XMEGA Custom Logic bit mask. */ ++#define PR_XCL_bp 7 /* XMEGA Custom Logic bit position. */ ++ ++#define PR_RTC_bm 0x04 /* Real-time Counter bit mask. */ ++#define PR_RTC_bp 2 /* Real-time Counter bit position. */ ++ ++#define PR_EVSYS_bm 0x02 /* Event System bit mask. */ ++#define PR_EVSYS_bp 1 /* Event System bit position. */ ++ ++#define PR_EDMA_bm 0x01 /* Enhanced DMA-Controller bit mask. */ ++#define PR_EDMA_bp 0 /* Enhanced DMA-Controller bit position. */ ++ ++/* PR.PRPA bit masks and bit positions */ ++#define PR_DAC_bm 0x04 /* Port A DAC bit mask. */ ++#define PR_DAC_bp 2 /* Port A DAC bit position. */ ++ ++#define PR_ADC_bm 0x02 /* Port A ADC bit mask. */ ++#define PR_ADC_bp 1 /* Port A ADC bit position. */ ++ ++#define PR_AC_bm 0x01 /* Port A Analog Comparator bit mask. */ ++#define PR_AC_bp 0 /* Port A Analog Comparator bit position. */ ++ ++/* PR.PRPC bit masks and bit positions */ ++#define PR_TWI_bm 0x40 /* Port C Two-wire Interface bit mask. */ ++#define PR_TWI_bp 6 /* Port C Two-wire Interface bit position. */ ++ ++#define PR_USART0_bm 0x10 /* Port C USART0 bit mask. */ ++#define PR_USART0_bp 4 /* Port C USART0 bit position. */ ++ ++#define PR_SPI_bm 0x08 /* Port C SPI bit mask. */ ++#define PR_SPI_bp 3 /* Port C SPI bit position. */ ++ ++#define PR_HIRES_bm 0x04 /* Port C WEX bit mask. */ ++#define PR_HIRES_bp 2 /* Port C WEX bit position. */ ++ ++#define PR_TC5_bm 0x02 /* Port C Timer/Counter5 bit mask. */ ++#define PR_TC5_bp 1 /* Port C Timer/Counter5 bit position. */ ++ ++#define PR_TC4_bm 0x01 /* Port C Timer/Counter4 bit mask. */ ++#define PR_TC4_bp 0 /* Port C Timer/Counter4 bit position. */ ++ ++/* PR.PRPD bit masks and bit positions */ ++/* PR_USART0 Predefined. */ ++/* PR_USART0 Predefined. */ ++ ++/* PR_TC5 Predefined. */ ++/* PR_TC5 Predefined. */ ++ ++/* SLEEP - Sleep Controller */ ++/* SLEEP.CTRL bit masks and bit positions */ ++#define SLEEP_SMODE_gm 0x0E /* Sleep Mode group mask. */ ++#define SLEEP_SMODE_gp 1 /* Sleep Mode group position. */ ++#define SLEEP_SMODE0_bm (1<<1) /* Sleep Mode bit 0 mask. */ ++#define SLEEP_SMODE0_bp 1 /* Sleep Mode bit 0 position. */ ++#define SLEEP_SMODE1_bm (1<<2) /* Sleep Mode bit 1 mask. */ ++#define SLEEP_SMODE1_bp 2 /* Sleep Mode bit 1 position. */ ++#define SLEEP_SMODE2_bm (1<<3) /* Sleep Mode bit 2 mask. */ ++#define SLEEP_SMODE2_bp 3 /* Sleep Mode bit 2 position. */ ++ ++#define SLEEP_SEN_bm 0x01 /* Sleep Enable bit mask. */ ++#define SLEEP_SEN_bp 0 /* Sleep Enable bit position. */ ++ ++/* OSC - Oscillator */ ++/* OSC.CTRL bit masks and bit positions */ ++#define OSC_RC8MLPM_bm 0x40 /* Internal 8 MHz RC Low Power Mode Enable bit mask. */ ++#define OSC_RC8MLPM_bp 6 /* Internal 8 MHz RC Low Power Mode Enable bit position. */ ++ ++#define OSC_RC8MEN_bm 0x20 /* Internal 8 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC8MEN_bp 5 /* Internal 8 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_PLLEN_bm 0x10 /* PLL Enable bit mask. */ ++#define OSC_PLLEN_bp 4 /* PLL Enable bit position. */ ++ ++#define OSC_XOSCEN_bm 0x08 /* External Oscillator Enable bit mask. */ ++#define OSC_XOSCEN_bp 3 /* External Oscillator Enable bit position. */ ++ ++#define OSC_RC32KEN_bm 0x04 /* Internal 32.768 kHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32KEN_bp 2 /* Internal 32.768 kHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC32MEN_bm 0x02 /* Internal 32 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC32MEN_bp 1 /* Internal 32 MHz RC Oscillator Enable bit position. */ ++ ++#define OSC_RC2MEN_bm 0x01 /* Internal 2 MHz RC Oscillator Enable bit mask. */ ++#define OSC_RC2MEN_bp 0 /* Internal 2 MHz RC Oscillator Enable bit position. */ ++ ++/* OSC.STATUS bit masks and bit positions */ ++#define OSC_RC8MRDY_bm 0x20 /* Internal 8 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC8MRDY_bp 5 /* Internal 8 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_PLLRDY_bm 0x10 /* PLL Ready bit mask. */ ++#define OSC_PLLRDY_bp 4 /* PLL Ready bit position. */ ++ ++#define OSC_XOSCRDY_bm 0x08 /* External Oscillator Ready bit mask. */ ++#define OSC_XOSCRDY_bp 3 /* External Oscillator Ready bit position. */ ++ ++#define OSC_RC32KRDY_bm 0x04 /* Internal 32.768 kHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32KRDY_bp 2 /* Internal 32.768 kHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC32MRDY_bm 0x02 /* Internal 32 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC32MRDY_bp 1 /* Internal 32 MHz RC Oscillator Ready bit position. */ ++ ++#define OSC_RC2MRDY_bm 0x01 /* Internal 2 MHz RC Oscillator Ready bit mask. */ ++#define OSC_RC2MRDY_bp 0 /* Internal 2 MHz RC Oscillator Ready bit position. */ ++ ++/* OSC.XOSCCTRL bit masks and bit positions */ ++#define OSC_FRQRANGE_gm 0xC0 /* Frequency Range group mask. */ ++#define OSC_FRQRANGE_gp 6 /* Frequency Range group position. */ ++#define OSC_FRQRANGE0_bm (1<<6) /* Frequency Range bit 0 mask. */ ++#define OSC_FRQRANGE0_bp 6 /* Frequency Range bit 0 position. */ ++#define OSC_FRQRANGE1_bm (1<<7) /* Frequency Range bit 1 mask. */ ++#define OSC_FRQRANGE1_bp 7 /* Frequency Range bit 1 position. */ ++ ++#define OSC_X32KLPM_bm 0x20 /* 32.768 kHz XTAL OSC Low-power Mode bit mask. */ ++#define OSC_X32KLPM_bp 5 /* 32.768 kHz XTAL OSC Low-power Mode bit position. */ ++ ++#define OSC_XOSCPWR_bm 0x10 /* 16 MHz Crystal Oscillator High Power mode bit mask. */ ++#define OSC_XOSCPWR_bp 4 /* 16 MHz Crystal Oscillator High Power mode bit position. */ ++ ++#define OSC_XOSCSEL_gm 0x1F /* External Oscillator Selection and Startup Time group mask. */ ++#define OSC_XOSCSEL_gp 0 /* External Oscillator Selection and Startup Time group position. */ ++#define OSC_XOSCSEL0_bm (1<<0) /* External Oscillator Selection and Startup Time bit 0 mask. */ ++#define OSC_XOSCSEL0_bp 0 /* External Oscillator Selection and Startup Time bit 0 position. */ ++#define OSC_XOSCSEL1_bm (1<<1) /* External Oscillator Selection and Startup Time bit 1 mask. */ ++#define OSC_XOSCSEL1_bp 1 /* External Oscillator Selection and Startup Time bit 1 position. */ ++#define OSC_XOSCSEL2_bm (1<<2) /* External Oscillator Selection and Startup Time bit 2 mask. */ ++#define OSC_XOSCSEL2_bp 2 /* External Oscillator Selection and Startup Time bit 2 position. */ ++#define OSC_XOSCSEL3_bm (1<<3) /* External Oscillator Selection and Startup Time bit 3 mask. */ ++#define OSC_XOSCSEL3_bp 3 /* External Oscillator Selection and Startup Time bit 3 position. */ ++#define OSC_XOSCSEL4_bm (1<<4) /* External Oscillator Selection and Startup Time bit 4 mask. */ ++#define OSC_XOSCSEL4_bp 4 /* External Oscillator Selection and Startup Time bit 4 position. */ ++ ++/* OSC.XOSCFAIL bit masks and bit positions */ ++#define OSC_PLLFDIF_bm 0x08 /* PLL Failure Detection Interrupt Flag bit mask. */ ++#define OSC_PLLFDIF_bp 3 /* PLL Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_PLLFDEN_bm 0x04 /* PLL Failure Detection Enable bit mask. */ ++#define OSC_PLLFDEN_bp 2 /* PLL Failure Detection Enable bit position. */ ++ ++#define OSC_XOSCFDIF_bm 0x02 /* XOSC Failure Detection Interrupt Flag bit mask. */ ++#define OSC_XOSCFDIF_bp 1 /* XOSC Failure Detection Interrupt Flag bit position. */ ++ ++#define OSC_XOSCFDEN_bm 0x01 /* XOSC Failure Detection Enable bit mask. */ ++#define OSC_XOSCFDEN_bp 0 /* XOSC Failure Detection Enable bit position. */ ++ ++/* OSC.PLLCTRL bit masks and bit positions */ ++#define OSC_PLLSRC_gm 0xC0 /* Clock Source group mask. */ ++#define OSC_PLLSRC_gp 6 /* Clock Source group position. */ ++#define OSC_PLLSRC0_bm (1<<6) /* Clock Source bit 0 mask. */ ++#define OSC_PLLSRC0_bp 6 /* Clock Source bit 0 position. */ ++#define OSC_PLLSRC1_bm (1<<7) /* Clock Source bit 1 mask. */ ++#define OSC_PLLSRC1_bp 7 /* Clock Source bit 1 position. */ ++ ++#define OSC_PLLDIV_bm 0x20 /* Divide by 2 bit mask. */ ++#define OSC_PLLDIV_bp 5 /* Divide by 2 bit position. */ ++ ++#define OSC_PLLFAC_gm 0x1F /* Multiplication Factor group mask. */ ++#define OSC_PLLFAC_gp 0 /* Multiplication Factor group position. */ ++#define OSC_PLLFAC0_bm (1<<0) /* Multiplication Factor bit 0 mask. */ ++#define OSC_PLLFAC0_bp 0 /* Multiplication Factor bit 0 position. */ ++#define OSC_PLLFAC1_bm (1<<1) /* Multiplication Factor bit 1 mask. */ ++#define OSC_PLLFAC1_bp 1 /* Multiplication Factor bit 1 position. */ ++#define OSC_PLLFAC2_bm (1<<2) /* Multiplication Factor bit 2 mask. */ ++#define OSC_PLLFAC2_bp 2 /* Multiplication Factor bit 2 position. */ ++#define OSC_PLLFAC3_bm (1<<3) /* Multiplication Factor bit 3 mask. */ ++#define OSC_PLLFAC3_bp 3 /* Multiplication Factor bit 3 position. */ ++#define OSC_PLLFAC4_bm (1<<4) /* Multiplication Factor bit 4 mask. */ ++#define OSC_PLLFAC4_bp 4 /* Multiplication Factor bit 4 position. */ ++ ++/* OSC.DFLLCTRL bit masks and bit positions */ ++#define OSC_RC32MCREF_gm 0x06 /* 32 MHz DFLL Calibration Reference group mask. */ ++#define OSC_RC32MCREF_gp 1 /* 32 MHz DFLL Calibration Reference group position. */ ++#define OSC_RC32MCREF0_bm (1<<1) /* 32 MHz DFLL Calibration Reference bit 0 mask. */ ++#define OSC_RC32MCREF0_bp 1 /* 32 MHz DFLL Calibration Reference bit 0 position. */ ++#define OSC_RC32MCREF1_bm (1<<2) /* 32 MHz DFLL Calibration Reference bit 1 mask. */ ++#define OSC_RC32MCREF1_bp 2 /* 32 MHz DFLL Calibration Reference bit 1 position. */ ++ ++/* OSC.RC8MCAL bit masks and bit positions */ ++#define OSC_RC8MCAL_gm 0xFF /* Calibration Bits group mask. */ ++#define OSC_RC8MCAL_gp 0 /* Calibration Bits group position. */ ++#define OSC_RC8MCAL0_bm (1<<0) /* Calibration Bits bit 0 mask. */ ++#define OSC_RC8MCAL0_bp 0 /* Calibration Bits bit 0 position. */ ++#define OSC_RC8MCAL1_bm (1<<1) /* Calibration Bits bit 1 mask. */ ++#define OSC_RC8MCAL1_bp 1 /* Calibration Bits bit 1 position. */ ++#define OSC_RC8MCAL2_bm (1<<2) /* Calibration Bits bit 2 mask. */ ++#define OSC_RC8MCAL2_bp 2 /* Calibration Bits bit 2 position. */ ++#define OSC_RC8MCAL3_bm (1<<3) /* Calibration Bits bit 3 mask. */ ++#define OSC_RC8MCAL3_bp 3 /* Calibration Bits bit 3 position. */ ++#define OSC_RC8MCAL4_bm (1<<4) /* Calibration Bits bit 4 mask. */ ++#define OSC_RC8MCAL4_bp 4 /* Calibration Bits bit 4 position. */ ++#define OSC_RC8MCAL5_bm (1<<5) /* Calibration Bits bit 5 mask. */ ++#define OSC_RC8MCAL5_bp 5 /* Calibration Bits bit 5 position. */ ++#define OSC_RC8MCAL6_bm (1<<6) /* Calibration Bits bit 6 mask. */ ++#define OSC_RC8MCAL6_bp 6 /* Calibration Bits bit 6 position. */ ++#define OSC_RC8MCAL7_bm (1<<7) /* Calibration Bits bit 7 mask. */ ++#define OSC_RC8MCAL7_bp 7 /* Calibration Bits bit 7 position. */ ++ ++/* DFLL - DFLL */ ++/* DFLL.CTRL bit masks and bit positions */ ++#define DFLL_ENABLE_bm 0x01 /* DFLL Enable bit mask. */ ++#define DFLL_ENABLE_bp 0 /* DFLL Enable bit position. */ ++ ++/* DFLL.CALA bit masks and bit positions */ ++#define DFLL_CALL_gm 0x7F /* DFLL Calibration Value A group mask. */ ++#define DFLL_CALL_gp 0 /* DFLL Calibration Value A group position. */ ++#define DFLL_CALL0_bm (1<<0) /* DFLL Calibration Value A bit 0 mask. */ ++#define DFLL_CALL0_bp 0 /* DFLL Calibration Value A bit 0 position. */ ++#define DFLL_CALL1_bm (1<<1) /* DFLL Calibration Value A bit 1 mask. */ ++#define DFLL_CALL1_bp 1 /* DFLL Calibration Value A bit 1 position. */ ++#define DFLL_CALL2_bm (1<<2) /* DFLL Calibration Value A bit 2 mask. */ ++#define DFLL_CALL2_bp 2 /* DFLL Calibration Value A bit 2 position. */ ++#define DFLL_CALL3_bm (1<<3) /* DFLL Calibration Value A bit 3 mask. */ ++#define DFLL_CALL3_bp 3 /* DFLL Calibration Value A bit 3 position. */ ++#define DFLL_CALL4_bm (1<<4) /* DFLL Calibration Value A bit 4 mask. */ ++#define DFLL_CALL4_bp 4 /* DFLL Calibration Value A bit 4 position. */ ++#define DFLL_CALL5_bm (1<<5) /* DFLL Calibration Value A bit 5 mask. */ ++#define DFLL_CALL5_bp 5 /* DFLL Calibration Value A bit 5 position. */ ++#define DFLL_CALL6_bm (1<<6) /* DFLL Calibration Value A bit 6 mask. */ ++#define DFLL_CALL6_bp 6 /* DFLL Calibration Value A bit 6 position. */ ++ ++/* DFLL.CALB bit masks and bit positions */ ++#define DFLL_CALH_gm 0x3F /* DFLL Calibration Value B group mask. */ ++#define DFLL_CALH_gp 0 /* DFLL Calibration Value B group position. */ ++#define DFLL_CALH0_bm (1<<0) /* DFLL Calibration Value B bit 0 mask. */ ++#define DFLL_CALH0_bp 0 /* DFLL Calibration Value B bit 0 position. */ ++#define DFLL_CALH1_bm (1<<1) /* DFLL Calibration Value B bit 1 mask. */ ++#define DFLL_CALH1_bp 1 /* DFLL Calibration Value B bit 1 position. */ ++#define DFLL_CALH2_bm (1<<2) /* DFLL Calibration Value B bit 2 mask. */ ++#define DFLL_CALH2_bp 2 /* DFLL Calibration Value B bit 2 position. */ ++#define DFLL_CALH3_bm (1<<3) /* DFLL Calibration Value B bit 3 mask. */ ++#define DFLL_CALH3_bp 3 /* DFLL Calibration Value B bit 3 position. */ ++#define DFLL_CALH4_bm (1<<4) /* DFLL Calibration Value B bit 4 mask. */ ++#define DFLL_CALH4_bp 4 /* DFLL Calibration Value B bit 4 position. */ ++#define DFLL_CALH5_bm (1<<5) /* DFLL Calibration Value B bit 5 mask. */ ++#define DFLL_CALH5_bp 5 /* DFLL Calibration Value B bit 5 position. */ ++ ++/* RST - Reset */ ++/* RST.STATUS bit masks and bit positions */ ++#define RST_SDRF_bm 0x40 /* Spike Detection Reset Flag bit mask. */ ++#define RST_SDRF_bp 6 /* Spike Detection Reset Flag bit position. */ ++ ++#define RST_SRF_bm 0x20 /* Software Reset Flag bit mask. */ ++#define RST_SRF_bp 5 /* Software Reset Flag bit position. */ ++ ++#define RST_PDIRF_bm 0x10 /* Programming and Debug Interface Interface Reset Flag bit mask. */ ++#define RST_PDIRF_bp 4 /* Programming and Debug Interface Interface Reset Flag bit position. */ ++ ++#define RST_WDRF_bm 0x08 /* Watchdog Reset Flag bit mask. */ ++#define RST_WDRF_bp 3 /* Watchdog Reset Flag bit position. */ ++ ++#define RST_BORF_bm 0x04 /* Brown-out Reset Flag bit mask. */ ++#define RST_BORF_bp 2 /* Brown-out Reset Flag bit position. */ ++ ++#define RST_EXTRF_bm 0x02 /* External Reset Flag bit mask. */ ++#define RST_EXTRF_bp 1 /* External Reset Flag bit position. */ ++ ++#define RST_PORF_bm 0x01 /* Power-on Reset Flag bit mask. */ ++#define RST_PORF_bp 0 /* Power-on Reset Flag bit position. */ ++ ++/* RST.CTRL bit masks and bit positions */ ++#define RST_SWRST_bm 0x01 /* Software Reset bit mask. */ ++#define RST_SWRST_bp 0 /* Software Reset bit position. */ ++ ++/* WDT - Watch-Dog Timer */ ++/* WDT.CTRL bit masks and bit positions */ ++#define WDT_PER_gm 0x3C /* Period group mask. */ ++#define WDT_PER_gp 2 /* Period group position. */ ++#define WDT_PER0_bm (1<<2) /* Period bit 0 mask. */ ++#define WDT_PER0_bp 2 /* Period bit 0 position. */ ++#define WDT_PER1_bm (1<<3) /* Period bit 1 mask. */ ++#define WDT_PER1_bp 3 /* Period bit 1 position. */ ++#define WDT_PER2_bm (1<<4) /* Period bit 2 mask. */ ++#define WDT_PER2_bp 4 /* Period bit 2 position. */ ++#define WDT_PER3_bm (1<<5) /* Period bit 3 mask. */ ++#define WDT_PER3_bp 5 /* Period bit 3 position. */ ++ ++#define WDT_ENABLE_bm 0x02 /* Enable bit mask. */ ++#define WDT_ENABLE_bp 1 /* Enable bit position. */ ++ ++#define WDT_CEN_bm 0x01 /* Change Enable bit mask. */ ++#define WDT_CEN_bp 0 /* Change Enable bit position. */ ++ ++/* WDT.WINCTRL bit masks and bit positions */ ++#define WDT_WPER_gm 0x3C /* Windowed Mode Period group mask. */ ++#define WDT_WPER_gp 2 /* Windowed Mode Period group position. */ ++#define WDT_WPER0_bm (1<<2) /* Windowed Mode Period bit 0 mask. */ ++#define WDT_WPER0_bp 2 /* Windowed Mode Period bit 0 position. */ ++#define WDT_WPER1_bm (1<<3) /* Windowed Mode Period bit 1 mask. */ ++#define WDT_WPER1_bp 3 /* Windowed Mode Period bit 1 position. */ ++#define WDT_WPER2_bm (1<<4) /* Windowed Mode Period bit 2 mask. */ ++#define WDT_WPER2_bp 4 /* Windowed Mode Period bit 2 position. */ ++#define WDT_WPER3_bm (1<<5) /* Windowed Mode Period bit 3 mask. */ ++#define WDT_WPER3_bp 5 /* Windowed Mode Period bit 3 position. */ ++ ++#define WDT_WEN_bm 0x02 /* Windowed Mode Enable bit mask. */ ++#define WDT_WEN_bp 1 /* Windowed Mode Enable bit position. */ ++ ++#define WDT_WCEN_bm 0x01 /* Windowed Mode Change Enable bit mask. */ ++#define WDT_WCEN_bp 0 /* Windowed Mode Change Enable bit position. */ ++ ++/* WDT.STATUS bit masks and bit positions */ ++#define WDT_SYNCBUSY_bm 0x01 /* Syncronization busy bit mask. */ ++#define WDT_SYNCBUSY_bp 0 /* Syncronization busy bit position. */ ++ ++/* MCU - MCU Control */ ++/* MCU.ANAINIT bit masks and bit positions */ ++#define MCU_STARTUPDLYA_gm 0x03 /* Analog startup delay Port A group mask. */ ++#define MCU_STARTUPDLYA_gp 0 /* Analog startup delay Port A group position. */ ++#define MCU_STARTUPDLYA0_bm (1<<0) /* Analog startup delay Port A bit 0 mask. */ ++#define MCU_STARTUPDLYA0_bp 0 /* Analog startup delay Port A bit 0 position. */ ++#define MCU_STARTUPDLYA1_bm (1<<1) /* Analog startup delay Port A bit 1 mask. */ ++#define MCU_STARTUPDLYA1_bp 1 /* Analog startup delay Port A bit 1 position. */ ++ ++/* MCU.EVSYSLOCK bit masks and bit positions */ ++#define MCU_EVSYS1LOCK_bm 0x10 /* Event Channel 4-7 Lock bit mask. */ ++#define MCU_EVSYS1LOCK_bp 4 /* Event Channel 4-7 Lock bit position. */ ++ ++#define MCU_EVSYS0LOCK_bm 0x01 /* Event Channel 0-3 Lock bit mask. */ ++#define MCU_EVSYS0LOCK_bp 0 /* Event Channel 0-3 Lock bit position. */ ++ ++/* MCU.WEXLOCK bit masks and bit positions */ ++#define MCU_WEXCLOCK_bm 0x01 /* WeX on T/C C4 Lock bit mask. */ ++#define MCU_WEXCLOCK_bp 0 /* WeX on T/C C4 Lock bit position. */ ++ ++/* MCU.FAULTLOCK bit masks and bit positions */ ++#define MCU_FAULTC5LOCK_bm 0x02 /* Fault on T/C C5 Lock bit mask. */ ++#define MCU_FAULTC5LOCK_bp 1 /* Fault on T/C C5 Lock bit position. */ ++ ++#define MCU_FAULTC4LOCK_bm 0x01 /* Fault on T/C C4 Lock bit mask. */ ++#define MCU_FAULTC4LOCK_bp 0 /* Fault on T/C C4 Lock bit position. */ ++ ++/* PMIC - Programmable Multi-level Interrupt Controller */ ++/* PMIC.STATUS bit masks and bit positions */ ++#define PMIC_NMIEX_bm 0x80 /* Non-maskable Interrupt Executing bit mask. */ ++#define PMIC_NMIEX_bp 7 /* Non-maskable Interrupt Executing bit position. */ ++ ++#define PMIC_HILVLEX_bm 0x04 /* High Level Interrupt Executing bit mask. */ ++#define PMIC_HILVLEX_bp 2 /* High Level Interrupt Executing bit position. */ ++ ++#define PMIC_MEDLVLEX_bm 0x02 /* Medium Level Interrupt Executing bit mask. */ ++#define PMIC_MEDLVLEX_bp 1 /* Medium Level Interrupt Executing bit position. */ ++ ++#define PMIC_LOLVLEX_bm 0x01 /* Low Level Interrupt Executing bit mask. */ ++#define PMIC_LOLVLEX_bp 0 /* Low Level Interrupt Executing bit position. */ ++ ++/* PMIC.INTPRI bit masks and bit positions */ ++#define PMIC_INTPRI_gm 0xFF /* Interrupt Priority group mask. */ ++#define PMIC_INTPRI_gp 0 /* Interrupt Priority group position. */ ++#define PMIC_INTPRI0_bm (1<<0) /* Interrupt Priority bit 0 mask. */ ++#define PMIC_INTPRI0_bp 0 /* Interrupt Priority bit 0 position. */ ++#define PMIC_INTPRI1_bm (1<<1) /* Interrupt Priority bit 1 mask. */ ++#define PMIC_INTPRI1_bp 1 /* Interrupt Priority bit 1 position. */ ++#define PMIC_INTPRI2_bm (1<<2) /* Interrupt Priority bit 2 mask. */ ++#define PMIC_INTPRI2_bp 2 /* Interrupt Priority bit 2 position. */ ++#define PMIC_INTPRI3_bm (1<<3) /* Interrupt Priority bit 3 mask. */ ++#define PMIC_INTPRI3_bp 3 /* Interrupt Priority bit 3 position. */ ++#define PMIC_INTPRI4_bm (1<<4) /* Interrupt Priority bit 4 mask. */ ++#define PMIC_INTPRI4_bp 4 /* Interrupt Priority bit 4 position. */ ++#define PMIC_INTPRI5_bm (1<<5) /* Interrupt Priority bit 5 mask. */ ++#define PMIC_INTPRI5_bp 5 /* Interrupt Priority bit 5 position. */ ++#define PMIC_INTPRI6_bm (1<<6) /* Interrupt Priority bit 6 mask. */ ++#define PMIC_INTPRI6_bp 6 /* Interrupt Priority bit 6 position. */ ++#define PMIC_INTPRI7_bm (1<<7) /* Interrupt Priority bit 7 mask. */ ++#define PMIC_INTPRI7_bp 7 /* Interrupt Priority bit 7 position. */ ++ ++/* PMIC.CTRL bit masks and bit positions */ ++#define PMIC_RREN_bm 0x80 /* Round-Robin Priority Enable bit mask. */ ++#define PMIC_RREN_bp 7 /* Round-Robin Priority Enable bit position. */ ++ ++#define PMIC_IVSEL_bm 0x40 /* Interrupt Vector Select bit mask. */ ++#define PMIC_IVSEL_bp 6 /* Interrupt Vector Select bit position. */ ++ ++#define PMIC_HILVLEN_bm 0x04 /* High Level Enable bit mask. */ ++#define PMIC_HILVLEN_bp 2 /* High Level Enable bit position. */ ++ ++#define PMIC_MEDLVLEN_bm 0x02 /* Medium Level Enable bit mask. */ ++#define PMIC_MEDLVLEN_bp 1 /* Medium Level Enable bit position. */ ++ ++#define PMIC_LOLVLEN_bm 0x01 /* Low Level Enable bit mask. */ ++#define PMIC_LOLVLEN_bp 0 /* Low Level Enable bit position. */ ++ ++/* PORTCFG - Port Configuration */ ++/* PORTCFG.CLKOUT bit masks and bit positions */ ++#define PORTCFG_CLKEVPIN_bm 0x80 /* Clock and Event Output Pin Select bit mask. */ ++#define PORTCFG_CLKEVPIN_bp 7 /* Clock and Event Output Pin Select bit position. */ ++ ++#define PORTCFG_RTCOUT_gm 0x60 /* RTC Clock Output Enable group mask. */ ++#define PORTCFG_RTCOUT_gp 5 /* RTC Clock Output Enable group position. */ ++#define PORTCFG_RTCOUT0_bm (1<<5) /* RTC Clock Output Enable bit 0 mask. */ ++#define PORTCFG_RTCOUT0_bp 5 /* RTC Clock Output Enable bit 0 position. */ ++#define PORTCFG_RTCOUT1_bm (1<<6) /* RTC Clock Output Enable bit 1 mask. */ ++#define PORTCFG_RTCOUT1_bp 6 /* RTC Clock Output Enable bit 1 position. */ ++ ++#define PORTCFG_CLKOUTSEL_gm 0x0C /* Clock Output Select group mask. */ ++#define PORTCFG_CLKOUTSEL_gp 2 /* Clock Output Select group position. */ ++#define PORTCFG_CLKOUTSEL0_bm (1<<2) /* Clock Output Select bit 0 mask. */ ++#define PORTCFG_CLKOUTSEL0_bp 2 /* Clock Output Select bit 0 position. */ ++#define PORTCFG_CLKOUTSEL1_bm (1<<3) /* Clock Output Select bit 1 mask. */ ++#define PORTCFG_CLKOUTSEL1_bp 3 /* Clock Output Select bit 1 position. */ ++ ++#define PORTCFG_CLKOUT_gm 0x03 /* Clock Output Port group mask. */ ++#define PORTCFG_CLKOUT_gp 0 /* Clock Output Port group position. */ ++#define PORTCFG_CLKOUT0_bm (1<<0) /* Clock Output Port bit 0 mask. */ ++#define PORTCFG_CLKOUT0_bp 0 /* Clock Output Port bit 0 position. */ ++#define PORTCFG_CLKOUT1_bm (1<<1) /* Clock Output Port bit 1 mask. */ ++#define PORTCFG_CLKOUT1_bp 1 /* Clock Output Port bit 1 position. */ ++ ++/* PORTCFG.ACEVOUT bit masks and bit positions */ ++#define PORTCFG_ACOUT_gm 0xC0 /* Analog Comparator Output Port group mask. */ ++#define PORTCFG_ACOUT_gp 6 /* Analog Comparator Output Port group position. */ ++#define PORTCFG_ACOUT0_bm (1<<6) /* Analog Comparator Output Port bit 0 mask. */ ++#define PORTCFG_ACOUT0_bp 6 /* Analog Comparator Output Port bit 0 position. */ ++#define PORTCFG_ACOUT1_bm (1<<7) /* Analog Comparator Output Port bit 1 mask. */ ++#define PORTCFG_ACOUT1_bp 7 /* Analog Comparator Output Port bit 1 position. */ ++ ++#define PORTCFG_EVOUT_gm 0x30 /* Event Channel Output Port group mask. */ ++#define PORTCFG_EVOUT_gp 4 /* Event Channel Output Port group position. */ ++#define PORTCFG_EVOUT0_bm (1<<4) /* Event Channel Output Port bit 0 mask. */ ++#define PORTCFG_EVOUT0_bp 4 /* Event Channel Output Port bit 0 position. */ ++#define PORTCFG_EVOUT1_bm (1<<5) /* Event Channel Output Port bit 1 mask. */ ++#define PORTCFG_EVOUT1_bp 5 /* Event Channel Output Port bit 1 position. */ ++ ++#define PORTCFG_EVASYEN_bm 0x08 /* Asynchronous Event Enabled bit mask. */ ++#define PORTCFG_EVASYEN_bp 3 /* Asynchronous Event Enabled bit position. */ ++ ++#define PORTCFG_EVOUTSEL_gm 0x07 /* Event Channel Output Selection group mask. */ ++#define PORTCFG_EVOUTSEL_gp 0 /* Event Channel Output Selection group position. */ ++#define PORTCFG_EVOUTSEL0_bm (1<<0) /* Event Channel Output Selection bit 0 mask. */ ++#define PORTCFG_EVOUTSEL0_bp 0 /* Event Channel Output Selection bit 0 position. */ ++#define PORTCFG_EVOUTSEL1_bm (1<<1) /* Event Channel Output Selection bit 1 mask. */ ++#define PORTCFG_EVOUTSEL1_bp 1 /* Event Channel Output Selection bit 1 position. */ ++#define PORTCFG_EVOUTSEL2_bm (1<<2) /* Event Channel Output Selection bit 2 mask. */ ++#define PORTCFG_EVOUTSEL2_bp 2 /* Event Channel Output Selection bit 2 position. */ ++ ++/* PORTCFG.SRLCTRL bit masks and bit positions */ ++#define PORTCFG_SRLENRA_bm 0x01 /* Slew Rate Limit Enable on PORTA bit mask. */ ++#define PORTCFG_SRLENRA_bp 0 /* Slew Rate Limit Enable on PORTA bit position. */ ++ ++#define PORTCFG_SRLENRC_bm 0x04 /* Slew Rate Limit Enable on PORTC bit mask. */ ++#define PORTCFG_SRLENRC_bp 2 /* Slew Rate Limit Enable on PORTC bit position. */ ++ ++#define PORTCFG_SRLENRD_bm 0x08 /* Slew Rate Limit Enable on PORTD bit mask. */ ++#define PORTCFG_SRLENRD_bp 3 /* Slew Rate Limit Enable on PORTD bit position. */ ++ ++#define PORTCFG_SRLENRR_bm 0x80 /* Slew Rate Limit Enable on PORTR bit mask. */ ++#define PORTCFG_SRLENRR_bp 7 /* Slew Rate Limit Enable on PORTR bit position. */ ++ ++/* CRC - Cyclic Redundancy Checker */ ++/* CRC.CTRL bit masks and bit positions */ ++#define CRC_RESET_gm 0xC0 /* Reset group mask. */ ++#define CRC_RESET_gp 6 /* Reset group position. */ ++#define CRC_RESET0_bm (1<<6) /* Reset bit 0 mask. */ ++#define CRC_RESET0_bp 6 /* Reset bit 0 position. */ ++#define CRC_RESET1_bm (1<<7) /* Reset bit 1 mask. */ ++#define CRC_RESET1_bp 7 /* Reset bit 1 position. */ ++ ++#define CRC_CRC32_bm 0x20 /* CRC Mode bit mask. */ ++#define CRC_CRC32_bp 5 /* CRC Mode bit position. */ ++ ++#define CRC_SOURCE_gm 0x0F /* Input Source group mask. */ ++#define CRC_SOURCE_gp 0 /* Input Source group position. */ ++#define CRC_SOURCE0_bm (1<<0) /* Input Source bit 0 mask. */ ++#define CRC_SOURCE0_bp 0 /* Input Source bit 0 position. */ ++#define CRC_SOURCE1_bm (1<<1) /* Input Source bit 1 mask. */ ++#define CRC_SOURCE1_bp 1 /* Input Source bit 1 position. */ ++#define CRC_SOURCE2_bm (1<<2) /* Input Source bit 2 mask. */ ++#define CRC_SOURCE2_bp 2 /* Input Source bit 2 position. */ ++#define CRC_SOURCE3_bm (1<<3) /* Input Source bit 3 mask. */ ++#define CRC_SOURCE3_bp 3 /* Input Source bit 3 position. */ ++ ++/* CRC.STATUS bit masks and bit positions */ ++#define CRC_ZERO_bm 0x02 /* Zero detection bit mask. */ ++#define CRC_ZERO_bp 1 /* Zero detection bit position. */ ++ ++#define CRC_BUSY_bm 0x01 /* Busy bit mask. */ ++#define CRC_BUSY_bp 0 /* Busy bit position. */ ++ ++/* EDMA - Enhanced DMA Controller */ ++/* EDMA.CTRL bit masks and bit positions */ ++#define EDMA_ENABLE_bm 0x80 /* Enable bit mask. */ ++#define EDMA_ENABLE_bp 7 /* Enable bit position. */ ++ ++#define EDMA_RESET_bm 0x40 /* Software Reset bit mask. */ ++#define EDMA_RESET_bp 6 /* Software Reset bit position. */ ++ ++#define EDMA_CHMODE_gm 0x30 /* Channel Mode group mask. */ ++#define EDMA_CHMODE_gp 4 /* Channel Mode group position. */ ++#define EDMA_CHMODE0_bm (1<<4) /* Channel Mode bit 0 mask. */ ++#define EDMA_CHMODE0_bp 4 /* Channel Mode bit 0 position. */ ++#define EDMA_CHMODE1_bm (1<<5) /* Channel Mode bit 1 mask. */ ++#define EDMA_CHMODE1_bp 5 /* Channel Mode bit 1 position. */ ++ ++#define EDMA_DBUFMODE_gm 0x0C /* Double Buffer Mode group mask. */ ++#define EDMA_DBUFMODE_gp 2 /* Double Buffer Mode group position. */ ++#define EDMA_DBUFMODE0_bm (1<<2) /* Double Buffer Mode bit 0 mask. */ ++#define EDMA_DBUFMODE0_bp 2 /* Double Buffer Mode bit 0 position. */ ++#define EDMA_DBUFMODE1_bm (1<<3) /* Double Buffer Mode bit 1 mask. */ ++#define EDMA_DBUFMODE1_bp 3 /* Double Buffer Mode bit 1 position. */ ++ ++#define EDMA_PRIMODE_gm 0x03 /* Priority Mode group mask. */ ++#define EDMA_PRIMODE_gp 0 /* Priority Mode group position. */ ++#define EDMA_PRIMODE0_bm (1<<0) /* Priority Mode bit 0 mask. */ ++#define EDMA_PRIMODE0_bp 0 /* Priority Mode bit 0 position. */ ++#define EDMA_PRIMODE1_bm (1<<1) /* Priority Mode bit 1 mask. */ ++#define EDMA_PRIMODE1_bp 1 /* Priority Mode bit 1 position. */ ++ ++/* EDMA.INTFLAGS bit masks and bit positions */ ++#define EDMA_CH3ERRIF_bm 0x80 /* Channel 3 Transaction Error Interrupt Flag bit mask. */ ++#define EDMA_CH3ERRIF_bp 7 /* Channel 3 Transaction Error Interrupt Flag bit position. */ ++ ++#define EDMA_CH2ERRIF_bm 0x40 /* Channel 2 Transaction Error Interrupt Flag bit mask. */ ++#define EDMA_CH2ERRIF_bp 6 /* Channel 2 Transaction Error Interrupt Flag bit position. */ ++ ++#define EDMA_CH1ERRIF_bm 0x20 /* Channel 1 Transaction Error Interrupt Flag bit mask. */ ++#define EDMA_CH1ERRIF_bp 5 /* Channel 1 Transaction Error Interrupt Flag bit position. */ ++ ++#define EDMA_CH0ERRIF_bm 0x10 /* Channel 0 Transaction Error Interrupt Flag bit mask. */ ++#define EDMA_CH0ERRIF_bp 4 /* Channel 0 Transaction Error Interrupt Flag bit position. */ ++ ++#define EDMA_CH3TRNFIF_bm 0x08 /* Channel 3 Transaction Complete Interrupt Flag bit mask. */ ++#define EDMA_CH3TRNFIF_bp 3 /* Channel 3 Transaction Complete Interrupt Flag bit position. */ ++ ++#define EDMA_CH2TRNFIF_bm 0x04 /* Channel 2 Transaction Complete Interrupt Flag bit mask. */ ++#define EDMA_CH2TRNFIF_bp 2 /* Channel 2 Transaction Complete Interrupt Flag bit position. */ ++ ++#define EDMA_CH1TRNFIF_bm 0x02 /* Channel 1 Transaction Complete Interrupt Flag bit mask. */ ++#define EDMA_CH1TRNFIF_bp 1 /* Channel 1 Transaction Complete Interrupt Flag bit position. */ ++ ++#define EDMA_CH0TRNFIF_bm 0x01 /* Channel 0 Transaction Complete Interrupt Flag bit mask. */ ++#define EDMA_CH0TRNFIF_bp 0 /* Channel 0 Transaction Complete Interrupt Flag bit position. */ ++ ++/* EDMA.STATUS bit masks and bit positions */ ++#define EDMA_CH3BUSY_bm 0x80 /* Channel 3 Busy Flag bit mask. */ ++#define EDMA_CH3BUSY_bp 7 /* Channel 3 Busy Flag bit position. */ ++ ++#define EDMA_CH2BUSY_bm 0x40 /* Channel 2 Busy Flag bit mask. */ ++#define EDMA_CH2BUSY_bp 6 /* Channel 2 Busy Flag bit position. */ ++ ++#define EDMA_CH1BUSY_bm 0x20 /* Channel 1 Busy Flag bit mask. */ ++#define EDMA_CH1BUSY_bp 5 /* Channel 1 Busy Flag bit position. */ ++ ++#define EDMA_CH0BUSY_bm 0x10 /* Channel 0 Busy Flag bit mask. */ ++#define EDMA_CH0BUSY_bp 4 /* Channel 0 Busy Flag bit position. */ ++ ++#define EDMA_CH3PEND_bm 0x08 /* Channel 3 Pending Flag bit mask. */ ++#define EDMA_CH3PEND_bp 3 /* Channel 3 Pending Flag bit position. */ ++ ++#define EDMA_CH2PEND_bm 0x04 /* Channel 2 Pending Flag bit mask. */ ++#define EDMA_CH2PEND_bp 2 /* Channel 2 Pending Flag bit position. */ ++ ++#define EDMA_CH1PEND_bm 0x02 /* Channel 1 Pending Flag bit mask. */ ++#define EDMA_CH1PEND_bp 1 /* Channel 1 Pending Flag bit position. */ ++ ++#define EDMA_CH0PEND_bm 0x01 /* Channel 0 Pending Flag bit mask. */ ++#define EDMA_CH0PEND_bp 0 /* Channel 0 Pending Flag bit position. */ ++ ++/* EDMA_CH.CTRLA bit masks and bit positions */ ++#define EDMA_CH_ENABLE_bm 0x80 /* Channel Enable bit mask. */ ++#define EDMA_CH_ENABLE_bp 7 /* Channel Enable bit position. */ ++ ++#define EDMA_CH_RESET_bm 0x40 /* Channel Software Reset bit mask. */ ++#define EDMA_CH_RESET_bp 6 /* Channel Software Reset bit position. */ ++ ++#define EDMA_CH_REPEAT_bm 0x20 /* Channel Repeat Mode bit mask. */ ++#define EDMA_CH_REPEAT_bp 5 /* Channel Repeat Mode bit position. */ ++ ++#define EDMA_CH_TRFREQ_bm 0x10 /* Channel Transfer Request bit mask. */ ++#define EDMA_CH_TRFREQ_bp 4 /* Channel Transfer Request bit position. */ ++ ++#define EDMA_CH_SINGLE_bm 0x04 /* Channel Single Shot Data Transfer bit mask. */ ++#define EDMA_CH_SINGLE_bp 2 /* Channel Single Shot Data Transfer bit position. */ ++ ++#define EDMA_CH_BURSTLEN_bm 0x01 /* Channel 2-bytes Burst Length bit mask. */ ++#define EDMA_CH_BURSTLEN_bp 0 /* Channel 2-bytes Burst Length bit position. */ ++ ++/* EDMA_CH.CTRLB bit masks and bit positions */ ++#define EDMA_CH_CHBUSY_bm 0x80 /* Channel Block Transfer Busy bit mask. */ ++#define EDMA_CH_CHBUSY_bp 7 /* Channel Block Transfer Busy bit position. */ ++ ++#define EDMA_CH_CHPEND_bm 0x40 /* Channel Block Transfer Pending bit mask. */ ++#define EDMA_CH_CHPEND_bp 6 /* Channel Block Transfer Pending bit position. */ ++ ++#define EDMA_CH_ERRIF_bm 0x20 /* Channel Transaction Error Interrupt Flag bit mask. */ ++#define EDMA_CH_ERRIF_bp 5 /* Channel Transaction Error Interrupt Flag bit position. */ ++ ++#define EDMA_CH_TRNIF_bm 0x10 /* Channel Transaction Complete Interrup Flag bit mask. */ ++#define EDMA_CH_TRNIF_bp 4 /* Channel Transaction Complete Interrup Flag bit position. */ ++ ++#define EDMA_CH_ERRINTLVL_gm 0x0C /* Channel Transaction Error Interrupt Level group mask. */ ++#define EDMA_CH_ERRINTLVL_gp 2 /* Channel Transaction Error Interrupt Level group position. */ ++#define EDMA_CH_ERRINTLVL0_bm (1<<2) /* Channel Transaction Error Interrupt Level bit 0 mask. */ ++#define EDMA_CH_ERRINTLVL0_bp 2 /* Channel Transaction Error Interrupt Level bit 0 position. */ ++#define EDMA_CH_ERRINTLVL1_bm (1<<3) /* Channel Transaction Error Interrupt Level bit 1 mask. */ ++#define EDMA_CH_ERRINTLVL1_bp 3 /* Channel Transaction Error Interrupt Level bit 1 position. */ ++ ++#define EDMA_CH_TRNINTLVL_gm 0x03 /* Channel Transaction Complete Interrupt Level group mask. */ ++#define EDMA_CH_TRNINTLVL_gp 0 /* Channel Transaction Complete Interrupt Level group position. */ ++#define EDMA_CH_TRNINTLVL0_bm (1<<0) /* Channel Transaction Complete Interrupt Level bit 0 mask. */ ++#define EDMA_CH_TRNINTLVL0_bp 0 /* Channel Transaction Complete Interrupt Level bit 0 position. */ ++#define EDMA_CH_TRNINTLVL1_bm (1<<1) /* Channel Transaction Complete Interrupt Level bit 1 mask. */ ++#define EDMA_CH_TRNINTLVL1_bp 1 /* Channel Transaction Complete Interrupt Level bit 1 position. */ ++ ++/* EDMA_CH.ADDRCTRL bit masks and bit positions */ ++#define EDMA_CH_RELOAD_gm 0x30 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group mask. */ ++#define EDMA_CH_RELOAD_gp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. group position. */ ++#define EDMA_CH_RELOAD0_bm (1<<4) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 mask. */ ++#define EDMA_CH_RELOAD0_bp 4 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 0 position. */ ++#define EDMA_CH_RELOAD1_bm (1<<5) /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 mask. */ ++#define EDMA_CH_RELOAD1_bp 5 /* Memory Address Reload for Peripheral Ch., or Source Address Reload for Standard Ch. bit 1 position. */ ++ ++#define EDMA_CH_DIR_gm 0x07 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group mask. */ ++#define EDMA_CH_DIR_gp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. group position. */ ++#define EDMA_CH_DIR0_bm (1<<0) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 mask. */ ++#define EDMA_CH_DIR0_bp 0 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 0 position. */ ++#define EDMA_CH_DIR1_bm (1<<1) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 mask. */ ++#define EDMA_CH_DIR1_bp 1 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 1 position. */ ++#define EDMA_CH_DIR2_bm (1<<2) /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 mask. */ ++#define EDMA_CH_DIR2_bp 2 /* Memory Address Mode for Peripheral Ch., or Source Address Mode for Standard Ch. bit 2 position. */ ++ ++/* EDMA_CH.DESTADDRCTRL bit masks and bit positions */ ++#define EDMA_CH_DESTRELOAD_gm 0x30 /* Destination Address Reload for Standard Channels Only. group mask. */ ++#define EDMA_CH_DESTRELOAD_gp 4 /* Destination Address Reload for Standard Channels Only. group position. */ ++#define EDMA_CH_DESTRELOAD0_bm (1<<4) /* Destination Address Reload for Standard Channels Only. bit 0 mask. */ ++#define EDMA_CH_DESTRELOAD0_bp 4 /* Destination Address Reload for Standard Channels Only. bit 0 position. */ ++#define EDMA_CH_DESTRELOAD1_bm (1<<5) /* Destination Address Reload for Standard Channels Only. bit 1 mask. */ ++#define EDMA_CH_DESTRELOAD1_bp 5 /* Destination Address Reload for Standard Channels Only. bit 1 position. */ ++ ++#define EDMA_CH_DESTDIR_gm 0x07 /* Destination Address Mode for Standard Channels Only. group mask. */ ++#define EDMA_CH_DESTDIR_gp 0 /* Destination Address Mode for Standard Channels Only. group position. */ ++#define EDMA_CH_DESTDIR0_bm (1<<0) /* Destination Address Mode for Standard Channels Only. bit 0 mask. */ ++#define EDMA_CH_DESTDIR0_bp 0 /* Destination Address Mode for Standard Channels Only. bit 0 position. */ ++#define EDMA_CH_DESTDIR1_bm (1<<1) /* Destination Address Mode for Standard Channels Only. bit 1 mask. */ ++#define EDMA_CH_DESTDIR1_bp 1 /* Destination Address Mode for Standard Channels Only. bit 1 position. */ ++#define EDMA_CH_DESTDIR2_bm (1<<2) /* Destination Address Mode for Standard Channels Only. bit 2 mask. */ ++#define EDMA_CH_DESTDIR2_bp 2 /* Destination Address Mode for Standard Channels Only. bit 2 position. */ ++ ++/* EDMA_CH.TRIGSRC bit masks and bit positions */ ++#define EDMA_CH_TRIGSRC_gm 0xFF /* Channel Trigger Source group mask. */ ++#define EDMA_CH_TRIGSRC_gp 0 /* Channel Trigger Source group position. */ ++#define EDMA_CH_TRIGSRC0_bm (1<<0) /* Channel Trigger Source bit 0 mask. */ ++#define EDMA_CH_TRIGSRC0_bp 0 /* Channel Trigger Source bit 0 position. */ ++#define EDMA_CH_TRIGSRC1_bm (1<<1) /* Channel Trigger Source bit 1 mask. */ ++#define EDMA_CH_TRIGSRC1_bp 1 /* Channel Trigger Source bit 1 position. */ ++#define EDMA_CH_TRIGSRC2_bm (1<<2) /* Channel Trigger Source bit 2 mask. */ ++#define EDMA_CH_TRIGSRC2_bp 2 /* Channel Trigger Source bit 2 position. */ ++#define EDMA_CH_TRIGSRC3_bm (1<<3) /* Channel Trigger Source bit 3 mask. */ ++#define EDMA_CH_TRIGSRC3_bp 3 /* Channel Trigger Source bit 3 position. */ ++#define EDMA_CH_TRIGSRC4_bm (1<<4) /* Channel Trigger Source bit 4 mask. */ ++#define EDMA_CH_TRIGSRC4_bp 4 /* Channel Trigger Source bit 4 position. */ ++#define EDMA_CH_TRIGSRC5_bm (1<<5) /* Channel Trigger Source bit 5 mask. */ ++#define EDMA_CH_TRIGSRC5_bp 5 /* Channel Trigger Source bit 5 position. */ ++#define EDMA_CH_TRIGSRC6_bm (1<<6) /* Channel Trigger Source bit 6 mask. */ ++#define EDMA_CH_TRIGSRC6_bp 6 /* Channel Trigger Source bit 6 position. */ ++#define EDMA_CH_TRIGSRC7_bm (1<<7) /* Channel Trigger Source bit 7 mask. */ ++#define EDMA_CH_TRIGSRC7_bp 7 /* Channel Trigger Source bit 7 position. */ ++ ++/* EVSYS - Event System */ ++/* EVSYS.CH0MUX bit masks and bit positions */ ++#define EVSYS_CHMUX_gm 0xFF /* Event Channel 0 Multiplexer group mask. */ ++#define EVSYS_CHMUX_gp 0 /* Event Channel 0 Multiplexer group position. */ ++#define EVSYS_CHMUX0_bm (1<<0) /* Event Channel 0 Multiplexer bit 0 mask. */ ++#define EVSYS_CHMUX0_bp 0 /* Event Channel 0 Multiplexer bit 0 position. */ ++#define EVSYS_CHMUX1_bm (1<<1) /* Event Channel 0 Multiplexer bit 1 mask. */ ++#define EVSYS_CHMUX1_bp 1 /* Event Channel 0 Multiplexer bit 1 position. */ ++#define EVSYS_CHMUX2_bm (1<<2) /* Event Channel 0 Multiplexer bit 2 mask. */ ++#define EVSYS_CHMUX2_bp 2 /* Event Channel 0 Multiplexer bit 2 position. */ ++#define EVSYS_CHMUX3_bm (1<<3) /* Event Channel 0 Multiplexer bit 3 mask. */ ++#define EVSYS_CHMUX3_bp 3 /* Event Channel 0 Multiplexer bit 3 position. */ ++#define EVSYS_CHMUX4_bm (1<<4) /* Event Channel 0 Multiplexer bit 4 mask. */ ++#define EVSYS_CHMUX4_bp 4 /* Event Channel 0 Multiplexer bit 4 position. */ ++#define EVSYS_CHMUX5_bm (1<<5) /* Event Channel 0 Multiplexer bit 5 mask. */ ++#define EVSYS_CHMUX5_bp 5 /* Event Channel 0 Multiplexer bit 5 position. */ ++#define EVSYS_CHMUX6_bm (1<<6) /* Event Channel 0 Multiplexer bit 6 mask. */ ++#define EVSYS_CHMUX6_bp 6 /* Event Channel 0 Multiplexer bit 6 position. */ ++#define EVSYS_CHMUX7_bm (1<<7) /* Event Channel 0 Multiplexer bit 7 mask. */ ++#define EVSYS_CHMUX7_bp 7 /* Event Channel 0 Multiplexer bit 7 position. */ ++ ++/* EVSYS.CH1MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH2MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH3MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH4MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH5MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH6MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH7MUX bit masks and bit positions */ ++/* EVSYS_CHMUX Predefined. */ ++/* EVSYS_CHMUX Predefined. */ ++ ++/* EVSYS.CH0CTRL bit masks and bit positions */ ++#define EVSYS_ROTARY_bm 0x80 /* Rotary Decoder Enable bit mask. */ ++#define EVSYS_ROTARY_bp 7 /* Rotary Decoder Enable bit position. */ ++ ++#define EVSYS_QDIRM_gm 0x60 /* Quadrature Decoder Index Recognition Mode group mask. */ ++#define EVSYS_QDIRM_gp 5 /* Quadrature Decoder Index Recognition Mode group position. */ ++#define EVSYS_QDIRM0_bm (1<<5) /* Quadrature Decoder Index Recognition Mode bit 0 mask. */ ++#define EVSYS_QDIRM0_bp 5 /* Quadrature Decoder Index Recognition Mode bit 0 position. */ ++#define EVSYS_QDIRM1_bm (1<<6) /* Quadrature Decoder Index Recognition Mode bit 1 mask. */ ++#define EVSYS_QDIRM1_bp 6 /* Quadrature Decoder Index Recognition Mode bit 1 position. */ ++ ++#define EVSYS_QDIEN_bm 0x10 /* Quadrature Decoder Index Enable bit mask. */ ++#define EVSYS_QDIEN_bp 4 /* Quadrature Decoder Index Enable bit position. */ ++ ++#define EVSYS_QDEN_bm 0x08 /* Quadrature Decoder Enable bit mask. */ ++#define EVSYS_QDEN_bp 3 /* Quadrature Decoder Enable bit position. */ ++ ++#define EVSYS_DIGFILT_gm 0x07 /* Digital Filter group mask. */ ++#define EVSYS_DIGFILT_gp 0 /* Digital Filter group position. */ ++#define EVSYS_DIGFILT0_bm (1<<0) /* Digital Filter bit 0 mask. */ ++#define EVSYS_DIGFILT0_bp 0 /* Digital Filter bit 0 position. */ ++#define EVSYS_DIGFILT1_bm (1<<1) /* Digital Filter bit 1 mask. */ ++#define EVSYS_DIGFILT1_bp 1 /* Digital Filter bit 1 position. */ ++#define EVSYS_DIGFILT2_bm (1<<2) /* Digital Filter bit 2 mask. */ ++#define EVSYS_DIGFILT2_bp 2 /* Digital Filter bit 2 position. */ ++ ++/* EVSYS.CH1CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH2CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH3CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH4CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH5CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH6CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.CH7CTRL bit masks and bit positions */ ++/* EVSYS_DIGFILT Predefined. */ ++/* EVSYS_DIGFILT Predefined. */ ++ ++/* EVSYS.DFCTRL bit masks and bit positions */ ++#define EVSYS_PRESCFILT_gm 0xF0 /* Prescaler Filter group mask. */ ++#define EVSYS_PRESCFILT_gp 4 /* Prescaler Filter group position. */ ++#define EVSYS_PRESCFILT0_bm (1<<4) /* Prescaler Filter bit 0 mask. */ ++#define EVSYS_PRESCFILT0_bp 4 /* Prescaler Filter bit 0 position. */ ++#define EVSYS_PRESCFILT1_bm (1<<5) /* Prescaler Filter bit 1 mask. */ ++#define EVSYS_PRESCFILT1_bp 5 /* Prescaler Filter bit 1 position. */ ++#define EVSYS_PRESCFILT2_bm (1<<6) /* Prescaler Filter bit 2 mask. */ ++#define EVSYS_PRESCFILT2_bp 6 /* Prescaler Filter bit 2 position. */ ++#define EVSYS_PRESCFILT3_bm (1<<7) /* Prescaler Filter bit 3 mask. */ ++#define EVSYS_PRESCFILT3_bp 7 /* Prescaler Filter bit 3 position. */ ++ ++#define EVSYS_FILTSEL_bm 0x08 /* Prescaler Filter Select bit mask. */ ++#define EVSYS_FILTSEL_bp 3 /* Prescaler Filter Select bit position. */ ++ ++#define EVSYS_PRESC_gm 0x07 /* Prescaler group mask. */ ++#define EVSYS_PRESC_gp 0 /* Prescaler group position. */ ++#define EVSYS_PRESC0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define EVSYS_PRESC0_bp 0 /* Prescaler bit 0 position. */ ++#define EVSYS_PRESC1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define EVSYS_PRESC1_bp 1 /* Prescaler bit 1 position. */ ++#define EVSYS_PRESC2_bm (1<<2) /* Prescaler bit 2 mask. */ ++#define EVSYS_PRESC2_bp 2 /* Prescaler bit 2 position. */ ++ ++/* NVM - Non Volatile Memory Controller */ ++/* NVM.CMD bit masks and bit positions */ ++#define NVM_CMD_gm 0x7F /* Command group mask. */ ++#define NVM_CMD_gp 0 /* Command group position. */ ++#define NVM_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define NVM_CMD0_bp 0 /* Command bit 0 position. */ ++#define NVM_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define NVM_CMD1_bp 1 /* Command bit 1 position. */ ++#define NVM_CMD2_bm (1<<2) /* Command bit 2 mask. */ ++#define NVM_CMD2_bp 2 /* Command bit 2 position. */ ++#define NVM_CMD3_bm (1<<3) /* Command bit 3 mask. */ ++#define NVM_CMD3_bp 3 /* Command bit 3 position. */ ++#define NVM_CMD4_bm (1<<4) /* Command bit 4 mask. */ ++#define NVM_CMD4_bp 4 /* Command bit 4 position. */ ++#define NVM_CMD5_bm (1<<5) /* Command bit 5 mask. */ ++#define NVM_CMD5_bp 5 /* Command bit 5 position. */ ++#define NVM_CMD6_bm (1<<6) /* Command bit 6 mask. */ ++#define NVM_CMD6_bp 6 /* Command bit 6 position. */ ++ ++/* NVM.CTRLA bit masks and bit positions */ ++#define NVM_CMDEX_bm 0x01 /* Command Execute bit mask. */ ++#define NVM_CMDEX_bp 0 /* Command Execute bit position. */ ++ ++/* NVM.CTRLB bit masks and bit positions */ ++#define NVM_EPRM_bm 0x02 /* EEPROM Power Reduction Enable bit mask. */ ++#define NVM_EPRM_bp 1 /* EEPROM Power Reduction Enable bit position. */ ++ ++#define NVM_SPMLOCK_bm 0x01 /* SPM Lock bit mask. */ ++#define NVM_SPMLOCK_bp 0 /* SPM Lock bit position. */ ++ ++/* NVM.INTCTRL bit masks and bit positions */ ++#define NVM_SPMLVL_gm 0x0C /* SPM Interrupt Level group mask. */ ++#define NVM_SPMLVL_gp 2 /* SPM Interrupt Level group position. */ ++#define NVM_SPMLVL0_bm (1<<2) /* SPM Interrupt Level bit 0 mask. */ ++#define NVM_SPMLVL0_bp 2 /* SPM Interrupt Level bit 0 position. */ ++#define NVM_SPMLVL1_bm (1<<3) /* SPM Interrupt Level bit 1 mask. */ ++#define NVM_SPMLVL1_bp 3 /* SPM Interrupt Level bit 1 position. */ ++ ++#define NVM_EELVL_gm 0x03 /* EEPROM Interrupt Level group mask. */ ++#define NVM_EELVL_gp 0 /* EEPROM Interrupt Level group position. */ ++#define NVM_EELVL0_bm (1<<0) /* EEPROM Interrupt Level bit 0 mask. */ ++#define NVM_EELVL0_bp 0 /* EEPROM Interrupt Level bit 0 position. */ ++#define NVM_EELVL1_bm (1<<1) /* EEPROM Interrupt Level bit 1 mask. */ ++#define NVM_EELVL1_bp 1 /* EEPROM Interrupt Level bit 1 position. */ ++ ++/* NVM.STATUS bit masks and bit positions */ ++#define NVM_NVMBUSY_bm 0x80 /* Non-volatile Memory Busy bit mask. */ ++#define NVM_NVMBUSY_bp 7 /* Non-volatile Memory Busy bit position. */ ++ ++#define NVM_FBUSY_bm 0x40 /* Flash Memory Busy bit mask. */ ++#define NVM_FBUSY_bp 6 /* Flash Memory Busy bit position. */ ++ ++#define NVM_EELOAD_bm 0x02 /* EEPROM Page Buffer Active Loading bit mask. */ ++#define NVM_EELOAD_bp 1 /* EEPROM Page Buffer Active Loading bit position. */ ++ ++#define NVM_FLOAD_bm 0x01 /* Flash Page Buffer Active Loading bit mask. */ ++#define NVM_FLOAD_bp 0 /* Flash Page Buffer Active Loading bit position. */ ++ ++/* NVM.LOCKBITS bit masks and bit positions */ ++#define NVM_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* ADC - Analog/Digital Converter */ ++/* ADC_CH.CTRL bit masks and bit positions */ ++#define ADC_CH_START_bm 0x80 /* Channel Start Conversion bit mask. */ ++#define ADC_CH_START_bp 7 /* Channel Start Conversion bit position. */ ++ ++#define ADC_CH_GAIN_gm 0x1C /* Gain Factor group mask. */ ++#define ADC_CH_GAIN_gp 2 /* Gain Factor group position. */ ++#define ADC_CH_GAIN0_bm (1<<2) /* Gain Factor bit 0 mask. */ ++#define ADC_CH_GAIN0_bp 2 /* Gain Factor bit 0 position. */ ++#define ADC_CH_GAIN1_bm (1<<3) /* Gain Factor bit 1 mask. */ ++#define ADC_CH_GAIN1_bp 3 /* Gain Factor bit 1 position. */ ++#define ADC_CH_GAIN2_bm (1<<4) /* Gain Factor bit 2 mask. */ ++#define ADC_CH_GAIN2_bp 4 /* Gain Factor bit 2 position. */ ++ ++#define ADC_CH_INPUTMODE_gm 0x03 /* Input Mode Select group mask. */ ++#define ADC_CH_INPUTMODE_gp 0 /* Input Mode Select group position. */ ++#define ADC_CH_INPUTMODE0_bm (1<<0) /* Input Mode Select bit 0 mask. */ ++#define ADC_CH_INPUTMODE0_bp 0 /* Input Mode Select bit 0 position. */ ++#define ADC_CH_INPUTMODE1_bm (1<<1) /* Input Mode Select bit 1 mask. */ ++#define ADC_CH_INPUTMODE1_bp 1 /* Input Mode Select bit 1 position. */ ++ ++/* ADC_CH.MUXCTRL bit masks and bit positions */ ++#define ADC_CH_MUXPOS_gm 0x78 /* MUX selection on Positive ADC Input group mask. */ ++#define ADC_CH_MUXPOS_gp 3 /* MUX selection on Positive ADC Input group position. */ ++#define ADC_CH_MUXPOS0_bm (1<<3) /* MUX selection on Positive ADC Input bit 0 mask. */ ++#define ADC_CH_MUXPOS0_bp 3 /* MUX selection on Positive ADC Input bit 0 position. */ ++#define ADC_CH_MUXPOS1_bm (1<<4) /* MUX selection on Positive ADC Input bit 1 mask. */ ++#define ADC_CH_MUXPOS1_bp 4 /* MUX selection on Positive ADC Input bit 1 position. */ ++#define ADC_CH_MUXPOS2_bm (1<<5) /* MUX selection on Positive ADC Input bit 2 mask. */ ++#define ADC_CH_MUXPOS2_bp 5 /* MUX selection on Positive ADC Input bit 2 position. */ ++#define ADC_CH_MUXPOS3_bm (1<<6) /* MUX selection on Positive ADC Input bit 3 mask. */ ++#define ADC_CH_MUXPOS3_bp 6 /* MUX selection on Positive ADC Input bit 3 position. */ ++ ++#define ADC_CH_MUXINT_gm 0x78 /* MUX selection on Internal ADC Input group mask. */ ++#define ADC_CH_MUXINT_gp 3 /* MUX selection on Internal ADC Input group position. */ ++#define ADC_CH_MUXINT0_bm (1<<3) /* MUX selection on Internal ADC Input bit 0 mask. */ ++#define ADC_CH_MUXINT0_bp 3 /* MUX selection on Internal ADC Input bit 0 position. */ ++#define ADC_CH_MUXINT1_bm (1<<4) /* MUX selection on Internal ADC Input bit 1 mask. */ ++#define ADC_CH_MUXINT1_bp 4 /* MUX selection on Internal ADC Input bit 1 position. */ ++#define ADC_CH_MUXINT2_bm (1<<5) /* MUX selection on Internal ADC Input bit 2 mask. */ ++#define ADC_CH_MUXINT2_bp 5 /* MUX selection on Internal ADC Input bit 2 position. */ ++#define ADC_CH_MUXINT3_bm (1<<6) /* MUX selection on Internal ADC Input bit 3 mask. */ ++#define ADC_CH_MUXINT3_bp 6 /* MUX selection on Internal ADC Input bit 3 position. */ ++ ++#define ADC_CH_MUXNEG_gm 0x03 /* MUX selection on Negative ADC Input group mask. */ ++#define ADC_CH_MUXNEG_gp 0 /* MUX selection on Negative ADC Input group position. */ ++#define ADC_CH_MUXNEG0_bm (1<<0) /* MUX selection on Negative ADC Input bit 0 mask. */ ++#define ADC_CH_MUXNEG0_bp 0 /* MUX selection on Negative ADC Input bit 0 position. */ ++#define ADC_CH_MUXNEG1_bm (1<<1) /* MUX selection on Negative ADC Input bit 1 mask. */ ++#define ADC_CH_MUXNEG1_bp 1 /* MUX selection on Negative ADC Input bit 1 position. */ ++ ++#define ADC_CH_MUXNEGL_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group mask. */ ++#define ADC_CH_MUXNEGL_gp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins group position. */ ++#define ADC_CH_MUXNEGL0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 mask. */ ++#define ADC_CH_MUXNEGL0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 0 position. */ ++#define ADC_CH_MUXNEGL1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 mask. */ ++#define ADC_CH_MUXNEGL1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 LSB pins bit 1 position. */ ++ ++#define ADC_CH_MUXNEGH_gm 0x03 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group mask. */ ++#define ADC_CH_MUXNEGH_gp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins group position. */ ++#define ADC_CH_MUXNEGH0_bm (1<<0) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 mask. */ ++#define ADC_CH_MUXNEGH0_bp 0 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 0 position. */ ++#define ADC_CH_MUXNEGH1_bm (1<<1) /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 mask. */ ++#define ADC_CH_MUXNEGH1_bp 1 /* MUX selection on Negative ADC Input Gain on 4 MSB pins bit 1 position. */ ++ ++/* ADC_CH.INTCTRL bit masks and bit positions */ ++#define ADC_CH_INTMODE_gm 0x0C /* Interrupt Mode group mask. */ ++#define ADC_CH_INTMODE_gp 2 /* Interrupt Mode group position. */ ++#define ADC_CH_INTMODE0_bm (1<<2) /* Interrupt Mode bit 0 mask. */ ++#define ADC_CH_INTMODE0_bp 2 /* Interrupt Mode bit 0 position. */ ++#define ADC_CH_INTMODE1_bm (1<<3) /* Interrupt Mode bit 1 mask. */ ++#define ADC_CH_INTMODE1_bp 3 /* Interrupt Mode bit 1 position. */ ++ ++#define ADC_CH_INTLVL_gm 0x03 /* Interrupt Level group mask. */ ++#define ADC_CH_INTLVL_gp 0 /* Interrupt Level group position. */ ++#define ADC_CH_INTLVL0_bm (1<<0) /* Interrupt Level bit 0 mask. */ ++#define ADC_CH_INTLVL0_bp 0 /* Interrupt Level bit 0 position. */ ++#define ADC_CH_INTLVL1_bm (1<<1) /* Interrupt Level bit 1 mask. */ ++#define ADC_CH_INTLVL1_bp 1 /* Interrupt Level bit 1 position. */ ++ ++/* ADC_CH.INTFLAGS bit masks and bit positions */ ++#define ADC_CH_IF_bm 0x01 /* Channel Interrupt Flag bit mask. */ ++#define ADC_CH_IF_bp 0 /* Channel Interrupt Flag bit position. */ ++ ++/* ADC_CH.SCAN bit masks and bit positions */ ++#define ADC_CH_INPUTOFFSET_gm 0xF0 /* Positive MUX Setting Offset group mask. */ ++#define ADC_CH_INPUTOFFSET_gp 4 /* Positive MUX Setting Offset group position. */ ++#define ADC_CH_INPUTOFFSET0_bm (1<<4) /* Positive MUX Setting Offset bit 0 mask. */ ++#define ADC_CH_INPUTOFFSET0_bp 4 /* Positive MUX Setting Offset bit 0 position. */ ++#define ADC_CH_INPUTOFFSET1_bm (1<<5) /* Positive MUX Setting Offset bit 1 mask. */ ++#define ADC_CH_INPUTOFFSET1_bp 5 /* Positive MUX Setting Offset bit 1 position. */ ++#define ADC_CH_INPUTOFFSET2_bm (1<<6) /* Positive MUX Setting Offset bit 2 mask. */ ++#define ADC_CH_INPUTOFFSET2_bp 6 /* Positive MUX Setting Offset bit 2 position. */ ++#define ADC_CH_INPUTOFFSET3_bm (1<<7) /* Positive MUX Setting Offset bit 3 mask. */ ++#define ADC_CH_INPUTOFFSET3_bp 7 /* Positive MUX Setting Offset bit 3 position. */ ++ ++#define ADC_CH_INPUTSCAN_gm 0x0F /* Number of Channels Included in Scan group mask. */ ++#define ADC_CH_INPUTSCAN_gp 0 /* Number of Channels Included in Scan group position. */ ++#define ADC_CH_INPUTSCAN0_bm (1<<0) /* Number of Channels Included in Scan bit 0 mask. */ ++#define ADC_CH_INPUTSCAN0_bp 0 /* Number of Channels Included in Scan bit 0 position. */ ++#define ADC_CH_INPUTSCAN1_bm (1<<1) /* Number of Channels Included in Scan bit 1 mask. */ ++#define ADC_CH_INPUTSCAN1_bp 1 /* Number of Channels Included in Scan bit 1 position. */ ++#define ADC_CH_INPUTSCAN2_bm (1<<2) /* Number of Channels Included in Scan bit 2 mask. */ ++#define ADC_CH_INPUTSCAN2_bp 2 /* Number of Channels Included in Scan bit 2 position. */ ++#define ADC_CH_INPUTSCAN3_bm (1<<3) /* Number of Channels Included in Scan bit 3 mask. */ ++#define ADC_CH_INPUTSCAN3_bp 3 /* Number of Channels Included in Scan bit 3 position. */ ++ ++/* ADC_CH.CORRCTRL bit masks and bit positions */ ++#define ADC_CH_CORREN_bm 0x01 /* Correction Enable bit mask. */ ++#define ADC_CH_CORREN_bp 0 /* Correction Enable bit position. */ ++ ++/* ADC_CH.OFFSETCORR1 bit masks and bit positions */ ++#define ADC_CH_OFFSETCORR_gm 0x0F /* Offset Correction Byte 1 group mask. */ ++#define ADC_CH_OFFSETCORR_gp 0 /* Offset Correction Byte 1 group position. */ ++#define ADC_CH_OFFSETCORR0_bm (1<<0) /* Offset Correction Byte 1 bit 0 mask. */ ++#define ADC_CH_OFFSETCORR0_bp 0 /* Offset Correction Byte 1 bit 0 position. */ ++#define ADC_CH_OFFSETCORR1_bm (1<<1) /* Offset Correction Byte 1 bit 1 mask. */ ++#define ADC_CH_OFFSETCORR1_bp 1 /* Offset Correction Byte 1 bit 1 position. */ ++#define ADC_CH_OFFSETCORR2_bm (1<<2) /* Offset Correction Byte 1 bit 2 mask. */ ++#define ADC_CH_OFFSETCORR2_bp 2 /* Offset Correction Byte 1 bit 2 position. */ ++#define ADC_CH_OFFSETCORR3_bm (1<<3) /* Offset Correction Byte 1 bit 3 mask. */ ++#define ADC_CH_OFFSETCORR3_bp 3 /* Offset Correction Byte 1 bit 3 position. */ ++ ++/* ADC_CH.GAINCORR1 bit masks and bit positions */ ++#define ADC_CH_GAINCORR_gm 0x0F /* Gain Correction Byte 1 group mask. */ ++#define ADC_CH_GAINCORR_gp 0 /* Gain Correction Byte 1 group position. */ ++#define ADC_CH_GAINCORR0_bm (1<<0) /* Gain Correction Byte 1 bit 0 mask. */ ++#define ADC_CH_GAINCORR0_bp 0 /* Gain Correction Byte 1 bit 0 position. */ ++#define ADC_CH_GAINCORR1_bm (1<<1) /* Gain Correction Byte 1 bit 1 mask. */ ++#define ADC_CH_GAINCORR1_bp 1 /* Gain Correction Byte 1 bit 1 position. */ ++#define ADC_CH_GAINCORR2_bm (1<<2) /* Gain Correction Byte 1 bit 2 mask. */ ++#define ADC_CH_GAINCORR2_bp 2 /* Gain Correction Byte 1 bit 2 position. */ ++#define ADC_CH_GAINCORR3_bm (1<<3) /* Gain Correction Byte 1 bit 3 mask. */ ++#define ADC_CH_GAINCORR3_bp 3 /* Gain Correction Byte 1 bit 3 position. */ ++ ++/* ADC_CH.AVGCTRL bit masks and bit positions */ ++#define ADC_CH_RIGHTSHIFT_gm 0x70 /* Right Shift group mask. */ ++#define ADC_CH_RIGHTSHIFT_gp 4 /* Right Shift group position. */ ++#define ADC_CH_RIGHTSHIFT0_bm (1<<4) /* Right Shift bit 0 mask. */ ++#define ADC_CH_RIGHTSHIFT0_bp 4 /* Right Shift bit 0 position. */ ++#define ADC_CH_RIGHTSHIFT1_bm (1<<5) /* Right Shift bit 1 mask. */ ++#define ADC_CH_RIGHTSHIFT1_bp 5 /* Right Shift bit 1 position. */ ++#define ADC_CH_RIGHTSHIFT2_bm (1<<6) /* Right Shift bit 2 mask. */ ++#define ADC_CH_RIGHTSHIFT2_bp 6 /* Right Shift bit 2 position. */ ++ ++#define ADC_CH_SAMPNUM_gm 0x0F /* Averaged Number of Samples group mask. */ ++#define ADC_CH_SAMPNUM_gp 0 /* Averaged Number of Samples group position. */ ++#define ADC_CH_SAMPNUM0_bm (1<<0) /* Averaged Number of Samples bit 0 mask. */ ++#define ADC_CH_SAMPNUM0_bp 0 /* Averaged Number of Samples bit 0 position. */ ++#define ADC_CH_SAMPNUM1_bm (1<<1) /* Averaged Number of Samples bit 1 mask. */ ++#define ADC_CH_SAMPNUM1_bp 1 /* Averaged Number of Samples bit 1 position. */ ++#define ADC_CH_SAMPNUM2_bm (1<<2) /* Averaged Number of Samples bit 2 mask. */ ++#define ADC_CH_SAMPNUM2_bp 2 /* Averaged Number of Samples bit 2 position. */ ++#define ADC_CH_SAMPNUM3_bm (1<<3) /* Averaged Number of Samples bit 3 mask. */ ++#define ADC_CH_SAMPNUM3_bp 3 /* Averaged Number of Samples bit 3 position. */ ++ ++/* ADC.CTRLA bit masks and bit positions */ ++#define ADC_START_bm 0x04 /* Start Conversion bit mask. */ ++#define ADC_START_bp 2 /* Start Conversion bit position. */ ++ ++#define ADC_FLUSH_bm 0x02 /* ADC Flush bit mask. */ ++#define ADC_FLUSH_bp 1 /* ADC Flush bit position. */ ++ ++#define ADC_ENABLE_bm 0x01 /* Enable ADC bit mask. */ ++#define ADC_ENABLE_bp 0 /* Enable ADC bit position. */ ++ ++/* ADC.CTRLB bit masks and bit positions */ ++#define ADC_CURRLIMIT_gm 0x60 /* Current Limitation group mask. */ ++#define ADC_CURRLIMIT_gp 5 /* Current Limitation group position. */ ++#define ADC_CURRLIMIT0_bm (1<<5) /* Current Limitation bit 0 mask. */ ++#define ADC_CURRLIMIT0_bp 5 /* Current Limitation bit 0 position. */ ++#define ADC_CURRLIMIT1_bm (1<<6) /* Current Limitation bit 1 mask. */ ++#define ADC_CURRLIMIT1_bp 6 /* Current Limitation bit 1 position. */ ++ ++#define ADC_CONMODE_bm 0x10 /* Conversion Mode bit mask. */ ++#define ADC_CONMODE_bp 4 /* Conversion Mode bit position. */ ++ ++#define ADC_FREERUN_bm 0x08 /* Free Running Mode Enable bit mask. */ ++#define ADC_FREERUN_bp 3 /* Free Running Mode Enable bit position. */ ++ ++#define ADC_RESOLUTION_gm 0x06 /* Result Resolution group mask. */ ++#define ADC_RESOLUTION_gp 1 /* Result Resolution group position. */ ++#define ADC_RESOLUTION0_bm (1<<1) /* Result Resolution bit 0 mask. */ ++#define ADC_RESOLUTION0_bp 1 /* Result Resolution bit 0 position. */ ++#define ADC_RESOLUTION1_bm (1<<2) /* Result Resolution bit 1 mask. */ ++#define ADC_RESOLUTION1_bp 2 /* Result Resolution bit 1 position. */ ++ ++/* ADC.REFCTRL bit masks and bit positions */ ++#define ADC_REFSEL_gm 0x70 /* Reference Selection group mask. */ ++#define ADC_REFSEL_gp 4 /* Reference Selection group position. */ ++#define ADC_REFSEL0_bm (1<<4) /* Reference Selection bit 0 mask. */ ++#define ADC_REFSEL0_bp 4 /* Reference Selection bit 0 position. */ ++#define ADC_REFSEL1_bm (1<<5) /* Reference Selection bit 1 mask. */ ++#define ADC_REFSEL1_bp 5 /* Reference Selection bit 1 position. */ ++#define ADC_REFSEL2_bm (1<<6) /* Reference Selection bit 2 mask. */ ++#define ADC_REFSEL2_bp 6 /* Reference Selection bit 2 position. */ ++ ++#define ADC_BANDGAP_bm 0x02 /* Bandgap enable bit mask. */ ++#define ADC_BANDGAP_bp 1 /* Bandgap enable bit position. */ ++ ++#define ADC_TEMPREF_bm 0x01 /* Temperature Reference Enable bit mask. */ ++#define ADC_TEMPREF_bp 0 /* Temperature Reference Enable bit position. */ ++ ++/* ADC.EVCTRL bit masks and bit positions */ ++#define ADC_EVSEL_gm 0x38 /* Event Input Select group mask. */ ++#define ADC_EVSEL_gp 3 /* Event Input Select group position. */ ++#define ADC_EVSEL0_bm (1<<3) /* Event Input Select bit 0 mask. */ ++#define ADC_EVSEL0_bp 3 /* Event Input Select bit 0 position. */ ++#define ADC_EVSEL1_bm (1<<4) /* Event Input Select bit 1 mask. */ ++#define ADC_EVSEL1_bp 4 /* Event Input Select bit 1 position. */ ++#define ADC_EVSEL2_bm (1<<5) /* Event Input Select bit 2 mask. */ ++#define ADC_EVSEL2_bp 5 /* Event Input Select bit 2 position. */ ++ ++#define ADC_EVACT_gm 0x07 /* Event Action Select group mask. */ ++#define ADC_EVACT_gp 0 /* Event Action Select group position. */ ++#define ADC_EVACT0_bm (1<<0) /* Event Action Select bit 0 mask. */ ++#define ADC_EVACT0_bp 0 /* Event Action Select bit 0 position. */ ++#define ADC_EVACT1_bm (1<<1) /* Event Action Select bit 1 mask. */ ++#define ADC_EVACT1_bp 1 /* Event Action Select bit 1 position. */ ++#define ADC_EVACT2_bm (1<<2) /* Event Action Select bit 2 mask. */ ++#define ADC_EVACT2_bp 2 /* Event Action Select bit 2 position. */ ++ ++/* ADC.PRESCALER bit masks and bit positions */ ++#define ADC_PRESCALER_gm 0x07 /* Clock Prescaler Selection group mask. */ ++#define ADC_PRESCALER_gp 0 /* Clock Prescaler Selection group position. */ ++#define ADC_PRESCALER0_bm (1<<0) /* Clock Prescaler Selection bit 0 mask. */ ++#define ADC_PRESCALER0_bp 0 /* Clock Prescaler Selection bit 0 position. */ ++#define ADC_PRESCALER1_bm (1<<1) /* Clock Prescaler Selection bit 1 mask. */ ++#define ADC_PRESCALER1_bp 1 /* Clock Prescaler Selection bit 1 position. */ ++#define ADC_PRESCALER2_bm (1<<2) /* Clock Prescaler Selection bit 2 mask. */ ++#define ADC_PRESCALER2_bp 2 /* Clock Prescaler Selection bit 2 position. */ ++ ++/* ADC.INTFLAGS bit masks and bit positions */ ++#define ADC_CH0IF_bm 0x01 /* Channel 0 Interrupt Flag bit mask. */ ++#define ADC_CH0IF_bp 0 /* Channel 0 Interrupt Flag bit position. */ ++ ++/* ADC.SAMPCTRL bit masks and bit positions */ ++#define ADC_SAMPVAL_gm 0x3F /* Sampling time control register group mask. */ ++#define ADC_SAMPVAL_gp 0 /* Sampling time control register group position. */ ++#define ADC_SAMPVAL0_bm (1<<0) /* Sampling time control register bit 0 mask. */ ++#define ADC_SAMPVAL0_bp 0 /* Sampling time control register bit 0 position. */ ++#define ADC_SAMPVAL1_bm (1<<1) /* Sampling time control register bit 1 mask. */ ++#define ADC_SAMPVAL1_bp 1 /* Sampling time control register bit 1 position. */ ++#define ADC_SAMPVAL2_bm (1<<2) /* Sampling time control register bit 2 mask. */ ++#define ADC_SAMPVAL2_bp 2 /* Sampling time control register bit 2 position. */ ++#define ADC_SAMPVAL3_bm (1<<3) /* Sampling time control register bit 3 mask. */ ++#define ADC_SAMPVAL3_bp 3 /* Sampling time control register bit 3 position. */ ++#define ADC_SAMPVAL4_bm (1<<4) /* Sampling time control register bit 4 mask. */ ++#define ADC_SAMPVAL4_bp 4 /* Sampling time control register bit 4 position. */ ++#define ADC_SAMPVAL5_bm (1<<5) /* Sampling time control register bit 5 mask. */ ++#define ADC_SAMPVAL5_bp 5 /* Sampling time control register bit 5 position. */ ++ ++/* DAC - Digital/Analog Converter */ ++/* DAC.CTRLA bit masks and bit positions */ ++#define DAC_IDOEN_bm 0x10 /* Internal Output Enable bit mask. */ ++#define DAC_IDOEN_bp 4 /* Internal Output Enable bit position. */ ++ ++#define DAC_CH1EN_bm 0x08 /* Channel 1 Output Enable bit mask. */ ++#define DAC_CH1EN_bp 3 /* Channel 1 Output Enable bit position. */ ++ ++#define DAC_CH0EN_bm 0x04 /* Channel 0 Output Enable bit mask. */ ++#define DAC_CH0EN_bp 2 /* Channel 0 Output Enable bit position. */ ++ ++#define DAC_LPMODE_bm 0x02 /* Low Power Mode bit mask. */ ++#define DAC_LPMODE_bp 1 /* Low Power Mode bit position. */ ++ ++#define DAC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define DAC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* DAC.CTRLB bit masks and bit positions */ ++#define DAC_CHSEL_gm 0x60 /* Channel Select group mask. */ ++#define DAC_CHSEL_gp 5 /* Channel Select group position. */ ++#define DAC_CHSEL0_bm (1<<5) /* Channel Select bit 0 mask. */ ++#define DAC_CHSEL0_bp 5 /* Channel Select bit 0 position. */ ++#define DAC_CHSEL1_bm (1<<6) /* Channel Select bit 1 mask. */ ++#define DAC_CHSEL1_bp 6 /* Channel Select bit 1 position. */ ++ ++#define DAC_CH1TRIG_bm 0x02 /* Channel 1 Event Trig Enable bit mask. */ ++#define DAC_CH1TRIG_bp 1 /* Channel 1 Event Trig Enable bit position. */ ++ ++#define DAC_CH0TRIG_bm 0x01 /* Channel 0 Event Trig Enable bit mask. */ ++#define DAC_CH0TRIG_bp 0 /* Channel 0 Event Trig Enable bit position. */ ++ ++/* DAC.CTRLC bit masks and bit positions */ ++#define DAC_REFSEL_gm 0x18 /* Reference Select group mask. */ ++#define DAC_REFSEL_gp 3 /* Reference Select group position. */ ++#define DAC_REFSEL0_bm (1<<3) /* Reference Select bit 0 mask. */ ++#define DAC_REFSEL0_bp 3 /* Reference Select bit 0 position. */ ++#define DAC_REFSEL1_bm (1<<4) /* Reference Select bit 1 mask. */ ++#define DAC_REFSEL1_bp 4 /* Reference Select bit 1 position. */ ++ ++#define DAC_LEFTADJ_bm 0x01 /* Left-adjust Result bit mask. */ ++#define DAC_LEFTADJ_bp 0 /* Left-adjust Result bit position. */ ++ ++/* DAC.EVCTRL bit masks and bit positions */ ++#define DAC_EVSPLIT_bm 0x08 /* Separate Event Channel Input for Channel 1 bit mask. */ ++#define DAC_EVSPLIT_bp 3 /* Separate Event Channel Input for Channel 1 bit position. */ ++ ++#define DAC_EVSEL_gm 0x07 /* Event Input Selection group mask. */ ++#define DAC_EVSEL_gp 0 /* Event Input Selection group position. */ ++#define DAC_EVSEL0_bm (1<<0) /* Event Input Selection bit 0 mask. */ ++#define DAC_EVSEL0_bp 0 /* Event Input Selection bit 0 position. */ ++#define DAC_EVSEL1_bm (1<<1) /* Event Input Selection bit 1 mask. */ ++#define DAC_EVSEL1_bp 1 /* Event Input Selection bit 1 position. */ ++#define DAC_EVSEL2_bm (1<<2) /* Event Input Selection bit 2 mask. */ ++#define DAC_EVSEL2_bp 2 /* Event Input Selection bit 2 position. */ ++ ++/* DAC.STATUS bit masks and bit positions */ ++#define DAC_CH1DRE_bm 0x02 /* Channel 1 Data Register Empty bit mask. */ ++#define DAC_CH1DRE_bp 1 /* Channel 1 Data Register Empty bit position. */ ++ ++#define DAC_CH0DRE_bm 0x01 /* Channel 0 Data Register Empty bit mask. */ ++#define DAC_CH0DRE_bp 0 /* Channel 0 Data Register Empty bit position. */ ++ ++/* DAC.CH0GAINCAL bit masks and bit positions */ ++#define DAC_CH0GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH0GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH0GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH0GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH0GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH0GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH0GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH0GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH0GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH0GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH0GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH0GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH0GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH0GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH0GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH0GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH0OFFSETCAL bit masks and bit positions */ ++#define DAC_CH0OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH0OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH0OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH0OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH0OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH0OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH0OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH0OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH0OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH0OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH0OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH0OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH0OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH0OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH0OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH0OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* DAC.CH1GAINCAL bit masks and bit positions */ ++#define DAC_CH1GAINCAL_gm 0x7F /* Gain Calibration group mask. */ ++#define DAC_CH1GAINCAL_gp 0 /* Gain Calibration group position. */ ++#define DAC_CH1GAINCAL0_bm (1<<0) /* Gain Calibration bit 0 mask. */ ++#define DAC_CH1GAINCAL0_bp 0 /* Gain Calibration bit 0 position. */ ++#define DAC_CH1GAINCAL1_bm (1<<1) /* Gain Calibration bit 1 mask. */ ++#define DAC_CH1GAINCAL1_bp 1 /* Gain Calibration bit 1 position. */ ++#define DAC_CH1GAINCAL2_bm (1<<2) /* Gain Calibration bit 2 mask. */ ++#define DAC_CH1GAINCAL2_bp 2 /* Gain Calibration bit 2 position. */ ++#define DAC_CH1GAINCAL3_bm (1<<3) /* Gain Calibration bit 3 mask. */ ++#define DAC_CH1GAINCAL3_bp 3 /* Gain Calibration bit 3 position. */ ++#define DAC_CH1GAINCAL4_bm (1<<4) /* Gain Calibration bit 4 mask. */ ++#define DAC_CH1GAINCAL4_bp 4 /* Gain Calibration bit 4 position. */ ++#define DAC_CH1GAINCAL5_bm (1<<5) /* Gain Calibration bit 5 mask. */ ++#define DAC_CH1GAINCAL5_bp 5 /* Gain Calibration bit 5 position. */ ++#define DAC_CH1GAINCAL6_bm (1<<6) /* Gain Calibration bit 6 mask. */ ++#define DAC_CH1GAINCAL6_bp 6 /* Gain Calibration bit 6 position. */ ++ ++/* DAC.CH1OFFSETCAL bit masks and bit positions */ ++#define DAC_CH1OFFSETCAL_gm 0x7F /* Offset Calibration group mask. */ ++#define DAC_CH1OFFSETCAL_gp 0 /* Offset Calibration group position. */ ++#define DAC_CH1OFFSETCAL0_bm (1<<0) /* Offset Calibration bit 0 mask. */ ++#define DAC_CH1OFFSETCAL0_bp 0 /* Offset Calibration bit 0 position. */ ++#define DAC_CH1OFFSETCAL1_bm (1<<1) /* Offset Calibration bit 1 mask. */ ++#define DAC_CH1OFFSETCAL1_bp 1 /* Offset Calibration bit 1 position. */ ++#define DAC_CH1OFFSETCAL2_bm (1<<2) /* Offset Calibration bit 2 mask. */ ++#define DAC_CH1OFFSETCAL2_bp 2 /* Offset Calibration bit 2 position. */ ++#define DAC_CH1OFFSETCAL3_bm (1<<3) /* Offset Calibration bit 3 mask. */ ++#define DAC_CH1OFFSETCAL3_bp 3 /* Offset Calibration bit 3 position. */ ++#define DAC_CH1OFFSETCAL4_bm (1<<4) /* Offset Calibration bit 4 mask. */ ++#define DAC_CH1OFFSETCAL4_bp 4 /* Offset Calibration bit 4 position. */ ++#define DAC_CH1OFFSETCAL5_bm (1<<5) /* Offset Calibration bit 5 mask. */ ++#define DAC_CH1OFFSETCAL5_bp 5 /* Offset Calibration bit 5 position. */ ++#define DAC_CH1OFFSETCAL6_bm (1<<6) /* Offset Calibration bit 6 mask. */ ++#define DAC_CH1OFFSETCAL6_bp 6 /* Offset Calibration bit 6 position. */ ++ ++/* AC - Analog Comparator */ ++/* AC.AC0CTRL bit masks and bit positions */ ++#define AC_INTMODE_gm 0xC0 /* Interrupt Mode group mask. */ ++#define AC_INTMODE_gp 6 /* Interrupt Mode group position. */ ++#define AC_INTMODE0_bm (1<<6) /* Interrupt Mode bit 0 mask. */ ++#define AC_INTMODE0_bp 6 /* Interrupt Mode bit 0 position. */ ++#define AC_INTMODE1_bm (1<<7) /* Interrupt Mode bit 1 mask. */ ++#define AC_INTMODE1_bp 7 /* Interrupt Mode bit 1 position. */ ++ ++#define AC_INTLVL_gm 0x30 /* Interrupt Level group mask. */ ++#define AC_INTLVL_gp 4 /* Interrupt Level group position. */ ++#define AC_INTLVL0_bm (1<<4) /* Interrupt Level bit 0 mask. */ ++#define AC_INTLVL0_bp 4 /* Interrupt Level bit 0 position. */ ++#define AC_INTLVL1_bm (1<<5) /* Interrupt Level bit 1 mask. */ ++#define AC_INTLVL1_bp 5 /* Interrupt Level bit 1 position. */ ++ ++#define AC_HYSMODE_gm 0x06 /* Hysteresis Mode group mask. */ ++#define AC_HYSMODE_gp 1 /* Hysteresis Mode group position. */ ++#define AC_HYSMODE0_bm (1<<1) /* Hysteresis Mode bit 0 mask. */ ++#define AC_HYSMODE0_bp 1 /* Hysteresis Mode bit 0 position. */ ++#define AC_HYSMODE1_bm (1<<2) /* Hysteresis Mode bit 1 mask. */ ++#define AC_HYSMODE1_bp 2 /* Hysteresis Mode bit 1 position. */ ++ ++#define AC_ENABLE_bm 0x01 /* Enable bit mask. */ ++#define AC_ENABLE_bp 0 /* Enable bit position. */ ++ ++/* AC.AC1CTRL bit masks and bit positions */ ++/* AC_INTMODE Predefined. */ ++/* AC_INTMODE Predefined. */ ++ ++/* AC_INTLVL Predefined. */ ++/* AC_INTLVL Predefined. */ ++ ++/* AC_HYSMODE Predefined. */ ++/* AC_HYSMODE Predefined. */ ++ ++/* AC_ENABLE Predefined. */ ++/* AC_ENABLE Predefined. */ ++ ++/* AC.AC0MUXCTRL bit masks and bit positions */ ++#define AC_MUXPOS_gm 0x38 /* MUX Positive Input group mask. */ ++#define AC_MUXPOS_gp 3 /* MUX Positive Input group position. */ ++#define AC_MUXPOS0_bm (1<<3) /* MUX Positive Input bit 0 mask. */ ++#define AC_MUXPOS0_bp 3 /* MUX Positive Input bit 0 position. */ ++#define AC_MUXPOS1_bm (1<<4) /* MUX Positive Input bit 1 mask. */ ++#define AC_MUXPOS1_bp 4 /* MUX Positive Input bit 1 position. */ ++#define AC_MUXPOS2_bm (1<<5) /* MUX Positive Input bit 2 mask. */ ++#define AC_MUXPOS2_bp 5 /* MUX Positive Input bit 2 position. */ ++ ++#define AC_MUXNEG_gm 0x07 /* MUX Negative Input group mask. */ ++#define AC_MUXNEG_gp 0 /* MUX Negative Input group position. */ ++#define AC_MUXNEG0_bm (1<<0) /* MUX Negative Input bit 0 mask. */ ++#define AC_MUXNEG0_bp 0 /* MUX Negative Input bit 0 position. */ ++#define AC_MUXNEG1_bm (1<<1) /* MUX Negative Input bit 1 mask. */ ++#define AC_MUXNEG1_bp 1 /* MUX Negative Input bit 1 position. */ ++#define AC_MUXNEG2_bm (1<<2) /* MUX Negative Input bit 2 mask. */ ++#define AC_MUXNEG2_bp 2 /* MUX Negative Input bit 2 position. */ ++ ++/* AC.AC1MUXCTRL bit masks and bit positions */ ++/* AC_MUXPOS Predefined. */ ++/* AC_MUXPOS Predefined. */ ++ ++/* AC_MUXNEG Predefined. */ ++/* AC_MUXNEG Predefined. */ ++ ++/* AC.CTRLA bit masks and bit positions */ ++#define AC_AC1INVEN_bm 0x08 /* Analog Comparator 1 Output Invert Enable bit mask. */ ++#define AC_AC1INVEN_bp 3 /* Analog Comparator 1 Output Invert Enable bit position. */ ++ ++#define AC_AC0INVEN_bm 0x04 /* Analog Comparator 0 Output Invert Enable bit mask. */ ++#define AC_AC0INVEN_bp 2 /* Analog Comparator 0 Output Invert Enable bit position. */ ++ ++#define AC_AC1OUT_bm 0x02 /* Analog Comparator 1 Output Enable bit mask. */ ++#define AC_AC1OUT_bp 1 /* Analog Comparator 1 Output Enable bit position. */ ++ ++#define AC_AC0OUT_bm 0x01 /* Analog Comparator 0 Output Enable bit mask. */ ++#define AC_AC0OUT_bp 0 /* Analog Comparator 0 Output Enable bit position. */ ++ ++/* AC.CTRLB bit masks and bit positions */ ++#define AC_SCALEFAC_gm 0x3F /* VCC Voltage Scaler Factor group mask. */ ++#define AC_SCALEFAC_gp 0 /* VCC Voltage Scaler Factor group position. */ ++#define AC_SCALEFAC0_bm (1<<0) /* VCC Voltage Scaler Factor bit 0 mask. */ ++#define AC_SCALEFAC0_bp 0 /* VCC Voltage Scaler Factor bit 0 position. */ ++#define AC_SCALEFAC1_bm (1<<1) /* VCC Voltage Scaler Factor bit 1 mask. */ ++#define AC_SCALEFAC1_bp 1 /* VCC Voltage Scaler Factor bit 1 position. */ ++#define AC_SCALEFAC2_bm (1<<2) /* VCC Voltage Scaler Factor bit 2 mask. */ ++#define AC_SCALEFAC2_bp 2 /* VCC Voltage Scaler Factor bit 2 position. */ ++#define AC_SCALEFAC3_bm (1<<3) /* VCC Voltage Scaler Factor bit 3 mask. */ ++#define AC_SCALEFAC3_bp 3 /* VCC Voltage Scaler Factor bit 3 position. */ ++#define AC_SCALEFAC4_bm (1<<4) /* VCC Voltage Scaler Factor bit 4 mask. */ ++#define AC_SCALEFAC4_bp 4 /* VCC Voltage Scaler Factor bit 4 position. */ ++#define AC_SCALEFAC5_bm (1<<5) /* VCC Voltage Scaler Factor bit 5 mask. */ ++#define AC_SCALEFAC5_bp 5 /* VCC Voltage Scaler Factor bit 5 position. */ ++ ++/* AC.WINCTRL bit masks and bit positions */ ++#define AC_WEN_bm 0x10 /* Window Mode Enable bit mask. */ ++#define AC_WEN_bp 4 /* Window Mode Enable bit position. */ ++ ++#define AC_WINTMODE_gm 0x0C /* Window Interrupt Mode group mask. */ ++#define AC_WINTMODE_gp 2 /* Window Interrupt Mode group position. */ ++#define AC_WINTMODE0_bm (1<<2) /* Window Interrupt Mode bit 0 mask. */ ++#define AC_WINTMODE0_bp 2 /* Window Interrupt Mode bit 0 position. */ ++#define AC_WINTMODE1_bm (1<<3) /* Window Interrupt Mode bit 1 mask. */ ++#define AC_WINTMODE1_bp 3 /* Window Interrupt Mode bit 1 position. */ ++ ++#define AC_WINTLVL_gm 0x03 /* Window Interrupt Level group mask. */ ++#define AC_WINTLVL_gp 0 /* Window Interrupt Level group position. */ ++#define AC_WINTLVL0_bm (1<<0) /* Window Interrupt Level bit 0 mask. */ ++#define AC_WINTLVL0_bp 0 /* Window Interrupt Level bit 0 position. */ ++#define AC_WINTLVL1_bm (1<<1) /* Window Interrupt Level bit 1 mask. */ ++#define AC_WINTLVL1_bp 1 /* Window Interrupt Level bit 1 position. */ ++ ++/* AC.STATUS bit masks and bit positions */ ++#define AC_WSTATE_gm 0xC0 /* Window Mode State group mask. */ ++#define AC_WSTATE_gp 6 /* Window Mode State group position. */ ++#define AC_WSTATE0_bm (1<<6) /* Window Mode State bit 0 mask. */ ++#define AC_WSTATE0_bp 6 /* Window Mode State bit 0 position. */ ++#define AC_WSTATE1_bm (1<<7) /* Window Mode State bit 1 mask. */ ++#define AC_WSTATE1_bp 7 /* Window Mode State bit 1 position. */ ++ ++#define AC_AC1STATE_bm 0x20 /* Analog Comparator 1 State bit mask. */ ++#define AC_AC1STATE_bp 5 /* Analog Comparator 1 State bit position. */ ++ ++#define AC_AC0STATE_bm 0x10 /* Analog Comparator 0 State bit mask. */ ++#define AC_AC0STATE_bp 4 /* Analog Comparator 0 State bit position. */ ++ ++#define AC_WIF_bm 0x04 /* Window Mode Interrupt Flag bit mask. */ ++#define AC_WIF_bp 2 /* Window Mode Interrupt Flag bit position. */ ++ ++#define AC_AC1IF_bm 0x02 /* Analog Comparator 1 Interrupt Flag bit mask. */ ++#define AC_AC1IF_bp 1 /* Analog Comparator 1 Interrupt Flag bit position. */ ++ ++#define AC_AC0IF_bm 0x01 /* Analog Comparator 0 Interrupt Flag bit mask. */ ++#define AC_AC0IF_bp 0 /* Analog Comparator 0 Interrupt Flag bit position. */ ++ ++/* AC.CURRCTRL bit masks and bit positions */ ++#define AC_CURREN_bm 0x80 /* Current Source Enable bit mask. */ ++#define AC_CURREN_bp 7 /* Current Source Enable bit position. */ ++ ++#define AC_CURRMODE_bm 0x40 /* Current Mode bit mask. */ ++#define AC_CURRMODE_bp 6 /* Current Mode bit position. */ ++ ++#define AC_AC1CURR_bm 0x02 /* Analog Comparator 1 current source output bit mask. */ ++#define AC_AC1CURR_bp 1 /* Analog Comparator 1 current source output bit position. */ ++ ++#define AC_AC0CURR_bm 0x01 /* Analog Comparator 0 current source output bit mask. */ ++#define AC_AC0CURR_bp 0 /* Analog Comparator 0 current source output bit position. */ ++ ++/* AC.CURRCALIB bit masks and bit positions */ ++#define AC_CALIB_gm 0x0F /* Current Source Calibration group mask. */ ++#define AC_CALIB_gp 0 /* Current Source Calibration group position. */ ++#define AC_CALIB0_bm (1<<0) /* Current Source Calibration bit 0 mask. */ ++#define AC_CALIB0_bp 0 /* Current Source Calibration bit 0 position. */ ++#define AC_CALIB1_bm (1<<1) /* Current Source Calibration bit 1 mask. */ ++#define AC_CALIB1_bp 1 /* Current Source Calibration bit 1 position. */ ++#define AC_CALIB2_bm (1<<2) /* Current Source Calibration bit 2 mask. */ ++#define AC_CALIB2_bp 2 /* Current Source Calibration bit 2 position. */ ++#define AC_CALIB3_bm (1<<3) /* Current Source Calibration bit 3 mask. */ ++#define AC_CALIB3_bp 3 /* Current Source Calibration bit 3 position. */ ++ ++/* RTC - Real-Time Clounter */ ++/* RTC.CTRL bit masks and bit positions */ ++#define RTC_CORREN_bm 0x08 /* Correction Enable bit mask. */ ++#define RTC_CORREN_bp 3 /* Correction Enable bit position. */ ++ ++#define RTC_PRESCALER_gm 0x07 /* Prescaling Factor group mask. */ ++#define RTC_PRESCALER_gp 0 /* Prescaling Factor group position. */ ++#define RTC_PRESCALER0_bm (1<<0) /* Prescaling Factor bit 0 mask. */ ++#define RTC_PRESCALER0_bp 0 /* Prescaling Factor bit 0 position. */ ++#define RTC_PRESCALER1_bm (1<<1) /* Prescaling Factor bit 1 mask. */ ++#define RTC_PRESCALER1_bp 1 /* Prescaling Factor bit 1 position. */ ++#define RTC_PRESCALER2_bm (1<<2) /* Prescaling Factor bit 2 mask. */ ++#define RTC_PRESCALER2_bp 2 /* Prescaling Factor bit 2 position. */ ++ ++/* RTC.STATUS bit masks and bit positions */ ++#define RTC_SYNCBUSY_bm 0x01 /* Synchronization Busy Flag bit mask. */ ++#define RTC_SYNCBUSY_bp 0 /* Synchronization Busy Flag bit position. */ ++ ++/* RTC.INTCTRL bit masks and bit positions */ ++#define RTC_COMPINTLVL_gm 0x0C /* Compare Match Interrupt Level group mask. */ ++#define RTC_COMPINTLVL_gp 2 /* Compare Match Interrupt Level group position. */ ++#define RTC_COMPINTLVL0_bm (1<<2) /* Compare Match Interrupt Level bit 0 mask. */ ++#define RTC_COMPINTLVL0_bp 2 /* Compare Match Interrupt Level bit 0 position. */ ++#define RTC_COMPINTLVL1_bm (1<<3) /* Compare Match Interrupt Level bit 1 mask. */ ++#define RTC_COMPINTLVL1_bp 3 /* Compare Match Interrupt Level bit 1 position. */ ++ ++#define RTC_OVFINTLVL_gm 0x03 /* Overflow Interrupt Level group mask. */ ++#define RTC_OVFINTLVL_gp 0 /* Overflow Interrupt Level group position. */ ++#define RTC_OVFINTLVL0_bm (1<<0) /* Overflow Interrupt Level bit 0 mask. */ ++#define RTC_OVFINTLVL0_bp 0 /* Overflow Interrupt Level bit 0 position. */ ++#define RTC_OVFINTLVL1_bm (1<<1) /* Overflow Interrupt Level bit 1 mask. */ ++#define RTC_OVFINTLVL1_bp 1 /* Overflow Interrupt Level bit 1 position. */ ++ ++/* RTC.INTFLAGS bit masks and bit positions */ ++#define RTC_COMPIF_bm 0x02 /* Compare Match Interrupt Flag bit mask. */ ++#define RTC_COMPIF_bp 1 /* Compare Match Interrupt Flag bit position. */ ++ ++#define RTC_OVFIF_bm 0x01 /* Overflow Interrupt Flag bit mask. */ ++#define RTC_OVFIF_bp 0 /* Overflow Interrupt Flag bit position. */ ++ ++/* RTC.CALIB bit masks and bit positions */ ++#define RTC_SIGN_bm 0x80 /* Correction Sign bit mask. */ ++#define RTC_SIGN_bp 7 /* Correction Sign bit position. */ ++ ++#define RTC_ERROR_gm 0x7F /* Error Value group mask. */ ++#define RTC_ERROR_gp 0 /* Error Value group position. */ ++#define RTC_ERROR0_bm (1<<0) /* Error Value bit 0 mask. */ ++#define RTC_ERROR0_bp 0 /* Error Value bit 0 position. */ ++#define RTC_ERROR1_bm (1<<1) /* Error Value bit 1 mask. */ ++#define RTC_ERROR1_bp 1 /* Error Value bit 1 position. */ ++#define RTC_ERROR2_bm (1<<2) /* Error Value bit 2 mask. */ ++#define RTC_ERROR2_bp 2 /* Error Value bit 2 position. */ ++#define RTC_ERROR3_bm (1<<3) /* Error Value bit 3 mask. */ ++#define RTC_ERROR3_bp 3 /* Error Value bit 3 position. */ ++#define RTC_ERROR4_bm (1<<4) /* Error Value bit 4 mask. */ ++#define RTC_ERROR4_bp 4 /* Error Value bit 4 position. */ ++#define RTC_ERROR5_bm (1<<5) /* Error Value bit 5 mask. */ ++#define RTC_ERROR5_bp 5 /* Error Value bit 5 position. */ ++#define RTC_ERROR6_bm (1<<6) /* Error Value bit 6 mask. */ ++#define RTC_ERROR6_bp 6 /* Error Value bit 6 position. */ ++ ++/* XCL - XMEGA Custom Logic */ ++/* XCL.CTRLA bit masks and bit positions */ ++#define XCL_LUT0OUTEN_gm 0xC0 /* LUT0 Output Enable group mask. */ ++#define XCL_LUT0OUTEN_gp 6 /* LUT0 Output Enable group position. */ ++#define XCL_LUT0OUTEN0_bm (1<<6) /* LUT0 Output Enable bit 0 mask. */ ++#define XCL_LUT0OUTEN0_bp 6 /* LUT0 Output Enable bit 0 position. */ ++#define XCL_LUT0OUTEN1_bm (1<<7) /* LUT0 Output Enable bit 1 mask. */ ++#define XCL_LUT0OUTEN1_bp 7 /* LUT0 Output Enable bit 1 position. */ ++ ++#define XCL_PORTSEL_gm 0x30 /* Port Selection group mask. */ ++#define XCL_PORTSEL_gp 4 /* Port Selection group position. */ ++#define XCL_PORTSEL0_bm (1<<4) /* Port Selection bit 0 mask. */ ++#define XCL_PORTSEL0_bp 4 /* Port Selection bit 0 position. */ ++#define XCL_PORTSEL1_bm (1<<5) /* Port Selection bit 1 mask. */ ++#define XCL_PORTSEL1_bp 5 /* Port Selection bit 1 position. */ ++ ++#define XCL_LUTCONF_gm 0x07 /* LUT Configuration group mask. */ ++#define XCL_LUTCONF_gp 0 /* LUT Configuration group position. */ ++#define XCL_LUTCONF0_bm (1<<0) /* LUT Configuration bit 0 mask. */ ++#define XCL_LUTCONF0_bp 0 /* LUT Configuration bit 0 position. */ ++#define XCL_LUTCONF1_bm (1<<1) /* LUT Configuration bit 1 mask. */ ++#define XCL_LUTCONF1_bp 1 /* LUT Configuration bit 1 position. */ ++#define XCL_LUTCONF2_bm (1<<2) /* LUT Configuration bit 2 mask. */ ++#define XCL_LUTCONF2_bp 2 /* LUT Configuration bit 2 position. */ ++ ++/* XCL.CTRLB bit masks and bit positions */ ++#define XCL_IN3SEL_gm 0xC0 /* Input Selection 3 group mask. */ ++#define XCL_IN3SEL_gp 6 /* Input Selection 3 group position. */ ++#define XCL_IN3SEL0_bm (1<<6) /* Input Selection 3 bit 0 mask. */ ++#define XCL_IN3SEL0_bp 6 /* Input Selection 3 bit 0 position. */ ++#define XCL_IN3SEL1_bm (1<<7) /* Input Selection 3 bit 1 mask. */ ++#define XCL_IN3SEL1_bp 7 /* Input Selection 3 bit 1 position. */ ++ ++#define XCL_IN2SEL_gm 0x30 /* Input Selection 2 group mask. */ ++#define XCL_IN2SEL_gp 4 /* Input Selection 2 group position. */ ++#define XCL_IN2SEL0_bm (1<<4) /* Input Selection 2 bit 0 mask. */ ++#define XCL_IN2SEL0_bp 4 /* Input Selection 2 bit 0 position. */ ++#define XCL_IN2SEL1_bm (1<<5) /* Input Selection 2 bit 1 mask. */ ++#define XCL_IN2SEL1_bp 5 /* Input Selection 2 bit 1 position. */ ++ ++#define XCL_IN1SEL_gm 0x0C /* Input Selection 1 group mask. */ ++#define XCL_IN1SEL_gp 2 /* Input Selection 1 group position. */ ++#define XCL_IN1SEL0_bm (1<<2) /* Input Selection 1 bit 0 mask. */ ++#define XCL_IN1SEL0_bp 2 /* Input Selection 1 bit 0 position. */ ++#define XCL_IN1SEL1_bm (1<<3) /* Input Selection 1 bit 1 mask. */ ++#define XCL_IN1SEL1_bp 3 /* Input Selection 1 bit 1 position. */ ++ ++#define XCL_IN0SEL_gm 0x03 /* Input Selection 0 group mask. */ ++#define XCL_IN0SEL_gp 0 /* Input Selection 0 group position. */ ++#define XCL_IN0SEL0_bm (1<<0) /* Input Selection 0 bit 0 mask. */ ++#define XCL_IN0SEL0_bp 0 /* Input Selection 0 bit 0 position. */ ++#define XCL_IN0SEL1_bm (1<<1) /* Input Selection 0 bit 1 mask. */ ++#define XCL_IN0SEL1_bp 1 /* Input Selection 0 bit 1 position. */ ++ ++/* XCL.CTRLC bit masks and bit positions */ ++#define XCL_EVASYSEL1_bm 0x80 /* Asynchronous Event Line Selection for LUT1 bit mask. */ ++#define XCL_EVASYSEL1_bp 7 /* Asynchronous Event Line Selection for LUT1 bit position. */ ++ ++#define XCL_EVASYSEL0_bm 0x40 /* Asynchronous Event Line Selection for LUT0 bit mask. */ ++#define XCL_EVASYSEL0_bp 6 /* Asynchronous Event Line Selection for LUT0 bit position. */ ++ ++#define XCL_DLYSEL_gm 0x30 /* Delay Selection group mask. */ ++#define XCL_DLYSEL_gp 4 /* Delay Selection group position. */ ++#define XCL_DLYSEL0_bm (1<<4) /* Delay Selection bit 0 mask. */ ++#define XCL_DLYSEL0_bp 4 /* Delay Selection bit 0 position. */ ++#define XCL_DLYSEL1_bm (1<<5) /* Delay Selection bit 1 mask. */ ++#define XCL_DLYSEL1_bp 5 /* Delay Selection bit 1 position. */ ++ ++#define XCL_DLY1CONF_gm 0x0C /* Delay Configuration on LUT1 group mask. */ ++#define XCL_DLY1CONF_gp 2 /* Delay Configuration on LUT1 group position. */ ++#define XCL_DLY1CONF0_bm (1<<2) /* Delay Configuration on LUT1 bit 0 mask. */ ++#define XCL_DLY1CONF0_bp 2 /* Delay Configuration on LUT1 bit 0 position. */ ++#define XCL_DLY1CONF1_bm (1<<3) /* Delay Configuration on LUT1 bit 1 mask. */ ++#define XCL_DLY1CONF1_bp 3 /* Delay Configuration on LUT1 bit 1 position. */ ++ ++#define XCL_DLY0CONF_gm 0x03 /* Delay Configuration on LUT0 group mask. */ ++#define XCL_DLY0CONF_gp 0 /* Delay Configuration on LUT0 group position. */ ++#define XCL_DLY0CONF0_bm (1<<0) /* Delay Configuration on LUT0 bit 0 mask. */ ++#define XCL_DLY0CONF0_bp 0 /* Delay Configuration on LUT0 bit 0 position. */ ++#define XCL_DLY0CONF1_bm (1<<1) /* Delay Configuration on LUT0 bit 1 mask. */ ++#define XCL_DLY0CONF1_bp 1 /* Delay Configuration on LUT0 bit 1 position. */ ++ ++/* XCL.CTRLD bit masks and bit positions */ ++#define XCL_TRUTH1_gm 0xF0 /* Truth Table of LUT1 group mask. */ ++#define XCL_TRUTH1_gp 4 /* Truth Table of LUT1 group position. */ ++#define XCL_TRUTH10_bm (1<<4) /* Truth Table of LUT1 bit 0 mask. */ ++#define XCL_TRUTH10_bp 4 /* Truth Table of LUT1 bit 0 position. */ ++#define XCL_TRUTH11_bm (1<<5) /* Truth Table of LUT1 bit 1 mask. */ ++#define XCL_TRUTH11_bp 5 /* Truth Table of LUT1 bit 1 position. */ ++#define XCL_TRUTH12_bm (1<<6) /* Truth Table of LUT1 bit 2 mask. */ ++#define XCL_TRUTH12_bp 6 /* Truth Table of LUT1 bit 2 position. */ ++#define XCL_TRUTH13_bm (1<<7) /* Truth Table of LUT1 bit 3 mask. */ ++#define XCL_TRUTH13_bp 7 /* Truth Table of LUT1 bit 3 position. */ ++ ++#define XCL_TRUTH0_gm 0x0F /* Truth Table of LUT0 group mask. */ ++#define XCL_TRUTH0_gp 0 /* Truth Table of LUT0 group position. */ ++#define XCL_TRUTH00_bm (1<<0) /* Truth Table of LUT0 bit 0 mask. */ ++#define XCL_TRUTH00_bp 0 /* Truth Table of LUT0 bit 0 position. */ ++#define XCL_TRUTH01_bm (1<<1) /* Truth Table of LUT0 bit 1 mask. */ ++#define XCL_TRUTH01_bp 1 /* Truth Table of LUT0 bit 1 position. */ ++#define XCL_TRUTH02_bm (1<<2) /* Truth Table of LUT0 bit 2 mask. */ ++#define XCL_TRUTH02_bp 2 /* Truth Table of LUT0 bit 2 position. */ ++#define XCL_TRUTH03_bm (1<<3) /* Truth Table of LUT0 bit 3 mask. */ ++#define XCL_TRUTH03_bp 3 /* Truth Table of LUT0 bit 3 position. */ ++ ++/* XCL.CTRLE bit masks and bit positions */ ++#define XCL_CMDSEL_bm 0x80 /* Timer/Counter Command Selection bit mask. */ ++#define XCL_CMDSEL_bp 7 /* Timer/Counter Command Selection bit position. */ ++ ++#define XCL_TCSEL_gm 0x70 /* Timer/Counter Selection group mask. */ ++#define XCL_TCSEL_gp 4 /* Timer/Counter Selection group position. */ ++#define XCL_TCSEL0_bm (1<<4) /* Timer/Counter Selection bit 0 mask. */ ++#define XCL_TCSEL0_bp 4 /* Timer/Counter Selection bit 0 position. */ ++#define XCL_TCSEL1_bm (1<<5) /* Timer/Counter Selection bit 1 mask. */ ++#define XCL_TCSEL1_bp 5 /* Timer/Counter Selection bit 1 position. */ ++#define XCL_TCSEL2_bm (1<<6) /* Timer/Counter Selection bit 2 mask. */ ++#define XCL_TCSEL2_bp 6 /* Timer/Counter Selection bit 2 position. */ ++ ++#define XCL_CLKSEL_gm 0x0F /* Clock Selection group mask. */ ++#define XCL_CLKSEL_gp 0 /* Clock Selection group position. */ ++#define XCL_CLKSEL0_bm (1<<0) /* Clock Selection bit 0 mask. */ ++#define XCL_CLKSEL0_bp 0 /* Clock Selection bit 0 position. */ ++#define XCL_CLKSEL1_bm (1<<1) /* Clock Selection bit 1 mask. */ ++#define XCL_CLKSEL1_bp 1 /* Clock Selection bit 1 position. */ ++#define XCL_CLKSEL2_bm (1<<2) /* Clock Selection bit 2 mask. */ ++#define XCL_CLKSEL2_bp 2 /* Clock Selection bit 2 position. */ ++#define XCL_CLKSEL3_bm (1<<3) /* Clock Selection bit 3 mask. */ ++#define XCL_CLKSEL3_bp 3 /* Clock Selection bit 3 position. */ ++ ++/* XCL.CTRLF bit masks and bit positions */ ++#define XCL_CMDEN_gm 0xC0 /* Command Enable group mask. */ ++#define XCL_CMDEN_gp 6 /* Command Enable group position. */ ++#define XCL_CMDEN0_bm (1<<6) /* Command Enable bit 0 mask. */ ++#define XCL_CMDEN0_bp 6 /* Command Enable bit 0 position. */ ++#define XCL_CMDEN1_bm (1<<7) /* Command Enable bit 1 mask. */ ++#define XCL_CMDEN1_bp 7 /* Command Enable bit 1 position. */ ++ ++#define XCL_CMP1_bm 0x20 /* Compare Channel 1 Output Value bit mask. */ ++#define XCL_CMP1_bp 5 /* Compare Channel 1 Output Value bit position. */ ++ ++#define XCL_CMP0_bm 0x10 /* Compare Channel 0 Output Value bit mask. */ ++#define XCL_CMP0_bp 4 /* Compare Channel 0 Output Value bit position. */ ++ ++#define XCL_CCEN1_bm 0x08 /* Compare or Capture Channel 1 Enable bit mask. */ ++#define XCL_CCEN1_bp 3 /* Compare or Capture Channel 1 Enable bit position. */ ++ ++#define XCL_CCEN0_bm 0x04 /* Compare or Capture Channel 0 Enable bit mask. */ ++#define XCL_CCEN0_bp 2 /* Compare or Capture Channel 0 Enable bit position. */ ++ ++#define XCL_MODE_gm 0x03 /* Timer/Counter Mode group mask. */ ++#define XCL_MODE_gp 0 /* Timer/Counter Mode group position. */ ++#define XCL_MODE0_bm (1<<0) /* Timer/Counter Mode bit 0 mask. */ ++#define XCL_MODE0_bp 0 /* Timer/Counter Mode bit 0 position. */ ++#define XCL_MODE1_bm (1<<1) /* Timer/Counter Mode bit 1 mask. */ ++#define XCL_MODE1_bp 1 /* Timer/Counter Mode bit 1 position. */ ++ ++/* XCL.CTRLG bit masks and bit positions */ ++#define XCL_EVACTEN_bm 0x80 /* Event Action Enable bit mask. */ ++#define XCL_EVACTEN_bp 7 /* Event Action Enable bit position. */ ++ ++#define XCL_EVACT1_gm 0x60 /* Event Action Selection on Timer/Counter 1 group mask. */ ++#define XCL_EVACT1_gp 5 /* Event Action Selection on Timer/Counter 1 group position. */ ++#define XCL_EVACT10_bm (1<<5) /* Event Action Selection on Timer/Counter 1 bit 0 mask. */ ++#define XCL_EVACT10_bp 5 /* Event Action Selection on Timer/Counter 1 bit 0 position. */ ++#define XCL_EVACT11_bm (1<<6) /* Event Action Selection on Timer/Counter 1 bit 1 mask. */ ++#define XCL_EVACT11_bp 6 /* Event Action Selection on Timer/Counter 1 bit 1 position. */ ++ ++#define XCL_EVACT0_gm 0x18 /* Event Action Selection on Timer/Counter 0 group mask. */ ++#define XCL_EVACT0_gp 3 /* Event Action Selection on Timer/Counter 0 group position. */ ++#define XCL_EVACT00_bm (1<<3) /* Event Action Selection on Timer/Counter 0 bit 0 mask. */ ++#define XCL_EVACT00_bp 3 /* Event Action Selection on Timer/Counter 0 bit 0 position. */ ++#define XCL_EVACT01_bm (1<<4) /* Event Action Selection on Timer/Counter 0 bit 1 mask. */ ++#define XCL_EVACT01_bp 4 /* Event Action Selection on Timer/Counter 0 bit 1 position. */ ++ ++#define XCL_EVSRC_gm 0x07 /* Event Source Selection group mask. */ ++#define XCL_EVSRC_gp 0 /* Event Source Selection group position. */ ++#define XCL_EVSRC0_bm (1<<0) /* Event Source Selection bit 0 mask. */ ++#define XCL_EVSRC0_bp 0 /* Event Source Selection bit 0 position. */ ++#define XCL_EVSRC1_bm (1<<1) /* Event Source Selection bit 1 mask. */ ++#define XCL_EVSRC1_bp 1 /* Event Source Selection bit 1 position. */ ++#define XCL_EVSRC2_bm (1<<2) /* Event Source Selection bit 2 mask. */ ++#define XCL_EVSRC2_bp 2 /* Event Source Selection bit 2 position. */ ++ ++/* XCL.INTCTRL bit masks and bit positions */ ++#define XCL_UNF1IE_bm 0x80 /* Underflow 1 Interrupt Enable bit mask. */ ++#define XCL_UNF1IE_bp 7 /* Underflow 1 Interrupt Enable bit position. */ ++ ++#define XCL_PEC1IE_bm 0x80 /* Peripheral Counter 1 Interrupt Enable bit mask. */ ++#define XCL_PEC1IE_bp 7 /* Peripheral Counter 1 Interrupt Enable bit position. */ ++ ++#define XCL_PEC21IE_bm 0x80 /* Peripheral High Counter 2 Interrupt Enable bit mask. */ ++#define XCL_PEC21IE_bp 7 /* Peripheral High Counter 2 Interrupt Enable bit position. */ ++ ++#define XCL_UNF0IE_bm 0x40 /* Underflow 0 Interrupt Enable bit mask. */ ++#define XCL_UNF0IE_bp 6 /* Underflow 0 Interrupt Enable bit position. */ ++ ++#define XCL_PEC0IE_bm 0x40 /* Peripheral Counter 0 Interrupt Enable bit mask. */ ++#define XCL_PEC0IE_bp 6 /* Peripheral Counter 0 Interrupt Enable bit position. */ ++ ++#define XCL_CC1IE_bm 0x20 /* Compare Or Capture 1 Interrupt Enable bit mask. */ ++#define XCL_CC1IE_bp 5 /* Compare Or Capture 1 Interrupt Enable bit position. */ ++ ++#define XCL_PEC20IE_bm 0x20 /* Peripheral Low Counter 2 Interrupt Enable bit mask. */ ++#define XCL_PEC20IE_bp 5 /* Peripheral Low Counter 2 Interrupt Enable bit position. */ ++ ++#define XCL_CC0IE_bm 0x10 /* Compare Or Capture 0 Interrupt Enable bit mask. */ ++#define XCL_CC0IE_bp 4 /* Compare Or Capture 0 Interrupt Enable bit position. */ ++ ++#define XCL_UNFINTLVL_gm 0x0C /* Timer Underflow Interrupt Level group mask. */ ++#define XCL_UNFINTLVL_gp 2 /* Timer Underflow Interrupt Level group position. */ ++#define XCL_UNFINTLVL0_bm (1<<2) /* Timer Underflow Interrupt Level bit 0 mask. */ ++#define XCL_UNFINTLVL0_bp 2 /* Timer Underflow Interrupt Level bit 0 position. */ ++#define XCL_UNFINTLVL1_bm (1<<3) /* Timer Underflow Interrupt Level bit 1 mask. */ ++#define XCL_UNFINTLVL1_bp 3 /* Timer Underflow Interrupt Level bit 1 position. */ ++ ++#define XCL_CCINTLVL_gm 0x03 /* Timer Compare or Capture Interrupt Level group mask. */ ++#define XCL_CCINTLVL_gp 0 /* Timer Compare or Capture Interrupt Level group position. */ ++#define XCL_CCINTLVL0_bm (1<<0) /* Timer Compare or Capture Interrupt Level bit 0 mask. */ ++#define XCL_CCINTLVL0_bp 0 /* Timer Compare or Capture Interrupt Level bit 0 position. */ ++#define XCL_CCINTLVL1_bm (1<<1) /* Timer Compare or Capture Interrupt Level bit 1 mask. */ ++#define XCL_CCINTLVL1_bp 1 /* Timer Compare or Capture Interrupt Level bit 1 position. */ ++ ++/* XCL.INTFLAGS bit masks and bit positions */ ++#define XCL_UNF1IF_bm 0x80 /* Timer/Counter 1 Underflow Interrupt Flag bit mask. */ ++#define XCL_UNF1IF_bp 7 /* Timer/Counter 1 Underflow Interrupt Flag bit position. */ ++ ++#define XCL_PEC1IF_bm 0x80 /* Peripheral Counter 1 Interrupt Flag bit mask. */ ++#define XCL_PEC1IF_bp 7 /* Peripheral Counter 1 Interrupt Flag bit position. */ ++ ++#define XCL_PEC21IF_bm 0x80 /* Peripheral High Counter 2 Interrupt Flag bit mask. */ ++#define XCL_PEC21IF_bp 7 /* Peripheral High Counter 2 Interrupt Flag bit position. */ ++ ++#define XCL_UNF0IF_bm 0x40 /* Timer/Counter 0 Underflow Interrupt Flag bit mask. */ ++#define XCL_UNF0IF_bp 6 /* Timer/Counter 0 Underflow Interrupt Flag bit position. */ ++ ++#define XCL_PEC0IF_bm 0x40 /* Peripheral Counter 0 Interrupt Flag bit mask. */ ++#define XCL_PEC0IF_bp 6 /* Peripheral Counter 0 Interrupt Flag bit position. */ ++ ++#define XCL_CC1IF_bm 0x20 /* Compare or Capture Channel 1 Interrupt Flag bit mask. */ ++#define XCL_CC1IF_bp 5 /* Compare or Capture Channel 1 Interrupt Flag bit position. */ ++ ++#define XCL_PEC20IF_bm 0x20 /* Peripheral Low Counter 2 Interrupt Flag bit mask. */ ++#define XCL_PEC20IF_bp 5 /* Peripheral Low Counter 2 Interrupt Flag bit position. */ ++ ++#define XCL_CC0IF_bm 0x10 /* Compare or Capture Channel 0 Interrupt Flag bit mask. */ ++#define XCL_CC0IF_bp 4 /* Compare or Capture Channel 0 Interrupt Flag bit position. */ ++ ++/* XCL.PLC bit masks and bit positions */ ++#define XCL_PLC_gm 0xFF /* Peripheral Lenght Control Bits group mask. */ ++#define XCL_PLC_gp 0 /* Peripheral Lenght Control Bits group position. */ ++#define XCL_PLC0_bm (1<<0) /* Peripheral Lenght Control Bits bit 0 mask. */ ++#define XCL_PLC0_bp 0 /* Peripheral Lenght Control Bits bit 0 position. */ ++#define XCL_PLC1_bm (1<<1) /* Peripheral Lenght Control Bits bit 1 mask. */ ++#define XCL_PLC1_bp 1 /* Peripheral Lenght Control Bits bit 1 position. */ ++#define XCL_PLC2_bm (1<<2) /* Peripheral Lenght Control Bits bit 2 mask. */ ++#define XCL_PLC2_bp 2 /* Peripheral Lenght Control Bits bit 2 position. */ ++#define XCL_PLC3_bm (1<<3) /* Peripheral Lenght Control Bits bit 3 mask. */ ++#define XCL_PLC3_bp 3 /* Peripheral Lenght Control Bits bit 3 position. */ ++#define XCL_PLC4_bm (1<<4) /* Peripheral Lenght Control Bits bit 4 mask. */ ++#define XCL_PLC4_bp 4 /* Peripheral Lenght Control Bits bit 4 position. */ ++#define XCL_PLC5_bm (1<<5) /* Peripheral Lenght Control Bits bit 5 mask. */ ++#define XCL_PLC5_bp 5 /* Peripheral Lenght Control Bits bit 5 position. */ ++#define XCL_PLC6_bm (1<<6) /* Peripheral Lenght Control Bits bit 6 mask. */ ++#define XCL_PLC6_bp 6 /* Peripheral Lenght Control Bits bit 6 position. */ ++#define XCL_PLC7_bm (1<<7) /* Peripheral Lenght Control Bits bit 7 mask. */ ++#define XCL_PLC7_bp 7 /* Peripheral Lenght Control Bits bit 7 position. */ ++ ++/* XCL.CNTL bit masks and bit positions */ ++#define XCL_BCNTO_gm 0xFF /* BTC0 Counter Byte group mask. */ ++#define XCL_BCNTO_gp 0 /* BTC0 Counter Byte group position. */ ++#define XCL_BCNTO0_bm (1<<0) /* BTC0 Counter Byte bit 0 mask. */ ++#define XCL_BCNTO0_bp 0 /* BTC0 Counter Byte bit 0 position. */ ++#define XCL_BCNTO1_bm (1<<1) /* BTC0 Counter Byte bit 1 mask. */ ++#define XCL_BCNTO1_bp 1 /* BTC0 Counter Byte bit 1 position. */ ++#define XCL_BCNTO2_bm (1<<2) /* BTC0 Counter Byte bit 2 mask. */ ++#define XCL_BCNTO2_bp 2 /* BTC0 Counter Byte bit 2 position. */ ++#define XCL_BCNTO3_bm (1<<3) /* BTC0 Counter Byte bit 3 mask. */ ++#define XCL_BCNTO3_bp 3 /* BTC0 Counter Byte bit 3 position. */ ++#define XCL_BCNTO4_bm (1<<4) /* BTC0 Counter Byte bit 4 mask. */ ++#define XCL_BCNTO4_bp 4 /* BTC0 Counter Byte bit 4 position. */ ++#define XCL_BCNTO5_bm (1<<5) /* BTC0 Counter Byte bit 5 mask. */ ++#define XCL_BCNTO5_bp 5 /* BTC0 Counter Byte bit 5 position. */ ++#define XCL_BCNTO6_bm (1<<6) /* BTC0 Counter Byte bit 6 mask. */ ++#define XCL_BCNTO6_bp 6 /* BTC0 Counter Byte bit 6 position. */ ++#define XCL_BCNTO7_bm (1<<7) /* BTC0 Counter Byte bit 7 mask. */ ++#define XCL_BCNTO7_bp 7 /* BTC0 Counter Byte bit 7 position. */ ++ ++#define XCL_CNTL_gm 0xFF /* TC16 Counter Low Byte group mask. */ ++#define XCL_CNTL_gp 0 /* TC16 Counter Low Byte group position. */ ++#define XCL_CNTL0_bm (1<<0) /* TC16 Counter Low Byte bit 0 mask. */ ++#define XCL_CNTL0_bp 0 /* TC16 Counter Low Byte bit 0 position. */ ++#define XCL_CNTL1_bm (1<<1) /* TC16 Counter Low Byte bit 1 mask. */ ++#define XCL_CNTL1_bp 1 /* TC16 Counter Low Byte bit 1 position. */ ++#define XCL_CNTL2_bm (1<<2) /* TC16 Counter Low Byte bit 2 mask. */ ++#define XCL_CNTL2_bp 2 /* TC16 Counter Low Byte bit 2 position. */ ++#define XCL_CNTL3_bm (1<<3) /* TC16 Counter Low Byte bit 3 mask. */ ++#define XCL_CNTL3_bp 3 /* TC16 Counter Low Byte bit 3 position. */ ++#define XCL_CNTL4_bm (1<<4) /* TC16 Counter Low Byte bit 4 mask. */ ++#define XCL_CNTL4_bp 4 /* TC16 Counter Low Byte bit 4 position. */ ++#define XCL_CNTL5_bm (1<<5) /* TC16 Counter Low Byte bit 5 mask. */ ++#define XCL_CNTL5_bp 5 /* TC16 Counter Low Byte bit 5 position. */ ++#define XCL_CNTL6_bm (1<<6) /* TC16 Counter Low Byte bit 6 mask. */ ++#define XCL_CNTL6_bp 6 /* TC16 Counter Low Byte bit 6 position. */ ++#define XCL_CNTL7_bm (1<<7) /* TC16 Counter Low Byte bit 7 mask. */ ++#define XCL_CNTL7_bp 7 /* TC16 Counter Low Byte bit 7 position. */ ++ ++#define XCL_PCNTO_gm 0xFF /* Peripheral Counter 0 Byte group mask. */ ++#define XCL_PCNTO_gp 0 /* Peripheral Counter 0 Byte group position. */ ++#define XCL_PCNTO0_bm (1<<0) /* Peripheral Counter 0 Byte bit 0 mask. */ ++#define XCL_PCNTO0_bp 0 /* Peripheral Counter 0 Byte bit 0 position. */ ++#define XCL_PCNTO1_bm (1<<1) /* Peripheral Counter 0 Byte bit 1 mask. */ ++#define XCL_PCNTO1_bp 1 /* Peripheral Counter 0 Byte bit 1 position. */ ++#define XCL_PCNTO2_bm (1<<2) /* Peripheral Counter 0 Byte bit 2 mask. */ ++#define XCL_PCNTO2_bp 2 /* Peripheral Counter 0 Byte bit 2 position. */ ++#define XCL_PCNTO3_bm (1<<3) /* Peripheral Counter 0 Byte bit 3 mask. */ ++#define XCL_PCNTO3_bp 3 /* Peripheral Counter 0 Byte bit 3 position. */ ++#define XCL_PCNTO4_bm (1<<4) /* Peripheral Counter 0 Byte bit 4 mask. */ ++#define XCL_PCNTO4_bp 4 /* Peripheral Counter 0 Byte bit 4 position. */ ++#define XCL_PCNTO5_bm (1<<5) /* Peripheral Counter 0 Byte bit 5 mask. */ ++#define XCL_PCNTO5_bp 5 /* Peripheral Counter 0 Byte bit 5 position. */ ++#define XCL_PCNTO6_bm (1<<6) /* Peripheral Counter 0 Byte bit 6 mask. */ ++#define XCL_PCNTO6_bp 6 /* Peripheral Counter 0 Byte bit 6 position. */ ++#define XCL_PCNTO7_bm (1<<7) /* Peripheral Counter 0 Byte bit 7 mask. */ ++#define XCL_PCNTO7_bp 7 /* Peripheral Counter 0 Byte bit 7 position. */ ++ ++/* XCL.CNTH bit masks and bit positions */ ++#define XCL_BCNT1_gm 0xFF /* BTC1 Counter Byte group mask. */ ++#define XCL_BCNT1_gp 0 /* BTC1 Counter Byte group position. */ ++#define XCL_BCNT10_bm (1<<0) /* BTC1 Counter Byte bit 0 mask. */ ++#define XCL_BCNT10_bp 0 /* BTC1 Counter Byte bit 0 position. */ ++#define XCL_BCNT11_bm (1<<1) /* BTC1 Counter Byte bit 1 mask. */ ++#define XCL_BCNT11_bp 1 /* BTC1 Counter Byte bit 1 position. */ ++#define XCL_BCNT12_bm (1<<2) /* BTC1 Counter Byte bit 2 mask. */ ++#define XCL_BCNT12_bp 2 /* BTC1 Counter Byte bit 2 position. */ ++#define XCL_BCNT13_bm (1<<3) /* BTC1 Counter Byte bit 3 mask. */ ++#define XCL_BCNT13_bp 3 /* BTC1 Counter Byte bit 3 position. */ ++#define XCL_BCNT14_bm (1<<4) /* BTC1 Counter Byte bit 4 mask. */ ++#define XCL_BCNT14_bp 4 /* BTC1 Counter Byte bit 4 position. */ ++#define XCL_BCNT15_bm (1<<5) /* BTC1 Counter Byte bit 5 mask. */ ++#define XCL_BCNT15_bp 5 /* BTC1 Counter Byte bit 5 position. */ ++#define XCL_BCNT16_bm (1<<6) /* BTC1 Counter Byte bit 6 mask. */ ++#define XCL_BCNT16_bp 6 /* BTC1 Counter Byte bit 6 position. */ ++#define XCL_BCNT17_bm (1<<7) /* BTC1 Counter Byte bit 7 mask. */ ++#define XCL_BCNT17_bp 7 /* BTC1 Counter Byte bit 7 position. */ ++ ++#define XCL_CNTH_gm 0xFF /* TC16 Counter High Byte group mask. */ ++#define XCL_CNTH_gp 0 /* TC16 Counter High Byte group position. */ ++#define XCL_CNTH0_bm (1<<0) /* TC16 Counter High Byte bit 0 mask. */ ++#define XCL_CNTH0_bp 0 /* TC16 Counter High Byte bit 0 position. */ ++#define XCL_CNTH1_bm (1<<1) /* TC16 Counter High Byte bit 1 mask. */ ++#define XCL_CNTH1_bp 1 /* TC16 Counter High Byte bit 1 position. */ ++#define XCL_CNTH2_bm (1<<2) /* TC16 Counter High Byte bit 2 mask. */ ++#define XCL_CNTH2_bp 2 /* TC16 Counter High Byte bit 2 position. */ ++#define XCL_CNTH3_bm (1<<3) /* TC16 Counter High Byte bit 3 mask. */ ++#define XCL_CNTH3_bp 3 /* TC16 Counter High Byte bit 3 position. */ ++#define XCL_CNTH4_bm (1<<4) /* TC16 Counter High Byte bit 4 mask. */ ++#define XCL_CNTH4_bp 4 /* TC16 Counter High Byte bit 4 position. */ ++#define XCL_CNTH5_bm (1<<5) /* TC16 Counter High Byte bit 5 mask. */ ++#define XCL_CNTH5_bp 5 /* TC16 Counter High Byte bit 5 position. */ ++#define XCL_CNTH6_bm (1<<6) /* TC16 Counter High Byte bit 6 mask. */ ++#define XCL_CNTH6_bp 6 /* TC16 Counter High Byte bit 6 position. */ ++#define XCL_CNTH7_bm (1<<7) /* TC16 Counter High Byte bit 7 mask. */ ++#define XCL_CNTH7_bp 7 /* TC16 Counter High Byte bit 7 position. */ ++ ++#define XCL_PCNT1_gm 0xFF /* Peripheral Counter 1 Byte group mask. */ ++#define XCL_PCNT1_gp 0 /* Peripheral Counter 1 Byte group position. */ ++#define XCL_PCNT10_bm (1<<0) /* Peripheral Counter 1 Byte bit 0 mask. */ ++#define XCL_PCNT10_bp 0 /* Peripheral Counter 1 Byte bit 0 position. */ ++#define XCL_PCNT11_bm (1<<1) /* Peripheral Counter 1 Byte bit 1 mask. */ ++#define XCL_PCNT11_bp 1 /* Peripheral Counter 1 Byte bit 1 position. */ ++#define XCL_PCNT12_bm (1<<2) /* Peripheral Counter 1 Byte bit 2 mask. */ ++#define XCL_PCNT12_bp 2 /* Peripheral Counter 1 Byte bit 2 position. */ ++#define XCL_PCNT13_bm (1<<3) /* Peripheral Counter 1 Byte bit 3 mask. */ ++#define XCL_PCNT13_bp 3 /* Peripheral Counter 1 Byte bit 3 position. */ ++#define XCL_PCNT14_bm (1<<4) /* Peripheral Counter 1 Byte bit 4 mask. */ ++#define XCL_PCNT14_bp 4 /* Peripheral Counter 1 Byte bit 4 position. */ ++#define XCL_PCNT15_bm (1<<5) /* Peripheral Counter 1 Byte bit 5 mask. */ ++#define XCL_PCNT15_bp 5 /* Peripheral Counter 1 Byte bit 5 position. */ ++#define XCL_PCNT16_bm (1<<6) /* Peripheral Counter 1 Byte bit 6 mask. */ ++#define XCL_PCNT16_bp 6 /* Peripheral Counter 1 Byte bit 6 position. */ ++#define XCL_PCNT17_bm (1<<7) /* Peripheral Counter 1 Byte bit 7 mask. */ ++#define XCL_PCNT17_bp 7 /* Peripheral Counter 1 Byte bit 7 position. */ ++ ++#define XCL_PCNT21_gm 0xF0 /* Peripheral High Counter 2 Bits group mask. */ ++#define XCL_PCNT21_gp 4 /* Peripheral High Counter 2 Bits group position. */ ++#define XCL_PCNT210_bm (1<<4) /* Peripheral High Counter 2 Bits bit 0 mask. */ ++#define XCL_PCNT210_bp 4 /* Peripheral High Counter 2 Bits bit 0 position. */ ++#define XCL_PCNT211_bm (1<<5) /* Peripheral High Counter 2 Bits bit 1 mask. */ ++#define XCL_PCNT211_bp 5 /* Peripheral High Counter 2 Bits bit 1 position. */ ++#define XCL_PCNT212_bm (1<<6) /* Peripheral High Counter 2 Bits bit 2 mask. */ ++#define XCL_PCNT212_bp 6 /* Peripheral High Counter 2 Bits bit 2 position. */ ++#define XCL_PCNT213_bm (1<<7) /* Peripheral High Counter 2 Bits bit 3 mask. */ ++#define XCL_PCNT213_bp 7 /* Peripheral High Counter 2 Bits bit 3 position. */ ++ ++#define XCL_PCNT20_gm 0x0F /* Peripheral Low Counter 2 Bits group mask. */ ++#define XCL_PCNT20_gp 0 /* Peripheral Low Counter 2 Bits group position. */ ++#define XCL_PCNT200_bm (1<<0) /* Peripheral Low Counter 2 Bits bit 0 mask. */ ++#define XCL_PCNT200_bp 0 /* Peripheral Low Counter 2 Bits bit 0 position. */ ++#define XCL_PCNT201_bm (1<<1) /* Peripheral Low Counter 2 Bits bit 1 mask. */ ++#define XCL_PCNT201_bp 1 /* Peripheral Low Counter 2 Bits bit 1 position. */ ++#define XCL_PCNT202_bm (1<<2) /* Peripheral Low Counter 2 Bits bit 2 mask. */ ++#define XCL_PCNT202_bp 2 /* Peripheral Low Counter 2 Bits bit 2 position. */ ++#define XCL_PCNT203_bm (1<<3) /* Peripheral Low Counter 2 Bits bit 3 mask. */ ++#define XCL_PCNT203_bp 3 /* Peripheral Low Counter 2 Bits bit 3 position. */ ++ ++/* XCL.CMPL bit masks and bit positions */ ++#define XCL_CMPL_gm 0xFF /* TC16 Compare Low Byte group mask. */ ++#define XCL_CMPL_gp 0 /* TC16 Compare Low Byte group position. */ ++#define XCL_CMPL0_bm (1<<0) /* TC16 Compare Low Byte bit 0 mask. */ ++#define XCL_CMPL0_bp 0 /* TC16 Compare Low Byte bit 0 position. */ ++#define XCL_CMPL1_bm (1<<1) /* TC16 Compare Low Byte bit 1 mask. */ ++#define XCL_CMPL1_bp 1 /* TC16 Compare Low Byte bit 1 position. */ ++#define XCL_CMPL2_bm (1<<2) /* TC16 Compare Low Byte bit 2 mask. */ ++#define XCL_CMPL2_bp 2 /* TC16 Compare Low Byte bit 2 position. */ ++#define XCL_CMPL3_bm (1<<3) /* TC16 Compare Low Byte bit 3 mask. */ ++#define XCL_CMPL3_bp 3 /* TC16 Compare Low Byte bit 3 position. */ ++#define XCL_CMPL4_bm (1<<4) /* TC16 Compare Low Byte bit 4 mask. */ ++#define XCL_CMPL4_bp 4 /* TC16 Compare Low Byte bit 4 position. */ ++#define XCL_CMPL5_bm (1<<5) /* TC16 Compare Low Byte bit 5 mask. */ ++#define XCL_CMPL5_bp 5 /* TC16 Compare Low Byte bit 5 position. */ ++#define XCL_CMPL6_bm (1<<6) /* TC16 Compare Low Byte bit 6 mask. */ ++#define XCL_CMPL6_bp 6 /* TC16 Compare Low Byte bit 6 position. */ ++#define XCL_CMPL7_bm (1<<7) /* TC16 Compare Low Byte bit 7 mask. */ ++#define XCL_CMPL7_bp 7 /* TC16 Compare Low Byte bit 7 position. */ ++ ++#define XCL_BCMP0_gm 0xFF /* BTC0 Compare Byte group mask. */ ++#define XCL_BCMP0_gp 0 /* BTC0 Compare Byte group position. */ ++#define XCL_BCMP00_bm (1<<0) /* BTC0 Compare Byte bit 0 mask. */ ++#define XCL_BCMP00_bp 0 /* BTC0 Compare Byte bit 0 position. */ ++#define XCL_BCMP01_bm (1<<1) /* BTC0 Compare Byte bit 1 mask. */ ++#define XCL_BCMP01_bp 1 /* BTC0 Compare Byte bit 1 position. */ ++#define XCL_BCMP02_bm (1<<2) /* BTC0 Compare Byte bit 2 mask. */ ++#define XCL_BCMP02_bp 2 /* BTC0 Compare Byte bit 2 position. */ ++#define XCL_BCMP03_bm (1<<3) /* BTC0 Compare Byte bit 3 mask. */ ++#define XCL_BCMP03_bp 3 /* BTC0 Compare Byte bit 3 position. */ ++#define XCL_BCMP04_bm (1<<4) /* BTC0 Compare Byte bit 4 mask. */ ++#define XCL_BCMP04_bp 4 /* BTC0 Compare Byte bit 4 position. */ ++#define XCL_BCMP05_bm (1<<5) /* BTC0 Compare Byte bit 5 mask. */ ++#define XCL_BCMP05_bp 5 /* BTC0 Compare Byte bit 5 position. */ ++#define XCL_BCMP06_bm (1<<6) /* BTC0 Compare Byte bit 6 mask. */ ++#define XCL_BCMP06_bp 6 /* BTC0 Compare Byte bit 6 position. */ ++#define XCL_BCMP07_bm (1<<7) /* BTC0 Compare Byte bit 7 mask. */ ++#define XCL_BCMP07_bp 7 /* BTC0 Compare Byte bit 7 position. */ ++ ++/* XCL.CMPH bit masks and bit positions */ ++#define XCL_CMPH_gm 0xFF /* TC16 Compare High Byte group mask. */ ++#define XCL_CMPH_gp 0 /* TC16 Compare High Byte group position. */ ++#define XCL_CMPH0_bm (1<<0) /* TC16 Compare High Byte bit 0 mask. */ ++#define XCL_CMPH0_bp 0 /* TC16 Compare High Byte bit 0 position. */ ++#define XCL_CMPH1_bm (1<<1) /* TC16 Compare High Byte bit 1 mask. */ ++#define XCL_CMPH1_bp 1 /* TC16 Compare High Byte bit 1 position. */ ++#define XCL_CMPH2_bm (1<<2) /* TC16 Compare High Byte bit 2 mask. */ ++#define XCL_CMPH2_bp 2 /* TC16 Compare High Byte bit 2 position. */ ++#define XCL_CMPH3_bm (1<<3) /* TC16 Compare High Byte bit 3 mask. */ ++#define XCL_CMPH3_bp 3 /* TC16 Compare High Byte bit 3 position. */ ++#define XCL_CMPH4_bm (1<<4) /* TC16 Compare High Byte bit 4 mask. */ ++#define XCL_CMPH4_bp 4 /* TC16 Compare High Byte bit 4 position. */ ++#define XCL_CMPH5_bm (1<<5) /* TC16 Compare High Byte bit 5 mask. */ ++#define XCL_CMPH5_bp 5 /* TC16 Compare High Byte bit 5 position. */ ++#define XCL_CMPH6_bm (1<<6) /* TC16 Compare High Byte bit 6 mask. */ ++#define XCL_CMPH6_bp 6 /* TC16 Compare High Byte bit 6 position. */ ++#define XCL_CMPH7_bm (1<<7) /* TC16 Compare High Byte bit 7 mask. */ ++#define XCL_CMPH7_bp 7 /* TC16 Compare High Byte bit 7 position. */ ++ ++#define XCL_BCMP1_gm 0xFF /* BTC1 Compare Byte group mask. */ ++#define XCL_BCMP1_gp 0 /* BTC1 Compare Byte group position. */ ++#define XCL_BCMP10_bm (1<<0) /* BTC1 Compare Byte bit 0 mask. */ ++#define XCL_BCMP10_bp 0 /* BTC1 Compare Byte bit 0 position. */ ++#define XCL_BCMP11_bm (1<<1) /* BTC1 Compare Byte bit 1 mask. */ ++#define XCL_BCMP11_bp 1 /* BTC1 Compare Byte bit 1 position. */ ++#define XCL_BCMP12_bm (1<<2) /* BTC1 Compare Byte bit 2 mask. */ ++#define XCL_BCMP12_bp 2 /* BTC1 Compare Byte bit 2 position. */ ++#define XCL_BCMP13_bm (1<<3) /* BTC1 Compare Byte bit 3 mask. */ ++#define XCL_BCMP13_bp 3 /* BTC1 Compare Byte bit 3 position. */ ++#define XCL_BCMP14_bm (1<<4) /* BTC1 Compare Byte bit 4 mask. */ ++#define XCL_BCMP14_bp 4 /* BTC1 Compare Byte bit 4 position. */ ++#define XCL_BCMP15_bm (1<<5) /* BTC1 Compare Byte bit 5 mask. */ ++#define XCL_BCMP15_bp 5 /* BTC1 Compare Byte bit 5 position. */ ++#define XCL_BCMP16_bm (1<<6) /* BTC1 Compare Byte bit 6 mask. */ ++#define XCL_BCMP16_bp 6 /* BTC1 Compare Byte bit 6 position. */ ++#define XCL_BCMP17_bm (1<<7) /* BTC1 Compare Byte bit 7 mask. */ ++#define XCL_BCMP17_bp 7 /* BTC1 Compare Byte bit 7 position. */ ++ ++/* XCL.PERCAPTL bit masks and bit positions */ ++#define XCL_PERL_gm 0xFF /* TC16 Low Byte Period group mask. */ ++#define XCL_PERL_gp 0 /* TC16 Low Byte Period group position. */ ++#define XCL_PERL0_bm (1<<0) /* TC16 Low Byte Period bit 0 mask. */ ++#define XCL_PERL0_bp 0 /* TC16 Low Byte Period bit 0 position. */ ++#define XCL_PERL1_bm (1<<1) /* TC16 Low Byte Period bit 1 mask. */ ++#define XCL_PERL1_bp 1 /* TC16 Low Byte Period bit 1 position. */ ++#define XCL_PERL2_bm (1<<2) /* TC16 Low Byte Period bit 2 mask. */ ++#define XCL_PERL2_bp 2 /* TC16 Low Byte Period bit 2 position. */ ++#define XCL_PERL3_bm (1<<3) /* TC16 Low Byte Period bit 3 mask. */ ++#define XCL_PERL3_bp 3 /* TC16 Low Byte Period bit 3 position. */ ++#define XCL_PERL4_bm (1<<4) /* TC16 Low Byte Period bit 4 mask. */ ++#define XCL_PERL4_bp 4 /* TC16 Low Byte Period bit 4 position. */ ++#define XCL_PERL5_bm (1<<5) /* TC16 Low Byte Period bit 5 mask. */ ++#define XCL_PERL5_bp 5 /* TC16 Low Byte Period bit 5 position. */ ++#define XCL_PERL6_bm (1<<6) /* TC16 Low Byte Period bit 6 mask. */ ++#define XCL_PERL6_bp 6 /* TC16 Low Byte Period bit 6 position. */ ++#define XCL_PERL7_bm (1<<7) /* TC16 Low Byte Period bit 7 mask. */ ++#define XCL_PERL7_bp 7 /* TC16 Low Byte Period bit 7 position. */ ++ ++#define XCL_CAPTL_gm 0xFF /* TC16 Capture Value Low Byte group mask. */ ++#define XCL_CAPTL_gp 0 /* TC16 Capture Value Low Byte group position. */ ++#define XCL_CAPTL0_bm (1<<0) /* TC16 Capture Value Low Byte bit 0 mask. */ ++#define XCL_CAPTL0_bp 0 /* TC16 Capture Value Low Byte bit 0 position. */ ++#define XCL_CAPTL1_bm (1<<1) /* TC16 Capture Value Low Byte bit 1 mask. */ ++#define XCL_CAPTL1_bp 1 /* TC16 Capture Value Low Byte bit 1 position. */ ++#define XCL_CAPTL2_bm (1<<2) /* TC16 Capture Value Low Byte bit 2 mask. */ ++#define XCL_CAPTL2_bp 2 /* TC16 Capture Value Low Byte bit 2 position. */ ++#define XCL_CAPTL3_bm (1<<3) /* TC16 Capture Value Low Byte bit 3 mask. */ ++#define XCL_CAPTL3_bp 3 /* TC16 Capture Value Low Byte bit 3 position. */ ++#define XCL_CAPTL4_bm (1<<4) /* TC16 Capture Value Low Byte bit 4 mask. */ ++#define XCL_CAPTL4_bp 4 /* TC16 Capture Value Low Byte bit 4 position. */ ++#define XCL_CAPTL5_bm (1<<5) /* TC16 Capture Value Low Byte bit 5 mask. */ ++#define XCL_CAPTL5_bp 5 /* TC16 Capture Value Low Byte bit 5 position. */ ++#define XCL_CAPTL6_bm (1<<6) /* TC16 Capture Value Low Byte bit 6 mask. */ ++#define XCL_CAPTL6_bp 6 /* TC16 Capture Value Low Byte bit 6 position. */ ++#define XCL_CAPTL7_bm (1<<7) /* TC16 Capture Value Low Byte bit 7 mask. */ ++#define XCL_CAPTL7_bp 7 /* TC16 Capture Value Low Byte bit 7 position. */ ++ ++#define XCL_BPER0_gm 0xFF /* BTC0 Period group mask. */ ++#define XCL_BPER0_gp 0 /* BTC0 Period group position. */ ++#define XCL_BPER00_bm (1<<0) /* BTC0 Period bit 0 mask. */ ++#define XCL_BPER00_bp 0 /* BTC0 Period bit 0 position. */ ++#define XCL_BPER01_bm (1<<1) /* BTC0 Period bit 1 mask. */ ++#define XCL_BPER01_bp 1 /* BTC0 Period bit 1 position. */ ++#define XCL_BPER02_bm (1<<2) /* BTC0 Period bit 2 mask. */ ++#define XCL_BPER02_bp 2 /* BTC0 Period bit 2 position. */ ++#define XCL_BPER03_bm (1<<3) /* BTC0 Period bit 3 mask. */ ++#define XCL_BPER03_bp 3 /* BTC0 Period bit 3 position. */ ++#define XCL_BPER04_bm (1<<4) /* BTC0 Period bit 4 mask. */ ++#define XCL_BPER04_bp 4 /* BTC0 Period bit 4 position. */ ++#define XCL_BPER05_bm (1<<5) /* BTC0 Period bit 5 mask. */ ++#define XCL_BPER05_bp 5 /* BTC0 Period bit 5 position. */ ++#define XCL_BPER06_bm (1<<6) /* BTC0 Period bit 6 mask. */ ++#define XCL_BPER06_bp 6 /* BTC0 Period bit 6 position. */ ++#define XCL_BPER07_bm (1<<7) /* BTC0 Period bit 7 mask. */ ++#define XCL_BPER07_bp 7 /* BTC0 Period bit 7 position. */ ++ ++#define XCL_BCAPT0_gm 0xFF /* BTC0 Capture Value Byte group mask. */ ++#define XCL_BCAPT0_gp 0 /* BTC0 Capture Value Byte group position. */ ++#define XCL_BCAPT00_bm (1<<0) /* BTC0 Capture Value Byte bit 0 mask. */ ++#define XCL_BCAPT00_bp 0 /* BTC0 Capture Value Byte bit 0 position. */ ++#define XCL_BCAPT01_bm (1<<1) /* BTC0 Capture Value Byte bit 1 mask. */ ++#define XCL_BCAPT01_bp 1 /* BTC0 Capture Value Byte bit 1 position. */ ++#define XCL_BCAPT02_bm (1<<2) /* BTC0 Capture Value Byte bit 2 mask. */ ++#define XCL_BCAPT02_bp 2 /* BTC0 Capture Value Byte bit 2 position. */ ++#define XCL_BCAPT03_bm (1<<3) /* BTC0 Capture Value Byte bit 3 mask. */ ++#define XCL_BCAPT03_bp 3 /* BTC0 Capture Value Byte bit 3 position. */ ++#define XCL_BCAPT04_bm (1<<4) /* BTC0 Capture Value Byte bit 4 mask. */ ++#define XCL_BCAPT04_bp 4 /* BTC0 Capture Value Byte bit 4 position. */ ++#define XCL_BCAPT05_bm (1<<5) /* BTC0 Capture Value Byte bit 5 mask. */ ++#define XCL_BCAPT05_bp 5 /* BTC0 Capture Value Byte bit 5 position. */ ++#define XCL_BCAPT06_bm (1<<6) /* BTC0 Capture Value Byte bit 6 mask. */ ++#define XCL_BCAPT06_bp 6 /* BTC0 Capture Value Byte bit 6 position. */ ++#define XCL_BCAPT07_bm (1<<7) /* BTC0 Capture Value Byte bit 7 mask. */ ++#define XCL_BCAPT07_bp 7 /* BTC0 Capture Value Byte bit 7 position. */ ++ ++/* XCL.PERCAPTH bit masks and bit positions */ ++#define XCL_PERH_gm 0xFF /* TC16 High Byte Period group mask. */ ++#define XCL_PERH_gp 0 /* TC16 High Byte Period group position. */ ++#define XCL_PERH0_bm (1<<0) /* TC16 High Byte Period bit 0 mask. */ ++#define XCL_PERH0_bp 0 /* TC16 High Byte Period bit 0 position. */ ++#define XCL_PERH1_bm (1<<1) /* TC16 High Byte Period bit 1 mask. */ ++#define XCL_PERH1_bp 1 /* TC16 High Byte Period bit 1 position. */ ++#define XCL_PERH2_bm (1<<2) /* TC16 High Byte Period bit 2 mask. */ ++#define XCL_PERH2_bp 2 /* TC16 High Byte Period bit 2 position. */ ++#define XCL_PERH3_bm (1<<3) /* TC16 High Byte Period bit 3 mask. */ ++#define XCL_PERH3_bp 3 /* TC16 High Byte Period bit 3 position. */ ++#define XCL_PERH4_bm (1<<4) /* TC16 High Byte Period bit 4 mask. */ ++#define XCL_PERH4_bp 4 /* TC16 High Byte Period bit 4 position. */ ++#define XCL_PERH5_bm (1<<5) /* TC16 High Byte Period bit 5 mask. */ ++#define XCL_PERH5_bp 5 /* TC16 High Byte Period bit 5 position. */ ++#define XCL_PERH6_bm (1<<6) /* TC16 High Byte Period bit 6 mask. */ ++#define XCL_PERH6_bp 6 /* TC16 High Byte Period bit 6 position. */ ++#define XCL_PERH7_bm (1<<7) /* TC16 High Byte Period bit 7 mask. */ ++#define XCL_PERH7_bp 7 /* TC16 High Byte Period bit 7 position. */ ++ ++#define XCL_CAPTH_gm 0xFF /* TC16 Capture Value High Byte group mask. */ ++#define XCL_CAPTH_gp 0 /* TC16 Capture Value High Byte group position. */ ++#define XCL_CAPTH0_bm (1<<0) /* TC16 Capture Value High Byte bit 0 mask. */ ++#define XCL_CAPTH0_bp 0 /* TC16 Capture Value High Byte bit 0 position. */ ++#define XCL_CAPTH1_bm (1<<1) /* TC16 Capture Value High Byte bit 1 mask. */ ++#define XCL_CAPTH1_bp 1 /* TC16 Capture Value High Byte bit 1 position. */ ++#define XCL_CAPTH2_bm (1<<2) /* TC16 Capture Value High Byte bit 2 mask. */ ++#define XCL_CAPTH2_bp 2 /* TC16 Capture Value High Byte bit 2 position. */ ++#define XCL_CAPTH3_bm (1<<3) /* TC16 Capture Value High Byte bit 3 mask. */ ++#define XCL_CAPTH3_bp 3 /* TC16 Capture Value High Byte bit 3 position. */ ++#define XCL_CAPTH4_bm (1<<4) /* TC16 Capture Value High Byte bit 4 mask. */ ++#define XCL_CAPTH4_bp 4 /* TC16 Capture Value High Byte bit 4 position. */ ++#define XCL_CAPTH5_bm (1<<5) /* TC16 Capture Value High Byte bit 5 mask. */ ++#define XCL_CAPTH5_bp 5 /* TC16 Capture Value High Byte bit 5 position. */ ++#define XCL_CAPTH6_bm (1<<6) /* TC16 Capture Value High Byte bit 6 mask. */ ++#define XCL_CAPTH6_bp 6 /* TC16 Capture Value High Byte bit 6 position. */ ++#define XCL_CAPTH7_bm (1<<7) /* TC16 Capture Value High Byte bit 7 mask. */ ++#define XCL_CAPTH7_bp 7 /* TC16 Capture Value High Byte bit 7 position. */ ++ ++#define XCL_BPER1_gm 0xFF /* BTC1 Period group mask. */ ++#define XCL_BPER1_gp 0 /* BTC1 Period group position. */ ++#define XCL_BPER10_bm (1<<0) /* BTC1 Period bit 0 mask. */ ++#define XCL_BPER10_bp 0 /* BTC1 Period bit 0 position. */ ++#define XCL_BPER11_bm (1<<1) /* BTC1 Period bit 1 mask. */ ++#define XCL_BPER11_bp 1 /* BTC1 Period bit 1 position. */ ++#define XCL_BPER12_bm (1<<2) /* BTC1 Period bit 2 mask. */ ++#define XCL_BPER12_bp 2 /* BTC1 Period bit 2 position. */ ++#define XCL_BPER13_bm (1<<3) /* BTC1 Period bit 3 mask. */ ++#define XCL_BPER13_bp 3 /* BTC1 Period bit 3 position. */ ++#define XCL_BPER14_bm (1<<4) /* BTC1 Period bit 4 mask. */ ++#define XCL_BPER14_bp 4 /* BTC1 Period bit 4 position. */ ++#define XCL_BPER15_bm (1<<5) /* BTC1 Period bit 5 mask. */ ++#define XCL_BPER15_bp 5 /* BTC1 Period bit 5 position. */ ++#define XCL_BPER16_bm (1<<6) /* BTC1 Period bit 6 mask. */ ++#define XCL_BPER16_bp 6 /* BTC1 Period bit 6 position. */ ++#define XCL_BPER17_bm (1<<7) /* BTC1 Period bit 7 mask. */ ++#define XCL_BPER17_bp 7 /* BTC1 Period bit 7 position. */ ++ ++#define XCL_BCAPT1_gm 0xFF /* BTC1 Capture Value Byte group mask. */ ++#define XCL_BCAPT1_gp 0 /* BTC1 Capture Value Byte group position. */ ++#define XCL_BCAPT10_bm (1<<0) /* BTC1 Capture Value Byte bit 0 mask. */ ++#define XCL_BCAPT10_bp 0 /* BTC1 Capture Value Byte bit 0 position. */ ++#define XCL_BCAPT11_bm (1<<1) /* BTC1 Capture Value Byte bit 1 mask. */ ++#define XCL_BCAPT11_bp 1 /* BTC1 Capture Value Byte bit 1 position. */ ++#define XCL_BCAPT12_bm (1<<2) /* BTC1 Capture Value Byte bit 2 mask. */ ++#define XCL_BCAPT12_bp 2 /* BTC1 Capture Value Byte bit 2 position. */ ++#define XCL_BCAPT13_bm (1<<3) /* BTC1 Capture Value Byte bit 3 mask. */ ++#define XCL_BCAPT13_bp 3 /* BTC1 Capture Value Byte bit 3 position. */ ++#define XCL_BCAPT14_bm (1<<4) /* BTC1 Capture Value Byte bit 4 mask. */ ++#define XCL_BCAPT14_bp 4 /* BTC1 Capture Value Byte bit 4 position. */ ++#define XCL_BCAPT15_bm (1<<5) /* BTC1 Capture Value Byte bit 5 mask. */ ++#define XCL_BCAPT15_bp 5 /* BTC1 Capture Value Byte bit 5 position. */ ++#define XCL_BCAPT16_bm (1<<6) /* BTC1 Capture Value Byte bit 6 mask. */ ++#define XCL_BCAPT16_bp 6 /* BTC1 Capture Value Byte bit 6 position. */ ++#define XCL_BCAPT17_bm (1<<7) /* BTC1 Capture Value Byte bit 7 mask. */ ++#define XCL_BCAPT17_bp 7 /* BTC1 Capture Value Byte bit 7 position. */ ++ ++/* TWI - Two-Wire Interface */ ++/* TWI.CTRL bit masks and bit positions */ ++#define TWI_BRIDGEEN_bm 0x80 /* Bridge Enable bit mask. */ ++#define TWI_BRIDGEEN_bp 7 /* Bridge Enable bit position. */ ++ ++#define TWI_SFMPEN_bm 0x40 /* Slave Fast Mode Plus Enable bit mask. */ ++#define TWI_SFMPEN_bp 6 /* Slave Fast Mode Plus Enable bit position. */ ++ ++#define TWI_SSDAHOLD_gm 0x30 /* Slave SDA Hold Time Enable group mask. */ ++#define TWI_SSDAHOLD_gp 4 /* Slave SDA Hold Time Enable group position. */ ++#define TWI_SSDAHOLD0_bm (1<<4) /* Slave SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SSDAHOLD0_bp 4 /* Slave SDA Hold Time Enable bit 0 position. */ ++#define TWI_SSDAHOLD1_bm (1<<5) /* Slave SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SSDAHOLD1_bp 5 /* Slave SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_FMPEN_bm 0x08 /* FMPLUS Enable bit mask. */ ++#define TWI_FMPEN_bp 3 /* FMPLUS Enable bit position. */ ++ ++#define TWI_SDAHOLD_gm 0x06 /* SDA Hold Time Enable group mask. */ ++#define TWI_SDAHOLD_gp 1 /* SDA Hold Time Enable group position. */ ++#define TWI_SDAHOLD0_bm (1<<1) /* SDA Hold Time Enable bit 0 mask. */ ++#define TWI_SDAHOLD0_bp 1 /* SDA Hold Time Enable bit 0 position. */ ++#define TWI_SDAHOLD1_bm (1<<2) /* SDA Hold Time Enable bit 1 mask. */ ++#define TWI_SDAHOLD1_bp 2 /* SDA Hold Time Enable bit 1 position. */ ++ ++#define TWI_EDIEN_bm 0x01 /* External Driver Interface Enable bit mask. */ ++#define TWI_EDIEN_bp 0 /* External Driver Interface Enable bit position. */ ++ ++/* TWI_MASTER.CTRLA bit masks and bit positions */ ++#define TWI_MASTER_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_MASTER_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_MASTER_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_MASTER_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_MASTER_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_MASTER_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_MASTER_RIEN_bm 0x20 /* Read Interrupt Enable bit mask. */ ++#define TWI_MASTER_RIEN_bp 5 /* Read Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_WIEN_bm 0x10 /* Write Interrupt Enable bit mask. */ ++#define TWI_MASTER_WIEN_bp 4 /* Write Interrupt Enable bit position. */ ++ ++#define TWI_MASTER_ENABLE_bm 0x08 /* Enable TWI Master bit mask. */ ++#define TWI_MASTER_ENABLE_bp 3 /* Enable TWI Master bit position. */ ++ ++/* TWI_MASTER.CTRLB bit masks and bit positions */ ++#define TWI_MASTER_TIMEOUT_gm 0x0C /* Inactive Bus Timeout group mask. */ ++#define TWI_MASTER_TIMEOUT_gp 2 /* Inactive Bus Timeout group position. */ ++#define TWI_MASTER_TIMEOUT0_bm (1<<2) /* Inactive Bus Timeout bit 0 mask. */ ++#define TWI_MASTER_TIMEOUT0_bp 2 /* Inactive Bus Timeout bit 0 position. */ ++#define TWI_MASTER_TIMEOUT1_bm (1<<3) /* Inactive Bus Timeout bit 1 mask. */ ++#define TWI_MASTER_TIMEOUT1_bp 3 /* Inactive Bus Timeout bit 1 position. */ ++ ++#define TWI_MASTER_QCEN_bm 0x02 /* Quick Command Enable bit mask. */ ++#define TWI_MASTER_QCEN_bp 1 /* Quick Command Enable bit position. */ ++ ++#define TWI_MASTER_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_MASTER_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++#define TWI_MASTER_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ ++#define TWI_MASTER_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ ++ ++#define TWI_MASTER_TSEXTEN_bm 0x20 /* Slave Extend Timeout Enable bit mask. */ ++#define TWI_MASTER_TSEXTEN_bp 5 /* Slave Extend Timeout Enable bit position. */ ++ ++#define TWI_MASTER_TMEXTEN_bm 0x40 /* Master Extend Timeout Enable bit mask. */ ++#define TWI_MASTER_TMEXTEN_bp 6 /* Master Extend Timeout Enable bit position. */ ++ ++#define TWI_MASTER_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ ++#define TWI_MASTER_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ ++ ++/* TWI_MASTER.CTRLC bit masks and bit positions */ ++#define TWI_MASTER_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_MASTER_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_MASTER_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_MASTER_CMD_gp 0 /* Command group position. */ ++#define TWI_MASTER_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_MASTER_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_MASTER_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_MASTER_CMD1_bp 1 /* Command bit 1 position. */ ++ ++/* TWI_MASTER.STATUS bit masks and bit positions */ ++#define TWI_MASTER_RIF_bm 0x80 /* Read Interrupt Flag bit mask. */ ++#define TWI_MASTER_RIF_bp 7 /* Read Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_WIF_bm 0x40 /* Write Interrupt Flag bit mask. */ ++#define TWI_MASTER_WIF_bp 6 /* Write Interrupt Flag bit position. */ ++ ++#define TWI_MASTER_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_MASTER_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_MASTER_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_MASTER_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_MASTER_ARBLOST_bm 0x08 /* Arbitration Lost bit mask. */ ++#define TWI_MASTER_ARBLOST_bp 3 /* Arbitration Lost bit position. */ ++ ++#define TWI_MASTER_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_MASTER_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_MASTER_BUSSTATE_gm 0x03 /* Bus State group mask. */ ++#define TWI_MASTER_BUSSTATE_gp 0 /* Bus State group position. */ ++#define TWI_MASTER_BUSSTATE0_bm (1<<0) /* Bus State bit 0 mask. */ ++#define TWI_MASTER_BUSSTATE0_bp 0 /* Bus State bit 0 position. */ ++#define TWI_MASTER_BUSSTATE1_bm (1<<1) /* Bus State bit 1 mask. */ ++#define TWI_MASTER_BUSSTATE1_bp 1 /* Bus State bit 1 position. */ ++ ++/* TWI_SLAVE.CTRLA bit masks and bit positions */ ++#define TWI_SLAVE_INTLVL_gm 0xC0 /* Interrupt Level group mask. */ ++#define TWI_SLAVE_INTLVL_gp 6 /* Interrupt Level group position. */ ++#define TWI_SLAVE_INTLVL0_bm (1<<6) /* Interrupt Level bit 0 mask. */ ++#define TWI_SLAVE_INTLVL0_bp 6 /* Interrupt Level bit 0 position. */ ++#define TWI_SLAVE_INTLVL1_bm (1<<7) /* Interrupt Level bit 1 mask. */ ++#define TWI_SLAVE_INTLVL1_bp 7 /* Interrupt Level bit 1 position. */ ++ ++#define TWI_SLAVE_DIEN_bm 0x20 /* Data Interrupt Enable bit mask. */ ++#define TWI_SLAVE_DIEN_bp 5 /* Data Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_APIEN_bm 0x10 /* Address/Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_APIEN_bp 4 /* Address/Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_ENABLE_bm 0x08 /* Enable TWI Slave bit mask. */ ++#define TWI_SLAVE_ENABLE_bp 3 /* Enable TWI Slave bit position. */ ++ ++#define TWI_SLAVE_PIEN_bm 0x04 /* Stop Interrupt Enable bit mask. */ ++#define TWI_SLAVE_PIEN_bp 2 /* Stop Interrupt Enable bit position. */ ++ ++#define TWI_SLAVE_PMEN_bm 0x02 /* Promiscuous Mode Enable bit mask. */ ++#define TWI_SLAVE_PMEN_bp 1 /* Promiscuous Mode Enable bit position. */ ++ ++#define TWI_SLAVE_SMEN_bm 0x01 /* Smart Mode Enable bit mask. */ ++#define TWI_SLAVE_SMEN_bp 0 /* Smart Mode Enable bit position. */ ++ ++/* TWI_SLAVE.CTRLB bit masks and bit positions */ ++#define TWI_SLAVE_ACKACT_bm 0x04 /* Acknowledge Action bit mask. */ ++#define TWI_SLAVE_ACKACT_bp 2 /* Acknowledge Action bit position. */ ++ ++#define TWI_SLAVE_CMD_gm 0x03 /* Command group mask. */ ++#define TWI_SLAVE_CMD_gp 0 /* Command group position. */ ++#define TWI_SLAVE_CMD0_bm (1<<0) /* Command bit 0 mask. */ ++#define TWI_SLAVE_CMD0_bp 0 /* Command bit 0 position. */ ++#define TWI_SLAVE_CMD1_bm (1<<1) /* Command bit 1 mask. */ ++#define TWI_SLAVE_CMD1_bp 1 /* Command bit 1 position. */ ++ ++#define TWI_SLAVE_TTOUTEN_bm 0x10 /* Ttimeout Enable bit mask. */ ++#define TWI_SLAVE_TTOUTEN_bp 4 /* Ttimeout Enable bit position. */ ++ ++#define TWI_SLAVE_TOIE_bm 0x80 /* Timeout Interrupt Enable bit mask. */ ++#define TWI_SLAVE_TOIE_bp 7 /* Timeout Interrupt Enable bit position. */ ++ ++/* TWI_SLAVE.STATUS bit masks and bit positions */ ++#define TWI_SLAVE_DIF_bm 0x80 /* Data Interrupt Flag bit mask. */ ++#define TWI_SLAVE_DIF_bp 7 /* Data Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_APIF_bm 0x40 /* Address/Stop Interrupt Flag bit mask. */ ++#define TWI_SLAVE_APIF_bp 6 /* Address/Stop Interrupt Flag bit position. */ ++ ++#define TWI_SLAVE_CLKHOLD_bm 0x20 /* Clock Hold bit mask. */ ++#define TWI_SLAVE_CLKHOLD_bp 5 /* Clock Hold bit position. */ ++ ++#define TWI_SLAVE_RXACK_bm 0x10 /* Received Acknowledge bit mask. */ ++#define TWI_SLAVE_RXACK_bp 4 /* Received Acknowledge bit position. */ ++ ++#define TWI_SLAVE_COLL_bm 0x08 /* Collision bit mask. */ ++#define TWI_SLAVE_COLL_bp 3 /* Collision bit position. */ ++ ++#define TWI_SLAVE_BUSERR_bm 0x04 /* Bus Error bit mask. */ ++#define TWI_SLAVE_BUSERR_bp 2 /* Bus Error bit position. */ ++ ++#define TWI_SLAVE_DIR_bm 0x02 /* Read/Write Direction bit mask. */ ++#define TWI_SLAVE_DIR_bp 1 /* Read/Write Direction bit position. */ ++ ++#define TWI_SLAVE_AP_bm 0x01 /* Slave Address or Stop bit mask. */ ++#define TWI_SLAVE_AP_bp 0 /* Slave Address or Stop bit position. */ ++ ++/* TWI_SLAVE.ADDRMASK bit masks and bit positions */ ++#define TWI_SLAVE_ADDRMASK_gm 0xFE /* Address Mask group mask. */ ++#define TWI_SLAVE_ADDRMASK_gp 1 /* Address Mask group position. */ ++#define TWI_SLAVE_ADDRMASK0_bm (1<<1) /* Address Mask bit 0 mask. */ ++#define TWI_SLAVE_ADDRMASK0_bp 1 /* Address Mask bit 0 position. */ ++#define TWI_SLAVE_ADDRMASK1_bm (1<<2) /* Address Mask bit 1 mask. */ ++#define TWI_SLAVE_ADDRMASK1_bp 2 /* Address Mask bit 1 position. */ ++#define TWI_SLAVE_ADDRMASK2_bm (1<<3) /* Address Mask bit 2 mask. */ ++#define TWI_SLAVE_ADDRMASK2_bp 3 /* Address Mask bit 2 position. */ ++#define TWI_SLAVE_ADDRMASK3_bm (1<<4) /* Address Mask bit 3 mask. */ ++#define TWI_SLAVE_ADDRMASK3_bp 4 /* Address Mask bit 3 position. */ ++#define TWI_SLAVE_ADDRMASK4_bm (1<<5) /* Address Mask bit 4 mask. */ ++#define TWI_SLAVE_ADDRMASK4_bp 5 /* Address Mask bit 4 position. */ ++#define TWI_SLAVE_ADDRMASK5_bm (1<<6) /* Address Mask bit 5 mask. */ ++#define TWI_SLAVE_ADDRMASK5_bp 6 /* Address Mask bit 5 position. */ ++#define TWI_SLAVE_ADDRMASK6_bm (1<<7) /* Address Mask bit 6 mask. */ ++#define TWI_SLAVE_ADDRMASK6_bp 7 /* Address Mask bit 6 position. */ ++ ++#define TWI_SLAVE_ADDREN_bm 0x01 /* Address Enable bit mask. */ ++#define TWI_SLAVE_ADDREN_bp 0 /* Address Enable bit position. */ ++ ++/* TWI_TIMEOUT.TOS bit masks and bit positions */ ++#define TWI_TIMEOUT_TTOUTMIF_bm 0x01 /* Master Ttimeout Interrupt Flag bit mask. */ ++#define TWI_TIMEOUT_TTOUTMIF_bp 0 /* Master Ttimeout Interrupt Flag bit position. */ ++ ++#define TWI_TIMEOUT_TSEXTIF_bm 0x02 /* Slave Extend Interrupt Flag bit mask. */ ++#define TWI_TIMEOUT_TSEXTIF_bp 1 /* Slave Extend Interrupt Flag bit position. */ ++ ++#define TWI_TIMEOUT_TMEXTIF_bm 0x04 /* Master Extend Interrupt Flag bit mask. */ ++#define TWI_TIMEOUT_TMEXTIF_bp 2 /* Master Extend Interrupt Flag bit position. */ ++ ++#define TWI_TIMEOUT_TTOUTSIF_bm 0x10 /* Slave Ttimeout Interrupt Flag bit mask. */ ++#define TWI_TIMEOUT_TTOUTSIF_bp 4 /* Slave Ttimeout Interrupt Flag bit position. */ ++ ++/* TWI_TIMEOUT.TOCONF bit masks and bit positions */ ++#define TWI_TIMEOUT_TTOUTMSEL_gm 0x07 /* Master Ttimeout Select group mask. */ ++#define TWI_TIMEOUT_TTOUTMSEL_gp 0 /* Master Ttimeout Select group position. */ ++#define TWI_TIMEOUT_TTOUTMSEL0_bm (1<<0) /* Master Ttimeout Select bit 0 mask. */ ++#define TWI_TIMEOUT_TTOUTMSEL0_bp 0 /* Master Ttimeout Select bit 0 position. */ ++#define TWI_TIMEOUT_TTOUTMSEL1_bm (1<<1) /* Master Ttimeout Select bit 1 mask. */ ++#define TWI_TIMEOUT_TTOUTMSEL1_bp 1 /* Master Ttimeout Select bit 1 position. */ ++#define TWI_TIMEOUT_TTOUTMSEL2_bm (1<<2) /* Master Ttimeout Select bit 2 mask. */ ++#define TWI_TIMEOUT_TTOUTMSEL2_bp 2 /* Master Ttimeout Select bit 2 position. */ ++ ++#define TWI_TIMEOUT_TMSEXTSEL_gm 0x18 /* Master/Slave Timeout Select group mask. */ ++#define TWI_TIMEOUT_TMSEXTSEL_gp 3 /* Master/Slave Timeout Select group position. */ ++#define TWI_TIMEOUT_TMSEXTSEL0_bm (1<<3) /* Master/Slave Timeout Select bit 0 mask. */ ++#define TWI_TIMEOUT_TMSEXTSEL0_bp 3 /* Master/Slave Timeout Select bit 0 position. */ ++#define TWI_TIMEOUT_TMSEXTSEL1_bm (1<<4) /* Master/Slave Timeout Select bit 1 mask. */ ++#define TWI_TIMEOUT_TMSEXTSEL1_bp 4 /* Master/Slave Timeout Select bit 1 position. */ ++ ++#define TWI_TIMEOUT_TTOUTSSEL_gm 0xE0 /* Slave Ttimeout Select group mask. */ ++#define TWI_TIMEOUT_TTOUTSSEL_gp 5 /* Slave Ttimeout Select group position. */ ++#define TWI_TIMEOUT_TTOUTSSEL0_bm (1<<5) /* Slave Ttimeout Select bit 0 mask. */ ++#define TWI_TIMEOUT_TTOUTSSEL0_bp 5 /* Slave Ttimeout Select bit 0 position. */ ++#define TWI_TIMEOUT_TTOUTSSEL1_bm (1<<6) /* Slave Ttimeout Select bit 1 mask. */ ++#define TWI_TIMEOUT_TTOUTSSEL1_bp 6 /* Slave Ttimeout Select bit 1 position. */ ++#define TWI_TIMEOUT_TTOUTSSEL2_bm (1<<7) /* Slave Ttimeout Select bit 2 mask. */ ++#define TWI_TIMEOUT_TTOUTSSEL2_bp 7 /* Slave Ttimeout Select bit 2 position. */ ++ ++/* PORT - Port Configuration */ ++/* PORT.INTCTRL bit masks and bit positions */ ++#define PORT_INTLVL_gm 0x03 /* Port Interrupt Level group mask. */ ++#define PORT_INTLVL_gp 0 /* Port Interrupt Level group position. */ ++#define PORT_INTLVL0_bm (1<<0) /* Port Interrupt Level bit 0 mask. */ ++#define PORT_INTLVL0_bp 0 /* Port Interrupt Level bit 0 position. */ ++#define PORT_INTLVL1_bm (1<<1) /* Port Interrupt Level bit 1 mask. */ ++#define PORT_INTLVL1_bp 1 /* Port Interrupt Level bit 1 position. */ ++ ++/* PORT.INTFLAGS bit masks and bit positions */ ++#define PORT_INT7IF_bm 0x80 /* Pin 7 Interrupt Flag bit mask. */ ++#define PORT_INT7IF_bp 7 /* Pin 7 Interrupt Flag bit position. */ ++ ++#define PORT_INT6IF_bm 0x40 /* Pin 6 Interrupt Flag bit mask. */ ++#define PORT_INT6IF_bp 6 /* Pin 6 Interrupt Flag bit position. */ ++ ++#define PORT_INT5IF_bm 0x20 /* Pin 5 Interrupt Flag bit mask. */ ++#define PORT_INT5IF_bp 5 /* Pin 5 Interrupt Flag bit position. */ ++ ++#define PORT_INT4IF_bm 0x10 /* Pin 4 Interrupt Flag bit mask. */ ++#define PORT_INT4IF_bp 4 /* Pin 4 Interrupt Flag bit position. */ ++ ++#define PORT_INT3IF_bm 0x08 /* Pin 3 Interrupt Flag bit mask. */ ++#define PORT_INT3IF_bp 3 /* Pin 3 Interrupt Flag bit position. */ ++ ++#define PORT_INT2IF_bm 0x04 /* Pin 2 Interrupt Flag bit mask. */ ++#define PORT_INT2IF_bp 2 /* Pin 2 Interrupt Flag bit position. */ ++ ++#define PORT_INT1IF_bm 0x02 /* Pin 1 Interrupt Flag bit mask. */ ++#define PORT_INT1IF_bp 1 /* Pin 1 Interrupt Flag bit position. */ ++ ++#define PORT_INT0IF_bm 0x01 /* Pin 0 Interrupt Flag bit mask. */ ++#define PORT_INT0IF_bp 0 /* Pin 0 Interrupt Flag bit position. */ ++ ++/* PORT.REMAP bit masks and bit positions */ ++#define PORT_USART0_bm 0x10 /* Usart0 bit mask. */ ++#define PORT_USART0_bp 4 /* Usart0 bit position. */ ++ ++#define PORT_TC4D_bm 0x08 /* Timer/Counter 4 Output Compare D bit mask. */ ++#define PORT_TC4D_bp 3 /* Timer/Counter 4 Output Compare D bit position. */ ++ ++#define PORT_TC4C_bm 0x04 /* Timer/Counter 4 Output Compare C bit mask. */ ++#define PORT_TC4C_bp 2 /* Timer/Counter 4 Output Compare C bit position. */ ++ ++#define PORT_TC4B_bm 0x02 /* Timer/Counter 4 Output Compare B bit mask. */ ++#define PORT_TC4B_bp 1 /* Timer/Counter 4 Output Compare B bit position. */ ++ ++#define PORT_TC4A_bm 0x01 /* Timer/Counter 4 Output Compare A bit mask. */ ++#define PORT_TC4A_bp 0 /* Timer/Counter 4 Output Compare A bit position. */ ++ ++/* PORT.PIN0CTRL bit masks and bit positions */ ++#define PORT_INVEN_bm 0x40 /* Inverted I/O Enable bit mask. */ ++#define PORT_INVEN_bp 6 /* Inverted I/O Enable bit position. */ ++ ++#define PORT_OPC_gm 0x38 /* Output/Pull Configuration group mask. */ ++#define PORT_OPC_gp 3 /* Output/Pull Configuration group position. */ ++#define PORT_OPC0_bm (1<<3) /* Output/Pull Configuration bit 0 mask. */ ++#define PORT_OPC0_bp 3 /* Output/Pull Configuration bit 0 position. */ ++#define PORT_OPC1_bm (1<<4) /* Output/Pull Configuration bit 1 mask. */ ++#define PORT_OPC1_bp 4 /* Output/Pull Configuration bit 1 position. */ ++#define PORT_OPC2_bm (1<<5) /* Output/Pull Configuration bit 2 mask. */ ++#define PORT_OPC2_bp 5 /* Output/Pull Configuration bit 2 position. */ ++ ++#define PORT_ISC_gm 0x07 /* Input/Sense Configuration group mask. */ ++#define PORT_ISC_gp 0 /* Input/Sense Configuration group position. */ ++#define PORT_ISC0_bm (1<<0) /* Input/Sense Configuration bit 0 mask. */ ++#define PORT_ISC0_bp 0 /* Input/Sense Configuration bit 0 position. */ ++#define PORT_ISC1_bm (1<<1) /* Input/Sense Configuration bit 1 mask. */ ++#define PORT_ISC1_bp 1 /* Input/Sense Configuration bit 1 position. */ ++#define PORT_ISC2_bm (1<<2) /* Input/Sense Configuration bit 2 mask. */ ++#define PORT_ISC2_bp 2 /* Input/Sense Configuration bit 2 position. */ ++ ++/* PORT.PIN1CTRL bit masks and bit positions */ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN2CTRL bit masks and bit positions */ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN3CTRL bit masks and bit positions */ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN4CTRL bit masks and bit positions */ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN5CTRL bit masks and bit positions */ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN6CTRL bit masks and bit positions */ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* PORT.PIN7CTRL bit masks and bit positions */ ++/* PORT_INVEN Predefined. */ ++/* PORT_INVEN Predefined. */ ++ ++/* PORT_OPC Predefined. */ ++/* PORT_OPC Predefined. */ ++ ++/* PORT_ISC Predefined. */ ++/* PORT_ISC Predefined. */ ++ ++/* TC - 16-bit Timer/Counter With PWM */ ++/* TC4.CTRLA bit masks and bit positions */ ++#define TC4_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ ++#define TC4_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ ++ ++#define TC4_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ ++#define TC4_EVSTART_bp 5 /* Start on Next Event bit position. */ ++ ++#define TC4_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ ++#define TC4_UPSTOP_bp 4 /* Stop on Next Update bit position. */ ++ ++#define TC4_CLKSEL_gm 0x0F /* Clock Select group mask. */ ++#define TC4_CLKSEL_gp 0 /* Clock Select group position. */ ++#define TC4_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ ++#define TC4_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ ++#define TC4_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ ++#define TC4_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ ++#define TC4_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ ++#define TC4_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ ++#define TC4_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ ++#define TC4_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ ++ ++/* TC4.CTRLB bit masks and bit positions */ ++#define TC4_BYTEM_gm 0xC0 /* Byte Mode group mask. */ ++#define TC4_BYTEM_gp 6 /* Byte Mode group position. */ ++#define TC4_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ ++#define TC4_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ ++#define TC4_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ ++#define TC4_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ ++ ++#define TC4_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ ++#define TC4_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ ++#define TC4_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ ++#define TC4_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ ++#define TC4_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ ++#define TC4_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ ++ ++#define TC4_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ ++#define TC4_WGMODE_gp 0 /* Waveform Generation Mode group position. */ ++#define TC4_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ ++#define TC4_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ ++#define TC4_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ ++#define TC4_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ ++#define TC4_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ ++#define TC4_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ ++ ++/* TC4.CTRLC bit masks and bit positions */ ++#define TC4_POLD_bm 0x80 /* Channel D Output Polarity bit mask. */ ++#define TC4_POLD_bp 7 /* Channel D Output Polarity bit position. */ ++ ++#define TC4_POLC_bm 0x40 /* Channel C Output Polarity bit mask. */ ++#define TC4_POLC_bp 6 /* Channel C Output Polarity bit position. */ ++ ++#define TC4_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ ++#define TC4_POLB_bp 5 /* Channel B Output Polarity bit position. */ ++ ++#define TC4_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ ++#define TC4_POLA_bp 4 /* Channel A Output Polarity bit position. */ ++ ++#define TC4_CMPD_bm 0x08 /* Channel D Compare Output Value bit mask. */ ++#define TC4_CMPD_bp 3 /* Channel D Compare Output Value bit position. */ ++ ++#define TC4_CMPC_bm 0x04 /* Channel C Compare Output Value bit mask. */ ++#define TC4_CMPC_bp 2 /* Channel C Compare Output Value bit position. */ ++ ++#define TC4_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ ++#define TC4_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ ++ ++#define TC4_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ ++#define TC4_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ ++ ++#define TC4_HCMPD_bm 0x80 /* High Channel D Compare Output Value bit mask. */ ++#define TC4_HCMPD_bp 7 /* High Channel D Compare Output Value bit position. */ ++ ++#define TC4_HCMPC_bm 0x40 /* High Channel C Compare Output Value bit mask. */ ++#define TC4_HCMPC_bp 6 /* High Channel C Compare Output Value bit position. */ ++ ++#define TC4_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ ++#define TC4_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ ++ ++#define TC4_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ ++#define TC4_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ ++ ++#define TC4_LCMPD_bm 0x08 /* Low Channel D Compare Output Value bit mask. */ ++#define TC4_LCMPD_bp 3 /* Low Channel D Compare Output Value bit position. */ ++ ++#define TC4_LCMPC_bm 0x04 /* Low Channel C Compare Output Value bit mask. */ ++#define TC4_LCMPC_bp 2 /* Low Channel C Compare Output Value bit position. */ ++ ++#define TC4_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ ++#define TC4_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ ++ ++#define TC4_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ ++#define TC4_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ ++ ++/* TC4.CTRLD bit masks and bit positions */ ++#define TC4_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC4_EVACT_gp 5 /* Event Action group position. */ ++#define TC4_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC4_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC4_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC4_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC4_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC4_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC4_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC4_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC4_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC4_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC4_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC4_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC4_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC4_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC4_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC4_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC4_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC4_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC4.CTRLE bit masks and bit positions */ ++#define TC4_CCDMODE_gm 0xC0 /* Channel D Compare or Capture Mode group mask. */ ++#define TC4_CCDMODE_gp 6 /* Channel D Compare or Capture Mode group position. */ ++#define TC4_CCDMODE0_bm (1<<6) /* Channel D Compare or Capture Mode bit 0 mask. */ ++#define TC4_CCDMODE0_bp 6 /* Channel D Compare or Capture Mode bit 0 position. */ ++#define TC4_CCDMODE1_bm (1<<7) /* Channel D Compare or Capture Mode bit 1 mask. */ ++#define TC4_CCDMODE1_bp 7 /* Channel D Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_CCCMODE_gm 0x30 /* Channel C Compare or Capture Mode group mask. */ ++#define TC4_CCCMODE_gp 4 /* Channel C Compare or Capture Mode group position. */ ++#define TC4_CCCMODE0_bm (1<<4) /* Channel C Compare or Capture Mode bit 0 mask. */ ++#define TC4_CCCMODE0_bp 4 /* Channel C Compare or Capture Mode bit 0 position. */ ++#define TC4_CCCMODE1_bm (1<<5) /* Channel C Compare or Capture Mode bit 1 mask. */ ++#define TC4_CCCMODE1_bp 5 /* Channel C Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ ++#define TC4_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ ++#define TC4_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ ++#define TC4_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ ++#define TC4_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ ++#define TC4_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ ++#define TC4_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ ++#define TC4_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ ++#define TC4_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ ++#define TC4_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ ++#define TC4_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_LCCDMODE_gm 0xC0 /* Channel Low D Compare or Capture Mode group mask. */ ++#define TC4_LCCDMODE_gp 6 /* Channel Low D Compare or Capture Mode group position. */ ++#define TC4_LCCDMODE0_bm (1<<6) /* Channel Low D Compare or Capture Mode bit 0 mask. */ ++#define TC4_LCCDMODE0_bp 6 /* Channel Low D Compare or Capture Mode bit 0 position. */ ++#define TC4_LCCDMODE1_bm (1<<7) /* Channel Low D Compare or Capture Mode bit 1 mask. */ ++#define TC4_LCCDMODE1_bp 7 /* Channel Low D Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_LCCCMODE_gm 0x30 /* Channel Low C Compare or Capture Mode group mask. */ ++#define TC4_LCCCMODE_gp 4 /* Channel Low C Compare or Capture Mode group position. */ ++#define TC4_LCCCMODE0_bm (1<<4) /* Channel Low C Compare or Capture Mode bit 0 mask. */ ++#define TC4_LCCCMODE0_bp 4 /* Channel Low C Compare or Capture Mode bit 0 position. */ ++#define TC4_LCCCMODE1_bm (1<<5) /* Channel Low C Compare or Capture Mode bit 1 mask. */ ++#define TC4_LCCCMODE1_bp 5 /* Channel Low C Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ ++#define TC4_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ ++#define TC4_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ ++#define TC4_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ ++#define TC4_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ ++#define TC4_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ ++#define TC4_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ ++#define TC4_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ ++#define TC4_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ ++#define TC4_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ ++#define TC4_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ ++ ++/* TC4.CTRLF bit masks and bit positions */ ++#define TC4_HCCDMODE_gm 0xC0 /* Channel High D Compare or Capture Mode group mask. */ ++#define TC4_HCCDMODE_gp 6 /* Channel High D Compare or Capture Mode group position. */ ++#define TC4_HCCDMODE0_bm (1<<6) /* Channel High D Compare or Capture Mode bit 0 mask. */ ++#define TC4_HCCDMODE0_bp 6 /* Channel High D Compare or Capture Mode bit 0 position. */ ++#define TC4_HCCDMODE1_bm (1<<7) /* Channel High D Compare or Capture Mode bit 1 mask. */ ++#define TC4_HCCDMODE1_bp 7 /* Channel High D Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_HCCCMODE_gm 0x30 /* Channel High C Compare or Capture Mode group mask. */ ++#define TC4_HCCCMODE_gp 4 /* Channel High C Compare or Capture Mode group position. */ ++#define TC4_HCCCMODE0_bm (1<<4) /* Channel High C Compare or Capture Mode bit 0 mask. */ ++#define TC4_HCCCMODE0_bp 4 /* Channel High C Compare or Capture Mode bit 0 position. */ ++#define TC4_HCCCMODE1_bm (1<<5) /* Channel High C Compare or Capture Mode bit 1 mask. */ ++#define TC4_HCCCMODE1_bp 5 /* Channel High C Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ ++#define TC4_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ ++#define TC4_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ ++#define TC4_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ ++#define TC4_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ ++#define TC4_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ ++ ++#define TC4_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ ++#define TC4_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ ++#define TC4_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ ++#define TC4_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ ++#define TC4_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ ++#define TC4_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ ++ ++/* TC4.INTCTRLA bit masks and bit positions */ ++#define TC4_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ ++#define TC4_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ ++#define TC4_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ ++#define TC4_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ ++#define TC4_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ ++#define TC4_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ ++ ++#define TC4_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ ++#define TC4_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ ++#define TC4_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ ++#define TC4_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ ++#define TC4_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ ++#define TC4_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ ++ ++#define TC4_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ ++#define TC4_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ ++#define TC4_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ ++#define TC4_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ ++#define TC4_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ ++#define TC4_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ ++ ++/* TC4.INTCTRLB bit masks and bit positions */ ++#define TC4_CCDINTLVL_gm 0xC0 /* Channel D Compare or Capture Interrupt Level group mask. */ ++#define TC4_CCDINTLVL_gp 6 /* Channel D Compare or Capture Interrupt Level group position. */ ++#define TC4_CCDINTLVL0_bm (1<<6) /* Channel D Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC4_CCDINTLVL0_bp 6 /* Channel D Compare or Capture Interrupt Level bit 0 position. */ ++#define TC4_CCDINTLVL1_bm (1<<7) /* Channel D Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC4_CCDINTLVL1_bp 7 /* Channel D Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC4_CCCINTLVL_gm 0x30 /* Channel C Compare or Capture Interrupt Level group mask. */ ++#define TC4_CCCINTLVL_gp 4 /* Channel C Compare or Capture Interrupt Level group position. */ ++#define TC4_CCCINTLVL0_bm (1<<4) /* Channel C Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC4_CCCINTLVL0_bp 4 /* Channel C Compare or Capture Interrupt Level bit 0 position. */ ++#define TC4_CCCINTLVL1_bm (1<<5) /* Channel C Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC4_CCCINTLVL1_bp 5 /* Channel C Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC4_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ ++#define TC4_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ ++#define TC4_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC4_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ ++#define TC4_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC4_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC4_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ ++#define TC4_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ ++#define TC4_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC4_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ ++#define TC4_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC4_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC4_LCCDINTLVL_gm 0xC0 /* Channel Low D Compare or Capture Interrupt Level group mask. */ ++#define TC4_LCCDINTLVL_gp 6 /* Channel Low D Compare or Capture Interrupt Level group position. */ ++#define TC4_LCCDINTLVL0_bm (1<<6) /* Channel Low D Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC4_LCCDINTLVL0_bp 6 /* Channel Low D Compare or Capture Interrupt Level bit 0 position. */ ++#define TC4_LCCDINTLVL1_bm (1<<7) /* Channel Low D Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC4_LCCDINTLVL1_bp 7 /* Channel Low D Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC4_LCCCINTLVL_gm 0x30 /* Channel Low C Compare or Capture Interrupt Level group mask. */ ++#define TC4_LCCCINTLVL_gp 4 /* Channel Low C Compare or Capture Interrupt Level group position. */ ++#define TC4_LCCCINTLVL0_bm (1<<4) /* Channel Low C Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC4_LCCCINTLVL0_bp 4 /* Channel Low C Compare or Capture Interrupt Level bit 0 position. */ ++#define TC4_LCCCINTLVL1_bm (1<<5) /* Channel Low C Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC4_LCCCINTLVL1_bp 5 /* Channel Low C Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC4_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ ++#define TC4_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ ++#define TC4_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC4_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ ++#define TC4_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC4_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC4_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ ++#define TC4_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ ++#define TC4_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC4_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ ++#define TC4_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC4_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ ++ ++/* TC4.CTRLGCLR bit masks and bit positions */ ++#define TC4_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ ++#define TC4_STOP_bp 5 /* Timer/Counter Stop bit position. */ ++ ++#define TC4_CMD_gm 0x0C /* Command group mask. */ ++#define TC4_CMD_gp 2 /* Command group position. */ ++#define TC4_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC4_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC4_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC4_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC4_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC4_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC4_DIR_bm 0x01 /* Counter Direction bit mask. */ ++#define TC4_DIR_bp 0 /* Counter Direction bit position. */ ++ ++/* TC4.CTRLGSET bit masks and bit positions */ ++/* TC4_STOP Predefined. */ ++/* TC4_STOP Predefined. */ ++ ++/* TC4_CMD Predefined. */ ++/* TC4_CMD Predefined. */ ++ ++/* TC4_LUPD Predefined. */ ++/* TC4_LUPD Predefined. */ ++ ++/* TC4_DIR Predefined. */ ++/* TC4_DIR Predefined. */ ++ ++/* TC4.CTRLHCLR bit masks and bit positions */ ++#define TC4_CCDBV_bm 0x10 /* Channel D Compare or Capture Buffer Valid bit mask. */ ++#define TC4_CCDBV_bp 4 /* Channel D Compare or Capture Buffer Valid bit position. */ ++ ++#define TC4_CCCBV_bm 0x08 /* Channel C Compare or Capture Buffer Valid bit mask. */ ++#define TC4_CCCBV_bp 3 /* Channel C Compare or Capture Buffer Valid bit position. */ ++ ++#define TC4_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ ++#define TC4_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ ++ ++#define TC4_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ ++#define TC4_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ ++ ++#define TC4_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC4_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++#define TC4_LCCDBV_bm 0x10 /* Channel Low D Compare or Capture Buffer Valid bit mask. */ ++#define TC4_LCCDBV_bp 4 /* Channel Low D Compare or Capture Buffer Valid bit position. */ ++ ++#define TC4_LCCCBV_bm 0x08 /* Channel Low C Compare or Capture Buffer Valid bit mask. */ ++#define TC4_LCCCBV_bp 3 /* Channel Low C Compare or Capture Buffer Valid bit position. */ ++ ++#define TC4_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ ++#define TC4_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ ++ ++#define TC4_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ ++#define TC4_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ ++ ++#define TC4_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ ++#define TC4_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ ++ ++/* TC4.CTRLHSET bit masks and bit positions */ ++/* TC4_CCDBV Predefined. */ ++/* TC4_CCDBV Predefined. */ ++ ++/* TC4_CCCBV Predefined. */ ++/* TC4_CCCBV Predefined. */ ++ ++/* TC4_CCBBV Predefined. */ ++/* TC4_CCBBV Predefined. */ ++ ++/* TC4_CCABV Predefined. */ ++/* TC4_CCABV Predefined. */ ++ ++/* TC4_PERBV Predefined. */ ++/* TC4_PERBV Predefined. */ ++ ++/* TC4_LCCDBV Predefined. */ ++/* TC4_LCCDBV Predefined. */ ++ ++/* TC4_LCCCBV Predefined. */ ++/* TC4_LCCCBV Predefined. */ ++ ++/* TC4_LCCBBV Predefined. */ ++/* TC4_LCCBBV Predefined. */ ++ ++/* TC4_LCCABV Predefined. */ ++/* TC4_LCCABV Predefined. */ ++ ++/* TC4_LPERBV Predefined. */ ++/* TC4_LPERBV Predefined. */ ++ ++/* TC4.INTFLAGS bit masks and bit positions */ ++#define TC4_CCDIF_bm 0x80 /* Channel D Compare or Capture Interrupt Flag bit mask. */ ++#define TC4_CCDIF_bp 7 /* Channel D Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC4_CCCIF_bm 0x40 /* Channel C Compare or Capture Interrupt Flag bit mask. */ ++#define TC4_CCCIF_bp 6 /* Channel C Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC4_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ ++#define TC4_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC4_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ ++#define TC4_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC4_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ ++#define TC4_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ ++ ++#define TC4_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC4_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC4_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ ++#define TC4_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ ++ ++#define TC4_LCCDIF_bm 0x80 /* Channel Low D Compare or Capture Interrupt Flag bit mask. */ ++#define TC4_LCCDIF_bp 7 /* Channel Low D Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC4_LCCCIF_bm 0x40 /* Channel Low C Compare or Capture Interrupt Flag bit mask. */ ++#define TC4_LCCCIF_bp 6 /* Channel Low C Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC4_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ ++#define TC4_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC4_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ ++#define TC4_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ ++ ++/* TC5.CTRLA bit masks and bit positions */ ++#define TC5_SYNCHEN_bm 0x40 /* Synchronization Enabled bit mask. */ ++#define TC5_SYNCHEN_bp 6 /* Synchronization Enabled bit position. */ ++ ++#define TC5_EVSTART_bm 0x20 /* Start on Next Event bit mask. */ ++#define TC5_EVSTART_bp 5 /* Start on Next Event bit position. */ ++ ++#define TC5_UPSTOP_bm 0x10 /* Stop on Next Update bit mask. */ ++#define TC5_UPSTOP_bp 4 /* Stop on Next Update bit position. */ ++ ++#define TC5_CLKSEL_gm 0x0F /* Clock Select group mask. */ ++#define TC5_CLKSEL_gp 0 /* Clock Select group position. */ ++#define TC5_CLKSEL0_bm (1<<0) /* Clock Select bit 0 mask. */ ++#define TC5_CLKSEL0_bp 0 /* Clock Select bit 0 position. */ ++#define TC5_CLKSEL1_bm (1<<1) /* Clock Select bit 1 mask. */ ++#define TC5_CLKSEL1_bp 1 /* Clock Select bit 1 position. */ ++#define TC5_CLKSEL2_bm (1<<2) /* Clock Select bit 2 mask. */ ++#define TC5_CLKSEL2_bp 2 /* Clock Select bit 2 position. */ ++#define TC5_CLKSEL3_bm (1<<3) /* Clock Select bit 3 mask. */ ++#define TC5_CLKSEL3_bp 3 /* Clock Select bit 3 position. */ ++ ++/* TC5.CTRLB bit masks and bit positions */ ++#define TC5_BYTEM_gm 0xC0 /* Byte Mode group mask. */ ++#define TC5_BYTEM_gp 6 /* Byte Mode group position. */ ++#define TC5_BYTEM0_bm (1<<6) /* Byte Mode bit 0 mask. */ ++#define TC5_BYTEM0_bp 6 /* Byte Mode bit 0 position. */ ++#define TC5_BYTEM1_bm (1<<7) /* Byte Mode bit 1 mask. */ ++#define TC5_BYTEM1_bp 7 /* Byte Mode bit 1 position. */ ++ ++#define TC5_CIRCEN_gm 0x30 /* Circular Buffer Enable group mask. */ ++#define TC5_CIRCEN_gp 4 /* Circular Buffer Enable group position. */ ++#define TC5_CIRCEN0_bm (1<<4) /* Circular Buffer Enable bit 0 mask. */ ++#define TC5_CIRCEN0_bp 4 /* Circular Buffer Enable bit 0 position. */ ++#define TC5_CIRCEN1_bm (1<<5) /* Circular Buffer Enable bit 1 mask. */ ++#define TC5_CIRCEN1_bp 5 /* Circular Buffer Enable bit 1 position. */ ++ ++#define TC5_WGMODE_gm 0x07 /* Waveform Generation Mode group mask. */ ++#define TC5_WGMODE_gp 0 /* Waveform Generation Mode group position. */ ++#define TC5_WGMODE0_bm (1<<0) /* Waveform Generation Mode bit 0 mask. */ ++#define TC5_WGMODE0_bp 0 /* Waveform Generation Mode bit 0 position. */ ++#define TC5_WGMODE1_bm (1<<1) /* Waveform Generation Mode bit 1 mask. */ ++#define TC5_WGMODE1_bp 1 /* Waveform Generation Mode bit 1 position. */ ++#define TC5_WGMODE2_bm (1<<2) /* Waveform Generation Mode bit 2 mask. */ ++#define TC5_WGMODE2_bp 2 /* Waveform Generation Mode bit 2 position. */ ++ ++/* TC5.CTRLC bit masks and bit positions */ ++#define TC5_POLB_bm 0x20 /* Channel B Output Polarity bit mask. */ ++#define TC5_POLB_bp 5 /* Channel B Output Polarity bit position. */ ++ ++#define TC5_POLA_bm 0x10 /* Channel A Output Polarity bit mask. */ ++#define TC5_POLA_bp 4 /* Channel A Output Polarity bit position. */ ++ ++#define TC5_CMPB_bm 0x02 /* Channel B Compare Output Value bit mask. */ ++#define TC5_CMPB_bp 1 /* Channel B Compare Output Value bit position. */ ++ ++#define TC5_CMPA_bm 0x01 /* Channel A Compare Output Value bit mask. */ ++#define TC5_CMPA_bp 0 /* Channel A Compare Output Value bit position. */ ++ ++#define TC5_HCMPB_bm 0x20 /* High Channel B Compare Output Value bit mask. */ ++#define TC5_HCMPB_bp 5 /* High Channel B Compare Output Value bit position. */ ++ ++#define TC5_HCMPA_bm 0x10 /* High Channel A Compare Output Value bit mask. */ ++#define TC5_HCMPA_bp 4 /* High Channel A Compare Output Value bit position. */ ++ ++#define TC5_LCMPB_bm 0x02 /* Low Channel B Compare Output Value bit mask. */ ++#define TC5_LCMPB_bp 1 /* Low Channel B Compare Output Value bit position. */ ++ ++#define TC5_LCMPA_bm 0x01 /* Low Channel A Compare Output Value bit mask. */ ++#define TC5_LCMPA_bp 0 /* Low Channel A Compare Output Value bit position. */ ++ ++/* TC5.CTRLD bit masks and bit positions */ ++#define TC5_EVACT_gm 0xE0 /* Event Action group mask. */ ++#define TC5_EVACT_gp 5 /* Event Action group position. */ ++#define TC5_EVACT0_bm (1<<5) /* Event Action bit 0 mask. */ ++#define TC5_EVACT0_bp 5 /* Event Action bit 0 position. */ ++#define TC5_EVACT1_bm (1<<6) /* Event Action bit 1 mask. */ ++#define TC5_EVACT1_bp 6 /* Event Action bit 1 position. */ ++#define TC5_EVACT2_bm (1<<7) /* Event Action bit 2 mask. */ ++#define TC5_EVACT2_bp 7 /* Event Action bit 2 position. */ ++ ++#define TC5_EVDLY_bm 0x10 /* Event Delay bit mask. */ ++#define TC5_EVDLY_bp 4 /* Event Delay bit position. */ ++ ++#define TC5_EVSEL_gm 0x0F /* Event Source Select group mask. */ ++#define TC5_EVSEL_gp 0 /* Event Source Select group position. */ ++#define TC5_EVSEL0_bm (1<<0) /* Event Source Select bit 0 mask. */ ++#define TC5_EVSEL0_bp 0 /* Event Source Select bit 0 position. */ ++#define TC5_EVSEL1_bm (1<<1) /* Event Source Select bit 1 mask. */ ++#define TC5_EVSEL1_bp 1 /* Event Source Select bit 1 position. */ ++#define TC5_EVSEL2_bm (1<<2) /* Event Source Select bit 2 mask. */ ++#define TC5_EVSEL2_bp 2 /* Event Source Select bit 2 position. */ ++#define TC5_EVSEL3_bm (1<<3) /* Event Source Select bit 3 mask. */ ++#define TC5_EVSEL3_bp 3 /* Event Source Select bit 3 position. */ ++ ++/* TC5.CTRLE bit masks and bit positions */ ++#define TC5_CCBMODE_gm 0x0C /* Channel B Compare or Capture Mode group mask. */ ++#define TC5_CCBMODE_gp 2 /* Channel B Compare or Capture Mode group position. */ ++#define TC5_CCBMODE0_bm (1<<2) /* Channel B Compare or Capture Mode bit 0 mask. */ ++#define TC5_CCBMODE0_bp 2 /* Channel B Compare or Capture Mode bit 0 position. */ ++#define TC5_CCBMODE1_bm (1<<3) /* Channel B Compare or Capture Mode bit 1 mask. */ ++#define TC5_CCBMODE1_bp 3 /* Channel B Compare or Capture Mode bit 1 position. */ ++ ++#define TC5_CCAMODE_gm 0x03 /* Channel A Compare or Capture Mode group mask. */ ++#define TC5_CCAMODE_gp 0 /* Channel A Compare or Capture Mode group position. */ ++#define TC5_CCAMODE0_bm (1<<0) /* Channel A Compare or Capture Mode bit 0 mask. */ ++#define TC5_CCAMODE0_bp 0 /* Channel A Compare or Capture Mode bit 0 position. */ ++#define TC5_CCAMODE1_bm (1<<1) /* Channel A Compare or Capture Mode bit 1 mask. */ ++#define TC5_CCAMODE1_bp 1 /* Channel A Compare or Capture Mode bit 1 position. */ ++ ++#define TC5_LCCBMODE_gm 0x0C /* Channel Low B Compare or Capture Mode group mask. */ ++#define TC5_LCCBMODE_gp 2 /* Channel Low B Compare or Capture Mode group position. */ ++#define TC5_LCCBMODE0_bm (1<<2) /* Channel Low B Compare or Capture Mode bit 0 mask. */ ++#define TC5_LCCBMODE0_bp 2 /* Channel Low B Compare or Capture Mode bit 0 position. */ ++#define TC5_LCCBMODE1_bm (1<<3) /* Channel Low B Compare or Capture Mode bit 1 mask. */ ++#define TC5_LCCBMODE1_bp 3 /* Channel Low B Compare or Capture Mode bit 1 position. */ ++ ++#define TC5_LCCAMODE_gm 0x03 /* Channel Low A Compare or Capture Mode group mask. */ ++#define TC5_LCCAMODE_gp 0 /* Channel Low A Compare or Capture Mode group position. */ ++#define TC5_LCCAMODE0_bm (1<<0) /* Channel Low A Compare or Capture Mode bit 0 mask. */ ++#define TC5_LCCAMODE0_bp 0 /* Channel Low A Compare or Capture Mode bit 0 position. */ ++#define TC5_LCCAMODE1_bm (1<<1) /* Channel Low A Compare or Capture Mode bit 1 mask. */ ++#define TC5_LCCAMODE1_bp 1 /* Channel Low A Compare or Capture Mode bit 1 position. */ ++ ++/* TC5.CTRLF bit masks and bit positions */ ++#define TC5_HCCBMODE_gm 0x0C /* Channel High B Compare or Capture Mode group mask. */ ++#define TC5_HCCBMODE_gp 2 /* Channel High B Compare or Capture Mode group position. */ ++#define TC5_HCCBMODE0_bm (1<<2) /* Channel High B Compare or Capture Mode bit 0 mask. */ ++#define TC5_HCCBMODE0_bp 2 /* Channel High B Compare or Capture Mode bit 0 position. */ ++#define TC5_HCCBMODE1_bm (1<<3) /* Channel High B Compare or Capture Mode bit 1 mask. */ ++#define TC5_HCCBMODE1_bp 3 /* Channel High B Compare or Capture Mode bit 1 position. */ ++ ++#define TC5_HCCAMODE_gm 0x03 /* Channel High A Compare or Capture Mode group mask. */ ++#define TC5_HCCAMODE_gp 0 /* Channel High A Compare or Capture Mode group position. */ ++#define TC5_HCCAMODE0_bm (1<<0) /* Channel High A Compare or Capture Mode bit 0 mask. */ ++#define TC5_HCCAMODE0_bp 0 /* Channel High A Compare or Capture Mode bit 0 position. */ ++#define TC5_HCCAMODE1_bm (1<<1) /* Channel High A Compare or Capture Mode bit 1 mask. */ ++#define TC5_HCCAMODE1_bp 1 /* Channel High A Compare or Capture Mode bit 1 position. */ ++ ++/* TC5.INTCTRLA bit masks and bit positions */ ++#define TC5_TRGINTLVL_gm 0x30 /* Timer Trigger Restart Interrupt Level group mask. */ ++#define TC5_TRGINTLVL_gp 4 /* Timer Trigger Restart Interrupt Level group position. */ ++#define TC5_TRGINTLVL0_bm (1<<4) /* Timer Trigger Restart Interrupt Level bit 0 mask. */ ++#define TC5_TRGINTLVL0_bp 4 /* Timer Trigger Restart Interrupt Level bit 0 position. */ ++#define TC5_TRGINTLVL1_bm (1<<5) /* Timer Trigger Restart Interrupt Level bit 1 mask. */ ++#define TC5_TRGINTLVL1_bp 5 /* Timer Trigger Restart Interrupt Level bit 1 position. */ ++ ++#define TC5_ERRINTLVL_gm 0x0C /* Timer Error Interrupt Level group mask. */ ++#define TC5_ERRINTLVL_gp 2 /* Timer Error Interrupt Level group position. */ ++#define TC5_ERRINTLVL0_bm (1<<2) /* Timer Error Interrupt Level bit 0 mask. */ ++#define TC5_ERRINTLVL0_bp 2 /* Timer Error Interrupt Level bit 0 position. */ ++#define TC5_ERRINTLVL1_bm (1<<3) /* Timer Error Interrupt Level bit 1 mask. */ ++#define TC5_ERRINTLVL1_bp 3 /* Timer Error Interrupt Level bit 1 position. */ ++ ++#define TC5_OVFINTLVL_gm 0x03 /* Timer Overflow/Underflow Interrupt Level group mask. */ ++#define TC5_OVFINTLVL_gp 0 /* Timer Overflow/Underflow Interrupt Level group position. */ ++#define TC5_OVFINTLVL0_bm (1<<0) /* Timer Overflow/Underflow Interrupt Level bit 0 mask. */ ++#define TC5_OVFINTLVL0_bp 0 /* Timer Overflow/Underflow Interrupt Level bit 0 position. */ ++#define TC5_OVFINTLVL1_bm (1<<1) /* Timer Overflow/Underflow Interrupt Level bit 1 mask. */ ++#define TC5_OVFINTLVL1_bp 1 /* Timer Overflow/Underflow Interrupt Level bit 1 position. */ ++ ++/* TC5.INTCTRLB bit masks and bit positions */ ++#define TC5_CCBINTLVL_gm 0x0C /* Channel B Compare or Capture Interrupt Level group mask. */ ++#define TC5_CCBINTLVL_gp 2 /* Channel B Compare or Capture Interrupt Level group position. */ ++#define TC5_CCBINTLVL0_bm (1<<2) /* Channel B Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC5_CCBINTLVL0_bp 2 /* Channel B Compare or Capture Interrupt Level bit 0 position. */ ++#define TC5_CCBINTLVL1_bm (1<<3) /* Channel B Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC5_CCBINTLVL1_bp 3 /* Channel B Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC5_CCAINTLVL_gm 0x03 /* Channel A Compare or Capture Interrupt Level group mask. */ ++#define TC5_CCAINTLVL_gp 0 /* Channel A Compare or Capture Interrupt Level group position. */ ++#define TC5_CCAINTLVL0_bm (1<<0) /* Channel A Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC5_CCAINTLVL0_bp 0 /* Channel A Compare or Capture Interrupt Level bit 0 position. */ ++#define TC5_CCAINTLVL1_bm (1<<1) /* Channel A Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC5_CCAINTLVL1_bp 1 /* Channel A Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC5_LCCBINTLVL_gm 0x0C /* Channel Low B Compare or Capture Interrupt Level group mask. */ ++#define TC5_LCCBINTLVL_gp 2 /* Channel Low B Compare or Capture Interrupt Level group position. */ ++#define TC5_LCCBINTLVL0_bm (1<<2) /* Channel Low B Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC5_LCCBINTLVL0_bp 2 /* Channel Low B Compare or Capture Interrupt Level bit 0 position. */ ++#define TC5_LCCBINTLVL1_bm (1<<3) /* Channel Low B Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC5_LCCBINTLVL1_bp 3 /* Channel Low B Compare or Capture Interrupt Level bit 1 position. */ ++ ++#define TC5_LCCAINTLVL_gm 0x03 /* Channel Low A Compare or Capture Interrupt Level group mask. */ ++#define TC5_LCCAINTLVL_gp 0 /* Channel Low A Compare or Capture Interrupt Level group position. */ ++#define TC5_LCCAINTLVL0_bm (1<<0) /* Channel Low A Compare or Capture Interrupt Level bit 0 mask. */ ++#define TC5_LCCAINTLVL0_bp 0 /* Channel Low A Compare or Capture Interrupt Level bit 0 position. */ ++#define TC5_LCCAINTLVL1_bm (1<<1) /* Channel Low A Compare or Capture Interrupt Level bit 1 mask. */ ++#define TC5_LCCAINTLVL1_bp 1 /* Channel Low A Compare or Capture Interrupt Level bit 1 position. */ ++ ++/* TC5.CTRLGCLR bit masks and bit positions */ ++#define TC5_STOP_bm 0x20 /* Timer/Counter Stop bit mask. */ ++#define TC5_STOP_bp 5 /* Timer/Counter Stop bit position. */ ++ ++#define TC5_CMD_gm 0x0C /* Command group mask. */ ++#define TC5_CMD_gp 2 /* Command group position. */ ++#define TC5_CMD0_bm (1<<2) /* Command bit 0 mask. */ ++#define TC5_CMD0_bp 2 /* Command bit 0 position. */ ++#define TC5_CMD1_bm (1<<3) /* Command bit 1 mask. */ ++#define TC5_CMD1_bp 3 /* Command bit 1 position. */ ++ ++#define TC5_LUPD_bm 0x02 /* Lock Update bit mask. */ ++#define TC5_LUPD_bp 1 /* Lock Update bit position. */ ++ ++#define TC5_DIR_bm 0x01 /* Counter Direction bit mask. */ ++#define TC5_DIR_bp 0 /* Counter Direction bit position. */ ++ ++/* TC5.CTRLGSET bit masks and bit positions */ ++/* TC5_STOP Predefined. */ ++/* TC5_STOP Predefined. */ ++ ++/* TC5_CMD Predefined. */ ++/* TC5_CMD Predefined. */ ++ ++/* TC5_LUPD Predefined. */ ++/* TC5_LUPD Predefined. */ ++ ++/* TC5_DIR Predefined. */ ++/* TC5_DIR Predefined. */ ++ ++/* TC5.CTRLHCLR bit masks and bit positions */ ++#define TC5_CCBBV_bm 0x04 /* Channel B Compare or Capture Buffer Valid bit mask. */ ++#define TC5_CCBBV_bp 2 /* Channel B Compare or Capture Buffer Valid bit position. */ ++ ++#define TC5_CCABV_bm 0x02 /* Channel A Compare or Capture Buffer Valid bit mask. */ ++#define TC5_CCABV_bp 1 /* Channel A Compare or Capture Buffer Valid bit position. */ ++ ++#define TC5_PERBV_bm 0x01 /* Period Buffer Valid bit mask. */ ++#define TC5_PERBV_bp 0 /* Period Buffer Valid bit position. */ ++ ++#define TC5_LCCBBV_bm 0x04 /* Channel Low B Compare or Capture Buffer Valid bit mask. */ ++#define TC5_LCCBBV_bp 2 /* Channel Low B Compare or Capture Buffer Valid bit position. */ ++ ++#define TC5_LCCABV_bm 0x02 /* Channel Low A Compare or Capture Buffer Valid bit mask. */ ++#define TC5_LCCABV_bp 1 /* Channel Low A Compare or Capture Buffer Valid bit position. */ ++ ++#define TC5_LPERBV_bm 0x01 /* Period Low Buffer Valid bit mask. */ ++#define TC5_LPERBV_bp 0 /* Period Low Buffer Valid bit position. */ ++ ++/* TC5.CTRLHSET bit masks and bit positions */ ++/* TC5_CCBBV Predefined. */ ++/* TC5_CCBBV Predefined. */ ++ ++/* TC5_CCABV Predefined. */ ++/* TC5_CCABV Predefined. */ ++ ++/* TC5_PERBV Predefined. */ ++/* TC5_PERBV Predefined. */ ++ ++/* TC5_LCCBBV Predefined. */ ++/* TC5_LCCBBV Predefined. */ ++ ++/* TC5_LCCABV Predefined. */ ++/* TC5_LCCABV Predefined. */ ++ ++/* TC5_LPERBV Predefined. */ ++/* TC5_LPERBV Predefined. */ ++ ++/* TC5.INTFLAGS bit masks and bit positions */ ++#define TC5_CCBIF_bm 0x20 /* Channel B Compare or Capture Interrupt Flag bit mask. */ ++#define TC5_CCBIF_bp 5 /* Channel B Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC5_CCAIF_bm 0x10 /* Channel A Compare or Capture Interrupt Flag bit mask. */ ++#define TC5_CCAIF_bp 4 /* Channel A Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC5_TRGIF_bm 0x04 /* Trigger Restart Interrupt Flag bit mask. */ ++#define TC5_TRGIF_bp 2 /* Trigger Restart Interrupt Flag bit position. */ ++ ++#define TC5_ERRIF_bm 0x02 /* Error Interrupt Flag bit mask. */ ++#define TC5_ERRIF_bp 1 /* Error Interrupt Flag bit position. */ ++ ++#define TC5_OVFIF_bm 0x01 /* Overflow/Underflow Interrupt Flag bit mask. */ ++#define TC5_OVFIF_bp 0 /* Overflow/Underflow Interrupt Flag bit position. */ ++ ++#define TC5_LCCBIF_bm 0x20 /* Channel Low B Compare or Capture Interrupt Flag bit mask. */ ++#define TC5_LCCBIF_bp 5 /* Channel Low B Compare or Capture Interrupt Flag bit position. */ ++ ++#define TC5_LCCAIF_bm 0x10 /* Channel Low A Compare or Capture Interrupt Flag bit mask. */ ++#define TC5_LCCAIF_bp 4 /* Channel Low A Compare or Capture Interrupt Flag bit position. */ ++ ++/* FAULT - Fault Extension */ ++/* FAULT.CTRLA bit masks and bit positions */ ++#define FAULT_RAMP_gm 0xC0 /* Ramp Mode Selection group mask. */ ++#define FAULT_RAMP_gp 6 /* Ramp Mode Selection group position. */ ++#define FAULT_RAMP0_bm (1<<6) /* Ramp Mode Selection bit 0 mask. */ ++#define FAULT_RAMP0_bp 6 /* Ramp Mode Selection bit 0 position. */ ++#define FAULT_RAMP1_bm (1<<7) /* Ramp Mode Selection bit 1 mask. */ ++#define FAULT_RAMP1_bp 7 /* Ramp Mode Selection bit 1 position. */ ++ ++#define FAULT_FDDBD_bm 0x20 /* Fault on Debug Break Detection bit mask. */ ++#define FAULT_FDDBD_bp 5 /* Fault on Debug Break Detection bit position. */ ++ ++#define FAULT_PORTCTRL_bm 0x10 /* Port Control Mode bit mask. */ ++#define FAULT_PORTCTRL_bp 4 /* Port Control Mode bit position. */ ++ ++#define FAULT_FUSE_bm 0x08 /* Fuse State bit mask. */ ++#define FAULT_FUSE_bp 3 /* Fuse State bit position. */ ++ ++#define FAULT_FILTERE_bm 0x04 /* Fault E Digital Filter Selection bit mask. */ ++#define FAULT_FILTERE_bp 2 /* Fault E Digital Filter Selection bit position. */ ++ ++#define FAULT_SRCE_gm 0x03 /* Fault E Input selection group mask. */ ++#define FAULT_SRCE_gp 0 /* Fault E Input selection group position. */ ++#define FAULT_SRCE0_bm (1<<0) /* Fault E Input selection bit 0 mask. */ ++#define FAULT_SRCE0_bp 0 /* Fault E Input selection bit 0 position. */ ++#define FAULT_SRCE1_bm (1<<1) /* Fault E Input selection bit 1 mask. */ ++#define FAULT_SRCE1_bp 1 /* Fault E Input selection bit 1 position. */ ++ ++/* FAULT.CTRLB bit masks and bit positions */ ++#define FAULT_SOFTA_bm 0x80 /* Fault A Software Mode bit mask. */ ++#define FAULT_SOFTA_bp 7 /* Fault A Software Mode bit position. */ ++ ++#define FAULT_HALTA_gm 0x60 /* Fault A Halt Action group mask. */ ++#define FAULT_HALTA_gp 5 /* Fault A Halt Action group position. */ ++#define FAULT_HALTA0_bm (1<<5) /* Fault A Halt Action bit 0 mask. */ ++#define FAULT_HALTA0_bp 5 /* Fault A Halt Action bit 0 position. */ ++#define FAULT_HALTA1_bm (1<<6) /* Fault A Halt Action bit 1 mask. */ ++#define FAULT_HALTA1_bp 6 /* Fault A Halt Action bit 1 position. */ ++ ++#define FAULT_RESTARTA_bm 0x10 /* Fault A Restart Action bit mask. */ ++#define FAULT_RESTARTA_bp 4 /* Fault A Restart Action bit position. */ ++ ++#define FAULT_KEEPA_bm 0x08 /* Fault A Keep Action bit mask. */ ++#define FAULT_KEEPA_bp 3 /* Fault A Keep Action bit position. */ ++ ++#define FAULT_SRCA_gm 0x03 /* Fault A Source Selection group mask. */ ++#define FAULT_SRCA_gp 0 /* Fault A Source Selection group position. */ ++#define FAULT_SRCA0_bm (1<<0) /* Fault A Source Selection bit 0 mask. */ ++#define FAULT_SRCA0_bp 0 /* Fault A Source Selection bit 0 position. */ ++#define FAULT_SRCA1_bm (1<<1) /* Fault A Source Selection bit 1 mask. */ ++#define FAULT_SRCA1_bp 1 /* Fault A Source Selection bit 1 position. */ ++ ++/* FAULT.CTRLC bit masks and bit positions */ ++#define FAULT_CAPTA_bm 0x20 /* Fault A Capture bit mask. */ ++#define FAULT_CAPTA_bp 5 /* Fault A Capture bit position. */ ++ ++#define FAULT_FILTERA_bm 0x04 /* Fault A Digital Filter Selection bit mask. */ ++#define FAULT_FILTERA_bp 2 /* Fault A Digital Filter Selection bit position. */ ++ ++#define FAULT_BLANKA_bm 0x02 /* Fault A Blanking bit mask. */ ++#define FAULT_BLANKA_bp 1 /* Fault A Blanking bit position. */ ++ ++#define FAULT_QUALA_bm 0x01 /* Fault A Qualification bit mask. */ ++#define FAULT_QUALA_bp 0 /* Fault A Qualification bit position. */ ++ ++/* FAULT.CTRLD bit masks and bit positions */ ++#define FAULT_SOFTB_bm 0x80 /* Fault B Software Mode bit mask. */ ++#define FAULT_SOFTB_bp 7 /* Fault B Software Mode bit position. */ ++ ++#define FAULT_HALTB_gm 0x60 /* Fault B Halt Action group mask. */ ++#define FAULT_HALTB_gp 5 /* Fault B Halt Action group position. */ ++#define FAULT_HALTB0_bm (1<<5) /* Fault B Halt Action bit 0 mask. */ ++#define FAULT_HALTB0_bp 5 /* Fault B Halt Action bit 0 position. */ ++#define FAULT_HALTB1_bm (1<<6) /* Fault B Halt Action bit 1 mask. */ ++#define FAULT_HALTB1_bp 6 /* Fault B Halt Action bit 1 position. */ ++ ++#define FAULT_RESTARTB_bm 0x10 /* Fault B Restart Action bit mask. */ ++#define FAULT_RESTARTB_bp 4 /* Fault B Restart Action bit position. */ ++ ++#define FAULT_KEEPB_bm 0x08 /* Fault B Keep Action bit mask. */ ++#define FAULT_KEEPB_bp 3 /* Fault B Keep Action bit position. */ ++ ++#define FAULT_SRCB_gm 0x03 /* Fault B Source Selection group mask. */ ++#define FAULT_SRCB_gp 0 /* Fault B Source Selection group position. */ ++#define FAULT_SRCB0_bm (1<<0) /* Fault B Source Selection bit 0 mask. */ ++#define FAULT_SRCB0_bp 0 /* Fault B Source Selection bit 0 position. */ ++#define FAULT_SRCB1_bm (1<<1) /* Fault B Source Selection bit 1 mask. */ ++#define FAULT_SRCB1_bp 1 /* Fault B Source Selection bit 1 position. */ ++ ++/* FAULT.CTRLE bit masks and bit positions */ ++#define FAULT_CAPTB_bm 0x20 /* Fault B Capture bit mask. */ ++#define FAULT_CAPTB_bp 5 /* Fault B Capture bit position. */ ++ ++#define FAULT_FILTERB_bm 0x04 /* Fault B Digital Filter Selection bit mask. */ ++#define FAULT_FILTERB_bp 2 /* Fault B Digital Filter Selection bit position. */ ++ ++#define FAULT_BLANKB_bm 0x02 /* Fault B Blanking bit mask. */ ++#define FAULT_BLANKB_bp 1 /* Fault B Blanking bit position. */ ++ ++#define FAULT_QUALB_bm 0x01 /* Fault B Qualification bit mask. */ ++#define FAULT_QUALB_bp 0 /* Fault B Qualification bit position. */ ++ ++/* FAULT.STATUS bit masks and bit positions */ ++#define FAULT_STATEB_bm 0x80 /* Fault B State bit mask. */ ++#define FAULT_STATEB_bp 7 /* Fault B State bit position. */ ++ ++#define FAULT_STATEA_bm 0x40 /* Fault A State bit mask. */ ++#define FAULT_STATEA_bp 6 /* Fault A State bit position. */ ++ ++#define FAULT_STATEE_bm 0x20 /* Fault E State bit mask. */ ++#define FAULT_STATEE_bp 5 /* Fault E State bit position. */ ++ ++#define FAULT_IDX_bm 0x08 /* Channel Index Flag bit mask. */ ++#define FAULT_IDX_bp 3 /* Channel Index Flag bit position. */ ++ ++#define FAULT_FAULTBIN_bm 0x04 /* Fault B Flag bit mask. */ ++#define FAULT_FAULTBIN_bp 2 /* Fault B Flag bit position. */ ++ ++#define FAULT_FAULTAIN_bm 0x02 /* Fault A Flag bit mask. */ ++#define FAULT_FAULTAIN_bp 1 /* Fault A Flag bit position. */ ++ ++#define FAULT_FAULTEIN_bm 0x01 /* Fault E Flag bit mask. */ ++#define FAULT_FAULTEIN_bp 0 /* Fault E Flag bit position. */ ++ ++/* FAULT.CTRLGCLR bit masks and bit positions */ ++#define FAULT_HALTBCLR_bm 0x80 /* State B Clear bit mask. */ ++#define FAULT_HALTBCLR_bp 7 /* State B Clear bit position. */ ++ ++#define FAULT_HALTACLR_bm 0x40 /* State A Clear bit mask. */ ++#define FAULT_HALTACLR_bp 6 /* State A Clear bit position. */ ++ ++#define FAULT_STATEECLR_bm 0x20 /* State E Clear bit mask. */ ++#define FAULT_STATEECLR_bp 5 /* State E Clear bit position. */ ++ ++#define FAULT_FAULTB_bm 0x04 /* Fault B Flag bit mask. */ ++#define FAULT_FAULTB_bp 2 /* Fault B Flag bit position. */ ++ ++#define FAULT_FAULTA_bm 0x02 /* Fault A Flag bit mask. */ ++#define FAULT_FAULTA_bp 1 /* Fault A Flag bit position. */ ++ ++#define FAULT_FAULTE_bm 0x01 /* Fault E Flag bit mask. */ ++#define FAULT_FAULTE_bp 0 /* Fault E Flag bit position. */ ++ ++/* FAULT.CTRLGSET bit masks and bit positions */ ++#define FAULT_FAULTBSW_bm 0x80 /* Software Fault B bit mask. */ ++#define FAULT_FAULTBSW_bp 7 /* Software Fault B bit position. */ ++ ++#define FAULT_FAULTASW_bm 0x40 /* Software Fault A bit mask. */ ++#define FAULT_FAULTASW_bp 6 /* Software Fault A bit position. */ ++ ++#define FAULT_FAULTESW_bm 0x20 /* Software Fault E bit mask. */ ++#define FAULT_FAULTESW_bp 5 /* Software Fault E bit position. */ ++ ++#define FAULT_IDXCMD_gm 0x18 /* Channel index Command group mask. */ ++#define FAULT_IDXCMD_gp 3 /* Channel index Command group position. */ ++#define FAULT_IDXCMD0_bm (1<<3) /* Channel index Command bit 0 mask. */ ++#define FAULT_IDXCMD0_bp 3 /* Channel index Command bit 0 position. */ ++#define FAULT_IDXCMD1_bm (1<<4) /* Channel index Command bit 1 mask. */ ++#define FAULT_IDXCMD1_bp 4 /* Channel index Command bit 1 position. */ ++ ++/* WEX - Waveform Extension */ ++/* WEX.CTRL bit masks and bit positions */ ++#define WEX_UPSEL_bm 0x80 /* Update Source Selection bit mask. */ ++#define WEX_UPSEL_bp 7 /* Update Source Selection bit position. */ ++ ++#define WEX_OTMX_gm 0x70 /* Output Matrix group mask. */ ++#define WEX_OTMX_gp 4 /* Output Matrix group position. */ ++#define WEX_OTMX0_bm (1<<4) /* Output Matrix bit 0 mask. */ ++#define WEX_OTMX0_bp 4 /* Output Matrix bit 0 position. */ ++#define WEX_OTMX1_bm (1<<5) /* Output Matrix bit 1 mask. */ ++#define WEX_OTMX1_bp 5 /* Output Matrix bit 1 position. */ ++#define WEX_OTMX2_bm (1<<6) /* Output Matrix bit 2 mask. */ ++#define WEX_OTMX2_bp 6 /* Output Matrix bit 2 position. */ ++ ++#define WEX_DTI3EN_bm 0x08 /* Dead-Time Insertion Generator 3 Enable bit mask. */ ++#define WEX_DTI3EN_bp 3 /* Dead-Time Insertion Generator 3 Enable bit position. */ ++ ++#define WEX_DTI2EN_bm 0x04 /* Dead-Time Insertion Generator 2 Enable bit mask. */ ++#define WEX_DTI2EN_bp 2 /* Dead-Time Insertion Generator 2 Enable bit position. */ ++ ++#define WEX_DTI1EN_bm 0x02 /* Dead-Time Insertion Generator 1 Enable bit mask. */ ++#define WEX_DTI1EN_bp 1 /* Dead-Time Insertion Generator 1 Enable bit position. */ ++ ++#define WEX_DTI0EN_bm 0x01 /* Dead-Time Insertion Generator 0 Enable bit mask. */ ++#define WEX_DTI0EN_bp 0 /* Dead-Time Insertion Generator 0 Enable bit position. */ ++ ++/* WEX.STATUSCLR bit masks and bit positions */ ++#define WEX_SWAPBUF_bm 0x04 /* Swap Buffer Valid bit mask. */ ++#define WEX_SWAPBUF_bp 2 /* Swap Buffer Valid bit position. */ ++ ++#define WEX_PGVBUFV_bm 0x02 /* Pattern Generator Value Buffer Valid bit mask. */ ++#define WEX_PGVBUFV_bp 1 /* Pattern Generator Value Buffer Valid bit position. */ ++ ++#define WEX_PGOBUFV_bm 0x01 /* Pattern Generator Overwrite Buffer Valid bit mask. */ ++#define WEX_PGOBUFV_bp 0 /* Pattern Generator Overwrite Buffer Valid bit position. */ ++ ++/* WEX.STATUSSET bit masks and bit positions */ ++/* WEX_SWAPBUF Predefined. */ ++/* WEX_SWAPBUF Predefined. */ ++ ++/* WEX_PGVBUFV Predefined. */ ++/* WEX_PGVBUFV Predefined. */ ++ ++/* WEX_PGOBUFV Predefined. */ ++/* WEX_PGOBUFV Predefined. */ ++ ++/* WEX.SWAP bit masks and bit positions */ ++#define WEX_SWAP3_bm 0x08 /* Swap DTI output pair 3 bit mask. */ ++#define WEX_SWAP3_bp 3 /* Swap DTI output pair 3 bit position. */ ++ ++#define WEX_SWAP2_bm 0x04 /* Swap DTI output pair 2 bit mask. */ ++#define WEX_SWAP2_bp 2 /* Swap DTI output pair 2 bit position. */ ++ ++#define WEX_SWAP1_bm 0x02 /* Swap DTI output pair 1 bit mask. */ ++#define WEX_SWAP1_bp 1 /* Swap DTI output pair 1 bit position. */ ++ ++#define WEX_SWAP0_bm 0x01 /* Swap DTI output pair 0 bit mask. */ ++#define WEX_SWAP0_bp 0 /* Swap DTI output pair 0 bit position. */ ++ ++/* WEX.SWAPBUF bit masks and bit positions */ ++#define WEX_SWAP3BUF_bm 0x08 /* Swap DTI output pair 3 bit mask. */ ++#define WEX_SWAP3BUF_bp 3 /* Swap DTI output pair 3 bit position. */ ++ ++#define WEX_SWAP2BUF_bm 0x04 /* Swap DTI output pair 2 bit mask. */ ++#define WEX_SWAP2BUF_bp 2 /* Swap DTI output pair 2 bit position. */ ++ ++#define WEX_SWAP1BUF_bm 0x02 /* Swap DTI output pair 1 bit mask. */ ++#define WEX_SWAP1BUF_bp 1 /* Swap DTI output pair 1 bit position. */ ++ ++#define WEX_SWAP0BUF_bm 0x01 /* Swap DTI output pair 0 bit mask. */ ++#define WEX_SWAP0BUF_bp 0 /* Swap DTI output pair 0 bit position. */ ++ ++/* HIRES - High-Resolution Extension */ ++/* HIRES.CTRLA bit masks and bit positions */ ++#define HIRES_HRPLUS_gm 0x0C /* High Resolution Plus group mask. */ ++#define HIRES_HRPLUS_gp 2 /* High Resolution Plus group position. */ ++#define HIRES_HRPLUS0_bm (1<<2) /* High Resolution Plus bit 0 mask. */ ++#define HIRES_HRPLUS0_bp 2 /* High Resolution Plus bit 0 position. */ ++#define HIRES_HRPLUS1_bm (1<<3) /* High Resolution Plus bit 1 mask. */ ++#define HIRES_HRPLUS1_bp 3 /* High Resolution Plus bit 1 position. */ ++ ++#define HIRES_HREN_gm 0x03 /* High Resolution Mode group mask. */ ++#define HIRES_HREN_gp 0 /* High Resolution Mode group position. */ ++#define HIRES_HREN0_bm (1<<0) /* High Resolution Mode bit 0 mask. */ ++#define HIRES_HREN0_bp 0 /* High Resolution Mode bit 0 position. */ ++#define HIRES_HREN1_bm (1<<1) /* High Resolution Mode bit 1 mask. */ ++#define HIRES_HREN1_bp 1 /* High Resolution Mode bit 1 position. */ ++ ++/* USART - Universal Asynchronous Receiver-Transmitter */ ++/* USART.STATUS bit masks and bit positions */ ++#define USART_RXCIF_bm 0x80 /* Receive Interrupt Flag bit mask. */ ++#define USART_RXCIF_bp 7 /* Receive Interrupt Flag bit position. */ ++ ++#define USART_TXCIF_bm 0x40 /* Transmit Interrupt Flag bit mask. */ ++#define USART_TXCIF_bp 6 /* Transmit Interrupt Flag bit position. */ ++ ++#define USART_DREIF_bm 0x20 /* Data Register Empty Flag bit mask. */ ++#define USART_DREIF_bp 5 /* Data Register Empty Flag bit position. */ ++ ++#define USART_FERR_bm 0x10 /* Frame Error bit mask. */ ++#define USART_FERR_bp 4 /* Frame Error bit position. */ ++ ++#define USART_BUFOVF_bm 0x08 /* Buffer Overflow bit mask. */ ++#define USART_BUFOVF_bp 3 /* Buffer Overflow bit position. */ ++ ++#define USART_PERR_bm 0x04 /* Parity Error bit mask. */ ++#define USART_PERR_bp 2 /* Parity Error bit position. */ ++ ++#define USART_RXSIF_bm 0x02 /* Receive Start Bit Interrupt Flag bit mask. */ ++#define USART_RXSIF_bp 1 /* Receive Start Bit Interrupt Flag bit position. */ ++ ++#define USART_RXB8_bm 0x01 /* Receive Bit 8 bit mask. */ ++#define USART_RXB8_bp 0 /* Receive Bit 8 bit position. */ ++ ++#define USART_DRIF_bm 0x01 /* Data Reception Flag bit mask. */ ++#define USART_DRIF_bp 0 /* Data Reception Flag bit position. */ ++ ++/* USART.CTRLA bit masks and bit positions */ ++#define USART_RXSIE_bm 0x80 /* Receive Start Interrupt Enable bit mask. */ ++#define USART_RXSIE_bp 7 /* Receive Start Interrupt Enable bit position. */ ++ ++#define USART_DRIE_bm 0x40 /* Data Reception Interrupt Enable bit mask. */ ++#define USART_DRIE_bp 6 /* Data Reception Interrupt Enable bit position. */ ++ ++#define USART_RXCINTLVL_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_RXCINTLVL_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_RXCINTLVL0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_RXCINTLVL0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_RXCINTLVL1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_RXCINTLVL1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_TXCINTLVL_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_TXCINTLVL_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_TXCINTLVL0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_TXCINTLVL0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_TXCINTLVL1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_TXCINTLVL1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_DREINTLVL_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_DREINTLVL_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_DREINTLVL0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_DREINTLVL0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_DREINTLVL1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_DREINTLVL1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.CTRLB bit masks and bit positions */ ++#define USART_ONEWIRE_bm 0x80 /* One Wire Mode bit mask. */ ++#define USART_ONEWIRE_bp 7 /* One Wire Mode bit position. */ ++ ++#define USART_SFDEN_bm 0x40 /* Start Frame Detection Enable bit mask. */ ++#define USART_SFDEN_bp 6 /* Start Frame Detection Enable bit position. */ ++ ++#define USART_RXEN_bm 0x10 /* Receiver Enable bit mask. */ ++#define USART_RXEN_bp 4 /* Receiver Enable bit position. */ ++ ++#define USART_TXEN_bm 0x08 /* Transmitter Enable bit mask. */ ++#define USART_TXEN_bp 3 /* Transmitter Enable bit position. */ ++ ++#define USART_CLK2X_bm 0x04 /* Double transmission speed bit mask. */ ++#define USART_CLK2X_bp 2 /* Double transmission speed bit position. */ ++ ++#define USART_MPCM_bm 0x02 /* Multi-processor Communication Mode bit mask. */ ++#define USART_MPCM_bp 1 /* Multi-processor Communication Mode bit position. */ ++ ++#define USART_TXB8_bm 0x01 /* Transmit bit 8 bit mask. */ ++#define USART_TXB8_bp 0 /* Transmit bit 8 bit position. */ ++ ++/* USART.CTRLC bit masks and bit positions */ ++#define USART_CMODE_gm 0xC0 /* Communication Mode group mask. */ ++#define USART_CMODE_gp 6 /* Communication Mode group position. */ ++#define USART_CMODE0_bm (1<<6) /* Communication Mode bit 0 mask. */ ++#define USART_CMODE0_bp 6 /* Communication Mode bit 0 position. */ ++#define USART_CMODE1_bm (1<<7) /* Communication Mode bit 1 mask. */ ++#define USART_CMODE1_bp 7 /* Communication Mode bit 1 position. */ ++ ++#define USART_PMODE_gm 0x30 /* Parity Mode group mask. */ ++#define USART_PMODE_gp 4 /* Parity Mode group position. */ ++#define USART_PMODE0_bm (1<<4) /* Parity Mode bit 0 mask. */ ++#define USART_PMODE0_bp 4 /* Parity Mode bit 0 position. */ ++#define USART_PMODE1_bm (1<<5) /* Parity Mode bit 1 mask. */ ++#define USART_PMODE1_bp 5 /* Parity Mode bit 1 position. */ ++ ++#define USART_SBMODE_bm 0x08 /* Stop Bit Mode bit mask. */ ++#define USART_SBMODE_bp 3 /* Stop Bit Mode bit position. */ ++ ++#define USART_CHSIZE_gm 0x07 /* Character Size group mask. */ ++#define USART_CHSIZE_gp 0 /* Character Size group position. */ ++#define USART_CHSIZE0_bm (1<<0) /* Character Size bit 0 mask. */ ++#define USART_CHSIZE0_bp 0 /* Character Size bit 0 position. */ ++#define USART_CHSIZE1_bm (1<<1) /* Character Size bit 1 mask. */ ++#define USART_CHSIZE1_bp 1 /* Character Size bit 1 position. */ ++#define USART_CHSIZE2_bm (1<<2) /* Character Size bit 2 mask. */ ++#define USART_CHSIZE2_bp 2 /* Character Size bit 2 position. */ ++ ++/* USART.CTRLD bit masks and bit positions */ ++#define USART_DECTYPE_gm 0x30 /* Receive Interrupt Level group mask. */ ++#define USART_DECTYPE_gp 4 /* Receive Interrupt Level group position. */ ++#define USART_DECTYPE0_bm (1<<4) /* Receive Interrupt Level bit 0 mask. */ ++#define USART_DECTYPE0_bp 4 /* Receive Interrupt Level bit 0 position. */ ++#define USART_DECTYPE1_bm (1<<5) /* Receive Interrupt Level bit 1 mask. */ ++#define USART_DECTYPE1_bp 5 /* Receive Interrupt Level bit 1 position. */ ++ ++#define USART_LUTACT_gm 0x0C /* Transmit Interrupt Level group mask. */ ++#define USART_LUTACT_gp 2 /* Transmit Interrupt Level group position. */ ++#define USART_LUTACT0_bm (1<<2) /* Transmit Interrupt Level bit 0 mask. */ ++#define USART_LUTACT0_bp 2 /* Transmit Interrupt Level bit 0 position. */ ++#define USART_LUTACT1_bm (1<<3) /* Transmit Interrupt Level bit 1 mask. */ ++#define USART_LUTACT1_bp 3 /* Transmit Interrupt Level bit 1 position. */ ++ ++#define USART_PECACT_gm 0x03 /* Data Register Empty Interrupt Level group mask. */ ++#define USART_PECACT_gp 0 /* Data Register Empty Interrupt Level group position. */ ++#define USART_PECACT0_bm (1<<0) /* Data Register Empty Interrupt Level bit 0 mask. */ ++#define USART_PECACT0_bp 0 /* Data Register Empty Interrupt Level bit 0 position. */ ++#define USART_PECACT1_bm (1<<1) /* Data Register Empty Interrupt Level bit 1 mask. */ ++#define USART_PECACT1_bp 1 /* Data Register Empty Interrupt Level bit 1 position. */ ++ ++/* USART.BAUDCTRLA bit masks and bit positions */ ++#define USART_BSEL_gm 0xFF /* Baud Rate Selection Bits [7:0] group mask. */ ++#define USART_BSEL_gp 0 /* Baud Rate Selection Bits [7:0] group position. */ ++#define USART_BSEL0_bm (1<<0) /* Baud Rate Selection Bits [7:0] bit 0 mask. */ ++#define USART_BSEL0_bp 0 /* Baud Rate Selection Bits [7:0] bit 0 position. */ ++#define USART_BSEL1_bm (1<<1) /* Baud Rate Selection Bits [7:0] bit 1 mask. */ ++#define USART_BSEL1_bp 1 /* Baud Rate Selection Bits [7:0] bit 1 position. */ ++#define USART_BSEL2_bm (1<<2) /* Baud Rate Selection Bits [7:0] bit 2 mask. */ ++#define USART_BSEL2_bp 2 /* Baud Rate Selection Bits [7:0] bit 2 position. */ ++#define USART_BSEL3_bm (1<<3) /* Baud Rate Selection Bits [7:0] bit 3 mask. */ ++#define USART_BSEL3_bp 3 /* Baud Rate Selection Bits [7:0] bit 3 position. */ ++#define USART_BSEL4_bm (1<<4) /* Baud Rate Selection Bits [7:0] bit 4 mask. */ ++#define USART_BSEL4_bp 4 /* Baud Rate Selection Bits [7:0] bit 4 position. */ ++#define USART_BSEL5_bm (1<<5) /* Baud Rate Selection Bits [7:0] bit 5 mask. */ ++#define USART_BSEL5_bp 5 /* Baud Rate Selection Bits [7:0] bit 5 position. */ ++#define USART_BSEL6_bm (1<<6) /* Baud Rate Selection Bits [7:0] bit 6 mask. */ ++#define USART_BSEL6_bp 6 /* Baud Rate Selection Bits [7:0] bit 6 position. */ ++#define USART_BSEL7_bm (1<<7) /* Baud Rate Selection Bits [7:0] bit 7 mask. */ ++#define USART_BSEL7_bp 7 /* Baud Rate Selection Bits [7:0] bit 7 position. */ ++ ++/* USART.BAUDCTRLB bit masks and bit positions */ ++#define USART_BSCALE_gm 0xF0 /* Baud Rate Scale group mask. */ ++#define USART_BSCALE_gp 4 /* Baud Rate Scale group position. */ ++#define USART_BSCALE0_bm (1<<4) /* Baud Rate Scale bit 0 mask. */ ++#define USART_BSCALE0_bp 4 /* Baud Rate Scale bit 0 position. */ ++#define USART_BSCALE1_bm (1<<5) /* Baud Rate Scale bit 1 mask. */ ++#define USART_BSCALE1_bp 5 /* Baud Rate Scale bit 1 position. */ ++#define USART_BSCALE2_bm (1<<6) /* Baud Rate Scale bit 2 mask. */ ++#define USART_BSCALE2_bp 6 /* Baud Rate Scale bit 2 position. */ ++#define USART_BSCALE3_bm (1<<7) /* Baud Rate Scale bit 3 mask. */ ++#define USART_BSCALE3_bp 7 /* Baud Rate Scale bit 3 position. */ ++ ++/* USART_BSEL Predefined. */ ++/* USART_BSEL Predefined. */ ++ ++/* SPI - Serial Peripheral Interface */ ++/* SPI.CTRL bit masks and bit positions */ ++#define SPI_CLK2X_bm 0x80 /* Enable Double Speed bit mask. */ ++#define SPI_CLK2X_bp 7 /* Enable Double Speed bit position. */ ++ ++#define SPI_ENABLE_bm 0x40 /* Enable SPI Module bit mask. */ ++#define SPI_ENABLE_bp 6 /* Enable SPI Module bit position. */ ++ ++#define SPI_DORD_bm 0x20 /* Data Order Setting bit mask. */ ++#define SPI_DORD_bp 5 /* Data Order Setting bit position. */ ++ ++#define SPI_MASTER_bm 0x10 /* Master Operation Enable bit mask. */ ++#define SPI_MASTER_bp 4 /* Master Operation Enable bit position. */ ++ ++#define SPI_MODE_gm 0x0C /* SPI Mode group mask. */ ++#define SPI_MODE_gp 2 /* SPI Mode group position. */ ++#define SPI_MODE0_bm (1<<2) /* SPI Mode bit 0 mask. */ ++#define SPI_MODE0_bp 2 /* SPI Mode bit 0 position. */ ++#define SPI_MODE1_bm (1<<3) /* SPI Mode bit 1 mask. */ ++#define SPI_MODE1_bp 3 /* SPI Mode bit 1 position. */ ++ ++#define SPI_PRESCALER_gm 0x03 /* Prescaler group mask. */ ++#define SPI_PRESCALER_gp 0 /* Prescaler group position. */ ++#define SPI_PRESCALER0_bm (1<<0) /* Prescaler bit 0 mask. */ ++#define SPI_PRESCALER0_bp 0 /* Prescaler bit 0 position. */ ++#define SPI_PRESCALER1_bm (1<<1) /* Prescaler bit 1 mask. */ ++#define SPI_PRESCALER1_bp 1 /* Prescaler bit 1 position. */ ++ ++/* SPI.INTCTRL bit masks and bit positions */ ++#define SPI_RXCIE_bm 0x80 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ ++#define SPI_RXCIE_bp 7 /* Receive Complete Interrupt Enable (In Buffer Modes Only). bit position. */ ++ ++#define SPI_TXCIE_bm 0x40 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit mask. */ ++#define SPI_TXCIE_bp 6 /* Transmit Complete Interrupt Enable (In Buffer Modes Only). bit position. */ ++ ++#define SPI_DREIE_bm 0x20 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit mask. */ ++#define SPI_DREIE_bp 5 /* Data Register Empty Interrupt Enable (In Buffer Modes Only). bit position. */ ++ ++#define SPI_SSIE_bm 0x10 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit mask. */ ++#define SPI_SSIE_bp 4 /* Slave Select Trigger Interrupt Enable (In Buffer Modes Only). bit position. */ ++ ++#define SPI_INTLVL_gm 0x03 /* Interrupt level group mask. */ ++#define SPI_INTLVL_gp 0 /* Interrupt level group position. */ ++#define SPI_INTLVL0_bm (1<<0) /* Interrupt level bit 0 mask. */ ++#define SPI_INTLVL0_bp 0 /* Interrupt level bit 0 position. */ ++#define SPI_INTLVL1_bm (1<<1) /* Interrupt level bit 1 mask. */ ++#define SPI_INTLVL1_bp 1 /* Interrupt level bit 1 position. */ ++ ++/* SPI.STATUS bit masks and bit positions */ ++#define SPI_IF_bm 0x80 /* Interrupt Flag (In Standard Mode Only). bit mask. */ ++#define SPI_IF_bp 7 /* Interrupt Flag (In Standard Mode Only). bit position. */ ++ ++#define SPI_RXCIF_bm 0x80 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ ++#define SPI_RXCIF_bp 7 /* Receive Complete Interrupt Flag (In Buffer Modes Only). bit position. */ ++ ++#define SPI_WRCOL_bm 0x40 /* Write Collision Flag (In Standard Mode Only). bit mask. */ ++#define SPI_WRCOL_bp 6 /* Write Collision Flag (In Standard Mode Only). bit position. */ ++ ++#define SPI_TXCIF_bm 0x40 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit mask. */ ++#define SPI_TXCIF_bp 6 /* Transmit Complete Interrupt Flag (In Buffer Modes Only). bit position. */ ++ ++#define SPI_DREIF_bm 0x20 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit mask. */ ++#define SPI_DREIF_bp 5 /* Data Register Empty Interrupt Flag (In Buffer Modes Only). bit position. */ ++ ++#define SPI_SSIF_bm 0x10 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit mask. */ ++#define SPI_SSIF_bp 4 /* Slave Select Trigger Interrupt Flag (In Buffer Modes Only). bit position. */ ++ ++#define SPI_BUFOVF_bm 0x01 /* Buffer Overflow (In Buffer Modes Only). bit mask. */ ++#define SPI_BUFOVF_bp 0 /* Buffer Overflow (In Buffer Modes Only). bit position. */ ++ ++/* SPI.CTRLB bit masks and bit positions */ ++#define SPI_BUFMODE_gm 0xC0 /* Buffer Modes group mask. */ ++#define SPI_BUFMODE_gp 6 /* Buffer Modes group position. */ ++#define SPI_BUFMODE0_bm (1<<6) /* Buffer Modes bit 0 mask. */ ++#define SPI_BUFMODE0_bp 6 /* Buffer Modes bit 0 position. */ ++#define SPI_BUFMODE1_bm (1<<7) /* Buffer Modes bit 1 mask. */ ++#define SPI_BUFMODE1_bp 7 /* Buffer Modes bit 1 position. */ ++ ++#define SPI_SSD_bm 0x04 /* Slave Select Disable bit mask. */ ++#define SPI_SSD_bp 2 /* Slave Select Disable bit position. */ ++ ++/* IRCOM - IR Communication Module */ ++/* IRCOM.CTRL bit masks and bit positions */ ++#define IRCOM_EVSEL_gm 0x0F /* Event Channel Select group mask. */ ++#define IRCOM_EVSEL_gp 0 /* Event Channel Select group position. */ ++#define IRCOM_EVSEL0_bm (1<<0) /* Event Channel Select bit 0 mask. */ ++#define IRCOM_EVSEL0_bp 0 /* Event Channel Select bit 0 position. */ ++#define IRCOM_EVSEL1_bm (1<<1) /* Event Channel Select bit 1 mask. */ ++#define IRCOM_EVSEL1_bp 1 /* Event Channel Select bit 1 position. */ ++#define IRCOM_EVSEL2_bm (1<<2) /* Event Channel Select bit 2 mask. */ ++#define IRCOM_EVSEL2_bp 2 /* Event Channel Select bit 2 position. */ ++#define IRCOM_EVSEL3_bm (1<<3) /* Event Channel Select bit 3 mask. */ ++#define IRCOM_EVSEL3_bp 3 /* Event Channel Select bit 3 position. */ ++ ++/* FUSE - Fuses and Lockbits */ ++/* NVM_LOCKBITS.LOCKBITS bit masks and bit positions */ ++#define NVM_LOCKBITS_BLBB_gm 0xC0 /* Boot Lock Bits - Boot Section group mask. */ ++#define NVM_LOCKBITS_BLBB_gp 6 /* Boot Lock Bits - Boot Section group position. */ ++#define NVM_LOCKBITS_BLBB0_bm (1<<6) /* Boot Lock Bits - Boot Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBB0_bp 6 /* Boot Lock Bits - Boot Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBB1_bm (1<<7) /* Boot Lock Bits - Boot Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBB1_bp 7 /* Boot Lock Bits - Boot Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBA_gm 0x30 /* Boot Lock Bits - Application Section group mask. */ ++#define NVM_LOCKBITS_BLBA_gp 4 /* Boot Lock Bits - Application Section group position. */ ++#define NVM_LOCKBITS_BLBA0_bm (1<<4) /* Boot Lock Bits - Application Section bit 0 mask. */ ++#define NVM_LOCKBITS_BLBA0_bp 4 /* Boot Lock Bits - Application Section bit 0 position. */ ++#define NVM_LOCKBITS_BLBA1_bm (1<<5) /* Boot Lock Bits - Application Section bit 1 mask. */ ++#define NVM_LOCKBITS_BLBA1_bp 5 /* Boot Lock Bits - Application Section bit 1 position. */ ++ ++#define NVM_LOCKBITS_BLBAT_gm 0x0C /* Boot Lock Bits - Application Table group mask. */ ++#define NVM_LOCKBITS_BLBAT_gp 2 /* Boot Lock Bits - Application Table group position. */ ++#define NVM_LOCKBITS_BLBAT0_bm (1<<2) /* Boot Lock Bits - Application Table bit 0 mask. */ ++#define NVM_LOCKBITS_BLBAT0_bp 2 /* Boot Lock Bits - Application Table bit 0 position. */ ++#define NVM_LOCKBITS_BLBAT1_bm (1<<3) /* Boot Lock Bits - Application Table bit 1 mask. */ ++#define NVM_LOCKBITS_BLBAT1_bp 3 /* Boot Lock Bits - Application Table bit 1 position. */ ++ ++#define NVM_LOCKBITS_LB_gm 0x03 /* Lock Bits group mask. */ ++#define NVM_LOCKBITS_LB_gp 0 /* Lock Bits group position. */ ++#define NVM_LOCKBITS_LB0_bm (1<<0) /* Lock Bits bit 0 mask. */ ++#define NVM_LOCKBITS_LB0_bp 0 /* Lock Bits bit 0 position. */ ++#define NVM_LOCKBITS_LB1_bm (1<<1) /* Lock Bits bit 1 mask. */ ++#define NVM_LOCKBITS_LB1_bp 1 /* Lock Bits bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE1 bit masks and bit positions */ ++#define NVM_FUSES_WDWP_gm 0xF0 /* Watchdog Window Timeout Period group mask. */ ++#define NVM_FUSES_WDWP_gp 4 /* Watchdog Window Timeout Period group position. */ ++#define NVM_FUSES_WDWP0_bm (1<<4) /* Watchdog Window Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDWP0_bp 4 /* Watchdog Window Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDWP1_bm (1<<5) /* Watchdog Window Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDWP1_bp 5 /* Watchdog Window Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDWP2_bm (1<<6) /* Watchdog Window Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDWP2_bp 6 /* Watchdog Window Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDWP3_bm (1<<7) /* Watchdog Window Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDWP3_bp 7 /* Watchdog Window Timeout Period bit 3 position. */ ++ ++#define NVM_FUSES_WDP_gm 0x0F /* Watchdog Timeout Period group mask. */ ++#define NVM_FUSES_WDP_gp 0 /* Watchdog Timeout Period group position. */ ++#define NVM_FUSES_WDP0_bm (1<<0) /* Watchdog Timeout Period bit 0 mask. */ ++#define NVM_FUSES_WDP0_bp 0 /* Watchdog Timeout Period bit 0 position. */ ++#define NVM_FUSES_WDP1_bm (1<<1) /* Watchdog Timeout Period bit 1 mask. */ ++#define NVM_FUSES_WDP1_bp 1 /* Watchdog Timeout Period bit 1 position. */ ++#define NVM_FUSES_WDP2_bm (1<<2) /* Watchdog Timeout Period bit 2 mask. */ ++#define NVM_FUSES_WDP2_bp 2 /* Watchdog Timeout Period bit 2 position. */ ++#define NVM_FUSES_WDP3_bm (1<<3) /* Watchdog Timeout Period bit 3 mask. */ ++#define NVM_FUSES_WDP3_bp 3 /* Watchdog Timeout Period bit 3 position. */ ++ ++/* NVM_FUSES.FUSEBYTE2 bit masks and bit positions */ ++#define NVM_FUSES_BOOTRST_bm 0x40 /* Boot Loader Section Reset Vector bit mask. */ ++#define NVM_FUSES_BOOTRST_bp 6 /* Boot Loader Section Reset Vector bit position. */ ++ ++#define NVM_FUSES_BODPD_gm 0x03 /* BOD Operation in Power-Down Mode group mask. */ ++#define NVM_FUSES_BODPD_gp 0 /* BOD Operation in Power-Down Mode group position. */ ++#define NVM_FUSES_BODPD0_bm (1<<0) /* BOD Operation in Power-Down Mode bit 0 mask. */ ++#define NVM_FUSES_BODPD0_bp 0 /* BOD Operation in Power-Down Mode bit 0 position. */ ++#define NVM_FUSES_BODPD1_bm (1<<1) /* BOD Operation in Power-Down Mode bit 1 mask. */ ++#define NVM_FUSES_BODPD1_bp 1 /* BOD Operation in Power-Down Mode bit 1 position. */ ++ ++/* NVM_FUSES.FUSEBYTE4 bit masks and bit positions */ ++#define NVM_FUSES_RSTDISBL_bm 0x10 /* External Reset Disable bit mask. */ ++#define NVM_FUSES_RSTDISBL_bp 4 /* External Reset Disable bit position. */ ++ ++#define NVM_FUSES_SUT_gm 0x0C /* Start-up Time group mask. */ ++#define NVM_FUSES_SUT_gp 2 /* Start-up Time group position. */ ++#define NVM_FUSES_SUT0_bm (1<<2) /* Start-up Time bit 0 mask. */ ++#define NVM_FUSES_SUT0_bp 2 /* Start-up Time bit 0 position. */ ++#define NVM_FUSES_SUT1_bm (1<<3) /* Start-up Time bit 1 mask. */ ++#define NVM_FUSES_SUT1_bp 3 /* Start-up Time bit 1 position. */ ++ ++#define NVM_FUSES_WDLOCK_bm 0x02 /* Watchdog Timer Lock bit mask. */ ++#define NVM_FUSES_WDLOCK_bp 1 /* Watchdog Timer Lock bit position. */ ++ ++/* NVM_FUSES.FUSEBYTE5 bit masks and bit positions */ ++#define NVM_FUSES_BODACT_gm 0x30 /* BOD Operation in Active Mode group mask. */ ++#define NVM_FUSES_BODACT_gp 4 /* BOD Operation in Active Mode group position. */ ++#define NVM_FUSES_BODACT0_bm (1<<4) /* BOD Operation in Active Mode bit 0 mask. */ ++#define NVM_FUSES_BODACT0_bp 4 /* BOD Operation in Active Mode bit 0 position. */ ++#define NVM_FUSES_BODACT1_bm (1<<5) /* BOD Operation in Active Mode bit 1 mask. */ ++#define NVM_FUSES_BODACT1_bp 5 /* BOD Operation in Active Mode bit 1 position. */ ++ ++#define NVM_FUSES_EESAVE_bm 0x08 /* Preserve EEPROM Through Chip Erase bit mask. */ ++#define NVM_FUSES_EESAVE_bp 3 /* Preserve EEPROM Through Chip Erase bit position. */ ++ ++#define NVM_FUSES_BODLVL_gm 0x07 /* Brownout Detection Voltage Level group mask. */ ++#define NVM_FUSES_BODLVL_gp 0 /* Brownout Detection Voltage Level group position. */ ++#define NVM_FUSES_BODLVL0_bm (1<<0) /* Brownout Detection Voltage Level bit 0 mask. */ ++#define NVM_FUSES_BODLVL0_bp 0 /* Brownout Detection Voltage Level bit 0 position. */ ++#define NVM_FUSES_BODLVL1_bm (1<<1) /* Brownout Detection Voltage Level bit 1 mask. */ ++#define NVM_FUSES_BODLVL1_bp 1 /* Brownout Detection Voltage Level bit 1 position. */ ++#define NVM_FUSES_BODLVL2_bm (1<<2) /* Brownout Detection Voltage Level bit 2 mask. */ ++#define NVM_FUSES_BODLVL2_bp 2 /* Brownout Detection Voltage Level bit 2 position. */ ++ ++/* NVM_FUSES.FUSEBYTE6 bit masks and bit positions */ ++#define NVM_FUSES_FDACT5_bm 0x80 /* Fault Dectection Action on TC5 bit mask. */ ++#define NVM_FUSES_FDACT5_bp 7 /* Fault Dectection Action on TC5 bit position. */ ++ ++#define NVM_FUSES_FDACT4_bm 0x40 /* Fault Dectection Action on TC4 bit mask. */ ++#define NVM_FUSES_FDACT4_bp 6 /* Fault Dectection Action on TC4 bit position. */ ++ ++#define NVM_FUSES_VALUE_gm 0x3F /* Port Pin Value group mask. */ ++#define NVM_FUSES_VALUE_gp 0 /* Port Pin Value group position. */ ++#define NVM_FUSES_VALUE0_bm (1<<0) /* Port Pin Value bit 0 mask. */ ++#define NVM_FUSES_VALUE0_bp 0 /* Port Pin Value bit 0 position. */ ++#define NVM_FUSES_VALUE1_bm (1<<1) /* Port Pin Value bit 1 mask. */ ++#define NVM_FUSES_VALUE1_bp 1 /* Port Pin Value bit 1 position. */ ++#define NVM_FUSES_VALUE2_bm (1<<2) /* Port Pin Value bit 2 mask. */ ++#define NVM_FUSES_VALUE2_bp 2 /* Port Pin Value bit 2 position. */ ++#define NVM_FUSES_VALUE3_bm (1<<3) /* Port Pin Value bit 3 mask. */ ++#define NVM_FUSES_VALUE3_bp 3 /* Port Pin Value bit 3 position. */ ++#define NVM_FUSES_VALUE4_bm (1<<4) /* Port Pin Value bit 4 mask. */ ++#define NVM_FUSES_VALUE4_bp 4 /* Port Pin Value bit 4 position. */ ++#define NVM_FUSES_VALUE5_bm (1<<5) /* Port Pin Value bit 5 mask. */ ++#define NVM_FUSES_VALUE5_bp 5 /* Port Pin Value bit 5 position. */ ++ ++ ++ ++// Generic Port Pins ++ ++#define PIN0_bm 0x01 ++#define PIN0_bp 0 ++#define PIN1_bm 0x02 ++#define PIN1_bp 1 ++#define PIN2_bm 0x04 ++#define PIN2_bp 2 ++#define PIN3_bm 0x08 ++#define PIN3_bp 3 ++#define PIN4_bm 0x10 ++#define PIN4_bp 4 ++#define PIN5_bm 0x20 ++#define PIN5_bp 5 ++#define PIN6_bm 0x40 ++#define PIN6_bp 6 ++#define PIN7_bm 0x80 ++#define PIN7_bp 7 ++ ++/* ========== Interrupt Vector Definitions ========== */ ++/* Vector 0 is the reset vector */ ++ ++/* OSC interrupt vectors */ ++#define OSC_OSCF_vect_num 1 ++#define OSC_OSCF_vect _VECTOR(1) /* Oscillator Failure Interrupt (NMI) */ ++ ++/* PORTR interrupt vectors */ ++#define PORTR_INT_vect_num 2 ++#define PORTR_INT_vect _VECTOR(2) /* External Interrupt */ ++ ++/* EDMA interrupt vectors */ ++#define EDMA_CH0_vect_num 3 ++#define EDMA_CH0_vect _VECTOR(3) /* EDMA Channel 0 Interrupt */ ++#define EDMA_CH1_vect_num 4 ++#define EDMA_CH1_vect _VECTOR(4) /* EDMA Channel 1 Interrupt */ ++#define EDMA_CH2_vect_num 5 ++#define EDMA_CH2_vect _VECTOR(5) /* EDMA Channel 2 Interrupt */ ++#define EDMA_CH3_vect_num 6 ++#define EDMA_CH3_vect _VECTOR(6) /* EDMA Channel 3 Interrupt */ ++ ++/* RTC interrupt vectors */ ++#define RTC_OVF_vect_num 7 ++#define RTC_OVF_vect _VECTOR(7) /* Overflow Interrupt */ ++#define RTC_COMP_vect_num 8 ++#define RTC_COMP_vect _VECTOR(8) /* Compare Interrupt */ ++ ++/* PORTC interrupt vectors */ ++#define PORTC_INT_vect_num 9 ++#define PORTC_INT_vect _VECTOR(9) /* External Interrupt */ ++ ++/* TWIC interrupt vectors */ ++#define TWIC_TWIS_vect_num 10 ++#define TWIC_TWIS_vect _VECTOR(10) /* TWI Slave Interrupt */ ++#define TWIC_TWIM_vect_num 11 ++#define TWIC_TWIM_vect _VECTOR(11) /* TWI Master Interrupt */ ++ ++/* TCC4 interrupt vectors */ ++#define TCC4_OVF_vect_num 12 ++#define TCC4_OVF_vect _VECTOR(12) /* Overflow Interrupt */ ++#define TCC4_ERR_vect_num 13 ++#define TCC4_ERR_vect _VECTOR(13) /* Error Interrupt */ ++#define TCC4_CCA_vect_num 14 ++#define TCC4_CCA_vect _VECTOR(14) /* Channel A Compare or Capture Interrupt */ ++#define TCC4_CCB_vect_num 15 ++#define TCC4_CCB_vect _VECTOR(15) /* Channel B Compare or Capture Interrupt */ ++#define TCC4_CCC_vect_num 16 ++#define TCC4_CCC_vect _VECTOR(16) /* Channel C Compare or Capture Interrupt */ ++#define TCC4_CCD_vect_num 17 ++#define TCC4_CCD_vect _VECTOR(17) /* Channel D Compare or Capture Interrupt */ ++ ++/* TCC5 interrupt vectors */ ++#define TCC5_OVF_vect_num 18 ++#define TCC5_OVF_vect _VECTOR(18) /* Overflow Interrupt */ ++#define TCC5_ERR_vect_num 19 ++#define TCC5_ERR_vect _VECTOR(19) /* Error Interrupt */ ++#define TCC5_CCA_vect_num 20 ++#define TCC5_CCA_vect _VECTOR(20) /* Channel A Compare or Capture Interrupt */ ++#define TCC5_CCB_vect_num 21 ++#define TCC5_CCB_vect _VECTOR(21) /* Channel B Compare or Capture Interrupt */ ++ ++/* SPIC interrupt vectors */ ++#define SPIC_INT_vect_num 22 ++#define SPIC_INT_vect _VECTOR(22) /* SPI Interrupt */ ++ ++/* USARTC0 interrupt vectors */ ++#define USARTC0_RXC_vect_num 23 ++#define USARTC0_RXC_vect _VECTOR(23) /* Reception Complete Interrupt */ ++#define USARTC0_DRE_vect_num 24 ++#define USARTC0_DRE_vect _VECTOR(24) /* Data Register Empty Interrupt */ ++#define USARTC0_TXC_vect_num 25 ++#define USARTC0_TXC_vect _VECTOR(25) /* Transmission Complete Interrupt */ ++ ++/* NVM interrupt vectors */ ++#define NVM_EE_vect_num 26 ++#define NVM_EE_vect _VECTOR(26) /* EE Interrupt */ ++#define NVM_SPM_vect_num 27 ++#define NVM_SPM_vect _VECTOR(27) /* SPM Interrupt */ ++ ++/* XCL interrupt vectors */ ++#define XCL_UNF_vect_num 28 ++#define XCL_UNF_vect _VECTOR(28) /* Timer/Counter Underflow Interrupt */ ++#define XCL_CC_vect_num 29 ++#define XCL_CC_vect _VECTOR(29) /* Timer/Counter Compare or Capture Interrupt */ ++ ++/* PORTA interrupt vectors */ ++#define PORTA_INT_vect_num 30 ++#define PORTA_INT_vect _VECTOR(30) /* External Interrupt */ ++ ++/* ACA interrupt vectors */ ++#define ACA_AC0_vect_num 31 ++#define ACA_AC0_vect _VECTOR(31) /* AC0 Interrupt */ ++#define ACA_AC1_vect_num 32 ++#define ACA_AC1_vect _VECTOR(32) /* AC1 Interrupt */ ++#define ACA_ACW_vect_num 33 ++#define ACA_ACW_vect _VECTOR(33) /* ACW Window Mode Interrupt */ ++ ++/* ADCA interrupt vectors */ ++#define ADCA_CH0_vect_num 34 ++#define ADCA_CH0_vect _VECTOR(34) /* ADC Channel Interrupt */ ++ ++/* PORTD interrupt vectors */ ++#define PORTD_INT_vect_num 35 ++#define PORTD_INT_vect _VECTOR(35) /* External Interrupt */ ++ ++/* TCD5 interrupt vectors */ ++#define TCD5_OVF_vect_num 36 ++#define TCD5_OVF_vect _VECTOR(36) /* Overflow Interrupt */ ++#define TCD5_ERR_vect_num 37 ++#define TCD5_ERR_vect _VECTOR(37) /* Error Interrupt */ ++#define TCD5_CCA_vect_num 38 ++#define TCD5_CCA_vect _VECTOR(38) /* Channel A Compare or Capture Interrupt */ ++#define TCD5_CCB_vect_num 39 ++#define TCD5_CCB_vect _VECTOR(39) /* Channel B Compare or Capture Interrupt */ ++ ++/* USARTD0 interrupt vectors */ ++#define USARTD0_RXC_vect_num 40 ++#define USARTD0_RXC_vect _VECTOR(40) /* Reception Complete Interrupt */ ++#define USARTD0_DRE_vect_num 41 ++#define USARTD0_DRE_vect _VECTOR(41) /* Data Register Empty Interrupt */ ++#define USARTD0_TXC_vect_num 42 ++#define USARTD0_TXC_vect _VECTOR(42) /* Transmission Complete Interrupt */ ++ ++#define _VECTOR_SIZE 4 /* Size of individual vector. */ ++#define _VECTORS_SIZE (43 * _VECTOR_SIZE) ++ ++ ++/* ========== Constants ========== */ ++ ++#define PROGMEM_START (0x0000) ++#define PROGMEM_SIZE (10240) ++#define PROGMEM_END (PROGMEM_START + PROGMEM_SIZE - 1) ++ ++#define APP_SECTION_START (0x0000) ++#define APP_SECTION_SIZE (8192) ++#define APP_SECTION_PAGE_SIZE (128) ++#define APP_SECTION_END (APP_SECTION_START + APP_SECTION_SIZE - 1) ++ ++#define APPTABLE_SECTION_START (0x1800) ++#define APPTABLE_SECTION_SIZE (2048) ++#define APPTABLE_SECTION_PAGE_SIZE (128) ++#define APPTABLE_SECTION_END (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1) ++ ++#define BOOT_SECTION_START (0x2000) ++#define BOOT_SECTION_SIZE (2048) ++#define BOOT_SECTION_PAGE_SIZE (128) ++#define BOOT_SECTION_END (BOOT_SECTION_START + BOOT_SECTION_SIZE - 1) ++ ++#define DATAMEM_START (0x0000) ++#define DATAMEM_SIZE (9216) ++#define DATAMEM_END (DATAMEM_START + DATAMEM_SIZE - 1) ++ ++#define IO_START (0x0000) ++#define IO_SIZE (4096) ++#define IO_PAGE_SIZE (0) ++#define IO_END (IO_START + IO_SIZE - 1) ++ ++#define MAPPED_EEPROM_START (0x1000) ++#define MAPPED_EEPROM_SIZE (512) ++#define MAPPED_EEPROM_PAGE_SIZE (0) ++#define MAPPED_EEPROM_END (MAPPED_EEPROM_START + MAPPED_EEPROM_SIZE - 1) ++ ++#define INTERNAL_SRAM_START (0x2000) ++#define INTERNAL_SRAM_SIZE (1024) ++#define INTERNAL_SRAM_PAGE_SIZE (0) ++#define INTERNAL_SRAM_END (INTERNAL_SRAM_START + INTERNAL_SRAM_SIZE - 1) ++ ++#define EEPROM_START (0x0000) ++#define EEPROM_SIZE (512) ++#define EEPROM_PAGE_SIZE (32) ++#define EEPROM_END (EEPROM_START + EEPROM_SIZE - 1) ++ ++#define SIGNATURES_START (0x0000) ++#define SIGNATURES_SIZE (3) ++#define SIGNATURES_PAGE_SIZE (0) ++#define SIGNATURES_END (SIGNATURES_START + SIGNATURES_SIZE - 1) ++ ++#define FUSES_START (0x0000) ++#define FUSES_SIZE (7) ++#define FUSES_PAGE_SIZE (0) ++#define FUSES_END (FUSES_START + FUSES_SIZE - 1) ++ ++#define LOCKBITS_START (0x0000) ++#define LOCKBITS_SIZE (1) ++#define LOCKBITS_PAGE_SIZE (0) ++#define LOCKBITS_END (LOCKBITS_START + LOCKBITS_SIZE - 1) ++ ++#define USER_SIGNATURES_START (0x0000) ++#define USER_SIGNATURES_SIZE (128) ++#define USER_SIGNATURES_PAGE_SIZE (128) ++#define USER_SIGNATURES_END (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1) ++ ++#define PROD_SIGNATURES_START (0x0000) ++#define PROD_SIGNATURES_SIZE (52) ++#define PROD_SIGNATURES_PAGE_SIZE (128) ++#define PROD_SIGNATURES_END (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1) ++ ++#define FLASHSTART PROGMEM_START ++#define FLASHEND PROGMEM_END ++#define SPM_PAGESIZE 128 ++#define RAMSTART INTERNAL_SRAM_START ++#define RAMSIZE INTERNAL_SRAM_SIZE ++#define RAMEND INTERNAL_SRAM_END ++#define E2END EEPROM_END ++#define E2PAGESIZE EEPROM_PAGE_SIZE ++ ++ ++/* ========== Fuses ========== */ ++#define FUSE_MEMORY_SIZE 7 ++ ++/* Fuse Byte 0 Reserved */ ++ ++/* Fuse Byte 1 */ ++#define FUSE_WDP0 (unsigned char)~_BV(0) /* Watchdog Timeout Period Bit 0 */ ++#define FUSE_WDP1 (unsigned char)~_BV(1) /* Watchdog Timeout Period Bit 1 */ ++#define FUSE_WDP2 (unsigned char)~_BV(2) /* Watchdog Timeout Period Bit 2 */ ++#define FUSE_WDP3 (unsigned char)~_BV(3) /* Watchdog Timeout Period Bit 3 */ ++#define FUSE_WDWP0 (unsigned char)~_BV(4) /* Watchdog Window Timeout Period Bit 0 */ ++#define FUSE_WDWP1 (unsigned char)~_BV(5) /* Watchdog Window Timeout Period Bit 1 */ ++#define FUSE_WDWP2 (unsigned char)~_BV(6) /* Watchdog Window Timeout Period Bit 2 */ ++#define FUSE_WDWP3 (unsigned char)~_BV(7) /* Watchdog Window Timeout Period Bit 3 */ ++#define FUSE1_DEFAULT (0xFF) ++ ++/* Fuse Byte 2 */ ++#define FUSE_BODPD0 (unsigned char)~_BV(0) /* BOD Operation in Power-Down Mode Bit 0 */ ++#define FUSE_BODPD1 (unsigned char)~_BV(1) /* BOD Operation in Power-Down Mode Bit 1 */ ++#define FUSE_BOOTRST (unsigned char)~_BV(6) /* Boot Loader Section Reset Vector */ ++#define FUSE2_DEFAULT (0xFF) ++ ++/* Fuse Byte 3 Reserved */ ++ ++/* Fuse Byte 4 */ ++#define FUSE_WDLOCK (unsigned char)~_BV(1) /* Watchdog Timer Lock */ ++#define FUSE_SUT0 (unsigned char)~_BV(2) /* Start-up Time Bit 0 */ ++#define FUSE_SUT1 (unsigned char)~_BV(3) /* Start-up Time Bit 1 */ ++#define FUSE_RSTDISBL (unsigned char)~_BV(4) /* External Reset Disable */ ++#define FUSE4_DEFAULT (0xFF) ++ ++/* Fuse Byte 5 */ ++#define FUSE_BODLVL0 (unsigned char)~_BV(0) /* Brownout Detection Voltage Level Bit 0 */ ++#define FUSE_BODLVL1 (unsigned char)~_BV(1) /* Brownout Detection Voltage Level Bit 1 */ ++#define FUSE_BODLVL2 (unsigned char)~_BV(2) /* Brownout Detection Voltage Level Bit 2 */ ++#define FUSE_EESAVE (unsigned char)~_BV(3) /* Preserve EEPROM Through Chip Erase */ ++#define FUSE_BODACT0 (unsigned char)~_BV(4) /* BOD Operation in Active Mode Bit 0 */ ++#define FUSE_BODACT1 (unsigned char)~_BV(5) /* BOD Operation in Active Mode Bit 1 */ ++#define FUSE5_DEFAULT (0xFF) ++ ++/* Fuse Byte 6 */ ++#define FUSE_VALUE0 (unsigned char)~_BV(0) /* Port Pin Value Bit 0 */ ++#define FUSE_VALUE1 (unsigned char)~_BV(1) /* Port Pin Value Bit 1 */ ++#define FUSE_VALUE2 (unsigned char)~_BV(2) /* Port Pin Value Bit 2 */ ++#define FUSE_VALUE3 (unsigned char)~_BV(3) /* Port Pin Value Bit 3 */ ++#define FUSE_VALUE4 (unsigned char)~_BV(4) /* Port Pin Value Bit 4 */ ++#define FUSE_VALUE5 (unsigned char)~_BV(5) /* Port Pin Value Bit 5 */ ++#define FUSE_FDACT4 (unsigned char)~_BV(6) /* Fault Dectection Action on TC4 */ ++#define FUSE_FDACT5 (unsigned char)~_BV(7) /* Fault Dectection Action on TC5 */ ++#define FUSE6_DEFAULT (0xFF) ++ ++/* ========== Lock Bits ========== */ ++#define __LOCK_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST ++#define __BOOT_LOCK_APPLICATION_BITS_EXIST ++#define __BOOT_LOCK_BOOT_BITS_EXIST ++ ++/* ========== Signature ========== */ ++#define SIGNATURE_0 0x1E ++#define SIGNATURE_1 0x93 ++#define SIGNATURE_2 0x41 ++ ++ ++#endif /* #ifdef _AVR_ATXMEGA8E5_H_INCLUDED */ ++ diff --git a/include/avr/lock.h b/include/avr/lock.h index 9adc668..25d284e 100644 --- a/include/avr/lock.h @@ -266260,7 +700569,7 @@ index 6a24830..c179edf 100644 #ifndef _AVR_PORTPINS_H_ #define _AVR_PORTPINS_H_ 1 diff --git a/include/avr/power.h b/include/avr/power.h -index 76bbd86..aa5b0c2 100644 +index 76bbd86..c70eeb0 100644 --- a/include/avr/power.h +++ b/include/avr/power.h @@ -1,4 +1,5 @@ @@ -266355,7 +700664,7 @@ index 76bbd86..aa5b0c2 100644 - AT90PWM81 + power_adc_disable() + Disable the Analog to Digital Converter module. -+ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny441, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATA6612C, ATA6613C, ATA6614Q, ATA6616C, ATA6617C, ATA664251, ATtiny1634, ATtiny4, ATtiny5, ATtiny9, ATtiny10, ATtiny13A, ATtiny20, ATtiny40 ++ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega48PB, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega88PB, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega168PB, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny441, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATA6612C, ATA6613C, ATA6614Q, ATA6616C, ATA6617C, ATA664251, ATtiny1634, ATtiny4, ATtiny5, ATtiny9, ATtiny10, ATtiny13A, ATtiny20, ATtiny40 @@ -266364,7 +700673,7 @@ index 76bbd86..aa5b0c2 100644 - AT90PWM81 + power_adc_enable() + Enable the Analog to Digital Converter module. -+ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny441, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATA6612C, ATA6613C, ATA6614Q, ATA6616C, ATA6617C, ATA664251, ATtiny1634, ATtiny4, ATtiny5, ATtiny9, ATtiny10, ATtiny13A, ATtiny20, ATtiny40 ++ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega48PB, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega88PB, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega168PB, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny441, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATA6612C, ATA6613C, ATA6614Q, ATA6616C, ATA6617C, ATA664251, ATtiny1634, ATtiny4, ATtiny5, ATtiny9, ATtiny10, ATtiny13A, ATtiny20, ATtiny40 @@ -266934,25 +701243,17 @@ index 76bbd86..aa5b0c2 100644 + Enable the SCI module + AT90SCR100 + - --#define power_spic_enable() (PR_PRPC &= (uint8_t)~(PR_SPI_bm)) --#define power_spic_disable() (PR_PRPC |= (uint8_t)PR_SPI_bm) --#define power_spid_enable() (PR_PRPD &= (uint8_t)~(PR_SPI_bm)) --#define power_spid_disable() (PR_PRPD |= (uint8_t)PR_SPI_bm) --#define power_spie_enable() (PR_PRPE &= (uint8_t)~(PR_SPI_bm)) --#define power_spie_disable() (PR_PRPE |= (uint8_t)PR_SPI_bm) --#define power_spif_enable() (PR_PRPF &= (uint8_t)~(PR_SPI_bm)) --#define power_spif_disable() (PR_PRPF |= (uint8_t)PR_SPI_bm) ++ + + power_spi_disable() + Disable the Serial Peripheral Interface module. -+ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny441, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBrevB, ATmega16HVB, ATmega16HVBrevB, ATA5790, ATA5795, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATA6612C, ATA6613C, ATA6614Q, ATA6616C, ATA6617C, ATA664251, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny20, ATtiny40 ++ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega48PB, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega88PB, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega168PB, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny441, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBrevB, ATmega16HVB, ATmega16HVBrevB, ATA5790, ATA5795, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATA6612C, ATA6613C, ATA6614Q, ATA6616C, ATA6617C, ATA664251, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny20, ATtiny40 + + + + power_spi_enable() + Enable the Serial Peripheral Interface module. -+ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny441, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBrevB, ATmega16HVB, ATmega16HVBrevB, ATA5790, ATA5795, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATA6612C, ATA6613C, ATA6614Q, ATA6616C, ATA6617C, ATA664251, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny20, ATtiny40 ++ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega48PB, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega88PB, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega168PB, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny441, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBrevB, ATmega16HVB, ATmega16HVBrevB, ATA5790, ATA5795, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATA6612C, ATA6613C, ATA6614Q, ATA6616C, ATA6617C, ATA664251, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny20, ATtiny40 + + + @@ -267102,37 +701403,37 @@ index 76bbd86..aa5b0c2 100644 + + power_timer0_disable() + Disable the Timer 0 module. -+ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny441, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBrevB, ATmega16HVB, ATmega16HVBrevB, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATA6612C, ATA6613C, ATA6614Q, ATA6616C, ATA6617C, ATA664251, ATtiny1634, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny4, ATtiny5, ATtiny9, ATtiny10, ATtiny13A, ATtiny20, ATtiny40 ++ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega48PB, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega88PB, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega168PB, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny441, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBrevB, ATmega16HVB, ATmega16HVBrevB, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATA6612C, ATA6613C, ATA6614Q, ATA6616C, ATA6617C, ATA664251, ATtiny1634, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny4, ATtiny5, ATtiny9, ATtiny10, ATtiny13A, ATtiny20, ATtiny40 + + + + power_timer0_enable() + Enable the Timer 0 module. -+ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny441, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBrevB, ATmega16HVB, ATmega16HVBrevB, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATA6612C, ATA6613C, ATA6614Q, ATA6616C, ATA6617C, ATA664251, ATtiny1634, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny4, ATtiny5, ATtiny9, ATtiny10, ATtiny13A, ATtiny20, ATtiny40 ++ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega48PB, ATmega88, ATmega88A, ATmega88P, ATmega88PB, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega168PB, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny441, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBrevB, ATmega16HVB, ATmega16HVBrevB, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATA6612C, ATA6613C, ATA6614Q, ATA6616C, ATA6617C, ATA664251, ATtiny1634, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny4, ATtiny5, ATtiny9, ATtiny10, ATtiny13A, ATtiny20, ATtiny40 + + + + power_timer1_disable() + Disable the Timer 1 module. -+ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny441, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBrevB, ATmega16HVB, ATmega16HVBrevB, ATA5790, ATA5795, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATA6612C, ATA6613C, ATA6614Q, ATA6616C, ATA6617C, ATA664251, ATtiny1634, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny20, ATtiny40 ++ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega48PB, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega88PB, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega168PB, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny441, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBrevB, ATmega16HVB, ATmega16HVBrevB, ATA5790, ATA5795, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATA6612C, ATA6613C, ATA6614Q, ATA6616C, ATA6617C, ATA664251, ATtiny1634, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny20, ATtiny40 + + + + power_timer1_enable() + Enable the Timer 1 module. -+ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny441, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBrevB, ATmega16HVB, ATmega16HVBrevB, ATA5790, ATA5795, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATA6612C, ATA6613C, ATA6614Q, ATA6616C, ATA6617C, ATA664251, ATtiny1634, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny20, ATtiny40 ++ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, AT90PWM81, AT90PWM161, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega48PB, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega88PB, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega168PB, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny441, ATtiny24, ATtiny24A, ATtiny44, ATtiny44A, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny261A, ATtiny461, ATtiny461A, ATtiny861, ATtiny861A, ATtiny43U, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBrevB, ATmega16HVB, ATmega16HVBrevB, ATA5790, ATA5795, ATmega16M1, ATmega32C1, ATmega32M1, ATmega64C1, ATmega64M1, ATtiny167, ATtiny87, ATA5505, ATA5272, ATA6612C, ATA6613C, ATA6614Q, ATA6616C, ATA6617C, ATA664251, ATtiny1634, AT90USB82, AT90USB162, ATmega8U2, ATmega16U2, ATmega32U2, AT90SCR100, ATtiny20, ATtiny40 + + + + power_timer2_disable() + Disable the Timer 2 module. -+ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny441, ATmega1284, ATmega1284P, ATA5790, ATA5795, ATA6612C, ATA6613C, ATA6614Q, AT90SCR100 ++ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48PB, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega88PB, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega168PB, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny441, ATmega1284, ATmega1284P, ATA5790, ATA5795, ATA6612C, ATA6613C, ATA6614Q, AT90SCR100 + + + + power_timer2_enable() + Enable the Timer 2 module. -+ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny441, ATmega1284, ATmega1284P, ATA5790, ATA5795, ATA6612C, ATA6613C, ATA6614Q, AT90SCR100 ++ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48PB, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega88PB, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega168PB, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny441, ATmega1284, ATmega1284P, ATA5790, ATA5795, ATA6612C, ATA6613C, ATA6614Q, AT90SCR100 + + + @@ -267174,13 +701475,13 @@ index 76bbd86..aa5b0c2 100644 + + power_twi_disable() + Disable the Two Wire Interface module. -+ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny441, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBrevB, ATmega16HVB, ATmega16HVBrevB, ATA6612C, ATA6613C, ATA6614Q, ATtiny1634, AT90SCR100, ATtiny20, ATtiny40, ATA5702M322 ++ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega48PB, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega88PB, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega168PB, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny441, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBrevB, ATmega16HVB, ATmega16HVBrevB, ATA6612C, ATA6613C, ATA6614Q, ATtiny1634, AT90SCR100, ATtiny20, ATtiny40, ATA5702M322 + + + + power_twi_enable() + Enable the Two Wire Interface module. -+ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny441, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBrevB, ATmega16HVB, ATmega16HVBrevB, ATA6612C, ATA6613C, ATA6614Q, ATtiny1634, AT90SCR100, ATtiny20, ATtiny40, ATA5702M322 ++ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega32U4, ATmega16U4, ATmega32U6, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega406, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega48PB, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega88PB, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega168PB, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny441, ATmega1284, ATmega1284P, ATmega32HVB, ATmega32HVBrevB, ATmega16HVB, ATmega16HVBrevB, ATA6612C, ATA6613C, ATA6614Q, ATtiny1634, AT90SCR100, ATtiny20, ATtiny40, ATA5702M322 + + + @@ -267234,13 +701535,13 @@ index 76bbd86..aa5b0c2 100644 + + power_usart0_disable() + Disable the USART 0 module. -+ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega32U4, ATmega16U4, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny441, ATA6612C, ATA6613C, ATA6614Q, ATmega1284, ATmega1284P, ATtiny1634, AT90SCR100 ++ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega32U4, ATmega16U4, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48PB, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega88PB, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega168PB, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny441, ATA6612C, ATA6613C, ATA6614Q, ATmega1284, ATmega1284P, ATtiny1634, AT90SCR100 + + + + power_usart0_enable() + Enable the USART 0 module. -+ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega32U4, ATmega16U4, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny441, ATA6612C, ATA6613C, ATA6614Q, ATmega1284, ATmega1284P, ATtiny1634, AT90SCR100 ++ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega128RFA1, ATmega32U4, ATmega16U4, ATmega165, ATmega165A, ATmega165P, ATmega165PA, ATmega325, ATmega325A, ATmega325PA, ATmega3250, ATmega3250A, ATmega3250PA, ATmega645, ATmega645A, ATmega645P, ATmega6450, ATmega6450A, ATmega6450P, ATmega169, ATmega169A, ATmega169P, ATmega169PA, ATmega329, ATmega329A, ATmega329P, ATmega329PA, ATmega3290, ATmega3290A, ATmega3290P, ATmega3290PA, ATmega649, ATmega649A, ATmega649P, ATmega6490, ATmega6490A, ATmega6490P, ATmega164A, ATmega164P, ATmega324A, ATmega324P, ATmega324PA, ATmega644P, ATmega644A, ATmega644PA, ATmega644, ATmega164PA, ATmega48, ATmega48A, ATmega48PA, ATmega48PB, ATmega48P, ATmega88, ATmega88A, ATmega88P, ATmega88PA, ATmega88PB, ATmega168, ATmega168A, ATmega168P, ATmega168PA, ATmega168PB, ATmega328, ATmega328P, ATtiny48, ATtiny88, ATtiny828, ATtiny441, ATA6612C, ATA6613C, ATA6614Q, ATmega1284, ATmega1284P, ATtiny1634, AT90SCR100 + + + @@ -268200,6 +702501,15 @@ index 76bbd86..aa5b0c2 100644 +#define power_usarte0_enable() (PR_PRPE &= (uint8_t)~(PR_USART0_bm)) +#define power_usarte0_disable() (PR_PRPE |= (uint8_t)PR_USART0_bm) + #define power_spic_enable() (PR_PRPC &= (uint8_t)~(PR_SPI_bm)) + #define power_spic_disable() (PR_PRPC |= (uint8_t)PR_SPI_bm) +-#define power_spid_enable() (PR_PRPD &= (uint8_t)~(PR_SPI_bm)) +-#define power_spid_disable() (PR_PRPD |= (uint8_t)PR_SPI_bm) +-#define power_spie_enable() (PR_PRPE &= (uint8_t)~(PR_SPI_bm)) +-#define power_spie_disable() (PR_PRPE |= (uint8_t)PR_SPI_bm) +-#define power_spif_enable() (PR_PRPF &= (uint8_t)~(PR_SPI_bm)) +-#define power_spif_disable() (PR_PRPF |= (uint8_t)PR_SPI_bm) + -#define power_hiresc_enable() (PR_PRPC &= (uint8_t)~(PR_HIRES_bm)) -#define power_hiresc_disable() (PR_PRPC |= (uint8_t)PR_HIRES_bm) -#define power_hiresd_enable() (PR_PRPD &= (uint8_t)~(PR_HIRES_bm)) @@ -268208,9 +702518,6 @@ index 76bbd86..aa5b0c2 100644 -#define power_hirese_disable() (PR_PRPE |= (uint8_t)PR_HIRES_bm) -#define power_hiresf_enable() (PR_PRPF &= (uint8_t)~(PR_HIRES_bm)) -#define power_hiresf_disable() (PR_PRPF |= (uint8_t)PR_HIRES_bm) -+#define power_spic_enable() (PR_PRPC &= (uint8_t)~(PR_SPI_bm)) -+#define power_spic_disable() (PR_PRPC |= (uint8_t)PR_SPI_bm) -+ +#define power_hiresc_enable() (PR_PRPC &= (uint8_t)~(PR_HIRES_bm)) +#define power_hiresc_disable() (PR_PRPC |= (uint8_t)PR_HIRES_bm) @@ -268415,19 +702722,23 @@ index 76bbd86..aa5b0c2 100644 #define power_adc_enable() (PRR0 &= (uint8_t)~(1 << PRADC)) #define power_adc_disable() (PRR0 |= (uint8_t)(1 << PRADC)) -@@ -1016,6 +2316,7 @@ do{ \ +@@ -1016,18 +2316,27 @@ do{ \ #elif defined(__AVR_ATmega48__) \ || defined(__AVR_ATmega48A__) \ +|| defined(__AVR_ATmega48PA__) \ ++|| defined(__AVR_ATmega48PB__) \ || defined(__AVR_ATmega48P__) \ || defined(__AVR_ATmega88__) \ || defined(__AVR_ATmega88A__) \ -@@ -1024,10 +2325,15 @@ do{ \ + || defined(__AVR_ATmega88P__) \ + || defined(__AVR_ATmega88PA__) \ ++|| defined(__AVR_ATmega88PB__) \ || defined(__AVR_ATmega168__) \ || defined(__AVR_ATmega168A__) \ || defined(__AVR_ATmega168P__) \ +|| defined(__AVR_ATmega168PA__) \ ++|| defined(__AVR_ATmega168PB__) \ || defined(__AVR_ATmega328__) \ || defined(__AVR_ATmega328P__) \ -|| defined(__AVR_ATtiny48__) \ @@ -268441,7 +702752,7 @@ index 76bbd86..aa5b0c2 100644 #define power_adc_enable() (PRR &= (uint8_t)~(1 << PRADC)) #define power_adc_disable() (PRR |= (uint8_t)(1 << PRADC)) -@@ -1038,22 +2344,70 @@ do{ \ +@@ -1038,22 +2347,70 @@ do{ \ #define power_usart0_enable() (PRR &= (uint8_t)~(1 << PRUSART0)) #define power_usart0_disable() (PRR |= (uint8_t)(1 << PRUSART0)) @@ -268504,15 +702815,15 @@ index 76bbd86..aa5b0c2 100644 + +#define power_twi_enable() (PRR &= (uint8_t)~(1 << PRTWI)) +#define power_twi_disable() (PRR |= (uint8_t)(1 << PRTWI)) -+ + +#define power_all_enable() (PRR &= (uint8_t)~((1<: avr-libc version macros \code #include \endcode diff --git a/include/avr/wdt.h b/include/avr/wdt.h -index 6c3dc80..fda6438 100644 +index 6c3dc80..92c62da 100644 --- a/include/avr/wdt.h +++ b/include/avr/wdt.h @@ -29,7 +29,7 @@ @@ -270182,7 +704472,7 @@ index 6c3dc80..fda6438 100644 || defined(__AVR_AT90PWM81__) \ || defined(__AVR_AT90USB1286__) \ || defined(__AVR_AT90USB1287__) \ -@@ -184,19 +249,26 @@ __asm__ __volatile__ ( \ +@@ -184,19 +249,27 @@ __asm__ __volatile__ ( \ || defined(__AVR_AT90USB646__) \ || defined(__AVR_AT90USB647__) \ || defined(__AVR_AT90USB82__) \ @@ -270206,17 +704496,11 @@ index 6c3dc80..fda6438 100644 || defined(__AVR_ATmega168A__) \ || defined(__AVR_ATmega168P__) \ +|| defined(__AVR_ATmega168PA__) \ ++|| defined(__AVR_ATmega168PB__) \ || defined(__AVR_ATmega169__) \ || defined(__AVR_ATmega169A__) \ || defined(__AVR_ATmega169P__) \ -@@ -204,12 +276,15 @@ __asm__ __volatile__ ( \ - || defined(__AVR_ATmega16HVA__) \ - || defined(__AVR_ATmega16HVA2__) \ - || defined(__AVR_ATmega16HVB__) \ --|| defined(__AVR_ATmega16HVBREVB__) \ -+|| defined(__AVR_ATmega16HVBrevB__) \ - || defined(__AVR_ATmega16M1__) \ - || defined(__AVR_ATmega16U2__) \ +@@ -210,6 +283,9 @@ __asm__ __volatile__ ( \ || defined(__AVR_ATmega16U4__) \ || defined(__AVR_ATmega2560__) \ || defined(__AVR_ATmega2561__) \ @@ -270226,7 +704510,7 @@ index 6c3dc80..fda6438 100644 || defined(__AVR_ATmega324__) \ || defined(__AVR_ATmega324A__) \ || defined(__AVR_ATmega324P__) \ -@@ -217,9 +292,11 @@ __asm__ __volatile__ ( \ +@@ -217,9 +293,11 @@ __asm__ __volatile__ ( \ || defined(__AVR_ATmega325__) \ || defined(__AVR_ATmega325A__) \ || defined(__AVR_ATmega325P__) \ @@ -270238,23 +704522,20 @@ index 6c3dc80..fda6438 100644 || defined(__AVR_ATmega328__) \ || defined(__AVR_ATmega328P__) \ || defined(__AVR_ATmega329__) \ -@@ -229,9 +306,10 @@ __asm__ __volatile__ ( \ +@@ -229,6 +307,7 @@ __asm__ __volatile__ ( \ || defined(__AVR_ATmega3290__) \ || defined(__AVR_ATmega3290A__) \ || defined(__AVR_ATmega3290P__) \ +|| defined(__AVR_ATmega3290PA__) \ || defined(__AVR_ATmega32C1__) \ || defined(__AVR_ATmega32HVB__) \ --|| defined(__AVR_ATmega32HVBREVB__) \ -+|| defined(__AVR_ATmega32HVBrevB__) \ - || defined(__AVR_ATmega32M1__) \ - || defined(__AVR_ATmega32U2__) \ - || defined(__AVR_ATmega32U4__) \ -@@ -239,7 +317,11 @@ __asm__ __volatile__ ( \ + || defined(__AVR_ATmega32HVBREVB__) \ +@@ -239,7 +318,12 @@ __asm__ __volatile__ ( \ || defined(__AVR_ATmega406__) \ || defined(__AVR_ATmega48__) \ || defined(__AVR_ATmega48A__) \ +|| defined(__AVR_ATmega48PA__) \ ++|| defined(__AVR_ATmega48PB__) \ || defined(__AVR_ATmega48P__) \ +|| defined(__AVR_ATmega64A__) \ +|| defined(__AVR_ATmega64RFR2__) \ @@ -270262,7 +704543,7 @@ index 6c3dc80..fda6438 100644 || defined(__AVR_ATmega640__) \ || defined(__AVR_ATmega644__) \ || defined(__AVR_ATmega644A__) \ -@@ -259,7 +341,9 @@ __asm__ __volatile__ ( \ +@@ -259,11 +343,14 @@ __asm__ __volatile__ ( \ || defined(__AVR_ATmega649P__) \ || defined(__AVR_ATmega64C1__) \ || defined(__AVR_ATmega64HVE__) \ @@ -270272,7 +704553,12 @@ index 6c3dc80..fda6438 100644 || defined(__AVR_ATmega88__) \ || defined(__AVR_ATmega88A__) \ || defined(__AVR_ATmega88P__) \ -@@ -271,7 +355,23 @@ __asm__ __volatile__ ( \ + || defined(__AVR_ATmega88PA__) \ ++|| defined(__AVR_ATmega88PB__) \ + || defined(__AVR_ATmega8HVA__) \ + || defined(__AVR_ATmega8U2__) \ + || defined(__AVR_ATtiny48__) \ +@@ -271,7 +358,23 @@ __asm__ __volatile__ ( \ || defined(__AVR_ATtiny87__) \ || defined(__AVR_ATtiny167__) \ || defined(__AVR_AT90SCR100__) \ @@ -270297,7 +704583,7 @@ index 6c3dc80..fda6438 100644 /* Use STS instruction. */ -@@ -305,6 +405,145 @@ __asm__ __volatile__ ( \ +@@ -305,6 +408,145 @@ __asm__ __volatile__ ( \ ) @@ -270443,7 +704729,7 @@ index 6c3dc80..fda6438 100644 #else -@@ -415,8 +654,10 @@ __asm__ __volatile__ ( \ +@@ -415,8 +657,10 @@ __asm__ __volatile__ ( \ ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561, ATmega8HVA, ATmega16HVA, ATmega32HVB, ATmega406, ATmega1284P, @@ -270455,7 +704741,7 @@ index 6c3dc80..fda6438 100644 AT90USB82, AT90USB162, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATtiny48, ATtiny88. -@@ -430,17 +671,22 @@ __asm__ __volatile__ ( \ +@@ -430,17 +674,22 @@ __asm__ __volatile__ ( \ ATtiny24, ATtiny44, ATtiny84, ATtiny84A, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861, diff --git a/avr-libc.build.bash b/avr-libc.build.bash index d87d2f5..0e7453a 100755 --- a/avr-libc.build.bash +++ b/avr-libc.build.bash @@ -17,21 +17,21 @@ then wget http://download.savannah.gnu.org/releases/avr-libc/avr-libc-1.8.0.tar.bz2 fi -tar xfjv avr-libc-1.8.0.tar.bz2 +tar xfv avr-libc-1.8.0.tar.bz2 cd avr-libc-1.8.0 -for p in ../avr-libc-patches/*.patch; do echo Applying $p; patch -p1 < $p; done +for p in ../avr-libc-patches/*.patch; do echo Applying $p; patch --binary -p1 < $p; done cd - -if [[ ! -f avr8-headers-6.2.0.334.zip ]] ; +if [[ ! -f avr8-headers-6.2.0.469.zip ]] ; then - wget http://distribute.atmel.no/tools/opensource/Atmel-AVR-GNU-Toolchain/3.4.4/avr8-headers-6.2.0.334.zip + wget http://distribute.atmel.no/tools/opensource/Atmel-AVR-GNU-Toolchain/3.4.5/avr8-headers-6.2.0.469.zip fi -unzip avr8-headers-6.2.0.334.zip -mv avr avr8-headers-6.2.0.334 +unzip avr8-headers-6.2.0.469.zip +mv avr avr8-headers-6.2.0.469 -for i in avr8-headers-6.2.0.334/io[0-9a-zA-Z]*.h +for i in avr8-headers-6.2.0.469/io[0-9a-zA-Z]*.h do cp -v -f $i avr-libc-1.8.0/include/avr/ done diff --git a/avrdude.build.bash b/avrdude.build.bash index 9231604..0451134 100755 --- a/avrdude.build.bash +++ b/avrdude.build.bash @@ -17,7 +17,7 @@ then wget http://download.savannah.gnu.org/releases/avrdude/avrdude-6.0.1.tar.gz fi -tar xfzv avrdude-6.0.1.tar.gz +tar xfv avrdude-6.0.1.tar.gz cd avrdude-6.0.1 for p in ../avrdude-patches/*.patch; do echo Applying $p; patch -p0 < $p; done diff --git a/binutils-patches/00-binutils-2.24-atmel.patch b/binutils-patches/00-binutils-2.24-atmel.patch index 7e6286c..9a37e03 100644 --- a/binutils-patches/00-binutils-2.24-atmel.patch +++ b/binutils-patches/00-binutils-2.24-atmel.patch @@ -3070,39 +3070,33 @@ index d9e743e..97d74ee 100644 AC_SUBST([am__untar]) ]) # _AM_PROG_TAR diff --git a/bfd/archures.c b/bfd/archures.c -index 97c540a..4a414e0 100644 +index 97c540a..80e5dfc 100644 --- a/bfd/archures.c +++ b/bfd/archures.c -@@ -398,6 +398,8 @@ DESCRIPTION +@@ -398,6 +398,7 @@ DESCRIPTION .#define bfd_mach_avr5 5 .#define bfd_mach_avr51 51 .#define bfd_mach_avr6 6 -+.#define bfd_mach_avr7 7 -+.#define bfd_mach_avrtiny 90 ++.#define bfd_mach_avrtiny 100 .#define bfd_mach_avrxmega1 101 .#define bfd_mach_avrxmega2 102 .#define bfd_mach_avrxmega3 103 diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h -index 756af87..43fee1c 100644 +index 756af87..6d58c43 100644 --- a/bfd/bfd-in2.h +++ b/bfd/bfd-in2.h -@@ -2153,6 +2153,8 @@ enum bfd_architecture +@@ -2153,6 +2153,7 @@ enum bfd_architecture #define bfd_mach_avr5 5 #define bfd_mach_avr51 51 #define bfd_mach_avr6 6 -+#define bfd_mach_avr7 7 -+#define bfd_mach_avrtiny 90 ++#define bfd_mach_avrtiny 100 #define bfd_mach_avrxmega1 101 #define bfd_mach_avrxmega2 102 #define bfd_mach_avrxmega3 103 -@@ -4251,6 +4253,20 @@ in .byte hi8(symbol) */ +@@ -4251,6 +4252,20 @@ in .byte hi8(symbol) */ in .byte hlo8(symbol) */ BFD_RELOC_AVR_8_HLO, -+/* This is a 7 bit reloc for the AVR that stores offset for 16bit sts/lds -+instructions supported only by Tiny core */ -+ BFD_RELOC_AVR_7_LDS16, -+ +/* AVR relocations to mark the difference of two local symbols. +These are only needed to support linker relaxation and can be ignored +when not relaxing. The field is set to the value of the difference @@ -3112,6 +3106,10 @@ index 756af87..43fee1c 100644 + BFD_RELOC_AVR_DIFF8, + BFD_RELOC_AVR_DIFF16, + BFD_RELOC_AVR_DIFF32, ++ ++/* This is a 7 bit reloc for the AVR that stores SRAM address for 16bit ++lds and sts instructions supported only tiny core. */ ++ BFD_RELOC_AVR_LDS_STS_16, + /* Renesas RL78 Relocations. */ BFD_RELOC_RL78_NEG8, @@ -8117,146 +8115,177 @@ index 90cd397..5cc5770 100755 if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5 diff --git a/bfd/cpu-avr.c b/bfd/cpu-avr.c -index 8083538..c7fa1cb 100644 +index 8083538..d3da25a 100644 --- a/bfd/cpu-avr.c +++ b/bfd/cpu-avr.c -@@ -135,25 +135,31 @@ static const bfd_arch_info_type arch_info_struct[] = +@@ -1,6 +1,5 @@ + /* BFD library support routines for the AVR architecture. +- Copyright 1999, 2000, 2002, 2005, 2006, 2007, 2008 +- Free Software Foundation, Inc. ++ Copyright (C) 1999-2014 Free Software Foundation, Inc. + Contributed by Denis Chertykov + This file is part of BFD, the Binary File Descriptor library. +@@ -68,7 +67,6 @@ compatible (const bfd_arch_info_type * a, + return a; + if (a->mach == bfd_mach_avr31 && b->mach == bfd_mach_avr3) + return b; +- + if (a->mach == bfd_mach_avr3 && b->mach == bfd_mach_avr35) + return a; + if (a->mach == bfd_mach_avr35 && b->mach == bfd_mach_avr3) +@@ -79,7 +77,6 @@ compatible (const bfd_arch_info_type * a, + if (a->mach == bfd_mach_avr51 && b->mach == bfd_mach_avr5) + return b; + +- + return NULL; + } + +@@ -136,25 +133,28 @@ static const bfd_arch_info_type arch_info_struct[] = /* 3-Byte PC. */ N (22, bfd_mach_avr6, "avr:6", FALSE, & arch_info_struct[10]), -+ -+ /* Tiny core (ATTiny10 & similar) */ -+ N (16, bfd_mach_avrtiny, "avr:90", FALSE, & arch_info_struct[11]), - /* Xmega 1 */ +- /* Xmega 1 */ - N (24, bfd_mach_avrxmega1, "avr:101", FALSE, & arch_info_struct[11]), -+ N (24, bfd_mach_avrxmega1, "avr:101", FALSE, & arch_info_struct[12]), - - /* Xmega 2 */ +- +- /* Xmega 2 */ - N (24, bfd_mach_avrxmega2, "avr:102", FALSE, & arch_info_struct[12]), - -+ N (24, bfd_mach_avrxmega2, "avr:102", FALSE, & arch_info_struct[13]), -+ - /* Xmega 3 */ +- /* Xmega 3 */ - N (24, bfd_mach_avrxmega3, "avr:103", FALSE, & arch_info_struct[13]), - -+ N (24, bfd_mach_avrxmega3, "avr:103", FALSE, & arch_info_struct[14]), -+ - /* Xmega 4 */ +- /* Xmega 4 */ - N (24, bfd_mach_avrxmega4, "avr:104", FALSE, & arch_info_struct[14]), - -+ N (24, bfd_mach_avrxmega4, "avr:104", FALSE, & arch_info_struct[15]), -+ - /* Xmega 5 */ +- /* Xmega 5 */ - N (24, bfd_mach_avrxmega5, "avr:105", FALSE, & arch_info_struct[15]), - -+ N (24, bfd_mach_avrxmega5, "avr:105", FALSE, & arch_info_struct[16]), -+ - /* Xmega 6 */ +- /* Xmega 6 */ - N (24, bfd_mach_avrxmega6, "avr:106", FALSE, & arch_info_struct[16]), - -+ N (24, bfd_mach_avrxmega6, "avr:106", FALSE, & arch_info_struct[17]), -+ -+ /* 20K flash. starts at 0x8000 */ -+ N (16, bfd_mach_avr7, "avr:7", FALSE, & arch_info_struct[18]), +- /* Xmega 7 */ ++ /* Tiny core (AVR Tiny). */ ++ N (16, bfd_mach_avrtiny, "avr:100", FALSE, & arch_info_struct[11]), ++ ++ /* Xmega 1. */ ++ N (24, bfd_mach_avrxmega1, "avr:101", FALSE, & arch_info_struct[12]), ++ ++ /* Xmega 2. */ ++ N (24, bfd_mach_avrxmega2, "avr:102", FALSE, & arch_info_struct[13]), + - /* Xmega 7 */ ++ /* Xmega 3. */ ++ N (24, bfd_mach_avrxmega3, "avr:103", FALSE, & arch_info_struct[14]), ++ ++ /* Xmega 4. */ ++ N (24, bfd_mach_avrxmega4, "avr:104", FALSE, & arch_info_struct[15]), ++ ++ /* Xmega 5. */ ++ N (24, bfd_mach_avrxmega5, "avr:105", FALSE, & arch_info_struct[16]), ++ ++ /* Xmega 6. */ ++ N (24, bfd_mach_avrxmega6, "avr:106", FALSE, & arch_info_struct[17]), ++ ++ /* Xmega 7. */ N (24, bfd_mach_avrxmega7, "avr:107", FALSE, NULL) + }; diff --git a/bfd/elf32-avr.c b/bfd/elf32-avr.c -index 43100cd..7cd4a0e 100644 +index 43100cd..596fc1f 100644 --- a/bfd/elf32-avr.c +++ b/bfd/elf32-avr.c -@@ -32,6 +32,15 @@ static bfd_boolean debug_relax = FALSE; +@@ -1,5 +1,5 @@ + /* AVR-specific support for 32-bit ELF +- Copyright 1999-2013 Free Software Foundation, Inc. ++ Copyright (C) 1999-2014 Free Software Foundation, Inc. + Contributed by Denis Chertykov + + This file is part of BFD, the Binary File Descriptor library. +@@ -32,6 +32,10 @@ static bfd_boolean debug_relax = FALSE; /* Enable debugging printout at stdout with this variable. */ static bfd_boolean debug_stubs = FALSE; +static bfd_reloc_status_type -+bfd_elf_avr_diff_reloc (bfd *abfd, -+ arelent *reloc_entry, -+ asymbol *symbol, -+ void *data, -+ asection *input_section, -+ bfd *output_bfd, -+ char **error_message); ++bfd_elf_avr_diff_reloc (bfd *, arelent *, asymbol *, void *, ++ asection *, bfd *, char **); + /* Hash table initialization and handling. Code is taken from the hppa port and adapted to the needs of AVR. */ -@@ -557,6 +566,59 @@ static reloc_howto_type elf_avr_howto_table[] = +@@ -557,6 +561,59 @@ static reloc_howto_type elf_avr_howto_table[] = 0xffffff, /* src_mask */ 0xffffff, /* dst_mask */ FALSE), /* pcrel_offset */ -+ /* 7 bit immediate for LDS/STS in Tiny core */ -+ HOWTO (R_AVR_7_LDS16, /* type */ -+ 0, /* rightshift */ -+ 1, /* size (0 = byte, 1 = short, 2 = long) */ -+ 7, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_dont,/* complain_on_overflow */ -+ bfd_elf_generic_reloc, /* special_function */ -+ "R_AVR_7_LDS16", /* name */ -+ FALSE, /* partial_inplace */ -+ 0xffff, /* src_mask */ -+ 0xffff, /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ HOWTO (R_AVR_DIFF8, /* type */ -+ 0, /* rightshift */ -+ 0, /* size (0 = byte, 1 = short, 2 = long) */ -+ 8, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_bitfield, /* complain_on_overflow */ -+ bfd_elf_avr_diff_reloc, /* special_function */ -+ "R_AVR_DIFF8", /* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0xff, /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ HOWTO (R_AVR_DIFF16, /* type */ -+ 0, /* rightshift */ -+ 1, /* size (0 = byte, 1 = short, 2 = long) */ -+ 16, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_bitfield, /* complain_on_overflow */ -+ bfd_elf_avr_diff_reloc, /* special_function */ -+ "R_AVR_DIFF16", /* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0xffff, /* dst_mask */ -+ FALSE), /* pcrel_offset */ -+ HOWTO (R_AVR_DIFF32, /* type */ -+ 0, /* rightshift */ -+ 2, /* size (0 = byte, 1 = short, 2 = long) */ -+ 32, /* bitsize */ -+ FALSE, /* pc_relative */ -+ 0, /* bitpos */ -+ complain_overflow_bitfield, /* complain_on_overflow */ -+ bfd_elf_avr_diff_reloc, /* special_function */ -+ "R_AVR_DIFF32", /* name */ -+ FALSE, /* partial_inplace */ -+ 0, /* src_mask */ -+ 0xffffffff, /* dst_mask */ -+ FALSE) /* pcrel_offset */ ++ HOWTO (R_AVR_DIFF8, /* type */ ++ 0, /* rightshift */ ++ 0, /* size (0 = byte, 1 = short, 2 = long) */ ++ 8, /* bitsize */ ++ FALSE, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_bitfield, /* complain_on_overflow */ ++ bfd_elf_avr_diff_reloc, /* special_function */ ++ "R_AVR_DIFF8", /* name */ ++ FALSE, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0xff, /* dst_mask */ ++ FALSE), /* pcrel_offset */ ++ HOWTO (R_AVR_DIFF16, /* type */ ++ 0, /* rightshift */ ++ 1, /* size (0 = byte, 1 = short, 2 = long) */ ++ 16, /* bitsize */ ++ FALSE, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_bitfield, /* complain_on_overflow */ ++ bfd_elf_avr_diff_reloc,/* special_function */ ++ "R_AVR_DIFF16", /* name */ ++ FALSE, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0xffff, /* dst_mask */ ++ FALSE), /* pcrel_offset */ ++ HOWTO (R_AVR_DIFF32, /* type */ ++ 0, /* rightshift */ ++ 2, /* size (0 = byte, 1 = short, 2 = long) */ ++ 32, /* bitsize */ ++ FALSE, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_bitfield, /* complain_on_overflow */ ++ bfd_elf_avr_diff_reloc,/* special_function */ ++ "R_AVR_DIFF32", /* name */ ++ FALSE, /* partial_inplace */ ++ 0, /* src_mask */ ++ 0xffffffff, /* dst_mask */ ++ FALSE), /* pcrel_offset */ ++ /* 7 bit immediate for LDS/STS in Tiny core. */ ++ HOWTO (R_AVR_LDS_STS_16, /* type */ ++ 0, /* rightshift */ ++ 1, /* size (0 = byte, 1 = short, 2 = long) */ ++ 7, /* bitsize */ ++ FALSE, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_dont,/* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_AVR_LDS_STS_16", /* name */ ++ FALSE, /* partial_inplace */ ++ 0xffff, /* src_mask */ ++ 0xffff, /* dst_mask */ ++ FALSE) /* pcrel_offset */ }; /* Map BFD reloc types to AVR ELF reloc types. */ -@@ -598,7 +660,11 @@ static const struct avr_reloc_map avr_reloc_map[] = +@@ -598,7 +655,11 @@ static const struct avr_reloc_map avr_reloc_map[] = { BFD_RELOC_8, R_AVR_8 }, { BFD_RELOC_AVR_8_LO, R_AVR_8_LO8 }, { BFD_RELOC_AVR_8_HI, R_AVR_8_HI8 }, - { BFD_RELOC_AVR_8_HLO, R_AVR_8_HLO8 } + { BFD_RELOC_AVR_8_HLO, R_AVR_8_HLO8 }, -+ { BFD_RELOC_AVR_7_LDS16, R_AVR_7_LDS16 }, + { BFD_RELOC_AVR_DIFF8, R_AVR_DIFF8 }, + { BFD_RELOC_AVR_DIFF16, R_AVR_DIFF16 }, -+ { BFD_RELOC_AVR_DIFF32, R_AVR_DIFF32 } ++ { BFD_RELOC_AVR_DIFF32, R_AVR_DIFF32 }, ++ { BFD_RELOC_AVR_LDS_STS_16, R_AVR_LDS_STS_16} }; /* Meant to be filled one day with the wrap around address for the -@@ -797,6 +863,22 @@ avr_get_stub_addr (bfd_vma srel, +@@ -797,6 +858,22 @@ avr_get_stub_addr (bfd_vma srel, return 0x020000; } @@ -8279,25 +8308,7 @@ index 43100cd..7cd4a0e 100644 /* Perform a single relocation. By default we use the standard BFD routines, but a few relocs, we have to do them ourselves. */ -@@ -1120,6 +1202,17 @@ avr_final_link_relocate (reloc_howto_type * howto, - bfd_put_16 (input_bfd, (bfd_vma) srel & 0xffff, contents+2); - break; - -+ case R_AVR_7_LDS16: -+ contents += rel->r_offset; -+ srel = (bfd_signed_vma) relocation + rel->r_addend; -+ if ((srel & 0xFFFF) < 0x40 || (srel & 0xFFFF) > 0xbf) -+ return bfd_reloc_outofrange; -+ srel = srel & 0x7f; -+ x = bfd_get_16 (input_bfd, contents); -+ x |= (srel & 0x0f) | ((srel & 0x30) << 5) | ((srel & 0x40) << 2); -+ bfd_put_16 (input_bfd, x, contents); -+ break; -+ - case R_AVR_16_PM: - use_stubs = (!htab->no_stubs); - contents += rel->r_offset; -@@ -1149,6 +1242,13 @@ avr_final_link_relocate (reloc_howto_type * howto, +@@ -1149,6 +1226,24 @@ avr_final_link_relocate (reloc_howto_type * howto, bfd_put_16 (input_bfd, (bfd_vma) srel &0x00ffff, contents); break; @@ -8307,51 +8318,40 @@ index 43100cd..7cd4a0e 100644 + /* Nothing to do here, as contents already contains the diff value. */ + r = bfd_reloc_ok; + break; ++ ++ case R_AVR_LDS_STS_16: ++ contents += rel->r_offset; ++ srel = (bfd_signed_vma) relocation + rel->r_addend; ++ if ((srel & 0xFFFF) < 0x40 || (srel & 0xFFFF) > 0xbf) ++ return bfd_reloc_outofrange; ++ srel = srel & 0x7f; ++ x = bfd_get_16 (input_bfd, contents); ++ x |= (srel & 0x0f) | ((srel & 0x30) << 5) | ((srel & 0x40) << 2); ++ bfd_put_16 (input_bfd, x, contents); ++ break; + default: r = _bfd_final_link_relocate (howto, input_bfd, input_section, contents, rel->r_offset, -@@ -1334,6 +1434,10 @@ bfd_elf_avr_final_write_processing (bfd *abfd, - val = E_AVR_MACH_AVR6; - break; - -+ case bfd_mach_avr7: -+ val = E_AVR_MACH_AVR7; -+ break; -+ - case bfd_mach_avrxmega1: - val = E_AVR_MACH_XMEGA1; - break; -@@ -1361,6 +1465,10 @@ bfd_elf_avr_final_write_processing (bfd *abfd, +@@ -1361,6 +1456,10 @@ bfd_elf_avr_final_write_processing (bfd *abfd, case bfd_mach_avrxmega7: val = E_AVR_MACH_XMEGA7; break; + -+ case bfd_mach_avrtiny: ++ case bfd_mach_avrtiny: + val = E_AVR_MACH_AVRTINY; + break; } elf_elfheader (abfd)->e_machine = EM_AVR; -@@ -1424,6 +1532,10 @@ elf32_avr_object_p (bfd *abfd) - e_set = bfd_mach_avr6; - break; - -+ case E_AVR_MACH_AVR7: -+ e_set = bfd_mach_avr7; -+ break; -+ - case E_AVR_MACH_XMEGA1: - e_set = bfd_mach_avrxmega1; - break; -@@ -1451,12 +1563,109 @@ elf32_avr_object_p (bfd *abfd) +@@ -1451,12 +1550,112 @@ elf32_avr_object_p (bfd *abfd) case E_AVR_MACH_XMEGA7: e_set = bfd_mach_avrxmega7; break; + -+ case E_AVR_MACH_AVRTINY: -+ e_set = bfd_mach_avrtiny; -+ break; ++ case E_AVR_MACH_AVRTINY: ++ e_set = bfd_mach_avrtiny; ++ break; } } return bfd_default_set_arch_mach (abfd, bfd_arch_avr, @@ -8368,9 +8368,9 @@ index 43100cd..7cd4a0e 100644 + || ELF32_R_TYPE (irel->r_info) == R_AVR_DIFF32); +} + -+/* Reduce the value written in the section by count if the shrinked insn address -+ happens to fall between the two symbols for which this diff reloc was -+ emitted. */ ++/* Reduce the diff value written in the section by count if the shrinked ++ insn address happens to fall between the two symbols for which this ++ diff reloc was emitted. */ + +static void +elf32_avr_adjust_diff_reloc_value (bfd *abfd, @@ -8422,8 +8422,11 @@ index 43100cd..7cd4a0e 100644 + bfd_vma end_address = symval + irel->r_addend; + bfd_vma start_address = end_address - x; + -+ if (shrinked_insn_address >= start_address && -+ shrinked_insn_address <= end_address) ++ /* Reduce the diff value by count bytes and write it back into section ++ contents. */ ++ ++ if (shrinked_insn_address >= start_address ++ && shrinked_insn_address <= end_address) + { + switch (ELF32_R_TYPE (irel->r_info)) + { @@ -8454,7 +8457,7 @@ index 43100cd..7cd4a0e 100644 /* Delete some bytes from a section while changing the size of an instruction. The parameter "addr" denotes the section-relative offset pointing just -@@ -1595,6 +1804,14 @@ elf32_avr_relax_delete_bytes (bfd *abfd, +@@ -1595,6 +1794,14 @@ elf32_avr_relax_delete_bytes (bfd *abfd, if (symval <= shrinked_insn_address && (symval + irel->r_addend) > shrinked_insn_address) { @@ -8469,34 +8472,41 @@ index 43100cd..7cd4a0e 100644 irel->r_addend -= count; if (debug_relax) +@@ -1765,8 +1972,8 @@ elf32_avr_relax_section (bfd *abfd, + bfd_vma symval; + + if ( ELF32_R_TYPE (irel->r_info) != R_AVR_13_PCREL +- && ELF32_R_TYPE (irel->r_info) != R_AVR_7_PCREL +- && ELF32_R_TYPE (irel->r_info) != R_AVR_CALL) ++ && ELF32_R_TYPE (irel->r_info) != R_AVR_7_PCREL ++ && ELF32_R_TYPE (irel->r_info) != R_AVR_CALL) + continue; + + /* Get the section contents if we haven't done so already. */ diff --git a/bfd/libbfd.h b/bfd/libbfd.h -index 4aaecbf..8045f03 100644 +index 4aaecbf..2754897 100644 --- a/bfd/libbfd.h +++ b/bfd/libbfd.h @@ -1947,6 +1947,10 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@", "BFD_RELOC_AVR_8_LO", "BFD_RELOC_AVR_8_HI", "BFD_RELOC_AVR_8_HLO", -+ "BFD_RELOC_AVR_7_LDS16", + "BFD_RELOC_AVR_DIFF8", + "BFD_RELOC_AVR_DIFF16", + "BFD_RELOC_AVR_DIFF32", ++ "BFD_RELOC_AVR_LDS_STS_16", "BFD_RELOC_RL78_NEG8", "BFD_RELOC_RL78_NEG16", "BFD_RELOC_RL78_NEG24", diff --git a/bfd/reloc.c b/bfd/reloc.c -index 77a04f8..6ad4401 100644 +index 77a04f8..eec472f 100644 --- a/bfd/reloc.c +++ b/bfd/reloc.c -@@ -4510,6 +4510,24 @@ ENUM +@@ -4510,7 +4510,24 @@ ENUM ENUMDOC This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol in .byte hlo8(symbol) -+ENUM -+ BFD_RELOC_AVR_7_LDS16 -+ENUMDOC -+ This is a 7 bit reloc for the AVR that stores offset for 16bit sts/lds -+ instructions supported only by Tiny core +- +ENUM + BFD_RELOC_AVR_DIFF8 +ENUMX @@ -8510,9 +8520,14 @@ index 77a04f8..6ad4401 100644 + assuming no relaxation. The relocation encodes the position of the + second symbol so the linker can determine whether to adjust the field + value. - ++ENUM ++ BFD_RELOC_AVR_LDS_STS_16 ++ENUMDOC ++ This is a 7 bit reloc for the AVR that stores SRAM address for 16bit ++ lds and sts instructions supported only tiny core. ENUM BFD_RELOC_RL78_NEG8 + ENUMX diff --git a/binutils/Makefile.in b/binutils/Makefile.in index e1e61dc..ffa8f68 100644 --- a/binutils/Makefile.in @@ -14827,7 +14842,7 @@ index fcf9784..1b2fd81 100755 if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5 diff --git a/binutils/size.c b/binutils/size.c -index 0937de5..173ee6f 100644 +index 0937de5..27db2e6 100644 --- a/binutils/size.c +++ b/binutils/size.c @@ -36,10 +36,31 @@ @@ -14875,7 +14890,7 @@ index 0937de5..173ee6f 100644 static int show_version = 0; static int show_help = 0; static int show_totals = 0; -@@ -64,6 +84,325 @@ static bfd_size_type total_textsize; +@@ -64,6 +84,328 @@ static bfd_size_type total_textsize; /* Program exit status. */ static int return_code = 0; @@ -15098,6 +15113,7 @@ index 0937de5..173ee6f 100644 + {"atmega168a", AVR16K, AVR1K, AVR512}, + {"atmega168p", AVR16K, AVR1K, AVR512}, + {"atmega168pa", AVR16K, AVR1K, AVR512}, ++ {"atmega168pb", AVR16K, AVR1K, AVR512}, + {"atmega169", AVR16K, AVR1K, AVR512}, + {"atmega169a", AVR16K, AVR1K, AVR512}, + {"atmega169p", AVR16K, AVR1K, AVR512}, @@ -15135,6 +15151,7 @@ index 0937de5..173ee6f 100644 + {"atmega88a", AVR8K, AVR1K, AVR512}, + {"atmega88p", AVR8K, AVR1K, AVR512}, + {"atmega88pa", AVR8K, AVR1K, AVR512}, ++ {"atmega88pb", AVR8K, AVR1K, AVR512}, + {"atmega8hva", AVR8K, 768UL, AVR256}, + {"atmega8u2", AVR8K, AVR512, AVR512}, + {"attiny84", AVR8K, AVR512, AVR512}, @@ -15152,6 +15169,7 @@ index 0937de5..173ee6f 100644 + {"atmega48", AVR4K, AVR512, AVR256}, + {"atmega48a", AVR4K, AVR512, AVR256}, + {"atmega48pa", AVR4K, AVR512, AVR256}, ++ {"atmega48pb", AVR4K, AVR512, AVR256}, + {"atmega48p", AVR4K, AVR512, AVR256}, + {"attiny4313", AVR4K, AVR256, AVR256}, + {"attiny43u", AVR4K, AVR256, AVR64}, @@ -15201,7 +15219,7 @@ index 0937de5..173ee6f 100644 static char *target = NULL; /* Forward declarations. */ -@@ -79,7 +418,9 @@ usage (FILE *stream, int status) +@@ -79,7 +421,9 @@ usage (FILE *stream, int status) fprintf (stream, _(" Displays the sizes of sections inside binary files\n")); fprintf (stream, _(" If no input file(s) are specified, a.out is assumed\n")); fprintf (stream, _(" The options are:\n\ @@ -15212,7 +15230,7 @@ index 0937de5..173ee6f 100644 -o|-d|-x --radix={8|10|16} Display numbers in octal, decimal or hex\n\ -t --totals Display the total sizes (Berkeley only)\n\ --common Display total size for *COM* syms\n\ -@@ -88,11 +429,7 @@ usage (FILE *stream, int status) +@@ -88,11 +432,7 @@ usage (FILE *stream, int status) -h --help Display this information\n\ -v --version Display the program's version\n\ \n"), @@ -15225,7 +15243,7 @@ index 0937de5..173ee6f 100644 ); list_supported_targets (program_name, stream); if (REPORT_BUGS_TO[0] && status == 0) -@@ -103,6 +440,8 @@ usage (FILE *stream, int status) +@@ -103,6 +443,8 @@ usage (FILE *stream, int status) #define OPTION_FORMAT (200) #define OPTION_RADIX (OPTION_FORMAT + 1) #define OPTION_TARGET (OPTION_RADIX + 1) @@ -15234,7 +15252,7 @@ index 0937de5..173ee6f 100644 static struct option long_options[] = { -@@ -110,12 +449,38 @@ static struct option long_options[] = +@@ -110,12 +452,38 @@ static struct option long_options[] = {"format", required_argument, 0, OPTION_FORMAT}, {"radix", required_argument, 0, OPTION_RADIX}, {"target", required_argument, 0, OPTION_TARGET}, @@ -15273,7 +15291,7 @@ index 0937de5..173ee6f 100644 int main (int, char **); int -@@ -141,7 +506,7 @@ main (int argc, char **argv) +@@ -141,7 +509,7 @@ main (int argc, char **argv) bfd_init (); set_default_bfd_target (); @@ -15282,7 +15300,7 @@ index 0937de5..173ee6f 100644 (int *) 0)) != EOF) switch (c) { -@@ -150,11 +515,15 @@ main (int argc, char **argv) +@@ -150,11 +518,15 @@ main (int argc, char **argv) { case 'B': case 'b': @@ -15300,7 +15318,7 @@ index 0937de5..173ee6f 100644 break; default: non_fatal (_("invalid argument to --format: %s"), optarg); -@@ -162,6 +531,14 @@ main (int argc, char **argv) +@@ -162,6 +534,14 @@ main (int argc, char **argv) } break; @@ -15315,7 +15333,7 @@ index 0937de5..173ee6f 100644 case OPTION_TARGET: target = optarg; break; -@@ -190,11 +567,14 @@ main (int argc, char **argv) +@@ -190,11 +570,14 @@ main (int argc, char **argv) break; case 'A': @@ -15332,7 +15350,7 @@ index 0937de5..173ee6f 100644 case 'v': case 'V': show_version = 1; -@@ -240,7 +620,7 @@ main (int argc, char **argv) +@@ -240,7 +623,7 @@ main (int argc, char **argv) for (; optind < argc;) display_file (argv[optind++]); @@ -15341,7 +15359,7 @@ index 0937de5..173ee6f 100644 { bfd_size_type total = total_textsize + total_datasize + total_bsssize; -@@ -599,13 +979,117 @@ print_sysv_format (bfd *file) +@@ -599,13 +982,117 @@ print_sysv_format (bfd *file) printf ("\n\n"); } @@ -24833,18 +24851,10 @@ index 411710e..78644c8 100644 +/* Define to `unsigned int' if does not define. */ +#undef size_t diff --git a/gas/config/tc-avr.c b/gas/config/tc-avr.c -index 332aa2d..555b50d 100644 +index 332aa2d..8612f6f 100644 --- a/gas/config/tc-avr.c +++ b/gas/config/tc-avr.c -@@ -82,6 +82,7 @@ static struct mcu_type_s mcu_types[] = - {"avr5", AVR_ISA_AVR51, bfd_mach_avr5}, - {"avr51", AVR_ISA_AVR51, bfd_mach_avr51}, - {"avr6", AVR_ISA_AVR6, bfd_mach_avr6}, -+ {"avr7", AVR_ISA_AVR7, bfd_mach_avr7}, - {"avrxmega1", AVR_ISA_XMEGA, bfd_mach_avrxmega1}, - {"avrxmega2", AVR_ISA_XMEGA, bfd_mach_avrxmega2}, - {"avrxmega3", AVR_ISA_XMEGA, bfd_mach_avrxmega3}, -@@ -89,6 +90,7 @@ static struct mcu_type_s mcu_types[] = +@@ -89,6 +89,7 @@ static struct mcu_type_s mcu_types[] = {"avrxmega5", AVR_ISA_XMEGA, bfd_mach_avrxmega5}, {"avrxmega6", AVR_ISA_XMEGA, bfd_mach_avrxmega6}, {"avrxmega7", AVR_ISA_XMEGA, bfd_mach_avrxmega7}, @@ -24852,7 +24862,7 @@ index 332aa2d..555b50d 100644 {"at90s1200", AVR_ISA_1200, bfd_mach_avr1}, {"attiny11", AVR_ISA_AVR1, bfd_mach_avr1}, {"attiny12", AVR_ISA_AVR1, bfd_mach_avr1}, -@@ -106,6 +108,8 @@ static struct mcu_type_s mcu_types[] = +@@ -106,6 +107,8 @@ static struct mcu_type_s mcu_types[] = {"at90s8515", AVR_ISA_AVR2, bfd_mach_avr2}, {"at90c8534", AVR_ISA_AVR2, bfd_mach_avr2}, {"at90s8535", AVR_ISA_AVR2, bfd_mach_avr2}, @@ -24861,7 +24871,7 @@ index 332aa2d..555b50d 100644 {"attiny13", AVR_ISA_AVR25, bfd_mach_avr25}, {"attiny13a", AVR_ISA_AVR25, bfd_mach_avr25}, {"attiny2313", AVR_ISA_AVR25, bfd_mach_avr25}, -@@ -115,11 +119,13 @@ static struct mcu_type_s mcu_types[] = +@@ -115,11 +118,13 @@ static struct mcu_type_s mcu_types[] = {"attiny4313", AVR_ISA_AVR25, bfd_mach_avr25}, {"attiny44", AVR_ISA_AVR25, bfd_mach_avr25}, {"attiny44a", AVR_ISA_AVR25, bfd_mach_avr25}, @@ -24875,7 +24885,7 @@ index 332aa2d..555b50d 100644 {"attiny261", AVR_ISA_AVR25, bfd_mach_avr25}, {"attiny261a", AVR_ISA_AVR25, bfd_mach_avr25}, {"attiny461", AVR_ISA_AVR25, bfd_mach_avr25}, -@@ -130,6 +136,7 @@ static struct mcu_type_s mcu_types[] = +@@ -130,6 +135,7 @@ static struct mcu_type_s mcu_types[] = {"attiny43u", AVR_ISA_AVR25, bfd_mach_avr25}, {"attiny48", AVR_ISA_AVR25, bfd_mach_avr25}, {"attiny88", AVR_ISA_AVR25, bfd_mach_avr25}, @@ -24883,7 +24893,7 @@ index 332aa2d..555b50d 100644 {"at86rf401", AVR_ISA_RF401, bfd_mach_avr25}, {"at43usb355", AVR_ISA_AVR3, bfd_mach_avr3}, {"at76c711", AVR_ISA_AVR3, bfd_mach_avr3}, -@@ -138,13 +145,22 @@ static struct mcu_type_s mcu_types[] = +@@ -138,18 +144,29 @@ static struct mcu_type_s mcu_types[] = {"attiny167", AVR_ISA_AVR35, bfd_mach_avr35}, {"at90usb82", AVR_ISA_AVR35, bfd_mach_avr35}, {"at90usb162", AVR_ISA_AVR35, bfd_mach_avr35}, @@ -24904,23 +24914,32 @@ index 332aa2d..555b50d 100644 {"atmega48a", AVR_ISA_AVR4, bfd_mach_avr4}, + {"atmega48pa", AVR_ISA_AVR4, bfd_mach_avr4}, {"atmega48p", AVR_ISA_AVR4, bfd_mach_avr4}, ++ {"atmega48pb", AVR_ISA_AVR4, bfd_mach_avr4}, {"atmega88", AVR_ISA_AVR4, bfd_mach_avr4}, {"atmega88a", AVR_ISA_AVR4, bfd_mach_avr4}, -@@ -159,6 +175,13 @@ static struct mcu_type_s mcu_types[] = + {"atmega88p", AVR_ISA_AVR4, bfd_mach_avr4}, + {"atmega88pa", AVR_ISA_AVR4, bfd_mach_avr4}, ++ {"atmega88pb", AVR_ISA_AVR4, bfd_mach_avr4}, + {"atmega8515", AVR_ISA_M8, bfd_mach_avr4}, + {"atmega8535", AVR_ISA_M8, bfd_mach_avr4}, + {"atmega8hva", AVR_ISA_AVR4, bfd_mach_avr4}, +@@ -159,6 +176,15 @@ static struct mcu_type_s mcu_types[] = {"at90pwm3", AVR_ISA_AVR4, bfd_mach_avr4}, {"at90pwm3b", AVR_ISA_AVR4, bfd_mach_avr4}, {"at90pwm81", AVR_ISA_AVR4, bfd_mach_avr4}, + {"at90pwm161", AVR_ISA_AVR5, bfd_mach_avr5}, + {"ata5702m322",AVR_ISA_AVR5, bfd_mach_avr5}, ++ {"ata5782", AVR_ISA_AVR5, bfd_mach_avr5}, + {"ata5790", AVR_ISA_AVR5, bfd_mach_avr5}, + {"ata5790n", AVR_ISA_AVR5, bfd_mach_avr5}, + {"ata5795", AVR_ISA_AVR5, bfd_mach_avr5}, ++ {"ata5831", AVR_ISA_AVR5, bfd_mach_avr5}, + {"ata6613c", AVR_ISA_AVR5, bfd_mach_avr5}, + {"ata6614q", AVR_ISA_AVR5, bfd_mach_avr5}, {"atmega16", AVR_ISA_AVR5, bfd_mach_avr5}, {"atmega16a", AVR_ISA_AVR5, bfd_mach_avr5}, {"atmega161", AVR_ISA_M161, bfd_mach_avr5}, -@@ -166,17 +189,21 @@ static struct mcu_type_s mcu_types[] = +@@ -166,17 +192,22 @@ static struct mcu_type_s mcu_types[] = {"atmega163", AVR_ISA_M161, bfd_mach_avr5}, {"atmega164a", AVR_ISA_AVR5, bfd_mach_avr5}, {"atmega164p", AVR_ISA_AVR5, bfd_mach_avr5}, @@ -24933,6 +24952,7 @@ index 332aa2d..555b50d 100644 {"atmega168a", AVR_ISA_AVR5, bfd_mach_avr5}, {"atmega168p", AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega168pa",AVR_ISA_AVR5, bfd_mach_avr5}, ++ {"atmega168pb",AVR_ISA_AVR5, bfd_mach_avr5}, {"atmega169", AVR_ISA_AVR5, bfd_mach_avr5}, {"atmega169a", AVR_ISA_AVR5, bfd_mach_avr5}, {"atmega169p", AVR_ISA_AVR5, bfd_mach_avr5}, @@ -24942,7 +24962,7 @@ index 332aa2d..555b50d 100644 {"atmega323", AVR_ISA_AVR5, bfd_mach_avr5}, {"atmega324a", AVR_ISA_AVR5, bfd_mach_avr5}, {"atmega324p", AVR_ISA_AVR5, bfd_mach_avr5}, -@@ -200,7 +227,10 @@ static struct mcu_type_s mcu_types[] = +@@ -200,7 +231,10 @@ static struct mcu_type_s mcu_types[] = {"atmega3290p",AVR_ISA_AVR5, bfd_mach_avr5}, {"atmega3290pa",AVR_ISA_AVR5, bfd_mach_avr5}, {"atmega406", AVR_ISA_AVR5, bfd_mach_avr5}, @@ -24953,7 +24973,7 @@ index 332aa2d..555b50d 100644 {"atmega640", AVR_ISA_AVR5, bfd_mach_avr5}, {"atmega644", AVR_ISA_AVR5, bfd_mach_avr5}, {"atmega644a", AVR_ISA_AVR5, bfd_mach_avr5}, -@@ -221,12 +251,13 @@ static struct mcu_type_s mcu_types[] = +@@ -221,12 +255,13 @@ static struct mcu_type_s mcu_types[] = {"atmega64rfr2",AVR_ISA_AVR5, bfd_mach_avr5}, {"atmega644rfr2",AVR_ISA_AVR5, bfd_mach_avr5}, {"atmega16hva",AVR_ISA_AVR5, bfd_mach_avr5}, @@ -24968,7 +24988,7 @@ index 332aa2d..555b50d 100644 {"at90can32" , AVR_ISA_AVR5, bfd_mach_avr5}, {"at90can64" , AVR_ISA_AVR5, bfd_mach_avr5}, {"at90pwm161", AVR_ISA_AVR5, bfd_mach_avr5}, -@@ -246,8 +277,10 @@ static struct mcu_type_s mcu_types[] = +@@ -246,8 +281,10 @@ static struct mcu_type_s mcu_types[] = {"at94k", AVR_ISA_94K, bfd_mach_avr5}, {"m3000", AVR_ISA_AVR5, bfd_mach_avr5}, {"atmega128", AVR_ISA_AVR51, bfd_mach_avr51}, @@ -24979,14 +24999,9 @@ index 332aa2d..555b50d 100644 {"atmega1284p",AVR_ISA_AVR51, bfd_mach_avr51}, {"atmega128rfa1",AVR_ISA_AVR51, bfd_mach_avr51}, {"atmega128rfr2",AVR_ISA_AVR51, bfd_mach_avr51}, -@@ -258,33 +291,68 @@ static struct mcu_type_s mcu_types[] = - {"atmega2560", AVR_ISA_AVR6, bfd_mach_avr6}, - {"atmega2561", AVR_ISA_AVR6, bfd_mach_avr6}, +@@ -260,31 +297,64 @@ static struct mcu_type_s mcu_types[] = {"atmega256rfr2", AVR_ISA_AVR6, bfd_mach_avr6}, -- {"atmega2564rfr2", AVR_ISA_AVR6, bfd_mach_avr6}, -+ {"atmega2564rfr2",AVR_ISA_AVR6, bfd_mach_avr6}, -+ {"ata5782", AVR_ISA_AVR7, bfd_mach_avr7}, -+ {"ata5831", AVR_ISA_AVR7, bfd_mach_avr7}, + {"atmega2564rfr2", AVR_ISA_AVR6, bfd_mach_avr6}, {"atxmega16a4", AVR_ISA_XMEGA, bfd_mach_avrxmega2}, + {"atxmega16a4u",AVR_ISA_XMEGAU, bfd_mach_avrxmega2}, + {"atxmega16c4", AVR_ISA_XMEGAU, bfd_mach_avrxmega2}, @@ -25007,7 +25022,7 @@ index 332aa2d..555b50d 100644 + {"atxmega64a4u",AVR_ISA_XMEGAU, bfd_mach_avrxmega4}, + {"atxmega64b1", AVR_ISA_XMEGAU, bfd_mach_avrxmega4}, + {"atxmega64b3", AVR_ISA_XMEGAU, bfd_mach_avrxmega4}, -+ {"atxmega64c3", AVR_ISA_XMEGAU, bfd_mach_avrxmega4}, ++ {"atxmega64c3", AVR_ISA_XMEGAU, bfd_mach_avrxmega4}, {"atxmega64d3", AVR_ISA_XMEGA, bfd_mach_avrxmega4}, + {"atxmega64d4", AVR_ISA_XMEGA, bfd_mach_avrxmega4}, {"atxmega64a1", AVR_ISA_XMEGA, bfd_mach_avrxmega5}, @@ -25026,8 +25041,7 @@ index 332aa2d..555b50d 100644 {"atxmega256a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6}, + {"atxmega256a3u",AVR_ISA_XMEGAU,bfd_mach_avrxmega6}, {"atxmega256a3b",AVR_ISA_XMEGA, bfd_mach_avrxmega6}, -- {"atxmega256a3bu",AVR_ISA_XMEGAU, bfd_mach_avrxmega6}, -+ {"atxmega256a3bu",AVR_ISA_XMEGAU,bfd_mach_avrxmega6}, + {"atxmega256a3bu",AVR_ISA_XMEGAU, bfd_mach_avrxmega6}, + {"atxmega256c3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6}, {"atxmega256d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6}, + {"atxmega384c3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6}, @@ -25051,12 +25065,12 @@ index 332aa2d..555b50d 100644 static struct mcu_type_s * avr_mcu = & default_mcu; /* AVR target-specific switches. */ -@@ -293,9 +361,11 @@ struct avr_opt_s +@@ -293,9 +363,11 @@ struct avr_opt_s int all_opcodes; /* -mall-opcodes: accept all known AVR opcodes. */ int no_skip_bug; /* -mno-skip-bug: no warnings for skipping 2-word insns. */ int no_wrap; /* -mno-wrap: reject rjmp/rcall with 8K wrap-around. */ -+ int link_relax; /* -mlink-relax: generate relocations for linker -+ relaxation. */ ++ int link_relax; /* -mlink-relax: generate relocations for linker ++ relaxation. */ }; -static struct avr_opt_s avr_opt = { 0, 0, 0 }; @@ -25064,7 +25078,7 @@ index 332aa2d..555b50d 100644 const char EXP_CHARS[] = "eE"; const char FLT_CHARS[] = "dD"; -@@ -353,17 +423,23 @@ static struct hash_control *avr_mod_hash; +@@ -353,17 +425,23 @@ static struct hash_control *avr_mod_hash; #define OPTION_MMCU 'm' enum options { @@ -25090,20 +25104,12 @@ index 332aa2d..555b50d 100644 { NULL, no_argument, NULL, 0 } }; -@@ -456,20 +532,26 @@ md_show_usage (FILE *stream) - " avr5 - enhanced AVR core with up to 64K program memory\n" - " avr51 - enhanced AVR core with up to 128K program memory\n" - " avr6 - enhanced AVR core with up to 256K program memory\n" -+ " avr7 - enhanced AVR core with up to 20K program memory\n" -+ " flash starting address is not zero\n" - " avrxmega2 - XMEGA, > 8K, < 64K FLASH, < 64K RAM\n" - " avrxmega3 - XMEGA, > 8K, <= 64K FLASH, > 64K RAM\n" - " avrxmega4 - XMEGA, > 64K, <= 128K FLASH, <= 64K RAM\n" +@@ -462,14 +540,17 @@ md_show_usage (FILE *stream) " avrxmega5 - XMEGA, > 64K, <= 128K FLASH, > 64K RAM\n" " avrxmega6 - XMEGA, > 128K, <= 256K FLASH, <= 64K RAM\n" " avrxmega7 - XMEGA, > 128K, <= 256K FLASH, > 64K RAM\n" -+ " avrtiny - AVR Tiny core\n" - " or immediate microcontroller name.\n")); +- " or immediate microcontroller name.\n")); ++ " avrtiny - AVR Tiny core with 16 gp registers\n")); fprintf (stream, - _(" -mall-opcodes accept all AVR opcodes, even if not supported by MCU\n" + _(" -mlist-devices list all supported devices\n" @@ -25120,7 +25126,7 @@ index 332aa2d..555b50d 100644 } static void -@@ -515,12 +597,20 @@ md_parse_option (int c, char *arg) +@@ -515,12 +596,20 @@ md_parse_option (int c, char *arg) type - this for allows passing -mmcu=... via gcc ASM_SPEC as well as .arch ... in the asm output at the same time. */ if (avr_mcu == &default_mcu || avr_mcu->mach == mcu_types[i].mach) @@ -25142,7 +25148,7 @@ index 332aa2d..555b50d 100644 case OPTION_ALL_OPCODES: avr_opt.all_opcodes = 1; return 1; -@@ -530,6 +620,12 @@ md_parse_option (int c, char *arg) +@@ -530,6 +619,12 @@ md_parse_option (int c, char *arg) case OPTION_NO_WRAP: avr_opt.no_wrap = 1; return 1; @@ -25155,7 +25161,7 @@ index 332aa2d..555b50d 100644 } return 0; -@@ -580,6 +676,7 @@ md_begin (void) +@@ -580,6 +675,7 @@ md_begin (void) } bfd_set_arch_mach (stdoutput, TARGET_ARCH, avr_mcu->mach); @@ -25163,33 +25169,92 @@ index 332aa2d..555b50d 100644 } /* Resolve STR as a constant expression and return the result. -@@ -810,6 +907,12 @@ avr_operand (struct avr_opcodes_s *opcode, - str = input_line_pointer; - } - +@@ -789,29 +885,40 @@ avr_operand (struct avr_opcodes_s *opcode, + case 'a': + case 'v': + if (*str == 'r' || *str == 'R') +- { +- char r_name[20]; +- +- str = extract_word (str, r_name, sizeof (r_name)); +- op_mask = 0xff; +- if (ISDIGIT (r_name[1])) +- { +- if (r_name[2] == '\0') +- op_mask = r_name[1] - '0'; +- else if (r_name[1] != '0' +- && ISDIGIT (r_name[2]) +- && r_name[3] == '\0') +- op_mask = (r_name[1] - '0') * 10 + r_name[2] - '0'; +- } +- } ++ { ++ char r_name[20]; ++ str = extract_word (str, r_name, sizeof (r_name)); ++ op_mask = 0xff; ++ if (ISDIGIT (r_name[1])) ++ { ++ if (r_name[2] == '\0') ++ op_mask = r_name[1] - '0'; ++ else if (r_name[1] != '0' ++ && ISDIGIT (r_name[2]) ++ && r_name[3] == '\0') ++ op_mask = (r_name[1] - '0') * 10 + r_name[2] - '0'; ++ } ++ } + else +- { +- op_mask = avr_get_constant (str, 31); +- str = input_line_pointer; +- } ++ { ++ op_mask = avr_get_constant (str, 31); ++ str = input_line_pointer; ++ } ++ + if (avr_mcu->mach == bfd_mach_avrtiny) + { + if (op_mask < 16 || op_mask > 31) -+ as_bad (_("register not supported")); ++ { ++ as_bad (_("register name or number from 16 to 31 required")); ++ break; ++ } + } -+ - if (op_mask <= 31) - { ++ else if (op_mask > 31) ++ { ++ as_bad (_("register name or number from 0 to 31 required")); ++ break; ++ } + +- if (op_mask <= 31) +- { switch (*op) -@@ -948,6 +1051,12 @@ avr_operand (struct avr_opcodes_s *opcode, + { + case 'a': +@@ -839,9 +946,6 @@ avr_operand (struct avr_opcodes_s *opcode, + break; + } + break; +- } +- as_bad (_("register name or number from 0 to 31 required")); +- break; + + case 'e': + { +@@ -948,6 +1052,12 @@ avr_operand (struct avr_opcodes_s *opcode, &op_expr, FALSE, BFD_RELOC_16); break; + case 'j': + str = parse_exp (str, &op_expr); + fix_new_exp (frag_now, where, opcode->insn_size * 2, -+ &op_expr, FALSE, BFD_RELOC_AVR_7_LDS16); ++ &op_expr, FALSE, BFD_RELOC_AVR_LDS_STS_16); + break; + case 'M': { bfd_reloc_code_real_type r_type; -@@ -1143,6 +1252,53 @@ md_pcrel_from_section (fixS *fixp, segT sec) +@@ -1143,6 +1253,53 @@ md_pcrel_from_section (fixS *fixp, segT sec) return fixp->fx_frag->fr_address + fixp->fx_where; } @@ -25243,7 +25308,7 @@ index 332aa2d..555b50d 100644 /* GAS will call this for each fixup. It should store the correct value in the object file. */ -@@ -1166,11 +1322,46 @@ md_apply_fix (fixS *fixP, valueT * valP, segT seg) +@@ -1166,11 +1323,46 @@ md_apply_fix (fixS *fixP, valueT * valP, segT seg) fixP->fx_done = 1; } } @@ -25291,7 +25356,7 @@ index 332aa2d..555b50d 100644 switch (fixP->fx_r_type) { default: -@@ -1180,6 +1371,19 @@ md_apply_fix (fixS *fixP, valueT * valP, segT seg) +@@ -1180,6 +1372,19 @@ md_apply_fix (fixS *fixP, valueT * valP, segT seg) case BFD_RELOC_AVR_13_PCREL: case BFD_RELOC_32: case BFD_RELOC_16: @@ -25311,24 +25376,29 @@ index 332aa2d..555b50d 100644 case BFD_RELOC_AVR_CALL: break; } -@@ -1256,6 +1460,17 @@ md_apply_fix (fixS *fixP, valueT * valP, segT seg) +@@ -1256,11 +1461,21 @@ md_apply_fix (fixS *fixP, valueT * valP, segT seg) bfd_putl16 ((bfd_vma) insn | LDI_IMMEDIATE (value), where); break; -+ case BFD_RELOC_AVR_7_LDS16: -+ if ((value < 0x40) || (value > 0xBF)) -+ as_warn_where (fixP->fx_file, fixP->fx_line, -+ _("operand out of range: 0x%lx"), -+ (unsigned long)value); -+ insn |= value & 0xF; -+ insn |= (value & 0x30) << 5; -+ insn |= (value & 0x40) << 2; -+ bfd_putl16 ((bfd_vma) insn, where); -+ break; ++ case BFD_RELOC_AVR_LDS_STS_16: ++ if ((value < 0x40) || (value > 0xBF)) ++ as_warn_where (fixP->fx_file, fixP->fx_line, ++ _("operand out of range: 0x%lx"), ++ (unsigned long)value); ++ insn |= ((value & 0xF) | ((value & 0x30) << 5) | ((value & 0x40) << 2)); ++ bfd_putl16 ((bfd_vma) insn, where); ++ break; + case BFD_RELOC_AVR_6: if ((value > 63) || (value < 0)) as_bad_where (fixP->fx_file, fixP->fx_line, + _("operand out of range: %ld"), value); +- bfd_putl16 ((bfd_vma) insn | ((value & 7) | ((value & (3 << 3)) << 7) | ((value & (1 << 5)) << 8)), where); ++ bfd_putl16 ((bfd_vma) insn | ((value & 7) | ((value & (3 << 3)) << 7) ++ | ((value & (1 << 5)) << 8)), where); + break; + + case BFD_RELOC_AVR_6_ADIW: @@ -1435,6 +1650,28 @@ md_assemble (char *str) opcode = (struct avr_opcodes_s *) hash_find (avr_hash, op); @@ -25336,11 +25406,11 @@ index 332aa2d..555b50d 100644 + if (opcode && !avr_opt.all_opcodes) + { + /* Check if the instruction's ISA bit is ON in the ISA bits of the part -+ specified by the user. If not look for other instructions specifica- -+ -tions with same mnemonic who's ISA bits matches. ++ specified by the user. If not look for other instructions ++ specifications with same mnemonic who's ISA bits matches. + + This requires include/opcode/avr.h to have the instructions with -+ same mnenomic to be specified in sequence. */ ++ same mnenomic to be specified in sequence. */ + + while ((opcode->isa & avr_mcu->isa) != opcode->isa) + { @@ -29717,7 +29787,7 @@ index 590528c..6147de1 100755 if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5 diff --git a/gas/doc/c-avr.texi b/gas/doc/c-avr.texi -index 213e82c..c35e40d 100644 +index 213e82c..e85c478 100644 --- a/gas/doc/c-avr.texi +++ b/gas/doc/c-avr.texi @@ -43,9 +43,9 @@ at90s8535). @@ -29733,7 +29803,7 @@ index 213e82c..c35e40d 100644 Instruction set avr3 is for the classic AVR core with up to 128K program memory space (MCU types: at43usb355, at76c711). -@@ -54,64 +54,73 @@ Instruction set avr31 is for the classic AVR core with exactly 128K program +@@ -54,64 +54,76 @@ Instruction set avr31 is for the classic AVR core with exactly 128K program memory space (MCU types: atmega103, at43usb320). Instruction set avr35 is for classic AVR core plus MOVW, CALL, and JMP @@ -29746,11 +29816,10 @@ index 213e82c..c35e40d 100644 -memory space (MCU types: atmega48, atmega48a, atmega48p, atmega8, atmega88, -atmega88a, atmega88p, atmega88pa, atmega8515, atmega8535, atmega8hva, at90pwm1, -at90pwm2, at90pwm2b, at90pwm3, at90pwm3b, at90pwm81, ata6289). -+memory space (MCU types: atmega48, atmega48a, atmega48pa, atmega48p, atmega8, -+M -+atmega8a, atmega88, atmega88a, atmega88p, atmega88pa, atmega8515, atmega8535, -+atmega8hva, at90pwm1, at90pwm2, at90pwm2b, at90pwm3, at90pwm3b, at90pwm81, -+ata6285, ata6286, ata6289, ata6612c). ++memory space (MCU types: atmega48, atmega48a, atmega48p, atmega48pa, atmega48pb, ++atmega8, atmega8a, atmega88, atmega88a, atmega88p, atmega88pa, atmega88pb, ++atmega8515, atmega8535, atmega8hva, at90pwm1, at90pwm2, at90pwm2b, at90pwm3, ++at90pwm3b, at90pwm81, ata6285, ata6286, ata6289, ata6612c). Instruction set avr5 is for the enhanced AVR core with up to 128K program -memory space (MCU types: atmega16, atmega16a, atmega161, atmega162, @@ -29769,80 +29838,103 @@ index 213e82c..c35e40d 100644 -at90can64, at90pwm161, at90pwm216, at90pwm316, atmega32c1, atmega64c1, -atmega16m1, atmega32m1, atmega64m1, atmega16u4, atmega32u4, -atmega32u6, at90usb646, at90usb647, at94k, at90scr100). -+memory space (MCU types: at90pwm161, atmega16, atmega16a, atmega161, atmega162, -+atmega163, atmega164a, atmega164p, atmega164pa, atmega165, atmega165a, -+atmega165p, atmega165pa, atmega168, atmega168a, atmega168p, atmega168pa, -+atmega169, atmega169a, atmega169p, atmega169pa, atmega32, atmega323, atmega324a, -+atmega324p, atmega324pa, atmega325, atmega325a, atmega32, atmega32a, atmega323, -+atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, atmega325p, -+atmega325p, atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, -+atmega328, atmega328p, atmega329, atmega329a, atmega329p, atmega329pa, -+atmega3290a, atmega3290p, atmega3290pa, atmega406, atmega64, atmega64a, -+atmega64rfr2, atmega644rfr2, atmega640, atmega644, atmega644a, atmega644p, -+atmega644pa, atmega645, atmega645a, atmega645p, atmega6450, atmega6450a, -+atmega6450p, atmega649, atmega649a, atmega649p, atmega6490, atmega6490a, -+atmega6490p, atmega16hva, atmega16hva2, atmega16hvb, atmega16hvbrevb, -+atmega32hvb, atmega32hvbrevb, atmega64hve, atmega64hve2, at90can32, at90can64, -+at90pwm161, at90pwm216, at90pwm316, atmega32c1, atmega64c1, atmega16m1, -+atmega32m1, atmega64m1, atmega16u4, atmega32u4, atmega32u6, at90usb646, -+at90usb647, at94k, at90scr100, ata5790, ata5790n, ata5795, ata6614q, ata6613c, ata5702m322). - - Instruction set avr51 is for the enhanced AVR core with exactly 128K program +- +-Instruction set avr51 is for the enhanced AVR core with exactly 128K program -memory space (MCU types: atmega128, atmega1280, atmega1281, atmega1284p, -atmega128rfa1, -atmega128rfr2, atmega1284rfr2, -+memory space (MCU types: atmega128, atmega128a, atmega1280, atmega1281, -+atmega1284, atmega1284p, atmega128rfa1, atmega128rfr2, atmega1284rfr2, - at90can128, at90usb1286, at90usb1287, m3000). - - Instruction set avr6 is for the enhanced AVR core with a 3-byte PC (MCU types: +-at90can128, at90usb1286, at90usb1287, m3000). +- +-Instruction set avr6 is for the enhanced AVR core with a 3-byte PC (MCU types: -atmega2560, atmega2561, -atmega256rfr2, atmega2564rfr2). -+atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2). -+ -+Instruction set avr7 is for the enhanced AVR core with 20K flash which starts -+from 0x8000 (MCU types: ata5782, ata5831) - - Instruction set avrxmega2 is for the XMEGA AVR core with 8K to 64K program +- +-Instruction set avrxmega2 is for the XMEGA AVR core with 8K to 64K program -memory space and less than 64K data space (MCU types: atxmega16a4, atxmega16d4, -atxmega16x1, atxmega32a4, atxmega32d4, atxmega32x1). -+memory space and less than 64K data space (MCU types: atxmega16a4, atxmega16a4u, -+atxmega16c4, atxmega16d4, atxmega16x1, atxmega32a4, atxmega32a4u, atxmega32c3, -+atxmega32c4, atxmega32d3, txmega32d4, atxmega16e5, atxmega8e5, atxmega32e5, -+atxmega32x1). - - Instruction set avrxmega3 is for the XMEGA AVR core with 8K to 64K program - memory space and greater than 64K data space (MCU types: none). - - Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K program +- +-Instruction set avrxmega3 is for the XMEGA AVR core with 8K to 64K program +-memory space and greater than 64K data space (MCU types: none). +- +-Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K program -memory space and less than 64K data space (MCU types: atxmega64a3, atxmega64d3). -+memory space and less than 64K data space (MCU types: atxmega64a3, atxmega64a3u, -+atxmega64a4u, atxmega64b1, atxmega64b3, atxmega64c3, atxmega64d3, atxmega64d4). - - Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K program - memory space and greater than 64K data space (MCU types: atxmega64a1, - atxmega64a1u). - +- +-Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K program +-memory space and greater than 64K data space (MCU types: atxmega64a1, +-atxmega64a1u). +- -Instruction set avrxmega6 is for the XMEGA AVR core with up to 256K program -memory space and less than 64K data space (MCU types: atxmega128a3, -atxmega128d3, atxmega192a3, atxmega128b1, atxmega192d3, atxmega256a3, -atxmega256a3b, atxmega256a3bu, atxmega192d3). -+Instruction set avrxmega6 is for the XMEGA AVR core with larger than 64K program -+memory space and less than 64K data space (MCU types: atxmega128a3, -+atxmega128a3u, atxmega128c3, atxmega128d3, atxmega128d4, atxmega192a3, -+atxmega192a3u, atxmega128b1, atxmega128b3, atxmega192c3, atxmega192d3, -+atxmega256a3, atxmega256a3u, atxmega256a3b, atxmega256a3bu, atxmega256c3, -+atxmega256d3, atxmega384c3, atxmega256d3). - +- -Instruction set avrxmega7 is for the XMEGA AVR core with up to 256K program -+Instruction set avrxmega7 is for the XMEGA AVR core with larger than 64K program - memory space and greater than 64K data space (MCU types: atxmega128a1, +-memory space and greater than 64K data space (MCU types: atxmega128a1, -atxmega128a1u). -+atxmega128a1u, atxmega128a4u). ++memory space (MCU types: at90pwm161, atmega16, atmega16a, atmega161, atmega162, ++atmega163, atmega164a, atmega164p, atmega164pa, atmega165, atmega165a, ++atmega165p, atmega165pa, atmega168, atmega168a, atmega168p, atmega168pa, ++atmega168pb, atmega169, atmega169a, atmega169p, atmega169pa, atmega32, ++atmega323, atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, ++atmega32, atmega32a, atmega323, atmega324a, atmega324p, atmega324pa, atmega325, ++atmega325a, atmega325p, atmega325pa, atmega3250, atmega3250a, atmega3250p, ++atmega3250pa, atmega328, atmega328p, atmega329, atmega329a, atmega329p, ++atmega329pa, atmega3290a, atmega3290p, atmega3290pa, atmega406, atmega64, ++atmega64a, atmega64rfr2, atmega644rfr2, atmega640, atmega644, atmega644a, ++atmega644p, atmega644pa, atmega645, atmega645a, atmega645p, atmega6450, ++atmega6450a, atmega6450p, atmega649, atmega649a, atmega649p, atmega6490, ++atmega6490a, atmega6490p, atmega16hva, atmega16hva2, atmega16hvb, ++atmega16hvbrevb, atmega32hvb, atmega32hvbrevb, atmega64hve, atmega64hve2, ++at90can32, at90can64, at90pwm161, at90pwm216, at90pwm316, atmega32c1, ++atmega64c1, atmega16m1, atmega32m1, atmega64m1, atmega16u4, atmega32u4, ++atmega32u6, at90usb646, at90usb647, at94k, at90scr100, ata5790, ata5790n, ++ata5795, ata6614q, ata6613c, ata5702m322). ++ ++Instruction set avr51 is for the enhanced AVR core with exactly 128K ++program memory space (MCU types: atmega128, atmega128a, atmega1280, ++atmega1281, atmega1284, atmega1284p, atmega128rfa1, atmega128rfr2, ++atmega1284rfr2, at90can128, at90usb1286, at90usb1287, m3000). ++ ++Instruction set avr6 is for the enhanced AVR core with a 3-byte PC ++(MCU types: atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2). ++ ++Instruction set avrxmega2 is for the XMEGA AVR core with 8K to 64K ++program memory space and less than 64K data space (MCU types: ++atxmega16a4, atxmega16a4u, atxmega16c4, atxmega16d4, atxmega16x1, ++atxmega32a4, atxmega32a4u, atxmega32c3, atxmega32c4, atxmega32d3, ++atxmega32d4, atxmega16e5, atxmega8e5, atxmega32e5, atxmega32x1). ++ ++Instruction set avrxmega3 is for the XMEGA AVR core with 8K to 64K ++program memory space and greater than 64K data space (MCU types: ++none). ++ ++Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K ++program memory space and less than 64K data space (MCU types: ++atxmega64a3, atxmega64a3u, atxmega64a4u, atxmega64b1, atxmega64b3, ++atxmega64c3, atxmega64d3, atxmega64d4). ++ ++Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K ++program memory space and greater than 64K data space (MCU types: ++atxmega64a1, atxmega64a1u). ++ ++Instruction set avrxmega6 is for the XMEGA AVR core with larger than ++64K program memory space and less than 64K data space (MCU types: ++atxmega128a3, atxmega128a3u, atxmega128c3, atxmega128d3, atxmega128d4, ++atxmega192a3, atxmega192a3u, atxmega128b1, atxmega128b3, atxmega192c3, ++atxmega192d3, atxmega256a3, atxmega256a3u, atxmega256a3b, ++atxmega256a3bu, atxmega256c3, atxmega256d3, atxmega384c3, ++atxmega256d3). ++ ++Instruction set avrxmega7 is for the XMEGA AVR core with larger than ++64K program memory space and greater than 64K data space (MCU types: ++atxmega128a1, atxmega128a1u, atxmega128a4u). ++ ++Instruction set avrtiny is for the ATtiny4/5/9/10/20/40 ++microcontrollers. @cindex @code{-mall-opcodes} command line option, AVR @item -mall-opcodes -@@ -125,6 +134,10 @@ This option disable warnings for skipping two-word instructions. +@@ -125,6 +137,10 @@ This option disable warnings for skipping two-word instructions. @item -mno-wrap This option reject @code{rjmp/rcall} instructions with 8K wrap-around. @@ -33111,10 +33203,10 @@ index 2567991..7d3e0c0 100644 #undef _FILE_OFFSET_BITS diff --git a/include/elf/avr.h b/include/elf/avr.h -index b45d902..1a29f4c 100644 +index b45d902..f919616 100644 --- a/include/elf/avr.h +++ b/include/elf/avr.h -@@ -41,13 +41,15 @@ +@@ -41,13 +41,14 @@ #define E_AVR_MACH_AVR5 5 #define E_AVR_MACH_AVR51 51 #define E_AVR_MACH_AVR6 6 @@ -33125,8 +33217,7 @@ index b45d902..1a29f4c 100644 -#define E_AVR_MACH_XMEGA5 105 -#define E_AVR_MACH_XMEGA6 106 -#define E_AVR_MACH_XMEGA7 107 -+#define E_AVR_MACH_AVR7 7 -+#define E_AVR_MACH_AVRTINY 90 ++#define E_AVR_MACH_AVRTINY 100 +#define E_AVR_MACH_XMEGA1 101 +#define E_AVR_MACH_XMEGA2 102 +#define E_AVR_MACH_XMEGA3 103 @@ -33137,21 +33228,29 @@ index b45d902..1a29f4c 100644 /* Relocations. */ START_RELOC_NUMBERS (elf_avr_reloc_type) -@@ -81,6 +83,10 @@ START_RELOC_NUMBERS (elf_avr_reloc_type) +@@ -81,6 +82,10 @@ START_RELOC_NUMBERS (elf_avr_reloc_type) RELOC_NUMBER (R_AVR_8_LO8, 27) RELOC_NUMBER (R_AVR_8_HI8, 28) RELOC_NUMBER (R_AVR_8_HLO8, 29) -+ RELOC_NUMBER (R_AVR_7_LDS16, 30) -+ RELOC_NUMBER (R_AVR_DIFF8, 31) -+ RELOC_NUMBER (R_AVR_DIFF16, 32) -+ RELOC_NUMBER (R_AVR_DIFF32, 33) ++ RELOC_NUMBER (R_AVR_DIFF8, 30) ++ RELOC_NUMBER (R_AVR_DIFF16, 31) ++ RELOC_NUMBER (R_AVR_DIFF32, 32) ++ RELOC_NUMBER (R_AVR_LDS_STS_16, 33) END_RELOC_NUMBERS (R_AVR_max) #endif /* _ELF_AVR_H */ diff --git a/include/opcode/avr.h b/include/opcode/avr.h -index f1d73ad..2b55fab 100644 +index f1d73ad..5683848 100644 --- a/include/opcode/avr.h +++ b/include/opcode/avr.h +@@ -1,6 +1,6 @@ + /* Opcode table for the Atmel AVR micro controllers. + +- Copyright 2000, 2001, 2004, 2006, 2008, 2010, 2012 Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + Contributed by Denis Chertykov + + This program is free software; you can redistribute it and/or modify @@ -22,6 +22,7 @@ #define AVR_ISA_LPM 0x0002 /* device has LPM */ #define AVR_ISA_LPMX 0x0004 /* device has LPM Rd,Z[+] */ @@ -33168,19 +33267,26 @@ index f1d73ad..2b55fab 100644 /* For the attiny26 which is missing LPM Rd,Z+. */ #define AVR_ISA_2xxe (AVR_ISA_2xxx | AVR_ISA_LPMX) #define AVR_ISA_RF401 (AVR_ISA_2xxx | AVR_ISA_MOVW | AVR_ISA_LPMX) -@@ -72,6 +74,11 @@ +@@ -72,6 +74,9 @@ AVR_ISA_ELPM | AVR_ISA_ELPMX | AVR_ISA_SPM | \ AVR_ISA_BRK | AVR_ISA_EIND | AVR_ISA_MOVW) -+#define AVR_ISA_AVR7 (AVR_ISA_M8 | AVR_ISA_MEGA | AVR_ISA_BRK ) -+ +#define AVR_ISA_AVRTINY (AVR_ISA_1200 | AVR_ISA_BRK | AVR_ISA_SRAM | \ + AVR_ISA_TINY) + #define REGISTER_P(x) ((x) == 'r' \ || (x) == 'd' \ || (x) == 'w' \ -@@ -110,6 +117,7 @@ +@@ -94,7 +99,7 @@ + `ld r,b' or `st b,r' respectively - next opcode entry)? */ + #define AVR_DISP0_P(x) (((x) & 0xFC07) == 0x8000) + +-/* constraint letters ++/* Constraint letters: + r - any register + d - `ldi' register (r16-r31) + v - `movw' even register (r0, r2, ..., r28, r30) +@@ -110,6 +115,7 @@ p - Port address value from 0 to 31. (cbi, sbi, sbic, sbis) K - immediate value from 0 to 63 (used in `adiw', `sbiw') i - immediate value @@ -33188,7 +33294,12 @@ index f1d73ad..2b55fab 100644 l - signed pc relative offset from -64 to 63 L - signed pc relative offset from -2048 to 2047 h - absolute code address (call, jmp) -@@ -160,8 +168,8 @@ AVR_INSN (sez, "", "1001010000011000", 1, AVR_ISA_1200, 0x9418) +@@ -156,12 +162,12 @@ AVR_INSN (set, "", "1001010001101000", 1, AVR_ISA_1200, 0x9468) + AVR_INSN (sev, "", "1001010000111000", 1, AVR_ISA_1200, 0x9438) + AVR_INSN (sez, "", "1001010000011000", 1, AVR_ISA_1200, 0x9418) + +- /* Same as {cl,se}[chinstvz] above. */ ++/* Same as {cl,se}[chinstvz] above. */ AVR_INSN (bclr, "S", "100101001SSS1000", 1, AVR_ISA_1200, 0x9488) AVR_INSN (bset, "S", "100101000SSS1000", 1, AVR_ISA_1200, 0x9408) @@ -33199,7 +33310,25 @@ index f1d73ad..2b55fab 100644 AVR_INSN (lpm, "?", "1001010111001000", 1, AVR_ISA_TINY1,0x95c8) AVR_INSN (lpm, "r,z", "1001000ddddd010+", 1, AVR_ISA_LPMX, 0x9004) -@@ -261,8 +269,8 @@ AVR_INSN (dec, "r", "1001010rrrrr1010", 1, AVR_ISA_1200, 0x940a) +@@ -190,7 +196,7 @@ AVR_INSN (or, "r,r", "001010rdddddrrrr", 1, AVR_ISA_1200, 0x2800) + AVR_INSN (sbc, "r,r", "000010rdddddrrrr", 1, AVR_ISA_1200, 0x0800) + AVR_INSN (sub, "r,r", "000110rdddddrrrr", 1, AVR_ISA_1200, 0x1800) + +- /* Shorthand for {eor,add,adc,and} r,r above. */ ++/* Shorthand for {eor,add,adc,and} r,r above. */ + AVR_INSN (clr, "r=r", "001001rdddddrrrr", 1, AVR_ISA_1200, 0x2400) + AVR_INSN (lsl, "r=r", "000011rdddddrrrr", 1, AVR_ISA_1200, 0x0c00) + AVR_INSN (rol, "r=r", "000111rdddddrrrr", 1, AVR_ISA_1200, 0x1c00) +@@ -245,7 +251,7 @@ AVR_INSN (brts, "l", "111100lllllll110", 1, AVR_ISA_1200, 0xf006) + AVR_INSN (brvc, "l", "111101lllllll011", 1, AVR_ISA_1200, 0xf403) + AVR_INSN (brvs, "l", "111100lllllll011", 1, AVR_ISA_1200, 0xf003) + +- /* Same as br?? above. */ ++/* Same as br?? above. */ + AVR_INSN (brbc, "s,l", "111101lllllllsss", 1, AVR_ISA_1200, 0xf400) + AVR_INSN (brbs, "s,l", "111100lllllllsss", 1, AVR_ISA_1200, 0xf000) + +@@ -261,18 +267,18 @@ AVR_INSN (dec, "r", "1001010rrrrr1010", 1, AVR_ISA_1200, 0x940a) AVR_INSN (inc, "r", "1001010rrrrr0011", 1, AVR_ISA_1200, 0x9403) AVR_INSN (lsr, "r", "1001010rrrrr0110", 1, AVR_ISA_1200, 0x9406) AVR_INSN (neg, "r", "1001010rrrrr0001", 1, AVR_ISA_1200, 0x9401) @@ -33210,7 +33339,19 @@ index f1d73ad..2b55fab 100644 AVR_INSN (ror, "r", "1001010rrrrr0111", 1, AVR_ISA_1200, 0x9407) AVR_INSN (swap, "r", "1001010rrrrr0010", 1, AVR_ISA_1200, 0x9402) -@@ -280,8 +288,10 @@ AVR_INSN (fmul, "a,a", "000000110ddd1rrr", 1, AVR_ISA_MUL, 0x0308) +- /* Atomic memory operations for XMEGA. List before `sts'. */ ++/* Atomic memory operations for XMEGA. List before `sts'. */ + AVR_INSN (xch, "z,r", "1001001rrrrr0100", 1, AVR_ISA_RMW, 0x9204) + AVR_INSN (las, "z,r", "1001001rrrrr0101", 1, AVR_ISA_RMW, 0x9205) + AVR_INSN (lac, "z,r", "1001001rrrrr0110", 1, AVR_ISA_RMW, 0x9206) + AVR_INSN (lat, "z,r", "1001001rrrrr0111", 1, AVR_ISA_RMW, 0x9207) + +- /* Known to be decoded as `nop' by the old core. */ ++/* Known to be decoded as `nop' by the old core. */ + AVR_INSN (movw, "v,v", "00000001ddddrrrr", 1, AVR_ISA_MOVW, 0x0100) + AVR_INSN (muls, "d,d", "00000010ddddrrrr", 1, AVR_ISA_MUL, 0x0200) + AVR_INSN (mulsu,"a,a", "000000110ddd0rrr", 1, AVR_ISA_MUL, 0x0300) +@@ -280,21 +286,23 @@ AVR_INSN (fmul, "a,a", "000000110ddd1rrr", 1, AVR_ISA_MUL, 0x0308) AVR_INSN (fmuls,"a,a", "000000111ddd0rrr", 1, AVR_ISA_MUL, 0x0380) AVR_INSN (fmulsu,"a,a","000000111ddd1rrr", 1, AVR_ISA_MUL, 0x0388) @@ -33221,21 +33362,31 @@ index f1d73ad..2b55fab 100644 +AVR_INSN (lds, "d,j", "10100kkkddddkkkk", 1, AVR_ISA_TINY, 0xA000) +AVR_INSN (lds, "r,i", "1001000ddddd0000", 2, AVR_ISA_2xxx, 0x9000) - /* Special case for b+0, `e' must be next entry after `b', - b={Y=1,Z=0}, ee={X=11,Y=10,Z=00}, !=1 if -e or e+ or X. */ +- /* Special case for b+0, `e' must be next entry after `b', +- b={Y=1,Z=0}, ee={X=11,Y=10,Z=00}, !=1 if -e or e+ or X. */ ++/* Special case for b+0, `e' must be next entry after `b', ++ b={Y=1,Z=0}, ee={X=11,Y=10,Z=00}, !=1 if -e or e+ or X. */ + AVR_INSN (ldd, "r,b", "10o0oo0dddddbooo", 1, AVR_ISA_2xxx, 0x8000) + AVR_INSN (ld, "r,e", "100!000dddddee-+", 1, AVR_ISA_1200, 0x8000) + AVR_INSN (std, "b,r", "10o0oo1rrrrrbooo", 1, AVR_ISA_2xxx, 0x8200) + AVR_INSN (st, "e,r", "100!001rrrrree-+", 1, AVR_ISA_1200, 0x8200) + +- /* These are for devices that don't exist yet +- (>128K program memory, PC = EIND:Z). */ ++/* These are for devices that don't exist yet ++ (>128K program memory, PC = EIND:Z). */ + AVR_INSN (eicall, "", "1001010100011001", 1, AVR_ISA_EIND, 0x9519) + AVR_INSN (eijmp, "", "1001010000011001", 1, AVR_ISA_EIND, 0x9419) + +-/* DES instruction for encryption and decryption */ ++/* DES instruction for encryption and decryption. */ + AVR_INSN (des, "E", "10010100EEEE1011", 1, AVR_ISA_DES, 0x940B) + diff --git a/ld/Makefile.am b/ld/Makefile.am -index b2b2a6e..e9ce514 100644 +index b2b2a6e..ddad575 100644 --- a/ld/Makefile.am +++ b/ld/Makefile.am -@@ -183,6 +183,7 @@ ALL_EMULATION_SOURCES = \ - eavr5.c \ - eavr51.c \ - eavr6.c \ -+ eavr7.c \ - eavrxmega1.c \ - eavrxmega2.c \ - eavrxmega3.c \ -@@ -190,6 +191,7 @@ ALL_EMULATION_SOURCES = \ +@@ -190,6 +190,7 @@ ALL_EMULATION_SOURCES = \ eavrxmega5.c \ eavrxmega6.c \ eavrxmega7.c \ @@ -33243,18 +33394,7 @@ index b2b2a6e..e9ce514 100644 ecoff_i860.c \ ecoff_sparc.c \ ecrisaout.c \ -@@ -845,6 +847,10 @@ eavr6.c: $(srcdir)/emulparams/avr6.sh $(srcdir)/emultempl/avrelf.em \ - $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ - ${GEN_DEPENDS} - ${GENSCRIPTS} avr6 "$(tdir_avr2)" -+eavr7.c: $(srcdir)/emulparams/avr7.sh $(srcdir)/emultempl/avrelf.em \ -+ $(ELF_DEPS) $(srcdir)/scripttempl/avr7.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} avr7 "$(tdir_avr2)" - eavrxmega1.c: $(srcdir)/emulparams/avrxmega1.sh \ - $(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ - ${GEN_DEPENDS} -@@ -873,6 +879,10 @@ eavrxmega7.c: $(srcdir)/emulparams/avrxmega7.sh \ +@@ -873,6 +874,10 @@ eavrxmega7.c: $(srcdir)/emulparams/avrxmega7.sh \ $(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ ${GEN_DEPENDS} ${GENSCRIPTS} avrxmega7 "$(tdir_avr2)" @@ -33266,303 +33406,10 @@ index b2b2a6e..e9ce514 100644 $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/i860coff.sc ${GEN_DEPENDS} ${GENSCRIPTS} coff_i860 "$(tdir_coff_i860)" diff --git a/ld/Makefile.in b/ld/Makefile.in -index b95a3d1..cc7cbb3 100644 +index b95a3d1..4c08767 100644 --- a/ld/Makefile.in +++ b/ld/Makefile.in -@@ -1,9 +1,8 @@ --# Makefile.in generated by automake 1.11.1 from Makefile.am. -+# Makefile.in generated by automake 1.14.1 from Makefile.am. - # @configure_input@ - --# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, --# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, --# Inc. -+# Copyright (C) 1994-2013 Free Software Foundation, Inc. -+ - # This Makefile.in is free software; the Free Software Foundation - # gives unlimited permission to copy and/or distribute it, - # with or without modifications, as long as this notice is preserved. -@@ -35,6 +34,51 @@ - - - VPATH = @srcdir@ -+am__is_gnu_make = test -n '$(MAKEFILE_LIST)' && test -n '$(MAKELEVEL)' -+am__make_running_with_option = \ -+ case $${target_option-} in \ -+ ?) ;; \ -+ *) echo "am__make_running_with_option: internal error: invalid" \ -+ "target option '$${target_option-}' specified" >&2; \ -+ exit 1;; \ -+ esac; \ -+ has_opt=no; \ -+ sane_makeflags=$$MAKEFLAGS; \ -+ if $(am__is_gnu_make); then \ -+ sane_makeflags=$$MFLAGS; \ -+ else \ -+ case $$MAKEFLAGS in \ -+ *\\[\ \ ]*) \ -+ bs=\\; \ -+ sane_makeflags=`printf '%s\n' "$$MAKEFLAGS" \ -+ | sed "s/$$bs$$bs[$$bs $$bs ]*//g"`;; \ -+ esac; \ -+ fi; \ -+ skip_next=no; \ -+ strip_trailopt () \ -+ { \ -+ flg=`printf '%s\n' "$$flg" | sed "s/$$1.*$$//"`; \ -+ }; \ -+ for flg in $$sane_makeflags; do \ -+ test $$skip_next = yes && { skip_next=no; continue; }; \ -+ case $$flg in \ -+ *=*|--*) continue;; \ -+ -*I) strip_trailopt 'I'; skip_next=yes;; \ -+ -*I?*) strip_trailopt 'I';; \ -+ -*O) strip_trailopt 'O'; skip_next=yes;; \ -+ -*O?*) strip_trailopt 'O';; \ -+ -*l) strip_trailopt 'l'; skip_next=yes;; \ -+ -*l?*) strip_trailopt 'l';; \ -+ -[dEDm]) skip_next=yes;; \ -+ -[JT]) skip_next=yes;; \ -+ esac; \ -+ case $$flg in \ -+ *$$target_option*) has_opt=yes; break;; \ -+ esac; \ -+ done; \ -+ test $$has_opt = yes -+am__make_dryrun = (target_option=n; $(am__make_running_with_option)) -+am__make_keepgoing = (target_option=k; $(am__make_running_with_option)) - pkgdatadir = $(datadir)/@PACKAGE@ - pkgincludedir = $(includedir)/@PACKAGE@ - pkglibdir = $(libdir)/@PACKAGE@ -@@ -60,12 +104,12 @@ bin_PROGRAMS = ld-new$(EXEEXT) - # though, so we use a bogus condition. - @GENINSRC_NEVER_TRUE@am__append_1 = ld.info - subdir = . --DIST_COMMON = NEWS README ChangeLog $(srcdir)/Makefile.in \ -- $(srcdir)/Makefile.am $(top_srcdir)/configure \ -- $(am__configure_deps) $(srcdir)/config.in \ -- $(srcdir)/../mkinstalldirs $(top_srcdir)/po/Make-in ldgram.h \ -- ldgram.c deffilep.h deffilep.c ldlex.c $(srcdir)/../depcomp \ -- $(srcdir)/../ylwrap $(ld_TEXINFOS) -+DIST_COMMON = $(srcdir)/Makefile.in $(srcdir)/Makefile.am \ -+ $(top_srcdir)/configure $(am__configure_deps) \ -+ $(srcdir)/config.in $(top_srcdir)/../mkinstalldirs \ -+ $(top_srcdir)/po/Make-in ldgram.h ldgram.c deffilep.h \ -+ deffilep.c ldlex.c $(top_srcdir)/../depcomp \ -+ $(top_srcdir)/../ylwrap $(ld_TEXINFOS) - ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 - am__aclocal_m4_deps = $(top_srcdir)/../bfd/acinclude.m4 \ - $(top_srcdir)/../config/zlib.m4 \ -@@ -96,9 +140,14 @@ libldtestplug_la_LIBADD = - @ENABLE_PLUGINS_TRUE@am_libldtestplug_la_OBJECTS = \ - @ENABLE_PLUGINS_TRUE@ libldtestplug_la-testplug.lo - libldtestplug_la_OBJECTS = $(am_libldtestplug_la_OBJECTS) --libldtestplug_la_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ -- $(LIBTOOLFLAGS) --mode=link $(CCLD) $(libldtestplug_la_CFLAGS) \ -- $(CFLAGS) $(libldtestplug_la_LDFLAGS) $(LDFLAGS) -o $@ -+AM_V_lt = $(am__v_lt_@AM_V@) -+am__v_lt_ = $(am__v_lt_@AM_DEFAULT_V@) -+am__v_lt_0 = --silent -+am__v_lt_1 = -+libldtestplug_la_LINK = $(LIBTOOL) $(AM_V_lt) --tag=CC \ -+ $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=link $(CCLD) \ -+ $(libldtestplug_la_CFLAGS) $(CFLAGS) \ -+ $(libldtestplug_la_LDFLAGS) $(LDFLAGS) -o $@ - @ENABLE_PLUGINS_TRUE@am_libldtestplug_la_rpath = - am__installdirs = "$(DESTDIR)$(bindir)" "$(DESTDIR)$(infodir)" \ - "$(DESTDIR)$(man1dir)" -@@ -112,30 +161,89 @@ am_ld_new_OBJECTS = ldgram.$(OBJEXT) ldlex-wrapper.$(OBJEXT) \ - $(am__objects_1) - ld_new_OBJECTS = $(am_ld_new_OBJECTS) - am__DEPENDENCIES_1 = -+AM_V_P = $(am__v_P_@AM_V@) -+am__v_P_ = $(am__v_P_@AM_DEFAULT_V@) -+am__v_P_0 = false -+am__v_P_1 = : -+AM_V_GEN = $(am__v_GEN_@AM_V@) -+am__v_GEN_ = $(am__v_GEN_@AM_DEFAULT_V@) -+am__v_GEN_0 = @echo " GEN " $@; -+am__v_GEN_1 = -+AM_V_at = $(am__v_at_@AM_V@) -+am__v_at_ = $(am__v_at_@AM_DEFAULT_V@) -+am__v_at_0 = @ -+am__v_at_1 = - DEFAULT_INCLUDES = -I.@am__isrc@ - depcomp = $(SHELL) $(top_srcdir)/../depcomp - am__depfiles_maybe = depfiles - am__mv = mv -f - COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ - $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) --LTCOMPILE = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ -- --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \ -- $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -+LTCOMPILE = $(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) \ -+ $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) \ -+ $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) \ -+ $(AM_CFLAGS) $(CFLAGS) -+AM_V_CC = $(am__v_CC_@AM_V@) -+am__v_CC_ = $(am__v_CC_@AM_DEFAULT_V@) -+am__v_CC_0 = @echo " CC " $@; -+am__v_CC_1 = - CCLD = $(CC) --LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ -- --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \ -- $(LDFLAGS) -o $@ -+LINK = $(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) \ -+ $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ -+ $(AM_LDFLAGS) $(LDFLAGS) -o $@ -+AM_V_CCLD = $(am__v_CCLD_@AM_V@) -+am__v_CCLD_ = $(am__v_CCLD_@AM_DEFAULT_V@) -+am__v_CCLD_0 = @echo " CCLD " $@; -+am__v_CCLD_1 = - @MAINTAINER_MODE_FALSE@am__skiplex = test -f $@ || --LEXCOMPILE = $(LEX) $(LFLAGS) $(AM_LFLAGS) --LTLEXCOMPILE = $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ -- --mode=compile $(LEX) $(LFLAGS) $(AM_LFLAGS) -+LEXCOMPILE = $(LEX) $(AM_LFLAGS) $(LFLAGS) -+LTLEXCOMPILE = $(LIBTOOL) $(AM_V_lt) $(AM_LIBTOOLFLAGS) \ -+ $(LIBTOOLFLAGS) --mode=compile $(LEX) $(AM_LFLAGS) $(LFLAGS) -+AM_V_LEX = $(am__v_LEX_@AM_V@) -+am__v_LEX_ = $(am__v_LEX_@AM_DEFAULT_V@) -+am__v_LEX_0 = @echo " LEX " $@; -+am__v_LEX_1 = - YLWRAP = $(top_srcdir)/../ylwrap - @MAINTAINER_MODE_FALSE@am__skipyacc = test -f $@ || --YACCCOMPILE = $(YACC) $(YFLAGS) $(AM_YFLAGS) --LTYACCCOMPILE = $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ -- --mode=compile $(YACC) $(YFLAGS) $(AM_YFLAGS) -+am__yacc_c2h = sed -e s/cc$$/hh/ -e s/cpp$$/hpp/ -e s/cxx$$/hxx/ \ -+ -e s/c++$$/h++/ -e s/c$$/h/ -+YACCCOMPILE = $(YACC) $(AM_YFLAGS) $(YFLAGS) -+LTYACCCOMPILE = $(LIBTOOL) $(AM_V_lt) $(AM_LIBTOOLFLAGS) \ -+ $(LIBTOOLFLAGS) --mode=compile $(YACC) $(AM_YFLAGS) $(YFLAGS) -+AM_V_YACC = $(am__v_YACC_@AM_V@) -+am__v_YACC_ = $(am__v_YACC_@AM_DEFAULT_V@) -+am__v_YACC_0 = @echo " YACC " $@; -+am__v_YACC_1 = - SOURCES = $(libldtestplug_la_SOURCES) $(ld_new_SOURCES) \ - $(EXTRA_ld_new_SOURCES) -+AM_V_DVIPS = $(am__v_DVIPS_@AM_V@) -+am__v_DVIPS_ = $(am__v_DVIPS_@AM_DEFAULT_V@) -+am__v_DVIPS_0 = @echo " DVIPS " $@; -+am__v_DVIPS_1 = -+AM_V_MAKEINFO = $(am__v_MAKEINFO_@AM_V@) -+am__v_MAKEINFO_ = $(am__v_MAKEINFO_@AM_DEFAULT_V@) -+am__v_MAKEINFO_0 = @echo " MAKEINFO" $@; -+am__v_MAKEINFO_1 = -+AM_V_INFOHTML = $(am__v_INFOHTML_@AM_V@) -+am__v_INFOHTML_ = $(am__v_INFOHTML_@AM_DEFAULT_V@) -+am__v_INFOHTML_0 = @echo " INFOHTML" $@; -+am__v_INFOHTML_1 = -+AM_V_TEXI2DVI = $(am__v_TEXI2DVI_@AM_V@) -+am__v_TEXI2DVI_ = $(am__v_TEXI2DVI_@AM_DEFAULT_V@) -+am__v_TEXI2DVI_0 = @echo " TEXI2DVI" $@; -+am__v_TEXI2DVI_1 = -+AM_V_TEXI2PDF = $(am__v_TEXI2PDF_@AM_V@) -+am__v_TEXI2PDF_ = $(am__v_TEXI2PDF_@AM_DEFAULT_V@) -+am__v_TEXI2PDF_0 = @echo " TEXI2PDF" $@; -+am__v_TEXI2PDF_1 = -+AM_V_texinfo = $(am__v_texinfo_@AM_V@) -+am__v_texinfo_ = $(am__v_texinfo_@AM_DEFAULT_V@) -+am__v_texinfo_0 = -q -+am__v_texinfo_1 = -+AM_V_texidevnull = $(am__v_texidevnull_@AM_V@) -+am__v_texidevnull_ = $(am__v_texidevnull_@AM_DEFAULT_V@) -+am__v_texidevnull_0 = > /dev/null -+am__v_texidevnull_1 = - INFO_DEPS = ld.info - am__TEXINFO_TEX_DIR = $(srcdir)/../texinfo - DVIS = ld.dvi -@@ -147,13 +255,19 @@ TEXI2PDF = $(TEXI2DVI) --pdf --batch - MAKEINFOHTML = $(MAKEINFO) --html - AM_MAKEINFOHTMLFLAGS = $(AM_MAKEINFOFLAGS) - DVIPS = dvips --RECURSIVE_TARGETS = all-recursive check-recursive dvi-recursive \ -- html-recursive info-recursive install-data-recursive \ -- install-dvi-recursive install-exec-recursive \ -- install-html-recursive install-info-recursive \ -- install-pdf-recursive install-ps-recursive install-recursive \ -- installcheck-recursive installdirs-recursive pdf-recursive \ -- ps-recursive uninstall-recursive -+RECURSIVE_TARGETS = all-recursive check-recursive cscopelist-recursive \ -+ ctags-recursive dvi-recursive html-recursive info-recursive \ -+ install-data-recursive install-dvi-recursive \ -+ install-exec-recursive install-html-recursive \ -+ install-info-recursive install-pdf-recursive \ -+ install-ps-recursive install-recursive installcheck-recursive \ -+ installdirs-recursive pdf-recursive ps-recursive \ -+ tags-recursive uninstall-recursive -+am__can_run_installinfo = \ -+ case $$AM_UPDATE_INFO_DIR in \ -+ n|no|NO) false;; \ -+ *) (install-info --version) >/dev/null 2>&1;; \ -+ esac - am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; - am__vpath_adj = case $$p in \ - $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \ -@@ -175,21 +289,51 @@ am__nobase_list = $(am__nobase_strip_setup); \ - am__base_list = \ - sed '$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;s/\n/ /g' | \ - sed '$$!N;$$!N;$$!N;$$!N;s/\n/ /g' -+am__uninstall_files_from_dir = { \ -+ test -z "$$files" \ -+ || { test ! -d "$$dir" && test ! -f "$$dir" && test ! -r "$$dir"; } \ -+ || { echo " ( cd '$$dir' && rm -f" $$files ")"; \ -+ $(am__cd) "$$dir" && rm -f $$files; }; \ -+ } - man1dir = $(mandir)/man1 - NROFF = nroff - MANS = $(man_MANS) - RECURSIVE_CLEAN_TARGETS = mostlyclean-recursive clean-recursive \ - distclean-recursive maintainer-clean-recursive --AM_RECURSIVE_TARGETS = $(RECURSIVE_TARGETS:-recursive=) \ -- $(RECURSIVE_CLEAN_TARGETS:-recursive=) tags TAGS ctags CTAGS -+am__recursive_targets = \ -+ $(RECURSIVE_TARGETS) \ -+ $(RECURSIVE_CLEAN_TARGETS) \ -+ $(am__extra_recursive_targets) -+AM_RECURSIVE_TARGETS = $(am__recursive_targets:-recursive=) TAGS CTAGS \ -+ cscope -+am__tagged_files = $(HEADERS) $(SOURCES) $(TAGS_FILES) \ -+ $(LISP)config.in -+# Read a list of newline-separated strings from the standard input, -+# and print each of them once, without duplicates. Input order is -+# *not* preserved. -+am__uniquify_input = $(AWK) '\ -+ BEGIN { nonempty = 0; } \ -+ { items[$$0] = 1; nonempty = 1; } \ -+ END { if (nonempty) { for (i in items) print i; }; } \ -+' -+# Make sure the list of sources is unique. This is necessary because, -+# e.g., the same source file might be shared among _SOURCES variables -+# for different programs/libraries. -+am__define_uniq_tagged_files = \ -+ list='$(am__tagged_files)'; \ -+ unique=`for i in $$list; do \ -+ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ -+ done | $(am__uniquify_input)` - ETAGS = etags - CTAGS = ctags -+CSCOPE = cscope - DEJATOOL = $(PACKAGE) - RUNTESTDEFAULTFLAGS = --tool $$tool --srcdir $$srcdir - DIST_SUBDIRS = $(SUBDIRS) - transform = s/^ld-new$$/$(installed_linker)/;@program_transform_name@ - ACLOCAL = @ACLOCAL@ - AMTAR = @AMTAR@ -+AM_DEFAULT_VERBOSITY = @AM_DEFAULT_VERBOSITY@ - AR = @AR@ - AUTOCONF = @AUTOCONF@ - AUTOHEADER = @AUTOHEADER@ -@@ -491,6 +635,7 @@ ALL_EMULATION_SOURCES = \ - eavr5.c \ - eavr51.c \ - eavr6.c \ -+ eavr7.c \ - eavrxmega1.c \ - eavrxmega2.c \ - eavrxmega3.c \ -@@ -498,6 +643,7 @@ ALL_EMULATION_SOURCES = \ +@@ -498,6 +498,7 @@ ALL_EMULATION_SOURCES = \ eavrxmega5.c \ eavrxmega6.c \ eavrxmega7.c \ @@ -33570,633 +33417,15 @@ index b95a3d1..cc7cbb3 100644 ecoff_i860.c \ ecoff_sparc.c \ ecrisaout.c \ -@@ -953,7 +1099,7 @@ all: $(BUILT_SOURCES) config.h - - .SUFFIXES: - .SUFFIXES: .c .dvi .l .lo .o .obj .ps .y --am--refresh: -+am--refresh: Makefile - @: - $(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(am__configure_deps) - @for dep in $?; do \ -@@ -989,10 +1135,8 @@ $(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps) - $(am__aclocal_m4_deps): - - config.h: stamp-h1 -- @if test ! -f $@; then \ -- rm -f stamp-h1; \ -- $(MAKE) $(AM_MAKEFLAGS) stamp-h1; \ -- else :; fi -+ @test -f $@ || rm -f stamp-h1 -+ @test -f $@ || $(MAKE) $(AM_MAKEFLAGS) stamp-h1 - - stamp-h1: $(srcdir)/config.in $(top_builddir)/config.status - @rm -f stamp-h1 -@@ -1009,24 +1153,32 @@ po/Makefile.in: $(top_builddir)/config.status $(top_srcdir)/po/Make-in - - clean-noinstLTLIBRARIES: - -test -z "$(noinst_LTLIBRARIES)" || rm -f $(noinst_LTLIBRARIES) -- @list='$(noinst_LTLIBRARIES)'; for p in $$list; do \ -- dir="`echo $$p | sed -e 's|/[^/]*$$||'`"; \ -- test "$$dir" != "$$p" || dir=.; \ -- echo "rm -f \"$${dir}/so_locations\""; \ -- rm -f "$${dir}/so_locations"; \ -- done --libldtestplug.la: $(libldtestplug_la_OBJECTS) $(libldtestplug_la_DEPENDENCIES) -- $(libldtestplug_la_LINK) $(am_libldtestplug_la_rpath) $(libldtestplug_la_OBJECTS) $(libldtestplug_la_LIBADD) $(LIBS) -+ @list='$(noinst_LTLIBRARIES)'; \ -+ locs=`for p in $$list; do echo $$p; done | \ -+ sed 's|^[^/]*$$|.|; s|/[^/]*$$||; s|$$|/so_locations|' | \ -+ sort -u`; \ -+ test -z "$$locs" || { \ -+ echo rm -f $${locs}; \ -+ rm -f $${locs}; \ -+ } -+ -+libldtestplug.la: $(libldtestplug_la_OBJECTS) $(libldtestplug_la_DEPENDENCIES) $(EXTRA_libldtestplug_la_DEPENDENCIES) -+ $(AM_V_CCLD)$(libldtestplug_la_LINK) $(am_libldtestplug_la_rpath) $(libldtestplug_la_OBJECTS) $(libldtestplug_la_LIBADD) $(LIBS) - install-binPROGRAMS: $(bin_PROGRAMS) - @$(NORMAL_INSTALL) -- test -z "$(bindir)" || $(MKDIR_P) "$(DESTDIR)$(bindir)" - @list='$(bin_PROGRAMS)'; test -n "$(bindir)" || list=; \ -+ if test -n "$$list"; then \ -+ echo " $(MKDIR_P) '$(DESTDIR)$(bindir)'"; \ -+ $(MKDIR_P) "$(DESTDIR)$(bindir)" || exit 1; \ -+ fi; \ - for p in $$list; do echo "$$p $$p"; done | \ - sed 's/$(EXEEXT)$$//' | \ -- while read p p1; do if test -f $$p || test -f $$p1; \ -- then echo "$$p"; echo "$$p"; else :; fi; \ -+ while read p p1; do if test -f $$p \ -+ || test -f $$p1 \ -+ ; then echo "$$p"; echo "$$p"; else :; fi; \ - done | \ -- sed -e 'p;s,.*/,,;n;h' -e 's|.*|.|' \ -+ sed -e 'p;s,.*/,,;n;h' \ -+ -e 's|.*|.|' \ - -e 'p;x;s,.*/,,;s/$(EXEEXT)$$//;$(transform);s/$$/$(EXEEXT)/' | \ - sed 'N;N;N;s,\n, ,g' | \ - $(AWK) 'BEGIN { files["."] = ""; dirs["."] = 1 } \ -@@ -1047,7 +1199,8 @@ uninstall-binPROGRAMS: - @list='$(bin_PROGRAMS)'; test -n "$(bindir)" || list=; \ - files=`for p in $$list; do echo "$$p"; done | \ - sed -e 'h;s,^.*/,,;s/$(EXEEXT)$$//;$(transform)' \ -- -e 's/$$/$(EXEEXT)/' `; \ -+ -e 's/$$/$(EXEEXT)/' \ -+ `; \ - test -n "$$list" || exit 0; \ - echo " ( cd '$(DESTDIR)$(bindir)' && rm -f" $$files ")"; \ - cd "$(DESTDIR)$(bindir)" && rm -f $$files -@@ -1061,18 +1214,15 @@ clean-binPROGRAMS: - echo " rm -f" $$list; \ - rm -f $$list - ldgram.h: ldgram.c -- @if test ! -f $@; then \ -- rm -f ldgram.c; \ -- $(MAKE) $(AM_MAKEFLAGS) ldgram.c; \ -- else :; fi -+ @if test ! -f $@; then rm -f ldgram.c; else :; fi -+ @if test ! -f $@; then $(MAKE) $(AM_MAKEFLAGS) ldgram.c; else :; fi - deffilep.h: deffilep.c -- @if test ! -f $@; then \ -- rm -f deffilep.c; \ -- $(MAKE) $(AM_MAKEFLAGS) deffilep.c; \ -- else :; fi --ld-new$(EXEEXT): $(ld_new_OBJECTS) $(ld_new_DEPENDENCIES) -+ @if test ! -f $@; then rm -f deffilep.c; else :; fi -+ @if test ! -f $@; then $(MAKE) $(AM_MAKEFLAGS) deffilep.c; else :; fi -+ -+ld-new$(EXEEXT): $(ld_new_OBJECTS) $(ld_new_DEPENDENCIES) $(EXTRA_ld_new_DEPENDENCIES) - @rm -f ld-new$(EXEEXT) -- $(LINK) $(ld_new_OBJECTS) $(ld_new_LDADD) $(LIBS) -+ $(AM_V_CCLD)$(LINK) $(ld_new_OBJECTS) $(ld_new_LDADD) $(LIBS) - - mostlyclean-compile: - -rm -f *.$(OBJEXT) -@@ -1127,6 +1277,8 @@ distclean-compile: +@@ -1127,6 +1128,7 @@ distclean-compile: @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eavr5.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eavr51.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eavr6.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eavr7.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eavrtiny.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eavrxmega1.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eavrxmega2.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eavrxmega3.Po@am__quote@ -@@ -1485,38 +1637,38 @@ distclean-compile: - @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/plugin.Po@am__quote@ - - .c.o: --@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $< --@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po --@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@ -+@am__fastdepCC_TRUE@ $(AM_V_CC)$(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $< -+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po -+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='$<' object='$@' libtool=no @AMDEPBACKSLASH@ - @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ --@am__fastdepCC_FALSE@ $(COMPILE) -c $< -+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(COMPILE) -c -o $@ $< - - .c.obj: --@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'` --@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po --@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@ -+@am__fastdepCC_TRUE@ $(AM_V_CC)$(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'` -+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po -+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='$<' object='$@' libtool=no @AMDEPBACKSLASH@ - @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ --@am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'` -+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(COMPILE) -c -o $@ `$(CYGPATH_W) '$<'` - - .c.lo: --@am__fastdepCC_TRUE@ $(LTCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $< --@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Plo --@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=yes @AMDEPBACKSLASH@ -+@am__fastdepCC_TRUE@ $(AM_V_CC)$(LTCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $< -+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Plo -+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='$<' object='$@' libtool=yes @AMDEPBACKSLASH@ - @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ --@am__fastdepCC_FALSE@ $(LTCOMPILE) -c -o $@ $< -+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(LTCOMPILE) -c -o $@ $< - - libldtestplug_la-testplug.lo: testplug.c --@am__fastdepCC_TRUE@ $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libldtestplug_la_CFLAGS) $(CFLAGS) -MT libldtestplug_la-testplug.lo -MD -MP -MF $(DEPDIR)/libldtestplug_la-testplug.Tpo -c -o libldtestplug_la-testplug.lo `test -f 'testplug.c' || echo '$(srcdir)/'`testplug.c --@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libldtestplug_la-testplug.Tpo $(DEPDIR)/libldtestplug_la-testplug.Plo --@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='testplug.c' object='libldtestplug_la-testplug.lo' libtool=yes @AMDEPBACKSLASH@ -+@am__fastdepCC_TRUE@ $(AM_V_CC)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libldtestplug_la_CFLAGS) $(CFLAGS) -MT libldtestplug_la-testplug.lo -MD -MP -MF $(DEPDIR)/libldtestplug_la-testplug.Tpo -c -o libldtestplug_la-testplug.lo `test -f 'testplug.c' || echo '$(srcdir)/'`testplug.c -+@am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) $(DEPDIR)/libldtestplug_la-testplug.Tpo $(DEPDIR)/libldtestplug_la-testplug.Plo -+@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(AM_V_CC)source='testplug.c' object='libldtestplug_la-testplug.lo' libtool=yes @AMDEPBACKSLASH@ - @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ --@am__fastdepCC_FALSE@ $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libldtestplug_la_CFLAGS) $(CFLAGS) -c -o libldtestplug_la-testplug.lo `test -f 'testplug.c' || echo '$(srcdir)/'`testplug.c -+@am__fastdepCC_FALSE@ $(AM_V_CC@am__nodep@)$(LIBTOOL) $(AM_V_lt) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libldtestplug_la_CFLAGS) $(CFLAGS) -c -o libldtestplug_la-testplug.lo `test -f 'testplug.c' || echo '$(srcdir)/'`testplug.c - - .l.c: -- $(am__skiplex) $(SHELL) $(YLWRAP) $< $(LEX_OUTPUT_ROOT).c $@ -- $(LEXCOMPILE) -+ $(AM_V_LEX)$(am__skiplex) $(SHELL) $(YLWRAP) $< $(LEX_OUTPUT_ROOT).c $@ -- $(LEXCOMPILE) - - .y.c: -- $(am__skipyacc) $(SHELL) $(YLWRAP) $< y.tab.c $@ y.tab.h $*.h y.output $*.output -- $(YACCCOMPILE) -+ $(AM_V_YACC)$(am__skipyacc) $(SHELL) $(YLWRAP) $< y.tab.c $@ y.tab.h `echo $@ | $(am__yacc_c2h)` y.output $*.output -- $(YACCCOMPILE) - - mostlyclean-libtool: - -rm -f *.lo -@@ -1528,7 +1680,7 @@ distclean-libtool: - -rm -f libtool config.lt - - ld.info: ld.texinfo $(ld_TEXINFOS) -- restore=: && backupdir="$(am__leading_dot)am$$$$" && \ -+ $(AM_V_MAKEINFO)restore=: && backupdir="$(am__leading_dot)am$$$$" && \ - rm -rf $$backupdir && mkdir $$backupdir && \ - if ($(MAKEINFO) --version) >/dev/null 2>&1; then \ - for f in $@ $@-[0-9] $@-[0-9][0-9] $(@:.info=).i[0-9] $(@:.info=).i[0-9][0-9]; do \ -@@ -1546,31 +1698,29 @@ ld.info: ld.texinfo $(ld_TEXINFOS) - rm -rf $$backupdir; exit $$rc - - ld.dvi: ld.texinfo $(ld_TEXINFOS) -- TEXINPUTS="$(am__TEXINFO_TEX_DIR)$(PATH_SEPARATOR)$$TEXINPUTS" \ -+ $(AM_V_TEXI2DVI)TEXINPUTS="$(am__TEXINFO_TEX_DIR)$(PATH_SEPARATOR)$$TEXINPUTS" \ - MAKEINFO='$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir)' \ -- $(TEXI2DVI) -o $@ `test -f 'ld.texinfo' || echo '$(srcdir)/'`ld.texinfo -+ $(TEXI2DVI) $(AM_V_texinfo) --build-dir=$(@:.dvi=.t2d) -o $@ $(AM_V_texidevnull) \ -+ `test -f 'ld.texinfo' || echo '$(srcdir)/'`ld.texinfo - - ld.pdf: ld.texinfo $(ld_TEXINFOS) -- TEXINPUTS="$(am__TEXINFO_TEX_DIR)$(PATH_SEPARATOR)$$TEXINPUTS" \ -+ $(AM_V_TEXI2PDF)TEXINPUTS="$(am__TEXINFO_TEX_DIR)$(PATH_SEPARATOR)$$TEXINPUTS" \ - MAKEINFO='$(MAKEINFO) $(AM_MAKEINFOFLAGS) $(MAKEINFOFLAGS) -I $(srcdir)' \ -- $(TEXI2PDF) -o $@ `test -f 'ld.texinfo' || echo '$(srcdir)/'`ld.texinfo -+ $(TEXI2PDF) $(AM_V_texinfo) --build-dir=$(@:.pdf=.t2p) -o $@ $(AM_V_texidevnull) \ -+ `test -f 'ld.texinfo' || echo '$(srcdir)/'`ld.texinfo - - ld.html: ld.texinfo $(ld_TEXINFOS) -- rm -rf $(@:.html=.htp) -- if $(MAKEINFOHTML) $(AM_MAKEINFOHTMLFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) \ -+ $(AM_V_MAKEINFO)rm -rf $(@:.html=.htp) -+ $(AM_V_at)if $(MAKEINFOHTML) $(AM_MAKEINFOHTMLFLAGS) $(MAKEINFOFLAGS) -I $(srcdir) \ - -o $(@:.html=.htp) `test -f 'ld.texinfo' || echo '$(srcdir)/'`ld.texinfo; \ - then \ -- rm -rf $@; \ -- if test ! -d $(@:.html=.htp) && test -d $(@:.html=); then \ -- mv $(@:.html=) $@; else mv $(@:.html=.htp) $@; fi; \ -+ rm -rf $@ && mv $(@:.html=.htp) $@; \ - else \ -- if test ! -d $(@:.html=.htp) && test -d $(@:.html=); then \ -- rm -rf $(@:.html=); else rm -Rf $(@:.html=.htp) $@; fi; \ -- exit 1; \ -+ rm -rf $(@:.html=.htp); exit 1; \ - fi - .dvi.ps: -- TEXINPUTS="$(am__TEXINFO_TEX_DIR)$(PATH_SEPARATOR)$$TEXINPUTS" \ -- $(DVIPS) -o $@ $< -+ $(AM_V_DVIPS)TEXINPUTS="$(am__TEXINFO_TEX_DIR)$(PATH_SEPARATOR)$$TEXINPUTS" \ -+ $(DVIPS) $(AM_V_texinfo) -o $@ $< - - uninstall-dvi-am: - @$(NORMAL_UNINSTALL) -@@ -1592,9 +1742,7 @@ uninstall-html-am: - - uninstall-info-am: - @$(PRE_UNINSTALL) -- @if test -d '$(DESTDIR)$(infodir)' && \ -- (install-info --version && \ -- install-info --version 2>&1 | sed 1q | grep -i -v debian) >/dev/null 2>&1; then \ -+ @if test -d '$(DESTDIR)$(infodir)' && $(am__can_run_installinfo); then \ - list='$(INFO_DEPS)'; \ - for file in $$list; do \ - relfile=`echo "$$file" | sed 's|^.*/||'`; \ -@@ -1651,8 +1799,7 @@ dist-info: $(INFO_DEPS) - done - - mostlyclean-aminfo: -- -rm -rf ld.aux ld.cp ld.cps ld.fn ld.fns ld.ky ld.log ld.pg ld.pgs ld.tmp \ -- ld.toc ld.tp ld.tps ld.vr ld.vrs -+ -rm -rf ld.t2d ld.t2p - - clean-aminfo: - -test -z "ld.dvi ld.pdf ld.ps ld.html" \ -@@ -1666,11 +1813,18 @@ maintainer-clean-aminfo: - done - install-man1: $(man_MANS) - @$(NORMAL_INSTALL) -- test -z "$(man1dir)" || $(MKDIR_P) "$(DESTDIR)$(man1dir)" -- @list=''; test -n "$(man1dir)" || exit 0; \ -- { for i in $$list; do echo "$$i"; done; \ -- l2='$(man_MANS)'; for i in $$l2; do echo "$$i"; done | \ -- sed -n '/\.1[a-z]*$$/p'; \ -+ @list1=''; \ -+ list2='$(man_MANS)'; \ -+ test -n "$(man1dir)" \ -+ && test -n "`echo $$list1$$list2`" \ -+ || exit 0; \ -+ echo " $(MKDIR_P) '$(DESTDIR)$(man1dir)'"; \ -+ $(MKDIR_P) "$(DESTDIR)$(man1dir)" || exit 1; \ -+ { for i in $$list1; do echo "$$i"; done; \ -+ if test -n "$$list2"; then \ -+ for i in $$list2; do echo "$$i"; done \ -+ | sed -n '/\.1[a-z]*$$/p'; \ -+ fi; \ - } | while read p; do \ - if test -f $$p; then d=; else d="$(srcdir)/"; fi; \ - echo "$$d$$p"; echo "$$p"; \ -@@ -1699,27 +1853,28 @@ uninstall-man1: - sed -n '/\.1[a-z]*$$/p'; \ - } | sed -e 's,.*/,,;h;s,.*\.,,;s,^[^1][0-9a-z]*$$,1,;x' \ - -e 's,\.[0-9a-z]*$$,,;$(transform);G;s,\n,.,'`; \ -- test -z "$$files" || { \ -- echo " ( cd '$(DESTDIR)$(man1dir)' && rm -f" $$files ")"; \ -- cd "$(DESTDIR)$(man1dir)" && rm -f $$files; } -+ dir='$(DESTDIR)$(man1dir)'; $(am__uninstall_files_from_dir) - - # This directory's subdirectories are mostly independent; you can cd --# into them and run `make' without going through this Makefile. --# To change the values of `make' variables: instead of editing Makefiles, --# (1) if the variable is set in `config.status', edit `config.status' --# (which will cause the Makefiles to be regenerated when you run `make'); --# (2) otherwise, pass the desired values on the `make' command line. --$(RECURSIVE_TARGETS): -- @fail= failcom='exit 1'; \ -- for f in x $$MAKEFLAGS; do \ -- case $$f in \ -- *=* | --[!k]*);; \ -- *k*) failcom='fail=yes';; \ -- esac; \ -- done; \ -+# into them and run 'make' without going through this Makefile. -+# To change the values of 'make' variables: instead of editing Makefiles, -+# (1) if the variable is set in 'config.status', edit 'config.status' -+# (which will cause the Makefiles to be regenerated when you run 'make'); -+# (2) otherwise, pass the desired values on the 'make' command line. -+$(am__recursive_targets): -+ @fail=; \ -+ if $(am__make_keepgoing); then \ -+ failcom='fail=yes'; \ -+ else \ -+ failcom='exit 1'; \ -+ fi; \ - dot_seen=no; \ - target=`echo $@ | sed s/-recursive//`; \ -- list='$(SUBDIRS)'; for subdir in $$list; do \ -+ case "$@" in \ -+ distclean-* | maintainer-clean-*) list='$(DIST_SUBDIRS)' ;; \ -+ *) list='$(SUBDIRS)' ;; \ -+ esac; \ -+ for subdir in $$list; do \ - echo "Making $$target in $$subdir"; \ - if test "$$subdir" = "."; then \ - dot_seen=yes; \ -@@ -1734,57 +1889,12 @@ $(RECURSIVE_TARGETS): - $(MAKE) $(AM_MAKEFLAGS) "$$target-am" || exit 1; \ - fi; test -z "$$fail" - --$(RECURSIVE_CLEAN_TARGETS): -- @fail= failcom='exit 1'; \ -- for f in x $$MAKEFLAGS; do \ -- case $$f in \ -- *=* | --[!k]*);; \ -- *k*) failcom='fail=yes';; \ -- esac; \ -- done; \ -- dot_seen=no; \ -- case "$@" in \ -- distclean-* | maintainer-clean-*) list='$(DIST_SUBDIRS)' ;; \ -- *) list='$(SUBDIRS)' ;; \ -- esac; \ -- rev=''; for subdir in $$list; do \ -- if test "$$subdir" = "."; then :; else \ -- rev="$$subdir $$rev"; \ -- fi; \ -- done; \ -- rev="$$rev ."; \ -- target=`echo $@ | sed s/-recursive//`; \ -- for subdir in $$rev; do \ -- echo "Making $$target in $$subdir"; \ -- if test "$$subdir" = "."; then \ -- local_target="$$target-am"; \ -- else \ -- local_target="$$target"; \ -- fi; \ -- ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \ -- || eval $$failcom; \ -- done && test -z "$$fail" --tags-recursive: -- list='$(SUBDIRS)'; for subdir in $$list; do \ -- test "$$subdir" = . || ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) tags); \ -- done --ctags-recursive: -- list='$(SUBDIRS)'; for subdir in $$list; do \ -- test "$$subdir" = . || ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) ctags); \ -- done -+ID: $(am__tagged_files) -+ $(am__define_uniq_tagged_files); mkid -fID $$unique -+tags: tags-recursive -+TAGS: tags - --ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES) -- list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \ -- unique=`for i in $$list; do \ -- if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ -- done | \ -- $(AWK) '{ files[$$0] = 1; nonempty = 1; } \ -- END { if (nonempty) { for (i in files) print i; }; }'`; \ -- mkid -fID $$unique --tags: TAGS -- --TAGS: tags-recursive $(HEADERS) $(SOURCES) config.in $(TAGS_DEPENDENCIES) \ -- $(TAGS_FILES) $(LISP) -+tags-am: $(TAGS_DEPENDENCIES) $(am__tagged_files) - set x; \ - here=`pwd`; \ - if ($(ETAGS) --etags-include --version) >/dev/null 2>&1; then \ -@@ -1800,12 +1910,7 @@ TAGS: tags-recursive $(HEADERS) $(SOURCES) config.in $(TAGS_DEPENDENCIES) \ - set "$$@" "$$include_option=$$here/$$subdir/TAGS"; \ - fi; \ - done; \ -- list='$(SOURCES) $(HEADERS) config.in $(LISP) $(TAGS_FILES)'; \ -- unique=`for i in $$list; do \ -- if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ -- done | \ -- $(AWK) '{ files[$$0] = 1; nonempty = 1; } \ -- END { if (nonempty) { for (i in files) print i; }; }'`; \ -+ $(am__define_uniq_tagged_files); \ - shift; \ - if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \ - test -n "$$unique" || unique=$$empty_fix; \ -@@ -1817,15 +1922,11 @@ TAGS: tags-recursive $(HEADERS) $(SOURCES) config.in $(TAGS_DEPENDENCIES) \ - $$unique; \ - fi; \ - fi --ctags: CTAGS --CTAGS: ctags-recursive $(HEADERS) $(SOURCES) config.in $(TAGS_DEPENDENCIES) \ -- $(TAGS_FILES) $(LISP) -- list='$(SOURCES) $(HEADERS) config.in $(LISP) $(TAGS_FILES)'; \ -- unique=`for i in $$list; do \ -- if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ -- done | \ -- $(AWK) '{ files[$$0] = 1; nonempty = 1; } \ -- END { if (nonempty) { for (i in files) print i; }; }'`; \ -+ctags: ctags-recursive -+ -+CTAGS: ctags -+ctags-am: $(TAGS_DEPENDENCIES) $(am__tagged_files) -+ $(am__define_uniq_tagged_files); \ - test -z "$(CTAGS_ARGS)$$unique" \ - || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \ - $$unique -@@ -1834,15 +1935,37 @@ GTAGS: - here=`$(am__cd) $(top_builddir) && pwd` \ - && $(am__cd) $(top_srcdir) \ - && gtags -i $(GTAGS_ARGS) "$$here" -+cscope: cscope.files -+ test ! -s cscope.files \ -+ || $(CSCOPE) -b -q $(AM_CSCOPEFLAGS) $(CSCOPEFLAGS) -i cscope.files $(CSCOPE_ARGS) -+clean-cscope: -+ -rm -f cscope.files -+cscope.files: clean-cscope cscopelist -+cscopelist: cscopelist-recursive -+ -+cscopelist-am: $(am__tagged_files) -+ list='$(am__tagged_files)'; \ -+ case "$(srcdir)" in \ -+ [\\/]* | ?:[\\/]*) sdir="$(srcdir)" ;; \ -+ *) sdir=$(subdir)/$(srcdir) ;; \ -+ esac; \ -+ for i in $$list; do \ -+ if test -f "$$i"; then \ -+ echo "$(subdir)/$$i"; \ -+ else \ -+ echo "$$sdir/$$i"; \ -+ fi; \ -+ done >> $(top_builddir)/cscope.files - - distclean-tags: - -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags --site.exp: Makefile -- @echo 'Making a new site.exp file...' -+ -rm -f cscope.out cscope.in.out cscope.po.out cscope.files -+site.exp: Makefile $(EXTRA_DEJAGNU_SITE_CONFIG) -+ @echo 'Making a new site.exp file ...' - @echo '## these variables are automatically generated by make ##' >site.tmp - @echo '# Do not edit here. If you wish to override these values' >>site.tmp - @echo '# edit the last section' >>site.tmp -- @echo 'set srcdir $(srcdir)' >>site.tmp -+ @echo 'set srcdir "$(srcdir)"' >>site.tmp - @echo "set objdir `pwd`" >>site.tmp - @echo 'set build_alias "$(build_alias)"' >>site.tmp - @echo 'set build_triplet $(build_triplet)' >>site.tmp -@@ -1850,9 +1973,16 @@ site.exp: Makefile - @echo 'set host_triplet $(host_triplet)' >>site.tmp - @echo 'set target_alias "$(target_alias)"' >>site.tmp - @echo 'set target_triplet $(target_triplet)' >>site.tmp -- @echo '## All variables above are generated by configure. Do Not Edit ##' >>site.tmp -- @test ! -f site.exp || \ -- sed '1,/^## All variables above are.*##/ d' site.exp >> site.tmp -+ @list='$(EXTRA_DEJAGNU_SITE_CONFIG)'; for f in $$list; do \ -+ echo "## Begin content included from file $$f. Do not modify. ##" \ -+ && cat `test -f "$$f" || echo '$(srcdir)/'`$$f \ -+ && echo "## End content included from file $$f. ##" \ -+ || exit 1; \ -+ done >> site.tmp -+ @echo "## End of auto-generated content; you can edit from here. ##" >> site.tmp -+ @if test -f site.exp; then \ -+ sed -e '1,/^## End of auto-generated content.*##/d' site.exp >> site.tmp; \ -+ fi - @-rm -f site.bak - @test ! -f site.exp || mv site.exp site.bak - @mv site.tmp site.exp -@@ -1884,10 +2014,15 @@ install-am: all-am - - installcheck: installcheck-recursive - install-strip: -- $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \ -- install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \ -- `test -z '$(STRIP)' || \ -- echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install -+ if test -z '$(STRIP)'; then \ -+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \ -+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \ -+ install; \ -+ else \ -+ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \ -+ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \ -+ "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'" install; \ -+ fi - mostlyclean-generic: - -test -z "$(MOSTLYCLEANFILES)" || rm -f $(MOSTLYCLEANFILES) - -@@ -1940,8 +2075,11 @@ install-dvi: install-dvi-recursive - - install-dvi-am: $(DVIS) - @$(NORMAL_INSTALL) -- test -z "$(dvidir)" || $(MKDIR_P) "$(DESTDIR)$(dvidir)" - @list='$(DVIS)'; test -n "$(dvidir)" || list=; \ -+ if test -n "$$list"; then \ -+ echo " $(MKDIR_P) '$(DESTDIR)$(dvidir)'"; \ -+ $(MKDIR_P) "$(DESTDIR)$(dvidir)" || exit 1; \ -+ fi; \ - for p in $$list; do \ - if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \ - echo "$$d$$p"; \ -@@ -1956,18 +2094,22 @@ install-html: install-html-recursive - - install-html-am: $(HTMLS) - @$(NORMAL_INSTALL) -- test -z "$(htmldir)" || $(MKDIR_P) "$(DESTDIR)$(htmldir)" - @list='$(HTMLS)'; list2=; test -n "$(htmldir)" || list=; \ -+ if test -n "$$list"; then \ -+ echo " $(MKDIR_P) '$(DESTDIR)$(htmldir)'"; \ -+ $(MKDIR_P) "$(DESTDIR)$(htmldir)" || exit 1; \ -+ fi; \ - for p in $$list; do \ - if test -f "$$p" || test -d "$$p"; then d=; else d="$(srcdir)/"; fi; \ - $(am__strip_dir) \ -- if test -d "$$d$$p"; then \ -+ d2=$$d$$p; \ -+ if test -d "$$d2"; then \ - echo " $(MKDIR_P) '$(DESTDIR)$(htmldir)/$$f'"; \ - $(MKDIR_P) "$(DESTDIR)$(htmldir)/$$f" || exit 1; \ -- echo " $(INSTALL_DATA) '$$d$$p'/* '$(DESTDIR)$(htmldir)/$$f'"; \ -- $(INSTALL_DATA) "$$d$$p"/* "$(DESTDIR)$(htmldir)/$$f" || exit $$?; \ -+ echo " $(INSTALL_DATA) '$$d2'/* '$(DESTDIR)$(htmldir)/$$f'"; \ -+ $(INSTALL_DATA) "$$d2"/* "$(DESTDIR)$(htmldir)/$$f" || exit $$?; \ - else \ -- list2="$$list2 $$d$$p"; \ -+ list2="$$list2 $$d2"; \ - fi; \ - done; \ - test -z "$$list2" || { echo "$$list2" | $(am__base_list) | \ -@@ -1979,9 +2121,12 @@ install-info: install-info-recursive - - install-info-am: $(INFO_DEPS) - @$(NORMAL_INSTALL) -- test -z "$(infodir)" || $(MKDIR_P) "$(DESTDIR)$(infodir)" - @srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; \ - list='$(INFO_DEPS)'; test -n "$(infodir)" || list=; \ -+ if test -n "$$list"; then \ -+ echo " $(MKDIR_P) '$(DESTDIR)$(infodir)'"; \ -+ $(MKDIR_P) "$(DESTDIR)$(infodir)" || exit 1; \ -+ fi; \ - for file in $$list; do \ - case $$file in \ - $(srcdir)/*) file=`echo "$$file" | sed "s|^$$srcdirstrip/||"`;; \ -@@ -1999,8 +2144,7 @@ install-info-am: $(INFO_DEPS) - echo " $(INSTALL_DATA) $$files '$(DESTDIR)$(infodir)'"; \ - $(INSTALL_DATA) $$files "$(DESTDIR)$(infodir)" || exit $$?; done - @$(POST_INSTALL) -- @if (install-info --version && \ -- install-info --version 2>&1 | sed 1q | grep -i -v debian) >/dev/null 2>&1; then \ -+ @if $(am__can_run_installinfo); then \ - list='$(INFO_DEPS)'; test -n "$(infodir)" || list=; \ - for file in $$list; do \ - relfile=`echo "$$file" | sed 's|^.*/||'`; \ -@@ -2014,8 +2158,11 @@ install-pdf: install-pdf-recursive - - install-pdf-am: $(PDFS) - @$(NORMAL_INSTALL) -- test -z "$(pdfdir)" || $(MKDIR_P) "$(DESTDIR)$(pdfdir)" - @list='$(PDFS)'; test -n "$(pdfdir)" || list=; \ -+ if test -n "$$list"; then \ -+ echo " $(MKDIR_P) '$(DESTDIR)$(pdfdir)'"; \ -+ $(MKDIR_P) "$(DESTDIR)$(pdfdir)" || exit 1; \ -+ fi; \ - for p in $$list; do \ - if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \ - echo "$$d$$p"; \ -@@ -2027,8 +2174,11 @@ install-ps: install-ps-recursive - - install-ps-am: $(PSS) - @$(NORMAL_INSTALL) -- test -z "$(psdir)" || $(MKDIR_P) "$(DESTDIR)$(psdir)" - @list='$(PSS)'; test -n "$(psdir)" || list=; \ -+ if test -n "$$list"; then \ -+ echo " $(MKDIR_P) '$(DESTDIR)$(psdir)'"; \ -+ $(MKDIR_P) "$(DESTDIR)$(psdir)" || exit 1; \ -+ fi; \ - for p in $$list; do \ - if test -f "$$p"; then d=; else d="$(srcdir)/"; fi; \ - echo "$$d$$p"; \ -@@ -2065,15 +2215,14 @@ uninstall-am: uninstall-binPROGRAMS uninstall-dvi-am uninstall-html-am \ - - uninstall-man: uninstall-man1 - --.MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) all check \ -- check-am ctags-recursive install install-am install-strip \ -- tags-recursive -+.MAKE: $(am__recursive_targets) all check check-am install install-am \ -+ install-strip - --.PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \ -- all all-am am--refresh check check-DEJAGNU check-am clean \ -- clean-aminfo clean-binPROGRAMS clean-generic clean-libtool \ -- clean-noinstLTLIBRARIES ctags ctags-recursive dist-info \ -- distclean distclean-DEJAGNU distclean-compile \ -+.PHONY: $(am__recursive_targets) CTAGS GTAGS TAGS all all-am \ -+ am--refresh check check-DEJAGNU check-am clean clean-aminfo \ -+ clean-binPROGRAMS clean-cscope clean-generic clean-libtool \ -+ clean-noinstLTLIBRARIES cscope cscopelist-am ctags ctags-am \ -+ dist-info distclean distclean-DEJAGNU distclean-compile \ - distclean-generic distclean-hdr distclean-libtool \ - distclean-local distclean-tags dvi dvi-am html html-am info \ - info-am install install-am install-binPROGRAMS install-data \ -@@ -2086,7 +2235,7 @@ uninstall-man: uninstall-man1 - maintainer-clean-aminfo maintainer-clean-generic mostlyclean \ - mostlyclean-aminfo mostlyclean-compile mostlyclean-generic \ - mostlyclean-libtool mostlyclean-local pdf pdf-am ps ps-am tags \ -- tags-recursive uninstall uninstall-am uninstall-binPROGRAMS \ -+ tags-am uninstall uninstall-am uninstall-binPROGRAMS \ - uninstall-dvi-am uninstall-html-am uninstall-info-am \ - uninstall-man uninstall-man1 uninstall-pdf-am uninstall-ps-am - -@@ -2329,6 +2478,10 @@ eavr6.c: $(srcdir)/emulparams/avr6.sh $(srcdir)/emultempl/avrelf.em \ - $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ - ${GEN_DEPENDS} - ${GENSCRIPTS} avr6 "$(tdir_avr2)" -+eavr7.c: $(srcdir)/emulparams/avr7.sh $(srcdir)/emultempl/avrelf.em \ -+ $(ELF_DEPS) $(srcdir)/scripttempl/avr7.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} avr7 "$(tdir_avr2)" - eavrxmega1.c: $(srcdir)/emulparams/avrxmega1.sh \ - $(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ - ${GEN_DEPENDS} -@@ -2357,6 +2510,10 @@ eavrxmega7.c: $(srcdir)/emulparams/avrxmega7.sh \ +@@ -2357,6 +2359,10 @@ eavrxmega7.c: $(srcdir)/emulparams/avrxmega7.sh \ $(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ ${GEN_DEPENDS} ${GENSCRIPTS} avrxmega7 "$(tdir_avr2)" @@ -34207,5749 +33436,8 @@ index b95a3d1..cc7cbb3 100644 ecoff_i860.c: $(srcdir)/emulparams/coff_i860.sh \ $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/i860coff.sc ${GEN_DEPENDS} ${GENSCRIPTS} coff_i860 "$(tdir_coff_i860)" -diff --git a/ld/aclocal.m4 b/ld/aclocal.m4 -index 6585160..5a9c990 100644 ---- a/ld/aclocal.m4 -+++ b/ld/aclocal.m4 -@@ -1,7 +1,7 @@ --# generated automatically by aclocal 1.11.1 -*- Autoconf -*- -+# generated automatically by aclocal 1.14.1 -*- Autoconf -*- -+ -+# Copyright (C) 1996-2013 Free Software Foundation, Inc. - --# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, --# 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. - # This file is free software; the Free Software Foundation - # gives unlimited permission to copy and/or distribute it, - # with or without modifications, as long as this notice is preserved. -@@ -11,15 +11,16 @@ - # even the implied warranty of MERCHANTABILITY or FITNESS FOR A - # PARTICULAR PURPOSE. - -+m4_ifndef([AC_CONFIG_MACRO_DIRS], [m4_defun([_AM_CONFIG_MACRO_DIRS], [])m4_defun([AC_CONFIG_MACRO_DIRS], [_AM_CONFIG_MACRO_DIRS($@)])]) - m4_ifndef([AC_AUTOCONF_VERSION], - [m4_copy([m4_PACKAGE_VERSION], [AC_AUTOCONF_VERSION])])dnl --m4_if(m4_defn([AC_AUTOCONF_VERSION]), [2.64],, --[m4_warning([this file was generated for autoconf 2.64. -+m4_if(m4_defn([AC_AUTOCONF_VERSION]), [2.69],, -+[m4_warning([this file was generated for autoconf 2.69. - You have another version of autoconf. It may work, but is not guaranteed to. - If you have problems, you may need to regenerate the build system entirely. --To do so, use the procedure documented by the package, typically `autoreconf'.])]) -+To do so, use the procedure documented by the package, typically 'autoreconf'.])]) - --# Copyright (C) 2002, 2003, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. -+# Copyright (C) 2002-2013 Free Software Foundation, Inc. - # - # This file is free software; the Free Software Foundation - # gives unlimited permission to copy and/or distribute it, -@@ -31,10 +32,10 @@ To do so, use the procedure documented by the package, typically `autoreconf'.]) - # generated from the m4 files accompanying Automake X.Y. - # (This private macro should not be called outside this file.) - AC_DEFUN([AM_AUTOMAKE_VERSION], --[am__api_version='1.11' -+[am__api_version='1.14' - dnl Some users find AM_AUTOMAKE_VERSION and mistake it for a way to - dnl require some minimum version. Point them to the right macro. --m4_if([$1], [1.11.1], [], -+m4_if([$1], [1.14.1], [], - [AC_FATAL([Do not call $0, use AM_INIT_AUTOMAKE([$1]).])])dnl - ]) - -@@ -50,22 +51,22 @@ m4_define([_AM_AUTOCONF_VERSION], []) - # Call AM_AUTOMAKE_VERSION and AM_AUTOMAKE_VERSION so they can be traced. - # This function is AC_REQUIREd by AM_INIT_AUTOMAKE. - AC_DEFUN([AM_SET_CURRENT_AUTOMAKE_VERSION], --[AM_AUTOMAKE_VERSION([1.11.1])dnl -+[AM_AUTOMAKE_VERSION([1.14.1])dnl - m4_ifndef([AC_AUTOCONF_VERSION], - [m4_copy([m4_PACKAGE_VERSION], [AC_AUTOCONF_VERSION])])dnl - _AM_AUTOCONF_VERSION(m4_defn([AC_AUTOCONF_VERSION]))]) - - # AM_AUX_DIR_EXPAND -*- Autoconf -*- - --# Copyright (C) 2001, 2003, 2005 Free Software Foundation, Inc. -+# Copyright (C) 2001-2013 Free Software Foundation, Inc. - # - # This file is free software; the Free Software Foundation - # gives unlimited permission to copy and/or distribute it, - # with or without modifications, as long as this notice is preserved. - - # For projects using AC_CONFIG_AUX_DIR([foo]), Autoconf sets --# $ac_aux_dir to `$srcdir/foo'. In other projects, it is set to --# `$srcdir', `$srcdir/..', or `$srcdir/../..'. -+# $ac_aux_dir to '$srcdir/foo'. In other projects, it is set to -+# '$srcdir', '$srcdir/..', or '$srcdir/../..'. - # - # Of course, Automake must honor this variable whenever it calls a - # tool from the auxiliary directory. The problem is that $srcdir (and -@@ -84,7 +85,7 @@ _AM_AUTOCONF_VERSION(m4_defn([AC_AUTOCONF_VERSION]))]) - # - # The reason of the latter failure is that $top_srcdir and $ac_aux_dir - # are both prefixed by $srcdir. In an in-source build this is usually --# harmless because $srcdir is `.', but things will broke when you -+# harmless because $srcdir is '.', but things will broke when you - # start a VPATH build or use an absolute $srcdir. - # - # So we could use something similar to $top_srcdir/$ac_aux_dir/missing, -@@ -110,22 +111,19 @@ am_aux_dir=`cd $ac_aux_dir && pwd` - - # AM_CONDITIONAL -*- Autoconf -*- - --# Copyright (C) 1997, 2000, 2001, 2003, 2004, 2005, 2006, 2008 --# Free Software Foundation, Inc. -+# Copyright (C) 1997-2013 Free Software Foundation, Inc. - # - # This file is free software; the Free Software Foundation - # gives unlimited permission to copy and/or distribute it, - # with or without modifications, as long as this notice is preserved. - --# serial 9 -- - # AM_CONDITIONAL(NAME, SHELL-CONDITION) - # ------------------------------------- - # Define a conditional. - AC_DEFUN([AM_CONDITIONAL], --[AC_PREREQ(2.52)dnl -- ifelse([$1], [TRUE], [AC_FATAL([$0: invalid condition: $1])], -- [$1], [FALSE], [AC_FATAL([$0: invalid condition: $1])])dnl -+[AC_PREREQ([2.52])dnl -+ m4_if([$1], [TRUE], [AC_FATAL([$0: invalid condition: $1])], -+ [$1], [FALSE], [AC_FATAL([$0: invalid condition: $1])])dnl - AC_SUBST([$1_TRUE])dnl - AC_SUBST([$1_FALSE])dnl - _AM_SUBST_NOTMAKE([$1_TRUE])dnl -@@ -144,16 +142,14 @@ AC_CONFIG_COMMANDS_PRE( - Usually this means the macro was only invoked conditionally.]]) - fi])]) - --# Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2009 --# Free Software Foundation, Inc. -+# Copyright (C) 1999-2013 Free Software Foundation, Inc. - # - # This file is free software; the Free Software Foundation - # gives unlimited permission to copy and/or distribute it, - # with or without modifications, as long as this notice is preserved. - --# serial 10 - --# There are a few dirty hacks below to avoid letting `AC_PROG_CC' be -+# There are a few dirty hacks below to avoid letting 'AC_PROG_CC' be - # written in clear, in which case automake, when reading aclocal.m4, - # will think it sees a *use*, and therefore will trigger all it's - # C support machinery. Also note that it means that autoscan, seeing -@@ -163,7 +159,7 @@ fi])]) - # _AM_DEPENDENCIES(NAME) - # ---------------------- - # See how the compiler implements dependency checking. --# NAME is "CC", "CXX", "GCJ", or "OBJC". -+# NAME is "CC", "CXX", "OBJC", "OBJCXX", "UPC", or "GJC". - # We try a few techniques and use that to set a single cache variable. - # - # We don't AC_REQUIRE the corresponding AC_PROG_CC since the latter was -@@ -176,12 +172,13 @@ AC_REQUIRE([AM_OUTPUT_DEPENDENCY_COMMANDS])dnl - AC_REQUIRE([AM_MAKE_INCLUDE])dnl - AC_REQUIRE([AM_DEP_TRACK])dnl - --ifelse([$1], CC, [depcc="$CC" am_compiler_list=], -- [$1], CXX, [depcc="$CXX" am_compiler_list=], -- [$1], OBJC, [depcc="$OBJC" am_compiler_list='gcc3 gcc'], -- [$1], UPC, [depcc="$UPC" am_compiler_list=], -- [$1], GCJ, [depcc="$GCJ" am_compiler_list='gcc3 gcc'], -- [depcc="$$1" am_compiler_list=]) -+m4_if([$1], [CC], [depcc="$CC" am_compiler_list=], -+ [$1], [CXX], [depcc="$CXX" am_compiler_list=], -+ [$1], [OBJC], [depcc="$OBJC" am_compiler_list='gcc3 gcc'], -+ [$1], [OBJCXX], [depcc="$OBJCXX" am_compiler_list='gcc3 gcc'], -+ [$1], [UPC], [depcc="$UPC" am_compiler_list=], -+ [$1], [GCJ], [depcc="$GCJ" am_compiler_list='gcc3 gcc'], -+ [depcc="$$1" am_compiler_list=]) - - AC_CACHE_CHECK([dependency style of $depcc], - [am_cv_$1_dependencies_compiler_type], -@@ -189,8 +186,9 @@ AC_CACHE_CHECK([dependency style of $depcc], - # We make a subdir and do the tests there. Otherwise we can end up - # making bogus files that we don't know about and never remove. For - # instance it was reported that on HP-UX the gcc test will end up -- # making a dummy file named `D' -- because `-MD' means `put the output -- # in D'. -+ # making a dummy file named 'D' -- because '-MD' means "put the output -+ # in D". -+ rm -rf conftest.dir - mkdir conftest.dir - # Copy depcomp to subdir because otherwise we won't find it if we're - # using a relative directory. -@@ -229,16 +227,16 @@ AC_CACHE_CHECK([dependency style of $depcc], - : > sub/conftest.c - for i in 1 2 3 4 5 6; do - echo '#include "conftst'$i'.h"' >> sub/conftest.c -- # Using `: > sub/conftst$i.h' creates only sub/conftst1.h with -- # Solaris 8's {/usr,}/bin/sh. -- touch sub/conftst$i.h -+ # Using ": > sub/conftst$i.h" creates only sub/conftst1.h with -+ # Solaris 10 /bin/sh. -+ echo '/* dummy */' > sub/conftst$i.h - done - echo "${am__include} ${am__quote}sub/conftest.Po${am__quote}" > confmf - -- # We check with `-c' and `-o' for the sake of the "dashmstdout" -+ # We check with '-c' and '-o' for the sake of the "dashmstdout" - # mode. It turns out that the SunPro C++ compiler does not properly -- # handle `-M -o', and we need to detect this. Also, some Intel -- # versions had trouble with output in subdirs -+ # handle '-M -o', and we need to detect this. Also, some Intel -+ # versions had trouble with output in subdirs. - am__obj=sub/conftest.${OBJEXT-o} - am__minus_obj="-o $am__obj" - case $depmode in -@@ -247,16 +245,16 @@ AC_CACHE_CHECK([dependency style of $depcc], - test "$am__universal" = false || continue - ;; - nosideeffect) -- # after this tag, mechanisms are not by side-effect, so they'll -- # only be used when explicitly requested -+ # After this tag, mechanisms are not by side-effect, so they'll -+ # only be used when explicitly requested. - if test "x$enable_dependency_tracking" = xyes; then - continue - else - break - fi - ;; -- msvisualcpp | msvcmsys) -- # This compiler won't grok `-c -o', but also, the minuso test has -+ msvc7 | msvc7msys | msvisualcpp | msvcmsys) -+ # This compiler won't grok '-c -o', but also, the minuso test has - # not run yet. These depmodes are late enough in the game, and - # so weak that their functioning should not be impacted. - am__obj=conftest.${OBJEXT-o} -@@ -304,7 +302,7 @@ AM_CONDITIONAL([am__fastdep$1], [ - # AM_SET_DEPDIR - # ------------- - # Choose a directory name for dependency files. --# This macro is AC_REQUIREd in _AM_DEPENDENCIES -+# This macro is AC_REQUIREd in _AM_DEPENDENCIES. - AC_DEFUN([AM_SET_DEPDIR], - [AC_REQUIRE([AM_SET_LEADING_DOT])dnl - AC_SUBST([DEPDIR], ["${am__leading_dot}deps"])dnl -@@ -314,34 +312,39 @@ AC_SUBST([DEPDIR], ["${am__leading_dot}deps"])dnl - # AM_DEP_TRACK - # ------------ - AC_DEFUN([AM_DEP_TRACK], --[AC_ARG_ENABLE(dependency-tracking, --[ --disable-dependency-tracking speeds up one-time build -- --enable-dependency-tracking do not reject slow dependency extractors]) -+[AC_ARG_ENABLE([dependency-tracking], [dnl -+AS_HELP_STRING( -+ [--enable-dependency-tracking], -+ [do not reject slow dependency extractors]) -+AS_HELP_STRING( -+ [--disable-dependency-tracking], -+ [speeds up one-time build])]) - if test "x$enable_dependency_tracking" != xno; then - am_depcomp="$ac_aux_dir/depcomp" - AMDEPBACKSLASH='\' -+ am__nodep='_no' - fi - AM_CONDITIONAL([AMDEP], [test "x$enable_dependency_tracking" != xno]) - AC_SUBST([AMDEPBACKSLASH])dnl - _AM_SUBST_NOTMAKE([AMDEPBACKSLASH])dnl -+AC_SUBST([am__nodep])dnl -+_AM_SUBST_NOTMAKE([am__nodep])dnl - ]) - - # Generate code to set up dependency tracking. -*- Autoconf -*- - --# Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2008 --# Free Software Foundation, Inc. -+# Copyright (C) 1999-2013 Free Software Foundation, Inc. - # - # This file is free software; the Free Software Foundation - # gives unlimited permission to copy and/or distribute it, - # with or without modifications, as long as this notice is preserved. - --#serial 5 - - # _AM_OUTPUT_DEPENDENCY_COMMANDS - # ------------------------------ - AC_DEFUN([_AM_OUTPUT_DEPENDENCY_COMMANDS], - [{ -- # Autoconf 2.62 quotes --file arguments for eval, but not when files -+ # Older Autoconf quotes --file arguments for eval, but not when files - # are listed without --file. Let's play safe and only enable the eval - # if we detect the quoting. - case $CONFIG_FILES in -@@ -354,7 +357,7 @@ AC_DEFUN([_AM_OUTPUT_DEPENDENCY_COMMANDS], - # Strip MF so we end up with the name of the file. - mf=`echo "$mf" | sed -e 's/:.*$//'` - # Check whether this is an Automake generated Makefile or not. -- # We used to match only the files named `Makefile.in', but -+ # We used to match only the files named 'Makefile.in', but - # some people rename them; so instead we look at the file content. - # Grep'ing the first line is not enough: some people post-process - # each Makefile.in and add a new line on top of each file to say so. -@@ -366,21 +369,19 @@ AC_DEFUN([_AM_OUTPUT_DEPENDENCY_COMMANDS], - continue - fi - # Extract the definition of DEPDIR, am__include, and am__quote -- # from the Makefile without running `make'. -+ # from the Makefile without running 'make'. - DEPDIR=`sed -n 's/^DEPDIR = //p' < "$mf"` - test -z "$DEPDIR" && continue - am__include=`sed -n 's/^am__include = //p' < "$mf"` -- test -z "am__include" && continue -+ test -z "$am__include" && continue - am__quote=`sed -n 's/^am__quote = //p' < "$mf"` -- # When using ansi2knr, U may be empty or an underscore; expand it -- U=`sed -n 's/^U = //p' < "$mf"` - # Find all dependency output files, they are included files with - # $(DEPDIR) in their names. We invoke sed twice because it is the - # simplest approach to changing $(DEPDIR) to its actual value in the - # expansion. - for file in `sed -n " - s/^$am__include $am__quote\(.*(DEPDIR).*\)$am__quote"'$/\1/p' <"$mf" | \ -- sed -e 's/\$(DEPDIR)/'"$DEPDIR"'/g' -e 's/\$U/'"$U"'/g'`; do -+ sed -e 's/\$(DEPDIR)/'"$DEPDIR"'/g'`; do - # Make sure the directory exists. - test -f "$dirpart/$file" && continue - fdir=`AS_DIRNAME(["$file"])` -@@ -398,7 +399,7 @@ AC_DEFUN([_AM_OUTPUT_DEPENDENCY_COMMANDS], - # This macro should only be invoked once -- use via AC_REQUIRE. - # - # This code is only required when automatic dependency tracking --# is enabled. FIXME. This creates each `.P' file that we will -+# is enabled. FIXME. This creates each '.P' file that we will - # need in order to bootstrap the dependency handling code. - AC_DEFUN([AM_OUTPUT_DEPENDENCY_COMMANDS], - [AC_CONFIG_COMMANDS([depfiles], -@@ -408,18 +409,21 @@ AC_DEFUN([AM_OUTPUT_DEPENDENCY_COMMANDS], - - # Do all the work for Automake. -*- Autoconf -*- - --# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, --# 2005, 2006, 2008, 2009 Free Software Foundation, Inc. -+# Copyright (C) 1996-2013 Free Software Foundation, Inc. - # - # This file is free software; the Free Software Foundation - # gives unlimited permission to copy and/or distribute it, - # with or without modifications, as long as this notice is preserved. - --# serial 16 -- - # This macro actually does too much. Some checks are only needed if - # your package does certain things. But this isn't really a big deal. - -+dnl Redefine AC_PROG_CC to automatically invoke _AM_PROG_CC_C_O. -+m4_define([AC_PROG_CC], -+m4_defn([AC_PROG_CC]) -+[_AM_PROG_CC_C_O -+]) -+ - # AM_INIT_AUTOMAKE(PACKAGE, VERSION, [NO-DEFINE]) - # AM_INIT_AUTOMAKE([OPTIONS]) - # ----------------------------------------------- -@@ -432,7 +436,7 @@ AC_DEFUN([AM_OUTPUT_DEPENDENCY_COMMANDS], - # arguments mandatory, and then we can depend on a new Autoconf - # release and drop the old call support. - AC_DEFUN([AM_INIT_AUTOMAKE], --[AC_PREREQ([2.62])dnl -+[AC_PREREQ([2.65])dnl - dnl Autoconf wants to disallow AM_ names. We explicitly allow - dnl the ones we care about. - m4_pattern_allow([^AM_[A-Z]+FLAGS$])dnl -@@ -461,31 +465,40 @@ AC_SUBST([CYGPATH_W]) - # Define the identity of the package. - dnl Distinguish between old-style and new-style calls. - m4_ifval([$2], --[m4_ifval([$3], [_AM_SET_OPTION([no-define])])dnl -+[AC_DIAGNOSE([obsolete], -+ [$0: two- and three-arguments forms are deprecated.]) -+m4_ifval([$3], [_AM_SET_OPTION([no-define])])dnl - AC_SUBST([PACKAGE], [$1])dnl - AC_SUBST([VERSION], [$2])], - [_AM_SET_OPTIONS([$1])dnl - dnl Diagnose old-style AC_INIT with new-style AM_AUTOMAKE_INIT. --m4_if(m4_ifdef([AC_PACKAGE_NAME], 1)m4_ifdef([AC_PACKAGE_VERSION], 1), 11,, -+m4_if( -+ m4_ifdef([AC_PACKAGE_NAME], [ok]):m4_ifdef([AC_PACKAGE_VERSION], [ok]), -+ [ok:ok],, - [m4_fatal([AC_INIT should be called with package and version arguments])])dnl - AC_SUBST([PACKAGE], ['AC_PACKAGE_TARNAME'])dnl - AC_SUBST([VERSION], ['AC_PACKAGE_VERSION'])])dnl - - _AM_IF_OPTION([no-define],, --[AC_DEFINE_UNQUOTED(PACKAGE, "$PACKAGE", [Name of package]) -- AC_DEFINE_UNQUOTED(VERSION, "$VERSION", [Version number of package])])dnl -+[AC_DEFINE_UNQUOTED([PACKAGE], ["$PACKAGE"], [Name of package]) -+ AC_DEFINE_UNQUOTED([VERSION], ["$VERSION"], [Version number of package])])dnl - - # Some tools Automake needs. - AC_REQUIRE([AM_SANITY_CHECK])dnl - AC_REQUIRE([AC_ARG_PROGRAM])dnl --AM_MISSING_PROG(ACLOCAL, aclocal-${am__api_version}) --AM_MISSING_PROG(AUTOCONF, autoconf) --AM_MISSING_PROG(AUTOMAKE, automake-${am__api_version}) --AM_MISSING_PROG(AUTOHEADER, autoheader) --AM_MISSING_PROG(MAKEINFO, makeinfo) -+AM_MISSING_PROG([ACLOCAL], [aclocal-${am__api_version}]) -+AM_MISSING_PROG([AUTOCONF], [autoconf]) -+AM_MISSING_PROG([AUTOMAKE], [automake-${am__api_version}]) -+AM_MISSING_PROG([AUTOHEADER], [autoheader]) -+AM_MISSING_PROG([MAKEINFO], [makeinfo]) - AC_REQUIRE([AM_PROG_INSTALL_SH])dnl - AC_REQUIRE([AM_PROG_INSTALL_STRIP])dnl --AC_REQUIRE([AM_PROG_MKDIR_P])dnl -+AC_REQUIRE([AC_PROG_MKDIR_P])dnl -+# For better backward compatibility. To be removed once Automake 1.9.x -+# dies out for good. For more background, see: -+# -+# -+AC_SUBST([mkdir_p], ['$(MKDIR_P)']) - # We need awk for the "check" target. The system "awk" is bad on - # some platforms. - AC_REQUIRE([AC_PROG_AWK])dnl -@@ -496,34 +509,78 @@ _AM_IF_OPTION([tar-ustar], [_AM_PROG_TAR([ustar])], - [_AM_PROG_TAR([v7])])]) - _AM_IF_OPTION([no-dependencies],, - [AC_PROVIDE_IFELSE([AC_PROG_CC], -- [_AM_DEPENDENCIES(CC)], -- [define([AC_PROG_CC], -- defn([AC_PROG_CC])[_AM_DEPENDENCIES(CC)])])dnl -+ [_AM_DEPENDENCIES([CC])], -+ [m4_define([AC_PROG_CC], -+ m4_defn([AC_PROG_CC])[_AM_DEPENDENCIES([CC])])])dnl - AC_PROVIDE_IFELSE([AC_PROG_CXX], -- [_AM_DEPENDENCIES(CXX)], -- [define([AC_PROG_CXX], -- defn([AC_PROG_CXX])[_AM_DEPENDENCIES(CXX)])])dnl -+ [_AM_DEPENDENCIES([CXX])], -+ [m4_define([AC_PROG_CXX], -+ m4_defn([AC_PROG_CXX])[_AM_DEPENDENCIES([CXX])])])dnl - AC_PROVIDE_IFELSE([AC_PROG_OBJC], -- [_AM_DEPENDENCIES(OBJC)], -- [define([AC_PROG_OBJC], -- defn([AC_PROG_OBJC])[_AM_DEPENDENCIES(OBJC)])])dnl -+ [_AM_DEPENDENCIES([OBJC])], -+ [m4_define([AC_PROG_OBJC], -+ m4_defn([AC_PROG_OBJC])[_AM_DEPENDENCIES([OBJC])])])dnl -+AC_PROVIDE_IFELSE([AC_PROG_OBJCXX], -+ [_AM_DEPENDENCIES([OBJCXX])], -+ [m4_define([AC_PROG_OBJCXX], -+ m4_defn([AC_PROG_OBJCXX])[_AM_DEPENDENCIES([OBJCXX])])])dnl - ]) --_AM_IF_OPTION([silent-rules], [AC_REQUIRE([AM_SILENT_RULES])])dnl --dnl The `parallel-tests' driver may need to know about EXEEXT, so add the --dnl `am__EXEEXT' conditional if _AM_COMPILER_EXEEXT was seen. This macro --dnl is hooked onto _AC_COMPILER_EXEEXT early, see below. -+AC_REQUIRE([AM_SILENT_RULES])dnl -+dnl The testsuite driver may need to know about EXEEXT, so add the -+dnl 'am__EXEEXT' conditional if _AM_COMPILER_EXEEXT was seen. This -+dnl macro is hooked onto _AC_COMPILER_EXEEXT early, see below. - AC_CONFIG_COMMANDS_PRE(dnl - [m4_provide_if([_AM_COMPILER_EXEEXT], - [AM_CONDITIONAL([am__EXEEXT], [test -n "$EXEEXT"])])])dnl --]) - --dnl Hook into `_AC_COMPILER_EXEEXT' early to learn its expansion. Do not -+# POSIX will say in a future version that running "rm -f" with no argument -+# is OK; and we want to be able to make that assumption in our Makefile -+# recipes. So use an aggressive probe to check that the usage we want is -+# actually supported "in the wild" to an acceptable degree. -+# See automake bug#10828. -+# To make any issue more visible, cause the running configure to be aborted -+# by default if the 'rm' program in use doesn't match our expectations; the -+# user can still override this though. -+if rm -f && rm -fr && rm -rf; then : OK; else -+ cat >&2 <<'END' -+Oops! -+ -+Your 'rm' program seems unable to run without file operands specified -+on the command line, even when the '-f' option is present. This is contrary -+to the behaviour of most rm programs out there, and not conforming with -+the upcoming POSIX standard: -+ -+Please tell bug-automake@gnu.org about your system, including the value -+of your $PATH and any error possibly output before this message. This -+can help us improve future automake versions. -+ -+END -+ if test x"$ACCEPT_INFERIOR_RM_PROGRAM" = x"yes"; then -+ echo 'Configuration will proceed anyway, since you have set the' >&2 -+ echo 'ACCEPT_INFERIOR_RM_PROGRAM variable to "yes"' >&2 -+ echo >&2 -+ else -+ cat >&2 <<'END' -+Aborting the configuration process, to ensure you take notice of the issue. -+ -+You can download and install GNU coreutils to get an 'rm' implementation -+that behaves properly: . -+ -+If you want to complete the configuration process using your problematic -+'rm' anyway, export the environment variable ACCEPT_INFERIOR_RM_PROGRAM -+to "yes", and re-run configure. -+ -+END -+ AC_MSG_ERROR([Your 'rm' program is bad, sorry.]) -+ fi -+fi]) -+ -+dnl Hook into '_AC_COMPILER_EXEEXT' early to learn its expansion. Do not - dnl add the conditional right here, as _AC_COMPILER_EXEEXT may be further - dnl mangled by Autoconf and run in a shell conditional statement. - m4_define([_AC_COMPILER_EXEEXT], - m4_defn([_AC_COMPILER_EXEEXT])[m4_provide([_AM_COMPILER_EXEEXT])]) - -- - # When config.status generates a header, we must update the stamp-h file. - # This file resides in the same directory as the config header - # that is generated. The stamp files are numbered to have different names. -@@ -545,7 +602,7 @@ for _am_header in $config_headers :; do - done - echo "timestamp for $_am_arg" >`AS_DIRNAME(["$_am_arg"])`/stamp-h[]$_am_stamp_count]) - --# Copyright (C) 2001, 2003, 2005, 2008 Free Software Foundation, Inc. -+# Copyright (C) 2001-2013 Free Software Foundation, Inc. - # - # This file is free software; the Free Software Foundation - # gives unlimited permission to copy and/or distribute it, -@@ -564,23 +621,20 @@ if test x"${install_sh}" != xset; then - install_sh="\${SHELL} $am_aux_dir/install-sh" - esac - fi --AC_SUBST(install_sh)]) -+AC_SUBST([install_sh])]) - --# Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2005 --# Free Software Foundation, Inc. -+# Copyright (C) 1998-2013 Free Software Foundation, Inc. - # - # This file is free software; the Free Software Foundation - # gives unlimited permission to copy and/or distribute it, - # with or without modifications, as long as this notice is preserved. - --# serial 5 -- - # AM_PROG_LEX - # ----------- - # Autoconf leaves LEX=: if lex or flex can't be found. Change that to a - # "missing" invocation, for better error output. - AC_DEFUN([AM_PROG_LEX], --[AC_PREREQ(2.50)dnl -+[AC_PREREQ([2.50])dnl - AC_REQUIRE([AM_MISSING_HAS_RUN])dnl - AC_REQUIRE([AC_PROG_LEX])dnl - if test "$LEX" = :; then -@@ -590,20 +644,17 @@ fi]) - # Add --enable-maintainer-mode option to configure. -*- Autoconf -*- - # From Jim Meyering - --# Copyright (C) 1996, 1998, 2000, 2001, 2002, 2003, 2004, 2005, 2008 --# Free Software Foundation, Inc. -+# Copyright (C) 1996-2013 Free Software Foundation, Inc. - # - # This file is free software; the Free Software Foundation - # gives unlimited permission to copy and/or distribute it, - # with or without modifications, as long as this notice is preserved. - --# serial 5 -- - # AM_MAINTAINER_MODE([DEFAULT-MODE]) - # ---------------------------------- - # Control maintainer-specific portions of Makefiles. --# Default is to disable them, unless `enable' is passed literally. --# For symmetry, `disable' may be passed as well. Anyway, the user -+# Default is to disable them, unless 'enable' is passed literally. -+# For symmetry, 'disable' may be passed as well. Anyway, the user - # can override the default with the --enable/--disable switch. - AC_DEFUN([AM_MAINTAINER_MODE], - [m4_case(m4_default([$1], [disable]), -@@ -611,13 +662,14 @@ AC_DEFUN([AM_MAINTAINER_MODE], - [disable], [m4_define([am_maintainer_other], [enable])], - [m4_define([am_maintainer_other], [enable]) - m4_warn([syntax], [unexpected argument to AM@&t@_MAINTAINER_MODE: $1])]) --AC_MSG_CHECKING([whether to am_maintainer_other maintainer-specific portions of Makefiles]) -+AC_MSG_CHECKING([whether to enable maintainer-specific portions of Makefiles]) - dnl maintainer-mode's default is 'disable' unless 'enable' is passed - AC_ARG_ENABLE([maintainer-mode], --[ --][am_maintainer_other][-maintainer-mode am_maintainer_other make rules and dependencies not useful -- (and sometimes confusing) to the casual installer], -- [USE_MAINTAINER_MODE=$enableval], -- [USE_MAINTAINER_MODE=]m4_if(am_maintainer_other, [enable], [no], [yes])) -+ [AS_HELP_STRING([--]am_maintainer_other[-maintainer-mode], -+ am_maintainer_other[ make rules and dependencies not useful -+ (and sometimes confusing) to the casual installer])], -+ [USE_MAINTAINER_MODE=$enableval], -+ [USE_MAINTAINER_MODE=]m4_if(am_maintainer_other, [enable], [no], [yes])) - AC_MSG_RESULT([$USE_MAINTAINER_MODE]) - AM_CONDITIONAL([MAINTAINER_MODE], [test $USE_MAINTAINER_MODE = yes]) - MAINT=$MAINTAINER_MODE_TRUE -@@ -625,18 +677,14 @@ AC_MSG_CHECKING([whether to am_maintainer_other maintainer-specific portions of - ] - ) - --AU_DEFUN([jm_MAINTAINER_MODE], [AM_MAINTAINER_MODE]) -- - # Check to see how 'make' treats includes. -*- Autoconf -*- - --# Copyright (C) 2001, 2002, 2003, 2005, 2009 Free Software Foundation, Inc. -+# Copyright (C) 2001-2013 Free Software Foundation, Inc. - # - # This file is free software; the Free Software Foundation - # gives unlimited permission to copy and/or distribute it, - # with or without modifications, as long as this notice is preserved. - --# serial 4 -- - # AM_MAKE_INCLUDE() - # ----------------- - # Check to see how make treats includes. -@@ -654,7 +702,7 @@ am__quote= - _am_result=none - # First try GNU make style include. - echo "include confinc" > confmf --# Ignore all kinds of additional output from `make'. -+# Ignore all kinds of additional output from 'make'. - case `$am_make -s -f confmf 2> /dev/null` in #( - *the\ am__doit\ target*) - am__include=include -@@ -681,15 +729,12 @@ rm -f confinc confmf - - # Fake the existence of programs that GNU maintainers use. -*- Autoconf -*- - --# Copyright (C) 1997, 1999, 2000, 2001, 2003, 2004, 2005, 2008 --# Free Software Foundation, Inc. -+# Copyright (C) 1997-2013 Free Software Foundation, Inc. - # - # This file is free software; the Free Software Foundation - # gives unlimited permission to copy and/or distribute it, - # with or without modifications, as long as this notice is preserved. - --# serial 6 -- - # AM_MISSING_PROG(NAME, PROGRAM) - # ------------------------------ - AC_DEFUN([AM_MISSING_PROG], -@@ -697,11 +742,10 @@ AC_DEFUN([AM_MISSING_PROG], - $1=${$1-"${am_missing_run}$2"} - AC_SUBST($1)]) - -- - # AM_MISSING_HAS_RUN - # ------------------ --# Define MISSING if not defined so far and test if it supports --run. --# If it does, set am_missing_run to use it, otherwise, to nothing. -+# Define MISSING if not defined so far and test if it is modern enough. -+# If it is, set am_missing_run to use it, otherwise, to nothing. - AC_DEFUN([AM_MISSING_HAS_RUN], - [AC_REQUIRE([AM_AUX_DIR_EXPAND])dnl - AC_REQUIRE_AUX_FILE([missing])dnl -@@ -714,63 +758,35 @@ if test x"${MISSING+set}" != xset; then - esac - fi - # Use eval to expand $SHELL --if eval "$MISSING --run true"; then -- am_missing_run="$MISSING --run " -+if eval "$MISSING --is-lightweight"; then -+ am_missing_run="$MISSING " - else - am_missing_run= -- AC_MSG_WARN([`missing' script is too old or missing]) -+ AC_MSG_WARN(['missing' script is too old or missing]) - fi - ]) - --# Copyright (C) 2003, 2004, 2005, 2006 Free Software Foundation, Inc. --# --# This file is free software; the Free Software Foundation --# gives unlimited permission to copy and/or distribute it, --# with or without modifications, as long as this notice is preserved. -- --# AM_PROG_MKDIR_P --# --------------- --# Check for `mkdir -p'. --AC_DEFUN([AM_PROG_MKDIR_P], --[AC_PREREQ([2.60])dnl --AC_REQUIRE([AC_PROG_MKDIR_P])dnl --dnl Automake 1.8 to 1.9.6 used to define mkdir_p. We now use MKDIR_P, --dnl while keeping a definition of mkdir_p for backward compatibility. --dnl @MKDIR_P@ is magic: AC_OUTPUT adjusts its value for each Makefile. --dnl However we cannot define mkdir_p as $(MKDIR_P) for the sake of --dnl Makefile.ins that do not define MKDIR_P, so we do our own --dnl adjustment using top_builddir (which is defined more often than --dnl MKDIR_P). --AC_SUBST([mkdir_p], ["$MKDIR_P"])dnl --case $mkdir_p in -- [[\\/$]]* | ?:[[\\/]]*) ;; -- */*) mkdir_p="\$(top_builddir)/$mkdir_p" ;; --esac --]) -- - # Helper functions for option handling. -*- Autoconf -*- - --# Copyright (C) 2001, 2002, 2003, 2005, 2008 Free Software Foundation, Inc. -+# Copyright (C) 2001-2013 Free Software Foundation, Inc. - # - # This file is free software; the Free Software Foundation - # gives unlimited permission to copy and/or distribute it, - # with or without modifications, as long as this notice is preserved. - --# serial 4 -- - # _AM_MANGLE_OPTION(NAME) - # ----------------------- - AC_DEFUN([_AM_MANGLE_OPTION], - [[_AM_OPTION_]m4_bpatsubst($1, [[^a-zA-Z0-9_]], [_])]) - - # _AM_SET_OPTION(NAME) --# ------------------------------ -+# -------------------- - # Set option NAME. Presently that only means defining a flag for this option. - AC_DEFUN([_AM_SET_OPTION], --[m4_define(_AM_MANGLE_OPTION([$1]), 1)]) -+[m4_define(_AM_MANGLE_OPTION([$1]), [1])]) - - # _AM_SET_OPTIONS(OPTIONS) --# ---------------------------------- -+# ------------------------ - # OPTIONS is a space-separated list of Automake options. - AC_DEFUN([_AM_SET_OPTIONS], - [m4_foreach_w([_AM_Option], [$1], [_AM_SET_OPTION(_AM_Option)])]) -@@ -781,24 +797,82 @@ AC_DEFUN([_AM_SET_OPTIONS], - AC_DEFUN([_AM_IF_OPTION], - [m4_ifset(_AM_MANGLE_OPTION([$1]), [$2], [$3])]) - --# Check to make sure that the build environment is sane. -*- Autoconf -*- -+# Copyright (C) 1999-2013 Free Software Foundation, Inc. -+# -+# This file is free software; the Free Software Foundation -+# gives unlimited permission to copy and/or distribute it, -+# with or without modifications, as long as this notice is preserved. - --# Copyright (C) 1996, 1997, 2000, 2001, 2003, 2005, 2008 --# Free Software Foundation, Inc. -+# _AM_PROG_CC_C_O -+# --------------- -+# Like AC_PROG_CC_C_O, but changed for automake. We rewrite AC_PROG_CC -+# to automatically call this. -+AC_DEFUN([_AM_PROG_CC_C_O], -+[AC_REQUIRE([AM_AUX_DIR_EXPAND])dnl -+AC_REQUIRE_AUX_FILE([compile])dnl -+AC_LANG_PUSH([C])dnl -+AC_CACHE_CHECK( -+ [whether $CC understands -c and -o together], -+ [am_cv_prog_cc_c_o], -+ [AC_LANG_CONFTEST([AC_LANG_PROGRAM([])]) -+ # Make sure it works both with $CC and with simple cc. -+ # Following AC_PROG_CC_C_O, we do the test twice because some -+ # compilers refuse to overwrite an existing .o file with -o, -+ # though they will create one. -+ am_cv_prog_cc_c_o=yes -+ for am_i in 1 2; do -+ if AM_RUN_LOG([$CC -c conftest.$ac_ext -o conftest2.$ac_objext]) \ -+ && test -f conftest2.$ac_objext; then -+ : OK -+ else -+ am_cv_prog_cc_c_o=no -+ break -+ fi -+ done -+ rm -f core conftest* -+ unset am_i]) -+if test "$am_cv_prog_cc_c_o" != yes; then -+ # Losing compiler, so override with the script. -+ # FIXME: It is wrong to rewrite CC. -+ # But if we don't then we get into trouble of one sort or another. -+ # A longer-term fix would be to have automake use am__CC in this case, -+ # and then we could set am__CC="\$(top_srcdir)/compile \$(CC)" -+ CC="$am_aux_dir/compile $CC" -+fi -+AC_LANG_POP([C])]) -+ -+# For backward compatibility. -+AC_DEFUN_ONCE([AM_PROG_CC_C_O], [AC_REQUIRE([AC_PROG_CC])]) -+ -+# Copyright (C) 2001-2013 Free Software Foundation, Inc. - # - # This file is free software; the Free Software Foundation - # gives unlimited permission to copy and/or distribute it, - # with or without modifications, as long as this notice is preserved. - --# serial 5 -+# AM_RUN_LOG(COMMAND) -+# ------------------- -+# Run COMMAND, save the exit status in ac_status, and log it. -+# (This has been adapted from Autoconf's _AC_RUN_LOG macro.) -+AC_DEFUN([AM_RUN_LOG], -+[{ echo "$as_me:$LINENO: $1" >&AS_MESSAGE_LOG_FD -+ ($1) >&AS_MESSAGE_LOG_FD 2>&AS_MESSAGE_LOG_FD -+ ac_status=$? -+ echo "$as_me:$LINENO: \$? = $ac_status" >&AS_MESSAGE_LOG_FD -+ (exit $ac_status); }]) -+ -+# Check to make sure that the build environment is sane. -*- Autoconf -*- -+ -+# Copyright (C) 1996-2013 Free Software Foundation, Inc. -+# -+# This file is free software; the Free Software Foundation -+# gives unlimited permission to copy and/or distribute it, -+# with or without modifications, as long as this notice is preserved. - - # AM_SANITY_CHECK - # --------------- - AC_DEFUN([AM_SANITY_CHECK], - [AC_MSG_CHECKING([whether build environment is sane]) --# Just in case --sleep 1 --echo timestamp > conftest.file - # Reject unsafe characters in $srcdir or the absolute working directory - # name. Accept space and tab only in the latter. - am_lf=' -@@ -809,32 +883,40 @@ case `pwd` in - esac - case $srcdir in - *[[\\\"\#\$\&\'\`$am_lf\ \ ]]*) -- AC_MSG_ERROR([unsafe srcdir value: `$srcdir']);; -+ AC_MSG_ERROR([unsafe srcdir value: '$srcdir']);; - esac - --# Do `set' in a subshell so we don't clobber the current shell's -+# Do 'set' in a subshell so we don't clobber the current shell's - # arguments. Must try -L first in case configure is actually a - # symlink; some systems play weird games with the mod time of symlinks - # (eg FreeBSD returns the mod time of the symlink's containing - # directory). - if ( -- set X `ls -Lt "$srcdir/configure" conftest.file 2> /dev/null` -- if test "$[*]" = "X"; then -- # -L didn't work. -- set X `ls -t "$srcdir/configure" conftest.file` -- fi -- rm -f conftest.file -- if test "$[*]" != "X $srcdir/configure conftest.file" \ -- && test "$[*]" != "X conftest.file $srcdir/configure"; then -- -- # If neither matched, then we have a broken ls. This can happen -- # if, for instance, CONFIG_SHELL is bash and it inherits a -- # broken ls alias from the environment. This has actually -- # happened. Such a system could not be considered "sane". -- AC_MSG_ERROR([ls -t appears to fail. Make sure there is not a broken --alias in your environment]) -- fi -- -+ am_has_slept=no -+ for am_try in 1 2; do -+ echo "timestamp, slept: $am_has_slept" > conftest.file -+ set X `ls -Lt "$srcdir/configure" conftest.file 2> /dev/null` -+ if test "$[*]" = "X"; then -+ # -L didn't work. -+ set X `ls -t "$srcdir/configure" conftest.file` -+ fi -+ if test "$[*]" != "X $srcdir/configure conftest.file" \ -+ && test "$[*]" != "X conftest.file $srcdir/configure"; then -+ -+ # If neither matched, then we have a broken ls. This can happen -+ # if, for instance, CONFIG_SHELL is bash and it inherits a -+ # broken ls alias from the environment. This has actually -+ # happened. Such a system could not be considered "sane". -+ AC_MSG_ERROR([ls -t appears to fail. Make sure there is not a broken -+ alias in your environment]) -+ fi -+ if test "$[2]" = conftest.file || test $am_try -eq 2; then -+ break -+ fi -+ # Just in case. -+ sleep 1 -+ am_has_slept=yes -+ done - test "$[2]" = conftest.file - ) - then -@@ -844,9 +926,85 @@ else - AC_MSG_ERROR([newly created file is older than distributed files! - Check your system clock]) - fi --AC_MSG_RESULT(yes)]) -+AC_MSG_RESULT([yes]) -+# If we didn't sleep, we still need to ensure time stamps of config.status and -+# generated files are strictly newer. -+am_sleep_pid= -+if grep 'slept: no' conftest.file >/dev/null 2>&1; then -+ ( sleep 1 ) & -+ am_sleep_pid=$! -+fi -+AC_CONFIG_COMMANDS_PRE( -+ [AC_MSG_CHECKING([that generated files are newer than configure]) -+ if test -n "$am_sleep_pid"; then -+ # Hide warnings about reused PIDs. -+ wait $am_sleep_pid 2>/dev/null -+ fi -+ AC_MSG_RESULT([done])]) -+rm -f conftest.file -+]) -+ -+# Copyright (C) 2009-2013 Free Software Foundation, Inc. -+# -+# This file is free software; the Free Software Foundation -+# gives unlimited permission to copy and/or distribute it, -+# with or without modifications, as long as this notice is preserved. -+ -+# AM_SILENT_RULES([DEFAULT]) -+# -------------------------- -+# Enable less verbose build rules; with the default set to DEFAULT -+# ("yes" being less verbose, "no" or empty being verbose). -+AC_DEFUN([AM_SILENT_RULES], -+[AC_ARG_ENABLE([silent-rules], [dnl -+AS_HELP_STRING( -+ [--enable-silent-rules], -+ [less verbose build output (undo: "make V=1")]) -+AS_HELP_STRING( -+ [--disable-silent-rules], -+ [verbose build output (undo: "make V=0")])dnl -+]) -+case $enable_silent_rules in @%:@ ((( -+ yes) AM_DEFAULT_VERBOSITY=0;; -+ no) AM_DEFAULT_VERBOSITY=1;; -+ *) AM_DEFAULT_VERBOSITY=m4_if([$1], [yes], [0], [1]);; -+esac -+dnl -+dnl A few 'make' implementations (e.g., NonStop OS and NextStep) -+dnl do not support nested variable expansions. -+dnl See automake bug#9928 and bug#10237. -+am_make=${MAKE-make} -+AC_CACHE_CHECK([whether $am_make supports nested variables], -+ [am_cv_make_support_nested_variables], -+ [if AS_ECHO([['TRUE=$(BAR$(V)) -+BAR0=false -+BAR1=true -+V=1 -+am__doit: -+ @$(TRUE) -+.PHONY: am__doit']]) | $am_make -f - >/dev/null 2>&1; then -+ am_cv_make_support_nested_variables=yes -+else -+ am_cv_make_support_nested_variables=no -+fi]) -+if test $am_cv_make_support_nested_variables = yes; then -+ dnl Using '$V' instead of '$(V)' breaks IRIX make. -+ AM_V='$(V)' -+ AM_DEFAULT_V='$(AM_DEFAULT_VERBOSITY)' -+else -+ AM_V=$AM_DEFAULT_VERBOSITY -+ AM_DEFAULT_V=$AM_DEFAULT_VERBOSITY -+fi -+AC_SUBST([AM_V])dnl -+AM_SUBST_NOTMAKE([AM_V])dnl -+AC_SUBST([AM_DEFAULT_V])dnl -+AM_SUBST_NOTMAKE([AM_DEFAULT_V])dnl -+AC_SUBST([AM_DEFAULT_VERBOSITY])dnl -+AM_BACKSLASH='\' -+AC_SUBST([AM_BACKSLASH])dnl -+_AM_SUBST_NOTMAKE([AM_BACKSLASH])dnl -+]) - --# Copyright (C) 2001, 2003, 2005 Free Software Foundation, Inc. -+# Copyright (C) 2001-2013 Free Software Foundation, Inc. - # - # This file is free software; the Free Software Foundation - # gives unlimited permission to copy and/or distribute it, -@@ -854,34 +1012,32 @@ AC_MSG_RESULT(yes)]) - - # AM_PROG_INSTALL_STRIP - # --------------------- --# One issue with vendor `install' (even GNU) is that you can't -+# One issue with vendor 'install' (even GNU) is that you can't - # specify the program used to strip binaries. This is especially - # annoying in cross-compiling environments, where the build's strip - # is unlikely to handle the host's binaries. - # Fortunately install-sh will honor a STRIPPROG variable, so we --# always use install-sh in `make install-strip', and initialize -+# always use install-sh in "make install-strip", and initialize - # STRIPPROG with the value of the STRIP variable (set by the user). - AC_DEFUN([AM_PROG_INSTALL_STRIP], - [AC_REQUIRE([AM_PROG_INSTALL_SH])dnl --# Installed binaries are usually stripped using `strip' when the user --# run `make install-strip'. However `strip' might not be the right -+# Installed binaries are usually stripped using 'strip' when the user -+# run "make install-strip". However 'strip' might not be the right - # tool to use in cross-compilation environments, therefore Automake --# will honor the `STRIP' environment variable to overrule this program. --dnl Don't test for $cross_compiling = yes, because it might be `maybe'. -+# will honor the 'STRIP' environment variable to overrule this program. -+dnl Don't test for $cross_compiling = yes, because it might be 'maybe'. - if test "$cross_compiling" != no; then - AC_CHECK_TOOL([STRIP], [strip], :) - fi - INSTALL_STRIP_PROGRAM="\$(install_sh) -c -s" - AC_SUBST([INSTALL_STRIP_PROGRAM])]) - --# Copyright (C) 2006, 2008 Free Software Foundation, Inc. -+# Copyright (C) 2006-2013 Free Software Foundation, Inc. - # - # This file is free software; the Free Software Foundation - # gives unlimited permission to copy and/or distribute it, - # with or without modifications, as long as this notice is preserved. - --# serial 2 -- - # _AM_SUBST_NOTMAKE(VARIABLE) - # --------------------------- - # Prevent Automake from outputting VARIABLE = @VARIABLE@ in Makefile.in. -@@ -889,24 +1045,22 @@ AC_SUBST([INSTALL_STRIP_PROGRAM])]) - AC_DEFUN([_AM_SUBST_NOTMAKE]) - - # AM_SUBST_NOTMAKE(VARIABLE) --# --------------------------- -+# -------------------------- - # Public sister of _AM_SUBST_NOTMAKE. - AC_DEFUN([AM_SUBST_NOTMAKE], [_AM_SUBST_NOTMAKE($@)]) - - # Check how to create a tarball. -*- Autoconf -*- - --# Copyright (C) 2004, 2005 Free Software Foundation, Inc. -+# Copyright (C) 2004-2013 Free Software Foundation, Inc. - # - # This file is free software; the Free Software Foundation - # gives unlimited permission to copy and/or distribute it, - # with or without modifications, as long as this notice is preserved. - --# serial 2 -- - # _AM_PROG_TAR(FORMAT) - # -------------------- - # Check how to create a tarball in format FORMAT. --# FORMAT should be one of `v7', `ustar', or `pax'. -+# FORMAT should be one of 'v7', 'ustar', or 'pax'. - # - # Substitute a variable $(am__tar) that is a command - # writing to stdout a FORMAT-tarball containing the directory -@@ -916,75 +1070,114 @@ AC_DEFUN([AM_SUBST_NOTMAKE], [_AM_SUBST_NOTMAKE($@)]) - # Substitute a variable $(am__untar) that extract such - # a tarball read from stdin. - # $(am__untar) < result.tar -+# - AC_DEFUN([_AM_PROG_TAR], --[# Always define AMTAR for backward compatibility. --AM_MISSING_PROG([AMTAR], [tar]) --m4_if([$1], [v7], -- [am__tar='${AMTAR} chof - "$$tardir"'; am__untar='${AMTAR} xf -'], -- [m4_case([$1], [ustar],, [pax],, -- [m4_fatal([Unknown tar format])]) --AC_MSG_CHECKING([how to create a $1 tar archive]) --# Loop over all known methods to create a tar archive until one works. -+[# Always define AMTAR for backward compatibility. Yes, it's still used -+# in the wild :-( We should find a proper way to deprecate it ... -+AC_SUBST([AMTAR], ['$${TAR-tar}']) -+ -+# We'll loop over all known methods to create a tar archive until one works. - _am_tools='gnutar m4_if([$1], [ustar], [plaintar]) pax cpio none' --_am_tools=${am_cv_prog_tar_$1-$_am_tools} --# Do not fold the above two line into one, because Tru64 sh and --# Solaris sh will not grok spaces in the rhs of `-'. --for _am_tool in $_am_tools --do -- case $_am_tool in -- gnutar) -- for _am_tar in tar gnutar gtar; -- do -- AM_RUN_LOG([$_am_tar --version]) && break -- done -- am__tar="$_am_tar --format=m4_if([$1], [pax], [posix], [$1]) -chf - "'"$$tardir"' -- am__tar_="$_am_tar --format=m4_if([$1], [pax], [posix], [$1]) -chf - "'"$tardir"' -- am__untar="$_am_tar -xf -" -- ;; -- plaintar) -- # Must skip GNU tar: if it does not support --format= it doesn't create -- # ustar tarball either. -- (tar --version) >/dev/null 2>&1 && continue -- am__tar='tar chf - "$$tardir"' -- am__tar_='tar chf - "$tardir"' -- am__untar='tar xf -' -- ;; -- pax) -- am__tar='pax -L -x $1 -w "$$tardir"' -- am__tar_='pax -L -x $1 -w "$tardir"' -- am__untar='pax -r' -- ;; -- cpio) -- am__tar='find "$$tardir" -print | cpio -o -H $1 -L' -- am__tar_='find "$tardir" -print | cpio -o -H $1 -L' -- am__untar='cpio -i -H $1 -d' -- ;; -- none) -- am__tar=false -- am__tar_=false -- am__untar=false -- ;; -- esac - -- # If the value was cached, stop now. We just wanted to have am__tar -- # and am__untar set. -- test -n "${am_cv_prog_tar_$1}" && break -+m4_if([$1], [v7], -+ [am__tar='$${TAR-tar} chof - "$$tardir"' am__untar='$${TAR-tar} xf -'], -+ -+ [m4_case([$1], -+ [ustar], -+ [# The POSIX 1988 'ustar' format is defined with fixed-size fields. -+ # There is notably a 21 bits limit for the UID and the GID. In fact, -+ # the 'pax' utility can hang on bigger UID/GID (see automake bug#8343 -+ # and bug#13588). -+ am_max_uid=2097151 # 2^21 - 1 -+ am_max_gid=$am_max_uid -+ # The $UID and $GID variables are not portable, so we need to resort -+ # to the POSIX-mandated id(1) utility. Errors in the 'id' calls -+ # below are definitely unexpected, so allow the users to see them -+ # (that is, avoid stderr redirection). -+ am_uid=`id -u || echo unknown` -+ am_gid=`id -g || echo unknown` -+ AC_MSG_CHECKING([whether UID '$am_uid' is supported by ustar format]) -+ if test $am_uid -le $am_max_uid; then -+ AC_MSG_RESULT([yes]) -+ else -+ AC_MSG_RESULT([no]) -+ _am_tools=none -+ fi -+ AC_MSG_CHECKING([whether GID '$am_gid' is supported by ustar format]) -+ if test $am_gid -le $am_max_gid; then -+ AC_MSG_RESULT([yes]) -+ else -+ AC_MSG_RESULT([no]) -+ _am_tools=none -+ fi], -+ -+ [pax], -+ [], -+ -+ [m4_fatal([Unknown tar format])]) -+ -+ AC_MSG_CHECKING([how to create a $1 tar archive]) -+ -+ # Go ahead even if we have the value already cached. We do so because we -+ # need to set the values for the 'am__tar' and 'am__untar' variables. -+ _am_tools=${am_cv_prog_tar_$1-$_am_tools} -+ -+ for _am_tool in $_am_tools; do -+ case $_am_tool in -+ gnutar) -+ for _am_tar in tar gnutar gtar; do -+ AM_RUN_LOG([$_am_tar --version]) && break -+ done -+ am__tar="$_am_tar --format=m4_if([$1], [pax], [posix], [$1]) -chf - "'"$$tardir"' -+ am__tar_="$_am_tar --format=m4_if([$1], [pax], [posix], [$1]) -chf - "'"$tardir"' -+ am__untar="$_am_tar -xf -" -+ ;; -+ plaintar) -+ # Must skip GNU tar: if it does not support --format= it doesn't create -+ # ustar tarball either. -+ (tar --version) >/dev/null 2>&1 && continue -+ am__tar='tar chf - "$$tardir"' -+ am__tar_='tar chf - "$tardir"' -+ am__untar='tar xf -' -+ ;; -+ pax) -+ am__tar='pax -L -x $1 -w "$$tardir"' -+ am__tar_='pax -L -x $1 -w "$tardir"' -+ am__untar='pax -r' -+ ;; -+ cpio) -+ am__tar='find "$$tardir" -print | cpio -o -H $1 -L' -+ am__tar_='find "$tardir" -print | cpio -o -H $1 -L' -+ am__untar='cpio -i -H $1 -d' -+ ;; -+ none) -+ am__tar=false -+ am__tar_=false -+ am__untar=false -+ ;; -+ esac - -- # tar/untar a dummy directory, and stop if the command works -- rm -rf conftest.dir -- mkdir conftest.dir -- echo GrepMe > conftest.dir/file -- AM_RUN_LOG([tardir=conftest.dir && eval $am__tar_ >conftest.tar]) -+ # If the value was cached, stop now. We just wanted to have am__tar -+ # and am__untar set. -+ test -n "${am_cv_prog_tar_$1}" && break -+ -+ # tar/untar a dummy directory, and stop if the command works. -+ rm -rf conftest.dir -+ mkdir conftest.dir -+ echo GrepMe > conftest.dir/file -+ AM_RUN_LOG([tardir=conftest.dir && eval $am__tar_ >conftest.tar]) -+ rm -rf conftest.dir -+ if test -s conftest.tar; then -+ AM_RUN_LOG([$am__untar /dev/null 2>&1 && break -+ fi -+ done - rm -rf conftest.dir -- if test -s conftest.tar; then -- AM_RUN_LOG([$am__untar /dev/null 2>&1 && break -- fi --done --rm -rf conftest.dir - --AC_CACHE_VAL([am_cv_prog_tar_$1], [am_cv_prog_tar_$1=$_am_tool]) --AC_MSG_RESULT([$am_cv_prog_tar_$1])]) -+ AC_CACHE_VAL([am_cv_prog_tar_$1], [am_cv_prog_tar_$1=$_am_tool]) -+ AC_MSG_RESULT([$am_cv_prog_tar_$1])]) -+ - AC_SUBST([am__tar]) - AC_SUBST([am__untar]) - ]) # _AM_PROG_TAR -diff --git a/ld/config.in b/ld/config.in -index f4a8a23..f13a3c1 100644 ---- a/ld/config.in -+++ b/ld/config.in -@@ -220,6 +220,11 @@ - `char[]'. */ - #undef YYTEXT_POINTER - -+/* Enable large inode numbers on Mac OS X 10.5. */ -+#ifndef _DARWIN_USE_64_BIT_INODE -+# define _DARWIN_USE_64_BIT_INODE 1 -+#endif -+ - /* Number of bits in a file offset, on hosts where this is settable. */ - #undef _FILE_OFFSET_BITS - -diff --git a/ld/configure b/ld/configure -index 63d17e2..8ca580d 100755 ---- a/ld/configure -+++ b/ld/configure -@@ -1,10 +1,10 @@ - #! /bin/sh - # Guess values for system-dependent variables and create Makefiles. --# Generated by GNU Autoconf 2.64. -+# Generated by GNU Autoconf 2.69. -+# -+# -+# Copyright (C) 1992-1996, 1998-2012 Free Software Foundation, Inc. - # --# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, --# 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software --# Foundation, Inc. - # - # This configure script is free software; the Free Software Foundation - # gives unlimited permission to copy, distribute and modify it. -@@ -87,6 +87,7 @@ fi - IFS=" "" $as_nl" - - # Find who we are. Look in the path if we contain no directory separator. -+as_myself= - case $0 in #(( - *[\\/]* ) as_myself=$0 ;; - *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -@@ -131,6 +132,31 @@ export LANGUAGE - # CDPATH. - (unset CDPATH) >/dev/null 2>&1 && unset CDPATH - -+# Use a proper internal environment variable to ensure we don't fall -+ # into an infinite loop, continuously re-executing ourselves. -+ if test x"${_as_can_reexec}" != xno && test "x$CONFIG_SHELL" != x; then -+ _as_can_reexec=no; export _as_can_reexec; -+ # We cannot yet assume a decent shell, so we have to provide a -+# neutralization value for shells without unset; and this also -+# works around shells that cannot unset nonexistent variables. -+# Preserve -v and -x to the replacement shell. -+BASH_ENV=/dev/null -+ENV=/dev/null -+(unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV -+case $- in # (((( -+ *v*x* | *x*v* ) as_opts=-vx ;; -+ *v* ) as_opts=-v ;; -+ *x* ) as_opts=-x ;; -+ * ) as_opts= ;; -+esac -+exec $CONFIG_SHELL $as_opts "$as_myself" ${1+"$@"} -+# Admittedly, this is quite paranoid, since all the known shells bail -+# out after a failed `exec'. -+$as_echo "$0: could not re-execute with $CONFIG_SHELL" >&2 -+as_fn_exit 255 -+ fi -+ # We don't want this to propagate to other subprocesses. -+ { _as_can_reexec=; unset _as_can_reexec;} - if test "x$CONFIG_SHELL" = x; then - as_bourne_compatible="if test -n \"\${ZSH_VERSION+set}\" && (emulate sh) >/dev/null 2>&1; then : - emulate sh -@@ -164,7 +190,8 @@ if ( set x; as_fn_ret_success y && test x = \"\$1\" ); then : - else - exitcode=1; echo positional parameters were not saved. - fi --test x\$exitcode = x0 || exit 1" -+test x\$exitcode = x0 || exit 1 -+test -x / || exit 1" - as_suggested=" as_lineno_1=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_1a=\$LINENO - as_lineno_2=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_2a=\$LINENO - eval 'test \"x\$as_lineno_1'\$as_run'\" != \"x\$as_lineno_2'\$as_run'\" && -@@ -217,14 +244,25 @@ IFS=$as_save_IFS - - - if test "x$CONFIG_SHELL" != x; then : -- # We cannot yet assume a decent shell, so we have to provide a -- # neutralization value for shells without unset; and this also -- # works around shells that cannot unset nonexistent variables. -- BASH_ENV=/dev/null -- ENV=/dev/null -- (unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV -- export CONFIG_SHELL -- exec "$CONFIG_SHELL" "$as_myself" ${1+"$@"} -+ export CONFIG_SHELL -+ # We cannot yet assume a decent shell, so we have to provide a -+# neutralization value for shells without unset; and this also -+# works around shells that cannot unset nonexistent variables. -+# Preserve -v and -x to the replacement shell. -+BASH_ENV=/dev/null -+ENV=/dev/null -+(unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV -+case $- in # (((( -+ *v*x* | *x*v* ) as_opts=-vx ;; -+ *v* ) as_opts=-v ;; -+ *x* ) as_opts=-x ;; -+ * ) as_opts= ;; -+esac -+exec $CONFIG_SHELL $as_opts "$as_myself" ${1+"$@"} -+# Admittedly, this is quite paranoid, since all the known shells bail -+# out after a failed `exec'. -+$as_echo "$0: could not re-execute with $CONFIG_SHELL" >&2 -+exit 255 - fi - - if test x$as_have_required = xno; then : -@@ -322,10 +360,18 @@ $as_echo X"$as_dir" | - test -d "$as_dir" && break - done - test -z "$as_dirs" || eval "mkdir $as_dirs" -- } || test -d "$as_dir" || as_fn_error "cannot create directory $as_dir" -+ } || test -d "$as_dir" || as_fn_error $? "cannot create directory $as_dir" - - - } # as_fn_mkdir_p -+ -+# as_fn_executable_p FILE -+# ----------------------- -+# Test if FILE is an executable regular file. -+as_fn_executable_p () -+{ -+ test -f "$1" && test -x "$1" -+} # as_fn_executable_p - # as_fn_append VAR VALUE - # ---------------------- - # Append the text in VALUE to the end of the definition contained in VAR. Take -@@ -362,19 +408,19 @@ else - fi # as_fn_arith - - --# as_fn_error ERROR [LINENO LOG_FD] --# --------------------------------- -+# as_fn_error STATUS ERROR [LINENO LOG_FD] -+# ---------------------------------------- - # Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are - # provided, also output the error to LOG_FD, referencing LINENO. Then exit the --# script with status $?, using 1 if that was 0. -+# script with STATUS, using 1 if that was 0. - as_fn_error () - { -- as_status=$?; test $as_status -eq 0 && as_status=1 -- if test "$3"; then -- as_lineno=${as_lineno-"$2"} as_lineno_stack=as_lineno_stack=$as_lineno_stack -- $as_echo "$as_me:${as_lineno-$LINENO}: error: $1" >&$3 -+ as_status=$1; test $as_status -eq 0 && as_status=1 -+ if test "$4"; then -+ as_lineno=${as_lineno-"$3"} as_lineno_stack=as_lineno_stack=$as_lineno_stack -+ $as_echo "$as_me:${as_lineno-$LINENO}: error: $2" >&$4 - fi -- $as_echo "$as_me: error: $1" >&2 -+ $as_echo "$as_me: error: $2" >&2 - as_fn_exit $as_status - } # as_fn_error - -@@ -447,6 +493,10 @@ as_cr_alnum=$as_cr_Letters$as_cr_digits - chmod +x "$as_me.lineno" || - { $as_echo "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2; as_fn_exit 1; } - -+ # If we had to re-execute with $CONFIG_SHELL, we're ensured to have -+ # already done that, so ensure we don't try to do so again and fall -+ # in an infinite loop. This has already happened in practice. -+ _as_can_reexec=no; export _as_can_reexec - # Don't try to exec as it changes $[0], causing all sort of problems - # (the dirname of $[0] is not the place where we might find the - # original and so on. Autoconf is especially sensitive to this). -@@ -481,16 +531,16 @@ if (echo >conf$$.file) 2>/dev/null; then - # ... but there are two gotchas: - # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail. - # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable. -- # In both cases, we have to default to `cp -p'. -+ # In both cases, we have to default to `cp -pR'. - ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe || -- as_ln_s='cp -p' -+ as_ln_s='cp -pR' - elif ln conf$$.file conf$$ 2>/dev/null; then - as_ln_s=ln - else -- as_ln_s='cp -p' -+ as_ln_s='cp -pR' - fi - else -- as_ln_s='cp -p' -+ as_ln_s='cp -pR' - fi - rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file - rmdir conf$$.dir 2>/dev/null -@@ -502,28 +552,8 @@ else - as_mkdir_p=false - fi - --if test -x / >/dev/null 2>&1; then -- as_test_x='test -x' --else -- if ls -dL / >/dev/null 2>&1; then -- as_ls_L_option=L -- else -- as_ls_L_option= -- fi -- as_test_x=' -- eval sh -c '\'' -- if test -d "$1"; then -- test -d "$1/."; -- else -- case $1 in #( -- -*)set "./$1";; -- esac; -- case `ls -ld'$as_ls_L_option' "$1" 2>/dev/null` in #(( -- ???[sx]*):;;*)false;;esac;fi -- '\'' sh -- ' --fi --as_executable_p=$as_test_x -+as_test_x='test -x' -+as_executable_p=as_fn_executable_p - - # Sed expression to map a string onto a valid CPP name. - as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'" -@@ -534,10 +564,11 @@ as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'" - SHELL=${CONFIG_SHELL-/bin/sh} - - --exec 7<&0 &1 -+test -n "$DJDIR" || exec 7<&0 &1 - - # Name of the host. --# hostname on some systems (SVR3.2, Linux) returns a bogus exit status, -+# hostname on some systems (SVR3.2, old GNU/Linux) returns a bogus exit status, - # so uname gets run too. - ac_hostname=`(hostname || uname -n) 2>/dev/null | sed 1q` - -@@ -676,9 +707,14 @@ use_sysroot - MAINT - MAINTAINER_MODE_FALSE - MAINTAINER_MODE_TRUE -+AM_BACKSLASH -+AM_DEFAULT_VERBOSITY -+AM_DEFAULT_V -+AM_V - am__fastdepCC_FALSE - am__fastdepCC_TRUE - CCDEPMODE -+am__nodep - AMDEPBACKSLASH - AMDEP_FALSE - AMDEP_TRUE -@@ -769,6 +805,7 @@ ac_subst_files='TDIRS' - ac_user_opts=' - enable_option_checking - enable_dependency_tracking -+enable_silent_rules - enable_maintainer_mode - with_lib_path - enable_targets -@@ -867,8 +904,9 @@ do - fi - - case $ac_option in -- *=*) ac_optarg=`expr "X$ac_option" : '[^=]*=\(.*\)'` ;; -- *) ac_optarg=yes ;; -+ *=?*) ac_optarg=`expr "X$ac_option" : '[^=]*=\(.*\)'` ;; -+ *=) ac_optarg= ;; -+ *) ac_optarg=yes ;; - esac - - # Accept the important Cygnus configure options, so we can diagnose typos. -@@ -913,7 +951,7 @@ do - ac_useropt=`expr "x$ac_option" : 'x-*disable-\(.*\)'` - # Reject names that are not valid shell variable names. - expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null && -- as_fn_error "invalid feature name: $ac_useropt" -+ as_fn_error $? "invalid feature name: $ac_useropt" - ac_useropt_orig=$ac_useropt - ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'` - case $ac_user_opts in -@@ -939,7 +977,7 @@ do - ac_useropt=`expr "x$ac_option" : 'x-*enable-\([^=]*\)'` - # Reject names that are not valid shell variable names. - expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null && -- as_fn_error "invalid feature name: $ac_useropt" -+ as_fn_error $? "invalid feature name: $ac_useropt" - ac_useropt_orig=$ac_useropt - ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'` - case $ac_user_opts in -@@ -1143,7 +1181,7 @@ do - ac_useropt=`expr "x$ac_option" : 'x-*with-\([^=]*\)'` - # Reject names that are not valid shell variable names. - expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null && -- as_fn_error "invalid package name: $ac_useropt" -+ as_fn_error $? "invalid package name: $ac_useropt" - ac_useropt_orig=$ac_useropt - ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'` - case $ac_user_opts in -@@ -1159,7 +1197,7 @@ do - ac_useropt=`expr "x$ac_option" : 'x-*without-\(.*\)'` - # Reject names that are not valid shell variable names. - expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null && -- as_fn_error "invalid package name: $ac_useropt" -+ as_fn_error $? "invalid package name: $ac_useropt" - ac_useropt_orig=$ac_useropt - ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'` - case $ac_user_opts in -@@ -1189,8 +1227,8 @@ do - | --x-librar=* | --x-libra=* | --x-libr=* | --x-lib=* | --x-li=* | --x-l=*) - x_libraries=$ac_optarg ;; - -- -*) as_fn_error "unrecognized option: \`$ac_option' --Try \`$0 --help' for more information." -+ -*) as_fn_error $? "unrecognized option: \`$ac_option' -+Try \`$0 --help' for more information" - ;; - - *=*) -@@ -1198,7 +1236,7 @@ Try \`$0 --help' for more information." - # Reject names that are not valid shell variable names. - case $ac_envvar in #( - '' | [0-9]* | *[!_$as_cr_alnum]* ) -- as_fn_error "invalid variable name: \`$ac_envvar'" ;; -+ as_fn_error $? "invalid variable name: \`$ac_envvar'" ;; - esac - eval $ac_envvar=\$ac_optarg - export $ac_envvar ;; -@@ -1208,7 +1246,7 @@ Try \`$0 --help' for more information." - $as_echo "$as_me: WARNING: you should use --build, --host, --target" >&2 - expr "x$ac_option" : ".*[^-._$as_cr_alnum]" >/dev/null && - $as_echo "$as_me: WARNING: invalid host type: $ac_option" >&2 -- : ${build_alias=$ac_option} ${host_alias=$ac_option} ${target_alias=$ac_option} -+ : "${build_alias=$ac_option} ${host_alias=$ac_option} ${target_alias=$ac_option}" - ;; - - esac -@@ -1216,13 +1254,13 @@ done - - if test -n "$ac_prev"; then - ac_option=--`echo $ac_prev | sed 's/_/-/g'` -- as_fn_error "missing argument to $ac_option" -+ as_fn_error $? "missing argument to $ac_option" - fi - - if test -n "$ac_unrecognized_opts"; then - case $enable_option_checking in - no) ;; -- fatal) as_fn_error "unrecognized options: $ac_unrecognized_opts" ;; -+ fatal) as_fn_error $? "unrecognized options: $ac_unrecognized_opts" ;; - *) $as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2 ;; - esac - fi -@@ -1245,7 +1283,7 @@ do - [\\/$]* | ?:[\\/]* ) continue;; - NONE | '' ) case $ac_var in *prefix ) continue;; esac;; - esac -- as_fn_error "expected an absolute directory name for --$ac_var: $ac_val" -+ as_fn_error $? "expected an absolute directory name for --$ac_var: $ac_val" - done - - # There might be people who depend on the old broken behavior: `$host' -@@ -1259,8 +1297,6 @@ target=$target_alias - if test "x$host_alias" != x; then - if test "x$build_alias" = x; then - cross_compiling=maybe -- $as_echo "$as_me: WARNING: If you wanted to set the --build type, don't use --host. -- If a cross compiler is detected then cross compile mode will be used." >&2 - elif test "x$build_alias" != "x$host_alias"; then - cross_compiling=yes - fi -@@ -1275,9 +1311,9 @@ test "$silent" = yes && exec 6>/dev/null - ac_pwd=`pwd` && test -n "$ac_pwd" && - ac_ls_di=`ls -di .` && - ac_pwd_ls_di=`cd "$ac_pwd" && ls -di .` || -- as_fn_error "working directory cannot be determined" -+ as_fn_error $? "working directory cannot be determined" - test "X$ac_ls_di" = "X$ac_pwd_ls_di" || -- as_fn_error "pwd does not report name of working directory" -+ as_fn_error $? "pwd does not report name of working directory" - - - # Find the source files, if location was not specified. -@@ -1316,11 +1352,11 @@ else - fi - if test ! -r "$srcdir/$ac_unique_file"; then - test "$ac_srcdir_defaulted" = yes && srcdir="$ac_confdir or .." -- as_fn_error "cannot find sources ($ac_unique_file) in $srcdir" -+ as_fn_error $? "cannot find sources ($ac_unique_file) in $srcdir" - fi - ac_msg="sources are in $srcdir, but \`cd $srcdir' does not work" - ac_abs_confdir=`( -- cd "$srcdir" && test -r "./$ac_unique_file" || as_fn_error "$ac_msg" -+ cd "$srcdir" && test -r "./$ac_unique_file" || as_fn_error $? "$ac_msg" - pwd)` - # When building in place, set srcdir=. - if test "$ac_abs_confdir" = "$ac_pwd"; then -@@ -1360,7 +1396,7 @@ Configuration: - --help=short display options specific to this package - --help=recursive display the short help of all the included packages - -V, --version display version information and exit -- -q, --quiet, --silent do not print \`checking...' messages -+ -q, --quiet, --silent do not print \`checking ...' messages - --cache-file=FILE cache test results in FILE [disabled] - -C, --config-cache alias for \`--cache-file=config.cache' - -n, --no-create do not create output files -@@ -1423,10 +1459,15 @@ Optional Features: - --disable-option-checking ignore unrecognized --enable/--with options - --disable-FEATURE do not include FEATURE (same as --enable-FEATURE=no) - --enable-FEATURE[=ARG] include FEATURE [ARG=yes] -- --disable-dependency-tracking speeds up one-time build -- --enable-dependency-tracking do not reject slow dependency extractors -- --enable-maintainer-mode enable make rules and dependencies not useful -- (and sometimes confusing) to the casual installer -+ --enable-dependency-tracking -+ do not reject slow dependency extractors -+ --disable-dependency-tracking -+ speeds up one-time build -+ --enable-silent-rules less verbose build output (undo: "make V=1") -+ --disable-silent-rules verbose build output (undo: "make V=0") -+ --enable-maintainer-mode -+ enable make rules and dependencies not useful (and -+ sometimes confusing) to the casual installer - --enable-targets alternative target configurations - --enable-64-bit-bfd 64-bit support (on hosts with narrower word sizes) - --enable-gold[=ARG] build gold [ARG={default,yes,no}] -@@ -1460,14 +1501,15 @@ Some influential environment variables: - LDFLAGS linker flags, e.g. -L if you have libraries in a - nonstandard directory - LIBS libraries to pass to the linker, e.g. -l -- CPPFLAGS C/C++/Objective C preprocessor flags, e.g. -I if -+ CPPFLAGS (Objective) C/C++ preprocessor flags, e.g. -I if - you have headers in a nonstandard directory - CPP C preprocessor - CXX C++ compiler command - CXXFLAGS C++ compiler flags - CXXCPP C++ preprocessor -- YACC The `Yet Another C Compiler' implementation to use. Defaults to -- the first program found out of: `bison -y', `byacc', `yacc'. -+ YACC The `Yet Another Compiler Compiler' implementation to use. -+ Defaults to the first program found out of: `bison -y', `byacc', -+ `yacc'. - YFLAGS The list of arguments that will be passed by default to $YACC. - This script will default YFLAGS to the empty string to avoid a - default value of `-d' given by some make applications. -@@ -1539,9 +1581,9 @@ test -n "$ac_init_help" && exit $ac_status - if $ac_init_version; then - cat <<\_ACEOF - configure --generated by GNU Autoconf 2.64 -+generated by GNU Autoconf 2.69 - --Copyright (C) 2009 Free Software Foundation, Inc. -+Copyright (C) 2012 Free Software Foundation, Inc. - This configure script is free software; the Free Software Foundation - gives unlimited permission to copy, distribute and modify it. - _ACEOF -@@ -1585,8 +1627,8 @@ sed 's/^/| /' conftest.$ac_ext >&5 - - ac_retval=1 - fi -- eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;} -- return $ac_retval -+ eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno -+ as_fn_set_status $ac_retval - - } # ac_fn_c_try_compile - -@@ -1617,7 +1659,7 @@ $as_echo "$ac_try_echo"; } >&5 - test ! -s conftest.err - } && test -s conftest$ac_exeext && { - test "$cross_compiling" = yes || -- $as_test_x conftest$ac_exeext -+ test -x conftest$ac_exeext - }; then : - ac_retval=0 - else -@@ -1631,8 +1673,8 @@ fi - # interfere with the next link command; also delete a directory that is - # left behind by Apple's compiler. We do this before executing the actions. - rm -rf conftest.dSYM conftest_ipa8_conftest.oo -- eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;} -- return $ac_retval -+ eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno -+ as_fn_set_status $ac_retval - - } # ac_fn_c_try_link - -@@ -1657,7 +1699,7 @@ $as_echo "$ac_try_echo"; } >&5 - mv -f conftest.er1 conftest.err - fi - $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 -- test $ac_status = 0; } >/dev/null && { -+ test $ac_status = 0; } > conftest.i && { - test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || - test ! -s conftest.err - }; then : -@@ -1668,8 +1710,8 @@ sed 's/^/| /' conftest.$ac_ext >&5 - - ac_retval=1 - fi -- eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;} -- return $ac_retval -+ eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno -+ as_fn_set_status $ac_retval - - } # ac_fn_c_try_cpp - -@@ -1706,8 +1748,8 @@ sed 's/^/| /' conftest.$ac_ext >&5 - - ac_retval=1 - fi -- eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;} -- return $ac_retval -+ eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno -+ as_fn_set_status $ac_retval - - } # ac_fn_cxx_try_compile - -@@ -1719,10 +1761,10 @@ fi - ac_fn_c_check_header_mongrel () - { - as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack -- if { as_var=$3; eval "test \"\${$as_var+set}\" = set"; }; then : -+ if eval \${$3+:} false; then : - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5 - $as_echo_n "checking for $2... " >&6; } --if { as_var=$3; eval "test \"\${$as_var+set}\" = set"; }; then : -+if eval \${$3+:} false; then : - $as_echo_n "(cached) " >&6 - fi - eval ac_res=\$$3 -@@ -1758,7 +1800,7 @@ if ac_fn_c_try_cpp "$LINENO"; then : - else - ac_header_preproc=no - fi --rm -f conftest.err conftest.$ac_ext -+rm -f conftest.err conftest.i conftest.$ac_ext - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_header_preproc" >&5 - $as_echo "$ac_header_preproc" >&6; } - -@@ -1785,7 +1827,7 @@ $as_echo "$as_me: WARNING: $2: proceeding with the compiler's result" >&2;} - esac - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5 - $as_echo_n "checking for $2... " >&6; } --if { as_var=$3; eval "test \"\${$as_var+set}\" = set"; }; then : -+if eval \${$3+:} false; then : - $as_echo_n "(cached) " >&6 - else - eval "$3=\$ac_header_compiler" -@@ -1794,7 +1836,7 @@ eval ac_res=\$$3 - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 - $as_echo "$ac_res" >&6; } - fi -- eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;} -+ eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno - - } # ac_fn_c_check_header_mongrel - -@@ -1835,8 +1877,8 @@ sed 's/^/| /' conftest.$ac_ext >&5 - ac_retval=$ac_status - fi - rm -rf conftest.dSYM conftest_ipa8_conftest.oo -- eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;} -- return $ac_retval -+ eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno -+ as_fn_set_status $ac_retval - - } # ac_fn_c_try_run - -@@ -1849,7 +1891,7 @@ ac_fn_c_check_header_compile () - as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5 - $as_echo_n "checking for $2... " >&6; } --if { as_var=$3; eval "test \"\${$as_var+set}\" = set"; }; then : -+if eval \${$3+:} false; then : - $as_echo_n "(cached) " >&6 - else - cat confdefs.h - <<_ACEOF >conftest.$ac_ext -@@ -1867,7 +1909,7 @@ fi - eval ac_res=\$$3 - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 - $as_echo "$ac_res" >&6; } -- eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;} -+ eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno - - } # ac_fn_c_check_header_compile - -@@ -1879,7 +1921,7 @@ ac_fn_c_check_func () - as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5 - $as_echo_n "checking for $2... " >&6; } --if { as_var=$3; eval "test \"\${$as_var+set}\" = set"; }; then : -+if eval \${$3+:} false; then : - $as_echo_n "(cached) " >&6 - else - cat confdefs.h - <<_ACEOF >conftest.$ac_ext -@@ -1934,7 +1976,7 @@ fi - eval ac_res=\$$3 - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 - $as_echo "$ac_res" >&6; } -- eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;} -+ eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno - - } # ac_fn_c_check_func - -@@ -1959,7 +2001,7 @@ $as_echo "$ac_try_echo"; } >&5 - mv -f conftest.er1 conftest.err - fi - $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 -- test $ac_status = 0; } >/dev/null && { -+ test $ac_status = 0; } > conftest.i && { - test -z "$ac_cxx_preproc_warn_flag$ac_cxx_werror_flag" || - test ! -s conftest.err - }; then : -@@ -1970,8 +2012,8 @@ sed 's/^/| /' conftest.$ac_ext >&5 - - ac_retval=1 - fi -- eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;} -- return $ac_retval -+ eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno -+ as_fn_set_status $ac_retval - - } # ac_fn_cxx_try_cpp - -@@ -2002,7 +2044,7 @@ $as_echo "$ac_try_echo"; } >&5 - test ! -s conftest.err - } && test -s conftest$ac_exeext && { - test "$cross_compiling" = yes || -- $as_test_x conftest$ac_exeext -+ test -x conftest$ac_exeext - }; then : - ac_retval=0 - else -@@ -2016,14 +2058,15 @@ fi - # interfere with the next link command; also delete a directory that is - # left behind by Apple's compiler. We do this before executing the actions. - rm -rf conftest.dSYM conftest_ipa8_conftest.oo -- eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;} -- return $ac_retval -+ eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno -+ as_fn_set_status $ac_retval - - } # ac_fn_cxx_try_link - --# ac_fn_c_check_decl LINENO SYMBOL VAR --# ------------------------------------ --# Tests whether SYMBOL is declared, setting cache variable VAR accordingly. -+# ac_fn_c_check_decl LINENO SYMBOL VAR INCLUDES -+# --------------------------------------------- -+# Tests whether SYMBOL is declared in INCLUDES, setting cache variable VAR -+# accordingly. - ac_fn_c_check_decl () - { - as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack -@@ -2031,7 +2074,7 @@ ac_fn_c_check_decl () - as_decl_use=`echo $2|sed -e 's/(/((/' -e 's/)/) 0&/' -e 's/,/) 0& (/g'` - { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $as_decl_name is declared" >&5 - $as_echo_n "checking whether $as_decl_name is declared... " >&6; } --if { as_var=$3; eval "test \"\${$as_var+set}\" = set"; }; then : -+if eval \${$3+:} false; then : - $as_echo_n "(cached) " >&6 - else - cat confdefs.h - <<_ACEOF >conftest.$ac_ext -@@ -2062,7 +2105,7 @@ fi - eval ac_res=\$$3 - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 - $as_echo "$ac_res" >&6; } -- eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;} -+ eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno - - } # ac_fn_c_check_decl - -@@ -2083,7 +2126,8 @@ int - main () - { - static int test_array [1 - 2 * !(($2) >= 0)]; --test_array [0] = 0 -+test_array [0] = 0; -+return test_array [0]; - - ; - return 0; -@@ -2099,7 +2143,8 @@ int - main () - { - static int test_array [1 - 2 * !(($2) <= $ac_mid)]; --test_array [0] = 0 -+test_array [0] = 0; -+return test_array [0]; - - ; - return 0; -@@ -2125,7 +2170,8 @@ int - main () - { - static int test_array [1 - 2 * !(($2) < 0)]; --test_array [0] = 0 -+test_array [0] = 0; -+return test_array [0]; - - ; - return 0; -@@ -2141,7 +2187,8 @@ int - main () - { - static int test_array [1 - 2 * !(($2) >= $ac_mid)]; --test_array [0] = 0 -+test_array [0] = 0; -+return test_array [0]; - - ; - return 0; -@@ -2175,7 +2222,8 @@ int - main () - { - static int test_array [1 - 2 * !(($2) <= $ac_mid)]; --test_array [0] = 0 -+test_array [0] = 0; -+return test_array [0]; - - ; - return 0; -@@ -2239,8 +2287,8 @@ rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ - rm -f conftest.val - - fi -- eval $as_lineno_stack; test "x$as_lineno_stack" = x && { as_lineno=; unset as_lineno;} -- return $ac_retval -+ eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno -+ as_fn_set_status $ac_retval - - } # ac_fn_c_compute_int - cat >config.log <<_ACEOF -@@ -2248,7 +2296,7 @@ This file contains any messages produced by compilers while - running configure, to aid debugging if configure makes a mistake. - - It was created by $as_me, which was --generated by GNU Autoconf 2.64. Invocation command line was -+generated by GNU Autoconf 2.69. Invocation command line was - - $ $0 $@ - -@@ -2358,11 +2406,9 @@ trap 'exit_status=$? - { - echo - -- cat <<\_ASBOX --## ---------------- ## -+ $as_echo "## ---------------- ## - ## Cache variables. ## --## ---------------- ## --_ASBOX -+## ---------------- ##" - echo - # The following way of writing the cache mishandles newlines in values, - ( -@@ -2396,11 +2442,9 @@ $as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; - ) - echo - -- cat <<\_ASBOX --## ----------------- ## -+ $as_echo "## ----------------- ## - ## Output variables. ## --## ----------------- ## --_ASBOX -+## ----------------- ##" - echo - for ac_var in $ac_subst_vars - do -@@ -2413,11 +2457,9 @@ _ASBOX - echo - - if test -n "$ac_subst_files"; then -- cat <<\_ASBOX --## ------------------- ## -+ $as_echo "## ------------------- ## - ## File substitutions. ## --## ------------------- ## --_ASBOX -+## ------------------- ##" - echo - for ac_var in $ac_subst_files - do -@@ -2431,11 +2473,9 @@ _ASBOX - fi - - if test -s confdefs.h; then -- cat <<\_ASBOX --## ----------- ## -+ $as_echo "## ----------- ## - ## confdefs.h. ## --## ----------- ## --_ASBOX -+## ----------- ##" - echo - cat confdefs.h - echo -@@ -2490,7 +2530,12 @@ _ACEOF - ac_site_file1=NONE - ac_site_file2=NONE - if test -n "$CONFIG_SITE"; then -- ac_site_file1=$CONFIG_SITE -+ # We do not want a PATH search for config.site. -+ case $CONFIG_SITE in #(( -+ -*) ac_site_file1=./$CONFIG_SITE;; -+ */*) ac_site_file1=$CONFIG_SITE;; -+ *) ac_site_file1=./$CONFIG_SITE;; -+ esac - elif test "x$prefix" != xNONE; then - ac_site_file1=$prefix/share/config.site - ac_site_file2=$prefix/etc/config.site -@@ -2501,18 +2546,22 @@ fi - for ac_site_file in "$ac_site_file1" "$ac_site_file2" - do - test "x$ac_site_file" = xNONE && continue -- if test -r "$ac_site_file"; then -+ if test /dev/null != "$ac_site_file" && test -r "$ac_site_file"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: loading site script $ac_site_file" >&5 - $as_echo "$as_me: loading site script $ac_site_file" >&6;} - sed 's/^/| /' "$ac_site_file" >&5 -- . "$ac_site_file" -+ . "$ac_site_file" \ -+ || { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 -+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} -+as_fn_error $? "failed to load site script $ac_site_file -+See \`config.log' for more details" "$LINENO" 5; } - fi - done - - if test -r "$cache_file"; then -- # Some versions of bash will fail to source /dev/null (special -- # files actually), so we avoid doing that. -- if test -f "$cache_file"; then -+ # Some versions of bash will fail to source /dev/null (special files -+ # actually), so we avoid doing that. DJGPP emulates it as a regular file. -+ if test /dev/null != "$cache_file" && test -f "$cache_file"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: loading cache $cache_file" >&5 - $as_echo "$as_me: loading cache $cache_file" >&6;} - case $cache_file in -@@ -2581,7 +2630,7 @@ if $ac_cache_corrupted; then - $as_echo "$as_me: error: in \`$ac_pwd':" >&2;} - { $as_echo "$as_me:${as_lineno-$LINENO}: error: changes in the environment can compromise the build" >&5 - $as_echo "$as_me: error: changes in the environment can compromise the build" >&2;} -- as_fn_error "run \`make distclean' and/or \`rm $cache_file' and start over" "$LINENO" 5 -+ as_fn_error $? "run \`make distclean' and/or \`rm $cache_file' and start over" "$LINENO" 5 - fi - ## -------------------- ## - ## Main body of script. ## -@@ -2601,16 +2650,22 @@ ac_compiler_gnu=$ac_cv_c_compiler_gnu - - ac_aux_dir= - for ac_dir in "$srcdir" "$srcdir/.." "$srcdir/../.."; do -- for ac_t in install-sh install.sh shtool; do -- if test -f "$ac_dir/$ac_t"; then -- ac_aux_dir=$ac_dir -- ac_install_sh="$ac_aux_dir/$ac_t -c" -- break 2 -- fi -- done -+ if test -f "$ac_dir/install-sh"; then -+ ac_aux_dir=$ac_dir -+ ac_install_sh="$ac_aux_dir/install-sh -c" -+ break -+ elif test -f "$ac_dir/install.sh"; then -+ ac_aux_dir=$ac_dir -+ ac_install_sh="$ac_aux_dir/install.sh -c" -+ break -+ elif test -f "$ac_dir/shtool"; then -+ ac_aux_dir=$ac_dir -+ ac_install_sh="$ac_aux_dir/shtool install -c" -+ break -+ fi - done - if test -z "$ac_aux_dir"; then -- as_fn_error "cannot find install-sh, install.sh, or shtool in \"$srcdir\" \"$srcdir/..\" \"$srcdir/../..\"" "$LINENO" 5 -+ as_fn_error $? "cannot find install-sh, install.sh, or shtool in \"$srcdir\" \"$srcdir/..\" \"$srcdir/../..\"" "$LINENO" 5 - fi - - # These three variables are undocumented and unsupported, -@@ -2624,27 +2679,27 @@ ac_configure="$SHELL $ac_aux_dir/configure" # Please don't use this var. - - # Make sure we can run config.sub. - $SHELL "$ac_aux_dir/config.sub" sun4 >/dev/null 2>&1 || -- as_fn_error "cannot run $SHELL $ac_aux_dir/config.sub" "$LINENO" 5 -+ as_fn_error $? "cannot run $SHELL $ac_aux_dir/config.sub" "$LINENO" 5 - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking build system type" >&5 - $as_echo_n "checking build system type... " >&6; } --if test "${ac_cv_build+set}" = set; then : -+if ${ac_cv_build+:} false; then : - $as_echo_n "(cached) " >&6 - else - ac_build_alias=$build_alias - test "x$ac_build_alias" = x && - ac_build_alias=`$SHELL "$ac_aux_dir/config.guess"` - test "x$ac_build_alias" = x && -- as_fn_error "cannot guess build type; you must specify one" "$LINENO" 5 -+ as_fn_error $? "cannot guess build type; you must specify one" "$LINENO" 5 - ac_cv_build=`$SHELL "$ac_aux_dir/config.sub" $ac_build_alias` || -- as_fn_error "$SHELL $ac_aux_dir/config.sub $ac_build_alias failed" "$LINENO" 5 -+ as_fn_error $? "$SHELL $ac_aux_dir/config.sub $ac_build_alias failed" "$LINENO" 5 - - fi - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_build" >&5 - $as_echo "$ac_cv_build" >&6; } - case $ac_cv_build in - *-*-*) ;; --*) as_fn_error "invalid value of canonical build" "$LINENO" 5;; -+*) as_fn_error $? "invalid value of canonical build" "$LINENO" 5;; - esac - build=$ac_cv_build - ac_save_IFS=$IFS; IFS='-' -@@ -2662,14 +2717,14 @@ case $build_os in *\ *) build_os=`echo "$build_os" | sed 's/ /-/g'`;; esac - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking host system type" >&5 - $as_echo_n "checking host system type... " >&6; } --if test "${ac_cv_host+set}" = set; then : -+if ${ac_cv_host+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test "x$host_alias" = x; then - ac_cv_host=$ac_cv_build - else - ac_cv_host=`$SHELL "$ac_aux_dir/config.sub" $host_alias` || -- as_fn_error "$SHELL $ac_aux_dir/config.sub $host_alias failed" "$LINENO" 5 -+ as_fn_error $? "$SHELL $ac_aux_dir/config.sub $host_alias failed" "$LINENO" 5 - fi - - fi -@@ -2677,7 +2732,7 @@ fi - $as_echo "$ac_cv_host" >&6; } - case $ac_cv_host in - *-*-*) ;; --*) as_fn_error "invalid value of canonical host" "$LINENO" 5;; -+*) as_fn_error $? "invalid value of canonical host" "$LINENO" 5;; - esac - host=$ac_cv_host - ac_save_IFS=$IFS; IFS='-' -@@ -2695,14 +2750,14 @@ case $host_os in *\ *) host_os=`echo "$host_os" | sed 's/ /-/g'`;; esac - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking target system type" >&5 - $as_echo_n "checking target system type... " >&6; } --if test "${ac_cv_target+set}" = set; then : -+if ${ac_cv_target+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test "x$target_alias" = x; then - ac_cv_target=$ac_cv_host - else - ac_cv_target=`$SHELL "$ac_aux_dir/config.sub" $target_alias` || -- as_fn_error "$SHELL $ac_aux_dir/config.sub $target_alias failed" "$LINENO" 5 -+ as_fn_error $? "$SHELL $ac_aux_dir/config.sub $target_alias failed" "$LINENO" 5 - fi - - fi -@@ -2710,7 +2765,7 @@ fi - $as_echo "$ac_cv_target" >&6; } - case $ac_cv_target in - *-*-*) ;; --*) as_fn_error "invalid value of canonical target" "$LINENO" 5;; -+*) as_fn_error $? "invalid value of canonical target" "$LINENO" 5;; - esac - target=$ac_cv_target - ac_save_IFS=$IFS; IFS='-' -@@ -2733,6 +2788,9 @@ test -n "$target_alias" && - NONENONEs,x,x, && - program_prefix=${target_alias}- - -+# expand $ac_aux_dir to an absolute path -+am_aux_dir=`cd $ac_aux_dir && pwd` -+ - ac_ext=c - ac_cpp='$CPP $CPPFLAGS' - ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' -@@ -2743,7 +2801,7 @@ if test -n "$ac_tool_prefix"; then - set dummy ${ac_tool_prefix}gcc; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_CC+set}" = set; then : -+if ${ac_cv_prog_CC+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$CC"; then -@@ -2755,7 +2813,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_CC="${ac_tool_prefix}gcc" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -2783,7 +2841,7 @@ if test -z "$ac_cv_prog_CC"; then - set dummy gcc; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_ac_ct_CC+set}" = set; then : -+if ${ac_cv_prog_ac_ct_CC+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$ac_ct_CC"; then -@@ -2795,7 +2853,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_ac_ct_CC="gcc" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -2836,7 +2894,7 @@ if test -z "$CC"; then - set dummy ${ac_tool_prefix}cc; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_CC+set}" = set; then : -+if ${ac_cv_prog_CC+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$CC"; then -@@ -2848,7 +2906,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_CC="${ac_tool_prefix}cc" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -2876,7 +2934,7 @@ if test -z "$CC"; then - set dummy cc; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_CC+set}" = set; then : -+if ${ac_cv_prog_CC+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$CC"; then -@@ -2889,7 +2947,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then - ac_prog_rejected=yes - continue -@@ -2935,7 +2993,7 @@ if test -z "$CC"; then - set dummy $ac_tool_prefix$ac_prog; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_CC+set}" = set; then : -+if ${ac_cv_prog_CC+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$CC"; then -@@ -2947,7 +3005,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_CC="$ac_tool_prefix$ac_prog" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -2979,7 +3037,7 @@ do - set dummy $ac_prog; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_ac_ct_CC+set}" = set; then : -+if ${ac_cv_prog_ac_ct_CC+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$ac_ct_CC"; then -@@ -2991,7 +3049,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_ac_ct_CC="$ac_prog" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -3033,8 +3091,8 @@ fi - - test -z "$CC" && { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 - $as_echo "$as_me: error: in \`$ac_pwd':" >&2;} --as_fn_error "no acceptable C compiler found in \$PATH --See \`config.log' for more details." "$LINENO" 5; } -+as_fn_error $? "no acceptable C compiler found in \$PATH -+See \`config.log' for more details" "$LINENO" 5; } - - # Provide some information about the compiler. - $as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler version" >&5 -@@ -3055,8 +3113,8 @@ $as_echo "$ac_try_echo"; } >&5 - ... rest of stderr output deleted ... - 10q' conftest.err >conftest.er1 - cat conftest.er1 >&5 -- rm -f conftest.er1 conftest.err - fi -+ rm -f conftest.er1 conftest.err - $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 - test $ac_status = 0; } - done -@@ -3073,12 +3131,12 @@ main () - } - _ACEOF - ac_clean_files_save=$ac_clean_files --ac_clean_files="$ac_clean_files a.out a.out.dSYM a.exe b.out conftest.out" -+ac_clean_files="$ac_clean_files a.out a.out.dSYM a.exe b.out" - # Try to create an executable without -o first, disregard a.out. - # It will help us diagnose broken compilers, and finding out an intuition - # of exeext. --{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler default output file name" >&5 --$as_echo_n "checking for C compiler default output file name... " >&6; } -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the C compiler works" >&5 -+$as_echo_n "checking whether the C compiler works... " >&6; } - ac_link_default=`$as_echo "$ac_link" | sed 's/ -o *conftest[^ ]*//'` - - # The possible output files: -@@ -3140,62 +3198,28 @@ test "$ac_cv_exeext" = no && ac_cv_exeext= - else - ac_file='' - fi --{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_file" >&5 --$as_echo "$ac_file" >&6; } - if test -z "$ac_file"; then : -- $as_echo "$as_me: failed program was:" >&5 -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 -+$as_echo "no" >&6; } -+$as_echo "$as_me: failed program was:" >&5 - sed 's/^/| /' conftest.$ac_ext >&5 - - { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 - $as_echo "$as_me: error: in \`$ac_pwd':" >&2;} --{ as_fn_set_status 77 --as_fn_error "C compiler cannot create executables --See \`config.log' for more details." "$LINENO" 5; }; } -+as_fn_error 77 "C compiler cannot create executables -+See \`config.log' for more details" "$LINENO" 5; } -+else -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 -+$as_echo "yes" >&6; } - fi -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler default output file name" >&5 -+$as_echo_n "checking for C compiler default output file name... " >&6; } -+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_file" >&5 -+$as_echo "$ac_file" >&6; } - ac_exeext=$ac_cv_exeext - --# Check that the compiler produces executables we can run. If not, either --# the compiler is broken, or we cross compile. --{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the C compiler works" >&5 --$as_echo_n "checking whether the C compiler works... " >&6; } --# If not cross compiling, check that we can run a simple program. --if test "$cross_compiling" != yes; then -- if { ac_try='./$ac_file' -- { { case "(($ac_try" in -- *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; -- *) ac_try_echo=$ac_try;; --esac --eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" --$as_echo "$ac_try_echo"; } >&5 -- (eval "$ac_try") 2>&5 -- ac_status=$? -- $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 -- test $ac_status = 0; }; }; then -- cross_compiling=no -- else -- if test "$cross_compiling" = maybe; then -- cross_compiling=yes -- else -- { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 --$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} --as_fn_error "cannot run C compiled programs. --If you meant to cross compile, use \`--host'. --See \`config.log' for more details." "$LINENO" 5; } -- fi -- fi --fi --{ $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 --$as_echo "yes" >&6; } -- --rm -f -r a.out a.out.dSYM a.exe conftest$ac_cv_exeext b.out conftest.out -+rm -f -r a.out a.out.dSYM a.exe conftest$ac_cv_exeext b.out - ac_clean_files=$ac_clean_files_save --# Check that the compiler produces executables we can run. If not, either --# the compiler is broken, or we cross compile. --{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are cross compiling" >&5 --$as_echo_n "checking whether we are cross compiling... " >&6; } --{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $cross_compiling" >&5 --$as_echo "$cross_compiling" >&6; } -- - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of executables" >&5 - $as_echo_n "checking for suffix of executables... " >&6; } - if { { ac_try="$ac_link" -@@ -3225,19 +3249,78 @@ done - else - { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 - $as_echo "$as_me: error: in \`$ac_pwd':" >&2;} --as_fn_error "cannot compute suffix of executables: cannot compile and link --See \`config.log' for more details." "$LINENO" 5; } -+as_fn_error $? "cannot compute suffix of executables: cannot compile and link -+See \`config.log' for more details" "$LINENO" 5; } - fi --rm -f conftest$ac_cv_exeext -+rm -f conftest conftest$ac_cv_exeext - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_exeext" >&5 - $as_echo "$ac_cv_exeext" >&6; } - - rm -f conftest.$ac_ext - EXEEXT=$ac_cv_exeext - ac_exeext=$EXEEXT -+cat confdefs.h - <<_ACEOF >conftest.$ac_ext -+/* end confdefs.h. */ -+#include -+int -+main () -+{ -+FILE *f = fopen ("conftest.out", "w"); -+ return ferror (f) || fclose (f) != 0; -+ -+ ; -+ return 0; -+} -+_ACEOF -+ac_clean_files="$ac_clean_files conftest.out" -+# Check that the compiler produces executables we can run. If not, either -+# the compiler is broken, or we cross compile. -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are cross compiling" >&5 -+$as_echo_n "checking whether we are cross compiling... " >&6; } -+if test "$cross_compiling" != yes; then -+ { { ac_try="$ac_link" -+case "(($ac_try" in -+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; -+ *) ac_try_echo=$ac_try;; -+esac -+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" -+$as_echo "$ac_try_echo"; } >&5 -+ (eval "$ac_link") 2>&5 -+ ac_status=$? -+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 -+ test $ac_status = 0; } -+ if { ac_try='./conftest$ac_cv_exeext' -+ { { case "(($ac_try" in -+ *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; -+ *) ac_try_echo=$ac_try;; -+esac -+eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" -+$as_echo "$ac_try_echo"; } >&5 -+ (eval "$ac_try") 2>&5 -+ ac_status=$? -+ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 -+ test $ac_status = 0; }; }; then -+ cross_compiling=no -+ else -+ if test "$cross_compiling" = maybe; then -+ cross_compiling=yes -+ else -+ { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 -+$as_echo "$as_me: error: in \`$ac_pwd':" >&2;} -+as_fn_error $? "cannot run C compiled programs. -+If you meant to cross compile, use \`--host'. -+See \`config.log' for more details" "$LINENO" 5; } -+ fi -+ fi -+fi -+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $cross_compiling" >&5 -+$as_echo "$cross_compiling" >&6; } -+ -+rm -f conftest.$ac_ext conftest$ac_cv_exeext conftest.out -+ac_clean_files=$ac_clean_files_save - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of object files" >&5 - $as_echo_n "checking for suffix of object files... " >&6; } --if test "${ac_cv_objext+set}" = set; then : -+if ${ac_cv_objext+:} false; then : - $as_echo_n "(cached) " >&6 - else - cat confdefs.h - <<_ACEOF >conftest.$ac_ext -@@ -3277,8 +3360,8 @@ sed 's/^/| /' conftest.$ac_ext >&5 - - { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 - $as_echo "$as_me: error: in \`$ac_pwd':" >&2;} --as_fn_error "cannot compute suffix of object files: cannot compile --See \`config.log' for more details." "$LINENO" 5; } -+as_fn_error $? "cannot compute suffix of object files: cannot compile -+See \`config.log' for more details" "$LINENO" 5; } - fi - rm -f conftest.$ac_cv_objext conftest.$ac_ext - fi -@@ -3288,7 +3371,7 @@ OBJEXT=$ac_cv_objext - ac_objext=$OBJEXT - { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using the GNU C compiler" >&5 - $as_echo_n "checking whether we are using the GNU C compiler... " >&6; } --if test "${ac_cv_c_compiler_gnu+set}" = set; then : -+if ${ac_cv_c_compiler_gnu+:} false; then : - $as_echo_n "(cached) " >&6 - else - cat confdefs.h - <<_ACEOF >conftest.$ac_ext -@@ -3325,7 +3408,7 @@ ac_test_CFLAGS=${CFLAGS+set} - ac_save_CFLAGS=$CFLAGS - { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC accepts -g" >&5 - $as_echo_n "checking whether $CC accepts -g... " >&6; } --if test "${ac_cv_prog_cc_g+set}" = set; then : -+if ${ac_cv_prog_cc_g+:} false; then : - $as_echo_n "(cached) " >&6 - else - ac_save_c_werror_flag=$ac_c_werror_flag -@@ -3403,7 +3486,7 @@ else - fi - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $CC option to accept ISO C89" >&5 - $as_echo_n "checking for $CC option to accept ISO C89... " >&6; } --if test "${ac_cv_prog_cc_c89+set}" = set; then : -+if ${ac_cv_prog_cc_c89+:} false; then : - $as_echo_n "(cached) " >&6 - else - ac_cv_prog_cc_c89=no -@@ -3412,8 +3495,7 @@ cat confdefs.h - <<_ACEOF >conftest.$ac_ext - /* end confdefs.h. */ - #include - #include --#include --#include -+struct stat; - /* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */ - struct buf { int x; }; - FILE * (*rcsopen) (struct buf *, struct stat *, int); -@@ -3498,10 +3580,69 @@ ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' - ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' - ac_compiler_gnu=$ac_cv_c_compiler_gnu - -+ac_ext=c -+ac_cpp='$CPP $CPPFLAGS' -+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' -+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' -+ac_compiler_gnu=$ac_cv_c_compiler_gnu -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC understands -c and -o together" >&5 -+$as_echo_n "checking whether $CC understands -c and -o together... " >&6; } -+if ${am_cv_prog_cc_c_o+:} false; then : -+ $as_echo_n "(cached) " >&6 -+else -+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext -+/* end confdefs.h. */ -+ -+int -+main () -+{ -+ -+ ; -+ return 0; -+} -+_ACEOF -+ # Make sure it works both with $CC and with simple cc. -+ # Following AC_PROG_CC_C_O, we do the test twice because some -+ # compilers refuse to overwrite an existing .o file with -o, -+ # though they will create one. -+ am_cv_prog_cc_c_o=yes -+ for am_i in 1 2; do -+ if { echo "$as_me:$LINENO: $CC -c conftest.$ac_ext -o conftest2.$ac_objext" >&5 -+ ($CC -c conftest.$ac_ext -o conftest2.$ac_objext) >&5 2>&5 -+ ac_status=$? -+ echo "$as_me:$LINENO: \$? = $ac_status" >&5 -+ (exit $ac_status); } \ -+ && test -f conftest2.$ac_objext; then -+ : OK -+ else -+ am_cv_prog_cc_c_o=no -+ break -+ fi -+ done -+ rm -f core conftest* -+ unset am_i -+fi -+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $am_cv_prog_cc_c_o" >&5 -+$as_echo "$am_cv_prog_cc_c_o" >&6; } -+if test "$am_cv_prog_cc_c_o" != yes; then -+ # Losing compiler, so override with the script. -+ # FIXME: It is wrong to rewrite CC. -+ # But if we don't then we get into trouble of one sort or another. -+ # A longer-term fix would be to have automake use am__CC in this case, -+ # and then we could set am__CC="\$(top_srcdir)/compile \$(CC)" -+ CC="$am_aux_dir/compile $CC" -+fi -+ac_ext=c -+ac_cpp='$CPP $CPPFLAGS' -+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' -+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' -+ac_compiler_gnu=$ac_cv_c_compiler_gnu -+ -+ - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for library containing strerror" >&5 - $as_echo_n "checking for library containing strerror... " >&6; } --if test "${ac_cv_search_strerror+set}" = set; then : -+if ${ac_cv_search_strerror+:} false; then : - $as_echo_n "(cached) " >&6 - else - ac_func_search_save_LIBS=$LIBS -@@ -3535,11 +3676,11 @@ for ac_lib in '' cposix; do - fi - rm -f core conftest.err conftest.$ac_objext \ - conftest$ac_exeext -- if test "${ac_cv_search_strerror+set}" = set; then : -+ if ${ac_cv_search_strerror+:} false; then : - break - fi - done --if test "${ac_cv_search_strerror+set}" = set; then : -+if ${ac_cv_search_strerror+:} false; then : - - else - ac_cv_search_strerror=no -@@ -3576,7 +3717,7 @@ am__api_version='1.11' - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for a BSD-compatible install" >&5 - $as_echo_n "checking for a BSD-compatible install... " >&6; } - if test -z "$INSTALL"; then --if test "${ac_cv_path_install+set}" = set; then : -+if ${ac_cv_path_install+:} false; then : - $as_echo_n "(cached) " >&6 - else - as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -@@ -3596,7 +3737,7 @@ case $as_dir/ in #(( - # by default. - for ac_prog in ginstall scoinst install; do - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_prog$ac_exec_ext" && $as_test_x "$as_dir/$ac_prog$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_prog$ac_exec_ext"; then - if test $ac_prog = install && - grep dspmsg "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then - # AIX install. It has an incompatible calling convention. -@@ -3654,56 +3795,71 @@ test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether build environment is sane" >&5 - $as_echo_n "checking whether build environment is sane... " >&6; } --# Just in case --sleep 1 --echo timestamp > conftest.file - # Reject unsafe characters in $srcdir or the absolute working directory - # name. Accept space and tab only in the latter. - am_lf=' - ' - case `pwd` in - *[\\\"\#\$\&\'\`$am_lf]*) -- as_fn_error "unsafe absolute working directory name" "$LINENO" 5;; -+ as_fn_error $? "unsafe absolute working directory name" "$LINENO" 5;; - esac - case $srcdir in - *[\\\"\#\$\&\'\`$am_lf\ \ ]*) -- as_fn_error "unsafe srcdir value: \`$srcdir'" "$LINENO" 5;; -+ as_fn_error $? "unsafe srcdir value: '$srcdir'" "$LINENO" 5;; - esac - --# Do `set' in a subshell so we don't clobber the current shell's -+# Do 'set' in a subshell so we don't clobber the current shell's - # arguments. Must try -L first in case configure is actually a - # symlink; some systems play weird games with the mod time of symlinks - # (eg FreeBSD returns the mod time of the symlink's containing - # directory). - if ( -- set X `ls -Lt "$srcdir/configure" conftest.file 2> /dev/null` -- if test "$*" = "X"; then -- # -L didn't work. -- set X `ls -t "$srcdir/configure" conftest.file` -- fi -- rm -f conftest.file -- if test "$*" != "X $srcdir/configure conftest.file" \ -- && test "$*" != "X conftest.file $srcdir/configure"; then -- -- # If neither matched, then we have a broken ls. This can happen -- # if, for instance, CONFIG_SHELL is bash and it inherits a -- # broken ls alias from the environment. This has actually -- # happened. Such a system could not be considered "sane". -- as_fn_error "ls -t appears to fail. Make sure there is not a broken --alias in your environment" "$LINENO" 5 -- fi -- -+ am_has_slept=no -+ for am_try in 1 2; do -+ echo "timestamp, slept: $am_has_slept" > conftest.file -+ set X `ls -Lt "$srcdir/configure" conftest.file 2> /dev/null` -+ if test "$*" = "X"; then -+ # -L didn't work. -+ set X `ls -t "$srcdir/configure" conftest.file` -+ fi -+ if test "$*" != "X $srcdir/configure conftest.file" \ -+ && test "$*" != "X conftest.file $srcdir/configure"; then -+ -+ # If neither matched, then we have a broken ls. This can happen -+ # if, for instance, CONFIG_SHELL is bash and it inherits a -+ # broken ls alias from the environment. This has actually -+ # happened. Such a system could not be considered "sane". -+ as_fn_error $? "ls -t appears to fail. Make sure there is not a broken -+ alias in your environment" "$LINENO" 5 -+ fi -+ if test "$2" = conftest.file || test $am_try -eq 2; then -+ break -+ fi -+ # Just in case. -+ sleep 1 -+ am_has_slept=yes -+ done - test "$2" = conftest.file - ) - then - # Ok. - : - else -- as_fn_error "newly created file is older than distributed files! -+ as_fn_error $? "newly created file is older than distributed files! - Check your system clock" "$LINENO" 5 - fi - { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 - $as_echo "yes" >&6; } -+# If we didn't sleep, we still need to ensure time stamps of config.status and -+# generated files are strictly newer. -+am_sleep_pid= -+if grep 'slept: no' conftest.file >/dev/null 2>&1; then -+ ( sleep 1 ) & -+ am_sleep_pid=$! -+fi -+ -+rm -f conftest.file -+ - test "$program_prefix" != NONE && - program_transform_name="s&^&$program_prefix&;$program_transform_name" - # Use a double $ so make ignores it. -@@ -3714,9 +3870,6 @@ test "$program_suffix" != NONE && - ac_script='s/[\\$]/&&/g;s/;s,x,x,$//' - program_transform_name=`$as_echo "$program_transform_name" | sed "$ac_script"` - --# expand $ac_aux_dir to an absolute path --am_aux_dir=`cd $ac_aux_dir && pwd` -- - if test x"${MISSING+set}" != xset; then - case $am_aux_dir in - *\ * | *\ *) -@@ -3726,12 +3879,12 @@ if test x"${MISSING+set}" != xset; then - esac - fi - # Use eval to expand $SHELL --if eval "$MISSING --run true"; then -- am_missing_run="$MISSING --run " -+if eval "$MISSING --is-lightweight"; then -+ am_missing_run="$MISSING " - else - am_missing_run= -- { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: \`missing' script is too old or missing" >&5 --$as_echo "$as_me: WARNING: \`missing' script is too old or missing" >&2;} -+ { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: 'missing' script is too old or missing" >&5 -+$as_echo "$as_me: WARNING: 'missing' script is too old or missing" >&2;} - fi - - if test x"${install_sh}" != xset; then -@@ -3743,17 +3896,17 @@ if test x"${install_sh}" != xset; then - esac - fi - --# Installed binaries are usually stripped using `strip' when the user --# run `make install-strip'. However `strip' might not be the right -+# Installed binaries are usually stripped using 'strip' when the user -+# run "make install-strip". However 'strip' might not be the right - # tool to use in cross-compilation environments, therefore Automake --# will honor the `STRIP' environment variable to overrule this program. -+# will honor the 'STRIP' environment variable to overrule this program. - if test "$cross_compiling" != no; then - if test -n "$ac_tool_prefix"; then - # Extract the first word of "${ac_tool_prefix}strip", so it can be a program name with args. - set dummy ${ac_tool_prefix}strip; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_STRIP+set}" = set; then : -+if ${ac_cv_prog_STRIP+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$STRIP"; then -@@ -3765,7 +3918,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_STRIP="${ac_tool_prefix}strip" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -3793,7 +3946,7 @@ if test -z "$ac_cv_prog_STRIP"; then - set dummy strip; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_ac_ct_STRIP+set}" = set; then : -+if ${ac_cv_prog_ac_ct_STRIP+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$ac_ct_STRIP"; then -@@ -3805,7 +3958,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_ac_ct_STRIP="strip" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -3846,7 +3999,7 @@ INSTALL_STRIP_PROGRAM="\$(install_sh) -c -s" - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for a thread-safe mkdir -p" >&5 - $as_echo_n "checking for a thread-safe mkdir -p... " >&6; } - if test -z "$MKDIR_P"; then -- if test "${ac_cv_path_mkdir+set}" = set; then : -+ if ${ac_cv_path_mkdir+:} false; then : - $as_echo_n "(cached) " >&6 - else - as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -@@ -3856,7 +4009,7 @@ do - test -z "$as_dir" && as_dir=. - for ac_prog in mkdir gmkdir; do - for ac_exec_ext in '' $ac_executable_extensions; do -- { test -f "$as_dir/$ac_prog$ac_exec_ext" && $as_test_x "$as_dir/$ac_prog$ac_exec_ext"; } || continue -+ as_fn_executable_p "$as_dir/$ac_prog$ac_exec_ext" || continue - case `"$as_dir/$ac_prog$ac_exec_ext" --version 2>&1` in #( - 'mkdir (GNU coreutils) '* | \ - 'mkdir (coreutils) '* | \ -@@ -3871,6 +4024,7 @@ IFS=$as_save_IFS - - fi - -+ test -d ./--version && rmdir ./--version - if test "${ac_cv_path_mkdir+set}" = set; then - MKDIR_P="$ac_cv_path_mkdir -p" - else -@@ -3878,26 +4032,19 @@ fi - # value for MKDIR_P within a source directory, because that will - # break other packages using the cache if that directory is - # removed, or if the value is a relative name. -- test -d ./--version && rmdir ./--version - MKDIR_P="$ac_install_sh -d" - fi - fi - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $MKDIR_P" >&5 - $as_echo "$MKDIR_P" >&6; } - --mkdir_p="$MKDIR_P" --case $mkdir_p in -- [\\/$]* | ?:[\\/]*) ;; -- */*) mkdir_p="\$(top_builddir)/$mkdir_p" ;; --esac -- - for ac_prog in gawk mawk nawk awk - do - # Extract the first word of "$ac_prog", so it can be a program name with args. - set dummy $ac_prog; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_AWK+set}" = set; then : -+if ${ac_cv_prog_AWK+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$AWK"; then -@@ -3909,7 +4056,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_AWK="$ac_prog" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -3937,7 +4084,7 @@ done - $as_echo_n "checking whether ${MAKE-make} sets \$(MAKE)... " >&6; } - set x ${MAKE-make} - ac_make=`$as_echo "$2" | sed 's/+/p/g; s/[^a-zA-Z0-9_]/_/g'` --if { as_var=ac_cv_prog_make_${ac_make}_set; eval "test \"\${$as_var+set}\" = set"; }; then : -+if eval \${ac_cv_prog_make_${ac_make}_set+:} false; then : - $as_echo_n "(cached) " >&6 - else - cat >conftest.make <<\_ACEOF -@@ -3945,7 +4092,7 @@ SHELL = /bin/sh - all: - @echo '@@@%%%=$(MAKE)=@@@%%%' - _ACEOF --# GNU make sometimes prints "make[1]: Entering...", which would confuse us. -+# GNU make sometimes prints "make[1]: Entering ...", which would confuse us. - case `${MAKE-make} -f conftest.make 2>/dev/null` in - *@@@%%%=?*=@@@%%%*) - eval ac_cv_prog_make_${ac_make}_set=yes;; -@@ -3992,7 +4139,7 @@ am__quote= - _am_result=none - # First try GNU make style include. - echo "include confinc" > confmf --# Ignore all kinds of additional output from `make'. -+# Ignore all kinds of additional output from 'make'. - case `$am_make -s -f confmf 2> /dev/null` in #( - *the\ am__doit\ target*) - am__include=include -@@ -4025,6 +4172,7 @@ fi - if test "x$enable_dependency_tracking" != xno; then - am_depcomp="$ac_aux_dir/depcomp" - AMDEPBACKSLASH='\' -+ am__nodep='_no' - fi - if test "x$enable_dependency_tracking" != xno; then - AMDEP_TRUE= -@@ -4035,13 +4183,52 @@ else - fi - - -+# Check whether --enable-silent-rules was given. -+if test "${enable_silent_rules+set}" = set; then : -+ enableval=$enable_silent_rules; -+fi -+ -+case $enable_silent_rules in # ((( -+ yes) AM_DEFAULT_VERBOSITY=0;; -+ no) AM_DEFAULT_VERBOSITY=1;; -+ *) AM_DEFAULT_VERBOSITY=1;; -+esac -+am_make=${MAKE-make} -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $am_make supports nested variables" >&5 -+$as_echo_n "checking whether $am_make supports nested variables... " >&6; } -+if ${am_cv_make_support_nested_variables+:} false; then : -+ $as_echo_n "(cached) " >&6 -+else -+ if $as_echo 'TRUE=$(BAR$(V)) -+BAR0=false -+BAR1=true -+V=1 -+am__doit: -+ @$(TRUE) -+.PHONY: am__doit' | $am_make -f - >/dev/null 2>&1; then -+ am_cv_make_support_nested_variables=yes -+else -+ am_cv_make_support_nested_variables=no -+fi -+fi -+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $am_cv_make_support_nested_variables" >&5 -+$as_echo "$am_cv_make_support_nested_variables" >&6; } -+if test $am_cv_make_support_nested_variables = yes; then -+ AM_V='$(V)' -+ AM_DEFAULT_V='$(AM_DEFAULT_VERBOSITY)' -+else -+ AM_V=$AM_DEFAULT_VERBOSITY -+ AM_DEFAULT_V=$AM_DEFAULT_VERBOSITY -+fi -+AM_BACKSLASH='\' -+ - if test "`cd $srcdir && pwd`" != "`pwd`"; then - # Use -I$(srcdir) only when $(srcdir) != ., so that make's output - # is not polluted with repeated "-I." - am__isrc=' -I$(srcdir)' - # test to see if srcdir already configured - if test -f $srcdir/config.status; then -- as_fn_error "source directory already configured; run \"make distclean\" there first" "$LINENO" 5 -+ as_fn_error $? "source directory already configured; run \"make distclean\" there first" "$LINENO" 5 - fi - fi - -@@ -4056,6 +4243,7 @@ fi - - - # Define the identity of the package. -+ - PACKAGE=ld - VERSION=${BFD_VERSION} - -@@ -4085,13 +4273,24 @@ AUTOHEADER=${AUTOHEADER-"${am_missing_run}autoheader"} - - MAKEINFO=${MAKEINFO-"${am_missing_run}makeinfo"} - -+# For better backward compatibility. To be removed once Automake 1.9.x -+# dies out for good. For more background, see: -+# -+# -+mkdir_p='$(MKDIR_P)' -+ - # We need awk for the "check" target. The system "awk" is bad on - # some platforms. --# Always define AMTAR for backward compatibility. -+# Always define AMTAR for backward compatibility. Yes, it's still used -+# in the wild :-( We should find a proper way to deprecate it ... -+AMTAR='$${TAR-tar}' -+ -+ -+# We'll loop over all known methods to create a tar archive until one works. -+_am_tools='gnutar pax cpio none' - --AMTAR=${AMTAR-"${am_missing_run}tar"} -+am__tar='$${TAR-tar} chof - "$$tardir"' am__untar='$${TAR-tar} xf -' - --am__tar='${AMTAR} chof - "$$tardir"'; am__untar='${AMTAR} xf -' - - - -@@ -4100,15 +4299,16 @@ depcc="$CC" am_compiler_list= - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking dependency style of $depcc" >&5 - $as_echo_n "checking dependency style of $depcc... " >&6; } --if test "${am_cv_CC_dependencies_compiler_type+set}" = set; then : -+if ${am_cv_CC_dependencies_compiler_type+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -z "$AMDEP_TRUE" && test -f "$am_depcomp"; then - # We make a subdir and do the tests there. Otherwise we can end up - # making bogus files that we don't know about and never remove. For - # instance it was reported that on HP-UX the gcc test will end up -- # making a dummy file named `D' -- because `-MD' means `put the output -- # in D'. -+ # making a dummy file named 'D' -- because '-MD' means "put the output -+ # in D". -+ rm -rf conftest.dir - mkdir conftest.dir - # Copy depcomp to subdir because otherwise we won't find it if we're - # using a relative directory. -@@ -4142,16 +4342,16 @@ else - : > sub/conftest.c - for i in 1 2 3 4 5 6; do - echo '#include "conftst'$i'.h"' >> sub/conftest.c -- # Using `: > sub/conftst$i.h' creates only sub/conftst1.h with -- # Solaris 8's {/usr,}/bin/sh. -- touch sub/conftst$i.h -+ # Using ": > sub/conftst$i.h" creates only sub/conftst1.h with -+ # Solaris 10 /bin/sh. -+ echo '/* dummy */' > sub/conftst$i.h - done - echo "${am__include} ${am__quote}sub/conftest.Po${am__quote}" > confmf - -- # We check with `-c' and `-o' for the sake of the "dashmstdout" -+ # We check with '-c' and '-o' for the sake of the "dashmstdout" - # mode. It turns out that the SunPro C++ compiler does not properly -- # handle `-M -o', and we need to detect this. Also, some Intel -- # versions had trouble with output in subdirs -+ # handle '-M -o', and we need to detect this. Also, some Intel -+ # versions had trouble with output in subdirs. - am__obj=sub/conftest.${OBJEXT-o} - am__minus_obj="-o $am__obj" - case $depmode in -@@ -4160,16 +4360,16 @@ else - test "$am__universal" = false || continue - ;; - nosideeffect) -- # after this tag, mechanisms are not by side-effect, so they'll -- # only be used when explicitly requested -+ # After this tag, mechanisms are not by side-effect, so they'll -+ # only be used when explicitly requested. - if test "x$enable_dependency_tracking" = xyes; then - continue - else - break - fi - ;; -- msvisualcpp | msvcmsys) -- # This compiler won't grok `-c -o', but also, the minuso test has -+ msvc7 | msvc7msys | msvisualcpp | msvcmsys) -+ # This compiler won't grok '-c -o', but also, the minuso test has - # not run yet. These depmodes are late enough in the game, and - # so weak that their functioning should not be impacted. - am__obj=conftest.${OBJEXT-o} -@@ -4224,6 +4424,47 @@ fi - - - -+# POSIX will say in a future version that running "rm -f" with no argument -+# is OK; and we want to be able to make that assumption in our Makefile -+# recipes. So use an aggressive probe to check that the usage we want is -+# actually supported "in the wild" to an acceptable degree. -+# See automake bug#10828. -+# To make any issue more visible, cause the running configure to be aborted -+# by default if the 'rm' program in use doesn't match our expectations; the -+# user can still override this though. -+if rm -f && rm -fr && rm -rf; then : OK; else -+ cat >&2 <<'END' -+Oops! -+ -+Your 'rm' program seems unable to run without file operands specified -+on the command line, even when the '-f' option is present. This is contrary -+to the behaviour of most rm programs out there, and not conforming with -+the upcoming POSIX standard: -+ -+Please tell bug-automake@gnu.org about your system, including the value -+of your $PATH and any error possibly output before this message. This -+can help us improve future automake versions. -+ -+END -+ if test x"$ACCEPT_INFERIOR_RM_PROGRAM" = x"yes"; then -+ echo 'Configuration will proceed anyway, since you have set the' >&2 -+ echo 'ACCEPT_INFERIOR_RM_PROGRAM variable to "yes"' >&2 -+ echo >&2 -+ else -+ cat >&2 <<'END' -+Aborting the configuration process, to ensure you take notice of the issue. -+ -+You can download and install GNU coreutils to get an 'rm' implementation -+that behaves properly: . -+ -+If you want to complete the configuration process using your problematic -+'rm' anyway, export the environment variable ACCEPT_INFERIOR_RM_PROGRAM -+to "yes", and re-run configure. -+ -+END -+ as_fn_error $? "Your 'rm' program is bad, sorry." "$LINENO" 5 -+ fi -+fi - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether to enable maintainer-specific portions of Makefiles" >&5 - $as_echo_n "checking whether to enable maintainer-specific portions of Makefiles... " >&6; } -@@ -4257,7 +4498,7 @@ fi - # Check whether --enable-targets was given. - if test "${enable_targets+set}" = set; then : - enableval=$enable_targets; case "${enableval}" in -- yes | "") as_fn_error "enable-targets option must specify target names or 'all'" "$LINENO" 5 -+ yes | "") as_fn_error $? "enable-targets option must specify target names or 'all'" "$LINENO" 5 - ;; - no) enable_targets= ;; - *) enable_targets=$enableval ;; -@@ -4268,7 +4509,7 @@ if test "${enable_64_bit_bfd+set}" = set; then : - enableval=$enable_64_bit_bfd; case "${enableval}" in - yes) want64=true ;; - no) want64=false ;; -- *) as_fn_error "bad value ${enableval} for 64-bit-bfd option" "$LINENO" 5 ;; -+ *) as_fn_error $? "bad value ${enableval} for 64-bit-bfd option" "$LINENO" 5 ;; - esac - else - want64=false -@@ -4330,7 +4571,7 @@ if test "${enable_gold+set}" = set; then : - installed_linker=ld.bfd - ;; - *) -- as_fn_error "invalid --enable-gold argument" "$LINENO" 5 -+ as_fn_error $? "invalid --enable-gold argument" "$LINENO" 5 - ;; - esac - else -@@ -4345,7 +4586,7 @@ fi - if test "${enable_got+set}" = set; then : - enableval=$enable_got; case "${enableval}" in - target | single | negative | multigot) got_handling=$enableval ;; -- *) as_fn_error "bad value ${enableval} for --enable-got option" "$LINENO" 5 ;; -+ *) as_fn_error $? "bad value ${enableval} for --enable-got option" "$LINENO" 5 ;; - esac - else - got_handling=target -@@ -4369,7 +4610,7 @@ $as_echo "#define GOT_HANDLING_DEFAULT GOT_HANDLING_NEGATIVE" >>confdefs.h - - $as_echo "#define GOT_HANDLING_DEFAULT GOT_HANDLING_MULTIGOT" >>confdefs.h - ;; -- *) as_fn_error "bad value ${got_handling} for --enable-got option" "$LINENO" 5 ;; -+ *) as_fn_error $? "bad value ${got_handling} for --enable-got option" "$LINENO" 5 ;; - esac - - ac_ext=c -@@ -4384,7 +4625,7 @@ if test -n "$CPP" && test -d "$CPP"; then - CPP= - fi - if test -z "$CPP"; then -- if test "${ac_cv_prog_CPP+set}" = set; then : -+ if ${ac_cv_prog_CPP+:} false; then : - $as_echo_n "(cached) " >&6 - else - # Double quotes because CPP needs to be expanded -@@ -4414,7 +4655,7 @@ else - # Broken: fails on valid input. - continue - fi --rm -f conftest.err conftest.$ac_ext -+rm -f conftest.err conftest.i conftest.$ac_ext - - # OK, works on sane cases. Now check whether nonexistent headers - # can be detected and how. -@@ -4430,11 +4671,11 @@ else - ac_preproc_ok=: - break - fi --rm -f conftest.err conftest.$ac_ext -+rm -f conftest.err conftest.i conftest.$ac_ext - - done - # Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. --rm -f conftest.err conftest.$ac_ext -+rm -f conftest.i conftest.err conftest.$ac_ext - if $ac_preproc_ok; then : - break - fi -@@ -4473,7 +4714,7 @@ else - # Broken: fails on valid input. - continue - fi --rm -f conftest.err conftest.$ac_ext -+rm -f conftest.err conftest.i conftest.$ac_ext - - # OK, works on sane cases. Now check whether nonexistent headers - # can be detected and how. -@@ -4489,18 +4730,18 @@ else - ac_preproc_ok=: - break - fi --rm -f conftest.err conftest.$ac_ext -+rm -f conftest.err conftest.i conftest.$ac_ext - - done - # Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. --rm -f conftest.err conftest.$ac_ext -+rm -f conftest.i conftest.err conftest.$ac_ext - if $ac_preproc_ok; then : - - else - { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 - $as_echo "$as_me: error: in \`$ac_pwd':" >&2;} --as_fn_error "C preprocessor \"$CPP\" fails sanity check --See \`config.log' for more details." "$LINENO" 5; } -+as_fn_error $? "C preprocessor \"$CPP\" fails sanity check -+See \`config.log' for more details" "$LINENO" 5; } - fi - - ac_ext=c -@@ -4512,7 +4753,7 @@ ac_compiler_gnu=$ac_cv_c_compiler_gnu - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for grep that handles long lines and -e" >&5 - $as_echo_n "checking for grep that handles long lines and -e... " >&6; } --if test "${ac_cv_path_GREP+set}" = set; then : -+if ${ac_cv_path_GREP+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -z "$GREP"; then -@@ -4526,7 +4767,7 @@ do - for ac_prog in grep ggrep; do - for ac_exec_ext in '' $ac_executable_extensions; do - ac_path_GREP="$as_dir/$ac_prog$ac_exec_ext" -- { test -f "$ac_path_GREP" && $as_test_x "$ac_path_GREP"; } || continue -+ as_fn_executable_p "$ac_path_GREP" || continue - # Check for GNU ac_path_GREP and select it if it is found. - # Check for GNU $ac_path_GREP - case `"$ac_path_GREP" --version 2>&1` in -@@ -4561,7 +4802,7 @@ esac - done - IFS=$as_save_IFS - if test -z "$ac_cv_path_GREP"; then -- as_fn_error "no acceptable grep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 -+ as_fn_error $? "no acceptable grep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 - fi - else - ac_cv_path_GREP=$GREP -@@ -4575,7 +4816,7 @@ $as_echo "$ac_cv_path_GREP" >&6; } - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for egrep" >&5 - $as_echo_n "checking for egrep... " >&6; } --if test "${ac_cv_path_EGREP+set}" = set; then : -+if ${ac_cv_path_EGREP+:} false; then : - $as_echo_n "(cached) " >&6 - else - if echo a | $GREP -E '(a|b)' >/dev/null 2>&1 -@@ -4592,7 +4833,7 @@ do - for ac_prog in egrep; do - for ac_exec_ext in '' $ac_executable_extensions; do - ac_path_EGREP="$as_dir/$ac_prog$ac_exec_ext" -- { test -f "$ac_path_EGREP" && $as_test_x "$ac_path_EGREP"; } || continue -+ as_fn_executable_p "$ac_path_EGREP" || continue - # Check for GNU ac_path_EGREP and select it if it is found. - # Check for GNU $ac_path_EGREP - case `"$ac_path_EGREP" --version 2>&1` in -@@ -4627,7 +4868,7 @@ esac - done - IFS=$as_save_IFS - if test -z "$ac_cv_path_EGREP"; then -- as_fn_error "no acceptable egrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 -+ as_fn_error $? "no acceptable egrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 - fi - else - ac_cv_path_EGREP=$EGREP -@@ -4660,7 +4901,7 @@ if test "${enable_werror+set}" = set; then : - enableval=$enable_werror; case "${enableval}" in - yes | y) ERROR_ON_WARNING="yes" ;; - no | n) ERROR_ON_WARNING="no" ;; -- *) as_fn_error "bad value ${enableval} for --enable-werror" "$LINENO" 5 ;; -+ *) as_fn_error $? "bad value ${enableval} for --enable-werror" "$LINENO" 5 ;; - esac - fi - -@@ -4717,7 +4958,7 @@ fi - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for LC_MESSAGES" >&5 - $as_echo_n "checking for LC_MESSAGES... " >&6; } --if test "${am_cv_val_LC_MESSAGES+set}" = set; then : -+if ${am_cv_val_LC_MESSAGES+:} false; then : - $as_echo_n "(cached) " >&6 - else - cat confdefs.h - <<_ACEOF >conftest.$ac_ext -@@ -4755,10 +4996,10 @@ ac_config_headers="$ac_config_headers config.h:config.in" - - - if test -z "$target" ; then -- as_fn_error "Unrecognized target system type; please check config.sub." "$LINENO" 5 -+ as_fn_error $? "Unrecognized target system type; please check config.sub." "$LINENO" 5 - fi - if test -z "$host" ; then -- as_fn_error "Unrecognized host system type; please check config.sub." "$LINENO" 5 -+ as_fn_error $? "Unrecognized host system type; please check config.sub." "$LINENO" 5 - fi - - # host-specific stuff: -@@ -4773,7 +5014,7 @@ if test -n "$ac_tool_prefix"; then - set dummy ${ac_tool_prefix}gcc; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_CC+set}" = set; then : -+if ${ac_cv_prog_CC+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$CC"; then -@@ -4785,7 +5026,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_CC="${ac_tool_prefix}gcc" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -4813,7 +5054,7 @@ if test -z "$ac_cv_prog_CC"; then - set dummy gcc; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_ac_ct_CC+set}" = set; then : -+if ${ac_cv_prog_ac_ct_CC+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$ac_ct_CC"; then -@@ -4825,7 +5066,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_ac_ct_CC="gcc" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -4866,7 +5107,7 @@ if test -z "$CC"; then - set dummy ${ac_tool_prefix}cc; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_CC+set}" = set; then : -+if ${ac_cv_prog_CC+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$CC"; then -@@ -4878,7 +5119,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_CC="${ac_tool_prefix}cc" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -4906,7 +5147,7 @@ if test -z "$CC"; then - set dummy cc; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_CC+set}" = set; then : -+if ${ac_cv_prog_CC+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$CC"; then -@@ -4919,7 +5160,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then - ac_prog_rejected=yes - continue -@@ -4965,7 +5206,7 @@ if test -z "$CC"; then - set dummy $ac_tool_prefix$ac_prog; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_CC+set}" = set; then : -+if ${ac_cv_prog_CC+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$CC"; then -@@ -4977,7 +5218,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_CC="$ac_tool_prefix$ac_prog" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -5009,7 +5250,7 @@ do - set dummy $ac_prog; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_ac_ct_CC+set}" = set; then : -+if ${ac_cv_prog_ac_ct_CC+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$ac_ct_CC"; then -@@ -5021,7 +5262,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_ac_ct_CC="$ac_prog" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -5063,8 +5304,8 @@ fi - - test -z "$CC" && { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 - $as_echo "$as_me: error: in \`$ac_pwd':" >&2;} --as_fn_error "no acceptable C compiler found in \$PATH --See \`config.log' for more details." "$LINENO" 5; } -+as_fn_error $? "no acceptable C compiler found in \$PATH -+See \`config.log' for more details" "$LINENO" 5; } - - # Provide some information about the compiler. - $as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler version" >&5 -@@ -5085,15 +5326,15 @@ $as_echo "$ac_try_echo"; } >&5 - ... rest of stderr output deleted ... - 10q' conftest.err >conftest.er1 - cat conftest.er1 >&5 -- rm -f conftest.er1 conftest.err - fi -+ rm -f conftest.er1 conftest.err - $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 - test $ac_status = 0; } - done - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using the GNU C compiler" >&5 - $as_echo_n "checking whether we are using the GNU C compiler... " >&6; } --if test "${ac_cv_c_compiler_gnu+set}" = set; then : -+if ${ac_cv_c_compiler_gnu+:} false; then : - $as_echo_n "(cached) " >&6 - else - cat confdefs.h - <<_ACEOF >conftest.$ac_ext -@@ -5130,7 +5371,7 @@ ac_test_CFLAGS=${CFLAGS+set} - ac_save_CFLAGS=$CFLAGS - { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC accepts -g" >&5 - $as_echo_n "checking whether $CC accepts -g... " >&6; } --if test "${ac_cv_prog_cc_g+set}" = set; then : -+if ${ac_cv_prog_cc_g+:} false; then : - $as_echo_n "(cached) " >&6 - else - ac_save_c_werror_flag=$ac_c_werror_flag -@@ -5208,7 +5449,7 @@ else - fi - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $CC option to accept ISO C89" >&5 - $as_echo_n "checking for $CC option to accept ISO C89... " >&6; } --if test "${ac_cv_prog_cc_c89+set}" = set; then : -+if ${ac_cv_prog_cc_c89+:} false; then : - $as_echo_n "(cached) " >&6 - else - ac_cv_prog_cc_c89=no -@@ -5217,8 +5458,7 @@ cat confdefs.h - <<_ACEOF >conftest.$ac_ext - /* end confdefs.h. */ - #include - #include --#include --#include -+struct stat; - /* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */ - struct buf { int x; }; - FILE * (*rcsopen) (struct buf *, struct stat *, int); -@@ -5303,6 +5543,65 @@ ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' - ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' - ac_compiler_gnu=$ac_cv_c_compiler_gnu - -+ac_ext=c -+ac_cpp='$CPP $CPPFLAGS' -+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' -+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' -+ac_compiler_gnu=$ac_cv_c_compiler_gnu -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC understands -c and -o together" >&5 -+$as_echo_n "checking whether $CC understands -c and -o together... " >&6; } -+if ${am_cv_prog_cc_c_o+:} false; then : -+ $as_echo_n "(cached) " >&6 -+else -+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext -+/* end confdefs.h. */ -+ -+int -+main () -+{ -+ -+ ; -+ return 0; -+} -+_ACEOF -+ # Make sure it works both with $CC and with simple cc. -+ # Following AC_PROG_CC_C_O, we do the test twice because some -+ # compilers refuse to overwrite an existing .o file with -o, -+ # though they will create one. -+ am_cv_prog_cc_c_o=yes -+ for am_i in 1 2; do -+ if { echo "$as_me:$LINENO: $CC -c conftest.$ac_ext -o conftest2.$ac_objext" >&5 -+ ($CC -c conftest.$ac_ext -o conftest2.$ac_objext) >&5 2>&5 -+ ac_status=$? -+ echo "$as_me:$LINENO: \$? = $ac_status" >&5 -+ (exit $ac_status); } \ -+ && test -f conftest2.$ac_objext; then -+ : OK -+ else -+ am_cv_prog_cc_c_o=no -+ break -+ fi -+ done -+ rm -f core conftest* -+ unset am_i -+fi -+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $am_cv_prog_cc_c_o" >&5 -+$as_echo "$am_cv_prog_cc_c_o" >&6; } -+if test "$am_cv_prog_cc_c_o" != yes; then -+ # Losing compiler, so override with the script. -+ # FIXME: It is wrong to rewrite CC. -+ # But if we don't then we get into trouble of one sort or another. -+ # A longer-term fix would be to have automake use am__CC in this case, -+ # and then we could set am__CC="\$(top_srcdir)/compile \$(CC)" -+ CC="$am_aux_dir/compile $CC" -+fi -+ac_ext=c -+ac_cpp='$CPP $CPPFLAGS' -+ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' -+ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' -+ac_compiler_gnu=$ac_cv_c_compiler_gnu -+ -+ - ac_ext=cpp - ac_cpp='$CXXCPP $CPPFLAGS' - ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5' -@@ -5319,7 +5618,7 @@ if test -z "$CXX"; then - set dummy $ac_tool_prefix$ac_prog; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_CXX+set}" = set; then : -+if ${ac_cv_prog_CXX+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$CXX"; then -@@ -5331,7 +5630,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_CXX="$ac_tool_prefix$ac_prog" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -5363,7 +5662,7 @@ do - set dummy $ac_prog; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_ac_ct_CXX+set}" = set; then : -+if ${ac_cv_prog_ac_ct_CXX+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$ac_ct_CXX"; then -@@ -5375,7 +5674,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_ac_ct_CXX="$ac_prog" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -5433,15 +5732,15 @@ $as_echo "$ac_try_echo"; } >&5 - ... rest of stderr output deleted ... - 10q' conftest.err >conftest.er1 - cat conftest.er1 >&5 -- rm -f conftest.er1 conftest.err - fi -+ rm -f conftest.er1 conftest.err - $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 - test $ac_status = 0; } - done - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using the GNU C++ compiler" >&5 - $as_echo_n "checking whether we are using the GNU C++ compiler... " >&6; } --if test "${ac_cv_cxx_compiler_gnu+set}" = set; then : -+if ${ac_cv_cxx_compiler_gnu+:} false; then : - $as_echo_n "(cached) " >&6 - else - cat confdefs.h - <<_ACEOF >conftest.$ac_ext -@@ -5478,7 +5777,7 @@ ac_test_CXXFLAGS=${CXXFLAGS+set} - ac_save_CXXFLAGS=$CXXFLAGS - { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CXX accepts -g" >&5 - $as_echo_n "checking whether $CXX accepts -g... " >&6; } --if test "${ac_cv_prog_cxx_g+set}" = set; then : -+if ${ac_cv_prog_cxx_g+:} false; then : - $as_echo_n "(cached) " >&6 - else - ac_save_cxx_werror_flag=$ac_cxx_werror_flag -@@ -5564,15 +5863,16 @@ depcc="$CXX" am_compiler_list= - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking dependency style of $depcc" >&5 - $as_echo_n "checking dependency style of $depcc... " >&6; } --if test "${am_cv_CXX_dependencies_compiler_type+set}" = set; then : -+if ${am_cv_CXX_dependencies_compiler_type+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -z "$AMDEP_TRUE" && test -f "$am_depcomp"; then - # We make a subdir and do the tests there. Otherwise we can end up - # making bogus files that we don't know about and never remove. For - # instance it was reported that on HP-UX the gcc test will end up -- # making a dummy file named `D' -- because `-MD' means `put the output -- # in D'. -+ # making a dummy file named 'D' -- because '-MD' means "put the output -+ # in D". -+ rm -rf conftest.dir - mkdir conftest.dir - # Copy depcomp to subdir because otherwise we won't find it if we're - # using a relative directory. -@@ -5606,16 +5906,16 @@ else - : > sub/conftest.c - for i in 1 2 3 4 5 6; do - echo '#include "conftst'$i'.h"' >> sub/conftest.c -- # Using `: > sub/conftst$i.h' creates only sub/conftst1.h with -- # Solaris 8's {/usr,}/bin/sh. -- touch sub/conftst$i.h -+ # Using ": > sub/conftst$i.h" creates only sub/conftst1.h with -+ # Solaris 10 /bin/sh. -+ echo '/* dummy */' > sub/conftst$i.h - done - echo "${am__include} ${am__quote}sub/conftest.Po${am__quote}" > confmf - -- # We check with `-c' and `-o' for the sake of the "dashmstdout" -+ # We check with '-c' and '-o' for the sake of the "dashmstdout" - # mode. It turns out that the SunPro C++ compiler does not properly -- # handle `-M -o', and we need to detect this. Also, some Intel -- # versions had trouble with output in subdirs -+ # handle '-M -o', and we need to detect this. Also, some Intel -+ # versions had trouble with output in subdirs. - am__obj=sub/conftest.${OBJEXT-o} - am__minus_obj="-o $am__obj" - case $depmode in -@@ -5624,16 +5924,16 @@ else - test "$am__universal" = false || continue - ;; - nosideeffect) -- # after this tag, mechanisms are not by side-effect, so they'll -- # only be used when explicitly requested -+ # After this tag, mechanisms are not by side-effect, so they'll -+ # only be used when explicitly requested. - if test "x$enable_dependency_tracking" = xyes; then - continue - else - break - fi - ;; -- msvisualcpp | msvcmsys) -- # This compiler won't grok `-c -o', but also, the minuso test has -+ msvc7 | msvc7msys | msvisualcpp | msvcmsys) -+ # This compiler won't grok '-c -o', but also, the minuso test has - # not run yet. These depmodes are late enough in the game, and - # so weak that their functioning should not be impacted. - am__obj=conftest.${OBJEXT-o} -@@ -5689,7 +5989,7 @@ fi - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for ANSI C header files" >&5 - $as_echo_n "checking for ANSI C header files... " >&6; } --if test "${ac_cv_header_stdc+set}" = set; then : -+if ${ac_cv_header_stdc+:} false; then : - $as_echo_n "(cached) " >&6 - else - cat confdefs.h - <<_ACEOF >conftest.$ac_ext -@@ -5806,8 +6106,7 @@ do : - as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` - ac_fn_c_check_header_compile "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default - " --eval as_val=\$$as_ac_Header -- if test "x$as_val" = x""yes; then : -+if eval test \"x\$"$as_ac_Header"\" = x"yes"; then : - cat >>confdefs.h <<_ACEOF - #define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 - _ACEOF -@@ -5819,7 +6118,7 @@ done - - - ac_fn_c_check_header_mongrel "$LINENO" "minix/config.h" "ac_cv_header_minix_config_h" "$ac_includes_default" --if test "x$ac_cv_header_minix_config_h" = x""yes; then : -+if test "x$ac_cv_header_minix_config_h" = xyes; then : - MINIX=yes - else - MINIX= -@@ -5841,14 +6140,14 @@ $as_echo "#define _MINIX 1" >>confdefs.h - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether it is safe to define __EXTENSIONS__" >&5 - $as_echo_n "checking whether it is safe to define __EXTENSIONS__... " >&6; } --if test "${ac_cv_safe_to_define___extensions__+set}" = set; then : -+if ${ac_cv_safe_to_define___extensions__+:} false; then : - $as_echo_n "(cached) " >&6 - else - cat confdefs.h - <<_ACEOF >conftest.$ac_ext - /* end confdefs.h. */ - --# define __EXTENSIONS__ 1 -- $ac_includes_default -+# define __EXTENSIONS__ 1 -+ $ac_includes_default - int - main () - { -@@ -5925,7 +6224,7 @@ if test "$enable_largefile" != no; then - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for special C compiler options needed for large files" >&5 - $as_echo_n "checking for special C compiler options needed for large files... " >&6; } --if test "${ac_cv_sys_largefile_CC+set}" = set; then : -+if ${ac_cv_sys_largefile_CC+:} false; then : - $as_echo_n "(cached) " >&6 - else - ac_cv_sys_largefile_CC=no -@@ -5976,7 +6275,7 @@ $as_echo "$ac_cv_sys_largefile_CC" >&6; } - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for _FILE_OFFSET_BITS value needed for large files" >&5 - $as_echo_n "checking for _FILE_OFFSET_BITS value needed for large files... " >&6; } --if test "${ac_cv_sys_file_offset_bits+set}" = set; then : -+if ${ac_cv_sys_file_offset_bits+:} false; then : - $as_echo_n "(cached) " >&6 - else - while :; do -@@ -6045,7 +6344,7 @@ rm -rf conftest* - if test $ac_cv_sys_file_offset_bits = unknown; then - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for _LARGE_FILES value needed for large files" >&5 - $as_echo_n "checking for _LARGE_FILES value needed for large files... " >&6; } --if test "${ac_cv_sys_large_files+set}" = set; then : -+if ${ac_cv_sys_large_files+:} false; then : - $as_echo_n "(cached) " >&6 - else - while :; do -@@ -6112,6 +6411,8 @@ _ACEOF - esac - rm -rf conftest* - fi -+ -+ - fi - - -@@ -6213,7 +6514,7 @@ esac - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for a sed that does not truncate output" >&5 - $as_echo_n "checking for a sed that does not truncate output... " >&6; } --if test "${ac_cv_path_SED+set}" = set; then : -+if ${ac_cv_path_SED+:} false; then : - $as_echo_n "(cached) " >&6 - else - ac_script=s/aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa/bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb/ -@@ -6233,7 +6534,7 @@ do - for ac_prog in sed gsed; do - for ac_exec_ext in '' $ac_executable_extensions; do - ac_path_SED="$as_dir/$ac_prog$ac_exec_ext" -- { test -f "$ac_path_SED" && $as_test_x "$ac_path_SED"; } || continue -+ as_fn_executable_p "$ac_path_SED" || continue - # Check for GNU ac_path_SED and select it if it is found. - # Check for GNU $ac_path_SED - case `"$ac_path_SED" --version 2>&1` in -@@ -6268,7 +6569,7 @@ esac - done - IFS=$as_save_IFS - if test -z "$ac_cv_path_SED"; then -- as_fn_error "no acceptable sed could be found in \$PATH" "$LINENO" 5 -+ as_fn_error $? "no acceptable sed could be found in \$PATH" "$LINENO" 5 - fi - else - ac_cv_path_SED=$SED -@@ -6295,7 +6596,7 @@ Xsed="$SED -e 1s/^X//" - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for fgrep" >&5 - $as_echo_n "checking for fgrep... " >&6; } --if test "${ac_cv_path_FGREP+set}" = set; then : -+if ${ac_cv_path_FGREP+:} false; then : - $as_echo_n "(cached) " >&6 - else - if echo 'ab*c' | $GREP -F 'ab*c' >/dev/null 2>&1 -@@ -6312,7 +6613,7 @@ do - for ac_prog in fgrep; do - for ac_exec_ext in '' $ac_executable_extensions; do - ac_path_FGREP="$as_dir/$ac_prog$ac_exec_ext" -- { test -f "$ac_path_FGREP" && $as_test_x "$ac_path_FGREP"; } || continue -+ as_fn_executable_p "$ac_path_FGREP" || continue - # Check for GNU ac_path_FGREP and select it if it is found. - # Check for GNU $ac_path_FGREP - case `"$ac_path_FGREP" --version 2>&1` in -@@ -6347,7 +6648,7 @@ esac - done - IFS=$as_save_IFS - if test -z "$ac_cv_path_FGREP"; then -- as_fn_error "no acceptable fgrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 -+ as_fn_error $? "no acceptable fgrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 - fi - else - ac_cv_path_FGREP=$FGREP -@@ -6426,7 +6727,7 @@ else - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for non-GNU ld" >&5 - $as_echo_n "checking for non-GNU ld... " >&6; } - fi --if test "${lt_cv_path_LD+set}" = set; then : -+if ${lt_cv_path_LD+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -z "$LD"; then -@@ -6463,10 +6764,10 @@ else - { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 - $as_echo "no" >&6; } - fi --test -z "$LD" && as_fn_error "no acceptable ld found in \$PATH" "$LINENO" 5 -+test -z "$LD" && as_fn_error $? "no acceptable ld found in \$PATH" "$LINENO" 5 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking if the linker ($LD) is GNU ld" >&5 - $as_echo_n "checking if the linker ($LD) is GNU ld... " >&6; } --if test "${lt_cv_prog_gnu_ld+set}" = set; then : -+if ${lt_cv_prog_gnu_ld+:} false; then : - $as_echo_n "(cached) " >&6 - else - # I'd rather use --version here, but apparently some GNU lds only accept -v. -@@ -6493,7 +6794,7 @@ with_gnu_ld=$lt_cv_prog_gnu_ld - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for BSD- or MS-compatible name lister (nm)" >&5 - $as_echo_n "checking for BSD- or MS-compatible name lister (nm)... " >&6; } --if test "${lt_cv_path_NM+set}" = set; then : -+if ${lt_cv_path_NM+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$NM"; then -@@ -6556,7 +6857,7 @@ else - set dummy $ac_tool_prefix$ac_prog; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_DUMPBIN+set}" = set; then : -+if ${ac_cv_prog_DUMPBIN+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$DUMPBIN"; then -@@ -6568,7 +6869,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_DUMPBIN="$ac_tool_prefix$ac_prog" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -6600,7 +6901,7 @@ do - set dummy $ac_prog; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_ac_ct_DUMPBIN+set}" = set; then : -+if ${ac_cv_prog_ac_ct_DUMPBIN+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$ac_ct_DUMPBIN"; then -@@ -6612,7 +6913,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_ac_ct_DUMPBIN="$ac_prog" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -6672,7 +6973,7 @@ test -z "$NM" && NM=nm - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking the name lister ($NM) interface" >&5 - $as_echo_n "checking the name lister ($NM) interface... " >&6; } --if test "${lt_cv_nm_interface+set}" = set; then : -+if ${lt_cv_nm_interface+:} false; then : - $as_echo_n "(cached) " >&6 - else - lt_cv_nm_interface="BSD nm" -@@ -6707,7 +7008,7 @@ fi - # find the maximum length of command line arguments - { $as_echo "$as_me:${as_lineno-$LINENO}: checking the maximum length of command line arguments" >&5 - $as_echo_n "checking the maximum length of command line arguments... " >&6; } --if test "${lt_cv_sys_max_cmd_len+set}" = set; then : -+if ${lt_cv_sys_max_cmd_len+:} false; then : - $as_echo_n "(cached) " >&6 - else - i=0 -@@ -6904,7 +7205,7 @@ esac - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $LD option to reload object files" >&5 - $as_echo_n "checking for $LD option to reload object files... " >&6; } --if test "${lt_cv_ld_reload_flag+set}" = set; then : -+if ${lt_cv_ld_reload_flag+:} false; then : - $as_echo_n "(cached) " >&6 - else - lt_cv_ld_reload_flag='-r' -@@ -6940,7 +7241,7 @@ if test -n "$ac_tool_prefix"; then - set dummy ${ac_tool_prefix}objdump; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_OBJDUMP+set}" = set; then : -+if ${ac_cv_prog_OBJDUMP+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$OBJDUMP"; then -@@ -6952,7 +7253,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_OBJDUMP="${ac_tool_prefix}objdump" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -6980,7 +7281,7 @@ if test -z "$ac_cv_prog_OBJDUMP"; then - set dummy objdump; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_ac_ct_OBJDUMP+set}" = set; then : -+if ${ac_cv_prog_ac_ct_OBJDUMP+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$ac_ct_OBJDUMP"; then -@@ -6992,7 +7293,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_ac_ct_OBJDUMP="objdump" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -7039,7 +7340,7 @@ test -z "$OBJDUMP" && OBJDUMP=objdump - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking how to recognize dependent libraries" >&5 - $as_echo_n "checking how to recognize dependent libraries... " >&6; } --if test "${lt_cv_deplibs_check_method+set}" = set; then : -+if ${lt_cv_deplibs_check_method+:} false; then : - $as_echo_n "(cached) " >&6 - else - lt_cv_file_magic_cmd='$MAGIC_CMD' -@@ -7260,7 +7561,7 @@ if test -n "$ac_tool_prefix"; then - set dummy ${ac_tool_prefix}ar; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_AR+set}" = set; then : -+if ${ac_cv_prog_AR+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$AR"; then -@@ -7272,7 +7573,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_AR="${ac_tool_prefix}ar" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -7300,7 +7601,7 @@ if test -z "$ac_cv_prog_AR"; then - set dummy ar; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_ac_ct_AR+set}" = set; then : -+if ${ac_cv_prog_ac_ct_AR+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$ac_ct_AR"; then -@@ -7312,7 +7613,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_ac_ct_AR="ar" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -7365,7 +7666,7 @@ if test -n "$ac_tool_prefix"; then - set dummy ${ac_tool_prefix}strip; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_STRIP+set}" = set; then : -+if ${ac_cv_prog_STRIP+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$STRIP"; then -@@ -7377,7 +7678,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_STRIP="${ac_tool_prefix}strip" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -7405,7 +7706,7 @@ if test -z "$ac_cv_prog_STRIP"; then - set dummy strip; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_ac_ct_STRIP+set}" = set; then : -+if ${ac_cv_prog_ac_ct_STRIP+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$ac_ct_STRIP"; then -@@ -7417,7 +7718,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_ac_ct_STRIP="strip" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -7464,7 +7765,7 @@ if test -n "$ac_tool_prefix"; then - set dummy ${ac_tool_prefix}ranlib; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_RANLIB+set}" = set; then : -+if ${ac_cv_prog_RANLIB+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$RANLIB"; then -@@ -7476,7 +7777,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -7504,7 +7805,7 @@ if test -z "$ac_cv_prog_RANLIB"; then - set dummy ranlib; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_ac_ct_RANLIB+set}" = set; then : -+if ${ac_cv_prog_ac_ct_RANLIB+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$ac_ct_RANLIB"; then -@@ -7516,7 +7817,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_ac_ct_RANLIB="ranlib" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -7633,7 +7934,7 @@ compiler=$CC - # Check for command to grab the raw symbol name followed by C symbol from nm. - { $as_echo "$as_me:${as_lineno-$LINENO}: checking command to parse $NM output from $compiler object" >&5 - $as_echo_n "checking command to parse $NM output from $compiler object... " >&6; } --if test "${lt_cv_sys_global_symbol_pipe+set}" = set; then : -+if ${lt_cv_sys_global_symbol_pipe+:} false; then : - $as_echo_n "(cached) " >&6 - else - -@@ -8017,7 +8318,7 @@ s390*-*linux*|s390*-*tpf*|sparc*-*linux*) - CFLAGS="$CFLAGS -belf" - { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the C compiler needs -belf" >&5 - $as_echo_n "checking whether the C compiler needs -belf... " >&6; } --if test "${lt_cv_cc_needs_belf+set}" = set; then : -+if ${lt_cv_cc_needs_belf+:} false; then : - $as_echo_n "(cached) " >&6 - else - ac_ext=c -@@ -8093,7 +8394,7 @@ need_locks="$enable_libtool_lock" - set dummy ${ac_tool_prefix}dsymutil; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_DSYMUTIL+set}" = set; then : -+if ${ac_cv_prog_DSYMUTIL+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$DSYMUTIL"; then -@@ -8105,7 +8406,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_DSYMUTIL="${ac_tool_prefix}dsymutil" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -8133,7 +8434,7 @@ if test -z "$ac_cv_prog_DSYMUTIL"; then - set dummy dsymutil; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_ac_ct_DSYMUTIL+set}" = set; then : -+if ${ac_cv_prog_ac_ct_DSYMUTIL+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$ac_ct_DSYMUTIL"; then -@@ -8145,7 +8446,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_ac_ct_DSYMUTIL="dsymutil" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -8185,7 +8486,7 @@ fi - set dummy ${ac_tool_prefix}nmedit; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_NMEDIT+set}" = set; then : -+if ${ac_cv_prog_NMEDIT+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$NMEDIT"; then -@@ -8197,7 +8498,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_NMEDIT="${ac_tool_prefix}nmedit" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -8225,7 +8526,7 @@ if test -z "$ac_cv_prog_NMEDIT"; then - set dummy nmedit; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_ac_ct_NMEDIT+set}" = set; then : -+if ${ac_cv_prog_ac_ct_NMEDIT+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$ac_ct_NMEDIT"; then -@@ -8237,7 +8538,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_ac_ct_NMEDIT="nmedit" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -8277,7 +8578,7 @@ fi - set dummy ${ac_tool_prefix}lipo; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_LIPO+set}" = set; then : -+if ${ac_cv_prog_LIPO+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$LIPO"; then -@@ -8289,7 +8590,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_LIPO="${ac_tool_prefix}lipo" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -8317,7 +8618,7 @@ if test -z "$ac_cv_prog_LIPO"; then - set dummy lipo; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_ac_ct_LIPO+set}" = set; then : -+if ${ac_cv_prog_ac_ct_LIPO+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$ac_ct_LIPO"; then -@@ -8329,7 +8630,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_ac_ct_LIPO="lipo" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -8369,7 +8670,7 @@ fi - set dummy ${ac_tool_prefix}otool; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_OTOOL+set}" = set; then : -+if ${ac_cv_prog_OTOOL+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$OTOOL"; then -@@ -8381,7 +8682,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_OTOOL="${ac_tool_prefix}otool" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -8409,7 +8710,7 @@ if test -z "$ac_cv_prog_OTOOL"; then - set dummy otool; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_ac_ct_OTOOL+set}" = set; then : -+if ${ac_cv_prog_ac_ct_OTOOL+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$ac_ct_OTOOL"; then -@@ -8421,7 +8722,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_ac_ct_OTOOL="otool" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -8461,7 +8762,7 @@ fi - set dummy ${ac_tool_prefix}otool64; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_OTOOL64+set}" = set; then : -+if ${ac_cv_prog_OTOOL64+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$OTOOL64"; then -@@ -8473,7 +8774,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_OTOOL64="${ac_tool_prefix}otool64" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -8501,7 +8802,7 @@ if test -z "$ac_cv_prog_OTOOL64"; then - set dummy otool64; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_ac_ct_OTOOL64+set}" = set; then : -+if ${ac_cv_prog_ac_ct_OTOOL64+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$ac_ct_OTOOL64"; then -@@ -8513,7 +8814,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_ac_ct_OTOOL64="otool64" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -8576,7 +8877,7 @@ fi - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for -single_module linker flag" >&5 - $as_echo_n "checking for -single_module linker flag... " >&6; } --if test "${lt_cv_apple_cc_single_mod+set}" = set; then : -+if ${lt_cv_apple_cc_single_mod+:} false; then : - $as_echo_n "(cached) " >&6 - else - lt_cv_apple_cc_single_mod=no -@@ -8605,7 +8906,7 @@ fi - $as_echo "$lt_cv_apple_cc_single_mod" >&6; } - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for -exported_symbols_list linker flag" >&5 - $as_echo_n "checking for -exported_symbols_list linker flag... " >&6; } --if test "${lt_cv_ld_exported_symbols_list+set}" = set; then : -+if ${lt_cv_ld_exported_symbols_list+:} false; then : - $as_echo_n "(cached) " >&6 - else - lt_cv_ld_exported_symbols_list=no -@@ -8637,7 +8938,7 @@ fi - $as_echo "$lt_cv_ld_exported_symbols_list" >&6; } - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for -force_load linker flag" >&5 - $as_echo_n "checking for -force_load linker flag... " >&6; } --if test "${lt_cv_ld_force_load+set}" = set; then : -+if ${lt_cv_ld_force_load+:} false; then : - $as_echo_n "(cached) " >&6 - else - lt_cv_ld_force_load=no -@@ -8704,7 +9005,7 @@ for ac_header in dlfcn.h - do : - ac_fn_c_check_header_compile "$LINENO" "dlfcn.h" "ac_cv_header_dlfcn_h" "$ac_includes_default - " --if test "x$ac_cv_header_dlfcn_h" = x""yes; then : -+if test "x$ac_cv_header_dlfcn_h" = xyes; then : - cat >>confdefs.h <<_ACEOF - #define HAVE_DLFCN_H 1 - _ACEOF -@@ -8892,7 +9193,7 @@ fi - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for objdir" >&5 - $as_echo_n "checking for objdir... " >&6; } --if test "${lt_cv_objdir+set}" = set; then : -+if ${lt_cv_objdir+:} false; then : - $as_echo_n "(cached) " >&6 - else - rm -f .libs 2>/dev/null -@@ -8970,7 +9271,7 @@ file_magic*) - if test "$file_magic_cmd" = '$MAGIC_CMD'; then - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for ${ac_tool_prefix}file" >&5 - $as_echo_n "checking for ${ac_tool_prefix}file... " >&6; } --if test "${lt_cv_path_MAGIC_CMD+set}" = set; then : -+if ${lt_cv_path_MAGIC_CMD+:} false; then : - $as_echo_n "(cached) " >&6 - else - case $MAGIC_CMD in -@@ -9036,7 +9337,7 @@ if test -z "$lt_cv_path_MAGIC_CMD"; then - if test -n "$ac_tool_prefix"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for file" >&5 - $as_echo_n "checking for file... " >&6; } --if test "${lt_cv_path_MAGIC_CMD+set}" = set; then : -+if ${lt_cv_path_MAGIC_CMD+:} false; then : - $as_echo_n "(cached) " >&6 - else - case $MAGIC_CMD in -@@ -9178,7 +9479,7 @@ if test "$GCC" = yes; then - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler supports -fno-rtti -fno-exceptions" >&5 - $as_echo_n "checking if $compiler supports -fno-rtti -fno-exceptions... " >&6; } --if test "${lt_cv_prog_compiler_rtti_exceptions+set}" = set; then : -+if ${lt_cv_prog_compiler_rtti_exceptions+:} false; then : - $as_echo_n "(cached) " >&6 - else - lt_cv_prog_compiler_rtti_exceptions=no -@@ -9531,7 +9832,7 @@ $as_echo "$lt_prog_compiler_pic" >&6; } - if test -n "$lt_prog_compiler_pic"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler PIC flag $lt_prog_compiler_pic works" >&5 - $as_echo_n "checking if $compiler PIC flag $lt_prog_compiler_pic works... " >&6; } --if test "${lt_cv_prog_compiler_pic_works+set}" = set; then : -+if ${lt_cv_prog_compiler_pic_works+:} false; then : - $as_echo_n "(cached) " >&6 - else - lt_cv_prog_compiler_pic_works=no -@@ -9590,7 +9891,7 @@ fi - wl=$lt_prog_compiler_wl eval lt_tmp_static_flag=\"$lt_prog_compiler_static\" - { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler static flag $lt_tmp_static_flag works" >&5 - $as_echo_n "checking if $compiler static flag $lt_tmp_static_flag works... " >&6; } --if test "${lt_cv_prog_compiler_static_works+set}" = set; then : -+if ${lt_cv_prog_compiler_static_works+:} false; then : - $as_echo_n "(cached) " >&6 - else - lt_cv_prog_compiler_static_works=no -@@ -9633,7 +9934,7 @@ fi - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler supports -c -o file.$ac_objext" >&5 - $as_echo_n "checking if $compiler supports -c -o file.$ac_objext... " >&6; } --if test "${lt_cv_prog_compiler_c_o+set}" = set; then : -+if ${lt_cv_prog_compiler_c_o+:} false; then : - $as_echo_n "(cached) " >&6 - else - lt_cv_prog_compiler_c_o=no -@@ -9688,7 +9989,7 @@ $as_echo "$lt_cv_prog_compiler_c_o" >&6; } - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler supports -c -o file.$ac_objext" >&5 - $as_echo_n "checking if $compiler supports -c -o file.$ac_objext... " >&6; } --if test "${lt_cv_prog_compiler_c_o+set}" = set; then : -+if ${lt_cv_prog_compiler_c_o+:} false; then : - $as_echo_n "(cached) " >&6 - else - lt_cv_prog_compiler_c_o=no -@@ -10504,7 +10805,7 @@ if test -z "$aix_libpath"; then aix_libpath="/usr/lib:/lib"; fi - # (HP92453-01 A.11.01.20 doesn't, HP92453-01 B.11.X.35175-35176.GP does) - { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $CC understands -b" >&5 - $as_echo_n "checking if $CC understands -b... " >&6; } --if test "${lt_cv_prog_compiler__b+set}" = set; then : -+if ${lt_cv_prog_compiler__b+:} false; then : - $as_echo_n "(cached) " >&6 - else - lt_cv_prog_compiler__b=no -@@ -10876,7 +11177,7 @@ x|xyes) - # to ld, don't add -lc before -lgcc. - { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether -lc should be explicitly linked in" >&5 - $as_echo_n "checking whether -lc should be explicitly linked in... " >&6; } --if test "${lt_cv_archive_cmds_need_lc+set}" = set; then : -+if ${lt_cv_archive_cmds_need_lc+:} false; then : - $as_echo_n "(cached) " >&6 - else - $RM conftest* -@@ -11514,7 +11815,7 @@ linux* | k*bsd*-gnu | kopensolaris*-gnu) - shlibpath_overrides_runpath=no - - # Some binutils ld are patched to set DT_RUNPATH -- if test "${lt_cv_shlibpath_overrides_runpath+set}" = set; then : -+ if ${lt_cv_shlibpath_overrides_runpath+:} false; then : - $as_echo_n "(cached) " >&6 - else - lt_cv_shlibpath_overrides_runpath=no -@@ -11934,7 +12235,7 @@ else - # if libdl is installed we need to link against it - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for dlopen in -ldl" >&5 - $as_echo_n "checking for dlopen in -ldl... " >&6; } --if test "${ac_cv_lib_dl_dlopen+set}" = set; then : -+if ${ac_cv_lib_dl_dlopen+:} false; then : - $as_echo_n "(cached) " >&6 - else - ac_check_lib_save_LIBS=$LIBS -@@ -11968,7 +12269,7 @@ LIBS=$ac_check_lib_save_LIBS - fi - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dl_dlopen" >&5 - $as_echo "$ac_cv_lib_dl_dlopen" >&6; } --if test "x$ac_cv_lib_dl_dlopen" = x""yes; then : -+if test "x$ac_cv_lib_dl_dlopen" = xyes; then : - lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-ldl" - else - -@@ -11982,12 +12283,12 @@ fi - - *) - ac_fn_c_check_func "$LINENO" "shl_load" "ac_cv_func_shl_load" --if test "x$ac_cv_func_shl_load" = x""yes; then : -+if test "x$ac_cv_func_shl_load" = xyes; then : - lt_cv_dlopen="shl_load" - else - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for shl_load in -ldld" >&5 - $as_echo_n "checking for shl_load in -ldld... " >&6; } --if test "${ac_cv_lib_dld_shl_load+set}" = set; then : -+if ${ac_cv_lib_dld_shl_load+:} false; then : - $as_echo_n "(cached) " >&6 - else - ac_check_lib_save_LIBS=$LIBS -@@ -12021,16 +12322,16 @@ LIBS=$ac_check_lib_save_LIBS - fi - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dld_shl_load" >&5 - $as_echo "$ac_cv_lib_dld_shl_load" >&6; } --if test "x$ac_cv_lib_dld_shl_load" = x""yes; then : -+if test "x$ac_cv_lib_dld_shl_load" = xyes; then : - lt_cv_dlopen="shl_load" lt_cv_dlopen_libs="-ldld" - else - ac_fn_c_check_func "$LINENO" "dlopen" "ac_cv_func_dlopen" --if test "x$ac_cv_func_dlopen" = x""yes; then : -+if test "x$ac_cv_func_dlopen" = xyes; then : - lt_cv_dlopen="dlopen" - else - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for dlopen in -ldl" >&5 - $as_echo_n "checking for dlopen in -ldl... " >&6; } --if test "${ac_cv_lib_dl_dlopen+set}" = set; then : -+if ${ac_cv_lib_dl_dlopen+:} false; then : - $as_echo_n "(cached) " >&6 - else - ac_check_lib_save_LIBS=$LIBS -@@ -12064,12 +12365,12 @@ LIBS=$ac_check_lib_save_LIBS - fi - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dl_dlopen" >&5 - $as_echo "$ac_cv_lib_dl_dlopen" >&6; } --if test "x$ac_cv_lib_dl_dlopen" = x""yes; then : -+if test "x$ac_cv_lib_dl_dlopen" = xyes; then : - lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-ldl" - else - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for dlopen in -lsvld" >&5 - $as_echo_n "checking for dlopen in -lsvld... " >&6; } --if test "${ac_cv_lib_svld_dlopen+set}" = set; then : -+if ${ac_cv_lib_svld_dlopen+:} false; then : - $as_echo_n "(cached) " >&6 - else - ac_check_lib_save_LIBS=$LIBS -@@ -12103,12 +12404,12 @@ LIBS=$ac_check_lib_save_LIBS - fi - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_svld_dlopen" >&5 - $as_echo "$ac_cv_lib_svld_dlopen" >&6; } --if test "x$ac_cv_lib_svld_dlopen" = x""yes; then : -+if test "x$ac_cv_lib_svld_dlopen" = xyes; then : - lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-lsvld" - else - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for dld_link in -ldld" >&5 - $as_echo_n "checking for dld_link in -ldld... " >&6; } --if test "${ac_cv_lib_dld_dld_link+set}" = set; then : -+if ${ac_cv_lib_dld_dld_link+:} false; then : - $as_echo_n "(cached) " >&6 - else - ac_check_lib_save_LIBS=$LIBS -@@ -12142,7 +12443,7 @@ LIBS=$ac_check_lib_save_LIBS - fi - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dld_dld_link" >&5 - $as_echo "$ac_cv_lib_dld_dld_link" >&6; } --if test "x$ac_cv_lib_dld_dld_link" = x""yes; then : -+if test "x$ac_cv_lib_dld_dld_link" = xyes; then : - lt_cv_dlopen="dld_link" lt_cv_dlopen_libs="-ldld" - fi - -@@ -12183,7 +12484,7 @@ fi - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether a program can dlopen itself" >&5 - $as_echo_n "checking whether a program can dlopen itself... " >&6; } --if test "${lt_cv_dlopen_self+set}" = set; then : -+if ${lt_cv_dlopen_self+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test "$cross_compiling" = yes; then : -@@ -12192,7 +12493,7 @@ else - lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 - lt_status=$lt_dlunknown - cat > conftest.$ac_ext <<_LT_EOF --#line 12195 "configure" -+#line 12496 "configure" - #include "confdefs.h" - - #if HAVE_DLFCN_H -@@ -12289,7 +12590,7 @@ $as_echo "$lt_cv_dlopen_self" >&6; } - wl=$lt_prog_compiler_wl eval LDFLAGS=\"\$LDFLAGS $lt_prog_compiler_static\" - { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether a statically linked program can dlopen itself" >&5 - $as_echo_n "checking whether a statically linked program can dlopen itself... " >&6; } --if test "${lt_cv_dlopen_self_static+set}" = set; then : -+if ${lt_cv_dlopen_self_static+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test "$cross_compiling" = yes; then : -@@ -12298,7 +12599,7 @@ else - lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 - lt_status=$lt_dlunknown - cat > conftest.$ac_ext <<_LT_EOF --#line 12301 "configure" -+#line 12602 "configure" - #include "confdefs.h" - - #if HAVE_DLFCN_H -@@ -12526,7 +12827,7 @@ ac_compiler_gnu=$ac_cv_cxx_compiler_gnu - { $as_echo "$as_me:${as_lineno-$LINENO}: checking how to run the C++ preprocessor" >&5 - $as_echo_n "checking how to run the C++ preprocessor... " >&6; } - if test -z "$CXXCPP"; then -- if test "${ac_cv_prog_CXXCPP+set}" = set; then : -+ if ${ac_cv_prog_CXXCPP+:} false; then : - $as_echo_n "(cached) " >&6 - else - # Double quotes because CXXCPP needs to be expanded -@@ -12556,7 +12857,7 @@ else - # Broken: fails on valid input. - continue - fi --rm -f conftest.err conftest.$ac_ext -+rm -f conftest.err conftest.i conftest.$ac_ext - - # OK, works on sane cases. Now check whether nonexistent headers - # can be detected and how. -@@ -12572,11 +12873,11 @@ else - ac_preproc_ok=: - break - fi --rm -f conftest.err conftest.$ac_ext -+rm -f conftest.err conftest.i conftest.$ac_ext - - done - # Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. --rm -f conftest.err conftest.$ac_ext -+rm -f conftest.i conftest.err conftest.$ac_ext - if $ac_preproc_ok; then : - break - fi -@@ -12615,7 +12916,7 @@ else - # Broken: fails on valid input. - continue - fi --rm -f conftest.err conftest.$ac_ext -+rm -f conftest.err conftest.i conftest.$ac_ext - - # OK, works on sane cases. Now check whether nonexistent headers - # can be detected and how. -@@ -12631,18 +12932,18 @@ else - ac_preproc_ok=: - break - fi --rm -f conftest.err conftest.$ac_ext -+rm -f conftest.err conftest.i conftest.$ac_ext - - done - # Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. --rm -f conftest.err conftest.$ac_ext -+rm -f conftest.i conftest.err conftest.$ac_ext - if $ac_preproc_ok; then : - - else - { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 - $as_echo "$as_me: error: in \`$ac_pwd':" >&2;} --as_fn_error "C++ preprocessor \"$CXXCPP\" fails sanity check --See \`config.log' for more details." "$LINENO" 5; } -+as_fn_error $? "C++ preprocessor \"$CXXCPP\" fails sanity check -+See \`config.log' for more details" "$LINENO" 5; } - fi - - ac_ext=c -@@ -12827,7 +13128,7 @@ else - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for non-GNU ld" >&5 - $as_echo_n "checking for non-GNU ld... " >&6; } - fi --if test "${lt_cv_path_LD+set}" = set; then : -+if ${lt_cv_path_LD+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -z "$LD"; then -@@ -12864,10 +13165,10 @@ else - { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 - $as_echo "no" >&6; } - fi --test -z "$LD" && as_fn_error "no acceptable ld found in \$PATH" "$LINENO" 5 -+test -z "$LD" && as_fn_error $? "no acceptable ld found in \$PATH" "$LINENO" 5 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking if the linker ($LD) is GNU ld" >&5 - $as_echo_n "checking if the linker ($LD) is GNU ld... " >&6; } --if test "${lt_cv_prog_gnu_ld+set}" = set; then : -+if ${lt_cv_prog_gnu_ld+:} false; then : - $as_echo_n "(cached) " >&6 - else - # I'd rather use --version here, but apparently some GNU lds only accept -v. -@@ -14414,7 +14715,7 @@ $as_echo "$lt_prog_compiler_pic_CXX" >&6; } - if test -n "$lt_prog_compiler_pic_CXX"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler PIC flag $lt_prog_compiler_pic_CXX works" >&5 - $as_echo_n "checking if $compiler PIC flag $lt_prog_compiler_pic_CXX works... " >&6; } --if test "${lt_cv_prog_compiler_pic_works_CXX+set}" = set; then : -+if ${lt_cv_prog_compiler_pic_works_CXX+:} false; then : - $as_echo_n "(cached) " >&6 - else - lt_cv_prog_compiler_pic_works_CXX=no -@@ -14470,7 +14771,7 @@ fi - wl=$lt_prog_compiler_wl_CXX eval lt_tmp_static_flag=\"$lt_prog_compiler_static_CXX\" - { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler static flag $lt_tmp_static_flag works" >&5 - $as_echo_n "checking if $compiler static flag $lt_tmp_static_flag works... " >&6; } --if test "${lt_cv_prog_compiler_static_works_CXX+set}" = set; then : -+if ${lt_cv_prog_compiler_static_works_CXX+:} false; then : - $as_echo_n "(cached) " >&6 - else - lt_cv_prog_compiler_static_works_CXX=no -@@ -14510,7 +14811,7 @@ fi - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler supports -c -o file.$ac_objext" >&5 - $as_echo_n "checking if $compiler supports -c -o file.$ac_objext... " >&6; } --if test "${lt_cv_prog_compiler_c_o_CXX+set}" = set; then : -+if ${lt_cv_prog_compiler_c_o_CXX+:} false; then : - $as_echo_n "(cached) " >&6 - else - lt_cv_prog_compiler_c_o_CXX=no -@@ -14562,7 +14863,7 @@ $as_echo "$lt_cv_prog_compiler_c_o_CXX" >&6; } - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler supports -c -o file.$ac_objext" >&5 - $as_echo_n "checking if $compiler supports -c -o file.$ac_objext... " >&6; } --if test "${lt_cv_prog_compiler_c_o_CXX+set}" = set; then : -+if ${lt_cv_prog_compiler_c_o_CXX+:} false; then : - $as_echo_n "(cached) " >&6 - else - lt_cv_prog_compiler_c_o_CXX=no -@@ -14695,7 +14996,7 @@ x|xyes) - # to ld, don't add -lc before -lgcc. - { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether -lc should be explicitly linked in" >&5 - $as_echo_n "checking whether -lc should be explicitly linked in... " >&6; } --if test "${lt_cv_archive_cmds_need_lc_CXX+set}" = set; then : -+if ${lt_cv_archive_cmds_need_lc_CXX+:} false; then : - $as_echo_n "(cached) " >&6 - else - $RM conftest* -@@ -15174,7 +15475,7 @@ linux* | k*bsd*-gnu | kopensolaris*-gnu) - shlibpath_overrides_runpath=no - - # Some binutils ld are patched to set DT_RUNPATH -- if test "${lt_cv_shlibpath_overrides_runpath+set}" = set; then : -+ if ${lt_cv_shlibpath_overrides_runpath+:} false; then : - $as_echo_n "(cached) " >&6 - else - lt_cv_shlibpath_overrides_runpath=no -@@ -15686,7 +15987,7 @@ rm -f conf$$.file - set dummy msgfmt; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_path_MSGFMT+set}" = set; then : -+if ${ac_cv_path_MSGFMT+:} false; then : - $as_echo_n "(cached) " >&6 - else - case "$MSGFMT" in -@@ -15726,7 +16027,7 @@ fi - set dummy gmsgfmt; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_path_GMSGFMT+set}" = set; then : -+if ${ac_cv_path_GMSGFMT+:} false; then : - $as_echo_n "(cached) " >&6 - else - case $GMSGFMT in -@@ -15740,7 +16041,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_path_GMSGFMT="$as_dir/$ac_word$ac_exec_ext" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -15797,7 +16098,7 @@ rm -f conf$$.file - set dummy xgettext; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_path_XGETTEXT+set}" = set; then : -+if ${ac_cv_path_XGETTEXT+:} false; then : - $as_echo_n "(cached) " >&6 - else - case "$XGETTEXT" in -@@ -15868,7 +16169,7 @@ rm -f conf$$.file - set dummy msgmerge; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_path_MSGMERGE+set}" = set; then : -+if ${ac_cv_path_MSGMERGE+:} false; then : - $as_echo_n "(cached) " >&6 - else - case "$MSGMERGE" in -@@ -15940,7 +16241,7 @@ do - set dummy $ac_prog; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_YACC+set}" = set; then : -+if ${ac_cv_prog_YACC+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$YACC"; then -@@ -15952,7 +16253,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_YACC="$ac_prog" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -15983,7 +16284,7 @@ do - set dummy $ac_prog; ac_word=$2 - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 - $as_echo_n "checking for $ac_word... " >&6; } --if test "${ac_cv_prog_LEX+set}" = set; then : -+if ${ac_cv_prog_LEX+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test -n "$LEX"; then -@@ -15995,7 +16296,7 @@ do - IFS=$as_save_IFS - test -z "$as_dir" && as_dir=. - for ac_exec_ext in '' $ac_executable_extensions; do -- if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then -+ if as_fn_executable_p "$as_dir/$ac_word$ac_exec_ext"; then - ac_cv_prog_LEX="$ac_prog" - $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 - break 2 -@@ -16027,7 +16328,8 @@ a { ECHO; } - b { REJECT; } - c { yymore (); } - d { yyless (1); } --e { yyless (input () != 0); } -+e { /* IRIX 6.5 flex 2.5.4 underquotes its yyless argument. */ -+ yyless ((input () != 0)); } - f { unput (yytext[0]); } - . { BEGIN INITIAL; } - %% -@@ -16053,7 +16355,7 @@ $as_echo "$ac_try_echo"; } >&5 - test $ac_status = 0; } - { $as_echo "$as_me:${as_lineno-$LINENO}: checking lex output file root" >&5 - $as_echo_n "checking lex output file root... " >&6; } --if test "${ac_cv_prog_lex_root+set}" = set; then : -+if ${ac_cv_prog_lex_root+:} false; then : - $as_echo_n "(cached) " >&6 - else - -@@ -16062,7 +16364,7 @@ if test -f lex.yy.c; then - elif test -f lexyy.c; then - ac_cv_prog_lex_root=lexyy - else -- as_fn_error "cannot find output from $LEX; giving up" "$LINENO" 5 -+ as_fn_error $? "cannot find output from $LEX; giving up" "$LINENO" 5 - fi - fi - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_lex_root" >&5 -@@ -16072,7 +16374,7 @@ LEX_OUTPUT_ROOT=$ac_cv_prog_lex_root - if test -z "${LEXLIB+set}"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: checking lex library" >&5 - $as_echo_n "checking lex library... " >&6; } --if test "${ac_cv_lib_lex+set}" = set; then : -+if ${ac_cv_lib_lex+:} false; then : - $as_echo_n "(cached) " >&6 - else - -@@ -16102,7 +16404,7 @@ fi - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether yytext is a pointer" >&5 - $as_echo_n "checking whether yytext is a pointer... " >&6; } --if test "${ac_cv_prog_lex_yytext_pointer+set}" = set; then : -+if ${ac_cv_prog_lex_yytext_pointer+:} false; then : - $as_echo_n "(cached) " >&6 - else - # POSIX says lex can declare yytext either as a pointer or an array; the -@@ -16113,7 +16415,8 @@ ac_save_LIBS=$LIBS - LIBS="$LEXLIB $ac_save_LIBS" - cat confdefs.h - <<_ACEOF >conftest.$ac_ext - /* end confdefs.h. */ --#define YYTEXT_POINTER 1 -+ -+ #define YYTEXT_POINTER 1 - `cat $LEX_OUTPUT_ROOT.c` - _ACEOF - if ac_fn_c_try_link "$LINENO"; then : -@@ -16171,7 +16474,7 @@ fi - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking how to compare bootstrapped objects" >&5 - $as_echo_n "checking how to compare bootstrapped objects... " >&6; } --if test "${gcc_cv_prog_cmp_skip+set}" = set; then : -+if ${gcc_cv_prog_cmp_skip+:} false; then : - $as_echo_n "(cached) " >&6 - else - echo abfoo >t1 -@@ -16212,8 +16515,7 @@ for ac_header in string.h strings.h stdlib.h unistd.h elf-hints.h limits.h local - do : - as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` - ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default" --eval as_val=\$$as_ac_Header -- if test "x$as_val" = x""yes; then : -+if eval test \"x\$"$as_ac_Header"\" = x"yes"; then : - cat >>confdefs.h <<_ACEOF - #define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 - _ACEOF -@@ -16226,8 +16528,7 @@ for ac_header in fcntl.h sys/file.h sys/time.h sys/stat.h - do : - as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` - ac_fn_c_check_header_mongrel "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default" --eval as_val=\$$as_ac_Header -- if test "x$as_val" = x""yes; then : -+if eval test \"x\$"$as_ac_Header"\" = x"yes"; then : - cat >>confdefs.h <<_ACEOF - #define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 - _ACEOF -@@ -16238,7 +16539,7 @@ done - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether string.h and strings.h may both be included" >&5 - $as_echo_n "checking whether string.h and strings.h may both be included... " >&6; } --if test "${gcc_cv_header_string+set}" = set; then : -+if ${gcc_cv_header_string+:} false; then : - $as_echo_n "(cached) " >&6 - else - cat confdefs.h - <<_ACEOF >conftest.$ac_ext -@@ -16272,8 +16573,7 @@ for ac_func in glob mkstemp realpath sbrk setlocale waitpid - do : - as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh` - ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var" --eval as_val=\$$as_ac_var -- if test "x$as_val" = x""yes; then : -+if eval test \"x\$"$as_ac_var"\" = x"yes"; then : - cat >>confdefs.h <<_ACEOF - #define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1 - _ACEOF -@@ -16285,8 +16585,7 @@ for ac_func in open lseek close - do : - as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh` - ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var" --eval as_val=\$$as_ac_var -- if test "x$as_val" = x""yes; then : -+if eval test \"x\$"$as_ac_var"\" = x"yes"; then : - cat >>confdefs.h <<_ACEOF - #define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1 - _ACEOF -@@ -16299,7 +16598,7 @@ for ac_hdr in dirent.h sys/ndir.h sys/dir.h ndir.h; do - as_ac_Header=`$as_echo "ac_cv_header_dirent_$ac_hdr" | $as_tr_sh` - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_hdr that defines DIR" >&5 - $as_echo_n "checking for $ac_hdr that defines DIR... " >&6; } --if { as_var=$as_ac_Header; eval "test \"\${$as_var+set}\" = set"; }; then : -+if eval \${$as_ac_Header+:} false; then : - $as_echo_n "(cached) " >&6 - else - cat confdefs.h - <<_ACEOF >conftest.$ac_ext -@@ -16326,8 +16625,7 @@ fi - eval ac_res=\$$as_ac_Header - { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 - $as_echo "$ac_res" >&6; } --eval as_val=\$$as_ac_Header -- if test "x$as_val" = x""yes; then : -+if eval test \"x\$"$as_ac_Header"\" = x"yes"; then : - cat >>confdefs.h <<_ACEOF - #define `$as_echo "HAVE_$ac_hdr" | $as_tr_cpp` 1 - _ACEOF -@@ -16340,7 +16638,7 @@ done - if test $ac_header_dirent = dirent.h; then - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for library containing opendir" >&5 - $as_echo_n "checking for library containing opendir... " >&6; } --if test "${ac_cv_search_opendir+set}" = set; then : -+if ${ac_cv_search_opendir+:} false; then : - $as_echo_n "(cached) " >&6 - else - ac_func_search_save_LIBS=$LIBS -@@ -16374,11 +16672,11 @@ for ac_lib in '' dir; do - fi - rm -f core conftest.err conftest.$ac_objext \ - conftest$ac_exeext -- if test "${ac_cv_search_opendir+set}" = set; then : -+ if ${ac_cv_search_opendir+:} false; then : - break - fi - done --if test "${ac_cv_search_opendir+set}" = set; then : -+if ${ac_cv_search_opendir+:} false; then : - - else - ac_cv_search_opendir=no -@@ -16397,7 +16695,7 @@ fi - else - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for library containing opendir" >&5 - $as_echo_n "checking for library containing opendir... " >&6; } --if test "${ac_cv_search_opendir+set}" = set; then : -+if ${ac_cv_search_opendir+:} false; then : - $as_echo_n "(cached) " >&6 - else - ac_func_search_save_LIBS=$LIBS -@@ -16431,11 +16729,11 @@ for ac_lib in '' x; do - fi - rm -f core conftest.err conftest.$ac_objext \ - conftest$ac_exeext -- if test "${ac_cv_search_opendir+set}" = set; then : -+ if ${ac_cv_search_opendir+:} false; then : - break - fi - done --if test "${ac_cv_search_opendir+set}" = set; then : -+if ${ac_cv_search_opendir+:} false; then : - - else - ac_cv_search_opendir=no -@@ -16458,7 +16756,7 @@ fi - enable_plugins=yes - ac_fn_c_check_header_compile "$LINENO" "dlfcn.h" "ac_cv_header_dlfcn_h" "$ac_includes_default - " --if test "x$ac_cv_header_dlfcn_h" = x""yes; then : -+if test "x$ac_cv_header_dlfcn_h" = xyes; then : - - else - enable_plugins=no -@@ -16467,7 +16765,7 @@ fi - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for library containing dlopen" >&5 - $as_echo_n "checking for library containing dlopen... " >&6; } --if test "${ac_cv_search_dlopen+set}" = set; then : -+if ${ac_cv_search_dlopen+:} false; then : - $as_echo_n "(cached) " >&6 - else - ac_func_search_save_LIBS=$LIBS -@@ -16501,11 +16799,11 @@ for ac_lib in '' dl; do - fi - rm -f core conftest.err conftest.$ac_objext \ - conftest$ac_exeext -- if test "${ac_cv_search_dlopen+set}" = set; then : -+ if ${ac_cv_search_dlopen+:} false; then : - break - fi - done --if test "${ac_cv_search_dlopen+set}" = set; then : -+if ${ac_cv_search_dlopen+:} false; then : - - else - ac_cv_search_dlopen=no -@@ -16527,8 +16825,7 @@ for ac_func in dlopen dlsym dlclose - do : - as_ac_var=`$as_echo "ac_cv_func_$ac_func" | $as_tr_sh` - ac_fn_c_check_func "$LINENO" "$ac_func" "$as_ac_var" --eval as_val=\$$as_ac_var -- if test "x$as_val" = x""yes; then : -+if eval test \"x\$"$as_ac_var"\" = x"yes"; then : - cat >>confdefs.h <<_ACEOF - #define `$as_echo "HAVE_$ac_func" | $as_tr_cpp` 1 - _ACEOF -@@ -16544,7 +16841,7 @@ if test x$enable_plugins = xno ; then - do : - ac_fn_c_check_header_compile "$LINENO" "windows.h" "ac_cv_header_windows_h" "$ac_includes_default - " --if test "x$ac_cv_header_windows_h" = x""yes; then : -+if test "x$ac_cv_header_windows_h" = xyes; then : - cat >>confdefs.h <<_ACEOF - #define HAVE_WINDOWS_H 1 - _ACEOF -@@ -16570,7 +16867,7 @@ else - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for .preinit_array/.init_array/.fini_array support" >&5 - $as_echo_n "checking for .preinit_array/.init_array/.fini_array support... " >&6; } --if test "${gcc_cv_initfini_array+set}" = set; then : -+if ${gcc_cv_initfini_array+:} false; then : - $as_echo_n "(cached) " >&6 - else - if test "x${build}" = "x${target}" ; then -@@ -16613,7 +16910,7 @@ fi - - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for a known getopt prototype in unistd.h" >&5 - $as_echo_n "checking for a known getopt prototype in unistd.h... " >&6; } --if test "${ld_cv_decl_getopt_unistd_h+set}" = set; then : -+if ${ld_cv_decl_getopt_unistd_h+:} false; then : - $as_echo_n "(cached) " >&6 - else - cat confdefs.h - <<_ACEOF >conftest.$ac_ext -@@ -16652,7 +16949,7 @@ $as_echo "#define USE_BINARY_FOPEN 1" >>confdefs.h - esac - - ac_fn_c_check_decl "$LINENO" "strstr" "ac_cv_have_decl_strstr" "$ac_includes_default" --if test "x$ac_cv_have_decl_strstr" = x""yes; then : -+if test "x$ac_cv_have_decl_strstr" = xyes; then : - ac_have_decl=1 - else - ac_have_decl=0 -@@ -16662,7 +16959,7 @@ cat >>confdefs.h <<_ACEOF - #define HAVE_DECL_STRSTR $ac_have_decl - _ACEOF - ac_fn_c_check_decl "$LINENO" "free" "ac_cv_have_decl_free" "$ac_includes_default" --if test "x$ac_cv_have_decl_free" = x""yes; then : -+if test "x$ac_cv_have_decl_free" = xyes; then : - ac_have_decl=1 - else - ac_have_decl=0 -@@ -16672,7 +16969,7 @@ cat >>confdefs.h <<_ACEOF - #define HAVE_DECL_FREE $ac_have_decl - _ACEOF - ac_fn_c_check_decl "$LINENO" "sbrk" "ac_cv_have_decl_sbrk" "$ac_includes_default" --if test "x$ac_cv_have_decl_sbrk" = x""yes; then : -+if test "x$ac_cv_have_decl_sbrk" = xyes; then : - ac_have_decl=1 - else - ac_have_decl=0 -@@ -16682,7 +16979,7 @@ cat >>confdefs.h <<_ACEOF - #define HAVE_DECL_SBRK $ac_have_decl - _ACEOF - ac_fn_c_check_decl "$LINENO" "getenv" "ac_cv_have_decl_getenv" "$ac_includes_default" --if test "x$ac_cv_have_decl_getenv" = x""yes; then : -+if test "x$ac_cv_have_decl_getenv" = xyes; then : - ac_have_decl=1 - else - ac_have_decl=0 -@@ -16692,7 +16989,7 @@ cat >>confdefs.h <<_ACEOF - #define HAVE_DECL_GETENV $ac_have_decl - _ACEOF - ac_fn_c_check_decl "$LINENO" "environ" "ac_cv_have_decl_environ" "$ac_includes_default" --if test "x$ac_cv_have_decl_environ" = x""yes; then : -+if test "x$ac_cv_have_decl_environ" = xyes; then : - ac_have_decl=1 - else - ac_have_decl=0 -@@ -16719,7 +17016,7 @@ fi - if test "$with_zlib" != "no"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: checking for library containing zlibVersion" >&5 - $as_echo_n "checking for library containing zlibVersion... " >&6; } --if test "${ac_cv_search_zlibVersion+set}" = set; then : -+if ${ac_cv_search_zlibVersion+:} false; then : - $as_echo_n "(cached) " >&6 - else - ac_func_search_save_LIBS=$LIBS -@@ -16753,11 +17050,11 @@ for ac_lib in '' z; do - fi - rm -f core conftest.err conftest.$ac_objext \ - conftest$ac_exeext -- if test "${ac_cv_search_zlibVersion+set}" = set; then : -+ if ${ac_cv_search_zlibVersion+:} false; then : - break - fi - done --if test "${ac_cv_search_zlibVersion+set}" = set; then : -+if ${ac_cv_search_zlibVersion+:} false; then : - - else - ac_cv_search_zlibVersion=no -@@ -16773,7 +17070,7 @@ if test "$ac_res" != no; then : - for ac_header in zlib.h - do : - ac_fn_c_check_header_mongrel "$LINENO" "zlib.h" "ac_cv_header_zlib_h" "$ac_includes_default" --if test "x$ac_cv_header_zlib_h" = x""yes; then : -+if test "x$ac_cv_header_zlib_h" = xyes; then : - cat >>confdefs.h <<_ACEOF - #define HAVE_ZLIB_H 1 - _ACEOF -@@ -16785,7 +17082,7 @@ done - fi - - if test "$with_zlib" = "yes" -a "$ac_cv_header_zlib_h" != "yes"; then -- as_fn_error "zlib (libz) library was explicitly requested but not found" "$LINENO" 5 -+ as_fn_error $? "zlib (libz) library was explicitly requested but not found" "$LINENO" 5 - fi - fi - -@@ -16798,7 +17095,7 @@ fi - # support string concatenation. - { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether ANSI C string concatenation works" >&5 - $as_echo_n "checking whether ANSI C string concatenation works... " >&6; } --if test "${ld_cv_string_concatenation+set}" = set; then : -+if ${ld_cv_string_concatenation+:} false; then : - $as_echo_n "(cached) " >&6 - else - cat confdefs.h - <<_ACEOF >conftest.$ac_ext -@@ -16848,7 +17145,7 @@ if test x${want64} = xfalse; then - # This bug is HP SR number 8606223364. - { $as_echo "$as_me:${as_lineno-$LINENO}: checking size of void *" >&5 - $as_echo_n "checking size of void *... " >&6; } --if test "${ac_cv_sizeof_void_p+set}" = set; then : -+if ${ac_cv_sizeof_void_p+:} false; then : - $as_echo_n "(cached) " >&6 - else - if ac_fn_c_compute_int "$LINENO" "(long int) (sizeof (void *))" "ac_cv_sizeof_void_p" "$ac_includes_default"; then : -@@ -16857,9 +17154,8 @@ else - if test "$ac_cv_type_void_p" = yes; then - { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 - $as_echo "$as_me: error: in \`$ac_pwd':" >&2;} --{ as_fn_set_status 77 --as_fn_error "cannot compute sizeof (void *) --See \`config.log' for more details." "$LINENO" 5; }; } -+as_fn_error 77 "cannot compute sizeof (void *) -+See \`config.log' for more details" "$LINENO" 5; } - else - ac_cv_sizeof_void_p=0 - fi -@@ -17064,10 +17360,21 @@ $as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; - :end' >>confcache - if diff "$cache_file" confcache >/dev/null 2>&1; then :; else - if test -w "$cache_file"; then -- test "x$cache_file" != "x/dev/null" && -+ if test "x$cache_file" != "x/dev/null"; then - { $as_echo "$as_me:${as_lineno-$LINENO}: updating cache $cache_file" >&5 - $as_echo "$as_me: updating cache $cache_file" >&6;} -- cat confcache >$cache_file -+ if test ! -f "$cache_file" || test -h "$cache_file"; then -+ cat confcache >"$cache_file" -+ else -+ case $cache_file in #( -+ */* | ?:*) -+ mv -f confcache "$cache_file"$$ && -+ mv -f "$cache_file"$$ "$cache_file" ;; #( -+ *) -+ mv -f confcache "$cache_file" ;; -+ esac -+ fi -+ fi - else - { $as_echo "$as_me:${as_lineno-$LINENO}: not updating unwritable cache $cache_file" >&5 - $as_echo "$as_me: not updating unwritable cache $cache_file" >&6;} -@@ -17083,6 +17390,7 @@ DEFS=-DHAVE_CONFIG_H - - ac_libobjs= - ac_ltlibobjs= -+U= - for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue - # 1. Remove the extension, and $U if already installed. - ac_script='s/\$U\././;s/\.o$//;s/\.obj$//' -@@ -17097,12 +17405,20 @@ LIBOBJS=$ac_libobjs - LTLIBOBJS=$ac_ltlibobjs - - -+{ $as_echo "$as_me:${as_lineno-$LINENO}: checking that generated files are newer than configure" >&5 -+$as_echo_n "checking that generated files are newer than configure... " >&6; } -+ if test -n "$am_sleep_pid"; then -+ # Hide warnings about reused PIDs. -+ wait $am_sleep_pid 2>/dev/null -+ fi -+ { $as_echo "$as_me:${as_lineno-$LINENO}: result: done" >&5 -+$as_echo "done" >&6; } - if test -z "${AMDEP_TRUE}" && test -z "${AMDEP_FALSE}"; then -- as_fn_error "conditional \"AMDEP\" was never defined. -+ as_fn_error $? "conditional \"AMDEP\" was never defined. - Usually this means the macro was only invoked conditionally." "$LINENO" 5 - fi - if test -z "${am__fastdepCC_TRUE}" && test -z "${am__fastdepCC_FALSE}"; then -- as_fn_error "conditional \"am__fastdepCC\" was never defined. -+ as_fn_error $? "conditional \"am__fastdepCC\" was never defined. - Usually this means the macro was only invoked conditionally." "$LINENO" 5 - fi - if test -n "$EXEEXT"; then -@@ -17114,27 +17430,27 @@ else - fi - - if test -z "${MAINTAINER_MODE_TRUE}" && test -z "${MAINTAINER_MODE_FALSE}"; then -- as_fn_error "conditional \"MAINTAINER_MODE\" was never defined. -+ as_fn_error $? "conditional \"MAINTAINER_MODE\" was never defined. - Usually this means the macro was only invoked conditionally." "$LINENO" 5 - fi - if test -z "${am__fastdepCXX_TRUE}" && test -z "${am__fastdepCXX_FALSE}"; then -- as_fn_error "conditional \"am__fastdepCXX\" was never defined. -+ as_fn_error $? "conditional \"am__fastdepCXX\" was never defined. - Usually this means the macro was only invoked conditionally." "$LINENO" 5 - fi - if test -z "${MAINTAINER_MODE_TRUE}" && test -z "${MAINTAINER_MODE_FALSE}"; then -- as_fn_error "conditional \"MAINTAINER_MODE\" was never defined. -+ as_fn_error $? "conditional \"MAINTAINER_MODE\" was never defined. - Usually this means the macro was only invoked conditionally." "$LINENO" 5 - fi - if test -z "${GENINSRC_NEVER_TRUE}" && test -z "${GENINSRC_NEVER_FALSE}"; then -- as_fn_error "conditional \"GENINSRC_NEVER\" was never defined. -+ as_fn_error $? "conditional \"GENINSRC_NEVER\" was never defined. - Usually this means the macro was only invoked conditionally." "$LINENO" 5 - fi - if test -z "${ENABLE_PLUGINS_TRUE}" && test -z "${ENABLE_PLUGINS_FALSE}"; then -- as_fn_error "conditional \"ENABLE_PLUGINS\" was never defined. -+ as_fn_error $? "conditional \"ENABLE_PLUGINS\" was never defined. - Usually this means the macro was only invoked conditionally." "$LINENO" 5 - fi - --: ${CONFIG_STATUS=./config.status} -+: "${CONFIG_STATUS=./config.status}" - ac_write_fail=0 - ac_clean_files_save=$ac_clean_files - ac_clean_files="$ac_clean_files $CONFIG_STATUS" -@@ -17235,6 +17551,7 @@ fi - IFS=" "" $as_nl" - - # Find who we are. Look in the path if we contain no directory separator. -+as_myself= - case $0 in #(( - *[\\/]* ) as_myself=$0 ;; - *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR -@@ -17280,19 +17597,19 @@ export LANGUAGE - (unset CDPATH) >/dev/null 2>&1 && unset CDPATH - - --# as_fn_error ERROR [LINENO LOG_FD] --# --------------------------------- -+# as_fn_error STATUS ERROR [LINENO LOG_FD] -+# ---------------------------------------- - # Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are - # provided, also output the error to LOG_FD, referencing LINENO. Then exit the --# script with status $?, using 1 if that was 0. -+# script with STATUS, using 1 if that was 0. - as_fn_error () - { -- as_status=$?; test $as_status -eq 0 && as_status=1 -- if test "$3"; then -- as_lineno=${as_lineno-"$2"} as_lineno_stack=as_lineno_stack=$as_lineno_stack -- $as_echo "$as_me:${as_lineno-$LINENO}: error: $1" >&$3 -+ as_status=$1; test $as_status -eq 0 && as_status=1 -+ if test "$4"; then -+ as_lineno=${as_lineno-"$3"} as_lineno_stack=as_lineno_stack=$as_lineno_stack -+ $as_echo "$as_me:${as_lineno-$LINENO}: error: $2" >&$4 - fi -- $as_echo "$as_me: error: $1" >&2 -+ $as_echo "$as_me: error: $2" >&2 - as_fn_exit $as_status - } # as_fn_error - -@@ -17430,16 +17747,16 @@ if (echo >conf$$.file) 2>/dev/null; then - # ... but there are two gotchas: - # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail. - # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable. -- # In both cases, we have to default to `cp -p'. -+ # In both cases, we have to default to `cp -pR'. - ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe || -- as_ln_s='cp -p' -+ as_ln_s='cp -pR' - elif ln conf$$.file conf$$ 2>/dev/null; then - as_ln_s=ln - else -- as_ln_s='cp -p' -+ as_ln_s='cp -pR' - fi - else -- as_ln_s='cp -p' -+ as_ln_s='cp -pR' - fi - rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file - rmdir conf$$.dir 2>/dev/null -@@ -17488,7 +17805,7 @@ $as_echo X"$as_dir" | - test -d "$as_dir" && break - done - test -z "$as_dirs" || eval "mkdir $as_dirs" -- } || test -d "$as_dir" || as_fn_error "cannot create directory $as_dir" -+ } || test -d "$as_dir" || as_fn_error $? "cannot create directory $as_dir" - - - } # as_fn_mkdir_p -@@ -17499,28 +17816,16 @@ else - as_mkdir_p=false - fi - --if test -x / >/dev/null 2>&1; then -- as_test_x='test -x' --else -- if ls -dL / >/dev/null 2>&1; then -- as_ls_L_option=L -- else -- as_ls_L_option= -- fi -- as_test_x=' -- eval sh -c '\'' -- if test -d "$1"; then -- test -d "$1/."; -- else -- case $1 in #( -- -*)set "./$1";; -- esac; -- case `ls -ld'$as_ls_L_option' "$1" 2>/dev/null` in #(( -- ???[sx]*):;;*)false;;esac;fi -- '\'' sh -- ' --fi --as_executable_p=$as_test_x -+ -+# as_fn_executable_p FILE -+# ----------------------- -+# Test if FILE is an executable regular file. -+as_fn_executable_p () -+{ -+ test -f "$1" && test -x "$1" -+} # as_fn_executable_p -+as_test_x='test -x' -+as_executable_p=as_fn_executable_p - - # Sed expression to map a string onto a valid CPP name. - as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'" -@@ -17542,7 +17847,7 @@ cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 - # values after options handling. - ac_log=" - This file was extended by $as_me, which was --generated by GNU Autoconf 2.64. Invocation command line was -+generated by GNU Autoconf 2.69. Invocation command line was - - CONFIG_FILES = $CONFIG_FILES - CONFIG_HEADERS = $CONFIG_HEADERS -@@ -17582,6 +17887,7 @@ Usage: $0 [OPTION]... [TAG]... - - -h, --help print this help, then exit - -V, --version print version number and configuration settings, then exit -+ --config print configuration, then exit - -q, --quiet, --silent - do not print progress messages - -d, --debug don't remove temporary files -@@ -17604,12 +17910,13 @@ Report bugs to the package provider." - - _ACEOF - cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 -+ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`" - ac_cs_version="\\ - config.status --configured by $0, generated by GNU Autoconf 2.64, -- with options \\"`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`\\" -+configured by $0, generated by GNU Autoconf 2.69, -+ with options \\"\$ac_cs_config\\" - --Copyright (C) 2009 Free Software Foundation, Inc. -+Copyright (C) 2012 Free Software Foundation, Inc. - This config.status script is free software; the Free Software Foundation - gives unlimited permission to copy, distribute and modify it." - -@@ -17627,11 +17934,16 @@ ac_need_defaults=: - while test $# != 0 - do - case $1 in -- --*=*) -+ --*=?*) - ac_option=`expr "X$1" : 'X\([^=]*\)='` - ac_optarg=`expr "X$1" : 'X[^=]*=\(.*\)'` - ac_shift=: - ;; -+ --*=) -+ ac_option=`expr "X$1" : 'X\([^=]*\)='` -+ ac_optarg= -+ ac_shift=: -+ ;; - *) - ac_option=$1 - ac_optarg=$2 -@@ -17645,12 +17957,15 @@ do - ac_cs_recheck=: ;; - --version | --versio | --versi | --vers | --ver | --ve | --v | -V ) - $as_echo "$ac_cs_version"; exit ;; -+ --config | --confi | --conf | --con | --co | --c ) -+ $as_echo "$ac_cs_config"; exit ;; - --debug | --debu | --deb | --de | --d | -d ) - debug=: ;; - --file | --fil | --fi | --f ) - $ac_shift - case $ac_optarg in - *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; -+ '') as_fn_error $? "missing file argument" ;; - esac - as_fn_append CONFIG_FILES " '$ac_optarg'" - ac_need_defaults=false;; -@@ -17663,7 +17978,7 @@ do - ac_need_defaults=false;; - --he | --h) - # Conflict between --help and --header -- as_fn_error "ambiguous option: \`$1' -+ as_fn_error $? "ambiguous option: \`$1' - Try \`$0 --help' for more information.";; - --help | --hel | -h ) - $as_echo "$ac_cs_usage"; exit ;; -@@ -17672,7 +17987,7 @@ Try \`$0 --help' for more information.";; - ac_cs_silent=: ;; - - # This is an error. -- -*) as_fn_error "unrecognized option: \`$1' -+ -*) as_fn_error $? "unrecognized option: \`$1' - Try \`$0 --help' for more information." ;; - - *) as_fn_append ac_config_targets " $1" -@@ -17692,7 +18007,7 @@ fi - _ACEOF - cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 - if \$ac_cs_recheck; then -- set X '$SHELL' '$0' $ac_configure_args \$ac_configure_extra_args --no-create --no-recursion -+ set X $SHELL '$0' $ac_configure_args \$ac_configure_extra_args --no-create --no-recursion - shift - \$as_echo "running CONFIG_SHELL=$SHELL \$*" >&6 - CONFIG_SHELL='$SHELL' -@@ -18100,7 +18415,7 @@ do - "Makefile") CONFIG_FILES="$CONFIG_FILES Makefile" ;; - "po/Makefile.in") CONFIG_FILES="$CONFIG_FILES po/Makefile.in:po/Make-in" ;; - -- *) as_fn_error "invalid argument: \`$ac_config_target'" "$LINENO" 5;; -+ *) as_fn_error $? "invalid argument: \`$ac_config_target'" "$LINENO" 5;; - esac - done - -@@ -18123,9 +18438,10 @@ fi - # after its creation but before its name has been assigned to `$tmp'. - $debug || - { -- tmp= -+ tmp= ac_tmp= - trap 'exit_status=$? -- { test -z "$tmp" || test ! -d "$tmp" || rm -fr "$tmp"; } && exit $exit_status -+ : "${ac_tmp:=$tmp}" -+ { test ! -d "$ac_tmp" || rm -fr "$ac_tmp"; } && exit $exit_status - ' 0 - trap 'as_fn_exit 1' 1 2 13 15 - } -@@ -18133,12 +18449,13 @@ $debug || - - { - tmp=`(umask 077 && mktemp -d "./confXXXXXX") 2>/dev/null` && -- test -n "$tmp" && test -d "$tmp" -+ test -d "$tmp" - } || - { - tmp=./conf$$-$RANDOM - (umask 077 && mkdir "$tmp") --} || as_fn_error "cannot create a temporary directory in ." "$LINENO" 5 -+} || as_fn_error $? "cannot create a temporary directory in ." "$LINENO" 5 -+ac_tmp=$tmp - - # Set up the scripts for CONFIG_FILES section. - # No need to generate them if there are no CONFIG_FILES. -@@ -18172,24 +18489,24 @@ if test "x$ac_cr" = x; then - fi - ac_cs_awk_cr=`$AWK 'BEGIN { print "a\rb" }' /dev/null` - if test "$ac_cs_awk_cr" = "a${ac_cr}b"; then -- ac_cs_awk_cr='\r' -+ ac_cs_awk_cr='\\r' - else - ac_cs_awk_cr=$ac_cr - fi - --echo 'BEGIN {' >"$tmp/subs1.awk" && -+echo 'BEGIN {' >"$ac_tmp/subs1.awk" && - _ACEOF - - # Create commands to substitute file output variables. - { - echo "cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1" && -- echo 'cat >>"\$tmp/subs1.awk" <<\\_ACAWK &&' && -+ echo 'cat >>"\$ac_tmp/subs1.awk" <<\\_ACAWK &&' && - echo "$ac_subst_files" | sed 's/.*/F["&"]="$&"/' && - echo "_ACAWK" && - echo "_ACEOF" - } >conf$$files.sh && - . ./conf$$files.sh || -- as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 -+ as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5 - rm -f conf$$files.sh - - { -@@ -18197,18 +18514,18 @@ rm -f conf$$files.sh - echo "$ac_subst_vars" | sed 's/.*/&!$&$ac_delim/' && - echo "_ACEOF" - } >conf$$subs.sh || -- as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 --ac_delim_num=`echo "$ac_subst_vars" | grep -c '$'` -+ as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5 -+ac_delim_num=`echo "$ac_subst_vars" | grep -c '^'` - ac_delim='%!_!# ' - for ac_last_try in false false false false false :; do - . ./conf$$subs.sh || -- as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 -+ as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5 - - ac_delim_n=`sed -n "s/.*$ac_delim\$/X/p" conf$$subs.awk | grep -c X` - if test $ac_delim_n = $ac_delim_num; then - break - elif $ac_last_try; then -- as_fn_error "could not make $CONFIG_STATUS" "$LINENO" 5 -+ as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5 - else - ac_delim="$ac_delim!$ac_delim _$ac_delim!! " - fi -@@ -18216,7 +18533,7 @@ done - rm -f conf$$subs.sh - - cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 --cat >>"\$tmp/subs1.awk" <<\\_ACAWK && -+cat >>"\$ac_tmp/subs1.awk" <<\\_ACAWK && - _ACEOF - sed -n ' - h -@@ -18230,7 +18547,7 @@ s/'"$ac_delim"'$// - t delim - :nl - h --s/\(.\{148\}\).*/\1/ -+s/\(.\{148\}\)..*/\1/ - t more1 - s/["\\]/\\&/g; s/^/"/; s/$/\\n"\\/ - p -@@ -18244,7 +18561,7 @@ s/.\{148\}// - t nl - :delim - h --s/\(.\{148\}\).*/\1/ -+s/\(.\{148\}\)..*/\1/ - t more2 - s/["\\]/\\&/g; s/^/"/; s/$/"/ - p -@@ -18264,7 +18581,7 @@ t delim - rm -f conf$$subs.awk - cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 - _ACAWK --cat >>"\$tmp/subs1.awk" <<_ACAWK && -+cat >>"\$ac_tmp/subs1.awk" <<_ACAWK && - for (key in S) S_is_set[key] = 1 - FS = "" - \$ac_cs_awk_pipe_init -@@ -18302,21 +18619,29 @@ if sed "s/$ac_cr//" < /dev/null > /dev/null 2>&1; then - sed "s/$ac_cr\$//; s/$ac_cr/$ac_cs_awk_cr/g" - else - cat --fi < "$tmp/subs1.awk" > "$tmp/subs.awk" \ -- || as_fn_error "could not setup config files machinery" "$LINENO" 5 -+fi < "$ac_tmp/subs1.awk" > "$ac_tmp/subs.awk" \ -+ || as_fn_error $? "could not setup config files machinery" "$LINENO" 5 - _ACEOF - --# VPATH may cause trouble with some makes, so we remove $(srcdir), --# ${srcdir} and @srcdir@ from VPATH if srcdir is ".", strip leading and -+# VPATH may cause trouble with some makes, so we remove sole $(srcdir), -+# ${srcdir} and @srcdir@ entries from VPATH if srcdir is ".", strip leading and - # trailing colons and then remove the whole line if VPATH becomes empty - # (actually we leave an empty line to preserve line numbers). - if test "x$srcdir" = x.; then -- ac_vpsub='/^[ ]*VPATH[ ]*=/{ --s/:*\$(srcdir):*/:/ --s/:*\${srcdir}:*/:/ --s/:*@srcdir@:*/:/ --s/^\([^=]*=[ ]*\):*/\1/ -+ ac_vpsub='/^[ ]*VPATH[ ]*=[ ]*/{ -+h -+s/// -+s/^/:/ -+s/[ ]*$/:/ -+s/:\$(srcdir):/:/g -+s/:\${srcdir}:/:/g -+s/:@srcdir@:/:/g -+s/^:*// - s/:*$// -+x -+s/\(=[ ]*\).*/\1/ -+G -+s/\n// - s/^[^=]*=[ ]*$// - }' - fi -@@ -18328,7 +18653,7 @@ fi # test -n "$CONFIG_FILES" - # No need to generate them if there are no CONFIG_HEADERS. - # This happens for instance with `./config.status Makefile'. - if test -n "$CONFIG_HEADERS"; then --cat >"$tmp/defines.awk" <<\_ACAWK || -+cat >"$ac_tmp/defines.awk" <<\_ACAWK || - BEGIN { - _ACEOF - -@@ -18340,11 +18665,11 @@ _ACEOF - # handling of long lines. - ac_delim='%!_!# ' - for ac_last_try in false false :; do -- ac_t=`sed -n "/$ac_delim/p" confdefs.h` -- if test -z "$ac_t"; then -+ ac_tt=`sed -n "/$ac_delim/p" confdefs.h` -+ if test -z "$ac_tt"; then - break - elif $ac_last_try; then -- as_fn_error "could not make $CONFIG_HEADERS" "$LINENO" 5 -+ as_fn_error $? "could not make $CONFIG_HEADERS" "$LINENO" 5 - else - ac_delim="$ac_delim!$ac_delim _$ac_delim!! " - fi -@@ -18429,7 +18754,7 @@ cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 - _ACAWK - _ACEOF - cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 -- as_fn_error "could not setup config headers machinery" "$LINENO" 5 -+ as_fn_error $? "could not setup config headers machinery" "$LINENO" 5 - fi # test -n "$CONFIG_HEADERS" - - -@@ -18442,7 +18767,7 @@ do - esac - case $ac_mode$ac_tag in - :[FHL]*:*);; -- :L* | :C*:*) as_fn_error "invalid tag \`$ac_tag'" "$LINENO" 5;; -+ :L* | :C*:*) as_fn_error $? "invalid tag \`$ac_tag'" "$LINENO" 5;; - :[FH]-) ac_tag=-:-;; - :[FH]*) ac_tag=$ac_tag:$ac_tag.in;; - esac -@@ -18461,7 +18786,7 @@ do - for ac_f - do - case $ac_f in -- -) ac_f="$tmp/stdin";; -+ -) ac_f="$ac_tmp/stdin";; - *) # Look for the file first in the build tree, then in the source tree - # (if the path is not absolute). The absolute path cannot be DOS-style, - # because $ac_f cannot contain `:'. -@@ -18470,7 +18795,7 @@ do - [\\/$]*) false;; - *) test -f "$srcdir/$ac_f" && ac_f="$srcdir/$ac_f";; - esac || -- as_fn_error "cannot find input file: \`$ac_f'" "$LINENO" 5;; -+ as_fn_error 1 "cannot find input file: \`$ac_f'" "$LINENO" 5;; - esac - case $ac_f in *\'*) ac_f=`$as_echo "$ac_f" | sed "s/'/'\\\\\\\\''/g"`;; esac - as_fn_append ac_file_inputs " '$ac_f'" -@@ -18496,8 +18821,8 @@ $as_echo "$as_me: creating $ac_file" >&6;} - esac - - case $ac_tag in -- *:-:* | *:-) cat >"$tmp/stdin" \ -- || as_fn_error "could not create $ac_file" "$LINENO" 5 ;; -+ *:-:* | *:-) cat >"$ac_tmp/stdin" \ -+ || as_fn_error $? "could not create $ac_file" "$LINENO" 5 ;; - esac - ;; - esac -@@ -18635,26 +18960,27 @@ $ac_datarootdir_hack - " - eval sed \"\$ac_sed_extra\" "$ac_file_inputs" | - if $ac_cs_awk_getline; then -- $AWK -f "$tmp/subs.awk" -+ $AWK -f "$ac_tmp/subs.awk" - else -- $AWK -f "$tmp/subs.awk" | $SHELL --fi >$tmp/out \ -- || as_fn_error "could not create $ac_file" "$LINENO" 5 -+ $AWK -f "$ac_tmp/subs.awk" | $SHELL -+fi \ -+ >$ac_tmp/out || as_fn_error $? "could not create $ac_file" "$LINENO" 5 - - test -z "$ac_datarootdir_hack$ac_datarootdir_seen" && -- { ac_out=`sed -n '/\${datarootdir}/p' "$tmp/out"`; test -n "$ac_out"; } && -- { ac_out=`sed -n '/^[ ]*datarootdir[ ]*:*=/p' "$tmp/out"`; test -z "$ac_out"; } && -+ { ac_out=`sed -n '/\${datarootdir}/p' "$ac_tmp/out"`; test -n "$ac_out"; } && -+ { ac_out=`sed -n '/^[ ]*datarootdir[ ]*:*=/p' \ -+ "$ac_tmp/out"`; test -z "$ac_out"; } && - { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file contains a reference to the variable \`datarootdir' --which seems to be undefined. Please make sure it is defined." >&5 -+which seems to be undefined. Please make sure it is defined" >&5 - $as_echo "$as_me: WARNING: $ac_file contains a reference to the variable \`datarootdir' --which seems to be undefined. Please make sure it is defined." >&2;} -+which seems to be undefined. Please make sure it is defined" >&2;} - -- rm -f "$tmp/stdin" -+ rm -f "$ac_tmp/stdin" - case $ac_file in -- -) cat "$tmp/out" && rm -f "$tmp/out";; -- *) rm -f "$ac_file" && mv "$tmp/out" "$ac_file";; -+ -) cat "$ac_tmp/out" && rm -f "$ac_tmp/out";; -+ *) rm -f "$ac_file" && mv "$ac_tmp/out" "$ac_file";; - esac \ -- || as_fn_error "could not create $ac_file" "$LINENO" 5 -+ || as_fn_error $? "could not create $ac_file" "$LINENO" 5 - ;; - :H) - # -@@ -18663,21 +18989,21 @@ which seems to be undefined. Please make sure it is defined." >&2;} - if test x"$ac_file" != x-; then - { - $as_echo "/* $configure_input */" \ -- && eval '$AWK -f "$tmp/defines.awk"' "$ac_file_inputs" -- } >"$tmp/config.h" \ -- || as_fn_error "could not create $ac_file" "$LINENO" 5 -- if diff "$ac_file" "$tmp/config.h" >/dev/null 2>&1; then -+ && eval '$AWK -f "$ac_tmp/defines.awk"' "$ac_file_inputs" -+ } >"$ac_tmp/config.h" \ -+ || as_fn_error $? "could not create $ac_file" "$LINENO" 5 -+ if diff "$ac_file" "$ac_tmp/config.h" >/dev/null 2>&1; then - { $as_echo "$as_me:${as_lineno-$LINENO}: $ac_file is unchanged" >&5 - $as_echo "$as_me: $ac_file is unchanged" >&6;} - else - rm -f "$ac_file" -- mv "$tmp/config.h" "$ac_file" \ -- || as_fn_error "could not create $ac_file" "$LINENO" 5 -+ mv "$ac_tmp/config.h" "$ac_file" \ -+ || as_fn_error $? "could not create $ac_file" "$LINENO" 5 - fi - else - $as_echo "/* $configure_input */" \ -- && eval '$AWK -f "$tmp/defines.awk"' "$ac_file_inputs" \ -- || as_fn_error "could not create -" "$LINENO" 5 -+ && eval '$AWK -f "$ac_tmp/defines.awk"' "$ac_file_inputs" \ -+ || as_fn_error $? "could not create -" "$LINENO" 5 - fi - # Compute "$ac_file"'s index in $config_headers. - _am_arg="$ac_file" -@@ -18723,7 +19049,7 @@ $as_echo "$as_me: executing $ac_file commands" >&6;} - - case $ac_file$ac_mode in - "depfiles":C) test x"$AMDEP_TRUE" != x"" || { -- # Autoconf 2.62 quotes --file arguments for eval, but not when files -+ # Older Autoconf quotes --file arguments for eval, but not when files - # are listed without --file. Let's play safe and only enable the eval - # if we detect the quoting. - case $CONFIG_FILES in -@@ -18736,7 +19062,7 @@ $as_echo "$as_me: executing $ac_file commands" >&6;} - # Strip MF so we end up with the name of the file. - mf=`echo "$mf" | sed -e 's/:.*$//'` - # Check whether this is an Automake generated Makefile or not. -- # We used to match only the files named `Makefile.in', but -+ # We used to match only the files named 'Makefile.in', but - # some people rename them; so instead we look at the file content. - # Grep'ing the first line is not enough: some people post-process - # each Makefile.in and add a new line on top of each file to say so. -@@ -18770,21 +19096,19 @@ $as_echo X"$mf" | - continue - fi - # Extract the definition of DEPDIR, am__include, and am__quote -- # from the Makefile without running `make'. -+ # from the Makefile without running 'make'. - DEPDIR=`sed -n 's/^DEPDIR = //p' < "$mf"` - test -z "$DEPDIR" && continue - am__include=`sed -n 's/^am__include = //p' < "$mf"` -- test -z "am__include" && continue -+ test -z "$am__include" && continue - am__quote=`sed -n 's/^am__quote = //p' < "$mf"` -- # When using ansi2knr, U may be empty or an underscore; expand it -- U=`sed -n 's/^U = //p' < "$mf"` - # Find all dependency output files, they are included files with - # $(DEPDIR) in their names. We invoke sed twice because it is the - # simplest approach to changing $(DEPDIR) to its actual value in the - # expansion. - for file in `sed -n " - s/^$am__include $am__quote\(.*(DEPDIR).*\)$am__quote"'$/\1/p' <"$mf" | \ -- sed -e 's/\$(DEPDIR)/'"$DEPDIR"'/g' -e 's/\$U/'"$U"'/g'`; do -+ sed -e 's/\$(DEPDIR)/'"$DEPDIR"'/g'`; do - # Make sure the directory exists. - test -f "$dirpart/$file" && continue - fdir=`$as_dirname -- "$file" || -@@ -19738,7 +20062,7 @@ _ACEOF - ac_clean_files=$ac_clean_files_save - - test $ac_write_fail = 0 || -- as_fn_error "write failure creating $CONFIG_STATUS" "$LINENO" 5 -+ as_fn_error $? "write failure creating $CONFIG_STATUS" "$LINENO" 5 - - - # configure is writing to config.log, and then calls config.status. -@@ -19759,7 +20083,7 @@ if test "$no_create" != yes; then - exec 5>>config.log - # Use ||, not &&, to avoid exiting from the if with $? = 1, which - # would make configure fail if this is the last instruction. -- $ac_cs_success || as_fn_exit $? -+ $ac_cs_success || as_fn_exit 1 - fi - if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then - { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5 diff --git a/ld/configure.tgt b/ld/configure.tgt -index c50730b..0811e90 100644 +index c50730b..433fdff 100644 --- a/ld/configure.tgt +++ b/ld/configure.tgt @@ -138,7 +138,7 @@ arm*-*-uclinux*) targ_emul=armelf_linux @@ -39957,36 +33445,17 @@ index c50730b..0811e90 100644 arm*-*-conix*) targ_emul=armelf ;; avr-*-*) targ_emul=avr2 - targ_extra_emuls="avr1 avr25 avr3 avr31 avr35 avr4 avr5 avr51 avr6 avrxmega1 avrxmega2 avrxmega3 avrxmega4 avrxmega5 avrxmega6 avrxmega7" -+ targ_extra_emuls="avr1 avr25 avr3 avr31 avr35 avr4 avr5 avr51 avr6 avr7 avrxmega1 avrxmega2 avrxmega3 avrxmega4 avrxmega5 avrxmega6 avrxmega7 avrtiny" ++ targ_extra_emuls="avr1 avr25 avr3 avr31 avr35 avr4 avr5 avr51 avr6 avrxmega1 avrxmega2 avrxmega3 avrxmega4 avrxmega5 avrxmega6 avrxmega7 avrtiny" ;; bfin-*-elf) targ_emul=elf32bfin; targ_extra_emuls="elf32bfinfd" -diff --git a/ld/emulparams/avr7.sh b/ld/emulparams/avr7.sh -new file mode 100644 -index 0000000..23a54e9 ---- /dev/null -+++ b/ld/emulparams/avr7.sh -@@ -0,0 +1,13 @@ -+ARCH=avr:7 -+MACHINE= -+SCRIPT_NAME=avr7 -+OUTPUT_FORMAT="elf32-avr" -+MAXPAGESIZE=1 -+EMBEDDED=yes -+TEMPLATE_NAME=elf32 -+ -+TEXT_ORIGIN=0x8000 -+TEXT_LENGTH=20K -+DATA_ORIGIN=0x800200 -+DATA_LENGTH=0x400 -+EXTRA_EM_FILE=avrelf diff --git a/ld/emulparams/avrtiny.sh b/ld/emulparams/avrtiny.sh new file mode 100644 -index 0000000..86a9f93 +index 0000000..b4ed14b --- /dev/null +++ b/ld/emulparams/avrtiny.sh @@ -0,0 +1,13 @@ -+ARCH=avr:90 ++ARCH=avr:100 +MACHINE= +SCRIPT_NAME=avrtiny +OUTPUT_FORMAT="elf32-avr" @@ -40000,7 +33469,7 @@ index 0000000..86a9f93 +DATA_LENGTH=0x100 +EXTRA_EM_FILE=avrelf diff --git a/ld/scripttempl/avr.sc b/ld/scripttempl/avr.sc -index bfce5fe..58ee72a 100644 +index bfce5fe..a3823c6 100644 --- a/ld/scripttempl/avr.sc +++ b/ld/scripttempl/avr.sc @@ -10,6 +10,7 @@ MEMORY @@ -40011,7 +33480,7 @@ index bfce5fe..58ee72a 100644 } SECTIONS -@@ -163,7 +164,7 @@ SECTIONS +@@ -163,13 +164,10 @@ SECTIONS ${RELOCATING+ _etext = . ; } } ${RELOCATING+ > text} @@ -40019,17 +33488,27 @@ index bfce5fe..58ee72a 100644 + .data ${RELOCATING-0} : { ${RELOCATING+ PROVIDE (__data_start = .) ; } - /* --gc-sections will delete empty .data. This leads to wrong start -@@ -177,7 +178,7 @@ SECTIONS +- /* --gc-sections will delete empty .data. This leads to wrong start +- addresses for subsequent sections because -Tdata= from the command +- line will have no effect, see PR13697. Thus, keep .data */ +- KEEP (*(.data)) ++ *(.data) + ${RELOCATING+ *(.data*)} + *(.rodata) /* We need to include .rodata here if gcc is used */ + ${RELOCATING+ *(.rodata*)} /* with -fdata-sections. */ +@@ -177,9 +175,9 @@ SECTIONS ${RELOCATING+. = ALIGN(2);} ${RELOCATING+ _edata = . ; } ${RELOCATING+ PROVIDE (__data_end = .) ; } - } ${RELOCATING+ > data} + } ${RELOCATING+ > data ${RELOCATING+AT> text}} - .bss ${RELOCATING-0} :${RELOCATING+ AT (ADDR (.bss))} +- .bss ${RELOCATING-0} :${RELOCATING+ AT (ADDR (.bss))} ++ .bss ${RELOCATING+ ADDR(.data) + SIZEOF (.data)} ${RELOCATING-0} :${RELOCATING+ AT (ADDR (.bss))} { -@@ -226,6 +227,11 @@ SECTIONS + ${RELOCATING+ PROVIDE (__bss_start = .) ; } + *(.bss) +@@ -226,6 +224,11 @@ SECTIONS KEEP(*(.signature*)) } ${RELOCATING+ > signature} @@ -40041,275 +33520,9 @@ index bfce5fe..58ee72a 100644 /* Stabs debugging sections. */ .stab 0 : { *(.stab) } .stabstr 0 : { *(.stabstr) } -diff --git a/ld/scripttempl/avr7.sc b/ld/scripttempl/avr7.sc -new file mode 100644 -index 0000000..9e6f897 ---- /dev/null -+++ b/ld/scripttempl/avr7.sc -@@ -0,0 +1,260 @@ -+cat < text} -+ -+ .data ${RELOCATING-0} : -+ { -+ ${RELOCATING+ PROVIDE (__data_start = .) ; } -+ KEEP (*(.data)) -+ *(.data*) -+ *(.rodata) /* We need to include .rodata here if gcc is used */ -+ *(.rodata*) /* with -fdata-sections. */ -+ *(.gnu.linkonce.d*) -+ ${RELOCATING+. = ALIGN(2);} -+ ${RELOCATING+ _edata = . ; } -+ ${RELOCATING+ PROVIDE (__data_end = .) ; } -+ } ${RELOCATING+ > data ${RELOCATING+AT> text}} -+ -+ .bss ${RELOCATING-0} :${RELOCATING+ AT (ADDR (.bss))} -+ { -+ ${RELOCATING+ PROVIDE (__bss_start = .) ; } -+ *(.bss) -+ *(.bss*) -+ *(COMMON) -+ ${RELOCATING+ PROVIDE (__bss_end = .) ; } -+ } ${RELOCATING+ > data} -+ -+ ${RELOCATING+ __data_load_start = LOADADDR(.data); } -+ ${RELOCATING+ __data_load_end = __data_load_start + SIZEOF(.data); } -+ -+ /* Global data not cleared after reset. */ -+ .noinit ${RELOCATING-0}: -+ { -+ ${RELOCATING+ PROVIDE (__noinit_start = .) ; } -+ *(.noinit*) -+ ${RELOCATING+ PROVIDE (__noinit_end = .) ; } -+ ${RELOCATING+ _end = . ; } -+ ${RELOCATING+ PROVIDE (__heap_start = .) ; } -+ } ${RELOCATING+ > data} -+ -+ .eeprom ${RELOCATING-0}: -+ { -+ KEEP (*(.eeprom*)) -+ ${RELOCATING+ __eeprom_end = . ; } -+ } ${RELOCATING+ > eeprom} -+ -+ .fuse ${RELOCATING-0}: -+ { -+ KEEP(*(.fuse)) -+ KEEP(*(.lfuse)) -+ KEEP(*(.hfuse)) -+ KEEP(*(.efuse)) -+ } ${RELOCATING+ > fuse} -+ -+ .lock ${RELOCATING-0}: -+ { -+ KEEP(*(.lock*)) -+ } ${RELOCATING+ > lock} -+ -+ .signature ${RELOCATING-0}: -+ { -+ KEEP(*(.signature*)) -+ } ${RELOCATING+ > signature} -+ -+ /* Stabs debugging sections. */ -+ .stab 0 : { *(.stab) } -+ .stabstr 0 : { *(.stabstr) } -+ .stab.excl 0 : { *(.stab.excl) } -+ .stab.exclstr 0 : { *(.stab.exclstr) } -+ .stab.index 0 : { *(.stab.index) } -+ .stab.indexstr 0 : { *(.stab.indexstr) } -+ .comment 0 : { *(.comment) } -+ -+ /* DWARF debug sections. -+ Symbols in the DWARF debugging sections are relative to the beginning -+ of the section so we begin them at 0. */ -+ -+ /* DWARF 1 */ -+ .debug 0 : { *(.debug) } -+ .line 0 : { *(.line) } -+ -+ /* GNU DWARF 1 extensions */ -+ .debug_srcinfo 0 : { *(.debug_srcinfo) } -+ .debug_sfnames 0 : { *(.debug_sfnames) } -+ -+ /* DWARF 1.1 and DWARF 2 */ -+ .debug_aranges 0 : { *(.debug_aranges) } -+ .debug_pubnames 0 : { *(.debug_pubnames) } -+ -+ /* DWARF 2 */ -+ .debug_info 0 : { *(.debug_info) *(.gnu.linkonce.wi.*) } -+ .debug_abbrev 0 : { *(.debug_abbrev) } -+ .debug_line 0 : { *(.debug_line) } -+ .debug_frame 0 : { *(.debug_frame) } -+ .debug_str 0 : { *(.debug_str) } -+ .debug_loc 0 : { *(.debug_loc) } -+ .debug_macinfo 0 : { *(.debug_macinfo) } -+} -+EOF -+ diff --git a/ld/scripttempl/avrtiny.sc b/ld/scripttempl/avrtiny.sc new file mode 100644 -index 0000000..87f3823 +index 0000000..910ec51 --- /dev/null +++ b/ld/scripttempl/avrtiny.sc @@ -0,0 +1,255 @@ @@ -40325,7 +33538,7 @@ index 0000000..87f3823 + /* Provide offsets for config, lock and signature to match + production file format. Ignore offsets in datasheet. */ + -+ config(rw!x) : ORIGIN = 0x820000, LENGTH = 2 ++ config (rw!x) : ORIGIN = 0x820000, LENGTH = 2 + lock (rw!x) : ORIGIN = 0x830000, LENGTH = 2 + signature (rw!x) : ORIGIN = 0x840000, LENGTH = 4 +} @@ -40495,7 +33708,7 @@ index 0000000..87f3823 + ${RELOCATING+ PROVIDE (__data_end = .) ; } + } ${RELOCATING+ > data ${RELOCATING+AT> text}} + -+ .bss ${RELOCATING-0} :${RELOCATING+ AT (ADDR (.bss))} ++ .bss ${RELOCATING+ ADDR(.data) + SIZEOF (.data)} ${RELOCATING-0} :${RELOCATING+ AT (ADDR (.bss))} + { + ${RELOCATING+ PROVIDE (__bss_start = .) ; } + *(.bss) diff --git a/binutils.build.bash b/binutils.build.bash index a39c99a..0c887eb 100755 --- a/binutils.build.bash +++ b/binutils.build.bash @@ -17,7 +17,7 @@ then wget http://mirror.switch.ch/ftp/mirror/gnu/binutils/binutils-2.24.tar.bz2 fi -tar xfjv binutils-2.24.tar.bz2 +tar xfv binutils-2.24.tar.bz2 cd binutils-2.24 for p in ../binutils-patches/*.patch; do echo Applying $p; patch -p1 < $p; done @@ -50,8 +50,6 @@ if [ -z "$MAKE_JOBS" ]; then MAKE_JOBS="2" fi -nice -n 10 make -j $MAKE_JOBS all-bfd TARGET-bfd=headers -rm bfd/Makefile nice -n 10 make -j $MAKE_JOBS configure-host nice -n 10 make -j $MAKE_JOBS all diff --git a/clean.bash b/clean.bash index e9a7273..f909e53 100755 --- a/clean.bash +++ b/clean.bash @@ -2,7 +2,7 @@ rm -rf autoconf-2.64 automake-1.11.1 -rm -rf gcc-4.8.1 gmp-5.0.2 mpc-0.9 mpfr-3.0.0 binutils-2.24 avr-libc-1.8.0 avr8-headers-6.2.0.334 avrdude-6.0.1 libusb-1.0.18 libusb-compat-0.1.5 gdb-7.7 *-build +rm -rf gcc-4.8.1 gmp-5.0.2 mpc-0.9 mpfr-3.0.0 binutils-2.24 avr-libc-1.8.0 avr8-headers-6.2.0.469 avrdude-6.0.1 libusb-1.0.18 libusb-compat-0.1.5 gdb-7.8 *-build rm -rf objdir/{info,man,share} diff --git a/gcc-patches/00-gcc-4.8.1-atmel.patch b/gcc-patches/00-gcc-4.8.1-atmel.patch index b2c1298..fea2874 100644 --- a/gcc-patches/00-gcc-4.8.1-atmel.patch +++ b/gcc-patches/00-gcc-4.8.1-atmel.patch @@ -1,7 +1,3 @@ -diff --git a/--exclude-vcs b/--exclude-vcs -new file mode 100644 -index 0000000..9a0ffa9 -Binary files /dev/null and b/--exclude-vcs differ diff --git a/gcc/ChangeLog.AVR b/gcc/ChangeLog.AVR new file mode 100644 index 0000000..ebc64d8 @@ -602,6 +598,31 @@ index ddb6d39..9efa48d 100644 if (last) { +diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c +index 5acc42d..66abe66 100644 +--- a/gcc/cfgexpand.c ++++ b/gcc/cfgexpand.c +@@ -2889,10 +2889,7 @@ expand_debug_expr (tree exp) + op0 = plus_constant (inner_mode, op0, INTVAL (op1)); + } + +- if (POINTER_TYPE_P (TREE_TYPE (exp))) +- as = TYPE_ADDR_SPACE (TREE_TYPE (TREE_TYPE (exp))); +- else +- as = ADDR_SPACE_GENERIC; ++ as = TYPE_ADDR_SPACE (TREE_TYPE (TREE_TYPE (TREE_OPERAND (exp, 0)))); + + op0 = convert_debug_memory_address (targetm.addr_space.address_mode (as), + op0, as); +@@ -3410,7 +3407,7 @@ expand_debug_expr (tree exp) + return NULL; + } + +- as = TYPE_ADDR_SPACE (TREE_TYPE (exp)); ++ as = TYPE_ADDR_SPACE (TREE_TYPE (TREE_TYPE (exp))); + op0 = convert_debug_memory_address (mode, XEXP (op0, 0), as); + + return op0; diff --git a/gcc/common.opt b/gcc/common.opt index bdbd3b6..f025331 100644 --- a/gcc/common.opt @@ -622,19 +643,18 @@ index bdbd3b6..f025331 100644 Common Joined UInteger Var(dwarf_version) Init(4) Negative(gstabs) Generate debug information in DWARF v2 (or later) format diff --git a/gcc/config/avr/avr-arch.h b/gcc/config/avr/avr-arch.h -index 27cea73..30a6ce5 100644 +index 27cea73..646d9fb 100644 --- a/gcc/config/avr/avr-arch.h +++ b/gcc/config/avr/avr-arch.h -@@ -35,6 +35,8 @@ enum avr_arch +@@ -35,6 +35,7 @@ enum avr_arch ARCH_AVR5, ARCH_AVR51, ARCH_AVR6, -+ ARCH_AVR7, + ARCH_AVRTINY, ARCH_AVRXMEGA2, ARCH_AVRXMEGA4, ARCH_AVRXMEGA5, -@@ -75,6 +77,9 @@ typedef struct +@@ -75,6 +76,9 @@ typedef struct and thus also the RAMPX, RAMPY and RAMPZ registers. */ int have_rampd; @@ -644,7 +664,7 @@ index 27cea73..30a6ce5 100644 /* Default start of data section address for architecture. */ int default_data_section_start; -@@ -100,32 +105,12 @@ typedef struct +@@ -100,35 +104,18 @@ typedef struct /* Index in avr_arch_types[]. */ enum avr_arch arch; @@ -680,7 +700,13 @@ index 27cea73..30a6ce5 100644 /* Start of data section. */ int data_section_start; -@@ -136,6 +121,42 @@ typedef struct ++ /* Start of text section. */ ++ int text_section_start; ++ + /* Number of 64k segments in the flash. */ + int n_flash; + +@@ -136,6 +123,42 @@ typedef struct const char *const library_name; } avr_mcu_t; @@ -724,10 +750,23 @@ index 27cea73..30a6ce5 100644 typedef struct diff --git a/gcc/config/avr/avr-c.c b/gcc/config/avr/avr-c.c -index 4e64405..a0b5f10 100644 +index 4e64405..a36656b 100644 --- a/gcc/config/avr/avr-c.c +++ b/gcc/config/avr/avr-c.c -@@ -322,6 +322,23 @@ avr_cpu_cpp_builtins (struct cpp_reader *pfile) +@@ -298,7 +298,11 @@ avr_cpu_cpp_builtins (struct cpp_reader *pfile) + if (avr_current_arch->macro) + cpp_define_formatted (pfile, "__AVR_ARCH__=%s", avr_current_arch->macro); + if (avr_current_device->macro) +- cpp_define (pfile, avr_current_device->macro); ++ { ++ cpp_define (pfile, avr_current_device->macro); ++ cpp_define_formatted (pfile, "__AVR_DEVICE_NAME__=%s", ++ avr_current_device->name); ++ } + if (AVR_HAVE_RAMPD) cpp_define (pfile, "__AVR_HAVE_RAMPD__"); + if (AVR_HAVE_RAMPX) cpp_define (pfile, "__AVR_HAVE_RAMPX__"); + if (AVR_HAVE_RAMPY) cpp_define (pfile, "__AVR_HAVE_RAMPY__"); +@@ -322,6 +326,23 @@ avr_cpu_cpp_builtins (struct cpp_reader *pfile) } if (AVR_XMEGA) cpp_define (pfile, "__AVR_XMEGA__"); @@ -751,7 +790,7 @@ index 4e64405..a0b5f10 100644 if (avr_current_arch->have_eijmp_eicall) { cpp_define (pfile, "__AVR_HAVE_EIJMP_EICALL__"); -@@ -346,7 +363,7 @@ avr_cpu_cpp_builtins (struct cpp_reader *pfile) +@@ -346,7 +367,7 @@ avr_cpu_cpp_builtins (struct cpp_reader *pfile) if (TARGET_NO_INTERRUPTS) cpp_define (pfile, "__NO_INTERRUPTS__"); @@ -760,7 +799,7 @@ index 4e64405..a0b5f10 100644 { cpp_define (pfile, "__AVR_ERRATA_SKIP__"); -@@ -354,6 +371,9 @@ avr_cpu_cpp_builtins (struct cpp_reader *pfile) +@@ -354,6 +375,9 @@ avr_cpu_cpp_builtins (struct cpp_reader *pfile) cpp_define (pfile, "__AVR_ERRATA_SKIP_JMP_CALL__"); } @@ -771,10 +810,10 @@ index 4e64405..a0b5f10 100644 avr_current_arch->sfr_offset); diff --git a/gcc/config/avr/avr-devices.c b/gcc/config/avr/avr-devices.c -index 48a9523..57617cc 100644 +index 48a9523..95e9b1f 100644 --- a/gcc/config/avr/avr-devices.c +++ b/gcc/config/avr/avr-devices.c -@@ -31,29 +31,31 @@ const avr_arch_t +@@ -31,29 +31,30 @@ const avr_arch_t avr_arch_types[] = { /* unknown device specified */ @@ -811,7 +850,6 @@ index 48a9523..57617cc 100644 + { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0x0060, 32, "5", "avr5" }, + { 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0x0060, 32, "51", "avr51" }, + { 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0x0060, 32, "6", "avr6" }, -+ { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0x0200, 32, "7", "avr7" }, - { 0, 1, 1, 1, 0, 0, 0, 1, 0, 0x2000, 0, "102", "avrxmega2" }, - { 0, 1, 1, 1, 1, 1, 0, 1, 0, 0x2000, 0, "104", "avrxmega4" }, @@ -827,31 +865,29 @@ index 48a9523..57617cc 100644 }; const avr_arch_info_t -@@ -85,6 +87,11 @@ avr_texinfo[] = +@@ -85,6 +86,9 @@ avr_texinfo[] = { ARCH_AVR6, "``Enhanced'' devices with 3-byte PC, i.e.@: with more than 128@tie{}KiB " "of program memory." }, -+ { ARCH_AVR7, -+ "``Enhanced'' devices with 20@tie{}KiB of program memory starts at 0x8000."}, + { ARCH_AVRTINY, + "``TINY'' Tiny core devices with 512@tie{}B up to 4@tie{}KiB of " + "program memory." }, { ARCH_AVRXMEGA2, "``XMEGA'' devices with more than 8@tie{}KiB and up to 64@tie{}KiB " "of program memory." }, -@@ -104,11 +111,11 @@ avr_texinfo[] = +@@ -104,11 +108,11 @@ avr_texinfo[] = const avr_mcu_t avr_mcu_types[] = { -#define AVR_MCU(NAME, ARCH, MACRO, SP8, ERR_SKIP, DATA_SEC, N_FLASH, LIBNAME)\ - { NAME, ARCH, MACRO, SP8, ERR_SKIP, DATA_SEC, N_FLASH, LIBNAME }, -+#define AVR_MCU(NAME, ARCH, DEV_ATTRIBUTE, MACRO, DATA_SEC, N_FLASH, LIBNAME)\ -+ { NAME, ARCH, DEV_ATTRIBUTE, MACRO, DATA_SEC, N_FLASH, LIBNAME }, ++#define AVR_MCU(NAME, ARCH, DEV_ATTRIBUTE, MACRO, DATA_SEC, TEXT_SEC, N_FLASH, LIBNAME)\ ++ { NAME, ARCH, DEV_ATTRIBUTE, MACRO, DATA_SEC, TEXT_SEC, N_FLASH, LIBNAME }, #include "avr-mcus.def" #undef AVR_MCU /* End of list. */ - { NULL, ARCH_UNKNOWN, NULL, 0, 0, 0, 0, NULL } -+ { NULL, ARCH_UNKNOWN, AVR_ISA_NONE, NULL, 0, 0, NULL } ++ { NULL, ARCH_UNKNOWN, AVR_ISA_NONE, NULL, 0, 0, 0, NULL } }; diff --git a/gcc/config/avr/avr-fixed.md b/gcc/config/avr/avr-fixed.md @@ -919,16 +955,16 @@ index 7d9b525..b2f0b9a 100644 ;; "*roundqq3.libgcc" "*rounduqq3.libgcc" diff --git a/gcc/config/avr/avr-mcus.def b/gcc/config/avr/avr-mcus.def -index 2a730ac..5797b9c 100644 +index 2a730ac..b9a7b8b 100644 --- a/gcc/config/avr/avr-mcus.def +++ b/gcc/config/avr/avr-mcus.def -@@ -33,305 +33,311 @@ +@@ -33,305 +33,314 @@ Before including this file, define a macro: - AVR_MCU (NAME, ARCH, MACRO, SHORT_SP, ERRATA_SKIP, DATA_SEC, N_FLASH, - LIBRARY_NAME) -+ AVR_MCU (NAME, ARCH, DEV_ATTRIBUTE, MACRO, DATA_SEC, N_FLASH, LIBRARY_NAME) ++ AVR_MCU (NAME, ARCH, DEV_ATTRIBUTE, MACRO, DATA_SEC, TEXT_SEC, N_FLASH, LIBRARY_NAME) where the arguments are the fields of avr_mcu_t: @@ -952,10 +988,11 @@ index 2a730ac..5797b9c 100644 + DATA_SEC First address of SRAM, used in -Tdata= by the driver. - DATA_SEC First address of SRAM, used in -Tdata= by the driver. -+ N_FLASH Number of 64 KiB flash segments, rounded up. ++ TEXT_SEC First address of Flash, used in -Text= by the driver. - N_FLASH Number of 64 KiB flash segments, rounded up. -- ++ N_FLASH Number of 64 KiB flash segments, rounded up. + - LIBRARY_NAME Used by the driver to linke startup code from avr-libc - as of crt.o + LIBRARY_NAME Used by the driver to linke startup code from avr-libc @@ -1174,220 +1211,221 @@ index 2a730ac..5797b9c 100644 -AVR_MCU ("atmega2560", ARCH_AVR6, "__AVR_ATmega2560__", 0, 0, 0x0200, 4, "m2560") -AVR_MCU ("atmega2561", ARCH_AVR6, "__AVR_ATmega2561__", 0, 0, 0x0200, 4, "m2561") +/* Classic, <= 8K, 2-byte PC. */ -+AVR_MCU ("avr2", ARCH_AVR2, AVR_ERRATA_SKIP, NULL, 0x0060, 6, "s8515") -+AVR_MCU ("at90s2313", ARCH_AVR2, AVR_SHORT_SP, "__AVR_AT90S2313__", 0x0060, 1, "s2313") -+AVR_MCU ("at90s2323", ARCH_AVR2, AVR_SHORT_SP, "__AVR_AT90S2323__", 0x0060, 1, "s2323") -+AVR_MCU ("at90s2333", ARCH_AVR2, AVR_SHORT_SP, "__AVR_AT90S2333__", 0x0060, 1, "s2333") -+AVR_MCU ("at90s2343", ARCH_AVR2, AVR_SHORT_SP, "__AVR_AT90S2343__", 0x0060, 1, "s2343") -+AVR_MCU ("attiny22", ARCH_AVR2, AVR_SHORT_SP, "__AVR_ATtiny22__", 0x0060, 1, "tn22") -+AVR_MCU ("attiny26", ARCH_AVR2, AVR_SHORT_SP, "__AVR_ATtiny26__", 0x0060, 1, "tn26") -+AVR_MCU ("at90s4414", ARCH_AVR2, AVR_ISA_NONE, "__AVR_AT90S4414__", 0x0060, 1, "s4414") -+AVR_MCU ("at90s4433", ARCH_AVR2, AVR_SHORT_SP, "__AVR_AT90S4433__", 0x0060, 1, "s4433") -+AVR_MCU ("at90s4434", ARCH_AVR2, AVR_ISA_NONE, "__AVR_AT90S4434__", 0x0060, 1, "s4434") -+AVR_MCU ("at90s8515", ARCH_AVR2, AVR_ERRATA_SKIP, "__AVR_AT90S8515__", 0x0060, 1, "s8515") -+AVR_MCU ("at90c8534", ARCH_AVR2, AVR_ISA_NONE, "__AVR_AT90C8534__", 0x0060, 1, "c8534") -+AVR_MCU ("at90s8535", ARCH_AVR2, AVR_ISA_NONE, "__AVR_AT90S8535__", 0x0060, 1, "s8535") ++AVR_MCU ("avr2", ARCH_AVR2, AVR_ERRATA_SKIP, NULL, 0x0060, 0x0, 6, "s8515") ++AVR_MCU ("at90s2313", ARCH_AVR2, AVR_SHORT_SP, "__AVR_AT90S2313__", 0x0060, 0x0, 1, "s2313") ++AVR_MCU ("at90s2323", ARCH_AVR2, AVR_SHORT_SP, "__AVR_AT90S2323__", 0x0060, 0x0, 1, "s2323") ++AVR_MCU ("at90s2333", ARCH_AVR2, AVR_SHORT_SP, "__AVR_AT90S2333__", 0x0060, 0x0, 1, "s2333") ++AVR_MCU ("at90s2343", ARCH_AVR2, AVR_SHORT_SP, "__AVR_AT90S2343__", 0x0060, 0x0, 1, "s2343") ++AVR_MCU ("attiny22", ARCH_AVR2, AVR_SHORT_SP, "__AVR_ATtiny22__", 0x0060, 0x0, 1, "tn22") ++AVR_MCU ("attiny26", ARCH_AVR2, AVR_SHORT_SP, "__AVR_ATtiny26__", 0x0060, 0x0, 1, "tn26") ++AVR_MCU ("at90s4414", ARCH_AVR2, AVR_ISA_NONE, "__AVR_AT90S4414__", 0x0060, 0x0, 1, "s4414") ++AVR_MCU ("at90s4433", ARCH_AVR2, AVR_SHORT_SP, "__AVR_AT90S4433__", 0x0060, 0x0, 1, "s4433") ++AVR_MCU ("at90s4434", ARCH_AVR2, AVR_ISA_NONE, "__AVR_AT90S4434__", 0x0060, 0x0, 1, "s4434") ++AVR_MCU ("at90s8515", ARCH_AVR2, AVR_ERRATA_SKIP, "__AVR_AT90S8515__", 0x0060, 0x0, 1, "s8515") ++AVR_MCU ("at90c8534", ARCH_AVR2, AVR_ISA_NONE, "__AVR_AT90C8534__", 0x0060, 0x0, 1, "c8534") ++AVR_MCU ("at90s8535", ARCH_AVR2, AVR_ISA_NONE, "__AVR_AT90S8535__", 0x0060, 0x0, 1, "s8535") +/* Classic + MOVW/LPMX, <= 8K + 2-byte PC. */ -+AVR_MCU ("avr25", ARCH_AVR25, AVR_ISA_NONE, NULL, 0x0060, 1, "tn85") -+AVR_MCU ("ata5272", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATA5272__", 0x0100, 1, "a5272") -+AVR_MCU ("ata6616c", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATA6616C__", 0x0100, 1, "a6616c") -+AVR_MCU ("attiny13", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny13__", 0x0060, 1, "tn13") -+AVR_MCU ("attiny13a", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny13A__", 0x0060, 1, "tn13a") -+AVR_MCU ("attiny2313", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny2313__", 0x0060, 1, "tn2313") -+AVR_MCU ("attiny2313a", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny2313A__", 0x0060, 1, "tn2313a") -+AVR_MCU ("attiny24", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny24__", 0x0060, 1, "tn24") -+AVR_MCU ("attiny24a", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny24A__", 0x0060, 1, "tn24a") -+AVR_MCU ("attiny4313", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny4313__", 0x0060, 1, "tn4313") -+AVR_MCU ("attiny44", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny44__", 0x0060, 1, "tn44") -+AVR_MCU ("attiny44a", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny44A__", 0x0060, 1, "tn44a") -+AVR_MCU ("attiny441", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny441__", 0x0100, 1, "tn441") -+AVR_MCU ("attiny84", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny84__", 0x0060, 1, "tn84") -+AVR_MCU ("attiny84a", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny84A__", 0x0060, 1, "tn84") -+AVR_MCU ("attiny25", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny25__", 0x0060, 1, "tn25") -+AVR_MCU ("attiny45", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny45__", 0x0060, 1, "tn45") -+AVR_MCU ("attiny85", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny85__", 0x0060, 1, "tn85") -+AVR_MCU ("attiny261", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny261__", 0x0060, 1, "tn261") -+AVR_MCU ("attiny261a", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny261A__", 0x0060, 1, "tn261a") -+AVR_MCU ("attiny461", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny461__", 0x0060, 1, "tn461") -+AVR_MCU ("attiny461a", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny461A__", 0x0060, 1, "tn461a") -+AVR_MCU ("attiny861", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny861__", 0x0060, 1, "tn861") -+AVR_MCU ("attiny861a", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny861A__", 0x0060, 1, "tn861a") -+AVR_MCU ("attiny43u", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny43U__", 0x0060, 1, "tn43u") -+AVR_MCU ("attiny87", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny87__", 0x0100, 1, "tn87") -+AVR_MCU ("attiny48", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny48__", 0x0100, 1, "tn48") -+AVR_MCU ("attiny88", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny88__", 0x0100, 1, "tn88") -+AVR_MCU ("attiny828", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny828__", 0x0100, 1, "tn828") -+AVR_MCU ("attiny841", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny841__", 0x0100, 1, "tn841") -+AVR_MCU ("at86rf401", ARCH_AVR25, AVR_ISA_NONE, "__AVR_AT86RF401__", 0x0060, 1, "86401") ++AVR_MCU ("avr25", ARCH_AVR25, AVR_ISA_NONE, NULL, 0x0060, 0x0, 1, "tn85") ++AVR_MCU ("ata5272", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATA5272__", 0x0100, 0x0, 1, "a5272") ++AVR_MCU ("ata6616c", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATA6616C__", 0x0100, 0x0, 1, "a6616c") ++AVR_MCU ("attiny13", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny13__", 0x0060, 0x0, 1, "tn13") ++AVR_MCU ("attiny13a", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny13A__", 0x0060, 0x0, 1, "tn13a") ++AVR_MCU ("attiny2313", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny2313__", 0x0060, 0x0, 1, "tn2313") ++AVR_MCU ("attiny2313a", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny2313A__", 0x0060, 0x0, 1, "tn2313a") ++AVR_MCU ("attiny24", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny24__", 0x0060, 0x0, 1, "tn24") ++AVR_MCU ("attiny24a", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny24A__", 0x0060, 0x0, 1, "tn24a") ++AVR_MCU ("attiny4313", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny4313__", 0x0060, 0x0, 1, "tn4313") ++AVR_MCU ("attiny44", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny44__", 0x0060, 0x0, 1, "tn44") ++AVR_MCU ("attiny44a", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny44A__", 0x0060, 0x0, 1, "tn44a") ++AVR_MCU ("attiny441", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny441__", 0x0100, 0x0, 1, "tn441") ++AVR_MCU ("attiny84", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny84__", 0x0060, 0x0, 1, "tn84") ++AVR_MCU ("attiny84a", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny84A__", 0x0060, 0x0, 1, "tn84") ++AVR_MCU ("attiny25", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny25__", 0x0060, 0x0, 1, "tn25") ++AVR_MCU ("attiny45", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny45__", 0x0060, 0x0, 1, "tn45") ++AVR_MCU ("attiny85", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny85__", 0x0060, 0x0, 1, "tn85") ++AVR_MCU ("attiny261", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny261__", 0x0060, 0x0, 1, "tn261") ++AVR_MCU ("attiny261a", ARCH_AVR25, AVR_SHORT_SP, "__AVR_ATtiny261A__", 0x0060, 0x0, 1, "tn261a") ++AVR_MCU ("attiny461", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny461__", 0x0060, 0x0, 1, "tn461") ++AVR_MCU ("attiny461a", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny461A__", 0x0060, 0x0, 1, "tn461a") ++AVR_MCU ("attiny861", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny861__", 0x0060, 0x0, 1, "tn861") ++AVR_MCU ("attiny861a", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny861A__", 0x0060, 0x0, 1, "tn861a") ++AVR_MCU ("attiny43u", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny43U__", 0x0060, 0x0, 1, "tn43u") ++AVR_MCU ("attiny87", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny87__", 0x0100, 0x0, 1, "tn87") ++AVR_MCU ("attiny48", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny48__", 0x0100, 0x0, 1, "tn48") ++AVR_MCU ("attiny88", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny88__", 0x0100, 0x0, 1, "tn88") ++AVR_MCU ("attiny828", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny828__", 0x0100, 0x0, 1, "tn828") ++AVR_MCU ("attiny841", ARCH_AVR25, AVR_ISA_NONE, "__AVR_ATtiny841__", 0x0100, 0x0, 1, "tn841") ++AVR_MCU ("at86rf401", ARCH_AVR25, AVR_ISA_NONE, "__AVR_AT86RF401__", 0x0060, 0x0, 1, "86401") +/* Classic, > 8K, <= 64K + 2-byte PC + { JMP/CALL }. */ -+AVR_MCU ("avr3", ARCH_AVR3, AVR_ISA_NONE, NULL, 0x0060, 1, "43355") -+AVR_MCU ("at43usb355", ARCH_AVR3, AVR_ISA_NONE, "__AVR_AT43USB355__", 0x0060, 1, "43355") -+AVR_MCU ("at76c711", ARCH_AVR3, AVR_ISA_NONE, "__AVR_AT76C711__", 0x0060, 1, "76711") ++AVR_MCU ("avr3", ARCH_AVR3, AVR_ISA_NONE, NULL, 0x0060, 0x0, 1, "43355") ++AVR_MCU ("at43usb355", ARCH_AVR3, AVR_ISA_NONE, "__AVR_AT43USB355__", 0x0060, 0x0, 1, "43355") ++AVR_MCU ("at76c711", ARCH_AVR3, AVR_ISA_NONE, "__AVR_AT76C711__", 0x0060, 0x0, 1, "76711") +/* Classic, == 128K + 2-byte PC + {JMP/CALL, ELPM }. */ -+AVR_MCU ("avr31", ARCH_AVR31, AVR_ERRATA_SKIP, NULL, 0x0060, 2, "m103") -+AVR_MCU ("atmega103", ARCH_AVR31, AVR_ERRATA_SKIP, "__AVR_ATmega103__", 0x0060, 2, "m103") -+AVR_MCU ("at43usb320", ARCH_AVR31, AVR_ISA_NONE, "__AVR_AT43USB320__", 0x0060, 2, "43320") ++AVR_MCU ("avr31", ARCH_AVR31, AVR_ERRATA_SKIP, NULL, 0x0060, 0x0, 2, "m103") ++AVR_MCU ("atmega103", ARCH_AVR31, AVR_ERRATA_SKIP, "__AVR_ATmega103__", 0x0060, 0x0, 2, "m103") ++AVR_MCU ("at43usb320", ARCH_AVR31, AVR_ISA_NONE, "__AVR_AT43USB320__", 0x0060, 0x0, 2, "43320") +/* Classic, >=16K, <=64K + 2-byte PC + MOVW/LPMX + JMP/CALL. */ -+AVR_MCU ("avr35", ARCH_AVR35, AVR_ISA_NONE, NULL, 0x0100, 1, "usb162") -+AVR_MCU ("ata5505", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATA5505__", 0x0100, 1, "a5505") -+AVR_MCU ("ata6617c", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATA6617C__", 0x0100, 1, "a6617c") -+AVR_MCU ("ata664251", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATA664251__", 0x0100, 1, "a664251") -+AVR_MCU ("at90usb82", ARCH_AVR35, AVR_ISA_NONE, "__AVR_AT90USB82__", 0x0100, 1, "usb82") -+AVR_MCU ("at90usb162", ARCH_AVR35, AVR_ISA_NONE, "__AVR_AT90USB162__", 0x0100, 1, "usb162") -+AVR_MCU ("atmega8u2", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATmega8U2__", 0x0100, 1, "m8u2") -+AVR_MCU ("atmega16u2", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATmega16U2__", 0x0100, 1, "m16u2") -+AVR_MCU ("atmega32u2", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATmega32U2__", 0x0100, 1, "m32u2") -+AVR_MCU ("attiny167", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATtiny167__", 0x0100, 1, "tn167") -+AVR_MCU ("attiny1634", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATtiny1634__", 0x0100, 1, "tn1634") ++AVR_MCU ("avr35", ARCH_AVR35, AVR_ISA_NONE, NULL, 0x0100, 0x0, 1, "usb162") ++AVR_MCU ("ata5505", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATA5505__", 0x0100, 0x0, 1, "a5505") ++AVR_MCU ("ata6617c", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATA6617C__", 0x0100, 0x0, 1, "a6617c") ++AVR_MCU ("ata664251", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATA664251__", 0x0100, 0x0, 1, "a664251") ++AVR_MCU ("at90usb82", ARCH_AVR35, AVR_ISA_NONE, "__AVR_AT90USB82__", 0x0100, 0x0, 1, "usb82") ++AVR_MCU ("at90usb162", ARCH_AVR35, AVR_ISA_NONE, "__AVR_AT90USB162__", 0x0100, 0x0, 1, "usb162") ++AVR_MCU ("atmega8u2", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATmega8U2__", 0x0100, 0x0, 1, "m8u2") ++AVR_MCU ("atmega16u2", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATmega16U2__", 0x0100, 0x0, 1, "m16u2") ++AVR_MCU ("atmega32u2", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATmega32U2__", 0x0100, 0x0, 1, "m32u2") ++AVR_MCU ("attiny167", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATtiny167__", 0x0100, 0x0, 1, "tn167") ++AVR_MCU ("attiny1634", ARCH_AVR35, AVR_ISA_NONE, "__AVR_ATtiny1634__", 0x0100, 0x0, 1, "tn1634") +/* Enhanced, <= 8K + 2-byte PC + { MOVW/LPMX, MUL }. */ -+AVR_MCU ("avr4", ARCH_AVR4, AVR_ISA_NONE, NULL, 0x0060, 1, "m8") -+AVR_MCU ("ata6285", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATA6285__", 0x0100, 1, "a6285") -+AVR_MCU ("ata6286", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATA6286__", 0x0100, 1, "a6286") -+AVR_MCU ("ata6289", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATA6289__", 0x0100, 1, "a6289") -+AVR_MCU ("ata6612c", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATA6612C__", 0x0100, 1, "a6612c") -+AVR_MCU ("atmega8", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega8__", 0x0060, 1, "m8") -+AVR_MCU ("atmega8a", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega8A__", 0x0060, 1, "m8a") -+AVR_MCU ("atmega48", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega48__", 0x0100, 1, "m48") -+AVR_MCU ("atmega48a", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega48A__", 0x0100, 1, "m48a") -+AVR_MCU ("atmega48p", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega48P__", 0x0100, 1, "m48p") -+AVR_MCU ("atmega48pa", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega48PA__", 0x0100, 1, "m48pa") -+AVR_MCU ("atmega88", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega88__", 0x0100, 1, "m88") -+AVR_MCU ("atmega88a", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega88A__", 0x0100, 1, "m88a") -+AVR_MCU ("atmega88p", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega88P__", 0x0100, 1, "m88p") -+AVR_MCU ("atmega88pa", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega88PA__", 0x0100, 1, "m88pa") -+AVR_MCU ("atmega8515", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega8515__", 0x0060, 1, "m8515") -+AVR_MCU ("atmega8535", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega8535__", 0x0060, 1, "m8535") -+AVR_MCU ("atmega8hva", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega8HVA__", 0x0100, 1, "m8hva") -+AVR_MCU ("at90pwm1", ARCH_AVR4, AVR_ISA_NONE, "__AVR_AT90PWM1__", 0x0100, 1, "90pwm1") -+AVR_MCU ("at90pwm2", ARCH_AVR4, AVR_ISA_NONE, "__AVR_AT90PWM2__", 0x0100, 1, "90pwm2") -+AVR_MCU ("at90pwm2b", ARCH_AVR4, AVR_ISA_NONE, "__AVR_AT90PWM2B__", 0x0100, 1, "90pwm2b") -+AVR_MCU ("at90pwm3", ARCH_AVR4, AVR_ISA_NONE, "__AVR_AT90PWM3__", 0x0100, 1, "90pwm3") -+AVR_MCU ("at90pwm3b", ARCH_AVR4, AVR_ISA_NONE, "__AVR_AT90PWM3B__", 0x0100, 1, "90pwm3b") -+AVR_MCU ("at90pwm81", ARCH_AVR4, AVR_ISA_NONE, "__AVR_AT90PWM81__", 0x0100, 1, "90pwm81") ++AVR_MCU ("avr4", ARCH_AVR4, AVR_ISA_NONE, NULL, 0x0060, 0x0, 1, "m8") ++AVR_MCU ("ata6285", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATA6285__", 0x0100, 0x0, 1, "a6285") ++AVR_MCU ("ata6286", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATA6286__", 0x0100, 0x0, 1, "a6286") ++AVR_MCU ("ata6289", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATA6289__", 0x0100, 0x0, 1, "a6289") ++AVR_MCU ("ata6612c", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATA6612C__", 0x0100, 0x0, 1, "a6612c") ++AVR_MCU ("atmega8", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega8__", 0x0060, 0x0, 1, "m8") ++AVR_MCU ("atmega8a", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega8A__", 0x0060, 0x0, 1, "m8a") ++AVR_MCU ("atmega48", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega48__", 0x0100, 0x0, 1, "m48") ++AVR_MCU ("atmega48a", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega48A__", 0x0100, 0x0, 1, "m48a") ++AVR_MCU ("atmega48p", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega48P__", 0x0100, 0x0, 1, "m48p") ++AVR_MCU ("atmega48pa", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega48PA__", 0x0100, 0x0, 1, "m48pa") ++AVR_MCU ("atmega48pb", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega48PB__", 0x0100, 0x0, 1, "m48pb") ++AVR_MCU ("atmega88", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega88__", 0x0100, 0x0, 1, "m88") ++AVR_MCU ("atmega88a", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega88A__", 0x0100, 0x0, 1, "m88a") ++AVR_MCU ("atmega88p", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega88P__", 0x0100, 0x0, 1, "m88p") ++AVR_MCU ("atmega88pa", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega88PA__", 0x0100, 0x0, 1, "m88pa") ++AVR_MCU ("atmega88pb", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega88PB__", 0x0100, 0x0, 1, "m88pb") ++AVR_MCU ("atmega8515", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega8515__", 0x0060, 0x0, 1, "m8515") ++AVR_MCU ("atmega8535", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega8535__", 0x0060, 0x0, 1, "m8535") ++AVR_MCU ("atmega8hva", ARCH_AVR4, AVR_ISA_NONE, "__AVR_ATmega8HVA__", 0x0100, 0x0, 1, "m8hva") ++AVR_MCU ("at90pwm1", ARCH_AVR4, AVR_ISA_NONE, "__AVR_AT90PWM1__", 0x0100, 0x0, 1, "90pwm1") ++AVR_MCU ("at90pwm2", ARCH_AVR4, AVR_ISA_NONE, "__AVR_AT90PWM2__", 0x0100, 0x0, 1, "90pwm2") ++AVR_MCU ("at90pwm2b", ARCH_AVR4, AVR_ISA_NONE, "__AVR_AT90PWM2B__", 0x0100, 0x0, 1, "90pwm2b") ++AVR_MCU ("at90pwm3", ARCH_AVR4, AVR_ISA_NONE, "__AVR_AT90PWM3__", 0x0100, 0x0, 1, "90pwm3") ++AVR_MCU ("at90pwm3b", ARCH_AVR4, AVR_ISA_NONE, "__AVR_AT90PWM3B__", 0x0100, 0x0, 1, "90pwm3b") ++AVR_MCU ("at90pwm81", ARCH_AVR4, AVR_ISA_NONE, "__AVR_AT90PWM81__", 0x0100, 0x0, 1, "90pwm81") +/* Enhanced, > 8K, <= 64K + 2-byte PC + { MOVW/LPMX, JMP/CALL, MUL }. */ -+AVR_MCU ("avr5", ARCH_AVR5, AVR_ISA_NONE, NULL, 0x0060, 1, "m16") -+AVR_MCU ("ata5702m322", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATA5702M322__", 0x0200, 1, "a5702m322") -+AVR_MCU ("ata5790", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATA5790__", 0x0100, 1, "a5790") -+AVR_MCU ("ata5790n", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATA5790N__", 0x0100, 1, "a5790n") -+AVR_MCU ("ata5795", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATA5795__", 0x0100, 1, "a5795") -+AVR_MCU ("ata6613c", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATA6613C__", 0x0100, 1, "a6613c") -+AVR_MCU ("ata6614q", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATA6614Q__", 0x0100, 1, "a6614q") -+AVR_MCU ("atmega16", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16__", 0x0060, 1, "m16") -+AVR_MCU ("atmega16a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16A__", 0x0060, 1, "m16a") -+AVR_MCU ("atmega161", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega161__", 0x0060, 1, "m161") -+AVR_MCU ("atmega162", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega162__", 0x0100, 1, "m162") -+AVR_MCU ("atmega163", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega163__", 0x0060, 1, "m163") -+AVR_MCU ("atmega164a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega164A__", 0x0100, 1, "m164a") -+AVR_MCU ("atmega164p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega164P__", 0x0100, 1, "m164p") -+AVR_MCU ("atmega164pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega164PA__", 0x0100, 1, "m164pa") -+AVR_MCU ("atmega165", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega165__", 0x0100, 1, "m165") -+AVR_MCU ("atmega165a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega165A__", 0x0100, 1, "m165a") -+AVR_MCU ("atmega165p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega165P__", 0x0100, 1, "m165p") -+AVR_MCU ("atmega165pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega165PA__", 0x0100, 1, "m165pa") -+AVR_MCU ("atmega168", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega168__", 0x0100, 1, "m168") -+AVR_MCU ("atmega168a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega168A__", 0x0100, 1, "m168a") -+AVR_MCU ("atmega168p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega168P__", 0x0100, 1, "m168p") -+AVR_MCU ("atmega168pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega168PA__", 0x0100, 1, "m168pa") -+AVR_MCU ("atmega169", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega169__", 0x0100, 1, "m169") -+AVR_MCU ("atmega169a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega169A__", 0x0100, 1, "m169a") -+AVR_MCU ("atmega169p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega169P__", 0x0100, 1, "m169p") -+AVR_MCU ("atmega169pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega169PA__", 0x0100, 1, "m169pa") -+AVR_MCU ("atmega16hvb", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16HVB__", 0x0100, 1, "m16hvb") -+AVR_MCU ("atmega16hvbrevb", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16HVBrevB__", 0x0100, 1, "m16hvbrevb") -+AVR_MCU ("atmega16m1", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16M1__", 0x0100, 1, "m16m1") -+AVR_MCU ("atmega16u4", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16U4__", 0x0100, 1, "m16u4") -+AVR_MCU ("atmega32a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32A__", 0x0060, 1, "m32a") -+AVR_MCU ("atmega32", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32__", 0x0060, 1, "m32") -+AVR_MCU ("atmega323", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega323__", 0x0060, 1, "m323") -+AVR_MCU ("atmega324a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega324A__", 0x0100, 1, "m324a") -+AVR_MCU ("atmega324p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega324P__", 0x0100, 1, "m324p") -+AVR_MCU ("atmega324pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega324PA__", 0x0100, 1, "m324pa") -+AVR_MCU ("atmega325", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega325__", 0x0100, 1, "m325") -+AVR_MCU ("atmega325a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega325A__", 0x0100, 1, "m325a") -+AVR_MCU ("atmega325p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega325P__", 0x0100, 1, "m325p") -+AVR_MCU ("atmega325pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega325PA__", 0x0100, 1, "m325pa") -+AVR_MCU ("atmega3250", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3250__", 0x0100, 1, "m3250") -+AVR_MCU ("atmega3250a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3250A__", 0x0100, 1, "m3250a") -+AVR_MCU ("atmega3250p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3250P__", 0x0100, 1, "m3250p") -+AVR_MCU ("atmega3250pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3250PA__", 0x0100, 1, "m3250pa") -+AVR_MCU ("atmega328", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega328__", 0x0100, 1, "m328") -+AVR_MCU ("atmega328p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega328P__", 0x0100, 1, "m328p") -+AVR_MCU ("atmega329", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega329__", 0x0100, 1, "m329") -+AVR_MCU ("atmega329a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega329A__", 0x0100, 1, "m329a") -+AVR_MCU ("atmega329p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega329P__", 0x0100, 1, "m329p") -+AVR_MCU ("atmega329pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega329PA__", 0x0100, 1, "m329pa") -+AVR_MCU ("atmega3290", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3290__", 0x0100, 1, "m3290") -+AVR_MCU ("atmega3290a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3290A__", 0x0100, 1, "m3290a") -+AVR_MCU ("atmega3290p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3290P__", 0x0100, 1, "m3290p") -+AVR_MCU ("atmega3290pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3290PA__", 0x0100, 1, "m3290pa") -+AVR_MCU ("atmega32c1", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32C1__", 0x0100, 1, "m32c1") -+AVR_MCU ("atmega32m1", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32M1__", 0x0100, 1, "m32m1") -+AVR_MCU ("atmega32u4", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32U4__", 0x0100, 1, "m32u4") -+AVR_MCU ("atmega32u6", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32U6__", 0x0100, 1, "m32u6") -+AVR_MCU ("atmega406", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega406__", 0x0100, 1, "m406") -+AVR_MCU ("atmega64", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64__", 0x0100, 1, "m64") -+AVR_MCU ("atmega64a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64A__", 0x0100, 1, "m64a") -+AVR_MCU ("atmega640", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega640__", 0x0200, 1, "m640") -+AVR_MCU ("atmega644", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega644__", 0x0100, 1, "m644") -+AVR_MCU ("atmega644a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega644A__", 0x0100, 1, "m644a") -+AVR_MCU ("atmega644p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega644P__", 0x0100, 1, "m644p") -+AVR_MCU ("atmega644pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega644PA__", 0x0100, 1, "m644pa") -+AVR_MCU ("atmega645", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega645__", 0x0100, 1, "m645") -+AVR_MCU ("atmega645a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega645A__", 0x0100, 1, "m645a") -+AVR_MCU ("atmega645p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega645P__", 0x0100, 1, "m645p") -+AVR_MCU ("atmega6450", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega6450__", 0x0100, 1, "m6450") -+AVR_MCU ("atmega6450a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega6450A__", 0x0100, 1, "m6450a") -+AVR_MCU ("atmega6450p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega6450P__", 0x0100, 1, "m6450p") -+AVR_MCU ("atmega649", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega649__", 0x0100, 1, "m649") -+AVR_MCU ("atmega649a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega649A__", 0x0100, 1, "m649a") -+AVR_MCU ("atmega649p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega649P__", 0x0100, 1, "m649p") -+AVR_MCU ("atmega6490", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega6490__", 0x0100, 1, "m6490") -+AVR_MCU ("atmega16hva", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16HVA__", 0x0100, 1, "m16hva") -+AVR_MCU ("atmega16hva2", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16HVA2__", 0x0100, 1, "m16hva2") -+AVR_MCU ("atmega32hvb", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32HVB__", 0x0100, 1, "m32hvb") -+AVR_MCU ("atmega6490a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega6490A__", 0x0100, 1, "m6490a") -+AVR_MCU ("atmega6490p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega6490P__", 0x0100, 1, "m6490p") -+AVR_MCU ("atmega64c1", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64C1__", 0x0100, 1, "m64c1") -+AVR_MCU ("atmega64m1", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64M1__", 0x0100, 1, "m64m1") -+AVR_MCU ("atmega64hve", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64HVE__", 0x0100, 1, "m64hve") -+AVR_MCU ("atmega64hve2", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64HVE2__", 0x0100, 1, "m64hve2") -+AVR_MCU ("atmega64rfr2", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64RFR2__", 0x0200, 1, "m64rfr2") -+AVR_MCU ("atmega644rfr2", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega644RFR2__", 0x0200, 1, "m644rfr2") -+AVR_MCU ("atmega32hvbrevb", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32HVBrevB__", 0x0100, 1, "m32hvbrevb") -+AVR_MCU ("at90can32", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90CAN32__", 0x0100, 1, "can32") -+AVR_MCU ("at90can64", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90CAN64__", 0x0100, 1, "can64") -+AVR_MCU ("at90pwm161", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90PWM161__", 0x0100, 1, "90pwm161") -+AVR_MCU ("at90pwm216", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90PWM216__", 0x0100, 1, "90pwm216") -+AVR_MCU ("at90pwm316", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90PWM316__", 0x0100, 1, "90pwm316") -+AVR_MCU ("at90scr100", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90SCR100__", 0x0100, 1, "90scr100") -+AVR_MCU ("at90usb646", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90USB646__", 0x0100, 1, "usb646") -+AVR_MCU ("at90usb647", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90USB647__", 0x0100, 1, "usb647") -+AVR_MCU ("at94k", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT94K__", 0x0060, 1, "at94k") -+AVR_MCU ("m3000", ARCH_AVR5, AVR_ISA_NONE, "__AVR_M3000__", 0x1000, 1, "m3000") ++AVR_MCU ("avr5", ARCH_AVR5, AVR_ISA_NONE, NULL, 0x0060, 0x0, 1, "m16") ++AVR_MCU ("ata5702m322", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATA5702M322__", 0x0200, 0x0, 1, "a5702m322") ++AVR_MCU ("ata5782", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATA5782__", 0x0200, 0x8000, 1, "a5782") ++AVR_MCU ("ata5790", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATA5790__", 0x0100, 0x0, 1, "a5790") ++AVR_MCU ("ata5790n", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATA5790N__", 0x0100, 0x0, 1, "a5790n") ++AVR_MCU ("ata5795", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATA5795__", 0x0100, 0x0, 1, "a5795") ++AVR_MCU ("ata5831", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATA5831__", 0x0200, 0x8000, 1, "a5831") ++AVR_MCU ("ata6613c", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATA6613C__", 0x0100, 0x0, 1, "a6613c") ++AVR_MCU ("ata6614q", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATA6614Q__", 0x0100, 0x0, 1, "a6614q") ++AVR_MCU ("atmega16", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16__", 0x0060, 0x0, 1, "m16") ++AVR_MCU ("atmega16a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16A__", 0x0060, 0x0, 1, "m16a") ++AVR_MCU ("atmega161", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega161__", 0x0060, 0x0, 1, "m161") ++AVR_MCU ("atmega162", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega162__", 0x0100, 0x0, 1, "m162") ++AVR_MCU ("atmega163", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega163__", 0x0060, 0x0, 1, "m163") ++AVR_MCU ("atmega164a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega164A__", 0x0100, 0x0, 1, "m164a") ++AVR_MCU ("atmega164p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega164P__", 0x0100, 0x0, 1, "m164p") ++AVR_MCU ("atmega164pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega164PA__", 0x0100, 0x0, 1, "m164pa") ++AVR_MCU ("atmega165", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega165__", 0x0100, 0x0, 1, "m165") ++AVR_MCU ("atmega165a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega165A__", 0x0100, 0x0, 1, "m165a") ++AVR_MCU ("atmega165p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega165P__", 0x0100, 0x0, 1, "m165p") ++AVR_MCU ("atmega165pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega165PA__", 0x0100, 0x0, 1, "m165pa") ++AVR_MCU ("atmega168", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega168__", 0x0100, 0x0, 1, "m168") ++AVR_MCU ("atmega168a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega168A__", 0x0100, 0x0, 1, "m168a") ++AVR_MCU ("atmega168p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega168P__", 0x0100, 0x0, 1, "m168p") ++AVR_MCU ("atmega168pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega168PA__", 0x0100, 0x0, 1, "m168pa") ++AVR_MCU ("atmega168pb", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega168PB__", 0x0100, 0x0, 1, "m168pb") ++AVR_MCU ("atmega169", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega169__", 0x0100, 0x0, 1, "m169") ++AVR_MCU ("atmega169a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega169A__", 0x0100, 0x0, 1, "m169a") ++AVR_MCU ("atmega169p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega169P__", 0x0100, 0x0, 1, "m169p") ++AVR_MCU ("atmega169pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega169PA__", 0x0100, 0x0, 1, "m169pa") ++AVR_MCU ("atmega16hvb", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16HVB__", 0x0100, 0x0, 1, "m16hvb") ++AVR_MCU ("atmega16hvbrevb", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16HVBREVB__", 0x0100, 0x0, 1, "m16hvbrevb") ++AVR_MCU ("atmega16m1", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16M1__", 0x0100, 0x0, 1, "m16m1") ++AVR_MCU ("atmega16u4", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16U4__", 0x0100, 0x0, 1, "m16u4") ++AVR_MCU ("atmega32a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32A__", 0x0060, 0x0, 1, "m32a") ++AVR_MCU ("atmega32", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32__", 0x0060, 0x0, 1, "m32") ++AVR_MCU ("atmega323", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega323__", 0x0060, 0x0, 1, "m323") ++AVR_MCU ("atmega324a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega324A__", 0x0100, 0x0, 1, "m324a") ++AVR_MCU ("atmega324p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega324P__", 0x0100, 0x0, 1, "m324p") ++AVR_MCU ("atmega324pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega324PA__", 0x0100, 0x0, 1, "m324pa") ++AVR_MCU ("atmega325", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega325__", 0x0100, 0x0, 1, "m325") ++AVR_MCU ("atmega325a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega325A__", 0x0100, 0x0, 1, "m325a") ++AVR_MCU ("atmega325p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega325P__", 0x0100, 0x0, 1, "m325p") ++AVR_MCU ("atmega325pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega325PA__", 0x0100, 0x0, 1, "m325pa") ++AVR_MCU ("atmega3250", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3250__", 0x0100, 0x0, 1, "m3250") ++AVR_MCU ("atmega3250a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3250A__", 0x0100, 0x0, 1, "m3250a") ++AVR_MCU ("atmega3250p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3250P__", 0x0100, 0x0, 1, "m3250p") ++AVR_MCU ("atmega3250pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3250PA__", 0x0100, 0x0, 1, "m3250pa") ++AVR_MCU ("atmega328", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega328__", 0x0100, 0x0, 1, "m328") ++AVR_MCU ("atmega328p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega328P__", 0x0100, 0x0, 1, "m328p") ++AVR_MCU ("atmega329", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega329__", 0x0100, 0x0, 1, "m329") ++AVR_MCU ("atmega329a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega329A__", 0x0100, 0x0, 1, "m329a") ++AVR_MCU ("atmega329p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega329P__", 0x0100, 0x0, 1, "m329p") ++AVR_MCU ("atmega329pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega329PA__", 0x0100, 0x0, 1, "m329pa") ++AVR_MCU ("atmega3290", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3290__", 0x0100, 0x0, 1, "m3290") ++AVR_MCU ("atmega3290a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3290A__", 0x0100, 0x0, 1, "m3290a") ++AVR_MCU ("atmega3290p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3290P__", 0x0100, 0x0, 1, "m3290p") ++AVR_MCU ("atmega3290pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega3290PA__", 0x0100, 0x0, 1, "m3290pa") ++AVR_MCU ("atmega32c1", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32C1__", 0x0100, 0x0, 1, "m32c1") ++AVR_MCU ("atmega32m1", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32M1__", 0x0100, 0x0, 1, "m32m1") ++AVR_MCU ("atmega32u4", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32U4__", 0x0100, 0x0, 1, "m32u4") ++AVR_MCU ("atmega32u6", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32U6__", 0x0100, 0x0, 1, "m32u6") ++AVR_MCU ("atmega406", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega406__", 0x0100, 0x0, 1, "m406") ++AVR_MCU ("atmega64", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64__", 0x0100, 0x0, 1, "m64") ++AVR_MCU ("atmega64a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64A__", 0x0100, 0x0, 1, "m64a") ++AVR_MCU ("atmega640", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega640__", 0x0200, 0x0, 1, "m640") ++AVR_MCU ("atmega644", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega644__", 0x0100, 0x0, 1, "m644") ++AVR_MCU ("atmega644a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega644A__", 0x0100, 0x0, 1, "m644a") ++AVR_MCU ("atmega644p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega644P__", 0x0100, 0x0, 1, "m644p") ++AVR_MCU ("atmega644pa", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega644PA__", 0x0100, 0x0, 1, "m644pa") ++AVR_MCU ("atmega645", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega645__", 0x0100, 0x0, 1, "m645") ++AVR_MCU ("atmega645a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega645A__", 0x0100, 0x0, 1, "m645a") ++AVR_MCU ("atmega645p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega645P__", 0x0100, 0x0, 1, "m645p") ++AVR_MCU ("atmega6450", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega6450__", 0x0100, 0x0, 1, "m6450") ++AVR_MCU ("atmega6450a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega6450A__", 0x0100, 0x0, 1, "m6450a") ++AVR_MCU ("atmega6450p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega6450P__", 0x0100, 0x0, 1, "m6450p") ++AVR_MCU ("atmega649", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega649__", 0x0100, 0x0, 1, "m649") ++AVR_MCU ("atmega649a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega649A__", 0x0100, 0x0, 1, "m649a") ++AVR_MCU ("atmega649p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega649P__", 0x0100, 0x0, 1, "m649p") ++AVR_MCU ("atmega6490", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega6490__", 0x0100, 0x0, 1, "m6490") ++AVR_MCU ("atmega16hva", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16HVA__", 0x0100, 0x0, 1, "m16hva") ++AVR_MCU ("atmega16hva2", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega16HVA2__", 0x0100, 0x0, 1, "m16hva2") ++AVR_MCU ("atmega32hvb", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32HVB__", 0x0100, 0x0, 1, "m32hvb") ++AVR_MCU ("atmega6490a", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega6490A__", 0x0100, 0x0, 1, "m6490a") ++AVR_MCU ("atmega6490p", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega6490P__", 0x0100, 0x0, 1, "m6490p") ++AVR_MCU ("atmega64c1", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64C1__", 0x0100, 0x0, 1, "m64c1") ++AVR_MCU ("atmega64m1", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64M1__", 0x0100, 0x0, 1, "m64m1") ++AVR_MCU ("atmega64hve", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64HVE__", 0x0100, 0x0, 1, "m64hve") ++AVR_MCU ("atmega64hve2", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64HVE2__", 0x0100, 0x0, 1, "m64hve2") ++AVR_MCU ("atmega64rfr2", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega64RFR2__", 0x0200, 0x0, 1, "m64rfr2") ++AVR_MCU ("atmega644rfr2", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega644RFR2__", 0x0200, 0x0, 1, "m644rfr2") ++AVR_MCU ("atmega32hvbrevb", ARCH_AVR5, AVR_ISA_NONE, "__AVR_ATmega32HVBREVB__", 0x0100, 0x0, 1, "m32hvbrevb") ++AVR_MCU ("at90can32", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90CAN32__", 0x0100, 0x0, 1, "can32") ++AVR_MCU ("at90can64", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90CAN64__", 0x0100, 0x0, 1, "can64") ++AVR_MCU ("at90pwm161", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90PWM161__", 0x0100, 0x0, 1, "90pwm161") ++AVR_MCU ("at90pwm216", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90PWM216__", 0x0100, 0x0, 1, "90pwm216") ++AVR_MCU ("at90pwm316", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90PWM316__", 0x0100, 0x0, 1, "90pwm316") ++AVR_MCU ("at90scr100", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90SCR100__", 0x0100, 0x0, 1, "90scr100") ++AVR_MCU ("at90usb646", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90USB646__", 0x0100, 0x0, 1, "usb646") ++AVR_MCU ("at90usb647", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT90USB647__", 0x0100, 0x0, 1, "usb647") ++AVR_MCU ("at94k", ARCH_AVR5, AVR_ISA_NONE, "__AVR_AT94K__", 0x0060, 0x0, 1, "at94k") ++AVR_MCU ("m3000", ARCH_AVR5, AVR_ISA_NONE, "__AVR_M3000__", 0x1000, 0x0, 1, "m3000") +/* Enhanced, == 128K + 2-byte PC + { MOVW/LPMX, JMP/CALL, MUL, ELPM, ELPMX }. */ -+AVR_MCU ("avr51", ARCH_AVR51, AVR_ISA_NONE, NULL, 0x0100, 2, "m128") -+AVR_MCU ("atmega128", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega128__", 0x0100, 2, "m128") -+AVR_MCU ("atmega128a", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega128A__", 0x0100, 2, "m128a") -+AVR_MCU ("atmega1280", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega1280__", 0x0200, 2, "m1280") -+AVR_MCU ("atmega1281", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega1281__", 0x0200, 2, "m1281") -+AVR_MCU ("atmega1284", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega1284__", 0x0100, 2, "m1284") -+AVR_MCU ("atmega1284p", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega1284P__", 0x0100, 2, "m1284p") -+AVR_MCU ("atmega128rfa1", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega128RFA1__", 0x0200, 2, "m128rfa1") -+AVR_MCU ("atmega128rfr2", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega128RFR2__", 0x0200, 2, "m128rfr2") -+AVR_MCU ("atmega1284rfr2", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega1284RFR2__", 0x0200, 2, "m1284rfr2") -+AVR_MCU ("at90can128", ARCH_AVR51, AVR_ISA_NONE, "__AVR_AT90CAN128__", 0x0100, 2, "can128") -+AVR_MCU ("at90usb1286", ARCH_AVR51, AVR_ISA_NONE, "__AVR_AT90USB1286__", 0x0100, 2, "usb1286") -+AVR_MCU ("at90usb1287", ARCH_AVR51, AVR_ISA_NONE, "__AVR_AT90USB1287__", 0x0100, 2, "usb1287") ++AVR_MCU ("avr51", ARCH_AVR51, AVR_ISA_NONE, NULL, 0x0100, 0x0, 2, "m128") ++AVR_MCU ("atmega128", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega128__", 0x0100, 0x0, 2, "m128") ++AVR_MCU ("atmega128a", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega128A__", 0x0100, 0x0, 2, "m128a") ++AVR_MCU ("atmega1280", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega1280__", 0x0200, 0x0, 2, "m1280") ++AVR_MCU ("atmega1281", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega1281__", 0x0200, 0x0, 2, "m1281") ++AVR_MCU ("atmega1284", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega1284__", 0x0100, 0x0, 2, "m1284") ++AVR_MCU ("atmega1284p", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega1284P__", 0x0100, 0x0, 2, "m1284p") ++AVR_MCU ("atmega128rfa1", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega128RFA1__", 0x0200, 0x0, 2, "m128rfa1") ++AVR_MCU ("atmega128rfr2", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega128RFR2__", 0x0200, 0x0, 2, "m128rfr2") ++AVR_MCU ("atmega1284rfr2", ARCH_AVR51, AVR_ISA_NONE, "__AVR_ATmega1284RFR2__", 0x0200, 0x0, 2, "m1284rfr2") ++AVR_MCU ("at90can128", ARCH_AVR51, AVR_ISA_NONE, "__AVR_AT90CAN128__", 0x0100, 0x0, 2, "can128") ++AVR_MCU ("at90usb1286", ARCH_AVR51, AVR_ISA_NONE, "__AVR_AT90USB1286__", 0x0100, 0x0, 2, "usb1286") ++AVR_MCU ("at90usb1287", ARCH_AVR51, AVR_ISA_NONE, "__AVR_AT90USB1287__", 0x0100, 0x0, 2, "usb1287") +/* Enhanced, == 256K + 3-Byte PC + { MOVW/LPMX, JMP/CALL, MUL, ELPM, ELPMX }. */ -+AVR_MCU ("avr6", ARCH_AVR6, AVR_ISA_NONE, NULL, 0x0200, 4, "m2561") -+AVR_MCU ("atmega2560", ARCH_AVR6, AVR_ISA_NONE, "__AVR_ATmega2560__", 0x0200, 4, "m2560") -+AVR_MCU ("atmega2561", ARCH_AVR6, AVR_ISA_NONE, "__AVR_ATmega2561__", 0x0200, 4, "m2561") -+AVR_MCU ("atmega256rfr2", ARCH_AVR6, AVR_ISA_NONE, "__AVR_ATmega256RFR2__", 0x0200, 4, "m256rfr2") -+AVR_MCU ("atmega2564rfr2", ARCH_AVR6, AVR_ISA_NONE, "__AVR_ATmega2564RFR2__", 0x0200, 4, "m2564rfr2") -+/* Enhanced, == 20K starts at 0x8000 */ -+AVR_MCU ("avr7", ARCH_AVR7, AVR_ISA_NONE, NULL, 0x0200, 1, "a5831") -+AVR_MCU ("ata5782", ARCH_AVR7, AVR_ISA_NONE, "__AVR_ATA5782__", 0x0200, 1, "a5782") -+AVR_MCU ("ata5831", ARCH_AVR7, AVR_ISA_NONE, "__AVR_ATA5831__", 0x0200, 1, "a5831") ++AVR_MCU ("avr6", ARCH_AVR6, AVR_ISA_NONE, NULL, 0x0200, 0x0, 4, "m2561") ++AVR_MCU ("atmega2560", ARCH_AVR6, AVR_ISA_NONE, "__AVR_ATmega2560__", 0x0200, 0x0, 4, "m2560") ++AVR_MCU ("atmega2561", ARCH_AVR6, AVR_ISA_NONE, "__AVR_ATmega2561__", 0x0200, 0x0, 4, "m2561") ++AVR_MCU ("atmega256rfr2", ARCH_AVR6, AVR_ISA_NONE, "__AVR_ATmega256RFR2__", 0x0200, 0x0, 4, "m256rfr2") ++AVR_MCU ("atmega2564rfr2", ARCH_AVR6, AVR_ISA_NONE, "__AVR_ATmega2564RFR2__", 0x0200, 0x0, 4, "m2564rfr2") /* Xmega, 16K <= Flash < 64K, RAM <= 64K */ -AVR_MCU ("avrxmega2", ARCH_AVRXMEGA2, NULL, 0, 0, 0x2000, 1, "x32a4") -AVR_MCU ("atxmega16a4", ARCH_AVRXMEGA2, "__AVR_ATxmega16A4__", 0, 0, 0x2000, 1, "x16a4") @@ -1405,20 +1443,20 @@ index 2a730ac..5797b9c 100644 -AVR_MCU ("atxmega32a4u", ARCH_AVRXMEGA2, "__AVR_ATxmega32A4U__", 0, 0, 0x2000, 1, "x32a4u") -AVR_MCU ("atxmega32c4", ARCH_AVRXMEGA2, "__AVR_ATxmega32C4__", 0, 0, 0x2000, 1, "x32c4") -AVR_MCU ("atxmega32e5", ARCH_AVRXMEGA2, "__AVR_ATxmega32E5__", 0, 0, 0x2000, 1, "x32e5") -+AVR_MCU ("avrxmega2", ARCH_AVRXMEGA2, AVR_ISA_NONE, NULL, 0x2000, 1, "x32a4") -+AVR_MCU ("atxmega8e5", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega8E5__", 0x2000, 1, "x8e5") -+AVR_MCU ("atxmega16a4", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega16A4__", 0x2000, 1, "x16a4") -+AVR_MCU ("atxmega16a4u", ARCH_AVRXMEGA2, AVR_ISA_RMW, "__AVR_ATxmega16A4U__", 0x2000, 1, "x16a4u") -+AVR_MCU ("atxmega16c4", ARCH_AVRXMEGA2, AVR_ISA_RMW, "__AVR_ATxmega16C4__", 0x2000, 1, "x16c4") -+AVR_MCU ("atxmega16d4", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega16D4__", 0x2000, 1, "x16d4") -+AVR_MCU ("atxmega16e5", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega16E5__", 0x2000, 1, "x16e5") -+AVR_MCU ("atxmega32a4", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega32A4__", 0x2000, 1, "x32a4") -+AVR_MCU ("atxmega32a4u", ARCH_AVRXMEGA2, AVR_ISA_RMW, "__AVR_ATxmega32A4U__", 0x2000, 1, "x32a4u") -+AVR_MCU ("atxmega32c3", ARCH_AVRXMEGA2, AVR_ISA_RMW, "__AVR_ATxmega32C3__", 0x2000, 1, "x32c3") -+AVR_MCU ("atxmega32c4", ARCH_AVRXMEGA2, AVR_ISA_RMW, "__AVR_ATxmega32C4__", 0x2000, 1, "x32c4") -+AVR_MCU ("atxmega32d3", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega32D3__", 0x2000, 1, "x32d3") -+AVR_MCU ("atxmega32d4", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega32D4__", 0x2000, 1, "x32d4") -+AVR_MCU ("atxmega32e5", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega32E5__", 0x2000, 1, "x32e5") ++AVR_MCU ("avrxmega2", ARCH_AVRXMEGA2, AVR_ISA_NONE, NULL, 0x2000, 0x0, 1, "x32a4") ++AVR_MCU ("atxmega8e5", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega8E5__", 0x2000, 0x0, 1, "x8e5") ++AVR_MCU ("atxmega16a4", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega16A4__", 0x2000, 0x0, 1, "x16a4") ++AVR_MCU ("atxmega16a4u", ARCH_AVRXMEGA2, AVR_ISA_RMW, "__AVR_ATxmega16A4U__", 0x2000, 0x0, 1, "x16a4u") ++AVR_MCU ("atxmega16c4", ARCH_AVRXMEGA2, AVR_ISA_RMW, "__AVR_ATxmega16C4__", 0x2000, 0x0, 1, "x16c4") ++AVR_MCU ("atxmega16d4", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega16D4__", 0x2000, 0x0, 1, "x16d4") ++AVR_MCU ("atxmega16e5", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega16E5__", 0x2000, 0x0, 1, "x16e5") ++AVR_MCU ("atxmega32a4", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega32A4__", 0x2000, 0x0, 1, "x32a4") ++AVR_MCU ("atxmega32a4u", ARCH_AVRXMEGA2, AVR_ISA_RMW, "__AVR_ATxmega32A4U__", 0x2000, 0x0, 1, "x32a4u") ++AVR_MCU ("atxmega32c3", ARCH_AVRXMEGA2, AVR_ISA_RMW, "__AVR_ATxmega32C3__", 0x2000, 0x0, 1, "x32c3") ++AVR_MCU ("atxmega32c4", ARCH_AVRXMEGA2, AVR_ISA_RMW, "__AVR_ATxmega32C4__", 0x2000, 0x0, 1, "x32c4") ++AVR_MCU ("atxmega32d3", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega32D3__", 0x2000, 0x0, 1, "x32d3") ++AVR_MCU ("atxmega32d4", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega32D4__", 0x2000, 0x0, 1, "x32d4") ++AVR_MCU ("atxmega32e5", ARCH_AVRXMEGA2, AVR_ISA_NONE, "__AVR_ATxmega32E5__", 0x2000, 0x0, 1, "x32e5") /* Xmega, 64K < Flash <= 128K, RAM <= 64K */ -AVR_MCU ("avrxmega4", ARCH_AVRXMEGA4, NULL, 0, 0, 0x2000, 2, "x64a4") -AVR_MCU ("atxmega64a3", ARCH_AVRXMEGA4, "__AVR_ATxmega64A3__", 0, 0, 0x2000, 2, "x64a3") @@ -1429,22 +1467,22 @@ index 2a730ac..5797b9c 100644 -AVR_MCU ("atxmega64b3", ARCH_AVRXMEGA4, "__AVR_ATxmega64B3__", 0, 0, 0x2000, 2, "x64b3") -AVR_MCU ("atxmega64c3", ARCH_AVRXMEGA4, "__AVR_ATxmega64C3__", 0, 0, 0x2000, 2, "x64c3") -AVR_MCU ("atxmega64d4", ARCH_AVRXMEGA4, "__AVR_ATxmega64D4__", 0, 0, 0x2000, 2, "x64d4") -+AVR_MCU ("avrxmega4", ARCH_AVRXMEGA4, AVR_ISA_NONE, NULL, 0x2000, 2, "x64a4") -+AVR_MCU ("atxmega64a3", ARCH_AVRXMEGA4, AVR_ISA_NONE, "__AVR_ATxmega64A3__", 0x2000, 2, "x64a3") -+AVR_MCU ("atxmega64a3u", ARCH_AVRXMEGA4, AVR_ISA_RMW, "__AVR_ATxmega64A3U__", 0x2000, 2, "x64a3u") -+AVR_MCU ("atxmega64a4u", ARCH_AVRXMEGA4, AVR_ISA_RMW, "__AVR_ATxmega64A4U__", 0x2000, 2, "x64a4u") -+AVR_MCU ("atxmega64b1", ARCH_AVRXMEGA4, AVR_ISA_RMW, "__AVR_ATxmega64B1__", 0x2000, 2, "x64b1") -+AVR_MCU ("atxmega64b3", ARCH_AVRXMEGA4, AVR_ISA_RMW, "__AVR_ATxmega64B3__", 0x2000, 2, "x64b3") -+AVR_MCU ("atxmega64c3", ARCH_AVRXMEGA4, AVR_ISA_RMW, "__AVR_ATxmega64C3__", 0x2000, 2, "x64c3") -+AVR_MCU ("atxmega64d3", ARCH_AVRXMEGA4, AVR_ISA_NONE, "__AVR_ATxmega64D3__", 0x2000, 2, "x64d3") -+AVR_MCU ("atxmega64d4", ARCH_AVRXMEGA4, AVR_ISA_NONE, "__AVR_ATxmega64D4__", 0x2000, 2, "x64d4") ++AVR_MCU ("avrxmega4", ARCH_AVRXMEGA4, AVR_ISA_NONE, NULL, 0x2000, 0x0, 2, "x64a4") ++AVR_MCU ("atxmega64a3", ARCH_AVRXMEGA4, AVR_ISA_NONE, "__AVR_ATxmega64A3__", 0x2000, 0x0, 2, "x64a3") ++AVR_MCU ("atxmega64a3u", ARCH_AVRXMEGA4, AVR_ISA_RMW, "__AVR_ATxmega64A3U__", 0x2000, 0x0, 2, "x64a3u") ++AVR_MCU ("atxmega64a4u", ARCH_AVRXMEGA4, AVR_ISA_RMW, "__AVR_ATxmega64A4U__", 0x2000, 0x0, 2, "x64a4u") ++AVR_MCU ("atxmega64b1", ARCH_AVRXMEGA4, AVR_ISA_RMW, "__AVR_ATxmega64B1__", 0x2000, 0x0, 2, "x64b1") ++AVR_MCU ("atxmega64b3", ARCH_AVRXMEGA4, AVR_ISA_RMW, "__AVR_ATxmega64B3__", 0x2000, 0x0, 2, "x64b3") ++AVR_MCU ("atxmega64c3", ARCH_AVRXMEGA4, AVR_ISA_RMW, "__AVR_ATxmega64C3__", 0x2000, 0x0, 2, "x64c3") ++AVR_MCU ("atxmega64d3", ARCH_AVRXMEGA4, AVR_ISA_NONE, "__AVR_ATxmega64D3__", 0x2000, 0x0, 2, "x64d3") ++AVR_MCU ("atxmega64d4", ARCH_AVRXMEGA4, AVR_ISA_NONE, "__AVR_ATxmega64D4__", 0x2000, 0x0, 2, "x64d4") /* Xmega, 64K < Flash <= 128K, RAM > 64K */ -AVR_MCU ("avrxmega5", ARCH_AVRXMEGA5, NULL, 0, 0, 0x2000, 2, "x64a1") -AVR_MCU ("atxmega64a1", ARCH_AVRXMEGA5, "__AVR_ATxmega64A1__", 0, 0, 0x2000, 2, "x64a1") -AVR_MCU ("atxmega64a1u", ARCH_AVRXMEGA5, "__AVR_ATxmega64A1U__", 0, 0, 0x2000, 2, "x64a1u") -+AVR_MCU ("avrxmega5", ARCH_AVRXMEGA5, AVR_ISA_NONE, NULL, 0x2000, 2, "x64a1") -+AVR_MCU ("atxmega64a1", ARCH_AVRXMEGA5, AVR_ISA_NONE, "__AVR_ATxmega64A1__", 0x2000, 2, "x64a1") -+AVR_MCU ("atxmega64a1u", ARCH_AVRXMEGA5, AVR_ISA_RMW, "__AVR_ATxmega64A1U__", 0x2000, 2, "x64a1u") ++AVR_MCU ("avrxmega5", ARCH_AVRXMEGA5, AVR_ISA_NONE, NULL, 0x2000, 0x0, 2, "x64a1") ++AVR_MCU ("atxmega64a1", ARCH_AVRXMEGA5, AVR_ISA_NONE, "__AVR_ATxmega64A1__", 0x2000, 0x0, 2, "x64a1") ++AVR_MCU ("atxmega64a1u", ARCH_AVRXMEGA5, AVR_ISA_RMW, "__AVR_ATxmega64A1U__", 0x2000, 0x0, 2, "x64a1u") /* Xmega, 128K < Flash, RAM <= 64K */ -AVR_MCU ("avrxmega6", ARCH_AVRXMEGA6, NULL, 0, 0, 0x2000, 6, "x128a3") -AVR_MCU ("atxmega128a3", ARCH_AVRXMEGA6, "__AVR_ATxmega128A3__", 0, 0, 0x2000, 3, "x128a3") @@ -1473,39 +1511,39 @@ index 2a730ac..5797b9c 100644 -AVR_MCU ("atxmega128a1", ARCH_AVRXMEGA7, "__AVR_ATxmega128A1__", 0, 0, 0x2000, 3, "x128a1") -AVR_MCU ("atxmega128a1u", ARCH_AVRXMEGA7, "__AVR_ATxmega128A1U__", 0, 0, 0x2000, 3, "x128a1u") -AVR_MCU ("atxmega128a4u", ARCH_AVRXMEGA7, "__AVR_ATxmega128A4U__", 0, 0, 0x2000, 3, "x128a4u") -+AVR_MCU ("avrxmega6", ARCH_AVRXMEGA6, AVR_ISA_NONE, NULL, 0x2000, 6, "x128a3") -+AVR_MCU ("atxmega128a3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega128A3__", 0x2000, 3, "x128a3") -+AVR_MCU ("atxmega128a3u", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega128A3U__", 0x2000, 3, "x128a3u") -+AVR_MCU ("atxmega128b1", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega128B1__", 0x2000, 3, "x128b1") -+AVR_MCU ("atxmega128b3", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega128B3__", 0x2000, 3, "x128b3") -+AVR_MCU ("atxmega128c3", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega128C3__", 0x2000, 3, "x128c3") -+AVR_MCU ("atxmega128d3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega128D3__", 0x2000, 3, "x128d3") -+AVR_MCU ("atxmega128d4", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega128D4__", 0x2000, 3, "x128d4") -+AVR_MCU ("atxmega192a3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega192A3__", 0x2000, 4, "x192a3") -+AVR_MCU ("atxmega192a3u", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega192A3U__", 0x2000, 4, "x192a3u") -+AVR_MCU ("atxmega192c3", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega192C3__", 0x2000, 4, "x192c3") -+AVR_MCU ("atxmega192d3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega192D3__", 0x2000, 4, "x192d3") -+AVR_MCU ("atxmega256a3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega256A3__", 0x2000, 5, "x256a3") -+AVR_MCU ("atxmega256a3b", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega256A3B__", 0x2000, 5, "x256a3b") -+AVR_MCU ("atxmega256a3bu", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega256A3BU__", 0x2000, 5, "x256a3bu") -+AVR_MCU ("atxmega256a3u", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega256A3U__", 0x2000, 5, "x256a3u") -+AVR_MCU ("atxmega256c3", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega256C3__", 0x2000, 5, "x256c3") -+AVR_MCU ("atxmega256d3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega256D3__", 0x2000, 5, "x256d3") -+AVR_MCU ("atxmega384c3", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega384C3__", 0x2000, 6, "x384c3") -+AVR_MCU ("atxmega384d3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega384D3__", 0x2000, 6, "x384d3") ++AVR_MCU ("avrxmega6", ARCH_AVRXMEGA6, AVR_ISA_NONE, NULL, 0x2000, 0x0, 6, "x128a3") ++AVR_MCU ("atxmega128a3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega128A3__", 0x2000, 0x0, 3, "x128a3") ++AVR_MCU ("atxmega128a3u", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega128A3U__", 0x2000, 0x0, 3, "x128a3u") ++AVR_MCU ("atxmega128b1", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega128B1__", 0x2000, 0x0, 3, "x128b1") ++AVR_MCU ("atxmega128b3", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega128B3__", 0x2000, 0x0, 3, "x128b3") ++AVR_MCU ("atxmega128c3", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega128C3__", 0x2000, 0x0, 3, "x128c3") ++AVR_MCU ("atxmega128d3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega128D3__", 0x2000, 0x0, 3, "x128d3") ++AVR_MCU ("atxmega128d4", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega128D4__", 0x2000, 0x0, 3, "x128d4") ++AVR_MCU ("atxmega192a3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega192A3__", 0x2000, 0x0, 4, "x192a3") ++AVR_MCU ("atxmega192a3u", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega192A3U__", 0x2000, 0x0, 4, "x192a3u") ++AVR_MCU ("atxmega192c3", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega192C3__", 0x2000, 0x0, 4, "x192c3") ++AVR_MCU ("atxmega192d3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega192D3__", 0x2000, 0x0, 4, "x192d3") ++AVR_MCU ("atxmega256a3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega256A3__", 0x2000, 0x0, 5, "x256a3") ++AVR_MCU ("atxmega256a3b", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega256A3B__", 0x2000, 0x0, 5, "x256a3b") ++AVR_MCU ("atxmega256a3bu", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega256A3BU__", 0x2000, 0x0, 5, "x256a3bu") ++AVR_MCU ("atxmega256a3u", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega256A3U__", 0x2000, 0x0, 5, "x256a3u") ++AVR_MCU ("atxmega256c3", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega256C3__", 0x2000, 0x0, 5, "x256c3") ++AVR_MCU ("atxmega256d3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega256D3__", 0x2000, 0x0, 5, "x256d3") ++AVR_MCU ("atxmega384c3", ARCH_AVRXMEGA6, AVR_ISA_RMW, "__AVR_ATxmega384C3__", 0x2000, 0x0, 6, "x384c3") ++AVR_MCU ("atxmega384d3", ARCH_AVRXMEGA6, AVR_ISA_NONE, "__AVR_ATxmega384D3__", 0x2000, 0x0, 6, "x384d3") +/* Xmega, >= 128K, <= 256K FLASH, > 64K RAM. */ -+AVR_MCU ("avrxmega7", ARCH_AVRXMEGA7, AVR_ISA_NONE, NULL, 0x2000, 3, "x128a1") -+AVR_MCU ("atxmega128a1", ARCH_AVRXMEGA7, AVR_ISA_NONE, "__AVR_ATxmega128A1__", 0x2000, 3, "x128a1") -+AVR_MCU ("atxmega128a1u", ARCH_AVRXMEGA7, AVR_ISA_RMW, "__AVR_ATxmega128A1U__", 0x2000, 3, "x128a1u") -+AVR_MCU ("atxmega128a4u", ARCH_AVRXMEGA7, AVR_ISA_RMW, "__AVR_ATxmega128A4U__", 0x2000, 3, "x128a4u") ++AVR_MCU ("avrxmega7", ARCH_AVRXMEGA7, AVR_ISA_NONE, NULL, 0x2000, 0x0, 3, "x128a1") ++AVR_MCU ("atxmega128a1", ARCH_AVRXMEGA7, AVR_ISA_NONE, "__AVR_ATxmega128A1__", 0x2000, 0x0, 3, "x128a1") ++AVR_MCU ("atxmega128a1u", ARCH_AVRXMEGA7, AVR_ISA_RMW, "__AVR_ATxmega128A1U__", 0x2000, 0x0, 3, "x128a1u") ++AVR_MCU ("atxmega128a4u", ARCH_AVRXMEGA7, AVR_ISA_RMW, "__AVR_ATxmega128A4U__", 0x2000, 0x0, 3, "x128a4u") +/* Tiny family */ -+AVR_MCU ("avrtiny", ARCH_AVRTINY, AVR_ISA_NONE, NULL, 0x0040, 1, "tn10") -+AVR_MCU ("attiny4", ARCH_AVRTINY, AVR_ISA_NONE, "__AVR_ATtiny4__", 0x0040, 1, "tn4") -+AVR_MCU ("attiny5", ARCH_AVRTINY, AVR_ISA_NONE, "__AVR_ATtiny5__", 0x0040, 1, "tn5") -+AVR_MCU ("attiny9", ARCH_AVRTINY, AVR_ISA_NONE, "__AVR_ATtiny9__", 0x0040, 1, "tn9") -+AVR_MCU ("attiny10", ARCH_AVRTINY, AVR_ISA_NONE, "__AVR_ATtiny10__", 0x0040, 1, "tn10") -+AVR_MCU ("attiny20", ARCH_AVRTINY, AVR_ISA_NONE, "__AVR_ATtiny20__", 0x0040, 1, "tn20") -+AVR_MCU ("attiny40", ARCH_AVRTINY, AVR_ISA_NONE, "__AVR_ATtiny40__", 0x0040, 1, "tn40") ++AVR_MCU ("avrtiny", ARCH_AVRTINY, AVR_ISA_NONE, NULL, 0x0040, 0x0, 1, "tn10") ++AVR_MCU ("attiny4", ARCH_AVRTINY, AVR_ISA_NONE, "__AVR_ATtiny4__", 0x0040, 0x0, 1, "tn4") ++AVR_MCU ("attiny5", ARCH_AVRTINY, AVR_ISA_NONE, "__AVR_ATtiny5__", 0x0040, 0x0, 1, "tn5") ++AVR_MCU ("attiny9", ARCH_AVRTINY, AVR_ISA_NONE, "__AVR_ATtiny9__", 0x0040, 0x0, 1, "tn9") ++AVR_MCU ("attiny10", ARCH_AVRTINY, AVR_ISA_NONE, "__AVR_ATtiny10__", 0x0040, 0x0, 1, "tn10") ++AVR_MCU ("attiny20", ARCH_AVRTINY, AVR_ISA_NONE, "__AVR_ATtiny20__", 0x0040, 0x0, 1, "tn20") ++AVR_MCU ("attiny40", ARCH_AVRTINY, AVR_ISA_NONE, "__AVR_ATtiny40__", 0x0040, 0x0, 1, "tn40") /* Assembler only. */ -AVR_MCU ("avr1", ARCH_AVR1, NULL, 0, 0, 0x0060, 1, "s1200") -AVR_MCU ("at90s1200", ARCH_AVR1, "__AVR_AT90S1200__", 0, 0, 0x0060, 1, "s1200") @@ -1513,12 +1551,12 @@ index 2a730ac..5797b9c 100644 -AVR_MCU ("attiny12", ARCH_AVR1, "__AVR_ATtiny12__", 0, 0, 0x0060, 1, "tn12") -AVR_MCU ("attiny15", ARCH_AVR1, "__AVR_ATtiny15__", 0, 0, 0x0060, 1, "tn15") -AVR_MCU ("attiny28", ARCH_AVR1, "__AVR_ATtiny28__", 0, 0, 0x0060, 1, "tn28") -+AVR_MCU ("avr1", ARCH_AVR1, AVR_ISA_NONE, NULL, 0x0060, 1, "s1200") -+AVR_MCU ("at90s1200", ARCH_AVR1, AVR_ISA_NONE, "__AVR_AT90S1200__", 0x0060, 1, "s1200") -+AVR_MCU ("attiny11", ARCH_AVR1, AVR_ISA_NONE, "__AVR_ATtiny11__", 0x0060, 1, "tn11") -+AVR_MCU ("attiny12", ARCH_AVR1, AVR_ISA_NONE, "__AVR_ATtiny12__", 0x0060, 1, "tn12") -+AVR_MCU ("attiny15", ARCH_AVR1, AVR_ISA_NONE, "__AVR_ATtiny15__", 0x0060, 1, "tn15") -+AVR_MCU ("attiny28", ARCH_AVR1, AVR_ISA_NONE, "__AVR_ATtiny28__", 0x0060, 1, "tn28") ++AVR_MCU ("avr1", ARCH_AVR1, AVR_ISA_NONE, NULL, 0x0060, 0x0, 1, "s1200") ++AVR_MCU ("at90s1200", ARCH_AVR1, AVR_ISA_NONE, "__AVR_AT90S1200__", 0x0060, 0x0, 1, "s1200") ++AVR_MCU ("attiny11", ARCH_AVR1, AVR_ISA_NONE, "__AVR_ATtiny11__", 0x0060, 0x0, 1, "tn11") ++AVR_MCU ("attiny12", ARCH_AVR1, AVR_ISA_NONE, "__AVR_ATtiny12__", 0x0060, 0x0, 1, "tn12") ++AVR_MCU ("attiny15", ARCH_AVR1, AVR_ISA_NONE, "__AVR_ATtiny15__", 0x0060, 0x0, 1, "tn15") ++AVR_MCU ("attiny28", ARCH_AVR1, AVR_ISA_NONE, "__AVR_ATtiny28__", 0x0060, 0x0, 1, "tn28") diff --git a/gcc/config/avr/avr-protos.h b/gcc/config/avr/avr-protos.h index 5246d06..f788bc9 100644 --- a/gcc/config/avr/avr-protos.h @@ -1560,7 +1598,7 @@ index 8e7278f..4137b06 100644 #define UINT64_TYPE (INT_TYPE_SIZE == 16 ? "long long unsigned int" : 0) diff --git a/gcc/config/avr/avr-tables.opt b/gcc/config/avr/avr-tables.opt -index 1a451bd..6ff2cbe 100644 +index 1a451bd..b5aa221 100644 --- a/gcc/config/avr/avr-tables.opt +++ b/gcc/config/avr/avr-tables.opt @@ -66,10 +66,10 @@ EnumValue @@ -1576,7 +1614,7 @@ index 1a451bd..6ff2cbe 100644 EnumValue Enum(avr_mcu) String(attiny13) Value(16) -@@ -99,676 +99,676 @@ EnumValue +@@ -99,710 +99,737 @@ EnumValue Enum(avr_mcu) String(attiny44a) Value(24) EnumValue @@ -1769,763 +1807,789 @@ index 1a451bd..6ff2cbe 100644 EnumValue -Enum(avr_mcu) String(at90pwm1) Value(72) -+Enum(avr_mcu) String(atmega88) Value(72) ++Enum(avr_mcu) String(atmega48pb) Value(72) EnumValue -Enum(avr_mcu) String(at90pwm2) Value(73) -+Enum(avr_mcu) String(atmega88a) Value(73) ++Enum(avr_mcu) String(atmega88) Value(73) EnumValue -Enum(avr_mcu) String(at90pwm2b) Value(74) -+Enum(avr_mcu) String(atmega88p) Value(74) ++Enum(avr_mcu) String(atmega88a) Value(74) EnumValue -Enum(avr_mcu) String(at90pwm3) Value(75) -+Enum(avr_mcu) String(atmega88pa) Value(75) ++Enum(avr_mcu) String(atmega88p) Value(75) EnumValue -Enum(avr_mcu) String(at90pwm3b) Value(76) -+Enum(avr_mcu) String(atmega8515) Value(76) ++Enum(avr_mcu) String(atmega88pa) Value(76) EnumValue -Enum(avr_mcu) String(at90pwm81) Value(77) -+Enum(avr_mcu) String(atmega8535) Value(77) ++Enum(avr_mcu) String(atmega88pb) Value(77) EnumValue -Enum(avr_mcu) String(avr5) Value(78) -+Enum(avr_mcu) String(atmega8hva) Value(78) ++Enum(avr_mcu) String(atmega8515) Value(78) EnumValue -Enum(avr_mcu) String(ata5790) Value(79) -+Enum(avr_mcu) String(at90pwm1) Value(79) ++Enum(avr_mcu) String(atmega8535) Value(79) EnumValue -Enum(avr_mcu) String(ata5790n) Value(80) -+Enum(avr_mcu) String(at90pwm2) Value(80) ++Enum(avr_mcu) String(atmega8hva) Value(80) EnumValue -Enum(avr_mcu) String(ata5795) Value(81) -+Enum(avr_mcu) String(at90pwm2b) Value(81) ++Enum(avr_mcu) String(at90pwm1) Value(81) EnumValue -Enum(avr_mcu) String(atmega16) Value(82) -+Enum(avr_mcu) String(at90pwm3) Value(82) ++Enum(avr_mcu) String(at90pwm2) Value(82) EnumValue -Enum(avr_mcu) String(atmega16a) Value(83) -+Enum(avr_mcu) String(at90pwm3b) Value(83) ++Enum(avr_mcu) String(at90pwm2b) Value(83) EnumValue -Enum(avr_mcu) String(atmega161) Value(84) -+Enum(avr_mcu) String(at90pwm81) Value(84) ++Enum(avr_mcu) String(at90pwm3) Value(84) EnumValue -Enum(avr_mcu) String(atmega162) Value(85) -+Enum(avr_mcu) String(avr5) Value(85) ++Enum(avr_mcu) String(at90pwm3b) Value(85) EnumValue -Enum(avr_mcu) String(atmega163) Value(86) -+Enum(avr_mcu) String(ata5702m322) Value(86) ++Enum(avr_mcu) String(at90pwm81) Value(86) EnumValue -Enum(avr_mcu) String(atmega164a) Value(87) -+Enum(avr_mcu) String(ata5790) Value(87) ++Enum(avr_mcu) String(avr5) Value(87) EnumValue -Enum(avr_mcu) String(atmega164p) Value(88) -+Enum(avr_mcu) String(ata5790n) Value(88) ++Enum(avr_mcu) String(ata5702m322) Value(88) EnumValue -Enum(avr_mcu) String(atmega164pa) Value(89) -+Enum(avr_mcu) String(ata5795) Value(89) ++Enum(avr_mcu) String(ata5782) Value(89) EnumValue -Enum(avr_mcu) String(atmega165) Value(90) -+Enum(avr_mcu) String(ata6613c) Value(90) ++Enum(avr_mcu) String(ata5790) Value(90) EnumValue -Enum(avr_mcu) String(atmega165a) Value(91) -+Enum(avr_mcu) String(ata6614q) Value(91) ++Enum(avr_mcu) String(ata5790n) Value(91) EnumValue -Enum(avr_mcu) String(atmega165p) Value(92) -+Enum(avr_mcu) String(atmega16) Value(92) ++Enum(avr_mcu) String(ata5795) Value(92) EnumValue -Enum(avr_mcu) String(atmega165pa) Value(93) -+Enum(avr_mcu) String(atmega16a) Value(93) ++Enum(avr_mcu) String(ata5831) Value(93) EnumValue -Enum(avr_mcu) String(atmega168) Value(94) -+Enum(avr_mcu) String(atmega161) Value(94) ++Enum(avr_mcu) String(ata6613c) Value(94) EnumValue -Enum(avr_mcu) String(atmega168a) Value(95) -+Enum(avr_mcu) String(atmega162) Value(95) ++Enum(avr_mcu) String(ata6614q) Value(95) EnumValue -Enum(avr_mcu) String(atmega168p) Value(96) -+Enum(avr_mcu) String(atmega163) Value(96) ++Enum(avr_mcu) String(atmega16) Value(96) EnumValue -Enum(avr_mcu) String(atmega168pa) Value(97) -+Enum(avr_mcu) String(atmega164a) Value(97) ++Enum(avr_mcu) String(atmega16a) Value(97) EnumValue -Enum(avr_mcu) String(atmega169) Value(98) -+Enum(avr_mcu) String(atmega164p) Value(98) ++Enum(avr_mcu) String(atmega161) Value(98) EnumValue -Enum(avr_mcu) String(atmega169a) Value(99) -+Enum(avr_mcu) String(atmega164pa) Value(99) ++Enum(avr_mcu) String(atmega162) Value(99) EnumValue -Enum(avr_mcu) String(atmega169p) Value(100) -+Enum(avr_mcu) String(atmega165) Value(100) ++Enum(avr_mcu) String(atmega163) Value(100) EnumValue -Enum(avr_mcu) String(atmega169pa) Value(101) -+Enum(avr_mcu) String(atmega165a) Value(101) ++Enum(avr_mcu) String(atmega164a) Value(101) EnumValue -Enum(avr_mcu) String(atmega16hva) Value(102) -+Enum(avr_mcu) String(atmega165p) Value(102) ++Enum(avr_mcu) String(atmega164p) Value(102) EnumValue -Enum(avr_mcu) String(atmega16hvb) Value(103) -+Enum(avr_mcu) String(atmega165pa) Value(103) ++Enum(avr_mcu) String(atmega164pa) Value(103) EnumValue -Enum(avr_mcu) String(atmega16hvbrevb) Value(104) -+Enum(avr_mcu) String(atmega168) Value(104) ++Enum(avr_mcu) String(atmega165) Value(104) EnumValue -Enum(avr_mcu) String(atmega16m1) Value(105) -+Enum(avr_mcu) String(atmega168a) Value(105) ++Enum(avr_mcu) String(atmega165a) Value(105) EnumValue -Enum(avr_mcu) String(atmega16u4) Value(106) -+Enum(avr_mcu) String(atmega168p) Value(106) ++Enum(avr_mcu) String(atmega165p) Value(106) EnumValue -Enum(avr_mcu) String(atmega26hvg) Value(107) -+Enum(avr_mcu) String(atmega168pa) Value(107) ++Enum(avr_mcu) String(atmega165pa) Value(107) EnumValue -Enum(avr_mcu) String(atmega32a) Value(108) -+Enum(avr_mcu) String(atmega169) Value(108) ++Enum(avr_mcu) String(atmega168) Value(108) EnumValue -Enum(avr_mcu) String(atmega32) Value(109) -+Enum(avr_mcu) String(atmega169a) Value(109) ++Enum(avr_mcu) String(atmega168a) Value(109) EnumValue -Enum(avr_mcu) String(atmega32a) Value(110) -+Enum(avr_mcu) String(atmega169p) Value(110) ++Enum(avr_mcu) String(atmega168p) Value(110) EnumValue -Enum(avr_mcu) String(atmega323) Value(111) -+Enum(avr_mcu) String(atmega169pa) Value(111) ++Enum(avr_mcu) String(atmega168pa) Value(111) EnumValue -Enum(avr_mcu) String(atmega324a) Value(112) -+Enum(avr_mcu) String(atmega16hvb) Value(112) ++Enum(avr_mcu) String(atmega168pb) Value(112) EnumValue -Enum(avr_mcu) String(atmega324p) Value(113) -+Enum(avr_mcu) String(atmega16hvbrevb) Value(113) ++Enum(avr_mcu) String(atmega169) Value(113) EnumValue -Enum(avr_mcu) String(atmega324pa) Value(114) -+Enum(avr_mcu) String(atmega16m1) Value(114) ++Enum(avr_mcu) String(atmega169a) Value(114) EnumValue -Enum(avr_mcu) String(atmega325) Value(115) -+Enum(avr_mcu) String(atmega16u4) Value(115) ++Enum(avr_mcu) String(atmega169p) Value(115) EnumValue -Enum(avr_mcu) String(atmega325a) Value(116) -+Enum(avr_mcu) String(atmega32a) Value(116) ++Enum(avr_mcu) String(atmega169pa) Value(116) EnumValue -Enum(avr_mcu) String(atmega325p) Value(117) -+Enum(avr_mcu) String(atmega32) Value(117) ++Enum(avr_mcu) String(atmega16hvb) Value(117) EnumValue -Enum(avr_mcu) String(atmega3250) Value(118) -+Enum(avr_mcu) String(atmega323) Value(118) ++Enum(avr_mcu) String(atmega16hvbrevb) Value(118) EnumValue -Enum(avr_mcu) String(atmega3250a) Value(119) -+Enum(avr_mcu) String(atmega324a) Value(119) ++Enum(avr_mcu) String(atmega16m1) Value(119) EnumValue -Enum(avr_mcu) String(atmega3250p) Value(120) -+Enum(avr_mcu) String(atmega324p) Value(120) ++Enum(avr_mcu) String(atmega16u4) Value(120) EnumValue -Enum(avr_mcu) String(atmega3250pa) Value(121) -+Enum(avr_mcu) String(atmega324pa) Value(121) ++Enum(avr_mcu) String(atmega32a) Value(121) EnumValue -Enum(avr_mcu) String(atmega328) Value(122) -+Enum(avr_mcu) String(atmega325) Value(122) ++Enum(avr_mcu) String(atmega32) Value(122) EnumValue -Enum(avr_mcu) String(atmega328p) Value(123) -+Enum(avr_mcu) String(atmega325a) Value(123) ++Enum(avr_mcu) String(atmega323) Value(123) EnumValue -Enum(avr_mcu) String(atmega329) Value(124) -+Enum(avr_mcu) String(atmega325p) Value(124) ++Enum(avr_mcu) String(atmega324a) Value(124) EnumValue -Enum(avr_mcu) String(atmega329a) Value(125) -+Enum(avr_mcu) String(atmega325pa) Value(125) ++Enum(avr_mcu) String(atmega324p) Value(125) EnumValue -Enum(avr_mcu) String(atmega329p) Value(126) -+Enum(avr_mcu) String(atmega3250) Value(126) ++Enum(avr_mcu) String(atmega324pa) Value(126) EnumValue -Enum(avr_mcu) String(atmega329pa) Value(127) -+Enum(avr_mcu) String(atmega3250a) Value(127) ++Enum(avr_mcu) String(atmega325) Value(127) EnumValue -Enum(avr_mcu) String(atmega3290) Value(128) -+Enum(avr_mcu) String(atmega3250p) Value(128) ++Enum(avr_mcu) String(atmega325a) Value(128) EnumValue -Enum(avr_mcu) String(atmega3290a) Value(129) -+Enum(avr_mcu) String(atmega3250pa) Value(129) ++Enum(avr_mcu) String(atmega325p) Value(129) EnumValue -Enum(avr_mcu) String(atmega3290p) Value(130) -+Enum(avr_mcu) String(atmega328) Value(130) ++Enum(avr_mcu) String(atmega325pa) Value(130) EnumValue -Enum(avr_mcu) String(atmega3290pa) Value(131) -+Enum(avr_mcu) String(atmega328p) Value(131) ++Enum(avr_mcu) String(atmega3250) Value(131) EnumValue -Enum(avr_mcu) String(atmega32c1) Value(132) -+Enum(avr_mcu) String(atmega329) Value(132) ++Enum(avr_mcu) String(atmega3250a) Value(132) EnumValue -Enum(avr_mcu) String(atmega32m1) Value(133) -+Enum(avr_mcu) String(atmega329a) Value(133) ++Enum(avr_mcu) String(atmega3250p) Value(133) EnumValue -Enum(avr_mcu) String(atmega32u4) Value(134) -+Enum(avr_mcu) String(atmega329p) Value(134) ++Enum(avr_mcu) String(atmega3250pa) Value(134) EnumValue -Enum(avr_mcu) String(atmega32u6) Value(135) -+Enum(avr_mcu) String(atmega329pa) Value(135) ++Enum(avr_mcu) String(atmega328) Value(135) EnumValue -Enum(avr_mcu) String(atmega406) Value(136) -+Enum(avr_mcu) String(atmega3290) Value(136) ++Enum(avr_mcu) String(atmega328p) Value(136) EnumValue -Enum(avr_mcu) String(atmega64) Value(137) -+Enum(avr_mcu) String(atmega3290a) Value(137) ++Enum(avr_mcu) String(atmega329) Value(137) EnumValue -Enum(avr_mcu) String(atmega64a) Value(138) -+Enum(avr_mcu) String(atmega3290p) Value(138) ++Enum(avr_mcu) String(atmega329a) Value(138) EnumValue -Enum(avr_mcu) String(atmega640) Value(139) -+Enum(avr_mcu) String(atmega3290pa) Value(139) ++Enum(avr_mcu) String(atmega329p) Value(139) EnumValue -Enum(avr_mcu) String(atmega644) Value(140) -+Enum(avr_mcu) String(atmega32c1) Value(140) ++Enum(avr_mcu) String(atmega329pa) Value(140) EnumValue -Enum(avr_mcu) String(atmega644a) Value(141) -+Enum(avr_mcu) String(atmega32m1) Value(141) ++Enum(avr_mcu) String(atmega3290) Value(141) EnumValue -Enum(avr_mcu) String(atmega644p) Value(142) -+Enum(avr_mcu) String(atmega32u4) Value(142) ++Enum(avr_mcu) String(atmega3290a) Value(142) EnumValue -Enum(avr_mcu) String(atmega644pa) Value(143) -+Enum(avr_mcu) String(atmega32u6) Value(143) ++Enum(avr_mcu) String(atmega3290p) Value(143) EnumValue -Enum(avr_mcu) String(atmega645) Value(144) -+Enum(avr_mcu) String(atmega406) Value(144) ++Enum(avr_mcu) String(atmega3290pa) Value(144) EnumValue -Enum(avr_mcu) String(atmega645a) Value(145) -+Enum(avr_mcu) String(atmega64) Value(145) ++Enum(avr_mcu) String(atmega32c1) Value(145) EnumValue -Enum(avr_mcu) String(atmega645p) Value(146) -+Enum(avr_mcu) String(atmega64a) Value(146) ++Enum(avr_mcu) String(atmega32m1) Value(146) EnumValue -Enum(avr_mcu) String(atmega6450) Value(147) -+Enum(avr_mcu) String(atmega640) Value(147) ++Enum(avr_mcu) String(atmega32u4) Value(147) EnumValue -Enum(avr_mcu) String(atmega6450a) Value(148) -+Enum(avr_mcu) String(atmega644) Value(148) ++Enum(avr_mcu) String(atmega32u6) Value(148) EnumValue -Enum(avr_mcu) String(atmega6450p) Value(149) -+Enum(avr_mcu) String(atmega644a) Value(149) ++Enum(avr_mcu) String(atmega406) Value(149) EnumValue -Enum(avr_mcu) String(atmega649) Value(150) -+Enum(avr_mcu) String(atmega644p) Value(150) ++Enum(avr_mcu) String(atmega64) Value(150) EnumValue -Enum(avr_mcu) String(atmega649a) Value(151) -+Enum(avr_mcu) String(atmega644pa) Value(151) ++Enum(avr_mcu) String(atmega64a) Value(151) EnumValue -Enum(avr_mcu) String(atmega649p) Value(152) -+Enum(avr_mcu) String(atmega645) Value(152) ++Enum(avr_mcu) String(atmega640) Value(152) EnumValue -Enum(avr_mcu) String(atmega6490) Value(153) -+Enum(avr_mcu) String(atmega645a) Value(153) ++Enum(avr_mcu) String(atmega644) Value(153) EnumValue -Enum(avr_mcu) String(atmega16hva) Value(154) -+Enum(avr_mcu) String(atmega645p) Value(154) ++Enum(avr_mcu) String(atmega644a) Value(154) EnumValue -Enum(avr_mcu) String(atmega16hva2) Value(155) -+Enum(avr_mcu) String(atmega6450) Value(155) ++Enum(avr_mcu) String(atmega644p) Value(155) EnumValue -Enum(avr_mcu) String(atmega16hvb) Value(156) -+Enum(avr_mcu) String(atmega6450a) Value(156) ++Enum(avr_mcu) String(atmega644pa) Value(156) EnumValue -Enum(avr_mcu) String(atmega32hvb) Value(157) -+Enum(avr_mcu) String(atmega6450p) Value(157) ++Enum(avr_mcu) String(atmega645) Value(157) EnumValue -Enum(avr_mcu) String(atmega6490a) Value(158) -+Enum(avr_mcu) String(atmega649) Value(158) ++Enum(avr_mcu) String(atmega645a) Value(158) EnumValue -Enum(avr_mcu) String(atmega6490p) Value(159) -+Enum(avr_mcu) String(atmega649a) Value(159) ++Enum(avr_mcu) String(atmega645p) Value(159) EnumValue -Enum(avr_mcu) String(atmega64c1) Value(160) -+Enum(avr_mcu) String(atmega649p) Value(160) ++Enum(avr_mcu) String(atmega6450) Value(160) EnumValue -Enum(avr_mcu) String(atmega64m1) Value(161) -+Enum(avr_mcu) String(atmega6490) Value(161) ++Enum(avr_mcu) String(atmega6450a) Value(161) EnumValue -Enum(avr_mcu) String(atmega64hve) Value(162) -+Enum(avr_mcu) String(atmega16hva) Value(162) ++Enum(avr_mcu) String(atmega6450p) Value(162) EnumValue -Enum(avr_mcu) String(atmega64rfa2) Value(163) -+Enum(avr_mcu) String(atmega16hva2) Value(163) ++Enum(avr_mcu) String(atmega649) Value(163) EnumValue -Enum(avr_mcu) String(atmega64rfr2) Value(164) -+Enum(avr_mcu) String(atmega32hvb) Value(164) ++Enum(avr_mcu) String(atmega649a) Value(164) EnumValue -Enum(avr_mcu) String(atmega32hvb) Value(165) -+Enum(avr_mcu) String(atmega6490a) Value(165) ++Enum(avr_mcu) String(atmega649p) Value(165) EnumValue -Enum(avr_mcu) String(atmega32hvbrevb) Value(166) -+Enum(avr_mcu) String(atmega6490p) Value(166) ++Enum(avr_mcu) String(atmega6490) Value(166) EnumValue -Enum(avr_mcu) String(atmega16hva2) Value(167) -+Enum(avr_mcu) String(atmega64c1) Value(167) ++Enum(avr_mcu) String(atmega16hva) Value(167) EnumValue -Enum(avr_mcu) String(atmega48hvf) Value(168) -+Enum(avr_mcu) String(atmega64m1) Value(168) ++Enum(avr_mcu) String(atmega16hva2) Value(168) EnumValue -Enum(avr_mcu) String(at90can32) Value(169) -+Enum(avr_mcu) String(atmega64hve) Value(169) ++Enum(avr_mcu) String(atmega32hvb) Value(169) EnumValue -Enum(avr_mcu) String(at90can64) Value(170) -+Enum(avr_mcu) String(atmega64hve2) Value(170) ++Enum(avr_mcu) String(atmega6490a) Value(170) EnumValue -Enum(avr_mcu) String(at90pwm161) Value(171) -+Enum(avr_mcu) String(atmega64rfr2) Value(171) ++Enum(avr_mcu) String(atmega6490p) Value(171) EnumValue -Enum(avr_mcu) String(at90pwm216) Value(172) -+Enum(avr_mcu) String(atmega644rfr2) Value(172) ++Enum(avr_mcu) String(atmega64c1) Value(172) EnumValue -Enum(avr_mcu) String(at90pwm316) Value(173) -+Enum(avr_mcu) String(atmega32hvbrevb) Value(173) ++Enum(avr_mcu) String(atmega64m1) Value(173) EnumValue -Enum(avr_mcu) String(atmega32c1) Value(174) -+Enum(avr_mcu) String(at90can32) Value(174) ++Enum(avr_mcu) String(atmega64hve) Value(174) EnumValue -Enum(avr_mcu) String(atmega64c1) Value(175) -+Enum(avr_mcu) String(at90can64) Value(175) ++Enum(avr_mcu) String(atmega64hve2) Value(175) EnumValue -Enum(avr_mcu) String(atmega16m1) Value(176) -+Enum(avr_mcu) String(at90pwm161) Value(176) ++Enum(avr_mcu) String(atmega64rfr2) Value(176) EnumValue -Enum(avr_mcu) String(atmega32m1) Value(177) -+Enum(avr_mcu) String(at90pwm216) Value(177) ++Enum(avr_mcu) String(atmega644rfr2) Value(177) EnumValue -Enum(avr_mcu) String(atmega64m1) Value(178) -+Enum(avr_mcu) String(at90pwm316) Value(178) ++Enum(avr_mcu) String(atmega32hvbrevb) Value(178) EnumValue -Enum(avr_mcu) String(atmega16u4) Value(179) -+Enum(avr_mcu) String(at90scr100) Value(179) ++Enum(avr_mcu) String(at90can32) Value(179) EnumValue -Enum(avr_mcu) String(atmega32u4) Value(180) -+Enum(avr_mcu) String(at90usb646) Value(180) ++Enum(avr_mcu) String(at90can64) Value(180) EnumValue -Enum(avr_mcu) String(atmega32u6) Value(181) -+Enum(avr_mcu) String(at90usb647) Value(181) ++Enum(avr_mcu) String(at90pwm161) Value(181) EnumValue -Enum(avr_mcu) String(at90scr100) Value(182) -+Enum(avr_mcu) String(at94k) Value(182) ++Enum(avr_mcu) String(at90pwm216) Value(182) EnumValue -Enum(avr_mcu) String(at90usb646) Value(183) -+Enum(avr_mcu) String(m3000) Value(183) ++Enum(avr_mcu) String(at90pwm316) Value(183) EnumValue -Enum(avr_mcu) String(at90usb647) Value(184) -+Enum(avr_mcu) String(avr51) Value(184) ++Enum(avr_mcu) String(at90scr100) Value(184) EnumValue -Enum(avr_mcu) String(at94k) Value(185) -+Enum(avr_mcu) String(atmega128) Value(185) ++Enum(avr_mcu) String(at90usb646) Value(185) EnumValue -Enum(avr_mcu) String(m3000) Value(186) -+Enum(avr_mcu) String(atmega128a) Value(186) ++Enum(avr_mcu) String(at90usb647) Value(186) EnumValue -Enum(avr_mcu) String(avr51) Value(187) -+Enum(avr_mcu) String(atmega1280) Value(187) ++Enum(avr_mcu) String(at94k) Value(187) EnumValue -Enum(avr_mcu) String(atmega128) Value(188) -+Enum(avr_mcu) String(atmega1281) Value(188) ++Enum(avr_mcu) String(m3000) Value(188) EnumValue -Enum(avr_mcu) String(atmega128a) Value(189) -+Enum(avr_mcu) String(atmega1284) Value(189) ++Enum(avr_mcu) String(avr51) Value(189) EnumValue -Enum(avr_mcu) String(atmega1280) Value(190) -+Enum(avr_mcu) String(atmega1284p) Value(190) ++Enum(avr_mcu) String(atmega128) Value(190) EnumValue -Enum(avr_mcu) String(atmega1281) Value(191) -+Enum(avr_mcu) String(atmega128rfa1) Value(191) ++Enum(avr_mcu) String(atmega128a) Value(191) EnumValue -Enum(avr_mcu) String(atmega1284) Value(192) -+Enum(avr_mcu) String(atmega128rfr2) Value(192) ++Enum(avr_mcu) String(atmega1280) Value(192) EnumValue -Enum(avr_mcu) String(atmega1284p) Value(193) -+Enum(avr_mcu) String(atmega1284rfr2) Value(193) ++Enum(avr_mcu) String(atmega1281) Value(193) EnumValue -Enum(avr_mcu) String(atmega128rfa1) Value(194) -+Enum(avr_mcu) String(at90can128) Value(194) ++Enum(avr_mcu) String(atmega1284) Value(194) EnumValue -Enum(avr_mcu) String(at90can128) Value(195) -+Enum(avr_mcu) String(at90usb1286) Value(195) ++Enum(avr_mcu) String(atmega1284p) Value(195) EnumValue -Enum(avr_mcu) String(at90usb1286) Value(196) -+Enum(avr_mcu) String(at90usb1287) Value(196) ++Enum(avr_mcu) String(atmega128rfa1) Value(196) EnumValue -Enum(avr_mcu) String(at90usb1287) Value(197) -+Enum(avr_mcu) String(avr6) Value(197) ++Enum(avr_mcu) String(atmega128rfr2) Value(197) EnumValue -Enum(avr_mcu) String(avr6) Value(198) -+Enum(avr_mcu) String(atmega2560) Value(198) ++Enum(avr_mcu) String(atmega1284rfr2) Value(198) EnumValue -Enum(avr_mcu) String(atmega2560) Value(199) -+Enum(avr_mcu) String(atmega2561) Value(199) ++Enum(avr_mcu) String(at90can128) Value(199) EnumValue -Enum(avr_mcu) String(atmega2561) Value(200) -+Enum(avr_mcu) String(atmega256rfr2) Value(200) ++Enum(avr_mcu) String(at90usb1286) Value(200) EnumValue -Enum(avr_mcu) String(avrxmega2) Value(201) -+Enum(avr_mcu) String(atmega2564rfr2) Value(201) ++Enum(avr_mcu) String(at90usb1287) Value(201) EnumValue -Enum(avr_mcu) String(atxmega16a4) Value(202) -+Enum(avr_mcu) String(avr7) Value(202) ++Enum(avr_mcu) String(avr6) Value(202) EnumValue -Enum(avr_mcu) String(atxmega16d4) Value(203) -+Enum(avr_mcu) String(ata5782) Value(203) ++Enum(avr_mcu) String(atmega2560) Value(203) EnumValue -Enum(avr_mcu) String(atxmega16x1) Value(204) -+Enum(avr_mcu) String(ata5831) Value(204) ++Enum(avr_mcu) String(atmega2561) Value(204) EnumValue -Enum(avr_mcu) String(atxmega32a4) Value(205) -+Enum(avr_mcu) String(avrxmega2) Value(205) ++Enum(avr_mcu) String(atmega256rfr2) Value(205) EnumValue -Enum(avr_mcu) String(atxmega32d4) Value(206) -+Enum(avr_mcu) String(atxmega8e5) Value(206) ++Enum(avr_mcu) String(atmega2564rfr2) Value(206) EnumValue -Enum(avr_mcu) String(atxmega32x1) Value(207) -+Enum(avr_mcu) String(atxmega16a4) Value(207) ++Enum(avr_mcu) String(avrxmega2) Value(207) EnumValue -Enum(avr_mcu) String(atmxt112sl) Value(208) -+Enum(avr_mcu) String(atxmega16a4u) Value(208) ++Enum(avr_mcu) String(atxmega8e5) Value(208) EnumValue -Enum(avr_mcu) String(atmxt224) Value(209) -+Enum(avr_mcu) String(atxmega16c4) Value(209) ++Enum(avr_mcu) String(atxmega16a4) Value(209) EnumValue -Enum(avr_mcu) String(atmxt224e) Value(210) -+Enum(avr_mcu) String(atxmega16d4) Value(210) ++Enum(avr_mcu) String(atxmega16a4u) Value(210) EnumValue -Enum(avr_mcu) String(atmxt336s) Value(211) -+Enum(avr_mcu) String(atxmega16e5) Value(211) ++Enum(avr_mcu) String(atxmega16c4) Value(211) EnumValue -Enum(avr_mcu) String(atxmega16a4u) Value(212) -+Enum(avr_mcu) String(atxmega32a4) Value(212) ++Enum(avr_mcu) String(atxmega16d4) Value(212) EnumValue -Enum(avr_mcu) String(atxmega16c4) Value(213) -+Enum(avr_mcu) String(atxmega32a4u) Value(213) ++Enum(avr_mcu) String(atxmega16e5) Value(213) EnumValue -Enum(avr_mcu) String(atxmega32a4u) Value(214) -+Enum(avr_mcu) String(atxmega32c3) Value(214) ++Enum(avr_mcu) String(atxmega32a4) Value(214) EnumValue - Enum(avr_mcu) String(atxmega32c4) Value(215) +-Enum(avr_mcu) String(atxmega32c4) Value(215) ++Enum(avr_mcu) String(atxmega32a4u) Value(215) EnumValue -Enum(avr_mcu) String(atxmega32e5) Value(216) -+Enum(avr_mcu) String(atxmega32d3) Value(216) ++Enum(avr_mcu) String(atxmega32c3) Value(216) EnumValue -Enum(avr_mcu) String(avrxmega4) Value(217) -+Enum(avr_mcu) String(atxmega32d4) Value(217) ++Enum(avr_mcu) String(atxmega32c4) Value(217) EnumValue -Enum(avr_mcu) String(atxmega64a3) Value(218) -+Enum(avr_mcu) String(atxmega32e5) Value(218) ++Enum(avr_mcu) String(atxmega32d3) Value(218) EnumValue -Enum(avr_mcu) String(atxmega64d3) Value(219) -+Enum(avr_mcu) String(avrxmega4) Value(219) ++Enum(avr_mcu) String(atxmega32d4) Value(219) EnumValue -Enum(avr_mcu) String(atxmega64a3u) Value(220) -+Enum(avr_mcu) String(atxmega64a3) Value(220) ++Enum(avr_mcu) String(atxmega32e5) Value(220) EnumValue -Enum(avr_mcu) String(atxmega64a4u) Value(221) -+Enum(avr_mcu) String(atxmega64a3u) Value(221) ++Enum(avr_mcu) String(avrxmega4) Value(221) EnumValue -Enum(avr_mcu) String(atxmega64b1) Value(222) -+Enum(avr_mcu) String(atxmega64a4u) Value(222) ++Enum(avr_mcu) String(atxmega64a3) Value(222) EnumValue -Enum(avr_mcu) String(atxmega64b3) Value(223) -+Enum(avr_mcu) String(atxmega64b1) Value(223) ++Enum(avr_mcu) String(atxmega64a3u) Value(223) EnumValue -Enum(avr_mcu) String(atxmega64c3) Value(224) -+Enum(avr_mcu) String(atxmega64b3) Value(224) ++Enum(avr_mcu) String(atxmega64a4u) Value(224) EnumValue -Enum(avr_mcu) String(atxmega64d4) Value(225) -+Enum(avr_mcu) String(atxmega64c3) Value(225) ++Enum(avr_mcu) String(atxmega64b1) Value(225) EnumValue -Enum(avr_mcu) String(avrxmega5) Value(226) -+Enum(avr_mcu) String(atxmega64d3) Value(226) ++Enum(avr_mcu) String(atxmega64b3) Value(226) EnumValue -Enum(avr_mcu) String(atxmega64a1) Value(227) -+Enum(avr_mcu) String(atxmega64d4) Value(227) ++Enum(avr_mcu) String(atxmega64c3) Value(227) EnumValue -Enum(avr_mcu) String(atxmega64a1u) Value(228) -+Enum(avr_mcu) String(avrxmega5) Value(228) ++Enum(avr_mcu) String(atxmega64d3) Value(228) EnumValue -Enum(avr_mcu) String(avrxmega6) Value(229) -+Enum(avr_mcu) String(atxmega64a1) Value(229) ++Enum(avr_mcu) String(atxmega64d4) Value(229) EnumValue -Enum(avr_mcu) String(atxmega128a3) Value(230) -+Enum(avr_mcu) String(atxmega64a1u) Value(230) ++Enum(avr_mcu) String(avrxmega5) Value(230) EnumValue -Enum(avr_mcu) String(atxmega128d3) Value(231) -+Enum(avr_mcu) String(avrxmega6) Value(231) ++Enum(avr_mcu) String(atxmega64a1) Value(231) EnumValue -Enum(avr_mcu) String(atxmega192a3) Value(232) -+Enum(avr_mcu) String(atxmega128a3) Value(232) ++Enum(avr_mcu) String(atxmega64a1u) Value(232) EnumValue -Enum(avr_mcu) String(atxmega192d3) Value(233) -+Enum(avr_mcu) String(atxmega128a3u) Value(233) ++Enum(avr_mcu) String(avrxmega6) Value(233) EnumValue -Enum(avr_mcu) String(atxmega256a3) Value(234) -+Enum(avr_mcu) String(atxmega128b1) Value(234) ++Enum(avr_mcu) String(atxmega128a3) Value(234) EnumValue -Enum(avr_mcu) String(atxmega256a3b) Value(235) -+Enum(avr_mcu) String(atxmega128b3) Value(235) ++Enum(avr_mcu) String(atxmega128a3u) Value(235) EnumValue -Enum(avr_mcu) String(atxmega256a3bu) Value(236) -+Enum(avr_mcu) String(atxmega128c3) Value(236) ++Enum(avr_mcu) String(atxmega128b1) Value(236) EnumValue -Enum(avr_mcu) String(atxmega256d3) Value(237) -+Enum(avr_mcu) String(atxmega128d3) Value(237) ++Enum(avr_mcu) String(atxmega128b3) Value(237) EnumValue -Enum(avr_mcu) String(atxmega128a3u) Value(238) -+Enum(avr_mcu) String(atxmega128d4) Value(238) ++Enum(avr_mcu) String(atxmega128c3) Value(238) EnumValue -Enum(avr_mcu) String(atxmega128b1) Value(239) -+Enum(avr_mcu) String(atxmega192a3) Value(239) ++Enum(avr_mcu) String(atxmega128d3) Value(239) EnumValue -Enum(avr_mcu) String(atxmega128b3) Value(240) -+Enum(avr_mcu) String(atxmega192a3u) Value(240) ++Enum(avr_mcu) String(atxmega128d4) Value(240) EnumValue -Enum(avr_mcu) String(atxmega128c3) Value(241) -+Enum(avr_mcu) String(atxmega192c3) Value(241) ++Enum(avr_mcu) String(atxmega192a3) Value(241) EnumValue -Enum(avr_mcu) String(atxmega128d4) Value(242) -+Enum(avr_mcu) String(atxmega192d3) Value(242) ++Enum(avr_mcu) String(atxmega192a3u) Value(242) EnumValue -Enum(avr_mcu) String(atmxt540s) Value(243) -+Enum(avr_mcu) String(atxmega256a3) Value(243) ++Enum(avr_mcu) String(atxmega192c3) Value(243) EnumValue -Enum(avr_mcu) String(atmxt540sreva) Value(244) -+Enum(avr_mcu) String(atxmega256a3b) Value(244) ++Enum(avr_mcu) String(atxmega192d3) Value(244) EnumValue -Enum(avr_mcu) String(atxmega192a3u) Value(245) -+Enum(avr_mcu) String(atxmega256a3bu) Value(245) ++Enum(avr_mcu) String(atxmega256a3) Value(245) EnumValue -Enum(avr_mcu) String(atxmega192c3) Value(246) -+Enum(avr_mcu) String(atxmega256a3u) Value(246) ++Enum(avr_mcu) String(atxmega256a3b) Value(246) EnumValue -Enum(avr_mcu) String(atxmega256a3u) Value(247) -+Enum(avr_mcu) String(atxmega256c3) Value(247) ++Enum(avr_mcu) String(atxmega256a3bu) Value(247) EnumValue -Enum(avr_mcu) String(atxmega256c3) Value(248) -+Enum(avr_mcu) String(atxmega256d3) Value(248) ++Enum(avr_mcu) String(atxmega256a3u) Value(248) EnumValue - Enum(avr_mcu) String(atxmega384c3) Value(249) -@@ -789,20 +789,41 @@ EnumValue - Enum(avr_mcu) String(atxmega128a4u) Value(254) +-Enum(avr_mcu) String(atxmega384c3) Value(249) ++Enum(avr_mcu) String(atxmega256c3) Value(249) + + EnumValue +-Enum(avr_mcu) String(atxmega384d3) Value(250) ++Enum(avr_mcu) String(atxmega256d3) Value(250) + + EnumValue +-Enum(avr_mcu) String(avrxmega7) Value(251) ++Enum(avr_mcu) String(atxmega384c3) Value(251) + + EnumValue +-Enum(avr_mcu) String(atxmega128a1) Value(252) ++Enum(avr_mcu) String(atxmega384d3) Value(252) + + EnumValue +-Enum(avr_mcu) String(atxmega128a1u) Value(253) ++Enum(avr_mcu) String(avrxmega7) Value(253) + + EnumValue +-Enum(avr_mcu) String(atxmega128a4u) Value(254) ++Enum(avr_mcu) String(atxmega128a1) Value(254) EnumValue -Enum(avr_mcu) String(avr1) Value(255) -+Enum(avr_mcu) String(avrtiny) Value(255) ++Enum(avr_mcu) String(atxmega128a1u) Value(255) EnumValue -Enum(avr_mcu) String(at90s1200) Value(256) -+Enum(avr_mcu) String(attiny4) Value(256) ++Enum(avr_mcu) String(atxmega128a4u) Value(256) EnumValue -Enum(avr_mcu) String(attiny11) Value(257) -+Enum(avr_mcu) String(attiny5) Value(257) ++Enum(avr_mcu) String(avrtiny) Value(257) EnumValue -Enum(avr_mcu) String(attiny12) Value(258) -+Enum(avr_mcu) String(attiny9) Value(258) ++Enum(avr_mcu) String(attiny4) Value(258) EnumValue -Enum(avr_mcu) String(attiny15) Value(259) -+Enum(avr_mcu) String(attiny10) Value(259) ++Enum(avr_mcu) String(attiny5) Value(259) EnumValue -Enum(avr_mcu) String(attiny28) Value(260) -+Enum(avr_mcu) String(attiny20) Value(260) ++Enum(avr_mcu) String(attiny9) Value(260) + +EnumValue -+Enum(avr_mcu) String(attiny40) Value(261) ++Enum(avr_mcu) String(attiny10) Value(261) + +EnumValue -+Enum(avr_mcu) String(avr1) Value(262) ++Enum(avr_mcu) String(attiny20) Value(262) + +EnumValue -+Enum(avr_mcu) String(at90s1200) Value(263) ++Enum(avr_mcu) String(attiny40) Value(263) + +EnumValue -+Enum(avr_mcu) String(attiny11) Value(264) ++Enum(avr_mcu) String(avr1) Value(264) + +EnumValue -+Enum(avr_mcu) String(attiny12) Value(265) ++Enum(avr_mcu) String(at90s1200) Value(265) + +EnumValue -+Enum(avr_mcu) String(attiny15) Value(266) ++Enum(avr_mcu) String(attiny11) Value(266) + +EnumValue -+Enum(avr_mcu) String(attiny28) Value(267) ++Enum(avr_mcu) String(attiny12) Value(267) ++ ++EnumValue ++Enum(avr_mcu) String(attiny15) Value(268) ++ ++EnumValue ++Enum(avr_mcu) String(attiny28) Value(269) diff --git a/gcc/config/avr/avr.c b/gcc/config/avr/avr.c -index c916d6b..c0bcb12 100644 +index c916d6b..c7e3467 100644 --- a/gcc/config/avr/avr.c +++ b/gcc/config/avr/avr.c @@ -77,6 +77,17 @@ @@ -3623,6 +3687,15 @@ index c916d6b..c0bcb12 100644 reg_base = REGNO (XEXP (base, 0)); if (disp > MAX_LD_OFFSET (GET_MODE (dest))) +@@ -3970,7 +4587,7 @@ avr_out_store_psi (rtx insn, rtx *op, int *plen) + "std Y+61,%A1" CR_TAB + "std Y+62,%B1" CR_TAB + "std Y+63,%C1" CR_TAB +- "sbiw r28,%o0-60", op, plen, -5); ++ "sbiw r28,%o0-61", op, plen, -5); + + return avr_asm_len ("subi r28,lo8(-%o0)" CR_TAB + "sbci r29,hi8(-%o0)" CR_TAB @@ -4074,6 +4691,30 @@ avr_out_movpsi (rtx insn, rtx *op, int *plen) return ""; } @@ -4487,7 +4560,7 @@ index c916d6b..c0bcb12 100644 #define TARGET_HARD_REGNO_SCRATCH_OK avr_hard_regno_scratch_ok #undef TARGET_CASE_VALUES_THRESHOLD diff --git a/gcc/config/avr/avr.h b/gcc/config/avr/avr.h -index f223a61..fa7c6e7 100644 +index f223a61..d76be98 100644 --- a/gcc/config/avr/avr.h +++ b/gcc/config/avr/avr.h @@ -88,8 +88,9 @@ enum @@ -4528,7 +4601,23 @@ index f223a61..fa7c6e7 100644 #define ELIMINABLE_REGS { \ {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ -@@ -510,7 +514,8 @@ extern const char *avr_device_to_sp8 (int argc, const char **argv); +@@ -489,6 +493,7 @@ typedef struct avr_args + extern const char *avr_device_to_as (int argc, const char **argv); + extern const char *avr_device_to_ld (int argc, const char **argv); + extern const char *avr_device_to_data_start (int argc, const char **argv); ++extern const char *avr_device_to_text_start (int argc, const char **argv); + extern const char *avr_device_to_startfiles (int argc, const char **argv); + extern const char *avr_device_to_devicelib (int argc, const char **argv); + extern const char *avr_device_to_sp8 (int argc, const char **argv); +@@ -497,6 +502,7 @@ extern const char *avr_device_to_sp8 (int argc, const char **argv); + { "device_to_as", avr_device_to_as }, \ + { "device_to_ld", avr_device_to_ld }, \ + { "device_to_data_start", avr_device_to_data_start }, \ ++ { "device_to_text_start", avr_device_to_text_start }, \ + { "device_to_startfile", avr_device_to_startfiles }, \ + { "device_to_devicelib", avr_device_to_devicelib }, \ + { "device_to_sp8", avr_device_to_sp8 }, +@@ -510,7 +516,8 @@ extern const char *avr_device_to_sp8 (int argc, const char **argv); %{!fenforce-eh-specs:-fno-enforce-eh-specs} \ %{!fexceptions:-fno-exceptions}" @@ -4538,7 +4627,17 @@ index f223a61..fa7c6e7 100644 #define LINK_SPEC "\ %{mrelax:--relax\ -@@ -571,6 +576,10 @@ struct GTY(()) machine_function +@@ -522,7 +529,8 @@ extern const char *avr_device_to_sp8 (int argc, const char **argv); + mmcu=at90can64*|\ + mmcu=at90usb64*:--pmem-wrap-around=64k}}}\ + %:device_to_ld(%{mmcu=*:%*})\ +-%:device_to_data_start(%{mmcu=*:%*})" ++%:device_to_data_start(%{mmcu=*:%*})\ ++%:device_to_text_start(%{mmcu=*:%*})" + + #define LIB_SPEC \ + "%{!mmcu=at90s1*:%{!mmcu=attiny11:%{!mmcu=attiny12:%{!mmcu=attiny15:%{!mmcu=attiny28: -lc }}}}}" +@@ -571,6 +579,10 @@ struct GTY(()) machine_function /* 'true' - if current function is a signal function as specified by the "signal" attribute. */ int is_signal; @@ -4772,7 +4871,7 @@ index 6b2e755..9b0f782 100644 +Target Report Mask(FRACT_CONV_TRUNC) +Allow to use truncation instead of rounding towards 0 for fractional int types diff --git a/gcc/config/avr/driver-avr.c b/gcc/config/avr/driver-avr.c -index e859f5f..c767c81 100644 +index e859f5f..b1448e7 100644 --- a/gcc/config/avr/driver-avr.c +++ b/gcc/config/avr/driver-avr.c @@ -59,8 +59,8 @@ avr_device_to_as (int argc, const char **argv) @@ -4786,7 +4885,38 @@ index e859f5f..c767c81 100644 } /* Returns command line parameters to pass to ld. */ -@@ -144,7 +144,7 @@ avr_device_to_sp8 (int argc, const char **argv) +@@ -101,6 +101,30 @@ avr_device_to_data_start (int argc, const char **argv) + return concat ("-Tdata ", data_section_start_str, NULL); + } + ++/* Returns command line parameters that describe start of text section. */ ++ ++const char * ++avr_device_to_text_start (int argc, const char **argv) ++{ ++ unsigned long text_section_start; ++ char text_section_start_str[16]; ++ ++ if (0 == argc) ++ return NULL; ++ ++ avr_set_current_device (argv[0]); ++ ++ if (avr_current_device->text_section_start == 0) ++ return NULL; ++ ++ text_section_start = avr_current_device->text_section_start; ++ ++ snprintf (text_section_start_str, sizeof(text_section_start_str) - 1, ++ "0x%lX", text_section_start); ++ ++ return concat ("-Ttext ", text_section_start_str, NULL); ++} ++ + /* Returns command line parameters that describe the device startfile. */ + + const char * +@@ -144,7 +168,7 @@ avr_device_to_sp8 (int argc, const char **argv) || avr_current_device->arch == ARCH_AVR25)) return ""; @@ -4862,7 +4992,7 @@ index 14ed658..78085be 100644 n_mcu++ option[name] = "mmcu=" name diff --git a/gcc/config/avr/t-multilib b/gcc/config/avr/t-multilib -index 6b1db60..d7c61d6 100644 +index 6b1db60..3539264 100644 --- a/gcc/config/avr/t-multilib +++ b/gcc/config/avr/t-multilib @@ -21,9 +21,9 @@ @@ -4870,19 +5000,14 @@ index 6b1db60..d7c61d6 100644 # . -MULTILIB_OPTIONS = mmcu=avr2/mmcu=avr25/mmcu=avr3/mmcu=avr31/mmcu=avr35/mmcu=avr4/mmcu=avr5/mmcu=avr51/mmcu=avr6/mmcu=avrxmega2/mmcu=avrxmega4/mmcu=avrxmega5/mmcu=avrxmega6/mmcu=avrxmega7 msp8 -+MULTILIB_OPTIONS = mmcu=avr2/mmcu=avr25/mmcu=avr3/mmcu=avr31/mmcu=avr35/mmcu=avr4/mmcu=avr5/mmcu=avr51/mmcu=avr6/mmcu=avr7/mmcu=avrxmega2/mmcu=avrxmega4/mmcu=avrxmega5/mmcu=avrxmega6/mmcu=avrxmega7/mmcu=avrtiny msp8 ++MULTILIB_OPTIONS = mmcu=avr2/mmcu=avr25/mmcu=avr3/mmcu=avr31/mmcu=avr35/mmcu=avr4/mmcu=avr5/mmcu=avr51/mmcu=avr6/mmcu=avrxmega2/mmcu=avrxmega4/mmcu=avrxmega5/mmcu=avrxmega6/mmcu=avrxmega7/mmcu=avrtiny msp8 -MULTILIB_DIRNAMES = avr2 avr25 avr3 avr31 avr35 avr4 avr5 avr51 avr6 avrxmega2 avrxmega4 avrxmega5 avrxmega6 avrxmega7 tiny-stack avr25/tiny-stack -+MULTILIB_DIRNAMES = avr2 avr25 avr3 avr31 avr35 avr4 avr5 avr51 avr6 avr7 avrxmega2 avrxmega4 avrxmega5 avrxmega6 avrxmega7 avrtiny tiny-stack avr25/tiny-stack ++MULTILIB_DIRNAMES = avr2 avr25 avr3 avr31 avr35 avr4 avr5 avr51 avr6 avrxmega2 avrxmega4 avrxmega5 avrxmega6 avrxmega7 avrtiny tiny-stack avr25/tiny-stack MULTILIB_EXCEPTIONS = \ mmcu=avr3/msp8 \ -@@ -33,11 +33,13 @@ MULTILIB_EXCEPTIONS = \ - mmcu=avr5/msp8 \ - mmcu=avr51/msp8 \ - mmcu=avr6/msp8 \ -+ mmcu=avr7/msp8 \ - mmcu=avrxmega2/msp8 \ +@@ -37,7 +37,8 @@ MULTILIB_EXCEPTIONS = \ mmcu=avrxmega4/msp8 \ mmcu=avrxmega5/msp8 \ mmcu=avrxmega6/msp8 \ @@ -4892,7 +5017,7 @@ index 6b1db60..d7c61d6 100644 MULTILIB_MATCHES = \ mmcu?avr2=mmcu?at90s2313 \ -@@ -52,8 +54,8 @@ MULTILIB_MATCHES = \ +@@ -52,8 +53,8 @@ MULTILIB_MATCHES = \ mmcu?avr2=mmcu?at90s8515 \ mmcu?avr2=mmcu?at90c8534 \ mmcu?avr2=mmcu?at90s8535 \ @@ -4902,7 +5027,7 @@ index 6b1db60..d7c61d6 100644 mmcu?avr25=mmcu?attiny13 \ mmcu?avr25=mmcu?attiny13a \ mmcu?avr25=mmcu?attiny2313 \ -@@ -63,6 +65,7 @@ MULTILIB_MATCHES = \ +@@ -63,6 +64,7 @@ MULTILIB_MATCHES = \ mmcu?avr25=mmcu?attiny4313 \ mmcu?avr25=mmcu?attiny44 \ mmcu?avr25=mmcu?attiny44a \ @@ -4910,7 +5035,7 @@ index 6b1db60..d7c61d6 100644 mmcu?avr25=mmcu?attiny84 \ mmcu?avr25=mmcu?attiny84a \ mmcu?avr25=mmcu?attiny25 \ -@@ -78,12 +81,16 @@ MULTILIB_MATCHES = \ +@@ -78,12 +80,16 @@ MULTILIB_MATCHES = \ mmcu?avr25=mmcu?attiny87 \ mmcu?avr25=mmcu?attiny48 \ mmcu?avr25=mmcu?attiny88 \ @@ -4927,7 +5052,7 @@ index 6b1db60..d7c61d6 100644 mmcu?avr35=mmcu?at90usb82 \ mmcu?avr35=mmcu?at90usb162 \ mmcu?avr35=mmcu?atmega8u2 \ -@@ -93,6 +100,8 @@ MULTILIB_MATCHES = \ +@@ -93,16 +99,20 @@ MULTILIB_MATCHES = \ mmcu?avr35=mmcu?attiny1634 \ mmcu?avr4=mmcu?ata6285 \ mmcu?avr4=mmcu?ata6286 \ @@ -4936,20 +5061,39 @@ index 6b1db60..d7c61d6 100644 mmcu?avr4=mmcu?atmega8 \ mmcu?avr4=mmcu?atmega8a \ mmcu?avr4=mmcu?atmega48 \ -@@ -112,9 +121,12 @@ MULTILIB_MATCHES = \ + mmcu?avr4=mmcu?atmega48a \ + mmcu?avr4=mmcu?atmega48p \ + mmcu?avr4=mmcu?atmega48pa \ ++ mmcu?avr4=mmcu?atmega48pb \ + mmcu?avr4=mmcu?atmega88 \ + mmcu?avr4=mmcu?atmega88a \ + mmcu?avr4=mmcu?atmega88p \ + mmcu?avr4=mmcu?atmega88pa \ ++ mmcu?avr4=mmcu?atmega88pb \ + mmcu?avr4=mmcu?atmega8515 \ + mmcu?avr4=mmcu?atmega8535 \ + mmcu?avr4=mmcu?atmega8hva \ +@@ -112,9 +122,14 @@ MULTILIB_MATCHES = \ mmcu?avr4=mmcu?at90pwm3 \ mmcu?avr4=mmcu?at90pwm3b \ mmcu?avr4=mmcu?at90pwm81 \ + mmcu?avr5=mmcu?ata5702m322 \ ++ mmcu?avr5=mmcu?ata5782 \ mmcu?avr5=mmcu?ata5790 \ mmcu?avr5=mmcu?ata5790n \ mmcu?avr5=mmcu?ata5795 \ ++ mmcu?avr5=mmcu?ata5831 \ + mmcu?avr5=mmcu?ata6613c \ + mmcu?avr5=mmcu?ata6614q \ mmcu?avr5=mmcu?atmega16 \ mmcu?avr5=mmcu?atmega16a \ mmcu?avr5=mmcu?atmega161 \ -@@ -135,15 +147,12 @@ MULTILIB_MATCHES = \ +@@ -131,19 +146,17 @@ MULTILIB_MATCHES = \ + mmcu?avr5=mmcu?atmega168a \ + mmcu?avr5=mmcu?atmega168p \ + mmcu?avr5=mmcu?atmega168pa \ ++ mmcu?avr5=mmcu?atmega168pb \ + mmcu?avr5=mmcu?atmega169 \ mmcu?avr5=mmcu?atmega169a \ mmcu?avr5=mmcu?atmega169p \ mmcu?avr5=mmcu?atmega169pa \ @@ -4965,7 +5109,7 @@ index 6b1db60..d7c61d6 100644 mmcu?avr5=mmcu?atmega323 \ mmcu?avr5=mmcu?atmega324a \ mmcu?avr5=mmcu?atmega324p \ -@@ -151,6 +160,7 @@ MULTILIB_MATCHES = \ +@@ -151,6 +164,7 @@ MULTILIB_MATCHES = \ mmcu?avr5=mmcu?atmega325 \ mmcu?avr5=mmcu?atmega325a \ mmcu?avr5=mmcu?atmega325p \ @@ -4973,7 +5117,7 @@ index 6b1db60..d7c61d6 100644 mmcu?avr5=mmcu?atmega3250 \ mmcu?avr5=mmcu?atmega3250a \ mmcu?avr5=mmcu?atmega3250p \ -@@ -189,32 +199,21 @@ MULTILIB_MATCHES = \ +@@ -189,32 +203,21 @@ MULTILIB_MATCHES = \ mmcu?avr5=mmcu?atmega6490 \ mmcu?avr5=mmcu?atmega16hva \ mmcu?avr5=mmcu?atmega16hva2 \ @@ -5008,7 +5152,7 @@ index 6b1db60..d7c61d6 100644 mmcu?avr5=mmcu?at90scr100 \ mmcu?avr5=mmcu?at90usb646 \ mmcu?avr5=mmcu?at90usb647 \ -@@ -227,57 +226,65 @@ MULTILIB_MATCHES = \ +@@ -227,57 +230,63 @@ MULTILIB_MATCHES = \ mmcu?avr51=mmcu?atmega1284 \ mmcu?avr51=mmcu?atmega1284p \ mmcu?avr51=mmcu?atmega128rfa1 \ @@ -5021,8 +5165,6 @@ index 6b1db60..d7c61d6 100644 mmcu?avr6=mmcu?atmega2561 \ + mmcu?avr6=mmcu?atmega256rfr2 \ + mmcu?avr6=mmcu?atmega2564rfr2 \ -+ mmcu?avr7=mmcu?ata5782 \ -+ mmcu?avr7=mmcu?ata5831 \ + mmcu?avrxmega2=mmcu?atxmega8e5 \ mmcu?avrxmega2=mmcu?atxmega16a4 \ - mmcu?avrxmega2=mmcu?atxmega16d4 \ @@ -5132,7 +5274,7 @@ index f2021b9..334d955 100644 has_mem = true; num_mems++; diff --git a/gcc/doc/avr-mmcu.texi b/gcc/doc/avr-mmcu.texi -index b1313c4..45d3b9a 100644 +index b1313c4..d018ff5 100644 --- a/gcc/doc/avr-mmcu.texi +++ b/gcc/doc/avr-mmcu.texi @@ -18,7 +18,7 @@ @@ -5144,7 +5286,7 @@ index b1313c4..45d3b9a 100644 @item avr3 ``Classic'' devices with 16@tie{}KiB up to 64@tie{}KiB of program memory. -@@ -30,27 +30,31 @@ +@@ -30,27 +30,27 @@ @item avr35 ``Classic'' devices with 16@tie{}KiB up to 64@tie{}KiB of program memory and with the @code{MOVW} instruction. @@ -5154,12 +5296,12 @@ index b1313c4..45d3b9a 100644 @item avr4 ``Enhanced'' devices with up to 8@tie{}KiB of program memory. -@*@var{mcu}@tie{}= @code{ata6285}, @code{ata6286}, @code{atmega48}, @code{atmega48a}, @code{atmega48p}, @code{atmega48pa}, @code{atmega8}, @code{atmega8a}, @code{atmega8hva}, @code{atmega8515}, @code{atmega8535}, @code{atmega88}, @code{atmega88a}, @code{atmega88p}, @code{atmega88pa}, @code{at90pwm1}, @code{at90pwm2}, @code{at90pwm2b}, @code{at90pwm3}, @code{at90pwm3b}, @code{at90pwm81}. -+@*@var{mcu}@tie{}= @code{ata6285}, @code{ata6286}, @code{ata6289}, @code{ata6612c}, @code{atmega48}, @code{atmega48a}, @code{atmega48p}, @code{atmega48pa}, @code{atmega8}, @code{atmega8a}, @code{atmega8hva}, @code{atmega8515}, @code{atmega8535}, @code{atmega88}, @code{atmega88a}, @code{atmega88p}, @code{atmega88pa}, @code{at90pwm1}, @code{at90pwm2}, @code{at90pwm2b}, @code{at90pwm3}, @code{at90pwm3b}, @code{at90pwm81}. ++@*@var{mcu}@tie{}= @code{ata6285}, @code{ata6286}, @code{ata6289}, @code{ata6612c}, @code{atmega48}, @code{atmega48a}, @code{atmega48p}, @code{atmega48pa}, @code{atmega48pb}, @code{atmega8}, @code{atmega8a}, @code{atmega8hva}, @code{atmega8515}, @code{atmega8535}, @code{atmega88}, @code{atmega88a}, @code{atmega88p}, @code{atmega88pa}, @code{atmega88pb}, @code{at90pwm1}, @code{at90pwm2}, @code{at90pwm2b}, @code{at90pwm3}, @code{at90pwm3b}, @code{at90pwm81}. @item avr5 ``Enhanced'' devices with 16@tie{}KiB up to 64@tie{}KiB of program memory. -@*@var{mcu}@tie{}= @code{ata5790}, @code{ata5790n}, @code{ata5795}, @code{atmega16}, @code{atmega16a}, @code{atmega16hva}, @code{atmega16hva}, @code{atmega16hva2}, @code{atmega16hva2}, @code{atmega16hvb}, @code{atmega16hvb}, @code{atmega16hvbrevb}, @code{atmega16m1}, @code{atmega16m1}, @code{atmega16u4}, @code{atmega16u4}, @code{atmega161}, @code{atmega162}, @code{atmega163}, @code{atmega164a}, @code{atmega164p}, @code{atmega164pa}, @code{atmega165}, @code{atmega165a}, @code{atmega165p}, @code{atmega165pa}, @code{atmega168}, @code{atmega168a}, @code{atmega168p}, @code{atmega168pa}, @code{atmega169}, @code{atmega169a}, @code{atmega169p}, @code{atmega169pa}, @code{atmega26hvg}, @code{atmega32}, @code{atmega32a}, @code{atmega32a}, @code{atmega32c1}, @code{atmega32c1}, @code{atmega32hvb}, @code{atmega32hvb}, @code{atmega32hvbrevb}, @code{atmega32m1}, @code{atmega32m1}, @code{atmega32u4}, @code{atmega32u4}, @code{atmega32u6}, @code{atmega32u6}, @code{atmega323}, @code{atmega324a}, @code{atmega324p}, @code{atmega324pa}, @code{atmega325}, @code{atmega325a}, @code{atmega325p}, @code{atmega3250}, @code{atmega3250a}, @code{atmega3250p}, @code{atmega3250pa}, @code{atmega328}, @code{atmega328p}, @code{atmega329}, @code{atmega329a}, @code{atmega329p}, @code{atmega329pa}, @code{atmega3290}, @code{atmega3290a}, @code{atmega3290p}, @code{atmega3290pa}, @code{atmega406}, @code{atmega48hvf}, @code{atmega64}, @code{atmega64a}, @code{atmega64c1}, @code{atmega64c1}, @code{atmega64hve}, @code{atmega64m1}, @code{atmega64m1}, @code{atmega64rfa2}, @code{atmega64rfr2}, @code{atmega640}, @code{atmega644}, @code{atmega644a}, @code{atmega644p}, @code{atmega644pa}, @code{atmega645}, @code{atmega645a}, @code{atmega645p}, @code{atmega6450}, @code{atmega6450a}, @code{atmega6450p}, @code{atmega649}, @code{atmega649a}, @code{atmega649p}, @code{atmega6490}, @code{atmega6490a}, @code{atmega6490p}, @code{at90can32}, @code{at90can64}, @code{at90pwm161}, @code{at90pwm216}, @code{at90pwm316}, @code{at90scr100}, @code{at90usb646}, @code{at90usb647}, @code{at94k}, @code{m3000}. -+@*@var{mcu}@tie{}= @code{ata5702m322}, @code{ata5790}, @code{ata5790n}, @code{ata5795}, @code{ata6613c}, @code{ata6614q}, @code{atmega16}, @code{atmega16a}, @code{atmega16hva}, @code{atmega16hva2}, @code{atmega16hvb}, @code{atmega16hvbrevb}, @code{atmega16m1}, @code{atmega16u4}, @code{atmega161}, @code{atmega162}, @code{atmega163}, @code{atmega164a}, @code{atmega164p}, @code{atmega164pa}, @code{atmega165}, @code{atmega165a}, @code{atmega165p}, @code{atmega165pa}, @code{atmega168}, @code{atmega168a}, @code{atmega168p}, @code{atmega168pa}, @code{atmega169}, @code{atmega169a}, @code{atmega169p}, @code{atmega169pa}, @code{atmega32}, @code{atmega32a}, @code{atmega32c1}, @code{atmega32hvb}, @code{atmega32hvbrevb}, @code{atmega32m1}, @code{atmega32u4}, @code{atmega32u6}, @code{atmega323}, @code{atmega324a}, @code{atmega324p}, @code{atmega324pa}, @code{atmega325}, @code{atmega325a}, @code{atmega325p}, @code{atmega325pa}, @code{atmega3250}, @code{atmega3250a}, @code{atmega3250p}, @code{atmega3250pa}, @code{atmega328}, @code{atmega328p}, @code{atmega329}, @code{atmega329a}, @code{atmega329p}, @code{atmega329pa}, @code{atmega3290}, @code{atmega3290a}, @code{atmega3290p}, @code{atmega3290pa}, @code{atmega406}, @code{atmega64}, @code{atmega64a}, @code{atmega64c1}, @code{atmega64hve}, @code{atmega64hve2}, @code{atmega64m1}, @code{atmega64rfr2}, @code{atmega640}, @code{atmega644}, @code{atmega644a}, @code{atmega644p}, @code{atmega644pa}, @code{atmega644rfr2}, @code{atmega645}, @code{atmega645a}, @code{atmega645p}, @code{atmega6450}, @code{atmega6450a}, @code{atmega6450p}, @code{atmega649}, @code{atmega649a}, @code{atmega649p}, @code{atmega6490}, @code{atmega6490a}, @code{atmega6490p}, @code{at90can32}, @code{at90can64}, @code{at90pwm161}, @code{at90pwm216}, @code{at90pwm316}, @code{at90scr100}, @code{at90usb646}, @code{at90usb647}, @code{at94k}, @code{m3000}. ++@*@var{mcu}@tie{}= @code{ata5702m322}, @code{ata5782}, @code{ata5790}, @code{ata5790n}, @code{ata5795}, @code{ata5831}, @code{ata6613c}, @code{ata6614q}, @code{atmega16}, @code{atmega16a}, @code{atmega16hva}, @code{atmega16hva2}, @code{atmega16hvb}, @code{atmega16hvbrevb}, @code{atmega16m1}, @code{atmega16u4}, @code{atmega161}, @code{atmega162}, @code{atmega163}, @code{atmega164a}, @code{atmega164p}, @code{atmega164pa}, @code{atmega165}, @code{atmega165a}, @code{atmega165p}, @code{atmega165pa}, @code{atmega168}, @code{atmega168a}, @code{atmega168p}, @code{atmega168pa}, @code{atmega168pb}, @code{atmega169}, @code{atmega169a}, @code{atmega169p}, @code{atmega169pa}, @code{atmega32}, @code{atmega32a}, @code{atmega32c1}, @code{atmega32hvb}, @code{atmega32hvbrevb}, @code{atmega32m1}, @code{atmega32u4}, @code{atmega32u6}, @code{atmega323}, @code{atmega324a}, @code{atmega324p}, @code{atmega324pa}, @code{atmega325}, @code{atmega325a}, @code{atmega325p}, @code{atmega325pa}, @code{atmega3250}, @code{atmega3250a}, @code{atmega3250p}, @code{atmega3250pa}, @code{atmega328}, @code{atmega328p}, @code{atmega329}, @code{atmega329a}, @code{atmega329p}, @code{atmega329pa}, @code{atmega3290}, @code{atmega3290a}, @code{atmega3290p}, @code{atmega3290pa}, @code{atmega406}, @code{atmega64}, @code{atmega64a}, @code{atmega64c1}, @code{atmega64hve}, @code{atmega64hve2}, @code{atmega64m1}, @code{atmega64rfr2}, @code{atmega640}, @code{atmega644}, @code{atmega644a}, @code{atmega644p}, @code{atmega644pa}, @code{atmega644rfr2}, @code{atmega645}, @code{atmega645a}, @code{atmega645p}, @code{atmega6450}, @code{atmega6450a}, @code{atmega6450p}, @code{atmega649}, @code{atmega649a}, @code{atmega649p}, @code{atmega6490}, @code{atmega6490a}, @code{atmega6490p}, @code{at90can32}, @code{at90can64}, @code{at90pwm161}, @code{at90pwm216}, @code{at90pwm316}, @code{at90scr100}, @code{at90usb646}, @code{at90usb647}, @code{at94k}, @code{m3000}. @item avr51 ``Enhanced'' devices with 128@tie{}KiB of program memory. @@ -5170,10 +5312,6 @@ index b1313c4..45d3b9a 100644 ``Enhanced'' devices with 3-byte PC, i.e.@: with more than 128@tie{}KiB of program memory. -@*@var{mcu}@tie{}= @code{atmega2560}, @code{atmega2561}. +@*@var{mcu}@tie{}= @code{atmega256rfr2}, @code{atmega2560}, @code{atmega2561}, @code{atmega2564rfr2}. -+ -+@item avr7 -+``Enhanced'' devices with 20@tie{}KiB of program memory starts at 0x8000. -+@*@var{mcu}@tie{}= @code{ata5782}, @code{ata5831}. @item avrxmega2 ``XMEGA'' devices with more than 8@tie{}KiB and up to 64@tie{}KiB of program memory. @@ -5182,7 +5320,7 @@ index b1313c4..45d3b9a 100644 @item avrxmega4 ``XMEGA'' devices with more than 64@tie{}KiB and up to 128@tie{}KiB of program memory. -@@ -62,12 +66,16 @@ +@@ -62,12 +62,16 @@ @item avrxmega6 ``XMEGA'' devices with more than 128@tie{}KiB of program memory. @@ -5201,10 +5339,25 @@ index b1313c4..45d3b9a 100644 This ISA is implemented by the minimal AVR core and supported for assembler only. @*@var{mcu}@tie{}= @code{attiny11}, @code{attiny12}, @code{attiny15}, @code{attiny28}, @code{at90s1200}. diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi -index a3e2ee0..361de1d 100644 +index a3e2ee0..e37551a 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi -@@ -11936,6 +11936,9 @@ instructions because of a hardware erratum. Skip instructions are +@@ -11867,6 +11867,14 @@ the device name as from the AVR user manual. The difference between + If @var{device} is not a device but only a core architecture like + @code{avr51}, this macro will not be defined. + ++@item __AVR_DEVICE_NAME__ ++Setting @code{-mmcu=@var{device}} defines this built-in macro to ++the device's name. For example, with @code{-mmcu=atmega8} the macro ++will be defined to @code{atmega8}. ++ ++If @var{device} is not a device but only a core architecture like ++@code{avr51}, this macro will not be defined. ++ + @item __AVR_XMEGA__ + The device / architecture belongs to the XMEGA family of devices. + +@@ -11936,6 +11944,9 @@ instructions because of a hardware erratum. Skip instructions are The second macro is only defined if @code{__AVR_HAVE_JMP_CALL__} is also set. @@ -8309,6 +8462,55 @@ index 0000000..51be22b + +void __attribute__((nmi)) nmi_fun() /* { dg-warning "'nmi_fun' appears to be a misspelled nmi handler" } */ +{} +diff --git a/gcc/testsuite/gcc.target/avr/pr52472.c b/gcc/testsuite/gcc.target/avr/pr52472.c +new file mode 100644 +index 0000000..701cfb4 +--- /dev/null ++++ b/gcc/testsuite/gcc.target/avr/pr52472.c +@@ -0,0 +1,16 @@ ++/* { dg-do compile } */ ++/* { dg-options "-Os -g -Wno-pointer-to-int-cast" } */ ++ ++/* This testcase exposes PR52472. expand_debug_expr mistakenly ++ considers the address space of data to be generic, and ++ asserts that PSImode pointers aren't valid in the generic ++ address space. */ ++ ++extern const __memx unsigned data[][10]; ++ ++unsigned long ice (void) ++{ ++ unsigned long addr32; ++ ++ return addr32 = ((unsigned long) data); ++} +diff --git a/gcc/testsuite/gcc.target/avr/pr60991.c b/gcc/testsuite/gcc.target/avr/pr60991.c +new file mode 100644 +index 0000000..a09f42a +--- /dev/null ++++ b/gcc/testsuite/gcc.target/avr/pr60991.c +@@ -0,0 +1,21 @@ ++/* { dg-do run } */ ++/* { dg-options "-O1" } */ ++ ++/* This testcase (simplified from the original bug report) exposes ++ PR60991. The code generated for writing the __int24 value corrupts ++ the frame pointer if the offset is <= 63 + MAX_LD_OFFSET */ ++ ++#include ++ ++int main(void) ++{ ++ volatile char junk[62]; ++ junk[0] = 5; ++ volatile __int24 staticConfig = 0; ++ ++ if (junk[0] != 5) ++ abort(); ++ ++ exit(0); ++ return 0; ++} diff --git a/gcc/testsuite/gcc.target/avr/progmem-error-1.cpp b/gcc/testsuite/gcc.target/avr/progmem-error-1.cpp index cf53cc8..934b93c 100644 --- a/gcc/testsuite/gcc.target/avr/progmem-error-1.cpp diff --git a/gcc.build.bash b/gcc.build.bash index 4a1e651..2703238 100755 --- a/gcc.build.bash +++ b/gcc.build.bash @@ -17,28 +17,28 @@ then wget http://mirror.switch.ch/ftp/mirror/gnu/gmp/gmp-5.0.2.tar.bz2 fi -tar xfjv gmp-5.0.2.tar.bz2 +tar xfv gmp-5.0.2.tar.bz2 if [[ ! -f mpfr-3.0.0.tar.bz2 ]] ; then wget http://mirror.switch.ch/ftp/mirror/gnu/mpfr/mpfr-3.0.0.tar.bz2 fi -tar xfjv mpfr-3.0.0.tar.bz2 +tar xfv mpfr-3.0.0.tar.bz2 if [[ ! -f mpc-0.9.tar.gz ]] ; then wget http://www.multiprecision.org/mpc/download/mpc-0.9.tar.gz fi -tar xfzv mpc-0.9.tar.gz +tar xfv mpc-0.9.tar.gz if [[ ! -f gcc-4.8.1.tar.bz2 ]] ; then wget http://mirror.switch.ch/ftp/mirror/gnu/gcc/gcc-4.8.1/gcc-4.8.1.tar.bz2 fi -tar xfjv gcc-4.8.1.tar.bz2 +tar xfv gcc-4.8.1.tar.bz2 pushd gcc-4.8.1 for p in ../gcc-patches/*.patch; do echo Applying $p; patch -p1 < $p; done diff --git a/gdb-patches/00-gdb-7.7-atmel.patch b/gdb-patches/00-gdb-7.8-atmel.patch similarity index 98% rename from gdb-patches/00-gdb-7.7-atmel.patch rename to gdb-patches/00-gdb-7.8-atmel.patch index c0c1d86..a25fcf7 100644 --- a/gdb-patches/00-gdb-7.7-atmel.patch +++ b/gdb-patches/00-gdb-7.8-atmel.patch @@ -1319,7 +1319,7 @@ index 0000000..302a230 + diff --git a/binutils/BRANCHES b/binutils/BRANCHES new file mode 100644 -index 0000000..f9e141a +index 0000000..6b9c410 --- /dev/null +++ b/binutils/BRANCHES @@ -0,0 +1,48 @@ @@ -1365,7 +1365,7 @@ index 0000000..f9e141a +binutils-2_22-branch +binutils-2_23-branch + -+Copyright (C) 2012 Free Software Foundation, Inc. ++Copyright (C) 2012-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -1373,10 +1373,238 @@ index 0000000..f9e141a +binutils-2_24-branch diff --git a/binutils/ChangeLog b/binutils/ChangeLog new file mode 100644 -index 0000000..284bd24 +index 0000000..50cb6cc --- /dev/null +++ b/binutils/ChangeLog -@@ -0,0 +1,695 @@ +@@ -0,0 +1,256 @@ ++2014-06-09 Romain Chastenet ++ ++ PR binutils/16252 ++ * dwarf.c (display_debug_frames): Remember the state of the ++ cfa_offset, cfa_reg, ra and cfa_exp field ++ ++2014-06-05 Joel Brobecker ++ ++ * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on ++ bfd's development.sh. ++ * Makefile.in, configure: Regenerate. ++ ++2014-05-16 Jon Turney ++ ++ * objcopy.c (is_nondebug_keep_contents_section): New function. ++ (setup_section): Use it. ++ ++2014-05-16 Kaushik Phata ++ ++ * readelf.c (get_machine_flags): Handle RL78 64-bit doubles flag. ++ ++2014-05-02 Alan Modra ++ ++ * emul_aix.c: Update bfd target vector naming. ++ * testsuite/binutils-all/objcopy.exp: Likewise. ++ ++2014-04-24 Christian Svensson ++ ++ * MAINTAINERS: Add myself and Stefan as OR1K maintainers. ++ ++2014-04-23 Andrew Bennett ++ ++ * doc/binutils.texi: Document the disassemble MIPS XPA instructions ++ command line option. ++ ++2014-04-22 Christian Svensson ++ ++ * readelf.c: Remove openrisc and or32 support. Add support for or1k. ++ ++2014-04-18 Tristan Gingold ++ ++ * od-macho.c (dump_section_map): Adjust as load commands ++ are now chained. ++ (dump_load_command, dump_section_content): Likewise. ++ ++2014-04-16 Tristan Gingold ++ ++ * od-macho.c (OPT_DYLD_INFO): New macro. ++ (options): Add entry for dyld_info. ++ (mach_o_help): Likewise. ++ (load_and_dump, dump_dyld_info_rebase, dump_dyld_info_bind) ++ (dump_dyld_info_export_1, dump_dyld_info_export): New functions. ++ (bfd_mach_o_dyld_rebase_type_name): New array. ++ (export_info_data): New struct. ++ (dump_dyld_info): Add verbose argument. Dump rebase, bind and ++ exports data. ++ (dump_load_command): Adjust dump_dyld_info call. ++ (mach_o_dump): Handle dyld_info. ++ ++2014-04-16 Tristan Gingold ++ ++ * od-macho.c (dump_header): Display sizeofcmds in decimal too. ++ (dump_segment): Reformat output. ++ (dump_dyld_info): Also display end offsets. ++ (dump_load_command): Add IDX argument, display commands size ++ and offset, reformat display. ++ (dump_load_commands): Adjust for added argument. ++ ++2014-04-07 Alan Modra ++ ++ PR binutils/16811 ++ * objcopy.c (copy_object): Error if no sections. ++ ++2014-04-03 Markus Trippelsdorf ++ ++ PR binutils/14698 ++ ar.c: Set plugin_target early if plugins are supported. ++ nm.c: Likewise. ++ ++2014-04-03 Tristan Gingold ++ ++ * od-macho.c (printf_uint64): New function. ++ (dump_load_command, dump_obj_compact_unwind): Use it. ++ (dump_exe_compact_unwind): Display personality functions. ++ ++2014-04-02 Tristan Gingold ++ ++ * od-macho.c (OPT_TWOLEVEL_HINTS): New macro. ++ (options): Add entry for twolevel_hints. ++ (dump_data_in_code): Fix error message. ++ (dump_twolevel_hints): New function. ++ (dump_load_command): Handle prebound dylib, prebind cksum ++ and twolevel hints. ++ (mach_o_dump): Handle twolevel hints. ++ ++2014-04-01 Tristan Gingold ++ ++ * od-macho.c (OPT_DATA_IN_CODE): New macro. ++ (options): Add entry for data in code. ++ (mach_o_help): Ditto. ++ (data_in_code_kind_name): New array. ++ (dump_data_in_code): New function. ++ (dump_load_command): Handle data in code. ++ (mach_o_dump): Ditto. ++ (dump_header): Display a terminal newline. ++ ++2014-03-27 Tristan Gingold ++ ++ * od-macho.c (dump_load_command): Display value for ++ BFD_MACH_O_LC_DYLD_ENVIRONMENT. Handle BFD_MACH_O_LC_DATA_IN_CODE ++ and BFD_MACH_O_LC_DYLIB_CODE_SIGN_DRS. ++ ++2014-03-27 Tristan Gingold ++ ++ * od-macho.c (OPT_FUNCTION_STARTS): New macro. ++ (options): Add entry for function_starts. ++ (mach_o_help): Ditto. ++ (disp_segment_prot): New function. ++ (dump_section_map): Call disp_segment_prot. ++ (dump_function_starts): New function. ++ (dump_obj_compact_unwind): Fix ouput indentation. ++ (dump_exe_compact_unwind): Fix ouput indentation. ++ (mach_o_dump): Handle function_starts. ++ ++2014-03-26 Tristan Gingold ++ ++ * od-macho.c (bfd_mach_o_cpu_name): Add BFD_MACH_O_CPU_TYPE_ARM64. ++ ++2014-03-24 Tristan Gingold ++ ++ * objdump.c (load_specific_debug_section): Set address of section. ++ ++2014-03-24 Tristan Gingold ++ ++ * od-macho.c (dump_unwind_encoding_x86): Set the factor. ++ (dump_exe_compact_unwind): Change the condition. Improve ++ indentation. ++ ++2014-03-20 Nick Clifton ++ ++ * readelf.c (process_version_sections): Fix off-by-one error in ++ previous delta. ++ ++2014-03-19 Nick Clifton ++ ++ PR binutils/16723 ++ * readelf.c (process_version_sections): Prevent an infinite loop ++ when the vn_next field is zero but there are still entries to be ++ processed. ++ ++2014-03-17 Tristan Gingold ++ ++ * od-macho.c (dump_section_header): Renames of dump_section. ++ (dump_segment): Adjust after renaming. ++ (OPT_COMPACT_UNWIND): Define. ++ (options): Add compact unwind. ++ (mach_o_help): Document compact_unwind. ++ (unwind_x86_64_regs, unwind_x86_regs): New arrays. ++ (dump_unwind_encoding_x86, dump_unwind_encoding) ++ (dump_obj_compact_unwind, dump_exe_compact_unwind) ++ (dump_section_content): New functions. ++ (mach_o_dump): Handle compact unwind. ++ ++2014-03-17 Tristan Gingold ++ ++ * od-macho.c (dump_load_command): Handle lazy load dylib. ++ ++2014-03-14 Anthony Green ++ ++ * objcopy.c (copy_object): Check fwrite return code. ++ ++2014-03-14 Meador Inge ++ ++ * dwarf.c (strnlen): Move prototype ... ++ * sysdep.h (strnlen): ... to here. ++ ++2014-03-12 Nick Clifton ++ ++ PR binutils/16652 ++ * doc/binutils.texi (ar cmdline): Move --plugin command line ++ option to after the command option. ++ ++2014-03-12 Dmitry Gorbachev ++ ++ PR binutils/16567 ++ * deflex.l: Add noinput and nounput options. ++ ++2014-03-12 Alan Modra ++ ++ * Makefile.in: Regenerate. ++ * doc/Makefile.in: Regenerate. ++ ++2014-03-06 Nick Clifton ++ ++ PR binutils/16664 ++ * readelf.c (process_attributes): Add checks for corrupt ++ attribute section names. ++ ++2014-03-05 Alan Modra ++ ++ Update copyright years. ++ ++2014-03-03 Alan Modra ++ ++ * README: Add "Copyright Notices" paragraph. ++ ++2014-02-11 Cary Coutant ++ ++ * binutils/dwarf.c (read_and_display_attr_value): Don't warn ++ for zero-length attribute value. ++ ++2014-02-10 Alan Modra ++ ++ * po/binutils.pot: Regenerate. ++ ++2014-02-06 Andrew Pinski ++ ++ * readelf.c (get_machine_flags): Handle E_MIPS_MACH_OCTEON3 case. ++ ++2014-02-06 Cary Coutant ++ ++ PR binutils/16444 ++ * readelf.c (print_gnu_note): Add support for NT_GNU_GOLD_VERSION. ++ ++2014-01-08 H.J. Lu ++ ++ * version.c (print_version): Update copyright year to 2014. ++ +2014-01-07 Tom Tromey + + * bucomm.c (fatal, non_fatal): Replace obsolete VA_* macros with @@ -1391,676 +1619,9 @@ index 0000000..284bd24 + * coffgrok.h (coff_ofile): Don't use PARAMS. + * nlmheader.y (strerror): Don't use PARAMS. + -+2013-12-31 Nick Clifton -+ -+ * objcopy.c (dump_sections): New list. -+ (command_line_switch): Add OPTION_DUMP_SECTION. -+ (copy_options): Add dump-section. -+ (copy_usage): Document new option. -+ (copy_object): Dump requested sections. -+ (copy_main): Handle --dump-section. -+ * doc/binutils.texi: Document --dump-section option. -+ * NEWS: Mention new feature. -+ -+2013-12-20 Nick Clifton -+ -+ PR binutils/16218 -+ * dwarf.c (read_and_display_attr_value): Only print a tab -+ character if it preceeds further text. -+ -+2013-12-19 Tom Tromey -+ -+ * dwarf.c (fetch_indirect_string): Don't bias by section address. -+ (fetch_indexed_string): Likewise. -+ (process_debug_info): Likewise. -+ (display_debug_loc): Likewise. -+ (display_debug_ranges): Likewise. -+ -+2013-12-13 Kuan-Lin Chen -+ Wei-Cheng Wang -+ -+ * readelf.c: Include elf/nds32.h -+ (guess_is_rela): Add case for EM_NDS32. -+ (dump_relocations): Add case for EM_NDS32. -+ (decode_NDS32_machine_flags): New. -+ (get_machine_flags): Add case for EM_NDS32. -+ (is_32bit_abs_reloc): Likewise. -+ (is_16bit_abs_reloc): Likewise. -+ (process_nds32_specific): New. -+ (process_arch_specific): Add case for EM_NDS32. -+ * NEWS: Announce Andes nds32 support. -+ * MAINTAINERS: Add nds32 maintainers. -+ -+2013-12-10 Roland McGrath -+ -+ * Makefile.am (install-exec-local): Prefix libtool invocation with -+ $(INSTALL_PROGRAM_ENV). -+ * Makefile.in: Regenerate. -+ -+2013-11-22 Cory Fields -+ -+ * windres.c (define_resource): Use zero for timestamp, making -+ output deterministic. time.h include is no longer needed. -+ * resres.c (res_append_resource): Likewise. -+ -+2013-11-13 Martin Mitas -+ -+ * rescoff.c (write_coff_file): Use 64-bit alignment for resource -+ data. -+ (coff_res_to_bin): Likewise. -+ -+2013-11-07 Doug Evans -+ -+ Add pretty-printing of .debug_gnu_pubnames, .debug_gnu_pubtypes. -+ * dwarf.c (get_gdb_index_symbol_kind_name): New function. -+ (display_debug_pubnames_worker): Renamed from display_debug_pubnames. -+ Add support for .debug_gnu_pubnames, .debug_gnu_pubtypes. -+ (display_debug_pubnames, display_debug_pubnames_gnu): New functions. -+ (display_gdb_index): Redo printing of symbol kind. -+ (debug_displays): Add .debug_gnu_pubnames, .debug_gnu_pubtypes. -+ * dwarf.h (dwarf_section_display_enum): Add gnu_pubnames, gnu_pubtypes. -+ * readelf.c (process_section_headers): Add gnu_pubnames, gnu_pubtypes. -+ -+2013-11-07 Roland McGrath -+ -+ * objdump.c (dump_dwarf): Grok bfd_mach_x86_64_nacl and -+ bfd_mach_x64_32_nacl as equivalent to bfd_mach_x86_64. -+ -+2013-10-30 Alan Modra -+ -+ * readelf.c (get_ppc_dynamic_type): Replace PPC_TLSOPT with PPC_OPT. -+ (get_ppc64_dynamic_type): Replace PPC64_TLSOPT with PPC64_OPT. -+ -+2013-10-30 Ulrich Weigand -+ -+ * readelf.c (get_ppc64_symbol_other): New function. -+ (get_symbol_other): Use it for EM_PPC64. -+ -+2013-10-30 Alan Modra -+ -+ * readelf.c (get_machine_flags): Display ABI version for EM_PPC64. -+ -+2013-10-24 Nick Clifton -+ -+ * nm.c (display_rel_file): Treat bfd_error_no_symbols as -+ non-fatal. -+ -+2013-10-14 Chao-ying Fu -+ -+ * readelf.c (display_mips_gnu_attribute): Support Tag_GNU_MIPS_ABI_MSA. -+ * doc/binutils.texi: Document -Mmsa disassembler option. -+ -+2013-10-14 Jan-Benedict Glaw -+ -+ * readelf.c (decode_arm_unwind): Don't initialize `addr'. -+ -+2013-10-14 Nick Clifton -+ -+ * readelf.c (decode_arm_unwind): Initialise addr structure. -+ (process_symbol_table): Free lengths. -+ * srcconv.c (wr_sc): Free info. -+ -+2013-10-11 Roland McGrath -+ -+ * winduni.c (languages): Use \345 (octal syntax) rather than -+ literal non-ASCII/non-UTF8 character in string literal. -+ -+ * readelf.c (print_dynamic_symbol): Use array subscript syntax -+ rather than addition syntax with string literal. -+ -+2013-10-09 Nick Clifton -+ -+ PR binutils/16023 -+ * debug.c (debug_type_samep): Add missing break statement. -+ -+ PR binutils/16024 -+ * objdump.c (usage): Mark as a no-return function. -+ (main): Add comment explaining why a break statement is not -+ needed. -+ -+ * dwarf.c (add64): New function. -+ (read_and_display_attr_value): Add CU offset in to the value -+ displayed for a DW_AT_ref8 attribute. -+ -+2013-10-01 Cory Fields -+ -+ * arsup.c (ar_save): Respect the deterministic setting when -+ reading from an mri script. -+ * ar.c (main): Set the default deterministic mode when reading -+ from an mri script. -+ -+2013-10-01 Jan-Benedict Glaw -+ -+ * dwarf.c (SAFE_BYTE_GET): Fix argument check. -+ -+2013-09-27 H.J. Lu -+ -+ * dwarf.c (display_debug_frames): Pass offset_size to -+ print_dwarf_vma for cie_id. -+ -+2013-09-20 Alan Modra -+ -+ * configure: Regenerate. -+ -+2013-09-18 Tristan Gingold -+ -+ * NEWS: Add marker for 2.24. -+ -+2013-09-18 Tristan Gingold -+ -+ * Makefile.am (LEXLIB): Define. Replase references to @LEXLIB@ -+ by $(LEXLIB). -+ * Makefile.in: Regenerate. -+ -+2013-09-17 Doug Gilmore -+ -+ * readelf.c (get_machine_flags): Handle EF_MIPS_FP64. -+ -+2013-09-12 Nick Clifton -+ -+ * dwarf.c (dwarf_vmatoa): Rename to dwarf_vmatoa_1 and add a -+ precision parameter. -+ (dwarf_vmatoa): New wrapper for dwarf_vmatoa_1. -+ (print_dwarf_vma): Use dwarf_vmatoa_1. -+ (SAFE_BYTE_GET): Add check that VAL is big enough to contain -+ AMOUNT bytes. -+ (process_debug_info): Use an unsigned int for the offset size. -+ (process_debug_pubnames): Likewise. -+ (display_debug_aranges): Likewise. -+ (struct Frame_Chunk): Use dwarf_vma type for pc_begin and pc_range -+ fields. -+ (frame_display_row): Use print_dwarf_vma to display dwarf_vma -+ values. -+ (display_debug_frames): Likewise. -+ -+2013-09-10 Nick Clifton -+ -+ * dwarf.c (display_debug_frames): Check for DW64_CIE_ID when -+ parsing 64-bit frames. -+ -+2013-08-27 Nick Clifton -+ -+ PR binutils/15796 -+ * ar.c (map_over_members): Correctly handle multiple same-name -+ entries on the command line and in the archive. -+ -+2013-08-23 H.J. Lu -+ -+ * doc/binutils.texi: Remove the extra space. -+ -+2013-08-23 Mikael Pettersson -+ -+ PR binutils/15779 -+ * doc/binutils.texi (ranlib -D): Correct description. -+ PR binutils/15777 -+ (nm --special-syms): Fix typo. -+ -+2013-08-23 Nick Clifton -+ -+ PR binutils/15798 -+ * doc/binutils.texi (ar cmdline): Update description of 'q' -+ command. -+ -+ PR binutils/14136 -+ (nm): Add description of 'I' symbol type. -+ -+2013-08-23 Yuri Chornoivan -+ -+ PR binutils/15834 -+ * od-xcoff.c: Fix typos. -+ -+2013-08-19 Tristan Gingold -+ -+ * nm.c (print_size_symbols): Directly get symbol size. -+ -+2013-08-12 Andreas Schwab -+ -+ PR binutils/15818 -+ * objdump.c (disassemble_section): Return early if nothing from -+ this section needs to be disassembled. -+ -+2013-08-09 Nick Clifton -+ -+ * readelf.c (get_machine_flags): Handle RL78 G10 flag. -+ -+2013-07-26 Sergey Guriev -+ Alexander Ivchenko -+ Maxim Kuznetsov -+ Sergey Lega -+ Anna Tikhonova -+ Ilya Tocar -+ Andrey Turetskiy -+ Ilya Verbin -+ Kirill Yukhin -+ Michael Zolotukhin -+ -+ * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and -+ numeration in comments. -+ (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to -+ dwarf table. -+ -+2013-07-19 Nick Clifton -+ -+ PR binutils/15745 -+ * readelf.c (get_unwind_section_word): Whilst searching for a -+ reloc section associated with an unwind section, check the type as -+ well as the section number. -+ -+2013-07-18 Jim Thomas -+ -+ * ar.c (usage): Fix C conformance issue. -+ -+2013-07-18 Nick Clifton -+ -+ * doc/binutils.texi (nm, objdump): Remove bogus links to STABS -+ documentation. -+ -+ * readelf.c (process_unwind): Do not return the result of a void -+ function. -+ -+2013-07-15 Maciej W. Rozycki -+ -+ * readelf.c (display_mips_gnu_attribute): Replace hardcoded magic -+ numbers with enum values. -+ -+2013-07-12 Maciej W. Rozycki -+ -+ * readelf.c (get_machine_flags): Handle EF_MIPS_NAN2008. -+ -+2013-07-10 Tristan Gingold -+ -+ * od-xcoff.c (OPT_LDINFO): Define. -+ (options): Add ldinfo. -+ (xcoff_help): Mention ldinfo. -+ (xcoff_dump): Rename to ... -+ (xcoff_dump_obj): ... this. Add a break. -+ (dump_dumpx_core): New function. -+ (xcoff_dump_core): Likewise. -+ (xcoff_dump): Likewise. -+ * doc/binutils.texi (objdump): Mention ldinfo. -+ -+2013-07-09 Tristan Gingold -+ -+ * configure.com: Add new defines to match changes in configure. -+ -+2013-05-28 Cary Coutant -+ -+ * dwarf.c (display_debug_lines_raw): Print section offsets. -+ -+2013-05-15 Cary Coutant -+ -+ * dwarf.c (SAFE_BYTE_GET64): Correct end-of-buffer check; -+ don't increment PTR. -+ (decode_location_expression): DW_OP_const2u should read 2 bytes. -+ (display_debug_lines_decoded): Adjust formatting. -+ * elfcomm.c (byte_get_little_endian): Add cases for 5-, 6-, and -+ 7-byte reads. -+ (byte_get_big_endian): Likewise. -+ (byte_get_signed): Likewise. -+ -+2013-05-09 Andrew Pinski -+ -+ * doc/binutils.texi: Document -Mvirt disassembler option. -+ -+2013-05-02 Nick Clifton -+ -+ * readelf.c: Add support for MSP430X architecture. -+ -+2013-05-02 Nick Clifton -+ -+ * dwarf.c (display_debug_lines_raw): Do not treat .debug_line.dwo -+ sections as if they were fragmentary .debug_line sections. -+ (display_debug_lines_decoded): Likewise. -+ -+2013-04-29 Nick Clifton -+ -+ * dwarf.c (read_debug_line_header): New function. Reads in a -+ header in a .debug_line section. -+ (display_debug_lines_raw): Use new function. Handle fragmentary -+ .debug_line sections. -+ (display_debug_lines_decoded): Likewise. -+ * readelf.c (process_section_headers): Handle fragmenatry -+ .debug_line sections. -+ (display_debug_section): Likewise. -+ -+2013-04-26 Ian Lance Taylor -+ -+ * MAINTAINERS: Add myself and Cary as gold maintainers. -+ -+2013-04-08 Tom Tromey -+ -+ * dwarf.c (process_debug_info): Check dwarf_cutoff_level. -+ -+2013-04-08 Tom Tromey -+ -+ * dwarf-mode.el: Bump version number. -+ (dwarf-mode): Remove autoload. -+ (dwarf-die-reference): Relax regexp. -+ -+2013-04-05 Alan Modra -+ -+ PR binutils/15324 -+ * configure.in: Add strnlen to AC_CHECK_DECLS, sort. -+ * dwarf.c (strnlen): Provide fallback decl. -+ * config.in: Regnerate. -+ * configure: Regenerate. -+ -+2013-03-29 H.J. Lu -+ -+ * dwarf.c (process_debug_info): Increment hdrptr by 8 after -+ SAFE_BYTE_GET64. -+ -+2013-03-27 Phil Krylov -+ -+ PR binutils/13409 -+ * winduni.c (codepages[]): Use UTF-16LE. -+ (wind_MultiByteToWideChar): Likewise. -+ (wind_WideCharToMultiByte): Likewise. -+ -+2013-03-27 Alan Modra -+ -+ PR binutils/15206 -+ * dwarf.c (read_and_display_attr_value): Cast format '*' arg to int. -+ -+2013-03-26 Nick Clifton -+ -+ PR binutils/15206 -+ * dwarf.c (SAFE_BYTE_GET): New macro - checks remaining buffer -+ space before calling byte_get. -+ (SAFE_BYTE_GET_AND_INC): New macro. -+ (SAFE_SIGNED_BYTE_GET): New macro. -+ (SAFE_SIGNED_BYTE_GET_AND_INC): New macro. -+ (SAFE_BYTE_GET64): New macro. -+ (process_extened_line_op): Use new macros. Use strnlen when -+ appropriate. -+ (fetch_indirect_string): Likewise. -+ (get_FORM_name): Likewise. -+ (decode_location_expression): Likewise. -+ (read_and_display_attr_value): Likewise. -+ (process_debug_info): Likewise. -+ (display_debug_lines_raw): Likewise. -+ (display_debug_lines_decoded): Likewise. -+ (display_debug_pubnames): Likewise. -+ (display_debug_macinfo): Likewise. -+ (get_line_filename_and_dirname): Likewise. -+ (display_debug_macro): Likewise. -+ (display_loc_list): Likewise. -+ (display_loc_list_dwo): Likewise. -+ (display_debug_aranges): Likewise. -+ (display_debug_ranges): Likewise. -+ (frame_display_row): Likewise. -+ (display_debug_frames): Likewise. -+ -+2013-03-25 Nick Clifton -+ -+ PR binutils/15202 -+ * dwarf.c (read_leb128): Add END parameter. Do not read at or -+ beyond end. -+ (read_sleb128): Add END parameter. -+ (read_uleb128): New function. -+ (process_extended_line_op): Pass END to leb128 functions. -+ (process_abbrev_section): Likewise. -+ (decode_location_expression): Likewise. -+ (read_and_display_attr_value): Likewise. -+ (read_and_display_attr): Likewise. -+ (process_debug_info): Likewise. -+ (display_debug_lines_raw): Likewise. -+ (display_debug_lines_decoded): Likewise. -+ (display_debug_macinfo): Likewise. -+ (get_line_filename_and_dirname): Likewise. -+ (display_debug_macro): Likewise. -+ (display_loc_list_dwo): Likewise. -+ (display_debug_ranges): Likewise. -+ * dwarf.h (read_leb128): Update prototype. -+ * readelf.c (read_uleb128): Add END parameter. -+ (decode_arm_unwind_bytecode): Pass END to read_uleb128. -+ (decode_tic6x_unwind_bytecode): Likewise. -+ (display_tag_value): New function. -+ (display_arm_attribute): Add END parameter. Pass END to -+ read_uleb128. Use display_tag_value. -+ (display_gnu_attribute): Likewise. -+ (display_power_gnu_attribute): Likewise. -+ (display_sparc_gnu_attribute): Likewise. -+ (display_mips_gnu_attribute): Likewise. -+ (display_tic6x_attribute): Likewise. -+ (process_attributes): Likewise. -+ (display_raw_attribute): New function. -+ -+2013-03-22 Nick Clifton -+ -+ PR binutils/15201 -+ * dwarf.c (display_debug_ranges): Add checks for reading beyond -+ the end of the section. -+ -+ PR binutils/15157 -+ * readelf.c (apply_relocations): Catch relocations with negative -+ offsets. -+ -+2013-03-15 Nick Clifton -+ -+ * addr2line.c (slurp_symtab): If canonicalization reveals that -+ there were no ordinary symbols, try loading the dynamic symbols -+ instead. -+ -+2013-03-14 Markos Chandras -+ -+ * MAINTAINERS: Add myself as Meta maintainer. -+ -+2013-03-08 Andreas Arnez -+ -+ * readelf.c (get_note_type): Add NT_S390_TDB. -+ -+2013-03-07 Alan Modra -+ -+ * strings.c (get_char): Dispense with buf[]. Instead shift -+ chars into big-endian value and byte-swap later if -+ little-endian. Don't EOF check value read from object. -+ -+2013-03-05 Corinna Vinschen -+ -+ * configure.in: Build DLL tools on x86_64-*-cygwin* as well. -+ * configure: Regenerate. -+ -+2013-03-04 Nick Clifton -+ -+ * elfcomm.c (error): Flush stdout before emitting the error -+ message. -+ (warn): Likewise. -+ -+2013-03-01 Cary Coutant -+ -+ * dwarf.c (cu_tu_indexes_read, shndx_pool, shndx_pool_size) -+ (shndx_pool_used): Move to top of file. -+ (struct cu_tu_set): New type. -+ (cu_count, tu_count, cu_sets, tu_sets): New file scope variables. -+ (fetch_indexed_string): Add "this_set" parameter. Update all callers. -+ (find_cu_tu_set_v2): New function. -+ (read_and_display_attr_value): Add "this_set" parameter. -+ (read_and_display_attr): Likewise. -+ (process_debug_info): Track base offsets for DWARF package files. -+ (load_debug_info): Call load_cu_tu_indexes. -+ (get_DW_SECT_short_name): New function. -+ (process_cu_tu_index): Add support for version 2 DWARF package files. -+ -+2013-02-27 Alan Modra -+ -+ PR binutils/15191 -+ * readelf.c (offsetof): Define. -+ (CHECK_ENTSIZE_VALUES): Remove extraneous indefinite article. -+ (process_corefile_note_segment): Allow notes without name or -+ desc. Combine out-of-range checks. Disallow "negative" -+ notesz or descsz. -+ -+2013-02-26 Nick Clifton -+ -+ PR binutils/15191 -+ * readelf.c (process_corefile_note_segment): Prevent attempts to -+ read beyond the end of the note buffer. -+ -+2013-02-15 Kai Tietz -+ -+ * objcopy.c (copy_main): Initialize context variable. -+ -+2013-02-15 Nick Clifton -+ -+ PR binutils/15140 -+ * ar.c (open_inarch): Fail on attempts to convert a normal archive -+ to a thin archive or vice versa. -+ * elfcomm.c (make_qualified_name): Handle corrupted thin -+ archives. -+ * readelf.c (process_archive): Likewise. -+ * doc/binutils.texi: Clarify documentation describing thin -+ archives. -+ -+2013-02-15 Nick Clifton -+ -+ PR binutils/15033 -+ * objcopy.c (enum change_action): Delete. -+ (struct section_list): Delete remove, copy, change_vma, change_lma -+ and set_flags fields. Add context field. -+ (find_section_list): Add a context parameter. Add support for -+ wildcard characters in section names. -+ (is_strip_section): Check for sections being both copied and -+ removed. -+ (copy_object): Pass context to find_section_list. -+ (setup_section): Likewise. -+ (copy_section): Likewise. -+ (copy_main): Likewise. -+ * doc/binutils: Document the new behaviour. -+ * NEWS: Mention the new feature -+ -+2013-02-14 Nick Clifton -+ -+ PR binutils/15125 -+ * objcopy.c (copy_object): Provide a helpful warning message when -+ adding a gnu_debuglink section to an object which already contains -+ one. -+ -+2013-02-07 Nick Clifton -+ -+ * elfcomm.c (get_archive_member_name): Prevent seg-fault if a -+ corrupt archive uses long names but has no long name table. -+ -+2013-02-06 Sandra Loosemore -+ Andrew Jenner -+ -+ Based on patches from Altera Corporation. -+ -+ * readelf.c: Include elf/nios2.h. -+ (dump_relocations): Add case for EM_ALTERA_NIOS2. -+ (get_nios2_dynamic_type): New. -+ (get_dynamic_type): Add case for EM_ALTERA_NIOS2. -+ (is_32bit_abs_reloc): Fix EM_ALTERA_NIOS2 case. -+ (is_16bit_abs_reloc): Likewise. -+ (is_none_reloc): Add EM_ALTERA_NIOS2 and EM_NIOS32 cases. -+ * NEWS: Note Altera Nios II support. -+ * MAINTAINERS: Add Nios II maintainers. -+ -+2013-01-29 Xi Wang -+ -+ * readelf.c (process_version_sections): Fix overflow checks to -+ avoid undefined behaviour. -+ -+2013-01-28 Doug Evans -+ -+ * dwarf.c (display_gdb_index): Handle .gdb_index version 8. -+ -+2013-01-28 Robert Schiele -+ -+ * objcopy.c (parse_flags): Add merge and strings section flags. -+ -+2013-01-25 Cary Coutant -+ -+ * dwarf.c (display_loc_list): Update offset for each line -+ printed. -+ (print_addr_index): New function. -+ (display_loc_list_dwo): Update offset for each line printed. -+ Fix problems displaying loclists in .dwo files. Add support -+ for type 4 entries. -+ (display_debug_loc): Remove custom header for .dwo files. -+ (display_debug_addr): Adjust formatting. -+ -+2013-01-25 Marco Atzeri -+ -+ * objcopy.c : Enable long section names for OPTION_ADD_GNU_DEBUGLINK. -+ -+2013-01-24 Doug Evans -+ -+ * dwarf.c (display_debug_addr): Add missing parentheses to expression. -+ -+2013-01-24 Nick Clifton -+ -+ * readelf.c (get_machine_flags): Decode E_V850E3V5_ARCH. -+ -+2013-01-23 Andreas Krebbel -+ -+ * readelf.c: Add strings for NT_S390_LAST_BREAK and -+ NT_S390_SYSTEM_CALL. -+ -+2013-01-18 Nick Clifton -+ -+ PR binutils/15026 -+ * addr2line.c (translate_addresses): When pretty printing, print -+ unknown function names on the same line as unknown symbol names. -+ -+2013-01-17 Nickolai Zeldovich -+ -+ * objdump.c (dump_target_specific): Fix NULL pointer test. -+ -+2013-01-16 Alan Modra -+ -+ PR binutils/15018 -+ * stabs.c (parse_stab_members): Always set physname here to avoid -+ gcc warning.. -+ (parse_stab_argtypes): ..and don't duplicate the init here. -+ -+2013-01-10 Will Newton -+ -+ * binutils/readelf.c: (guess_is_rela): Add EM_METAG. -+ (dump_relocations): Add EM_METAG. -+ (get_machine_name): Correct case for Meta. -+ (is_32bit_abs_reloc): Add support for Meta ADDR32 reloc. -+ (is_none_reloc): Add support for Meta NONE reloc. -+ -+2013-01-08 Yufeng Zhang -+ -+ * readelf.c (get_note_type): Handle NT_ARM_TLS, NT_ARM_HW_BREAK -+ and NT_ARM_HW_WATCH. -+ -+2013-01-07 Roland McGrath -+ -+ * objcopy.c (deterministic): Make int rather than bfd_boolean, -+ initialize to -1. -+ (strip_options, copy_options): Add -U/--disable-deterministic-archives. -+ (default_deterministic): New function. -+ (strip_main, copy_main): Handle -U. Call default_deterministic. -+ (copy_usage, strip_usage): Describe -U. Cite whether -D or -U is -+ the default based on DEFAULT_AR_DETERMINISTIC. -+ * doc/binutils.texi (objcopy, strip): Describe -U and effect of -+ configure options on -D. -+ -+ * ar.c (default_deterministic): Comment fix. -+ -+2013-01-07 Patrice Dumas -+ -+ * doc/binutils.texi: Fix ordering of top level nodes. -+ Replace erroneous uses of @itemx with @item. -+ -+2013-01-04 Andreas Schwab -+ -+ * doc/binutils.texi (elfedit): Fix use of @itemx in @table. -+ -+2013-01-03 Marcus Shawcroft -+ -+ * MAINTAINERS: Add myself as AArch64 co-maintainer. -+ -+2013-01-02 H.J. Lu -+ -+ * version.c (print_version): Update copyright year to 2013. -+ -+For older changes see ChangeLog-2012 ++For older changes see ChangeLog-2013 + -+Copyright (C) 2013 Free Software Foundation, Inc. ++Copyright (C) 2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -15338,6 +14899,693 @@ index 0000000..da7d9e4 +fill-column: 74 +version-control: never +End: +diff --git a/binutils/ChangeLog-2013 b/binutils/ChangeLog-2013 +new file mode 100644 +index 0000000..541de44 +--- /dev/null ++++ b/binutils/ChangeLog-2013 +@@ -0,0 +1,681 @@ ++2013-12-31 Nick Clifton ++ ++ * objcopy.c (dump_sections): New list. ++ (command_line_switch): Add OPTION_DUMP_SECTION. ++ (copy_options): Add dump-section. ++ (copy_usage): Document new option. ++ (copy_object): Dump requested sections. ++ (copy_main): Handle --dump-section. ++ * doc/binutils.texi: Document --dump-section option. ++ * NEWS: Mention new feature. ++ ++2013-12-20 Nick Clifton ++ ++ PR binutils/16218 ++ * dwarf.c (read_and_display_attr_value): Only print a tab ++ character if it preceeds further text. ++ ++2013-12-19 Tom Tromey ++ ++ * dwarf.c (fetch_indirect_string): Don't bias by section address. ++ (fetch_indexed_string): Likewise. ++ (process_debug_info): Likewise. ++ (display_debug_loc): Likewise. ++ (display_debug_ranges): Likewise. ++ ++2013-12-13 Kuan-Lin Chen ++ Wei-Cheng Wang ++ ++ * readelf.c: Include elf/nds32.h ++ (guess_is_rela): Add case for EM_NDS32. ++ (dump_relocations): Add case for EM_NDS32. ++ (decode_NDS32_machine_flags): New. ++ (get_machine_flags): Add case for EM_NDS32. ++ (is_32bit_abs_reloc): Likewise. ++ (is_16bit_abs_reloc): Likewise. ++ (process_nds32_specific): New. ++ (process_arch_specific): Add case for EM_NDS32. ++ * NEWS: Announce Andes nds32 support. ++ * MAINTAINERS: Add nds32 maintainers. ++ ++2013-12-10 Roland McGrath ++ ++ * Makefile.am (install-exec-local): Prefix libtool invocation with ++ $(INSTALL_PROGRAM_ENV). ++ * Makefile.in: Regenerate. ++ ++2013-11-22 Cory Fields ++ ++ * windres.c (define_resource): Use zero for timestamp, making ++ output deterministic. time.h include is no longer needed. ++ * resres.c (res_append_resource): Likewise. ++ ++2013-11-13 Martin Mitas ++ ++ * rescoff.c (write_coff_file): Use 64-bit alignment for resource ++ data. ++ (coff_res_to_bin): Likewise. ++ ++2013-11-07 Doug Evans ++ ++ Add pretty-printing of .debug_gnu_pubnames, .debug_gnu_pubtypes. ++ * dwarf.c (get_gdb_index_symbol_kind_name): New function. ++ (display_debug_pubnames_worker): Renamed from display_debug_pubnames. ++ Add support for .debug_gnu_pubnames, .debug_gnu_pubtypes. ++ (display_debug_pubnames, display_debug_pubnames_gnu): New functions. ++ (display_gdb_index): Redo printing of symbol kind. ++ (debug_displays): Add .debug_gnu_pubnames, .debug_gnu_pubtypes. ++ * dwarf.h (dwarf_section_display_enum): Add gnu_pubnames, gnu_pubtypes. ++ * readelf.c (process_section_headers): Add gnu_pubnames, gnu_pubtypes. ++ ++2013-11-07 Roland McGrath ++ ++ * objdump.c (dump_dwarf): Grok bfd_mach_x86_64_nacl and ++ bfd_mach_x64_32_nacl as equivalent to bfd_mach_x86_64. ++ ++2013-10-30 Alan Modra ++ ++ * readelf.c (get_ppc_dynamic_type): Replace PPC_TLSOPT with PPC_OPT. ++ (get_ppc64_dynamic_type): Replace PPC64_TLSOPT with PPC64_OPT. ++ ++2013-10-30 Ulrich Weigand ++ ++ * readelf.c (get_ppc64_symbol_other): New function. ++ (get_symbol_other): Use it for EM_PPC64. ++ ++2013-10-30 Alan Modra ++ ++ * readelf.c (get_machine_flags): Display ABI version for EM_PPC64. ++ ++2013-10-24 Nick Clifton ++ ++ * nm.c (display_rel_file): Treat bfd_error_no_symbols as ++ non-fatal. ++ ++2013-10-14 Chao-ying Fu ++ ++ * readelf.c (display_mips_gnu_attribute): Support Tag_GNU_MIPS_ABI_MSA. ++ * doc/binutils.texi: Document -Mmsa disassembler option. ++ ++2013-10-14 Jan-Benedict Glaw ++ ++ * readelf.c (decode_arm_unwind): Don't initialize `addr'. ++ ++2013-10-14 Nick Clifton ++ ++ * readelf.c (decode_arm_unwind): Initialise addr structure. ++ (process_symbol_table): Free lengths. ++ * srcconv.c (wr_sc): Free info. ++ ++2013-10-11 Roland McGrath ++ ++ * winduni.c (languages): Use \345 (octal syntax) rather than ++ literal non-ASCII/non-UTF8 character in string literal. ++ ++ * readelf.c (print_dynamic_symbol): Use array subscript syntax ++ rather than addition syntax with string literal. ++ ++2013-10-09 Nick Clifton ++ ++ PR binutils/16023 ++ * debug.c (debug_type_samep): Add missing break statement. ++ ++ PR binutils/16024 ++ * objdump.c (usage): Mark as a no-return function. ++ (main): Add comment explaining why a break statement is not ++ needed. ++ ++ * dwarf.c (add64): New function. ++ (read_and_display_attr_value): Add CU offset in to the value ++ displayed for a DW_AT_ref8 attribute. ++ ++2013-10-01 Cory Fields ++ ++ * arsup.c (ar_save): Respect the deterministic setting when ++ reading from an mri script. ++ * ar.c (main): Set the default deterministic mode when reading ++ from an mri script. ++ ++2013-10-01 Jan-Benedict Glaw ++ ++ * dwarf.c (SAFE_BYTE_GET): Fix argument check. ++ ++2013-09-27 H.J. Lu ++ ++ * dwarf.c (display_debug_frames): Pass offset_size to ++ print_dwarf_vma for cie_id. ++ ++2013-09-20 Alan Modra ++ ++ * configure: Regenerate. ++ ++2013-09-18 Tristan Gingold ++ ++ * NEWS: Add marker for 2.24. ++ ++2013-09-18 Tristan Gingold ++ ++ * Makefile.am (LEXLIB): Define. Replase references to @LEXLIB@ ++ by $(LEXLIB). ++ * Makefile.in: Regenerate. ++ ++2013-09-17 Doug Gilmore ++ ++ * readelf.c (get_machine_flags): Handle EF_MIPS_FP64. ++ ++2013-09-12 Nick Clifton ++ ++ * dwarf.c (dwarf_vmatoa): Rename to dwarf_vmatoa_1 and add a ++ precision parameter. ++ (dwarf_vmatoa): New wrapper for dwarf_vmatoa_1. ++ (print_dwarf_vma): Use dwarf_vmatoa_1. ++ (SAFE_BYTE_GET): Add check that VAL is big enough to contain ++ AMOUNT bytes. ++ (process_debug_info): Use an unsigned int for the offset size. ++ (process_debug_pubnames): Likewise. ++ (display_debug_aranges): Likewise. ++ (struct Frame_Chunk): Use dwarf_vma type for pc_begin and pc_range ++ fields. ++ (frame_display_row): Use print_dwarf_vma to display dwarf_vma ++ values. ++ (display_debug_frames): Likewise. ++ ++2013-09-10 Nick Clifton ++ ++ * dwarf.c (display_debug_frames): Check for DW64_CIE_ID when ++ parsing 64-bit frames. ++ ++2013-08-27 Nick Clifton ++ ++ PR binutils/15796 ++ * ar.c (map_over_members): Correctly handle multiple same-name ++ entries on the command line and in the archive. ++ ++2013-08-23 H.J. Lu ++ ++ * doc/binutils.texi: Remove the extra space. ++ ++2013-08-23 Mikael Pettersson ++ ++ PR binutils/15779 ++ * doc/binutils.texi (ranlib -D): Correct description. ++ PR binutils/15777 ++ (nm --special-syms): Fix typo. ++ ++2013-08-23 Nick Clifton ++ ++ PR binutils/15798 ++ * doc/binutils.texi (ar cmdline): Update description of 'q' ++ command. ++ ++ PR binutils/14136 ++ (nm): Add description of 'I' symbol type. ++ ++2013-08-23 Yuri Chornoivan ++ ++ PR binutils/15834 ++ * od-xcoff.c: Fix typos. ++ ++2013-08-19 Tristan Gingold ++ ++ * nm.c (print_size_symbols): Directly get symbol size. ++ ++2013-08-12 Andreas Schwab ++ ++ PR binutils/15818 ++ * objdump.c (disassemble_section): Return early if nothing from ++ this section needs to be disassembled. ++ ++2013-08-09 Nick Clifton ++ ++ * readelf.c (get_machine_flags): Handle RL78 G10 flag. ++ ++2013-07-26 Sergey Guriev ++ Alexander Ivchenko ++ Maxim Kuznetsov ++ Sergey Lega ++ Anna Tikhonova ++ Ilya Tocar ++ Andrey Turetskiy ++ Ilya Verbin ++ Kirill Yukhin ++ Michael Zolotukhin ++ ++ * dwarf.c (dwarf_regnames_i386): Add k0-k7 registers and ++ numeration in comments. ++ (dwarf_regnames_x86_64): Add xmm16-31 and k0-k7 registers to ++ dwarf table. ++ ++2013-07-19 Nick Clifton ++ ++ PR binutils/15745 ++ * readelf.c (get_unwind_section_word): Whilst searching for a ++ reloc section associated with an unwind section, check the type as ++ well as the section number. ++ ++2013-07-18 Jim Thomas ++ ++ * ar.c (usage): Fix C conformance issue. ++ ++2013-07-18 Nick Clifton ++ ++ * doc/binutils.texi (nm, objdump): Remove bogus links to STABS ++ documentation. ++ ++ * readelf.c (process_unwind): Do not return the result of a void ++ function. ++ ++2013-07-15 Maciej W. Rozycki ++ ++ * readelf.c (display_mips_gnu_attribute): Replace hardcoded magic ++ numbers with enum values. ++ ++2013-07-12 Maciej W. Rozycki ++ ++ * readelf.c (get_machine_flags): Handle EF_MIPS_NAN2008. ++ ++2013-07-10 Tristan Gingold ++ ++ * od-xcoff.c (OPT_LDINFO): Define. ++ (options): Add ldinfo. ++ (xcoff_help): Mention ldinfo. ++ (xcoff_dump): Rename to ... ++ (xcoff_dump_obj): ... this. Add a break. ++ (dump_dumpx_core): New function. ++ (xcoff_dump_core): Likewise. ++ (xcoff_dump): Likewise. ++ * doc/binutils.texi (objdump): Mention ldinfo. ++ ++2013-07-09 Tristan Gingold ++ ++ * configure.com: Add new defines to match changes in configure. ++ ++2013-05-28 Cary Coutant ++ ++ * dwarf.c (display_debug_lines_raw): Print section offsets. ++ ++2013-05-15 Cary Coutant ++ ++ * dwarf.c (SAFE_BYTE_GET64): Correct end-of-buffer check; ++ don't increment PTR. ++ (decode_location_expression): DW_OP_const2u should read 2 bytes. ++ (display_debug_lines_decoded): Adjust formatting. ++ * elfcomm.c (byte_get_little_endian): Add cases for 5-, 6-, and ++ 7-byte reads. ++ (byte_get_big_endian): Likewise. ++ (byte_get_signed): Likewise. ++ ++2013-05-09 Andrew Pinski ++ ++ * doc/binutils.texi: Document -Mvirt disassembler option. ++ ++2013-05-02 Nick Clifton ++ ++ * readelf.c: Add support for MSP430X architecture. ++ ++2013-05-02 Nick Clifton ++ ++ * dwarf.c (display_debug_lines_raw): Do not treat .debug_line.dwo ++ sections as if they were fragmentary .debug_line sections. ++ (display_debug_lines_decoded): Likewise. ++ ++2013-04-29 Nick Clifton ++ ++ * dwarf.c (read_debug_line_header): New function. Reads in a ++ header in a .debug_line section. ++ (display_debug_lines_raw): Use new function. Handle fragmentary ++ .debug_line sections. ++ (display_debug_lines_decoded): Likewise. ++ * readelf.c (process_section_headers): Handle fragmenatry ++ .debug_line sections. ++ (display_debug_section): Likewise. ++ ++2013-04-26 Ian Lance Taylor ++ ++ * MAINTAINERS: Add myself and Cary as gold maintainers. ++ ++2013-04-08 Tom Tromey ++ ++ * dwarf.c (process_debug_info): Check dwarf_cutoff_level. ++ ++2013-04-08 Tom Tromey ++ ++ * dwarf-mode.el: Bump version number. ++ (dwarf-mode): Remove autoload. ++ (dwarf-die-reference): Relax regexp. ++ ++2013-04-05 Alan Modra ++ ++ PR binutils/15324 ++ * configure.in: Add strnlen to AC_CHECK_DECLS, sort. ++ * dwarf.c (strnlen): Provide fallback decl. ++ * config.in: Regnerate. ++ * configure: Regenerate. ++ ++2013-03-29 H.J. Lu ++ ++ * dwarf.c (process_debug_info): Increment hdrptr by 8 after ++ SAFE_BYTE_GET64. ++ ++2013-03-27 Phil Krylov ++ ++ PR binutils/13409 ++ * winduni.c (codepages[]): Use UTF-16LE. ++ (wind_MultiByteToWideChar): Likewise. ++ (wind_WideCharToMultiByte): Likewise. ++ ++2013-03-27 Alan Modra ++ ++ PR binutils/15206 ++ * dwarf.c (read_and_display_attr_value): Cast format '*' arg to int. ++ ++2013-03-26 Nick Clifton ++ ++ PR binutils/15206 ++ * dwarf.c (SAFE_BYTE_GET): New macro - checks remaining buffer ++ space before calling byte_get. ++ (SAFE_BYTE_GET_AND_INC): New macro. ++ (SAFE_SIGNED_BYTE_GET): New macro. ++ (SAFE_SIGNED_BYTE_GET_AND_INC): New macro. ++ (SAFE_BYTE_GET64): New macro. ++ (process_extened_line_op): Use new macros. Use strnlen when ++ appropriate. ++ (fetch_indirect_string): Likewise. ++ (get_FORM_name): Likewise. ++ (decode_location_expression): Likewise. ++ (read_and_display_attr_value): Likewise. ++ (process_debug_info): Likewise. ++ (display_debug_lines_raw): Likewise. ++ (display_debug_lines_decoded): Likewise. ++ (display_debug_pubnames): Likewise. ++ (display_debug_macinfo): Likewise. ++ (get_line_filename_and_dirname): Likewise. ++ (display_debug_macro): Likewise. ++ (display_loc_list): Likewise. ++ (display_loc_list_dwo): Likewise. ++ (display_debug_aranges): Likewise. ++ (display_debug_ranges): Likewise. ++ (frame_display_row): Likewise. ++ (display_debug_frames): Likewise. ++ ++2013-03-25 Nick Clifton ++ ++ PR binutils/15202 ++ * dwarf.c (read_leb128): Add END parameter. Do not read at or ++ beyond end. ++ (read_sleb128): Add END parameter. ++ (read_uleb128): New function. ++ (process_extended_line_op): Pass END to leb128 functions. ++ (process_abbrev_section): Likewise. ++ (decode_location_expression): Likewise. ++ (read_and_display_attr_value): Likewise. ++ (read_and_display_attr): Likewise. ++ (process_debug_info): Likewise. ++ (display_debug_lines_raw): Likewise. ++ (display_debug_lines_decoded): Likewise. ++ (display_debug_macinfo): Likewise. ++ (get_line_filename_and_dirname): Likewise. ++ (display_debug_macro): Likewise. ++ (display_loc_list_dwo): Likewise. ++ (display_debug_ranges): Likewise. ++ * dwarf.h (read_leb128): Update prototype. ++ * readelf.c (read_uleb128): Add END parameter. ++ (decode_arm_unwind_bytecode): Pass END to read_uleb128. ++ (decode_tic6x_unwind_bytecode): Likewise. ++ (display_tag_value): New function. ++ (display_arm_attribute): Add END parameter. Pass END to ++ read_uleb128. Use display_tag_value. ++ (display_gnu_attribute): Likewise. ++ (display_power_gnu_attribute): Likewise. ++ (display_sparc_gnu_attribute): Likewise. ++ (display_mips_gnu_attribute): Likewise. ++ (display_tic6x_attribute): Likewise. ++ (process_attributes): Likewise. ++ (display_raw_attribute): New function. ++ ++2013-03-22 Nick Clifton ++ ++ PR binutils/15201 ++ * dwarf.c (display_debug_ranges): Add checks for reading beyond ++ the end of the section. ++ ++ PR binutils/15157 ++ * readelf.c (apply_relocations): Catch relocations with negative ++ offsets. ++ ++2013-03-15 Nick Clifton ++ ++ * addr2line.c (slurp_symtab): If canonicalization reveals that ++ there were no ordinary symbols, try loading the dynamic symbols ++ instead. ++ ++2013-03-14 Markos Chandras ++ ++ * MAINTAINERS: Add myself as Meta maintainer. ++ ++2013-03-08 Andreas Arnez ++ ++ * readelf.c (get_note_type): Add NT_S390_TDB. ++ ++2013-03-07 Alan Modra ++ ++ * strings.c (get_char): Dispense with buf[]. Instead shift ++ chars into big-endian value and byte-swap later if ++ little-endian. Don't EOF check value read from object. ++ ++2013-03-05 Corinna Vinschen ++ ++ * configure.in: Build DLL tools on x86_64-*-cygwin* as well. ++ * configure: Regenerate. ++ ++2013-03-04 Nick Clifton ++ ++ * elfcomm.c (error): Flush stdout before emitting the error ++ message. ++ (warn): Likewise. ++ ++2013-03-01 Cary Coutant ++ ++ * dwarf.c (cu_tu_indexes_read, shndx_pool, shndx_pool_size) ++ (shndx_pool_used): Move to top of file. ++ (struct cu_tu_set): New type. ++ (cu_count, tu_count, cu_sets, tu_sets): New file scope variables. ++ (fetch_indexed_string): Add "this_set" parameter. Update all callers. ++ (find_cu_tu_set_v2): New function. ++ (read_and_display_attr_value): Add "this_set" parameter. ++ (read_and_display_attr): Likewise. ++ (process_debug_info): Track base offsets for DWARF package files. ++ (load_debug_info): Call load_cu_tu_indexes. ++ (get_DW_SECT_short_name): New function. ++ (process_cu_tu_index): Add support for version 2 DWARF package files. ++ ++2013-02-27 Alan Modra ++ ++ PR binutils/15191 ++ * readelf.c (offsetof): Define. ++ (CHECK_ENTSIZE_VALUES): Remove extraneous indefinite article. ++ (process_corefile_note_segment): Allow notes without name or ++ desc. Combine out-of-range checks. Disallow "negative" ++ notesz or descsz. ++ ++2013-02-26 Nick Clifton ++ ++ PR binutils/15191 ++ * readelf.c (process_corefile_note_segment): Prevent attempts to ++ read beyond the end of the note buffer. ++ ++2013-02-15 Kai Tietz ++ ++ * objcopy.c (copy_main): Initialize context variable. ++ ++2013-02-15 Nick Clifton ++ ++ PR binutils/15140 ++ * ar.c (open_inarch): Fail on attempts to convert a normal archive ++ to a thin archive or vice versa. ++ * elfcomm.c (make_qualified_name): Handle corrupted thin ++ archives. ++ * readelf.c (process_archive): Likewise. ++ * doc/binutils.texi: Clarify documentation describing thin ++ archives. ++ ++2013-02-15 Nick Clifton ++ ++ PR binutils/15033 ++ * objcopy.c (enum change_action): Delete. ++ (struct section_list): Delete remove, copy, change_vma, change_lma ++ and set_flags fields. Add context field. ++ (find_section_list): Add a context parameter. Add support for ++ wildcard characters in section names. ++ (is_strip_section): Check for sections being both copied and ++ removed. ++ (copy_object): Pass context to find_section_list. ++ (setup_section): Likewise. ++ (copy_section): Likewise. ++ (copy_main): Likewise. ++ * doc/binutils: Document the new behaviour. ++ * NEWS: Mention the new feature ++ ++2013-02-14 Nick Clifton ++ ++ PR binutils/15125 ++ * objcopy.c (copy_object): Provide a helpful warning message when ++ adding a gnu_debuglink section to an object which already contains ++ one. ++ ++2013-02-07 Nick Clifton ++ ++ * elfcomm.c (get_archive_member_name): Prevent seg-fault if a ++ corrupt archive uses long names but has no long name table. ++ ++2013-02-06 Sandra Loosemore ++ Andrew Jenner ++ ++ Based on patches from Altera Corporation. ++ ++ * readelf.c: Include elf/nios2.h. ++ (dump_relocations): Add case for EM_ALTERA_NIOS2. ++ (get_nios2_dynamic_type): New. ++ (get_dynamic_type): Add case for EM_ALTERA_NIOS2. ++ (is_32bit_abs_reloc): Fix EM_ALTERA_NIOS2 case. ++ (is_16bit_abs_reloc): Likewise. ++ (is_none_reloc): Add EM_ALTERA_NIOS2 and EM_NIOS32 cases. ++ * NEWS: Note Altera Nios II support. ++ * MAINTAINERS: Add Nios II maintainers. ++ ++2013-01-29 Xi Wang ++ ++ * readelf.c (process_version_sections): Fix overflow checks to ++ avoid undefined behaviour. ++ ++2013-01-28 Doug Evans ++ ++ * dwarf.c (display_gdb_index): Handle .gdb_index version 8. ++ ++2013-01-28 Robert Schiele ++ ++ * objcopy.c (parse_flags): Add merge and strings section flags. ++ ++2013-01-25 Cary Coutant ++ ++ * dwarf.c (display_loc_list): Update offset for each line ++ printed. ++ (print_addr_index): New function. ++ (display_loc_list_dwo): Update offset for each line printed. ++ Fix problems displaying loclists in .dwo files. Add support ++ for type 4 entries. ++ (display_debug_loc): Remove custom header for .dwo files. ++ (display_debug_addr): Adjust formatting. ++ ++2013-01-25 Marco Atzeri ++ ++ * objcopy.c : Enable long section names for OPTION_ADD_GNU_DEBUGLINK. ++ ++2013-01-24 Doug Evans ++ ++ * dwarf.c (display_debug_addr): Add missing parentheses to expression. ++ ++2013-01-24 Nick Clifton ++ ++ * readelf.c (get_machine_flags): Decode E_V850E3V5_ARCH. ++ ++2013-01-23 Andreas Krebbel ++ ++ * readelf.c: Add strings for NT_S390_LAST_BREAK and ++ NT_S390_SYSTEM_CALL. ++ ++2013-01-18 Nick Clifton ++ ++ PR binutils/15026 ++ * addr2line.c (translate_addresses): When pretty printing, print ++ unknown function names on the same line as unknown symbol names. ++ ++2013-01-17 Nickolai Zeldovich ++ ++ * objdump.c (dump_target_specific): Fix NULL pointer test. ++ ++2013-01-16 Alan Modra ++ ++ PR binutils/15018 ++ * stabs.c (parse_stab_members): Always set physname here to avoid ++ gcc warning.. ++ (parse_stab_argtypes): ..and don't duplicate the init here. ++ ++2013-01-10 Will Newton ++ ++ * binutils/readelf.c: (guess_is_rela): Add EM_METAG. ++ (dump_relocations): Add EM_METAG. ++ (get_machine_name): Correct case for Meta. ++ (is_32bit_abs_reloc): Add support for Meta ADDR32 reloc. ++ (is_none_reloc): Add support for Meta NONE reloc. ++ ++2013-01-08 Yufeng Zhang ++ ++ * readelf.c (get_note_type): Handle NT_ARM_TLS, NT_ARM_HW_BREAK ++ and NT_ARM_HW_WATCH. ++ ++2013-01-07 Roland McGrath ++ ++ * objcopy.c (deterministic): Make int rather than bfd_boolean, ++ initialize to -1. ++ (strip_options, copy_options): Add -U/--disable-deterministic-archives. ++ (default_deterministic): New function. ++ (strip_main, copy_main): Handle -U. Call default_deterministic. ++ (copy_usage, strip_usage): Describe -U. Cite whether -D or -U is ++ the default based on DEFAULT_AR_DETERMINISTIC. ++ * doc/binutils.texi (objcopy, strip): Describe -U and effect of ++ configure options on -D. ++ ++ * ar.c (default_deterministic): Comment fix. ++ ++2013-01-07 Patrice Dumas ++ ++ * doc/binutils.texi: Fix ordering of top level nodes. ++ Replace erroneous uses of @itemx with @item. ++ ++2013-01-04 Andreas Schwab ++ ++ * doc/binutils.texi (elfedit): Fix use of @itemx in @table. ++ ++2013-01-03 Marcus Shawcroft ++ ++ * MAINTAINERS: Add myself as AArch64 co-maintainer. ++ ++2013-01-02 H.J. Lu ++ ++ * version.c (print_version): Update copyright year to 2013. ++ ++For older changes see ChangeLog-2012 ++ ++Copyright (C) 2013 Free Software Foundation, Inc. ++ ++Copying and distribution of this file, with or without modification, ++are permitted in any medium without royalty provided the copyright ++notice and this notice are preserved. ++ ++Local Variables: ++mode: change-log ++left-margin: 8 ++fill-column: 74 ++version-control: never ++End: diff --git a/binutils/ChangeLog-9197 b/binutils/ChangeLog-9197 new file mode 100644 index 0000000..883aa5c @@ -22489,10 +22737,10 @@ index 0000000..75f231e +End: diff --git a/binutils/MAINTAINERS b/binutils/MAINTAINERS new file mode 100644 -index 0000000..cb6aa03 +index 0000000..6966b72 --- /dev/null +++ b/binutils/MAINTAINERS -@@ -0,0 +1,286 @@ +@@ -0,0 +1,288 @@ + ========= Binutils Maintainers ========= + +This is the list of individuals responsible for maintenance and update @@ -22609,6 +22857,8 @@ index 0000000..cb6aa03 + NetBSD support Matt Thomas + Nios II Sandra Loosemore + Nios II Andrew Jenner ++ OR1K Christian Svensson ++ OR1K Stefan Kristiansson + PPC Geoff Keating + PPC Alan Modra + PPC vector ext Aldy Hernandez @@ -22774,20 +23024,20 @@ index 0000000..cb6aa03 +Please do not commit any patches to a branch you did not create +without the explicit permission of the person who created the branch. + -+Copyright (C) 2012 Free Software Foundation, Inc. ++Copyright (C) 2012-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright +notice and this notice are preserved. diff --git a/binutils/Makefile.am b/binutils/Makefile.am new file mode 100644 -index 0000000..e35db01 +index 0000000..aca2610 --- /dev/null +++ b/binutils/Makefile.am -@@ -0,0 +1,547 @@ +@@ -0,0 +1,548 @@ +## Process this file with automake to generate Makefile.in +# -+# Copyright 2012, 2013 Free Software Foundation ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -23301,7 +23551,8 @@ index 0000000..e35db01 + +# We extract version from bfd/configure.in, make sure to rerun configure +# when BFD's version changes. -+CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in ++CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in \ ++ $(BFDDIR)/development.sh + +DISTCLEANFILES = sysroff.c sysroff.h site.exp site.bak embedspu + @@ -23334,10 +23585,10 @@ index 0000000..e35db01 + done diff --git a/binutils/Makefile.in b/binutils/Makefile.in new file mode 100644 -index 0000000..3408769 +index 0000000..c9e9e38 --- /dev/null +++ b/binutils/Makefile.in -@@ -0,0 +1,1481 @@ +@@ -0,0 +1,1483 @@ +# Makefile.in generated by automake 1.11.1 from Makefile.am. +# @configure_input@ + @@ -23356,7 +23607,7 @@ index 0000000..3408769 +@SET_MAKE@ + +# -+# Copyright 2012, 2013 Free Software Foundation ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -23956,7 +24207,9 @@ index 0000000..3408769 + +# We extract version from bfd/configure.in, make sure to rerun configure +# when BFD's version changes. -+CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in ++CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in \ ++ $(BFDDIR)/development.sh ++ +DISTCLEANFILES = sysroff.c sysroff.h site.exp site.bak embedspu +MOSTLYCLEANFILES = sysinfo$(EXEEXT_FOR_BUILD) bin2c$(EXEEXT_FOR_BUILD) \ + binutils.log binutils.sum abcdefgh* @@ -24821,7 +25074,7 @@ index 0000000..3408769 +.NOEXPORT: diff --git a/binutils/NEWS b/binutils/NEWS new file mode 100644 -index 0000000..b19f87b +index 0000000..8ca7a9c --- /dev/null +++ b/binutils/NEWS @@ -0,0 +1,496 @@ @@ -25312,7 +25565,7 @@ index 0000000..b19f87b + and/or local symbols only. They now also support long options. + + -+Copyright (C) 2012 Free Software Foundation, Inc. ++Copyright (C) 2012-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -25323,10 +25576,10 @@ index 0000000..b19f87b +End: diff --git a/binutils/README b/binutils/README new file mode 100644 -index 0000000..d11e945 +index 0000000..f16e68a --- /dev/null +++ b/binutils/README -@@ -0,0 +1,290 @@ +@@ -0,0 +1,299 @@ + README for BINUTILS + +These are the GNU binutils. These are utilities of use when dealing @@ -25342,6 +25595,15 @@ index 0000000..d11e945 +which give more information about those specific programs. + + ++Copyright Notices ++================= ++ ++Copyright years on binutils source files may be listed using range ++notation, e.g., 1991-2012, indicating that every year in the range, ++inclusive, is a copyrightable year that could otherwise be listed ++individually. ++ ++ +Unpacking and Installation -- quick overview +============================================ + @@ -25612,7 +25874,7 @@ index 0000000..d11e945 +If you have any problems or questions about the binutils on VMS, feel +free to mail me at kkaempf@rmi.de. + -+Copyright (C) 2012 Free Software Foundation, Inc. ++Copyright (C) 2012-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -26638,13 +26900,12 @@ index 0000000..fd838a6 +m4_include([../lt~obsolete.m4]) diff --git a/binutils/addr2line.c b/binutils/addr2line.c new file mode 100644 -index 0000000..0de7398 +index 0000000..f88e745 --- /dev/null +++ b/binutils/addr2line.c -@@ -0,0 +1,502 @@ +@@ -0,0 +1,501 @@ +/* addr2line.c -- convert addresses to line number and function name -+ Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, -+ 2007, 2009 Free Software Foundation, Inc. ++ Copyright (C) 1997-2014 Free Software Foundation, Inc. + Contributed by Ulrich Lauther + + This file is part of GNU Binutils. @@ -27146,12 +27407,12 @@ index 0000000..0de7398 +} diff --git a/binutils/ar.c b/binutils/ar.c new file mode 100644 -index 0000000..a11ed15 +index 0000000..ebd9528 --- /dev/null +++ b/binutils/ar.c -@@ -0,0 +1,1479 @@ +@@ -0,0 +1,1481 @@ +/* ar.c - Archive modify and extract. -+ Copyright 1991-2013 Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -27290,7 +27551,11 @@ index 0000000..a11ed15 + +static int show_help = 0; + ++#if BFD_SUPPORTS_PLUGINS ++static const char *plugin_target = "plugin"; ++#else +static const char *plugin_target = NULL; ++#endif + +static const char *target = NULL; + @@ -27723,7 +27988,6 @@ index 0000000..a11ed15 + break; + case OPTION_PLUGIN: +#if BFD_SUPPORTS_PLUGINS -+ plugin_target = "plugin"; + bfd_plugin_set_plugin (optarg); +#else + fprintf (stderr, _("sorry - this program has been built without plugin support\n")); @@ -27784,7 +28048,6 @@ index 0000000..a11ed15 + /* PR binutils/13493: Support plugins. */ + case OPTION_PLUGIN: +#if BFD_SUPPORTS_PLUGINS -+ plugin_target = "plugin"; + bfd_plugin_set_plugin (optarg); +#else + fprintf (stderr, _("sorry - this program has been built without plugin support\n")); @@ -28631,17 +28894,16 @@ index 0000000..a11ed15 +} diff --git a/binutils/arlex.l b/binutils/arlex.l new file mode 100644 -index 0000000..4080580 +index 0000000..2cda0a2 --- /dev/null +++ b/binutils/arlex.l -@@ -0,0 +1,95 @@ +@@ -0,0 +1,94 @@ +%option noinput nounput + +%{ +/* arlex.l - Strange script language lexer */ + -+/* Copyright 1992, 1997, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2011 -+ Free Software Foundation, Inc. ++/* Copyright (C) 1992-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -28732,15 +28994,14 @@ index 0000000..4080580 +#endif diff --git a/binutils/arparse.y b/binutils/arparse.y new file mode 100644 -index 0000000..113c548 +index 0000000..0e52efe --- /dev/null +++ b/binutils/arparse.y -@@ -0,0 +1,204 @@ +@@ -0,0 +1,203 @@ +%{ +/* arparse.y - Stange script language parser */ + -+/* Copyright 1992, 1993, 1995, 1997, 1999, 2002, 2003, 2005, 2007 -+ Free Software Foundation, Inc. ++/* Copyright (C) 1992-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -28942,12 +29203,12 @@ index 0000000..113c548 +} diff --git a/binutils/arsup.c b/binutils/arsup.c new file mode 100644 -index 0000000..9c6953e +index 0000000..da51e16 --- /dev/null +++ b/binutils/arsup.c @@ -0,0 +1,484 @@ +/* arsup.c - Archive support for MRI compatibility -+ Copyright 1992-2013 2008 Free Software Foundation, Inc. ++ Copyright (C) 1992-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -29432,13 +29693,12 @@ index 0000000..9c6953e +} diff --git a/binutils/arsup.h b/binutils/arsup.h new file mode 100644 -index 0000000..5b17681 +index 0000000..7cfbc95 --- /dev/null +++ b/binutils/arsup.h -@@ -0,0 +1,63 @@ +@@ -0,0 +1,62 @@ +/* arsup.h - archive support header file -+ Copyright 1992, 1993, 1994, 1996, 2001, 2002, 2003, 2005, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1992-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -29501,12 +29761,12 @@ index 0000000..5b17681 +extern int interactive; diff --git a/binutils/bfdtest1.c b/binutils/bfdtest1.c new file mode 100644 -index 0000000..eaee2fd +index 0000000..fc9b0ff --- /dev/null +++ b/binutils/bfdtest1.c @@ -0,0 +1,70 @@ +/* A program to test BFD. -+ Copyright 2012 Free Software Foundation, Inc. ++ Copyright (C) 2012-2014 Free Software Foundation, Inc. + + This file is part of the GNU Binutils. + @@ -29577,124 +29837,124 @@ index 0000000..eaee2fd +} diff --git a/binutils/bfdtest2.c b/binutils/bfdtest2.c new file mode 100644 -index 0000000..bdea620 +index 0000000..a791080 --- /dev/null +++ b/binutils/bfdtest2.c @@ -0,0 +1,106 @@ -+/* A program to test BFD. -+ Copyright 2012 Free Software Foundation, Inc. -+ -+ This file is part of the GNU Binutils. -+ -+ This program is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3 of the License, or -+ (at your option) any later version. -+ -+ This program is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with this program; if not, write to the Free Software -+ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -+ MA 02110-1301, USA. */ -+ -+#include "sysdep.h" -+#include "bfd.h" -+ -+static void -+die (const char *s) -+{ -+ printf ("oops: %s\n", s); -+ exit (1); -+} -+ -+static void * -+iovec_open (struct bfd *nbfd ATTRIBUTE_UNUSED, void *open_closure) -+{ -+ return open_closure; -+} -+ -+static file_ptr iovec_read (struct bfd *nbfd ATTRIBUTE_UNUSED, -+ void *stream, void *buf, file_ptr nbytes, -+ file_ptr offset) -+{ -+ FILE* file = (FILE*) stream; -+ -+ if (fseek(file, offset, SEEK_SET) != 0) -+ die ("fseek error"); -+ -+ return fread (buf, 1, nbytes, file); -+} -+ -+static int -+iovec_stat (struct bfd *abfd ATTRIBUTE_UNUSED, -+ void *stream, struct stat *sb) -+{ -+ return fstat (fileno ((FILE*) stream), sb); -+} -+ -+static bfd_boolean -+check_format_any (struct bfd *abfd, bfd_format format) -+{ -+ char** targets = NULL; -+ -+ if (bfd_check_format_matches (abfd, format, &targets)) -+ return TRUE; -+ -+ if (targets) -+ { -+ bfd_find_target (targets[0], abfd); -+ -+ return bfd_check_format (abfd, format); -+ } -+ -+ return FALSE; -+} -+ -+int -+main (int argc, const char** argv) -+{ -+ FILE* file; -+ bfd *abfd, *mbfd; -+ -+ if (argc < 2) -+ die ("Usage: test archivefile"); -+ -+ file = fopen(argv[1], "rb"); -+ if (!file) -+ die ("file not found"); -+ -+ abfd = bfd_openr_iovec (argv[1], 0, iovec_open, file, -+ iovec_read, NULL, iovec_stat); -+ if (!abfd) -+ die ("error opening file"); -+ -+ if (!check_format_any (abfd, bfd_archive)) -+ die ("not an archive"); -+ -+ mbfd = bfd_openr_next_archived_file (abfd, 0); -+ if (!mbfd) -+ die ("error opening archive member"); -+ -+ if (!bfd_close (mbfd)) -+ die ("error closing archive member"); -+ -+ if (!bfd_close (abfd)) -+ die ("error closing archive"); -+ -+ return 0; -+} ++/* A program to test BFD. ++ Copyright (C) 2012-2014 Free Software Foundation, Inc. ++ ++ This file is part of the GNU Binutils. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, write to the Free Software ++ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ++ MA 02110-1301, USA. */ ++ ++#include "sysdep.h" ++#include "bfd.h" ++ ++static void ++die (const char *s) ++{ ++ printf ("oops: %s\n", s); ++ exit (1); ++} ++ ++static void * ++iovec_open (struct bfd *nbfd ATTRIBUTE_UNUSED, void *open_closure) ++{ ++ return open_closure; ++} ++ ++static file_ptr iovec_read (struct bfd *nbfd ATTRIBUTE_UNUSED, ++ void *stream, void *buf, file_ptr nbytes, ++ file_ptr offset) ++{ ++ FILE* file = (FILE*) stream; ++ ++ if (fseek(file, offset, SEEK_SET) != 0) ++ die ("fseek error"); ++ ++ return fread (buf, 1, nbytes, file); ++} ++ ++static int ++iovec_stat (struct bfd *abfd ATTRIBUTE_UNUSED, ++ void *stream, struct stat *sb) ++{ ++ return fstat (fileno ((FILE*) stream), sb); ++} ++ ++static bfd_boolean ++check_format_any (struct bfd *abfd, bfd_format format) ++{ ++ char** targets = NULL; ++ ++ if (bfd_check_format_matches (abfd, format, &targets)) ++ return TRUE; ++ ++ if (targets) ++ { ++ bfd_find_target (targets[0], abfd); ++ ++ return bfd_check_format (abfd, format); ++ } ++ ++ return FALSE; ++} ++ ++int ++main (int argc, const char** argv) ++{ ++ FILE* file; ++ bfd *abfd, *mbfd; ++ ++ if (argc < 2) ++ die ("Usage: test archivefile"); ++ ++ file = fopen(argv[1], "rb"); ++ if (!file) ++ die ("file not found"); ++ ++ abfd = bfd_openr_iovec (argv[1], 0, iovec_open, file, ++ iovec_read, NULL, iovec_stat); ++ if (!abfd) ++ die ("error opening file"); ++ ++ if (!check_format_any (abfd, bfd_archive)) ++ die ("not an archive"); ++ ++ mbfd = bfd_openr_next_archived_file (abfd, 0); ++ if (!mbfd) ++ die ("error opening archive member"); ++ ++ if (!bfd_close (mbfd)) ++ die ("error closing archive member"); ++ ++ if (!bfd_close (abfd)) ++ die ("error closing archive"); ++ ++ return 0; ++} diff --git a/binutils/bin2c.c b/binutils/bin2c.c new file mode 100644 -index 0000000..0719fb9 +index 0000000..3c9c094 --- /dev/null +++ b/binutils/bin2c.c @@ -0,0 +1,66 @@ +/* bin2c.c -- dump binary file in hex format -+ Copyright 2007, 2008 Free Software Foundation, Inc. ++ Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -29761,13 +30021,12 @@ index 0000000..0719fb9 +} diff --git a/binutils/binemul.c b/binutils/binemul.c new file mode 100644 -index 0000000..6bfcb15 +index 0000000..fccdec8 --- /dev/null +++ b/binutils/binemul.c -@@ -0,0 +1,149 @@ +@@ -0,0 +1,148 @@ +/* Binutils emulation layer. -+ Copyright 2002, 2003, 2005, 2007, 2008, 2010 -+ Free Software Foundation, Inc. ++ Copyright (C) 2002-2014 Free Software Foundation, Inc. + Written by Tom Rix, Red Hat Inc. + + This file is part of GNU Binutils. @@ -29916,12 +30175,12 @@ index 0000000..6bfcb15 +} diff --git a/binutils/binemul.h b/binutils/binemul.h new file mode 100644 -index 0000000..a93b7b0 +index 0000000..8698267 --- /dev/null +++ b/binutils/binemul.h @@ -0,0 +1,71 @@ +/* Binutils emulation layer. -+ Copyright 2002, 2003, 2005, 2007, 2008 Free Software Foundation, Inc. ++ Copyright (C) 2002-2014 Free Software Foundation, Inc. + Written by Tom Rix, Red Hat Inc. + + This file is part of GNU Binutils. @@ -29993,14 +30252,12 @@ index 0000000..a93b7b0 +#endif diff --git a/binutils/bucomm.c b/binutils/bucomm.c new file mode 100644 -index 0000000..8272d6a +index 0000000..fd73070 --- /dev/null +++ b/binutils/bucomm.c -@@ -0,0 +1,628 @@ +@@ -0,0 +1,626 @@ +/* bucomm.c -- Bin Utils COMmon code. -+ Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002, -+ 2003, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2014 -+ Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -30627,14 +30884,12 @@ index 0000000..8272d6a +} diff --git a/binutils/bucomm.h b/binutils/bucomm.h new file mode 100644 -index 0000000..fcbc32b +index 0000000..a93c378 --- /dev/null +++ b/binutils/bucomm.h -@@ -0,0 +1,79 @@ +@@ -0,0 +1,77 @@ +/* bucomm.h -- binutils common include file. -+ Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, -+ 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2009 -+ Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -30712,13 +30967,12 @@ index 0000000..fcbc32b +#endif /* _BUCOMM_H */ diff --git a/binutils/budbg.h b/binutils/budbg.h new file mode 100644 -index 0000000..b87defb +index 0000000..9753ddf --- /dev/null +++ b/binutils/budbg.h -@@ -0,0 +1,57 @@ +@@ -0,0 +1,56 @@ +/* budbg.c -- Interfaces to the generic debugging information routines. -+ Copyright 1995, 1996, 2002, 2003, 2005, 2007, 2008, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1995-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor . + + This file is part of GNU Binutils. @@ -30775,13 +31029,12 @@ index 0000000..b87defb +#endif diff --git a/binutils/coffdump.c b/binutils/coffdump.c new file mode 100644 -index 0000000..d871e1e +index 0000000..b4c8415 --- /dev/null +++ b/binutils/coffdump.c -@@ -0,0 +1,558 @@ +@@ -0,0 +1,557 @@ +/* Coff file dumper. -+ Copyright 1994, 1995, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007, -+ 2011 Free Software Foundation, Inc. ++ Copyright (C) 1994-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -31339,13 +31592,12 @@ index 0000000..d871e1e +} diff --git a/binutils/coffgrok.c b/binutils/coffgrok.c new file mode 100644 -index 0000000..746edc1 +index 0000000..f37f266 --- /dev/null +++ b/binutils/coffgrok.c -@@ -0,0 +1,744 @@ +@@ -0,0 +1,743 @@ +/* coffgrok.c -+ Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2003, 2004, 2005, -+ 2007, 2009 Free Software Foundation, Inc. ++ Copyright (C) 1994-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -32089,12 +32341,12 @@ index 0000000..746edc1 +} diff --git a/binutils/coffgrok.h b/binutils/coffgrok.h new file mode 100644 -index 0000000..fd4a952 +index 0000000..75e0824 --- /dev/null +++ b/binutils/coffgrok.h @@ -0,0 +1,226 @@ +/* coffgrok.h -+ Copyright 2001, 2002, 2003, 2005, 2007, 2014 Free Software Foundation, Inc. ++ Copyright (C) 2001-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -32598,10 +32850,10 @@ index 0000000..0a8551f +#undef _POSIX_SOURCE diff --git a/binutils/configure b/binutils/configure new file mode 100755 -index 0000000..fcf9784 +index 0000000..1272e53 --- /dev/null +++ b/binutils/configure -@@ -0,0 +1,16653 @@ +@@ -0,0 +1,16656 @@ +#! /bin/sh +# Guess values for system-dependent variables and create Makefiles. +# Generated by GNU Autoconf 2.64. @@ -44196,6 +44448,9 @@ index 0000000..fcf9784 + + + ++# Set the 'development' global. ++. $srcdir/../bfd/development.sh ++ +GCC_WARN_CFLAGS="-W -Wall -Wstrict-prototypes -Wmissing-prototypes" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ @@ -44230,8 +44485,8 @@ index 0000000..fcf9784 + *) ;; +esac + -+# Enable -Werror by default when using gcc -+if test "${GCC}" = yes -a -z "${ERROR_ON_WARNING}" ; then ++# Enable -Werror by default when using gcc. Turn it off for releases. ++if test "${GCC}" = yes -a -z "${ERROR_ON_WARNING}" -a "$development" = true ; then + ERROR_ON_WARNING=yes +fi + @@ -49257,7 +49512,7 @@ index 0000000..fcf9784 + diff --git a/binutils/configure.com b/binutils/configure.com new file mode 100644 -index 0000000..baf987c +index 0000000..eb354ef --- /dev/null +++ b/binutils/configure.com @@ -0,0 +1,146 @@ @@ -49266,7 +49521,7 @@ index 0000000..baf987c +$! We do not use the configure script, since we do not have /bin/sh +$! to execute it. +$! -+$! Copyright 2012 Free Software Foundation ++$! Copyright (C) 2012-2014 Free Software Foundation, Inc. +$! +$! This file is free software; you can redistribute it and/or modify +$! it under the terms of the GNU General Public License as published by @@ -49409,13 +49664,13 @@ index 0000000..baf987c +$EOD diff --git a/binutils/configure.in b/binutils/configure.in new file mode 100644 -index 0000000..4072178 +index 0000000..f3e6130 --- /dev/null +++ b/binutils/configure.in @@ -0,0 +1,499 @@ +dnl Process this file with autoconf to produce a configure script. +dnl -+dnl Copyright 2012 Free Software Foundation ++dnl Copyright (C) 2012-2014 Free Software Foundation, Inc. +dnl +dnl This file is free software; you can redistribute it and/or modify +dnl it under the terms of the GNU General Public License as published by @@ -49914,7 +50169,7 @@ index 0000000..4072178 +AC_OUTPUT diff --git a/binutils/configure.tgt b/binutils/configure.tgt new file mode 100644 -index 0000000..90f735b +index 0000000..e9184a5 --- /dev/null +++ b/binutils/configure.tgt @@ -0,0 +1,42 @@ @@ -49923,7 +50178,7 @@ index 0000000..90f735b +# file lets us skip running autoconf when modifying target specific +# information. + -+# Copyright 2012 Free Software Foundation ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -49962,13 +50217,12 @@ index 0000000..90f735b +esac diff --git a/binutils/cxxfilt.c b/binutils/cxxfilt.c new file mode 100644 -index 0000000..770df9b +index 0000000..157ebe0 --- /dev/null +++ b/binutils/cxxfilt.c -@@ -0,0 +1,289 @@ +@@ -0,0 +1,288 @@ +/* Demangler for GNU C++ - main program -+ Copyright 1989, 1991, 1994, 1995, 1996, 1997, 1998, 1999, -+ 2000, 2001, 2002, 2003, 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 1989-2014 Free Software Foundation, Inc. + Written by James Clark (jjc@jclark.uucp) + Rewritten by Fred Fish (fnf@cygnus.com) for ARM and Lucid demangling + Modified by Satish Pai (pai@apollo.hp.com) for HP demangling @@ -50257,12 +50511,12 @@ index 0000000..770df9b +} diff --git a/binutils/debug.c b/binutils/debug.c new file mode 100644 -index 0000000..0aa1f50 +index 0000000..2934ea5 --- /dev/null +++ b/binutils/debug.c @@ -0,0 +1,3371 @@ +/* debug.c -- Handle generic debugging information. -+ Copyright 1995-2013 Free Software Foundation, Inc. ++ Copyright (C) 1995-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor . + + This file is part of GNU Binutils. @@ -53634,13 +53888,12 @@ index 0000000..0aa1f50 +} diff --git a/binutils/debug.h b/binutils/debug.h new file mode 100644 -index 0000000..1846119 +index 0000000..4850ccc --- /dev/null +++ b/binutils/debug.h -@@ -0,0 +1,793 @@ +@@ -0,0 +1,792 @@ +/* debug.h -- Describe generic debugging information. -+ Copyright 1995, 1996, 2002, 2003, 2005, 2007, 2009 -+ Free Software Foundation, Inc. ++ Copyright (C) 1995-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor . + + This file is part of GNU Binutils. @@ -54433,14 +54686,15 @@ index 0000000..1846119 +#endif /* DEBUG_H */ diff --git a/binutils/deflex.l b/binutils/deflex.l new file mode 100644 -index 0000000..317f6be +index 0000000..0a9a0d9 --- /dev/null +++ b/binutils/deflex.l -@@ -0,0 +1,98 @@ +@@ -0,0 +1,97 @@ ++%option noinput nounput ++ +%{/* deflex.l - Lexer for .def files */ + -+/* Copyright 1995, 1997, 1998, 1999, 2002, 2003, 2004, 2005, 2007 -+ Free Software Foundation, Inc. ++/* Copyright (C) 1995-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -54467,8 +54721,6 @@ index 0000000..317f6be +#include "defparse.h" +#include "dlltool.h" + -+#define YY_NO_UNPUT -+ +int linenumber; + +%} @@ -54537,14 +54789,13 @@ index 0000000..317f6be +#endif diff --git a/binutils/defparse.y b/binutils/defparse.y new file mode 100644 -index 0000000..a4e73eb +index 0000000..badc312 --- /dev/null +++ b/binutils/defparse.y -@@ -0,0 +1,245 @@ +@@ -0,0 +1,244 @@ +%{ /* defparse.y - parser for .def files */ + -+/* Copyright 1995, 1997, 1998, 1999, 2001, 2004, 2005, 2007 -+ Free Software Foundation, Inc. ++/* Copyright (C) 1995-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -54814,13 +55065,12 @@ index 0000000..4823f1e +$s/$/ \\/ diff --git a/binutils/dlltool.c b/binutils/dlltool.c new file mode 100644 -index 0000000..b540975 +index 0000000..8b013f0 --- /dev/null +++ b/binutils/dlltool.c -@@ -0,0 +1,4548 @@ +@@ -0,0 +1,4547 @@ +/* dlltool.c -- tool to generate stuff for PE style DLLs -+ Copyright 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, -+ 2005, 2006, 2007, 2008, 2009, 2011, 2012, 2014 Free Software Foundation, Inc. ++ Copyright (C) 1995-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -59368,13 +59618,12 @@ index 0000000..b540975 +#endif /* DLLTOOL_MCORE_ELF */ diff --git a/binutils/dlltool.h b/binutils/dlltool.h new file mode 100644 -index 0000000..f3b203b +index 0000000..c6b1243 --- /dev/null +++ b/binutils/dlltool.h -@@ -0,0 +1,40 @@ +@@ -0,0 +1,39 @@ +/* dlltool.h -- header file for dlltool -+ Copyright 1997, 1998, 2003, 2004, 2005, 2007, 2009, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1997-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -59414,13 +59663,12 @@ index 0000000..f3b203b +extern int linenumber; diff --git a/binutils/dllwrap.c b/binutils/dllwrap.c new file mode 100644 -index 0000000..5f2c803 +index 0000000..85ace9b --- /dev/null +++ b/binutils/dllwrap.c -@@ -0,0 +1,1254 @@ +@@ -0,0 +1,1253 @@ +/* dllwrap.c -- wrapper for DLLTOOL and GCC to generate PE style DLLs -+ Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2009, -+ 2011, 2012, 2014 Free Software Foundation, Inc. ++ Copyright (C) 1998-2014 Free Software Foundation, Inc. + Contributed by Mumit Khan (khan@xraylith.wisc.edu). + + This file is part of GNU Binutils. @@ -60674,13 +60922,13 @@ index 0000000..5f2c803 +} diff --git a/binutils/doc/Makefile.am b/binutils/doc/Makefile.am new file mode 100644 -index 0000000..51fa0a0 +index 0000000..e7a38c2 --- /dev/null +++ b/binutils/doc/Makefile.am @@ -0,0 +1,201 @@ +## Process this file with automake to generate Makefile.in +# -+# Copyright 2012 Free Software Foundation ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -60881,7 +61129,7 @@ index 0000000..51fa0a0 +info-local: $(MANS) diff --git a/binutils/doc/Makefile.in b/binutils/doc/Makefile.in new file mode 100644 -index 0000000..596dbda +index 0000000..9e22548 --- /dev/null +++ b/binutils/doc/Makefile.in @@ -0,0 +1,888 @@ @@ -60903,7 +61151,7 @@ index 0000000..596dbda +@SET_MAKE@ + +# -+# Copyright 2012 Free Software Foundation ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -61775,10 +62023,10 @@ index 0000000..596dbda +.NOEXPORT: diff --git a/binutils/doc/binutils.texi b/binutils/doc/binutils.texi new file mode 100644 -index 0000000..39aa077 +index 0000000..3375d36 --- /dev/null +++ b/binutils/doc/binutils.texi -@@ -0,0 +1,4900 @@ +@@ -0,0 +1,4903 @@ +\input texinfo @c -*- Texinfo -*- +@setfilename binutils.info +@settitle @sc{gnu} Binary Utilities @@ -61791,7 +62039,7 @@ index 0000000..39aa077 + +@copying +@c man begin COPYRIGHT -+Copyright @copyright{} 1991-2013 Free Software Foundation, Inc. ++Copyright @copyright{} 1991-2014 Free Software Foundation, Inc. + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License, Version 1.3 @@ -61955,7 +62203,7 @@ index 0000000..39aa077 +@c man title ar create, modify, and extract from archives + +@smallexample -+ar [@option{--plugin} @var{name}] [-]@var{p}[@var{mod} [@var{relpos}] [@var{count}]] [@option{--target} @var{bfdname}] @var{archive} [@var{member}@dots{}] ++ar [-]@var{p}[@var{mod}] [@option{--plugin} @var{name}] [@option{--target} @var{bfdname}] [@var{relpos}] [@var{count}] @var{archive} [@var{member}@dots{}] +ar -M [ cfa_offset = fc->cfa_offset; ++ rs->cfa_reg = fc->cfa_reg; ++ rs->ra = fc->ra; ++ rs->cfa_exp = fc->cfa_exp; + rs->ncols = fc->ncols; + rs->col_type = (short int *) xcmalloc (rs->ncols, -+ sizeof (short int)); -+ rs->col_offset = (int *) xcmalloc (rs->ncols, sizeof (int)); -+ memcpy (rs->col_type, fc->col_type, rs->ncols); -+ memcpy (rs->col_offset, fc->col_offset, rs->ncols * sizeof (int)); ++ sizeof (* rs->col_type)); ++ rs->col_offset = (int *) xcmalloc (rs->ncols, sizeof (* rs->col_offset)); ++ memcpy (rs->col_type, fc->col_type, rs->ncols * sizeof (* fc->col_type)); ++ memcpy (rs->col_offset, fc->col_offset, rs->ncols * sizeof (* fc->col_offset)); + rs->next = remembered_state; + remembered_state = rs; + break; @@ -73225,10 +73476,14 @@ index 0000000..1a62d9f + if (rs) + { + remembered_state = rs->next; ++ fc->cfa_offset = rs->cfa_offset; ++ fc->cfa_reg = rs->cfa_reg; ++ fc->ra = rs->ra; ++ fc->cfa_exp = rs->cfa_exp; + frame_need_space (fc, rs->ncols - 1); -+ memcpy (fc->col_type, rs->col_type, rs->ncols); ++ memcpy (fc->col_type, rs->col_type, rs->ncols * sizeof (* rs->col_type)); + memcpy (fc->col_offset, rs->col_offset, -+ rs->ncols * sizeof (int)); ++ rs->ncols * sizeof (* rs->col_offset)); + free (rs->col_type); + free (rs->col_offset); + free (rs); @@ -74260,12 +74515,12 @@ index 0000000..1a62d9f +}; diff --git a/binutils/dwarf.h b/binutils/dwarf.h new file mode 100644 -index 0000000..1cd4201 +index 0000000..db235a9 --- /dev/null +++ b/binutils/dwarf.h @@ -0,0 +1,254 @@ +/* dwarf.h - DWARF support header file -+ Copyright 2005-2013 Free Software Foundation, Inc. ++ Copyright (C) 2005-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -74520,12 +74775,12 @@ index 0000000..1cd4201 +extern dwarf_vma read_leb128 (unsigned char *, unsigned int *, bfd_boolean, const unsigned char * const); diff --git a/binutils/elfcomm.c b/binutils/elfcomm.c new file mode 100644 -index 0000000..d5b4313 +index 0000000..f1502b9 --- /dev/null +++ b/binutils/elfcomm.c @@ -0,0 +1,853 @@ +/* elfcomm.c -- common code for ELF format file. -+ Copyright 2010-2013 Free Software Foundation, Inc. ++ Copyright (C) 2010-2014 Free Software Foundation, Inc. + + Originally developed by Eric Youngdale + Modifications by Nick Clifton @@ -75379,13 +75634,12 @@ index 0000000..d5b4313 +} diff --git a/binutils/elfcomm.h b/binutils/elfcomm.h new file mode 100644 -index 0000000..a8c3aa3 +index 0000000..f41a8ac --- /dev/null +++ b/binutils/elfcomm.h -@@ -0,0 +1,112 @@ +@@ -0,0 +1,111 @@ +/* elfcomm.h -- include file of common code for ELF format file. -+ Copyright 2010 -+ Free Software Foundation, Inc. ++ Copyright (C) 2010-2014 Free Software Foundation, Inc. + + Originally developed by Eric Youngdale + Modifications by Nick Clifton @@ -75497,13 +75751,12 @@ index 0000000..a8c3aa3 +#endif /* _ELFCOMM_H */ diff --git a/binutils/elfedit.c b/binutils/elfedit.c new file mode 100644 -index 0000000..d9e23a1 +index 0000000..5f21382 --- /dev/null +++ b/binutils/elfedit.c -@@ -0,0 +1,738 @@ +@@ -0,0 +1,737 @@ +/* elfedit.c -- Update the ELF header of an ELF format file -+ Copyright 2010, 2011, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 2010-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -76241,14 +76494,14 @@ index 0000000..d9e23a1 +} diff --git a/binutils/embedspu.sh b/binutils/embedspu.sh new file mode 100644 -index 0000000..8b19e76 +index 0000000..82eb6e9 --- /dev/null +++ b/binutils/embedspu.sh @@ -0,0 +1,260 @@ +#! /bin/sh +# Embed an SPU ELF executable into a PowerPC object file. +# -+# Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++# Copyright (C) 2006-2014 Free Software Foundation, Inc. +# +# This file is part of GNU Binutils. +# @@ -76507,13 +76760,12 @@ index 0000000..8b19e76 +main "$@" diff --git a/binutils/emul_aix.c b/binutils/emul_aix.c new file mode 100644 -index 0000000..2f6a3e4 +index 0000000..78ccccc --- /dev/null +++ b/binutils/emul_aix.c -@@ -0,0 +1,141 @@ +@@ -0,0 +1,140 @@ +/* Binutils emulation layer. -+ Copyright 2002, 2003, 2005, 2006, 2007, 2008, 2010 -+ Free Software Foundation, Inc. ++ Copyright (C) 2002-2014 Free Software Foundation, Inc. + Written by Tom Rix, Red Hat Inc. + + This file is part of GNU Binutils. @@ -76564,17 +76816,17 @@ index 0000000..2f6a3e4 +static bfd_boolean +check_aix (bfd *try_bfd) +{ -+ extern const bfd_target rs6000coff_vec; -+ extern const bfd_target rs6000coff64_vec; -+ extern const bfd_target aix5coff64_vec; ++ extern const bfd_target rs6000_xcoff_vec; ++ extern const bfd_target rs6000_xcoff64_vec; ++ extern const bfd_target rs6000_xcoff64_aix_vec; + + if (bfd_check_format (try_bfd, bfd_object)) + { -+ if (!X32 && try_bfd->xvec == &rs6000coff_vec) ++ if (!X32 && try_bfd->xvec == &rs6000_xcoff_vec) + return FALSE; + -+ if (!X64 && (try_bfd->xvec == &rs6000coff64_vec -+ || try_bfd->xvec == &aix5coff64_vec)) ++ if (!X64 && (try_bfd->xvec == &rs6000_xcoff64_vec ++ || try_bfd->xvec == &rs6000_xcoff64_aix_vec)) + return FALSE; + } + return TRUE; @@ -76654,12 +76906,12 @@ index 0000000..2f6a3e4 +}; diff --git a/binutils/emul_vanilla.c b/binutils/emul_vanilla.c new file mode 100644 -index 0000000..d15287d +index 0000000..98ac822 --- /dev/null +++ b/binutils/emul_vanilla.c @@ -0,0 +1,30 @@ +/* Binutils emulation layer. -+ Copyright (C) 2002, 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 2002-2014 Free Software Foundation, Inc. + Written by Tom Rix, Red Hat Inc. + + This file is part of GNU Binutils. @@ -76690,13 +76942,12 @@ index 0000000..d15287d +}; diff --git a/binutils/filemode.c b/binutils/filemode.c new file mode 100644 -index 0000000..8b29def +index 0000000..6c7f673 --- /dev/null +++ b/binutils/filemode.c -@@ -0,0 +1,249 @@ +@@ -0,0 +1,248 @@ +/* filemode.c -- make a string describing file modes -+ Copyright 1985, 1990, 1991, 1994, 1995, 1997, 1999, 2002, 2003, 2005, -+ 2007 Free Software Foundation, Inc. ++ Copyright (C) 1985-2014 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by @@ -76945,13 +77196,12 @@ index 0000000..8b29def +} diff --git a/binutils/ieee.c b/binutils/ieee.c new file mode 100644 -index 0000000..044da31 +index 0000000..4834047 --- /dev/null +++ b/binutils/ieee.c -@@ -0,0 +1,7411 @@ +@@ -0,0 +1,7410 @@ +/* ieee.c -- Read and write IEEE-695 debugging information. -+ Copyright 1996, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007, -+ 2008, 2009, 2010, 2011 Free Software Foundation, Inc. ++ Copyright (C) 1996-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor . + + This file is part of GNU Binutils. @@ -84362,11 +84612,11 @@ index 0000000..044da31 +} diff --git a/binutils/is-ranlib.c b/binutils/is-ranlib.c new file mode 100644 -index 0000000..947d8d2 +index 0000000..e5d41ec --- /dev/null +++ b/binutils/is-ranlib.c @@ -0,0 +1,22 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -84390,11 +84640,11 @@ index 0000000..947d8d2 +int is_ranlib = 1; diff --git a/binutils/is-strip.c b/binutils/is-strip.c new file mode 100644 -index 0000000..1fddbe2 +index 0000000..4b892ae --- /dev/null +++ b/binutils/is-strip.c @@ -0,0 +1,23 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -84419,7 +84669,7 @@ index 0000000..1fddbe2 +int is_strip = 1; diff --git a/binutils/makefile.vms b/binutils/makefile.vms new file mode 100644 -index 0000000..7fe2e0c +index 0000000..0630b4b --- /dev/null +++ b/binutils/makefile.vms @@ -0,0 +1,90 @@ @@ -84430,7 +84680,7 @@ index 0000000..7fe2e0c +# +# Created by Klaus Kaempf, kkaempf@rmi.de +# -+# Copyright 2012 Free Software Foundation ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -84515,11 +84765,11 @@ index 0000000..7fe2e0c + $(RM) makefile.vms; diff --git a/binutils/maybe-ranlib.c b/binutils/maybe-ranlib.c new file mode 100644 -index 0000000..64f9514 +index 0000000..70498cb --- /dev/null +++ b/binutils/maybe-ranlib.c @@ -0,0 +1,23 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -84544,11 +84794,11 @@ index 0000000..64f9514 +int is_ranlib = -1; diff --git a/binutils/maybe-strip.c b/binutils/maybe-strip.c new file mode 100644 -index 0000000..0502fbb +index 0000000..ade4adb --- /dev/null +++ b/binutils/maybe-strip.c @@ -0,0 +1,23 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -84573,13 +84823,12 @@ index 0000000..0502fbb +int is_strip = -1; diff --git a/binutils/mclex.c b/binutils/mclex.c new file mode 100644 -index 0000000..2f0e144 +index 0000000..8e2a94e --- /dev/null +++ b/binutils/mclex.c -@@ -0,0 +1,441 @@ +@@ -0,0 +1,440 @@ +/* mclex.c -- lexer for Windows mc files parser. -+ Copyright 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 2007-2014 Free Software Foundation, Inc. + + Written by Kai Tietz, Onevision. + @@ -85020,13 +85269,12 @@ index 0000000..2f0e144 +} diff --git a/binutils/mcparse.y b/binutils/mcparse.y new file mode 100644 -index 0000000..35328d1 +index 0000000..121cfa9 --- /dev/null +++ b/binutils/mcparse.y -@@ -0,0 +1,356 @@ +@@ -0,0 +1,355 @@ +%{ /* mcparse.y -- parser for Windows mc files -+ Copyright 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 2007-2014 Free Software Foundation, Inc. + + Parser for Windows mc files + Written by Kai Tietz, Onevision. @@ -85382,14 +85630,12 @@ index 0000000..35328d1 +/* Something else. */ diff --git a/binutils/nlmconv.c b/binutils/nlmconv.c new file mode 100644 -index 0000000..64214e7 +index 0000000..0513f29 --- /dev/null +++ b/binutils/nlmconv.c -@@ -0,0 +1,2138 @@ +@@ -0,0 +1,2136 @@ +/* nlmconv.c -- NLM conversion program -+ Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, -+ 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2011, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1993-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -87526,12 +87772,12 @@ index 0000000..64214e7 +} diff --git a/binutils/nlmconv.h b/binutils/nlmconv.h new file mode 100644 -index 0000000..7ab2dd3 +index 0000000..318a9af --- /dev/null +++ b/binutils/nlmconv.h @@ -0,0 +1,86 @@ +/* nlmconv.h -- header file for NLM conversion program -+ Copyright 1993, 2002, 2003, 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 1993-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -87618,13 +87864,12 @@ index 0000000..7ab2dd3 +extern bfd_boolean nlmlex_file (const char *); diff --git a/binutils/nlmheader.y b/binutils/nlmheader.y new file mode 100644 -index 0000000..9550fe5 +index 0000000..b011279 --- /dev/null +++ b/binutils/nlmheader.y -@@ -0,0 +1,960 @@ +@@ -0,0 +1,959 @@ +%{/* nlmheader.y - parse NLM header specification keywords. -+ Copyright 1993, 1994, 1995, 1997, 1998, 2001, 2002, 2003, 2005, 2007, -+ 2010, 2014 Free Software Foundation, Inc. ++ Copyright (C) 1993-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -88584,14 +88829,12 @@ index 0000000..9550fe5 +} diff --git a/binutils/nm.c b/binutils/nm.c new file mode 100644 -index 0000000..156194f +index 0000000..2a44a84 --- /dev/null +++ b/binutils/nm.c -@@ -0,0 +1,1706 @@ +@@ -0,0 +1,1707 @@ +/* nm.c -- Describe symbol table of a rel file. -+ Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, -+ 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009, 2010, 2011, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -88767,7 +89010,11 @@ index 0000000..156194f +static char desc_format[] = "%04x"; + +static char *target = NULL; -+static char *plugin_target = NULL; ++#if BFD_SUPPORTS_PLUGINS ++static const char *plugin_target = "plugin"; ++#else ++static const char *plugin_target = NULL; ++#endif + +/* Used to cache the line numbers for a BFD. */ +static bfd *lineno_cache_bfd; @@ -90238,7 +90485,6 @@ index 0000000..156194f + + case OPTION_PLUGIN: /* --plugin */ +#if BFD_SUPPORTS_PLUGINS -+ plugin_target = "plugin"; + bfd_plugin_set_plugin (optarg); +#else + fatal (_("sorry - this program has been built without plugin support\n")); @@ -90296,11 +90542,11 @@ index 0000000..156194f +} diff --git a/binutils/not-ranlib.c b/binutils/not-ranlib.c new file mode 100644 -index 0000000..6431f84 +index 0000000..9fa108b --- /dev/null +++ b/binutils/not-ranlib.c @@ -0,0 +1,22 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -90324,11 +90570,11 @@ index 0000000..6431f84 +int is_ranlib = 0; diff --git a/binutils/not-strip.c b/binutils/not-strip.c new file mode 100644 -index 0000000..8ffbba6 +index 0000000..64aa244 --- /dev/null +++ b/binutils/not-strip.c @@ -0,0 +1,23 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -90353,12 +90599,12 @@ index 0000000..8ffbba6 +int is_strip = 0; diff --git a/binutils/objcopy.c b/binutils/objcopy.c new file mode 100644 -index 0000000..9a6bb72 +index 0000000..46fd8bc --- /dev/null +++ b/binutils/objcopy.c -@@ -0,0 +1,4368 @@ +@@ -0,0 +1,4397 @@ +/* objcopy.c -- copy object file from input to output, optionally massaging it. -+ Copyright 1991-2013 Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -91500,6 +91746,24 @@ index 0000000..9a6bb72 + return FALSE; +} + ++static bfd_boolean ++is_nondebug_keep_contents_section (bfd *ibfd, asection *isection) ++{ ++ /* Always keep ELF note sections. */ ++ if (ibfd->xvec->flavour == bfd_target_elf_flavour) ++ return (elf_section_type (isection) == SHT_NOTE); ++ ++ /* Always keep the .build-id section for PE/COFF. ++ ++ Strictly, this should be written "always keep the section storing the debug ++ directory", but that may be the .text section for objects produced by some ++ tools, which it is not sensible to keep. */ ++ if (ibfd->xvec->flavour == bfd_target_coff_flavour) ++ return (strcmp (bfd_get_section_name (ibfd, isection), ".build-id") == 0); ++ ++ return FALSE; ++} ++ +/* Return true if SYM is a hidden symbol. */ + +static bfd_boolean @@ -91957,6 +92221,13 @@ index 0000000..9a6bb72 + return FALSE; + } + ++ if (ibfd->sections == NULL) ++ { ++ non_fatal (_("error: the input file '%s' has no sections"), ++ bfd_get_archive_filename (ibfd)); ++ return FALSE; ++ } ++ + if (verbose) + printf (_("copy from `%s' [%s] to `%s' [%s]\n"), + bfd_get_archive_filename (ibfd), bfd_get_target (ibfd), @@ -92234,7 +92505,12 @@ index 0000000..9a6bb72 + + bfd_byte * contents = xmalloc (size); + if (bfd_get_section_contents (ibfd, sec, contents, 0, size)) -+ fwrite (contents, 1, size, f); ++ { ++ if (fwrite (contents, 1, size, f) != size) ++ fatal (_("error writing section contents to %s (error: %s)"), ++ pdump->filename, ++ strerror (errno)); ++ } + else + bfd_nonfatal_message (NULL, ibfd, sec, + _("could not retrieve section contents")); @@ -93042,8 +93318,7 @@ index 0000000..9a6bb72 + flags = p->flags | (flags & (SEC_HAS_CONTENTS | SEC_RELOC)); + else if (strip_symbols == STRIP_NONDEBUG + && (flags & (SEC_ALLOC | SEC_GROUP)) != 0 -+ && !(ibfd->xvec->flavour == bfd_target_elf_flavour -+ && elf_section_type (isection) == SHT_NOTE)) ++ && !is_nondebug_keep_contents_section (ibfd, isection)) + { + flags &= ~(SEC_HAS_CONTENTS | SEC_LOAD | SEC_GROUP); + if (obfd->xvec->flavour == bfd_target_elf_flavour) @@ -94727,12 +95002,12 @@ index 0000000..9a6bb72 +} diff --git a/binutils/objdump.c b/binutils/objdump.c new file mode 100644 -index 0000000..0098ae7 +index 0000000..14f4122 --- /dev/null +++ b/binutils/objdump.c @@ -0,0 +1,3697 @@ +/* objdump.c -- dump information about an object file. -+ Copyright 1990-2013 Free Software Foundation, Inc. ++ Copyright (C) 1990-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -96992,7 +97267,7 @@ index 0000000..0098ae7 + if (section->start != NULL) + return 1; + -+ section->address = 0; ++ section->address = bfd_get_section_vma (abfd, sec); + section->size = bfd_get_section_size (sec); + section->start = NULL; + ret = bfd_get_full_section_contents (abfd, sec, §ion->start); @@ -98430,12 +98705,12 @@ index 0000000..0098ae7 +} diff --git a/binutils/objdump.h b/binutils/objdump.h new file mode 100644 -index 0000000..214ecc6 +index 0000000..5ac00e7 --- /dev/null +++ b/binutils/objdump.h @@ -0,0 +1,51 @@ +/* objdump.h -+ Copyright 2011, 2012 Free Software Foundation, Inc. ++ Copyright (C) 2011-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -98487,12 +98762,12 @@ index 0000000..214ecc6 +extern const struct objdump_private_desc objdump_private_desc_mach_o; diff --git a/binutils/od-macho.c b/binutils/od-macho.c new file mode 100644 -index 0000000..e62f137 +index 0000000..4371f9f --- /dev/null +++ b/binutils/od-macho.c -@@ -0,0 +1,1119 @@ +@@ -0,0 +1,2145 @@ +/* od-macho.c -- dump information about an Mach-O object file. -+ Copyright 2011, 2012 Free Software Foundation, Inc. ++ Copyright (C) 2011-2014 Free Software Foundation, Inc. + Written by Tristan Gingold, Adacore. + + This file is part of GNU Binutils. @@ -98524,6 +98799,7 @@ index 0000000..e62f137 +#include "mach-o.h" +#include "mach-o/external.h" +#include "mach-o/codesign.h" ++#include "mach-o/unwind.h" + +/* Index of the options in the options[] array. */ +#define OPT_HEADER 0 @@ -98533,6 +98809,11 @@ index 0000000..e62f137 +#define OPT_DYSYMTAB 4 +#define OPT_CODESIGN 5 +#define OPT_SEG_SPLIT_INFO 6 ++#define OPT_COMPACT_UNWIND 7 ++#define OPT_FUNCTION_STARTS 8 ++#define OPT_DATA_IN_CODE 9 ++#define OPT_TWOLEVEL_HINTS 10 ++#define OPT_DYLD_INFO 11 + +/* List of actions. */ +static struct objdump_private_option options[] = @@ -98544,6 +98825,11 @@ index 0000000..e62f137 + { "dysymtab", 0 }, + { "codesign", 0 }, + { "seg_split_info", 0 }, ++ { "compact_unwind", 0 }, ++ { "function_starts", 0 }, ++ { "data_in_code", 0 }, ++ { "twolevel_hints", 0 }, ++ { "dyld_info", 0 }, + { NULL, 0 } + }; + @@ -98554,13 +98840,18 @@ index 0000000..e62f137 +{ + fprintf (stream, _("\ +For Mach-O files:\n\ -+ header Display the file header\n\ -+ section Display the segments and sections commands\n\ -+ map Display the section map\n\ -+ load Display the load commands\n\ -+ dysymtab Display the dynamic symbol table\n\ -+ codesign Display code signature\n\ -+ seg_split_info Display segment split info\n\ ++ header Display the file header\n\ ++ section Display the segments and sections commands\n\ ++ map Display the section map\n\ ++ load Display the load commands\n\ ++ dysymtab Display the dynamic symbol table\n\ ++ codesign Display code signature\n\ ++ seg_split_info Display segment split info\n\ ++ compact_unwind Display compact unwinding info\n\ ++ function_starts Display start address of functions\n\ ++ data_in_code Display data in code entries\n\ ++ twolevel_hints Display the two-level namespace lookup hints table\n\ ++ dyld_info Display dyld information\n\ +")); +} + @@ -98588,6 +98879,7 @@ index 0000000..e62f137 + { "powerpc", BFD_MACH_O_CPU_TYPE_POWERPC }, + { "powerpc_64", BFD_MACH_O_CPU_TYPE_POWERPC_64 }, + { "x86_64", BFD_MACH_O_CPU_TYPE_X86_64 }, ++ { "arm64", BFD_MACH_O_CPU_TYPE_ARM64 }, + { NULL, 0} +}; + @@ -98728,6 +99020,15 @@ index 0000000..e62f137 + printf ("-"); +} + ++/* Print a bfd_uint64_t, using a platform independant style. */ ++ ++static void ++printf_uint64 (bfd_uint64_t v) ++{ ++ printf ("0x%08lx%08lx", ++ (unsigned long)((v >> 16) >> 16), (unsigned long)(v & 0xffffffffUL)); ++} ++ +static const char * +bfd_mach_o_get_name_or_null (const bfd_mach_o_xlat_name *table, + unsigned long val) @@ -98764,42 +99065,49 @@ index 0000000..e62f137 + h->filetype, + bfd_mach_o_get_name (bfd_mach_o_filetype_name, h->filetype)); + printf (_(" ncmds : %08lx (%lu)\n"), h->ncmds, h->ncmds); -+ printf (_(" sizeofcmds: %08lx\n"), h->sizeofcmds); ++ printf (_(" sizeofcmds: %08lx (%lu)\n"), h->sizeofcmds, h->sizeofcmds); + printf (_(" flags : %08lx ("), h->flags); + bfd_mach_o_print_flags (bfd_mach_o_header_flags_name, h->flags); + fputs (_(")\n"), stdout); + printf (_(" reserved : %08x\n"), h->reserved); ++ putchar ('\n'); ++} ++ ++static void ++disp_segment_prot (unsigned int prot) ++{ ++ putchar (prot & BFD_MACH_O_PROT_READ ? 'r' : '-'); ++ putchar (prot & BFD_MACH_O_PROT_WRITE ? 'w' : '-'); ++ putchar (prot & BFD_MACH_O_PROT_EXECUTE ? 'x' : '-'); +} + +static void +dump_section_map (bfd *abfd) +{ + bfd_mach_o_data_struct *mdata = bfd_mach_o_get_data (abfd); -+ unsigned int i; ++ bfd_mach_o_load_command *cmd; + unsigned int sec_nbr = 0; + + fputs (_("Segments and Sections:\n"), stdout); + fputs (_(" #: Segment name Section name Address\n"), stdout); + -+ for (i = 0; i < mdata->header.ncmds; i++) ++ for (cmd = mdata->first_command; cmd != NULL; cmd = cmd->next) + { + bfd_mach_o_segment_command *seg; + bfd_mach_o_section *sec; + -+ if (mdata->commands[i].type != BFD_MACH_O_LC_SEGMENT -+ && mdata->commands[i].type != BFD_MACH_O_LC_SEGMENT_64) ++ if (cmd->type != BFD_MACH_O_LC_SEGMENT ++ && cmd->type != BFD_MACH_O_LC_SEGMENT_64) + continue; + -+ seg = &mdata->commands[i].command.segment; ++ seg = &cmd->command.segment; + + printf ("[Segment %-16s ", seg->segname); + printf_vma (seg->vmaddr); + putchar ('-'); + printf_vma (seg->vmaddr + seg->vmsize - 1); + putchar (' '); -+ putchar (seg->initprot & BFD_MACH_O_PROT_READ ? 'r' : '-'); -+ putchar (seg->initprot & BFD_MACH_O_PROT_WRITE ? 'w' : '-'); -+ putchar (seg->initprot & BFD_MACH_O_PROT_EXECUTE ? 'x' : '-'); ++ disp_segment_prot (seg->initprot); + printf ("]\n"); + + for (sec = seg->sect_head; sec != NULL; sec = sec->next) @@ -98815,7 +99123,7 @@ index 0000000..e62f137 +} + +static void -+dump_section (bfd *abfd ATTRIBUTE_UNUSED, bfd_mach_o_section *sec) ++dump_section_header (bfd *abfd ATTRIBUTE_UNUSED, bfd_mach_o_section *sec) +{ + printf (" Section: %-16s %-16s (bfdname: %s)\n", + sec->sectname, sec->segname, sec->bfdsection->name); @@ -98868,23 +99176,28 @@ index 0000000..e62f137 + bfd_mach_o_segment_command *seg = &cmd->command.segment; + bfd_mach_o_section *sec; + -+ printf (" name: %s\n", *seg->segname ? seg->segname : "*none*"); -+ printf (" vmaddr: "); ++ printf (" name: %16s", *seg->segname ? seg->segname : "*none*"); ++ printf (" nsects: %lu", seg->nsects); ++ printf (" flags: %lx", seg->flags); ++ printf (" initprot: "); ++ disp_segment_prot (seg->initprot); ++ printf (" maxprot: "); ++ disp_segment_prot (seg->maxprot); ++ printf ("\n"); ++ printf (" vmaddr: "); + printf_vma (seg->vmaddr); + printf (" vmsize: "); + printf_vma (seg->vmsize); + printf ("\n"); -+ printf (" fileoff: "); ++ printf (" fileoff: "); + printf_vma (seg->fileoff); + printf (" filesize: "); + printf_vma ((bfd_vma)seg->filesize); + printf (" endoff: "); + printf_vma ((bfd_vma)(seg->fileoff + seg->filesize)); + printf ("\n"); -+ printf (" nsects: %lu ", seg->nsects); -+ printf (" flags: %lx\n", seg->flags); + for (sec = seg->sect_head; sec != NULL; sec = sec->next) -+ dump_section (abfd, sec); ++ dump_section_header (abfd, sec); +} + +static void @@ -99080,21 +99393,365 @@ index 0000000..e62f137 + +} + ++static bfd_boolean ++load_and_dump (bfd *abfd, ufile_ptr off, unsigned int len, ++ void (*dump)(bfd *abfd, unsigned char *buf, unsigned int len, ++ ufile_ptr off)) ++{ ++ unsigned char *buf; ++ ++ if (len == 0) ++ return TRUE; ++ ++ buf = xmalloc (len); ++ ++ if (bfd_seek (abfd, off, SEEK_SET) == 0 ++ && bfd_bread (buf, len, abfd) == len) ++ dump (abfd, buf, len, off); ++ else ++ return FALSE; ++ ++ free (buf); ++ return TRUE; ++} ++ ++static const bfd_mach_o_xlat_name bfd_mach_o_dyld_rebase_type_name[] = ++{ ++ { "pointer", BFD_MACH_O_REBASE_TYPE_POINTER }, ++ { "text_abs32", BFD_MACH_O_REBASE_TYPE_TEXT_ABSOLUTE32 }, ++ { "text_pcrel32", BFD_MACH_O_REBASE_TYPE_TEXT_PCREL32 }, ++ { NULL, 0 } ++}; ++ +static void -+dump_dyld_info (bfd *abfd ATTRIBUTE_UNUSED, bfd_mach_o_load_command *cmd) ++dump_dyld_info_rebase (bfd *abfd, unsigned char *buf, unsigned int len, ++ ufile_ptr off ATTRIBUTE_UNUSED) ++{ ++ unsigned int i; ++ bfd_mach_o_data_struct *mdata = bfd_mach_o_get_data (abfd); ++ unsigned int ptrsize = mdata->header.version == 2 ? 8 : 4; ++ ++ for (i = 0; i < len; ) ++ { ++ unsigned char b = buf[i++]; ++ unsigned char imm = b & BFD_MACH_O_REBASE_IMMEDIATE_MASK; ++ bfd_vma leb; ++ unsigned int leblen; ++ ++ printf (" [0x%04x] 0x%02x: ", i, b); ++ switch (b & BFD_MACH_O_REBASE_OPCODE_MASK) ++ { ++ case BFD_MACH_O_REBASE_OPCODE_DONE: ++ printf ("done\n"); ++ return; ++ case BFD_MACH_O_REBASE_OPCODE_SET_TYPE_IMM: ++ printf ("set_type %s\n", ++ bfd_mach_o_get_name (bfd_mach_o_dyld_rebase_type_name, imm)); ++ break; ++ case BFD_MACH_O_REBASE_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB: ++ leb = read_unsigned_leb128 (abfd, buf + i, &leblen); ++ printf ("set segment: %u and offset: 0x%08x\n", ++ imm, (unsigned) leb); ++ i += leblen; ++ break; ++ case BFD_MACH_O_REBASE_OPCODE_ADD_ADDR_ULEB: ++ leb = read_unsigned_leb128 (abfd, buf + i, &leblen); ++ printf ("add addr uleb: 0x%08x\n", (unsigned) leb); ++ i += leblen; ++ break; ++ case BFD_MACH_O_REBASE_OPCODE_ADD_ADDR_IMM_SCALED: ++ printf ("add addr imm scaled: %u\n", imm * ptrsize); ++ break; ++ case BFD_MACH_O_REBASE_OPCODE_DO_REBASE_IMM_TIMES: ++ printf ("rebase imm times: %u\n", imm); ++ break; ++ case BFD_MACH_O_REBASE_OPCODE_DO_REBASE_ULEB_TIMES: ++ leb = read_unsigned_leb128 (abfd, buf + i, &leblen); ++ printf ("rebase uleb times: %u\n", (unsigned) leb); ++ i += leblen; ++ break; ++ case BFD_MACH_O_REBASE_OPCODE_DO_REBASE_ADD_ADDR_ULEB: ++ leb = read_unsigned_leb128 (abfd, buf + i, &leblen); ++ printf ("rebase add addr uleb: %u\n", (unsigned) leb); ++ i += leblen; ++ break; ++ case BFD_MACH_O_REBASE_OPCODE_DO_REBASE_ULEB_TIMES_SKIPPING_ULEB: ++ leb = read_unsigned_leb128 (abfd, buf + i, &leblen); ++ printf ("rebase uleb times (%u)", (unsigned) leb); ++ i += leblen; ++ leb = read_unsigned_leb128 (abfd, buf + i, &leblen); ++ printf (" skipping uleb (%u)\n", (unsigned) leb); ++ i += leblen; ++ break; ++ default: ++ printf ("unknown\n"); ++ return; ++ } ++ } ++ printf (" rebase commands without end!\n"); ++} ++ ++static void ++dump_dyld_info_bind (bfd *abfd, unsigned char *buf, unsigned int len, ++ ufile_ptr off ATTRIBUTE_UNUSED) ++{ ++ unsigned int i; ++ bfd_mach_o_data_struct *mdata = bfd_mach_o_get_data (abfd); ++ unsigned int ptrsize = mdata->header.version == 2 ? 8 : 4; ++ ++ for (i = 0; i < len; ) ++ { ++ unsigned char b = buf[i++]; ++ unsigned char imm = b & BFD_MACH_O_BIND_IMMEDIATE_MASK; ++ bfd_vma leb; ++ unsigned int leblen; ++ ++ printf (" [0x%04x] 0x%02x: ", i, b); ++ switch (b & BFD_MACH_O_BIND_OPCODE_MASK) ++ { ++ case BFD_MACH_O_BIND_OPCODE_DONE: ++ printf ("done\n"); ++ return; ++ case BFD_MACH_O_BIND_OPCODE_SET_DYLIB_ORDINAL_IMM: ++ printf ("set dylib ordinal imm: %u\n", imm); ++ break; ++ case BFD_MACH_O_BIND_OPCODE_SET_DYLIB_ORDINAL_ULEB: ++ leb = read_unsigned_leb128 (abfd, buf + i, &leblen); ++ printf ("set dylib ordinal uleb: %u\n", imm); ++ i += leblen; ++ break; ++ case BFD_MACH_O_BIND_OPCODE_SET_DYLIB_SPECIAL_IMM: ++ imm = (imm != 0) ? imm | BFD_MACH_O_BIND_OPCODE_MASK : imm; ++ printf ("set dylib special imm: %d\n", imm); ++ break; ++ case BFD_MACH_O_BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM: ++ printf ("set symbol trailing flags imm: 0x%02x, ", imm); ++ for (; i < len && buf[i] != 0; i++) ++ putchar (buf[i] >= ' ' && buf[i] < 0x7f ? buf[i] : '?'); ++ putchar ('\n'); ++ i++; ++ break; ++ case BFD_MACH_O_BIND_OPCODE_SET_TYPE_IMM: ++ /* Kludge: use the same table as rebase type. */ ++ printf ("set_type %s\n", ++ bfd_mach_o_get_name (bfd_mach_o_dyld_rebase_type_name, imm)); ++ break; ++ case BFD_MACH_O_BIND_OPCODE_SET_ADDEND_SLEB: ++ { ++ bfd_signed_vma svma; ++ svma = read_unsigned_leb128 (abfd, buf + i, &leblen); ++ printf ("set addend sleb: 0x%08x\n", (unsigned) svma); ++ i += leblen; ++ } ++ break; ++ case BFD_MACH_O_BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB: ++ leb = read_unsigned_leb128 (abfd, buf + i, &leblen); ++ printf ("set segment: %u and offset: 0x%08x\n", ++ imm, (unsigned) leb); ++ i += leblen; ++ break; ++ case BFD_MACH_O_BIND_OPCODE_ADD_ADDR_ULEB: ++ leb = read_unsigned_leb128 (abfd, buf + i, &leblen); ++ printf ("add addr uleb: 0x%08x\n", (unsigned) leb); ++ i += leblen; ++ break; ++ case BFD_MACH_O_BIND_OPCODE_DO_BIND: ++ printf ("do bind\n"); ++ break; ++ case BFD_MACH_O_BIND_OPCODE_DO_BIND_ADD_ADDR_ULEB: ++ leb = read_unsigned_leb128 (abfd, buf + i, &leblen); ++ printf ("do bind add addr uleb: 0x%08x\n", (unsigned) leb); ++ i += leblen; ++ break; ++ case BFD_MACH_O_BIND_OPCODE_DO_BIND_ADD_ADDR_IMM_SCALED: ++ printf ("do bind add addr imm scaled: %u\n", imm * ptrsize); ++ break; ++ case BFD_MACH_O_BIND_OPCODE_DO_BIND_ULEB_TIMES_SKIPPING_ULEB: ++ leb = read_unsigned_leb128 (abfd, buf + i, &leblen); ++ printf ("do bind uleb times (%u)", (unsigned) leb); ++ i += leblen; ++ leb = read_unsigned_leb128 (abfd, buf + i, &leblen); ++ printf (" skipping uleb (%u)\n", (unsigned) leb); ++ i += leblen; ++ break; ++ default: ++ printf ("unknown\n"); ++ return; ++ } ++ } ++ printf (" bind commands without end!\n"); ++} ++ ++struct export_info_data ++{ ++ const unsigned char *name; ++ struct export_info_data *next; ++}; ++ ++static void ++dump_dyld_info_export_1 (bfd *abfd, unsigned char *buf, unsigned int len, ++ unsigned int off, struct export_info_data *parent, ++ struct export_info_data *base) ++{ ++ bfd_vma size; ++ unsigned int leblen; ++ unsigned int child_count; ++ unsigned int i; ++ ++ size = read_unsigned_leb128 (abfd, buf + off, &leblen); ++ off += leblen; ++ ++ if (size != 0) ++ { ++ bfd_vma flags; ++ struct export_info_data *d; ++ ++ flags = read_unsigned_leb128 (abfd, buf + off, &leblen); ++ off += leblen; ++ ++ fputs (" ", stdout); ++ switch (flags & BFD_MACH_O_EXPORT_SYMBOL_FLAGS_KIND_MASK) ++ { ++ case BFD_MACH_O_EXPORT_SYMBOL_FLAGS_KIND_REGULAR: ++ putchar ('-'); ++ break; ++ case BFD_MACH_O_EXPORT_SYMBOL_FLAGS_KIND_THREAD_LOCAL: ++ putchar ('T'); ++ break; ++ default: ++ putchar ('?'); ++ break; ++ } ++ putchar ((flags & BFD_MACH_O_EXPORT_SYMBOL_FLAGS_WEAK_DEFINITION) ? ++ 'W' : '-'); ++ ++ if (flags & BFD_MACH_O_EXPORT_SYMBOL_FLAGS_REEXPORT) ++ { ++ bfd_vma lib; ++ ++ lib = read_unsigned_leb128 (abfd, buf + off, &leblen); ++ off += leblen; ++ ++ fputs (" [reexport] ", stdout); ++ for (d = base; d != NULL; d = d->next) ++ printf ("%s", d->name); ++ ++ fputs (" (", stdout); ++ if (buf[off] != 0) ++ { ++ fputs ((const char *)buf + off, stdout); ++ putchar (' '); ++ off += strlen ((const char *)buf + off); ++ } ++ printf ("from dylib %u)\n", (unsigned) lib); ++ off++; ++ } ++ else ++ { ++ bfd_vma offset; ++ bfd_vma resolv = 0; ++ ++ offset = read_unsigned_leb128 (abfd, buf + off, &leblen); ++ off += leblen; ++ ++ if (flags & BFD_MACH_O_EXPORT_SYMBOL_FLAGS_STUB_AND_RESOLVER) ++ { ++ resolv = read_unsigned_leb128 (abfd, buf + off, &leblen); ++ off += leblen; ++ } ++ ++ printf (" 0x%08x ", (unsigned) offset); ++ for (d = base; d != NULL; d = d->next) ++ printf ("%s", d->name); ++ if (flags & BFD_MACH_O_EXPORT_SYMBOL_FLAGS_STUB_AND_RESOLVER) ++ printf (" [resolv: 0x%08x]", (unsigned) resolv); ++ printf ("\n"); ++ } ++ } ++ ++ child_count = read_unsigned_leb128 (abfd, buf + off, &leblen); ++ off += leblen; ++ ++ for (i = 0; i < child_count; i++) ++ { ++ struct export_info_data sub_data; ++ bfd_vma sub_off; ++ ++ sub_data.name = buf + off; ++ sub_data.next = NULL; ++ parent->next = &sub_data; ++ ++ off += strlen ((const char *)buf + off) + 1; ++ ++ sub_off = read_unsigned_leb128 (abfd, buf + off, &leblen); ++ off += leblen; ++ ++ dump_dyld_info_export_1 (abfd, buf, len, sub_off, &sub_data, base); ++ } ++} ++ ++static void ++dump_dyld_info_export (bfd *abfd, unsigned char *buf, unsigned int len, ++ ufile_ptr off ATTRIBUTE_UNUSED) ++{ ++ struct export_info_data data; ++ ++ data.name = (const unsigned char *) ""; ++ data.next = NULL; ++ ++ printf (" fl offset sym (Flags: Tls Weak)\n"); ++ dump_dyld_info_export_1 (abfd, buf, len, 0, &data, &data); ++} ++ ++static void ++dump_dyld_info (bfd *abfd, bfd_mach_o_load_command *cmd, ++ bfd_boolean verbose) +{ + bfd_mach_o_dyld_info_command *info = &cmd->command.dyld_info; + -+ printf (" rebase: off: 0x%08x size: %-8u\n", -+ info->rebase_off, info->rebase_size); -+ printf (" bind: off: 0x%08x size: %-8u\n", -+ info->bind_off, info->bind_size); -+ printf (" weak bind: off: 0x%08x size: %-8u\n", -+ info->weak_bind_off, info->weak_bind_size); -+ printf (" lazy bind: off: 0x%08x size: %-8u\n", -+ info->lazy_bind_off, info->lazy_bind_size); -+ printf (" export: off: 0x%08x size: %-8u\n", -+ info->export_off, info->export_size); ++ printf (" rebase: off: 0x%08x size: %-8u (endoff: 0x%08x)\n", ++ info->rebase_off, info->rebase_size, ++ info->rebase_off + info->rebase_size); ++ printf (" bind: off: 0x%08x size: %-8u (endoff: 0x%08x)\n", ++ info->bind_off, info->bind_size, ++ info->bind_off + info->bind_size); ++ printf (" weak bind: off: 0x%08x size: %-8u (endoff: 0x%08x)\n", ++ info->weak_bind_off, info->weak_bind_size, ++ info->weak_bind_off + info->weak_bind_size); ++ printf (" lazy bind: off: 0x%08x size: %-8u (endoff: 0x%08x)\n", ++ info->lazy_bind_off, info->lazy_bind_size, ++ info->lazy_bind_off + info->lazy_bind_size); ++ printf (" export: off: 0x%08x size: %-8u (endoff: 0x%08x)\n", ++ info->export_off, info->export_size, ++ info->export_off + info->export_size); ++ ++ if (!verbose) ++ return; ++ ++ printf (" rebase:\n"); ++ if (!load_and_dump (abfd, info->rebase_off, info->rebase_size, ++ dump_dyld_info_rebase)) ++ non_fatal (_("cannot read rebase dyld info")); ++ ++ printf (" bind:\n"); ++ if (!load_and_dump (abfd, info->bind_off, info->bind_size, ++ dump_dyld_info_bind)) ++ non_fatal (_("cannot read bind dyld info")); ++ ++ printf (" weak bind:\n"); ++ if (!load_and_dump (abfd, info->weak_bind_off, info->weak_bind_size, ++ dump_dyld_info_bind)) ++ non_fatal (_("cannot read weak bind dyld info")); ++ ++ printf (" lazy bind:\n"); ++ if (!load_and_dump (abfd, info->lazy_bind_off, info->lazy_bind_size, ++ dump_dyld_info_bind)) ++ non_fatal (_("cannot read lazy bind dyld info")); ++ ++ printf (" exported symbols:\n"); ++ if (!load_and_dump (abfd, info->export_off, info->export_size, ++ dump_dyld_info_export)) ++ non_fatal (_("cannot read export symbols dyld info")); +} + +static void @@ -99400,19 +100057,161 @@ index 0000000..e62f137 +} + +static void ++dump_function_starts (bfd *abfd, bfd_mach_o_linkedit_command *cmd) ++{ ++ unsigned char *buf = xmalloc (cmd->datasize); ++ unsigned char *end_buf = buf + cmd->datasize; ++ unsigned char *p; ++ bfd_vma addr; ++ ++ if (bfd_seek (abfd, cmd->dataoff, SEEK_SET) != 0 ++ || bfd_bread (buf, cmd->datasize, abfd) != cmd->datasize) ++ { ++ non_fatal (_("cannot read function starts")); ++ free (buf); ++ return; ++ } ++ ++ /* Function starts are delta encoded, starting from the base address. */ ++ addr = bfd_mach_o_get_base_address (abfd); ++ ++ for (p = buf; ;) ++ { ++ bfd_vma delta = 0; ++ unsigned int shift = 0; ++ ++ if (*p == 0 || p == end_buf) ++ break; ++ while (1) ++ { ++ unsigned char b = *p++; ++ ++ delta |= (b & 0x7f) << shift; ++ if ((b & 0x80) == 0) ++ break; ++ if (p == end_buf) ++ { ++ fputs (" [truncated]\n", stdout); ++ break; ++ } ++ shift += 7; ++ } ++ ++ addr += delta; ++ fputs (" ", stdout); ++ bfd_printf_vma (abfd, addr); ++ putchar ('\n'); ++ } ++ free (buf); ++} ++ ++static const bfd_mach_o_xlat_name data_in_code_kind_name[] = ++{ ++ { "data", BFD_MACH_O_DICE_KIND_DATA }, ++ { "1 byte jump table", BFD_MACH_O_DICE_JUMP_TABLES8 }, ++ { "2 bytes jump table", BFD_MACH_O_DICE_JUMP_TABLES16 }, ++ { "4 bytes jump table", BFD_MACH_O_DICE_JUMP_TABLES32 }, ++ { "4 bytes abs jump table", BFD_MACH_O_DICE_ABS_JUMP_TABLES32 }, ++ { NULL, 0 } ++}; ++ ++static void ++dump_data_in_code (bfd *abfd, bfd_mach_o_linkedit_command *cmd) ++{ ++ unsigned char *buf; ++ unsigned char *p; ++ ++ if (cmd->datasize == 0) ++ { ++ printf (" no data_in_code entries\n"); ++ return; ++ } ++ ++ buf = xmalloc (cmd->datasize); ++ if (bfd_seek (abfd, cmd->dataoff, SEEK_SET) != 0 ++ || bfd_bread (buf, cmd->datasize, abfd) != cmd->datasize) ++ { ++ non_fatal (_("cannot read data_in_code")); ++ free (buf); ++ return; ++ } ++ ++ printf (" offset length kind\n"); ++ for (p = buf; p < buf + cmd->datasize; ) ++ { ++ struct mach_o_data_in_code_entry_external *dice; ++ unsigned int offset; ++ unsigned int length; ++ unsigned int kind; ++ ++ dice = (struct mach_o_data_in_code_entry_external *) p; ++ ++ offset = bfd_get_32 (abfd, dice->offset); ++ length = bfd_get_16 (abfd, dice->length); ++ kind = bfd_get_16 (abfd, dice->kind); ++ ++ printf (" 0x%08x 0x%04x 0x%04x %s\n", offset, length, kind, ++ bfd_mach_o_get_name (data_in_code_kind_name, kind)); ++ ++ p += sizeof (*dice); ++ } ++ free (buf); ++} ++ ++static void ++dump_twolevel_hints (bfd *abfd, bfd_mach_o_twolevel_hints_command *cmd) ++{ ++ size_t sz = 4 * cmd->nhints; ++ unsigned char *buf; ++ unsigned char *p; ++ ++ buf = xmalloc (sz); ++ if (bfd_seek (abfd, cmd->offset, SEEK_SET) != 0 ++ || bfd_bread (buf, sz, abfd) != sz) ++ { ++ non_fatal (_("cannot read twolevel hints")); ++ free (buf); ++ return; ++ } ++ ++ for (p = buf; p < buf + sz; p += 4) ++ { ++ unsigned int v; ++ unsigned int isub_image; ++ unsigned int itoc; ++ ++ v = bfd_get_32 (abfd, p); ++ if (bfd_big_endian (abfd)) ++ { ++ isub_image = (v >> 24) & 0xff; ++ itoc = v & 0xffffff; ++ } ++ else ++ { ++ isub_image = v & 0xff; ++ itoc = (v >> 8) & 0xffffff; ++ } ++ ++ printf (" %3u %8u\n", isub_image, itoc); ++ } ++ free (buf); ++} ++ ++static void +dump_load_command (bfd *abfd, bfd_mach_o_load_command *cmd, -+ bfd_boolean verbose) ++ unsigned int idx, bfd_boolean verbose) +{ + bfd_mach_o_data_struct *mdata = bfd_mach_o_get_data (abfd); + const char *cmd_name; + + cmd_name = bfd_mach_o_get_name_or_null + (bfd_mach_o_load_command_name, cmd->type); -+ printf ("Load command "); ++ printf ("Load command #%-2u (size: %3u, offset: %4u): ", ++ idx, cmd->len, cmd->offset); + if (cmd_name == NULL) -+ printf ("0x%02x:", cmd->type); ++ printf ("0x%02x\n", cmd->type); + else -+ printf ("%s:", cmd_name); ++ printf ("%s\n", cmd_name); + + switch (cmd->type) + { @@ -99425,19 +100224,21 @@ index 0000000..e62f137 + bfd_mach_o_uuid_command *uuid = &cmd->command.uuid; + unsigned int j; + ++ printf (" "); + for (j = 0; j < sizeof (uuid->uuid); j ++) + printf (" %02x", uuid->uuid[j]); + putchar ('\n'); + } + break; + case BFD_MACH_O_LC_LOAD_DYLIB: ++ case BFD_MACH_O_LC_LAZY_LOAD_DYLIB: + case BFD_MACH_O_LC_LOAD_WEAK_DYLIB: + case BFD_MACH_O_LC_REEXPORT_DYLIB: + case BFD_MACH_O_LC_ID_DYLIB: + case BFD_MACH_O_LC_LOAD_UPWARD_DYLIB: + { + bfd_mach_o_dylib_command *dylib = &cmd->command.dylib; -+ printf (" %s\n", dylib->name_str); ++ printf (" name: %s\n", dylib->name_str); + printf (" time stamp: 0x%08lx\n", + dylib->timestamp); + printf (" current version: 0x%08lx\n", @@ -99448,13 +100249,15 @@ index 0000000..e62f137 + break; + case BFD_MACH_O_LC_LOAD_DYLINKER: + case BFD_MACH_O_LC_ID_DYLINKER: -+ printf (" %s\n", cmd->command.dylinker.name_str); ++ printf (" %s\n", cmd->command.dylinker.name_str); ++ break; ++ case BFD_MACH_O_LC_DYLD_ENVIRONMENT: ++ printf (" %s\n", cmd->command.dylinker.name_str); + break; + case BFD_MACH_O_LC_SYMTAB: + { + bfd_mach_o_symtab_command *symtab = &cmd->command.symtab; -+ printf ("\n" -+ " symoff: 0x%08x nsyms: %8u (endoff: 0x%08x)\n", ++ printf (" symoff: 0x%08x nsyms: %8u (endoff: 0x%08x)\n", + symtab->symoff, symtab->nsyms, + symtab->symoff + symtab->nsyms + * (mdata->header.version == 2 @@ -99465,14 +100268,13 @@ index 0000000..e62f137 + break; + } + case BFD_MACH_O_LC_DYSYMTAB: -+ putchar ('\n'); + dump_dysymtab (abfd, cmd, verbose); + break; + case BFD_MACH_O_LC_LOADFVMLIB: + case BFD_MACH_O_LC_IDFVMLIB: + { + bfd_mach_o_fvmlib_command *fvmlib = &cmd->command.fvmlib; -+ printf (" %s\n", fvmlib->name_str); ++ printf (" fvmlib: %s\n", fvmlib->name_str); + printf (" minor version: 0x%08x\n", fvmlib->minor_version); + printf (" header address: 0x%08x\n", fvmlib->header_addr); + } @@ -99480,20 +100282,35 @@ index 0000000..e62f137 + case BFD_MACH_O_LC_CODE_SIGNATURE: + case BFD_MACH_O_LC_SEGMENT_SPLIT_INFO: + case BFD_MACH_O_LC_FUNCTION_STARTS: ++ case BFD_MACH_O_LC_DATA_IN_CODE: ++ case BFD_MACH_O_LC_DYLIB_CODE_SIGN_DRS: + { + bfd_mach_o_linkedit_command *linkedit = &cmd->command.linkedit; + printf -+ ("\n" -+ " dataoff: 0x%08lx datasize: 0x%08lx (endoff: 0x%08lx)\n", ++ (" dataoff: 0x%08lx datasize: 0x%08lx (endoff: 0x%08lx)\n", + linkedit->dataoff, linkedit->datasize, + linkedit->dataoff + linkedit->datasize); + -+ if (verbose && cmd->type == BFD_MACH_O_LC_CODE_SIGNATURE) -+ dump_code_signature (abfd, linkedit); -+ else if (verbose && cmd->type == BFD_MACH_O_LC_SEGMENT_SPLIT_INFO) -+ dump_segment_split_info (abfd, linkedit); -+ break; ++ if (verbose) ++ switch (cmd->type) ++ { ++ case BFD_MACH_O_LC_CODE_SIGNATURE: ++ dump_code_signature (abfd, linkedit); ++ break; ++ case BFD_MACH_O_LC_SEGMENT_SPLIT_INFO: ++ dump_segment_split_info (abfd, linkedit); ++ break; ++ case BFD_MACH_O_LC_FUNCTION_STARTS: ++ dump_function_starts (abfd, linkedit); ++ break; ++ case BFD_MACH_O_LC_DATA_IN_CODE: ++ dump_data_in_code (abfd, linkedit); ++ break; ++ default: ++ break; ++ } + } ++ break; + case BFD_MACH_O_LC_SUB_FRAMEWORK: + case BFD_MACH_O_LC_SUB_UMBRELLA: + case BFD_MACH_O_LC_SUB_LIBRARY: @@ -99501,7 +100318,7 @@ index 0000000..e62f137 + case BFD_MACH_O_LC_RPATH: + { + bfd_mach_o_str_command *str = &cmd->command.str; -+ printf (" %s\n", str->str); ++ printf (" %s\n", str->str); + break; + } + case BFD_MACH_O_LC_THREAD: @@ -99512,52 +100329,80 @@ index 0000000..e62f137 + { + bfd_mach_o_encryption_info_command *cryp = + &cmd->command.encryption_info; -+ printf -+ ("\n" -+ " cryptoff: 0x%08x cryptsize: 0x%08x (endoff 0x%08x)" -+ " cryptid: %u\n", -+ cryp->cryptoff, cryp->cryptsize, -+ cryp->cryptoff + cryp->cryptsize, -+ cryp->cryptid); ++ printf (" cryptoff: 0x%08x cryptsize: 0x%08x (endoff 0x%08x)" ++ " cryptid: %u\n", ++ cryp->cryptoff, cryp->cryptsize, ++ cryp->cryptoff + cryp->cryptsize, ++ cryp->cryptid); + } + break; + case BFD_MACH_O_LC_DYLD_INFO: -+ putchar ('\n'); -+ dump_dyld_info (abfd, cmd); ++ dump_dyld_info (abfd, cmd, verbose); + break; + case BFD_MACH_O_LC_VERSION_MIN_MACOSX: + case BFD_MACH_O_LC_VERSION_MIN_IPHONEOS: + { + bfd_mach_o_version_min_command *ver = &cmd->command.version_min; + -+ printf (" %u.%u.%u\n", ver->rel, ver->maj, ver->min); ++ printf (" %u.%u.%u\n", ver->rel, ver->maj, ver->min); + } + break; + case BFD_MACH_O_LC_SOURCE_VERSION: + { + bfd_mach_o_source_version_command *version = + &cmd->command.source_version; -+ printf ("\n" -+ " version a.b.c.d.e: %u.%u.%u.%u.%u\n", ++ printf (" version a.b.c.d.e: %u.%u.%u.%u.%u\n", + version->a, version->b, version->c, version->d, version->e); + break; + } ++ case BFD_MACH_O_LC_PREBOUND_DYLIB: ++ { ++ bfd_mach_o_prebound_dylib_command *pbdy = &cmd->command.prebound_dylib; ++ unsigned char *lm = pbdy->linked_modules; ++ unsigned int j; ++ unsigned int last; ++ ++ printf (" dylib: %s\n", pbdy->name_str); ++ printf (" nmodules: %u\n", pbdy->nmodules); ++ printf (" linked modules (at %u): ", ++ pbdy->linked_modules_offset - cmd->offset); ++ last = pbdy->nmodules > 32 ? 32 : pbdy->nmodules; ++ for (j = 0; j < last; j++) ++ printf ("%u", (lm[j >> 3] >> (j & 7)) & 1); ++ if (last < pbdy->nmodules) ++ printf ("..."); ++ putchar ('\n'); ++ break; ++ } ++ case BFD_MACH_O_LC_PREBIND_CKSUM: ++ { ++ bfd_mach_o_prebind_cksum_command *cksum = &cmd->command.prebind_cksum; ++ printf (" 0x%08x\n", cksum->cksum); ++ break; ++ } ++ case BFD_MACH_O_LC_TWOLEVEL_HINTS: ++ { ++ bfd_mach_o_twolevel_hints_command *hints = ++ &cmd->command.twolevel_hints; ++ ++ printf (" table offset: 0x%08x nbr hints: %u\n", ++ hints->offset, hints->nhints); ++ if (verbose) ++ dump_twolevel_hints (abfd, hints); ++ break; ++ } + case BFD_MACH_O_LC_MAIN: + { + bfd_mach_o_main_command *entry = &cmd->command.main; -+ printf ("\n" -+ " entry offset: "); -+ printf_vma (entry->entryoff); ++ printf (" entry offset: "); ++ printf_uint64 (entry->entryoff); + printf ("\n" + " stack size: "); -+ printf_vma (entry->stacksize); ++ printf_uint64 (entry->stacksize); + printf ("\n"); + break; + } + default: -+ putchar ('\n'); -+ printf (" offset: 0x%08lx\n", (unsigned long)cmd->offset); -+ printf (" size: 0x%08lx\n", (unsigned long)cmd->len); + break; + } + putchar ('\n'); @@ -99567,16 +100412,457 @@ index 0000000..e62f137 +dump_load_commands (bfd *abfd, unsigned int cmd32, unsigned int cmd64) +{ + bfd_mach_o_data_struct *mdata = bfd_mach_o_get_data (abfd); ++ bfd_mach_o_load_command *cmd; + unsigned int i; + -+ for (i = 0; i < mdata->header.ncmds; i++) ++ for (cmd = mdata->first_command, i = 0; cmd != NULL; cmd = cmd->next, i++) + { -+ bfd_mach_o_load_command *cmd = &mdata->commands[i]; -+ + if (cmd32 == 0) -+ dump_load_command (abfd, cmd, FALSE); ++ dump_load_command (abfd, cmd, i, FALSE); + else if (cmd->type == cmd32 || cmd->type == cmd64) -+ dump_load_command (abfd, cmd, TRUE); ++ dump_load_command (abfd, cmd, i, TRUE); ++ } ++} ++ ++static const char * const unwind_x86_64_regs[] = ++ {"", "rbx", "r12", "r13", "r14", "r15", "rbp", "???" }; ++ ++static const char * const unwind_x86_regs[] = ++ {"", "ebx", "ecx", "edx", "edi", "edi", "ebp", "???" }; ++ ++/* Dump x86 or x86-64 compact unwind encoding. Works for both architecture, ++ as the encoding is the same (but not register names). */ ++ ++static void ++dump_unwind_encoding_x86 (unsigned int encoding, unsigned int sz, ++ const char * const regs_name[]) ++{ ++ unsigned int mode; ++ ++ mode = encoding & MACH_O_UNWIND_X86_64_MODE_MASK; ++ switch (mode) ++ { ++ case MACH_O_UNWIND_X86_64_MODE_RBP_FRAME: ++ { ++ unsigned int regs; ++ char pfx = sz == 8 ? 'R' : 'E'; ++ ++ regs = encoding & MACH_O_UNWIND_X86_64_RBP_FRAME_REGSITERS; ++ printf (" %cSP frame", pfx); ++ if (regs != 0) ++ { ++ unsigned int offset; ++ int i; ++ ++ offset = (encoding & MACH_O_UNWIND_X86_64_RBP_FRAME_OFFSET) >> 16; ++ printf (" at %cBP-%u:", pfx, offset * sz); ++ for (i = 0; i < 5; i++) ++ { ++ unsigned int reg = (regs >> (i * 3)) & 0x7; ++ if (reg != MACH_O_UNWIND_X86_64_REG_NONE) ++ printf (" %s", regs_name[reg]); ++ } ++ } ++ } ++ break; ++ case MACH_O_UNWIND_X86_64_MODE_STACK_IMMD: ++ case MACH_O_UNWIND_X86_64_MODE_STACK_IND: ++ { ++ unsigned int stack_size; ++ unsigned int reg_count; ++ unsigned int reg_perm; ++ unsigned int regs[6]; ++ int i, j; ++ ++ printf (" frameless"); ++ stack_size = ++ (encoding & MACH_O_UNWIND_X86_64_FRAMELESS_STACK_SIZE) >> 16; ++ reg_count = ++ (encoding & MACH_O_UNWIND_X86_64_FRAMELESS_REG_COUNT) >> 10; ++ reg_perm = encoding & MACH_O_UNWIND_X86_64_FRAMELESS_REG_PERMUTATION; ++ ++ if (mode == MACH_O_UNWIND_X86_64_MODE_STACK_IMMD) ++ printf (" size: 0x%03x", stack_size * sz); ++ else ++ { ++ unsigned int stack_adj; ++ ++ stack_adj = ++ (encoding & MACH_O_UNWIND_X86_64_FRAMELESS_STACK_ADJUST) >> 13; ++ printf (" size at 0x%03x + 0x%02x", stack_size, stack_adj * sz); ++ } ++ /* Registers are coded using arithmetic compression: the register ++ is indexed in range 0-6, the second in range 0-5, the third in ++ range 0-4, etc. Already used registers are removed in next ++ ranges. */ ++#define DO_PERM(R, NUM) R = reg_perm / NUM; reg_perm -= R * NUM ++ switch (reg_count) ++ { ++ case 6: ++ case 5: ++ DO_PERM (regs[0], 120); ++ DO_PERM (regs[1], 24); ++ DO_PERM (regs[2], 6); ++ DO_PERM (regs[3], 2); ++ DO_PERM (regs[4], 1); ++ regs[5] = 0; /* Not used if reg_count = 5. */ ++ break; ++ case 4: ++ DO_PERM (regs[0], 60); ++ DO_PERM (regs[1], 12); ++ DO_PERM (regs[2], 3); ++ DO_PERM (regs[3], 1); ++ break; ++ case 3: ++ DO_PERM (regs[0], 20); ++ DO_PERM (regs[1], 4); ++ DO_PERM (regs[2], 1); ++ break; ++ case 2: ++ DO_PERM (regs[0], 5); ++ DO_PERM (regs[1], 1); ++ break; ++ case 1: ++ DO_PERM (regs[0], 1); ++ break; ++ case 0: ++ break; ++ default: ++ printf (" [bad reg count]"); ++ return; ++ } ++#undef DO_PERM ++ /* Renumber. */ ++ for (i = reg_count - 1; i >= 0; i--) ++ { ++ unsigned int inc = 1; ++ for (j = 0; j < i; j++) ++ if (regs[i] >= regs[j]) ++ inc++; ++ regs[i] += inc; ++ } ++ /* Display. */ ++ for (i = 0; i < (int) reg_count; i++) ++ printf (" %s", regs_name[regs[i]]); ++ } ++ break; ++ case MACH_O_UNWIND_X86_64_MODE_DWARF: ++ printf (" Dwarf offset: 0x%06x", ++ encoding & MACH_O_UNWIND_X86_64_DWARF_SECTION_OFFSET); ++ break; ++ default: ++ printf (" [unhandled mode]"); ++ break; ++ } ++} ++ ++static void ++dump_unwind_encoding (bfd_mach_o_data_struct *mdata, unsigned int encoding) ++{ ++ printf ("0x%08x", encoding); ++ if (encoding == 0) ++ return; ++ ++ switch (mdata->header.cputype) ++ { ++ case BFD_MACH_O_CPU_TYPE_X86_64: ++ dump_unwind_encoding_x86 (encoding, 8, unwind_x86_64_regs); ++ break; ++ case BFD_MACH_O_CPU_TYPE_I386: ++ dump_unwind_encoding_x86 (encoding, 4, unwind_x86_regs); ++ break; ++ default: ++ printf (" [unhandled cpu]"); ++ break; ++ } ++ if (encoding & MACH_O_UNWIND_HAS_LSDA) ++ printf (" LSDA"); ++ if (encoding & MACH_O_UNWIND_PERSONALITY_MASK) ++ printf (" PERS(%u)", ++ ((encoding & MACH_O_UNWIND_PERSONALITY_MASK) ++ >> MACH_O_UNWIND_PERSONALITY_SHIFT)); ++} ++ ++static void ++dump_obj_compact_unwind (bfd *abfd, ++ const unsigned char *content, bfd_size_type size) ++{ ++ bfd_mach_o_data_struct *mdata = bfd_mach_o_get_data (abfd); ++ int is_64 = mdata->header.version == 2; ++ const unsigned char *p; ++ ++ printf ("Compact unwind info:\n"); ++ printf (" start length personality lsda\n"); ++ ++ if (is_64) ++ { ++ struct mach_o_compact_unwind_64 *e = ++ (struct mach_o_compact_unwind_64 *) content; ++ ++ for (p = content; p < content + size; p += sizeof (*e)) ++ { ++ e = (struct mach_o_compact_unwind_64 *) p; ++ ++ putchar (' '); ++ printf_uint64 (bfd_get_64 (abfd, e->start)); ++ printf (" %08lx", bfd_get_32 (abfd, e->length)); ++ putchar (' '); ++ printf_uint64 (bfd_get_64 (abfd, e->personality)); ++ putchar (' '); ++ printf_uint64 (bfd_get_64 (abfd, e->lsda)); ++ putchar ('\n'); ++ ++ printf (" encoding: "); ++ dump_unwind_encoding (mdata, bfd_get_32 (abfd, e->encoding)); ++ putchar ('\n'); ++ } ++ } ++ else ++ { ++ printf ("unhandled\n"); ++ } ++} ++ ++static void ++dump_exe_compact_unwind (bfd *abfd, ++ const unsigned char *content, bfd_size_type size) ++{ ++ bfd_mach_o_data_struct *mdata = bfd_mach_o_get_data (abfd); ++ struct mach_o_unwind_info_header *hdr; ++ unsigned int version; ++ unsigned int encodings_offset; ++ unsigned int encodings_count; ++ unsigned int personality_offset; ++ unsigned int personality_count; ++ unsigned int index_offset; ++ unsigned int index_count; ++ struct mach_o_unwind_index_entry *index_entry; ++ unsigned int i; ++ ++ /* The header. */ ++ printf ("Compact unwind info:\n"); ++ ++ hdr = (struct mach_o_unwind_info_header *) content; ++ if (size < sizeof (*hdr)) ++ { ++ printf (" truncated!\n"); ++ return; ++ } ++ ++ version = bfd_get_32 (abfd, hdr->version); ++ if (version != MACH_O_UNWIND_SECTION_VERSION) ++ { ++ printf (" unknown version: %u\n", version); ++ return; ++ } ++ encodings_offset = bfd_get_32 (abfd, hdr->encodings_array_offset); ++ encodings_count = bfd_get_32 (abfd, hdr->encodings_array_count); ++ personality_offset = bfd_get_32 (abfd, hdr->personality_array_offset); ++ personality_count = bfd_get_32 (abfd, hdr->personality_array_count); ++ index_offset = bfd_get_32 (abfd, hdr->index_offset); ++ index_count = bfd_get_32 (abfd, hdr->index_count); ++ printf (" %u encodings, %u personalities, %u level-1 indexes:\n", ++ encodings_count, personality_count, index_count); ++ ++ /* Personality. */ ++ if (personality_count > 0) ++ { ++ const unsigned char *pers = content + personality_offset; ++ ++ printf (" personalities\n"); ++ for (i = 0; i < personality_count; i++) ++ printf (" %u: 0x%08x\n", i, ++ (unsigned) bfd_get_32 (abfd, pers + 4 * i)); ++ } ++ ++ /* Level-1 index. */ ++ printf (" idx function level2 off lsda off\n"); ++ ++ index_entry = (struct mach_o_unwind_index_entry *) (content + index_offset); ++ for (i = 0; i < index_count; i++) ++ { ++ unsigned int func_offset; ++ unsigned int level2_offset; ++ unsigned int lsda_offset; ++ ++ func_offset = bfd_get_32 (abfd, index_entry->function_offset); ++ level2_offset = bfd_get_32 (abfd, index_entry->second_level_offset); ++ lsda_offset = bfd_get_32 (abfd, index_entry->lsda_index_offset); ++ printf (" %3u 0x%08x 0x%08x 0x%08x\n", ++ i, func_offset, level2_offset, lsda_offset); ++ index_entry++; ++ } ++ ++ /* Level-1 index. */ ++ index_entry = (struct mach_o_unwind_index_entry *) (content + index_offset); ++ for (i = 0; i < index_count; i++) ++ { ++ unsigned int func_offset; ++ unsigned int level2_offset; ++ const unsigned char *level2; ++ unsigned int kind; ++ ++ func_offset = bfd_get_32 (abfd, index_entry->function_offset); ++ level2_offset = bfd_get_32 (abfd, index_entry->second_level_offset); ++ ++ /* No level-2 for this index (should be the last index). */ ++ if (level2_offset == 0) ++ continue; ++ ++ level2 = content + level2_offset; ++ kind = bfd_get_32 (abfd, level2); ++ switch (kind) ++ { ++ case MACH_O_UNWIND_SECOND_LEVEL_COMPRESSED: ++ { ++ struct mach_o_unwind_compressed_second_level_page_header *l2; ++ unsigned int entry_offset; ++ unsigned int entry_count; ++ unsigned int l2_encodings_offset; ++ unsigned int l2_encodings_count; ++ const unsigned char *en; ++ unsigned int j; ++ ++ l2 = (struct mach_o_unwind_compressed_second_level_page_header *) ++ level2; ++ entry_offset = bfd_get_16 (abfd, l2->entry_page_offset); ++ entry_count = bfd_get_16 (abfd, l2->entry_count); ++ l2_encodings_offset = bfd_get_16 (abfd, l2->encodings_offset); ++ l2_encodings_count = bfd_get_16 (abfd, l2->encodings_count); ++ ++ printf (" index %2u: compressed second level: " ++ "%u entries, %u encodings (at 0x%08x)\n", ++ i, entry_count, l2_encodings_count, l2_encodings_offset); ++ printf (" # function eidx encoding\n"); ++ ++ en = level2 + entry_offset; ++ for (j = 0; j < entry_count; j++) ++ { ++ unsigned int entry; ++ unsigned int en_func; ++ unsigned int enc_idx; ++ unsigned int encoding; ++ const unsigned char *enc_addr; ++ ++ entry = bfd_get_32 (abfd, en); ++ en_func = ++ MACH_O_UNWIND_INFO_COMPRESSED_ENTRY_FUNC_OFFSET (entry); ++ enc_idx = ++ MACH_O_UNWIND_INFO_COMPRESSED_ENTRY_ENCODING_INDEX (entry); ++ if (enc_idx < encodings_count) ++ enc_addr = content + encodings_offset ++ + 4 * enc_idx; ++ else ++ enc_addr = level2 + l2_encodings_offset ++ + 4 * (enc_idx - encodings_count); ++ encoding = bfd_get_32 (abfd, enc_addr); ++ ++ printf (" %4u 0x%08x [%3u] ", j, ++ func_offset + en_func, enc_idx); ++ dump_unwind_encoding (mdata, encoding); ++ putchar ('\n'); ++ ++ en += 4; ++ } ++ } ++ break; ++ ++ case MACH_O_UNWIND_SECOND_LEVEL_REGULAR: ++ { ++ struct mach_o_unwind_regular_second_level_page_header *l2; ++ struct mach_o_unwind_regular_second_level_entry *en; ++ unsigned int entry_offset; ++ unsigned int entry_count; ++ unsigned int j; ++ ++ l2 = (struct mach_o_unwind_regular_second_level_page_header *) ++ level2; ++ ++ entry_offset = bfd_get_16 (abfd, l2->entry_page_offset); ++ entry_count = bfd_get_16 (abfd, l2->entry_count); ++ printf (" index %2u: regular level 2 at 0x%04x, %u entries\n", ++ i, entry_offset, entry_count); ++ printf (" # function encoding\n"); ++ ++ en = (struct mach_o_unwind_regular_second_level_entry *) ++ (level2 + entry_offset); ++ for (j = 0; j < entry_count; j++) ++ { ++ unsigned int en_func; ++ unsigned int encoding; ++ ++ en_func = bfd_get_32 (abfd, en->function_offset); ++ encoding = bfd_get_32 (abfd, en->encoding); ++ printf (" %-4u 0x%08x ", j, en_func); ++ dump_unwind_encoding (mdata, encoding); ++ putchar ('\n'); ++ en++; ++ } ++ } ++ break; ++ ++ default: ++ printf (" index %2u: unhandled second level format (%u)\n", ++ i, kind); ++ break; ++ } ++ ++ { ++ struct mach_o_unwind_lsda_index_entry *lsda; ++ unsigned int lsda_offset; ++ unsigned int next_lsda_offset; ++ unsigned int nbr_lsda; ++ unsigned int j; ++ ++ lsda_offset = bfd_get_32 (abfd, index_entry->lsda_index_offset); ++ next_lsda_offset = bfd_get_32 (abfd, index_entry[1].lsda_index_offset); ++ lsda = (struct mach_o_unwind_lsda_index_entry *) ++ (content + lsda_offset); ++ nbr_lsda = (next_lsda_offset - lsda_offset) / sizeof (*lsda); ++ for (j = 0; j < nbr_lsda; j++) ++ { ++ printf (" lsda %3u: function 0x%08x lsda 0x%08x\n", ++ j, (unsigned int) bfd_get_32 (abfd, lsda->function_offset), ++ (unsigned int) bfd_get_32 (abfd, lsda->lsda_offset)); ++ lsda++; ++ } ++ } ++ index_entry++; ++ } ++} ++ ++static void ++dump_section_content (bfd *abfd, ++ const char *segname, const char *sectname, ++ void (*dump)(bfd*, const unsigned char*, bfd_size_type)) ++{ ++ bfd_mach_o_data_struct *mdata = bfd_mach_o_get_data (abfd); ++ bfd_mach_o_load_command *cmd; ++ ++ for (cmd = mdata->first_command; cmd != NULL; cmd = cmd->next) ++ { ++ if (cmd->type == BFD_MACH_O_LC_SEGMENT ++ || cmd->type == BFD_MACH_O_LC_SEGMENT_64) ++ { ++ bfd_mach_o_segment_command *seg = &cmd->command.segment; ++ bfd_mach_o_section *sec; ++ for (sec = seg->sect_head; sec != NULL; sec = sec->next) ++ if (strcmp (sec->segname, segname) == 0 ++ && strcmp (sec->sectname, sectname) == 0) ++ { ++ bfd_size_type size; ++ asection *bfdsec = sec->bfdsection; ++ unsigned char *content; ++ ++ size = bfd_get_section_size (bfdsec); ++ content = (unsigned char *) xmalloc (size); ++ bfd_get_section_contents (abfd, bfdsec, content, 0, size); ++ ++ (*dump)(abfd, content, size); ++ ++ free (content); ++ } ++ } + } +} + @@ -99599,6 +100885,21 @@ index 0000000..e62f137 + dump_load_commands (abfd, BFD_MACH_O_LC_CODE_SIGNATURE, 0); + if (options[OPT_SEG_SPLIT_INFO].selected) + dump_load_commands (abfd, BFD_MACH_O_LC_SEGMENT_SPLIT_INFO, 0); ++ if (options[OPT_FUNCTION_STARTS].selected) ++ dump_load_commands (abfd, BFD_MACH_O_LC_FUNCTION_STARTS, 0); ++ if (options[OPT_DATA_IN_CODE].selected) ++ dump_load_commands (abfd, BFD_MACH_O_LC_DATA_IN_CODE, 0); ++ if (options[OPT_TWOLEVEL_HINTS].selected) ++ dump_load_commands (abfd, BFD_MACH_O_LC_TWOLEVEL_HINTS, 0); ++ if (options[OPT_COMPACT_UNWIND].selected) ++ { ++ dump_section_content (abfd, "__LD", "__compact_unwind", ++ dump_obj_compact_unwind); ++ dump_section_content (abfd, "__TEXT", "__unwind_info", ++ dump_exe_compact_unwind); ++ } ++ if (options[OPT_DYLD_INFO].selected) ++ dump_load_commands (abfd, BFD_MACH_O_LC_DYLD_INFO, 0); +} + +/* Vector for Mach-O. */ @@ -99612,12 +100913,12 @@ index 0000000..e62f137 + }; diff --git a/binutils/od-xcoff.c b/binutils/od-xcoff.c new file mode 100644 -index 0000000..223e192 +index 0000000..ddd5af6 --- /dev/null +++ b/binutils/od-xcoff.c @@ -0,0 +1,1842 @@ +/* od-xcoff.c -- dump information about an xcoff object file. -+ Copyright 2011-2013 Free Software Foundation, Inc. ++ Copyright (C) 2011-2014 Free Software Foundation, Inc. + Written by Tristan Gingold, Adacore. + + This file is part of GNU Binutils. @@ -101460,13 +102761,13 @@ index 0000000..223e192 + }; diff --git a/binutils/po/Make-in b/binutils/po/Make-in new file mode 100644 -index 0000000..f8f6525 +index 0000000..dafc461 --- /dev/null +++ b/binutils/po/Make-in @@ -0,0 +1,258 @@ +# Makefile for program source directory in GNU NLS utilities package. +# Copyright (C) 1995, 1996, 1997 by Ulrich Drepper -+# Copyright 2003, 2006, 2007, 2009 Free Software Foundation, Inc. ++# Copyright (C) 2003-2014 Free Software Foundation, Inc. +# +# This file may be copied and used freely without restrictions. It can +# be used in projects which are not available under the GNU Public License @@ -109763,10 +111064,10 @@ index 0000000..127468f +msgstr "%s: предупреждение: неизвеÑтен размер за полето '%s' на Ñтруктурата" diff --git a/binutils/po/binutils.pot b/binutils/po/binutils.pot new file mode 100644 -index 0000000..0d08397 +index 0000000..84551c5 --- /dev/null +++ b/binutils/po/binutils.pot -@@ -0,0 +1,7975 @@ +@@ -0,0 +1,8865 @@ +# SOME DESCRIPTIVE TITLE. +# Copyright (C) YEAR THE PACKAGE'S COPYRIGHT HOLDER +# This file is distributed under the same license as the PACKAGE package. @@ -109777,7 +111078,7 @@ index 0000000..0d08397 +msgstr "" +"Project-Id-Version: PACKAGE VERSION\n" +"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n" -+"POT-Creation-Date: 2011-10-25 11:20+0100\n" ++"POT-Creation-Date: 2014-02-10 09:42+1030\n" +"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" +"Last-Translator: FULL NAME \n" +"Language-Team: LANGUAGE \n" @@ -109822,10 +111123,10 @@ index 0000000..0d08397 +"\n" +msgstr "" + -+#: addr2line.c:101 ar.c:304 ar.c:333 coffdump.c:471 dlltool.c:3938 -+#: dllwrap.c:524 elfedit.c:653 nlmconv.c:1114 objcopy.c:576 objcopy.c:611 -+#: readelf.c:3214 size.c:99 srconv.c:1743 strings.c:667 sysdump.c:653 -+#: windmc.c:228 windres.c:695 ++#: addr2line.c:101 ar.c:332 ar.c:369 coffdump.c:471 dlltool.c:3969 ++#: dllwrap.c:518 elfedit.c:651 nlmconv.c:1113 objcopy.c:606 objcopy.c:656 ++#: readelf.c:3705 size.c:99 srconv.c:1744 strings.c:653 sysdump.c:653 ++#: windmc.c:228 windres.c:687 +#, c-format +msgid "Report bugs to %s\n" +msgstr "" @@ -109835,7 +111136,7 @@ index 0000000..0d08397 +#. file name pair that is about to be printed below. Eg: +#. +#. foo at 123:bar.c -+#: addr2line.c:276 ++#: addr2line.c:297 +#, c-format +msgid " at " +msgstr "" @@ -109846,221 +111147,250 @@ index 0000000..0d08397 +#. by the next iteration of the while loop. Eg: +#. +#. 123:bar.c (inlined by) 456:main.c -+#: addr2line.c:308 ++#: addr2line.c:338 +#, c-format +msgid " (inlined by) " +msgstr "" + -+#: addr2line.c:341 ++#: addr2line.c:371 +#, c-format +msgid "%s: cannot get addresses from archive" +msgstr "" + -+#: addr2line.c:358 ++#: addr2line.c:388 +#, c-format +msgid "%s: cannot find section %s" +msgstr "" + -+#: addr2line.c:427 nm.c:1570 objdump.c:3423 ++#: addr2line.c:457 nm.c:1572 objdump.c:3479 +#, c-format +msgid "unknown demangling style `%s'" +msgstr "" + -+#: ar.c:238 ++#: ar.c:253 +#, c-format +msgid "no entry %s in archive\n" +msgstr "" + -+#: ar.c:254 ++#: ar.c:267 +#, c-format +msgid "" +"Usage: %s [emulation options] [-]{dmpqrstx}[abcDfilMNoPsSTuvV] [--plugin " +"] [member-name] [count] archive-file file...\n" +msgstr "" + -+#: ar.c:260 ++#: ar.c:273 +#, c-format +msgid "" +"Usage: %s [emulation options] [-]{dmpqrstx}[abcDfilMNoPsSTuvV] [member-name] " +"[count] archive-file file...\n" +msgstr "" + -+#: ar.c:266 ++#: ar.c:281 +#, c-format +msgid " %s -M [ - read options from \n" +msgstr "" + -+#: ar.c:293 ++#: ar.c:321 +#, c-format +msgid " --target=BFDNAME - specify the target object format as BFDNAME\n" +msgstr "" + -+#: ar.c:295 ++#: ar.c:323 +#, c-format +msgid " optional:\n" +msgstr "" + -+#: ar.c:296 ++#: ar.c:324 +#, c-format +msgid " --plugin

- load the specified plugin\n" +msgstr "" + -+#: ar.c:317 ++#: ar.c:345 +#, c-format +msgid "Usage: %s [options] archive\n" +msgstr "" + -+#: ar.c:318 ++#: ar.c:346 +#, c-format +msgid " Generate an index to speed access to archives\n" +msgstr "" + -+#: ar.c:319 ++#: ar.c:347 +#, c-format +msgid "" +" The options are:\n" +" @ Read options from \n" +msgstr "" + -+#: ar.c:322 ++#: ar.c:350 +#, c-format +msgid " --plugin Load the specified plugin\n" +msgstr "" + -+#: ar.c:325 ++#: ar.c:354 ++#, c-format ++msgid "" ++" -D Use zero for symbol map timestamp (default)\n" ++" -U Use an actual symbol map timestamp\n" ++msgstr "" ++ ++#: ar.c:358 ++#, c-format ++msgid "" ++" -D Use zero for symbol map timestamp\n" ++" -U Use actual symbol map timestamp (default)\n" ++msgstr "" ++ ++#: ar.c:361 +#, c-format +msgid "" +" -t Update the archive's symbol map timestamp\n" @@ -110068,74 +111398,88 @@ index 0000000..0d08397 +" -v --version Print version information\n" +msgstr "" + -+#: ar.c:449 ++#: ar.c:485 +msgid "two different operation options specified" +msgstr "" + -+#: ar.c:538 nm.c:1643 ++#: ar.c:577 ar.c:638 nm.c:1654 +#, c-format +msgid "sorry - this program has been built without plugin support\n" +msgstr "" + -+#: ar.c:693 ++#: ar.c:761 +msgid "no operation specified" +msgstr "" + -+#: ar.c:696 ++#: ar.c:764 +msgid "`u' is only meaningful with the `r' option." +msgstr "" + -+#: ar.c:699 ++#: ar.c:767 +msgid "`u' is not meaningful with the `D' option." +msgstr "" + -+#: ar.c:707 ++#: ar.c:770 ++msgid "`u' modifier ignored since `D' is the default (see `U')" ++msgstr "" ++ ++#: ar.c:781 +msgid "`N' is only meaningful with the `x' and `d' options." +msgstr "" + -+#: ar.c:710 ++#: ar.c:784 +msgid "Value for `N' must be positive." +msgstr "" + -+#: ar.c:724 ++#: ar.c:798 +msgid "`x' cannot be used on thin archives." +msgstr "" + -+#: ar.c:771 ++#: ar.c:845 +#, c-format +msgid "internal error -- this option not implemented" +msgstr "" + -+#: ar.c:840 ++#: ar.c:914 +#, c-format +msgid "creating %s" +msgstr "" + -+#: ar.c:889 ar.c:943 ar.c:1272 objcopy.c:2080 ++#: ar.c:945 ++#, c-format ++msgid "Cannot convert existing library %s to thin format" ++msgstr "" ++ ++#: ar.c:951 ++#, c-format ++msgid "Cannot convert existing thin library %s to normal format" ++msgstr "" ++ ++#: ar.c:983 ar.c:1037 ar.c:1366 objcopy.c:2294 +#, c-format +msgid "internal stat error on %s" +msgstr "" + -+#: ar.c:908 ar.c:976 ++#: ar.c:1002 ar.c:1070 +#, c-format +msgid "%s is not a valid archive" +msgstr "" + -+#: ar.c:1034 ++#: ar.c:1128 +msgid "could not create temporary file whilst writing archive" +msgstr "" + -+#: ar.c:1177 ++#: ar.c:1271 +#, c-format +msgid "No member named `%s'\n" +msgstr "" + -+#: ar.c:1227 ++#: ar.c:1321 +#, c-format +msgid "no entry %s in archive %s!" +msgstr "" + -+#: ar.c:1366 ++#: ar.c:1460 +#, c-format +msgid "%s: no archive map to update" +msgstr "" @@ -110170,27 +111514,27 @@ index 0000000..0d08397 +msgid "%s: no output archive specified yet\n" +msgstr "" + -+#: arsup.c:250 arsup.c:288 arsup.c:330 arsup.c:350 arsup.c:416 ++#: arsup.c:250 arsup.c:288 arsup.c:330 arsup.c:353 arsup.c:419 +#, c-format +msgid "%s: no open output archive\n" +msgstr "" + -+#: arsup.c:261 arsup.c:371 arsup.c:397 ++#: arsup.c:261 arsup.c:374 arsup.c:400 +#, c-format +msgid "%s: can't open file %s\n" +msgstr "" + -+#: arsup.c:315 arsup.c:393 arsup.c:474 ++#: arsup.c:315 arsup.c:396 arsup.c:477 +#, c-format +msgid "%s: can't find module file %s\n" +msgstr "" + -+#: arsup.c:425 ++#: arsup.c:428 +#, c-format +msgid "Current open archive is %s\n" +msgstr "" + -+#: arsup.c:449 ++#: arsup.c:452 +#, c-format +msgid "%s: no open archive\n" +msgstr "" @@ -110206,81 +111550,81 @@ index 0000000..0d08397 +msgid " emulation options: \n" +msgstr "" + -+#: bucomm.c:163 ++#: bucomm.c:164 +#, c-format +msgid "can't set BFD default target to `%s': %s" +msgstr "" + -+#: bucomm.c:175 ++#: bucomm.c:176 +#, c-format +msgid "%s: Matching formats:" +msgstr "" + -+#: bucomm.c:190 ++#: bucomm.c:191 +#, c-format +msgid "Supported targets:" +msgstr "" + -+#: bucomm.c:192 ++#: bucomm.c:193 +#, c-format +msgid "%s: supported targets:" +msgstr "" + -+#: bucomm.c:210 ++#: bucomm.c:211 +#, c-format +msgid "Supported architectures:" +msgstr "" + -+#: bucomm.c:212 ++#: bucomm.c:213 +#, c-format +msgid "%s: supported architectures:" +msgstr "" + -+#: bucomm.c:228 ++#: bucomm.c:229 +msgid "big endian" +msgstr "" + -+#: bucomm.c:229 ++#: bucomm.c:230 +msgid "little endian" +msgstr "" + -+#: bucomm.c:230 ++#: bucomm.c:231 +msgid "endianness unknown" +msgstr "" + -+#: bucomm.c:251 ++#: bucomm.c:252 +#, c-format +msgid "" +"%s\n" +" (header %s, data %s)\n" +msgstr "" + -+#: bucomm.c:407 ++#: bucomm.c:408 +#, c-format +msgid "BFD header file version %s\n" +msgstr "" + -+#: bucomm.c:559 ++#: bucomm.c:562 +#, c-format +msgid "%s: bad number: %s" +msgstr "" + -+#: bucomm.c:576 strings.c:409 ++#: bucomm.c:579 strings.c:408 +#, c-format +msgid "'%s': No such file" +msgstr "" + -+#: bucomm.c:578 strings.c:411 ++#: bucomm.c:581 strings.c:410 +#, c-format +msgid "Warning: could not locate '%s'. reason: %s" +msgstr "" + -+#: bucomm.c:582 ++#: bucomm.c:585 +#, c-format +msgid "Warning: '%s' is not an ordinary file" +msgstr "" + -+#: bucomm.c:584 ++#: bucomm.c:587 +#, c-format +msgid "Warning: '%s' has negative size, probably it is too large" +msgstr "" @@ -110390,7 +111734,7 @@ index 0000000..0d08397 +msgid "Symbol %s, tag %d, number %d" +msgstr "" + -+#: coffdump.c:345 readelf.c:12215 readelf.c:12289 ++#: coffdump.c:345 readelf.c:13103 readelf.c:13177 +#, c-format +msgid "Type" +msgstr "" @@ -110459,881 +111803,881 @@ index 0000000..0d08397 +"\n" +msgstr "" + -+#: coffdump.c:533 srconv.c:1833 sysdump.c:710 ++#: coffdump.c:533 srconv.c:1834 sysdump.c:710 +msgid "no input file specified" +msgstr "" + -+#: cxxfilt.c:119 nm.c:269 objdump.c:281 ++#: cxxfilt.c:119 nm.c:270 objdump.c:281 +#, c-format +msgid "Report bugs to %s.\n" +msgstr "" + -+#: debug.c:648 ++#: debug.c:647 +msgid "debug_add_to_current_namespace: no current file" +msgstr "" + -+#: debug.c:727 ++#: debug.c:726 +msgid "debug_start_source: no debug_set_filename call" +msgstr "" + -+#: debug.c:781 ++#: debug.c:780 +msgid "debug_record_function: no debug_set_filename call" +msgstr "" + -+#: debug.c:833 ++#: debug.c:832 +msgid "debug_record_parameter: no current function" +msgstr "" + -+#: debug.c:865 ++#: debug.c:864 +msgid "debug_end_function: no current function" +msgstr "" + -+#: debug.c:871 ++#: debug.c:870 +msgid "debug_end_function: some blocks were not closed" +msgstr "" + -+#: debug.c:899 ++#: debug.c:898 +msgid "debug_start_block: no current block" +msgstr "" + -+#: debug.c:935 ++#: debug.c:934 +msgid "debug_end_block: no current block" +msgstr "" + -+#: debug.c:942 ++#: debug.c:941 +msgid "debug_end_block: attempt to close top level block" +msgstr "" + -+#: debug.c:965 ++#: debug.c:964 +msgid "debug_record_line: no current unit" +msgstr "" + +#. FIXME -+#: debug.c:1018 ++#: debug.c:1017 +msgid "debug_start_common_block: not implemented" +msgstr "" + +#. FIXME -+#: debug.c:1029 ++#: debug.c:1028 +msgid "debug_end_common_block: not implemented" +msgstr "" + +#. FIXME. -+#: debug.c:1113 ++#: debug.c:1112 +msgid "debug_record_label: not implemented" +msgstr "" + -+#: debug.c:1135 ++#: debug.c:1134 +msgid "debug_record_variable: no current file" +msgstr "" + -+#: debug.c:1663 ++#: debug.c:1662 +msgid "debug_make_undefined_type: unsupported kind" +msgstr "" + -+#: debug.c:1840 ++#: debug.c:1839 +msgid "debug_name_type: no current file" +msgstr "" + -+#: debug.c:1885 ++#: debug.c:1884 +msgid "debug_tag_type: no current file" +msgstr "" + -+#: debug.c:1893 ++#: debug.c:1892 +msgid "debug_tag_type: extra tag attempted" +msgstr "" + -+#: debug.c:1930 ++#: debug.c:1929 +#, c-format +msgid "Warning: changing type size from %d to %d\n" +msgstr "" + -+#: debug.c:1952 ++#: debug.c:1951 +msgid "debug_find_named_type: no current compilation unit" +msgstr "" + -+#: debug.c:2055 ++#: debug.c:2054 +#, c-format +msgid "debug_get_real_type: circular debug information for %s\n" +msgstr "" + -+#: debug.c:2482 ++#: debug.c:2481 +msgid "debug_write_type: illegal type encountered" +msgstr "" + -+#: dlltool.c:902 dlltool.c:928 dlltool.c:959 ++#: dlltool.c:918 dlltool.c:944 dlltool.c:975 +#, c-format +msgid "Internal error: Unknown machine type: %d" +msgstr "" + -+#: dlltool.c:1000 ++#: dlltool.c:1016 +#, c-format +msgid "Can't open def file: %s" +msgstr "" + -+#: dlltool.c:1005 ++#: dlltool.c:1021 +#, c-format +msgid "Processing def file: %s" +msgstr "" + -+#: dlltool.c:1009 ++#: dlltool.c:1025 +msgid "Processed def file" +msgstr "" + -+#: dlltool.c:1033 ++#: dlltool.c:1049 +#, c-format +msgid "Syntax error in def file %s:%d" +msgstr "" + -+#: dlltool.c:1070 ++#: dlltool.c:1086 +#, c-format +msgid "%s: Path components stripped from image name, '%s'." +msgstr "" + -+#: dlltool.c:1088 ++#: dlltool.c:1104 +#, c-format +msgid "NAME: %s base: %x" +msgstr "" + -+#: dlltool.c:1091 dlltool.c:1112 ++#: dlltool.c:1107 dlltool.c:1128 +msgid "Can't have LIBRARY and NAME" +msgstr "" + -+#: dlltool.c:1109 ++#: dlltool.c:1125 +#, c-format +msgid "LIBRARY: %s base: %x" +msgstr "" + -+#: dlltool.c:1266 ++#: dlltool.c:1282 +#, c-format +msgid "VERSION %d.%d\n" +msgstr "" + -+#: dlltool.c:1314 ++#: dlltool.c:1330 +#, c-format +msgid "run: %s %s" +msgstr "" + -+#: dlltool.c:1354 resrc.c:293 ++#: dlltool.c:1370 resrc.c:288 +#, c-format +msgid "wait: %s" +msgstr "" + -+#: dlltool.c:1359 dllwrap.c:422 resrc.c:298 ++#: dlltool.c:1375 dllwrap.c:416 resrc.c:293 +#, c-format +msgid "subprocess got fatal signal %d" +msgstr "" + -+#: dlltool.c:1365 dllwrap.c:429 resrc.c:305 ++#: dlltool.c:1381 dllwrap.c:423 resrc.c:300 +#, c-format +msgid "%s exited with status %d" +msgstr "" + -+#: dlltool.c:1396 ++#: dlltool.c:1412 +#, c-format +msgid "Sucking in info from %s section in %s" +msgstr "" + -+#: dlltool.c:1536 ++#: dlltool.c:1552 +#, c-format +msgid "Excluding symbol: %s" +msgstr "" + -+#: dlltool.c:1625 dlltool.c:1636 nm.c:1012 nm.c:1023 ++#: dlltool.c:1641 dlltool.c:1652 nm.c:1006 nm.c:1016 nm.c:1025 +#, c-format +msgid "%s: no symbols" +msgstr "" + +#. FIXME: we ought to read in and block out the base relocations. -+#: dlltool.c:1662 ++#: dlltool.c:1678 +#, c-format +msgid "Done reading %s" +msgstr "" + -+#: dlltool.c:1672 ++#: dlltool.c:1688 +#, c-format +msgid "Unable to open object file: %s: %s" +msgstr "" + -+#: dlltool.c:1675 ++#: dlltool.c:1691 +#, c-format +msgid "Scanning object file %s" +msgstr "" + -+#: dlltool.c:1690 ++#: dlltool.c:1708 +#, c-format +msgid "Cannot produce mcore-elf dll from archive file: %s" +msgstr "" + -+#: dlltool.c:1792 ++#: dlltool.c:1810 +msgid "Adding exports to output file" +msgstr "" + -+#: dlltool.c:1844 ++#: dlltool.c:1862 +msgid "Added exports to output file" +msgstr "" + -+#: dlltool.c:1986 ++#: dlltool.c:2004 +#, c-format +msgid "Generating export file: %s" +msgstr "" + -+#: dlltool.c:1991 ++#: dlltool.c:2009 +#, c-format +msgid "Unable to open temporary assembler file: %s" +msgstr "" + -+#: dlltool.c:1994 ++#: dlltool.c:2012 +#, c-format +msgid "Opened temporary file: %s" +msgstr "" + -+#: dlltool.c:2171 ++#: dlltool.c:2189 +msgid "failed to read the number of entries from base file" +msgstr "" + -+#: dlltool.c:2219 ++#: dlltool.c:2237 +msgid "Generated exports file" +msgstr "" + -+#: dlltool.c:2428 ++#: dlltool.c:2447 +#, c-format +msgid "bfd_open failed open stub file: %s: %s" +msgstr "" + -+#: dlltool.c:2432 ++#: dlltool.c:2451 +#, c-format +msgid "Creating stub file: %s" +msgstr "" + -+#: dlltool.c:2894 ++#: dlltool.c:2922 +#, c-format +msgid "bfd_open failed reopen stub file: %s: %s" +msgstr "" + -+#: dlltool.c:2908 dlltool.c:2984 ++#: dlltool.c:2936 dlltool.c:3012 +#, c-format +msgid "failed to open temporary head file: %s" +msgstr "" + -+#: dlltool.c:2970 dlltool.c:3050 ++#: dlltool.c:2998 dlltool.c:3081 +#, c-format +msgid "failed to open temporary head file: %s: %s" +msgstr "" + -+#: dlltool.c:3064 ++#: dlltool.c:3095 +#, c-format +msgid "failed to open temporary tail file: %s" +msgstr "" + -+#: dlltool.c:3121 ++#: dlltool.c:3152 +#, c-format +msgid "failed to open temporary tail file: %s: %s" +msgstr "" + -+#: dlltool.c:3143 ++#: dlltool.c:3174 +#, c-format +msgid "Can't create .lib file: %s: %s" +msgstr "" + -+#: dlltool.c:3147 ++#: dlltool.c:3178 +#, c-format +msgid "Creating library file: %s" +msgstr "" + -+#: dlltool.c:3239 dlltool.c:3245 ++#: dlltool.c:3270 dlltool.c:3276 +#, c-format +msgid "cannot delete %s: %s" +msgstr "" + -+#: dlltool.c:3250 ++#: dlltool.c:3281 +msgid "Created lib file" +msgstr "" + -+#: dlltool.c:3462 ++#: dlltool.c:3493 +#, c-format +msgid "Can't open .lib file: %s: %s" +msgstr "" + -+#: dlltool.c:3470 dlltool.c:3492 ++#: dlltool.c:3501 dlltool.c:3523 +#, c-format +msgid "%s is not a library" +msgstr "" + -+#: dlltool.c:3510 ++#: dlltool.c:3541 +#, c-format +msgid "Import library `%s' specifies two or more dlls" +msgstr "" + -+#: dlltool.c:3521 ++#: dlltool.c:3552 +#, c-format +msgid "Unable to determine dll name for `%s' (not an import library?)" +msgstr "" + -+#: dlltool.c:3745 ++#: dlltool.c:3776 +#, c-format +msgid "Warning, ignoring duplicate EXPORT %s %d,%d" +msgstr "" + -+#: dlltool.c:3751 ++#: dlltool.c:3782 +#, c-format +msgid "Error, duplicate EXPORT with ordinals: %s" +msgstr "" + -+#: dlltool.c:3856 ++#: dlltool.c:3887 +msgid "Processing definitions" +msgstr "" + -+#: dlltool.c:3888 ++#: dlltool.c:3919 +msgid "Processed definitions" +msgstr "" + +#. xgetext:c-format -+#: dlltool.c:3895 dllwrap.c:483 ++#: dlltool.c:3926 dllwrap.c:477 +#, c-format +msgid "Usage %s \n" +msgstr "" + +#. xgetext:c-format -+#: dlltool.c:3897 ++#: dlltool.c:3928 +#, c-format +msgid "" +" -m --machine Create as DLL for . [default: %s]\n" +msgstr "" + -+#: dlltool.c:3898 ++#: dlltool.c:3929 +#, c-format +msgid "" +" possible : arm[_interwork], i386, mcore[-elf]{-le|-be}, " +"ppc, thumb\n" +msgstr "" + -+#: dlltool.c:3899 ++#: dlltool.c:3930 +#, c-format +msgid " -e --output-exp Generate an export file.\n" +msgstr "" + -+#: dlltool.c:3900 ++#: dlltool.c:3931 +#, c-format +msgid " -l --output-lib Generate an interface library.\n" +msgstr "" + -+#: dlltool.c:3901 ++#: dlltool.c:3932 +#, c-format +msgid " -y --output-delaylib Create a delay-import library.\n" +msgstr "" + -+#: dlltool.c:3902 ++#: dlltool.c:3933 +#, c-format +msgid " -a --add-indirect Add dll indirects to export file.\n" +msgstr "" + -+#: dlltool.c:3903 ++#: dlltool.c:3934 +#, c-format +msgid "" +" -D --dllname Name of input dll to put into interface lib.\n" +msgstr "" + -+#: dlltool.c:3904 ++#: dlltool.c:3935 +#, c-format +msgid " -d --input-def Name of .def file to be read in.\n" +msgstr "" + -+#: dlltool.c:3905 ++#: dlltool.c:3936 +#, c-format +msgid " -z --output-def Name of .def file to be created.\n" +msgstr "" + -+#: dlltool.c:3906 ++#: dlltool.c:3937 +#, c-format +msgid " --export-all-symbols Export all symbols to .def\n" +msgstr "" + -+#: dlltool.c:3907 ++#: dlltool.c:3938 +#, c-format +msgid " --no-export-all-symbols Only export listed symbols\n" +msgstr "" + -+#: dlltool.c:3908 ++#: dlltool.c:3939 +#, c-format +msgid " --exclude-symbols Don't export \n" +msgstr "" + -+#: dlltool.c:3909 ++#: dlltool.c:3940 +#, c-format +msgid " --no-default-excludes Clear default exclude symbols\n" +msgstr "" + -+#: dlltool.c:3910 ++#: dlltool.c:3941 +#, c-format +msgid " -b --base-file Read linker generated base file.\n" +msgstr "" + -+#: dlltool.c:3911 ++#: dlltool.c:3942 +#, c-format +msgid " -x --no-idata4 Don't generate idata$4 section.\n" +msgstr "" + -+#: dlltool.c:3912 ++#: dlltool.c:3943 +#, c-format +msgid " -c --no-idata5 Don't generate idata$5 section.\n" +msgstr "" + -+#: dlltool.c:3913 ++#: dlltool.c:3944 +#, c-format +msgid "" +" --use-nul-prefixed-import-tables Use zero prefixed idata$4 and idata" +"$5.\n" +msgstr "" + -+#: dlltool.c:3914 ++#: dlltool.c:3945 +#, c-format +msgid "" +" -U --add-underscore Add underscores to all symbols in interface " +"library.\n" +msgstr "" + -+#: dlltool.c:3915 ++#: dlltool.c:3946 +#, c-format +msgid "" +" --add-stdcall-underscore Add underscores to stdcall symbols in " +"interface library.\n" +msgstr "" + -+#: dlltool.c:3916 ++#: dlltool.c:3947 +#, c-format +msgid "" +" --no-leading-underscore All symbols shouldn't be prefixed by an " +"underscore.\n" +msgstr "" + -+#: dlltool.c:3917 ++#: dlltool.c:3948 +#, c-format +msgid "" +" --leading-underscore All symbols should be prefixed by an " +"underscore.\n" +msgstr "" + -+#: dlltool.c:3918 ++#: dlltool.c:3949 +#, c-format +msgid " -k --kill-at Kill @ from exported names.\n" +msgstr "" + -+#: dlltool.c:3919 ++#: dlltool.c:3950 +#, c-format +msgid " -A --add-stdcall-alias Add aliases without @.\n" +msgstr "" + -+#: dlltool.c:3920 ++#: dlltool.c:3951 +#, c-format +msgid " -p --ext-prefix-alias Add aliases with .\n" +msgstr "" + -+#: dlltool.c:3921 ++#: dlltool.c:3952 +#, c-format +msgid " -S --as Use for assembler.\n" +msgstr "" + -+#: dlltool.c:3922 ++#: dlltool.c:3953 +#, c-format +msgid " -f --as-flags Pass to the assembler.\n" +msgstr "" + -+#: dlltool.c:3923 ++#: dlltool.c:3954 +#, c-format +msgid "" +" -C --compat-implib Create backward compatible import library.\n" +msgstr "" + -+#: dlltool.c:3924 ++#: dlltool.c:3955 +#, c-format +msgid "" +" -n --no-delete Keep temp files (repeat for extra " +"preservation).\n" +msgstr "" + -+#: dlltool.c:3925 ++#: dlltool.c:3956 +#, c-format +msgid "" +" -t --temp-prefix Use to construct temp file names.\n" +msgstr "" + -+#: dlltool.c:3926 ++#: dlltool.c:3957 +#, c-format +msgid "" +" -I --identify Report the name of the DLL associated with " +".\n" +msgstr "" + -+#: dlltool.c:3927 ++#: dlltool.c:3958 +#, c-format +msgid "" +" --identify-strict Causes --identify to report error when multiple " +"DLLs.\n" +msgstr "" + -+#: dlltool.c:3928 ++#: dlltool.c:3959 +#, c-format +msgid " -v --verbose Be verbose.\n" +msgstr "" + -+#: dlltool.c:3929 ++#: dlltool.c:3960 +#, c-format +msgid " -V --version Display the program version.\n" +msgstr "" + -+#: dlltool.c:3930 ++#: dlltool.c:3961 +#, c-format +msgid " -h --help Display this information.\n" +msgstr "" + -+#: dlltool.c:3931 ++#: dlltool.c:3962 +#, c-format +msgid " @ Read options from .\n" +msgstr "" + -+#: dlltool.c:3933 ++#: dlltool.c:3964 +#, c-format +msgid "" +" -M --mcore-elf Process mcore-elf object files into .\n" +msgstr "" + -+#: dlltool.c:3934 ++#: dlltool.c:3965 +#, c-format +msgid " -L --linker Use as the linker.\n" +msgstr "" + -+#: dlltool.c:3935 ++#: dlltool.c:3966 +#, c-format +msgid " -F --linker-flags Pass to the linker.\n" +msgstr "" + -+#: dlltool.c:4082 ++#: dlltool.c:4113 +#, c-format +msgid "Path components stripped from dllname, '%s'." +msgstr "" + -+#: dlltool.c:4130 ++#: dlltool.c:4161 +#, c-format +msgid "Unable to open base-file: %s" +msgstr "" + -+#: dlltool.c:4165 ++#: dlltool.c:4196 +#, c-format +msgid "Machine '%s' not supported" +msgstr "" + -+#: dlltool.c:4245 ++#: dlltool.c:4276 +#, c-format +msgid "Warning, machine type (%d) not supported for delayimport." +msgstr "" + -+#: dlltool.c:4313 dllwrap.c:213 ++#: dlltool.c:4344 dllwrap.c:207 +#, c-format +msgid "Tried file: %s" +msgstr "" + -+#: dlltool.c:4320 dllwrap.c:220 ++#: dlltool.c:4351 dllwrap.c:214 +#, c-format +msgid "Using file: %s" +msgstr "" + -+#: dllwrap.c:303 ++#: dllwrap.c:297 +#, c-format +msgid "Keeping temporary base file %s" +msgstr "" + -+#: dllwrap.c:305 ++#: dllwrap.c:299 +#, c-format +msgid "Deleting temporary base file %s" +msgstr "" + -+#: dllwrap.c:319 ++#: dllwrap.c:313 +#, c-format +msgid "Keeping temporary exp file %s" +msgstr "" + -+#: dllwrap.c:321 ++#: dllwrap.c:315 +#, c-format +msgid "Deleting temporary exp file %s" +msgstr "" + -+#: dllwrap.c:334 ++#: dllwrap.c:328 +#, c-format +msgid "Keeping temporary def file %s" +msgstr "" + -+#: dllwrap.c:336 ++#: dllwrap.c:330 +#, c-format +msgid "Deleting temporary def file %s" +msgstr "" + -+#: dllwrap.c:417 ++#: dllwrap.c:411 +#, c-format +msgid "pwait returns: %s" +msgstr "" + -+#: dllwrap.c:484 ++#: dllwrap.c:478 +#, c-format +msgid " Generic options:\n" +msgstr "" + -+#: dllwrap.c:485 ++#: dllwrap.c:479 +#, c-format +msgid " @ Read options from \n" +msgstr "" + -+#: dllwrap.c:486 ++#: dllwrap.c:480 +#, c-format +msgid " --quiet, -q Work quietly\n" +msgstr "" + -+#: dllwrap.c:487 ++#: dllwrap.c:481 +#, c-format +msgid " --verbose, -v Verbose\n" +msgstr "" + -+#: dllwrap.c:488 ++#: dllwrap.c:482 +#, c-format +msgid " --version Print dllwrap version\n" +msgstr "" + -+#: dllwrap.c:489 ++#: dllwrap.c:483 +#, c-format +msgid " --implib Synonym for --output-lib\n" +msgstr "" + -+#: dllwrap.c:490 ++#: dllwrap.c:484 +#, c-format +msgid " Options for %s:\n" +msgstr "" + -+#: dllwrap.c:491 ++#: dllwrap.c:485 +#, c-format +msgid " --driver-name Defaults to \"gcc\"\n" +msgstr "" + -+#: dllwrap.c:492 ++#: dllwrap.c:486 +#, c-format +msgid " --driver-flags Override default ld flags\n" +msgstr "" + -+#: dllwrap.c:493 ++#: dllwrap.c:487 +#, c-format +msgid " --dlltool-name Defaults to \"dlltool\"\n" +msgstr "" + -+#: dllwrap.c:494 ++#: dllwrap.c:488 +#, c-format +msgid " --entry Specify alternate DLL entry point\n" +msgstr "" + -+#: dllwrap.c:495 ++#: dllwrap.c:489 +#, c-format +msgid " --image-base Specify image base address\n" +msgstr "" + -+#: dllwrap.c:496 ++#: dllwrap.c:490 +#, c-format +msgid " --target i386-cygwin32 or i386-mingw32\n" +msgstr "" + -+#: dllwrap.c:497 ++#: dllwrap.c:491 +#, c-format +msgid " --dry-run Show what needs to be run\n" +msgstr "" + -+#: dllwrap.c:498 ++#: dllwrap.c:492 +#, c-format +msgid " --mno-cygwin Create Mingw DLL\n" +msgstr "" + -+#: dllwrap.c:499 ++#: dllwrap.c:493 +#, c-format +msgid " Options passed to DLLTOOL:\n" +msgstr "" + -+#: dllwrap.c:500 ++#: dllwrap.c:494 +#, c-format +msgid " --machine \n" +msgstr "" + -+#: dllwrap.c:501 ++#: dllwrap.c:495 +#, c-format +msgid " --output-exp Generate export file.\n" +msgstr "" + -+#: dllwrap.c:502 ++#: dllwrap.c:496 +#, c-format +msgid " --output-lib Generate input library.\n" +msgstr "" + -+#: dllwrap.c:503 ++#: dllwrap.c:497 +#, c-format +msgid " --add-indirect Add dll indirects to export file.\n" +msgstr "" + -+#: dllwrap.c:504 ++#: dllwrap.c:498 +#, c-format +msgid " --dllname Name of input dll to put into output lib.\n" +msgstr "" + -+#: dllwrap.c:505 ++#: dllwrap.c:499 +#, c-format +msgid " --def Name input .def file\n" +msgstr "" + -+#: dllwrap.c:506 ++#: dllwrap.c:500 +#, c-format +msgid " --output-def Name output .def file\n" +msgstr "" + -+#: dllwrap.c:507 ++#: dllwrap.c:501 +#, c-format +msgid " --export-all-symbols Export all symbols to .def\n" +msgstr "" + -+#: dllwrap.c:508 ++#: dllwrap.c:502 +#, c-format +msgid " --no-export-all-symbols Only export .drectve symbols\n" +msgstr "" + -+#: dllwrap.c:509 ++#: dllwrap.c:503 +#, c-format +msgid " --exclude-symbols Exclude from .def\n" +msgstr "" + -+#: dllwrap.c:510 ++#: dllwrap.c:504 +#, c-format +msgid " --no-default-excludes Zap default exclude symbols\n" +msgstr "" + -+#: dllwrap.c:511 ++#: dllwrap.c:505 +#, c-format +msgid " --base-file Read linker generated base file\n" +msgstr "" + -+#: dllwrap.c:512 ++#: dllwrap.c:506 +#, c-format +msgid " --no-idata4 Don't generate idata$4 section\n" +msgstr "" + -+#: dllwrap.c:513 ++#: dllwrap.c:507 +#, c-format +msgid " --no-idata5 Don't generate idata$5 section\n" +msgstr "" + -+#: dllwrap.c:514 ++#: dllwrap.c:508 +#, c-format +msgid " -U Add underscores to .lib\n" +msgstr "" + -+#: dllwrap.c:515 ++#: dllwrap.c:509 +#, c-format +msgid " -k Kill @ from exported names\n" +msgstr "" + -+#: dllwrap.c:516 ++#: dllwrap.c:510 +#, c-format +msgid " --add-stdcall-alias Add aliases without @\n" +msgstr "" + -+#: dllwrap.c:517 ++#: dllwrap.c:511 +#, c-format +msgid " --as Use for assembler\n" +msgstr "" + -+#: dllwrap.c:518 ++#: dllwrap.c:512 +#, c-format +msgid " --nodelete Keep temp files.\n" +msgstr "" + -+#: dllwrap.c:519 ++#: dllwrap.c:513 +#, c-format +msgid " --no-leading-underscore Entrypoint without underscore\n" +msgstr "" + -+#: dllwrap.c:520 ++#: dllwrap.c:514 +#, c-format +msgid " --leading-underscore Entrypoint with underscore.\n" +msgstr "" + -+#: dllwrap.c:521 ++#: dllwrap.c:515 +#, c-format +msgid " Rest are passed unmodified to the language driver\n" +msgstr "" + -+#: dllwrap.c:805 ++#: dllwrap.c:799 +msgid "Must provide at least one of -o or --dllname options" +msgstr "" + -+#: dllwrap.c:834 ++#: dllwrap.c:828 +msgid "" +"no export definition file provided.\n" +"Creating one, but that may not be what you want" +msgstr "" + -+#: dllwrap.c:1023 ++#: dllwrap.c:1017 +#, c-format +msgid "DLLTOOL name : %s\n" +msgstr "" + -+#: dllwrap.c:1024 ++#: dllwrap.c:1018 +#, c-format +msgid "DLLTOOL options : %s\n" +msgstr "" + -+#: dllwrap.c:1025 ++#: dllwrap.c:1019 +#, c-format +msgid "DRIVER name : %s\n" +msgstr "" + -+#: dllwrap.c:1026 ++#: dllwrap.c:1020 +#, c-format +msgid "DRIVER options : %s\n" +msgstr "" + -+#: dwarf.c:132 -+msgid "Wrong size in print_dwarf_vma" -+msgstr "" -+ -+#: dwarf.c:256 dwarf.c:3027 ++#: dwarf.c:406 dwarf.c:3215 +msgid "badly formed extended line op encountered!\n" +msgstr "" + -+#: dwarf.c:263 ++#: dwarf.c:413 +#, c-format +msgid " Extended opcode %d: " +msgstr "" + -+#: dwarf.c:268 ++#: dwarf.c:418 +#, c-format +msgid "" +"End of Sequence\n" +"\n" +msgstr "" + -+#: dwarf.c:274 ++#: dwarf.c:424 +#, c-format +msgid "set Address to 0x%s\n" +msgstr "" + -+#: dwarf.c:280 ++#: dwarf.c:430 +#, c-format -+msgid " define new File Table entry\n" ++msgid "define new File Table entry\n" +msgstr "" + -+#: dwarf.c:281 dwarf.c:2555 ++#: dwarf.c:431 dwarf.c:2777 +#, c-format +msgid " Entry\tDir\tTime\tSize\tName\n" +msgstr "" + -+#: dwarf.c:295 ++#: dwarf.c:445 ++msgid "DW_LNE_define_file: Bad opcode length\n" ++msgstr "" ++ ++#: dwarf.c:449 +#, c-format +msgid "set Discriminator to %s\n" +msgstr "" + -+#: dwarf.c:370 ++#: dwarf.c:524 +#, c-format +msgid " UNKNOWN DW_LNE_HP_SFC opcode (%u)\n" +msgstr "" @@ -111342,1240 +112686,1537 @@ index 0000000..0d08397 +#. the limited range of the unsigned char data type used +#. for op_code. +#. && op_code <= DW_LNE_hi_user -+#: dwarf.c:387 ++#: dwarf.c:541 +#, c-format +msgid "user defined: " +msgstr "" + -+#: dwarf.c:389 ++#: dwarf.c:543 +#, c-format +msgid "UNKNOWN: " +msgstr "" + -+#: dwarf.c:390 ++#: dwarf.c:544 +#, c-format +msgid "length %d [" +msgstr "" + -+#: dwarf.c:407 ++#: dwarf.c:561 dwarf.c:599 +msgid "" +msgstr "" + -+#: dwarf.c:413 ++#: dwarf.c:565 +#, c-format +msgid "DW_FORM_strp offset too big: %s\n" +msgstr "" + -+#: dwarf.c:415 ++#: dwarf.c:567 +msgid "" +msgstr "" + -+#: dwarf.c:655 ++#: dwarf.c:585 ++msgid "" ++msgstr "" ++ ++#: dwarf.c:586 ++msgid "" ++msgstr "" ++ ++#: dwarf.c:592 ++#, c-format ++msgid "DW_FORM_GNU_str_index offset too big: %s\n" ++msgstr "" ++ ++#: dwarf.c:594 ++msgid "" ++msgstr "" ++ ++#: dwarf.c:598 ++msgid "" ++msgstr "" ++ ++#: dwarf.c:605 ++#, c-format ++msgid "DW_FORM_GNU_str_index indirect offset too big: %s\n" ++msgstr "" ++ ++#: dwarf.c:607 ++msgid "" ++msgstr "" ++ ++#: dwarf.c:619 ++msgid "" ++msgstr "" ++ ++#: dwarf.c:623 ++#, c-format ++msgid "Offset into section %s too big: %s\n" ++msgstr "" ++ ++#. Report the missing single zero which ends the section. ++#: dwarf.c:788 ++msgid ".debug_abbrev section not zero terminated\n" ++msgstr "" ++ ++#: dwarf.c:802 +#, c-format +msgid "Unknown TAG value: %lx" +msgstr "" + -+#: dwarf.c:696 ++#: dwarf.c:822 +#, c-format +msgid "Unknown FORM value: %lx" +msgstr "" + -+#: dwarf.c:705 ++#: dwarf.c:836 +#, c-format +msgid " %s byte block: " +msgstr "" + -+#: dwarf.c:1050 ++#: dwarf.c:1188 +#, c-format +msgid "(DW_OP_call_ref in frame info)" +msgstr "" + -+#: dwarf.c:1075 ++#: dwarf.c:1210 +#, c-format +msgid "size: %s " +msgstr "" + -+#: dwarf.c:1078 ++#: dwarf.c:1213 +#, c-format +msgid "offset: %s " +msgstr "" + -+#: dwarf.c:1098 ++#: dwarf.c:1233 +#, c-format +msgid "DW_OP_GNU_push_tls_address or DW_OP_HP_unknown" +msgstr "" + -+#: dwarf.c:1122 ++#: dwarf.c:1257 +#, c-format +msgid "(DW_OP_GNU_implicit_pointer in frame info)" +msgstr "" + -+#: dwarf.c:1234 ++#: dwarf.c:1377 +#, c-format +msgid "(User defined location op)" +msgstr "" + -+#: dwarf.c:1236 ++#: dwarf.c:1379 +#, c-format +msgid "(Unknown location op)" +msgstr "" + -+#: dwarf.c:1283 ++#: dwarf.c:1473 ++msgid "corrupt attribute\n" ++msgstr "" ++ ++#: dwarf.c:1488 +msgid "Internal error: DWARF version is not 2, 3 or 4.\n" +msgstr "" + -+#: dwarf.c:1389 ++#: dwarf.c:1614 +msgid "DW_FORM_data8 is unsupported when sizeof (dwarf_vma) != 8\n" +msgstr "" + -+#: dwarf.c:1439 ++#: dwarf.c:1665 +#, c-format +msgid " (indirect string, offset: 0x%s): %s" +msgstr "" + -+#: dwarf.c:1464 ++#: dwarf.c:1676 +#, c-format -+msgid "Unrecognized form: %lu\n" -+msgstr "" -+ -+#: dwarf.c:1557 -+#, c-format -+msgid "(not inlined)" -+msgstr "" -+ -+#: dwarf.c:1560 -+#, c-format -+msgid "(inlined)" -+msgstr "" -+ -+#: dwarf.c:1563 -+#, c-format -+msgid "(declared as inline but ignored)" -+msgstr "" -+ -+#: dwarf.c:1566 -+#, c-format -+msgid "(declared as inline and inlined)" -+msgstr "" -+ -+#: dwarf.c:1569 -+#, c-format -+msgid " (Unknown inline attribute value: %s)" -+msgstr "" -+ -+#: dwarf.c:1608 -+#, c-format -+msgid "(implementation defined: %s)" -+msgstr "" -+ -+#: dwarf.c:1611 -+#, c-format -+msgid "(Unknown: %s)" -+msgstr "" -+ -+#: dwarf.c:1649 -+#, c-format -+msgid "(user defined type)" -+msgstr "" -+ -+#: dwarf.c:1651 -+#, c-format -+msgid "(unknown type)" -+msgstr "" -+ -+#: dwarf.c:1663 -+#, c-format -+msgid "(unknown accessibility)" -+msgstr "" -+ -+#: dwarf.c:1674 -+#, c-format -+msgid "(unknown visibility)" ++msgid " (indexed string: 0x%s): %s" +msgstr "" + +#: dwarf.c:1684 +#, c-format ++msgid " (alt indirect string, offset: 0x%s)" ++msgstr "" ++ ++#: dwarf.c:1707 ++#, c-format ++msgid " (addr_index: 0x%s): %s" ++msgstr "" ++ ++#: dwarf.c:1713 ++#, c-format ++msgid "Unrecognized form: %lu\n" ++msgstr "" ++ ++#: dwarf.c:1815 ++#, c-format ++msgid "(not inlined)" ++msgstr "" ++ ++#: dwarf.c:1818 ++#, c-format ++msgid "(inlined)" ++msgstr "" ++ ++#: dwarf.c:1821 ++#, c-format ++msgid "(declared as inline but ignored)" ++msgstr "" ++ ++#: dwarf.c:1824 ++#, c-format ++msgid "(declared as inline and inlined)" ++msgstr "" ++ ++#: dwarf.c:1827 ++#, c-format ++msgid " (Unknown inline attribute value: %s)" ++msgstr "" ++ ++#: dwarf.c:1869 ++#, c-format ++msgid "(implementation defined: %s)" ++msgstr "" ++ ++#: dwarf.c:1872 ++#, c-format ++msgid "(Unknown: %s)" ++msgstr "" ++ ++#: dwarf.c:1911 ++#, c-format ++msgid "(user defined type)" ++msgstr "" ++ ++#: dwarf.c:1913 ++#, c-format ++msgid "(unknown type)" ++msgstr "" ++ ++#: dwarf.c:1926 ++#, c-format ++msgid "(unknown accessibility)" ++msgstr "" ++ ++#: dwarf.c:1938 ++#, c-format ++msgid "(unknown visibility)" ++msgstr "" ++ ++#: dwarf.c:1949 ++#, c-format +msgid "(unknown virtuality)" +msgstr "" + -+#: dwarf.c:1695 ++#: dwarf.c:1961 +#, c-format +msgid "(unknown case)" +msgstr "" + -+#: dwarf.c:1708 ++#: dwarf.c:1975 +#, c-format +msgid "(user defined)" +msgstr "" + -+#: dwarf.c:1710 ++#: dwarf.c:1977 +#, c-format +msgid "(unknown convention)" +msgstr "" + -+#: dwarf.c:1717 ++#: dwarf.c:1985 +#, c-format +msgid "(undefined)" +msgstr "" + -+#: dwarf.c:1740 ++#: dwarf.c:2008 +#, c-format -+msgid "(location list)" ++msgid " (location list)" +msgstr "" + -+#: dwarf.c:1761 dwarf.c:4045 ++#: dwarf.c:2029 dwarf.c:4209 dwarf.c:4335 +#, c-format +msgid " [without DW_AT_frame_base]" +msgstr "" + -+#: dwarf.c:1777 ++#: dwarf.c:2046 +#, c-format +msgid "" +"Offset %s used as value for DW_AT_import attribute of DIE at offset %lx is " +"too big.\n" +msgstr "" + -+#: dwarf.c:1787 ++#: dwarf.c:2056 +#, c-format -+msgid "[Abbrev Number: %ld" ++msgid "\t[Abbrev Number: %ld" +msgstr "" + -+#: dwarf.c:1978 ++#: dwarf.c:2098 +#, c-format +msgid "Unknown AT value: %lx" +msgstr "" + -+#: dwarf.c:2049 ++#: dwarf.c:2171 +#, c-format +msgid "Reserved length value (0x%s) found in section %s\n" +msgstr "" + -+#: dwarf.c:2061 ++#: dwarf.c:2183 +#, c-format +msgid "Corrupt unit length (0x%s) found in section %s\n" +msgstr "" + -+#: dwarf.c:2069 ++#: dwarf.c:2191 +#, c-format +msgid "No comp units in %s section ?" +msgstr "" + -+#: dwarf.c:2078 ++#: dwarf.c:2200 +#, c-format +msgid "Not enough memory for a debug info array of %u entries" +msgstr "" + -+#: dwarf.c:2087 dwarf.c:3296 dwarf.c:3390 dwarf.c:3551 dwarf.c:3779 -+#: dwarf.c:3911 dwarf.c:4081 dwarf.c:4150 dwarf.c:4354 ++#: dwarf.c:2209 dwarf.c:3544 dwarf.c:3669 dwarf.c:3833 dwarf.c:4086 ++#: dwarf.c:4444 dwarf.c:4528 dwarf.c:4597 dwarf.c:4738 dwarf.c:4884 ++#: dwarf.c:6321 +#, c-format +msgid "" +"Contents of the %s section:\n" +"\n" +msgstr "" + -+#: dwarf.c:2095 ++#: dwarf.c:2221 +#, c-format +msgid "Unable to locate %s section!\n" +msgstr "" + -+#: dwarf.c:2176 ++#: dwarf.c:2309 +#, c-format +msgid " Compilation Unit @ offset 0x%s:\n" +msgstr "" + -+#: dwarf.c:2178 ++#: dwarf.c:2311 +#, c-format +msgid " Length: 0x%s (%s)\n" +msgstr "" + -+#: dwarf.c:2181 ++#: dwarf.c:2314 +#, c-format +msgid " Version: %d\n" +msgstr "" + -+#: dwarf.c:2182 ++#: dwarf.c:2315 +#, c-format -+msgid " Abbrev Offset: %s\n" ++msgid " Abbrev Offset: 0x%s\n" +msgstr "" + -+#: dwarf.c:2184 ++#: dwarf.c:2317 +#, c-format +msgid " Pointer Size: %d\n" +msgstr "" + -+#: dwarf.c:2188 ++#: dwarf.c:2322 +#, c-format -+msgid " Signature: " ++msgid " Signature: 0x%s\n" +msgstr "" + -+#: dwarf.c:2192 ++#: dwarf.c:2325 +#, c-format +msgid " Type Offset: 0x%s\n" +msgstr "" + -+#: dwarf.c:2200 ++#: dwarf.c:2333 ++#, c-format ++msgid " Section contributions:\n" ++msgstr "" ++ ++#: dwarf.c:2334 ++#, c-format ++msgid " .debug_abbrev.dwo: 0x%s 0x%s\n" ++msgstr "" ++ ++#: dwarf.c:2337 ++#, c-format ++msgid " .debug_line.dwo: 0x%s 0x%s\n" ++msgstr "" ++ ++#: dwarf.c:2340 ++#, c-format ++msgid " .debug_loc.dwo: 0x%s 0x%s\n" ++msgstr "" ++ ++#: dwarf.c:2343 ++#, c-format ++msgid " .debug_str_offsets.dwo: 0x%s 0x%s\n" ++msgstr "" ++ ++#: dwarf.c:2352 +#, c-format +msgid "" +"Debug info is corrupted, length of CU at %s extends beyond end of section " +"(length = %s)\n" +msgstr "" + -+#: dwarf.c:2213 ++#: dwarf.c:2365 +#, c-format +msgid "CU at offset %s contains corrupt or unsupported version number: %d.\n" +msgstr "" + -+#: dwarf.c:2224 ++#: dwarf.c:2375 +#, c-format +msgid "" +"Debug info is corrupted, abbrev offset (%lx) is larger than abbrev section " +"size (%lx)\n" +msgstr "" + -+#: dwarf.c:2274 ++#: dwarf.c:2421 +#, c-format -+msgid "" -+"Bogus end-of-siblings marker detected at offset %lx in .debug_info section\n" ++msgid " <%d><%lx>: Abbrev Number: 0\n" +msgstr "" + -+#: dwarf.c:2278 ++#: dwarf.c:2431 ++#, c-format ++msgid "Bogus end-of-siblings marker detected at offset %lx in %s section\n" ++msgstr "" ++ ++#: dwarf.c:2435 +msgid "Further warnings about bogus end-of-sibling markers suppressed\n" +msgstr "" + -+#: dwarf.c:2297 ++#: dwarf.c:2454 +#, c-format +msgid " <%d><%lx>: Abbrev Number: %lu" +msgstr "" + -+#: dwarf.c:2301 ++#: dwarf.c:2458 +#, c-format +msgid " <%d><%lx>: ...\n" +msgstr "" + -+#: dwarf.c:2320 ++#: dwarf.c:2477 +#, c-format +msgid "" +"DIE at offset %lx refers to abbreviation number %lu which does not exist\n" +msgstr "" + -+#: dwarf.c:2422 ++#: dwarf.c:2634 ++msgid "The line info appears to be corrupt - the section is too small\n" ++msgstr "" ++ ++#: dwarf.c:2647 ++msgid "Only DWARF version 2, 3 and 4 line info is currently supported.\n" ++msgstr "" ++ ++#: dwarf.c:2660 ++msgid "Invalid maximum operations per insn.\n" ++msgstr "" ++ ++#: dwarf.c:2687 +#, c-format +msgid "" +"Raw dump of debug contents of section %s:\n" +"\n" +msgstr "" + -+#: dwarf.c:2460 -+#, c-format -+msgid "" -+"The information in section %s appears to be corrupt - the section is too " -+"small\n" -+msgstr "" -+ -+#: dwarf.c:2472 dwarf.c:2840 -+msgid "Only DWARF version 2, 3 and 4 line info is currently supported.\n" -+msgstr "" -+ -+#: dwarf.c:2486 dwarf.c:2855 -+msgid "Invalid maximum operations per insn.\n" -+msgstr "" -+ -+#: dwarf.c:2505 dwarf.c:3574 ++#: dwarf.c:2727 dwarf.c:3854 +#, c-format +msgid " Offset: 0x%lx\n" +msgstr "" + -+#: dwarf.c:2506 ++#: dwarf.c:2728 +#, c-format +msgid " Length: %ld\n" +msgstr "" + -+#: dwarf.c:2507 ++#: dwarf.c:2729 +#, c-format +msgid " DWARF Version: %d\n" +msgstr "" + -+#: dwarf.c:2508 ++#: dwarf.c:2730 +#, c-format +msgid " Prologue Length: %d\n" +msgstr "" + -+#: dwarf.c:2509 ++#: dwarf.c:2731 +#, c-format +msgid " Minimum Instruction Length: %d\n" +msgstr "" + -+#: dwarf.c:2511 ++#: dwarf.c:2733 +#, c-format +msgid " Maximum Ops per Instruction: %d\n" +msgstr "" + -+#: dwarf.c:2512 ++#: dwarf.c:2734 +#, c-format +msgid " Initial value of 'is_stmt': %d\n" +msgstr "" + -+#: dwarf.c:2513 ++#: dwarf.c:2735 +#, c-format +msgid " Line Base: %d\n" +msgstr "" + -+#: dwarf.c:2514 ++#: dwarf.c:2736 +#, c-format +msgid " Line Range: %d\n" +msgstr "" + -+#: dwarf.c:2515 ++#: dwarf.c:2737 +#, c-format +msgid " Opcode Base: %d\n" +msgstr "" + -+#: dwarf.c:2524 ++#: dwarf.c:2744 +#, c-format +msgid "" +"\n" +" Opcodes:\n" +msgstr "" + -+#: dwarf.c:2527 ++#: dwarf.c:2747 +#, c-format +msgid " Opcode %d has %d args\n" +msgstr "" + -+#: dwarf.c:2533 ++#: dwarf.c:2753 +#, c-format +msgid "" +"\n" +" The Directory Table is empty.\n" +msgstr "" + -+#: dwarf.c:2536 ++#: dwarf.c:2756 +#, c-format +msgid "" +"\n" -+" The Directory Table:\n" ++" The Directory Table (offset 0x%lx):\n" +msgstr "" + -+#: dwarf.c:2551 ++#: dwarf.c:2772 +#, c-format +msgid "" +"\n" +" The File Name Table is empty.\n" +msgstr "" + -+#: dwarf.c:2554 ++#: dwarf.c:2775 +#, c-format +msgid "" +"\n" -+" The File Name Table:\n" ++" The File Name Table (offset 0x%lx):\n" +msgstr "" + -+#. Now display the statements. -+#: dwarf.c:2584 ++#: dwarf.c:2801 ++msgid "Corrupt file name table entry\n" ++msgstr "" ++ ++#: dwarf.c:2815 +#, c-format -+msgid "" -+"\n" -+" Line Number Statements:\n" ++msgid " No Line Number Statements.\n" +msgstr "" + -+#: dwarf.c:2603 ++#: dwarf.c:2818 ++#, c-format ++msgid " Line Number Statements:\n" ++msgstr "" ++ ++#: dwarf.c:2839 +#, c-format +msgid " Special opcode %d: advance Address by %s to 0x%s" +msgstr "" + -+#: dwarf.c:2617 ++#: dwarf.c:2853 +#, c-format +msgid " Special opcode %d: advance Address by %s to 0x%s[%d]" +msgstr "" + -+#: dwarf.c:2625 ++#: dwarf.c:2861 +#, c-format +msgid " and Line by %s to %d\n" +msgstr "" + -+#: dwarf.c:2635 ++#: dwarf.c:2871 +#, c-format +msgid " Copy\n" +msgstr "" + -+#: dwarf.c:2645 ++#: dwarf.c:2881 +#, c-format +msgid " Advance PC by %s to 0x%s\n" +msgstr "" + -+#: dwarf.c:2658 ++#: dwarf.c:2894 +#, c-format +msgid " Advance PC by %s to 0x%s[%d]\n" +msgstr "" + -+#: dwarf.c:2669 ++#: dwarf.c:2905 +#, c-format +msgid " Advance Line by %s to %d\n" +msgstr "" + -+#: dwarf.c:2677 ++#: dwarf.c:2913 +#, c-format +msgid " Set File Name to entry %s in the File Name Table\n" +msgstr "" + -+#: dwarf.c:2685 ++#: dwarf.c:2921 +#, c-format +msgid " Set column to %s\n" +msgstr "" + -+#: dwarf.c:2693 ++#: dwarf.c:2929 +#, c-format +msgid " Set is_stmt to %s\n" +msgstr "" + -+#: dwarf.c:2698 ++#: dwarf.c:2934 +#, c-format +msgid " Set basic block\n" +msgstr "" + -+#: dwarf.c:2708 ++#: dwarf.c:2944 +#, c-format +msgid " Advance PC by constant %s to 0x%s\n" +msgstr "" + -+#: dwarf.c:2721 ++#: dwarf.c:2957 +#, c-format +msgid " Advance PC by constant %s to 0x%s[%d]\n" +msgstr "" + -+#: dwarf.c:2733 ++#: dwarf.c:2968 +#, c-format +msgid " Advance PC by fixed size amount %s to 0x%s\n" +msgstr "" + -+#: dwarf.c:2739 ++#: dwarf.c:2974 +#, c-format +msgid " Set prologue_end to true\n" +msgstr "" + -+#: dwarf.c:2743 ++#: dwarf.c:2978 +#, c-format +msgid " Set epilogue_begin to true\n" +msgstr "" + -+#: dwarf.c:2749 ++#: dwarf.c:2984 +#, c-format +msgid " Set ISA to %s\n" +msgstr "" + -+#: dwarf.c:2753 dwarf.c:3168 ++#: dwarf.c:2988 dwarf.c:3377 +#, c-format +msgid " Unknown opcode %d with operands: " +msgstr "" + -+#: dwarf.c:2787 ++#: dwarf.c:3026 +#, c-format +msgid "" +"Decoded dump of debug contents of section %s:\n" +"\n" +msgstr "" + -+#: dwarf.c:2828 -+msgid "The line info appears to be corrupt - the section is too small\n" -+msgstr "" -+ -+#: dwarf.c:2960 ++#: dwarf.c:3143 +#, c-format +msgid "CU: %s:\n" +msgstr "" + -+#: dwarf.c:2961 dwarf.c:2972 ++#: dwarf.c:3144 dwarf.c:3156 +#, c-format +msgid "File name Line number Starting address\n" +msgstr "" + -+#: dwarf.c:2968 ++#: dwarf.c:3152 +#, c-format +msgid "CU: %s/%s:\n" +msgstr "" + -+#: dwarf.c:3059 ++#: dwarf.c:3266 +#, c-format -+msgid "UNKNOWN: length %d\n" ++msgid "UNKNOWN (%u): length %d\n" +msgstr "" + -+#: dwarf.c:3164 ++#: dwarf.c:3308 ++#, c-format ++msgid "" ++"\n" ++" [Use file table entry %d]\n" ++msgstr "" ++ ++#: dwarf.c:3314 ++#, c-format ++msgid "" ++"\n" ++" [Use directory table entry %d]\n" ++msgstr "" ++ ++#: dwarf.c:3373 +#, c-format +msgid " Set ISA to %lu\n" +msgstr "" + -+#: dwarf.c:3330 dwarf.c:4195 ++#: dwarf.c:3518 ++msgid "no info" ++msgstr "" ++ ++#: dwarf.c:3519 ++msgid "type" ++msgstr "" ++ ++#: dwarf.c:3520 ++msgid "variable" ++msgstr "" ++ ++#: dwarf.c:3521 ++msgid "function" ++msgstr "" ++ ++#: dwarf.c:3522 ++msgid "other" ++msgstr "" ++ ++#: dwarf.c:3523 ++msgid "unused5" ++msgstr "" ++ ++#: dwarf.c:3524 ++msgid "unused6" ++msgstr "" ++ ++#: dwarf.c:3525 ++msgid "unused7" ++msgstr "" ++ ++#: dwarf.c:3573 dwarf.c:4636 +#, c-format +msgid "" +".debug_info offset of 0x%lx in %s section does not point to a CU header.\n" +msgstr "" + -+#: dwarf.c:3344 ++#: dwarf.c:3586 +msgid "Only DWARF 2 and 3 pubnames are currently supported\n" +msgstr "" + -+#: dwarf.c:3351 ++#: dwarf.c:3593 +#, c-format +msgid " Length: %ld\n" +msgstr "" + -+#: dwarf.c:3353 ++#: dwarf.c:3595 +#, c-format +msgid " Version: %d\n" +msgstr "" + -+#: dwarf.c:3355 ++#: dwarf.c:3597 +#, c-format +msgid " Offset into .debug_info section: 0x%lx\n" +msgstr "" + -+#: dwarf.c:3357 ++#: dwarf.c:3599 +#, c-format +msgid " Size of area in .debug_info section: %ld\n" +msgstr "" + -+#: dwarf.c:3360 ++#: dwarf.c:3603 ++#, c-format ++msgid "" ++"\n" ++" Offset Kind Name\n" ++msgstr "" ++ ++#: dwarf.c:3605 +#, c-format +msgid "" +"\n" +" Offset\tName\n" +msgstr "" + -+#: dwarf.c:3411 ++#: dwarf.c:3632 ++msgid "s" ++msgstr "" ++ ++#: dwarf.c:3632 ++msgid "g" ++msgstr "" ++ ++#: dwarf.c:3690 +#, c-format +msgid " DW_MACINFO_start_file - lineno: %d filenum: %d\n" +msgstr "" + -+#: dwarf.c:3417 ++#: dwarf.c:3696 +#, c-format +msgid " DW_MACINFO_end_file\n" +msgstr "" + -+#: dwarf.c:3425 ++#: dwarf.c:3704 +#, c-format +msgid " DW_MACINFO_define - lineno : %d macro : %s\n" +msgstr "" + -+#: dwarf.c:3434 ++#: dwarf.c:3713 +#, c-format +msgid " DW_MACINFO_undef - lineno : %d macro : %s\n" +msgstr "" + -+#: dwarf.c:3446 ++#: dwarf.c:3725 +#, c-format +msgid " DW_MACINFO_vendor_ext - constant : %d string : %s\n" +msgstr "" + -+#: dwarf.c:3566 ++#: dwarf.c:3846 +#, c-format +msgid "Only GNU extension to DWARF 4 of %s is currently supported.\n" +msgstr "" + -+#: dwarf.c:3576 ++#: dwarf.c:3856 +#, c-format +msgid " Version: %d\n" +msgstr "" + -+#: dwarf.c:3577 ++#: dwarf.c:3857 +#, c-format +msgid " Offset size: %d\n" +msgstr "" + -+#: dwarf.c:3582 ++#: dwarf.c:3861 +#, c-format +msgid " Offset into .debug_line: 0x%lx\n" +msgstr "" + -+#: dwarf.c:3593 ++#: dwarf.c:3875 +#, c-format +msgid " Extension opcode arguments:\n" +msgstr "" + -+#: dwarf.c:3601 ++#: dwarf.c:3883 +#, c-format +msgid " DW_MACRO_GNU_%02x has no arguments\n" +msgstr "" + -+#: dwarf.c:3604 ++#: dwarf.c:3886 +#, c-format +msgid " DW_MACRO_GNU_%02x arguments: " +msgstr "" + -+#: dwarf.c:3628 ++#: dwarf.c:3912 +#, c-format +msgid "Invalid extension opcode form %s\n" +msgstr "" + -+#: dwarf.c:3645 ++#: dwarf.c:3929 +msgid ".debug_macro section not zero terminated\n" +msgstr "" + -+#: dwarf.c:3666 ++#: dwarf.c:3950 +msgid "DW_MACRO_GNU_start_file used, but no .debug_line offset provided.\n" +msgstr "" + -+#: dwarf.c:3672 ++#: dwarf.c:3956 +#, c-format +msgid " DW_MACRO_GNU_start_file - lineno: %d filenum: %d\n" +msgstr "" + -+#: dwarf.c:3675 ++#: dwarf.c:3959 +#, c-format +msgid " DW_MACRO_GNU_start_file - lineno: %d filenum: %d filename: %s%s%s\n" +msgstr "" + -+#: dwarf.c:3683 ++#: dwarf.c:3967 +#, c-format +msgid " DW_MACRO_GNU_end_file\n" +msgstr "" + -+#: dwarf.c:3691 ++#: dwarf.c:3975 +#, c-format +msgid " DW_MACRO_GNU_define - lineno : %d macro : %s\n" +msgstr "" + -+#: dwarf.c:3700 ++#: dwarf.c:3984 +#, c-format +msgid " DW_MACRO_GNU_undef - lineno : %d macro : %s\n" +msgstr "" + -+#: dwarf.c:3710 ++#: dwarf.c:3993 +#, c-format +msgid " DW_MACRO_GNU_define_indirect - lineno : %d macro : %s\n" +msgstr "" + -+#: dwarf.c:3720 ++#: dwarf.c:4002 +#, c-format +msgid " DW_MACRO_GNU_undef_indirect - lineno : %d macro : %s\n" +msgstr "" + -+#: dwarf.c:3727 ++#: dwarf.c:4008 +#, c-format +msgid " DW_MACRO_GNU_transparent_include - offset : 0x%lx\n" +msgstr "" + -+#: dwarf.c:3734 ++#: dwarf.c:4016 ++#, c-format ++msgid " DW_MACRO_GNU_define_indirect_alt - lineno : %d macro offset : 0x%lx\n" ++msgstr "" ++ ++#: dwarf.c:4024 ++#, c-format ++msgid " DW_MACRO_GNU_undef_indirect_alt - lineno : %d macro offset : 0x%lx\n" ++msgstr "" ++ ++#: dwarf.c:4030 ++#, c-format ++msgid " DW_MACRO_GNU_transparent_include_alt - offset : 0x%lx\n" ++msgstr "" ++ ++#: dwarf.c:4037 +#, c-format +msgid " Unknown macro opcode %02x seen\n" +msgstr "" + -+#: dwarf.c:3746 ++#: dwarf.c:4049 +#, c-format +msgid " DW_MACRO_GNU_%02x\n" +msgstr "" + -+#: dwarf.c:3749 ++#: dwarf.c:4052 +#, c-format +msgid " DW_MACRO_GNU_%02x -" +msgstr "" + -+#: dwarf.c:3790 ++#: dwarf.c:4100 +#, c-format -+msgid " Number TAG\n" ++msgid " Number TAG (0x%lx)\n" +msgstr "" + -+#: dwarf.c:3799 ++#: dwarf.c:4109 +msgid "has children" +msgstr "" + -+#: dwarf.c:3799 ++#: dwarf.c:4109 +msgid "no children" +msgstr "" + -+#: dwarf.c:3850 dwarf.c:4077 dwarf.c:4311 ++#: dwarf.c:4150 dwarf.c:4182 dwarf.c:4191 dwarf.c:4264 dwarf.c:4312 ++#: dwarf.c:4320 ++#, c-format ++msgid "Location list starting at offset 0x%lx is not terminated.\n" ++msgstr "" ++ ++#: dwarf.c:4166 dwarf.c:4274 dwarf.c:4939 ++#, c-format ++msgid "\n" ++msgstr "" ++ ++#: dwarf.c:4176 ++#, c-format ++msgid "(base address)\n" ++msgstr "" ++ ++#: dwarf.c:4212 ++msgid " (start == end)" ++msgstr "" ++ ++#: dwarf.c:4214 ++msgid " (start > end)" ++msgstr "" ++ ++#: dwarf.c:4281 ++#, c-format ++msgid "(base address selection entry)\n" ++msgstr "" ++ ++#: dwarf.c:4305 ++#, c-format ++msgid "Unknown location list entry type 0x%x.\n" ++msgstr "" ++ ++#: dwarf.c:4384 dwarf.c:4524 dwarf.c:4727 dwarf.c:4790 dwarf.c:4837 +#, c-format +msgid "" +"\n" +"The %s section is empty.\n" +msgstr "" + -+#: dwarf.c:3856 dwarf.c:4317 ++#: dwarf.c:4390 dwarf.c:4733 dwarf.c:4843 +#, c-format +msgid "" +"Unable to load/parse the .debug_info section, so cannot interpret the %s " +"section.\n" +msgstr "" + -+#: dwarf.c:3900 ++#: dwarf.c:4434 +msgid "No location lists in .debug_info section!\n" +msgstr "" + -+#: dwarf.c:3905 ++#: dwarf.c:4438 +#, c-format +msgid "Location lists in %s section start at 0x%s\n" +msgstr "" + -+#: dwarf.c:3912 ++#: dwarf.c:4445 +#, c-format +msgid " Offset Begin End Expression\n" +msgstr "" + -+#: dwarf.c:3961 ++#: dwarf.c:4481 +#, c-format +msgid "There is a hole [0x%lx - 0x%lx] in .debug_loc section.\n" +msgstr "" + -+#: dwarf.c:3965 ++#: dwarf.c:4485 +#, c-format +msgid "There is an overlap [0x%lx - 0x%lx] in .debug_loc section.\n" +msgstr "" + -+#: dwarf.c:3973 ++#: dwarf.c:4493 +#, c-format +msgid "Offset 0x%lx is bigger than .debug_loc section size.\n" +msgstr "" + -+#: dwarf.c:3982 dwarf.c:4017 dwarf.c:4027 -+#, c-format -+msgid "Location list starting at offset 0x%lx is not terminated.\n" -+msgstr "" -+ -+#: dwarf.c:4001 dwarf.c:4405 -+#, c-format -+msgid "\n" -+msgstr "" -+ -+#: dwarf.c:4011 -+#, c-format -+msgid "(base address)\n" -+msgstr "" -+ -+#: dwarf.c:4048 -+msgid " (start == end)" -+msgstr "" -+ -+#: dwarf.c:4050 -+msgid " (start > end)" -+msgstr "" -+ -+#: dwarf.c:4060 ++#: dwarf.c:4507 +#, c-format +msgid "There are %ld unused bytes at the end of section %s\n" +msgstr "" + -+#: dwarf.c:4206 ++#: dwarf.c:4644 +msgid "Only DWARF 2 and 3 aranges are currently supported.\n" +msgstr "" + -+#: dwarf.c:4210 ++#: dwarf.c:4648 +#, c-format +msgid " Length: %ld\n" +msgstr "" + -+#: dwarf.c:4212 ++#: dwarf.c:4650 +#, c-format +msgid " Version: %d\n" +msgstr "" + -+#: dwarf.c:4213 ++#: dwarf.c:4651 +#, c-format +msgid " Offset into .debug_info: 0x%lx\n" +msgstr "" + -+#: dwarf.c:4215 ++#: dwarf.c:4653 +#, c-format +msgid " Pointer Size: %d\n" +msgstr "" + -+#: dwarf.c:4216 ++#: dwarf.c:4654 +#, c-format +msgid " Segment Size: %d\n" +msgstr "" + -+#: dwarf.c:4222 ++#: dwarf.c:4660 +#, c-format +msgid "Invalid address size in %s section!\n" +msgstr "" + -+#: dwarf.c:4232 ++#: dwarf.c:4670 +msgid "Pointer size + Segment size is not a power of two.\n" +msgstr "" + -+#: dwarf.c:4237 ++#: dwarf.c:4675 +#, c-format +msgid "" +"\n" +" Address Length\n" +msgstr "" + -+#: dwarf.c:4239 ++#: dwarf.c:4677 +#, c-format +msgid "" +"\n" +" Address Length\n" +msgstr "" + -+#: dwarf.c:4327 -+msgid "No range lists in .debug_info section!\n" ++#: dwarf.c:4760 ++#, c-format ++msgid " For compilation unit at offset 0x%s:\n" +msgstr "" + -+#: dwarf.c:4351 ++#: dwarf.c:4763 ++#, c-format ++msgid "\tIndex\tAddress\n" ++msgstr "" ++ ++#: dwarf.c:4770 ++#, c-format ++msgid "\t%d:\t" ++msgstr "" ++ ++#. This can happen when the file was compiled with -gsplit-debug ++#. which removes references to range lists from the primary .o file. ++#: dwarf.c:4856 ++#, c-format ++msgid "No range lists in .debug_info section.\n" ++msgstr "" ++ ++#: dwarf.c:4881 +#, c-format +msgid "Range lists in %s section start at 0x%lx\n" +msgstr "" + -+#: dwarf.c:4355 ++#: dwarf.c:4885 +#, c-format +msgid " Offset Begin End\n" +msgstr "" + -+#: dwarf.c:4376 ++#: dwarf.c:4905 +#, c-format +msgid "There is a hole [0x%lx - 0x%lx] in %s section.\n" +msgstr "" + -+#: dwarf.c:4380 ++#: dwarf.c:4912 +#, c-format +msgid "There is an overlap [0x%lx - 0x%lx] in %s section.\n" +msgstr "" + -+#: dwarf.c:4423 ++#: dwarf.c:4957 +msgid "(start == end)" +msgstr "" + -+#: dwarf.c:4425 ++#: dwarf.c:4959 +msgid "(start > end)" +msgstr "" + -+#: dwarf.c:4678 ++#: dwarf.c:5229 +msgid "bad register: " +msgstr "" + +#. The documentation for the format of this file is in gdb/dwarf2read.c. -+#: dwarf.c:4681 dwarf.c:5490 ++#: dwarf.c:5232 dwarf.c:6072 +#, c-format +msgid "Contents of the %s section:\n" +msgstr "" + -+#: dwarf.c:5451 ++#: dwarf.c:6033 +#, c-format +msgid " DW_CFA_??? (User defined call frame op: %#x)\n" +msgstr "" + -+#: dwarf.c:5453 ++#: dwarf.c:6035 +#, c-format +msgid "unsupported or unknown Dwarf Call Frame Instruction number: %#x\n" +msgstr "" + -+#: dwarf.c:5494 ++#: dwarf.c:6076 +#, c-format +msgid "Truncated header in the %s section.\n" +msgstr "" + -+#: dwarf.c:5499 ++#: dwarf.c:6081 +#, c-format +msgid "Version %ld\n" +msgstr "" + -+#: dwarf.c:5506 -+msgid "The address table data in version 3 may be wrong.\n" -+msgstr "" -+ -+#: dwarf.c:5509 -+msgid "Version 4 does not support case insensitive lookups.\n" -+msgstr "" -+ -+#: dwarf.c:5514 ++#: dwarf.c:6087 +#, c-format +msgid "Unsupported version %lu.\n" +msgstr "" + -+#: dwarf.c:5530 ++#: dwarf.c:6091 ++msgid "The address table data in version 3 may be wrong.\n" ++msgstr "" ++ ++#: dwarf.c:6093 ++msgid "Version 4 does not support case insensitive lookups.\n" ++msgstr "" ++ ++#: dwarf.c:6095 ++msgid "Version 5 does not include inlined functions.\n" ++msgstr "" ++ ++#: dwarf.c:6097 ++msgid "Version 6 does not include symbol attributes.\n" ++msgstr "" ++ ++#: dwarf.c:6115 +#, c-format +msgid "Corrupt header in the %s section.\n" +msgstr "" + -+#: dwarf.c:5545 ++#: dwarf.c:6130 +#, c-format +msgid "" +"\n" +"CU table:\n" +msgstr "" + -+#: dwarf.c:5551 ++#: dwarf.c:6136 +#, c-format +msgid "[%3u] 0x%lx - 0x%lx\n" +msgstr "" + -+#: dwarf.c:5556 ++#: dwarf.c:6141 +#, c-format +msgid "" +"\n" +"TU table:\n" +msgstr "" + -+#: dwarf.c:5563 ++#: dwarf.c:6148 +#, c-format +msgid "[%3u] 0x%lx 0x%lx " +msgstr "" + -+#: dwarf.c:5570 ++#: dwarf.c:6155 +#, c-format +msgid "" +"\n" +"Address table:\n" +msgstr "" + -+#: dwarf.c:5579 ++#: dwarf.c:6164 +#, c-format +msgid "%lu\n" +msgstr "" + -+#: dwarf.c:5582 ++#: dwarf.c:6167 +#, c-format +msgid "" +"\n" +"Symbol table:\n" +msgstr "" + -+#: dwarf.c:5616 ++#: dwarf.c:6200 ++msgid "static" ++msgstr "" ++ ++#: dwarf.c:6200 ++msgid "global" ++msgstr "" ++ ++#: dwarf.c:6238 dwarf.c:6249 ++msgid "Internal error: out of space in the shndx pool.\n" ++msgstr "" ++ ++#: dwarf.c:6322 ++#, c-format ++msgid " Version: %d\n" ++msgstr "" ++ ++#: dwarf.c:6324 ++#, c-format ++msgid " Number of columns: %d\n" ++msgstr "" ++ ++#: dwarf.c:6325 ++#, c-format ++msgid " Number of used entries: %d\n" ++msgstr "" ++ ++#: dwarf.c:6326 ++#, c-format ++msgid "" ++" Number of slots: %d\n" ++"\n" ++msgstr "" ++ ++#: dwarf.c:6331 ++#, c-format ++msgid "Section %s too small for %d hash table entries\n" ++msgstr "" ++ ++#: dwarf.c:6351 ++#, c-format ++msgid " [%3d] Signature: 0x%s Sections: " ++msgstr "" ++ ++#: dwarf.c:6358 ++#, c-format ++msgid "Section %s too small for shndx pool\n" ++msgstr "" ++ ++#: dwarf.c:6398 ++#, c-format ++msgid "Section %s too small for offset and size tables\n" ++msgstr "" ++ ++#: dwarf.c:6405 ++#, c-format ++msgid " Offset table\n" ++msgstr "" ++ ++#: dwarf.c:6407 dwarf.c:6471 ++msgid "signature" ++msgstr "" ++ ++#: dwarf.c:6407 dwarf.c:6471 ++msgid "dwo_id" ++msgstr "" ++ ++#: dwarf.c:6443 dwarf.c:6489 ++#, c-format ++msgid " [%3d] 0x%s" ++msgstr "" ++ ++#: dwarf.c:6469 ++#, c-format ++msgid " Size table\n" ++msgstr "" ++ ++#: dwarf.c:6511 ++#, c-format ++msgid " Unsupported version\n" ++msgstr "" ++ ++#: dwarf.c:6576 +#, c-format +msgid "Displaying the debug contents of section %s is not yet supported.\n" +msgstr "" + -+#: dwarf.c:5752 dwarf.c:5822 ++#: dwarf.c:6714 dwarf.c:6784 +#, c-format +msgid "Unrecognized debug option '%s'\n" +msgstr "" + -+#: elfcomm.c:39 ++#: elfcomm.c:42 +#, c-format +msgid "%s: Error: " +msgstr "" + -+#: elfcomm.c:50 ++#: elfcomm.c:56 +#, c-format +msgid "%s: Warning: " +msgstr "" + -+#: elfcomm.c:82 elfcomm.c:117 elfcomm.c:167 elfcomm.c:216 ++#: elfcomm.c:88 elfcomm.c:123 elfcomm.c:224 elfcomm.c:330 +#, c-format +msgid "Unhandled data length: %d\n" +msgstr "" + -+#: elfcomm.c:263 elfcomm.c:277 elfcomm.c:645 readelf.c:3683 readelf.c:3991 -+#: readelf.c:4034 readelf.c:4108 readelf.c:4187 readelf.c:4965 readelf.c:4989 -+#: readelf.c:7397 readelf.c:7443 readelf.c:7642 readelf.c:8863 readelf.c:8877 -+#: readelf.c:9423 readelf.c:9439 readelf.c:9482 readelf.c:9507 readelf.c:11904 -+#: readelf.c:12096 readelf.c:12929 ++#: elfcomm.c:405 elfcomm.c:419 elfcomm.c:833 readelf.c:4177 readelf.c:4485 ++#: readelf.c:4528 readelf.c:4602 readelf.c:4681 readelf.c:5468 readelf.c:5492 ++#: readelf.c:7979 readelf.c:8025 readelf.c:8224 readelf.c:9525 readelf.c:9539 ++#: readelf.c:10085 readelf.c:10102 readelf.c:10145 readelf.c:10171 ++#: readelf.c:12792 readelf.c:12984 readelf.c:13978 +msgid "Out of memory\n" +msgstr "" + -+#: elfcomm.c:312 -+#, c-format -+msgid "%s: failed to seek to first archive header\n" -+msgstr "" -+ -+#: elfcomm.c:321 elfcomm.c:611 elfedit.c:340 readelf.c:13418 -+#, c-format -+msgid "%s: failed to read archive header\n" -+msgstr "" -+ -+#: elfcomm.c:347 -+#, c-format -+msgid "%s: the archive index is empty\n" -+msgstr "" -+ -+#: elfcomm.c:355 elfcomm.c:381 -+#, c-format -+msgid "%s: failed to read archive index\n" -+msgstr "" -+ -+#: elfcomm.c:365 -+#, c-format -+msgid "" -+"%s: the archive index is supposed to have %ld entries, but the size in the " -+"header is too small\n" -+msgstr "" -+ -+#: elfcomm.c:373 -+msgid "Out of memory whilst trying to read archive symbol index\n" -+msgstr "" -+ -+#: elfcomm.c:392 -+msgid "Out of memory whilst trying to convert the archive symbol index\n" -+msgstr "" -+ -+#: elfcomm.c:405 -+#, c-format -+msgid "%s: the archive has an index but no symbols\n" -+msgstr "" -+ -+#: elfcomm.c:413 -+msgid "Out of memory whilst trying to read archive index symbol table\n" -+msgstr "" -+ -+#: elfcomm.c:419 -+#, c-format -+msgid "%s: failed to read archive index symbol table\n" -+msgstr "" -+ -+#: elfcomm.c:428 ++#: elfcomm.c:456 +#, c-format +msgid "%s: failed to skip archive symbol table\n" +msgstr "" + -+#: elfcomm.c:440 ++#: elfcomm.c:475 ++#, c-format ++msgid "%s: the archive index is empty\n" ++msgstr "" ++ ++#: elfcomm.c:483 elfcomm.c:510 ++#, c-format ++msgid "%s: failed to read archive index\n" ++msgstr "" ++ ++#: elfcomm.c:492 ++#, c-format ++msgid "" ++"%s: the archive index is supposed to have %ld entries of %d bytes, but the " ++"size is only %ld\n" ++msgstr "" ++ ++#: elfcomm.c:502 ++msgid "Out of memory whilst trying to read archive symbol index\n" ++msgstr "" ++ ++#: elfcomm.c:522 ++msgid "Out of memory whilst trying to convert the archive symbol index\n" ++msgstr "" ++ ++#: elfcomm.c:535 ++#, c-format ++msgid "%s: the archive has an index but no symbols\n" ++msgstr "" ++ ++#: elfcomm.c:543 ++msgid "Out of memory whilst trying to read archive index symbol table\n" ++msgstr "" ++ ++#: elfcomm.c:551 ++#, c-format ++msgid "%s: failed to read archive index symbol table\n" ++msgstr "" ++ ++#: elfcomm.c:561 +#, c-format +msgid "%s: failed to read archive header following archive index\n" +msgstr "" + -+#: elfcomm.c:446 ++#: elfcomm.c:594 ++#, c-format ++msgid "%s: failed to seek to first archive header\n" ++msgstr "" ++ ++#: elfcomm.c:603 elfcomm.c:791 elfedit.c:338 readelf.c:14477 ++#, c-format ++msgid "%s: failed to read archive header\n" ++msgstr "" ++ ++#: elfcomm.c:620 +#, c-format +msgid "%s has no archive index\n" +msgstr "" + -+#: elfcomm.c:457 ++#: elfcomm.c:631 +msgid "Out of memory reading long symbol names in archive\n" +msgstr "" + -+#: elfcomm.c:465 ++#: elfcomm.c:639 +#, c-format +msgid "%s: failed to read long symbol name string table\n" +msgstr "" + -+#: elfcomm.c:605 ++#: elfcomm.c:713 ++msgid "Archive member uses long names, but no longname table found\n" ++msgstr "" ++ ++#: elfcomm.c:785 +#, c-format +msgid "%s: failed to seek to next file name\n" +msgstr "" + -+#: elfcomm.c:616 elfedit.c:347 readelf.c:13424 ++#: elfcomm.c:796 elfedit.c:345 readelf.c:14483 +#, c-format +msgid "%s: did not find a valid archive header\n" +msgstr "" + -+#: elfedit.c:73 ++#: elfcomm.c:815 readelf.c:279 readelf.c:5586 readelf.c:6098 readelf.c:8774 ++#: readelf.c:8890 readelf.c:9895 readelf.c:9989 readelf.c:10050 ++#: readelf.c:13313 readelf.c:13316 ++msgid "" ++msgstr "" ++ ++#: elfedit.c:71 +#, c-format +msgid "%s: Not an ELF file - wrong magic bytes at the start\n" +msgstr "" + -+#: elfedit.c:81 ++#: elfedit.c:79 +#, c-format +msgid "%s: Unsupported EI_VERSION: %d is not %d\n" +msgstr "" + -+#: elfedit.c:97 ++#: elfedit.c:95 +#, c-format +msgid "%s: Unmatched EI_CLASS: %d is not %d\n" +msgstr "" + -+#: elfedit.c:108 ++#: elfedit.c:106 +#, c-format +msgid "%s: Unmatched e_machine: %d is not %d\n" +msgstr "" + -+#: elfedit.c:119 ++#: elfedit.c:117 +#, c-format +msgid "%s: Unmatched e_type: %d is not %d\n" +msgstr "" + -+#: elfedit.c:130 ++#: elfedit.c:128 +#, c-format +msgid "%s: Unmatched EI_OSABI: %d is not %d\n" +msgstr "" + -+#: elfedit.c:163 ++#: elfedit.c:161 +#, c-format +msgid "%s: Failed to update ELF header: %s\n" +msgstr "" + -+#: elfedit.c:196 ++#: elfedit.c:194 +#, c-format +msgid "Unsupported EI_CLASS: %d\n" +msgstr "" + -+#: elfedit.c:229 ++#: elfedit.c:227 +msgid "" +"This executable has been built without support for a\n" +"64 bit data type and so it cannot process 64 bit ELF files.\n" +msgstr "" + -+#: elfedit.c:270 ++#: elfedit.c:268 +#, c-format +msgid "%s: Failed to read ELF header\n" +msgstr "" + -+#: elfedit.c:277 ++#: elfedit.c:275 +#, c-format +msgid "%s: Failed to seek to ELF header\n" +msgstr "" + -+#: elfedit.c:331 readelf.c:13410 ++#: elfedit.c:329 readelf.c:14469 +#, c-format +msgid "%s: failed to seek to next archive header\n" +msgstr "" + -+#: elfedit.c:362 elfedit.c:371 readelf.c:13438 readelf.c:13447 ++#: elfedit.c:360 elfedit.c:369 readelf.c:14497 readelf.c:14506 +#, c-format +msgid "%s: bad archive file name\n" +msgstr "" + -+#: elfedit.c:391 elfedit.c:483 ++#: elfedit.c:389 elfedit.c:481 +#, c-format +msgid "Input file '%s' is not readable\n" +msgstr "" + -+#: elfedit.c:415 ++#: elfedit.c:413 +#, c-format +msgid "%s: failed to seek to archive member\n" +msgstr "" + -+#: elfedit.c:454 readelf.c:13533 ++#: elfedit.c:452 readelf.c:14601 +#, c-format +msgid "'%s': No such file\n" +msgstr "" + -+#: elfedit.c:456 readelf.c:13535 ++#: elfedit.c:454 readelf.c:14603 +#, c-format +msgid "Could not locate '%s'. System error message: %s\n" +msgstr "" + -+#: elfedit.c:463 readelf.c:13542 ++#: elfedit.c:461 readelf.c:14610 +#, c-format +msgid "'%s' is not an ordinary file\n" +msgstr "" + -+#: elfedit.c:489 readelf.c:13555 ++#: elfedit.c:487 readelf.c:14623 +#, c-format +msgid "%s: Failed to read file's magic number\n" +msgstr "" + -+#: elfedit.c:547 ++#: elfedit.c:545 +#, c-format +msgid "Unknown OSABI: %s\n" +msgstr "" + -+#: elfedit.c:568 ++#: elfedit.c:566 +#, c-format +msgid "Unknown machine type: %s\n" +msgstr "" + -+#: elfedit.c:587 ++#: elfedit.c:585 +#, c-format +msgid "Unknown machine type: %d\n" +msgstr "" + -+#: elfedit.c:606 ++#: elfedit.c:604 +#, c-format +msgid "Unknown type: %s\n" +msgstr "" + -+#: elfedit.c:637 ++#: elfedit.c:635 +#, c-format +msgid "Usage: %s elffile(s)\n" +msgstr "" + -+#: elfedit.c:639 ++#: elfedit.c:637 +#, c-format +msgid " Update the ELF header of ELF files\n" +msgstr "" + -+#: elfedit.c:640 objcopy.c:475 objcopy.c:585 ++#: elfedit.c:638 objcopy.c:489 objcopy.c:615 +#, c-format +msgid " The options are:\n" +msgstr "" + -+#: elfedit.c:641 ++#: elfedit.c:639 +#, c-format +msgid "" +" --input-mach Set input machine type to \n" @@ -112848,120 +114489,120 @@ index 0000000..0d08397 +msgid "Duplicate symbol entered into keyword list." +msgstr "" + -+#: nlmconv.c:274 srconv.c:1824 ++#: nlmconv.c:273 srconv.c:1825 +msgid "input and output files must be different" +msgstr "" + -+#: nlmconv.c:321 ++#: nlmconv.c:320 +msgid "input file named both on command line and with INPUT" +msgstr "" + -+#: nlmconv.c:330 ++#: nlmconv.c:329 +msgid "no input file" +msgstr "" + -+#: nlmconv.c:360 ++#: nlmconv.c:359 +msgid "no name for output file" +msgstr "" + -+#: nlmconv.c:374 ++#: nlmconv.c:373 +msgid "warning: input and output formats are not compatible" +msgstr "" + -+#: nlmconv.c:404 ++#: nlmconv.c:403 +msgid "make .bss section" +msgstr "" + -+#: nlmconv.c:414 ++#: nlmconv.c:413 +msgid "make .nlmsections section" +msgstr "" + -+#: nlmconv.c:442 ++#: nlmconv.c:441 +msgid "set .bss vma" +msgstr "" + -+#: nlmconv.c:449 ++#: nlmconv.c:448 +msgid "set .data size" +msgstr "" + -+#: nlmconv.c:629 ++#: nlmconv.c:628 +#, c-format +msgid "warning: symbol %s imported but not in import list" +msgstr "" + -+#: nlmconv.c:649 ++#: nlmconv.c:648 +msgid "set start address" +msgstr "" + -+#: nlmconv.c:698 ++#: nlmconv.c:697 +#, c-format +msgid "warning: START procedure %s not defined" +msgstr "" + -+#: nlmconv.c:700 ++#: nlmconv.c:699 +#, c-format +msgid "warning: EXIT procedure %s not defined" +msgstr "" + -+#: nlmconv.c:702 ++#: nlmconv.c:701 +#, c-format +msgid "warning: CHECK procedure %s not defined" +msgstr "" + -+#: nlmconv.c:722 nlmconv.c:908 ++#: nlmconv.c:721 nlmconv.c:907 +msgid "custom section" +msgstr "" + -+#: nlmconv.c:742 nlmconv.c:937 ++#: nlmconv.c:741 nlmconv.c:936 +msgid "help section" +msgstr "" + -+#: nlmconv.c:764 nlmconv.c:955 ++#: nlmconv.c:763 nlmconv.c:954 +msgid "message section" +msgstr "" + -+#: nlmconv.c:779 nlmconv.c:988 ++#: nlmconv.c:778 nlmconv.c:987 +msgid "module section" +msgstr "" + -+#: nlmconv.c:798 nlmconv.c:1004 ++#: nlmconv.c:797 nlmconv.c:1003 +msgid "rpc section" +msgstr "" + +#. There is no place to record this information. -+#: nlmconv.c:834 ++#: nlmconv.c:833 +#, c-format +msgid "%s: warning: shared libraries can not have uninitialized data" +msgstr "" + -+#: nlmconv.c:855 nlmconv.c:1023 ++#: nlmconv.c:854 nlmconv.c:1022 +msgid "shared section" +msgstr "" + -+#: nlmconv.c:863 ++#: nlmconv.c:862 +msgid "warning: No version number given" +msgstr "" + -+#: nlmconv.c:903 nlmconv.c:932 nlmconv.c:950 nlmconv.c:999 nlmconv.c:1018 ++#: nlmconv.c:902 nlmconv.c:931 nlmconv.c:949 nlmconv.c:998 nlmconv.c:1017 +#, c-format +msgid "%s: read: %s" +msgstr "" + -+#: nlmconv.c:925 ++#: nlmconv.c:924 +msgid "warning: FULLMAP is not supported; try ld -M" +msgstr "" + -+#: nlmconv.c:1101 ++#: nlmconv.c:1100 +#, c-format +msgid "Usage: %s [option(s)] [in-file [out-file]]\n" +msgstr "" + -+#: nlmconv.c:1102 ++#: nlmconv.c:1101 +#, c-format +msgid " Convert an object file into a NetWare Loadable Module\n" +msgstr "" + -+#: nlmconv.c:1103 ++#: nlmconv.c:1102 +#, c-format +msgid "" +" The options are:\n" @@ -112975,74 +114616,74 @@ index 0000000..0d08397 +" -v --version Display the program's version\n" +msgstr "" + -+#: nlmconv.c:1144 ++#: nlmconv.c:1143 +#, c-format +msgid "support not compiled in for %s" +msgstr "" + -+#: nlmconv.c:1181 ++#: nlmconv.c:1180 +msgid "make section" +msgstr "" + -+#: nlmconv.c:1195 ++#: nlmconv.c:1194 +msgid "set section size" +msgstr "" + -+#: nlmconv.c:1201 ++#: nlmconv.c:1200 +msgid "set section alignment" +msgstr "" + -+#: nlmconv.c:1205 ++#: nlmconv.c:1204 +msgid "set section flags" +msgstr "" + -+#: nlmconv.c:1216 ++#: nlmconv.c:1215 +msgid "set .nlmsections size" +msgstr "" + -+#: nlmconv.c:1297 nlmconv.c:1305 nlmconv.c:1314 nlmconv.c:1319 ++#: nlmconv.c:1296 nlmconv.c:1304 nlmconv.c:1313 nlmconv.c:1318 +msgid "set .nlmsection contents" +msgstr "" + -+#: nlmconv.c:1796 ++#: nlmconv.c:1795 +msgid "stub section sizes" +msgstr "" + -+#: nlmconv.c:1843 ++#: nlmconv.c:1842 +msgid "writing stub" +msgstr "" + -+#: nlmconv.c:1927 ++#: nlmconv.c:1926 +#, c-format +msgid "unresolved PC relative reloc against %s" +msgstr "" + -+#: nlmconv.c:1991 ++#: nlmconv.c:1990 +#, c-format +msgid "overflow when adjusting relocation against %s" +msgstr "" + -+#: nlmconv.c:2118 ++#: nlmconv.c:2117 +#, c-format +msgid "%s: execution of %s failed: " +msgstr "" + -+#: nlmconv.c:2133 ++#: nlmconv.c:2132 +#, c-format +msgid "Execution of %s failed" +msgstr "" + -+#: nm.c:225 size.c:78 strings.c:650 ++#: nm.c:226 size.c:78 strings.c:636 +#, c-format +msgid "Usage: %s [option(s)] [file(s)]\n" +msgstr "" + -+#: nm.c:226 ++#: nm.c:227 +#, c-format +msgid " List symbols in [file(s)] (a.out by default).\n" +msgstr "" + -+#: nm.c:227 ++#: nm.c:228 +#, c-format +msgid "" +" The options are:\n" @@ -113073,12 +114714,12 @@ index 0000000..0d08397 +" -r, --reverse-sort Reverse the sense of the sort\n" +msgstr "" + -+#: nm.c:250 ++#: nm.c:251 +#, c-format +msgid " --plugin NAME Load the specified plugin\n" +msgstr "" + -+#: nm.c:253 ++#: nm.c:254 +#, c-format +msgid "" +" -S, --print-size Print size of defined symbols\n" @@ -113096,39 +114737,39 @@ index 0000000..0d08397 +"\n" +msgstr "" + -+#: nm.c:301 ++#: nm.c:302 +#, c-format +msgid "%s: invalid radix" +msgstr "" + -+#: nm.c:325 ++#: nm.c:326 +#, c-format +msgid "%s: invalid output format" +msgstr "" + -+#: nm.c:346 readelf.c:8616 readelf.c:8661 ++#: nm.c:347 readelf.c:9254 readelf.c:9304 +#, c-format +msgid ": %d" +msgstr "" + -+#: nm.c:348 readelf.c:8625 readelf.c:8679 ++#: nm.c:349 readelf.c:9263 readelf.c:9323 +#, c-format +msgid ": %d" +msgstr "" + -+#: nm.c:350 readelf.c:8628 readelf.c:8682 ++#: nm.c:351 readelf.c:9266 readelf.c:9326 +#, c-format +msgid ": %d" +msgstr "" + -+#: nm.c:390 ++#: nm.c:391 +#, c-format +msgid "" +"\n" +"Archive index:\n" +msgstr "" + -+#: nm.c:1258 ++#: nm.c:1260 +#, c-format +msgid "" +"\n" @@ -113137,7 +114778,7 @@ index 0000000..0d08397 +"\n" +msgstr "" + -+#: nm.c:1260 ++#: nm.c:1262 +#, c-format +msgid "" +"\n" @@ -113146,7 +114787,7 @@ index 0000000..0d08397 +"\n" +msgstr "" + -+#: nm.c:1262 nm.c:1313 ++#: nm.c:1264 nm.c:1315 +#, c-format +msgid "" +"Name Value Class Type Size Line " @@ -113154,7 +114795,7 @@ index 0000000..0d08397 +"\n" +msgstr "" + -+#: nm.c:1265 nm.c:1316 ++#: nm.c:1267 nm.c:1318 +#, c-format +msgid "" +"Name Value Class Type " @@ -113162,57 +114803,57 @@ index 0000000..0d08397 +"\n" +msgstr "" + -+#: nm.c:1309 -+#, c-format -+msgid "" -+"\n" -+"\n" -+"Undefined symbols from %s[%s]:\n" -+"\n" -+msgstr "" -+ +#: nm.c:1311 +#, c-format +msgid "" +"\n" +"\n" ++"Undefined symbols from %s[%s]:\n" ++"\n" ++msgstr "" ++ ++#: nm.c:1313 ++#, c-format ++msgid "" ++"\n" ++"\n" +"Symbols from %s[%s]:\n" +"\n" +msgstr "" + -+#: nm.c:1403 ++#: nm.c:1405 +#, c-format +msgid "Print width has not been initialized (%d)" +msgstr "" + -+#: nm.c:1631 ++#: nm.c:1642 +msgid "Only -X 32_64 is supported" +msgstr "" + -+#: nm.c:1660 ++#: nm.c:1671 +msgid "Using the --size-sort and --undefined-only options together" +msgstr "" + -+#: nm.c:1661 ++#: nm.c:1672 +msgid "will produce no output, since undefined symbols have no size." +msgstr "" + -+#: nm.c:1689 ++#: nm.c:1700 +#, c-format +msgid "data size %ld" +msgstr "" + -+#: objcopy.c:473 srconv.c:1732 ++#: objcopy.c:487 srconv.c:1733 +#, c-format +msgid "Usage: %s [option(s)] in-file [out-file]\n" +msgstr "" + -+#: objcopy.c:474 ++#: objcopy.c:488 +#, c-format +msgid " Copies a binary file, possibly transforming it in the process\n" +msgstr "" + -+#: objcopy.c:476 ++#: objcopy.c:490 +#, c-format +msgid "" +" -I --input-target Assume input file is in format \n" @@ -113225,6 +114866,31 @@ index 0000000..0d08397 +"possible\n" +" -p --preserve-dates Copy modified/access timestamps to the " +"output\n" ++msgstr "" ++ ++#: objcopy.c:498 objcopy.c:623 ++#, c-format ++msgid "" ++" -D --enable-deterministic-archives\n" ++" Produce deterministic output when " ++"stripping archives (default)\n" ++" -U --disable-deterministic-archives\n" ++" Disable -D behavior\n" ++msgstr "" ++ ++#: objcopy.c:504 objcopy.c:629 ++#, c-format ++msgid "" ++" -D --enable-deterministic-archives\n" ++" Produce deterministic output when " ++"stripping archives\n" ++" -U --disable-deterministic-archives\n" ++" Disable -D behavior (default)\n" ++msgstr "" ++ ++#: objcopy.c:509 ++#, c-format ++msgid "" +" -j --only-section Only copy section into the output\n" +" --add-gnu-debuglink= Add section .gnu_debuglink linking to " +"\n" @@ -113232,6 +114898,7 @@ index 0000000..0d08397 +" -S --strip-all Remove all symbol and relocation " +"information\n" +" -g --strip-debug Remove all debugging symbols & sections\n" ++" --strip-dwo Remove all DWO sections\n" +" --strip-unneeded Remove all symbols not needed by " +"relocations\n" +" -N --strip-symbol Do not copy symbol \n" @@ -113241,6 +114908,7 @@ index 0000000..0d08397 +" relocations\n" +" --only-keep-debug Strip everything but the debug " +"information\n" ++" --extract-dwo Copy only DWO sections\n" +" --extract-symbol Remove section contents but keep symbols\n" +" -K --keep-symbol Do not strip symbol \n" +" --keep-file-symbols Do not strip file symbol(s)\n" @@ -113286,6 +114954,8 @@ index 0000000..0d08397 +"\n" +" --add-section = Add section found in to " +"output\n" ++" --dump-section = Dump the contents of section into " ++"\n" +" --rename-section =[,] Rename section to \n" +" --long-section-names {enable|disable|keep}\n" +" Handle long section names in Coff " @@ -113348,17 +115018,17 @@ index 0000000..0d08397 +"supported\n" +msgstr "" + -+#: objcopy.c:583 ++#: objcopy.c:613 +#, c-format +msgid "Usage: %s in-file(s)\n" +msgstr "" + -+#: objcopy.c:584 ++#: objcopy.c:614 +#, c-format +msgid " Removes symbols and sections from files\n" +msgstr "" + -+#: objcopy.c:586 ++#: objcopy.c:616 +#, c-format +msgid "" +" -I --input-target= Assume input file is in format \n" @@ -113368,10 +115038,16 @@ index 0000000..0d08397 +"\n" +" -p --preserve-dates Copy modified/access timestamps to the " +"output\n" ++msgstr "" ++ ++#: objcopy.c:634 ++#, c-format ++msgid "" +" -R --remove-section= Remove section from the output\n" +" -s --strip-all Remove all symbol and relocation " +"information\n" +" -g -S -d --strip-debug Remove all debugging symbols & sections\n" ++" --strip-dwo Remove all DWO sections\n" +" --strip-unneeded Remove all symbols not needed by " +"relocations\n" +" --only-keep-debug Strip everything but the debug " @@ -113390,361 +115066,402 @@ index 0000000..0d08397 +" -o Place stripped output into \n" +msgstr "" + -+#: objcopy.c:659 ++#: objcopy.c:706 +#, c-format +msgid "unrecognized section flag `%s'" +msgstr "" + -+#: objcopy.c:660 ++#: objcopy.c:707 +#, c-format +msgid "supported flags: %s" +msgstr "" + -+#: objcopy.c:761 ++#: objcopy.c:763 ++#, c-format ++msgid "error: %s both copied and removed" ++msgstr "" ++ ++#: objcopy.c:769 ++#, c-format ++msgid "error: %s both sets and alters VMA" ++msgstr "" ++ ++#: objcopy.c:775 ++#, c-format ++msgid "error: %s both sets and alters LMA" ++msgstr "" ++ ++#: objcopy.c:869 +#, c-format +msgid "cannot open '%s': %s" +msgstr "" + -+#: objcopy.c:764 objcopy.c:3417 ++#: objcopy.c:872 objcopy.c:3701 +#, c-format +msgid "%s: fread failed" +msgstr "" + -+#: objcopy.c:837 ++#: objcopy.c:945 +#, c-format +msgid "%s:%d: Ignoring rubbish found on this line" +msgstr "" + -+#: objcopy.c:1153 ++#: objcopy.c:1063 ++#, c-format ++msgid "error: section %s matches both remove and copy options" ++msgstr "" ++ ++#: objcopy.c:1292 +#, c-format +msgid "not stripping symbol `%s' because it is named in a relocation" +msgstr "" + -+#: objcopy.c:1236 ++#: objcopy.c:1375 +#, c-format +msgid "%s: Multiple redefinition of symbol \"%s\"" +msgstr "" + -+#: objcopy.c:1240 ++#: objcopy.c:1379 +#, c-format +msgid "%s: Symbol \"%s\" is target of more than one redefinition" +msgstr "" + -+#: objcopy.c:1268 ++#: objcopy.c:1407 +#, c-format +msgid "couldn't open symbol redefinition file %s (error: %s)" +msgstr "" + -+#: objcopy.c:1346 ++#: objcopy.c:1485 +#, c-format +msgid "%s:%d: garbage found at end of line" +msgstr "" + -+#: objcopy.c:1349 ++#: objcopy.c:1488 +#, c-format +msgid "%s:%d: missing new symbol name" +msgstr "" + -+#: objcopy.c:1359 ++#: objcopy.c:1498 +#, c-format +msgid "%s:%d: premature end of file" +msgstr "" + -+#: objcopy.c:1385 ++#: objcopy.c:1524 +#, c-format +msgid "stat returns negative size for `%s'" +msgstr "" + -+#: objcopy.c:1397 ++#: objcopy.c:1536 +#, c-format +msgid "copy from `%s' [unknown] to `%s' [unknown]\n" +msgstr "" + -+#: objcopy.c:1454 ++#: objcopy.c:1593 +msgid "Unable to change endianness of input file(s)" +msgstr "" + -+#: objcopy.c:1463 ++#: objcopy.c:1602 +#, c-format +msgid "copy from `%s' [%s] to `%s' [%s]\n" +msgstr "" + -+#: objcopy.c:1512 ++#: objcopy.c:1651 +#, c-format +msgid "Input file `%s' ignores binary architecture parameter." +msgstr "" + -+#: objcopy.c:1520 ++#: objcopy.c:1659 +#, c-format +msgid "Unable to recognise the format of the input file `%s'" +msgstr "" + -+#: objcopy.c:1523 ++#: objcopy.c:1662 +#, c-format +msgid "Output file cannot represent architecture `%s'" +msgstr "" + -+#: objcopy.c:1586 ++#: objcopy.c:1725 +#, c-format +msgid "warning: file alignment (0x%s) > section alignment (0x%s)" +msgstr "" + -+#: objcopy.c:1645 ++#: objcopy.c:1783 +#, c-format +msgid "can't add section '%s'" +msgstr "" + -+#: objcopy.c:1659 ++#: objcopy.c:1797 +#, c-format +msgid "can't create section `%s'" +msgstr "" + -+#: objcopy.c:1705 ++#: objcopy.c:1847 ++#, c-format ++msgid "can't dump section '%s' - it does not exist" ++msgstr "" ++ ++#: objcopy.c:1855 ++msgid "can't dump section - it has no contents" ++msgstr "" ++ ++#: objcopy.c:1863 ++msgid "can't dump section - it is empty" ++msgstr "" ++ ++#: objcopy.c:1872 ++msgid "could not open section dump file" ++msgstr "" ++ ++#: objcopy.c:1881 ++msgid "could not retrieve section contents" ++msgstr "" ++ ++#: objcopy.c:1895 ++#, c-format ++msgid "%s: debuglink section already exists" ++msgstr "" ++ ++#: objcopy.c:1907 +#, c-format +msgid "cannot create debug link section `%s'" +msgstr "" + -+#: objcopy.c:1798 ++#: objcopy.c:2001 +msgid "Can't fill gap after section" +msgstr "" + -+#: objcopy.c:1822 ++#: objcopy.c:2025 +msgid "can't add padding" +msgstr "" + -+#: objcopy.c:1913 ++#: objcopy.c:2121 +#, c-format +msgid "cannot fill debug link section `%s'" +msgstr "" + -+#: objcopy.c:1976 ++#: objcopy.c:2184 +msgid "error copying private BFD data" +msgstr "" + -+#: objcopy.c:1987 ++#: objcopy.c:2195 +#, c-format +msgid "this target does not support %lu alternative machine codes" +msgstr "" + -+#: objcopy.c:1991 ++#: objcopy.c:2199 +msgid "treating that number as an absolute e_machine value instead" +msgstr "" + -+#: objcopy.c:1995 ++#: objcopy.c:2203 +msgid "ignoring the alternative value" +msgstr "" + -+#: objcopy.c:2027 objcopy.c:2063 ++#: objcopy.c:2235 objcopy.c:2277 +#, c-format +msgid "cannot create tempdir for archive copying (error: %s)" +msgstr "" + -+#: objcopy.c:2093 ++#: objcopy.c:2307 +msgid "Unable to recognise the format of file" +msgstr "" + -+#: objcopy.c:2220 ++#: objcopy.c:2434 +#, c-format +msgid "error: the input file '%s' is empty" +msgstr "" + -+#: objcopy.c:2364 ++#: objcopy.c:2578 +#, c-format +msgid "Multiple renames of section %s" +msgstr "" + -+#: objcopy.c:2415 ++#: objcopy.c:2629 +msgid "error in private header data" +msgstr "" + -+#: objcopy.c:2493 ++#: objcopy.c:2706 +msgid "failed to create output section" +msgstr "" + -+#: objcopy.c:2507 ++#: objcopy.c:2720 +msgid "failed to set size" +msgstr "" + -+#: objcopy.c:2521 ++#: objcopy.c:2739 +msgid "failed to set vma" +msgstr "" + -+#: objcopy.c:2546 ++#: objcopy.c:2764 +msgid "failed to set alignment" +msgstr "" + -+#: objcopy.c:2580 ++#: objcopy.c:2798 +msgid "failed to copy private data" +msgstr "" + -+#: objcopy.c:2662 ++#: objcopy.c:2895 +msgid "relocation count is negative" +msgstr "" + +#. User must pad the section up in order to do this. -+#: objcopy.c:2723 ++#: objcopy.c:2977 +#, c-format +msgid "" +"cannot reverse bytes: length of section %s must be evenly divisible by %d" +msgstr "" + -+#: objcopy.c:2909 ++#: objcopy.c:3169 +msgid "can't create debugging section" +msgstr "" + -+#: objcopy.c:2922 ++#: objcopy.c:3182 +msgid "can't set debugging section contents" +msgstr "" + -+#: objcopy.c:2930 ++#: objcopy.c:3190 +#, c-format +msgid "don't know how to write debugging information for %s" +msgstr "" + -+#: objcopy.c:3073 ++#: objcopy.c:3351 +msgid "could not create temporary file to hold stripped copy" +msgstr "" + -+#: objcopy.c:3145 ++#: objcopy.c:3423 +#, c-format +msgid "%s: bad version in PE subsystem" +msgstr "" + -+#: objcopy.c:3175 ++#: objcopy.c:3453 +#, c-format +msgid "unknown PE subsystem: %s" +msgstr "" + -+#: objcopy.c:3237 ++#: objcopy.c:3514 +msgid "byte number must be non-negative" +msgstr "" + -+#: objcopy.c:3243 ++#: objcopy.c:3520 +#, c-format +msgid "architecture %s unknown" +msgstr "" + -+#: objcopy.c:3251 ++#: objcopy.c:3528 +msgid "interleave must be positive" +msgstr "" + -+#: objcopy.c:3260 ++#: objcopy.c:3537 +msgid "interleave width must be positive" +msgstr "" + -+#: objcopy.c:3280 objcopy.c:3288 -+#, c-format -+msgid "%s both copied and removed" -+msgstr "" -+ -+#: objcopy.c:3387 objcopy.c:3467 objcopy.c:3575 objcopy.c:3606 objcopy.c:3630 -+#: objcopy.c:3634 objcopy.c:3654 ++#: objcopy.c:3671 objcopy.c:3723 objcopy.c:3774 objcopy.c:3890 objcopy.c:3922 ++#: objcopy.c:3945 objcopy.c:3949 objcopy.c:3969 +#, c-format +msgid "bad format for %s" +msgstr "" + -+#: objcopy.c:3399 ++#: objcopy.c:3683 +#, c-format +msgid "cannot open: %s: %s" +msgstr "" + -+#: objcopy.c:3544 ++#: objcopy.c:3859 +#, c-format +msgid "Warning: truncating gap-fill from 0x%s to 0x%x" +msgstr "" + -+#: objcopy.c:3705 ++#: objcopy.c:4020 +#, c-format +msgid "unknown long section names option '%s'" +msgstr "" + -+#: objcopy.c:3723 ++#: objcopy.c:4038 +msgid "unable to parse alternative machine code" +msgstr "" + -+#: objcopy.c:3768 ++#: objcopy.c:4087 +msgid "number of bytes to reverse must be positive and even" +msgstr "" + -+#: objcopy.c:3771 ++#: objcopy.c:4090 +#, c-format +msgid "Warning: ignoring previous --reverse-bytes value of %d" +msgstr "" + -+#: objcopy.c:3786 ++#: objcopy.c:4105 +#, c-format +msgid "%s: invalid reserve value for --heap" +msgstr "" + -+#: objcopy.c:3792 ++#: objcopy.c:4111 +#, c-format +msgid "%s: invalid commit value for --heap" +msgstr "" + -+#: objcopy.c:3817 ++#: objcopy.c:4136 +#, c-format +msgid "%s: invalid reserve value for --stack" +msgstr "" + -+#: objcopy.c:3823 ++#: objcopy.c:4142 +#, c-format +msgid "%s: invalid commit value for --stack" +msgstr "" + -+#: objcopy.c:3852 ++#: objcopy.c:4171 +msgid "interleave start byte must be set with --byte" +msgstr "" + -+#: objcopy.c:3855 ++#: objcopy.c:4174 +msgid "byte number must be less than interleave" +msgstr "" + -+#: objcopy.c:3858 ++#: objcopy.c:4177 +msgid "interleave width must be less than or equal to interleave - byte`" +msgstr "" + -+#: objcopy.c:3885 ++#: objcopy.c:4206 +#, c-format +msgid "unknown input EFI target: %s" +msgstr "" + -+#: objcopy.c:3916 ++#: objcopy.c:4237 +#, c-format +msgid "unknown output EFI target: %s" +msgstr "" + -+#: objcopy.c:3929 ++#: objcopy.c:4250 +#, c-format +msgid "warning: could not locate '%s'. System error message: %s" +msgstr "" + -+#: objcopy.c:3941 ++#: objcopy.c:4262 +#, c-format +msgid "" +"warning: could not create temporary file whilst copying '%s', (error: %s)" +msgstr "" + -+#: objcopy.c:3969 objcopy.c:3983 ++#: objcopy.c:4292 objcopy.c:4306 +#, c-format +msgid "%s %s%c0x%s never used" +msgstr "" + -+#: objdump.c:201 ++#: objdump.c:198 +#, c-format +msgid "Usage: %s \n" +msgstr "" + -+#: objdump.c:202 ++#: objdump.c:199 +#, c-format +msgid " Display information from object .\n" +msgstr "" + -+#: objdump.c:203 ++#: objdump.c:200 +#, c-format +msgid " At least one of the following switches must be given:\n" +msgstr "" + -+#: objdump.c:204 ++#: objdump.c:201 +#, c-format +msgid "" +" -a, --archive-headers Display archive header information\n" @@ -113767,7 +115484,8 @@ index 0000000..0d08397 +" --dwarf[=rawline,=decodedline,=info,=abbrev,=pubnames,=aranges,=macro," +"=frames,\n" +" =frames-interp,=str,=loc,=Ranges,=pubtypes,\n" -+" =gdb_index,=trace_info,=trace_abbrev,=trace_aranges]\n" ++" =gdb_index,=trace_info,=trace_abbrev,=trace_aranges,\n" ++" =addr,=cu_index]\n" +" Display DWARF info in the file\n" +" -t, --syms Display the contents of the symbol table(s)\n" +" -T, --dynamic-syms Display the contents of the dynamic symbol table\n" @@ -113780,14 +115498,14 @@ index 0000000..0d08397 +" -H, --help Display this information\n" +msgstr "" + -+#: objdump.c:236 ++#: objdump.c:234 +#, c-format +msgid "" +"\n" +" The following switches are optional:\n" +msgstr "" + -+#: objdump.c:237 ++#: objdump.c:235 +#, c-format +msgid "" +" -b, --target=BFDNAME Specify the target object format as " @@ -113829,13 +115547,15 @@ index 0000000..0d08397 +" --prefix-strip=LEVEL Strip initial directory names for -S\n" +msgstr "" + -+#: objdump.c:263 ++#: objdump.c:261 +#, c-format +msgid "" +" --dwarf-depth=N Do not display DIEs at depth N or greater\n" +" --dwarf-start=N Display DIEs starting with N, at the same " +"depth\n" +" or deeper\n" ++" --dwarf-check Make additional dwarf internal consistency " ++"checks. \n" +"\n" +msgstr "" + @@ -113846,189 +115566,395 @@ index 0000000..0d08397 +"Options supported for -P/--private switch:\n" +msgstr "" + -+#: objdump.c:426 ++#: objdump.c:428 +#, c-format +msgid "section '%s' mentioned in a -j option, but not found in any input file" +msgstr "" + -+#: objdump.c:530 ++#: objdump.c:532 +#, c-format +msgid "Sections:\n" +msgstr "" + -+#: objdump.c:533 objdump.c:537 ++#: objdump.c:535 objdump.c:539 +#, c-format +msgid "Idx Name Size VMA LMA File off Algn" +msgstr "" + -+#: objdump.c:539 ++#: objdump.c:541 +#, c-format +msgid "" +"Idx Name Size VMA LMA File off " +"Algn" +msgstr "" + -+#: objdump.c:543 ++#: objdump.c:545 +#, c-format +msgid " Flags" +msgstr "" + -+#: objdump.c:586 ++#: objdump.c:588 +#, c-format +msgid "%s: not a dynamic object" +msgstr "" + -+#: objdump.c:1012 objdump.c:1036 ++#: objdump.c:1014 objdump.c:1038 +#, c-format +msgid " (File Offset: 0x%lx)" +msgstr "" + -+#: objdump.c:1662 ++#: objdump.c:1680 +#, c-format +msgid "disassemble_fn returned length %d" +msgstr "" + -+#: objdump.c:1967 ++#: objdump.c:1994 +#, c-format +msgid "" +"\n" +"Disassembly of section %s:\n" +msgstr "" + -+#: objdump.c:2143 ++#: objdump.c:2171 +#, c-format +msgid "can't use supplied machine %s" +msgstr "" + -+#: objdump.c:2162 ++#: objdump.c:2190 +#, c-format +msgid "can't disassemble for architecture %s\n" +msgstr "" + -+#: objdump.c:2242 objdump.c:2265 ++#: objdump.c:2270 objdump.c:2287 +#, c-format +msgid "" +"\n" +"Can't get contents for section '%s'.\n" +msgstr "" + -+#: objdump.c:2406 ++#: objdump.c:2432 +#, c-format +msgid "" +"No %s section present\n" +"\n" +msgstr "" + -+#: objdump.c:2415 ++#: objdump.c:2441 +#, c-format +msgid "reading %s section of %s failed: %s" +msgstr "" + -+#: objdump.c:2459 ++#: objdump.c:2485 +#, c-format +msgid "" +"Contents of %s section:\n" +"\n" +msgstr "" + -+#: objdump.c:2590 ++#: objdump.c:2616 +#, c-format +msgid "architecture: %s, " +msgstr "" + -+#: objdump.c:2593 ++#: objdump.c:2619 +#, c-format +msgid "flags 0x%08x:\n" +msgstr "" + -+#: objdump.c:2607 ++#: objdump.c:2633 +#, c-format +msgid "" +"\n" +"start address 0x" +msgstr "" + -+#: objdump.c:2633 ++#: objdump.c:2659 +msgid "option -P/--private not supported by this file" +msgstr "" + -+#: objdump.c:2657 ++#: objdump.c:2683 +#, c-format +msgid "target specific dump '%s' not supported" +msgstr "" + -+#: objdump.c:2721 ++#: objdump.c:2747 +#, c-format +msgid "Contents of section %s:" +msgstr "" + -+#: objdump.c:2723 ++#: objdump.c:2749 +#, c-format +msgid " (Starting at file offset: 0x%lx)" +msgstr "" + -+#: objdump.c:2729 ++#: objdump.c:2755 +msgid "Reading section failed" +msgstr "" + -+#: objdump.c:2832 ++#: objdump.c:2858 +#, c-format +msgid "no symbols\n" +msgstr "" + -+#: objdump.c:2839 ++#: objdump.c:2865 +#, c-format +msgid "no information for symbol number %ld\n" +msgstr "" + -+#: objdump.c:2842 ++#: objdump.c:2868 +#, c-format +msgid "could not determine the type of symbol number %ld\n" +msgstr "" + -+#: objdump.c:3163 ++#: objdump.c:3206 +#, c-format +msgid "" +"\n" +"%s: file format %s\n" +msgstr "" + -+#: objdump.c:3223 ++#: objdump.c:3268 +#, c-format +msgid "%s: printing debugging information failed" +msgstr "" + -+#: objdump.c:3327 ++#: objdump.c:3359 +#, c-format +msgid "In archive %s:\n" +msgstr "" + -+#: objdump.c:3438 ++#: objdump.c:3361 ++#, c-format ++msgid "In nested archive %s:\n" ++msgstr "" ++ ++#: objdump.c:3494 +msgid "error: the start address should be before the end address" +msgstr "" + -+#: objdump.c:3443 ++#: objdump.c:3499 +msgid "error: the stop address should be after the start address" +msgstr "" + -+#: objdump.c:3455 ++#: objdump.c:3511 +msgid "error: prefix strip must be non-negative" +msgstr "" + -+#: objdump.c:3460 ++#: objdump.c:3516 +msgid "error: instruction width must be positive" +msgstr "" + -+#: objdump.c:3469 ++#: objdump.c:3525 +msgid "unrecognized -E option" +msgstr "" + -+#: objdump.c:3480 ++#: objdump.c:3536 +#, c-format +msgid "unrecognized --endian type `%s'" +msgstr "" + -+#: od-xcoff.c:75 ++#: od-macho.c:62 ++#, c-format ++msgid "" ++"For Mach-O files:\n" ++" header Display the file header\n" ++" section Display the segments and sections commands\n" ++" map Display the section map\n" ++" load Display the load commands\n" ++" dysymtab Display the dynamic symbol table\n" ++" codesign Display code signature\n" ++" seg_split_info Display segment split info\n" ++msgstr "" ++ ++#: od-macho.c:265 ++msgid "Mach-O header:\n" ++msgstr "" ++ ++#: od-macho.c:266 ++#, c-format ++msgid " magic : %08lx\n" ++msgstr "" ++ ++#: od-macho.c:267 ++#, c-format ++msgid " cputype : %08lx (%s)\n" ++msgstr "" ++ ++#: od-macho.c:269 ++#, c-format ++msgid " cpusubtype: %08lx\n" ++msgstr "" ++ ++#: od-macho.c:270 ++#, c-format ++msgid " filetype : %08lx (%s)\n" ++msgstr "" ++ ++#: od-macho.c:273 ++#, c-format ++msgid " ncmds : %08lx (%lu)\n" ++msgstr "" ++ ++#: od-macho.c:274 ++#, c-format ++msgid " sizeofcmds: %08lx\n" ++msgstr "" ++ ++#: od-macho.c:275 ++#, c-format ++msgid " flags : %08lx (" ++msgstr "" ++ ++#: od-macho.c:277 ++msgid ")\n" ++msgstr "" ++ ++#: od-macho.c:278 ++#, c-format ++msgid " reserved : %08x\n" ++msgstr "" ++ ++#: od-macho.c:288 ++msgid "Segments and Sections:\n" ++msgstr "" ++ ++#: od-macho.c:289 ++msgid " #: Segment name Section name Address\n" ++msgstr "" ++ ++#: od-macho.c:684 od-macho.c:691 od-macho.c:765 od-macho.c:817 ++#, c-format ++msgid " [bad block length]\n" ++msgstr "" ++ ++#: od-macho.c:688 ++#, c-format ++msgid " %u index entries:\n" ++msgstr "" ++ ++#: od-macho.c:701 ++#, c-format ++msgid " index entry %u: type: %08x, offset: %08x\n" ++msgstr "" ++ ++#: od-macho.c:772 ++#, c-format ++msgid " version: %08x\n" ++msgstr "" ++ ++#: od-macho.c:773 ++#, c-format ++msgid " flags: %08x\n" ++msgstr "" ++ ++#: od-macho.c:774 ++#, c-format ++msgid " hash offset: %08x\n" ++msgstr "" ++ ++#: od-macho.c:776 ++#, c-format ++msgid " ident offset: %08x (- %08x)\n" ++msgstr "" ++ ++#: od-macho.c:778 ++#, c-format ++msgid " identity: %s\n" ++msgstr "" ++ ++#: od-macho.c:779 ++#, c-format ++msgid " nbr special slots: %08x (at offset %08x)\n" ++msgstr "" ++ ++#: od-macho.c:782 ++#, c-format ++msgid " nbr code slots: %08x\n" ++msgstr "" ++ ++#: od-macho.c:783 ++#, c-format ++msgid " code limit: %08x\n" ++msgstr "" ++ ++#: od-macho.c:784 ++#, c-format ++msgid " hash size: %02x\n" ++msgstr "" ++ ++#: od-macho.c:785 ++#, c-format ++msgid " hash type: %02x (%s)\n" ++msgstr "" ++ ++#: od-macho.c:788 ++#, c-format ++msgid " spare1: %02x\n" ++msgstr "" ++ ++#: od-macho.c:789 ++#, c-format ++msgid " page size: %02x\n" ++msgstr "" ++ ++#: od-macho.c:790 ++#, c-format ++msgid " spare2: %08x\n" ++msgstr "" ++ ++#: od-macho.c:792 ++#, c-format ++msgid " scatter offset: %08x\n" ++msgstr "" ++ ++#: od-macho.c:804 ++#, c-format ++msgid " [truncated block]\n" ++msgstr "" ++ ++#: od-macho.c:812 ++#, c-format ++msgid " magic : %08x (%s)\n" ++msgstr "" ++ ++#: od-macho.c:814 ++#, c-format ++msgid " length: %08x\n" ++msgstr "" ++ ++#: od-macho.c:845 ++msgid "cannot read code signature data" ++msgstr "" ++ ++#: od-macho.c:873 ++msgid "cannot read segment split info" ++msgstr "" ++ ++#: od-macho.c:879 ++msgid "segment split info is not nul terminated" ++msgstr "" ++ ++#: od-macho.c:887 ++#, c-format ++msgid " 32 bit pointers:\n" ++msgstr "" ++ ++#: od-macho.c:890 ++#, c-format ++msgid " 64 bit pointers:\n" ++msgstr "" ++ ++#: od-macho.c:893 ++#, c-format ++msgid " PPC hi-16:\n" ++msgstr "" ++ ++#: od-macho.c:896 ++#, c-format ++msgid " Unhandled location type %u\n" ++msgstr "" ++ ++#: od-xcoff.c:77 +#, c-format +msgid "" +"For XCOFF files:\n" @@ -114043,387 +115969,428 @@ index 0000000..0d08397 +" typchk Display type-check section\n" +" traceback Display traceback tags\n" +" toc Display toc symbols\n" -+msgstr "" -+ -+#: od-xcoff.c:416 -+#, c-format -+msgid " nbr sections: %d\n" -+msgstr "" -+ -+#: od-xcoff.c:417 -+#, c-format -+msgid " time and date: 0x%08x - " ++" ldinfo Display loader info in core files\n" +msgstr "" + +#: od-xcoff.c:419 +#, c-format ++msgid " nbr sections: %d\n" ++msgstr "" ++ ++#: od-xcoff.c:420 ++#, c-format ++msgid " time and date: 0x%08x - " ++msgstr "" ++ ++#: od-xcoff.c:422 ++#, c-format +msgid "not set\n" +msgstr "" + -+#: od-xcoff.c:426 -+#, c-format -+msgid " symbols off: 0x%08x\n" -+msgstr "" -+ -+#: od-xcoff.c:427 -+#, c-format -+msgid " nbr symbols: %d\n" -+msgstr "" -+ -+#: od-xcoff.c:428 -+#, c-format -+msgid " opt hdr sz: %d\n" -+msgstr "" -+ +#: od-xcoff.c:429 +#, c-format -+msgid " flags: 0x%04x " ++msgid " symbols off: 0x%08x\n" +msgstr "" + -+#: od-xcoff.c:443 ++#: od-xcoff.c:430 +#, c-format -+msgid "Auxiliary header:\n" ++msgid " nbr symbols: %d\n" ++msgstr "" ++ ++#: od-xcoff.c:431 ++#, c-format ++msgid " opt hdr sz: %d\n" ++msgstr "" ++ ++#: od-xcoff.c:432 ++#, c-format ++msgid " flags: 0x%04x " +msgstr "" + +#: od-xcoff.c:446 +#, c-format ++msgid "Auxiliary header:\n" ++msgstr "" ++ ++#: od-xcoff.c:449 ++#, c-format +msgid " No aux header\n" +msgstr "" + -+#: od-xcoff.c:451 ++#: od-xcoff.c:454 +#, c-format -+msgid "warning: optionnal header size too large (> %d)\n" ++msgid "warning: optional header size too large (> %d)\n" +msgstr "" + -+#: od-xcoff.c:457 ++#: od-xcoff.c:460 +msgid "cannot read auxhdr" +msgstr "" + -+#: od-xcoff.c:522 ++#: od-xcoff.c:525 +#, c-format +msgid "Section headers (at %u+%u=0x%08x to 0x%08x):\n" +msgstr "" + -+#: od-xcoff.c:527 ++#: od-xcoff.c:530 +#, c-format +msgid " No section header\n" +msgstr "" + -+#: od-xcoff.c:532 od-xcoff.c:544 od-xcoff.c:599 ++#: od-xcoff.c:535 od-xcoff.c:547 od-xcoff.c:602 +msgid "cannot read section header" +msgstr "" + -+#: od-xcoff.c:558 ++#: od-xcoff.c:561 +#, c-format +msgid " Flags: %08x " +msgstr "" + -+#: od-xcoff.c:566 ++#: od-xcoff.c:569 +#, c-format +msgid "overflow - nreloc: %u, nlnno: %u\n" +msgstr "" + -+#: od-xcoff.c:587 od-xcoff.c:922 od-xcoff.c:978 ++#: od-xcoff.c:590 od-xcoff.c:925 od-xcoff.c:981 +msgid "cannot read section headers" +msgstr "" + -+#: od-xcoff.c:646 ++#: od-xcoff.c:649 +msgid "cannot read strings table length" +msgstr "" + -+#: od-xcoff.c:662 ++#: od-xcoff.c:665 +msgid "cannot read strings table" +msgstr "" + -+#: od-xcoff.c:670 ++#: od-xcoff.c:673 +msgid "cannot read symbol table" +msgstr "" + -+#: od-xcoff.c:685 ++#: od-xcoff.c:688 +msgid "cannot read symbol entry" +msgstr "" + -+#: od-xcoff.c:720 ++#: od-xcoff.c:723 +msgid "cannot read symbol aux entry" +msgstr "" + -+#: od-xcoff.c:742 ++#: od-xcoff.c:745 +#, c-format +msgid "Symbols table (strtable at 0x%08x)" +msgstr "" + -+#: od-xcoff.c:747 ++#: od-xcoff.c:750 +#, c-format +msgid "" +":\n" +" No symbols\n" +msgstr "" + -+#: od-xcoff.c:753 ++#: od-xcoff.c:756 +#, c-format +msgid " (no strings):\n" +msgstr "" + -+#: od-xcoff.c:755 ++#: od-xcoff.c:758 +#, c-format +msgid " (strings size: %08x):\n" +msgstr "" + +#. Translators: 'sc' is for storage class, 'off' for offset. -+#: od-xcoff.c:769 ++#: od-xcoff.c:772 +#, c-format +msgid " # sc value section type aux name/off\n" +msgstr "" + +#. Section length, number of relocs and line number. -+#: od-xcoff.c:821 ++#: od-xcoff.c:824 +#, c-format +msgid " scnlen: %08x nreloc: %-6u nlinno: %-6u\n" +msgstr "" + +#. Section length and number of relocs. -+#: od-xcoff.c:828 ++#: od-xcoff.c:831 +#, c-format +msgid " scnlen: %08x nreloc: %-6u\n" +msgstr "" + -+#: od-xcoff.c:891 ++#: od-xcoff.c:894 +#, c-format +msgid "offset: %08x" +msgstr "" + -+#: od-xcoff.c:934 ++#: od-xcoff.c:937 +#, c-format +msgid "Relocations for %s (%u)\n" +msgstr "" + -+#: od-xcoff.c:937 ++#: od-xcoff.c:940 +msgid "cannot read relocations" +msgstr "" + -+#: od-xcoff.c:950 ++#: od-xcoff.c:953 +msgid "cannot read relocation entry" +msgstr "" + -+#: od-xcoff.c:990 ++#: od-xcoff.c:993 +#, c-format +msgid "Line numbers for %s (%u)\n" +msgstr "" + -+#: od-xcoff.c:993 ++#: od-xcoff.c:996 +msgid "cannot read line numbers" +msgstr "" + +#. Line number, symbol index and physical address. -+#: od-xcoff.c:997 ++#: od-xcoff.c:1000 +#, c-format +msgid "lineno symndx/paddr\n" +msgstr "" + -+#: od-xcoff.c:1005 ++#: od-xcoff.c:1008 +msgid "cannot read line number entry" +msgstr "" + -+#: od-xcoff.c:1048 ++#: od-xcoff.c:1051 +#, c-format +msgid "no .loader section in file\n" +msgstr "" + -+#: od-xcoff.c:1054 ++#: od-xcoff.c:1057 +#, c-format +msgid "section .loader is too short\n" +msgstr "" + -+#: od-xcoff.c:1061 ++#: od-xcoff.c:1064 +#, c-format +msgid "Loader header:\n" +msgstr "" + -+#: od-xcoff.c:1063 ++#: od-xcoff.c:1066 +#, c-format +msgid " version: %u\n" +msgstr "" + -+#: od-xcoff.c:1066 ++#: od-xcoff.c:1069 +#, c-format +msgid " Unhandled version\n" +msgstr "" + -+#: od-xcoff.c:1071 ++#: od-xcoff.c:1074 +#, c-format +msgid " nbr symbols: %u\n" +msgstr "" + -+#: od-xcoff.c:1073 ++#: od-xcoff.c:1076 +#, c-format +msgid " nbr relocs: %u\n" +msgstr "" + +#. Import string table length. -+#: od-xcoff.c:1075 ++#: od-xcoff.c:1078 +#, c-format +msgid " import strtab len: %u\n" +msgstr "" + -+#: od-xcoff.c:1078 ++#: od-xcoff.c:1081 +#, c-format +msgid " nbr import files: %u\n" +msgstr "" + -+#: od-xcoff.c:1080 ++#: od-xcoff.c:1083 +#, c-format +msgid " import file off: %u\n" +msgstr "" + -+#: od-xcoff.c:1082 ++#: od-xcoff.c:1085 +#, c-format +msgid " string table len: %u\n" +msgstr "" + -+#: od-xcoff.c:1084 ++#: od-xcoff.c:1087 +#, c-format +msgid " string table off: %u\n" +msgstr "" + -+#: od-xcoff.c:1087 ++#: od-xcoff.c:1090 +#, c-format +msgid "Dynamic symbols:\n" +msgstr "" + -+#: od-xcoff.c:1094 ++#: od-xcoff.c:1097 +#, c-format +msgid " %4u %08x %3u " +msgstr "" + -+#: od-xcoff.c:1107 ++#: od-xcoff.c:1110 +#, c-format +msgid " %3u %3u " +msgstr "" + -+#: od-xcoff.c:1116 ++#: od-xcoff.c:1119 +#, c-format +msgid "(bad offset: %u)" +msgstr "" + -+#: od-xcoff.c:1123 ++#: od-xcoff.c:1126 +#, c-format +msgid "Dynamic relocs:\n" +msgstr "" + -+#: od-xcoff.c:1163 ++#: od-xcoff.c:1166 +#, c-format +msgid "Import files:\n" +msgstr "" + -+#: od-xcoff.c:1195 ++#: od-xcoff.c:1198 +#, c-format +msgid "no .except section in file\n" +msgstr "" + -+#: od-xcoff.c:1203 ++#: od-xcoff.c:1206 +#, c-format +msgid "Exception table:\n" +msgstr "" + -+#: od-xcoff.c:1238 ++#: od-xcoff.c:1241 +#, c-format +msgid "no .typchk section in file\n" +msgstr "" + -+#: od-xcoff.c:1245 ++#: od-xcoff.c:1248 +#, c-format +msgid "Type-check section:\n" +msgstr "" + -+#: od-xcoff.c:1292 ++#: od-xcoff.c:1295 +#, c-format +msgid " address beyond section size\n" +msgstr "" + -+#: od-xcoff.c:1302 ++#: od-xcoff.c:1305 +#, c-format +msgid " tags at %08x\n" +msgstr "" + -+#: od-xcoff.c:1380 ++#: od-xcoff.c:1383 +#, c-format +msgid " number of CTL anchors: %u\n" +msgstr "" + -+#: od-xcoff.c:1399 ++#: od-xcoff.c:1402 +#, c-format +msgid " Name (len: %u): " +msgstr "" + -+#: od-xcoff.c:1402 ++#: od-xcoff.c:1405 +#, c-format +msgid "[truncated]\n" +msgstr "" + -+#: od-xcoff.c:1421 ++#: od-xcoff.c:1424 +#, c-format +msgid " (end of tags at %08x)\n" +msgstr "" + -+#: od-xcoff.c:1424 ++#: od-xcoff.c:1427 +#, c-format +msgid " no tags found\n" +msgstr "" + -+#: od-xcoff.c:1428 ++#: od-xcoff.c:1431 +#, c-format +msgid " Truncated .text section\n" +msgstr "" + -+#: od-xcoff.c:1513 ++#: od-xcoff.c:1516 +#, c-format +msgid "TOC:\n" +msgstr "" + -+#: od-xcoff.c:1556 ++#: od-xcoff.c:1559 +#, c-format +msgid "Nbr entries: %-8u Size: %08x (%u)\n" +msgstr "" + -+#: od-xcoff.c:1640 ++#: od-xcoff.c:1643 +msgid "cannot read header" +msgstr "" + -+#: od-xcoff.c:1648 ++#: od-xcoff.c:1651 +#, c-format +msgid "File header:\n" +msgstr "" + -+#: od-xcoff.c:1649 ++#: od-xcoff.c:1652 +#, c-format +msgid " magic: 0x%04x (0%04o) " +msgstr "" + -+#: od-xcoff.c:1653 ++#: od-xcoff.c:1656 +#, c-format +msgid "(WRMAGIC: writable text segments)" +msgstr "" + -+#: od-xcoff.c:1656 ++#: od-xcoff.c:1659 +#, c-format +msgid "(ROMAGIC: readonly sharablee text segments)" +msgstr "" + -+#: od-xcoff.c:1659 ++#: od-xcoff.c:1662 +#, c-format +msgid "(TOCMAGIC: readonly text segments and TOC)" +msgstr "" + -+#: od-xcoff.c:1662 ++#: od-xcoff.c:1665 +#, c-format +msgid "unknown magic" +msgstr "" + -+#: od-xcoff.c:1669 ++#: od-xcoff.c:1673 od-xcoff.c:1813 +#, c-format +msgid " Unhandled magic\n" +msgstr "" + ++#: od-xcoff.c:1737 ++msgid "cannot read loader info table" ++msgstr "" ++ ++#: od-xcoff.c:1769 ++#, c-format ++msgid "" ++"\n" ++"ldinfo dump not supported in 32 bits environments\n" ++msgstr "" ++ ++#: od-xcoff.c:1787 ++msgid "cannot core read header" ++msgstr "" ++ ++#: od-xcoff.c:1794 ++#, c-format ++msgid "Core header:\n" ++msgstr "" ++ ++#: od-xcoff.c:1795 ++#, c-format ++msgid " version: 0x%08x " ++msgstr "" ++ ++#: od-xcoff.c:1799 ++#, c-format ++msgid "(dumpx format - aix4.3 / 32 bits)" ++msgstr "" ++ ++#: od-xcoff.c:1802 ++#, c-format ++msgid "(dumpxx format - aix5.0 / 64 bits)" ++msgstr "" ++ ++#: od-xcoff.c:1805 ++#, c-format ++msgid "unknown format" ++msgstr "" ++ +#: rclex.c:197 +msgid "invalid value specified for pragma code_page.\n" +msgstr "" @@ -114463,250 +116430,256 @@ index 0000000..0d08397 +msgid "Last stabs entries before error:\n" +msgstr "" + -+#: readelf.c:268 ++#: readelf.c:277 +msgid "" +msgstr "" + -+#: readelf.c:269 ++#: readelf.c:278 +msgid "" +msgstr "" + -+#: readelf.c:270 readelf.c:5083 readelf.c:5594 readelf.c:8132 readelf.c:8250 -+#: readelf.c:9233 readelf.c:9327 readelf.c:9388 readelf.c:12391 -+#: readelf.c:12394 -+msgid "" -+msgstr "" -+ -+#: readelf.c:309 ++#: readelf.c:318 +#, c-format +msgid "Unable to seek to 0x%lx for %s\n" +msgstr "" + -+#: readelf.c:324 ++#: readelf.c:333 +#, c-format +msgid "Out of memory allocating 0x%lx bytes for %s\n" +msgstr "" + -+#: readelf.c:334 ++#: readelf.c:343 +#, c-format +msgid "Unable to read in 0x%lx bytes of %s\n" +msgstr "" + -+#: readelf.c:638 ++#: readelf.c:678 +msgid "Don't know about relocations on this machine architecture\n" +msgstr "" + -+#: readelf.c:659 readelf.c:757 ++#: readelf.c:699 readelf.c:797 +msgid "32-bit relocation data" +msgstr "" + -+#: readelf.c:671 readelf.c:701 readelf.c:768 readelf.c:797 ++#: readelf.c:711 readelf.c:741 readelf.c:808 readelf.c:837 +msgid "out of memory parsing relocs\n" +msgstr "" + -+#: readelf.c:689 readelf.c:786 ++#: readelf.c:729 readelf.c:826 +msgid "64-bit relocation data" +msgstr "" + -+#: readelf.c:902 ++#: readelf.c:953 +#, c-format +msgid "" +" Offset Info Type Sym. Value Symbol's Name + Addend\n" +msgstr "" + -+#: readelf.c:904 ++#: readelf.c:955 +#, c-format +msgid " Offset Info Type Sym.Value Sym. Name + Addend\n" +msgstr "" + -+#: readelf.c:909 ++#: readelf.c:960 +#, c-format +msgid " Offset Info Type Sym. Value Symbol's Name\n" +msgstr "" + -+#: readelf.c:911 ++#: readelf.c:962 +#, c-format +msgid " Offset Info Type Sym.Value Sym. Name\n" +msgstr "" + -+#: readelf.c:919 ++#: readelf.c:970 +#, c-format +msgid "" +" Offset Info Type Symbol's Value " +"Symbol's Name + Addend\n" +msgstr "" + -+#: readelf.c:921 ++#: readelf.c:972 +#, c-format +msgid "" +" Offset Info Type Sym. Value Sym. Name + " +"Addend\n" +msgstr "" + -+#: readelf.c:926 ++#: readelf.c:977 +#, c-format +msgid "" +" Offset Info Type Symbol's Value " +"Symbol's Name\n" +msgstr "" + -+#: readelf.c:928 ++#: readelf.c:979 +#, c-format +msgid "" +" Offset Info Type Sym. Value Sym. Name\n" +msgstr "" + -+#: readelf.c:1245 readelf.c:1405 readelf.c:1413 ++#: readelf.c:1327 readelf.c:1491 readelf.c:1499 +#, c-format +msgid "unrecognized: %-7lx" +msgstr "" + -+#: readelf.c:1270 ++#: readelf.c:1352 +#, c-format +msgid "" +msgstr "" + -+#: readelf.c:1277 ++#: readelf.c:1359 +#, c-format +msgid " bad symbol index: %08lx" +msgstr "" + -+#: readelf.c:1363 ++#: readelf.c:1445 +#, c-format +msgid "" +msgstr "" + -+#: readelf.c:1365 ++#: readelf.c:1447 +#, c-format +msgid "" +msgstr "" + -+#: readelf.c:1758 ++#: readelf.c:1858 +#, c-format +msgid "Processor Specific: %lx" +msgstr "" + -+#: readelf.c:1782 ++#: readelf.c:1882 +#, c-format +msgid "Operating System specific: %lx" +msgstr "" + -+#: readelf.c:1786 readelf.c:2858 ++#: readelf.c:1886 readelf.c:3315 +#, c-format +msgid ": %lx" +msgstr "" + -+#: readelf.c:1799 ++#: readelf.c:1899 +msgid "NONE (None)" +msgstr "" + -+#: readelf.c:1800 ++#: readelf.c:1900 +msgid "REL (Relocatable file)" +msgstr "" + -+#: readelf.c:1801 ++#: readelf.c:1901 +msgid "EXEC (Executable file)" +msgstr "" + -+#: readelf.c:1802 ++#: readelf.c:1902 +msgid "DYN (Shared object file)" +msgstr "" + -+#: readelf.c:1803 ++#: readelf.c:1903 +msgid "CORE (Core file)" +msgstr "" + -+#: readelf.c:1807 ++#: readelf.c:1907 +#, c-format +msgid "Processor Specific: (%x)" +msgstr "" + -+#: readelf.c:1809 ++#: readelf.c:1909 +#, c-format +msgid "OS Specific: (%x)" +msgstr "" + -+#: readelf.c:1811 ++#: readelf.c:1911 +#, c-format +msgid ": %x" +msgstr "" + -+#: readelf.c:1823 ++#: readelf.c:1923 +msgid "None" +msgstr "" + -+#: readelf.c:1994 ++#: readelf.c:2096 +#, c-format +msgid ": 0x%x" +msgstr "" + -+#: readelf.c:2180 ++#: readelf.c:2313 +msgid ", " +msgstr "" + -+#: readelf.c:2266 readelf.c:7485 ++#: readelf.c:2600 readelf.c:8067 +msgid "unknown" +msgstr "" + -+#: readelf.c:2267 ++#: readelf.c:2601 +msgid "unknown mac" +msgstr "" + -+#: readelf.c:2331 ++#: readelf.c:2665 +msgid ", relocatable" +msgstr "" + -+#: readelf.c:2334 ++#: readelf.c:2668 +msgid ", relocatable-lib" +msgstr "" + -+#: readelf.c:2357 ++#: readelf.c:2754 +msgid ", unknown v850 architecture variant" +msgstr "" + -+#: readelf.c:2414 ++#: readelf.c:2818 +msgid ", unknown CPU" +msgstr "" + -+#: readelf.c:2429 ++#: readelf.c:2833 +msgid ", unknown ABI" +msgstr "" + -+#: readelf.c:2452 readelf.c:2486 ++#: readelf.c:2856 readelf.c:2888 +msgid ", unknown ISA" +msgstr "" + -+#: readelf.c:2663 ++#: readelf.c:3034 ++msgid ": architecture variant: " ++msgstr "" ++ ++#: readelf.c:3053 ++msgid ": unknown" ++msgstr "" ++ ++#: readelf.c:3057 ++msgid ": unknown extra flag bits also present" ++msgstr "" ++ ++#: readelf.c:3103 +msgid "Standalone App" +msgstr "" + -+#: readelf.c:2672 ++#: readelf.c:3112 +msgid "Bare-metal C6000" +msgstr "" + -+#: readelf.c:2682 readelf.c:3471 readelf.c:3487 ++#: readelf.c:3122 readelf.c:3965 readelf.c:3981 +#, c-format +msgid "" +msgstr "" + +#. This message is probably going to be displayed in a 15 +#. character wide field, so put the hex value first. -+#: readelf.c:3108 ++#: readelf.c:3596 +#, c-format +msgid "%08x: " +msgstr "" + -+#: readelf.c:3163 ++#: readelf.c:3653 +#, c-format +msgid "Usage: readelf elf-file(s)\n" +msgstr "" + -+#: readelf.c:3164 ++#: readelf.c:3654 +#, c-format +msgid " Display information about the contents of ELF format files\n" +msgstr "" + -+#: readelf.c:3165 ++#: readelf.c:3655 +#, c-format +msgid "" +" Options are:\n" @@ -114727,8 +116700,7 @@ index 0000000..0d08397 +" -u --unwind Display the unwind info (if present)\n" +" -d --dynamic Display the dynamic section (if present)\n" +" -V --version-info Display the version sections (if present)\n" -+" -A --arch-specific Display architecture specific information (if " -+"any).\n" ++" -A --arch-specific Display architecture specific information (if any)\n" +" -c --archive-index Display the symbol/file index in an archive\n" +" -D --use-dynamic Use the dynamic section info when displaying " +"symbols\n" @@ -114745,11 +116717,12 @@ index 0000000..0d08397 +" --debug-dump[=rawline,=decodedline,=info,=abbrev,=pubnames,=aranges,=macro," +"=frames,\n" +" =frames-interp,=str,=loc,=Ranges,=pubtypes,\n" -+" =gdb_index,=trace_info,=trace_abbrev,=trace_aranges]\n" ++" =gdb_index,=trace_info,=trace_abbrev,=trace_aranges,\n" ++" =addr,=cu_index]\n" +" Display the contents of DWARF2 debug sections\n" +msgstr "" + -+#: readelf.c:3197 ++#: readelf.c:3688 +#, c-format +msgid "" +" --dwarf-depth=N Do not display DIEs at depth N or greater\n" @@ -114757,14 +116730,14 @@ index 0000000..0d08397 +" or deeper\n" +msgstr "" + -+#: readelf.c:3202 ++#: readelf.c:3693 +#, c-format +msgid "" +" -i --instruction-dump=\n" +" Disassemble the contents of section \n" +msgstr "" + -+#: readelf.c:3206 ++#: readelf.c:3697 +#, c-format +msgid "" +" -I --histogram Display histogram of bucket list lengths\n" @@ -114774,421 +116747,425 @@ index 0000000..0d08397 +" -v --version Display the version number of readelf\n" +msgstr "" + -+#: readelf.c:3235 readelf.c:3264 readelf.c:3268 readelf.c:13623 ++#: readelf.c:3726 readelf.c:3755 readelf.c:3759 readelf.c:14691 +msgid "Out of memory allocating dump request table.\n" +msgstr "" + -+#: readelf.c:3440 ++#: readelf.c:3934 +#, c-format +msgid "Invalid option '-%c'\n" +msgstr "" + -+#: readelf.c:3455 ++#: readelf.c:3949 +msgid "Nothing to do.\n" +msgstr "" + -+#: readelf.c:3467 readelf.c:3483 readelf.c:8068 ++#: readelf.c:3961 readelf.c:3977 readelf.c:8710 +msgid "none" +msgstr "" + -+#: readelf.c:3484 ++#: readelf.c:3978 +msgid "2's complement, little endian" +msgstr "" + -+#: readelf.c:3485 ++#: readelf.c:3979 +msgid "2's complement, big endian" +msgstr "" + -+#: readelf.c:3503 ++#: readelf.c:3997 +msgid "Not an ELF file - it has the wrong magic bytes at the start\n" +msgstr "" + -+#: readelf.c:3513 ++#: readelf.c:4007 +#, c-format +msgid "ELF Header:\n" +msgstr "" + -+#: readelf.c:3514 ++#: readelf.c:4008 +#, c-format +msgid " Magic: " +msgstr "" + -+#: readelf.c:3518 ++#: readelf.c:4012 +#, c-format +msgid " Class: %s\n" +msgstr "" + -+#: readelf.c:3520 ++#: readelf.c:4014 +#, c-format +msgid " Data: %s\n" +msgstr "" + -+#: readelf.c:3522 ++#: readelf.c:4016 +#, c-format +msgid " Version: %d %s\n" +msgstr "" + -+#: readelf.c:3527 ++#: readelf.c:4021 +#, c-format +msgid "" +msgstr "" + -+#: readelf.c:3529 ++#: readelf.c:4023 +#, c-format +msgid " OS/ABI: %s\n" +msgstr "" + -+#: readelf.c:3531 ++#: readelf.c:4025 +#, c-format +msgid " ABI Version: %d\n" +msgstr "" + -+#: readelf.c:3533 ++#: readelf.c:4027 +#, c-format +msgid " Type: %s\n" +msgstr "" + -+#: readelf.c:3535 ++#: readelf.c:4029 +#, c-format +msgid " Machine: %s\n" +msgstr "" + -+#: readelf.c:3537 ++#: readelf.c:4031 +#, c-format +msgid " Version: 0x%lx\n" +msgstr "" + -+#: readelf.c:3540 ++#: readelf.c:4034 +#, c-format +msgid " Entry point address: " +msgstr "" + -+#: readelf.c:3542 ++#: readelf.c:4036 +#, c-format +msgid "" +"\n" +" Start of program headers: " +msgstr "" + -+#: readelf.c:3544 ++#: readelf.c:4038 +#, c-format +msgid "" +" (bytes into file)\n" +" Start of section headers: " +msgstr "" + -+#: readelf.c:3546 ++#: readelf.c:4040 +#, c-format +msgid " (bytes into file)\n" +msgstr "" + -+#: readelf.c:3548 ++#: readelf.c:4042 +#, c-format +msgid " Flags: 0x%lx%s\n" +msgstr "" + -+#: readelf.c:3551 ++#: readelf.c:4045 +#, c-format +msgid " Size of this header: %ld (bytes)\n" +msgstr "" + -+#: readelf.c:3553 ++#: readelf.c:4047 +#, c-format +msgid " Size of program headers: %ld (bytes)\n" +msgstr "" + -+#: readelf.c:3555 ++#: readelf.c:4049 +#, c-format +msgid " Number of program headers: %ld" +msgstr "" + -+#: readelf.c:3562 ++#: readelf.c:4056 +#, c-format +msgid " Size of section headers: %ld (bytes)\n" +msgstr "" + -+#: readelf.c:3564 ++#: readelf.c:4058 +#, c-format +msgid " Number of section headers: %ld" +msgstr "" + -+#: readelf.c:3569 ++#: readelf.c:4063 +#, c-format +msgid " Section header string table index: %ld" +msgstr "" + -+#: readelf.c:3576 ++#: readelf.c:4070 +#, c-format +msgid " " +msgstr "" + -+#: readelf.c:3610 readelf.c:3644 ++#: readelf.c:4104 readelf.c:4138 +msgid "program headers" +msgstr "" + -+#: readelf.c:3711 ++#: readelf.c:4205 +msgid "" +"possibly corrupt ELF header - it has a non-zero program header offset, but " +"no program headers" +msgstr "" + -+#: readelf.c:3714 ++#: readelf.c:4208 +#, c-format +msgid "" +"\n" +"There are no program headers in this file.\n" +msgstr "" + -+#: readelf.c:3720 ++#: readelf.c:4214 +#, c-format +msgid "" +"\n" +"Elf file type is %s\n" +msgstr "" + -+#: readelf.c:3721 ++#: readelf.c:4215 +#, c-format +msgid "Entry point " +msgstr "" + -+#: readelf.c:3723 ++#: readelf.c:4217 +#, c-format +msgid "" +"\n" +"There are %d program headers, starting at offset " +msgstr "" + -+#: readelf.c:3735 readelf.c:3737 ++#: readelf.c:4229 readelf.c:4231 +#, c-format +msgid "" +"\n" +"Program Headers:\n" +msgstr "" + -+#: readelf.c:3741 ++#: readelf.c:4235 +#, c-format +msgid "" +" Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align\n" +msgstr "" + -+#: readelf.c:3744 ++#: readelf.c:4238 +#, c-format +msgid "" +" Type Offset VirtAddr PhysAddr FileSiz " +"MemSiz Flg Align\n" +msgstr "" + -+#: readelf.c:3748 ++#: readelf.c:4242 +#, c-format +msgid " Type Offset VirtAddr PhysAddr\n" +msgstr "" + -+#: readelf.c:3750 ++#: readelf.c:4244 +#, c-format +msgid " FileSiz MemSiz Flags Align\n" +msgstr "" + -+#: readelf.c:3843 ++#: readelf.c:4337 +msgid "more than one dynamic segment\n" +msgstr "" + -+#: readelf.c:3862 ++#: readelf.c:4356 +msgid "no .dynamic section in the dynamic segment\n" +msgstr "" + -+#: readelf.c:3877 ++#: readelf.c:4371 +msgid "the .dynamic section is not contained within the dynamic segment\n" +msgstr "" + -+#: readelf.c:3880 ++#: readelf.c:4374 +msgid "the .dynamic section is not the first section in the dynamic segment.\n" +msgstr "" + -+#: readelf.c:3888 ++#: readelf.c:4382 +msgid "Unable to find program interpreter name\n" +msgstr "" + -+#: readelf.c:3895 ++#: readelf.c:4389 +msgid "" +"Internal error: failed to create format string to display program " +"interpreter\n" +msgstr "" + -+#: readelf.c:3899 ++#: readelf.c:4393 +msgid "Unable to read program interpreter name\n" +msgstr "" + -+#: readelf.c:3902 ++#: readelf.c:4396 +#, c-format +msgid "" +"\n" +" [Requesting program interpreter: %s]" +msgstr "" + -+#: readelf.c:3914 ++#: readelf.c:4408 +#, c-format +msgid "" +"\n" +" Section to Segment mapping:\n" +msgstr "" + -+#: readelf.c:3915 ++#: readelf.c:4409 +#, c-format +msgid " Segment Sections...\n" +msgstr "" + -+#: readelf.c:3951 ++#: readelf.c:4445 +msgid "Cannot interpret virtual addresses without program headers.\n" +msgstr "" + -+#: readelf.c:3967 ++#: readelf.c:4461 +#, c-format +msgid "Virtual address 0x%lx not located in any PT_LOAD segment.\n" +msgstr "" + -+#: readelf.c:3982 readelf.c:4025 ++#: readelf.c:4476 readelf.c:4519 +msgid "section headers" +msgstr "" + -+#: readelf.c:4074 readelf.c:4154 ++#: readelf.c:4568 readelf.c:4648 +msgid "sh_entsize is zero\n" +msgstr "" + -+#: readelf.c:4082 readelf.c:4162 ++#: readelf.c:4576 readelf.c:4656 +msgid "Invalid sh_entsize\n" +msgstr "" + -+#: readelf.c:4087 readelf.c:4167 ++#: readelf.c:4581 readelf.c:4661 +msgid "symbols" +msgstr "" + -+#: readelf.c:4099 readelf.c:4178 ++#: readelf.c:4593 readelf.c:4672 +msgid "symbol table section indicies" +msgstr "" + -+#: readelf.c:4439 ++#: readelf.c:4933 +#, c-format +msgid "UNKNOWN (%*.*lx)" +msgstr "" + -+#: readelf.c:4461 ++#: readelf.c:4955 +msgid "" +"possibly corrupt ELF file header - it has a non-zero section header offset, " +"but no section headers\n" +msgstr "" + -+#: readelf.c:4464 ++#: readelf.c:4958 +#, c-format +msgid "" +"\n" +"There are no sections in this file.\n" +msgstr "" + -+#: readelf.c:4470 ++#: readelf.c:4964 +#, c-format +msgid "There are %d section headers, starting at offset 0x%lx:\n" +msgstr "" + -+#: readelf.c:4491 readelf.c:5079 readelf.c:5491 readelf.c:5797 readelf.c:6210 -+#: readelf.c:7093 readelf.c:9213 ++#: readelf.c:4985 readelf.c:5582 readelf.c:5994 readelf.c:6302 readelf.c:6713 ++#: readelf.c:7674 readelf.c:9875 +msgid "string table" +msgstr "" + -+#: readelf.c:4558 -+#, c-format -+msgid "Section %d has invalid sh_entsize %lx (expected %lx)\n" ++#: readelf.c:5052 ++msgid "Section %d has invalid sh_entsize of %" +msgstr "" + -+#: readelf.c:4578 ++#: readelf.c:5054 ++#, c-format ++msgid "(Using the expected size of %d for the rest of this dump)\n" ++msgstr "" ++ ++#: readelf.c:5075 +msgid "File contains multiple dynamic symbol tables\n" +msgstr "" + -+#: readelf.c:4590 ++#: readelf.c:5087 +msgid "File contains multiple dynamic string tables\n" +msgstr "" + -+#: readelf.c:4596 ++#: readelf.c:5093 +msgid "dynamic strings" +msgstr "" + -+#: readelf.c:4603 ++#: readelf.c:5100 +msgid "File contains multiple symtab shndx tables\n" +msgstr "" + -+#: readelf.c:4674 ++#: readelf.c:5178 +#, c-format +msgid "" +"\n" +"Section Headers:\n" +msgstr "" + -+#: readelf.c:4676 ++#: readelf.c:5180 +#, c-format +msgid "" +"\n" +"Section Header:\n" +msgstr "" + -+#: readelf.c:4682 readelf.c:4693 readelf.c:4704 ++#: readelf.c:5186 readelf.c:5197 readelf.c:5208 +#, c-format +msgid " [Nr] Name\n" +msgstr "" + -+#: readelf.c:4683 ++#: readelf.c:5187 +#, c-format +msgid " Type Addr Off Size ES Lk Inf Al\n" +msgstr "" + -+#: readelf.c:4687 ++#: readelf.c:5191 +#, c-format +msgid "" +" [Nr] Name Type Addr Off Size ES Flg Lk " +"Inf Al\n" +msgstr "" + -+#: readelf.c:4694 ++#: readelf.c:5198 +#, c-format +msgid " Type Address Off Size ES Lk Inf Al\n" +msgstr "" + -+#: readelf.c:4698 ++#: readelf.c:5202 +#, c-format +msgid "" +" [Nr] Name Type Address Off Size ES " +"Flg Lk Inf Al\n" +msgstr "" + -+#: readelf.c:4705 ++#: readelf.c:5209 +#, c-format +msgid " Type Address Offset Link\n" +msgstr "" + -+#: readelf.c:4706 ++#: readelf.c:5210 +#, c-format +msgid " Size EntSize Info Align\n" +msgstr "" + -+#: readelf.c:4710 ++#: readelf.c:5214 +#, c-format +msgid " [Nr] Name Type Address Offset\n" +msgstr "" + -+#: readelf.c:4711 ++#: readelf.c:5215 +#, c-format +msgid " Size EntSize Flags Link Info Align\n" +msgstr "" + -+#: readelf.c:4716 ++#: readelf.c:5220 +#, c-format +msgid " Flags\n" +msgstr "" + -+#: readelf.c:4796 ++#: readelf.c:5298 +#, c-format +msgid "section %u: sh_link value of %u is larger than the number of sections\n" +msgstr "" + -+#: readelf.c:4896 ++#: readelf.c:5398 +#, c-format +msgid "" +"Key to Flags:\n" @@ -115197,7 +117174,7 @@ index 0000000..0d08397 +" O (extra OS processing required) o (OS specific), p (processor specific)\n" +msgstr "" + -+#: readelf.c:4901 ++#: readelf.c:5403 +#, c-format +msgid "" +"Key to Flags:\n" @@ -115206,830 +117183,881 @@ index 0000000..0d08397 +" O (extra OS processing required) o (OS specific), p (processor specific)\n" +msgstr "" + -+#: readelf.c:4923 ++#: readelf.c:5425 +#, c-format +msgid "[: 0x%x] " +msgstr "" + -+#: readelf.c:4949 ++#: readelf.c:5451 +#, c-format +msgid "" +"\n" +"There are no sections to group in this file.\n" +msgstr "" + -+#: readelf.c:4956 ++#: readelf.c:5458 +msgid "Section headers are not available!\n" +msgstr "" + -+#: readelf.c:4980 ++#: readelf.c:5483 +#, c-format +msgid "" +"\n" +"There are no section groups in this file.\n" +msgstr "" + -+#: readelf.c:5018 ++#: readelf.c:5521 +#, c-format +msgid "Bad sh_link in group section `%s'\n" +msgstr "" + -+#: readelf.c:5032 ++#: readelf.c:5535 +#, c-format +msgid "Corrupt header in group section `%s'\n" +msgstr "" + -+#: readelf.c:5038 readelf.c:5049 ++#: readelf.c:5541 readelf.c:5552 +#, c-format +msgid "Bad sh_info in group section `%s'\n" +msgstr "" + -+#: readelf.c:5088 ++#: readelf.c:5591 +msgid "section data" +msgstr "" + -+#: readelf.c:5099 ++#: readelf.c:5602 +#, c-format +msgid "" +"\n" +"%sgroup section [%5u] `%s' [%s] contains %u sections:\n" +msgstr "" + -+#: readelf.c:5102 ++#: readelf.c:5605 +#, c-format +msgid " [Index] Name\n" +msgstr "" + -+#: readelf.c:5116 ++#: readelf.c:5619 +#, c-format +msgid "section [%5u] in group section [%5u] > maximum section [%5u]\n" +msgstr "" + -+#: readelf.c:5125 ++#: readelf.c:5628 +#, c-format +msgid "section [%5u] in group section [%5u] already in group section [%5u]\n" +msgstr "" + -+#: readelf.c:5138 ++#: readelf.c:5641 +#, c-format +msgid "section 0 in group section [%5u]\n" +msgstr "" + -+#: readelf.c:5205 ++#: readelf.c:5708 +msgid "dynamic section image fixups" +msgstr "" + -+#: readelf.c:5217 ++#: readelf.c:5720 +#, c-format +msgid "" +"\n" +"Image fixups for needed library #%d: %s - ident: %lx\n" +msgstr "" + -+#: readelf.c:5220 ++#: readelf.c:5723 +#, c-format +msgid "Seg Offset Type SymVec DataType\n" +msgstr "" + -+#: readelf.c:5252 ++#: readelf.c:5755 +msgid "dynamic section image relocations" +msgstr "" + -+#: readelf.c:5256 ++#: readelf.c:5759 +#, c-format +msgid "" +"\n" +"Image relocs\n" +msgstr "" + -+#: readelf.c:5258 ++#: readelf.c:5761 +#, c-format +msgid "" +"Seg Offset Type Addend Seg Sym Off\n" +msgstr "" + -+#: readelf.c:5313 ++#: readelf.c:5816 +msgid "dynamic string section" +msgstr "" + -+#: readelf.c:5414 ++#: readelf.c:5917 +#, c-format +msgid "" +"\n" +"'%s' relocation section at offset 0x%lx contains %ld bytes:\n" +msgstr "" + -+#: readelf.c:5429 ++#: readelf.c:5932 +#, c-format +msgid "" +"\n" +"There are no dynamic relocations in this file.\n" +msgstr "" + -+#: readelf.c:5453 ++#: readelf.c:5956 +#, c-format +msgid "" +"\n" +"Relocation section " +msgstr "" + -+#: readelf.c:5460 readelf.c:5890 readelf.c:6227 ++#: readelf.c:5963 readelf.c:6395 readelf.c:6730 +#, c-format +msgid " at offset 0x%lx contains %lu entries:\n" +msgstr "" + -+#: readelf.c:5510 ++#: readelf.c:6013 +#, c-format +msgid "" +"\n" +"There are no relocations in this file.\n" +msgstr "" + -+#: readelf.c:5648 ++#: readelf.c:6153 +#, c-format +msgid "\tUnknown version.\n" +msgstr "" + -+#: readelf.c:5701 readelf.c:6074 ++#: readelf.c:6206 readelf.c:6577 +msgid "unwind table" +msgstr "" + -+#: readelf.c:5743 readelf.c:6156 readelf.c:6415 ++#: readelf.c:6248 readelf.c:6659 readelf.c:6942 readelf.c:6955 +#, c-format +msgid "Skipping unexpected relocation type %s\n" +msgstr "" + -+#: readelf.c:5805 readelf.c:6218 readelf.c:7101 readelf.c:7148 ++#: readelf.c:6310 readelf.c:6721 readelf.c:7682 +#, c-format +msgid "" +"\n" +"There are no unwind sections in this file.\n" +msgstr "" + -+#: readelf.c:5868 ++#: readelf.c:6373 +#, c-format +msgid "" +"\n" +"Could not find unwind info section for " +msgstr "" + -+#: readelf.c:5873 readelf.c:5888 readelf.c:6225 ++#: readelf.c:6378 readelf.c:6393 readelf.c:6728 +#, c-format +msgid "'%s'" +msgstr "" + -+#: readelf.c:5880 ++#: readelf.c:6385 +msgid "unwind info" +msgstr "" + -+#: readelf.c:5883 readelf.c:6224 ++#: readelf.c:6388 readelf.c:6727 +#, c-format +msgid "" +"\n" +"Unwind section " +msgstr "" + -+#: readelf.c:6333 ++#: readelf.c:6849 +msgid "unwind data" +msgstr "" + -+#: readelf.c:6386 ++#: readelf.c:6908 +#, c-format +msgid "Skipping unexpected relocation at offset 0x%lx\n" +msgstr "" + -+#: readelf.c:6490 ++#: readelf.c:7023 +#, c-format +msgid "[Truncated opcode]\n" +msgstr "" + -+#: readelf.c:6534 readelf.c:6734 ++#: readelf.c:7067 readelf.c:7267 +#, c-format +msgid "Refuse to unwind" +msgstr "" + -+#: readelf.c:6557 ++#: readelf.c:7090 +#, c-format +msgid " [Reserved]" +msgstr "" + -+#: readelf.c:6585 ++#: readelf.c:7118 +#, c-format +msgid " finish" +msgstr "" + -+#: readelf.c:6590 readelf.c:6676 ++#: readelf.c:7123 readelf.c:7209 +#, c-format +msgid "[Spare]" +msgstr "" + -+#: readelf.c:6697 readelf.c:6831 ++#: readelf.c:7230 readelf.c:7366 +#, c-format +msgid " [unsupported opcode]" +msgstr "" + -+#: readelf.c:6781 ++#: readelf.c:7315 +#, c-format +msgid "pop frame {" +msgstr "" + -+#: readelf.c:6792 ++#: readelf.c:7326 +msgid "[pad]" +msgstr "" + -+#: readelf.c:6820 ++#: readelf.c:7355 +#, c-format +msgid "sp = sp + %ld" +msgstr "" + -+#: readelf.c:6878 ++#: readelf.c:7421 +#, c-format +msgid " Personality routine: " +msgstr "" + -+#: readelf.c:6896 ++#: readelf.c:7453 +#, c-format +msgid " [Truncated data]\n" +msgstr "" + -+#: readelf.c:6911 ++#: readelf.c:7476 +#, c-format -+msgid " Compact model %d\n" ++msgid "Corrupt ARM compact model table entry: %x \n" +msgstr "" + -+#: readelf.c:6947 ++#: readelf.c:7479 ++#, c-format ++msgid " Compact model index: %d\n" ++msgstr "" ++ ++#: readelf.c:7504 ++msgid "Unknown ARM compact model index encountered\n" ++msgstr "" ++ ++#: readelf.c:7505 ++#, c-format ++msgid " [reserved]\n" ++msgstr "" ++ ++#: readelf.c:7518 +#, c-format +msgid " Restore stack from frame pointer\n" +msgstr "" + -+#: readelf.c:6949 ++#: readelf.c:7520 +#, c-format +msgid " Stack increment %d\n" +msgstr "" + -+#: readelf.c:6950 ++#: readelf.c:7521 +#, c-format +msgid " Registers restored: " +msgstr "" + -+#: readelf.c:6955 ++#: readelf.c:7526 +#, c-format +msgid " Return register: %s\n" +msgstr "" + -+#: readelf.c:7038 ++#: readelf.c:7530 ++#, c-format ++msgid " [reserved (%d)]\n" ++msgstr "" ++ ++#: readelf.c:7534 ++#, c-format ++msgid "Unsupported architecture type %d encountered when decoding unwind table" ++msgstr "" ++ ++#: readelf.c:7573 ++#, c-format ++msgid "corrupt index table entry: %x\n" ++msgstr "" ++ ++#: readelf.c:7616 +#, c-format +msgid "Could not locate .ARM.extab section containing 0x%lx.\n" +msgstr "" + -+#: readelf.c:7107 ++#: readelf.c:7654 ++#, c-format ++msgid "" ++"Unsupported architecture type %d encountered when processing unwind table" ++msgstr "" ++ ++#: readelf.c:7688 +#, c-format +msgid "" +"\n" +"Unwind table index '%s' at offset 0x%lx contains %lu entries:\n" +msgstr "" + -+#: readelf.c:7159 ++#: readelf.c:7730 +#, c-format -+msgid "NONE\n" ++msgid "" ++"\n" ++"The decoding of unwind sections for machine type %s is not currently " ++"supported.\n" +msgstr "" + -+#: readelf.c:7185 ++#: readelf.c:7741 +#, c-format -+msgid "Interface Version: %s\n" ++msgid "NONE" +msgstr "" + -+#: readelf.c:7187 ++#: readelf.c:7766 +#, c-format -+msgid "\n" ++msgid "Interface Version: %s" +msgstr "" + -+#: readelf.c:7200 -+#, c-format -+msgid "Time Stamp: %s\n" ++#: readelf.c:7768 ++msgid "" +msgstr "" + -+#: readelf.c:8123 ++#: readelf.c:8765 +#, c-format +msgid "" +"\n" +"Version definition section '%s' contains %u entries:\n" +msgstr "" + -+#: readelf.c:8126 ++#: readelf.c:8768 +#, c-format +msgid " Addr: 0x" +msgstr "" + -+#: readelf.c:8128 readelf.c:8246 readelf.c:8390 ++#: readelf.c:8770 readelf.c:8886 readelf.c:9028 +#, c-format +msgid " Offset: %#08lx Link: %u (%s)\n" +msgstr "" + -+#: readelf.c:8136 ++#: readelf.c:8778 +msgid "version definition section" +msgstr "" + -+#: readelf.c:8169 ++#: readelf.c:8811 +#, c-format +msgid " %#06x: Rev: %d Flags: %s" +msgstr "" + -+#: readelf.c:8172 ++#: readelf.c:8814 +#, c-format +msgid " Index: %d Cnt: %d " +msgstr "" + -+#: readelf.c:8188 ++#: readelf.c:8829 +#, c-format +msgid "Name: %s\n" +msgstr "" + -+#: readelf.c:8190 ++#: readelf.c:8831 +#, c-format +msgid "Name index: %ld\n" +msgstr "" + -+#: readelf.c:8212 ++#: readelf.c:8852 +#, c-format +msgid " %#06x: Parent %d: %s\n" +msgstr "" + -+#: readelf.c:8215 ++#: readelf.c:8855 +#, c-format +msgid " %#06x: Parent %d, name index: %ld\n" +msgstr "" + -+#: readelf.c:8220 ++#: readelf.c:8860 +#, c-format +msgid " Version def aux past end of section\n" +msgstr "" + -+#: readelf.c:8226 ++#: readelf.c:8866 +#, c-format +msgid " Version definition past end of section\n" +msgstr "" + -+#: readelf.c:8241 ++#: readelf.c:8881 +#, c-format +msgid "" +"\n" +"Version needs section '%s' contains %u entries:\n" +msgstr "" + -+#: readelf.c:8244 ++#: readelf.c:8884 +#, c-format +msgid " Addr: 0x" +msgstr "" + -+#: readelf.c:8255 ++#: readelf.c:8895 +msgid "Version Needs section" +msgstr "" + -+#: readelf.c:8283 ++#: readelf.c:8923 +#, c-format +msgid " %#06x: Version: %d" +msgstr "" + -+#: readelf.c:8286 ++#: readelf.c:8926 +#, c-format +msgid " File: %s" +msgstr "" + -+#: readelf.c:8288 ++#: readelf.c:8928 +#, c-format +msgid " File: %lx" +msgstr "" + -+#: readelf.c:8290 ++#: readelf.c:8930 +#, c-format +msgid " Cnt: %d\n" +msgstr "" + -+#: readelf.c:8315 ++#: readelf.c:8954 +#, c-format +msgid " %#06x: Name: %s" +msgstr "" + -+#: readelf.c:8318 ++#: readelf.c:8957 +#, c-format +msgid " %#06x: Name index: %lx" +msgstr "" + -+#: readelf.c:8321 ++#: readelf.c:8960 +#, c-format +msgid " Flags: %s Version: %d\n" +msgstr "" + -+#: readelf.c:8334 ++#: readelf.c:8972 +msgid "Missing Version Needs auxillary information\n" +msgstr "" + -+#: readelf.c:8340 ++#: readelf.c:8978 +msgid "Missing Version Needs information\n" +msgstr "" + -+#: readelf.c:8378 ++#: readelf.c:9016 +msgid "version string table" +msgstr "" + -+#: readelf.c:8385 ++#: readelf.c:9023 +#, c-format +msgid "" +"\n" +"Version symbols section '%s' contains %d entries:\n" +msgstr "" + -+#: readelf.c:8388 ++#: readelf.c:9026 +#, c-format +msgid " Addr: " +msgstr "" + -+#: readelf.c:8399 ++#: readelf.c:9037 +msgid "version symbol data" +msgstr "" + -+#: readelf.c:8427 ++#: readelf.c:9065 +msgid " 0 (*local*) " +msgstr "" + -+#: readelf.c:8431 ++#: readelf.c:9069 +msgid " 1 (*global*) " +msgstr "" + -+#: readelf.c:8442 ++#: readelf.c:9080 +msgid "invalid index into symbol array\n" +msgstr "" + -+#: readelf.c:8476 readelf.c:9279 ++#: readelf.c:9114 readelf.c:9941 +msgid "version need" +msgstr "" + -+#: readelf.c:8487 ++#: readelf.c:9125 +msgid "version need aux (2)" +msgstr "" + -+#: readelf.c:8508 readelf.c:8570 ++#: readelf.c:9146 readelf.c:9208 +msgid "*invalid*" +msgstr "" + -+#: readelf.c:8538 readelf.c:9357 ++#: readelf.c:9176 readelf.c:10019 +msgid "version def" +msgstr "" + -+#: readelf.c:8564 readelf.c:9379 ++#: readelf.c:9202 readelf.c:10041 +msgid "version def aux" +msgstr "" + -+#: readelf.c:8599 ++#: readelf.c:9237 +#, c-format +msgid "" +"\n" +"No version information found in this file.\n" +msgstr "" + -+#: readelf.c:8807 ++#: readelf.c:9433 ++#, c-format ++msgid ": %d" ++msgstr "" ++ ++#: readelf.c:9467 +#, c-format +msgid ": %x" +msgstr "" + -+#: readelf.c:8869 ++#: readelf.c:9531 +msgid "Unable to read in dynamic data\n" +msgstr "" + -+#: readelf.c:8919 ++#: readelf.c:9581 +#, c-format +msgid " " +msgstr "" + -+#: readelf.c:8962 readelf.c:9014 readelf.c:9038 readelf.c:9068 readelf.c:9092 ++#: readelf.c:9624 readelf.c:9676 readelf.c:9700 readelf.c:9730 readelf.c:9754 +msgid "Unable to seek to start of dynamic information\n" +msgstr "" + -+#: readelf.c:8968 readelf.c:9020 ++#: readelf.c:9630 readelf.c:9682 +msgid "Failed to read in number of buckets\n" +msgstr "" + -+#: readelf.c:8974 ++#: readelf.c:9636 +msgid "Failed to read in number of chains\n" +msgstr "" + -+#: readelf.c:9076 ++#: readelf.c:9738 +msgid "Failed to determine last chain length\n" +msgstr "" + -+#: readelf.c:9120 ++#: readelf.c:9782 +#, c-format +msgid "" +"\n" +"Symbol table for image:\n" +msgstr "" + -+#: readelf.c:9122 readelf.c:9140 ++#: readelf.c:9784 readelf.c:9802 +#, c-format +msgid " Num Buc: Value Size Type Bind Vis Ndx Name\n" +msgstr "" + -+#: readelf.c:9124 readelf.c:9142 ++#: readelf.c:9786 readelf.c:9804 +#, c-format +msgid " Num Buc: Value Size Type Bind Vis Ndx Name\n" +msgstr "" + -+#: readelf.c:9138 ++#: readelf.c:9800 +#, c-format +msgid "" +"\n" +"Symbol table of `.gnu.hash' for image:\n" +msgstr "" + -+#: readelf.c:9182 ++#: readelf.c:9844 +#, c-format +msgid "" +"\n" +"Symbol table '%s' has a sh_entsize of zero!\n" +msgstr "" + -+#: readelf.c:9187 ++#: readelf.c:9849 +#, c-format +msgid "" +"\n" +"Symbol table '%s' contains %lu entries:\n" +msgstr "" + -+#: readelf.c:9192 ++#: readelf.c:9854 +#, c-format +msgid " Num: Value Size Type Bind Vis Ndx Name\n" +msgstr "" + -+#: readelf.c:9194 ++#: readelf.c:9856 +#, c-format +msgid " Num: Value Size Type Bind Vis Ndx Name\n" +msgstr "" + -+#: readelf.c:9249 ++#: readelf.c:9911 +msgid "version data" +msgstr "" + -+#: readelf.c:9298 ++#: readelf.c:9960 +msgid "version need aux (3)" +msgstr "" + -+#: readelf.c:9332 ++#: readelf.c:9994 +msgid "bad dynamic symbol\n" +msgstr "" + -+#: readelf.c:9404 ++#: readelf.c:10066 +#, c-format +msgid "" +"\n" +"Dynamic symbol information is not available for displaying symbols.\n" +msgstr "" + -+#: readelf.c:9416 ++#: readelf.c:10078 +#, c-format +msgid "" +"\n" +"Histogram for bucket list length (total of %lu buckets):\n" +msgstr "" + -+#: readelf.c:9418 readelf.c:9488 ++#: readelf.c:10080 readelf.c:10151 +#, c-format +msgid " Length Number %% of total Coverage\n" +msgstr "" + -+#: readelf.c:9486 ++#: readelf.c:10149 +#, c-format +msgid "" +"\n" +"Histogram for `.gnu.hash' bucket list length (total of %lu buckets):\n" +msgstr "" + -+#: readelf.c:9552 ++#: readelf.c:10216 +#, c-format +msgid "" +"\n" +"Dynamic info segment at offset 0x%lx contains %d entries:\n" +msgstr "" + -+#: readelf.c:9555 ++#: readelf.c:10219 +#, c-format +msgid " Num: Name BoundTo Flags\n" +msgstr "" + -+#: readelf.c:9564 ++#: readelf.c:10228 +#, c-format +msgid "" +msgstr "" + -+#: readelf.c:9646 ++#: readelf.c:10328 ++msgid "Unhandled MSP430 reloc type found after SYM_DIFF reloc" ++msgstr "" ++ ++#: readelf.c:10364 +msgid "Unhandled MN10300 reloc type found after SYM_DIFF reloc" +msgstr "" + -+#: readelf.c:9813 ++#: readelf.c:10543 +#, c-format +msgid "" +"Missing knowledge of 32-bit reloc types used in DWARF sections of machine " +"number %d\n" +msgstr "" + -+#: readelf.c:10138 ++#: readelf.c:10899 +#, c-format +msgid "unable to apply unsupported reloc type %d to section %s\n" +msgstr "" + -+#: readelf.c:10146 ++#: readelf.c:10907 +#, c-format +msgid "skipping invalid relocation offset 0x%lx in section %s\n" +msgstr "" + -+#: readelf.c:10155 ++#: readelf.c:10916 +#, c-format +msgid "skipping invalid relocation symbol index 0x%lx in section %s\n" +msgstr "" + -+#: readelf.c:10177 ++#: readelf.c:10938 +#, c-format +msgid "skipping unexpected symbol type %s in %ld'th relocation in section %s\n" +msgstr "" + -+#: readelf.c:10223 ++#: readelf.c:10984 +#, c-format +msgid "" +"\n" +"Assembly dump of section %s\n" +msgstr "" + -+#: readelf.c:10244 ++#: readelf.c:11005 +#, c-format +msgid "" +"\n" +"Section '%s' has no data to dump.\n" +msgstr "" + -+#: readelf.c:10250 ++#: readelf.c:11011 +msgid "section contents" +msgstr "" + -+#: readelf.c:10269 ++#: readelf.c:11030 +#, c-format +msgid "" +"\n" +"String dump of section '%s':\n" +msgstr "" + -+#: readelf.c:10287 ++#: readelf.c:11048 +#, c-format +msgid "" +" Note: This section has relocations against it, but these have NOT been " +"applied to this dump.\n" +msgstr "" + -+#: readelf.c:10318 ++#: readelf.c:11079 +#, c-format +msgid " No strings found in this section." +msgstr "" + -+#: readelf.c:10340 ++#: readelf.c:11101 +#, c-format +msgid "" +"\n" +"Hex dump of section '%s':\n" +msgstr "" + -+#: readelf.c:10364 ++#: readelf.c:11125 +#, c-format +msgid "" +" NOTE: This section has relocations against it, but these have NOT been " +"applied to this dump.\n" +msgstr "" + -+#: readelf.c:10498 ++#: readelf.c:11259 +#, c-format +msgid "%s section data" +msgstr "" + -+#: readelf.c:10568 ++#: readelf.c:11339 +#, c-format +msgid "" +"\n" @@ -116040,836 +118068,999 @@ index 0000000..0d08397 +#. which has the NOBITS type - the bits in the file will be random. +#. This can happen when a file containing a .eh_frame section is +#. stripped with the --only-keep-debug command line option. -+#: readelf.c:10577 ++#: readelf.c:11348 +#, c-format +msgid "section '%s' has the NOBITS type - its contents are unreliable.\n" +msgstr "" + -+#: readelf.c:10613 ++#: readelf.c:11393 +#, c-format +msgid "Unrecognized debug section: %s\n" +msgstr "" + -+#: readelf.c:10641 ++#: readelf.c:11421 +#, c-format +msgid "Section '%s' was not dumped because it does not exist!\n" +msgstr "" + -+#: readelf.c:10682 ++#: readelf.c:11462 +#, c-format +msgid "Section %d was not dumped because it does not exist!\n" +msgstr "" + -+#: readelf.c:10860 readelf.c:10874 readelf.c:10893 readelf.c:11293 ++#: readelf.c:11512 ++msgid "corrupt tag\n" ++msgstr "" ++ ++#: readelf.c:11688 readelf.c:11702 readelf.c:11721 readelf.c:12070 ++#: readelf.c:12333 readelf.c:12346 readelf.c:12359 +#, c-format +msgid "None\n" +msgstr "" + -+#: readelf.c:10861 ++#: readelf.c:11689 +#, c-format +msgid "Application\n" +msgstr "" + -+#: readelf.c:10862 ++#: readelf.c:11690 +#, c-format +msgid "Realtime\n" +msgstr "" + -+#: readelf.c:10863 ++#: readelf.c:11691 +#, c-format +msgid "Microcontroller\n" +msgstr "" + -+#: readelf.c:10864 ++#: readelf.c:11692 +#, c-format +msgid "Application or Realtime\n" +msgstr "" + -+#: readelf.c:10875 readelf.c:10895 readelf.c:11347 readelf.c:11365 -+#: readelf.c:11440 readelf.c:11461 ++#: readelf.c:11703 readelf.c:11723 readelf.c:12124 readelf.c:12142 ++#: readelf.c:12217 readelf.c:12238 +#, c-format +msgid "8-byte\n" +msgstr "" + -+#: readelf.c:10876 readelf.c:11443 readelf.c:11464 ++#: readelf.c:11704 readelf.c:12220 readelf.c:12241 +#, c-format +msgid "4-byte\n" +msgstr "" + -+#: readelf.c:10880 readelf.c:10899 ++#: readelf.c:11708 readelf.c:11727 +#, c-format +msgid "8-byte and up to %d-byte extended\n" +msgstr "" + -+#: readelf.c:10894 ++#: readelf.c:11722 +#, c-format +msgid "8-byte, except leaf SP\n" +msgstr "" + -+#: readelf.c:10910 readelf.c:11000 readelf.c:11479 ++#: readelf.c:11738 readelf.c:11815 readelf.c:12256 +#, c-format +msgid "flag = %d, vendor = %s\n" +msgstr "" + -+#: readelf.c:10916 ++#: readelf.c:11744 +#, c-format +msgid "True\n" +msgstr "" + -+#: readelf.c:11045 readelf.c:11231 ++#: readelf.c:11810 ++#, c-format ++msgid "flag = %d, vendor = \n" ++msgstr "" ++ ++#: readelf.c:11811 ++msgid "corrupt vendor attribute\n" ++msgstr "" ++ ++#: readelf.c:11844 readelf.c:12001 +#, c-format +msgid "Hard or soft float\n" +msgstr "" + -+#: readelf.c:11048 ++#: readelf.c:11847 +#, c-format +msgid "Hard float\n" +msgstr "" + -+#: readelf.c:11051 readelf.c:11240 ++#: readelf.c:11850 readelf.c:12010 +#, c-format +msgid "Soft float\n" +msgstr "" + -+#: readelf.c:11054 ++#: readelf.c:11853 +#, c-format +msgid "Single-precision hard float\n" +msgstr "" + -+#: readelf.c:11071 readelf.c:11097 ++#: readelf.c:11870 readelf.c:11902 +#, c-format +msgid "Any\n" +msgstr "" + -+#: readelf.c:11074 ++#: readelf.c:11873 +#, c-format +msgid "Generic\n" +msgstr "" + -+#: readelf.c:11103 ++#: readelf.c:11892 ++msgid "corrupt Tag_GNU_Power_ABI_Struct_Return" ++msgstr "" ++ ++#: readelf.c:11908 +#, c-format +msgid "Memory\n" +msgstr "" + -+#: readelf.c:11234 ++#: readelf.c:12004 +#, c-format +msgid "Hard float (double precision)\n" +msgstr "" + -+#: readelf.c:11237 ++#: readelf.c:12007 +#, c-format +msgid "Hard float (single precision)\n" +msgstr "" + -+#: readelf.c:11243 ++#: readelf.c:12013 +#, c-format +msgid "Hard float (MIPS32r2 64-bit FPU)\n" +msgstr "" + -+#: readelf.c:11326 ++#: readelf.c:12034 ++#, c-format ++msgid "Any MSA or not\n" ++msgstr "" ++ ++#: readelf.c:12037 ++#, c-format ++msgid "128-bit MSA\n" ++msgstr "" ++ ++#: readelf.c:12103 +#, c-format +msgid "Not used\n" +msgstr "" + -+#: readelf.c:11329 ++#: readelf.c:12106 +#, c-format +msgid "2 bytes\n" +msgstr "" + -+#: readelf.c:11332 ++#: readelf.c:12109 +#, c-format +msgid "4 bytes\n" +msgstr "" + -+#: readelf.c:11350 readelf.c:11368 readelf.c:11446 readelf.c:11467 ++#: readelf.c:12127 readelf.c:12145 readelf.c:12223 readelf.c:12244 +#, c-format +msgid "16-byte\n" +msgstr "" + -+#: readelf.c:11383 ++#: readelf.c:12160 +#, c-format +msgid "DSBT addressing not used\n" +msgstr "" + -+#: readelf.c:11386 ++#: readelf.c:12163 +#, c-format +msgid "DSBT addressing used\n" +msgstr "" + -+#: readelf.c:11401 ++#: readelf.c:12178 +#, c-format +msgid "Data addressing position-dependent\n" +msgstr "" + -+#: readelf.c:11404 ++#: readelf.c:12181 +#, c-format +msgid "Data addressing position-independent, GOT near DP\n" +msgstr "" + -+#: readelf.c:11407 ++#: readelf.c:12184 +#, c-format +msgid "Data addressing position-independent, GOT far from DP\n" +msgstr "" + -+#: readelf.c:11422 ++#: readelf.c:12199 +#, c-format +msgid "Code addressing position-dependent\n" +msgstr "" + -+#: readelf.c:11425 ++#: readelf.c:12202 +#, c-format +msgid "Code addressing position-independent\n" +msgstr "" + -+#: readelf.c:11531 ++#: readelf.c:12334 ++#, c-format ++msgid "MSP430\n" ++msgstr "" ++ ++#: readelf.c:12335 ++#, c-format ++msgid "MSP430X\n" ++msgstr "" ++ ++#: readelf.c:12347 readelf.c:12360 ++#, c-format ++msgid "Small\n" ++msgstr "" ++ ++#: readelf.c:12348 readelf.c:12361 ++#, c-format ++msgid "Large\n" ++msgstr "" ++ ++#: readelf.c:12362 ++#, c-format ++msgid "Restricted Large\n" ++msgstr "" ++ ++#: readelf.c:12368 ++#, c-format ++msgid " : " ++msgstr "" ++ ++#: readelf.c:12411 +msgid "attributes" +msgstr "" + -+#: readelf.c:11552 ++#: readelf.c:12432 +#, c-format +msgid "ERROR: Bad section length (%d > %d)\n" +msgstr "" + -+#: readelf.c:11558 ++#: readelf.c:12438 +#, c-format +msgid "Attribute Section: %s\n" +msgstr "" + -+#: readelf.c:11583 ++#: readelf.c:12463 +#, c-format +msgid "ERROR: Bad subsection length (%d > %d)\n" +msgstr "" + -+#: readelf.c:11595 ++#: readelf.c:12475 +#, c-format +msgid "File Attributes\n" +msgstr "" + -+#: readelf.c:11598 ++#: readelf.c:12478 +#, c-format +msgid "Section Attributes:" +msgstr "" + -+#: readelf.c:11601 ++#: readelf.c:12481 +#, c-format +msgid "Symbol Attributes:" +msgstr "" + -+#: readelf.c:11616 ++#: readelf.c:12496 +#, c-format +msgid "Unknown tag: %d\n" +msgstr "" + -+#. ??? Do something sensible, like dump hex. -+#: readelf.c:11635 ++#: readelf.c:12515 +#, c-format +msgid " Unknown section contexts\n" +msgstr "" + -+#: readelf.c:11642 ++#: readelf.c:12523 +#, c-format +msgid "Unknown format '%c'\n" +msgstr "" + -+#: readelf.c:11693 readelf.c:11715 ++#: readelf.c:12581 readelf.c:12603 +msgid "" +msgstr "" + -+#: readelf.c:11810 readelf.c:12344 ++#: readelf.c:12698 readelf.c:13266 +msgid "liblist section data" +msgstr "" + -+#: readelf.c:11813 ++#: readelf.c:12701 +#, c-format +msgid "" +"\n" +"Section '.liblist' contains %lu entries:\n" +msgstr "" + -+#: readelf.c:11815 ++#: readelf.c:12703 +msgid "" +" Library Time Stamp Checksum Version Flags\n" +msgstr "" + -+#: readelf.c:11841 ++#: readelf.c:12729 +#, c-format +msgid "" +msgstr "" + -+#: readelf.c:11846 ++#: readelf.c:12734 +msgid " NONE" +msgstr "" + -+#: readelf.c:11897 ++#: readelf.c:12785 +msgid "options" +msgstr "" + -+#: readelf.c:11928 ++#: readelf.c:12816 +#, c-format +msgid "" +"\n" +"Section '%s' contains %d entries:\n" +msgstr "" + -+#: readelf.c:12089 ++#: readelf.c:12977 +msgid "conflict list found without a dynamic symbol table\n" +msgstr "" + -+#: readelf.c:12106 readelf.c:12121 ++#: readelf.c:12994 readelf.c:13009 +msgid "conflict" +msgstr "" + -+#: readelf.c:12131 ++#: readelf.c:13019 +#, c-format +msgid "" +"\n" +"Section '.conflict' contains %lu entries:\n" +msgstr "" + -+#: readelf.c:12133 ++#: readelf.c:13021 +msgid " Num: Index Value Name" +msgstr "" + -+#: readelf.c:12145 readelf.c:12234 readelf.c:12305 ++#: readelf.c:13033 readelf.c:13122 readelf.c:13193 +#, c-format +msgid "" +msgstr "" + -+#: readelf.c:12167 ++#: readelf.c:13055 +msgid "Global Offset Table data" +msgstr "" + -+#: readelf.c:12171 ++#: readelf.c:13059 +#, c-format +msgid "" +"\n" +"Primary GOT:\n" +msgstr "" + -+#: readelf.c:12172 ++#: readelf.c:13060 +#, c-format +msgid " Canonical gp value: " +msgstr "" + -+#: readelf.c:12176 readelf.c:12276 ++#: readelf.c:13064 readelf.c:13164 +#, c-format +msgid " Reserved entries:\n" +msgstr "" + -+#: readelf.c:12177 ++#: readelf.c:13065 +#, c-format +msgid " %*s %10s %*s Purpose\n" +msgstr "" + -+#: readelf.c:12178 readelf.c:12195 readelf.c:12211 readelf.c:12278 -+#: readelf.c:12287 ++#: readelf.c:13066 readelf.c:13083 readelf.c:13099 readelf.c:13166 ++#: readelf.c:13175 +msgid "Address" +msgstr "" + -+#: readelf.c:12178 readelf.c:12195 readelf.c:12212 ++#: readelf.c:13066 readelf.c:13083 readelf.c:13100 +msgid "Access" +msgstr "" + -+#: readelf.c:12179 readelf.c:12196 readelf.c:12213 readelf.c:12278 -+#: readelf.c:12288 ++#: readelf.c:13067 readelf.c:13084 readelf.c:13101 readelf.c:13166 ++#: readelf.c:13176 +msgid "Initial" +msgstr "" + -+#: readelf.c:12181 ++#: readelf.c:13069 +#, c-format +msgid " Lazy resolver\n" +msgstr "" + -+#: readelf.c:12187 ++#: readelf.c:13075 +#, c-format +msgid " Module pointer (GNU extension)\n" +msgstr "" + -+#: readelf.c:12193 ++#: readelf.c:13081 +#, c-format +msgid " Local entries:\n" +msgstr "" + -+#: readelf.c:12209 ++#: readelf.c:13097 +#, c-format +msgid " Global entries:\n" +msgstr "" + -+#: readelf.c:12214 readelf.c:12289 ++#: readelf.c:13102 readelf.c:13177 +msgid "Sym.Val." +msgstr "" + +#. Note for translators: "Ndx" = abbreviated form of "Index". -+#: readelf.c:12217 readelf.c:12289 ++#: readelf.c:13105 readelf.c:13177 +msgid "Ndx" +msgstr "" + -+#: readelf.c:12217 readelf.c:12289 ++#: readelf.c:13105 readelf.c:13177 +msgid "Name" +msgstr "" + -+#: readelf.c:12271 ++#: readelf.c:13159 +msgid "Procedure Linkage Table data" +msgstr "" + -+#: readelf.c:12277 ++#: readelf.c:13165 +#, c-format +msgid " %*s %*s Purpose\n" +msgstr "" + -+#: readelf.c:12280 ++#: readelf.c:13168 +#, c-format +msgid " PLT lazy resolver\n" +msgstr "" + -+#: readelf.c:12282 ++#: readelf.c:13170 +#, c-format +msgid " Module pointer\n" +msgstr "" + -+#: readelf.c:12285 ++#: readelf.c:13173 +#, c-format +msgid " Entries:\n" +msgstr "" + -+#: readelf.c:12352 ++#: readelf.c:13218 ++msgid "NDS32 elf flags section" ++msgstr "" ++ ++#: readelf.c:13274 +msgid "liblist string table" +msgstr "" + -+#: readelf.c:12362 ++#: readelf.c:13284 +#, c-format +msgid "" +"\n" +"Library list section '%s' contains %lu entries:\n" +msgstr "" + -+#: readelf.c:12366 ++#: readelf.c:13288 +msgid " Library Time Stamp Checksum Version Flags" +msgstr "" + -+#: readelf.c:12416 ++#: readelf.c:13338 +msgid "NT_AUXV (auxiliary vector)" +msgstr "" + -+#: readelf.c:12418 ++#: readelf.c:13340 +msgid "NT_PRSTATUS (prstatus structure)" +msgstr "" + -+#: readelf.c:12420 ++#: readelf.c:13342 +msgid "NT_FPREGSET (floating point registers)" +msgstr "" + -+#: readelf.c:12422 ++#: readelf.c:13344 +msgid "NT_PRPSINFO (prpsinfo structure)" +msgstr "" + -+#: readelf.c:12424 ++#: readelf.c:13346 +msgid "NT_TASKSTRUCT (task structure)" +msgstr "" + -+#: readelf.c:12426 ++#: readelf.c:13348 +msgid "NT_PRXFPREG (user_xfpregs structure)" +msgstr "" + -+#: readelf.c:12428 ++#: readelf.c:13350 +msgid "NT_PPC_VMX (ppc Altivec registers)" +msgstr "" + -+#: readelf.c:12430 ++#: readelf.c:13352 +msgid "NT_PPC_VSX (ppc VSX registers)" +msgstr "" + -+#: readelf.c:12432 ++#: readelf.c:13354 ++msgid "NT_386_TLS (x86 TLS information)" ++msgstr "" ++ ++#: readelf.c:13356 ++msgid "NT_386_IOPERM (x86 I/O permissions)" ++msgstr "" ++ ++#: readelf.c:13358 +msgid "NT_X86_XSTATE (x86 XSAVE extended state)" +msgstr "" + -+#: readelf.c:12434 ++#: readelf.c:13360 +msgid "NT_S390_HIGH_GPRS (s390 upper register halves)" +msgstr "" + -+#: readelf.c:12436 ++#: readelf.c:13362 +msgid "NT_S390_TIMER (s390 timer register)" +msgstr "" + -+#: readelf.c:12438 ++#: readelf.c:13364 +msgid "NT_S390_TODCMP (s390 TOD comparator register)" +msgstr "" + -+#: readelf.c:12440 ++#: readelf.c:13366 +msgid "NT_S390_TODPREG (s390 TOD programmable register)" +msgstr "" + -+#: readelf.c:12442 ++#: readelf.c:13368 +msgid "NT_S390_CTRS (s390 control registers)" +msgstr "" + -+#: readelf.c:12444 ++#: readelf.c:13370 +msgid "NT_S390_PREFIX (s390 prefix register)" +msgstr "" + -+#: readelf.c:12446 ++#: readelf.c:13372 ++msgid "NT_S390_LAST_BREAK (s390 last breaking event address)" ++msgstr "" ++ ++#: readelf.c:13374 ++msgid "NT_S390_SYSTEM_CALL (s390 system call restart data)" ++msgstr "" ++ ++#: readelf.c:13376 ++msgid "NT_S390_TDB (s390 transaction diagnostic block)" ++msgstr "" ++ ++#: readelf.c:13378 +msgid "NT_ARM_VFP (arm VFP registers)" +msgstr "" + -+#: readelf.c:12448 ++#: readelf.c:13380 ++msgid "NT_ARM_TLS (AArch TLS registers)" ++msgstr "" ++ ++#: readelf.c:13382 ++msgid "NT_ARM_HW_BREAK (AArch hardware breakpoint registers)" ++msgstr "" ++ ++#: readelf.c:13384 ++msgid "NT_ARM_HW_WATCH (AArch hardware watchpoint registers)" ++msgstr "" ++ ++#: readelf.c:13386 +msgid "NT_PSTATUS (pstatus structure)" +msgstr "" + -+#: readelf.c:12450 ++#: readelf.c:13388 +msgid "NT_FPREGS (floating point registers)" +msgstr "" + -+#: readelf.c:12452 ++#: readelf.c:13390 +msgid "NT_PSINFO (psinfo structure)" +msgstr "" + -+#: readelf.c:12454 ++#: readelf.c:13392 +msgid "NT_LWPSTATUS (lwpstatus_t structure)" +msgstr "" + -+#: readelf.c:12456 ++#: readelf.c:13394 +msgid "NT_LWPSINFO (lwpsinfo_t structure)" +msgstr "" + -+#: readelf.c:12458 ++#: readelf.c:13396 +msgid "NT_WIN32PSTATUS (win32_pstatus structure)" +msgstr "" + -+#: readelf.c:12466 ++#: readelf.c:13398 ++msgid "NT_SIGINFO (siginfo_t data)" ++msgstr "" ++ ++#: readelf.c:13400 ++msgid "NT_FILE (mapped files)" ++msgstr "" ++ ++#: readelf.c:13408 +msgid "NT_VERSION (version)" +msgstr "" + -+#: readelf.c:12468 ++#: readelf.c:13410 +msgid "NT_ARCH (architecture)" +msgstr "" + -+#: readelf.c:12473 readelf.c:12496 readelf.c:12575 readelf.c:12633 -+#: readelf.c:12710 ++#: readelf.c:13415 readelf.c:13524 readelf.c:13614 readelf.c:13672 ++#: readelf.c:13749 +#, c-format +msgid "Unknown note type: (0x%08x)" +msgstr "" + -+#: readelf.c:12485 ++#: readelf.c:13432 ++#, c-format ++msgid " Cannot decode 64-bit note in 32-bit build\n" ++msgstr "" ++ ++#: readelf.c:13440 ++#, c-format ++msgid " Malformed note - too short for header\n" ++msgstr "" ++ ++#: readelf.c:13449 ++#, c-format ++msgid " Malformed note - does not end with \\0\n" ++msgstr "" ++ ++#: readelf.c:13461 ++#, c-format ++msgid " Malformed note - too short for supplied file count\n" ++msgstr "" ++ ++#: readelf.c:13465 ++#, c-format ++msgid " Page size: " ++msgstr "" ++ ++#: readelf.c:13469 ++#, c-format ++msgid " %*s%*s%*s\n" ++msgstr "" ++ ++#: readelf.c:13470 ++msgid "Start" ++msgstr "" ++ ++#: readelf.c:13471 ++msgid "End" ++msgstr "" ++ ++#: readelf.c:13472 ++msgid "Page Offset" ++msgstr "" ++ ++#: readelf.c:13480 ++#, c-format ++msgid " Malformed note - filenames end too early\n" ++msgstr "" ++ ++#: readelf.c:13513 +msgid "NT_GNU_ABI_TAG (ABI version tag)" +msgstr "" + -+#: readelf.c:12487 ++#: readelf.c:13515 +msgid "NT_GNU_HWCAP (DSO-supplied software HWCAP info)" +msgstr "" + -+#: readelf.c:12489 ++#: readelf.c:13517 +msgid "NT_GNU_BUILD_ID (unique build ID bitstring)" +msgstr "" + -+#: readelf.c:12491 ++#: readelf.c:13519 +msgid "NT_GNU_GOLD_VERSION (gold version)" +msgstr "" + -+#: readelf.c:12509 ++#: readelf.c:13537 +#, c-format +msgid " Build ID: " +msgstr "" + -+#: readelf.c:12548 ++#: readelf.c:13576 +#, c-format +msgid " OS: %s, ABI: %ld.%ld.%ld\n" +msgstr "" + ++#: readelf.c:13585 ++#, c-format ++msgid " Version: " ++msgstr "" ++ +#. NetBSD core "procinfo" structure. -+#: readelf.c:12565 ++#: readelf.c:13604 +msgid "NetBSD procinfo structure" +msgstr "" + -+#: readelf.c:12592 readelf.c:12606 ++#: readelf.c:13631 readelf.c:13645 +msgid "PT_GETREGS (reg structure)" +msgstr "" + -+#: readelf.c:12594 readelf.c:12608 ++#: readelf.c:13633 readelf.c:13647 +msgid "PT_GETFPREGS (fpreg structure)" +msgstr "" + -+#: readelf.c:12627 ++#: readelf.c:13666 +msgid "NT_STAPSDT (SystemTap probe descriptors)" +msgstr "" + -+#: readelf.c:12660 ++#: readelf.c:13699 +#, c-format +msgid " Provider: %s\n" +msgstr "" + -+#: readelf.c:12661 ++#: readelf.c:13700 +#, c-format +msgid " Name: %s\n" +msgstr "" + -+#: readelf.c:12662 ++#: readelf.c:13701 +#, c-format +msgid " Location: " +msgstr "" + -+#: readelf.c:12664 ++#: readelf.c:13703 +#, c-format +msgid ", Base: " +msgstr "" + -+#: readelf.c:12666 ++#: readelf.c:13705 +#, c-format +msgid ", Semaphore: " +msgstr "" + -+#: readelf.c:12669 ++#: readelf.c:13708 +#, c-format +msgid " Arguments: %s\n" +msgstr "" + -+#: readelf.c:12682 ++#: readelf.c:13721 +msgid "NT_VMS_MHD (module header)" +msgstr "" + -+#: readelf.c:12684 ++#: readelf.c:13723 +msgid "NT_VMS_LNM (language name)" +msgstr "" + -+#: readelf.c:12686 ++#: readelf.c:13725 +msgid "NT_VMS_SRC (source files)" +msgstr "" + -+#: readelf.c:12690 ++#: readelf.c:13729 +msgid "NT_VMS_EIDC (consistency check)" +msgstr "" + -+#: readelf.c:12692 ++#: readelf.c:13731 +msgid "NT_VMS_FPMODE (FP mode)" +msgstr "" + -+#: readelf.c:12696 ++#: readelf.c:13735 +msgid "NT_VMS_IMGNAM (image name)" +msgstr "" + -+#: readelf.c:12698 ++#: readelf.c:13737 +msgid "NT_VMS_IMGID (image id)" +msgstr "" + -+#: readelf.c:12700 ++#: readelf.c:13739 +msgid "NT_VMS_LINKID (link id)" +msgstr "" + -+#: readelf.c:12702 ++#: readelf.c:13741 +msgid "NT_VMS_IMGBID (build id)" +msgstr "" + -+#: readelf.c:12704 ++#: readelf.c:13743 +msgid "NT_VMS_GSTNAM (sym table name)" +msgstr "" + -+#: readelf.c:12724 ++#: readelf.c:13763 +#, c-format +msgid " Creation date : %.17s\n" +msgstr "" + -+#: readelf.c:12725 ++#: readelf.c:13764 +#, c-format +msgid " Last patch date: %.17s\n" +msgstr "" + -+#: readelf.c:12726 ++#: readelf.c:13765 +#, c-format +msgid " Module name : %s\n" +msgstr "" + -+#: readelf.c:12727 ++#: readelf.c:13766 +#, c-format +msgid " Module version : %s\n" +msgstr "" + -+#: readelf.c:12730 ++#: readelf.c:13769 +#, c-format +msgid " Invalid size\n" +msgstr "" + -+#: readelf.c:12733 ++#: readelf.c:13772 +#, c-format +msgid " Language: %s\n" +msgstr "" + -+#: readelf.c:12737 ++#: readelf.c:13776 +#, c-format +msgid " Floating Point mode: " +msgstr "" + -+#: readelf.c:12742 ++#: readelf.c:13781 +#, c-format +msgid " Link time: " +msgstr "" + -+#: readelf.c:12748 ++#: readelf.c:13787 +#, c-format +msgid " Patch time: " +msgstr "" + -+#: readelf.c:12754 ++#: readelf.c:13793 +#, c-format +msgid " Major id: %u, minor id: %u\n" +msgstr "" + -+#: readelf.c:12757 ++#: readelf.c:13796 +#, c-format +msgid " Last modified : " +msgstr "" + -+#: readelf.c:12760 ++#: readelf.c:13799 +#, c-format +msgid "" +"\n" +" Link flags : " +msgstr "" + -+#: readelf.c:12763 ++#: readelf.c:13802 +#, c-format +msgid " Header flags: 0x%08x\n" +msgstr "" + -+#: readelf.c:12765 ++#: readelf.c:13804 +#, c-format +msgid " Image id : %s\n" +msgstr "" + -+#: readelf.c:12769 ++#: readelf.c:13808 +#, c-format +msgid " Image name: %s\n" +msgstr "" + -+#: readelf.c:12772 ++#: readelf.c:13811 +#, c-format +msgid " Global symbol table name: %s\n" +msgstr "" + -+#: readelf.c:12775 ++#: readelf.c:13814 +#, c-format +msgid " Image id: %s\n" +msgstr "" + -+#: readelf.c:12778 ++#: readelf.c:13817 +#, c-format +msgid " Linker id: %s\n" +msgstr "" + -+#: readelf.c:12853 ++#: readelf.c:13894 +msgid "notes" +msgstr "" + -+#: readelf.c:12859 ++#: readelf.c:13900 +#, c-format +msgid "" +"\n" -+"Notes at offset 0x%08lx with length 0x%08lx:\n" ++"Displaying notes found at file offset 0x%08lx with length 0x%08lx:\n" +msgstr "" + -+#: readelf.c:12861 ++#: readelf.c:13902 +#, c-format +msgid " %-20s %10s\tDescription\n" +msgstr "" + -+#: readelf.c:12861 ++#: readelf.c:13902 +msgid "Owner" +msgstr "" + -+#: readelf.c:12861 ++#: readelf.c:13902 +msgid "Data size" +msgstr "" + -+#: readelf.c:12899 readelf.c:12912 ++#: readelf.c:13919 readelf.c:13940 +#, c-format -+msgid "corrupt note found at offset %lx into core notes\n" ++msgid "Corrupt note: only %d bytes remain, not enough for a full note\n" +msgstr "" + -+#: readelf.c:12901 readelf.c:12914 ++#: readelf.c:13959 +#, c-format -+msgid " type: %lx, namesize: %08lx, descsize: %08lx\n" ++msgid "note with invalid namesz and/or descsz found at offset 0x%lx\n" +msgstr "" + -+#: readelf.c:13010 ++#: readelf.c:13961 ++#, c-format ++msgid " type: 0x%lx, namesize: 0x%08lx, descsize: 0x%08lx\n" ++msgstr "" ++ ++#: readelf.c:14059 +#, c-format +msgid "No note segments present in the core file.\n" +msgstr "" + -+#: readelf.c:13102 ++#: readelf.c:14156 +msgid "" +"This instance of readelf has been built without support for a\n" +"64 bit data type and so it cannot read 64 bit ELF files.\n" +msgstr "" + -+#: readelf.c:13149 ++#: readelf.c:14203 +#, c-format +msgid "%s: Failed to read file header\n" +msgstr "" + -+#: readelf.c:13163 ++#: readelf.c:14217 +#, c-format +msgid "" +"\n" +"File: %s\n" +msgstr "" + -+#: readelf.c:13335 ++#: readelf.c:14389 +#, c-format +msgid "%s: unable to dump the index as none was found\n" +msgstr "" + -+#: readelf.c:13341 ++#: readelf.c:14395 +#, c-format +msgid "Index of archive %s: (%ld entries, 0x%lx bytes in the symbol table)\n" +msgstr "" + -+#: readelf.c:13359 ++#: readelf.c:14413 +#, c-format -+msgid "Binary %s contains:\n" ++msgid "Contents of binary %s at offset " +msgstr "" + -+#: readelf.c:13367 ++#: readelf.c:14423 +#, c-format +msgid "%s: end of the symbol table reached before the end of the index\n" +msgstr "" + -+#: readelf.c:13378 ++#: readelf.c:14437 +#, c-format +msgid "" -+"%s: symbols remain in the index symbol table, but without corresponding " -+"entries in the index table\n" ++"%s: %ld bytes remain in the symbol table, but without corresponding entries " ++"in the index table\n" +msgstr "" + -+#: readelf.c:13383 ++#: readelf.c:14442 +#, c-format +msgid "%s: failed to seek back to start of object files in the archive\n" +msgstr "" + -+#: readelf.c:13466 readelf.c:13549 ++#: readelf.c:14525 readelf.c:14617 +#, c-format +msgid "Input file '%s' is not readable.\n" +msgstr "" + -+#: readelf.c:13488 ++#: readelf.c:14543 ++#, c-format ++msgid "%s: contains corrupt thin archive: %s\n" ++msgstr "" ++ ++#: readelf.c:14556 +#, c-format +msgid "%s: failed to seek to archive member.\n" +msgstr "" + -+#: readelf.c:13567 ++#: readelf.c:14635 +#, c-format +msgid "File %s is not an archive so its index cannot be displayed.\n" +msgstr "" + -+#: rename.c:124 ++#: rename.c:122 +#, c-format +msgid "%s: cannot set time: %s" +msgstr "" + +#. We have to clean up here. -+#: rename.c:159 rename.c:197 ++#: rename.c:157 rename.c:195 +#, c-format +msgid "unable to rename '%s'; reason: %s" +msgstr "" + -+#: rename.c:205 ++#: rename.c:203 +#, c-format +msgid "unable to copy file '%s'; reason: %s" +msgstr "" @@ -116981,7 +119172,7 @@ index 0000000..0d08397 +msgid "group cursor header" +msgstr "" + -+#: resbin.c:801 resrc.c:1355 ++#: resbin.c:801 resrc.c:1350 +#, c-format +msgid "unexpected group cursor type %d" +msgstr "" @@ -116994,7 +119185,7 @@ index 0000000..0d08397 +msgid "group icon header" +msgstr "" + -+#: resbin.c:856 resrc.c:1302 ++#: resbin.c:856 resrc.c:1297 +#, c-format +msgid "unexpected group icon type %d" +msgstr "" @@ -117003,7 +119194,7 @@ index 0000000..0d08397 +msgid "group icon" +msgstr "" + -+#: resbin.c:935 resbin.c:1173 ++#: resbin.c:935 resbin.c:1169 +msgid "unexpected version string" +msgstr "" + @@ -117045,206 +119236,206 @@ index 0000000..0d08397 +msgid "unexpected stringfileinfo value length %ld" +msgstr "" + -+#: resbin.c:1059 ++#: resbin.c:1056 +msgid "version stringtable" +msgstr "" + -+#: resbin.c:1067 ++#: resbin.c:1064 +#, c-format +msgid "unexpected version stringtable value length %ld" +msgstr "" + -+#: resbin.c:1084 ++#: resbin.c:1081 +msgid "version string" +msgstr "" + -+#: resbin.c:1101 ++#: resbin.c:1096 +#, c-format +msgid "unexpected version string length %ld != %ld + %ld" +msgstr "" + -+#: resbin.c:1108 ++#: resbin.c:1103 +#, c-format +msgid "unexpected version string length %ld < %ld" +msgstr "" + -+#: resbin.c:1133 ++#: resbin.c:1129 +#, c-format +msgid "unexpected varfileinfo value length %ld" +msgstr "" + -+#: resbin.c:1152 ++#: resbin.c:1148 +msgid "version varfileinfo" +msgstr "" + -+#: resbin.c:1167 ++#: resbin.c:1163 +#, c-format +msgid "unexpected version value length %ld" +msgstr "" + -+#: rescoff.c:124 ++#: rescoff.c:123 +msgid "filename required for COFF input" +msgstr "" + -+#: rescoff.c:141 ++#: rescoff.c:140 +#, c-format +msgid "%s: no resource section" +msgstr "" + -+#: rescoff.c:173 ++#: rescoff.c:172 +#, c-format +msgid "%s: %s: address out of bounds" +msgstr "" + -+#: rescoff.c:190 ++#: rescoff.c:189 +msgid "directory" +msgstr "" + -+#: rescoff.c:218 ++#: rescoff.c:217 +msgid "named directory entry" +msgstr "" + -+#: rescoff.c:227 ++#: rescoff.c:226 +msgid "directory entry name" +msgstr "" + -+#: rescoff.c:247 ++#: rescoff.c:246 +msgid "named subdirectory" +msgstr "" + -+#: rescoff.c:255 ++#: rescoff.c:254 +msgid "named resource" +msgstr "" + -+#: rescoff.c:270 ++#: rescoff.c:269 +msgid "ID directory entry" +msgstr "" + -+#: rescoff.c:287 ++#: rescoff.c:286 +msgid "ID subdirectory" +msgstr "" + -+#: rescoff.c:295 ++#: rescoff.c:294 +msgid "ID resource" +msgstr "" + -+#: rescoff.c:320 ++#: rescoff.c:319 +msgid "resource type unknown" +msgstr "" + -+#: rescoff.c:323 ++#: rescoff.c:322 +msgid "data entry" +msgstr "" + -+#: rescoff.c:331 ++#: rescoff.c:330 +msgid "resource data" +msgstr "" + -+#: rescoff.c:336 ++#: rescoff.c:335 +msgid "resource data size" +msgstr "" + -+#: rescoff.c:431 ++#: rescoff.c:430 +msgid "filename required for COFF output" +msgstr "" + -+#: rescoff.c:715 ++#: rescoff.c:714 +msgid "can't get BFD_RELOC_RVA relocation type" +msgstr "" + -+#: resrc.c:262 resrc.c:333 ++#: resrc.c:257 resrc.c:328 +#, c-format +msgid "can't open temporary file `%s': %s" +msgstr "" + -+#: resrc.c:268 ++#: resrc.c:263 +#, c-format +msgid "can't redirect stdout: `%s': %s" +msgstr "" + -+#: resrc.c:329 ++#: resrc.c:324 +#, c-format +msgid "can't execute `%s': %s" +msgstr "" + -+#: resrc.c:338 ++#: resrc.c:333 +#, c-format +msgid "Using temporary file `%s' to read preprocessor output\n" +msgstr "" + -+#: resrc.c:345 ++#: resrc.c:340 +#, c-format +msgid "can't popen `%s': %s" +msgstr "" + -+#: resrc.c:347 ++#: resrc.c:342 +#, c-format +msgid "Using popen to read preprocessor output\n" +msgstr "" + -+#: resrc.c:413 ++#: resrc.c:408 +#, c-format +msgid "Tried `%s'\n" +msgstr "" + -+#: resrc.c:424 ++#: resrc.c:419 +#, c-format +msgid "Using `%s'\n" +msgstr "" + -+#: resrc.c:608 ++#: resrc.c:603 +msgid "preprocessing failed." +msgstr "" + -+#: resrc.c:639 ++#: resrc.c:634 +#, c-format +msgid "%s: unexpected EOF" +msgstr "" + -+#: resrc.c:688 ++#: resrc.c:683 +#, c-format +msgid "%s: read of %lu returned %lu" +msgstr "" + -+#: resrc.c:727 resrc.c:1502 ++#: resrc.c:722 resrc.c:1497 +#, c-format +msgid "stat failed on bitmap file `%s': %s" +msgstr "" + -+#: resrc.c:778 ++#: resrc.c:773 +#, c-format +msgid "cursor file `%s' does not contain cursor data" +msgstr "" + -+#: resrc.c:810 resrc.c:1210 ++#: resrc.c:805 resrc.c:1205 +#, c-format +msgid "%s: fseek to %lu failed: %s" +msgstr "" + -+#: resrc.c:936 ++#: resrc.c:931 +msgid "help ID requires DIALOGEX" +msgstr "" + -+#: resrc.c:938 ++#: resrc.c:933 +msgid "control data requires DIALOGEX" +msgstr "" + -+#: resrc.c:966 ++#: resrc.c:961 +#, c-format +msgid "stat failed on font file `%s': %s" +msgstr "" + -+#: resrc.c:1179 ++#: resrc.c:1174 +#, c-format +msgid "icon file `%s' does not contain icon data" +msgstr "" + -+#: resrc.c:1724 resrc.c:1759 ++#: resrc.c:1723 resrc.c:1758 +#, c-format +msgid "stat failed on file `%s': %s" +msgstr "" + -+#: resrc.c:1958 ++#: resrc.c:1957 +#, c-format +msgid "can't open `%s' for output: %s" +msgstr "" @@ -117286,12 +119477,12 @@ index 0000000..0d08397 +msgid "Invalid radix: %s\n" +msgstr "" + -+#: srconv.c:1733 ++#: srconv.c:1734 +#, c-format +msgid "Convert a COFF object file into a SYSROFF object file\n" +msgstr "" + -+#: srconv.c:1734 ++#: srconv.c:1735 +#, c-format +msgid "" +" The options are:\n" @@ -117303,7 +119494,7 @@ index 0000000..0d08397 +" -v --version Print the program's version number\n" +msgstr "" + -+#: srconv.c:1880 ++#: srconv.c:1881 +#, c-format +msgid "unable to open output file %s" +msgstr "" @@ -117372,91 +119563,91 @@ index 0000000..0d08397 +msgid "const/volatile indicator missing" +msgstr "" + -+#: stabs.c:2924 ++#: stabs.c:2921 +#, c-format +msgid "No mangling for \"%s\"\n" +msgstr "" + -+#: stabs.c:3224 ++#: stabs.c:3221 +msgid "Undefined N_EXCL" +msgstr "" + -+#: stabs.c:3304 ++#: stabs.c:3301 +#, c-format +msgid "Type file number %d out of range\n" +msgstr "" + -+#: stabs.c:3309 ++#: stabs.c:3306 +#, c-format +msgid "Type index number %d out of range\n" +msgstr "" + -+#: stabs.c:3388 ++#: stabs.c:3385 +#, c-format +msgid "Unrecognized XCOFF type %d\n" +msgstr "" + -+#: stabs.c:3680 ++#: stabs.c:3677 +#, c-format +msgid "bad mangled name `%s'\n" +msgstr "" + -+#: stabs.c:3775 ++#: stabs.c:3772 +#, c-format +msgid "no argument types in mangled string\n" +msgstr "" + -+#: stabs.c:5125 ++#: stabs.c:5122 +#, c-format +msgid "Demangled name is not a function\n" +msgstr "" + -+#: stabs.c:5167 ++#: stabs.c:5164 +#, c-format +msgid "Unexpected type in v3 arglist demangling\n" +msgstr "" + -+#: stabs.c:5234 ++#: stabs.c:5236 +#, c-format +msgid "Unrecognized demangle component %d\n" +msgstr "" + -+#: stabs.c:5286 ++#: stabs.c:5288 +#, c-format +msgid "Failed to print demangled template\n" +msgstr "" + -+#: stabs.c:5366 ++#: stabs.c:5368 +#, c-format +msgid "Couldn't get demangled builtin type\n" +msgstr "" + -+#: stabs.c:5415 ++#: stabs.c:5417 +#, c-format +msgid "Unexpected demangled varargs\n" +msgstr "" + -+#: stabs.c:5422 ++#: stabs.c:5424 +#, c-format +msgid "Unrecognized demangled builtin type\n" +msgstr "" + -+#: strings.c:186 strings.c:245 ++#: strings.c:185 strings.c:244 +#, c-format +msgid "invalid integer argument %s" +msgstr "" + -+#: strings.c:248 ++#: strings.c:247 +#, c-format +msgid "invalid minimum string length %d" +msgstr "" + -+#: strings.c:651 ++#: strings.c:637 +#, c-format +msgid " Display printable strings in [file(s)] (stdin by default)\n" +msgstr "" + -+#: strings.c:652 ++#: strings.c:638 +#, c-format +msgid "" +" The options are:\n" @@ -117528,7 +119719,7 @@ index 0000000..0d08397 + +#: version.c:36 +#, c-format -+msgid "Copyright 2011 Free Software Foundation, Inc.\n" ++msgid "Copyright 2014 Free Software Foundation, Inc.\n" +msgstr "" + +#: version.c:37 @@ -117586,7 +119777,7 @@ index 0000000..0d08397 +" -V --version Print version information\n" +msgstr "" + -+#: windmc.c:261 windres.c:411 ++#: windmc.c:261 windres.c:403 +#, c-format +msgid "%s: warning: " +msgstr "" @@ -117619,48 +119810,48 @@ index 0000000..0d08397 +msgid "input file does not seems to be UFT16.\n" +msgstr "" + -+#: windres.c:216 ++#: windres.c:213 +#, c-format +msgid "can't open %s `%s': %s" +msgstr "" + -+#: windres.c:390 ++#: windres.c:382 +#, c-format +msgid ": expected to be a directory\n" +msgstr "" + -+#: windres.c:402 ++#: windres.c:394 +#, c-format +msgid ": expected to be a leaf\n" +msgstr "" + -+#: windres.c:413 ++#: windres.c:405 +#, c-format +msgid ": duplicate value\n" +msgstr "" + -+#: windres.c:563 ++#: windres.c:555 +#, c-format +msgid "unknown format type `%s'" +msgstr "" + -+#: windres.c:564 ++#: windres.c:556 +#, c-format +msgid "%s: supported formats:" +msgstr "" + +#. Otherwise, we give up. -+#: windres.c:647 ++#: windres.c:639 +#, c-format +msgid "can not determine type of file `%s'; use the -J option" +msgstr "" + -+#: windres.c:659 ++#: windres.c:651 +#, c-format +msgid "Usage: %s [option(s)] [input-file] [output-file]\n" +msgstr "" + -+#: windres.c:661 ++#: windres.c:653 +#, c-format +msgid "" +" The options are:\n" @@ -117683,12 +119874,12 @@ index 0000000..0d08397 +" --no-use-temp-file Use popen (default)\n" +msgstr "" + -+#: windres.c:679 ++#: windres.c:671 +#, c-format +msgid " --yydebug Turn on parser debugging\n" +msgstr "" + -+#: windres.c:682 ++#: windres.c:674 +#, c-format +msgid "" +" -r Ignored for compatibility with rc\n" @@ -117697,7 +119888,7 @@ index 0000000..0d08397 +" -V --version Print version information\n" +msgstr "" + -+#: windres.c:687 ++#: windres.c:679 +#, c-format +msgid "" +"FORMAT is one of rc, res, or coff, and is deduced from the file name\n" @@ -117705,26 +119896,26 @@ index 0000000..0d08397 +"No input-file is stdin, default rc. No output-file is stdout, default rc.\n" +msgstr "" + -+#: windres.c:850 ++#: windres.c:842 +msgid "invalid codepage specified.\n" +msgstr "" + -+#: windres.c:865 ++#: windres.c:857 +msgid "invalid option -f\n" +msgstr "" + -+#: windres.c:870 ++#: windres.c:862 +msgid "No filename following the -fo option.\n" +msgstr "" + -+#: windres.c:959 ++#: windres.c:951 +#, c-format +msgid "" +"Option -I is deprecated for setting the input format, please use -J " +"instead.\n" +msgstr "" + -+#: windres.c:1072 ++#: windres.c:1064 +msgid "no resources" +msgstr "" + @@ -246651,13 +248842,12 @@ index 0000000..0e02eed +msgstr "%s：警告：çµæ§‹ä¸­ã€Œ%sã€æ¬„ä½çš„大å°æœªçŸ¥" diff --git a/binutils/prdbg.c b/binutils/prdbg.c new file mode 100644 -index 0000000..091cefe +index 0000000..fab60a6 --- /dev/null +++ b/binutils/prdbg.c -@@ -0,0 +1,2838 @@ +@@ -0,0 +1,2837 @@ +/* prdbg.c -- Print out generic debugging information. -+ Copyright 1995, 1996, 1999, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009, 2011 Free Software Foundation, Inc. ++ Copyright (C) 1995-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor . + Tags style generation written by Salvador E. Tropea . + @@ -249495,13 +251685,13 @@ index 0000000..091cefe +} diff --git a/binutils/ranlib.sh b/binutils/ranlib.sh new file mode 100755 -index 0000000..f6cee8a +index 0000000..0df4a37 --- /dev/null +++ b/binutils/ranlib.sh @@ -0,0 +1,22 @@ +#!/bin/sh +# A simple ranlib script, to use less disk space than a ranlib program. -+# Copyright 2004, 2007 Free Software Foundation, Inc. ++# Copyright (C) 2004-2014 Free Software Foundation, Inc. + +# This program is part of GNU Binutils. + @@ -249523,14 +251713,13 @@ index 0000000..f6cee8a +ar s "$1" diff --git a/binutils/rclex.c b/binutils/rclex.c new file mode 100644 -index 0000000..07ae179 +index 0000000..692f713 --- /dev/null +++ b/binutils/rclex.c -@@ -0,0 +1,905 @@ +@@ -0,0 +1,904 @@ +/* rclex.c -- lexer for Windows rc files parser */ + -+/* Copyright 1997, 1998, 1999, 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009 -+ Free Software Foundation, Inc. ++/* Copyright (C) 1997-2014 Free Software Foundation, Inc. + + Written by Kai Tietz, Onevision. + @@ -250434,13 +252623,12 @@ index 0000000..07ae179 +} diff --git a/binutils/rcparse.y b/binutils/rcparse.y new file mode 100644 -index 0000000..f4101d5 +index 0000000..f552ce5 --- /dev/null +++ b/binutils/rcparse.y -@@ -0,0 +1,2013 @@ +@@ -0,0 +1,2012 @@ +%{ /* rcparse.y -- parser for Windows rc files -+ Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007, 2008, -+ 2011 Free Software Foundation, Inc. ++ Copyright (C) 1997-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor, Cygnus Support. + Extended by Kai Tietz, Onevision. + @@ -252453,13 +254641,12 @@ index 0000000..f4101d5 +} diff --git a/binutils/rdcoff.c b/binutils/rdcoff.c new file mode 100644 -index 0000000..473305e +index 0000000..859aefe --- /dev/null +++ b/binutils/rdcoff.c -@@ -0,0 +1,876 @@ +@@ -0,0 +1,875 @@ +/* stabs.c -- Parse COFF debugging information -+ Copyright 1996, 1999, 2000, 2002, 2003, 2005, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1996-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor . + + This file is part of GNU Binutils. @@ -253335,13 +255522,12 @@ index 0000000..473305e +} diff --git a/binutils/rddbg.c b/binutils/rddbg.c new file mode 100644 -index 0000000..27abd66 +index 0000000..bfa54ab --- /dev/null +++ b/binutils/rddbg.c -@@ -0,0 +1,450 @@ +@@ -0,0 +1,449 @@ +/* rddbg.c -- Read debugging information into a generic form. -+ Copyright 1995, 1996, 1997, 2000, 2002, 2003, 2005, 2007, 2008, -+ 2010 Free Software Foundation, Inc. ++ Copyright (C) 1995-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor . + + This file is part of GNU Binutils. @@ -253791,12 +255977,12 @@ index 0000000..27abd66 +} diff --git a/binutils/readelf.c b/binutils/readelf.c new file mode 100644 -index 0000000..7d228d6 +index 0000000..af6463e --- /dev/null +++ b/binutils/readelf.c -@@ -0,0 +1,14701 @@ +@@ -0,0 +1,14734 @@ +/* readelf.c -- display contents of an ELF format file -+ Copyright 1998-2013 Free Software Foundation, Inc. ++ Copyright (C) 1998-2014 Free Software Foundation, Inc. + + Originally developed by Eric Youngdale + Modifications by Nick Clifton @@ -253930,7 +256116,7 @@ index 0000000..7d228d6 +#include "elf/msp430.h" +#include "elf/nds32.h" +#include "elf/nios2.h" -+#include "elf/or32.h" ++#include "elf/or1k.h" +#include "elf/pj.h" +#include "elf/ppc.h" +#include "elf/ppc64.h" @@ -254377,8 +256563,6 @@ index 0000000..7d228d6 + case EM_MIPS: + case EM_MIPS_RS3_LE: + case EM_CYGNUS_M32R: -+ case EM_OPENRISC: -+ case EM_OR32: + case EM_SCORE: + case EM_XGATE: + return FALSE; @@ -254426,6 +256610,7 @@ index 0000000..7d228d6 + case EM_MT: + case EM_NDS32: + case EM_NIOS32: ++ case EM_OR1K: + case EM_PPC64: + case EM_PPC: + case EM_RL78: @@ -254982,9 +257167,8 @@ index 0000000..7d228d6 + rtype = elf_h8_reloc_type (type); + break; + -+ case EM_OPENRISC: -+ case EM_OR32: -+ rtype = elf_or32_reloc_type (type); ++ case EM_OR1K: ++ rtype = elf_or1k_reloc_type (type); + break; + + case EM_PJ: @@ -255811,8 +257995,7 @@ index 0000000..7d228d6 + case EM_S390: return "IBM S/390"; + case EM_SCORE: return "SUNPLUS S+Core"; + case EM_XSTORMY16: return "Sanyo XStormy16 CPU core"; -+ case EM_OPENRISC: -+ case EM_OR32: return "OpenRISC"; ++ case EM_OR1K: return "OpenRISC 1000"; + case EM_ARC_A5: return "ARC International ARCompact processor"; + case EM_CRX: return "National Semiconductor CRX microprocessor"; + case EM_ADAPTEVA_EPIPHANY: return "Adapteva EPIPHANY"; @@ -256605,6 +258788,7 @@ index 0000000..7d228d6 + case E_MIPS_MACH_LS3A: strcat (buf, ", loongson-3a"); break; + case E_MIPS_MACH_OCTEON: strcat (buf, ", octeon"); break; + case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break; ++ case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break; + case E_MIPS_MACH_XLR: strcat (buf, ", xlr"); break; + case 0: + /* We simply ignore the field in this case to avoid confusion: @@ -256690,6 +258874,11 @@ index 0000000..7d228d6 + if (e_flags & EF_SH_FDPIC) + strcat (buf, ", fdpic"); + break; ++ ++ case EM_OR1K: ++ if (e_flags & EF_OR1K_NODELAY) ++ strcat (buf, ", no delay"); ++ break; + + case EM_SPARCV9: + if (e_flags & EF_SPARC_32PLUS) @@ -256803,6 +258992,8 @@ index 0000000..7d228d6 + case EM_RL78: + if (e_flags & E_FLAG_RL78_G10) + strcat (buf, ", G10"); ++ if (e_flags & E_FLAG_RL78_64BIT_DOUBLES) ++ strcat (buf, ", 64-bit doubles"); + break; + + case EM_RX: @@ -262767,6 +264958,12 @@ index 0000000..7d228d6 + if (j < ent.vn_cnt) + warn (_("Missing Version Needs auxillary information\n")); + ++ if (ent.vn_next == 0 && cnt < section->sh_info - 1) ++ { ++ warn (_("Corrupt Version Needs structure - offset to next structure is zero with entries still left to be processed\n")); ++ cnt = section->sh_info; ++ break; ++ } + idx += ent.vn_next; + } + @@ -264275,9 +266472,8 @@ index 0000000..7d228d6 + return reloc_type == 12; /* R_NIOS2_BFD_RELOC_32. */ + case EM_NIOS32: + return reloc_type == 1; /* R_NIOS_32. */ -+ case EM_OPENRISC: -+ case EM_OR32: -+ return reloc_type == 1; /* R_OR32_32. */ ++ case EM_OR1K: ++ return reloc_type == 1; /* R_OR1K_32. */ + case EM_PARISC: + return (reloc_type == 1 /* R_PARISC_DIR32. */ + || reloc_type == 41); /* R_PARISC_SECREL32. */ @@ -264365,6 +266561,8 @@ index 0000000..7d228d6 + return reloc_type == 3; /* R_ARM_REL32 */ + case EM_MICROBLAZE: + return reloc_type == 2; /* R_MICROBLAZE_32_PCREL. */ ++ case EM_OR1K: ++ return reloc_type == 9; /* R_OR1K_32_PCREL. */ + case EM_PARISC: + return reloc_type == 9; /* R_PARISC_PCREL32. */ + case EM_PPC: @@ -264530,6 +266728,8 @@ index 0000000..7d228d6 + return reloc_type == 13; /* R_NIOS2_BFD_RELOC_16. */ + case EM_NIOS32: + return reloc_type == 9; /* R_NIOS_16. */ ++ case EM_OR1K: ++ return reloc_type == 2; /* R_OR1K_16. */ + case EM_TI_C6000: + return reloc_type == 2; /* R_C6000_ABS16. */ + case EM_XC16X: @@ -264586,6 +266786,7 @@ index 0000000..7d228d6 + case EM_C166: /* R_XC16X_NONE. */ + case EM_ALTERA_NIOS2: /* R_NIOS2_NONE. */ + case EM_NIOS32: /* R_NIOS_NONE. */ ++ case EM_OR1K: /* R_OR1K_NONE. */ + return reloc_type == 0; + case EM_AARCH64: + return reloc_type == 0 || reloc_type == 256; @@ -266216,7 +268417,7 @@ index 0000000..7d228d6 + + while (len > 0) + { -+ int namelen; ++ unsigned int namelen; + bfd_boolean public_section; + bfd_boolean gnu_section; + @@ -266225,12 +268426,21 @@ index 0000000..7d228d6 + + if (section_len > len) + { -+ printf (_("ERROR: Bad section length (%d > %d)\n"), -+ (int) section_len, (int) len); ++ error (_("Length of attribute (%u) greater than length of section (%u)\n"), ++ (unsigned) section_len, (unsigned) len); + section_len = len; + } + + len -= section_len; ++ section_len -= 4; ++ ++ namelen = strnlen ((char *) p, section_len) + 1; ++ if (namelen == 0 || namelen >= section_len) ++ { ++ error (_("Corrupt attribute section name\n")); ++ break; ++ } ++ + printf (_("Attribute Section: %s\n"), p); + + if (public_name && streq ((char *) p, public_name)) @@ -266243,10 +268453,8 @@ index 0000000..7d228d6 + else + gnu_section = FALSE; + -+ namelen = strlen ((char *) p) + 1; + p += namelen; -+ section_len -= namelen + 4; -+ ++ section_len -= namelen; + while (section_len > 0) + { + int tag = *(p++); @@ -266256,8 +268464,8 @@ index 0000000..7d228d6 + size = byte_get (p, 4); + if (size > section_len) + { -+ printf (_("ERROR: Bad subsection length (%d > %d)\n"), -+ (int) size, (int) section_len); ++ error (_("Bad subsection length (%u > %u)\n"), ++ (unsigned) size, (unsigned) section_len); + size = section_len; + } + @@ -266316,7 +268524,7 @@ index 0000000..7d228d6 + } + } + else -+ printf (_("Unknown format '%c'\n"), *p); ++ printf (_("Unknown format '%c' (%d)\n"), *p, *p); + + free (contents); + } @@ -267373,6 +269581,17 @@ index 0000000..7d228d6 + major, minor, subminor); + } + break; ++ ++ case NT_GNU_GOLD_VERSION: ++ { ++ unsigned long i; ++ ++ printf (_(" Version: ")); ++ for (i = 0; i < pnote->descsz && pnote->descdata[i] != '\0'; ++i) ++ printf ("%c", pnote->descdata[i]); ++ printf ("\n"); ++ } ++ break; + } + + return 1; @@ -268498,12 +270717,12 @@ index 0000000..7d228d6 +} diff --git a/binutils/rename.c b/binutils/rename.c new file mode 100644 -index 0000000..5923a3f +index 0000000..41698f7 --- /dev/null +++ b/binutils/rename.c @@ -0,0 +1,212 @@ +/* rename.c -- rename a file, preserving symlinks. -+ Copyright 1999, 2002, 2003, 2005, 2007, 2008 Free Software Foundation, Inc. ++ Copyright (C) 1999-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -268716,13 +270935,12 @@ index 0000000..5923a3f +} diff --git a/binutils/resbin.c b/binutils/resbin.c new file mode 100644 -index 0000000..548ff38 +index 0000000..8684ae3 --- /dev/null +++ b/binutils/resbin.c -@@ -0,0 +1,2160 @@ +@@ -0,0 +1,2159 @@ +/* resbin.c -- manipulate the Windows binary resource format. -+ Copyright 1997, 1998, 1999, 2002, 2003, 2005, 2006, 2007, 2009, 2010, 2011 -+ Free Software Foundation, Inc. ++ Copyright (C) 1997-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor, Cygnus Support. + Rewritten by Kai Tietz, Onevision. + @@ -270882,12 +273100,12 @@ index 0000000..548ff38 +} diff --git a/binutils/rescoff.c b/binutils/rescoff.c new file mode 100644 -index 0000000..c594719 +index 0000000..607c823 --- /dev/null +++ b/binutils/rescoff.c @@ -0,0 +1,749 @@ +/* rescoff.c -- read and write resources in Windows COFF files. -+ Copyright 1997-2013 Free Software Foundation, Inc. ++ Copyright (C) 1997-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor, Cygnus Support. + Rewritten by Kai Tietz, Onevision. + @@ -271637,13 +273855,12 @@ index 0000000..c594719 +} diff --git a/binutils/resrc.c b/binutils/resrc.c new file mode 100644 -index 0000000..bfc3bd4 +index 0000000..65f1c11 --- /dev/null +++ b/binutils/resrc.c -@@ -0,0 +1,3374 @@ +@@ -0,0 +1,3373 @@ +/* resrc.c -- read and write Windows rc files. -+ Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007, 2008, 2011 -+ Free Software Foundation, Inc. ++ Copyright (C) 1997-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor, Cygnus Support. + Rewritten by Kai Tietz, Onevision. + @@ -275017,12 +277234,12 @@ index 0000000..bfc3bd4 +} diff --git a/binutils/resres.c b/binutils/resres.c new file mode 100644 -index 0000000..84f956f +index 0000000..03c42e6 --- /dev/null +++ b/binutils/resres.c @@ -0,0 +1,731 @@ +/* resres.c: read_res_file and write_res_file implementation for windres. -+ Copyright 1998-2013 Free Software Foundation, Inc. ++ Copyright (C) 1998-2014 Free Software Foundation, Inc. + Written by Anders Norlander . + Rewritten by Kai Tietz, Onevision. + @@ -275754,7 +277971,7 @@ index 0000000..84f956f +} diff --git a/binutils/sanity.sh b/binutils/sanity.sh new file mode 100755 -index 0000000..8edb490 +index 0000000..5fa0cfc --- /dev/null +++ b/binutils/sanity.sh @@ -0,0 +1,67 @@ @@ -275762,7 +277979,7 @@ index 0000000..8edb490 +### quick sanity test for the binutils. +### +# This file was written K. Richard Pixley. -+# Copyright 2007 Free Software Foundation, Inc. ++# Copyright (C) 2007-2014 Free Software Foundation, Inc. + +# This program is part of GNU Binutils. + @@ -275827,14 +278044,12 @@ index 0000000..8edb490 +exit 0 diff --git a/binutils/size.c b/binutils/size.c new file mode 100644 -index 0000000..0937de5 +index 0000000..e727165 --- /dev/null +++ b/binutils/size.c -@@ -0,0 +1,611 @@ +@@ -0,0 +1,609 @@ +/* size.c -- report size of various sections of an executable file. -+ Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, -+ 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 -+ Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -276444,13 +278659,12 @@ index 0000000..0937de5 +} diff --git a/binutils/srconv.c b/binutils/srconv.c new file mode 100644 -index 0000000..dcf33b9 +index 0000000..13119b4 --- /dev/null +++ b/binutils/srconv.c -@@ -0,0 +1,1893 @@ +@@ -0,0 +1,1892 @@ +/* srconv.c -- Sysroff conversion program -+ Copyright 1994, 1995, 1996, 1998, 1999, 2000, 2001, 2002, 2003, 2004, -+ 2005, 2007, 2008, 2009 Free Software Foundation, Inc. ++ Copyright (C) 1994-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -278343,13 +280557,12 @@ index 0000000..dcf33b9 +} diff --git a/binutils/stabs.c b/binutils/stabs.c new file mode 100644 -index 0000000..8b45977 +index 0000000..2a2674d --- /dev/null +++ b/binutils/stabs.c -@@ -0,0 +1,5433 @@ +@@ -0,0 +1,5432 @@ +/* stabs.c -- Parse stabs debugging information -+ Copyright 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, -+ 2005, 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. ++ Copyright (C) 1995-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor . + + This file is part of GNU Binutils. @@ -283789,14 +286002,12 @@ index 0000000..9788f70 +timestamp diff --git a/binutils/strings.c b/binutils/strings.c new file mode 100644 -index 0000000..d591630 +index 0000000..bb00d41 --- /dev/null +++ b/binutils/strings.c -@@ -0,0 +1,655 @@ +@@ -0,0 +1,653 @@ +/* strings -- print the strings of printable characters in files -+ Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, -+ 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2011, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1993-2014 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by @@ -284450,14 +286661,12 @@ index 0000000..d591630 +} diff --git a/binutils/sysdep.h b/binutils/sysdep.h new file mode 100644 -index 0000000..5164e79 +index 0000000..689e8c9 --- /dev/null +++ b/binutils/sysdep.h -@@ -0,0 +1,188 @@ +@@ -0,0 +1,190 @@ +/* sysdep.h -- handle host dependencies for binutils -+ Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, -+ 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -284570,6 +286779,10 @@ index 0000000..5164e79 +extern int vsnprintf(char *, size_t, const char *, va_list); +#endif + ++#if !HAVE_DECL_STRNLEN ++size_t strnlen (const char *, size_t); ++#endif ++ +#ifndef O_RDONLY +#define O_RDONLY 0 +#endif @@ -284644,13 +286857,12 @@ index 0000000..5164e79 +#endif /* _BIN_SYSDEP_H */ diff --git a/binutils/sysdump.c b/binutils/sysdump.c new file mode 100644 -index 0000000..4d5d38d +index 0000000..5ae324f --- /dev/null +++ b/binutils/sysdump.c -@@ -0,0 +1,719 @@ +@@ -0,0 +1,718 @@ +/* Sysroff object format dumper. -+ Copyright 1994, 1995, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007, -+ 2009, 2011 Free Software Foundation, Inc. ++ Copyright (C) 1994-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -285369,11 +287581,11 @@ index 0000000..4d5d38d +} diff --git a/binutils/sysinfo.y b/binutils/sysinfo.y new file mode 100644 -index 0000000..bab635e +index 0000000..b675491 --- /dev/null +++ b/binutils/sysinfo.y @@ -0,0 +1,429 @@ -+/* Copyright 2001, 2003, 2005, 2007, 2009 Free Software Foundation, Inc. ++/* Copyright (C) 2001-2014 Free Software Foundation, Inc. + Written by Steve Chamberlain of Cygnus Support (steve@cygnus.com). + + This file is part of GNU binutils. @@ -285804,14 +288016,14 @@ index 0000000..bab635e +} diff --git a/binutils/syslex.l b/binutils/syslex.l new file mode 100644 -index 0000000..14aee73 +index 0000000..0b99b1a --- /dev/null +++ b/binutils/syslex.l @@ -0,0 +1,85 @@ +%option noinput nounput + +%{ -+/* Copyright 2001, 2003, 2005, 2007, 2011, 2012 Free Software Foundation, Inc. ++/* Copyright (C) 2001-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -285895,11 +288107,11 @@ index 0000000..14aee73 +"repeat" { return REPEAT;} diff --git a/binutils/syslex_wrap.c b/binutils/syslex_wrap.c new file mode 100644 -index 0000000..49c65f6 +index 0000000..7d02616 --- /dev/null +++ b/binutils/syslex_wrap.c @@ -0,0 +1,25 @@ -+/* Copyright 2012 Free Software Foundation, Inc. ++/* Copyright (C) 2012-2014 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by @@ -286436,10 +288648,48 @@ index 0000000..390fe42 + diff --git a/binutils/testsuite/ChangeLog b/binutils/testsuite/ChangeLog new file mode 100644 -index 0000000..45defaf +index 0000000..9e98d0c --- /dev/null +++ b/binutils/testsuite/ChangeLog -@@ -0,0 +1,315 @@ +@@ -0,0 +1,353 @@ ++2014-06-03 Nick Clifton ++ ++ * binutils-all/ar.exp: Skip tests involving bfdtest1 and bfdtest2 ++ if these executables are not present. ++ ++2014-04-30 Nick Clifton ++ ++ * binutils-all/debug_str.s: New test. ++ * binutils-all/debug_str.d: New test control file. ++ * binutils-all/compress.exp: Run debug_str test. ++ ++2014-04-22 Christian Svensson ++ ++ * binutils-all/objcopy.exp: Remove openrisc and or32 support. Add ++ support for or1k. ++ * binutils-all/objdump.exp: Likewise. ++ * binutils-all/dw2-decodedline-1.S: Likewise. ++ ++2014-03-26 Jiong Wang ++ ++ * binutils-all/aarch64/aarch64.exp: New test driver for AArch64. ++ * binutils-all/aarch64/unallocated-encoding.s: New testcase. ++ * binutils-all/aarch64/unallocated-encoding.d: Ditto. ++ ++2014-03-17 Nick Clifton ++ ++ * binutils-all/readelf.ss: Add skip of MSP430 defined symbols. ++ ++2014-01-29 Nick Clifton ++ ++ PR binutils/16318 ++ * binutils-all/strip-10.d: Revert previous delta. ++ ++2014-01-28 Nick Clifton ++ ++ PR binutils/16318 ++ * binutils-all/strip-10.d: Allow "System V" in the osabi field. ++ +2013-12-20 Nick Clifton + + PR binutils/16218 @@ -286743,7 +288993,7 @@ index 0000000..45defaf + +For older changes see ChangeLog-0411 + -+Copyright (C) 2012 Free Software Foundation, Inc. ++Copyright (C) 2012-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -288821,6 +291071,134 @@ index 0000000..54061d3 +fill-column: 74 +version-control: never +End: +diff --git a/binutils/testsuite/binutils-all/aarch64/aarch64.exp b/binutils/testsuite/binutils-all/aarch64/aarch64.exp +new file mode 100644 +index 0000000..e189711 +--- /dev/null ++++ b/binutils/testsuite/binutils-all/aarch64/aarch64.exp +@@ -0,0 +1,30 @@ ++# Copyright (C) 2014 Free Software Foundation, Inc. ++ ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 3 of the License, or ++# (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. ++ ++if {![istarget "aarch64*-*-*"] ++ || ![is_elf_format]} then { ++ return ++} ++ ++set tempfile tmpdir/aarch64temp.o ++set copyfile tmpdir/aarch64copy ++ ++set test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]] ++foreach t $test_list { ++ # We need to strip the ".d", but can leave the dirname. ++ verbose [file rootname $t] ++ run_dump_test [file rootname $t] ++} +diff --git a/binutils/testsuite/binutils-all/aarch64/unallocated-encoding.d b/binutils/testsuite/binutils-all/aarch64/unallocated-encoding.d +new file mode 100644 +index 0000000..64063e2 +--- /dev/null ++++ b/binutils/testsuite/binutils-all/aarch64/unallocated-encoding.d +@@ -0,0 +1,29 @@ ++#PROG: objcopy ++#objdump: -dr ++#name: Disassembler detects unallocated instruction encodings. ++ ++.*: +file format .*aarch64.* ++ ++Disassembly of section \.text: ++ ++0000000000000000 <.*>: ++ 0: 0d0047de .inst 0x0d0047de ; undefined ++ 4: 0d2047dd .inst 0x0d2047dd ; undefined ++ 8: 0d0067dc .inst 0x0d0067dc ; undefined ++ c: 0d2067db .inst 0x0d2067db ; undefined ++ 10: 0d008bde .inst 0x0d008bde ; undefined ++ 14: 0d208bdd .inst 0x0d208bdd ; undefined ++ 18: 0d00abdc .inst 0x0d00abdc ; undefined ++ 1c: 0d20abdb .inst 0x0d20abdb ; undefined ++ 20: 0d008fde .inst 0x0d008fde ; undefined ++ 24: 0d208fdd .inst 0x0d208fdd ; undefined ++ 28: 0d00afdc .inst 0x0d00afdc ; undefined ++ 2c: 0d20afdb .inst 0x0d20afdb ; undefined ++ 30: 0d0097de .inst 0x0d0097de ; undefined ++ 34: 0d2097dd .inst 0x0d2097dd ; undefined ++ 38: 0d00b7dc .inst 0x0d00b7dc ; undefined ++ 3c: 0d20b7db .inst 0x0d20b7db ; undefined ++ 40: 0d009fde .inst 0x0d009fde ; undefined ++ 44: 0d209fdd .inst 0x0d209fdd ; undefined ++ 48: 0d00bfdc .inst 0x0d00bfdc ; undefined ++ 4c: 0d20bfdb .inst 0x0d20bfdb ; undefined +diff --git a/binutils/testsuite/binutils-all/aarch64/unallocated-encoding.s b/binutils/testsuite/binutils-all/aarch64/unallocated-encoding.s +new file mode 100644 +index 0000000..fb96adc +--- /dev/null ++++ b/binutils/testsuite/binutils-all/aarch64/unallocated-encoding.s +@@ -0,0 +1,51 @@ ++ .text ++func: ++ //scale 1, size<0> check for H. ++ #st1 {v30.h}[0], [x30] ++ .inst 0x0d0043de | (1 << 10) ++ #st2 {v29.h, v30.h}[0], [x30] ++ .inst 0x0d2043dd | (1 << 10) ++ #st3 {v28.h, v29.h, v30.h}[0], [x30] ++ .inst 0x0d0063dc | (1 << 10) ++ #st4 {v27.h, v28.h, v29.h, v30.h}[0], [x30] ++ .inst 0x0d2063db | (1 << 10) ++ ++ //scale 2, size<1> check for S. ++ #st1 {v30.s}[0], [x30] ++ .inst 0x0d0083de | (1 << 11) ++ #st2 {v29.s, v30.s}[0], [x30] ++ .inst 0x0d2083dd | (1 << 11) ++ #st3 {v28.s, v29.s, v30.s}[0], [x30] ++ .inst 0x0d00a3dc | (1 << 11) ++ #st4 {v27.s, v28.s, v29.s, v30.s}[0], [x30] ++ .inst 0x0d20a3db | (1 << 11) ++ ++ //scale 2, size<1> check for D. ++ #st1 {v30.d}[0], [x30] ++ .inst 0x0d0087de | (1 << 11) ++ #st2 {v29.d, v30.d}[0], [x30] ++ .inst 0x0d2087dd | (1 << 11) ++ #st3 {v28.d, v29.d, v30.d}[0], [x30] ++ .inst 0x0d00a7dc | (1 << 11) ++ #st4 {v27.d, v28.d, v29.d, v30.d}[0], [x30] ++ .inst 0x0d20a7db | (1 << 11) ++ ++ //scale 2, S-bit check for D. ++ #st1 {v30.d}[0], [x30] ++ .inst 0x0d0087de | (2 << 11) ++ #st2 {v29.d, v30.d}[0], [x30] ++ .inst 0x0d2087dd | (2 << 11) ++ #st3 {v28.d, v29.d, v30.d}[0], [x30] ++ .inst 0x0d00a7dc | (2 << 11) ++ #st4 {v27.d, v28.d, v29.d, v30.d}[0], [x30] ++ .inst 0x0d20a7db | (2 << 11) ++ ++ //scale 2, size<1> & S-bit check for D. ++ #st1 {v30.d}[0], [x30] ++ .inst 0x0d0087de | (3 << 11) ++ #st2 {v29.d, v30.d}[0], [x30] ++ .inst 0x0d2087dd | (3 << 11) ++ #st3 {v28.d, v29.d, v30.d}[0], [x30] ++ .inst 0x0d00a7dc | (3 << 11) ++ #st4 {v27.d, v28.d, v29.d, v30.d}[0], [x30] ++ .inst 0x0d20a7db | (3 << 11) diff --git a/binutils/testsuite/binutils-all/add-empty-section.d b/binutils/testsuite/binutils-all/add-empty-section.d new file mode 100644 index 0000000..c9162a5 @@ -288871,12 +291249,11 @@ index 0000000..d59d4a0 +symbol=nothing diff --git a/binutils/testsuite/binutils-all/ar.exp b/binutils/testsuite/binutils-all/ar.exp new file mode 100644 -index 0000000..6efc159 +index 0000000..21b7a69 --- /dev/null +++ b/binutils/testsuite/binutils-all/ar.exp -@@ -0,0 +1,575 @@ -+# Copyright 1995, 1997, 2002, 2004, 2007, 2008, 2009, 2010, 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,582 @@ ++# Copyright (C) 1995-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -289435,16 +291812,24 @@ index 0000000..6efc159 + +# Run the tests. + -+set bfdtests [list bfdtest1 bfdtest2] ++# Only run the bfdtest checks if the programs exist. Since these ++# programs are built but not installed, running the testsuite on an ++# installed toolchain will produce ERRORs about missing bfdtest1 and ++# bfdtest2 executables. ++if { [file exists $base_dir/bfdtest1] && [file exists $base_dir/bfdtest2] } { ++ set bfdtests [list bfdtest1 bfdtest2] ++ ++ long_filenames $bfdtests ++ thin_archive $bfdtests ++ thin_archive_with_nested $bfdtests ++} + -+long_filenames $bfdtests +symbol_table -+thin_archive $bfdtests -+thin_archive_with_nested $bfdtests +argument_parsing +deterministic_archive +delete_an_element +move_an_element ++ +if { [is_elf_format] + && ![istarget "*-*-hpux*"] + && ![istarget "msp*-*-*"] } { @@ -289452,12 +291837,11 @@ index 0000000..6efc159 +} diff --git a/binutils/testsuite/binutils-all/arm/objdump.exp b/binutils/testsuite/binutils-all/arm/objdump.exp new file mode 100644 -index 0000000..321e2a9 +index 0000000..93c44da --- /dev/null +++ b/binutils/testsuite/binutils-all/arm/objdump.exp -@@ -0,0 +1,89 @@ -+# Copyright 2004, 2007, 2009 -+# Free Software Foundation, Inc. +@@ -0,0 +1,88 @@ ++# Copyright (C) 2004-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -289602,12 +291986,11 @@ index 0000000..b9de442 + bx lr diff --git a/binutils/testsuite/binutils-all/bfin/objdump.exp b/binutils/testsuite/binutils-all/bfin/objdump.exp new file mode 100644 -index 0000000..df7d4da +index 0000000..ba803ee --- /dev/null +++ b/binutils/testsuite/binutils-all/bfin/objdump.exp -@@ -0,0 +1,53 @@ -+# Copyright 2009 -+# Free Software Foundation, Inc. +@@ -0,0 +1,52 @@ ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -289693,12 +292076,11 @@ index 0000000..9e00650 + .comm common_symbol,4 diff --git a/binutils/testsuite/binutils-all/compress.exp b/binutils/testsuite/binutils-all/compress.exp new file mode 100644 -index 0000000..8cf6138 +index 0000000..d74555d --- /dev/null +++ b/binutils/testsuite/binutils-all/compress.exp -@@ -0,0 +1,176 @@ -+# Copyright 2010, 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,185 @@ ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -289873,6 +292255,16 @@ index 0000000..8cf6138 + fail "objcopy ($testname)" + } +} ++ ++if ![is_remote host] { ++ set tempfile tmpdir/debug_str.o ++ set copyfile tmpdir/debug_str.copy ++} else { ++ set tempfile [remote_download host tmpdir/debug_str.o] ++ set copyfile debug_str.copy ++} ++ ++run_dump_test "debug_str" diff --git a/binutils/testsuite/binutils-all/copy-1.d b/binutils/testsuite/binutils-all/copy-1.d new file mode 100644 index 0000000..f2b0d9e @@ -289979,13 +292371,46 @@ index 0000000..33c13b8 + .section bar +bar_symbol: + .long 2 +diff --git a/binutils/testsuite/binutils-all/debug_str.d b/binutils/testsuite/binutils-all/debug_str.d +new file mode 100644 +index 0000000..eda1db1 +--- /dev/null ++++ b/binutils/testsuite/binutils-all/debug_str.d +@@ -0,0 +1,9 @@ ++#PROG: objcopy ++#source: debug_str.s ++#objdump: -h ++#name: Uncompressed .debug_str section starting with ZLIB ++ ++.*ebug_str.copy.o: file format .* ++#... ++ . .debug_str 0+01. 0+0 0+0 0+0.. 2..0 ++#... +diff --git a/binutils/testsuite/binutils-all/debug_str.s b/binutils/testsuite/binutils-all/debug_str.s +new file mode 100644 +index 0000000..485d0cc +--- /dev/null ++++ b/binutils/testsuite/binutils-all/debug_str.s +@@ -0,0 +1,12 @@ ++/* This test is derived from a C source file which, when compiled by gcc ++ with debugging enabled, managed to create a .debug_str section whose ++ first string was ZLIB_VER_SUBVERSION. The code in bfd/compress.c ++ used to just check for the characters "ZLIB" at the start of a section ++ and then assume that the section was compressed. This meant that the BFD ++ library then processed the next 8 bytes as if they were the size of the ++ decompressed version of the section. Naturally with this test case the ++ resulting size was gigantic and consequently the library quickly ran out ++ of memory. */ ++ ++ .section .debug_str,"MS",@progbits,1 ++ .string "ZLIB_VER_SUBREVISION 0" diff --git a/binutils/testsuite/binutils-all/dlltool.exp b/binutils/testsuite/binutils-all/dlltool.exp new file mode 100644 -index 0000000..e0385d7 +index 0000000..169fe2c --- /dev/null +++ b/binutils/testsuite/binutils-all/dlltool.exp @@ -0,0 +1,282 @@ -+# Copyright 2002, 2004, 2006, 2007, 2009 Free Software Foundation, Inc. ++# Copyright (C) 2002-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -290277,13 +292702,13 @@ index 0000000..6335d22 + .ascii "test_string" diff --git a/binutils/testsuite/binutils-all/dw2-1.S b/binutils/testsuite/binutils-all/dw2-1.S new file mode 100644 -index 0000000..ed46cd0 +index 0000000..234b11b --- /dev/null +++ b/binutils/testsuite/binutils-all/dw2-1.S @@ -0,0 +1,198 @@ +/* This testcase is derived from a similar test in GDB. + -+ Copyright 2008, 2009, 2010 Free Software Foundation, Inc. ++ Copyright (C) 2008-2014 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by @@ -290590,13 +293015,13 @@ index 0000000..3811019 + diff --git a/binutils/testsuite/binutils-all/dw2-2.S b/binutils/testsuite/binutils-all/dw2-2.S new file mode 100644 -index 0000000..d9046a9 +index 0000000..e792e8a --- /dev/null +++ b/binutils/testsuite/binutils-all/dw2-2.S @@ -0,0 +1,195 @@ +/* This testcase is derived from a similar test in GDB. + -+ Copyright 2008, 2009, 2010 Free Software Foundation, Inc. ++ Copyright (C) 2008-2014 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by @@ -290791,13 +293216,13 @@ index 0000000..d9046a9 + .byte 0x0 /* Terminator */ diff --git a/binutils/testsuite/binutils-all/dw2-compressed.S b/binutils/testsuite/binutils-all/dw2-compressed.S new file mode 100644 -index 0000000..37ba916 +index 0000000..b38961a --- /dev/null +++ b/binutils/testsuite/binutils-all/dw2-compressed.S @@ -0,0 +1,218 @@ +/* This testcase is derived from a similar test in GDB. + -+ Copyright 2008, 2009 Free Software Foundation, Inc. ++ Copyright (C) 2008-2014 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by @@ -291013,6 +293438,28 @@ index 0000000..37ba916 + .byte 0x9c + .byte 0x00 + .byte 0x92 +diff --git a/binutils/testsuite/binutils-all/dw2-decodedline-1.S b/binutils/testsuite/binutils-all/dw2-decodedline-1.S +new file mode 100644 +index 0000000..aa94ded +--- /dev/null ++++ b/binutils/testsuite/binutils-all/dw2-decodedline-1.S +@@ -0,0 +1,16 @@ ++ .file "dw2-decodedline.c" ++ .file 1 "dw2-decodedline.c" ++ .file 2 "directory/file1.c" ++ .text ++.globl f1 ++ .type f1, %function ++f1: ++ .loc 2 1 0 ++ l.nop ++ .size f1, .-f1 ++.globl main ++ .type main, %function ++main: ++ .loc 1 2 0 ++ l.nop ++ .size main, .-main diff --git a/binutils/testsuite/binutils-all/dw2-decodedline.S b/binutils/testsuite/binutils-all/dw2-decodedline.S new file mode 100644 index 0000000..a54bdcf @@ -291131,12 +293578,11 @@ index 0000000..4336dd8 +#... diff --git a/binutils/testsuite/binutils-all/elfedit.exp b/binutils/testsuite/binutils-all/elfedit.exp new file mode 100644 -index 0000000..500906d +index 0000000..c5465dc --- /dev/null +++ b/binutils/testsuite/binutils-all/elfedit.exp -@@ -0,0 +1,35 @@ -+# Copyright 2010, 2011 -+# Free Software Foundation, Inc. +@@ -0,0 +1,34 @@ ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -291422,12 +293868,11 @@ index 0000000..501e10f + .PROCEND diff --git a/binutils/testsuite/binutils-all/hppa/objdump.exp b/binutils/testsuite/binutils-all/hppa/objdump.exp new file mode 100644 -index 0000000..c6d1640 +index 0000000..833230b --- /dev/null +++ b/binutils/testsuite/binutils-all/hppa/objdump.exp -@@ -0,0 +1,96 @@ -+# Copyright 1993, 1994, 1995, 1997, 1999, 2000, 2002, 2007, 2009 -+# Free Software Foundation, Inc. +@@ -0,0 +1,95 @@ ++# Copyright (C) 1993-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -291891,12 +294336,11 @@ index 0000000..f05380f +#... diff --git a/binutils/testsuite/binutils-all/i386/i386.exp b/binutils/testsuite/binutils-all/i386/i386.exp new file mode 100644 -index 0000000..4b9fffd +index 0000000..7b85ba4 --- /dev/null +++ b/binutils/testsuite/binutils-all/i386/i386.exp -@@ -0,0 +1,38 @@ -+# Copyright 2010, 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,37 @@ ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -292087,12 +294531,11 @@ index 0000000..b3718d5 + movem.l %d0-%d3,(%sp) diff --git a/binutils/testsuite/binutils-all/m68k/objdump.exp b/binutils/testsuite/binutils-all/m68k/objdump.exp new file mode 100644 -index 0000000..5043ef7 +index 0000000..c50009b --- /dev/null +++ b/binutils/testsuite/binutils-all/m68k/objdump.exp -@@ -0,0 +1,79 @@ -+# Copyright 2004, 2007, 2009, 2010 -+# Free Software Foundation, Inc. +@@ -0,0 +1,78 @@ ++# Copyright (C) 2004-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -292172,12 +294615,11 @@ index 0000000..5043ef7 +} diff --git a/binutils/testsuite/binutils-all/mips/mips.exp b/binutils/testsuite/binutils-all/mips/mips.exp new file mode 100644 -index 0000000..eba8868 +index 0000000..b325307 --- /dev/null +++ b/binutils/testsuite/binutils-all/mips/mips.exp -@@ -0,0 +1,26 @@ -+# Copyright 2013 -+# Free Software Foundation, Inc. +@@ -0,0 +1,25 @@ ++# Copyright (C) 2013-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -292411,11 +294853,11 @@ index 0000000..8e2f1f4 + .size text_symbol3, . - text_symbol3 diff --git a/binutils/testsuite/binutils-all/nm.exp b/binutils/testsuite/binutils-all/nm.exp new file mode 100644 -index 0000000..e9e7f5f +index 0000000..1a5667b --- /dev/null +++ b/binutils/testsuite/binutils-all/nm.exp @@ -0,0 +1,209 @@ -+# Copyright 1993, 1994, 1995, 1997, 2007, 2009 Free Software Foundation, Inc. ++# Copyright (C) 1993-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -292645,13 +295087,11 @@ index 0000000..17a7d59 +#... diff --git a/binutils/testsuite/binutils-all/objcopy.exp b/binutils/testsuite/binutils-all/objcopy.exp new file mode 100644 -index 0000000..dca962d +index 0000000..a7e1396 --- /dev/null +++ b/binutils/testsuite/binutils-all/objcopy.exp -@@ -0,0 +1,1007 @@ -+# Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, -+# 2004, 2006, 2007, 2009, 2010, 2011 -+# Free Software Foundation, Inc. +@@ -0,0 +1,1004 @@ ++# Copyright (C) 1994-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -292737,7 +295177,6 @@ index 0000000..dca962d + setup_xfail "m68*-*-*coff" "m68*-*-hpux*" "m68*-*-lynxos*" + setup_xfail "m68*-*-sysv*" "m68*-apple-aux*" + setup_xfail "m8*-*" -+ setup_xfail "or32-*-rtems*" "or32-*-coff" + setup_xfail "sh-*-coff*" + setup_xfail "tic80-*-*" "w65-*" + @@ -293634,10 +296073,10 @@ index 0000000..dca962d + # The symbol table for some MIPS targets is sorted differently than + # the ELF canonical order, so the regexps in localize-hidden-1.d fail + # to match. These tests must be matched to targets for which -+ # targ_defvec=bfd_elf32_bigmips_vec, -+ # targ_defvec=bfd_elf32_littlemips_vec, -+ # targ_defvec=bfd_elf32_nbigmips_vec or -+ # targ_defvec=bfd_elf32_nlittlemips_vec in config.bfd. When syncing, ++ # targ_defvec=mips_elf32_be_vec, ++ # targ_defvec=mips_elf32_le_vec, ++ # targ_defvec=mips_elf32_n_be_vec or ++ # targ_defvec=mips_elf32_n_le_vec in config.bfd. When syncing, + # don't forget that earlier case-matches trump later ones. + if { ![istarget "mips*-sde-elf*"] && ![istarget "mips*-mti-elf*"] + && ![istarget "mips64*-*-openbsd*"] } { @@ -293788,13 +296227,11 @@ index 0000000..3846f4f + diff --git a/binutils/testsuite/binutils-all/objdump.exp b/binutils/testsuite/binutils-all/objdump.exp new file mode 100644 -index 0000000..aa1ff2c +index 0000000..430ba93 --- /dev/null +++ b/binutils/testsuite/binutils-all/objdump.exp -@@ -0,0 +1,249 @@ -+# Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, -+# 2003, 2004, 2007, 2008, 2009, 2011, 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,250 @@ ++# Copyright (C) 1993-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -293833,8 +296270,8 @@ index 0000000..aa1ff2c +lappend cpus_expected aarch64 alpha arc arm cris +lappend cpus_expected d10v d30v fr30 fr500 fr550 h8 hppa i386 i860 i960 ip2022 +lappend cpus_expected m16c m32c m32r m68hc11 m68hc12 m68k m88k MCore MicroBlaze -+lappend cpus_expected mips mn10200 mn10300 ms1 msp MSP430 nds32 n1h_v3 ns32k -+lappend cpus_expected pj powerpc pyramid romp rs6000 s390 sh sparc ++lappend cpus_expected mips mn10200 mn10300 ms1 msp MSP430 nds32 n1h_v3 ns32k ++lappend cpus_expected or1k or1knd pj powerpc pyramid romp rs6000 s390 sh sparc +lappend cpus_expected tahoe tic54x tic80 tilegx tms320c30 tms320c4x tms320c54x +lappend cpus_expected v850 vax we32k x86-64 xscale xtensa z8k z8001 z8002 + @@ -293997,7 +296434,7 @@ index 0000000..aa1ff2c +} + +# Test objdump -WL on a file that contains line information for multiple files and search directories. -+# Not supported on mcore, moxie and openrisc targets because they do not (yet) support the generation ++# Not supported on mcore and moxie targets because they do not (yet) support the generation +# of DWARF2 line debug information. + +if { ![is_elf_format] @@ -294007,12 +296444,15 @@ index 0000000..aa1ff2c + || [istarget "ia64*-*-*"] + || [istarget "mcore-*-*"] + || [istarget "moxie-*-*"] -+ || [istarget "openrisc-*-*"] -+ || [istarget "or32-*-*"] +} then { + unsupported "objump decode line" +} else { -+ if { ![binutils_assemble $srcdir/$subdir/dw2-decodedline.S tmpdir/dw2-decodedline.o] } then { ++ if { [istarget "or1k*-*-*"] } then { ++ set decodedline_testsrc $srcdir/$subdir/dw2-decodedline-1.S ++ } else { ++ set decodedline_testsrc $srcdir/$subdir/dw2-decodedline.S ++ } ++ if { ![binutils_assemble $decodedline_testsrc tmpdir/dw2-decodedline.o] } then { + fail "objdump decoded line" + } + @@ -294058,11 +296498,11 @@ index 0000000..aea35df + 0040 e6e0e6b6 e3660002 00049c00 92 .....f....... diff --git a/binutils/testsuite/binutils-all/readelf.exp b/binutils/testsuite/binutils-all/readelf.exp new file mode 100644 -index 0000000..9a3e6bd +index 0000000..2a6bc6a --- /dev/null +++ b/binutils/testsuite/binutils-all/readelf.exp @@ -0,0 +1,362 @@ -+# Copyright 1999-2013 Free Software Foundation, Inc. ++# Copyright (C) 1999-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -294541,10 +296981,10 @@ index 0000000..2e05d68 +#... diff --git a/binutils/testsuite/binutils-all/readelf.ss b/binutils/testsuite/binutils-all/readelf.ss new file mode 100644 -index 0000000..9bb0f2e +index 0000000..e9ab3ef --- /dev/null +++ b/binutils/testsuite/binutils-all/readelf.ss -@@ -0,0 +1,18 @@ +@@ -0,0 +1,20 @@ + +Symbol table '.symtab' contains .* entries: + +Num: +Value +Size +Type +Bind +Vis +Ndx +Name @@ -294563,6 +297003,8 @@ index 0000000..9bb0f2e + +..: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +UND external_symbol + +..: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +[34] data_symbol + +..: 00000004 +4 +(COMMON|OBJECT) +GLOBAL +DEFAULT +(COM|ANSI_COM) common_symbol ++# The MSP430 adds special crt0 symbols here. ++#... diff --git a/binutils/testsuite/binutils-all/readelf.ss-64 b/binutils/testsuite/binutils-all/readelf.ss-64 new file mode 100644 index 0000000..c100c14 @@ -294659,12 +297101,11 @@ index 0000000..43d60b1 + diff --git a/binutils/testsuite/binutils-all/size.exp b/binutils/testsuite/binutils-all/size.exp new file mode 100644 -index 0000000..5050a54 +index 0000000..47cf91b --- /dev/null +++ b/binutils/testsuite/binutils-all/size.exp -@@ -0,0 +1,82 @@ -+# Copyright 1993, 1994, 1995, 1997, 1998, 2007, 2009 -+# Free Software Foundation, Inc. +@@ -0,0 +1,81 @@ ++# Copyright (C) 1993-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -295190,13 +297631,12 @@ index 0000000..18f9010 + diff --git a/binutils/testsuite/binutils-all/vax/objdump.exp b/binutils/testsuite/binutils-all/vax/objdump.exp new file mode 100644 -index 0000000..f4734a5 +index 0000000..1cbbedd --- /dev/null +++ b/binutils/testsuite/binutils-all/vax/objdump.exp -@@ -0,0 +1,64 @@ +@@ -0,0 +1,63 @@ +# -+# Copyright 1993, 1994, 1995, 1997, 1999, 2000, 2002, 2005, 2007, 2009 -+# Free Software Foundation, Inc. ++# Copyright (C) 1993-2014 Free Software Foundation, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -295294,7 +297734,7 @@ index 0000000..0092b83 Binary files /dev/null and b/binutils/testsuite/binutils-all/windres/MSG00001.bin differ diff --git a/binutils/testsuite/binutils-all/windres/README b/binutils/testsuite/binutils-all/windres/README new file mode 100644 -index 0000000..6711446 +index 0000000..4658cb3 --- /dev/null +++ b/binutils/testsuite/binutils-all/windres/README @@ -0,0 +1,33 @@ @@ -295326,7 +297766,7 @@ index 0000000..6711446 +The windres tests only run for ix86 targets, because the +MSVC-generated *.rsd files are generated for that. + -+Copyright (C) 2012 Free Software Foundation, Inc. ++Copyright (C) 2012-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -295502,14 +297942,14 @@ index 0000000..270b622 + 0070 4b000000 00000000 K....... diff --git a/binutils/testsuite/binutils-all/windres/dialog0.rc b/binutils/testsuite/binutils-all/windres/dialog0.rc new file mode 100644 -index 0000000..2e0bf4d +index 0000000..fba7ed7 --- /dev/null +++ b/binutils/testsuite/binutils-all/windres/dialog0.rc @@ -0,0 +1,4 @@ -+101 DIALOG 0, 0, 186, 95 -+BEGIN -+ DEFPUSHBUTTON "OK", 1, 129, 7, 50, 14 -+END ++101 DIALOG 0, 0, 186, 95 ++BEGIN ++ DEFPUSHBUTTON "OK", 1, 129, 7, 50, 14 ++END diff --git a/binutils/testsuite/binutils-all/windres/dialog0.rsd b/binutils/testsuite/binutils-all/windres/dialog0.rsd new file mode 100644 index 0000000..270b622 @@ -295526,15 +297966,15 @@ index 0000000..270b622 + 0070 4b000000 00000000 K....... diff --git a/binutils/testsuite/binutils-all/windres/dialog1.rc b/binutils/testsuite/binutils-all/windres/dialog1.rc new file mode 100644 -index 0000000..31ffc8e +index 0000000..71deb4a --- /dev/null +++ b/binutils/testsuite/binutils-all/windres/dialog1.rc @@ -0,0 +1,5 @@ -+101 DIALOG DISCARDABLE 0, 0, 186, 95 -+BEGIN -+ DEFPUSHBUTTON "OK", 1, 129, 7, 50, 14 -+END -+ ++101 DIALOG DISCARDABLE 0, 0, 186, 95 ++BEGIN ++ DEFPUSHBUTTON "OK", 1, 129, 7, 50, 14 ++END ++ diff --git a/binutils/testsuite/binutils-all/windres/dialog1.rsd b/binutils/testsuite/binutils-all/windres/dialog1.rsd new file mode 100644 index 0000000..270b622 @@ -295857,38 +298297,38 @@ index 0000000..c124a82 + 0280 746d6c3e tml> diff --git a/binutils/testsuite/binutils-all/windres/html1.hm b/binutils/testsuite/binutils-all/windres/html1.hm new file mode 100644 -index 0000000..ae9cc85 +index 0000000..ffc5a18 --- /dev/null +++ b/binutils/testsuite/binutils-all/windres/html1.hm @@ -0,0 +1,11 @@ -+ -+ -+ -+ -+ Windres -+ -+ -+ -+This is a test page for windres HTML resource. -+ ++ ++ ++ ++ ++ Windres ++ ++ ++ ++This is a test page for windres HTML resource. ++ + \ No newline at end of file diff --git a/binutils/testsuite/binutils-all/windres/html2.hm b/binutils/testsuite/binutils-all/windres/html2.hm new file mode 100644 -index 0000000..77f6de0 +index 0000000..2fb343b --- /dev/null +++ b/binutils/testsuite/binutils-all/windres/html2.hm @@ -0,0 +1,11 @@ -+ -+ -+ -+ -+ Windres -+ -+ -+ -+This is a second test page for windres HTML resource. -+ ++ ++ ++ ++ ++ Windres ++ ++ ++ ++This is a second test page for windres HTML resource. ++ + \ No newline at end of file diff --git a/binutils/testsuite/binutils-all/windres/lang.rc b/binutils/testsuite/binutils-all/windres/lang.rc @@ -295986,12 +298426,12 @@ index 0000000..9d108a5 + 00a0 10000000 25310d0a 25320d0a 00000000 ....%1..%2...... diff --git a/binutils/testsuite/binutils-all/windres/msupdate b/binutils/testsuite/binutils-all/windres/msupdate new file mode 100755 -index 0000000..94d3698 +index 0000000..f723c97 --- /dev/null +++ b/binutils/testsuite/binutils-all/windres/msupdate @@ -0,0 +1,40 @@ +#!/bin/sh -+# Copyright 2001, 2007, 2009 Free Software Foundation, Inc. ++# Copyright (C) 2001-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -296696,11 +299136,11 @@ index 0000000..141ddb1 + 0320 6f006e00 00000000 0704e404 o.n......... diff --git a/binutils/testsuite/binutils-all/windres/windres.exp b/binutils/testsuite/binutils-all/windres/windres.exp new file mode 100644 -index 0000000..9f8dd25 +index 0000000..77ef7b8 --- /dev/null +++ b/binutils/testsuite/binutils-all/windres/windres.exp @@ -0,0 +1,178 @@ -+# Copyright 2001, 2003, 2004, 2006, 2007, 2009 Free Software Foundation, Inc. ++# Copyright (C) 2001-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -297239,12 +299679,11 @@ index 0000000..a0308c8 +#... diff --git a/binutils/testsuite/binutils-all/x86-64/x86-64.exp b/binutils/testsuite/binutils-all/x86-64/x86-64.exp new file mode 100644 -index 0000000..ccabc63 +index 0000000..0bb1c9f --- /dev/null +++ b/binutils/testsuite/binutils-all/x86-64/x86-64.exp -@@ -0,0 +1,34 @@ -+# Copyright 2010, 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,33 @@ ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -297279,12 +299718,11 @@ index 0000000..ccabc63 +} diff --git a/binutils/testsuite/config/default.exp b/binutils/testsuite/config/default.exp new file mode 100644 -index 0000000..c5595a1 +index 0000000..4694863 --- /dev/null +++ b/binutils/testsuite/config/default.exp -@@ -0,0 +1,135 @@ -+# Copyright 1993, 1994, 1995, 1997, 1999, 2001, 2002, 2004, 2005, 2007, 2009 -+# Free Software Foundation, Inc. +@@ -0,0 +1,134 @@ ++# Copyright (C) 1993-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -297430,12 +299868,11 @@ index 0000000..5b1b808 +s/ \.comm common_symbol,4/common_symbol .comm 4/ diff --git a/binutils/testsuite/lib/binutils-common.exp b/binutils/testsuite/lib/binutils-common.exp new file mode 100644 -index 0000000..af0040e +index 0000000..14a8122 --- /dev/null +++ b/binutils/testsuite/lib/binutils-common.exp -@@ -0,0 +1,342 @@ -+# Copyright 1993, 1994, 1995, 1996, 1997, 2000, 2001, 2003, 2004, 2006, 2007, -+# 2009, 2010, 2011, 2012 Free Software Foundation, Inc. +@@ -0,0 +1,341 @@ ++# Copyright (C) 1993-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -297778,12 +300215,11 @@ index 0000000..af0040e +} diff --git a/binutils/testsuite/lib/utils-lib.exp b/binutils/testsuite/lib/utils-lib.exp new file mode 100644 -index 0000000..3fe6c14 +index 0000000..b7f5101 --- /dev/null +++ b/binutils/testsuite/lib/utils-lib.exp -@@ -0,0 +1,558 @@ -+# Copyright 1993, 1994, 1995, 1996, 1997, 2000, 2001, 2003, 2004, 2006, 2007, -+# 2009, 2010, 2012 Free Software Foundation, Inc. +@@ -0,0 +1,557 @@ ++# Copyright (C) 1993-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -298342,13 +300778,12 @@ index 0000000..3fe6c14 +} diff --git a/binutils/unwind-ia64.c b/binutils/unwind-ia64.c new file mode 100644 -index 0000000..249114f +index 0000000..642f9b2 --- /dev/null +++ b/binutils/unwind-ia64.c -@@ -0,0 +1,1086 @@ +@@ -0,0 +1,1085 @@ +/* unwind-ia64.c -- utility routines to dump IA-64 unwind info for readelf. -+ Copyright 2000, 2001, 2002, 2003, 2005, 2007, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + + Contributed by David Mosberger-Tang + @@ -299434,12 +301869,12 @@ index 0000000..249114f +} diff --git a/binutils/unwind-ia64.h b/binutils/unwind-ia64.h new file mode 100644 -index 0000000..b004bc3 +index 0000000..a1cfa34 --- /dev/null +++ b/binutils/unwind-ia64.h @@ -0,0 +1,32 @@ +/* unwind-ia64.h -- dump IA-64 unwind info. -+ Copyright 2000, 2001, 2002, 2003, 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of GNU Binutils. @@ -299472,14 +301907,12 @@ index 0000000..b004bc3 +extern const unsigned char *unw_decode (const unsigned char *, int, void *); diff --git a/binutils/version.c b/binutils/version.c new file mode 100644 -index 0000000..332dff1 +index 0000000..fab6bf9 --- /dev/null +++ b/binutils/version.c -@@ -0,0 +1,42 @@ +@@ -0,0 +1,40 @@ +/* version.c -- binutils version information -+ Copyright 1991, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, -+ 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 -+ Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -299511,7 +301944,7 @@ index 0000000..332dff1 + /* This output is intended to follow the GNU standards document. */ + /* xgettext:c-format */ + printf ("GNU %s %s\n", name, BFD_VERSION_STRING); -+ printf (_("Copyright 2013 Free Software Foundation, Inc.\n")); ++ printf (_("Copyright (C) 2014 Free Software Foundation, Inc.\n")); + printf (_("\ +This program is free software; you may redistribute it under the terms of\n\ +the GNU General Public License version 3 or (at your option) any later version.\n\ @@ -299520,13 +301953,12 @@ index 0000000..332dff1 +} diff --git a/binutils/windint.h b/binutils/windint.h new file mode 100644 -index 0000000..0a75899 +index 0000000..cfbfb7a --- /dev/null +++ b/binutils/windint.h -@@ -0,0 +1,1098 @@ +@@ -0,0 +1,1097 @@ +/* windint.h -- internal header file for windres program. -+ Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007, 2011 -+ Free Software Foundation, Inc. ++ Copyright (C) 1997-2014 Free Software Foundation, Inc. + Written by Kai Tietz, Onevision. + + This file is part of GNU Binutils. @@ -300624,13 +303056,12 @@ index 0000000..0a75899 +#endif diff --git a/binutils/windmc.c b/binutils/windmc.c new file mode 100644 -index 0000000..e4f9b59 +index 0000000..01785db --- /dev/null +++ b/binutils/windmc.c -@@ -0,0 +1,1172 @@ +@@ -0,0 +1,1171 @@ +/* windmc.c -- a program to compile Windows message files. -+ Copyright 2007, 2008, 2009, 2010, 2011 -+ Free Software Foundation, Inc. ++ Copyright (C) 2007-2014 Free Software Foundation, Inc. + Written by Kai Tietz, Onevision. + + This file is part of GNU Binutils. @@ -301802,13 +304233,12 @@ index 0000000..e4f9b59 +} diff --git a/binutils/windmc.h b/binutils/windmc.h new file mode 100644 -index 0000000..9ce638f +index 0000000..5b556fa --- /dev/null +++ b/binutils/windmc.h -@@ -0,0 +1,99 @@ +@@ -0,0 +1,98 @@ +/* windmc.h -- header file for windmc program. -+ Copyright 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 2007-2014 Free Software Foundation, Inc. + Written by Kai Tietz, Onevision. + + This file is part of GNU Binutils. @@ -301907,12 +304337,12 @@ index 0000000..9ce638f +#endif diff --git a/binutils/windres.c b/binutils/windres.c new file mode 100644 -index 0000000..64afb3a +index 0000000..7fa90fc --- /dev/null +++ b/binutils/windres.c @@ -0,0 +1,1406 @@ +/* windres.c -- a program to manipulate Windows resources -+ Copyright 1997-2013 Free Software Foundation, Inc. ++ Copyright (C) 1997-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor, Cygnus Support. + Rewritten by Kai Tietz, Onevision. + @@ -303319,13 +305749,12 @@ index 0000000..64afb3a +} diff --git a/binutils/windres.h b/binutils/windres.h new file mode 100644 -index 0000000..bd6dd05 +index 0000000..2d0b3ff --- /dev/null +++ b/binutils/windres.h -@@ -0,0 +1,123 @@ +@@ -0,0 +1,122 @@ +/* windres.h -- header file for windres program. -+ Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007, 2011 -+ Free Software Foundation, Inc. ++ Copyright (C) 1997-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor, Cygnus Support. + Rewritten by Kai Tietz, Onevision. + @@ -303448,12 +305877,12 @@ index 0000000..bd6dd05 +#define wr_print_flush(FP) wr_print ((FP),NULL) diff --git a/binutils/winduni.c b/binutils/winduni.c new file mode 100644 -index 0000000..f3fb280 +index 0000000..b0b729e --- /dev/null +++ b/binutils/winduni.c @@ -0,0 +1,905 @@ +/* winduni.c -- unicode support for the windres program. -+ Copyright 1997-2013 Free Software Foundation, Inc. ++ Copyright (C) 1997-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor, Cygnus Support. + Rewritten by Kai Tietz, Onevision. + @@ -304359,13 +306788,12 @@ index 0000000..f3fb280 +} diff --git a/binutils/winduni.h b/binutils/winduni.h new file mode 100644 -index 0000000..8b3a389 +index 0000000..a4a4877 --- /dev/null +++ b/binutils/winduni.h -@@ -0,0 +1,140 @@ +@@ -0,0 +1,139 @@ +/* winduni.h -- header file for unicode support for windres program. -+ Copyright 1997, 1998, 2002, 2005, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1997-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor, Cygnus Support. + Rewritten by Kai Tietz, Onevision. + @@ -304505,13 +306933,12 @@ index 0000000..8b3a389 +#endif diff --git a/binutils/wrstabs.c b/binutils/wrstabs.c new file mode 100644 -index 0000000..bbf257e +index 0000000..a931094 --- /dev/null +++ b/binutils/wrstabs.c -@@ -0,0 +1,2272 @@ +@@ -0,0 +1,2271 @@ +/* wrstabs.c -- Output stabs debugging information -+ Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006, -+ 2007, 2009 Free Software Foundation, Inc. ++ Copyright (C) 1996-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor . + + This file is part of GNU Binutils. @@ -306782,7 +309209,7 @@ index 0000000..bbf257e + (const char *) NULL); +} diff --git a/configure.ac b/configure.ac -index 3d10b1d..b24b33d 100644 +index e92b6c0..07c3a66 100644 --- a/configure.ac +++ b/configure.ac @@ -141,7 +141,7 @@ host_libs="intl libiberty opcodes bfd readline tcl tk itcl libgui zlib libbacktr @@ -306794,12 +309221,74 @@ index 3d10b1d..b24b33d 100644 # libgcj represents the runtime libraries only used by gcj. libgcj="target-libffi \ +diff --git a/djunpack.bat b/djunpack.bat +old mode 100644 +new mode 100755 +index 8daf99d..5c6e9b2 +--- a/djunpack.bat ++++ b/djunpack.bat +@@ -17,8 +17,8 @@ Rem + Rem The following 2 lines need to be changed with each new GDB release, to + Rem be identical to the name of the top-level directory where the GDB + Rem distribution unpacks itself. +-set GDBVER=gdb-7.8 +-if "%GDBVER%"=="gdb-7.8" GoTo EnvOk ++set GDBVER=gdb-5.0 ++if "%GDBVER%"=="gdb-5.0" GoTo EnvOk + Rem If their environment space is too small, re-exec with a larger one + command.com /e:4096 /c %0 %1 + GoTo End diff --git a/elfcpp/ChangeLog b/elfcpp/ChangeLog new file mode 100644 -index 0000000..2399da6 +index 0000000..f14ed9b --- /dev/null +++ b/elfcpp/ChangeLog -@@ -0,0 +1,318 @@ +@@ -0,0 +1,363 @@ ++2014-04-22 Christian Svensson ++ ++ * elfcpp.h: Remove openrisc and or32 support. ++ ++2014-04-15 Sasa Stankovic ++ ++ * mips.h (R _MIPS16_TLS_GD, R_MIPS16_TLS_LDM, R_MIPS16_TLS_DTPREL_HI16, ++ R_MIPS16_TLS_DTPREL_LO16, R_MIPS16_TLS_GOTTPREL, ++ R_MIPS16_TLS_TPREL_HI16, R_MIPS16_TLS_TPREL_LO16, R_MICROMIPS_26_S1, ++ R_MICROMIPS_HI16, R_MICROMIPS_LO16, R_MICROMIPS_GPREL16, ++ R_MICROMIPS_LITERAL, R_MICROMIPS_GOT16, R_MICROMIPS_PC7_S1, ++ R_MICROMIPS_PC10_S1, R_MICROMIPS_PC16_S1, R_MICROMIPS_CALL16, ++ R_MICROMIPS_GOT_DISP, R_MICROMIPS_GOT_PAGE, R_MICROMIPS_GOT_OFST, ++ R_MICROMIPS_GOT_HI16, R_MICROMIPS_GOT_LO16, R_MICROMIPS_SUB, ++ R_MICROMIPS_HIGHER, R_MICROMIPS_HIGHEST, R_MICROMIPS_CALL_HI16, ++ R_MICROMIPS_CALL_LO16, R_MICROMIPS_SCN_DISP, R_MICROMIPS_JALR, ++ R_MICROMIPS_HI0_LO16, R_MICROMIPS_TLS_GD, R_MICROMIPS_TLS_LDM, ++ R_MICROMIPS_TLS_DTPREL_HI16, R_MICROMIPS_TLS_DTPREL_LO16, ++ R_MICROMIPS_TLS_GOTTPREL, R_MICROMIPS_TLS_TPREL_HI16, ++ R_MICROMIPS_TLS_TPREL_LO16, R_MICROMIPS_GPREL7_S2, ++ R_MICROMIPS_PC23_S20, R_MIPS_EH): New enums for relocations (mips16 and ++ micromips). ++ (STO_MIPS_FLAGS): New enum constant. ++ (elf_st_is_mips16): New function. ++ (elf_st_is_micromips): New function. ++ (is_micromips): New function. ++ (abi_n32): New function. ++ (abi_n64): New function. ++ (ODK_NULL, ODK_REGINFO, ODK_EXCEPTIONS, ODK_PAD, ODK_HWPATCH, ODK_FILL, ++ ODK_TAGS, ODK_HWAND, ODK_HWOR, ODK_GP_GROUP, ODK_IDENT): New enum ++ constants. ++ * elfcpp.h (SHT_MIPS_OPTIONS): New enum constant. ++ ++2014-03-05 Alan Modra ++ ++ Update copyright years. ++ ++2014-03-05 Alan Modra ++ ++ * powerpc.h (R_PPC64_REL24_NOTOC, R_PPC64_ADDR64_LOCAL): Define. ++ ++2014-02-06 Andrew Pinski ++ ++ * mips.h (E_MIPS_MACH_OCTEON3): New enum constant. ++ +2013-11-17 H.J. Lu + + * x86_64.h (R_X86_64_PC32_BND): New. @@ -307106,7 +309595,7 @@ index 0000000..2399da6 + + * Added source code to GNU binutils. + -+Copyright (C) 2008-2012 Free Software Foundation, Inc. ++Copyright (C) 2008-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -307120,7 +309609,7 @@ index 0000000..2399da6 +End: diff --git a/elfcpp/README b/elfcpp/README new file mode 100644 -index 0000000..8739b96 +index 0000000..b6f65ab --- /dev/null +++ b/elfcpp/README @@ -0,0 +1,16 @@ @@ -307135,20 +309624,20 @@ index 0000000..8739b96 +ELF file class (32 or 64 bits) and the endianness. + + -+Copyright (C) 2012 Free Software Foundation, Inc. ++Copyright (C) 2012-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright +notice and this notice are preserved. diff --git a/elfcpp/arm.h b/elfcpp/arm.h new file mode 100644 -index 0000000..ab0618a +index 0000000..8c6b6bf --- /dev/null +++ b/elfcpp/arm.h @@ -0,0 +1,352 @@ +// arm.h -- ELF definitions specific to EM_ARM -*- C++ -*- + -+// Copyright 2009, 2012 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Doug Kwan . + +// This file is part of elfcpp. @@ -307500,13 +309989,13 @@ index 0000000..ab0618a +#endif // !defined(ELFCPP_ARM_H) diff --git a/elfcpp/dwarf.h b/elfcpp/dwarf.h new file mode 100644 -index 0000000..de8b9ba +index 0000000..f7f3027 --- /dev/null +++ b/elfcpp/dwarf.h @@ -0,0 +1,240 @@ +// dwarf.h -- DWARF2 constants -*- C++ -*- + -+// Copyright 2006, 2007, 2008, 2011, 2012 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of elfcpp. @@ -307746,14 +310235,13 @@ index 0000000..de8b9ba +#endif // !defined(ELFCPP_DWARF_H) diff --git a/elfcpp/elfcpp.h b/elfcpp/elfcpp.h new file mode 100644 -index 0000000..067c775 +index 0000000..561b54a --- /dev/null +++ b/elfcpp/elfcpp.h -@@ -0,0 +1,1923 @@ +@@ -0,0 +1,1924 @@ +// elfcpp.h -- main header file for elfcpp -*- C++ -*- + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2012 -+// Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of elfcpp. @@ -307999,7 +310487,7 @@ index 0000000..067c775 + EM_MN10300 = 89, + EM_MN10200 = 90, + EM_PJ = 91, -+ EM_OPENRISC = 92, ++ EM_OR1K = 92, + EM_ARC_A5 = 93, + EM_XTENSA = 94, + EM_VIDEOCORE = 95, @@ -308041,7 +310529,7 @@ index 0000000..067c775 + // Old AVR objects used 0x1057 (EM_AVR is correct). + // Old MSP430 objects used 0x1059 (EM_MSP430 is correct). + // Old FR30 objects used 0x3330 (EM_FR30 is correct). -+ // Old OpenRISC objects used 0x3426 and 0x8472 (EM_OPENRISC is correct). ++ // Old OpenRISC objects used 0x3426 and 0x8472 (EM_OR1K is correct). + // Old D10V objects used 0x7650 (EM_D10V is correct). + // Old D30V objects used 0x7676 (EM_D30V is correct). + // Old IP2X objects used 0x8217 (EM_IP2K is correct). @@ -308153,9 +310641,11 @@ index 0000000..067c775 + // x86_64 unwind information. + SHT_X86_64_UNWIND = 0x70000001, + -+ //MIPS-specific section types. -+ // Register info section ++ // MIPS-specific section types. ++ // Section contains register usage information. + SHT_MIPS_REGINFO = 0x70000006, ++ // Section contains miscellaneous options. ++ SHT_MIPS_OPTIONS = 0x7000000d, + + // Link editor is to sort the entries in this section based on the + // address specified in the associated symbol table entry. @@ -309675,13 +312165,13 @@ index 0000000..067c775 +#endif // !defined(ELFPCP_H) diff --git a/elfcpp/elfcpp_file.h b/elfcpp/elfcpp_file.h new file mode 100644 -index 0000000..8dd7ad5 +index 0000000..bcb0275 --- /dev/null +++ b/elfcpp/elfcpp_file.h @@ -0,0 +1,688 @@ +// elfcpp_file.h -- file access for elfcpp -*- C++ -*- + -+// Copyright 2006, 2007, Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of elfcpp. @@ -310369,13 +312859,13 @@ index 0000000..8dd7ad5 +#endif // !defined(ELFCPP_FILE_H) diff --git a/elfcpp/elfcpp_internal.h b/elfcpp/elfcpp_internal.h new file mode 100644 -index 0000000..df84e7e +index 0000000..357ccc1 --- /dev/null +++ b/elfcpp/elfcpp_internal.h @@ -0,0 +1,240 @@ +// elfcpp_internal.h -- internals for elfcpp -*- C++ -*- + -+// Copyright 2006, 2007, Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of elfcpp. @@ -310615,13 +313105,13 @@ index 0000000..df84e7e +#endif // !defined(ELFCPP_INTERNAL_H) diff --git a/elfcpp/elfcpp_swap.h b/elfcpp/elfcpp_swap.h new file mode 100644 -index 0000000..833da5d +index 0000000..6a06763 --- /dev/null +++ b/elfcpp/elfcpp_swap.h @@ -0,0 +1,500 @@ +// elfcpp_swap.h -- Handle swapping for elfcpp -*- C++ -*- + -+// Copyright 2006, 2007, 2008, 2009, 2012 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of elfcpp. @@ -311121,13 +313611,13 @@ index 0000000..833da5d +#endif // !defined(ELFCPP_SWAP_H) diff --git a/elfcpp/i386.h b/elfcpp/i386.h new file mode 100644 -index 0000000..6903859 +index 0000000..6b20964 --- /dev/null +++ b/elfcpp/i386.h @@ -0,0 +1,98 @@ +// i386.h -- ELF definitions specific to EM_386 -*- C++ -*- + -+// Copyright 2006, 2007, 2010 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of elfcpp. @@ -311225,14 +313715,15 @@ index 0000000..6903859 +#endif // !defined(ELFCPP_I386_H) diff --git a/elfcpp/mips.h b/elfcpp/mips.h new file mode 100644 -index 0000000..8c2d8f4 +index 0000000..91f7270 --- /dev/null +++ b/elfcpp/mips.h -@@ -0,0 +1,267 @@ +@@ -0,0 +1,377 @@ +// mips.h -- ELF definitions specific to EM_MIPS -*- C++ -*- + -+// Copyright 2012 Free Software Foundation, Inc. -+// Written by Aleksandar Simeonov . ++// Copyright (C) 2012-2014 Free Software Foundation, Inc. ++// Written by Sasa Stankovic ++// and Aleksandar Simeonov . + +// This file is part of elfcpp. + @@ -311277,16 +313768,16 @@ index 0000000..8c2d8f4 +{ + R_MIPS_NONE = 0, + R_MIPS_16 = 1, -+ R_MIPS_32 = 2, -+ R_MIPS_REL32 = 3, ++ R_MIPS_32 = 2, // In Elf 64: alias R_MIPS_ADD ++ R_MIPS_REL32 = 3, // In Elf 64: alias R_MIPS_REL + R_MIPS_26 = 4, + R_MIPS_HI16 = 5, + R_MIPS_LO16 = 6, -+ R_MIPS_GPREL16 = 7, ++ R_MIPS_GPREL16 = 7, // In Elf 64: alias R_MIPS_GPREL + R_MIPS_LITERAL = 8, -+ R_MIPS_GOT16 = 9, ++ R_MIPS_GOT16 = 9, // In Elf 64: alias R_MIPS_GOT + R_MIPS_PC16 = 10, -+ R_MIPS_CALL16 = 11, ++ R_MIPS_CALL16 = 11, // In Elf 64: alias R_MIPS_CALL + R_MIPS_GPREL32 = 12, + R_MIPS_UNUSED1 = 13, + R_MIPS_UNUSED2 = 14, @@ -311300,48 +313791,101 @@ index 0000000..8c2d8f4 + R_MIPS_GOT_HI16 = 22, + R_MIPS_GOT_LO16 = 23, + R_MIPS_SUB = 24, -+ R_MIPS_INSERT_A = 25, // Empty relocation -+ R_MIPS_INSERT_B = 26, // Empty relocation -+ R_MIPS_DELETE = 27, // Empty relocation ++ R_MIPS_INSERT_A = 25, ++ R_MIPS_INSERT_B = 26, ++ R_MIPS_DELETE = 27, + R_MIPS_HIGHER = 28, + R_MIPS_HIGHEST = 29, + R_MIPS_CALL_HI16 = 30, + R_MIPS_CALL_LO16 = 31, + R_MIPS_SCN_DISP = 32, -+ R_MIPS_REL16 = 33, // Empty relocation -+ R_MIPS_ADD_IMMEDIATE = 34, // Empty relocation -+ R_MIPS_PJUMP = 35, // Empty relocation -+ R_MIPS_RELGOT = 36, // Empty relocation ++ R_MIPS_REL16 = 33, ++ R_MIPS_ADD_IMMEDIATE = 34, ++ R_MIPS_PJUMP = 35, ++ R_MIPS_RELGOT = 36, + R_MIPS_JALR = 37, ++ // TLS relocations. + R_MIPS_TLS_DTPMOD32 = 38, + R_MIPS_TLS_DTPREL32 = 39, -+ R_MIPS_TLS_DTPMOD64 = 40, // Empty relocation -+ R_MIPS_TLS_DTPREL64 = 41, // Empty relocation ++ R_MIPS_TLS_DTPMOD64 = 40, ++ R_MIPS_TLS_DTPREL64 = 41, + R_MIPS_TLS_GD = 42, + R_MIPS_TLS_LDM = 43, + R_MIPS_TLS_DTPREL_HI16 = 44, + R_MIPS_TLS_DTPREL_LO16 = 45, + R_MIPS_TLS_GOTTPREL = 46, + R_MIPS_TLS_TPREL32 = 47, -+ R_MIPS_TLS_TPREL64 = 48, // Empty relocation ++ R_MIPS_TLS_TPREL64 = 48, + R_MIPS_TLS_TPREL_HI16 = 49, + R_MIPS_TLS_TPREL_LO16 = 50, + R_MIPS_GLOB_DAT = 51, ++ // These relocs are used for the mips16. + R_MIPS16_26 = 100, + R_MIPS16_GPREL = 101, + R_MIPS16_GOT16 = 102, + R_MIPS16_CALL16 = 103, + R_MIPS16_HI16 = 104, + R_MIPS16_LO16 = 105, ++ R_MIPS16_TLS_GD = 106, ++ R_MIPS16_TLS_LDM = 107, ++ R_MIPS16_TLS_DTPREL_HI16 = 108, ++ R_MIPS16_TLS_DTPREL_LO16 = 109, ++ R_MIPS16_TLS_GOTTPREL = 110, ++ R_MIPS16_TLS_TPREL_HI16 = 111, ++ R_MIPS16_TLS_TPREL_LO16 = 112, ++ + R_MIPS_COPY = 126, + R_MIPS_JUMP_SLOT = 127, ++ ++ // These relocations are specific to microMIPS. ++ R_MICROMIPS_26_S1 = 133, ++ R_MICROMIPS_HI16 = 134, ++ R_MICROMIPS_LO16 = 135, ++ R_MICROMIPS_GPREL16 = 136, // In Elf 64: alias R_MICROMIPS_GPREL ++ R_MICROMIPS_LITERAL = 137, ++ R_MICROMIPS_GOT16 = 138, // In Elf 64: alias R_MICROMIPS_GOT ++ R_MICROMIPS_PC7_S1 = 139, ++ R_MICROMIPS_PC10_S1 = 140, ++ R_MICROMIPS_PC16_S1 = 141, ++ R_MICROMIPS_CALL16 = 142, // In Elf 64: alias R_MICROMIPS_CALL ++ R_MICROMIPS_GOT_DISP = 145, ++ R_MICROMIPS_GOT_PAGE = 146, ++ R_MICROMIPS_GOT_OFST = 147, ++ R_MICROMIPS_GOT_HI16 = 148, ++ R_MICROMIPS_GOT_LO16 = 149, ++ R_MICROMIPS_SUB = 150, ++ R_MICROMIPS_HIGHER = 151, ++ R_MICROMIPS_HIGHEST = 152, ++ R_MICROMIPS_CALL_HI16 = 153, ++ R_MICROMIPS_CALL_LO16 = 154, ++ R_MICROMIPS_SCN_DISP = 155, ++ R_MICROMIPS_JALR = 156, ++ R_MICROMIPS_HI0_LO16 = 157, ++ // TLS relocations. ++ R_MICROMIPS_TLS_GD = 162, ++ R_MICROMIPS_TLS_LDM = 163, ++ R_MICROMIPS_TLS_DTPREL_HI16 = 164, ++ R_MICROMIPS_TLS_DTPREL_LO16 = 165, ++ R_MICROMIPS_TLS_GOTTPREL = 166, ++ R_MICROMIPS_TLS_TPREL_HI16 = 169, ++ R_MICROMIPS_TLS_TPREL_LO16 = 170, ++ // microMIPS GP- and PC-relative relocations. ++ R_MICROMIPS_GPREL7_S2 = 172, ++ R_MICROMIPS_PC23_S2 = 173, ++ ++ // This was a GNU extension used by embedded-PIC. It was co-opted by ++ // mips-linux for exception-handling data. GCC stopped using it in ++ // May, 2004, then started using it again for compact unwind tables. + R_MIPS_PC32 = 248, ++ R_MIPS_EH = 249, ++ // This relocation is used internally by gas. + R_MIPS_GNU_REL16_S2 = 250, ++ // These are GNU extensions to enable C++ vtable garbage collection. + R_MIPS_GNU_VTINHERIT = 253, + R_MIPS_GNU_VTENTRY = 254 +}; + -+// Processor specific flags for the ELF header e_flags field. */ ++// Processor specific flags for the ELF header e_flags field. +enum +{ + // At least one .noreorder directive appears in the source. @@ -311395,6 +313939,7 @@ index 0000000..8c2d8f4 + E_MIPS_MACH_OCTEON = 0x008b0000, + E_MIPS_MACH_XLR = 0x008c0000, + E_MIPS_MACH_OCTEON2 = 0x008d0000, ++ E_MIPS_MACH_OCTEON3 = 0x008e0000, + E_MIPS_MACH_5400 = 0x00910000, + E_MIPS_MACH_5500 = 0x00980000, + E_MIPS_MACH_9000 = 0x00990000, @@ -311466,6 +314011,10 @@ index 0000000..8c2d8f4 + // Note that one of the MIPS16 bits overlaps with STO_MIPS_PIC. + STO_MIPS_ISA = 0xc0, + ++ // The mask spanning the rest of MIPS psABI flags. At most one is expected ++ // to be set except for STO_MIPS16. ++ STO_MIPS_FLAGS = ~(STO_MIPS_ISA | 0x3), ++ + // The MIPS psABI was updated in 2008 with support for PLTs and copy + // relocs. There are therefore two types of nonzero SHN_UNDEF functions: + // PLT entries and traditional MIPS lazy binding stubs. We mark the former @@ -311493,18 +314042,69 @@ index 0000000..8c2d8f4 + DTP_OFFSET = 0x8000 +}; + ++ ++bool ++elf_st_is_mips16(unsigned char st_other) ++{ return (st_other & elfcpp::STO_MIPS16) == elfcpp::STO_MIPS16; } ++ ++bool ++elf_st_is_micromips(unsigned char st_other) ++{ return (st_other & elfcpp::STO_MIPS_ISA) == elfcpp::STO_MICROMIPS; } ++ ++// Whether the ABI is N32. ++bool ++abi_n32(elfcpp::Elf_Word e_flags) ++{ return (e_flags & elfcpp::EF_MIPS_ABI2) != 0; } ++ ++// Whether the ABI is N64. ++bool ++abi_64(unsigned char ei_class) ++{ return ei_class == elfcpp::ELFCLASS64; } ++ ++// Whether the file has microMIPS code. ++bool ++is_micromips(elfcpp::Elf_Word e_flags) ++{ return (e_flags & elfcpp::EF_MIPS_ARCH_ASE_MICROMIPS) != 0; } ++ ++// Values which may appear in the kind field of an Elf_Options structure. ++enum ++{ ++ // Undefined. ++ ODK_NULL = 0, ++ // Register usage and GP value. ++ ODK_REGINFO = 1, ++ // Exception processing information. ++ ODK_EXCEPTIONS = 2, ++ // Section padding information. ++ ODK_PAD = 3, ++ // Hardware workarounds performed. ++ ODK_HWPATCH = 4, ++ // Fill value used by the linker. ++ ODK_FILL = 5, ++ // Reserved space for desktop tools. ++ ODK_TAGS = 6, ++ // Hardware workarounds, AND bits when merging. ++ ODK_HWAND = 7, ++ // Hardware workarounds, OR bits when merging. ++ ODK_HWOR = 8, ++ // GP group to use for text/data sections. ++ ODK_GP_GROUP = 9, ++ // ID information. ++ ODK_IDENT = 10 ++}; ++ +} // End namespace elfcpp. + +#endif // !defined(ELFCPP_MIPS_H) diff --git a/elfcpp/powerpc.h b/elfcpp/powerpc.h new file mode 100644 -index 0000000..98354a2 +index 0000000..2a22121 --- /dev/null +++ b/elfcpp/powerpc.h -@@ -0,0 +1,272 @@ +@@ -0,0 +1,274 @@ +// powerpc.h -- ELF definitions specific to EM_PPC and EM_PPC64 -*- C++ -*- + -+// Copyright 2008, 2010, 2012, 2013 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by David S. Miller . + +// This file is part of elfcpp. @@ -311680,6 +314280,8 @@ index 0000000..98354a2 + R_PPC_EMB_BIT_FLD = 115, + R_PPC64_DTPREL16_HIGHA = 115, + R_PPC_EMB_RELSDA = 116, ++ R_PPC64_REL24_NOTOC = 116, ++ R_PPC64_ADDR64_LOCAL = 117, + + R_PPC_VLE_REL8 = 216, + R_PPC_VLE_REL15 = 217, @@ -311776,13 +314378,13 @@ index 0000000..98354a2 +#endif // !defined(ELFCPP_POWERPC_H) diff --git a/elfcpp/sparc.h b/elfcpp/sparc.h new file mode 100644 -index 0000000..6b561be +index 0000000..b46016e --- /dev/null +++ b/elfcpp/sparc.h @@ -0,0 +1,173 @@ +// sparc.h -- ELF definitions specific to EM_SPARC -*- C++ -*- + -+// Copyright 2008, 2010 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by David S. Miller . + +// This file is part of elfcpp. @@ -311955,13 +314557,13 @@ index 0000000..6b561be +#endif // !defined(ELFCPP_SPARC_H) diff --git a/elfcpp/tilegx.h b/elfcpp/tilegx.h new file mode 100644 -index 0000000..fd80bcb +index 0000000..1ba1243 --- /dev/null +++ b/elfcpp/tilegx.h @@ -0,0 +1,171 @@ +// tilegx.h -- ELF definitions specific to EM_TILEGX -*- C++ -*- + -+// Copyright 2012 Free Software Foundation, Inc. ++// Copyright (C) 2012-2014 Free Software Foundation, Inc. +// Written by Jiong Wang (jiwang@tilera.com) + +// This file is part of elfcpp. @@ -312132,13 +314734,13 @@ index 0000000..fd80bcb +#endif // !defined(ELFCPP_TILEGX_H) diff --git a/elfcpp/x86_64.h b/elfcpp/x86_64.h new file mode 100644 -index 0000000..79fa13f +index 0000000..4b2f76d --- /dev/null +++ b/elfcpp/x86_64.h @@ -0,0 +1,104 @@ +// x86-64.h -- ELF definitions specific to EM_X86_64 -*- C++ -*- + -+// Copyright 2006, 2007, 2010 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Andrew Chatham. + +// This file is part of elfcpp. @@ -312838,7 +315440,7 @@ index 0000000..efb8c77 +--- Jason Molenda diff --git a/gas/CONTRIBUTORS b/gas/CONTRIBUTORS new file mode 100644 -index 0000000..21403d7 +index 0000000..c0384e2 --- /dev/null +++ b/gas/CONTRIBUTORS @@ -0,0 +1,116 @@ @@ -312953,7 +315555,7 @@ index 0000000..21403d7 +want to be, let us know. Some of the history has been lost; we aren't +intentionally leaving anyone out. + -+Copyright (C) 2012 Free Software Foundation, Inc. ++Copyright (C) 2012-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -313640,10 +316242,775 @@ index 0000000..94a9ed0 +. diff --git a/gas/ChangeLog b/gas/ChangeLog new file mode 100644 -index 0000000..9fcc6fd +index 0000000..fd331d7 --- /dev/null +++ b/gas/ChangeLog -@@ -0,0 +1,2123 @@ +@@ -0,0 +1,797 @@ ++2014-06-07 Alan Modra ++ ++ * config/tc-ppc.c (ppc_insert_operand): Handle PPC_OPERAND_SIGNOPT ++ on unsigned fields. Comment on PPC_OPERAND_SIGNOPT signed fields ++ in 64-bit mode. ++ ++2014-06-02 Martin Storsjo ++ ++ * doc/c-aarch64.texi: Fix the documentation on :pg_hi21:. ++ ++2014-06-05 Joel Brobecker ++ ++ * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on ++ bfd's development.sh. ++ * Makefile.in, configure: Regenerate. ++ ++2014-06-03 Nick Clifton ++ ++ * config/tc-msp430.c (OPTION_WARN_INTR_NOPS): Use y instead of z. ++ (OPTION_NO_WARN_INTR_NOPS): Use Y instead of Z. ++ * doc/c-msp430.texi: Update command line option description. ++ ++2014-05-22 Alan Modra ++ ++ * listing.c (listing_warning, listing_error): Add space after colon. ++ * messages.c (as_warn_internal, as_bad_internal): Use the same ++ string as above. ++ ++2014-05-20 Matthew Fortune ++ ++ * config/tc-mips.c (file_mips_opts_checked): New static global. ++ (s_module): New static function. ++ (file_ase): Remove. ++ (mips_pseudo_table): Add .module handler. ++ (mips_set_ase): Add opts argument and use instead of mips_opts. ++ (md_assemble): Use file_mips_check_options. ++ (md_parse_option): Update to use file_mips_opts instead of mips_opts. ++ (mips_set_architecture): Delete function. Moved to... ++ (mips_after_parse_args): Here. All logic now applies to ++ file_mips_opts first and then copies the final state to mips_opts. ++ Move error checking and defaults inference to mips_check_options and ++ file_mips_check_options. ++ (mips_check_options): New static function. Common option checking for ++ command line, .module and .set. Use .module values in error messages ++ instead of refering to command line options. ++ (file_mips_check_options): New static function. A wrapper for ++ mips_check_options with file_mips_opts. Updates BFD arch based on ++ final options. ++ (s_mipsset): Split into s_mipsset and parse_code_option. Settings ++ supported by both .set and .module are moved to parse_code_option. ++ Warnings and errors are kept in s_mipsset because when ++ parse_code_option is used with s_module the warnings are deferred ++ until code is generated. Any setting supporting 'default' value is ++ kept in s_mipsset as it is not applicable to s_module. Inferred ++ settings are also kept in s_mipsset as s_module does not infer any ++ settings. Use mips_check_options. ++ (parse_code_option): New static function derived from s_mipsset. ++ (s_module): New static function that implements .module. Allows file ++ level settings to be changed until code is generated. ++ (s_cpload, s_cpsetup, s_cplocal): Use file_mips_check_options. ++ (s_cprestore, s_cpreturn, s_cpadd, mips_address_bytes): Likewise. ++ (mips_elf_final_processing): Update file_ase to file_mips_opts.ase. ++ (md_mips_end): Use file_mips_check_options. ++ * doc/c-mips.texi: Document .module. ++ ++2014-05-20 Matthew Fortune ++ ++ * messages.c (as_warn_internal): Remove extra whitespace from ++ warning messages. ++ ++2014-05-20 Matthew Fortune ++ ++ * config/tc-mips.c (FP64_ASES): Add ASE_MSA. ++ (mips_after_parse_args): Do not select ASE_MSA without -mfp64. ++ ++2014-05-20 Mike Stump ++ ++ * messages.c (as_warn_internal): Ensure we don't interleave output ++ within a single line when make -j is used. ++ (as_bad_internal): Likewise. ++ ++2014-05-20 Richard Sandiford ++ ++ * config/obj-elf.h (obj_elf_seen_attribute): Declare. ++ * config/obj-elf.c (recorded_attribute_info): New structure. ++ (recorded_attributes): New variable. ++ (record_attribute, obj_elf_seen_attribute): New functions. ++ (obj_elf_vendor_attribute): Record which attributes have been seen. ++ ++2014-05-20 Nick Clifton ++ ++ * config/tc-msp430.c (CHECK_RELOC_MSP430): Add OP parameter. ++ Generate BFD_RELOC_MSP430_ABS_HI16 if vshift is 1. ++ (msp430_srcoperand): Store vshift value in operand. ++ ++2014-05-19 Nick Clifton ++ ++ PR gas/16858 ++ * config/tc-i386.c (md_apply_fix): Improve the detection of code ++ symbols for 32-bit PE targets. ++ ++2014-05-18 Richard Sandiford ++ ++ * config/tc-mips.c (md_obj_begin): Delete. ++ (md_obj_end): Fold into... ++ (md_mips_end): ...here. Move to end of file. ++ ++2014-05-17 Nick Clifton ++ ++ PR gas/16946 ++ * config/tc-v850.c (handle_ctoff): Generate an error if called ++ when using the RH850 ABI. ++ ++2014-05-16 Kaushik Phata ++ ++ * config/tc-rl78.c (enum options): Add OPTION_32BIT_DOUBLES ++ and OPTION_64BIT_DOUBLES. ++ (md_longopts): Add -m32bit-doubles and -m64bit-doubles. ++ (md_parse_option): Parse -m32bit-doubles and -m64bit-doubles. ++ (md_show_usage): Show all of the RL78 options. ++ (rl78_float_cons): New static functions. ++ (md_pseudo_table): Update handler for "double". ++ * doc/c-rl78.texi: Document new options. ++ * doc/as.texinfo: Likewise. ++ ++2014-05-13 Matthew Fortune ++ ++ * config/tc-mips.c (mips_set_options): Rename gp32 to gp throughout. ++ (HAVE_32BIT_GPRS, HAVE_64BIT_GPRS): Remove. Re-implement via GPR_SIZE. ++ (HAVE_32BIT_FPRS, HAVE_64BIT_FPRS): Remove. Re-implement via FPR_SIZE. ++ (GPR_SIZE, FPR_SIZE): New macros. Use throughout. ++ ++2014-05-08 Matthew Fortune ++ ++ * config/tc-mips.c (md_parse_option): Update missed file_mips_isa ++ references. ++ ++2014-05-08 Matthew Fortune ++ ++ * config/tc-mips.c (mips_set_options): Rename fp32 field to fp. ++ Update fp32 == 0 to fp == 64 and fp32 == 1 to fp != 64 throughout. ++ (file_mips_gp32, file_mips_fp32, file_mips_soft_float, ++ file_mips_single_float, file_mips_isa, file_mips_arch): Merge into ++ one struct... ++ (file_mips_opts): Here. New static global. Update throughout. ++ (mips_opts): Update defaults for gp32 and fp. ++ ++2014-05-08 Matthew Fortune ++ ++ * config/tc-mips.c (streq): Define. ++ (mips_convert_symbolic_attribute): New function. ++ * config/tc-mips.h (CONVERT_SYMBOLIC_ATTRIBUTE): Define. ++ (mips_convert_symbolic_attribute): New prototype. ++ ++2014-05-02 Max Filippov ++ ++ * config/tc-xtensa.c (md_apply_fix): mark BFD_RELOC_XTENSA_DIFF* ++ fixups as signed. ++ ++2014-05-07 Andrew Bennett ++ ++ * tc-mips.c (ISA_SUPPORTS_MIPS16E): Add mips32r3, mips32r5, mips64r3 ++ and mips64r5. ++ (ISA_HAS_64BIT_FPRS): Likewise. ++ (ISA_HAS_ROR): Likewise. ++ (ISA_HAS_ODD_SINGLE_FPR): Likewise. ++ (ISA_HAS_MXHC1): Likewise. ++ (hilo_interlocks): Likewise. ++ (md_longopts): Likewise. ++ (ISA_HAS_64BIT_REGS): Add mips64r3 and mips64r5. ++ (ISA_HAS_DROR): Likewise. ++ (options): Add OPTION_MIPS32R3, OPTION_MIPS32R5, OPTION_MIPS64R3, and ++ OPTION_MIPS64R5. ++ (mips_isa_rev): Add support for mips32r3, mips32r5, mips64r3 and ++ mips64r5. ++ (md_parse_option): Likewise. ++ (s_mipsset): Likewise. ++ (mips_cpu_info_table): Add entries for mips32r3, mips32r5, mips64r3 ++ and mips64r5. Also change p5600 entry to be mips32r5. ++ * configure.in: Add support for mips32r3, mips32r5, mips64r3 and ++ mips64r5. ++ * configure: Regenerate. ++ * doc/c-mips.texi: Document the -mips32r3, -mips32r5, -mips64r3 and ++ -mips64r5 command line options. ++ * doc/as.texinfo: Likewise. ++ ++2014-04-28 Nick Clifton ++ ++ PR gas/16858 ++ * config/tc-i386.c (md_apply_fix): Do not adjust value of ++ pc-relative fixes against weak symbols. ++ ++2014-04-26 Alan Modra ++ ++ * po/POTFILES.in: Regenerate. ++ ++2014-04-24 Nick Clifton ++ ++ * config/tc-arm.c (s_ltorg): Only create a mapping symbol for ELF ++ based targets. ++ ++2014-04-23 Will Newton ++ ++ * config/tc-arm.c (s_ltorg): Call make_mapping_symbol ++ directly instead of mapping_state. ++ ++2014-04-23 Andrew Bennett ++ ++ * config/tc-mips.c (options): Add OPTION_XPA and OPTION_NO_XPA. ++ (md_longopts): Add xpa and no-xpa command line options. ++ (mips_ases): Add MIPS XPA ASE. ++ (mips_cpu_info_table): Update p5600 entry to allow the XPA ASE. ++ * doc/as.texinfo: Document the MIPS XPA command line options. ++ * doc/c-mips.texi: Document the MIPS XPA command line options, ++ and assembler directives. ++ ++2014-04-22 Sandra Loosemore ++ ++ * config/tc-nios2.c (nios2_consume_arg): Add case for 'E' to ++ unbreak self-test mode. ++ ++2014-04-22 Max Filippov ++ ++ * config/tc-xtensa.c (xtensa_handle_align): record alignment for the ++ first section frag. ++ ++2014-04-22 Christian Svensson ++ ++ * Makefile.am: Remove openrisc and or32 support. Add support for or1k. ++ * configure.in: Likewise. ++ * configure.tgt: Likewise. ++ * doc/as.texinfo: Likewise. ++ * config/obj-coff.h: Likewise. ++ * config/tc-or1k.c: New file. ++ * config/tc-or1k.h: New file. ++ * config/tc-openrisc.c: Delete. ++ * config/tc-openrisc.h: Delete. ++ * config/tc-or32.c: Delete. ++ * config/tc-or32.h: Delete. ++ * Makefile.in: Regenerate. ++ * configure: Regenerate. ++ ++2014-04-16 Alan Modra ++ ++ * config/tc-tilegx.h (TC_CONS_FIX_NEW): Add RELOC arg. ++ * config/tc-tilepro.h (TC_CONS_FIX_NEW): Likewise. ++ ++2014-04-10 Senthil Kumar Selvaraj ++ ++ * config/tc-avr.c: Add new flag mlink-relax. ++ (md_show_usage): Add flag and help text. ++ (md_parse_option): Record whether link relax is turned on. ++ (relaxable_section): New. ++ (avr_validate_fix_sub): New. ++ (avr_force_relocation): New. ++ (md_apply_fix): Generate DIFF reloc. ++ (avr_allow_local_subtract): New. ++ ++ * config/tc-avr.h (TC_LINKRELAX_FIXUP): Define to 0. ++ (TC_FORCE_RELOCATION): Define. ++ (TC_FORCE_RELOCATION_SUB_SAME): Define. ++ (TC_VALIDATE_FIX_SUB): Define. ++ (avr_force_relocation): Declare. ++ (avr_validate_fix_sub): Declare. ++ (md_allow_local_subtract): Define. ++ (avr_allow_local_subtract): Declare. ++ ++2014-04-10 Andrew Bennett ++ ++ * config/tc-mips.c (mips_cpu_info_table): Add P5600 ++ configuation. ++ * doc/c-mips.texi: Document p5600. ++ ++2014-04-09 Nick Clifton ++ ++ * config/tc-rl78.h (TC_CONS_FIX_NEW): Add RELOC parameter. ++ * config/tc-z80.h (TC_CONS_FIX_NEW): Discard RELOC parameter. ++ * config/tc-aarch64.h (TC_CONS_FIX_NEW): Discard RELOC parameter. ++ * read.c (emit_expr_fix): Mark the r parameter as potentially ++ unused. ++ ++2014-04-09 Alan Modra ++ ++ * config/tc-ppc.c (warn_476, last_insn, last_seg, last_subseg): ++ New static vars. ++ (md_longopts, md_parse_option, md_show_usage): Add --ppc476-workaround. ++ (ppc_elf_cons_fix_check): New function. ++ (md_assemble): Set last_insn, last_seg, last_subseg. ++ (ppc_byte, md_apply_fix): Handle warn_476. ++ * config/tc-ppc.h (TC_CONS_FIX_CHECK): Define. ++ (ppc_elf_cons_fix_check): Declare. ++ * read.c (cons_worker): Invoke TC_CONS_FIX_CHECK. ++ ++2014-04-09 Alan Modra ++ ++ * gas/config/tc-alpha.h (TC_CONS_FIX_NEW): Add RELOC parameter. ++ * gas/config/tc-arc.c (arc_cons_fix_new): Add reloc parameter. ++ * gas/config/tc-arc.h (arc_cons_fix_new): Update prototype. ++ (TC_CONS_FIX_NEW): Add RELOC parameter. ++ * gas/config/tc-arm.c (cons_fix_new_arm): Similarly ++ * gas/config/tc-arm.h (cons_fix_new_arm, TC_CONS_FIX_NEW): Similarly. ++ * gas/config/tc-cr16.c (cr16_cons_fix_new): Similarly. ++ * gas/config/tc-cr16.h (cr16_cons_fix_new, TC_CONS_FIX_NEW): Similarly. ++ * gas/config/tc-crx.h (TC_CONS_FIX_NEW): Similarly. ++ * gas/config/tc-m32c.c (m32c_cons_fix_new): Similarly. ++ * gas/config/tc-m32c.h (m32c_cons_fix_new, TC_CONS_FIX_NEW): Similarly. ++ * gas/config/tc-mn10300.c (mn10300_cons_fix_new): Similarly. ++ * gas/config/tc-mn10300.h (mn10300_cons_fix_new, TC_CONS_FIX_NEW): ++ Similarly. ++ * gas/config/tc-ns32k.c (cons_fix_new_ns32k): Similarly. ++ * gas/config/tc-ns32k.h (cons_fix_new_ns32k): Similarly. ++ * gas/config/tc-pj.c (pj_cons_fix_new_pj): Similarly. ++ * gas/config/tc-pj.h (pj_cons_fix_new_pj, TC_CONS_FIX_NEW): Similarly. ++ * gas/config/tc-rx.c (rx_cons_fix_new): Similarly. ++ * gas/config/tc-rx.h (rx_cons_fix_new, TC_CONS_FIX_NEW): Similarly. ++ * gas/config/tc-sh.c (sh_cons_fix_new): Similarly. ++ * gas/config/tc-sh.h (sh_cons_fix_new, TC_CONS_FIX_NEW): Similarly. ++ * gas/config/tc-tic54x.c (tic54x_cons_fix_new): Similarly. ++ * gas/config/tc-tic54x.h (tic54x_cons_fix_new, TC_CONS_FIX_NEW): ++ Similarly. ++ * gas/config/tc-tic6x.c (tic6x_cons_fix_new): Similarly. ++ * gas/config/tc-tic6x.h (tic6x_cons_fix_new, TC_CONS_FIX_NEW): ++ Similarly. ++ * gas/config/tc-arc.c (arc_parse_cons_expression): Return reloc. ++ * gas/config/tc-arc.h (arc_parse_cons_expression): Update proto. ++ * gas/config/tc-avr.c (exp_mod_data): Make global. ++ (pexp_mod_data): Delete. ++ (avr_parse_cons_expression): Return exp_mod_data pointer. ++ (avr_cons_fix_new): Add exp_mod_data_t pointer param. ++ (exp_mod_data_t): Move typedef.. ++ * gas/config/tc-avr.h: ..to here. ++ (exp_mod_data): Declare. ++ (TC_PARSE_CONS_RETURN_TYPE, TC_PARSE_CONS_RETURN_NONE): Define. ++ (avr_parse_cons_expression, avr_cons_fix_new): Update prototype. ++ (TC_CONS_FIX_NEW): Update. ++ * gas/config/tc-hppa.c (hppa_field_selector): Delete static var. ++ (cons_fix_new_hppa): Add hppa_field_selector param. ++ (fix_new_hppa): Adjust. ++ (parse_cons_expression_hppa): Return field selector. ++ * gas/config/tc-hppa.h (parse_cons_expression_hppa): Update proto. ++ (cons_fix_new_hppa): Likewise. ++ (TC_PARSE_CONS_RETURN_TYPE, TC_PARSE_CONS_RETURN_NONE): Define. ++ * gas/config/tc-i386.c (got_reloc): Delete static var. ++ (x86_cons_fix_new): Add reloc param. ++ (x86_cons): Return got reloc. ++ * gas/config/tc-i386.h (x86_cons, x86_cons_fix_new): Update proto. ++ (TC_CONS_FIX_NEW): Add RELOC param. ++ * gas/config/tc-ia64.c (ia64_cons_fix_new): Add reloc param. Adjust ++ calls. ++ * gas/config/tc-ia64.h (ia64_cons_fix_new): Update prototype. ++ (TC_CONS_FIX_NEW): Add reloc param. ++ * gas/config/tc-microblaze.c (parse_cons_expression_microblaze): ++ Return reloc. ++ (cons_fix_new_microblaze): Add reloc param. ++ * gas/config/tc-microblaze.h: Formatting. ++ (parse_cons_expression_microblaze): Update proto. ++ (cons_fix_new_microblaze): Likewise. ++ * gas/config/tc-nios2.c (nios2_tls_ldo_reloc): Delete static var. ++ (nios2_cons): Return ldo reloc. ++ (nios2_cons_fix_new): Delete. ++ * gas/config/tc-nios2.h (nios2_cons): Update prototype. ++ (nios2_cons_fix_new, TC_CONS_FIX_NEW): Delete. ++ * gas/config/tc-ppc.c (md_pseudo_table): Remove quad, long, word, ++ short. Make llong use cons. ++ (ppc_elf_suffix): Return BFD_RELOC_NONE rather than BFD_RELOC_UNUSED. ++ (ppc_elf_cons): Delete. ++ (ppc_elf_parse_cons): New function. ++ (ppc_elf_validate_fix): Don't check for BFD_RELOC_UNUSED. ++ (md_assemble): Use BFD_RELOC_NONE rather than BFD_RELOC_UNUSED. ++ * gas/config/tc-ppc.h (TC_PARSE_CONS_EXPRESSION): Define ++ (ppc_elf_parse_cons): Declare. ++ * gas/config/tc-sparc.c (sparc_cons_special_reloc): Delete static var. ++ (sparc_cons): Return reloc specifier. ++ (cons_fix_new_sparc): Add reloc specifier param. ++ (sparc_cfi_emit_pcrel_expr): Use emit_expr_with_reloc. ++ * gas/config/tc-sparc.h (TC_PARSE_CONS_RETURN_TYPE): Define. ++ (TC_PARSE_CONS_RETURN_NONE): Define. ++ (sparc_cons, cons_fix_new_sparc): Update prototype. ++ * gas/config/tc-v850.c (hold_cons_reloc): Delete static var. ++ (v850_reloc_prefix): Use BFD_RELOC_NONE rather than BFD_RELOC_UNUSED. ++ (md_assemble): Likewise. ++ (parse_cons_expression_v850): Return reloc. ++ (cons_fix_new_v850): Add reloc parameter. ++ * gas/config/tc-v850.h (parse_cons_expression_v850): Update proto. ++ (cons_fix_new_v850): Likewise. ++ * gas/config/tc-vax.c (vax_cons_special_reloc): Delete static var. ++ (vax_cons): Return reloc. ++ (vax_cons_fix_new): Add reloc parameter. ++ * gas/config/tc-vax.h (vax_cons, vax_cons_fix_new): Update proto. ++ * gas/config/tc-xstormy16.c (xstormy16_cons_fix_new): Add reloc param. ++ * gas/config/tc-xstormy16.h (xstormy16_cons_fix_new): Update proto. ++ * gas/dwarf2dbg.c (TC_PARSE_CONS_RETURN_NONE): Provide default. ++ (emit_fixed_inc_line_addr): Adjust exmit_expr_fix calls. ++ * gas/read.c (TC_PARSE_CONS_EXPRESSION): Return value. ++ (do_parse_cons_expression): Adjust. ++ (cons_worker): Pass return value from TC_PARSE_CONS_EXPRESSION ++ to emit_expr_with_reloc. ++ (emit_expr_with_reloc): New function handling reloc, mostly ++ extracted from.. ++ (emit_expr): ..here. ++ (emit_expr_fix): Add reloc param. Adjust TC_CONS_FIX_NEW invocation. ++ Handle reloc. ++ (parse_mri_cons): Convert to ISO. ++ * gas/read.h (TC_PARSE_CONS_RETURN_TYPE): Define. ++ (TC_PARSE_CONS_RETURN_NONE): Define. ++ (emit_expr_with_reloc): Declare. ++ (emit_expr_fix): Update prototype. ++ * gas/write.c (write_object_file): Update TC_CONS_FIX_NEW invocation. ++ ++2014-04-03 Ilya Tocar ++ ++ * config/tc-i386.c (cpu_arch): Add .se1. ++ * doc/c-i386.texi: Document .se1/se1. ++ ++2014-04-02 DJ Delorie ++ ++ * config/tc-rl78.c (md_apply_fix): Add overflow warnings for ++ pc-relative branches. ++ ++2014-04-02 Nick Clifton ++ ++ PR gas/16765 ++ * config/tc-arm.c (create_unwind_entry): Report an error if an ++ attempt to recreate an unwind directive is encountered. ++ ++2014-03-27 Nick Clifton ++ ++ * config/tc-score.c (s3_parse_pce_inst): Add "%s" parameter to ++ sprintf in order to avoid a compile time warning. ++ ++2014-03-26 Nick Clifton ++ ++ * config/tc-rl78.c (rl78_op): Issue an error message if a 16-bit ++ relocation is used on an 8-bit operand or vice versa. ++ (tc_gen_reloc): Use the RL78_16U relocation for RL78_CODE. ++ (md_apply_fix): Add support for RL78_HI8, RL78_HI16 and RL78_LO16. ++ ++2014-03-25 Nick Clifton ++ ++ * config/obj-coff-seh.c (obj_coff_seh_code): New function - ++ switches the current segment back to the code segment recorded ++ when seh_proc was last invoked. ++ * config/obj-coff-seh.h (SEH_CMDS): Add seh_code. ++ ++2014-03-25 Alan Modra ++ ++ * config/tc-ppc.c (ppc_is_toc_sym): Revert 2014-03-05. ++ (md_assemble): Likewise. Warn. ++ ++2014-03-21 David Weatherford ++ Max Filippov ++ ++ * config/tc-xtensa.c (xtensa_check_frag_count) ++ xtensa_create_trampoline_frag, ++ xtensa_maybe_create_trampoline_frag, init_trampoline_frag, ++ find_trampoline_seg, search_trampolines, get_best_trampoline, ++ check_and_update_trampolines, add_jump_to_trampoline, ++ dump_trampolines): New functions. ++ (md_parse_option): Add cases for --[no-]trampolines options. ++ (md_assemble, finish_vinsn, xtensa_end): Add call to ++ xtensa_check_frag_count. ++ (xg_assemble_vliw_tokens): Add call to ++ xtensa_maybe_create_trampoline_frag. ++ (xtensa_relax_frag): Relax fragments with RELAX_TRAMPOLINE state. ++ (relax_frag_immed): Relax jump instructions that cannot reach its ++ target. ++ * config/tc-xtensa.h (xtensa_relax_statesE::RELAX_TRAMPOLINE): New ++ relax state. ++ * doc/as.texinfo: Document --[no-]trampolines command-line options. ++ * doc/c-xtensa.texi: Document trampolines relaxation and command ++ line options. ++ * frags.c (get_frag_count, clear_frag_count): New function. ++ (frag_alloc): Increment totalfrags counter. ++ * frags.h (get_frag_count, clear_frag_count): New function. ++ ++2014-03-20 DJ Delorie ++ ++ * config/rl78-defs.h (RL78_RELAX_NONE, RL78_RELAX_BRANCH): Add. ++ * config/rl78-parse.y (BC, BNC, BZ, BNZ, BH, BHZ, bt_bf): Call ++ rl78_relax(). ++ * config/tc-rl78.h (md_relax_frag): Define. ++ (rl78_relax_frag): Declare. ++ * config/tc-rl78.c (rl78_relax): Add. ++ (md_assemble): Set up the variable frags also when relaxing. ++ (op_type_T): New. ++ (rl78_opcode_type): New. ++ (rl78_frag_fix_value): New. ++ (md_estimate_size_before_relax): New-ish. ++ (rl78_relax_frag): New. ++ (md_convert_frag): New-ish. ++ ++2014-03-20 Richard Sandiford ++ ++ * config/tc-mips.h (DIFF_EXPR_OK, CFI_DIFF_EXPR_OK): Define. ++ * config/tc-mips.c (md_pcrel_from): Remove error message. ++ (md_apply_fix): Convert PC-relative BFD_RELOC_32s to ++ BFD_RELOC_32_PCREL. Report a specific error message for unhandled ++ PC-relative expressions. Handle BFD_RELOC_8. ++ ++2014-03-19 Jose E. Marchesi ++ ++ * config/tc-sparc.c (hpriv_reg_table): Added entries for ++ %hstick_offset and %hstick_enable. ++ * doc/c-sparc.texi (Sparc-Regs): Document the %hstick_offset and ++ %hstick_enable hyperprivileged registers. ++ ++2014-03-19 Daniel Gutson ++ Nick Clifton ++ ++ * config/tc-arm.c (codecomposer_syntax): New flag that states whether the ++ CCS syntax compatibility mode is on or off. ++ (asmfunc_states): New enum to represent the asmfunc directive state. ++ (asmfunc_state): New variable holding the asmfunc directive state. ++ (comment_chars): Rename to arm_comment_chars. ++ (line_separator_chars): Rename to arm_line_separator_chars. ++ (s_ccs_ref): New function that handles the .ref directive. ++ (asmfunc_debug): New function. ++ (s_ccs_asmfunc): New function that handles the .asmfunc directive. ++ (s_ccs_endasmfunc): New function that handles the .endasmfunc directive. ++ (s_ccs_def): New function that handles the .def directive. ++ (tc_start_label_without_colon): New function. ++ (md_pseudo_table): Added new CCS directives. ++ (arm_ccs_mode): New function that handles the -mccs command line option. ++ (arm_long_opts): Added new -mccs command line option. ++ * config/tc-arm.h (LABELS_WITHOUT_COLONS): New macro. ++ (TC_START_LABEL_WITHOUT_COLON): New macro. ++ (tc_start_label_without_colon): Added extern function declaration. ++ (tc_comment_chars): Define. ++ (tc_line_separator_chars): Define. ++ * app.c (do_scrub_begin): Use tc_line_separator_chars, if defined. ++ * read.c (read_begin): Likewise. ++ * doc/as.texinfo: Add documentation for the -mccs command line ++ option. ++ * doc/c-arm.texi: Likewise. ++ * doc/internals.texi: Document tc_line_separator_chars. ++ * NEWS: Mention the new feature. ++ ++2014-03-18 Jiong Wang ++ ++ * config/tc-aarch64.c (aarch64_opts): Add new option ++ "mno-verbose-error". ++ (verbose_error_p): Initialize to 1. ++ * doc/c-aarch64.texi (AArch64 Options): Document -mverbose-error ++ and -mno-verbose-error. ++ ++2014-03-17 Nick Clifton ++ ++ PR gas/16694 ++ * config/tc-arm.c (tc_arm_regname_to_dw2regnum): Parse VFP ++ registers as well. ++ ++2014-03-13 Richard Earnshaw ++ Jiong Wang ++ ++ * doc/c-aarch64.texi: Clean up some formatting issues. ++ (AArch64 Options): Document -mcpu and -march. ++ (AArch64 Extensions): New node. ++ ++2014-03-13 Tristan Gingold ++ ++ * config/tc-i386.c (use_big_obj): Declare. ++ (OPTION_MBIG_OBJ): Define. ++ (md_longopts): Add -mbig-obj option. ++ (md_parse_option): Handle it. ++ (md_show_usage): Display help for this option. ++ (i386_target_format): Use bigobj for x86-64 if -mbig-obj. ++ * doc/c-i386.texi: Document the option. ++ ++2014-03-12 Nick Clifton ++ ++ PR gas/16688 ++ * config/tc-aarch64.c (literal_expression): New structure. ++ (literal_pool): Replace exp array with literal_expression array. ++ (add_to_lit_pool): When adding a bignum cache the big value. ++ (s_ltorg): When emitting a bignum initialise the global bignum ++ array from the cached value. ++ ++2014-03-12 Alan Modra ++ ++ * Makefile.in: Regenerate. ++ * config.in: Regenerate. ++ * doc/Makefile.in: Regenerate. ++ ++2014-03-06 Pitchumani Sivanupandi ++ Vishnu KS ++ Senthil Kumar Selvaraj ++ Soundararajan ++ ++ * gas/tc-avr.c: Add new devices ++ avr25: ata5272, attiny828 ++ avr35: ata5505, attiny1634 ++ avr4: atmega8a, ata6285, ata6286, atmega48pa ++ avr5: at90pwm161, ata5790, ata5795, atmega164pa, atmega165pa, ++ atmega168pa, atmega32a, atmega64rfr2, atmega644rfr2, atmega64a, ++ atmega16hva2 ++ avr51: atmega128a, atmega1284 ++ avrxmega2: atxmega16a4u, atxmega16c4, atxmega32a4u, atxmega32c4, ++ atxmega32e5, atxmega16e5, atxmega8e5 ++ avrxmega4: atxmega64a3u, atxmega64a4u, atxmega64b1, atxmega64b3, ++ atxmega64c3, atxmega64d4 ++ avrxmega6: atxmega128a3u, atxmega128b3, atxmega128c3, ++ atxmega128d4, atxmega192a3u, atxmega192c3, atxmega256a3u, ++ atxmega256c3, atxmega384c3, atxmega384d3 ++ avrxmega7: atxmega128a4u ++ * doc/c-avr.texi: Ditto. ++ ++2014-03-05 Alan Modra ++ ++ Update copyright years. ++ ++2014-03-05 Alan Modra ++ ++ * config/tc-ppc.c (ppc_elf_suffix): Support @localentry. ++ (md_apply_fix): Support R_PPC64_ADDR64_LOCAL. ++ ++2014-03-05 Alan Modra ++ ++ * config/tc-ppc.c (md_assemble): Move code adjusting reloc types ++ later. Merge absolute and relative branch reloc selection. ++ Generate 16-bit relocs for most 16-bit insn fields given a ++ non-constant expression. ++ ++2014-03-05 Alan Modra ++ ++ * config/tc-ppc.c (ppc_is_toc_sym): Remove OBJ_ELF support. ++ (md_assemble): Don't call ppc_is_toc_sym for ELF. ++ ++2014-03-04 Heiher ++ ++ * config/tc-mips.c (mips_cpu_info_table): Use ISA_MIPS64R2 for ++ Loongson-3A. ++ ++2014-03-03 Nick Clifton ++ ++ * config/msp430/msp430.c: Replace known mcu array with known ++ msp430 ISA mcu name array. ++ Accept any name for -mmcu option. ++ Add -mz option to warn about missing NOP following an interrupt ++ status change. ++ (check_for_nop): New. ++ (msp430_operands): Emit a warning, if requested, when an interrupt ++ changing instruction is not followed by a NOP. ++ * doc/c-msp430.c: Document -mz option. ++ ++2014-03-03 Alan Modra ++ ++ * config/bfin-lex-wrapper.c: Correct copyright date. ++ * config/obj-fdpicelf.c: Likewise. ++ * config/obj-fdpicelf.h: Likewise. ++ * config/tc-frv.c: Correct copyright punctuation. ++ * config/tc-ip2k.c: Likewise. ++ * config/tc-iq2000.c: Likewise. ++ * config/tc-mep.c: Likewise. ++ * config/tc-tic4x.c: Likewise. ++ * config/tc-tic4x.h: Likewise. ++ ++2014-03-01 Senthil Kumar Selvaraj ++ ++ * config/tc-avr.c: Remove atxmega16x1. ++ ++2014-02-28 Alan Modra ++ ++ * dwarf2dbg.c (out_debug_line): Correct .debug_line header_length ++ field for 64-bit dwarf. ++ ++2014-02-21 Ilya Tocar ++ ++ * config/tc-i386.c (cpu_arch): Add .prefetchwt1. ++ * doc/c-i386.texi: Document .prefetchwt1/prefetchwt1. ++ ++2014-02-12 Ilya Tocar ++ ++ * config/tc-i386.c (cpu_arch): Add .clflushopt, .xsavec, .xsaves. ++ * doc/c-i386.texi: Document .xsavec/xsavec/.xsaves/xsaves/ ++ clflushopt/.clfushopt. ++ ++2014-02-10 Alan Modra ++ ++ * po/POTFILES.in: Regenerate. ++ * po/gas.pot: Regenerate. ++ ++2014-02-03 Sandra Loosemore ++ ++ * config/tc-nios2.c (md_apply_fix): Test for new relocs. ++ (nios2_special_reloc): Add %call_lo, %call_hiadj, %got_lo, ++ %got_hiadj relocation operators. Sort table and add comment ++ to explain ordering. ++ (nios2_fix_adjustable): Test for new relocs. ++ * doc/c-nios2.texi (Nios II Relocations): Document new relocation ++ operators. ++ ++2014-01-30 Sandra Loosemore ++ ++ * config/tc-nios2.c (md_apply_fix): Handle BFD_RELOC_NIOS2_CALL26_NOAT. ++ (nios2_assemble_args_m): Likewise. ++ (md_assemble): Likewise. ++ ++2014-01-24 DJ Delorie ++ ++ * config/tc-msp430.c (msp430_section): Always flag data sections, ++ regardless of -md. ++ (msp430_frob_section): New. Make sure all sections are noticed if ++ they have content. ++ (msp430_lcomm): New. Flag bss if .lcomm is seen. ++ (msp430_comm): New. Likewise. ++ (md_pseudo_table): Add them. ++ * config/tc-msp430.h (msp430_frob_section): Declare. ++ (tc_frob_section): Define. ++ ++2014-01-23 Nick Clifton ++ ++ * config/tc-msp430.c (show_mcu_list): Delete. ++ (md_parse_option): Accept any MCU name. Accept several more ++ variants for the -mcpu option. ++ (md_show_usage): Do not call show_mcu_list. ++ ++2014-01-22 DJ Delorie ++ ++ * config/tc-msp430.c (msp430_refsym): New: ".refsym " ++ * doc/c-msp430.texi (MSP430 Directives): Document it. ++ ++2014-01-22 Michael Zolotukhin ++ ++ * config/tc-i386.c (check_VecOperands): Remove regzmm from AVX2 ++ gather assert. ++ ++2014-01-22 Michael Zolotukhin ++ ++ PR gas/16489 ++ * config/tc-i386.c (check_VecOperands): Add check for invalid ++ register set in AVX512 gathers. ++ ++2014-01-22 Alan Modra ++ ++ * config/tc-tic4x.c (md_shortopts): s/CONST/const/. ++ ++2014-01-21 DJ Delorie ++ ++ * config/tc-rl78.c (require_end_of_expr): New. ++ (md_operand): Call it. ++ (rl78_cons_fix_new): Mark LO16, HI16, ahd HI8 internal relocations ++ as not overflowing. ++ ++2014-01-17 Will Newton ++ ++ * config/tc-arm.c (do_vfp_nsyn_cvt_fpv8): Set OP to 1 ++ for the s32.f64 flavours of VCVT. ++ ++2014-01-14 Nick Clifton ++ ++ PR gas/16434 ++ * config/tc-z80.c (wrong_match): Provide format string to ++ as_warn. ++ (parse_exp_not_indexed): Delete unused variable dummy. ++ (emit_byte): Delete unused variable fixp. ++ ++2014-01-08 H.J. Lu ++ ++ * config/tc-i386.c (regbnd): Removed. ++ (vec_disp8): Likewise. ++ ++2014-01-08 H.J. Lu ++ ++ * as.c (parse_args): Update copyright year to 2014. ++ +2014-01-07 Tom Tromey + + * config/tc-tic30.c (debug): Avoid old VA_* compatibility @@ -313662,2100 +317029,9 @@ index 0000000..9fcc6fd + + * config/tc-aarch64.c (aarch64_cpus): Add entry for "xgene-1" + -+2013-12-20 Tristan Gingold -+ -+ * doc/c-arm.texi (ARM Directives): Remove duplicate .pad entry. -+ -+2013-12-18 Yufeng Zhang -+ -+ * config/tc-aarch64.c (md_assemble): Defer the feature checking until -+ do_encode () succeeds. -+ -+2013-12-18 Nick Clifton -+ -+ * config/tc-rx.c (rx_include): Rename 'eof' to 'last_char' in -+ order to avoid conflict with same named variable in MinGW system -+ header file. -+ -+2013-12-13 Nick Clifton -+ -+ * config/tc-msp430.c (mcu_types): Add some more 430X mcu names. -+ (OPTION_INTR_NOPS): Define. -+ (gen_interrupt_nops): Default to FALSE. -+ (md_parse_opton): Add support for OPTION_INTR_NOPS. -+ (md_longopts): Add -mn. -+ (md_show_usage): Add -mn. -+ (msp430_operands): Generate NOPs for all MCUs not just 430Xv2. -+ * doc/c-msp430.c: Document -mn. -+ -+2013-12-13 Kuan-Lin Chen -+ Wei-Cheng Wang -+ Hsiang-Kai Wang -+ Hui-Wen Ni -+ -+ * Makefile.am (TARGET_CPU_CFILES): Add config/tc-nds32.c. -+ (TARGET_CPU_HFILES): Add config/tc-nds32.h. -+ * Makefile.in: Regenerate. -+ * configure.in (nds32): Add nds32 target extension config support. -+ * configure.tgt : Add case for nds32-*-elf* and nds32-*-linux*. -+ * configure: Regenerate. -+ * config/tc-nds32.c: New file for nds32. -+ * config/tc-nds32.h: New file for nds32. -+ * doc/Makefile.am (CPU_DOCS): Add c-nds32.texi. -+ * doc/Makefile.in: Regenerate. -+ * doc/as.texinfo: Add nds32 options. -+ * doc/all.texi: Set NDS32. -+ * doc/c-nds32.texi: New file dor nds32 document. -+ * NEWS: Announce Andes nds32 support. -+ -+2013-12-10 Roland McGrath -+ -+ * Makefile.am (install-exec-bindir): Prefix libtool invocation -+ with $(INSTALL_PROGRAM_ENV). -+ (install-exec-tooldir): Likewise. -+ * Makefile.in: Regenerate. -+ -+2013-12-07 Mike Frysinger -+ -+ * config/bfin-aux.h: Remove +x file mode. -+ * config/tc-epiphany.c: Likewise. -+ * config/tc-epiphany.h: Likewise. -+ -+2013-12-03 Tristan Gingold -+ -+ * config/tc-i386-intel.c (i386_intel_simplify): Avoid arithmetic -+ overflow on pointers. -+ -+2013-11-19 Yufeng Zhang -+ -+ Revert -+ -+ 2013-11-19 Nick Clifton -+ -+ * config/tc-aarch64.c (parse_sys_reg): Do not issue error messages -+ for deprecated system registers when parsing pstate fields. -+ -+2013-11-19 Nick Clifton -+ -+ * config/tc-aarch64.c (parse_sys_reg): Do not issue error messages -+ for deprecated system registers when parsing pstate fields. -+ -+2013-11-19 Catherine Moore -+ -+ * config/tc-mips.c (mips_fix_pmc_rm7000): Declare. -+ (options): Add OPTION_FIX_PMC_RM7000 and OPTION_NO_FIX_PMC_RM7000. -+ (md_longopts): Add mfix-pmc-rm7000 and mno-fix-pmc-rm7000. -+ (INSN_DMULT): Define. -+ (INSN_DMULTU): Define. -+ (insns_between): Detect PMC RM7000 errata. -+ (md_parse_option): Supprt OPTION_FIX_PMC_RM7000 and -+ OPTION_NO_FIX_PMC_RM7000. -+ * doc/as.texinfo: Document new options. -+ * doc/c-mips.texi: Likewise. -+ -+2013-11-19 Alexey Makhalov -+ -+ PR gas/16109 -+ * app.c (do_scrub_chars): Only insert a newline character if -+ end-of-file has been reached. -+ -+2013-11-18 H.J. Lu -+ -+ * config/tc-i386.c (lex_got): Add a dummy "int bnd_prefix" -+ argument. -+ -+2013-11-18 Renlin Li -+ -+ * config/tc-arm.c (arm_archs): New armv7ve architecture option. -+ (arm_cpus): Replace ARM_ARCH_V7A_IDIV_MP_SEC_VIRT with -+ ARM_ARCH_V7VE for cortex-a7, cortex-a12 and cortex-a15. -+ (cpu_arch_ver): Likewise. -+ * doc/c-arm.texi: Document armv7ve. -+ -+2013-11-18 Zhenqiang Chen -+ -+ * config/tc-aarch64.c (parse_sys_reg): Support -+ S2____. -+ -+2013-11-18 Yufeng Zhang -+ -+ Revert -+ -+ 2013-11-15 Yufeng Zhang -+ -+ * config/tc-aarch64.c (set_other_error): New function. -+ (parse_sys_reg): Add new parameter 'sys_reg' and if non-NULL set -+ the variable to which it points with 'o'. -+ (parse_operands): Update; check for write to read-only system -+ registers or read from write-only ones. -+ -+2013-11-17 H.J. Lu -+ -+ * config/tc-i386.c (reloc): Add an argument, bnd_prefix, to -+ indicate if instruction has the BND prefix. Return -+ BFD_RELOC_X86_64_PC32_BND instead of BFD_RELOC_32_PCREL if -+ bnd_prefix isn't zero. -+ (output_branch): Pass BFD_RELOC_X86_64_PC32_BND to frag_var -+ if needed. -+ (output_jump): Update reloc call. -+ (output_interseg_jump): Likewise. -+ (output_disp): Likewise. -+ (output_imm): Likewise. -+ (x86_cons_fix_new): Likewise. -+ (lex_got): Add an argument, bnd_prefix, to indicate if -+ instruction has the BND prefix. Use BFD_RELOC_X86_64_PLT32_BND -+ if needed. -+ (x86_cons): Update lex_got call. -+ (i386_immediate): Likewise. -+ (i386_displacement): Likewise. -+ (md_apply_fix): Handle BFD_RELOC_X86_64_PC32_BND and -+ BFD_RELOC_X86_64_PLT32_BND. -+ (tc_gen_reloc): Likewise. -+ * config/tc-i386-intel.c (i386_operator): Update lex_got call. -+ -+2013-11-15 Yufeng Zhang -+ -+ * config/tc-aarch64.c (set_other_error): New function. -+ (parse_sys_reg): Add new parameter 'sys_reg' and if non-NULL set -+ the variable to which it points with 'o'. -+ (parse_operands): Update; check for write to read-only system -+ registers or read from write-only ones. -+ -+2013-11-15 Michael Zolotukhin -+ -+ * config/tc-i386.c (check_VecOperands): Reorder checks. -+ -+2013-11-11 Catherine Moore -+ -+ * config/mips/tc-mips.c (convert_reg_type): Use -+ INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY. -+ (reg_needs_delay): Likewise. -+ (insns_between): Likewise. -+ -+2013-11-08 Jan-Benedict Glaw -+ -+ * config/tc-aarch64.c (parse_sys_reg): Update to use aarch64_sys_reg; -+ call aarch64_sys_reg_deprecated_p and warn about the deprecated -+ system registers. -+ -+2013-11-05 Yufeng Zhang -+ -+ * config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_COND1. -+ -+2013-11-05 Will Newton -+ -+ PR gas/16103 -+ * config/tc-aarch64.c (parse_operands): Avoid trying to -+ parse a vector register as an immediate. -+ -+2013-11-04 Jan Beulich -+ -+ * config/tc-i386.c (check_long_reg): Correct comment indentation. -+ (check_qword_reg): Correct comment and its indentation. -+ (check_word_reg): Extend comment and correct its indentation. Also -+ check for 64-bit register. -+ -+2013-10-30 Ulrich Weigand -+ -+ * config/tc-ppc.c (md_pseudo_table): Add .localentry. -+ (ppc_elf_localentry): New function. -+ (ppc_force_relocation): Force relocs on all branches to localenty -+ symbols. -+ (ppc_fix_adjustable): Don't reduce such symbols to section+offset. -+ -+2013-10-30 Alan Modra -+ -+ * config/tc-ppc.c: Include elf/ppc64.h. -+ (ppc_abiversion): New variable. -+ (md_pseudo_table): Add .abiversion. -+ (ppc_elf_abiversion, ppc_elf_end): New functions. -+ * config/tc-ppc.h (md_end): Define. -+ -+2013-10-30 Alan Modra -+ -+ * config/tc-ppc.c (SEX16): Don't mask. -+ (REPORT_OVERFLOW_HI): Define as zero. -+ (ppc_elf_suffix): Support @high, @higha, @dtprel@high, @dtprel@higha, -+ @tprel@high, and @tprel@higha modifiers. -+ (md_assemble): Ignore X_unsigned when applying 16-bit insn fields. -+ Add (disabled) code to check @h and @ha reloc overflow for powerpc64. -+ Handle new relocs. -+ (md_apply_fix): Similarly. -+ -+2013-10-18 Chao-ying Fu -+ -+ * config/tc-mips.c (fpr_read_mask): Test MSA registers. -+ (fpr_write_mask): Test MSA registers. -+ (can_swap_branch_p): Check fpr write followed by fpr read. -+ -+2013-10-18 Nick Clifton -+ -+ * config/tc-tic6x.c (tic6x_parse_operand): Revert previous delta. -+ -+2013-10-14 Richard Sandiford -+ Chao-ying Fu -+ -+ * config/tc-mips.c (options): Add OPTION_MSA and OPTION_NO_MSA. -+ (md_longopts): Add mmsa and mno-msa. -+ (mips_ases): Add msa. -+ (RTYPE_MASK): Update. -+ (RTYPE_MSA): New define. -+ (OT_REG_ELEMENT): Replace with... -+ (OT_INTEGER_INDEX, OT_REG_INDEX): ...these new operand types. -+ (mips_operand_token): Replace reg_element with index. -+ (mips_parse_argument_token): Treat vector indices as separate tokens. -+ Handle register indices. -+ (md_begin): Add MSA register names. -+ (operand_reg_mask): Handle cases for OP_IMM_INDEX and OP_REG_INDEX. -+ (convert_reg_type): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL. -+ (match_mdmx_imm_reg_operand): Update accordingly. -+ (match_imm_index_operand): New function. -+ (match_reg_index_operand): New function. -+ (match_operand): Handle cases for OP_IMM_INDEX and OP_REG_INDEX. -+ (md_convert_frag): Convert bz.b/h/w/d, bnz.b/h/w/d, bz.v bnz.v. -+ (md_show_usage): Print -mmsa and -mno-msa. -+ * doc/as.texinfo: Document -mmsa and -mno-msa. -+ * doc/c-mips.texi: Document -mmsa and -mno-msa. -+ Document .set msa and .set nomsa. -+ -+2013-10-14 Nick Clifton -+ -+ * read.c (add_include_dir): Use xrealloc. -+ * config/tc-score.c (do_macro_bcmp): Initialise inst_main. -+ * config/tc-tic6x.c (tic6x_parse_operand): Initialise second_reg. -+ -+2013-10-13 Sandra Loosemore -+ -+ * config/tc-nios2.c (nios2_consume_arg): Make the "ba" warning -+ also test/refer to "sstatus". Reformat the warning message. -+ -+2013-10-10 Sean Keys -+ -+ * tc-xgate.c (xgate_find_match): Refactor opcode matching. -+ -+2013-10-10 Jan Beulich -+ -+ * tc-i386-intel.c (i386_intel_simplify_register): Suppress base/index -+ swapping for bndmk, bndldx, and bndstx. -+ -+2013-10-09 Nick Clifton -+ -+ PR gas/16025 -+ * config/tc-epiphany.c (md_convert_frag): Add missing break -+ statement. -+ -+ PR gas/16026 -+ * config/tc-mn10200.c (md_convert_frag): Add missing break -+ statement. -+ -+2013-10-08 Jan Beulich -+ -+ * tc-i386.c (check_word_reg): Remove misplaced "else". -+ (check_long_reg): Restore symmetry with check_word_reg. -+ -+2013-10-08 Jan Beulich -+ -+ * gas/config/tc-arm.c (do_t_push_pop): Honor inst.size_req. Simplify -+ LR/PC check. -+ -+2013-10-08 Nick Clifton -+ -+ * config/tc-msp430.c (msp430_operands): Accept ".a" as an alias -+ for "a". Issue error messages for unrecognised or corrrupt -+ size extensions. -+ -+2013-10-04 Kyrylo Tkachov -+ -+ * config/tc-arm.c (do_t_mvn_tst): Use narrow form for tst when -+ possible. -+ -+2013-09-30 Saravanan Ekanathan -+ -+ * config/tc-i386.c (cpu_arch): Add CPU_BDVER4_FLAGS. -+ * doc/c-i386.texi: Add -march=bdver4 option. -+ -+2013-09-20 Alan Modra -+ -+ * configure: Regenerate. -+ -+2013-09-18 Tristan Gingold -+ -+ * NEWS: Add marker for 2.24. -+ -+2013-09-18 Nick Clifton -+ -+ * config/tc-msp430.c (OPTION_MOVE_DATA): Define. -+ (move_data): New variable. -+ (md_parse_option): Parse -md. -+ (msp430_section): New function. Catch references to the .bss or -+ .data sections and generate a special symbol for use by the libcrt -+ library. -+ (md_pseudo_table): Intercept .section directives. -+ (md_longopt): Add -md -+ (md_show_usage): Likewise. -+ (msp430_operands): Generate a warning message if a NOP is inserted -+ into the instruction stream. -+ * doc/c-msp430.texi (node MSP430 Options): Document -md option. -+ -+2013-09-17 Doug Gilmore -+ -+ * config/tc-mips.c (mips_elf_final_processing): Set -+ EF_MIPS_FP64 for -mgp32 -mfp64, removing old FIXME. -+ -+2013-09-16 Will Newton -+ -+ * config/tc-arm.c (do_neon_ld_st_interleave): Add constraint -+ disallowing element size 64 with interleave other than 1. -+ -+2013-09-12 Chao-ying Fu -+ -+ * config/tc-mips.c (match_insn): Set error when $31 is used for -+ bltzal* and bgezal*. -+ -+2013-09-04 Tristan Gingold -+ -+ * config/tc-ppc.c (md_apply_fix): Handle defined after use toc -+ symbols. -+ -+2013-09-04 Roland McGrath -+ -+ PR gas/15914 -+ * config/tc-arm.c (T16_32_TAB): Add _udf. -+ (do_t_udf): New function. -+ (insns): Add "udf". -+ -+2013-08-23 Sandeep Kumar Singh -+ -+ * config/rx-parse.y: Rearrange the components of a bison grammar to issue -+ assembler errors at correct position. -+ -+2013-08-23 Yuri Chornoivan -+ -+ PR binutils/15834 -+ * config/tc-ia64.c: Fix typos. -+ * config/tc-sparc.c: Likewise. -+ * config/tc-z80.c: Likewise. -+ * doc/c-i386.texi: Likewise. -+ * doc/c-m32r.texi: Likewise. -+ -+2013-08-23 Will Newton -+ -+ * config/tc-arm.c: (do_neon_ldx_stx): Add extra constraints -+ for pre-indexed addressing modes. -+ -+2013-08-21 Alan Modra -+ -+ * symbols.c (fb_label_instance_inc, fb_label_instance): Properly -+ range check label number for use with fb_low_counter array. -+ -+2013-08-19 Richard Sandiford -+ -+ * config/tc-mips.c (mips_check_isa_supports_ase, reg_lookup) -+ (mips_parse_argument_token, validate_micromips_insn, md_begin) -+ (check_regno, match_float_constant, check_completed_insn, append_insn) -+ (match_insn, match_mips16_insn, match_insns, macro_start) -+ (macro_build_ldst_constoffset, load_register, macro, mips_ip) -+ (mips16_ip, mips_set_option_string, md_parse_option) -+ (mips_after_parse_args, mips_after_parse_args, md_pcrel_from) -+ (md_apply_fix, s_align, s_option, s_mipsset, s_tls_rel_directive) -+ (s_gpword, s_gpdword, s_ehword, s_nan, tc_gen_reloc, md_convert_frag) -+ (s_mips_end, s_mips_ent, s_mips_frame, s_mips_mask, mips_parse_cpu): -+ Start error messages with a lower-case letter. Do not end error -+ messages with a period. Wrap long messages to 80 character-lines. -+ Use "cannot" instead of "can't" and "can not". -+ -+2013-08-19 Richard Sandiford -+ -+ * config/tc-mips.c (imm_expr): Expand comment. -+ (set_at, macro, mips16_macro): Expect imm_expr to be O_constant -+ when populated. -+ -+2013-08-19 Richard Sandiford -+ -+ * config/tc-mips.c (imm2_expr): Delete. -+ (md_assemble, match_insn, imm2_expr.X_op, mips_ip): Update accordingly. -+ -+2013-08-19 Richard Sandiford -+ -+ * config/tc-mips.c (report_bad_range, report_bad_field): Delete. -+ (macro): Remove M_DEXT and M_DINS handling. -+ -+2013-08-19 Richard Sandiford -+ -+ * config/tc-mips.c (mips_arg_info): Replace allow_nonconst and -+ lax_max with lax_match. -+ (match_int_operand): Update accordingly. Don't report an error -+ for !lax_match-only cases. -+ (match_insn): Replace more_alts with lax_match and use it to -+ initialize the mips_arg_info field. Add a complete_p parameter. -+ Handle implicit VU0 suffixes here. -+ (match_invalid_for_isa, match_insns, match_mips16_insns): New -+ functions. -+ (mips_ip, mips16_ip): Use them. -+ -+2013-08-19 Richard Sandiford -+ -+ * config/tc-mips.c (match_expression): Report uses of registers here. -+ Add a "must be an immediate expression" error. Handle elided offsets -+ here rather than... -+ (match_int_operand): ...here. -+ -+2013-08-19 Richard Sandiford -+ -+ * config/tc-mips.c (mips_arg_info): Remove soft_match. -+ (match_out_of_range, match_not_constant): New functions. -+ (match_const_int): Remove fallback parameter and check for soft_match. -+ Use match_not_constant. -+ (match_mapped_int_operand, match_addiusp_operand) -+ (match_perf_reg_operand, match_save_restore_list_operand) -+ (match_mdmx_imm_reg_operand): Update accordingly. Use -+ match_out_of_range and set_insn_error* instead of as_bad. -+ (match_int_operand): Likewise. Use match_not_constant in the -+ !allows_nonconst case. -+ (match_float_constant): Report invalid float constants. -+ (match_insn, match_mips16_insn): Remove soft_match code. Rely on -+ match_float_constant to check for invalid constants. Fail the -+ match if match_const_int or match_float_constant return false. -+ (mips_ip): Update accordingly. -+ (mips16_ip): Likewise. Undo null termination of instruction name -+ once lookup is complete. -+ -+2013-08-19 Richard Sandiford -+ -+ * config/tc-mips.c (mips_insn_error_format): New enum. -+ (mips_insn_error): New struct. -+ (insn_error): Change to a mips_insn_error. -+ (clear_insn_error, set_insn_error_format, set_insn_error) -+ (set_insn_error_i, set_insn_error_ss, report_insn_error): New -+ functions. -+ (mips_parse_argument_token, md_assemble, match_insn) -+ (match_mips16_insn): Use them instead of manipulating insn_error -+ directly. -+ (mips_ip, mips16_ip): Likewise. Simplify control flow. -+ -+2013-08-19 Richard Sandiford -+ -+ * config/tc-mips.c (normalize_constant_expr): Move further up file. -+ (normalize_address_expr): Likewise. -+ (match_insn, match_mips16_insn): New functions, split out from... -+ (mips_ip, mips16_ip): ...here. -+ -+2013-08-19 Richard Sandiford -+ -+ * config/tc-mips.c (operand_reg_mask, match_operand): Handle -+ OP_OPTIONAL_REG. -+ (mips_ip, mips16_ip): Use mips_optional_operand_p to check -+ for optional operands. -+ -+2013-08-16 Alan Modra -+ -+ * config/tc-ppc.c (ppc_elf_cons): Allow @l and other reloc -+ modifiers generally. -+ -+2013-08-16 Alan Modra -+ -+ * config/tc-ppc.c (ppc_elf_lcomm): Use subsection 1. -+ -+2013-08-14 David Edelsohn -+ -+ * config/tc-ppc.c (ppc_comm): Accept optional fourth .lcomm -+ argument as alignment. -+ -+2013-08-09 Nick Clifton -+ -+ * config/tc-rl78.c (elf_flags): New variable. -+ (enum options): Add OPTION_G10. -+ (md_longopts): Add mg10. -+ (md_parse_option): Parse -mg10. -+ (rl78_elf_final_processing): New function. -+ * config/tc-rl78.c (tc_final_processing): Define. -+ * doc/c-rl78.texi: Document -mg10 option. -+ -+2013-08-06 Jürgen Urban -+ -+ * config/tc-mips.c (match_vu0_suffix_operand): Allow single-channel -+ suffixes to be elided too. -+ (mips_lookup_insn): Don't reject INSN2_VU0_CHANNEL_SUFFIX here. -+ (mips_ip): Assume .xyzw if no VU0 suffix is specified. Allow +N -+ to be omitted too. -+ -+2013-08-05 John Tytgat -+ -+ * po/POTFILES.in: Regenerate. -+ -+2013-08-05 Eric Botcazou -+ Konrad Eisele -+ -+ * config/tc-sparc.c (sparc_arch_types): Add leon. -+ (sparc_arch): Move sparc4 around and add leon. -+ (sparc_target_format): Document -Aleon. -+ * doc/c-sparc.texi: Likewise. -+ -+2013-08-05 Richard Sandiford -+ -+ * config/tc-mips.c (mips_lookup_insn): Make length and opend signed. -+ -+2013-08-04 Jürgen Urban -+ Richard Sandiford -+ -+ * config/tc-mips.c (MAX_OPERANDS): Bump to 6. -+ (RWARN): Bump to 0x8000000. -+ (RTYPE_VI, RTYPE_VF, RTYPE_R5900_I, RTYPE_R5900_Q, RTYPE_R5900_R) -+ (RTYPE_R5900_ACC): New register types. -+ (RTYPE_MASK): Include them. -+ (R5900_I_NAMES, R5900_Q_NAMES, R5900_R_NAMES, R5900_ACC_NAMES): New -+ macros. -+ (reg_names): Include them. -+ (mips_parse_register_1): New function, split out from... -+ (mips_parse_register): ...here. Add a channels_ptr parameter. -+ Look for VU0 channel suffixes when nonnull. -+ (reg_lookup): Update the call to mips_parse_register. -+ (mips_parse_vu0_channels): New function. -+ (OT_CHANNELS, OT_DOUBLE_CHAR): New mips_operand_token_types. -+ (mips_operand_token): Add a "channels" field to the union. -+ Extend the comment above "ch" to OT_DOUBLE_CHAR. -+ (mips_parse_base_start): Match -- and ++. Handle channel suffixes. -+ (mips_parse_argument_token): Handle channel suffixes here too. -+ (validate_mips_insn): Handle INSN2_VU0_CHANNEL_SUFFIX. -+ Ignore OP_VU0_MATCH_SUFFIX when calculating the used bits. -+ Handle '#' formats. -+ (md_begin): Register $vfN and $vfI registers. -+ (operand_reg_mask): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. -+ (convert_reg_type): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I, -+ OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC. -+ (match_vu0_suffix_operand): New function. -+ (match_operand): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. -+ (macro): Use "+7" rather than "E" for LDQ2 and STQ2. -+ (mips_lookup_insn): New function. -+ (mips_ip): Use it. Allow "+K" operands to be elided at the end -+ of an instruction. Handle '#' sequences. -+ -+2013-08-03 Richard Sandiford -+ -+ * config/tc-mips.c (macro, mips16_macro): Create an array of operand -+ values and use it instead of sreg, treg, xreg, etc. -+ -+2013-08-03 Richard Sandiford -+ -+ * config/tc-mips.c (match_int_operand): Use mips_int_operand_min -+ and mips_int_operand_max. -+ (mips16_immed_operand, mips16_immed_operands, MIPS16_NUM_IMMED): -+ Delete. -+ (mips16_immed_operand, mips16_immed_in_range_p): New functions. -+ (mips16_immed, mips16_extended_frag): Use them. Use mips_int_operand -+ instead of mips16_immed_operand. -+ -+2013-08-03 Richard Sandiford -+ -+ * config/tc-mips.c (mips16_macro): Don't use move_register. -+ (mips16_ip): Allow macros to use 'p'. -+ -+2013-08-01 Richard Sandiford -+ -+ * config/tc-mips.c (MAX_OPERANDS): New macro. -+ (mips_operand_array): New structure. -+ (mips_operands, mips16_operands, micromips_operands): New arrays. -+ (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map) -+ (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map) -+ (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map) -+ (micromips_to_32_reg_q_map): Delete. -+ (insn_operands, insn_opno, insn_extract_operand): New functions. -+ (validate_mips_insn): Take a mips_operand_array as argument and -+ use it to build up a list of operands. Extend to handle INSN_MACRO -+ and MIPS16. -+ (validate_mips16_insn): New function. -+ (validate_micromips_insn): Take a mips_operand_array as argument. -+ Handle INSN_MACRO. -+ (md_begin): Initialize mips_operands, mips16_operands and -+ micromips_operands. Call validate_mips_insn and -+ validate_micromips_insn for macro instructions too. -+ Call validate_mips16_insn for MIPS16 instructions. -+ (insn_read_mask, insn_write_mask, operand_reg_mask, insn_reg_mask): -+ New functions. -+ (gpr_read_mask, gpr_write_mask, fpr_read_mask, fpr_write_mask): Use -+ them. Handle INSN_UDI. -+ (get_append_method): Use gpr_read_mask. -+ -+2013-08-01 Richard Sandiford -+ -+ * config/tc-mips.c (compact_branch_p, uncond_branch_p): Use the same -+ flags for MIPS16 and non-MIPS16 instructions. -+ (gpr_mod_mask): Move the INSN2_MOD_SP case outside the micromips block. -+ (gpr_read_mask): Use INSN2_READ_GPR_31 for MIPS16 instructions too. -+ (gpr_write_mask): Remove MIPS16_INSN_WRITE_SP handling. -+ (can_swap_branch_p, get_append_method): Use the same flags for MIPS16 -+ and non-MIPS16 instructions. Fix formatting. -+ -+2013-08-01 Richard Sandiford -+ -+ * config/tc-mips.c (reg_needs_delay): Move later in file. -+ Use gpr_write_mask. -+ (insns_between): Use gpr_read_mask instead of EXTRACT_OPERAND. -+ -+2013-07-26 Sergey Guriev -+ Alexander Ivchenko -+ Maxim Kuznetsov -+ Sergey Lega -+ Anna Tikhonova -+ Ilya Tocar -+ Andrey Turetskiy -+ Ilya Verbin -+ Kirill Yukhin -+ Michael Zolotukhin -+ -+ * config/tc-i386-intel.c (O_zmmword_ptr): New. -+ (i386_types): Add zmmword. -+ (i386_intel_simplify_register): Allow regzmm. -+ (i386_intel_simplify): Handle zmmwords. -+ (i386_intel_operand): Handle RC/SAE, vector operations and -+ zmmwords. -+ * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. -+ (struct RC_Operation): New. -+ (struct Mask_Operation): New. -+ (struct Broadcast_Operation): New. -+ (vex_prefix): Size of bytes increased to 4 to support EVEX -+ encoding. -+ (enum i386_error): Add new error codes: unsupported_broadcast, -+ broadcast_not_on_src_operand, broadcast_needed, -+ unsupported_masking, mask_not_on_destination, no_default_mask, -+ unsupported_rc_sae, rc_sae_operand_not_last_imm, -+ invalid_register_operand, try_vector_disp8. -+ (struct _i386_insn): Add new fields vrex, need_vrex, mask, -+ rounding, broadcast, memshift. -+ (struct RC_name): New. -+ (RC_NamesTable): New. -+ (evexlig): New. -+ (evexwig): New. -+ (extra_symbol_chars): Add '{'. -+ (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. -+ (i386_operand_type): Add regzmm, regmask and vec_disp8. -+ (match_mem_size): Handle zmmwords. -+ (operand_type_match): Handle zmm-registers. -+ (mode_from_disp_size): Handle vec_disp8. -+ (fits_in_vec_disp8): New. -+ (md_begin): Handle {} properly. -+ (type_names): Add "rZMM", "Mask reg" and "Vector d8". -+ (build_vex_prefix): Handle vrex. -+ (build_evex_prefix): New. -+ (process_immext): Adjust to properly handle EVEX. -+ (md_assemble): Add EVEX encoding support. -+ (swap_2_operands): Correctly handle operands with masking, -+ broadcasting or RC/SAE. -+ (check_VecOperands): Support EVEX features. -+ (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. -+ (match_template): Support regzmm and handle new error codes. -+ (process_suffix): Handle zmmwords and zmm-registers. -+ (check_byte_reg): Extend to zmm-registers. -+ (process_operands): Extend to zmm-registers. -+ (build_modrm_byte): Handle EVEX. -+ (output_insn): Adjust to properly handle EVEX case. -+ (disp_size): Handle vec_disp8. -+ (output_disp): Support compressed disp8*N evex feature. -+ (output_imm): Handle RC/SAE immediates properly. -+ (check_VecOperations): New. -+ (i386_immediate): Handle EVEX features. -+ (i386_index_check): Handle zmmwords and zmm-registers. -+ (RC_SAE_immediate): New. -+ (i386_att_operand): Handle EVEX features. -+ (parse_real_register): Add a check for ZMM/Mask registers. -+ (OPTION_MEVEXLIG): New. -+ (OPTION_MEVEXWIG): New. -+ (md_longopts): Add mevexlig and mevexwig. -+ (md_parse_option): Handle mevexlig and mevexwig options. -+ (md_show_usage): Add description for mevexlig and mevexwig. -+ * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, -+ avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. -+ -+2013-07-25 Michael Zolotukhin -+ -+ * config/tc-i386.c (cpu_arch): Add .sha. -+ * doc/c-i386.texi: Document sha/.sha. -+ -+2013-07-24 Anna Tikhonova -+ Kirill Yukhin -+ Michael Zolotukhin -+ -+ * config/tc-i386.c (BND_PREFIX): New. -+ (struct _i386_insn): Add new field bnd_prefix. -+ (add_bnd_prefix): New. -+ (cpu_arch): Add MPX. -+ (i386_operand_type): Add regbnd. -+ (md_assemble): Handle BND prefixes. -+ (parse_insn): Likewise. -+ (output_branch): Likewise. -+ (output_jump): Likewise. -+ (build_modrm_byte): Handle regbnd. -+ (OPTION_MADD_BND_PREFIX): New. -+ (md_longopts): Add entry for 'madd-bnd-prefix'. -+ (md_parse_option): Handle madd-bnd-prefix option. -+ (md_show_usage): Add description for madd-bnd-prefix -+ option. -+ * doc/c-i386.texi: Document mpx/.mpx and -madd-bnd-prefix. -+ -+2013-07-24 Tristan Gingold -+ -+ * config/tc-ppc.c (md_apply_fix): Adjust BFD_RELOC_PPC_B16 on -+ xcoff targets. -+ -+2013-07-24 Andreas Krebbel -+ -+ * config/tc-s390.c (s390_machine): Don't force the .machine -+ argument to lower case. -+ -+2013-07-22 Kyrylo Tkachov -+ -+ * config/tc-arm.c (s_arm_arch_extension): Improve error message -+ for invalid extension. -+ -+2013-07-19 Yufeng Zhang -+ -+ * config/tc-aarch64.c (enum aarch64_abi_type): New enumeration tag. -+ (AARCH64_ABI_LP64, AARCH64_ABI_ILP32): New enumerators. -+ (aarch64_abi): New variable. -+ (ilp32_p): Change to be a macro. -+ (aarch64_opts): Remove the support for option -milp32 and -mlp64. -+ (struct aarch64_option_abi_value_table): New struct. -+ (aarch64_abis): New table. -+ (aarch64_parse_abi): New function. -+ (aarch64_long_opts): Add entry for -mabi=. -+ * doc/as.texinfo (Target AArch64 options): Document -mabi. -+ * doc/c-aarch64.texi: Likewise. -+ -+2013-07-18 Jim Thomas -+ -+ * config/tc-i386-intel.c (i386_intel_operand): Fixed signed vs -+ unsigned comparison. -+ -+2013-07-18 Sandeep Kumar Singh -+ -+ * config/rx-defs.h: Add macros for RX100, RX200, RX600, and -+ RX610. -+ * config/rx-parse.y: (rx_check_float_support): Add function to -+ check floating point operation support for target RX100 and -+ RX200. -+ * config/tc-rx.c: Add CPU options RX100, RX200, RX600, and RX610. -+ * doc/c-rx.texi: Add -mcpu option to recognize macros for RX100, -+ RX200, RX600, and RX610 -+ -+2013-07-18 Senthil Kumar Selvaraj -+ -+ * config/tc-avr.c (md_show_usage): Add avrxmega2 to help text -+ -+2013-07-18 Vishnu K.S -+ -+ * config/tc-avr.c: Make ata6289's ISA to AVR_ISA_AVR4. -+ * doc/c-avr.texi: Likewise. -+ -+2013-07-15 Richard Sandiford -+ -+ * config/tc-mips.c (match_save_restore_list_operand): Avoid -Wformat -+ error with older GCCs. -+ (mips16_macro_build): Dereference args. -+ -+2013-07-14 Richard Sandiford -+ -+ * config/tc-mips.c (mips_prefer_vec_regno, mips_parse_register): -+ New functions, split out from... -+ (reg_lookup): ...here. Remove itbl support. -+ (reglist_lookup): Delete. -+ (mips_operand_token_type): New enum. -+ (mips_operand_token): New structure. -+ (mips_operand_tokens): New variable. -+ (mips_add_token, mips_parse_base_start, mips_parse_argument_token) -+ (mips_parse_arguments): New functions. -+ (md_begin): Initialize mips_operand_tokens. -+ (mips_arg_info): Add a token field. Remove optional_reg field. -+ (match_char, match_expression): New functions. -+ (match_const_int): Use match_expression. Remove "s" argument -+ and return a boolean result. Remove O_register handling. -+ (match_regno, match_reg, match_reg_range): New functions. -+ (match_int_operand, match_mapped_int_operand, match_msb_operand) -+ (match_reg_operand, match_reg_pair_operand, match_perf_reg_operand) -+ (match_addiusp_operand, match_clo_clz_dest_operand) -+ (match_lwm_swm_list_operand, match_entry_exit_operand) -+ (match_save_restore_list_operand, match_mdmx_imm_reg_operand) -+ (match_tied_reg_operand): Remove "s" argument and return a boolean -+ result. Match tokens rather than text. Update calls to -+ match_const_int. Rely on match_regno to call check_regno. -+ (match_pcrel_operand, match_pc_operand): Replace "s" argument with -+ "arg" argument. Return a boolean result. -+ (parse_float_constant): Replace with... -+ (match_float_constant): ...this new function. -+ (match_operand): Remove "s" argument and return a boolean result. -+ Update calls to subfunctions. -+ (mips_ip, mips16_ip): Call mips_parse_arguments. Use match routines -+ rather than string-parsing routines. Update handling of optional -+ registers for token scheme. -+ -+2013-07-14 Richard Sandiford -+ -+ * config/tc-mips.c (parse_float_constant): Split out from... -+ (mips_ip): ...here. -+ -+2013-07-14 Richard Sandiford -+ -+ * config/tc-mips.c (INSERT_BITS, INSERT_OPERAND, MIPS16_INSERT_OPERAND): -+ Delete. -+ -+2013-07-14 Richard Sandiford -+ -+ * config/tc-mips.c (mips32_to_16_reg_map): Delete. -+ (match_entry_exit_operand): New function. -+ (match_save_restore_list_operand): Likewise. -+ (match_operand): Use them. -+ (check_absolute_expr): Delete. -+ (mips16_ip): Rewrite main parsing loop to use mips_operands. -+ -+2013-07-14 Richard Sandiford -+ -+ * config/tc-mips.c: Enable functions commented out in previous patch. -+ (SKIP_SPACE_TABS): Move further up file. -+ (mips32_to_micromips_reg_b_map, mips32_to_micromips_reg_c_map) -+ (mips32_to_micromips_reg_d_map, mips32_to_micromips_reg_e_map) -+ (ips32_to_micromips_reg_f_map, mips32_to_micromips_reg_g_map) -+ (mips32_to_micromips_reg_l_map, mips32_to_micromips_reg_m_map) -+ (mips32_to_micromips_reg_q_map, mips32_to_micromips_reg_n_map) -+ (micromips_imm_b_map, micromips_imm_c_map): Delete. -+ (mips_lookup_reg_pair): Delete. -+ (macro): Use report_bad_range and report_bad_field. -+ (mips_immed, expr_const_in_range): Delete. -+ (mips_ip): Rewrite main parsing loop to use new functions. -+ -+2013-07-14 Richard Sandiford -+ -+ * config/tc-mips.c (mips_oddfpreg_ok): Move further up file. -+ Change return type to bfd_boolean. -+ (report_bad_range, report_bad_field): New functions. -+ (mips_arg_info): New structure. -+ (match_const_int, convert_reg_type, check_regno, match_int_operand) -+ (match_mapped_int_operand, match_msb_operand, match_reg_operand) -+ (match_reg_pair_operand, match_pcrel_operand, match_perf_reg_operand) -+ (match_addiusp_operand, match_clo_clz_dest_operand) -+ (match_lwm_swm_list_operand, match_mdmx_imm_reg_operand) -+ (match_pc_operand, match_tied_reg_operand, match_operand) -+ (check_completed_insn): New functions, commented out for now. -+ -+2013-07-14 Richard Sandiford -+ -+ * config/tc-mips.c (insn_insert_operand): New function. -+ (macro_build, mips16_macro_build): Put null character check -+ in the for loop and convert continues to breaks. Use operand -+ structures to handle constant operands. -+ -+2013-07-14 Richard Sandiford -+ -+ * config/tc-mips.c (validate_mips_insn): Move further up file. -+ Add insn_bits and decode_operand arguments. Use the mips_operand -+ fields to work out which bits an operand occupies. Detect double -+ definitions. -+ (validate_micromips_insn): Move further up file. Call into -+ validate_mips_insn. -+ -+2013-07-14 Richard Sandiford -+ -+ * config/tc-mips.c (mips16_macro_build): Remove 'Y' case. -+ -+2013-07-14 Richard Sandiford -+ -+ * config/tc-mips.c (macro_build): Take an int for "C", "k", "\\" -+ and "~". -+ (macro): Update accordingly. -+ -+2013-07-14 Richard Sandiford -+ -+ * config/tc-mips.c (imm_expr, imm2_expr, offset_expr): Tweak commentary. -+ (imm_reloc): Delete. -+ (md_assemble): Remove imm_reloc handling. -+ (mips_ip): Update commentary. Use offset_expr and offset_reloc -+ rather than imm_expr and imm_reloc for 'i', 'j' and 'u'. -+ Use a temporary array rather than imm_reloc when parsing -+ constant expressions. Remove imm_reloc initialization. -+ (mips16_ip): Update commentary. Use offset_expr and offset_reloc -+ for the relaxable field. Use a relax_char variable to track the -+ type of this field. Remove imm_reloc initialization. -+ -+2013-07-14 Richard Sandiford -+ -+ * config/tc-mips.c (mips16_ip): Handle "I". -+ -+2013-07-12 Maciej W. Rozycki -+ -+ * config/tc-mips.c (mips_flag_nan2008): New variable. -+ (options): Add OPTION_NAN enum value. -+ (md_longopts): Handle it. -+ (md_parse_option): Likewise. -+ (s_nan): New function. -+ (mips_elf_final_processing): Handle EF_MIPS_NAN2008. -+ (md_show_usage): Add -mnan. -+ -+ * doc/as.texinfo (Overview): Add -mnan. -+ * doc/c-mips.texi (MIPS Opts): Document -mnan. -+ (MIPS NaN Encodings): New node. Document .nan directive. -+ (MIPS-Dependent): List the new node. -+ -+2013-07-09 Tristan Gingold -+ -+ * configure.com: Define HAVE_SYS_TYPES_H and HAVE_UNISTD_H -+ -+2013-07-08 Richard Sandiford -+ -+ * config/tc-mips.c (mips_ip): Unconditionally parse an expression -+ for 'A' and assume that the constant has been elided if the result -+ is an O_register. -+ -+2013-07-07 Richard Sandiford -+ -+ * config/tc-mips.c (gprel16_reloc_p): New function. -+ (macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are -+ BFD_RELOC_UNUSED. -+ (offset_high_part, small_offset_p): New functions. -+ (nacro): Use them. Remove *_OB and *_DOB cases. For single- -+ register load and store macros, handle the 16-bit offset case first. -+ If a 16-bit offset is not suitable for the instruction we're -+ generating, load it into the temporary register using -+ ADDRESS_ADDI_INSN. Make the M_LI_DD code fall through into the -+ M_L_DAB code once the address has been constructed. For double load -+ and store macros, again handle the 16-bit offset case first. -+ If the second register cannot be accessed from the same high -+ part as the first, load it into AT using ADDRESS_ADDI_INSN. -+ Fix the handling of LD in cases where the first register is the -+ same as the base. Also handle the case where the offset is -+ not 16 bits and the second register cannot be accessed from the -+ same high part as the first. For unaligned loads and stores, -+ fuse the offbits == 12 and old "ab" handling. Apply this handling -+ whenever the second offset needs a different high part from the first. -+ Construct the offset using ADDRESS_ADDI_INSN where possible, -+ for offbits == 16 as well as offbits == 12. Use offset_reloc -+ when constructing the individual loads and stores. -+ (mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc -+ and offset_reloc before matching against a particular opcode. -+ Handle elided 'A' constants. Allow 'A' constants to use -+ relocation operators. -+ -+2013-07-07 Richard Sandiford -+ -+ * config/tc-mips.c (validate_mips_insn): Remove "[" and "]" handling. -+ (mips_ip): Likewise. Do not set is_mdmx for INSN_5400 instructions. -+ Check constraints on the VR5400 RZU.OB, SLL.OB and SRL.OB instructions. -+ -+2013-07-07 Richard Sandiford -+ -+ * config/tc-mips.c (mips_ip): Preserve the real bit number for "+p". -+ Require the msb to be <= 31 for "+s". Check that the size is <= 31 -+ for both "+s" and "+S". -+ -+2013-07-07 Richard Sandiford -+ -+ * config/tc-mips.c (validate_mips_insn, validate_micromips_insn): -+ (mips_ip, mips16_ip): Handle "+i". -+ -+2013-07-07 Richard Sandiford -+ -+ * config/tc-mips.c (mips32_to_micromips_reg_h_map): Delete. -+ (micromips_to_32_reg_h_map): Rename to... -+ (micromips_to_32_reg_h_map1): ...this. -+ (micromips_to_32_reg_i_map): Rename to... -+ (micromips_to_32_reg_h_map2): ...this. -+ (mips_lookup_reg_pair): New function. -+ (gpr_write_mask, macro): Adjust after above renaming. -+ (validate_micromips_insn): Remove "mi" handling. -+ (mips_ip): Likewise. Parse both registers in a pair for "mh". -+ -+2013-07-07 Richard Sandiford -+ -+ * config/tc-mips.c (validate_mips_insn, validate_micromips_insn) -+ (mips_ip): Remove "+D" and "+T" handling. -+ -+2013-07-05 Andreas Krebbel -+ -+ * config/tc-s390.c (md_gather_operands, md_apply_fix): Support new -+ relocs. -+ -+2013-07-03 Marcus Shawcroft -+ -+ * config/tc-aarch64.c (reloc_table): Merge got_prel19 into got. -+ -+2013-07-02 Marcus Shawcroft -+ -+ * config/tc-aarch64.c (md_apply_fix): Reorder case values. -+ (aarch64_force_relocation): Likewise. -+ -+2013-07-02 Alan Modra -+ -+ * config/tc-ppc.c (ppc_elf_adjust_symtab): Don't make .TOC. weak. -+ -+2013-06-26 Maciej W. Rozycki -+ -+ * doc/as.texinfo (Overview): Remove @samp from MIPS ISA names. -+ * doc/c-mips.texi (MIPS Options): Remove @sc from MIPS ISA names. -+ Replace @sc{mips16} with literal `MIPS16'. -+ (MIPS ISA): Replace @sc{mips3} with literal `MIPS III'. -+ -+2013-06-26 Yufeng Zhang -+ -+ * config/tc-aarch64.c (reloc_table): Replace -+ BFD_RELOC_AARCH64_LD64_GOT_LO12_NC with -+ BFD_RELOC_AARCH64_LD_GOT_LO12_NC; likewise to -+ BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC and -+ BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC. -+ (md_apply_fix): Handle BFD_RELOC_AARCH64_LD_GOT_LO12_NC, -+ BFD_RELOC_AARCH64_LD32_GOT_LO12_NC, -+ BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC, -+ BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC, -+ BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC and -+ BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC. -+ (aarch64_force_relocation): Likewise. -+ -+2013-06-26 Yufeng Zhang -+ -+ * config/tc-aarch64.c (ilp32_p): New static variable. -+ (elf64_aarch64_target_format): Return the target according to the -+ value of 'ilp32_p'. -+ (md_begin): Determine 'mach' according to the value of 'ilp32_p'. -+ (aarch64_opts): Add support for options '-milp32' and '-mlp64'. -+ (aarch64_dwarf2_addr_size): New function. -+ * config/tc-aarch64.h (aarch64_dwarf2_addr_size): New declaration. -+ (DWARF2_ADDR_SIZE): New define. -+ -+2013-06-26 Richard Sandiford -+ -+ * doc/c-mips.texi: Use ISA instead of @sc{isa}. -+ -+2013-06-26 Richard Sandiford -+ -+ * config/tc-mips.c (validate_mips_insn): Use STYPE rather than SHAMT. -+ -+2013-06-25 Maciej W. Rozycki -+ -+ * config/tc-mips.c (mips_set_options): Add insn32 member. -+ (mips_opts): Initialize it. -+ (NOP_INSN, NOP_INSN_SIZE): Handle insn32 mode. -+ (options): Add OPTION_INSN32 and OPTION_NO_INSN32 enum values. -+ (md_longopts): Add "minsn32" and "mno-insn32" options. -+ (is_size_valid): Handle insn32 mode. -+ (md_assemble): Pass instruction string down to macro. -+ (brk_fmt): Add second dimension and insn32 mode initializers. -+ (mfhl_fmt): Likewise. -+ (BRK_FMT, MFHL_FMT): Handle insn32 mode. -+ (macro_build) <'c'>: Handle microMIPS 32-bit BREAK encoding. -+ (macro_build_jalr, move_register): Handle insn32 mode. -+ (macro_build_branch_rs): Likewise. -+ (macro): Handle insn32 mode. -+ , , : New cases. -+ (mips_ip): Handle insn32 mode. -+ (md_parse_option): Handle OPTION_INSN32 and OPTION_NO_INSN32. -+ (s_mipsset): Handle "insn32" and "noinsn32" pseudo-ops. -+ (mips_handle_align): Handle insn32 mode. -+ (md_show_usage): Add -minsn32 and -mno-insn32. -+ -+ * doc/as.texinfo (Target MIPS options): Add -minsn32 and -+ -mno-insn32 options. -+ (-minsn32, -mno-insn32): New options. -+ * doc/c-mips.texi (MIPS Opts): Add -minsn32 and -mno-insn32 -+ options. -+ (MIPS assembly options): New node. Document .set insn32 and -+ .set noinsn32. -+ (MIPS-Dependent): List the new node. -+ -+2013-06-25 Nick Clifton -+ -+ * config/tc-msp430.c (msp430_srcoperand): Do not allow the use of -+ the PC in indirect addressing on 430xv2 parts. -+ (msp430_operands): Add version test to hardware bug encoding -+ restrictions. -+ -+2013-06-24 Roland McGrath -+ -+ * config/tc-arm.c (parse_reg_list): Use skip_past_char for '}', -+ so it skips whitespace before it. -+ (s_arm_unwind_save_mmxwr, s_arm_unwind_save_mmxwcg): Likewise. -+ -+ * config/tc-arm.c (arm_symbol_chars): Include '{' and '}'. -+ (arm_reg_parse_multi): Skip whitespace first. -+ (parse_reg_list): Likewise. -+ (parse_vfp_reg_list): Likewise. -+ (s_arm_unwind_save_mmxwcg): Likewise. -+ -+2013-06-24 Nick Clifton -+ -+ PR gas/15623 -+ * config/tc-arm.c (do_t_smc): Mark as ending an IT block. -+ -+2013-06-23 Richard Sandiford -+ -+ * config/tc-mips.c (mips_ip): Fix swapped bit numbers in comments. -+ -+2013-06-23 Richard Sandiford -+ -+ * config/tc-mips.c: Assert that offsetT and valueT are at least -+ 8 bytes in size. -+ (GPR_SMIN, GPR_SMAX): New macros. -+ (macro, mips_ip): Remove code for 4-byte valueT and offsetT. -+ -+2013-06-22 Richard Sandiford -+ -+ * config/tc-mips.c: Remove OBJ_ELF, OBJ_MAYBE_ELF and IS_ELF -+ conditions. Remove any code deselected by them. -+ (s_mips_frame, s_mips_mask): Handle ECOFF_DEBUGGING case first. -+ -+2013-06-22 Richard Sandiford -+ -+ * NEWS: Note removal of ECOFF support. -+ * doc/as.texinfo (--emulation): Update for the removal of MIPS ECOFF. -+ * Makefile.am (TARG_ENV_HFILES): Remove config/te-lnews.h. -+ (MULTI_CFILES): Remove config/e-mipsecoff.c. -+ * Makefile.in: Regenerate. -+ * configure.in: Remove MIPS ECOFF references. -+ (mips-sony-bsd*, mips-*-bsd*, mips-*-lnews*-ecoff, mips-*-*-ecoff): -+ Delete cases. -+ (mips-*-irix5*-*, mips*-*-linux*-*, mips*-*-freebsd*) -+ (mips*-*-kfreebsd*-gnu, mips-*-*-elf): Fold into... -+ (mips-*-*): ...this single case. -+ (mipsbecoff, mipslecoff, mipsecoff): Remove emulations. Expect -+ MIPS emulations to be e-mipself*. -+ * configure: Regenerate. -+ * configure.tgt (mips-sony-bsd*, mips-*-ultrix*, mips-*-osf*) -+ (mips-*-ecoff*, mips-*-pe*, mips-*-irix*, ips-*-lnews*, mips-*-riscos*) -+ (mips-*-sysv*): Remove coff and ecoff cases. -+ * as.c (mipsbecoff, mipslecoff, mipsecoff): Remove. -+ * ecoff.c: Remove reference to MIPS ECOFF. -+ * config/e-mipsecoff.c, config/te-lnews.h: Delete files. -+ * config/tc-mips.c (ECOFF_LITTLE_FORMAT): Delete. -+ (RDATA_SECTION_NAME, mips_target_form): Remove COFF and ECOFF cases. -+ (mips_hi_fixup): Tweak comment. -+ (append_insn): Require a howto. -+ (mips_after_parse_args): Remove OBJ_MAYBE_ECOFF code. -+ -+2013-06-22 Richard Sandiford -+ -+ * doc/as.texinfo: Use MIPS rather than @sc{mips} throughout. -+ Use "CPU" instead of "cpu". -+ * doc/c-mips.texi: Likewise. -+ (MIPS Opts): Rename to MIPS Options. -+ (MIPS option stack): Rename to MIPS Option Stack. -+ (MIPS ASE instruction generation overrides): Rename to -+ MIPS ASE Instruction Generation Overrides (for now). -+ (MIPS floating-point): Rename to MIPS Floating-Point. -+ -+2013-06-22 Richard Sandiford -+ -+ * doc/c-mips.texi (MIPS Macros): New section. -+ (MIPS Object): Replace with... -+ (MIPS Small Data): ...this new section. -+ -+2013-06-22 Richard Sandiford -+ -+ * doc/c-mips.texi (MIPS symbol sizes): Move section further up file. -+ Capitalize name. Use @kindex instead of @cindex for .set entries. -+ -+2013-06-22 Richard Sandiford -+ -+ * doc/c-mips.texi (MIPS Stabs): Remove section. -+ -+2013-06-20 Richard Sandiford -+ -+ * config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS, ISA_SUPPORTS_DSP_ASE) -+ (ISA_SUPPORTS_DSP64_ASE, ISA_SUPPORTS_DSPR2_ASE, ISA_SUPPORTS_EVA_ASE) -+ (ISA_SUPPORTS_MT_ASE, ISA_SUPPORTS_MCU_ASE, ISA_SUPPORTS_VIRT_ASE) -+ (ISA_SUPPORTS_VIRT64_ASE): Delete. -+ (mips_ase): New structure. -+ (mips_ases): New table. -+ (FP64_ASES): New macro. -+ (mips_ase_groups): New array. -+ (mips_isa_rev, mips_ase_mask, mips_check_isa_supports_ase) -+ (mips_check_isa_supports_ases, mips_set_ase, mips_lookup_ase): New -+ functions. -+ (is_opcode_valid): Use mips_ases to get the 64-bit ASE flags. -+ (md_parse_option): Use mips_ases and mips_set_ase instead of -+ separate case statements for each ASE option. -+ (mips_after_parse_args): Use FP64_ASES. Use -+ mips_check_isa_supports_ases to check the ASEs against -+ other options. -+ (s_mipsset): Use mips_ases and mips_set_ase instead of -+ separate if statements for each ASE option. Use -+ mips_check_isa_supports_ases, even when a non-ASE option -+ is specified. -+ -+2013-06-19 Greta Yorsh -+ -+ * config/tc-arm.c (arm_cpus): Add support for Cortex-A12. -+ -+2013-06-18 Richard Sandiford -+ -+ * config/tc-mips.c (md_shortopts, options, md_longopts) -+ (md_longopts_size): Move earlier in file. -+ -+2013-06-18 Richard Sandiford -+ -+ * config/tc-mips.c (mips_set_options): Replace separate "ase_*" fields -+ with a single "ase" bitmask. -+ (mips_opts): Update accordingly. -+ (file_ase, file_ase_explicit): New variables. -+ (file_ase_mips3d, file_ase_mdmx, file_ase_smartmips, file_ase_dsp) -+ (file_ase_dspr2, file_ase_eva, file_ase_mt, file_ase_virt): Delete. -+ (ISA_HAS_ROR): Adjust for mips_set_options change. -+ (is_opcode_valid): Take the base ase mask directly from mips_opts. -+ (mips_ip): Adjust for mips_set_options change. -+ (md_parse_option): Likewise. Update file_ase_explicit. -+ (mips_after_parse_args): Adjust for mips_set_options change. -+ Use bitmask operations to select the default ASEs. Set file_ase -+ rather than individual per-ASE variables. -+ (s_mipsset): Adjust for mips_set_options change. -+ (mips_elf_final_processing): Test file_ase rather than -+ file_ase_mdmx. Remove commented-out code. -+ -+2013-06-18 Richard Sandiford -+ -+ * config/tc-mips.c (mips_cpu_info): Add an "ase" field. -+ (MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP, MIPS_CPU_ASE_MT) -+ (MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX, MIPS_CPU_ASE_DSPR2) -+ (MIPS_CPU_ASE_MCU, MIPS_CPU_ASE_VIRT, MIPS_CPU_ASE_EVA): Delete. -+ (mips_after_parse_args): Use the new "ase" field to choose -+ the default ASEs. -+ (mips_cpu_info_table): Move ASEs from the "flags" field to the -+ "ase" field. -+ -+2013-06-18 Richard Earnshaw -+ -+ * config/tc-arm.c (symbol_preemptible): New function. -+ (relax_branch): Use it. -+ -+2013-06-17 Catherine Moore -+ Maciej W. Rozycki -+ Chao-Ying Fu -+ -+ * config/tc-mips.c (mips_set_options): Add ase_eva. -+ (mips_set_options mips_opts): Add ase_eva. -+ (file_ase_eva): Declare. -+ (ISA_SUPPORTS_EVA_ASE): Define. -+ (IS_SEXT_9BIT_NUM): Define. -+ (MIPS_CPU_ASE_EVA): Define. -+ (is_opcode_valid): Add support for ase_eva. -+ (macro_build): Likewise. -+ (macro): Likewise. -+ (validate_mips_insn): Likewise. -+ (validate_micromips_insn): Likewise. -+ (mips_ip): Likewise. -+ (options): Add OPTION_EVA and OPTION_NO_EVA. -+ (md_longopts): Add -meva and -mno-eva. -+ (md_parse_option): Process new options. -+ (mips_after_parse_args): Check for valid EVA combinations. -+ (s_mipsset): Likewise. -+ -+2013-06-14 Richard Sandiford -+ -+ * dwarf2dbg.h (dwarf2_move_insn): Declare. -+ * dwarf2dbg.c (line_subseg): Add pmove_tail. -+ (get_line_subseg): Add create_p argument. Initialize pmove_tail. -+ (dwarf2_gen_line_info_1): Update call accordingly. -+ (dwarf2_move_insn): New function. -+ * config/tc-mips.c (append_insn): Use dwarf2_move_insn. -+ -+2013-06-14 Richard Sandiford -+ -+ Revert: -+ -+ 2011-09-05 Richard Sandiford -+ -+ PR gas/13024 -+ * dwarf2dbg.c (pending_lines, pending_lines_tail): New variables. -+ (dwarf2_gen_line_info_1): Delete. -+ (dwarf2_push_line, dwarf2_flush_pending_lines): New functions. -+ (dwarf2_gen_line_info, dwarf2_emit_label): Use them. -+ (dwarf2_consume_line_info): Call dwarf2_flush_pending_lines. -+ (dwarf2_directive_loc): Push previous .locs instead of generating -+ them immediately. -+ -+2013-06-13 Chao-ying Fu -+ -+ * config/tc-mips.c (ISA_SUPPORTS_VIRT_ASE): Support micromips. -+ (ISA_SUPPORTS_VIRT64_ASE): Support 64-bit micromips. -+ -+2013-06-13 Nick Clifton -+ -+ PR gas/15602 -+ * config/tc-m68k.h (TC_CHECK_ADJUSTED_BROKEN_DOT_WORD): Define. -+ * config/tc-m68k.c (tc_m68k_check_adjusted_broken_word): New -+ function. Generates an error if the adjusted offset is out of a -+ 16-bit range. -+ -+2013-06-12 Sandra Loosemore -+ -+ * config/tc-nios2.c (md_apply_fix): Mask constant -+ BFD_RELOC_NIOS2_HIADJ16 value to 16 bits. -+ -+2013-06-10 Maciej W. Rozycki -+ -+ * config/tc-mips.c (append_insn): Don't do branch relaxation for -+ MIPS-3D instructions either. -+ (md_convert_frag): Update the COPx branch mask accordingly. -+ -+ * config/tc-mips.c (md_show_usage): Document --[no-]relax-branch -+ option. -+ * doc/as.texinfo (Overview): Add --relax-branch and -+ --no-relax-branch. -+ * doc/c-mips.texi (MIPS Opts): Document --relax-branch and -+ --no-relax-branch. -+ -+2013-06-09 Sandra Loosemore -+ -+ * config/tc-nios2.c (nios2_parse_args): Allow trap argument to -+ omitted. -+ -+2013-06-08 Catherine Moore -+ -+ * config/tc-mips.c (is_opcode_valid): Build ASE mask. -+ (is_opcode_valid_16): Pass ase value to opcode_is_member. -+ (append_insn): Change INSN_xxxx to ASE_xxxx. -+ -+2013-06-01 George Thomas -+ -+ * gas/config/tc-avr.c: Change ISA for devices with USB support to -+ AVR_ISA_XMEGAU -+ -+2013-05-31 H.J. Lu -+ -+ * config/tc-i386.c (md_begin): Don't align text/data/bss sections -+ for ELF. -+ -+2013-05-31 Paul Brook -+ -+ * config/tc-mips.c (s_ehword): New. -+ -+2013-05-30 Paul Brook -+ -+ * config/tc-mips.c (md_apply_fix): Support BFD_RELOC_MIPS_EH. -+ -+2013-05-29 Maciej W. Rozycki -+ -+ * write.c (resolve_reloc_expr_symbols): On REL targets don't -+ convert relocs who have no relocatable field either. Rephrase -+ the conditional so that the PC-relative check is only applied -+ for REL targets. -+ -+2013-05-28 Chao-ying Fu -+ -+ * config/tc-mips.c (macro) : Don't use $zero for address -+ calculation. -+ -+2013-05-28 Yufeng Zhang -+ -+ * config/tc-aarch64.c (reloc_table): Update to use -+ BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21 instead of -+ BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE. -+ (md_apply_fix): Likewise. -+ (aarch64_force_relocation): Likewise. -+ -+2013-05-28 Kyrylo Tkachov -+ -+ * config/tc-arm.c (it_fsm_post_encode): Improve -+ warning messages about deprecated IT block formats. -+ -+2013-05-28 Marcus Shawcroft -+ -+ * config/tc-aarch64.c (md_apply_fix): Move value range checking -+ inside fx_done condition. -+ -+2013-05-22 Jürgen Urban -+ -+ * config/tc-mips.c (macro): Handle M_LQC2_AB and M_SQC2_AB. -+ -+2013-05-20 Peter Bergner -+ -+ * config/tc-ppc.c (ppc_setup_opcodes): Use new_seg to fix error -+ and clean up warning when using PRINT_OPCODE_TABLE. -+ -+2013-05-20 Alan Modra -+ -+ * config/tc-ppc.c (md_apply_fix): Hoist code common to insn -+ and data fixups performing shift/high adjust/sign extension on -+ fieldval. Sink fx_pcrel handling and checks. Use fixP->fx_size -+ when writing data fixups rather than recalculating size. -+ -+2013-05-16 Jan-Benedict Glaw -+ -+ * doc/c-msp430.texi: Fix typo. -+ -+2013-05-16 Tristan Gingold -+ -+ * config/tc-ppc.c (ppc_is_toc_sym): Symbols of class XMC_TC -+ are also TOC symbols. -+ -+2013-05-16 Nick Clifton -+ -+ * config/tc-msp430.c: Make -mmcu recognise more part numbers. -+ Add -mcpu command to specify core type. -+ * doc/c-msp430.texi: Update documentation. -+ -+2013-05-09 Andrew Pinski -+ -+ * config/tc-mips.c (struct mips_set_options): New ase_virt field. -+ (mips_opts): Update for the new field. -+ (file_ase_virt): New variable. -+ (ISA_SUPPORTS_VIRT_ASE): New macro. -+ (ISA_SUPPORTS_VIRT64_ASE): New macro. -+ (MIPS_CPU_ASE_VIRT): New define. -+ (is_opcode_valid): Handle ase_virt. -+ (macro_build): Handle "+J". -+ (validate_mips_insn): Likewise. -+ (mips_ip): Likewise. -+ (enum options): Add OPTION_VIRT and OPTION_NO_VIRT. -+ (md_longopts): Add mvirt and mnovirt -+ (md_parse_option): Handle OPTION_VIRT and OPTION_NO_VIRT. -+ (mips_after_parse_args): Handle ase_virt field. -+ (s_mipsset): Handle "virt" and "novirt". -+ (mips_elf_final_processing): Add a comment about virt ASE might need -+ a new flag. -+ (md_show_usage): Print out the usage of -mvirt and mno-virt options. -+ * doc/c-mips.texi: Document -mvirt and -mno-virt. -+ Document ".set virt" and ".set novirt". -+ -+2013-05-09 Alan Modra -+ -+ * config/tc-ppc.c (md_apply_fix): Sign extend fieldval under -+ control of operand flag bits. -+ -+2013-05-07 Alan Modra -+ -+ * config/tc-ppc.c (PPC_VLE_SPLIT16A): Delete unused macro. -+ (PPC_VLE_SPLIT16D, PPC_VLE_LO16A, PPC_VLE_LO16D): Likewise. -+ (PPC_VLE_HI16A, PPC_VLE_HI16D): Likewise. -+ (PPC_VLE_HA16A, PPC_VLE_HA16D): Likewise. -+ (md_apply_fix): Set fx_no_overflow for assorted relocations. -+ Shift and sign-extend fieldval for use by some VLE reloc -+ operand->insert functions. -+ -+2013-05-06 Paul Brook -+ Catherine Moore -+ -+ * config/tc-mips.c (md_pcrel_from): Handle BFD_RELOC_32_PCREL. -+ (limited_pcrel_reloc_p): Likewise. -+ (md_apply_fix): Likewise. -+ (tc_gen_reloc): Likewise. -+ -+2013-05-06 Richard Sandiford -+ -+ * config/tc-mips.c (limited_pcrel_reloc_p): New function. -+ (mips_fix_adjustable): Adjust pc-relative check to use -+ limited_pc_reloc_p. -+ -+2013-05-02 Richard Sandiford -+ -+ * config/tc-mips.c (mips_pseudo_table): Add stabd and stabs entries. -+ (s_mips_stab): Do not restrict to stabn only. -+ -+2013-05-02 Nick Clifton -+ -+ * config/tc-msp430.c: Add support for the MSP430X architecture. -+ Add code to insert a NOP instruction after any instruction that -+ might change the interrupt state. -+ Add support for the LARGE memory model. -+ Add code to initialise the .MSP430.attributes section. -+ * config/tc-msp430.h: Add support for the MSP430X architecture. -+ * doc/c-msp430.texi: Document the new -mL and -mN command line -+ options. -+ * NEWS: Mention support for the MSP430X architecture. -+ -+2013-05-01 Maciej W. Rozycki -+ -+ * configure.tgt: Replace alpha*-*-linuxecoff* pattern with -+ alpha*-*-linux*ecoff*. -+ -+2013-04-30 Chao-ying Fu -+ -+ * config/tc-mips.c (mips_ip): Add sizelo. -+ For "+C", "+G", and "+H", set sizelo and compare against it. -+ -+2013-04-29 Nick Clifton -+ -+ * as.c (Options): Add -gdwarf-sections. -+ (parse_args): Likewise. -+ * as.h (flag_dwarf_sections): Declare. -+ * dwarf2dbg.c (emit_fixed_inc_line_addr): Skip section changes. -+ (process_entries): When -gdwarf-sections is enabled generate -+ fragmentary .debug_line sections. -+ (out_debug_line): Set the section for the .debug_line section end -+ symbol. -+ * doc/as.texinfo: Document -gdwarf-sections. -+ * NEWS: Mention -gdwarf-sections. -+ -+2013-04-26 Christian Groessler -+ -+ * config/tc-z8k.c (md_parse_option): Set z8k_target_from_cmdline -+ according to the target parameter. Don't call s_segm since s_segm -+ calls bfd_set_arch_mach using stdoutput, but stdoutput isn't -+ initialized yet. -+ (md_begin): Call s_segm according to target parameter from command -+ line. -+ -+2013-04-25 Alan Modra -+ -+ * configure.in: Allow little-endian linux. -+ * configure: Regenerate. -+ -+2013-04-24 Sandra Loosemore -+ -+ * config/tc-nios2.c (nios2_control_register_arg_p): Rename -+ "fstatus" control register to "eccinj". -+ -+2013-04-19 Kai Tietz -+ -+ * configure.tgt (i386-*-cygwin): Handle x86_64 cygwin. -+ -+2013-04-15 Julian Brown -+ -+ * expr.c (add_to_result, subtract_from_result): Make global. -+ * expr.h (add_to_result, subtract_from_result): Add prototypes. -+ * config/tc-sh.c (sh_optimize_expr): Use add_to_result, -+ subtract_from_result to handle extra bit of precision for .sleb128 -+ directive operands. -+ -+2013-04-10 Julian Brown -+ -+ * read.c (convert_to_bignum): Add sign parameter. Use it -+ instead of X_unsigned to determine sign of resulting bignum. -+ (emit_expr): Pass extra argument to convert_to_bignum. -+ (emit_leb128_expr): Use X_extrabit instead of X_unsigned. Pass -+ X_extrabit to convert_to_bignum. -+ (parse_bitfield_cons): Set X_extrabit. -+ * expr.c (make_expr_symbol, expr_build_uconstant, operand): -+ Initialise X_extrabit field as appropriate. -+ (add_to_result): New. -+ (subtract_from_result): New. -+ (expr): Use above. -+ * expr.h (expressionS): Add X_extrabit field. -+ -+2013-04-10 Jan Beulich -+ -+ * gas/config/tc-arm.c (encode_arm_addr_mode_3): Only reject base -+ register being PC when is_t or writeback, and use distinct -+ diagnostic for the latter case. -+ -+2013-04-10 Jan Beulich -+ -+ * gas/config/tc-arm.c (parse_operands): Re-write -+ po_barrier_or_imm(). -+ (do_barrier): Remove bogus constraint(). -+ (do_t_barrier): Remove. -+ -+2013-04-09 Joerg Wunsch -+ -+ * gas/config/tc-avr.c (mcu_types): Add ATmega64RFR2, -+ ATmega644RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega256RFR2, -+ ATmega2564RFR2 -+ * gas/doc/c-avr.texi (-mmcu documentation): Likewise. -+ -+2013-04-09 Jan Beulich -+ -+ * gas/config/tc-arm.c (do_vmrs): Accept all control registers. -+ Use local variable Rt in more places. -+ (do_vmsr): Accept all control registers. -+ -+2013-04-09 Jan Beulich -+ -+ * gas/config/tc-arm.c (do_neon_mov): Fake an instruction suffix -+ if there was none specified for moves between scalar and core -+ register. -+ -+2013-04-09 Jan Beulich -+ -+ * gas/config/tc-arm.c (do_neon_ldx_stx): Reject VSTn in the -+ NEON_ALL_LANES case. -+ -+2013-04-08 Jan Beulich -+ -+ * gas/config/tc-arm.c (do_neon_ldr_str): Correct disgnostics for -+ PC-relative VSTR. -+ -+2013-04-08 Jan Beulich -+ -+ * gas/config/tc-arm.c (reg_names): Convert duplicate SP_fiq -+ entry to sp_fiq. -+ -+2013-04-03 Alan Modra -+ -+ * doc/as.texinfo: Add support to generate man options for h8300. -+ * doc/c-h8300.texi: Likewise. -+ -+2013-03-28 Ramana Radhakrishnan -+ -+ * config/tc-arm.c (arm_cpus): Add support for Cortex-A53 and -+ Cortex-A57. -+ -+2013-03-27 Alexis Deruelle -+ -+ PR binutils/15068 -+ * config/tc-tic6x.c (tic6x_try_encode): Add use of bitfields array. -+ -+2013-03-26 Nick Clifton -+ -+ PR gas/15295 -+ * listing.c (rebuffer_line): Rewrite to avoid seeking back to the -+ start of the file each time. -+ -+ PR gas/15178 -+ * config/tc-sparc.h (ELF_TARGET_FORMAT): Set to elf32-sparc for -+ FreeBSD targets. -+ -+2013-03-26 Douglas B Rupp -+ -+ * config/tc-ia64.c (emit_one_bundle): Move last_slot adjustment -+ after fixup. -+ -+2013-03-21 Will Newton -+ -+ * config/tc-arm.c (encode_thumb32_addr_mode): Emit an error for all -+ pc-relative str instructions in Thumb mode. -+ -+2013-03-21 Michael Schewe -+ -+ * config/tc-h8300.c (do_a_fix_imm): Add relaxation of mov -+ @(disp:32,ERx) to mov @(disp:16,ERx) insns by new reloc -+ R_H8_DISP32A16. -+ * config/tc-h8300.h: Remove duplicated defines. -+ -+2013-03-21 Senthil Kumar Selvaraj -+ -+ PR gas/15282 -+ * tc-avr.c (mcu_has_3_byte_pc): New function. -+ (tc_cfi_frame_initial_instructions): Call it to find return -+ address size. -+ -+2013-03-20 Alexis Deruelle -+ -+ PR gas/15095 -+ * config/tc-tic6x.c (tic6x_try_encode): Handle -+ tic6x_coding_dreg_(msb|lsb) field coding types and use it to -+ encode register pair numbers when required. -+ -+2013-03-15 Will Newton -+ -+ * config/tc-arm.c (do_neon_ldr_str): Fix error check for PC register -+ in vstr in Thumb mode for pre-ARMv7 cores. -+ -+2013-03-14 Andreas Schwab -+ -+ * doc/c-arc.texi (ARC Directives): Revert last change and use -+ @itemize instead of @table. -+ * doc/c-arm.texi (ARM-Instruction-Set): Likewise. -+ -+2013-03-14 Nick Clifton -+ -+ PR gas/15273 -+ * config/tc-arm.c (do_co_reg): Do not call check_obsolete with a -+ NULL message, instead just check ARM_CPU_IS_ANY directly. -+ -+2013-03-14 Nick Clifton -+ -+ PR gas/15212 -+ * doc/c-arc.texi (ARC Directives): Use @code instead of @bullet -+ for table format. -+ * doc/c-arm.texi (ARM-Instruction-Set): Likewise. Also add text -+ to the @item directives. -+ (ARM-Neon-Alignment): Move to correct place in the document. -+ * doc/c-cr16.texi (CR16 Operand Qualifiers): Fix up table -+ formatting. -+ * doc/c-tic54x.texi (TIC54X-Subsyms): Correct use of -+ @smallexample. -+ -+2013-03-12 Sebastian Huber -+ -+ * config/tc-nios2.c (nios2_consume_arg): Delete 'k' case. Add 'o' -+ case. Add default BAD_CASE to switch. -+ -+2013-03-11 Sebastian Huber -+ -+ * config/tc-nios2.c (nios2_assemble_args_ds): New function. -+ (nios2_arg_info_structs): Add "d,s" and "d,s,E" entries. -+ -+2013-03-11 Kyrylo Tkachov -+ -+ * config/tc-arm.c (crc_ext_armv8): New feature set. -+ (UNPRED_REG): New macro. -+ (do_crc32_1): New function. -+ (do_crc32b, do_crc32h, do_crc32w, do_crc32cb, -+ do_crc32ch, do_crc32cw): Likewise. -+ (TUEc): New macro. -+ (insns): Add entries for crc32 mnemonics. -+ (arm_extensions): Add entry for crc. -+ -+2013-03-08 Chung-Lin Tang -+ -+ * write.h (struct fix): Add fx_dot_frag field. -+ (dot_frag): Declare. -+ * write.c (dot_frag): New variable. -+ (fix_new_internal): Set fx_dot_frag field with dot_frag. -+ (fixup_segment): Base calculation of fx_offset with fx_dot_frag. -+ * expr.c (expr): Save value of frag_now in dot_frag when setting -+ dot_value. -+ * read.c (emit_expr): Likewise. Delete comments. -+ -+2013-03-07 H.J. Lu -+ -+ * config/tc-i386.c (flag_code_names): Removed. -+ (i386_index_check): Rewrote. -+ -+2013-03-05 Yufeng Zhang -+ -+ * config/tc-aarch64.c (aarch64_imm_float_p): Rename 'e' to 'pattern'; -+ add comment. -+ (aarch64_double_precision_fmovable): New function. -+ (parse_aarch64_imm_float): Add parameter 'dp_p'; call the new -+ function; handle hexadecimal representation of IEEE754 encoding. -+ (parse_operands): Update the call to parse_aarch64_imm_float. -+ -+2013-02-28 H.J. Lu -+ -+ * config/tc-i386.c (_i386_insn): Replace have_hle with hle_prefix. -+ (check_hle): Updated. -+ (md_assemble): Likewise. -+ (parse_insn): Likewise. -+ -+2013-02-28 H.J. Lu -+ -+ * config/tc-i386.c (_i386_insn): Add rep_prefix. -+ (md_assemble): Check if REP prefix is OK. -+ (parse_insn): Remove expecting_string_instruction. Set -+ i.rep_prefix. -+ -+2013-02-28 Yufeng Zhang -+ -+ * config/tc-aarch64.c (aarch64_features): Add the 'crc' option. -+ -+2013-02-28 Yufeng Zhang -+ -+ * config/tc-aarch64.c (parse_sys_reg): Allow the full range of CRn -+ for system registers. -+ -+2013-02-27 DJ Delorie -+ -+ * config/tc-rl78.c (reloc_function): Add %code -> BFD_RELOC_RL78_CODE. -+ (rl78_op): Handle %code(). -+ (rl78_cons_fix_new): Likewise, but ignore for 20-bit operands. -+ (tc_gen_reloc): Likwise; convert to a computed reloc. -+ (md_apply_fix): Likewise. -+ -+2013-02-25 Kaushik Phatak -+ -+ * config/rl78-parse.y: Fix encoding of DIVWU insn. -+ -+2013-02-25 Terry Guo -+ -+ * config/tc-arm.c (arm_cpus): Add cortex-r7 entry. -+ * doc/c-arm.texi: Add cortex-r7 and missing cortex-r5 to -+ list of accepted CPUs. -+ -+2013-02-19 H.J. Lu -+ -+ PR gas/15159 -+ * config/tc-i386.c (cpu_arch): Add ".smap". -+ -+ * doc/c-i386.texi: Document smap. -+ -+2013-02-18 Maciej W. Rozycki -+ -+ * config/tc-mips.c (s_cpload): Call mips_mark_labels and set -+ mips_assembling_insn appropriately. -+ (s_cpsetup, s_cprestore, s_cpreturn, s_cpadd): Likewise. -+ -+2013-02-18 Maciej W. Rozycki -+ -+ * config/tc-mips.c (append_insn): Correct indentation, remove -+ extraneous braces. -+ -+2013-02-15 Kyrylo Tkachov -+ -+ * config/tc-arm.c (do_neon_mov): Break on NS_NULL. -+ -+2013-02-15 Sebastian Huber -+ -+ * configure.tgt: Add nios2-*-rtems*. -+ -+2013-02-14 Yufeng Zhang -+ -+ * config/tc-aarch64.c (md_begin): Change to check if 'name' is -+ NULL. -+ -+2013-02-09 Jürgen Urban -+ -+ * config/tc-mips.c (CPU_HAS_LDC1_SDC1): New macro. -+ (macro): Use it. Assert that trunc.w.s is not used for r5900. -+ -+2013-02-08 Yi-Hsiu, Hsu -+ -+ * gas/config/tc-arm.c (arm_cpus): Add support for mcpu=marvell-pj4 -+ core. -+ -+2013-02-06 Sandra Loosemore -+ Andrew Jenner -+ -+ Based on patches from Altera Corporation. -+ -+ * Makefile.am (TARGET_CPU_CFILES): Add config/tc-nios2.c. -+ (TARGET_CPU_HFILES): Add config/tc-nios2.h. -+ * Makefile.in: Regenerated. -+ * configure.tgt: Add case for nios2*-linux*. -+ * config/obj-elf.c: Conditionally include elf/nios2.h. -+ * config/tc-nios2.c: New file. -+ * config/tc-nios2.h: New file. -+ * doc/Makefile.am (CPU_DOCS): Add c-nios2.texi. -+ * doc/Makefile.in: Regenerated. -+ * doc/all.texi: Set NIOSII. -+ * doc/as.texinfo (Overview): Add Nios II options. -+ (Machine Dependencies): Include c-nios2.texi. -+ * doc/c-nios2.texi: New file. -+ * NEWS: Note Altera Nios II support. -+ -+2013-02-06 Alan Modra -+ -+ PR gas/14255 -+ * config/tc-avr.h (TC_VALIDATE_FIX): Mark symbol used by reloc. -+ Don't skip fixups with fx_subsy non-NULL. -+ * config/tc-avr.c (tc_gen_reloc): Don't specially handle fixups -+ with fx_subsy non-NULL. -+ -+2013-02-04 H.J. Lu -+ -+ * doc/c-metag.texi: Add "@c man" markers. -+ -+2013-02-04 Alan Modra -+ -+ * write.c (fixup_segment): Return void. Delete seg_reloc_count -+ related code. -+ (TC_ADJUST_RELOC_COUNT): Delete. -+ * config/tc-i960.h (TC_ADJUST_RELOC_COUNT): Delete. -+ -+2013-02-04 Alan Modra -+ -+ * po/POTFILES.in: Regenerate. -+ -+2013-01-30 Markos Chandras -+ -+ * config/tc-metag.c: Make SWAP instruction less permissive with -+ its operands. -+ -+2013-01-29 DJ Delorie -+ -+ * config/tc-rl78.c (rl78_cons_fix_new): Handle user-specified -+ relocs in .word/.etc statements. -+ -+2013-01-29 Roland McGrath -+ -+ * config/tc-arm.c (md_apply_fix): Use as_bad_where for "bad -+ immediate value for 8-bit offset" error so it shows line info. -+ -+2013-01-24 Joseph Myers -+ -+ * config/tc-ppc.c (md_assemble): Do not generate APUinfo sections -+ for 64-bit output. -+ -+2013-01-24 Nick Clifton -+ -+ * config/tc-v850.c: Add support for e3v5 architecture. -+ * doc/c-v850.texi: Mention new support. -+ -+2013-01-23 Nick Clifton -+ -+ PR gas/15039 -+ * config/tc-avr.c: Include dwarf2dbg.h. -+ -+2013-01-18 H.J. Lu -+ -+ * config/tc-i386.c (reloc): Support size relocation only for ELF. -+ (tc_i386_fix_adjustable): Likewise. -+ (lex_got): Likewise. -+ (tc_gen_reloc): Likewise. -+ -+2013-01-17 Yufeng Zhang -+ -+ * config/tc-aarch64.c (output_operand_error_record): Change to output -+ the out-of-range error message as value-expected message if there is -+ only one single value in the expected range. -+ (programmer_friendly_fixup): Remove the handling of 8-bit MOVI with -+ LSL #0 as a programmer-friendly feature. -+ -+2013-01-16 H.J. Lu -+ -+ * config/tc-i386.c (reloc): Support BFD_RELOC_SIZE32. -+ (tc_i386_fix_adjustable): Keep symbol for BFD_RELOC_32_SIZE and -+ BFD_RELOC_64_SIZE relocations. -+ (lex_got): Support "symbol@SIZE" and don't create GOT symbol -+ for it. -+ (tc_gen_reloc): Resolve BFD_RELOC_SIZE32 and BFD_RELOC_SIZE64 -+ relocations against local symbols. -+ -+2013-01-16 Alan Modra -+ -+ * config/tc-ppc.c (md_assemble ): Ignore line after -+ finding some sort of toc syntax error, and break to avoid -+ compiler uninit warning. -+ -+2013-01-15 H.J. Lu -+ -+ PR gas/15019 -+ * config/tc-i386.c (lex_got): Increment length by 1 if the -+ relocation token is removed. -+ -+2013-01-15 Nick Clifton -+ -+ * config/tc-v850.c (md_assemble): Allow signed values for -+ V850E_IMMEDIATE. -+ -+2013-01-11 Sean Keys -+ -+ * config/tc-xgate.c (md_begin): Fix mistake made when going from -+ git to cvs. -+ -+2013-01-10 Peter Bergner -+ -+ * doc/as.texinfo (Target PowerPC): Document -mpower8 and -mhtm. -+ * doc/c-ppc.texi (PowerPC-Opts): Likewise. -+ * config/tc-ppc.c (md_show_usage): Likewise. -+ (ppc_handle_align): Handle power8's group ending nop. -+ -+2013-01-10 Sean Keys -+ -+ * config/tc-xgate.c (md_begin): Fix the printing of opcodes so -+ that the assember exits after the opcodes have been printed. -+ -+2013-01-10 H.J. Lu -+ -+ * app.c: Remove trailing white spaces. -+ * as.c: Likewise. -+ * as.h: Likewise. -+ * cond.c: Likewise. -+ * dw2gencfi.c: Likewise. -+ * dwarf2dbg.h: Likewise. -+ * ecoff.c: Likewise. -+ * input-file.c: Likewise. -+ * itbl-lex.h: Likewise. -+ * output-file.c: Likewise. -+ * read.c: Likewise. -+ * sb.c: Likewise. -+ * subsegs.c: Likewise. -+ * symbols.c: Likewise. -+ * write.c: Likewise. -+ * config/tc-i386.c: Likewise. -+ * doc/Makefile.am: Likewise. -+ * doc/Makefile.in: Likewise. -+ * doc/c-aarch64.texi: Likewise. -+ * doc/c-alpha.texi: Likewise. -+ * doc/c-arc.texi: Likewise. -+ * doc/c-arm.texi: Likewise. -+ * doc/c-avr.texi: Likewise. -+ * doc/c-bfin.texi: Likewise. -+ * doc/c-cr16.texi: Likewise. -+ * doc/c-d10v.texi: Likewise. -+ * doc/c-d30v.texi: Likewise. -+ * doc/c-h8300.texi: Likewise. -+ * doc/c-hppa.texi: Likewise. -+ * doc/c-i370.texi: Likewise. -+ * doc/c-i386.texi: Likewise. -+ * doc/c-i860.texi: Likewise. -+ * doc/c-m32c.texi: Likewise. -+ * doc/c-m32r.texi: Likewise. -+ * doc/c-m68hc11.texi: Likewise. -+ * doc/c-m68k.texi: Likewise. -+ * doc/c-microblaze.texi: Likewise. -+ * doc/c-mips.texi: Likewise. -+ * doc/c-msp430.texi: Likewise. -+ * doc/c-mt.texi: Likewise. -+ * doc/c-s390.texi: Likewise. -+ * doc/c-score.texi: Likewise. -+ * doc/c-sh.texi: Likewise. -+ * doc/c-sh64.texi: Likewise. -+ * doc/c-tic54x.texi: Likewise. -+ * doc/c-tic6x.texi: Likewise. -+ * doc/c-v850.texi: Likewise. -+ * doc/c-xc16x.texi: Likewise. -+ * doc/c-xgate.texi: Likewise. -+ * doc/c-xtensa.texi: Likewise. -+ * doc/c-z80.texi: Likewise. -+ * doc/internals.texi: Likewise. -+ -+2013-01-10 Roland McGrath -+ -+ * hash.c (hash_new_sized): Make it global. -+ * hash.h: Declare it. -+ * macro.c (define_macro): Use hash_new_sized instead of hash_new, -+ pass a small size. -+ -+2013-01-10 Will Newton -+ -+ * Makefile.am: Add Meta. -+ * Makefile.in: Regenerate. -+ * config/tc-metag.c: New file. -+ * config/tc-metag.h: New file. -+ * configure.tgt: Add Meta. -+ * doc/Makefile.am: Add Meta. -+ * doc/Makefile.in: Regenerate. -+ * doc/all.texi: Add Meta. -+ * doc/as.texiinfo: Document Meta options. -+ * doc/c-metag.texi: New file. -+ -+2013-01-09 Steve Ellcey -+ -+ * config/tc-i386.c (md_begin): Remove 'internal Error' from as_fatal -+ calls. -+ * config/tc-mips.c (internalError): Remove, replace with abort. -+ -+2013-01-08 Yufeng Zhang -+ -+ * config/tc-aarch64.c (parse_operands): Change to compare the result -+ of function call 'parse_sys_reg' with 'PARSE_FAIL' instead of 'FALSE'. -+ -+2013-01-07 Nick Clifton -+ -+ PR gas/14887 -+ * config/tc-arm.c (skip_past_char): Skip whitespace before the -+ anticipated character. -+ * config/tc-arm.c (parse_address_main): Delete skip of whitespace -+ here as it is no longer needed. -+ -+2013-01-06 Andreas Schwab -+ -+ * doc/c-mips.texi (MIPS Opts): Fix use of @itemx. -+ * doc/c-score.texi (SCORE-Opts): Likewise. -+ * doc/c-tic54x.texi (TIC54X-Directives): Likewise. -+ -+2013-01-04 Juergen Urban -+ -+ * config/tc-mips.c: Add support for MIPS r5900. -+ Add M_LQ_AB and M_SQ_AB to support large values for instructions -+ lq and sq. -+ (can_swap_branch_p, get_append_method): Detect some conditional -+ short loops to fix a bug on the r5900 by NOP in the branch delay -+ slot. -+ (M_MUL): Support 3 operands in multu on r5900. -+ (M_TRUNCWS): Support trunc.w.s on r5900 in MIPS ISA I. -+ (s_mipsset): Force 32 bit floating point on r5900. -+ (mips_ip): Check parameter range of instructions mfps and mtps on -+ r5900. -+ * configure.in: Detect CPU type when target string contains r5900 -+ (e.g. mips64r5900el-linux-gnu). -+ -+2013-01-02 H.J. Lu -+ -+ * as.c (parse_args): Update copyright year to 2013. -+ -+2013-01-02 Yufeng Zhang -+ -+ * config/tc-aarch64.c (aarch64_cpus): Add entries for "cortex-a53" -+ and "cortex57". -+ -+2013-01-02 Nick Clifton -+ -+ PR gas/14987 -+ * config/tc-arm.c (parse_address_main): Skip whitespace before a -+ closing bracket. -+ -+For older changes see ChangeLog-2012 ++For older changes see ChangeLog-2013 + -+Copyright (C) 2013 Free Software Foundation, Inc. ++Copyright (C) 2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -354578,6 +355854,2117 @@ index 0000000..15e56a6 +fill-column: 74 +version-control: never +End: +diff --git a/gas/ChangeLog-2013 b/gas/ChangeLog-2013 +new file mode 100644 +index 0000000..8295850 +--- /dev/null ++++ b/gas/ChangeLog-2013 +@@ -0,0 +1,2105 @@ ++2013-12-20 Tristan Gingold ++ ++ * doc/c-arm.texi (ARM Directives): Remove duplicate .pad entry. ++ ++2013-12-18 Yufeng Zhang ++ ++ * config/tc-aarch64.c (md_assemble): Defer the feature checking until ++ do_encode () succeeds. ++ ++2013-12-18 Nick Clifton ++ ++ * config/tc-rx.c (rx_include): Rename 'eof' to 'last_char' in ++ order to avoid conflict with same named variable in MinGW system ++ header file. ++ ++2013-12-13 Nick Clifton ++ ++ * config/tc-msp430.c (mcu_types): Add some more 430X mcu names. ++ (OPTION_INTR_NOPS): Define. ++ (gen_interrupt_nops): Default to FALSE. ++ (md_parse_opton): Add support for OPTION_INTR_NOPS. ++ (md_longopts): Add -mn. ++ (md_show_usage): Add -mn. ++ (msp430_operands): Generate NOPs for all MCUs not just 430Xv2. ++ * doc/c-msp430.c: Document -mn. ++ ++2013-12-13 Kuan-Lin Chen ++ Wei-Cheng Wang ++ Hsiang-Kai Wang ++ Hui-Wen Ni ++ ++ * Makefile.am (TARGET_CPU_CFILES): Add config/tc-nds32.c. ++ (TARGET_CPU_HFILES): Add config/tc-nds32.h. ++ * Makefile.in: Regenerate. ++ * configure.in (nds32): Add nds32 target extension config support. ++ * configure.tgt : Add case for nds32-*-elf* and nds32-*-linux*. ++ * configure: Regenerate. ++ * config/tc-nds32.c: New file for nds32. ++ * config/tc-nds32.h: New file for nds32. ++ * doc/Makefile.am (CPU_DOCS): Add c-nds32.texi. ++ * doc/Makefile.in: Regenerate. ++ * doc/as.texinfo: Add nds32 options. ++ * doc/all.texi: Set NDS32. ++ * doc/c-nds32.texi: New file dor nds32 document. ++ * NEWS: Announce Andes nds32 support. ++ ++2013-12-10 Roland McGrath ++ ++ * Makefile.am (install-exec-bindir): Prefix libtool invocation ++ with $(INSTALL_PROGRAM_ENV). ++ (install-exec-tooldir): Likewise. ++ * Makefile.in: Regenerate. ++ ++2013-12-07 Mike Frysinger ++ ++ * config/bfin-aux.h: Remove +x file mode. ++ * config/tc-epiphany.c: Likewise. ++ * config/tc-epiphany.h: Likewise. ++ ++2013-12-03 Tristan Gingold ++ ++ * config/tc-i386-intel.c (i386_intel_simplify): Avoid arithmetic ++ overflow on pointers. ++ ++2013-11-19 Yufeng Zhang ++ ++ Revert ++ ++ 2013-11-19 Nick Clifton ++ ++ * config/tc-aarch64.c (parse_sys_reg): Do not issue error messages ++ for deprecated system registers when parsing pstate fields. ++ ++2013-11-19 Nick Clifton ++ ++ * config/tc-aarch64.c (parse_sys_reg): Do not issue error messages ++ for deprecated system registers when parsing pstate fields. ++ ++2013-11-19 Catherine Moore ++ ++ * config/tc-mips.c (mips_fix_pmc_rm7000): Declare. ++ (options): Add OPTION_FIX_PMC_RM7000 and OPTION_NO_FIX_PMC_RM7000. ++ (md_longopts): Add mfix-pmc-rm7000 and mno-fix-pmc-rm7000. ++ (INSN_DMULT): Define. ++ (INSN_DMULTU): Define. ++ (insns_between): Detect PMC RM7000 errata. ++ (md_parse_option): Supprt OPTION_FIX_PMC_RM7000 and ++ OPTION_NO_FIX_PMC_RM7000. ++ * doc/as.texinfo: Document new options. ++ * doc/c-mips.texi: Likewise. ++ ++2013-11-19 Alexey Makhalov ++ ++ PR gas/16109 ++ * app.c (do_scrub_chars): Only insert a newline character if ++ end-of-file has been reached. ++ ++2013-11-18 H.J. Lu ++ ++ * config/tc-i386.c (lex_got): Add a dummy "int bnd_prefix" ++ argument. ++ ++2013-11-18 Renlin Li ++ ++ * config/tc-arm.c (arm_archs): New armv7ve architecture option. ++ (arm_cpus): Replace ARM_ARCH_V7A_IDIV_MP_SEC_VIRT with ++ ARM_ARCH_V7VE for cortex-a7, cortex-a12 and cortex-a15. ++ (cpu_arch_ver): Likewise. ++ * doc/c-arm.texi: Document armv7ve. ++ ++2013-11-18 Zhenqiang Chen ++ ++ * config/tc-aarch64.c (parse_sys_reg): Support ++ S2____. ++ ++2013-11-18 Yufeng Zhang ++ ++ Revert ++ ++ 2013-11-15 Yufeng Zhang ++ ++ * config/tc-aarch64.c (set_other_error): New function. ++ (parse_sys_reg): Add new parameter 'sys_reg' and if non-NULL set ++ the variable to which it points with 'o'. ++ (parse_operands): Update; check for write to read-only system ++ registers or read from write-only ones. ++ ++2013-11-17 H.J. Lu ++ ++ * config/tc-i386.c (reloc): Add an argument, bnd_prefix, to ++ indicate if instruction has the BND prefix. Return ++ BFD_RELOC_X86_64_PC32_BND instead of BFD_RELOC_32_PCREL if ++ bnd_prefix isn't zero. ++ (output_branch): Pass BFD_RELOC_X86_64_PC32_BND to frag_var ++ if needed. ++ (output_jump): Update reloc call. ++ (output_interseg_jump): Likewise. ++ (output_disp): Likewise. ++ (output_imm): Likewise. ++ (x86_cons_fix_new): Likewise. ++ (lex_got): Add an argument, bnd_prefix, to indicate if ++ instruction has the BND prefix. Use BFD_RELOC_X86_64_PLT32_BND ++ if needed. ++ (x86_cons): Update lex_got call. ++ (i386_immediate): Likewise. ++ (i386_displacement): Likewise. ++ (md_apply_fix): Handle BFD_RELOC_X86_64_PC32_BND and ++ BFD_RELOC_X86_64_PLT32_BND. ++ (tc_gen_reloc): Likewise. ++ * config/tc-i386-intel.c (i386_operator): Update lex_got call. ++ ++2013-11-15 Yufeng Zhang ++ ++ * config/tc-aarch64.c (set_other_error): New function. ++ (parse_sys_reg): Add new parameter 'sys_reg' and if non-NULL set ++ the variable to which it points with 'o'. ++ (parse_operands): Update; check for write to read-only system ++ registers or read from write-only ones. ++ ++2013-11-15 Michael Zolotukhin ++ ++ * config/tc-i386.c (check_VecOperands): Reorder checks. ++ ++2013-11-11 Catherine Moore ++ ++ * config/mips/tc-mips.c (convert_reg_type): Use ++ INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY. ++ (reg_needs_delay): Likewise. ++ (insns_between): Likewise. ++ ++2013-11-08 Jan-Benedict Glaw ++ ++ * config/tc-aarch64.c (parse_sys_reg): Update to use aarch64_sys_reg; ++ call aarch64_sys_reg_deprecated_p and warn about the deprecated ++ system registers. ++ ++2013-11-05 Yufeng Zhang ++ ++ * config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_COND1. ++ ++2013-11-05 Will Newton ++ ++ PR gas/16103 ++ * config/tc-aarch64.c (parse_operands): Avoid trying to ++ parse a vector register as an immediate. ++ ++2013-11-04 Jan Beulich ++ ++ * config/tc-i386.c (check_long_reg): Correct comment indentation. ++ (check_qword_reg): Correct comment and its indentation. ++ (check_word_reg): Extend comment and correct its indentation. Also ++ check for 64-bit register. ++ ++2013-10-30 Ulrich Weigand ++ ++ * config/tc-ppc.c (md_pseudo_table): Add .localentry. ++ (ppc_elf_localentry): New function. ++ (ppc_force_relocation): Force relocs on all branches to localenty ++ symbols. ++ (ppc_fix_adjustable): Don't reduce such symbols to section+offset. ++ ++2013-10-30 Alan Modra ++ ++ * config/tc-ppc.c: Include elf/ppc64.h. ++ (ppc_abiversion): New variable. ++ (md_pseudo_table): Add .abiversion. ++ (ppc_elf_abiversion, ppc_elf_end): New functions. ++ * config/tc-ppc.h (md_end): Define. ++ ++2013-10-30 Alan Modra ++ ++ * config/tc-ppc.c (SEX16): Don't mask. ++ (REPORT_OVERFLOW_HI): Define as zero. ++ (ppc_elf_suffix): Support @high, @higha, @dtprel@high, @dtprel@higha, ++ @tprel@high, and @tprel@higha modifiers. ++ (md_assemble): Ignore X_unsigned when applying 16-bit insn fields. ++ Add (disabled) code to check @h and @ha reloc overflow for powerpc64. ++ Handle new relocs. ++ (md_apply_fix): Similarly. ++ ++2013-10-18 Chao-ying Fu ++ ++ * config/tc-mips.c (fpr_read_mask): Test MSA registers. ++ (fpr_write_mask): Test MSA registers. ++ (can_swap_branch_p): Check fpr write followed by fpr read. ++ ++2013-10-18 Nick Clifton ++ ++ * config/tc-tic6x.c (tic6x_parse_operand): Revert previous delta. ++ ++2013-10-14 Richard Sandiford ++ Chao-ying Fu ++ ++ * config/tc-mips.c (options): Add OPTION_MSA and OPTION_NO_MSA. ++ (md_longopts): Add mmsa and mno-msa. ++ (mips_ases): Add msa. ++ (RTYPE_MASK): Update. ++ (RTYPE_MSA): New define. ++ (OT_REG_ELEMENT): Replace with... ++ (OT_INTEGER_INDEX, OT_REG_INDEX): ...these new operand types. ++ (mips_operand_token): Replace reg_element with index. ++ (mips_parse_argument_token): Treat vector indices as separate tokens. ++ Handle register indices. ++ (md_begin): Add MSA register names. ++ (operand_reg_mask): Handle cases for OP_IMM_INDEX and OP_REG_INDEX. ++ (convert_reg_type): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL. ++ (match_mdmx_imm_reg_operand): Update accordingly. ++ (match_imm_index_operand): New function. ++ (match_reg_index_operand): New function. ++ (match_operand): Handle cases for OP_IMM_INDEX and OP_REG_INDEX. ++ (md_convert_frag): Convert bz.b/h/w/d, bnz.b/h/w/d, bz.v bnz.v. ++ (md_show_usage): Print -mmsa and -mno-msa. ++ * doc/as.texinfo: Document -mmsa and -mno-msa. ++ * doc/c-mips.texi: Document -mmsa and -mno-msa. ++ Document .set msa and .set nomsa. ++ ++2013-10-14 Nick Clifton ++ ++ * read.c (add_include_dir): Use xrealloc. ++ * config/tc-score.c (do_macro_bcmp): Initialise inst_main. ++ * config/tc-tic6x.c (tic6x_parse_operand): Initialise second_reg. ++ ++2013-10-13 Sandra Loosemore ++ ++ * config/tc-nios2.c (nios2_consume_arg): Make the "ba" warning ++ also test/refer to "sstatus". Reformat the warning message. ++ ++2013-10-10 Sean Keys ++ ++ * tc-xgate.c (xgate_find_match): Refactor opcode matching. ++ ++2013-10-10 Jan Beulich ++ ++ * tc-i386-intel.c (i386_intel_simplify_register): Suppress base/index ++ swapping for bndmk, bndldx, and bndstx. ++ ++2013-10-09 Nick Clifton ++ ++ PR gas/16025 ++ * config/tc-epiphany.c (md_convert_frag): Add missing break ++ statement. ++ ++ PR gas/16026 ++ * config/tc-mn10200.c (md_convert_frag): Add missing break ++ statement. ++ ++2013-10-08 Jan Beulich ++ ++ * tc-i386.c (check_word_reg): Remove misplaced "else". ++ (check_long_reg): Restore symmetry with check_word_reg. ++ ++2013-10-08 Jan Beulich ++ ++ * gas/config/tc-arm.c (do_t_push_pop): Honor inst.size_req. Simplify ++ LR/PC check. ++ ++2013-10-08 Nick Clifton ++ ++ * config/tc-msp430.c (msp430_operands): Accept ".a" as an alias ++ for "a". Issue error messages for unrecognised or corrrupt ++ size extensions. ++ ++2013-10-04 Kyrylo Tkachov ++ ++ * config/tc-arm.c (do_t_mvn_tst): Use narrow form for tst when ++ possible. ++ ++2013-09-30 Saravanan Ekanathan ++ ++ * config/tc-i386.c (cpu_arch): Add CPU_BDVER4_FLAGS. ++ * doc/c-i386.texi: Add -march=bdver4 option. ++ ++2013-09-20 Alan Modra ++ ++ * configure: Regenerate. ++ ++2013-09-18 Tristan Gingold ++ ++ * NEWS: Add marker for 2.24. ++ ++2013-09-18 Nick Clifton ++ ++ * config/tc-msp430.c (OPTION_MOVE_DATA): Define. ++ (move_data): New variable. ++ (md_parse_option): Parse -md. ++ (msp430_section): New function. Catch references to the .bss or ++ .data sections and generate a special symbol for use by the libcrt ++ library. ++ (md_pseudo_table): Intercept .section directives. ++ (md_longopt): Add -md ++ (md_show_usage): Likewise. ++ (msp430_operands): Generate a warning message if a NOP is inserted ++ into the instruction stream. ++ * doc/c-msp430.texi (node MSP430 Options): Document -md option. ++ ++2013-09-17 Doug Gilmore ++ ++ * config/tc-mips.c (mips_elf_final_processing): Set ++ EF_MIPS_FP64 for -mgp32 -mfp64, removing old FIXME. ++ ++2013-09-16 Will Newton ++ ++ * config/tc-arm.c (do_neon_ld_st_interleave): Add constraint ++ disallowing element size 64 with interleave other than 1. ++ ++2013-09-12 Chao-ying Fu ++ ++ * config/tc-mips.c (match_insn): Set error when $31 is used for ++ bltzal* and bgezal*. ++ ++2013-09-04 Tristan Gingold ++ ++ * config/tc-ppc.c (md_apply_fix): Handle defined after use toc ++ symbols. ++ ++2013-09-04 Roland McGrath ++ ++ PR gas/15914 ++ * config/tc-arm.c (T16_32_TAB): Add _udf. ++ (do_t_udf): New function. ++ (insns): Add "udf". ++ ++2013-08-23 Sandeep Kumar Singh ++ ++ * config/rx-parse.y: Rearrange the components of a bison grammar to issue ++ assembler errors at correct position. ++ ++2013-08-23 Yuri Chornoivan ++ ++ PR binutils/15834 ++ * config/tc-ia64.c: Fix typos. ++ * config/tc-sparc.c: Likewise. ++ * config/tc-z80.c: Likewise. ++ * doc/c-i386.texi: Likewise. ++ * doc/c-m32r.texi: Likewise. ++ ++2013-08-23 Will Newton ++ ++ * config/tc-arm.c: (do_neon_ldx_stx): Add extra constraints ++ for pre-indexed addressing modes. ++ ++2013-08-21 Alan Modra ++ ++ * symbols.c (fb_label_instance_inc, fb_label_instance): Properly ++ range check label number for use with fb_low_counter array. ++ ++2013-08-19 Richard Sandiford ++ ++ * config/tc-mips.c (mips_check_isa_supports_ase, reg_lookup) ++ (mips_parse_argument_token, validate_micromips_insn, md_begin) ++ (check_regno, match_float_constant, check_completed_insn, append_insn) ++ (match_insn, match_mips16_insn, match_insns, macro_start) ++ (macro_build_ldst_constoffset, load_register, macro, mips_ip) ++ (mips16_ip, mips_set_option_string, md_parse_option) ++ (mips_after_parse_args, mips_after_parse_args, md_pcrel_from) ++ (md_apply_fix, s_align, s_option, s_mipsset, s_tls_rel_directive) ++ (s_gpword, s_gpdword, s_ehword, s_nan, tc_gen_reloc, md_convert_frag) ++ (s_mips_end, s_mips_ent, s_mips_frame, s_mips_mask, mips_parse_cpu): ++ Start error messages with a lower-case letter. Do not end error ++ messages with a period. Wrap long messages to 80 character-lines. ++ Use "cannot" instead of "can't" and "can not". ++ ++2013-08-19 Richard Sandiford ++ ++ * config/tc-mips.c (imm_expr): Expand comment. ++ (set_at, macro, mips16_macro): Expect imm_expr to be O_constant ++ when populated. ++ ++2013-08-19 Richard Sandiford ++ ++ * config/tc-mips.c (imm2_expr): Delete. ++ (md_assemble, match_insn, imm2_expr.X_op, mips_ip): Update accordingly. ++ ++2013-08-19 Richard Sandiford ++ ++ * config/tc-mips.c (report_bad_range, report_bad_field): Delete. ++ (macro): Remove M_DEXT and M_DINS handling. ++ ++2013-08-19 Richard Sandiford ++ ++ * config/tc-mips.c (mips_arg_info): Replace allow_nonconst and ++ lax_max with lax_match. ++ (match_int_operand): Update accordingly. Don't report an error ++ for !lax_match-only cases. ++ (match_insn): Replace more_alts with lax_match and use it to ++ initialize the mips_arg_info field. Add a complete_p parameter. ++ Handle implicit VU0 suffixes here. ++ (match_invalid_for_isa, match_insns, match_mips16_insns): New ++ functions. ++ (mips_ip, mips16_ip): Use them. ++ ++2013-08-19 Richard Sandiford ++ ++ * config/tc-mips.c (match_expression): Report uses of registers here. ++ Add a "must be an immediate expression" error. Handle elided offsets ++ here rather than... ++ (match_int_operand): ...here. ++ ++2013-08-19 Richard Sandiford ++ ++ * config/tc-mips.c (mips_arg_info): Remove soft_match. ++ (match_out_of_range, match_not_constant): New functions. ++ (match_const_int): Remove fallback parameter and check for soft_match. ++ Use match_not_constant. ++ (match_mapped_int_operand, match_addiusp_operand) ++ (match_perf_reg_operand, match_save_restore_list_operand) ++ (match_mdmx_imm_reg_operand): Update accordingly. Use ++ match_out_of_range and set_insn_error* instead of as_bad. ++ (match_int_operand): Likewise. Use match_not_constant in the ++ !allows_nonconst case. ++ (match_float_constant): Report invalid float constants. ++ (match_insn, match_mips16_insn): Remove soft_match code. Rely on ++ match_float_constant to check for invalid constants. Fail the ++ match if match_const_int or match_float_constant return false. ++ (mips_ip): Update accordingly. ++ (mips16_ip): Likewise. Undo null termination of instruction name ++ once lookup is complete. ++ ++2013-08-19 Richard Sandiford ++ ++ * config/tc-mips.c (mips_insn_error_format): New enum. ++ (mips_insn_error): New struct. ++ (insn_error): Change to a mips_insn_error. ++ (clear_insn_error, set_insn_error_format, set_insn_error) ++ (set_insn_error_i, set_insn_error_ss, report_insn_error): New ++ functions. ++ (mips_parse_argument_token, md_assemble, match_insn) ++ (match_mips16_insn): Use them instead of manipulating insn_error ++ directly. ++ (mips_ip, mips16_ip): Likewise. Simplify control flow. ++ ++2013-08-19 Richard Sandiford ++ ++ * config/tc-mips.c (normalize_constant_expr): Move further up file. ++ (normalize_address_expr): Likewise. ++ (match_insn, match_mips16_insn): New functions, split out from... ++ (mips_ip, mips16_ip): ...here. ++ ++2013-08-19 Richard Sandiford ++ ++ * config/tc-mips.c (operand_reg_mask, match_operand): Handle ++ OP_OPTIONAL_REG. ++ (mips_ip, mips16_ip): Use mips_optional_operand_p to check ++ for optional operands. ++ ++2013-08-16 Alan Modra ++ ++ * config/tc-ppc.c (ppc_elf_cons): Allow @l and other reloc ++ modifiers generally. ++ ++2013-08-16 Alan Modra ++ ++ * config/tc-ppc.c (ppc_elf_lcomm): Use subsection 1. ++ ++2013-08-14 David Edelsohn ++ ++ * config/tc-ppc.c (ppc_comm): Accept optional fourth .lcomm ++ argument as alignment. ++ ++2013-08-09 Nick Clifton ++ ++ * config/tc-rl78.c (elf_flags): New variable. ++ (enum options): Add OPTION_G10. ++ (md_longopts): Add mg10. ++ (md_parse_option): Parse -mg10. ++ (rl78_elf_final_processing): New function. ++ * config/tc-rl78.c (tc_final_processing): Define. ++ * doc/c-rl78.texi: Document -mg10 option. ++ ++2013-08-06 Jürgen Urban ++ ++ * config/tc-mips.c (match_vu0_suffix_operand): Allow single-channel ++ suffixes to be elided too. ++ (mips_lookup_insn): Don't reject INSN2_VU0_CHANNEL_SUFFIX here. ++ (mips_ip): Assume .xyzw if no VU0 suffix is specified. Allow +N ++ to be omitted too. ++ ++2013-08-05 John Tytgat ++ ++ * po/POTFILES.in: Regenerate. ++ ++2013-08-05 Eric Botcazou ++ Konrad Eisele ++ ++ * config/tc-sparc.c (sparc_arch_types): Add leon. ++ (sparc_arch): Move sparc4 around and add leon. ++ (sparc_target_format): Document -Aleon. ++ * doc/c-sparc.texi: Likewise. ++ ++2013-08-05 Richard Sandiford ++ ++ * config/tc-mips.c (mips_lookup_insn): Make length and opend signed. ++ ++2013-08-04 Jürgen Urban ++ Richard Sandiford ++ ++ * config/tc-mips.c (MAX_OPERANDS): Bump to 6. ++ (RWARN): Bump to 0x8000000. ++ (RTYPE_VI, RTYPE_VF, RTYPE_R5900_I, RTYPE_R5900_Q, RTYPE_R5900_R) ++ (RTYPE_R5900_ACC): New register types. ++ (RTYPE_MASK): Include them. ++ (R5900_I_NAMES, R5900_Q_NAMES, R5900_R_NAMES, R5900_ACC_NAMES): New ++ macros. ++ (reg_names): Include them. ++ (mips_parse_register_1): New function, split out from... ++ (mips_parse_register): ...here. Add a channels_ptr parameter. ++ Look for VU0 channel suffixes when nonnull. ++ (reg_lookup): Update the call to mips_parse_register. ++ (mips_parse_vu0_channels): New function. ++ (OT_CHANNELS, OT_DOUBLE_CHAR): New mips_operand_token_types. ++ (mips_operand_token): Add a "channels" field to the union. ++ Extend the comment above "ch" to OT_DOUBLE_CHAR. ++ (mips_parse_base_start): Match -- and ++. Handle channel suffixes. ++ (mips_parse_argument_token): Handle channel suffixes here too. ++ (validate_mips_insn): Handle INSN2_VU0_CHANNEL_SUFFIX. ++ Ignore OP_VU0_MATCH_SUFFIX when calculating the used bits. ++ Handle '#' formats. ++ (md_begin): Register $vfN and $vfI registers. ++ (operand_reg_mask): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. ++ (convert_reg_type): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I, ++ OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC. ++ (match_vu0_suffix_operand): New function. ++ (match_operand): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. ++ (macro): Use "+7" rather than "E" for LDQ2 and STQ2. ++ (mips_lookup_insn): New function. ++ (mips_ip): Use it. Allow "+K" operands to be elided at the end ++ of an instruction. Handle '#' sequences. ++ ++2013-08-03 Richard Sandiford ++ ++ * config/tc-mips.c (macro, mips16_macro): Create an array of operand ++ values and use it instead of sreg, treg, xreg, etc. ++ ++2013-08-03 Richard Sandiford ++ ++ * config/tc-mips.c (match_int_operand): Use mips_int_operand_min ++ and mips_int_operand_max. ++ (mips16_immed_operand, mips16_immed_operands, MIPS16_NUM_IMMED): ++ Delete. ++ (mips16_immed_operand, mips16_immed_in_range_p): New functions. ++ (mips16_immed, mips16_extended_frag): Use them. Use mips_int_operand ++ instead of mips16_immed_operand. ++ ++2013-08-03 Richard Sandiford ++ ++ * config/tc-mips.c (mips16_macro): Don't use move_register. ++ (mips16_ip): Allow macros to use 'p'. ++ ++2013-08-01 Richard Sandiford ++ ++ * config/tc-mips.c (MAX_OPERANDS): New macro. ++ (mips_operand_array): New structure. ++ (mips_operands, mips16_operands, micromips_operands): New arrays. ++ (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map) ++ (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map) ++ (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map) ++ (micromips_to_32_reg_q_map): Delete. ++ (insn_operands, insn_opno, insn_extract_operand): New functions. ++ (validate_mips_insn): Take a mips_operand_array as argument and ++ use it to build up a list of operands. Extend to handle INSN_MACRO ++ and MIPS16. ++ (validate_mips16_insn): New function. ++ (validate_micromips_insn): Take a mips_operand_array as argument. ++ Handle INSN_MACRO. ++ (md_begin): Initialize mips_operands, mips16_operands and ++ micromips_operands. Call validate_mips_insn and ++ validate_micromips_insn for macro instructions too. ++ Call validate_mips16_insn for MIPS16 instructions. ++ (insn_read_mask, insn_write_mask, operand_reg_mask, insn_reg_mask): ++ New functions. ++ (gpr_read_mask, gpr_write_mask, fpr_read_mask, fpr_write_mask): Use ++ them. Handle INSN_UDI. ++ (get_append_method): Use gpr_read_mask. ++ ++2013-08-01 Richard Sandiford ++ ++ * config/tc-mips.c (compact_branch_p, uncond_branch_p): Use the same ++ flags for MIPS16 and non-MIPS16 instructions. ++ (gpr_mod_mask): Move the INSN2_MOD_SP case outside the micromips block. ++ (gpr_read_mask): Use INSN2_READ_GPR_31 for MIPS16 instructions too. ++ (gpr_write_mask): Remove MIPS16_INSN_WRITE_SP handling. ++ (can_swap_branch_p, get_append_method): Use the same flags for MIPS16 ++ and non-MIPS16 instructions. Fix formatting. ++ ++2013-08-01 Richard Sandiford ++ ++ * config/tc-mips.c (reg_needs_delay): Move later in file. ++ Use gpr_write_mask. ++ (insns_between): Use gpr_read_mask instead of EXTRACT_OPERAND. ++ ++2013-07-26 Sergey Guriev ++ Alexander Ivchenko ++ Maxim Kuznetsov ++ Sergey Lega ++ Anna Tikhonova ++ Ilya Tocar ++ Andrey Turetskiy ++ Ilya Verbin ++ Kirill Yukhin ++ Michael Zolotukhin ++ ++ * config/tc-i386-intel.c (O_zmmword_ptr): New. ++ (i386_types): Add zmmword. ++ (i386_intel_simplify_register): Allow regzmm. ++ (i386_intel_simplify): Handle zmmwords. ++ (i386_intel_operand): Handle RC/SAE, vector operations and ++ zmmwords. ++ * config/tc-i386.c (ZMMWORD_MNEM_SUFFIX): New. ++ (struct RC_Operation): New. ++ (struct Mask_Operation): New. ++ (struct Broadcast_Operation): New. ++ (vex_prefix): Size of bytes increased to 4 to support EVEX ++ encoding. ++ (enum i386_error): Add new error codes: unsupported_broadcast, ++ broadcast_not_on_src_operand, broadcast_needed, ++ unsupported_masking, mask_not_on_destination, no_default_mask, ++ unsupported_rc_sae, rc_sae_operand_not_last_imm, ++ invalid_register_operand, try_vector_disp8. ++ (struct _i386_insn): Add new fields vrex, need_vrex, mask, ++ rounding, broadcast, memshift. ++ (struct RC_name): New. ++ (RC_NamesTable): New. ++ (evexlig): New. ++ (evexwig): New. ++ (extra_symbol_chars): Add '{'. ++ (cpu_arch): Add AVX512F, AVX512CD, AVX512ER and AVX512PF. ++ (i386_operand_type): Add regzmm, regmask and vec_disp8. ++ (match_mem_size): Handle zmmwords. ++ (operand_type_match): Handle zmm-registers. ++ (mode_from_disp_size): Handle vec_disp8. ++ (fits_in_vec_disp8): New. ++ (md_begin): Handle {} properly. ++ (type_names): Add "rZMM", "Mask reg" and "Vector d8". ++ (build_vex_prefix): Handle vrex. ++ (build_evex_prefix): New. ++ (process_immext): Adjust to properly handle EVEX. ++ (md_assemble): Add EVEX encoding support. ++ (swap_2_operands): Correctly handle operands with masking, ++ broadcasting or RC/SAE. ++ (check_VecOperands): Support EVEX features. ++ (VEX_check_operands): Properly handle 16 upper [xyz]mm registers. ++ (match_template): Support regzmm and handle new error codes. ++ (process_suffix): Handle zmmwords and zmm-registers. ++ (check_byte_reg): Extend to zmm-registers. ++ (process_operands): Extend to zmm-registers. ++ (build_modrm_byte): Handle EVEX. ++ (output_insn): Adjust to properly handle EVEX case. ++ (disp_size): Handle vec_disp8. ++ (output_disp): Support compressed disp8*N evex feature. ++ (output_imm): Handle RC/SAE immediates properly. ++ (check_VecOperations): New. ++ (i386_immediate): Handle EVEX features. ++ (i386_index_check): Handle zmmwords and zmm-registers. ++ (RC_SAE_immediate): New. ++ (i386_att_operand): Handle EVEX features. ++ (parse_real_register): Add a check for ZMM/Mask registers. ++ (OPTION_MEVEXLIG): New. ++ (OPTION_MEVEXWIG): New. ++ (md_longopts): Add mevexlig and mevexwig. ++ (md_parse_option): Handle mevexlig and mevexwig options. ++ (md_show_usage): Add description for mevexlig and mevexwig. ++ * doc/c-i386.texi: Document avx512f/.avx512f, avx512cd/.avx512cd, ++ avx512er/.avx512er, avx512pf/.avx512pf, mevexlig and mevexwig. ++ ++2013-07-25 Michael Zolotukhin ++ ++ * config/tc-i386.c (cpu_arch): Add .sha. ++ * doc/c-i386.texi: Document sha/.sha. ++ ++2013-07-24 Anna Tikhonova ++ Kirill Yukhin ++ Michael Zolotukhin ++ ++ * config/tc-i386.c (BND_PREFIX): New. ++ (struct _i386_insn): Add new field bnd_prefix. ++ (add_bnd_prefix): New. ++ (cpu_arch): Add MPX. ++ (i386_operand_type): Add regbnd. ++ (md_assemble): Handle BND prefixes. ++ (parse_insn): Likewise. ++ (output_branch): Likewise. ++ (output_jump): Likewise. ++ (build_modrm_byte): Handle regbnd. ++ (OPTION_MADD_BND_PREFIX): New. ++ (md_longopts): Add entry for 'madd-bnd-prefix'. ++ (md_parse_option): Handle madd-bnd-prefix option. ++ (md_show_usage): Add description for madd-bnd-prefix ++ option. ++ * doc/c-i386.texi: Document mpx/.mpx and -madd-bnd-prefix. ++ ++2013-07-24 Tristan Gingold ++ ++ * config/tc-ppc.c (md_apply_fix): Adjust BFD_RELOC_PPC_B16 on ++ xcoff targets. ++ ++2013-07-24 Andreas Krebbel ++ ++ * config/tc-s390.c (s390_machine): Don't force the .machine ++ argument to lower case. ++ ++2013-07-22 Kyrylo Tkachov ++ ++ * config/tc-arm.c (s_arm_arch_extension): Improve error message ++ for invalid extension. ++ ++2013-07-19 Yufeng Zhang ++ ++ * config/tc-aarch64.c (enum aarch64_abi_type): New enumeration tag. ++ (AARCH64_ABI_LP64, AARCH64_ABI_ILP32): New enumerators. ++ (aarch64_abi): New variable. ++ (ilp32_p): Change to be a macro. ++ (aarch64_opts): Remove the support for option -milp32 and -mlp64. ++ (struct aarch64_option_abi_value_table): New struct. ++ (aarch64_abis): New table. ++ (aarch64_parse_abi): New function. ++ (aarch64_long_opts): Add entry for -mabi=. ++ * doc/as.texinfo (Target AArch64 options): Document -mabi. ++ * doc/c-aarch64.texi: Likewise. ++ ++2013-07-18 Jim Thomas ++ ++ * config/tc-i386-intel.c (i386_intel_operand): Fixed signed vs ++ unsigned comparison. ++ ++2013-07-18 Sandeep Kumar Singh ++ ++ * config/rx-defs.h: Add macros for RX100, RX200, RX600, and ++ RX610. ++ * config/rx-parse.y: (rx_check_float_support): Add function to ++ check floating point operation support for target RX100 and ++ RX200. ++ * config/tc-rx.c: Add CPU options RX100, RX200, RX600, and RX610. ++ * doc/c-rx.texi: Add -mcpu option to recognize macros for RX100, ++ RX200, RX600, and RX610 ++ ++2013-07-18 Senthil Kumar Selvaraj ++ ++ * config/tc-avr.c (md_show_usage): Add avrxmega2 to help text ++ ++2013-07-18 Vishnu K.S ++ ++ * config/tc-avr.c: Make ata6289's ISA to AVR_ISA_AVR4. ++ * doc/c-avr.texi: Likewise. ++ ++2013-07-15 Richard Sandiford ++ ++ * config/tc-mips.c (match_save_restore_list_operand): Avoid -Wformat ++ error with older GCCs. ++ (mips16_macro_build): Dereference args. ++ ++2013-07-14 Richard Sandiford ++ ++ * config/tc-mips.c (mips_prefer_vec_regno, mips_parse_register): ++ New functions, split out from... ++ (reg_lookup): ...here. Remove itbl support. ++ (reglist_lookup): Delete. ++ (mips_operand_token_type): New enum. ++ (mips_operand_token): New structure. ++ (mips_operand_tokens): New variable. ++ (mips_add_token, mips_parse_base_start, mips_parse_argument_token) ++ (mips_parse_arguments): New functions. ++ (md_begin): Initialize mips_operand_tokens. ++ (mips_arg_info): Add a token field. Remove optional_reg field. ++ (match_char, match_expression): New functions. ++ (match_const_int): Use match_expression. Remove "s" argument ++ and return a boolean result. Remove O_register handling. ++ (match_regno, match_reg, match_reg_range): New functions. ++ (match_int_operand, match_mapped_int_operand, match_msb_operand) ++ (match_reg_operand, match_reg_pair_operand, match_perf_reg_operand) ++ (match_addiusp_operand, match_clo_clz_dest_operand) ++ (match_lwm_swm_list_operand, match_entry_exit_operand) ++ (match_save_restore_list_operand, match_mdmx_imm_reg_operand) ++ (match_tied_reg_operand): Remove "s" argument and return a boolean ++ result. Match tokens rather than text. Update calls to ++ match_const_int. Rely on match_regno to call check_regno. ++ (match_pcrel_operand, match_pc_operand): Replace "s" argument with ++ "arg" argument. Return a boolean result. ++ (parse_float_constant): Replace with... ++ (match_float_constant): ...this new function. ++ (match_operand): Remove "s" argument and return a boolean result. ++ Update calls to subfunctions. ++ (mips_ip, mips16_ip): Call mips_parse_arguments. Use match routines ++ rather than string-parsing routines. Update handling of optional ++ registers for token scheme. ++ ++2013-07-14 Richard Sandiford ++ ++ * config/tc-mips.c (parse_float_constant): Split out from... ++ (mips_ip): ...here. ++ ++2013-07-14 Richard Sandiford ++ ++ * config/tc-mips.c (INSERT_BITS, INSERT_OPERAND, MIPS16_INSERT_OPERAND): ++ Delete. ++ ++2013-07-14 Richard Sandiford ++ ++ * config/tc-mips.c (mips32_to_16_reg_map): Delete. ++ (match_entry_exit_operand): New function. ++ (match_save_restore_list_operand): Likewise. ++ (match_operand): Use them. ++ (check_absolute_expr): Delete. ++ (mips16_ip): Rewrite main parsing loop to use mips_operands. ++ ++2013-07-14 Richard Sandiford ++ ++ * config/tc-mips.c: Enable functions commented out in previous patch. ++ (SKIP_SPACE_TABS): Move further up file. ++ (mips32_to_micromips_reg_b_map, mips32_to_micromips_reg_c_map) ++ (mips32_to_micromips_reg_d_map, mips32_to_micromips_reg_e_map) ++ (ips32_to_micromips_reg_f_map, mips32_to_micromips_reg_g_map) ++ (mips32_to_micromips_reg_l_map, mips32_to_micromips_reg_m_map) ++ (mips32_to_micromips_reg_q_map, mips32_to_micromips_reg_n_map) ++ (micromips_imm_b_map, micromips_imm_c_map): Delete. ++ (mips_lookup_reg_pair): Delete. ++ (macro): Use report_bad_range and report_bad_field. ++ (mips_immed, expr_const_in_range): Delete. ++ (mips_ip): Rewrite main parsing loop to use new functions. ++ ++2013-07-14 Richard Sandiford ++ ++ * config/tc-mips.c (mips_oddfpreg_ok): Move further up file. ++ Change return type to bfd_boolean. ++ (report_bad_range, report_bad_field): New functions. ++ (mips_arg_info): New structure. ++ (match_const_int, convert_reg_type, check_regno, match_int_operand) ++ (match_mapped_int_operand, match_msb_operand, match_reg_operand) ++ (match_reg_pair_operand, match_pcrel_operand, match_perf_reg_operand) ++ (match_addiusp_operand, match_clo_clz_dest_operand) ++ (match_lwm_swm_list_operand, match_mdmx_imm_reg_operand) ++ (match_pc_operand, match_tied_reg_operand, match_operand) ++ (check_completed_insn): New functions, commented out for now. ++ ++2013-07-14 Richard Sandiford ++ ++ * config/tc-mips.c (insn_insert_operand): New function. ++ (macro_build, mips16_macro_build): Put null character check ++ in the for loop and convert continues to breaks. Use operand ++ structures to handle constant operands. ++ ++2013-07-14 Richard Sandiford ++ ++ * config/tc-mips.c (validate_mips_insn): Move further up file. ++ Add insn_bits and decode_operand arguments. Use the mips_operand ++ fields to work out which bits an operand occupies. Detect double ++ definitions. ++ (validate_micromips_insn): Move further up file. Call into ++ validate_mips_insn. ++ ++2013-07-14 Richard Sandiford ++ ++ * config/tc-mips.c (mips16_macro_build): Remove 'Y' case. ++ ++2013-07-14 Richard Sandiford ++ ++ * config/tc-mips.c (macro_build): Take an int for "C", "k", "\\" ++ and "~". ++ (macro): Update accordingly. ++ ++2013-07-14 Richard Sandiford ++ ++ * config/tc-mips.c (imm_expr, imm2_expr, offset_expr): Tweak commentary. ++ (imm_reloc): Delete. ++ (md_assemble): Remove imm_reloc handling. ++ (mips_ip): Update commentary. Use offset_expr and offset_reloc ++ rather than imm_expr and imm_reloc for 'i', 'j' and 'u'. ++ Use a temporary array rather than imm_reloc when parsing ++ constant expressions. Remove imm_reloc initialization. ++ (mips16_ip): Update commentary. Use offset_expr and offset_reloc ++ for the relaxable field. Use a relax_char variable to track the ++ type of this field. Remove imm_reloc initialization. ++ ++2013-07-14 Richard Sandiford ++ ++ * config/tc-mips.c (mips16_ip): Handle "I". ++ ++2013-07-12 Maciej W. Rozycki ++ ++ * config/tc-mips.c (mips_flag_nan2008): New variable. ++ (options): Add OPTION_NAN enum value. ++ (md_longopts): Handle it. ++ (md_parse_option): Likewise. ++ (s_nan): New function. ++ (mips_elf_final_processing): Handle EF_MIPS_NAN2008. ++ (md_show_usage): Add -mnan. ++ ++ * doc/as.texinfo (Overview): Add -mnan. ++ * doc/c-mips.texi (MIPS Opts): Document -mnan. ++ (MIPS NaN Encodings): New node. Document .nan directive. ++ (MIPS-Dependent): List the new node. ++ ++2013-07-09 Tristan Gingold ++ ++ * configure.com: Define HAVE_SYS_TYPES_H and HAVE_UNISTD_H ++ ++2013-07-08 Richard Sandiford ++ ++ * config/tc-mips.c (mips_ip): Unconditionally parse an expression ++ for 'A' and assume that the constant has been elided if the result ++ is an O_register. ++ ++2013-07-07 Richard Sandiford ++ ++ * config/tc-mips.c (gprel16_reloc_p): New function. ++ (macro_read_relocs): Assume BFD_RELOC_LO16 if all relocs are ++ BFD_RELOC_UNUSED. ++ (offset_high_part, small_offset_p): New functions. ++ (nacro): Use them. Remove *_OB and *_DOB cases. For single- ++ register load and store macros, handle the 16-bit offset case first. ++ If a 16-bit offset is not suitable for the instruction we're ++ generating, load it into the temporary register using ++ ADDRESS_ADDI_INSN. Make the M_LI_DD code fall through into the ++ M_L_DAB code once the address has been constructed. For double load ++ and store macros, again handle the 16-bit offset case first. ++ If the second register cannot be accessed from the same high ++ part as the first, load it into AT using ADDRESS_ADDI_INSN. ++ Fix the handling of LD in cases where the first register is the ++ same as the base. Also handle the case where the offset is ++ not 16 bits and the second register cannot be accessed from the ++ same high part as the first. For unaligned loads and stores, ++ fuse the offbits == 12 and old "ab" handling. Apply this handling ++ whenever the second offset needs a different high part from the first. ++ Construct the offset using ADDRESS_ADDI_INSN where possible, ++ for offbits == 16 as well as offbits == 12. Use offset_reloc ++ when constructing the individual loads and stores. ++ (mips_ip): Set up imm_expr, imm2_expr, offset_expr, imm_reloc ++ and offset_reloc before matching against a particular opcode. ++ Handle elided 'A' constants. Allow 'A' constants to use ++ relocation operators. ++ ++2013-07-07 Richard Sandiford ++ ++ * config/tc-mips.c (validate_mips_insn): Remove "[" and "]" handling. ++ (mips_ip): Likewise. Do not set is_mdmx for INSN_5400 instructions. ++ Check constraints on the VR5400 RZU.OB, SLL.OB and SRL.OB instructions. ++ ++2013-07-07 Richard Sandiford ++ ++ * config/tc-mips.c (mips_ip): Preserve the real bit number for "+p". ++ Require the msb to be <= 31 for "+s". Check that the size is <= 31 ++ for both "+s" and "+S". ++ ++2013-07-07 Richard Sandiford ++ ++ * config/tc-mips.c (validate_mips_insn, validate_micromips_insn): ++ (mips_ip, mips16_ip): Handle "+i". ++ ++2013-07-07 Richard Sandiford ++ ++ * config/tc-mips.c (mips32_to_micromips_reg_h_map): Delete. ++ (micromips_to_32_reg_h_map): Rename to... ++ (micromips_to_32_reg_h_map1): ...this. ++ (micromips_to_32_reg_i_map): Rename to... ++ (micromips_to_32_reg_h_map2): ...this. ++ (mips_lookup_reg_pair): New function. ++ (gpr_write_mask, macro): Adjust after above renaming. ++ (validate_micromips_insn): Remove "mi" handling. ++ (mips_ip): Likewise. Parse both registers in a pair for "mh". ++ ++2013-07-07 Richard Sandiford ++ ++ * config/tc-mips.c (validate_mips_insn, validate_micromips_insn) ++ (mips_ip): Remove "+D" and "+T" handling. ++ ++2013-07-05 Andreas Krebbel ++ ++ * config/tc-s390.c (md_gather_operands, md_apply_fix): Support new ++ relocs. ++ ++2013-07-03 Marcus Shawcroft ++ ++ * config/tc-aarch64.c (reloc_table): Merge got_prel19 into got. ++ ++2013-07-02 Marcus Shawcroft ++ ++ * config/tc-aarch64.c (md_apply_fix): Reorder case values. ++ (aarch64_force_relocation): Likewise. ++ ++2013-07-02 Alan Modra ++ ++ * config/tc-ppc.c (ppc_elf_adjust_symtab): Don't make .TOC. weak. ++ ++2013-06-26 Maciej W. Rozycki ++ ++ * doc/as.texinfo (Overview): Remove @samp from MIPS ISA names. ++ * doc/c-mips.texi (MIPS Options): Remove @sc from MIPS ISA names. ++ Replace @sc{mips16} with literal `MIPS16'. ++ (MIPS ISA): Replace @sc{mips3} with literal `MIPS III'. ++ ++2013-06-26 Yufeng Zhang ++ ++ * config/tc-aarch64.c (reloc_table): Replace ++ BFD_RELOC_AARCH64_LD64_GOT_LO12_NC with ++ BFD_RELOC_AARCH64_LD_GOT_LO12_NC; likewise to ++ BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC and ++ BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC. ++ (md_apply_fix): Handle BFD_RELOC_AARCH64_LD_GOT_LO12_NC, ++ BFD_RELOC_AARCH64_LD32_GOT_LO12_NC, ++ BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC, ++ BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC, ++ BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC and ++ BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC. ++ (aarch64_force_relocation): Likewise. ++ ++2013-06-26 Yufeng Zhang ++ ++ * config/tc-aarch64.c (ilp32_p): New static variable. ++ (elf64_aarch64_target_format): Return the target according to the ++ value of 'ilp32_p'. ++ (md_begin): Determine 'mach' according to the value of 'ilp32_p'. ++ (aarch64_opts): Add support for options '-milp32' and '-mlp64'. ++ (aarch64_dwarf2_addr_size): New function. ++ * config/tc-aarch64.h (aarch64_dwarf2_addr_size): New declaration. ++ (DWARF2_ADDR_SIZE): New define. ++ ++2013-06-26 Richard Sandiford ++ ++ * doc/c-mips.texi: Use ISA instead of @sc{isa}. ++ ++2013-06-26 Richard Sandiford ++ ++ * config/tc-mips.c (validate_mips_insn): Use STYPE rather than SHAMT. ++ ++2013-06-25 Maciej W. Rozycki ++ ++ * config/tc-mips.c (mips_set_options): Add insn32 member. ++ (mips_opts): Initialize it. ++ (NOP_INSN, NOP_INSN_SIZE): Handle insn32 mode. ++ (options): Add OPTION_INSN32 and OPTION_NO_INSN32 enum values. ++ (md_longopts): Add "minsn32" and "mno-insn32" options. ++ (is_size_valid): Handle insn32 mode. ++ (md_assemble): Pass instruction string down to macro. ++ (brk_fmt): Add second dimension and insn32 mode initializers. ++ (mfhl_fmt): Likewise. ++ (BRK_FMT, MFHL_FMT): Handle insn32 mode. ++ (macro_build) <'c'>: Handle microMIPS 32-bit BREAK encoding. ++ (macro_build_jalr, move_register): Handle insn32 mode. ++ (macro_build_branch_rs): Likewise. ++ (macro): Handle insn32 mode. ++ , , : New cases. ++ (mips_ip): Handle insn32 mode. ++ (md_parse_option): Handle OPTION_INSN32 and OPTION_NO_INSN32. ++ (s_mipsset): Handle "insn32" and "noinsn32" pseudo-ops. ++ (mips_handle_align): Handle insn32 mode. ++ (md_show_usage): Add -minsn32 and -mno-insn32. ++ ++ * doc/as.texinfo (Target MIPS options): Add -minsn32 and ++ -mno-insn32 options. ++ (-minsn32, -mno-insn32): New options. ++ * doc/c-mips.texi (MIPS Opts): Add -minsn32 and -mno-insn32 ++ options. ++ (MIPS assembly options): New node. Document .set insn32 and ++ .set noinsn32. ++ (MIPS-Dependent): List the new node. ++ ++2013-06-25 Nick Clifton ++ ++ * config/tc-msp430.c (msp430_srcoperand): Do not allow the use of ++ the PC in indirect addressing on 430xv2 parts. ++ (msp430_operands): Add version test to hardware bug encoding ++ restrictions. ++ ++2013-06-24 Roland McGrath ++ ++ * config/tc-arm.c (parse_reg_list): Use skip_past_char for '}', ++ so it skips whitespace before it. ++ (s_arm_unwind_save_mmxwr, s_arm_unwind_save_mmxwcg): Likewise. ++ ++ * config/tc-arm.c (arm_symbol_chars): Include '{' and '}'. ++ (arm_reg_parse_multi): Skip whitespace first. ++ (parse_reg_list): Likewise. ++ (parse_vfp_reg_list): Likewise. ++ (s_arm_unwind_save_mmxwcg): Likewise. ++ ++2013-06-24 Nick Clifton ++ ++ PR gas/15623 ++ * config/tc-arm.c (do_t_smc): Mark as ending an IT block. ++ ++2013-06-23 Richard Sandiford ++ ++ * config/tc-mips.c (mips_ip): Fix swapped bit numbers in comments. ++ ++2013-06-23 Richard Sandiford ++ ++ * config/tc-mips.c: Assert that offsetT and valueT are at least ++ 8 bytes in size. ++ (GPR_SMIN, GPR_SMAX): New macros. ++ (macro, mips_ip): Remove code for 4-byte valueT and offsetT. ++ ++2013-06-22 Richard Sandiford ++ ++ * config/tc-mips.c: Remove OBJ_ELF, OBJ_MAYBE_ELF and IS_ELF ++ conditions. Remove any code deselected by them. ++ (s_mips_frame, s_mips_mask): Handle ECOFF_DEBUGGING case first. ++ ++2013-06-22 Richard Sandiford ++ ++ * NEWS: Note removal of ECOFF support. ++ * doc/as.texinfo (--emulation): Update for the removal of MIPS ECOFF. ++ * Makefile.am (TARG_ENV_HFILES): Remove config/te-lnews.h. ++ (MULTI_CFILES): Remove config/e-mipsecoff.c. ++ * Makefile.in: Regenerate. ++ * configure.in: Remove MIPS ECOFF references. ++ (mips-sony-bsd*, mips-*-bsd*, mips-*-lnews*-ecoff, mips-*-*-ecoff): ++ Delete cases. ++ (mips-*-irix5*-*, mips*-*-linux*-*, mips*-*-freebsd*) ++ (mips*-*-kfreebsd*-gnu, mips-*-*-elf): Fold into... ++ (mips-*-*): ...this single case. ++ (mipsbecoff, mipslecoff, mipsecoff): Remove emulations. Expect ++ MIPS emulations to be e-mipself*. ++ * configure: Regenerate. ++ * configure.tgt (mips-sony-bsd*, mips-*-ultrix*, mips-*-osf*) ++ (mips-*-ecoff*, mips-*-pe*, mips-*-irix*, ips-*-lnews*, mips-*-riscos*) ++ (mips-*-sysv*): Remove coff and ecoff cases. ++ * as.c (mipsbecoff, mipslecoff, mipsecoff): Remove. ++ * ecoff.c: Remove reference to MIPS ECOFF. ++ * config/e-mipsecoff.c, config/te-lnews.h: Delete files. ++ * config/tc-mips.c (ECOFF_LITTLE_FORMAT): Delete. ++ (RDATA_SECTION_NAME, mips_target_form): Remove COFF and ECOFF cases. ++ (mips_hi_fixup): Tweak comment. ++ (append_insn): Require a howto. ++ (mips_after_parse_args): Remove OBJ_MAYBE_ECOFF code. ++ ++2013-06-22 Richard Sandiford ++ ++ * doc/as.texinfo: Use MIPS rather than @sc{mips} throughout. ++ Use "CPU" instead of "cpu". ++ * doc/c-mips.texi: Likewise. ++ (MIPS Opts): Rename to MIPS Options. ++ (MIPS option stack): Rename to MIPS Option Stack. ++ (MIPS ASE instruction generation overrides): Rename to ++ MIPS ASE Instruction Generation Overrides (for now). ++ (MIPS floating-point): Rename to MIPS Floating-Point. ++ ++2013-06-22 Richard Sandiford ++ ++ * doc/c-mips.texi (MIPS Macros): New section. ++ (MIPS Object): Replace with... ++ (MIPS Small Data): ...this new section. ++ ++2013-06-22 Richard Sandiford ++ ++ * doc/c-mips.texi (MIPS symbol sizes): Move section further up file. ++ Capitalize name. Use @kindex instead of @cindex for .set entries. ++ ++2013-06-22 Richard Sandiford ++ ++ * doc/c-mips.texi (MIPS Stabs): Remove section. ++ ++2013-06-20 Richard Sandiford ++ ++ * config/tc-mips.c (ISA_SUPPORTS_SMARTMIPS, ISA_SUPPORTS_DSP_ASE) ++ (ISA_SUPPORTS_DSP64_ASE, ISA_SUPPORTS_DSPR2_ASE, ISA_SUPPORTS_EVA_ASE) ++ (ISA_SUPPORTS_MT_ASE, ISA_SUPPORTS_MCU_ASE, ISA_SUPPORTS_VIRT_ASE) ++ (ISA_SUPPORTS_VIRT64_ASE): Delete. ++ (mips_ase): New structure. ++ (mips_ases): New table. ++ (FP64_ASES): New macro. ++ (mips_ase_groups): New array. ++ (mips_isa_rev, mips_ase_mask, mips_check_isa_supports_ase) ++ (mips_check_isa_supports_ases, mips_set_ase, mips_lookup_ase): New ++ functions. ++ (is_opcode_valid): Use mips_ases to get the 64-bit ASE flags. ++ (md_parse_option): Use mips_ases and mips_set_ase instead of ++ separate case statements for each ASE option. ++ (mips_after_parse_args): Use FP64_ASES. Use ++ mips_check_isa_supports_ases to check the ASEs against ++ other options. ++ (s_mipsset): Use mips_ases and mips_set_ase instead of ++ separate if statements for each ASE option. Use ++ mips_check_isa_supports_ases, even when a non-ASE option ++ is specified. ++ ++2013-06-19 Greta Yorsh ++ ++ * config/tc-arm.c (arm_cpus): Add support for Cortex-A12. ++ ++2013-06-18 Richard Sandiford ++ ++ * config/tc-mips.c (md_shortopts, options, md_longopts) ++ (md_longopts_size): Move earlier in file. ++ ++2013-06-18 Richard Sandiford ++ ++ * config/tc-mips.c (mips_set_options): Replace separate "ase_*" fields ++ with a single "ase" bitmask. ++ (mips_opts): Update accordingly. ++ (file_ase, file_ase_explicit): New variables. ++ (file_ase_mips3d, file_ase_mdmx, file_ase_smartmips, file_ase_dsp) ++ (file_ase_dspr2, file_ase_eva, file_ase_mt, file_ase_virt): Delete. ++ (ISA_HAS_ROR): Adjust for mips_set_options change. ++ (is_opcode_valid): Take the base ase mask directly from mips_opts. ++ (mips_ip): Adjust for mips_set_options change. ++ (md_parse_option): Likewise. Update file_ase_explicit. ++ (mips_after_parse_args): Adjust for mips_set_options change. ++ Use bitmask operations to select the default ASEs. Set file_ase ++ rather than individual per-ASE variables. ++ (s_mipsset): Adjust for mips_set_options change. ++ (mips_elf_final_processing): Test file_ase rather than ++ file_ase_mdmx. Remove commented-out code. ++ ++2013-06-18 Richard Sandiford ++ ++ * config/tc-mips.c (mips_cpu_info): Add an "ase" field. ++ (MIPS_CPU_ASE_SMARTMIPS, MIPS_CPU_ASE_DSP, MIPS_CPU_ASE_MT) ++ (MIPS_CPU_ASE_MIPS3D, MIPS_CPU_ASE_MDMX, MIPS_CPU_ASE_DSPR2) ++ (MIPS_CPU_ASE_MCU, MIPS_CPU_ASE_VIRT, MIPS_CPU_ASE_EVA): Delete. ++ (mips_after_parse_args): Use the new "ase" field to choose ++ the default ASEs. ++ (mips_cpu_info_table): Move ASEs from the "flags" field to the ++ "ase" field. ++ ++2013-06-18 Richard Earnshaw ++ ++ * config/tc-arm.c (symbol_preemptible): New function. ++ (relax_branch): Use it. ++ ++2013-06-17 Catherine Moore ++ Maciej W. Rozycki ++ Chao-Ying Fu ++ ++ * config/tc-mips.c (mips_set_options): Add ase_eva. ++ (mips_set_options mips_opts): Add ase_eva. ++ (file_ase_eva): Declare. ++ (ISA_SUPPORTS_EVA_ASE): Define. ++ (IS_SEXT_9BIT_NUM): Define. ++ (MIPS_CPU_ASE_EVA): Define. ++ (is_opcode_valid): Add support for ase_eva. ++ (macro_build): Likewise. ++ (macro): Likewise. ++ (validate_mips_insn): Likewise. ++ (validate_micromips_insn): Likewise. ++ (mips_ip): Likewise. ++ (options): Add OPTION_EVA and OPTION_NO_EVA. ++ (md_longopts): Add -meva and -mno-eva. ++ (md_parse_option): Process new options. ++ (mips_after_parse_args): Check for valid EVA combinations. ++ (s_mipsset): Likewise. ++ ++2013-06-14 Richard Sandiford ++ ++ * dwarf2dbg.h (dwarf2_move_insn): Declare. ++ * dwarf2dbg.c (line_subseg): Add pmove_tail. ++ (get_line_subseg): Add create_p argument. Initialize pmove_tail. ++ (dwarf2_gen_line_info_1): Update call accordingly. ++ (dwarf2_move_insn): New function. ++ * config/tc-mips.c (append_insn): Use dwarf2_move_insn. ++ ++2013-06-14 Richard Sandiford ++ ++ Revert: ++ ++ 2011-09-05 Richard Sandiford ++ ++ PR gas/13024 ++ * dwarf2dbg.c (pending_lines, pending_lines_tail): New variables. ++ (dwarf2_gen_line_info_1): Delete. ++ (dwarf2_push_line, dwarf2_flush_pending_lines): New functions. ++ (dwarf2_gen_line_info, dwarf2_emit_label): Use them. ++ (dwarf2_consume_line_info): Call dwarf2_flush_pending_lines. ++ (dwarf2_directive_loc): Push previous .locs instead of generating ++ them immediately. ++ ++2013-06-13 Chao-ying Fu ++ ++ * config/tc-mips.c (ISA_SUPPORTS_VIRT_ASE): Support micromips. ++ (ISA_SUPPORTS_VIRT64_ASE): Support 64-bit micromips. ++ ++2013-06-13 Nick Clifton ++ ++ PR gas/15602 ++ * config/tc-m68k.h (TC_CHECK_ADJUSTED_BROKEN_DOT_WORD): Define. ++ * config/tc-m68k.c (tc_m68k_check_adjusted_broken_word): New ++ function. Generates an error if the adjusted offset is out of a ++ 16-bit range. ++ ++2013-06-12 Sandra Loosemore ++ ++ * config/tc-nios2.c (md_apply_fix): Mask constant ++ BFD_RELOC_NIOS2_HIADJ16 value to 16 bits. ++ ++2013-06-10 Maciej W. Rozycki ++ ++ * config/tc-mips.c (append_insn): Don't do branch relaxation for ++ MIPS-3D instructions either. ++ (md_convert_frag): Update the COPx branch mask accordingly. ++ ++ * config/tc-mips.c (md_show_usage): Document --[no-]relax-branch ++ option. ++ * doc/as.texinfo (Overview): Add --relax-branch and ++ --no-relax-branch. ++ * doc/c-mips.texi (MIPS Opts): Document --relax-branch and ++ --no-relax-branch. ++ ++2013-06-09 Sandra Loosemore ++ ++ * config/tc-nios2.c (nios2_parse_args): Allow trap argument to ++ omitted. ++ ++2013-06-08 Catherine Moore ++ ++ * config/tc-mips.c (is_opcode_valid): Build ASE mask. ++ (is_opcode_valid_16): Pass ase value to opcode_is_member. ++ (append_insn): Change INSN_xxxx to ASE_xxxx. ++ ++2013-06-01 George Thomas ++ ++ * gas/config/tc-avr.c: Change ISA for devices with USB support to ++ AVR_ISA_XMEGAU ++ ++2013-05-31 H.J. Lu ++ ++ * config/tc-i386.c (md_begin): Don't align text/data/bss sections ++ for ELF. ++ ++2013-05-31 Paul Brook ++ ++ * config/tc-mips.c (s_ehword): New. ++ ++2013-05-30 Paul Brook ++ ++ * config/tc-mips.c (md_apply_fix): Support BFD_RELOC_MIPS_EH. ++ ++2013-05-29 Maciej W. Rozycki ++ ++ * write.c (resolve_reloc_expr_symbols): On REL targets don't ++ convert relocs who have no relocatable field either. Rephrase ++ the conditional so that the PC-relative check is only applied ++ for REL targets. ++ ++2013-05-28 Chao-ying Fu ++ ++ * config/tc-mips.c (macro) : Don't use $zero for address ++ calculation. ++ ++2013-05-28 Yufeng Zhang ++ ++ * config/tc-aarch64.c (reloc_table): Update to use ++ BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21 instead of ++ BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE. ++ (md_apply_fix): Likewise. ++ (aarch64_force_relocation): Likewise. ++ ++2013-05-28 Kyrylo Tkachov ++ ++ * config/tc-arm.c (it_fsm_post_encode): Improve ++ warning messages about deprecated IT block formats. ++ ++2013-05-28 Marcus Shawcroft ++ ++ * config/tc-aarch64.c (md_apply_fix): Move value range checking ++ inside fx_done condition. ++ ++2013-05-22 Jürgen Urban ++ ++ * config/tc-mips.c (macro): Handle M_LQC2_AB and M_SQC2_AB. ++ ++2013-05-20 Peter Bergner ++ ++ * config/tc-ppc.c (ppc_setup_opcodes): Use new_seg to fix error ++ and clean up warning when using PRINT_OPCODE_TABLE. ++ ++2013-05-20 Alan Modra ++ ++ * config/tc-ppc.c (md_apply_fix): Hoist code common to insn ++ and data fixups performing shift/high adjust/sign extension on ++ fieldval. Sink fx_pcrel handling and checks. Use fixP->fx_size ++ when writing data fixups rather than recalculating size. ++ ++2013-05-16 Jan-Benedict Glaw ++ ++ * doc/c-msp430.texi: Fix typo. ++ ++2013-05-16 Tristan Gingold ++ ++ * config/tc-ppc.c (ppc_is_toc_sym): Symbols of class XMC_TC ++ are also TOC symbols. ++ ++2013-05-16 Nick Clifton ++ ++ * config/tc-msp430.c: Make -mmcu recognise more part numbers. ++ Add -mcpu command to specify core type. ++ * doc/c-msp430.texi: Update documentation. ++ ++2013-05-09 Andrew Pinski ++ ++ * config/tc-mips.c (struct mips_set_options): New ase_virt field. ++ (mips_opts): Update for the new field. ++ (file_ase_virt): New variable. ++ (ISA_SUPPORTS_VIRT_ASE): New macro. ++ (ISA_SUPPORTS_VIRT64_ASE): New macro. ++ (MIPS_CPU_ASE_VIRT): New define. ++ (is_opcode_valid): Handle ase_virt. ++ (macro_build): Handle "+J". ++ (validate_mips_insn): Likewise. ++ (mips_ip): Likewise. ++ (enum options): Add OPTION_VIRT and OPTION_NO_VIRT. ++ (md_longopts): Add mvirt and mnovirt ++ (md_parse_option): Handle OPTION_VIRT and OPTION_NO_VIRT. ++ (mips_after_parse_args): Handle ase_virt field. ++ (s_mipsset): Handle "virt" and "novirt". ++ (mips_elf_final_processing): Add a comment about virt ASE might need ++ a new flag. ++ (md_show_usage): Print out the usage of -mvirt and mno-virt options. ++ * doc/c-mips.texi: Document -mvirt and -mno-virt. ++ Document ".set virt" and ".set novirt". ++ ++2013-05-09 Alan Modra ++ ++ * config/tc-ppc.c (md_apply_fix): Sign extend fieldval under ++ control of operand flag bits. ++ ++2013-05-07 Alan Modra ++ ++ * config/tc-ppc.c (PPC_VLE_SPLIT16A): Delete unused macro. ++ (PPC_VLE_SPLIT16D, PPC_VLE_LO16A, PPC_VLE_LO16D): Likewise. ++ (PPC_VLE_HI16A, PPC_VLE_HI16D): Likewise. ++ (PPC_VLE_HA16A, PPC_VLE_HA16D): Likewise. ++ (md_apply_fix): Set fx_no_overflow for assorted relocations. ++ Shift and sign-extend fieldval for use by some VLE reloc ++ operand->insert functions. ++ ++2013-05-06 Paul Brook ++ Catherine Moore ++ ++ * config/tc-mips.c (md_pcrel_from): Handle BFD_RELOC_32_PCREL. ++ (limited_pcrel_reloc_p): Likewise. ++ (md_apply_fix): Likewise. ++ (tc_gen_reloc): Likewise. ++ ++2013-05-06 Richard Sandiford ++ ++ * config/tc-mips.c (limited_pcrel_reloc_p): New function. ++ (mips_fix_adjustable): Adjust pc-relative check to use ++ limited_pc_reloc_p. ++ ++2013-05-02 Richard Sandiford ++ ++ * config/tc-mips.c (mips_pseudo_table): Add stabd and stabs entries. ++ (s_mips_stab): Do not restrict to stabn only. ++ ++2013-05-02 Nick Clifton ++ ++ * config/tc-msp430.c: Add support for the MSP430X architecture. ++ Add code to insert a NOP instruction after any instruction that ++ might change the interrupt state. ++ Add support for the LARGE memory model. ++ Add code to initialise the .MSP430.attributes section. ++ * config/tc-msp430.h: Add support for the MSP430X architecture. ++ * doc/c-msp430.texi: Document the new -mL and -mN command line ++ options. ++ * NEWS: Mention support for the MSP430X architecture. ++ ++2013-05-01 Maciej W. Rozycki ++ ++ * configure.tgt: Replace alpha*-*-linuxecoff* pattern with ++ alpha*-*-linux*ecoff*. ++ ++2013-04-30 Chao-ying Fu ++ ++ * config/tc-mips.c (mips_ip): Add sizelo. ++ For "+C", "+G", and "+H", set sizelo and compare against it. ++ ++2013-04-29 Nick Clifton ++ ++ * as.c (Options): Add -gdwarf-sections. ++ (parse_args): Likewise. ++ * as.h (flag_dwarf_sections): Declare. ++ * dwarf2dbg.c (emit_fixed_inc_line_addr): Skip section changes. ++ (process_entries): When -gdwarf-sections is enabled generate ++ fragmentary .debug_line sections. ++ (out_debug_line): Set the section for the .debug_line section end ++ symbol. ++ * doc/as.texinfo: Document -gdwarf-sections. ++ * NEWS: Mention -gdwarf-sections. ++ ++2013-04-26 Christian Groessler ++ ++ * config/tc-z8k.c (md_parse_option): Set z8k_target_from_cmdline ++ according to the target parameter. Don't call s_segm since s_segm ++ calls bfd_set_arch_mach using stdoutput, but stdoutput isn't ++ initialized yet. ++ (md_begin): Call s_segm according to target parameter from command ++ line. ++ ++2013-04-25 Alan Modra ++ ++ * configure.in: Allow little-endian linux. ++ * configure: Regenerate. ++ ++2013-04-24 Sandra Loosemore ++ ++ * config/tc-nios2.c (nios2_control_register_arg_p): Rename ++ "fstatus" control register to "eccinj". ++ ++2013-04-19 Kai Tietz ++ ++ * configure.tgt (i386-*-cygwin): Handle x86_64 cygwin. ++ ++2013-04-15 Julian Brown ++ ++ * expr.c (add_to_result, subtract_from_result): Make global. ++ * expr.h (add_to_result, subtract_from_result): Add prototypes. ++ * config/tc-sh.c (sh_optimize_expr): Use add_to_result, ++ subtract_from_result to handle extra bit of precision for .sleb128 ++ directive operands. ++ ++2013-04-10 Julian Brown ++ ++ * read.c (convert_to_bignum): Add sign parameter. Use it ++ instead of X_unsigned to determine sign of resulting bignum. ++ (emit_expr): Pass extra argument to convert_to_bignum. ++ (emit_leb128_expr): Use X_extrabit instead of X_unsigned. Pass ++ X_extrabit to convert_to_bignum. ++ (parse_bitfield_cons): Set X_extrabit. ++ * expr.c (make_expr_symbol, expr_build_uconstant, operand): ++ Initialise X_extrabit field as appropriate. ++ (add_to_result): New. ++ (subtract_from_result): New. ++ (expr): Use above. ++ * expr.h (expressionS): Add X_extrabit field. ++ ++2013-04-10 Jan Beulich ++ ++ * gas/config/tc-arm.c (encode_arm_addr_mode_3): Only reject base ++ register being PC when is_t or writeback, and use distinct ++ diagnostic for the latter case. ++ ++2013-04-10 Jan Beulich ++ ++ * gas/config/tc-arm.c (parse_operands): Re-write ++ po_barrier_or_imm(). ++ (do_barrier): Remove bogus constraint(). ++ (do_t_barrier): Remove. ++ ++2013-04-09 Joerg Wunsch ++ ++ * gas/config/tc-avr.c (mcu_types): Add ATmega64RFR2, ++ ATmega644RFR2, ATmega128RFR2, ATmega1284RFR2, ATmega256RFR2, ++ ATmega2564RFR2 ++ * gas/doc/c-avr.texi (-mmcu documentation): Likewise. ++ ++2013-04-09 Jan Beulich ++ ++ * gas/config/tc-arm.c (do_vmrs): Accept all control registers. ++ Use local variable Rt in more places. ++ (do_vmsr): Accept all control registers. ++ ++2013-04-09 Jan Beulich ++ ++ * gas/config/tc-arm.c (do_neon_mov): Fake an instruction suffix ++ if there was none specified for moves between scalar and core ++ register. ++ ++2013-04-09 Jan Beulich ++ ++ * gas/config/tc-arm.c (do_neon_ldx_stx): Reject VSTn in the ++ NEON_ALL_LANES case. ++ ++2013-04-08 Jan Beulich ++ ++ * gas/config/tc-arm.c (do_neon_ldr_str): Correct disgnostics for ++ PC-relative VSTR. ++ ++2013-04-08 Jan Beulich ++ ++ * gas/config/tc-arm.c (reg_names): Convert duplicate SP_fiq ++ entry to sp_fiq. ++ ++2013-04-03 Alan Modra ++ ++ * doc/as.texinfo: Add support to generate man options for h8300. ++ * doc/c-h8300.texi: Likewise. ++ ++2013-03-28 Ramana Radhakrishnan ++ ++ * config/tc-arm.c (arm_cpus): Add support for Cortex-A53 and ++ Cortex-A57. ++ ++2013-03-27 Alexis Deruelle ++ ++ PR binutils/15068 ++ * config/tc-tic6x.c (tic6x_try_encode): Add use of bitfields array. ++ ++2013-03-26 Nick Clifton ++ ++ PR gas/15295 ++ * listing.c (rebuffer_line): Rewrite to avoid seeking back to the ++ start of the file each time. ++ ++ PR gas/15178 ++ * config/tc-sparc.h (ELF_TARGET_FORMAT): Set to elf32-sparc for ++ FreeBSD targets. ++ ++2013-03-26 Douglas B Rupp ++ ++ * config/tc-ia64.c (emit_one_bundle): Move last_slot adjustment ++ after fixup. ++ ++2013-03-21 Will Newton ++ ++ * config/tc-arm.c (encode_thumb32_addr_mode): Emit an error for all ++ pc-relative str instructions in Thumb mode. ++ ++2013-03-21 Michael Schewe ++ ++ * config/tc-h8300.c (do_a_fix_imm): Add relaxation of mov ++ @(disp:32,ERx) to mov @(disp:16,ERx) insns by new reloc ++ R_H8_DISP32A16. ++ * config/tc-h8300.h: Remove duplicated defines. ++ ++2013-03-21 Senthil Kumar Selvaraj ++ ++ PR gas/15282 ++ * tc-avr.c (mcu_has_3_byte_pc): New function. ++ (tc_cfi_frame_initial_instructions): Call it to find return ++ address size. ++ ++2013-03-20 Alexis Deruelle ++ ++ PR gas/15095 ++ * config/tc-tic6x.c (tic6x_try_encode): Handle ++ tic6x_coding_dreg_(msb|lsb) field coding types and use it to ++ encode register pair numbers when required. ++ ++2013-03-15 Will Newton ++ ++ * config/tc-arm.c (do_neon_ldr_str): Fix error check for PC register ++ in vstr in Thumb mode for pre-ARMv7 cores. ++ ++2013-03-14 Andreas Schwab ++ ++ * doc/c-arc.texi (ARC Directives): Revert last change and use ++ @itemize instead of @table. ++ * doc/c-arm.texi (ARM-Instruction-Set): Likewise. ++ ++2013-03-14 Nick Clifton ++ ++ PR gas/15273 ++ * config/tc-arm.c (do_co_reg): Do not call check_obsolete with a ++ NULL message, instead just check ARM_CPU_IS_ANY directly. ++ ++2013-03-14 Nick Clifton ++ ++ PR gas/15212 ++ * doc/c-arc.texi (ARC Directives): Use @code instead of @bullet ++ for table format. ++ * doc/c-arm.texi (ARM-Instruction-Set): Likewise. Also add text ++ to the @item directives. ++ (ARM-Neon-Alignment): Move to correct place in the document. ++ * doc/c-cr16.texi (CR16 Operand Qualifiers): Fix up table ++ formatting. ++ * doc/c-tic54x.texi (TIC54X-Subsyms): Correct use of ++ @smallexample. ++ ++2013-03-12 Sebastian Huber ++ ++ * config/tc-nios2.c (nios2_consume_arg): Delete 'k' case. Add 'o' ++ case. Add default BAD_CASE to switch. ++ ++2013-03-11 Sebastian Huber ++ ++ * config/tc-nios2.c (nios2_assemble_args_ds): New function. ++ (nios2_arg_info_structs): Add "d,s" and "d,s,E" entries. ++ ++2013-03-11 Kyrylo Tkachov ++ ++ * config/tc-arm.c (crc_ext_armv8): New feature set. ++ (UNPRED_REG): New macro. ++ (do_crc32_1): New function. ++ (do_crc32b, do_crc32h, do_crc32w, do_crc32cb, ++ do_crc32ch, do_crc32cw): Likewise. ++ (TUEc): New macro. ++ (insns): Add entries for crc32 mnemonics. ++ (arm_extensions): Add entry for crc. ++ ++2013-03-08 Chung-Lin Tang ++ ++ * write.h (struct fix): Add fx_dot_frag field. ++ (dot_frag): Declare. ++ * write.c (dot_frag): New variable. ++ (fix_new_internal): Set fx_dot_frag field with dot_frag. ++ (fixup_segment): Base calculation of fx_offset with fx_dot_frag. ++ * expr.c (expr): Save value of frag_now in dot_frag when setting ++ dot_value. ++ * read.c (emit_expr): Likewise. Delete comments. ++ ++2013-03-07 H.J. Lu ++ ++ * config/tc-i386.c (flag_code_names): Removed. ++ (i386_index_check): Rewrote. ++ ++2013-03-05 Yufeng Zhang ++ ++ * config/tc-aarch64.c (aarch64_imm_float_p): Rename 'e' to 'pattern'; ++ add comment. ++ (aarch64_double_precision_fmovable): New function. ++ (parse_aarch64_imm_float): Add parameter 'dp_p'; call the new ++ function; handle hexadecimal representation of IEEE754 encoding. ++ (parse_operands): Update the call to parse_aarch64_imm_float. ++ ++2013-02-28 H.J. Lu ++ ++ * config/tc-i386.c (_i386_insn): Replace have_hle with hle_prefix. ++ (check_hle): Updated. ++ (md_assemble): Likewise. ++ (parse_insn): Likewise. ++ ++2013-02-28 H.J. Lu ++ ++ * config/tc-i386.c (_i386_insn): Add rep_prefix. ++ (md_assemble): Check if REP prefix is OK. ++ (parse_insn): Remove expecting_string_instruction. Set ++ i.rep_prefix. ++ ++2013-02-28 Yufeng Zhang ++ ++ * config/tc-aarch64.c (aarch64_features): Add the 'crc' option. ++ ++2013-02-28 Yufeng Zhang ++ ++ * config/tc-aarch64.c (parse_sys_reg): Allow the full range of CRn ++ for system registers. ++ ++2013-02-27 DJ Delorie ++ ++ * config/tc-rl78.c (reloc_function): Add %code -> BFD_RELOC_RL78_CODE. ++ (rl78_op): Handle %code(). ++ (rl78_cons_fix_new): Likewise, but ignore for 20-bit operands. ++ (tc_gen_reloc): Likwise; convert to a computed reloc. ++ (md_apply_fix): Likewise. ++ ++2013-02-25 Kaushik Phatak ++ ++ * config/rl78-parse.y: Fix encoding of DIVWU insn. ++ ++2013-02-25 Terry Guo ++ ++ * config/tc-arm.c (arm_cpus): Add cortex-r7 entry. ++ * doc/c-arm.texi: Add cortex-r7 and missing cortex-r5 to ++ list of accepted CPUs. ++ ++2013-02-19 H.J. Lu ++ ++ PR gas/15159 ++ * config/tc-i386.c (cpu_arch): Add ".smap". ++ ++ * doc/c-i386.texi: Document smap. ++ ++2013-02-18 Maciej W. Rozycki ++ ++ * config/tc-mips.c (s_cpload): Call mips_mark_labels and set ++ mips_assembling_insn appropriately. ++ (s_cpsetup, s_cprestore, s_cpreturn, s_cpadd): Likewise. ++ ++2013-02-18 Maciej W. Rozycki ++ ++ * config/tc-mips.c (append_insn): Correct indentation, remove ++ extraneous braces. ++ ++2013-02-15 Kyrylo Tkachov ++ ++ * config/tc-arm.c (do_neon_mov): Break on NS_NULL. ++ ++2013-02-15 Sebastian Huber ++ ++ * configure.tgt: Add nios2-*-rtems*. ++ ++2013-02-14 Yufeng Zhang ++ ++ * config/tc-aarch64.c (md_begin): Change to check if 'name' is ++ NULL. ++ ++2013-02-09 Jürgen Urban ++ ++ * config/tc-mips.c (CPU_HAS_LDC1_SDC1): New macro. ++ (macro): Use it. Assert that trunc.w.s is not used for r5900. ++ ++2013-02-08 Yi-Hsiu, Hsu ++ ++ * gas/config/tc-arm.c (arm_cpus): Add support for mcpu=marvell-pj4 ++ core. ++ ++2013-02-06 Sandra Loosemore ++ Andrew Jenner ++ ++ Based on patches from Altera Corporation. ++ ++ * Makefile.am (TARGET_CPU_CFILES): Add config/tc-nios2.c. ++ (TARGET_CPU_HFILES): Add config/tc-nios2.h. ++ * Makefile.in: Regenerated. ++ * configure.tgt: Add case for nios2*-linux*. ++ * config/obj-elf.c: Conditionally include elf/nios2.h. ++ * config/tc-nios2.c: New file. ++ * config/tc-nios2.h: New file. ++ * doc/Makefile.am (CPU_DOCS): Add c-nios2.texi. ++ * doc/Makefile.in: Regenerated. ++ * doc/all.texi: Set NIOSII. ++ * doc/as.texinfo (Overview): Add Nios II options. ++ (Machine Dependencies): Include c-nios2.texi. ++ * doc/c-nios2.texi: New file. ++ * NEWS: Note Altera Nios II support. ++ ++2013-02-06 Alan Modra ++ ++ PR gas/14255 ++ * config/tc-avr.h (TC_VALIDATE_FIX): Mark symbol used by reloc. ++ Don't skip fixups with fx_subsy non-NULL. ++ * config/tc-avr.c (tc_gen_reloc): Don't specially handle fixups ++ with fx_subsy non-NULL. ++ ++2013-02-04 H.J. Lu ++ ++ * doc/c-metag.texi: Add "@c man" markers. ++ ++2013-02-04 Alan Modra ++ ++ * write.c (fixup_segment): Return void. Delete seg_reloc_count ++ related code. ++ (TC_ADJUST_RELOC_COUNT): Delete. ++ * config/tc-i960.h (TC_ADJUST_RELOC_COUNT): Delete. ++ ++2013-02-04 Alan Modra ++ ++ * po/POTFILES.in: Regenerate. ++ ++2013-01-30 Markos Chandras ++ ++ * config/tc-metag.c: Make SWAP instruction less permissive with ++ its operands. ++ ++2013-01-29 DJ Delorie ++ ++ * config/tc-rl78.c (rl78_cons_fix_new): Handle user-specified ++ relocs in .word/.etc statements. ++ ++2013-01-29 Roland McGrath ++ ++ * config/tc-arm.c (md_apply_fix): Use as_bad_where for "bad ++ immediate value for 8-bit offset" error so it shows line info. ++ ++2013-01-24 Joseph Myers ++ ++ * config/tc-ppc.c (md_assemble): Do not generate APUinfo sections ++ for 64-bit output. ++ ++2013-01-24 Nick Clifton ++ ++ * config/tc-v850.c: Add support for e3v5 architecture. ++ * doc/c-v850.texi: Mention new support. ++ ++2013-01-23 Nick Clifton ++ ++ PR gas/15039 ++ * config/tc-avr.c: Include dwarf2dbg.h. ++ ++2013-01-18 H.J. Lu ++ ++ * config/tc-i386.c (reloc): Support size relocation only for ELF. ++ (tc_i386_fix_adjustable): Likewise. ++ (lex_got): Likewise. ++ (tc_gen_reloc): Likewise. ++ ++2013-01-17 Yufeng Zhang ++ ++ * config/tc-aarch64.c (output_operand_error_record): Change to output ++ the out-of-range error message as value-expected message if there is ++ only one single value in the expected range. ++ (programmer_friendly_fixup): Remove the handling of 8-bit MOVI with ++ LSL #0 as a programmer-friendly feature. ++ ++2013-01-16 H.J. Lu ++ ++ * config/tc-i386.c (reloc): Support BFD_RELOC_SIZE32. ++ (tc_i386_fix_adjustable): Keep symbol for BFD_RELOC_32_SIZE and ++ BFD_RELOC_64_SIZE relocations. ++ (lex_got): Support "symbol@SIZE" and don't create GOT symbol ++ for it. ++ (tc_gen_reloc): Resolve BFD_RELOC_SIZE32 and BFD_RELOC_SIZE64 ++ relocations against local symbols. ++ ++2013-01-16 Alan Modra ++ ++ * config/tc-ppc.c (md_assemble ): Ignore line after ++ finding some sort of toc syntax error, and break to avoid ++ compiler uninit warning. ++ ++2013-01-15 H.J. Lu ++ ++ PR gas/15019 ++ * config/tc-i386.c (lex_got): Increment length by 1 if the ++ relocation token is removed. ++ ++2013-01-15 Nick Clifton ++ ++ * config/tc-v850.c (md_assemble): Allow signed values for ++ V850E_IMMEDIATE. ++ ++2013-01-11 Sean Keys ++ ++ * config/tc-xgate.c (md_begin): Fix mistake made when going from ++ git to cvs. ++ ++2013-01-10 Peter Bergner ++ ++ * doc/as.texinfo (Target PowerPC): Document -mpower8 and -mhtm. ++ * doc/c-ppc.texi (PowerPC-Opts): Likewise. ++ * config/tc-ppc.c (md_show_usage): Likewise. ++ (ppc_handle_align): Handle power8's group ending nop. ++ ++2013-01-10 Sean Keys ++ ++ * config/tc-xgate.c (md_begin): Fix the printing of opcodes so ++ that the assember exits after the opcodes have been printed. ++ ++2013-01-10 H.J. Lu ++ ++ * app.c: Remove trailing white spaces. ++ * as.c: Likewise. ++ * as.h: Likewise. ++ * cond.c: Likewise. ++ * dw2gencfi.c: Likewise. ++ * dwarf2dbg.h: Likewise. ++ * ecoff.c: Likewise. ++ * input-file.c: Likewise. ++ * itbl-lex.h: Likewise. ++ * output-file.c: Likewise. ++ * read.c: Likewise. ++ * sb.c: Likewise. ++ * subsegs.c: Likewise. ++ * symbols.c: Likewise. ++ * write.c: Likewise. ++ * config/tc-i386.c: Likewise. ++ * doc/Makefile.am: Likewise. ++ * doc/Makefile.in: Likewise. ++ * doc/c-aarch64.texi: Likewise. ++ * doc/c-alpha.texi: Likewise. ++ * doc/c-arc.texi: Likewise. ++ * doc/c-arm.texi: Likewise. ++ * doc/c-avr.texi: Likewise. ++ * doc/c-bfin.texi: Likewise. ++ * doc/c-cr16.texi: Likewise. ++ * doc/c-d10v.texi: Likewise. ++ * doc/c-d30v.texi: Likewise. ++ * doc/c-h8300.texi: Likewise. ++ * doc/c-hppa.texi: Likewise. ++ * doc/c-i370.texi: Likewise. ++ * doc/c-i386.texi: Likewise. ++ * doc/c-i860.texi: Likewise. ++ * doc/c-m32c.texi: Likewise. ++ * doc/c-m32r.texi: Likewise. ++ * doc/c-m68hc11.texi: Likewise. ++ * doc/c-m68k.texi: Likewise. ++ * doc/c-microblaze.texi: Likewise. ++ * doc/c-mips.texi: Likewise. ++ * doc/c-msp430.texi: Likewise. ++ * doc/c-mt.texi: Likewise. ++ * doc/c-s390.texi: Likewise. ++ * doc/c-score.texi: Likewise. ++ * doc/c-sh.texi: Likewise. ++ * doc/c-sh64.texi: Likewise. ++ * doc/c-tic54x.texi: Likewise. ++ * doc/c-tic6x.texi: Likewise. ++ * doc/c-v850.texi: Likewise. ++ * doc/c-xc16x.texi: Likewise. ++ * doc/c-xgate.texi: Likewise. ++ * doc/c-xtensa.texi: Likewise. ++ * doc/c-z80.texi: Likewise. ++ * doc/internals.texi: Likewise. ++ ++2013-01-10 Roland McGrath ++ ++ * hash.c (hash_new_sized): Make it global. ++ * hash.h: Declare it. ++ * macro.c (define_macro): Use hash_new_sized instead of hash_new, ++ pass a small size. ++ ++2013-01-10 Will Newton ++ ++ * Makefile.am: Add Meta. ++ * Makefile.in: Regenerate. ++ * config/tc-metag.c: New file. ++ * config/tc-metag.h: New file. ++ * configure.tgt: Add Meta. ++ * doc/Makefile.am: Add Meta. ++ * doc/Makefile.in: Regenerate. ++ * doc/all.texi: Add Meta. ++ * doc/as.texiinfo: Document Meta options. ++ * doc/c-metag.texi: New file. ++ ++2013-01-09 Steve Ellcey ++ ++ * config/tc-i386.c (md_begin): Remove 'internal Error' from as_fatal ++ calls. ++ * config/tc-mips.c (internalError): Remove, replace with abort. ++ ++2013-01-08 Yufeng Zhang ++ ++ * config/tc-aarch64.c (parse_operands): Change to compare the result ++ of function call 'parse_sys_reg' with 'PARSE_FAIL' instead of 'FALSE'. ++ ++2013-01-07 Nick Clifton ++ ++ PR gas/14887 ++ * config/tc-arm.c (skip_past_char): Skip whitespace before the ++ anticipated character. ++ * config/tc-arm.c (parse_address_main): Delete skip of whitespace ++ here as it is no longer needed. ++ ++2013-01-06 Andreas Schwab ++ ++ * doc/c-mips.texi (MIPS Opts): Fix use of @itemx. ++ * doc/c-score.texi (SCORE-Opts): Likewise. ++ * doc/c-tic54x.texi (TIC54X-Directives): Likewise. ++ ++2013-01-04 Juergen Urban ++ ++ * config/tc-mips.c: Add support for MIPS r5900. ++ Add M_LQ_AB and M_SQ_AB to support large values for instructions ++ lq and sq. ++ (can_swap_branch_p, get_append_method): Detect some conditional ++ short loops to fix a bug on the r5900 by NOP in the branch delay ++ slot. ++ (M_MUL): Support 3 operands in multu on r5900. ++ (M_TRUNCWS): Support trunc.w.s on r5900 in MIPS ISA I. ++ (s_mipsset): Force 32 bit floating point on r5900. ++ (mips_ip): Check parameter range of instructions mfps and mtps on ++ r5900. ++ * configure.in: Detect CPU type when target string contains r5900 ++ (e.g. mips64r5900el-linux-gnu). ++ ++2013-01-02 H.J. Lu ++ ++ * as.c (parse_args): Update copyright year to 2013. ++ ++2013-01-02 Yufeng Zhang ++ ++ * config/tc-aarch64.c (aarch64_cpus): Add entries for "cortex-a53" ++ and "cortex57". ++ ++2013-01-02 Nick Clifton ++ ++ PR gas/14987 ++ * config/tc-arm.c (parse_address_main): Skip whitespace before a ++ closing bracket. ++ ++For older changes see ChangeLog-2012 ++ ++Copyright (C) 2013 Free Software Foundation, Inc. ++ ++Copying and distribution of this file, with or without modification, ++are permitted in any medium without royalty provided the copyright ++notice and this notice are preserved. ++ ++Local Variables: ++mode: change-log ++left-margin: 8 ++fill-column: 74 ++version-control: never ++End: diff --git a/gas/ChangeLog-9295 b/gas/ChangeLog-9295 new file mode 100644 index 0000000..b8a25fe @@ -367716,7 +371103,7 @@ index 0000000..b8a25fe +End: diff --git a/gas/ChangeLog-9697 b/gas/ChangeLog-9697 new file mode 100644 -index 0000000..499daf4 +index 0000000..96e1aee --- /dev/null +++ b/gas/ChangeLog-9697 @@ -0,0 +1,5972 @@ @@ -373680,7 +377067,7 @@ index 0000000..499daf4 + +For older changes see ChangeLog-9295 + -+Copyright (C) 1996,1997 Free Software Foundation, Inc. ++Copyright (C) 1996-1997 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -373694,7 +377081,7 @@ index 0000000..499daf4 +End: diff --git a/gas/ChangeLog-9899 b/gas/ChangeLog-9899 new file mode 100644 -index 0000000..97276f4 +index 0000000..99cf19d --- /dev/null +++ b/gas/ChangeLog-9899 @@ -0,0 +1,4873 @@ @@ -378559,7 +381946,7 @@ index 0000000..97276f4 + +For older changes see ChangeLog-9697 + -+Copyright (C) 1998,1999 Free Software Foundation, Inc. ++Copyright (C) 1998-1999 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -378573,26 +381960,26 @@ index 0000000..97276f4 +End: diff --git a/gas/MAINTAINERS b/gas/MAINTAINERS new file mode 100644 -index 0000000..cd933df +index 0000000..360ebd0 --- /dev/null +++ b/gas/MAINTAINERS @@ -0,0 +1,7 @@ +See ../binutils/MAINTAINERS + -+Copyright (C) 2012 Free Software Foundation, Inc. ++Copyright (C) 2012-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright +notice and this notice are preserved. diff --git a/gas/Makefile.am b/gas/Makefile.am new file mode 100644 -index 0000000..cf6d877 +index 0000000..669ab19 --- /dev/null +++ b/gas/Makefile.am @@ -0,0 +1,698 @@ +## Process this file with automake to generate Makefile.in +# -+# Copyright 2012, 2013 Free Software Foundation ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -378759,8 +382146,7 @@ index 0000000..cf6d877 + config/tc-nds32.c \ + config/tc-nios2.c \ + config/tc-ns32k.c \ -+ config/tc-openrisc.c \ -+ config/tc-or32.c \ ++ config/tc-or1k.c \ + config/tc-pdp11.c \ + config/tc-pj.c \ + config/tc-ppc.c \ @@ -378831,8 +382217,7 @@ index 0000000..cf6d877 + config/tc-nds32.h \ + config/tc-nios2.h \ + config/tc-ns32k.h \ -+ config/tc-openrisc.h \ -+ config/tc-or32.h \ ++ config/tc-or1k.h \ + config/tc-pdp11.h \ + config/tc-pj.h \ + config/tc-ppc.h \ @@ -379287,13 +382672,15 @@ index 0000000..cf6d877 + - (cd stage3 ; rm -f as$(EXEEXT) ; mv -f * ..) + - rmdir stage3 + -+CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in $(srcdir)/configure.tgt ++CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in \ ++ $(srcdir)/configure.tgt \ ++ $(BFDDIR)/development.sh diff --git a/gas/Makefile.in b/gas/Makefile.in new file mode 100644 -index 0000000..01475a1 +index 0000000..2ca56df --- /dev/null +++ b/gas/Makefile.in -@@ -0,0 +1,2710 @@ +@@ -0,0 +1,2696 @@ +# Makefile.in generated by automake 1.11.1 from Makefile.am. +# @configure_input@ + @@ -379312,7 +382699,7 @@ index 0000000..01475a1 +@SET_MAKE@ + +# -+# Copyright 2012, 2013 Free Software Foundation ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -379732,8 +383119,7 @@ index 0000000..01475a1 + config/tc-nds32.c \ + config/tc-nios2.c \ + config/tc-ns32k.c \ -+ config/tc-openrisc.c \ -+ config/tc-or32.c \ ++ config/tc-or1k.c \ + config/tc-pdp11.c \ + config/tc-pj.c \ + config/tc-ppc.c \ @@ -379804,8 +383190,7 @@ index 0000000..01475a1 + config/tc-nds32.h \ + config/tc-nios2.h \ + config/tc-ns32k.h \ -+ config/tc-openrisc.h \ -+ config/tc-or32.h \ ++ config/tc-or1k.h \ + config/tc-pdp11.h \ + config/tc-pj.h \ + config/tc-ppc.h \ @@ -379975,7 +383360,10 @@ index 0000000..01475a1 + testsuite/site.exp site.bak site.exp stage stage1 stage2 + +against = stage2 -+CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in $(srcdir)/configure.tgt ++CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in \ ++ $(srcdir)/configure.tgt \ ++ $(BFDDIR)/development.sh ++ +all: config.h + $(MAKE) $(AM_MAKEFLAGS) all-recursive + @@ -380155,8 +383543,7 @@ index 0000000..01475a1 +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-nds32.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-nios2.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-ns32k.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-openrisc.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-or32.Po@am__quote@ ++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-or1k.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-pdp11.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-pj.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/tc-ppc.Po@am__quote@ @@ -380809,33 +384196,19 @@ index 0000000..01475a1 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-ns32k.obj `if test -f 'config/tc-ns32k.c'; then $(CYGPATH_W) 'config/tc-ns32k.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-ns32k.c'; fi` + -+tc-openrisc.o: config/tc-openrisc.c -+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-openrisc.o -MD -MP -MF $(DEPDIR)/tc-openrisc.Tpo -c -o tc-openrisc.o `test -f 'config/tc-openrisc.c' || echo '$(srcdir)/'`config/tc-openrisc.c -+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-openrisc.Tpo $(DEPDIR)/tc-openrisc.Po -+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-openrisc.c' object='tc-openrisc.o' libtool=no @AMDEPBACKSLASH@ ++tc-or1k.o: config/tc-or1k.c ++@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-or1k.o -MD -MP -MF $(DEPDIR)/tc-or1k.Tpo -c -o tc-or1k.o `test -f 'config/tc-or1k.c' || echo '$(srcdir)/'`config/tc-or1k.c ++@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-or1k.Tpo $(DEPDIR)/tc-or1k.Po ++@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-or1k.c' object='tc-or1k.o' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ -+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-openrisc.o `test -f 'config/tc-openrisc.c' || echo '$(srcdir)/'`config/tc-openrisc.c ++@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-or1k.o `test -f 'config/tc-or1k.c' || echo '$(srcdir)/'`config/tc-or1k.c + -+tc-openrisc.obj: config/tc-openrisc.c -+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-openrisc.obj -MD -MP -MF $(DEPDIR)/tc-openrisc.Tpo -c -o tc-openrisc.obj `if test -f 'config/tc-openrisc.c'; then $(CYGPATH_W) 'config/tc-openrisc.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-openrisc.c'; fi` -+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-openrisc.Tpo $(DEPDIR)/tc-openrisc.Po -+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-openrisc.c' object='tc-openrisc.obj' libtool=no @AMDEPBACKSLASH@ ++tc-or1k.obj: config/tc-or1k.c ++@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-or1k.obj -MD -MP -MF $(DEPDIR)/tc-or1k.Tpo -c -o tc-or1k.obj `if test -f 'config/tc-or1k.c'; then $(CYGPATH_W) 'config/tc-or1k.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-or1k.c'; fi` ++@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-or1k.Tpo $(DEPDIR)/tc-or1k.Po ++@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-or1k.c' object='tc-or1k.obj' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ -+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-openrisc.obj `if test -f 'config/tc-openrisc.c'; then $(CYGPATH_W) 'config/tc-openrisc.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-openrisc.c'; fi` -+ -+tc-or32.o: config/tc-or32.c -+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-or32.o -MD -MP -MF $(DEPDIR)/tc-or32.Tpo -c -o tc-or32.o `test -f 'config/tc-or32.c' || echo '$(srcdir)/'`config/tc-or32.c -+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-or32.Tpo $(DEPDIR)/tc-or32.Po -+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-or32.c' object='tc-or32.o' libtool=no @AMDEPBACKSLASH@ -+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ -+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-or32.o `test -f 'config/tc-or32.c' || echo '$(srcdir)/'`config/tc-or32.c -+ -+tc-or32.obj: config/tc-or32.c -+@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-or32.obj -MD -MP -MF $(DEPDIR)/tc-or32.Tpo -c -o tc-or32.obj `if test -f 'config/tc-or32.c'; then $(CYGPATH_W) 'config/tc-or32.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-or32.c'; fi` -+@am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/tc-or32.Tpo $(DEPDIR)/tc-or32.Po -+@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='config/tc-or32.c' object='tc-or32.obj' libtool=no @AMDEPBACKSLASH@ -+@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ -+@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-or32.obj `if test -f 'config/tc-or32.c'; then $(CYGPATH_W) 'config/tc-or32.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-or32.c'; fi` ++@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o tc-or1k.obj `if test -f 'config/tc-or1k.c'; then $(CYGPATH_W) 'config/tc-or1k.c'; else $(CYGPATH_W) '$(srcdir)/config/tc-or1k.c'; fi` + +tc-pdp11.o: config/tc-pdp11.c +@am__fastdepCC_TRUE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT tc-pdp11.o -MD -MP -MF $(DEPDIR)/tc-pdp11.Tpo -c -o tc-pdp11.o `test -f 'config/tc-pdp11.c' || echo '$(srcdir)/'`config/tc-pdp11.c @@ -382006,12 +385379,17 @@ index 0000000..01475a1 +.NOEXPORT: diff --git a/gas/NEWS b/gas/NEWS new file mode 100644 -index 0000000..2e62450 +index 0000000..debf37f --- /dev/null +++ b/gas/NEWS -@@ -0,0 +1,628 @@ +@@ -0,0 +1,633 @@ +-*- text -*- + ++* Replace support for openrisc and or32 with support for or1k. ++ ++* Enhanced the ARM port to accept the assembler output from the CodeComposer ++ Studio tool. Support is enabled via the new command line option -mccs. ++ +* Add support for the Andes NDS32. + +Changes in 2.24: @@ -382629,7 +386007,7 @@ index 0000000..2e62450 + of new CPUs and formats, lots of bugs fixed. + + -+Copyright (C) 2012 Free Software Foundation, Inc. ++Copyright (C) 2012-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -382640,7 +386018,7 @@ index 0000000..2e62450 +End: diff --git a/gas/README b/gas/README new file mode 100644 -index 0000000..b185977 +index 0000000..9eb0a98 --- /dev/null +++ b/gas/README @@ -0,0 +1,170 @@ @@ -382809,7 +386187,7 @@ index 0000000..b185977 + +See ../binutils/README for what we need in a bug report. + -+Copyright (C) 2012 Free Software Foundation, Inc. ++Copyright (C) 2012-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -383932,14 +387310,12 @@ index 0000000..ea731ac +m4_include([acinclude.m4]) diff --git a/gas/app.c b/gas/app.c new file mode 100644 -index 0000000..1a7ce95 +index 0000000..32a172f --- /dev/null +++ b/gas/app.c -@@ -0,0 +1,1480 @@ +@@ -0,0 +1,1481 @@ +/* This is the Assembler Pre-Processor -+ Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, -+ 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009, 2010, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -384098,7 +387474,10 @@ index 0000000..1a7ce95 + for (p = line_comment_chars; *p; p++) + lex[(unsigned char) *p] = LEX_IS_LINE_COMMENT_START; + -+ for (p = line_separator_chars; *p; p++) ++#ifndef tc_line_separator_chars ++#define tc_line_separator_chars line_separator_chars ++#endif ++ for (p = tc_line_separator_chars; *p; p++) + lex[(unsigned char) *p] = LEX_IS_LINE_SEPARATOR; + +#ifdef tc_parallel_separator_chars @@ -385418,12 +388797,12 @@ index 0000000..1a7ce95 +} diff --git a/gas/as.c b/gas/as.c new file mode 100644 -index 0000000..f198043 +index 0000000..752af64 --- /dev/null +++ b/gas/as.c @@ -0,0 +1,1326 @@ +/* as.c - GAS main program. -+ Copyright 1987-2013 Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -386050,7 +389429,7 @@ index 0000000..f198043 + case OPTION_VERSION: + /* This output is intended to follow the GNU standards document. */ + printf (_("GNU assembler %s\n"), BFD_VERSION_STRING); -+ printf (_("Copyright 2013 Free Software Foundation, Inc.\n")); ++ printf (_("Copyright (C) 2014 Free Software Foundation, Inc.\n")); + printf (_("\ +This program is free software; you may redistribute it under the terms of\n\ +the GNU General Public License version 3 or later.\n\ @@ -386750,12 +390129,12 @@ index 0000000..f198043 +} diff --git a/gas/as.h b/gas/as.h new file mode 100644 -index 0000000..1fefee9 +index 0000000..df04dce --- /dev/null +++ b/gas/as.h @@ -0,0 +1,634 @@ +/* as.h - global header file -+ Copyright 1987-2013 Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -387390,12 +390769,12 @@ index 0000000..1fefee9 +#endif /* GAS */ diff --git a/gas/asintl.h b/gas/asintl.h new file mode 100644 -index 0000000..b392bb3 +index 0000000..1634872 --- /dev/null +++ b/gas/asintl.h @@ -0,0 +1,52 @@ +/* asintl.h - gas-specific header for gettext code. -+ Copyright 1998, 1999, 2000, 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 1998-2014 Free Software Foundation, Inc. + + Written by Tom Tromey + @@ -387448,13 +390827,12 @@ index 0000000..b392bb3 +#endif diff --git a/gas/atof-generic.c b/gas/atof-generic.c new file mode 100644 -index 0000000..40a9ff0 +index 0000000..ced567b --- /dev/null +++ b/gas/atof-generic.c -@@ -0,0 +1,614 @@ +@@ -0,0 +1,613 @@ +/* atof_generic.c - turn a string of digits into a Flonum -+ Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1998, 1999, 2000, -+ 2001, 2003, 2005, 2006, 2007, 2009 Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -388068,12 +391446,12 @@ index 0000000..40a9ff0 +/* end of atof_generic.c */ diff --git a/gas/bignum.h b/gas/bignum.h new file mode 100644 -index 0000000..41c3559 +index 0000000..4ec1b47 --- /dev/null +++ b/gas/bignum.h @@ -0,0 +1,42 @@ +/* bignum.h-arbitrary precision integers -+ Copyright 1987, 1992, 2003, 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -388116,13 +391494,12 @@ index 0000000..41c3559 +typedef unsigned short LITTLENUM_TYPE; diff --git a/gas/bit_fix.h b/gas/bit_fix.h new file mode 100644 -index 0000000..a83bddc +index 0000000..809905c --- /dev/null +++ b/gas/bit_fix.h -@@ -0,0 +1,48 @@ +@@ -0,0 +1,47 @@ +/* bit_fix.h -+ Copyright 1987, 1992, 2000, 2001, 2003, 2005, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -388170,13 +391547,12 @@ index 0000000..a83bddc +#endif /* __bit_fix_h__ */ diff --git a/gas/cgen.c b/gas/cgen.c new file mode 100644 -index 0000000..f7706c1 +index 0000000..61ac60d --- /dev/null +++ b/gas/cgen.c -@@ -0,0 +1,1091 @@ +@@ -0,0 +1,1090 @@ +/* GAS interface for targets using CGEN: Cpu tools GENerator. -+ Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, -+ 2006, 2007, 2009, 2010, 2011, 2012 Free Software Foundation, Inc. ++ Copyright (C) 1996-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -389267,13 +392643,12 @@ index 0000000..f7706c1 +} diff --git a/gas/cgen.h b/gas/cgen.h new file mode 100644 -index 0000000..847e042 +index 0000000..0b85b38 --- /dev/null +++ b/gas/cgen.h -@@ -0,0 +1,106 @@ +@@ -0,0 +1,105 @@ +/* GAS cgen support. -+ Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007, 2011 -+ Free Software Foundation, Inc. ++ Copyright (C) 1998-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -389379,12 +392754,12 @@ index 0000000..847e042 +#endif /* GAS_CGEN_H */ diff --git a/gas/compress-debug.c b/gas/compress-debug.c new file mode 100644 -index 0000000..0907600 +index 0000000..7a49e42 --- /dev/null +++ b/gas/compress-debug.c @@ -0,0 +1,117 @@ +/* compress-debug.c - compress debug sections -+ Copyright 2010 Free Software Foundation, Inc. ++ Copyright (C) 2010-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -389502,12 +392877,12 @@ index 0000000..0907600 +} diff --git a/gas/compress-debug.h b/gas/compress-debug.h new file mode 100644 -index 0000000..9d821e9 +index 0000000..54085ff --- /dev/null +++ b/gas/compress-debug.h @@ -0,0 +1,39 @@ +/* compress-debug.h - Header file for compressed debug sections. -+ Copyright 2010 Free Software Foundation, Inc. ++ Copyright (C) 2010-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -389547,13 +392922,12 @@ index 0000000..9d821e9 +#endif /* COMPRESS_DEBUG_H */ diff --git a/gas/cond.c b/gas/cond.c new file mode 100644 -index 0000000..c309123 +index 0000000..3b9b450 --- /dev/null +++ b/gas/cond.c -@@ -0,0 +1,577 @@ +@@ -0,0 +1,576 @@ +/* cond.c - conditional assembly pseudo-ops, and .include -+ Copyright 1990, 1991, 1992, 1993, 1995, 1997, 1998, 2000, 2001, 2002, -+ 2003, 2005, 2006, 2007 Free Software Foundation, Inc. ++ Copyright (C) 1990-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -390130,10 +393504,10 @@ index 0000000..c309123 +} diff --git a/gas/config.in b/gas/config.in new file mode 100644 -index 0000000..411710e +index 0000000..f3ed2b4 --- /dev/null +++ b/gas/config.in -@@ -0,0 +1,362 @@ +@@ -0,0 +1,380 @@ +/* config.in. Generated from configure.in by autoheader. */ + +/* Check that config.h is #included before system headers @@ -390315,6 +393689,24 @@ index 0000000..411710e +/* Choose a default ABI for MIPS targets. */ +#undef MIPS_DEFAULT_ABI + ++/* Define value for nds32_arch_name */ ++#undef NDS32_DEFAULT_ARCH_NAME ++ ++/* Define default value for nds32_audio_ext */ ++#undef NDS32_DEFAULT_AUDIO_EXT ++ ++/* Define default value for nds32_dx_regs */ ++#undef NDS32_DEFAULT_DX_REGS ++ ++/* Define default value for nds32_perf_ext */ ++#undef NDS32_DEFAULT_PERF_EXT ++ ++/* Define default value for nds32_perf_ext2 */ ++#undef NDS32_DEFAULT_PERF_EXT2 ++ ++/* Define default value for nds32_string_ext */ ++#undef NDS32_DEFAULT_STRING_EXT ++ +/* Define if environ is not declared in system header files. */ +#undef NEED_DECLARATION_ENVIRON + @@ -390498,14 +393890,13 @@ index 0000000..411710e +#endif diff --git a/gas/config/aout_gnu.h b/gas/config/aout_gnu.h new file mode 100644 -index 0000000..99186b9 +index 0000000..35ab91b --- /dev/null +++ b/gas/config/aout_gnu.h -@@ -0,0 +1,451 @@ +@@ -0,0 +1,450 @@ +/* This file is aout_gnu.h + -+ Copyright 1987, 1988, 1989, 1990, 1991, 1992, 1993, 1994, 2000, 2002, -+ 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -390955,13 +394346,12 @@ index 0000000..99186b9 +/* end of aout_gnu.h */ diff --git a/gas/config/atof-ieee.c b/gas/config/atof-ieee.c new file mode 100644 -index 0000000..32e5707 +index 0000000..d23405c --- /dev/null +++ b/gas/config/atof-ieee.c -@@ -0,0 +1,813 @@ +@@ -0,0 +1,812 @@ +/* atof_ieee.c - turn a Flonum into an IEEE floating point number -+ Copyright 1987, 1992, 1994, 1996, 1997, 1998, 1999, 2000, 2001, 2005, -+ 2007, 2009 Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -391774,13 +395164,12 @@ index 0000000..32e5707 +} diff --git a/gas/config/atof-vax.c b/gas/config/atof-vax.c new file mode 100644 -index 0000000..6e81ffe +index 0000000..9075b97 --- /dev/null +++ b/gas/config/atof-vax.c -@@ -0,0 +1,451 @@ +@@ -0,0 +1,450 @@ +/* atof_vax.c - turn a Flonum into a VAX floating point number -+ Copyright 1987, 1992, 1993, 1995, 1997, 1999, 2000, 2005, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -392231,13 +395620,12 @@ index 0000000..6e81ffe +} diff --git a/gas/config/bfin-aux.h b/gas/config/bfin-aux.h new file mode 100644 -index 0000000..e78a4e8 +index 0000000..44665b9 --- /dev/null +++ b/gas/config/bfin-aux.h -@@ -0,0 +1,69 @@ +@@ -0,0 +1,68 @@ +/* bfin-aux.h ADI Blackfin Header file for gas -+ Copyright 2005, 2007, 2009, 2010 -+ Free Software Foundation, Inc. ++ Copyright (C) 2005-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -392306,13 +395694,12 @@ index 0000000..e78a4e8 +INSTR_T bfin_gen_multi_instr (INSTR_T, INSTR_T, INSTR_T); diff --git a/gas/config/bfin-defs.h b/gas/config/bfin-defs.h new file mode 100644 -index 0000000..b43fe76 +index 0000000..0f494c8 --- /dev/null +++ b/gas/config/bfin-defs.h -@@ -0,0 +1,398 @@ +@@ -0,0 +1,397 @@ +/* bfin-defs.h ADI Blackfin gas header file -+ Copyright 2005, 2006, 2007, 2009, 2010, 2011 -+ Free Software Foundation, Inc. ++ Copyright (C) 2005-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -392710,12 +396097,11 @@ index 0000000..b43fe76 + diff --git a/gas/config/bfin-lex-wrapper.c b/gas/config/bfin-lex-wrapper.c new file mode 100644 -index 0000000..e61118c +index 0000000..d836c30 --- /dev/null +++ b/gas/config/bfin-lex-wrapper.c -@@ -0,0 +1,26 @@ -+/* Copyright 20012 -+ Free Software Foundation, Inc. +@@ -0,0 +1,25 @@ ++/* Copyright (C) 2012-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -392742,13 +396128,12 @@ index 0000000..e61118c +#include "bfin-lex.c" diff --git a/gas/config/bfin-lex.l b/gas/config/bfin-lex.l new file mode 100644 -index 0000000..9792323 +index 0000000..c8462c5 --- /dev/null +++ b/gas/config/bfin-lex.l -@@ -0,0 +1,557 @@ +@@ -0,0 +1,556 @@ +/* bfin-lex.l ADI Blackfin lexer -+ Copyright 2005, 2006, 2007, 2008, 2010 -+ Free Software Foundation, Inc. ++ Copyright (C) 2005-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -393305,13 +396690,12 @@ index 0000000..9792323 +#endif diff --git a/gas/config/bfin-parse.y b/gas/config/bfin-parse.y new file mode 100644 -index 0000000..4eaf6f1 +index 0000000..fe742ad --- /dev/null +++ b/gas/config/bfin-parse.y -@@ -0,0 +1,4673 @@ +@@ -0,0 +1,4672 @@ +/* bfin-parse.y ADI Blackfin parser -+ Copyright 2005, 2006, 2007, 2008, 2009, 2010, 2011 -+ Free Software Foundation, Inc. ++ Copyright (C) 2005-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -397984,11 +401368,11 @@ index 0000000..4eaf6f1 + diff --git a/gas/config/e-crisaout.c b/gas/config/e-crisaout.c new file mode 100644 -index 0000000..4adeb0b +index 0000000..c1fa544 --- /dev/null +++ b/gas/config/e-crisaout.c @@ -0,0 +1,38 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -398028,11 +401412,11 @@ index 0000000..4adeb0b +#include "emul-target.h" diff --git a/gas/config/e-criself.c b/gas/config/e-criself.c new file mode 100644 -index 0000000..f4372f0 +index 0000000..db86924 --- /dev/null +++ b/gas/config/e-criself.c @@ -0,0 +1,38 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -398072,11 +401456,11 @@ index 0000000..f4372f0 +#include "emul-target.h" diff --git a/gas/config/e-i386aout.c b/gas/config/e-i386aout.c new file mode 100644 -index 0000000..779111a +index 0000000..7fd7c31 --- /dev/null +++ b/gas/config/e-i386aout.c @@ -0,0 +1,38 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -398116,11 +401500,11 @@ index 0000000..779111a +#include "emul-target.h" diff --git a/gas/config/e-i386coff.c b/gas/config/e-i386coff.c new file mode 100644 -index 0000000..6cc42c0 +index 0000000..272a167 --- /dev/null +++ b/gas/config/e-i386coff.c @@ -0,0 +1,38 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -398160,11 +401544,11 @@ index 0000000..6cc42c0 +#include "emul-target.h" diff --git a/gas/config/e-i386elf.c b/gas/config/e-i386elf.c new file mode 100644 -index 0000000..8fbd878 +index 0000000..a5b2713 --- /dev/null +++ b/gas/config/e-i386elf.c @@ -0,0 +1,38 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -398204,11 +401588,11 @@ index 0000000..8fbd878 +#include "emul-target.h" diff --git a/gas/config/e-mipself.c b/gas/config/e-mipself.c new file mode 100644 -index 0000000..8f37b82 +index 0000000..bc7f09f --- /dev/null +++ b/gas/config/e-mipself.c @@ -0,0 +1,56 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -398266,13 +401650,13 @@ index 0000000..8f37b82 +#include "emul-target.h" diff --git a/gas/config/itbl-mips.h b/gas/config/itbl-mips.h new file mode 100644 -index 0000000..90c83d1 +index 0000000..69f1dc4 --- /dev/null +++ b/gas/config/itbl-mips.h @@ -0,0 +1,46 @@ +/* itbl-mips.h + -+ Copyright 1997, 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 1997-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -398318,13 +401702,12 @@ index 0000000..90c83d1 +#define ITBL_NUM_MACROS M_NUM_MACROS diff --git a/gas/config/m68k-parse.h b/gas/config/m68k-parse.h new file mode 100644 -index 0000000..4f91385 +index 0000000..b4c0b5b --- /dev/null +++ b/gas/config/m68k-parse.h -@@ -0,0 +1,359 @@ +@@ -0,0 +1,358 @@ +/* m68k-parse.h -- header file for m68k assembler -+ Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000, -+ 2003, 2004, 2005, 2006, 2007, 2009 Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -398683,13 +402066,12 @@ index 0000000..4f91385 +extern int flag_reg_prefix_optional; diff --git a/gas/config/m68k-parse.y b/gas/config/m68k-parse.y new file mode 100644 -index 0000000..2c58266 +index 0000000..d5c59a1 --- /dev/null +++ b/gas/config/m68k-parse.y -@@ -0,0 +1,1119 @@ +@@ -0,0 +1,1118 @@ +/* m68k.y -- bison grammar for m68k operand parsing -+ Copyright 1995, 1996, 1997, 1998, 2001, 2003, 2004, 2005, 2007, 2009 -+ Free Software Foundation, Inc. ++ Copyright (C) 1995-2014 Free Software Foundation, Inc. + Written by Ken Raeburn and Ian Lance Taylor, Cygnus Support + + This file is part of GAS, the GNU Assembler. @@ -399808,14 +403190,12 @@ index 0000000..2c58266 +} diff --git a/gas/config/obj-aout.c b/gas/config/obj-aout.c new file mode 100644 -index 0000000..ce72135 +index 0000000..28369c0 --- /dev/null +++ b/gas/config/obj-aout.c -@@ -0,0 +1,345 @@ +@@ -0,0 +1,343 @@ +/* a.out object file format -+ Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1999, 2000, -+ 2001, 2002, 2003, 2004, 2005, 2007, 2009, 2010, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1989-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -400159,13 +403539,12 @@ index 0000000..ce72135 +}; diff --git a/gas/config/obj-aout.h b/gas/config/obj-aout.h new file mode 100644 -index 0000000..c4184d8 +index 0000000..784dae7 --- /dev/null +++ b/gas/config/obj-aout.h -@@ -0,0 +1,71 @@ +@@ -0,0 +1,70 @@ +/* obj-aout.h, a.out object file format for gas, the assembler. -+ Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 2000, -+ 2002, 2003, 2005, 2007, 2009 Free Software Foundation, Inc. ++ Copyright (C) 1989-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -400236,13 +403615,12 @@ index 0000000..c4184d8 +#define AOUT_STABS diff --git a/gas/config/obj-coff-seh.c b/gas/config/obj-coff-seh.c new file mode 100644 -index 0000000..83e8cb6 +index 0000000..ad3fc87 --- /dev/null +++ b/gas/config/obj-coff-seh.c -@@ -0,0 +1,1018 @@ +@@ -0,0 +1,1024 @@ +/* seh pdata/xdata coff object file format -+ Copyright 2009, 2010 -+ Free Software Foundation, Inc. ++ Copyright (C) 2009-2014 Free Software Foundation, Inc. + + This file is part of GAS. + @@ -400412,6 +403790,13 @@ index 0000000..83e8cb6 + return 0; +} + ++/* Switch back to the code section, whatever that may be. */ ++static void ++obj_coff_seh_code (int ignored ATTRIBUTE_UNUSED) ++{ ++ subseg_set (seh_ctx_cur->code_seg, 0); ++} ++ +static void +switch_xdata (int subseg, segT code_seg) +{ @@ -401260,13 +404645,12 @@ index 0000000..83e8cb6 +} diff --git a/gas/config/obj-coff-seh.h b/gas/config/obj-coff-seh.h new file mode 100644 -index 0000000..71c803f +index 0000000..cf49485 --- /dev/null +++ b/gas/config/obj-coff-seh.h -@@ -0,0 +1,205 @@ +@@ -0,0 +1,206 @@ +/* seh pdata/xdata coff object file format -+ Copyright 2009, 2010, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 2009-2014 Free Software Foundation, Inc. + + This file is part of GAS. + @@ -401323,6 +404707,7 @@ index 0000000..71c803f + .seh_savereg + .seh_savexmm + .seh_pushframe ++ .seh_code +*/ + +/* architecture specific pdata/xdata handling. */ @@ -401340,6 +404725,7 @@ index 0000000..71c803f + {"seh_32", obj_coff_seh_32, 1}, \ + {"seh_no32", obj_coff_seh_32, 0}, \ + {"seh_handler", obj_coff_seh_handler, 0}, \ ++ {"seh_code", obj_coff_seh_code, 0}, \ + {"seh_handlerdata", obj_coff_seh_handlerdata, 0}, + +/* Type definitions. */ @@ -401415,6 +404801,7 @@ index 0000000..71c803f +static void obj_coff_seh_proc (int); +static void obj_coff_seh_handler (int); +static void obj_coff_seh_handlerdata (int); ++static void obj_coff_seh_code (int); + +#define UNDSEC bfd_und_section_ptr + @@ -401468,17 +404855,14 @@ index 0000000..71c803f + PEX64_SCOPE_ENTRY_SIZE * (IDX)) + +#endif -+ diff --git a/gas/config/obj-coff.c b/gas/config/obj-coff.c new file mode 100644 -index 0000000..dbe2f07 +index 0000000..79c8f88 --- /dev/null +++ b/gas/config/obj-coff.c -@@ -0,0 +1,1957 @@ +@@ -0,0 +1,1955 @@ +/* coff object file format -+ Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, -+ 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2009, 2010 -+ Free Software Foundation, Inc. ++ Copyright (C) 1989-2014 Free Software Foundation, Inc. + + This file is part of GAS. + @@ -403434,14 +406818,12 @@ index 0000000..dbe2f07 +}; diff --git a/gas/config/obj-coff.h b/gas/config/obj-coff.h new file mode 100644 -index 0000000..ff5548e +index 0000000..dba6b63 --- /dev/null +++ b/gas/config/obj-coff.h -@@ -0,0 +1,415 @@ +@@ -0,0 +1,408 @@ +/* coff object file format -+ Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, -+ 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2009 -+ Free Software Foundation, Inc. ++ Copyright (C) 1989-2014 Free Software Foundation, Inc. + + This file is part of GAS. + @@ -403517,11 +406899,6 @@ index 0000000..ff5548e +#endif +#endif + -+#ifdef TC_OR32 -+#include "coff/or32.h" -+#define TARGET_FORMAT "coff-or32-big" -+#endif -+ +#ifdef TC_I960 +#include "coff/i960.h" +#define TARGET_FORMAT "coff-Intel-little" @@ -403855,13 +407232,12 @@ index 0000000..ff5548e +#endif /* OBJ_FORMAT_H */ diff --git a/gas/config/obj-ecoff.c b/gas/config/obj-ecoff.c new file mode 100644 -index 0000000..a3e5308 +index 0000000..3c1df47 --- /dev/null +++ b/gas/config/obj-ecoff.c -@@ -0,0 +1,320 @@ +@@ -0,0 +1,319 @@ +/* ECOFF object file format. -+ Copyright 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, 2002, -+ 2005, 2007, 2009, 2010 Free Software Foundation, Inc. ++ Copyright (C) 1993-2014 Free Software Foundation, Inc. + Contributed by Cygnus Support. + This file was put together by Ian Lance Taylor . + @@ -404181,13 +407557,12 @@ index 0000000..a3e5308 +}; diff --git a/gas/config/obj-ecoff.h b/gas/config/obj-ecoff.h new file mode 100644 -index 0000000..1d93dd9 +index 0000000..70cafdf --- /dev/null +++ b/gas/config/obj-ecoff.h -@@ -0,0 +1,78 @@ +@@ -0,0 +1,77 @@ +/* ECOFF object file format header file. -+ Copyright 1993, 1994, 1995, 1996, 1997, 1999, 2002, 2004, 2005, -+ 2007, 2009 Free Software Foundation, Inc. ++ Copyright (C) 1993-2014 Free Software Foundation, Inc. + Contributed by Cygnus Support. + Written by Ian Lance Taylor . + @@ -404265,14 +407640,12 @@ index 0000000..1d93dd9 +extern void obj_ecoff_set_ext (symbolS *, EXTR *); diff --git a/gas/config/obj-elf.c b/gas/config/obj-elf.c new file mode 100644 -index 0000000..3377261 +index 0000000..e406f7b --- /dev/null +++ b/gas/config/obj-elf.c -@@ -0,0 +1,2626 @@ +@@ -0,0 +1,2681 @@ +/* ELF object file format -+ Copyright 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, -+ 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1992-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -405731,6 +409104,62 @@ index 0000000..3377261 +} +#define skip_past_comma(str) skip_past_char (str, ',') + ++/* A list of attributes that have been explicitly set by the assembly code. ++ VENDOR is the vendor id, BASE is the tag shifted right by the number ++ of bits in MASK, and bit N of MASK is set if tag BASE+N has been set. */ ++struct recorded_attribute_info { ++ struct recorded_attribute_info *next; ++ int vendor; ++ unsigned int base; ++ unsigned long mask; ++}; ++static struct recorded_attribute_info *recorded_attributes; ++ ++/* Record that we have seen an explicit specification of attribute TAG ++ for vendor VENDOR. */ ++ ++static void ++record_attribute (int vendor, unsigned int tag) ++{ ++ unsigned int base; ++ unsigned long mask; ++ struct recorded_attribute_info *rai; ++ ++ base = tag / (8 * sizeof (rai->mask)); ++ mask = 1UL << (tag % (8 * sizeof (rai->mask))); ++ for (rai = recorded_attributes; rai; rai = rai->next) ++ if (rai->vendor == vendor && rai->base == base) ++ { ++ rai->mask |= mask; ++ return; ++ } ++ ++ rai = XNEW (struct recorded_attribute_info); ++ rai->next = recorded_attributes; ++ rai->vendor = vendor; ++ rai->base = base; ++ rai->mask = mask; ++ recorded_attributes = rai; ++} ++ ++/* Return true if we have seen an explicit specification of attribute TAG ++ for vendor VENDOR. */ ++ ++bfd_boolean ++obj_elf_seen_attribute (int vendor, unsigned int tag) ++{ ++ unsigned int base; ++ unsigned long mask; ++ struct recorded_attribute_info *rai; ++ ++ base = tag / (8 * sizeof (rai->mask)); ++ mask = 1UL << (tag % (8 * sizeof (rai->mask))); ++ for (rai = recorded_attributes; rai; rai = rai->next) ++ if (rai->vendor == vendor && rai->base == base) ++ return (rai->mask & mask) != 0; ++ return FALSE; ++} ++ +/* Parse an attribute directive for VENDOR. + Returns the attribute number read, or zero on error. */ + @@ -405813,6 +409242,7 @@ index 0000000..3377261 + s = demand_copy_C_string (&len); + } + ++ record_attribute (vendor, tag); + switch (type & 3) + { + case 3: @@ -406897,14 +410327,12 @@ index 0000000..3377261 +}; diff --git a/gas/config/obj-elf.h b/gas/config/obj-elf.h new file mode 100644 -index 0000000..d4fd4d5 +index 0000000..3f8f8f4 --- /dev/null +++ b/gas/config/obj-elf.h @@ -0,0 +1,252 @@ +/* ELF object file format. -+ Copyright 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, -+ 2002, 2003, 2004, 2005, 2006, 2007, 2009, 2010, 2011 -+ Free Software Foundation, Inc. ++ Copyright (C) 1992-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -407070,6 +410498,8 @@ index 0000000..d4fd4d5 + (const char *, int, bfd_vma, int, const char *, int, int); +extern struct fix *obj_elf_vtable_inherit (int); +extern struct fix *obj_elf_vtable_entry (int); ++extern bfd_boolean obj_elf_seen_attribute ++ (int, unsigned int); +extern int obj_elf_vendor_attribute (int); + +/* BFD wants to write the udata field, which is a no-no for the @@ -407155,13 +410585,12 @@ index 0000000..d4fd4d5 +#endif /* _OBJ_ELF_H */ diff --git a/gas/config/obj-evax.c b/gas/config/obj-evax.c new file mode 100644 -index 0000000..2fda63d +index 0000000..a38269c --- /dev/null +++ b/gas/config/obj-evax.c -@@ -0,0 +1,525 @@ +@@ -0,0 +1,524 @@ +/* obj-evax.c - EVAX (openVMS/Alpha) object file format. -+ Copyright 1996, 1997, 2005, 2007, 2008, 2009, 2010, 2011, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1996-2014 Free Software Foundation, Inc. + Contributed by Klaus Kämpf (kkaempf@progis.de) of + proGIS Software, Aachen, Germany. + Extensively enhanced by Douglas Rupp of AdaCore. @@ -407686,13 +411115,12 @@ index 0000000..2fda63d +/* end of obj-evax.c */ diff --git a/gas/config/obj-evax.h b/gas/config/obj-evax.h new file mode 100644 -index 0000000..b7520b7 +index 0000000..c1fc9be --- /dev/null +++ b/gas/config/obj-evax.h -@@ -0,0 +1,112 @@ +@@ -0,0 +1,111 @@ +/* This file is obj-evax.h -+ Copyright 1996, 2000, 2005, 2007, 2009, 2010 -+ Free Software Foundation, Inc. ++ Copyright (C) 1996-2014 Free Software Foundation, Inc. + Contributed by Klaus Kämpf (kkaempf@progis.de) of + proGIS Software, Aachen, Germany. + @@ -407804,12 +411232,11 @@ index 0000000..b7520b7 + */ diff --git a/gas/config/obj-fdpicelf.c b/gas/config/obj-fdpicelf.c new file mode 100644 -index 0000000..8a486b0 +index 0000000..13d945d --- /dev/null +++ b/gas/config/obj-fdpicelf.c -@@ -0,0 +1,21 @@ -+/* Copyright 20012 -+ Free Software Foundation, Inc. +@@ -0,0 +1,20 @@ ++/* Copyright (C) 2012-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -407831,12 +411258,11 @@ index 0000000..8a486b0 +#include "obj-elf.c" diff --git a/gas/config/obj-fdpicelf.h b/gas/config/obj-fdpicelf.h new file mode 100644 -index 0000000..e91acda +index 0000000..6da1ef2 --- /dev/null +++ b/gas/config/obj-fdpicelf.h -@@ -0,0 +1,22 @@ -+/* Copyright 20012 -+ Free Software Foundation, Inc. +@@ -0,0 +1,21 @@ ++/* Copyright (C) 2012-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -407859,12 +411285,12 @@ index 0000000..e91acda +#include "obj-elf.h" diff --git a/gas/config/obj-macho.c b/gas/config/obj-macho.c new file mode 100644 -index 0000000..21281a0 +index 0000000..ec29847 --- /dev/null +++ b/gas/config/obj-macho.c @@ -0,0 +1,1990 @@ +/* Mach-O object file format -+ Copyright 2009, 2011, 2012 Free Software Foundation, Inc. ++ Copyright (C) 2009-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -409855,12 +413281,12 @@ index 0000000..21281a0 +} diff --git a/gas/config/obj-macho.h b/gas/config/obj-macho.h new file mode 100644 -index 0000000..92cb8ef +index 0000000..632fb8d --- /dev/null +++ b/gas/config/obj-macho.h @@ -0,0 +1,119 @@ +/* Mach-O object file format for gas, the assembler. -+ Copyright 2009, 2011, 2012 Free Software Foundation, Inc. ++ Copyright (C) 2009-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -409980,11 +413406,11 @@ index 0000000..92cb8ef +#endif /* _OBJ_MACH_O_H */ diff --git a/gas/config/obj-multi.c b/gas/config/obj-multi.c new file mode 100644 -index 0000000..0741137 +index 0000000..8c78d62 --- /dev/null +++ b/gas/config/obj-multi.c @@ -0,0 +1,23 @@ -+/* Copyright 2007, 2009 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -410009,13 +413435,12 @@ index 0000000..0741137 + diff --git a/gas/config/obj-multi.h b/gas/config/obj-multi.h new file mode 100644 -index 0000000..353162e +index 0000000..e656e2c --- /dev/null +++ b/gas/config/obj-multi.h -@@ -0,0 +1,174 @@ +@@ -0,0 +1,173 @@ +/* Multiple object format emulation. -+ Copyright 1995, 1996, 1997, 1999, 2000, 2002, 2004, 2005, 2007, 2009, 2010 -+ Free Software Foundation, Inc. ++ Copyright (C) 1995-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -410189,13 +413614,12 @@ index 0000000..353162e +#endif /* _OBJ_MULTI_H */ diff --git a/gas/config/obj-som.c b/gas/config/obj-som.c new file mode 100644 -index 0000000..9598e10 +index 0000000..47acab8 --- /dev/null +++ b/gas/config/obj-som.c -@@ -0,0 +1,329 @@ +@@ -0,0 +1,328 @@ +/* SOM object file format. -+ Copyright 1993, 1994, 1998, 2000, 2002, 2003, 2004, 2005, 2006, -+ 2007, 2008, 2009 Free Software Foundation, Inc. ++ Copyright (C) 1993-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -410524,13 +413948,12 @@ index 0000000..9598e10 +}; diff --git a/gas/config/obj-som.h b/gas/config/obj-som.h new file mode 100644 -index 0000000..9fac3c2 +index 0000000..bb2aead --- /dev/null +++ b/gas/config/obj-som.h -@@ -0,0 +1,75 @@ +@@ -0,0 +1,74 @@ +/* SOM object file format. -+ Copyright 1993, 1994, 1995, 1998, 2000, 2004, 2005, 2006, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1993-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -410605,13 +414028,12 @@ index 0000000..9fac3c2 +#endif /* _OBJ_SOM_H */ diff --git a/gas/config/rl78-defs.h b/gas/config/rl78-defs.h new file mode 100644 -index 0000000..ebe19a9 +index 0000000..0af8874 --- /dev/null +++ b/gas/config/rl78-defs.h -@@ -0,0 +1,50 @@ +@@ -0,0 +1,52 @@ +/* rl78-defs.h Renesas RL78 internal definitions -+ Copyright 2008, 2009 -+ Free Software Foundation, Inc. ++ Copyright (C) 2008-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -410637,6 +414059,9 @@ index 0000000..ebe19a9 +#define RL78REL_DATA 0 +#define RL78REL_PCREL 1 + ++#define RL78_RELAX_NONE 0 ++#define RL78_RELAX_BRANCH 1 ++ +extern int rl78_error (const char *); +extern void rl78_lex_init (char *, char *); +extern void rl78_prefix (int); @@ -410661,12 +414086,12 @@ index 0000000..ebe19a9 +#endif diff --git a/gas/config/rl78-parse.y b/gas/config/rl78-parse.y new file mode 100644 -index 0000000..1f01920 +index 0000000..e358a27 --- /dev/null +++ b/gas/config/rl78-parse.y @@ -0,0 +1,1598 @@ +/* rl78-parse.y Renesas RL78 parser -+ Copyright 2011-2013 Free Software Foundation, Inc. ++ Copyright (C) 2011-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -410957,22 +414382,22 @@ index 0000000..1f01920 +/* ---------------------------------------------------------------------- */ + + | BC '$' EXPR -+ { B1 (0xdc); PC1 ($3); } ++ { B1 (0xdc); PC1 ($3); rl78_relax (RL78_RELAX_BRANCH, 0); } + + | BNC '$' EXPR -+ { B1 (0xde); PC1 ($3); } ++ { B1 (0xde); PC1 ($3); rl78_relax (RL78_RELAX_BRANCH, 0); } + + | BZ '$' EXPR -+ { B1 (0xdd); PC1 ($3); } ++ { B1 (0xdd); PC1 ($3); rl78_relax (RL78_RELAX_BRANCH, 0); } + + | BNZ '$' EXPR -+ { B1 (0xdf); PC1 ($3); } ++ { B1 (0xdf); PC1 ($3); rl78_relax (RL78_RELAX_BRANCH, 0); } + + | BH '$' EXPR -+ { B2 (0x61, 0xc3); PC1 ($3); } ++ { B2 (0x61, 0xc3); PC1 ($3); rl78_relax (RL78_RELAX_BRANCH, 0); } + + | BNH '$' EXPR -+ { B2 (0x61, 0xd3); PC1 ($3); } ++ { B2 (0x61, 0xd3); PC1 ($3); rl78_relax (RL78_RELAX_BRANCH, 0); } + +/* ---------------------------------------------------------------------- */ + @@ -411820,12 +415245,12 @@ index 0000000..1f01920 + ; + +andor1 : AND1 { $$ = 0x05; rl78_bit_insn = 1; } -+ | OR1 { $$ = 0x06; rl78_bit_insn = 1;} ++ | OR1 { $$ = 0x06; rl78_bit_insn = 1; } + | XOR1 { $$ = 0x07; rl78_bit_insn = 1; } + ; + -+bt_bf : BT { $$ = 0x02; rl78_bit_insn = 1;} -+ | BF { $$ = 0x04; rl78_bit_insn = 1; } ++bt_bf : BT { $$ = 0x02; rl78_bit_insn = 1; rl78_relax (RL78_RELAX_BRANCH, 0); } ++ | BF { $$ = 0x04; rl78_bit_insn = 1; rl78_relax (RL78_RELAX_BRANCH, 0); } + | BTCLR { $$ = 0x00; rl78_bit_insn = 1; } + ; + @@ -412265,12 +415690,12 @@ index 0000000..1f01920 + diff --git a/gas/config/rx-defs.h b/gas/config/rx-defs.h new file mode 100644 -index 0000000..78ab4df +index 0000000..93c4fa9 --- /dev/null +++ b/gas/config/rx-defs.h @@ -0,0 +1,69 @@ +/* rx-defs.h Renesas RX internal definitions -+ Copyright 2008-2013 Free Software Foundation, Inc. ++ Copyright (C) 2008-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -412340,12 +415765,12 @@ index 0000000..78ab4df +#endif /* RX_DEFS_H */ diff --git a/gas/config/rx-parse.y b/gas/config/rx-parse.y new file mode 100644 -index 0000000..3933e6b +index 0000000..c4cba9f --- /dev/null +++ b/gas/config/rx-parse.y @@ -0,0 +1,1641 @@ +/* rx-parse.y Renesas RX parser -+ Copyright 2008-2013 Free Software Foundation, Inc. ++ Copyright (C) 2008-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -413987,14 +417412,13 @@ index 0000000..3933e6b +} diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c new file mode 100644 -index 0000000..4b243ce +index 0000000..67c0871 --- /dev/null +++ b/gas/config/tc-aarch64.c -@@ -0,0 +1,7577 @@ +@@ -0,0 +1,7615 @@ +/* tc-aarch64.c -- Assemble for the AArch64 ISA + -+ Copyright 2009, 2010, 2011, 2012, 2013 -+ Free Software Foundation, Inc. ++ Copyright (C) 2009-2014 Free Software Foundation, Inc. + Contributed by ARM Ltd. + + This file is part of GAS. @@ -414429,9 +417853,16 @@ index 0000000..4b243ce + and per-sub-section basis. */ + +#define MAX_LITERAL_POOL_SIZE 1024 ++typedef struct literal_expression ++{ ++ expressionS exp; ++ /* If exp.op == O_big then this bignum holds a copy of the global bignum value. */ ++ LITTLENUM_TYPE * bignum; ++} literal_expression; ++ +typedef struct literal_pool +{ -+ expressionS literals[MAX_LITERAL_POOL_SIZE]; ++ literal_expression literals[MAX_LITERAL_POOL_SIZE]; + unsigned int next_free_entry; + unsigned int id; + symbolS *symbol; @@ -415610,17 +419041,19 @@ index 0000000..4b243ce + /* Check if this literal value is already in the pool. */ + for (entry = 0; entry < pool->next_free_entry; entry++) + { -+ if ((pool->literals[entry].X_op == exp->X_op) ++ expressionS * litexp = & pool->literals[entry].exp; ++ ++ if ((litexp->X_op == exp->X_op) + && (exp->X_op == O_constant) -+ && (pool->literals[entry].X_add_number == exp->X_add_number) -+ && (pool->literals[entry].X_unsigned == exp->X_unsigned)) ++ && (litexp->X_add_number == exp->X_add_number) ++ && (litexp->X_unsigned == exp->X_unsigned)) + break; + -+ if ((pool->literals[entry].X_op == exp->X_op) ++ if ((litexp->X_op == exp->X_op) + && (exp->X_op == O_symbol) -+ && (pool->literals[entry].X_add_number == exp->X_add_number) -+ && (pool->literals[entry].X_add_symbol == exp->X_add_symbol) -+ && (pool->literals[entry].X_op_symbol == exp->X_op_symbol)) ++ && (litexp->X_add_number == exp->X_add_number) ++ && (litexp->X_add_symbol == exp->X_add_symbol) ++ && (litexp->X_op_symbol == exp->X_op_symbol)) + break; + } + @@ -415633,8 +419066,18 @@ index 0000000..4b243ce + return FALSE; + } + -+ pool->literals[entry] = *exp; ++ pool->literals[entry].exp = *exp; + pool->next_free_entry += 1; ++ if (exp->X_op == O_big) ++ { ++ /* PR 16688: Bignums are held in a single global array. We must ++ copy and preserve that value now, before it is overwritten. */ ++ pool->literals[entry].bignum = xmalloc (CHARS_PER_LITTLENUM * exp->X_add_number); ++ memcpy (pool->literals[entry].bignum, generic_bignum, ++ CHARS_PER_LITTLENUM * exp->X_add_number); ++ } ++ else ++ pool->literals[entry].bignum = NULL; + } + + exp->X_op = O_symbol; @@ -415728,8 +419171,26 @@ index 0000000..4b243ce + symbol_table_insert (pool->symbol); + + for (entry = 0; entry < pool->next_free_entry; entry++) -+ /* First output the expression in the instruction to the pool. */ -+ emit_expr (&(pool->literals[entry]), size); /* .word|.xword */ ++ { ++ expressionS * exp = & pool->literals[entry].exp; ++ ++ if (exp->X_op == O_big) ++ { ++ /* PR 16688: Restore the global bignum value. */ ++ gas_assert (pool->literals[entry].bignum != NULL); ++ memcpy (generic_bignum, pool->literals[entry].bignum, ++ CHARS_PER_LITTLENUM * exp->X_add_number); ++ } ++ ++ /* First output the expression in the instruction to the pool. */ ++ emit_expr (exp, size); /* .word|.xword */ ++ ++ if (exp->X_op == O_big) ++ { ++ free (pool->literals[entry].bignum); ++ pool->literals[entry].bignum = NULL; ++ } ++ } + + /* Mark the pool as empty. */ + pool->next_free_entry = 0; @@ -416809,7 +420270,7 @@ index 0000000..4b243ce + if (**str == '\0') + return TRUE; + -+ /* Otherwise, we have a shifted reloc modifier, so rewind to ++ /* Otherwise, we have a shifted reloc modifier, so rewind to + recover the variable name and continue parsing for the shifter. */ + *str = p; + return parse_shifter_operand_imm (str, operand, mode); @@ -417510,9 +420971,9 @@ index 0000000..4b243ce + +/* Diagnostics on operands errors. */ + -+/* By default, output one-line error message only. -+ Enable the verbose error message by -merror-verbose. */ -+static int verbose_error_p = 0; ++/* By default, output verbose error message. ++ Disable the verbose error message by -mno-verbose-error. */ ++static int verbose_error_p = 1; + +#ifdef DEBUG_AARCH64 +/* N.B. this is only for the purpose of debugging. */ @@ -421112,6 +424573,8 @@ index 0000000..4b243ce +#endif /* DEBUG_AARCH64 */ + {"mverbose-error", N_("output verbose error messages"), &verbose_error_p, 1, + NULL}, ++ {"mno-verbose-error", N_("do not output verbose error messages"), ++ &verbose_error_p, 0, NULL}, + {NULL, NULL, NULL, 0, NULL} +}; + @@ -421570,12 +425033,12 @@ index 0000000..4b243ce +} diff --git a/gas/config/tc-aarch64.h b/gas/config/tc-aarch64.h new file mode 100644 -index 0000000..74a81d6 +index 0000000..94a3dc9 --- /dev/null +++ b/gas/config/tc-aarch64.h @@ -0,0 +1,234 @@ +/* tc-aarch64.h -- Header file for tc-aarch64.c. -+ Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc. ++ Copyright (C) 2009-2014 Free Software Foundation, Inc. + Contributed by ARM Ltd. + + This file is part of GAS. @@ -421690,7 +425153,7 @@ index 0000000..74a81d6 + || (FIX)->fx_r_type == BFD_RELOC_32 \ + || TC_FORCE_RELOCATION (FIX)) + -+#define TC_CONS_FIX_NEW cons_fix_new_aarch64 ++#define TC_CONS_FIX_NEW(f,w,s,e,r) cons_fix_new_aarch64 ((f), (w), (s), (e)) + +/* Max code alignment is 32 bytes */ +#define MAX_MEM_FOR_RS_ALIGN_CODE 31 @@ -421810,14 +425273,12 @@ index 0000000..74a81d6 +#endif /* TC_AARCH64 */ diff --git a/gas/config/tc-alpha.c b/gas/config/tc-alpha.c new file mode 100644 -index 0000000..d020896 +index 0000000..ea6aa19 --- /dev/null +++ b/gas/config/tc-alpha.c -@@ -0,0 +1,6371 @@ +@@ -0,0 +1,6369 @@ +/* tc-alpha.c - Processor-specific code for the DEC Alpha AXP CPU. -+ Copyright 1989, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, -+ 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009, 2010 -+ Free Software Foundation, Inc. ++ Copyright (C) 1989-2014 Free Software Foundation, Inc. + Contributed by Carnegie Mellon University, 1993. + Written by Alessandro Forin, based on earlier gas-1.38 target CPU files. + Modified by Ken Raeburn for gas-2.x and ECOFF support. @@ -428187,14 +431648,12 @@ index 0000000..d020896 +#include "config/atof-vax.c" diff --git a/gas/config/tc-alpha.h b/gas/config/tc-alpha.h new file mode 100644 -index 0000000..284c1e4 +index 0000000..98f81f5 --- /dev/null +++ b/gas/config/tc-alpha.h -@@ -0,0 +1,187 @@ +@@ -0,0 +1,186 @@ +/* This file is tc-alpha.h -+ Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 -+ 2005, 2006, 2007, 2009 -+ Free Software Foundation, Inc. ++ Copyright (C) 1994-2014 Free Software Foundation, Inc. + Written by Ken Raeburn . + + This file is part of GAS, the GNU Assembler. @@ -428266,7 +431725,8 @@ index 0000000..284c1e4 + +#define tc_canonicalize_symbol_name evax_shorten_name + -+#define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) \ ++#define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP,RELOC) \ ++ (void) RELOC, \ + fix_new_exp (FRAG, OFF, (int)LEN, EXP, 0, \ + LEN == 2 ? BFD_RELOC_16 \ + : LEN == 4 ? BFD_RELOC_32 \ @@ -428380,13 +431840,12 @@ index 0000000..284c1e4 +#define DWARF2_CIE_DATA_ALIGNMENT (-8) diff --git a/gas/config/tc-arc.c b/gas/config/tc-arc.c new file mode 100644 -index 0000000..8d2da96 +index 0000000..5499d88 --- /dev/null +++ b/gas/config/tc-arc.c -@@ -0,0 +1,1896 @@ +@@ -0,0 +1,1897 @@ +/* tc-arc.c -- Assembler for the ARC -+ Copyright 1994, 1995, 1997, 1999, 2000, 2001, 2002, 2003, 2004, 2005, -+ 2006, 2007, 2009, 2011 Free Software Foundation, Inc. ++ Copyright (C) 1994-2014 Free Software Foundation, Inc. + Contributed by Doug Evans (dje@cygnus.com). + + This file is part of GAS, the GNU Assembler. @@ -429547,7 +433006,7 @@ index 0000000..8d2da96 + Values for the status register are specified with %st(label). + `label' will be right shifted by 2. */ + -+void ++bfd_reloc_code_real_type +arc_parse_cons_expression (expressionS *exp, + unsigned int nbytes ATTRIBUTE_UNUSED) +{ @@ -429566,6 +433025,7 @@ index 0000000..8d2da96 + arc_code_symbol (exp); + input_line_pointer = p; + } ++ return BFD_RELOC_NONE; +} + +/* Record a fixup for a cons expression. */ @@ -429574,7 +433034,8 @@ index 0000000..8d2da96 +arc_cons_fix_new (fragS *frag, + int where, + int nbytes, -+ expressionS *exp) ++ expressionS *exp, ++ bfd_reloc_code_real_type r ATTRIBUTE_UNUSED) +{ + if (nbytes == 4) + { @@ -430282,13 +433743,12 @@ index 0000000..8d2da96 +} diff --git a/gas/config/tc-arc.h b/gas/config/tc-arc.h new file mode 100644 -index 0000000..26c0d5f +index 0000000..a2789e6 --- /dev/null +++ b/gas/config/tc-arc.h -@@ -0,0 +1,73 @@ +@@ -0,0 +1,74 @@ +/* tc-arc.h - Macros and type defines for the ARC. -+ Copyright 1994, 1995, 1997, 2000, 2001, 2002, 2005, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1994-2014 Free Software Foundation, Inc. + Contributed by Doug Evans (dje@cygnus.com). + + This file is part of GAS, the GNU Assembler. @@ -430343,13 +433803,15 @@ index 0000000..26c0d5f + +/* The ARC needs to parse reloc specifiers in .word. */ + -+extern void arc_parse_cons_expression (struct expressionS *, unsigned); ++extern bfd_reloc_code_real_type arc_parse_cons_expression (struct expressionS *, ++ unsigned); +#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) \ + arc_parse_cons_expression (EXP, NBYTES) + -+extern void arc_cons_fix_new (struct frag *, int, int, struct expressionS *); -+#define TC_CONS_FIX_NEW(FRAG, WHERE, NBYTES, EXP) \ -+ arc_cons_fix_new (FRAG, WHERE, NBYTES, EXP) ++extern void arc_cons_fix_new (struct frag *, int, int, struct expressionS *, ++ bfd_reloc_code_real_type); ++#define TC_CONS_FIX_NEW(FRAG, WHERE, NBYTES, EXP, RELOC) \ ++ arc_cons_fix_new (FRAG, WHERE, NBYTES, EXP, RELOC) + +#define DWARF2_LINE_MIN_INSN_LENGTH 4 + @@ -430361,12 +433823,12 @@ index 0000000..26c0d5f +#define EXTERN_FORCE_RELOC 0 diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c new file mode 100644 -index 0000000..08b5ea2 +index 0000000..590855c --- /dev/null +++ b/gas/config/tc-arm.c -@@ -0,0 +1,25206 @@ +@@ -0,0 +1,25383 @@ +/* tc-arm.c -- Assemble for the ARM -+ Copyright 1994-2013 Free Software Foundation, Inc. ++ Copyright (C) 1994-2014 Free Software Foundation, Inc. + Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) + Modified by David Taylor (dtaylor@armltd.co.uk) + Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com) @@ -430504,6 +433966,8 @@ index 0000000..08b5ea2 +/* Warn on using deprecated features. */ +static int warn_on_deprecated = TRUE; + ++/* Understand CodeComposer Studio assembly syntax. */ ++bfd_boolean codecomposer_syntax = FALSE; + +/* Variables that we set while parsing command-line options. Once all + options have been read we re-process these values to set the real @@ -431162,6 +434626,15 @@ index 0000000..08b5ea2 +/* Pointer to a linked list of literal pools. */ +literal_pool * list_of_pools = NULL; + ++typedef enum asmfunc_states ++{ ++ OUTSIDE_ASMFUNC, ++ WAITING_ASMFUNC_NAME, ++ WAITING_ENDASMFUNC ++} asmfunc_states; ++ ++static asmfunc_states asmfunc_state = OUTSIDE_ASMFUNC; ++ +#ifdef OBJ_ELF +# define now_it seg_info (now_seg)->tc_segment_info_data.current_it +#else @@ -431220,7 +434693,7 @@ index 0000000..08b5ea2 + +/* This array holds the chars that always start a comment. If the + pre-processor is disabled, these aren't very useful. */ -+const char comment_chars[] = "@"; ++char arm_comment_chars[] = "@"; + +/* This array holds the chars that only start a comment at the beginning of + a line. If the line seems to have the form '# 123 filename' @@ -431231,7 +434704,7 @@ index 0000000..08b5ea2 +/* Also note that comments like this one will always work. */ +const char line_comment_chars[] = "#"; + -+const char line_separator_chars[] = ";"; ++char arm_line_separator_chars[] = ";"; + +/* Chars that can be used to separate mant + from exp in floating point numbers. */ @@ -433379,6 +436852,104 @@ index 0000000..08b5ea2 + demand_empty_rest_of_line (); +} + ++/* Directives: CodeComposer Studio. */ ++ ++/* .ref (for CodeComposer Studio syntax only). */ ++static void ++s_ccs_ref (int unused ATTRIBUTE_UNUSED) ++{ ++ if (codecomposer_syntax) ++ ignore_rest_of_line (); ++ else ++ as_bad (_(".ref pseudo-op only available with -mccs flag.")); ++} ++ ++/* If name is not NULL, then it is used for marking the beginning of a ++ function, wherease if it is NULL then it means the function end. */ ++static void ++asmfunc_debug (const char * name) ++{ ++ static const char * last_name = NULL; ++ ++ if (name != NULL) ++ { ++ gas_assert (last_name == NULL); ++ last_name = name; ++ ++ if (debug_type == DEBUG_STABS) ++ stabs_generate_asm_func (name, name); ++ } ++ else ++ { ++ gas_assert (last_name != NULL); ++ ++ if (debug_type == DEBUG_STABS) ++ stabs_generate_asm_endfunc (last_name, last_name); ++ ++ last_name = NULL; ++ } ++} ++ ++static void ++s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED) ++{ ++ if (codecomposer_syntax) ++ { ++ switch (asmfunc_state) ++ { ++ case OUTSIDE_ASMFUNC: ++ asmfunc_state = WAITING_ASMFUNC_NAME; ++ break; ++ ++ case WAITING_ASMFUNC_NAME: ++ as_bad (_(".asmfunc repeated.")); ++ break; ++ ++ case WAITING_ENDASMFUNC: ++ as_bad (_(".asmfunc without function.")); ++ break; ++ } ++ demand_empty_rest_of_line (); ++ } ++ else ++ as_bad (_(".asmfunc pseudo-op only available with -mccs flag.")); ++} ++ ++static void ++s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED) ++{ ++ if (codecomposer_syntax) ++ { ++ switch (asmfunc_state) ++ { ++ case OUTSIDE_ASMFUNC: ++ as_bad (_(".endasmfunc without a .asmfunc.")); ++ break; ++ ++ case WAITING_ASMFUNC_NAME: ++ as_bad (_(".endasmfunc without function.")); ++ break; ++ ++ case WAITING_ENDASMFUNC: ++ asmfunc_state = OUTSIDE_ASMFUNC; ++ asmfunc_debug (NULL); ++ break; ++ } ++ demand_empty_rest_of_line (); ++ } ++ else ++ as_bad (_(".endasmfunc pseudo-op only available with -mccs flag.")); ++} ++ ++static void ++s_ccs_def (int name) ++{ ++ if (codecomposer_syntax) ++ s_globl (name); ++ else ++ as_bad (_(".def pseudo-op only available with -mccs flag.")); ++} ++ +/* Directives: Literal pools. */ + +static literal_pool * @@ -433495,6 +437066,32 @@ index 0000000..08b5ea2 + return SUCCESS; +} + ++bfd_boolean ++tc_start_label_without_colon (char unused1 ATTRIBUTE_UNUSED, const char * rest) ++{ ++ bfd_boolean ret = TRUE; ++ ++ if (codecomposer_syntax && asmfunc_state == WAITING_ASMFUNC_NAME) ++ { ++ const char *label = rest; ++ ++ while (!is_end_of_line[(int) label[-1]]) ++ --label; ++ ++ if (*label == '.') ++ { ++ as_bad (_("Invalid label '%s'"), label); ++ ret = FALSE; ++ } ++ ++ asmfunc_debug (label); ++ ++ asmfunc_state = WAITING_ENDASMFUNC; ++ } ++ ++ return ret; ++} ++ +/* Can't use symbol_new here, so have to create a symbol and then at + a later date assign it a value. Thats what these functions do. */ + @@ -433560,8 +437157,6 @@ index 0000000..08b5ea2 + || pool->next_free_entry == 0) + return; + -+ mapping_state (MAP_DATA); -+ + /* Align pool as you have word accesses. + Only make a frag if we have to. */ + if (!need_pass_2) @@ -433569,6 +437164,10 @@ index 0000000..08b5ea2 + + record_alignment (now_seg, 2); + ++#ifdef OBJ_ELF ++ seg_info (now_seg)->tc_segment_info_data.mapstate = MAP_DATA; ++ make_mapping_symbol (MAP_DATA, (valueT) frag_now_fix (), frag_now); ++#endif + sprintf (sym_name, "$$lit_\002%x", pool->id); + + symbol_locate (pool->symbol, sym_name, now_seg, @@ -434501,15 +438100,24 @@ index 0000000..08b5ea2 + s_arm_unwind_save_fpa (reg->number); + return; + -+ case REG_TYPE_RN: s_arm_unwind_save_core (); return; ++ case REG_TYPE_RN: ++ s_arm_unwind_save_core (); ++ return; ++ + case REG_TYPE_VFD: + if (arch_v6) + s_arm_unwind_save_vfp_armv6 (); + else + s_arm_unwind_save_vfp (); + return; -+ case REG_TYPE_MMXWR: s_arm_unwind_save_mmxwr (); return; -+ case REG_TYPE_MMXWCG: s_arm_unwind_save_mmxwcg (); return; ++ ++ case REG_TYPE_MMXWR: ++ s_arm_unwind_save_mmxwr (); ++ return; ++ ++ case REG_TYPE_MMXWCG: ++ s_arm_unwind_save_mmxwcg (); ++ return; + + default: + as_bad (_(".unwind_save does not support this kind of register")); @@ -434844,6 +438452,13 @@ index 0000000..08b5ea2 +#ifdef TE_PE + {"secrel32", pe_directive_secrel, 0}, +#endif ++ ++ /* These are for compatibility with CodeComposer Studio. */ ++ {"ref", s_ccs_ref, 0}, ++ {"def", s_ccs_def, 0}, ++ {"asmfunc", s_ccs_asmfunc, 0}, ++ {"endasmfunc", s_ccs_endasmfunc, 0}, ++ + { 0, 0, 0 } +}; + @@ -445038,7 +448653,7 @@ index 0000000..08b5ea2 + { + case neon_cvt_flavour_s32_f64: + sz = 1; -+ op = 0; ++ op = 1; + break; + case neon_cvt_flavour_s32_f32: + sz = 0; @@ -451208,7 +454823,7 @@ index 0000000..08b5ea2 + +/* Start an unwind table entry. HAVE_DATA is nonzero if we have additional + personality routine data. Returns zero, or the index table value for -+ and inline entry. */ ++ an inline entry. */ + +static valueT +create_unwind_entry (int have_data) @@ -451279,7 +454894,12 @@ index 0000000..08b5ea2 + } + else + { -+ gas_assert (unwind.personality_index == -1); ++ /* PR 16765: Missing or misplaced unwind directives can trigger this. */ ++ if (unwind.personality_index != -1) ++ { ++ as_bad (_("attempt to recreate an unwind entry")); ++ return 1; ++ } + + /* An extra byte is required for the opcode count. */ + size = unwind.opcode_count + 1; @@ -451386,11 +455006,19 @@ index 0000000..08b5ea2 +tc_arm_regname_to_dw2regnum (char *regname) +{ + int reg = arm_reg_parse (®name, REG_TYPE_RN); ++ if (reg != FAIL) ++ return reg; + -+ if (reg == FAIL) -+ return -1; ++ /* PR 16694: Allow VFP registers as well. */ ++ reg = arm_reg_parse (®name, REG_TYPE_VFS); ++ if (reg != FAIL) ++ return 64 + reg; + -+ return reg; ++ reg = arm_reg_parse (®name, REG_TYPE_VFD); ++ if (reg != FAIL) ++ return reg + 256; ++ ++ return -1; +} + +#ifdef TE_PE @@ -453362,9 +456990,9 @@ index 0000000..08b5ea2 +cons_fix_new_arm (fragS * frag, + int where, + int size, -+ expressionS * exp) ++ expressionS * exp, ++ bfd_reloc_code_real_type reloc) +{ -+ bfd_reloc_code_real_type type; + int pcrel = 0; + + /* Pick a reloc. @@ -453372,17 +457000,17 @@ index 0000000..08b5ea2 + switch (size) + { + case 1: -+ type = BFD_RELOC_8; ++ reloc = BFD_RELOC_8; + break; + case 2: -+ type = BFD_RELOC_16; ++ reloc = BFD_RELOC_16; + break; + case 4: + default: -+ type = BFD_RELOC_32; ++ reloc = BFD_RELOC_32; + break; + case 8: -+ type = BFD_RELOC_64; ++ reloc = BFD_RELOC_64; + break; + } + @@ -453390,11 +457018,11 @@ index 0000000..08b5ea2 + if (exp->X_op == O_secrel) + { + exp->X_op = O_symbol; -+ type = BFD_RELOC_32_SECREL; ++ reloc = BFD_RELOC_32_SECREL; + } +#endif + -+ fix_new_exp (frag, where, (int) size, exp, pcrel, type); ++ fix_new_exp (frag, where, size, exp, pcrel, reloc); +} + +#if defined (OBJ_COFF) @@ -454873,6 +458501,15 @@ index 0000000..08b5ea2 + return ret; +} + ++static bfd_boolean ++arm_ccs_mode (char * unused ATTRIBUTE_UNUSED) ++{ ++ codecomposer_syntax = TRUE; ++ arm_comment_chars[0] = ';'; ++ arm_line_separator_chars[0] = 0; ++ return TRUE; ++} ++ +struct arm_long_option_table arm_long_opts[] = +{ + {"mcpu=", N_("\t assemble for CPU "), @@ -454889,6 +458526,8 @@ index 0000000..08b5ea2 +#endif + {"mimplicit-it=", N_("\t controls implicit insertion of IT instructions"), + arm_parse_it_mode, NULL}, ++ {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"), ++ arm_ccs_mode, NULL}, + {NULL, NULL, 0, NULL} +}; + @@ -455573,13 +459212,12 @@ index 0000000..08b5ea2 +#endif /* OBJ_ELF */ diff --git a/gas/config/tc-arm.h b/gas/config/tc-arm.h new file mode 100644 -index 0000000..3a0fab0 +index 0000000..a7a0cd0 --- /dev/null +++ b/gas/config/tc-arm.h -@@ -0,0 +1,366 @@ +@@ -0,0 +1,379 @@ +/* This file is tc-arm.h -+ Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, -+ 2004, 2005, 2006, 2007, 2008, 2009, 2012 Free Software Foundation, Inc. ++ Copyright (C) 1994-2014 Free Software Foundation, Inc. + Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) + Modified by David Taylor (dtaylor@armltd.co.uk) + @@ -455661,6 +459299,10 @@ index 0000000..3a0fab0 +/* We support double slash line-comments for compatibility with the ARM AArch64 Assembler. */ +#define DOUBLESLASH_LINE_COMMENTS + ++/* We conditionally support labels without a colon. */ ++#define LABELS_WITHOUT_COLONS codecomposer_syntax ++extern bfd_boolean codecomposer_syntax; ++ +#define tc_symbol_chars arm_symbol_chars +extern const char arm_symbol_chars[]; + @@ -455680,6 +459322,9 @@ index 0000000..3a0fab0 + +#define md_start_line_hook() arm_start_line_hook () + ++#define TC_START_LABEL_WITHOUT_COLON(c, l) tc_start_label_without_colon (c, l) ++extern bfd_boolean tc_start_label_without_colon (char, const char *); ++ +#define tc_frob_label(S) arm_frob_label (S) + +/* We also need to mark assembler created symbols: */ @@ -455921,7 +459566,8 @@ index 0000000..3a0fab0 +extern char * arm_canonicalize_symbol_name (char *); +extern void arm_adjust_symtab (void); +extern void armelf_frob_symbol (symbolS *, int *); -+extern void cons_fix_new_arm (fragS *, int, int, expressionS *); ++extern void cons_fix_new_arm (fragS *, int, int, expressionS *, ++ bfd_reloc_code_real_type); +extern void arm_init_frag (struct frag *, int); +extern void arm_handle_align (struct frag *); +extern bfd_boolean arm_fix_adjustable (struct fix *); @@ -455943,15 +459589,21 @@ index 0000000..3a0fab0 +extern int arm_convert_symbolic_attribute (const char *); +extern int arm_apply_sym_value (struct fix *); +#endif ++ ++#define tc_comment_chars arm_comment_chars ++extern char arm_comment_chars[]; ++ ++#define tc_line_separator_chars arm_line_separator_chars ++extern char arm_line_separator_chars[]; diff --git a/gas/config/tc-avr.c b/gas/config/tc-avr.c new file mode 100644 -index 0000000..332aa2d +index 0000000..e4bc59c --- /dev/null +++ b/gas/config/tc-avr.c -@@ -0,0 +1,1619 @@ +@@ -0,0 +1,1780 @@ +/* tc-avr.c -- Assembler code for the ATMEL AVR + -+ Copyright 1999-2013 Free Software Foundation, Inc. ++ Copyright (C) 1999-2014 Free Software Foundation, Inc. + Contributed by Denis Chertykov + + This file is part of GAS, the GNU Assembler. @@ -456057,6 +459709,7 @@ index 0000000..332aa2d + {"at90s8515", AVR_ISA_AVR2, bfd_mach_avr2}, + {"at90c8534", AVR_ISA_AVR2, bfd_mach_avr2}, + {"at90s8535", AVR_ISA_AVR2, bfd_mach_avr2}, ++ {"ata5272", AVR_ISA_AVR25, bfd_mach_avr25}, + {"attiny13", AVR_ISA_AVR25, bfd_mach_avr25}, + {"attiny13a", AVR_ISA_AVR25, bfd_mach_avr25}, + {"attiny2313", AVR_ISA_AVR25, bfd_mach_avr25}, @@ -456081,6 +459734,7 @@ index 0000000..332aa2d + {"attiny43u", AVR_ISA_AVR25, bfd_mach_avr25}, + {"attiny48", AVR_ISA_AVR25, bfd_mach_avr25}, + {"attiny88", AVR_ISA_AVR25, bfd_mach_avr25}, ++ {"attiny828", AVR_ISA_AVR25, bfd_mach_avr25}, + {"at86rf401", AVR_ISA_RF401, bfd_mach_avr25}, + {"at43usb355", AVR_ISA_AVR3, bfd_mach_avr3}, + {"at76c711", AVR_ISA_AVR3, bfd_mach_avr3}, @@ -456089,13 +459743,19 @@ index 0000000..332aa2d + {"attiny167", AVR_ISA_AVR35, bfd_mach_avr35}, + {"at90usb82", AVR_ISA_AVR35, bfd_mach_avr35}, + {"at90usb162", AVR_ISA_AVR35, bfd_mach_avr35}, ++ {"ata5505", AVR_ISA_AVR35, bfd_mach_avr35}, + {"atmega8u2", AVR_ISA_AVR35, bfd_mach_avr35}, + {"atmega16u2", AVR_ISA_AVR35, bfd_mach_avr35}, + {"atmega32u2", AVR_ISA_AVR35, bfd_mach_avr35}, ++ {"attiny1634", AVR_ISA_AVR35, bfd_mach_avr35}, + {"atmega8", AVR_ISA_M8, bfd_mach_avr4}, + {"ata6289", AVR_ISA_AVR4, bfd_mach_avr4}, ++ {"atmega8a", AVR_ISA_M8, bfd_mach_avr4}, ++ {"ata6285", AVR_ISA_AVR4, bfd_mach_avr4}, ++ {"ata6286", AVR_ISA_AVR4, bfd_mach_avr4}, + {"atmega48", AVR_ISA_AVR4, bfd_mach_avr4}, + {"atmega48a", AVR_ISA_AVR4, bfd_mach_avr4}, ++ {"atmega48pa", AVR_ISA_AVR4, bfd_mach_avr4}, + {"atmega48p", AVR_ISA_AVR4, bfd_mach_avr4}, + {"atmega88", AVR_ISA_AVR4, bfd_mach_avr4}, + {"atmega88a", AVR_ISA_AVR4, bfd_mach_avr4}, @@ -456110,6 +459770,9 @@ index 0000000..332aa2d + {"at90pwm3", AVR_ISA_AVR4, bfd_mach_avr4}, + {"at90pwm3b", AVR_ISA_AVR4, bfd_mach_avr4}, + {"at90pwm81", AVR_ISA_AVR4, bfd_mach_avr4}, ++ {"at90pwm161", AVR_ISA_AVR5, bfd_mach_avr5}, ++ {"ata5790", AVR_ISA_AVR5, bfd_mach_avr5}, ++ {"ata5795", AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega16", AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega16a", AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega161", AVR_ISA_M161, bfd_mach_avr5}, @@ -456117,17 +459780,21 @@ index 0000000..332aa2d + {"atmega163", AVR_ISA_M161, bfd_mach_avr5}, + {"atmega164a", AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega164p", AVR_ISA_AVR5, bfd_mach_avr5}, ++ {"atmega164pa",AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega165", AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega165a", AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega165p", AVR_ISA_AVR5, bfd_mach_avr5}, ++ {"atmega165pa",AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega168", AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega168a", AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega168p", AVR_ISA_AVR5, bfd_mach_avr5}, ++ {"atmega168pa",AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega169", AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega169a", AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega169p", AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega169pa",AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega32", AVR_ISA_AVR5, bfd_mach_avr5}, ++ {"atmega32a", AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega323", AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega324a", AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega324p", AVR_ISA_AVR5, bfd_mach_avr5}, @@ -456151,7 +459818,10 @@ index 0000000..332aa2d + {"atmega3290p",AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega3290pa",AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega406", AVR_ISA_AVR5, bfd_mach_avr5}, ++ {"atmega64rfr2", AVR_ISA_AVR5, bfd_mach_avr5}, ++ {"atmega644rfr2",AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega64", AVR_ISA_AVR5, bfd_mach_avr5}, ++ {"atmega64a", AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega640", AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega644", AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega644a", AVR_ISA_AVR5, bfd_mach_avr5}, @@ -456172,7 +459842,7 @@ index 0000000..332aa2d + {"atmega64rfr2",AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega644rfr2",AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega16hva",AVR_ISA_AVR5, bfd_mach_avr5}, -+ {"atmega16hva2",AVR_ISA_AVR5, bfd_mach_avr5}, ++ {"atmega16hva2",AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega16hvb",AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega16hvbrevb",AVR_ISA_AVR5,bfd_mach_avr5}, + {"atmega32hvb",AVR_ISA_AVR5, bfd_mach_avr5}, @@ -456197,8 +459867,10 @@ index 0000000..332aa2d + {"at94k", AVR_ISA_94K, bfd_mach_avr5}, + {"m3000", AVR_ISA_AVR5, bfd_mach_avr5}, + {"atmega128", AVR_ISA_AVR51, bfd_mach_avr51}, ++ {"atmega128a", AVR_ISA_AVR51, bfd_mach_avr51}, + {"atmega1280", AVR_ISA_AVR51, bfd_mach_avr51}, + {"atmega1281", AVR_ISA_AVR51, bfd_mach_avr51}, ++ {"atmega1284", AVR_ISA_AVR51, bfd_mach_avr51}, + {"atmega1284p",AVR_ISA_AVR51, bfd_mach_avr51}, + {"atmega128rfa1",AVR_ISA_AVR51, bfd_mach_avr51}, + {"atmega128rfr2",AVR_ISA_AVR51, bfd_mach_avr51}, @@ -456211,31 +459883,56 @@ index 0000000..332aa2d + {"atmega256rfr2", AVR_ISA_AVR6, bfd_mach_avr6}, + {"atmega2564rfr2", AVR_ISA_AVR6, bfd_mach_avr6}, + {"atxmega16a4", AVR_ISA_XMEGA, bfd_mach_avrxmega2}, ++ {"atxmega16a4u",AVR_ISA_XMEGAU, bfd_mach_avrxmega2}, ++ {"atxmega16c4", AVR_ISA_XMEGAU, bfd_mach_avrxmega2}, + {"atxmega16d4", AVR_ISA_XMEGA, bfd_mach_avrxmega2}, -+ {"atxmega16x1", AVR_ISA_XMEGA, bfd_mach_avrxmega2}, + {"atxmega32a4", AVR_ISA_XMEGA, bfd_mach_avrxmega2}, ++ {"atxmega32a4u",AVR_ISA_XMEGAU, bfd_mach_avrxmega2}, ++ {"atxmega32c4", AVR_ISA_XMEGAU, bfd_mach_avrxmega2}, + {"atxmega32d4", AVR_ISA_XMEGA, bfd_mach_avrxmega2}, ++ {"atxmega32e5", AVR_ISA_XMEGA, bfd_mach_avrxmega2}, ++ {"atxmega16e5", AVR_ISA_XMEGA, bfd_mach_avrxmega2}, ++ {"atxmega8e5", AVR_ISA_XMEGA, bfd_mach_avrxmega2}, + {"atxmega32x1", AVR_ISA_XMEGA, bfd_mach_avrxmega2}, + {"atxmega64a3", AVR_ISA_XMEGA, bfd_mach_avrxmega4}, ++ {"atxmega64a3u",AVR_ISA_XMEGAU, bfd_mach_avrxmega4}, ++ {"atxmega64a4u",AVR_ISA_XMEGAU, bfd_mach_avrxmega4}, ++ {"atxmega64b1", AVR_ISA_XMEGAU, bfd_mach_avrxmega4}, ++ {"atxmega64b3", AVR_ISA_XMEGAU, bfd_mach_avrxmega4}, ++ {"atxmega64c3", AVR_ISA_XMEGAU, bfd_mach_avrxmega4}, + {"atxmega64d3", AVR_ISA_XMEGA, bfd_mach_avrxmega4}, ++ {"atxmega64d4", AVR_ISA_XMEGA, bfd_mach_avrxmega4}, + {"atxmega64a1", AVR_ISA_XMEGA, bfd_mach_avrxmega5}, + {"atxmega64a1u",AVR_ISA_XMEGAU, bfd_mach_avrxmega5}, + {"atxmega128a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6}, ++ {"atxmega128a3u",AVR_ISA_XMEGAU,bfd_mach_avrxmega6}, + {"atxmega128b1", AVR_ISA_XMEGAU, bfd_mach_avrxmega6}, ++ {"atxmega128b3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6}, ++ {"atxmega128c3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6}, + {"atxmega128d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6}, ++ {"atxmega128d4", AVR_ISA_XMEGA, bfd_mach_avrxmega6}, + {"atxmega192a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6}, ++ {"atxmega192a3u",AVR_ISA_XMEGAU,bfd_mach_avrxmega6}, ++ {"atxmega192c3", AVR_ISA_XMEGAU, bfd_mach_avrxmega6}, + {"atxmega192d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6}, + {"atxmega256a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6}, ++ {"atxmega256a3u",AVR_ISA_XMEGAU,bfd_mach_avrxmega6}, + {"atxmega256a3b",AVR_ISA_XMEGA, bfd_mach_avrxmega6}, + {"atxmega256a3bu",AVR_ISA_XMEGAU, bfd_mach_avrxmega6}, ++ {"atxmega256c3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6}, + {"atxmega256d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6}, ++ {"atxmega384c3", AVR_ISA_XMEGAU,bfd_mach_avrxmega6}, ++ {"atxmega384d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6}, + {"atxmega128a1", AVR_ISA_XMEGA, bfd_mach_avrxmega7}, + {"atxmega128a1u", AVR_ISA_XMEGAU, bfd_mach_avrxmega7}, ++ {"atxmega128a4u", AVR_ISA_XMEGAU, bfd_mach_avrxmega7}, + {NULL, 0, 0} +}; + ++ +/* Current MCU type. */ +static struct mcu_type_s default_mcu = {"avr2", AVR_ISA_AVR2, bfd_mach_avr2}; ++static struct mcu_type_s specified_mcu; +static struct mcu_type_s * avr_mcu = & default_mcu; + +/* AVR target-specific switches. */ @@ -456244,9 +459941,11 @@ index 0000000..332aa2d + int all_opcodes; /* -mall-opcodes: accept all known AVR opcodes. */ + int no_skip_bug; /* -mno-skip-bug: no warnings for skipping 2-word insns. */ + int no_wrap; /* -mno-wrap: reject rjmp/rcall with 8K wrap-around. */ ++ int link_relax; /* -mlink-relax: generate relocations for linker ++ relaxation. */ +}; + -+static struct avr_opt_s avr_opt = { 0, 0, 0 }; ++static struct avr_opt_s avr_opt = { 0, 0, 0, 0 }; + +const char EXP_CHARS[] = "eE"; +const char FLT_CHARS[] = "dD"; @@ -456306,7 +460005,9 @@ index 0000000..332aa2d +{ + OPTION_ALL_OPCODES = OPTION_MD_BASE + 1, + OPTION_NO_SKIP_BUG, -+ OPTION_NO_WRAP ++ OPTION_NO_WRAP, ++ OPTION_ISA_RMW, ++ OPTION_LINK_RELAX +}; + +struct option md_longopts[] = @@ -456315,6 +460016,8 @@ index 0000000..332aa2d + { "mall-opcodes", no_argument, NULL, OPTION_ALL_OPCODES }, + { "mno-skip-bug", no_argument, NULL, OPTION_NO_SKIP_BUG }, + { "mno-wrap", no_argument, NULL, OPTION_NO_WRAP }, ++ { "mrmw", no_argument, NULL, OPTION_ISA_RMW }, ++ { "mlink-relax", no_argument, NULL, OPTION_LINK_RELAX }, + { NULL, no_argument, NULL, 0 } +}; + @@ -456419,7 +460122,10 @@ index 0000000..332aa2d + " -mno-skip-bug disable warnings for skipping two-word instructions\n" + " (default for avr4, avr5)\n" + " -mno-wrap reject rjmp/rcall instructions with 8K wrap-around\n" -+ " (default for avr3, avr5)\n")); ++ " (default for avr3, avr5)\n" ++ " -mrmw accept Read-Modify-Write instructions\n" ++ " -mlink-relax generate relocations for linker relaxation\n" ++ )); + show_mcu_list (stream); +} + @@ -456466,7 +460172,12 @@ index 0000000..332aa2d + type - this for allows passing -mmcu=... via gcc ASM_SPEC as well + as .arch ... in the asm output at the same time. */ + if (avr_mcu == &default_mcu || avr_mcu->mach == mcu_types[i].mach) -+ avr_mcu = &mcu_types[i]; ++ { ++ specified_mcu.name = mcu_types[i].name; ++ specified_mcu.isa |= mcu_types[i].isa; ++ specified_mcu.mach = mcu_types[i].mach; ++ avr_mcu = &specified_mcu; ++ } + else + as_fatal (_("redefinition of mcu type `%s' to `%s'"), + avr_mcu->name, mcu_types[i].name); @@ -456481,6 +460192,12 @@ index 0000000..332aa2d + case OPTION_NO_WRAP: + avr_opt.no_wrap = 1; + return 1; ++ case OPTION_ISA_RMW: ++ specified_mcu.isa |= AVR_ISA_RMW; ++ return 1; ++ case OPTION_LINK_RELAX: ++ avr_opt.link_relax = 1; ++ return 1; + } + + return 0; @@ -456531,6 +460248,7 @@ index 0000000..332aa2d + } + + bfd_set_arch_mach (stdoutput, TARGET_ARCH, avr_mcu->mach); ++ linkrelax = avr_opt.link_relax; +} + +/* Resolve STR as a constant expression and return the result. @@ -457094,6 +460812,53 @@ index 0000000..332aa2d + return fixp->fx_frag->fr_address + fixp->fx_where; +} + ++static bfd_boolean ++relaxable_section (asection *sec) ++{ ++ return (sec->flags & SEC_DEBUGGING) == 0; ++} ++ ++/* Does whatever the xtensa port does. */ ++int ++avr_validate_fix_sub (fixS *fix) ++{ ++ segT add_symbol_segment, sub_symbol_segment; ++ ++ /* The difference of two symbols should be resolved by the assembler when ++ linkrelax is not set. If the linker may relax the section containing ++ the symbols, then an Xtensa DIFF relocation must be generated so that ++ the linker knows to adjust the difference value. */ ++ if (!linkrelax || fix->fx_addsy == NULL) ++ return 0; ++ ++ /* Make sure both symbols are in the same segment, and that segment is ++ "normal" and relaxable. If the segment is not "normal", then the ++ fix is not valid. If the segment is not "relaxable", then the fix ++ should have been handled earlier. */ ++ add_symbol_segment = S_GET_SEGMENT (fix->fx_addsy); ++ if (! SEG_NORMAL (add_symbol_segment) || ++ ! relaxable_section (add_symbol_segment)) ++ return 0; ++ ++ sub_symbol_segment = S_GET_SEGMENT (fix->fx_subsy); ++ return (sub_symbol_segment == add_symbol_segment); ++} ++ ++/* TC_FORCE_RELOCATION hook */ ++ ++/* If linkrelax is turned on, and the symbol to relocate ++ against is in a relaxable segment, don't compute the value - ++ generate a relocation instead. */ ++int ++avr_force_relocation (fixS *fix) ++{ ++ if (linkrelax && fix->fx_addsy ++ && relaxable_section (S_GET_SEGMENT (fix->fx_addsy))) ++ return 1; ++ ++ return generic_force_reloc (fix); ++} ++ +/* GAS will call this for each fixup. It should store the correct + value in the object file. */ + @@ -457117,11 +460882,47 @@ index 0000000..332aa2d + fixP->fx_done = 1; + } + } ++ else if (linkrelax && fixP->fx_subsy) ++ { ++ /* For a subtraction relocation expression, generate one ++ of the DIFF relocs, with the value being the difference. ++ Note that a sym1 - sym2 expression is adjusted into a ++ section_start_sym + sym4_offset_from_section_start - sym1 ++ expression. fixP->fx_addsy holds the section start symbol, ++ fixP->fx_offset holds sym2's offset, and fixP->fx_subsy ++ holds sym1. Calculate the current difference and write value, ++ but leave fx_offset as is - during relaxation, ++ fx_offset - value gives sym1's value */ + ++ switch (fixP->fx_r_type) ++ { ++ case BFD_RELOC_8: ++ fixP->fx_r_type = BFD_RELOC_AVR_DIFF8; ++ break; ++ case BFD_RELOC_16: ++ fixP->fx_r_type = BFD_RELOC_AVR_DIFF16; ++ break; ++ case BFD_RELOC_32: ++ fixP->fx_r_type = BFD_RELOC_AVR_DIFF32; ++ break; ++ default: ++ as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex")); ++ break; ++ } ++ ++ value = S_GET_VALUE (fixP->fx_addsy) + ++ fixP->fx_offset - S_GET_VALUE (fixP->fx_subsy); ++ ++ fixP->fx_subsy = NULL; ++ } + /* We don't actually support subtracting a symbol. */ + if (fixP->fx_subsy != (symbolS *) NULL) + as_bad_where (fixP->fx_file, fixP->fx_line, _("expression too complex")); + ++ /* For the DIFF relocs, write the value into the object file while still ++ keeping fx_done FALSE, as both the difference (recorded in the object file) ++ and the sym offset (part of fixP) are needed at link relax time */ ++ where = (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where; + switch (fixP->fx_r_type) + { + default: @@ -457131,6 +460932,16 @@ index 0000000..332aa2d + case BFD_RELOC_AVR_13_PCREL: + case BFD_RELOC_32: + case BFD_RELOC_16: ++ break; ++ case BFD_RELOC_AVR_DIFF8: ++ *where = value; ++ break; ++ case BFD_RELOC_AVR_DIFF16: ++ bfd_putl16 ((bfd_vma) value, where); ++ break; ++ case BFD_RELOC_AVR_DIFF32: ++ bfd_putl32 ((bfd_vma) value, where); ++ break; + case BFD_RELOC_AVR_CALL: + break; + } @@ -457415,22 +461226,7 @@ index 0000000..332aa2d + } +} + -+typedef struct -+{ -+ /* Name of the expression modifier allowed with .byte, .word, etc. */ -+ const char *name; -+ -+ /* Only allowed with n bytes of data. */ -+ int nbytes; -+ -+ /* Associated RELOC. */ -+ bfd_reloc_code_real_type reloc; -+ -+ /* Part of the error message. */ -+ const char *error; -+} exp_mod_data_t; -+ -+static const exp_mod_data_t exp_mod_data[] = ++const exp_mod_data_t exp_mod_data[] = +{ + /* Default, must be first. */ + { "", 0, BFD_RELOC_16, "" }, @@ -457451,21 +461247,16 @@ index 0000000..332aa2d + { NULL, 0, 0, NULL } +}; + -+/* Data to pass between `avr_parse_cons_expression' and `avr_cons_fix_new'. */ -+static const exp_mod_data_t *pexp_mod_data = &exp_mod_data[0]; -+ +/* Parse special CONS expression: pm (expression) or alternatively + gs (expression). These are used for addressing program memory. Moreover, + define lo8 (expression), hi8 (expression) and hlo8 (expression). */ + -+void ++const exp_mod_data_t * +avr_parse_cons_expression (expressionS *exp, int nbytes) +{ + const exp_mod_data_t *pexp = &exp_mod_data[0]; + char *tmp; + -+ pexp_mod_data = pexp; -+ + tmp = input_line_pointer = skip_space (input_line_pointer); + + /* The first entry of exp_mod_data[] contains an entry if no @@ -457483,18 +461274,18 @@ index 0000000..332aa2d + if (*input_line_pointer == '(') + { + input_line_pointer = skip_space (input_line_pointer + 1); -+ pexp_mod_data = pexp; + expression (exp); + + if (*input_line_pointer == ')') -+ ++input_line_pointer; ++ { ++ ++input_line_pointer; ++ return pexp; ++ } + else + { + as_bad (_("`)' required")); -+ pexp_mod_data = &exp_mod_data[0]; ++ return &exp_mod_data[0]; + } -+ -+ return; + } + + input_line_pointer = tmp; @@ -457504,13 +461295,15 @@ index 0000000..332aa2d + } + + expression (exp); ++ return &exp_mod_data[0]; +} + +void +avr_cons_fix_new (fragS *frag, + int where, + int nbytes, -+ expressionS *exp) ++ expressionS *exp, ++ const exp_mod_data_t *pexp_mod_data) +{ + int bad = 0; + @@ -457540,8 +461333,6 @@ index 0000000..332aa2d + + if (bad) + as_bad (_("illegal %srelocation size: %d"), pexp_mod_data->error, nbytes); -+ -+ pexp_mod_data = &exp_mod_data[0]; +} + +static bfd_boolean @@ -457568,15 +461359,36 @@ index 0000000..332aa2d + do not line up the same way as for targers that use pre-decrement. */ + cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, 1-return_size); +} ++ ++bfd_boolean ++avr_allow_local_subtract (expressionS * left, ++ expressionS * right, ++ segT section) ++{ ++ /* If we are not in relaxation mode, subtraction is OK. */ ++ if (!linkrelax) ++ return TRUE; ++ ++ /* If the symbols are not in a code section then they are OK. */ ++ if ((section->flags & SEC_CODE) == 0) ++ return TRUE; ++ ++ if (left->X_add_symbol == right->X_add_symbol) ++ return TRUE; ++ ++ /* We have to assume that there may be instructions between the ++ two symbols and that relaxation may increase the distance between ++ them. */ ++ return FALSE; ++} diff --git a/gas/config/tc-avr.h b/gas/config/tc-avr.h new file mode 100644 -index 0000000..ee36e65 +index 0000000..fb596ad --- /dev/null +++ b/gas/config/tc-avr.h -@@ -0,0 +1,173 @@ +@@ -0,0 +1,215 @@ +/* This file is tc-avr.h -+ Copyright 1999, 2000, 2001, 2002, 2005, 2006, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1999-2014 Free Software Foundation, Inc. + + Contributed by Denis Chertykov + @@ -457627,16 +461439,36 @@ index 0000000..ee36e65 + will point to the start of the expression. */ +#define md_operand(x) + ++typedef struct ++{ ++ /* Name of the expression modifier allowed with .byte, .word, etc. */ ++ const char *name; ++ ++ /* Only allowed with n bytes of data. */ ++ int nbytes; ++ ++ /* Associated RELOC. */ ++ bfd_reloc_code_real_type reloc; ++ ++ /* Part of the error message. */ ++ const char *error; ++} exp_mod_data_t; ++ ++extern const exp_mod_data_t exp_mod_data[]; ++#define TC_PARSE_CONS_RETURN_TYPE const exp_mod_data_t * ++#define TC_PARSE_CONS_RETURN_NONE exp_mod_data ++ +/* You may define this macro to parse an expression used in a data + allocation pseudo-op such as `.word'. You can use this to + recognize relocation directives that may appear in such directives. */ +#define TC_PARSE_CONS_EXPRESSION(EXPR,N) avr_parse_cons_expression (EXPR, N) -+extern void avr_parse_cons_expression (expressionS *, int); ++extern const exp_mod_data_t *avr_parse_cons_expression (expressionS *, int); + +/* You may define this macro to generate a fixup for a data + allocation pseudo-op. */ -+#define TC_CONS_FIX_NEW(FRAG,WHERE,N,EXP) avr_cons_fix_new (FRAG, WHERE, N, EXP) -+extern void avr_cons_fix_new (fragS *,int, int, expressionS *); ++#define TC_CONS_FIX_NEW avr_cons_fix_new ++extern void avr_cons_fix_new (fragS *,int, int, expressionS *, ++ const exp_mod_data_t *); + +/* This should just call either `number_to_chars_bigendian' or + `number_to_chars_littleendian', whichever is appropriate. On @@ -457669,6 +461501,18 @@ index 0000000..ee36e65 + visible symbols can be overridden. */ +#define EXTERN_FORCE_RELOC 0 + ++/* If defined, this macro allows control over whether fixups for a ++ given section will be processed when the linkrelax variable is ++ set. Define it to zero and handle things in md_apply_fix instead.*/ ++#define TC_LINKRELAX_FIXUP(SEG) 0 ++ ++/* If this macro returns non-zero, it guarantees that a relocation will be emitted ++ even when the value can be resolved locally. Do that if linkrelax is turned on */ ++#define TC_FORCE_RELOCATION(fix) avr_force_relocation (fix) ++#define TC_FORCE_RELOCATION_SUB_SAME(fix, seg) \ ++ (! SEG_NORMAL (seg) || avr_force_relocation (fix)) ++extern int avr_force_relocation (struct fix *); ++ +/* Values passed to md_apply_fix don't include the symbol value. */ +#define MD_APPLY_SYM_VALUE(FIX) 0 + @@ -457726,6 +461570,12 @@ index 0000000..ee36e65 + goto SKIP; \ + } + ++/* This macro is evaluated for any fixup with a fx_subsy that ++ fixup_segment cannot reduce to a number. If the macro returns ++ false an error will be reported. */ ++#define TC_VALIDATE_FIX_SUB(fix, seg) avr_validate_fix_sub (fix) ++extern int avr_validate_fix_sub (struct fix *); ++ +/* This target is buggy, and sets fix size too large. */ +#define TC_FX_SIZE_SLACK(FIX) 2 + @@ -457747,15 +461597,19 @@ index 0000000..ee36e65 +/* Define a hook to setup initial CFI state. */ +extern void tc_cfi_frame_initial_instructions (void); +#define tc_cfi_frame_initial_instructions tc_cfi_frame_initial_instructions ++ ++/* The difference between same-section symbols may be affected by linker ++ relaxation, so do not resolve such expressions in the assembler. */ ++#define md_allow_local_subtract(l,r,s) avr_allow_local_subtract (l, r, s) ++extern bfd_boolean avr_allow_local_subtract (expressionS *, expressionS *, segT); diff --git a/gas/config/tc-bfin.c b/gas/config/tc-bfin.c new file mode 100644 -index 0000000..99e9b1e +index 0000000..8366cbf --- /dev/null +++ b/gas/config/tc-bfin.c -@@ -0,0 +1,2734 @@ +@@ -0,0 +1,2733 @@ +/* tc-bfin.c -- Assembler for the ADI Blackfin. -+ Copyright 2005, 2006, 2007, 2008, 2009, 2010 -+ Free Software Foundation, Inc. ++ Copyright (C) 2005-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -460489,13 +464343,12 @@ index 0000000..99e9b1e +} diff --git a/gas/config/tc-bfin.h b/gas/config/tc-bfin.h new file mode 100644 -index 0000000..9ec990d +index 0000000..38f8c67 --- /dev/null +++ b/gas/config/tc-bfin.h -@@ -0,0 +1,85 @@ +@@ -0,0 +1,84 @@ +/* tc-bfin.h - header file for tc-bfin.c -+ Copyright 2005, 2006, 2007, 2008, 2009 -+ Free Software Foundation, Inc. ++ Copyright (C) 2005-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -460580,13 +464433,12 @@ index 0000000..9ec990d +/* end of tc-bfin.h */ diff --git a/gas/config/tc-cr16.c b/gas/config/tc-cr16.c new file mode 100644 -index 0000000..8d6e780 +index 0000000..bcdf978 --- /dev/null +++ b/gas/config/tc-cr16.c -@@ -0,0 +1,2571 @@ +@@ -0,0 +1,2569 @@ +/* tc-cr16.c -- Assembler code for the CR16 CPU core. -+ Copyright 2007, 2008, 2009, 2010, 2011 -+ Free Software Foundation, Inc. ++ Copyright (C) 2007-2014 Free Software Foundation, Inc. + + Contributed by M R Swami Reddy + @@ -461079,10 +464931,9 @@ index 0000000..8d6e780 +/* Record a fixup for a cons expression. */ + +void -+cr16_cons_fix_new (fragS *frag, int offset, int len, expressionS *exp) ++cr16_cons_fix_new (fragS *frag, int offset, int len, expressionS *exp, ++ bfd_reloc_code_real_type rtype) +{ -+ int rtype = BFD_RELOC_UNUSED; -+ + switch (len) + { + default: rtype = BFD_RELOC_NONE; break; @@ -463157,12 +467008,12 @@ index 0000000..8d6e780 +} diff --git a/gas/config/tc-cr16.h b/gas/config/tc-cr16.h new file mode 100644 -index 0000000..739317f +index 0000000..9da8cb7 --- /dev/null +++ b/gas/config/tc-cr16.h -@@ -0,0 +1,75 @@ +@@ -0,0 +1,76 @@ +/* tc-cr16.h -- Header file for tc-cr16.c, the CR16 GAS port. -+ Copyright 2007, 2008, 2009 Free Software Foundation, Inc. ++ Copyright (C) 2007-2014 Free Software Foundation, Inc. + + Contributed by M R Swami Reddy + @@ -463220,12 +467071,13 @@ index 0000000..739317f + of two bytes long. */ +#define DWARF2_LINE_MIN_INSN_LENGTH 2 + -+extern void cr16_cons_fix_new (struct frag *, int, int, struct expressionS *); ++extern void cr16_cons_fix_new (struct frag *, int, int, struct expressionS *, ++ bfd_reloc_code_real_type); +/* This is called by emit_expr when creating a reloc for a cons. + We could use the definition there, except that we want to handle + the CR16 reloc type specially, rather than the BFD_RELOC type. */ -+#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP) \ -+ cr16_cons_fix_new (FRAG, OFF, LEN, EXP) ++#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP, RELOC) \ ++ cr16_cons_fix_new (FRAG, OFF, LEN, EXP, RELOC) + +/* Give an error if a frag containing code is not aligned to a 2-byte + boundary. */ @@ -463238,13 +467090,12 @@ index 0000000..739317f +#endif /* TC_CR16_H */ diff --git a/gas/config/tc-cris.c b/gas/config/tc-cris.c new file mode 100644 -index 0000000..657c7ed +index 0000000..86d8062 --- /dev/null +++ b/gas/config/tc-cris.c -@@ -0,0 +1,4407 @@ +@@ -0,0 +1,4406 @@ +/* tc-cris.c -- Assembler code for the CRIS CPU core. -+ Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 -+ Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + + Contributed by Axis Communications AB, Lund, Sweden. + Originally written for GAS 1.38.1 by Mikael Asker. @@ -467651,13 +471502,12 @@ index 0000000..657c7ed + */ diff --git a/gas/config/tc-cris.h b/gas/config/tc-cris.h new file mode 100644 -index 0000000..56584bf +index 0000000..ce3ad73 --- /dev/null +++ b/gas/config/tc-cris.h -@@ -0,0 +1,171 @@ +@@ -0,0 +1,170 @@ +/* tc-cris.h -- Header file for tc-cris.c, the CRIS GAS port. -+ Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2009 -+ Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + + Contributed by Axis Communications AB, Lund, Sweden. + Originally written for GAS 1.38.1 by Mikael Asker. @@ -467828,13 +471678,12 @@ index 0000000..56584bf + */ diff --git a/gas/config/tc-crx.c b/gas/config/tc-crx.c new file mode 100644 -index 0000000..3b06a78 +index 0000000..61a31b3 --- /dev/null +++ b/gas/config/tc-crx.c -@@ -0,0 +1,2011 @@ +@@ -0,0 +1,2010 @@ +/* tc-crx.c -- Assembler code for the CRX CPU core. -+ Copyright 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 2004-2014 Free Software Foundation, Inc. + + Contributed by Tomer Levi, NSC, Israel. + Originally written for GAS 2.12 by Tomer Levi, NSC, Israel. @@ -469845,12 +473694,12 @@ index 0000000..3b06a78 +} diff --git a/gas/config/tc-crx.h b/gas/config/tc-crx.h new file mode 100644 -index 0000000..3036dc6 +index 0000000..da6d710 --- /dev/null +++ b/gas/config/tc-crx.h -@@ -0,0 +1,78 @@ +@@ -0,0 +1,79 @@ +/* tc-crx.h -- Header file for tc-crx.c, the CRX GAS port. -+ Copyright 2004, 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 2004-2014 Free Software Foundation, Inc. + + Contributed by Tomer Levi, NSC, Israel. + Originally written for GAS 2.12 by Tomer Levi, NSC, Israel. @@ -469911,7 +473760,8 @@ index 0000000..3036dc6 +/* This is called by emit_expr when creating a reloc for a cons. + We could use the definition there, except that we want to handle + the CRX reloc type specially, rather than the BFD_RELOC type. */ -+#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP) \ ++#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP, RELOC) \ ++ (void) RELOC, \ + fix_new_exp (FRAG, OFF, (int) LEN, EXP, 0, \ + LEN == 1 ? BFD_RELOC_CRX_NUM8 \ + : LEN == 2 ? BFD_RELOC_CRX_NUM16 \ @@ -469929,14 +473779,12 @@ index 0000000..3036dc6 +#endif /* TC_CRX_H */ diff --git a/gas/config/tc-d10v.c b/gas/config/tc-d10v.c new file mode 100644 -index 0000000..983c2f8 +index 0000000..8e3d171 --- /dev/null +++ b/gas/config/tc-d10v.c -@@ -0,0 +1,1821 @@ +@@ -0,0 +1,1819 @@ +/* tc-d10v.c -- Assembler code for the Mitsubishi D10V -+ Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006, -+ 2007, 2009, 2010 -+ Free Software Foundation, Inc. ++ Copyright (C) 1996-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -471756,13 +475604,12 @@ index 0000000..983c2f8 + diff --git a/gas/config/tc-d10v.h b/gas/config/tc-d10v.h new file mode 100644 -index 0000000..3c32624 +index 0000000..55dc1cc --- /dev/null +++ b/gas/config/tc-d10v.h -@@ -0,0 +1,64 @@ +@@ -0,0 +1,63 @@ +/* tc-d10v.h -- Header file for tc-d10v.c. -+ Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2005, 2007, 2009, -+ 2010, 2011 Free Software Foundation, Inc. ++ Copyright (C) 1996-2014 Free Software Foundation, Inc. + Written by Martin Hunt, Cygnus Support. + + This file is part of GAS, the GNU Assembler. @@ -471826,13 +475673,12 @@ index 0000000..3c32624 +#define md_flush_pending_output d10v_cleanup diff --git a/gas/config/tc-d30v.c b/gas/config/tc-d30v.c new file mode 100644 -index 0000000..9a3477b +index 0000000..9076e41 --- /dev/null +++ b/gas/config/tc-d30v.c -@@ -0,0 +1,2127 @@ +@@ -0,0 +1,2126 @@ +/* tc-d30v.c -- Assembler code for the Mitsubishi D30V -+ Copyright 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008, -+ 2009, 2010 Free Software Foundation, Inc. ++ Copyright (C) 1997-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -473959,13 +477805,12 @@ index 0000000..9a3477b +}; diff --git a/gas/config/tc-d30v.h b/gas/config/tc-d30v.h new file mode 100644 -index 0000000..e75f3d8 +index 0000000..3e11a1c --- /dev/null +++ b/gas/config/tc-d30v.h -@@ -0,0 +1,65 @@ +@@ -0,0 +1,64 @@ +/* tc-310v.h -- Header file for tc-d30v.c. -+ Copyright 1997, 1998, 2000, 2001, 2002, 2005, 2007, 2009, 2011 -+ Free Software Foundation, Inc. ++ Copyright (C) 1997-2014 Free Software Foundation, Inc. + Written by Martin Hunt, Cygnus Support. + + This file is part of GAS, the GNU Assembler. @@ -474030,13 +477875,12 @@ index 0000000..e75f3d8 +#define EXTERN_FORCE_RELOC 0 diff --git a/gas/config/tc-dlx.c b/gas/config/tc-dlx.c new file mode 100644 -index 0000000..a629533 +index 0000000..4cbc5c0 --- /dev/null +++ b/gas/config/tc-dlx.c -@@ -0,0 +1,1243 @@ +@@ -0,0 +1,1242 @@ +/* tc-dlx.c -- Assemble for the DLX -+ Copyright 2002, 2003, 2004, 2005, 2007, 2009, 2010, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 2002-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -475279,12 +479123,12 @@ index 0000000..a629533 +} diff --git a/gas/config/tc-dlx.h b/gas/config/tc-dlx.h new file mode 100644 -index 0000000..de5506b +index 0000000..e299f27 --- /dev/null +++ b/gas/config/tc-dlx.h @@ -0,0 +1,66 @@ +/* tc-dlx.h -- Assemble for the DLX -+ Copyright 2002, 2003, 2005, 2006, 2007 Free Software Foundation, Inc. ++ Copyright (C) 2002-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -475351,12 +479195,12 @@ index 0000000..de5506b +#define DIFF_EXPR_OK diff --git a/gas/config/tc-epiphany.c b/gas/config/tc-epiphany.c new file mode 100644 -index 0000000..d472968 +index 0000000..ebaedc4 --- /dev/null +++ b/gas/config/tc-epiphany.c @@ -0,0 +1,1111 @@ +/* tc-epiphany.c -- Assembler for the Adapteva EPIPHANY -+ Copyright 2009-2013 Free Software Foundation, Inc. ++ Copyright (C) 2009-2014 Free Software Foundation, Inc. + Contributed by Embecosm on behalf of Adapteva, Inc. + + This file is part of GAS, the GNU Assembler. @@ -476468,12 +480312,12 @@ index 0000000..d472968 +} diff --git a/gas/config/tc-epiphany.h b/gas/config/tc-epiphany.h new file mode 100644 -index 0000000..ed5782e +index 0000000..ddfb475 --- /dev/null +++ b/gas/config/tc-epiphany.h @@ -0,0 +1,102 @@ +/* tc-epiphany.h -- Header file for tc-epiphany.c. -+ Copyright 2009, 2011 Free Software Foundation, Inc. ++ Copyright (C) 2009-2014 Free Software Foundation, Inc. + Contributed by Embecosm on behalf of Adapteva, Inc. + + This file is part of GAS, the GNU Assembler. @@ -476576,13 +480420,12 @@ index 0000000..ed5782e +extern void epiphany_apply_fix (fixS *fixP, valueT *valP, segT seg); diff --git a/gas/config/tc-fr30.c b/gas/config/tc-fr30.c new file mode 100644 -index 0000000..8e01fb2 +index 0000000..07c2b8f --- /dev/null +++ b/gas/config/tc-fr30.c -@@ -0,0 +1,420 @@ +@@ -0,0 +1,419 @@ +/* tc-fr30.c -- Assembler for the Fujitsu FR30. -+ Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2009 -+ Free Software Foundation, Inc. ++ Copyright (C) 1998-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -477002,13 +480845,12 @@ index 0000000..8e01fb2 +} diff --git a/gas/config/tc-fr30.h b/gas/config/tc-fr30.h new file mode 100644 -index 0000000..9709cdd +index 0000000..3ed399b --- /dev/null +++ b/gas/config/tc-fr30.h -@@ -0,0 +1,66 @@ +@@ -0,0 +1,65 @@ +/* tc-fr30.h -- Header file for tc-fr30.c. -+ Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007, 2009 -+ Free Software Foundation, Inc. ++ Copyright (C) 1998-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -477074,13 +480916,12 @@ index 0000000..9709cdd +extern char fr30_is_colon_insn (char *); diff --git a/gas/config/tc-frv.c b/gas/config/tc-frv.c new file mode 100644 -index 0000000..9cdbe26 +index 0000000..faaa1c2 --- /dev/null +++ b/gas/config/tc-frv.c -@@ -0,0 +1,1834 @@ +@@ -0,0 +1,1833 @@ +/* tc-frv.c -- Assembler for the Fujitsu FRV. -+ Copyright 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 -+ Free Software Foundation. Inc. ++ Copyright (C) 2002-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -478914,13 +482755,12 @@ index 0000000..9cdbe26 +} diff --git a/gas/config/tc-frv.h b/gas/config/tc-frv.h new file mode 100644 -index 0000000..c29210e +index 0000000..9b4e606 --- /dev/null +++ b/gas/config/tc-frv.h -@@ -0,0 +1,126 @@ +@@ -0,0 +1,125 @@ +/* tc-frv.h -- Header file for tc-frv.c. -+ Copyright 2002, 2004, 2005, 2007, 2008, 2009 -+ Free Software Foundation, Inc. ++ Copyright (C) 2002-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -479046,13 +482886,13 @@ index 0000000..c29210e + while (0) diff --git a/gas/config/tc-generic.c b/gas/config/tc-generic.c new file mode 100644 -index 0000000..258878a +index 0000000..778429a --- /dev/null +++ b/gas/config/tc-generic.c @@ -0,0 +1,22 @@ +/* This file is tc-generic.c + -+ Copyright 2004, 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 2004-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -479074,14 +482914,13 @@ index 0000000..258878a + target cpu specific files. */ diff --git a/gas/config/tc-generic.h b/gas/config/tc-generic.h new file mode 100644 -index 0000000..bbaa359 +index 0000000..ec7593f --- /dev/null +++ b/gas/config/tc-generic.h -@@ -0,0 +1,36 @@ +@@ -0,0 +1,35 @@ +/* This file is tc-generic.h + -+ Copyright 1987, 1991, 1992, 1995, 1997, 2005, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -479116,12 +482955,12 @@ index 0000000..bbaa359 + diff --git a/gas/config/tc-h8300.c b/gas/config/tc-h8300.c new file mode 100644 -index 0000000..032831b +index 0000000..e4b827b --- /dev/null +++ b/gas/config/tc-h8300.c @@ -0,0 +1,2258 @@ +/* tc-h8300.c -- Assemble code for the Renesas H8/300 -+ Copyright 1991-2013 Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -481380,12 +485219,12 @@ index 0000000..032831b +} diff --git a/gas/config/tc-h8300.h b/gas/config/tc-h8300.h new file mode 100644 -index 0000000..0a2e828 +index 0000000..35dfea8 --- /dev/null +++ b/gas/config/tc-h8300.h @@ -0,0 +1,90 @@ +/* This file is tc-h8300.h -+ Copyright 1987-2013 Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -481476,14 +485315,12 @@ index 0000000..0a2e828 +#define H_TICK_HEX 1 diff --git a/gas/config/tc-hppa.c b/gas/config/tc-hppa.c new file mode 100644 -index 0000000..6e2debe +index 0000000..5ee7f72 --- /dev/null +++ b/gas/config/tc-hppa.c -@@ -0,0 +1,8804 @@ +@@ -0,0 +1,8798 @@ +/* tc-hppa.c -- Assemble for the PA -+ Copyright 1989, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, -+ 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1989-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -482090,9 +485927,6 @@ index 0000000..6e2debe + seen in each subspace. */ +static label_symbol_struct *label_symbols_rootp = NULL; + -+/* Holds the last field selector. */ -+static int hppa_field_selector; -+ +/* Nonzero when strict matching is enabled. Zero otherwise. + + Each opcode in the table has a flag which indicates whether or @@ -482747,7 +486581,8 @@ index 0000000..6e2debe + hppa_field_selector is set by the parse_cons_expression_hppa. */ + +void -+cons_fix_new_hppa (fragS *frag, int where, int size, expressionS *exp) ++cons_fix_new_hppa (fragS *frag, int where, int size, expressionS *exp, ++ int hppa_field_selector) +{ + unsigned int rel_type; + @@ -482784,9 +486619,6 @@ index 0000000..6e2debe + fix_new_hppa (frag, where, size, + (symbolS *) NULL, (offsetT) 0, exp, 0, rel_type, + hppa_field_selector, size * 8, 0, 0); -+ -+ /* Reset field selector to its default state. */ -+ hppa_field_selector = 0; +} + +/* Mark (via expr_end) the end of an expression (I think). FIXME. */ @@ -484001,11 +487833,12 @@ index 0000000..6e2debe +/* Parse a .byte, .word, .long expression for the HPPA. Called by + cons via the TC_PARSE_CONS_EXPRESSION macro. */ + -+void ++int +parse_cons_expression_hppa (expressionS *exp) +{ -+ hppa_field_selector = pa_chk_field_selector (&input_line_pointer); ++ int hppa_field_selector = pa_chk_field_selector (&input_line_pointer); + expression (exp); ++ return hppa_field_selector; +} + +/* Evaluate an absolute expression EXP which may be modified by @@ -490286,14 +494119,12 @@ index 0000000..6e2debe +#endif diff --git a/gas/config/tc-hppa.h b/gas/config/tc-hppa.h new file mode 100644 -index 0000000..78d9edf +index 0000000..4277e10 --- /dev/null +++ b/gas/config/tc-hppa.h @@ -0,0 +1,240 @@ +/* tc-hppa.h -- Header file for the PA -+ Copyright 1989, 1993, 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, -+ 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1989-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -490384,8 +494215,8 @@ index 0000000..78d9edf + +/* pa_define_label gets used outside of tc-hppa.c via tc_frob_label. */ +extern void pa_define_label (symbolS *); -+extern void parse_cons_expression_hppa (expressionS *); -+extern void cons_fix_new_hppa (fragS *, int, int, expressionS *); ++extern int parse_cons_expression_hppa (expressionS *); ++extern void cons_fix_new_hppa (fragS *, int, int, expressionS *, int); +extern int hppa_force_relocation (struct fix *); + +/* This gets called before writing the object file to make sure @@ -490406,6 +494237,8 @@ index 0000000..78d9edf +#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) \ + parse_cons_expression_hppa (EXP) +#define TC_CONS_FIX_NEW cons_fix_new_hppa ++#define TC_PARSE_CONS_RETURN_TYPE int ++#define TC_PARSE_CONS_RETURN_NONE e_fsel + +/* On the PA, an exclamation point can appear in an instruction. It is + used in FP comparison instructions and as an end of line marker. @@ -490532,14 +494365,13 @@ index 0000000..78d9edf +#endif /* _TC_HPPA_H */ diff --git a/gas/config/tc-i370.c b/gas/config/tc-i370.c new file mode 100644 -index 0000000..bf362a3 +index 0000000..399b7f3 --- /dev/null +++ b/gas/config/tc-i370.c -@@ -0,0 +1,2667 @@ +@@ -0,0 +1,2666 @@ +/* tc-i370.c -- Assembler for the IBM 360/370/390 instruction set. + Loosely based on the ppc files by Linas Vepstas 1998, 99 -+ Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, -+ 2004, 2005, 2006, 2007, 2009, 2010 Free Software Foundation, Inc. ++ Copyright (C) 1994-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor, Cygnus Support. + + This file is part of GAS, the GNU Assembler. @@ -493205,13 +497037,12 @@ index 0000000..bf362a3 +}; diff --git a/gas/config/tc-i370.h b/gas/config/tc-i370.h new file mode 100644 -index 0000000..71e7184 +index 0000000..6ee29a3 --- /dev/null +++ b/gas/config/tc-i370.h -@@ -0,0 +1,64 @@ +@@ -0,0 +1,63 @@ +/* tc-i370.h -- Header file for tc-i370.c. -+ Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2005, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1994-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor, Cygnus Support. + + This file is part of GAS, the GNU Assembler. @@ -493275,13 +497106,12 @@ index 0000000..71e7184 +extern const char *i370_comment_chars; diff --git a/gas/config/tc-i386-intel.c b/gas/config/tc-i386-intel.c new file mode 100644 -index 0000000..6df17e2 +index 0000000..b55d985 --- /dev/null +++ b/gas/config/tc-i386-intel.c -@@ -0,0 +1,1005 @@ +@@ -0,0 +1,1004 @@ +/* tc-i386.c -- Assemble Intel syntax code for ix86/x86-64 -+ Copyright 2009, 2010 -+ Free Software Foundation, Inc. ++ Copyright (C) 2009-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -494286,15 +498116,12 @@ index 0000000..6df17e2 +} diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c new file mode 100644 -index 0000000..c6e1dba +index 0000000..341d100 --- /dev/null +++ b/gas/config/tc-i386.c -@@ -0,0 +1,10562 @@ +@@ -0,0 +1,10617 @@ +/* tc-i386.c -- Assemble code for the Intel 80386 -+ Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, -+ 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, -+ 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1989-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -494808,6 +498635,11 @@ index 0000000..c6e1dba +static enum x86_elf_abi x86_elf_abi = I386_ABI; +#endif + ++#if defined (TE_PE) || defined (TE_PEP) ++/* Use big object file format. */ ++static int use_big_obj = 0; ++#endif ++ +/* 1 for intel syntax, + 0 if att syntax. */ +static int intel_syntax = 0; @@ -495196,6 +499028,16 @@ index 0000000..c6e1dba + CPU_MPX_FLAGS, 0, 0 }, + { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN, + CPU_SHA_FLAGS, 0, 0 }, ++ { STRING_COMMA_LEN (".clflushopt"), PROCESSOR_UNKNOWN, ++ CPU_CLFLUSHOPT_FLAGS, 0, 0 }, ++ { STRING_COMMA_LEN (".xsavec"), PROCESSOR_UNKNOWN, ++ CPU_XSAVEC_FLAGS, 0, 0 }, ++ { STRING_COMMA_LEN (".xsaves"), PROCESSOR_UNKNOWN, ++ CPU_XSAVES_FLAGS, 0, 0 }, ++ { STRING_COMMA_LEN (".prefetchwt1"), PROCESSOR_UNKNOWN, ++ CPU_PREFETCHWT1_FLAGS, 0, 0 }, ++ { STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN, ++ CPU_SE1_FLAGS, 0, 0 }, +}; + +#ifdef I386COFF @@ -495959,8 +499801,6 @@ index 0000000..c6e1dba +static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S; +static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S; +static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4; -+static const i386_operand_type regbnd = OPERAND_TYPE_REGBND; -+static const i386_operand_type vec_disp8 = OPERAND_TYPE_VEC_DISP8; + +enum operand_type +{ @@ -498668,11 +502508,9 @@ index 0000000..c6e1dba + if (i.reg_operands == 2 && !i.mask) + { + gas_assert (i.types[0].bitfield.regxmm -+ || i.types[0].bitfield.regymm -+ || i.types[0].bitfield.regzmm); ++ || i.types[0].bitfield.regymm); + gas_assert (i.types[2].bitfield.regxmm -+ || i.types[2].bitfield.regymm -+ || i.types[2].bitfield.regzmm); ++ || i.types[2].bitfield.regymm); + if (operand_check == check_none) + return 0; + if (register_number (i.op[0].regs) @@ -498689,6 +502527,22 @@ index 0000000..c6e1dba + } + as_warn (_("mask, index, and destination registers should be distinct")); + } ++ else if (i.reg_operands == 1 && i.mask) ++ { ++ if ((i.types[1].bitfield.regymm ++ || i.types[1].bitfield.regzmm) ++ && (register_number (i.op[1].regs) ++ == register_number (i.index_reg))) ++ { ++ if (operand_check == check_error) ++ { ++ i.error = invalid_vector_register_set; ++ return 1; ++ } ++ if (operand_check != check_none) ++ as_warn (_("index and destination registers should be distinct")); ++ } ++ } + } + + /* Check if broadcast is supported by the instruction and is applied @@ -501602,16 +505456,13 @@ index 0000000..c6e1dba + +/* x86_cons_fix_new is called via the expression parsing code when a + reloc is needed. We use this hook to get the correct .got reloc. */ -+static enum bfd_reloc_code_real got_reloc = NO_RELOC; +static int cons_sign = -1; + +void +x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len, -+ expressionS *exp) ++ expressionS *exp, bfd_reloc_code_real_type r) +{ -+ enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, 0, got_reloc); -+ -+ got_reloc = NO_RELOC; ++ r = reloc (len, 0, cons_sign, 0, r); + +#ifdef TE_PE + if (exp->X_op == O_secrel) @@ -501907,9 +505758,11 @@ index 0000000..c6e1dba + +#endif /* TE_PE */ + -+void ++bfd_reloc_code_real_type +x86_cons (expressionS *exp, int size) +{ ++ bfd_reloc_code_real_type got_reloc = NO_RELOC; ++ + intel_syntax = -intel_syntax; + + exp->X_md = 0; @@ -501956,6 +505809,8 @@ index 0000000..c6e1dba + + if (intel_syntax) + i386_intel_simplify (exp); ++ ++ return got_reloc; +} + +static void @@ -503413,8 +507268,21 @@ index 0000000..c6e1dba +#endif + } +#if defined (OBJ_COFF) && defined (TE_PE) -+ if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy)) ++ if (fixP->fx_addsy != NULL ++ && S_IS_WEAK (fixP->fx_addsy) ++ /* PR 16858: Do not modify weak function references. */ ++ && ! fixP->fx_pcrel) + { ++#if !defined (TE_PEP) ++ /* For x86 PE weak function symbols are neither PC-relative ++ nor do they set S_IS_FUNCTION. So the only reliable way ++ to detect them is to check the flags of their containing ++ section. */ ++ if (S_GET_SEGMENT (fixP->fx_addsy) != NULL ++ && S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_CODE) ++ ; ++ else ++#endif + value -= S_GET_VALUE (fixP->fx_addsy); + } +#endif @@ -503772,6 +507640,7 @@ index 0000000..c6e1dba +#define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15) +#define OPTION_MEVEXLIG (OPTION_MD_BASE + 16) +#define OPTION_MEVEXWIG (OPTION_MD_BASE + 17) ++#define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18) + +struct option md_longopts[] = +{ @@ -503798,6 +507667,9 @@ index 0000000..c6e1dba + {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX}, + {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG}, + {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG}, ++# if defined (TE_PE) || defined (TE_PEP) ++ {"mbig-obj", no_argument, NULL, OPTION_MBIG_OBJ}, ++#endif + {NULL, no_argument, NULL, 0} +}; +size_t md_longopts_size = sizeof (md_longopts); @@ -504079,6 +507951,12 @@ index 0000000..c6e1dba + as_fatal (_("invalid -mevexwig= option: `%s'"), arg); + break; + ++# if defined (TE_PE) || defined (TE_PEP) ++ case OPTION_MBIG_OBJ: ++ use_big_obj = 1; ++ break; ++#endif ++ + default: + return 0; + } @@ -504231,6 +508109,10 @@ index 0000000..c6e1dba + -mold-gcc support old (<= 2.8.1) versions of gcc\n")); + fprintf (stream, _("\ + -madd-bnd-prefix add BND prefix for all valid branches\n")); ++# if defined (TE_PE) || defined (TE_PEP) ++ fprintf (stream, _("\ ++ -mbig-obj generate big object files\n")); ++#endif +} + +#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ @@ -504269,7 +508151,10 @@ index 0000000..c6e1dba +#if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF) +# if defined (TE_PE) || defined (TE_PEP) + case bfd_target_coff_flavour: -+ return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386"; ++ if (flag_code == CODE_64BIT) ++ return use_big_obj ? "pe-bigobj-x86-64" : "pe-x86-64"; ++ else ++ return "pe-i386"; +# elif defined (TE_GO32) + case bfd_target_coff_flavour: + return "coff-go32"; @@ -504854,14 +508739,12 @@ index 0000000..c6e1dba +#endif /* OBJ_ELF || OBJ_MAYBE_ELF */ diff --git a/gas/config/tc-i386.h b/gas/config/tc-i386.h new file mode 100644 -index 0000000..de132d6 +index 0000000..8b5c7d7 --- /dev/null +++ b/gas/config/tc-i386.h -@@ -0,0 +1,342 @@ +@@ -0,0 +1,341 @@ +/* tc-i386.h -- Header file for tc-i386.c -+ Copyright 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, -+ 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1989-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -504994,11 +508877,12 @@ index 0000000..de132d6 +#if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && !defined (LEX_AT) +#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) x86_cons (EXP, NBYTES) +#endif -+extern void x86_cons (expressionS *, int); ++extern bfd_reloc_code_real_type x86_cons (expressionS *, int); + -+#define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) x86_cons_fix_new(FRAG, OFF, LEN, EXP) ++#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP, RELOC) \ ++ x86_cons_fix_new(FRAG, OFF, LEN, EXP, RELOC) +extern void x86_cons_fix_new -+ (fragS *, unsigned int, unsigned int, expressionS *); ++(fragS *, unsigned int, unsigned int, expressionS *, bfd_reloc_code_real_type); + +#define TC_ADDRESS_BYTES x86_address_bytes +extern int x86_address_bytes (void); @@ -505202,13 +509086,12 @@ index 0000000..de132d6 +#endif /* TC_I386 */ diff --git a/gas/config/tc-i860.c b/gas/config/tc-i860.c new file mode 100644 -index 0000000..32aed0f +index 0000000..1b55b80 --- /dev/null +++ b/gas/config/tc-i860.c -@@ -0,0 +1,1492 @@ +@@ -0,0 +1,1491 @@ +/* tc-i860.c -- Assembler for the Intel i860 architecture. -+ Copyright 1989, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2002, -+ 2003, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. ++ Copyright (C) 1989-2014 Free Software Foundation, Inc. + + Brought back from the dead and completely reworked + by Jason Eckhardt . @@ -506700,13 +510583,12 @@ index 0000000..32aed0f +} diff --git a/gas/config/tc-i860.h b/gas/config/tc-i860.h new file mode 100644 -index 0000000..c261892 +index 0000000..692ea30 --- /dev/null +++ b/gas/config/tc-i860.h -@@ -0,0 +1,96 @@ +@@ -0,0 +1,95 @@ +/* tc-i860.h -- Header file for the i860. -+ Copyright 1991, 1992, 1995, 1998, 2000, 2001, 2002, 2003, 2005, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + + Brought back from the dead and completely reworked + by Jason Eckhardt . @@ -506802,14 +510684,12 @@ index 0000000..c261892 +#endif /* TC_I860 */ diff --git a/gas/config/tc-i960.c b/gas/config/tc-i960.c new file mode 100644 -index 0000000..44664df +index 0000000..7595e1d --- /dev/null +++ b/gas/config/tc-i960.c -@@ -0,0 +1,2669 @@ +@@ -0,0 +1,2667 @@ +/* tc-i960.c - All the i80960-specific stuff -+ Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, -+ 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2009, 2010 -+ Free Software Foundation, Inc. ++ Copyright (C) 1989-2014 Free Software Foundation, Inc. + + This file is part of GAS. + @@ -509477,14 +513357,12 @@ index 0000000..44664df +}; diff --git a/gas/config/tc-i960.h b/gas/config/tc-i960.h new file mode 100644 -index 0000000..3949b6c +index 0000000..ee6d050 --- /dev/null +++ b/gas/config/tc-i960.h -@@ -0,0 +1,188 @@ +@@ -0,0 +1,186 @@ +/* tc-i960.h - Basic 80960 instruction formats. -+ Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1997, 1998, 1999, -+ 2000, 2001, 2002, 2003, 2005, 2007, 2008 -+ Free Software Foundation, Inc. ++ Copyright (C) 1989-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -509671,12 +513549,12 @@ index 0000000..3949b6c +#endif diff --git a/gas/config/tc-ia64.c b/gas/config/tc-ia64.c new file mode 100644 -index 0000000..b8ffe4e +index 0000000..38b6b67 --- /dev/null +++ b/gas/config/tc-ia64.c -@@ -0,0 +1,12069 @@ +@@ -0,0 +1,12070 @@ +/* tc-ia64.c -- Assembler for the HP/Intel IA-64 architecture. -+ Copyright 1998-2013 Free Software Foundation, Inc. ++ Copyright (C) 1998-2014 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of GAS, the GNU Assembler. @@ -514143,14 +518021,15 @@ index 0000000..b8ffe4e + symbol_get_frag (unwind.proc_pending.sym)); + else + e.X_add_symbol = unwind.proc_pending.sym; -+ ia64_cons_fix_new (frag_now, where, bytes_per_address, &e); ++ ia64_cons_fix_new (frag_now, where, bytes_per_address, &e, ++ BFD_RELOC_NONE); + + e.X_op = O_pseudo_fixup; + e.X_op_symbol = pseudo_func[FUNC_SEG_RELATIVE].u.sym; + e.X_add_number = 0; + e.X_add_symbol = proc_end; + ia64_cons_fix_new (frag_now, where + bytes_per_address, -+ bytes_per_address, &e); ++ bytes_per_address, &e, BFD_RELOC_NONE); + + if (unwind.info) + { @@ -514159,7 +518038,7 @@ index 0000000..b8ffe4e + e.X_add_number = 0; + e.X_add_symbol = unwind.info; + ia64_cons_fix_new (frag_now, where + (bytes_per_address * 2), -+ bytes_per_address, &e); ++ bytes_per_address, &e, BFD_RELOC_NONE); + } + } + subseg_set (saved_seg, saved_subseg); @@ -520733,9 +524612,9 @@ index 0000000..b8ffe4e + fixup. We pick the right reloc code depending on the byteorder + currently in effect. */ +void -+ia64_cons_fix_new (fragS *f, int where, int nbytes, expressionS *exp) ++ia64_cons_fix_new (fragS *f, int where, int nbytes, expressionS *exp, ++ bfd_reloc_code_real_type code) +{ -+ bfd_reloc_code_real_type code; + fixS *fix; + + switch (nbytes) @@ -521746,13 +525625,12 @@ index 0000000..b8ffe4e +#endif /* TE_VMS */ diff --git a/gas/config/tc-ia64.h b/gas/config/tc-ia64.h new file mode 100644 -index 0000000..7cade49 +index 0000000..6884c59 --- /dev/null +++ b/gas/config/tc-ia64.h @@ -0,0 +1,331 @@ +/* tc-ia64.h -- Header file for tc-ia64.c. -+ Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008, -+ 2009, 2010 Free Software Foundation, Inc. ++ Copyright (C) 1998-2014 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of GAS, the GNU Assembler. @@ -521859,7 +525737,8 @@ index 0000000..7cade49 +extern void ia64_flush_insns (void); +extern int ia64_fix_adjustable (struct fix *); +extern int ia64_force_relocation (struct fix *); -+extern void ia64_cons_fix_new (fragS *, int, int, expressionS *); ++extern void ia64_cons_fix_new (fragS *, int, int, expressionS *, ++ bfd_reloc_code_real_type); +extern void ia64_validate_fix (struct fix *); +extern char * ia64_canonicalize_symbol_name (char *); +extern bfd_vma ia64_elf_section_letter (int, char **); @@ -521901,7 +525780,7 @@ index 0000000..7cade49 +#define md_elf_section_flags ia64_elf_section_flags +#define TC_FIX_TYPE struct ia64_fix +#define TC_INIT_FIX_DATA(f) { f->tc_fix_data.opnd = 0; } -+#define TC_CONS_FIX_NEW(f,o,l,e) ia64_cons_fix_new (f, o, l, e) ++#define TC_CONS_FIX_NEW(f,o,l,e,r) ia64_cons_fix_new (f, o, l, e, r) +#define TC_VALIDATE_FIX(fix,seg,skip) ia64_validate_fix (fix) +#define MD_PCREL_FROM_SECTION(fix,sec) ia64_pcrel_from_section (fix, sec) +#define md_section_align(seg,size) (size) @@ -522083,13 +525962,12 @@ index 0000000..7cade49 +#endif diff --git a/gas/config/tc-ip2k.c b/gas/config/tc-ip2k.c new file mode 100644 -index 0000000..3836cc9 +index 0000000..9c8c22c --- /dev/null +++ b/gas/config/tc-ip2k.c -@@ -0,0 +1,427 @@ +@@ -0,0 +1,426 @@ +/* tc-ip2k.c -- Assembler for the Scenix IP2xxx. -+ Copyright (C) 2000, 2002, 2003, 2005, 2006, 2007, 2009 -+ Free Software Foundation. Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -522516,12 +526394,12 @@ index 0000000..3836cc9 + diff --git a/gas/config/tc-ip2k.h b/gas/config/tc-ip2k.h new file mode 100644 -index 0000000..01efdc2 +index 0000000..c33ab2b --- /dev/null +++ b/gas/config/tc-ip2k.h @@ -0,0 +1,65 @@ +/* tc-ip2k.h -- Header file for tc-ip2k.c. -+ Copyright (C) 2000, 2002, 2005, 2007, 2009 Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -522587,13 +526465,12 @@ index 0000000..01efdc2 +extern void gas_cgen_md_operand (expressionS *); diff --git a/gas/config/tc-iq2000.c b/gas/config/tc-iq2000.c new file mode 100644 -index 0000000..e8ed21d +index 0000000..7939abc --- /dev/null +++ b/gas/config/tc-iq2000.c -@@ -0,0 +1,988 @@ +@@ -0,0 +1,987 @@ +/* tc-iq2000.c -- Assembler for the Sitera IQ2000. -+ Copyright (C) 2003, 2004, 2005, 2006, 2007, 2009, 2010 -+ Free Software Foundation. Inc. ++ Copyright (C) 2003-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -523581,12 +527458,12 @@ index 0000000..e8ed21d +}; diff --git a/gas/config/tc-iq2000.h b/gas/config/tc-iq2000.h new file mode 100644 -index 0000000..0b1de12 +index 0000000..ab4f877 --- /dev/null +++ b/gas/config/tc-iq2000.h @@ -0,0 +1,65 @@ +/* tc-iq2000.h -- Header file for tc-iq2000.c. -+ Copyright (C) 2003, 2004, 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 2003-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -523652,12 +527529,12 @@ index 0000000..0b1de12 +extern long md_pcrel_from_section (struct fix *, segT); diff --git a/gas/config/tc-lm32.c b/gas/config/tc-lm32.c new file mode 100644 -index 0000000..88ffabb +index 0000000..07c8c82 --- /dev/null +++ b/gas/config/tc-lm32.c @@ -0,0 +1,421 @@ +/* tc-lm32.c - Lattice Mico32 assembler. -+ Copyright 2008, 2012 Free Software Foundation, Inc. ++ Copyright (C) 2008-2014 Free Software Foundation, Inc. + Contributed by Jon Beniston + + This file is part of GAS, the GNU Assembler. @@ -524079,12 +527956,12 @@ index 0000000..88ffabb +} diff --git a/gas/config/tc-lm32.h b/gas/config/tc-lm32.h new file mode 100644 -index 0000000..dbba939 +index 0000000..295efc1 --- /dev/null +++ b/gas/config/tc-lm32.h @@ -0,0 +1,50 @@ +/* tc-lm32.h -- Header file for tc-lm32.c -+ Copyright 2008 Free Software Foundation, Inc. ++ Copyright (C) 2008-2014 Free Software Foundation, Inc. + Contributed by Jon Beniston + + This file is part of GAS, the GNU Assembler. @@ -524135,12 +528012,12 @@ index 0000000..dbba939 + diff --git a/gas/config/tc-m32c.c b/gas/config/tc-m32c.c new file mode 100644 -index 0000000..9c523e2 +index 0000000..8e24edb --- /dev/null +++ b/gas/config/tc-m32c.c -@@ -0,0 +1,1295 @@ +@@ -0,0 +1,1294 @@ +/* tc-m32c.c -- Assembler for the Renesas M32C. -+ Copyright (C) 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation. ++ Copyright (C) 2005-2014 Free Software Foundation, Inc. + Contributed by RedHat. + + This file is part of GAS, the GNU Assembler. @@ -525160,10 +529037,9 @@ index 0000000..9c523e2 +m32c_cons_fix_new (fragS * frag, + int where, + int size, -+ expressionS *exp) ++ expressionS *exp, ++ bfd_reloc_code_real_type type) +{ -+ bfd_reloc_code_real_type type; -+ + switch (size) + { + case 1: @@ -525436,13 +529312,12 @@ index 0000000..9c523e2 +} diff --git a/gas/config/tc-m32c.h b/gas/config/tc-m32c.h new file mode 100644 -index 0000000..b69ab50 +index 0000000..3af0092 --- /dev/null +++ b/gas/config/tc-m32c.h @@ -0,0 +1,87 @@ +/* tc-m32c.h -- Header file for tc-m32c.c. -+ Copyright (C) 2004, 2005, 2006, 2007, 2008, 2009 -+ Free Software Foundation, Inc. ++ Copyright (C) 2004-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -525500,9 +529375,10 @@ index 0000000..b69ab50 +#define TC_FORCE_RELOCATION(fix) m32c_force_relocation (fix) +extern int m32c_force_relocation (struct fix *); + -+#define TC_CONS_FIX_NEW(FRAG, WHERE, NBYTES, EXP) \ -+ m32c_cons_fix_new (FRAG, WHERE, NBYTES, EXP) -+extern void m32c_cons_fix_new (fragS *, int, int, expressionS *); ++#define TC_CONS_FIX_NEW(FRAG, WHERE, NBYTES, EXP, RELOC) \ ++ m32c_cons_fix_new (FRAG, WHERE, NBYTES, EXP, RELOC) ++extern void m32c_cons_fix_new (fragS *, int, int, expressionS *, ++ bfd_reloc_code_real_type); + +extern const struct relax_type md_relax_table[]; +#define TC_GENERIC_RELAX_TABLE md_relax_table @@ -525529,13 +529405,12 @@ index 0000000..b69ab50 +#define H_TICK_HEX 1 diff --git a/gas/config/tc-m32r.c b/gas/config/tc-m32r.c new file mode 100644 -index 0000000..c8a6584 +index 0000000..172b8f9 --- /dev/null +++ b/gas/config/tc-m32r.c -@@ -0,0 +1,2410 @@ +@@ -0,0 +1,2409 @@ +/* tc-m32r.c -- Assembler for the Renesas M32R. -+ Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, -+ 2006, 2007, 2009, 2011, 2012 Free Software Foundation, Inc. ++ Copyright (C) 1996-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -527945,13 +531820,12 @@ index 0000000..c8a6584 +} diff --git a/gas/config/tc-m32r.h b/gas/config/tc-m32r.h new file mode 100644 -index 0000000..3265712 +index 0000000..892b3ab --- /dev/null +++ b/gas/config/tc-m32r.h -@@ -0,0 +1,126 @@ +@@ -0,0 +1,125 @@ +/* tc-m32r.h -- Header file for tc-m32r.c. -+ Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, -+ 2007, 2009, 2011 Free Software Foundation, Inc. ++ Copyright (C) 1996-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -528077,14 +531951,13 @@ index 0000000..3265712 +extern int m32r_cgen_parse_fix_exp (int, expressionS *); diff --git a/gas/config/tc-m68851.h b/gas/config/tc-m68851.h new file mode 100644 -index 0000000..79121f1 +index 0000000..7c449d6 --- /dev/null +++ b/gas/config/tc-m68851.h -@@ -0,0 +1,277 @@ +@@ -0,0 +1,276 @@ +/* This file is tc-m68851.h + -+ Copyright 1987, 1988, 1989, 1990, 1991, 1992, 2000, 2005, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -528360,14 +532233,12 @@ index 0000000..79121f1 +#endif /* m68851 */ diff --git a/gas/config/tc-m68hc11.c b/gas/config/tc-m68hc11.c new file mode 100644 -index 0000000..3189121 +index 0000000..3641912 --- /dev/null +++ b/gas/config/tc-m68hc11.c -@@ -0,0 +1,4501 @@ +@@ -0,0 +1,4499 @@ +/* tc-m68hc11.c -- Assembler code for the Motorola 68HC11 & 68HC12. -+ Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2009, 2010, -+ 2011, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1999-2014 Free Software Foundation, Inc. + Written by Stephane Carrez (stcarrez@nerim.fr) + XGATE and S12X added by James Murray (jsm@jsm-net.demon.co.uk) + @@ -532867,13 +536738,12 @@ index 0000000..3189121 +} diff --git a/gas/config/tc-m68hc11.h b/gas/config/tc-m68hc11.h new file mode 100644 -index 0000000..51c489c +index 0000000..59079dd --- /dev/null +++ b/gas/config/tc-m68hc11.h -@@ -0,0 +1,109 @@ +@@ -0,0 +1,108 @@ +/* tc-m68hc11.h -- Header file for tc-m68hc11.c. -+ Copyright 1999, 2000, 2001, 2002, 2003, 2005, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1999-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -532982,14 +536852,12 @@ index 0000000..51c489c +extern void m68hc11_print_statistics (FILE *); diff --git a/gas/config/tc-m68k.c b/gas/config/tc-m68k.c new file mode 100644 -index 0000000..d16b5d9 +index 0000000..2005cd2 --- /dev/null +++ b/gas/config/tc-m68k.c -@@ -0,0 +1,8149 @@ +@@ -0,0 +1,8147 @@ +/* tc-m68k.c -- Assemble for the m68k family -+ Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, -+ 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -541137,14 +545005,12 @@ index 0000000..d16b5d9 + diff --git a/gas/config/tc-m68k.h b/gas/config/tc-m68k.h new file mode 100644 -index 0000000..bf938f2 +index 0000000..3978b6a --- /dev/null +++ b/gas/config/tc-m68k.h -@@ -0,0 +1,196 @@ +@@ -0,0 +1,194 @@ +/* This file is tc-m68k.h -+ Copyright 1987, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, -+ 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -541339,13 +545205,12 @@ index 0000000..bf938f2 + struct broken_word *); diff --git a/gas/config/tc-mcore.c b/gas/config/tc-mcore.c new file mode 100644 -index 0000000..04cf336 +index 0000000..d111eda --- /dev/null +++ b/gas/config/tc-mcore.c -@@ -0,0 +1,2236 @@ +@@ -0,0 +1,2235 @@ +/* tc-mcore.c -- Assemble code for M*Core -+ Copyright 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009 -+ Free Software Foundation, Inc. ++ Copyright (C) 1999-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -543581,14 +547446,13 @@ index 0000000..04cf336 +#endif /* OBJ_ELF */ diff --git a/gas/config/tc-mcore.h b/gas/config/tc-mcore.h new file mode 100644 -index 0000000..36087c6 +index 0000000..3437e00 --- /dev/null +++ b/gas/config/tc-mcore.h -@@ -0,0 +1,96 @@ +@@ -0,0 +1,95 @@ +/* This file is tc-mcore.h + -+ Copyright 1999, 2000, 2001, 2002, 2003, 2005, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1999-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -543683,13 +547547,12 @@ index 0000000..36087c6 +#endif /* TC_MCORE */ diff --git a/gas/config/tc-mep.c b/gas/config/tc-mep.c new file mode 100644 -index 0000000..377e4c3 +index 0000000..cb06881 --- /dev/null +++ b/gas/config/tc-mep.c -@@ -0,0 +1,2203 @@ +@@ -0,0 +1,2202 @@ +/* tc-mep.c -- Assembler for the Toshiba Media Processor. -+ Copyright (C) 2001, 2002, 2003, 2004, 2005, 2007, 2009, 2012 -+ Free Software Foundation. Inc. ++ Copyright (C) 2001-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -545892,12 +549755,12 @@ index 0000000..377e4c3 +} diff --git a/gas/config/tc-mep.h b/gas/config/tc-mep.h new file mode 100644 -index 0000000..59f83b0 +index 0000000..0df5de8 --- /dev/null +++ b/gas/config/tc-mep.h @@ -0,0 +1,119 @@ +/* tc-mep.h -- Header file for tc-mep.c. -+ Copyright (C) 2001, 2002, 2005, 2007, 2009 Free Software Foundation, Inc. ++ Copyright (C) 2001-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -546017,12 +549880,12 @@ index 0000000..59f83b0 +typedef enum exp_par_insn_{FIRST, SECOND} EXP_PAR_INSN; diff --git a/gas/config/tc-metag.c b/gas/config/tc-metag.c new file mode 100644 -index 0000000..f42d2f1 +index 0000000..cb2fc99 --- /dev/null +++ b/gas/config/tc-metag.c @@ -0,0 +1,7141 @@ +/* tc-metag.c -- Assembler for the Imagination Technologies Meta. -+ Copyright (C) 2013 Free Software Foundation, Inc. ++ Copyright (C) 2013-2014 Free Software Foundation, Inc. + Contributed by Imagination Technologies Ltd. + + This file is part of GAS, the GNU Assembler. @@ -553164,12 +557027,12 @@ index 0000000..f42d2f1 +} diff --git a/gas/config/tc-metag.h b/gas/config/tc-metag.h new file mode 100644 -index 0000000..e0411f5 +index 0000000..10a2c7b --- /dev/null +++ b/gas/config/tc-metag.h @@ -0,0 +1,72 @@ +/* tc-metag.h -- Header file for tc-metag.c. -+ Copyright (C) 2013 Free Software Foundation, Inc. ++ Copyright (C) 2013-2014 Free Software Foundation, Inc. + Contributed by Imagination Technologies Ltd. + + This file is part of GAS, the GNU Assembler. @@ -553242,13 +557105,13 @@ index 0000000..e0411f5 +#define tc_symbol_chars metag_symbol_chars diff --git a/gas/config/tc-microblaze.c b/gas/config/tc-microblaze.c new file mode 100644 -index 0000000..872737b +index 0000000..cf4ee44 --- /dev/null +++ b/gas/config/tc-microblaze.c -@@ -0,0 +1,2525 @@ +@@ -0,0 +1,2524 @@ +/* tc-microblaze.c -- Assemble code for Xilinx MicroBlaze + -+ Copyright 2009, 2010, 2012 Free Software Foundation. ++ Copyright (C) 2009-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -554050,7 +557913,7 @@ index 0000000..872737b + return tmpbuf; +} + -+extern void ++extern bfd_reloc_code_real_type +parse_cons_expression_microblaze (expressionS *exp, int size) +{ + if (size == 4) @@ -554076,6 +557939,7 @@ index 0000000..872737b + } + else + expression (exp); ++ return BFD_RELOC_NONE; +} + +/* This is the guts of the machine-dependent assembler. STR points to a @@ -555733,11 +559597,9 @@ index 0000000..872737b +cons_fix_new_microblaze (fragS * frag, + int where, + int size, -+ expressionS *exp) ++ expressionS *exp, ++ bfd_reloc_code_real_type r) +{ -+ -+ bfd_reloc_code_real_type r; -+ + if ((exp->X_op == O_subtract) && (exp->X_add_symbol) && + (exp->X_op_symbol) && (now_seg != absolute_section) && (size == 4) + && (!S_IS_LOCAL (exp->X_op_symbol))) @@ -555773,13 +559635,13 @@ index 0000000..872737b +} diff --git a/gas/config/tc-microblaze.h b/gas/config/tc-microblaze.h new file mode 100644 -index 0000000..340f533 +index 0000000..d44f2fa --- /dev/null +++ b/gas/config/tc-microblaze.h -@@ -0,0 +1,116 @@ +@@ -0,0 +1,120 @@ +/* tc-microblaze.h -- Header file for tc-microblaze.c. + -+ Copyright 2009, 2014 Free Software Foundation, Inc. ++ Copyright (C) 2009-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -555815,8 +559677,10 @@ index 0000000..340f533 + relocs for such expressions as -relax in linker can change the value + of such expressions */ +#define TC_CONS_FIX_NEW cons_fix_new_microblaze -+#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) parse_cons_expression_microblaze (EXP, NBYTES) -+extern void parse_cons_expression_microblaze (expressionS *, int); ++#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) \ ++ parse_cons_expression_microblaze (EXP, NBYTES) ++extern bfd_reloc_code_real_type parse_cons_expression_microblaze ++ (expressionS *, int); + +#define TC_FORCE_RELOCATION_SECTION(FIXP,SEG) 1 +#define UNDEFINED_DIFFERENCE_OK 1 @@ -555887,7 +559751,9 @@ index 0000000..340f533 +extern valueT md_section_align (segT, valueT); +extern long md_pcrel_from_section (fixS *, segT); +extern arelent * tc_gen_reloc (asection *, fixS *); -+extern void cons_fix_new_microblaze (fragS *, int, int, expressionS *); ++extern void cons_fix_new_microblaze (fragS *, int, int, ++ expressionS *, ++ bfd_reloc_code_real_type); +extern void md_apply_fix3 (fixS *, valueT *, segT); + +#define EXTERN_FORCE_RELOC -1 @@ -555895,14 +559761,12 @@ index 0000000..340f533 +#endif /* TC_MICROBLAZE */ diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c new file mode 100644 -index 0000000..34f1bf0 +index 0000000..4814a69 --- /dev/null +++ b/gas/config/tc-mips.c -@@ -0,0 +1,18251 @@ +@@ -0,0 +1,18411 @@ +/* tc-mips.c -- assemble code for a MIPS chip. -+ Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, -+ 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 -+ Free Software Foundation, Inc. ++ Copyright (C) 1993-2014 Free Software Foundation, Inc. + Contributed by the OSF and Ralph Campbell. + Written by Keith Knowles and Ralph Campbell, working independently. + Modified for ECOFF and R4000 support by Ian Lance Taylor of Cygnus @@ -555945,6 +559809,8 @@ index 0000000..34f1bf0 +#define DBG(x) +#endif + ++#define streq(a, b) (strcmp (a, b) == 0) ++ +#define SKIP_SPACE_TABS(S) \ + do { while (*(S) == ' ' || *(S) == '\t') ++(S); } while (0) + @@ -556142,8 +560008,8 @@ index 0000000..34f1bf0 + /* Restrict general purpose registers and floating point registers + to 32 bit. This is initially determined when -mgp32 or -mfp32 + is passed but can changed if the assembler code uses .set mipsN. */ -+ int gp32; -+ int fp32; ++ int gp; ++ int fp; + /* MIPS architecture (CPU) type. Changed by .set arch=FOO, the -march + command line option, and the default CPU. */ + int arch; @@ -556160,38 +560026,36 @@ index 0000000..34f1bf0 + bfd_boolean single_float; +}; + -+/* This is the struct we use to hold the current set of options. Note -+ that we must set the isa field to ISA_UNKNOWN and the ASE fields to -+ -1 to indicate that they have not been initialized. */ -+ -+/* True if -mgp32 was passed. */ -+static int file_mips_gp32 = -1; -+ -+/* True if -mfp32 was passed. */ -+static int file_mips_fp32 = -1; -+ -+/* 1 if -msoft-float, 0 if -mhard-float. The default is 0. */ -+static int file_mips_soft_float = 0; -+ -+/* 1 if -msingle-float, 0 if -mdouble-float. The default is 0. */ -+static int file_mips_single_float = 0; ++/* Specifies whether module level options have been checked yet. */ ++static bfd_boolean file_mips_opts_checked = FALSE; + +/* True if -mnan=2008, false if -mnan=legacy. */ +static bfd_boolean mips_flag_nan2008 = FALSE; + ++/* This is the struct we use to hold the module level set of options. ++ Note that we must set the isa field to ISA_UNKNOWN and the ASE, gp and ++ fp fields to -1 to indicate that they have not been initialized. */ ++ ++static struct mips_set_options file_mips_opts = ++{ ++ /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, ++ /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, ++ /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, ++ /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, ++ /* soft_float */ FALSE, /* single_float */ FALSE ++}; ++ ++/* This is similar to file_mips_opts, but for the current set of options. */ ++ +static struct mips_set_options mips_opts = +{ + /* isa */ ISA_UNKNOWN, /* ase */ 0, /* mips16 */ -1, /* micromips */ -1, + /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, + /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, -+ /* gp32 */ 0, /* fp32 */ 0, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, ++ /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, + /* soft_float */ FALSE, /* single_float */ FALSE +}; + -+/* The set of ASEs that were selected on the command line, either -+ explicitly via ASE options or implicitly through things like -march. */ -+static unsigned int file_ase; -+ +/* Which bits of file_ase were explicitly set or cleared by ASE options. */ +static unsigned int file_ase_explicit; + @@ -556201,16 +560065,17 @@ index 0000000..34f1bf0 +unsigned long mips_gprmask; +unsigned long mips_cprmask[4]; + -+/* MIPS ISA we are using for this output file. */ -+static int file_mips_isa = ISA_UNKNOWN; -+ +/* True if any MIPS16 code was produced. */ +static int file_ase_mips16; + +#define ISA_SUPPORTS_MIPS16E (mips_opts.isa == ISA_MIPS32 \ + || mips_opts.isa == ISA_MIPS32R2 \ ++ || mips_opts.isa == ISA_MIPS32R3 \ ++ || mips_opts.isa == ISA_MIPS32R5 \ + || mips_opts.isa == ISA_MIPS64 \ -+ || mips_opts.isa == ISA_MIPS64R2) ++ || mips_opts.isa == ISA_MIPS64R2 \ ++ || mips_opts.isa == ISA_MIPS64R3 \ ++ || mips_opts.isa == ISA_MIPS64R5) + +/* True if any microMIPS code was produced. */ +static int file_ase_micromips; @@ -556228,7 +560093,6 @@ index 0000000..34f1bf0 +#endif + +/* The argument of the -march= flag. The architecture we are assembling. */ -+static int file_mips_arch = CPU_UNKNOWN; +static const char *mips_arch_string; + +/* The argument of the -mtune= flag. The architecture for which we @@ -556254,7 +560118,9 @@ index 0000000..34f1bf0 + || (ISA) == ISA_MIPS4 \ + || (ISA) == ISA_MIPS5 \ + || (ISA) == ISA_MIPS64 \ -+ || (ISA) == ISA_MIPS64R2) ++ || (ISA) == ISA_MIPS64R2 \ ++ || (ISA) == ISA_MIPS64R3 \ ++ || (ISA) == ISA_MIPS64R5) + +/* Return true if ISA supports 64 bit wide float registers. */ +#define ISA_HAS_64BIT_FPRS(ISA) \ @@ -556262,13 +560128,19 @@ index 0000000..34f1bf0 + || (ISA) == ISA_MIPS4 \ + || (ISA) == ISA_MIPS5 \ + || (ISA) == ISA_MIPS32R2 \ ++ || (ISA) == ISA_MIPS32R3 \ ++ || (ISA) == ISA_MIPS32R5 \ + || (ISA) == ISA_MIPS64 \ -+ || (ISA) == ISA_MIPS64R2) ++ || (ISA) == ISA_MIPS64R2 \ ++ || (ISA) == ISA_MIPS64R3 \ ++ || (ISA) == ISA_MIPS64R5 ) + +/* Return true if ISA supports 64-bit right rotate (dror et al.) + instructions. */ +#define ISA_HAS_DROR(ISA) \ + ((ISA) == ISA_MIPS64R2 \ ++ || (ISA) == ISA_MIPS64R3 \ ++ || (ISA) == ISA_MIPS64R5 \ + || (mips_opts.micromips \ + && ISA_HAS_64BIT_REGS (ISA)) \ + ) @@ -556277,7 +560149,11 @@ index 0000000..34f1bf0 + instructions. */ +#define ISA_HAS_ROR(ISA) \ + ((ISA) == ISA_MIPS32R2 \ ++ || (ISA) == ISA_MIPS32R3 \ ++ || (ISA) == ISA_MIPS32R5 \ + || (ISA) == ISA_MIPS64R2 \ ++ || (ISA) == ISA_MIPS64R3 \ ++ || (ISA) == ISA_MIPS64R5 \ + || (mips_opts.ase & ASE_SMARTMIPS) \ + || mips_opts.micromips \ + ) @@ -556286,23 +560162,32 @@ index 0000000..34f1bf0 +#define ISA_HAS_ODD_SINGLE_FPR(ISA) \ + ((ISA) == ISA_MIPS32 \ + || (ISA) == ISA_MIPS32R2 \ ++ || (ISA) == ISA_MIPS32R3 \ ++ || (ISA) == ISA_MIPS32R5 \ + || (ISA) == ISA_MIPS64 \ -+ || (ISA) == ISA_MIPS64R2) ++ || (ISA) == ISA_MIPS64R2 \ ++ || (ISA) == ISA_MIPS64R3 \ ++ || (ISA) == ISA_MIPS64R5) + +/* Return true if ISA supports move to/from high part of a 64-bit + floating-point register. */ +#define ISA_HAS_MXHC1(ISA) \ + ((ISA) == ISA_MIPS32R2 \ -+ || (ISA) == ISA_MIPS64R2) ++ || (ISA) == ISA_MIPS32R3 \ ++ || (ISA) == ISA_MIPS32R5 \ ++ || (ISA) == ISA_MIPS64R2 \ ++ || (ISA) == ISA_MIPS64R3 \ ++ || (ISA) == ISA_MIPS64R5) + -+#define HAVE_32BIT_GPRS \ -+ (mips_opts.gp32 || !ISA_HAS_64BIT_REGS (mips_opts.isa)) ++#define GPR_SIZE \ ++ (mips_opts.gp == 64 && !ISA_HAS_64BIT_REGS (mips_opts.isa) \ ++ ? 32 \ ++ : mips_opts.gp) + -+#define HAVE_32BIT_FPRS \ -+ (mips_opts.fp32 || !ISA_HAS_64BIT_FPRS (mips_opts.isa)) -+ -+#define HAVE_64BIT_GPRS (!HAVE_32BIT_GPRS) -+#define HAVE_64BIT_FPRS (!HAVE_32BIT_FPRS) ++#define FPR_SIZE \ ++ (mips_opts.fp == 64 && !ISA_HAS_64BIT_FPRS (mips_opts.isa) \ ++ ? 32 \ ++ : mips_opts.fp) + +#define HAVE_NEWABI (mips_abi == N32_ABI || mips_abi == N64_ABI) + @@ -556313,7 +560198,7 @@ index 0000000..34f1bf0 + +/* The ABI-derived address size. */ +#define HAVE_64BIT_ADDRESSES \ -+ (HAVE_64BIT_GPRS && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) ++ (GPR_SIZE == 64 && (mips_abi == EABI_ABI || mips_abi == N64_ABI)) +#define HAVE_32BIT_ADDRESSES (!HAVE_64BIT_ADDRESSES) + +/* The size of symbolic constants (i.e., expressions of the form @@ -556376,8 +560261,12 @@ index 0000000..34f1bf0 +#define hilo_interlocks \ + (mips_opts.isa == ISA_MIPS32 \ + || mips_opts.isa == ISA_MIPS32R2 \ ++ || mips_opts.isa == ISA_MIPS32R3 \ ++ || mips_opts.isa == ISA_MIPS32R5 \ + || mips_opts.isa == ISA_MIPS64 \ + || mips_opts.isa == ISA_MIPS64R2 \ ++ || mips_opts.isa == ISA_MIPS64R3 \ ++ || mips_opts.isa == ISA_MIPS64R5 \ + || mips_opts.arch == CPU_R4010 \ + || mips_opts.arch == CPU_R5900 \ + || mips_opts.arch == CPU_R10000 \ @@ -556440,7 +560329,7 @@ index 0000000..34f1bf0 + ((mips_opts.mips16 | mips_opts.micromips) != 0) + +/* The minimum and maximum signed values that can be stored in a GPR. */ -+#define GPR_SMAX ((offsetT) (((valueT) 1 << (HAVE_64BIT_GPRS ? 63 : 31)) - 1)) ++#define GPR_SMAX ((offsetT) (((valueT) 1 << (GPR_SIZE - 1)) - 1)) +#define GPR_SMIN (-GPR_SMAX - 1) + +/* MIPS PIC level. */ @@ -557172,8 +561061,7 @@ index 0000000..34f1bf0 +static void s_cpadd (int); +static void s_insn (int); +static void s_nan (int); -+static void md_obj_begin (void); -+static void md_obj_end (void); ++static void s_module (int); +static void s_mips_ent (int); +static void s_mips_end (int); +static void s_mips_frame (int); @@ -557186,6 +561074,7 @@ index 0000000..34f1bf0 +static int relaxed_branch_length (fragS *, asection *, int); +static int relaxed_micromips_16bit_branch_length (fragS *, asection *, int); +static int relaxed_micromips_32bit_branch_length (fragS *, asection *, int); ++static void file_mips_check_options (void); + +/* Table and functions used to map between CPU/ISA names, and + ISA levels, and CPU numbers. */ @@ -557220,7 +561109,11 @@ index 0000000..34f1bf0 + OPTION_MIPS32, + OPTION_MIPS64, + OPTION_MIPS32R2, ++ OPTION_MIPS32R3, ++ OPTION_MIPS32R5, + OPTION_MIPS64R2, ++ OPTION_MIPS64R3, ++ OPTION_MIPS64R5, + OPTION_MIPS16, + OPTION_NO_MIPS16, + OPTION_MIPS3D, @@ -557241,6 +561134,8 @@ index 0000000..34f1bf0 + OPTION_NO_DSPR2, + OPTION_EVA, + OPTION_NO_EVA, ++ OPTION_XPA, ++ OPTION_NO_XPA, + OPTION_MICROMIPS, + OPTION_NO_MICROMIPS, + OPTION_MCU, @@ -557323,7 +561218,11 @@ index 0000000..34f1bf0 + {"mips32", no_argument, NULL, OPTION_MIPS32}, + {"mips64", no_argument, NULL, OPTION_MIPS64}, + {"mips32r2", no_argument, NULL, OPTION_MIPS32R2}, ++ {"mips32r3", no_argument, NULL, OPTION_MIPS32R3}, ++ {"mips32r5", no_argument, NULL, OPTION_MIPS32R5}, + {"mips64r2", no_argument, NULL, OPTION_MIPS64R2}, ++ {"mips64r3", no_argument, NULL, OPTION_MIPS64R3}, ++ {"mips64r5", no_argument, NULL, OPTION_MIPS64R5}, + + /* Options which specify Application Specific Extensions (ASEs). */ + {"mips16", no_argument, NULL, OPTION_MIPS16}, @@ -557350,6 +561249,8 @@ index 0000000..34f1bf0 + {"mno-virt", no_argument, NULL, OPTION_NO_VIRT}, + {"mmsa", no_argument, NULL, OPTION_MSA}, + {"mno-msa", no_argument, NULL, OPTION_NO_MSA}, ++ {"mxpa", no_argument, NULL, OPTION_XPA}, ++ {"mno-xpa", no_argument, NULL, OPTION_NO_XPA}, + + /* Old-style architecture options. Don't add more of these. */ + {"m4650", no_argument, NULL, OPTION_M4650}, @@ -557502,11 +561403,15 @@ index 0000000..34f1bf0 + + { "msa", ASE_MSA, ASE_MSA64, + OPTION_MSA, OPTION_NO_MSA, -+ 2, 2, 2, 2 } ++ 2, 2, 2, 2 }, ++ ++ { "xpa", ASE_XPA, 0, ++ OPTION_XPA, OPTION_NO_XPA, ++ 2, 2, -1, -1 } +}; + +/* The set of ASEs that require -mfp64. */ -+#define FP64_ASES (ASE_MIPS3D | ASE_MDMX) ++#define FP64_ASES (ASE_MIPS3D | ASE_MDMX | ASE_MSA) + +/* Groups of ASE_* flags that represent different revisions of an ASE. */ +static const unsigned int mips_ase_groups[] = { @@ -557555,6 +561460,7 @@ index 0000000..34f1bf0 + {"cpadd", s_cpadd, 0}, + {"insn", s_insn, 0}, + {"nan", s_nan, 0}, ++ {"module", s_module, 0}, + + /* Relatively generic pseudo-ops that happen to be used on MIPS + chips. */ @@ -557622,6 +561528,7 @@ index 0000000..34f1bf0 +int +mips_address_bytes (void) +{ ++ file_mips_check_options (); + return HAVE_64BIT_ADDRESSES ? 8 : 4; +} + @@ -557756,6 +561663,12 @@ index 0000000..34f1bf0 + if (mips_opts.isa == ISA_MIPS32R2 || mips_opts.isa == ISA_MIPS64R2) + return 2; + ++ if (mips_opts.isa == ISA_MIPS32R3 || mips_opts.isa == ISA_MIPS64R3) ++ return 3; ++ ++ if (mips_opts.isa == ISA_MIPS32R5 || mips_opts.isa == ISA_MIPS64R5) ++ return 5; ++ + /* microMIPS implies revision 2 or above. */ + if (mips_opts.micromips) + return 2; @@ -557808,7 +561721,7 @@ index 0000000..34f1bf0 + ase->name, base, size, min_rev); + } + if ((ase->flags & FP64_ASES) -+ && mips_opts.fp32 ++ && mips_opts.fp != 64 + && (warned_fp32 & ase->flags) != ase->flags) + { + warned_fp32 |= ase->flags; @@ -557836,14 +561749,15 @@ index 0000000..34f1bf0 + that were affected. */ + +static unsigned int -+mips_set_ase (const struct mips_ase *ase, bfd_boolean enabled_p) ++mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts, ++ bfd_boolean enabled_p) +{ + unsigned int mask; + + mask = mips_ase_mask (ase->flags); -+ mips_opts.ase &= ~mask; ++ opts->ase &= ~mask; + if (enabled_p) -+ mips_opts.ase |= ase->flags; ++ opts->ase |= ase->flags; + return mask; +} + @@ -559239,7 +563153,7 @@ index 0000000..34f1bf0 + g_switch_value = 0; + } + -+ if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch)) ++ if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) + as_warn (_("could not set architecture and machine")); + + op_hash = hash_new (); @@ -559484,19 +563398,141 @@ index 0000000..34f1bf0 + subseg_set (seg, subseg); + } + -+ if (! ECOFF_DEBUGGING) -+ md_obj_begin (); -+ + if (mips_fix_vr4120) + init_vr4120_conflicts (); +} + -+void -+md_mips_end (void) ++/* Perform consistency checks on the current options. */ ++ ++static void ++mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks) +{ -+ mips_emit_delays (); -+ if (! ECOFF_DEBUGGING) -+ md_obj_end (); ++ /* Check the size of integer registers agrees with the ABI and ISA. */ ++ if (opts->gp == 64 && !ISA_HAS_64BIT_REGS (opts->isa)) ++ as_bad (_("`gp=64' used with a 32-bit processor")); ++ else if (abi_checks ++ && opts->gp == 32 && ABI_NEEDS_64BIT_REGS (mips_abi)) ++ as_bad (_("`gp=32' used with a 64-bit ABI")); ++ else if (abi_checks ++ && opts->gp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi)) ++ as_bad (_("`gp=64' used with a 32-bit ABI")); ++ ++ /* Check the size of the float registers agrees with the ABI and ISA. */ ++ switch (opts->fp) ++ { ++ case 64: ++ if (!ISA_HAS_64BIT_FPRS (opts->isa)) ++ as_bad (_("`fp=64' used with a 32-bit fpu")); ++ else if (abi_checks ++ && ABI_NEEDS_32BIT_REGS (mips_abi) ++ && !ISA_HAS_MXHC1 (opts->isa)) ++ as_warn (_("`fp=64' used with a 32-bit ABI")); ++ break; ++ case 32: ++ if (abi_checks ++ && ABI_NEEDS_64BIT_REGS (mips_abi)) ++ as_warn (_("`fp=32' used with a 64-bit ABI")); ++ break; ++ default: ++ as_bad (_("Unknown size of floating point registers")); ++ break; ++ } ++ ++ if (opts->micromips == 1 && opts->mips16 == 1) ++ as_bad (_("`mips16' cannot be used with `micromips'")); ++} ++ ++/* Perform consistency checks on the module level options exactly once. ++ This is a deferred check that happens: ++ at the first .set directive ++ or, at the first pseudo op that generates code (inc .dc.a) ++ or, at the first instruction ++ or, at the end. */ ++ ++static void ++file_mips_check_options (void) ++{ ++ const struct mips_cpu_info *arch_info = 0; ++ ++ if (file_mips_opts_checked) ++ return; ++ ++ /* The following code determines the register size. ++ Similar code was added to GCC 3.3 (see override_options() in ++ config/mips/mips.c). The GAS and GCC code should be kept in sync ++ as much as possible. */ ++ ++ if (file_mips_opts.gp < 0) ++ { ++ /* Infer the integer register size from the ABI and processor. ++ Restrict ourselves to 32-bit registers if that's all the ++ processor has, or if the ABI cannot handle 64-bit registers. */ ++ file_mips_opts.gp = (ABI_NEEDS_32BIT_REGS (mips_abi) ++ || !ISA_HAS_64BIT_REGS (file_mips_opts.isa)) ++ ? 32 : 64; ++ } ++ ++ if (file_mips_opts.fp < 0) ++ { ++ /* No user specified float register size. ++ ??? GAS treats single-float processors as though they had 64-bit ++ float registers (although it complains when double-precision ++ instructions are used). As things stand, saying they have 32-bit ++ registers would lead to spurious "register must be even" messages. ++ So here we assume float registers are never smaller than the ++ integer ones. */ ++ if (file_mips_opts.gp == 64) ++ /* 64-bit integer registers implies 64-bit float registers. */ ++ file_mips_opts.fp = 64; ++ else if ((file_mips_opts.ase & FP64_ASES) ++ && ISA_HAS_64BIT_FPRS (file_mips_opts.isa)) ++ /* Handle ASEs that require 64-bit float registers, if possible. */ ++ file_mips_opts.fp = 64; ++ else ++ /* 32-bit float registers. */ ++ file_mips_opts.fp = 32; ++ } ++ ++ arch_info = mips_cpu_info_from_arch (file_mips_opts.arch); ++ ++ /* End of GCC-shared inference code. */ ++ ++ /* This flag is set when we have a 64-bit capable CPU but use only ++ 32-bit wide registers. Note that EABI does not use it. */ ++ if (ISA_HAS_64BIT_REGS (file_mips_opts.isa) ++ && ((mips_abi == NO_ABI && file_mips_opts.gp == 32) ++ || mips_abi == O32_ABI)) ++ mips_32bitmode = 1; ++ ++ if (file_mips_opts.isa == ISA_MIPS1 && mips_trap) ++ as_bad (_("trap exception not supported at ISA 1")); ++ ++ /* If the selected architecture includes support for ASEs, enable ++ generation of code for them. */ ++ if (file_mips_opts.mips16 == -1) ++ file_mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_opts.arch)) ? 1 : 0; ++ if (file_mips_opts.micromips == -1) ++ file_mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_opts.arch)) ++ ? 1 : 0; ++ ++ /* Some ASEs require 64-bit FPRs, so -mfp32 should stop those ASEs from ++ being selected implicitly. */ ++ if (file_mips_opts.fp != 64) ++ file_ase_explicit |= ASE_MIPS3D | ASE_MDMX | ASE_MSA; ++ ++ /* If the user didn't explicitly select or deselect a particular ASE, ++ use the default setting for the CPU. */ ++ file_mips_opts.ase |= (arch_info->ase & ~file_ase_explicit); ++ ++ /* Set up the current options. These may change throughout assembly. */ ++ mips_opts = file_mips_opts; ++ ++ mips_check_isa_supports_ases (); ++ mips_check_options (&file_mips_opts, TRUE); ++ file_mips_opts_checked = TRUE; ++ ++ if (!bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_opts.arch)) ++ as_warn (_("could not set architecture and machine")); +} + +void @@ -559506,6 +563542,8 @@ index 0000000..34f1bf0 + bfd_reloc_code_real_type unused_reloc[3] + = {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED}; + ++ file_mips_check_options (); ++ + imm_expr.X_op = O_absent; + offset_expr.X_op = O_absent; + offset_reloc[0] = BFD_RELOC_UNUSED; @@ -560075,7 +564113,7 @@ index 0000000..34f1bf0 + pinfo = ip->insn_mo->pinfo; + /* Conservatively treat all operands to an FP_D instruction are doubles. + (This is overly pessimistic for things like cvt.d.s.) */ -+ if (HAVE_32BIT_FPRS && (pinfo & FP_D)) ++ if (FPR_SIZE != 64 && (pinfo & FP_D)) + mask |= mask << 1; + return mask; +} @@ -560094,7 +564132,7 @@ index 0000000..34f1bf0 + pinfo = ip->insn_mo->pinfo; + /* Conservatively treat all operands to an FP_D instruction are doubles. + (This is overly pessimistic for things like cvt.s.d.) */ -+ if (HAVE_32BIT_FPRS && (pinfo & FP_D)) ++ if (FPR_SIZE != 64 && (pinfo & FP_D)) + mask |= mask << 1; + return mask; +} @@ -560361,7 +564399,7 @@ index 0000000..34f1bf0 + + if (type == OP_REG_FP + && (regno & 1) != 0 -+ && HAVE_32BIT_FPRS ++ && FPR_SIZE != 64 + && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum)) + as_warn (_("float register should be even, was %d"), regno); + @@ -561223,7 +565261,7 @@ index 0000000..34f1bf0 + but the GPRs are only 32 bits wide. */ + /* ??? No longer true with the addition of MTHC1, but this + is legacy code... */ -+ && (using_gprs || !(HAVE_64BIT_FPRS && HAVE_32BIT_GPRS)) ++ && (using_gprs || !(FPR_SIZE == 64 && GPR_SIZE == 32)) + && ((data[0] == 0 && data[1] == 0) + || (data[2] == 0 && data[3] == 0)) + && ((data[4] == 0 && data[5] == 0) @@ -561233,7 +565271,7 @@ index 0000000..34f1bf0 + If using 32-bit registers, set IMM to the high order 32 bits and + OFFSET to the low order 32 bits. Otherwise, set IMM to the entire + 64 bit constant. */ -+ if (using_gprs ? HAVE_32BIT_GPRS : HAVE_32BIT_FPRS) ++ if (using_gprs ? GPR_SIZE == 32 : FPR_SIZE != 64) + { + imm->X_op = O_constant; + offset->X_op = O_constant; @@ -562729,7 +566767,7 @@ index 0000000..34f1bf0 + + /* These relocations can have an addend that won't fit in + 4 octets for 64bit assembly. */ -+ if (HAVE_64BIT_GPRS ++ if (GPR_SIZE == 64 + && ! howto->partial_inplace + && (reloc_type[0] == BFD_RELOC_16 + || reloc_type[0] == BFD_RELOC_32 @@ -563143,7 +567181,7 @@ index 0000000..34f1bf0 + if (!match_const_int (&arg, &imm_expr.X_add_number)) + return FALSE; + imm_expr.X_op = O_constant; -+ if (HAVE_32BIT_GPRS) ++ if (GPR_SIZE == 32) + normalize_constant_expr (&imm_expr); + continue; + @@ -563353,7 +567391,7 @@ index 0000000..34f1bf0 + if (!match_const_int (&arg, &imm_expr.X_add_number)) + return FALSE; + imm_expr.X_op = O_constant; -+ if (HAVE_32BIT_GPRS) ++ if (GPR_SIZE == 32) + normalize_constant_expr (&imm_expr); + continue; + @@ -564080,7 +568118,7 @@ index 0000000..34f1bf0 + AT, reg, BFD_RELOC_LO16); + else + { -+ load_register (AT, &imm_expr, HAVE_64BIT_GPRS); ++ load_register (AT, &imm_expr, GPR_SIZE == 64); + macro_build (NULL, unsignedp ? "sltu" : "slt", "d,v,t", AT, reg, AT); + } +} @@ -564206,7 +568244,7 @@ index 0000000..34f1bf0 + + /* The value is larger than 32 bits. */ + -+ if (!dbl || HAVE_32BIT_GPRS) ++ if (!dbl || GPR_SIZE == 32) + { + char value[32]; + @@ -564662,7 +568700,7 @@ index 0000000..34f1bf0 + && !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT)) + macro_build (NULL, "move", "mp,mj", dest, source); + else -+ macro_build (NULL, HAVE_32BIT_GPRS ? "addu" : "daddu", "d,v,t", ++ macro_build (NULL, GPR_SIZE == 32 ? "addu" : "daddu", "d,v,t", + dest, source, 0); +} + @@ -565145,7 +569183,7 @@ index 0000000..34f1bf0 + } + + used_at = 1; -+ load_register (AT, &imm_expr, HAVE_64BIT_GPRS); ++ load_register (AT, &imm_expr, GPR_SIZE == 64); + macro_build (NULL, s2, "d,v,t", op[0], op[1], AT); + break; + @@ -565189,7 +569227,7 @@ index 0000000..34f1bf0 + { + op[1] = AT; + used_at = 1; -+ load_register (op[1], &imm_expr, HAVE_64BIT_GPRS); ++ load_register (op[1], &imm_expr, GPR_SIZE == 64); + } + /* Fall through. */ + case M_BEQL: @@ -565289,7 +569327,7 @@ index 0000000..34f1bf0 + likely = 1; + case M_BGTU_I: + if (op[0] == 0 -+ || (HAVE_32BIT_GPRS ++ || (GPR_SIZE == 32 + && imm_expr.X_add_number == -1)) + goto do_false; + ++imm_expr.X_add_number; @@ -565406,7 +569444,7 @@ index 0000000..34f1bf0 + likely = 1; + case M_BLEU_I: + if (op[0] == 0 -+ || (HAVE_32BIT_GPRS ++ || (GPR_SIZE == 32 + && imm_expr.X_add_number == -1)) + goto do_true; + ++imm_expr.X_add_number; @@ -565671,7 +569709,7 @@ index 0000000..34f1bf0 + zero, we then add a base register to it. */ + + breg = op[2]; -+ if (dbl && HAVE_32BIT_GPRS) ++ if (dbl && GPR_SIZE == 32) + as_warn (_("dla used to load 32-bit register")); + + if (!dbl && HAVE_64BIT_OBJECTS) @@ -567334,7 +571372,7 @@ index 0000000..34f1bf0 + zero or in OFFSET_EXPR. */ + if (imm_expr.X_op == O_constant) + { -+ if (HAVE_64BIT_GPRS) ++ if (GPR_SIZE == 64) + load_register (op[0], &imm_expr, 1); + else + { @@ -567383,7 +571421,7 @@ index 0000000..34f1bf0 + } + + /* Now we load the register(s). */ -+ if (HAVE_64BIT_GPRS) ++ if (GPR_SIZE == 64) + { + used_at = 1; + macro_build (&offset_expr, "ld", "t,o(b)", op[0], @@ -567414,10 +571452,10 @@ index 0000000..34f1bf0 + if (imm_expr.X_op == O_constant) + { + used_at = 1; -+ load_register (AT, &imm_expr, HAVE_64BIT_FPRS); -+ if (HAVE_64BIT_FPRS) ++ load_register (AT, &imm_expr, FPR_SIZE == 64); ++ if (FPR_SIZE == 64) + { -+ gas_assert (HAVE_64BIT_GPRS); ++ gas_assert (GPR_SIZE == 64); + macro_build (NULL, "dmtc1", "t,S", AT, op[0]); + } + else @@ -567515,7 +571553,7 @@ index 0000000..34f1bf0 + + case M_LD_AB: + fmt = "t,o(b)"; -+ if (HAVE_64BIT_GPRS) ++ if (GPR_SIZE == 64) + { + s = "ld"; + goto ld; @@ -567525,7 +571563,7 @@ index 0000000..34f1bf0 + + case M_SD_AB: + fmt = "t,o(b)"; -+ if (HAVE_64BIT_GPRS) ++ if (GPR_SIZE == 64) + { + s = "sd"; + goto ld_st; @@ -568166,19 +572204,19 @@ index 0000000..34f1bf0 + && imm_expr.X_add_number < 0) + { + imm_expr.X_add_number = -imm_expr.X_add_number; -+ macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", ++ macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", + "t,r,j", op[0], op[1], BFD_RELOC_LO16); + } + else if (CPU_HAS_SEQ (mips_opts.arch)) + { + used_at = 1; -+ load_register (AT, &imm_expr, HAVE_64BIT_GPRS); ++ load_register (AT, &imm_expr, GPR_SIZE == 64); + macro_build (NULL, "seq", "d,v,t", op[0], op[1], AT); + break; + } + else + { -+ load_register (AT, &imm_expr, HAVE_64BIT_GPRS); ++ load_register (AT, &imm_expr, GPR_SIZE == 64); + macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); + used_at = 1; + } @@ -568203,7 +572241,7 @@ index 0000000..34f1bf0 + op[0], op[1], BFD_RELOC_LO16); + else + { -+ load_register (AT, &imm_expr, HAVE_64BIT_GPRS); ++ load_register (AT, &imm_expr, GPR_SIZE == 64); + macro_build (NULL, mask == M_SGE_I ? "slt" : "sltu", "d,v,t", + op[0], op[1], AT); + used_at = 1; @@ -568227,7 +572265,7 @@ index 0000000..34f1bf0 + s = "sltu"; + sgti: + used_at = 1; -+ load_register (AT, &imm_expr, HAVE_64BIT_GPRS); ++ load_register (AT, &imm_expr, GPR_SIZE == 64); + macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); + break; + @@ -568248,7 +572286,7 @@ index 0000000..34f1bf0 + s = "sltu"; + slei: + used_at = 1; -+ load_register (AT, &imm_expr, HAVE_64BIT_GPRS); ++ load_register (AT, &imm_expr, GPR_SIZE == 64); + macro_build (NULL, s, "d,v,t", op[0], AT, op[1]); + macro_build (&expr1, "xori", "t,r,i", op[0], op[0], BFD_RELOC_LO16); + break; @@ -568262,7 +572300,7 @@ index 0000000..34f1bf0 + break; + } + used_at = 1; -+ load_register (AT, &imm_expr, HAVE_64BIT_GPRS); ++ load_register (AT, &imm_expr, GPR_SIZE == 64); + macro_build (NULL, "slt", "d,v,t", op[0], op[1], AT); + break; + @@ -568275,7 +572313,7 @@ index 0000000..34f1bf0 + break; + } + used_at = 1; -+ load_register (AT, &imm_expr, HAVE_64BIT_GPRS); ++ load_register (AT, &imm_expr, GPR_SIZE == 64); + macro_build (NULL, "sltu", "d,v,t", op[0], op[1], AT); + break; + @@ -568301,7 +572339,7 @@ index 0000000..34f1bf0 + { + as_warn (_("instruction %s: result is always true"), + ip->insn_mo->name); -+ macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j", ++ macro_build (&expr1, GPR_SIZE == 32 ? "addiu" : "daddiu", "t,r,j", + op[0], 0, BFD_RELOC_LO16); + break; + } @@ -568323,19 +572361,19 @@ index 0000000..34f1bf0 + && imm_expr.X_add_number < 0) + { + imm_expr.X_add_number = -imm_expr.X_add_number; -+ macro_build (&imm_expr, HAVE_32BIT_GPRS ? "addiu" : "daddiu", ++ macro_build (&imm_expr, GPR_SIZE == 32 ? "addiu" : "daddiu", + "t,r,j", op[0], op[1], BFD_RELOC_LO16); + } + else if (CPU_HAS_SEQ (mips_opts.arch)) + { + used_at = 1; -+ load_register (AT, &imm_expr, HAVE_64BIT_GPRS); ++ load_register (AT, &imm_expr, GPR_SIZE == 64); + macro_build (NULL, "sne", "d,v,t", op[0], op[1], AT); + break; + } + else + { -+ load_register (AT, &imm_expr, HAVE_64BIT_GPRS); ++ load_register (AT, &imm_expr, GPR_SIZE == 64); + macro_build (NULL, "xor", "d,v,t", op[0], op[1], AT); + used_at = 1; + } @@ -568401,7 +572439,7 @@ index 0000000..34f1bf0 + s = "tne"; + trap: + used_at = 1; -+ load_register (AT, &imm_expr, HAVE_64BIT_GPRS); ++ load_register (AT, &imm_expr, GPR_SIZE == 64); + macro_build (NULL, s, "s,t", op[0], AT); + break; + @@ -569351,7 +573389,7 @@ index 0000000..34f1bf0 + for (i = 0; i < ARRAY_SIZE (mips_ases); i++) + if (c == mips_ases[i].option_on || c == mips_ases[i].option_off) + { -+ file_ase_explicit |= mips_set_ase (&mips_ases[i], ++ file_ase_explicit |= mips_set_ase (&mips_ases[i], &file_mips_opts, + c == mips_ases[i].option_on); + return 1; + } @@ -569401,39 +573439,55 @@ index 0000000..34f1bf0 + break; + + case OPTION_MIPS1: -+ file_mips_isa = ISA_MIPS1; ++ file_mips_opts.isa = ISA_MIPS1; + break; + + case OPTION_MIPS2: -+ file_mips_isa = ISA_MIPS2; ++ file_mips_opts.isa = ISA_MIPS2; + break; + + case OPTION_MIPS3: -+ file_mips_isa = ISA_MIPS3; ++ file_mips_opts.isa = ISA_MIPS3; + break; + + case OPTION_MIPS4: -+ file_mips_isa = ISA_MIPS4; ++ file_mips_opts.isa = ISA_MIPS4; + break; + + case OPTION_MIPS5: -+ file_mips_isa = ISA_MIPS5; ++ file_mips_opts.isa = ISA_MIPS5; + break; + + case OPTION_MIPS32: -+ file_mips_isa = ISA_MIPS32; ++ file_mips_opts.isa = ISA_MIPS32; + break; + + case OPTION_MIPS32R2: -+ file_mips_isa = ISA_MIPS32R2; ++ file_mips_opts.isa = ISA_MIPS32R2; ++ break; ++ ++ case OPTION_MIPS32R3: ++ file_mips_opts.isa = ISA_MIPS32R3; ++ break; ++ ++ case OPTION_MIPS32R5: ++ file_mips_opts.isa = ISA_MIPS32R5; + break; + + case OPTION_MIPS64R2: -+ file_mips_isa = ISA_MIPS64R2; ++ file_mips_opts.isa = ISA_MIPS64R2; ++ break; ++ ++ case OPTION_MIPS64R3: ++ file_mips_opts.isa = ISA_MIPS64R3; ++ break; ++ ++ case OPTION_MIPS64R5: ++ file_mips_opts.isa = ISA_MIPS64R5; + break; + + case OPTION_MIPS64: -+ file_mips_isa = ISA_MIPS64; ++ file_mips_opts.isa = ISA_MIPS64; + break; + + case OPTION_MTUNE: @@ -569477,32 +573531,32 @@ index 0000000..34f1bf0 + break; + + case OPTION_MICROMIPS: -+ if (mips_opts.mips16 == 1) ++ if (file_mips_opts.mips16 == 1) + { + as_bad (_("-mmicromips cannot be used with -mips16")); + return 0; + } -+ mips_opts.micromips = 1; ++ file_mips_opts.micromips = 1; + mips_no_prev_insn (); + break; + + case OPTION_NO_MICROMIPS: -+ mips_opts.micromips = 0; ++ file_mips_opts.micromips = 0; + mips_no_prev_insn (); + break; + + case OPTION_MIPS16: -+ if (mips_opts.micromips == 1) ++ if (file_mips_opts.micromips == 1) + { + as_bad (_("-mips16 cannot be used with -micromips")); + return 0; + } -+ mips_opts.mips16 = 1; ++ file_mips_opts.mips16 = 1; + mips_no_prev_insn (); + break; + + case OPTION_NO_MIPS16: -+ mips_opts.mips16 = 0; ++ file_mips_opts.mips16 = 0; + mips_no_prev_insn (); + break; + @@ -569571,11 +573625,11 @@ index 0000000..34f1bf0 + break; + + case OPTION_INSN32: -+ mips_opts.insn32 = TRUE; ++ file_mips_opts.insn32 = TRUE; + break; + + case OPTION_NO_INSN32: -+ mips_opts.insn32 = FALSE; ++ file_mips_opts.insn32 = FALSE; + break; + + case OPTION_MSHARED: @@ -569587,11 +573641,11 @@ index 0000000..34f1bf0 + break; + + case OPTION_MSYM32: -+ mips_opts.sym32 = TRUE; ++ file_mips_opts.sym32 = TRUE; + break; + + case OPTION_MNO_SYM32: -+ mips_opts.sym32 = FALSE; ++ file_mips_opts.sym32 = FALSE; + break; + + /* When generating ELF code, we permit -KPIC and -call_shared to @@ -569641,35 +573695,35 @@ index 0000000..34f1bf0 + break; + + case OPTION_GP32: -+ file_mips_gp32 = 1; ++ file_mips_opts.gp = 32; + break; + + case OPTION_GP64: -+ file_mips_gp32 = 0; ++ file_mips_opts.gp = 64; + break; + + case OPTION_FP32: -+ file_mips_fp32 = 1; ++ file_mips_opts.fp = 32; + break; + + case OPTION_FP64: -+ file_mips_fp32 = 0; ++ file_mips_opts.fp = 64; + break; + + case OPTION_SINGLE_FLOAT: -+ file_mips_single_float = 1; ++ file_mips_opts.single_float = 1; + break; + + case OPTION_DOUBLE_FLOAT: -+ file_mips_single_float = 0; ++ file_mips_opts.single_float = 0; + break; + + case OPTION_SOFT_FLOAT: -+ file_mips_soft_float = 1; ++ file_mips_opts.soft_float = 1; + break; + + case OPTION_HARD_FLOAT: -+ file_mips_soft_float = 0; ++ file_mips_opts.soft_float = 0; + break; + + case OPTION_MABI: @@ -569744,22 +573798,7 @@ index 0000000..34f1bf0 + return 1; +} + -+/* Set up globals to generate code for the ISA or processor -+ described by INFO. */ -+ -+static void -+mips_set_architecture (const struct mips_cpu_info *info) -+{ -+ if (info != 0) -+ { -+ file_mips_arch = info->cpu; -+ mips_opts.arch = info->cpu; -+ mips_opts.isa = info->isa; -+ } -+} -+ -+ -+/* Likewise for tuning. */ ++/* Set up globals to tune for the ISA or processor described by INFO. */ + +static void +mips_set_tune (const struct mips_cpu_info *info) @@ -569786,7 +573825,7 @@ index 0000000..34f1bf0 + if (mips_abi == NO_ABI) + mips_abi = MIPS_DEFAULT_ABI; + -+ /* The following code determines the architecture and register size. ++ /* The following code determines the architecture. + Similar code was added to GCC 3.3 (see override_options() in + config/mips/mips.c). The GAS and GCC code should be kept in sync + as much as possible. */ @@ -569794,9 +573833,9 @@ index 0000000..34f1bf0 + if (mips_arch_string != 0) + arch_info = mips_parse_cpu ("-march", mips_arch_string); + -+ if (file_mips_isa != ISA_UNKNOWN) ++ if (file_mips_opts.isa != ISA_UNKNOWN) + { -+ /* Handle -mipsN. At this point, file_mips_isa contains the ++ /* Handle -mipsN. At this point, file_mips_opts.isa contains the + ISA level specified by -mipsN, while arch_info->isa contains + the -march selection (if any). */ + if (arch_info != 0) @@ -569804,14 +573843,14 @@ index 0000000..34f1bf0 + /* -march takes precedence over -mipsN, since it is more descriptive. + There's no harm in specifying both as long as the ISA levels + are the same. */ -+ if (file_mips_isa != arch_info->isa) ++ if (file_mips_opts.isa != arch_info->isa) + as_bad (_("-%s conflicts with the other architecture options," + " which imply -%s"), -+ mips_cpu_info_from_isa (file_mips_isa)->name, ++ mips_cpu_info_from_isa (file_mips_opts.isa)->name, + mips_cpu_info_from_isa (arch_info->isa)->name); + } + else -+ arch_info = mips_cpu_info_from_isa (file_mips_isa); ++ arch_info = mips_cpu_info_from_isa (file_mips_opts.isa); + } + + if (arch_info == 0) @@ -569824,9 +573863,17 @@ index 0000000..34f1bf0 + as_bad (_("-march=%s is not compatible with the selected ABI"), + arch_info->name); + -+ mips_set_architecture (arch_info); ++ file_mips_opts.arch = arch_info->cpu; ++ file_mips_opts.isa = arch_info->isa; + -+ /* Optimize for file_mips_arch, unless -mtune selects a different processor. */ ++ /* Set up initial mips_opts state. */ ++ mips_opts = file_mips_opts; ++ ++ /* The register size inference code is now placed in ++ file_mips_check_options. */ ++ ++ /* Optimize for file_mips_opts.arch, unless -mtune selects a different ++ processor. */ + if (mips_tune_string != 0) + tune_info = mips_parse_cpu ("-mtune", mips_tune_string); + @@ -569835,101 +573882,6 @@ index 0000000..34f1bf0 + else + mips_set_tune (tune_info); + -+ if (file_mips_gp32 >= 0) -+ { -+ /* The user specified the size of the integer registers. Make sure -+ it agrees with the ABI and ISA. */ -+ if (file_mips_gp32 == 0 && !ISA_HAS_64BIT_REGS (mips_opts.isa)) -+ as_bad (_("-mgp64 used with a 32-bit processor")); -+ else if (file_mips_gp32 == 1 && ABI_NEEDS_64BIT_REGS (mips_abi)) -+ as_bad (_("-mgp32 used with a 64-bit ABI")); -+ else if (file_mips_gp32 == 0 && ABI_NEEDS_32BIT_REGS (mips_abi)) -+ as_bad (_("-mgp64 used with a 32-bit ABI")); -+ } -+ else -+ { -+ /* Infer the integer register size from the ABI and processor. -+ Restrict ourselves to 32-bit registers if that's all the -+ processor has, or if the ABI cannot handle 64-bit registers. */ -+ file_mips_gp32 = (ABI_NEEDS_32BIT_REGS (mips_abi) -+ || !ISA_HAS_64BIT_REGS (mips_opts.isa)); -+ } -+ -+ switch (file_mips_fp32) -+ { -+ default: -+ case -1: -+ /* No user specified float register size. -+ ??? GAS treats single-float processors as though they had 64-bit -+ float registers (although it complains when double-precision -+ instructions are used). As things stand, saying they have 32-bit -+ registers would lead to spurious "register must be even" messages. -+ So here we assume float registers are never smaller than the -+ integer ones. */ -+ if (file_mips_gp32 == 0) -+ /* 64-bit integer registers implies 64-bit float registers. */ -+ file_mips_fp32 = 0; -+ else if ((mips_opts.ase & FP64_ASES) -+ && ISA_HAS_64BIT_FPRS (mips_opts.isa)) -+ /* -mips3d and -mdmx imply 64-bit float registers, if possible. */ -+ file_mips_fp32 = 0; -+ else -+ /* 32-bit float registers. */ -+ file_mips_fp32 = 1; -+ break; -+ -+ /* The user specified the size of the float registers. Check if it -+ agrees with the ABI and ISA. */ -+ case 0: -+ if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) -+ as_bad (_("-mfp64 used with a 32-bit fpu")); -+ else if (ABI_NEEDS_32BIT_REGS (mips_abi) -+ && !ISA_HAS_MXHC1 (mips_opts.isa)) -+ as_warn (_("-mfp64 used with a 32-bit ABI")); -+ break; -+ case 1: -+ if (ABI_NEEDS_64BIT_REGS (mips_abi)) -+ as_warn (_("-mfp32 used with a 64-bit ABI")); -+ break; -+ } -+ -+ /* End of GCC-shared inference code. */ -+ -+ /* This flag is set when we have a 64-bit capable CPU but use only -+ 32-bit wide registers. Note that EABI does not use it. */ -+ if (ISA_HAS_64BIT_REGS (mips_opts.isa) -+ && ((mips_abi == NO_ABI && file_mips_gp32 == 1) -+ || mips_abi == O32_ABI)) -+ mips_32bitmode = 1; -+ -+ if (mips_opts.isa == ISA_MIPS1 && mips_trap) -+ as_bad (_("trap exception not supported at ISA 1")); -+ -+ /* If the selected architecture includes support for ASEs, enable -+ generation of code for them. */ -+ if (mips_opts.mips16 == -1) -+ mips_opts.mips16 = (CPU_HAS_MIPS16 (file_mips_arch)) ? 1 : 0; -+ if (mips_opts.micromips == -1) -+ mips_opts.micromips = (CPU_HAS_MICROMIPS (file_mips_arch)) ? 1 : 0; -+ -+ /* MIPS3D and MDMX require 64-bit FPRs, so -mfp32 should stop those -+ ASEs from being selected implicitly. */ -+ if (file_mips_fp32 == 1) -+ file_ase_explicit |= ASE_MIPS3D | ASE_MDMX; -+ -+ /* If the user didn't explicitly select or deselect a particular ASE, -+ use the default setting for the CPU. */ -+ mips_opts.ase |= (arch_info->ase & ~file_ase_explicit); -+ -+ file_mips_isa = mips_opts.isa; -+ file_ase = mips_opts.ase; -+ mips_opts.gp32 = file_mips_gp32; -+ mips_opts.fp32 = file_mips_fp32; -+ mips_opts.soft_float = file_mips_soft_float; -+ mips_opts.single_float = file_mips_single_float; -+ -+ mips_check_isa_supports_ases (); -+ + if (mips_flag_mdebug < 0) + mips_flag_mdebug = 0; +} @@ -569960,15 +573912,7 @@ index 0000000..34f1bf0 + /* Return the address of the delay slot. */ + return addr + 4; + -+ case BFD_RELOC_32_PCREL: -+ return addr; -+ + default: -+ /* We have no relocation type for PC relative MIPS16 instructions. */ -+ if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg) -+ as_bad_where (fixP->fx_file, fixP->fx_line, -+ _("PC relative MIPS16 instruction references" -+ " a different section")); + return addr; + } +} @@ -570165,13 +574109,38 @@ index 0000000..34f1bf0 + unsigned long insn; + reloc_howto_type *howto; + -+ /* We ignore generic BFD relocations we don't know about. */ -+ howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); -+ if (! howto) -+ return; ++ if (fixP->fx_pcrel) ++ switch (fixP->fx_r_type) ++ { ++ case BFD_RELOC_16_PCREL_S2: ++ case BFD_RELOC_MICROMIPS_7_PCREL_S1: ++ case BFD_RELOC_MICROMIPS_10_PCREL_S1: ++ case BFD_RELOC_MICROMIPS_16_PCREL_S1: ++ case BFD_RELOC_32_PCREL: ++ break; ++ ++ case BFD_RELOC_32: ++ fixP->fx_r_type = BFD_RELOC_32_PCREL; ++ break; ++ ++ default: ++ as_bad_where (fixP->fx_file, fixP->fx_line, ++ _("PC-relative reference to a different section")); ++ break; ++ } ++ ++ /* Handle BFD_RELOC_8, since it's easy. Punt on other bfd relocations ++ that have no MIPS ELF equivalent. */ ++ if (fixP->fx_r_type != BFD_RELOC_8) ++ { ++ howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type); ++ if (!howto) ++ return; ++ } + + gas_assert (fixP->fx_size == 2 + || fixP->fx_size == 4 ++ || fixP->fx_r_type == BFD_RELOC_8 + || fixP->fx_r_type == BFD_RELOC_16 + || fixP->fx_r_type == BFD_RELOC_64 + || fixP->fx_r_type == BFD_RELOC_CTOR @@ -570183,12 +574152,6 @@ index 0000000..34f1bf0 + + buf = fixP->fx_frag->fr_literal + fixP->fx_where; + -+ gas_assert (!fixP->fx_pcrel || fixP->fx_r_type == BFD_RELOC_16_PCREL_S2 -+ || fixP->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1 -+ || fixP->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1 -+ || fixP->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1 -+ || fixP->fx_r_type == BFD_RELOC_32_PCREL); -+ + /* Don't treat parts of a composite relocation as done. There are two + reasons for this: + @@ -570338,6 +574301,7 @@ index 0000000..34f1bf0 + case BFD_RELOC_32: + case BFD_RELOC_32_PCREL: + case BFD_RELOC_16: ++ case BFD_RELOC_8: + /* If we are deleting this reloc entry, we must fill in the + value now. This can happen if we have a .word which is not + resolved when it appears but is later defined. */ @@ -570805,30 +574769,11 @@ index 0000000..34f1bf0 + +static struct mips_option_stack *mips_opts_stack; + -+/* Handle the .set pseudo-op. */ -+ -+static void -+s_mipsset (int x ATTRIBUTE_UNUSED) ++static bfd_boolean ++parse_code_option (char * name) +{ -+ char *name = input_line_pointer, ch; + const struct mips_ase *ase; -+ -+ while (!is_end_of_line[(unsigned char) *input_line_pointer]) -+ ++input_line_pointer; -+ ch = *input_line_pointer; -+ *input_line_pointer = '\0'; -+ -+ if (strcmp (name, "reorder") == 0) -+ { -+ if (mips_opts.noreorder) -+ end_noreorder (); -+ } -+ else if (strcmp (name, "noreorder") == 0) -+ { -+ if (!mips_opts.noreorder) -+ start_noreorder (); -+ } -+ else if (strncmp (name, "at=", 3) == 0) ++ if (strncmp (name, "at=", 3) == 0) + { + char *s = name + 3; + @@ -570836,61 +574781,25 @@ index 0000000..34f1bf0 + as_bad (_("unrecognized register name `%s'"), s); + } + else if (strcmp (name, "at") == 0) -+ { -+ mips_opts.at = ATREG; -+ } ++ mips_opts.at = ATREG; + else if (strcmp (name, "noat") == 0) -+ { -+ mips_opts.at = ZERO; -+ } -+ else if (strcmp (name, "macro") == 0) -+ { -+ mips_opts.warn_about_macros = 0; -+ } -+ else if (strcmp (name, "nomacro") == 0) -+ { -+ if (mips_opts.noreorder == 0) -+ as_bad (_("`noreorder' must be set before `nomacro'")); -+ mips_opts.warn_about_macros = 1; -+ } ++ mips_opts.at = ZERO; + else if (strcmp (name, "move") == 0 || strcmp (name, "novolatile") == 0) -+ { -+ mips_opts.nomove = 0; -+ } ++ mips_opts.nomove = 0; + else if (strcmp (name, "nomove") == 0 || strcmp (name, "volatile") == 0) -+ { -+ mips_opts.nomove = 1; -+ } ++ mips_opts.nomove = 1; + else if (strcmp (name, "bopt") == 0) -+ { -+ mips_opts.nobopt = 0; -+ } ++ mips_opts.nobopt = 0; + else if (strcmp (name, "nobopt") == 0) -+ { -+ mips_opts.nobopt = 1; -+ } -+ else if (strcmp (name, "gp=default") == 0) -+ mips_opts.gp32 = file_mips_gp32; ++ mips_opts.nobopt = 1; + else if (strcmp (name, "gp=32") == 0) -+ mips_opts.gp32 = 1; ++ mips_opts.gp = 32; + else if (strcmp (name, "gp=64") == 0) -+ { -+ if (!ISA_HAS_64BIT_REGS (mips_opts.isa)) -+ as_warn (_("%s isa does not support 64-bit registers"), -+ mips_cpu_info_from_isa (mips_opts.isa)->name); -+ mips_opts.gp32 = 0; -+ } -+ else if (strcmp (name, "fp=default") == 0) -+ mips_opts.fp32 = file_mips_fp32; ++ mips_opts.gp = 64; + else if (strcmp (name, "fp=32") == 0) -+ mips_opts.fp32 = 1; ++ mips_opts.fp = 32; + else if (strcmp (name, "fp=64") == 0) -+ { -+ if (!ISA_HAS_64BIT_FPRS (mips_opts.isa)) -+ as_warn (_("%s isa does not support 64-bit floating point registers"), -+ mips_cpu_info_from_isa (mips_opts.isa)->name); -+ mips_opts.fp32 = 0; -+ } ++ mips_opts.fp = 64; + else if (strcmp (name, "softfloat") == 0) + mips_opts.soft_float = 1; + else if (strcmp (name, "hardfloat") == 0) @@ -570901,45 +574810,29 @@ index 0000000..34f1bf0 + mips_opts.single_float = 0; + else if (strcmp (name, "mips16") == 0 + || strcmp (name, "MIPS-16") == 0) -+ { -+ if (mips_opts.micromips == 1) -+ as_fatal (_("`mips16' cannot be used with `micromips'")); -+ mips_opts.mips16 = 1; -+ } ++ mips_opts.mips16 = 1; + else if (strcmp (name, "nomips16") == 0 + || strcmp (name, "noMIPS-16") == 0) + mips_opts.mips16 = 0; + else if (strcmp (name, "micromips") == 0) -+ { -+ if (mips_opts.mips16 == 1) -+ as_fatal (_("`micromips' cannot be used with `mips16'")); -+ mips_opts.micromips = 1; -+ } ++ mips_opts.micromips = 1; + else if (strcmp (name, "nomicromips") == 0) + mips_opts.micromips = 0; + else if (name[0] == 'n' + && name[1] == 'o' + && (ase = mips_lookup_ase (name + 2))) -+ mips_set_ase (ase, FALSE); ++ mips_set_ase (ase, &mips_opts, FALSE); + else if ((ase = mips_lookup_ase (name))) -+ mips_set_ase (ase, TRUE); ++ mips_set_ase (ase, &mips_opts, TRUE); + else if (strncmp (name, "mips", 4) == 0 || strncmp (name, "arch=", 5) == 0) + { -+ int reset = 0; -+ + /* Permit the user to change the ISA and architecture on the fly. + Needless to say, misuse can cause serious problems. */ -+ if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) -+ { -+ reset = 1; -+ mips_opts.isa = file_mips_isa; -+ mips_opts.arch = file_mips_arch; -+ } -+ else if (strncmp (name, "arch=", 5) == 0) ++ if (strncmp (name, "arch=", 5) == 0) + { + const struct mips_cpu_info *p; + -+ p = mips_parse_cpu("internal use", name + 5); ++ p = mips_parse_cpu ("internal use", name + 5); + if (!p) + as_bad (_("unknown architecture %s"), name + 5); + else @@ -570952,7 +574845,7 @@ index 0000000..34f1bf0 + { + const struct mips_cpu_info *p; + -+ p = mips_parse_cpu("internal use", name); ++ p = mips_parse_cpu ("internal use", name); + if (!p) + as_bad (_("unknown ISA level %s"), name + 4); + else @@ -570963,42 +574856,6 @@ index 0000000..34f1bf0 + } + else + as_bad (_("unknown ISA or architecture %s"), name); -+ -+ switch (mips_opts.isa) -+ { -+ case 0: -+ break; -+ case ISA_MIPS1: -+ case ISA_MIPS2: -+ case ISA_MIPS32: -+ case ISA_MIPS32R2: -+ mips_opts.gp32 = 1; -+ mips_opts.fp32 = 1; -+ break; -+ case ISA_MIPS3: -+ case ISA_MIPS4: -+ case ISA_MIPS5: -+ case ISA_MIPS64: -+ case ISA_MIPS64R2: -+ mips_opts.gp32 = 0; -+ if (mips_opts.arch == CPU_R5900) -+ { -+ mips_opts.fp32 = 1; -+ } -+ else -+ { -+ mips_opts.fp32 = 0; -+ } -+ break; -+ default: -+ as_bad (_("unknown ISA level %s"), name + 4); -+ break; -+ } -+ if (reset) -+ { -+ mips_opts.gp32 = file_mips_gp32; -+ mips_opts.fp32 = file_mips_fp32; -+ } + } + else if (strcmp (name, "autoextend") == 0) + mips_opts.noautoextend = 0; @@ -571008,6 +574865,68 @@ index 0000000..34f1bf0 + mips_opts.insn32 = TRUE; + else if (strcmp (name, "noinsn32") == 0) + mips_opts.insn32 = FALSE; ++ else if (strcmp (name, "sym32") == 0) ++ mips_opts.sym32 = TRUE; ++ else if (strcmp (name, "nosym32") == 0) ++ mips_opts.sym32 = FALSE; ++ else ++ return FALSE; ++ return TRUE; ++} ++ ++/* Handle the .set pseudo-op. */ ++ ++static void ++s_mipsset (int x ATTRIBUTE_UNUSED) ++{ ++ char *name = input_line_pointer, ch; ++ int prev_isa = mips_opts.isa; ++ ++ file_mips_check_options (); ++ ++ while (!is_end_of_line[(unsigned char) *input_line_pointer]) ++ ++input_line_pointer; ++ ch = *input_line_pointer; ++ *input_line_pointer = '\0'; ++ ++ if (strchr (name, ',')) ++ { ++ /* Generic ".set" directive; use the generic handler. */ ++ *input_line_pointer = ch; ++ input_line_pointer = name; ++ s_set (0); ++ return; ++ } ++ ++ if (strcmp (name, "reorder") == 0) ++ { ++ if (mips_opts.noreorder) ++ end_noreorder (); ++ } ++ else if (strcmp (name, "noreorder") == 0) ++ { ++ if (!mips_opts.noreorder) ++ start_noreorder (); ++ } ++ else if (strcmp (name, "macro") == 0) ++ mips_opts.warn_about_macros = 0; ++ else if (strcmp (name, "nomacro") == 0) ++ { ++ if (mips_opts.noreorder == 0) ++ as_bad (_("`noreorder' must be set before `nomacro'")); ++ mips_opts.warn_about_macros = 1; ++ } ++ else if (strcmp (name, "gp=default") == 0) ++ mips_opts.gp = file_mips_opts.gp; ++ else if (strcmp (name, "fp=default") == 0) ++ mips_opts.fp = file_mips_opts.fp; ++ else if (strcmp (name, "mips0") == 0 || strcmp (name, "arch=default") == 0) ++ { ++ mips_opts.isa = file_mips_opts.isa; ++ mips_opts.arch = file_mips_opts.arch; ++ mips_opts.gp = file_mips_opts.gp; ++ mips_opts.fp = file_mips_opts.fp; ++ } + else if (strcmp (name, "push") == 0) + { + struct mips_option_stack *s; @@ -571038,23 +574957,75 @@ index 0000000..34f1bf0 + free (s); + } + } -+ else if (strcmp (name, "sym32") == 0) -+ mips_opts.sym32 = TRUE; -+ else if (strcmp (name, "nosym32") == 0) -+ mips_opts.sym32 = FALSE; -+ else if (strchr (name, ',')) ++ else if (!parse_code_option (name)) ++ as_warn (_("tried to set unrecognized symbol: %s\n"), name); ++ ++ /* The use of .set [arch|cpu]= historically 'fixes' the width of gp and fp ++ registers based on what is supported by the arch/cpu. */ ++ if (mips_opts.isa != prev_isa) + { -+ /* Generic ".set" directive; use the generic handler. */ -+ *input_line_pointer = ch; -+ input_line_pointer = name; -+ s_set (0); -+ return; ++ switch (mips_opts.isa) ++ { ++ case 0: ++ break; ++ case ISA_MIPS1: ++ case ISA_MIPS2: ++ case ISA_MIPS32: ++ case ISA_MIPS32R2: ++ case ISA_MIPS32R3: ++ case ISA_MIPS32R5: ++ mips_opts.gp = 32; ++ mips_opts.fp = 32; ++ break; ++ case ISA_MIPS3: ++ case ISA_MIPS4: ++ case ISA_MIPS5: ++ case ISA_MIPS64: ++ case ISA_MIPS64R2: ++ case ISA_MIPS64R3: ++ case ISA_MIPS64R5: ++ mips_opts.gp = 64; ++ if (mips_opts.arch == CPU_R5900) ++ mips_opts.fp = 32; ++ else ++ mips_opts.fp = 64; ++ break; ++ default: ++ as_bad (_("unknown ISA level %s"), name + 4); ++ break; ++ } ++ } ++ ++ mips_check_options (&mips_opts, FALSE); ++ ++ mips_check_isa_supports_ases (); ++ *input_line_pointer = ch; ++ demand_empty_rest_of_line (); ++} ++ ++/* Handle the .module pseudo-op. */ ++ ++static void ++s_module (int ignore ATTRIBUTE_UNUSED) ++{ ++ char *name = input_line_pointer, ch; ++ ++ while (!is_end_of_line[(unsigned char) *input_line_pointer]) ++ ++input_line_pointer; ++ ch = *input_line_pointer; ++ *input_line_pointer = '\0'; ++ ++ if (!file_mips_opts_checked) ++ { ++ if (!parse_code_option (name)) ++ as_bad (_(".module used with unrecognized symbol: %s\n"), name); ++ ++ /* Update module level settings from mips_opts. */ ++ file_mips_opts = mips_opts; + } + else -+ { -+ as_warn (_("tried to set unrecognized symbol: %s\n"), name); -+ } -+ mips_check_isa_supports_ases (); ++ as_bad (_(".module is not permitted after generating code")); ++ + *input_line_pointer = ch; + demand_empty_rest_of_line (); +} @@ -571101,6 +575072,8 @@ index 0000000..34f1bf0 + int reg; + int in_shared; + ++ file_mips_check_options (); ++ + /* If we are not generating SVR4 PIC code, or if this is NewABI code, + .cpload is ignored. */ + if (mips_pic != SVR4_PIC || HAVE_NEWABI) @@ -571178,6 +575151,8 @@ index 0000000..34f1bf0 + expressionS ex_sym; + int reg1; + ++ file_mips_check_options (); ++ + /* If we are not generating SVR4 PIC code, .cpsetup is ignored. + We also need NewABI support. */ + if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) @@ -571281,6 +575256,8 @@ index 0000000..34f1bf0 +static void +s_cplocal (int ignore ATTRIBUTE_UNUSED) +{ ++ file_mips_check_options (); ++ + /* If we are not generating SVR4 PIC code, or if this is not NewABI code, + .cplocal is ignored. */ + if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) @@ -571309,6 +575286,8 @@ index 0000000..34f1bf0 +{ + expressionS ex; + ++ file_mips_check_options (); ++ + /* If we are not generating SVR4 PIC code, or if this is NewABI code, + .cprestore is ignored. */ + if (mips_pic != SVR4_PIC || HAVE_NEWABI) @@ -571356,6 +575335,8 @@ index 0000000..34f1bf0 +{ + expressionS ex; + ++ file_mips_check_options (); ++ + /* If we are not generating SVR4 PIC code, .cpreturn is ignored. + We also need NewABI support. */ + if (mips_pic != SVR4_PIC || ! HAVE_NEWABI) @@ -571590,6 +575571,8 @@ index 0000000..34f1bf0 +{ + int reg; + ++ file_mips_check_options (); ++ + /* This is ignored when not generating SVR4 PIC code. */ + if (mips_pic != SVR4_PIC) + { @@ -573211,7 +577194,7 @@ index 0000000..34f1bf0 + elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_M16; + if (file_ase_micromips) + elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MICROMIPS; -+ if (file_ase & ASE_MDMX) ++ if (file_mips_opts.ase & ASE_MDMX) + elf_elfheader (stdoutput)->e_flags |= EF_MIPS_ARCH_ASE_MDMX; + + /* Set the MIPS ELF ABI flags. */ @@ -573221,7 +577204,7 @@ index 0000000..34f1bf0 + elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_O64; + else if (mips_abi == EABI_ABI) + { -+ if (!file_mips_gp32) ++ if (file_mips_opts.gp == 64) + elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI64; + else + elf_elfheader (stdoutput)->e_flags |= E_MIPS_ABI_EABI32; @@ -573238,7 +577221,7 @@ index 0000000..34f1bf0 + elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008; + + /* 32 bit code with 64 bit FP registers. */ -+ if (!file_mips_fp32 && ABI_NEEDS_32BIT_REGS (mips_abi)) ++ if (file_mips_opts.fp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi)) + elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64; +} + @@ -573342,19 +577325,6 @@ index 0000000..34f1bf0 + fragp->fr_var = size; +} + -+static void -+md_obj_begin (void) -+{ -+} -+ -+static void -+md_obj_end (void) -+{ -+ /* Check for premature end, nesting errors, etc. */ -+ if (cur_proc_ptr) -+ as_warn (_("missing .end at end of assembly")); -+} -+ +static long +get_number (void) +{ @@ -573689,8 +577659,12 @@ index 0000000..34f1bf0 + { "mips5", MIPS_CPU_IS_ISA, 0, ISA_MIPS5, CPU_MIPS5 }, + { "mips32", MIPS_CPU_IS_ISA, 0, ISA_MIPS32, CPU_MIPS32 }, + { "mips32r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R2, CPU_MIPS32R2 }, ++ { "mips32r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R3, CPU_MIPS32R3 }, ++ { "mips32r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS32R5, CPU_MIPS32R5 }, + { "mips64", MIPS_CPU_IS_ISA, 0, ISA_MIPS64, CPU_MIPS64 }, + { "mips64r2", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R2, CPU_MIPS64R2 }, ++ { "mips64r3", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R3, CPU_MIPS64R3 }, ++ { "mips64r5", MIPS_CPU_IS_ISA, 0, ISA_MIPS64R5, CPU_MIPS64R5 }, + + /* MIPS I */ + { "r3000", 0, 0, ISA_MIPS1, CPU_R3000 }, @@ -573793,6 +577767,8 @@ index 0000000..34f1bf0 + { "1004kf2_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, + { "1004kf", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, + { "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, ++ /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */ ++ { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 }, + + /* MIPS 64 */ + { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 }, @@ -573805,7 +577781,7 @@ index 0000000..34f1bf0 + /* Broadcom SB-1A CPU core */ + { "sb1a", 0, ASE_MIPS3D | ASE_MDMX, ISA_MIPS64, CPU_SB1 }, + -+ { "loongson3a", 0, 0, ISA_MIPS64, CPU_LOONGSON_3A }, ++ { "loongson3a", 0, 0, ISA_MIPS64R2, CPU_LOONGSON_3A }, + + /* MIPS 64 Release 2 */ + @@ -573906,8 +577882,9 @@ index 0000000..34f1bf0 + if (ABI_NEEDS_64BIT_REGS (mips_abi)) + return mips_cpu_info_from_isa (ISA_MIPS3); + -+ if (file_mips_gp32 >= 0) -+ return mips_cpu_info_from_isa (file_mips_gp32 ? ISA_MIPS1 : ISA_MIPS3); ++ if (file_mips_opts.gp >= 0) ++ return mips_cpu_info_from_isa (file_mips_opts.gp == 32 ++ ? ISA_MIPS1 : ISA_MIPS3); + + return mips_cpu_info_from_isa (MIPS_DEFAULT_64BIT + ? ISA_MIPS3 @@ -574001,8 +577978,12 @@ index 0000000..34f1bf0 +-mips5 generate MIPS ISA V instructions\n\ +-mips32 generate MIPS32 ISA instructions\n\ +-mips32r2 generate MIPS32 release 2 ISA instructions\n\ ++-mips32r3 generate MIPS32 release 3 ISA instructions\n\ ++-mips32r5 generate MIPS32 release 5 ISA instructions\n\ +-mips64 generate MIPS64 ISA instructions\n\ +-mips64r2 generate MIPS64 release 2 ISA instructions\n\ ++-mips64r3 generate MIPS64 release 3 ISA instructions\n\ ++-mips64r5 generate MIPS64 release 5 ISA instructions\n\ +-march=CPU/-mtune=CPU generate code/schedule for CPU, where CPU is one of:\n")); + + first = 1; @@ -574050,6 +578031,9 @@ index 0000000..34f1bf0 +-mmsa generate MSA instructions\n\ +-mno-msa do not generate MSA instructions\n")); + fprintf (stream, _("\ ++-mxpa generate eXtended Physical Address (XPA) instructions\n\ ++-mno-xpa do not generate eXtended Physical Address (XPA) instructions\n")); ++ fprintf (stream, _("\ +-mvirt generate Virtualization instructions\n\ +-mno-virt do not generate Virtualization instructions\n")); + fprintf (stream, _("\ @@ -574150,15 +578134,56 @@ index 0000000..34f1bf0 + + return regnum; +} ++ ++/* Implement CONVERT_SYMBOLIC_ATTRIBUTE. ++ Given a symbolic attribute NAME, return the proper integer value. ++ Returns -1 if the attribute is not known. */ ++ ++int ++mips_convert_symbolic_attribute (const char *name) ++{ ++ static const struct ++ { ++ const char * name; ++ const int tag; ++ } ++ attribute_table[] = ++ { ++#define T(tag) {#tag, tag} ++ T (Tag_GNU_MIPS_ABI_FP), ++ T (Tag_GNU_MIPS_ABI_MSA), ++#undef T ++ }; ++ unsigned int i; ++ ++ if (name == NULL) ++ return -1; ++ ++ for (i = 0; i < ARRAY_SIZE (attribute_table); i++) ++ if (streq (name, attribute_table[i].name)) ++ return attribute_table[i].tag; ++ ++ return -1; ++} ++ ++void ++md_mips_end (void) ++{ ++ mips_emit_delays (); ++ if (cur_proc_ptr) ++ as_warn (_("missing .end at end of assembly")); ++ ++ /* Just in case no code was emitted, do the consistency check. */ ++ file_mips_check_options (); ++} diff --git a/gas/config/tc-mips.h b/gas/config/tc-mips.h new file mode 100644 -index 0000000..c7eaa04 +index 0000000..0b8e607 --- /dev/null +++ b/gas/config/tc-mips.h -@@ -0,0 +1,193 @@ +@@ -0,0 +1,200 @@ +/* tc-mips.h -- header file for tc-mips.c. -+ Copyright 1993, 1994, 1995, 1996, 1997, 2000, 2001, 2002, 2003, 2004, -+ 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. ++ Copyright (C) 1993-2014 Free Software Foundation, Inc. + Contributed by the OSF and Ralph Campbell. + Written by Keith Knowles and Ralph Campbell, working independently. + Modified for ECOFF support by Ian Lance Taylor of Cygnus Support. @@ -574348,16 +578373,23 @@ index 0000000..c7eaa04 +#define DWARF2_DEFAULT_RETURN_COLUMN 31 +#define DWARF2_CIE_DATA_ALIGNMENT (-4) + ++#define DIFF_EXPR_OK ++/* We define DIFF_EXPR_OK because of R_MIPS_PC32, but we have no ++ 64-bit form for n64 CFIs. */ ++#define CFI_DIFF_EXPR_OK 0 ++ ++#define CONVERT_SYMBOLIC_ATTRIBUTE(name) mips_convert_symbolic_attribute (name) ++extern int mips_convert_symbolic_attribute (const char *); ++ +#endif /* TC_MIPS */ diff --git a/gas/config/tc-mmix.c b/gas/config/tc-mmix.c new file mode 100644 -index 0000000..7052b11 +index 0000000..ab0fd00 --- /dev/null +++ b/gas/config/tc-mmix.c -@@ -0,0 +1,4322 @@ +@@ -0,0 +1,4321 @@ +/* tc-mmix.c -- Assembler for Don Knuth's MMIX. -+ Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, -+ 2012 Free Software Foundation. ++ Copyright (C) 2001-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -578679,13 +582711,12 @@ index 0000000..7052b11 +} diff --git a/gas/config/tc-mmix.h b/gas/config/tc-mmix.h new file mode 100644 -index 0000000..dba24a2 +index 0000000..78d8adf --- /dev/null +++ b/gas/config/tc-mmix.h -@@ -0,0 +1,241 @@ +@@ -0,0 +1,240 @@ +/* tc-mmix.h -- Header file for tc-mmix.c. -+ Copyright (C) 2001, 2002, 2003, 2005, 2007, 2008 -+ Free Software Foundation, Inc. ++ Copyright (C) 2001-2014 Free Software Foundation, Inc. + Written by Hans-Peter Nilsson (hp@bitrange.com). + + This file is part of GAS, the GNU Assembler. @@ -578926,12 +582957,12 @@ index 0000000..dba24a2 +#define TC_GLOBAL_REGISTER_SYMBOL_OK diff --git a/gas/config/tc-mn10200.c b/gas/config/tc-mn10200.c new file mode 100644 -index 0000000..e9c70f2 +index 0000000..f76fb08 --- /dev/null +++ b/gas/config/tc-mn10200.c @@ -0,0 +1,1340 @@ +/* tc-mn10200.c -- Assembler code for the Matsushita 10200 -+ Copyright 1996-2013 Free Software Foundation, Inc. ++ Copyright (C) 1996-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -580272,12 +584303,12 @@ index 0000000..e9c70f2 + diff --git a/gas/config/tc-mn10200.h b/gas/config/tc-mn10200.h new file mode 100644 -index 0000000..1fed461 +index 0000000..6eb0418 --- /dev/null +++ b/gas/config/tc-mn10200.h @@ -0,0 +1,46 @@ +/* tc-mn10200.h -- Header file for tc-mn10200.c. -+ Copyright 1996, 1997, 2000, 2001, 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 1996-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -580324,13 +584355,12 @@ index 0000000..1fed461 + diff --git a/gas/config/tc-mn10300.c b/gas/config/tc-mn10300.c new file mode 100644 -index 0000000..4029c64 +index 0000000..3d159b1 --- /dev/null +++ b/gas/config/tc-mn10300.c @@ -0,0 +1,2639 @@ +/* tc-mn10300.c -- Assembler code for the Matsushita 10300 -+ Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, -+ 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. ++ Copyright (C) 1996-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -581344,7 +585374,8 @@ index 0000000..4029c64 +} + +void -+mn10300_cons_fix_new (fragS *frag, int off, int size, expressionS *exp) ++mn10300_cons_fix_new (fragS *frag, int off, int size, expressionS *exp, ++ bfd_reloc_code_real_type r ATTRIBUTE_UNUSED) +{ + struct mn10300_fixup fixup; + @@ -582969,13 +587000,12 @@ index 0000000..4029c64 +} diff --git a/gas/config/tc-mn10300.h b/gas/config/tc-mn10300.h new file mode 100644 -index 0000000..53c4150 +index 0000000..d502430 --- /dev/null +++ b/gas/config/tc-mn10300.h @@ -0,0 +1,126 @@ +/* tc-mn10300.h -- Header file for tc-mn10300.c. -+ Copyright 1996, 1997, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008 -+ Free Software Foundation, Inc. ++ Copyright (C) 1996-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -583015,9 +587045,10 @@ index 0000000..53c4150 + mn10300_parse_name ((NAME), (EXPRP), (MODE), (NEXTCHARP)) +int mn10300_parse_name (char const *, expressionS *, enum expr_mode, char *); + -+#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP) \ -+ mn10300_cons_fix_new ((FRAG), (OFF), (LEN), (EXP)) -+void mn10300_cons_fix_new (fragS *, int, int, expressionS *); ++#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP, RELOC) \ ++ mn10300_cons_fix_new ((FRAG), (OFF), (LEN), (EXP), (RELOC)) ++void mn10300_cons_fix_new (fragS *, int, int, expressionS *, ++ bfd_reloc_code_real_type); + +/* This is used to construct expressions out of @GOTOFF, @PLT and @GOT + symbols. The relocation type is stored in X_md. */ @@ -583101,13 +587132,12 @@ index 0000000..53c4150 +#define md_allow_eh_opt (linkrelax == 0) diff --git a/gas/config/tc-moxie.c b/gas/config/tc-moxie.c new file mode 100644 -index 0000000..fa8ace5 +index 0000000..430a144 --- /dev/null +++ b/gas/config/tc-moxie.c -@@ -0,0 +1,846 @@ +@@ -0,0 +1,845 @@ +/* tc-moxie.c -- Assemble code for moxie -+ Copyright 2009, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 2009-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -583953,13 +587983,13 @@ index 0000000..fa8ace5 +} diff --git a/gas/config/tc-moxie.h b/gas/config/tc-moxie.h new file mode 100644 -index 0000000..af4fe51 +index 0000000..d5a24cd --- /dev/null +++ b/gas/config/tc-moxie.h @@ -0,0 +1,47 @@ +/* tc-moxie.h -- Header file for tc-moxie.c. + -+ Copyright 2009, 2012 Free Software Foundation, Inc. ++ Copyright (C) 2009-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -584006,13 +588036,13 @@ index 0000000..af4fe51 +#define md_section_align(SEGMENT, SIZE) (SIZE) diff --git a/gas/config/tc-msp430.c b/gas/config/tc-msp430.c new file mode 100644 -index 0000000..c2a7b9b +index 0000000..1398b8c --- /dev/null +++ b/gas/config/tc-msp430.c -@@ -0,0 +1,4215 @@ +@@ -0,0 +1,3936 @@ +/* tc-msp430.c -- Assembler code for the Texas Instruments MSP430 + -+ Copyright (C) 2002-2013 Free Software Foundation, Inc. ++ Copyright (C) 2002-2014 Free Software Foundation, Inc. + Contributed by Dmitry Diky + + This file is part of GAS, the GNU Assembler. @@ -584276,499 +588306,36 @@ index 0000000..c2a7b9b + MSP_ISA_430Xv2 +} msp_isa; + -+struct mcu_type_s -+{ -+ char * name; -+ msp_isa isa; -+}; -+ -+static struct mcu_type_s mcu_types[] = -+{ -+ {"msp430afe221", MSP_ISA_430}, -+ {"msp430afe222", MSP_ISA_430}, -+ {"msp430afe223", MSP_ISA_430}, -+ {"msp430afe231", MSP_ISA_430}, -+ {"msp430afe232", MSP_ISA_430}, -+ {"msp430afe233", MSP_ISA_430}, -+ {"msp430afe251", MSP_ISA_430}, -+ {"msp430afe252", MSP_ISA_430}, -+ {"msp430afe253", MSP_ISA_430}, -+ {"msp430c091", MSP_ISA_430}, -+ {"msp430c092", MSP_ISA_430}, -+ {"msp430c111", MSP_ISA_430}, -+ {"msp430c1111", MSP_ISA_430}, -+ {"msp430c112", MSP_ISA_430}, -+ {"msp430c1121", MSP_ISA_430}, -+ {"msp430e112", MSP_ISA_430}, -+ {"msp430c1331", MSP_ISA_430}, -+ {"msp430c1351", MSP_ISA_430}, -+ {"msp430c311s", MSP_ISA_430}, -+ {"msp430c312", MSP_ISA_430}, -+ {"msp430c313", MSP_ISA_430}, -+ {"msp430c314", MSP_ISA_430}, -+ {"msp430c315", MSP_ISA_430}, -+ {"msp430c323", MSP_ISA_430}, -+ {"msp430c325", MSP_ISA_430}, -+ {"msp430c336", MSP_ISA_430}, -+ {"msp430c337", MSP_ISA_430}, -+ {"msp430c412", MSP_ISA_430}, -+ {"msp430c413", MSP_ISA_430}, -+ {"msp430e313", MSP_ISA_430}, -+ {"msp430e315", MSP_ISA_430}, -+ {"msp430e325", MSP_ISA_430}, -+ {"msp430e337", MSP_ISA_430}, -+ {"msp430f110", MSP_ISA_430}, -+ {"msp430f1101", MSP_ISA_430}, -+ {"msp430f1101a", MSP_ISA_430}, -+ {"msp430f1111", MSP_ISA_430}, -+ {"msp430f1111a", MSP_ISA_430}, -+ {"msp430f112", MSP_ISA_430}, -+ {"msp430f1121", MSP_ISA_430}, -+ {"msp430f1121a", MSP_ISA_430}, -+ {"msp430f1122", MSP_ISA_430}, -+ {"msp430f1132", MSP_ISA_430}, -+ {"msp430f122", MSP_ISA_430}, -+ {"msp430f1222", MSP_ISA_430}, -+ {"msp430f123", MSP_ISA_430}, -+ {"msp430f1232", MSP_ISA_430}, -+ {"msp430f133", MSP_ISA_430}, -+ {"msp430f135", MSP_ISA_430}, -+ {"msp430f147", MSP_ISA_430}, -+ {"msp430f1471", MSP_ISA_430}, -+ {"msp430f148", MSP_ISA_430}, -+ {"msp430f1481", MSP_ISA_430}, -+ {"msp430f149", MSP_ISA_430}, -+ {"msp430f1491", MSP_ISA_430}, -+ {"msp430f155", MSP_ISA_430}, -+ {"msp430f156", MSP_ISA_430}, -+ {"msp430f157", MSP_ISA_430}, -+ {"msp430f1610", MSP_ISA_430}, -+ {"msp430f1611", MSP_ISA_430}, -+ {"msp430f1612", MSP_ISA_430}, -+ {"msp430f167", MSP_ISA_430}, -+ {"msp430f168", MSP_ISA_430}, -+ {"msp430f169", MSP_ISA_430}, -+ {"msp430f2001", MSP_ISA_430}, -+ {"msp430f2002", MSP_ISA_430}, -+ {"msp430f2003", MSP_ISA_430}, -+ {"msp430f2011", MSP_ISA_430}, -+ {"msp430f2012", MSP_ISA_430}, -+ {"msp430f2013", MSP_ISA_430}, -+ {"msp430f2101", MSP_ISA_430}, -+ {"msp430f2111", MSP_ISA_430}, -+ {"msp430f2112", MSP_ISA_430}, -+ {"msp430f2121", MSP_ISA_430}, -+ {"msp430f2122", MSP_ISA_430}, -+ {"msp430f2131", MSP_ISA_430}, -+ {"msp430f2132", MSP_ISA_430}, -+ {"msp430f2232", MSP_ISA_430}, -+ {"msp430f2234", MSP_ISA_430}, -+ {"msp430f2252", MSP_ISA_430}, -+ {"msp430f2254", MSP_ISA_430}, -+ {"msp430f2272", MSP_ISA_430}, -+ {"msp430f2274", MSP_ISA_430}, -+ {"msp430f233", MSP_ISA_430}, -+ {"msp430f2330", MSP_ISA_430}, -+ {"msp430f235", MSP_ISA_430}, -+ {"msp430f2350", MSP_ISA_430}, -+ {"msp430f2370", MSP_ISA_430}, -+ {"msp430f2410", MSP_ISA_430}, -+ {"msp430f247", MSP_ISA_430}, -+ {"msp430f2471", MSP_ISA_430}, -+ {"msp430f248", MSP_ISA_430}, -+ {"msp430f2481", MSP_ISA_430}, -+ {"msp430f249", MSP_ISA_430}, -+ {"msp430f2491", MSP_ISA_430}, -+ {"msp430f412", MSP_ISA_430}, -+ {"msp430f413", MSP_ISA_430}, -+ {"msp430f4132", MSP_ISA_430}, -+ {"msp430f415", MSP_ISA_430}, -+ {"msp430f4152", MSP_ISA_430}, -+ {"msp430f417", MSP_ISA_430}, -+ {"msp430f423", MSP_ISA_430}, -+ {"msp430f423a", MSP_ISA_430}, -+ {"msp430f425", MSP_ISA_430}, -+ {"msp430f4250", MSP_ISA_430}, -+ {"msp430f425a", MSP_ISA_430}, -+ {"msp430f4260", MSP_ISA_430}, -+ {"msp430f427", MSP_ISA_430}, -+ {"msp430f4270", MSP_ISA_430}, -+ {"msp430f427a", MSP_ISA_430}, -+ {"msp430f435", MSP_ISA_430}, -+ {"msp430f4351", MSP_ISA_430}, -+ {"msp430f436", MSP_ISA_430}, -+ {"msp430f4361", MSP_ISA_430}, -+ {"msp430f437", MSP_ISA_430}, -+ {"msp430f4371", MSP_ISA_430}, -+ {"msp430f438", MSP_ISA_430}, -+ {"msp430f439", MSP_ISA_430}, -+ {"msp430f447", MSP_ISA_430}, -+ {"msp430f448", MSP_ISA_430}, -+ {"msp430f4481", MSP_ISA_430}, -+ {"msp430f449", MSP_ISA_430}, -+ {"msp430f4491", MSP_ISA_430}, -+ {"msp430f477", MSP_ISA_430}, -+ {"msp430f478", MSP_ISA_430}, -+ {"msp430f4783", MSP_ISA_430}, -+ {"msp430f4784", MSP_ISA_430}, -+ {"msp430f479", MSP_ISA_430}, -+ {"msp430f4793", MSP_ISA_430}, -+ {"msp430f4794", MSP_ISA_430}, -+ {"msp430fe423", MSP_ISA_430}, -+ {"msp430fe4232", MSP_ISA_430}, -+ {"msp430fe423a", MSP_ISA_430}, -+ {"msp430fe4242", MSP_ISA_430}, -+ {"msp430fe425", MSP_ISA_430}, -+ {"msp430fe4252", MSP_ISA_430}, -+ {"msp430fe425a", MSP_ISA_430}, -+ {"msp430fe427", MSP_ISA_430}, -+ {"msp430fe4272", MSP_ISA_430}, -+ {"msp430fe427a", MSP_ISA_430}, -+ {"msp430fg4250", MSP_ISA_430}, -+ {"msp430fg4260", MSP_ISA_430}, -+ {"msp430fg4270", MSP_ISA_430}, -+ {"msp430fg437", MSP_ISA_430}, -+ {"msp430fg438", MSP_ISA_430}, -+ {"msp430fg439", MSP_ISA_430}, -+ {"msp430fg477", MSP_ISA_430}, -+ {"msp430fg478", MSP_ISA_430}, -+ {"msp430fg479", MSP_ISA_430}, -+ {"msp430fw423", MSP_ISA_430}, -+ {"msp430fw425", MSP_ISA_430}, -+ {"msp430fw427", MSP_ISA_430}, -+ {"msp430fw428", MSP_ISA_430}, -+ {"msp430fw429", MSP_ISA_430}, -+ {"msp430g2001", MSP_ISA_430}, -+ {"msp430g2101", MSP_ISA_430}, -+ {"msp430g2102", MSP_ISA_430}, -+ {"msp430g2111", MSP_ISA_430}, -+ {"msp430g2112", MSP_ISA_430}, -+ {"msp430g2113", MSP_ISA_430}, -+ {"msp430g2121", MSP_ISA_430}, -+ {"msp430g2131", MSP_ISA_430}, -+ {"msp430g2132", MSP_ISA_430}, -+ {"msp430g2152", MSP_ISA_430}, -+ {"msp430g2153", MSP_ISA_430}, -+ {"msp430g2201", MSP_ISA_430}, -+ {"msp430g2202", MSP_ISA_430}, -+ {"msp430g2203", MSP_ISA_430}, -+ {"msp430g2210", MSP_ISA_430}, -+ {"msp430g2211", MSP_ISA_430}, -+ {"msp430g2212", MSP_ISA_430}, -+ {"msp430g2213", MSP_ISA_430}, -+ {"msp430g2221", MSP_ISA_430}, -+ {"msp430g2230", MSP_ISA_430}, -+ {"msp430g2231", MSP_ISA_430}, -+ {"msp430g2232", MSP_ISA_430}, -+ {"msp430g2233", MSP_ISA_430}, -+ {"msp430g2252", MSP_ISA_430}, -+ {"msp430g2253", MSP_ISA_430}, -+ {"msp430g2302", MSP_ISA_430}, -+ {"msp430g2303", MSP_ISA_430}, -+ {"msp430g2312", MSP_ISA_430}, -+ {"msp430g2313", MSP_ISA_430}, -+ {"msp430g2332", MSP_ISA_430}, -+ {"msp430g2333", MSP_ISA_430}, -+ {"msp430g2352", MSP_ISA_430}, -+ {"msp430g2353", MSP_ISA_430}, -+ {"msp430g2402", MSP_ISA_430}, -+ {"msp430g2403", MSP_ISA_430}, -+ {"msp430g2412", MSP_ISA_430}, -+ {"msp430g2413", MSP_ISA_430}, -+ {"msp430g2432", MSP_ISA_430}, -+ {"msp430g2433", MSP_ISA_430}, -+ {"msp430g2444", MSP_ISA_430}, -+ {"msp430g2452", MSP_ISA_430}, -+ {"msp430g2453", MSP_ISA_430}, -+ {"msp430g2513", MSP_ISA_430}, -+ {"msp430g2533", MSP_ISA_430}, -+ {"msp430g2544", MSP_ISA_430}, -+ {"msp430g2553", MSP_ISA_430}, -+ {"msp430g2744", MSP_ISA_430}, -+ {"msp430g2755", MSP_ISA_430}, -+ {"msp430g2855", MSP_ISA_430}, -+ {"msp430g2955", MSP_ISA_430}, -+ {"msp430l092", MSP_ISA_430}, -+ {"msp430p112", MSP_ISA_430}, -+ {"msp430p313", MSP_ISA_430}, -+ {"msp430p315", MSP_ISA_430}, -+ {"msp430p315s", MSP_ISA_430}, -+ {"msp430p325", MSP_ISA_430}, -+ {"msp430p337", MSP_ISA_430}, -+ {"msp430tch5e", MSP_ISA_430}, -+ -+ /* NB/ This section of the list should be kept in sync with the ones in: -+ gcc/config/msp430/t-msp430 -+ gcc/config/msp430/msp430.c */ -+ -+ {"msp430cg4616", MSP_ISA_430X}, -+ {"msp430cg4617", MSP_ISA_430X}, -+ {"msp430cg4618", MSP_ISA_430X}, -+ {"msp430cg4619", MSP_ISA_430X}, -+ {"msp430f2416", MSP_ISA_430X}, -+ {"msp430f2417", MSP_ISA_430X}, -+ {"msp430f2418", MSP_ISA_430X}, -+ {"msp430f2419", MSP_ISA_430X}, -+ {"msp430f2616", MSP_ISA_430X}, -+ {"msp430f2617", MSP_ISA_430X}, -+ {"msp430f2618", MSP_ISA_430X}, -+ {"msp430f2619", MSP_ISA_430X}, -+ {"msp430f47126", MSP_ISA_430X}, -+ {"msp430f47127", MSP_ISA_430X}, -+ {"msp430f47163", MSP_ISA_430X}, -+ {"msp430f47173", MSP_ISA_430X}, -+ {"msp430f47183", MSP_ISA_430X}, -+ {"msp430f47193", MSP_ISA_430X}, -+ {"msp430f47166", MSP_ISA_430X}, -+ {"msp430f47176", MSP_ISA_430X}, -+ {"msp430f47186", MSP_ISA_430X}, -+ {"msp430f47196", MSP_ISA_430X}, -+ {"msp430f47167", MSP_ISA_430X}, -+ {"msp430f47177", MSP_ISA_430X}, -+ {"msp430f47187", MSP_ISA_430X}, -+ {"msp430f47197", MSP_ISA_430X}, -+ {"msp430f46161", MSP_ISA_430X}, -+ {"msp430f46171", MSP_ISA_430X}, -+ {"msp430f46181", MSP_ISA_430X}, -+ {"msp430f46191", MSP_ISA_430X}, -+ {"msp430f4616", MSP_ISA_430X}, -+ {"msp430f4617", MSP_ISA_430X}, -+ {"msp430f4618", MSP_ISA_430X}, -+ {"msp430f4619", MSP_ISA_430X}, -+ {"msp430fg4616", MSP_ISA_430X}, -+ {"msp430fg4617", MSP_ISA_430X}, -+ {"msp430fg4618", MSP_ISA_430X}, -+ {"msp430fg4619", MSP_ISA_430X}, -+ -+ {"msp430x241x", MSP_ISA_430X}, -+ {"msp430x26x", MSP_ISA_430X}, -+ {"msp430x461x1", MSP_ISA_430X}, -+ {"msp430x46x", MSP_ISA_430X}, -+ {"msp430x471x3", MSP_ISA_430X}, -+ {"msp430x471x6", MSP_ISA_430X}, -+ {"msp430x471x7", MSP_ISA_430X}, -+ {"msp430xg46x", MSP_ISA_430X}, -+ -+ {"msp430f5418", MSP_ISA_430Xv2}, -+ {"msp430f5419", MSP_ISA_430Xv2}, -+ {"msp430f5435", MSP_ISA_430Xv2}, -+ {"msp430f5436", MSP_ISA_430Xv2}, -+ {"msp430f5437", MSP_ISA_430Xv2}, -+ {"msp430f5438", MSP_ISA_430Xv2}, -+ {"msp430f5418a", MSP_ISA_430Xv2}, -+ {"msp430f5419a", MSP_ISA_430Xv2}, -+ {"msp430f5435a", MSP_ISA_430Xv2}, -+ {"msp430f5436a", MSP_ISA_430Xv2}, -+ {"msp430f5437a", MSP_ISA_430Xv2}, -+ {"msp430f5438a", MSP_ISA_430Xv2}, -+ {"msp430f5212", MSP_ISA_430Xv2}, -+ {"msp430f5213", MSP_ISA_430Xv2}, -+ {"msp430f5214", MSP_ISA_430Xv2}, -+ {"msp430f5217", MSP_ISA_430Xv2}, -+ {"msp430f5218", MSP_ISA_430Xv2}, -+ {"msp430f5219", MSP_ISA_430Xv2}, -+ {"msp430f5222", MSP_ISA_430Xv2}, -+ {"msp430f5223", MSP_ISA_430Xv2}, -+ {"msp430f5224", MSP_ISA_430Xv2}, -+ {"msp430f5227", MSP_ISA_430Xv2}, -+ {"msp430f5228", MSP_ISA_430Xv2}, -+ {"msp430f5229", MSP_ISA_430Xv2}, -+ {"msp430f5304", MSP_ISA_430Xv2}, -+ {"msp430f5308", MSP_ISA_430Xv2}, -+ {"msp430f5309", MSP_ISA_430Xv2}, -+ {"msp430f5310", MSP_ISA_430Xv2}, -+ {"msp430f5340", MSP_ISA_430Xv2}, -+ {"msp430f5341", MSP_ISA_430Xv2}, -+ {"msp430f5342", MSP_ISA_430Xv2}, -+ {"msp430f5324", MSP_ISA_430Xv2}, -+ {"msp430f5325", MSP_ISA_430Xv2}, -+ {"msp430f5326", MSP_ISA_430Xv2}, -+ {"msp430f5327", MSP_ISA_430Xv2}, -+ {"msp430f5328", MSP_ISA_430Xv2}, -+ {"msp430f5329", MSP_ISA_430Xv2}, -+ {"msp430f5500", MSP_ISA_430Xv2}, -+ {"msp430f5501", MSP_ISA_430Xv2}, -+ {"msp430f5502", MSP_ISA_430Xv2}, -+ {"msp430f5503", MSP_ISA_430Xv2}, -+ {"msp430f5504", MSP_ISA_430Xv2}, -+ {"msp430f5505", MSP_ISA_430Xv2}, -+ {"msp430f5506", MSP_ISA_430Xv2}, -+ {"msp430f5507", MSP_ISA_430Xv2}, -+ {"msp430f5508", MSP_ISA_430Xv2}, -+ {"msp430f5509", MSP_ISA_430Xv2}, -+ {"msp430f5510", MSP_ISA_430Xv2}, -+ {"msp430f5513", MSP_ISA_430Xv2}, -+ {"msp430f5514", MSP_ISA_430Xv2}, -+ {"msp430f5515", MSP_ISA_430Xv2}, -+ {"msp430f5517", MSP_ISA_430Xv2}, -+ {"msp430f5519", MSP_ISA_430Xv2}, -+ {"msp430f5521", MSP_ISA_430Xv2}, -+ {"msp430f5522", MSP_ISA_430Xv2}, -+ {"msp430f5524", MSP_ISA_430Xv2}, -+ {"msp430f5525", MSP_ISA_430Xv2}, -+ {"msp430f5526", MSP_ISA_430Xv2}, -+ {"msp430f5527", MSP_ISA_430Xv2}, -+ {"msp430f5528", MSP_ISA_430Xv2}, -+ {"msp430f5529", MSP_ISA_430Xv2}, -+ {"cc430f5133", MSP_ISA_430Xv2}, -+ {"cc430f5135", MSP_ISA_430Xv2}, -+ {"cc430f5137", MSP_ISA_430Xv2}, -+ {"cc430f6125", MSP_ISA_430Xv2}, -+ {"cc430f6126", MSP_ISA_430Xv2}, -+ {"cc430f6127", MSP_ISA_430Xv2}, -+ {"cc430f6135", MSP_ISA_430Xv2}, -+ {"cc430f6137", MSP_ISA_430Xv2}, -+ {"cc430f5123", MSP_ISA_430Xv2}, -+ {"cc430f5125", MSP_ISA_430Xv2}, -+ {"cc430f5143", MSP_ISA_430Xv2}, -+ {"cc430f5145", MSP_ISA_430Xv2}, -+ {"cc430f5147", MSP_ISA_430Xv2}, -+ {"cc430f6143", MSP_ISA_430Xv2}, -+ {"cc430f6145", MSP_ISA_430Xv2}, -+ {"cc430f6147", MSP_ISA_430Xv2}, -+ {"msp430f5333", MSP_ISA_430Xv2}, -+ {"msp430f5335", MSP_ISA_430Xv2}, -+ {"msp430f5336", MSP_ISA_430Xv2}, -+ {"msp430f5338", MSP_ISA_430Xv2}, -+ {"msp430f5630", MSP_ISA_430Xv2}, -+ {"msp430f5631", MSP_ISA_430Xv2}, -+ {"msp430f5632", MSP_ISA_430Xv2}, -+ {"msp430f5633", MSP_ISA_430Xv2}, -+ {"msp430f5634", MSP_ISA_430Xv2}, -+ {"msp430f5635", MSP_ISA_430Xv2}, -+ {"msp430f5636", MSP_ISA_430Xv2}, -+ {"msp430f5637", MSP_ISA_430Xv2}, -+ {"msp430f5638", MSP_ISA_430Xv2}, -+ {"msp430f6433", MSP_ISA_430Xv2}, -+ {"msp430f6435", MSP_ISA_430Xv2}, -+ {"msp430f6436", MSP_ISA_430Xv2}, -+ {"msp430f6438", MSP_ISA_430Xv2}, -+ {"msp430f6630", MSP_ISA_430Xv2}, -+ {"msp430f6631", MSP_ISA_430Xv2}, -+ {"msp430f6632", MSP_ISA_430Xv2}, -+ {"msp430f6633", MSP_ISA_430Xv2}, -+ {"msp430f6634", MSP_ISA_430Xv2}, -+ {"msp430f6635", MSP_ISA_430Xv2}, -+ {"msp430f6636", MSP_ISA_430Xv2}, -+ {"msp430f6637", MSP_ISA_430Xv2}, -+ {"msp430f6638", MSP_ISA_430Xv2}, -+ {"msp430f5358", MSP_ISA_430Xv2}, -+ {"msp430f5359", MSP_ISA_430Xv2}, -+ {"msp430f5658", MSP_ISA_430Xv2}, -+ {"msp430f5659", MSP_ISA_430Xv2}, -+ {"msp430f6458", MSP_ISA_430Xv2}, -+ {"msp430f6459", MSP_ISA_430Xv2}, -+ {"msp430f6658", MSP_ISA_430Xv2}, -+ {"msp430f6659", MSP_ISA_430Xv2}, -+ {"msp430f5131", MSP_ISA_430Xv2}, -+ {"msp430f5151", MSP_ISA_430Xv2}, -+ {"msp430f5171", MSP_ISA_430Xv2}, -+ {"msp430f5132", MSP_ISA_430Xv2}, -+ {"msp430f5152", MSP_ISA_430Xv2}, -+ {"msp430f5172", MSP_ISA_430Xv2}, -+ {"msp430f6720", MSP_ISA_430Xv2}, -+ {"msp430f6721", MSP_ISA_430Xv2}, -+ {"msp430f6723", MSP_ISA_430Xv2}, -+ {"msp430f6724", MSP_ISA_430Xv2}, -+ {"msp430f6725", MSP_ISA_430Xv2}, -+ {"msp430f6726", MSP_ISA_430Xv2}, -+ {"msp430f6730", MSP_ISA_430Xv2}, -+ {"msp430f6731", MSP_ISA_430Xv2}, -+ {"msp430f6733", MSP_ISA_430Xv2}, -+ {"msp430f6734", MSP_ISA_430Xv2}, -+ {"msp430f6735", MSP_ISA_430Xv2}, -+ {"msp430f6736", MSP_ISA_430Xv2}, -+ {"msp430f67451", MSP_ISA_430Xv2}, -+ {"msp430f67651", MSP_ISA_430Xv2}, -+ {"msp430f67751", MSP_ISA_430Xv2}, -+ {"msp430f67461", MSP_ISA_430Xv2}, -+ {"msp430f67661", MSP_ISA_430Xv2}, -+ {"msp430f67761", MSP_ISA_430Xv2}, -+ {"msp430f67471", MSP_ISA_430Xv2}, -+ {"msp430f67671", MSP_ISA_430Xv2}, -+ {"msp430f67771", MSP_ISA_430Xv2}, -+ {"msp430f67481", MSP_ISA_430Xv2}, -+ {"msp430f67681", MSP_ISA_430Xv2}, -+ {"msp430f67781", MSP_ISA_430Xv2}, -+ {"msp430f67491", MSP_ISA_430Xv2}, -+ {"msp430f67691", MSP_ISA_430Xv2}, -+ {"msp430f67791", MSP_ISA_430Xv2}, -+ {"msp430f6745", MSP_ISA_430Xv2}, -+ {"msp430f6765", MSP_ISA_430Xv2}, -+ {"msp430f6775", MSP_ISA_430Xv2}, -+ {"msp430f6746", MSP_ISA_430Xv2}, -+ {"msp430f6766", MSP_ISA_430Xv2}, -+ {"msp430f6776", MSP_ISA_430Xv2}, -+ {"msp430f6747", MSP_ISA_430Xv2}, -+ {"msp430f6767", MSP_ISA_430Xv2}, -+ {"msp430f6777", MSP_ISA_430Xv2}, -+ {"msp430f6748", MSP_ISA_430Xv2}, -+ {"msp430f6768", MSP_ISA_430Xv2}, -+ {"msp430f6778", MSP_ISA_430Xv2}, -+ {"msp430f6749", MSP_ISA_430Xv2}, -+ {"msp430f6769", MSP_ISA_430Xv2}, -+ {"msp430f6779", MSP_ISA_430Xv2}, -+ {"msp430fr5720", MSP_ISA_430Xv2}, -+ {"msp430fr5721", MSP_ISA_430Xv2}, -+ {"msp430fr5722", MSP_ISA_430Xv2}, -+ {"msp430fr5723", MSP_ISA_430Xv2}, -+ {"msp430fr5724", MSP_ISA_430Xv2}, -+ {"msp430fr5725", MSP_ISA_430Xv2}, -+ {"msp430fr5726", MSP_ISA_430Xv2}, -+ {"msp430fr5727", MSP_ISA_430Xv2}, -+ {"msp430fr5728", MSP_ISA_430Xv2}, -+ {"msp430fr5729", MSP_ISA_430Xv2}, -+ {"msp430fr5730", MSP_ISA_430Xv2}, -+ {"msp430fr5731", MSP_ISA_430Xv2}, -+ {"msp430fr5732", MSP_ISA_430Xv2}, -+ {"msp430fr5733", MSP_ISA_430Xv2}, -+ {"msp430fr5734", MSP_ISA_430Xv2}, -+ {"msp430fr5735", MSP_ISA_430Xv2}, -+ {"msp430fr5736", MSP_ISA_430Xv2}, -+ {"msp430fr5737", MSP_ISA_430Xv2}, -+ {"msp430fr5738", MSP_ISA_430Xv2}, -+ {"msp430fr5739", MSP_ISA_430Xv2}, -+ {"msp430bt5190", MSP_ISA_430Xv2}, -+ {"msp430fr5949", MSP_ISA_430Xv2}, -+ {"msp430fr5969", MSP_ISA_430Xv2}, -+ {"msp430sl5438a", MSP_ISA_430Xv2}, -+ -+ /* Generic names. */ -+ {"msp430", MSP_ISA_430}, -+ {"msp430X", MSP_ISA_430X}, -+ {"msp430Xv2", MSP_ISA_430Xv2}, -+ -+ {NULL, 0} -+}; -+ -+static struct mcu_type_s default_mcu = { "msp430x11", MSP_ISA_430 }; -+static struct mcu_type_s msp430x_mcu = { "msp430x", MSP_ISA_430X }; -+static struct mcu_type_s msp430xv2_mcu = { "msp430xv2", MSP_ISA_430Xv2 }; -+ -+static struct mcu_type_s * msp430_mcu = & default_mcu; ++static enum msp_isa selected_isa = MSP_ISA_430Xv2; + +static inline bfd_boolean +target_is_430x (void) +{ -+ return msp430_mcu->isa >= MSP_ISA_430X; ++ return selected_isa >= MSP_ISA_430X; +} + +static inline bfd_boolean +target_is_430xv2 (void) +{ -+ return msp430_mcu->isa == MSP_ISA_430Xv2; ++ return selected_isa == MSP_ISA_430Xv2; +} + -+/* Generate a 16-bit relocation. -+ For the 430X we generate a relocation without linkwer range checking -+ if the value is being used in an extended (ie 20-bit) instruction. ++/* Generate an absolute 16-bit relocation. ++ For the 430X we generate a relocation without linker range checking ++ if the value is being used in an extended (ie 20-bit) instruction, ++ otherwise if have a shifted expression we use a HI reloc. + For the 430 we generate a relocation without assembler range checking -+ if we are handling an immediate value or a byte-width instruction. */ ++ if we are handling an immediate value or a byte-width instruction. */ ++ +#undef CHECK_RELOC_MSP430 -+#define CHECK_RELOC_MSP430 \ -+ (target_is_430x () \ -+ ? (extended_op ? BFD_RELOC_16 : BFD_RELOC_MSP430X_ABS16) \ -+ : ((imm_op || byte_op) \ ++#define CHECK_RELOC_MSP430(OP) \ ++ (target_is_430x () \ ++ ? (extended_op \ ++ ? BFD_RELOC_16 \ ++ : ((OP).vshift == 1) \ ++ ? BFD_RELOC_MSP430_ABS_HI16 \ ++ : BFD_RELOC_MSP430X_ABS16) \ ++ : ((imm_op || byte_op) \ + ? BFD_RELOC_MSP430_16_BYTE : BFD_RELOC_MSP430_16)) + +/* Generate a 16-bit pc-relative relocation. @@ -585145,9 +588712,12 @@ index 0000000..c2a7b9b +#define OPTION_POLYMORPHS 'P' +#define OPTION_LARGE 'l' +static bfd_boolean large_model = FALSE; -+#define OPTION_INTR_NOPS 'n' +#define OPTION_NO_INTR_NOPS 'N' ++#define OPTION_INTR_NOPS 'n' +static bfd_boolean gen_interrupt_nops = FALSE; ++#define OPTION_WARN_INTR_NOPS 'y' ++#define OPTION_NO_WARN_INTR_NOPS 'Y' ++static bfd_boolean warn_interrupt_nops = TRUE; +#define OPTION_MCPU 'c' +#define OPTION_MOVE_DATA 'd' +static bfd_boolean move_data = FALSE; @@ -585164,63 +588734,108 @@ index 0000000..c2a7b9b + target_is_430x () ? bfd_mach_msp430x : bfd_mach_msp11); +} + -+static void -+show_mcu_list (FILE * stream) ++/* This is the full list of MCU names that are known to only ++ support the 430 ISA. */ ++static const char * msp430_mcu_names [] = +{ -+ int i; -+ -+ fprintf (stream, _("Known MCU names:\n")); -+ -+ for (i = 0; mcu_types[i].name; i++) -+ { -+ fprintf (stream, "%14.14s", mcu_types[i].name); -+ if ((i % 6) == 5) -+ fprintf (stream, "\n"); -+ } -+ -+ fprintf (stream, "\n"); -+} ++"msp430afe221", "msp430afe222", "msp430afe223", "msp430afe231", ++"msp430afe232", "msp430afe233", "msp430afe251", "msp430afe252", ++"msp430afe253", "msp430c091", "msp430c092", "msp430c111", ++"msp430c1111", "msp430c112", "msp430c1121", "msp430c1331", ++"msp430c1351", "msp430c311s", "msp430c312", "msp430c313", ++"msp430c314", "msp430c315", "msp430c323", "msp430c325", ++"msp430c336", "msp430c337", "msp430c412", "msp430c413", ++"msp430e112", "msp430e313", "msp430e315", "msp430e325", ++"msp430e337", "msp430f110", "msp430f1101", "msp430f1101a", ++"msp430f1111", "msp430f1111a", "msp430f112", "msp430f1121", ++"msp430f1121a", "msp430f1122", "msp430f1132", "msp430f122", ++"msp430f1222", "msp430f123", "msp430f1232", "msp430f133", ++"msp430f135", "msp430f147", "msp430f1471", "msp430f148", ++"msp430f1481", "msp430f149", "msp430f1491", "msp430f155", ++"msp430f156", "msp430f157", "msp430f1610", "msp430f1611", ++"msp430f1612", "msp430f167", "msp430f168", "msp430f169", ++"msp430f2001", "msp430f2002", "msp430f2003", "msp430f2011", ++"msp430f2012", "msp430f2013", "msp430f2101", "msp430f2111", ++"msp430f2112", "msp430f2121", "msp430f2122", "msp430f2131", ++"msp430f2132", "msp430f2232", "msp430f2234", "msp430f2252", ++"msp430f2254", "msp430f2272", "msp430f2274", "msp430f233", ++"msp430f2330", "msp430f235", "msp430f2350", "msp430f2370", ++"msp430f2410", "msp430f247", "msp430f2471", "msp430f248", ++"msp430f2481", "msp430f249", "msp430f2491", "msp430f412", ++"msp430f413", "msp430f4132", "msp430f415", "msp430f4152", ++"msp430f417", "msp430f423", "msp430f423a", "msp430f425", ++"msp430f4250", "msp430f425a", "msp430f4260", "msp430f427", ++"msp430f4270", "msp430f427a", "msp430f435", "msp430f4351", ++"msp430f436", "msp430f4361", "msp430f437", "msp430f4371", ++"msp430f438", "msp430f439", "msp430f447", "msp430f448", ++"msp430f4481", "msp430f449", "msp430f4491", "msp430f477", ++"msp430f478", "msp430f4783", "msp430f4784", "msp430f479", ++"msp430f4793", "msp430f4794", "msp430fe423", "msp430fe4232", ++"msp430fe423a", "msp430fe4242", "msp430fe425", "msp430fe4252", ++"msp430fe425a", "msp430fe427", "msp430fe4272", "msp430fe427a", ++"msp430fg4250", "msp430fg4260", "msp430fg4270", "msp430fg437", ++"msp430fg438", "msp430fg439", "msp430fg477", "msp430fg478", ++"msp430fg479", "msp430fw423", "msp430fw425", "msp430fw427", ++"msp430fw428", "msp430fw429", "msp430g2001", "msp430g2101", ++"msp430g2102", "msp430g2111", "msp430g2112", "msp430g2113", ++"msp430g2121", "msp430g2131", "msp430g2132", "msp430g2152", ++"msp430g2153", "msp430g2201", "msp430g2202", "msp430g2203", ++"msp430g2210", "msp430g2211", "msp430g2212", "msp430g2213", ++"msp430g2221", "msp430g2230", "msp430g2231", "msp430g2232", ++"msp430g2233", "msp430g2252", "msp430g2253", "msp430g2302", ++"msp430g2303", "msp430g2312", "msp430g2313", "msp430g2332", ++"msp430g2333", "msp430g2352", "msp430g2353", "msp430g2402", ++"msp430g2403", "msp430g2412", "msp430g2413", "msp430g2432", ++"msp430g2433", "msp430g2444", "msp430g2452", "msp430g2453", ++"msp430g2513", "msp430g2533", "msp430g2544", "msp430g2553", ++"msp430g2744", "msp430g2755", "msp430g2855", "msp430g2955", ++"msp430i2020", "msp430i2021", "msp430i2030", "msp430i2031", ++"msp430i2040", "msp430i2041", "msp430l092", "msp430p112", ++"msp430p313", "msp430p315", "msp430p315s", "msp430p325", ++"msp430p337", "msp430tch5e" ++}; + +int +md_parse_option (int c, char * arg) +{ -+ int i; -+ + switch (c) + { + case OPTION_MMCU: + if (arg == NULL) + as_fatal (_("MCU option requires a name\n")); + -+ for (i = 0; mcu_types[i].name; ++i) -+ if (strcasecmp (mcu_types[i].name, arg) == 0) -+ break; -+ -+ if (mcu_types[i].name == NULL) -+ { -+ show_mcu_list (stderr); -+ as_fatal (_("unknown MCU: %s\n"), arg); -+ } -+ -+ /* Allow switching to the same or a lesser architecture. */ -+ if (msp430_mcu == &default_mcu || msp430_mcu->isa >= mcu_types[i].isa) -+ msp430_mcu = mcu_types + i; ++ if (strcasecmp ("msp430", arg) == 0) ++ selected_isa = MSP_ISA_430; ++ else if (strcasecmp ("msp430xv2", arg) == 0) ++ selected_isa = MSP_ISA_430Xv2; ++ else if (strcasecmp ("msp430x", arg) == 0) ++ selected_isa = MSP_ISA_430X; + else -+ as_fatal (_("redefinition of mcu type '%s' to '%s'"), -+ msp430_mcu->name, mcu_types[i].name); ++ { ++ int i; ++ ++ for (i = sizeof msp430_mcu_names / sizeof msp430_mcu_names[0]; i--;) ++ if (strcasecmp (msp430_mcu_names[i], arg) == 0) ++ { ++ selected_isa = MSP_ISA_430; ++ break; ++ } ++ } ++ /* It is not an error if we do not match the MCU name. */ + return 1; + + case OPTION_MCPU: -+ if (strcmp (arg, "430") == 0) -+ msp430_mcu = & default_mcu; -+ else if (strcmp (arg, "430x") == 0 -+ || strcmp (arg, "430X") == 0) -+ msp430_mcu = & msp430x_mcu; -+ else if (strcasecmp (arg, "430xv2") == 0) -+ msp430_mcu = & msp430xv2_mcu; ++ if (strcmp (arg, "430") == 0 ++ || strcasecmp (arg, "msp430") == 0) ++ selected_isa = MSP_ISA_430; ++ else if (strcasecmp (arg, "430x") == 0 ++ || strcasecmp (arg, "msp430x") == 0) ++ selected_isa = MSP_ISA_430X; ++ else if (strcasecmp (arg, "430xv2") == 0 ++ || strcasecmp (arg, "msp430xv2") == 0) ++ selected_isa = MSP_ISA_430Xv2; + else + as_fatal (_("unrecognised argument to -mcpu option '%s'"), arg); -+ + return 1; + + case OPTION_RELAX: @@ -585242,6 +588857,13 @@ index 0000000..c2a7b9b + gen_interrupt_nops = TRUE; + return 1; + ++ case OPTION_WARN_INTR_NOPS: ++ warn_interrupt_nops = TRUE; ++ return 1; ++ case OPTION_NO_WARN_INTR_NOPS: ++ warn_interrupt_nops = FALSE; ++ return 1; ++ + case OPTION_MOVE_DATA: + move_data = TRUE; + return 1; @@ -585250,6 +588872,18 @@ index 0000000..c2a7b9b + return 0; +} + ++/* The intention here is to have the mere presence of these sections ++ cause the object to have a reference to a well-known symbol. This ++ reference pulls in the bits of the runtime (crt0) that initialize ++ these sections. Thus, for example, the startup code to call ++ memset() to initialize .bss will only be linked in when there is a ++ non-empty .bss section. Otherwise, the call would exist but have a ++ zero length parameter, which is a waste of memory and cycles. ++ ++ The code which initializes these sections should have a global ++ label for these symbols, and should be marked with KEEP() in the ++ linker script. ++ */ +static void +msp430_section (int arg) +{ @@ -585260,15 +588894,57 @@ index 0000000..c2a7b9b + || strncmp (name, ".gnu.linkonce.b.", 16) == 0) + (void) symbol_find_or_make ("__crt0_init_bss"); + -+ if (move_data -+ && (strncmp (name, ".data", 5) == 0 -+ || strncmp (name, ".gnu.linkonce.d.", 16) == 0)) ++ if (strncmp (name, ".data", 5) == 0 ++ || strncmp (name, ".gnu.linkonce.d.", 16) == 0) + (void) symbol_find_or_make ("__crt0_movedata"); + + input_line_pointer = saved_ilp; + obj_elf_section (arg); +} + ++void ++msp430_frob_section (asection *sec) ++{ ++ const char *name = sec->name; ++ ++ if (sec->size == 0) ++ return; ++ ++ if (strncmp (name, ".bss", 4) == 0 ++ || strncmp (name, ".gnu.linkonce.b.", 16) == 0) ++ (void) symbol_find_or_make ("__crt0_init_bss"); ++ ++ if (strncmp (name, ".data", 5) == 0 ++ || strncmp (name, ".gnu.linkonce.d.", 16) == 0) ++ (void) symbol_find_or_make ("__crt0_movedata"); ++} ++ ++static void ++msp430_lcomm (int ignore ATTRIBUTE_UNUSED) ++{ ++ symbolS *symbolP = s_comm_internal (0, s_lcomm_internal); ++ ++ if (symbolP) ++ symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; ++ (void) symbol_find_or_make ("__crt0_init_bss"); ++} ++ ++static void ++msp430_comm (int needs_align) ++{ ++ s_comm_internal (needs_align, elf_common_parse); ++ (void) symbol_find_or_make ("__crt0_init_bss"); ++} ++ ++static void ++msp430_refsym (int arg ATTRIBUTE_UNUSED) ++{ ++ char sym_name[1024]; ++ input_line_pointer = extract_word (input_line_pointer, sym_name, 1024); ++ ++ (void) symbol_find_or_make (sym_name); ++} ++ +const pseudo_typeS md_pseudo_table[] = +{ + {"arch", msp430_set_arch, OPTION_MMCU}, @@ -585279,10 +588955,13 @@ index 0000000..c2a7b9b + {"sect", msp430_section, 0}, + {"sect.s", msp430_section, 0}, + {"pushsection", msp430_section, 1}, ++ {"refsym", msp430_refsym, 0}, ++ {"comm", msp430_comm, 0}, ++ {"lcomm", msp430_lcomm, 0}, + {NULL, NULL, 0} +}; + -+const char *md_shortopts = "mm:,mP,mQ,ml,mN"; ++const char *md_shortopts = "mm:,mP,mQ,ml,mN,mn,my,mY"; + +struct option md_longopts[] = +{ @@ -585293,6 +588972,8 @@ index 0000000..c2a7b9b + {"ml", no_argument, NULL, OPTION_LARGE}, + {"mN", no_argument, NULL, OPTION_NO_INTR_NOPS}, + {"mn", no_argument, NULL, OPTION_INTR_NOPS}, ++ {"mY", no_argument, NULL, OPTION_NO_WARN_INTR_NOPS}, ++ {"my", no_argument, NULL, OPTION_WARN_INTR_NOPS}, + {"md", no_argument, NULL, OPTION_MOVE_DATA}, + {NULL, no_argument, NULL, 0} +}; @@ -585312,13 +588993,15 @@ index 0000000..c2a7b9b + fprintf (stream, + _(" -ml - enable large code model\n")); + fprintf (stream, -+ _(" -mN - disable generation of NOP after changing interrupts\n")); ++ _(" -mN - do not insert NOPs after changing interrupts (default)\n")); + fprintf (stream, -+ _(" -mn - enable generation of NOP after changing interrupts\n")); ++ _(" -mn - insert a NOP after changing interrupts\n")); ++ fprintf (stream, ++ _(" -mY - do not warn about missing NOPs after changing interrupts\n")); ++ fprintf (stream, ++ _(" -my - warn about missing NOPs after changing interrupts (default)\n")); + fprintf (stream, + _(" -md - Force copying of data from ROM to RAM at startup\n")); -+ -+ show_mcu_list (stream); +} + +symbolS * @@ -585403,7 +589086,7 @@ index 0000000..c2a7b9b +msp430_srcoperand (struct msp430_operand_s * op, + char * l, + int bin, -+ int * imm_op, ++ bfd_boolean * imm_op, + bfd_boolean allow_20bit_values, + bfd_boolean constants_allowed) +{ @@ -585423,7 +589106,7 @@ index 0000000..c2a7b9b + hhi(x) - x = (x >> 48) & 0xffff + The value _MUST_ be constant expression: #hlo(1231231231). */ + -+ *imm_op = 1; ++ *imm_op = TRUE; + + if (strncasecmp (h, "#llo(", 5) == 0) + { @@ -585458,9 +589141,10 @@ index 0000000..c2a7b9b + + op->reg = 0; /* Reg PC. */ + op->am = 3; -+ op->ol = 1; /* Immediate will follow an instruction. */ ++ op->ol = 1; /* Immediate will follow an instruction. */ + __tl = h + 1 + rval; + op->mode = OP_EXP; ++ op->vshift = vshift; + + parse_exp (__tl, &(op->exp)); + if (op->exp.X_op == O_constant) @@ -585476,6 +589160,7 @@ index 0000000..c2a7b9b + { + x = (x >> 16) & 0xffff; + op->exp.X_add_number = x; ++ op->vshift = 0; + } + else if (vshift > 1) + { @@ -585484,6 +589169,7 @@ index 0000000..c2a7b9b + else + op->exp.X_add_number = 0; /* Nothing left. */ + x = op->exp.X_add_number; ++ op->vshift = 0; + } + + if (allow_20bit_values) @@ -585573,16 +589259,20 @@ index 0000000..c2a7b9b + } + else if (op->exp.X_op == O_symbol) + { ++ if (vshift > 1) ++ as_bad (_("error: unsupported #foo() directive used on symbol")); + op->mode = OP_EXP; + } + else if (op->exp.X_op == O_big) + { + short x; ++ + if (vshift != -1) + { + op->exp.X_op = O_constant; + op->exp.X_add_number = 0xffff & generic_bignum[vshift]; + x = op->exp.X_add_number; ++ op->vshift = 0; + } + else + { @@ -585656,6 +589346,7 @@ index 0000000..c2a7b9b + __tl = h + 1; + parse_exp (__tl, &(op->exp)); + op->mode = OP_EXP; ++ op->vshift = 0; + if (op->exp.X_op == O_constant) + { + int x = op->exp.X_add_number; @@ -585719,6 +589410,7 @@ index 0000000..c2a7b9b + as_bad (_("cannot use indirect addressing with the PC")); + return 1; + } ++ + return 0; + } + @@ -585729,7 +589421,7 @@ index 0000000..c2a7b9b + char *m = strrchr (l, ')'); + char *t; + -+ *imm_op = 1; ++ *imm_op = TRUE; + + if (!h) + break; @@ -585762,6 +589454,7 @@ index 0000000..c2a7b9b + __tl = l; + *h = 0; + op->mode = OP_EXP; ++ op->vshift = 0; + parse_exp (__tl, &(op->exp)); + if (op->exp.X_op == O_constant) + { @@ -585823,6 +589516,7 @@ index 0000000..c2a7b9b + /* An expression starting with a minus sign is a constant, not an address. */ + op->am = (*l == '-' ? 3 : 1); + op->ol = 1; ++ op->vshift = 0; + __tl = l; + parse_exp (__tl, &(op->exp)); + return 0; @@ -585857,6 +589551,7 @@ index 0000000..c2a7b9b + op->mode = OP_EXP; + op->am = 1; + op->ol = 1; ++ op->vshift = 0; + parse_exp (__tl, &(op->exp)); + + if (op->exp.X_op != O_constant || op->exp.X_add_number != 0) @@ -585877,7 +589572,6 @@ index 0000000..c2a7b9b + return 0; +} + -+ +/* Attempt to encode a MOVA instruction with the given operands. + Returns the length of the encoded instruction if successful + or 0 upon failure. If the encoding fails, an error message @@ -586137,6 +589831,8 @@ index 0000000..c2a7b9b + return 0; +} + ++static bfd_boolean check_for_nop = FALSE; ++ +#define is_opcode(NAME) (strcmp (opcode->name, NAME) == 0) + +/* Parse instruction operands. @@ -586153,7 +589849,7 @@ index 0000000..c2a7b9b + struct msp430_operand_s op1, op2; + int res = 0; + static short ZEROS = 0; -+ int byte_op, imm_op; ++ bfd_boolean byte_op, imm_op; + int op_length = 0; + int fmt; + int extended = 0x1800; @@ -586162,6 +589858,7 @@ index 0000000..c2a7b9b + const char * error_message; + static signed int repeat_count = 0; + bfd_boolean fix_emitted; ++ bfd_boolean nop_check_needed = FALSE; + + /* Opcode is the one from opcodes table + line contains something like @@ -586169,7 +589866,7 @@ index 0000000..c2a7b9b + or + .b @r2+, 5(R1). */ + -+ byte_op = 0; ++ byte_op = FALSE; + addr_op = FALSE; + if (*line == '.') + { @@ -586181,7 +589878,7 @@ index 0000000..c2a7b9b + case 'b': + /* Byte operation. */ + bin |= BYTE_OPERATION; -+ byte_op = 1; ++ byte_op = TRUE; + check = TRUE; + break; + @@ -586263,7 +589960,7 @@ index 0000000..c2a7b9b + memset (&op1, 0, sizeof (op1)); + memset (&op2, 0, sizeof (op2)); + -+ imm_op = 0; ++ imm_op = FALSE; + + if ((fmt = opcode->fmt) < 0) + { @@ -586294,12 +589991,40 @@ index 0000000..c2a7b9b + repeat_count = 0; + } + ++ if (check_for_nop && is_opcode ("nop")) ++ check_for_nop = FALSE; ++ + switch (fmt) + { + case 0: /* Emulated. */ + switch (opcode->insn_opnumb) + { + case 0: ++ if (is_opcode ("eint") || is_opcode ("dint")) ++ { ++ if (check_for_nop) ++ { ++ if (warn_interrupt_nops) ++ { ++ if (gen_interrupt_nops) ++ as_warn (_("NOP inserted between two instructions that change interrupt state")); ++ else ++ as_warn (_("a NOP might be needed here because of successive changes in interrupt state")); ++ } ++ ++ if (gen_interrupt_nops) ++ { ++ /* Emit a NOP between interrupt enable/disable. ++ See 1.3.4.1 of the MSP430x5xx User Guide. */ ++ insn_length += 2; ++ frag = frag_more (2); ++ bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag); ++ } ++ } ++ ++ nop_check_needed = TRUE; ++ } ++ + /* Set/clear bits instructions. */ + if (extended_op) + { @@ -586308,25 +590033,13 @@ index 0000000..c2a7b9b + + /* Emit the extension word. */ + insn_length += 2; -+ frag = frag_more (insn_length); ++ frag = frag_more (2); + bfd_putl16 (extended, frag); + } + + insn_length += 2; -+ frag = frag_more (insn_length); ++ frag = frag_more (2); + bfd_putl16 ((bfd_vma) bin, frag); -+ -+ if (gen_interrupt_nops -+ && (is_opcode ("eint") || is_opcode ("dint"))) -+ { -+ /* Emit a NOP following interrupt enable/disable. -+ See 1.3.4.1 of the MSP430x5xx User Guide. */ -+ insn_length += 2; -+ frag = frag_more (2); -+ as_warn (_("a NOP instruction has been inserted after %s"), -+ opcode->name); -+ bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag); -+ } + dwarf2_emit_insn (insn_length); + break; + @@ -586337,9 +590050,37 @@ index 0000000..c2a7b9b + if (res) + break; + ++ bin |= (op1.reg | (op1.am << 7)); ++ ++ if (is_opcode ("clr") && bin == 0x4302 /* CLR R2*/) ++ { ++ if (check_for_nop) ++ { ++ if (warn_interrupt_nops) ++ { ++ if (gen_interrupt_nops) ++ as_warn (_("NOP inserted between two instructions that change interrupt state")); ++ else ++ as_warn (_("a NOP might be needed here because of successive changes in interrupt state")); ++ } ++ ++ if (gen_interrupt_nops) ++ { ++ /* Emit a NOP between interrupt enable/disable. ++ See 1.3.4.1 of the MSP430x5xx User Guide. */ ++ insn_length += 2; ++ frag = frag_more (2); ++ bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag); ++ } ++ } ++ ++ nop_check_needed = TRUE; ++ } ++ + /* Compute the entire instruction length, in bytes. */ -+ insn_length = (extended_op ? 2 : 0) + 2 + (op1.ol * 2); -+ frag = frag_more (insn_length); ++ op_length = (extended_op ? 2 : 0) + 2 + (op1.ol * 2); ++ insn_length += op_length; ++ frag = frag_more (op_length); + where = frag - frag_now->fr_literal; + + if (extended_op) @@ -586372,7 +590113,6 @@ index 0000000..c2a7b9b + where += 2; + } + -+ bin |= (op1.reg | (op1.am << 7)); + bfd_putl16 ((bfd_vma) bin, frag); + frag += 2; + where += 2; @@ -586391,7 +590131,7 @@ index 0000000..c2a7b9b + { + if (op1.reg) + fix_new_exp (frag_now, where, 2, -+ &(op1.exp), FALSE, CHECK_RELOC_MSP430); ++ &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1)); + else + fix_new_exp (frag_now, where, 2, + &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL); @@ -586399,19 +590139,6 @@ index 0000000..c2a7b9b + } + } + -+ if (gen_interrupt_nops -+ && is_opcode ("clr") -+ && bin == 0x4302 /* CLR R2*/) -+ { -+ /* Emit a NOP following interrupt enable/disable. -+ See 1.3.4.1 of the MSP430x5xx User Guide. */ -+ insn_length += 2; -+ frag = frag_more (2); -+ bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag); -+ as_warn (_("a NOP instruction has been inserted after %s"), -+ opcode->name); -+ } -+ + dwarf2_emit_insn (insn_length); + break; + @@ -586439,7 +590166,7 @@ index 0000000..c2a7b9b + || is_opcode ("rlc"))) + { + as_bad (_("%s: attempt to rotate the PC register"), opcode->name); -+ return 0; ++ break; + } + + if (extended_op) @@ -586506,7 +590233,7 @@ index 0000000..c2a7b9b + { + if (op1.reg || (op1.reg == 0 && op1.am == 3)) /* Not PC relative. */ + fix_new_exp (frag_now, where, 2, -+ &(op1.exp), FALSE, CHECK_RELOC_MSP430); ++ &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1)); + else + fix_new_exp (frag_now, where, 2, + &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL); @@ -586530,7 +590257,7 @@ index 0000000..c2a7b9b + { + if (op2.reg) /* Not PC relative. */ + fix_new_exp (frag_now, where, 2, -+ &(op2.exp), FALSE, CHECK_RELOC_MSP430); ++ &(op2.exp), FALSE, CHECK_RELOC_MSP430 (op2)); + else + fix_new_exp (frag_now, where, 2, + &(op2.exp), TRUE, CHECK_RELOC_MSP430_PCREL); @@ -586546,7 +590273,7 @@ index 0000000..c2a7b9b + if (extended_op) + { + as_bad ("Internal error: state 0/3 not coded for extended instructions"); -+ return 0; ++ break; + } + + line = extract_operand (line, l1, sizeof (l1)); @@ -586554,8 +590281,8 @@ index 0000000..c2a7b9b + if (res) + break; + -+ byte_op = 0; -+ imm_op = 0; ++ byte_op = FALSE; ++ imm_op = FALSE; + bin |= ((op1.reg << 8) | (op1.am << 4)); + op_length = 2 + 2 * op1.ol; + frag = frag_more (op_length); @@ -586576,7 +590303,7 @@ index 0000000..c2a7b9b + + if (op1.reg || (op1.reg == 0 && op1.am == 3)) + fix_new_exp (frag_now, where, 2, -+ &(op1.exp), FALSE, CHECK_RELOC_MSP430); ++ &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1)); + else + fix_new_exp (frag_now, where, 2, + &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL); @@ -586591,14 +590318,14 @@ index 0000000..c2a7b9b + fix_emitted = FALSE; + + line = extract_operand (line, l1, sizeof (l1)); -+ imm_op = 0; ++ imm_op = FALSE; + + res = msp430_srcoperand (&op1, l1, opcode->bin_opcode, &imm_op, + extended_op, FALSE); + if (res) + break; + -+ byte_op = 0; ++ byte_op = FALSE; + + op_length = 2 + 2 * op1.ol; + frag = frag_more (op_length); @@ -586650,7 +590377,7 @@ index 0000000..c2a7b9b + if (op1.ol != 1) + { + as_bad ("Internal error: unexpected CALLA instruction length: %d\n", op1.ol); -+ return 0; ++ break; + } + + bfd_putl16 ((bfd_vma) ZEROS, frag + 2); @@ -586675,21 +590402,21 @@ index 0000000..c2a7b9b + if (*l1 != '#') + { + as_bad (_("expected #n as first argument of %s"), opcode->name); -+ return 0; ++ break; + } + parse_exp (l1 + 1, &(op1.exp)); + if (op1.exp.X_op != O_constant) + { + as_bad (_("expected constant expression for first argument of %s"), + opcode->name); -+ return 0; ++ break; + } + + if ((reg = check_reg (l2)) == -1) + { + as_bad (_("expected register as second argument of %s"), + opcode->name); -+ return 0; ++ break; + } + + op_length = 2; @@ -586707,17 +590434,17 @@ index 0000000..c2a7b9b + if (reg - n + 1 < 0) + { + as_bad (_("Too many registers popped")); -+ return 0; ++ break; + } + -+ /* CPU21 parts cannot use POPM to restore the SR register. */ ++ /* CPU21 errata: cannot use POPM to restore the SR register. */ + if (target_is_430xv2 () + && (reg - n + 1 < 3) + && reg >= 2 + && is_opcode ("popm")) + { + as_bad (_("Cannot use POPM to restore the SR register")); -+ return 0; ++ break; + } + + bin |= (reg - n + 1); @@ -586737,7 +590464,7 @@ index 0000000..c2a7b9b + if (extended & 0xff) + { + as_bad (_("repeat count cannot be used with %s"), opcode->name); -+ return 0; ++ break; + } + + line = extract_operand (line, l1, sizeof (l1)); @@ -586746,34 +590473,34 @@ index 0000000..c2a7b9b + if (*l1 != '#') + { + as_bad (_("expected #n as first argument of %s"), opcode->name); -+ return 0; ++ break; + } + parse_exp (l1 + 1, &(op1.exp)); + if (op1.exp.X_op != O_constant) + { + as_bad (_("expected constant expression for first argument of %s"), + opcode->name); -+ return 0; ++ break; + } + n = op1.exp.X_add_number; + if (n > 4 || n < 1) + { + as_bad (_("expected first argument of %s to be in the range 1-4"), + opcode->name); -+ return 0; ++ break; + } + + if ((reg = check_reg (l2)) == -1) + { + as_bad (_("expected register as second argument of %s"), + opcode->name); -+ return 0; ++ break; + } + + if (target_is_430xv2 () && reg == 0) + { + as_bad (_("%s: attempt to rotate the PC register"), opcode->name); -+ return 0; ++ break; + } + + op_length = 2; @@ -586799,7 +590526,7 @@ index 0000000..c2a7b9b + if (extended & 0xff) + { + as_bad (_("repeat count cannot be used with %s"), opcode->name); -+ return 0; ++ break; + } + + line = extract_operand (line, l1, sizeof (l1)); @@ -586807,13 +590534,13 @@ index 0000000..c2a7b9b + { + as_bad (_("expected register as argument of %s"), + opcode->name); -+ return 0; ++ break; + } + + if (target_is_430xv2 () && reg == 0) + { + as_bad (_("%s: attempt to rotate the PC register"), opcode->name); -+ return 0; ++ break; + } + + if (byte_op) @@ -586858,7 +590585,7 @@ index 0000000..c2a7b9b + if (extended & 0xff) + { + as_bad (_("repeat count cannot be used with %s"), opcode->name); -+ return 0; ++ break; + } + + line = extract_operand (line, l1, sizeof (l1)); @@ -586877,7 +590604,7 @@ index 0000000..c2a7b9b + { + as_bad (_("expected value of first argument of %s to fit into 20-bits"), + opcode->name); -+ return 0; ++ break; + } + + bin |= ((n >> 16) & 0xf) << 8; @@ -586896,7 +590623,7 @@ index 0000000..c2a7b9b + { + as_bad (_("expected register name or constant as first argument of %s"), + opcode->name); -+ return 0; ++ break; + } + + bin |= (n << 8) | (1 << 6); @@ -586907,7 +590634,7 @@ index 0000000..c2a7b9b + { + as_bad (_("expected register as second argument of %s"), + opcode->name); -+ return 0; ++ break; + } + + frag = frag_more (op_length); @@ -586925,7 +590652,7 @@ index 0000000..c2a7b9b + } + + case 9: /* MOVA, BRA, RETA. */ -+ imm_op = 0; ++ imm_op = FALSE; + bin = opcode->bin_opcode; + + if (is_opcode ("reta")) @@ -586970,7 +590697,7 @@ index 0000000..c2a7b9b + & error_message)) == 0) + { + as_bad (error_message, opcode->name); -+ return 0; ++ break; + } + dwarf2_emit_insn (op_length); + break; @@ -586984,13 +590711,13 @@ index 0000000..c2a7b9b + if (op1.exp.X_op != O_constant) + { + as_bad (_("expected constant value as argument to RPT")); -+ return 0; ++ break; + } + if (op1.exp.X_add_number < 1 + || op1.exp.X_add_number > (1 << 4)) + { + as_bad (_("expected constant in the range 2..16")); -+ return 0; ++ break; + } + + /* We silently accept and ignore a repeat count of 1. */ @@ -587011,7 +590738,7 @@ index 0000000..c2a7b9b + else + { + as_bad (_("expected constant or register name as argument to RPT insn")); -+ return 0; ++ break; + } + } + break; @@ -587046,14 +590773,43 @@ index 0000000..c2a7b9b + } + } + ++ bin |= (op2.reg | (op1.reg << 8) | (op1.am << 4) | (op2.am << 7)); ++ ++ if ( (is_opcode ("bic") && bin == 0xc232) ++ || (is_opcode ("bis") && bin == 0xd232) ++ || (is_opcode ("mov") && op2.mode == OP_REG && op2.reg == 2)) ++ { ++ if (check_for_nop) ++ { ++ if (warn_interrupt_nops) ++ { ++ if (gen_interrupt_nops) ++ as_warn (_("NOP inserted between two instructions that change interrupt state")); ++ else ++ as_warn (_("a NOP might be needed here because of successive changes in interrupt state")); ++ } ++ ++ if (gen_interrupt_nops) ++ { ++ /* Emit a NOP between interrupt enable/disable. ++ See 1.3.4.1 of the MSP430x5xx User Guide. */ ++ insn_length += 2; ++ frag = frag_more (2); ++ bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag); ++ } ++ } ++ ++ nop_check_needed = TRUE; ++ } ++ + /* Compute the entire length of the instruction in bytes. */ -+ insn_length = -+ (extended_op ? 2 : 0) /* The extension word. */ ++ op_length = (extended_op ? 2 : 0) /* The extension word. */ + + 2 /* The opcode */ + + (2 * op1.ol) /* The first operand. */ + + (2 * op2.ol); /* The second operand. */ + -+ frag = frag_more (insn_length); ++ insn_length += op_length; ++ frag = frag_more (op_length); + where = frag - frag_now->fr_literal; + + if (extended_op) @@ -587103,7 +590859,6 @@ index 0000000..c2a7b9b + frag += 2; + } + -+ bin |= (op2.reg | (op1.reg << 8) | (op1.am << 4) | (op2.am << 7)); + bfd_putl16 ((bfd_vma) bin, frag); + where += 2; + frag += 2; @@ -587122,7 +590877,7 @@ index 0000000..c2a7b9b + { + if (op1.reg || (op1.reg == 0 && op1.am == 3)) /* Not PC relative. */ + fix_new_exp (frag_now, where, 2, -+ &(op1.exp), FALSE, CHECK_RELOC_MSP430); ++ &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1)); + else + fix_new_exp (frag_now, where, 2, + &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL); @@ -587147,7 +590902,7 @@ index 0000000..c2a7b9b + { + if (op2.reg) /* Not PC relative. */ + fix_new_exp (frag_now, where, 2, -+ &(op2.exp), FALSE, CHECK_RELOC_MSP430); ++ &(op2.exp), FALSE, CHECK_RELOC_MSP430 (op2)); + else + fix_new_exp (frag_now, where, 2, + &(op2.exp), TRUE, CHECK_RELOC_MSP430_PCREL); @@ -587155,20 +590910,6 @@ index 0000000..c2a7b9b + } + } + -+ if (gen_interrupt_nops -+ && ( (is_opcode ("bic") && bin == 0xc232) -+ || (is_opcode ("bis") && bin == 0xd232) -+ || (is_opcode ("mov") && op2.mode == OP_REG && op2.reg == 2))) -+ { -+ /* Emit a NOP following interrupt enable/disable. -+ See 1.3.4.1 of the MSP430x5xx User Guide. */ -+ insn_length += 2; -+ frag = frag_more (2); -+ bfd_putl16 ((bfd_vma) 0x4303 /* NOP */, frag); -+ as_warn (_("a NOP instruction has been inserted after %s"), -+ opcode->name); -+ } -+ + dwarf2_emit_insn (insn_length); + break; + @@ -587198,7 +590939,7 @@ index 0000000..c2a7b9b + || is_opcode ("rrc"))) + { + as_bad (_("%s: attempt to rotate the PC register"), opcode->name); -+ return 0; ++ break; + } + + insn_length = (extended_op ? 2 : 0) + 2 + (op1.ol * 2); @@ -587217,7 +590958,7 @@ index 0000000..c2a7b9b + { + as_bad (_("%s instruction does not accept a .b suffix"), + opcode->name); -+ return 0; ++ break; + } + else if (! addr_op) + extended |= BYTE_OPERATION; @@ -587269,7 +591010,7 @@ index 0000000..c2a7b9b + { + if (op1.reg || (op1.reg == 0 && op1.am == 3)) /* Not PC relative. */ + fix_new_exp (frag_now, where, 2, -+ &(op1.exp), FALSE, CHECK_RELOC_MSP430); ++ &(op1.exp), FALSE, CHECK_RELOC_MSP430 (op1)); + else + fix_new_exp (frag_now, where, 2, + &(op1.exp), TRUE, CHECK_RELOC_MSP430_PCREL); @@ -587463,6 +591204,7 @@ index 0000000..c2a7b9b + } + + input_line_pointer = line; ++ check_for_nop = nop_check_needed; + return 0; +} + @@ -587668,6 +591410,12 @@ index 0000000..c2a7b9b + bfd_putl16 ((bfd_vma) value, where); + break; + ++ case BFD_RELOC_MSP430_ABS_HI16: ++ value >>= 16; ++ value &= 0xffff; /* Get rid of extended sign. */ ++ bfd_putl16 ((bfd_vma) value, where); ++ break; ++ + case BFD_RELOC_32: + bfd_putl16 ((bfd_vma) value, where); + break; @@ -588191,6 +591939,9 @@ index 0000000..c2a7b9b +void +msp430_md_end (void) +{ ++ if (check_for_nop == TRUE && warn_interrupt_nops) ++ as_warn ("assembly finished with the last instruction changing interrupt state - a NOP might be needed"); ++ + bfd_elf_add_proc_attr_int (stdoutput, OFBA_MSPABI_Tag_ISA, + target_is_430x () ? 2 : 1); + @@ -588227,12 +591978,12 @@ index 0000000..c2a7b9b +} diff --git a/gas/config/tc-msp430.h b/gas/config/tc-msp430.h new file mode 100644 -index 0000000..f805f66 +index 0000000..72f6dd8 --- /dev/null +++ b/gas/config/tc-msp430.h -@@ -0,0 +1,168 @@ +@@ -0,0 +1,172 @@ +/* This file is tc-msp430.h -+ Copyright (C) 2002-2013 Free Software Foundation, Inc. ++ Copyright (C) 2002-2014 Free Software Foundation, Inc. + + Contributed by Dmitry Diky + @@ -588353,6 +592104,10 @@ index 0000000..f805f66 + msp430_force_relocation_local (FIX) +extern int msp430_force_relocation_local (struct fix *); + ++/* We need to add reference symbols for .data/.bss. */ ++#define tc_frob_section(sec) msp430_frob_section (sec) ++extern void msp430_frob_section (asection *); ++ +extern int msp430_enable_relax; +extern int msp430_enable_polys; + @@ -588401,12 +592156,12 @@ index 0000000..f805f66 +#define TC_LINKRELAX_FIXUP(seg) (seg->flags & SEC_CODE) diff --git a/gas/config/tc-mt.c b/gas/config/tc-mt.c new file mode 100644 -index 0000000..6e54782 +index 0000000..d832297 --- /dev/null +++ b/gas/config/tc-mt.c @@ -0,0 +1,483 @@ +/* tc-mt.c -- Assembler for the Morpho Technologies mt . -+ Copyright (C) 2005, 2006, 2007, 2010 Free Software Foundation. ++ Copyright (C) 2005-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -588890,12 +592645,12 @@ index 0000000..6e54782 +} diff --git a/gas/config/tc-mt.h b/gas/config/tc-mt.h new file mode 100644 -index 0000000..27c0fa6 +index 0000000..1d3a827 --- /dev/null +++ b/gas/config/tc-mt.h @@ -0,0 +1,70 @@ +/* tc-mt.h -- Header file for tc-mt.c. -+ Copyright (C) 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 2005-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -588966,12 +592721,12 @@ index 0000000..27c0fa6 + diff --git a/gas/config/tc-nds32.c b/gas/config/tc-nds32.c new file mode 100644 -index 0000000..91f8855 +index 0000000..94479ba --- /dev/null +++ b/gas/config/tc-nds32.c @@ -0,0 +1,5920 @@ +/* tc-nds32.c -- Assemble for the nds32 -+ Copyright (C) 2012-2013 Free Software Foundation, Inc. ++ Copyright (C) 2012-2014 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GAS, the GNU Assembler. @@ -594892,12 +598647,12 @@ index 0000000..91f8855 +} diff --git a/gas/config/tc-nds32.h b/gas/config/tc-nds32.h new file mode 100644 -index 0000000..255fbae +index 0000000..731bb87 --- /dev/null +++ b/gas/config/tc-nds32.h @@ -0,0 +1,264 @@ +/* tc-nds32.h -- Header file for tc-nds32.c. -+ Copyright (C) 2012-2013 Free Software Foundation, Inc. ++ Copyright (C) 2012-2014 Free Software Foundation, Inc. + Contributed by Andes Technology Corporation. + + This file is part of GAS. @@ -595162,12 +598917,12 @@ index 0000000..255fbae +#endif /* TC_NDS32 */ diff --git a/gas/config/tc-nios2.c b/gas/config/tc-nios2.c new file mode 100644 -index 0000000..08b7aec +index 0000000..21f4288 --- /dev/null +++ b/gas/config/tc-nios2.c -@@ -0,0 +1,3100 @@ +@@ -0,0 +1,3105 @@ +/* Altera Nios II assembler. -+ Copyright (C) 2012, 2013 Free Software Foundation, Inc. ++ Copyright (C) 2012-2014 Free Software Foundation, Inc. + Contributed by Nigel Gray (ngray@altera.com). + Contributed by Mentor Graphics, Inc. + @@ -596332,6 +600087,11 @@ index 0000000..08b7aec + || fixP->fx_r_type == BFD_RELOC_NIOS2_TLS_LE16 + || fixP->fx_r_type == BFD_RELOC_NIOS2_GOTOFF + || fixP->fx_r_type == BFD_RELOC_NIOS2_TLS_DTPREL ++ || fixP->fx_r_type == BFD_RELOC_NIOS2_CALL26_NOAT ++ || fixP->fx_r_type == BFD_RELOC_NIOS2_GOT_LO ++ || fixP->fx_r_type == BFD_RELOC_NIOS2_GOT_HA ++ || fixP->fx_r_type == BFD_RELOC_NIOS2_CALL_LO ++ || fixP->fx_r_type == BFD_RELOC_NIOS2_CALL_HA + /* Add other relocs here as we generate them. */ + )); + @@ -596468,21 +600228,28 @@ index 0000000..08b7aec + bfd_reloc_code_real_type reloc_type; +}; + ++/* This table is sorted so that prefix strings are listed after the longer ++ strings that include them -- e.g., %got after %got_hiadj, etc. */ ++ +struct nios2_special_relocS nios2_special_reloc[] = { + {"%hiadj", BFD_RELOC_NIOS2_HIADJ16}, + {"%hi", BFD_RELOC_NIOS2_HI16}, + {"%lo", BFD_RELOC_NIOS2_LO16}, + {"%gprel", BFD_RELOC_NIOS2_GPREL}, ++ {"%call_lo", BFD_RELOC_NIOS2_CALL_LO}, ++ {"%call_hiadj", BFD_RELOC_NIOS2_CALL_HA}, + {"%call", BFD_RELOC_NIOS2_CALL16}, + {"%gotoff_lo", BFD_RELOC_NIOS2_GOTOFF_LO}, + {"%gotoff_hiadj", BFD_RELOC_NIOS2_GOTOFF_HA}, ++ {"%gotoff", BFD_RELOC_NIOS2_GOTOFF}, ++ {"%got_hiadj", BFD_RELOC_NIOS2_GOT_HA}, ++ {"%got_lo", BFD_RELOC_NIOS2_GOT_LO}, ++ {"%got", BFD_RELOC_NIOS2_GOT16}, + {"%tls_gd", BFD_RELOC_NIOS2_TLS_GD16}, + {"%tls_ldm", BFD_RELOC_NIOS2_TLS_LDM16}, + {"%tls_ldo", BFD_RELOC_NIOS2_TLS_LDO16}, + {"%tls_ie", BFD_RELOC_NIOS2_TLS_IE16}, + {"%tls_le", BFD_RELOC_NIOS2_TLS_LE16}, -+ {"%gotoff", BFD_RELOC_NIOS2_GOTOFF}, -+ {"%got", BFD_RELOC_NIOS2_GOT16} +}; + +#define NIOS2_NUM_SPECIAL_RELOCS \ @@ -596763,7 +600530,10 @@ index 0000000..08b7aec + unsigned long immed + = nios2_assemble_expression (insn_info->insn_tokens[1], insn_info, + insn_info->insn_reloc, -+ BFD_RELOC_NIOS2_CALL26, 0); ++ (nios2_as_options.noat ++ ? BFD_RELOC_NIOS2_CALL26_NOAT ++ : BFD_RELOC_NIOS2_CALL26), ++ 0); + + SET_INSN_FIELD (IMM26, insn_info->insn_code, immed); + nios2_check_assembly (insn_info->insn_code, insn_info->insn_tokens[2]); @@ -597159,6 +600929,7 @@ index 0000000..08b7aec + as_bad (_("badly formed expression near %s"), argstr); + break; + case 'o': ++ case 'E': + break; + default: + BAD_CASE (*parsestr); @@ -597896,7 +601667,10 @@ index 0000000..08b7aec + && !nios2_as_options.noat + && insn->insn_nios2_opcode->pinfo & NIOS2_INSN_CALL + && insn->insn_reloc -+ && insn->insn_reloc->reloc_type == BFD_RELOC_NIOS2_CALL26) ++ && ((insn->insn_reloc->reloc_type ++ == BFD_RELOC_NIOS2_CALL26) ++ || (insn->insn_reloc->reloc_type ++ == BFD_RELOC_NIOS2_CALL26_NOAT))) + output_call (insn); + else if (insn->insn_nios2_opcode->pinfo & NIOS2_INSN_ANDI) + output_andi (insn); @@ -597985,7 +601759,12 @@ index 0000000..08b7aec + || fixp->fx_r_type == BFD_RELOC_NIOS2_TLS_DTPMOD + || fixp->fx_r_type == BFD_RELOC_NIOS2_TLS_DTPREL + || fixp->fx_r_type == BFD_RELOC_NIOS2_TLS_TPREL -+ || fixp->fx_r_type == BFD_RELOC_NIOS2_GOTOFF) ++ || fixp->fx_r_type == BFD_RELOC_NIOS2_GOTOFF ++ || fixp->fx_r_type == BFD_RELOC_NIOS2_GOT_LO ++ || fixp->fx_r_type == BFD_RELOC_NIOS2_GOT_HA ++ || fixp->fx_r_type == BFD_RELOC_NIOS2_CALL_LO ++ || fixp->fx_r_type == BFD_RELOC_NIOS2_CALL_HA ++ ) + return 0; + + return 1; @@ -598148,12 +601927,10 @@ index 0000000..08b7aec +} + +/* Implement TC_PARSE_CONS_EXPRESSION to handle %tls_ldo(...) */ -+static int nios2_tls_ldo_reloc; -+ -+void ++bfd_reloc_code_real_type +nios2_cons (expressionS *exp, int size) +{ -+ nios2_tls_ldo_reloc = 0; ++ bfd_reloc_code_real_type nios2_tls_ldo_reloc = BFD_RELOC_NONE; + + SKIP_WHITESPACE (); + if (input_line_pointer[0] == '%') @@ -598166,10 +601943,10 @@ index 0000000..08b7aec + else + { + input_line_pointer += 8; -+ nios2_tls_ldo_reloc = 1; ++ nios2_tls_ldo_reloc = BFD_RELOC_NIOS2_TLS_DTPREL; + } + } -+ if (nios2_tls_ldo_reloc) ++ if (nios2_tls_ldo_reloc != BFD_RELOC_NONE) + { + SKIP_WHITESPACE (); + if (input_line_pointer[0] != '(') @@ -598211,26 +601988,9 @@ index 0000000..08b7aec + } + } + } -+ if (!nios2_tls_ldo_reloc) ++ if (nios2_tls_ldo_reloc == BFD_RELOC_NONE) + expression (exp); -+} -+ -+/* Implement TC_CONS_FIX_NEW. */ -+void -+nios2_cons_fix_new (fragS *frag, int where, unsigned int nbytes, -+ expressionS *exp) -+{ -+ bfd_reloc_code_real_type r; -+ -+ r = (nbytes == 1 ? BFD_RELOC_8 -+ : (nbytes == 2 ? BFD_RELOC_16 -+ : (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); -+ -+ if (nios2_tls_ldo_reloc) -+ r = BFD_RELOC_NIOS2_TLS_DTPREL; -+ -+ fix_new_exp (frag, where, (int) nbytes, exp, 0, r); -+ nios2_tls_ldo_reloc = 0; ++ return nios2_tls_ldo_reloc; +} + +/* Implement HANDLE_ALIGN. */ @@ -598268,12 +602028,12 @@ index 0000000..08b7aec +} diff --git a/gas/config/tc-nios2.h b/gas/config/tc-nios2.h new file mode 100644 -index 0000000..9e69194 +index 0000000..82bb624 --- /dev/null +++ b/gas/config/tc-nios2.h -@@ -0,0 +1,125 @@ +@@ -0,0 +1,121 @@ +/* Definitions for Altera Nios II assembler. -+ Copyright (C) 2012, 2013 Free Software Foundation, Inc. ++ Copyright (C) 2012-2014 Free Software Foundation, Inc. + Contributed by Nigel Gray (ngray@altera.com). + Contributed by Mentor Graphics, Inc. + @@ -598381,11 +602141,7 @@ index 0000000..9e69194 +#define CFI_DIFF_EXPR_OK 0 + +#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) nios2_cons (EXP, NBYTES) -+extern void nios2_cons (expressionS *exp, int size); -+ -+#define TC_CONS_FIX_NEW nios2_cons_fix_new -+extern void nios2_cons_fix_new (struct frag *frag, int where, -+ unsigned int nbytes, struct expressionS *exp); ++extern bfd_reloc_code_real_type nios2_cons (expressionS *exp, int size); + +/* We want .cfi_* pseudo-ops for generating unwind info. */ +#define TARGET_USE_CFIPOP 1 @@ -598399,14 +602155,12 @@ index 0000000..9e69194 +#endif /* TC_NIOS2 */ diff --git a/gas/config/tc-ns32k.c b/gas/config/tc-ns32k.c new file mode 100644 -index 0000000..709a9bc +index 0000000..1c97d43 --- /dev/null +++ b/gas/config/tc-ns32k.c -@@ -0,0 +1,2254 @@ +@@ -0,0 +1,2253 @@ +/* ns32k.c -- Assemble on the National Semiconductor 32k series -+ Copyright 1987, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, -+ 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -600588,7 +604342,8 @@ index 0000000..709a9bc +cons_fix_new_ns32k (fragS *frag, /* Which frag? */ + int where, /* Where in that frag? */ + int size, /* 1, 2 or 4 usually. */ -+ expressionS *exp) /* Expression. */ ++ expressionS *exp, /* Expression. */ ++ bfd_reloc_code_real_type r ATTRIBUTE_UNUSED) +{ + fix_new_ns32k_exp (frag, where, size, exp, + 0, 2, 0, 0, 0, 0); @@ -600659,13 +604414,12 @@ index 0000000..709a9bc +} diff --git a/gas/config/tc-ns32k.h b/gas/config/tc-ns32k.h new file mode 100644 -index 0000000..0ee53e5 +index 0000000..02d7196 --- /dev/null +++ b/gas/config/tc-ns32k.h @@ -0,0 +1,123 @@ +/* tc-ns32k.h -- Opcode table for National Semi 32k processor -+ Copyright 1987, 1992, 1993, 1994, 1995, 1997, 2000, 2002, 2005, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -600720,7 +604474,8 @@ index 0000000..0ee53e5 +#define ARG_LEN 50 + +#define TC_CONS_FIX_NEW cons_fix_new_ns32k -+extern void cons_fix_new_ns32k (fragS *, int, int, expressionS *); ++extern void cons_fix_new_ns32k (fragS *, int, int, expressionS *, ++ bfd_reloc_code_real_type); + +/* The NS32x32 has a non 0 nop instruction which should be used in aligns. */ +#define NOP_OPCODE 0xa2 @@ -600786,16 +604541,15 @@ index 0000000..0ee53e5 + fix_bsr (FIX)); \ + } \ + while (0) -diff --git a/gas/config/tc-openrisc.c b/gas/config/tc-openrisc.c +diff --git a/gas/config/tc-or1k.c b/gas/config/tc-or1k.c new file mode 100644 -index 0000000..981cdfb +index 0000000..7b479ca --- /dev/null -+++ b/gas/config/tc-openrisc.c -@@ -0,0 +1,363 @@ -+/* tc-openrisc.c -- Assembler for the OpenRISC family. -+ Copyright 2001, 2002, 2003, 2005, 2006, 2007, 2009 -+ Free Software Foundation. -+ Contributed by Johan Rydberg, jrydberg@opencores.org ++++ b/gas/config/tc-or1k.c +@@ -0,0 +1,362 @@ ++/* tc-or1k.c -- Assembler for the OpenRISC family. ++ Copyright 2001-2014 Free Software Foundation. ++ Contributed for OR32 by Johan Rydberg, jrydberg@opencores.org + + This file is part of GAS, the GNU Assembler. + @@ -600810,26 +604564,25 @@ index 0000000..981cdfb + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License -+ along with GAS; see the file COPYING. If not, write to -+ the Free Software Foundation, 51 Franklin Street - Fifth Floor, -+ Boston, MA 02110-1301, USA. */ -+ ++ along with this program; if not, see */ +#include "as.h" ++#include "safe-ctype.h" +#include "subsegs.h" +#include "symcat.h" -+#include "opcodes/openrisc-desc.h" -+#include "opcodes/openrisc-opc.h" ++#include "opcodes/or1k-desc.h" ++#include "opcodes/or1k-opc.h" +#include "cgen.h" ++#include "elf/or1k.h" ++#include "dw2gencfi.h" + +/* Structure to hold all of the different components describing + an individual instruction. */ -+typedef struct openrisc_insn openrisc_insn; + -+struct openrisc_insn ++typedef struct +{ -+ const CGEN_INSN * insn; -+ const CGEN_INSN * orig_insn; -+ CGEN_FIELDS fields; ++ const CGEN_INSN * insn; ++ const CGEN_INSN * orig_insn; ++ CGEN_FIELDS fields; +#if CGEN_INT_INSN_P + CGEN_INSN_INT buffer [1]; +#define INSN_VALUE(buf) (*(buf)) @@ -600837,13 +604590,13 @@ index 0000000..981cdfb + unsigned char buffer [CGEN_MAX_INSN_SIZE]; +#define INSN_VALUE(buf) (buf) +#endif -+ char * addr; -+ fragS * frag; ++ char * addr; ++ fragS * frag; + int num_fixups; + fixS * fixups [GAS_CGEN_MAX_FIXUPS]; + int indices [MAX_OPERAND_INSTANCES]; -+}; -+ ++} ++or1k_insn; + +const char comment_chars[] = "#"; +const char line_comment_chars[] = "#"; @@ -600851,9 +604604,8 @@ index 0000000..981cdfb +const char EXP_CHARS[] = "eE"; +const char FLT_CHARS[] = "dD"; + -+ -+#define OPENRISC_SHORTOPTS "m:" -+const char * md_shortopts = OPENRISC_SHORTOPTS; ++#define OR1K_SHORTOPTS "m:" ++const char * md_shortopts = OR1K_SHORTOPTS; + +struct option md_longopts[] = +{ @@ -600861,7 +604613,7 @@ index 0000000..981cdfb +}; +size_t md_longopts_size = sizeof (md_longopts); + -+unsigned long openrisc_machine = 0; /* default */ ++unsigned long or1k_machine = 0; /* default */ + +int +md_parse_option (int c ATTRIBUTE_UNUSED, char * arg ATTRIBUTE_UNUSED) @@ -600880,30 +604632,38 @@ index 0000000..981cdfb + discard_rest_of_line (); +} + -+const char openrisc_comment_chars [] = ";#"; ++static bfd_boolean nodelay = FALSE; ++static void ++s_nodelay (int val ATTRIBUTE_UNUSED) ++{ ++ nodelay = TRUE; ++} ++ ++const char or1k_comment_chars [] = ";#"; + +/* The target specific pseudo-ops which we support. */ +const pseudo_typeS md_pseudo_table[] = +{ ++ { "align", s_align_bytes, 0 }, + { "word", cons, 4 }, + { "proc", ignore_pseudo, 0 }, + { "endproc", ignore_pseudo, 0 }, -+ { NULL, NULL, 0 } ++ { "nodelay", s_nodelay, 0 }, ++ { NULL, NULL, 0 } +}; + + -+ +void +md_begin (void) +{ + /* Initialize the `cgen' interface. */ + + /* Set the machine number and endian. */ -+ gas_cgen_cpu_desc = openrisc_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0, ++ gas_cgen_cpu_desc = or1k_cgen_cpu_open (CGEN_CPU_OPEN_MACHS, 0, + CGEN_CPU_OPEN_ENDIAN, + CGEN_ENDIAN_BIG, + CGEN_CPU_OPEN_END); -+ openrisc_cgen_init_asm (gas_cgen_cpu_desc); ++ or1k_cgen_init_asm (gas_cgen_cpu_desc); + + /* This is a callback from cgen to gas to parse operands. */ + cgen_set_parse_operand_fn (gas_cgen_cpu_desc, gas_cgen_parse_operand); @@ -600913,13 +604673,13 @@ index 0000000..981cdfb +md_assemble (char * str) +{ + static int last_insn_had_delay_slot = 0; -+ openrisc_insn insn; ++ or1k_insn insn; + char * errmsg; + + /* Initialize GAS's cgen interface for a new instruction. */ + gas_cgen_init_parse (); + -+ insn.insn = openrisc_cgen_assemble_insn ++ insn.insn = or1k_cgen_assemble_insn + (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg); + + if (!insn.insn) @@ -600930,10 +604690,11 @@ index 0000000..981cdfb + + /* Doesn't really matter what we pass for RELAX_P here. */ + gas_cgen_finish_insn (insn.insn, insn.buffer, -+ CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL); ++ CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL); + + last_insn_had_delay_slot + = CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_DELAY_SLOT); ++ (void) last_insn_had_delay_slot; +} + + @@ -600963,10 +604724,8 @@ index 0000000..981cdfb + return 0; +} + -+ -+/* Interface to relax_segment. */ + -+/* FIXME: Look through this. */ ++/* Interface to relax_segment. */ + +const relax_typeS md_relax_table[] = +{ @@ -600980,71 +604739,14 @@ index 0000000..981cdfb + each list. */ + {1, 1, 0, 0}, + -+ /* The displacement used by GAS is from the end of the 2 byte insn, -+ so we subtract 2 from the following. */ -+ /* 16 bit insn, 8 bit disp -> 10 bit range. -+ This doesn't handle a branch in the right slot at the border: -+ the "& -4" isn't taken into account. It's not important enough to -+ complicate things over it, so we subtract an extra 2 (or + 2 in -ve -+ case). */ -+ {511 - 2 - 2, -512 - 2 + 2, 0, 2 }, -+ /* 32 bit insn, 24 bit disp -> 26 bit range. */ -+ {0x2000000 - 1 - 2, -0x2000000 - 2, 2, 0 }, -+ /* Same thing, but with leading nop for alignment. */ -+ {0x2000000 - 1 - 2, -0x2000000 - 2, 4, 0 } ++ /* The displacement used by GAS is from the end of the 4 byte insn, ++ so we subtract 4 from the following. */ ++ {(((1 << 25) - 1) << 2) - 4, -(1 << 25) - 4, 0, 0}, +}; + -+/* Return an initial guess of the length by which a fragment must grow to -+ hold a branch to reach its destination. -+ Also updates fr_type/fr_subtype as necessary. -+ -+ Called just before doing relaxation. -+ Any symbol that is now undefined will not become defined. -+ The guess for fr_var is ACTUALLY the growth beyond fr_fix. -+ Whatever we do to grow fr_fix or fr_var contributes to our returned value. -+ Although it may not be explicit in the frag, pretend fr_var starts with a -+ 0 value. */ -+ +int -+md_estimate_size_before_relax (fragS * fragP, segT segment) ++md_estimate_size_before_relax (fragS * fragP, segT segment ATTRIBUTE_UNUSED) +{ -+ /* The only thing we have to handle here are symbols outside of the -+ current segment. They may be undefined or in a different segment in -+ which case linker scripts may place them anywhere. -+ However, we can't finish the fragment here and emit the reloc as insn -+ alignment requirements may move the insn about. */ -+ -+ if (S_GET_SEGMENT (fragP->fr_symbol) != segment) -+ { -+ /* The symbol is undefined in this segment. -+ Change the relaxation subtype to the max allowable and leave -+ all further handling to md_convert_frag. */ -+ fragP->fr_subtype = 2; -+ -+ { -+ const CGEN_INSN * insn; -+ int i; -+ -+ /* Update the recorded insn. -+ Fortunately we don't have to look very far. -+ FIXME: Change this to record in the instruction the next higher -+ relaxable insn to use. */ -+ for (i = 0, insn = fragP->fr_cgen.insn; i < 4; i++, insn++) -+ { -+ if ((strcmp (CGEN_INSN_MNEMONIC (insn), -+ CGEN_INSN_MNEMONIC (fragP->fr_cgen.insn)) -+ == 0) -+ && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED)) -+ break; -+ } -+ if (i == 4) -+ abort (); -+ -+ fragP->fr_cgen.insn = insn; -+ return 2; -+ } -+ } -+ + return md_relax_table[fragP->fr_subtype].rlx_length; +} + @@ -601057,13 +604759,13 @@ index 0000000..981cdfb + +void +md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, -+ segT sec ATTRIBUTE_UNUSED, -+ fragS * fragP ATTRIBUTE_UNUSED) ++ segT sec ATTRIBUTE_UNUSED, ++ fragS * fragP ATTRIBUTE_UNUSED) +{ + /* FIXME */ +} + -+ ++ +/* Functions concerning relocs. */ + +/* The location from which a PC relative jump should be calculated, @@ -601074,12 +604776,16 @@ index 0000000..981cdfb +{ + if (fixP->fx_addsy != (symbolS *) NULL + && (! S_IS_DEFINED (fixP->fx_addsy) -+ || S_GET_SEGMENT (fixP->fx_addsy) != sec)) -+ /* The symbol is undefined (or is defined but not in this section). -+ Let the linker figure it out. */ -+ return 0; ++ || (S_GET_SEGMENT (fixP->fx_addsy) != sec) ++ || S_IS_EXTERNAL (fixP->fx_addsy) ++ || S_IS_WEAK (fixP->fx_addsy))) ++ { ++ /* The symbol is undefined (or is defined but not in this section). ++ Let the linker figure it out. */ ++ return 0; ++ } + -+ return (fixP->fx_frag->fr_address + fixP->fx_where) & ~1; ++ return fixP->fx_frag->fr_address + fixP->fx_where; +} + + @@ -601089,40 +604795,23 @@ index 0000000..981cdfb + +bfd_reloc_code_real_type +md_cgen_lookup_reloc (const CGEN_INSN * insn ATTRIBUTE_UNUSED, -+ const CGEN_OPERAND * operand, -+ fixS * fixP) ++ const CGEN_OPERAND * operand, ++ fixS * fixP) +{ -+ bfd_reloc_code_real_type type; ++ if (fixP->fx_cgen.opinfo) ++ return fixP->fx_cgen.opinfo; + + switch (operand->type) + { -+ case OPENRISC_OPERAND_ABS_26: -+ fixP->fx_pcrel = 0; -+ type = BFD_RELOC_OPENRISC_ABS_26; -+ goto emit; -+ case OPENRISC_OPERAND_DISP_26: ++ case OR1K_OPERAND_DISP26: + fixP->fx_pcrel = 1; -+ type = BFD_RELOC_OPENRISC_REL_26; -+ goto emit; ++ return BFD_RELOC_OR1K_REL_26; + -+ case OPENRISC_OPERAND_HI16: -+ type = BFD_RELOC_HI16; -+ goto emit; -+ -+ case OPENRISC_OPERAND_LO16: -+ type = BFD_RELOC_LO16; -+ goto emit; -+ -+ emit: -+ return type; -+ -+ default : /* avoid -Wall warning */ -+ break; ++ default: /* avoid -Wall warning */ ++ return BFD_RELOC_NONE; + } -+ -+ return BFD_RELOC_NONE; +} -+ ++ +/* Write a value out to the object file, using the appropriate endianness. */ + +void @@ -601133,10 +604822,9 @@ index 0000000..981cdfb + +/* Turn a string in input_line_pointer into a floating point constant of type + type, and store the appropriate bytes in *litP. The number of LITTLENUMS -+ emitted is stored in *sizeP . An error message is returned, or NULL on OK. -+*/ ++ emitted is stored in *sizeP . An error message is returned, or NULL on OK. */ + -+/* Equal to MAX_PRECISION in atof-ieee.c */ ++/* Equal to MAX_PRECISION in atof-ieee.c. */ +#define MAX_LITTLENUMS 6 + +char * @@ -601146,23 +604834,89 @@ index 0000000..981cdfb +} + +bfd_boolean -+openrisc_fix_adjustable (fixS * fixP) ++or1k_fix_adjustable (fixS * fixP) +{ + /* We need the symbol name for the VTABLE entries. */ + if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT + || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) -+ return 0; ++ return FALSE; + -+ return 1; ++ return TRUE; +} -diff --git a/gas/config/tc-openrisc.h b/gas/config/tc-openrisc.h ++ ++#define GOT_NAME "_GLOBAL_OFFSET_TABLE_" ++ ++arelent * ++tc_gen_reloc (asection *sec, fixS *fx) ++{ ++ bfd_reloc_code_real_type code = fx->fx_r_type; ++ ++ if (fx->fx_addsy != NULL ++ && strcmp (S_GET_NAME (fx->fx_addsy), GOT_NAME) == 0 ++ && (code == BFD_RELOC_OR1K_GOTPC_HI16 ++ || code == BFD_RELOC_OR1K_GOTPC_LO16)) ++ { ++ arelent * reloc; ++ ++ reloc = xmalloc (sizeof (* reloc)); ++ reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); ++ *reloc->sym_ptr_ptr = symbol_get_bfdsym (fx->fx_addsy); ++ reloc->address = fx->fx_frag->fr_address + fx->fx_where; ++ reloc->howto = bfd_reloc_type_lookup (stdoutput, fx->fx_r_type); ++ reloc->addend = fx->fx_offset; ++ return reloc; ++ } ++ ++ return gas_cgen_tc_gen_reloc (sec, fx); ++} ++ ++void ++or1k_apply_fix (struct fix *f, valueT *t, segT s) ++{ ++ gas_cgen_md_apply_fix (f, t, s); ++ ++ switch (f->fx_r_type) ++ { ++ case BFD_RELOC_OR1K_TLS_GD_HI16: ++ case BFD_RELOC_OR1K_TLS_GD_LO16: ++ case BFD_RELOC_OR1K_TLS_LDM_HI16: ++ case BFD_RELOC_OR1K_TLS_LDM_LO16: ++ case BFD_RELOC_OR1K_TLS_LDO_HI16: ++ case BFD_RELOC_OR1K_TLS_LDO_LO16: ++ case BFD_RELOC_OR1K_TLS_IE_HI16: ++ case BFD_RELOC_OR1K_TLS_IE_LO16: ++ case BFD_RELOC_OR1K_TLS_LE_HI16: ++ case BFD_RELOC_OR1K_TLS_LE_LO16: ++ S_SET_THREAD_LOCAL (f->fx_addsy); ++ break; ++ default: ++ break; ++ } ++} ++ ++void ++or1k_elf_final_processing (void) ++{ ++ if (nodelay) ++ elf_elfheader (stdoutput)->e_flags |= EF_OR1K_NODELAY; ++} ++ ++/* Standard calling conventions leave the CFA at SP on entry. */ ++ ++void ++or1k_cfi_frame_initial_instructions (void) ++{ ++ cfi_add_CFA_def_cfa_register (1); ++} ++ +diff --git a/gas/config/tc-or1k.h b/gas/config/tc-or1k.h new file mode 100644 -index 0000000..c1b0ea1 +index 0000000..18e22a5 --- /dev/null -+++ b/gas/config/tc-openrisc.h -@@ -0,0 +1,61 @@ -+/* tc-openrisc.h -- Header file for tc-openrisc.c. -+ Copyright 2001, 2002, 2003, 2005, 2007 Free Software Foundation, Inc. ++++ b/gas/config/tc-or1k.h +@@ -0,0 +1,79 @@ ++/* tc-or1k.h -- Header file for tc-or1k.c. ++ Copyright 2001-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -601177,30 +604931,28 @@ index 0000000..c1b0ea1 + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License -+ along with GAS; see the file COPYING. If not, write to -+ the Free Software Foundation, 51 Franklin Street - Fifth Floor, -+ Boston, MA 02110-1301, USA. */ ++ along with this program; if not, see */ + -+#define TC_OPENRISC ++#define TC_OR1K + -+#define LISTING_HEADER "OpenRISC GAS " ++#define LISTING_HEADER "Or1k GAS " + +/* The target BFD architecture. */ -+#define TARGET_ARCH bfd_arch_openrisc ++#define TARGET_ARCH bfd_arch_or1k + -+extern unsigned long openrisc_machine; -+#define TARGET_MACH (openrisc_machine) ++extern unsigned long or1k_machine; ++#define TARGET_MACH (or1k_machine) + -+#define TARGET_FORMAT "elf32-openrisc" -+#define TARGET_BYTES_BIG_ENDIAN 1 ++#define TARGET_FORMAT "elf32-or1k" ++#define TARGET_BYTES_BIG_ENDIAN 1 + -+extern const char openrisc_comment_chars []; -+#define tc_comment_chars openrisc_comment_chars ++extern const char or1k_comment_chars []; ++#define tc_comment_chars or1k_comment_chars + +/* Permit temporary numeric labels. */ -+#define LOCAL_LABELS_FB 1 ++#define LOCAL_LABELS_FB 1 + -+#define DIFF_EXPR_OK 1 /* .-foo gets turned into PC relative relocs */ ++#define DIFF_EXPR_OK 1 /* .-foo gets turned into PC relative relocs. */ + +/* We don't need to handle .word strangely. */ +#define WORKING_DOT_WORD @@ -601208,12 +604960,11 @@ index 0000000..c1b0ea1 +/* Values passed to md_apply_fix don't include the symbol value. */ +#define MD_APPLY_SYM_VALUE(FIX) 0 + -+#define md_apply_fix gas_cgen_md_apply_fix ++#define md_apply_fix or1k_apply_fix ++extern void or1k_apply_fix (struct fix *, valueT *, segT); + -+extern bfd_boolean openrisc_fix_adjustable (struct fix *); -+#define tc_fix_adjustable(FIX) openrisc_fix_adjustable (FIX) -+ -+#define tc_gen_reloc gas_cgen_tc_gen_reloc ++extern bfd_boolean or1k_fix_adjustable (struct fix *); ++#define tc_fix_adjustable(FIX) or1k_fix_adjustable (FIX) + +/* Call md_pcrel_from_section(), not md_pcrel_from(). */ +extern long md_pcrel_from_section (struct fix *, segT); @@ -601222,1050 +604973,35 @@ index 0000000..c1b0ea1 +/* For 8 vs 16 vs 32 bit branch selection. */ +extern const struct relax_type md_relax_table[]; +#define TC_GENERIC_RELAX_TABLE md_relax_table -diff --git a/gas/config/tc-or32.c b/gas/config/tc-or32.c -new file mode 100644 -index 0000000..23e44af ---- /dev/null -+++ b/gas/config/tc-or32.c -@@ -0,0 +1,967 @@ -+/* Assembly backend for the OpenRISC 1000. -+ Copyright (C) 2002, 2003, 2005, 2007, 2009, 2010, 2012 -+ Free Software Foundation, Inc. -+ Contributed by Damjan Lampret . -+ Modified bu Johan Rydberg, . -+ Based upon a29k port. + -+ This file is part of GAS, the GNU Assembler. ++#define GAS_CGEN_PCREL_R_TYPE(r_type) gas_cgen_pcrel_r_type(r_type) + -+ GAS is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. ++#define elf_tc_final_processing or1k_elf_final_processing ++void or1k_elf_final_processing (void); + -+ GAS is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. ++/* Enable cfi directives. */ ++#define TARGET_USE_CFIPOP 1 + -+ You should have received a copy of the GNU General Public License -+ along with GAS; see the file COPYING. If not, write to -+ the Free Software Foundation, 51 Franklin Street - Fifth Floor, -+ Boston, MA 02110-1301, USA. */ ++/* Stack grows to lower addresses and wants 4 byte boundary. */ ++#define DWARF2_CIE_DATA_ALIGNMENT -4 + -+/* tc-a29k.c used as a template. */ ++/* Define the column that represents the PC. */ ++#define DWARF2_DEFAULT_RETURN_COLUMN 9 + -+#include "as.h" -+#include "safe-ctype.h" -+#include "opcode/or32.h" -+#include "elf/or32.h" ++/* or1k instructions are 4 bytes long. */ ++#define DWARF2_LINE_MIN_INSN_LENGTH 4 + -+#define DEBUG 0 -+ -+#ifndef REGISTER_PREFIX -+#define REGISTER_PREFIX '%' -+#endif -+ -+/* Make it easier to clone this machine desc into another one. */ -+#define machine_opcode or32_opcode -+#define machine_opcodes or32_opcodes -+#define machine_ip or32_ip -+#define machine_it or32_it -+ -+/* Handle of the OPCODE hash table. */ -+static struct hash_control *op_hash = NULL; -+ -+struct machine_it -+{ -+ char * error; -+ unsigned long opcode; -+ struct nlist * nlistp; -+ expressionS exp; -+ int pcrel; -+ int reloc_offset; /* Offset of reloc within insn. */ -+ int reloc; -+} -+the_insn; -+ -+const pseudo_typeS md_pseudo_table[] = -+{ -+ {"align", s_align_bytes, 4 }, -+ {"space", s_space, 0 }, -+ {"cputype", s_ignore, 0 }, -+ {"reg", s_lsym, 0 }, /* Register equate, same as equ. */ -+ {"sect", s_ignore, 0 }, /* Creation of coff sections. */ -+ {"proc", s_ignore, 0 }, /* Start of a function. */ -+ {"endproc", s_ignore, 0 }, /* Function end. */ -+ {"word", cons, 4 }, -+ {NULL, 0, 0 }, -+}; -+ -+int md_short_jump_size = 4; -+int md_long_jump_size = 4; -+ -+/* This array holds the chars that always start a comment. -+ If the pre-processor is disabled, these aren't very useful. */ -+const char comment_chars[] = "#"; -+ -+/* This array holds the chars that only start a comment at the beginning of -+ a line. If the line seems to have the form '# 123 filename' -+ .line and .file directives will appear in the pre-processed output. */ -+/* Note that input_file.c hand checks for '#' at the beginning of the -+ first line of the input file. This is because the compiler outputs -+ #NO_APP at the beginning of its output. */ -+/* Also note that comments like this one will always work. */ -+const char line_comment_chars[] = "#"; -+ -+/* We needed an unused char for line separation to work around the -+ lack of macros, using sed and such. */ -+const char line_separator_chars[] = ";"; -+ -+/* Chars that can be used to separate mant from exp in floating point nums. */ -+const char EXP_CHARS[] = "eE"; -+ -+/* Chars that mean this number is a floating point constant. -+ As in 0f12.456 -+ or 0d1.2345e12. */ -+const char FLT_CHARS[] = "rRsSfFdDxXpP"; -+ -+/* "l.jalr r9" precalculated opcode. */ -+static unsigned long jalr_r9_opcode; -+ -+static void machine_ip (char *); -+ -+ -+/* Set bits in machine opcode according to insn->encoding -+ description and passed operand. */ -+ -+static void -+encode (const struct machine_opcode *insn, -+ unsigned long *opcode, -+ signed long param_val, -+ char param_ch) -+{ -+ int opc_pos = 0; -+ int param_pos = 0; -+ char *enc; -+ -+#if DEBUG -+ printf (" encode: opcode=%.8lx param_val=%.8lx abs=%.8lx param_ch=%c\n", -+ *opcode, param_val, abs (param_val), param_ch); -+#endif -+ for (enc = insn->encoding; *enc != '\0'; enc++) -+ if (*enc == param_ch) -+ { -+ if (enc - 2 >= insn->encoding && (*(enc - 2) == '0') && (*(enc - 1) == 'x')) -+ continue; -+ else -+ param_pos ++; -+ } -+ -+ opc_pos = 32; -+ -+ for (enc = insn->encoding; *enc != '\0';) -+ { -+ if ((*enc == '0') && (*(enc + 1) == 'x')) -+ { -+ int tmp = strtol (enc, NULL, 16); -+ -+ opc_pos -= 4; -+ *opcode |= tmp << opc_pos; -+ enc += 3; -+ } -+ else if ((*enc == '0') || (*enc == '-')) -+ { -+ opc_pos--; -+ enc++; -+ } -+ else if (*enc == '1') -+ { -+ opc_pos--; -+ *opcode |= 1 << opc_pos; -+ enc++; -+ } -+ else if (*enc == param_ch) -+ { -+ opc_pos--; -+ param_pos--; -+ *opcode |= ((param_val >> param_pos) & 0x1) << opc_pos; -+ enc++; -+ } -+ else if (ISALPHA (*enc)) -+ { -+ opc_pos--; -+ enc++; -+ } -+ else -+ enc++; -+ } -+ -+#if DEBUG -+ printf (" opcode=%.8lx\n", *opcode); -+#endif -+} -+ -+/* This function is called once, at assembler startup time. It should -+ set up all the tables, etc., that the MD part of the assembler will -+ need. */ -+ -+void -+md_begin (void) -+{ -+ const char *retval = NULL; -+ int lose = 0; -+ int skipnext = 0; -+ unsigned int i; -+ -+ /* Hash up all the opcodes for fast use later. */ -+ op_hash = hash_new (); -+ -+ for (i = 0; i < or32_num_opcodes; i++) -+ { -+ const char *name = machine_opcodes[i].name; -+ -+ if (skipnext) -+ { -+ skipnext = 0; -+ continue; -+ } -+ -+ retval = hash_insert (op_hash, name, (void *) &machine_opcodes[i]); -+ if (retval != NULL) -+ { -+ fprintf (stderr, "internal error: can't hash `%s': %s\n", -+ machine_opcodes[i].name, retval); -+ lose = 1; -+ } -+ } -+ -+ if (lose) -+ as_fatal (_("Broken assembler. No assembly attempted.")); -+ -+ encode (&machine_opcodes[insn_index ("l.jalr")], &jalr_r9_opcode, 9, 'B'); -+} -+ -+/* Returns non zero if instruction is to be used. */ -+ -+static int -+check_invalid_opcode (unsigned long opcode) -+{ -+ return opcode == jalr_r9_opcode; -+} -+ -+/* Assemble a single instruction. Its label has already been handled -+ by the generic front end. We just parse opcode and operands, and -+ produce the bytes of data and relocation. */ -+ -+void -+md_assemble (char *str) -+{ -+ char *toP; -+ -+#if DEBUG -+ printf ("NEW INSTRUCTION\n"); -+#endif -+ -+ know (str); -+ machine_ip (str); -+ toP = frag_more (4); -+ -+ /* Put out the opcode. */ -+ md_number_to_chars (toP, the_insn.opcode, 4); -+ -+ /* Put out the symbol-dependent stuff. */ -+ if (the_insn.reloc != BFD_RELOC_NONE) -+ { -+ fix_new_exp (frag_now, -+ (toP - frag_now->fr_literal + the_insn.reloc_offset), -+ 4, /* size */ -+ &the_insn.exp, -+ the_insn.pcrel, -+ the_insn.reloc); -+ } -+} -+ -+/* This is true of the we have issued a "lo(" or "hi"(. */ -+static int waiting_for_shift = 0; -+ -+static int mask_or_shift = 0; -+ -+static char * -+parse_operand (char *s, expressionS *operandp, int opt) -+{ -+ char *save = input_line_pointer; -+ char *new_pointer; -+ -+#if DEBUG -+ printf (" PROCESS NEW OPERAND(%s) == %c (%d)\n", s, opt ? opt : '!', opt); -+#endif -+ -+ input_line_pointer = s; -+ -+ if (strncasecmp (s, "HI(", 3) == 0) -+ { -+ waiting_for_shift = 1; -+ mask_or_shift = BFD_RELOC_HI16; -+ -+ input_line_pointer += 3; -+ } -+ else if (strncasecmp (s, "LO(", 3) == 0) -+ { -+ mask_or_shift = BFD_RELOC_LO16; -+ -+ input_line_pointer += 3; -+ } -+ else -+ mask_or_shift = 0; -+ -+ if ((*s == '(') && (*(s+1) == 'r')) -+ s++; -+ -+ if ((*s == 'r') && ISDIGIT (*(s + 1))) -+ { -+ operandp->X_add_number = strtol (s + 1, NULL, 10); -+ operandp->X_op = O_register; -+ for (; (*s != ',') && (*s != '\0');) -+ s++; -+ input_line_pointer = save; -+ return s; -+ } -+ -+ expression (operandp); -+ -+ if (operandp->X_op == O_absent) -+ { -+ if (! opt) -+ as_bad (_("missing operand")); -+ else -+ { -+ operandp->X_add_number = 0; -+ operandp->X_op = O_constant; -+ } -+ } -+ -+ new_pointer = input_line_pointer; -+ input_line_pointer = save; -+ -+#if DEBUG -+ printf (" %s=parse_operand(%s): operandp->X_op = %u\n", new_pointer, s, -+ operandp->X_op); -+#endif -+ -+ return new_pointer; -+} -+ -+/* Instruction parsing. Takes a string containing the opcode. -+ Operands are at input_line_pointer. Output is in the_insn. -+ Warnings or errors are generated. */ -+ -+static void -+machine_ip (char *str) -+{ -+ char *s; -+ const char *args; -+ const struct machine_opcode *insn; -+ unsigned long opcode; -+ expressionS the_operand; -+ expressionS *operand = &the_operand; -+ unsigned int regno; -+ int reloc = BFD_RELOC_NONE; -+ -+#if DEBUG -+ printf ("machine_ip(%s)\n", str); -+#endif -+ -+ s = str; -+ for (; ISALNUM (*s) || *s == '.'; ++s) -+ if (ISUPPER (*s)) -+ *s = TOLOWER (*s); -+ -+ switch (*s) -+ { -+ case '\0': -+ break; -+ -+ case ' ': /* FIXME-SOMEDAY more whitespace. */ -+ *s++ = '\0'; -+ break; -+ -+ default: -+ as_bad (_("unknown opcode1: `%s'"), str); -+ return; -+ } -+ -+ if ((insn = (struct machine_opcode *) hash_find (op_hash, str)) == NULL) -+ { -+ as_bad (_("unknown opcode2 `%s'."), str); -+ return; -+ } -+ -+ opcode = 0; -+ memset (&the_insn, '\0', sizeof (the_insn)); -+ the_insn.reloc = BFD_RELOC_NONE; -+ -+ reloc = BFD_RELOC_NONE; -+ -+ /* Build the opcode, checking as we go to make sure that the -+ operands match. -+ -+ If an operand matches, we modify the_insn or opcode appropriately, -+ and do a "continue". If an operand fails to match, we "break". */ -+ if (insn->args[0] != '\0') -+ /* Prime the pump. */ -+ s = parse_operand (s, operand, insn->args[0] == 'I'); -+ -+ for (args = insn->args;; ++args) -+ { -+#if DEBUG -+ printf (" args = %s\n", args); -+#endif -+ switch (*args) -+ { -+ case '\0': /* End of args. */ -+ /* We have have 0 args, do the bazoooka! */ -+ if (args == insn->args) -+ encode (insn, &opcode, 0, 0); -+ -+ if (*s == '\0') -+ { -+ /* We are truly done. */ -+ the_insn.opcode = opcode; -+ if (check_invalid_opcode (opcode)) -+ as_bad (_("instruction not allowed: %s"), str); -+ return; -+ } -+ as_bad (_("too many operands: %s"), s); -+ break; -+ -+ case ',': /* Must match a comma. */ -+ if (*s++ == ',') -+ { -+ reloc = BFD_RELOC_NONE; -+ -+ /* Parse next operand. */ -+ s = parse_operand (s, operand, args[1] == 'I'); -+#if DEBUG -+ printf (" ',' case: operand->X_add_number = %d, *args = %s, *s = %s\n", -+ operand->X_add_number, args, s); -+#endif -+ continue; -+ } -+ break; -+ -+ case '(': /* Must match a (. */ -+ s = parse_operand (s, operand, args[1] == 'I'); -+ continue; -+ -+ case ')': /* Must match a ). */ -+ continue; -+ -+ case 'r': /* A general register. */ -+ args++; -+ -+ if (operand->X_op != O_register) -+ break; /* Only registers. */ -+ -+ know (operand->X_add_symbol == 0); -+ know (operand->X_op_symbol == 0); -+ regno = operand->X_add_number; -+ encode (insn, &opcode, regno, *args); -+#if DEBUG -+ printf (" r: operand->X_op = %d\n", operand->X_op); -+#endif -+ continue; -+ -+ default: -+ /* if (! ISALPHA (*args)) -+ break; */ /* Only immediate values. */ -+ -+ if (mask_or_shift) -+ { -+#if DEBUG -+ printf ("mask_or_shift = %d\n", mask_or_shift); -+#endif -+ reloc = mask_or_shift; -+ } -+ mask_or_shift = 0; -+ -+ if (strncasecmp (args, "LO(", 3) == 0) -+ { -+#if DEBUG -+ printf ("reloc_const\n"); -+#endif -+ reloc = BFD_RELOC_LO16; -+ } -+ else if (strncasecmp (args, "HI(", 3) == 0) -+ { -+#if DEBUG -+ printf ("reloc_consth\n"); -+#endif -+ reloc = BFD_RELOC_HI16; -+ } -+ -+ if (*s == '(') -+ operand->X_op = O_constant; -+ else if (*s == ')') -+ s += 1; -+#if DEBUG -+ printf (" default case: operand->X_add_number = %d, *args = %s, *s = %s\n", operand->X_add_number, args, s); -+#endif -+ if (operand->X_op == O_constant) -+ { -+ if (reloc == BFD_RELOC_NONE) -+ { -+ bfd_vma v, mask; -+ -+ mask = 0x3ffffff; -+ v = abs (operand->X_add_number) & ~ mask; -+ if (v) -+ as_bad (_("call/jmp target out of range (1)")); -+ } -+ -+ if (reloc == BFD_RELOC_HI16) -+ operand->X_add_number = ((operand->X_add_number >> 16) & 0xffff); -+ -+ the_insn.pcrel = 0; -+ encode (insn, &opcode, operand->X_add_number, *args); -+ /* the_insn.reloc = BFD_RELOC_NONE; */ -+ continue; -+ } -+ -+ if (reloc == BFD_RELOC_NONE) -+ the_insn.reloc = BFD_RELOC_32_GOT_PCREL; -+ else -+ the_insn.reloc = reloc; -+ -+ /* the_insn.reloc = insn->reloc; */ -+#if DEBUG -+ printf (" reloc sym=%d\n", the_insn.reloc); -+ printf (" BFD_RELOC_NONE=%d\n", BFD_RELOC_NONE); -+#endif -+ the_insn.exp = *operand; -+ -+ /* the_insn.reloc_offset = 1; */ -+ the_insn.pcrel = 1; /* Assume PC-relative jump. */ -+ -+ /* FIXME-SOON, Do we figure out whether abs later, after -+ know sym val? */ -+ if (reloc == BFD_RELOC_LO16 || reloc == BFD_RELOC_HI16) -+ the_insn.pcrel = 0; -+ -+ encode (insn, &opcode, operand->X_add_number, *args); -+ continue; -+ } -+ -+ /* Types or values of args don't match. */ -+ as_bad (_("invalid operands")); -+ return; -+ } -+} -+ -+char * -+md_atof (int type, char * litP, int * sizeP) -+{ -+ return ieee_md_atof (type, litP, sizeP, TRUE); -+} -+ -+/* Write out big-endian. */ -+ -+void -+md_number_to_chars (char *buf, valueT val, int n) -+{ -+ number_to_chars_bigendian (buf, val, n); -+} -+ -+void -+md_apply_fix (fixS * fixP, valueT * val, segT seg ATTRIBUTE_UNUSED) -+{ -+ char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; -+ long t_val; -+ -+ t_val = (long) *val; -+ -+#if DEBUG -+ printf ("md_apply_fix val:%x\n", t_val); -+#endif -+ -+ fixP->fx_addnumber = t_val; /* Remember value for emit_reloc. */ -+ -+ switch (fixP->fx_r_type) -+ { -+ case BFD_RELOC_32: /* XXXXXXXX pattern in a word. */ -+#if DEBUG -+ printf ("reloc_const: val=%x\n", t_val); -+#endif -+ buf[0] = t_val >> 24; -+ buf[1] = t_val >> 16; -+ buf[2] = t_val >> 8; -+ buf[3] = t_val; -+ break; -+ -+ case BFD_RELOC_16: /* XXXX0000 pattern in a word. */ -+#if DEBUG -+ printf ("reloc_const: val=%x\n", t_val); -+#endif -+ buf[0] = t_val >> 8; -+ buf[1] = t_val; -+ break; -+ -+ case BFD_RELOC_8: /* XX000000 pattern in a word. */ -+#if DEBUG -+ printf ("reloc_const: val=%x\n", t_val); -+#endif -+ buf[0] = t_val; -+ break; -+ -+ case BFD_RELOC_LO16: /* 0000XXXX pattern in a word. */ -+#if DEBUG -+ printf ("reloc_const: val=%x\n", t_val); -+#endif -+ buf[2] = t_val >> 8; /* Holds bits 0000XXXX. */ -+ buf[3] = t_val; -+ break; -+ -+ case BFD_RELOC_HI16: /* 0000XXXX pattern in a word. */ -+#if DEBUG -+ printf ("reloc_consth: val=%x\n", t_val); -+#endif -+ buf[2] = t_val >> 24; /* Holds bits XXXX0000. */ -+ buf[3] = t_val >> 16; -+ break; -+ -+ case BFD_RELOC_32_GOT_PCREL: /* 0000XXXX pattern in a word. */ -+ if (!fixP->fx_done) -+ ; -+ else if (fixP->fx_pcrel) -+ { -+ long v = t_val >> 28; -+ -+ if (v != 0 && v != -1) -+ as_bad_where (fixP->fx_file, fixP->fx_line, -+ _("call/jmp target out of range (2)")); -+ } -+ else -+ /* This case was supposed to be handled in machine_ip. */ -+ abort (); -+ -+ buf[0] |= (t_val >> 26) & 0x03; /* Holds bits 0FFFFFFC of address. */ -+ buf[1] = t_val >> 18; -+ buf[2] = t_val >> 10; -+ buf[3] = t_val >> 2; -+ break; -+ -+ case BFD_RELOC_VTABLE_INHERIT: -+ case BFD_RELOC_VTABLE_ENTRY: -+ fixP->fx_done = 0; -+ break; -+ -+ case BFD_RELOC_NONE: -+ default: -+ as_bad (_("bad relocation type: 0x%02x"), fixP->fx_r_type); -+ break; -+ } -+ -+ if (fixP->fx_addsy == (symbolS *) NULL) -+ fixP->fx_done = 1; -+} -+ -+/* Should never be called for or32. */ -+ -+void -+md_create_short_jump (char * ptr ATTRIBUTE_UNUSED, -+ addressT from_addr ATTRIBUTE_UNUSED, -+ addressT to_addr ATTRIBUTE_UNUSED, -+ fragS * frag ATTRIBUTE_UNUSED, -+ symbolS * to_symbol ATTRIBUTE_UNUSED) -+{ -+ as_fatal ("or32_create_short_jmp\n"); -+} -+ -+/* Should never be called for or32. */ -+ -+void -+md_convert_frag (bfd * headers ATTRIBUTE_UNUSED, -+ segT seg ATTRIBUTE_UNUSED, -+ fragS * fragP ATTRIBUTE_UNUSED) -+{ -+ as_fatal ("or32_convert_frag\n"); -+} -+ -+/* Should never be called for or32. */ -+ -+void -+md_create_long_jump (char * ptr ATTRIBUTE_UNUSED, -+ addressT from_addr ATTRIBUTE_UNUSED, -+ addressT to_addr ATTRIBUTE_UNUSED, -+ fragS * frag ATTRIBUTE_UNUSED, -+ symbolS * to_symbol ATTRIBUTE_UNUSED) -+{ -+ as_fatal ("or32_create_long_jump\n"); -+} -+ -+/* Should never be called for or32. */ -+ -+int -+md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED, -+ segT segtype ATTRIBUTE_UNUSED) -+{ -+ as_fatal ("or32_estimate_size_before_relax\n"); -+ return 0; -+} -+ -+/* Translate internal representation of relocation info to target format. -+ -+ On sparc/29k: first 4 bytes are normal unsigned long address, next three -+ bytes are index, most sig. byte first. Byte 7 is broken up with -+ bit 7 as external, bits 6 & 5 unused, and the lower -+ five bits as relocation type. Next 4 bytes are long addend. */ -+/* Thanx and a tip of the hat to Michael Bloom, mb@ttidca.tti.com. */ -+ -+#ifdef OBJ_AOUT -+void -+tc_aout_fix_to_chars (char *where, -+ fixS *fixP, -+ relax_addressT segment_address_in_file) -+{ -+ long r_symbolnum; -+ -+#if DEBUG -+ printf ("tc_aout_fix_to_chars\n"); -+#endif -+ -+ know (fixP->fx_r_type < BFD_RELOC_NONE); -+ know (fixP->fx_addsy != NULL); -+ -+ md_number_to_chars -+ (where, -+ fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file, -+ 4); -+ -+ r_symbolnum = (S_IS_DEFINED (fixP->fx_addsy) -+ ? S_GET_TYPE (fixP->fx_addsy) -+ : fixP->fx_addsy->sy_number); -+ -+ where[4] = (r_symbolnum >> 16) & 0x0ff; -+ where[5] = (r_symbolnum >> 8) & 0x0ff; -+ where[6] = r_symbolnum & 0x0ff; -+ where[7] = (((!S_IS_DEFINED (fixP->fx_addsy)) << 7) & 0x80) | (0 & 0x60) | (fixP->fx_r_type & 0x1F); -+ -+ /* Also easy. */ -+ md_number_to_chars (&where[8], fixP->fx_addnumber, 4); -+} -+ -+#endif /* OBJ_AOUT */ -+ -+const char *md_shortopts = ""; -+ -+struct option md_longopts[] = -+{ -+ { NULL, no_argument, NULL, 0 } -+}; -+size_t md_longopts_size = sizeof (md_longopts); -+ -+int -+md_parse_option (int c ATTRIBUTE_UNUSED, char * arg ATTRIBUTE_UNUSED) -+{ -+ return 0; -+} -+ -+void -+md_show_usage (FILE * stream ATTRIBUTE_UNUSED) -+{ -+} -+ -+/* This is called when a line is unrecognized. This is used to handle -+ definitions of or32 style local labels. */ -+ -+int -+or32_unrecognized_line (int c) -+{ -+ int lab; -+ char *s; -+ -+ if (c != '$' -+ || ! ISDIGIT ((unsigned char) input_line_pointer[0])) -+ return 0; -+ -+ s = input_line_pointer; -+ -+ lab = 0; -+ while (ISDIGIT ((unsigned char) *s)) -+ { -+ lab = lab * 10 + *s - '0'; -+ ++s; -+ } -+ -+ if (*s != ':') -+ /* Not a label definition. */ -+ return 0; -+ -+ if (dollar_label_defined (lab)) -+ { -+ as_bad (_("label \"$%d\" redefined"), lab); -+ return 0; -+ } -+ -+ define_dollar_label (lab); -+ colon (dollar_label_name (lab, 0)); -+ input_line_pointer = s + 1; -+ -+ return 1; -+} -+ -+/* Default the values of symbols known that should be "predefined". We -+ don't bother to predefine them unless you actually use one, since there -+ are a lot of them. */ -+ -+symbolS * -+md_undefined_symbol (char *name ATTRIBUTE_UNUSED) -+{ -+ return NULL; -+} -+ -+/* Parse an operand that is machine-specific. */ -+ -+void -+md_operand (expressionS *expressionP) -+{ -+#if DEBUG -+ printf (" md_operand(input_line_pointer = %s)\n", input_line_pointer); -+#endif -+ -+ if (input_line_pointer[0] == REGISTER_PREFIX && input_line_pointer[1] == 'r') -+ { -+ /* We have a numeric register expression. No biggy. */ -+ input_line_pointer += 2; /* Skip %r */ -+ (void) expression (expressionP); -+ -+ if (expressionP->X_op != O_constant -+ || expressionP->X_add_number > 255) -+ as_bad (_("Invalid expression after %%%%\n")); -+ expressionP->X_op = O_register; -+ } -+ else if (input_line_pointer[0] == '&') -+ { -+ /* We are taking the 'address' of a register...this one is not -+ in the manual, but it *is* in traps/fpsymbol.h! What they -+ seem to want is the register number, as an absolute number. */ -+ input_line_pointer++; /* Skip & */ -+ (void) expression (expressionP); -+ -+ if (expressionP->X_op != O_register) -+ as_bad (_("invalid register in & expression")); -+ else -+ expressionP->X_op = O_constant; -+ } -+ else if (input_line_pointer[0] == '$' -+ && ISDIGIT ((unsigned char) input_line_pointer[1])) -+ { -+ long lab; -+ char *name; -+ symbolS *sym; -+ -+ /* This is a local label. */ -+ ++input_line_pointer; -+ lab = (long) get_absolute_expression (); -+ -+ if (dollar_label_defined (lab)) -+ { -+ name = dollar_label_name (lab, 0); -+ sym = symbol_find (name); -+ } -+ else -+ { -+ name = dollar_label_name (lab, 1); -+ sym = symbol_find_or_make (name); -+ } -+ -+ expressionP->X_op = O_symbol; -+ expressionP->X_add_symbol = sym; -+ expressionP->X_add_number = 0; -+ } -+ else if (input_line_pointer[0] == '$') -+ { -+ char *s; -+ char type; -+ int fieldnum, fieldlimit; -+ LITTLENUM_TYPE floatbuf[8]; -+ -+ /* $float(), $doubleN(), or $extendN() convert floating values -+ to integers. */ -+ s = input_line_pointer; -+ -+ ++s; -+ -+ fieldnum = 0; -+ if (strncmp (s, "double", sizeof "double" - 1) == 0) -+ { -+ s += sizeof "double" - 1; -+ type = 'd'; -+ fieldlimit = 2; -+ } -+ else if (strncmp (s, "float", sizeof "float" - 1) == 0) -+ { -+ s += sizeof "float" - 1; -+ type = 'f'; -+ fieldlimit = 1; -+ } -+ else if (strncmp (s, "extend", sizeof "extend" - 1) == 0) -+ { -+ s += sizeof "extend" - 1; -+ type = 'x'; -+ fieldlimit = 4; -+ } -+ else -+ return; -+ -+ if (ISDIGIT (*s)) -+ { -+ fieldnum = *s - '0'; -+ ++s; -+ } -+ if (fieldnum >= fieldlimit) -+ return; -+ -+ SKIP_WHITESPACE (); -+ if (*s != '(') -+ return; -+ ++s; -+ SKIP_WHITESPACE (); -+ -+ s = atof_ieee (s, type, floatbuf); -+ if (s == NULL) -+ return; -+ s = s; -+ -+ SKIP_WHITESPACE (); -+ if (*s != ')') -+ return; -+ ++s; -+ SKIP_WHITESPACE (); -+ -+ input_line_pointer = s; -+ expressionP->X_op = O_constant; -+ expressionP->X_unsigned = 1; -+ expressionP->X_add_number = ((floatbuf[fieldnum * 2] -+ << LITTLENUM_NUMBER_OF_BITS) -+ + floatbuf[fieldnum * 2 + 1]); -+ } -+} -+ -+/* Round up a section size to the appropriate boundary. */ -+ -+valueT -+md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size ATTRIBUTE_UNUSED) -+{ -+ return size; /* Byte alignment is fine. */ -+} -+ -+/* Exactly what point is a PC-relative offset relative TO? -+ On the 29000, they're relative to the address of the instruction, -+ which we have set up as the address of the fixup too. */ -+ -+long -+md_pcrel_from (fixS *fixP) -+{ -+ return fixP->fx_where + fixP->fx_frag->fr_address; -+} -+ -+/* Generate a reloc for a fixup. */ -+ -+arelent * -+tc_gen_reloc (asection *seg ATTRIBUTE_UNUSED, fixS *fixp) -+{ -+ arelent *reloc; -+ -+ reloc = xmalloc (sizeof (arelent)); -+ reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *)); -+ *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); -+ reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; -+ /* reloc->address = fixp->fx_frag->fr_address + fixp->fx_where + fixp->fx_addnumber;*/ -+ reloc->howto = bfd_reloc_type_lookup (stdoutput, fixp->fx_r_type); -+ -+ if (reloc->howto == (reloc_howto_type *) NULL) -+ { -+ as_bad_where (fixp->fx_file, fixp->fx_line, -+ _("reloc %d not supported by object file format"), -+ (int) fixp->fx_r_type); -+ return NULL; -+ } -+ -+ if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) -+ reloc->address = fixp->fx_offset; -+ -+ reloc->addend = fixp->fx_addnumber; -+ return reloc; -+} -diff --git a/gas/config/tc-or32.h b/gas/config/tc-or32.h -new file mode 100644 -index 0000000..bd0d37f ---- /dev/null -+++ b/gas/config/tc-or32.h -@@ -0,0 +1,56 @@ -+/* tc-or32.h -- Assemble for the OpenRISC 1000. -+ Copyright (C) 2002, 2003. 2005, 2007 Free Software Foundation, Inc. -+ Contributed by Damjan Lampret . -+ Based upon a29k port. -+ -+ This file is part of GAS, the GNU Assembler. -+ -+ GAS is free software; you can redistribute it and/or modify -+ it under the terms of the GNU General Public License as published by -+ the Free Software Foundation; either version 3, or (at your option) -+ any later version. -+ -+ GAS is distributed in the hope that it will be useful, -+ but WITHOUT ANY WARRANTY; without even the implied warranty of -+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ GNU General Public License for more details. -+ -+ You should have received a copy of the GNU General Public License -+ along with GAS; see the file COPYING. If not, write to -+ the Free Software Foundation, 51 Franklin Street - Fifth Floor, -+ Boston, MA 02110-1301, USA. */ -+ -+#define TC_OR32 -+ -+#define TARGET_BYTES_BIG_ENDIAN 1 -+ -+#define LEX_DOLLAR 1 -+ -+#ifdef OBJ_ELF -+#define TARGET_FORMAT "elf32-or32" -+#define TARGET_ARCH bfd_arch_or32 -+#endif -+ -+#ifdef OBJ_COFF -+#define TARGET_FORMAT "coff-or32-big" -+#define reloc_type int -+#endif -+ -+#define tc_unrecognized_line(c) or32_unrecognized_line (c) -+ -+extern int or32_unrecognized_line (int); -+ -+#define tc_coff_symbol_emit_hook(a) ; /* Not used. */ -+ -+#define COFF_MAGIC SIPFBOMAGIC -+ -+/* No shared lib support, so we don't need to ensure externally -+ visible symbols can be overridden. */ -+#define EXTERN_FORCE_RELOC 0 -+ -+#ifdef OBJ_ELF -+/* Values passed to md_apply_fix don't include the symbol value. */ -+#define MD_APPLY_SYM_VALUE(FIX) 0 -+#endif -+ -+#define ZERO_BASED_SEGMENTS ++#define tc_cfi_frame_initial_instructions \ ++ or1k_cfi_frame_initial_instructions ++extern void or1k_cfi_frame_initial_instructions (void); diff --git a/gas/config/tc-pdp11.c b/gas/config/tc-pdp11.c new file mode 100644 -index 0000000..98e241f +index 0000000..1b3df58 --- /dev/null +++ b/gas/config/tc-pdp11.c -@@ -0,0 +1,1454 @@ +@@ -0,0 +1,1453 @@ +/* tc-pdp11.c - pdp11-specific - -+ Copyright 2001, 2002, 2004, 2005, 2007, 2009 -+ Free Software Foundation, Inc. ++ Copyright (C) 2001-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -603719,12 +606455,12 @@ index 0000000..98e241f +} diff --git a/gas/config/tc-pdp11.h b/gas/config/tc-pdp11.h new file mode 100644 -index 0000000..31a690e +index 0000000..af71667 --- /dev/null +++ b/gas/config/tc-pdp11.h @@ -0,0 +1,33 @@ +/* tc-pdp11.h -- Header file for tc-pdp11.c. -+ Copyright 2001, 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 2001-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -603758,13 +606494,12 @@ index 0000000..31a690e +/* end of tc-pdp11.h */ diff --git a/gas/config/tc-pj.c b/gas/config/tc-pj.c new file mode 100644 -index 0000000..9dbe810 +index 0000000..dba4cbc --- /dev/null +++ b/gas/config/tc-pj.c @@ -0,0 +1,495 @@ +/* tc-pj.c -- Assemble code for Pico Java -+ Copyright 1999, 2000, 2001, 2002, 2003, 2005, 2007, 2009, 2010 -+ Free Software Foundation, Inc. ++ Copyright (C) 1999-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -603861,7 +606596,8 @@ index 0000000..9dbe810 + we want to handle magic pending reloc expressions specially. */ + +void -+pj_cons_fix_new_pj (fragS *frag, int where, int nbytes, expressionS *exp) ++pj_cons_fix_new_pj (fragS *frag, int where, int nbytes, expressionS *exp, ++ bfd_reloc_code_real_type r ATTRIBUTE_UNUSED) +{ + static int rv[5][2] = + { { 0, 0 }, @@ -604259,12 +606995,12 @@ index 0000000..9dbe810 +} diff --git a/gas/config/tc-pj.h b/gas/config/tc-pj.h new file mode 100644 -index 0000000..bec85a2 +index 0000000..eda1792 --- /dev/null +++ b/gas/config/tc-pj.h -@@ -0,0 +1,60 @@ +@@ -0,0 +1,61 @@ +/* This file is tc-pj.h -+ Copyright 1999, 2000, 2001, 2002, 2003, 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 1999-2014 Free Software Foundation, Inc. + + Contributed by Steve Chamberlain of Transmeta, sac@pobox.com + @@ -604296,7 +607032,8 @@ index 0000000..bec85a2 + ? "Pico Java GAS Big Endian" \ + : "Pico Java GAS Little Endian") + -+void pj_cons_fix_new_pj (struct frag *, int, int, expressionS *); ++void pj_cons_fix_new_pj (struct frag *, int, int, expressionS *, ++ bfd_reloc_code_real_type); +arelent *tc_gen_reloc (asection *, struct fix *); + +#define md_section_align(SEGMENT, SIZE) (SIZE) @@ -604310,8 +607047,8 @@ index 0000000..bec85a2 +#define md_pcrel_from(FIX) \ + ((FIX)->fx_where + (FIX)->fx_frag->fr_address - 1) + -+#define TC_CONS_FIX_NEW(FRAG, WHERE, NBYTES, EXP) \ -+ pj_cons_fix_new_pj (FRAG, WHERE, NBYTES, EXP) ++#define TC_CONS_FIX_NEW(FRAG, WHERE, NBYTES, EXP, RELOC) \ ++ pj_cons_fix_new_pj (FRAG, WHERE, NBYTES, EXP, RELOC) + +/* No shared lib support, so we don't need to ensure externally + visible symbols can be overridden. */ @@ -604325,14 +607062,12 @@ index 0000000..bec85a2 + || (FIX)->fx_r_type == BFD_RELOC_VTABLE_ENTRY)) diff --git a/gas/config/tc-ppc.c b/gas/config/tc-ppc.c new file mode 100644 -index 0000000..7c99e43 +index 0000000..ff4ea64 --- /dev/null +++ b/gas/config/tc-ppc.c -@@ -0,0 +1,7174 @@ +@@ -0,0 +1,7188 @@ +/* tc-ppc.c -- Assemble for the PowerPC or POWER (RS/6000) -+ Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, -+ 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1994-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor, Cygnus Support. + + This file is part of GAS, the GNU Assembler. @@ -604462,7 +607197,6 @@ index 0000000..7c99e43 +#endif + +#ifdef OBJ_ELF -+static void ppc_elf_cons (int); +static void ppc_elf_rdata (int); +static void ppc_elf_lcomm (int); +static void ppc_elf_localentry (int); @@ -604545,6 +607279,12 @@ index 0000000..7c99e43 + has_large_toc_reloc = 1, + has_small_toc_reloc = 2 +} toc_reloc_types; ++ ++/* Warn on emitting data to code sections. */ ++int warn_476; ++unsigned long last_insn; ++segT last_seg; ++subsegT last_subseg; + +/* The target specific pseudo-ops which we support. */ + @@ -604590,11 +607330,7 @@ index 0000000..7c99e43 +#endif + +#ifdef OBJ_ELF -+ { "llong", ppc_elf_cons, 8 }, -+ { "quad", ppc_elf_cons, 8 }, -+ { "long", ppc_elf_cons, 4 }, -+ { "word", ppc_elf_cons, 2 }, -+ { "short", ppc_elf_cons, 2 }, ++ { "llong", cons, 8 }, + { "rdata", ppc_elf_rdata, 0 }, + { "rodata", ppc_elf_rdata, 0 }, + { "lcomm", ppc_elf_lcomm, 0 }, @@ -605403,6 +608139,8 @@ index 0000000..7c99e43 +#define OPTION_NOPS (OPTION_MD_BASE + 0) +const struct option md_longopts[] = { + {"nops", required_argument, NULL, OPTION_NOPS}, ++ {"ppc476-workaround", no_argument, &warn_476, 1}, ++ {"no-ppc476-workaround", no_argument, &warn_476, 0}, + {NULL, no_argument, NULL, 0} +}; +const size_t md_longopts_size = sizeof (md_longopts); @@ -605581,6 +608319,9 @@ index 0000000..7c99e43 + } + break; + ++ case 0: ++ break; ++ + default: + return 0; + } @@ -605654,7 +608395,8 @@ index 0000000..7c99e43 +-Qy, -Qn ignored\n")); +#endif + fprintf (stream, _("\ -+-nops=count when aligning, more than COUNT nops uses a branch\n")); ++-nops=count when aligning, more than COUNT nops uses a branch\n\ ++-ppc476-workaround warn if emitting data to code sections\n")); +} + +/* Set ppc_cpu if it is not already set. */ @@ -606107,10 +608849,23 @@ index 0000000..7c99e43 + right = max & -max; + min = 0; + -+ if ((operand->flags & PPC_OPERAND_SIGNED) != 0) ++ if ((operand->flags & PPC_OPERAND_SIGNOPT) != 0) + { -+ if ((operand->flags & PPC_OPERAND_SIGNOPT) == 0) -+ max = (max >> 1) & -right; ++ /* Extend the allowed range for addis to [-65536, 65535]. ++ Similarly for some VLE high part insns. For 64-bit it ++ would be good to disable this for signed fields since the ++ value is sign extended into the high 32 bits of the register. ++ If the value is, say, an address, then we might care about ++ the high bits. However, gcc as of 2014-06 uses unsigned ++ values when loading the high part of 64-bit constants using ++ lis. ++ Use the same extended range for cmpli, to allow at least ++ [-32768, 65535]. */ ++ min = ~max & -right; ++ } ++ else if ((operand->flags & PPC_OPERAND_SIGNED) != 0) ++ { ++ max = (max >> 1) & -right; + min = ~max & -right; + } + @@ -606283,17 +609038,18 @@ index 0000000..7c99e43 + MAP64 ("dtprel@highera", BFD_RELOC_PPC64_DTPREL16_HIGHERA), + MAP64 ("dtprel@highest", BFD_RELOC_PPC64_DTPREL16_HIGHEST), + MAP64 ("dtprel@highesta", BFD_RELOC_PPC64_DTPREL16_HIGHESTA), ++ MAP64 ("localentry", BFD_RELOC_PPC64_ADDR64_LOCAL), + MAP64 ("tprel@high", BFD_RELOC_PPC64_TPREL16_HIGH), + MAP64 ("tprel@higha", BFD_RELOC_PPC64_TPREL16_HIGHA), + MAP64 ("tprel@higher", BFD_RELOC_PPC64_TPREL16_HIGHER), + MAP64 ("tprel@highera", BFD_RELOC_PPC64_TPREL16_HIGHERA), + MAP64 ("tprel@highest", BFD_RELOC_PPC64_TPREL16_HIGHEST), + MAP64 ("tprel@highesta", BFD_RELOC_PPC64_TPREL16_HIGHESTA), -+ { (char *) 0, 0, 0, 0, BFD_RELOC_UNUSED } ++ { (char *) 0, 0, 0, 0, BFD_RELOC_NONE } + }; + + if (*str++ != '@') -+ return BFD_RELOC_UNUSED; ++ return BFD_RELOC_NONE; + + for (ch = *str, str2 = ident; + (str2 < ident + sizeof (ident) - 1 @@ -606379,63 +609135,49 @@ index 0000000..7c99e43 + return (bfd_reloc_code_real_type) reloc; + } + -+ return BFD_RELOC_UNUSED; ++ return BFD_RELOC_NONE; +} + -+/* Like normal .long/.short/.word, except support @got, etc. -+ Clobbers input_line_pointer, checks end-of-line. */ -+static void -+ppc_elf_cons (int nbytes /* 1=.byte, 2=.word, 4=.long, 8=.llong */) ++/* Support @got, etc. on constants emitted via .short, .int etc. */ ++ ++bfd_reloc_code_real_type ++ppc_elf_parse_cons (expressionS *exp, unsigned int nbytes) +{ -+ expressionS exp; -+ bfd_reloc_code_real_type reloc; ++ expression (exp); ++ if (nbytes >= 2 && *input_line_pointer == '@') ++ return ppc_elf_suffix (&input_line_pointer, exp); ++ return BFD_RELOC_NONE; ++} + -+ if (is_it_end_of_statement ()) ++/* Warn when emitting data to code sections, unless we are emitting ++ a relocation that ld --ppc476-workaround uses to recognise data ++ *and* there was an unconditional branch prior to the data. */ ++ ++void ++ppc_elf_cons_fix_check (expressionS *exp ATTRIBUTE_UNUSED, ++ unsigned int nbytes, fixS *fix) ++{ ++ if (warn_476 ++ && (now_seg->flags & SEC_CODE) != 0 ++ && (nbytes != 4 ++ || fix == NULL ++ || !(fix->fx_r_type == BFD_RELOC_32 ++ || fix->fx_r_type == BFD_RELOC_CTOR ++ || fix->fx_r_type == BFD_RELOC_32_PCREL) ++ || !(last_seg == now_seg && last_subseg == now_subseg) ++ || !((last_insn & (0x3f << 26)) == (18u << 26) ++ || ((last_insn & (0x3f << 26)) == (16u << 26) ++ && (last_insn & (0x14 << 21)) == (0x14 << 21)) ++ || ((last_insn & (0x3f << 26)) == (19u << 26) ++ && (last_insn & (0x3ff << 1)) == (16u << 1) ++ && (last_insn & (0x14 << 21)) == (0x14 << 21))))) + { -+ demand_empty_rest_of_line (); -+ return; ++ /* Flag that we've warned. */ ++ if (fix != NULL) ++ fix->fx_tcbit = 1; ++ ++ as_warn (_("data in executable section")); + } -+ -+ do -+ { -+ expression (&exp); -+ if (*input_line_pointer == '@' -+ && (reloc = ppc_elf_suffix (&input_line_pointer, -+ &exp)) != BFD_RELOC_UNUSED) -+ { -+ reloc_howto_type *reloc_howto; -+ int size; -+ -+ reloc_howto = bfd_reloc_type_lookup (stdoutput, reloc); -+ size = bfd_get_reloc_size (reloc_howto); -+ -+ if (size > nbytes) -+ { -+ as_bad (_("%s relocations do not fit in %d bytes\n"), -+ reloc_howto->name, nbytes); -+ } -+ else -+ { -+ char *p; -+ int offset; -+ -+ p = frag_more (nbytes); -+ memset (p, 0, nbytes); -+ offset = 0; -+ if (target_big_endian) -+ offset = nbytes - size; -+ fix_new_exp (frag_now, p - frag_now->fr_literal + offset, size, -+ &exp, 0, reloc); -+ } -+ } -+ else -+ emit_expr (&exp, (unsigned int) nbytes); -+ } -+ while (*input_line_pointer++ == ','); -+ -+ /* Put terminator back into stream. */ -+ input_line_pointer--; -+ demand_empty_rest_of_line (); +} + +/* Solaris pseduo op to change to the .rodata section. */ @@ -606670,8 +609412,7 @@ index 0000000..7c99e43 + return; + + case SHLIB_MRELOCATABLE: -+ if (fixp->fx_r_type <= BFD_RELOC_UNUSED -+ && fixp->fx_r_type != BFD_RELOC_16_GOTOFF ++ if (fixp->fx_r_type != BFD_RELOC_16_GOTOFF + && fixp->fx_r_type != BFD_RELOC_HI16_GOTOFF + && fixp->fx_r_type != BFD_RELOC_LO16_GOTOFF + && fixp->fx_r_type != BFD_RELOC_HI16_S_GOTOFF @@ -607171,12 +609912,12 @@ index 0000000..7c99e43 + /* FIXME: these next two specifically specify 32/64 bit + toc entries. We don't support them today. Is this + the right way to say that? */ -+ toc_reloc = BFD_RELOC_UNUSED; ++ toc_reloc = BFD_RELOC_NONE; + as_bad (_("unimplemented toc32 expression modifier")); + break; + case must_be_64: + /* FIXME: see above. */ -+ toc_reloc = BFD_RELOC_UNUSED; ++ toc_reloc = BFD_RELOC_NONE; + as_bad (_("unimplemented toc64 expression modifier")); + break; + default: @@ -607246,7 +609987,7 @@ index 0000000..7c99e43 + bfd_reloc_code_real_type reloc; + char *orig_str = str; + -+ if ((reloc = ppc_elf_suffix (&str, &ex)) != BFD_RELOC_UNUSED) ++ if ((reloc = ppc_elf_suffix (&str, &ex)) != BFD_RELOC_NONE) + switch (reloc) + { + default: @@ -607332,7 +610073,7 @@ index 0000000..7c99e43 + } + else + { -+ bfd_reloc_code_real_type reloc = BFD_RELOC_UNUSED; ++ bfd_reloc_code_real_type reloc = BFD_RELOC_NONE; +#ifdef OBJ_ELF + if (ex.X_op == O_symbol && str[0] == '(') + { @@ -607349,7 +610090,7 @@ index 0000000..7c99e43 + expression (&tls_exp); + if (tls_exp.X_op == O_symbol) + { -+ reloc = BFD_RELOC_UNUSED; ++ reloc = BFD_RELOC_NONE; + if (strncasecmp (input_line_pointer, "@tlsgd)", 7) == 0) + { + reloc = BFD_RELOC_PPC_TLSGD; @@ -607360,7 +610101,7 @@ index 0000000..7c99e43 + reloc = BFD_RELOC_PPC_TLSLD; + input_line_pointer += 7; + } -+ if (reloc != BFD_RELOC_UNUSED) ++ if (reloc != BFD_RELOC_NONE) + { + SKIP_WHITESPACE (); + str = input_line_pointer; @@ -607377,7 +610118,7 @@ index 0000000..7c99e43 + } + } + -+ if ((reloc = ppc_elf_suffix (&str, &ex)) != BFD_RELOC_UNUSED) ++ if ((reloc = ppc_elf_suffix (&str, &ex)) != BFD_RELOC_NONE) + { + /* Some TLS tweaks. */ + switch (reloc) @@ -607473,116 +610214,21 @@ index 0000000..7c99e43 + break; + } + } -+ -+ /* For the absolute forms of branches, convert the PC -+ relative form back into the absolute. */ -+ if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) -+ { -+ switch (reloc) -+ { -+ case BFD_RELOC_PPC_B26: -+ reloc = BFD_RELOC_PPC_BA26; -+ break; -+ case BFD_RELOC_PPC_B16: -+ reloc = BFD_RELOC_PPC_BA16; -+ break; -+ case BFD_RELOC_PPC_B16_BRTAKEN: -+ reloc = BFD_RELOC_PPC_BA16_BRTAKEN; -+ break; -+ case BFD_RELOC_PPC_B16_BRNTAKEN: -+ reloc = BFD_RELOC_PPC_BA16_BRNTAKEN; -+ break; -+ default: -+ break; -+ } -+ } -+ -+ switch (reloc) -+ { -+ case BFD_RELOC_PPC_TOC16: -+ toc_reloc_types |= has_small_toc_reloc; -+ break; -+ case BFD_RELOC_PPC64_TOC16_LO: -+ case BFD_RELOC_PPC64_TOC16_HI: -+ case BFD_RELOC_PPC64_TOC16_HA: -+ toc_reloc_types |= has_large_toc_reloc; -+ break; -+ default: -+ break; -+ } -+ -+ if ((operand->flags & (PPC_OPERAND_DS | PPC_OPERAND_DQ)) != 0) -+ { -+ switch (reloc) -+ { -+ case BFD_RELOC_16: -+ reloc = BFD_RELOC_PPC64_ADDR16_DS; -+ break; -+ case BFD_RELOC_LO16: -+ reloc = BFD_RELOC_PPC64_ADDR16_LO_DS; -+ break; -+ case BFD_RELOC_16_GOTOFF: -+ reloc = BFD_RELOC_PPC64_GOT16_DS; -+ break; -+ case BFD_RELOC_LO16_GOTOFF: -+ reloc = BFD_RELOC_PPC64_GOT16_LO_DS; -+ break; -+ case BFD_RELOC_LO16_PLTOFF: -+ reloc = BFD_RELOC_PPC64_PLT16_LO_DS; -+ break; -+ case BFD_RELOC_16_BASEREL: -+ reloc = BFD_RELOC_PPC64_SECTOFF_DS; -+ break; -+ case BFD_RELOC_LO16_BASEREL: -+ reloc = BFD_RELOC_PPC64_SECTOFF_LO_DS; -+ break; -+ case BFD_RELOC_PPC_TOC16: -+ reloc = BFD_RELOC_PPC64_TOC16_DS; -+ break; -+ case BFD_RELOC_PPC64_TOC16_LO: -+ reloc = BFD_RELOC_PPC64_TOC16_LO_DS; -+ break; -+ case BFD_RELOC_PPC64_PLTGOT16: -+ reloc = BFD_RELOC_PPC64_PLTGOT16_DS; -+ break; -+ case BFD_RELOC_PPC64_PLTGOT16_LO: -+ reloc = BFD_RELOC_PPC64_PLTGOT16_LO_DS; -+ break; -+ case BFD_RELOC_PPC_DTPREL16: -+ reloc = BFD_RELOC_PPC64_DTPREL16_DS; -+ break; -+ case BFD_RELOC_PPC_DTPREL16_LO: -+ reloc = BFD_RELOC_PPC64_DTPREL16_LO_DS; -+ break; -+ case BFD_RELOC_PPC_TPREL16: -+ reloc = BFD_RELOC_PPC64_TPREL16_DS; -+ break; -+ case BFD_RELOC_PPC_TPREL16_LO: -+ reloc = BFD_RELOC_PPC64_TPREL16_LO_DS; -+ break; -+ case BFD_RELOC_PPC_GOT_DTPREL16: -+ case BFD_RELOC_PPC_GOT_DTPREL16_LO: -+ case BFD_RELOC_PPC_GOT_TPREL16: -+ case BFD_RELOC_PPC_GOT_TPREL16_LO: -+ break; -+ default: -+ as_bad (_("unsupported relocation for DS offset field")); -+ break; -+ } -+ } + } +#endif /* OBJ_ELF */ + -+ if (reloc != BFD_RELOC_UNUSED) ++ if (reloc != BFD_RELOC_NONE) + ; + /* Determine a BFD reloc value based on the operand information. + We are only prepared to turn a few of the operands into + relocs. */ -+ else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0 ++ else if ((operand->flags & (PPC_OPERAND_RELATIVE ++ | PPC_OPERAND_ABSOLUTE)) != 0 + && operand->bitm == 0x3fffffc + && operand->shift == 0) + reloc = BFD_RELOC_PPC_B26; -+ else if ((operand->flags & PPC_OPERAND_RELATIVE) != 0 ++ else if ((operand->flags & (PPC_OPERAND_RELATIVE ++ | PPC_OPERAND_ABSOLUTE)) != 0 + && operand->bitm == 0xfffc + && operand->shift == 0) + reloc = BFD_RELOC_PPC_B16; @@ -607598,40 +610244,126 @@ index 0000000..7c99e43 + && operand->bitm == 0x1fffffe + && operand->shift == 0) + reloc = BFD_RELOC_PPC_VLE_REL24; -+ else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0 -+ && operand->bitm == 0x3fffffc -+ && operand->shift == 0) -+ reloc = BFD_RELOC_PPC_BA26; -+ else if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0 -+ && operand->bitm == 0xfffc -+ && operand->shift == 0) -+ reloc = BFD_RELOC_PPC_BA16; -+#if defined (OBJ_XCOFF) || defined (OBJ_ELF) -+ else if ((operand->flags & PPC_OPERAND_PARENS) != 0 ++ else if ((operand->flags & PPC_OPERAND_NEGATIVE) == 0 + && (operand->bitm & 0xfff0) == 0xfff0 + && operand->shift == 0) + { ++ reloc = BFD_RELOC_16; ++#if defined OBJ_XCOFF || defined OBJ_ELF + /* Note: the symbol may be not yet defined. */ -+ if (ppc_is_toc_sym (ex.X_add_symbol)) ++ if ((operand->flags & PPC_OPERAND_PARENS) != 0 ++ && ppc_is_toc_sym (ex.X_add_symbol)) + { + reloc = BFD_RELOC_PPC_TOC16; +#ifdef OBJ_ELF -+ if (ppc_obj64 -+ && (operand->flags & PPC_OPERAND_DS) != 0) -+ reloc = BFD_RELOC_PPC64_TOC16_DS; ++ as_warn (_("assuming %s on symbol"), ++ ppc_obj64 ? "@toc" : "@xgot"); +#endif + } -+ else -+ { -+ reloc = BFD_RELOC_16; -+#ifdef OBJ_ELF -+ if (ppc_obj64 -+ && (operand->flags & PPC_OPERAND_DS) != 0) -+ reloc = BFD_RELOC_PPC64_ADDR16_DS; +#endif ++ } ++ ++ /* For the absolute forms of branches, convert the PC ++ relative form back into the absolute. */ ++ if ((operand->flags & PPC_OPERAND_ABSOLUTE) != 0) ++ { ++ switch (reloc) ++ { ++ case BFD_RELOC_PPC_B26: ++ reloc = BFD_RELOC_PPC_BA26; ++ break; ++ case BFD_RELOC_PPC_B16: ++ reloc = BFD_RELOC_PPC_BA16; ++ break; ++#ifdef OBJ_ELF ++ case BFD_RELOC_PPC_B16_BRTAKEN: ++ reloc = BFD_RELOC_PPC_BA16_BRTAKEN; ++ break; ++ case BFD_RELOC_PPC_B16_BRNTAKEN: ++ reloc = BFD_RELOC_PPC_BA16_BRNTAKEN; ++ break; ++#endif ++ default: ++ break; + } + } -+#endif /* defined (OBJ_XCOFF) || defined (OBJ_ELF) */ ++ ++#ifdef OBJ_ELF ++ switch (reloc) ++ { ++ case BFD_RELOC_PPC_TOC16: ++ toc_reloc_types |= has_small_toc_reloc; ++ break; ++ case BFD_RELOC_PPC64_TOC16_LO: ++ case BFD_RELOC_PPC64_TOC16_HI: ++ case BFD_RELOC_PPC64_TOC16_HA: ++ toc_reloc_types |= has_large_toc_reloc; ++ break; ++ default: ++ break; ++ } ++ ++ if (ppc_obj64 ++ && (operand->flags & (PPC_OPERAND_DS | PPC_OPERAND_DQ)) != 0) ++ { ++ switch (reloc) ++ { ++ case BFD_RELOC_16: ++ reloc = BFD_RELOC_PPC64_ADDR16_DS; ++ break; ++ case BFD_RELOC_LO16: ++ reloc = BFD_RELOC_PPC64_ADDR16_LO_DS; ++ break; ++ case BFD_RELOC_16_GOTOFF: ++ reloc = BFD_RELOC_PPC64_GOT16_DS; ++ break; ++ case BFD_RELOC_LO16_GOTOFF: ++ reloc = BFD_RELOC_PPC64_GOT16_LO_DS; ++ break; ++ case BFD_RELOC_LO16_PLTOFF: ++ reloc = BFD_RELOC_PPC64_PLT16_LO_DS; ++ break; ++ case BFD_RELOC_16_BASEREL: ++ reloc = BFD_RELOC_PPC64_SECTOFF_DS; ++ break; ++ case BFD_RELOC_LO16_BASEREL: ++ reloc = BFD_RELOC_PPC64_SECTOFF_LO_DS; ++ break; ++ case BFD_RELOC_PPC_TOC16: ++ reloc = BFD_RELOC_PPC64_TOC16_DS; ++ break; ++ case BFD_RELOC_PPC64_TOC16_LO: ++ reloc = BFD_RELOC_PPC64_TOC16_LO_DS; ++ break; ++ case BFD_RELOC_PPC64_PLTGOT16: ++ reloc = BFD_RELOC_PPC64_PLTGOT16_DS; ++ break; ++ case BFD_RELOC_PPC64_PLTGOT16_LO: ++ reloc = BFD_RELOC_PPC64_PLTGOT16_LO_DS; ++ break; ++ case BFD_RELOC_PPC_DTPREL16: ++ reloc = BFD_RELOC_PPC64_DTPREL16_DS; ++ break; ++ case BFD_RELOC_PPC_DTPREL16_LO: ++ reloc = BFD_RELOC_PPC64_DTPREL16_LO_DS; ++ break; ++ case BFD_RELOC_PPC_TPREL16: ++ reloc = BFD_RELOC_PPC64_TPREL16_DS; ++ break; ++ case BFD_RELOC_PPC_TPREL16_LO: ++ reloc = BFD_RELOC_PPC64_TPREL16_LO_DS; ++ break; ++ case BFD_RELOC_PPC_GOT_DTPREL16: ++ case BFD_RELOC_PPC_GOT_DTPREL16_LO: ++ case BFD_RELOC_PPC_GOT_TPREL16: ++ case BFD_RELOC_PPC_GOT_TPREL16_LO: ++ break; ++ default: ++ as_bad (_("unsupported relocation for DS offset field")); ++ break; ++ } ++ } ++#endif + + /* We need to generate a fixup for this expression. */ + if (fc >= MAX_INSN_FIXUPS) @@ -607737,6 +610469,9 @@ index 0000000..7c99e43 + frag_now->insn_addr = addr_mod; + frag_now->has_code = 1; + md_number_to_chars (f, insn, insn_length); ++ last_insn = insn; ++ last_seg = now_seg; ++ last_subseg = now_subseg; + +#ifdef OBJ_ELF + dwarf2_emit_insn (insn_length); @@ -607746,7 +610481,7 @@ index 0000000..7c99e43 + for (i = 0; i < fc; i++) + { + fixS *fixP; -+ if (fixups[i].reloc != BFD_RELOC_UNUSED) ++ if (fixups[i].reloc != BFD_RELOC_NONE) + { + reloc_howto_type *reloc_howto; + int size; @@ -607779,7 +610514,7 @@ index 0000000..7c99e43 + insn_length, + &fixups[i].exp, + (operand->flags & PPC_OPERAND_RELATIVE) != 0, -+ BFD_RELOC_UNUSED); ++ BFD_RELOC_NONE); + } + fixP->fx_pcrel_adjust = fixups[i].opindex; + } @@ -607894,6 +610629,8 @@ index 0000000..7c99e43 +static void +ppc_byte (int ignore ATTRIBUTE_UNUSED) +{ ++ int count = 0; ++ + if (*input_line_pointer != '\"') + { + cons (1); @@ -607917,8 +610654,11 @@ index 0000000..7c99e43 + } + + FRAG_APPEND_1_CHAR (c); ++ ++count; + } + ++ if (warn_476 && count != 0 && (now_seg->flags & SEC_CODE) != 0) ++ as_warn (_("data in executable section")); + demand_empty_rest_of_line (); +} + @@ -610803,7 +613543,7 @@ index 0000000..7c99e43 + fixups we generated by the calls to fix_new_exp, above. */ + +void -+md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) ++md_apply_fix (fixS *fixP, valueT *valP, segT seg) +{ + valueT value = * valP; + offsetT fieldval; @@ -611151,7 +613891,7 @@ index 0000000..7c99e43 + return; + + gas_assert (fixP->fx_addsy != NULL); -+ if (fixP->fx_r_type == BFD_RELOC_UNUSED) ++ if (fixP->fx_r_type == BFD_RELOC_NONE) + { + char *sfile; + unsigned int sline; @@ -611199,6 +613939,7 @@ index 0000000..7c99e43 + case BFD_RELOC_PPC64_HIGHEST_S: + case BFD_RELOC_PPC64_ADDR16_HIGH: + case BFD_RELOC_PPC64_ADDR16_HIGHA: ++ case BFD_RELOC_PPC64_ADDR64_LOCAL: + break; + + case BFD_RELOC_PPC_DTPMOD: @@ -611315,6 +614056,16 @@ index 0000000..7c99e43 + if (fixP->fx_size && APPLY_RELOC) + md_number_to_chars (fixP->fx_frag->fr_literal + fixP->fx_where, + fieldval, fixP->fx_size); ++ if (warn_476 ++ && (seg->flags & SEC_CODE) != 0 ++ && fixP->fx_size == 4 ++ && fixP->fx_done ++ && !fixP->fx_tcbit ++ && (fixP->fx_r_type == BFD_RELOC_32 ++ || fixP->fx_r_type == BFD_RELOC_CTOR ++ || fixP->fx_r_type == BFD_RELOC_32_PCREL)) ++ as_warn_where (fixP->fx_file, fixP->fx_line, ++ _("data in executable section")); + } + + /* We are only able to convert some relocs to pc-relative. */ @@ -611505,13 +614256,12 @@ index 0000000..7c99e43 +} diff --git a/gas/config/tc-ppc.h b/gas/config/tc-ppc.h new file mode 100644 -index 0000000..6095416 +index 0000000..3cd9bf1 --- /dev/null +++ b/gas/config/tc-ppc.h -@@ -0,0 +1,283 @@ +@@ -0,0 +1,290 @@ +/* tc-ppc.h -- Header file for tc-ppc.c. -+ Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, -+ 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. ++ Copyright (C) 1994-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor, Cygnus Support. + + This file is part of GAS, the GNU Assembler. @@ -611743,6 +614493,14 @@ index 0000000..6095416 +/* Values passed to md_apply_fix don't include symbol values. */ +#define MD_APPLY_SYM_VALUE(FIX) 0 + ++#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) \ ++ ppc_elf_parse_cons (EXP, NBYTES) ++extern bfd_reloc_code_real_type ppc_elf_parse_cons (expressionS *, ++ unsigned int); ++#define TC_CONS_FIX_CHECK(EXP, NBYTES, FIX) \ ++ ppc_elf_cons_fix_check (EXP, NBYTES, FIX) ++extern void ppc_elf_cons_fix_check (expressionS *, unsigned int, struct fix *); ++ +#define tc_frob_file_before_adjust ppc_frob_file_before_adjust +extern void ppc_frob_file_before_adjust (void); + @@ -611794,12 +614552,12 @@ index 0000000..6095416 +#define DWARF2_CIE_DATA_ALIGNMENT ppc_cie_data_alignment diff --git a/gas/config/tc-rl78.c b/gas/config/tc-rl78.c new file mode 100644 -index 0000000..651f3f6 +index 0000000..0cd7e5b --- /dev/null +++ b/gas/config/tc-rl78.c -@@ -0,0 +1,844 @@ +@@ -0,0 +1,1403 @@ +/* tc-rl78.c -- Assembler for the Renesas RL78 -+ Copyright 2011-2013 Free Software Foundation, Inc. ++ Copyright (C) 2011-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -611886,6 +614644,15 @@ index 0000000..651f3f6 +static rl78_bytesT rl78_bytes; + +void ++rl78_relax (int type, int pos) ++{ ++ rl78_bytes.relax[rl78_bytes.n_relax].type = type; ++ rl78_bytes.relax[rl78_bytes.n_relax].field_pos = pos; ++ rl78_bytes.relax[rl78_bytes.n_relax].val_ofs = rl78_bytes.n_base + rl78_bytes.n_ops; ++ rl78_bytes.n_relax ++; ++} ++ ++void +rl78_linkrelax_addr16 (void) +{ + rl78_bytes.link_relax |= RL78_RELAXA_ADDR16; @@ -611999,6 +614766,16 @@ index 0000000..651f3f6 + if (nbytes > 2 + && exp.X_md == BFD_RELOC_RL78_CODE) + exp.X_md = 0; ++ ++ if (nbytes == 1 ++ && (exp.X_md == BFD_RELOC_RL78_LO16 ++ || exp.X_md == BFD_RELOC_RL78_HI16)) ++ as_bad (_("16-bit relocation used in 8-bit operand")); ++ ++ if (nbytes == 2 ++ && exp.X_md == BFD_RELOC_RL78_HI8) ++ as_bad (_("8-bit relocation used in 16-bit operand")); ++ + rl78_op_fixup (exp, rl78_bytes.n_ops * 8, nbytes * 8, type); + memset (rl78_bytes.ops + rl78_bytes.n_ops, 0, nbytes); + rl78_bytes.n_ops += nbytes; @@ -612063,6 +614840,8 @@ index 0000000..651f3f6 +{ + OPTION_RELAX = OPTION_MD_BASE, + OPTION_G10, ++ OPTION_32BIT_DOUBLES, ++ OPTION_64BIT_DOUBLES, +}; + +#define RL78_SHORTOPTS "" @@ -612073,6 +614852,8 @@ index 0000000..651f3f6 +{ + {"relax", no_argument, NULL, OPTION_RELAX}, + {"mg10", no_argument, NULL, OPTION_G10}, ++ {"m32bit-doubles", no_argument, NULL, OPTION_32BIT_DOUBLES}, ++ {"m64bit-doubles", no_argument, NULL, OPTION_64BIT_DOUBLES}, + {NULL, no_argument, NULL, 0} +}; +size_t md_longopts_size = sizeof (md_longopts); @@ -612089,6 +614870,14 @@ index 0000000..651f3f6 + case OPTION_G10: + elf_flags |= E_FLAG_RL78_G10; + return 1; ++ ++ case OPTION_32BIT_DOUBLES: ++ elf_flags &= ~ E_FLAG_RL78_64BIT_DOUBLES; ++ return 1; ++ ++ case OPTION_64BIT_DOUBLES: ++ elf_flags |= E_FLAG_RL78_64BIT_DOUBLES; ++ return 1; + } + return 0; +} @@ -612096,9 +614885,12 @@ index 0000000..651f3f6 +void +md_show_usage (FILE * stream ATTRIBUTE_UNUSED) +{ ++ fprintf (stream, _(" RL78 specific command line options:\n")); ++ fprintf (stream, _(" --mg10 Enable support for G10 variant\n")); ++ fprintf (stream, _(" --m32bit-doubles [default]\n")); ++ fprintf (stream, _(" --m64bit-doubles\n")); +} + -+ +static void +s_bss (int ignore ATTRIBUTE_UNUSED) +{ @@ -612109,15 +614901,23 @@ index 0000000..651f3f6 + demand_empty_rest_of_line (); +} + ++static void ++rl78_float_cons (int ignore ATTRIBUTE_UNUSED) ++{ ++ if (elf_flags & E_FLAG_RL78_64BIT_DOUBLES) ++ return float_cons ('d'); ++ return float_cons ('f'); ++} ++ +/* The target specific pseudo-ops which we support. */ +const pseudo_typeS md_pseudo_table[] = +{ -+ /* Our "standard" pseudos. */ -+ { "double", float_cons, 'd' }, -+ { "bss", s_bss, 0 }, -+ { "3byte", cons, 3 }, -+ { "int", cons, 4 }, -+ { "word", cons, 4 }, ++ /* Our "standard" pseudos. */ ++ { "double", rl78_float_cons, 'd' }, ++ { "bss", s_bss, 0 }, ++ { "3byte", cons, 3 }, ++ { "int", cons, 4 }, ++ { "word", cons, 4 }, + + /* End of list marker. */ + { NULL, NULL, 0 } @@ -612147,6 +614947,23 @@ index 0000000..651f3f6 + number_to_chars_littleendian (buf, val, n); +} + ++static void ++require_end_of_expr (char *fname) ++{ ++ while (* input_line_pointer == ' ' ++ || * input_line_pointer == '\t') ++ input_line_pointer ++; ++ ++ if (! * input_line_pointer ++ || strchr ("\n\r,", * input_line_pointer) ++ || strchr (comment_chars, * input_line_pointer) ++ || strchr (line_comment_chars, * input_line_pointer) ++ || strchr (line_separator_chars, * input_line_pointer)) ++ return; ++ ++ as_bad (_("%%%s() must be outermost term in expression"), fname); ++} ++ +static struct +{ + char * fname; @@ -612188,6 +615005,8 @@ index 0000000..651f3f6 + input_line_pointer ++; + + exp->X_md = reloc; ++ ++ require_end_of_expr (reloc_functions[i].fname); +} + +void @@ -612267,12 +615086,13 @@ index 0000000..651f3f6 + rl78_parse (); + + /* This simplifies the relaxation code. */ -+ if (rl78_bytes.link_relax) ++ if (rl78_bytes.n_relax || rl78_bytes.link_relax) + { + int olen = rl78_bytes.n_prefix + rl78_bytes.n_base + rl78_bytes.n_ops; + /* We do it this way because we want the frag to have the -+ rl78_bytes in it, which we initialize above. */ -+ bytes = frag_more (olen); ++ rl78_bytes in it, which we initialize above. The extra bytes ++ are for relaxing. */ ++ bytes = frag_more (olen + 3); + frag_then = frag_now; + frag_variant (rs_machine_dependent, + olen /* max_chars */, @@ -612352,6 +615172,7 @@ index 0000000..651f3f6 + expressionS * exp) +{ + bfd_reloc_code_real_type type; ++ fixS *fixP; + + switch (size) + { @@ -612401,16 +615222,495 @@ index 0000000..651f3f6 + type = BFD_RELOC_RL78_DIFF; + } + -+ fix_new_exp (frag, where, (int) size, exp, 0, type); ++ fixP = fix_new_exp (frag, where, (int) size, exp, 0, type); ++ switch (exp->X_md) ++ { ++ /* These are intended to have values larger than the container, ++ since the backend puts only the portion we need in it. ++ However, we don't have a backend-specific reloc for them as ++ they're handled with complex relocations. */ ++ case BFD_RELOC_RL78_LO16: ++ case BFD_RELOC_RL78_HI16: ++ case BFD_RELOC_RL78_HI8: ++ fixP->fx_no_overflow = 1; ++ break; ++ default: ++ break; ++ } +} + -+/* No relaxation just yet */ ++ ++/*----------------------------------------------------------------------*/ ++/* To recap: we estimate everything based on md_estimate_size, then ++ adjust based on rl78_relax_frag. When it all settles, we call ++ md_convert frag to update the bytes. The relaxation types and ++ relocations are in fragP->tc_frag_data, which is a copy of that ++ rl78_bytes. ++ ++ Our scheme is as follows: fr_fix has the size of the smallest ++ opcode (like BRA.S). We store the number of total bytes we need in ++ fr_subtype. When we're done relaxing, we use fr_subtype and the ++ existing opcode bytes to figure out what actual opcode we need to ++ put in there. If the fixup isn't resolvable now, we use the ++ maximal size. */ ++ ++#define TRACE_RELAX 0 ++#define tprintf if (TRACE_RELAX) printf ++ ++ ++typedef enum ++{ ++ OT_other, ++ OT_bt, ++ OT_bt_sfr, ++ OT_bt_es, ++ OT_bc, ++ OT_bh ++} op_type_T; ++ ++/* We're looking for these types of relaxations: ++ ++ BT 00110001 sbit0cc1 addr---- (cc is 10 (BF) or 01 (BT)) ++ B~T 00110001 sbit0cc1 00000011 11101110 pcrel16- -------- (BR $!pcrel20) ++ ++ BT sfr 00110001 sbit0cc0 sfr----- addr---- ++ BT ES: 00010001 00101110 sbit0cc1 addr---- ++ ++ BC 110111cc addr---- ++ B~C 110111cc 00000011 11101110 pcrel16- -------- (BR $!pcrel20) ++ ++ BH 01100001 110c0011 00000011 11101110 pcrel16- -------- (BR $!pcrel20) ++ B~H 01100001 110c0011 00000011 11101110 pcrel16- -------- (BR $!pcrel20) ++*/ ++ ++/* Given the opcode bytes at OP, figure out which opcode it is and ++ return the type of opcode. We use this to re-encode the opcode as ++ a different size later. */ ++ ++static op_type_T ++rl78_opcode_type (char * op) ++{ ++ if (op[0] == 0x31 ++ && ((op[1] & 0x0f) == 0x05 ++ || (op[1] & 0x0f) == 0x03)) ++ return OT_bt; ++ ++ if (op[0] == 0x31 ++ && ((op[1] & 0x0f) == 0x04 ++ || (op[1] & 0x0f) == 0x02)) ++ return OT_bt_sfr; ++ ++ if (op[0] == 0x11 ++ && op[1] == 0x31 ++ && ((op[2] & 0x0f) == 0x05 ++ || (op[2] & 0x0f) == 0x03)) ++ return OT_bt_es; ++ ++ if ((op[0] & 0xfc) == 0xdc) ++ return OT_bc; ++ ++ if (op[0] == 0x61 ++ && (op[1] & 0xef) == 0xc3) ++ return OT_bh; ++ ++ return OT_other; ++} ++ ++/* Returns zero if *addrP has the target address. Else returns nonzero ++ if we cannot compute the target address yet. */ ++ ++static int ++rl78_frag_fix_value (fragS * fragP, ++ segT segment, ++ int which, ++ addressT * addrP, ++ int need_diff, ++ addressT * sym_addr) ++{ ++ addressT addr = 0; ++ rl78_bytesT * b = fragP->tc_frag_data; ++ expressionS * exp = & b->fixups[which].exp; ++ ++ if (need_diff && exp->X_op != O_subtract) ++ return 1; ++ ++ if (exp->X_add_symbol) ++ { ++ if (S_FORCE_RELOC (exp->X_add_symbol, 1)) ++ return 1; ++ if (S_GET_SEGMENT (exp->X_add_symbol) != segment) ++ return 1; ++ addr += S_GET_VALUE (exp->X_add_symbol); ++ } ++ ++ if (exp->X_op_symbol) ++ { ++ if (exp->X_op != O_subtract) ++ return 1; ++ if (S_FORCE_RELOC (exp->X_op_symbol, 1)) ++ return 1; ++ if (S_GET_SEGMENT (exp->X_op_symbol) != segment) ++ return 1; ++ addr -= S_GET_VALUE (exp->X_op_symbol); ++ } ++ if (sym_addr) ++ * sym_addr = addr; ++ addr += exp->X_add_number; ++ * addrP = addr; ++ return 0; ++} ++ ++/* Estimate how big the opcode is after this relax pass. The return ++ value is the difference between fr_fix and the actual size. We ++ compute the total size in rl78_relax_frag and store it in fr_subtype, ++ sowe only need to subtract fx_fix and return it. */ ++ +int +md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED, segT segment ATTRIBUTE_UNUSED) +{ -+ return 0; ++ int opfixsize; ++ int delta; ++ ++ /* This is the size of the opcode that's accounted for in fr_fix. */ ++ opfixsize = fragP->fr_fix - (fragP->fr_opcode - fragP->fr_literal); ++ /* This is the size of the opcode that isn't. */ ++ delta = (fragP->fr_subtype - opfixsize); ++ ++ tprintf (" -> opfixsize %d delta %d\n", opfixsize, delta); ++ return delta; +} + ++/* Given the new addresses for this relax pass, figure out how big ++ each opcode must be. We store the total number of bytes needed in ++ fr_subtype. The return value is the difference between the size ++ after the last pass and the size after this pass, so we use the old ++ fr_subtype to calculate the difference. */ ++ ++int ++rl78_relax_frag (segT segment ATTRIBUTE_UNUSED, fragS * fragP, long stretch) ++{ ++ addressT addr0, sym_addr; ++ addressT mypc; ++ int disp; ++ int oldsize = fragP->fr_subtype; ++ int newsize = oldsize; ++ op_type_T optype; ++ int ri; ++ ++ mypc = fragP->fr_address + (fragP->fr_opcode - fragP->fr_literal); ++ ++ /* If we ever get more than one reloc per opcode, this is the one ++ we're relaxing. */ ++ ri = 0; ++ ++ optype = rl78_opcode_type (fragP->fr_opcode); ++ /* Try to get the target address. */ ++ if (rl78_frag_fix_value (fragP, segment, ri, & addr0, ++ fragP->tc_frag_data->relax[ri].type != RL78_RELAX_BRANCH, ++ & sym_addr)) ++ { ++ /* If we don't, we must use the maximum size for the linker. */ ++ switch (fragP->tc_frag_data->relax[ri].type) ++ { ++ case RL78_RELAX_BRANCH: ++ switch (optype) ++ { ++ case OT_bt: ++ newsize = 6; ++ break; ++ case OT_bt_sfr: ++ case OT_bt_es: ++ newsize = 7; ++ break; ++ case OT_bc: ++ newsize = 5; ++ break; ++ case OT_bh: ++ newsize = 6; ++ break; ++ case OT_other: ++ newsize = oldsize; ++ break; ++ } ++ break; ++ ++ } ++ fragP->fr_subtype = newsize; ++ tprintf (" -> new %d old %d delta %d (external)\n", newsize, oldsize, newsize-oldsize); ++ return newsize - oldsize; ++ } ++ ++ if (sym_addr > mypc) ++ addr0 += stretch; ++ ++ switch (fragP->tc_frag_data->relax[ri].type) ++ { ++ case RL78_RELAX_BRANCH: ++ disp = (int) addr0 - (int) mypc; ++ ++ switch (optype) ++ { ++ case OT_bt: ++ if (disp >= -128 && (disp - (oldsize-2)) <= 127) ++ newsize = 3; ++ else ++ newsize = 6; ++ break; ++ case OT_bt_sfr: ++ case OT_bt_es: ++ if (disp >= -128 && (disp - (oldsize-3)) <= 127) ++ newsize = 4; ++ else ++ newsize = 7; ++ break; ++ case OT_bc: ++ if (disp >= -128 && (disp - (oldsize-1)) <= 127) ++ newsize = 2; ++ else ++ newsize = 5; ++ break; ++ case OT_bh: ++ if (disp >= -128 && (disp - (oldsize-2)) <= 127) ++ newsize = 3; ++ else ++ newsize = 6; ++ break; ++ case OT_other: ++ newsize = oldsize; ++ break; ++ } ++ break; ++ } ++ ++ /* This prevents infinite loops in align-heavy sources. */ ++ if (newsize < oldsize) ++ { ++ if (fragP->tc_frag_data->times_shrank > 10 ++ && fragP->tc_frag_data->times_grown > 10) ++ newsize = oldsize; ++ if (fragP->tc_frag_data->times_shrank < 20) ++ fragP->tc_frag_data->times_shrank ++; ++ } ++ else if (newsize > oldsize) ++ { ++ if (fragP->tc_frag_data->times_grown < 20) ++ fragP->tc_frag_data->times_grown ++; ++ } ++ ++ fragP->fr_subtype = newsize; ++ tprintf (" -> new %d old %d delta %d\n", newsize, oldsize, newsize-oldsize); ++ return newsize - oldsize; ++ } ++ ++/* This lets us test for the opcode type and the desired size in a ++ switch statement. */ ++#define OPCODE(type,size) ((type) * 16 + (size)) ++ ++/* Given the opcode stored in fr_opcode and the number of bytes we ++ think we need, encode a new opcode. We stored a pointer to the ++ fixup for this opcode in the tc_frag_data structure. If we can do ++ the fixup here, we change the relocation type to "none" (we test ++ for that in tc_gen_reloc) else we change it to the right type for ++ the new (biggest) opcode. */ ++ ++void ++md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, ++ segT segment ATTRIBUTE_UNUSED, ++ fragS * fragP ATTRIBUTE_UNUSED) ++{ ++ rl78_bytesT * rl78b = fragP->tc_frag_data; ++ addressT addr0, mypc; ++ int disp; ++ int reloc_type, reloc_adjust; ++ char * op = fragP->fr_opcode; ++ int keep_reloc = 0; ++ int ri; ++ int fi = (rl78b->n_fixups > 1) ? 1 : 0; ++ fixS * fix = rl78b->fixups[fi].fixP; ++ ++ /* If we ever get more than one reloc per opcode, this is the one ++ we're relaxing. */ ++ ri = 0; ++ ++ /* We used a new frag for this opcode, so the opcode address should ++ be the frag address. */ ++ mypc = fragP->fr_address + (fragP->fr_opcode - fragP->fr_literal); ++ tprintf("\033[32mmypc: 0x%x\033[0m\n", (int)mypc); ++ ++ /* Try to get the target address. If we fail here, we just use the ++ largest format. */ ++ if (rl78_frag_fix_value (fragP, segment, 0, & addr0, ++ fragP->tc_frag_data->relax[ri].type != RL78_RELAX_BRANCH, 0)) ++ { ++ /* We don't know the target address. */ ++ keep_reloc = 1; ++ addr0 = 0; ++ disp = 0; ++ tprintf ("unknown addr ? - %x = ?\n", (int)mypc); ++ } ++ else ++ { ++ /* We know the target address, and it's in addr0. */ ++ disp = (int) addr0 - (int) mypc; ++ tprintf ("known addr %x - %x = %d\n", (int)addr0, (int)mypc, disp); ++ } ++ ++ if (linkrelax) ++ keep_reloc = 1; ++ ++ reloc_type = BFD_RELOC_NONE; ++ reloc_adjust = 0; ++ ++ switch (fragP->tc_frag_data->relax[ri].type) ++ { ++ case RL78_RELAX_BRANCH: ++ switch (OPCODE (rl78_opcode_type (fragP->fr_opcode), fragP->fr_subtype)) ++ { ++ ++ case OPCODE (OT_bt, 3): /* BT A,$ - no change. */ ++ disp -= 3; ++ op[2] = disp; ++ break; ++ ++ case OPCODE (OT_bt, 6): /* BT A,$ - long version. */ ++ disp -= 3; ++ op[1] ^= 0x06; /* toggle conditional. */ ++ op[2] = 3; /* displacement over long branch. */ ++ disp -= 3; ++ op[3] = 0xEE; /* BR $!addr20 */ ++ op[4] = disp & 0xff; ++ op[5] = disp >> 8; ++ reloc_type = keep_reloc ? BFD_RELOC_16_PCREL : BFD_RELOC_NONE; ++ reloc_adjust = 2; ++ break; ++ ++ case OPCODE (OT_bt_sfr, 4): /* BT PSW,$ - no change. */ ++ disp -= 4; ++ op[3] = disp; ++ break; ++ ++ case OPCODE (OT_bt_sfr, 7): /* BT PSW,$ - long version. */ ++ disp -= 4; ++ op[1] ^= 0x06; /* toggle conditional. */ ++ op[3] = 3; /* displacement over long branch. */ ++ disp -= 3; ++ op[4] = 0xEE; /* BR $!addr20 */ ++ op[5] = disp & 0xff; ++ op[6] = disp >> 8; ++ reloc_type = keep_reloc ? BFD_RELOC_16_PCREL : BFD_RELOC_NONE; ++ reloc_adjust = 2; ++ break; ++ ++ case OPCODE (OT_bt_es, 4): /* BT ES:[HL],$ - no change. */ ++ disp -= 4; ++ op[3] = disp; ++ break; ++ ++ case OPCODE (OT_bt_es, 7): /* BT PSW,$ - long version. */ ++ disp -= 4; ++ op[2] ^= 0x06; /* toggle conditional. */ ++ op[3] = 3; /* displacement over long branch. */ ++ disp -= 3; ++ op[4] = 0xEE; /* BR $!addr20 */ ++ op[5] = disp & 0xff; ++ op[6] = disp >> 8; ++ reloc_type = keep_reloc ? BFD_RELOC_16_PCREL : BFD_RELOC_NONE; ++ reloc_adjust = 2; ++ break; ++ ++ case OPCODE (OT_bc, 2): /* BC $ - no change. */ ++ disp -= 2; ++ op[1] = disp; ++ break; ++ ++ case OPCODE (OT_bc, 5): /* BC $ - long version. */ ++ disp -= 2; ++ op[0] ^= 0x02; /* toggle conditional. */ ++ op[1] = 3; ++ disp -= 3; ++ op[2] = 0xEE; /* BR $!addr20 */ ++ op[3] = disp & 0xff; ++ op[4] = disp >> 8; ++ reloc_type = keep_reloc ? BFD_RELOC_16_PCREL : BFD_RELOC_NONE; ++ reloc_adjust = 2; ++ break; ++ ++ case OPCODE (OT_bh, 3): /* BH $ - no change. */ ++ disp -= 3; ++ op[2] = disp; ++ break; ++ ++ case OPCODE (OT_bh, 6): /* BC $ - long version. */ ++ disp -= 3; ++ op[1] ^= 0x10; /* toggle conditional. */ ++ op[2] = 3; ++ disp -= 3; ++ op[3] = 0xEE; /* BR $!addr20 */ ++ op[4] = disp & 0xff; ++ op[5] = disp >> 8; ++ reloc_type = keep_reloc ? BFD_RELOC_16_PCREL : BFD_RELOC_NONE; ++ reloc_adjust = 2; ++ break; ++ ++ default: ++ fprintf(stderr, "Missed case %d %d at 0x%lx\n", ++ rl78_opcode_type (fragP->fr_opcode), fragP->fr_subtype, mypc); ++ abort (); ++ ++ } ++ break; ++ ++ default: ++ if (rl78b->n_fixups) ++ { ++ reloc_type = fix->fx_r_type; ++ reloc_adjust = 0; ++ } ++ break; ++ } ++ ++ if (rl78b->n_fixups) ++ { ++ ++ fix->fx_r_type = reloc_type; ++ fix->fx_where += reloc_adjust; ++ switch (reloc_type) ++ { ++ case BFD_RELOC_NONE: ++ fix->fx_size = 0; ++ break; ++ case BFD_RELOC_8: ++ fix->fx_size = 1; ++ break; ++ case BFD_RELOC_16_PCREL: ++ fix->fx_size = 2; ++ break; ++ } ++ } ++ ++ fragP->fr_fix = fragP->fr_subtype + (fragP->fr_opcode - fragP->fr_literal); ++ tprintf ("fragP->fr_fix now %ld (%d + (%p - %p)\n", (long) fragP->fr_fix, ++ fragP->fr_subtype, fragP->fr_opcode, fragP->fr_literal); ++ fragP->fr_var = 0; ++ ++ tprintf ("compare 0x%lx vs 0x%lx - 0x%lx = 0x%lx (%p)\n", ++ (long)fragP->fr_fix, ++ (long)fragP->fr_next->fr_address, (long)fragP->fr_address, ++ (long)(fragP->fr_next->fr_address - fragP->fr_address), ++ fragP->fr_next); ++ ++ if (fragP->fr_next != NULL ++ && ((offsetT) (fragP->fr_next->fr_address - fragP->fr_address) ++ != fragP->fr_fix)) ++ as_bad (_("bad frag at %p : fix %ld addr %ld %ld \n"), fragP, ++ (long) fragP->fr_fix, ++ (long) fragP->fr_address, (long) fragP->fr_next->fr_address); ++} ++ ++/* End of relaxation code. ++ ----------------------------------------------------------------------*/ ++ ++ +arelent ** +tc_gen_reloc (asection * seg ATTRIBUTE_UNUSED, fixS * fixp) +{ @@ -612488,8 +615788,8 @@ index 0000000..651f3f6 + break; + + case BFD_RELOC_RL78_CODE: -+ SYM0 (); -+ OP (ABS16); ++ reloc[0]->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_RL78_16U); ++ reloc[1] = NULL; + break; + + case BFD_RELOC_RL78_LO16: @@ -612591,13 +615891,23 @@ index 0000000..651f3f6 + f->fx_done = 1; + break; + -+ case BFD_RELOC_8: + case BFD_RELOC_8_PCREL: ++ if ((long)val < -128 || (long)val > 127) ++ as_bad_where (f->fx_file, f->fx_line, ++ _("value of %ld too large for 8-bit branch"), ++ val); ++ /* Fall through. */ ++ case BFD_RELOC_8: + op[0] = val; + break; + -+ case BFD_RELOC_16: + case BFD_RELOC_16_PCREL: ++ if ((long)val < -32768 || (long)val > 32767) ++ as_bad_where (f->fx_file, f->fx_line, ++ _("value of %ld too large for 16-bit branch"), ++ val); ++ /* Fall through. */ ++ case BFD_RELOC_16: + case BFD_RELOC_RL78_CODE: + op[0] = val; + op[1] = val >> 8; @@ -612617,6 +615927,22 @@ index 0000000..651f3f6 + op[3] = val >> 24; + break; + ++ case BFD_RELOC_RL78_HI8: ++ val = val >> 16; ++ op[0] = val; ++ break; ++ ++ case BFD_RELOC_RL78_HI16: ++ val = val >> 16; ++ op[0] = val; ++ op[1] = val >> 8; ++ break; ++ ++ case BFD_RELOC_RL78_LO16: ++ op[0] = val; ++ op[1] = val >> 8; ++ break; ++ + default: + as_bad (_("Unknown reloc in md_apply_fix: %s"), + bfd_get_reloc_code_name (f->fx_r_type)); @@ -612633,23 +615959,14 @@ index 0000000..651f3f6 + int align = bfd_get_section_alignment (stdoutput, segment); + return ((size + (1 << align) - 1) & (-1 << align)); +} -+ -+void -+md_convert_frag (bfd * abfd ATTRIBUTE_UNUSED, -+ segT segment ATTRIBUTE_UNUSED, -+ fragS * fragP ATTRIBUTE_UNUSED) -+{ -+ /* No relaxation yet */ -+ fragP->fr_var = 0; -+} diff --git a/gas/config/tc-rl78.h b/gas/config/tc-rl78.h new file mode 100644 -index 0000000..67f12c9 +index 0000000..5b6a312 --- /dev/null +++ b/gas/config/tc-rl78.h -@@ -0,0 +1,81 @@ +@@ -0,0 +1,84 @@ +/* tc-rl78.h - header file for Renesas RL78 -+ Copyright 2011-2013 Free Software Foundation, Inc. ++ Copyright (C) 2011-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -612699,6 +616016,9 @@ index 0000000..67f12c9 +#define md_end rl78_md_end +extern void rl78_md_end (void); + ++#define md_relax_frag rl78_relax_frag ++extern int rl78_relax_frag (segT, fragS *, long); ++ +#define TC_FRAG_TYPE struct rl78_bytesT * +#define TC_FRAG_INIT rl78_frag_init +extern void rl78_frag_init (fragS *); @@ -612714,7 +616034,7 @@ index 0000000..67f12c9 + rl78_validate_fix_sub (FIX) +extern int rl78_validate_fix_sub (struct fix *); + -+#define TC_CONS_FIX_NEW(FRAG, WHERE, NBYTES, EXP) \ ++#define TC_CONS_FIX_NEW(FRAG, WHERE, NBYTES, EXP, RET) \ + rl78_cons_fix_new (FRAG, WHERE, NBYTES, EXP) +extern void rl78_cons_fix_new (fragS *, int, int, expressionS *); + @@ -612731,12 +616051,12 @@ index 0000000..67f12c9 +extern void rl78_elf_final_processing (void); diff --git a/gas/config/tc-rx.c b/gas/config/tc-rx.c new file mode 100644 -index 0000000..0e4b7a8 +index 0000000..c4842f9 --- /dev/null +++ b/gas/config/tc-rx.c -@@ -0,0 +1,2690 @@ +@@ -0,0 +1,2689 @@ +/* tc-rx.c -- Assembler for the Renesas RX -+ Copyright 2008-2013 Free Software Foundation, Inc. ++ Copyright (C) 2008-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -614907,10 +618227,9 @@ index 0000000..0e4b7a8 +rx_cons_fix_new (fragS * frag, + int where, + int size, -+ expressionS * exp) ++ expressionS * exp, ++ bfd_reloc_code_real_type type) +{ -+ bfd_reloc_code_real_type type; -+ + switch (size) + { + case 1: @@ -615427,13 +618746,12 @@ index 0000000..0e4b7a8 +} diff --git a/gas/config/tc-rx.h b/gas/config/tc-rx.h new file mode 100644 -index 0000000..6f2db1c +index 0000000..b82812d --- /dev/null +++ b/gas/config/tc-rx.h @@ -0,0 +1,105 @@ +/* tc-rx.h - header file for Renesas RX -+ Copyright 2008, 2009 -+ Free Software Foundation, Inc. ++ Copyright (C) 2008-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -615502,9 +618820,10 @@ index 0000000..6f2db1c + rx_validate_fix_sub (FIX) +extern int rx_validate_fix_sub (struct fix *); + -+#define TC_CONS_FIX_NEW(FRAG, WHERE, NBYTES, EXP) \ -+ rx_cons_fix_new (FRAG, WHERE, NBYTES, EXP) -+extern void rx_cons_fix_new (fragS *, int, int, expressionS *); ++#define TC_CONS_FIX_NEW(FRAG, WHERE, NBYTES, EXP, RELOC) \ ++ rx_cons_fix_new (FRAG, WHERE, NBYTES, EXP, RELOC) ++extern void rx_cons_fix_new (fragS *, int, int, expressionS *, ++ bfd_reloc_code_real_type); + +#define tc_fix_adjustable(x) 0 + @@ -615538,13 +618857,12 @@ index 0000000..6f2db1c +extern void rx_start_line (void); diff --git a/gas/config/tc-s390.c b/gas/config/tc-s390.c new file mode 100644 -index 0000000..c504f18 +index 0000000..59f6ab6 --- /dev/null +++ b/gas/config/tc-s390.c -@@ -0,0 +1,2519 @@ +@@ -0,0 +1,2518 @@ +/* tc-s390.c -- Assemble for the S390 -+ Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009, 2010 Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). + + This file is part of GAS, the GNU Assembler. @@ -618063,13 +621381,12 @@ index 0000000..c504f18 +} diff --git a/gas/config/tc-s390.h b/gas/config/tc-s390.h new file mode 100644 -index 0000000..f896e44 +index 0000000..88c857b --- /dev/null +++ b/gas/config/tc-s390.h -@@ -0,0 +1,101 @@ +@@ -0,0 +1,100 @@ +/* tc-s390.h -- Header file for tc-s390.c. -+ Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 -+ Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + Written by Martin Schwidefsky (schwidefsky@de.ibm.com). + + This file is part of GAS, the GNU Assembler. @@ -618170,12 +621487,12 @@ index 0000000..f896e44 +#define elf_tc_final_processing s390_elf_final_processing diff --git a/gas/config/tc-score.c b/gas/config/tc-score.c new file mode 100644 -index 0000000..822b9cf +index 0000000..6242b8c --- /dev/null +++ b/gas/config/tc-score.c @@ -0,0 +1,7836 @@ +/* tc-score.c -- Assembler for Score -+ Copyright 2006, 2007, 2008, 2009, 2011, 2012 Free Software Foundation, Inc. ++ Copyright (C) 2006-2014 Free Software Foundation, Inc. + Contributed by: + Brain.lin (brain.lin@sunplusct.com) + Mei Ligang (ligang@sunnorth.com.cn) @@ -623539,7 +626856,7 @@ index 0000000..822b9cf + || ((pec_part_1.size == s3_INSN16_SIZE) && (s3_inst.size == s3_INSN_SIZE))) + { + s3_inst.error = _("pce instruction error (16 bit || 16 bit)'"); -+ sprintf (s3_inst.str, insnstr); ++ sprintf (s3_inst.str, "%s", insnstr); + return; + } + @@ -626012,12 +629329,12 @@ index 0000000..822b9cf +} diff --git a/gas/config/tc-score.h b/gas/config/tc-score.h new file mode 100644 -index 0000000..b46ef79 +index 0000000..5b11f30 --- /dev/null +++ b/gas/config/tc-score.h @@ -0,0 +1,78 @@ +/* tc-score.h -- Score specific file for assembler -+ Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc. ++ Copyright (C) 2006-2014 Free Software Foundation, Inc. + Contributed by: + Brain.lin (brain.lin@sunplusct.com) + Mei Ligang (ligang@sunnorth.com.cn) @@ -626096,12 +629413,12 @@ index 0000000..b46ef79 +#endif /*TC_SCORE */ diff --git a/gas/config/tc-score7.c b/gas/config/tc-score7.c new file mode 100644 -index 0000000..520bd07 +index 0000000..0a0db2d --- /dev/null +++ b/gas/config/tc-score7.c @@ -0,0 +1,6972 @@ +/* tc-score7.c -- Assembler for Score7 -+ Copyright 2009, 2011, 2012 Free Software Foundation, Inc. ++ Copyright (C) 2009-2014 Free Software Foundation, Inc. + Contributed by: + Brain.lin (brain.lin@sunplusct.com) + Mei Ligang (ligang@sunnorth.com.cn) @@ -633074,14 +636391,12 @@ index 0000000..520bd07 +} diff --git a/gas/config/tc-sh.c b/gas/config/tc-sh.c new file mode 100644 -index 0000000..6b7bd5a +index 0000000..a0cd212 --- /dev/null +++ b/gas/config/tc-sh.c -@@ -0,0 +1,4642 @@ +@@ -0,0 +1,4641 @@ +/* tc-sh.c -- Assemble code for the Renesas / SuperH SH -+ Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, -+ 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1993-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -633847,9 +637162,10 @@ index 0000000..6b7bd5a +/* Add expression EXP of SIZE bytes to offset OFF of fragment FRAG. */ + +void -+sh_cons_fix_new (fragS *frag, int off, int size, expressionS *exp) ++sh_cons_fix_new (fragS *frag, int off, int size, expressionS *exp, ++ bfd_reloc_code_real_type r_type) +{ -+ bfd_reloc_code_real_type r_type = BFD_RELOC_UNUSED; ++ r_type = BFD_RELOC_UNUSED; + + if (sh_check_fixup (exp, &r_type)) + as_bad (_("Invalid PIC expression.")); @@ -637722,13 +641038,12 @@ index 0000000..6b7bd5a +#endif /* OBJ_ELF */ diff --git a/gas/config/tc-sh.h b/gas/config/tc-sh.h new file mode 100644 -index 0000000..2a69627 +index 0000000..97b6b6d --- /dev/null +++ b/gas/config/tc-sh.h @@ -0,0 +1,259 @@ +/* This file is tc-sh.h -+ Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, -+ 2003, 2004, 2005, 2006, 2007, 2008, 2010 Free Software Foundation, Inc. ++ Copyright (C) 1993-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -637961,9 +641276,10 @@ index 0000000..2a69627 +int sh_parse_name (char const *, expressionS *, + enum expr_mode, char *); + -+#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP) \ -+ sh_cons_fix_new ((FRAG), (OFF), (LEN), (EXP)) -+void sh_cons_fix_new (fragS *, int, int, expressionS *); ++#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP, RELOC) \ ++ sh_cons_fix_new ((FRAG), (OFF), (LEN), (EXP), (RELOC)) ++void sh_cons_fix_new (fragS *, int, int, expressionS *, ++ bfd_reloc_code_real_type); + +/* This is used to construct expressions out of @GOTOFF, @PLT and @GOT + symbols. The relocation type is stored in X_md. */ @@ -637987,13 +641303,12 @@ index 0000000..2a69627 +#define H_TICK_HEX 1 diff --git a/gas/config/tc-sh64.c b/gas/config/tc-sh64.c new file mode 100644 -index 0000000..db69846 +index 0000000..eba0a5b --- /dev/null +++ b/gas/config/tc-sh64.c -@@ -0,0 +1,3528 @@ +@@ -0,0 +1,3527 @@ +/* tc-sh64.c -- Assemble code for the SuperH SH SHcompact and SHmedia. -+ Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 -+ Free Software Foundation. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -641521,13 +644836,12 @@ index 0000000..db69846 +} diff --git a/gas/config/tc-sh64.h b/gas/config/tc-sh64.h new file mode 100644 -index 0000000..e01b3de +index 0000000..35702a0 --- /dev/null +++ b/gas/config/tc-sh64.h -@@ -0,0 +1,228 @@ +@@ -0,0 +1,227 @@ +/* This file is tc-sh64.h -+ Copyright 2000, 2001, 2002, 2003, 2005, 2007, 2008 -+ Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -641755,12 +645069,12 @@ index 0000000..e01b3de +extern int sh64_fake_label (const char *); diff --git a/gas/config/tc-sparc.c b/gas/config/tc-sparc.c new file mode 100644 -index 0000000..bcb8464 +index 0000000..5b0baad --- /dev/null +++ b/gas/config/tc-sparc.c -@@ -0,0 +1,4794 @@ +@@ -0,0 +1,4790 @@ +/* tc-sparc.c -- Assemble for the SPARC -+ Copyright 1989-2013 Free Software Foundation, Inc. ++ Copyright (C) 1989-2014 Free Software Foundation, Inc. + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify @@ -642548,6 +645862,8 @@ index 0000000..bcb8464 + {"hintp", 3}, + {"htba", 5}, + {"hver", 6}, ++ {"hstick_offset", 28}, ++ {"hstick_enable", 29}, + {"hstick_cmpr", 31}, + {"", -1}, /* End marker. */ +}; @@ -646027,11 +649343,6 @@ index 0000000..bcb8464 + +static int sparc_no_align_cons = 0; + -+/* This static variable is set by sparc_cons to emit requested types -+ of relocations in cons_fix_new_sparc. */ -+ -+static const char *sparc_cons_special_reloc; -+ +/* This handles the unaligned space allocation pseudo-ops, such as + .uaword. .uaword is just like .word, but the value does not need + to be aligned. */ @@ -646299,13 +649610,13 @@ index 0000000..bcb8464 + elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3; +} + -+void ++const char * +sparc_cons (expressionS *exp, int size) +{ + char *save; ++ const char *sparc_cons_special_reloc = NULL; + + SKIP_WHITESPACE (); -+ sparc_cons_special_reloc = NULL; + save = input_line_pointer; + if (input_line_pointer[0] == '%' + && input_line_pointer[1] == 'r' @@ -646432,6 +649743,7 @@ index 0000000..bcb8464 + } + if (sparc_cons_special_reloc == NULL) + expression (exp); ++ return sparc_cons_special_reloc; +} + +#endif @@ -646444,7 +649756,8 @@ index 0000000..bcb8464 +cons_fix_new_sparc (fragS *frag, + int where, + unsigned int nbytes, -+ expressionS *exp) ++ expressionS *exp, ++ const char *sparc_cons_special_reloc) +{ + bfd_reloc_code_real_type r; + @@ -646493,7 +649806,6 @@ index 0000000..bcb8464 + } + + fix_new_exp (frag, where, (int) nbytes, exp, 0, r); -+ sparc_cons_special_reloc = NULL; +} + +void @@ -646547,22 +649859,18 @@ index 0000000..bcb8464 +void +sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes) +{ -+ sparc_cons_special_reloc = "disp"; + sparc_no_align_cons = 1; -+ emit_expr (exp, nbytes); ++ emit_expr_with_reloc (exp, nbytes, "disp"); + sparc_no_align_cons = 0; -+ sparc_cons_special_reloc = NULL; +} diff --git a/gas/config/tc-sparc.h b/gas/config/tc-sparc.h new file mode 100644 -index 0000000..5671c14 +index 0000000..ef76c0b --- /dev/null +++ b/gas/config/tc-sparc.h -@@ -0,0 +1,203 @@ +@@ -0,0 +1,204 @@ +/* tc-sparc.h - Macros and type defines for the sparc. -+ Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, -+ 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2010 -+ Free Software Foundation, Inc. ++ Copyright (C) 1989-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -646718,14 +650026,17 @@ index 0000000..5671c14 + +#endif + ++#define TC_PARSE_CONS_RETURN_TYPE const char * ++#define TC_PARSE_CONS_RETURN_NONE NULL ++ +#ifdef OBJ_ELF +#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) sparc_cons (EXP, NBYTES) -+extern void sparc_cons (expressionS *, int); ++extern const char *sparc_cons (expressionS *, int); +#endif + +#define TC_CONS_FIX_NEW cons_fix_new_sparc +extern void cons_fix_new_sparc -+ (struct frag *, int, unsigned int, struct expressionS *); ++(struct frag *, int, unsigned int, struct expressionS *, const char *); + +#define TC_FIX_TYPE valueT + @@ -646764,13 +650075,13 @@ index 0000000..5671c14 +/* end of tc-sparc.h */ diff --git a/gas/config/tc-spu.c b/gas/config/tc-spu.c new file mode 100644 -index 0000000..d80c621 +index 0000000..717cc33 --- /dev/null +++ b/gas/config/tc-spu.c @@ -0,0 +1,1100 @@ +/* spu.c -- Assembler for the IBM Synergistic Processing Unit (SPU) + -+ Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc. ++ Copyright (C) 2006-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -647870,13 +651181,13 @@ index 0000000..d80c621 +} diff --git a/gas/config/tc-spu.h b/gas/config/tc-spu.h new file mode 100644 -index 0000000..5047d35 +index 0000000..0839344 --- /dev/null +++ b/gas/config/tc-spu.h @@ -0,0 +1,109 @@ +/* spu.h -- Assembler for spu + -+ Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc. ++ Copyright (C) 2006-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -647985,13 +651296,12 @@ index 0000000..5047d35 +#endif /* TC_SPU */ diff --git a/gas/config/tc-tic30.c b/gas/config/tc-tic30.c new file mode 100644 -index 0000000..5474df5 +index 0000000..dbcbf3c --- /dev/null +++ b/gas/config/tc-tic30.c -@@ -0,0 +1,2003 @@ +@@ -0,0 +1,2002 @@ +/* tc-c30.c -- Assembly code for the Texas Instruments TMS320C30 -+ Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2009, 2014 -+ Free Software Foundation, Inc. ++ Copyright (C) 1998-2014 Free Software Foundation, Inc. + Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au) + + This file is part of GAS, the GNU Assembler. @@ -649994,12 +653304,12 @@ index 0000000..5474df5 +} diff --git a/gas/config/tc-tic30.h b/gas/config/tc-tic30.h new file mode 100644 -index 0000000..a5ec412 +index 0000000..e39d7b0 --- /dev/null +++ b/gas/config/tc-tic30.h @@ -0,0 +1,51 @@ +/* tc-tic30.h -- Header file for tc-tic30.c -+ Copyright 1998, 2000, 2002, 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 1998-2014 Free Software Foundation, Inc. + Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au) + + This file is part of GAS, the GNU Assembler. @@ -650051,13 +653361,12 @@ index 0000000..a5ec412 +#endif diff --git a/gas/config/tc-tic4x.c b/gas/config/tc-tic4x.c new file mode 100644 -index 0000000..dd21000 +index 0000000..7559ad5 --- /dev/null +++ b/gas/config/tc-tic4x.c -@@ -0,0 +1,3039 @@ +@@ -0,0 +1,3038 @@ +/* tc-tic4x.c -- Assemble for the Texas Instruments TMS320C[34]x. -+ Copyright (C) 1997,1998, 2002, 2003, 2005, 2006, 2007, 2008, 2009, 2010, -+ 2012 Free Software Foundation. Inc. ++ Copyright (C) 1997-2014 Free Software Foundation, Inc. + + Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz) + @@ -650139,7 +653448,7 @@ index 0000000..dd21000 +#define OPTION_ENHANCED (OPTION_MD_BASE + 7) +#define OPTION_REV (OPTION_MD_BASE + 8) + -+CONST char *md_shortopts = "bm:prs"; ++const char *md_shortopts = "bm:prs"; +struct option md_longopts[] = +{ + { "mcpu", required_argument, NULL, OPTION_CPU }, @@ -653096,13 +656405,12 @@ index 0000000..dd21000 +} diff --git a/gas/config/tc-tic4x.h b/gas/config/tc-tic4x.h new file mode 100644 -index 0000000..b35eaa7 +index 0000000..14b3511 --- /dev/null +++ b/gas/config/tc-tic4x.h -@@ -0,0 +1,94 @@ +@@ -0,0 +1,93 @@ +/* tc-tic4x.h -- Assemble for the Texas TMS320C[34]X. -+ Copyright (C) 1997, 2002, 2003, 2005, 2007, 2008 -+ Free Software Foundation. Inc. ++ Copyright (C) 1997-2014 Free Software Foundation, Inc. + + Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz) + @@ -653196,13 +656504,12 @@ index 0000000..b35eaa7 + diff --git a/gas/config/tc-tic54x.c b/gas/config/tc-tic54x.c new file mode 100644 -index 0000000..d4bd75f +index 0000000..bba743c --- /dev/null +++ b/gas/config/tc-tic54x.c -@@ -0,0 +1,5410 @@ +@@ -0,0 +1,5408 @@ +/* tc-tic54x.c -- Assembly code for the Texas Instruments TMS320C54X -+ Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+ 2009, 2010, 2012 Free Software Foundation, Inc. ++ Copyright (C) 1999-2014 Free Software Foundation, Inc. + Contributed by Timothy Wall (twall@cygnus.com) + + This file is part of GAS, the GNU Assembler. @@ -658324,10 +661631,9 @@ index 0000000..d4bd75f +/* Handle cons expressions. */ + +void -+tic54x_cons_fix_new (fragS *frag, int where, int octets, expressionS *expn) ++tic54x_cons_fix_new (fragS *frag, int where, int octets, expressionS *expn, ++ bfd_reloc_code_real_type r) +{ -+ bfd_reloc_code_real_type r; -+ + switch (octets) + { + default: @@ -658612,12 +661918,12 @@ index 0000000..d4bd75f +} diff --git a/gas/config/tc-tic54x.h b/gas/config/tc-tic54x.h new file mode 100644 -index 0000000..93342de +index 0000000..3fe8be8 --- /dev/null +++ b/gas/config/tc-tic54x.h -@@ -0,0 +1,126 @@ +@@ -0,0 +1,128 @@ +/* tc-tic54x.h -- Header file for tc-tic54x.c -+ Copyright 1999, 2000, 2001, 2005, 2007, 2008 Free Software Foundation, Inc. ++ Copyright (C) 1999-2014 Free Software Foundation, Inc. + Contributed by Timothy Wall (twall@alum.mit.edu) + + This file is part of GAS, the GNU Assembler. @@ -658687,8 +661993,10 @@ index 0000000..93342de +extern int tic54x_start_label (int, char *); + +/* custom handling for relocations in cons expressions */ -+#define TC_CONS_FIX_NEW(FRAG,OFF,LEN,EXP) tic54x_cons_fix_new(FRAG,OFF,LEN,EXP) -+extern void tic54x_cons_fix_new (fragS *,int,int,expressionS *); ++#define TC_CONS_FIX_NEW(FRAG, OFF, LEN, EXP, RELOC) \ ++ tic54x_cons_fix_new (FRAG, OFF, LEN, EXP, RELOC) ++extern void tic54x_cons_fix_new (fragS *, int, int, expressionS *, ++ bfd_reloc_code_real_type); + +/* Define md_number_to_chars as the appropriate standard big endian or + little endian function. Mostly littleendian, but longwords and floats are @@ -658744,12 +662052,12 @@ index 0000000..93342de +#endif diff --git a/gas/config/tc-tic6x.c b/gas/config/tc-tic6x.c new file mode 100644 -index 0000000..81f33f4 +index 0000000..aca07d3 --- /dev/null +++ b/gas/config/tc-tic6x.c -@@ -0,0 +1,5376 @@ +@@ -0,0 +1,5375 @@ +/* TI C6X assembler. -+ Copyright 2010-2013 Free Software Foundation, Inc. ++ Copyright (C) 2010-2014 Free Software Foundation, Inc. + Contributed by Joseph Myers + Bernd Schmidt + @@ -660762,10 +664070,9 @@ index 0000000..81f33f4 + go through the error checking in tic6x_fix_new_exp. */ + +void -+tic6x_cons_fix_new (fragS *frag, int where, int size, expressionS *exp) ++tic6x_cons_fix_new (fragS *frag, int where, int size, expressionS *exp, ++ bfd_reloc_code_real_type r_type) +{ -+ bfd_reloc_code_real_type r_type; -+ + switch (size) + { + case 1: @@ -664126,13 +667433,12 @@ index 0000000..81f33f4 +} diff --git a/gas/config/tc-tic6x.h b/gas/config/tc-tic6x.h new file mode 100644 -index 0000000..12bdead +index 0000000..dc110e8 --- /dev/null +++ b/gas/config/tc-tic6x.h -@@ -0,0 +1,228 @@ +@@ -0,0 +1,227 @@ +/* Definitions for TI C6X assembler. -+ Copyright 2010 -+ Free Software Foundation, Inc. ++ Copyright (C) 2010-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -664317,10 +667623,10 @@ index 0000000..12bdead +#define md_start_line_hook() tic6x_start_line_hook () +extern void tic6x_start_line_hook (void); + -+#define TC_CONS_FIX_NEW(frag, where, size, exp) \ -+ tic6x_cons_fix_new (frag, where, size, exp) -+extern void tic6x_cons_fix_new (fragS *frag, int where, int size, -+ expressionS *exp); ++#define TC_CONS_FIX_NEW(frag, where, size, exp, reloc) \ ++ tic6x_cons_fix_new (frag, where, size, exp, reloc) ++extern void tic6x_cons_fix_new (fragS *, int, int, expressionS *, ++ bfd_reloc_code_real_type); + +#define tc_fix_adjustable(FIX) tic6x_fix_adjustable (FIX) +extern bfd_boolean tic6x_fix_adjustable (struct fix *); @@ -664360,12 +667666,12 @@ index 0000000..12bdead +#define tc_cfi_section_name ".c6xabi.exidx" diff --git a/gas/config/tc-tilegx.c b/gas/config/tc-tilegx.c new file mode 100644 -index 0000000..19a04c2 +index 0000000..3176d2f --- /dev/null +++ b/gas/config/tc-tilegx.c @@ -0,0 +1,1895 @@ +/* tc-tilegx.c -- Assemble for a Tile-Gx chip. -+ Copyright 2011 Free Software Foundation, Inc. ++ Copyright (C) 2011-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -666261,12 +669567,12 @@ index 0000000..19a04c2 +} diff --git a/gas/config/tc-tilegx.h b/gas/config/tc-tilegx.h new file mode 100644 -index 0000000..ec8a40d +index 0000000..6de89da --- /dev/null +++ b/gas/config/tc-tilegx.h @@ -0,0 +1,93 @@ +/* tc-tilegx.h - Macros and type defines for a TILE-Gx chip. -+ Copyright 2011 Free Software Foundation, Inc. ++ Copyright (C) 2011-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -666320,7 +669626,7 @@ index 0000000..ec8a40d + +extern void tilegx_cons_fix_new (struct frag *, int, + int, struct expressionS *); -+#define TC_CONS_FIX_NEW(FRAG, WHERE, NBYTES, EXP) \ ++#define TC_CONS_FIX_NEW(FRAG, WHERE, NBYTES, EXP, RELOC) \ + tilegx_cons_fix_new (FRAG, WHERE, NBYTES, EXP) + +extern int tilegx_parse_name (char *, expressionS *, char *); @@ -666360,12 +669666,12 @@ index 0000000..ec8a40d +#endif /* TC_TILEGX */ diff --git a/gas/config/tc-tilepro.c b/gas/config/tc-tilepro.c new file mode 100644 -index 0000000..733a628 +index 0000000..8a378c0 --- /dev/null +++ b/gas/config/tc-tilepro.c @@ -0,0 +1,1677 @@ +/* tc-tilepro.c -- Assemble for a TILEPro chip. -+ Copyright 2011 Free Software Foundation, Inc. ++ Copyright (C) 2011-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -668043,12 +671349,12 @@ index 0000000..733a628 +} diff --git a/gas/config/tc-tilepro.h b/gas/config/tc-tilepro.h new file mode 100644 -index 0000000..5374d26 +index 0000000..92d31b1 --- /dev/null +++ b/gas/config/tc-tilepro.h @@ -0,0 +1,93 @@ +/* tc-tile.h - Macros and type defines for a TILEPro chip. -+ Copyright 2011 Free Software Foundation, Inc. ++ Copyright (C) 2011-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -668103,7 +671409,7 @@ index 0000000..5374d26 +extern void tilepro_cons_fix_new (struct frag *, int, + int, struct expressionS *); + -+#define TC_CONS_FIX_NEW(FRAG, WHERE, NBYTES, EXP) \ ++#define TC_CONS_FIX_NEW(FRAG, WHERE, NBYTES, EXP, RELOC) \ + tilepro_cons_fix_new (FRAG, WHERE, NBYTES, EXP) + +extern int tilepro_parse_name (char *, expressionS *, char *); @@ -668142,12 +671448,12 @@ index 0000000..5374d26 +#endif /* TC_TILEPRO */ diff --git a/gas/config/tc-v850.c b/gas/config/tc-v850.c new file mode 100644 -index 0000000..a23387c +index 0000000..91acec4 --- /dev/null +++ b/gas/config/tc-v850.c -@@ -0,0 +1,3713 @@ +@@ -0,0 +1,3718 @@ +/* tc-v850.c -- Assembler code for the NEC V850 -+ Copyright 1996-2013 Free Software Foundation, Inc. ++ Copyright (C) 1996-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -668175,9 +671481,6 @@ index 0000000..a23387c +/* Sign-extend a 16-bit number. */ +#define SEXT16(x) ((((x) & 0xffff) ^ (~0x7fff)) + 0x8000) + -+/* Temporarily holds the reloc in a cons expression. */ -+static bfd_reloc_code_real_type hold_cons_reloc = BFD_RELOC_UNUSED; -+ +/* Set to TRUE if we want to be pedantic about signed overflows. */ +static bfd_boolean warn_signed_overflows = FALSE; +static bfd_boolean warn_unsigned_overflows = FALSE; @@ -670180,6 +673483,12 @@ index 0000000..a23387c +static bfd_reloc_code_real_type +handle_ctoff (const struct v850_operand *operand, const char **errmsg) +{ ++ if (v850_target_arch == bfd_arch_v850_rh850) ++ { ++ *errmsg = _("ctoff() is not supported by the rh850 ABI. Use -mgcc-abi instead"); ++ return BFD_RELOC_64; /* Used to indicate an error condition. */ ++ } ++ + if (operand == NULL) + return BFD_RELOC_V850_CALLT_16_16_OFFSET; + @@ -670304,7 +673613,7 @@ index 0000000..a23387c + if (paren_skipped) + --input_line_pointer; + -+ return BFD_RELOC_UNUSED; ++ return BFD_RELOC_NONE; +} + +/* Insert an operand value into an instruction. */ @@ -670555,7 +673864,7 @@ index 0000000..a23387c + input_line_pointer = str; + + /* lo(), hi(), hi0(), etc... */ -+ if ((reloc = v850_reloc_prefix (operand, &errmsg)) != BFD_RELOC_UNUSED) ++ if ((reloc = v850_reloc_prefix (operand, &errmsg)) != BFD_RELOC_NONE) + { + /* This is a fake reloc, used to indicate an error condition. */ + if (reloc == BFD_RELOC_64) @@ -671125,7 +674434,7 @@ index 0000000..a23387c + + fixups[fc].exp = ex; + fixups[fc].opindex = *opindex_ptr; -+ fixups[fc].reloc = BFD_RELOC_UNUSED; ++ fixups[fc].reloc = BFD_RELOC_NONE; + ++fc; + break; + } @@ -671387,7 +674696,7 @@ index 0000000..a23387c + + reloc = fixups[i].reloc; + -+ if (reloc != BFD_RELOC_UNUSED) ++ if (reloc != BFD_RELOC_NONE) + { + reloc_howto_type *reloc_howto = + bfd_reloc_type_lookup (stdoutput, reloc); @@ -671782,15 +675091,18 @@ index 0000000..a23387c +/* Parse a cons expression. We have to handle hi(), lo(), etc + on the v850. */ + -+void ++bfd_reloc_code_real_type +parse_cons_expression_v850 (expressionS *exp) +{ + const char *errmsg; ++ bfd_reloc_code_real_type r; ++ + /* See if there's a reloc prefix like hi() we have to handle. */ -+ hold_cons_reloc = v850_reloc_prefix (NULL, &errmsg); ++ r = v850_reloc_prefix (NULL, &errmsg); + + /* Do normal expression parsing. */ + expression (exp); ++ return r; +} + +/* Create a fixup for a cons expression. If parse_cons_expression_v850 @@ -671801,24 +675113,23 @@ index 0000000..a23387c +cons_fix_new_v850 (fragS *frag, + int where, + int size, -+ expressionS *exp) ++ expressionS *exp, ++ bfd_reloc_code_real_type r) +{ -+ if (hold_cons_reloc == BFD_RELOC_UNUSED) ++ if (r == BFD_RELOC_NONE) + { + if (size == 4) -+ hold_cons_reloc = BFD_RELOC_32; ++ r = BFD_RELOC_32; + if (size == 2) -+ hold_cons_reloc = BFD_RELOC_16; ++ r = BFD_RELOC_16; + if (size == 1) -+ hold_cons_reloc = BFD_RELOC_8; ++ r = BFD_RELOC_8; + } + + if (exp != NULL) -+ fix_new_exp (frag, where, size, exp, 0, hold_cons_reloc); ++ fix_new_exp (frag, where, size, exp, 0, r); + else -+ fix_new (frag, where, size, NULL, 0, 0, hold_cons_reloc); -+ -+ hold_cons_reloc = BFD_RELOC_UNUSED; ++ fix_new (frag, where, size, NULL, 0, 0, r); +} + +bfd_boolean @@ -671861,13 +675172,12 @@ index 0000000..a23387c +} diff --git a/gas/config/tc-v850.h b/gas/config/tc-v850.h new file mode 100644 -index 0000000..2762770 +index 0000000..a0aeeb4 --- /dev/null +++ b/gas/config/tc-v850.h @@ -0,0 +1,86 @@ +/* tc-v850.h -- Header file for tc-v850.c. -+ Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1996-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -671926,10 +675236,11 @@ index 0000000..2762770 +/* We need to handle lo(), hi(), etc etc in .hword, .word, etc + directives, so we have to parse "cons" expressions ourselves. */ +#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) parse_cons_expression_v850 (EXP) -+extern void parse_cons_expression_v850 (expressionS *); ++extern bfd_reloc_code_real_type parse_cons_expression_v850 (expressionS *); + +#define TC_CONS_FIX_NEW cons_fix_new_v850 -+extern void cons_fix_new_v850 (fragS *, int, int, expressionS *); ++extern void cons_fix_new_v850 (fragS *, int, int, expressionS *, ++ bfd_reloc_code_real_type); + +#define TC_GENERIC_RELAX_TABLE md_relax_table +extern const struct relax_type md_relax_table[]; @@ -671953,14 +675264,12 @@ index 0000000..2762770 +#define TC_INIT_FIX_DATA(fixP) (fixP)->tc_fix_data = NULL diff --git a/gas/config/tc-vax.c b/gas/config/tc-vax.c new file mode 100644 -index 0000000..185a9a2 +index 0000000..0740a9b --- /dev/null +++ b/gas/config/tc-vax.c -@@ -0,0 +1,3413 @@ +@@ -0,0 +1,3404 @@ +/* tc-vax.c - vax-specific - -+ Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1998, 2000, 2001, 2002, -+ 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -675225,12 +678534,11 @@ index 0000000..185a9a2 + } +} + -+static char *vax_cons_special_reloc; -+ -+void ++bfd_reloc_code_real_type +vax_cons (expressionS *exp, int size) +{ + char *save; ++ char *vax_cons_special_reloc; + + SKIP_WHITESPACE (); + vax_cons_special_reloc = NULL; @@ -675334,35 +678642,29 @@ index 0000000..185a9a2 + } + if (vax_cons_special_reloc == NULL) + expression (exp); ++ else ++ switch (size) ++ { ++ case 1: return BFD_RELOC_8_PCREL; ++ case 2: return BFD_RELOC_16_PCREL; ++ case 4: return BFD_RELOC_32_PCREL; ++ } ++ return BFD_RELOC_NONE; +} + +/* This is called by emit_expr via TC_CONS_FIX_NEW when creating a + reloc for a cons. */ + +void -+vax_cons_fix_new (fragS *frag, int where, unsigned int nbytes, expressionS *exp) ++vax_cons_fix_new (fragS *frag, int where, unsigned int nbytes, expressionS *exp, ++ bfd_reloc_code_real_type r) +{ -+ bfd_reloc_code_real_type r; -+ -+ r = (nbytes == 1 ? BFD_RELOC_8 : -+ (nbytes == 2 ? BFD_RELOC_16 : BFD_RELOC_32)); -+ -+ if (vax_cons_special_reloc) -+ { -+ if (*vax_cons_special_reloc == 'p') -+ { -+ switch (nbytes) -+ { -+ case 1: r = BFD_RELOC_8_PCREL; break; -+ case 2: r = BFD_RELOC_16_PCREL; break; -+ case 4: r = BFD_RELOC_32_PCREL; break; -+ default: abort (); -+ } -+ } -+ } ++ if (r == BFD_RELOC_NONE) ++ r = (nbytes == 1 ? BFD_RELOC_8 ++ : nbytes == 2 ? BFD_RELOC_16 ++ : BFD_RELOC_32); + + fix_new_exp (frag, where, (int) nbytes, exp, 0, r); -+ vax_cons_special_reloc = NULL; +} + +char * @@ -675372,13 +678674,12 @@ index 0000000..185a9a2 +} diff --git a/gas/config/tc-vax.h b/gas/config/tc-vax.h new file mode 100644 -index 0000000..84722ff +index 0000000..cc94bb2 --- /dev/null +++ b/gas/config/tc-vax.h @@ -0,0 +1,79 @@ +/* tc-vax.h -- Header file for tc-vax.c. -+ Copyright 1987, 1991, 1992, 1993, 1995, 1996, 1997, 2000, 2002, 2005, -+ 2006, 2007 Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -675428,8 +678729,9 @@ index 0000000..84722ff +#ifdef OBJ_ELF +#define TC_PARSE_CONS_EXPRESSION(EXP, NBYTES) vax_cons (EXP, NBYTES) +#define TC_CONS_FIX_NEW vax_cons_fix_new -+void vax_cons (expressionS *, int); -+void vax_cons_fix_new (struct frag *, int, unsigned int, struct expressionS *); ++bfd_reloc_code_real_type vax_cons (expressionS *, int); ++void vax_cons_fix_new (struct frag *, int, unsigned int, struct expressionS *, ++ bfd_reloc_code_real_type); +#endif + +extern const struct relax_type md_relax_table[]; @@ -675457,12 +678759,12 @@ index 0000000..84722ff + */ diff --git a/gas/config/tc-xc16x.c b/gas/config/tc-xc16x.c new file mode 100644 -index 0000000..c628d86 +index 0000000..6073387 --- /dev/null +++ b/gas/config/tc-xc16x.c @@ -0,0 +1,349 @@ +/* tc-xc16x.c -- Assembler for the Infineon XC16X. -+ Copyright 2006, 2007, 2009 Free Software Foundation, Inc. ++ Copyright (C) 2006-2014 Free Software Foundation, Inc. + Contributed by KPIT Cummins Infosystems + + This file is part of GAS, the GNU Assembler. @@ -675812,12 +679114,12 @@ index 0000000..c628d86 +} diff --git a/gas/config/tc-xc16x.h b/gas/config/tc-xc16x.h new file mode 100644 -index 0000000..fa79a51 +index 0000000..03bfec9 --- /dev/null +++ b/gas/config/tc-xc16x.h @@ -0,0 +1,60 @@ +/* This file is tc-xc16x.h -+ Copyright 2006, 2007, 2014 Free Software Foundation, Inc. ++ Copyright (C) 2006-2014 Free Software Foundation, Inc. + Contributed by KPIT Cummins Infosystems + + This file is part of GAS, the GNU Assembler. @@ -675878,13 +679180,12 @@ index 0000000..fa79a51 +#define md_operand(x) diff --git a/gas/config/tc-xgate.c b/gas/config/tc-xgate.c new file mode 100644 -index 0000000..7ed1ef6 +index 0000000..f244c57 --- /dev/null +++ b/gas/config/tc-xgate.c -@@ -0,0 +1,1353 @@ +@@ -0,0 +1,1352 @@ +/* tc-xgate.c -- Assembler code for Freescale XGATE -+ Copyright 2010, 2011, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 2010-2014 Free Software Foundation, Inc. + Contributed by Sean Keys + + This file is part of GAS, the GNU Assembler. @@ -677237,12 +680538,12 @@ index 0000000..7ed1ef6 +} diff --git a/gas/config/tc-xgate.h b/gas/config/tc-xgate.h new file mode 100644 -index 0000000..04349a7 +index 0000000..30cff98 --- /dev/null +++ b/gas/config/tc-xgate.h @@ -0,0 +1,115 @@ +/* tc-xgate.h -- Header file for tc-xgate.c. -+ Copyright 2010, 2011, 2012 Free Software Foundation, Inc. ++ Copyright (C) 2010-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -677358,13 +680659,12 @@ index 0000000..04349a7 +#endif diff --git a/gas/config/tc-xstormy16.c b/gas/config/tc-xstormy16.c new file mode 100644 -index 0000000..74c5bce +index 0000000..e8eba89 --- /dev/null +++ b/gas/config/tc-xstormy16.c -@@ -0,0 +1,602 @@ +@@ -0,0 +1,600 @@ +/* tc-xstormy16.c -- Assembler for the Sanyo XSTORMY16. -+ Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2009, 2010 -+ Free Software Foundation. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -677558,10 +680858,9 @@ index 0000000..74c5bce +xstormy16_cons_fix_new (fragS *f, + int where, + int nbytes, -+ expressionS *exp) ++ expressionS *exp, ++ bfd_reloc_code_real_type code) +{ -+ bfd_reloc_code_real_type code; -+ + if (exp->X_op == O_fptr_symbol) + { + switch (nbytes) @@ -677966,12 +681265,12 @@ index 0000000..74c5bce +} diff --git a/gas/config/tc-xstormy16.h b/gas/config/tc-xstormy16.h new file mode 100644 -index 0000000..5e1fb86 +index 0000000..064a85c --- /dev/null +++ b/gas/config/tc-xstormy16.h -@@ -0,0 +1,68 @@ +@@ -0,0 +1,69 @@ +/* tc-xstormy16.h -- Header file for tc-xstormy16.c. -+ Copyright 2000, 2001, 2002, 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -678029,7 +681328,8 @@ index 0000000..5e1fb86 +extern long md_pcrel_from_section (struct fix *, segT); + +#define TC_CONS_FIX_NEW xstormy16_cons_fix_new -+extern void xstormy16_cons_fix_new (fragS *f, int, int, expressionS *); ++extern void xstormy16_cons_fix_new (fragS *f, int, int, expressionS *, ++ bfd_reloc_code_real_type); + +#define md_cgen_record_fixup_exp xstormy16_cgen_record_fixup_exp + @@ -678040,13 +681340,12 @@ index 0000000..5e1fb86 +#define TC_FX_SIZE_SLACK(FIX) 2 diff --git a/gas/config/tc-xtensa.c b/gas/config/tc-xtensa.c new file mode 100644 -index 0000000..7075531 +index 0000000..7547c0a --- /dev/null +++ b/gas/config/tc-xtensa.c -@@ -0,0 +1,12048 @@ +@@ -0,0 +1,12603 @@ +/* tc-xtensa.c -- Assemble Xtensa instructions. -+ Copyright 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 2003-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -678515,6 +681814,12 @@ index 0000000..7075531 +static void finish_vinsn (vliw_insn *); +static bfd_boolean emit_single_op (TInsn *); +static int total_frag_text_expansion (fragS *); ++static bfd_boolean use_trampolines = TRUE; ++static void xtensa_check_frag_count (void); ++static void xtensa_create_trampoline_frag (bfd_boolean); ++static void xtensa_maybe_create_trampoline_frag (void); ++struct trampoline_frag; ++static int init_trampoline_frag (struct trampoline_frag *); + +/* Alignment Functions. */ + @@ -678567,6 +681872,7 @@ index 0000000..7075531 +static void tinsn_immed_from_frag (TInsn *, fragS *, int); +static int get_num_stack_text_bytes (IStack *); +static int get_num_stack_literal_bytes (IStack *); ++static bfd_boolean tinsn_to_slotbuf (xtensa_format, int, TInsn *, xtensa_insnbuf); + +/* vliw_insn functions. */ + @@ -678734,7 +682040,10 @@ index 0000000..7075531 + option_prefer_l32r, + option_prefer_const16, + -+ option_target_hardware ++ option_target_hardware, ++ ++ option_trampolines, ++ option_no_trampolines, +}; + +const char *md_shortopts = ""; @@ -678807,6 +682116,9 @@ index 0000000..7075531 + + { "target-hardware", required_argument, NULL, option_target_hardware }, + ++ { "trampolines", no_argument, NULL, option_trampolines }, ++ { "no-trampolines", no_argument, NULL, option_no_trampolines }, ++ + { NULL, no_argument, NULL, 0 } +}; + @@ -678987,6 +682299,14 @@ index 0000000..7075531 + directive_state[directive_transform] = FALSE; + return 1; + ++ case option_trampolines: ++ use_trampolines = TRUE; ++ return 1; ++ ++ case option_no_trampolines: ++ use_trampolines = FALSE; ++ return 1; ++ + default: + return 0; + } @@ -679010,7 +682330,9 @@ index 0000000..7075531 + flix bundles\n\ + --no-allow-flix neither allow hand-written nor generate\n\ + flix bundles\n\ -+ --rename-section old=new Rename section 'old' to 'new'\n", stream); ++ --rename-section old=new Rename section 'old' to 'new'\n\ ++ --[no-]trampolines [Do not] generate trampolines (jumps to jumps)\n\ ++ when jumps do not reach their targets\n", stream); +} + + @@ -683615,6 +686937,8 @@ index 0000000..7075531 + + /* We've just emitted a new instruction so clear the list of labels. */ + xtensa_clear_insn_labels (); ++ ++ xtensa_check_frag_count (); +} + + @@ -683631,7 +686955,6 @@ index 0000000..7075531 + && ! fragP->tc_frag_data.is_literal + && (fragP->fr_type == rs_align + || fragP->fr_type == rs_align_code) -+ && fragP->fr_address + fragP->fr_fix > 0 + && fragP->fr_offset > 0 + && now_seg != bss_section) + { @@ -683890,12 +687213,15 @@ index 0000000..7075531 + { + case BFD_RELOC_8: + fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF8; ++ fixP->fx_signed = 1; + break; + case BFD_RELOC_16: + fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF16; ++ fixP->fx_signed = 1; + break; + case BFD_RELOC_32: + fixP->fx_r_type = BFD_RELOC_XTENSA_DIFF32; ++ fixP->fx_signed = 1; + break; + default: + break; @@ -684419,6 +687745,8 @@ index 0000000..7075531 + xg_assemble_vliw_tokens (vinsn); + + xg_clear_vinsn (vinsn); ++ ++ xtensa_check_frag_count (); +} + + @@ -685187,6 +688515,7 @@ index 0000000..7075531 + RELAX_UNREACHABLE, + frag_now->fr_symbol, frag_now->fr_offset, NULL); + xtensa_set_frag_assembly_state (frag_now); ++ xtensa_maybe_create_trampoline_frag (); + } + else if (is_branch && do_align_targets ()) + { @@ -685269,9 +688598,164 @@ index 0000000..7075531 + xtensa_sanity_check (); + + xtensa_add_config_info (); ++ ++ xtensa_check_frag_count (); +} + + ++struct trampoline_frag ++{ ++ struct trampoline_frag *next; ++ bfd_boolean needs_jump_around; ++ fragS *fragP; ++ fixS *fixP; ++}; ++ ++struct trampoline_seg ++{ ++ struct trampoline_seg *next; ++ asection *seg; ++ struct trampoline_frag trampoline_list; ++}; ++ ++static struct trampoline_seg trampoline_seg_list; ++#define J_RANGE (128 * 1024) ++ ++static int unreachable_count = 0; ++ ++ ++static void ++xtensa_maybe_create_trampoline_frag (void) ++{ ++ if (!use_trampolines) ++ return; ++ ++ /* We create an area for possible trampolines every 10 unreachable frags. ++ These are preferred over the ones not preceded by an unreachable frag, ++ because we don't have to jump around them. This function is called after ++ each RELAX_UNREACHABLE frag is created. */ ++ ++ if (++unreachable_count > 10) ++ { ++ xtensa_create_trampoline_frag (FALSE); ++ clear_frag_count (); ++ unreachable_count = 0; ++ } ++} ++ ++static void ++xtensa_check_frag_count (void) ++{ ++ if (!use_trampolines || frag_now->tc_frag_data.is_no_transform) ++ return; ++ ++ /* We create an area for possible trampolines every 8000 frags or so. This ++ is an estimate based on the max range of a "j" insn (+/-128K) divided ++ by a typical frag byte count (16), minus a few for safety. This function ++ is called after each source line is processed. */ ++ ++ if (get_frag_count () > 8000) ++ { ++ xtensa_create_trampoline_frag (TRUE); ++ clear_frag_count (); ++ unreachable_count = 0; ++ } ++} ++ ++static xtensa_insnbuf trampoline_buf = NULL; ++static xtensa_insnbuf trampoline_slotbuf = NULL; ++ ++#define TRAMPOLINE_FRAG_SIZE 3000 ++ ++static void ++xtensa_create_trampoline_frag (bfd_boolean needs_jump_around) ++{ ++ /* Emit a frag where we can place intermediate jump instructions, ++ in case we need to jump farther than 128K bytes. ++ Each jump instruction takes three bytes. ++ We allocate enough for 1000 trampolines in each frag. ++ If that's not enough, oh well. */ ++ ++ struct trampoline_seg *ts = trampoline_seg_list.next; ++ struct trampoline_frag *tf; ++ char *varP; ++ fragS *fragP; ++ int size = TRAMPOLINE_FRAG_SIZE; ++ ++ for ( ; ts; ts = ts->next) ++ { ++ if (ts->seg == now_seg) ++ break; ++ } ++ ++ if (ts == NULL) ++ { ++ ts = (struct trampoline_seg *)xcalloc(sizeof (struct trampoline_seg), 1); ++ ts->next = trampoline_seg_list.next; ++ trampoline_seg_list.next = ts; ++ ts->seg = now_seg; ++ } ++ ++ frag_wane (frag_now); ++ frag_new (0); ++ xtensa_set_frag_assembly_state (frag_now); ++ varP = frag_var (rs_machine_dependent, size, size, RELAX_TRAMPOLINE, NULL, 0, NULL); ++ fragP = (fragS *)(varP - SIZEOF_STRUCT_FRAG); ++ if (trampoline_buf == NULL) ++ { ++ trampoline_buf = xtensa_insnbuf_alloc (xtensa_default_isa); ++ trampoline_slotbuf = xtensa_insnbuf_alloc (xtensa_default_isa); ++ } ++ tf = (struct trampoline_frag *)xmalloc(sizeof (struct trampoline_frag)); ++ tf->next = ts->trampoline_list.next; ++ ts->trampoline_list.next = tf; ++ tf->needs_jump_around = needs_jump_around; ++ tf->fragP = fragP; ++ tf->fixP = NULL; ++} ++ ++ ++static struct trampoline_seg * ++find_trampoline_seg (asection *seg) ++{ ++ struct trampoline_seg *ts = trampoline_seg_list.next; ++ ++ for ( ; ts; ts = ts->next) ++ { ++ if (ts->seg == seg) ++ return ts; ++ } ++ ++ return NULL; ++} ++ ++ ++void dump_trampolines (void); ++ ++void ++dump_trampolines (void) ++{ ++ struct trampoline_seg *ts = trampoline_seg_list.next; ++ ++ for ( ; ts; ts = ts->next) ++ { ++ asection *seg = ts->seg; ++ ++ if (seg == NULL) ++ continue; ++ fprintf(stderr, "SECTION %s\n", seg->name); ++ struct trampoline_frag *tf = ts->trampoline_list.next; ++ for ( ; tf; tf = tf->next) ++ { ++ if (tf->fragP == NULL) ++ continue; ++ fprintf(stderr, " 0x%08x: fix=%d, jump_around=%s\n", ++ (int)tf->fragP->fr_address, (int)tf->fragP->fr_fix, ++ tf->needs_jump_around ? "T" : "F"); ++ } ++ } ++} ++ +static void +xtensa_cleanup_align_frags (void) +{ @@ -686755,6 +690239,149 @@ index 0000000..7075531 + new_stretch += relax_frag_for_align (fragP, stretch); + break; + ++ case RELAX_TRAMPOLINE: ++ if (fragP->tc_frag_data.relax_seen) ++ { ++ segment_info_type *seginfo = seg_info (now_seg); ++ fragS *fP; /* The out-of-range jump. */ ++ fixS *fixP; ++ ++ /* Scan for jumps that will not reach. */ ++ for (fixP = seginfo->fix_root; fixP ; fixP = fixP->fx_next) ++ { ++ symbolS *s = fixP->fx_addsy; ++ xtensa_opcode opcode; ++ int target; ++ int addr; ++ int delta; ++ ++ if (fixP->fx_r_type < BFD_RELOC_XTENSA_SLOT0_OP || ++ fixP->fx_r_type > BFD_RELOC_XTENSA_SLOT14_OP) ++ continue; ++ xtensa_insnbuf_from_chars (isa, trampoline_buf, ++ (unsigned char *) fixP->fx_frag->fr_literal + fixP->fx_where, ++ 0); ++ fmt = xtensa_format_decode (isa, trampoline_buf); ++ gas_assert (fmt != XTENSA_UNDEFINED); ++ slot = fixP->tc_fix_data.slot; ++ xtensa_format_get_slot (isa, fmt, slot, trampoline_buf, trampoline_slotbuf); ++ opcode = xtensa_opcode_decode (isa, fmt, slot, trampoline_slotbuf); ++ if (opcode != xtensa_j_opcode) ++ continue; ++ target = S_GET_VALUE (s); ++ addr = fixP->fx_frag->fr_address; ++ delta = target - addr + stretch; ++ if (delta > J_RANGE || delta < -1 * J_RANGE) ++ { /* Found an out-of-range jump; scan the list of trampolines for the best match. */ ++ struct trampoline_seg *ts = find_trampoline_seg (now_seg); ++ struct trampoline_frag *tf = ts->trampoline_list.next; ++ struct trampoline_frag *prev = &ts->trampoline_list; ++ int lower = (target < addr) ? target : addr; ++ int upper = (target > addr) ? target : addr; ++ int midpoint = lower + (upper - lower) / 2; ++ ++ if ((upper - lower) > 2 * J_RANGE) ++ { ++ /* One trampoline won't suffice; we need multiple jumps. ++ Jump to the trampoline that's farthest, but still in ++ range relative to the original "j" instruction. */ ++ for ( ; tf; prev = tf, tf = tf->next ) ++ { ++ int this_addr = tf->fragP->fr_address + tf->fragP->fr_fix; ++ int next_addr = (tf->next) ? tf->next->fragP->fr_address + tf->next->fragP->fr_fix : 0 ; ++ ++ if (addr == lower) ++ { ++ /* Forward jump. */ ++ if (this_addr - addr < J_RANGE) ++ break; ++ } ++ else ++ { ++ /* Backward jump. */ ++ if (next_addr == 0 || addr - next_addr > J_RANGE) ++ break; ++ } ++ } ++ } ++ else ++ { ++ struct trampoline_frag *best_tf = NULL; ++ int best_delta = 0; ++ ++ for ( ; tf; prev = tf, tf = tf->next ) ++ { ++ int this_addr = tf->fragP->fr_address + tf->fragP->fr_fix; ++ int this_delta = abs (this_addr - midpoint); ++ ++ if (!best_tf || this_delta < best_delta) ++ { ++ best_tf = tf; ++ best_delta = this_delta; ++ } ++ } ++ tf = best_tf; ++ } ++ if (tf->fragP == fragP) ++ { ++ int trampaddr = fragP->fr_address + fragP->fr_fix; ++ ++ if (abs (addr - trampaddr) < J_RANGE) ++ { /* The trampoline is in range of original; fix it! */ ++ fixS *newfixP; ++ int offset; ++ TInsn insn; ++ symbolS *lsym; ++ ++ new_stretch += init_trampoline_frag (tf); ++ offset = fragP->fr_fix; /* Where to assemble the j insn. */ ++ lsym = fragP->fr_symbol; ++ fP = fixP->fx_frag; ++ /* Assemble a jump to the target label here. */ ++ tinsn_init (&insn); ++ insn.insn_type = ITYPE_INSN; ++ insn.opcode = xtensa_j_opcode; ++ insn.ntok = 1; ++ set_expr_symbol_offset (&insn.tok[0], lsym, offset); ++ fmt = xg_get_single_format (xtensa_j_opcode); ++ tinsn_to_slotbuf (fmt, 0, &insn, trampoline_slotbuf); ++ xtensa_format_set_slot (isa, fmt, 0, trampoline_buf, trampoline_slotbuf); ++ xtensa_insnbuf_to_chars (isa, trampoline_buf, (unsigned char *)fragP->fr_literal + offset, 3); ++ fragP->fr_fix += 3; ++ fragP->fr_var -= 3; ++ /* Add a fix-up for the original j insn. */ ++ newfixP = fix_new (fP, fixP->fx_where, fixP->fx_size, lsym, fragP->fr_fix - 3, TRUE, fixP->fx_r_type); ++ newfixP->fx_no_overflow = 1; ++ newfixP->tc_fix_data.X_add_symbol = lsym; ++ newfixP->tc_fix_data.X_add_number = offset; ++ newfixP->tc_fix_data.slot = slot; ++ /* Move the fix-up from the original j insn to this one. */ ++ fixP->fx_frag = fragP; ++ fixP->fx_where = fragP->fr_fix - 3; ++ fixP->tc_fix_data.slot = 0; ++ /* Adjust the jump around this trampoline (if present). */ ++ if (tf->fixP != NULL) ++ { ++ tf->fixP->fx_offset += 3; ++ } ++ new_stretch += 3; ++ fragP->tc_frag_data.relax_seen = FALSE; /* Need another pass. */ ++ /* Do we have room for more? */ ++ if (fragP->fr_var < 3) ++ { /* No, convert to fill. */ ++ frag_wane (fragP); ++ fragP->fr_subtype = 0; ++ /* Remove from the trampoline_list. */ ++ prev->next = tf->next; ++ break; ++ } ++ } ++ } ++ } ++ } ++ } ++ break; ++ + default: + as_bad (_("bad relaxation state")); + } @@ -687193,6 +690820,200 @@ index 0000000..7075531 +} + + ++static struct trampoline_frag * ++search_trampolines (TInsn *tinsn, fragS *fragP, bfd_boolean unreachable_only) ++{ ++ struct trampoline_seg *ts = find_trampoline_seg (now_seg); ++ struct trampoline_frag *tf = (ts) ? ts->trampoline_list.next : NULL; ++ struct trampoline_frag *best_tf = NULL; ++ int best_delta = 0; ++ int best_addr = 0; ++ symbolS *sym = tinsn->tok[0].X_add_symbol; ++ offsetT target = S_GET_VALUE (sym) + tinsn->tok[0].X_add_number; ++ offsetT addr = fragP->fr_address; ++ offsetT lower = (addr < target) ? addr : target; ++ offsetT upper = (addr > target) ? addr : target; ++ int delta = upper - lower; ++ offsetT midpoint = lower + delta / 2; ++ int this_delta = -1; ++ int this_addr = -1; ++ ++ if (delta > 2 * J_RANGE) ++ { ++ /* One trampoline won't do; we need multiple. ++ Choose the farthest trampoline that's still in range of the original ++ and let a later pass finish the job. */ ++ for ( ; tf; tf = tf->next) ++ { ++ int next_addr = (tf->next) ? tf->next->fragP->fr_address + tf->next->fragP->fr_fix : 0; ++ ++ this_addr = tf->fragP->fr_address + tf->fragP->fr_fix; ++ if (lower == addr) ++ { ++ /* Forward jump. */ ++ if (this_addr - addr < J_RANGE) ++ break; ++ } ++ else ++ { ++ /* Backward jump. */ ++ if (next_addr == 0 || addr - next_addr > J_RANGE) ++ break; ++ } ++ if (abs (addr - this_addr) < J_RANGE) ++ return tf; ++ ++ return NULL; ++ } ++ } ++ for ( ; tf; tf = tf->next) ++ { ++ this_addr = tf->fragP->fr_address + tf->fragP->fr_fix; ++ this_delta = abs (this_addr - midpoint); ++ if (unreachable_only && tf->needs_jump_around) ++ continue; ++ if (!best_tf || this_delta < best_delta) ++ { ++ best_tf = tf; ++ best_delta = this_delta; ++ best_addr = this_addr; ++ } ++ } ++ ++ if (best_tf && ++ best_delta < J_RANGE && ++ abs(best_addr - lower) < J_RANGE && ++ abs(best_addr - upper) < J_RANGE) ++ return best_tf; ++ ++ return NULL; /* No suitable trampoline found. */ ++} ++ ++ ++static struct trampoline_frag * ++get_best_trampoline (TInsn *tinsn, fragS *fragP) ++{ ++ struct trampoline_frag *tf = NULL; ++ ++ tf = search_trampolines (tinsn, fragP, TRUE); /* Try unreachable first. */ ++ ++ if (tf == NULL) ++ tf = search_trampolines (tinsn, fragP, FALSE); /* Try ones needing a jump-around, too. */ ++ ++ return tf; ++} ++ ++ ++static void ++check_and_update_trampolines (void) ++{ ++ struct trampoline_seg *ts = find_trampoline_seg (now_seg); ++ struct trampoline_frag *tf = ts->trampoline_list.next; ++ struct trampoline_frag *prev = &ts->trampoline_list; ++ ++ for ( ; tf; prev = tf, tf = tf->next) ++ { ++ if (tf->fragP->fr_var < 3) ++ { ++ frag_wane (tf->fragP); ++ prev->next = tf->next; ++ tf->fragP = NULL; ++ } ++ } ++} ++ ++ ++static int ++init_trampoline_frag (struct trampoline_frag *trampP) ++{ ++ fragS *fp = trampP->fragP; ++ int growth = 0; ++ ++ if (fp->fr_fix == 0) ++ { ++ symbolS *lsym; ++ char label[10 + 2 * sizeof(fp)]; ++ sprintf (label, ".L0_TR_%p", fp); ++ ++ lsym = (symbolS *)local_symbol_make (label, now_seg, 0, fp); ++ fp->fr_symbol = lsym; ++ if (trampP->needs_jump_around) ++ { ++ /* Add a jump around this block of jumps, in case ++ control flows into this block. */ ++ fixS *fixP; ++ TInsn insn; ++ xtensa_format fmt; ++ xtensa_isa isa = xtensa_default_isa; ++ ++ fp->tc_frag_data.is_insn = 1; ++ /* Assemble a jump insn. */ ++ tinsn_init (&insn); ++ insn.insn_type = ITYPE_INSN; ++ insn.opcode = xtensa_j_opcode; ++ insn.ntok = 1; ++ set_expr_symbol_offset (&insn.tok[0], lsym, 3); ++ fmt = xg_get_single_format (xtensa_j_opcode); ++ tinsn_to_slotbuf (fmt, 0, &insn, trampoline_slotbuf); ++ xtensa_format_set_slot (isa, fmt, 0, trampoline_buf, trampoline_slotbuf); ++ xtensa_insnbuf_to_chars (isa, trampoline_buf, (unsigned char *)fp->fr_literal, 3); ++ fp->fr_fix += 3; ++ fp->fr_var -= 3; ++ growth = 3; ++ fixP = fix_new (fp, 0, 3, lsym, 3, TRUE, BFD_RELOC_XTENSA_SLOT0_OP); ++ trampP->fixP = fixP; ++ } ++ } ++ return growth; ++} ++ ++ ++static int ++add_jump_to_trampoline (struct trampoline_frag *trampP, fragS *origfrag) ++{ ++ fragS *tramp = trampP->fragP; ++ fixS *fixP; ++ int offset = tramp->fr_fix; /* Where to assemble the j insn. */ ++ TInsn insn; ++ symbolS *lsym; ++ symbolS *tsym; ++ int toffset; ++ xtensa_format fmt; ++ xtensa_isa isa = xtensa_default_isa; ++ int growth = 0; ++ ++ lsym = tramp->fr_symbol; ++ /* Assemble a jump to the target label in the trampoline frag. */ ++ tsym = origfrag->tc_frag_data.slot_symbols[0]; ++ toffset = origfrag-> tc_frag_data.slot_offsets[0]; ++ tinsn_init (&insn); ++ insn.insn_type = ITYPE_INSN; ++ insn.opcode = xtensa_j_opcode; ++ insn.ntok = 1; ++ set_expr_symbol_offset (&insn.tok[0], tsym, toffset); ++ fmt = xg_get_single_format (xtensa_j_opcode); ++ tinsn_to_slotbuf (fmt, 0, &insn, trampoline_slotbuf); ++ xtensa_format_set_slot (isa, fmt, 0, trampoline_buf, trampoline_slotbuf); ++ xtensa_insnbuf_to_chars (isa, trampoline_buf, (unsigned char *)tramp->fr_literal + offset, 3); ++ tramp->fr_fix += 3; ++ tramp->fr_var -= 3; ++ growth = 3; ++ /* add a fix-up for the trampoline jump. */ ++ fixP = fix_new (tramp, tramp->fr_fix - 3, 3, tsym, toffset, TRUE, BFD_RELOC_XTENSA_SLOT0_OP); ++ /* Modify the jump at the start of this trampoline to point past the newly-added jump. */ ++ fixP = trampP->fixP; ++ if (fixP) ++ fixP->fx_offset += 3; ++ /* Modify the original j to point here. */ ++ origfrag->tc_frag_data.slot_symbols[0] = lsym; ++ origfrag->tc_frag_data.slot_offsets[0] = tramp->fr_fix - 3; ++ /* If trampoline is full, remove it from the list. */ ++ check_and_update_trampolines (); ++ ++ return growth; ++} ++ ++ +static long +relax_frag_immed (segT segP, + fragS *fragP, @@ -687331,6 +691152,37 @@ index 0000000..7075531 + if (negatable_branch && istack.ninsn > 1) + update_next_frag_state (fragP); + ++ /* If last insn is a jump, and it cannot reach its target, try to find a trampoline. */ ++ if (istack.ninsn > 2 && ++ istack.insn[istack.ninsn - 1].insn_type == ITYPE_LABEL && ++ istack.insn[istack.ninsn - 2].insn_type == ITYPE_INSN && ++ istack.insn[istack.ninsn - 2].opcode == xtensa_j_opcode) ++ { ++ TInsn *jinsn = &istack.insn[istack.ninsn - 2]; ++ ++ if (!xg_symbolic_immeds_fit (jinsn, segP, fragP, fragP->fr_offset, total_text_diff)) ++ { ++ struct trampoline_frag *tf = get_best_trampoline (jinsn, fragP); ++ ++ if (tf) ++ { ++ this_text_diff += init_trampoline_frag (tf); ++ this_text_diff += add_jump_to_trampoline (tf, fragP); ++ } ++ else ++ { ++ /* If target symbol is undefined, assume it will reach once linked. */ ++ expressionS *exp = &istack.insn[istack.ninsn - 2].tok[0]; ++ ++ if (exp->X_op == O_symbol && S_IS_DEFINED (exp->X_add_symbol)) ++ { ++ as_bad_where (fragP->fr_file, fragP->fr_line, ++ _("jump target out of range; no usable trampoline found")); ++ } ++ } ++ } ++ } ++ + return this_text_diff; +} + @@ -687451,6 +691303,9 @@ index 0000000..7075531 + else + as_bad (_("invalid relaxation fragment result")); + break; ++ ++ case RELAX_TRAMPOLINE: ++ break; + } + + fragp->fr_var = 0; @@ -690094,13 +693949,12 @@ index 0000000..7075531 +} diff --git a/gas/config/tc-xtensa.h b/gas/config/tc-xtensa.h new file mode 100644 -index 0000000..969f24c +index 0000000..4672bc6 --- /dev/null +++ b/gas/config/tc-xtensa.h -@@ -0,0 +1,461 @@ +@@ -0,0 +1,465 @@ +/* tc-xtensa.h -- Header file for tc-xtensa.c. -+ Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008, 2009 -+ Free Software Foundation, Inc. ++ Copyright (C) 2003-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -690281,6 +694135,11 @@ index 0000000..969f24c + prevent the linker from changing the size of any frag between the + section start and the org frag. */ + ++ RELAX_TRAMPOLINE, ++ /* Every few thousand frags, we insert one of these, just in case we may ++ need some space for a trampoline (jump to a jump) because the function ++ has gotten too big. If not needed, it disappears. */ ++ + RELAX_NONE +}; + @@ -690561,12 +694420,12 @@ index 0000000..969f24c +#endif /* TC_XTENSA */ diff --git a/gas/config/tc-z80.c b/gas/config/tc-z80.c new file mode 100644 -index 0000000..6d5b621 +index 0000000..54fa322 --- /dev/null +++ b/gas/config/tc-z80.c -@@ -0,0 +1,2066 @@ +@@ -0,0 +1,2064 @@ +/* tc-z80.c -- Assemble code for the Zilog Z80 and ASCII R800 -+ Copyright 2005, 2006, 2007, 2008, 2009, 2012 Free Software Foundation, Inc. ++ Copyright (C) 2005-2014 Free Software Foundation, Inc. + Contributed by Arnold Metselaar + + This file is part of GAS, the GNU Assembler. @@ -691034,7 +694893,7 @@ index 0000000..6d5b621 + if (ins_type & ins_err) + error (_(p)); + else -+ as_warn (_(p)); ++ as_warn ("%s", _(p)); +} + +static void @@ -691111,12 +694970,11 @@ index 0000000..6d5b621 +{ + const char *p; + int indir; -+ segT dummy; + + p = skip_space (s); + op->X_md = indir = is_indir (p); + input_line_pointer = (char*) s ; -+ dummy = expression (op); ++ expression (op); + switch (op->X_op) + { + case O_absent: @@ -691272,7 +695130,6 @@ index 0000000..6d5b621 +{ + char *p; + int lo, hi; -+ fixS * fixp; + + p = frag_more (1); + *p = val->X_add_number; @@ -691299,8 +695156,8 @@ index 0000000..6d5b621 + } + else + { -+ fixp = fix_new_exp (frag_now, p - frag_now->fr_literal, 1, val, -+ (r_type == BFD_RELOC_8_PCREL) ? TRUE : FALSE, r_type); ++ fix_new_exp (frag_now, p - frag_now->fr_literal, 1, val, ++ (r_type == BFD_RELOC_8_PCREL) ? TRUE : FALSE, r_type); + /* FIXME : Process constant offsets immediately. */ + } +} @@ -692633,12 +696490,12 @@ index 0000000..6d5b621 +} diff --git a/gas/config/tc-z80.h b/gas/config/tc-z80.h new file mode 100644 -index 0000000..48428a9 +index 0000000..7409871 --- /dev/null +++ b/gas/config/tc-z80.h @@ -0,0 +1,109 @@ +/* this is tc-z80.h -+ Copyright 2005, 2006, 2007, 2012 Free Software Foundation, Inc. ++ Copyright (C) 2005-2014 Free Software Foundation, Inc. + + Contributed by Arnold Metselaar + @@ -692694,7 +696551,7 @@ index 0000000..48428a9 +/* Define some functions to be called by generic code. */ +#define md_end z80_md_end +#define md_start_line_hook() { if (z80_start_line_hook ()) continue; } -+#define TC_CONS_FIX_NEW z80_cons_fix_new ++#define TC_CONS_FIX_NEW(f,w,s,e,r) z80_cons_fix_new ((f), (w), (s), (e)) + +extern void z80_md_end (void); +extern int z80_start_line_hook (void); @@ -692748,13 +696605,12 @@ index 0000000..48428a9 +#endif diff --git a/gas/config/tc-z8k.c b/gas/config/tc-z8k.c new file mode 100644 -index 0000000..2442032 +index 0000000..3b5f0b8 --- /dev/null +++ b/gas/config/tc-z8k.c -@@ -0,0 +1,1566 @@ +@@ -0,0 +1,1565 @@ +/* tc-z8k.c -- Assemble code for the Zilog Z800n -+ Copyright 1992, 1993, 1994, 1995, 1996, 1998, 2000, 2001, 2002, 2003, -+ 2005, 2006, 2007, 2009, 2013 Free Software Foundation, Inc. ++ Copyright (C) 1992-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -694320,14 +698176,12 @@ index 0000000..2442032 +} diff --git a/gas/config/tc-z8k.h b/gas/config/tc-z8k.h new file mode 100644 -index 0000000..454547e +index 0000000..be5f651 --- /dev/null +++ b/gas/config/tc-z8k.h -@@ -0,0 +1,41 @@ +@@ -0,0 +1,39 @@ +/* This file is tc-z8k.h -+ Copyright 1987, 1988, 1989, 1990, 1991, 1992, 1993, 1995, 1997, 1998, -+ 2000, 2002, 2003, 2005, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -694367,13 +698221,12 @@ index 0000000..454547e +#define md_operand(x) diff --git a/gas/config/te-386bsd.h b/gas/config/te-386bsd.h new file mode 100644 -index 0000000..d5bb165 +index 0000000..7228d9a --- /dev/null +++ b/gas/config/te-386bsd.h -@@ -0,0 +1,33 @@ +@@ -0,0 +1,32 @@ +/* te-386bsd.h -- 386BSD target environment declarations. -+ Copyright 1987, 1990, 1991, 1992, 1993, 2000, 2005, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -694406,11 +698259,11 @@ index 0000000..d5bb165 +/* end of te-386bsd.h */ diff --git a/gas/config/te-aix5.h b/gas/config/te-aix5.h new file mode 100644 -index 0000000..1b1f33c +index 0000000..91ba577 --- /dev/null +++ b/gas/config/te-aix5.h @@ -0,0 +1,22 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -694434,11 +698287,11 @@ index 0000000..1b1f33c +#include "obj-format.h" diff --git a/gas/config/te-armeabi.h b/gas/config/te-armeabi.h new file mode 100644 -index 0000000..b6f1e36 +index 0000000..fdd78ab --- /dev/null +++ b/gas/config/te-armeabi.h @@ -0,0 +1,27 @@ -+/* Copyright 2005, 2007, 2009 Free Software Foundation, Inc. ++/* Copyright (C) 2005-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -694467,11 +698320,11 @@ index 0000000..b6f1e36 +#include "obj-format.h" diff --git a/gas/config/te-armlinuxeabi.h b/gas/config/te-armlinuxeabi.h new file mode 100644 -index 0000000..bcb2062 +index 0000000..9147f77 --- /dev/null +++ b/gas/config/te-armlinuxeabi.h @@ -0,0 +1,24 @@ -+/* Copyright 2004, 2005, 2007, 2009 Free Software Foundation, Inc. ++/* Copyright (C) 2004-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -694497,12 +698350,12 @@ index 0000000..bcb2062 +#define EABI_DEFAULT EF_ARM_EABI_VER5 diff --git a/gas/config/te-dragonfly.h b/gas/config/te-dragonfly.h new file mode 100644 -index 0000000..45da36f +index 0000000..9db1b39 --- /dev/null +++ b/gas/config/te-dragonfly.h @@ -0,0 +1,30 @@ +/* te-dragonfly.h -- DragonFlyBSD target environment declarations. -+ Copyright 2011 Free Software Foundation, Inc. ++ Copyright (C) 2011-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -694533,11 +698386,11 @@ index 0000000..45da36f +#include "obj-format.h" diff --git a/gas/config/te-dynix.h b/gas/config/te-dynix.h new file mode 100644 -index 0000000..1f84967 +index 0000000..05a497e --- /dev/null +++ b/gas/config/te-dynix.h @@ -0,0 +1,26 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -694565,11 +698418,11 @@ index 0000000..1f84967 +#include "obj-format.h" diff --git a/gas/config/te-epoc-pe.h b/gas/config/te-epoc-pe.h new file mode 100644 -index 0000000..f2864a1 +index 0000000..50dbd68 --- /dev/null +++ b/gas/config/te-epoc-pe.h @@ -0,0 +1,27 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -694598,12 +698451,12 @@ index 0000000..f2864a1 +#include "obj-format.h" diff --git a/gas/config/te-freebsd.h b/gas/config/te-freebsd.h new file mode 100644 -index 0000000..44f0258 +index 0000000..3744294 --- /dev/null +++ b/gas/config/te-freebsd.h @@ -0,0 +1,30 @@ +/* te-freebsd.h -- FreeBSD target environment declarations. -+ Copyright 2000, 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -694634,11 +698487,11 @@ index 0000000..44f0258 +#include "obj-format.h" diff --git a/gas/config/te-generic.h b/gas/config/te-generic.h new file mode 100644 -index 0000000..0f56199 +index 0000000..9427d58 --- /dev/null +++ b/gas/config/te-generic.h @@ -0,0 +1,38 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -694678,11 +698531,11 @@ index 0000000..0f56199 + diff --git a/gas/config/te-gnu.h b/gas/config/te-gnu.h new file mode 100644 -index 0000000..8f41d26 +index 0000000..0ea31fa --- /dev/null +++ b/gas/config/te-gnu.h @@ -0,0 +1,23 @@ -+/* Copyright 2005, 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2005-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -694707,11 +698560,11 @@ index 0000000..8f41d26 +#include "obj-format.h" diff --git a/gas/config/te-go32.h b/gas/config/te-go32.h new file mode 100644 -index 0000000..58553b5 +index 0000000..70a59fc --- /dev/null +++ b/gas/config/te-go32.h @@ -0,0 +1,31 @@ -+/* Copyright 2007, 2009 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -694744,13 +698597,12 @@ index 0000000..58553b5 +#include "obj-format.h" diff --git a/gas/config/te-hppa.h b/gas/config/te-hppa.h new file mode 100644 -index 0000000..279b855 +index 0000000..5c78978 --- /dev/null +++ b/gas/config/te-hppa.h -@@ -0,0 +1,29 @@ +@@ -0,0 +1,28 @@ +/* Machine specific defines for the PA machine -+ Copyright 1987, 1991, 1992, 1993, 1995, 2000, 2005, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -694779,11 +698631,11 @@ index 0000000..279b855 +#include "obj-format.h" diff --git a/gas/config/te-hppa64.h b/gas/config/te-hppa64.h new file mode 100644 -index 0000000..372909f +index 0000000..519b01a --- /dev/null +++ b/gas/config/te-hppa64.h @@ -0,0 +1,25 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -694810,11 +698662,11 @@ index 0000000..372909f +#include "obj-format.h" diff --git a/gas/config/te-hppalinux64.h b/gas/config/te-hppalinux64.h new file mode 100644 -index 0000000..233263f +index 0000000..a98b041 --- /dev/null +++ b/gas/config/te-hppalinux64.h @@ -0,0 +1,24 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -694840,11 +698692,11 @@ index 0000000..233263f +#include "obj-format.h" diff --git a/gas/config/te-hpux.h b/gas/config/te-hpux.h new file mode 100644 -index 0000000..f228ba2 +index 0000000..67cd30b --- /dev/null +++ b/gas/config/te-hpux.h @@ -0,0 +1,23 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -694869,11 +698721,11 @@ index 0000000..f228ba2 +#include "obj-format.h" diff --git a/gas/config/te-i386aix.h b/gas/config/te-i386aix.h new file mode 100644 -index 0000000..2b174a9 +index 0000000..79e3cc8 --- /dev/null +++ b/gas/config/te-i386aix.h @@ -0,0 +1,38 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -694913,11 +698765,11 @@ index 0000000..2b174a9 +/* end of te-i386aix.h */ diff --git a/gas/config/te-ia64aix.h b/gas/config/te-ia64aix.h new file mode 100644 -index 0000000..ebff460 +index 0000000..63768a3 --- /dev/null +++ b/gas/config/te-ia64aix.h @@ -0,0 +1,23 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -694942,11 +698794,11 @@ index 0000000..ebff460 +#include "obj-format.h" diff --git a/gas/config/te-interix.h b/gas/config/te-interix.h new file mode 100644 -index 0000000..3f55221 +index 0000000..a348921 --- /dev/null +++ b/gas/config/te-interix.h @@ -0,0 +1,35 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -694983,12 +698835,12 @@ index 0000000..3f55221 +#include "obj-format.h" diff --git a/gas/config/te-irix.h b/gas/config/te-irix.h new file mode 100644 -index 0000000..c694216 +index 0000000..ed81905 --- /dev/null +++ b/gas/config/te-irix.h @@ -0,0 +1,31 @@ +/* IRIX targets -+ Copyright 2002, 2003, 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 2002-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -695020,11 +698872,11 @@ index 0000000..c694216 +#endif diff --git a/gas/config/te-linux.h b/gas/config/te-linux.h new file mode 100644 -index 0000000..9a83aab +index 0000000..466f664 --- /dev/null +++ b/gas/config/te-linux.h @@ -0,0 +1,23 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -695049,11 +698901,11 @@ index 0000000..9a83aab +#include "obj-format.h" diff --git a/gas/config/te-lynx.h b/gas/config/te-lynx.h new file mode 100644 -index 0000000..4c2c747 +index 0000000..336d1b0 --- /dev/null +++ b/gas/config/te-lynx.h @@ -0,0 +1,26 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -695081,11 +698933,11 @@ index 0000000..4c2c747 +#endif diff --git a/gas/config/te-mach.h b/gas/config/te-mach.h new file mode 100644 -index 0000000..f76f884 +index 0000000..77f873d --- /dev/null +++ b/gas/config/te-mach.h @@ -0,0 +1,21 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -695108,11 +698960,11 @@ index 0000000..f76f884 +#include "obj-format.h" diff --git a/gas/config/te-macos.h b/gas/config/te-macos.h new file mode 100644 -index 0000000..51b25c4 +index 0000000..336444c --- /dev/null +++ b/gas/config/te-macos.h @@ -0,0 +1,28 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -695142,11 +698994,11 @@ index 0000000..51b25c4 +#include "obj-format.h" diff --git a/gas/config/te-nacl.h b/gas/config/te-nacl.h new file mode 100644 -index 0000000..d64a44d +index 0000000..2547f9f --- /dev/null +++ b/gas/config/te-nacl.h @@ -0,0 +1,30 @@ -+/* Copyright 2012 Free Software Foundation, Inc. ++/* Copyright (C) 2012-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -695178,13 +699030,12 @@ index 0000000..d64a44d +#include "obj-format.h" diff --git a/gas/config/te-nbsd.h b/gas/config/te-nbsd.h new file mode 100644 -index 0000000..ce29101 +index 0000000..4249291 --- /dev/null +++ b/gas/config/te-nbsd.h -@@ -0,0 +1,24 @@ +@@ -0,0 +1,23 @@ +/* te-nbsd.h -- NetBSD target environment declarations. -+ Copyright 1987, 1990, 1991, 1992, 1994, 1998, 2000, 2005, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -695208,11 +699059,11 @@ index 0000000..ce29101 +#include "obj-format.h" diff --git a/gas/config/te-nbsd532.h b/gas/config/te-nbsd532.h new file mode 100644 -index 0000000..e22b6a7 +index 0000000..7952483 --- /dev/null +++ b/gas/config/te-nbsd532.h @@ -0,0 +1,32 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -695246,12 +699097,12 @@ index 0000000..e22b6a7 +#define NS32381 diff --git a/gas/config/te-netware.h b/gas/config/te-netware.h new file mode 100644 -index 0000000..61c9bd5 +index 0000000..9fc5928 --- /dev/null +++ b/gas/config/te-netware.h @@ -0,0 +1,28 @@ +/* te-netware.h -- NetWare target environment declarations. -+ Copyright 2004, 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 2004-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -695280,11 +699131,11 @@ index 0000000..61c9bd5 +#include "obj-format.h" diff --git a/gas/config/te-pc532mach.h b/gas/config/te-pc532mach.h new file mode 100644 -index 0000000..0639def +index 0000000..4241c5a --- /dev/null +++ b/gas/config/te-pc532mach.h @@ -0,0 +1,32 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -695318,11 +699169,11 @@ index 0000000..0639def +#define NS32381 diff --git a/gas/config/te-pe.h b/gas/config/te-pe.h new file mode 100644 -index 0000000..1ac632c +index 0000000..a6b857d --- /dev/null +++ b/gas/config/te-pe.h @@ -0,0 +1,26 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -695350,11 +699201,11 @@ index 0000000..1ac632c +#include "obj-format.h" diff --git a/gas/config/te-pep.h b/gas/config/te-pep.h new file mode 100644 -index 0000000..abc305e +index 0000000..2995761 --- /dev/null +++ b/gas/config/te-pep.h @@ -0,0 +1,29 @@ -+/* Copyright 2006, 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2006-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -695385,11 +699236,11 @@ index 0000000..abc305e +#include "obj-format.h" diff --git a/gas/config/te-psos.h b/gas/config/te-psos.h new file mode 100644 -index 0000000..a61e261 +index 0000000..e6e2d97 --- /dev/null +++ b/gas/config/te-psos.h @@ -0,0 +1,35 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -695426,11 +699277,11 @@ index 0000000..a61e261 +#include "obj-format.h" diff --git a/gas/config/te-riscix.h b/gas/config/te-riscix.h new file mode 100644 -index 0000000..dcd87e5 +index 0000000..9fa9f85 --- /dev/null +++ b/gas/config/te-riscix.h @@ -0,0 +1,25 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -695457,11 +699308,11 @@ index 0000000..dcd87e5 +#include "obj-format.h" diff --git a/gas/config/te-solaris.h b/gas/config/te-solaris.h new file mode 100644 -index 0000000..9c628c2 +index 0000000..3865999 --- /dev/null +++ b/gas/config/te-solaris.h @@ -0,0 +1,40 @@ -+/* Copyright 2008, 2010 Free Software Foundation, Inc. ++/* Copyright (C) 2008-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -695503,12 +699354,12 @@ index 0000000..9c628c2 +#endif diff --git a/gas/config/te-sparcaout.h b/gas/config/te-sparcaout.h new file mode 100644 -index 0000000..3c6c76f +index 0000000..5502650 --- /dev/null +++ b/gas/config/te-sparcaout.h @@ -0,0 +1,22 @@ +/* te-sparcaout.h -- embedded sparc-aout target environment declarations. -+ Copyright 1996, 2000, 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 1996-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -695531,13 +699382,12 @@ index 0000000..3c6c76f +#include "obj-format.h" diff --git a/gas/config/te-sun3.h b/gas/config/te-sun3.h new file mode 100644 -index 0000000..d7dd637 +index 0000000..7138e22 --- /dev/null +++ b/gas/config/te-sun3.h -@@ -0,0 +1,49 @@ +@@ -0,0 +1,48 @@ +/* te-sun3.h -- Sun-3 target environment declarations. -+ Copyright 1987, 1990, 1991, 1992, 2000, 2003, 2005, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -695586,11 +699436,11 @@ index 0000000..d7dd637 +/* end of te-sun3.h */ diff --git a/gas/config/te-svr4.h b/gas/config/te-svr4.h new file mode 100644 -index 0000000..a33304a +index 0000000..f989a9d --- /dev/null +++ b/gas/config/te-svr4.h @@ -0,0 +1,23 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -695615,11 +699465,11 @@ index 0000000..a33304a +#include "obj-format.h" diff --git a/gas/config/te-symbian.h b/gas/config/te-symbian.h new file mode 100644 -index 0000000..02a4e10 +index 0000000..4b52b22 --- /dev/null +++ b/gas/config/te-symbian.h @@ -0,0 +1,22 @@ -+/* Copyright 2004, 2005, 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2004-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -695643,12 +699493,12 @@ index 0000000..02a4e10 +#include "te-armeabi.h" diff --git a/gas/config/te-tmips.h b/gas/config/te-tmips.h new file mode 100644 -index 0000000..e7ab8cc +index 0000000..ce5dbda --- /dev/null +++ b/gas/config/te-tmips.h @@ -0,0 +1,40 @@ +/* Traditional MIPS targets -+ Copyright 2000, 2003, 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -695689,11 +699539,11 @@ index 0000000..e7ab8cc +#endif diff --git a/gas/config/te-uclinux.h b/gas/config/te-uclinux.h new file mode 100644 -index 0000000..4a5d879 +index 0000000..bb0ead0 --- /dev/null +++ b/gas/config/te-uclinux.h @@ -0,0 +1,22 @@ -+/* Copyright 2009 Free Software Foundation, Inc. ++/* Copyright (C) 2009-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -695717,12 +699567,12 @@ index 0000000..4a5d879 +#include "te-generic.h" diff --git a/gas/config/te-vms.c b/gas/config/te-vms.c new file mode 100644 -index 0000000..42f965a +index 0000000..8bb15c5 --- /dev/null +++ b/gas/config/te-vms.c @@ -0,0 +1,347 @@ +/* te-vms.c -- Utilities for VMS. -+ Copyright 2009 Free Software Foundation, Inc. ++ Copyright (C) 2009-2014 Free Software Foundation, Inc. + + Written by Douglas B Rupp + @@ -696070,11 +699920,11 @@ index 0000000..42f965a +} diff --git a/gas/config/te-vms.h b/gas/config/te-vms.h new file mode 100644 -index 0000000..0c3a194 +index 0000000..34012e1 --- /dev/null +++ b/gas/config/te-vms.h @@ -0,0 +1,41 @@ -+/* Copyright 2009 Free Software Foundation, Inc. ++/* Copyright (C) 2009-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -696117,13 +699967,12 @@ index 0000000..0c3a194 + vms_dwarf2_file_name(FILENAME, DIRNAME) diff --git a/gas/config/te-vxworks.h b/gas/config/te-vxworks.h new file mode 100644 -index 0000000..8c7d505 +index 0000000..e22b1a3 --- /dev/null +++ b/gas/config/te-vxworks.h -@@ -0,0 +1,31 @@ +@@ -0,0 +1,30 @@ +/* te-vxworks.h -- VxWorks target environment declarations. -+ Copyright 2005, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 2005-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -696154,11 +700003,11 @@ index 0000000..8c7d505 +#endif diff --git a/gas/config/te-wince-pe.h b/gas/config/te-wince-pe.h new file mode 100644 -index 0000000..fc41c00 +index 0000000..a2049ba --- /dev/null +++ b/gas/config/te-wince-pe.h @@ -0,0 +1,21 @@ -+/* Copyright 2007 Free Software Foundation, Inc. ++/* Copyright (C) 2007-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -696181,13 +700030,12 @@ index 0000000..fc41c00 +#include "te-pe.h" diff --git a/gas/config/vax-inst.h b/gas/config/vax-inst.h new file mode 100644 -index 0000000..4f4f961 +index 0000000..c6ce102 --- /dev/null +++ b/gas/config/vax-inst.h -@@ -0,0 +1,80 @@ +@@ -0,0 +1,79 @@ +/* vax-inst.h - GNU - Part of vax.c -+ Copyright 1987, 1992, 1995, 2000, 2002, 2005, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -696267,13 +700115,12 @@ index 0000000..4f4f961 +/* end of vax-inst.h */ diff --git a/gas/config/xtensa-istack.h b/gas/config/xtensa-istack.h new file mode 100644 -index 0000000..75b56b2 +index 0000000..d9aee8f --- /dev/null +++ b/gas/config/xtensa-istack.h -@@ -0,0 +1,106 @@ +@@ -0,0 +1,105 @@ +/* Declarations for stacks of tokenized Xtensa instructions. -+ Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008 -+ Free Software Foundation, Inc. ++ Copyright (C) 2003-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -696379,13 +700226,12 @@ index 0000000..75b56b2 +#endif /* !XTENSA_ISTACK_H */ diff --git a/gas/config/xtensa-relax.c b/gas/config/xtensa-relax.c new file mode 100644 -index 0000000..681369e +index 0000000..df8a55a --- /dev/null +++ b/gas/config/xtensa-relax.c -@@ -0,0 +1,1925 @@ +@@ -0,0 +1,1924 @@ +/* Table of relaxations for Xtensa assembly. -+ Copyright 2003, 2004, 2005, 2006, 2007, 2008, 2009 -+ Free Software Foundation, Inc. ++ Copyright (C) 2003-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -698310,12 +702156,12 @@ index 0000000..681369e +} diff --git a/gas/config/xtensa-relax.h b/gas/config/xtensa-relax.h new file mode 100644 -index 0000000..4c56166 +index 0000000..ba07939 --- /dev/null +++ b/gas/config/xtensa-relax.h @@ -0,0 +1,189 @@ +/* Table of relaxations for Xtensa assembly. -+ Copyright 2003, 2004, 2005, 2007, 2008, 2009 Free Software Foundation, Inc. ++ Copyright (C) 2003-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -698505,10 +702351,10 @@ index 0000000..4c56166 +#endif /* !XTENSA_RELAX_H */ diff --git a/gas/configure b/gas/configure new file mode 100755 -index 0000000..8a89e4f +index 0000000..1e1086f --- /dev/null +++ b/gas/configure -@@ -0,0 +1,16878 @@ +@@ -0,0 +1,16895 @@ +#! /bin/sh +# Guess values for system-dependent variables and create Makefiles. +# Generated by GNU Autoconf 2.64. @@ -710086,6 +713932,9 @@ index 0000000..8a89e4f +using_cgen=no + + ++# Set the 'development' global. ++. $srcdir/../bfd/development.sh ++ +GCC_WARN_CFLAGS="-W -Wall -Wstrict-prototypes -Wmissing-prototypes" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ @@ -710120,8 +713969,8 @@ index 0000000..8a89e4f + *) ;; +esac + -+# Enable -Werror by default when using gcc -+if test "${GCC}" = yes -a -z "${ERROR_ON_WARNING}" ; then ++# Enable -Werror by default when using gcc. Turn it off for releases. ++if test "${GCC}" = yes -a -z "${ERROR_ON_WARNING}" -a "$development" = true ; then + ERROR_ON_WARNING=yes +fi + @@ -710547,12 +714396,24 @@ index 0000000..8a89e4f + mipsisa32r2 | mipsisa32r2el) + mips_cpu=mips32r2 + ;; ++ mipsisa32r3 | mipsisa32r3el) ++ mips_cpu=mips32r3 ++ ;; ++ mipsisa32r5 | mipsisa32r5el) ++ mips_cpu=mips32r5 ++ ;; + mipsisa64 | mipsisa64el) + mips_cpu=mips64 + ;; + mipsisa64r2 | mipsisa64r2el) + mips_cpu=mips64r2 + ;; ++ mipsisa64r3 | mipsisa64r3el) ++ mips_cpu=mips64r3 ++ ;; ++ mipsisa64r5 | mipsisa64r5el) ++ mips_cpu=mips64r5 ++ ;; + mipstx39 | mipstx39el) + mips_cpu=r3900 + ;; @@ -710661,7 +714522,7 @@ index 0000000..8a89e4f + fi + ;; + -+ epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | openrisc) ++ epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | or1k) + using_cgen=yes + ;; + @@ -710937,6 +714798,8 @@ index 0000000..8a89e4f +cgen_cpu_prefix="" +if test $using_cgen = yes ; then + case ${target_cpu} in ++ or1knd) ++ cgen_cpu_prefix=or1k ;; + *) cgen_cpu_prefix=${target_cpu} ;; + esac + @@ -715389,7 +719252,7 @@ index 0000000..8a89e4f + diff --git a/gas/configure.com b/gas/configure.com new file mode 100644 -index 0000000..3811298 +index 0000000..982d331 --- /dev/null +++ b/gas/configure.com @@ -0,0 +1,280 @@ @@ -715398,7 +719261,7 @@ index 0000000..3811298 +$! files for a VMS system. We do not use the configure script, since we +$! do not have /bin/sh to execute it. +$! -+$! Copyright 2012 Free Software Foundation ++$! Copyright (C) 2012-2014 Free Software Foundation, Inc. +$! +$! This file is free software; you can redistribute it and/or modify +$! it under the terms of the GNU General Public License as published by @@ -715675,16 +719538,16 @@ index 0000000..3811298 + diff --git a/gas/configure.in b/gas/configure.in new file mode 100644 -index 0000000..9e1ba59 +index 0000000..b9f9a98 --- /dev/null +++ b/gas/configure.in -@@ -0,0 +1,840 @@ +@@ -0,0 +1,854 @@ +dnl Process this file with autoconf to produce a configure script. +dnl +dnl And be careful when changing it! If you must add tests with square +dnl brackets, be sure changequote invocations surround it. +dnl -+dnl Copyright 2012, 2013 Free Software Foundation ++dnl Copyright (C) 2012-2014 Free Software Foundation, Inc. +dnl +dnl This file is free software; you can redistribute it and/or modify +dnl it under the terms of the GNU General Public License as published by @@ -715894,12 +719757,24 @@ index 0000000..9e1ba59 + mipsisa32r2 | mipsisa32r2el) + mips_cpu=mips32r2 + ;; ++ mipsisa32r3 | mipsisa32r3el) ++ mips_cpu=mips32r3 ++ ;; ++ mipsisa32r5 | mipsisa32r5el) ++ mips_cpu=mips32r5 ++ ;; + mipsisa64 | mipsisa64el) + mips_cpu=mips64 + ;; + mipsisa64r2 | mipsisa64r2el) + mips_cpu=mips64r2 + ;; ++ mipsisa64r3 | mipsisa64r3el) ++ mips_cpu=mips64r3 ++ ;; ++ mipsisa64r5 | mipsisa64r5el) ++ mips_cpu=mips64r5 ++ ;; + mipstx39 | mipstx39el) + mips_cpu=r3900 + ;; @@ -716002,7 +719877,7 @@ index 0000000..9e1ba59 + fi + ;; + -+ epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | openrisc) ++ epiphany | fr30 | ip2k | iq2000 | lm32 | m32r | or1k) + using_cgen=yes + ;; + @@ -716249,6 +720124,8 @@ index 0000000..9e1ba59 +cgen_cpu_prefix="" +if test $using_cgen = yes ; then + case ${target_cpu} in ++ or1knd) ++ cgen_cpu_prefix=or1k ;; + *) cgen_cpu_prefix=${target_cpu} ;; + esac + AC_SUBST(cgen_cpu_prefix) @@ -716521,13 +720398,13 @@ index 0000000..9e1ba59 +AC_OUTPUT diff --git a/gas/configure.tgt b/gas/configure.tgt new file mode 100644 -index 0000000..fdc0612 +index 0000000..7d5afa9 --- /dev/null +++ b/gas/configure.tgt -@@ -0,0 +1,490 @@ +@@ -0,0 +1,488 @@ +# gas target specific configuration file. This is a -*- sh -*- file. +# -+# Copyright 2012 Free Software Foundation ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -716608,7 +720485,7 @@ index 0000000..fdc0612 + mt) cpu_type=mt endian=big ;; + nds32be) cpu_type=nds32 endian=big ;; + nds32le) cpu_type=nds32 endian=little ;; -+ or32*) cpu_type=or32 endian=big ;; ++ or1k* | or1knd*) cpu_type=or1k endian=big ;; + pjl*) cpu_type=pj endian=little ;; + pj*) cpu_type=pj endian=big ;; + powerpc*le*) cpu_type=ppc endian=little ;; @@ -716884,10 +720761,8 @@ index 0000000..fdc0612 + ns32k-pc532-lites*) fmt=aout em=nbsd532 ;; + ns32k-*-*n*bsd*) fmt=aout em=nbsd532 ;; + -+ openrisc-*-*) fmt=elf ;; -+ -+ or32-*-rtems*) fmt=elf ;; -+ or32-*-elf) fmt=elf ;; ++ or1k-*-elf | or1knd-*-elf) fmt=elf endian=big ;; ++ or1k-*-linux* | or1knd-*-linux*) fmt=elf em=linux endian=big ;; + + pj*) fmt=elf ;; + @@ -717001,7 +720876,7 @@ index 0000000..fdc0612 +esac + +case ${cpu_type} in -+ aarch64 | alpha | arm | i386 | ia64 | microblaze | mips | ns32k | pdp11 | ppc | sparc | z80 | z8k) ++ aarch64 | alpha | arm | i386 | ia64 | microblaze | mips | ns32k | or1k | or1knd | pdp11 | ppc | sparc | z80 | z8k) + bfd_gas=yes + ;; +esac @@ -717017,13 +720892,12 @@ index 0000000..fdc0612 +fi diff --git a/gas/debug.c b/gas/debug.c new file mode 100644 -index 0000000..02695fc +index 0000000..cc3a106 --- /dev/null +++ b/gas/debug.c -@@ -0,0 +1,106 @@ +@@ -0,0 +1,105 @@ +/* This file is debug.c -+ Copyright 1987, 1988, 1989, 1990, 1991, 1992, 2000, 2005, 2006, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -717187,13 +721061,12 @@ index 0000000..6959140 +$s/$/ \\/ diff --git a/gas/depend.c b/gas/depend.c new file mode 100644 -index 0000000..7a3c54c +index 0000000..16f79c1 --- /dev/null +++ b/gas/depend.c -@@ -0,0 +1,208 @@ +@@ -0,0 +1,207 @@ +/* depend.c - Handle dependency tracking. -+ Copyright 1997, 1998, 2000, 2001, 2003, 2004, 2005, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1997-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -717401,13 +721274,13 @@ index 0000000..7a3c54c +} diff --git a/gas/doc/Makefile.am b/gas/doc/Makefile.am new file mode 100644 -index 0000000..e5b3c5f +index 0000000..10f2e68 --- /dev/null +++ b/gas/doc/Makefile.am @@ -0,0 +1,141 @@ +## Process this file with automake to generate Makefile.in +# -+# Copyright 2012 Free Software Foundation ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -717548,7 +721421,7 @@ index 0000000..e5b3c5f +endif diff --git a/gas/doc/Makefile.in b/gas/doc/Makefile.in new file mode 100644 -index 0000000..5a65e17 +index 0000000..c51f99c --- /dev/null +++ b/gas/doc/Makefile.in @@ -0,0 +1,807 @@ @@ -717570,7 +721443,7 @@ index 0000000..5a65e17 +@SET_MAKE@ + +# -+# Copyright 2012 Free Software Foundation ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -718361,11 +722234,11 @@ index 0000000..5a65e17 +.NOEXPORT: diff --git a/gas/doc/all.texi b/gas/doc/all.texi new file mode 100644 -index 0000000..5e1ed04 +index 0000000..94b88bf --- /dev/null +++ b/gas/doc/all.texi @@ -0,0 +1,106 @@ -+@c Copyright 1992-2013 Free Software Foundation, Inc. ++@c Copyright (C) 1992-2014 Free Software Foundation, Inc. +@c This file is part of the documentation for the GAS manual + +@c Configuration settings for all-inclusive version of manual @@ -718473,12 +722346,12 @@ index 0000000..5e1ed04 +@clear OBJ-NAME diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo new file mode 100644 -index 0000000..739b5b9 +index 0000000..0f0956c --- /dev/null +++ b/gas/doc/as.texinfo -@@ -0,0 +1,7792 @@ +@@ -0,0 +1,7815 @@ +\input texinfo @c -*-Texinfo-*- -+@c Copyright 1991-2013 Free Software Foundation, Inc. ++@c Copyright (C) 1991-2014 Free Software Foundation, Inc. +@c UPDATE!! On future updates-- +@c (1) check for new machine-dep cmdline options in +@c md_parse_option definitions in config/tc-*.c @@ -718579,7 +722452,7 @@ index 0000000..739b5b9 +This file documents the GNU Assembler "@value{AS}". + +@c man begin COPYRIGHT -+Copyright @copyright{} 1991-2013 Free Software Foundation, Inc. ++Copyright @copyright{} 1991-2014 Free Software Foundation, Inc. + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License, Version 1.3 @@ -718628,7 +722501,7 @@ index 0000000..739b5b9 +@end tex + +@vskip 0pt plus 1filll -+Copyright @copyright{} 1991-2013 Free Software Foundation, Inc. ++Copyright @copyright{} 1991-2014 Free Software Foundation, Inc. + + Permission is granted to copy, distribute and/or modify this document + under the terms of the GNU Free Documentation License, Version 1.3 @@ -718880,7 +722753,8 @@ index 0000000..739b5b9 + [@b{-mabi}=@var{ABI}] [@b{-32}] [@b{-n32}] [@b{-64}] [@b{-mfp32}] [@b{-mgp32}] + [@b{-march}=@var{CPU}] [@b{-mtune}=@var{CPU}] [@b{-mips1}] [@b{-mips2}] + [@b{-mips3}] [@b{-mips4}] [@b{-mips5}] [@b{-mips32}] [@b{-mips32r2}] -+ [@b{-mips64}] [@b{-mips64r2}] ++ [@b{-mips32r3}] [@b{-mips32r5}] [@b{-mips64}] [@b{-mips64r2}] ++ [@b{-mips64r3}] [@b{-mips64r5}] + [@b{-construct-floats}] [@b{-no-construct-floats}] + [@b{-mnan=@var{encoding}}] + [@b{-trap}] [@b{-no-break}] [@b{-break}] [@b{-no-trap}] @@ -718892,6 +722766,7 @@ index 0000000..739b5b9 + [@b{-mdsp}] [@b{-mno-dsp}] + [@b{-mdspr2}] [@b{-mno-dspr2}] + [@b{-mmsa}] [@b{-mno-msa}] ++ [@b{-mxpa}] [@b{-mno-xpa}] + [@b{-mmt}] [@b{-mno-mt}] + [@b{-mmcu}] [@b{-mno-mcu}] + [@b{-minsn32}] [@b{-mno-insn32}] @@ -718956,6 +722831,12 @@ index 0000000..739b5b9 + [@b{-msolaris}|@b{-mno-solaris}] + [@b{-nops=@var{count}}] +@end ifset ++@ifset RL78 ++ ++@emph{Target RL78 options:} ++ [@b{-mg10}] ++ [@b{-m32bit-doubles}|@b{-m64bit-doubles}] ++@end ifset +@ifset RX + +@emph{Target RX options:} @@ -719022,6 +722903,7 @@ index 0000000..739b5b9 + [@b{--[no-]target-align}] [@b{--[no-]longcalls}] + [@b{--[no-]transform}] + [@b{--rename-section} @var{oldname}=@var{newname}] ++ [@b{--[no-]trampolines}] +@end ifset + +@ifset Z80 @@ -719327,6 +723209,8 @@ index 0000000..739b5b9 +@item -mthumb-interwork +Specify that the code has been generated with interworking between Thumb and +ARM code in mind. ++@item -mccs ++Turns on CodeComposer Studio assembly syntax compatibility mode. +@item -k +Specify that PIC code has been generated. +@end table @@ -719741,15 +723625,21 @@ index 0000000..739b5b9 +@itemx -mips5 +@itemx -mips32 +@itemx -mips32r2 ++@itemx -mips32r3 ++@itemx -mips32r5 +@itemx -mips64 +@itemx -mips64r2 ++@itemx -mips64r3 ++@itemx -mips64r5 +Generate code for a particular MIPS Instruction Set Architecture level. +@samp{-mips1} is an alias for @samp{-march=r3000}, @samp{-mips2} is an +alias for @samp{-march=r6000}, @samp{-mips3} is an alias for +@samp{-march=r4000} and @samp{-mips4} is an alias for @samp{-march=r8000}. -+@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips64}, and -+@samp{-mips64r2} correspond to generic MIPS V, MIPS32, MIPS32 Release 2, -+MIPS64, and MIPS64 Release 2 ISA processors, respectively. ++@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips32r3}, ++@samp{-mips32r5}, @samp{-mips64}, @samp{-mips64r2}, @samp{-mips64r3}, and ++@samp{-mips64r5} correspond to generic MIPS V, MIPS32, MIPS32 Release 2, ++MIPS32 Release 3, MIPS32 Release 5, MIPS64, MIPS64 Release 2, ++MIPS64 Release 3, and MIPS64 Release 5 ISA processors, respectively. + +@item -march=@var{cpu} +Generate code for a particular MIPS CPU. @@ -719833,6 +723723,12 @@ index 0000000..739b5b9 +This tells the assembler to accept MSA instructions. +@samp{-mno-msa} turns off this option. + ++@item -mxpa ++@itemx -mno-xpa ++Generate code for the MIPS eXtended Physical Address (XPA) Extension. ++This tells the assembler to accept XPA instructions. ++@samp{-mno-xpa} turns off this option. ++ +@item -mmt +@itemx -mno-mt +Generate code for the MT Application Specific Extension. @@ -722826,7 +726722,7 @@ index 0000000..739b5b9 +with no-op instructions when appropriate. + +The way the required alignment is specified varies from system to system. -+For the arc, hppa, i386 using ELF, i860, iq2000, m68k, or32, ++For the arc, hppa, i386 using ELF, i860, iq2000, m68k, or1k, +s390, sparc, tic4x, tic80 and xtensa, the first expression is the +alignment request in bytes. For example @samp{.align 8} advances +the location counter until it is a multiple of 8. If the location counter @@ -726271,11 +730167,11 @@ index 0000000..739b5b9 +@c End: diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi new file mode 100644 -index 0000000..6019006 +index 0000000..1f4ce4c --- /dev/null +++ b/gas/doc/c-aarch64.texi -@@ -0,0 +1,281 @@ -+@c Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc. +@@ -0,0 +1,359 @@ ++@c Copyright (C) 2009-2014 Free Software Foundation, Inc. +@c Contributed by ARM Ltd. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. @@ -726293,9 +730189,9 @@ index 0000000..6019006 +@end ifclear + +@cindex AArch64 support -+@cindex Thumb support +@menu +* AArch64 Options:: Options ++* AArch64 Extensions:: Extensions +* AArch64 Syntax:: Syntax +* AArch64 Floating Point:: Floating Point +* AArch64 Directives:: AArch64 Machine Directives @@ -726311,25 +730207,103 @@ index 0000000..6019006 +@c man begin OPTIONS +@table @gcctabopt + -+@cindex @code{-EB} command line option, AArch64 ++@cindex @option{-EB} command line option, AArch64 +@item -EB +This option specifies that the output generated by the assembler should +be marked as being encoded for a big-endian processor. + -+@cindex @code{-EL} command line option, AArch64 ++@cindex @option{-EL} command line option, AArch64 +@item -EL +This option specifies that the output generated by the assembler should +be marked as being encoded for a little-endian processor. + -+@cindex @code{-mabi=} command line option, AArch64 ++@cindex @option{-mabi=} command line option, AArch64 +@item -mabi=@var{abi} +Specify which ABI the source code uses. The recognized arguments +are: @code{ilp32} and @code{lp64}, which decides the generated object +file in ELF32 and ELF64 format respectively. The default is @code{lp64}. + ++@cindex @option{-mcpu=} command line option, AArch64 ++@item -mcpu=@var{processor}[+@var{extension}@dots{}] ++This option specifies the target processor. The assembler will issue an error ++message if an attempt is made to assemble an instruction which will not execute ++on the target processor. The following processor names are recognized: ++@code{cortex-a53}, ++@code{cortex-a57}, ++and ++@code{xgene-1}. ++The special name @code{all} may be used to allow the assembler to accept ++instructions valid for any supported processor, including all optional ++extensions. ++ ++In addition to the basic instruction set, the assembler can be told to ++accept, or restrict, various extension mnemonics that extend the ++processor. @xref{AArch64 Extensions}. ++ ++If some implementations of a particular processor can have an ++extension, then then those extensions are automatically enabled. ++Consequently, you will not normally have to specify any additional ++extensions. ++ ++@cindex @option{-march=} command line option, AArch64 ++@item -march=@var{architecture}[+@var{extension}@dots{}] ++This option specifies the target architecture. The assembler will ++issue an error message if an attempt is made to assemble an ++instruction which will not execute on the target architecture. The ++only value for @var{architecture} is @code{armv8-a}. ++ ++If both @option{-mcpu} and @option{-march} are specified, the ++assembler will use the setting for @option{-mcpu}. If neither are ++specified, the assembler will default to @option{-mcpu=all}. ++ ++The architecture option can be extended with the same instruction set ++extension options as the @option{-mcpu} option. Unlike ++@option{-mcpu}, extensions are not always enabled by default, ++@xref{AArch64 Extensions}. ++ ++@cindex @code{-mverbose-error} command line option, AArch64 ++@item -mverbose-error ++This option enables verbose error messages for AArch64 gas. This option ++is enabled by default. ++ ++@cindex @code{-mno-verbose-error} command line option, AArch64 ++@item -mno-verbose-error ++This option disables verbose error messages in AArch64 gas. ++ +@end table +@c man end + ++@node AArch64 Extensions ++@section Architecture Extensions ++ ++The table below lists the permitted architecture extensions that are ++supported by the assembler and the conditions under which they are ++automatically enabled. ++ ++Multiple extensions may be specified, separated by a @code{+}. ++Extension mnemonics may also be removed from those the assembler ++accepts. This is done by prepending @code{no} to the option that adds ++the extension. Extensions that are removed must be listed after all ++extensions that have been added. ++ ++Enabling an extension that requires other extensions will ++automatically cause those extensions to be enabled. Similarly, ++disabling an extension that is required by other extensions will ++automatically cause those extensions to be disabled. ++ ++@multitable @columnfractions .12 .17 .17 .54 ++@headitem Extension @tab Minimum Architecture @tab Enabled by default ++ @tab Description ++@item @code{crc} @tab ARMv8-A @tab No ++ @tab Enable CRC instructions. ++@item @code{crypto} @tab ARMv8-A @tab No ++ @tab Enable cryptographic extensions. This implies @code{fp} and @code{simd}. ++@item @code{fp} @tab ARMv8-A @tab ARMv8-A or later ++ @tab Enable floating-point extensions. ++@item @code{simd} @tab ARMv8-A @tab ARMv8-A or later ++ @tab Enable Advanced SIMD extensions. This implies @code{fp}. ++@end multitable ++ +@node AArch64 Syntax +@section Syntax +@menu @@ -726385,24 +730359,24 @@ index 0000000..6019006 +@cindex ADRP, ADD, LDR/STR group relocations, AArch64 +Relocations for @samp{ADRP}, and @samp{ADD}, @samp{LDR} or @samp{STR} +instructions can be generated by prefixing the label with -+@samp{#:pg_hi21:} and @samp{#:lo12:} respectively. ++@samp{:pg_hi21:} and @samp{#:lo12:} respectively. + +For example to use 33-bit (+/-4GB) pc-relative addressing to +load the address of @var{foo} into x0: + +@smallexample -+ adrp x0, #:pg_hi21:foo ++ adrp x0, :pg_hi21:foo + add x0, x0, #:lo12:foo +@end smallexample + +Or to load the value of @var{foo} into x0: + +@smallexample -+ adrp x0, #:pg_hi21:foo ++ adrp x0, :pg_hi21:foo + ldr x0, [x0, #:lo12:foo] +@end smallexample + -+Note that @samp{#:pg_hi21:} is optional. ++Note that @samp{:pg_hi21:} is optional. + +@smallexample + adrp x0, foo @@ -726411,7 +730385,7 @@ index 0000000..6019006 +is equivalent to + +@smallexample -+ adrp x0, #:pg_hi21:foo ++ adrp x0, :pg_hi21:foo +@end smallexample + +@node AArch64 Floating Point @@ -726451,12 +730425,12 @@ index 0000000..6019006 +This directive causes the current contents of the literal pool to be +dumped into the current section (which is assumed to be the .text +section) at the current location (aligned to a word boundary). -+@code{GAS} maintains a separate literal pool for each section and each ++GAS maintains a separate literal pool for each section and each +sub-section. The @code{.ltorg} directive will only affect the literal +pool of the current section and sub-section. At the end of assembly +all remaining, un-empty literal pools will automatically be dumped. + -+Note - older versions of @code{GAS} would dump the current literal ++Note - older versions of GAS would dump the current literal +pool any time a section change occurred. This is no longer done, since +it prevents accurate control of the placement of literal pools. + @@ -726517,7 +730491,7 @@ index 0000000..6019006 + +@cindex AArch64 opcodes +@cindex opcodes for AArch64 -+@code{@value{AS}} implements all the standard AArch64 opcodes. It also ++GAS implements all the standard AArch64 opcodes. It also +implements several pseudo opcodes, including several synthetic load +instructions. + @@ -726558,12 +730532,11 @@ index 0000000..6019006 +@end table diff --git a/gas/doc/c-alpha.texi b/gas/doc/c-alpha.texi new file mode 100644 -index 0000000..dd48413 +index 0000000..302ed0f --- /dev/null +++ b/gas/doc/c-alpha.texi -@@ -0,0 +1,487 @@ -+@c Copyright 2002, 2003, 2005, 2009, 2011 -+@c Free Software Foundation, Inc. +@@ -0,0 +1,486 @@ ++@c Copyright (C) 2002-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@c man end @@ -727051,11 +731024,11 @@ index 0000000..dd48413 +@end ifnottex diff --git a/gas/doc/c-arc.texi b/gas/doc/c-arc.texi new file mode 100644 -index 0000000..38bd3c8 +index 0000000..c7bbb66 --- /dev/null +++ b/gas/doc/c-arc.texi @@ -0,0 +1,340 @@ -+@c Copyright 2000-2013 Free Software Foundation, Inc. ++@c Copyright (C) 2000-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. + @@ -727397,11 +731370,11 @@ index 0000000..38bd3c8 +Reference Manual}, ARC International (www.arc.com) diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi new file mode 100644 -index 0000000..df7313d +index 0000000..7bcce94 --- /dev/null +++ b/gas/doc/c-arm.texi -@@ -0,0 +1,1183 @@ -+@c Copyright 1996-2013 Free Software Foundation, Inc. +@@ -0,0 +1,1187 @@ ++@c Copyright (C) 1996-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. + @@ -727772,6 +731745,10 @@ index 0000000..df7313d +Enable or disable warnings about using deprecated options or +features. The default is to warn. + ++@cindex @code{-mccs} command line option, ARM ++@item -mccs ++Turns on CodeComposer Studio assembly syntax compatibility mode. ++ +@end table + + @@ -728586,11 +732563,11 @@ index 0000000..df7313d +ARM Architecture} available from @uref{http://infocenter.arm.com}. diff --git a/gas/doc/c-avr.texi b/gas/doc/c-avr.texi new file mode 100644 -index 0000000..213e82c +index 0000000..305e64c --- /dev/null +++ b/gas/doc/c-avr.texi -@@ -0,0 +1,417 @@ -+@c Copyright 2006-2013 Free Software Foundation, Inc. +@@ -0,0 +1,425 @@ ++@c Copyright (C) 2006-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. + @@ -728637,7 +732614,7 @@ index 0000000..213e82c +attiny2313a, attiny24, attiny24a, attiny4313, attiny44, attiny44a, attiny84, +attiny84a, attiny25, attiny45, attiny85, attiny261, attiny261a, attiny461, +attiny461a, attiny861, attiny861a, attiny87, attiny43u, attiny48, attiny88, -+at86rf401). ++attiny828, at86rf401, ata6289, ata5272). + +Instruction set avr3 is for the classic AVR core with up to 128K program +memory space (MCU types: at43usb355, at76c711). @@ -728646,64 +732623,68 @@ index 0000000..213e82c +memory space (MCU types: atmega103, at43usb320). + +Instruction set avr35 is for classic AVR core plus MOVW, CALL, and JMP -+instructions (MCU types: attiny167, at90usb82, at90usb162, atmega8u2, -+atmega16u2, atmega32u2). ++instructions (MCU types: attiny167, attiny1634, at90usb82, at90usb162, ++atmega8u2, atmega16u2, atmega32u2, ata5505). + +Instruction set avr4 is for the enhanced AVR core with up to 8K program -+memory space (MCU types: atmega48, atmega48a, atmega48p, atmega8, atmega88, -+atmega88a, atmega88p, atmega88pa, atmega8515, atmega8535, atmega8hva, at90pwm1, -+at90pwm2, at90pwm2b, at90pwm3, at90pwm3b, at90pwm81, ata6289). ++memory space (MCU types: atmega48, atmega48a, atmega48pa, atmega48p, atmega8, ++atmega8a, atmega88, atmega88a, atmega88p, atmega88pa, atmega8515, atmega8535, ++atmega8hva, at90pwm1, at90pwm2, at90pwm2b, at90pwm3, at90pwm3b, at90pwm81, ++ata6285, ata6286). + +Instruction set avr5 is for the enhanced AVR core with up to 128K program -+memory space (MCU types: atmega16, atmega16a, atmega161, atmega162, -+atmega163, atmega164a, atmega164p, atmega165, atmega165a, atmega165p, -+atmega168, atmega168a, atmega168p, atmega169, atmega169a, atmega169p, -+atmega169pa, atmega32, atmega323, atmega324a, atmega324p, atmega325, -+atmega325a, atmega325p, atmega325pa, atmega3250, atmega3250a, -+atmega3250p, atmega3250pa, atmega328, atmega328p, atmega329, -+atmega329a, atmega329p, atmega329pa, atmega3290, atmega3290a, -+atmega3290p, atmega3290pa, atmega406, atmega64, atmega640, atmega644, -+atmega644a, atmega644p, atmega644pa, atmega645, atmega645a, -+atmega645p, atmega6450, atmega6450a, atmega6450p, atmega649, -+atmega649a, atmega649p, atmega6490, atmega6490a, atmega6490p, -+atmega64rfr2, atmega644rfr2, atmega16hva, atmega16hva2, atmega16hvb, -+atmega16hvbrevb, atmega32hvb, atmega32hvbrevb, atmega64hve, at90can32, -+at90can64, at90pwm161, at90pwm216, at90pwm316, atmega32c1, atmega64c1, -+atmega16m1, atmega32m1, atmega64m1, atmega16u4, atmega32u4, -+atmega32u6, at90usb646, at90usb647, at94k, at90scr100). ++memory space (MCU types: at90pwm161, atmega16, atmega16a, atmega161, atmega162, ++atmega163, atmega164a, atmega164p, atmega164pa, atmega165, atmega165a, ++atmega165p, atmega165pa, atmega168, atmega168a, atmega168p, atmega168pa, ++atmega169, atmega169a, atmega169p, atmega169pa, atmega32, atmega323, atmega324a, ++atmega324p, atmega324pa, atmega325, atmega325a, atmega32, atmega32a, atmega323, ++atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, atmega325p, ++atmega325p, atmega325pa, atmega3250, atmega3250a, atmega3250p, atmega3250pa, ++atmega328, atmega328p, atmega329, atmega329a, atmega329p, atmega329pa, ++atmega3290a, atmega3290p, atmega3290pa, atmega406, atmega64, atmega64a, ++atmega64rfr2, atmega644rfr2, atmega640, atmega644, atmega644a, atmega644p, ++atmega644pa, atmega645, atmega645a, atmega645p, atmega6450, atmega6450a, ++atmega6450p, atmega649, atmega649a, atmega649p, atmega6490, atmega6490a, ++atmega6490p, atmega16hva, atmega16hva2, atmega16hvb, atmega16hvbrevb, ++atmega32hvb, atmega32hvbrevb, atmega64hve, at90can32, at90can64, at90pwm161, ++at90pwm216, at90pwm316, atmega32c1, atmega64c1, atmega16m1, atmega32m1, ++atmega64m1, atmega16u4, atmega32u4, atmega32u6, at90usb646, at90usb647, at94k, ++at90scr100, ata5790, ata5795). + +Instruction set avr51 is for the enhanced AVR core with exactly 128K program -+memory space (MCU types: atmega128, atmega1280, atmega1281, atmega1284p, -+atmega128rfa1, -+atmega128rfr2, atmega1284rfr2, ++memory space (MCU types: atmega128, atmega128a, atmega1280, atmega1281, ++atmega1284, atmega1284p, atmega128rfa1, atmega128rfr2, atmega1284rfr2, +at90can128, at90usb1286, at90usb1287, m3000). + +Instruction set avr6 is for the enhanced AVR core with a 3-byte PC (MCU types: -+atmega2560, atmega2561, -+atmega256rfr2, atmega2564rfr2). ++atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2). + +Instruction set avrxmega2 is for the XMEGA AVR core with 8K to 64K program -+memory space and less than 64K data space (MCU types: atxmega16a4, atxmega16d4, -+atxmega16x1, atxmega32a4, atxmega32d4, atxmega32x1). ++memory space and less than 64K data space (MCU types: atxmega16a4, atxmega16a4u, ++atxmega16c4, atxmega16d4, atxmega16x1, atxmega32a4, atxmega32a4u, atxmega32c4, ++atxmega32d4, atxmega16e5, atxmega8e5, atxmega32e5, atxmega32x1). + +Instruction set avrxmega3 is for the XMEGA AVR core with 8K to 64K program +memory space and greater than 64K data space (MCU types: none). + +Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K program -+memory space and less than 64K data space (MCU types: atxmega64a3, atxmega64d3). ++memory space and less than 64K data space (MCU types: atxmega64a3, atxmega64a3u, ++atxmega64a4u, atxmega64b1, atxmega64b3, atxmega64c3, atxmega64d3, atxmega64d4). + +Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K program +memory space and greater than 64K data space (MCU types: atxmega64a1, +atxmega64a1u). + -+Instruction set avrxmega6 is for the XMEGA AVR core with up to 256K program -+memory space and less than 64K data space (MCU types: atxmega128a3, -+atxmega128d3, atxmega192a3, atxmega128b1, atxmega192d3, atxmega256a3, -+atxmega256a3b, atxmega256a3bu, atxmega192d3). ++Instruction set avrxmega6 is for the XMEGA AVR core with larger than 64K program ++memory space and less than 64K data space (MCU types: atxmega128a3, ++atxmega128a3u, atxmega128c3, atxmega128d3, atxmega128d4, atxmega192a3, ++atxmega192a3u, atxmega128b1, atxmega128b3, atxmega192c3, atxmega192d3, ++atxmega256a3, atxmega256a3u, atxmega256a3b, atxmega256a3bu, atxmega256c3, ++atxmega256d3, atxmega384c3, atxmega256d3). + -+Instruction set avrxmega7 is for the XMEGA AVR core with up to 256K program ++Instruction set avrxmega7 is for the XMEGA AVR core with larger than 64K program +memory space and greater than 64K data space (MCU types: atxmega128a1, -+atxmega128a1u). ++atxmega128a1u, atxmega128a4u). + +@cindex @code{-mall-opcodes} command line option, AVR +@item -mall-opcodes @@ -728717,6 +732698,10 @@ index 0000000..213e82c +@item -mno-wrap +This option reject @code{rjmp/rcall} instructions with 8K wrap-around. + ++@cindex @code{-mrmw} command line option, AVR ++@item -mrmw ++Accept Read-Modify-Write (@code{XCH,LAC,LAS,LAT}) instructions. ++ +@end table + + @@ -729009,12 +732994,11 @@ index 0000000..213e82c +@end smallexample diff --git a/gas/doc/c-bfin.texi b/gas/doc/c-bfin.texi new file mode 100644 -index 0000000..870e0db +index 0000000..35de1fa --- /dev/null +++ b/gas/doc/c-bfin.texi -@@ -0,0 +1,274 @@ -+@c Copyright 2005, 2006, 2009, 2010, 2011 -+@c Free Software Foundation, Inc. +@@ -0,0 +1,273 @@ ++@c Copyright (C) 2005-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@c man end @@ -729289,11 +733273,11 @@ index 0000000..870e0db +@end table diff --git a/gas/doc/c-cr16.texi b/gas/doc/c-cr16.texi new file mode 100644 -index 0000000..b996d73 +index 0000000..20b118d --- /dev/null +++ b/gas/doc/c-cr16.texi @@ -0,0 +1,124 @@ -+@c Copyright 2007-2013 Free Software Foundation, Inc. ++@c Copyright (C) 2007-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. + @@ -729419,11 +733403,11 @@ index 0000000..b996d73 +line. diff --git a/gas/doc/c-cris.texi b/gas/doc/c-cris.texi new file mode 100644 -index 0000000..ff27921 +index 0000000..73ba059 --- /dev/null +++ b/gas/doc/c-cris.texi @@ -0,0 +1,411 @@ -+@c Copyright 2002, 2004 Free Software Foundation, Inc. ++@c Copyright (C) 2002-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@c CRIS description contributed by Axis Communications. @@ -729836,11 +733820,11 @@ index 0000000..ff27921 +@end table diff --git a/gas/doc/c-d10v.texi b/gas/doc/c-d10v.texi new file mode 100644 -index 0000000..d6c0bb6 +index 0000000..3dd52b5 --- /dev/null +++ b/gas/doc/c-d10v.texi @@ -0,0 +1,264 @@ -+@c Copyright 1996, 2000, 2002 Free Software Foundation, Inc. ++@c Copyright (C) 1996-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC @@ -730106,11 +734090,11 @@ index 0000000..d6c0bb6 + diff --git a/gas/doc/c-d30v.texi b/gas/doc/c-d30v.texi new file mode 100644 -index 0000000..aec7f68 +index 0000000..6e86f4d --- /dev/null +++ b/gas/doc/c-d30v.texi @@ -0,0 +1,299 @@ -+@c Copyright (C) 1997, 2011 Free Software Foundation, Inc. ++@c Copyright (C) 1997-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC @@ -730411,11 +734395,11 @@ index 0000000..aec7f68 + diff --git a/gas/doc/c-epiphany.texi b/gas/doc/c-epiphany.texi new file mode 100644 -index 0000000..8e2b94d +index 0000000..29862c2 --- /dev/null +++ b/gas/doc/c-epiphany.texi @@ -0,0 +1,67 @@ -+@c Copyright 1999, 2002, 2011 Free Software Foundation, Inc. ++@c Copyright (C) 1999-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@c man end @@ -730484,12 +734468,11 @@ index 0000000..8e2b94d +line. diff --git a/gas/doc/c-h8300.texi b/gas/doc/c-h8300.texi new file mode 100644 -index 0000000..5245c66 +index 0000000..cbdebba --- /dev/null +++ b/gas/doc/c-h8300.texi -@@ -0,0 +1,365 @@ -+@c Copyright (C) 1991, 1992, 1993, 1994, 1995, 2003, 2008, 2011 -+@c Free Software Foundation, Inc. +@@ -0,0 +1,364 @@ ++@c Copyright (C) 1991-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC @@ -730855,12 +734838,11 @@ index 0000000..5245c66 +the suffix and the register size do not match. diff --git a/gas/doc/c-hppa.texi b/gas/doc/c-hppa.texi new file mode 100644 -index 0000000..2bb1ae4 +index 0000000..0e0e152 --- /dev/null +++ b/gas/doc/c-hppa.texi -@@ -0,0 +1,301 @@ -+@c Copyright 1991, 1992, 1993, 1994, 1995, 1998, 2004, 2011 -+@c Free Software Foundation, Inc. +@@ -0,0 +1,300 @@ ++@c Copyright (C) 1991-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@page @@ -731162,11 +735144,11 @@ index 0000000..2bb1ae4 +(HP 09740-90039). diff --git a/gas/doc/c-i370.texi b/gas/doc/c-i370.texi new file mode 100644 -index 0000000..a580a7c +index 0000000..2a05a94 --- /dev/null +++ b/gas/doc/c-i370.texi @@ -0,0 +1,200 @@ -+@c Copyright 2000, 2002 Free Software Foundation, Inc. ++@c Copyright (C) 2000-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC @@ -731368,11 +735350,11 @@ index 0000000..a580a7c +@cite{ESA/390 Principles of Operation} (IBM Publication Number DZ9AR004). diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi new file mode 100644 -index 0000000..8a4a5f1 +index 0000000..1952cee --- /dev/null +++ b/gas/doc/c-i386.texi -@@ -0,0 +1,1128 @@ -+@c Copyright 1991-2013 Free Software Foundation, Inc. +@@ -0,0 +1,1135 @@ ++@c Copyright (C) 1991-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@c man end @@ -731657,6 +735639,11 @@ index 0000000..8a4a5f1 +This option forces the assembler to add BND prefix to all branches, even +if such prefix was not explicitly specified in the source code. + ++@cindex @samp{-mbig-obj} option, x86-64 ++@item -mbig-obj ++On x86-64 PE/COFF target this option forces the use of big object file ++format, which allows more than 32768 sections. ++ +@end table +@c man end + @@ -732437,6 +736424,8 @@ index 0000000..8a4a5f1 +@item @samp{.rtm} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw} +@item @samp{.smap} @tab @samp{.mpx} +@item @samp{.smap} @tab @samp{.sha} ++@item @samp{.smap} @tab @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} ++@item @samp{.smap} @tab @samp{.prefetchwt1} +@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5} +@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm} +@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16} @@ -732502,11 +736491,11 @@ index 0000000..8a4a5f1 + diff --git a/gas/doc/c-i860.texi b/gas/doc/c-i860.texi new file mode 100644 -index 0000000..a66024e +index 0000000..7940a94 --- /dev/null +++ b/gas/doc/c-i860.texi @@ -0,0 +1,197 @@ -+@c Copyright 2000, 2003, 2011 Free Software Foundation, Inc. ++@c Copyright (C) 2000-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC @@ -732705,12 +736694,11 @@ index 0000000..a66024e +line. diff --git a/gas/doc/c-i960.texi b/gas/doc/c-i960.texi new file mode 100644 -index 0000000..e8a2e61 +index 0000000..65f0a07 --- /dev/null +++ b/gas/doc/c-i960.texi -@@ -0,0 +1,325 @@ -+@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 2002, 2006, 2011 -+@c Free Software Foundation, Inc. +@@ -0,0 +1,324 @@ ++@c Copyright (C) 1991-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC @@ -733036,12 +737024,11 @@ index 0000000..e8a2e61 +line. diff --git a/gas/doc/c-ia64.texi b/gas/doc/c-ia64.texi new file mode 100644 -index 0000000..eb92836 +index 0000000..afbec2f --- /dev/null +++ b/gas/doc/c-ia64.texi -@@ -0,0 +1,202 @@ -+@c Copyright 2002, 2003, 2005 -+@c Free Software Foundation, Inc. +@@ -0,0 +1,201 @@ ++@c Copyright (C) 2002-2014 Free Software Foundation, Inc. +@c Contributed by David Mosberger-Tang +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. @@ -733244,12 +737231,11 @@ index 0000000..eb92836 +@end ifnottex diff --git a/gas/doc/c-ip2k.texi b/gas/doc/c-ip2k.texi new file mode 100644 -index 0000000..c33042b +index 0000000..7f88176 --- /dev/null +++ b/gas/doc/c-ip2k.texi -@@ -0,0 +1,71 @@ -+@c Copyright 2002, 2011 -+@c Free Software Foundation, Inc. +@@ -0,0 +1,70 @@ ++@c Copyright (C) 2002-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC @@ -733321,12 +737307,11 @@ index 0000000..c33042b +character. diff --git a/gas/doc/c-lm32.texi b/gas/doc/c-lm32.texi new file mode 100644 -index 0000000..d09fd27 +index 0000000..767748b --- /dev/null +++ b/gas/doc/c-lm32.texi -@@ -0,0 +1,233 @@ -+@c Copyright 2008, 2011 -+@c Free Software Foundation, Inc. +@@ -0,0 +1,232 @@ ++@c Copyright (C) 2008-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. + @@ -733560,12 +737545,11 @@ index 0000000..d09fd27 +@code{@value{AS}} implements all the standard LM32 opcodes. diff --git a/gas/doc/c-m32c.texi b/gas/doc/c-m32c.texi new file mode 100644 -index 0000000..16acc8d +index 0000000..2a4ee36 --- /dev/null +++ b/gas/doc/c-m32c.texi -@@ -0,0 +1,149 @@ -+@c Copyright 2005, 2008 -+@c Free Software Foundation, Inc. +@@ -0,0 +1,148 @@ ++@c Copyright (C) 2005-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC @@ -733715,11 +737699,11 @@ index 0000000..16acc8d +line. diff --git a/gas/doc/c-m32r.texi b/gas/doc/c-m32r.texi new file mode 100644 -index 0000000..abb0728 +index 0000000..079f372 --- /dev/null +++ b/gas/doc/c-m32r.texi @@ -0,0 +1,356 @@ -+@c Copyright 1991-2013 Free Software Foundation, Inc. ++@c Copyright (C) 1991-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC @@ -734077,13 +738061,11 @@ index 0000000..abb0728 +@end table diff --git a/gas/doc/c-m68hc11.texi b/gas/doc/c-m68hc11.texi new file mode 100644 -index 0000000..2583c01 +index 0000000..cf06667 --- /dev/null +++ b/gas/doc/c-m68hc11.texi -@@ -0,0 +1,478 @@ -+@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2003, -+@c 2006, 2011, 2012 -+@c Free Software Foundation, Inc. +@@ -0,0 +1,476 @@ ++@c Copyright (C) 1991-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC @@ -734561,12 +738543,11 @@ index 0000000..2583c01 + diff --git a/gas/doc/c-m68k.texi b/gas/doc/c-m68k.texi new file mode 100644 -index 0000000..7beca11 +index 0000000..d260d3d --- /dev/null +++ b/gas/doc/c-m68k.texi -@@ -0,0 +1,637 @@ -+@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2003, -+@c 2004, 2006, 2007, 2011 Free Software Foundation, Inc. +@@ -0,0 +1,636 @@ ++@c Copyright (C) 1991-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC @@ -735204,11 +739185,11 @@ index 0000000..7beca11 +by the @samp{;} character. diff --git a/gas/doc/c-metag.texi b/gas/doc/c-metag.texi new file mode 100644 -index 0000000..f55db22 +index 0000000..09f8958 --- /dev/null +++ b/gas/doc/c-metag.texi @@ -0,0 +1,86 @@ -+@c Copyright 2013 Free Software Foundation, Inc. ++@c Copyright (C) 2013-2014 Free Software Foundation, Inc. +@c Contributed by Imagination Technologies Ltd. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. @@ -735296,12 +739277,11 @@ index 0000000..f55db22 +such as @samp{D0.0}. diff --git a/gas/doc/c-microblaze.texi b/gas/doc/c-microblaze.texi new file mode 100644 -index 0000000..0027019 +index 0000000..a1c71ce --- /dev/null +++ b/gas/doc/c-microblaze.texi -@@ -0,0 +1,100 @@ -+@c Copyright 2009, 2011 -+@c Free Software Foundation, Inc. +@@ -0,0 +1,99 @@ ++@c Copyright (C) 2009-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC @@ -735402,13 +739382,11 @@ index 0000000..0027019 +line. diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi new file mode 100644 -index 0000000..dfada1e +index 0000000..d2795e7 --- /dev/null +++ b/gas/doc/c-mips.texi -@@ -0,0 +1,931 @@ -+@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001, -+@c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2013 -+@c Free Software Foundation, Inc. +@@ -0,0 +1,963 @@ ++@c Copyright (C) 1991-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC @@ -735491,16 +739469,22 @@ index 0000000..dfada1e +@itemx -mips5 +@itemx -mips32 +@itemx -mips32r2 ++@itemx -mips32r3 ++@itemx -mips32r5 +@itemx -mips64 +@itemx -mips64r2 ++@itemx -mips64r3 ++@itemx -mips64r5 +Generate code for a particular MIPS Instruction Set Architecture level. +@samp{-mips1} corresponds to the R2000 and R3000 processors, +@samp{-mips2} to the R6000 processor, @samp{-mips3} to the +R4000 processor, and @samp{-mips4} to the R8000 and R10000 processors. -+@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips64}, and -+@samp{-mips64r2} correspond to generic MIPS V, MIPS32, MIPS32 Release 2, -+MIPS64, and MIPS64 Release 2 ISA processors, respectively. You can also -+switch instruction sets during the assembly; see @ref{MIPS ISA, ++@samp{-mips5}, @samp{-mips32}, @samp{-mips32r2}, @samp{-mips32r3}, ++@samp{-mips32r5}, @samp{-mips64}, @samp{-mips64r2}, @samp{-mips64r3}, and ++@samp{-mips64r5} correspond to generic MIPS V, MIPS32, MIPS32 Release 2, ++MIPS32 Release 3, MIPS32 Release 5, MIPS64, and MIPS64 Release 2, ++MIPS64 Release 3, and MIPS64 Release 5 ISA processors, respectively. You ++can also switch instruction sets during the assembly; see @ref{MIPS ISA, +Directives to override the ISA level}. + +@item -mgp32 @@ -735593,6 +739577,12 @@ index 0000000..dfada1e +This tells the assembler to accept MSA instructions. +@samp{-mno-msa} turns off this option. + ++@item -mxpa ++@itemx -mno-xpa ++Generate code for the MIPS eXtended Physical Address (XPA) Extension. ++This tells the assembler to accept XPA instructions. ++@samp{-mno-xpa} turns off this option. ++ +@item -mvirt +@itemx -mno-virt +Generate code for the Virtualization Application Specific Extension. @@ -735747,6 +739737,7 @@ index 0000000..dfada1e +1004kf2_1, +1004kf, +1004kf1_1, ++p5600, +5kc, +5kf, +20kc, @@ -736055,8 +740046,8 @@ index 0000000..dfada1e +@kindex @code{.set mips@var{n}} +@sc{gnu} @code{@value{AS}} supports an additional directive to change +the MIPS Instruction Set Architecture level on the fly: @code{.set -+mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 64 -+or 64r2. ++mips@var{n}}. @var{n} should be a number from 0 to 5, or 32, 32r2, 32r3, ++32r5, 64, 64r2, 64r3 or 64r5. +The values other than 0 make the assembler accept instructions +for the corresponding ISA level, from that point on in the +assembly. @code{.set mips@var{n}} affects not only which instructions @@ -736090,6 +740081,20 @@ index 0000000..dfada1e +@node MIPS assembly options +@section Directives to control code generation + ++@cindex MIPS directives to override command line options ++@kindex @code{.module} ++The @code{.module} directive allows command line options to be set directly ++from assembly. The format of the directive matches the @code{.set} ++directive but only those options which are relevant to a whole module are ++supported. The effect of a @code{.module} directive is the same as the ++corresponding command line option. Where @code{.set} directives support ++returning to a default then the @code{.module} directives do not as they ++define the defaults. ++ ++These module-level directives must appear first in assembly. ++ ++Traditional MIPS assemblers do not support this directive. ++ +@cindex MIPS 32-bit microMIPS instruction generation override +@kindex @code{.set insn32} +@kindex @code{.set noinsn32} @@ -736288,6 +740293,13 @@ index 0000000..dfada1e +on in the assembly. The @code{.set novirt} directive prevents Virtualization +instructions from being accepted. + ++@cindex MIPS eXtended Physical Address (XPA) instruction generation override ++@kindex @code{.set xpa} ++@kindex @code{.set noxpa} ++The directive @code{.set xpa} makes the assembler accept instructions ++from the XPA Extension from that point on in the assembly. The ++@code{.set noxpa} directive prevents XPA instructions from being accepted. ++ +Traditional MIPS assemblers do not support these directives. + +@node MIPS Floating-Point @@ -736339,11 +740351,11 @@ index 0000000..dfada1e +line. diff --git a/gas/doc/c-mmix.texi b/gas/doc/c-mmix.texi new file mode 100644 -index 0000000..009f9d3 +index 0000000..24d242c --- /dev/null +++ b/gas/doc/c-mmix.texi @@ -0,0 +1,589 @@ -+@c Copyright 2001, 2002, 2003, 2006, 2011 Free Software Foundation, Inc. ++@c Copyright (C) 2001-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@c MMIX description by Hans-Peter Nilsson, hp@bitrange.com @@ -736934,11 +740946,11 @@ index 0000000..009f9d3 +@end table diff --git a/gas/doc/c-msp430.texi b/gas/doc/c-msp430.texi new file mode 100644 -index 0000000..77d6fd1 +index 0000000..cae3d8a --- /dev/null +++ b/gas/doc/c-msp430.texi -@@ -0,0 +1,372 @@ -+@c Copyright 2002-2013 Free Software Foundation, Inc. +@@ -0,0 +1,388 @@ ++@c Copyright (C) 2002-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC @@ -736969,13 +740981,12 @@ index 0000000..77d6fd1 +@table @code + +@item -mmcu -+selects the mpu arch. If the architecture is 430Xv2 then this also -+enables NOP generation unless the @option{-mN} is also specified. ++selects the mcu architecture. If the architecture is 430Xv2 then this ++also enables NOP generation unless the @option{-mN} is also specified. + +@item -mcpu +selects the cpu architecture. If the architecture is 430Xv2 then this -+also enables NOP generation unless the @option{-mN} is also -+specified. ++also enables NOP generation unless the @option{-mN} is also specified. + +@item -mP +enables polymorph instructions handler. @@ -736995,17 +741006,25 @@ index 0000000..77d6fd1 +followed by a NOP instruction in order to ensure the correct +processing of interrupts. By default it is up to the programmer to +supply these NOP instructions, but this command line option enables -+the automatic insertion by the assembler. Note - the assembler does -+not peek ahead to the next instruction so it will insert a NOP even -+one is already present. ++the automatic insertion by the assembler, if they are missing. + -+@c end-sanitize-msp430 -+@c %redact note changed text for mN option +@item -mN +disables the generation of a NOP instruction following any instruction +that might change the interrupts enabled/disabled state. This is the +default behaviour. + ++@item -my ++tells the assembler to generate a warning message if a NOP does not ++immediately forllow an instruction that enables or disables ++interrupts. This is the default. ++ ++Note that this option can be stacked with the @option{-mn} option so ++that the assembler will both warn about missing NOP instructions and ++then insert them automatically. ++ ++@item -mY ++disables warnings about missing NOP instructions. ++ +@item -md +mark the object file as one that requires data to copied from ROM to +RAM at execution startup. Disabled by default. @@ -737203,6 +741222,15 @@ index 0000000..77d6fd1 +@item .profiler +This directive instructs assembler to add new profile entry to the object file. + ++@cindex @code{refsym} directive, MSP 430 ++@item .refsym ++This directive instructs assembler to add an undefined reference to ++the symbol following the directive. The maximum symbol name length is ++1023 characters. No relocation is created for this symbol; it will ++exist purely for pulling in object files from archives. Note that ++this reloc is not sufficient to prevent garbage collection; use a ++KEEP() directive in the linker file to preserve such objects. ++ +@end table + +@node MSP430 Opcodes @@ -737312,12 +741340,11 @@ index 0000000..77d6fd1 +@end smallexample diff --git a/gas/doc/c-mt.texi b/gas/doc/c-mt.texi new file mode 100644 -index 0000000..02843f2 +index 0000000..f6ee21d --- /dev/null +++ b/gas/doc/c-mt.texi -@@ -0,0 +1,71 @@ -+@c Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 -+@c Free Software Foundation, Inc. +@@ -0,0 +1,70 @@ ++@c Copyright (C) 1996-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. + @@ -737389,11 +741416,11 @@ index 0000000..02843f2 + diff --git a/gas/doc/c-nds32.texi b/gas/doc/c-nds32.texi new file mode 100644 -index 0000000..9636fcc +index 0000000..21f3b82 --- /dev/null +++ b/gas/doc/c-nds32.texi @@ -0,0 +1,299 @@ -+@c Copyright 2013 Free Software Foundation, Inc. ++@c Copyright (C) 2013-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@c man end @@ -737694,11 +741721,11 @@ index 0000000..9636fcc +@end table diff --git a/gas/doc/c-nios2.texi b/gas/doc/c-nios2.texi new file mode 100644 -index 0000000..1d45dd2 +index 0000000..e2aa125 --- /dev/null +++ b/gas/doc/c-nios2.texi -@@ -0,0 +1,249 @@ -+@c Copyright 2012, 2013 Free Software Foundation, Inc. +@@ -0,0 +1,257 @@ ++@c Copyright (C) 2012-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@c man end @@ -737831,7 +741858,11 @@ index 0000000..1d45dd2 +@end smallexample + +@cindex @code{call} directive, Nios II ++@cindex @code{call_lo} directive, Nios II ++@cindex @code{call_hiadj} directive, Nios II +@cindex @code{got} directive, Nios II ++@cindex @code{got_lo} directive, Nios II ++@cindex @code{got_hiadj} directive, Nios II +@cindex @code{gotoff} directive, Nios II +@cindex @code{gotoff_lo} directive, Nios II +@cindex @code{gotoff_hiadj} directive, Nios II @@ -737841,7 +741872,11 @@ index 0000000..1d45dd2 +@cindex @code{tls_ldm} directive, Nios II +@cindex @code{tls_ldo} directive, Nios II +@item %call(@var{expression}) ++@item %call_lo(@var{expression}) ++@item %call_hiadj(@var{expression}) +@itemx %got(@var{expression}) ++@itemx %got_lo(@var{expression}) ++@itemx %got_hiadj(@var{expression}) +@itemx %gotoff(@var{expression}) +@itemx %gotoff_lo(@var{expression}) +@itemx %gotoff_hiadj(@var{expression}) @@ -737949,12 +741984,11 @@ index 0000000..1d45dd2 +pseudo-instructions. diff --git a/gas/doc/c-ns32k.texi b/gas/doc/c-ns32k.texi new file mode 100644 -index 0000000..7b6544c +index 0000000..c2b8e53 --- /dev/null +++ b/gas/doc/c-ns32k.texi -@@ -0,0 +1,77 @@ -+@c Copyright 1991, 1992, 1993, 1994, 1995, 2002 -+@c Free Software Foundation, Inc. +@@ -0,0 +1,76 @@ ++@c Copyright (C) 1991-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. + @@ -738032,11 +742066,11 @@ index 0000000..7b6544c +line. diff --git a/gas/doc/c-pdp11.texi b/gas/doc/c-pdp11.texi new file mode 100644 -index 0000000..c5e0c3d +index 0000000..62ed9d5 --- /dev/null +++ b/gas/doc/c-pdp11.texi @@ -0,0 +1,357 @@ -+@c Copyright 2001, 2002, 2006 Free Software Foundation, Inc. ++@c Copyright (C) 2001-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC @@ -738395,11 +742429,11 @@ index 0000000..c5e0c3d +supported yet. diff --git a/gas/doc/c-pj.texi b/gas/doc/c-pj.texi new file mode 100644 -index 0000000..dcf32ab +index 0000000..e124cae --- /dev/null +++ b/gas/doc/c-pj.texi @@ -0,0 +1,52 @@ -+@c Copyright 1999, 2002, 2011 Free Software Foundation, Inc. ++@c Copyright (C) 1999-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@page @@ -738453,12 +742487,11 @@ index 0000000..dcf32ab +line. diff --git a/gas/doc/c-ppc.texi b/gas/doc/c-ppc.texi new file mode 100644 -index 0000000..c2209ed +index 0000000..c457a50 --- /dev/null +++ b/gas/doc/c-ppc.texi -@@ -0,0 +1,231 @@ -+@c Copyright 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009, 2010, 2011 -+@c 2012 Free Software Foundation, Inc. +@@ -0,0 +1,230 @@ ++@c Copyright (C) 2001-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@c man end @@ -738690,11 +742723,11 @@ index 0000000..c2209ed +line. diff --git a/gas/doc/c-rl78.texi b/gas/doc/c-rl78.texi new file mode 100644 -index 0000000..0964ac4 +index 0000000..a714548 --- /dev/null +++ b/gas/doc/c-rl78.texi -@@ -0,0 +1,126 @@ -+@c Copyright 2011-2013 Free Software Foundation, Inc. +@@ -0,0 +1,136 @@ ++@c Copyright (C) 2011-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC @@ -738728,6 +742761,14 @@ index 0000000..0964ac4 +Mark the generated binary as targeting the G10 variant of the RL78 +architecture. + ++@item m32bit-doubles ++Mark the generated binary as one that uses 32-bits to hold the ++@code{double} floating point type. This is the default. ++ ++@item m64bit-doubles ++Mark the generated binary as one that uses 64-bits to hold the ++@code{double} floating point type. ++ +@end table + +@node RL78-Modifiers @@ -738781,8 +742822,10 @@ index 0000000..0964ac4 +@table @code + +@item .double -+Output a constant in ``double'' format, which is a 32-bit floating -+point value on RL78. ++Output a constant in ``double'' format, which is either a 32-bit ++or a 64-bit floating point value, depending upon the setting of the ++@option{-m32bit-doubles}|@option{-m64bit-doubles} command line ++option. + +@item .bss +Select the BSS section. @@ -738822,11 +742865,11 @@ index 0000000..0964ac4 +line. diff --git a/gas/doc/c-rx.texi b/gas/doc/c-rx.texi new file mode 100644 -index 0000000..2b3ab39 +index 0000000..5f24fd3 --- /dev/null +++ b/gas/doc/c-rx.texi @@ -0,0 +1,237 @@ -+@c Copyright 2008-2013 Free Software Foundation, Inc. ++@c Copyright (C) 2008-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC @@ -739065,12 +743108,11 @@ index 0000000..2b3ab39 +line. diff --git a/gas/doc/c-s390.texi b/gas/doc/c-s390.texi new file mode 100644 -index 0000000..1935fb3 +index 0000000..a4fdf4a --- /dev/null +++ b/gas/doc/c-s390.texi -@@ -0,0 +1,900 @@ -+@c Copyright 2009, 2011 -+@c Free Software Foundation, Inc. +@@ -0,0 +1,899 @@ ++@c Copyright (C) 2009-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC @@ -739971,12 +744013,11 @@ index 0000000..1935fb3 +@samp{.long} and @samp{.quad} directives must be used. diff --git a/gas/doc/c-score.texi b/gas/doc/c-score.texi new file mode 100644 -index 0000000..8335ae7 +index 0000000..73dee16 --- /dev/null +++ b/gas/doc/c-score.texi -@@ -0,0 +1,168 @@ -+@c Copyright 2009, 2011, 2013 -+@c Free Software Foundation, Inc. +@@ -0,0 +1,167 @@ ++@c Copyright (C) 2009-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC @@ -740145,12 +744186,11 @@ index 0000000..8335ae7 +line. diff --git a/gas/doc/c-sh.texi b/gas/doc/c-sh.texi new file mode 100644 -index 0000000..967cea4 +index 0000000..8e58282 --- /dev/null +++ b/gas/doc/c-sh.texi -@@ -0,0 +1,346 @@ -+@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 2001, 2003, 2004, -+@c 2005, 2008, 2010, 2011, 2012 Free Software Foundation, Inc. +@@ -0,0 +1,345 @@ ++@c Copyright (C) 1991-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@page @@ -740497,11 +744537,11 @@ index 0000000..967cea4 + diff --git a/gas/doc/c-sh64.texi b/gas/doc/c-sh64.texi new file mode 100644 -index 0000000..6857f29 +index 0000000..7ccb285 --- /dev/null +++ b/gas/doc/c-sh64.texi @@ -0,0 +1,219 @@ -+@c Copyright (C) 2002, 2003, 2008, 2011, 2012 Free Software Foundation, Inc. ++@c Copyright (C) 2002-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@page @@ -740722,13 +744762,11 @@ index 0000000..6857f29 +@end table diff --git a/gas/doc/c-sparc.texi b/gas/doc/c-sparc.texi new file mode 100644 -index 0000000..f6b9815 +index 0000000..8915528 --- /dev/null +++ b/gas/doc/c-sparc.texi -@@ -0,0 +1,876 @@ -+@c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2002, 2008, -+@c 2011 -+@c Free Software Foundation, Inc. +@@ -0,0 +1,882 @@ ++@c Copyright (C) 1991-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC @@ -741137,9 +745175,17 @@ index 0000000..f6b9815 +to as @samp{%hver}. + +@item ++The hyperprivileged system tick offset register is referred to as ++@samp{%hstick_offset}. Note that there is no @samp{%hstick} register, ++the normal @samp{%stick} is used. ++ ++@item ++The hyperprivileged system tick enable register is referred to as ++@samp{%hstick_enable}. ++ ++@item +The hyperprivileged system tick compare register is referred -+to as @samp{%hstick_cmpr}. Note that there is no @samp{%hstick} -+register, the normal @samp{%stick} is used. ++to as @samp{%hstick_cmpr}. +@end itemize + +@node Sparc-Constants @@ -741604,11 +745650,11 @@ index 0000000..f6b9815 +@end table diff --git a/gas/doc/c-tic54x.texi b/gas/doc/c-tic54x.texi new file mode 100644 -index 0000000..8a37316 +index 0000000..50b3611 --- /dev/null +++ b/gas/doc/c-tic54x.texi @@ -0,0 +1,797 @@ -+@c Copyright 2000-2013 Free Software Foundation, Inc. ++@c Copyright (C) 2000-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@c TI TMS320C54X description by Timothy Wall, twall@cygnus.com @@ -742407,11 +746453,11 @@ index 0000000..8a37316 + diff --git a/gas/doc/c-tic6x.texi b/gas/doc/c-tic6x.texi new file mode 100644 -index 0000000..a39a9a7 +index 0000000..cd44988 --- /dev/null +++ b/gas/doc/c-tic6x.texi @@ -0,0 +1,195 @@ -+@c Copyright 2010, 2011 Free Software Foundation, Inc. ++@c Copyright (C) 2010-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@c man end @@ -742608,12 +746654,11 @@ index 0000000..a39a9a7 +@end table diff --git a/gas/doc/c-tilegx.texi b/gas/doc/c-tilegx.texi new file mode 100644 -index 0000000..0d8c038 +index 0000000..528ae7f --- /dev/null +++ b/gas/doc/c-tilegx.texi -@@ -0,0 +1,363 @@ -+@c Copyright 2011 -+@c Free Software Foundation, Inc. +@@ -0,0 +1,362 @@ ++@c Copyright (C) 2011-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@c man end @@ -742977,12 +747022,11 @@ index 0000000..0d8c038 +@end table diff --git a/gas/doc/c-tilepro.texi b/gas/doc/c-tilepro.texi new file mode 100644 -index 0000000..5d80c4f +index 0000000..a8989ab --- /dev/null +++ b/gas/doc/c-tilepro.texi -@@ -0,0 +1,332 @@ -+@c Copyright 2011 -+@c Free Software Foundation, Inc. +@@ -0,0 +1,331 @@ ++@c Copyright (C) 2011-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC @@ -743315,11 +747359,11 @@ index 0000000..5d80c4f + diff --git a/gas/doc/c-v850.texi b/gas/doc/c-v850.texi new file mode 100644 -index 0000000..2516a83 +index 0000000..7fe3719 --- /dev/null +++ b/gas/doc/c-v850.texi @@ -0,0 +1,475 @@ -+@c Copyright 1997-2013 Free Software Foundation, Inc. ++@c Copyright (C) 1997-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. + @@ -743796,12 +747840,11 @@ index 0000000..2516a83 +Ltd. diff --git a/gas/doc/c-vax.texi b/gas/doc/c-vax.texi new file mode 100644 -index 0000000..9eacd10 +index 0000000..1df7453 --- /dev/null +++ b/gas/doc/c-vax.texi -@@ -0,0 +1,384 @@ -+@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1998, 2002, 2011 -+@c Free Software Foundation, Inc. +@@ -0,0 +1,383 @@ ++@c Copyright (C) 1991-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@c VAX/VMS description enhanced and corrected by Klaus K"aempf, kkaempf@progis.de @@ -744186,11 +748229,11 @@ index 0000000..9eacd10 +line. diff --git a/gas/doc/c-xc16x.texi b/gas/doc/c-xc16x.texi new file mode 100644 -index 0000000..9589139 +index 0000000..fd5ff7f --- /dev/null +++ b/gas/doc/c-xc16x.texi @@ -0,0 +1,80 @@ -+@c Copyright 2006, 2011 Free Software Foundation, Inc. ++@c Copyright (C) 2006-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. + @@ -744272,12 +748315,11 @@ index 0000000..9589139 +The XC16X assembler does not support a line separator character. diff --git a/gas/doc/c-xgate.texi b/gas/doc/c-xgate.texi new file mode 100644 -index 0000000..360554f +index 0000000..46b9480 --- /dev/null +++ b/gas/doc/c-xgate.texi -@@ -0,0 +1,209 @@ -+@c Copyright 2012 -+@c Free Software Foundation, Inc. +@@ -0,0 +1,208 @@ ++@c Copyright (C) 2012-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC @@ -744487,11 +748529,11 @@ index 0000000..360554f + diff --git a/gas/doc/c-xstormy16.texi b/gas/doc/c-xstormy16.texi new file mode 100644 -index 0000000..31ba6f9 +index 0000000..5196537 --- /dev/null +++ b/gas/doc/c-xstormy16.texi @@ -0,0 +1,104 @@ -+@c Copyright 2010, 2011 Free Software Foundation, Inc. ++@c Copyright (C) 2010-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. + @@ -744597,12 +748639,11 @@ index 0000000..31ba6f9 +@end table diff --git a/gas/doc/c-xtensa.texi b/gas/doc/c-xtensa.texi new file mode 100644 -index 0000000..bf5b38b +index 0000000..e763e36 --- /dev/null +++ b/gas/doc/c-xtensa.texi -@@ -0,0 +1,820 @@ -+@c Copyright (C) 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2011 -+@c Free Software Foundation, Inc. +@@ -0,0 +1,911 @@ ++@c Copyright (C) 2002-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@c @@ -744695,6 +748736,16 @@ index 0000000..bf5b38b +@kindex --rename-section +Rename the @var{oldname} section to @var{newname}. This option can be used +multiple times to rename multiple sections. ++ ++@item --trampolines | --no-trampolines ++@kindex --trampolines ++@kindex --no-trampolines ++Enable or disable transformation of jump instructions to allow jumps ++across a greater range of addresses. @xref{Xtensa Jump Relaxation, ++,Jump Trampolines}. This option should be used when jump targets can ++potentially be out of range. In the absence of such jumps this option ++does not affect code size or performance. The default is ++@samp{--trampolines}. +@end table + +@c man end @@ -744915,6 +748966,7 @@ index 0000000..bf5b38b +@menu +* Xtensa Branch Relaxation:: Relaxation of Branches. +* Xtensa Call Relaxation:: Relaxation of Function Calls. ++* Xtensa Jump Relaxation:: Relaxation of Jumps. +* Xtensa Immediate Relaxation:: Relaxation of other Immediate Fields. +@end menu + @@ -745002,6 +749054,87 @@ index 0000000..bf5b38b +enabled using the @samp{--longcalls} command-line option or the +@code{longcalls} directive (@pxref{Longcalls Directive, ,longcalls}). + ++@node Xtensa Jump Relaxation ++@subsection Jump Relaxation ++@cindex relaxation of jump instructions ++@cindex jump instructions, relaxation ++ ++Jump instruction may require relaxation because the Xtensa jump instruction ++(@code{J}) provide a PC-relative offset of only 128 Kbytes in either ++direction. One option is to use jump long (@code{J.L}) instruction, which ++depending on jump distance may be assembled as jump (@code{J}) or indirect ++jump (@code{JX}). However it needs a free register. When there's no spare ++register it is possible to plant intermediate jump sites (trampolines) ++between the jump instruction and its target. These sites may be located in ++areas unreachable by normal code execution flow, in that case they only ++contain intermediate jumps, or they may be inserted in the middle of code ++block, in which case there's an additional jump from the beginning of the ++trampoline to the instruction past its end. So, for example: ++ ++@smallexample ++@group ++ j 1f ++ ... ++ retw ++ ... ++ mov a10, a2 ++ call8 func ++ ... ++1: ++ ... ++@end group ++@end smallexample ++ ++might be relaxed to: ++ ++@smallexample ++@group ++ j .L0_TR_1 ++ ... ++ retw ++.L0_TR_1: ++ j 1f ++ ... ++ mov a10, a2 ++ call8 func ++ ... ++1: ++ ... ++@end group ++@end smallexample ++ ++or to: ++ ++@smallexample ++@group ++ j .L0_TR_1 ++ ... ++ retw ++ ... ++ mov a10, a2 ++ j .L0_TR_0 ++.L0_TR_1: ++ j 1f ++.L0_TR_0: ++ call8 func ++ ... ++1: ++ ... ++@end group ++@end smallexample ++ ++The Xtensa assempler uses trampolines with jump around only when it cannot ++find suitable unreachable trampoline. There may be multiple trampolines ++between the jump instruction and its target. ++ ++This relaxation does not apply to jumps to undefined symbols, assuming they ++will reach their targets once resolved. ++ ++Jump relaxation is enabled by default because it does not affect code size ++or performance while the code itself is small. This relaxation may be ++disabled completely with @samp{--no-trampolines} or @samp{--no-transform} ++command-line options (@pxref{Xtensa Options, ,Command Line Options}). ++ +@node Xtensa Immediate Relaxation +@subsection Other Immediate Field Relaxation +@cindex immediate fields, relaxation @@ -745423,11 +749556,11 @@ index 0000000..bf5b38b +@c End: diff --git a/gas/doc/c-z80.texi b/gas/doc/c-z80.texi new file mode 100644 -index 0000000..df5a65f +index 0000000..4e1f91c --- /dev/null +++ b/gas/doc/c-z80.texi @@ -0,0 +1,268 @@ -+@c Copyright 2011 Free Software Foundation, Inc. ++@c Copyright (C) 2011-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. + @@ -745697,12 +749830,11 @@ index 0000000..df5a65f + diff --git a/gas/doc/c-z8k.texi b/gas/doc/c-z8k.texi new file mode 100644 -index 0000000..51f00e1 +index 0000000..bc20150 --- /dev/null +++ b/gas/doc/c-z8k.texi -@@ -0,0 +1,405 @@ -+@c Copyright 1991, 1992, 1993, 1994, 1995, 2003, 2011 -+@c Free Software Foundation, Inc. +@@ -0,0 +1,404 @@ ++@c Copyright (C) 1991-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. +@ifset GENERIC @@ -746620,12 +750752,11 @@ index 0000000..8805f1a + diff --git a/gas/doc/h8.texi b/gas/doc/h8.texi new file mode 100644 -index 0000000..2b9e9dd +index 0000000..59e5135 --- /dev/null +++ b/gas/doc/h8.texi -@@ -0,0 +1,31 @@ -+@c Copyright 2012 -+@c Free Software Foundation, Inc. +@@ -0,0 +1,30 @@ ++@c Copyright (C) 2012-2014 Free Software Foundation, Inc. +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. + @@ -746657,14 +750788,12 @@ index 0000000..2b9e9dd +@set abnormal-separator diff --git a/gas/doc/internals.texi b/gas/doc/internals.texi new file mode 100644 -index 0000000..cf15fb5 +index 0000000..76f812d --- /dev/null +++ b/gas/doc/internals.texi -@@ -0,0 +1,1990 @@ +@@ -0,0 +1,1997 @@ +\input texinfo -+@c Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, -+@c 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 -+@c Free Software Foundation, Inc. ++@c Copyright (C) 1991-2014 Free Software Foundation, Inc. +@setfilename internals.info +@node Top +@top Assembler Internals @@ -747549,6 +751678,8 @@ index 0000000..cf15fb5 +@item tc_comment_chars +@cindex tc_comment_chars +If this macro is defined, GAS will use it instead of @code{comment_chars}. ++This has the advantage that this macro does not have to refer to a constant ++array. + +@item tc_symbol_chars +@cindex tc_symbol_chars @@ -747573,6 +751704,13 @@ index 0000000..cf15fb5 +if found in a comment, such as after a character in line_comment_chars or +comment_chars. + ++@item tc_line_separator_chars ++@cindex tc_line_separator_chars ++If this macro is defined, GAS will use it instead of ++@code{line_separator_chars}. This has the advantage that this macro does not ++have to refer to a constant array. ++ ++ +@item EXP_CHARS +@cindex EXP_CHARS +This is a null terminated @code{const char} array of characters which may be @@ -748653,13 +752791,12 @@ index 0000000..cf15fb5 +@c End: diff --git a/gas/dw2gencfi.c b/gas/dw2gencfi.c new file mode 100644 -index 0000000..faa8384 +index 0000000..c282705 --- /dev/null +++ b/gas/dw2gencfi.c -@@ -0,0 +1,2044 @@ +@@ -0,0 +1,2043 @@ +/* dw2gencfi.c - Support for generating Dwarf2 CFI information. -+ Copyright 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 -+ Free Software Foundation, Inc. ++ Copyright (C) 2003-2014 Free Software Foundation, Inc. + Contributed by Michal Ludvig + + This file is part of GAS, the GNU Assembler. @@ -750703,12 +754840,12 @@ index 0000000..faa8384 +#endif /* TARGET_USE_CFIPOP */ diff --git a/gas/dw2gencfi.h b/gas/dw2gencfi.h new file mode 100644 -index 0000000..7f83496 +index 0000000..8ce9819 --- /dev/null +++ b/gas/dw2gencfi.h @@ -0,0 +1,132 @@ +/* dw2gencfi.h - Support for generating Dwarf2 CFI information. -+ Copyright 2003, 2004, 2005, 2007, 2009 Free Software Foundation, Inc. ++ Copyright (C) 2003-2014 Free Software Foundation, Inc. + Contributed by Michal Ludvig + + This file is part of GAS, the GNU Assembler. @@ -750841,12 +754978,12 @@ index 0000000..7f83496 +#endif /* DW2GENCFI_H */ diff --git a/gas/dwarf2dbg.c b/gas/dwarf2dbg.c new file mode 100644 -index 0000000..6d6ee2d +index 0000000..5cc4662 --- /dev/null +++ b/gas/dwarf2dbg.c -@@ -0,0 +1,1944 @@ +@@ -0,0 +1,1952 @@ +/* dwarf2dbg.c - DWARF2 debug support -+ Copyright 1999-2013 Free Software Foundation, Inc. ++ Copyright (C) 1999-2014 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang + + This file is part of GAS, the GNU Assembler. @@ -751005,6 +755142,10 @@ index 0000000..6d6ee2d +/* The maximum address skip amount that can be encoded with a special op. */ +#define MAX_SPECIAL_ADDR_DELTA SPECIAL_ADDR(255) + ++#ifndef TC_PARSE_CONS_RETURN_NONE ++#define TC_PARSE_CONS_RETURN_NONE BFD_RELOC_NONE ++#endif ++ +struct line_entry { + struct line_entry *next; + symbolS *label; @@ -751991,13 +756132,13 @@ index 0000000..6d6ee2d + exp.X_op = O_symbol; + exp.X_add_symbol = to_sym; + exp.X_add_number = 0; -+ emit_expr_fix (&exp, sizeof_address, frag, p); ++ emit_expr_fix (&exp, sizeof_address, frag, p, TC_PARSE_CONS_RETURN_NONE); + p += sizeof_address; + } + else + { + *p++ = DW_LNS_fixed_advance_pc; -+ emit_expr_fix (pexp, 2, frag, p); ++ emit_expr_fix (pexp, 2, frag, p, TC_PARSE_CONS_RETURN_NONE); + p += 2; + } + @@ -752362,7 +756503,7 @@ index 0000000..6d6ee2d +out_debug_line (segT line_seg) +{ + expressionS exp; -+ symbolS *prologue_end; ++ symbolS *prologue_start, *prologue_end; + symbolS *line_end; + struct line_seg *s; + int sizeof_offset; @@ -752374,10 +756515,14 @@ index 0000000..6d6ee2d + out_two (DWARF2_LINE_VERSION); + + /* Length of the prologue following this length. */ ++ prologue_start = symbol_temp_make (); + prologue_end = symbol_temp_make (); ++ exp.X_op = O_subtract; + exp.X_add_symbol = prologue_end; -+ exp.X_add_number = - (4 + 2 + 4); ++ exp.X_op_symbol = prologue_start; ++ exp.X_add_number = 0; + emit_expr (&exp, sizeof_offset); ++ symbol_set_value_now (prologue_start); + + /* Parameters of the state machine. */ + out_byte (DWARF2_LINE_MIN_INSN_LENGTH); @@ -752791,13 +756936,12 @@ index 0000000..6d6ee2d +} diff --git a/gas/dwarf2dbg.h b/gas/dwarf2dbg.h new file mode 100644 -index 0000000..84ef8f6 +index 0000000..fdb185f --- /dev/null +++ b/gas/dwarf2dbg.h -@@ -0,0 +1,116 @@ +@@ -0,0 +1,115 @@ +/* dwarf2dbg.h - DWARF2 debug support -+ Copyright 1999, 2000, 2002, 2003, 2005, 2006, 2007, 2009 -+ Free Software Foundation, Inc. ++ Copyright (C) 1999-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -752913,14 +757057,12 @@ index 0000000..84ef8f6 +#endif /* AS_DWARF2DBG_H */ diff --git a/gas/ecoff.c b/gas/ecoff.c new file mode 100644 -index 0000000..821b02c +index 0000000..771c8b5 --- /dev/null +++ b/gas/ecoff.c -@@ -0,0 +1,5244 @@ +@@ -0,0 +1,5242 @@ +/* ECOFF debugging support. -+ Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, -+ 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1993-2014 Free Software Foundation, Inc. + Contributed by Cygnus Support. + This file was put together by Ian Lance Taylor . A + good deal of it comes directly from mips-tfile.c, by Michael @@ -758163,13 +762305,12 @@ index 0000000..821b02c +#endif /* ECOFF_DEBUGGING */ diff --git a/gas/ecoff.h b/gas/ecoff.h new file mode 100644 -index 0000000..f4f8356 +index 0000000..02bc747 --- /dev/null +++ b/gas/ecoff.h -@@ -0,0 +1,113 @@ +@@ -0,0 +1,112 @@ +/* ecoff.h -- header file for ECOFF debugging support -+ Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2003, 2004, 2005, -+ 2007, 2009 Free Software Foundation, Inc. ++ Copyright (C) 1993-2014 Free Software Foundation, Inc. + Contributed by Cygnus Support. + Put together by Ian Lance Taylor . + @@ -758282,13 +762423,12 @@ index 0000000..f4f8356 +#endif /* ! GAS_ECOFF_H */ diff --git a/gas/ehopt.c b/gas/ehopt.c new file mode 100644 -index 0000000..70e1a00 +index 0000000..56756ff --- /dev/null +++ b/gas/ehopt.c -@@ -0,0 +1,557 @@ +@@ -0,0 +1,556 @@ +/* ehopt.c--optimize gcc exception frame information. -+ Copyright 1998, 2000, 2001, 2003, 2005, 2007, 2008, 2009 -+ Free Software Foundation, Inc. ++ Copyright (C) 1998-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor . + + This file is part of GAS, the GNU Assembler. @@ -758845,12 +762985,12 @@ index 0000000..70e1a00 +} diff --git a/gas/emul-target.h b/gas/emul-target.h new file mode 100644 -index 0000000..d6069eb +index 0000000..6faae47 --- /dev/null +++ b/gas/emul-target.h @@ -0,0 +1,64 @@ +/* emul-target.h. Default values for struct emulation defined in emul.h -+ Copyright 1995, 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 1995-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -758915,12 +763055,12 @@ index 0000000..d6069eb + }; diff --git a/gas/emul.h b/gas/emul.h new file mode 100644 -index 0000000..4080364 +index 0000000..2a07a58 --- /dev/null +++ b/gas/emul.h @@ -0,0 +1,44 @@ +/* emul.h. File format emulation routines -+ Copyright 1995, 2003, 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 1995-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -758965,14 +763105,12 @@ index 0000000..4080364 +#endif diff --git a/gas/expr.c b/gas/expr.c new file mode 100644 -index 0000000..c4b2b75 +index 0000000..b39c70d --- /dev/null +++ b/gas/expr.c -@@ -0,0 +1,2367 @@ +@@ -0,0 +1,2365 @@ +/* expr.c -operands, expressions- -+ Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, -+ 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2009, 2010, 2011, -+ 2012 Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -761338,13 +765476,12 @@ index 0000000..c4b2b75 +} diff --git a/gas/expr.h b/gas/expr.h new file mode 100644 -index 0000000..438ac0d +index 0000000..d5eb286 --- /dev/null +++ b/gas/expr.h -@@ -0,0 +1,189 @@ +@@ -0,0 +1,188 @@ +/* expr.h -> header file for expr.c -+ Copyright 1987, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, -+ 2002, 2003, 2005, 2007, 2009 Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -761533,13 +765670,12 @@ index 0000000..438ac0d +int resolve_expression (expressionS *); diff --git a/gas/flonum-copy.c b/gas/flonum-copy.c new file mode 100644 -index 0000000..c1131b1 +index 0000000..15b2a59 --- /dev/null +++ b/gas/flonum-copy.c -@@ -0,0 +1,71 @@ +@@ -0,0 +1,70 @@ +/* flonum_copy.c - copy a flonum -+ Copyright 1987, 1990, 1991, 1992, 1993, 2000, 2003, 2005, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -761610,13 +765746,12 @@ index 0000000..c1131b1 +} diff --git a/gas/flonum-konst.c b/gas/flonum-konst.c new file mode 100644 -index 0000000..cb60bea +index 0000000..86865c7 --- /dev/null +++ b/gas/flonum-konst.c -@@ -0,0 +1,228 @@ +@@ -0,0 +1,227 @@ +/* flonum_const.c - Useful Flonum constants -+ Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 2000, 2002, -+ 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -761844,13 +765979,12 @@ index 0000000..cb60bea +#endif diff --git a/gas/flonum-mult.c b/gas/flonum-mult.c new file mode 100644 -index 0000000..e5f32fc +index 0000000..c9aeebd --- /dev/null +++ b/gas/flonum-mult.c -@@ -0,0 +1,188 @@ +@@ -0,0 +1,187 @@ +/* flonum_mult.c - multiply two flonums -+ Copyright 1987, 1990, 1991, 1992, 1995, 2000, 2002, 2003, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -762038,13 +766172,12 @@ index 0000000..e5f32fc +} diff --git a/gas/flonum.h b/gas/flonum.h new file mode 100644 -index 0000000..c27dd22 +index 0000000..fc9f7af --- /dev/null +++ b/gas/flonum.h -@@ -0,0 +1,102 @@ +@@ -0,0 +1,101 @@ +/* flonum.h - Floating point package -+ Copyright 1987, 1990, 1991, 1992, 1994, 1996, 2000, 2003, 2005, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -762146,14 +766279,12 @@ index 0000000..c27dd22 +#define ERROR_EXPONENT_OVERFLOW (2) diff --git a/gas/frags.c b/gas/frags.c new file mode 100644 -index 0000000..beb251b +index 0000000..e14099d --- /dev/null +++ b/gas/frags.c -@@ -0,0 +1,445 @@ +@@ -0,0 +1,458 @@ +/* frags.c - manage frags - -+ Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, -+ 1999, 2000, 2001, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2011, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -762178,6 +766309,20 @@ index 0000000..beb251b + +extern fragS zero_address_frag; +extern fragS predefined_address_frag; ++ ++static int totalfrags; ++ ++int ++get_frag_count (void) ++{ ++ return totalfrags; ++} ++ ++void ++clear_frag_count (void) ++{ ++ totalfrags = 0; ++} + +/* Initialization for frag routines. */ + @@ -762224,6 +766369,7 @@ index 0000000..beb251b + ptr = (fragS *) obstack_alloc (ob, SIZEOF_STRUCT_FRAG); + obstack_alignment_mask (ob) = oalign; + memset (ptr, 0, SIZEOF_STRUCT_FRAG); ++ totalfrags++; + return ptr; +} + @@ -762597,14 +766743,12 @@ index 0000000..beb251b +} diff --git a/gas/frags.h b/gas/frags.h new file mode 100644 -index 0000000..f5846be +index 0000000..2f9e1b5 --- /dev/null +++ b/gas/frags.h -@@ -0,0 +1,160 @@ +@@ -0,0 +1,161 @@ +/* frags.h - Header file for the frag concept. -+ Copyright 1987, 1992, 1993, 1994, 1995, 1997, 1998, 1999, 2000, 2001, -+ 2002, 2003, 2004, 2005, 2006, 2007, 2010, 2011, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -762760,6 +766904,9 @@ index 0000000..f5846be + +bfd_boolean frag_offset_fixed_p (const fragS *, const fragS *, offsetT *); + ++int get_frag_count (void); ++void clear_frag_count (void); ++ +#endif /* FRAGS_H */ diff --git a/gas/gdbinit.in b/gas/gdbinit.in new file mode 100644 @@ -762807,14 +766954,12 @@ index 0000000..fb1046d +break abort diff --git a/gas/hash.c b/gas/hash.c new file mode 100644 -index 0000000..bae8386 +index 0000000..9a57784 --- /dev/null +++ b/gas/hash.c -@@ -0,0 +1,597 @@ +@@ -0,0 +1,595 @@ +/* hash.c -- gas hash table code -+ Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, -+ 2000, 2001, 2002, 2003, 2005, 2007, 2008, 2009, 2011, 2013 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -763410,13 +767555,12 @@ index 0000000..bae8386 +#endif /* TEST */ diff --git a/gas/hash.h b/gas/hash.h new file mode 100644 -index 0000000..c7ea7b5 +index 0000000..881dcf1 --- /dev/null +++ b/gas/hash.h -@@ -0,0 +1,89 @@ +@@ -0,0 +1,88 @@ +/* hash.h -- header file for gas hash table routines -+ Copyright 1987, 1992, 1993, 1995, 1999, 2003, 2005, 2007, 2008, 2013 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -763505,14 +767649,12 @@ index 0000000..c7ea7b5 +#endif /* HASH_H */ diff --git a/gas/input-file.c b/gas/input-file.c new file mode 100644 -index 0000000..ecf1b44 +index 0000000..354ff56 --- /dev/null +++ b/gas/input-file.c -@@ -0,0 +1,259 @@ +@@ -0,0 +1,257 @@ +/* input_file.c - Deal with Input Files - -+ Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1999, 2000, 2001, -+ 2002, 2003, 2005, 2006, 2007, 2009, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -763770,13 +767912,12 @@ index 0000000..ecf1b44 +} diff --git a/gas/input-file.h b/gas/input-file.h new file mode 100644 -index 0000000..7148cc5 +index 0000000..7f7b65f --- /dev/null +++ b/gas/input-file.h -@@ -0,0 +1,66 @@ +@@ -0,0 +1,65 @@ +/* input_file.h header for input-file.c -+ Copyright 1987, 1992, 1993, 2000, 2003, 2005, 2006, 2007, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -763842,14 +767983,12 @@ index 0000000..7148cc5 +void input_file_pop (char *arg); diff --git a/gas/input-scrub.c b/gas/input-scrub.c new file mode 100644 -index 0000000..adae4d4 +index 0000000..042005a --- /dev/null +++ b/gas/input-scrub.c -@@ -0,0 +1,523 @@ +@@ -0,0 +1,521 @@ +/* input_scrub.c - Break up input buffers into whole numbers of lines. -+ Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, -+ 2000, 2001, 2003, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -764371,11 +768510,11 @@ index 0000000..adae4d4 +} diff --git a/gas/itbl-lex-wrapper.c b/gas/itbl-lex-wrapper.c new file mode 100644 -index 0000000..c60459f +index 0000000..0f4e26b --- /dev/null +++ b/gas/itbl-lex-wrapper.c @@ -0,0 +1,25 @@ -+/* Copyright 2012 Free Software Foundation, Inc. ++/* Copyright (C) 2012-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -764402,12 +768541,12 @@ index 0000000..c60459f +#include "itbl-lex.c" diff --git a/gas/itbl-lex.h b/gas/itbl-lex.h new file mode 100644 -index 0000000..03af699 +index 0000000..f6a3246 --- /dev/null +++ b/gas/itbl-lex.h @@ -0,0 +1,23 @@ +/* itbl-lex.h -+ Copyright 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 2005-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -764431,13 +768570,12 @@ index 0000000..03af699 +extern int yylex (void); diff --git a/gas/itbl-lex.l b/gas/itbl-lex.l new file mode 100644 -index 0000000..7893a57 +index 0000000..77f3239 --- /dev/null +++ b/gas/itbl-lex.l -@@ -0,0 +1,113 @@ +@@ -0,0 +1,112 @@ +/* itbl-lex.l -+ Copyright 1997, 1998, 2001, 2002, 2005, 2006, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1997-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -764550,13 +768688,12 @@ index 0000000..7893a57 +#endif diff --git a/gas/itbl-ops.c b/gas/itbl-ops.c new file mode 100644 -index 0000000..e97a636 +index 0000000..24b255f --- /dev/null +++ b/gas/itbl-ops.c -@@ -0,0 +1,891 @@ +@@ -0,0 +1,890 @@ +/* itbl-ops.c -+ Copyright 1997, 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007, -+ 2009, 2010 Free Software Foundation, Inc. ++ Copyright (C) 1997-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -765447,13 +769584,12 @@ index 0000000..e97a636 +} diff --git a/gas/itbl-ops.h b/gas/itbl-ops.h new file mode 100644 -index 0000000..52338b3 +index 0000000..c443e06 --- /dev/null +++ b/gas/itbl-ops.h -@@ -0,0 +1,101 @@ +@@ -0,0 +1,100 @@ +/* itbl-ops.h -+ Copyright 1997, 1999, 2000, 2003, 2005, 2006, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1997-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -765554,12 +769690,12 @@ index 0000000..52338b3 + int sbit, int ebit, unsigned long flags); diff --git a/gas/itbl-parse.y b/gas/itbl-parse.y new file mode 100644 -index 0000000..cf757fb +index 0000000..17c7803 --- /dev/null +++ b/gas/itbl-parse.y @@ -0,0 +1,458 @@ +/* itbl-parse.y -+ Copyright 1997, 2002, 2003, 2005, 2006, 2007 Free Software Foundation, Inc. ++ Copyright (C) 1997-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -766018,14 +770154,12 @@ index 0000000..cf757fb +} diff --git a/gas/listing.c b/gas/listing.c new file mode 100644 -index 0000000..182d504 +index 0000000..0192dd0 --- /dev/null +++ b/gas/listing.c -@@ -0,0 +1,1660 @@ +@@ -0,0 +1,1658 @@ +/* listing.c - maintain assembly listings -+ Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, -+ 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009, 2010 -+ Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -766279,13 +770413,13 @@ index 0000000..182d504 +void +listing_warning (const char *message) +{ -+ listing_message (_("Warning:"), message); ++ listing_message (_("Warning: "), message); +} + +void +listing_error (const char *message) +{ -+ listing_message (_("Error:"), message); ++ listing_message (_("Error: "), message); +} + +static file_info_type * @@ -767684,13 +771818,12 @@ index 0000000..182d504 +#endif diff --git a/gas/listing.h b/gas/listing.h new file mode 100644 -index 0000000..79afdac +index 0000000..af20082 --- /dev/null +++ b/gas/listing.h -@@ -0,0 +1,67 @@ +@@ -0,0 +1,66 @@ +/* This file is listing.h -+ Copyright 1987, 1988, 1989, 1990, 1991, 1992, 1993, 1995, 1997, 1998, -+ 2003, 2005, 2007, 2008, 2009 Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -767757,12 +771890,12 @@ index 0000000..79afdac +/* end of listing.h */ diff --git a/gas/literal.c b/gas/literal.c new file mode 100644 -index 0000000..6cbbe7e +index 0000000..b2a9dde --- /dev/null +++ b/gas/literal.c @@ -0,0 +1,96 @@ +/* literal.c - GAS literal pool management. -+ Copyright 1994, 2000, 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 1994-2014 Free Software Foundation, Inc. + Written by Ken Raeburn (raeburn@cygnus.com). + + This file is part of GAS, the GNU Assembler. @@ -767859,13 +771992,12 @@ index 0000000..6cbbe7e +#endif diff --git a/gas/macro.c b/gas/macro.c new file mode 100644 -index 0000000..75b9b7e +index 0000000..4589bd8 --- /dev/null +++ b/gas/macro.c -@@ -0,0 +1,1382 @@ +@@ -0,0 +1,1381 @@ +/* macro.c - macro support for gas -+ Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, -+ 2004, 2005, 2006, 2007, 2008, 2011, 2012, 2013 Free Software Foundation, Inc. ++ Copyright (C) 1994-2014 Free Software Foundation, Inc. + + Written by Steve and Judy Chamberlain of Cygnus Support, + sac@cygnus.com @@ -769247,13 +773379,12 @@ index 0000000..75b9b7e +} diff --git a/gas/macro.h b/gas/macro.h new file mode 100644 -index 0000000..b109178 +index 0000000..133c4c9 --- /dev/null +++ b/gas/macro.h -@@ -0,0 +1,97 @@ +@@ -0,0 +1,96 @@ +/* macro.h - header file for macro support for gas -+ Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2002, 2003, 2004, 2005, 2006, -+ 2007, 2012 Free Software Foundation, Inc. ++ Copyright (C) 1994-2014 Free Software Foundation, Inc. + + Written by Steve and Judy Chamberlain of Cygnus Support, + sac@cygnus.com @@ -769350,7 +773481,7 @@ index 0000000..b109178 +#endif diff --git a/gas/makefile.vms b/gas/makefile.vms new file mode 100644 -index 0000000..b7c29c8 +index 0000000..6047fd0 --- /dev/null +++ b/gas/makefile.vms @@ -0,0 +1,79 @@ @@ -769359,7 +773490,7 @@ index 0000000..b7c29c8 +# +# Created by Klaus Kaempf, kkaempf@progis.de +# -+# Copyright 2012 Free Software Foundation ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -769435,14 +773566,12 @@ index 0000000..b7c29c8 + $(RM) targ-cpu.c; diff --git a/gas/messages.c b/gas/messages.c new file mode 100644 -index 0000000..e1734f2 +index 0000000..2865c9d --- /dev/null +++ b/gas/messages.c -@@ -0,0 +1,440 @@ +@@ -0,0 +1,436 @@ +/* messages.c - error reporter - -+ Copyright 1987, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 2000, 2001, -+ 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify @@ -769594,13 +773723,12 @@ index 0000000..e1734f2 + if (file) + { + if (line != 0) -+ fprintf (stderr, "%s:%u: ", file, line); ++ fprintf (stderr, "%s:%u: %s%s\n", file, line, _("Warning: "), buffer); + else -+ fprintf (stderr, "%s: ", file); ++ fprintf (stderr, "%s: %s%s\n", file, _("Warning: "), buffer); + } -+ fprintf (stderr, _("Warning: ")); -+ fputs (buffer, stderr); -+ (void) putc ('\n', stderr); ++ else ++ fprintf (stderr, "%s%s\n", _("Warning: "), buffer); +#ifndef NO_LISTING + listing_warning (buffer); +#endif @@ -769660,13 +773788,12 @@ index 0000000..e1734f2 + if (file) + { + if (line != 0) -+ fprintf (stderr, "%s:%u: ", file, line); ++ fprintf (stderr, "%s:%u: %s%s\n", file, line, _("Error: "), buffer); + else -+ fprintf (stderr, "%s: ", file); ++ fprintf (stderr, "%s: %s%s\n", file, _("Error: "), buffer); + } -+ fprintf (stderr, _("Error: ")); -+ fputs (buffer, stderr); -+ (void) putc ('\n', stderr); ++ else ++ fprintf (stderr, "%s%s\n", _("Error: "), buffer); +#ifndef NO_LISTING + listing_error (buffer); +#endif @@ -769881,15 +774008,14 @@ index 0000000..e1734f2 +} diff --git a/gas/obj.h b/gas/obj.h new file mode 100644 -index 0000000..c2d4836 +index 0000000..f97c615 --- /dev/null +++ b/gas/obj.h -@@ -0,0 +1,87 @@ +@@ -0,0 +1,86 @@ +/* obj.h - defines the object dependent hooks for all object + format backends. + -+ Copyright 1987, 1990, 1991, 1992, 1993, 1995, 1996, 1997, 1999, 2000, -+ 2002, 2003, 2004, 2005, 2007, 2009, 2010 Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -769974,13 +774100,12 @@ index 0000000..c2d4836 +/* end of obj.h */ diff --git a/gas/output-file.c b/gas/output-file.c new file mode 100644 -index 0000000..25bd291 +index 0000000..d52fe16 --- /dev/null +++ b/gas/output-file.c -@@ -0,0 +1,74 @@ +@@ -0,0 +1,73 @@ +/* output-file.c - Deal with the output file -+ Copyright 1987, 1990, 1991, 1992, 1993, 1994, 1996, 1998, 1999, 2001, -+ 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -770054,14 +774179,13 @@ index 0000000..25bd291 +} diff --git a/gas/output-file.h b/gas/output-file.h new file mode 100644 -index 0000000..d276d28 +index 0000000..28022ef --- /dev/null +++ b/gas/output-file.h -@@ -0,0 +1,26 @@ +@@ -0,0 +1,25 @@ +/* This file is output-file.h + -+ Copyright 1987, 1988, 1989, 1990, 1991, 1992, 2003, 2005, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -770086,13 +774210,13 @@ index 0000000..d276d28 +/* end of output-file.h */ diff --git a/gas/po/Make-in b/gas/po/Make-in new file mode 100644 -index 0000000..f8f6525 +index 0000000..dafc461 --- /dev/null +++ b/gas/po/Make-in @@ -0,0 +1,258 @@ +# Makefile for program source directory in GNU NLS utilities package. +# Copyright (C) 1995, 1996, 1997 by Ulrich Drepper -+# Copyright 2003, 2006, 2007, 2009 Free Software Foundation, Inc. ++# Copyright (C) 2003-2014 Free Software Foundation, Inc. +# +# This file may be copied and used freely without restrictions. It can +# be used in projects which are not available under the GNU Public License @@ -770350,7 +774474,7 @@ index 0000000..f8f6525 +.NOEXPORT: diff --git a/gas/po/POTFILES.in b/gas/po/POTFILES.in new file mode 100644 -index 0000000..a77439b +index 0000000..dc63835 --- /dev/null +++ b/gas/po/POTFILES.in @@ -0,0 +1,261 @@ @@ -770471,14 +774595,14 @@ index 0000000..a77439b +config/tc-msp430.h +config/tc-mt.c +config/tc-mt.h ++config/tc-nds32.c ++config/tc-nds32.h +config/tc-nios2.c +config/tc-nios2.h +config/tc-ns32k.c +config/tc-ns32k.h -+config/tc-openrisc.c -+config/tc-openrisc.h -+config/tc-or32.c -+config/tc-or32.h ++config/tc-or1k.c ++config/tc-or1k.h +config/tc-pdp11.c +config/tc-pdp11.h +config/tc-pj.c @@ -825833,10 +829957,10 @@ index 0000000..80eee53 +#~ msgstr "sections invalides pour une opération sur « %s » et « %s » initialisant « %s »" diff --git a/gas/po/gas.pot b/gas/po/gas.pot new file mode 100644 -index 0000000..f1eec3b +index 0000000..622d08b --- /dev/null +++ b/gas/po/gas.pot -@@ -0,0 +1,17365 @@ +@@ -0,0 +1,19388 @@ +# SOME DESCRIPTIVE TITLE. +# Copyright (C) YEAR THE PACKAGE'S COPYRIGHT HOLDER +# This file is distributed under the same license as the PACKAGE package. @@ -825847,7 +829971,7 @@ index 0000000..f1eec3b +msgstr "" +"Project-Id-Version: PACKAGE VERSION\n" +"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n" -+"POT-Creation-Date: 2011-10-25 12:00+0100\n" ++"POT-Creation-Date: 2014-02-10 09:42+1030\n" +"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" +"Last-Translator: FULL NAME \n" +"Language-Team: LANGUAGE \n" @@ -825856,64 +829980,64 @@ index 0000000..f1eec3b +"Content-Type: text/plain; charset=CHARSET\n" +"Content-Transfer-Encoding: 8bit\n" + -+#: app.c:488 app.c:502 ++#: app.c:489 app.c:503 +msgid "end of file in comment" +msgstr "" + -+#: app.c:580 app.c:627 ++#: app.c:581 app.c:628 +#, c-format +msgid "end of file in string; '%c' inserted" +msgstr "" + -+#: app.c:653 ++#: app.c:654 +#, c-format +msgid "unknown escape '\\%c' in string; ignored" +msgstr "" + -+#: app.c:826 ++#: app.c:827 +msgid "end of file not at end of a line; newline inserted" +msgstr "" + -+#: app.c:989 ++#: app.c:990 +msgid "end of file in multiline comment" +msgstr "" + -+#: app.c:1064 ++#: app.c:1065 +msgid "end of file after a one-character quote; \\0 inserted" +msgstr "" + -+#: app.c:1072 ++#: app.c:1073 +msgid "end of file in escape character" +msgstr "" + -+#: app.c:1084 ++#: app.c:1085 +msgid "missing close quote; (assumed)" +msgstr "" + -+#: app.c:1153 app.c:1208 app.c:1219 app.c:1293 ++#: app.c:1154 app.c:1209 app.c:1221 app.c:1301 +msgid "end of file in comment; newline inserted" +msgstr "" + -+#: as.c:162 ++#: as.c:161 +msgid "missing emulation mode name" +msgstr "" + -+#: as.c:177 ++#: as.c:176 +#, c-format +msgid "unrecognized emulation name `%s'" +msgstr "" + -+#: as.c:224 ++#: as.c:223 +#, c-format +msgid "GNU assembler version %s (%s) using BFD version %s\n" +msgstr "" + -+#: as.c:231 ++#: as.c:230 +#, c-format +msgid "Usage: %s [option...] [asmfile...]\n" +msgstr "" + -+#: as.c:233 ++#: as.c:232 +#, c-format +msgid "" +"Options:\n" @@ -825930,159 +830054,166 @@ index 0000000..f1eec3b +" \t =FILE list to FILE (must be last sub-option)\n" +msgstr "" + -+#: as.c:247 ++#: as.c:246 +#, c-format +msgid " --alternate initially turn on alternate macro syntax\n" +msgstr "" + -+#: as.c:250 ++#: as.c:249 +#, c-format +msgid "" +" --compress-debug-sections\n" +" compress DWARF debug sections using zlib\n" +msgstr "" + -+#: as.c:253 ++#: as.c:252 +#, c-format +msgid "" +" --nocompress-debug-sections\n" +" don't compress DWARF debug sections\n" +msgstr "" + -+#: as.c:257 ++#: as.c:256 +#, c-format +msgid " -D produce assembler debugging messages\n" +msgstr "" + -+#: as.c:259 ++#: as.c:258 +#, c-format +msgid "" +" --debug-prefix-map OLD=NEW\n" +" map OLD to NEW in debug information\n" +msgstr "" + -+#: as.c:262 ++#: as.c:261 +#, c-format +msgid " --defsym SYM=VAL define symbol SYM to given value\n" +msgstr "" + -+#: as.c:278 ++#: as.c:277 +#, c-format +msgid " emulate output (default %s)\n" +msgstr "" + -+#: as.c:283 ++#: as.c:282 +#, c-format +msgid " --execstack require executable stack for this object\n" +msgstr "" + -+#: as.c:285 ++#: as.c:284 +#, c-format +msgid "" +" --noexecstack don't require executable stack for this object\n" +msgstr "" + -+#: as.c:287 ++#: as.c:286 +#, c-format +msgid "" +" --size-check=[error|warning]\n" +"\t\t\t ELF .size directive check (default --size-check=error)\n" +msgstr "" + -+#: as.c:291 ++#: as.c:290 +#, c-format +msgid " -f skip whitespace and comment preprocessing\n" +msgstr "" + -+#: as.c:293 ++#: as.c:292 +#, c-format +msgid " -g --gen-debug generate debugging information\n" +msgstr "" + -+#: as.c:295 ++#: as.c:294 +#, c-format +msgid " --gstabs generate STABS debugging information\n" +msgstr "" + -+#: as.c:297 ++#: as.c:296 +#, c-format +msgid "" +" --gstabs+ generate STABS debug info with GNU extensions\n" +msgstr "" + -+#: as.c:299 ++#: as.c:298 +#, c-format +msgid " --gdwarf-2 generate DWARF2 debugging information\n" +msgstr "" + -+#: as.c:301 ++#: as.c:300 ++#, c-format ++msgid "" ++" --gdwarf-sections generate per-function section names for DWARF line " ++"information\n" ++msgstr "" ++ ++#: as.c:302 +#, c-format +msgid " --hash-size= set the hash table size close to \n" +msgstr "" + -+#: as.c:303 ++#: as.c:304 +#, c-format +msgid " --help show this message and exit\n" +msgstr "" + -+#: as.c:305 ++#: as.c:306 +#, c-format +msgid " --target-help show target specific options\n" +msgstr "" + -+#: as.c:307 ++#: as.c:308 +#, c-format +msgid "" +" -I DIR add DIR to search list for .include directives\n" +msgstr "" + -+#: as.c:309 ++#: as.c:310 +#, c-format +msgid " -J don't warn about signed overflow\n" +msgstr "" + -+#: as.c:311 ++#: as.c:312 +#, c-format +msgid "" +" -K warn when differences altered for long " +"displacements\n" +msgstr "" + -+#: as.c:313 ++#: as.c:314 +#, c-format +msgid " -L,--keep-locals keep local symbols (e.g. starting with `L')\n" +msgstr "" + -+#: as.c:315 ++#: as.c:316 +#, c-format +msgid " -M,--mri assemble in MRI compatibility mode\n" +msgstr "" + -+#: as.c:317 ++#: as.c:318 +#, c-format +msgid "" +" --MD FILE write dependency information in FILE (default " +"none)\n" +msgstr "" + -+#: as.c:319 ++#: as.c:320 +#, c-format +msgid " -nocpp ignored\n" +msgstr "" + -+#: as.c:321 ++#: as.c:322 +#, c-format +msgid "" +" -o OBJFILE name the object-file output OBJFILE (default a." +"out)\n" +msgstr "" + -+#: as.c:323 ++#: as.c:324 +#, c-format +msgid " -R fold data section into text section\n" +msgstr "" + -+#: as.c:325 ++#: as.c:326 +#, c-format +msgid "" +" --reduce-memory-overheads \n" @@ -826090,44 +830221,44 @@ index 0000000..f1eec3b +" assembly times\n" +msgstr "" + -+#: as.c:329 ++#: as.c:330 +#, c-format +msgid "" +" --statistics print various measured statistics from execution\n" +msgstr "" + -+#: as.c:331 ++#: as.c:332 +#, c-format +msgid " --strip-local-absolute strip local absolute symbols\n" +msgstr "" + -+#: as.c:333 ++#: as.c:334 +#, c-format +msgid "" +" --traditional-format Use same format as native assembler when possible\n" +msgstr "" + -+#: as.c:335 ++#: as.c:336 +#, c-format +msgid " --version print assembler version number and exit\n" +msgstr "" + -+#: as.c:337 ++#: as.c:338 +#, c-format +msgid " -W --no-warn suppress warnings\n" +msgstr "" + -+#: as.c:339 ++#: as.c:340 +#, c-format +msgid " --warn don't suppress warnings\n" +msgstr "" + -+#: as.c:341 ++#: as.c:342 +#, c-format +msgid " --fatal-warnings treat warnings as errors\n" +msgstr "" + -+#: as.c:344 ++#: as.c:345 +#, c-format +msgid "" +" --itbl INSTTBL extend instruction set to include instructions\n" @@ -826135,22 +830266,22 @@ index 0000000..f1eec3b +"INSTTBL\n" +msgstr "" + -+#: as.c:348 ++#: as.c:349 +#, c-format +msgid " -w ignored\n" +msgstr "" + -+#: as.c:350 ++#: as.c:351 +#, c-format +msgid " -X ignored\n" +msgstr "" + -+#: as.c:352 ++#: as.c:353 +#, c-format +msgid " -Z generate object file even after errors\n" +msgstr "" + -+#: as.c:354 ++#: as.c:355 +#, c-format +msgid "" +" --listing-lhs-width set the width in words of the output data column " @@ -826158,7 +830289,7 @@ index 0000000..f1eec3b +" the listing\n" +msgstr "" + -+#: as.c:357 ++#: as.c:358 +#, c-format +msgid "" +" --listing-lhs-width2 set the width in words of the continuation lines\n" @@ -826167,47 +830298,47 @@ index 0000000..f1eec3b +" the width of the first line\n" +msgstr "" + -+#: as.c:361 ++#: as.c:362 +#, c-format +msgid "" +" --listing-rhs-width set the max width in characters of the lines from\n" +" the source file\n" +msgstr "" + -+#: as.c:364 ++#: as.c:365 +#, c-format +msgid "" +" --listing-cont-lines set the maximum number of continuation lines used\n" +" for the output data column of the listing\n" +msgstr "" + -+#: as.c:367 ++#: as.c:368 +#, c-format +msgid " @FILE read options from FILE\n" +msgstr "" + -+#: as.c:375 ++#: as.c:376 +#, c-format +msgid "Report bugs to %s\n" +msgstr "" + -+#: as.c:587 ++#: as.c:590 +#, c-format +msgid "unrecognized option -%c%s" +msgstr "" + +#. This output is intended to follow the GNU standards document. -+#: as.c:625 ++#: as.c:628 +#, c-format +msgid "GNU assembler %s\n" +msgstr "" + -+#: as.c:626 ++#: as.c:629 +#, c-format -+msgid "Copyright 2011 Free Software Foundation, Inc.\n" ++msgid "Copyright 2014 Free Software Foundation, Inc.\n" +msgstr "" + -+#: as.c:627 ++#: as.c:630 +#, c-format +msgid "" +"This program is free software; you may redistribute it under the terms of\n" @@ -826215,91 +830346,91 @@ index 0000000..f1eec3b +"This program has absolutely no warranty.\n" +msgstr "" + -+#: as.c:631 ++#: as.c:634 +#, c-format +msgid "This assembler was configured for a target of `%s'.\n" +msgstr "" + -+#: as.c:638 ++#: as.c:641 +msgid "multiple emulation names specified" +msgstr "" + -+#: as.c:640 ++#: as.c:643 +msgid "emulations not handled in this configuration" +msgstr "" + -+#: as.c:645 ++#: as.c:648 +#, c-format +msgid "alias = %s\n" +msgstr "" + -+#: as.c:646 ++#: as.c:649 +#, c-format +msgid "canonical = %s\n" +msgstr "" + -+#: as.c:647 ++#: as.c:650 +#, c-format +msgid "cpu-type = %s\n" +msgstr "" + -+#: as.c:649 ++#: as.c:652 +#, c-format +msgid "format = %s\n" +msgstr "" + -+#: as.c:652 ++#: as.c:655 +#, c-format +msgid "bfd-target = %s\n" +msgstr "" + -+#: as.c:660 ++#: as.c:663 +msgid "cannot compress debug sections (zlib not installed)" +msgstr "" + -+#: as.c:681 ++#: as.c:684 +msgid "bad defsym; format is --defsym name=value" +msgstr "" + -+#: as.c:701 ++#: as.c:704 +msgid "no file name following -t option" +msgstr "" + -+#: as.c:716 ++#: as.c:719 +#, c-format +msgid "failed to read instruction table %s\n" +msgstr "" + -+#: as.c:828 ++#: as.c:835 +#, c-format +msgid "Invalid --size-check= option: `%s'" +msgstr "" + -+#: as.c:896 ++#: as.c:903 +#, c-format +msgid "invalid listing option `%c'" +msgstr "" + -+#: as.c:949 ++#: as.c:956 +msgid "--hash-size needs a numeric argument" +msgstr "" + -+#: as.c:974 ++#: as.c:981 +#, c-format +msgid "%s: total time in assembly: %ld.%06ld\n" +msgstr "" + -+#: as.c:977 ++#: as.c:984 +#, c-format +msgid "%s: data size %ld\n" +msgstr "" + -+#: as.c:1292 ++#: as.c:1308 +#, c-format +msgid "%d warnings, treating warnings as errors" +msgstr "" + -+#: as.h:184 ++#: as.h:189 +#, c-format +msgid "Case value %ld unexpected at line %d of file \"%s\"\n" +msgstr "" @@ -826308,71 +830439,72 @@ index 0000000..f1eec3b +#. * We have a GROSS internal error. +#. * This should never happen. +#. -+#: atof-generic.c:417 config/tc-m68k.c:3579 ++#: atof-generic.c:417 config/tc-m68k.c:3583 +msgid "failed sanity check" +msgstr "" + +#: cgen.c:113 config/tc-alpha.c:2101 config/tc-alpha.c:2125 +#: config/tc-arc.c:1684 config/tc-d10v.c:552 config/tc-d30v.c:538 -+#: config/tc-mn10200.c:1101 config/tc-mn10300.c:1751 config/tc-ppc.c:2617 -+#: config/tc-ppc.c:2768 config/tc-ppc.c:2910 config/tc-ppc.c:2921 -+#: config/tc-s390.c:1250 config/tc-s390.c:1364 config/tc-s390.c:1493 -+#: config/tc-v850.c:2229 config/tc-v850.c:2300 config/tc-v850.c:2346 -+#: config/tc-v850.c:2383 config/tc-v850.c:2420 config/tc-v850.c:2649 ++#: config/tc-mn10200.c:1101 config/tc-mn10300.c:1753 config/tc-ppc.c:2861 ++#: config/tc-ppc.c:3038 config/tc-ppc.c:3307 config/tc-s390.c:1262 ++#: config/tc-s390.c:1382 config/tc-s390.c:1511 config/tc-v850.c:2523 ++#: config/tc-v850.c:2594 config/tc-v850.c:2641 config/tc-v850.c:2678 ++#: config/tc-v850.c:2715 config/tc-v850.c:2976 +msgid "too many fixups" +msgstr "" + +#: cgen.c:400 cgen.c:420 config/tc-arc.c:1665 config/tc-d10v.c:463 +#: config/tc-d30v.c:454 config/tc-i370.c:2125 config/tc-mn10200.c:1043 -+#: config/tc-mn10300.c:1676 config/tc-ppc.c:2656 config/tc-s390.c:1221 -+#: config/tc-v850.c:2337 config/tc-v850.c:2371 config/tc-v850.c:2411 -+#: config/tc-v850.c:2622 config/tc-z80.c:417 ++#: config/tc-mn10300.c:1678 config/tc-ppc.c:2903 config/tc-s390.c:1233 ++#: config/tc-v850.c:2632 config/tc-v850.c:2666 config/tc-v850.c:2706 ++#: config/tc-v850.c:2949 config/tc-z80.c:444 +msgid "illegal operand" +msgstr "" + -+#: cgen.c:424 config/tc-arc.c:1667 config/tc-avr.c:632 config/tc-d10v.c:465 -+#: config/tc-d30v.c:456 config/tc-h8300.c:500 config/tc-i370.c:2127 -+#: config/tc-mcore.c:662 config/tc-microblaze.c:579 config/tc-mmix.c:488 -+#: config/tc-mn10200.c:1046 config/tc-mn10300.c:1679 config/tc-msp430.c:452 -+#: config/tc-or32.c:307 config/tc-ppc.c:2658 config/tc-s390.c:1239 -+#: config/tc-sh.c:1387 config/tc-sh64.c:2213 config/tc-v850.c:2341 -+#: config/tc-v850.c:2375 config/tc-v850.c:2415 config/tc-v850.c:2625 -+#: config/tc-z80.c:570 config/tc-z8k.c:350 ++#: cgen.c:424 config/tc-arc.c:1667 config/tc-avr.c:639 config/tc-d10v.c:465 ++#: config/tc-d30v.c:456 config/tc-h8300.c:497 config/tc-i370.c:2127 ++#: config/tc-mcore.c:662 config/tc-microblaze.c:604 config/tc-mmix.c:495 ++#: config/tc-mn10200.c:1046 config/tc-mn10300.c:1681 config/tc-msp430.c:883 ++#: config/tc-or32.c:307 config/tc-ppc.c:2905 config/tc-s390.c:1251 ++#: config/tc-sh.c:1386 config/tc-sh64.c:2213 config/tc-v850.c:2636 ++#: config/tc-v850.c:2670 config/tc-v850.c:2710 config/tc-v850.c:2952 ++#: config/tc-xgate.c:897 config/tc-z80.c:555 config/tc-z8k.c:350 +msgid "missing operand" +msgstr "" + -+#: cgen.c:799 ++#: cgen.c:800 +msgid "a reloc on this operand implies an overflow" +msgstr "" + -+#: cgen.c:822 ++#: cgen.c:823 +msgid "operand mask overflow" +msgstr "" + +#. We can't actually support subtracting a symbol. -+#: cgen.c:886 config/tc-arc.c:1249 config/tc-arm.c:1649 config/tc-arm.c:9195 -+#: config/tc-arm.c:9247 config/tc-arm.c:9494 config/tc-arm.c:10301 -+#: config/tc-arm.c:11396 config/tc-arm.c:11436 config/tc-arm.c:11776 -+#: config/tc-arm.c:11815 config/tc-avr.c:1165 config/tc-cris.c:4047 -+#: config/tc-d10v.c:1511 config/tc-d30v.c:1915 config/tc-mips.c:5697 -+#: config/tc-msp430.c:1936 config/tc-ppc.c:6072 config/tc-spu.c:957 -+#: config/tc-spu.c:981 config/tc-tilegx.c:1421 config/tc-tilepro.c:1268 -+#: config/tc-v850.c:3084 config/tc-xstormy16.c:483 config/tc-xtensa.c:5833 -+#: config/tc-xtensa.c:11830 ++#: cgen.c:887 config/tc-arc.c:1249 config/tc-arm.c:1683 config/tc-arm.c:9384 ++#: config/tc-arm.c:9436 config/tc-arm.c:9685 config/tc-arm.c:10506 ++#: config/tc-arm.c:11632 config/tc-arm.c:11672 config/tc-arm.c:12015 ++#: config/tc-arm.c:12056 config/tc-avr.c:1172 config/tc-avr.c:1397 ++#: config/tc-cris.c:4047 config/tc-d10v.c:1511 config/tc-d30v.c:1915 ++#: config/tc-mips.c:8510 config/tc-mips.c:9797 config/tc-mips.c:11029 ++#: config/tc-mips.c:11684 config/tc-nds32.c:5775 config/tc-ppc.c:6515 ++#: config/tc-spu.c:957 config/tc-spu.c:981 config/tc-tilegx.c:1485 ++#: config/tc-tilepro.c:1346 config/tc-v850.c:3435 config/tc-xstormy16.c:483 ++#: config/tc-xtensa.c:5833 config/tc-xtensa.c:11830 +msgid "expression too complex" +msgstr "" + -+#: cgen.c:982 config/tc-arc.c:1310 config/tc-ppc.c:6197 config/tc-s390.c:2135 -+#: config/tc-v850.c:3131 config/tc-xstormy16.c:537 ++#: cgen.c:983 config/tc-arc.c:1310 config/tc-ppc.c:6832 config/tc-ppc.c:7048 ++#: config/tc-s390.c:2246 config/tc-v850.c:3487 config/tc-xstormy16.c:537 +msgid "unresolved expression that must be resolved" +msgstr "" + -+#: cgen.c:1007 config/tc-xstormy16.c:562 ++#: cgen.c:1008 config/tc-xstormy16.c:562 +#, c-format +msgid "internal error: can't install fix for reloc type %d (`%s')" +msgstr "" + -+#: cgen.c:1060 ++#: cgen.c:1061 config/tc-nios2.c:1231 +msgid "relocation is not supported" +msgstr "" + @@ -826452,8 +830584,8 @@ index 0000000..f1eec3b +msgid "Infinities are not supported by this target\n" +msgstr "" + -+#: config/atof-ieee.c:784 config/atof-vax.c:450 config/tc-arm.c:1040 -+#: config/tc-ia64.c:11435 config/tc-tic30.c:1259 config/tc-tic4x.c:2598 ++#: config/atof-ieee.c:784 config/atof-vax.c:450 config/tc-arm.c:1070 ++#: config/tc-ia64.c:11651 config/tc-tic30.c:1259 config/tc-tic4x.c:2592 +msgid "Unrecognized or unsupported floating point constant" +msgstr "" + @@ -826467,104 +830599,104 @@ index 0000000..f1eec3b +msgid "Attempt to put an undefined symbol into set %s" +msgstr "" + -+#: config/obj-aout.c:115 config/obj-coff.c:1398 ++#: config/obj-aout.c:115 config/obj-coff.c:1401 +#, c-format +msgid "Symbol `%s' can not be both weak and common" +msgstr "" + -+#: config/obj-coff.c:140 dw2gencfi.c:214 ++#: config/obj-coff.c:141 dw2gencfi.c:214 +#, c-format +msgid "Inserting \"%s\" into structure table failed: %s" +msgstr "" + -+#: config/obj-coff.c:219 config/obj-coff.c:1701 config/obj-macho.c:202 -+#: config/tc-ppc.c:5147 config/tc-tic54x.c:4008 read.c:2795 ++#: config/obj-coff.c:220 config/obj-coff.c:1705 config/tc-ppc.c:5519 ++#: config/tc-tic54x.c:4008 read.c:2896 +#, c-format +msgid "error setting flags for \"%s\": %s" +msgstr "" + +#. Zero is used as an end marker in the file. -+#: config/obj-coff.c:438 ++#: config/obj-coff.c:439 +msgid "Line numbers must be positive integers\n" +msgstr "" + -+#: config/obj-coff.c:470 ++#: config/obj-coff.c:471 +msgid ".ln pseudo-op inside .def/.endef: ignored." +msgstr "" + -+#: config/obj-coff.c:512 ecoff.c:3250 ++#: config/obj-coff.c:513 ecoff.c:3249 +msgid ".loc outside of .text" +msgstr "" + -+#: config/obj-coff.c:519 ++#: config/obj-coff.c:520 +msgid ".loc pseudo-op inside .def/.endef: ignored." +msgstr "" + -+#: config/obj-coff.c:600 ++#: config/obj-coff.c:601 +msgid ".def pseudo-op used inside of .def/.endef: ignored." +msgstr "" + -+#: config/obj-coff.c:636 ++#: config/obj-coff.c:637 +msgid ".endef pseudo-op used outside of .def/.endef: ignored." +msgstr "" + -+#: config/obj-coff.c:675 ++#: config/obj-coff.c:676 +#, c-format +msgid "`%s' symbol without preceding function" +msgstr "" + -+#: config/obj-coff.c:762 ++#: config/obj-coff.c:763 +#, c-format +msgid "unexpected storage class %d" +msgstr "" + -+#: config/obj-coff.c:870 ++#: config/obj-coff.c:871 +msgid ".dim pseudo-op used outside of .def/.endef: ignored." +msgstr "" + -+#: config/obj-coff.c:890 ++#: config/obj-coff.c:891 +msgid "badly formed .dim directive ignored" +msgstr "" + -+#: config/obj-coff.c:939 ++#: config/obj-coff.c:940 +msgid ".size pseudo-op used outside of .def/.endef ignored." +msgstr "" + -+#: config/obj-coff.c:954 ++#: config/obj-coff.c:955 +msgid ".scl pseudo-op used outside of .def/.endef ignored." +msgstr "" + -+#: config/obj-coff.c:971 ++#: config/obj-coff.c:972 +msgid ".tag pseudo-op used outside of .def/.endef ignored." +msgstr "" + -+#: config/obj-coff.c:989 ++#: config/obj-coff.c:990 +#, c-format +msgid "tag not found for .tag %s" +msgstr "" + -+#: config/obj-coff.c:1002 ++#: config/obj-coff.c:1003 +msgid ".type pseudo-op used outside of .def/.endef ignored." +msgstr "" + -+#: config/obj-coff.c:1021 ++#: config/obj-coff.c:1022 +msgid ".val pseudo-op used outside of .def/.endef ignored." +msgstr "" + -+#: config/obj-coff.c:1178 ++#: config/obj-coff.c:1179 +msgid "badly formed .weak directive ignored" +msgstr "" + -+#: config/obj-coff.c:1356 ++#: config/obj-coff.c:1357 +msgid "mismatched .eb" +msgstr "" + -+#: config/obj-coff.c:1377 ++#: config/obj-coff.c:1380 +#, c-format +msgid "C_EFCN symbol for %s out of scope" +msgstr "" + -+#: config/obj-coff.c:1431 ++#: config/obj-coff.c:1434 +#, c-format +msgid "Warning: internal error: forgetting to set endndx of %s" +msgstr "" @@ -826572,22 +830704,22 @@ index 0000000..f1eec3b +#. STYP_INFO +#. STYP_LIB +#. STYP_OVER -+#: config/obj-coff.c:1667 ++#: config/obj-coff.c:1670 +#, c-format +msgid "unsupported section attribute '%c'" +msgstr "" + -+#: config/obj-coff.c:1671 config/tc-ppc.c:5129 ++#: config/obj-coff.c:1674 config/tc-ppc.c:5501 +#, c-format +msgid "unknown section attribute '%c'" +msgstr "" + -+#: config/obj-coff.c:1713 config/obj-macho.c:216 ++#: config/obj-coff.c:1717 config/obj-macho.c:276 +#, c-format +msgid "Ignoring changed section attributes for %s" +msgstr "" + -+#: config/obj-coff.c:1853 ++#: config/obj-coff.c:1857 +#, c-format +msgid "0x%lx: \"%s\" type = %ld, class = %d, segment = %d\n" +msgstr "" @@ -826600,228 +830732,390 @@ index 0000000..f1eec3b +msgid "Can't set register masks" +msgstr "" + -+#: config/obj-elf.c:334 config/tc-sparc.c:4092 config/tc-v850.c:503 ++#: config/obj-elf.c:342 config/tc-sparc.c:4193 config/tc-v850.c:512 +#, c-format +msgid "bad .common segment %s" +msgstr "" + -+#: config/obj-elf.c:411 ++#: config/obj-elf.c:419 +msgid "Missing symbol name in directive" +msgstr "" + -+#: config/obj-elf.c:618 ++#: config/obj-elf.c:625 +#, c-format +msgid "setting incorrect section type for %s" +msgstr "" + -+#: config/obj-elf.c:623 ++#: config/obj-elf.c:630 +#, c-format +msgid "ignoring incorrect section type for %s" +msgstr "" + -+#: config/obj-elf.c:665 ++#: config/obj-elf.c:680 +#, c-format +msgid "setting incorrect section attributes for %s" +msgstr "" + -+#: config/obj-elf.c:720 ++#: config/obj-elf.c:735 +#, c-format +msgid "ignoring changed section type for %s" +msgstr "" + -+#: config/obj-elf.c:732 ++#: config/obj-elf.c:747 +#, c-format +msgid "ignoring changed section attributes for %s" +msgstr "" + -+#: config/obj-elf.c:734 ++#: config/obj-elf.c:749 +#, c-format +msgid "ignoring changed section entity size for %s" +msgstr "" + -+#: config/obj-elf.c:794 ++#: config/obj-elf.c:809 +msgid "unrecognized .section attribute: want a,e,w,x,M,S,G,T" +msgstr "" + -+#: config/obj-elf.c:836 read.c:2779 ++#: config/obj-elf.c:851 read.c:2880 +msgid "unrecognized section type" +msgstr "" + -+#: config/obj-elf.c:868 ++#: config/obj-elf.c:883 +msgid "unrecognized section attribute" +msgstr "" + -+#: config/obj-elf.c:899 config/tc-alpha.c:4208 ++#: config/obj-elf.c:914 config/tc-alpha.c:4208 +msgid "missing name" +msgstr "" + -+#: config/obj-elf.c:1030 ++#: config/obj-elf.c:1045 +msgid "invalid merge entity size" +msgstr "" + -+#: config/obj-elf.c:1037 ++#: config/obj-elf.c:1052 +msgid "entity size for SHF_MERGE not specified" +msgstr "" + -+#: config/obj-elf.c:1043 ++#: config/obj-elf.c:1058 +msgid "? section flag ignored with G present" +msgstr "" + -+#: config/obj-elf.c:1062 ++#: config/obj-elf.c:1082 +msgid "group name for SHF_GROUP not specified" +msgstr "" + -+#: config/obj-elf.c:1085 ++#: config/obj-elf.c:1105 +msgid "character following name is not '#'" +msgstr "" + -+#: config/obj-elf.c:1204 ++#: config/obj-elf.c:1224 +msgid ".previous without corresponding .section; ignored" +msgstr "" + -+#: config/obj-elf.c:1230 ++#: config/obj-elf.c:1250 +msgid ".popsection without corresponding .pushsection; ignored" +msgstr "" + -+#: config/obj-elf.c:1276 ++#: config/obj-elf.c:1296 +msgid "expected comma after name in .symver" +msgstr "" + -+#: config/obj-elf.c:1300 ++#: config/obj-elf.c:1320 +#, c-format +msgid "missing version name in `%s' for symbol `%s'" +msgstr "" + -+#: config/obj-elf.c:1311 ++#: config/obj-elf.c:1331 +#, c-format +msgid "multiple versions [`%s'|`%s'] for symbol `%s'" +msgstr "" + -+#: config/obj-elf.c:1348 ++#: config/obj-elf.c:1368 +#, c-format +msgid "expected `%s' to have already been set for .vtable_inherit" +msgstr "" + -+#: config/obj-elf.c:1358 ++#: config/obj-elf.c:1378 +msgid "expected comma after name in .vtable_inherit" +msgstr "" + -+#: config/obj-elf.c:1411 ++#: config/obj-elf.c:1431 +msgid "expected comma after name in .vtable_entry" +msgstr "" + -+#: config/obj-elf.c:1534 ++#: config/obj-elf.c:1507 ++#, c-format ++msgid "Attribute name not recognised: %s" ++msgstr "" ++ ++#: config/obj-elf.c:1522 ++msgid "expected numeric constant" ++msgstr "" ++ ++#: config/obj-elf.c:1531 config/tc-arm.c:6097 ++msgid "expected comma" ++msgstr "" ++ ++#: config/obj-elf.c:1563 ++msgid "bad string constant" ++msgstr "" ++ ++#: config/obj-elf.c:1567 ++msgid "expected , " ++msgstr "" ++ ++#: config/obj-elf.c:1686 +msgid "expected quoted string" +msgstr "" + -+#: config/obj-elf.c:1554 ++#: config/obj-elf.c:1706 +#, c-format +msgid "expected comma after name `%s' in .size directive" +msgstr "" + -+#: config/obj-elf.c:1563 ++#: config/obj-elf.c:1715 +msgid "missing expression in .size directive" +msgstr "" + -+#: config/obj-elf.c:1687 ++#: config/obj-elf.c:1839 +#, c-format +msgid "symbol '%s' is already defined" +msgstr "" + -+#: config/obj-elf.c:1707 config/obj-elf.c:1719 ++#: config/obj-elf.c:1860 ++#, c-format ++msgid "symbol type \"%s\" is supported only by GNU and FreeBSD targets" ++msgstr "" ++ ++#: config/obj-elf.c:1872 +#, c-format +msgid "symbol type \"%s\" is supported only by GNU targets" +msgstr "" + -+#: config/obj-elf.c:1730 ++#: config/obj-elf.c:1883 +#, c-format +msgid "unrecognized symbol type \"%s\"" +msgstr "" + -+#: config/obj-elf.c:1900 config/obj-elf.c:1903 ++#: config/obj-elf.c:2053 config/obj-elf.c:2056 +#, c-format +msgid ".size expression for %s does not evaluate to a constant" +msgstr "" + -+#: config/obj-elf.c:1935 ++#: config/obj-elf.c:2088 +#, c-format +msgid "" +"invalid attempt to declare external version name as default in symbol `%s'" +msgstr "" + -+#: config/obj-elf.c:1996 ecoff.c:3608 ++#: config/obj-elf.c:2149 ecoff.c:3607 +#, c-format +msgid "symbol `%s' can not be both weak and common" +msgstr "" + -+#: config/obj-elf.c:2113 ++#: config/obj-elf.c:2266 +#, c-format +msgid "assuming all members of group `%s' are COMDAT" +msgstr "" + -+#: config/obj-elf.c:2125 ++#: config/obj-elf.c:2278 +#, c-format +msgid "can't create group: %s" +msgstr "" + -+#: config/obj-elf.c:2264 ++#: config/obj-elf.c:2417 +#, c-format +msgid "failed to set up debugging information: %s" +msgstr "" + -+#: config/obj-elf.c:2284 ++#: config/obj-elf.c:2437 +#, c-format +msgid "can't start writing .mdebug section: %s" +msgstr "" + -+#: config/obj-elf.c:2292 ++#: config/obj-elf.c:2445 +#, c-format +msgid "could not write .mdebug section: %s" +msgstr "" + -+#: config/obj-evax.c:129 ++#: config/obj-evax.c:130 +#, c-format +msgid "no entry symbol for global function '%s'" +msgstr "" + -+#: config/obj-macho.c:77 -+msgid "missing segment name" ++#. make a temp string. ++#: config/obj-macho.c:119 ++#, c-format ++msgid "the %s name '%s' is too long (maximum 16 characters)" +msgstr "" + -+#: config/obj-macho.c:89 -+msgid "missing comma after segment name" ++#: config/obj-macho.c:130 ++#, c-format ++msgid "expected a %s name followed by a `,'" +msgstr "" + -+#: config/obj-macho.c:98 -+msgid "missing section name" ++#: config/obj-macho.c:195 ++#, c-format ++msgid "cannot overide zerofill section type for `%s,%s'" +msgstr "" + -+#: config/obj-macho.c:114 -+msgid "missing section type name" ++#: config/obj-macho.c:258 ++#, c-format ++msgid "failed to set flags for \"%s\": %s" +msgstr "" + -+#: config/obj-macho.c:124 ++#: config/obj-macho.c:349 +#, c-format +msgid "unknown or invalid section type '%s'" +msgstr "" + -+#: config/obj-macho.c:140 -+msgid "missing section attribute identifier" -+msgstr "" -+ -+#: config/obj-macho.c:149 ++#: config/obj-macho.c:388 +#, c-format +msgid "unknown or invalid section attribute '%s'" +msgstr "" + -+#: config/obj-macho.c:161 -+msgid "unexpected sizeof_stub expression" ++#: config/obj-macho.c:409 ++msgid "unexpected section size information" +msgstr "" + -+#: config/obj-macho.c:166 ++#: config/obj-macho.c:421 +msgid "missing sizeof_stub expression" +msgstr "" + ++#: config/obj-macho.c:486 config/tc-ia64.c:1093 config/tc-ia64.c:11814 ++#: config/tc-score.c:6105 read.c:1669 ++msgid "expected symbol name" ++msgstr "" ++ ++#: config/obj-macho.c:499 read.c:490 ++msgid "bad or irreducible absolute expression" ++msgstr "" ++ ++#: config/obj-macho.c:505 config/tc-score.c:6122 read.c:1707 ++msgid "missing size expression" ++msgstr "" ++ ++#: config/obj-macho.c:514 config/tc-ia64.c:1128 read.c:1713 ++#, c-format ++msgid "size (%ld) out of range, ignored" ++msgstr "" ++ ++#: config/obj-macho.c:524 config/tc-score.c:6266 ecoff.c:3364 read.c:1725 ++#: read.c:1831 read.c:2568 read.c:3198 read.c:3560 symbols.c:341 symbols.c:437 ++#, c-format ++msgid "symbol `%s' is already defined" ++msgstr "" ++ ++#: config/obj-macho.c:534 read.c:1740 ++#, c-format ++msgid "size of \"%s\" is already %ld; not changing to %ld" ++msgstr "" ++ ++#: config/obj-macho.c:545 ++msgid "align value not recognized, using size" ++msgstr "" ++ ++#: config/obj-macho.c:550 config/obj-macho.c:913 ++#, c-format ++msgid "Alignment (%lu) too large: 15 assumed." ++msgstr "" ++ ++#: config/obj-macho.c:616 ++#, c-format ++msgid "BFD is out of sync with GAS, unhandled well-known section type `%s'" ++msgstr "" ++ ++#: config/obj-macho.c:818 ++#, c-format ++msgid "%s is not used for the selected target" ++msgstr "" ++ ++#: config/obj-macho.c:883 ++msgid "internal error: base section index out of range" ++msgstr "" ++ ++#: config/obj-macho.c:969 ++#, c-format ++msgid "internal error: bad file property ID %d" ++msgstr "" ++ ++#: config/obj-macho.c:977 ++msgid "failed to set subsections by symbols" ++msgstr "" ++ ++#: config/obj-macho.c:1041 ++#, c-format ++msgid "'%s' previously declared as '%s'." ++msgstr "" ++ ++#: config/obj-macho.c:1092 config/obj-macho.c:1412 config/obj-macho.c:1494 ++#, c-format ++msgid "" ++"'%s' can't be a weak_definition (currently only supported in sections of " ++"type coalesced)" ++msgstr "" ++ ++#: config/obj-macho.c:1177 ++msgid "use of .indirect_symbols requires `-dynamic'" ++msgstr "" ++ ++#: config/obj-macho.c:1194 ++#, c-format ++msgid "" ++"attempt to add an indirect_symbol to a stub or reference section with a zero-" ++"sized element at %s" ++msgstr "" ++ ++#: config/obj-macho.c:1225 ++msgid "an .indirect_symbol must be in a symbol pointer or stub section." ++msgstr "" ++ ++#: config/obj-macho.c:1491 ++#, c-format ++msgid "'%s' can't be a weak_definition (since it is undefined)" ++msgstr "" ++ ++#: config/obj-macho.c:1497 ++#, c-format ++msgid "Non-global symbol: '%s' can't be a weak_definition." ++msgstr "" ++ ++#: config/obj-macho.c:1503 ++#, c-format ++msgid "internal error: [%s] unexpected code [%lx] in frob symbol" ++msgstr "" ++ ++#: config/obj-macho.c:1544 ++#, c-format ++msgid "unrecognized stab type '%c'" ++msgstr "" ++ ++#: config/obj-macho.c:1595 ++#, c-format ++msgid "`%s' can't be undefined in `%s' - `%s' {%s section}" ++msgstr "" ++ ++#: config/obj-macho.c:1603 ++#, c-format ++msgid "`%s' can't be undefined in `%s' {%s section} - `%s'" ++msgstr "" ++ ++#: config/obj-macho.c:1610 ++#, c-format ++msgid "`%s' and `%s' can't be undefined in `%s' - `%s'" ++msgstr "" ++ ++#: config/obj-macho.c:1812 ++#, c-format ++msgid "" ++"the number of .indirect_symbols defined in section %s does not match the " ++"number expected (%d defined, %d expected)" ++msgstr "" ++ ++#: config/obj-macho.c:1825 ++#, c-format ++msgid "internal error: failed to allocate %d indirectsymbol pointers" ++msgstr "" ++ +#: config/obj-som.c:58 +msgid "Only one .compiler pseudo-op per file!" +msgstr "" @@ -826861,6 +831155,733 @@ index 0000000..f1eec3b +msgid "attaching copyright header %s: %s" +msgstr "" + ++#: config/tc-aarch64.c:353 ++msgid "integer 32-bit register expected" ++msgstr "" ++ ++#: config/tc-aarch64.c:356 ++msgid "integer 64-bit register expected" ++msgstr "" ++ ++#: config/tc-aarch64.c:359 ++msgid "integer register expected" ++msgstr "" ++ ++#: config/tc-aarch64.c:362 ++msgid "integer, zero or SP register expected" ++msgstr "" ++ ++#: config/tc-aarch64.c:365 ++msgid "8-bit SIMD scalar register expected" ++msgstr "" ++ ++#: config/tc-aarch64.c:368 ++msgid "16-bit SIMD scalar or floating-point half precision register expected" ++msgstr "" ++ ++#: config/tc-aarch64.c:372 ++msgid "32-bit SIMD scalar or floating-point single precision register expected" ++msgstr "" ++ ++#: config/tc-aarch64.c:376 ++msgid "64-bit SIMD scalar or floating-point double precision register expected" ++msgstr "" ++ ++#: config/tc-aarch64.c:380 ++msgid "128-bit SIMD scalar or floating-point quad precision register expected" ++msgstr "" ++ ++#: config/tc-aarch64.c:384 ++msgid "C0 - C15 expected" ++msgstr "" ++ ++#: config/tc-aarch64.c:387 config/tc-arm.c:4119 ++msgid "register expected" ++msgstr "" ++ ++#. any [BHSDQ]P FP ++#: config/tc-aarch64.c:390 ++msgid "SIMD scalar or floating-point register expected" ++msgstr "" ++ ++#. any V reg ++#: config/tc-aarch64.c:393 ++msgid "vector register expected" ++msgstr "" ++ ++#: config/tc-aarch64.c:396 ++#, c-format ++msgid "invalid register type %d" ++msgstr "" ++ ++#. Define some common error messages. ++#: config/tc-aarch64.c:408 ++msgid "SP not allowed here" ++msgstr "" ++ ++#: config/tc-aarch64.c:551 config/tc-aarch64.c:553 config/tc-arm.c:979 ++#: config/tc-score.c:6515 expr.c:1363 read.c:2550 ++msgid "bad expression" ++msgstr "" ++ ++#: config/tc-aarch64.c:563 config/tc-arm.c:990 config/tc-i860.c:1004 ++#: config/tc-sparc.c:3096 ++msgid "bad segment" ++msgstr "" ++ ++#: config/tc-aarch64.c:774 ++#, c-format ++msgid "bad size %d in vector width specifier" ++msgstr "" ++ ++#: config/tc-aarch64.c:807 ++#, c-format ++msgid "unexpected character `%c' in element size" ++msgstr "" ++ ++#: config/tc-aarch64.c:809 ++msgid "missing element size" ++msgstr "" ++ ++#: config/tc-aarch64.c:815 ++#, c-format ++msgid "invalid element size %d and vector size combination %c" ++msgstr "" ++ ++#: config/tc-aarch64.c:842 config/tc-arm.c:1375 ++msgid "vector type expected" ++msgstr "" ++ ++#: config/tc-aarch64.c:923 ++msgid "this type of register can't be indexed" ++msgstr "" ++ ++#: config/tc-aarch64.c:929 ++msgid "index not allowed inside register list" ++msgstr "" ++ ++#: config/tc-aarch64.c:939 config/tc-aarch64.c:1839 config/tc-aarch64.c:1993 ++#: config/tc-arm.c:1480 config/tc-arm.c:3400 config/tc-arm.c:4499 ++msgid "constant expression required" ++msgstr "" ++ ++#. Indexed vector register expected. ++#: config/tc-aarch64.c:951 ++msgid "indexed vector register expected" ++msgstr "" ++ ++#: config/tc-aarch64.c:958 ++msgid "invalid use of vector register" ++msgstr "" ++ ++#: config/tc-aarch64.c:1048 config/tc-arm.c:1744 ++msgid "expecting {" ++msgstr "" ++ ++#: config/tc-aarch64.c:1073 ++msgid "invalid vector register in list" ++msgstr "" ++ ++#: config/tc-aarch64.c:1080 ++msgid "invalid scalar register in list" ++msgstr "" ++ ++#: config/tc-aarch64.c:1093 ++msgid "invalid range in vector register list" ++msgstr "" ++ ++#: config/tc-aarch64.c:1106 ++msgid "type mismatch in vector register list" ++msgstr "" ++ ++#: config/tc-aarch64.c:1123 ++msgid "end of vector register list not found" ++msgstr "" ++ ++#: config/tc-aarch64.c:1139 ++msgid "constant expression required." ++msgstr "" ++ ++#: config/tc-aarch64.c:1149 ++msgid "expected index" ++msgstr "" ++ ++#: config/tc-aarch64.c:1156 ++msgid "too many registers in vector register list" ++msgstr "" ++ ++#: config/tc-aarch64.c:1161 ++msgid "empty vector register list" ++msgstr "" ++ ++#: config/tc-aarch64.c:1183 config/tc-arm.c:2126 ++#, c-format ++msgid "ignoring attempt to redefine built-in register '%s'" ++msgstr "" ++ ++#: config/tc-aarch64.c:1189 config/tc-arm.c:2131 ++#, c-format ++msgid "ignoring redefinition of register alias '%s'" ++msgstr "" ++ ++#: config/tc-aarch64.c:1235 config/tc-arm.c:2198 ++#, c-format ++msgid "unknown register '%s' -- .req ignored" ++msgstr "" ++ ++#: config/tc-aarch64.c:1291 config/tc-arm.c:2405 ++msgid "invalid syntax for .req directive" ++msgstr "" ++ ++#: config/tc-aarch64.c:1316 config/tc-arm.c:2443 ++msgid "invalid syntax for .unreq directive" ++msgstr "" ++ ++#: config/tc-aarch64.c:1322 config/tc-arm.c:2450 ++#, c-format ++msgid "unknown register alias '%s'" ++msgstr "" ++ ++#: config/tc-aarch64.c:1324 ++#, c-format ++msgid "ignoring attempt to undefine built-in register '%s'" ++msgstr "" ++ ++#: config/tc-aarch64.c:1639 config/tc-arm.c:3108 ++msgid "literal pool overflow" ++msgstr "" ++ ++#: config/tc-aarch64.c:1792 config/tc-aarch64.c:5020 config/tc-arm.c:3278 ++#: config/tc-arm.c:6585 ++msgid "unrecognized relocation suffix" ++msgstr "" ++ ++#: config/tc-aarch64.c:1794 ++msgid "unimplemented relocation suffix" ++msgstr "" ++ ++#: config/tc-aarch64.c:1962 config/tc-aarch64.c:2196 ++msgid "immediate operand required" ++msgstr "" ++ ++#: config/tc-aarch64.c:1970 ++msgid "missing immediate expression" ++msgstr "" ++ ++#: config/tc-aarch64.c:2176 config/tc-aarch64.c:4871 ++msgid "invalid floating-point constant" ++msgstr "" ++ ++#: config/tc-aarch64.c:2548 config/tc-arm.c:4794 config/tc-arm.c:4803 ++msgid "shift expression expected" ++msgstr "" ++ ++#: config/tc-aarch64.c:2556 ++msgid "shift operator expected" ++msgstr "" ++ ++#: config/tc-aarch64.c:2564 ++msgid "invalid use of 'MSL'" ++msgstr "" ++ ++#: config/tc-aarch64.c:2573 ++msgid "extending shift is not permitted" ++msgstr "" ++ ++#: config/tc-aarch64.c:2581 ++msgid "'ROR' shift is not permitted" ++msgstr "" ++ ++#: config/tc-aarch64.c:2589 ++msgid "only 'LSL' shift is permitted" ++msgstr "" ++ ++#: config/tc-aarch64.c:2599 ++msgid "invalid shift for the register offset addressing mode" ++msgstr "" ++ ++#: config/tc-aarch64.c:2607 ++msgid "invalid shift operator" ++msgstr "" ++ ++#: config/tc-aarch64.c:2636 ++msgid "missing shift amount" ++msgstr "" ++ ++#: config/tc-aarch64.c:2643 ++msgid "constant shift amount required" ++msgstr "" ++ ++#: config/tc-aarch64.c:2648 ++msgid "shift amount out of range 0 to 63" ++msgstr "" ++ ++#: config/tc-aarch64.c:2697 ++msgid "unexpected shift operator" ++msgstr "" ++ ++#: config/tc-aarch64.c:2733 ++msgid "unexpected register in the immediate operand" ++msgstr "" ++ ++#: config/tc-aarch64.c:2758 ++msgid "integer register expected in the extended/shifted operand register" ++msgstr "" ++ ++#: config/tc-aarch64.c:2793 config/tc-aarch64.c:2904 config/tc-aarch64.c:3011 ++#: config/tc-aarch64.c:3153 config/tc-aarch64.c:3200 ++msgid "unknown relocation modifier" ++msgstr "" ++ ++#: config/tc-aarch64.c:2800 config/tc-aarch64.c:2911 config/tc-aarch64.c:3018 ++#: config/tc-aarch64.c:3160 config/tc-aarch64.c:3207 ++msgid "this relocation modifier is not allowed on this instruction" ++msgstr "" ++ ++#: config/tc-aarch64.c:2919 config/tc-aarch64.c:3029 ++msgid "invalid relocation expression" ++msgstr "" ++ ++#: config/tc-aarch64.c:2937 ++msgid "invalid address" ++msgstr "" ++ ++#: config/tc-aarch64.c:2989 ++msgid "invalid use of 32-bit register offset" ++msgstr "" ++ ++#: config/tc-aarch64.c:2995 ++msgid "invalid use of 64-bit register offset" ++msgstr "" ++ ++#. [Xn],#expr ++#: config/tc-aarch64.c:3040 config/tc-aarch64.c:3092 ++msgid "invalid expression in the address" ++msgstr "" ++ ++#: config/tc-aarch64.c:3049 config/tc-arm.c:5306 config/tc-arm.c:5876 ++msgid "']' expected" ++msgstr "" ++ ++#: config/tc-aarch64.c:3057 ++msgid "register offset not allowed in pre-indexed addressing mode" ++msgstr "" ++ ++#: config/tc-aarch64.c:3072 config/tc-arm.c:5342 ++msgid "cannot combine pre- and post-indexing" ++msgstr "" ++ ++#: config/tc-aarch64.c:3083 ++msgid "invalid 32-bit register offset" ++msgstr "" ++ ++#. Reject [Rn]! ++#: config/tc-aarch64.c:3104 ++msgid "missing offset in the pre-indexed address" ++msgstr "" ++ ++#: config/tc-aarch64.c:3318 ++#, c-format ++msgid "" ++"system register name '%s' is deprecated and may be removed in a future " ++"release" ++msgstr "" ++ ++#: config/tc-aarch64.c:3390 ++msgid "immediate value out of range " ++msgstr "" ++ ++#: config/tc-aarch64.c:3898 ++#, c-format ++msgid "Info: " ++msgstr "" ++ ++#: config/tc-aarch64.c:3932 config/tc-score.c:2750 config/tc-score.c:6504 ++#, c-format ++msgid "%s -- `%s'" ++msgstr "" ++ ++#: config/tc-aarch64.c:3934 ++#, c-format ++msgid "%s at operand %d -- `%s'" ++msgstr "" ++ ++#: config/tc-aarch64.c:3938 ++#, c-format ++msgid "operand %d should be %s -- `%s'" ++msgstr "" ++ ++#: config/tc-aarch64.c:3943 ++#, c-format ++msgid "operand mismatch -- `%s'" ++msgstr "" ++ ++#. Print the hint. ++#: config/tc-aarch64.c:4004 ++msgid " did you mean this?" ++msgstr "" ++ ++#: config/tc-aarch64.c:4007 config/tc-aarch64.c:4034 ++#, c-format ++msgid " %s" ++msgstr "" ++ ++#: config/tc-aarch64.c:4012 ++msgid " other valid variant(s):" ++msgstr "" ++ ++#: config/tc-aarch64.c:4042 ++#, c-format ++msgid "%s out of range %d to %d at operand %d -- `%s'" ++msgstr "" ++ ++#: config/tc-aarch64.c:4043 config/tc-aarch64.c:4047 config/tc-aarch64.c:5353 ++msgid "immediate value" ++msgstr "" ++ ++#: config/tc-aarch64.c:4046 ++#, c-format ++msgid "%s expected to be %d at operand %d -- `%s'" ++msgstr "" ++ ++#: config/tc-aarch64.c:4053 ++#, c-format ++msgid "" ++"invalid number of registers in the list; only 1 register is expected at " ++"operand %d -- `%s'" ++msgstr "" ++ ++#: config/tc-aarch64.c:4057 ++#, c-format ++msgid "" ++"invalid number of registers in the list; %d registers are expected at " ++"operand %d -- `%s'" ++msgstr "" ++ ++#: config/tc-aarch64.c:4063 ++#, c-format ++msgid "immediate value should be a multiple of %d at operand %d -- `%s'" ++msgstr "" ++ ++#: config/tc-aarch64.c:4314 ++msgid "bad vector arrangement type" ++msgstr "" ++ ++#: config/tc-aarch64.c:4420 ++msgid "the specified relocation type is not allowed for MOVK" ++msgstr "" ++ ++#: config/tc-aarch64.c:4449 config/tc-aarch64.c:4459 ++msgid "the specified relocation type is not allowed for 32-bit register" ++msgstr "" ++ ++#: config/tc-aarch64.c:4594 ++msgid "comma expected between operands" ++msgstr "" ++ ++#: config/tc-aarch64.c:4687 ++msgid "the top half of a 128-bit FP/SIMD register is expected" ++msgstr "" ++ ++#: config/tc-aarch64.c:4725 config/tc-arm.c:1813 config/tc-arm.c:1858 ++#: config/tc-h8300.c:1043 ++msgid "invalid register list" ++msgstr "" ++ ++#: config/tc-aarch64.c:4790 config/tc-aarch64.c:4811 ++msgid "immediate zero expected" ++msgstr "" ++ ++#: config/tc-aarch64.c:4885 ++msgid "shift not allowed for bitmask immediate" ++msgstr "" ++ ++#: config/tc-aarch64.c:4939 ++msgid "can't mix relocation modifier with explicit shift" ++msgstr "" ++ ++#: config/tc-aarch64.c:4982 ++msgid "invalid condition" ++msgstr "" ++ ++#: config/tc-aarch64.c:5007 ++msgid "invalid pc-relative address" ++msgstr "" ++ ++#. Only permit "=value" in the literal load instructions. ++#. The literal will be generated by programmer_friendly_fixup. ++#: config/tc-aarch64.c:5015 ++msgid "invalid use of \"=immediate\"" ++msgstr "" ++ ++#: config/tc-aarch64.c:5081 ++msgid "the optional immediate offset can only be 0" ++msgstr "" ++ ++#: config/tc-aarch64.c:5096 config/tc-aarch64.c:5114 config/tc-aarch64.c:5131 ++#: config/tc-aarch64.c:5150 config/tc-aarch64.c:5165 ++msgid "invalid addressing mode" ++msgstr "" ++ ++#: config/tc-aarch64.c:5136 ++msgid "relocation not allowed" ++msgstr "" ++ ++#: config/tc-aarch64.c:5175 ++msgid "writeback value should be an immediate constant" ++msgstr "" ++ ++#: config/tc-aarch64.c:5186 ++msgid "unknown or missing system register name" ++msgstr "" ++ ++#: config/tc-aarch64.c:5196 ++msgid "unknown or missing PSTATE field name" ++msgstr "" ++ ++#: config/tc-aarch64.c:5220 ++msgid "unknown or missing operation name" ++msgstr "" ++ ++#: config/tc-aarch64.c:5233 ++msgid "the specified option is not accepted in ISB" ++msgstr "" ++ ++#: config/tc-aarch64.c:5253 config/tc-aarch64.c:6305 config/tc-arm.c:6800 ++#, c-format ++msgid "unhandled operand code %d" ++msgstr "" ++ ++#: config/tc-aarch64.c:5284 ++msgid "unexpected comma before the omitted optional operand" ++msgstr "" ++ ++#: config/tc-aarch64.c:5301 ++msgid "unexpected characters following instruction" ++msgstr "" ++ ++#: config/tc-aarch64.c:5379 config/tc-arm.c:4905 config/tc-arm.c:5441 ++#: config/tc-arm.c:7318 ++msgid "constant expression expected" ++msgstr "" ++ ++#: config/tc-aarch64.c:5386 config/tc-arm.c:7359 ++msgid "literal pool insertion failed" ++msgstr "" ++ ++#: config/tc-aarch64.c:5504 ++#, c-format ++msgid "unknown mnemonic `%s' -- `%s'" ++msgstr "" ++ ++#: config/tc-aarch64.c:5512 ++#, c-format ++msgid "unexpected comma after the mnemonic name `%s' -- `%s'" ++msgstr "" ++ ++#: config/tc-aarch64.c:5562 ++#, c-format ++msgid "selected processor does not support `%s'" ++msgstr "" ++ ++#: config/tc-aarch64.c:5836 ++#, c-format ++msgid "alignments greater than %d bytes not supported in .text sections" ++msgstr "" ++ ++#: config/tc-aarch64.c:5969 config/tc-arm.c:21185 ++msgid "GOT already in the symbol table" ++msgstr "" ++ ++#: config/tc-aarch64.c:6131 ++msgid "immediate cannot be moved by a single instruction" ++msgstr "" ++ ++#: config/tc-aarch64.c:6174 config/tc-aarch64.c:6219 config/tc-aarch64.c:6245 ++#: config/tc-arm.c:14422 config/tc-arm.c:14449 config/tc-arm.c:14993 ++#: config/tc-arm.c:15474 config/tc-metag.c:2444 config/tc-metag.c:2453 ++#: config/tc-metag.c:2492 config/tc-metag.c:2501 config/tc-metag.c:3020 ++#: config/tc-metag.c:3029 ++msgid "immediate out of range" ++msgstr "" ++ ++#: config/tc-aarch64.c:6238 config/tc-metag.c:4655 config/tc-xtensa.c:4111 ++msgid "invalid immediate" ++msgstr "" ++ ++#: config/tc-aarch64.c:6300 config/tc-tic6x.c:3864 config/tc-tic6x.c:3929 ++#: config/tc-tic6x.c:3956 config/tc-tic6x.c:3984 ++msgid "immediate offset out of range" ++msgstr "" ++ ++#: config/tc-aarch64.c:6374 config/tc-arm.c:21523 config/tc-arm.c:21574 ++#: config/tc-arm.c:21855 ++#, c-format ++msgid "undefined symbol %s used as an immediate value" ++msgstr "" ++ ++#: config/tc-aarch64.c:6386 ++msgid "pc-relative load offset not word aligned" ++msgstr "" ++ ++#: config/tc-aarch64.c:6389 ++msgid "pc-relative load offset out of range" ++msgstr "" ++ ++#: config/tc-aarch64.c:6401 ++msgid "pc-relative address offset out of range" ++msgstr "" ++ ++#: config/tc-aarch64.c:6413 config/tc-aarch64.c:6428 ++msgid "conditional branch target not word aligned" ++msgstr "" ++ ++#: config/tc-aarch64.c:6416 config/tc-aarch64.c:6431 config/tc-arm.c:22118 ++msgid "conditional branch out of range" ++msgstr "" ++ ++#: config/tc-aarch64.c:6444 ++msgid "branch target not word aligned" ++msgstr "" ++ ++#: config/tc-aarch64.c:6447 config/tc-arm.c:753 config/tc-mips.c:14494 ++msgid "branch out of range" ++msgstr "" ++ ++#: config/tc-aarch64.c:6481 config/tc-arm.c:21746 config/tc-arm.c:21761 ++#: config/tc-arm.c:21776 config/tc-arm.c:21787 config/tc-arm.c:21810 ++#: config/tc-arm.c:22522 config/tc-moxie.c:710 config/tc-pj.c:448 ++#: config/tc-sh.c:4291 ++msgid "offset out of range" ++msgstr "" ++ ++#: config/tc-aarch64.c:6494 ++msgid "unsigned value out of range" ++msgstr "" ++ ++#: config/tc-aarch64.c:6502 ++msgid "signed value out of range" ++msgstr "" ++ ++#: config/tc-aarch64.c:6610 ++#, c-format ++msgid "unexpected %s fixup" ++msgstr "" ++ ++#: config/tc-aarch64.c:6676 config/tc-arm.c:22958 config/tc-arm.c:22979 ++#: config/tc-mips.c:16546 config/tc-score.c:7480 ++#, c-format ++msgid "cannot represent %s relocation in this object file format" ++msgstr "" ++ ++#: config/tc-aarch64.c:6709 ++#, c-format ++msgid "cannot do %u-byte relocation" ++msgstr "" ++ ++#: config/tc-aarch64.c:6967 config/tc-arc.c:212 config/tc-arm.c:23434 ++#: config/tc-score.c:6299 config/tc-score.c:6528 config/tc-score.c:6533 ++msgid "virtual memory exhausted" ++msgstr "" ++ ++#: config/tc-aarch64.c:7114 config/tc-arm.c:23759 ++msgid "assemble for big-endian" ++msgstr "" ++ ++#: config/tc-aarch64.c:7115 config/tc-arm.c:23760 ++msgid "assemble for little-endian" ++msgstr "" ++ ++#: config/tc-aarch64.c:7118 ++msgid "temporary switch for dumping" ++msgstr "" ++ ++#: config/tc-aarch64.c:7120 ++msgid "output verbose error messages" ++msgstr "" ++ ++#: config/tc-aarch64.c:7210 config/tc-arm.c:24261 ++msgid "invalid architectural extension" ++msgstr "" ++ ++#: config/tc-aarch64.c:7235 config/tc-arm.c:24293 ++msgid "must specify extensions to add before specifying those to remove" ++msgstr "" ++ ++#: config/tc-aarch64.c:7243 config/tc-arm.c:24301 ++msgid "missing architectural extension" ++msgstr "" ++ ++#: config/tc-aarch64.c:7262 config/tc-arm.c:24338 ++#, c-format ++msgid "unknown architectural extension `%s'" ++msgstr "" ++ ++#: config/tc-aarch64.c:7286 config/tc-arm.c:24372 config/tc-metag.c:5833 ++#, c-format ++msgid "missing cpu name `%s'" ++msgstr "" ++ ++#: config/tc-aarch64.c:7300 config/tc-aarch64.c:7519 config/tc-arm.c:24398 ++#: config/tc-arm.c:24939 config/tc-metag.c:5844 ++#, c-format ++msgid "unknown cpu `%s'" ++msgstr "" ++ ++#: config/tc-aarch64.c:7318 config/tc-arm.c:24416 ++#, c-format ++msgid "missing architecture name `%s'" ++msgstr "" ++ ++#: config/tc-aarch64.c:7332 config/tc-aarch64.c:7566 config/tc-arm.c:24433 ++#: config/tc-arm.c:24973 config/tc-arm.c:25004 config/tc-score.c:7715 ++#, c-format ++msgid "unknown architecture `%s'\n" ++msgstr "" ++ ++#: config/tc-aarch64.c:7357 ++#, c-format ++msgid "missing abi name `%s'" ++msgstr "" ++ ++#: config/tc-aarch64.c:7368 ++#, c-format ++msgid "unknown abi `%s'\n" ++msgstr "" ++ ++#: config/tc-aarch64.c:7374 ++msgid "\t specify for ABI " ++msgstr "" ++ ++#: config/tc-aarch64.c:7377 config/tc-arm.c:24511 config/tc-metag.c:5910 ++msgid "\t assemble for CPU " ++msgstr "" ++ ++#: config/tc-aarch64.c:7379 config/tc-arm.c:24513 ++msgid "\t assemble for architecture " ++msgstr "" ++ ++#: config/tc-aarch64.c:7418 config/tc-aarch64.c:7438 config/tc-arm.c:24567 ++#: config/tc-arm.c:24585 config/tc-arm.c:24605 config/tc-metag.c:5935 ++#, c-format ++msgid "option `-%c%s' is deprecated: %s" ++msgstr "" ++ ++#: config/tc-aarch64.c:7458 ++#, c-format ++msgid " AArch64-specific assembler options:\n" ++msgstr "" ++ ++#: config/tc-aarch64.c:7469 config/tc-arm.c:24636 ++#, c-format ++msgid " -EB assemble code for a big-endian cpu\n" ++msgstr "" ++ ++#: config/tc-aarch64.c:7474 config/tc-arm.c:24641 ++#, c-format ++msgid " -EL assemble code for a little-endian cpu\n" ++msgstr "" ++ +#: config/tc-alpha.c:655 +#, c-format +msgid "No !literal!%ld was found" @@ -826930,8 +831951,8 @@ index 0000000..f1eec3b +msgid "opcode `%s' not supported for target %s" +msgstr "" + -+#: config/tc-alpha.c:1194 config/tc-alpha.c:3367 config/tc-avr.c:1441 -+#: config/tc-msp430.c:1828 ++#: config/tc-alpha.c:1194 config/tc-alpha.c:3367 config/tc-avr.c:1440 ++#: config/tc-msp430.c:3521 +#, c-format +msgid "unknown opcode `%s'" +msgstr "" @@ -827012,8 +832033,8 @@ index 0000000..f1eec3b +msgstr "" + +#: config/tc-alpha.c:1998 config/tc-arc.c:292 config/tc-mn10200.c:857 -+#: config/tc-mn10300.c:1148 config/tc-ppc.c:1730 config/tc-s390.c:638 -+#: config/tc-tilegx.c:408 config/tc-tilegx.c:471 config/tc-tilepro.c:369 ++#: config/tc-mn10300.c:1150 config/tc-ppc.c:1820 config/tc-s390.c:650 ++#: config/tc-tilegx.c:427 config/tc-tilegx.c:476 config/tc-tilepro.c:383 +msgid "operand" +msgstr "" + @@ -827029,22 +832050,23 @@ index 0000000..f1eec3b +msgid "can not resolve expression" +msgstr "" + -+#: config/tc-alpha.c:3516 config/tc-i370.c:1055 config/tc-microblaze.c:185 -+#: config/tc-ppc.c:2055 config/tc-ppc.c:4892 ++#: config/tc-alpha.c:3516 config/tc-i370.c:1055 config/tc-microblaze.c:199 ++#: config/tc-ppc.c:2156 config/tc-ppc.c:5264 +#, c-format +msgid ".COMMon length (%ld.) <0! Ignored." +msgstr "" + -+#: config/tc-alpha.c:3527 config/tc-sparc.c:3963 config/tc-v850.c:298 ++#: config/tc-alpha.c:3527 config/tc-ia64.c:1104 config/tc-sparc.c:4064 ++#: config/tc-v850.c:307 +msgid "Ignoring attempt to re-define symbol" +msgstr "" + -+#: config/tc-alpha.c:3619 config/tc-ppc.c:4929 config/tc-sparc.c:3971 ++#: config/tc-alpha.c:3619 config/tc-sparc.c:4072 +#, c-format +msgid "Length of .comm \"%s\" is already %ld. Not changed to %ld." +msgstr "" + -+#: config/tc-alpha.c:3722 ecoff.c:3064 ++#: config/tc-alpha.c:3722 ecoff.c:3063 +msgid ".ent directive has no name" +msgstr "" + @@ -827052,7 +832074,7 @@ index 0000000..f1eec3b +msgid "nested .ent directives" +msgstr "" + -+#: config/tc-alpha.c:3775 ecoff.c:3015 ++#: config/tc-alpha.c:3775 ecoff.c:3014 +msgid ".end directive has no name" +msgstr "" + @@ -827064,28 +832086,28 @@ index 0000000..f1eec3b +msgid ".end directive names different symbol than .ent" +msgstr "" + -+#: config/tc-alpha.c:3829 ecoff.c:3150 ++#: config/tc-alpha.c:3829 ecoff.c:3149 +msgid ".fmask outside of .ent" +msgstr "" + -+#: config/tc-alpha.c:3831 config/tc-score.c:5598 ecoff.c:3214 ++#: config/tc-alpha.c:3831 config/tc-score.c:5598 ecoff.c:3213 +msgid ".mask outside of .ent" +msgstr "" + -+#: config/tc-alpha.c:3839 ecoff.c:3157 ++#: config/tc-alpha.c:3839 ecoff.c:3156 +msgid "bad .fmask directive" +msgstr "" + -+#: config/tc-alpha.c:3841 ecoff.c:3221 ++#: config/tc-alpha.c:3841 ecoff.c:3220 +msgid "bad .mask directive" +msgstr "" + -+#: config/tc-alpha.c:3874 config/tc-mips.c:18816 config/tc-score.c:5740 -+#: ecoff.c:3178 ++#: config/tc-alpha.c:3874 config/tc-mips.c:17705 config/tc-score.c:5740 ++#: ecoff.c:3177 +msgid ".frame outside of .ent" +msgstr "" + -+#: config/tc-alpha.c:3885 ecoff.c:3189 ++#: config/tc-alpha.c:3885 config/tc-mips.c:17716 ecoff.c:3188 +msgid "bad .frame directive" +msgstr "" + @@ -827135,122 +832157,128 @@ index 0000000..f1eec3b +msgid ".handler directive has no name" +msgstr "" + -+#: config/tc-alpha.c:4445 ++#: config/tc-alpha.c:4446 +msgid "Bad .frame directive 1./2. param" +msgstr "" + -+#: config/tc-alpha.c:4457 ++#: config/tc-alpha.c:4456 ++#, c-format ++msgid "Bad RA (%d) register for .frame" ++msgstr "" ++ ++#: config/tc-alpha.c:4461 +msgid "Bad .frame directive 3./4. param" +msgstr "" + -+#: config/tc-alpha.c:4494 ++#: config/tc-alpha.c:4497 +msgid ".pdesc directive not in link (.link) section" +msgstr "" + -+#: config/tc-alpha.c:4501 ++#: config/tc-alpha.c:4504 +msgid ".pdesc directive has no entry symbol" +msgstr "" + -+#: config/tc-alpha.c:4512 ++#: config/tc-alpha.c:4515 +msgid ".pdesc has a bad entry symbol" +msgstr "" + -+#: config/tc-alpha.c:4523 ++#: config/tc-alpha.c:4526 +msgid ".pdesc doesn't match with last .ent" +msgstr "" + -+#: config/tc-alpha.c:4538 ++#: config/tc-alpha.c:4541 +msgid "No comma after .pdesc " +msgstr "" + -+#: config/tc-alpha.c:4558 ++#: config/tc-alpha.c:4561 +msgid "unknown procedure kind" +msgstr "" + -+#: config/tc-alpha.c:4653 ++#: config/tc-alpha.c:4656 +msgid ".name directive not in link (.link) section" +msgstr "" + -+#: config/tc-alpha.c:4661 ++#: config/tc-alpha.c:4664 +msgid ".name directive has no symbol" +msgstr "" + -+#: config/tc-alpha.c:4695 ++#: config/tc-alpha.c:4698 +msgid "No symbol after .linkage" +msgstr "" + -+#: config/tc-alpha.c:4743 ++#: config/tc-alpha.c:4746 +msgid "No symbol after .code_address" +msgstr "" + -+#: config/tc-alpha.c:4769 config/tc-score.c:5604 ++#: config/tc-alpha.c:4772 config/tc-score.c:5604 +msgid "Bad .mask directive" +msgstr "" + -+#: config/tc-alpha.c:4787 ++#: config/tc-alpha.c:4790 +msgid "Bad .fmask directive" +msgstr "" + -+#: config/tc-alpha.c:4944 ++#: config/tc-alpha.c:4947 +#, c-format +msgid "Expected comma after name \"%s\"" +msgstr "" + -+#: config/tc-alpha.c:4956 ++#: config/tc-alpha.c:4959 +#, c-format +msgid "unhandled: .proc %s,%d" +msgstr "" + -+#: config/tc-alpha.c:4990 ++#: config/tc-alpha.c:4993 +#, c-format +msgid "Tried to .set unrecognized mode `%s'" +msgstr "" + -+#: config/tc-alpha.c:5016 ++#: config/tc-alpha.c:5019 +#, c-format +msgid "Bad base register, using $%d." +msgstr "" + -+#: config/tc-alpha.c:5037 ++#: config/tc-alpha.c:5040 config/tc-nios2.c:385 config/tc-nios2.c:500 +#, c-format +msgid "Alignment too large: %d. assumed" +msgstr "" + -+#: config/tc-alpha.c:5041 config/tc-d30v.c:2060 ++#: config/tc-alpha.c:5044 config/tc-d30v.c:2060 config/tc-nios2.c:389 ++#: config/tc-nios2.c:504 +msgid "Alignment negative: 0 assumed" +msgstr "" + -+#: config/tc-alpha.c:5136 config/tc-alpha.c:5628 ++#: config/tc-alpha.c:5139 config/tc-alpha.c:5631 +#, c-format +msgid "Unknown CPU identifier `%s'" +msgstr "" + -+#: config/tc-alpha.c:5327 ++#: config/tc-alpha.c:5330 +#, c-format +msgid "Chose GP value of %lx\n" +msgstr "" + -+#: config/tc-alpha.c:5341 ++#: config/tc-alpha.c:5344 +msgid "bad .section directive: want a,s,w,x,M,S,G,T in string" +msgstr "" + -+#: config/tc-alpha.c:5430 ++#: config/tc-alpha.c:5433 +#, c-format +msgid "internal error: can't hash opcode `%s': %s" +msgstr "" + -+#: config/tc-alpha.c:5466 ++#: config/tc-alpha.c:5469 +#, c-format +msgid "internal error: can't hash macro `%s': %s" +msgstr "" + -+#: config/tc-alpha.c:5550 config/tc-arm.c:6818 config/tc-arm.c:6830 ++#: config/tc-alpha.c:5553 config/tc-arm.c:6871 config/tc-arm.c:6883 +#: config/tc-i960.c:708 config/tc-xtensa.c:5315 config/tc-xtensa.c:5393 -+#: config/tc-xtensa.c:5510 config/tc-z80.c:1897 ++#: config/tc-xtensa.c:5510 config/tc-z80.c:1927 +msgid "syntax error" +msgstr "" + -+#: config/tc-alpha.c:5679 ++#: config/tc-alpha.c:5682 +msgid "" +"Alpha options:\n" +"-32addr\t\t\ttreat addresses as 32-bit values\n" @@ -827262,7 +832290,7 @@ index 0000000..f1eec3b +"\t\t\tthese variants include PALcode opcodes\n" +msgstr "" + -+#: config/tc-alpha.c:5689 ++#: config/tc-alpha.c:5692 +msgid "" +"VMS options:\n" +"-+\t\t\tencode (don't truncate) names longer than 64 characters\n" @@ -827270,62 +832298,56 @@ index 0000000..f1eec3b +"-replace/-noreplace\tenable or disable the optimization of procedure calls\n" +msgstr "" + -+#: config/tc-alpha.c:5940 ++#: config/tc-alpha.c:5943 +#, c-format +msgid "unhandled relocation type %s" +msgstr "" + -+#: config/tc-alpha.c:5953 ++#: config/tc-alpha.c:5956 +msgid "non-absolute expression in constant field" +msgstr "" + -+#: config/tc-alpha.c:5967 ++#: config/tc-alpha.c:5970 +#, c-format +msgid "type %d reloc done?\n" +msgstr "" + -+#: config/tc-alpha.c:6014 config/tc-alpha.c:6021 config/tc-mips.c:11711 -+#: config/tc-mips.c:12396 ++#: config/tc-alpha.c:6017 config/tc-alpha.c:6024 +msgid "Used $at without \".set noat\"" +msgstr "" + -+#: config/tc-alpha.c:6190 ++#: config/tc-alpha.c:6193 +#, c-format +msgid "!samegp reloc against symbol without .prologue: %s" +msgstr "" + -+#: config/tc-alpha.c:6234 config/tc-tilegx.c:1700 config/tc-tilepro.c:1499 ++#: config/tc-alpha.c:6237 config/tc-tilegx.c:1751 config/tc-tilepro.c:1531 +#: config/tc-xtensa.c:5999 +#, c-format +msgid "cannot represent `%s' relocation in object file" +msgstr "" + -+#: config/tc-alpha.c:6240 ++#: config/tc-alpha.c:6243 +#, c-format +msgid "internal error? cannot generate `%s' relocation" +msgstr "" + -+#: config/tc-alpha.c:6339 ++#: config/tc-alpha.c:6342 +#, c-format +msgid "frame reg expected, using $%d." +msgstr "" + +#: config/tc-arc.c:194 config/tc-arc.c:215 config/tc-arc.c:992 -+#: config/tc-h8300.c:77 config/tc-h8300.c:86 config/tc-h8300.c:96 -+#: config/tc-h8300.c:106 config/tc-h8300.c:116 config/tc-h8300.c:127 -+#: config/tc-h8300.c:244 config/tc-hppa.c:6887 config/tc-hppa.c:6893 -+#: config/tc-hppa.c:6899 config/tc-hppa.c:6905 config/tc-hppa.c:8312 -+#: config/tc-lm32.c:198 config/tc-mn10300.c:937 config/tc-mn10300.c:942 -+#: config/tc-mn10300.c:2433 config/tc-xc16x.c:79 config/tc-xc16x.c:86 -+#: config/tc-xc16x.c:93 ++#: config/tc-h8300.c:75 config/tc-h8300.c:84 config/tc-h8300.c:94 ++#: config/tc-h8300.c:104 config/tc-h8300.c:114 config/tc-h8300.c:125 ++#: config/tc-h8300.c:242 config/tc-hppa.c:6898 config/tc-hppa.c:6904 ++#: config/tc-hppa.c:6910 config/tc-hppa.c:6916 config/tc-hppa.c:8323 ++#: config/tc-lm32.c:197 config/tc-mips.c:3342 config/tc-mn10300.c:939 ++#: config/tc-mn10300.c:944 config/tc-mn10300.c:2441 config/tc-xc16x.c:79 ++#: config/tc-xc16x.c:86 config/tc-xc16x.c:93 +msgid "could not set architecture and machine" +msgstr "" + -+#: config/tc-arc.c:212 config/tc-arm.c:22402 config/tc-score.c:6299 -+#: config/tc-score.c:6528 config/tc-score.c:6533 -+msgid "virtual memory exhausted" -+msgstr "" -+ +#: config/tc-arc.c:432 config/tc-arc.c:671 +msgid "expected comma after operand name" +msgstr "" @@ -827412,7 +832434,7 @@ index 0000000..f1eec3b +msgid "unknown suffix class" +msgstr "" + -+#: config/tc-arc.c:862 config/tc-tic6x.c:582 ++#: config/tc-arc.c:862 config/tc-tic6x.c:581 +msgid "expected comma after symbol name" +msgstr "" + @@ -827462,8 +832484,8 @@ index 0000000..f1eec3b +msgid "missing ')' in %%-op" +msgstr "" + -+#: config/tc-arc.c:1364 config/tc-dlx.c:1201 config/tc-i960.c:2639 -+#: config/tc-m32r.c:2281 config/tc-sparc.c:3651 ++#: config/tc-arc.c:1364 config/tc-dlx.c:1206 config/tc-i960.c:2639 ++#: config/tc-m32r.c:2281 config/tc-nds32.c:5825 config/tc-sparc.c:3751 +#, c-format +msgid "internal error: can't export reloc type %d (`%s')" +msgstr "" @@ -827483,8 +832505,8 @@ index 0000000..f1eec3b + +#. xgettext:c-format. +#: config/tc-arc.c:1759 config/tc-i370.c:2207 config/tc-mn10200.c:1142 -+#: config/tc-mn10300.c:1820 config/tc-ppc.c:2970 config/tc-s390.c:1506 -+#: config/tc-v850.c:2699 ++#: config/tc-mn10300.c:1822 config/tc-ppc.c:3355 config/tc-s390.c:1524 ++#: config/tc-v850.c:3026 +#, c-format +msgid "junk at end of line: `%s'" +msgstr "" @@ -827502,823 +832524,737 @@ index 0000000..f1eec3b +msgid "conditional branch follows set of flags" +msgstr "" + -+#: config/tc-arc.c:1893 config/tc-arm.c:16330 ++#: config/tc-arc.c:1893 config/tc-arm.c:17216 +#, c-format +msgid "bad instruction `%s'" +msgstr "" + -+#: config/tc-arm.c:539 ++#: config/tc-arm.c:556 +msgid "ARM register expected" +msgstr "" + -+#: config/tc-arm.c:540 ++#: config/tc-arm.c:557 +msgid "bad or missing co-processor number" +msgstr "" + -+#: config/tc-arm.c:541 ++#: config/tc-arm.c:558 +msgid "co-processor register expected" +msgstr "" + -+#: config/tc-arm.c:542 ++#: config/tc-arm.c:559 +msgid "FPA register expected" +msgstr "" + -+#: config/tc-arm.c:543 ++#: config/tc-arm.c:560 +msgid "VFP single precision register expected" +msgstr "" + -+#: config/tc-arm.c:544 ++#: config/tc-arm.c:561 +msgid "VFP/Neon double precision register expected" +msgstr "" + -+#: config/tc-arm.c:545 ++#: config/tc-arm.c:562 +msgid "Neon quad precision register expected" +msgstr "" + -+#: config/tc-arm.c:546 ++#: config/tc-arm.c:563 +msgid "VFP single or double precision register expected" +msgstr "" + -+#: config/tc-arm.c:547 ++#: config/tc-arm.c:564 +msgid "Neon double or quad precision register expected" +msgstr "" + -+#: config/tc-arm.c:548 ++#: config/tc-arm.c:565 +msgid "VFP single, double or Neon quad precision register expected" +msgstr "" + -+#: config/tc-arm.c:549 ++#: config/tc-arm.c:566 +msgid "VFP system register expected" +msgstr "" + -+#: config/tc-arm.c:550 ++#: config/tc-arm.c:567 +msgid "Maverick MVF register expected" +msgstr "" + -+#: config/tc-arm.c:551 ++#: config/tc-arm.c:568 +msgid "Maverick MVD register expected" +msgstr "" + -+#: config/tc-arm.c:552 ++#: config/tc-arm.c:569 +msgid "Maverick MVFX register expected" +msgstr "" + -+#: config/tc-arm.c:553 ++#: config/tc-arm.c:570 +msgid "Maverick MVDX register expected" +msgstr "" + -+#: config/tc-arm.c:554 ++#: config/tc-arm.c:571 +msgid "Maverick MVAX register expected" +msgstr "" + -+#: config/tc-arm.c:555 ++#: config/tc-arm.c:572 +msgid "Maverick DSPSC register expected" +msgstr "" + -+#: config/tc-arm.c:556 ++#: config/tc-arm.c:573 +msgid "iWMMXt data register expected" +msgstr "" + -+#: config/tc-arm.c:557 config/tc-arm.c:6597 ++#: config/tc-arm.c:574 config/tc-arm.c:6650 +msgid "iWMMXt control register expected" +msgstr "" + -+#: config/tc-arm.c:558 ++#: config/tc-arm.c:575 +msgid "iWMMXt scalar register expected" +msgstr "" + -+#: config/tc-arm.c:559 ++#: config/tc-arm.c:576 +msgid "XScale accumulator register expected" +msgstr "" + +#. For score5u : div/mul will pop warning message, mmu/alw/asw will pop error message. -+#: config/tc-arm.c:708 config/tc-score.c:259 ++#: config/tc-arm.c:734 config/tc-score.c:259 +msgid "bad arguments to instruction" +msgstr "" + -+#: config/tc-arm.c:709 ++#: config/tc-arm.c:735 +msgid "r13 not allowed here" +msgstr "" + -+#: config/tc-arm.c:710 ++#: config/tc-arm.c:736 +msgid "r15 not allowed here" +msgstr "" + -+#: config/tc-arm.c:711 ++#: config/tc-arm.c:737 +msgid "instruction cannot be conditional" +msgstr "" + -+#: config/tc-arm.c:712 ++#: config/tc-arm.c:738 +msgid "registers may not be the same" +msgstr "" + -+#: config/tc-arm.c:713 ++#: config/tc-arm.c:739 +msgid "lo register required" +msgstr "" + -+#: config/tc-arm.c:714 ++#: config/tc-arm.c:740 +msgid "instruction not supported in Thumb16 mode" +msgstr "" + -+#: config/tc-arm.c:715 ++#: config/tc-arm.c:741 +msgid "instruction does not accept this addressing mode" +msgstr "" + -+#: config/tc-arm.c:716 ++#: config/tc-arm.c:742 +msgid "branch must be last instruction in IT block" +msgstr "" + -+#: config/tc-arm.c:717 ++#: config/tc-arm.c:743 +msgid "instruction not allowed in IT block" +msgstr "" + -+#: config/tc-arm.c:718 ++#: config/tc-arm.c:744 +msgid "selected FPU does not support instruction" +msgstr "" + -+#: config/tc-arm.c:719 ++#: config/tc-arm.c:745 +msgid "thumb conditional instruction should be in IT block" +msgstr "" + -+#: config/tc-arm.c:720 ++#: config/tc-arm.c:746 +msgid "incorrect condition in IT block" +msgstr "" + -+#: config/tc-arm.c:721 ++#: config/tc-arm.c:747 +msgid "IT falling in the range of a previous IT block" +msgstr "" + -+#: config/tc-arm.c:722 ++#: config/tc-arm.c:748 +msgid "missing .fnstart before unwinding directive" +msgstr "" + -+#: config/tc-arm.c:724 ++#: config/tc-arm.c:750 +msgid "cannot use register index with PC-relative addressing" +msgstr "" + -+#: config/tc-arm.c:726 ++#: config/tc-arm.c:752 +msgid "cannot use writeback with PC-relative addressing" +msgstr "" + -+#: config/tc-arm.c:727 -+msgid "branch out of range" ++#: config/tc-arm.c:754 ++msgid "using " +msgstr "" + -+#: config/tc-arm.c:921 ++#: config/tc-arm.c:951 +msgid "immediate expression requires a # prefix" +msgstr "" + -+#: config/tc-arm.c:949 read.c:3663 ++#: config/tc-arm.c:979 read.c:3727 +msgid "missing expression" +msgstr "" + -+#: config/tc-arm.c:949 config/tc-score.c:6515 expr.c:1357 read.c:2456 -+msgid "bad expression" -+msgstr "" -+ -+#: config/tc-arm.c:960 config/tc-i860.c:1004 config/tc-sparc.c:3023 -+msgid "bad segment" -+msgstr "" -+ -+#: config/tc-arm.c:979 config/tc-arm.c:4883 config/tc-i960.c:1300 ++#: config/tc-arm.c:1009 config/tc-arm.c:4917 config/tc-i960.c:1300 +#: config/tc-score.c:1210 +msgid "invalid constant" +msgstr "" + -+#: config/tc-arm.c:1109 ++#: config/tc-arm.c:1139 +msgid "expected #constant" +msgstr "" + -+#: config/tc-arm.c:1270 ++#: config/tc-arm.c:1302 +#, c-format +msgid "unexpected character `%c' in type specifier" +msgstr "" + -+#: config/tc-arm.c:1287 ++#: config/tc-arm.c:1319 +#, c-format +msgid "bad size %d in type specifier" +msgstr "" + -+#: config/tc-arm.c:1337 ++#: config/tc-arm.c:1369 +msgid "only one type should be specified for operand" +msgstr "" + -+#: config/tc-arm.c:1343 -+msgid "vector type expected" -+msgstr "" -+ -+#: config/tc-arm.c:1415 ++#: config/tc-arm.c:1447 +msgid "can't redefine type for operand" +msgstr "" + -+#: config/tc-arm.c:1426 ++#: config/tc-arm.c:1458 +msgid "only D registers may be indexed" +msgstr "" + -+#: config/tc-arm.c:1432 ++#: config/tc-arm.c:1464 +msgid "can't change index for operand" +msgstr "" + -+#: config/tc-arm.c:1448 config/tc-arm.c:3367 config/tc-arm.c:4465 -+msgid "constant expression required" -+msgstr "" -+ -+#: config/tc-arm.c:1495 ++#: config/tc-arm.c:1527 +msgid "register operand expected, but got scalar" +msgstr "" + -+#: config/tc-arm.c:1528 ++#: config/tc-arm.c:1560 +msgid "scalar must have an index" +msgstr "" + -+#: config/tc-arm.c:1533 config/tc-arm.c:14916 config/tc-arm.c:14966 -+#: config/tc-arm.c:15381 ++#: config/tc-arm.c:1565 config/tc-arm.c:15368 config/tc-arm.c:15428 ++#: config/tc-arm.c:15850 +msgid "scalar index out of range" +msgstr "" + -+#: config/tc-arm.c:1581 ++#: config/tc-arm.c:1615 +msgid "bad range in register list" +msgstr "" + -+#: config/tc-arm.c:1589 config/tc-arm.c:1598 config/tc-arm.c:1639 ++#: config/tc-arm.c:1623 config/tc-arm.c:1632 config/tc-arm.c:1673 +#, c-format +msgid "Warning: duplicated register (r%d) in register list" +msgstr "" + -+#: config/tc-arm.c:1601 ++#: config/tc-arm.c:1635 +msgid "Warning: register range not in ascending order" +msgstr "" + -+#: config/tc-arm.c:1612 ++#: config/tc-arm.c:1646 +msgid "missing `}'" +msgstr "" + -+#: config/tc-arm.c:1628 ++#: config/tc-arm.c:1662 +msgid "invalid register mask" +msgstr "" + -+#: config/tc-arm.c:1710 -+msgid "expecting {" -+msgstr "" -+ -+#: config/tc-arm.c:1765 config/tc-arm.c:1809 ++#: config/tc-arm.c:1797 config/tc-arm.c:1841 +msgid "register out of range in list" +msgstr "" + -+#: config/tc-arm.c:1781 config/tc-arm.c:1826 config/tc-h8300.c:1040 -+#: config/tc-mips.c:13602 config/tc-mips.c:13624 -+msgid "invalid register list" -+msgstr "" -+ -+#: config/tc-arm.c:1787 config/tc-arm.c:3881 config/tc-arm.c:4014 ++#: config/tc-arm.c:1819 config/tc-arm.c:3915 config/tc-arm.c:4049 +msgid "register list not in ascending order" +msgstr "" + -+#: config/tc-arm.c:1818 ++#: config/tc-arm.c:1850 +msgid "register range not in ascending order" +msgstr "" + -+#: config/tc-arm.c:1851 ++#: config/tc-arm.c:1883 +msgid "non-contiguous register range" +msgstr "" + -+#: config/tc-arm.c:1910 ++#: config/tc-arm.c:1942 +msgid "register stride must be 1 or 2" +msgstr "" + -+#: config/tc-arm.c:1911 ++#: config/tc-arm.c:1943 +msgid "mismatched element/structure types in list" +msgstr "" + -+#: config/tc-arm.c:1975 ++#: config/tc-arm.c:2007 +msgid "don't use Rn-Rm syntax with non-unit stride" +msgstr "" + -+#: config/tc-arm.c:2030 ++#: config/tc-arm.c:2062 +msgid "error parsing element/structure list" +msgstr "" + -+#: config/tc-arm.c:2036 ++#: config/tc-arm.c:2068 +msgid "expected }" +msgstr "" + -+#: config/tc-arm.c:2093 -+#, c-format -+msgid "ignoring attempt to redefine built-in register '%s'" -+msgstr "" -+ -+#: config/tc-arm.c:2098 -+#, c-format -+msgid "ignoring redefinition of register alias '%s'" -+msgstr "" -+ -+#: config/tc-arm.c:2126 ++#: config/tc-arm.c:2159 +msgid "attempt to redefine typed alias" +msgstr "" + -+#: config/tc-arm.c:2165 -+#, c-format -+msgid "unknown register '%s' -- .req ignored" -+msgstr "" -+ -+#: config/tc-arm.c:2260 ++#: config/tc-arm.c:2293 +msgid "bad type for register" +msgstr "" + -+#: config/tc-arm.c:2271 ++#: config/tc-arm.c:2304 +msgid "expression must be constant" +msgstr "" + -+#: config/tc-arm.c:2288 ++#: config/tc-arm.c:2321 +msgid "can't redefine the type of a register alias" +msgstr "" + -+#: config/tc-arm.c:2295 ++#: config/tc-arm.c:2328 +msgid "you must specify a single type only" +msgstr "" + -+#: config/tc-arm.c:2308 ++#: config/tc-arm.c:2341 +msgid "can't redefine the index of a scalar alias" +msgstr "" + -+#: config/tc-arm.c:2316 ++#: config/tc-arm.c:2349 +msgid "scalar index must be constant" +msgstr "" + -+#: config/tc-arm.c:2325 ++#: config/tc-arm.c:2358 +msgid "expecting ]" +msgstr "" + -+#: config/tc-arm.c:2372 -+msgid "invalid syntax for .req directive" -+msgstr "" -+ -+#: config/tc-arm.c:2378 ++#: config/tc-arm.c:2411 +msgid "invalid syntax for .dn directive" +msgstr "" + -+#: config/tc-arm.c:2384 ++#: config/tc-arm.c:2417 +msgid "invalid syntax for .qn directive" +msgstr "" + -+#: config/tc-arm.c:2410 -+msgid "invalid syntax for .unreq directive" -+msgstr "" -+ -+#: config/tc-arm.c:2417 -+#, c-format -+msgid "unknown register alias '%s'" -+msgstr "" -+ -+#: config/tc-arm.c:2419 ++#: config/tc-arm.c:2452 +#, c-format +msgid "ignoring attempt to use .unreq on fixed register name: '%s'" +msgstr "" + -+#: config/tc-arm.c:2687 ++#: config/tc-arm.c:2720 +#, c-format +msgid "Failed to find real start of function: %s\n" +msgstr "" + -+#: config/tc-arm.c:2704 ++#: config/tc-arm.c:2737 +msgid "selected processor does not support THUMB opcodes" +msgstr "" + -+#: config/tc-arm.c:2717 ++#: config/tc-arm.c:2750 +msgid "selected processor does not support ARM opcodes" +msgstr "" + -+#: config/tc-arm.c:2729 ++#: config/tc-arm.c:2762 +#, c-format +msgid "invalid instruction size selected (%d)" +msgstr "" + -+#: config/tc-arm.c:2761 ++#: config/tc-arm.c:2794 +#, c-format +msgid "invalid operand to .code directive (%d) (expecting 16 or 32)" +msgstr "" + -+#: config/tc-arm.c:2817 ++#: config/tc-arm.c:2850 +#, c-format +msgid "expected comma after name \"%s\"" +msgstr "" + -+#: config/tc-arm.c:2867 config/tc-m32r.c:588 ++#: config/tc-arm.c:2900 config/tc-m32r.c:588 +#, c-format +msgid "symbol `%s' already defined" +msgstr "" + -+#: config/tc-arm.c:2901 ++#: config/tc-arm.c:2934 +#, c-format +msgid "unrecognized syntax mode \"%s\"" +msgstr "" + -+#: config/tc-arm.c:2922 ++#: config/tc-arm.c:2955 +#, c-format +msgid "alignment too large: %d assumed" +msgstr "" + -+#: config/tc-arm.c:2925 ++#: config/tc-arm.c:2958 +msgid "alignment negative. 0 assumed." +msgstr "" + -+#: config/tc-arm.c:3075 -+msgid "literal pool overflow" -+msgstr "" -+ -+#: config/tc-arm.c:3245 config/tc-arm.c:6532 -+msgid "unrecognized relocation suffix" -+msgstr "" -+ -+#: config/tc-arm.c:3260 ++#: config/tc-arm.c:3293 +msgid "(plt) is only valid on branch targets" +msgstr "" + -+#: config/tc-arm.c:3266 config/tc-s390.c:1134 config/tc-s390.c:1771 ++#: config/tc-arm.c:3299 config/tc-s390.c:1146 config/tc-s390.c:1789 +#: config/tc-xtensa.c:1591 +#, c-format +msgid "%s relocations do not fit in %d bytes" +msgstr "" + -+#: config/tc-arm.c:3343 ++#: config/tc-arm.c:3376 +msgid ".inst.n operand too big. Use .inst.w instead" +msgstr "" + -+#: config/tc-arm.c:3363 ++#: config/tc-arm.c:3396 +msgid "cannot determine Thumb instruction size. Use .inst.n/.inst.w instead" +msgstr "" + -+#: config/tc-arm.c:3393 ++#: config/tc-arm.c:3426 +msgid "width suffixes are invalid in ARM mode" +msgstr "" + -+#: config/tc-arm.c:3435 dwarf2dbg.c:744 ++#: config/tc-arm.c:3468 dwarf2dbg.c:762 +msgid "expected 0 or 1" +msgstr "" + -+#: config/tc-arm.c:3439 ++#: config/tc-arm.c:3472 +msgid "missing comma" +msgstr "" + -+#: config/tc-arm.c:3472 ++#: config/tc-arm.c:3505 +msgid "duplicate .fnstart directive" +msgstr "" + -+#: config/tc-arm.c:3503 config/tc-tic6x.c:413 ++#: config/tc-arm.c:3536 config/tc-tic6x.c:412 +msgid "duplicate .handlerdata directive" +msgstr "" + -+#: config/tc-arm.c:3522 ++#: config/tc-arm.c:3555 +msgid ".fnend directive without .fnstart" +msgstr "" + -+#: config/tc-arm.c:3588 config/tc-tic6x.c:394 ++#: config/tc-arm.c:3622 config/tc-tic6x.c:393 +msgid "personality routine specified for cantunwind frame" +msgstr "" + -+#: config/tc-arm.c:3605 config/tc-tic6x.c:455 ++#: config/tc-arm.c:3639 config/tc-tic6x.c:454 +msgid "duplicate .personalityindex directive" +msgstr "" + -+#: config/tc-arm.c:3612 config/tc-tic6x.c:462 ++#: config/tc-arm.c:3646 config/tc-tic6x.c:461 +msgid "bad personality routine number" +msgstr "" + -+#: config/tc-arm.c:3634 config/tc-tic6x.c:479 ++#: config/tc-arm.c:3668 config/tc-tic6x.c:478 +msgid "duplicate .personality directive" +msgstr "" + -+#: config/tc-arm.c:3657 config/tc-arm.c:3785 config/tc-arm.c:3833 ++#: config/tc-arm.c:3691 config/tc-arm.c:3819 config/tc-arm.c:3867 +msgid "expected register list" +msgstr "" + -+#: config/tc-arm.c:3739 ++#: config/tc-arm.c:3773 +msgid "expected , " +msgstr "" + -+#: config/tc-arm.c:3748 ++#: config/tc-arm.c:3782 +msgid "number of registers must be in the range [1:4]" +msgstr "" + -+#: config/tc-arm.c:3895 config/tc-arm.c:4028 ++#: config/tc-arm.c:3929 config/tc-arm.c:4063 +msgid "bad register range" +msgstr "" + -+#: config/tc-arm.c:4085 -+msgid "register expected" -+msgstr "" -+ -+#: config/tc-arm.c:4095 ++#: config/tc-arm.c:4129 +msgid "FPA .unwind_save does not take a register list" +msgstr "" + -+#: config/tc-arm.c:4114 ++#: config/tc-arm.c:4148 +msgid ".unwind_save does not support this kind of register" +msgstr "" + -+#: config/tc-arm.c:4153 ++#: config/tc-arm.c:4187 +msgid "SP and PC not permitted in .unwind_movsp directive" +msgstr "" + -+#: config/tc-arm.c:4158 ++#: config/tc-arm.c:4192 +msgid "unexpected .unwind_movsp directive" +msgstr "" + -+#: config/tc-arm.c:4185 ++#: config/tc-arm.c:4219 +msgid "stack increment must be multiple of 4" +msgstr "" + -+#: config/tc-arm.c:4217 ++#: config/tc-arm.c:4251 +msgid "expected , " +msgstr "" + -+#: config/tc-arm.c:4235 ++#: config/tc-arm.c:4269 +msgid "register must be either sp or set by a previousunwind_movsp directive" +msgstr "" + -+#: config/tc-arm.c:4274 ++#: config/tc-arm.c:4308 +msgid "expected , " +msgstr "" + -+#: config/tc-arm.c:4286 ++#: config/tc-arm.c:4320 +msgid "unwind opcode too long" +msgstr "" + -+#: config/tc-arm.c:4291 ++#: config/tc-arm.c:4325 +msgid "invalid unwind opcode" +msgstr "" + -+#: config/tc-arm.c:4471 config/tc-arm.c:5410 config/tc-arm.c:9497 -+#: config/tc-arm.c:10032 config/tc-arm.c:13378 config/tc-arm.c:21410 -+#: config/tc-arm.c:21435 config/tc-arm.c:21443 config/tc-z8k.c:1144 -+#: config/tc-z8k.c:1154 ++#: config/tc-arm.c:4505 config/tc-arm.c:5447 config/tc-arm.c:9688 ++#: config/tc-arm.c:10211 config/tc-arm.c:12231 config/tc-arm.c:13664 ++#: config/tc-arm.c:22438 config/tc-arm.c:22463 config/tc-arm.c:22471 ++#: config/tc-metag.c:5175 config/tc-z8k.c:1144 config/tc-z8k.c:1154 +msgid "immediate value out of range" +msgstr "" + -+#: config/tc-arm.c:4636 ++#: config/tc-arm.c:4670 +msgid "invalid FPA immediate expression" +msgstr "" + -+#: config/tc-arm.c:4760 config/tc-arm.c:4769 -+msgid "shift expression expected" -+msgstr "" -+ -+#: config/tc-arm.c:4783 ++#: config/tc-arm.c:4817 +msgid "'LSL' or 'ASR' required" +msgstr "" + -+#: config/tc-arm.c:4791 ++#: config/tc-arm.c:4825 +msgid "'LSL' required" +msgstr "" + -+#: config/tc-arm.c:4799 ++#: config/tc-arm.c:4833 +msgid "'ASR' required" +msgstr "" + -+#: config/tc-arm.c:4871 config/tc-arm.c:5404 config/tc-arm.c:7259 -+msgid "constant expression expected" -+msgstr "" -+ -+#: config/tc-arm.c:4878 ++#: config/tc-arm.c:4912 +msgid "invalid rotation" +msgstr "" + -+#: config/tc-arm.c:5037 config/tc-arm.c:5201 ++#: config/tc-arm.c:5071 config/tc-arm.c:5238 +msgid "unknown group relocation" +msgstr "" + -+#: config/tc-arm.c:5073 ++#: config/tc-arm.c:5107 +msgid "alignment must be constant" +msgstr "" + -+#: config/tc-arm.c:5232 ++#: config/tc-arm.c:5269 +msgid "this group relocation is not allowed on this instruction" +msgstr "" + -+#: config/tc-arm.c:5269 config/tc-arm.c:5817 -+msgid "']' expected" -+msgstr "" -+ -+#: config/tc-arm.c:5287 ++#: config/tc-arm.c:5324 +msgid "'}' expected at end of 'option' field" +msgstr "" + -+#: config/tc-arm.c:5292 ++#: config/tc-arm.c:5329 +msgid "cannot combine index with option" +msgstr "" + -+#: config/tc-arm.c:5305 -+msgid "cannot combine pre- and post-indexing" -+msgstr "" -+ -+#: config/tc-arm.c:5548 ++#: config/tc-arm.c:5585 +msgid "unexpected bit specified after APSR" +msgstr "" + -+#: config/tc-arm.c:5560 ++#: config/tc-arm.c:5597 +msgid "selected processor does not support DSP extension" +msgstr "" + -+#: config/tc-arm.c:5572 ++#: config/tc-arm.c:5609 +msgid "bad bitmask specified after APSR" +msgstr "" + -+#: config/tc-arm.c:5596 ++#: config/tc-arm.c:5633 +msgid "writing to APSR without specifying a bitmask is deprecated" +msgstr "" + -+#: config/tc-arm.c:5608 config/tc-arm.c:11125 config/tc-arm.c:11164 -+#: config/tc-arm.c:11168 ++#: config/tc-arm.c:5645 config/tc-arm.c:11356 config/tc-arm.c:11400 ++#: config/tc-arm.c:11404 +msgid "selected processor does not support requested special purpose register" +msgstr "" + -+#: config/tc-arm.c:5613 ++#: config/tc-arm.c:5650 +msgid "flag for {c}psr instruction expected" +msgstr "" + -+#: config/tc-arm.c:5638 ++#: config/tc-arm.c:5675 +msgid "unrecognized CPS flag" +msgstr "" + -+#: config/tc-arm.c:5645 ++#: config/tc-arm.c:5682 +msgid "missing CPS flags" +msgstr "" + -+#: config/tc-arm.c:5668 config/tc-arm.c:5674 ++#: config/tc-arm.c:5705 config/tc-arm.c:5711 +msgid "valid endian specifiers are be or le" +msgstr "" + -+#: config/tc-arm.c:5696 ++#: config/tc-arm.c:5733 +msgid "missing rotation field after comma" +msgstr "" + -+#: config/tc-arm.c:5711 ++#: config/tc-arm.c:5748 +msgid "rotation can only be 0, 8, 16, or 24" +msgstr "" + -+#: config/tc-arm.c:5740 ++#: config/tc-arm.c:5777 +msgid "condition required" +msgstr "" + -+#: config/tc-arm.c:5779 config/tc-arm.c:7846 ++#: config/tc-arm.c:5838 config/tc-arm.c:8012 +msgid "'[' expected" +msgstr "" + -+#: config/tc-arm.c:5792 ++#: config/tc-arm.c:5851 +msgid "',' expected" +msgstr "" + -+#: config/tc-arm.c:5809 ++#: config/tc-arm.c:5868 +msgid "invalid shift" +msgstr "" + -+#: config/tc-arm.c:5882 ++#: config/tc-arm.c:5941 +msgid "can't use Neon quad register here" +msgstr "" + -+#: config/tc-arm.c:5948 ++#: config/tc-arm.c:6007 +msgid "expected or or operand" +msgstr "" + -+#: config/tc-arm.c:6028 ++#: config/tc-arm.c:6087 +msgid "parse error" +msgstr "" + -+#: config/tc-arm.c:6038 read.c:2127 -+msgid "expected comma" -+msgstr "" -+ +#. ISB can only take SY as an option. -+#: config/tc-arm.c:6298 ++#: config/tc-arm.c:6351 +msgid "invalid barrier type" +msgstr "" + -+#: config/tc-arm.c:6435 ++#: config/tc-arm.c:6488 +msgid "immediate value is out of range" +msgstr "" + -+#: config/tc-arm.c:6582 ++#: config/tc-arm.c:6635 +msgid "iWMMXt data or control register expected" +msgstr "" + -+#: config/tc-arm.c:6622 ++#: config/tc-arm.c:6675 +msgid "Banked registers are not available with this architecture." +msgstr "" + -+#: config/tc-arm.c:6747 -+#, c-format -+msgid "unhandled operand code %d" -+msgstr "" -+ -+#: config/tc-arm.c:6844 config/tc-score.c:264 ++#: config/tc-arm.c:6897 config/tc-score.c:264 +msgid "garbage following instruction" +msgstr "" + +#. If REG is R13 (the stack pointer), warn that its use is +#. deprecated. -+#: config/tc-arm.c:6885 ++#: config/tc-arm.c:6938 +msgid "use of r13 is deprecated" +msgstr "" + -+#: config/tc-arm.c:6955 ++#: config/tc-arm.c:7008 +msgid "D register out of range for selected VFP version" +msgstr "" + -+#: config/tc-arm.c:7038 ++#: config/tc-arm.c:7087 config/tc-arm.c:9416 ++msgid "Instruction does not support =N addresses" ++msgstr "" ++ ++#: config/tc-arm.c:7095 +msgid "instruction does not accept preindexed addressing" +msgstr "" + +#. unindexed - only for coprocessor -+#: config/tc-arm.c:7054 config/tc-arm.c:9290 ++#: config/tc-arm.c:7111 config/tc-arm.c:9479 +msgid "instruction does not accept unindexed addressing" +msgstr "" + -+#: config/tc-arm.c:7062 ++#: config/tc-arm.c:7119 +msgid "destination register same as write-back base" +msgstr "" + -+#: config/tc-arm.c:7063 ++#: config/tc-arm.c:7120 +msgid "source register same as write-back base" +msgstr "" + -+#: config/tc-arm.c:7113 ++#: config/tc-arm.c:7170 +msgid "use of PC in this instruction is deprecated" +msgstr "" + -+#: config/tc-arm.c:7136 ++#: config/tc-arm.c:7193 +msgid "instruction does not accept scaled register index" +msgstr "" + -+#: config/tc-arm.c:7188 ++#: config/tc-arm.c:7247 +msgid "instruction does not support unindexed addressing" +msgstr "" + -+#: config/tc-arm.c:7203 ++#: config/tc-arm.c:7262 +msgid "pc may not be used with write-back" +msgstr "" + -+#: config/tc-arm.c:7208 ++#: config/tc-arm.c:7267 +msgid "instruction does not support writeback" +msgstr "" + -+#: config/tc-arm.c:7254 ++#: config/tc-arm.c:7313 +msgid "invalid pseudo operation" +msgstr "" + -+#: config/tc-arm.c:7300 -+msgid "literal pool insertion failed" -+msgstr "" -+ -+#: config/tc-arm.c:7359 ++#: config/tc-arm.c:7442 +msgid "Rn must not overlap other operands" +msgstr "" + -+#: config/tc-arm.c:7364 -+msgid "swp{b} use is deprecated for this architecture" ++#: config/tc-arm.c:7447 ++msgid "swp{b} use is obsoleted for ARMv8 and later" +msgstr "" + -+#: config/tc-arm.c:7461 config/tc-arm.c:9864 -+msgid "bad barrier type" ++#: config/tc-arm.c:7450 ++msgid "swp{b} use is deprecated for ARMv6 and ARMv7" +msgstr "" + -+#: config/tc-arm.c:7472 config/tc-arm.c:7491 config/tc-arm.c:7504 -+#: config/tc-arm.c:9876 config/tc-arm.c:9907 config/tc-arm.c:9929 ++#: config/tc-arm.c:7552 config/tc-arm.c:7571 config/tc-arm.c:7584 ++#: config/tc-arm.c:10052 config/tc-arm.c:10083 config/tc-arm.c:10105 +msgid "bit-field extends past end of register" +msgstr "" + -+#: config/tc-arm.c:7534 ++#: config/tc-arm.c:7614 +msgid "the only valid suffixes here are '(plt)' and '(tlscall)'" +msgstr "" + -+#: config/tc-arm.c:7587 ++#: config/tc-arm.c:7667 +msgid "use of r15 in blx in ARM mode is not really useful" +msgstr "" + -+#: config/tc-arm.c:7609 ++#: config/tc-arm.c:7689 +msgid "use of r15 in bx in ARM mode is not really useful" +msgstr "" + -+#: config/tc-arm.c:7634 ++#: config/tc-arm.c:7714 +msgid "use of r15 in bxj is not really useful" +msgstr "" + -+#: config/tc-arm.c:7813 config/tc-arm.c:7822 ++#: config/tc-arm.c:7762 ++msgid "This coprocessor register access is deprecated in ARMv8" ++msgstr "" ++ ++#: config/tc-arm.c:7962 config/tc-arm.c:7971 +msgid "writeback of base register is UNPREDICTABLE" +msgstr "" + -+#: config/tc-arm.c:7816 ++#: config/tc-arm.c:7965 +msgid "writeback of base register when in register list is UNPREDICTABLE" +msgstr "" + -+#: config/tc-arm.c:7826 ++#: config/tc-arm.c:7975 +msgid "if writeback register is in list, it must be the lowest reg in the list" +msgstr "" + -+#: config/tc-arm.c:7841 ++#: config/tc-arm.c:8007 +msgid "first transfer register must be even" +msgstr "" + -+#: config/tc-arm.c:7844 ++#: config/tc-arm.c:8010 +msgid "can only transfer two consecutive registers" +msgstr "" + @@ -828326,1186 +833262,1151 @@ index 0000000..f1eec3b +#. have been called in the first place. +#. If op 2 were present and equal to PC, this function wouldn't +#. have been called in the first place. -+#: config/tc-arm.c:7845 config/tc-arm.c:7915 config/tc-arm.c:8544 -+#: config/tc-arm.c:10652 ++#: config/tc-arm.c:8011 config/tc-arm.c:8081 config/tc-arm.c:8714 ++#: config/tc-arm.c:10857 +msgid "r14 not allowed here" +msgstr "" + -+#: config/tc-arm.c:7857 ++#: config/tc-arm.c:8023 +msgid "base register written back, and overlaps second transfer register" +msgstr "" + -+#: config/tc-arm.c:7867 ++#: config/tc-arm.c:8033 +msgid "index register overlaps transfer register" +msgstr "" + -+#: config/tc-arm.c:7896 config/tc-arm.c:8511 ++#: config/tc-arm.c:8062 config/tc-arm.c:8681 +msgid "offset must be zero in ARM encoding" +msgstr "" + -+#: config/tc-arm.c:7909 config/tc-arm.c:8538 ++#: config/tc-arm.c:8075 config/tc-arm.c:8708 +msgid "even register required" +msgstr "" + -+#: config/tc-arm.c:7912 ++#: config/tc-arm.c:8078 +msgid "can only load two consecutive registers" +msgstr "" + -+#: config/tc-arm.c:7930 ++#: config/tc-arm.c:8096 +msgid "ldr to register 15 must be 4-byte alligned" +msgstr "" + -+#: config/tc-arm.c:7953 config/tc-arm.c:7985 ++#: config/tc-arm.c:8119 config/tc-arm.c:8151 +msgid "this instruction requires a post-indexed address" +msgstr "" + -+#: config/tc-arm.c:8012 ++#: config/tc-arm.c:8178 +msgid "Rd and Rm should be different in mla" +msgstr "" + -+#: config/tc-arm.c:8036 config/tc-arm.c:10996 ++#: config/tc-arm.c:8202 config/tc-arm.c:11221 +msgid ":lower16: not allowed this instruction" +msgstr "" + -+#: config/tc-arm.c:8038 ++#: config/tc-arm.c:8204 +msgid ":upper16: not allowed instruction" +msgstr "" + -+#: config/tc-arm.c:8057 config/tc-arm.c:8100 ++#: config/tc-arm.c:8223 +msgid "operand 1 must be FPSCR" +msgstr "" + -+#: config/tc-arm.c:8119 -+msgid "operand 0 must be FPSCR" -+msgstr "" -+ -+#: config/tc-arm.c:8139 config/tc-arm.c:11114 ++#: config/tc-arm.c:8305 config/tc-arm.c:11340 +msgid "bad register for mrs" +msgstr "" + -+#: config/tc-arm.c:8146 config/tc-arm.c:11131 ++#: config/tc-arm.c:8312 config/tc-arm.c:11363 +msgid "'APSR', 'CPSR' or 'SPSR' expected" +msgstr "" + -+#: config/tc-arm.c:8187 ++#: config/tc-arm.c:8353 +msgid "Rd and Rm should be different in mul" +msgstr "" + -+#: config/tc-arm.c:8206 config/tc-arm.c:8456 config/tc-arm.c:11265 ++#: config/tc-arm.c:8372 config/tc-arm.c:8626 config/tc-arm.c:11501 +msgid "rdhi and rdlo must be different" +msgstr "" + -+#: config/tc-arm.c:8212 ++#: config/tc-arm.c:8378 +msgid "rdhi, rdlo and rm must all be different" +msgstr "" + -+#: config/tc-arm.c:8278 ++#: config/tc-arm.c:8444 +msgid "'[' expected after PLD mnemonic" +msgstr "" + -+#: config/tc-arm.c:8280 config/tc-arm.c:8295 ++#: config/tc-arm.c:8446 config/tc-arm.c:8461 +msgid "post-indexed expression used in preload instruction" +msgstr "" + -+#: config/tc-arm.c:8282 config/tc-arm.c:8297 ++#: config/tc-arm.c:8448 config/tc-arm.c:8463 +msgid "writeback used in preload instruction" +msgstr "" + -+#: config/tc-arm.c:8284 config/tc-arm.c:8299 ++#: config/tc-arm.c:8450 config/tc-arm.c:8465 +msgid "unindexed addressing used in preload instruction" +msgstr "" + -+#: config/tc-arm.c:8293 ++#: config/tc-arm.c:8459 +msgid "'[' expected after PLI mnemonic" +msgstr "" + -+#: config/tc-arm.c:8401 config/tc-arm.c:11639 config/tc-arm.c:11671 -+#: config/tc-arm.c:11714 ++#: config/tc-arm.c:8550 config/tc-arm.c:11817 ++msgid "setend use is deprecated for ARMv8" ++msgstr "" ++ ++#: config/tc-arm.c:8571 config/tc-arm.c:11878 config/tc-arm.c:11910 ++#: config/tc-arm.c:11953 +msgid "extraneous shift as part of operand to shift insn" +msgstr "" + -+#: config/tc-arm.c:8482 ++#: config/tc-arm.c:8652 +msgid "SRS base register must be r13" +msgstr "" + -+#: config/tc-arm.c:8541 ++#: config/tc-arm.c:8711 +msgid "can only store two consecutive registers" +msgstr "" + -+#: config/tc-arm.c:8636 config/tc-arm.c:8653 ++#: config/tc-arm.c:8825 config/tc-arm.c:8842 +msgid "only two consecutive VFP SP registers allowed here" +msgstr "" + -+#: config/tc-arm.c:8681 config/tc-arm.c:8696 ++#: config/tc-arm.c:8870 config/tc-arm.c:8885 +msgid "this addressing mode requires base-register writeback" +msgstr "" + +#. If srcsize is 16, inst.operands[1].imm must be in the range 0-16. +#. i.e. immbits must be in range 0 - 16. -+#: config/tc-arm.c:8813 ++#: config/tc-arm.c:9002 +msgid "immediate value out of range, expected range [0, 16]" +msgstr "" + +#. If srcsize is 32, inst.operands[1].imm must be in the range 1-32. +#. i.e. immbits must be in range 0 - 31. -+#: config/tc-arm.c:8820 ++#: config/tc-arm.c:9009 +msgid "immediate value out of range, expected range [1, 32]" +msgstr "" + -+#: config/tc-arm.c:8886 ++#: config/tc-arm.c:9075 +msgid "this instruction does not support indexing" +msgstr "" + -+#: config/tc-arm.c:8909 ++#: config/tc-arm.c:9098 +msgid "only r15 allowed here" +msgstr "" + -+#: config/tc-arm.c:9044 ++#: config/tc-arm.c:9233 +msgid "immediate operand requires iWMMXt2" +msgstr "" + -+#: config/tc-arm.c:9188 ++#: config/tc-arm.c:9377 +msgid "shift by register not allowed in thumb mode" +msgstr "" + -+#: config/tc-arm.c:9200 config/tc-arm.c:11820 config/tc-arm.c:20800 ++#: config/tc-arm.c:9389 config/tc-arm.c:12061 config/tc-arm.c:21828 +msgid "shift expression is too large" +msgstr "" + -+#: config/tc-arm.c:9227 -+msgid "Instruction does not support =N addresses" -+msgstr "" -+ -+#: config/tc-arm.c:9233 ++#: config/tc-arm.c:9422 +msgid "cannot use register index with this instruction" +msgstr "" + -+#: config/tc-arm.c:9235 ++#: config/tc-arm.c:9424 +msgid "Thumb does not support negative register indexing" +msgstr "" + -+#: config/tc-arm.c:9237 ++#: config/tc-arm.c:9426 +msgid "Thumb does not support register post-indexing" +msgstr "" + -+#: config/tc-arm.c:9239 ++#: config/tc-arm.c:9428 +msgid "Thumb does not support register indexing with writeback" +msgstr "" + -+#: config/tc-arm.c:9241 ++#: config/tc-arm.c:9430 +msgid "Thumb supports only LSL in shifted register indexing" +msgstr "" + -+#: config/tc-arm.c:9250 config/tc-arm.c:14718 ++#: config/tc-arm.c:9439 config/tc-arm.c:15160 +msgid "shift out of range" +msgstr "" + -+#: config/tc-arm.c:9259 ++#: config/tc-arm.c:9448 +msgid "cannot use writeback with this instruction" +msgstr "" + -+#: config/tc-arm.c:9280 ++#: config/tc-arm.c:9469 +msgid "cannot use post-indexing with PC-relative addressing" +msgstr "" + -+#: config/tc-arm.c:9281 ++#: config/tc-arm.c:9470 +msgid "cannot use post-indexing with this instruction" +msgstr "" + -+#: config/tc-arm.c:9492 ++#: config/tc-arm.c:9683 +msgid "only SUBS PC, LR, #const allowed" +msgstr "" + -+#: config/tc-arm.c:9574 config/tc-arm.c:9729 config/tc-arm.c:9826 -+#: config/tc-arm.c:11075 config/tc-arm.c:11371 ++#: config/tc-arm.c:9765 config/tc-arm.c:9920 config/tc-arm.c:10017 ++#: config/tc-arm.c:11301 config/tc-arm.c:11607 +msgid "shift must be constant" +msgstr "" + -+#: config/tc-arm.c:9579 ++#: config/tc-arm.c:9770 +msgid "shift value over 3 not allowed in thumb mode" +msgstr "" + -+#: config/tc-arm.c:9581 ++#: config/tc-arm.c:9772 +msgid "only LSL shift allowed in thumb mode" +msgstr "" + -+#: config/tc-arm.c:9605 config/tc-arm.c:9744 config/tc-arm.c:9841 -+#: config/tc-arm.c:11088 ++#: config/tc-arm.c:9796 config/tc-arm.c:9935 config/tc-arm.c:10032 ++#: config/tc-arm.c:11314 +msgid "unshifted register required" +msgstr "" + -+#: config/tc-arm.c:9620 config/tc-arm.c:9852 config/tc-arm.c:11226 ++#: config/tc-arm.c:9811 config/tc-arm.c:10043 config/tc-arm.c:11462 +msgid "dest must overlap one source register" +msgstr "" + -+#: config/tc-arm.c:9747 ++#: config/tc-arm.c:9938 +msgid "dest and source1 must be the same register" +msgstr "" + -+#: config/tc-arm.c:10028 ++#: config/tc-arm.c:10207 +msgid "instruction is always unconditional" +msgstr "" + -+#: config/tc-arm.c:10130 ++#: config/tc-arm.c:10322 +msgid "selected processor does not support 'A' form of this instruction" +msgstr "" + -+#: config/tc-arm.c:10133 ++#: config/tc-arm.c:10325 +msgid "Thumb does not support the 2-argument form of this instruction" +msgstr "" + -+#: config/tc-arm.c:10241 ++#: config/tc-arm.c:10446 +msgid "SP not allowed in register list" +msgstr "" + -+#: config/tc-arm.c:10245 config/tc-arm.c:10351 ++#: config/tc-arm.c:10450 config/tc-arm.c:10556 +msgid "" +"having the base register in the register list when using write back is " +"UNPREDICTABLE" +msgstr "" + -+#: config/tc-arm.c:10253 ++#: config/tc-arm.c:10458 +msgid "LR and PC should not both be in register list" +msgstr "" + -+#: config/tc-arm.c:10261 ++#: config/tc-arm.c:10466 +msgid "PC not allowed in register list" +msgstr "" + -+#: config/tc-arm.c:10303 ++#: config/tc-arm.c:10508 +msgid "Thumb load/store multiple does not support {reglist}^" +msgstr "" + -+#: config/tc-arm.c:10328 config/tc-arm.c:10405 ++#: config/tc-arm.c:10533 config/tc-arm.c:10610 +#, c-format +msgid "value stored for r%d is UNKNOWN" +msgstr "" + -+#: config/tc-arm.c:10398 ++#: config/tc-arm.c:10603 +msgid "Thumb-2 instruction only valid in unified syntax" +msgstr "" + -+#: config/tc-arm.c:10402 config/tc-arm.c:10412 ++#: config/tc-arm.c:10607 config/tc-arm.c:10617 +msgid "this instruction will write back the base register" +msgstr "" + -+#: config/tc-arm.c:10415 ++#: config/tc-arm.c:10620 +msgid "this instruction will not write back the base register" +msgstr "" + -+#: config/tc-arm.c:10446 ++#: config/tc-arm.c:10651 +msgid "r14 not allowed as first register when second register is omitted" +msgstr "" + -+#: config/tc-arm.c:10546 ++#: config/tc-arm.c:10751 +msgid "" +"This instruction may be unpredictable if executed on M-profile cores with " +"interrupts enabled." +msgstr "" + -+#: config/tc-arm.c:10575 config/tc-arm.c:10588 config/tc-arm.c:10624 ++#: config/tc-arm.c:10780 config/tc-arm.c:10793 config/tc-arm.c:10829 +msgid "Thumb does not support this addressing mode" +msgstr "" + -+#: config/tc-arm.c:10592 ++#: config/tc-arm.c:10797 +msgid "byte or halfword not valid for base register" +msgstr "" + -+#: config/tc-arm.c:10595 ++#: config/tc-arm.c:10800 +msgid "r15 based store not allowed" +msgstr "" + -+#: config/tc-arm.c:10597 ++#: config/tc-arm.c:10802 +msgid "invalid base register for register offset" +msgstr "" + -+#: config/tc-arm.c:10779 ++#: config/tc-arm.c:10859 ++msgid "r12 not allowed here" ++msgstr "" ++ ++#: config/tc-arm.c:10865 ++msgid "base register written back, and overlaps one of transfer registers" ++msgstr "" ++ ++#: config/tc-arm.c:10993 +#, c-format +msgid "" +"Use of r%u as a source register is deprecated when r%u is the destination " +"register." +msgstr "" + -+#: config/tc-arm.c:10952 ++#: config/tc-arm.c:11177 +msgid "shifts in CMP/MOV instructions are only supported in unified syntax" +msgstr "" + -+#: config/tc-arm.c:10980 ++#: config/tc-arm.c:11205 +msgid "only lo regs allowed with immediate" +msgstr "" + -+#: config/tc-arm.c:11001 ++#: config/tc-arm.c:11226 +msgid ":upper16: not allowed this instruction" +msgstr "" + -+#: config/tc-arm.c:11149 ++#: config/tc-arm.c:11381 +msgid "Thumb encoding does not support an immediate here" +msgstr "" + -+#: config/tc-arm.c:11231 ++#: config/tc-arm.c:11467 +msgid "Thumb-2 MUL must not set flags" +msgstr "" + -+#: config/tc-arm.c:11296 ++#: config/tc-arm.c:11532 +msgid "Thumb does not support NOP with hints" +msgstr "" + -+#: config/tc-arm.c:11434 ++#: config/tc-arm.c:11670 +msgid "push/pop do not support {reglist}^" +msgstr "" + -+#: config/tc-arm.c:11457 ++#: config/tc-arm.c:11692 +msgid "invalid register list to push/pop instruction" +msgstr "" + -+#: config/tc-arm.c:11698 ++#: config/tc-arm.c:11937 +msgid "source1 and dest must be same register" +msgstr "" + -+#: config/tc-arm.c:11723 ++#: config/tc-arm.c:11962 +msgid "ror #imm not supported" +msgstr "" + -+#: config/tc-arm.c:11774 ++#: config/tc-arm.c:12013 +msgid "SMC is not permitted on this architecture" +msgstr "" + -+#: config/tc-arm.c:11937 ++#: config/tc-arm.c:12178 +msgid "Thumb encoding does not support rotation" +msgstr "" + -+#: config/tc-arm.c:11952 ++#: config/tc-arm.c:12193 +msgid "SVC is not permitted on this architecture" +msgstr "" + -+#: config/tc-arm.c:11968 ++#: config/tc-arm.c:12209 +msgid "instruction requires register index" +msgstr "" + -+#: config/tc-arm.c:11977 ++#: config/tc-arm.c:12218 +msgid "instruction does not allow shifted index" +msgstr "" + -+#: config/tc-arm.c:12122 ++#: config/tc-arm.c:12402 +msgid "invalid neon suffix for non neon instruction" +msgstr "" + -+#: config/tc-arm.c:12413 config/tc-arm.c:12748 ++#: config/tc-arm.c:12697 config/tc-arm.c:13034 config/tc-arm.c:14689 ++#: config/tc-arm.c:16082 +msgid "invalid instruction shape" +msgstr "" + -+#: config/tc-arm.c:12657 ++#: config/tc-arm.c:12942 +msgid "types specified in both the mnemonic and operands" +msgstr "" + -+#: config/tc-arm.c:12694 ++#: config/tc-arm.c:12979 +msgid "operand types can't be inferred" +msgstr "" + -+#: config/tc-arm.c:12700 ++#: config/tc-arm.c:12985 +msgid "type specifier has the wrong number of parts" +msgstr "" + -+#: config/tc-arm.c:12764 config/tc-arm.c:14459 config/tc-arm.c:14466 ++#: config/tc-arm.c:13050 config/tc-arm.c:14829 config/tc-arm.c:14836 +msgid "operand size must match register width" +msgstr "" + -+#: config/tc-arm.c:12775 ++#: config/tc-arm.c:13061 +msgid "bad type in Neon instruction" +msgstr "" + -+#: config/tc-arm.c:12786 ++#: config/tc-arm.c:13072 +msgid "inconsistent types in Neon instruction" +msgstr "" + -+#: config/tc-arm.c:13603 ++#: config/tc-arm.c:13889 +msgid "first and second operands shall be the same register" +msgstr "" + -+#: config/tc-arm.c:13871 ++#: config/tc-arm.c:14165 +msgid "scalar out of range for multiply instruction" +msgstr "" + -+#: config/tc-arm.c:14047 config/tc-arm.c:14059 ++#: config/tc-arm.c:14341 config/tc-arm.c:14353 +msgid "immediate out of range for insert" +msgstr "" + -+#: config/tc-arm.c:14071 config/tc-arm.c:15066 ++#: config/tc-arm.c:14365 config/tc-arm.c:15533 +msgid "immediate out of range for shift" +msgstr "" + -+#: config/tc-arm.c:14128 config/tc-arm.c:14155 config/tc-arm.c:14564 -+#: config/tc-arm.c:15012 -+msgid "immediate out of range" -+msgstr "" -+ -+#: config/tc-arm.c:14192 ++#: config/tc-arm.c:14486 +msgid "immediate out of range for narrowing operation" +msgstr "" + -+#: config/tc-arm.c:14317 ++#: config/tc-arm.c:14620 +msgid "operands 0 and 1 must be the same register" +msgstr "" + -+#: config/tc-arm.c:14538 ++#: config/tc-arm.c:14699 config/tc-arm.c:16165 ++msgid "invalid rounding mode" ++msgstr "" ++ ++#: config/tc-arm.c:14967 +msgid "operand size must be specified for immediate VMOV" +msgstr "" + -+#: config/tc-arm.c:14548 ++#: config/tc-arm.c:14977 +msgid "immediate has bits set outside the operand size" +msgstr "" + -+#: config/tc-arm.c:14744 ++#: config/tc-arm.c:15142 ++msgid "Instruction form not available on this architecture." ++msgstr "" ++ ++#: config/tc-arm.c:15186 +msgid "elements must be smaller than reversal region" +msgstr "" + -+#: config/tc-arm.c:14915 config/tc-arm.c:14965 ++#: config/tc-arm.c:15367 config/tc-arm.c:15427 +msgid "bad type for scalar" +msgstr "" + -+#: config/tc-arm.c:15029 config/tc-arm.c:15037 ++#: config/tc-arm.c:15491 config/tc-arm.c:15499 +msgid "VFP registers must be adjacent" +msgstr "" + -+#: config/tc-arm.c:15178 ++#: config/tc-arm.c:15645 +msgid "bad list length for table lookup" +msgstr "" + -+#: config/tc-arm.c:15208 ++#: config/tc-arm.c:15675 +msgid "writeback (!) must be used for VLDMDB and VSTMDB" +msgstr "" + -+#: config/tc-arm.c:15211 ++#: config/tc-arm.c:15678 +msgid "register list must contain at least 1 and at most 16 registers" +msgstr "" + -+#: config/tc-arm.c:15236 -+msgid "Use of PC here is deprecated" -+msgstr "" -+ -+#: config/tc-arm.c:15238 ++#: config/tc-arm.c:15703 +msgid "Use of PC here is UNPREDICTABLE" +msgstr "" + -+#: config/tc-arm.c:15301 ++#: config/tc-arm.c:15705 ++msgid "Use of PC here is deprecated" ++msgstr "" ++ ++#: config/tc-arm.c:15768 +msgid "bad alignment" +msgstr "" + -+#: config/tc-arm.c:15318 ++#: config/tc-arm.c:15785 +msgid "bad list type for instruction" +msgstr "" + -+#: config/tc-arm.c:15360 ++#: config/tc-arm.c:15787 ++msgid "bad element type for instruction" ++msgstr "" ++ ++#: config/tc-arm.c:15829 +msgid "unsupported alignment for instruction" +msgstr "" + -+#: config/tc-arm.c:15379 config/tc-arm.c:15473 config/tc-arm.c:15484 -+#: config/tc-arm.c:15494 config/tc-arm.c:15508 ++#: config/tc-arm.c:15848 config/tc-arm.c:15942 config/tc-arm.c:15953 ++#: config/tc-arm.c:15963 config/tc-arm.c:15977 +msgid "bad list length" +msgstr "" + -+#: config/tc-arm.c:15384 ++#: config/tc-arm.c:15853 +msgid "stride of 2 unavailable when element size is 8" +msgstr "" + -+#: config/tc-arm.c:15417 config/tc-arm.c:15492 ++#: config/tc-arm.c:15886 config/tc-arm.c:15961 +msgid "can't use alignment with this instruction" +msgstr "" + -+#: config/tc-arm.c:15559 ++#: config/tc-arm.c:16033 +msgid "post-index must be a register" +msgstr "" + -+#: config/tc-arm.c:15561 ++#: config/tc-arm.c:16035 +msgid "bad register for post-index" +msgstr "" + -+#: config/tc-arm.c:15897 config/tc-arm.c:15983 ++#: config/tc-arm.c:16720 config/tc-arm.c:16806 +msgid "conditional infixes are deprecated in unified syntax" +msgstr "" + -+#: config/tc-arm.c:16131 ++#: config/tc-arm.c:16957 +msgid "Warning: conditional outside an IT block for Thumb." +msgstr "" + -+#: config/tc-arm.c:16336 ++#: config/tc-arm.c:17109 ++msgid "Short branches, Undefined, SVC, LDM/STM" ++msgstr "" ++ ++#: config/tc-arm.c:17110 ++msgid "Miscellaneous 16-bit instructions" ++msgstr "" ++ ++#: config/tc-arm.c:17111 ++msgid "ADR" ++msgstr "" ++ ++#: config/tc-arm.c:17112 ++msgid "Literal loads" ++msgstr "" ++ ++#: config/tc-arm.c:17113 ++msgid "Hi-register ADD, MOV, CMP, BX, BLX using pc" ++msgstr "" ++ ++#: config/tc-arm.c:17114 ++msgid "Hi-register ADD, MOV, CMP using pc" ++msgstr "" ++ ++#: config/tc-arm.c:17133 ++msgid "IT blocks containing 32-bit Thumb instructions are deprecated in ARMv8" ++msgstr "" ++ ++#: config/tc-arm.c:17145 ++#, c-format ++msgid "" ++"IT blocks containing 16-bit Thumb instructions of the following class are " ++"deprecated in ARMv8: %s" ++msgstr "" ++ ++#: config/tc-arm.c:17158 ++msgid "" ++"IT blocks containing more than one conditional instruction are deprecated in " ++"ARMv8" ++msgstr "" ++ ++#: config/tc-arm.c:17222 +msgid "s suffix on comparison instruction is deprecated" +msgstr "" + -+#: config/tc-arm.c:16355 ++#: config/tc-arm.c:17241 +#, c-format +msgid "selected processor does not support Thumb mode `%s'" +msgstr "" + -+#: config/tc-arm.c:16361 ++#: config/tc-arm.c:17247 +msgid "Thumb does not support conditional execution" +msgstr "" + -+#: config/tc-arm.c:16380 ++#: config/tc-arm.c:17266 +#, c-format +msgid "selected processor does not support Thumb-2 mode `%s'" +msgstr "" + -+#: config/tc-arm.c:16405 ++#: config/tc-arm.c:17291 +#, c-format +msgid "cannot honor width suffix -- `%s'" +msgstr "" + -+#: config/tc-arm.c:16446 ++#: config/tc-arm.c:17332 +#, c-format +msgid "selected processor does not support ARM mode `%s'" +msgstr "" + -+#: config/tc-arm.c:16451 ++#: config/tc-arm.c:17337 +#, c-format +msgid "width suffixes are invalid in ARM mode -- `%s'" +msgstr "" + -+#: config/tc-arm.c:16484 ++#: config/tc-arm.c:17370 +#, c-format +msgid "attempt to use an ARM instruction on a Thumb-only processor -- `%s'" +msgstr "" + -+#: config/tc-arm.c:16501 ++#: config/tc-arm.c:17387 +#, c-format +msgid "section '%s' finished with an open IT block." +msgstr "" + -+#: config/tc-arm.c:16506 ++#: config/tc-arm.c:17392 +msgid "file finished with an open IT block." +msgstr "" + -+#: config/tc-arm.c:19545 ++#: config/tc-arm.c:20557 +#, c-format +msgid "alignments greater than %d bytes not supported in .text sections." +msgstr "" + -+#: config/tc-arm.c:19813 config/tc-ia64.c:3469 ++#: config/tc-arm.c:20825 config/tc-ia64.c:3612 +#, c-format +msgid "Group section `%s' has no group signature" +msgstr "" + -+#: config/tc-arm.c:19858 ++#: config/tc-arm.c:20870 +msgid "handlerdata in cantunwind frame" +msgstr "" + -+#: config/tc-arm.c:19875 ++#: config/tc-arm.c:20887 +msgid "too many unwind opcodes for personality routine 0" +msgstr "" + -+#: config/tc-arm.c:19907 ++#: config/tc-arm.c:20923 +msgid "too many unwind opcodes" +msgstr "" + -+#: config/tc-arm.c:20167 -+msgid "GOT already in the symbol table" -+msgstr "" -+ -+#: config/tc-arm.c:20505 config/tc-arm.c:20547 config/tc-arm.c:20827 -+#, c-format -+msgid "undefined symbol %s used as an immediate value" -+msgstr "" -+ -+#: config/tc-arm.c:20507 config/tc-arm.c:20549 ++#: config/tc-arm.c:21525 config/tc-arm.c:21576 +#, c-format +msgid "symbol %s is in a different section" +msgstr "" + -+#: config/tc-arm.c:20509 config/tc-arm.c:20551 ++#: config/tc-arm.c:21527 config/tc-arm.c:21578 +#, c-format +msgid "symbol %s is weak and may be overridden later" +msgstr "" + -+#: config/tc-arm.c:20528 config/tc-arm.c:20869 ++#: config/tc-arm.c:21555 config/tc-arm.c:21897 +#, c-format +msgid "invalid constant (%lx) after fixup" +msgstr "" + -+#: config/tc-arm.c:20584 ++#: config/tc-arm.c:21611 +#, c-format +msgid "unable to compute ADRL instructions for PC offset of 0x%lx" +msgstr "" + -+#: config/tc-arm.c:20619 config/tc-arm.c:20649 ++#: config/tc-arm.c:21646 config/tc-arm.c:21676 +msgid "invalid literal constant: pool needs to be closer" +msgstr "" + -+#: config/tc-arm.c:20622 config/tc-arm.c:20670 ++#: config/tc-arm.c:21649 config/tc-arm.c:21698 +#, c-format +msgid "bad immediate value for offset (%ld)" +msgstr "" + -+#: config/tc-arm.c:20651 ++#: config/tc-arm.c:21679 +#, c-format +msgid "bad immediate value for 8-bit offset (%ld)" +msgstr "" + -+#: config/tc-arm.c:20711 ++#: config/tc-arm.c:21739 +msgid "offset not a multiple of 4" +msgstr "" + -+#: config/tc-arm.c:20718 config/tc-arm.c:20733 config/tc-arm.c:20748 -+#: config/tc-arm.c:20759 config/tc-arm.c:20782 config/tc-arm.c:21494 -+#: config/tc-moxie.c:662 config/tc-pj.c:448 config/tc-sh.c:4281 -+msgid "offset out of range" -+msgstr "" -+ -+#: config/tc-arm.c:20885 ++#: config/tc-arm.c:21913 +msgid "invalid smc expression" +msgstr "" + -+#: config/tc-arm.c:20894 ++#: config/tc-arm.c:21922 +msgid "invalid hvc expression" +msgstr "" + -+#: config/tc-arm.c:20905 config/tc-arm.c:20914 ++#: config/tc-arm.c:21933 config/tc-arm.c:21942 +msgid "invalid swi expression" +msgstr "" + -+#: config/tc-arm.c:20924 ++#: config/tc-arm.c:21952 +msgid "invalid expression in load/store multiple" +msgstr "" + -+#: config/tc-arm.c:20985 ++#: config/tc-arm.c:22013 +#, c-format +msgid "blx to '%s' an ARM ISA state function changed to bl" +msgstr "" + -+#: config/tc-arm.c:21004 ++#: config/tc-arm.c:22032 +msgid "misaligned branch destination" +msgstr "" + -+#: config/tc-arm.c:21090 -+msgid "conditional branch out of range" -+msgstr "" -+ -+#: config/tc-arm.c:21124 ++#: config/tc-arm.c:22152 +#, c-format +msgid "blx to Thumb func '%s' from Thumb ISA state changed to bl" +msgstr "" + -+#: config/tc-arm.c:21174 ++#: config/tc-arm.c:22202 +msgid "Thumb2 branch out of range" +msgstr "" + -+#: config/tc-arm.c:21263 ++#: config/tc-arm.c:22291 +msgid "rel31 relocation overflow" +msgstr "" + -+#: config/tc-arm.c:21275 config/tc-arm.c:21303 ++#: config/tc-arm.c:22303 config/tc-arm.c:22331 +msgid "co-processor offset out of range" +msgstr "" + -+#: config/tc-arm.c:21320 ++#: config/tc-arm.c:22348 +#, c-format +msgid "invalid offset, target not word aligned (0x%08lX)" +msgstr "" + -+#: config/tc-arm.c:21327 config/tc-arm.c:21336 config/tc-arm.c:21344 -+#: config/tc-arm.c:21352 config/tc-arm.c:21360 ++#: config/tc-arm.c:22355 config/tc-arm.c:22364 config/tc-arm.c:22372 ++#: config/tc-arm.c:22380 config/tc-arm.c:22388 +#, c-format +msgid "invalid offset, value too big (0x%08lX)" +msgstr "" + -+#: config/tc-arm.c:21401 ++#: config/tc-arm.c:22429 +msgid "invalid Hi register with immediate" +msgstr "" + -+#: config/tc-arm.c:21417 ++#: config/tc-arm.c:22445 +msgid "invalid immediate for stack address calculation" +msgstr "" + -+#: config/tc-arm.c:21425 ++#: config/tc-arm.c:22453 +#, c-format +msgid "invalid immediate for address calculation (value = 0x%08lX)" +msgstr "" + -+#: config/tc-arm.c:21455 ++#: config/tc-arm.c:22483 +#, c-format +msgid "invalid immediate: %ld is out of range" +msgstr "" + -+#: config/tc-arm.c:21467 ++#: config/tc-arm.c:22495 +#, c-format +msgid "invalid shift value: %ld" +msgstr "" + -+#: config/tc-arm.c:21546 ++#: config/tc-arm.c:22574 +#, c-format +msgid "the offset 0x%08lX is not representable" +msgstr "" + -+#: config/tc-arm.c:21586 ++#: config/tc-arm.c:22614 +#, c-format +msgid "bad offset 0x%08lX (only 12 bits available for the magnitude)" +msgstr "" + -+#: config/tc-arm.c:21625 ++#: config/tc-arm.c:22653 +#, c-format +msgid "bad offset 0x%08lX (only 8 bits available for the magnitude)" +msgstr "" + -+#: config/tc-arm.c:21665 ++#: config/tc-arm.c:22693 +#, c-format +msgid "bad offset 0x%08lX (must be word-aligned)" +msgstr "" + -+#: config/tc-arm.c:21670 ++#: config/tc-arm.c:22698 +#, c-format +msgid "bad offset 0x%08lX (must be an 8-bit number of words)" +msgstr "" + -+#: config/tc-arm.c:21701 config/tc-score.c:7392 ++#: config/tc-arm.c:22729 config/tc-score.c:7392 +#, c-format +msgid "bad relocation fixup type (%d)" +msgstr "" + -+#: config/tc-arm.c:21812 ++#: config/tc-arm.c:22840 +msgid "literal referenced across section boundary" +msgstr "" + -+#: config/tc-arm.c:21879 ++#: config/tc-arm.c:22907 +msgid "internal relocation (type: IMMEDIATE) not fixed up" +msgstr "" + -+#: config/tc-arm.c:21884 ++#: config/tc-arm.c:22912 +msgid "ADRL used for a symbol not defined in the same file" +msgstr "" + -+#: config/tc-arm.c:21899 ++#: config/tc-arm.c:22927 +#, c-format +msgid "undefined local label `%s'" +msgstr "" + -+#: config/tc-arm.c:21905 ++#: config/tc-arm.c:22933 +msgid "internal_relocation (type: OFFSET_IMM) not fixed up" +msgstr "" + -+#: config/tc-arm.c:21927 config/tc-cris.c:3986 config/tc-mcore.c:1926 -+#: config/tc-microblaze.c:1833 config/tc-mmix.c:2867 config/tc-moxie.c:757 ++#: config/tc-arm.c:22955 config/tc-cris.c:3986 config/tc-mcore.c:1926 ++#: config/tc-microblaze.c:1965 config/tc-mmix.c:2893 config/tc-moxie.c:820 +#: config/tc-ns32k.c:2248 config/tc-score.c:7478 +msgid "" +msgstr "" + -+#: config/tc-arm.c:21930 config/tc-arm.c:21951 config/tc-score.c:7480 -+#, c-format -+msgid "cannot represent %s relocation in this object file format" -+msgstr "" -+ -+#: config/tc-arm.c:22307 ++#: config/tc-arm.c:23339 +#, c-format +msgid "%s: unexpected function type: %d" +msgstr "" + -+#: config/tc-arm.c:22436 ++#: config/tc-arm.c:23476 +msgid "use of old and new-style options to set CPU type" +msgstr "" + -+#: config/tc-arm.c:22446 ++#: config/tc-arm.c:23486 +msgid "use of old and new-style options to set FPU type" +msgstr "" + -+#: config/tc-arm.c:22522 ++#: config/tc-arm.c:23562 +msgid "hard-float conflicts with specified fpu" +msgstr "" + -+#: config/tc-arm.c:22709 ++#: config/tc-arm.c:23749 +msgid "generate PIC code" +msgstr "" + -+#: config/tc-arm.c:22710 ++#: config/tc-arm.c:23750 +msgid "assemble Thumb code" +msgstr "" + -+#: config/tc-arm.c:22711 ++#: config/tc-arm.c:23751 +msgid "support ARM/Thumb interworking" +msgstr "" + -+#: config/tc-arm.c:22713 ++#: config/tc-arm.c:23753 +msgid "code uses 32-bit program counter" +msgstr "" + -+#: config/tc-arm.c:22714 ++#: config/tc-arm.c:23754 +msgid "code uses 26-bit program counter" +msgstr "" + -+#: config/tc-arm.c:22715 ++#: config/tc-arm.c:23755 +msgid "floating point args are in fp regs" +msgstr "" + -+#: config/tc-arm.c:22717 ++#: config/tc-arm.c:23757 +msgid "re-entrant code" +msgstr "" + -+#: config/tc-arm.c:22718 ++#: config/tc-arm.c:23758 +msgid "code is ATPCS conformant" +msgstr "" + -+#: config/tc-arm.c:22719 -+msgid "assemble for big-endian" -+msgstr "" -+ -+#: config/tc-arm.c:22720 -+msgid "assemble for little-endian" -+msgstr "" -+ +#. These are recognized by the assembler, but have no affect on code. -+#: config/tc-arm.c:22724 ++#: config/tc-arm.c:23764 +msgid "use frame pointer" +msgstr "" + -+#: config/tc-arm.c:22725 ++#: config/tc-arm.c:23765 +msgid "use stack size checking" +msgstr "" + -+#: config/tc-arm.c:22728 ++#: config/tc-arm.c:23768 +msgid "do not warn on use of deprecated feature" +msgstr "" + +#. DON'T add any new processors to this list -- we want the whole list +#. to go away... Add them to the processors table instead. -+#: config/tc-arm.c:22745 config/tc-arm.c:22746 ++#: config/tc-arm.c:23785 config/tc-arm.c:23786 +msgid "use -mcpu=arm1" +msgstr "" + -+#: config/tc-arm.c:22747 config/tc-arm.c:22748 ++#: config/tc-arm.c:23787 config/tc-arm.c:23788 +msgid "use -mcpu=arm2" +msgstr "" + -+#: config/tc-arm.c:22749 config/tc-arm.c:22750 ++#: config/tc-arm.c:23789 config/tc-arm.c:23790 +msgid "use -mcpu=arm250" +msgstr "" + -+#: config/tc-arm.c:22751 config/tc-arm.c:22752 ++#: config/tc-arm.c:23791 config/tc-arm.c:23792 +msgid "use -mcpu=arm3" +msgstr "" + -+#: config/tc-arm.c:22753 config/tc-arm.c:22754 ++#: config/tc-arm.c:23793 config/tc-arm.c:23794 +msgid "use -mcpu=arm6" +msgstr "" + -+#: config/tc-arm.c:22755 config/tc-arm.c:22756 ++#: config/tc-arm.c:23795 config/tc-arm.c:23796 +msgid "use -mcpu=arm600" +msgstr "" + -+#: config/tc-arm.c:22757 config/tc-arm.c:22758 ++#: config/tc-arm.c:23797 config/tc-arm.c:23798 +msgid "use -mcpu=arm610" +msgstr "" + -+#: config/tc-arm.c:22759 config/tc-arm.c:22760 ++#: config/tc-arm.c:23799 config/tc-arm.c:23800 +msgid "use -mcpu=arm620" +msgstr "" + -+#: config/tc-arm.c:22761 config/tc-arm.c:22762 ++#: config/tc-arm.c:23801 config/tc-arm.c:23802 +msgid "use -mcpu=arm7" +msgstr "" + -+#: config/tc-arm.c:22763 config/tc-arm.c:22764 ++#: config/tc-arm.c:23803 config/tc-arm.c:23804 +msgid "use -mcpu=arm70" +msgstr "" + -+#: config/tc-arm.c:22765 config/tc-arm.c:22766 ++#: config/tc-arm.c:23805 config/tc-arm.c:23806 +msgid "use -mcpu=arm700" +msgstr "" + -+#: config/tc-arm.c:22767 config/tc-arm.c:22768 ++#: config/tc-arm.c:23807 config/tc-arm.c:23808 +msgid "use -mcpu=arm700i" +msgstr "" + -+#: config/tc-arm.c:22769 config/tc-arm.c:22770 ++#: config/tc-arm.c:23809 config/tc-arm.c:23810 +msgid "use -mcpu=arm710" +msgstr "" + -+#: config/tc-arm.c:22771 config/tc-arm.c:22772 ++#: config/tc-arm.c:23811 config/tc-arm.c:23812 +msgid "use -mcpu=arm710c" +msgstr "" + -+#: config/tc-arm.c:22773 config/tc-arm.c:22774 ++#: config/tc-arm.c:23813 config/tc-arm.c:23814 +msgid "use -mcpu=arm720" +msgstr "" + -+#: config/tc-arm.c:22775 config/tc-arm.c:22776 ++#: config/tc-arm.c:23815 config/tc-arm.c:23816 +msgid "use -mcpu=arm7d" +msgstr "" + -+#: config/tc-arm.c:22777 config/tc-arm.c:22778 ++#: config/tc-arm.c:23817 config/tc-arm.c:23818 +msgid "use -mcpu=arm7di" +msgstr "" + -+#: config/tc-arm.c:22779 config/tc-arm.c:22780 ++#: config/tc-arm.c:23819 config/tc-arm.c:23820 +msgid "use -mcpu=arm7m" +msgstr "" + -+#: config/tc-arm.c:22781 config/tc-arm.c:22782 ++#: config/tc-arm.c:23821 config/tc-arm.c:23822 +msgid "use -mcpu=arm7dm" +msgstr "" + -+#: config/tc-arm.c:22783 config/tc-arm.c:22784 ++#: config/tc-arm.c:23823 config/tc-arm.c:23824 +msgid "use -mcpu=arm7dmi" +msgstr "" + -+#: config/tc-arm.c:22785 config/tc-arm.c:22786 ++#: config/tc-arm.c:23825 config/tc-arm.c:23826 +msgid "use -mcpu=arm7100" +msgstr "" + -+#: config/tc-arm.c:22787 config/tc-arm.c:22788 ++#: config/tc-arm.c:23827 config/tc-arm.c:23828 +msgid "use -mcpu=arm7500" +msgstr "" + -+#: config/tc-arm.c:22789 config/tc-arm.c:22790 ++#: config/tc-arm.c:23829 config/tc-arm.c:23830 +msgid "use -mcpu=arm7500fe" +msgstr "" + -+#: config/tc-arm.c:22791 config/tc-arm.c:22792 config/tc-arm.c:22793 -+#: config/tc-arm.c:22794 ++#: config/tc-arm.c:23831 config/tc-arm.c:23832 config/tc-arm.c:23833 ++#: config/tc-arm.c:23834 +msgid "use -mcpu=arm7tdmi" +msgstr "" + -+#: config/tc-arm.c:22795 config/tc-arm.c:22796 ++#: config/tc-arm.c:23835 config/tc-arm.c:23836 +msgid "use -mcpu=arm710t" +msgstr "" + -+#: config/tc-arm.c:22797 config/tc-arm.c:22798 ++#: config/tc-arm.c:23837 config/tc-arm.c:23838 +msgid "use -mcpu=arm720t" +msgstr "" + -+#: config/tc-arm.c:22799 config/tc-arm.c:22800 ++#: config/tc-arm.c:23839 config/tc-arm.c:23840 +msgid "use -mcpu=arm740t" +msgstr "" + -+#: config/tc-arm.c:22801 config/tc-arm.c:22802 ++#: config/tc-arm.c:23841 config/tc-arm.c:23842 +msgid "use -mcpu=arm8" +msgstr "" + -+#: config/tc-arm.c:22803 config/tc-arm.c:22804 ++#: config/tc-arm.c:23843 config/tc-arm.c:23844 +msgid "use -mcpu=arm810" +msgstr "" + -+#: config/tc-arm.c:22805 config/tc-arm.c:22806 ++#: config/tc-arm.c:23845 config/tc-arm.c:23846 +msgid "use -mcpu=arm9" +msgstr "" + -+#: config/tc-arm.c:22807 config/tc-arm.c:22808 ++#: config/tc-arm.c:23847 config/tc-arm.c:23848 +msgid "use -mcpu=arm9tdmi" +msgstr "" + -+#: config/tc-arm.c:22809 config/tc-arm.c:22810 ++#: config/tc-arm.c:23849 config/tc-arm.c:23850 +msgid "use -mcpu=arm920" +msgstr "" + -+#: config/tc-arm.c:22811 config/tc-arm.c:22812 ++#: config/tc-arm.c:23851 config/tc-arm.c:23852 +msgid "use -mcpu=arm940" +msgstr "" + -+#: config/tc-arm.c:22813 ++#: config/tc-arm.c:23853 +msgid "use -mcpu=strongarm" +msgstr "" + -+#: config/tc-arm.c:22815 ++#: config/tc-arm.c:23855 +msgid "use -mcpu=strongarm110" +msgstr "" + -+#: config/tc-arm.c:22817 ++#: config/tc-arm.c:23857 +msgid "use -mcpu=strongarm1100" +msgstr "" + -+#: config/tc-arm.c:22819 ++#: config/tc-arm.c:23859 +msgid "use -mcpu=strongarm1110" +msgstr "" + -+#: config/tc-arm.c:22820 ++#: config/tc-arm.c:23860 +msgid "use -mcpu=xscale" +msgstr "" + -+#: config/tc-arm.c:22821 ++#: config/tc-arm.c:23861 +msgid "use -mcpu=iwmmxt" +msgstr "" + -+#: config/tc-arm.c:22822 ++#: config/tc-arm.c:23862 +msgid "use -mcpu=all" +msgstr "" + +#. Architecture variants -- don't add any more to this list either. -+#: config/tc-arm.c:22825 config/tc-arm.c:22826 ++#: config/tc-arm.c:23865 config/tc-arm.c:23866 +msgid "use -march=armv2" +msgstr "" + -+#: config/tc-arm.c:22827 config/tc-arm.c:22828 ++#: config/tc-arm.c:23867 config/tc-arm.c:23868 +msgid "use -march=armv2a" +msgstr "" + -+#: config/tc-arm.c:22829 config/tc-arm.c:22830 ++#: config/tc-arm.c:23869 config/tc-arm.c:23870 +msgid "use -march=armv3" +msgstr "" + -+#: config/tc-arm.c:22831 config/tc-arm.c:22832 ++#: config/tc-arm.c:23871 config/tc-arm.c:23872 +msgid "use -march=armv3m" +msgstr "" + -+#: config/tc-arm.c:22833 config/tc-arm.c:22834 ++#: config/tc-arm.c:23873 config/tc-arm.c:23874 +msgid "use -march=armv4" +msgstr "" + -+#: config/tc-arm.c:22835 config/tc-arm.c:22836 ++#: config/tc-arm.c:23875 config/tc-arm.c:23876 +msgid "use -march=armv4t" +msgstr "" + -+#: config/tc-arm.c:22837 config/tc-arm.c:22838 ++#: config/tc-arm.c:23877 config/tc-arm.c:23878 +msgid "use -march=armv5" +msgstr "" + -+#: config/tc-arm.c:22839 config/tc-arm.c:22840 ++#: config/tc-arm.c:23879 config/tc-arm.c:23880 +msgid "use -march=armv5t" +msgstr "" + -+#: config/tc-arm.c:22841 config/tc-arm.c:22842 ++#: config/tc-arm.c:23881 config/tc-arm.c:23882 +msgid "use -march=armv5te" +msgstr "" + +#. Floating point variants -- don't add any more to this list either. -+#: config/tc-arm.c:22845 ++#: config/tc-arm.c:23885 +msgid "use -mfpu=fpe" +msgstr "" + -+#: config/tc-arm.c:22846 ++#: config/tc-arm.c:23886 +msgid "use -mfpu=fpa10" +msgstr "" + -+#: config/tc-arm.c:22847 ++#: config/tc-arm.c:23887 +msgid "use -mfpu=fpa11" +msgstr "" + -+#: config/tc-arm.c:22849 ++#: config/tc-arm.c:23889 +msgid "use either -mfpu=softfpa or -mfpu=softvfp" +msgstr "" + -+#: config/tc-arm.c:23178 -+msgid "invalid architectural extension" -+msgstr "" -+ -+#: config/tc-arm.c:23211 -+msgid "must specify extensions to add before specifying those to remove" -+msgstr "" -+ -+#: config/tc-arm.c:23219 -+msgid "missing architectural extension" -+msgstr "" -+ -+#: config/tc-arm.c:23234 ++#: config/tc-arm.c:24315 +msgid "extension does not apply to the base architecture" +msgstr "" + -+#: config/tc-arm.c:23257 -+#, c-format -+msgid "unknown architectural extension `%s'" -+msgstr "" -+ -+#: config/tc-arm.c:23259 ++#: config/tc-arm.c:24340 +msgid "architectural extensions must be specified in alphabetical order" +msgstr "" + -+#: config/tc-arm.c:23291 -+#, c-format -+msgid "missing cpu name `%s'" -+msgstr "" -+ -+#: config/tc-arm.c:23317 config/tc-arm.c:23813 -+#, c-format -+msgid "unknown cpu `%s'" -+msgstr "" -+ -+#: config/tc-arm.c:23335 -+#, c-format -+msgid "missing architecture name `%s'" -+msgstr "" -+ -+#: config/tc-arm.c:23352 config/tc-arm.c:23847 config/tc-arm.c:23878 -+#: config/tc-arm.c:23929 config/tc-score.c:7715 -+#, c-format -+msgid "unknown architecture `%s'\n" -+msgstr "" -+ -+#: config/tc-arm.c:23368 config/tc-arm.c:23960 ++#: config/tc-arm.c:24449 config/tc-arm.c:25086 +#, c-format +msgid "unknown floating point format `%s'\n" +msgstr "" + -+#: config/tc-arm.c:23384 ++#: config/tc-arm.c:24465 +#, c-format +msgid "unknown floating point abi `%s'\n" +msgstr "" + -+#: config/tc-arm.c:23400 ++#: config/tc-arm.c:24481 +#, c-format +msgid "unknown EABI `%s'\n" +msgstr "" + -+#: config/tc-arm.c:23420 ++#: config/tc-arm.c:24501 +#, c-format +msgid "unknown implicit IT mode `%s', should be arm, thumb, always, or never." +msgstr "" + -+#: config/tc-arm.c:23430 -+msgid "\t assemble for CPU " -+msgstr "" -+ -+#: config/tc-arm.c:23432 -+msgid "\t assemble for architecture " -+msgstr "" -+ -+#: config/tc-arm.c:23434 ++#: config/tc-arm.c:24515 config/tc-metag.c:5912 +msgid "\t assemble for FPU architecture " +msgstr "" + -+#: config/tc-arm.c:23436 ++#: config/tc-arm.c:24517 +msgid "\t assemble for floating point ABI " +msgstr "" + -+#: config/tc-arm.c:23439 ++#: config/tc-arm.c:24520 +msgid "\t\t assemble for eabi version " +msgstr "" + -+#: config/tc-arm.c:23442 ++#: config/tc-arm.c:24523 +msgid "\t controls implicit insertion of IT instructions" +msgstr "" + -+#: config/tc-arm.c:23486 config/tc-arm.c:23504 config/tc-arm.c:23524 -+#, c-format -+msgid "option `-%c%s' is deprecated: %s" -+msgstr "" -+ -+#: config/tc-arm.c:23544 ++#: config/tc-arm.c:24625 +#, c-format +msgid " ARM-specific assembler options:\n" +msgstr "" + -+#: config/tc-arm.c:23555 -+#, c-format -+msgid " -EB assemble code for a big-endian cpu\n" -+msgstr "" -+ -+#: config/tc-arm.c:23560 -+#, c-format -+msgid " -EL assemble code for a little-endian cpu\n" -+msgstr "" -+ -+#: config/tc-arm.c:23564 ++#: config/tc-arm.c:24645 +#, c-format +msgid " --fix-v4bx Allow BX in ARMv4 code\n" +msgstr "" + -+#: config/tc-arm.c:23911 ++#: config/tc-arm.c:25037 +#, c-format +msgid "" +"architectural extension `%s' is not allowed for the current base architecture" +msgstr "" + -+#: config/tc-avr.c:373 ++#: config/tc-arm.c:25055 ++#, c-format ++msgid "unknown architecture extension `%s'\n" ++msgstr "" ++ ++#: config/tc-avr.c:379 +#, c-format +msgid "Known MCU names:" +msgstr "" + -+#: config/tc-avr.c:438 ++#: config/tc-avr.c:444 +#, c-format +msgid "" +"AVR Assembler options:\n" @@ -829523,6 +834424,7 @@ index 0000000..f1eec3b +" avr5 - enhanced AVR core with up to 64K program memory\n" +" avr51 - enhanced AVR core with up to 128K program memory\n" +" avr6 - enhanced AVR core with up to 256K program memory\n" ++" avrxmega2 - XMEGA, > 8K, < 64K FLASH, < 64K RAM\n" +" avrxmega3 - XMEGA, > 8K, <= 64K FLASH, > 64K RAM\n" +" avrxmega4 - XMEGA, > 64K, <= 128K FLASH, <= 64K RAM\n" +" avrxmega5 - XMEGA, > 64K, <= 128K FLASH, > 64K RAM\n" @@ -829531,7 +834433,7 @@ index 0000000..f1eec3b +" or immediate microcontroller name.\n" +msgstr "" + -+#: config/tc-avr.c:460 ++#: config/tc-avr.c:467 +#, c-format +msgid "" +" -mall-opcodes accept all AVR opcodes, even if not supported by MCU\n" @@ -829541,153 +834443,153 @@ index 0000000..f1eec3b +" (default for avr3, avr5)\n" +msgstr "" + -+#: config/tc-avr.c:504 config/tc-msp430.c:743 ++#: config/tc-avr.c:511 +#, c-format +msgid "unknown MCU: %s\n" +msgstr "" + -+#: config/tc-avr.c:513 ++#: config/tc-avr.c:520 +#, c-format +msgid "redefinition of mcu type `%s' to `%s'" +msgstr "" + -+#: config/tc-avr.c:591 ++#: config/tc-avr.c:598 +msgid "constant value required" +msgstr "" + -+#: config/tc-avr.c:594 ++#: config/tc-avr.c:601 +#, c-format +msgid "number must be positive and less than %d" +msgstr "" + -+#: config/tc-avr.c:620 config/tc-avr.c:757 ++#: config/tc-avr.c:627 config/tc-avr.c:764 +#, c-format +msgid "constant out of 8-bit range: %d" +msgstr "" + -+#: config/tc-avr.c:688 config/tc-score.c:1199 read.c:3661 ++#: config/tc-avr.c:695 config/tc-score.c:1199 read.c:3725 +msgid "illegal expression" +msgstr "" + -+#: config/tc-avr.c:717 config/tc-avr.c:1508 ++#: config/tc-avr.c:724 config/tc-avr.c:1542 +msgid "`)' required" +msgstr "" + -+#: config/tc-avr.c:812 ++#: config/tc-avr.c:819 +msgid "register r16-r23 required" +msgstr "" + -+#: config/tc-avr.c:818 ++#: config/tc-avr.c:825 +msgid "register number above 15 required" +msgstr "" + -+#: config/tc-avr.c:824 ++#: config/tc-avr.c:831 +msgid "even register number required" +msgstr "" + -+#: config/tc-avr.c:830 ++#: config/tc-avr.c:837 +msgid "register r24, r26, r28 or r30 required" +msgstr "" + -+#: config/tc-avr.c:836 ++#: config/tc-avr.c:843 +msgid "register name or number from 0 to 31 required" +msgstr "" + -+#: config/tc-avr.c:854 ++#: config/tc-avr.c:861 +msgid "pointer register (X, Y or Z) required" +msgstr "" + -+#: config/tc-avr.c:861 ++#: config/tc-avr.c:868 +msgid "cannot both predecrement and postincrement" +msgstr "" + -+#: config/tc-avr.c:869 ++#: config/tc-avr.c:876 +msgid "addressing mode not supported" +msgstr "" + -+#: config/tc-avr.c:875 ++#: config/tc-avr.c:882 +msgid "can't predecrement" +msgstr "" + -+#: config/tc-avr.c:878 ++#: config/tc-avr.c:885 +msgid "pointer register Z required" +msgstr "" + -+#: config/tc-avr.c:897 ++#: config/tc-avr.c:904 +msgid "postincrement not supported" +msgstr "" + -+#: config/tc-avr.c:907 ++#: config/tc-avr.c:914 +msgid "pointer register (Y or Z) required" +msgstr "" + -+#: config/tc-avr.c:1021 ++#: config/tc-avr.c:1028 config/tc-xgate.c:1349 +#, c-format +msgid "unknown constraint `%c'" +msgstr "" + -+#: config/tc-avr.c:1073 ++#: config/tc-avr.c:1080 +msgid "`,' required" +msgstr "" + -+#: config/tc-avr.c:1091 ++#: config/tc-avr.c:1098 +msgid "undefined combination of operands" +msgstr "" + -+#: config/tc-avr.c:1100 ++#: config/tc-avr.c:1107 +msgid "skipping two-word instruction" +msgstr "" + -+#: config/tc-avr.c:1192 config/tc-avr.c:1208 config/tc-avr.c:1329 -+#: config/tc-msp430.c:1969 config/tc-msp430.c:1987 ++#: config/tc-avr.c:1199 config/tc-avr.c:1215 config/tc-avr.c:1336 ++#: config/tc-msp430.c:3659 config/tc-msp430.c:3678 +#, c-format +msgid "odd address operand: %ld" +msgstr "" + -+#: config/tc-avr.c:1200 config/tc-avr.c:1219 config/tc-avr.c:1237 -+#: config/tc-avr.c:1248 config/tc-avr.c:1255 config/tc-avr.c:1262 -+#: config/tc-d10v.c:505 config/tc-d30v.c:554 config/tc-msp430.c:1977 -+#: config/tc-msp430.c:1992 config/tc-msp430.c:2002 ++#: config/tc-avr.c:1207 config/tc-avr.c:1226 config/tc-avr.c:1244 ++#: config/tc-avr.c:1255 config/tc-avr.c:1262 config/tc-avr.c:1269 ++#: config/tc-d10v.c:505 config/tc-d30v.c:554 config/tc-msp430.c:3667 ++#: config/tc-msp430.c:3685 +#, c-format +msgid "operand out of range: %ld" +msgstr "" + -+#: config/tc-avr.c:1338 config/tc-d10v.c:1594 config/tc-d30v.c:2037 -+#: config/tc-msp430.c:2020 ++#: config/tc-avr.c:1357 config/tc-d10v.c:1594 config/tc-d30v.c:2037 ++#: config/tc-msp430.c:3750 +#, c-format +msgid "line %d: unknown relocation type: 0x%x" +msgstr "" + -+#: config/tc-avr.c:1352 ++#: config/tc-avr.c:1371 +msgid "only constant expression allowed" +msgstr "" + +#. xgettext:c-format. -+#: config/tc-avr.c:1412 config/tc-bfin.c:833 config/tc-d10v.c:1466 -+#: config/tc-d30v.c:1774 config/tc-mn10200.c:782 config/tc-mn10300.c:2170 -+#: config/tc-msp430.c:2055 config/tc-or32.c:957 config/tc-ppc.c:6581 -+#: config/tc-spu.c:879 config/tc-spu.c:1090 config/tc-v850.c:3000 -+#: config/tc-z80.c:2021 ++#: config/tc-avr.c:1411 config/tc-bfin.c:833 config/tc-d10v.c:1466 ++#: config/tc-d30v.c:1774 config/tc-metag.c:7023 config/tc-mn10200.c:782 ++#: config/tc-mn10300.c:2178 config/tc-msp430.c:3798 config/tc-or32.c:957 ++#: config/tc-ppc.c:7121 config/tc-spu.c:879 config/tc-spu.c:1090 ++#: config/tc-v850.c:3351 config/tc-z80.c:2051 +#, c-format +msgid "reloc %d not supported by object file format" +msgstr "" + -+#: config/tc-avr.c:1435 config/tc-h8300.c:1935 config/tc-mcore.c:881 -+#: config/tc-microblaze.c:823 config/tc-moxie.c:178 config/tc-msp430.c:1820 -+#: config/tc-pj.c:253 config/tc-sh.c:2590 config/tc-z8k.c:1216 ++#: config/tc-avr.c:1434 config/tc-h8300.c:1954 config/tc-mcore.c:881 ++#: config/tc-microblaze.c:920 config/tc-moxie.c:182 config/tc-msp430.c:3513 ++#: config/tc-pj.c:253 config/tc-sh.c:2589 config/tc-z8k.c:1216 +msgid "can't find opcode " +msgstr "" + -+#: config/tc-avr.c:1452 ++#: config/tc-avr.c:1451 +#, c-format +msgid "illegal opcode %s for mcu %s" +msgstr "" + -+#: config/tc-avr.c:1463 ++#: config/tc-avr.c:1462 +msgid "garbage at end of line" +msgstr "" + -+#: config/tc-avr.c:1537 config/tc-avr.c:1544 ++#: config/tc-avr.c:1591 +#, c-format +msgid "illegal %srelocation size: %d" +msgstr "" @@ -829752,21 +834654,21 @@ index 0000000..f1eec3b +msgid "rel too far BFD_RELOC_16" +msgstr "" + -+#: config/tc-cr16.c:165 read.c:4421 ++#: config/tc-cr16.c:165 read.c:4484 +msgid "using a bit field width of zero" +msgstr "" + -+#: config/tc-cr16.c:173 read.c:4429 ++#: config/tc-cr16.c:173 read.c:4492 +#, c-format +msgid "field width \"%s\" too complex for a bitfield" +msgstr "" + -+#: config/tc-cr16.c:182 read.c:4437 ++#: config/tc-cr16.c:182 read.c:4500 +#, c-format +msgid "field width %lu too big to fit in %d bytes: truncated to %d bits" +msgstr "" + -+#: config/tc-cr16.c:204 read.c:4459 ++#: config/tc-cr16.c:204 read.c:4522 +#, c-format +msgid "field value \"%s\" too complex for a bitfield" +msgstr "" @@ -829776,44 +834678,44 @@ index 0000000..f1eec3b +msgid "Unknown register pair - index relative mode: `%d'" +msgstr "" + -+#: config/tc-cr16.c:570 config/tc-crx.c:345 config/tc-mn10200.c:769 -+#: write.c:1003 ++#: config/tc-cr16.c:570 config/tc-crx.c:346 config/tc-mn10200.c:769 ++#: write.c:1012 +#, c-format +msgid "can't resolve `%s' {%s section} - `%s' {%s section}" +msgstr "" + -+#: config/tc-cr16.c:600 config/tc-crx.c:361 ++#: config/tc-cr16.c:600 config/tc-crx.c:362 +#, c-format +msgid "internal error: reloc %d (`%s') not supported by object file format" +msgstr "" + -+#: config/tc-cr16.c:693 config/tc-i386.c:8839 config/tc-s390.c:1911 ++#: config/tc-cr16.c:693 config/tc-i386.c:10111 config/tc-s390.c:2002 +msgid "GOT already in symbol table" +msgstr "" + +#: config/tc-cr16.c:802 config/tc-cr16.c:825 config/tc-cris.c:1190 -+#: config/tc-crx.c:535 config/tc-crx.c:562 config/tc-crx.c:580 ++#: config/tc-crx.c:536 config/tc-crx.c:563 config/tc-crx.c:581 +#: config/tc-pdp11.c:194 +msgid "Virtual memory exhausted" +msgstr "" + -+#: config/tc-cr16.c:810 config/tc-crx.c:572 config/tc-crx.c:591 -+#: config/tc-m68k.c:4656 config/tc-tilegx.c:300 config/tc-tilepro.c:242 ++#: config/tc-cr16.c:810 config/tc-crx.c:573 config/tc-crx.c:592 ++#: config/tc-m68k.c:4660 config/tc-tilegx.c:319 config/tc-tilepro.c:256 +#, c-format +msgid "Internal Error: Can't hash %s: %s" +msgstr "" + -+#: config/tc-cr16.c:836 config/tc-cris.c:1224 config/tc-crx.c:545 ++#: config/tc-cr16.c:836 config/tc-cris.c:1224 config/tc-crx.c:546 +#, c-format +msgid "Can't hash `%s': %s\n" +msgstr "" + -+#: config/tc-cr16.c:837 config/tc-cris.c:1225 config/tc-crx.c:546 ++#: config/tc-cr16.c:837 config/tc-cris.c:1225 config/tc-crx.c:547 +msgid "(unknown reason)" +msgstr "" + +#. Missing or bad expr becomes absolute 0. -+#: config/tc-cr16.c:889 config/tc-crx.c:619 ++#: config/tc-cr16.c:889 config/tc-crx.c:620 +#, c-format +msgid "missing or invalid displacement expression `%s' taken as 0" +msgstr "" @@ -829828,19 +834730,19 @@ index 0000000..f1eec3b +msgid "operand %d: illegal use expression: `%s`" +msgstr "" + -+#: config/tc-cr16.c:1115 config/tc-crx.c:1127 ++#: config/tc-cr16.c:1115 config/tc-crx.c:1128 +#, c-format +msgid "Unknown register: `%d'" +msgstr "" + +#. Issue a error message when register is illegal. -+#: config/tc-cr16.c:1123 config/tc-crx.c:1135 ++#: config/tc-cr16.c:1123 config/tc-crx.c:1136 +#, c-format +msgid "Illegal register (`%s') in Instruction: `%s'" +msgstr "" + -+#: config/tc-cr16.c:1194 config/tc-cr16.c:1269 config/tc-crx.c:757 -+#: config/tc-crx.c:777 config/tc-crx.c:792 ++#: config/tc-cr16.c:1194 config/tc-cr16.c:1269 config/tc-crx.c:758 ++#: config/tc-crx.c:778 config/tc-crx.c:793 +#, c-format +msgid "Illegal register `%s' in Instruction `%s'" +msgstr "" @@ -829858,24 +834760,24 @@ index 0000000..f1eec3b +msgid "garbage after index spec ignored" +msgstr "" + -+#: config/tc-cr16.c:1412 config/tc-crx.c:936 ++#: config/tc-cr16.c:1412 config/tc-crx.c:937 +#, c-format +msgid "Illegal operands (whitespace): `%s'" +msgstr "" + +#: config/tc-cr16.c:1424 config/tc-cr16.c:1431 config/tc-cr16.c:1448 -+#: config/tc-crx.c:948 config/tc-crx.c:955 config/tc-crx.c:972 -+#: config/tc-crx.c:1764 ++#: config/tc-crx.c:949 config/tc-crx.c:956 config/tc-crx.c:973 ++#: config/tc-crx.c:1765 +#, c-format +msgid "Missing matching brackets : `%s'" +msgstr "" + -+#: config/tc-cr16.c:1480 config/tc-crx.c:998 ++#: config/tc-cr16.c:1480 config/tc-crx.c:999 +#, c-format +msgid "Unknown exception: `%s'" +msgstr "" + -+#: config/tc-cr16.c:1565 config/tc-crx.c:1094 ++#: config/tc-cr16.c:1565 config/tc-crx.c:1095 +#, c-format +msgid "Illegal `cinv' parameter: `%c'" +msgstr "" @@ -829919,7 +834821,7 @@ index 0000000..f1eec3b +msgid "Illegal 32 bit - processor register (`%s') in Instruction: `%s'" +msgstr "" + -+#: config/tc-cr16.c:2100 config/tc-crx.c:1662 config/tc-crx.c:1679 ++#: config/tc-cr16.c:2100 config/tc-crx.c:1663 config/tc-crx.c:1680 +#, c-format +msgid "Same src/dest register is used (`r%d'), result is undefined" +msgstr "" @@ -829943,7 +834845,7 @@ index 0000000..f1eec3b +msgid "`%s' Illegal use of register." +msgstr "" + -+#: config/tc-cr16.c:2154 config/tc-crx.c:1671 ++#: config/tc-cr16.c:2154 config/tc-crx.c:1672 +#, c-format +msgid "`%s' has undefined result" +msgstr "" @@ -829953,57 +834855,57 @@ index 0000000..f1eec3b +msgid "Same src/dest register is used (`r%d'),result is undefined" +msgstr "" + -+#: config/tc-cr16.c:2333 config/tc-crx.c:1576 ++#: config/tc-cr16.c:2333 config/tc-crx.c:1577 +msgid "Incorrect number of operands" +msgstr "" + -+#: config/tc-cr16.c:2335 config/tc-crx.c:1578 ++#: config/tc-cr16.c:2335 config/tc-crx.c:1579 +#, c-format +msgid "Illegal type of operand (arg %d)" +msgstr "" + -+#: config/tc-cr16.c:2341 config/tc-crx.c:1584 ++#: config/tc-cr16.c:2341 config/tc-crx.c:1585 +#, c-format +msgid "Operand out of range (arg %d)" +msgstr "" + -+#: config/tc-cr16.c:2344 config/tc-crx.c:1587 ++#: config/tc-cr16.c:2344 config/tc-crx.c:1588 +#, c-format +msgid "Operand has odd displacement (arg %d)" +msgstr "" + -+#: config/tc-cr16.c:2347 config/tc-cr16.c:2378 config/tc-crx.c:1600 -+#: config/tc-crx.c:1631 ++#: config/tc-cr16.c:2347 config/tc-cr16.c:2378 config/tc-crx.c:1601 ++#: config/tc-crx.c:1632 +#, c-format +msgid "Illegal operand (arg %d)" +msgstr "" + +#. Give an error if a frag containing code is not aligned to a 2-byte +#. boundary. -+#: config/tc-cr16.c:2480 config/tc-cr16.h:73 config/tc-crx.c:1953 -+#: config/tc-crx.h:76 ++#: config/tc-cr16.c:2480 config/tc-cr16.h:73 config/tc-crx.c:1954 ++#: config/tc-crx.h:76 config/tc-ppc.c:3402 config/tc-ppc.c:6375 +msgid "instruction address is not a multiple of 2" +msgstr "" + +#: config/tc-cr16.c:2555 config/tc-cris.c:1538 config/tc-cris.c:1546 -+#: config/tc-crx.c:1989 config/tc-dlx.c:685 config/tc-hppa.c:3244 -+#: config/tc-hppa.c:3251 config/tc-i860.c:491 config/tc-i860.c:508 ++#: config/tc-crx.c:1990 config/tc-dlx.c:690 config/tc-hppa.c:3248 ++#: config/tc-hppa.c:3255 config/tc-i860.c:491 config/tc-i860.c:508 +#: config/tc-i860.c:988 config/tc-sparc.c:1518 config/tc-sparc.c:1526 +#, c-format +msgid "Unknown opcode: `%s'" +msgstr "" + -+#: config/tc-cris.c:551 config/tc-m68hc11.c:2733 ++#: config/tc-cris.c:551 config/tc-m68hc11.c:3898 +#, c-format +msgid "internal inconsistency problem in %s: fr_symbol %lx" +msgstr "" + -+#: config/tc-cris.c:555 config/tc-m68hc11.c:2737 config/tc-msp430.c:2246 ++#: config/tc-cris.c:555 config/tc-m68hc11.c:3902 config/tc-msp430.c:4148 +#, c-format +msgid "internal inconsistency problem in %s: resolved symbol" +msgstr "" + -+#: config/tc-cris.c:565 config/tc-m68hc11.c:2743 ++#: config/tc-cris.c:565 config/tc-m68hc11.c:3908 +#, c-format +msgid "internal inconsistency problem in %s: fr_subtype %d" +msgstr "" @@ -830086,7 +834988,7 @@ index 0000000..f1eec3b + +#. We've come to the end of instructions with this +#. opcode, so it must be an error. -+#: config/tc-cris.c:2079 config/tc-mips.c:13126 ++#: config/tc-cris.c:2079 +msgid "Illegal operands" +msgstr "" + @@ -830208,13 +835110,13 @@ index 0000000..f1eec3b +msgid "invalid in --march=: %s" +msgstr "" + -+#: config/tc-cris.c:3938 config/tc-moxie.c:709 ++#: config/tc-cris.c:3938 config/tc-moxie.c:772 +msgid "" +"Semantics error. This type of operand can not be relocated, it must be an " +"assembly-time constant" +msgstr "" + -+#: config/tc-cris.c:3987 config/tc-moxie.c:758 ++#: config/tc-cris.c:3987 config/tc-moxie.c:821 +#, c-format +msgid "Cannot generate relocation type for symbol %s, code %s" +msgstr "" @@ -830310,81 +835212,81 @@ index 0000000..f1eec3b +msgid ".arch requires a matching --march=... option" +msgstr "" + -+#: config/tc-crx.c:820 ++#: config/tc-crx.c:821 +#, c-format +msgid "Illegal Scale - `%d'" +msgstr "" + -+#: config/tc-crx.c:1264 ++#: config/tc-crx.c:1263 +#, c-format +msgid "Illegal Co-processor register in Instruction `%s' " +msgstr "" + -+#: config/tc-crx.c:1271 ++#: config/tc-crx.c:1270 +#, c-format +msgid "Illegal Co-processor special register in Instruction `%s' " +msgstr "" + -+#: config/tc-crx.c:1590 ++#: config/tc-crx.c:1591 +#, c-format +msgid "Invalid DISPU4 operand value (arg %d)" +msgstr "" + -+#: config/tc-crx.c:1593 ++#: config/tc-crx.c:1594 +#, c-format +msgid "Invalid CST4 operand value (arg %d)" +msgstr "" + -+#: config/tc-crx.c:1596 ++#: config/tc-crx.c:1597 +#, c-format +msgid "Operand value is not within upper 64 KB (arg %d)" +msgstr "" + -+#: config/tc-crx.c:1733 ++#: config/tc-crx.c:1734 +msgid "Invalid Register in Register List" +msgstr "" + -+#: config/tc-crx.c:1787 ++#: config/tc-crx.c:1788 +#, c-format +msgid "Illegal register `%s' in cop-register list" +msgstr "" + -+#: config/tc-crx.c:1795 ++#: config/tc-crx.c:1796 +#, c-format +msgid "Illegal register `%s' in cop-special-register list" +msgstr "" + -+#: config/tc-crx.c:1814 ++#: config/tc-crx.c:1815 +#, c-format +msgid "Illegal register `%s' in user register list" +msgstr "" + -+#: config/tc-crx.c:1833 ++#: config/tc-crx.c:1834 +#, c-format +msgid "Illegal register `%s' in register list" +msgstr "" + -+#: config/tc-crx.c:1839 ++#: config/tc-crx.c:1840 +#, c-format +msgid "Maximum %d bits may be set in `mask16' operand" +msgstr "" + -+#: config/tc-crx.c:1848 ++#: config/tc-crx.c:1849 +#, c-format +msgid "rest of line ignored; first ignored character is `%c'" +msgstr "" + -+#: config/tc-crx.c:1856 ++#: config/tc-crx.c:1857 +#, c-format +msgid "Illegal `mask16' operand, operation is undefined - `%s'" +msgstr "" + +#. HI can't be specified without LO (and vise-versa). -+#: config/tc-crx.c:1862 ++#: config/tc-crx.c:1863 +msgid "HI/LO registers should be specified together" +msgstr "" + -+#: config/tc-crx.c:1868 ++#: config/tc-crx.c:1869 +msgid "HI/LO registers should be specified without additional registers" +msgstr "" + @@ -830681,80 +835583,84 @@ index 0000000..f1eec3b +msgid ".endfunc missing for previous .proc" +msgstr "" + -+#: config/tc-dlx.c:291 config/tc-i860.c:227 config/tc-mips.c:2321 ++#: config/tc-dlx.c:296 config/tc-i860.c:227 config/tc-mips.c:3354 ++#: config/tc-nios2.c:2611 config/tc-nios2.c:2625 config/tc-nios2.c:2640 ++#: config/tc-nios2.c:2654 +#, c-format +msgid "internal error: can't hash `%s': %s\n" +msgstr "" + +#. Probably a memory allocation problem? Give up now. -+#: config/tc-dlx.c:298 config/tc-hppa.c:8354 config/tc-mips.c:2324 -+#: config/tc-mips.c:2416 config/tc-or32.c:211 config/tc-sparc.c:888 ++#. Probably a memory allocation problem. Give up now. ++#: config/tc-dlx.c:303 config/tc-hppa.c:8365 config/tc-nios2.c:2614 ++#: config/tc-nios2.c:2628 config/tc-nios2.c:2643 config/tc-nios2.c:2657 ++#: config/tc-nios2.c:2773 config/tc-or32.c:211 config/tc-sparc.c:899 +msgid "Broken assembler. No assembly attempted." +msgstr "" + -+#: config/tc-dlx.c:328 ++#: config/tc-dlx.c:333 +#, c-format +msgid "Bad operand for a load instruction: <%s>" +msgstr "" + -+#: config/tc-dlx.c:442 ++#: config/tc-dlx.c:447 +#, c-format +msgid "Bad operand for a store instruction: <%s>" +msgstr "" + -+#: config/tc-dlx.c:622 ++#: config/tc-dlx.c:627 +#, c-format +msgid "Expression Error for operand modifier %%hi/%%lo\n" +msgstr "" + -+#: config/tc-dlx.c:635 config/tc-or32.c:811 ++#: config/tc-dlx.c:640 config/tc-or32.c:811 +#, c-format +msgid "Invalid expression after %%%%\n" +msgstr "" + -+#: config/tc-dlx.c:703 config/tc-tic4x.c:2487 ++#: config/tc-dlx.c:708 config/tc-tic4x.c:2481 +#, c-format +msgid "Unknown opcode `%s'." +msgstr "" + -+#: config/tc-dlx.c:715 ++#: config/tc-dlx.c:720 +msgid "Can not set dlx_skip_hi16_flag" +msgstr "" + -+#: config/tc-dlx.c:729 ++#: config/tc-dlx.c:734 +#, c-format +msgid "Missing arguments for opcode <%s>." +msgstr "" + -+#: config/tc-dlx.c:763 ++#: config/tc-dlx.c:768 +#, c-format +msgid "Too many operands: %s" +msgstr "" + -+#: config/tc-dlx.c:800 ++#: config/tc-dlx.c:805 +#, c-format +msgid "Both the_insn.HI and the_insn.LO are set : %s" +msgstr "" + -+#: config/tc-dlx.c:870 ++#: config/tc-dlx.c:875 +msgid "failed regnum sanity check." +msgstr "" + -+#: config/tc-dlx.c:883 ++#: config/tc-dlx.c:888 +msgid "failed general register sanity check." +msgstr "" + +#. Types or values of args don't match. -+#: config/tc-dlx.c:891 ++#: config/tc-dlx.c:896 +msgid "Invalid operands" +msgstr "" + -+#: config/tc-dlx.c:1120 config/tc-or32.c:773 ++#: config/tc-dlx.c:1125 config/tc-or32.c:773 +#, c-format +msgid "label \"$%d\" redefined" +msgstr "" + -+#: config/tc-dlx.c:1158 ++#: config/tc-dlx.c:1163 +msgid "Invalid expression after # number\n" +msgstr "" + @@ -830771,7 +835677,7 @@ index 0000000..f1eec3b +msgid "register is out of order" +msgstr "" + -+#: config/tc-epiphany.c:401 config/tc-m68k.c:6037 config/tc-m68k.c:6066 ++#: config/tc-epiphany.c:401 config/tc-m68k.c:6041 config/tc-m68k.c:6070 +msgid "bad register list" +msgstr "" + @@ -830947,181 +835853,181 @@ index 0000000..f1eec3b +msgid "Relocation %s is not safe for %s" +msgstr "" + -+#: config/tc-h8300.c:174 ++#: config/tc-h8300.c:172 +#, c-format +msgid "new section '%s' defined without attributes - this might cause problems" +msgstr "" + -+#: config/tc-h8300.c:446 config/tc-h8300.c:454 ++#: config/tc-h8300.c:443 config/tc-h8300.c:451 +msgid "Reg not valid for H8/300" +msgstr "" + -+#: config/tc-h8300.c:535 ++#: config/tc-h8300.c:532 +msgid "invalid operand size requested" +msgstr "" + -+#: config/tc-h8300.c:634 ++#: config/tc-h8300.c:637 +msgid "Invalid register list for ldm/stm\n" +msgstr "" + -+#: config/tc-h8300.c:660 config/tc-h8300.c:665 config/tc-h8300.c:672 ++#: config/tc-h8300.c:663 config/tc-h8300.c:668 config/tc-h8300.c:675 +msgid "mismatch between register and suffix" +msgstr "" + -+#: config/tc-h8300.c:677 ++#: config/tc-h8300.c:680 +msgid "invalid suffix after register." +msgstr "" + -+#: config/tc-h8300.c:699 ++#: config/tc-h8300.c:702 +msgid "address too high for vector table jmp/jsr" +msgstr "" + -+#: config/tc-h8300.c:726 config/tc-h8300.c:838 config/tc-h8300.c:848 ++#: config/tc-h8300.c:729 config/tc-h8300.c:841 config/tc-h8300.c:851 +msgid "Wrong size pointer register for architecture." +msgstr "" + -+#: config/tc-h8300.c:785 config/tc-h8300.c:793 config/tc-h8300.c:822 ++#: config/tc-h8300.c:788 config/tc-h8300.c:796 config/tc-h8300.c:825 +msgid "expected @(exp, reg16)" +msgstr "" + -+#: config/tc-h8300.c:811 ++#: config/tc-h8300.c:814 +msgid "expected .L, .W or .B for register in indexed addressing mode" +msgstr "" + -+#: config/tc-h8300.c:1005 ++#: config/tc-h8300.c:1008 +msgid "expected valid addressing mode for mova: \"@(disp, ea.sz),ERn\"" +msgstr "" + -+#: config/tc-h8300.c:1023 config/tc-h8300.c:1032 ++#: config/tc-h8300.c:1026 config/tc-h8300.c:1035 +msgid "expected register" +msgstr "" + -+#: config/tc-h8300.c:1048 ++#: config/tc-h8300.c:1051 +msgid "expected closing paren" +msgstr "" + -+#: config/tc-h8300.c:1107 ++#: config/tc-h8300.c:1110 +#, c-format +msgid "can't use high part of register in operand %d" +msgstr "" + -+#: config/tc-h8300.c:1264 ++#: config/tc-h8300.c:1267 +#, c-format +msgid "Opcode `%s' with these operand types not available in %s mode" +msgstr "" + -+#: config/tc-h8300.c:1273 ++#: config/tc-h8300.c:1276 +msgid "mismatch between opcode size and operand size" +msgstr "" + -+#: config/tc-h8300.c:1309 ++#: config/tc-h8300.c:1312 +#, c-format +msgid "operand %s0x%lx out of range." +msgstr "" + -+#: config/tc-h8300.c:1416 ++#: config/tc-h8300.c:1429 +msgid "Can't work out size of operand.\n" +msgstr "" + -+#: config/tc-h8300.c:1465 ++#: config/tc-h8300.c:1478 +#, c-format +msgid "Opcode `%s' with these operand types not available in H8/300 mode" +msgstr "" + -+#: config/tc-h8300.c:1470 ++#: config/tc-h8300.c:1483 +#, c-format +msgid "Opcode `%s' with these operand types not available in H8/300H mode" +msgstr "" + -+#: config/tc-h8300.c:1476 ++#: config/tc-h8300.c:1489 +#, c-format +msgid "Opcode `%s' with these operand types not available in H8/300S mode" +msgstr "" + -+#: config/tc-h8300.c:1537 config/tc-h8300.c:1557 ++#: config/tc-h8300.c:1550 config/tc-h8300.c:1570 +msgid "Need #1 or #2 here" +msgstr "" + -+#: config/tc-h8300.c:1552 ++#: config/tc-h8300.c:1565 +msgid "#4 not valid on H8/300." +msgstr "" + -+#: config/tc-h8300.c:1660 config/tc-h8300.c:1742 ++#: config/tc-h8300.c:1680 config/tc-h8300.c:1762 +#, c-format +msgid "branch operand has odd offset (%lx)\n" +msgstr "" + -+#: config/tc-h8300.c:1780 ++#: config/tc-h8300.c:1800 +msgid "destination operand must be 16 bit register" +msgstr "" + -+#: config/tc-h8300.c:1789 ++#: config/tc-h8300.c:1809 +msgid "source operand must be 8 bit register" +msgstr "" + -+#: config/tc-h8300.c:1797 ++#: config/tc-h8300.c:1817 +msgid "destination operand must be 16bit absolute address" +msgstr "" + -+#: config/tc-h8300.c:1804 ++#: config/tc-h8300.c:1824 +msgid "destination operand must be 8 bit register" +msgstr "" + -+#: config/tc-h8300.c:1812 ++#: config/tc-h8300.c:1832 +msgid "source operand must be 16bit absolute address" +msgstr "" + +#. This seems more sane than saying "too many operands". We'll +#. get here only if the trailing trash starts with a comma. +#. Types or values of args don't match. -+#: config/tc-h8300.c:1820 config/tc-mmix.c:472 config/tc-mmix.c:484 -+#: config/tc-mmix.c:2505 config/tc-mmix.c:2529 config/tc-mmix.c:2802 -+#: config/tc-or32.c:527 ++#: config/tc-h8300.c:1840 config/tc-mips.c:13043 config/tc-mips.c:13111 ++#: config/tc-mmix.c:479 config/tc-mmix.c:491 config/tc-mmix.c:2531 ++#: config/tc-mmix.c:2555 config/tc-mmix.c:2828 config/tc-or32.c:527 +msgid "invalid operands" +msgstr "" + -+#: config/tc-h8300.c:1851 ++#: config/tc-h8300.c:1871 +msgid "operand/size mis-match" +msgstr "" + -+#: config/tc-h8300.c:1952 config/tc-mips.c:13197 config/tc-sh.c:2971 -+#: config/tc-sh64.c:2795 config/tc-z8k.c:1226 ++#: config/tc-h8300.c:1971 config/tc-sh.c:2970 config/tc-sh64.c:2795 ++#: config/tc-z8k.c:1226 +msgid "unknown opcode" +msgstr "" + -+#: config/tc-h8300.c:1985 ++#: config/tc-h8300.c:2004 +msgid "invalid operand in ldm" +msgstr "" + -+#: config/tc-h8300.c:1994 ++#: config/tc-h8300.c:2013 +msgid "invalid operand in stm" +msgstr "" + -+#: config/tc-h8300.c:2120 ++#: config/tc-h8300.c:2139 +#, c-format +msgid "call to tc_aout_fix_to_chars \n" +msgstr "" + -+#: config/tc-h8300.c:2129 config/tc-xc16x.c:347 ++#: config/tc-h8300.c:2148 config/tc-xc16x.c:347 +#, c-format +msgid "call to md_convert_frag \n" +msgstr "" + -+#: config/tc-h8300.c:2180 config/tc-xc16x.c:251 ++#: config/tc-h8300.c:2199 config/tc-xc16x.c:251 +#, c-format +msgid "call to md_estimate_size_before_relax \n" +msgstr "" + -+#: config/tc-h8300.c:2195 ++#: config/tc-h8300.c:2214 +msgid "Unexpected reference to a symbol in a non-code section" +msgstr "" + -+#: config/tc-h8300.c:2211 config/tc-xc16x.c:292 ++#: config/tc-h8300.c:2230 config/tc-xc16x.c:292 +msgid "Difference of symbols in different sections is not supported" +msgstr "" + -+#: config/tc-h8300.c:2233 config/tc-mcore.c:2199 config/tc-microblaze.c:2294 -+#: config/tc-pj.c:487 config/tc-sh.c:4468 config/tc-tic6x.c:4500 ++#: config/tc-h8300.c:2252 config/tc-mcore.c:2199 config/tc-microblaze.c:2444 ++#: config/tc-pj.c:487 config/tc-sh.c:4478 config/tc-tic6x.c:4523 +#: config/tc-xc16x.c:315 +#, c-format +msgid "Cannot represent relocation type %s" @@ -831203,7 +836109,7 @@ index 0000000..f1eec3b +msgid "Undefined absolute constant: '%s'." +msgstr "" + -+#: config/tc-hppa.c:2261 config/tc-hppa.c:5717 ++#: config/tc-hppa.c:2261 config/tc-hppa.c:5728 +msgid "could not update architecture and machine" +msgstr "" + @@ -831222,348 +836128,348 @@ index 0000000..f1eec3b +msgid "Invalid FP Operand Format: %3s" +msgstr "" + -+#: config/tc-hppa.c:2591 ++#: config/tc-hppa.c:2561 +msgid "Bad segment (should be absolute)." +msgstr "" + -+#: config/tc-hppa.c:2617 ++#: config/tc-hppa.c:2621 +#, c-format +msgid "Invalid argument location: %s\n" +msgstr "" + -+#: config/tc-hppa.c:2646 ++#: config/tc-hppa.c:2650 +#, c-format +msgid "Invalid argument description: %d" +msgstr "" + -+#: config/tc-hppa.c:3475 ++#: config/tc-hppa.c:3479 +msgid "Invalid Indexed Load Completer." +msgstr "" + -+#: config/tc-hppa.c:3480 ++#: config/tc-hppa.c:3484 +msgid "Invalid Indexed Load Completer Syntax." +msgstr "" + -+#: config/tc-hppa.c:3514 ++#: config/tc-hppa.c:3518 +msgid "Invalid Short Load/Store Completer." +msgstr "" + -+#: config/tc-hppa.c:3574 config/tc-hppa.c:3579 ++#: config/tc-hppa.c:3578 config/tc-hppa.c:3583 +msgid "Invalid Store Bytes Short Completer" +msgstr "" + -+#: config/tc-hppa.c:3894 config/tc-hppa.c:3900 ++#: config/tc-hppa.c:3898 config/tc-hppa.c:3904 +msgid "Invalid left/right combination completer" +msgstr "" + -+#: config/tc-hppa.c:3949 config/tc-hppa.c:3956 ++#: config/tc-hppa.c:3953 config/tc-hppa.c:3960 +msgid "Invalid permutation completer" +msgstr "" + -+#: config/tc-hppa.c:4056 ++#: config/tc-hppa.c:4060 +#, c-format +msgid "Invalid Add Condition: %s" +msgstr "" + -+#: config/tc-hppa.c:4072 config/tc-hppa.c:4082 ++#: config/tc-hppa.c:4076 config/tc-hppa.c:4086 +msgid "Invalid Add and Branch Condition" +msgstr "" + -+#: config/tc-hppa.c:4103 config/tc-hppa.c:4248 ++#: config/tc-hppa.c:4107 config/tc-hppa.c:4252 +msgid "Invalid Compare/Subtract Condition" +msgstr "" + -+#: config/tc-hppa.c:4143 ++#: config/tc-hppa.c:4147 +#, c-format +msgid "Invalid Branch On Bit Condition: %c" +msgstr "" + -+#: config/tc-hppa.c:4146 ++#: config/tc-hppa.c:4150 +msgid "Missing Branch On Bit Condition" +msgstr "" + -+#: config/tc-hppa.c:4231 ++#: config/tc-hppa.c:4235 +#, c-format +msgid "Invalid Compare/Subtract Condition: %s" +msgstr "" + -+#: config/tc-hppa.c:4263 ++#: config/tc-hppa.c:4267 +msgid "Invalid Compare and Branch Condition" +msgstr "" + -+#: config/tc-hppa.c:4359 ++#: config/tc-hppa.c:4363 +msgid "Invalid Logical Instruction Condition." +msgstr "" + -+#: config/tc-hppa.c:4421 ++#: config/tc-hppa.c:4425 +msgid "Invalid Shift/Extract/Deposit Condition." +msgstr "" + -+#: config/tc-hppa.c:4534 ++#: config/tc-hppa.c:4542 +msgid "Invalid Unit Instruction Condition." +msgstr "" + -+#: config/tc-hppa.c:5013 config/tc-hppa.c:5045 config/tc-hppa.c:5076 -+#: config/tc-hppa.c:5106 ++#: config/tc-hppa.c:5021 config/tc-hppa.c:5053 config/tc-hppa.c:5084 ++#: config/tc-hppa.c:5114 +msgid "Branch to unaligned address" +msgstr "" + -+#: config/tc-hppa.c:5290 ++#: config/tc-hppa.c:5298 +msgid "Invalid SFU identifier" +msgstr "" + -+#: config/tc-hppa.c:5340 ++#: config/tc-hppa.c:5348 +msgid "Invalid COPR identifier" +msgstr "" + -+#: config/tc-hppa.c:5469 ++#: config/tc-hppa.c:5477 +msgid "Invalid Floating Point Operand Format." +msgstr "" + -+#: config/tc-hppa.c:5586 config/tc-hppa.c:5606 config/tc-hppa.c:5626 -+#: config/tc-hppa.c:5646 config/tc-hppa.c:5666 ++#: config/tc-hppa.c:5597 config/tc-hppa.c:5617 config/tc-hppa.c:5637 ++#: config/tc-hppa.c:5657 config/tc-hppa.c:5677 +msgid "Invalid register for single precision fmpyadd or fmpysub" +msgstr "" + -+#: config/tc-hppa.c:5734 ++#: config/tc-hppa.c:5745 +#, c-format +msgid "Invalid operands %s" +msgstr "" + -+#: config/tc-hppa.c:5744 ++#: config/tc-hppa.c:5755 +#, c-format +msgid "Immediates %d and %d will give undefined behavior." +msgstr "" + -+#: config/tc-hppa.c:5796 config/tc-hppa.c:7023 config/tc-hppa.c:7078 ++#: config/tc-hppa.c:5807 config/tc-hppa.c:7034 config/tc-hppa.c:7089 +msgid "Missing function name for .PROC (corrupted label chain)" +msgstr "" + -+#: config/tc-hppa.c:5799 config/tc-hppa.c:7081 ++#: config/tc-hppa.c:5810 config/tc-hppa.c:7092 +msgid "Missing function name for .PROC" +msgstr "" + -+#: config/tc-hppa.c:5858 ++#: config/tc-hppa.c:5869 +msgid "Argument to .BLOCK/.BLOCKZ must be between 0 and 0x3fffffff" +msgstr "" + -+#: config/tc-hppa.c:5954 ++#: config/tc-hppa.c:5965 +#, c-format +msgid "Invalid .CALL argument: %s" +msgstr "" + -+#: config/tc-hppa.c:6102 ++#: config/tc-hppa.c:6113 +msgid ".callinfo is not within a procedure definition" +msgstr "" + -+#: config/tc-hppa.c:6122 ++#: config/tc-hppa.c:6133 +#, c-format +msgid "FRAME parameter must be a multiple of 8: %d\n" +msgstr "" + -+#: config/tc-hppa.c:6141 ++#: config/tc-hppa.c:6152 +msgid "Value for ENTRY_GR must be in the range 3..18\n" +msgstr "" + -+#: config/tc-hppa.c:6153 ++#: config/tc-hppa.c:6164 +msgid "Value for ENTRY_FR must be in the range 12..21\n" +msgstr "" + -+#: config/tc-hppa.c:6163 ++#: config/tc-hppa.c:6174 +msgid "Value for ENTRY_SR must be 3\n" +msgstr "" + -+#: config/tc-hppa.c:6219 ++#: config/tc-hppa.c:6230 +#, c-format +msgid "Invalid .CALLINFO argument: %s" +msgstr "" + -+#: config/tc-hppa.c:6329 ++#: config/tc-hppa.c:6340 +msgid "The .ENTER pseudo-op is not supported" +msgstr "" + -+#: config/tc-hppa.c:6345 ++#: config/tc-hppa.c:6356 +msgid "Misplaced .entry. Ignored." +msgstr "" + -+#: config/tc-hppa.c:6349 ++#: config/tc-hppa.c:6360 +msgid "Missing .callinfo." +msgstr "" + -+#: config/tc-hppa.c:6413 ++#: config/tc-hppa.c:6424 +msgid ".REG expression must be a register" +msgstr "" + -+#: config/tc-hppa.c:6429 ++#: config/tc-hppa.c:6440 +msgid "bad or irreducible absolute expression; zero assumed" +msgstr "" + -+#: config/tc-hppa.c:6440 ++#: config/tc-hppa.c:6451 +msgid ".REG must use a label" +msgstr "" + -+#: config/tc-hppa.c:6442 ++#: config/tc-hppa.c:6453 +msgid ".EQU must use a label" +msgstr "" + -+#: config/tc-hppa.c:6504 ++#: config/tc-hppa.c:6515 +#, c-format +msgid "Symbol '%s' could not be created." +msgstr "" + -+#: config/tc-hppa.c:6508 ++#: config/tc-hppa.c:6519 +msgid "No memory for symbol name." +msgstr "" + -+#: config/tc-hppa.c:6558 ++#: config/tc-hppa.c:6569 +msgid ".EXIT must appear within a procedure" +msgstr "" + -+#: config/tc-hppa.c:6562 ++#: config/tc-hppa.c:6573 +msgid "Missing .callinfo" +msgstr "" + -+#: config/tc-hppa.c:6566 ++#: config/tc-hppa.c:6577 +msgid "No .ENTRY for this .EXIT" +msgstr "" + -+#: config/tc-hppa.c:6606 ++#: config/tc-hppa.c:6617 +#, c-format +msgid "Using ENTRY rather than CODE in export directive for %s" +msgstr "" + -+#: config/tc-hppa.c:6729 ++#: config/tc-hppa.c:6740 +#, c-format +msgid "Undefined .EXPORT/.IMPORT argument (ignored): %s" +msgstr "" + -+#: config/tc-hppa.c:6753 ++#: config/tc-hppa.c:6764 +#, c-format +msgid "Cannot define export symbol: %s\n" +msgstr "" + -+#: config/tc-hppa.c:6850 ++#: config/tc-hppa.c:6861 +msgid "Missing label name on .LABEL" +msgstr "" + -+#: config/tc-hppa.c:6855 ++#: config/tc-hppa.c:6866 +msgid "extra .LABEL arguments ignored." +msgstr "" + -+#: config/tc-hppa.c:6871 ++#: config/tc-hppa.c:6882 +msgid "The .LEAVE pseudo-op is not supported" +msgstr "" + -+#: config/tc-hppa.c:6909 ++#: config/tc-hppa.c:6920 +msgid "Unrecognized .LEVEL argument\n" +msgstr "" + -+#: config/tc-hppa.c:6943 ++#: config/tc-hppa.c:6954 +#, c-format +msgid "Cannot define static symbol: %s\n" +msgstr "" + -+#: config/tc-hppa.c:6977 ++#: config/tc-hppa.c:6988 +msgid "Nested procedures" +msgstr "" + -+#: config/tc-hppa.c:6987 ++#: config/tc-hppa.c:6998 +msgid "Cannot allocate unwind descriptor\n" +msgstr "" + -+#: config/tc-hppa.c:7085 ++#: config/tc-hppa.c:7096 +msgid "misplaced .procend" +msgstr "" + -+#: config/tc-hppa.c:7088 ++#: config/tc-hppa.c:7099 +msgid "Missing .callinfo for this procedure" +msgstr "" + -+#: config/tc-hppa.c:7091 ++#: config/tc-hppa.c:7102 +msgid "Missing .EXIT for a .ENTRY" +msgstr "" + -+#: config/tc-hppa.c:7128 ++#: config/tc-hppa.c:7139 +msgid "Not in a space.\n" +msgstr "" + -+#: config/tc-hppa.c:7131 ++#: config/tc-hppa.c:7142 +msgid "Not in a subspace.\n" +msgstr "" + -+#: config/tc-hppa.c:7220 ++#: config/tc-hppa.c:7231 +msgid "Invalid .SPACE argument" +msgstr "" + -+#: config/tc-hppa.c:7266 ++#: config/tc-hppa.c:7277 +msgid "Can't change spaces within a procedure definition. Ignored" +msgstr "" + -+#: config/tc-hppa.c:7394 ++#: config/tc-hppa.c:7405 +#, c-format +msgid "Undefined space: '%s' Assuming space number = 0." +msgstr "" + -+#: config/tc-hppa.c:7417 ++#: config/tc-hppa.c:7428 +msgid "Must be in a space before changing or declaring subspaces.\n" +msgstr "" + -+#: config/tc-hppa.c:7421 ++#: config/tc-hppa.c:7432 +msgid "Can't change subspaces within a procedure definition. Ignored" +msgstr "" + -+#: config/tc-hppa.c:7457 ++#: config/tc-hppa.c:7468 +msgid "Parameters of an existing subspace can't be modified" +msgstr "" + -+#: config/tc-hppa.c:7509 ++#: config/tc-hppa.c:7520 +msgid "Alignment must be a power of 2" +msgstr "" + -+#: config/tc-hppa.c:7556 ++#: config/tc-hppa.c:7567 +msgid "FIRST not supported as a .SUBSPACE argument" +msgstr "" + -+#: config/tc-hppa.c:7558 ++#: config/tc-hppa.c:7569 +msgid "Invalid .SUBSPACE argument" +msgstr "" + -+#: config/tc-hppa.c:7747 ++#: config/tc-hppa.c:7758 +#, c-format +msgid "Internal error: Unable to find containing space for %s." +msgstr "" + -+#: config/tc-hppa.c:7785 ++#: config/tc-hppa.c:7796 +#, c-format +msgid "Out of memory: could not allocate new space chain entry: %s\n" +msgstr "" + -+#: config/tc-hppa.c:7873 ++#: config/tc-hppa.c:7884 +#, c-format +msgid "Out of memory: could not allocate new subspace chain entry: %s\n" +msgstr "" + -+#: config/tc-hppa.c:8318 ++#: config/tc-hppa.c:8329 +msgid "-R option not supported on this target." +msgstr "" + -+#: config/tc-hppa.c:8335 config/tc-sparc.c:843 config/tc-sparc.c:880 ++#: config/tc-hppa.c:8346 config/tc-sparc.c:854 config/tc-sparc.c:891 +#, c-format +msgid "Internal error: can't hash `%s': %s\n" +msgstr "" + -+#: config/tc-hppa.c:8344 config/tc-i860.c:236 ++#: config/tc-hppa.c:8355 config/tc-i860.c:236 +#, c-format +msgid "internal error: losing opcode: `%s' \"%s\"\n" +msgstr "" + -+#: config/tc-i370.c:419 config/tc-ppc.c:1185 config/tc-s390.c:420 -+#: config/tc-s390.c:427 ++#: config/tc-i370.c:419 config/tc-ppc.c:1218 config/tc-s390.c:432 ++#: config/tc-s390.c:439 +#, c-format +msgid "invalid switch -m%s" +msgstr "" + -+#: config/tc-i370.c:516 config/tc-s390.c:507 ++#: config/tc-i370.c:516 config/tc-s390.c:519 +#, c-format +msgid "Internal assembler error for instruction %s" +msgstr "" @@ -831573,11 +836479,11 @@ index 0000000..f1eec3b +msgid "Internal assembler error for macro %s" +msgstr "" + -+#: config/tc-i370.c:630 config/tc-ppc.c:1893 ++#: config/tc-i370.c:630 config/tc-ppc.c:1995 +msgid "identifier+constant@got means identifier@got+constant" +msgstr "" + -+#: config/tc-i370.c:684 config/tc-m68k.c:8077 config/tc-ppc.c:1982 ++#: config/tc-i370.c:684 config/tc-m68k.c:8079 config/tc-ppc.c:2083 +#, c-format +msgid "%s relocations do not fit in %d bytes\n" +msgstr "" @@ -831599,29 +836505,28 @@ index 0000000..f1eec3b +msgid "this DS form not yet supported" +msgstr "" + -+#: config/tc-i370.c:1046 config/tc-m32r.c:1493 config/tc-microblaze.c:177 -+#: config/tc-ppc.c:2047 config/tc-ppc.c:4884 ++#: config/tc-i370.c:1046 config/tc-m32r.c:1493 config/tc-microblaze.c:191 +msgid "Expected comma after symbol-name: rest of line ignored." +msgstr "" + -+#: config/tc-i370.c:1069 config/tc-m32r.c:1517 config/tc-microblaze.c:199 -+#: config/tc-ppc.c:2069 config/tc-ppc.c:3272 config/tc-ppc.c:4908 ++#: config/tc-i370.c:1069 config/tc-m32r.c:1517 config/tc-microblaze.c:213 ++#: config/tc-ppc.c:2170 config/tc-ppc.c:3653 config/tc-ppc.c:3696 ++#: config/tc-ppc.c:5280 +msgid "ignoring bad alignment" +msgstr "" + -+#: config/tc-i370.c:1080 config/tc-m32r.c:1544 config/tc-microblaze.c:210 -+#: config/tc-ppc.c:2080 config/tc-ppc.c:4920 ++#: config/tc-i370.c:1080 config/tc-m32r.c:1544 config/tc-microblaze.c:224 +#, c-format +msgid "Ignoring attempt to re-define symbol `%s'." +msgstr "" + -+#: config/tc-i370.c:1088 config/tc-microblaze.c:218 config/tc-ppc.c:2088 ++#: config/tc-i370.c:1088 config/tc-microblaze.c:232 +#, c-format +msgid "Length of .lcomm \"%s\" is already %ld. Not changed to %ld." +msgstr "" + -+#: config/tc-i370.c:1107 config/tc-m32r.c:1529 config/tc-microblaze.c:234 -+#: config/tc-ppc.c:2106 config/tc-v850.c:375 ++#: config/tc-i370.c:1107 config/tc-m32r.c:1529 config/tc-microblaze.c:248 ++#: config/tc-v850.c:384 +msgid "Common alignment not a power of 2" +msgstr "" + @@ -831674,12 +836579,12 @@ index 0000000..f1eec3b +msgid "droping register %d in section %s previously used in section %s" +msgstr "" + -+#: config/tc-i370.c:1847 config/tc-ppc.c:3109 ++#: config/tc-i370.c:1847 config/tc-ppc.c:3490 +msgid "wrong number of operands" +msgstr "" + -+#: config/tc-i370.c:1928 config/tc-mn10200.c:899 config/tc-mn10300.c:1251 -+#: config/tc-ppc.c:2405 config/tc-s390.c:1590 config/tc-v850.c:2024 ++#: config/tc-i370.c:1928 config/tc-mn10200.c:899 config/tc-mn10300.c:1253 ++#: config/tc-s390.c:1608 config/tc-v850.c:2313 +#, c-format +msgid "Unrecognized opcode: `%s'" +msgstr "" @@ -831698,539 +836603,678 @@ index 0000000..f1eec3b +msgid "Internal Error: bad instruction length" +msgstr "" + -+#: config/tc-i386.c:1885 ++#: config/tc-i386.c:2077 +#, c-format +msgid "%s shortened to %s" +msgstr "" + -+#: config/tc-i386.c:1971 ++#: config/tc-i386.c:2163 +msgid "same type of prefix used twice" +msgstr "" + -+#: config/tc-i386.c:1998 ++#: config/tc-i386.c:2190 +#, c-format +msgid "64bit mode not supported on `%s'." +msgstr "" + -+#: config/tc-i386.c:2007 ++#: config/tc-i386.c:2199 +#, c-format +msgid "32bit mode not supported on `%s'." +msgstr "" + -+#: config/tc-i386.c:2047 ++#: config/tc-i386.c:2239 +msgid "bad argument to syntax directive." +msgstr "" + -+#: config/tc-i386.c:2096 -+msgid "bad argument to sse_check directive." ++#: config/tc-i386.c:2302 ++#, c-format ++msgid "bad argument to %s_check directive." +msgstr "" + -+#: config/tc-i386.c:2100 -+msgid "missing argument for sse_check directive" ++#: config/tc-i386.c:2306 ++#, c-format ++msgid "missing argument for %s_check directive" +msgstr "" + -+#: config/tc-i386.c:2135 ++#: config/tc-i386.c:2341 +#, c-format +msgid "`%s' is not supported on `%s'" +msgstr "" + -+#: config/tc-i386.c:2209 ++#: config/tc-i386.c:2415 +#, c-format +msgid "no such architecture: `%s'" +msgstr "" + -+#: config/tc-i386.c:2214 ++#: config/tc-i386.c:2420 +msgid "missing cpu architecture" +msgstr "" + -+#: config/tc-i386.c:2228 ++#: config/tc-i386.c:2434 +#, c-format +msgid "no such architecture modifier: `%s'" +msgstr "" + -+#: config/tc-i386.c:2243 config/tc-i386.c:2266 ++#: config/tc-i386.c:2449 config/tc-i386.c:2472 +msgid "Intel L1OM is 64bit ELF only" +msgstr "" + -+#: config/tc-i386.c:2250 config/tc-i386.c:2273 ++#: config/tc-i386.c:2456 config/tc-i386.c:2479 +msgid "Intel K1OM is 64bit ELF only" +msgstr "" + -+#: config/tc-i386.c:2284 config/tc-i386.c:8711 ++#: config/tc-i386.c:2490 config/tc-i386.c:9976 +msgid "unknown architecture" +msgstr "" + -+#: config/tc-i386.c:2318 config/tc-i386.c:2340 ++#: config/tc-i386.c:2524 config/tc-i386.c:2546 +#, c-format -+msgid "internal Error: Can't hash %s: %s" ++msgid "can't hash %s: %s" +msgstr "" + -+#: config/tc-i386.c:2635 ++#: config/tc-i386.c:2839 ++msgid "there are no pc-relative size relocations" ++msgstr "" ++ ++#: config/tc-i386.c:2849 +#, c-format +msgid "unknown relocation (%u)" +msgstr "" + -+#: config/tc-i386.c:2637 ++#: config/tc-i386.c:2851 +#, c-format +msgid "%u-byte relocation cannot be applied to %u-byte field" +msgstr "" + -+#: config/tc-i386.c:2641 ++#: config/tc-i386.c:2855 +msgid "non-pc-relative relocation for pc-relative field" +msgstr "" + -+#: config/tc-i386.c:2646 ++#: config/tc-i386.c:2860 +msgid "relocated field and relocation type differ in signedness" +msgstr "" + -+#: config/tc-i386.c:2655 ++#: config/tc-i386.c:2869 +msgid "there are no unsigned pc-relative relocations" +msgstr "" + -+#: config/tc-i386.c:2663 ++#: config/tc-i386.c:2879 +#, c-format +msgid "cannot do %u byte pc-relative relocation" +msgstr "" + -+#: config/tc-i386.c:2680 ++#: config/tc-i386.c:2896 +#, c-format +msgid "cannot do %s %u byte relocation" +msgstr "" + -+#: config/tc-i386.c:2964 ++#: config/tc-i386.c:3352 +#, c-format +msgid "can't use register '%s%s' as operand %d in '%s'." +msgstr "" + -+#: config/tc-i386.c:3076 ++#: config/tc-i386.c:3391 config/tc-i386.c:3528 ++#, c-format ++msgid "invalid instruction `%s' after `%s'" ++msgstr "" ++ ++#: config/tc-i386.c:3397 ++#, c-format ++msgid "missing `lock' with `%s'" ++msgstr "" ++ ++#: config/tc-i386.c:3404 ++#, c-format ++msgid "instruction `%s' after `xacquire' not allowed" ++msgstr "" ++ ++#: config/tc-i386.c:3411 ++#, c-format ++msgid "memory destination needed for instruction `%s' after `xrelease'" ++msgstr "" ++ ++#: config/tc-i386.c:3502 +#, c-format +msgid "SSE instruction `%s' is used" +msgstr "" + -+#: config/tc-i386.c:3090 config/tc-i386.c:4562 ++#: config/tc-i386.c:3516 config/tc-i386.c:5263 +#, c-format +msgid "ambiguous operand size for `%s'" +msgstr "" + -+#: config/tc-i386.c:3107 ++#: config/tc-i386.c:3541 +msgid "expecting lockable instruction after `lock'" +msgstr "" + ++#: config/tc-i386.c:3551 ++msgid "expecting valid branch instruction after `bnd'" ++msgstr "" ++ ++#: config/tc-i386.c:3556 ++msgid "32-bit address isn't allowed in 64-bit MPX instructions." ++msgstr "" ++ +#. UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. -+#: config/tc-i386.c:3158 ++#: config/tc-i386.c:3611 +#, c-format +msgid "translating to `%sp'" +msgstr "" + -+#: config/tc-i386.c:3213 ++#: config/tc-i386.c:3669 +#, c-format +msgid "can't encode register '%s%s' in an instruction requiring REX prefix." +msgstr "" + -+#: config/tc-i386.c:3256 config/tc-i386.c:3388 ++#: config/tc-i386.c:3709 config/tc-i386.c:3850 +#, c-format +msgid "no such instruction: `%s'" +msgstr "" + -+#: config/tc-i386.c:3267 config/tc-i386.c:3421 ++#: config/tc-i386.c:3720 config/tc-i386.c:3883 +#, c-format +msgid "invalid character %s in mnemonic" +msgstr "" + -+#: config/tc-i386.c:3274 ++#: config/tc-i386.c:3727 +msgid "expecting prefix; got nothing" +msgstr "" + -+#: config/tc-i386.c:3276 ++#: config/tc-i386.c:3729 +msgid "expecting mnemonic; got nothing" +msgstr "" + -+#: config/tc-i386.c:3291 config/tc-i386.c:3439 ++#: config/tc-i386.c:3744 config/tc-i386.c:3901 +#, c-format +msgid "`%s' is only supported in 64-bit mode" +msgstr "" + -+#: config/tc-i386.c:3292 config/tc-i386.c:3438 ++#: config/tc-i386.c:3745 config/tc-i386.c:3900 +#, c-format +msgid "`%s' is not supported in 64-bit mode" +msgstr "" + -+#: config/tc-i386.c:3304 ++#: config/tc-i386.c:3757 +#, c-format +msgid "redundant %s prefix" +msgstr "" + -+#: config/tc-i386.c:3445 ++#: config/tc-i386.c:3907 +#, c-format +msgid "`%s' is not supported on `%s%s'" +msgstr "" + -+#: config/tc-i386.c:3456 ++#: config/tc-i386.c:3918 +msgid "use .code16 to ensure correct addressing mode" +msgstr "" + -+#: config/tc-i386.c:3469 -+#, c-format -+msgid "expecting string instruction after `%s'" -+msgstr "" -+ -+#: config/tc-i386.c:3501 ++#: config/tc-i386.c:3942 +#, c-format +msgid "invalid character %s before operand %d" +msgstr "" + -+#: config/tc-i386.c:3515 ++#: config/tc-i386.c:3956 +#, c-format +msgid "unbalanced parenthesis in operand %d." +msgstr "" + -+#: config/tc-i386.c:3518 ++#: config/tc-i386.c:3959 +#, c-format +msgid "unbalanced brackets in operand %d." +msgstr "" + -+#: config/tc-i386.c:3527 ++#: config/tc-i386.c:3968 +#, c-format +msgid "invalid character %s in operand %d" +msgstr "" + -+#: config/tc-i386.c:3555 ++#: config/tc-i386.c:3996 +#, c-format +msgid "spurious operands; (%d operands/instruction max)" +msgstr "" + -+#: config/tc-i386.c:3578 ++#: config/tc-i386.c:4019 +msgid "expecting operand after ','; got nothing" +msgstr "" + -+#: config/tc-i386.c:3583 ++#: config/tc-i386.c:4024 +msgid "expecting operand before ','; got nothing" +msgstr "" + -+#: config/tc-i386.c:4257 ++#: config/tc-i386.c:4394 ++msgid "mask, index, and destination registers should be distinct" ++msgstr "" ++ ++#: config/tc-i386.c:4409 ++msgid "index and destination registers should be distinct" ++msgstr "" ++ ++#: config/tc-i386.c:4923 +msgid "operand size mismatch" +msgstr "" + -+#: config/tc-i386.c:4260 ++#: config/tc-i386.c:4926 +msgid "operand type mismatch" +msgstr "" + -+#: config/tc-i386.c:4263 ++#: config/tc-i386.c:4929 +msgid "register type mismatch" +msgstr "" + -+#: config/tc-i386.c:4266 ++#: config/tc-i386.c:4932 +msgid "number of operands mismatch" +msgstr "" + -+#: config/tc-i386.c:4269 ++#: config/tc-i386.c:4935 +msgid "invalid instruction suffix" +msgstr "" + -+#: config/tc-i386.c:4272 -+msgid "Imm4 isn't the first operand" ++#: config/tc-i386.c:4938 ++msgid "constant doesn't fit in 4 bits" +msgstr "" + -+#: config/tc-i386.c:4275 ++#: config/tc-i386.c:4941 +msgid "only supported with old gcc" +msgstr "" + -+#: config/tc-i386.c:4278 ++#: config/tc-i386.c:4944 +msgid "unsupported with Intel mnemonic" +msgstr "" + -+#: config/tc-i386.c:4281 ++#: config/tc-i386.c:4947 +msgid "unsupported syntax" +msgstr "" + -+#: config/tc-i386.c:4284 -+msgid "unsupported" ++#: config/tc-i386.c:4950 ++#, c-format ++msgid "unsupported instruction `%s'" +msgstr "" + -+#: config/tc-i386.c:4287 ++#: config/tc-i386.c:4954 +msgid "invalid VSIB address" +msgstr "" + -+#: config/tc-i386.c:4290 ++#: config/tc-i386.c:4957 ++msgid "mask, index, and destination registers must be distinct" ++msgstr "" ++ ++#: config/tc-i386.c:4960 +msgid "unsupported vector index register" +msgstr "" + -+#: config/tc-i386.c:4293 ++#: config/tc-i386.c:4963 ++msgid "unsupported broadcast" ++msgstr "" ++ ++#: config/tc-i386.c:4966 ++msgid "broadcast not on source memory operand" ++msgstr "" ++ ++#: config/tc-i386.c:4969 ++msgid "broadcast is needed for operand of such type" ++msgstr "" ++ ++#: config/tc-i386.c:4972 ++msgid "unsupported masking" ++msgstr "" ++ ++#: config/tc-i386.c:4975 ++msgid "mask not on destination operand" ++msgstr "" ++ ++#: config/tc-i386.c:4978 ++msgid "default mask isn't allowed" ++msgstr "" ++ ++#: config/tc-i386.c:4981 ++msgid "unsupported static rounding/sae" ++msgstr "" ++ ++#: config/tc-i386.c:4985 ++msgid "RC/SAE operand must precede immediate operands" ++msgstr "" ++ ++#: config/tc-i386.c:4987 ++msgid "RC/SAE operand must follow immediate operands" ++msgstr "" ++ ++#: config/tc-i386.c:4990 config/tc-metag.c:4788 config/tc-metag.c:5529 ++#: config/tc-metag.c:5551 ++msgid "invalid register operand" ++msgstr "" ++ ++#: config/tc-i386.c:4993 +#, c-format +msgid "%s for `%s'" +msgstr "" + -+#: config/tc-i386.c:4304 ++#: config/tc-i386.c:5004 +#, c-format +msgid "indirect %s without `*'" +msgstr "" + +#. Warn them that a data or address size prefix doesn't +#. affect assembly of the next line of code. -+#: config/tc-i386.c:4312 ++#: config/tc-i386.c:5012 +#, c-format +msgid "stand-alone `%s' prefix" +msgstr "" + -+#: config/tc-i386.c:4346 config/tc-i386.c:4362 ++#: config/tc-i386.c:5046 config/tc-i386.c:5062 +#, c-format +msgid "`%s' operand %d must use `%ses' segment" +msgstr "" + +#. We have to know the operand size for crc32. -+#: config/tc-i386.c:4416 ++#: config/tc-i386.c:5116 +#, c-format +msgid "ambiguous memory operand size for `%s`" +msgstr "" + -+#: config/tc-i386.c:4535 ++#: config/tc-i386.c:5236 +msgid "" +"no instruction mnemonic suffix given and no register operands; can't size " +"instruction" +msgstr "" + -+#: config/tc-i386.c:4672 config/tc-i386.c:4747 config/tc-i386.c:4776 -+#: config/tc-i386.c:4822 config/tc-i386.c:4860 -+#, c-format -+msgid "incorrect register `%s%s' used with `%c' suffix" -+msgstr "" -+ -+#: config/tc-i386.c:4680 config/tc-i386.c:4754 config/tc-i386.c:4867 ++#: config/tc-i386.c:5378 config/tc-i386.c:5452 config/tc-i386.c:5563 +#, c-format +msgid "using `%s%s' instead of `%s%s' due to `%c' suffix" +msgstr "" + -+#: config/tc-i386.c:4706 config/tc-i386.c:4730 config/tc-i386.c:4798 -+#: config/tc-i386.c:4843 ++#: config/tc-i386.c:5405 config/tc-i386.c:5429 config/tc-i386.c:5494 ++#: config/tc-i386.c:5539 +#, c-format +msgid "`%s%s' not allowed with `%s%c'" +msgstr "" + -+#: config/tc-i386.c:4932 ++#: config/tc-i386.c:5446 config/tc-i386.c:5472 config/tc-i386.c:5518 ++#: config/tc-i386.c:5557 ++#, c-format ++msgid "incorrect register `%s%s' used with `%c' suffix" ++msgstr "" ++ ++#: config/tc-i386.c:5626 +msgid "no instruction mnemonic suffix given; can't determine immediate size" +msgstr "" + -+#: config/tc-i386.c:4968 ++#: config/tc-i386.c:5662 +#, c-format +msgid "the last operand of `%s' must be `%s%s'" +msgstr "" + -+#: config/tc-i386.c:4971 ++#: config/tc-i386.c:5665 +#, c-format +msgid "the first operand of `%s' must be `%s%s'" +msgstr "" + -+#: config/tc-i386.c:5119 ++#: config/tc-i386.c:5814 +#, c-format +msgid "you can't `pop %scs'" +msgstr "" + +#. Reversed arguments on faddp, fsubp, etc. -+#: config/tc-i386.c:5148 ++#: config/tc-i386.c:5843 +#, c-format +msgid "translating to `%s %s%s,%s%s'" +msgstr "" + +#. Extraneous `l' suffix on fp insn. -+#: config/tc-i386.c:5155 ++#: config/tc-i386.c:5850 +#, c-format +msgid "translating to `%s %s%s'" +msgstr "" + -+#: config/tc-i386.c:5183 ++#: config/tc-i386.c:5878 +#, c-format +msgid "segment override on `%s' is ineffectual" +msgstr "" + -+#: config/tc-i386.c:5923 config/tc-i386.c:6017 config/tc-i386.c:6062 ++#: config/tc-i386.c:6694 config/tc-i386.c:6801 config/tc-i386.c:6858 +msgid "skipping prefixes on this instruction" +msgstr "" + -+#: config/tc-i386.c:6082 ++#: config/tc-i386.c:6878 +msgid "16-bit jump out of range" +msgstr "" + -+#: config/tc-i386.c:6091 ++#: config/tc-i386.c:6887 +#, c-format +msgid "can't handle non absolute segment in `%s'" +msgstr "" + -+#: config/tc-i386.c:6671 ++#: config/tc-i386.c:7515 config/tc-i386.c:7618 +#, c-format +msgid "@%s reloc is not supported with %d-bit output format" +msgstr "" + -+#: config/tc-i386.c:6719 ++#: config/tc-i386.c:7667 +#, c-format +msgid "missing or invalid expression `%s'" +msgstr "" + -+#: config/tc-i386.c:6776 ++#: config/tc-i386.c:7747 ++#, c-format ++msgid "Unsupported broadcast: `%s'" ++msgstr "" ++ ++#: config/tc-i386.c:7762 ++#, c-format ++msgid "`%s' can't be used for write mask" ++msgstr "" ++ ++#: config/tc-i386.c:7785 ++#, c-format ++msgid "invalid write mask `%s'" ++msgstr "" ++ ++#: config/tc-i386.c:7807 config/tc-i386.c:8439 ++#, c-format ++msgid "duplicated `%s'" ++msgstr "" ++ ++#: config/tc-i386.c:7817 ++#, c-format ++msgid "invalid zeroing-masking `%s'" ++msgstr "" ++ ++#: config/tc-i386.c:7830 ++#, c-format ++msgid "missing `}' in `%s'" ++msgstr "" ++ ++#. We don't know this one. ++#: config/tc-i386.c:7838 ++#, c-format ++msgid "unknown vector operation: `%s'" ++msgstr "" ++ ++#: config/tc-i386.c:7858 +#, c-format +msgid "at most %d immediate operands are allowed" +msgstr "" + -+#: config/tc-i386.c:6798 config/tc-i386.c:7045 ++#: config/tc-i386.c:7892 config/tc-i386.c:8141 +#, c-format +msgid "junk `%s' after expression" +msgstr "" + -+#: config/tc-i386.c:6819 ++#: config/tc-i386.c:7913 +#, c-format +msgid "missing or invalid immediate expression `%s'" +msgstr "" + -+#: config/tc-i386.c:6842 config/tc-i386.c:7135 ++#: config/tc-i386.c:7936 config/tc-i386.c:8231 +#, c-format +msgid "unimplemented segment %s in operand" +msgstr "" + -+#: config/tc-i386.c:6849 ++#: config/tc-i386.c:7943 +#, c-format +msgid "illegal immediate register operand %s" +msgstr "" + -+#: config/tc-i386.c:6897 ++#: config/tc-i386.c:7991 +#, c-format +msgid "expecting scale factor of 1, 2, 4, or 8: got `%s'" +msgstr "" + -+#: config/tc-i386.c:6906 ++#: config/tc-i386.c:8000 +#, c-format +msgid "scale factor of %d without an index register" +msgstr "" + -+#: config/tc-i386.c:6928 ++#: config/tc-i386.c:8022 +#, c-format +msgid "at most %d displacement operands are allowed" +msgstr "" + -+#: config/tc-i386.c:7101 ++#: config/tc-i386.c:8197 +#, c-format +msgid "missing or invalid displacement expression `%s'" +msgstr "" + -+#: config/tc-i386.c:7118 ++#: config/tc-i386.c:8214 +#, c-format +msgid "0x%lx out range of signed 32bit displacement" +msgstr "" + -+#: config/tc-i386.c:7222 ++#: config/tc-i386.c:8354 +#, c-format +msgid "`%s' is not valid here (expected `%c%s%s%c')" +msgstr "" + -+#: config/tc-i386.c:7306 ++#: config/tc-i386.c:8366 +#, c-format +msgid "`%s' is not a valid %s expression" +msgstr "" + -+#: config/tc-i386.c:7311 ++#: config/tc-i386.c:8452 +#, c-format -+msgid "`%s' is not a valid %s-bit %s expression" ++msgid "Missing '}': '%s'" +msgstr "" + -+#: config/tc-i386.c:7392 ++#: config/tc-i386.c:8458 ++#, c-format ++msgid "Junk after '}': '%s'" ++msgstr "" ++ ++#: config/tc-i386.c:8543 +#, c-format +msgid "bad memory operand `%s'" +msgstr "" + -+#: config/tc-i386.c:7407 ++#: config/tc-i386.c:8567 +#, c-format +msgid "junk `%s' after register" +msgstr "" + -+#: config/tc-i386.c:7420 config/tc-i386.c:7536 config/tc-i386.c:7577 ++#: config/tc-i386.c:8580 config/tc-i386.c:8714 config/tc-i386.c:8758 +#, c-format +msgid "bad register name `%s'" +msgstr "" + -+#: config/tc-i386.c:7428 ++#: config/tc-i386.c:8588 +msgid "immediate operand illegal with absolute jump" +msgstr "" + -+#: config/tc-i386.c:7450 ++#: config/tc-i386.c:8616 +#, c-format +msgid "too many memory references for `%s'" +msgstr "" + -+#: config/tc-i386.c:7528 ++#: config/tc-i386.c:8703 +#, c-format +msgid "expecting `,' or `)' after index register in `%s'" +msgstr "" + -+#: config/tc-i386.c:7553 ++#: config/tc-i386.c:8731 +#, c-format +msgid "expecting `)' after scale factor in `%s'" +msgstr "" + -+#: config/tc-i386.c:7561 ++#: config/tc-i386.c:8739 +#, c-format +msgid "expecting index register or scale factor after `,'; got '%c'" +msgstr "" + -+#: config/tc-i386.c:7569 ++#: config/tc-i386.c:8747 +#, c-format +msgid "expecting `,' or `)' after base register in `%s'" +msgstr "" + +#. It's not a memory operand; argh! -+#: config/tc-i386.c:7613 ++#: config/tc-i386.c:8794 +#, c-format +msgid "invalid char %s beginning operand %d `%s'" +msgstr "" + -+#: config/tc-i386.c:7791 ++#: config/tc-i386.c:8984 +msgid "long jump required" +msgstr "" + -+#: config/tc-i386.c:7846 ++#: config/tc-i386.c:9039 +msgid "jump target out of range" +msgstr "" + -+#: config/tc-i386.c:8360 ++#: config/tc-i386.c:9579 +msgid "no compiled in support for x86_64" +msgstr "" + -+#: config/tc-i386.c:8380 ++#: config/tc-i386.c:9599 +msgid "no compiled in support for 32bit x86_64" +msgstr "" + -+#: config/tc-i386.c:8384 ++#: config/tc-i386.c:9603 +msgid "32bit x86_64 is only supported for ELF" +msgstr "" + -+#: config/tc-i386.c:8414 config/tc-i386.c:8470 ++#: config/tc-i386.c:9633 config/tc-i386.c:9689 +#, c-format +msgid "invalid -march= option: `%s'" +msgstr "" + -+#: config/tc-i386.c:8479 config/tc-i386.c:8491 ++#: config/tc-i386.c:9698 config/tc-i386.c:9710 +#, c-format +msgid "invalid -mtune= option: `%s'" +msgstr "" + -+#: config/tc-i386.c:8500 ++#: config/tc-i386.c:9719 +#, c-format +msgid "invalid -mmnemonic= option: `%s'" +msgstr "" + -+#: config/tc-i386.c:8509 ++#: config/tc-i386.c:9728 +#, c-format +msgid "invalid -msyntax= option: `%s'" +msgstr "" + -+#: config/tc-i386.c:8536 ++#: config/tc-i386.c:9755 +#, c-format +msgid "invalid -msse-check= option: `%s'" +msgstr "" + -+#: config/tc-i386.c:8545 ++#: config/tc-i386.c:9766 ++#, c-format ++msgid "invalid -moperand-check= option: `%s'" ++msgstr "" ++ ++#: config/tc-i386.c:9775 +#, c-format +msgid "invalid -mavxscalar= option: `%s'" +msgstr "" + -+#: config/tc-i386.c:8637 ++#: config/tc-i386.c:9790 ++#, c-format ++msgid "invalid -mevexlig= option: `%s'" ++msgstr "" ++ ++#: config/tc-i386.c:9799 ++#, c-format ++msgid "invalid -mevexwig= option: `%s'" ++msgstr "" ++ ++#: config/tc-i386.c:9891 +#, c-format +msgid "" +" -Q ignored\n" @@ -832238,34 +837282,34 @@ index 0000000..f1eec3b +" -k ignored\n" +msgstr "" + -+#: config/tc-i386.c:8642 ++#: config/tc-i386.c:9896 +#, c-format +msgid "" +" -n Do not optimize code alignment\n" +" -q quieten some warnings\n" +msgstr "" + -+#: config/tc-i386.c:8646 ++#: config/tc-i386.c:9900 +#, c-format +msgid " -s ignored\n" +msgstr "" + -+#: config/tc-i386.c:8651 ++#: config/tc-i386.c:9905 +#, c-format +msgid " --32/--64/--x32 generate 32bit/64bit/x32 code\n" +msgstr "" + -+#: config/tc-i386.c:8655 ++#: config/tc-i386.c:9909 +#, c-format +msgid " --divide do not treat `/' as a comment character\n" +msgstr "" + -+#: config/tc-i386.c:8658 ++#: config/tc-i386.c:9912 +#, c-format +msgid " --divide ignored\n" +msgstr "" + -+#: config/tc-i386.c:8661 ++#: config/tc-i386.c:9915 +#, c-format +msgid "" +" -march=CPU[,+EXTENSION...]\n" @@ -832273,29 +837317,36 @@ index 0000000..f1eec3b +"of:\n" +msgstr "" + -+#: config/tc-i386.c:8665 ++#: config/tc-i386.c:9919 +#, c-format +msgid " EXTENSION is combination of:\n" +msgstr "" + -+#: config/tc-i386.c:8668 ++#: config/tc-i386.c:9922 +#, c-format +msgid " -mtune=CPU optimize for CPU, CPU is one of:\n" +msgstr "" + -+#: config/tc-i386.c:8671 ++#: config/tc-i386.c:9925 +#, c-format +msgid " -msse2avx encode SSE instructions with VEX prefix\n" +msgstr "" + -+#: config/tc-i386.c:8673 ++#: config/tc-i386.c:9927 +#, c-format +msgid "" +" -msse-check=[none|error|warning]\n" +" check SSE instructions\n" +msgstr "" + -+#: config/tc-i386.c:8676 ++#: config/tc-i386.c:9930 ++#, c-format ++msgid "" ++" -moperand-check=[none|error|warning]\n" ++" check operand combinations for validity\n" ++msgstr "" ++ ++#: config/tc-i386.c:9933 +#, c-format +msgid "" +" -mavxscalar=[128|256] encode scalar AVX instructions with specific " @@ -832303,68 +837354,93 @@ index 0000000..f1eec3b +" length\n" +msgstr "" + -+#: config/tc-i386.c:8679 ++#: config/tc-i386.c:9936 ++#, c-format ++msgid "" ++" -mevexlig=[128|256|512] encode scalar EVEX instructions with specific " ++"vector\n" ++" length\n" ++msgstr "" ++ ++#: config/tc-i386.c:9939 ++#, c-format ++msgid "" ++" -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W " ++"value\n" ++" for EVEX.W bit ignored instructions\n" ++msgstr "" ++ ++#: config/tc-i386.c:9942 +#, c-format +msgid " -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n" +msgstr "" + -+#: config/tc-i386.c:8681 ++#: config/tc-i386.c:9944 +#, c-format +msgid " -msyntax=[att|intel] use AT&T/Intel syntax\n" +msgstr "" + -+#: config/tc-i386.c:8683 ++#: config/tc-i386.c:9946 +#, c-format +msgid " -mindex-reg support pseudo index registers\n" +msgstr "" + -+#: config/tc-i386.c:8685 ++#: config/tc-i386.c:9948 +#, c-format +msgid " -mnaked-reg don't require `%%' prefix for registers\n" +msgstr "" + -+#: config/tc-i386.c:8687 ++#: config/tc-i386.c:9950 +#, c-format +msgid " -mold-gcc support old (<= 2.8.1) versions of gcc\n" +msgstr "" + -+#: config/tc-i386.c:8761 ++#: config/tc-i386.c:9952 ++#, c-format ++msgid " -madd-bnd-prefix add BND prefix for all valid branches\n" ++msgstr "" ++ ++#: config/tc-i386.c:10026 +msgid "Intel L1OM is 64bit only" +msgstr "" + -+#: config/tc-i386.c:8767 ++#: config/tc-i386.c:10032 +msgid "Intel K1OM is 64bit only" +msgstr "" + -+#: config/tc-i386.c:8984 ++#: config/tc-i386.c:10213 ++msgid "symbol size computation overflow" ++msgstr "" ++ ++#: config/tc-i386.c:10277 +#, c-format +msgid "can not do %d byte pc-relative relocation" +msgstr "" + -+#: config/tc-i386.c:9002 ++#: config/tc-i386.c:10298 +#, c-format +msgid "can not do %d byte relocation" +msgstr "" + -+#: config/tc-i386.c:9070 ++#: config/tc-i386.c:10366 +#, c-format +msgid "cannot represent relocation type %s in x32 mode" +msgstr "" + -+#: config/tc-i386.c:9105 config/tc-s390.c:2346 ++#: config/tc-i386.c:10402 config/tc-s390.c:2479 +#, c-format +msgid "cannot represent relocation type %s" +msgstr "" + -+#: config/tc-i386.c:9222 ++#: config/tc-i386.c:10519 +msgid "bad .section directive: want a,l,w,x,M,S,G,T in string" +msgstr "" + -+#: config/tc-i386.c:9225 ++#: config/tc-i386.c:10522 +msgid "bad .section directive: want a,w,x,M,S,G,T in string" +msgstr "" + -+#: config/tc-i386.c:9244 ++#: config/tc-i386.c:10541 +msgid ".largecomm supported only in 64bit mode, producing .comm" +msgstr "" + @@ -832388,8 +837464,8 @@ index 0000000..f1eec3b +msgid "Defective assembler. No assembly attempted." +msgstr "" + -+#: config/tc-i860.c:393 config/tc-i860.c:939 config/tc-m68k.c:3914 -+#: config/tc-m68k.c:3946 config/tc-sparc.c:2824 ++#: config/tc-i860.c:393 config/tc-i860.c:939 config/tc-m68k.c:3918 ++#: config/tc-m68k.c:3950 config/tc-sparc.c:2897 +msgid "failed sanity check." +msgstr "" + @@ -832628,592 +837704,608 @@ index 0000000..f1eec3b +msgid "No 'bal' entry point for leafproc %s" +msgstr "" + -+#: config/tc-ia64.c:864 ++#: config/tc-ia64.c:872 +msgid "bad .section directive: want a,o,s,w,x,M,S,G,T in string" +msgstr "" + -+#: config/tc-ia64.c:916 ++#: config/tc-ia64.c:924 +msgid "Size of frame exceeds maximum of 96 registers" +msgstr "" + -+#: config/tc-ia64.c:921 ++#: config/tc-ia64.c:929 +msgid "Size of rotating registers exceeds frame size" +msgstr "" + -+#: config/tc-ia64.c:1008 ++#: config/tc-ia64.c:1016 +msgid "Unwind directive not followed by an instruction." +msgstr "" + -+#: config/tc-ia64.c:1017 config/tc-ia64.c:7449 ++#: config/tc-ia64.c:1025 config/tc-ia64.c:7648 +msgid "qualifying predicate not followed by instruction" +msgstr "" + -+#: config/tc-ia64.c:1082 config/tc-ia64.c:1116 ++#: config/tc-ia64.c:1082 ++msgid "expected ',' after section name" ++msgstr "" ++ ++#: config/tc-ia64.c:1118 ++msgid "expected ',' after symbol name" ++msgstr "" ++ ++#: config/tc-ia64.c:1142 ++msgid "expected ',' after symbol size" ++msgstr "" ++ ++#: config/tc-ia64.c:1225 config/tc-ia64.c:1259 +msgid "record type is not valid" +msgstr "" + -+#: config/tc-ia64.c:1185 ++#: config/tc-ia64.c:1328 +msgid "Invalid record type for P3 format." +msgstr "" + -+#: config/tc-ia64.c:1221 ++#: config/tc-ia64.c:1364 +msgid "Invalid record type for format P6" +msgstr "" + -+#: config/tc-ia64.c:1401 config/tc-ia64.c:1453 ++#: config/tc-ia64.c:1544 config/tc-ia64.c:1596 +msgid "Invalid record type for format B1" +msgstr "" + -+#: config/tc-ia64.c:1486 ++#: config/tc-ia64.c:1629 +msgid "Invalid record type for format X1" +msgstr "" + -+#: config/tc-ia64.c:1528 ++#: config/tc-ia64.c:1671 +msgid "Invalid record type for format X3" +msgstr "" + -+#: config/tc-ia64.c:1566 ++#: config/tc-ia64.c:1709 +msgid "Previous .save incomplete" +msgstr "" + -+#: config/tc-ia64.c:2391 ++#: config/tc-ia64.c:2534 +msgid "spill_mask record unimplemented." +msgstr "" + -+#: config/tc-ia64.c:2448 ++#: config/tc-ia64.c:2591 +msgid "record_type_not_valid" +msgstr "" + -+#: config/tc-ia64.c:2533 ++#: config/tc-ia64.c:2676 +msgid "Ignoring attempt to spill beyond end of region" +msgstr "" + -+#: config/tc-ia64.c:2592 ++#: config/tc-ia64.c:2735 +msgid "Only constant space allocation is supported" +msgstr "" + -+#: config/tc-ia64.c:2606 ++#: config/tc-ia64.c:2749 +msgid "Only constant offsets are supported" +msgstr "" + -+#: config/tc-ia64.c:2629 ++#: config/tc-ia64.c:2772 +msgid "Section switching in code is not supported." +msgstr "" + -+#: config/tc-ia64.c:2671 ++#: config/tc-ia64.c:2814 +msgid " Insn slot not set in unwind record." +msgstr "" + -+#: config/tc-ia64.c:2745 ++#: config/tc-ia64.c:2888 +msgid "frgr_mem record before region record!" +msgstr "" + -+#: config/tc-ia64.c:2756 ++#: config/tc-ia64.c:2899 +msgid "fr_mem record before region record!" +msgstr "" + -+#: config/tc-ia64.c:2765 ++#: config/tc-ia64.c:2908 +msgid "gr_mem record before region record!" +msgstr "" + -+#: config/tc-ia64.c:2774 ++#: config/tc-ia64.c:2917 +msgid "br_mem record before region record!" +msgstr "" + -+#: config/tc-ia64.c:2784 ++#: config/tc-ia64.c:2927 +msgid "gr_gr record before region record!" +msgstr "" + -+#: config/tc-ia64.c:2792 ++#: config/tc-ia64.c:2935 +msgid "br_gr record before region record!" +msgstr "" + -+#: config/tc-ia64.c:2910 ++#: config/tc-ia64.c:3053 +#, c-format +msgid "First operand to .%s must be a predicate" +msgstr "" + -+#: config/tc-ia64.c:2914 ++#: config/tc-ia64.c:3057 +#, c-format +msgid "Pointless use of p0 as first operand to .%s" +msgstr "" + -+#: config/tc-ia64.c:2970 ++#: config/tc-ia64.c:3113 +#, c-format +msgid "Operand %d to .%s must be a preserved register" +msgstr "" + -+#: config/tc-ia64.c:3006 ++#: config/tc-ia64.c:3149 +#, c-format +msgid "Operand %d to .%s must be a writable register" +msgstr "" + -+#: config/tc-ia64.c:3031 ++#: config/tc-ia64.c:3174 +#, c-format +msgid "Radix `%s' unsupported or invalid" +msgstr "" + -+#: config/tc-ia64.c:3061 config/tc-ia64.c:3066 ++#: config/tc-ia64.c:3204 config/tc-ia64.c:3209 +#, c-format +msgid ".%s outside of %s" +msgstr "" + -+#: config/tc-ia64.c:3151 ++#: config/tc-ia64.c:3294 +msgid "Tags on unwind pseudo-ops aren't supported, yet" +msgstr "" + -+#: config/tc-ia64.c:3173 ++#: config/tc-ia64.c:3316 +msgid "First operand to .fframe must be a constant" +msgstr "" + -+#: config/tc-ia64.c:3193 ++#: config/tc-ia64.c:3336 +msgid "First operand to .vframe must be a general register" +msgstr "" + -+#: config/tc-ia64.c:3201 ++#: config/tc-ia64.c:3344 +msgid "Operand of .vframe contradicts .prologue" +msgstr "" + -+#: config/tc-ia64.c:3211 ++#: config/tc-ia64.c:3354 +msgid ".vframepsp is meaningless, assuming .vframesp was meant" +msgstr "" + -+#: config/tc-ia64.c:3219 ++#: config/tc-ia64.c:3362 +msgid "Operand to .vframesp must be a constant (sp-relative offset)" +msgstr "" + -+#: config/tc-ia64.c:3246 ++#: config/tc-ia64.c:3389 +msgid "First operand to .save not a register" +msgstr "" + -+#: config/tc-ia64.c:3252 ++#: config/tc-ia64.c:3395 +msgid "Second operand to .save not a valid register" +msgstr "" + -+#: config/tc-ia64.c:3283 config/tc-ia64.c:3294 config/tc-ia64.c:3302 ++#: config/tc-ia64.c:3426 config/tc-ia64.c:3437 config/tc-ia64.c:3445 +msgid "Second operand of .save contradicts .prologue" +msgstr "" + -+#: config/tc-ia64.c:3309 ++#: config/tc-ia64.c:3452 +msgid "First operand to .save not a valid register" +msgstr "" + -+#: config/tc-ia64.c:3327 ++#: config/tc-ia64.c:3470 +msgid "First operand to .restore must be stack pointer (sp)" +msgstr "" + -+#: config/tc-ia64.c:3336 ++#: config/tc-ia64.c:3479 +msgid "Second operand to .restore must be a constant >= 0" +msgstr "" + -+#: config/tc-ia64.c:3346 ++#: config/tc-ia64.c:3489 +#, c-format +msgid "Epilogue count of %lu exceeds number of nested prologues (%u)" +msgstr "" + -+#: config/tc-ia64.c:3433 ++#: config/tc-ia64.c:3576 +#, c-format +msgid "Illegal section name `%s' (causes unwind section name clash)" +msgstr "" + -+#: config/tc-ia64.c:3624 ++#: config/tc-ia64.c:3767 +msgid "First operand to .altrp not a valid branch register" +msgstr "" + -+#: config/tc-ia64.c:3653 ++#: config/tc-ia64.c:3796 +#, c-format +msgid "First operand to .%s not a register" +msgstr "" + -+#: config/tc-ia64.c:3658 ++#: config/tc-ia64.c:3801 +#, c-format +msgid "Second operand to .%s not a constant" +msgstr "" + -+#: config/tc-ia64.c:3725 ++#: config/tc-ia64.c:3868 +#, c-format +msgid "First operand to .%s not a valid register" +msgstr "" + -+#: config/tc-ia64.c:3748 ++#: config/tc-ia64.c:3891 +msgid "First operand to .save.g must be a positive 4-bit constant" +msgstr "" + -+#: config/tc-ia64.c:3761 ++#: config/tc-ia64.c:3904 +msgid "Second operand to .save.g must be a general register" +msgstr "" + -+#: config/tc-ia64.c:3766 ++#: config/tc-ia64.c:3909 +#, c-format +msgid "Second operand to .save.g must be the first of %d general registers" +msgstr "" + -+#: config/tc-ia64.c:3789 ++#: config/tc-ia64.c:3932 +msgid "Operand to .save.f must be a positive 20-bit constant" +msgstr "" + -+#: config/tc-ia64.c:3812 ++#: config/tc-ia64.c:3955 +msgid "First operand to .save.b must be a positive 5-bit constant" +msgstr "" + -+#: config/tc-ia64.c:3825 ++#: config/tc-ia64.c:3968 +msgid "Second operand to .save.b must be a general register" +msgstr "" + -+#: config/tc-ia64.c:3830 ++#: config/tc-ia64.c:3973 +#, c-format +msgid "Second operand to .save.b must be the first of %d general registers" +msgstr "" + -+#: config/tc-ia64.c:3856 ++#: config/tc-ia64.c:3999 +msgid "First operand to .save.gf must be a non-negative 4-bit constant" +msgstr "" + -+#: config/tc-ia64.c:3864 ++#: config/tc-ia64.c:4007 +msgid "Second operand to .save.gf must be a non-negative 20-bit constant" +msgstr "" + -+#: config/tc-ia64.c:3872 ++#: config/tc-ia64.c:4015 +msgid "Operands to .save.gf may not be both zero" +msgstr "" + -+#: config/tc-ia64.c:3889 ++#: config/tc-ia64.c:4032 +msgid "Operand to .spill must be a constant" +msgstr "" + -+#: config/tc-ia64.c:3958 ++#: config/tc-ia64.c:4101 +#, c-format +msgid "Operand %d to .%s must be a constant" +msgstr "" + -+#: config/tc-ia64.c:3979 ++#: config/tc-ia64.c:4122 +#, c-format +msgid "Missing .label_state %ld" +msgstr "" + -+#: config/tc-ia64.c:4033 ++#: config/tc-ia64.c:4176 +msgid "Operand to .label_state must be a constant" +msgstr "" + -+#: config/tc-ia64.c:4052 ++#: config/tc-ia64.c:4195 +msgid "Operand to .copy_state must be a constant" +msgstr "" + -+#: config/tc-ia64.c:4075 ++#: config/tc-ia64.c:4218 +msgid "First operand to .unwabi must be a constant" +msgstr "" + -+#: config/tc-ia64.c:4081 ++#: config/tc-ia64.c:4224 +msgid "Second operand to .unwabi must be a constant" +msgstr "" + -+#: config/tc-ia64.c:4116 ++#: config/tc-ia64.c:4259 +msgid "Missing .endp after previous .proc" +msgstr "" + -+#: config/tc-ia64.c:4135 ++#: config/tc-ia64.c:4278 +msgid "Empty argument of .proc" +msgstr "" + -+#: config/tc-ia64.c:4140 ++#: config/tc-ia64.c:4283 +#, c-format +msgid "`%s' was already defined" +msgstr "" + -+#: config/tc-ia64.c:4183 ++#: config/tc-ia64.c:4326 +msgid "Initial .body should precede any instructions" +msgstr "" + -+#: config/tc-ia64.c:4202 ++#: config/tc-ia64.c:4345 +msgid ".prologue within prologue" +msgstr "" + -+#: config/tc-ia64.c:4207 ++#: config/tc-ia64.c:4350 +msgid "Initial .prologue should precede any instructions" +msgstr "" + -+#: config/tc-ia64.c:4217 ++#: config/tc-ia64.c:4360 +msgid "First operand to .prologue must be a positive 4-bit constant" +msgstr "" + -+#: config/tc-ia64.c:4219 ++#: config/tc-ia64.c:4362 +msgid "Pointless use of zero first operand to .prologue" +msgstr "" + -+#: config/tc-ia64.c:4233 ++#: config/tc-ia64.c:4376 +msgid "Using a constant as second operand to .prologue is deprecated" +msgstr "" + -+#: config/tc-ia64.c:4239 ++#: config/tc-ia64.c:4382 +msgid "Second operand to .prologue must be a general register" +msgstr "" + -+#: config/tc-ia64.c:4244 ++#: config/tc-ia64.c:4387 +#, c-format +msgid "Second operand to .prologue must be the first of %d general registers" +msgstr "" + -+#: config/tc-ia64.c:4356 ++#: config/tc-ia64.c:4499 +#, c-format +msgid "`%s' was not defined within procedure" +msgstr "" + -+#: config/tc-ia64.c:4394 ++#: config/tc-ia64.c:4537 +msgid "Empty argument of .endp" +msgstr "" + -+#: config/tc-ia64.c:4408 ++#: config/tc-ia64.c:4551 +#, c-format +msgid "`%s' was not specified with previous .proc" +msgstr "" + -+#: config/tc-ia64.c:4423 ++#: config/tc-ia64.c:4566 +#, c-format +msgid "`%s' should be an operand to this .endp" +msgstr "" + -+#: config/tc-ia64.c:4464 config/tc-ia64.c:4802 config/tc-ia64.c:5109 ++#: config/tc-ia64.c:4607 config/tc-ia64.c:4945 config/tc-ia64.c:5252 +msgid "Comma expected" +msgstr "" + -+#: config/tc-ia64.c:4505 ++#: config/tc-ia64.c:4648 +msgid "Expected '['" +msgstr "" + -+#: config/tc-ia64.c:4514 config/tc-ia64.c:7584 ++#: config/tc-ia64.c:4657 config/tc-ia64.c:7783 +msgid "Expected ']'" +msgstr "" + -+#: config/tc-ia64.c:4519 ++#: config/tc-ia64.c:4662 +msgid "Number of elements must be positive" +msgstr "" + -+#: config/tc-ia64.c:4530 ++#: config/tc-ia64.c:4673 +#, c-format +msgid "Used more than the declared %d rotating registers" +msgstr "" + -+#: config/tc-ia64.c:4538 ++#: config/tc-ia64.c:4681 +msgid "Used more than the available 96 rotating registers" +msgstr "" + -+#: config/tc-ia64.c:4545 ++#: config/tc-ia64.c:4688 +msgid "Used more than the available 48 rotating registers" +msgstr "" + -+#: config/tc-ia64.c:4573 ++#: config/tc-ia64.c:4716 +#, c-format +msgid "Attempt to redefine register set `%s'" +msgstr "" + -+#: config/tc-ia64.c:4639 ++#: config/tc-ia64.c:4782 +#, c-format +msgid "Unknown psr option `%s'" +msgstr "" + -+#: config/tc-ia64.c:4687 ++#: config/tc-ia64.c:4830 +msgid "Missing section name" +msgstr "" + -+#: config/tc-ia64.c:4697 ++#: config/tc-ia64.c:4840 +msgid "Comma expected after section name" +msgstr "" + -+#: config/tc-ia64.c:4708 ++#: config/tc-ia64.c:4851 +msgid "Creating sections with .xdataN/.xrealN/.xstringZ is deprecated." +msgstr "" + -+#: config/tc-ia64.c:4797 ++#: config/tc-ia64.c:4940 +msgid "Register name expected" +msgstr "" + -+#: config/tc-ia64.c:4810 ++#: config/tc-ia64.c:4953 +msgid "Register value annotation ignored" +msgstr "" + -+#: config/tc-ia64.c:4849 ++#: config/tc-ia64.c:4992 +msgid "Directive invalid within a bundle" +msgstr "" + -+#: config/tc-ia64.c:4940 ++#: config/tc-ia64.c:5083 +msgid "Missing predicate relation type" +msgstr "" + -+#: config/tc-ia64.c:4946 ++#: config/tc-ia64.c:5089 +msgid "Unrecognized predicate relation type" +msgstr "" + -+#: config/tc-ia64.c:4992 ++#: config/tc-ia64.c:5135 +msgid "Bad register range" +msgstr "" + -+#: config/tc-ia64.c:5001 config/tc-ia64.c:7529 ++#: config/tc-ia64.c:5144 config/tc-ia64.c:7728 +msgid "Predicate register expected" +msgstr "" + -+#: config/tc-ia64.c:5006 ++#: config/tc-ia64.c:5149 +msgid "Duplicate predicate register ignored" +msgstr "" + -+#: config/tc-ia64.c:5022 ++#: config/tc-ia64.c:5165 +msgid "Predicate source and target required" +msgstr "" + -+#: config/tc-ia64.c:5024 config/tc-ia64.c:5036 ++#: config/tc-ia64.c:5167 config/tc-ia64.c:5179 +msgid "Use of p0 is not valid in this context" +msgstr "" + -+#: config/tc-ia64.c:5031 ++#: config/tc-ia64.c:5174 +msgid "At least two PR arguments expected" +msgstr "" + -+#: config/tc-ia64.c:5045 ++#: config/tc-ia64.c:5188 +msgid "At least one PR argument expected" +msgstr "" + -+#: config/tc-ia64.c:5080 ++#: config/tc-ia64.c:5223 +#, c-format +msgid "Inserting \"%s\" into entry hint table failed: %s" +msgstr "" + +#. FIXME -- need 62-bit relocation type -+#: config/tc-ia64.c:5548 ++#: config/tc-ia64.c:5702 +msgid "62-bit relocation not yet implemented" +msgstr "" + +#. XXX technically, this is wrong: we should not be issuing warning +#. messages until we're sure this instruction pattern is going to +#. be used! -+#: config/tc-ia64.c:5632 ++#: config/tc-ia64.c:5788 +msgid "lower 16 bits of mask ignored" +msgstr "" + -+#: config/tc-ia64.c:5946 ++#: config/tc-ia64.c:6017 ++msgid "stride must be a multiple of 64; lower 6 bits ignored" ++msgstr "" ++ ++#: config/tc-ia64.c:6135 +msgid "Expected separator `='" +msgstr "" + -+#: config/tc-ia64.c:5980 ++#: config/tc-ia64.c:6169 +msgid "Duplicate equal sign (=) in instruction" +msgstr "" + -+#: config/tc-ia64.c:5987 ++#: config/tc-ia64.c:6176 +#, c-format +msgid "Illegal operand separator `%c'" +msgstr "" + -+#: config/tc-ia64.c:6102 ++#: config/tc-ia64.c:6291 +#, c-format +msgid "Operand %u of `%s' should be %s" +msgstr "" + -+#: config/tc-ia64.c:6106 ++#: config/tc-ia64.c:6295 +msgid "Wrong number of output operands" +msgstr "" + -+#: config/tc-ia64.c:6108 ++#: config/tc-ia64.c:6297 +msgid "Wrong number of input operands" +msgstr "" + -+#: config/tc-ia64.c:6110 ++#: config/tc-ia64.c:6299 +msgid "Operand mismatch" +msgstr "" + -+#: config/tc-ia64.c:6192 ++#: config/tc-ia64.c:6381 +#, c-format +msgid "Invalid use of `%c%d' as output operand" +msgstr "" + -+#: config/tc-ia64.c:6195 ++#: config/tc-ia64.c:6384 +#, c-format +msgid "Invalid use of `r%d' as base update address operand" +msgstr "" + -+#: config/tc-ia64.c:6219 ++#: config/tc-ia64.c:6408 +#, c-format +msgid "Invalid duplicate use of `%c%d'" +msgstr "" + -+#: config/tc-ia64.c:6226 ++#: config/tc-ia64.c:6415 +#, c-format +msgid "Invalid simultaneous use of `f%d' and `f%d'" +msgstr "" + -+#: config/tc-ia64.c:6232 ++#: config/tc-ia64.c:6421 +#, c-format +msgid "Dangerous simultaneous use of `f%d' and `f%d'" +msgstr "" + -+#: config/tc-ia64.c:6276 ++#: config/tc-ia64.c:6465 +msgid "Value truncated to 62 bits" +msgstr "" + -+#: config/tc-ia64.c:6339 ++#: config/tc-ia64.c:6533 +#, c-format +msgid "Bad operand value: %s" +msgstr "" + +#. Give an error if a frag containing code is not aligned to a 16 byte +#. boundary. -+#: config/tc-ia64.c:6414 config/tc-ia64.h:177 ++#: config/tc-ia64.c:6608 config/tc-ia64.h:177 +msgid "instruction address is not a multiple of 16" +msgstr "" + -+#: config/tc-ia64.c:6482 ++#: config/tc-ia64.c:6676 +#, c-format +msgid "`%s' must be last in bundle" +msgstr "" + -+#: config/tc-ia64.c:6514 ++#: config/tc-ia64.c:6708 +#, c-format +msgid "Internal error: don't know how to force %s to end of instruction group" +msgstr "" + -+#: config/tc-ia64.c:6527 ++#: config/tc-ia64.c:6721 +#, c-format +msgid "`%s' must be last in instruction group" +msgstr "" + -+#: config/tc-ia64.c:6557 ++#: config/tc-ia64.c:6751 +msgid "Label must be first in a bundle" +msgstr "" + -+#: config/tc-ia64.c:6634 ++#: config/tc-ia64.c:6828 +msgid "hint in B unit may be treated as nop" +msgstr "" + -+#: config/tc-ia64.c:6645 ++#: config/tc-ia64.c:6839 +msgid "hint in B unit can't be used" +msgstr "" + -+#: config/tc-ia64.c:6659 ++#: config/tc-ia64.c:6853 +msgid "emit_one_bundle: unexpected dynamic op" +msgstr "" + -+#: config/tc-ia64.c:6782 ++#: config/tc-ia64.c:6978 +#, c-format +msgid "`%s' does not fit into %s template" +msgstr "" + -+#: config/tc-ia64.c:6797 ++#: config/tc-ia64.c:6993 +#, c-format +msgid "`%s' does not fit into bundle" +msgstr "" + -+#: config/tc-ia64.c:6809 ++#: config/tc-ia64.c:7005 +#, c-format +msgid "`%s' can't go in %s of %s template" +msgstr "" + -+#: config/tc-ia64.c:6815 ++#: config/tc-ia64.c:7011 +msgid "Missing '}' at end of file" +msgstr "" + -+#: config/tc-ia64.c:6962 ++#: config/tc-ia64.c:7158 +#, c-format +msgid "Unrecognized option '-x%s'" +msgstr "" + -+#: config/tc-ia64.c:6989 ++#: config/tc-ia64.c:7185 +msgid "" +"IA-64 options:\n" +" --mconstant-gp\t mark output file as using the constant-GP model\n" @@ -833233,7 +838325,7 @@ index 0000000..f1eec3b +msgstr "" + +#. Note for translators: "automagically" can be translated as "automatically" here. -+#: config/tc-ia64.c:7006 ++#: config/tc-ia64.c:7202 +msgid "" +" -xauto\t\t automagically remove dependency violations (default)\n" +" -xnone\t\t turn off dependency violation checking\n" @@ -833244,239 +838336,234 @@ index 0000000..f1eec3b +"\t\t\t dependency violation checking\n" +msgstr "" + -+#: config/tc-ia64.c:7021 ++#: config/tc-ia64.c:7217 +msgid "--gstabs is not supported for ia64" +msgstr "" + -+#: config/tc-ia64.c:7259 ++#: config/tc-ia64.c:7455 +#, c-format +msgid "ia64.md_begin: can't hash `%s': %s" +msgstr "" + -+#: config/tc-ia64.c:7320 ++#: config/tc-ia64.c:7519 +#, c-format +msgid "Inserting \"%s\" into constant hash table failed: %s" +msgstr "" + -+#: config/tc-ia64.c:7332 config/tc-mips.c:2310 ++#: config/tc-ia64.c:7531 config/tc-tilegx.c:263 +msgid "Could not set architecture and machine" +msgstr "" + -+#: config/tc-ia64.c:7464 ++#: config/tc-ia64.c:7663 +msgid "Explicit stops are ignored in auto mode" +msgstr "" + -+#: config/tc-ia64.c:7473 ++#: config/tc-ia64.c:7672 +msgid "Found '{' when manual bundling is already turned on" +msgstr "" + -+#: config/tc-ia64.c:7486 ++#: config/tc-ia64.c:7685 +msgid "Found '{' after explicit switch to automatic mode" +msgstr "" + -+#: config/tc-ia64.c:7492 ++#: config/tc-ia64.c:7691 +msgid "Found '}' when manual bundling is off" +msgstr "" + -+#: config/tc-ia64.c:7519 ++#: config/tc-ia64.c:7718 +msgid "Expected ')'" +msgstr "" + -+#: config/tc-ia64.c:7524 ++#: config/tc-ia64.c:7723 +msgid "Qualifying predicate expected" +msgstr "" + -+#: config/tc-ia64.c:7543 ++#: config/tc-ia64.c:7742 +msgid "Tag must come before qualifying predicate." +msgstr "" + -+#: config/tc-ia64.c:7573 ++#: config/tc-ia64.c:7772 +msgid "Expected ':'" +msgstr "" + -+#: config/tc-ia64.c:7589 ++#: config/tc-ia64.c:7788 +msgid "Tag name expected" +msgstr "" + -+#: config/tc-ia64.c:7691 ++#: config/tc-ia64.c:7890 +msgid "Rotating register index must be a non-negative constant" +msgstr "" + -+#: config/tc-ia64.c:7696 ++#: config/tc-ia64.c:7895 +#, c-format +msgid "Index out of range 0..%u" +msgstr "" + -+#: config/tc-ia64.c:7708 ++#: config/tc-ia64.c:7907 +msgid "Indirect register index must be a general register" +msgstr "" + -+#: config/tc-ia64.c:7717 ++#: config/tc-ia64.c:7916 +msgid "Index can only be applied to rotating or indirect registers" +msgstr "" + -+#: config/tc-ia64.c:7753 config/tc-xstormy16.c:146 ++#: config/tc-ia64.c:7952 config/tc-xstormy16.c:146 +msgid "Expected '('" +msgstr "" + -+#: config/tc-ia64.c:7761 config/tc-pdp11.c:448 config/tc-pdp11.c:512 -+#: config/tc-pdp11.c:546 config/tc-tilegx.c:991 config/tc-tilepro.c:860 ++#: config/tc-ia64.c:7960 config/tc-pdp11.c:448 config/tc-pdp11.c:512 ++#: config/tc-pdp11.c:546 config/tc-tilegx.c:1046 config/tc-tilepro.c:938 +#: config/tc-xstormy16.c:155 +msgid "Missing ')'" +msgstr "" + -+#: config/tc-ia64.c:7779 config/tc-xstormy16.c:162 ++#: config/tc-ia64.c:7978 config/tc-xstormy16.c:162 +msgid "Not a symbolic expression" +msgstr "" + -+#: config/tc-ia64.c:7784 config/tc-ia64.c:7798 ++#: config/tc-ia64.c:7983 config/tc-ia64.c:7997 +msgid "Illegal combination of relocation functions" +msgstr "" + -+#: config/tc-ia64.c:7887 ++#: config/tc-ia64.c:8086 +msgid "No current frame" +msgstr "" + -+#: config/tc-ia64.c:7889 -+#, c-format -+msgid "Register number out of range 0..%u" -+msgstr "" -+ -+#: config/tc-ia64.c:7927 -+msgid "Standalone `#' is illegal" -+msgstr "" -+ -+#: config/tc-ia64.c:7930 -+msgid "Redundant `#' suffix operators" -+msgstr "" -+ +#: config/tc-ia64.c:8088 +#, c-format ++msgid "Register number out of range 0..%u" ++msgstr "" ++ ++#: config/tc-ia64.c:8126 ++msgid "Standalone `#' is illegal" ++msgstr "" ++ ++#: config/tc-ia64.c:8129 ++msgid "Redundant `#' suffix operators" ++msgstr "" ++ ++#: config/tc-ia64.c:8287 ++#, c-format +msgid "Unhandled dependency %s for %s (%s), note %d" +msgstr "" + -+#: config/tc-ia64.c:9383 ++#: config/tc-ia64.c:9599 +#, c-format +msgid "Unrecognized dependency specifier %d\n" +msgstr "" + -+#: config/tc-ia64.c:10259 ++#: config/tc-ia64.c:10475 +msgid "Only the first path encountering the conflict is reported" +msgstr "" + -+#: config/tc-ia64.c:10261 ++#: config/tc-ia64.c:10477 +msgid "This is the location of the conflicting usage" +msgstr "" + -+#: config/tc-ia64.c:10522 ++#: config/tc-ia64.c:10738 +#, c-format +msgid "Unknown opcode `%s'" +msgstr "" + -+#: config/tc-ia64.c:10600 ++#: config/tc-ia64.c:10816 +#, c-format +msgid "AR %d can only be accessed by %c-unit" +msgstr "" + -+#: config/tc-ia64.c:10612 ++#: config/tc-ia64.c:10828 +msgid "hint.b may be treated as nop" +msgstr "" + -+#: config/tc-ia64.c:10615 ++#: config/tc-ia64.c:10831 +msgid "hint.b shouldn't be used" +msgstr "" + -+#: config/tc-ia64.c:10654 ++#: config/tc-ia64.c:10870 +#, c-format +msgid "`%s' cannot be predicated" +msgstr "" + -+#: config/tc-ia64.c:10726 ++#: config/tc-ia64.c:10942 +msgid "Closing bracket missing" +msgstr "" + -+#: config/tc-ia64.c:10735 ++#: config/tc-ia64.c:10951 +msgid "Index must be a general register" +msgstr "" + -+#: config/tc-ia64.c:10900 ++#: config/tc-ia64.c:11116 +#, c-format +msgid "Unsupported fixup size %d" +msgstr "" + +#. This should be an error, but since previously there wasn't any +#. diagnostic here, don't make it fail because of this for now. -+#: config/tc-ia64.c:11172 ++#: config/tc-ia64.c:11388 +#, c-format +msgid "Cannot express %s%d%s relocation" +msgstr "" + -+#: config/tc-ia64.c:11191 ++#: config/tc-ia64.c:11407 +msgid "No addend allowed in @fptr() relocation" +msgstr "" + -+#: config/tc-ia64.c:11230 ++#: config/tc-ia64.c:11446 +msgid "integer operand out of range" +msgstr "" + -+#: config/tc-ia64.c:11297 ++#: config/tc-ia64.c:11513 +#, c-format +msgid "%s must have a constant value" +msgstr "" + -+#: config/tc-ia64.c:11317 ++#: config/tc-ia64.c:11533 +msgid "cannot resolve @slotcount parameter" +msgstr "" + -+#: config/tc-ia64.c:11350 ++#: config/tc-ia64.c:11566 +msgid "invalid @slotcount value" +msgstr "" + -+#: config/tc-ia64.c:11387 config/tc-z8k.c:1372 ++#: config/tc-ia64.c:11603 config/tc-z8k.c:1371 +#, c-format +msgid "Cannot represent %s relocation in object file" +msgstr "" + -+#: config/tc-ia64.c:11498 ++#: config/tc-ia64.c:11714 +msgid "Can't add stop bit to mark end of instruction group" +msgstr "" + -+#: config/tc-ia64.c:11598 config/tc-score.c:6105 read.c:1448 read.c:2434 -+#: read.c:3137 read.c:3475 read.c:3519 -+msgid "expected symbol name" -+msgstr "" -+ -+#: config/tc-ia64.c:11608 read.c:2444 read.c:3147 read.c:3503 stabs.c:469 ++#: config/tc-ia64.c:11824 read.c:2540 read.c:3234 read.c:3571 stabs.c:469 +#, c-format +msgid "expected comma after \"%s\"" +msgstr "" + -+#: config/tc-ia64.c:11650 ++#: config/tc-ia64.c:11866 +#, c-format +msgid "`%s' is already the alias of %s `%s'" +msgstr "" + -+#: config/tc-ia64.c:11660 ++#: config/tc-ia64.c:11876 +#, c-format +msgid "%s `%s' already has an alias `%s'" +msgstr "" + -+#: config/tc-ia64.c:11671 ++#: config/tc-ia64.c:11887 +#, c-format +msgid "inserting \"%s\" into %s alias hash table failed: %s" +msgstr "" + -+#: config/tc-ia64.c:11679 ++#: config/tc-ia64.c:11895 +#, c-format +msgid "inserting \"%s\" into %s name hash table failed: %s" +msgstr "" + -+#: config/tc-ia64.c:11705 ++#: config/tc-ia64.c:11921 +#, c-format +msgid "symbol `%s' aliased to `%s' is not used" +msgstr "" + -+#: config/tc-ia64.c:11728 ++#: config/tc-ia64.c:11944 +#, c-format +msgid "section `%s' aliased to `%s' is not used" +msgstr "" @@ -833520,19 +838607,19 @@ index 0000000..f1eec3b +msgid "Unmatched high relocation" +msgstr "" + -+#: config/tc-iq2000.c:829 config/tc-mips.c:18680 config/tc-score.c:5815 ++#: config/tc-iq2000.c:829 config/tc-mips.c:17570 config/tc-score.c:5815 +msgid ".end not in text section" +msgstr "" + -+#: config/tc-iq2000.c:833 config/tc-mips.c:18684 config/tc-score.c:5818 ++#: config/tc-iq2000.c:833 config/tc-score.c:5818 +msgid ".end directive without a preceding .ent directive." +msgstr "" + -+#: config/tc-iq2000.c:842 config/tc-mips.c:18693 config/tc-score.c:5826 ++#: config/tc-iq2000.c:842 config/tc-score.c:5826 +msgid ".end symbol does not match .ent symbol." +msgstr "" + -+#: config/tc-iq2000.c:845 config/tc-mips.c:18700 config/tc-score.c:5831 ++#: config/tc-iq2000.c:845 config/tc-mips.c:17590 config/tc-score.c:5831 +msgid ".end directive missing or unknown symbol" +msgstr "" + @@ -833540,7 +838627,7 @@ index 0000000..f1eec3b +msgid "Expected simple number." +msgstr "" + -+#: config/tc-iq2000.c:892 config/tc-mips.c:18605 config/tc-score.c:5667 ++#: config/tc-iq2000.c:892 config/tc-mips.c:17495 config/tc-score.c:5667 +#, c-format +msgid " *input_line_pointer == '%c' 0x%02x\n" +msgstr "" @@ -833549,7 +838636,7 @@ index 0000000..f1eec3b +msgid "Invalid number" +msgstr "" + -+#: config/tc-iq2000.c:928 config/tc-mips.c:18772 config/tc-score.c:5705 ++#: config/tc-iq2000.c:928 config/tc-score.c:5705 +msgid ".ent or .aent not in text section." +msgstr "" + @@ -833557,7 +838644,7 @@ index 0000000..f1eec3b +msgid "missing `.end'" +msgstr "" + -+#: config/tc-lm32.c:237 config/tc-moxie.c:575 ++#: config/tc-lm32.c:236 config/tc-moxie.c:579 config/tc-nios2.c:283 +msgid "bad call to md_atof" +msgstr "" + @@ -833571,7 +838658,7 @@ index 0000000..f1eec3b +msgid "Unrecognised option: -hidden" +msgstr "" + -+#: config/tc-m32r.c:358 config/tc-sparc.c:610 ++#: config/tc-m32r.c:358 config/tc-sparc.c:619 +msgid "Unrecognized option following -K" +msgstr "" + @@ -833792,8 +838879,8 @@ index 0000000..f1eec3b +msgid "Length of .scomm \"%s\" is already %ld. Not changed to %ld." +msgstr "" + -+#: config/tc-m32r.c:1930 config/tc-m32r.c:1983 config/tc-sh.c:775 -+#: config/tc-sh.c:2456 ++#: config/tc-m32r.c:1930 config/tc-m32r.c:1983 config/tc-nds32.c:4060 ++#: config/tc-nds32.c:4092 config/tc-sh.c:775 config/tc-sh.c:2455 +msgid "Invalid PIC expression." +msgstr "" + @@ -833801,12 +838888,13 @@ index 0000000..f1eec3b +msgid "Unmatched high/shigh reloc" +msgstr "" + -+#: config/tc-m68hc11.c:371 ++#: config/tc-m68hc11.c:418 +#, c-format +msgid "" +"Motorola 68HC11/68HC12/68HCS12 options:\n" +" -m68hc11 | -m68hc12 |\n" -+" -m68hcs12 specify the processor [default %s]\n" ++" -m68hcs12 | -mm9s12x |\n" ++" -mm9s12xg specify the processor [default %s]\n" +" -mshort use 16-bit int ABI (default)\n" +" -mlong use 32-bit int ABI\n" +" -mshort-double use 32-bit double ABI\n" @@ -833818,60 +838906,81 @@ index 0000000..f1eec3b +" when the instruction does not support direct mode\n" +" --print-insn-syntax print the syntax of instruction in case of error\n" +" --print-opcodes print the list of instructions with syntax\n" ++" --xgate-ramoffset offset ram addresses by 0xc000\n" +" --generate-example generate an example of each instruction\n" +" (used for testing)\n" +msgstr "" + -+#: config/tc-m68hc11.c:417 ++#: config/tc-m68hc11.c:466 config/tc-xgate.c:285 +#, c-format +msgid "Default target `%s' is not supported." +msgstr "" + +#. Dump the opcode statistics table. -+#: config/tc-m68hc11.c:435 ++#: config/tc-m68hc11.c:484 +#, c-format +msgid "Name # Modes Min ops Max ops Modes mask # Used\n" +msgstr "" + -+#: config/tc-m68hc11.c:501 ++#: config/tc-m68hc11.c:563 +#, c-format +msgid "Option `%s' is not recognized." +msgstr "" + -+#: config/tc-m68hc11.c:671 ++#: config/tc-m68hc11.c:753 ++msgid "imm3" ++msgstr "" ++ ++#: config/tc-m68hc11.c:761 ++msgid "RD" ++msgstr "" ++ ++#: config/tc-m68hc11.c:769 ++msgid "RD,RS" ++msgstr "" ++ ++#: config/tc-m68hc11.c:777 ++msgid "RI, #imm4" ++msgstr "" ++ ++#: config/tc-m68hc11.c:809 ++msgid "RD, (RI,#offs5)" ++msgstr "" ++ ++#: config/tc-m68hc11.c:861 +msgid "#" +msgstr "" + -+#: config/tc-m68hc11.c:680 ++#: config/tc-m68hc11.c:870 +msgid "#" +msgstr "" + -+#: config/tc-m68hc11.c:689 config/tc-m68hc11.c:698 ++#: config/tc-m68hc11.c:879 config/tc-m68hc11.c:888 +msgid ",X" +msgstr "" + -+#: config/tc-m68hc11.c:725 ++#: config/tc-m68hc11.c:915 +msgid "*" +msgstr "" + -+#: config/tc-m68hc11.c:737 ++#: config/tc-m68hc11.c:927 +msgid "#" +msgstr "" + -+#: config/tc-m68hc11.c:747 ++#: config/tc-m68hc11.c:937 +#, c-format +msgid "symbol%d" +msgstr "" + -+#: config/tc-m68hc11.c:749 ++#: config/tc-m68hc11.c:939 +msgid "" +msgstr "" + -+#: config/tc-m68hc11.c:768 ++#: config/tc-m68hc11.c:958 +msgid "

: ++ 0: cf 93 push r28 ++ 2: df 93 push r29 ++ 4: cd b7 in r28, 0x3d ; 61 ++ 6: de b7 in r29, 0x3e ; 62 ++ 8: c4 92 xch Z, r12 ++ a: c5 92 las Z, r12 ++ c: c6 92 lac Z, r12 ++ e: c7 92 lat Z, r12 ++ 10: 80 e0 ldi r24, 0x00 ; 0 ++ 12: 90 e0 ldi r25, 0x00 ; 0 ++ 14: df 91 pop r29 ++ 16: cf 91 pop r28 ++ 18: 08 95 ret +diff --git a/gas/testsuite/gas/avr/rmw.s b/gas/testsuite/gas/avr/rmw.s +new file mode 100644 +index 0000000..fca39c9 +--- /dev/null ++++ b/gas/testsuite/gas/avr/rmw.s +@@ -0,0 +1,32 @@ ++ .file "rmw.s" ++__SP_H__ = 0x3e ++__SP_L__ = 0x3d ++__SREG__ = 0x3f ++__CCP__ = 0x34 ++__tmp_reg__ = 0 ++__zero_reg__ = 1 ++ .text ++.global main ++ .type main, @function ++main: ++ push r28 ++ push r29 ++ in r28,__SP_L__ ++ in r29,__SP_H__ ++/* prologue: function */ ++/* frame size = 0 */ ++/* stack size = 2 */ ++.L__stack_usage = 2 ++/* #APP */ ++ xch Z, r12 ++ las Z, r12 ++ lac Z, r12 ++ lat Z, r12 ++/* #NOAPP */ ++ ldi r24,0 ++ ldi r25,0 ++/* epilogue start */ ++ pop r29 ++ pop r28 ++ ret ++ .size main, .-main diff --git a/gas/testsuite/gas/bfin/allinsn16.d b/gas/testsuite/gas/bfin/allinsn16.d new file mode 100644 index 0000000..1ffe890 @@ -1088158,12 +1095342,11 @@ index 0000000..74ddc4e + diff --git a/gas/testsuite/gas/bfin/bfin.exp b/gas/testsuite/gas/bfin/bfin.exp new file mode 100644 -index 0000000..93f1a3d +index 0000000..c771923 --- /dev/null +++ b/gas/testsuite/gas/bfin/bfin.exp -@@ -0,0 +1,68 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,67 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1089345,12 +1096528,11 @@ index 0000000..50648cc +CC = ! CC ; /* (a) */ diff --git a/gas/testsuite/gas/bfin/error.exp b/gas/testsuite/gas/bfin/error.exp new file mode 100644 -index 0000000..a0a0331 +index 0000000..be5995e --- /dev/null +++ b/gas/testsuite/gas/bfin/error.exp -@@ -0,0 +1,27 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,26 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1097240,10 +1104422,10 @@ index 0000000..a4ff135 + .cfi_endproc diff --git a/gas/testsuite/gas/cfi/cfi-arm-1.d b/gas/testsuite/gas/cfi/cfi-arm-1.d new file mode 100644 -index 0000000..8987a7c +index 0000000..0d831e0 --- /dev/null +++ b/gas/testsuite/gas/cfi/cfi-arm-1.d -@@ -0,0 +1,27 @@ +@@ -0,0 +1,32 @@ +#readelf: -wf +#name: CFI on ARM + @@ -1097259,7 +1104441,7 @@ index 0000000..8987a7c + + DW_CFA_def_cfa: r13 ofs 0 + -+00000014 0+0020 0+0018 FDE cie=0+0000 pc=0+0000..0+0018 ++00000014 0+002c 0+0018 FDE cie=0+0000 pc=0+0000..0+0018 + DW_CFA_advance_loc: 4 to 00000004 + DW_CFA_def_cfa: r12 ofs 0 + DW_CFA_advance_loc: 4 to 00000008 @@ -1097270,13 +1104452,18 @@ index 0000000..8987a7c + DW_CFA_offset: r14 at cfa-24 + DW_CFA_advance_loc: 4 to 00000010 + DW_CFA_def_cfa: r11 ofs 16 -+ ++ DW_CFA_advance_loc: 4 to 00000014 ++ DW_CFA_offset: r1 at cfa-16 ++ DW_CFA_offset_extended: r65 at cfa-20 ++ DW_CFA_offset_extended: r267 at cfa-48 ++ DW_CFA_nop ++ DW_CFA_nop diff --git a/gas/testsuite/gas/cfi/cfi-arm-1.s b/gas/testsuite/gas/cfi/cfi-arm-1.s new file mode 100644 -index 0000000..8c9d917 +index 0000000..d962442 --- /dev/null +++ b/gas/testsuite/gas/cfi/cfi-arm-1.s -@@ -0,0 +1,23 @@ +@@ -0,0 +1,29 @@ +#; $ as -o test.o gas-cfi-test.s && gcc -nostdlib -o test test.o + + .file "a.c" @@ -1097297,6 +1104484,12 @@ index 0000000..8c9d917 + sub fp, ip, #20 + .cfi_def_cfa fp, 16 + nop ++ ++ # Test fix for PR 16694 - the use of VFP registers in .cfi_offset directives. ++ .cfi_offset r1, -16 ++ .cfi_offset s1, -20 ++ .cfi_offset d11, -48 ++ + ldmea fp, {fp, sp, pc} + .cfi_endproc + .size foo, .-foo @@ -1099419,12 +1106612,11 @@ index 0000000..bc69fff + .cfi_endproc diff --git a/gas/testsuite/gas/cfi/cfi.exp b/gas/testsuite/gas/cfi/cfi.exp new file mode 100644 -index 0000000..3071ec3 +index 0000000..d0b7c35 --- /dev/null +++ b/gas/testsuite/gas/cfi/cfi.exp -@@ -0,0 +1,126 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,125 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1100032,24 +1107224,24 @@ index 0000000..eb1558d + 34: 22 f1 diff --git a/gas/testsuite/gas/cr16/bal_test.s b/gas/testsuite/gas/cr16/bal_test.s new file mode 100644 -index 0000000..ff329ab +index 0000000..b89f1f6 --- /dev/null +++ b/gas/testsuite/gas/cr16/bal_test.s @@ -0,0 +1,14 @@ -+ .text -+ .global main -+main: -+bal (ra),*+0xff122 -+bal (ra),*+0xfff126 -+bal (ra),*+0x22 -+bal (ra),*+0x122 -+bal (ra),*+0xf122 -+bal (ra),*+0x812a -+bal (r1,r0),*+0x122 -+bal (r11,r10),*+0xcff122 -+bal (r7,r6),*+0xaff122 -+bal (r4,r3),*+0x8ff122 -+bal (r8,r7),*+0xfff122 ++ .text ++ .global main ++main: ++bal (ra),*+0xff122 ++bal (ra),*+0xfff126 ++bal (ra),*+0x22 ++bal (ra),*+0x122 ++bal (ra),*+0xf122 ++bal (ra),*+0x812a ++bal (r1,r0),*+0x122 ++bal (r11,r10),*+0xcff122 ++bal (r7,r6),*+0xaff122 ++bal (r4,r3),*+0x8ff122 ++bal (r8,r7),*+0xfff122 diff --git a/gas/testsuite/gas/cr16/bcc_test.d b/gas/testsuite/gas/cr16/bcc_test.d new file mode 100644 index 0000000..4613edf @@ -1100127,69 +1107319,69 @@ index 0000000..4613edf + bc: fe ff diff --git a/gas/testsuite/gas/cr16/bcc_test.s b/gas/testsuite/gas/cr16/bcc_test.s new file mode 100644 -index 0000000..e22dbe8 +index 0000000..50f3fbe --- /dev/null +++ b/gas/testsuite/gas/cr16/bcc_test.s @@ -0,0 +1,59 @@ -+ .text -+ .global main -+main: -+ ################### -+ # bcc disp9/disp17/disp25 -+ ################### -+ # bcc disp9 -+ ################### -+ beq *+0x022 -+ bne *+0x032 -+ bcc *+0x044 -+ bcc *+0x054 -+ bhi *+0x066 -+ blt *+0x076 -+ bgt *+0x088 -+ bfs *+0x09a -+ bfc *+0x0aa -+ blo *+0x1bc -+ bhi *+0x1cc -+ blt *+0x1d6 -+ bge *+0x1e6 -+ br *+0x0f6 -+ ################### -+ # bcc disp17 -+ ################### -+ beq *+0x112 -+ beq *+0x1f12 -+ beq *+0x0f22 -+ bne *+0x0f34 -+ bcc *+0x0f44 -+ bcc *+0x0f56 -+ bhi *+0x0f66 -+ blt *+0x0f78 -+ bgt *+0x0f88 -+ bfs *+0x0f9a -+ bfc *+0x0faa -+ blo *+0x1fbc -+ bhi *+0x1fcc -+ blt *+0x1fda -+ bge *+0x1fea -+ br *+0xfffa -+ ################### -+ # bcc disp25 -+ ################### -+ beq *+0xff1f12 -+ beq *+0xaa0f22 -+ bne *+0xbb0f34 -+ bcc *+0xcc0f44 -+ bcc *+0xdd0f56 -+ bhi *+0x990f66 -+ blt *+0x880f78 -+ bgt *+0x770f88 -+ bfs *+0x660f9a -+ bfc *+0x550faa -+ blo *+0x441fbc -+ bhi *+0x331fcc -+ blt *+0x221fde -+ bge *+0x111fee -+ br *+0x0ffffe ++ .text ++ .global main ++main: ++ ################### ++ # bcc disp9/disp17/disp25 ++ ################### ++ # bcc disp9 ++ ################### ++ beq *+0x022 ++ bne *+0x032 ++ bcc *+0x044 ++ bcc *+0x054 ++ bhi *+0x066 ++ blt *+0x076 ++ bgt *+0x088 ++ bfs *+0x09a ++ bfc *+0x0aa ++ blo *+0x1bc ++ bhi *+0x1cc ++ blt *+0x1d6 ++ bge *+0x1e6 ++ br *+0x0f6 ++ ################### ++ # bcc disp17 ++ ################### ++ beq *+0x112 ++ beq *+0x1f12 ++ beq *+0x0f22 ++ bne *+0x0f34 ++ bcc *+0x0f44 ++ bcc *+0x0f56 ++ bhi *+0x0f66 ++ blt *+0x0f78 ++ bgt *+0x0f88 ++ bfs *+0x0f9a ++ bfc *+0x0faa ++ blo *+0x1fbc ++ bhi *+0x1fcc ++ blt *+0x1fda ++ bge *+0x1fea ++ br *+0xfffa ++ ################### ++ # bcc disp25 ++ ################### ++ beq *+0xff1f12 ++ beq *+0xaa0f22 ++ bne *+0xbb0f34 ++ bcc *+0xcc0f44 ++ bcc *+0xdd0f56 ++ bhi *+0x990f66 ++ blt *+0x880f78 ++ bgt *+0x770f88 ++ bfs *+0x660f9a ++ bfc *+0x550faa ++ blo *+0x441fbc ++ bhi *+0x331fcc ++ blt *+0x221fde ++ bge *+0x111fee ++ br *+0x0ffffe diff --git a/gas/testsuite/gas/cr16/beq0_test.d b/gas/testsuite/gas/cr16/beq0_test.d new file mode 100644 index 0000000..82f923c @@ -1100695,22 +1107887,22 @@ index 0000000..b834936 +[ ]*a: 0f 00[ ]*cinv[ ]*\[d,i,u\] diff --git a/gas/testsuite/gas/cr16/cinv_test.s b/gas/testsuite/gas/cr16/cinv_test.s new file mode 100644 -index 0000000..9d2490b +index 0000000..eda4b97 --- /dev/null +++ b/gas/testsuite/gas/cr16/cinv_test.s @@ -0,0 +1,12 @@ -+ .text -+ .global main -+main: -+ ############################## -+ # cin [i/i,u/d/d,u/d,i/d,i,u] -+ ############################## -+ cinv [i] -+ cinv [i,u] -+ cinv [d] -+ cinv [d,u] -+ cinv [d,i] -+ cinv [d,i,u] ++ .text ++ .global main ++main: ++ ############################## ++ # cin [i/i,u/d/d,u/d,i/d,i,u] ++ ############################## ++ cinv [i] ++ cinv [i,u] ++ cinv [d] ++ cinv [d,u] ++ cinv [d,i] ++ cinv [d,i,u] diff --git a/gas/testsuite/gas/cr16/cmp_test.d b/gas/testsuite/gas/cr16/cmp_test.d new file mode 100644 index 0000000..6c3e101 @@ -1100838,12 +1108030,11 @@ index 0000000..2d0af3b + cmpd $8,(sp) diff --git a/gas/testsuite/gas/cr16/cr16.exp b/gas/testsuite/gas/cr16/cr16.exp new file mode 100644 -index 0000000..d4d259e +index 0000000..478f78e --- /dev/null +++ b/gas/testsuite/gas/cr16/cr16.exp -@@ -0,0 +1,31 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,30 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1101099,82 +1108290,82 @@ index 0000000..0e22d57 + e4: ff ff diff --git a/gas/testsuite/gas/cr16/loadb_test.s b/gas/testsuite/gas/cr16/loadb_test.s new file mode 100644 -index 0000000..05345b9 +index 0000000..258e3b3 --- /dev/null +++ b/gas/testsuite/gas/cr16/loadb_test.s @@ -0,0 +1,72 @@ -+ .text -+ .global main -+main: -+ ###################### -+ # loadb abs20/24 reg -+ ###################### -+ loadb 0x0,r0 -+ loadb 0xff,r1 -+ loadb 0xfff,r3 -+ loadb 0x1234,r4 -+ loadb 0x1234,r5 -+ loadb 0x7A1234,r0 -+ loadb 0xBA1234,r1 -+ loadb 0xffffff,r2 -+ ###################### -+ # loadb abs20 rel reg -+ ###################### -+ loadb [r12]0x0,r0 -+ loadb [r13]0x0,r0 -+ loadb [r12]0xff,r1 -+ loadb [r13]0xff,r1 -+ loadb [r12]0xfff,r3 -+ loadb [r13]0xfff,r3 -+ loadb [r12]0x1234,r4 -+ loadb [r13]0x1234,r4 -+ loadb [r12]0x1234,r5 -+ loadb [r13]0x1234,r5 -+ loadb [r12]0x4567,r2 -+ loadb [r13]0xA1234,r2 -+ ################################### -+ # loadb rbase(disp20/-disp20) reg -+ ################################### -+ loadb 0x4(r1,r0),r1 -+ loadb 0x4(r3,r2),r3 -+ loadb 0x1234(r1,r0),r4 -+ loadb 0x1234(r3,r2),r5 -+ loadb 0xA1234(r1,r0),r6 -+ loadb -0x4(r1,r0),r1 -+ loadb -0x4(r3,r2),r3 -+ loadb -0x1234(r1,r0),r4 -+ loadb -0x1234(r3,r2),r5 -+ loadb -0xA1234(r1,r0),r6 -+ ################################################# -+ # loadb rpbase(disp4/disp16/disp20/-disp20) reg -+ ################################################# -+ loadb 0x0(r1,r0),r0 -+ loadb 0x0(r1,r0),r1 -+ loadb 0xf(r1,r0),r0 -+ loadb 0xf(r1,r0),r1 -+ loadb 0x1234(r1,r0),r2 -+ loadb 0xabcd(r3,r2),r3 -+ loadb 0xAfff(r4,r3),r4 -+ loadb 0xA1234(r6,r5),r5 -+ loadb -0xf(r1,r0),r0 -+ loadb -0xf(r1,r0),r1 -+ loadb -0x1234(r1,r0),r2 -+ loadb -0xabcd(r3,r2),r3 -+ loadb -0xAfff(r4,r3),r4 -+ loadb -0xA1234(r6,r5),r5 -+ #################################### -+ # loadb rbase(disp0/disp14) rel reg -+ #################################### -+ loadb [r12]0x0(r1,r0),r0 -+ loadb [r13]0x0(r1,r0),r1 -+ loadb [r12]0x1234(r1,r0),r2 -+ loadb [r13]0x1abcd(r1,r0),r3 -+ ################################# -+ # loadb rpbase(disp20) rel reg -+ ################################# -+ loadb [r12]0xA1234(r1,r0),r4 -+ loadb [r13]0xB1234(r1,r0),r5 -+ loadb [r13]0xfffff(r1,r0),r6 ++ .text ++ .global main ++main: ++ ###################### ++ # loadb abs20/24 reg ++ ###################### ++ loadb 0x0,r0 ++ loadb 0xff,r1 ++ loadb 0xfff,r3 ++ loadb 0x1234,r4 ++ loadb 0x1234,r5 ++ loadb 0x7A1234,r0 ++ loadb 0xBA1234,r1 ++ loadb 0xffffff,r2 ++ ###################### ++ # loadb abs20 rel reg ++ ###################### ++ loadb [r12]0x0,r0 ++ loadb [r13]0x0,r0 ++ loadb [r12]0xff,r1 ++ loadb [r13]0xff,r1 ++ loadb [r12]0xfff,r3 ++ loadb [r13]0xfff,r3 ++ loadb [r12]0x1234,r4 ++ loadb [r13]0x1234,r4 ++ loadb [r12]0x1234,r5 ++ loadb [r13]0x1234,r5 ++ loadb [r12]0x4567,r2 ++ loadb [r13]0xA1234,r2 ++ ################################### ++ # loadb rbase(disp20/-disp20) reg ++ ################################### ++ loadb 0x4(r1,r0),r1 ++ loadb 0x4(r3,r2),r3 ++ loadb 0x1234(r1,r0),r4 ++ loadb 0x1234(r3,r2),r5 ++ loadb 0xA1234(r1,r0),r6 ++ loadb -0x4(r1,r0),r1 ++ loadb -0x4(r3,r2),r3 ++ loadb -0x1234(r1,r0),r4 ++ loadb -0x1234(r3,r2),r5 ++ loadb -0xA1234(r1,r0),r6 ++ ################################################# ++ # loadb rpbase(disp4/disp16/disp20/-disp20) reg ++ ################################################# ++ loadb 0x0(r1,r0),r0 ++ loadb 0x0(r1,r0),r1 ++ loadb 0xf(r1,r0),r0 ++ loadb 0xf(r1,r0),r1 ++ loadb 0x1234(r1,r0),r2 ++ loadb 0xabcd(r3,r2),r3 ++ loadb 0xAfff(r4,r3),r4 ++ loadb 0xA1234(r6,r5),r5 ++ loadb -0xf(r1,r0),r0 ++ loadb -0xf(r1,r0),r1 ++ loadb -0x1234(r1,r0),r2 ++ loadb -0xabcd(r3,r2),r3 ++ loadb -0xAfff(r4,r3),r4 ++ loadb -0xA1234(r6,r5),r5 ++ #################################### ++ # loadb rbase(disp0/disp14) rel reg ++ #################################### ++ loadb [r12]0x0(r1,r0),r0 ++ loadb [r13]0x0(r1,r0),r1 ++ loadb [r12]0x1234(r1,r0),r2 ++ loadb [r13]0x1abcd(r1,r0),r3 ++ ################################# ++ # loadb rpbase(disp20) rel reg ++ ################################# ++ loadb [r12]0xA1234(r1,r0),r4 ++ loadb [r13]0xB1234(r1,r0),r5 ++ loadb [r13]0xfffff(r1,r0),r6 diff --git a/gas/testsuite/gas/cr16/loadd_test.d b/gas/testsuite/gas/cr16/loadd_test.d new file mode 100644 index 0000000..77ea45f @@ -1101262,82 +1108453,82 @@ index 0000000..77ea45f + e4: ff ff diff --git a/gas/testsuite/gas/cr16/loadd_test.s b/gas/testsuite/gas/cr16/loadd_test.s new file mode 100644 -index 0000000..22c641f +index 0000000..677752d --- /dev/null +++ b/gas/testsuite/gas/cr16/loadd_test.s @@ -0,0 +1,72 @@ -+ .text -+ .global main -+main: -+ ###################### -+ # loadd abs20/24 regp -+ ###################### -+ loadd 0x0,(r1,r0) -+ loadd 0xff,(r1,r0) -+ loadd 0xfff,(r3,r2) -+ loadd 0x1234,(r4,r3) -+ loadd 0x1234,(r5,r4) -+ loadd 0x7A1234,(r1,r0) -+ loadd 0xBA1234,(r1,r0) -+ loadd 0xffffff,(r2,r1) -+ ###################### -+ # loadd abs20 rel regp -+ ###################### -+ loadd [r12]0x0,(r1,r0) -+ loadd [r13]0x0,(r1,r0) -+ loadd [r12]0xff,(r1,r0) -+ loadd [r13]0xff,(r1,r0) -+ loadd [r12]0xfff,(r3,r2) -+ loadd [r13]0xfff,(r3,r2) -+ loadd [r12]0x1234,(r4,r3) -+ loadd [r13]0x1234,(r4,r3) -+ loadd [r12]0x1234,(r5,r4) -+ loadd [r13]0x1234,(r5,r4) -+ loadd [r12]0x4567,(r2,r1) -+ loadd [r13]0xA1234,(r2,r1) -+ ################################### -+ # loadd rbase(disp20/-disp20) regp -+ ################################### -+ loadd 0x4(r1,r0),(r2,r1) -+ loadd 0x4(r3,r2),(r3,r2) -+ loadd 0x1234(r1,r0),(r4,r3) -+ loadd 0x1234(r3,r2),(r5,r4) -+ loadd 0xA1234(r1,r0),(r6,r5) -+ loadd -0x4(r1,r0),(r2,r1) -+ loadd -0x4(r3,r2),(r3,r2) -+ loadd -0x1234(r1,r0),(r4,r3) -+ loadd -0x1234(r3,r2),(r5,r4) -+ loadd -0xA1234(r1,r0),(r6,r5) -+ ################################################# -+ # loadd rpbase(disp4/disp16/disp20/-disp20) reg -+ ################################################# -+ loadd 0x0(r1,r0),(r1,r0) -+ loadd 0x0(r1,r0),(r1,r0) -+ loadd 0xf(r1,r0),(r1,r0) -+ loadd 0xf(r1,r0),(r1,r0) -+ loadd 0x1234(r1,r0),(r2,r1) -+ loadd 0xabcd(r3,r2),(r3,r2) -+ loadd 0xAfff(r4,r3),(r4,r3) -+ loadd 0xA1234(r6,r5),(r7,r6) -+ loadd -0xf(r1,r0),(r1,r0) -+ loadd -0xf(r1,r0),(r1,r0) -+ loadd -0x1234(r1,r0),(r2,r1) -+ loadd -0xabcd(r3,r2),(r3,r2) -+ loadd -0xAfff(r4,r3),(r5,r4) -+ loadd -0xA1234(r6,r5),(r5,r4) -+ #################################### -+ # loadd rbase(disp0/disp14) rel reg -+ #################################### -+ loadd [r12]0x0(r1,r0),(r1,r0) -+ loadd [r13]0x0(r1,r0),(r1,r0) -+ loadd [r12]0x1234(r1,r0),(r2,r1) -+ loadd [r13]0x1abcd(r1,r0),(r3,r2) -+ ################################# -+ # loadd rpbase(disp20) rel reg -+ ################################# -+ loadd [r12]0xA1234(r1,r0),(r3,r2) -+ loadd [r13]0xB1234(r1,r0),(r4,r3) -+ loadd [r13]0xfffff(r1,r0),(r5,r4) ++ .text ++ .global main ++main: ++ ###################### ++ # loadd abs20/24 regp ++ ###################### ++ loadd 0x0,(r1,r0) ++ loadd 0xff,(r1,r0) ++ loadd 0xfff,(r3,r2) ++ loadd 0x1234,(r4,r3) ++ loadd 0x1234,(r5,r4) ++ loadd 0x7A1234,(r1,r0) ++ loadd 0xBA1234,(r1,r0) ++ loadd 0xffffff,(r2,r1) ++ ###################### ++ # loadd abs20 rel regp ++ ###################### ++ loadd [r12]0x0,(r1,r0) ++ loadd [r13]0x0,(r1,r0) ++ loadd [r12]0xff,(r1,r0) ++ loadd [r13]0xff,(r1,r0) ++ loadd [r12]0xfff,(r3,r2) ++ loadd [r13]0xfff,(r3,r2) ++ loadd [r12]0x1234,(r4,r3) ++ loadd [r13]0x1234,(r4,r3) ++ loadd [r12]0x1234,(r5,r4) ++ loadd [r13]0x1234,(r5,r4) ++ loadd [r12]0x4567,(r2,r1) ++ loadd [r13]0xA1234,(r2,r1) ++ ################################### ++ # loadd rbase(disp20/-disp20) regp ++ ################################### ++ loadd 0x4(r1,r0),(r2,r1) ++ loadd 0x4(r3,r2),(r3,r2) ++ loadd 0x1234(r1,r0),(r4,r3) ++ loadd 0x1234(r3,r2),(r5,r4) ++ loadd 0xA1234(r1,r0),(r6,r5) ++ loadd -0x4(r1,r0),(r2,r1) ++ loadd -0x4(r3,r2),(r3,r2) ++ loadd -0x1234(r1,r0),(r4,r3) ++ loadd -0x1234(r3,r2),(r5,r4) ++ loadd -0xA1234(r1,r0),(r6,r5) ++ ################################################# ++ # loadd rpbase(disp4/disp16/disp20/-disp20) reg ++ ################################################# ++ loadd 0x0(r1,r0),(r1,r0) ++ loadd 0x0(r1,r0),(r1,r0) ++ loadd 0xf(r1,r0),(r1,r0) ++ loadd 0xf(r1,r0),(r1,r0) ++ loadd 0x1234(r1,r0),(r2,r1) ++ loadd 0xabcd(r3,r2),(r3,r2) ++ loadd 0xAfff(r4,r3),(r4,r3) ++ loadd 0xA1234(r6,r5),(r7,r6) ++ loadd -0xf(r1,r0),(r1,r0) ++ loadd -0xf(r1,r0),(r1,r0) ++ loadd -0x1234(r1,r0),(r2,r1) ++ loadd -0xabcd(r3,r2),(r3,r2) ++ loadd -0xAfff(r4,r3),(r5,r4) ++ loadd -0xA1234(r6,r5),(r5,r4) ++ #################################### ++ # loadd rbase(disp0/disp14) rel reg ++ #################################### ++ loadd [r12]0x0(r1,r0),(r1,r0) ++ loadd [r13]0x0(r1,r0),(r1,r0) ++ loadd [r12]0x1234(r1,r0),(r2,r1) ++ loadd [r13]0x1abcd(r1,r0),(r3,r2) ++ ################################# ++ # loadd rpbase(disp20) rel reg ++ ################################# ++ loadd [r12]0xA1234(r1,r0),(r3,r2) ++ loadd [r13]0xB1234(r1,r0),(r4,r3) ++ loadd [r13]0xfffff(r1,r0),(r5,r4) diff --git a/gas/testsuite/gas/cr16/loadm_test.d b/gas/testsuite/gas/cr16/loadm_test.d new file mode 100644 index 0000000..7d7ff3e @@ -1101487,82 +1108678,82 @@ index 0000000..cc4f311 + e4: ff ff diff --git a/gas/testsuite/gas/cr16/loadw_test.s b/gas/testsuite/gas/cr16/loadw_test.s new file mode 100644 -index 0000000..853e98f +index 0000000..bd9a2bb --- /dev/null +++ b/gas/testsuite/gas/cr16/loadw_test.s @@ -0,0 +1,72 @@ -+ .text -+ .global main -+main: -+ ###################### -+ # loadw abs20/24 reg -+ ###################### -+ loadw 0x0,r0 -+ loadw 0xff,r1 -+ loadw 0xfff,r3 -+ loadw 0x1234,r4 -+ loadw 0x1234,r5 -+ loadw 0x7A1234,r0 -+ loadw 0xBA1234,r1 -+ loadw 0xffffff,r2 -+ ###################### -+ # loadw abs20 rel reg -+ ###################### -+ loadw [r12]0x0,r0 -+ loadw [r13]0x0,r0 -+ loadw [r12]0xff,r1 -+ loadw [r13]0xff,r1 -+ loadw [r12]0xfff,r3 -+ loadw [r13]0xfff,r3 -+ loadw [r12]0x1234,r4 -+ loadw [r13]0x1234,r4 -+ loadw [r12]0x1234,r5 -+ loadw [r13]0x1234,r5 -+ loadw [r12]0x4567,r2 -+ loadw [r13]0xA1234,r2 -+ ################################### -+ # loadw rbase(disp20/-disp20) reg -+ ################################### -+ loadw 0x4(r1,r0),r1 -+ loadw 0x4(r3,r2),r3 -+ loadw 0x1234(r1,r0),r4 -+ loadw 0x1234(r3,r2),r5 -+ loadw 0xA1234(r1,r0),r6 -+ loadw -0x4(r1,r0),r1 -+ loadw -0x4(r3,r2),r3 -+ loadw -0x1234(r1,r0),r4 -+ loadw -0x1234(r3,r2),r5 -+ loadw -0xA1234(r1,r0),r6 -+ ################################################# -+ # loadw rpbase(disp4/disp16/disp20/-disp20) reg -+ ################################################# -+ loadw 0x0(r1,r0),r0 -+ loadw 0x0(r1,r0),r1 -+ loadw 0xf(r1,r0),r0 -+ loadw 0xf(r1,r0),r1 -+ loadw 0x1234(r1,r0),r2 -+ loadw 0xabcd(r3,r2),r3 -+ loadw 0xAfff(r4,r3),r4 -+ loadw 0xA1234(r6,r5),r5 -+ loadw -0xf(r1,r0),r0 -+ loadw -0xf(r1,r0),r1 -+ loadw -0x1234(r1,r0),r2 -+ loadw -0xabcd(r3,r2),r3 -+ loadw -0xAfff(r4,r3),r4 -+ loadw -0xA1234(r6,r5),r5 -+ #################################### -+ # loadw rbase(disp0/disp14) rel reg -+ #################################### -+ loadw [r12]0x0(r1,r0),r0 -+ loadw [r13]0x0(r1,r0),r1 -+ loadw [r12]0x1234(r1,r0),r2 -+ loadw [r13]0x1abcd(r1,r0),r3 -+ ################################# -+ # loadw rpbase(disp20) rel reg -+ ################################# -+ loadw [r12]0xA1234(r1,r0),r4 -+ loadw [r13]0xB1234(r1,r0),r5 -+ loadw [r13]0xfffff(r1,r0),r6 ++ .text ++ .global main ++main: ++ ###################### ++ # loadw abs20/24 reg ++ ###################### ++ loadw 0x0,r0 ++ loadw 0xff,r1 ++ loadw 0xfff,r3 ++ loadw 0x1234,r4 ++ loadw 0x1234,r5 ++ loadw 0x7A1234,r0 ++ loadw 0xBA1234,r1 ++ loadw 0xffffff,r2 ++ ###################### ++ # loadw abs20 rel reg ++ ###################### ++ loadw [r12]0x0,r0 ++ loadw [r13]0x0,r0 ++ loadw [r12]0xff,r1 ++ loadw [r13]0xff,r1 ++ loadw [r12]0xfff,r3 ++ loadw [r13]0xfff,r3 ++ loadw [r12]0x1234,r4 ++ loadw [r13]0x1234,r4 ++ loadw [r12]0x1234,r5 ++ loadw [r13]0x1234,r5 ++ loadw [r12]0x4567,r2 ++ loadw [r13]0xA1234,r2 ++ ################################### ++ # loadw rbase(disp20/-disp20) reg ++ ################################### ++ loadw 0x4(r1,r0),r1 ++ loadw 0x4(r3,r2),r3 ++ loadw 0x1234(r1,r0),r4 ++ loadw 0x1234(r3,r2),r5 ++ loadw 0xA1234(r1,r0),r6 ++ loadw -0x4(r1,r0),r1 ++ loadw -0x4(r3,r2),r3 ++ loadw -0x1234(r1,r0),r4 ++ loadw -0x1234(r3,r2),r5 ++ loadw -0xA1234(r1,r0),r6 ++ ################################################# ++ # loadw rpbase(disp4/disp16/disp20/-disp20) reg ++ ################################################# ++ loadw 0x0(r1,r0),r0 ++ loadw 0x0(r1,r0),r1 ++ loadw 0xf(r1,r0),r0 ++ loadw 0xf(r1,r0),r1 ++ loadw 0x1234(r1,r0),r2 ++ loadw 0xabcd(r3,r2),r3 ++ loadw 0xAfff(r4,r3),r4 ++ loadw 0xA1234(r6,r5),r5 ++ loadw -0xf(r1,r0),r0 ++ loadw -0xf(r1,r0),r1 ++ loadw -0x1234(r1,r0),r2 ++ loadw -0xabcd(r3,r2),r3 ++ loadw -0xAfff(r4,r3),r4 ++ loadw -0xA1234(r6,r5),r5 ++ #################################### ++ # loadw rbase(disp0/disp14) rel reg ++ #################################### ++ loadw [r12]0x0(r1,r0),r0 ++ loadw [r13]0x0(r1,r0),r1 ++ loadw [r12]0x1234(r1,r0),r2 ++ loadw [r13]0x1abcd(r1,r0),r3 ++ ################################# ++ # loadw rpbase(disp20) rel reg ++ ################################# ++ loadw [r12]0xA1234(r1,r0),r4 ++ loadw [r13]0xB1234(r1,r0),r5 ++ loadw [r13]0xfffff(r1,r0),r6 diff --git a/gas/testsuite/gas/cr16/lpsp_test.d b/gas/testsuite/gas/cr16/lpsp_test.d new file mode 100644 index 0000000..66ca8e2 @@ -1101628,73 +1108819,73 @@ index 0000000..66ca8e2 + bc: 14 00 68 30 sprd car1,\(r9,r8\) diff --git a/gas/testsuite/gas/cr16/lpsp_test.s b/gas/testsuite/gas/cr16/lpsp_test.s new file mode 100644 -index 0000000..7f487da +index 0000000..8e9d459 --- /dev/null +++ b/gas/testsuite/gas/cr16/lpsp_test.s @@ -0,0 +1,63 @@ -+ .text -+ .global main -+main: -+ ################ -+ # lpr reg, preg -+ ################ -+ lpr r1,psr -+ lpr r2,cfg -+ lpr r2,intbasel -+ lpr r3,intbaseh -+ lpr r4,ispl -+ lpr r5,isph -+ lpr r6,uspl -+ lpr r7,usph -+ lpr r8,dsr -+ lpr r9,dcrl -+ lpr r10,dcrh -+ lpr r11,car0l -+ lpr r0,car0h -+ lpr r1,car1l -+ lpr r3,car1h -+ ################# -+ # lprd regp, preg -+ ################# -+ lprd (r1,r0),psr -+ lprd (r2,r1),cfg -+ lprd (r3,r2),intbase -+ lprd (r4,r3),isp -+ lprd (r5,r4),usp -+ lprd (r6,r5),dsr -+ lprd (r7,r6),dcr -+ lprd (r8,r7),car0 -+ lprd (r9,r8),car1 -+ ################# -+ # spr preg, reg -+ ################# -+ spr psr,r0 -+ spr cfg,r1 -+ spr intbasel,r2 -+ spr intbaseh,r3 -+ spr ispl,r4 -+ spr isph,r5 -+ spr uspl,r6 -+ spr usph,r7 -+ spr dsr,r8 -+ spr dcrl,r9 -+ spr dcrh,r10 -+ spr car0l,r11 -+ spr car0h,r0 -+ spr car1l,r1 -+ spr car1h,r2 -+ ################# -+ # sprd preg, regp -+ ################# -+ sprd psr,(r1,r0) -+ sprd cfg,(r2,r1) -+ sprd intbase,(r3,r2) -+ sprd isp,(r4,r3) -+ sprd usp,(r5,r4) -+ sprd dsr,(r6,r5) -+ sprd dcr,(r7,r6) -+ sprd car0,(r8,r7) -+ sprd car1,(r9,r8) ++ .text ++ .global main ++main: ++ ################ ++ # lpr reg, preg ++ ################ ++ lpr r1,psr ++ lpr r2,cfg ++ lpr r2,intbasel ++ lpr r3,intbaseh ++ lpr r4,ispl ++ lpr r5,isph ++ lpr r6,uspl ++ lpr r7,usph ++ lpr r8,dsr ++ lpr r9,dcrl ++ lpr r10,dcrh ++ lpr r11,car0l ++ lpr r0,car0h ++ lpr r1,car1l ++ lpr r3,car1h ++ ################# ++ # lprd regp, preg ++ ################# ++ lprd (r1,r0),psr ++ lprd (r2,r1),cfg ++ lprd (r3,r2),intbase ++ lprd (r4,r3),isp ++ lprd (r5,r4),usp ++ lprd (r6,r5),dsr ++ lprd (r7,r6),dcr ++ lprd (r8,r7),car0 ++ lprd (r9,r8),car1 ++ ################# ++ # spr preg, reg ++ ################# ++ spr psr,r0 ++ spr cfg,r1 ++ spr intbasel,r2 ++ spr intbaseh,r3 ++ spr ispl,r4 ++ spr isph,r5 ++ spr uspl,r6 ++ spr usph,r7 ++ spr dsr,r8 ++ spr dcrl,r9 ++ spr dcrh,r10 ++ spr car0l,r11 ++ spr car0h,r0 ++ spr car1l,r1 ++ spr car1h,r2 ++ ################# ++ # sprd preg, regp ++ ################# ++ sprd psr,(r1,r0) ++ sprd cfg,(r2,r1) ++ sprd intbase,(r3,r2) ++ sprd isp,(r4,r3) ++ sprd usp,(r5,r4) ++ sprd dsr,(r6,r5) ++ sprd dcr,(r7,r6) ++ sprd car0,(r8,r7) ++ sprd car1,(r9,r8) diff --git a/gas/testsuite/gas/cr16/lsh_test.d b/gas/testsuite/gas/cr16/lsh_test.d new file mode 100644 index 0000000..aba1cda @@ -1102231,12 +1109422,11 @@ index 0000000..df140c1 + #ord $8,(sp) diff --git a/gas/testsuite/gas/cr16/pic.exp b/gas/testsuite/gas/cr16/pic.exp new file mode 100644 -index 0000000..a8d12e1 +index 0000000..b46a69f --- /dev/null +++ b/gas/testsuite/gas/cr16/pic.exp -@@ -0,0 +1,23 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,22 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1103222,153 +1110412,153 @@ index 0000000..dc2a9c2 + 1e4: 45 23 diff --git a/gas/testsuite/gas/cr16/storb_test.s b/gas/testsuite/gas/cr16/storb_test.s new file mode 100644 -index 0000000..63d8047 +index 0000000..2cd2706 --- /dev/null +++ b/gas/testsuite/gas/cr16/storb_test.s @@ -0,0 +1,143 @@ -+ .text -+ .global main -+main: -+ ###################### -+ # storb reg abs20/24 -+ ###################### -+ storb r0,0x0 -+ storb r1,0xff -+ storb r3,0xfff -+ storb r4,0x1234 -+ storb r5,0x1234 -+ storb r0,0x7A1234 -+ storb r1,0xBA1234 -+ storb r2,0xffffff -+ ###################### -+ # storb abs20 rel reg -+ ###################### -+ storb r0,[r12]0x0 -+ storb r0,[r13]0x0 -+ storb r1,[r12]0xff -+ storb r1,[r13]0xff -+ storb r3,[r12]0xfff -+ storb r3,[r13]0xfff -+ storb r4,[r12]0x1234 -+ storb r4,[r13]0x1234 -+ storb r5,[r12]0x1234 -+ storb r5,[r13]0x1234 -+ storb r2,[r12]0x4567 -+ storb r2,[r13]0xA1234 -+ ################################### -+ # storb reg rbase(disp20/-disp20) -+ ################################### -+ storb r1,0x4(r1,r0) -+ storb r3,0x4(r3,r2) -+ storb r4,0x1234(r1,r0) -+ storb r5,0x1234(r3,r2) -+ storb r6,0xA1234(r1,r0) -+ storb r1,-0x4(r1,r0) -+ storb r3,-0x4(r3,r2) -+ storb r4,-0x1234(r1,r0) -+ storb r5,-0x1234(r3,r2) -+ storb r6,-0xA1234(r1,r0) -+ ################################################# -+ # storb reg rpbase(disp4/disp16/disp20/-disp20) -+ ################################################# -+ storb r0,0x0(r1,r0) -+ storb r0,0x0(r1,r0) -+ storb r0,0xf(r1,r0) -+ storb r1,0xf(r1,r0) -+ storb r2,0x1234(r1,r0) -+ storb r3,0xabcd(r3,r2) -+ storb r4,0xAfff(r4,r3) -+ storb r5,0xA1234(r6,r5) -+ storb r0,-0xf(r1,r0) -+ storb r1,-0xf(r1,r0) -+ storb r2,-0x1234(r1,r0) -+ storb r3,-0xabcd(r3,r2) -+ storb r4,-0xAfff(r4,r3) -+ storb r5,-0xA1234(r6,r5) -+ #################################### -+ # storb rbase(disp0/disp14) rel reg -+ #################################### -+ storb r0,[r12]0x0(r1,r0) -+ storb r1,[r13]0x0(r1,r0) -+ storb r2,[r12]0x1234(r1,r0) -+ storb r3,[r13]0x1abcd(r1,r0) -+ ################################# -+ # storb reg rpbase(disp20) rel -+ ################################# -+ storb r4,[r12]0xA1234(r1,r0) -+ storb r5,[r13]0xB1234(r1,r0) -+ storb r6,[r13]0xfffff(r1,r0) -+ ####################### -+ # storb reg, uimm16/20 -+ ###################### -+ storb $4,0xbcd -+ storb $5,0xaabcd -+ storb $3,0xfaabcd -+ -+ ####################### -+ # storb reg, uimm16/20 -+ ###################### -+ storb $5,[r12]0x14 -+ storb $4,[r13]0xabfc -+ storb $3,[r12]0x1234 -+ storb $3,[r13]0x1234 -+ storb $3,[r12]0x34 -+ ####################### -+ # storb imm, index-rbase -+ ###################### -+ storb $3,[r12]0xa7a(r1,r0) -+ storb $3,[r12]0xa7a(r3,r2) -+ storb $3,[r12]0xa7a(r4,r3) -+ storb $3,[r12]0xa7a(r5,r4) -+ storb $3,[r12]0xa7a(r6,r5) -+ storb $3,[r12]0xa7a(r7,r6) -+ storb $3,[r12]0xa7a(r9,r8) -+ storb $3,[r12]0xa7a(r11,r10) -+ storb $3,[r13]0xa7a(r1,r0) -+ storb $3,[r13]0xa7a(r3,r2) -+ storb $3,[r13]0xa7a(r4,r3) -+ storb $3,[r13]0xa7a(r5,r4) -+ storb $3,[r13]0xa7a(r6,r5) -+ storb $3,[r13]0xa7a(r7,r6) -+ storb $3,[r13]0xa7a(r9,r8) -+ storb $3,[r13]0xa7a(r11,r10) -+ storb $5,[r13]0xb7a(r4,r3) -+ storb $1,[r12]0x17a(r6,r5) -+ storb $1,[r13]0x134(r6,r5) -+ storb $3,[r12]0xabcde(r4,r3) -+ storb $5,[r13]0xabcd(r4,r3) -+ storb $3,[r12]0xabcd(r6,r5) -+ storb $3,[r13]0xbcde(r6,r5) -+ ####################### -+ # storb imm4, rbase(disp) -+ ###################### -+ storb $5,0x0(r2) -+ storb $3,0x34(r12) -+ storb $3,0xab(r13) -+ storb $5,0xad(r1) -+ storb $5,0xcd(r2) -+ storb $5,0xfff(r0) -+ storb $3,0xbcd(r4) -+ storb $3,0xfff(r12) -+ storb $3,0xfff(r13) -+ storb $3,0xffff(r13) -+ storb $3,0x2343(r12) -+ storb $3,0x12345(r2) -+ storb $3,0x4abcd(r8) -+ storb $3,0xfabcd(r13) -+ storb $3,0xfabcd(r8) -+ storb $3,0xfabcd(r9) -+ storb $3,0x4abcd(r9) -+ ########################## -+ # storb imm, disp20(rpbase) -+ ######################### -+ storb $3,0x0(r2,r1) -+ storb $5,0x1(r2,r1) -+ storb $4,0x1234(r2,r1) -+ storb $3,0x1234(r2,r1) -+ storb $3,0x12345(r2,r1) -+ storb $3,0x123(r2,r1) -+ storb $3,0x12345(r2,r1) ++ .text ++ .global main ++main: ++ ###################### ++ # storb reg abs20/24 ++ ###################### ++ storb r0,0x0 ++ storb r1,0xff ++ storb r3,0xfff ++ storb r4,0x1234 ++ storb r5,0x1234 ++ storb r0,0x7A1234 ++ storb r1,0xBA1234 ++ storb r2,0xffffff ++ ###################### ++ # storb abs20 rel reg ++ ###################### ++ storb r0,[r12]0x0 ++ storb r0,[r13]0x0 ++ storb r1,[r12]0xff ++ storb r1,[r13]0xff ++ storb r3,[r12]0xfff ++ storb r3,[r13]0xfff ++ storb r4,[r12]0x1234 ++ storb r4,[r13]0x1234 ++ storb r5,[r12]0x1234 ++ storb r5,[r13]0x1234 ++ storb r2,[r12]0x4567 ++ storb r2,[r13]0xA1234 ++ ################################### ++ # storb reg rbase(disp20/-disp20) ++ ################################### ++ storb r1,0x4(r1,r0) ++ storb r3,0x4(r3,r2) ++ storb r4,0x1234(r1,r0) ++ storb r5,0x1234(r3,r2) ++ storb r6,0xA1234(r1,r0) ++ storb r1,-0x4(r1,r0) ++ storb r3,-0x4(r3,r2) ++ storb r4,-0x1234(r1,r0) ++ storb r5,-0x1234(r3,r2) ++ storb r6,-0xA1234(r1,r0) ++ ################################################# ++ # storb reg rpbase(disp4/disp16/disp20/-disp20) ++ ################################################# ++ storb r0,0x0(r1,r0) ++ storb r0,0x0(r1,r0) ++ storb r0,0xf(r1,r0) ++ storb r1,0xf(r1,r0) ++ storb r2,0x1234(r1,r0) ++ storb r3,0xabcd(r3,r2) ++ storb r4,0xAfff(r4,r3) ++ storb r5,0xA1234(r6,r5) ++ storb r0,-0xf(r1,r0) ++ storb r1,-0xf(r1,r0) ++ storb r2,-0x1234(r1,r0) ++ storb r3,-0xabcd(r3,r2) ++ storb r4,-0xAfff(r4,r3) ++ storb r5,-0xA1234(r6,r5) ++ #################################### ++ # storb rbase(disp0/disp14) rel reg ++ #################################### ++ storb r0,[r12]0x0(r1,r0) ++ storb r1,[r13]0x0(r1,r0) ++ storb r2,[r12]0x1234(r1,r0) ++ storb r3,[r13]0x1abcd(r1,r0) ++ ################################# ++ # storb reg rpbase(disp20) rel ++ ################################# ++ storb r4,[r12]0xA1234(r1,r0) ++ storb r5,[r13]0xB1234(r1,r0) ++ storb r6,[r13]0xfffff(r1,r0) ++ ####################### ++ # storb reg, uimm16/20 ++ ###################### ++ storb $4,0xbcd ++ storb $5,0xaabcd ++ storb $3,0xfaabcd ++ ++ ####################### ++ # storb reg, uimm16/20 ++ ###################### ++ storb $5,[r12]0x14 ++ storb $4,[r13]0xabfc ++ storb $3,[r12]0x1234 ++ storb $3,[r13]0x1234 ++ storb $3,[r12]0x34 ++ ####################### ++ # storb imm, index-rbase ++ ###################### ++ storb $3,[r12]0xa7a(r1,r0) ++ storb $3,[r12]0xa7a(r3,r2) ++ storb $3,[r12]0xa7a(r4,r3) ++ storb $3,[r12]0xa7a(r5,r4) ++ storb $3,[r12]0xa7a(r6,r5) ++ storb $3,[r12]0xa7a(r7,r6) ++ storb $3,[r12]0xa7a(r9,r8) ++ storb $3,[r12]0xa7a(r11,r10) ++ storb $3,[r13]0xa7a(r1,r0) ++ storb $3,[r13]0xa7a(r3,r2) ++ storb $3,[r13]0xa7a(r4,r3) ++ storb $3,[r13]0xa7a(r5,r4) ++ storb $3,[r13]0xa7a(r6,r5) ++ storb $3,[r13]0xa7a(r7,r6) ++ storb $3,[r13]0xa7a(r9,r8) ++ storb $3,[r13]0xa7a(r11,r10) ++ storb $5,[r13]0xb7a(r4,r3) ++ storb $1,[r12]0x17a(r6,r5) ++ storb $1,[r13]0x134(r6,r5) ++ storb $3,[r12]0xabcde(r4,r3) ++ storb $5,[r13]0xabcd(r4,r3) ++ storb $3,[r12]0xabcd(r6,r5) ++ storb $3,[r13]0xbcde(r6,r5) ++ ####################### ++ # storb imm4, rbase(disp) ++ ###################### ++ storb $5,0x0(r2) ++ storb $3,0x34(r12) ++ storb $3,0xab(r13) ++ storb $5,0xad(r1) ++ storb $5,0xcd(r2) ++ storb $5,0xfff(r0) ++ storb $3,0xbcd(r4) ++ storb $3,0xfff(r12) ++ storb $3,0xfff(r13) ++ storb $3,0xffff(r13) ++ storb $3,0x2343(r12) ++ storb $3,0x12345(r2) ++ storb $3,0x4abcd(r8) ++ storb $3,0xfabcd(r13) ++ storb $3,0xfabcd(r8) ++ storb $3,0xfabcd(r9) ++ storb $3,0x4abcd(r9) ++ ########################## ++ # storb imm, disp20(rpbase) ++ ######################### ++ storb $3,0x0(r2,r1) ++ storb $5,0x1(r2,r1) ++ storb $4,0x1234(r2,r1) ++ storb $3,0x1234(r2,r1) ++ storb $3,0x12345(r2,r1) ++ storb $3,0x123(r2,r1) ++ storb $3,0x12345(r2,r1) diff --git a/gas/testsuite/gas/cr16/stord_test.d b/gas/testsuite/gas/cr16/stord_test.d new file mode 100644 index 0000000..9e31b7a @@ -1103457,82 +1110647,82 @@ index 0000000..9e31b7a + e6: ff ff diff --git a/gas/testsuite/gas/cr16/stord_test.s b/gas/testsuite/gas/cr16/stord_test.s new file mode 100644 -index 0000000..68b1f07 +index 0000000..dcac741 --- /dev/null +++ b/gas/testsuite/gas/cr16/stord_test.s @@ -0,0 +1,72 @@ -+ .text -+ .global main -+main: -+ ###################### -+ # stord abs20/24 regp -+ ###################### -+ stord (r1,r0),0x0 -+ stord (r1,r0),0xff -+ stord (r3,r2),0xfff -+ stord (r4,r3),0x1234 -+ stord (r5,r4),0x1234 -+ stord (r1,r0),0x7A1234 -+ stord (r1,r0),0xBA1234 -+ stord (r2,r1),0xffffff -+ ###################### -+ # stord abs20 rel regp -+ ###################### -+ stord (r1,r0),[r12]0x0 -+ stord (r1,r0),[r13]0x0 -+ stord (r1,r0),[r12]0xff -+ stord (r1,r0),[r13]0xff -+ stord (r3,r2),[r12]0xfff -+ stord (r3,r2),[r13]0xfff -+ stord (r4,r3),[r12]0x1234 -+ stord (r4,r3),[r13]0x1234 -+ stord (r5,r4),[r12]0x1234 -+ stord (r5,r4),[r13]0x1234 -+ stord (r2,r1),[r12]0x4567 -+ stord (r2,r1),[r13]0xA1234 -+ ################################### -+ # stord regp rbase(disp20/-disp20) -+ ################################### -+ stord (r2,r1),0x4(r1,r0) -+ stord (r3,r2),0x4(r3,r2) -+ stord (r4,r3),0x1234(r1,r0) -+ stord (r5,r4),0x1234(r3,r2) -+ stord (r6,r5),0xA1234(r1,r0) -+ stord (r2,r1),-0x4(r1,r0) -+ stord (r3,r2),-0x4(r3,r2) -+ stord (r4,r3),-0x1234(r1,r0) -+ stord (r5,r4),-0x1234(r3,r2) -+ stord (r6,r5),-0xA1234(r1,r0) -+ ################################################# -+ # stord regp rpbase(disp4/disp16/disp20/-disp20) -+ ################################################# -+ stord (r1,r0),0x0(r1,r0) -+ stord (r1,r0),0x0(r1,r0) -+ stord (r1,r0),0xf(r1,r0) -+ stord (r1,r0),0xf(r1,r0) -+ stord (r2,r1),0x1234(r1,r0) -+ stord (r3,r2),0xabcd(r3,r2) -+ stord (r4,r3),0xAfff(r4,r3) -+ stord (r7,r6),0xA1234(r6,r5) -+ stord (r1,r0),-0xf(r1,r0) -+ stord (r1,r0),-0xf(r1,r0) -+ stord (r2,r1),-0x1234(r1,r0) -+ stord (r3,r2),-0xabcd(r3,r2) -+ stord (r5,r4),-0xAfff(r4,r3) -+ stord (r5,r4),-0xA1234(r6,r5) -+ #################################### -+ # stord rbase(disp0/disp14) rel reg -+ #################################### -+ stord (r1,r0),[r12]0x0(r1,r0) -+ stord (r1,r0),[r13]0x0(r1,r0) -+ stord (r2,r1),[r12]0x1234(r1,r0) -+ stord (r3,r2),[r13]0x1abcd(r1,r0) -+ ################################# -+ # stord rpbase(disp20) rel reg -+ ################################# -+ stord (r3,r2),[r12]0xA1234(r1,r0) -+ stord (r4,r3),[r13]0xB1234(r1,r0) -+ stord (r5,r4),[r13]0xfffff(r1,r0) ++ .text ++ .global main ++main: ++ ###################### ++ # stord abs20/24 regp ++ ###################### ++ stord (r1,r0),0x0 ++ stord (r1,r0),0xff ++ stord (r3,r2),0xfff ++ stord (r4,r3),0x1234 ++ stord (r5,r4),0x1234 ++ stord (r1,r0),0x7A1234 ++ stord (r1,r0),0xBA1234 ++ stord (r2,r1),0xffffff ++ ###################### ++ # stord abs20 rel regp ++ ###################### ++ stord (r1,r0),[r12]0x0 ++ stord (r1,r0),[r13]0x0 ++ stord (r1,r0),[r12]0xff ++ stord (r1,r0),[r13]0xff ++ stord (r3,r2),[r12]0xfff ++ stord (r3,r2),[r13]0xfff ++ stord (r4,r3),[r12]0x1234 ++ stord (r4,r3),[r13]0x1234 ++ stord (r5,r4),[r12]0x1234 ++ stord (r5,r4),[r13]0x1234 ++ stord (r2,r1),[r12]0x4567 ++ stord (r2,r1),[r13]0xA1234 ++ ################################### ++ # stord regp rbase(disp20/-disp20) ++ ################################### ++ stord (r2,r1),0x4(r1,r0) ++ stord (r3,r2),0x4(r3,r2) ++ stord (r4,r3),0x1234(r1,r0) ++ stord (r5,r4),0x1234(r3,r2) ++ stord (r6,r5),0xA1234(r1,r0) ++ stord (r2,r1),-0x4(r1,r0) ++ stord (r3,r2),-0x4(r3,r2) ++ stord (r4,r3),-0x1234(r1,r0) ++ stord (r5,r4),-0x1234(r3,r2) ++ stord (r6,r5),-0xA1234(r1,r0) ++ ################################################# ++ # stord regp rpbase(disp4/disp16/disp20/-disp20) ++ ################################################# ++ stord (r1,r0),0x0(r1,r0) ++ stord (r1,r0),0x0(r1,r0) ++ stord (r1,r0),0xf(r1,r0) ++ stord (r1,r0),0xf(r1,r0) ++ stord (r2,r1),0x1234(r1,r0) ++ stord (r3,r2),0xabcd(r3,r2) ++ stord (r4,r3),0xAfff(r4,r3) ++ stord (r7,r6),0xA1234(r6,r5) ++ stord (r1,r0),-0xf(r1,r0) ++ stord (r1,r0),-0xf(r1,r0) ++ stord (r2,r1),-0x1234(r1,r0) ++ stord (r3,r2),-0xabcd(r3,r2) ++ stord (r5,r4),-0xAfff(r4,r3) ++ stord (r5,r4),-0xA1234(r6,r5) ++ #################################### ++ # stord rbase(disp0/disp14) rel reg ++ #################################### ++ stord (r1,r0),[r12]0x0(r1,r0) ++ stord (r1,r0),[r13]0x0(r1,r0) ++ stord (r2,r1),[r12]0x1234(r1,r0) ++ stord (r3,r2),[r13]0x1abcd(r1,r0) ++ ################################# ++ # stord rpbase(disp20) rel reg ++ ################################# ++ stord (r3,r2),[r12]0xA1234(r1,r0) ++ stord (r4,r3),[r13]0xB1234(r1,r0) ++ stord (r5,r4),[r13]0xfffff(r1,r0) diff --git a/gas/testsuite/gas/cr16/storm_test.d b/gas/testsuite/gas/cr16/storm_test.d new file mode 100644 index 0000000..8e103ba @@ -1103756,154 +1110946,154 @@ index 0000000..02b1b65 + 1e4: 45 23 diff --git a/gas/testsuite/gas/cr16/storw_test.s b/gas/testsuite/gas/cr16/storw_test.s new file mode 100644 -index 0000000..e27b198 +index 0000000..6adee5c --- /dev/null +++ b/gas/testsuite/gas/cr16/storw_test.s @@ -0,0 +1,144 @@ -+ .text -+ .global main -+main: -+ ###################### -+ # storw reg abs20/24 -+ ###################### -+ storw r0,0x0 -+ storw r1,0xff -+ storw r3,0xfff -+ storw r4,0x1234 -+ storw r5,0x1234 -+ storw r0,0x7A1234 -+ storw r1,0xBA1234 -+ storw r2,0xffffff -+ ###################### -+ # storw abs20 rel reg -+ ###################### -+ storw r0,[r12]0x0 -+ storw r0,[r13]0x0 -+ storw r1,[r12]0xff -+ storw r1,[r13]0xff -+ storw r3,[r12]0xfff -+ storw r3,[r13]0xfff -+ storw r4,[r12]0x1234 -+ storw r4,[r13]0x1234 -+ storw r5,[r12]0x1234 -+ storw r5,[r13]0x1234 -+ storw r2,[r12]0x4567 -+ storw r2,[r13]0xA1234 -+ ################################### -+ # storw reg rbase(disp20/-disp20) -+ ################################### -+ storw r1,0x4(r1,r0) -+ storw r3,0x4(r3,r2) -+ storw r4,0x1234(r1,r0) -+ storw r5,0x1234(r3,r2) -+ storw r6,0xA1234(r1,r0) -+ storw r1,-0x4(r1,r0) -+ storw r3,-0x4(r3,r2) -+ storw r4,-0x1234(r1,r0) -+ storw r5,-0x1234(r3,r2) -+ storw r6,-0xA1234(r1,r0) -+ ################################################# -+ # storw reg rpbase(disp4/disp16/disp20/-disp20) -+ ################################################# -+ storw r0,0x0(r1,r0) -+ storw r0,0x0(r1,r0) -+ storw r0,0xf(r1,r0) -+ storw r1,0xf(r1,r0) -+ storw r2,0x1234(r1,r0) -+ storw r3,0xabcd(r3,r2) -+ storw r4,0xAfff(r4,r3) -+ storw r5,0xA1234(r6,r5) -+ storw r0,-0xf(r1,r0) -+ storw r1,-0xf(r1,r0) -+ storw r2,-0x1234(r1,r0) -+ storw r3,-0xabcd(r3,r2) -+ storw r4,-0xAfff(r4,r3) -+ storw r5,-0xA1234(r6,r5) -+ #################################### -+ # storw rbase(disp0/disp14) rel reg -+ #################################### -+ storw r0,[r12]0x0(r1,r0) -+ storw r1,[r13]0x0(r1,r0) -+ storw r2,[r12]0x1234(r1,r0) -+ storw r3,[r13]0x1abcd(r1,r0) -+ ################################# -+ # storw reg rpbase(disp20) rel -+ ################################# -+ storw r4,[r12]0xA1234(r1,r0) -+ storw r5,[r13]0xB1234(r1,r0) -+ storw r6,[r13]0xfffff(r1,r0) -+ ####################### -+ # storw reg, uimm16/20 -+ ###################### -+ storw $4,0xbcd -+ storw $5,0xaabcd -+ storw $3,0xfaabcd -+ -+ ####################### -+ # storw reg, uimm16/20 -+ ###################### -+ storw $5,[r12]0x14 -+ storw $4,[r13]0xabfc -+ storw $3,[r12]0x1234 -+ storw $3,[r13]0x1234 -+ storw $3,[r12]0x34 -+ ####################### -+ # storw imm, index-rbase -+ ###################### -+ storw $3,[r12]0xa7a(r1,r0) -+ storw $3,[r12]0xa7a(r3,r2) -+ storw $3,[r12]0xa7a(r4,r3) -+ storw $3,[r12]0xa7a(r5,r4) -+ storw $3,[r12]0xa7a(r6,r5) -+ storw $3,[r12]0xa7a(r7,r6) -+ storw $3,[r12]0xa7a(r9,r8) -+ storw $3,[r12]0xa7a(r11,r10) -+ storw $3,[r13]0xa7a(r1,r0) -+ storw $3,[r13]0xa7a(r3,r2) -+ storw $3,[r13]0xa7a(r4,r3) -+ storw $3,[r13]0xa7a(r5,r4) -+ storw $3,[r13]0xa7a(r6,r5) -+ storw $3,[r13]0xa7a(r7,r6) -+ storw $3,[r13]0xa7a(r9,r8) -+ storw $3,[r13]0xa7a(r11,r10) -+ storw $5,[r13]0xb7a(r4,r3) -+ storw $1,[r12]0x17a(r6,r5) -+ storw $1,[r13]0x134(r6,r5) -+ storw $3,[r12]0xabcde(r4,r3) -+ storw $5,[r13]0xabcd(r4,r3) -+ storw $3,[r12]0xabcd(r6,r5) -+ storw $3,[r13]0xbcde(r6,r5) -+ ####################### -+ # storw imm4, rbase(disp) -+ ###################### -+ storw $5,0x0(r2) -+ storw $3,0x34(r12) -+ storw $3,0xab(r13) -+ storw $5,0xad(r1) -+ storw $5,0xcd(r2) -+ storw $5,0xfff(r0) -+ storw $3,0xbcd(r4) -+ storw $3,0xfff(r12) -+ storw $3,0xfff(r13) -+ storw $3,0xffff(r13) -+ storw $3,0x2343(r12) -+ storw $3,0x12345(r2) -+ storw $3,0x4abcd(r8) -+ storw $3,0xfabcd(r13) -+ storw $3,0xfabcd(r8) -+ storw $3,0xfabcd(r9) -+ storw $3,0x4abcd(r9) -+ ########################## -+ # storw imm, disp20(rpbase) -+ ######################### -+ storw $3,0x0(r2,r1) -+ storw $5,0x1(r2,r1) -+ storw $4,0x1234(r2,r1) -+ storw $3,0x1234(r2,r1) -+ storw $3,0x12345(r2,r1) -+ storw $3,0x123(r2,r1) -+ storw $3,0x12345(r2,r1) -+ ++ .text ++ .global main ++main: ++ ###################### ++ # storw reg abs20/24 ++ ###################### ++ storw r0,0x0 ++ storw r1,0xff ++ storw r3,0xfff ++ storw r4,0x1234 ++ storw r5,0x1234 ++ storw r0,0x7A1234 ++ storw r1,0xBA1234 ++ storw r2,0xffffff ++ ###################### ++ # storw abs20 rel reg ++ ###################### ++ storw r0,[r12]0x0 ++ storw r0,[r13]0x0 ++ storw r1,[r12]0xff ++ storw r1,[r13]0xff ++ storw r3,[r12]0xfff ++ storw r3,[r13]0xfff ++ storw r4,[r12]0x1234 ++ storw r4,[r13]0x1234 ++ storw r5,[r12]0x1234 ++ storw r5,[r13]0x1234 ++ storw r2,[r12]0x4567 ++ storw r2,[r13]0xA1234 ++ ################################### ++ # storw reg rbase(disp20/-disp20) ++ ################################### ++ storw r1,0x4(r1,r0) ++ storw r3,0x4(r3,r2) ++ storw r4,0x1234(r1,r0) ++ storw r5,0x1234(r3,r2) ++ storw r6,0xA1234(r1,r0) ++ storw r1,-0x4(r1,r0) ++ storw r3,-0x4(r3,r2) ++ storw r4,-0x1234(r1,r0) ++ storw r5,-0x1234(r3,r2) ++ storw r6,-0xA1234(r1,r0) ++ ################################################# ++ # storw reg rpbase(disp4/disp16/disp20/-disp20) ++ ################################################# ++ storw r0,0x0(r1,r0) ++ storw r0,0x0(r1,r0) ++ storw r0,0xf(r1,r0) ++ storw r1,0xf(r1,r0) ++ storw r2,0x1234(r1,r0) ++ storw r3,0xabcd(r3,r2) ++ storw r4,0xAfff(r4,r3) ++ storw r5,0xA1234(r6,r5) ++ storw r0,-0xf(r1,r0) ++ storw r1,-0xf(r1,r0) ++ storw r2,-0x1234(r1,r0) ++ storw r3,-0xabcd(r3,r2) ++ storw r4,-0xAfff(r4,r3) ++ storw r5,-0xA1234(r6,r5) ++ #################################### ++ # storw rbase(disp0/disp14) rel reg ++ #################################### ++ storw r0,[r12]0x0(r1,r0) ++ storw r1,[r13]0x0(r1,r0) ++ storw r2,[r12]0x1234(r1,r0) ++ storw r3,[r13]0x1abcd(r1,r0) ++ ################################# ++ # storw reg rpbase(disp20) rel ++ ################################# ++ storw r4,[r12]0xA1234(r1,r0) ++ storw r5,[r13]0xB1234(r1,r0) ++ storw r6,[r13]0xfffff(r1,r0) ++ ####################### ++ # storw reg, uimm16/20 ++ ###################### ++ storw $4,0xbcd ++ storw $5,0xaabcd ++ storw $3,0xfaabcd ++ ++ ####################### ++ # storw reg, uimm16/20 ++ ###################### ++ storw $5,[r12]0x14 ++ storw $4,[r13]0xabfc ++ storw $3,[r12]0x1234 ++ storw $3,[r13]0x1234 ++ storw $3,[r12]0x34 ++ ####################### ++ # storw imm, index-rbase ++ ###################### ++ storw $3,[r12]0xa7a(r1,r0) ++ storw $3,[r12]0xa7a(r3,r2) ++ storw $3,[r12]0xa7a(r4,r3) ++ storw $3,[r12]0xa7a(r5,r4) ++ storw $3,[r12]0xa7a(r6,r5) ++ storw $3,[r12]0xa7a(r7,r6) ++ storw $3,[r12]0xa7a(r9,r8) ++ storw $3,[r12]0xa7a(r11,r10) ++ storw $3,[r13]0xa7a(r1,r0) ++ storw $3,[r13]0xa7a(r3,r2) ++ storw $3,[r13]0xa7a(r4,r3) ++ storw $3,[r13]0xa7a(r5,r4) ++ storw $3,[r13]0xa7a(r6,r5) ++ storw $3,[r13]0xa7a(r7,r6) ++ storw $3,[r13]0xa7a(r9,r8) ++ storw $3,[r13]0xa7a(r11,r10) ++ storw $5,[r13]0xb7a(r4,r3) ++ storw $1,[r12]0x17a(r6,r5) ++ storw $1,[r13]0x134(r6,r5) ++ storw $3,[r12]0xabcde(r4,r3) ++ storw $5,[r13]0xabcd(r4,r3) ++ storw $3,[r12]0xabcd(r6,r5) ++ storw $3,[r13]0xbcde(r6,r5) ++ ####################### ++ # storw imm4, rbase(disp) ++ ###################### ++ storw $5,0x0(r2) ++ storw $3,0x34(r12) ++ storw $3,0xab(r13) ++ storw $5,0xad(r1) ++ storw $5,0xcd(r2) ++ storw $5,0xfff(r0) ++ storw $3,0xbcd(r4) ++ storw $3,0xfff(r12) ++ storw $3,0xfff(r13) ++ storw $3,0xffff(r13) ++ storw $3,0x2343(r12) ++ storw $3,0x12345(r2) ++ storw $3,0x4abcd(r8) ++ storw $3,0xfabcd(r13) ++ storw $3,0xfabcd(r8) ++ storw $3,0xfabcd(r9) ++ storw $3,0x4abcd(r9) ++ ########################## ++ # storw imm, disp20(rpbase) ++ ######################### ++ storw $3,0x0(r2,r1) ++ storw $5,0x1(r2,r1) ++ storw $4,0x1234(r2,r1) ++ storw $3,0x1234(r2,r1) ++ storw $3,0x12345(r2,r1) ++ storw $3,0x123(r2,r1) ++ storw $3,0x12345(r2,r1) ++ diff --git a/gas/testsuite/gas/cr16/sub_test.d b/gas/testsuite/gas/cr16/sub_test.d new file mode 100644 index 0000000..1744836 @@ -1109602,11 +1116792,11 @@ index 0000000..5a937c0 + move.d r7,[r8]@ move.d r9,[r8] diff --git a/gas/testsuite/gas/cris/cris.exp b/gas/testsuite/gas/cris/cris.exp new file mode 100644 -index 0000000..0086cc9 +index 0000000..f0bfd3a --- /dev/null +++ b/gas/testsuite/gas/cris/cris.exp @@ -0,0 +1,562 @@ -+# Copyright 1999, 2000, 2002, 2005, 2007 Free Software Foundation, Inc. ++# Copyright (C) 1999-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1119896,12 +1127086,11 @@ index 0000000..e05701b +^[ ]+\.\.\. diff --git a/gas/testsuite/gas/crx/allinsn.exp b/gas/testsuite/gas/crx/allinsn.exp new file mode 100644 -index 0000000..574dd89 +index 0000000..71396d2 --- /dev/null +++ b/gas/testsuite/gas/crx/allinsn.exp -@@ -0,0 +1,31 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,30 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1124190,12 +1131379,11 @@ index 0000000..dc32ca1 + diff --git a/gas/testsuite/gas/d10v/d10v.exp b/gas/testsuite/gas/d10v/d10v.exp new file mode 100644 -index 0000000..4f22918 +index 0000000..debd219 --- /dev/null +++ b/gas/testsuite/gas/d10v/d10v.exp -@@ -0,0 +1,106 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,105 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1130590,7 +1137778,7 @@ index 0000000..b96ab46 \ No newline at end of file diff --git a/gas/testsuite/gas/d30v/bittest.l b/gas/testsuite/gas/d30v/bittest.l new file mode 100644 -index 0000000..250003f +index 0000000..c3d029c --- /dev/null +++ b/gas/testsuite/gas/d30v/bittest.l @@ -0,0 +1,53 @@ @@ -1130615,16 +1137803,16 @@ index 0000000..250003f + 10 0000 00F00000 nop -> ldw R1, @\(R2,R3\) + 10 84401083 + 11 0008 04406144 nop || ldw R6, @\(R5,R4\) -+.* Warning:Swapping instruction order ++.* Warning: Swapping instruction order + 11 00F00000 + 12 + 13 0010 00F00000 nop -> BSET R1, R2, R3 + 13 82201083 + 14 0018 80F00000 nop <- BTST F1, R2, R3 -+.* Warning:Executing btst in IU in reverse serial may not work ++.* Warning: Executing btst in IU in reverse serial may not work + 14 02001083 + 15 0020 00F00000 nop || BCLR R1, R2, R3 -+.* Warning:Executing bclr in IU may not work in parallel execution ++.* Warning: Executing bclr in IU may not work in parallel execution + 15 02301083 + 16 0028 00F00000 nop -> BNOT R1, R2, R3 + 16 82101083 @@ -1130632,8 +1137820,8 @@ index 0000000..250003f + 17 80F00000 + 18 + 19 0038 047C0105 bset r1, r2, r3 || moddec r4, 5 -+.* Warning:Executing bset in IU may not work -+.* Warning:Swapping instruction order ++.* Warning: Executing bset in IU may not work ++.* Warning: Swapping instruction order + 19 02201083 + 20 + 21 bset r1, r2, r3 @@ -1130683,12 +1137871,11 @@ index 0000000..b79a56c + bset r1, r2, r3 diff --git a/gas/testsuite/gas/d30v/d30.exp b/gas/testsuite/gas/d30v/d30.exp new file mode 100644 -index 0000000..1d14881 +index 0000000..1ed384c --- /dev/null +++ b/gas/testsuite/gas/d30v/d30.exp -@@ -0,0 +1,39 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,38 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1132244,7 +1139431,7 @@ index 0000000..2a99bf9 + jmp r62 diff --git a/gas/testsuite/gas/d30v/serial.l b/gas/testsuite/gas/d30v/serial.l new file mode 100644 -index 0000000..84b475d +index 0000000..8ee33bf --- /dev/null +++ b/gas/testsuite/gas/d30v/serial.l @@ -0,0 +1,43 @@ @@ -1132262,20 +1139449,20 @@ index 0000000..84b475d + 4 # will never be executed. GAS should detect this. + 5 + 6 \?\?\?\? ........ trap r21 -> add r2, r0, r0 ; right instruction will never be executed. -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 6 ........ + 7 \?\?\?\? 08002000 dbt -> add r2, r0, r0 ; ditto -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 7 00F00000 + 7 00B00000 + 7 00F00000 + 8 \?\?\?\? 08002000 rtd -> add r2, r0, r0 ; ditto -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 8 00F00000 + 8 00A00000 + 8 00F00000 + 9 \?\?\?\? 08002000 reit -> add r2, r0, r0 ; ditto -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 9 00F00000 + 9 00800000 + 9 00F00000 @@ -1132313,7 +1139500,7 @@ index 0000000..0995d63 + mvtsys mod_s, r1 -> add r2, r0, r0 ; OK diff --git a/gas/testsuite/gas/d30v/serial2.l b/gas/testsuite/gas/d30v/serial2.l new file mode 100644 -index 0000000..a799bb9 +index 0000000..327c0f3 --- /dev/null +++ b/gas/testsuite/gas/d30v/serial2.l @@ -0,0 +1,135 @@ @@ -1132346,58 +1139533,58 @@ index 0000000..a799bb9 + 3 .text + 4 + 5 \?\?\?\? ........ bra -3 -> add r3,r0,0 ; Invalid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 5 ........ + 6 \?\?\?\? 08083000 bsr -3 -> add r3,r0,0 ; Invalid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 6 00F00000 + 6 002BFFFF + 6 00F00000 + 7 + 8 \?\?\?\? 08083000 bra/tx -3 -> add r3,r0,0 ; Valid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 8 00F00000 + 8 100BFFFF + 8 00F00000 + 9 \?\?\?\? 08083000 bsr/tx -3 -> add r3,r0,0 ; Valid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 9 00F00000 + 9 102BFFFF + 9 00F00000 + 10 + 11 \?\?\?\? 08083000 bsr -3 -> bsr -10 ; Invalid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 11 00F00000 + 11 002BFFFF + 11 00F00000 + 12 \?\?\?\? 002BFFFE bsr -3 -> bsr/xt -10 ; Invalid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 12 00F00000 + 12 002BFFFF + 12 00F00000 + 13 \?\?\?\? 302BFFFE bsr/tx -3 -> bsr -10 ; Valid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 13 00F00000 + 13 102BFFFF + 13 00F00000 + 14 \?\?\?\? 002BFFFE bsr/tx -3 -> bsr/fx -10 ; Valid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 14 00F00000 + 14 102BFFFF + 14 00F00000 + 15 + 16 \?\?\?\? 202BFFFE bra -3 -> bra 10 ; Invalid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 16 00F00000 + 16 000BFFFF + 16 00F00000 + 17 \?\?\?\? 00080001 bra -3 -> bra/tx 10 ; Invalid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 17 00F00000 + 17 000BFFFF + 17 00F00000 + 18 \?\?\?\? 10080001 bra/tx -3 -> bra 10 ; Valid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + GAS LISTING .* + + @@ -1132405,49 +1139592,49 @@ index 0000000..a799bb9 + 18 100BFFFF + 18 00F00000 + 19 \?\?\?\? 00080001 bra/tx -3 -> bra/fx 10 ; Valid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 19 00F00000 + 19 100BFFFF + 19 00F00000 + 20 + 21 \?\?\?\? 20080001 bsr -3 -> bra 10 ; Invalid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 21 00F00000 + 21 002BFFFF + 21 00F00000 + 22 \?\?\?\? 00080001 bsr -3 -> bra/tx 10 ; Invalid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 22 00F00000 + 22 002BFFFF + 22 00F00000 + 23 \?\?\?\? 10080001 bsr/tx -3 -> bra 10 ; Valid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 23 00F00000 + 23 102BFFFF + 23 00F00000 + 24 \?\?\?\? 00080001 bsr/tx -3 -> bra/fx 10 ; Valid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 24 00F00000 + 24 102BFFFF + 24 00F00000 + 25 + 26 \?\?\?\? 20080001 bra -3 -> bsr 10 ; Invalid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 26 00F00000 + 26 000BFFFF + 26 00F00000 + 27 \?\?\?\? 00280001 bra -3 -> bsr/tx 10 ; Invalid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 27 00F00000 + 27 000BFFFF + 27 00F00000 + 28 \?\?\?\? 10280001 bra/tx -3 -> bsr 10 ; Valid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 28 00F00000 + 28 100BFFFF + 28 00F00000 + 29 \?\?\?\? 00280001 bra/tx -3 -> bsr/fx 10 ; Valid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 29 00F00000 + 29 100BFFFF + 29 00F00000 @@ -1132489,7 +1139676,7 @@ index 0000000..0453159 + bra/tx -3 -> bsr/fx 10 ; Valid diff --git a/gas/testsuite/gas/d30v/serial2O.l b/gas/testsuite/gas/d30v/serial2O.l new file mode 100644 -index 0000000..dc5b9c7 +index 0000000..ed7e71d --- /dev/null +++ b/gas/testsuite/gas/d30v/serial2O.l @@ -0,0 +1,96 @@ @@ -1132512,10 +1139699,10 @@ index 0000000..dc5b9c7 + 3 .text + 4 + 5 \?\?\?\? ........ bra -3 -> add r3,r0,0 ; Invalid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 5 ........ + 6 \?\?\?\? 08083000 bsr -3 -> add r3,r0,0 ; Invalid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 6 00F00000 + 6 002BFFFF + 6 00F00000 @@ -1132528,10 +1139715,10 @@ index 0000000..dc5b9c7 + 9 88083000 + 10 + 11 \?\?\?\? 002BFFFF bsr -3 -> bsr -10 ; Invalid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 11 00F00000 + 12 \?\?\?\? 002BFFFE bsr -3 -> bsr/xt -10 ; Invalid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 12 00F00000 + 12 002BFFFF + 12 00F00000 @@ -1132543,10 +1139730,10 @@ index 0000000..dc5b9c7 + 14 A02BFFFE + 15 + 16 \?\?\?\? 000BFFFF bra -3 -> bra 10 ; Invalid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 16 00F00000 + 17 \?\?\?\? 00080001 bra -3 -> bra/tx 10 ; Invalid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 17 00F00000 + 17 000BFFFF + 17 00F00000 @@ -1132558,10 +1139745,10 @@ index 0000000..dc5b9c7 + 19 A0080001 + 20 + 21 \?\?\?\? 002BFFFF bsr -3 -> bra 10 ; Invalid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 21 00F00000 + 22 \?\?\?\? 00080001 bsr -3 -> bra/tx 10 ; Invalid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 22 00F00000 + 22 002BFFFF + GAS LISTING .* @@ -1132576,10 +1139763,10 @@ index 0000000..dc5b9c7 + 24 A0080001 + 25 + 26 \?\?\?\? 000BFFFF bra -3 -> bsr 10 ; Invalid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 26 00F00000 + 27 \?\?\?\? 00280001 bra -3 -> bsr/tx 10 ; Invalid -+\*\*\*\* Error:Unable to mix instructions as specified ++.* Error: Unable to mix instructions as specified + 27 00F00000 + 27 000BFFFF + 27 00F00000 @@ -1132626,7 +1139813,7 @@ index 0000000..0453159 + bra/tx -3 -> bsr/fx 10 ; Valid diff --git a/gas/testsuite/gas/d30v/warn_oddreg.l b/gas/testsuite/gas/d30v/warn_oddreg.l new file mode 100644 -index 0000000..f1fb43c +index 0000000..3b9d2dd --- /dev/null +++ b/gas/testsuite/gas/d30v/warn_oddreg.l @@ -0,0 +1,40 @@ @@ -1132647,28 +1139834,28 @@ index 0000000..f1fb43c + 3 # and mulx2h + 4 + 5 0000 05681000 st2w r1, @(r0, 0) || nop -+.* Warning:Odd numbered register used as target of multi-register instruction ++.* Warning: Odd numbered register used as target of multi-register instruction + 5 00F00000 + 6 0008 04681000 ld2w r1, @(r0, 0) || nop -+.* Warning:Odd numbered register used as target of multi-register instruction ++.* Warning: Odd numbered register used as target of multi-register instruction + 6 00F00000 + 7 0010 04581000 ld4bh r1, @(r0, 0) || nop -+.* Warning:Odd numbered register used as target of multi-register instruction ++.* Warning: Odd numbered register used as target of multi-register instruction + 7 00F00000 + 8 0018 04D81000 ld4bhu r1, @(r0, 0) || nop -+.* Warning:Odd numbered register used as target of multi-register instruction ++.* Warning: Odd numbered register used as target of multi-register instruction + 8 00F00000 + 9 0020 04381000 ld2h r1, @(r0, 0) || nop -+.* Warning:Odd numbered register used as target of multi-register instruction ++.* Warning: Odd numbered register used as target of multi-register instruction + 9 00F00000 + 10 0028 05581000 st4hb r1, @(r0, 0) || nop -+.* Warning:Odd numbered register used as target of multi-register instruction ++.* Warning: Odd numbered register used as target of multi-register instruction + 10 00F00000 + 11 0030 05381000 st2h r1, @(r0, 0) || nop -+.* Warning:Odd numbered register used as target of multi-register instruction ++.* Warning: Odd numbered register used as target of multi-register instruction + 11 00F00000 + 12 0038 00F00000 nop || mulx2h r1, r5, r6 -+.* Warning:Odd numbered register used as target of multi-register instruction ++.* Warning: Odd numbered register used as target of multi-register instruction + 12 0A101146 diff --git a/gas/testsuite/gas/d30v/warn_oddreg.s b/gas/testsuite/gas/d30v/warn_oddreg.s new file mode 100644 @@ -1132690,12 +1139877,11 @@ index 0000000..c09f750 +nop || mulx2h r1, r5, r6 diff --git a/gas/testsuite/gas/dlx/alltests.exp b/gas/testsuite/gas/dlx/alltests.exp new file mode 100644 -index 0000000..e17e744 +index 0000000..2c9030d --- /dev/null +++ b/gas/testsuite/gas/dlx/alltests.exp -@@ -0,0 +1,28 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,27 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1133409,13 +1140595,13 @@ index 0000000..bae2f63 + diff --git a/gas/testsuite/gas/elf/dwarf2-1.s b/gas/testsuite/gas/elf/dwarf2-1.s new file mode 100644 -index 0000000..887fdd6 +index 0000000..6dd208c --- /dev/null +++ b/gas/testsuite/gas/elf/dwarf2-1.s @@ -0,0 +1,199 @@ +/* This testcase is derived from a similar test in GDB. + -+ Copyright 2009 Free Software Foundation, Inc. ++ Copyright (C) 2009-2014 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by @@ -1133725,13 +1140911,13 @@ index 0000000..b42a2ec + diff --git a/gas/testsuite/gas/elf/dwarf2-2.s b/gas/testsuite/gas/elf/dwarf2-2.s new file mode 100644 -index 0000000..38f62b8 +index 0000000..4c6b1cf --- /dev/null +++ b/gas/testsuite/gas/elf/dwarf2-2.s @@ -0,0 +1,199 @@ +/* This testcase is derived from a similar test in GDB. + -+ Copyright 2009 Free Software Foundation, Inc. ++ Copyright (C) 2009-2014 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by @@ -1134255,11 +1141441,11 @@ index 0000000..1029943 +LEFDE1: diff --git a/gas/testsuite/gas/elf/elf.exp b/gas/testsuite/gas/elf/elf.exp new file mode 100644 -index 0000000..d40e9f3 +index 0000000..a967d2f --- /dev/null +++ b/gas/testsuite/gas/elf/elf.exp @@ -0,0 +1,220 @@ -+# Copyright 2012-2013 Free Software Foundation, Inc. ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1135453,15 +1142639,18 @@ index 0000000..6b8b107 + .byte 0,0,0,0 diff --git a/gas/testsuite/gas/elf/struct.d b/gas/testsuite/gas/elf/struct.d new file mode 100644 -index 0000000..420c6e5 +index 0000000..dac6b56 --- /dev/null +++ b/gas/testsuite/gas/elf/struct.d -@@ -0,0 +1,10 @@ +@@ -0,0 +1,13 @@ +#nm: --extern-only +#name: ELF struct -+ ++# +# Test the .struct pseudo-op. ++# The #... is there to match extra symbols inserted by ++# some toolchains, eg msp430-elf will add _crt0_movedata. + ++#... +0+0 D l1 +0+4 D l2 +0+2 A w1 @@ -1135676,14 +1142865,14 @@ index 0000000..d0a1afd \ No newline at end of file diff --git a/gas/testsuite/gas/elf/warn-2.s b/gas/testsuite/gas/elf/warn-2.s new file mode 100644 -index 0000000..6f4454f +index 0000000..9800cd4 --- /dev/null +++ b/gas/testsuite/gas/elf/warn-2.s @@ -0,0 +1,23 @@ +;# { dg-do assemble } +;# { dg-options "--gdwarf2 --defsym nop_type=0" } +;# { dg-options "--gdwarf2 --defsym nop_type=1" { target ia64-*-* } } -+;# { dg-options "--gdwarf2 --defsym nop_type=2" { target or32-*-* openrisc-*-* } } ++;# { dg-options "--gdwarf2 --defsym nop_type=2" { target or1k*-*-* } } +;# { dg-options "--gdwarf2 --defsym nop_type=3" { target i370-*-* } } + + .offset 40 @@ -1135702,7 +1142891,7 @@ index 0000000..6f4454f + .endif + .endif + -+;# { dg-warning "Warning: dwarf line number information for .* ignored" "" { xfail i370-*-* mcore-*-* mn10200-*-* moxie-*-* openrisc-*-* or32-*-* v850*-*-* } 0 } ++;# { dg-warning "Warning: dwarf line number information for .* ignored" "" { xfail i370-*-* mcore-*-* mn10200-*-* moxie-*-* v850*-*-* } 0 } diff --git a/gas/testsuite/gas/epiphany/addr-syntax.d b/gas/testsuite/gas/epiphany/addr-syntax.d new file mode 100644 index 0000000..d9dc3e6 @@ -1137147,12 +1144336,11 @@ index 0000000..3a8039b + ef2: fc1f 640e bitr.l r31,r15 diff --git a/gas/testsuite/gas/epiphany/allinsn.exp b/gas/testsuite/gas/epiphany/allinsn.exp new file mode 100644 -index 0000000..2503b8f +index 0000000..2428ba1 --- /dev/null +++ b/gas/testsuite/gas/epiphany/allinsn.exp -@@ -0,0 +1,28 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,27 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1140177,12 +1147365,11 @@ index 0000000..2bac763 + 198: 97 30 reti diff --git a/gas/testsuite/gas/fr30/allinsn.exp b/gas/testsuite/gas/fr30/allinsn.exp new file mode 100644 -index 0000000..3c9309d +index 0000000..4cf788e --- /dev/null +++ b/gas/testsuite/gas/fr30/allinsn.exp -@@ -0,0 +1,22 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,21 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1140645,12 +1147832,11 @@ index 0000000..683d24a + reti diff --git a/gas/testsuite/gas/fr30/fr30.exp b/gas/testsuite/gas/fr30/fr30.exp new file mode 100644 -index 0000000..9770bdf +index 0000000..925ba72 --- /dev/null +++ b/gas/testsuite/gas/fr30/fr30.exp -@@ -0,0 +1,22 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,21 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1142339,12 +1149525,11 @@ index 0000000..7b96806 + 898: 81 ec 01 c0 mwcuti fr0,0x0,fr0 diff --git a/gas/testsuite/gas/frv/allinsn.exp b/gas/testsuite/gas/frv/allinsn.exp new file mode 100644 -index 0000000..bb7e4b6 +index 0000000..9f71f0c --- /dev/null +++ b/gas/testsuite/gas/frv/allinsn.exp -@@ -0,0 +1,39 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,38 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1146336,12 +1153521,11 @@ index 0000000..b44a19f + .word 0 diff --git a/gas/testsuite/gas/h8300/h8300-coff.exp b/gas/testsuite/gas/h8300/h8300-coff.exp new file mode 100644 -index 0000000..4b294fb +index 0000000..6db6b17 --- /dev/null +++ b/gas/testsuite/gas/h8300/h8300-coff.exp -@@ -0,0 +1,300 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,299 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1146642,12 +1153826,11 @@ index 0000000..4b294fb +} diff --git a/gas/testsuite/gas/h8300/h8300-elf.exp b/gas/testsuite/gas/h8300/h8300-elf.exp new file mode 100644 -index 0000000..232b593 +index 0000000..198b1d7 --- /dev/null +++ b/gas/testsuite/gas/h8300/h8300-elf.exp -@@ -0,0 +1,301 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,300 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1146949,12 +1154132,11 @@ index 0000000..232b593 +} diff --git a/gas/testsuite/gas/h8300/h8300.exp b/gas/testsuite/gas/h8300/h8300.exp new file mode 100644 -index 0000000..10434b4 +index 0000000..250b4ff --- /dev/null +++ b/gas/testsuite/gas/h8300/h8300.exp -@@ -0,0 +1,2266 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,2265 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1150443,12 +1157625,11 @@ index 0000000..7aef522 + .end diff --git a/gas/testsuite/gas/h8300/t01_mov.exp b/gas/testsuite/gas/h8300/t01_mov.exp new file mode 100644 -index 0000000..2946972 +index 0000000..e452562 --- /dev/null +++ b/gas/testsuite/gas/h8300/t01_mov.exp -@@ -0,0 +1,3031 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,3030 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1153480,1124 +1160661,1123 @@ index 0000000..2946972 + diff --git a/gas/testsuite/gas/h8300/t01_mov.s b/gas/testsuite/gas/h8300/t01_mov.s new file mode 100644 -index 0000000..ff618d9 +index 0000000..c8d35de --- /dev/null +++ b/gas/testsuite/gas/h8300/t01_mov.s @@ -0,0 +1,1106 @@ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+;mov -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ .h8300sx -+ .text -+_start: -+ mov.b #0x12:8,r3h ;f312 -+ mov.b #0x12:8,@er3 ;017d0312 -+ mov.b #0x12:8,@(0x1:2,er3) ;017d1312 -+ mov.b #0x12:8,@-er3 ;017db312 -+ mov.b #0x12:8,@er3+ ;017d8312 -+ mov.b #0x12:8,@er3- ;017da312 -+ mov.b #0x12:8,@+er3 ;017d9312 -+ mov.b #0x12:8,@(0x1234:16,er3) ;017dc3121234 -+ mov.b #0x12:8,@(0x12345678:32,er3) ;017dcb1212345678 -+ mov.b #0x12:8,@(0x1234:16,r3l.b) ;017dd3121234 -+ mov.b #0x12:8,@(0x1234:16,r3.w) ;017de3121234 -+ mov.b #0x12:8,@(0x1234:16,er3.l) ;017df3121234 -+ mov.b #0x12:8,@(0x12345678:32,r3l.b) ;017ddb1212345678 -+ mov.b #0x12:8,@(0x12345678:32,r3.w) ;017deb1212345678 -+ mov.b #0x12:8,@(0x12345678:32,er3.l) ;017dfb1212345678 -+ mov.b #0x12:8,@0x1234:16 ;017d40121234 -+ mov.b #0x12:8,@0x12345678:32 ;017d481212345678 -+ -+ mov.b #0x1:4,@0x1234:16 ;6ad11234 -+ mov.b #0x1:4,@0x12345678:32 ;6af112345678 -+ -+ mov.b r3h,r1h ;0c31 -+ -+ mov.b r3h,@er1 ;6893 -+ mov.b r3h,@(0x1:2,er1) ;01716893 -+ mov.b r3h,@-er1 ;6c93 -+ mov.b r3h,@er1+ ;01736c93 -+ mov.b r3h,@er1- ;01716c93 -+ mov.b r3h,@+er1 ;01726c93 -+ mov.b r3h,@(0x1234:16,er1) ;6e931234 -+ mov.b r3h,@(0x12345678:32,er1) ;78106aa312345678 -+ mov.b r3h,@(0x1234:16,r1l.b) ;01716e931234 -+ mov.b r3h,@(0x1234:16,r1.w) ;01726e931234 -+ mov.b r3h,@(0x1234:16,er1.l) ;01736e931234 -+ mov.b r3h,@(0x12345678:32,r1l.b) ;78116aa312345678 -+ mov.b r3h,@(0x12345678:32,r1.w) ;78126aa312345678 -+ mov.b r3h,@(0x12345678:32,er1.l) ;78136aa312345678 -+ mov.b r3h,@0xffffff12:8 ;3312 -+ mov.b r3h,@0x1234:16 ;6a831234 -+ mov.b r3h,@0x12345678:32 ;6aa312345678 -+ -+ mov.b @er3,r1h ;6831 -+ mov.b @(0x1:2,er3),r1h ;01716831 -+ mov.b @er3+,r1h ;6c31 -+ mov.b @-er3,r1h ;01736c31 -+ mov.b @+er3,r1h ;01716c31 -+ mov.b @er3-,r1h ;01726c31 -+ mov.b @(0x1234:16,er3),r1h ;6e311234 -+ mov.b @(0x12345678:32,er3),r1h ;78306a2112345678 -+ mov.b @(0x1234:16,r3l.b),r1h ;01716e311234 -+ mov.b @(0x1234:16,r3.w),r1h ;01726e311234 -+ mov.b @(0x1234:16,er3.l),r1h ;01736e311234 -+ mov.b @(0x12345678:32,r3l.b),r1h ;78316a2112345678 -+ mov.b @(0x12345678:32,r3.w),r1h ;78326a2112345678 -+ mov.b @(0x12345678:32,er3.l),r1h ;78336a2112345678 -+ mov.b @0xffffff12:8,r3h ;2312 -+ mov.b @0x1234:16,r3h ;6a031234 -+ mov.b @0x12345678:32,r3h ;6a2312345678 -+ -+ mov.b @er3,@er1 ;01780301 -+ mov.b @er3,@(0x1:2,er1) ;01780311 -+ mov.b @er3,@er1+ ;01780381 -+ mov.b @er3,@-er1 ;017803b1 -+ mov.b @er3,@+er1 ;01780391 -+ mov.b @er3,@er1- ;017803a1 -+ mov.b @er3,@(0x1234:16,er1) ;017803c11234 -+ mov.b @er3,@(0x12345678:32,er1) ;017803c912345678 -+ mov.b @er3,@(0x1234:16,r1l.b) ;017803d11234 -+ mov.b @er3,@(0x1234:16,r1.w) ;017803e11234 -+ mov.b @er3,@(0x1234:16,er1.l) ;017803f11234 -+ mov.b @er3,@(0x12345678:32,r1l.b) ;017803d912345678 -+ mov.b @er3,@(0x12345678:32,r1.w) ;017803e912345678 -+ mov.b @er3,@(0x12345678:32,er1.l) ;017803f912345678 -+ mov.b @er3,@0x1234:16 ;017803401234 -+ mov.b @er3,@0x12345678:32 ;0178034812345678 -+ -+ mov.b @(0x1:2,er3),@er1 ;01781301 -+ mov.b @(0x1:2,er3),@(0x1:2,er1) ;01781311 -+ mov.b @(0x1:2,er3),@er1+ ;01781381 -+ mov.b @(0x1:2,er3),@-er1 ;017813b1 -+ mov.b @(0x1:2,er3),@+er1 ;01781391 -+ mov.b @(0x1:2,er3),@er1- ;017813a1 -+ mov.b @(0x1:2,er3),@(0x1234:16,er1) ;017813c11234 -+ mov.b @(0x1:2,er3),@(0x12345678:32,er1) ;017813c912345678 -+ mov.b @(0x1:2,er3),@(0x1234:16,r1l.b) ;017813d11234 -+ mov.b @(0x1:2,er3),@(0x1234:16,r1.w) ;017813e11234 -+ mov.b @(0x1:2,er3),@(0x1234:16,er1.l) ;017813f11234 -+ mov.b @(0x1:2,er3),@(0x12345678:32,r1l.b) ;017813d912345678 -+ mov.b @(0x1:2,er3),@(0x12345678:32,r1.w) ;017813e912345678 -+ mov.b @(0x1:2,er3),@(0x12345678:32,er1.l) ;017813f912345678 -+ mov.b @(0x1:2,er3),@0x1234:16 ;017813401234 -+ mov.b @(0x1:2,er3),@0x12345678:32 ;0178134812345678 -+ -+ mov.b @-er3,@er1 ;0178b301 -+ mov.b @-er3,@(0x1:2,er1) ;0178b311 -+ mov.b @-er3,@er1+ ;0178b381 -+ mov.b @-er3,@-er1 ;0178b3b1 -+ mov.b @-er3,@+er1 ;0178b391 -+ mov.b @-er3,@er1- ;0178b3a1 -+ mov.b @-er3,@(0x1234:16,er1) ;0178b3c11234 -+ mov.b @-er3,@(0x12345678:32,er1) ;0178b3c912345678 -+ mov.b @-er3,@(0x1234:16,r1l.b) ;0178b3d11234 -+ mov.b @-er3,@(0x1234:16,r1.w) ;0178b3e11234 -+ mov.b @-er3,@(0x1234:16,er1.l) ;0178b3f11234 -+ mov.b @-er3,@(0x12345678:32,r1l.b) ;0178b3d912345678 -+ mov.b @-er3,@(0x12345678:32,r1.w) ;0178b3e912345678 -+ mov.b @-er3,@(0x12345678:32,er1.l) ;0178b3f912345678 -+ mov.b @-er3,@0x1234:16 ;0178b3401234 -+ mov.b @-er3,@0x12345678:32 ;0178b34812345678 -+ -+ mov.b @er3+,@er1 ;01788301 -+ mov.b @er3+,@(0x1:2,er1) ;01788311 -+ mov.b @er3+,@er1+ ;01788381 -+ mov.b @er3+,@-er1 ;017883b1 -+ mov.b @er3+,@+er1 ;01788391 -+ mov.b @er3+,@er1- ;017883a1 -+ mov.b @er3+,@(0x1234:16,er1) ;017883c11234 -+ mov.b @er3+,@(0x12345678:32,er1) ;017883c912345678 -+ mov.b @er3+,@(0x1234:16,r1l.b) ;017883d11234 -+ mov.b @er3+,@(0x1234:16,r1.w) ;017883e11234 -+ mov.b @er3+,@(0x1234:16,er1.l) ;017883f11234 -+ mov.b @er3+,@(0x12345678:32,r1l.b) ;017883d912345678 -+ mov.b @er3+,@(0x12345678:32,r1.w) ;017883e912345678 -+ mov.b @er3+,@(0x12345678:32,er1.l) ;017883f912345678 -+ mov.b @er3+,@0x1234:16 ;017883401234 -+ mov.b @er3+,@0x12345678:32 ;0178834812345678 -+ -+ mov.b @er3-,@er1 ;0178a301 -+ mov.b @er3-,@(0x1:2,er1) ;0178a311 -+ mov.b @er3-,@er1+ ;0178a381 -+ mov.b @er3-,@-er1 ;0178a3b1 -+ mov.b @er3-,@+er1 ;0178a391 -+ mov.b @er3-,@er1- ;0178a3a1 -+ mov.b @er3-,@(0x1234:16,er1) ;0178a3c11234 -+ mov.b @er3-,@(0x12345678:32,er1) ;0178a3c912345678 -+ mov.b @er3-,@(0x1234:16,r1l.b) ;0178a3d11234 -+ mov.b @er3-,@(0x1234:16,r1.w) ;0178a3e11234 -+ mov.b @er3-,@(0x1234:16,er1.l) ;0178a3f11234 -+ mov.b @er3-,@(0x12345678:32,r1l.b) ;0178a3d912345678 -+ mov.b @er3-,@(0x12345678:32,r1.w) ;0178a3e912345678 -+ mov.b @er3-,@(0x12345678:32,er1.l) ;0178a3f912345678 -+ mov.b @er3-,@0x1234:16 ;0178a3401234 -+ mov.b @er3-,@0x12345678:32 ;0178a34812345678 -+ -+ mov.b @+er3,@er1 ;01789301 -+ mov.b @+er3,@(0x1:2,er1) ;01789311 -+ mov.b @+er3,@er1+ ;01789381 -+ mov.b @+er3,@-er1 ;017893b1 -+ mov.b @+er3,@+er1 ;01789391 -+ mov.b @+er3,@er1- ;017893a1 -+ mov.b @+er3,@(0x1234:16,er1) ;017893c11234 -+ mov.b @+er3,@(0x12345678:32,er1) ;017893c912345678 -+ mov.b @+er3,@(0x1234:16,r1l.b) ;017893d11234 -+ mov.b @+er3,@(0x1234:16,r1.w) ;017893e11234 -+ mov.b @+er3,@(0x1234:16,er1.l) ;017893f11234 -+ mov.b @+er3,@(0x12345678:32,r1l.b) ;017893d912345678 -+ mov.b @+er3,@(0x12345678:32,r1.w) ;017893e912345678 -+ mov.b @+er3,@(0x12345678:32,er1.l) ;017893f912345678 -+ mov.b @+er3,@0x1234:16 ;017893401234 -+ mov.b @+er3,@0x12345678:32 ;0178934812345678 -+ -+ mov.b @(0x1234:16,er3),@er1 ;0178c3011234 -+ mov.b @(0x1234:16,er3),@(0x1:2,er1) ;0178c3111234 -+ mov.b @(0x1234:16,er3),@er1+ ;0178c3811234 -+ mov.b @(0x1234:16,er3),@-er1 ;0178c3b11234 -+ mov.b @(0x1234:16,er3),@+er1 ;0178c3911234 -+ mov.b @(0x1234:16,er3),@er1- ;0178c3a11234 -+ mov.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;0178c3c112349abc -+ mov.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;0178c3c912349abcdef0 -+ mov.b @(0x1234:16,er3),@(0xffff9abc:16,r1l.b) ;0178c3d112349abc -+ mov.b @(0x1234:16,er3),@(0xffff9abc:16,r1.w) ;0178c3e112349abc -+ mov.b @(0x1234:16,er3),@(0xffff9abc:16,er1.l) ;0178c3f112349abc -+ mov.b @(0x1234:16,er3),@(0x9abcdef0:32,r1l.b) ;0178c3d912349abcdef0 -+ mov.b @(0x1234:16,er3),@(0x9abcdef0:32,r1.w) ;0178c3e912349abcdef0 -+ mov.b @(0x1234:16,er3),@(0x9abcdef0:32,er1.l) ;0178c3f912349abcdef0 -+ mov.b @(0x1234:16,er3),@0xffff9abc:16 ;0178c34012349abc -+ mov.b @(0x1234:16,er3),@0x9abcdef0:32 ;0178c34812349abcdef0 -+ -+ mov.b @(0x12345678:32,er3),@er1 ;0178cb0112345678 -+ mov.b @(0x12345678:32,er3),@(0x1:2,er1) ;0178cb1112345678 -+ mov.b @(0x12345678:32,er3),@er1+ ;0178cb8112345678 -+ mov.b @(0x12345678:32,er3),@-er1 ;0178cbb112345678 -+ mov.b @(0x12345678:32,er3),@+er1 ;0178cb9112345678 -+ mov.b @(0x12345678:32,er3),@er1- ;0178cba112345678 -+ mov.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;0178cbc1123456789abc -+ mov.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;0178cbc9123456789abcdef0 -+ mov.b @(0x12345678:32,er3),@(0xffff9abc:16,r1l.b) ;0178cbd1123456789abc -+ mov.b @(0x12345678:32,er3),@(0xffff9abc:16,r1.w) ;0178cbe1123456789abc -+ mov.b @(0x12345678:32,er3),@(0xffff9abc:16,er1.l) ;0178cbf1123456789abc -+ mov.b @(0x12345678:32,er3),@(0x9abcdef0:32,r1l.b) ;0178cbd9123456789abcdef0 -+ mov.b @(0x12345678:32,er3),@(0x9abcdef0:32,r1.w) ;0178cbe9123456789abcdef0 -+ mov.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1.l) ;0178cbf9123456789abcdef0 -+ mov.b @(0x12345678:32,er3),@0xffff9abc:16 ;0178cb40123456789abc -+ mov.b @(0x12345678:32,er3),@0x9abcdef0:32 ;0178cb48123456789abcdef0 -+ -+ mov.b @(0x1234:16,r3l.b),@er1 ;0178d3011234 -+ mov.b @(0x1234:16,r3l.b),@(0x1:2,er1) ;0178d3111234 -+ mov.b @(0x1234:16,r3l.b),@er1+ ;0178d3811234 -+ mov.b @(0x1234:16,r3l.b),@-er1 ;0178d3b11234 -+ mov.b @(0x1234:16,r3l.b),@+er1 ;0178d3911234 -+ mov.b @(0x1234:16,r3l.b),@er1- ;0178d3a11234 -+ mov.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r1l.b) ;0178d3d112349abc -+ mov.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r1.w) ;0178d3e112349abc -+ mov.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1.l) ;0178d3f112349abc -+ mov.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r1l.b) ;0178d3d912349abcdef0 -+ mov.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r1.w) ;0178d3e912349abcdef0 -+ mov.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1.l) ;0178d3f912349abcdef0 -+ mov.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;0178d34012349abc -+ mov.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;0178d34812349abcdef0 -+ -+ mov.b @(0x1234:16,r3.w),@er1 ;0178e3011234 -+ mov.b @(0x1234:16,r3.w),@(0x1:2,er1) ;0178e3111234 -+ mov.b @(0x1234:16,r3.w),@er1+ ;0178e3811234 -+ mov.b @(0x1234:16,r3.w),@-er1 ;0178e3b11234 -+ mov.b @(0x1234:16,r3.w),@+er1 ;0178e3911234 -+ mov.b @(0x1234:16,r3.w),@er1- ;0178e3a11234 -+ mov.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;0178e3c112349abc -+ mov.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;0178e3c912349abcdef0 -+ mov.b @(0x1234:16,r3.w),@(0xffff9abc:16,r3l.b) ;0178e3d312349abc -+ mov.b @(0x1234:16,r3.w),@(0xffff9abc:16,r3.w) ;0178e3e312349abc -+ mov.b @(0x1234:16,r3.w),@(0xffff9abc:16,er3.l) ;0178e3f312349abc -+ mov.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r3l.b) ;0178e3db12349abcdef0 -+ mov.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r3.w) ;0178e3eb12349abcdef0 -+ mov.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er3.l) ;0178e3fb12349abcdef0 -+ mov.b @(0x1234:16,r3.w),@0xffff9abc:16 ;0178e34012349abc -+ mov.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;0178e34812349abcdef0 -+ -+ mov.b @(0x1234:16,er3.l),@er1 ;0178f3011234 -+ mov.b @(0x1234:16,er3.l),@(0x1:2,er1) ;0178f3111234 -+ mov.b @(0x1234:16,er3.l),@er1+ ;0178f3811234 -+ mov.b @(0x1234:16,er3.l),@-er1 ;0178f3b11234 -+ mov.b @(0x1234:16,er3.l),@+er1 ;0178f3911234 -+ mov.b @(0x1234:16,er3.l),@er1- ;0178f3a11234 -+ mov.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;0178f3c112349abc -+ mov.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;0178f3c912349abcdef0 -+ mov.b @(0x1234:16,er3.l),@(0xffff9abc:16,r3l.b) ;0178f3d312349abc -+ mov.b @(0x1234:16,er3.l),@(0xffff9abc:16,r3.w) ;0178f3e312349abc -+ mov.b @(0x1234:16,er3.l),@(0xffff9abc:16,er3.l) ;0178f3f312349abc -+ mov.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r3l.b) ;0178f3db12349abcdef0 -+ mov.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r3.w) ;0178f3eb12349abcdef0 -+ mov.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er3.l) ;0178f3fb12349abcdef0 -+ mov.b @(0x1234:16,er3.l),@0xffff9abc:16 ;0178f34012349abc -+ mov.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;0178f34812349abcdef0 -+ -+ mov.b @(0x12345678:32,r3l.b),@er1 ;0178db0112345678 -+ mov.b @(0x12345678:32,r3l.b),@(0x1:2,er1) ;0178db1112345678 -+ mov.b @(0x12345678:32,r3l.b),@er1+ ;0178db8112345678 -+ mov.b @(0x12345678:32,r3l.b),@-er1 ;0178dbb112345678 -+ mov.b @(0x12345678:32,r3l.b),@+er1 ;0178db9112345678 -+ mov.b @(0x12345678:32,r3l.b),@er1- ;0178dba112345678 -+ mov.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;0178dbc1123456789abc -+ mov.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;0178dbc9123456789abcdef0 -+ mov.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r3l.b) ;0178dbd3123456789abc -+ mov.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r3.w) ;0178dbe3123456789abc -+ mov.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er3.l) ;0178dbf3123456789abc -+ mov.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3l.b) ;0178dbdb123456789abcdef0 -+ mov.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3.w) ;0178dbeb123456789abcdef0 -+ mov.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er3.l) ;0178dbfb123456789abcdef0 -+ mov.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;0178db40123456789abc -+ mov.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;0178db48123456789abcdef0 -+ -+ mov.b @(0x12345678:32,r3.w),@er1 ;0178eb0112345678 -+ mov.b @(0x12345678:32,r3.w),@(0x1:2,er1) ;0178eb1112345678 -+ mov.b @(0x12345678:32,r3.w),@er1+ ;0178eb8112345678 -+ mov.b @(0x12345678:32,r3.w),@-er1 ;0178ebb112345678 -+ mov.b @(0x12345678:32,r3.w),@+er1 ;0178eb9112345678 -+ mov.b @(0x12345678:32,r3.w),@er1- ;0178eba112345678 -+ mov.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;0178ebc1123456789abc -+ mov.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;0178ebc9123456789abcdef0 -+ mov.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r3l.b) ;0178ebd3123456789abc -+ mov.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r3.w) ;0178ebe3123456789abc -+ mov.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er3.l) ;0178ebf3123456789abc -+ mov.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3l.b) ;0178ebdb123456789abcdef0 -+ mov.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3.w) ;0178ebeb123456789abcdef0 -+ mov.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er3.l) ;0178ebfb123456789abcdef0 -+ mov.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;0178eb40123456789abc -+ mov.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;0178eb48123456789abcdef0 -+ -+ mov.b @(0x12345678:32,er3.l),@er1 ;0178fb0112345678 -+ mov.b @(0x12345678:32,er3.l),@(0x1:2,er1) ;0178fb1112345678 -+ mov.b @(0x12345678:32,er3.l),@er1+ ;0178fb8112345678 -+ mov.b @(0x12345678:32,er3.l),@-er1 ;0178fbb112345678 -+ mov.b @(0x12345678:32,er3.l),@+er1 ;0178fb9112345678 -+ mov.b @(0x12345678:32,er3.l),@er1- ;0178fba112345678 -+ mov.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;0178fbc1123456789abc -+ mov.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;0178fbc9123456789abcdef0 -+ mov.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r3l.b) ;0178fbd3123456789abc -+ mov.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r3.w) ;0178fbe3123456789abc -+ mov.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er3.l) ;0178fbf3123456789abc -+ mov.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3l.b) ;0178fbdb123456789abcdef0 -+ mov.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3.w) ;0178fbeb123456789abcdef0 -+ mov.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er3.l) ;0178fbfb123456789abcdef0 -+ mov.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;0178fb40123456789abc -+ mov.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;0178fb48123456789abcdef0 -+ -+ mov.b @0x1234:16,@er1 ;017840011234 -+ mov.b @0x1234:16,@(0x1:2,er1) ;017840111234 -+ mov.b @0x1234:16,@er1+ ;017840811234 -+ mov.b @0x1234:16,@-er1 ;017840b11234 -+ mov.b @0x1234:16,@+er1 ;017840911234 -+ mov.b @0x1234:16,@er1- ;017840a11234 -+ mov.b @0x1234:16,@(0xffff9abc:16,er1) ;017840c112349abc -+ mov.b @0x1234:16,@(0x9abcdef0:32,er1) ;017840c912349abcdef0 -+ mov.b @0x1234:16,@(0xffff9abc:16,r3l.b) ;017840d312349abc -+ mov.b @0x1234:16,@(0xffff9abc:16,r3.w) ;017840e312349abc -+ mov.b @0x1234:16,@(0xffff9abc:16,er3.l) ;017840f312349abc -+ mov.b @0x1234:16,@(0x9abcdef0:32,r3l.b) ;017840db12349abcdef0 -+ mov.b @0x1234:16,@(0x9abcdef0:32,r3.w) ;017840eb12349abcdef0 -+ mov.b @0x1234:16,@(0x9abcdef0:32,er3.l) ;017840fb12349abcdef0 -+ mov.b @0x1234:16,@0xffff9abc:16 ;0178404012349abc -+ mov.b @0x1234:16,@0x9abcdef0:32 ;0178404812349abcdef0 -+ -+ mov.b @0x12345678:32,@er1 ;0178480112345678 -+ mov.b @0x12345678:32,@(0x1:2,er1) ;0178481112345678 -+ mov.b @0x12345678:32,@er1+ ;0178488112345678 -+ mov.b @0x12345678:32,@-er1 ;017848b112345678 -+ mov.b @0x12345678:32,@+er1 ;0178489112345678 -+ mov.b @0x12345678:32,@er1- ;017848a112345678 -+ mov.b @0x12345678:32,@(0xffff9abc:16,er1) ;017848c1123456789abc -+ mov.b @0x12345678:32,@(0x9abcdef0:32,er1) ;017848c9123456789abcdef0 -+ mov.b @0x12345678:32,@(0xffff9abc:16,r3l.b) ;017848d3123456789abc -+ mov.b @0x12345678:32,@(0xffff9abc:16,r3.w) ;017848e3123456789abc -+ mov.b @0x12345678:32,@(0xffff9abc:16,er3.l) ;017848f3123456789abc -+ mov.b @0x12345678:32,@(0x9abcdef0:32,r3l.b) ;017848db123456789abcdef0 -+ mov.b @0x12345678:32,@(0x9abcdef0:32,r3.w) ;017848eb123456789abcdef0 -+ mov.b @0x12345678:32,@(0x9abcdef0:32,er3.l) ;017848fb123456789abcdef0 -+ mov.b @0x12345678:32,@0xffff9abc:16 ;01784840123456789abc -+ mov.b @0x12345678:32,@0x9abcdef0:32 ;01784848123456789abcdef0 -+ -+ mov.w #0x1234:16,r1 ;79011234 -+ mov.w #0x1:3,r3 ;0f13 -+ mov.w #0x1234:16,@er1 ;797412340100 -+ mov.w #0x1234:16,@(0x2:2,er1) ;797412341100 -+ mov.w #0x1234:16,@er1+ ;797412348100 -+ mov.w #0x1234:16,@-er1 ;79741234b100 -+ mov.w #0x1234:16,@+er1 ;797412349100 -+ mov.w #0x1234:16,@er1- ;79741234a100 -+ mov.w #0x1234:16,@(0x1234:16,er1) ;79741234c1001234 -+ mov.w #0x1234:16,@(0x12345678:32,er1) ;79741234c90012345678 -+ mov.w #0x1234:16,@(0x1234:16,r3l.b) ;79741234d3001234 -+ mov.w #0x1234:16,@(0x1234:16,r3.w) ;79741234e3001234 -+ mov.w #0x1234:16,@(0x1234:16,er3.l) ;79741234f3001234 -+ mov.w #0x1234:16,@(0x12345678:32,r3l.b) ;79741234db0012345678 -+ mov.w #0x1234:16,@(0x12345678:32,r3.w) ;79741234eb0012345678 -+ mov.w #0x1234:16,@(0x12345678:32,er3.l) ;79741234fb0012345678 -+ mov.w #0x1234:16,@0x1234:16 ;7974123440001234 -+ mov.w #0x1234:16,@0x12345678:32 ;79741234480012345678 -+ -+ mov.w #0x12:8,@er1 ;015d0112 -+ mov.w #0x12:8,@(0x2:2,er1) ;015d1112 -+ mov.w #0x12:8,@er1+ ;015d8112 -+ mov.w #0x12:8,@-er1 ;015db112 -+ mov.w #0x12:8,@+er1 ;015d9112 -+ mov.w #0x12:8,@er1- ;015da112 -+ mov.w #0x12:8,@(0x1234:16,er1) ;015dc1121234 -+ mov.w #0x12:8,@(0x12345678:32,er1) ;015dc91212345678 -+ mov.w #0x12:8,@(0x1234:16,r3l.b) ;015dd3121234 -+ mov.w #0x12:8,@(0x1234:16,r3.w) ;015de3121234 -+ mov.w #0x12:8,@(0x1234:16,er3.l) ;015df3121234 -+ mov.w #0x12:8,@(0x12345678:32,r3l.b) ;015ddb1212345678 -+ mov.w #0x12:8,@(0x12345678:32,r3.w) ;015deb1212345678 -+ mov.w #0x12:8,@(0x12345678:32,er3.l) ;015dfb1212345678 -+ mov.w #0x12:8,@0x1234:16 ;015d40121234 -+ mov.w #0x12:8,@0x12345678:32 ;015d481212345678 -+ -+ mov.w #0x1:4,@0x1234:16 ;6bd11234 -+ mov.w #0x1:4,@0x12345678:32 ;6bf112345678 -+ -+ mov.w r2,r1 ;0d21 -+ -+ mov.w r2,@er1 ;6992 -+ mov.w r2,@(0x2:2,er1) ;01516992 -+ mov.w r2,@er1+ ;01536d92 -+ mov.w r2,@-er1 ;6d92 -+ mov.w r2,@+er1 ;01526d92 -+ mov.w r2,@er1- ;01516d92 -+ mov.w r2,@(0x1234:16,er1) ;6f921234 -+ mov.w r2,@(0x12345678:32,er1) ;78106ba212345678 -+ mov.w r2,@(0x1234:16,r3l.b) ;01516fb21234 -+ mov.w r2,@(0x1234:16,r3.w) ;01526fb21234 -+ mov.w r2,@(0x1234:16,er3.l) ;01536fb21234 -+ mov.w r2,@(0x12345678:32,r3l.b) ;78316ba212345678 -+ mov.w r2,@(0x12345678:32,r3.w) ;78326ba212345678 -+ mov.w r2,@(0x12345678:32,er3.l) ;78336ba212345678 -+ mov.w r2,@0x1234:16 ;6b821234 -+ mov.w r2,@0x12345678:32 ;6ba212345678 -+ -+ mov.w @er2,r1 ;6921 -+ mov.w @(0x2:2,er2),r1 ;01516921 -+ mov.w @er2+,r1 ;6d21 -+ mov.w @-er2,r1 ;01536d21 -+ mov.w @+er2,r1 ;01516d21 -+ mov.w @er2-,r1 ;01526d21 -+ mov.w @(0x1234:16,er1),r1 ;6f111234 -+ mov.w @(0x12345678:32,er1),r1 ;78106b2112345678 -+ mov.w @(0x1234:16,r3l.b),r1 ;01516f311234 -+ mov.w @(0x1234:16,r3.w),r1 ;01526f311234 -+ mov.w @(0x1234:16,er3.l),r1 ;01536f311234 -+ mov.w @(0x12345678:32,r3l.b),r1 ;78316b2112345678 -+ mov.w @(0x12345678:32,r3.w),r1 ;78326b2112345678 -+ mov.w @(0x12345678:32,er3.l),r1 ;78336b2112345678 -+ mov.w @0x1234:16,r1 ;6b011234 -+ mov.w @0x12345678:32,r1 ;6b2112345678 -+ -+ mov.w @er2,@er1 ;01580201 -+ mov.w @er2,@(0x2:2,er1) ;01580211 -+ mov.w @er2,@er1+ ;01580281 -+ mov.w @er2,@-er1 ;015802b1 -+ mov.w @er2,@+er1 ;01580291 -+ mov.w @er2,@er1- ;015802a1 -+ mov.w @er2,@(0x1234:16,er1) ;015802c11234 -+ mov.w @er2,@(0x12345678:32,er1) ;015802c912345678 -+ mov.w @er2,@(0x1234:16,r3l.b) ;015802d31234 -+ mov.w @er2,@(0x1234:16,r3.w) ;015802e31234 -+ mov.w @er2,@(0x1234:16,er3.l) ;015802f31234 -+ mov.w @er2,@(0x12345678:32,r3l.b) ;015802db12345678 -+ mov.w @er2,@(0x12345678:32,r3.w) ;015802eb12345678 -+ mov.w @er2,@(0x12345678:32,er3.l) ;015802fb12345678 -+ mov.w @er2,@0x1234:16 ;015802401234 -+ mov.w @er2,@0x12345678:32 ;0158024812345678 -+ -+ mov.w @(0x2:2,er2),@er1 ;01581201 -+ mov.w @(0x2:2,er2),@(0x2:2,er1) ;01581211 -+ mov.w @(0x2:2,er2),@er1+ ;01581281 -+ mov.w @(0x2:2,er2),@-er1 ;015812b1 -+ mov.w @(0x2:2,er2),@+er1 ;01581291 -+ mov.w @(0x2:2,er2),@er1- ;015812a1 -+ mov.w @(0x2:2,er2),@(0x1234:16,er1) ;015812c11234 -+ mov.w @(0x2:2,er2),@(0x12345678:32,er1) ;015812c912345678 -+ mov.w @(0x2:2,er2),@(0x1234:16,r3l.b) ;015812d31234 -+ mov.w @(0x2:2,er2),@(0x1234:16,r3.w) ;015812e31234 -+ mov.w @(0x2:2,er2),@(0x1234:16,er3.l) ;015812f31234 -+ mov.w @(0x2:2,er2),@(0x12345678:32,r3l.b) ;015812db12345678 -+ mov.w @(0x2:2,er2),@(0x12345678:32,r3.w) ;015812eb12345678 -+ mov.w @(0x2:2,er2),@(0x12345678:32,er3.l) ;015812fb12345678 -+ mov.w @(0x2:2,er2),@0x1234:16 ;015812401234 -+ mov.w @(0x2:2,er2),@0x12345678:32 ;0158124812345678 -+ -+ mov.w @-er2,@er1 ;0158b201 -+ mov.w @-er2,@(0x2:2,er1) ;0158b211 -+ mov.w @-er2,@er1+ ;0158b281 -+ mov.w @-er2,@-er1 ;0158b2b1 -+ mov.w @-er2,@+er1 ;0158b291 -+ mov.w @-er2,@er1- ;0158b2a1 -+ mov.w @-er2,@(0x1234:16,er1) ;0158b2c11234 -+ mov.w @-er2,@(0x12345678:32,er1) ;0158b2c912345678 -+ mov.w @-er2,@(0x1234:16,r3l.b) ;0158b2d31234 -+ mov.w @-er2,@(0x1234:16,r3.w) ;0158b2e31234 -+ mov.w @-er2,@(0x1234:16,er3.l) ;0158b2f31234 -+ mov.w @-er2,@(0x12345678:32,r3l.b) ;0158b2db12345678 -+ mov.w @-er2,@(0x12345678:32,r3.w) ;0158b2eb12345678 -+ mov.w @-er2,@(0x12345678:32,er3.l) ;0158b2fb12345678 -+ mov.w @-er2,@0x1234:16 ;0158b2401234 -+ mov.w @-er2,@0x12345678:32 ;0158b24812345678 -+ -+ mov.w @er2+,@er1 ;01588201 -+ mov.w @er2+,@(0x2:2,er1) ;01588211 -+ mov.w @er2+,@er1+ ;01588281 -+ mov.w @er2+,@-er1 ;015882b1 -+ mov.w @er2+,@+er1 ;01588291 -+ mov.w @er2+,@er1- ;015882a1 -+ mov.w @er2+,@(0x1234:16,er1) ;015882c11234 -+ mov.w @er2+,@(0x12345678:32,er1) ;015882c912345678 -+ mov.w @er2+,@(0x1234:16,r3l.b) ;015882d31234 -+ mov.w @er2+,@(0x1234:16,r3.w) ;015882e31234 -+ mov.w @er2+,@(0x1234:16,er3.l) ;015882f31234 -+ mov.w @er2+,@(0x12345678:32,r3l.b) ;015882db12345678 -+ mov.w @er2+,@(0x12345678:32,r3.w) ;015882eb12345678 -+ mov.w @er2+,@(0x12345678:32,er3.l) ;015882fb12345678 -+ mov.w @er2+,@0x1234:16 ;015882401234 -+ mov.w @er2+,@0x12345678:32 ;0158824812345678 -+ -+ mov.w @er2-,@er1 ;0158a201 -+ mov.w @er2-,@(0x2:2,er1) ;0158a211 -+ mov.w @er2-,@er1+ ;0158a281 -+ mov.w @er2-,@-er1 ;0158a2b1 -+ mov.w @er2-,@+er1 ;0158a291 -+ mov.w @er2-,@er1- ;0158a2a1 -+ mov.w @er2-,@(0x1234:16,er1) ;0158a2c11234 -+ mov.w @er2-,@(0x12345678:32,er1) ;0158a2c912345678 -+ mov.w @er2-,@(0x1234:16,r3l.b) ;0158a2d31234 -+ mov.w @er2-,@(0x1234:16,r3.w) ;0158a2e31234 -+ mov.w @er2-,@(0x1234:16,er3.l) ;0158a2f31234 -+ mov.w @er2-,@(0x12345678:32,r3l.b) ;0158a2db12345678 -+ mov.w @er2-,@(0x12345678:32,r3.w) ;0158a2eb12345678 -+ mov.w @er2-,@(0x12345678:32,er3.l) ;0158a2fb12345678 -+ mov.w @er2-,@0x1234:16 ;0158a2401234 -+ mov.w @er2-,@0x12345678:32 ;0158a24812345678 -+ -+ mov.w @+er2,@er1 ;01589201 -+ mov.w @+er2,@(0x2:2,er1) ;01589211 -+ mov.w @+er2,@er1+ ;01589281 -+ mov.w @+er2,@-er1 ;015892b1 -+ mov.w @+er2,@+er1 ;01589291 -+ mov.w @+er2,@er1- ;015892a1 -+ mov.w @+er2,@(0x1234:16,er1) ;015892c11234 -+ mov.w @+er2,@(0x12345678:32,er1) ;015892c912345678 -+ mov.w @+er2,@(0x1234:16,r3l.b) ;015892d31234 -+ mov.w @+er2,@(0x1234:16,r3.w) ;015892e31234 -+ mov.w @+er2,@(0x1234:16,er3.l) ;015892f31234 -+ mov.w @+er2,@(0x12345678:32,r3l.b) ;015892db12345678 -+ mov.w @+er2,@(0x12345678:32,r3.w) ;015892eb12345678 -+ mov.w @+er2,@(0x12345678:32,er3.l) ;015892fb12345678 -+ mov.w @+er2,@0x1234:16 ;015892401234 -+ mov.w @+er2,@0x12345678:32 ;0158924812345678 -+ -+ mov.w @(0x1234:16,er2),@er1 ;0158c2011234 -+ mov.w @(0x1234:16,er2),@(0x2:2,er1) ;0158c2111234 -+ mov.w @(0x1234:16,er2),@er1+ ;0158c2811234 -+ mov.w @(0x1234:16,er2),@-er1 ;0158c2b11234 -+ mov.w @(0x1234:16,er2),@+er1 ;0158c2911234 -+ mov.w @(0x1234:16,er2),@er1- ;0158c2a11234 -+ mov.w @(0x1234:16,er2),@(0xffff9abc:16,er1) ;0158c2c112349abc -+ mov.w @(0x1234:16,er2),@(0x9abcdef0:32,er1) ;0158c2c912349abcdef0 -+ mov.w @(0x1234:16,er2),@(0xffff9abc:16,r3l.b) ;0158c2d312349abc -+ mov.w @(0x1234:16,er2),@(0xffff9abc:16,r3.w) ;0158c2e312349abc -+ mov.w @(0x1234:16,er2),@(0xffff9abc:16,er3.l) ;0158c2f312349abc -+ mov.w @(0x1234:16,er2),@(0x9abcdef0:32,r3l.b) ;0158c2db12349abcdef0 -+ mov.w @(0x1234:16,er2),@(0x9abcdef0:32,r3.w) ;0158c2eb12349abcdef0 -+ mov.w @(0x1234:16,er2),@(0x9abcdef0:32,er3.l) ;0158c2fb12349abcdef0 -+ mov.w @(0x1234:16,er2),@0xffff9abc:16 ;0158c24012349abc -+ mov.w @(0x1234:16,er2),@0x9abcdef0:32 ;0158c24812349abcdef0 -+ -+ mov.w @(0x12345678:32,er2),@er1 ;0158ca0112345678 -+ mov.w @(0x12345678:32,er2),@(0x2:2,er1) ;0158ca1112345678 -+ mov.w @(0x12345678:32,er2),@er1+ ;0158ca8112345678 -+ mov.w @(0x12345678:32,er2),@-er1 ;0158cab112345678 -+ mov.w @(0x12345678:32,er2),@+er1 ;0158ca9112345678 -+ mov.w @(0x12345678:32,er2),@er1- ;0158caa112345678 -+ mov.w @(0x12345678:32,er2),@(0xffff9abc:16,er1) ;0158cac1123456789abc -+ mov.w @(0x12345678:32,er2),@(0x9abcdef0:32,er1) ;0158cac9123456789abcdef0 -+ mov.w @(0x12345678:32,er2),@(0xffff9abc:16,r3l.b) ;0158cad3123456789abc -+ mov.w @(0x12345678:32,er2),@(0xffff9abc:16,r3.w) ;0158cae3123456789abc -+ mov.w @(0x12345678:32,er2),@(0xffff9abc:16,er3.l) ;0158caf3123456789abc -+ mov.w @(0x12345678:32,er2),@(0x9abcdef0:32,r3l.b) ;0158cadb123456789abcdef0 -+ mov.w @(0x12345678:32,er2),@(0x9abcdef0:32,r3.w) ;0158caeb123456789abcdef0 -+ mov.w @(0x12345678:32,er2),@(0x9abcdef0:32,er3.l) ;0158cafb123456789abcdef0 -+ mov.w @(0x12345678:32,er2),@0xffff9abc:16 ;0158ca40123456789abc -+ mov.w @(0x12345678:32,er2),@0x9abcdef0:32 ;0158ca48123456789abcdef0 -+ -+ mov.w @(0x1234:16,r3l.b),@er1 ;0158d3011234 -+ mov.w @(0x1234:16,r3l.b),@(0x2:2,er1) ;0158d3111234 -+ mov.w @(0x1234:16,r3l.b),@er1+ ;0158d3811234 -+ mov.w @(0x1234:16,r3l.b),@-er1 ;0158d3b11234 -+ mov.w @(0x1234:16,r3l.b),@+er1 ;0158d3911234 -+ mov.w @(0x1234:16,r3l.b),@er1- ;0158d3a11234 -+ mov.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;0158d3c112349abc -+ mov.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;0158d3c912349abcdef0 -+ mov.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r3l.b) ;0158d3d312349abc -+ mov.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r3.w) ;0158d3e312349abc -+ mov.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er3.l) ;0158d3f312349abc -+ mov.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r3l.b) ;0158d3db12349abcdef0 -+ mov.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r3.w) ;0158d3eb12349abcdef0 -+ mov.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er3.l) ;0158d3fb12349abcdef0 -+ mov.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;0158d34012349abc -+ mov.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;0158d34812349abcdef0 -+ -+ mov.w @(0x1234:16,r3.w),@er1 ;0158e3011234 -+ mov.w @(0x1234:16,r3.w),@(0x2:2,er1) ;0158e3111234 -+ mov.w @(0x1234:16,r3.w),@er1+ ;0158e3811234 -+ mov.w @(0x1234:16,r3.w),@-er1 ;0158e3b11234 -+ mov.w @(0x1234:16,r3.w),@+er1 ;0158e3911234 -+ mov.w @(0x1234:16,r3.w),@er1- ;0158e3a11234 -+ mov.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;0158e3c112349abc -+ mov.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;0158e3c912349abcdef0 -+ mov.w @(0x1234:16,r3.w),@(0xffff9abc:16,r3l.b) ;0158e3d312349abc -+ mov.w @(0x1234:16,r3.w),@(0xffff9abc:16,r3.w) ;0158e3e312349abc -+ mov.w @(0x1234:16,r3.w),@(0xffff9abc:16,er3.l) ;0158e3f312349abc -+ mov.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r3l.b) ;0158e3db12349abcdef0 -+ mov.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r3.w) ;0158e3eb12349abcdef0 -+ mov.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er3.l) ;0158e3fb12349abcdef0 -+ mov.w @(0x1234:16,r3.w),@0xffff9abc:16 ;0158e34012349abc -+ mov.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;0158e34812349abcdef0 -+ -+ mov.w @(0x1234:16,er3.l),@er1 ;0158f3011234 -+ mov.w @(0x1234:16,er3.l),@(0x2:2,er1) ;0158f3111234 -+ mov.w @(0x1234:16,er3.l),@er1+ ;0158f3811234 -+ mov.w @(0x1234:16,er3.l),@-er1 ;0158f3b11234 -+ mov.w @(0x1234:16,er3.l),@+er1 ;0158f3911234 -+ mov.w @(0x1234:16,er3.l),@er1- ;0158f3a11234 -+ mov.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;0158f3c112349abc -+ mov.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;0158f3c912349abcdef0 -+ mov.w @(0x1234:16,er3.l),@(0xffff9abc:16,r3l.b) ;0158f3d312349abc -+ mov.w @(0x1234:16,er3.l),@(0xffff9abc:16,r3.w) ;0158f3e312349abc -+ mov.w @(0x1234:16,er3.l),@(0xffff9abc:16,er3.l) ;0158f3f312349abc -+ mov.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r3l.b) ;0158f3db12349abcdef0 -+ mov.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r3.w) ;0158f3eb12349abcdef0 -+ mov.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er3.l) ;0158f3fb12349abcdef0 -+ mov.w @(0x1234:16,er3.l),@0xffff9abc:16 ;0158f34012349abc -+ mov.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;0158f34812349abcdef0 -+ -+ mov.w @(0x12345678:32,r3l.b),@er1 ;0158db0112345678 -+ mov.w @(0x12345678:32,r3l.b),@(0x2:2,er1) ;0158db1112345678 -+ mov.w @(0x12345678:32,r3l.b),@er1+ ;0158db8112345678 -+ mov.w @(0x12345678:32,r3l.b),@-er1 ;0158dbb112345678 -+ mov.w @(0x12345678:32,r3l.b),@+er1 ;0158db9112345678 -+ mov.w @(0x12345678:32,r3l.b),@er1- ;0158dba112345678 -+ mov.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;0158dbc1123456789abc -+ mov.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;0158dbc9123456789abcdef0 -+ mov.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r3l.b) ;0158dbd3123456789abc -+ mov.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r3.w) ;0158dbe3123456789abc -+ mov.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er3.l) ;0158dbf3123456789abc -+ mov.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3l.b) ;0158dbdb123456789abcdef0 -+ mov.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3.w) ;0158dbeb123456789abcdef0 -+ mov.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er3.l) ;0158dbfb123456789abcdef0 -+ mov.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;0158db40123456789abc -+ mov.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;0158db48123456789abcdef0 -+ -+ mov.w @(0x12345678:32,r3.w),@er1 ;0158eb0112345678 -+ mov.w @(0x12345678:32,r3.w),@(0x2:2,er1) ;0158eb1112345678 -+ mov.w @(0x12345678:32,r3.w),@er1+ ;0158eb8112345678 -+ mov.w @(0x12345678:32,r3.w),@-er1 ;0158ebb112345678 -+ mov.w @(0x12345678:32,r3.w),@+er1 ;0158eb9112345678 -+ mov.w @(0x12345678:32,r3.w),@er1- ;0158eba112345678 -+ mov.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;0158ebc1123456789abc -+ mov.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;0158ebc9123456789abcdef0 -+ mov.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r3l.b) ;0158ebd3123456789abc -+ mov.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r3.w) ;0158ebe3123456789abc -+ mov.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er3.l) ;0158ebf3123456789abc -+ mov.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3l.b) ;0158ebdb123456789abcdef0 -+ mov.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3.w) ;0158ebeb123456789abcdef0 -+ mov.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er3.l) ;0158ebfb123456789abcdef0 -+ mov.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;0158eb40123456789abc -+ mov.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;0158eb48123456789abcdef0 -+ -+ mov.w @(0x12345678:32,er3.l),@er1 ;0158fb0112345678 -+ mov.w @(0x12345678:32,er3.l),@(0x2:2,er1) ;0158fb1112345678 -+ mov.w @(0x12345678:32,er3.l),@er1+ ;0158fb8112345678 -+ mov.w @(0x12345678:32,er3.l),@-er1 ;0158fbb112345678 -+ mov.w @(0x12345678:32,er3.l),@+er1 ;0158fb9112345678 -+ mov.w @(0x12345678:32,er3.l),@er1- ;0158fba112345678 -+ mov.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;0158fbc1123456789abc -+ mov.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;0158fbc9123456789abcdef0 -+ mov.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r3l.b) ;0158fbd3123456789abc -+ mov.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r3.w) ;0158fbe3123456789abc -+ mov.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er3.l) ;0158fbf3123456789abc -+ mov.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3l.b) ;0158fbdb123456789abcdef0 -+ mov.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3.w) ;0158fbeb123456789abcdef0 -+ mov.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er3.l) ;0158fbfb123456789abcdef0 -+ mov.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;0158fb40123456789abc -+ mov.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;0158fb48123456789abcdef0 -+ -+ mov.w @0x1234:16,@er1 ;015840011234 -+ mov.w @0x1234:16,@(0x2:2,er1) ;015840111234 -+ mov.w @0x1234:16,@er1+ ;015840811234 -+ mov.w @0x1234:16,@-er1 ;015840b11234 -+ mov.w @0x1234:16,@+er1 ;015840911234 -+ mov.w @0x1234:16,@er1- ;015840a11234 -+ mov.w @0x1234:16,@(0xffff9abc:16,er1) ;015840c112349abc -+ mov.w @0x1234:16,@(0x9abcdef0:32,er1) ;015840c912349abcdef0 -+ mov.w @0x1234:16,@(0xffff9abc:16,r3l.b) ;015840d312349abc -+ mov.w @0x1234:16,@(0xffff9abc:16,r3.w) ;015840e312349abc -+ mov.w @0x1234:16,@(0xffff9abc:16,er3.l) ;015840f312349abc -+ mov.w @0x1234:16,@(0x9abcdef0:32,r3l.b) ;015840db12349abcdef0 -+ mov.w @0x1234:16,@(0x9abcdef0:32,r3.w) ;015840eb12349abcdef0 -+ mov.w @0x1234:16,@(0x9abcdef0:32,er3.l) ;015840fb12349abcdef0 -+ mov.w @0x1234:16,@0xffff9abc:16 ;0158404012349abc -+ mov.w @0x1234:16,@0x9abcdef0:32 ;0158404812349abcdef0 -+ -+ mov.w @0x12345678:32,@er1 ;0158480112345678 -+ mov.w @0x12345678:32,@(0x2:2,er1) ;0158481112345678 -+ mov.w @0x12345678:32,@er1+ ;0158488112345678 -+ mov.w @0x12345678:32,@-er1 ;015848b112345678 -+ mov.w @0x12345678:32,@+er1 ;0158489112345678 -+ mov.w @0x12345678:32,@er1- ;015848a112345678 -+ mov.w @0x12345678:32,@(0xffff9abc:16,er1) ;015848c1123456789abc -+ mov.w @0x12345678:32,@(0x9abcdef0:32,er1) ;015848c9123456789abcdef0 -+ mov.w @0x12345678:32,@(0xffff9abc:16,r3l.b) ;015848d3123456789abc -+ mov.w @0x12345678:32,@(0xffff9abc:16,r3.w) ;015848e3123456789abc -+ mov.w @0x12345678:32,@(0xffff9abc:16,er3.l) ;015848f3123456789abc -+ mov.w @0x12345678:32,@(0x9abcdef0:32,r3l.b) ;015848db123456789abcdef0 -+ mov.w @0x12345678:32,@(0x9abcdef0:32,r3.w) ;015848eb123456789abcdef0 -+ mov.w @0x12345678:32,@(0x9abcdef0:32,er3.l) ;015848fb123456789abcdef0 -+ mov.w @0x12345678:32,@0xffff9abc:16 ;01584840123456789abc -+ mov.w @0x12345678:32,@0x9abcdef0:32 ;01584848123456789abcdef0 -+ -+ mov.l #0x12345678:32,er1 ;7a0112345678 -+ -+ mov.l #0x1234:16,er1 ;7a091234 -+ -+ mov.l #0x1:3,er3 ;0f9b -+ -+ mov.l #0x12345678:32,@er1 ;7a74123456780100 -+ mov.l #0x12345678:32,@(0x4:2,er1) ;7a74123456781100 -+ mov.l #0x12345678:32,@-er1 ;7a7412345678b100 -+ mov.l #0x12345678:32,@er1+ ;7a74123456788100 -+ mov.l #0x12345678:32,@er1- ;7a7412345678a100 -+ mov.l #0x12345678:32,@+er1 ;7a74123456789100 -+ mov.l #0x12345678:32,@(0x1234:16,er1) ;7a7412345678c1001234 -+ mov.l #0x12345678:32,@(0x12345678:32,er1) ;7a7412345678c90012345678 -+ mov.l #0x12345678:32,@(0x1234:16,r3l.b) ;7a7412345678d3001234 -+ mov.l #0x12345678:32,@(0x1234:16,r3.w) ;7a7412345678e3001234 -+ mov.l #0x12345678:32,@(0x1234:16,er3.l) ;7a7412345678f3001234 -+ mov.l #0x12345678:32,@(0x12345678:32,r3l.b) ;7a7412345678db0012345678 -+ mov.l #0x12345678:32,@(0x12345678:32,r3.w) ;7a7412345678eb0012345678 -+ mov.l #0x12345678:32,@(0x12345678:32,er3.l) ;7a7412345678fb0012345678 -+ mov.l #0x12345678:32,@0x1234:16 ;7a741234567840001234 -+ mov.l #0x12345678:32,@0x12345678:32 ;7a7412345678480012345678 -+ -+ mov.l #0x1234:16,@er1 ;7a7c12340100 -+ mov.l #0x1234:16,@(0x4:2,er1) ;7a7c12341100 -+ mov.l #0x1234:16,@-er1 ;7a7c1234b100 -+ mov.l #0x1234:16,@er1+ ;7a7c12348100 -+ mov.l #0x1234:16,@er1- ;7a7c1234a100 -+ mov.l #0x1234:16,@+er1 ;7a7c12349100 -+ mov.l #0x1234:16,@(0x1234:16,er1) ;7a7c1234c1001234 -+ mov.l #0x1234:16,@(0x12345678:32,er1) ;7a7c1234c90012345678 -+ mov.l #0x1234:16,@(0x1234:16,r3l.b) ;7a7c1234d3001234 -+ mov.l #0x1234:16,@(0x1234:16,r3.w) ;7a7c1234e3001234 -+ mov.l #0x1234:16,@(0x1234:16,er3.l) ;7a7c1234f3001234 -+ mov.l #0x1234:16,@(0x12345678:32,r3l.b) ;7a7c1234db0012345678 -+ mov.l #0x1234:16,@(0x12345678:32,r3.w) ;7a7c1234eb0012345678 -+ mov.l #0x1234:16,@(0x12345678:32,er3.l) ;7a7c1234fb0012345678 -+ mov.l #0x1234:16,@0x1234:16 ;7a7c123440001234 -+ mov.l #0x1234:16,@0x12345678:32 ;7a7c1234480012345678 -+ -+ mov.l #0x12:8,@er1 ;010d0112 -+ mov.l #0x12:8,@(0x4:2,er1) ;010d1112 -+ mov.l #0x12:8,@-er1 ;010db112 -+ mov.l #0x12:8,@er1+ ;010d8112 -+ mov.l #0x12:8,@er1- ;010da112 -+ mov.l #0x12:8,@+er1 ;010d9112 -+ mov.l #0x12:8,@(0x1234:16,er1) ;010dc1121234 -+ mov.l #0x12:8,@(0x12345678:32,er1) ;010dc91212345678 -+ mov.l #0x12:8,@(0x1234:16,r3l.b) ;010dd3121234 -+ mov.l #0x12:8,@(0x1234:16,r3.w) ;010de3121234 -+ mov.l #0x12:8,@(0x1234:16,er3.l) ;010df3121234 -+ mov.l #0x12:8,@(0x12345678:32,r3l.b) ;010ddb1212345678 -+ mov.l #0x12:8,@(0x12345678:32,r3.w) ;010deb1212345678 -+ mov.l #0x12:8,@(0x12345678:32,er3.l) ;010dfb1212345678 -+ mov.l #0x12:8,@0x1234:16 ;010d40121234 -+ mov.l #0x12:8,@0x12345678:32 ;010d481212345678 -+ -+ mov.l er2,er1 ;0fa1 -+ -+ mov.l er2,@er1 ;01006992 -+ mov.l er2,@(0x4:2,er1) ;01016992 -+ mov.l er2,@-er1 ;01006d92 -+ mov.l er2,@er1+ ;01036d92 -+ mov.l er2,@er1- ;01016d92 -+ mov.l er2,@+er1 ;01026d92 -+ mov.l er2,@(0x1234:16,er1) ;01006f921234 -+ mov.l er2,@(0x12345678:32,er1) ;78906ba212345678 -+ mov.l er2,@(0x1234:16,r3l.b) ;01016fb21234 -+ mov.l er2,@(0x1234:16,r3.w) ;01026fb21234 -+ mov.l er2,@(0x1234:16,er3.l) ;01036fb21234 -+ mov.l er2,@(0x12345678:32,r3l.b) ;78b16ba212345678 -+ mov.l er2,@(0x12345678:32,r3.w) ;78b26ba212345678 -+ mov.l er2,@(0x12345678:32,er3.l) ;78b36ba212345678 -+ mov.l er2,@0x1234:16 ;01006b821234 -+ mov.l er2,@0x12345678:32 ;01006ba212345678 -+ -+ mov.l @er2,er1 ;01006921 -+ mov.l @(0x4:2,er2),er1 ;01016921 -+ mov.l @er2+,er1 ;01006d21 -+ mov.l @-er2,er1 ;01036d21 -+ mov.l @+er2,er1 ;01016d21 -+ mov.l @er2-,er1 ;01026d21 -+ mov.l @(0x1234:16,er1),er1 ;01006f111234 -+ mov.l @(0x12345678:32,er1),er1 ;78906b2112345678 -+ mov.l @(0x1234:16,r3l.b),er1 ;01016f311234 -+ mov.l @(0x1234:16,r3.w),er1 ;01026f311234 -+ mov.l @(0x1234:16,er3.l),er1 ;01036f311234 -+ mov.l @(0x12345678:32,r3l.b),er1 ;78b16b2112345678 -+ mov.l @(0x12345678:32,r3.w),er1 ;78b26b2112345678 -+ mov.l @(0x12345678:32,er3.l),er1 ;78b36b2112345678 -+ mov.l @0x1234:16,er1 ;01006b011234 -+ mov.l @0x12345678:32,er1 ;01006b2112345678 -+ -+ mov.l @er2,@er1 ;01080201 -+ mov.l @er2,@(0x4:2,er1) ;01080211 -+ mov.l @er2,@er1+ ;01080281 -+ mov.l @er2,@-er1 ;010802b1 -+ mov.l @er2,@+er1 ;01080291 -+ mov.l @er2,@er1- ;010802a1 -+ mov.l @er2,@(0x1234:16,er1) ;010802c11234 -+ mov.l @er2,@(0x12345678:32,er1) ;010802c912345678 -+ mov.l @er2,@(0x1234:16,r3l.b) ;010802d31234 -+ mov.l @er2,@(0x1234:16,r3.w) ;010802e31234 -+ mov.l @er2,@(0x1234:16,er3.l) ;010802f31234 -+ mov.l @er2,@(0x12345678:32,r3l.b) ;010802db12345678 -+ mov.l @er2,@(0x12345678:32,r3.w) ;010802eb12345678 -+ mov.l @er2,@(0x12345678:32,er3.l) ;010802fb12345678 -+ mov.l @er2,@0x1234:16 ;010802401234 -+ mov.l @er2,@0x12345678:32 ;0108024812345678 -+ -+ mov.l @(0x4:2,er2),@er1 ;01081201 -+ mov.l @(0x4:2,er2),@(0x4:2,er1) ;01081211 -+ mov.l @(0x4:2,er2),@er1+ ;01081281 -+ mov.l @(0x4:2,er2),@-er1 ;010812b1 -+ mov.l @(0x4:2,er2),@+er1 ;01081291 -+ mov.l @(0x4:2,er2),@er1- ;010812a1 -+ mov.l @(0x4:2,er2),@(0x1234:16,er1) ;010812c11234 -+ mov.l @(0x4:2,er2),@(0x12345678:32,er1) ;010812c912345678 -+ mov.l @(0x4:2,er2),@(0x1234:16,r3l.b) ;010812d31234 -+ mov.l @(0x4:2,er2),@(0x1234:16,r3.w) ;010812e31234 -+ mov.l @(0x4:2,er2),@(0x1234:16,er3.l) ;010812f31234 -+ mov.l @(0x4:2,er2),@(0x12345678:32,r3l.b) ;010812db12345678 -+ mov.l @(0x4:2,er2),@(0x12345678:32,r3.w) ;010812eb12345678 -+ mov.l @(0x4:2,er2),@(0x12345678:32,er3.l) ;010812fb12345678 -+ mov.l @(0x4:2,er2),@0x1234:16 ;010812401234 -+ mov.l @(0x4:2,er2),@0x12345678:32 ;0108124812345678 -+ -+ mov.l @-er2,@er1 ;0108b201 -+ mov.l @-er2,@(0x4:2,er1) ;0108b211 -+ mov.l @-er2,@er1+ ;0108b281 -+ mov.l @-er2,@-er1 ;0108b2b1 -+ mov.l @-er2,@+er1 ;0108b291 -+ mov.l @-er2,@er1- ;0108b2a1 -+ mov.l @-er2,@(0x1234:16,er1) ;0108b2c11234 -+ mov.l @-er2,@(0x12345678:32,er1) ;0108b2c912345678 -+ mov.l @-er2,@(0x1234:16,r3l.b) ;0108b2d31234 -+ mov.l @-er2,@(0x1234:16,r3.w) ;0108b2e31234 -+ mov.l @-er2,@(0x1234:16,er3.l) ;0108b2f31234 -+ mov.l @-er2,@(0x12345678:32,r3l.b) ;0108b2db12345678 -+ mov.l @-er2,@(0x12345678:32,r3.w) ;0108b2eb12345678 -+ mov.l @-er2,@(0x12345678:32,er3.l) ;0108b2fb12345678 -+ mov.l @-er2,@0x1234:16 ;0108b2401234 -+ mov.l @-er2,@0x12345678:32 ;0108b24812345678 -+ -+ mov.l @er2+,@er1 ;01088201 -+ mov.l @er2+,@(0x4:2,er1) ;01088211 -+ mov.l @er2+,@er1+ ;01088281 -+ mov.l @er2+,@-er1 ;010882b1 -+ mov.l @er2+,@+er1 ;01088291 -+ mov.l @er2+,@er1- ;010882a1 -+ mov.l @er2+,@(0x1234:16,er1) ;010882c11234 -+ mov.l @er2+,@(0x12345678:32,er1) ;010882c912345678 -+ mov.l @er2+,@(0x1234:16,r3l.b) ;010882d31234 -+ mov.l @er2+,@(0x1234:16,r3.w) ;010882e31234 -+ mov.l @er2+,@(0x1234:16,er3.l) ;010882f31234 -+ mov.l @er2+,@(0x12345678:32,r3l.b) ;010882db12345678 -+ mov.l @er2+,@(0x12345678:32,r3.w) ;010882eb12345678 -+ mov.l @er2+,@(0x12345678:32,er3.l) ;010882fb12345678 -+ mov.l @er2+,@0x1234:16 ;010882401234 -+ mov.l @er2+,@0x12345678:32 ;0108824812345678 -+ -+ mov.l @er2-,@er1 ;0108a201 -+ mov.l @er2-,@(0x4:2,er1) ;0108a211 -+ mov.l @er2-,@er1+ ;0108a281 -+ mov.l @er2-,@-er1 ;0108a2b1 -+ mov.l @er2-,@+er1 ;0108a291 -+ mov.l @er2-,@er1- ;0108a2a1 -+ mov.l @er2-,@(0x1234:16,er1) ;0108a2c11234 -+ mov.l @er2-,@(0x12345678:32,er1) ;0108a2c912345678 -+ mov.l @er2-,@(0x1234:16,r3l.b) ;0108a2d31234 -+ mov.l @er2-,@(0x1234:16,r3.w) ;0108a2e31234 -+ mov.l @er2-,@(0x1234:16,er3.l) ;0108a2f31234 -+ mov.l @er2-,@(0x12345678:32,r3l.b) ;0108a2db12345678 -+ mov.l @er2-,@(0x12345678:32,r3.w) ;0108a2eb12345678 -+ mov.l @er2-,@(0x12345678:32,er3.l) ;0108a2fb12345678 -+ mov.l @er2-,@0x1234:16 ;0108a2401234 -+ mov.l @er2-,@0x12345678:32 ;0108a24812345678 -+ -+ mov.l @+er2,@er1 ;01089201 -+ mov.l @+er2,@(0x4:2,er1) ;01089211 -+ mov.l @+er2,@er1+ ;01089281 -+ mov.l @+er2,@-er1 ;010892b1 -+ mov.l @+er2,@+er1 ;01089291 -+ mov.l @+er2,@er1- ;010892a1 -+ mov.l @+er2,@(0x1234:16,er1) ;010892c11234 -+ mov.l @+er2,@(0x12345678:32,er1) ;010892c912345678 -+ mov.l @+er2,@(0x1234:16,r3l.b) ;010892d31234 -+ mov.l @+er2,@(0x1234:16,r3.w) ;010892e31234 -+ mov.l @+er2,@(0x1234:16,er3.l) ;010892f31234 -+ mov.l @+er2,@(0x12345678:32,r3l.b) ;010892db12345678 -+ mov.l @+er2,@(0x12345678:32,r3.w) ;010892eb12345678 -+ mov.l @+er2,@(0x12345678:32,er3.l) ;010892fb12345678 -+ mov.l @+er2,@0x1234:16 ;010892401234 -+ mov.l @+er2,@0x12345678:32 ;0108924812345678 -+ -+ mov.l @(0x1234:16,er2),@er1 ;0108c2011234 -+ mov.l @(0x1234:16,er2),@(0x4:2,er1) ;0108c2111234 -+ mov.l @(0x1234:16,er2),@er1+ ;0108c2811234 -+ mov.l @(0x1234:16,er2),@-er1 ;0108c2b11234 -+ mov.l @(0x1234:16,er2),@+er1 ;0108c2911234 -+ mov.l @(0x1234:16,er2),@er1- ;0108c2a11234 -+ mov.l @(0x1234:16,er2),@(0xffff9abc:16,er1) ;0108c2c112349abc -+ mov.l @(0x1234:16,er2),@(0x9abcdef0:32,er1) ;0108c2c912349abcdef0 -+ mov.l @(0x1234:16,er2),@(0xffff9abc:16,r3l.b) ;0108c2d312349abc -+ mov.l @(0x1234:16,er2),@(0xffff9abc:16,r3.w) ;0108c2e312349abc -+ mov.l @(0x1234:16,er2),@(0xffff9abc:16,er3.l) ;0108c2f312349abc -+ mov.l @(0x1234:16,er2),@(0x9abcdef0:32,r3l.b) ;0108c2db12349abcdef0 -+ mov.l @(0x1234:16,er2),@(0x9abcdef0:32,r3.w) ;0108c2eb12349abcdef0 -+ mov.l @(0x1234:16,er2),@(0x9abcdef0:32,er3.l) ;0108c2fb12349abcdef0 -+ mov.l @(0x1234:16,er2),@0xffff9abc:16 ;0108c24012349abc -+ mov.l @(0x1234:16,er2),@0x9abcdef0:32 ;0108c24812349abcdef0 -+ -+ mov.l @(0x12345678:32,er2),@er1 ;0108ca0112345678 -+ mov.l @(0x12345678:32,er2),@(0x4:2,er1) ;0108ca1112345678 -+ mov.l @(0x12345678:32,er2),@er1+ ;0108ca8112345678 -+ mov.l @(0x12345678:32,er2),@-er1 ;0108cab112345678 -+ mov.l @(0x12345678:32,er2),@+er1 ;0108ca9112345678 -+ mov.l @(0x12345678:32,er2),@er1- ;0108caa112345678 -+ mov.l @(0x12345678:32,er2),@(0xffff9abc:16,er1) ;0108cac1123456789abc -+ mov.l @(0x12345678:32,er2),@(0x9abcdef0:32,er1) ;0108cac9123456789abcdef0 -+ mov.l @(0x12345678:32,er2),@(0xffff9abc:16,r3l.b) ;0108cad3123456789abc -+ mov.l @(0x12345678:32,er2),@(0xffff9abc:16,r3.w) ;0108cae3123456789abc -+ mov.l @(0x12345678:32,er2),@(0xffff9abc:16,er3.l) ;0108caf3123456789abc -+ mov.l @(0x12345678:32,er2),@(0x9abcdef0:32,r3l.b) ;0108cadb123456789abcdef0 -+ mov.l @(0x12345678:32,er2),@(0x9abcdef0:32,r3.w) ;0108caeb123456789abcdef0 -+ mov.l @(0x12345678:32,er2),@(0x9abcdef0:32,er3.l) ;0108cafb123456789abcdef0 -+ mov.l @(0x12345678:32,er2),@0xffff9abc:16 ;0108ca40123456789abc -+ mov.l @(0x12345678:32,er2),@0x9abcdef0:32 ;0108ca48123456789abcdef0 -+ -+ mov.l @(0x1234:16,r3l.b),@er1 ;0108d3011234 -+ mov.l @(0x1234:16,r3l.b),@(0x4:2,er1) ;0108d3111234 -+ mov.l @(0x1234:16,r3l.b),@er1+ ;0108d3811234 -+ mov.l @(0x1234:16,r3l.b),@-er1 ;0108d3b11234 -+ mov.l @(0x1234:16,r3l.b),@+er1 ;0108d3911234 -+ mov.l @(0x1234:16,r3l.b),@er1- ;0108d3a11234 -+ mov.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;0108d3c112349abc -+ mov.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;0108d3c912349abcdef0 -+ mov.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r3l.b) ;0108d3d312349abc -+ mov.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r3.w) ;0108d3e312349abc -+ mov.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er3.l) ;0108d3f312349abc -+ mov.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r3l.b) ;0108d3db12349abcdef0 -+ mov.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r3.w) ;0108d3eb12349abcdef0 -+ mov.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er3.l) ;0108d3fb12349abcdef0 -+ mov.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;0108d34012349abc -+ mov.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;0108d34812349abcdef0 -+ -+ mov.l @(0x1234:16,r3.w),@er1 ;0108e3011234 -+ mov.l @(0x1234:16,r3.w),@(0x4:2,er1) ;0108e3111234 -+ mov.l @(0x1234:16,r3.w),@er1+ ;0108e3811234 -+ mov.l @(0x1234:16,r3.w),@-er1 ;0108e3b11234 -+ mov.l @(0x1234:16,r3.w),@+er1 ;0108e3911234 -+ mov.l @(0x1234:16,r3.w),@er1- ;0108e3a11234 -+ mov.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;0108e3c112349abc -+ mov.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;0108e3c912349abcdef0 -+ mov.l @(0x1234:16,r3.w),@(0xffff9abc:16,r3l.b) ;0108e3d312349abc -+ mov.l @(0x1234:16,r3.w),@(0xffff9abc:16,r3.w) ;0108e3e312349abc -+ mov.l @(0x1234:16,r3.w),@(0xffff9abc:16,er3.l) ;0108e3f312349abc -+ mov.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r3l.b) ;0108e3db12349abcdef0 -+ mov.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r3.w) ;0108e3eb12349abcdef0 -+ mov.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er3.l) ;0108e3fb12349abcdef0 -+ mov.l @(0x1234:16,r3.w),@0xffff9abc:16 ;0108e34012349abc -+ mov.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;0108e34812349abcdef0 -+ -+ mov.l @(0x1234:16,er3.l),@er1 ;0108f3011234 -+ mov.l @(0x1234:16,er3.l),@(0x4:2,er1) ;0108f3111234 -+ mov.l @(0x1234:16,er3.l),@er1+ ;0108f3811234 -+ mov.l @(0x1234:16,er3.l),@-er1 ;0108f3b11234 -+ mov.l @(0x1234:16,er3.l),@+er1 ;0108f3911234 -+ mov.l @(0x1234:16,er3.l),@er1- ;0108f3a11234 -+ mov.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;0108f3c112349abc -+ mov.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;0108f3c912349abcdef0 -+ mov.l @(0x1234:16,er3.l),@(0xffff9abc:16,r3l.b) ;0108f3d312349abc -+ mov.l @(0x1234:16,er3.l),@(0xffff9abc:16,r3.w) ;0108f3e312349abc -+ mov.l @(0x1234:16,er3.l),@(0xffff9abc:16,er3.l) ;0108f3f312349abc -+ mov.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r3l.b) ;0108f3db12349abcdef0 -+ mov.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r3.w) ;0108f3eb12349abcdef0 -+ mov.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er3.l) ;0108f3fb12349abcdef0 -+ mov.l @(0x1234:16,er3.l),@0xffff9abc:16 ;0108f34012349abc -+ mov.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;0108f34812349abcdef0 -+ -+ mov.l @(0x12345678:32,r3l.b),@er1 ;0108db0112345678 -+ mov.l @(0x12345678:32,r3l.b),@(0x4:2,er1) ;0108db1112345678 -+ mov.l @(0x12345678:32,r3l.b),@er1+ ;0108db8112345678 -+ mov.l @(0x12345678:32,r3l.b),@-er1 ;0108dbb112345678 -+ mov.l @(0x12345678:32,r3l.b),@+er1 ;0108db9112345678 -+ mov.l @(0x12345678:32,r3l.b),@er1- ;0108dba112345678 -+ mov.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;0108dbc1123456789abc -+ mov.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;0108dbc9123456789abcdef0 -+ mov.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r3l.b) ;0108dbd3123456789abc -+ mov.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r3.w) ;0108dbe3123456789abc -+ mov.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er3.l) ;0108dbf3123456789abc -+ mov.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3l.b) ;0108dbdb123456789abcdef0 -+ mov.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3.w) ;0108dbeb123456789abcdef0 -+ mov.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er3.l) ;0108dbfb123456789abcdef0 -+ mov.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;0108db40123456789abc -+ mov.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;0108db48123456789abcdef0 -+ -+ mov.l @(0x12345678:32,r3.w),@er1 ;0108eb0112345678 -+ mov.l @(0x12345678:32,r3.w),@(0x4:2,er1) ;0108eb1112345678 -+ mov.l @(0x12345678:32,r3.w),@er1+ ;0108eb8112345678 -+ mov.l @(0x12345678:32,r3.w),@-er1 ;0108ebb112345678 -+ mov.l @(0x12345678:32,r3.w),@+er1 ;0108eb9112345678 -+ mov.l @(0x12345678:32,r3.w),@er1- ;0108eba112345678 -+ mov.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;0108ebc1123456789abc -+ mov.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;0108ebc9123456789abcdef0 -+ mov.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r3l.b) ;0108ebd3123456789abc -+ mov.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r3.w) ;0108ebe3123456789abc -+ mov.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er3.l) ;0108ebf3123456789abc -+ mov.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3l.b) ;0108ebdb123456789abcdef0 -+ mov.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3.w) ;0108ebeb123456789abcdef0 -+ mov.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er3.l) ;0108ebfb123456789abcdef0 -+ mov.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;0108eb40123456789abc -+ mov.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;0108eb48123456789abcdef0 -+ -+ mov.l @(0x12345678:32,er3.l),@er1 ;0108fb0112345678 -+ mov.l @(0x12345678:32,er3.l),@(0x4:2,er1) ;0108fb1112345678 -+ mov.l @(0x12345678:32,er3.l),@er1+ ;0108fb8112345678 -+ mov.l @(0x12345678:32,er3.l),@-er1 ;0108fbb112345678 -+ mov.l @(0x12345678:32,er3.l),@+er1 ;0108fb9112345678 -+ mov.l @(0x12345678:32,er3.l),@er1- ;0108fba112345678 -+ mov.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;0108fbc1123456789abc -+ mov.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;0108fbc9123456789abcdef0 -+ mov.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r3l.b) ;0108fbd3123456789abc -+ mov.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r3.w) ;0108fbe3123456789abc -+ mov.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er3.l) ;0108fbf3123456789abc -+ mov.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3l.b) ;0108fbdb123456789abcdef0 -+ mov.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3.w) ;0108fbeb123456789abcdef0 -+ mov.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er3.l) ;0108fbfb123456789abcdef0 -+ mov.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;0108fb40123456789abc -+ mov.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;0108fb48123456789abcdef0 -+ -+ mov.l @0x1234:16,@er1 ;010840011234 -+ mov.l @0x1234:16,@(0x4:2,er1) ;010840111234 -+ mov.l @0x1234:16,@er1+ ;010840811234 -+ mov.l @0x1234:16,@-er1 ;010840b11234 -+ mov.l @0x1234:16,@+er1 ;010840911234 -+ mov.l @0x1234:16,@er1- ;010840a11234 -+ mov.l @0x1234:16,@(0xffff9abc:16,er1) ;010840c112349abc -+ mov.l @0x1234:16,@(0x9abcdef0:32,er1) ;010840c912349abcdef0 -+ mov.l @0x1234:16,@(0xffff9abc:16,r3l.b) ;010840d312349abc -+ mov.l @0x1234:16,@(0xffff9abc:16,r3.w) ;010840e312349abc -+ mov.l @0x1234:16,@(0xffff9abc:16,er3.l) ;010840f312349abc -+ mov.l @0x1234:16,@(0x9abcdef0:32,r3l.b) ;010840db12349abcdef0 -+ mov.l @0x1234:16,@(0x9abcdef0:32,r3.w) ;010840eb12349abcdef0 -+ mov.l @0x1234:16,@(0x9abcdef0:32,er3.l) ;010840fb12349abcdef0 -+ mov.l @0x1234:16,@0xffff9abc:16 ;0108404012349abc -+ mov.l @0x1234:16,@0x9abcdef0:32 ;0108404812349abcdef0 -+ -+ mov.l @0x12345678:32,@er1 ;0108480112345678 -+ mov.l @0x12345678:32,@(0x4:2,er1) ;0108481112345678 -+ mov.l @0x12345678:32,@er1+ ;0108488112345678 -+ mov.l @0x12345678:32,@-er1 ;010848b112345678 -+ mov.l @0x12345678:32,@+er1 ;0108489112345678 -+ mov.l @0x12345678:32,@er1- ;010848a112345678 -+ mov.l @0x12345678:32,@(0xffff9abc:16,er1) ;010848c1123456789abc -+ mov.l @0x12345678:32,@(0x9abcdef0:32,er1) ;010848c9123456789abcdef0 -+ mov.l @0x12345678:32,@(0xffff9abc:16,r3l.b) ;010848d3123456789abc -+ mov.l @0x12345678:32,@(0xffff9abc:16,r3.w) ;010848e3123456789abc -+ mov.l @0x12345678:32,@(0xffff9abc:16,er3.l) ;010848f3123456789abc -+ mov.l @0x12345678:32,@(0x9abcdef0:32,r3l.b) ;010848db123456789abcdef0 -+ mov.l @0x12345678:32,@(0x9abcdef0:32,r3.w) ;010848eb123456789abcdef0 -+ mov.l @0x12345678:32,@(0x9abcdef0:32,er3.l) ;010848fb123456789abcdef0 -+ mov.l @0x12345678:32,@0xffff9abc:16 ;01084840123456789abc -+ mov.l @0x12345678:32,@0x9abcdef0:32 ;01084848123456789abcdef0 -+ -+ movtpe.b r2h,@0x1234:16 ;6ac21234 -+ movfpe.b @0x1234:16,r1h ;6a411234 -+ -+ ldm @sp+,(er0-er1) ;01106d71 -+ ldm @sp+,(er1-er2) ;01106d72 -+ ldm @sp+,(er2-er3) ;01106d73 -+ ldm @sp+,(er3-er4) ;01106d74 -+ ldm @sp+,(er4-er5) ;01106d75 -+ ldm @sp+,(er5-er6) ;01106d76 -+ ldm @sp+,(er6-er7) ;01106d77 -+ -+ ldm @sp+,(er0-er2) ;01206d72 -+ ldm @sp+,(er1-er3) ;01206d73 -+ ldm @sp+,(er2-er4) ;01206d74 -+ ldm @sp+,(er3-er5) ;01206d75 -+ ldm @sp+,(er4-er6) ;01206d76 -+ ldm @sp+,(er5-er7) ;01206d77 -+ -+ ldm @sp+,(er0-er3) ;01306d73 -+ ldm @sp+,(er1-er4) ;01306d74 -+ ldm @sp+,(er2-er5) ;01306d75 -+ ldm @sp+,(er3-er6) ;01306d76 -+ ldm @sp+,(er4-er7) ;01306d77 -+ -+ stm (er0-er1),@-sp ;01106df0 -+ stm (er1-er2),@-sp ;01106df1 -+ stm (er2-er3),@-sp ;01106df2 -+ stm (er3-er4),@-sp ;01106df3 -+ stm (er4-er5),@-sp ;01106df4 -+ stm (er5-er6),@-sp ;01106df5 -+ stm (er6-er7),@-sp ;01106df6 -+ -+ stm (er0-er2),@-sp ;01206df0 -+ stm (er1-er3),@-sp ;01206df1 -+ stm (er2-er4),@-sp ;01206df2 -+ stm (er3-er5),@-sp ;01206df3 -+ stm (er4-er6),@-sp ;01206df4 -+ stm (er5-er7),@-sp ;01206df5 -+ -+ stm (er0-er3),@-sp ;01306df0 -+ stm (er1-er4),@-sp ;01306df1 -+ stm (er2-er5),@-sp ;01306df2 -+ stm (er3-er6),@-sp ;01306df3 -+ stm (er4-er7),@-sp ;01306df4 -+ -+ eepmov.b ;7b5c598f -+ -+ eepmov.w ;7bd4598f -+ -+ movmd.b ;7b94 -+ movmd.w ;7ba4 -+ movmd.l ;7bb4 -+ movsd.b label ;7b840004 -+ nop ;0000 -+ nop ;0000 -+label: -+ -+ .end -+ ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;mov ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ .h8300sx ++ .text ++_start: ++ mov.b #0x12:8,r3h ;f312 ++ mov.b #0x12:8,@er3 ;017d0312 ++ mov.b #0x12:8,@(0x1:2,er3) ;017d1312 ++ mov.b #0x12:8,@-er3 ;017db312 ++ mov.b #0x12:8,@er3+ ;017d8312 ++ mov.b #0x12:8,@er3- ;017da312 ++ mov.b #0x12:8,@+er3 ;017d9312 ++ mov.b #0x12:8,@(0x1234:16,er3) ;017dc3121234 ++ mov.b #0x12:8,@(0x12345678:32,er3) ;017dcb1212345678 ++ mov.b #0x12:8,@(0x1234:16,r3l.b) ;017dd3121234 ++ mov.b #0x12:8,@(0x1234:16,r3.w) ;017de3121234 ++ mov.b #0x12:8,@(0x1234:16,er3.l) ;017df3121234 ++ mov.b #0x12:8,@(0x12345678:32,r3l.b) ;017ddb1212345678 ++ mov.b #0x12:8,@(0x12345678:32,r3.w) ;017deb1212345678 ++ mov.b #0x12:8,@(0x12345678:32,er3.l) ;017dfb1212345678 ++ mov.b #0x12:8,@0x1234:16 ;017d40121234 ++ mov.b #0x12:8,@0x12345678:32 ;017d481212345678 ++ ++ mov.b #0x1:4,@0x1234:16 ;6ad11234 ++ mov.b #0x1:4,@0x12345678:32 ;6af112345678 ++ ++ mov.b r3h,r1h ;0c31 ++ ++ mov.b r3h,@er1 ;6893 ++ mov.b r3h,@(0x1:2,er1) ;01716893 ++ mov.b r3h,@-er1 ;6c93 ++ mov.b r3h,@er1+ ;01736c93 ++ mov.b r3h,@er1- ;01716c93 ++ mov.b r3h,@+er1 ;01726c93 ++ mov.b r3h,@(0x1234:16,er1) ;6e931234 ++ mov.b r3h,@(0x12345678:32,er1) ;78106aa312345678 ++ mov.b r3h,@(0x1234:16,r1l.b) ;01716e931234 ++ mov.b r3h,@(0x1234:16,r1.w) ;01726e931234 ++ mov.b r3h,@(0x1234:16,er1.l) ;01736e931234 ++ mov.b r3h,@(0x12345678:32,r1l.b) ;78116aa312345678 ++ mov.b r3h,@(0x12345678:32,r1.w) ;78126aa312345678 ++ mov.b r3h,@(0x12345678:32,er1.l) ;78136aa312345678 ++ mov.b r3h,@0xffffff12:8 ;3312 ++ mov.b r3h,@0x1234:16 ;6a831234 ++ mov.b r3h,@0x12345678:32 ;6aa312345678 ++ ++ mov.b @er3,r1h ;6831 ++ mov.b @(0x1:2,er3),r1h ;01716831 ++ mov.b @er3+,r1h ;6c31 ++ mov.b @-er3,r1h ;01736c31 ++ mov.b @+er3,r1h ;01716c31 ++ mov.b @er3-,r1h ;01726c31 ++ mov.b @(0x1234:16,er3),r1h ;6e311234 ++ mov.b @(0x12345678:32,er3),r1h ;78306a2112345678 ++ mov.b @(0x1234:16,r3l.b),r1h ;01716e311234 ++ mov.b @(0x1234:16,r3.w),r1h ;01726e311234 ++ mov.b @(0x1234:16,er3.l),r1h ;01736e311234 ++ mov.b @(0x12345678:32,r3l.b),r1h ;78316a2112345678 ++ mov.b @(0x12345678:32,r3.w),r1h ;78326a2112345678 ++ mov.b @(0x12345678:32,er3.l),r1h ;78336a2112345678 ++ mov.b @0xffffff12:8,r3h ;2312 ++ mov.b @0x1234:16,r3h ;6a031234 ++ mov.b @0x12345678:32,r3h ;6a2312345678 ++ ++ mov.b @er3,@er1 ;01780301 ++ mov.b @er3,@(0x1:2,er1) ;01780311 ++ mov.b @er3,@er1+ ;01780381 ++ mov.b @er3,@-er1 ;017803b1 ++ mov.b @er3,@+er1 ;01780391 ++ mov.b @er3,@er1- ;017803a1 ++ mov.b @er3,@(0x1234:16,er1) ;017803c11234 ++ mov.b @er3,@(0x12345678:32,er1) ;017803c912345678 ++ mov.b @er3,@(0x1234:16,r1l.b) ;017803d11234 ++ mov.b @er3,@(0x1234:16,r1.w) ;017803e11234 ++ mov.b @er3,@(0x1234:16,er1.l) ;017803f11234 ++ mov.b @er3,@(0x12345678:32,r1l.b) ;017803d912345678 ++ mov.b @er3,@(0x12345678:32,r1.w) ;017803e912345678 ++ mov.b @er3,@(0x12345678:32,er1.l) ;017803f912345678 ++ mov.b @er3,@0x1234:16 ;017803401234 ++ mov.b @er3,@0x12345678:32 ;0178034812345678 ++ ++ mov.b @(0x1:2,er3),@er1 ;01781301 ++ mov.b @(0x1:2,er3),@(0x1:2,er1) ;01781311 ++ mov.b @(0x1:2,er3),@er1+ ;01781381 ++ mov.b @(0x1:2,er3),@-er1 ;017813b1 ++ mov.b @(0x1:2,er3),@+er1 ;01781391 ++ mov.b @(0x1:2,er3),@er1- ;017813a1 ++ mov.b @(0x1:2,er3),@(0x1234:16,er1) ;017813c11234 ++ mov.b @(0x1:2,er3),@(0x12345678:32,er1) ;017813c912345678 ++ mov.b @(0x1:2,er3),@(0x1234:16,r1l.b) ;017813d11234 ++ mov.b @(0x1:2,er3),@(0x1234:16,r1.w) ;017813e11234 ++ mov.b @(0x1:2,er3),@(0x1234:16,er1.l) ;017813f11234 ++ mov.b @(0x1:2,er3),@(0x12345678:32,r1l.b) ;017813d912345678 ++ mov.b @(0x1:2,er3),@(0x12345678:32,r1.w) ;017813e912345678 ++ mov.b @(0x1:2,er3),@(0x12345678:32,er1.l) ;017813f912345678 ++ mov.b @(0x1:2,er3),@0x1234:16 ;017813401234 ++ mov.b @(0x1:2,er3),@0x12345678:32 ;0178134812345678 ++ ++ mov.b @-er3,@er1 ;0178b301 ++ mov.b @-er3,@(0x1:2,er1) ;0178b311 ++ mov.b @-er3,@er1+ ;0178b381 ++ mov.b @-er3,@-er1 ;0178b3b1 ++ mov.b @-er3,@+er1 ;0178b391 ++ mov.b @-er3,@er1- ;0178b3a1 ++ mov.b @-er3,@(0x1234:16,er1) ;0178b3c11234 ++ mov.b @-er3,@(0x12345678:32,er1) ;0178b3c912345678 ++ mov.b @-er3,@(0x1234:16,r1l.b) ;0178b3d11234 ++ mov.b @-er3,@(0x1234:16,r1.w) ;0178b3e11234 ++ mov.b @-er3,@(0x1234:16,er1.l) ;0178b3f11234 ++ mov.b @-er3,@(0x12345678:32,r1l.b) ;0178b3d912345678 ++ mov.b @-er3,@(0x12345678:32,r1.w) ;0178b3e912345678 ++ mov.b @-er3,@(0x12345678:32,er1.l) ;0178b3f912345678 ++ mov.b @-er3,@0x1234:16 ;0178b3401234 ++ mov.b @-er3,@0x12345678:32 ;0178b34812345678 ++ ++ mov.b @er3+,@er1 ;01788301 ++ mov.b @er3+,@(0x1:2,er1) ;01788311 ++ mov.b @er3+,@er1+ ;01788381 ++ mov.b @er3+,@-er1 ;017883b1 ++ mov.b @er3+,@+er1 ;01788391 ++ mov.b @er3+,@er1- ;017883a1 ++ mov.b @er3+,@(0x1234:16,er1) ;017883c11234 ++ mov.b @er3+,@(0x12345678:32,er1) ;017883c912345678 ++ mov.b @er3+,@(0x1234:16,r1l.b) ;017883d11234 ++ mov.b @er3+,@(0x1234:16,r1.w) ;017883e11234 ++ mov.b @er3+,@(0x1234:16,er1.l) ;017883f11234 ++ mov.b @er3+,@(0x12345678:32,r1l.b) ;017883d912345678 ++ mov.b @er3+,@(0x12345678:32,r1.w) ;017883e912345678 ++ mov.b @er3+,@(0x12345678:32,er1.l) ;017883f912345678 ++ mov.b @er3+,@0x1234:16 ;017883401234 ++ mov.b @er3+,@0x12345678:32 ;0178834812345678 ++ ++ mov.b @er3-,@er1 ;0178a301 ++ mov.b @er3-,@(0x1:2,er1) ;0178a311 ++ mov.b @er3-,@er1+ ;0178a381 ++ mov.b @er3-,@-er1 ;0178a3b1 ++ mov.b @er3-,@+er1 ;0178a391 ++ mov.b @er3-,@er1- ;0178a3a1 ++ mov.b @er3-,@(0x1234:16,er1) ;0178a3c11234 ++ mov.b @er3-,@(0x12345678:32,er1) ;0178a3c912345678 ++ mov.b @er3-,@(0x1234:16,r1l.b) ;0178a3d11234 ++ mov.b @er3-,@(0x1234:16,r1.w) ;0178a3e11234 ++ mov.b @er3-,@(0x1234:16,er1.l) ;0178a3f11234 ++ mov.b @er3-,@(0x12345678:32,r1l.b) ;0178a3d912345678 ++ mov.b @er3-,@(0x12345678:32,r1.w) ;0178a3e912345678 ++ mov.b @er3-,@(0x12345678:32,er1.l) ;0178a3f912345678 ++ mov.b @er3-,@0x1234:16 ;0178a3401234 ++ mov.b @er3-,@0x12345678:32 ;0178a34812345678 ++ ++ mov.b @+er3,@er1 ;01789301 ++ mov.b @+er3,@(0x1:2,er1) ;01789311 ++ mov.b @+er3,@er1+ ;01789381 ++ mov.b @+er3,@-er1 ;017893b1 ++ mov.b @+er3,@+er1 ;01789391 ++ mov.b @+er3,@er1- ;017893a1 ++ mov.b @+er3,@(0x1234:16,er1) ;017893c11234 ++ mov.b @+er3,@(0x12345678:32,er1) ;017893c912345678 ++ mov.b @+er3,@(0x1234:16,r1l.b) ;017893d11234 ++ mov.b @+er3,@(0x1234:16,r1.w) ;017893e11234 ++ mov.b @+er3,@(0x1234:16,er1.l) ;017893f11234 ++ mov.b @+er3,@(0x12345678:32,r1l.b) ;017893d912345678 ++ mov.b @+er3,@(0x12345678:32,r1.w) ;017893e912345678 ++ mov.b @+er3,@(0x12345678:32,er1.l) ;017893f912345678 ++ mov.b @+er3,@0x1234:16 ;017893401234 ++ mov.b @+er3,@0x12345678:32 ;0178934812345678 ++ ++ mov.b @(0x1234:16,er3),@er1 ;0178c3011234 ++ mov.b @(0x1234:16,er3),@(0x1:2,er1) ;0178c3111234 ++ mov.b @(0x1234:16,er3),@er1+ ;0178c3811234 ++ mov.b @(0x1234:16,er3),@-er1 ;0178c3b11234 ++ mov.b @(0x1234:16,er3),@+er1 ;0178c3911234 ++ mov.b @(0x1234:16,er3),@er1- ;0178c3a11234 ++ mov.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;0178c3c112349abc ++ mov.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;0178c3c912349abcdef0 ++ mov.b @(0x1234:16,er3),@(0xffff9abc:16,r1l.b) ;0178c3d112349abc ++ mov.b @(0x1234:16,er3),@(0xffff9abc:16,r1.w) ;0178c3e112349abc ++ mov.b @(0x1234:16,er3),@(0xffff9abc:16,er1.l) ;0178c3f112349abc ++ mov.b @(0x1234:16,er3),@(0x9abcdef0:32,r1l.b) ;0178c3d912349abcdef0 ++ mov.b @(0x1234:16,er3),@(0x9abcdef0:32,r1.w) ;0178c3e912349abcdef0 ++ mov.b @(0x1234:16,er3),@(0x9abcdef0:32,er1.l) ;0178c3f912349abcdef0 ++ mov.b @(0x1234:16,er3),@0xffff9abc:16 ;0178c34012349abc ++ mov.b @(0x1234:16,er3),@0x9abcdef0:32 ;0178c34812349abcdef0 ++ ++ mov.b @(0x12345678:32,er3),@er1 ;0178cb0112345678 ++ mov.b @(0x12345678:32,er3),@(0x1:2,er1) ;0178cb1112345678 ++ mov.b @(0x12345678:32,er3),@er1+ ;0178cb8112345678 ++ mov.b @(0x12345678:32,er3),@-er1 ;0178cbb112345678 ++ mov.b @(0x12345678:32,er3),@+er1 ;0178cb9112345678 ++ mov.b @(0x12345678:32,er3),@er1- ;0178cba112345678 ++ mov.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;0178cbc1123456789abc ++ mov.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;0178cbc9123456789abcdef0 ++ mov.b @(0x12345678:32,er3),@(0xffff9abc:16,r1l.b) ;0178cbd1123456789abc ++ mov.b @(0x12345678:32,er3),@(0xffff9abc:16,r1.w) ;0178cbe1123456789abc ++ mov.b @(0x12345678:32,er3),@(0xffff9abc:16,er1.l) ;0178cbf1123456789abc ++ mov.b @(0x12345678:32,er3),@(0x9abcdef0:32,r1l.b) ;0178cbd9123456789abcdef0 ++ mov.b @(0x12345678:32,er3),@(0x9abcdef0:32,r1.w) ;0178cbe9123456789abcdef0 ++ mov.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1.l) ;0178cbf9123456789abcdef0 ++ mov.b @(0x12345678:32,er3),@0xffff9abc:16 ;0178cb40123456789abc ++ mov.b @(0x12345678:32,er3),@0x9abcdef0:32 ;0178cb48123456789abcdef0 ++ ++ mov.b @(0x1234:16,r3l.b),@er1 ;0178d3011234 ++ mov.b @(0x1234:16,r3l.b),@(0x1:2,er1) ;0178d3111234 ++ mov.b @(0x1234:16,r3l.b),@er1+ ;0178d3811234 ++ mov.b @(0x1234:16,r3l.b),@-er1 ;0178d3b11234 ++ mov.b @(0x1234:16,r3l.b),@+er1 ;0178d3911234 ++ mov.b @(0x1234:16,r3l.b),@er1- ;0178d3a11234 ++ mov.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r1l.b) ;0178d3d112349abc ++ mov.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r1.w) ;0178d3e112349abc ++ mov.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1.l) ;0178d3f112349abc ++ mov.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r1l.b) ;0178d3d912349abcdef0 ++ mov.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r1.w) ;0178d3e912349abcdef0 ++ mov.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1.l) ;0178d3f912349abcdef0 ++ mov.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;0178d34012349abc ++ mov.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;0178d34812349abcdef0 ++ ++ mov.b @(0x1234:16,r3.w),@er1 ;0178e3011234 ++ mov.b @(0x1234:16,r3.w),@(0x1:2,er1) ;0178e3111234 ++ mov.b @(0x1234:16,r3.w),@er1+ ;0178e3811234 ++ mov.b @(0x1234:16,r3.w),@-er1 ;0178e3b11234 ++ mov.b @(0x1234:16,r3.w),@+er1 ;0178e3911234 ++ mov.b @(0x1234:16,r3.w),@er1- ;0178e3a11234 ++ mov.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;0178e3c112349abc ++ mov.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;0178e3c912349abcdef0 ++ mov.b @(0x1234:16,r3.w),@(0xffff9abc:16,r3l.b) ;0178e3d312349abc ++ mov.b @(0x1234:16,r3.w),@(0xffff9abc:16,r3.w) ;0178e3e312349abc ++ mov.b @(0x1234:16,r3.w),@(0xffff9abc:16,er3.l) ;0178e3f312349abc ++ mov.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r3l.b) ;0178e3db12349abcdef0 ++ mov.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r3.w) ;0178e3eb12349abcdef0 ++ mov.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er3.l) ;0178e3fb12349abcdef0 ++ mov.b @(0x1234:16,r3.w),@0xffff9abc:16 ;0178e34012349abc ++ mov.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;0178e34812349abcdef0 ++ ++ mov.b @(0x1234:16,er3.l),@er1 ;0178f3011234 ++ mov.b @(0x1234:16,er3.l),@(0x1:2,er1) ;0178f3111234 ++ mov.b @(0x1234:16,er3.l),@er1+ ;0178f3811234 ++ mov.b @(0x1234:16,er3.l),@-er1 ;0178f3b11234 ++ mov.b @(0x1234:16,er3.l),@+er1 ;0178f3911234 ++ mov.b @(0x1234:16,er3.l),@er1- ;0178f3a11234 ++ mov.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;0178f3c112349abc ++ mov.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;0178f3c912349abcdef0 ++ mov.b @(0x1234:16,er3.l),@(0xffff9abc:16,r3l.b) ;0178f3d312349abc ++ mov.b @(0x1234:16,er3.l),@(0xffff9abc:16,r3.w) ;0178f3e312349abc ++ mov.b @(0x1234:16,er3.l),@(0xffff9abc:16,er3.l) ;0178f3f312349abc ++ mov.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r3l.b) ;0178f3db12349abcdef0 ++ mov.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r3.w) ;0178f3eb12349abcdef0 ++ mov.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er3.l) ;0178f3fb12349abcdef0 ++ mov.b @(0x1234:16,er3.l),@0xffff9abc:16 ;0178f34012349abc ++ mov.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;0178f34812349abcdef0 ++ ++ mov.b @(0x12345678:32,r3l.b),@er1 ;0178db0112345678 ++ mov.b @(0x12345678:32,r3l.b),@(0x1:2,er1) ;0178db1112345678 ++ mov.b @(0x12345678:32,r3l.b),@er1+ ;0178db8112345678 ++ mov.b @(0x12345678:32,r3l.b),@-er1 ;0178dbb112345678 ++ mov.b @(0x12345678:32,r3l.b),@+er1 ;0178db9112345678 ++ mov.b @(0x12345678:32,r3l.b),@er1- ;0178dba112345678 ++ mov.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;0178dbc1123456789abc ++ mov.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;0178dbc9123456789abcdef0 ++ mov.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r3l.b) ;0178dbd3123456789abc ++ mov.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r3.w) ;0178dbe3123456789abc ++ mov.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er3.l) ;0178dbf3123456789abc ++ mov.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3l.b) ;0178dbdb123456789abcdef0 ++ mov.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3.w) ;0178dbeb123456789abcdef0 ++ mov.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er3.l) ;0178dbfb123456789abcdef0 ++ mov.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;0178db40123456789abc ++ mov.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;0178db48123456789abcdef0 ++ ++ mov.b @(0x12345678:32,r3.w),@er1 ;0178eb0112345678 ++ mov.b @(0x12345678:32,r3.w),@(0x1:2,er1) ;0178eb1112345678 ++ mov.b @(0x12345678:32,r3.w),@er1+ ;0178eb8112345678 ++ mov.b @(0x12345678:32,r3.w),@-er1 ;0178ebb112345678 ++ mov.b @(0x12345678:32,r3.w),@+er1 ;0178eb9112345678 ++ mov.b @(0x12345678:32,r3.w),@er1- ;0178eba112345678 ++ mov.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;0178ebc1123456789abc ++ mov.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;0178ebc9123456789abcdef0 ++ mov.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r3l.b) ;0178ebd3123456789abc ++ mov.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r3.w) ;0178ebe3123456789abc ++ mov.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er3.l) ;0178ebf3123456789abc ++ mov.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3l.b) ;0178ebdb123456789abcdef0 ++ mov.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3.w) ;0178ebeb123456789abcdef0 ++ mov.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er3.l) ;0178ebfb123456789abcdef0 ++ mov.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;0178eb40123456789abc ++ mov.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;0178eb48123456789abcdef0 ++ ++ mov.b @(0x12345678:32,er3.l),@er1 ;0178fb0112345678 ++ mov.b @(0x12345678:32,er3.l),@(0x1:2,er1) ;0178fb1112345678 ++ mov.b @(0x12345678:32,er3.l),@er1+ ;0178fb8112345678 ++ mov.b @(0x12345678:32,er3.l),@-er1 ;0178fbb112345678 ++ mov.b @(0x12345678:32,er3.l),@+er1 ;0178fb9112345678 ++ mov.b @(0x12345678:32,er3.l),@er1- ;0178fba112345678 ++ mov.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;0178fbc1123456789abc ++ mov.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;0178fbc9123456789abcdef0 ++ mov.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r3l.b) ;0178fbd3123456789abc ++ mov.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r3.w) ;0178fbe3123456789abc ++ mov.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er3.l) ;0178fbf3123456789abc ++ mov.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3l.b) ;0178fbdb123456789abcdef0 ++ mov.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3.w) ;0178fbeb123456789abcdef0 ++ mov.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er3.l) ;0178fbfb123456789abcdef0 ++ mov.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;0178fb40123456789abc ++ mov.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;0178fb48123456789abcdef0 ++ ++ mov.b @0x1234:16,@er1 ;017840011234 ++ mov.b @0x1234:16,@(0x1:2,er1) ;017840111234 ++ mov.b @0x1234:16,@er1+ ;017840811234 ++ mov.b @0x1234:16,@-er1 ;017840b11234 ++ mov.b @0x1234:16,@+er1 ;017840911234 ++ mov.b @0x1234:16,@er1- ;017840a11234 ++ mov.b @0x1234:16,@(0xffff9abc:16,er1) ;017840c112349abc ++ mov.b @0x1234:16,@(0x9abcdef0:32,er1) ;017840c912349abcdef0 ++ mov.b @0x1234:16,@(0xffff9abc:16,r3l.b) ;017840d312349abc ++ mov.b @0x1234:16,@(0xffff9abc:16,r3.w) ;017840e312349abc ++ mov.b @0x1234:16,@(0xffff9abc:16,er3.l) ;017840f312349abc ++ mov.b @0x1234:16,@(0x9abcdef0:32,r3l.b) ;017840db12349abcdef0 ++ mov.b @0x1234:16,@(0x9abcdef0:32,r3.w) ;017840eb12349abcdef0 ++ mov.b @0x1234:16,@(0x9abcdef0:32,er3.l) ;017840fb12349abcdef0 ++ mov.b @0x1234:16,@0xffff9abc:16 ;0178404012349abc ++ mov.b @0x1234:16,@0x9abcdef0:32 ;0178404812349abcdef0 ++ ++ mov.b @0x12345678:32,@er1 ;0178480112345678 ++ mov.b @0x12345678:32,@(0x1:2,er1) ;0178481112345678 ++ mov.b @0x12345678:32,@er1+ ;0178488112345678 ++ mov.b @0x12345678:32,@-er1 ;017848b112345678 ++ mov.b @0x12345678:32,@+er1 ;0178489112345678 ++ mov.b @0x12345678:32,@er1- ;017848a112345678 ++ mov.b @0x12345678:32,@(0xffff9abc:16,er1) ;017848c1123456789abc ++ mov.b @0x12345678:32,@(0x9abcdef0:32,er1) ;017848c9123456789abcdef0 ++ mov.b @0x12345678:32,@(0xffff9abc:16,r3l.b) ;017848d3123456789abc ++ mov.b @0x12345678:32,@(0xffff9abc:16,r3.w) ;017848e3123456789abc ++ mov.b @0x12345678:32,@(0xffff9abc:16,er3.l) ;017848f3123456789abc ++ mov.b @0x12345678:32,@(0x9abcdef0:32,r3l.b) ;017848db123456789abcdef0 ++ mov.b @0x12345678:32,@(0x9abcdef0:32,r3.w) ;017848eb123456789abcdef0 ++ mov.b @0x12345678:32,@(0x9abcdef0:32,er3.l) ;017848fb123456789abcdef0 ++ mov.b @0x12345678:32,@0xffff9abc:16 ;01784840123456789abc ++ mov.b @0x12345678:32,@0x9abcdef0:32 ;01784848123456789abcdef0 ++ ++ mov.w #0x1234:16,r1 ;79011234 ++ mov.w #0x1:3,r3 ;0f13 ++ mov.w #0x1234:16,@er1 ;797412340100 ++ mov.w #0x1234:16,@(0x2:2,er1) ;797412341100 ++ mov.w #0x1234:16,@er1+ ;797412348100 ++ mov.w #0x1234:16,@-er1 ;79741234b100 ++ mov.w #0x1234:16,@+er1 ;797412349100 ++ mov.w #0x1234:16,@er1- ;79741234a100 ++ mov.w #0x1234:16,@(0x1234:16,er1) ;79741234c1001234 ++ mov.w #0x1234:16,@(0x12345678:32,er1) ;79741234c90012345678 ++ mov.w #0x1234:16,@(0x1234:16,r3l.b) ;79741234d3001234 ++ mov.w #0x1234:16,@(0x1234:16,r3.w) ;79741234e3001234 ++ mov.w #0x1234:16,@(0x1234:16,er3.l) ;79741234f3001234 ++ mov.w #0x1234:16,@(0x12345678:32,r3l.b) ;79741234db0012345678 ++ mov.w #0x1234:16,@(0x12345678:32,r3.w) ;79741234eb0012345678 ++ mov.w #0x1234:16,@(0x12345678:32,er3.l) ;79741234fb0012345678 ++ mov.w #0x1234:16,@0x1234:16 ;7974123440001234 ++ mov.w #0x1234:16,@0x12345678:32 ;79741234480012345678 ++ ++ mov.w #0x12:8,@er1 ;015d0112 ++ mov.w #0x12:8,@(0x2:2,er1) ;015d1112 ++ mov.w #0x12:8,@er1+ ;015d8112 ++ mov.w #0x12:8,@-er1 ;015db112 ++ mov.w #0x12:8,@+er1 ;015d9112 ++ mov.w #0x12:8,@er1- ;015da112 ++ mov.w #0x12:8,@(0x1234:16,er1) ;015dc1121234 ++ mov.w #0x12:8,@(0x12345678:32,er1) ;015dc91212345678 ++ mov.w #0x12:8,@(0x1234:16,r3l.b) ;015dd3121234 ++ mov.w #0x12:8,@(0x1234:16,r3.w) ;015de3121234 ++ mov.w #0x12:8,@(0x1234:16,er3.l) ;015df3121234 ++ mov.w #0x12:8,@(0x12345678:32,r3l.b) ;015ddb1212345678 ++ mov.w #0x12:8,@(0x12345678:32,r3.w) ;015deb1212345678 ++ mov.w #0x12:8,@(0x12345678:32,er3.l) ;015dfb1212345678 ++ mov.w #0x12:8,@0x1234:16 ;015d40121234 ++ mov.w #0x12:8,@0x12345678:32 ;015d481212345678 ++ ++ mov.w #0x1:4,@0x1234:16 ;6bd11234 ++ mov.w #0x1:4,@0x12345678:32 ;6bf112345678 ++ ++ mov.w r2,r1 ;0d21 ++ ++ mov.w r2,@er1 ;6992 ++ mov.w r2,@(0x2:2,er1) ;01516992 ++ mov.w r2,@er1+ ;01536d92 ++ mov.w r2,@-er1 ;6d92 ++ mov.w r2,@+er1 ;01526d92 ++ mov.w r2,@er1- ;01516d92 ++ mov.w r2,@(0x1234:16,er1) ;6f921234 ++ mov.w r2,@(0x12345678:32,er1) ;78106ba212345678 ++ mov.w r2,@(0x1234:16,r3l.b) ;01516fb21234 ++ mov.w r2,@(0x1234:16,r3.w) ;01526fb21234 ++ mov.w r2,@(0x1234:16,er3.l) ;01536fb21234 ++ mov.w r2,@(0x12345678:32,r3l.b) ;78316ba212345678 ++ mov.w r2,@(0x12345678:32,r3.w) ;78326ba212345678 ++ mov.w r2,@(0x12345678:32,er3.l) ;78336ba212345678 ++ mov.w r2,@0x1234:16 ;6b821234 ++ mov.w r2,@0x12345678:32 ;6ba212345678 ++ ++ mov.w @er2,r1 ;6921 ++ mov.w @(0x2:2,er2),r1 ;01516921 ++ mov.w @er2+,r1 ;6d21 ++ mov.w @-er2,r1 ;01536d21 ++ mov.w @+er2,r1 ;01516d21 ++ mov.w @er2-,r1 ;01526d21 ++ mov.w @(0x1234:16,er1),r1 ;6f111234 ++ mov.w @(0x12345678:32,er1),r1 ;78106b2112345678 ++ mov.w @(0x1234:16,r3l.b),r1 ;01516f311234 ++ mov.w @(0x1234:16,r3.w),r1 ;01526f311234 ++ mov.w @(0x1234:16,er3.l),r1 ;01536f311234 ++ mov.w @(0x12345678:32,r3l.b),r1 ;78316b2112345678 ++ mov.w @(0x12345678:32,r3.w),r1 ;78326b2112345678 ++ mov.w @(0x12345678:32,er3.l),r1 ;78336b2112345678 ++ mov.w @0x1234:16,r1 ;6b011234 ++ mov.w @0x12345678:32,r1 ;6b2112345678 ++ ++ mov.w @er2,@er1 ;01580201 ++ mov.w @er2,@(0x2:2,er1) ;01580211 ++ mov.w @er2,@er1+ ;01580281 ++ mov.w @er2,@-er1 ;015802b1 ++ mov.w @er2,@+er1 ;01580291 ++ mov.w @er2,@er1- ;015802a1 ++ mov.w @er2,@(0x1234:16,er1) ;015802c11234 ++ mov.w @er2,@(0x12345678:32,er1) ;015802c912345678 ++ mov.w @er2,@(0x1234:16,r3l.b) ;015802d31234 ++ mov.w @er2,@(0x1234:16,r3.w) ;015802e31234 ++ mov.w @er2,@(0x1234:16,er3.l) ;015802f31234 ++ mov.w @er2,@(0x12345678:32,r3l.b) ;015802db12345678 ++ mov.w @er2,@(0x12345678:32,r3.w) ;015802eb12345678 ++ mov.w @er2,@(0x12345678:32,er3.l) ;015802fb12345678 ++ mov.w @er2,@0x1234:16 ;015802401234 ++ mov.w @er2,@0x12345678:32 ;0158024812345678 ++ ++ mov.w @(0x2:2,er2),@er1 ;01581201 ++ mov.w @(0x2:2,er2),@(0x2:2,er1) ;01581211 ++ mov.w @(0x2:2,er2),@er1+ ;01581281 ++ mov.w @(0x2:2,er2),@-er1 ;015812b1 ++ mov.w @(0x2:2,er2),@+er1 ;01581291 ++ mov.w @(0x2:2,er2),@er1- ;015812a1 ++ mov.w @(0x2:2,er2),@(0x1234:16,er1) ;015812c11234 ++ mov.w @(0x2:2,er2),@(0x12345678:32,er1) ;015812c912345678 ++ mov.w @(0x2:2,er2),@(0x1234:16,r3l.b) ;015812d31234 ++ mov.w @(0x2:2,er2),@(0x1234:16,r3.w) ;015812e31234 ++ mov.w @(0x2:2,er2),@(0x1234:16,er3.l) ;015812f31234 ++ mov.w @(0x2:2,er2),@(0x12345678:32,r3l.b) ;015812db12345678 ++ mov.w @(0x2:2,er2),@(0x12345678:32,r3.w) ;015812eb12345678 ++ mov.w @(0x2:2,er2),@(0x12345678:32,er3.l) ;015812fb12345678 ++ mov.w @(0x2:2,er2),@0x1234:16 ;015812401234 ++ mov.w @(0x2:2,er2),@0x12345678:32 ;0158124812345678 ++ ++ mov.w @-er2,@er1 ;0158b201 ++ mov.w @-er2,@(0x2:2,er1) ;0158b211 ++ mov.w @-er2,@er1+ ;0158b281 ++ mov.w @-er2,@-er1 ;0158b2b1 ++ mov.w @-er2,@+er1 ;0158b291 ++ mov.w @-er2,@er1- ;0158b2a1 ++ mov.w @-er2,@(0x1234:16,er1) ;0158b2c11234 ++ mov.w @-er2,@(0x12345678:32,er1) ;0158b2c912345678 ++ mov.w @-er2,@(0x1234:16,r3l.b) ;0158b2d31234 ++ mov.w @-er2,@(0x1234:16,r3.w) ;0158b2e31234 ++ mov.w @-er2,@(0x1234:16,er3.l) ;0158b2f31234 ++ mov.w @-er2,@(0x12345678:32,r3l.b) ;0158b2db12345678 ++ mov.w @-er2,@(0x12345678:32,r3.w) ;0158b2eb12345678 ++ mov.w @-er2,@(0x12345678:32,er3.l) ;0158b2fb12345678 ++ mov.w @-er2,@0x1234:16 ;0158b2401234 ++ mov.w @-er2,@0x12345678:32 ;0158b24812345678 ++ ++ mov.w @er2+,@er1 ;01588201 ++ mov.w @er2+,@(0x2:2,er1) ;01588211 ++ mov.w @er2+,@er1+ ;01588281 ++ mov.w @er2+,@-er1 ;015882b1 ++ mov.w @er2+,@+er1 ;01588291 ++ mov.w @er2+,@er1- ;015882a1 ++ mov.w @er2+,@(0x1234:16,er1) ;015882c11234 ++ mov.w @er2+,@(0x12345678:32,er1) ;015882c912345678 ++ mov.w @er2+,@(0x1234:16,r3l.b) ;015882d31234 ++ mov.w @er2+,@(0x1234:16,r3.w) ;015882e31234 ++ mov.w @er2+,@(0x1234:16,er3.l) ;015882f31234 ++ mov.w @er2+,@(0x12345678:32,r3l.b) ;015882db12345678 ++ mov.w @er2+,@(0x12345678:32,r3.w) ;015882eb12345678 ++ mov.w @er2+,@(0x12345678:32,er3.l) ;015882fb12345678 ++ mov.w @er2+,@0x1234:16 ;015882401234 ++ mov.w @er2+,@0x12345678:32 ;0158824812345678 ++ ++ mov.w @er2-,@er1 ;0158a201 ++ mov.w @er2-,@(0x2:2,er1) ;0158a211 ++ mov.w @er2-,@er1+ ;0158a281 ++ mov.w @er2-,@-er1 ;0158a2b1 ++ mov.w @er2-,@+er1 ;0158a291 ++ mov.w @er2-,@er1- ;0158a2a1 ++ mov.w @er2-,@(0x1234:16,er1) ;0158a2c11234 ++ mov.w @er2-,@(0x12345678:32,er1) ;0158a2c912345678 ++ mov.w @er2-,@(0x1234:16,r3l.b) ;0158a2d31234 ++ mov.w @er2-,@(0x1234:16,r3.w) ;0158a2e31234 ++ mov.w @er2-,@(0x1234:16,er3.l) ;0158a2f31234 ++ mov.w @er2-,@(0x12345678:32,r3l.b) ;0158a2db12345678 ++ mov.w @er2-,@(0x12345678:32,r3.w) ;0158a2eb12345678 ++ mov.w @er2-,@(0x12345678:32,er3.l) ;0158a2fb12345678 ++ mov.w @er2-,@0x1234:16 ;0158a2401234 ++ mov.w @er2-,@0x12345678:32 ;0158a24812345678 ++ ++ mov.w @+er2,@er1 ;01589201 ++ mov.w @+er2,@(0x2:2,er1) ;01589211 ++ mov.w @+er2,@er1+ ;01589281 ++ mov.w @+er2,@-er1 ;015892b1 ++ mov.w @+er2,@+er1 ;01589291 ++ mov.w @+er2,@er1- ;015892a1 ++ mov.w @+er2,@(0x1234:16,er1) ;015892c11234 ++ mov.w @+er2,@(0x12345678:32,er1) ;015892c912345678 ++ mov.w @+er2,@(0x1234:16,r3l.b) ;015892d31234 ++ mov.w @+er2,@(0x1234:16,r3.w) ;015892e31234 ++ mov.w @+er2,@(0x1234:16,er3.l) ;015892f31234 ++ mov.w @+er2,@(0x12345678:32,r3l.b) ;015892db12345678 ++ mov.w @+er2,@(0x12345678:32,r3.w) ;015892eb12345678 ++ mov.w @+er2,@(0x12345678:32,er3.l) ;015892fb12345678 ++ mov.w @+er2,@0x1234:16 ;015892401234 ++ mov.w @+er2,@0x12345678:32 ;0158924812345678 ++ ++ mov.w @(0x1234:16,er2),@er1 ;0158c2011234 ++ mov.w @(0x1234:16,er2),@(0x2:2,er1) ;0158c2111234 ++ mov.w @(0x1234:16,er2),@er1+ ;0158c2811234 ++ mov.w @(0x1234:16,er2),@-er1 ;0158c2b11234 ++ mov.w @(0x1234:16,er2),@+er1 ;0158c2911234 ++ mov.w @(0x1234:16,er2),@er1- ;0158c2a11234 ++ mov.w @(0x1234:16,er2),@(0xffff9abc:16,er1) ;0158c2c112349abc ++ mov.w @(0x1234:16,er2),@(0x9abcdef0:32,er1) ;0158c2c912349abcdef0 ++ mov.w @(0x1234:16,er2),@(0xffff9abc:16,r3l.b) ;0158c2d312349abc ++ mov.w @(0x1234:16,er2),@(0xffff9abc:16,r3.w) ;0158c2e312349abc ++ mov.w @(0x1234:16,er2),@(0xffff9abc:16,er3.l) ;0158c2f312349abc ++ mov.w @(0x1234:16,er2),@(0x9abcdef0:32,r3l.b) ;0158c2db12349abcdef0 ++ mov.w @(0x1234:16,er2),@(0x9abcdef0:32,r3.w) ;0158c2eb12349abcdef0 ++ mov.w @(0x1234:16,er2),@(0x9abcdef0:32,er3.l) ;0158c2fb12349abcdef0 ++ mov.w @(0x1234:16,er2),@0xffff9abc:16 ;0158c24012349abc ++ mov.w @(0x1234:16,er2),@0x9abcdef0:32 ;0158c24812349abcdef0 ++ ++ mov.w @(0x12345678:32,er2),@er1 ;0158ca0112345678 ++ mov.w @(0x12345678:32,er2),@(0x2:2,er1) ;0158ca1112345678 ++ mov.w @(0x12345678:32,er2),@er1+ ;0158ca8112345678 ++ mov.w @(0x12345678:32,er2),@-er1 ;0158cab112345678 ++ mov.w @(0x12345678:32,er2),@+er1 ;0158ca9112345678 ++ mov.w @(0x12345678:32,er2),@er1- ;0158caa112345678 ++ mov.w @(0x12345678:32,er2),@(0xffff9abc:16,er1) ;0158cac1123456789abc ++ mov.w @(0x12345678:32,er2),@(0x9abcdef0:32,er1) ;0158cac9123456789abcdef0 ++ mov.w @(0x12345678:32,er2),@(0xffff9abc:16,r3l.b) ;0158cad3123456789abc ++ mov.w @(0x12345678:32,er2),@(0xffff9abc:16,r3.w) ;0158cae3123456789abc ++ mov.w @(0x12345678:32,er2),@(0xffff9abc:16,er3.l) ;0158caf3123456789abc ++ mov.w @(0x12345678:32,er2),@(0x9abcdef0:32,r3l.b) ;0158cadb123456789abcdef0 ++ mov.w @(0x12345678:32,er2),@(0x9abcdef0:32,r3.w) ;0158caeb123456789abcdef0 ++ mov.w @(0x12345678:32,er2),@(0x9abcdef0:32,er3.l) ;0158cafb123456789abcdef0 ++ mov.w @(0x12345678:32,er2),@0xffff9abc:16 ;0158ca40123456789abc ++ mov.w @(0x12345678:32,er2),@0x9abcdef0:32 ;0158ca48123456789abcdef0 ++ ++ mov.w @(0x1234:16,r3l.b),@er1 ;0158d3011234 ++ mov.w @(0x1234:16,r3l.b),@(0x2:2,er1) ;0158d3111234 ++ mov.w @(0x1234:16,r3l.b),@er1+ ;0158d3811234 ++ mov.w @(0x1234:16,r3l.b),@-er1 ;0158d3b11234 ++ mov.w @(0x1234:16,r3l.b),@+er1 ;0158d3911234 ++ mov.w @(0x1234:16,r3l.b),@er1- ;0158d3a11234 ++ mov.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;0158d3c112349abc ++ mov.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;0158d3c912349abcdef0 ++ mov.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r3l.b) ;0158d3d312349abc ++ mov.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r3.w) ;0158d3e312349abc ++ mov.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er3.l) ;0158d3f312349abc ++ mov.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r3l.b) ;0158d3db12349abcdef0 ++ mov.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r3.w) ;0158d3eb12349abcdef0 ++ mov.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er3.l) ;0158d3fb12349abcdef0 ++ mov.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;0158d34012349abc ++ mov.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;0158d34812349abcdef0 ++ ++ mov.w @(0x1234:16,r3.w),@er1 ;0158e3011234 ++ mov.w @(0x1234:16,r3.w),@(0x2:2,er1) ;0158e3111234 ++ mov.w @(0x1234:16,r3.w),@er1+ ;0158e3811234 ++ mov.w @(0x1234:16,r3.w),@-er1 ;0158e3b11234 ++ mov.w @(0x1234:16,r3.w),@+er1 ;0158e3911234 ++ mov.w @(0x1234:16,r3.w),@er1- ;0158e3a11234 ++ mov.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;0158e3c112349abc ++ mov.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;0158e3c912349abcdef0 ++ mov.w @(0x1234:16,r3.w),@(0xffff9abc:16,r3l.b) ;0158e3d312349abc ++ mov.w @(0x1234:16,r3.w),@(0xffff9abc:16,r3.w) ;0158e3e312349abc ++ mov.w @(0x1234:16,r3.w),@(0xffff9abc:16,er3.l) ;0158e3f312349abc ++ mov.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r3l.b) ;0158e3db12349abcdef0 ++ mov.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r3.w) ;0158e3eb12349abcdef0 ++ mov.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er3.l) ;0158e3fb12349abcdef0 ++ mov.w @(0x1234:16,r3.w),@0xffff9abc:16 ;0158e34012349abc ++ mov.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;0158e34812349abcdef0 ++ ++ mov.w @(0x1234:16,er3.l),@er1 ;0158f3011234 ++ mov.w @(0x1234:16,er3.l),@(0x2:2,er1) ;0158f3111234 ++ mov.w @(0x1234:16,er3.l),@er1+ ;0158f3811234 ++ mov.w @(0x1234:16,er3.l),@-er1 ;0158f3b11234 ++ mov.w @(0x1234:16,er3.l),@+er1 ;0158f3911234 ++ mov.w @(0x1234:16,er3.l),@er1- ;0158f3a11234 ++ mov.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;0158f3c112349abc ++ mov.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;0158f3c912349abcdef0 ++ mov.w @(0x1234:16,er3.l),@(0xffff9abc:16,r3l.b) ;0158f3d312349abc ++ mov.w @(0x1234:16,er3.l),@(0xffff9abc:16,r3.w) ;0158f3e312349abc ++ mov.w @(0x1234:16,er3.l),@(0xffff9abc:16,er3.l) ;0158f3f312349abc ++ mov.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r3l.b) ;0158f3db12349abcdef0 ++ mov.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r3.w) ;0158f3eb12349abcdef0 ++ mov.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er3.l) ;0158f3fb12349abcdef0 ++ mov.w @(0x1234:16,er3.l),@0xffff9abc:16 ;0158f34012349abc ++ mov.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;0158f34812349abcdef0 ++ ++ mov.w @(0x12345678:32,r3l.b),@er1 ;0158db0112345678 ++ mov.w @(0x12345678:32,r3l.b),@(0x2:2,er1) ;0158db1112345678 ++ mov.w @(0x12345678:32,r3l.b),@er1+ ;0158db8112345678 ++ mov.w @(0x12345678:32,r3l.b),@-er1 ;0158dbb112345678 ++ mov.w @(0x12345678:32,r3l.b),@+er1 ;0158db9112345678 ++ mov.w @(0x12345678:32,r3l.b),@er1- ;0158dba112345678 ++ mov.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;0158dbc1123456789abc ++ mov.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;0158dbc9123456789abcdef0 ++ mov.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r3l.b) ;0158dbd3123456789abc ++ mov.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r3.w) ;0158dbe3123456789abc ++ mov.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er3.l) ;0158dbf3123456789abc ++ mov.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3l.b) ;0158dbdb123456789abcdef0 ++ mov.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3.w) ;0158dbeb123456789abcdef0 ++ mov.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er3.l) ;0158dbfb123456789abcdef0 ++ mov.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;0158db40123456789abc ++ mov.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;0158db48123456789abcdef0 ++ ++ mov.w @(0x12345678:32,r3.w),@er1 ;0158eb0112345678 ++ mov.w @(0x12345678:32,r3.w),@(0x2:2,er1) ;0158eb1112345678 ++ mov.w @(0x12345678:32,r3.w),@er1+ ;0158eb8112345678 ++ mov.w @(0x12345678:32,r3.w),@-er1 ;0158ebb112345678 ++ mov.w @(0x12345678:32,r3.w),@+er1 ;0158eb9112345678 ++ mov.w @(0x12345678:32,r3.w),@er1- ;0158eba112345678 ++ mov.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;0158ebc1123456789abc ++ mov.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;0158ebc9123456789abcdef0 ++ mov.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r3l.b) ;0158ebd3123456789abc ++ mov.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r3.w) ;0158ebe3123456789abc ++ mov.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er3.l) ;0158ebf3123456789abc ++ mov.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3l.b) ;0158ebdb123456789abcdef0 ++ mov.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3.w) ;0158ebeb123456789abcdef0 ++ mov.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er3.l) ;0158ebfb123456789abcdef0 ++ mov.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;0158eb40123456789abc ++ mov.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;0158eb48123456789abcdef0 ++ ++ mov.w @(0x12345678:32,er3.l),@er1 ;0158fb0112345678 ++ mov.w @(0x12345678:32,er3.l),@(0x2:2,er1) ;0158fb1112345678 ++ mov.w @(0x12345678:32,er3.l),@er1+ ;0158fb8112345678 ++ mov.w @(0x12345678:32,er3.l),@-er1 ;0158fbb112345678 ++ mov.w @(0x12345678:32,er3.l),@+er1 ;0158fb9112345678 ++ mov.w @(0x12345678:32,er3.l),@er1- ;0158fba112345678 ++ mov.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;0158fbc1123456789abc ++ mov.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;0158fbc9123456789abcdef0 ++ mov.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r3l.b) ;0158fbd3123456789abc ++ mov.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r3.w) ;0158fbe3123456789abc ++ mov.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er3.l) ;0158fbf3123456789abc ++ mov.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3l.b) ;0158fbdb123456789abcdef0 ++ mov.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3.w) ;0158fbeb123456789abcdef0 ++ mov.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er3.l) ;0158fbfb123456789abcdef0 ++ mov.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;0158fb40123456789abc ++ mov.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;0158fb48123456789abcdef0 ++ ++ mov.w @0x1234:16,@er1 ;015840011234 ++ mov.w @0x1234:16,@(0x2:2,er1) ;015840111234 ++ mov.w @0x1234:16,@er1+ ;015840811234 ++ mov.w @0x1234:16,@-er1 ;015840b11234 ++ mov.w @0x1234:16,@+er1 ;015840911234 ++ mov.w @0x1234:16,@er1- ;015840a11234 ++ mov.w @0x1234:16,@(0xffff9abc:16,er1) ;015840c112349abc ++ mov.w @0x1234:16,@(0x9abcdef0:32,er1) ;015840c912349abcdef0 ++ mov.w @0x1234:16,@(0xffff9abc:16,r3l.b) ;015840d312349abc ++ mov.w @0x1234:16,@(0xffff9abc:16,r3.w) ;015840e312349abc ++ mov.w @0x1234:16,@(0xffff9abc:16,er3.l) ;015840f312349abc ++ mov.w @0x1234:16,@(0x9abcdef0:32,r3l.b) ;015840db12349abcdef0 ++ mov.w @0x1234:16,@(0x9abcdef0:32,r3.w) ;015840eb12349abcdef0 ++ mov.w @0x1234:16,@(0x9abcdef0:32,er3.l) ;015840fb12349abcdef0 ++ mov.w @0x1234:16,@0xffff9abc:16 ;0158404012349abc ++ mov.w @0x1234:16,@0x9abcdef0:32 ;0158404812349abcdef0 ++ ++ mov.w @0x12345678:32,@er1 ;0158480112345678 ++ mov.w @0x12345678:32,@(0x2:2,er1) ;0158481112345678 ++ mov.w @0x12345678:32,@er1+ ;0158488112345678 ++ mov.w @0x12345678:32,@-er1 ;015848b112345678 ++ mov.w @0x12345678:32,@+er1 ;0158489112345678 ++ mov.w @0x12345678:32,@er1- ;015848a112345678 ++ mov.w @0x12345678:32,@(0xffff9abc:16,er1) ;015848c1123456789abc ++ mov.w @0x12345678:32,@(0x9abcdef0:32,er1) ;015848c9123456789abcdef0 ++ mov.w @0x12345678:32,@(0xffff9abc:16,r3l.b) ;015848d3123456789abc ++ mov.w @0x12345678:32,@(0xffff9abc:16,r3.w) ;015848e3123456789abc ++ mov.w @0x12345678:32,@(0xffff9abc:16,er3.l) ;015848f3123456789abc ++ mov.w @0x12345678:32,@(0x9abcdef0:32,r3l.b) ;015848db123456789abcdef0 ++ mov.w @0x12345678:32,@(0x9abcdef0:32,r3.w) ;015848eb123456789abcdef0 ++ mov.w @0x12345678:32,@(0x9abcdef0:32,er3.l) ;015848fb123456789abcdef0 ++ mov.w @0x12345678:32,@0xffff9abc:16 ;01584840123456789abc ++ mov.w @0x12345678:32,@0x9abcdef0:32 ;01584848123456789abcdef0 ++ ++ mov.l #0x12345678:32,er1 ;7a0112345678 ++ ++ mov.l #0x1234:16,er1 ;7a091234 ++ ++ mov.l #0x1:3,er3 ;0f9b ++ ++ mov.l #0x12345678:32,@er1 ;7a74123456780100 ++ mov.l #0x12345678:32,@(0x4:2,er1) ;7a74123456781100 ++ mov.l #0x12345678:32,@-er1 ;7a7412345678b100 ++ mov.l #0x12345678:32,@er1+ ;7a74123456788100 ++ mov.l #0x12345678:32,@er1- ;7a7412345678a100 ++ mov.l #0x12345678:32,@+er1 ;7a74123456789100 ++ mov.l #0x12345678:32,@(0x1234:16,er1) ;7a7412345678c1001234 ++ mov.l #0x12345678:32,@(0x12345678:32,er1) ;7a7412345678c90012345678 ++ mov.l #0x12345678:32,@(0x1234:16,r3l.b) ;7a7412345678d3001234 ++ mov.l #0x12345678:32,@(0x1234:16,r3.w) ;7a7412345678e3001234 ++ mov.l #0x12345678:32,@(0x1234:16,er3.l) ;7a7412345678f3001234 ++ mov.l #0x12345678:32,@(0x12345678:32,r3l.b) ;7a7412345678db0012345678 ++ mov.l #0x12345678:32,@(0x12345678:32,r3.w) ;7a7412345678eb0012345678 ++ mov.l #0x12345678:32,@(0x12345678:32,er3.l) ;7a7412345678fb0012345678 ++ mov.l #0x12345678:32,@0x1234:16 ;7a741234567840001234 ++ mov.l #0x12345678:32,@0x12345678:32 ;7a7412345678480012345678 ++ ++ mov.l #0x1234:16,@er1 ;7a7c12340100 ++ mov.l #0x1234:16,@(0x4:2,er1) ;7a7c12341100 ++ mov.l #0x1234:16,@-er1 ;7a7c1234b100 ++ mov.l #0x1234:16,@er1+ ;7a7c12348100 ++ mov.l #0x1234:16,@er1- ;7a7c1234a100 ++ mov.l #0x1234:16,@+er1 ;7a7c12349100 ++ mov.l #0x1234:16,@(0x1234:16,er1) ;7a7c1234c1001234 ++ mov.l #0x1234:16,@(0x12345678:32,er1) ;7a7c1234c90012345678 ++ mov.l #0x1234:16,@(0x1234:16,r3l.b) ;7a7c1234d3001234 ++ mov.l #0x1234:16,@(0x1234:16,r3.w) ;7a7c1234e3001234 ++ mov.l #0x1234:16,@(0x1234:16,er3.l) ;7a7c1234f3001234 ++ mov.l #0x1234:16,@(0x12345678:32,r3l.b) ;7a7c1234db0012345678 ++ mov.l #0x1234:16,@(0x12345678:32,r3.w) ;7a7c1234eb0012345678 ++ mov.l #0x1234:16,@(0x12345678:32,er3.l) ;7a7c1234fb0012345678 ++ mov.l #0x1234:16,@0x1234:16 ;7a7c123440001234 ++ mov.l #0x1234:16,@0x12345678:32 ;7a7c1234480012345678 ++ ++ mov.l #0x12:8,@er1 ;010d0112 ++ mov.l #0x12:8,@(0x4:2,er1) ;010d1112 ++ mov.l #0x12:8,@-er1 ;010db112 ++ mov.l #0x12:8,@er1+ ;010d8112 ++ mov.l #0x12:8,@er1- ;010da112 ++ mov.l #0x12:8,@+er1 ;010d9112 ++ mov.l #0x12:8,@(0x1234:16,er1) ;010dc1121234 ++ mov.l #0x12:8,@(0x12345678:32,er1) ;010dc91212345678 ++ mov.l #0x12:8,@(0x1234:16,r3l.b) ;010dd3121234 ++ mov.l #0x12:8,@(0x1234:16,r3.w) ;010de3121234 ++ mov.l #0x12:8,@(0x1234:16,er3.l) ;010df3121234 ++ mov.l #0x12:8,@(0x12345678:32,r3l.b) ;010ddb1212345678 ++ mov.l #0x12:8,@(0x12345678:32,r3.w) ;010deb1212345678 ++ mov.l #0x12:8,@(0x12345678:32,er3.l) ;010dfb1212345678 ++ mov.l #0x12:8,@0x1234:16 ;010d40121234 ++ mov.l #0x12:8,@0x12345678:32 ;010d481212345678 ++ ++ mov.l er2,er1 ;0fa1 ++ ++ mov.l er2,@er1 ;01006992 ++ mov.l er2,@(0x4:2,er1) ;01016992 ++ mov.l er2,@-er1 ;01006d92 ++ mov.l er2,@er1+ ;01036d92 ++ mov.l er2,@er1- ;01016d92 ++ mov.l er2,@+er1 ;01026d92 ++ mov.l er2,@(0x1234:16,er1) ;01006f921234 ++ mov.l er2,@(0x12345678:32,er1) ;78906ba212345678 ++ mov.l er2,@(0x1234:16,r3l.b) ;01016fb21234 ++ mov.l er2,@(0x1234:16,r3.w) ;01026fb21234 ++ mov.l er2,@(0x1234:16,er3.l) ;01036fb21234 ++ mov.l er2,@(0x12345678:32,r3l.b) ;78b16ba212345678 ++ mov.l er2,@(0x12345678:32,r3.w) ;78b26ba212345678 ++ mov.l er2,@(0x12345678:32,er3.l) ;78b36ba212345678 ++ mov.l er2,@0x1234:16 ;01006b821234 ++ mov.l er2,@0x12345678:32 ;01006ba212345678 ++ ++ mov.l @er2,er1 ;01006921 ++ mov.l @(0x4:2,er2),er1 ;01016921 ++ mov.l @er2+,er1 ;01006d21 ++ mov.l @-er2,er1 ;01036d21 ++ mov.l @+er2,er1 ;01016d21 ++ mov.l @er2-,er1 ;01026d21 ++ mov.l @(0x1234:16,er1),er1 ;01006f111234 ++ mov.l @(0x12345678:32,er1),er1 ;78906b2112345678 ++ mov.l @(0x1234:16,r3l.b),er1 ;01016f311234 ++ mov.l @(0x1234:16,r3.w),er1 ;01026f311234 ++ mov.l @(0x1234:16,er3.l),er1 ;01036f311234 ++ mov.l @(0x12345678:32,r3l.b),er1 ;78b16b2112345678 ++ mov.l @(0x12345678:32,r3.w),er1 ;78b26b2112345678 ++ mov.l @(0x12345678:32,er3.l),er1 ;78b36b2112345678 ++ mov.l @0x1234:16,er1 ;01006b011234 ++ mov.l @0x12345678:32,er1 ;01006b2112345678 ++ ++ mov.l @er2,@er1 ;01080201 ++ mov.l @er2,@(0x4:2,er1) ;01080211 ++ mov.l @er2,@er1+ ;01080281 ++ mov.l @er2,@-er1 ;010802b1 ++ mov.l @er2,@+er1 ;01080291 ++ mov.l @er2,@er1- ;010802a1 ++ mov.l @er2,@(0x1234:16,er1) ;010802c11234 ++ mov.l @er2,@(0x12345678:32,er1) ;010802c912345678 ++ mov.l @er2,@(0x1234:16,r3l.b) ;010802d31234 ++ mov.l @er2,@(0x1234:16,r3.w) ;010802e31234 ++ mov.l @er2,@(0x1234:16,er3.l) ;010802f31234 ++ mov.l @er2,@(0x12345678:32,r3l.b) ;010802db12345678 ++ mov.l @er2,@(0x12345678:32,r3.w) ;010802eb12345678 ++ mov.l @er2,@(0x12345678:32,er3.l) ;010802fb12345678 ++ mov.l @er2,@0x1234:16 ;010802401234 ++ mov.l @er2,@0x12345678:32 ;0108024812345678 ++ ++ mov.l @(0x4:2,er2),@er1 ;01081201 ++ mov.l @(0x4:2,er2),@(0x4:2,er1) ;01081211 ++ mov.l @(0x4:2,er2),@er1+ ;01081281 ++ mov.l @(0x4:2,er2),@-er1 ;010812b1 ++ mov.l @(0x4:2,er2),@+er1 ;01081291 ++ mov.l @(0x4:2,er2),@er1- ;010812a1 ++ mov.l @(0x4:2,er2),@(0x1234:16,er1) ;010812c11234 ++ mov.l @(0x4:2,er2),@(0x12345678:32,er1) ;010812c912345678 ++ mov.l @(0x4:2,er2),@(0x1234:16,r3l.b) ;010812d31234 ++ mov.l @(0x4:2,er2),@(0x1234:16,r3.w) ;010812e31234 ++ mov.l @(0x4:2,er2),@(0x1234:16,er3.l) ;010812f31234 ++ mov.l @(0x4:2,er2),@(0x12345678:32,r3l.b) ;010812db12345678 ++ mov.l @(0x4:2,er2),@(0x12345678:32,r3.w) ;010812eb12345678 ++ mov.l @(0x4:2,er2),@(0x12345678:32,er3.l) ;010812fb12345678 ++ mov.l @(0x4:2,er2),@0x1234:16 ;010812401234 ++ mov.l @(0x4:2,er2),@0x12345678:32 ;0108124812345678 ++ ++ mov.l @-er2,@er1 ;0108b201 ++ mov.l @-er2,@(0x4:2,er1) ;0108b211 ++ mov.l @-er2,@er1+ ;0108b281 ++ mov.l @-er2,@-er1 ;0108b2b1 ++ mov.l @-er2,@+er1 ;0108b291 ++ mov.l @-er2,@er1- ;0108b2a1 ++ mov.l @-er2,@(0x1234:16,er1) ;0108b2c11234 ++ mov.l @-er2,@(0x12345678:32,er1) ;0108b2c912345678 ++ mov.l @-er2,@(0x1234:16,r3l.b) ;0108b2d31234 ++ mov.l @-er2,@(0x1234:16,r3.w) ;0108b2e31234 ++ mov.l @-er2,@(0x1234:16,er3.l) ;0108b2f31234 ++ mov.l @-er2,@(0x12345678:32,r3l.b) ;0108b2db12345678 ++ mov.l @-er2,@(0x12345678:32,r3.w) ;0108b2eb12345678 ++ mov.l @-er2,@(0x12345678:32,er3.l) ;0108b2fb12345678 ++ mov.l @-er2,@0x1234:16 ;0108b2401234 ++ mov.l @-er2,@0x12345678:32 ;0108b24812345678 ++ ++ mov.l @er2+,@er1 ;01088201 ++ mov.l @er2+,@(0x4:2,er1) ;01088211 ++ mov.l @er2+,@er1+ ;01088281 ++ mov.l @er2+,@-er1 ;010882b1 ++ mov.l @er2+,@+er1 ;01088291 ++ mov.l @er2+,@er1- ;010882a1 ++ mov.l @er2+,@(0x1234:16,er1) ;010882c11234 ++ mov.l @er2+,@(0x12345678:32,er1) ;010882c912345678 ++ mov.l @er2+,@(0x1234:16,r3l.b) ;010882d31234 ++ mov.l @er2+,@(0x1234:16,r3.w) ;010882e31234 ++ mov.l @er2+,@(0x1234:16,er3.l) ;010882f31234 ++ mov.l @er2+,@(0x12345678:32,r3l.b) ;010882db12345678 ++ mov.l @er2+,@(0x12345678:32,r3.w) ;010882eb12345678 ++ mov.l @er2+,@(0x12345678:32,er3.l) ;010882fb12345678 ++ mov.l @er2+,@0x1234:16 ;010882401234 ++ mov.l @er2+,@0x12345678:32 ;0108824812345678 ++ ++ mov.l @er2-,@er1 ;0108a201 ++ mov.l @er2-,@(0x4:2,er1) ;0108a211 ++ mov.l @er2-,@er1+ ;0108a281 ++ mov.l @er2-,@-er1 ;0108a2b1 ++ mov.l @er2-,@+er1 ;0108a291 ++ mov.l @er2-,@er1- ;0108a2a1 ++ mov.l @er2-,@(0x1234:16,er1) ;0108a2c11234 ++ mov.l @er2-,@(0x12345678:32,er1) ;0108a2c912345678 ++ mov.l @er2-,@(0x1234:16,r3l.b) ;0108a2d31234 ++ mov.l @er2-,@(0x1234:16,r3.w) ;0108a2e31234 ++ mov.l @er2-,@(0x1234:16,er3.l) ;0108a2f31234 ++ mov.l @er2-,@(0x12345678:32,r3l.b) ;0108a2db12345678 ++ mov.l @er2-,@(0x12345678:32,r3.w) ;0108a2eb12345678 ++ mov.l @er2-,@(0x12345678:32,er3.l) ;0108a2fb12345678 ++ mov.l @er2-,@0x1234:16 ;0108a2401234 ++ mov.l @er2-,@0x12345678:32 ;0108a24812345678 ++ ++ mov.l @+er2,@er1 ;01089201 ++ mov.l @+er2,@(0x4:2,er1) ;01089211 ++ mov.l @+er2,@er1+ ;01089281 ++ mov.l @+er2,@-er1 ;010892b1 ++ mov.l @+er2,@+er1 ;01089291 ++ mov.l @+er2,@er1- ;010892a1 ++ mov.l @+er2,@(0x1234:16,er1) ;010892c11234 ++ mov.l @+er2,@(0x12345678:32,er1) ;010892c912345678 ++ mov.l @+er2,@(0x1234:16,r3l.b) ;010892d31234 ++ mov.l @+er2,@(0x1234:16,r3.w) ;010892e31234 ++ mov.l @+er2,@(0x1234:16,er3.l) ;010892f31234 ++ mov.l @+er2,@(0x12345678:32,r3l.b) ;010892db12345678 ++ mov.l @+er2,@(0x12345678:32,r3.w) ;010892eb12345678 ++ mov.l @+er2,@(0x12345678:32,er3.l) ;010892fb12345678 ++ mov.l @+er2,@0x1234:16 ;010892401234 ++ mov.l @+er2,@0x12345678:32 ;0108924812345678 ++ ++ mov.l @(0x1234:16,er2),@er1 ;0108c2011234 ++ mov.l @(0x1234:16,er2),@(0x4:2,er1) ;0108c2111234 ++ mov.l @(0x1234:16,er2),@er1+ ;0108c2811234 ++ mov.l @(0x1234:16,er2),@-er1 ;0108c2b11234 ++ mov.l @(0x1234:16,er2),@+er1 ;0108c2911234 ++ mov.l @(0x1234:16,er2),@er1- ;0108c2a11234 ++ mov.l @(0x1234:16,er2),@(0xffff9abc:16,er1) ;0108c2c112349abc ++ mov.l @(0x1234:16,er2),@(0x9abcdef0:32,er1) ;0108c2c912349abcdef0 ++ mov.l @(0x1234:16,er2),@(0xffff9abc:16,r3l.b) ;0108c2d312349abc ++ mov.l @(0x1234:16,er2),@(0xffff9abc:16,r3.w) ;0108c2e312349abc ++ mov.l @(0x1234:16,er2),@(0xffff9abc:16,er3.l) ;0108c2f312349abc ++ mov.l @(0x1234:16,er2),@(0x9abcdef0:32,r3l.b) ;0108c2db12349abcdef0 ++ mov.l @(0x1234:16,er2),@(0x9abcdef0:32,r3.w) ;0108c2eb12349abcdef0 ++ mov.l @(0x1234:16,er2),@(0x9abcdef0:32,er3.l) ;0108c2fb12349abcdef0 ++ mov.l @(0x1234:16,er2),@0xffff9abc:16 ;0108c24012349abc ++ mov.l @(0x1234:16,er2),@0x9abcdef0:32 ;0108c24812349abcdef0 ++ ++ mov.l @(0x12345678:32,er2),@er1 ;0108ca0112345678 ++ mov.l @(0x12345678:32,er2),@(0x4:2,er1) ;0108ca1112345678 ++ mov.l @(0x12345678:32,er2),@er1+ ;0108ca8112345678 ++ mov.l @(0x12345678:32,er2),@-er1 ;0108cab112345678 ++ mov.l @(0x12345678:32,er2),@+er1 ;0108ca9112345678 ++ mov.l @(0x12345678:32,er2),@er1- ;0108caa112345678 ++ mov.l @(0x12345678:32,er2),@(0xffff9abc:16,er1) ;0108cac1123456789abc ++ mov.l @(0x12345678:32,er2),@(0x9abcdef0:32,er1) ;0108cac9123456789abcdef0 ++ mov.l @(0x12345678:32,er2),@(0xffff9abc:16,r3l.b) ;0108cad3123456789abc ++ mov.l @(0x12345678:32,er2),@(0xffff9abc:16,r3.w) ;0108cae3123456789abc ++ mov.l @(0x12345678:32,er2),@(0xffff9abc:16,er3.l) ;0108caf3123456789abc ++ mov.l @(0x12345678:32,er2),@(0x9abcdef0:32,r3l.b) ;0108cadb123456789abcdef0 ++ mov.l @(0x12345678:32,er2),@(0x9abcdef0:32,r3.w) ;0108caeb123456789abcdef0 ++ mov.l @(0x12345678:32,er2),@(0x9abcdef0:32,er3.l) ;0108cafb123456789abcdef0 ++ mov.l @(0x12345678:32,er2),@0xffff9abc:16 ;0108ca40123456789abc ++ mov.l @(0x12345678:32,er2),@0x9abcdef0:32 ;0108ca48123456789abcdef0 ++ ++ mov.l @(0x1234:16,r3l.b),@er1 ;0108d3011234 ++ mov.l @(0x1234:16,r3l.b),@(0x4:2,er1) ;0108d3111234 ++ mov.l @(0x1234:16,r3l.b),@er1+ ;0108d3811234 ++ mov.l @(0x1234:16,r3l.b),@-er1 ;0108d3b11234 ++ mov.l @(0x1234:16,r3l.b),@+er1 ;0108d3911234 ++ mov.l @(0x1234:16,r3l.b),@er1- ;0108d3a11234 ++ mov.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;0108d3c112349abc ++ mov.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;0108d3c912349abcdef0 ++ mov.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r3l.b) ;0108d3d312349abc ++ mov.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r3.w) ;0108d3e312349abc ++ mov.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er3.l) ;0108d3f312349abc ++ mov.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r3l.b) ;0108d3db12349abcdef0 ++ mov.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r3.w) ;0108d3eb12349abcdef0 ++ mov.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er3.l) ;0108d3fb12349abcdef0 ++ mov.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;0108d34012349abc ++ mov.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;0108d34812349abcdef0 ++ ++ mov.l @(0x1234:16,r3.w),@er1 ;0108e3011234 ++ mov.l @(0x1234:16,r3.w),@(0x4:2,er1) ;0108e3111234 ++ mov.l @(0x1234:16,r3.w),@er1+ ;0108e3811234 ++ mov.l @(0x1234:16,r3.w),@-er1 ;0108e3b11234 ++ mov.l @(0x1234:16,r3.w),@+er1 ;0108e3911234 ++ mov.l @(0x1234:16,r3.w),@er1- ;0108e3a11234 ++ mov.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;0108e3c112349abc ++ mov.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;0108e3c912349abcdef0 ++ mov.l @(0x1234:16,r3.w),@(0xffff9abc:16,r3l.b) ;0108e3d312349abc ++ mov.l @(0x1234:16,r3.w),@(0xffff9abc:16,r3.w) ;0108e3e312349abc ++ mov.l @(0x1234:16,r3.w),@(0xffff9abc:16,er3.l) ;0108e3f312349abc ++ mov.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r3l.b) ;0108e3db12349abcdef0 ++ mov.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r3.w) ;0108e3eb12349abcdef0 ++ mov.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er3.l) ;0108e3fb12349abcdef0 ++ mov.l @(0x1234:16,r3.w),@0xffff9abc:16 ;0108e34012349abc ++ mov.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;0108e34812349abcdef0 ++ ++ mov.l @(0x1234:16,er3.l),@er1 ;0108f3011234 ++ mov.l @(0x1234:16,er3.l),@(0x4:2,er1) ;0108f3111234 ++ mov.l @(0x1234:16,er3.l),@er1+ ;0108f3811234 ++ mov.l @(0x1234:16,er3.l),@-er1 ;0108f3b11234 ++ mov.l @(0x1234:16,er3.l),@+er1 ;0108f3911234 ++ mov.l @(0x1234:16,er3.l),@er1- ;0108f3a11234 ++ mov.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;0108f3c112349abc ++ mov.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;0108f3c912349abcdef0 ++ mov.l @(0x1234:16,er3.l),@(0xffff9abc:16,r3l.b) ;0108f3d312349abc ++ mov.l @(0x1234:16,er3.l),@(0xffff9abc:16,r3.w) ;0108f3e312349abc ++ mov.l @(0x1234:16,er3.l),@(0xffff9abc:16,er3.l) ;0108f3f312349abc ++ mov.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r3l.b) ;0108f3db12349abcdef0 ++ mov.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r3.w) ;0108f3eb12349abcdef0 ++ mov.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er3.l) ;0108f3fb12349abcdef0 ++ mov.l @(0x1234:16,er3.l),@0xffff9abc:16 ;0108f34012349abc ++ mov.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;0108f34812349abcdef0 ++ ++ mov.l @(0x12345678:32,r3l.b),@er1 ;0108db0112345678 ++ mov.l @(0x12345678:32,r3l.b),@(0x4:2,er1) ;0108db1112345678 ++ mov.l @(0x12345678:32,r3l.b),@er1+ ;0108db8112345678 ++ mov.l @(0x12345678:32,r3l.b),@-er1 ;0108dbb112345678 ++ mov.l @(0x12345678:32,r3l.b),@+er1 ;0108db9112345678 ++ mov.l @(0x12345678:32,r3l.b),@er1- ;0108dba112345678 ++ mov.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;0108dbc1123456789abc ++ mov.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;0108dbc9123456789abcdef0 ++ mov.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r3l.b) ;0108dbd3123456789abc ++ mov.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r3.w) ;0108dbe3123456789abc ++ mov.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er3.l) ;0108dbf3123456789abc ++ mov.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3l.b) ;0108dbdb123456789abcdef0 ++ mov.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r3.w) ;0108dbeb123456789abcdef0 ++ mov.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er3.l) ;0108dbfb123456789abcdef0 ++ mov.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;0108db40123456789abc ++ mov.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;0108db48123456789abcdef0 ++ ++ mov.l @(0x12345678:32,r3.w),@er1 ;0108eb0112345678 ++ mov.l @(0x12345678:32,r3.w),@(0x4:2,er1) ;0108eb1112345678 ++ mov.l @(0x12345678:32,r3.w),@er1+ ;0108eb8112345678 ++ mov.l @(0x12345678:32,r3.w),@-er1 ;0108ebb112345678 ++ mov.l @(0x12345678:32,r3.w),@+er1 ;0108eb9112345678 ++ mov.l @(0x12345678:32,r3.w),@er1- ;0108eba112345678 ++ mov.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;0108ebc1123456789abc ++ mov.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;0108ebc9123456789abcdef0 ++ mov.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r3l.b) ;0108ebd3123456789abc ++ mov.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r3.w) ;0108ebe3123456789abc ++ mov.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er3.l) ;0108ebf3123456789abc ++ mov.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3l.b) ;0108ebdb123456789abcdef0 ++ mov.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r3.w) ;0108ebeb123456789abcdef0 ++ mov.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er3.l) ;0108ebfb123456789abcdef0 ++ mov.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;0108eb40123456789abc ++ mov.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;0108eb48123456789abcdef0 ++ ++ mov.l @(0x12345678:32,er3.l),@er1 ;0108fb0112345678 ++ mov.l @(0x12345678:32,er3.l),@(0x4:2,er1) ;0108fb1112345678 ++ mov.l @(0x12345678:32,er3.l),@er1+ ;0108fb8112345678 ++ mov.l @(0x12345678:32,er3.l),@-er1 ;0108fbb112345678 ++ mov.l @(0x12345678:32,er3.l),@+er1 ;0108fb9112345678 ++ mov.l @(0x12345678:32,er3.l),@er1- ;0108fba112345678 ++ mov.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;0108fbc1123456789abc ++ mov.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;0108fbc9123456789abcdef0 ++ mov.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r3l.b) ;0108fbd3123456789abc ++ mov.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r3.w) ;0108fbe3123456789abc ++ mov.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er3.l) ;0108fbf3123456789abc ++ mov.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3l.b) ;0108fbdb123456789abcdef0 ++ mov.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r3.w) ;0108fbeb123456789abcdef0 ++ mov.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er3.l) ;0108fbfb123456789abcdef0 ++ mov.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;0108fb40123456789abc ++ mov.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;0108fb48123456789abcdef0 ++ ++ mov.l @0x1234:16,@er1 ;010840011234 ++ mov.l @0x1234:16,@(0x4:2,er1) ;010840111234 ++ mov.l @0x1234:16,@er1+ ;010840811234 ++ mov.l @0x1234:16,@-er1 ;010840b11234 ++ mov.l @0x1234:16,@+er1 ;010840911234 ++ mov.l @0x1234:16,@er1- ;010840a11234 ++ mov.l @0x1234:16,@(0xffff9abc:16,er1) ;010840c112349abc ++ mov.l @0x1234:16,@(0x9abcdef0:32,er1) ;010840c912349abcdef0 ++ mov.l @0x1234:16,@(0xffff9abc:16,r3l.b) ;010840d312349abc ++ mov.l @0x1234:16,@(0xffff9abc:16,r3.w) ;010840e312349abc ++ mov.l @0x1234:16,@(0xffff9abc:16,er3.l) ;010840f312349abc ++ mov.l @0x1234:16,@(0x9abcdef0:32,r3l.b) ;010840db12349abcdef0 ++ mov.l @0x1234:16,@(0x9abcdef0:32,r3.w) ;010840eb12349abcdef0 ++ mov.l @0x1234:16,@(0x9abcdef0:32,er3.l) ;010840fb12349abcdef0 ++ mov.l @0x1234:16,@0xffff9abc:16 ;0108404012349abc ++ mov.l @0x1234:16,@0x9abcdef0:32 ;0108404812349abcdef0 ++ ++ mov.l @0x12345678:32,@er1 ;0108480112345678 ++ mov.l @0x12345678:32,@(0x4:2,er1) ;0108481112345678 ++ mov.l @0x12345678:32,@er1+ ;0108488112345678 ++ mov.l @0x12345678:32,@-er1 ;010848b112345678 ++ mov.l @0x12345678:32,@+er1 ;0108489112345678 ++ mov.l @0x12345678:32,@er1- ;010848a112345678 ++ mov.l @0x12345678:32,@(0xffff9abc:16,er1) ;010848c1123456789abc ++ mov.l @0x12345678:32,@(0x9abcdef0:32,er1) ;010848c9123456789abcdef0 ++ mov.l @0x12345678:32,@(0xffff9abc:16,r3l.b) ;010848d3123456789abc ++ mov.l @0x12345678:32,@(0xffff9abc:16,r3.w) ;010848e3123456789abc ++ mov.l @0x12345678:32,@(0xffff9abc:16,er3.l) ;010848f3123456789abc ++ mov.l @0x12345678:32,@(0x9abcdef0:32,r3l.b) ;010848db123456789abcdef0 ++ mov.l @0x12345678:32,@(0x9abcdef0:32,r3.w) ;010848eb123456789abcdef0 ++ mov.l @0x12345678:32,@(0x9abcdef0:32,er3.l) ;010848fb123456789abcdef0 ++ mov.l @0x12345678:32,@0xffff9abc:16 ;01084840123456789abc ++ mov.l @0x12345678:32,@0x9abcdef0:32 ;01084848123456789abcdef0 ++ ++ movtpe.b r2h,@0x1234:16 ;6ac21234 ++ movfpe.b @0x1234:16,r1h ;6a411234 ++ ++ ldm @sp+,(er0-er1) ;01106d71 ++ ldm @sp+,(er1-er2) ;01106d72 ++ ldm @sp+,(er2-er3) ;01106d73 ++ ldm @sp+,(er3-er4) ;01106d74 ++ ldm @sp+,(er4-er5) ;01106d75 ++ ldm @sp+,(er5-er6) ;01106d76 ++ ldm @sp+,(er6-er7) ;01106d77 ++ ++ ldm @sp+,(er0-er2) ;01206d72 ++ ldm @sp+,(er1-er3) ;01206d73 ++ ldm @sp+,(er2-er4) ;01206d74 ++ ldm @sp+,(er3-er5) ;01206d75 ++ ldm @sp+,(er4-er6) ;01206d76 ++ ldm @sp+,(er5-er7) ;01206d77 ++ ++ ldm @sp+,(er0-er3) ;01306d73 ++ ldm @sp+,(er1-er4) ;01306d74 ++ ldm @sp+,(er2-er5) ;01306d75 ++ ldm @sp+,(er3-er6) ;01306d76 ++ ldm @sp+,(er4-er7) ;01306d77 ++ ++ stm (er0-er1),@-sp ;01106df0 ++ stm (er1-er2),@-sp ;01106df1 ++ stm (er2-er3),@-sp ;01106df2 ++ stm (er3-er4),@-sp ;01106df3 ++ stm (er4-er5),@-sp ;01106df4 ++ stm (er5-er6),@-sp ;01106df5 ++ stm (er6-er7),@-sp ;01106df6 ++ ++ stm (er0-er2),@-sp ;01206df0 ++ stm (er1-er3),@-sp ;01206df1 ++ stm (er2-er4),@-sp ;01206df2 ++ stm (er3-er5),@-sp ;01206df3 ++ stm (er4-er6),@-sp ;01206df4 ++ stm (er5-er7),@-sp ;01206df5 ++ ++ stm (er0-er3),@-sp ;01306df0 ++ stm (er1-er4),@-sp ;01306df1 ++ stm (er2-er5),@-sp ;01306df2 ++ stm (er3-er6),@-sp ;01306df3 ++ stm (er4-er7),@-sp ;01306df4 ++ ++ eepmov.b ;7b5c598f ++ ++ eepmov.w ;7bd4598f ++ ++ movmd.b ;7b94 ++ movmd.w ;7ba4 ++ movmd.l ;7bb4 ++ movsd.b label ;7b840004 ++ nop ;0000 ++ nop ;0000 ++label: ++ ++ .end ++ diff --git a/gas/testsuite/gas/h8300/t02_mova.exp b/gas/testsuite/gas/h8300/t02_mova.exp new file mode 100644 -index 0000000..c44b5cb +index 0000000..0e3a496 --- /dev/null +++ b/gas/testsuite/gas/h8300/t02_mova.exp -@@ -0,0 +1,731 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,730 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1155329,255 +1162509,254 @@ index 0000000..c44b5cb + diff --git a/gas/testsuite/gas/h8300/t02_mova.s b/gas/testsuite/gas/h8300/t02_mova.s new file mode 100644 -index 0000000..df3fcdb +index 0000000..945e6f7 --- /dev/null +++ b/gas/testsuite/gas/h8300/t02_mova.s @@ -0,0 +1,237 @@ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+;mova -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ .h8300sx -+ .text -+_start: -+ mova/b.c @(0x1234:16,r3l.b),er1 ;7A891234 -+ mova/b.c @(0x1234:16,r3.w),er1 ;7A991234 -+ mova/w.c @(0x1234:16,r3l.b),er1 ;7AA91234 -+ mova/w.c @(0x1234:16,r3.w),er1 ;7AB91234 -+ mova/l.c @(0x1234:16,r3l.b),er1 ;7AC91234 -+ mova/l.c @(0x1234:16,r3.w),er1 ;7AD91234 -+ mova/b.c @(0x12345678:32,r3l.b),er1 ;7A8112345678 -+ mova/b.c @(0x12345678:32,r3.w),er1 ;7A9112345678 -+ mova/w.c @(0x12345678:32,r3l.b),er1 ;7AA112345678 -+ mova/w.c @(0x12345678:32,r3.w),er1 ;7AB112345678 -+ mova/l.c @(0x12345678:32,r3l.b),er1 ;7AC112345678 -+ mova/l.c @(0x12345678:32,r3.w),er1 ;7AD112345678 -+ -+ mova/b.l @(0x1234:16,r3l.b),er1 ;78B87A891234 -+ mova/b.l @(0x1234:16,r3.w),er1 ;78397A991234 -+ mova/w.l @(0x1234:16,r3l.b),er1 ;78B87AA91234 -+ mova/w.l @(0x1234:16,r3.w),er1 ;78397AB91234 -+ mova/l.l @(0x1234:16,r3l.b),er1 ;78B87AC91234 -+ mova/l.l @(0x1234:16,r3.w),er1 ;78397AD91234 -+ mova/b.l @(0x12345678:32,r3l.b),er1 ;78B87A8112345678 -+ mova/b.l @(0x12345678:32,r3.w),er1 ;78397A9112345678 -+ mova/w.l @(0x12345678:32,r3l.b),er1 ;78B87AA112345678 -+ mova/w.l @(0x12345678:32,r3.w),er1 ;78397AB112345678 -+ mova/l.l @(0x12345678:32,r3l.b),er1 ;78B87AC112345678 -+ mova/l.l @(0x12345678:32,r3.w),er1 ;78397AD112345678 -+ -+ mova/b.l @(0x1234:16,@er2.b),er1 ;017F02811234 -+ mova/b.l @(0x1234:16,@(0x1:2,er2).b),er1 ;017F12811234 -+ mova/b.l @(0x1234:16,@er2+.b),er1 ;017F82811234 -+ mova/b.l @(0x1234:16,@-er2.b),er1 ;017FB2811234 -+ mova/b.l @(0x1234:16,@+er2.b),er1 ;017F92811234 -+ mova/b.l @(0x1234:16,@er2-.b),er1 ;017FA2811234 -+ mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,er2).b),er1 ;017FC2819ABC1234 -+ mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,er2).b),er1 ;017FCA819ABCDEF01234 -+ mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,r2L.b).b),er1 ;017FD2819ABC1234 -+ mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,r2.w).b),er1 ;017FE2819ABC1234 -+ mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,er2.l).b),er1 ;017FF2819ABC1234 -+ mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,r2L.b).b),er1 ;017FDA819ABCDEF01234 -+ mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,r2.w).b),er1 ;017FEA819ABCDEF01234 -+ mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,er2.l).b),er1 ;017FFA819ABCDEF01234 -+ mova/b.l @(0x1234:16,@0xFFFF9ABC:16.b),er1 ;017F40819ABC1234 -+ mova/b.l @(0x1234:16,@0x9ABCDEF0:32.b),er1 ;017F48819ABCDEF01234 -+ -+ mova/b.l @(0x1234:16,@er2.w),er1 ;015F02911234 -+ mova/b.l @(0x1234:16,@(0x2:2,er2).w),er1 ;015F12911234 -+ mova/b.l @(0x1234:16,@er2+.w),er1 ;015F82911234 -+ mova/b.l @(0x1234:16,@-er2.w),er1 ;015FB2911234 -+ mova/b.l @(0x1234:16,@+er2.w),er1 ;015F92911234 -+ mova/b.l @(0x1234:16,@er2-.w),er1 ;015FA2911234 -+ mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,er2).w),er1 ;015FC2919ABC1234 -+ mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,er2).w),er1 ;015FCA919ABCDEF01234 -+ mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,r2L.b).w),er1 ;015FD2919ABC1234 -+ mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,r2.w).w),er1 ;015FE2919ABC1234 -+ mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,er2.l).w),er1 ;015FF2919ABC1234 -+ mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,r2L.b).w),er1 ;015FDA919ABCDEF01234 -+ mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,r2.w).w),er1 ;015FEA919ABCDEF01234 -+ mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,er2.l).w),er1 ;015FFA919ABCDEF01234 -+ mova/b.l @(0x1234:16,@0xFFFF9ABC:16.w),er1 ;015F40919ABC1234 -+ mova/b.l @(0x1234:16,@0x9ABCDEF0:32.w),er1 ;015F48919ABCDEF01234 -+ -+ mova/w.l @(0x1234:16,@er2.b),er1 ;017F02A11234 -+ mova/w.l @(0x1234:16,@(0x1:2,er2).b),er1 ;017F12A11234 -+ mova/w.l @(0x1234:16,@er2+.b),er1 ;017F82A11234 -+ mova/w.l @(0x1234:16,@-er2.b),er1 ;017FB2A11234 -+ mova/w.l @(0x1234:16,@+er2.b),er1 ;017F92A11234 -+ mova/w.l @(0x1234:16,@er2-.b),er1 ;017FA2A11234 -+ mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,er2).b),er1 ;017FC2A19ABC1234 -+ mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,er2).b),er1 ;017FCAA19ABCDEF01234 -+ mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,r2L.b).b),er1 ;017FD2A19ABC1234 -+ mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,r2.w).b),er1 ;017FE2A19ABC1234 -+ mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,er2.l).b),er1 ;017FF2A19ABC1234 -+ mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,r2L.b).b),er1 ;017FDAA19ABCDEF01234 -+ mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,r2.w).b),er1 ;017FEAA19ABCDEF01234 -+ mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,er2.l).b),er1 ;017FFAA19ABCDEF01234 -+ mova/w.l @(0x1234:16,@0xFFFF9ABC:16.b),er1 ;017F40A19ABC1234 -+ mova/w.l @(0x1234:16,@0x9ABCDEF0:32.b),er1 ;017F48A19ABCDEF01234 -+ -+ mova/w.l @(0x1234:16,@er2.w),er1 ;015F02B11234 -+ mova/w.l @(0x1234:16,@(0x2:2,er2).w),er1 ;015F12B11234 -+ mova/w.l @(0x1234:16,@er2+.w),er1 ;015F82B11234 -+ mova/w.l @(0x1234:16,@-er2.w),er1 ;015FB2B11234 -+ mova/w.l @(0x1234:16,@+er2.w),er1 ;015F92B11234 -+ mova/w.l @(0x1234:16,@er2-.w),er1 ;015FA2B11234 -+ mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,er2).w),er1 ;015FC2B19ABC1234 -+ mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,er2).w),er1 ;015FCAB19ABCDEF01234 -+ mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,r2L.b).w),er1 ;015FD2B19ABC1234 -+ mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,r2.w).w),er1 ;015FE2B19ABC1234 -+ mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,er2.l).w),er1 ;015FF2B19ABC1234 -+ mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,r2L.b).w),er1 ;015FDAB19ABCDEF01234 -+ mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,r2.w).w),er1 ;015FEAB19ABCDEF01234 -+ mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,er2.l).w),er1 ;015FFAB19ABCDEF01234 -+ mova/w.l @(0x1234:16,@0xFFFF9ABC:16.w),er1 ;015F40B19ABC1234 -+ mova/w.l @(0x1234:16,@0x9ABCDEF0:32.w),er1 ;015F48B19ABCDEF01234 -+ -+ mova/l.l @(0x1234:16,@er2.b),er1 ;017F02C11234 -+ mova/l.l @(0x1234:16,@(0x1:2,er2).b),er1 ;017F12C11234 -+ mova/l.l @(0x1234:16,@er2+.b),er1 ;017F82C11234 -+ mova/l.l @(0x1234:16,@-er2.b),er1 ;017FB2C11234 -+ mova/l.l @(0x1234:16,@+er2.b),er1 ;017F92C11234 -+ mova/l.l @(0x1234:16,@er2-.b),er1 ;017FA2C11234 -+ mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,er2).b),er1 ;017FC2C19ABC1234 -+ mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,er2).b),er1 ;017FCAC19ABCDEF01234 -+ mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,r2L.b).b),er1 ;017FD2C19ABC1234 -+ mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,r2.w).b),er1 ;017FE2C19ABC1234 -+ mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,er2.l).b),er1 ;017FF2C19ABC1234 -+ mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,r2L.b).b),er1 ;017FDAC19ABCDEF01234 -+ mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,r2.w).b),er1 ;017FEAC19ABCDEF01234 -+ mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,er2.l).b),er1 ;017FFAC19ABCDEF01234 -+ mova/l.l @(0x1234:16,@0xFFFF9ABC:16.b),er1 ;017F40C19ABC1234 -+ mova/l.l @(0x1234:16,@0x9ABCDEF0:32.b),er1 ;017F48C19ABCDEF01234 -+ -+ mova/l.l @(0x1234:16,@er2.w),er1 ;015F02D11234 -+ mova/l.l @(0x1234:16,@(0x2:2,er2).w),er1 ;015F12D11234 -+ mova/l.l @(0x1234:16,@er2+.w),er1 ;015F82D11234 -+ mova/l.l @(0x1234:16,@-er2.w),er1 ;015FB2D11234 -+ mova/l.l @(0x1234:16,@+er2.w),er1 ;015F92D11234 -+ mova/l.l @(0x1234:16,@er2-.w),er1 ;015FA2D11234 -+ mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,er2).w),er1 ;015FC2D19ABC1234 -+ mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,er2).w),er1 ;015FCAD19ABCDEF01234 -+ mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,r2L.b).w),er1 ;015FD2D19ABC1234 -+ mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,r2.w).w),er1 ;015FE2D19ABC1234 -+ mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,er2.l).w),er1 ;015FF2D19ABC1234 -+ mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,r2L.b).w),er1 ;015FDAD19ABCDEF01234 -+ mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,r2.w).w),er1 ;015FEAD19ABCDEF01234 -+ mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,er2.l).w),er1 ;015FFAD19ABCDEF01234 -+ mova/l.l @(0x1234:16,@0xFFFF9ABC:16.w),er1 ;015F40D19ABC1234 -+ mova/l.l @(0x1234:16,@0x9ABCDEF0:32.w),er1 ;015F48D19ABCDEF01234 -+ -+ mova/b.l @(0x12345678:32,@er2.b),er1 ;017F028912345678 -+ mova/b.l @(0x12345678:32,@(0x1:2,er2).b),er1 ;017F128912345678 -+ mova/b.l @(0x12345678:32,@er2+.b),er1 ;017F828912345678 -+ mova/b.l @(0x12345678:32,@-er2.b),er1 ;017FB28912345678 -+ mova/b.l @(0x12345678:32,@+er2.b),er1 ;017F928912345678 -+ mova/b.l @(0x12345678:32,@er2-.b),er1 ;017FA28912345678 -+ mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,er2).b),er1 ;017FC2899ABC12345678 -+ mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,er2).b),er1 ;017FCA899ABCDEF012345678 -+ mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,r2L.b).b),er1 ;017FD2899ABC12345678 -+ mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,r2.w).b),er1 ;017FE2899ABC12345678 -+ mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,er2.l).b),er1 ;017FF2899ABC12345678 -+ mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,r2L.b).b),er1 ;017FDA899ABCDEF012345678 -+ mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,r2.w).b),er1 ;017FEA899ABCDEF012345678 -+ mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,er2.l).b),er1 ;017FFA899ABCDEF012345678 -+ mova/b.l @(0x12345678:32,@0xFFFF9ABC:16.b),er1 ;017F40899ABC12345678 -+ mova/b.l @(0x12345678:32,@0x9ABCDEF0:32.b),er1 ;017F48899ABCDEF012345678 -+ -+ mova/b.l @(0x12345678:32,@er2.w),er1 ;015F029912345678 -+ mova/b.l @(0x12345678:32,@(0x2:2,er2).w),er1 ;015F129912345678 -+ mova/b.l @(0x12345678:32,@er2+.w),er1 ;015F829912345678 -+ mova/b.l @(0x12345678:32,@-er2.w),er1 ;015FB29912345678 -+ mova/b.l @(0x12345678:32,@+er2.w),er1 ;015F929912345678 -+ mova/b.l @(0x12345678:32,@er2-.w),er1 ;015FA29912345678 -+ mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,er2).w),er1 ;015FC2999ABC12345678 -+ mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,er2).w),er1 ;015FCA999ABCDEF012345678 -+ mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,r2L.b).w),er1 ;015FD2999ABC12345678 -+ mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,r2.w).w),er1 ;015FE2999ABC12345678 -+ mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,er2.l).w),er1 ;015FF2999ABC12345678 -+ mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,r2L.b).w),er1 ;015FDA999ABCDEF012345678 -+ mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,r2.w).w),er1 ;015FEA999ABCDEF012345678 -+ mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,er2.l).w),er1 ;015FFA999ABCDEF012345678 -+ mova/b.l @(0x12345678:32,@0xFFFF9ABC:16.w),er1 ;015F40999ABC12345678 -+ mova/b.l @(0x12345678:32,@0x9ABCDEF0:32.w),er1 ;015F48999ABCDEF012345678 -+ -+ mova/w.l @(0x12345678:32,@er2.b),er1 ;017F02A912345678 -+ mova/w.l @(0x12345678:32,@(0x1:2,er2).b),er1 ;017F12A912345678 -+ mova/w.l @(0x12345678:32,@er2+.b),er1 ;017F82A912345678 -+ mova/w.l @(0x12345678:32,@-er2.b),er1 ;017FB2A912345678 -+ mova/w.l @(0x12345678:32,@+er2.b),er1 ;017F92A912345678 -+ mova/w.l @(0x12345678:32,@er2-.b),er1 ;017FA2A912345678 -+ mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,er2).b),er1 ;017FC2A99ABC12345678 -+ mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,er2).b),er1 ;017FCAA99ABCDEF012345678 -+ mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,r2L.b).b),er1 ;017FD2A99ABC12345678 -+ mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,r2.w).b),er1 ;017FE2A99ABC12345678 -+ mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,er2.l).b),er1 ;017FF2A99ABC12345678 -+ mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,r2L.b).b),er1 ;017FDAA99ABCDEF012345678 -+ mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,r2.w).b),er1 ;017FEAA99ABCDEF012345678 -+ mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,er2.l).b),er1 ;017FFAA99ABCDEF012345678 -+ mova/w.l @(0x12345678:32,@0xFFFF9ABC:16.b),er1 ;017F40A99ABC12345678 -+ mova/w.l @(0x12345678:32,@0x9ABCDEF0:32.b),er1 ;017F48A99ABCDEF012345678 -+ -+ mova/w.l @(0x12345678:32,@er2.w),er1 ;015F02B912345678 -+ mova/w.l @(0x12345678:32,@(0x2:2,er2).w),er1 ;015F12B912345678 -+ mova/w.l @(0x12345678:32,@er2+.w),er1 ;015F82B912345678 -+ mova/w.l @(0x12345678:32,@-er2.w),er1 ;015FB2B912345678 -+ mova/w.l @(0x12345678:32,@+er2.w),er1 ;015F92B912345678 -+ mova/w.l @(0x12345678:32,@er2-.w),er1 ;015FA2B912345678 -+ mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,er2).w),er1 ;015FC2B99ABC12345678 -+ mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,er2).w),er1 ;015FCAB99ABCDEF012345678 -+ mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,r2L.b).w),er1 ;015FD2B99ABC12345678 -+ mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,r2.w).w),er1 ;015FE2B99ABC12345678 -+ mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,er2.l).w),er1 ;015FF2B99ABC12345678 -+ mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,r2L.b).w),er1 ;015FDAB99ABCDEF012345678 -+ mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,r2.w).w),er1 ;015FEAB99ABCDEF012345678 -+ mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,er2.l).w),er1 ;015FFAB99ABCDEF012345678 -+ mova/w.l @(0x12345678:32,@0xFFFF9ABC:16.w),er1 ;015F40B99ABC12345678 -+ mova/w.l @(0x12345678:32,@0x9ABCDEF0:32.w),er1 ;015F48B99ABCDEF012345678 -+ -+ mova/l.l @(0x12345678:32,@er2.b),er1 ;017F02C912345678 -+ mova/l.l @(0x12345678:32,@(0x1:2,er2).b),er1 ;017F12C912345678 -+ mova/l.l @(0x12345678:32,@er2+.b),er1 ;017F82C912345678 -+ mova/l.l @(0x12345678:32,@-er2.b),er1 ;017FB2C912345678 -+ mova/l.l @(0x12345678:32,@+er2.b),er1 ;017F92C912345678 -+ mova/l.l @(0x12345678:32,@er2-.b),er1 ;017FA2C912345678 -+ mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,er2).b),er1 ;017FC2C99ABC12345678 -+ mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,er2).b),er1 ;017FCAC99ABCDEF012345678 -+ mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,r2L.b).b),er1 ;017FD2C99ABC12345678 -+ mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,r2.w).b),er1 ;017FE2C99ABC12345678 -+ mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,er2.l).b),er1 ;017FF2C99ABC12345678 -+ mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,r2L.b).b),er1 ;017FDAC99ABCDEF012345678 -+ mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,r2.w).b),er1 ;017FEAC99ABCDEF012345678 -+ mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,er2.l).b),er1 ;017FFAC99ABCDEF012345678 -+ mova/l.l @(0x12345678:32,@0xFFFF9ABC:16.b),er1 ;017F40C99ABC12345678 -+ mova/l.l @(0x12345678:32,@0x9ABCDEF0:32.b),er1 ;017F48C99ABCDEF012345678 -+ -+ mova/l.l @(0x12345678:32,@er2.w),er1 ;015F02D912345678 -+ mova/l.l @(0x12345678:32,@(0x2:2,er2).w),er1 ;015F12D912345678 -+ mova/l.l @(0x12345678:32,@er2+.w),er1 ;015F82D912345678 -+ mova/l.l @(0x12345678:32,@-er2.w),er1 ;015FB2D912345678 -+ mova/l.l @(0x12345678:32,@+er2.w),er1 ;015F92D912345678 -+ mova/l.l @(0x12345678:32,@er2-.w),er1 ;015FA2D912345678 -+ mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,er2).w),er1 ;015FC2D99ABC12345678 -+ mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,er2).w),er1 ;015FCAD99ABCDEF012345678 -+ mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,r2L.b).w),er1 ;015FD2D99ABC12345678 -+ mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,r2.w).w),er1 ;015FE2D99ABC12345678 -+ mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,er2.l).w),er1 ;015FF2D99ABC12345678 -+ mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,r2L.b).w),er1 ;015FDAD99ABCDEF012345678 -+ mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,r2.w).w),er1 ;015FEAD99ABCDEF012345678 -+ mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,er2.l).w),er1 ;015FFAD99ABCDEF012345678 -+ mova/l.l @(0x12345678:32,@0xFFFF9ABC:16.w),er1 ;015F40D99ABC12345678 -+ mova/l.l @(0x12345678:32,@0x9ABCDEF0:32.w),er1 ;015F48D99ABCDEF012345678 -+ -+ .end ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;mova ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ .h8300sx ++ .text ++_start: ++ mova/b.c @(0x1234:16,r3l.b),er1 ;7A891234 ++ mova/b.c @(0x1234:16,r3.w),er1 ;7A991234 ++ mova/w.c @(0x1234:16,r3l.b),er1 ;7AA91234 ++ mova/w.c @(0x1234:16,r3.w),er1 ;7AB91234 ++ mova/l.c @(0x1234:16,r3l.b),er1 ;7AC91234 ++ mova/l.c @(0x1234:16,r3.w),er1 ;7AD91234 ++ mova/b.c @(0x12345678:32,r3l.b),er1 ;7A8112345678 ++ mova/b.c @(0x12345678:32,r3.w),er1 ;7A9112345678 ++ mova/w.c @(0x12345678:32,r3l.b),er1 ;7AA112345678 ++ mova/w.c @(0x12345678:32,r3.w),er1 ;7AB112345678 ++ mova/l.c @(0x12345678:32,r3l.b),er1 ;7AC112345678 ++ mova/l.c @(0x12345678:32,r3.w),er1 ;7AD112345678 ++ ++ mova/b.l @(0x1234:16,r3l.b),er1 ;78B87A891234 ++ mova/b.l @(0x1234:16,r3.w),er1 ;78397A991234 ++ mova/w.l @(0x1234:16,r3l.b),er1 ;78B87AA91234 ++ mova/w.l @(0x1234:16,r3.w),er1 ;78397AB91234 ++ mova/l.l @(0x1234:16,r3l.b),er1 ;78B87AC91234 ++ mova/l.l @(0x1234:16,r3.w),er1 ;78397AD91234 ++ mova/b.l @(0x12345678:32,r3l.b),er1 ;78B87A8112345678 ++ mova/b.l @(0x12345678:32,r3.w),er1 ;78397A9112345678 ++ mova/w.l @(0x12345678:32,r3l.b),er1 ;78B87AA112345678 ++ mova/w.l @(0x12345678:32,r3.w),er1 ;78397AB112345678 ++ mova/l.l @(0x12345678:32,r3l.b),er1 ;78B87AC112345678 ++ mova/l.l @(0x12345678:32,r3.w),er1 ;78397AD112345678 ++ ++ mova/b.l @(0x1234:16,@er2.b),er1 ;017F02811234 ++ mova/b.l @(0x1234:16,@(0x1:2,er2).b),er1 ;017F12811234 ++ mova/b.l @(0x1234:16,@er2+.b),er1 ;017F82811234 ++ mova/b.l @(0x1234:16,@-er2.b),er1 ;017FB2811234 ++ mova/b.l @(0x1234:16,@+er2.b),er1 ;017F92811234 ++ mova/b.l @(0x1234:16,@er2-.b),er1 ;017FA2811234 ++ mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,er2).b),er1 ;017FC2819ABC1234 ++ mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,er2).b),er1 ;017FCA819ABCDEF01234 ++ mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,r2L.b).b),er1 ;017FD2819ABC1234 ++ mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,r2.w).b),er1 ;017FE2819ABC1234 ++ mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,er2.l).b),er1 ;017FF2819ABC1234 ++ mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,r2L.b).b),er1 ;017FDA819ABCDEF01234 ++ mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,r2.w).b),er1 ;017FEA819ABCDEF01234 ++ mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,er2.l).b),er1 ;017FFA819ABCDEF01234 ++ mova/b.l @(0x1234:16,@0xFFFF9ABC:16.b),er1 ;017F40819ABC1234 ++ mova/b.l @(0x1234:16,@0x9ABCDEF0:32.b),er1 ;017F48819ABCDEF01234 ++ ++ mova/b.l @(0x1234:16,@er2.w),er1 ;015F02911234 ++ mova/b.l @(0x1234:16,@(0x2:2,er2).w),er1 ;015F12911234 ++ mova/b.l @(0x1234:16,@er2+.w),er1 ;015F82911234 ++ mova/b.l @(0x1234:16,@-er2.w),er1 ;015FB2911234 ++ mova/b.l @(0x1234:16,@+er2.w),er1 ;015F92911234 ++ mova/b.l @(0x1234:16,@er2-.w),er1 ;015FA2911234 ++ mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,er2).w),er1 ;015FC2919ABC1234 ++ mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,er2).w),er1 ;015FCA919ABCDEF01234 ++ mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,r2L.b).w),er1 ;015FD2919ABC1234 ++ mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,r2.w).w),er1 ;015FE2919ABC1234 ++ mova/b.l @(0x1234:16,@(0xFFFF9ABC:16,er2.l).w),er1 ;015FF2919ABC1234 ++ mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,r2L.b).w),er1 ;015FDA919ABCDEF01234 ++ mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,r2.w).w),er1 ;015FEA919ABCDEF01234 ++ mova/b.l @(0x1234:16,@(0x9ABCDEF0:32,er2.l).w),er1 ;015FFA919ABCDEF01234 ++ mova/b.l @(0x1234:16,@0xFFFF9ABC:16.w),er1 ;015F40919ABC1234 ++ mova/b.l @(0x1234:16,@0x9ABCDEF0:32.w),er1 ;015F48919ABCDEF01234 ++ ++ mova/w.l @(0x1234:16,@er2.b),er1 ;017F02A11234 ++ mova/w.l @(0x1234:16,@(0x1:2,er2).b),er1 ;017F12A11234 ++ mova/w.l @(0x1234:16,@er2+.b),er1 ;017F82A11234 ++ mova/w.l @(0x1234:16,@-er2.b),er1 ;017FB2A11234 ++ mova/w.l @(0x1234:16,@+er2.b),er1 ;017F92A11234 ++ mova/w.l @(0x1234:16,@er2-.b),er1 ;017FA2A11234 ++ mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,er2).b),er1 ;017FC2A19ABC1234 ++ mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,er2).b),er1 ;017FCAA19ABCDEF01234 ++ mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,r2L.b).b),er1 ;017FD2A19ABC1234 ++ mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,r2.w).b),er1 ;017FE2A19ABC1234 ++ mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,er2.l).b),er1 ;017FF2A19ABC1234 ++ mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,r2L.b).b),er1 ;017FDAA19ABCDEF01234 ++ mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,r2.w).b),er1 ;017FEAA19ABCDEF01234 ++ mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,er2.l).b),er1 ;017FFAA19ABCDEF01234 ++ mova/w.l @(0x1234:16,@0xFFFF9ABC:16.b),er1 ;017F40A19ABC1234 ++ mova/w.l @(0x1234:16,@0x9ABCDEF0:32.b),er1 ;017F48A19ABCDEF01234 ++ ++ mova/w.l @(0x1234:16,@er2.w),er1 ;015F02B11234 ++ mova/w.l @(0x1234:16,@(0x2:2,er2).w),er1 ;015F12B11234 ++ mova/w.l @(0x1234:16,@er2+.w),er1 ;015F82B11234 ++ mova/w.l @(0x1234:16,@-er2.w),er1 ;015FB2B11234 ++ mova/w.l @(0x1234:16,@+er2.w),er1 ;015F92B11234 ++ mova/w.l @(0x1234:16,@er2-.w),er1 ;015FA2B11234 ++ mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,er2).w),er1 ;015FC2B19ABC1234 ++ mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,er2).w),er1 ;015FCAB19ABCDEF01234 ++ mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,r2L.b).w),er1 ;015FD2B19ABC1234 ++ mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,r2.w).w),er1 ;015FE2B19ABC1234 ++ mova/w.l @(0x1234:16,@(0xFFFF9ABC:16,er2.l).w),er1 ;015FF2B19ABC1234 ++ mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,r2L.b).w),er1 ;015FDAB19ABCDEF01234 ++ mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,r2.w).w),er1 ;015FEAB19ABCDEF01234 ++ mova/w.l @(0x1234:16,@(0x9ABCDEF0:32,er2.l).w),er1 ;015FFAB19ABCDEF01234 ++ mova/w.l @(0x1234:16,@0xFFFF9ABC:16.w),er1 ;015F40B19ABC1234 ++ mova/w.l @(0x1234:16,@0x9ABCDEF0:32.w),er1 ;015F48B19ABCDEF01234 ++ ++ mova/l.l @(0x1234:16,@er2.b),er1 ;017F02C11234 ++ mova/l.l @(0x1234:16,@(0x1:2,er2).b),er1 ;017F12C11234 ++ mova/l.l @(0x1234:16,@er2+.b),er1 ;017F82C11234 ++ mova/l.l @(0x1234:16,@-er2.b),er1 ;017FB2C11234 ++ mova/l.l @(0x1234:16,@+er2.b),er1 ;017F92C11234 ++ mova/l.l @(0x1234:16,@er2-.b),er1 ;017FA2C11234 ++ mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,er2).b),er1 ;017FC2C19ABC1234 ++ mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,er2).b),er1 ;017FCAC19ABCDEF01234 ++ mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,r2L.b).b),er1 ;017FD2C19ABC1234 ++ mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,r2.w).b),er1 ;017FE2C19ABC1234 ++ mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,er2.l).b),er1 ;017FF2C19ABC1234 ++ mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,r2L.b).b),er1 ;017FDAC19ABCDEF01234 ++ mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,r2.w).b),er1 ;017FEAC19ABCDEF01234 ++ mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,er2.l).b),er1 ;017FFAC19ABCDEF01234 ++ mova/l.l @(0x1234:16,@0xFFFF9ABC:16.b),er1 ;017F40C19ABC1234 ++ mova/l.l @(0x1234:16,@0x9ABCDEF0:32.b),er1 ;017F48C19ABCDEF01234 ++ ++ mova/l.l @(0x1234:16,@er2.w),er1 ;015F02D11234 ++ mova/l.l @(0x1234:16,@(0x2:2,er2).w),er1 ;015F12D11234 ++ mova/l.l @(0x1234:16,@er2+.w),er1 ;015F82D11234 ++ mova/l.l @(0x1234:16,@-er2.w),er1 ;015FB2D11234 ++ mova/l.l @(0x1234:16,@+er2.w),er1 ;015F92D11234 ++ mova/l.l @(0x1234:16,@er2-.w),er1 ;015FA2D11234 ++ mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,er2).w),er1 ;015FC2D19ABC1234 ++ mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,er2).w),er1 ;015FCAD19ABCDEF01234 ++ mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,r2L.b).w),er1 ;015FD2D19ABC1234 ++ mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,r2.w).w),er1 ;015FE2D19ABC1234 ++ mova/l.l @(0x1234:16,@(0xFFFF9ABC:16,er2.l).w),er1 ;015FF2D19ABC1234 ++ mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,r2L.b).w),er1 ;015FDAD19ABCDEF01234 ++ mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,r2.w).w),er1 ;015FEAD19ABCDEF01234 ++ mova/l.l @(0x1234:16,@(0x9ABCDEF0:32,er2.l).w),er1 ;015FFAD19ABCDEF01234 ++ mova/l.l @(0x1234:16,@0xFFFF9ABC:16.w),er1 ;015F40D19ABC1234 ++ mova/l.l @(0x1234:16,@0x9ABCDEF0:32.w),er1 ;015F48D19ABCDEF01234 ++ ++ mova/b.l @(0x12345678:32,@er2.b),er1 ;017F028912345678 ++ mova/b.l @(0x12345678:32,@(0x1:2,er2).b),er1 ;017F128912345678 ++ mova/b.l @(0x12345678:32,@er2+.b),er1 ;017F828912345678 ++ mova/b.l @(0x12345678:32,@-er2.b),er1 ;017FB28912345678 ++ mova/b.l @(0x12345678:32,@+er2.b),er1 ;017F928912345678 ++ mova/b.l @(0x12345678:32,@er2-.b),er1 ;017FA28912345678 ++ mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,er2).b),er1 ;017FC2899ABC12345678 ++ mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,er2).b),er1 ;017FCA899ABCDEF012345678 ++ mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,r2L.b).b),er1 ;017FD2899ABC12345678 ++ mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,r2.w).b),er1 ;017FE2899ABC12345678 ++ mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,er2.l).b),er1 ;017FF2899ABC12345678 ++ mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,r2L.b).b),er1 ;017FDA899ABCDEF012345678 ++ mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,r2.w).b),er1 ;017FEA899ABCDEF012345678 ++ mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,er2.l).b),er1 ;017FFA899ABCDEF012345678 ++ mova/b.l @(0x12345678:32,@0xFFFF9ABC:16.b),er1 ;017F40899ABC12345678 ++ mova/b.l @(0x12345678:32,@0x9ABCDEF0:32.b),er1 ;017F48899ABCDEF012345678 ++ ++ mova/b.l @(0x12345678:32,@er2.w),er1 ;015F029912345678 ++ mova/b.l @(0x12345678:32,@(0x2:2,er2).w),er1 ;015F129912345678 ++ mova/b.l @(0x12345678:32,@er2+.w),er1 ;015F829912345678 ++ mova/b.l @(0x12345678:32,@-er2.w),er1 ;015FB29912345678 ++ mova/b.l @(0x12345678:32,@+er2.w),er1 ;015F929912345678 ++ mova/b.l @(0x12345678:32,@er2-.w),er1 ;015FA29912345678 ++ mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,er2).w),er1 ;015FC2999ABC12345678 ++ mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,er2).w),er1 ;015FCA999ABCDEF012345678 ++ mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,r2L.b).w),er1 ;015FD2999ABC12345678 ++ mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,r2.w).w),er1 ;015FE2999ABC12345678 ++ mova/b.l @(0x12345678:32,@(0xFFFF9ABC:16,er2.l).w),er1 ;015FF2999ABC12345678 ++ mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,r2L.b).w),er1 ;015FDA999ABCDEF012345678 ++ mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,r2.w).w),er1 ;015FEA999ABCDEF012345678 ++ mova/b.l @(0x12345678:32,@(0x9ABCDEF0:32,er2.l).w),er1 ;015FFA999ABCDEF012345678 ++ mova/b.l @(0x12345678:32,@0xFFFF9ABC:16.w),er1 ;015F40999ABC12345678 ++ mova/b.l @(0x12345678:32,@0x9ABCDEF0:32.w),er1 ;015F48999ABCDEF012345678 ++ ++ mova/w.l @(0x12345678:32,@er2.b),er1 ;017F02A912345678 ++ mova/w.l @(0x12345678:32,@(0x1:2,er2).b),er1 ;017F12A912345678 ++ mova/w.l @(0x12345678:32,@er2+.b),er1 ;017F82A912345678 ++ mova/w.l @(0x12345678:32,@-er2.b),er1 ;017FB2A912345678 ++ mova/w.l @(0x12345678:32,@+er2.b),er1 ;017F92A912345678 ++ mova/w.l @(0x12345678:32,@er2-.b),er1 ;017FA2A912345678 ++ mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,er2).b),er1 ;017FC2A99ABC12345678 ++ mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,er2).b),er1 ;017FCAA99ABCDEF012345678 ++ mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,r2L.b).b),er1 ;017FD2A99ABC12345678 ++ mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,r2.w).b),er1 ;017FE2A99ABC12345678 ++ mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,er2.l).b),er1 ;017FF2A99ABC12345678 ++ mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,r2L.b).b),er1 ;017FDAA99ABCDEF012345678 ++ mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,r2.w).b),er1 ;017FEAA99ABCDEF012345678 ++ mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,er2.l).b),er1 ;017FFAA99ABCDEF012345678 ++ mova/w.l @(0x12345678:32,@0xFFFF9ABC:16.b),er1 ;017F40A99ABC12345678 ++ mova/w.l @(0x12345678:32,@0x9ABCDEF0:32.b),er1 ;017F48A99ABCDEF012345678 ++ ++ mova/w.l @(0x12345678:32,@er2.w),er1 ;015F02B912345678 ++ mova/w.l @(0x12345678:32,@(0x2:2,er2).w),er1 ;015F12B912345678 ++ mova/w.l @(0x12345678:32,@er2+.w),er1 ;015F82B912345678 ++ mova/w.l @(0x12345678:32,@-er2.w),er1 ;015FB2B912345678 ++ mova/w.l @(0x12345678:32,@+er2.w),er1 ;015F92B912345678 ++ mova/w.l @(0x12345678:32,@er2-.w),er1 ;015FA2B912345678 ++ mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,er2).w),er1 ;015FC2B99ABC12345678 ++ mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,er2).w),er1 ;015FCAB99ABCDEF012345678 ++ mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,r2L.b).w),er1 ;015FD2B99ABC12345678 ++ mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,r2.w).w),er1 ;015FE2B99ABC12345678 ++ mova/w.l @(0x12345678:32,@(0xFFFF9ABC:16,er2.l).w),er1 ;015FF2B99ABC12345678 ++ mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,r2L.b).w),er1 ;015FDAB99ABCDEF012345678 ++ mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,r2.w).w),er1 ;015FEAB99ABCDEF012345678 ++ mova/w.l @(0x12345678:32,@(0x9ABCDEF0:32,er2.l).w),er1 ;015FFAB99ABCDEF012345678 ++ mova/w.l @(0x12345678:32,@0xFFFF9ABC:16.w),er1 ;015F40B99ABC12345678 ++ mova/w.l @(0x12345678:32,@0x9ABCDEF0:32.w),er1 ;015F48B99ABCDEF012345678 ++ ++ mova/l.l @(0x12345678:32,@er2.b),er1 ;017F02C912345678 ++ mova/l.l @(0x12345678:32,@(0x1:2,er2).b),er1 ;017F12C912345678 ++ mova/l.l @(0x12345678:32,@er2+.b),er1 ;017F82C912345678 ++ mova/l.l @(0x12345678:32,@-er2.b),er1 ;017FB2C912345678 ++ mova/l.l @(0x12345678:32,@+er2.b),er1 ;017F92C912345678 ++ mova/l.l @(0x12345678:32,@er2-.b),er1 ;017FA2C912345678 ++ mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,er2).b),er1 ;017FC2C99ABC12345678 ++ mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,er2).b),er1 ;017FCAC99ABCDEF012345678 ++ mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,r2L.b).b),er1 ;017FD2C99ABC12345678 ++ mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,r2.w).b),er1 ;017FE2C99ABC12345678 ++ mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,er2.l).b),er1 ;017FF2C99ABC12345678 ++ mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,r2L.b).b),er1 ;017FDAC99ABCDEF012345678 ++ mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,r2.w).b),er1 ;017FEAC99ABCDEF012345678 ++ mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,er2.l).b),er1 ;017FFAC99ABCDEF012345678 ++ mova/l.l @(0x12345678:32,@0xFFFF9ABC:16.b),er1 ;017F40C99ABC12345678 ++ mova/l.l @(0x12345678:32,@0x9ABCDEF0:32.b),er1 ;017F48C99ABCDEF012345678 ++ ++ mova/l.l @(0x12345678:32,@er2.w),er1 ;015F02D912345678 ++ mova/l.l @(0x12345678:32,@(0x2:2,er2).w),er1 ;015F12D912345678 ++ mova/l.l @(0x12345678:32,@er2+.w),er1 ;015F82D912345678 ++ mova/l.l @(0x12345678:32,@-er2.w),er1 ;015FB2D912345678 ++ mova/l.l @(0x12345678:32,@+er2.w),er1 ;015F92D912345678 ++ mova/l.l @(0x12345678:32,@er2-.w),er1 ;015FA2D912345678 ++ mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,er2).w),er1 ;015FC2D99ABC12345678 ++ mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,er2).w),er1 ;015FCAD99ABCDEF012345678 ++ mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,r2L.b).w),er1 ;015FD2D99ABC12345678 ++ mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,r2.w).w),er1 ;015FE2D99ABC12345678 ++ mova/l.l @(0x12345678:32,@(0xFFFF9ABC:16,er2.l).w),er1 ;015FF2D99ABC12345678 ++ mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,r2L.b).w),er1 ;015FDAD99ABCDEF012345678 ++ mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,r2.w).w),er1 ;015FEAD99ABCDEF012345678 ++ mova/l.l @(0x12345678:32,@(0x9ABCDEF0:32,er2.l).w),er1 ;015FFAD99ABCDEF012345678 ++ mova/l.l @(0x12345678:32,@0xFFFF9ABC:16.w),er1 ;015F40D99ABC12345678 ++ mova/l.l @(0x12345678:32,@0x9ABCDEF0:32.w),er1 ;015F48D99ABCDEF012345678 ++ ++ .end diff --git a/gas/testsuite/gas/h8300/t03_add.exp b/gas/testsuite/gas/h8300/t03_add.exp new file mode 100644 -index 0000000..44d3579 +index 0000000..1b84cef --- /dev/null +++ b/gas/testsuite/gas/h8300/t03_add.exp -@@ -0,0 +1,3038 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,3037 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1158616,995 +1165795,994 @@ index 0000000..44d3579 + diff --git a/gas/testsuite/gas/h8300/t03_add.s b/gas/testsuite/gas/h8300/t03_add.s new file mode 100644 -index 0000000..c698dbc +index 0000000..80d433a --- /dev/null +++ b/gas/testsuite/gas/h8300/t03_add.s @@ -0,0 +1,977 @@ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+;arith_1 -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ .h8300sx -+ .text -+_start: -+ add.b #0x12:8,r1h ;8112 -+ add.b #0x12:8,@er1 ;7d108012 -+ add.b #0x12:8,@(0x3:2,er1) ;017768188012 -+ add.b #0x12:8,@er1+ ;01746c188012 -+ add.b #0x12:8,@-er1 ;01776c188012 -+ add.b #0x12:8,@+er1 ;01756c188012 -+ add.b #0x12:8,@er1- ;01766c188012 -+ add.b #0x12:8,@(0x1234:16,er1) ;01746e1812348012 -+ add.b #0x12:8,@(0x12345678:32,er1) ;78146a28123456788012 -+ add.b #0x12:8,@(0x1234:16,r2l.b) ;01756e2812348012 -+ add.b #0x12:8,@(0x1234:16,r2.w) ;01766e2812348012 -+ add.b #0x12:8,@(0x1234:16,er2.l) ;01776e2812348012 -+ add.b #0x12:8,@(0x12345678:32,r2l.b) ;78256a28123456788012 -+ add.b #0x12:8,@(0x12345678:32,r2.w) ;78266a28123456788012 -+ add.b #0x12:8,@(0x12345678:32,er2.l) ;78276a28123456788012 -+ add.b #0x12:8,@0xffffff9a:8 ;7f9a8012 -+ add.b #0x12:8,@0x1234:16 ;6a1812348012 -+ add.b #0x12:8,@0x12345678:32 ;6a38123456788012 -+ -+ add.b r3h,r1h ;0831 -+ -+ add.b r3h,@er1 ;7d100830 -+ add.b r3h,@(0x3:2,er1) ;01793113 -+ add.b r3h,@er1+ ;01798113 -+ add.b r3h,@-er1 ;0179b113 -+ add.b r3h,@+er1 ;01799113 -+ add.b r3h,@er1- ;0179a113 -+ add.b r3h,@(0x1234:16,er1) ;0179c1131234 -+ add.b r3h,@(0x12345678:32,er1) ;0179c91312345678 -+ add.b r3h,@(0x1234:16,r2l.b) ;0179d2131234 -+ add.b r3h,@(0x1234:16,r2.w) ;0179e2131234 -+ add.b r3h,@(0x1234:16,er2.l) ;0179f2131234 -+ add.b r3h,@(0x12345678:32,r2l.b) ;0179da1312345678 -+ add.b r3h,@(0x12345678:32,r2.w) ;0179ea1312345678 -+ add.b r3h,@(0x12345678:32,er2.l) ;0179fa1312345678 -+ add.b r3h,@0xffffff12:8 ;7f120830 -+ add.b r3h,@0x1234:16 ;6a1812340830 -+ add.b r3h,@0x12345678:32 ;6a38123456780830 -+ -+ add.b @er3,r1h ;7c300801 -+ add.b @(0x3:2,er3),r1h ;017a3311 -+ add.b @er3+,r1h ;017a8311 -+ add.b @-er3,r1h ;017ab311 -+ add.b @+er3,r1h ;017a9311 -+ add.b @er3-,r1h ;017aa311 -+ add.b @(0x1234:16,er1),r1h ;017ac1111234 -+ add.b @(0x12345678:32,er1),r1h ;017ac91112345678 -+ add.b @(0x1234:16,r2l.b),r1h ;017ad2111234 -+ add.b @(0x1234:16,r2.w),r1h ;017ae2111234 -+ add.b @(0x1234:16,er2.l),r1h ;017af2111234 -+ add.b @(0x12345678:32,r2l.b),r1h ;017ada1112345678 -+ add.b @(0x12345678:32,r2.w),r1h ;017aea1112345678 -+ add.b @(0x12345678:32,er2.l),r1h ;017afa1112345678 -+ add.b @0xffffff12:8,r1h ;7e120801 -+ add.b @0x1234:16,r1h ;6a1012340801 -+ add.b @0x12345678:32,r1h ;6a30123456780801 -+ -+ add.b @er3,@er1 ;7c350110 -+ add.b @er3,@(3:2,er1) ;7c353110 -+ add.b @er3,@-er1 ;7c35b110 -+ add.b @er3,@er1+ ;7c358110 -+ add.b @er3,@er1- ;7c35a110 -+ add.b @er3,@+er1 ;7c359110 -+ add.b @er3,@(0xffff9abc:16,er1) ;7c35c1109abc -+ add.b @er3,@(0x9abcdef0:32,er1) ;7c35c9109abcdef0 -+ add.b @er3,@(0xffff9abc:16,r2l.b) ;7c35d2109abc -+ add.b @er3,@(0xffff9abc:16,r2.w) ;7c35e2109abc -+ add.b @er3,@(0xffff9abc:16,er2.l) ;7c35f2109abc -+ add.b @er3,@(0x9abcdef0:32,r2l.b) ;7c35da109abcdef0 -+ add.b @er3,@(0x9abcdef0:32,r2.w) ;7c35ea109abcdef0 -+ add.b @er3,@(0x9abcdef0:32,er2.l) ;7c35fa109abcdef0 -+ add.b @er3,@0xffff9abc:16 ;7c3540109abc -+ add.b @er3,@0x9abcdef0:32 ;7c3548109abcdef0 -+ -+ add.b @-er3,@er1 ;01776c3c0110 -+ add.b @-er3,@(3:2,er1) ;01776c3c3110 -+ add.b @-er3,@-er1 ;01776c3cb110 -+ add.b @-er3,@er1+ ;01776c3c8110 -+ add.b @-er3,@er1- ;01776c3ca110 -+ add.b @-er3,@+er1 ;01776c3c9110 -+ add.b @-er3,@(0xffff9abc:16,er1) ;01776c3cc1109abc -+ add.b @-er3,@(0x9abcdef0:32,er1) ;01776c3cc9109abcdef0 -+ add.b @-er3,@(0xffff9abc:16,r2l.b) ;01776c3cd2109abc -+ add.b @-er3,@(0xffff9abc:16,r2.w) ;01776c3ce2109abc -+ add.b @-er3,@(0xffff9abc:16,er2.l) ;01776c3cf2109abc -+ add.b @-er3,@(0x9abcdef0:32,r2l.b) ;01776c3cda109abcdef0 -+ add.b @-er3,@(0x9abcdef0:32,r2.w) ;01776c3cea109abcdef0 -+ add.b @-er3,@(0x9abcdef0:32,er2.l) ;01776c3cfa109abcdef0 -+ add.b @-er3,@0xffff9abc:16 ;01776c3c40109abc -+ add.b @-er3,@0x9abcdef0:32 ;01776c3c48109abcdef0 -+ -+ add.b @er3+,@er1 ;01746c3c0110 -+ add.b @er3+,@(3:2,er1) ;01746c3c3110 -+ add.b @er3+,@-er1 ;01746c3cb110 -+ add.b @er3+,@er1+ ;01746c3c8110 -+ add.b @er3+,@er1- ;01746c3ca110 -+ add.b @er3+,@+er1 ;01746c3c9110 -+ add.b @er3+,@(0xffff9abc:16,er1) ;01746c3cc1109abc -+ add.b @er3+,@(0x9abcdef0:32,er1) ;01746c3cc9109abcdef0 -+ add.b @er3+,@(0xffff9abc:16,r2l.b) ;01746c3cd2109abc -+ add.b @er3+,@(0xffff9abc:16,r2.w) ;01746c3ce2109abc -+ add.b @er3+,@(0xffff9abc:16,er2.l) ;01746c3cf2109abc -+ add.b @er3+,@(0x9abcdef0:32,r2l.b) ;01746c3cda109abcdef0 -+ add.b @er3+,@(0x9abcdef0:32,r2.w) ;01746c3cea109abcdef0 -+ add.b @er3+,@(0x9abcdef0:32,er2.l) ;01746c3cfa109abcdef0 -+ add.b @er3+,@0xffff9abc:16 ;01746c3c40109abc -+ add.b @er3+,@0x9abcdef0:32 ;01746c3c48109abcdef0 -+ -+ add.b @er3-,@er1 ;01766c3c0110 -+ add.b @er3-,@(3:2,er1) ;01766c3c3110 -+ add.b @er3-,@-er1 ;01766c3cb110 -+ add.b @er3-,@er1+ ;01766c3c8110 -+ add.b @er3-,@er1- ;01766c3ca110 -+ add.b @er3-,@+er1 ;01766c3c9110 -+ add.b @er3-,@(0xffff9abc:16,er1) ;01766c3cc1109abc -+ add.b @er3-,@(0x9abcdef0:32,er1) ;01766c3cc9109abcdef0 -+ add.b @er3-,@(0xffff9abc:16,r2l.b) ;01766c3cd2109abc -+ add.b @er3-,@(0xffff9abc:16,r2.w) ;01766c3ce2109abc -+ add.b @er3-,@(0xffff9abc:16,er2.l) ;01766c3cf2109abc -+ add.b @er3-,@(0x9abcdef0:32,r2l.b) ;01766c3cda109abcdef0 -+ add.b @er3-,@(0x9abcdef0:32,r2.w) ;01766c3cea109abcdef0 -+ add.b @er3-,@(0x9abcdef0:32,er2.l) ;01766c3cfa109abcdef0 -+ add.b @er3-,@0xffff9abc:16 ;01766c3c40109abc -+ add.b @er3-,@0x9abcdef0:32 ;01766c3c48109abcdef0 -+ -+ add.b @+er3,@er1 ;01756c3c0110 -+ add.b @+er3,@(3:2,er1) ;01756c3c3110 -+ add.b @+er3,@-er1 ;01756c3cb110 -+ add.b @+er3,@er1+ ;01756c3c8110 -+ add.b @+er3,@er1- ;01756c3ca110 -+ add.b @+er3,@+er1 ;01756c3c9110 -+ add.b @+er3,@(0xffff9abc:16,er1) ;01756c3cc1109abc -+ add.b @+er3,@(0x9abcdef0:32,er1) ;01756c3cc9109abcdef0 -+ add.b @+er3,@(0xffff9abc:16,r2l.b) ;01756c3cd2109abc -+ add.b @+er3,@(0xffff9abc:16,r2.w) ;01756c3ce2109abc -+ add.b @+er3,@(0xffff9abc:16,er2.l) ;01756c3cf2109abc -+ add.b @+er3,@(0x9abcdef0:32,r2l.b) ;01756c3cda109abcdef0 -+ add.b @+er3,@(0x9abcdef0:32,r2.w) ;01756c3cea109abcdef0 -+ add.b @+er3,@(0x9abcdef0:32,er2.l) ;01756c3cfa109abcdef0 -+ add.b @+er3,@0xffff9abc:16 ;01756c3c40109abc -+ add.b @+er3,@0x9abcdef0:32 ;01756c3c48109abcdef0 -+ -+ add.b @(0x1234:16,er3),@er1 ;01746e3c12340110 -+ add.b @(0x1234:16,er3),@(3:2,er1) ;01746e3c12343110 -+ add.b @(0x1234:16,er3),@-er1 ;01746e3c1234b110 -+ add.b @(0x1234:16,er3),@er1+ ;01746e3c12348110 -+ add.b @(0x1234:16,er3),@er1- ;01746e3c1234a110 -+ add.b @(0x1234:16,er3),@+er1 ;01746e3c12349110 -+ add.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01746e3c1234c1109abc -+ add.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01746e3c1234c9109abcdef0 -+ add.b @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01746e3c1234d2109abc -+ add.b @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01746e3c1234e2109abc -+ add.b @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01746e3c1234f2109abc -+ add.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01746e3c1234da109abcdef0 -+ add.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01746e3c1234ea109abcdef0 -+ add.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01746e3c1234fa109abcdef0 -+ add.b @(0x1234:16,er3),@0xffff9abc:16 ;01746e3c123440109abc -+ add.b @(0x1234:16,er3),@0x9abcdef0:32 ;01746e3c123448109abcdef0 -+ -+ add.b @(0x12345678:32,er3),@er1 ;78346a2c123456780110 -+ add.b @(0x12345678:32,er3),@(3:2,er1) ;78346a2c123456783110 -+ add.b @(0x12345678:32,er3),@-er1 ;78346a2c12345678b110 -+ add.b @(0x12345678:32,er3),@er1+ ;78346a2c123456788110 -+ add.b @(0x12345678:32,er3),@er1- ;78346a2c12345678a110 -+ add.b @(0x12345678:32,er3),@+er1 ;78346a2c123456789110 -+ add.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346a2c12345678c1109abc -+ add.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346a2c12345678c9109abcdef0 -+ add.b @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346a2c12345678d2109abc -+ add.b @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346a2c12345678e2109abc -+ add.b @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346a2c12345678f2109abc -+ add.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346a2c12345678da109abcdef0 -+ add.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346a2c12345678ea109abcdef0 -+ add.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346a2c12345678fa109abcdef0 -+ add.b @(0x12345678:32,er3),@0xffff9abc:16 ;78346a2c1234567840109abc -+ add.b @(0x12345678:32,er3),@0x9abcdef0:32 ;78346a2c1234567848109abcdef0 -+ -+ add.b @(0x1234:16,r3l.b),@er1 ;01756e3c12340110 -+ add.b @(0x1234:16,r3l.b),@(3:2,er1) ;01756e3c12343110 -+ add.b @(0x1234:16,r3l.b),@-er1 ;01756e3c1234b110 -+ add.b @(0x1234:16,r3l.b),@er1+ ;01756e3c12348110 -+ add.b @(0x1234:16,r3l.b),@er1- ;01756e3c1234a110 -+ add.b @(0x1234:16,r3l.b),@+er1 ;01756e3c12349110 -+ add.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01756e3c1234c1109abc -+ add.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01756e3c1234c9109abcdef0 -+ add.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01756e3c1234d2109abc -+ add.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01756e3c1234e2109abc -+ add.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01756e3c1234f2109abc -+ add.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01756e3c1234da109abcdef0 -+ add.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01756e3c1234ea109abcdef0 -+ add.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01756e3c1234fa109abcdef0 -+ add.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;01756e3c123440109abc -+ add.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01756e3c123448109abcdef0 -+ -+ add.b @(0x1234:16,r3.w),@er1 ;01766e3c12340110 -+ add.b @(0x1234:16,r3.w),@(3:2,er1) ;01766e3c12343110 -+ add.b @(0x1234:16,r3.w),@-er1 ;01766e3c1234b110 -+ add.b @(0x1234:16,r3.w),@er1+ ;01766e3c12348110 -+ add.b @(0x1234:16,r3.w),@er1- ;01766e3c1234a110 -+ add.b @(0x1234:16,r3.w),@+er1 ;01766e3c12349110 -+ add.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01766e3c1234c1109abc -+ add.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01766e3c1234c9109abcdef0 -+ add.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01766e3c1234d2109abc -+ add.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01766e3c1234e2109abc -+ add.b @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01766e3c1234f2109abc -+ add.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01766e3c1234da109abcdef0 -+ add.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01766e3c1234ea109abcdef0 -+ add.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01766e3c1234fa109abcdef0 -+ add.b @(0x1234:16,r3.w),@0xffff9abc:16 ;01766e3c123440109abc -+ add.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;01766e3c123448109abcdef0 -+ -+ add.b @(0x1234:16,er3.l),@er1 ;01776e3c12340110 -+ add.b @(0x1234:16,er3.l),@(3:2,er1) ;01776e3c12343110 -+ add.b @(0x1234:16,er3.l),@-er1 ;01776e3c1234b110 -+ add.b @(0x1234:16,er3.l),@er1+ ;01776e3c12348110 -+ add.b @(0x1234:16,er3.l),@er1- ;01776e3c1234a110 -+ add.b @(0x1234:16,er3.l),@+er1 ;01776e3c12349110 -+ add.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01776e3c1234c1109abc -+ add.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01776e3c1234c9109abcdef0 -+ add.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01776e3c1234d2109abc -+ add.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01776e3c1234e2109abc -+ add.b @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01776e3c1234f2109abc -+ add.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01776e3c1234da109abcdef0 -+ add.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01776e3c1234ea109abcdef0 -+ add.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01776e3c1234fa109abcdef0 -+ add.b @(0x1234:16,er3.l),@0xffff9abc:16 ;01776e3c123440109abc -+ add.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;01776e3c123448109abcdef0 -+ -+ add.b @(0x12345678:32,r3l.b),@er1 ;78356a2c123456780110 -+ add.b @(0x12345678:32,r3l.b),@(3:2,er1) ;78356a2c123456783110 -+ add.b @(0x12345678:32,r3l.b),@-er1 ;78356a2c12345678b110 -+ add.b @(0x12345678:32,r3l.b),@er1+ ;78356a2c123456788110 -+ add.b @(0x12345678:32,r3l.b),@er1- ;78356a2c12345678a110 -+ add.b @(0x12345678:32,r3l.b),@+er1 ;78356a2c123456789110 -+ add.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356a2c12345678c1109abc -+ add.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356a2c12345678c9109abcdef0 -+ add.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356a2c12345678d2109abc -+ add.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356a2c12345678e2109abc -+ add.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356a2c12345678f2109abc -+ add.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356a2c12345678da109abcdef0 -+ add.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356a2c12345678ea109abcdef0 -+ add.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356a2c12345678fa109abcdef0 -+ add.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356a2c1234567840109abc -+ add.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356a2c1234567848109abcdef0 -+ -+ add.b @(0x12345678:32,r3.w),@er1 ;78366a2c123456780110 -+ add.b @(0x12345678:32,r3.w),@(3:2,er1) ;78366a2c123456783110 -+ add.b @(0x12345678:32,r3.w),@-er1 ;78366a2c12345678b110 -+ add.b @(0x12345678:32,r3.w),@er1+ ;78366a2c123456788110 -+ add.b @(0x12345678:32,r3.w),@er1- ;78366a2c12345678a110 -+ add.b @(0x12345678:32,r3.w),@+er1 ;78366a2c123456789110 -+ add.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366a2c12345678c1109abc -+ add.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366a2c12345678c9109abcdef0 -+ add.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366a2c12345678d2109abc -+ add.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366a2c12345678e2109abc -+ add.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366a2c12345678f2109abc -+ add.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366a2c12345678da109abcdef0 -+ add.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366a2c12345678ea109abcdef0 -+ add.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366a2c12345678fa109abcdef0 -+ add.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366a2c1234567840109abc -+ add.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366a2c1234567848109abcdef0 -+ -+ add.b @(0x12345678:32,er3.l),@er1 ;78376a2c123456780110 -+ add.b @(0x12345678:32,er3.l),@(3:2,er1) ;78376a2c123456783110 -+ add.b @(0x12345678:32,er3.l),@-er1 ;78376a2c12345678b110 -+ add.b @(0x12345678:32,er3.l),@er1+ ;78376a2c123456788110 -+ add.b @(0x12345678:32,er3.l),@er1- ;78376a2c12345678a110 -+ add.b @(0x12345678:32,er3.l),@+er1 ;78376a2c123456789110 -+ add.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376a2c12345678c1109abc -+ add.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376a2c12345678c9109abcdef0 -+ add.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376a2c12345678d2109abc -+ add.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376a2c12345678e2109abc -+ add.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376a2c12345678f2109abc -+ add.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376a2c12345678da109abcdef0 -+ add.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376a2c12345678ea109abcdef0 -+ add.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376a2c12345678fa109abcdef0 -+ add.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376a2c1234567840109abc -+ add.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376a2c1234567848109abcdef0 -+ -+ add.b @0x1234:16,@er1 ;6a1512340110 -+ add.b @0x1234:16,@(3:2,er1) ;6a1512343110 -+ add.b @0x1234:16,@-er1 ;6a151234b110 -+ add.b @0x1234:16,@er1+ ;6a1512348110 -+ add.b @0x1234:16,@er1- ;6a151234a110 -+ add.b @0x1234:16,@+er1 ;6a1512349110 -+ add.b @0x1234:16,@(0xffff9abc:16,er1) ;6a151234c1109abc -+ add.b @0x1234:16,@(0x9abcdef0:32,er1) ;6a151234c9109abcdef0 -+ add.b @0x1234:16,@(0xffff9abc:16,r2l.b) ;6a151234d2109abc -+ add.b @0x1234:16,@(0xffff9abc:16,r2.w) ;6a151234e2109abc -+ add.b @0x1234:16,@(0xffff9abc:16,er2.l) ;6a151234f2109abc -+ add.b @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6a151234da109abcdef0 -+ add.b @0x1234:16,@(0x9abcdef0:32,r2.w) ;6a151234ea109abcdef0 -+ add.b @0x1234:16,@(0x9abcdef0:32,er2.l) ;6a151234fa109abcdef0 -+ add.b @0x1234:16,@0xffff9abc:16 ;6a15123440109abc -+ add.b @0x1234:16,@0x9abcdef0:32 ;6a15123448109abcdef0 -+ -+ add.b @0x12345678:32,@er1 ;6a35123456780110 -+ add.b @0x12345678:32,@(3:2,er1) ;6a35123456783110 -+ add.b @0x12345678:32,@-er1 ;6a3512345678b110 -+ add.b @0x12345678:32,@er1+ ;6a35123456788110 -+ add.b @0x12345678:32,@er1- ;6a3512345678a110 -+ add.b @0x12345678:32,@+er1 ;6a35123456789110 -+ add.b @0x12345678:32,@(0xffff9abc:16,er1) ;6a3512345678c1109abc -+ add.b @0x12345678:32,@(0x9abcdef0:32,er1) ;6a3512345678c9109abcdef0 -+ add.b @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6a3512345678d2109abc -+ add.b @0x12345678:32,@(0xffff9abc:16,r2.w) ;6a3512345678e2109abc -+ add.b @0x12345678:32,@(0xffff9abc:16,er2.l) ;6a3512345678f2109abc -+ add.b @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6a3512345678da109abcdef0 -+ add.b @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6a3512345678ea109abcdef0 -+ add.b @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6a3512345678fa109abcdef0 -+ add.b @0x12345678:32,@0xffff9abc:16 ;6a351234567840109abc -+ add.b @0x12345678:32,@0x9abcdef0:32 ;6a351234567848109abcdef0 -+ -+ add.w #0x1234:16,r1 ;79111234 -+ add.w #0x7:3,r2 ;0a72 -+ add.w #0x1234:16,@er1 ;015e01101234 -+ add.w #0x1234:16,@(0x6:2,er1) ;015e31101234 -+ add.w #0x1234:16,@er1+ ;015e81101234 -+ add.w #0x1234:16,@-er1 ;015eb1101234 -+ add.w #0x1234:16,@+er1 ;015e91101234 -+ add.w #0x1234:16,@er1- ;015ea1101234 -+ add.w #0x1234:16,@(0xffff9abc:16,er1) ;015ec1109abc1234 -+ add.w #0x1234:16,@(0x9abcdef0:32,er1) ;015ec9109abcdef01234 -+ add.w #0x1234:16,@(0xffff9abc:16,r2l.b) ;015ed2109abc1234 -+ add.w #0x1234:16,@(0xffff9abc:16,r2.w) ;015ee2109abc1234 -+ add.w #0x1234:16,@(0xffff9abc:16,er2.l) ;015ef2109abc1234 -+ add.w #0x1234:16,@(0x9abcdef0:32,r2l.b) ;015eda109abcdef01234 -+ add.w #0x1234:16,@(0x9abcdef0:32,r2.w) ;015eea109abcdef01234 -+ add.w #0x1234:16,@(0x9abcdef0:32,er2.l) ;015efa109abcdef01234 -+ add.w #0x1234:16,@0xffff9abc:16 ;015e40109abc1234 -+ add.w #0x1234:16,@0x9abcdef0:32 ;015e48109abcdef01234 -+ -+ add.w #0x7:3,@er1 ;7d900a70 -+ add.w #0x7:3,@0x1234:16 ;6b1812340a70 -+ add.w #0x7:3,@0x12345678:32 ;6b38123456780a70 -+ -+ add.w r3,r1 ;0931 -+ -+ add.w r3,@er1 ;7d900930 -+ add.w r3,@(0x6:2,er1) ;01593113 -+ add.w r3,@er1+ ;01598113 -+ add.w r3,@-er1 ;0159b113 -+ add.w r3,@+er1 ;01599113 -+ add.w r3,@er1- ;0159a113 -+ add.w r3,@(0x1234:16,er1) ;0159c1131234 -+ add.w r3,@(0x12345678:32,er1) ;0159c91312345678 -+ add.w r3,@(0x1234:16,r2l.b) ;0159d2131234 -+ add.w r3,@(0x1234:16,r2.w) ;0159e2131234 -+ add.w r3,@(0x1234:16,er2.l) ;0159f2131234 -+ add.w r3,@(0x12345678:32,r2l.b) ;0159da1312345678 -+ add.w r3,@(0x12345678:32,r2.w) ;0159ea1312345678 -+ add.w r3,@(0x12345678:32,er2.l) ;0159fa1312345678 -+ add.w r3,@0x1234:16 ;6b1812340930 -+ add.w r3,@0x12345678:32 ;6b38123456780930 -+ -+ add.w @er3,r1 ;7cb00901 -+ add.w @(0x6:2,er1),r1 ;015a3111 -+ add.w @er3+,r1 ;015a8311 -+ add.w @-er3,r1 ;015ab311 -+ add.w @+er3,r1 ;015a9311 -+ add.w @er3-,r1 ;015aa311 -+ add.w @(0x1234:16,er1),r1 ;015ac1111234 -+ add.w @(0x12345678:32,er1),r1 ;015ac91112345678 -+ add.w @(0x1234:16,r2l.b),r1 ;015ad2111234 -+ add.w @(0x1234:16,r2.w),r1 ;015ae2111234 -+ add.w @(0x1234:16,er2.l),r1 ;015af2111234 -+ add.w @(0x12345678:32,r2l.b),r1 ;015ada1112345678 -+ add.w @(0x12345678:32,r2.w),r1 ;015aea1112345678 -+ add.w @(0x12345678:32,er2.l),r1 ;015afa1112345678 -+ add.w @0x1234:16,r1 ;6b1012340901 -+ add.w @0x12345678:32,r1 ;6b30123456780901 -+ -+ add.w @er3,@er1 ;7cb50110 -+ add.w @er3,@(6:2,er1) ;7cb53110 -+ add.w @er3,@-er1 ;7cb5b110 -+ add.w @er3,@er1+ ;7cb58110 -+ add.w @er3,@er1- ;7cb5a110 -+ add.w @er3,@+er1 ;7cb59110 -+ add.w @er3,@(0xffff9abc:16,er1) ;7cb5c1109abc -+ add.w @er3,@(0x9abcdef0:32,er1) ;7cb5c9109abcdef0 -+ add.w @er3,@(0xffff9abc:16,r2l.b) ;7cb5d2109abc -+ add.w @er3,@(0xffff9abc:16,r2.w) ;7cb5e2109abc -+ add.w @er3,@(0xffff9abc:16,er2.l) ;7cb5f2109abc -+ add.w @er3,@(0x9abcdef0:32,r2l.b) ;7cb5da109abcdef0 -+ add.w @er3,@(0x9abcdef0:32,r2.w) ;7cb5ea109abcdef0 -+ add.w @er3,@(0x9abcdef0:32,er2.l) ;7cb5fa109abcdef0 -+ add.w @er3,@0xffff9abc:16 ;7cb540109abc -+ add.w @er3,@0x9abcdef0:32 ;7cb548109abcdef0 -+ -+ add.w @-er3,@er1 ;01576d3c0110 -+ add.w @-er3,@(6:2,er1) ;01576d3c3110 -+ add.w @-er3,@-er1 ;01576d3cb110 -+ add.w @-er3,@er1+ ;01576d3c8110 -+ add.w @-er3,@er1- ;01576d3ca110 -+ add.w @-er3,@+er1 ;01576d3c9110 -+ add.w @-er3,@(0xffff9abc:16,er1) ;01576d3cc1109abc -+ add.w @-er3,@(0x9abcdef0:32,er1) ;01576d3cc9109abcdef0 -+ add.w @-er3,@(0xffff9abc:16,r2l.b) ;01576d3cd2109abc -+ add.w @-er3,@(0xffff9abc:16,r2.w) ;01576d3ce2109abc -+ add.w @-er3,@(0xffff9abc:16,er2.l) ;01576d3cf2109abc -+ add.w @-er3,@(0x9abcdef0:32,r2l.b) ;01576d3cda109abcdef0 -+ add.w @-er3,@(0x9abcdef0:32,r2.w) ;01576d3cea109abcdef0 -+ add.w @-er3,@(0x9abcdef0:32,er2.l) ;01576d3cfa109abcdef0 -+ add.w @-er3,@0xffff9abc:16 ;01576d3c40109abc -+ add.w @-er3,@0x9abcdef0:32 ;01576d3c48109abcdef0 -+ -+ add.w @er3+,@er1 ;01546d3c0110 -+ add.w @er3+,@(6:2,er1) ;01546d3c3110 -+ add.w @er3+,@-er1 ;01546d3cb110 -+ add.w @er3+,@er1+ ;01546d3c8110 -+ add.w @er3+,@er1- ;01546d3ca110 -+ add.w @er3+,@+er1 ;01546d3c9110 -+ add.w @er3+,@(0xffff9abc:16,er1) ;01546d3cc1109abc -+ add.w @er3+,@(0x9abcdef0:32,er1) ;01546d3cc9109abcdef0 -+ add.w @er3+,@(0xffff9abc:16,r2l.b) ;01546d3cd2109abc -+ add.w @er3+,@(0xffff9abc:16,r2.w) ;01546d3ce2109abc -+ add.w @er3+,@(0xffff9abc:16,er2.l) ;01546d3cf2109abc -+ add.w @er3+,@(0x9abcdef0:32,r2l.b) ;01546d3cda109abcdef0 -+ add.w @er3+,@(0x9abcdef0:32,r2.w) ;01546d3cea109abcdef0 -+ add.w @er3+,@(0x9abcdef0:32,er2.l) ;01546d3cfa109abcdef0 -+ add.w @er3+,@0xffff9abc:16 ;01546d3c40109abc -+ add.w @er3+,@0x9abcdef0:32 ;01546d3c48109abcdef0 -+ -+ add.w @er3-,@er1 ;01566d3c0110 -+ add.w @er3-,@(6:2,er1) ;01566d3c3110 -+ add.w @er3-,@-er1 ;01566d3cb110 -+ add.w @er3-,@er1+ ;01566d3c8110 -+ add.w @er3-,@er1- ;01566d3ca110 -+ add.w @er3-,@+er1 ;01566d3c9110 -+ add.w @er3-,@(0xffff9abc:16,er1) ;01566d3cc1109abc -+ add.w @er3-,@(0x9abcdef0:32,er1) ;01566d3cc9109abcdef0 -+ add.w @er3-,@(0xffff9abc:16,r2l.b) ;01566d3cd2109abc -+ add.w @er3-,@(0xffff9abc:16,r2.w) ;01566d3ce2109abc -+ add.w @er3-,@(0xffff9abc:16,er2.l) ;01566d3cf2109abc -+ add.w @er3-,@(0x9abcdef0:32,r2l.b) ;01566d3cda109abcdef0 -+ add.w @er3-,@(0x9abcdef0:32,r2.w) ;01566d3cea109abcdef0 -+ add.w @er3-,@(0x9abcdef0:32,er2.l) ;01566d3cfa109abcdef0 -+ add.w @er3-,@0xffff9abc:16 ;01566d3c40109abc -+ add.w @er3-,@0x9abcdef0:32 ;01566d3c48109abcdef0 -+ -+ add.w @+er3,@er1 ;01556d3c0110 -+ add.w @+er3,@(6:2,er1) ;01556d3c3110 -+ add.w @+er3,@-er1 ;01556d3cb110 -+ add.w @+er3,@er1+ ;01556d3c8110 -+ add.w @+er3,@er1- ;01556d3ca110 -+ add.w @+er3,@+er1 ;01556d3c9110 -+ add.w @+er3,@(0xffff9abc:16,er1) ;01556d3cc1109abc -+ add.w @+er3,@(0x9abcdef0:32,er1) ;01556d3cc9109abcdef0 -+ add.w @+er3,@(0xffff9abc:16,r2l.b) ;01556d3cd2109abc -+ add.w @+er3,@(0xffff9abc:16,r2.w) ;01556d3ce2109abc -+ add.w @+er3,@(0xffff9abc:16,er2.l) ;01556d3cf2109abc -+ add.w @+er3,@(0x9abcdef0:32,r2l.b) ;01556d3cda109abcdef0 -+ add.w @+er3,@(0x9abcdef0:32,r2.w) ;01556d3cea109abcdef0 -+ add.w @+er3,@(0x9abcdef0:32,er2.l) ;01556d3cfa109abcdef0 -+ add.w @+er3,@0xffff9abc:16 ;01556d3c40109abc -+ add.w @+er3,@0x9abcdef0:32 ;01556d3c48109abcdef0 -+ -+ add.w @(0x1234:16,er3),@er1 ;01546f3c12340110 -+ add.w @(0x1234:16,er3),@(6:2,er1) ;01546f3c12343110 -+ add.w @(0x1234:16,er3),@-er1 ;01546f3c1234b110 -+ add.w @(0x1234:16,er3),@er1+ ;01546f3c12348110 -+ add.w @(0x1234:16,er3),@er1- ;01546f3c1234a110 -+ add.w @(0x1234:16,er3),@+er1 ;01546f3c12349110 -+ add.w @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01546f3c1234c1109abc -+ add.w @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01546f3c1234c9109abcdef0 -+ add.w @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01546f3c1234d2109abc -+ add.w @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01546f3c1234e2109abc -+ add.w @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01546f3c1234f2109abc -+ add.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01546f3c1234da109abcdef0 -+ add.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01546f3c1234ea109abcdef0 -+ add.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01546f3c1234fa109abcdef0 -+ add.w @(0x1234:16,er3),@0xffff9abc:16 ;01546f3c123440109abc -+ add.w @(0x1234:16,er3),@0x9abcdef0:32 ;01546f3c123448109abcdef0 -+ -+ add.w @(0x12345678:32,er3),@er1 ;78346b2c123456780110 -+ add.w @(0x12345678:32,er3),@(6:2,er1) ;78346b2c123456783110 -+ add.w @(0x12345678:32,er3),@-er1 ;78346b2c12345678b110 -+ add.w @(0x12345678:32,er3),@er1+ ;78346b2c123456788110 -+ add.w @(0x12345678:32,er3),@er1- ;78346b2c12345678a110 -+ add.w @(0x12345678:32,er3),@+er1 ;78346b2c123456789110 -+ add.w @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346b2c12345678c1109abc -+ add.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346b2c12345678c9109abcdef0 -+ add.w @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346b2c12345678d2109abc -+ add.w @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346b2c12345678e2109abc -+ add.w @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346b2c12345678f2109abc -+ add.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346b2c12345678da109abcdef0 -+ add.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346b2c12345678ea109abcdef0 -+ add.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346b2c12345678fa109abcdef0 -+ add.w @(0x12345678:32,er3),@0xffff9abc:16 ;78346b2c1234567840109abc -+ add.w @(0x12345678:32,er3),@0x9abcdef0:32 ;78346b2c1234567848109abcdef0 -+ -+ add.w @(0x1234:16,r3l.b),@er1 ;01556f3c12340110 -+ add.w @(0x1234:16,r3l.b),@(6:2,er1) ;01556f3c12343110 -+ add.w @(0x1234:16,r3l.b),@-er1 ;01556f3c1234b110 -+ add.w @(0x1234:16,r3l.b),@er1+ ;01556f3c12348110 -+ add.w @(0x1234:16,r3l.b),@er1- ;01556f3c1234a110 -+ add.w @(0x1234:16,r3l.b),@+er1 ;01556f3c12349110 -+ add.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01556f3c1234c1109abc -+ add.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01556f3c1234c9109abcdef0 -+ add.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01556f3c1234d2109abc -+ add.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01556f3c1234e2109abc -+ add.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01556f3c1234f2109abc -+ add.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01556f3c1234da109abcdef0 -+ add.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01556f3c1234ea109abcdef0 -+ add.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01556f3c1234fa109abcdef0 -+ add.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;01556f3c123440109abc -+ add.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01556f3c123448109abcdef0 -+ -+ add.w @(0x1234:16,r3.w),@er1 ;01566f3c12340110 -+ add.w @(0x1234:16,r3.w),@(6:2,er1) ;01566f3c12343110 -+ add.w @(0x1234:16,r3.w),@-er1 ;01566f3c1234b110 -+ add.w @(0x1234:16,r3.w),@er1+ ;01566f3c12348110 -+ add.w @(0x1234:16,r3.w),@er1- ;01566f3c1234a110 -+ add.w @(0x1234:16,r3.w),@+er1 ;01566f3c12349110 -+ add.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01566f3c1234c1109abc -+ add.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01566f3c1234c9109abcdef0 -+ add.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01566f3c1234d2109abc -+ add.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01566f3c1234e2109abc -+ add.w @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01566f3c1234f2109abc -+ add.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01566f3c1234da109abcdef0 -+ add.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01566f3c1234ea109abcdef0 -+ add.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01566f3c1234fa109abcdef0 -+ add.w @(0x1234:16,r3.w),@0xffff9abc:16 ;01566f3c123440109abc -+ add.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;01566f3c123448109abcdef0 -+ -+ add.w @(0x1234:16,er3.l),@er1 ;01576f3c12340110 -+ add.w @(0x1234:16,er3.l),@(6:2,er1) ;01576f3c12343110 -+ add.w @(0x1234:16,er3.l),@-er1 ;01576f3c1234b110 -+ add.w @(0x1234:16,er3.l),@er1+ ;01576f3c12348110 -+ add.w @(0x1234:16,er3.l),@er1- ;01576f3c1234a110 -+ add.w @(0x1234:16,er3.l),@+er1 ;01576f3c12349110 -+ add.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01576f3c1234c1109abc -+ add.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01576f3c1234c9109abcdef0 -+ add.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01576f3c1234d2109abc -+ add.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01576f3c1234e2109abc -+ add.w @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01576f3c1234f2109abc -+ add.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01576f3c1234da109abcdef0 -+ add.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01576f3c1234ea109abcdef0 -+ add.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01576f3c1234fa109abcdef0 -+ add.w @(0x1234:16,er3.l),@0xffff9abc:16 ;01576f3c123440109abc -+ add.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;01576f3c123448109abcdef0 -+ -+ add.w @(0x12345678:32,r3l.b),@er1 ;78356b2c123456780110 -+ add.w @(0x12345678:32,r3l.b),@(6:2,er1) ;78356b2c123456783110 -+ add.w @(0x12345678:32,r3l.b),@-er1 ;78356b2c12345678b110 -+ add.w @(0x12345678:32,r3l.b),@er1+ ;78356b2c123456788110 -+ add.w @(0x12345678:32,r3l.b),@er1- ;78356b2c12345678a110 -+ add.w @(0x12345678:32,r3l.b),@+er1 ;78356b2c123456789110 -+ add.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356b2c12345678c1109abc -+ add.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356b2c12345678c9109abcdef0 -+ add.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356b2c12345678d2109abc -+ add.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356b2c12345678e2109abc -+ add.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356b2c12345678f2109abc -+ add.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356b2c12345678da109abcdef0 -+ add.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356b2c12345678ea109abcdef0 -+ add.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356b2c12345678fa109abcdef0 -+ add.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356b2c1234567840109abc -+ add.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356b2c1234567848109abcdef0 -+ -+ add.w @(0x12345678:32,r3.w),@er1 ;78366b2c123456780110 -+ add.w @(0x12345678:32,r3.w),@(6:2,er1) ;78366b2c123456783110 -+ add.w @(0x12345678:32,r3.w),@-er1 ;78366b2c12345678b110 -+ add.w @(0x12345678:32,r3.w),@er1+ ;78366b2c123456788110 -+ add.w @(0x12345678:32,r3.w),@er1- ;78366b2c12345678a110 -+ add.w @(0x12345678:32,r3.w),@+er1 ;78366b2c123456789110 -+ add.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366b2c12345678c1109abc -+ add.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366b2c12345678c9109abcdef0 -+ add.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366b2c12345678d2109abc -+ add.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366b2c12345678e2109abc -+ add.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366b2c12345678f2109abc -+ add.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366b2c12345678da109abcdef0 -+ add.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366b2c12345678ea109abcdef0 -+ add.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366b2c12345678fa109abcdef0 -+ add.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366b2c1234567840109abc -+ add.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366b2c1234567848109abcdef0 -+ -+ add.w @(0x12345678:32,er3.l),@er1 ;78376b2c123456780110 -+ add.w @(0x12345678:32,er3.l),@(6:2,er1) ;78376b2c123456783110 -+ add.w @(0x12345678:32,er3.l),@-er1 ;78376b2c12345678b110 -+ add.w @(0x12345678:32,er3.l),@er1+ ;78376b2c123456788110 -+ add.w @(0x12345678:32,er3.l),@er1- ;78376b2c12345678a110 -+ add.w @(0x12345678:32,er3.l),@+er1 ;78376b2c123456789110 -+ add.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376b2c12345678c1109abc -+ add.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376b2c12345678c9109abcdef0 -+ add.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376b2c12345678d2109abc -+ add.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376b2c12345678e2109abc -+ add.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376b2c12345678f2109abc -+ add.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376b2c12345678da109abcdef0 -+ add.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376b2c12345678ea109abcdef0 -+ add.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376b2c12345678fa109abcdef0 -+ add.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376b2c1234567840109abc -+ add.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376b2c1234567848109abcdef0 -+ -+ add.w @0x1234:16,@er1 ;6b1512340110 -+ add.w @0x1234:16,@(6:2,er1) ;6b1512343110 -+ add.w @0x1234:16,@-er1 ;6b151234b110 -+ add.w @0x1234:16,@er1+ ;6b1512348110 -+ add.w @0x1234:16,@er1- ;6b151234a110 -+ add.w @0x1234:16,@+er1 ;6b1512349110 -+ add.w @0x1234:16,@(0xffff9abc:16,er1) ;6b151234c1109abc -+ add.w @0x1234:16,@(0x9abcdef0:32,er1) ;6b151234c9109abcdef0 -+ add.w @0x1234:16,@(0xffff9abc:16,r2l.b) ;6b151234d2109abc -+ add.w @0x1234:16,@(0xffff9abc:16,r2.w) ;6b151234e2109abc -+ add.w @0x1234:16,@(0xffff9abc:16,er2.l) ;6b151234f2109abc -+ add.w @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6b151234da109abcdef0 -+ add.w @0x1234:16,@(0x9abcdef0:32,r2.w) ;6b151234ea109abcdef0 -+ add.w @0x1234:16,@(0x9abcdef0:32,er2.l) ;6b151234fa109abcdef0 -+ add.w @0x1234:16,@0xffff9abc:16 ;6b15123440109abc -+ add.w @0x1234:16,@0x9abcdef0:32 ;6b15123448109abcdef0 -+ -+ add.w @0x12345678:32,@er1 ;6b35123456780110 -+ add.w @0x12345678:32,@(6:2,er1) ;6b35123456783110 -+ add.w @0x12345678:32,@-er1 ;6b3512345678b110 -+ add.w @0x12345678:32,@er1+ ;6b35123456788110 -+ add.w @0x12345678:32,@er1- ;6b3512345678a110 -+ add.w @0x12345678:32,@+er1 ;6b35123456789110 -+ add.w @0x12345678:32,@(0xffff9abc:16,er1) ;6b3512345678c1109abc -+ add.w @0x12345678:32,@(0x9abcdef0:32,er1) ;6b3512345678c9109abcdef0 -+ add.w @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6b3512345678d2109abc -+ add.w @0x12345678:32,@(0xffff9abc:16,r2.w) ;6b3512345678e2109abc -+ add.w @0x12345678:32,@(0xffff9abc:16,er2.l) ;6b3512345678f2109abc -+ add.w @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6b3512345678da109abcdef0 -+ add.w @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6b3512345678ea109abcdef0 -+ add.w @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6b3512345678fa109abcdef0 -+ add.w @0x12345678:32,@0xffff9abc:16 ;6b351234567840109abc -+ add.w @0x12345678:32,@0x9abcdef0:32 ;6b351234567848109abcdef0 -+ -+ add.l #0x12345678:32,er1 ;7a1112345678 -+ add.l #0x1234:16,er1 ;7a191234 -+ add.l #0x7:3,er2 ;0afa -+ add.l #0x12345678:32,@er1 ;010e011812345678 -+ add.l #0x12345678:32,@(0xc:2,er1) ;010e311812345678 -+ add.l #0x12345678:32,@er1+ ;010e811812345678 -+ add.l #0x12345678:32,@-er1 ;010eb11812345678 -+ add.l #0x12345678:32,@+er1 ;010e911812345678 -+ add.l #0x12345678:32,@er1- ;010ea11812345678 -+ add.l #0x12345678:32,@(0xffff9abc:16,er1) ;010ec1189abc12345678 -+ add.l #0x12345678:32,@(0x9abcdef0:32,er1) ;010ec9189abcdef012345678 -+ add.l #0x12345678:32,@(0xffff9abc:16,r2l.b) ;010ed2189abc12345678 -+ add.l #0x12345678:32,@(0xffff9abc:16,r2.w) ;010ee2189abc12345678 -+ add.l #0x12345678:32,@(0xffff9abc:16,er2.l) ;010ef2189abc12345678 -+ add.l #0x12345678:32,@(0x9abcdef0:32,r2l.b) ;010eda189abcdef012345678 -+ add.l #0x12345678:32,@(0x9abcdef0:32,r2.w) ;010eea189abcdef012345678 -+ add.l #0x12345678:32,@(0x9abcdef0:32,er2.l) ;010efa189abcdef012345678 -+ add.l #0x12345678:32,@0xffff9abc:16 ;010e40189abc12345678 -+ add.l #0x12345678:32,@0x9abcdef0:32 ;010e48189abcdef012345678 -+ add.l #0x1234:16,@er1 ;010e01101234 -+ add.l #0x1234:16,@(0xc:2,er1) ;010e31101234 -+ add.l #0x1234:16,@er1+ ;010e81101234 -+ add.l #0x1234:16,@-er1 ;010eb1101234 -+ add.l #0x1234:16,@+er1 ;010e91101234 -+ add.l #0x1234:16,@er1- ;010ea1101234 -+ add.l #0x1234:16,@(0xffff9abc:16,er1) ;010ec1109abc1234 -+ add.l #0x1234:16,@(0x9abcdef0:32,er1) ;010ec9109abcdef01234 -+ add.l #0x1234:16,@(0xffff9abc:16,r2l.b) ;010ed2109abc1234 -+ add.l #0x1234:16,@(0xffff9abc:16,r2.w) ;010ee2109abc1234 -+ add.l #0x1234:16,@(0xffff9abc:16,er2.l) ;010ef2109abc1234 -+ add.l #0x1234:16,@(0x9abcdef0:32,r2l.b) ;010eda109abcdef01234 -+ add.l #0x1234:16,@(0x9abcdef0:32,r2.w) ;010eea109abcdef01234 -+ add.l #0x1234:16,@(0x9abcdef0:32,er2.l) ;010efa109abcdef01234 -+ add.l #0x1234:16,@0xffff9abc:16 ;010e40109abc1234 -+ add.l #0x1234:16,@0x9abcdef0:32 ;010e48109abcdef01234 -+ -+ add.l er3,er1 ;0ab1 -+ -+ add.l er3,@er1 ;01090113 -+ add.l er3,@(0xc:2,er1) ;01093113 -+ add.l er3,@er1+ ;01098113 -+ add.l er3,@-er1 ;0109b113 -+ add.l er3,@+er1 ;01099113 -+ add.l er3,@er1- ;0109a113 -+ add.l er3,@(0x1234:16,er1) ;0109c1131234 -+ add.l er3,@(0x12345678:32,er1) ;0109c91312345678 -+ add.l er3,@(0x1234:16,r2l.b) ;0109d2131234 -+ add.l er3,@(0x1234:16,r2.w) ;0109e2131234 -+ add.l er3,@(0x1234:16,er2.l) ;0109f2131234 -+ add.l er3,@(0x12345678:32,r2l.b) ;0109da1312345678 -+ add.l er3,@(0x12345678:32,r2.w) ;0109ea1312345678 -+ add.l er3,@(0x12345678:32,er2.l) ;0109fa1312345678 -+ add.l er3,@0x1234:16 ;010940131234 -+ add.l er3,@0x12345678:32 ;0109481312345678 -+ -+ add.l @er3,er1 ;010a0311 -+ add.l @(0xc:2,er3),er1 ;010a3311 -+ add.l @er3+,er1 ;010a8311 -+ add.l @-er3,er1 ;010ab311 -+ add.l @+er3,er1 ;010a9311 -+ add.l @er3-,er1 ;010aa311 -+ add.l @(0x1234:16,er1),er1 ;010ac1111234 -+ add.l @(0x12345678:32,er1),er1 ;010ac91112345678 -+ add.l @(0x1234:16,r2l.b),er1 ;010ad2111234 -+ add.l @(0x1234:16,r2.w),er1 ;010ae2111234 -+ add.l @(0x1234:16,er2.l),er1 ;010af2111234 -+ add.l @(0x12345678:32,r2l.b),er1 ;010ada1112345678 -+ add.l @(0x12345678:32,r2.w),er1 ;010aea1112345678 -+ add.l @(0x12345678:32,er2.l),er1 ;010afa1112345678 -+ add.l @0x1234:16,er1 ;010a40111234 -+ add.l @0x12345678:32,er1 ;010a481112345678 -+ -+ add.l @er3,@er1 ;0104693c0110 -+ add.l @er3,@(0xc:2,er1) ;0104693c3110 -+ add.l @er3,@-er1 ;0104693cb110 -+ add.l @er3,@er1+ ;0104693c8110 -+ add.l @er3,@er1- ;0104693ca110 -+ add.l @er3,@+er1 ;0104693c9110 -+ add.l @er3,@(0xffff9abc:16,er1) ;0104693cc1109abc -+ add.l @er3,@(0x9abcdef0:32,er1) ;0104693cc9109abcdef0 -+ add.l @er3,@(0xffff9abc:16,r2l.b) ;0104693cd2109abc -+ add.l @er3,@(0xffff9abc:16,r2.w) ;0104693ce2109abc -+ add.l @er3,@(0xffff9abc:16,er2.l) ;0104693cf2109abc -+ add.l @er3,@(0x9abcdef0:32,r2l.b) ;0104693cda109abcdef0 -+ add.l @er3,@(0x9abcdef0:32,r2.w) ;0104693cea109abcdef0 -+ add.l @er3,@(0x9abcdef0:32,er2.l) ;0104693cfa109abcdef0 -+ add.l @er3,@0xffff9abc:16 ;0104693c40109abc -+ add.l @er3,@0x9abcdef0:32 ;0104693c48109abcdef0 -+ -+ add.l @(0xc:2,er3),@er1 ;0107693c0110 -+ add.l @(0xc:2,er3),@(0xc:2,er1) ;0107693c3110 -+ add.l @(0xc:2,er3),@-er1 ;0107693cb110 -+ add.l @(0xc:2,er3),@er1+ ;0107693c8110 -+ add.l @(0xc:2,er3),@er1- ;0107693ca110 -+ add.l @(0xc:2,er3),@+er1 ;0107693c9110 -+ add.l @(0xc:2,er3),@(0xffff9abc:16,er1) ;0107693cc1109abc -+ add.l @(0xc:2,er3),@(0x9abcdef0:32,er1) ;0107693cc9109abcdef0 -+ add.l @(0xc:2,er3),@(0xffff9abc:16,r2l.b) ;0107693cd2109abc -+ add.l @(0xc:2,er3),@(0xffff9abc:16,r2.w) ;0107693ce2109abc -+ add.l @(0xc:2,er3),@(0xffff9abc:16,er2.l) ;0107693cf2109abc -+ add.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b) ;0107693cda109abcdef0 -+ add.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w) ;0107693cea109abcdef0 -+ add.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l) ;0107693cfa109abcdef0 -+ add.l @(0xc:2,er3),@0xffff9abc:16 ;0107693c40109abc -+ add.l @(0xc:2,er3),@0x9abcdef0:32 ;0107693c48109abcdef0 -+ -+ add.l @-er3,@er1 ;01076d3c0110 -+ add.l @-er3,@(0xc:2,er1) ;01076d3c3110 -+ add.l @-er3,@-er1 ;01076d3cb110 -+ add.l @-er3,@er1+ ;01076d3c8110 -+ add.l @-er3,@er1- ;01076d3ca110 -+ add.l @-er3,@+er1 ;01076d3c9110 -+ add.l @-er3,@(0xffff9abc:16,er1) ;01076d3cc1109abc -+ add.l @-er3,@(0x9abcdef0:32,er1) ;01076d3cc9109abcdef0 -+ add.l @-er3,@(0xffff9abc:16,r2l.b) ;01076d3cd2109abc -+ add.l @-er3,@(0xffff9abc:16,r2.w) ;01076d3ce2109abc -+ add.l @-er3,@(0xffff9abc:16,er2.l) ;01076d3cf2109abc -+ add.l @-er3,@(0x9abcdef0:32,r2l.b) ;01076d3cda109abcdef0 -+ add.l @-er3,@(0x9abcdef0:32,r2.w) ;01076d3cea109abcdef0 -+ add.l @-er3,@(0x9abcdef0:32,er2.l) ;01076d3cfa109abcdef0 -+ add.l @-er3,@0xffff9abc:16 ;01076d3c40109abc -+ add.l @-er3,@0x9abcdef0:32 ;01076d3c48109abcdef0 -+ -+ add.l @er3+,@er1 ;01046d3c0110 -+ add.l @er3+,@(0xc:2,er1) ;01046d3c3110 -+ add.l @er3+,@-er1 ;01046d3cb110 -+ add.l @er3+,@er1+ ;01046d3c8110 -+ add.l @er3+,@er1- ;01046d3ca110 -+ add.l @er3+,@+er1 ;01046d3c9110 -+ add.l @er3+,@(0xffff9abc:16,er1) ;01046d3cc1109abc -+ add.l @er3+,@(0x9abcdef0:32,er1) ;01046d3cc9109abcdef0 -+ add.l @er3+,@(0xffff9abc:16,r2l.b) ;01046d3cd2109abc -+ add.l @er3+,@(0xffff9abc:16,r2.w) ;01046d3ce2109abc -+ add.l @er3+,@(0xffff9abc:16,er2.l) ;01046d3cf2109abc -+ add.l @er3+,@(0x9abcdef0:32,r2l.b) ;01046d3cda109abcdef0 -+ add.l @er3+,@(0x9abcdef0:32,r2.w) ;01046d3cea109abcdef0 -+ add.l @er3+,@(0x9abcdef0:32,er2.l) ;01046d3cfa109abcdef0 -+ add.l @er3+,@0xffff9abc:16 ;01046d3c40109abc -+ add.l @er3+,@0x9abcdef0:32 ;01046d3c48109abcdef0 -+ -+ add.l @er3-,@er1 ;01066d3c0110 -+ add.l @er3-,@(0xc:2,er1) ;01066d3c3110 -+ add.l @er3-,@-er1 ;01066d3cb110 -+ add.l @er3-,@er1+ ;01066d3c8110 -+ add.l @er3-,@er1- ;01066d3ca110 -+ add.l @er3-,@+er1 ;01066d3c9110 -+ add.l @er3-,@(0xffff9abc:16,er1) ;01066d3cc1109abc -+ add.l @er3-,@(0x9abcdef0:32,er1) ;01066d3cc9109abcdef0 -+ add.l @er3-,@(0xffff9abc:16,r2l.b) ;01066d3cd2109abc -+ add.l @er3-,@(0xffff9abc:16,r2.w) ;01066d3ce2109abc -+ add.l @er3-,@(0xffff9abc:16,er2.l) ;01066d3cf2109abc -+ add.l @er3-,@(0x9abcdef0:32,r2l.b) ;01066d3cda109abcdef0 -+ add.l @er3-,@(0x9abcdef0:32,r2.w) ;01066d3cea109abcdef0 -+ add.l @er3-,@(0x9abcdef0:32,er2.l) ;01066d3cfa109abcdef0 -+ add.l @er3-,@0xffff9abc:16 ;01066d3c40109abc -+ add.l @er3-,@0x9abcdef0:32 ;01066d3c48109abcdef0 -+ -+ add.l @+er3,@er1 ;01056d3c0110 -+ add.l @+er3,@(0xc:2,er1) ;01056d3c3110 -+ add.l @+er3,@-er1 ;01056d3cb110 -+ add.l @+er3,@er1+ ;01056d3c8110 -+ add.l @+er3,@er1- ;01056d3ca110 -+ add.l @+er3,@+er1 ;01056d3c9110 -+ add.l @+er3,@(0xffff9abc:16,er1) ;01056d3cc1109abc -+ add.l @+er3,@(0x9abcdef0:32,er1) ;01056d3cc9109abcdef0 -+ add.l @+er3,@(0xffff9abc:16,r2l.b) ;01056d3cd2109abc -+ add.l @+er3,@(0xffff9abc:16,r2.w) ;01056d3ce2109abc -+ add.l @+er3,@(0xffff9abc:16,er2.l) ;01056d3cf2109abc -+ add.l @+er3,@(0x9abcdef0:32,r2l.b) ;01056d3cda109abcdef0 -+ add.l @+er3,@(0x9abcdef0:32,r2.w) ;01056d3cea109abcdef0 -+ add.l @+er3,@(0x9abcdef0:32,er2.l) ;01056d3cfa109abcdef0 -+ add.l @+er3,@0xffff9abc:16 ;01056d3c40109abc -+ add.l @+er3,@0x9abcdef0:32 ;01056d3c48109abcdef0 -+ -+ add.l @(0x1234:16,er3),@er1 ;01046f3c12340110 -+ add.l @(0x1234:16,er3),@(0xc:2,er1) ;01046f3c12343110 -+ add.l @(0x1234:16,er3),@-er1 ;01046f3c1234b110 -+ add.l @(0x1234:16,er3),@er1+ ;01046f3c12348110 -+ add.l @(0x1234:16,er3),@er1- ;01046f3c1234a110 -+ add.l @(0x1234:16,er3),@+er1 ;01046f3c12349110 -+ add.l @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01046f3c1234c1109abc -+ add.l @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01046f3c1234c9109abcdef0 -+ add.l @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01046f3c1234d2109abc -+ add.l @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01046f3c1234e2109abc -+ add.l @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01046f3c1234f2109abc -+ add.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01046f3c1234da109abcdef0 -+ add.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01046f3c1234ea109abcdef0 -+ add.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01046f3c1234fa109abcdef0 -+ add.l @(0x1234:16,er3),@0xffff9abc:16 ;01046f3c123440109abc -+ add.l @(0x1234:16,er3),@0x9abcdef0:32 ;01046f3c123448109abcdef0 -+ -+ add.l @(0x12345678:32,er3),@er1 ;78b46b2c123456780110 -+ add.l @(0x12345678:32,er3),@(0xc:2,er1) ;78b46b2c123456783110 -+ add.l @(0x12345678:32,er3),@-er1 ;78b46b2c12345678b110 -+ add.l @(0x12345678:32,er3),@er1+ ;78b46b2c123456788110 -+ add.l @(0x12345678:32,er3),@er1- ;78b46b2c12345678a110 -+ add.l @(0x12345678:32,er3),@+er1 ;78b46b2c123456789110 -+ add.l @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78b46b2c12345678c1109abc -+ add.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78b46b2c12345678c9109abcdef0 -+ add.l @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78b46b2c12345678d2109abc -+ add.l @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78b46b2c12345678e2109abc -+ add.l @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78b46b2c12345678f2109abc -+ add.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78b46b2c12345678da109abcdef0 -+ add.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78b46b2c12345678ea109abcdef0 -+ add.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78b46b2c12345678fa109abcdef0 -+ add.l @(0x12345678:32,er3),@0xffff9abc:16 ;78b46b2c1234567840109abc -+ add.l @(0x12345678:32,er3),@0x9abcdef0:32 ;78b46b2c1234567848109abcdef0 -+ -+ add.l @(0x1234:16,r3l.b),@er1 ;01056f3c12340110 -+ add.l @(0x1234:16,r3l.b),@(0xc:2,er1) ;01056f3c12343110 -+ add.l @(0x1234:16,r3l.b),@-er1 ;01056f3c1234b110 -+ add.l @(0x1234:16,r3l.b),@er1+ ;01056f3c12348110 -+ add.l @(0x1234:16,r3l.b),@er1- ;01056f3c1234a110 -+ add.l @(0x1234:16,r3l.b),@+er1 ;01056f3c12349110 -+ add.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01056f3c1234c1109abc -+ add.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01056f3c1234c9109abcdef0 -+ add.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01056f3c1234d2109abc -+ add.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01056f3c1234e2109abc -+ add.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01056f3c1234f2109abc -+ add.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01056f3c1234da109abcdef0 -+ add.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01056f3c1234ea109abcdef0 -+ add.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01056f3c1234fa109abcdef0 -+ add.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;01056f3c123440109abc -+ add.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01056f3c123448109abcdef0 -+ -+ add.l @(0x1234:16,r3.w),@er1 ;01066f3c12340110 -+ add.l @(0x1234:16,r3.w),@(0xc:2,er1) ;01066f3c12343110 -+ add.l @(0x1234:16,r3.w),@-er1 ;01066f3c1234b110 -+ add.l @(0x1234:16,r3.w),@er1+ ;01066f3c12348110 -+ add.l @(0x1234:16,r3.w),@er1- ;01066f3c1234a110 -+ add.l @(0x1234:16,r3.w),@+er1 ;01066f3c12349110 -+ add.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01066f3c1234c1109abc -+ add.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01066f3c1234c9109abcdef0 -+ add.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01066f3c1234d2109abc -+ add.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01066f3c1234e2109abc -+ add.l @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01066f3c1234f2109abc -+ add.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01066f3c1234da109abcdef0 -+ add.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01066f3c1234ea109abcdef0 -+ add.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01066f3c1234fa109abcdef0 -+ add.l @(0x1234:16,r3.w),@0xffff9abc:16 ;01066f3c123440109abc -+ add.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;01066f3c123448109abcdef0 -+ -+ add.l @(0x1234:16,er3.l),@er1 ;01076f3c12340110 -+ add.l @(0x1234:16,er3.l),@(0xc:2,er1) ;01076f3c12343110 -+ add.l @(0x1234:16,er3.l),@-er1 ;01076f3c1234b110 -+ add.l @(0x1234:16,er3.l),@er1+ ;01076f3c12348110 -+ add.l @(0x1234:16,er3.l),@er1- ;01076f3c1234a110 -+ add.l @(0x1234:16,er3.l),@+er1 ;01076f3c12349110 -+ add.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01076f3c1234c1109abc -+ add.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01076f3c1234c9109abcdef0 -+ add.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01076f3c1234d2109abc -+ add.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01076f3c1234e2109abc -+ add.l @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01076f3c1234f2109abc -+ add.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01076f3c1234da109abcdef0 -+ add.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01076f3c1234ea109abcdef0 -+ add.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01076f3c1234fa109abcdef0 -+ add.l @(0x1234:16,er3.l),@0xffff9abc:16 ;01076f3c123440109abc -+ add.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;01076f3c123448109abcdef0 -+ -+ add.l @(0x12345678:32,r3l.b),@er1 ;78b56b2c123456780110 -+ add.l @(0x12345678:32,r3l.b),@(0xc:2,er1) ;78b56b2c123456783110 -+ add.l @(0x12345678:32,r3l.b),@-er1 ;78b56b2c12345678b110 -+ add.l @(0x12345678:32,r3l.b),@er1+ ;78b56b2c123456788110 -+ add.l @(0x12345678:32,r3l.b),@er1- ;78b56b2c12345678a110 -+ add.l @(0x12345678:32,r3l.b),@+er1 ;78b56b2c123456789110 -+ add.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78b56b2c12345678c1109abc -+ add.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78b56b2c12345678c9109abcdef0 -+ add.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78b56b2c12345678d2109abc -+ add.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78b56b2c12345678e2109abc -+ add.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78b56b2c12345678f2109abc -+ add.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78b56b2c12345678da109abcdef0 -+ add.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78b56b2c12345678ea109abcdef0 -+ add.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78b56b2c12345678fa109abcdef0 -+ add.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78b56b2c1234567840109abc -+ add.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78b56b2c1234567848109abcdef0 -+ -+ add.l @(0x12345678:32,r3.w),@er1 ;78b66b2c123456780110 -+ add.l @(0x12345678:32,r3.w),@(0xc:2,er1) ;78b66b2c123456783110 -+ add.l @(0x12345678:32,r3.w),@-er1 ;78b66b2c12345678b110 -+ add.l @(0x12345678:32,r3.w),@er1+ ;78b66b2c123456788110 -+ add.l @(0x12345678:32,r3.w),@er1- ;78b66b2c12345678a110 -+ add.l @(0x12345678:32,r3.w),@+er1 ;78b66b2c123456789110 -+ add.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78b66b2c12345678c1109abc -+ add.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78b66b2c12345678c9109abcdef0 -+ add.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78b66b2c12345678d2109abc -+ add.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78b66b2c12345678e2109abc -+ add.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78b66b2c12345678f2109abc -+ add.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78b66b2c12345678da109abcdef0 -+ add.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78b66b2c12345678ea109abcdef0 -+ add.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78b66b2c12345678fa109abcdef0 -+ add.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;78b66b2c1234567840109abc -+ add.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78b66b2c1234567848109abcdef0 -+ -+ add.l @(0x12345678:32,er3.l),@er1 ;78b76b2c123456780110 -+ add.l @(0x12345678:32,er3.l),@(0xc:2,er1) ;78b76b2c123456783110 -+ add.l @(0x12345678:32,er3.l),@-er1 ;78b76b2c12345678b110 -+ add.l @(0x12345678:32,er3.l),@er1+ ;78b76b2c123456788110 -+ add.l @(0x12345678:32,er3.l),@er1- ;78b76b2c12345678a110 -+ add.l @(0x12345678:32,er3.l),@+er1 ;78b76b2c123456789110 -+ add.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78b76b2c12345678c1109abc -+ add.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78b76b2c12345678c9109abcdef0 -+ add.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78b76b2c12345678d2109abc -+ add.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78b76b2c12345678e2109abc -+ add.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78b76b2c12345678f2109abc -+ add.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78b76b2c12345678da109abcdef0 -+ add.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78b76b2c12345678ea109abcdef0 -+ add.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78b76b2c12345678fa109abcdef0 -+ add.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;78b76b2c1234567840109abc -+ add.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78b76b2c1234567848109abcdef0 -+ -+ add.l @0x1234:16,@er1 ;01046b0c12340110 -+ add.l @0x1234:16,@(0xc:2,er1) ;01046b0c12343110 -+ add.l @0x1234:16,@-er1 ;01046b0c1234b110 -+ add.l @0x1234:16,@er1+ ;01046b0c12348110 -+ add.l @0x1234:16,@er1- ;01046b0c1234a110 -+ add.l @0x1234:16,@+er1 ;01046b0c12349110 -+ add.l @0x1234:16,@(0xffff9abc:16,er1) ;01046b0c1234c1109abc -+ add.l @0x1234:16,@(0x9abcdef0:32,er1) ;01046b0c1234c9109abcdef0 -+ add.l @0x1234:16,@(0xffff9abc:16,r2l.b) ;01046b0c1234d2109abc -+ add.l @0x1234:16,@(0xffff9abc:16,r2.w) ;01046b0c1234e2109abc -+ add.l @0x1234:16,@(0xffff9abc:16,er2.l) ;01046b0c1234f2109abc -+ add.l @0x1234:16,@(0x9abcdef0:32,r2l.b) ;01046b0c1234da109abcdef0 -+ add.l @0x1234:16,@(0x9abcdef0:32,r2.w) ;01046b0c1234ea109abcdef0 -+ add.l @0x1234:16,@(0x9abcdef0:32,er2.l) ;01046b0c1234fa109abcdef0 -+ add.l @0x1234:16,@0xffff9abc:16 ;01046b0c123440109abc -+ add.l @0x1234:16,@0x9abcdef0:32 ;01046b0c123448109abcdef0 -+ -+ add.l @0x12345678:32,@er1 ;01046b2c123456780110 -+ add.l @0x12345678:32,@(0xc:2,er1) ;01046b2c123456783110 -+ add.l @0x12345678:32,@-er1 ;01046b2c12345678b110 -+ add.l @0x12345678:32,@er1+ ;01046b2c123456788110 -+ add.l @0x12345678:32,@er1- ;01046b2c12345678a110 -+ add.l @0x12345678:32,@+er1 ;01046b2c123456789110 -+ add.l @0x12345678:32,@(0xffff9abc:16,er1) ;01046b2c12345678c1109abc -+ add.l @0x12345678:32,@(0x9abcdef0:32,er1) ;01046b2c12345678c9109abcdef0 -+ add.l @0x12345678:32,@(0xffff9abc:16,r2l.b) ;01046b2c12345678d2109abc -+ add.l @0x12345678:32,@(0xffff9abc:16,r2.w) ;01046b2c12345678e2109abc -+ add.l @0x12345678:32,@(0xffff9abc:16,er2.l) ;01046b2c12345678f2109abc -+ add.l @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;01046b2c12345678da109abcdef0 -+ add.l @0x12345678:32,@(0x9abcdef0:32,r2.w) ;01046b2c12345678ea109abcdef0 -+ add.l @0x12345678:32,@(0x9abcdef0:32,er2.l) ;01046b2c12345678fa109abcdef0 -+ add.l @0x12345678:32,@0xffff9abc:16 ;01046b2c1234567840109abc -+ add.l @0x12345678:32,@0x9abcdef0:32 ;01046b2c1234567848109abcdef0 -+ -+ .end ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;arith_1 ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ .h8300sx ++ .text ++_start: ++ add.b #0x12:8,r1h ;8112 ++ add.b #0x12:8,@er1 ;7d108012 ++ add.b #0x12:8,@(0x3:2,er1) ;017768188012 ++ add.b #0x12:8,@er1+ ;01746c188012 ++ add.b #0x12:8,@-er1 ;01776c188012 ++ add.b #0x12:8,@+er1 ;01756c188012 ++ add.b #0x12:8,@er1- ;01766c188012 ++ add.b #0x12:8,@(0x1234:16,er1) ;01746e1812348012 ++ add.b #0x12:8,@(0x12345678:32,er1) ;78146a28123456788012 ++ add.b #0x12:8,@(0x1234:16,r2l.b) ;01756e2812348012 ++ add.b #0x12:8,@(0x1234:16,r2.w) ;01766e2812348012 ++ add.b #0x12:8,@(0x1234:16,er2.l) ;01776e2812348012 ++ add.b #0x12:8,@(0x12345678:32,r2l.b) ;78256a28123456788012 ++ add.b #0x12:8,@(0x12345678:32,r2.w) ;78266a28123456788012 ++ add.b #0x12:8,@(0x12345678:32,er2.l) ;78276a28123456788012 ++ add.b #0x12:8,@0xffffff9a:8 ;7f9a8012 ++ add.b #0x12:8,@0x1234:16 ;6a1812348012 ++ add.b #0x12:8,@0x12345678:32 ;6a38123456788012 ++ ++ add.b r3h,r1h ;0831 ++ ++ add.b r3h,@er1 ;7d100830 ++ add.b r3h,@(0x3:2,er1) ;01793113 ++ add.b r3h,@er1+ ;01798113 ++ add.b r3h,@-er1 ;0179b113 ++ add.b r3h,@+er1 ;01799113 ++ add.b r3h,@er1- ;0179a113 ++ add.b r3h,@(0x1234:16,er1) ;0179c1131234 ++ add.b r3h,@(0x12345678:32,er1) ;0179c91312345678 ++ add.b r3h,@(0x1234:16,r2l.b) ;0179d2131234 ++ add.b r3h,@(0x1234:16,r2.w) ;0179e2131234 ++ add.b r3h,@(0x1234:16,er2.l) ;0179f2131234 ++ add.b r3h,@(0x12345678:32,r2l.b) ;0179da1312345678 ++ add.b r3h,@(0x12345678:32,r2.w) ;0179ea1312345678 ++ add.b r3h,@(0x12345678:32,er2.l) ;0179fa1312345678 ++ add.b r3h,@0xffffff12:8 ;7f120830 ++ add.b r3h,@0x1234:16 ;6a1812340830 ++ add.b r3h,@0x12345678:32 ;6a38123456780830 ++ ++ add.b @er3,r1h ;7c300801 ++ add.b @(0x3:2,er3),r1h ;017a3311 ++ add.b @er3+,r1h ;017a8311 ++ add.b @-er3,r1h ;017ab311 ++ add.b @+er3,r1h ;017a9311 ++ add.b @er3-,r1h ;017aa311 ++ add.b @(0x1234:16,er1),r1h ;017ac1111234 ++ add.b @(0x12345678:32,er1),r1h ;017ac91112345678 ++ add.b @(0x1234:16,r2l.b),r1h ;017ad2111234 ++ add.b @(0x1234:16,r2.w),r1h ;017ae2111234 ++ add.b @(0x1234:16,er2.l),r1h ;017af2111234 ++ add.b @(0x12345678:32,r2l.b),r1h ;017ada1112345678 ++ add.b @(0x12345678:32,r2.w),r1h ;017aea1112345678 ++ add.b @(0x12345678:32,er2.l),r1h ;017afa1112345678 ++ add.b @0xffffff12:8,r1h ;7e120801 ++ add.b @0x1234:16,r1h ;6a1012340801 ++ add.b @0x12345678:32,r1h ;6a30123456780801 ++ ++ add.b @er3,@er1 ;7c350110 ++ add.b @er3,@(3:2,er1) ;7c353110 ++ add.b @er3,@-er1 ;7c35b110 ++ add.b @er3,@er1+ ;7c358110 ++ add.b @er3,@er1- ;7c35a110 ++ add.b @er3,@+er1 ;7c359110 ++ add.b @er3,@(0xffff9abc:16,er1) ;7c35c1109abc ++ add.b @er3,@(0x9abcdef0:32,er1) ;7c35c9109abcdef0 ++ add.b @er3,@(0xffff9abc:16,r2l.b) ;7c35d2109abc ++ add.b @er3,@(0xffff9abc:16,r2.w) ;7c35e2109abc ++ add.b @er3,@(0xffff9abc:16,er2.l) ;7c35f2109abc ++ add.b @er3,@(0x9abcdef0:32,r2l.b) ;7c35da109abcdef0 ++ add.b @er3,@(0x9abcdef0:32,r2.w) ;7c35ea109abcdef0 ++ add.b @er3,@(0x9abcdef0:32,er2.l) ;7c35fa109abcdef0 ++ add.b @er3,@0xffff9abc:16 ;7c3540109abc ++ add.b @er3,@0x9abcdef0:32 ;7c3548109abcdef0 ++ ++ add.b @-er3,@er1 ;01776c3c0110 ++ add.b @-er3,@(3:2,er1) ;01776c3c3110 ++ add.b @-er3,@-er1 ;01776c3cb110 ++ add.b @-er3,@er1+ ;01776c3c8110 ++ add.b @-er3,@er1- ;01776c3ca110 ++ add.b @-er3,@+er1 ;01776c3c9110 ++ add.b @-er3,@(0xffff9abc:16,er1) ;01776c3cc1109abc ++ add.b @-er3,@(0x9abcdef0:32,er1) ;01776c3cc9109abcdef0 ++ add.b @-er3,@(0xffff9abc:16,r2l.b) ;01776c3cd2109abc ++ add.b @-er3,@(0xffff9abc:16,r2.w) ;01776c3ce2109abc ++ add.b @-er3,@(0xffff9abc:16,er2.l) ;01776c3cf2109abc ++ add.b @-er3,@(0x9abcdef0:32,r2l.b) ;01776c3cda109abcdef0 ++ add.b @-er3,@(0x9abcdef0:32,r2.w) ;01776c3cea109abcdef0 ++ add.b @-er3,@(0x9abcdef0:32,er2.l) ;01776c3cfa109abcdef0 ++ add.b @-er3,@0xffff9abc:16 ;01776c3c40109abc ++ add.b @-er3,@0x9abcdef0:32 ;01776c3c48109abcdef0 ++ ++ add.b @er3+,@er1 ;01746c3c0110 ++ add.b @er3+,@(3:2,er1) ;01746c3c3110 ++ add.b @er3+,@-er1 ;01746c3cb110 ++ add.b @er3+,@er1+ ;01746c3c8110 ++ add.b @er3+,@er1- ;01746c3ca110 ++ add.b @er3+,@+er1 ;01746c3c9110 ++ add.b @er3+,@(0xffff9abc:16,er1) ;01746c3cc1109abc ++ add.b @er3+,@(0x9abcdef0:32,er1) ;01746c3cc9109abcdef0 ++ add.b @er3+,@(0xffff9abc:16,r2l.b) ;01746c3cd2109abc ++ add.b @er3+,@(0xffff9abc:16,r2.w) ;01746c3ce2109abc ++ add.b @er3+,@(0xffff9abc:16,er2.l) ;01746c3cf2109abc ++ add.b @er3+,@(0x9abcdef0:32,r2l.b) ;01746c3cda109abcdef0 ++ add.b @er3+,@(0x9abcdef0:32,r2.w) ;01746c3cea109abcdef0 ++ add.b @er3+,@(0x9abcdef0:32,er2.l) ;01746c3cfa109abcdef0 ++ add.b @er3+,@0xffff9abc:16 ;01746c3c40109abc ++ add.b @er3+,@0x9abcdef0:32 ;01746c3c48109abcdef0 ++ ++ add.b @er3-,@er1 ;01766c3c0110 ++ add.b @er3-,@(3:2,er1) ;01766c3c3110 ++ add.b @er3-,@-er1 ;01766c3cb110 ++ add.b @er3-,@er1+ ;01766c3c8110 ++ add.b @er3-,@er1- ;01766c3ca110 ++ add.b @er3-,@+er1 ;01766c3c9110 ++ add.b @er3-,@(0xffff9abc:16,er1) ;01766c3cc1109abc ++ add.b @er3-,@(0x9abcdef0:32,er1) ;01766c3cc9109abcdef0 ++ add.b @er3-,@(0xffff9abc:16,r2l.b) ;01766c3cd2109abc ++ add.b @er3-,@(0xffff9abc:16,r2.w) ;01766c3ce2109abc ++ add.b @er3-,@(0xffff9abc:16,er2.l) ;01766c3cf2109abc ++ add.b @er3-,@(0x9abcdef0:32,r2l.b) ;01766c3cda109abcdef0 ++ add.b @er3-,@(0x9abcdef0:32,r2.w) ;01766c3cea109abcdef0 ++ add.b @er3-,@(0x9abcdef0:32,er2.l) ;01766c3cfa109abcdef0 ++ add.b @er3-,@0xffff9abc:16 ;01766c3c40109abc ++ add.b @er3-,@0x9abcdef0:32 ;01766c3c48109abcdef0 ++ ++ add.b @+er3,@er1 ;01756c3c0110 ++ add.b @+er3,@(3:2,er1) ;01756c3c3110 ++ add.b @+er3,@-er1 ;01756c3cb110 ++ add.b @+er3,@er1+ ;01756c3c8110 ++ add.b @+er3,@er1- ;01756c3ca110 ++ add.b @+er3,@+er1 ;01756c3c9110 ++ add.b @+er3,@(0xffff9abc:16,er1) ;01756c3cc1109abc ++ add.b @+er3,@(0x9abcdef0:32,er1) ;01756c3cc9109abcdef0 ++ add.b @+er3,@(0xffff9abc:16,r2l.b) ;01756c3cd2109abc ++ add.b @+er3,@(0xffff9abc:16,r2.w) ;01756c3ce2109abc ++ add.b @+er3,@(0xffff9abc:16,er2.l) ;01756c3cf2109abc ++ add.b @+er3,@(0x9abcdef0:32,r2l.b) ;01756c3cda109abcdef0 ++ add.b @+er3,@(0x9abcdef0:32,r2.w) ;01756c3cea109abcdef0 ++ add.b @+er3,@(0x9abcdef0:32,er2.l) ;01756c3cfa109abcdef0 ++ add.b @+er3,@0xffff9abc:16 ;01756c3c40109abc ++ add.b @+er3,@0x9abcdef0:32 ;01756c3c48109abcdef0 ++ ++ add.b @(0x1234:16,er3),@er1 ;01746e3c12340110 ++ add.b @(0x1234:16,er3),@(3:2,er1) ;01746e3c12343110 ++ add.b @(0x1234:16,er3),@-er1 ;01746e3c1234b110 ++ add.b @(0x1234:16,er3),@er1+ ;01746e3c12348110 ++ add.b @(0x1234:16,er3),@er1- ;01746e3c1234a110 ++ add.b @(0x1234:16,er3),@+er1 ;01746e3c12349110 ++ add.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01746e3c1234c1109abc ++ add.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01746e3c1234c9109abcdef0 ++ add.b @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01746e3c1234d2109abc ++ add.b @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01746e3c1234e2109abc ++ add.b @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01746e3c1234f2109abc ++ add.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01746e3c1234da109abcdef0 ++ add.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01746e3c1234ea109abcdef0 ++ add.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01746e3c1234fa109abcdef0 ++ add.b @(0x1234:16,er3),@0xffff9abc:16 ;01746e3c123440109abc ++ add.b @(0x1234:16,er3),@0x9abcdef0:32 ;01746e3c123448109abcdef0 ++ ++ add.b @(0x12345678:32,er3),@er1 ;78346a2c123456780110 ++ add.b @(0x12345678:32,er3),@(3:2,er1) ;78346a2c123456783110 ++ add.b @(0x12345678:32,er3),@-er1 ;78346a2c12345678b110 ++ add.b @(0x12345678:32,er3),@er1+ ;78346a2c123456788110 ++ add.b @(0x12345678:32,er3),@er1- ;78346a2c12345678a110 ++ add.b @(0x12345678:32,er3),@+er1 ;78346a2c123456789110 ++ add.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346a2c12345678c1109abc ++ add.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346a2c12345678c9109abcdef0 ++ add.b @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346a2c12345678d2109abc ++ add.b @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346a2c12345678e2109abc ++ add.b @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346a2c12345678f2109abc ++ add.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346a2c12345678da109abcdef0 ++ add.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346a2c12345678ea109abcdef0 ++ add.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346a2c12345678fa109abcdef0 ++ add.b @(0x12345678:32,er3),@0xffff9abc:16 ;78346a2c1234567840109abc ++ add.b @(0x12345678:32,er3),@0x9abcdef0:32 ;78346a2c1234567848109abcdef0 ++ ++ add.b @(0x1234:16,r3l.b),@er1 ;01756e3c12340110 ++ add.b @(0x1234:16,r3l.b),@(3:2,er1) ;01756e3c12343110 ++ add.b @(0x1234:16,r3l.b),@-er1 ;01756e3c1234b110 ++ add.b @(0x1234:16,r3l.b),@er1+ ;01756e3c12348110 ++ add.b @(0x1234:16,r3l.b),@er1- ;01756e3c1234a110 ++ add.b @(0x1234:16,r3l.b),@+er1 ;01756e3c12349110 ++ add.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01756e3c1234c1109abc ++ add.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01756e3c1234c9109abcdef0 ++ add.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01756e3c1234d2109abc ++ add.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01756e3c1234e2109abc ++ add.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01756e3c1234f2109abc ++ add.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01756e3c1234da109abcdef0 ++ add.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01756e3c1234ea109abcdef0 ++ add.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01756e3c1234fa109abcdef0 ++ add.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;01756e3c123440109abc ++ add.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01756e3c123448109abcdef0 ++ ++ add.b @(0x1234:16,r3.w),@er1 ;01766e3c12340110 ++ add.b @(0x1234:16,r3.w),@(3:2,er1) ;01766e3c12343110 ++ add.b @(0x1234:16,r3.w),@-er1 ;01766e3c1234b110 ++ add.b @(0x1234:16,r3.w),@er1+ ;01766e3c12348110 ++ add.b @(0x1234:16,r3.w),@er1- ;01766e3c1234a110 ++ add.b @(0x1234:16,r3.w),@+er1 ;01766e3c12349110 ++ add.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01766e3c1234c1109abc ++ add.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01766e3c1234c9109abcdef0 ++ add.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01766e3c1234d2109abc ++ add.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01766e3c1234e2109abc ++ add.b @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01766e3c1234f2109abc ++ add.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01766e3c1234da109abcdef0 ++ add.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01766e3c1234ea109abcdef0 ++ add.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01766e3c1234fa109abcdef0 ++ add.b @(0x1234:16,r3.w),@0xffff9abc:16 ;01766e3c123440109abc ++ add.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;01766e3c123448109abcdef0 ++ ++ add.b @(0x1234:16,er3.l),@er1 ;01776e3c12340110 ++ add.b @(0x1234:16,er3.l),@(3:2,er1) ;01776e3c12343110 ++ add.b @(0x1234:16,er3.l),@-er1 ;01776e3c1234b110 ++ add.b @(0x1234:16,er3.l),@er1+ ;01776e3c12348110 ++ add.b @(0x1234:16,er3.l),@er1- ;01776e3c1234a110 ++ add.b @(0x1234:16,er3.l),@+er1 ;01776e3c12349110 ++ add.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01776e3c1234c1109abc ++ add.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01776e3c1234c9109abcdef0 ++ add.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01776e3c1234d2109abc ++ add.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01776e3c1234e2109abc ++ add.b @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01776e3c1234f2109abc ++ add.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01776e3c1234da109abcdef0 ++ add.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01776e3c1234ea109abcdef0 ++ add.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01776e3c1234fa109abcdef0 ++ add.b @(0x1234:16,er3.l),@0xffff9abc:16 ;01776e3c123440109abc ++ add.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;01776e3c123448109abcdef0 ++ ++ add.b @(0x12345678:32,r3l.b),@er1 ;78356a2c123456780110 ++ add.b @(0x12345678:32,r3l.b),@(3:2,er1) ;78356a2c123456783110 ++ add.b @(0x12345678:32,r3l.b),@-er1 ;78356a2c12345678b110 ++ add.b @(0x12345678:32,r3l.b),@er1+ ;78356a2c123456788110 ++ add.b @(0x12345678:32,r3l.b),@er1- ;78356a2c12345678a110 ++ add.b @(0x12345678:32,r3l.b),@+er1 ;78356a2c123456789110 ++ add.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356a2c12345678c1109abc ++ add.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356a2c12345678c9109abcdef0 ++ add.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356a2c12345678d2109abc ++ add.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356a2c12345678e2109abc ++ add.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356a2c12345678f2109abc ++ add.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356a2c12345678da109abcdef0 ++ add.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356a2c12345678ea109abcdef0 ++ add.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356a2c12345678fa109abcdef0 ++ add.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356a2c1234567840109abc ++ add.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356a2c1234567848109abcdef0 ++ ++ add.b @(0x12345678:32,r3.w),@er1 ;78366a2c123456780110 ++ add.b @(0x12345678:32,r3.w),@(3:2,er1) ;78366a2c123456783110 ++ add.b @(0x12345678:32,r3.w),@-er1 ;78366a2c12345678b110 ++ add.b @(0x12345678:32,r3.w),@er1+ ;78366a2c123456788110 ++ add.b @(0x12345678:32,r3.w),@er1- ;78366a2c12345678a110 ++ add.b @(0x12345678:32,r3.w),@+er1 ;78366a2c123456789110 ++ add.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366a2c12345678c1109abc ++ add.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366a2c12345678c9109abcdef0 ++ add.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366a2c12345678d2109abc ++ add.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366a2c12345678e2109abc ++ add.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366a2c12345678f2109abc ++ add.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366a2c12345678da109abcdef0 ++ add.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366a2c12345678ea109abcdef0 ++ add.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366a2c12345678fa109abcdef0 ++ add.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366a2c1234567840109abc ++ add.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366a2c1234567848109abcdef0 ++ ++ add.b @(0x12345678:32,er3.l),@er1 ;78376a2c123456780110 ++ add.b @(0x12345678:32,er3.l),@(3:2,er1) ;78376a2c123456783110 ++ add.b @(0x12345678:32,er3.l),@-er1 ;78376a2c12345678b110 ++ add.b @(0x12345678:32,er3.l),@er1+ ;78376a2c123456788110 ++ add.b @(0x12345678:32,er3.l),@er1- ;78376a2c12345678a110 ++ add.b @(0x12345678:32,er3.l),@+er1 ;78376a2c123456789110 ++ add.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376a2c12345678c1109abc ++ add.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376a2c12345678c9109abcdef0 ++ add.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376a2c12345678d2109abc ++ add.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376a2c12345678e2109abc ++ add.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376a2c12345678f2109abc ++ add.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376a2c12345678da109abcdef0 ++ add.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376a2c12345678ea109abcdef0 ++ add.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376a2c12345678fa109abcdef0 ++ add.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376a2c1234567840109abc ++ add.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376a2c1234567848109abcdef0 ++ ++ add.b @0x1234:16,@er1 ;6a1512340110 ++ add.b @0x1234:16,@(3:2,er1) ;6a1512343110 ++ add.b @0x1234:16,@-er1 ;6a151234b110 ++ add.b @0x1234:16,@er1+ ;6a1512348110 ++ add.b @0x1234:16,@er1- ;6a151234a110 ++ add.b @0x1234:16,@+er1 ;6a1512349110 ++ add.b @0x1234:16,@(0xffff9abc:16,er1) ;6a151234c1109abc ++ add.b @0x1234:16,@(0x9abcdef0:32,er1) ;6a151234c9109abcdef0 ++ add.b @0x1234:16,@(0xffff9abc:16,r2l.b) ;6a151234d2109abc ++ add.b @0x1234:16,@(0xffff9abc:16,r2.w) ;6a151234e2109abc ++ add.b @0x1234:16,@(0xffff9abc:16,er2.l) ;6a151234f2109abc ++ add.b @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6a151234da109abcdef0 ++ add.b @0x1234:16,@(0x9abcdef0:32,r2.w) ;6a151234ea109abcdef0 ++ add.b @0x1234:16,@(0x9abcdef0:32,er2.l) ;6a151234fa109abcdef0 ++ add.b @0x1234:16,@0xffff9abc:16 ;6a15123440109abc ++ add.b @0x1234:16,@0x9abcdef0:32 ;6a15123448109abcdef0 ++ ++ add.b @0x12345678:32,@er1 ;6a35123456780110 ++ add.b @0x12345678:32,@(3:2,er1) ;6a35123456783110 ++ add.b @0x12345678:32,@-er1 ;6a3512345678b110 ++ add.b @0x12345678:32,@er1+ ;6a35123456788110 ++ add.b @0x12345678:32,@er1- ;6a3512345678a110 ++ add.b @0x12345678:32,@+er1 ;6a35123456789110 ++ add.b @0x12345678:32,@(0xffff9abc:16,er1) ;6a3512345678c1109abc ++ add.b @0x12345678:32,@(0x9abcdef0:32,er1) ;6a3512345678c9109abcdef0 ++ add.b @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6a3512345678d2109abc ++ add.b @0x12345678:32,@(0xffff9abc:16,r2.w) ;6a3512345678e2109abc ++ add.b @0x12345678:32,@(0xffff9abc:16,er2.l) ;6a3512345678f2109abc ++ add.b @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6a3512345678da109abcdef0 ++ add.b @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6a3512345678ea109abcdef0 ++ add.b @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6a3512345678fa109abcdef0 ++ add.b @0x12345678:32,@0xffff9abc:16 ;6a351234567840109abc ++ add.b @0x12345678:32,@0x9abcdef0:32 ;6a351234567848109abcdef0 ++ ++ add.w #0x1234:16,r1 ;79111234 ++ add.w #0x7:3,r2 ;0a72 ++ add.w #0x1234:16,@er1 ;015e01101234 ++ add.w #0x1234:16,@(0x6:2,er1) ;015e31101234 ++ add.w #0x1234:16,@er1+ ;015e81101234 ++ add.w #0x1234:16,@-er1 ;015eb1101234 ++ add.w #0x1234:16,@+er1 ;015e91101234 ++ add.w #0x1234:16,@er1- ;015ea1101234 ++ add.w #0x1234:16,@(0xffff9abc:16,er1) ;015ec1109abc1234 ++ add.w #0x1234:16,@(0x9abcdef0:32,er1) ;015ec9109abcdef01234 ++ add.w #0x1234:16,@(0xffff9abc:16,r2l.b) ;015ed2109abc1234 ++ add.w #0x1234:16,@(0xffff9abc:16,r2.w) ;015ee2109abc1234 ++ add.w #0x1234:16,@(0xffff9abc:16,er2.l) ;015ef2109abc1234 ++ add.w #0x1234:16,@(0x9abcdef0:32,r2l.b) ;015eda109abcdef01234 ++ add.w #0x1234:16,@(0x9abcdef0:32,r2.w) ;015eea109abcdef01234 ++ add.w #0x1234:16,@(0x9abcdef0:32,er2.l) ;015efa109abcdef01234 ++ add.w #0x1234:16,@0xffff9abc:16 ;015e40109abc1234 ++ add.w #0x1234:16,@0x9abcdef0:32 ;015e48109abcdef01234 ++ ++ add.w #0x7:3,@er1 ;7d900a70 ++ add.w #0x7:3,@0x1234:16 ;6b1812340a70 ++ add.w #0x7:3,@0x12345678:32 ;6b38123456780a70 ++ ++ add.w r3,r1 ;0931 ++ ++ add.w r3,@er1 ;7d900930 ++ add.w r3,@(0x6:2,er1) ;01593113 ++ add.w r3,@er1+ ;01598113 ++ add.w r3,@-er1 ;0159b113 ++ add.w r3,@+er1 ;01599113 ++ add.w r3,@er1- ;0159a113 ++ add.w r3,@(0x1234:16,er1) ;0159c1131234 ++ add.w r3,@(0x12345678:32,er1) ;0159c91312345678 ++ add.w r3,@(0x1234:16,r2l.b) ;0159d2131234 ++ add.w r3,@(0x1234:16,r2.w) ;0159e2131234 ++ add.w r3,@(0x1234:16,er2.l) ;0159f2131234 ++ add.w r3,@(0x12345678:32,r2l.b) ;0159da1312345678 ++ add.w r3,@(0x12345678:32,r2.w) ;0159ea1312345678 ++ add.w r3,@(0x12345678:32,er2.l) ;0159fa1312345678 ++ add.w r3,@0x1234:16 ;6b1812340930 ++ add.w r3,@0x12345678:32 ;6b38123456780930 ++ ++ add.w @er3,r1 ;7cb00901 ++ add.w @(0x6:2,er1),r1 ;015a3111 ++ add.w @er3+,r1 ;015a8311 ++ add.w @-er3,r1 ;015ab311 ++ add.w @+er3,r1 ;015a9311 ++ add.w @er3-,r1 ;015aa311 ++ add.w @(0x1234:16,er1),r1 ;015ac1111234 ++ add.w @(0x12345678:32,er1),r1 ;015ac91112345678 ++ add.w @(0x1234:16,r2l.b),r1 ;015ad2111234 ++ add.w @(0x1234:16,r2.w),r1 ;015ae2111234 ++ add.w @(0x1234:16,er2.l),r1 ;015af2111234 ++ add.w @(0x12345678:32,r2l.b),r1 ;015ada1112345678 ++ add.w @(0x12345678:32,r2.w),r1 ;015aea1112345678 ++ add.w @(0x12345678:32,er2.l),r1 ;015afa1112345678 ++ add.w @0x1234:16,r1 ;6b1012340901 ++ add.w @0x12345678:32,r1 ;6b30123456780901 ++ ++ add.w @er3,@er1 ;7cb50110 ++ add.w @er3,@(6:2,er1) ;7cb53110 ++ add.w @er3,@-er1 ;7cb5b110 ++ add.w @er3,@er1+ ;7cb58110 ++ add.w @er3,@er1- ;7cb5a110 ++ add.w @er3,@+er1 ;7cb59110 ++ add.w @er3,@(0xffff9abc:16,er1) ;7cb5c1109abc ++ add.w @er3,@(0x9abcdef0:32,er1) ;7cb5c9109abcdef0 ++ add.w @er3,@(0xffff9abc:16,r2l.b) ;7cb5d2109abc ++ add.w @er3,@(0xffff9abc:16,r2.w) ;7cb5e2109abc ++ add.w @er3,@(0xffff9abc:16,er2.l) ;7cb5f2109abc ++ add.w @er3,@(0x9abcdef0:32,r2l.b) ;7cb5da109abcdef0 ++ add.w @er3,@(0x9abcdef0:32,r2.w) ;7cb5ea109abcdef0 ++ add.w @er3,@(0x9abcdef0:32,er2.l) ;7cb5fa109abcdef0 ++ add.w @er3,@0xffff9abc:16 ;7cb540109abc ++ add.w @er3,@0x9abcdef0:32 ;7cb548109abcdef0 ++ ++ add.w @-er3,@er1 ;01576d3c0110 ++ add.w @-er3,@(6:2,er1) ;01576d3c3110 ++ add.w @-er3,@-er1 ;01576d3cb110 ++ add.w @-er3,@er1+ ;01576d3c8110 ++ add.w @-er3,@er1- ;01576d3ca110 ++ add.w @-er3,@+er1 ;01576d3c9110 ++ add.w @-er3,@(0xffff9abc:16,er1) ;01576d3cc1109abc ++ add.w @-er3,@(0x9abcdef0:32,er1) ;01576d3cc9109abcdef0 ++ add.w @-er3,@(0xffff9abc:16,r2l.b) ;01576d3cd2109abc ++ add.w @-er3,@(0xffff9abc:16,r2.w) ;01576d3ce2109abc ++ add.w @-er3,@(0xffff9abc:16,er2.l) ;01576d3cf2109abc ++ add.w @-er3,@(0x9abcdef0:32,r2l.b) ;01576d3cda109abcdef0 ++ add.w @-er3,@(0x9abcdef0:32,r2.w) ;01576d3cea109abcdef0 ++ add.w @-er3,@(0x9abcdef0:32,er2.l) ;01576d3cfa109abcdef0 ++ add.w @-er3,@0xffff9abc:16 ;01576d3c40109abc ++ add.w @-er3,@0x9abcdef0:32 ;01576d3c48109abcdef0 ++ ++ add.w @er3+,@er1 ;01546d3c0110 ++ add.w @er3+,@(6:2,er1) ;01546d3c3110 ++ add.w @er3+,@-er1 ;01546d3cb110 ++ add.w @er3+,@er1+ ;01546d3c8110 ++ add.w @er3+,@er1- ;01546d3ca110 ++ add.w @er3+,@+er1 ;01546d3c9110 ++ add.w @er3+,@(0xffff9abc:16,er1) ;01546d3cc1109abc ++ add.w @er3+,@(0x9abcdef0:32,er1) ;01546d3cc9109abcdef0 ++ add.w @er3+,@(0xffff9abc:16,r2l.b) ;01546d3cd2109abc ++ add.w @er3+,@(0xffff9abc:16,r2.w) ;01546d3ce2109abc ++ add.w @er3+,@(0xffff9abc:16,er2.l) ;01546d3cf2109abc ++ add.w @er3+,@(0x9abcdef0:32,r2l.b) ;01546d3cda109abcdef0 ++ add.w @er3+,@(0x9abcdef0:32,r2.w) ;01546d3cea109abcdef0 ++ add.w @er3+,@(0x9abcdef0:32,er2.l) ;01546d3cfa109abcdef0 ++ add.w @er3+,@0xffff9abc:16 ;01546d3c40109abc ++ add.w @er3+,@0x9abcdef0:32 ;01546d3c48109abcdef0 ++ ++ add.w @er3-,@er1 ;01566d3c0110 ++ add.w @er3-,@(6:2,er1) ;01566d3c3110 ++ add.w @er3-,@-er1 ;01566d3cb110 ++ add.w @er3-,@er1+ ;01566d3c8110 ++ add.w @er3-,@er1- ;01566d3ca110 ++ add.w @er3-,@+er1 ;01566d3c9110 ++ add.w @er3-,@(0xffff9abc:16,er1) ;01566d3cc1109abc ++ add.w @er3-,@(0x9abcdef0:32,er1) ;01566d3cc9109abcdef0 ++ add.w @er3-,@(0xffff9abc:16,r2l.b) ;01566d3cd2109abc ++ add.w @er3-,@(0xffff9abc:16,r2.w) ;01566d3ce2109abc ++ add.w @er3-,@(0xffff9abc:16,er2.l) ;01566d3cf2109abc ++ add.w @er3-,@(0x9abcdef0:32,r2l.b) ;01566d3cda109abcdef0 ++ add.w @er3-,@(0x9abcdef0:32,r2.w) ;01566d3cea109abcdef0 ++ add.w @er3-,@(0x9abcdef0:32,er2.l) ;01566d3cfa109abcdef0 ++ add.w @er3-,@0xffff9abc:16 ;01566d3c40109abc ++ add.w @er3-,@0x9abcdef0:32 ;01566d3c48109abcdef0 ++ ++ add.w @+er3,@er1 ;01556d3c0110 ++ add.w @+er3,@(6:2,er1) ;01556d3c3110 ++ add.w @+er3,@-er1 ;01556d3cb110 ++ add.w @+er3,@er1+ ;01556d3c8110 ++ add.w @+er3,@er1- ;01556d3ca110 ++ add.w @+er3,@+er1 ;01556d3c9110 ++ add.w @+er3,@(0xffff9abc:16,er1) ;01556d3cc1109abc ++ add.w @+er3,@(0x9abcdef0:32,er1) ;01556d3cc9109abcdef0 ++ add.w @+er3,@(0xffff9abc:16,r2l.b) ;01556d3cd2109abc ++ add.w @+er3,@(0xffff9abc:16,r2.w) ;01556d3ce2109abc ++ add.w @+er3,@(0xffff9abc:16,er2.l) ;01556d3cf2109abc ++ add.w @+er3,@(0x9abcdef0:32,r2l.b) ;01556d3cda109abcdef0 ++ add.w @+er3,@(0x9abcdef0:32,r2.w) ;01556d3cea109abcdef0 ++ add.w @+er3,@(0x9abcdef0:32,er2.l) ;01556d3cfa109abcdef0 ++ add.w @+er3,@0xffff9abc:16 ;01556d3c40109abc ++ add.w @+er3,@0x9abcdef0:32 ;01556d3c48109abcdef0 ++ ++ add.w @(0x1234:16,er3),@er1 ;01546f3c12340110 ++ add.w @(0x1234:16,er3),@(6:2,er1) ;01546f3c12343110 ++ add.w @(0x1234:16,er3),@-er1 ;01546f3c1234b110 ++ add.w @(0x1234:16,er3),@er1+ ;01546f3c12348110 ++ add.w @(0x1234:16,er3),@er1- ;01546f3c1234a110 ++ add.w @(0x1234:16,er3),@+er1 ;01546f3c12349110 ++ add.w @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01546f3c1234c1109abc ++ add.w @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01546f3c1234c9109abcdef0 ++ add.w @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01546f3c1234d2109abc ++ add.w @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01546f3c1234e2109abc ++ add.w @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01546f3c1234f2109abc ++ add.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01546f3c1234da109abcdef0 ++ add.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01546f3c1234ea109abcdef0 ++ add.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01546f3c1234fa109abcdef0 ++ add.w @(0x1234:16,er3),@0xffff9abc:16 ;01546f3c123440109abc ++ add.w @(0x1234:16,er3),@0x9abcdef0:32 ;01546f3c123448109abcdef0 ++ ++ add.w @(0x12345678:32,er3),@er1 ;78346b2c123456780110 ++ add.w @(0x12345678:32,er3),@(6:2,er1) ;78346b2c123456783110 ++ add.w @(0x12345678:32,er3),@-er1 ;78346b2c12345678b110 ++ add.w @(0x12345678:32,er3),@er1+ ;78346b2c123456788110 ++ add.w @(0x12345678:32,er3),@er1- ;78346b2c12345678a110 ++ add.w @(0x12345678:32,er3),@+er1 ;78346b2c123456789110 ++ add.w @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346b2c12345678c1109abc ++ add.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346b2c12345678c9109abcdef0 ++ add.w @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346b2c12345678d2109abc ++ add.w @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346b2c12345678e2109abc ++ add.w @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346b2c12345678f2109abc ++ add.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346b2c12345678da109abcdef0 ++ add.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346b2c12345678ea109abcdef0 ++ add.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346b2c12345678fa109abcdef0 ++ add.w @(0x12345678:32,er3),@0xffff9abc:16 ;78346b2c1234567840109abc ++ add.w @(0x12345678:32,er3),@0x9abcdef0:32 ;78346b2c1234567848109abcdef0 ++ ++ add.w @(0x1234:16,r3l.b),@er1 ;01556f3c12340110 ++ add.w @(0x1234:16,r3l.b),@(6:2,er1) ;01556f3c12343110 ++ add.w @(0x1234:16,r3l.b),@-er1 ;01556f3c1234b110 ++ add.w @(0x1234:16,r3l.b),@er1+ ;01556f3c12348110 ++ add.w @(0x1234:16,r3l.b),@er1- ;01556f3c1234a110 ++ add.w @(0x1234:16,r3l.b),@+er1 ;01556f3c12349110 ++ add.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01556f3c1234c1109abc ++ add.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01556f3c1234c9109abcdef0 ++ add.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01556f3c1234d2109abc ++ add.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01556f3c1234e2109abc ++ add.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01556f3c1234f2109abc ++ add.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01556f3c1234da109abcdef0 ++ add.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01556f3c1234ea109abcdef0 ++ add.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01556f3c1234fa109abcdef0 ++ add.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;01556f3c123440109abc ++ add.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01556f3c123448109abcdef0 ++ ++ add.w @(0x1234:16,r3.w),@er1 ;01566f3c12340110 ++ add.w @(0x1234:16,r3.w),@(6:2,er1) ;01566f3c12343110 ++ add.w @(0x1234:16,r3.w),@-er1 ;01566f3c1234b110 ++ add.w @(0x1234:16,r3.w),@er1+ ;01566f3c12348110 ++ add.w @(0x1234:16,r3.w),@er1- ;01566f3c1234a110 ++ add.w @(0x1234:16,r3.w),@+er1 ;01566f3c12349110 ++ add.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01566f3c1234c1109abc ++ add.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01566f3c1234c9109abcdef0 ++ add.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01566f3c1234d2109abc ++ add.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01566f3c1234e2109abc ++ add.w @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01566f3c1234f2109abc ++ add.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01566f3c1234da109abcdef0 ++ add.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01566f3c1234ea109abcdef0 ++ add.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01566f3c1234fa109abcdef0 ++ add.w @(0x1234:16,r3.w),@0xffff9abc:16 ;01566f3c123440109abc ++ add.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;01566f3c123448109abcdef0 ++ ++ add.w @(0x1234:16,er3.l),@er1 ;01576f3c12340110 ++ add.w @(0x1234:16,er3.l),@(6:2,er1) ;01576f3c12343110 ++ add.w @(0x1234:16,er3.l),@-er1 ;01576f3c1234b110 ++ add.w @(0x1234:16,er3.l),@er1+ ;01576f3c12348110 ++ add.w @(0x1234:16,er3.l),@er1- ;01576f3c1234a110 ++ add.w @(0x1234:16,er3.l),@+er1 ;01576f3c12349110 ++ add.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01576f3c1234c1109abc ++ add.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01576f3c1234c9109abcdef0 ++ add.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01576f3c1234d2109abc ++ add.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01576f3c1234e2109abc ++ add.w @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01576f3c1234f2109abc ++ add.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01576f3c1234da109abcdef0 ++ add.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01576f3c1234ea109abcdef0 ++ add.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01576f3c1234fa109abcdef0 ++ add.w @(0x1234:16,er3.l),@0xffff9abc:16 ;01576f3c123440109abc ++ add.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;01576f3c123448109abcdef0 ++ ++ add.w @(0x12345678:32,r3l.b),@er1 ;78356b2c123456780110 ++ add.w @(0x12345678:32,r3l.b),@(6:2,er1) ;78356b2c123456783110 ++ add.w @(0x12345678:32,r3l.b),@-er1 ;78356b2c12345678b110 ++ add.w @(0x12345678:32,r3l.b),@er1+ ;78356b2c123456788110 ++ add.w @(0x12345678:32,r3l.b),@er1- ;78356b2c12345678a110 ++ add.w @(0x12345678:32,r3l.b),@+er1 ;78356b2c123456789110 ++ add.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356b2c12345678c1109abc ++ add.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356b2c12345678c9109abcdef0 ++ add.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356b2c12345678d2109abc ++ add.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356b2c12345678e2109abc ++ add.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356b2c12345678f2109abc ++ add.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356b2c12345678da109abcdef0 ++ add.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356b2c12345678ea109abcdef0 ++ add.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356b2c12345678fa109abcdef0 ++ add.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356b2c1234567840109abc ++ add.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356b2c1234567848109abcdef0 ++ ++ add.w @(0x12345678:32,r3.w),@er1 ;78366b2c123456780110 ++ add.w @(0x12345678:32,r3.w),@(6:2,er1) ;78366b2c123456783110 ++ add.w @(0x12345678:32,r3.w),@-er1 ;78366b2c12345678b110 ++ add.w @(0x12345678:32,r3.w),@er1+ ;78366b2c123456788110 ++ add.w @(0x12345678:32,r3.w),@er1- ;78366b2c12345678a110 ++ add.w @(0x12345678:32,r3.w),@+er1 ;78366b2c123456789110 ++ add.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366b2c12345678c1109abc ++ add.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366b2c12345678c9109abcdef0 ++ add.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366b2c12345678d2109abc ++ add.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366b2c12345678e2109abc ++ add.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366b2c12345678f2109abc ++ add.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366b2c12345678da109abcdef0 ++ add.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366b2c12345678ea109abcdef0 ++ add.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366b2c12345678fa109abcdef0 ++ add.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366b2c1234567840109abc ++ add.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366b2c1234567848109abcdef0 ++ ++ add.w @(0x12345678:32,er3.l),@er1 ;78376b2c123456780110 ++ add.w @(0x12345678:32,er3.l),@(6:2,er1) ;78376b2c123456783110 ++ add.w @(0x12345678:32,er3.l),@-er1 ;78376b2c12345678b110 ++ add.w @(0x12345678:32,er3.l),@er1+ ;78376b2c123456788110 ++ add.w @(0x12345678:32,er3.l),@er1- ;78376b2c12345678a110 ++ add.w @(0x12345678:32,er3.l),@+er1 ;78376b2c123456789110 ++ add.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376b2c12345678c1109abc ++ add.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376b2c12345678c9109abcdef0 ++ add.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376b2c12345678d2109abc ++ add.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376b2c12345678e2109abc ++ add.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376b2c12345678f2109abc ++ add.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376b2c12345678da109abcdef0 ++ add.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376b2c12345678ea109abcdef0 ++ add.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376b2c12345678fa109abcdef0 ++ add.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376b2c1234567840109abc ++ add.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376b2c1234567848109abcdef0 ++ ++ add.w @0x1234:16,@er1 ;6b1512340110 ++ add.w @0x1234:16,@(6:2,er1) ;6b1512343110 ++ add.w @0x1234:16,@-er1 ;6b151234b110 ++ add.w @0x1234:16,@er1+ ;6b1512348110 ++ add.w @0x1234:16,@er1- ;6b151234a110 ++ add.w @0x1234:16,@+er1 ;6b1512349110 ++ add.w @0x1234:16,@(0xffff9abc:16,er1) ;6b151234c1109abc ++ add.w @0x1234:16,@(0x9abcdef0:32,er1) ;6b151234c9109abcdef0 ++ add.w @0x1234:16,@(0xffff9abc:16,r2l.b) ;6b151234d2109abc ++ add.w @0x1234:16,@(0xffff9abc:16,r2.w) ;6b151234e2109abc ++ add.w @0x1234:16,@(0xffff9abc:16,er2.l) ;6b151234f2109abc ++ add.w @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6b151234da109abcdef0 ++ add.w @0x1234:16,@(0x9abcdef0:32,r2.w) ;6b151234ea109abcdef0 ++ add.w @0x1234:16,@(0x9abcdef0:32,er2.l) ;6b151234fa109abcdef0 ++ add.w @0x1234:16,@0xffff9abc:16 ;6b15123440109abc ++ add.w @0x1234:16,@0x9abcdef0:32 ;6b15123448109abcdef0 ++ ++ add.w @0x12345678:32,@er1 ;6b35123456780110 ++ add.w @0x12345678:32,@(6:2,er1) ;6b35123456783110 ++ add.w @0x12345678:32,@-er1 ;6b3512345678b110 ++ add.w @0x12345678:32,@er1+ ;6b35123456788110 ++ add.w @0x12345678:32,@er1- ;6b3512345678a110 ++ add.w @0x12345678:32,@+er1 ;6b35123456789110 ++ add.w @0x12345678:32,@(0xffff9abc:16,er1) ;6b3512345678c1109abc ++ add.w @0x12345678:32,@(0x9abcdef0:32,er1) ;6b3512345678c9109abcdef0 ++ add.w @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6b3512345678d2109abc ++ add.w @0x12345678:32,@(0xffff9abc:16,r2.w) ;6b3512345678e2109abc ++ add.w @0x12345678:32,@(0xffff9abc:16,er2.l) ;6b3512345678f2109abc ++ add.w @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6b3512345678da109abcdef0 ++ add.w @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6b3512345678ea109abcdef0 ++ add.w @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6b3512345678fa109abcdef0 ++ add.w @0x12345678:32,@0xffff9abc:16 ;6b351234567840109abc ++ add.w @0x12345678:32,@0x9abcdef0:32 ;6b351234567848109abcdef0 ++ ++ add.l #0x12345678:32,er1 ;7a1112345678 ++ add.l #0x1234:16,er1 ;7a191234 ++ add.l #0x7:3,er2 ;0afa ++ add.l #0x12345678:32,@er1 ;010e011812345678 ++ add.l #0x12345678:32,@(0xc:2,er1) ;010e311812345678 ++ add.l #0x12345678:32,@er1+ ;010e811812345678 ++ add.l #0x12345678:32,@-er1 ;010eb11812345678 ++ add.l #0x12345678:32,@+er1 ;010e911812345678 ++ add.l #0x12345678:32,@er1- ;010ea11812345678 ++ add.l #0x12345678:32,@(0xffff9abc:16,er1) ;010ec1189abc12345678 ++ add.l #0x12345678:32,@(0x9abcdef0:32,er1) ;010ec9189abcdef012345678 ++ add.l #0x12345678:32,@(0xffff9abc:16,r2l.b) ;010ed2189abc12345678 ++ add.l #0x12345678:32,@(0xffff9abc:16,r2.w) ;010ee2189abc12345678 ++ add.l #0x12345678:32,@(0xffff9abc:16,er2.l) ;010ef2189abc12345678 ++ add.l #0x12345678:32,@(0x9abcdef0:32,r2l.b) ;010eda189abcdef012345678 ++ add.l #0x12345678:32,@(0x9abcdef0:32,r2.w) ;010eea189abcdef012345678 ++ add.l #0x12345678:32,@(0x9abcdef0:32,er2.l) ;010efa189abcdef012345678 ++ add.l #0x12345678:32,@0xffff9abc:16 ;010e40189abc12345678 ++ add.l #0x12345678:32,@0x9abcdef0:32 ;010e48189abcdef012345678 ++ add.l #0x1234:16,@er1 ;010e01101234 ++ add.l #0x1234:16,@(0xc:2,er1) ;010e31101234 ++ add.l #0x1234:16,@er1+ ;010e81101234 ++ add.l #0x1234:16,@-er1 ;010eb1101234 ++ add.l #0x1234:16,@+er1 ;010e91101234 ++ add.l #0x1234:16,@er1- ;010ea1101234 ++ add.l #0x1234:16,@(0xffff9abc:16,er1) ;010ec1109abc1234 ++ add.l #0x1234:16,@(0x9abcdef0:32,er1) ;010ec9109abcdef01234 ++ add.l #0x1234:16,@(0xffff9abc:16,r2l.b) ;010ed2109abc1234 ++ add.l #0x1234:16,@(0xffff9abc:16,r2.w) ;010ee2109abc1234 ++ add.l #0x1234:16,@(0xffff9abc:16,er2.l) ;010ef2109abc1234 ++ add.l #0x1234:16,@(0x9abcdef0:32,r2l.b) ;010eda109abcdef01234 ++ add.l #0x1234:16,@(0x9abcdef0:32,r2.w) ;010eea109abcdef01234 ++ add.l #0x1234:16,@(0x9abcdef0:32,er2.l) ;010efa109abcdef01234 ++ add.l #0x1234:16,@0xffff9abc:16 ;010e40109abc1234 ++ add.l #0x1234:16,@0x9abcdef0:32 ;010e48109abcdef01234 ++ ++ add.l er3,er1 ;0ab1 ++ ++ add.l er3,@er1 ;01090113 ++ add.l er3,@(0xc:2,er1) ;01093113 ++ add.l er3,@er1+ ;01098113 ++ add.l er3,@-er1 ;0109b113 ++ add.l er3,@+er1 ;01099113 ++ add.l er3,@er1- ;0109a113 ++ add.l er3,@(0x1234:16,er1) ;0109c1131234 ++ add.l er3,@(0x12345678:32,er1) ;0109c91312345678 ++ add.l er3,@(0x1234:16,r2l.b) ;0109d2131234 ++ add.l er3,@(0x1234:16,r2.w) ;0109e2131234 ++ add.l er3,@(0x1234:16,er2.l) ;0109f2131234 ++ add.l er3,@(0x12345678:32,r2l.b) ;0109da1312345678 ++ add.l er3,@(0x12345678:32,r2.w) ;0109ea1312345678 ++ add.l er3,@(0x12345678:32,er2.l) ;0109fa1312345678 ++ add.l er3,@0x1234:16 ;010940131234 ++ add.l er3,@0x12345678:32 ;0109481312345678 ++ ++ add.l @er3,er1 ;010a0311 ++ add.l @(0xc:2,er3),er1 ;010a3311 ++ add.l @er3+,er1 ;010a8311 ++ add.l @-er3,er1 ;010ab311 ++ add.l @+er3,er1 ;010a9311 ++ add.l @er3-,er1 ;010aa311 ++ add.l @(0x1234:16,er1),er1 ;010ac1111234 ++ add.l @(0x12345678:32,er1),er1 ;010ac91112345678 ++ add.l @(0x1234:16,r2l.b),er1 ;010ad2111234 ++ add.l @(0x1234:16,r2.w),er1 ;010ae2111234 ++ add.l @(0x1234:16,er2.l),er1 ;010af2111234 ++ add.l @(0x12345678:32,r2l.b),er1 ;010ada1112345678 ++ add.l @(0x12345678:32,r2.w),er1 ;010aea1112345678 ++ add.l @(0x12345678:32,er2.l),er1 ;010afa1112345678 ++ add.l @0x1234:16,er1 ;010a40111234 ++ add.l @0x12345678:32,er1 ;010a481112345678 ++ ++ add.l @er3,@er1 ;0104693c0110 ++ add.l @er3,@(0xc:2,er1) ;0104693c3110 ++ add.l @er3,@-er1 ;0104693cb110 ++ add.l @er3,@er1+ ;0104693c8110 ++ add.l @er3,@er1- ;0104693ca110 ++ add.l @er3,@+er1 ;0104693c9110 ++ add.l @er3,@(0xffff9abc:16,er1) ;0104693cc1109abc ++ add.l @er3,@(0x9abcdef0:32,er1) ;0104693cc9109abcdef0 ++ add.l @er3,@(0xffff9abc:16,r2l.b) ;0104693cd2109abc ++ add.l @er3,@(0xffff9abc:16,r2.w) ;0104693ce2109abc ++ add.l @er3,@(0xffff9abc:16,er2.l) ;0104693cf2109abc ++ add.l @er3,@(0x9abcdef0:32,r2l.b) ;0104693cda109abcdef0 ++ add.l @er3,@(0x9abcdef0:32,r2.w) ;0104693cea109abcdef0 ++ add.l @er3,@(0x9abcdef0:32,er2.l) ;0104693cfa109abcdef0 ++ add.l @er3,@0xffff9abc:16 ;0104693c40109abc ++ add.l @er3,@0x9abcdef0:32 ;0104693c48109abcdef0 ++ ++ add.l @(0xc:2,er3),@er1 ;0107693c0110 ++ add.l @(0xc:2,er3),@(0xc:2,er1) ;0107693c3110 ++ add.l @(0xc:2,er3),@-er1 ;0107693cb110 ++ add.l @(0xc:2,er3),@er1+ ;0107693c8110 ++ add.l @(0xc:2,er3),@er1- ;0107693ca110 ++ add.l @(0xc:2,er3),@+er1 ;0107693c9110 ++ add.l @(0xc:2,er3),@(0xffff9abc:16,er1) ;0107693cc1109abc ++ add.l @(0xc:2,er3),@(0x9abcdef0:32,er1) ;0107693cc9109abcdef0 ++ add.l @(0xc:2,er3),@(0xffff9abc:16,r2l.b) ;0107693cd2109abc ++ add.l @(0xc:2,er3),@(0xffff9abc:16,r2.w) ;0107693ce2109abc ++ add.l @(0xc:2,er3),@(0xffff9abc:16,er2.l) ;0107693cf2109abc ++ add.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b) ;0107693cda109abcdef0 ++ add.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w) ;0107693cea109abcdef0 ++ add.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l) ;0107693cfa109abcdef0 ++ add.l @(0xc:2,er3),@0xffff9abc:16 ;0107693c40109abc ++ add.l @(0xc:2,er3),@0x9abcdef0:32 ;0107693c48109abcdef0 ++ ++ add.l @-er3,@er1 ;01076d3c0110 ++ add.l @-er3,@(0xc:2,er1) ;01076d3c3110 ++ add.l @-er3,@-er1 ;01076d3cb110 ++ add.l @-er3,@er1+ ;01076d3c8110 ++ add.l @-er3,@er1- ;01076d3ca110 ++ add.l @-er3,@+er1 ;01076d3c9110 ++ add.l @-er3,@(0xffff9abc:16,er1) ;01076d3cc1109abc ++ add.l @-er3,@(0x9abcdef0:32,er1) ;01076d3cc9109abcdef0 ++ add.l @-er3,@(0xffff9abc:16,r2l.b) ;01076d3cd2109abc ++ add.l @-er3,@(0xffff9abc:16,r2.w) ;01076d3ce2109abc ++ add.l @-er3,@(0xffff9abc:16,er2.l) ;01076d3cf2109abc ++ add.l @-er3,@(0x9abcdef0:32,r2l.b) ;01076d3cda109abcdef0 ++ add.l @-er3,@(0x9abcdef0:32,r2.w) ;01076d3cea109abcdef0 ++ add.l @-er3,@(0x9abcdef0:32,er2.l) ;01076d3cfa109abcdef0 ++ add.l @-er3,@0xffff9abc:16 ;01076d3c40109abc ++ add.l @-er3,@0x9abcdef0:32 ;01076d3c48109abcdef0 ++ ++ add.l @er3+,@er1 ;01046d3c0110 ++ add.l @er3+,@(0xc:2,er1) ;01046d3c3110 ++ add.l @er3+,@-er1 ;01046d3cb110 ++ add.l @er3+,@er1+ ;01046d3c8110 ++ add.l @er3+,@er1- ;01046d3ca110 ++ add.l @er3+,@+er1 ;01046d3c9110 ++ add.l @er3+,@(0xffff9abc:16,er1) ;01046d3cc1109abc ++ add.l @er3+,@(0x9abcdef0:32,er1) ;01046d3cc9109abcdef0 ++ add.l @er3+,@(0xffff9abc:16,r2l.b) ;01046d3cd2109abc ++ add.l @er3+,@(0xffff9abc:16,r2.w) ;01046d3ce2109abc ++ add.l @er3+,@(0xffff9abc:16,er2.l) ;01046d3cf2109abc ++ add.l @er3+,@(0x9abcdef0:32,r2l.b) ;01046d3cda109abcdef0 ++ add.l @er3+,@(0x9abcdef0:32,r2.w) ;01046d3cea109abcdef0 ++ add.l @er3+,@(0x9abcdef0:32,er2.l) ;01046d3cfa109abcdef0 ++ add.l @er3+,@0xffff9abc:16 ;01046d3c40109abc ++ add.l @er3+,@0x9abcdef0:32 ;01046d3c48109abcdef0 ++ ++ add.l @er3-,@er1 ;01066d3c0110 ++ add.l @er3-,@(0xc:2,er1) ;01066d3c3110 ++ add.l @er3-,@-er1 ;01066d3cb110 ++ add.l @er3-,@er1+ ;01066d3c8110 ++ add.l @er3-,@er1- ;01066d3ca110 ++ add.l @er3-,@+er1 ;01066d3c9110 ++ add.l @er3-,@(0xffff9abc:16,er1) ;01066d3cc1109abc ++ add.l @er3-,@(0x9abcdef0:32,er1) ;01066d3cc9109abcdef0 ++ add.l @er3-,@(0xffff9abc:16,r2l.b) ;01066d3cd2109abc ++ add.l @er3-,@(0xffff9abc:16,r2.w) ;01066d3ce2109abc ++ add.l @er3-,@(0xffff9abc:16,er2.l) ;01066d3cf2109abc ++ add.l @er3-,@(0x9abcdef0:32,r2l.b) ;01066d3cda109abcdef0 ++ add.l @er3-,@(0x9abcdef0:32,r2.w) ;01066d3cea109abcdef0 ++ add.l @er3-,@(0x9abcdef0:32,er2.l) ;01066d3cfa109abcdef0 ++ add.l @er3-,@0xffff9abc:16 ;01066d3c40109abc ++ add.l @er3-,@0x9abcdef0:32 ;01066d3c48109abcdef0 ++ ++ add.l @+er3,@er1 ;01056d3c0110 ++ add.l @+er3,@(0xc:2,er1) ;01056d3c3110 ++ add.l @+er3,@-er1 ;01056d3cb110 ++ add.l @+er3,@er1+ ;01056d3c8110 ++ add.l @+er3,@er1- ;01056d3ca110 ++ add.l @+er3,@+er1 ;01056d3c9110 ++ add.l @+er3,@(0xffff9abc:16,er1) ;01056d3cc1109abc ++ add.l @+er3,@(0x9abcdef0:32,er1) ;01056d3cc9109abcdef0 ++ add.l @+er3,@(0xffff9abc:16,r2l.b) ;01056d3cd2109abc ++ add.l @+er3,@(0xffff9abc:16,r2.w) ;01056d3ce2109abc ++ add.l @+er3,@(0xffff9abc:16,er2.l) ;01056d3cf2109abc ++ add.l @+er3,@(0x9abcdef0:32,r2l.b) ;01056d3cda109abcdef0 ++ add.l @+er3,@(0x9abcdef0:32,r2.w) ;01056d3cea109abcdef0 ++ add.l @+er3,@(0x9abcdef0:32,er2.l) ;01056d3cfa109abcdef0 ++ add.l @+er3,@0xffff9abc:16 ;01056d3c40109abc ++ add.l @+er3,@0x9abcdef0:32 ;01056d3c48109abcdef0 ++ ++ add.l @(0x1234:16,er3),@er1 ;01046f3c12340110 ++ add.l @(0x1234:16,er3),@(0xc:2,er1) ;01046f3c12343110 ++ add.l @(0x1234:16,er3),@-er1 ;01046f3c1234b110 ++ add.l @(0x1234:16,er3),@er1+ ;01046f3c12348110 ++ add.l @(0x1234:16,er3),@er1- ;01046f3c1234a110 ++ add.l @(0x1234:16,er3),@+er1 ;01046f3c12349110 ++ add.l @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01046f3c1234c1109abc ++ add.l @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01046f3c1234c9109abcdef0 ++ add.l @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01046f3c1234d2109abc ++ add.l @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01046f3c1234e2109abc ++ add.l @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01046f3c1234f2109abc ++ add.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01046f3c1234da109abcdef0 ++ add.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01046f3c1234ea109abcdef0 ++ add.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01046f3c1234fa109abcdef0 ++ add.l @(0x1234:16,er3),@0xffff9abc:16 ;01046f3c123440109abc ++ add.l @(0x1234:16,er3),@0x9abcdef0:32 ;01046f3c123448109abcdef0 ++ ++ add.l @(0x12345678:32,er3),@er1 ;78b46b2c123456780110 ++ add.l @(0x12345678:32,er3),@(0xc:2,er1) ;78b46b2c123456783110 ++ add.l @(0x12345678:32,er3),@-er1 ;78b46b2c12345678b110 ++ add.l @(0x12345678:32,er3),@er1+ ;78b46b2c123456788110 ++ add.l @(0x12345678:32,er3),@er1- ;78b46b2c12345678a110 ++ add.l @(0x12345678:32,er3),@+er1 ;78b46b2c123456789110 ++ add.l @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78b46b2c12345678c1109abc ++ add.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78b46b2c12345678c9109abcdef0 ++ add.l @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78b46b2c12345678d2109abc ++ add.l @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78b46b2c12345678e2109abc ++ add.l @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78b46b2c12345678f2109abc ++ add.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78b46b2c12345678da109abcdef0 ++ add.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78b46b2c12345678ea109abcdef0 ++ add.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78b46b2c12345678fa109abcdef0 ++ add.l @(0x12345678:32,er3),@0xffff9abc:16 ;78b46b2c1234567840109abc ++ add.l @(0x12345678:32,er3),@0x9abcdef0:32 ;78b46b2c1234567848109abcdef0 ++ ++ add.l @(0x1234:16,r3l.b),@er1 ;01056f3c12340110 ++ add.l @(0x1234:16,r3l.b),@(0xc:2,er1) ;01056f3c12343110 ++ add.l @(0x1234:16,r3l.b),@-er1 ;01056f3c1234b110 ++ add.l @(0x1234:16,r3l.b),@er1+ ;01056f3c12348110 ++ add.l @(0x1234:16,r3l.b),@er1- ;01056f3c1234a110 ++ add.l @(0x1234:16,r3l.b),@+er1 ;01056f3c12349110 ++ add.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01056f3c1234c1109abc ++ add.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01056f3c1234c9109abcdef0 ++ add.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01056f3c1234d2109abc ++ add.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01056f3c1234e2109abc ++ add.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01056f3c1234f2109abc ++ add.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01056f3c1234da109abcdef0 ++ add.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01056f3c1234ea109abcdef0 ++ add.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01056f3c1234fa109abcdef0 ++ add.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;01056f3c123440109abc ++ add.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01056f3c123448109abcdef0 ++ ++ add.l @(0x1234:16,r3.w),@er1 ;01066f3c12340110 ++ add.l @(0x1234:16,r3.w),@(0xc:2,er1) ;01066f3c12343110 ++ add.l @(0x1234:16,r3.w),@-er1 ;01066f3c1234b110 ++ add.l @(0x1234:16,r3.w),@er1+ ;01066f3c12348110 ++ add.l @(0x1234:16,r3.w),@er1- ;01066f3c1234a110 ++ add.l @(0x1234:16,r3.w),@+er1 ;01066f3c12349110 ++ add.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01066f3c1234c1109abc ++ add.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01066f3c1234c9109abcdef0 ++ add.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01066f3c1234d2109abc ++ add.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01066f3c1234e2109abc ++ add.l @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01066f3c1234f2109abc ++ add.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01066f3c1234da109abcdef0 ++ add.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01066f3c1234ea109abcdef0 ++ add.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01066f3c1234fa109abcdef0 ++ add.l @(0x1234:16,r3.w),@0xffff9abc:16 ;01066f3c123440109abc ++ add.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;01066f3c123448109abcdef0 ++ ++ add.l @(0x1234:16,er3.l),@er1 ;01076f3c12340110 ++ add.l @(0x1234:16,er3.l),@(0xc:2,er1) ;01076f3c12343110 ++ add.l @(0x1234:16,er3.l),@-er1 ;01076f3c1234b110 ++ add.l @(0x1234:16,er3.l),@er1+ ;01076f3c12348110 ++ add.l @(0x1234:16,er3.l),@er1- ;01076f3c1234a110 ++ add.l @(0x1234:16,er3.l),@+er1 ;01076f3c12349110 ++ add.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01076f3c1234c1109abc ++ add.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01076f3c1234c9109abcdef0 ++ add.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01076f3c1234d2109abc ++ add.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01076f3c1234e2109abc ++ add.l @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01076f3c1234f2109abc ++ add.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01076f3c1234da109abcdef0 ++ add.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01076f3c1234ea109abcdef0 ++ add.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01076f3c1234fa109abcdef0 ++ add.l @(0x1234:16,er3.l),@0xffff9abc:16 ;01076f3c123440109abc ++ add.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;01076f3c123448109abcdef0 ++ ++ add.l @(0x12345678:32,r3l.b),@er1 ;78b56b2c123456780110 ++ add.l @(0x12345678:32,r3l.b),@(0xc:2,er1) ;78b56b2c123456783110 ++ add.l @(0x12345678:32,r3l.b),@-er1 ;78b56b2c12345678b110 ++ add.l @(0x12345678:32,r3l.b),@er1+ ;78b56b2c123456788110 ++ add.l @(0x12345678:32,r3l.b),@er1- ;78b56b2c12345678a110 ++ add.l @(0x12345678:32,r3l.b),@+er1 ;78b56b2c123456789110 ++ add.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78b56b2c12345678c1109abc ++ add.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78b56b2c12345678c9109abcdef0 ++ add.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78b56b2c12345678d2109abc ++ add.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78b56b2c12345678e2109abc ++ add.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78b56b2c12345678f2109abc ++ add.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78b56b2c12345678da109abcdef0 ++ add.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78b56b2c12345678ea109abcdef0 ++ add.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78b56b2c12345678fa109abcdef0 ++ add.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78b56b2c1234567840109abc ++ add.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78b56b2c1234567848109abcdef0 ++ ++ add.l @(0x12345678:32,r3.w),@er1 ;78b66b2c123456780110 ++ add.l @(0x12345678:32,r3.w),@(0xc:2,er1) ;78b66b2c123456783110 ++ add.l @(0x12345678:32,r3.w),@-er1 ;78b66b2c12345678b110 ++ add.l @(0x12345678:32,r3.w),@er1+ ;78b66b2c123456788110 ++ add.l @(0x12345678:32,r3.w),@er1- ;78b66b2c12345678a110 ++ add.l @(0x12345678:32,r3.w),@+er1 ;78b66b2c123456789110 ++ add.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78b66b2c12345678c1109abc ++ add.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78b66b2c12345678c9109abcdef0 ++ add.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78b66b2c12345678d2109abc ++ add.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78b66b2c12345678e2109abc ++ add.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78b66b2c12345678f2109abc ++ add.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78b66b2c12345678da109abcdef0 ++ add.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78b66b2c12345678ea109abcdef0 ++ add.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78b66b2c12345678fa109abcdef0 ++ add.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;78b66b2c1234567840109abc ++ add.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78b66b2c1234567848109abcdef0 ++ ++ add.l @(0x12345678:32,er3.l),@er1 ;78b76b2c123456780110 ++ add.l @(0x12345678:32,er3.l),@(0xc:2,er1) ;78b76b2c123456783110 ++ add.l @(0x12345678:32,er3.l),@-er1 ;78b76b2c12345678b110 ++ add.l @(0x12345678:32,er3.l),@er1+ ;78b76b2c123456788110 ++ add.l @(0x12345678:32,er3.l),@er1- ;78b76b2c12345678a110 ++ add.l @(0x12345678:32,er3.l),@+er1 ;78b76b2c123456789110 ++ add.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78b76b2c12345678c1109abc ++ add.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78b76b2c12345678c9109abcdef0 ++ add.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78b76b2c12345678d2109abc ++ add.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78b76b2c12345678e2109abc ++ add.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78b76b2c12345678f2109abc ++ add.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78b76b2c12345678da109abcdef0 ++ add.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78b76b2c12345678ea109abcdef0 ++ add.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78b76b2c12345678fa109abcdef0 ++ add.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;78b76b2c1234567840109abc ++ add.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78b76b2c1234567848109abcdef0 ++ ++ add.l @0x1234:16,@er1 ;01046b0c12340110 ++ add.l @0x1234:16,@(0xc:2,er1) ;01046b0c12343110 ++ add.l @0x1234:16,@-er1 ;01046b0c1234b110 ++ add.l @0x1234:16,@er1+ ;01046b0c12348110 ++ add.l @0x1234:16,@er1- ;01046b0c1234a110 ++ add.l @0x1234:16,@+er1 ;01046b0c12349110 ++ add.l @0x1234:16,@(0xffff9abc:16,er1) ;01046b0c1234c1109abc ++ add.l @0x1234:16,@(0x9abcdef0:32,er1) ;01046b0c1234c9109abcdef0 ++ add.l @0x1234:16,@(0xffff9abc:16,r2l.b) ;01046b0c1234d2109abc ++ add.l @0x1234:16,@(0xffff9abc:16,r2.w) ;01046b0c1234e2109abc ++ add.l @0x1234:16,@(0xffff9abc:16,er2.l) ;01046b0c1234f2109abc ++ add.l @0x1234:16,@(0x9abcdef0:32,r2l.b) ;01046b0c1234da109abcdef0 ++ add.l @0x1234:16,@(0x9abcdef0:32,r2.w) ;01046b0c1234ea109abcdef0 ++ add.l @0x1234:16,@(0x9abcdef0:32,er2.l) ;01046b0c1234fa109abcdef0 ++ add.l @0x1234:16,@0xffff9abc:16 ;01046b0c123440109abc ++ add.l @0x1234:16,@0x9abcdef0:32 ;01046b0c123448109abcdef0 ++ ++ add.l @0x12345678:32,@er1 ;01046b2c123456780110 ++ add.l @0x12345678:32,@(0xc:2,er1) ;01046b2c123456783110 ++ add.l @0x12345678:32,@-er1 ;01046b2c12345678b110 ++ add.l @0x12345678:32,@er1+ ;01046b2c123456788110 ++ add.l @0x12345678:32,@er1- ;01046b2c12345678a110 ++ add.l @0x12345678:32,@+er1 ;01046b2c123456789110 ++ add.l @0x12345678:32,@(0xffff9abc:16,er1) ;01046b2c12345678c1109abc ++ add.l @0x12345678:32,@(0x9abcdef0:32,er1) ;01046b2c12345678c9109abcdef0 ++ add.l @0x12345678:32,@(0xffff9abc:16,r2l.b) ;01046b2c12345678d2109abc ++ add.l @0x12345678:32,@(0xffff9abc:16,r2.w) ;01046b2c12345678e2109abc ++ add.l @0x12345678:32,@(0xffff9abc:16,er2.l) ;01046b2c12345678f2109abc ++ add.l @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;01046b2c12345678da109abcdef0 ++ add.l @0x12345678:32,@(0x9abcdef0:32,r2.w) ;01046b2c12345678ea109abcdef0 ++ add.l @0x12345678:32,@(0x9abcdef0:32,er2.l) ;01046b2c12345678fa109abcdef0 ++ add.l @0x12345678:32,@0xffff9abc:16 ;01046b2c1234567840109abc ++ add.l @0x12345678:32,@0x9abcdef0:32 ;01046b2c1234567848109abcdef0 ++ ++ .end diff --git a/gas/testsuite/gas/h8300/t04_sub.exp b/gas/testsuite/gas/h8300/t04_sub.exp new file mode 100644 -index 0000000..455931e +index 0000000..50bd31b --- /dev/null +++ b/gas/testsuite/gas/h8300/t04_sub.exp -@@ -0,0 +1,3037 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,3036 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1162642,994 +1169820,993 @@ index 0000000..455931e + diff --git a/gas/testsuite/gas/h8300/t04_sub.s b/gas/testsuite/gas/h8300/t04_sub.s new file mode 100644 -index 0000000..d9476d3 +index 0000000..c9c064c --- /dev/null +++ b/gas/testsuite/gas/h8300/t04_sub.s @@ -0,0 +1,976 @@ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+;arith_1 -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ .h8300sx -+ .text -+_start: -+ sub.b #0x12:8,@er1 ;7d10a112 -+ sub.b #0x12:8,@(0x3:2,er1) ;01776818a112 -+ sub.b #0x12:8,@er1+ ;01746c18a112 -+ sub.b #0x12:8,@-er1 ;01776c18a112 -+ sub.b #0x12:8,@+er1 ;01756c18a112 -+ sub.b #0x12:8,@er1- ;01766c18a112 -+ sub.b #0x12:8,@(0x1234:16,er1) ;01746e181234a112 -+ sub.b #0x12:8,@(0x12345678:32,er1) ;78146a2812345678a112 -+ sub.b #0x12:8,@(0x1234:16,r2l.b) ;01756e281234a112 -+ sub.b #0x12:8,@(0x1234:16,r2.w) ;01766e281234a112 -+ sub.b #0x12:8,@(0x1234:16,er2.l) ;01776e281234a112 -+ sub.b #0x12:8,@(0x12345678:32,r2l.b) ;78256a2812345678a112 -+ sub.b #0x12:8,@(0x12345678:32,r2.w) ;78266a2812345678a112 -+ sub.b #0x12:8,@(0x12345678:32,er2.l) ;78276a2812345678a112 -+ sub.b #0x12:8,@0xffffff9a:8 ;7f9aa112 -+ sub.b #0x12:8,@0x1234:16 ;6a181234a112 -+ sub.b #0x12:8,@0x12345678:32 ;6a3812345678a112 -+ -+ sub.b r3h,r1h ;1831 -+ -+ sub.b r3h,@er1 ;7d101830 -+ sub.b r3h,@(0x3:2,er1) ;01793133 -+ sub.b r3h,@er1+ ;01798133 -+ sub.b r3h,@-er1 ;0179b133 -+ sub.b r3h,@+er1 ;01799133 -+ sub.b r3h,@er1- ;0179a133 -+ sub.b r3h,@(0x1234:16,er1) ;0179c1331234 -+ sub.b r3h,@(0x12345678:32,er1) ;0179c93312345678 -+ sub.b r3h,@(0x1234:16,r2l.b) ;0179d2331234 -+ sub.b r3h,@(0x1234:16,r2.w) ;0179e2331234 -+ sub.b r3h,@(0x1234:16,er2.l) ;0179f2331234 -+ sub.b r3h,@(0x12345678:32,r2l.b) ;0179da3312345678 -+ sub.b r3h,@(0x12345678:32,r2.w) ;0179ea3312345678 -+ sub.b r3h,@(0x12345678:32,er2.l) ;0179fa3312345678 -+ sub.b r3h,@0xffffff12:8 ;7f121830 -+ sub.b r3h,@0x1234:16 ;6a1812341830 -+ sub.b r3h,@0x12345678:32 ;6a38123456781830 -+ -+ sub.b @er3,r1h ;7c301801 -+ sub.b @(0x3:2,er3),r1h ;017a3331 -+ sub.b @er3+,r1h ;017a8331 -+ sub.b @-er3,r1h ;017ab331 -+ sub.b @+er3,r1h ;017a9331 -+ sub.b @er3-,r1h ;017aa331 -+ sub.b @(0x1234:16,er1),r1h ;017ac1311234 -+ sub.b @(0x12345678:32,er1),r1h ;017ac93112345678 -+ sub.b @(0x1234:16,r2l.b),r1h ;017ad2311234 -+ sub.b @(0x1234:16,r2.w),r1h ;017ae2311234 -+ sub.b @(0x1234:16,er2.l),r1h ;017af2311234 -+ sub.b @(0x12345678:32,r2l.b),r1h ;017ada3112345678 -+ sub.b @(0x12345678:32,r2.w),r1h ;017aea3112345678 -+ sub.b @(0x12345678:32,er2.l),r1h ;017afa3112345678 -+ sub.b @0xffffff12:8,r1h ;7e121801 -+ sub.b @0x1234:16,r1h ;6a1012341801 -+ sub.b @0x12345678:32,r1h ;6a30123456781801 -+ -+ sub.b @er3,@er1 ;7c350130 -+ sub.b @er3,@(3:2,er1) ;7c353130 -+ sub.b @er3,@-er1 ;7c35b130 -+ sub.b @er3,@er1+ ;7c358130 -+ sub.b @er3,@er1- ;7c35a130 -+ sub.b @er3,@+er1 ;7c359130 -+ sub.b @er3,@(0xffff9abc:16,er1) ;7c35c1309abc -+ sub.b @er3,@(0x9abcdef0:32,er1) ;7c35c9309abcdef0 -+ sub.b @er3,@(0xffff9abc:16,r2l.b) ;7c35d2309abc -+ sub.b @er3,@(0xffff9abc:16,r2.w) ;7c35e2309abc -+ sub.b @er3,@(0xffff9abc:16,er2.l) ;7c35f2309abc -+ sub.b @er3,@(0x9abcdef0:32,r2l.b) ;7c35da309abcdef0 -+ sub.b @er3,@(0x9abcdef0:32,r2.w) ;7c35ea309abcdef0 -+ sub.b @er3,@(0x9abcdef0:32,er2.l) ;7c35fa309abcdef0 -+ sub.b @er3,@0xffff9abc:16 ;7c3540309abc -+ sub.b @er3,@0x9abcdef0:32 ;7c3548309abcdef0 -+ -+ sub.b @-er3,@er1 ;01776c3c0130 -+ sub.b @-er3,@(3:2,er1) ;01776c3c3130 -+ sub.b @-er3,@-er1 ;01776c3cb130 -+ sub.b @-er3,@er1+ ;01776c3c8130 -+ sub.b @-er3,@er1- ;01776c3ca130 -+ sub.b @-er3,@+er1 ;01776c3c9130 -+ sub.b @-er3,@(0xffff9abc:16,er1) ;01776c3cc1309abc -+ sub.b @-er3,@(0x9abcdef0:32,er1) ;01776c3cc9309abcdef0 -+ sub.b @-er3,@(0xffff9abc:16,r2l.b) ;01776c3cd2309abc -+ sub.b @-er3,@(0xffff9abc:16,r2.w) ;01776c3ce2309abc -+ sub.b @-er3,@(0xffff9abc:16,er2.l) ;01776c3cf2309abc -+ sub.b @-er3,@(0x9abcdef0:32,r2l.b) ;01776c3cda309abcdef0 -+ sub.b @-er3,@(0x9abcdef0:32,r2.w) ;01776c3cea309abcdef0 -+ sub.b @-er3,@(0x9abcdef0:32,er2.l) ;01776c3cfa309abcdef0 -+ sub.b @-er3,@0xffff9abc:16 ;01776c3c40309abc -+ sub.b @-er3,@0x9abcdef0:32 ;01776c3c48309abcdef0 -+ -+ sub.b @er3+,@er1 ;01746c3c0130 -+ sub.b @er3+,@(3:2,er1) ;01746c3c3130 -+ sub.b @er3+,@-er1 ;01746c3cb130 -+ sub.b @er3+,@er1+ ;01746c3c8130 -+ sub.b @er3+,@er1- ;01746c3ca130 -+ sub.b @er3+,@+er1 ;01746c3c9130 -+ sub.b @er3+,@(0xffff9abc:16,er1) ;01746c3cc1309abc -+ sub.b @er3+,@(0x9abcdef0:32,er1) ;01746c3cc9309abcdef0 -+ sub.b @er3+,@(0xffff9abc:16,r2l.b) ;01746c3cd2309abc -+ sub.b @er3+,@(0xffff9abc:16,r2.w) ;01746c3ce2309abc -+ sub.b @er3+,@(0xffff9abc:16,er2.l) ;01746c3cf2309abc -+ sub.b @er3+,@(0x9abcdef0:32,r2l.b) ;01746c3cda309abcdef0 -+ sub.b @er3+,@(0x9abcdef0:32,r2.w) ;01746c3cea309abcdef0 -+ sub.b @er3+,@(0x9abcdef0:32,er2.l) ;01746c3cfa309abcdef0 -+ sub.b @er3+,@0xffff9abc:16 ;01746c3c40309abc -+ sub.b @er3+,@0x9abcdef0:32 ;01746c3c48309abcdef0 -+ -+ sub.b @er3-,@er1 ;01766c3c0130 -+ sub.b @er3-,@(3:2,er1) ;01766c3c3130 -+ sub.b @er3-,@-er1 ;01766c3cb130 -+ sub.b @er3-,@er1+ ;01766c3c8130 -+ sub.b @er3-,@er1- ;01766c3ca130 -+ sub.b @er3-,@+er1 ;01766c3c9130 -+ sub.b @er3-,@(0xffff9abc:16,er1) ;01766c3cc1309abc -+ sub.b @er3-,@(0x9abcdef0:32,er1) ;01766c3cc9309abcdef0 -+ sub.b @er3-,@(0xffff9abc:16,r2l.b) ;01766c3cd2309abc -+ sub.b @er3-,@(0xffff9abc:16,r2.w) ;01766c3ce2309abc -+ sub.b @er3-,@(0xffff9abc:16,er2.l) ;01766c3cf2309abc -+ sub.b @er3-,@(0x9abcdef0:32,r2l.b) ;01766c3cda309abcdef0 -+ sub.b @er3-,@(0x9abcdef0:32,r2.w) ;01766c3cea309abcdef0 -+ sub.b @er3-,@(0x9abcdef0:32,er2.l) ;01766c3cfa309abcdef0 -+ sub.b @er3-,@0xffff9abc:16 ;01766c3c40309abc -+ sub.b @er3-,@0x9abcdef0:32 ;01766c3c48309abcdef0 -+ -+ sub.b @+er3,@er1 ;01756c3c0130 -+ sub.b @+er3,@(3:2,er1) ;01756c3c3130 -+ sub.b @+er3,@-er1 ;01756c3cb130 -+ sub.b @+er3,@er1+ ;01756c3c8130 -+ sub.b @+er3,@er1- ;01756c3ca130 -+ sub.b @+er3,@+er1 ;01756c3c9130 -+ sub.b @+er3,@(0xffff9abc:16,er1) ;01756c3cc1309abc -+ sub.b @+er3,@(0x9abcdef0:32,er1) ;01756c3cc9309abcdef0 -+ sub.b @+er3,@(0xffff9abc:16,r2l.b) ;01756c3cd2309abc -+ sub.b @+er3,@(0xffff9abc:16,r2.w) ;01756c3ce2309abc -+ sub.b @+er3,@(0xffff9abc:16,er2.l) ;01756c3cf2309abc -+ sub.b @+er3,@(0x9abcdef0:32,r2l.b) ;01756c3cda309abcdef0 -+ sub.b @+er3,@(0x9abcdef0:32,r2.w) ;01756c3cea309abcdef0 -+ sub.b @+er3,@(0x9abcdef0:32,er2.l) ;01756c3cfa309abcdef0 -+ sub.b @+er3,@0xffff9abc:16 ;01756c3c40309abc -+ sub.b @+er3,@0x9abcdef0:32 ;01756c3c48309abcdef0 -+ -+ sub.b @(0x1234:16,er3),@er1 ;01746e3c12340130 -+ sub.b @(0x1234:16,er3),@(3:2,er1) ;01746e3c12343130 -+ sub.b @(0x1234:16,er3),@-er1 ;01746e3c1234b130 -+ sub.b @(0x1234:16,er3),@er1+ ;01746e3c12348130 -+ sub.b @(0x1234:16,er3),@er1- ;01746e3c1234a130 -+ sub.b @(0x1234:16,er3),@+er1 ;01746e3c12349130 -+ sub.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01746e3c1234c1309abc -+ sub.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01746e3c1234c9309abcdef0 -+ sub.b @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01746e3c1234d2309abc -+ sub.b @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01746e3c1234e2309abc -+ sub.b @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01746e3c1234f2309abc -+ sub.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01746e3c1234da309abcdef0 -+ sub.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01746e3c1234ea309abcdef0 -+ sub.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01746e3c1234fa309abcdef0 -+ sub.b @(0x1234:16,er3),@0xffff9abc:16 ;01746e3c123440309abc -+ sub.b @(0x1234:16,er3),@0x9abcdef0:32 ;01746e3c123448309abcdef0 -+ -+ sub.b @(0x12345678:32,er3),@er1 ;78346a2c123456780130 -+ sub.b @(0x12345678:32,er3),@(3:2,er1) ;78346a2c123456783130 -+ sub.b @(0x12345678:32,er3),@-er1 ;78346a2c12345678b130 -+ sub.b @(0x12345678:32,er3),@er1+ ;78346a2c123456788130 -+ sub.b @(0x12345678:32,er3),@er1- ;78346a2c12345678a130 -+ sub.b @(0x12345678:32,er3),@+er1 ;78346a2c123456789130 -+ sub.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346a2c12345678c1309abc -+ sub.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346a2c12345678c9309abcdef0 -+ sub.b @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346a2c12345678d2309abc -+ sub.b @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346a2c12345678e2309abc -+ sub.b @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346a2c12345678f2309abc -+ sub.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346a2c12345678da309abcdef0 -+ sub.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346a2c12345678ea309abcdef0 -+ sub.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346a2c12345678fa309abcdef0 -+ sub.b @(0x12345678:32,er3),@0xffff9abc:16 ;78346a2c1234567840309abc -+ sub.b @(0x12345678:32,er3),@0x9abcdef0:32 ;78346a2c1234567848309abcdef0 -+ -+ sub.b @(0x1234:16,r3l.b),@er1 ;01756e3c12340130 -+ sub.b @(0x1234:16,r3l.b),@(3:2,er1) ;01756e3c12343130 -+ sub.b @(0x1234:16,r3l.b),@-er1 ;01756e3c1234b130 -+ sub.b @(0x1234:16,r3l.b),@er1+ ;01756e3c12348130 -+ sub.b @(0x1234:16,r3l.b),@er1- ;01756e3c1234a130 -+ sub.b @(0x1234:16,r3l.b),@+er1 ;01756e3c12349130 -+ sub.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01756e3c1234c1309abc -+ sub.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01756e3c1234c9309abcdef0 -+ sub.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01756e3c1234d2309abc -+ sub.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01756e3c1234e2309abc -+ sub.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01756e3c1234f2309abc -+ sub.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01756e3c1234da309abcdef0 -+ sub.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01756e3c1234ea309abcdef0 -+ sub.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01756e3c1234fa309abcdef0 -+ sub.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;01756e3c123440309abc -+ sub.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01756e3c123448309abcdef0 -+ -+ sub.b @(0x1234:16,r3.w),@er1 ;01766e3c12340130 -+ sub.b @(0x1234:16,r3.w),@(3:2,er1) ;01766e3c12343130 -+ sub.b @(0x1234:16,r3.w),@-er1 ;01766e3c1234b130 -+ sub.b @(0x1234:16,r3.w),@er1+ ;01766e3c12348130 -+ sub.b @(0x1234:16,r3.w),@er1- ;01766e3c1234a130 -+ sub.b @(0x1234:16,r3.w),@+er1 ;01766e3c12349130 -+ sub.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01766e3c1234c1309abc -+ sub.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01766e3c1234c9309abcdef0 -+ sub.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01766e3c1234d2309abc -+ sub.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01766e3c1234e2309abc -+ sub.b @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01766e3c1234f2309abc -+ sub.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01766e3c1234da309abcdef0 -+ sub.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01766e3c1234ea309abcdef0 -+ sub.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01766e3c1234fa309abcdef0 -+ sub.b @(0x1234:16,r3.w),@0xffff9abc:16 ;01766e3c123440309abc -+ sub.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;01766e3c123448309abcdef0 -+ -+ sub.b @(0x1234:16,er3.l),@er1 ;01776e3c12340130 -+ sub.b @(0x1234:16,er3.l),@(3:2,er1) ;01776e3c12343130 -+ sub.b @(0x1234:16,er3.l),@-er1 ;01776e3c1234b130 -+ sub.b @(0x1234:16,er3.l),@er1+ ;01776e3c12348130 -+ sub.b @(0x1234:16,er3.l),@er1- ;01776e3c1234a130 -+ sub.b @(0x1234:16,er3.l),@+er1 ;01776e3c12349130 -+ sub.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01776e3c1234c1309abc -+ sub.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01776e3c1234c9309abcdef0 -+ sub.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01776e3c1234d2309abc -+ sub.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01776e3c1234e2309abc -+ sub.b @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01776e3c1234f2309abc -+ sub.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01776e3c1234da309abcdef0 -+ sub.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01776e3c1234ea309abcdef0 -+ sub.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01776e3c1234fa309abcdef0 -+ sub.b @(0x1234:16,er3.l),@0xffff9abc:16 ;01776e3c123440309abc -+ sub.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;01776e3c123448309abcdef0 -+ -+ sub.b @(0x12345678:32,r3l.b),@er1 ;78356a2c123456780130 -+ sub.b @(0x12345678:32,r3l.b),@(3:2,er1) ;78356a2c123456783130 -+ sub.b @(0x12345678:32,r3l.b),@-er1 ;78356a2c12345678b130 -+ sub.b @(0x12345678:32,r3l.b),@er1+ ;78356a2c123456788130 -+ sub.b @(0x12345678:32,r3l.b),@er1- ;78356a2c12345678a130 -+ sub.b @(0x12345678:32,r3l.b),@+er1 ;78356a2c123456789130 -+ sub.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356a2c12345678c1309abc -+ sub.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356a2c12345678c9309abcdef0 -+ sub.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356a2c12345678d2309abc -+ sub.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356a2c12345678e2309abc -+ sub.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356a2c12345678f2309abc -+ sub.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356a2c12345678da309abcdef0 -+ sub.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356a2c12345678ea309abcdef0 -+ sub.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356a2c12345678fa309abcdef0 -+ sub.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356a2c1234567840309abc -+ sub.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356a2c1234567848309abcdef0 -+ -+ sub.b @(0x12345678:32,r3.w),@er1 ;78366a2c123456780130 -+ sub.b @(0x12345678:32,r3.w),@(3:2,er1) ;78366a2c123456783130 -+ sub.b @(0x12345678:32,r3.w),@-er1 ;78366a2c12345678b130 -+ sub.b @(0x12345678:32,r3.w),@er1+ ;78366a2c123456788130 -+ sub.b @(0x12345678:32,r3.w),@er1- ;78366a2c12345678a130 -+ sub.b @(0x12345678:32,r3.w),@+er1 ;78366a2c123456789130 -+ sub.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366a2c12345678c1309abc -+ sub.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366a2c12345678c9309abcdef0 -+ sub.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366a2c12345678d2309abc -+ sub.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366a2c12345678e2309abc -+ sub.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366a2c12345678f2309abc -+ sub.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366a2c12345678da309abcdef0 -+ sub.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366a2c12345678ea309abcdef0 -+ sub.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366a2c12345678fa309abcdef0 -+ sub.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366a2c1234567840309abc -+ sub.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366a2c1234567848309abcdef0 -+ -+ sub.b @(0x12345678:32,er3.l),@er1 ;78376a2c123456780130 -+ sub.b @(0x12345678:32,er3.l),@(3:2,er1) ;78376a2c123456783130 -+ sub.b @(0x12345678:32,er3.l),@-er1 ;78376a2c12345678b130 -+ sub.b @(0x12345678:32,er3.l),@er1+ ;78376a2c123456788130 -+ sub.b @(0x12345678:32,er3.l),@er1- ;78376a2c12345678a130 -+ sub.b @(0x12345678:32,er3.l),@+er1 ;78376a2c123456789130 -+ sub.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376a2c12345678c1309abc -+ sub.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376a2c12345678c9309abcdef0 -+ sub.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376a2c12345678d2309abc -+ sub.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376a2c12345678e2309abc -+ sub.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376a2c12345678f2309abc -+ sub.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376a2c12345678da309abcdef0 -+ sub.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376a2c12345678ea309abcdef0 -+ sub.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376a2c12345678fa309abcdef0 -+ sub.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376a2c1234567840309abc -+ sub.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376a2c1234567848309abcdef0 -+ -+ sub.b @0x1234:16,@er1 ;6a1512340130 -+ sub.b @0x1234:16,@(3:2,er1) ;6a1512343130 -+ sub.b @0x1234:16,@-er1 ;6a151234b130 -+ sub.b @0x1234:16,@er1+ ;6a1512348130 -+ sub.b @0x1234:16,@er1- ;6a151234a130 -+ sub.b @0x1234:16,@+er1 ;6a1512349130 -+ sub.b @0x1234:16,@(0xffff9abc:16,er1) ;6a151234c1309abc -+ sub.b @0x1234:16,@(0x9abcdef0:32,er1) ;6a151234c9309abcdef0 -+ sub.b @0x1234:16,@(0xffff9abc:16,r2l.b) ;6a151234d2309abc -+ sub.b @0x1234:16,@(0xffff9abc:16,r2.w) ;6a151234e2309abc -+ sub.b @0x1234:16,@(0xffff9abc:16,er2.l) ;6a151234f2309abc -+ sub.b @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6a151234da309abcdef0 -+ sub.b @0x1234:16,@(0x9abcdef0:32,r2.w) ;6a151234ea309abcdef0 -+ sub.b @0x1234:16,@(0x9abcdef0:32,er2.l) ;6a151234fa309abcdef0 -+ sub.b @0x1234:16,@0xffff9abc:16 ;6a15123440309abc -+ sub.b @0x1234:16,@0x9abcdef0:32 ;6a15123448309abcdef0 -+ -+ sub.b @0x12345678:32,@er1 ;6a35123456780130 -+ sub.b @0x12345678:32,@(3:2,er1) ;6a35123456783130 -+ sub.b @0x12345678:32,@-er1 ;6a3512345678b130 -+ sub.b @0x12345678:32,@er1+ ;6a35123456788130 -+ sub.b @0x12345678:32,@er1- ;6a3512345678a130 -+ sub.b @0x12345678:32,@+er1 ;6a35123456789130 -+ sub.b @0x12345678:32,@(0xffff9abc:16,er1) ;6a3512345678c1309abc -+ sub.b @0x12345678:32,@(0x9abcdef0:32,er1) ;6a3512345678c9309abcdef0 -+ sub.b @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6a3512345678d2309abc -+ sub.b @0x12345678:32,@(0xffff9abc:16,r2.w) ;6a3512345678e2309abc -+ sub.b @0x12345678:32,@(0xffff9abc:16,er2.l) ;6a3512345678f2309abc -+ sub.b @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6a3512345678da309abcdef0 -+ sub.b @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6a3512345678ea309abcdef0 -+ sub.b @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6a3512345678fa309abcdef0 -+ sub.b @0x12345678:32,@0xffff9abc:16 ;6a351234567840309abc -+ sub.b @0x12345678:32,@0x9abcdef0:32 ;6a351234567848309abcdef0 -+ -+ sub.w #0x1234:16,r1 ;79311234 -+ sub.w #7:3,r2 ;1a72 -+ sub.w #0x1234:16,@er1 ;015e01301234 -+ sub.w #0x1234:16,@(0x6:2,er1) ;015e31301234 -+ sub.w #0x1234:16,@er1+ ;015e81301234 -+ sub.w #0x1234:16,@-er1 ;015eb1301234 -+ sub.w #0x1234:16,@+er1 ;015e91301234 -+ sub.w #0x1234:16,@er1- ;015ea1301234 -+ sub.w #0x1234:16,@(0xffff9abc:16,er1) ;015ec1309abc1234 -+ sub.w #0x1234:16,@(0x9abcdef0:32,er1) ;015ec9309abcdef01234 -+ sub.w #0x1234:16,@(0xffff9abc:16,r2l.b) ;015ed2309abc1234 -+ sub.w #0x1234:16,@(0xffff9abc:16,r2.w) ;015ee2309abc1234 -+ sub.w #0x1234:16,@(0xffff9abc:16,er2.l) ;015ef2309abc1234 -+ sub.w #0x1234:16,@(0x9abcdef0:32,r2l.b) ;015eda309abcdef01234 -+ sub.w #0x1234:16,@(0x9abcdef0:32,r2.w) ;015eea309abcdef01234 -+ sub.w #0x1234:16,@(0x9abcdef0:32,er2.l) ;015efa309abcdef01234 -+ sub.w #0x1234:16,@0xffff9abc:16 ;015e40309abc1234 -+ sub.w #0x1234:16,@0x9abcdef0:32 ;015e48309abcdef01234 -+ -+ sub.w #0x7:3,@er1 ;7d901a70 -+ sub.w #0x7:3,@0x1234:16 ;6b1812341a70 -+ sub.w #0x7:3,@0x12345678:32 ;6b38123456781a70 -+ -+ sub.w r3,r1 ;1931 -+ -+ sub.w r3,@er1 ;7d901930 -+ sub.w r3,@(0x6:2,er1) ;01593133 -+ sub.w r3,@er1+ ;01598133 -+ sub.w r3,@-er1 ;0159b133 -+ sub.w r3,@+er1 ;01599133 -+ sub.w r3,@er1- ;0159a133 -+ sub.w r3,@(0x1234:16,er1) ;0159c1331234 -+ sub.w r3,@(0x12345678:32,er1) ;0159c93312345678 -+ sub.w r3,@(0x1234:16,r2l.b) ;0159d2331234 -+ sub.w r3,@(0x1234:16,r2.w) ;0159e2331234 -+ sub.w r3,@(0x1234:16,er2.l) ;0159f2331234 -+ sub.w r3,@(0x12345678:32,r2l.b) ;0159da3312345678 -+ sub.w r3,@(0x12345678:32,r2.w) ;0159ea3312345678 -+ sub.w r3,@(0x12345678:32,er2.l) ;0159fa3312345678 -+ sub.w r3,@0x1234:16 ;6b1812341930 -+ sub.w r3,@0x12345678:32 ;6b38123456781930 -+ -+ sub.w @er3,r1 ;7cb01901 -+ sub.w @(0x6:2,er3),r1 ;015a3331 -+ sub.w @er3+,r1 ;015a8331 -+ sub.w @-er3,r1 ;015ab331 -+ sub.w @+er3,r1 ;015a9331 -+ sub.w @er3-,r1 ;015aa331 -+ sub.w @(0x1234:16,er1),r1 ;015ac1311234 -+ sub.w @(0x12345678:32,er1),r1 ;015ac93112345678 -+ sub.w @(0x1234:16,r2l.b),r1 ;015ad2311234 -+ sub.w @(0x1234:16,r2.w),r1 ;015ae2311234 -+ sub.w @(0x1234:16,er2.l),r1 ;015af2311234 -+ sub.w @(0x12345678:32,r2l.b),r1 ;015ada3112345678 -+ sub.w @(0x12345678:32,r2.w),r1 ;015aea3112345678 -+ sub.w @(0x12345678:32,er2.l),r1 ;015afa3112345678 -+ sub.w @0x1234:16,r1 ;6b1012341901 -+ sub.w @0x12345678:32,r1 ;6b30123456781901 -+ -+ sub.w @er3,@er1 ;7cb50130 -+ sub.w @er3,@(6:2,er1) ;7cb53130 -+ sub.w @er3,@-er1 ;7cb5b130 -+ sub.w @er3,@er1+ ;7cb58130 -+ sub.w @er3,@er1- ;7cb5a130 -+ sub.w @er3,@+er1 ;7cb59130 -+ sub.w @er3,@(0xffff9abc:16,er1) ;7cb5c1309abc -+ sub.w @er3,@(0x9abcdef0:32,er1) ;7cb5c9309abcdef0 -+ sub.w @er3,@(0xffff9abc:16,r2l.b) ;7cb5d2309abc -+ sub.w @er3,@(0xffff9abc:16,r2.w) ;7cb5e2309abc -+ sub.w @er3,@(0xffff9abc:16,er2.l) ;7cb5f2309abc -+ sub.w @er3,@(0x9abcdef0:32,r2l.b) ;7cb5da309abcdef0 -+ sub.w @er3,@(0x9abcdef0:32,r2.w) ;7cb5ea309abcdef0 -+ sub.w @er3,@(0x9abcdef0:32,er2.l) ;7cb5fa309abcdef0 -+ sub.w @er3,@0xffff9abc:16 ;7cb540309abc -+ sub.w @er3,@0x9abcdef0:32 ;7cb548309abcdef0 -+ -+ sub.w @-er3,@er1 ;01576d3c0130 -+ sub.w @-er3,@(6:2,er1) ;01576d3c3130 -+ sub.w @-er3,@-er1 ;01576d3cb130 -+ sub.w @-er3,@er1+ ;01576d3c8130 -+ sub.w @-er3,@er1- ;01576d3ca130 -+ sub.w @-er3,@+er1 ;01576d3c9130 -+ sub.w @-er3,@(0xffff9abc:16,er1) ;01576d3cc1309abc -+ sub.w @-er3,@(0x9abcdef0:32,er1) ;01576d3cc9309abcdef0 -+ sub.w @-er3,@(0xffff9abc:16,r2l.b) ;01576d3cd2309abc -+ sub.w @-er3,@(0xffff9abc:16,r2.w) ;01576d3ce2309abc -+ sub.w @-er3,@(0xffff9abc:16,er2.l) ;01576d3cf2309abc -+ sub.w @-er3,@(0x9abcdef0:32,r2l.b) ;01576d3cda309abcdef0 -+ sub.w @-er3,@(0x9abcdef0:32,r2.w) ;01576d3cea309abcdef0 -+ sub.w @-er3,@(0x9abcdef0:32,er2.l) ;01576d3cfa309abcdef0 -+ sub.w @-er3,@0xffff9abc:16 ;01576d3c40309abc -+ sub.w @-er3,@0x9abcdef0:32 ;01576d3c48309abcdef0 -+ -+ sub.w @er3+,@er1 ;01546d3c0130 -+ sub.w @er3+,@(6:2,er1) ;01546d3c3130 -+ sub.w @er3+,@-er1 ;01546d3cb130 -+ sub.w @er3+,@er1+ ;01546d3c8130 -+ sub.w @er3+,@er1- ;01546d3ca130 -+ sub.w @er3+,@+er1 ;01546d3c9130 -+ sub.w @er3+,@(0xffff9abc:16,er1) ;01546d3cc1309abc -+ sub.w @er3+,@(0x9abcdef0:32,er1) ;01546d3cc9309abcdef0 -+ sub.w @er3+,@(0xffff9abc:16,r2l.b) ;01546d3cd2309abc -+ sub.w @er3+,@(0xffff9abc:16,r2.w) ;01546d3ce2309abc -+ sub.w @er3+,@(0xffff9abc:16,er2.l) ;01546d3cf2309abc -+ sub.w @er3+,@(0x9abcdef0:32,r2l.b) ;01546d3cda309abcdef0 -+ sub.w @er3+,@(0x9abcdef0:32,r2.w) ;01546d3cea309abcdef0 -+ sub.w @er3+,@(0x9abcdef0:32,er2.l) ;01546d3cfa309abcdef0 -+ sub.w @er3+,@0xffff9abc:16 ;01546d3c40309abc -+ sub.w @er3+,@0x9abcdef0:32 ;01546d3c48309abcdef0 -+ -+ sub.w @er3-,@er1 ;01566d3c0130 -+ sub.w @er3-,@(6:2,er1) ;01566d3c3130 -+ sub.w @er3-,@-er1 ;01566d3cb130 -+ sub.w @er3-,@er1+ ;01566d3c8130 -+ sub.w @er3-,@er1- ;01566d3ca130 -+ sub.w @er3-,@+er1 ;01566d3c9130 -+ sub.w @er3-,@(0xffff9abc:16,er1) ;01566d3cc1309abc -+ sub.w @er3-,@(0x9abcdef0:32,er1) ;01566d3cc9309abcdef0 -+ sub.w @er3-,@(0xffff9abc:16,r2l.b) ;01566d3cd2309abc -+ sub.w @er3-,@(0xffff9abc:16,r2.w) ;01566d3ce2309abc -+ sub.w @er3-,@(0xffff9abc:16,er2.l) ;01566d3cf2309abc -+ sub.w @er3-,@(0x9abcdef0:32,r2l.b) ;01566d3cda309abcdef0 -+ sub.w @er3-,@(0x9abcdef0:32,r2.w) ;01566d3cea309abcdef0 -+ sub.w @er3-,@(0x9abcdef0:32,er2.l) ;01566d3cfa309abcdef0 -+ sub.w @er3-,@0xffff9abc:16 ;01566d3c40309abc -+ sub.w @er3-,@0x9abcdef0:32 ;01566d3c48309abcdef0 -+ -+ sub.w @+er3,@er1 ;01556d3c0130 -+ sub.w @+er3,@(6:2,er1) ;01556d3c3130 -+ sub.w @+er3,@-er1 ;01556d3cb130 -+ sub.w @+er3,@er1+ ;01556d3c8130 -+ sub.w @+er3,@er1- ;01556d3ca130 -+ sub.w @+er3,@+er1 ;01556d3c9130 -+ sub.w @+er3,@(0xffff9abc:16,er1) ;01556d3cc1309abc -+ sub.w @+er3,@(0x9abcdef0:32,er1) ;01556d3cc9309abcdef0 -+ sub.w @+er3,@(0xffff9abc:16,r2l.b) ;01556d3cd2309abc -+ sub.w @+er3,@(0xffff9abc:16,r2.w) ;01556d3ce2309abc -+ sub.w @+er3,@(0xffff9abc:16,er2.l) ;01556d3cf2309abc -+ sub.w @+er3,@(0x9abcdef0:32,r2l.b) ;01556d3cda309abcdef0 -+ sub.w @+er3,@(0x9abcdef0:32,r2.w) ;01556d3cea309abcdef0 -+ sub.w @+er3,@(0x9abcdef0:32,er2.l) ;01556d3cfa309abcdef0 -+ sub.w @+er3,@0xffff9abc:16 ;01556d3c40309abc -+ sub.w @+er3,@0x9abcdef0:32 ;01556d3c48309abcdef0 -+ -+ sub.w @(0x1234:16,er3),@er1 ;01546f3c12340130 -+ sub.w @(0x1234:16,er3),@(6:2,er1) ;01546f3c12343130 -+ sub.w @(0x1234:16,er3),@-er1 ;01546f3c1234b130 -+ sub.w @(0x1234:16,er3),@er1+ ;01546f3c12348130 -+ sub.w @(0x1234:16,er3),@er1- ;01546f3c1234a130 -+ sub.w @(0x1234:16,er3),@+er1 ;01546f3c12349130 -+ sub.w @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01546f3c1234c1309abc -+ sub.w @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01546f3c1234c9309abcdef0 -+ sub.w @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01546f3c1234d2309abc -+ sub.w @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01546f3c1234e2309abc -+ sub.w @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01546f3c1234f2309abc -+ sub.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01546f3c1234da309abcdef0 -+ sub.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01546f3c1234ea309abcdef0 -+ sub.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01546f3c1234fa309abcdef0 -+ sub.w @(0x1234:16,er3),@0xffff9abc:16 ;01546f3c123440309abc -+ sub.w @(0x1234:16,er3),@0x9abcdef0:32 ;01546f3c123448309abcdef0 -+ -+ sub.w @(0x12345678:32,er3),@er1 ;78346b2c123456780130 -+ sub.w @(0x12345678:32,er3),@(6:2,er1) ;78346b2c123456783130 -+ sub.w @(0x12345678:32,er3),@-er1 ;78346b2c12345678b130 -+ sub.w @(0x12345678:32,er3),@er1+ ;78346b2c123456788130 -+ sub.w @(0x12345678:32,er3),@er1- ;78346b2c12345678a130 -+ sub.w @(0x12345678:32,er3),@+er1 ;78346b2c123456789130 -+ sub.w @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346b2c12345678c1309abc -+ sub.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346b2c12345678c9309abcdef0 -+ sub.w @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346b2c12345678d2309abc -+ sub.w @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346b2c12345678e2309abc -+ sub.w @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346b2c12345678f2309abc -+ sub.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346b2c12345678da309abcdef0 -+ sub.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346b2c12345678ea309abcdef0 -+ sub.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346b2c12345678fa309abcdef0 -+ sub.w @(0x12345678:32,er3),@0xffff9abc:16 ;78346b2c1234567840309abc -+ sub.w @(0x12345678:32,er3),@0x9abcdef0:32 ;78346b2c1234567848309abcdef0 -+ -+ sub.w @(0x1234:16,r3l.b),@er1 ;01556f3c12340130 -+ sub.w @(0x1234:16,r3l.b),@(6:2,er1) ;01556f3c12343130 -+ sub.w @(0x1234:16,r3l.b),@-er1 ;01556f3c1234b130 -+ sub.w @(0x1234:16,r3l.b),@er1+ ;01556f3c12348130 -+ sub.w @(0x1234:16,r3l.b),@er1- ;01556f3c1234a130 -+ sub.w @(0x1234:16,r3l.b),@+er1 ;01556f3c12349130 -+ sub.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01556f3c1234c1309abc -+ sub.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01556f3c1234c9309abcdef0 -+ sub.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01556f3c1234d2309abc -+ sub.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01556f3c1234e2309abc -+ sub.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01556f3c1234f2309abc -+ sub.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01556f3c1234da309abcdef0 -+ sub.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01556f3c1234ea309abcdef0 -+ sub.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01556f3c1234fa309abcdef0 -+ sub.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;01556f3c123440309abc -+ sub.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01556f3c123448309abcdef0 -+ -+ sub.w @(0x1234:16,r3.w),@er1 ;01566f3c12340130 -+ sub.w @(0x1234:16,r3.w),@(6:2,er1) ;01566f3c12343130 -+ sub.w @(0x1234:16,r3.w),@-er1 ;01566f3c1234b130 -+ sub.w @(0x1234:16,r3.w),@er1+ ;01566f3c12348130 -+ sub.w @(0x1234:16,r3.w),@er1- ;01566f3c1234a130 -+ sub.w @(0x1234:16,r3.w),@+er1 ;01566f3c12349130 -+ sub.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01566f3c1234c1309abc -+ sub.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01566f3c1234c9309abcdef0 -+ sub.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01566f3c1234d2309abc -+ sub.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01566f3c1234e2309abc -+ sub.w @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01566f3c1234f2309abc -+ sub.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01566f3c1234da309abcdef0 -+ sub.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01566f3c1234ea309abcdef0 -+ sub.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01566f3c1234fa309abcdef0 -+ sub.w @(0x1234:16,r3.w),@0xffff9abc:16 ;01566f3c123440309abc -+ sub.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;01566f3c123448309abcdef0 -+ -+ sub.w @(0x1234:16,er3.l),@er1 ;01576f3c12340130 -+ sub.w @(0x1234:16,er3.l),@(6:2,er1) ;01576f3c12343130 -+ sub.w @(0x1234:16,er3.l),@-er1 ;01576f3c1234b130 -+ sub.w @(0x1234:16,er3.l),@er1+ ;01576f3c12348130 -+ sub.w @(0x1234:16,er3.l),@er1- ;01576f3c1234a130 -+ sub.w @(0x1234:16,er3.l),@+er1 ;01576f3c12349130 -+ sub.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01576f3c1234c1309abc -+ sub.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01576f3c1234c9309abcdef0 -+ sub.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01576f3c1234d2309abc -+ sub.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01576f3c1234e2309abc -+ sub.w @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01576f3c1234f2309abc -+ sub.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01576f3c1234da309abcdef0 -+ sub.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01576f3c1234ea309abcdef0 -+ sub.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01576f3c1234fa309abcdef0 -+ sub.w @(0x1234:16,er3.l),@0xffff9abc:16 ;01576f3c123440309abc -+ sub.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;01576f3c123448309abcdef0 -+ -+ sub.w @(0x12345678:32,r3l.b),@er1 ;78356b2c123456780130 -+ sub.w @(0x12345678:32,r3l.b),@(6:2,er1) ;78356b2c123456783130 -+ sub.w @(0x12345678:32,r3l.b),@-er1 ;78356b2c12345678b130 -+ sub.w @(0x12345678:32,r3l.b),@er1+ ;78356b2c123456788130 -+ sub.w @(0x12345678:32,r3l.b),@er1- ;78356b2c12345678a130 -+ sub.w @(0x12345678:32,r3l.b),@+er1 ;78356b2c123456789130 -+ sub.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356b2c12345678c1309abc -+ sub.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356b2c12345678c9309abcdef0 -+ sub.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356b2c12345678d2309abc -+ sub.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356b2c12345678e2309abc -+ sub.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356b2c12345678f2309abc -+ sub.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356b2c12345678da309abcdef0 -+ sub.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356b2c12345678ea309abcdef0 -+ sub.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356b2c12345678fa309abcdef0 -+ sub.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356b2c1234567840309abc -+ sub.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356b2c1234567848309abcdef0 -+ -+ sub.w @(0x12345678:32,r3.w),@er1 ;78366b2c123456780130 -+ sub.w @(0x12345678:32,r3.w),@(6:2,er1) ;78366b2c123456783130 -+ sub.w @(0x12345678:32,r3.w),@-er1 ;78366b2c12345678b130 -+ sub.w @(0x12345678:32,r3.w),@er1+ ;78366b2c123456788130 -+ sub.w @(0x12345678:32,r3.w),@er1- ;78366b2c12345678a130 -+ sub.w @(0x12345678:32,r3.w),@+er1 ;78366b2c123456789130 -+ sub.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366b2c12345678c1309abc -+ sub.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366b2c12345678c9309abcdef0 -+ sub.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366b2c12345678d2309abc -+ sub.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366b2c12345678e2309abc -+ sub.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366b2c12345678f2309abc -+ sub.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366b2c12345678da309abcdef0 -+ sub.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366b2c12345678ea309abcdef0 -+ sub.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366b2c12345678fa309abcdef0 -+ sub.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366b2c1234567840309abc -+ sub.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366b2c1234567848309abcdef0 -+ -+ sub.w @(0x12345678:32,er3.l),@er1 ;78376b2c123456780130 -+ sub.w @(0x12345678:32,er3.l),@(6:2,er1) ;78376b2c123456783130 -+ sub.w @(0x12345678:32,er3.l),@-er1 ;78376b2c12345678b130 -+ sub.w @(0x12345678:32,er3.l),@er1+ ;78376b2c123456788130 -+ sub.w @(0x12345678:32,er3.l),@er1- ;78376b2c12345678a130 -+ sub.w @(0x12345678:32,er3.l),@+er1 ;78376b2c123456789130 -+ sub.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376b2c12345678c1309abc -+ sub.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376b2c12345678c9309abcdef0 -+ sub.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376b2c12345678d2309abc -+ sub.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376b2c12345678e2309abc -+ sub.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376b2c12345678f2309abc -+ sub.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376b2c12345678da309abcdef0 -+ sub.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376b2c12345678ea309abcdef0 -+ sub.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376b2c12345678fa309abcdef0 -+ sub.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376b2c1234567840309abc -+ sub.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376b2c1234567848309abcdef0 -+ -+ sub.w @0x1234:16,@er1 ;6b1512340130 -+ sub.w @0x1234:16,@(6:2,er1) ;6b1512343130 -+ sub.w @0x1234:16,@-er1 ;6b151234b130 -+ sub.w @0x1234:16,@er1+ ;6b1512348130 -+ sub.w @0x1234:16,@er1- ;6b151234a130 -+ sub.w @0x1234:16,@+er1 ;6b1512349130 -+ sub.w @0x1234:16,@(0xffff9abc:16,er1) ;6b151234c1309abc -+ sub.w @0x1234:16,@(0x9abcdef0:32,er1) ;6b151234c9309abcdef0 -+ sub.w @0x1234:16,@(0xffff9abc:16,r2l.b) ;6b151234d2309abc -+ sub.w @0x1234:16,@(0xffff9abc:16,r2.w) ;6b151234e2309abc -+ sub.w @0x1234:16,@(0xffff9abc:16,er2.l) ;6b151234f2309abc -+ sub.w @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6b151234da309abcdef0 -+ sub.w @0x1234:16,@(0x9abcdef0:32,r2.w) ;6b151234ea309abcdef0 -+ sub.w @0x1234:16,@(0x9abcdef0:32,er2.l) ;6b151234fa309abcdef0 -+ sub.w @0x1234:16,@0xffff9abc:16 ;6b15123440309abc -+ sub.w @0x1234:16,@0x9abcdef0:32 ;6b15123448309abcdef0 -+ -+ sub.w @0x12345678:32,@er1 ;6b35123456780130 -+ sub.w @0x12345678:32,@(6:2,er1) ;6b35123456783130 -+ sub.w @0x12345678:32,@-er1 ;6b3512345678b130 -+ sub.w @0x12345678:32,@er1+ ;6b35123456788130 -+ sub.w @0x12345678:32,@er1- ;6b3512345678a130 -+ sub.w @0x12345678:32,@+er1 ;6b35123456789130 -+ sub.w @0x12345678:32,@(0xffff9abc:16,er1) ;6b3512345678c1309abc -+ sub.w @0x12345678:32,@(0x9abcdef0:32,er1) ;6b3512345678c9309abcdef0 -+ sub.w @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6b3512345678d2309abc -+ sub.w @0x12345678:32,@(0xffff9abc:16,r2.w) ;6b3512345678e2309abc -+ sub.w @0x12345678:32,@(0xffff9abc:16,er2.l) ;6b3512345678f2309abc -+ sub.w @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6b3512345678da309abcdef0 -+ sub.w @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6b3512345678ea309abcdef0 -+ sub.w @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6b3512345678fa309abcdef0 -+ sub.w @0x12345678:32,@0xffff9abc:16 ;6b351234567840309abc -+ sub.w @0x12345678:32,@0x9abcdef0:32 ;6b351234567848309abcdef0 -+ -+ sub.l #0x12345678:32,er1 ;7a3112345678 -+ sub.l #0x1234:16,er1 ;7a391234 -+ sub.l #0x7:3,er2 ;1afa -+ sub.l #0x12345678:32,@er1 ;010e013812345678 -+ sub.l #0x12345678:32,@(0xc:2,er1) ;010e313812345678 -+ sub.l #0x12345678:32,@er1+ ;010e813812345678 -+ sub.l #0x12345678:32,@-er1 ;010eb13812345678 -+ sub.l #0x12345678:32,@+er1 ;010e913812345678 -+ sub.l #0x12345678:32,@er1- ;010ea13812345678 -+ sub.l #0x12345678:32,@(0xffff9abc:16,er1) ;010ec1389abc12345678 -+ sub.l #0x12345678:32,@(0x9abcdef0:32,er1) ;010ec9389abcdef012345678 -+ sub.l #0x12345678:32,@(0xffff9abc:16,r2l.b) ;010ed2389abc12345678 -+ sub.l #0x12345678:32,@(0xffff9abc:16,r2.w) ;010ee2389abc12345678 -+ sub.l #0x12345678:32,@(0xffff9abc:16,er2.l) ;010ef2389abc12345678 -+ sub.l #0x12345678:32,@(0x9abcdef0:32,r2l.b) ;010eda389abcdef012345678 -+ sub.l #0x12345678:32,@(0x9abcdef0:32,r2.w) ;010eea389abcdef012345678 -+ sub.l #0x12345678:32,@(0x9abcdef0:32,er2.l) ;010efa389abcdef012345678 -+ sub.l #0x12345678:32,@0xffff9abc:16 ;010e40389abc12345678 -+ sub.l #0x12345678:32,@0x9abcdef0:32 ;010e48389abcdef012345678 -+ sub.l #0x1234:16,@er1 ;010e01301234 -+ sub.l #0x1234:16,@(0xc:2,er1) ;010e31301234 -+ sub.l #0x1234:16,@er1+ ;010e81301234 -+ sub.l #0x1234:16,@-er1 ;010eb1301234 -+ sub.l #0x1234:16,@+er1 ;010e91301234 -+ sub.l #0x1234:16,@er1- ;010ea1301234 -+ sub.l #0x1234:16,@(0xffff9abc:16,er1) ;010ec1309abc1234 -+ sub.l #0x1234:16,@(0x9abcdef0:32,er1) ;010ec9309abcdef01234 -+ sub.l #0x1234:16,@(0xffff9abc:16,r2l.b) ;010ed2309abc1234 -+ sub.l #0x1234:16,@(0xffff9abc:16,r2.w) ;010ee2309abc1234 -+ sub.l #0x1234:16,@(0xffff9abc:16,er2.l) ;010ef2309abc1234 -+ sub.l #0x1234:16,@(0x9abcdef0:32,r2l.b) ;010eda309abcdef01234 -+ sub.l #0x1234:16,@(0x9abcdef0:32,r2.w) ;010eea309abcdef01234 -+ sub.l #0x1234:16,@(0x9abcdef0:32,er2.l) ;010efa309abcdef01234 -+ sub.l #0x1234:16,@0xffff9abc:16 ;010e40309abc1234 -+ sub.l #0x1234:16,@0x9abcdef0:32 ;010e48309abcdef01234 -+ -+ sub.l er3,er1 ;1ab1 -+ -+ sub.l er3,@er1 ;01090133 -+ sub.l er3,@(0xc:2,er1) ;01093133 -+ sub.l er3,@er1+ ;01098133 -+ sub.l er3,@-er1 ;0109b133 -+ sub.l er3,@+er1 ;01099133 -+ sub.l er3,@er1- ;0109a133 -+ sub.l er3,@(0x1234:16,er1) ;0109c1331234 -+ sub.l er3,@(0x12345678:32,er1) ;0109c93312345678 -+ sub.l er3,@(0x1234:16,r2l.b) ;0109d2331234 -+ sub.l er3,@(0x1234:16,r2.w) ;0109e2331234 -+ sub.l er3,@(0x1234:16,er2.l) ;0109f2331234 -+ sub.l er3,@(0x12345678:32,r2l.b) ;0109da3312345678 -+ sub.l er3,@(0x12345678:32,r2.w) ;0109ea3312345678 -+ sub.l er3,@(0x12345678:32,er2.l) ;0109fa3312345678 -+ sub.l er3,@0x1234:16 ;010940331234 -+ sub.l er3,@0x12345678:32 ;0109483312345678 -+ -+ sub.l @er3,er1 ;010a0331 -+ sub.l @(0xc:2,er3),er1 ;010a3331 -+ sub.l @er3+,er1 ;010a8331 -+ sub.l @-er3,er1 ;010ab331 -+ sub.l @+er3,er1 ;010a9331 -+ sub.l @er3-,er1 ;010aa331 -+ sub.l @(0x1234:16,er1),er1 ;010ac1311234 -+ sub.l @(0x12345678:32,er1),er1 ;010ac93112345678 -+ sub.l @(0x1234:16,r2l.b),er1 ;010ad2311234 -+ sub.l @(0x1234:16,r2.w),er1 ;010ae2311234 -+ sub.l @(0x1234:16,er2.l),er1 ;010af2311234 -+ sub.l @(0x12345678:32,r2l.b),er1 ;010ada3112345678 -+ sub.l @(0x12345678:32,r2.w),er1 ;010aea3112345678 -+ sub.l @(0x12345678:32,er2.l),er1 ;010afa3112345678 -+ sub.l @0x1234:16,er1 ;010a40311234 -+ sub.l @0x12345678:32,er1 ;010a483112345678 -+ -+ sub.l @er3,@er1 ;0104693c0130 -+ sub.l @er3,@(0xc:2,er1) ;0104693c3130 -+ sub.l @er3,@-er1 ;0104693cb130 -+ sub.l @er3,@er1+ ;0104693c8130 -+ sub.l @er3,@er1- ;0104693ca130 -+ sub.l @er3,@+er1 ;0104693c9130 -+ sub.l @er3,@(0xffff9abc:16,er1) ;0104693cc1309abc -+ sub.l @er3,@(0x9abcdef0:32,er1) ;0104693cc9309abcdef0 -+ sub.l @er3,@(0xffff9abc:16,r2l.b) ;0104693cd2309abc -+ sub.l @er3,@(0xffff9abc:16,r2.w) ;0104693ce2309abc -+ sub.l @er3,@(0xffff9abc:16,er2.l) ;0104693cf2309abc -+ sub.l @er3,@(0x9abcdef0:32,r2l.b) ;0104693cda309abcdef0 -+ sub.l @er3,@(0x9abcdef0:32,r2.w) ;0104693cea309abcdef0 -+ sub.l @er3,@(0x9abcdef0:32,er2.l) ;0104693cfa309abcdef0 -+ sub.l @er3,@0xffff9abc:16 ;0104693c40309abc -+ sub.l @er3,@0x9abcdef0:32 ;0104693c48309abcdef0 -+ -+ sub.l @(0xc:2,er3),@er1 ;0107693c0130 -+ sub.l @(0xc:2,er3),@(0xc:2,er1) ;0107693c3130 -+ sub.l @(0xc:2,er3),@-er1 ;0107693cb130 -+ sub.l @(0xc:2,er3),@er1+ ;0107693c8130 -+ sub.l @(0xc:2,er3),@er1- ;0107693ca130 -+ sub.l @(0xc:2,er3),@+er1 ;0107693c9130 -+ sub.l @(0xc:2,er3),@(0xffff9abc:16,er1) ;0107693cc1309abc -+ sub.l @(0xc:2,er3),@(0x9abcdef0:32,er1) ;0107693cc9309abcdef0 -+ sub.l @(0xc:2,er3),@(0xffff9abc:16,r2l.b) ;0107693cd2309abc -+ sub.l @(0xc:2,er3),@(0xffff9abc:16,r2.w) ;0107693ce2309abc -+ sub.l @(0xc:2,er3),@(0xffff9abc:16,er2.l) ;0107693cf2309abc -+ sub.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b) ;0107693cda309abcdef0 -+ sub.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w) ;0107693cea309abcdef0 -+ sub.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l) ;0107693cfa309abcdef0 -+ sub.l @(0xc:2,er3),@0xffff9abc:16 ;0107693c40309abc -+ sub.l @(0xc:2,er3),@0x9abcdef0:32 ;0107693c48309abcdef0 -+ -+ sub.l @-er3,@er1 ;01076d3c0130 -+ sub.l @-er3,@(0xc:2,er1) ;01076d3c3130 -+ sub.l @-er3,@-er1 ;01076d3cb130 -+ sub.l @-er3,@er1+ ;01076d3c8130 -+ sub.l @-er3,@er1- ;01076d3ca130 -+ sub.l @-er3,@+er1 ;01076d3c9130 -+ sub.l @-er3,@(0xffff9abc:16,er1) ;01076d3cc1309abc -+ sub.l @-er3,@(0x9abcdef0:32,er1) ;01076d3cc9309abcdef0 -+ sub.l @-er3,@(0xffff9abc:16,r2l.b) ;01076d3cd2309abc -+ sub.l @-er3,@(0xffff9abc:16,r2.w) ;01076d3ce2309abc -+ sub.l @-er3,@(0xffff9abc:16,er2.l) ;01076d3cf2309abc -+ sub.l @-er3,@(0x9abcdef0:32,r2l.b) ;01076d3cda309abcdef0 -+ sub.l @-er3,@(0x9abcdef0:32,r2.w) ;01076d3cea309abcdef0 -+ sub.l @-er3,@(0x9abcdef0:32,er2.l) ;01076d3cfa309abcdef0 -+ sub.l @-er3,@0xffff9abc:16 ;01076d3c40309abc -+ sub.l @-er3,@0x9abcdef0:32 ;01076d3c48309abcdef0 -+ -+ sub.l @er3+,@er1 ;01046d3c0130 -+ sub.l @er3+,@(0xc:2,er1) ;01046d3c3130 -+ sub.l @er3+,@-er1 ;01046d3cb130 -+ sub.l @er3+,@er1+ ;01046d3c8130 -+ sub.l @er3+,@er1- ;01046d3ca130 -+ sub.l @er3+,@+er1 ;01046d3c9130 -+ sub.l @er3+,@(0xffff9abc:16,er1) ;01046d3cc1309abc -+ sub.l @er3+,@(0x9abcdef0:32,er1) ;01046d3cc9309abcdef0 -+ sub.l @er3+,@(0xffff9abc:16,r2l.b) ;01046d3cd2309abc -+ sub.l @er3+,@(0xffff9abc:16,r2.w) ;01046d3ce2309abc -+ sub.l @er3+,@(0xffff9abc:16,er2.l) ;01046d3cf2309abc -+ sub.l @er3+,@(0x9abcdef0:32,r2l.b) ;01046d3cda309abcdef0 -+ sub.l @er3+,@(0x9abcdef0:32,r2.w) ;01046d3cea309abcdef0 -+ sub.l @er3+,@(0x9abcdef0:32,er2.l) ;01046d3cfa309abcdef0 -+ sub.l @er3+,@0xffff9abc:16 ;01046d3c40309abc -+ sub.l @er3+,@0x9abcdef0:32 ;01046d3c48309abcdef0 -+ -+ sub.l @er3-,@er1 ;01066d3c0130 -+ sub.l @er3-,@(0xc:2,er1) ;01066d3c3130 -+ sub.l @er3-,@-er1 ;01066d3cb130 -+ sub.l @er3-,@er1+ ;01066d3c8130 -+ sub.l @er3-,@er1- ;01066d3ca130 -+ sub.l @er3-,@+er1 ;01066d3c9130 -+ sub.l @er3-,@(0xffff9abc:16,er1) ;01066d3cc1309abc -+ sub.l @er3-,@(0x9abcdef0:32,er1) ;01066d3cc9309abcdef0 -+ sub.l @er3-,@(0xffff9abc:16,r2l.b) ;01066d3cd2309abc -+ sub.l @er3-,@(0xffff9abc:16,r2.w) ;01066d3ce2309abc -+ sub.l @er3-,@(0xffff9abc:16,er2.l) ;01066d3cf2309abc -+ sub.l @er3-,@(0x9abcdef0:32,r2l.b) ;01066d3cda309abcdef0 -+ sub.l @er3-,@(0x9abcdef0:32,r2.w) ;01066d3cea309abcdef0 -+ sub.l @er3-,@(0x9abcdef0:32,er2.l) ;01066d3cfa309abcdef0 -+ sub.l @er3-,@0xffff9abc:16 ;01066d3c40309abc -+ sub.l @er3-,@0x9abcdef0:32 ;01066d3c48309abcdef0 -+ -+ sub.l @+er3,@er1 ;01056d3c0130 -+ sub.l @+er3,@(0xc:2,er1) ;01056d3c3130 -+ sub.l @+er3,@-er1 ;01056d3cb130 -+ sub.l @+er3,@er1+ ;01056d3c8130 -+ sub.l @+er3,@er1- ;01056d3ca130 -+ sub.l @+er3,@+er1 ;01056d3c9130 -+ sub.l @+er3,@(0xffff9abc:16,er1) ;01056d3cc1309abc -+ sub.l @+er3,@(0x9abcdef0:32,er1) ;01056d3cc9309abcdef0 -+ sub.l @+er3,@(0xffff9abc:16,r2l.b) ;01056d3cd2309abc -+ sub.l @+er3,@(0xffff9abc:16,r2.w) ;01056d3ce2309abc -+ sub.l @+er3,@(0xffff9abc:16,er2.l) ;01056d3cf2309abc -+ sub.l @+er3,@(0x9abcdef0:32,r2l.b) ;01056d3cda309abcdef0 -+ sub.l @+er3,@(0x9abcdef0:32,r2.w) ;01056d3cea309abcdef0 -+ sub.l @+er3,@(0x9abcdef0:32,er2.l) ;01056d3cfa309abcdef0 -+ sub.l @+er3,@0xffff9abc:16 ;01056d3c40309abc -+ sub.l @+er3,@0x9abcdef0:32 ;01056d3c48309abcdef0 -+ -+ sub.l @(0x1234:16,er3),@er1 ;01046f3c12340130 -+ sub.l @(0x1234:16,er3),@(0xc:2,er1) ;01046f3c12343130 -+ sub.l @(0x1234:16,er3),@-er1 ;01046f3c1234b130 -+ sub.l @(0x1234:16,er3),@er1+ ;01046f3c12348130 -+ sub.l @(0x1234:16,er3),@er1- ;01046f3c1234a130 -+ sub.l @(0x1234:16,er3),@+er1 ;01046f3c12349130 -+ sub.l @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01046f3c1234c1309abc -+ sub.l @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01046f3c1234c9309abcdef0 -+ sub.l @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01046f3c1234d2309abc -+ sub.l @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01046f3c1234e2309abc -+ sub.l @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01046f3c1234f2309abc -+ sub.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01046f3c1234da309abcdef0 -+ sub.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01046f3c1234ea309abcdef0 -+ sub.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01046f3c1234fa309abcdef0 -+ sub.l @(0x1234:16,er3),@0xffff9abc:16 ;01046f3c123440309abc -+ sub.l @(0x1234:16,er3),@0x9abcdef0:32 ;01046f3c123448309abcdef0 -+ -+ sub.l @(0x12345678:32,er3),@er1 ;78b46b2c123456780130 -+ sub.l @(0x12345678:32,er3),@(0xc:2,er1) ;78b46b2c123456783130 -+ sub.l @(0x12345678:32,er3),@-er1 ;78b46b2c12345678b130 -+ sub.l @(0x12345678:32,er3),@er1+ ;78b46b2c123456788130 -+ sub.l @(0x12345678:32,er3),@er1- ;78b46b2c12345678a130 -+ sub.l @(0x12345678:32,er3),@+er1 ;78b46b2c123456789130 -+ sub.l @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78b46b2c12345678c1309abc -+ sub.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78b46b2c12345678c9309abcdef0 -+ sub.l @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78b46b2c12345678d2309abc -+ sub.l @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78b46b2c12345678e2309abc -+ sub.l @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78b46b2c12345678f2309abc -+ sub.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78b46b2c12345678da309abcdef0 -+ sub.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78b46b2c12345678ea309abcdef0 -+ sub.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78b46b2c12345678fa309abcdef0 -+ sub.l @(0x12345678:32,er3),@0xffff9abc:16 ;78b46b2c1234567840309abc -+ sub.l @(0x12345678:32,er3),@0x9abcdef0:32 ;78b46b2c1234567848309abcdef0 -+ -+ sub.l @(0x1234:16,r3l.b),@er1 ;01056f3c12340130 -+ sub.l @(0x1234:16,r3l.b),@(0xc:2,er1) ;01056f3c12343130 -+ sub.l @(0x1234:16,r3l.b),@-er1 ;01056f3c1234b130 -+ sub.l @(0x1234:16,r3l.b),@er1+ ;01056f3c12348130 -+ sub.l @(0x1234:16,r3l.b),@er1- ;01056f3c1234a130 -+ sub.l @(0x1234:16,r3l.b),@+er1 ;01056f3c12349130 -+ sub.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01056f3c1234c1309abc -+ sub.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01056f3c1234c9309abcdef0 -+ sub.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01056f3c1234d2309abc -+ sub.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01056f3c1234e2309abc -+ sub.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01056f3c1234f2309abc -+ sub.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01056f3c1234da309abcdef0 -+ sub.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01056f3c1234ea309abcdef0 -+ sub.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01056f3c1234fa309abcdef0 -+ sub.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;01056f3c123440309abc -+ sub.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01056f3c123448309abcdef0 -+ -+ sub.l @(0x1234:16,r3.w),@er1 ;01066f3c12340130 -+ sub.l @(0x1234:16,r3.w),@(0xc:2,er1) ;01066f3c12343130 -+ sub.l @(0x1234:16,r3.w),@-er1 ;01066f3c1234b130 -+ sub.l @(0x1234:16,r3.w),@er1+ ;01066f3c12348130 -+ sub.l @(0x1234:16,r3.w),@er1- ;01066f3c1234a130 -+ sub.l @(0x1234:16,r3.w),@+er1 ;01066f3c12349130 -+ sub.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01066f3c1234c1309abc -+ sub.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01066f3c1234c9309abcdef0 -+ sub.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01066f3c1234d2309abc -+ sub.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01066f3c1234e2309abc -+ sub.l @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01066f3c1234f2309abc -+ sub.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01066f3c1234da309abcdef0 -+ sub.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01066f3c1234ea309abcdef0 -+ sub.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01066f3c1234fa309abcdef0 -+ sub.l @(0x1234:16,r3.w),@0xffff9abc:16 ;01066f3c123440309abc -+ sub.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;01066f3c123448309abcdef0 -+ -+ sub.l @(0x1234:16,er3.l),@er1 ;01076f3c12340130 -+ sub.l @(0x1234:16,er3.l),@(0xc:2,er1) ;01076f3c12343130 -+ sub.l @(0x1234:16,er3.l),@-er1 ;01076f3c1234b130 -+ sub.l @(0x1234:16,er3.l),@er1+ ;01076f3c12348130 -+ sub.l @(0x1234:16,er3.l),@er1- ;01076f3c1234a130 -+ sub.l @(0x1234:16,er3.l),@+er1 ;01076f3c12349130 -+ sub.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01076f3c1234c1309abc -+ sub.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01076f3c1234c9309abcdef0 -+ sub.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01076f3c1234d2309abc -+ sub.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01076f3c1234e2309abc -+ sub.l @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01076f3c1234f2309abc -+ sub.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01076f3c1234da309abcdef0 -+ sub.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01076f3c1234ea309abcdef0 -+ sub.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01076f3c1234fa309abcdef0 -+ sub.l @(0x1234:16,er3.l),@0xffff9abc:16 ;01076f3c123440309abc -+ sub.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;01076f3c123448309abcdef0 -+ -+ sub.l @(0x12345678:32,r3l.b),@er1 ;78b56b2c123456780130 -+ sub.l @(0x12345678:32,r3l.b),@(0xc:2,er1) ;78b56b2c123456783130 -+ sub.l @(0x12345678:32,r3l.b),@-er1 ;78b56b2c12345678b130 -+ sub.l @(0x12345678:32,r3l.b),@er1+ ;78b56b2c123456788130 -+ sub.l @(0x12345678:32,r3l.b),@er1- ;78b56b2c12345678a130 -+ sub.l @(0x12345678:32,r3l.b),@+er1 ;78b56b2c123456789130 -+ sub.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78b56b2c12345678c1309abc -+ sub.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78b56b2c12345678c9309abcdef0 -+ sub.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78b56b2c12345678d2309abc -+ sub.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78b56b2c12345678e2309abc -+ sub.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78b56b2c12345678f2309abc -+ sub.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78b56b2c12345678da309abcdef0 -+ sub.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78b56b2c12345678ea309abcdef0 -+ sub.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78b56b2c12345678fa309abcdef0 -+ sub.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78b56b2c1234567840309abc -+ sub.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78b56b2c1234567848309abcdef0 -+ -+ sub.l @(0x12345678:32,r3.w),@er1 ;78b66b2c123456780130 -+ sub.l @(0x12345678:32,r3.w),@(0xc:2,er1) ;78b66b2c123456783130 -+ sub.l @(0x12345678:32,r3.w),@-er1 ;78b66b2c12345678b130 -+ sub.l @(0x12345678:32,r3.w),@er1+ ;78b66b2c123456788130 -+ sub.l @(0x12345678:32,r3.w),@er1- ;78b66b2c12345678a130 -+ sub.l @(0x12345678:32,r3.w),@+er1 ;78b66b2c123456789130 -+ sub.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78b66b2c12345678c1309abc -+ sub.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78b66b2c12345678c9309abcdef0 -+ sub.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78b66b2c12345678d2309abc -+ sub.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78b66b2c12345678e2309abc -+ sub.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78b66b2c12345678f2309abc -+ sub.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78b66b2c12345678da309abcdef0 -+ sub.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78b66b2c12345678ea309abcdef0 -+ sub.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78b66b2c12345678fa309abcdef0 -+ sub.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;78b66b2c1234567840309abc -+ sub.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78b66b2c1234567848309abcdef0 -+ -+ sub.l @(0x12345678:32,er3.l),@er1 ;78b76b2c123456780130 -+ sub.l @(0x12345678:32,er3.l),@(0xc:2,er1) ;78b76b2c123456783130 -+ sub.l @(0x12345678:32,er3.l),@-er1 ;78b76b2c12345678b130 -+ sub.l @(0x12345678:32,er3.l),@er1+ ;78b76b2c123456788130 -+ sub.l @(0x12345678:32,er3.l),@er1- ;78b76b2c12345678a130 -+ sub.l @(0x12345678:32,er3.l),@+er1 ;78b76b2c123456789130 -+ sub.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78b76b2c12345678c1309abc -+ sub.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78b76b2c12345678c9309abcdef0 -+ sub.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78b76b2c12345678d2309abc -+ sub.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78b76b2c12345678e2309abc -+ sub.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78b76b2c12345678f2309abc -+ sub.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78b76b2c12345678da309abcdef0 -+ sub.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78b76b2c12345678ea309abcdef0 -+ sub.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78b76b2c12345678fa309abcdef0 -+ sub.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;78b76b2c1234567840309abc -+ sub.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78b76b2c1234567848309abcdef0 -+ -+ sub.l @0x1234:16,@er1 ;01046b0c12340130 -+ sub.l @0x1234:16,@(0xc:2,er1) ;01046b0c12343130 -+ sub.l @0x1234:16,@-er1 ;01046b0c1234b130 -+ sub.l @0x1234:16,@er1+ ;01046b0c12348130 -+ sub.l @0x1234:16,@er1- ;01046b0c1234a130 -+ sub.l @0x1234:16,@+er1 ;01046b0c12349130 -+ sub.l @0x1234:16,@(0xffff9abc:16,er1) ;01046b0c1234c1309abc -+ sub.l @0x1234:16,@(0x9abcdef0:32,er1) ;01046b0c1234c9309abcdef0 -+ sub.l @0x1234:16,@(0xffff9abc:16,r2l.b) ;01046b0c1234d2309abc -+ sub.l @0x1234:16,@(0xffff9abc:16,r2.w) ;01046b0c1234e2309abc -+ sub.l @0x1234:16,@(0xffff9abc:16,er2.l) ;01046b0c1234f2309abc -+ sub.l @0x1234:16,@(0x9abcdef0:32,r2l.b) ;01046b0c1234da309abcdef0 -+ sub.l @0x1234:16,@(0x9abcdef0:32,r2.w) ;01046b0c1234ea309abcdef0 -+ sub.l @0x1234:16,@(0x9abcdef0:32,er2.l) ;01046b0c1234fa309abcdef0 -+ sub.l @0x1234:16,@0xffff9abc:16 ;01046b0c123440309abc -+ sub.l @0x1234:16,@0x9abcdef0:32 ;01046b0c123448309abcdef0 -+ -+ sub.l @0x12345678:32,@er1 ;01046b2c123456780130 -+ sub.l @0x12345678:32,@(0xc:2,er1) ;01046b2c123456783130 -+ sub.l @0x12345678:32,@-er1 ;01046b2c12345678b130 -+ sub.l @0x12345678:32,@er1+ ;01046b2c123456788130 -+ sub.l @0x12345678:32,@er1- ;01046b2c12345678a130 -+ sub.l @0x12345678:32,@+er1 ;01046b2c123456789130 -+ sub.l @0x12345678:32,@(0xffff9abc:16,er1) ;01046b2c12345678c1309abc -+ sub.l @0x12345678:32,@(0x9abcdef0:32,er1) ;01046b2c12345678c9309abcdef0 -+ sub.l @0x12345678:32,@(0xffff9abc:16,r2l.b) ;01046b2c12345678d2309abc -+ sub.l @0x12345678:32,@(0xffff9abc:16,r2.w) ;01046b2c12345678e2309abc -+ sub.l @0x12345678:32,@(0xffff9abc:16,er2.l) ;01046b2c12345678f2309abc -+ sub.l @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;01046b2c12345678da309abcdef0 -+ sub.l @0x12345678:32,@(0x9abcdef0:32,r2.w) ;01046b2c12345678ea309abcdef0 -+ sub.l @0x12345678:32,@(0x9abcdef0:32,er2.l) ;01046b2c12345678fa309abcdef0 -+ sub.l @0x12345678:32,@0xffff9abc:16 ;01046b2c1234567840309abc -+ sub.l @0x12345678:32,@0x9abcdef0:32 ;01046b2c1234567848309abcdef0 -+ -+ .end ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;arith_1 ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ .h8300sx ++ .text ++_start: ++ sub.b #0x12:8,@er1 ;7d10a112 ++ sub.b #0x12:8,@(0x3:2,er1) ;01776818a112 ++ sub.b #0x12:8,@er1+ ;01746c18a112 ++ sub.b #0x12:8,@-er1 ;01776c18a112 ++ sub.b #0x12:8,@+er1 ;01756c18a112 ++ sub.b #0x12:8,@er1- ;01766c18a112 ++ sub.b #0x12:8,@(0x1234:16,er1) ;01746e181234a112 ++ sub.b #0x12:8,@(0x12345678:32,er1) ;78146a2812345678a112 ++ sub.b #0x12:8,@(0x1234:16,r2l.b) ;01756e281234a112 ++ sub.b #0x12:8,@(0x1234:16,r2.w) ;01766e281234a112 ++ sub.b #0x12:8,@(0x1234:16,er2.l) ;01776e281234a112 ++ sub.b #0x12:8,@(0x12345678:32,r2l.b) ;78256a2812345678a112 ++ sub.b #0x12:8,@(0x12345678:32,r2.w) ;78266a2812345678a112 ++ sub.b #0x12:8,@(0x12345678:32,er2.l) ;78276a2812345678a112 ++ sub.b #0x12:8,@0xffffff9a:8 ;7f9aa112 ++ sub.b #0x12:8,@0x1234:16 ;6a181234a112 ++ sub.b #0x12:8,@0x12345678:32 ;6a3812345678a112 ++ ++ sub.b r3h,r1h ;1831 ++ ++ sub.b r3h,@er1 ;7d101830 ++ sub.b r3h,@(0x3:2,er1) ;01793133 ++ sub.b r3h,@er1+ ;01798133 ++ sub.b r3h,@-er1 ;0179b133 ++ sub.b r3h,@+er1 ;01799133 ++ sub.b r3h,@er1- ;0179a133 ++ sub.b r3h,@(0x1234:16,er1) ;0179c1331234 ++ sub.b r3h,@(0x12345678:32,er1) ;0179c93312345678 ++ sub.b r3h,@(0x1234:16,r2l.b) ;0179d2331234 ++ sub.b r3h,@(0x1234:16,r2.w) ;0179e2331234 ++ sub.b r3h,@(0x1234:16,er2.l) ;0179f2331234 ++ sub.b r3h,@(0x12345678:32,r2l.b) ;0179da3312345678 ++ sub.b r3h,@(0x12345678:32,r2.w) ;0179ea3312345678 ++ sub.b r3h,@(0x12345678:32,er2.l) ;0179fa3312345678 ++ sub.b r3h,@0xffffff12:8 ;7f121830 ++ sub.b r3h,@0x1234:16 ;6a1812341830 ++ sub.b r3h,@0x12345678:32 ;6a38123456781830 ++ ++ sub.b @er3,r1h ;7c301801 ++ sub.b @(0x3:2,er3),r1h ;017a3331 ++ sub.b @er3+,r1h ;017a8331 ++ sub.b @-er3,r1h ;017ab331 ++ sub.b @+er3,r1h ;017a9331 ++ sub.b @er3-,r1h ;017aa331 ++ sub.b @(0x1234:16,er1),r1h ;017ac1311234 ++ sub.b @(0x12345678:32,er1),r1h ;017ac93112345678 ++ sub.b @(0x1234:16,r2l.b),r1h ;017ad2311234 ++ sub.b @(0x1234:16,r2.w),r1h ;017ae2311234 ++ sub.b @(0x1234:16,er2.l),r1h ;017af2311234 ++ sub.b @(0x12345678:32,r2l.b),r1h ;017ada3112345678 ++ sub.b @(0x12345678:32,r2.w),r1h ;017aea3112345678 ++ sub.b @(0x12345678:32,er2.l),r1h ;017afa3112345678 ++ sub.b @0xffffff12:8,r1h ;7e121801 ++ sub.b @0x1234:16,r1h ;6a1012341801 ++ sub.b @0x12345678:32,r1h ;6a30123456781801 ++ ++ sub.b @er3,@er1 ;7c350130 ++ sub.b @er3,@(3:2,er1) ;7c353130 ++ sub.b @er3,@-er1 ;7c35b130 ++ sub.b @er3,@er1+ ;7c358130 ++ sub.b @er3,@er1- ;7c35a130 ++ sub.b @er3,@+er1 ;7c359130 ++ sub.b @er3,@(0xffff9abc:16,er1) ;7c35c1309abc ++ sub.b @er3,@(0x9abcdef0:32,er1) ;7c35c9309abcdef0 ++ sub.b @er3,@(0xffff9abc:16,r2l.b) ;7c35d2309abc ++ sub.b @er3,@(0xffff9abc:16,r2.w) ;7c35e2309abc ++ sub.b @er3,@(0xffff9abc:16,er2.l) ;7c35f2309abc ++ sub.b @er3,@(0x9abcdef0:32,r2l.b) ;7c35da309abcdef0 ++ sub.b @er3,@(0x9abcdef0:32,r2.w) ;7c35ea309abcdef0 ++ sub.b @er3,@(0x9abcdef0:32,er2.l) ;7c35fa309abcdef0 ++ sub.b @er3,@0xffff9abc:16 ;7c3540309abc ++ sub.b @er3,@0x9abcdef0:32 ;7c3548309abcdef0 ++ ++ sub.b @-er3,@er1 ;01776c3c0130 ++ sub.b @-er3,@(3:2,er1) ;01776c3c3130 ++ sub.b @-er3,@-er1 ;01776c3cb130 ++ sub.b @-er3,@er1+ ;01776c3c8130 ++ sub.b @-er3,@er1- ;01776c3ca130 ++ sub.b @-er3,@+er1 ;01776c3c9130 ++ sub.b @-er3,@(0xffff9abc:16,er1) ;01776c3cc1309abc ++ sub.b @-er3,@(0x9abcdef0:32,er1) ;01776c3cc9309abcdef0 ++ sub.b @-er3,@(0xffff9abc:16,r2l.b) ;01776c3cd2309abc ++ sub.b @-er3,@(0xffff9abc:16,r2.w) ;01776c3ce2309abc ++ sub.b @-er3,@(0xffff9abc:16,er2.l) ;01776c3cf2309abc ++ sub.b @-er3,@(0x9abcdef0:32,r2l.b) ;01776c3cda309abcdef0 ++ sub.b @-er3,@(0x9abcdef0:32,r2.w) ;01776c3cea309abcdef0 ++ sub.b @-er3,@(0x9abcdef0:32,er2.l) ;01776c3cfa309abcdef0 ++ sub.b @-er3,@0xffff9abc:16 ;01776c3c40309abc ++ sub.b @-er3,@0x9abcdef0:32 ;01776c3c48309abcdef0 ++ ++ sub.b @er3+,@er1 ;01746c3c0130 ++ sub.b @er3+,@(3:2,er1) ;01746c3c3130 ++ sub.b @er3+,@-er1 ;01746c3cb130 ++ sub.b @er3+,@er1+ ;01746c3c8130 ++ sub.b @er3+,@er1- ;01746c3ca130 ++ sub.b @er3+,@+er1 ;01746c3c9130 ++ sub.b @er3+,@(0xffff9abc:16,er1) ;01746c3cc1309abc ++ sub.b @er3+,@(0x9abcdef0:32,er1) ;01746c3cc9309abcdef0 ++ sub.b @er3+,@(0xffff9abc:16,r2l.b) ;01746c3cd2309abc ++ sub.b @er3+,@(0xffff9abc:16,r2.w) ;01746c3ce2309abc ++ sub.b @er3+,@(0xffff9abc:16,er2.l) ;01746c3cf2309abc ++ sub.b @er3+,@(0x9abcdef0:32,r2l.b) ;01746c3cda309abcdef0 ++ sub.b @er3+,@(0x9abcdef0:32,r2.w) ;01746c3cea309abcdef0 ++ sub.b @er3+,@(0x9abcdef0:32,er2.l) ;01746c3cfa309abcdef0 ++ sub.b @er3+,@0xffff9abc:16 ;01746c3c40309abc ++ sub.b @er3+,@0x9abcdef0:32 ;01746c3c48309abcdef0 ++ ++ sub.b @er3-,@er1 ;01766c3c0130 ++ sub.b @er3-,@(3:2,er1) ;01766c3c3130 ++ sub.b @er3-,@-er1 ;01766c3cb130 ++ sub.b @er3-,@er1+ ;01766c3c8130 ++ sub.b @er3-,@er1- ;01766c3ca130 ++ sub.b @er3-,@+er1 ;01766c3c9130 ++ sub.b @er3-,@(0xffff9abc:16,er1) ;01766c3cc1309abc ++ sub.b @er3-,@(0x9abcdef0:32,er1) ;01766c3cc9309abcdef0 ++ sub.b @er3-,@(0xffff9abc:16,r2l.b) ;01766c3cd2309abc ++ sub.b @er3-,@(0xffff9abc:16,r2.w) ;01766c3ce2309abc ++ sub.b @er3-,@(0xffff9abc:16,er2.l) ;01766c3cf2309abc ++ sub.b @er3-,@(0x9abcdef0:32,r2l.b) ;01766c3cda309abcdef0 ++ sub.b @er3-,@(0x9abcdef0:32,r2.w) ;01766c3cea309abcdef0 ++ sub.b @er3-,@(0x9abcdef0:32,er2.l) ;01766c3cfa309abcdef0 ++ sub.b @er3-,@0xffff9abc:16 ;01766c3c40309abc ++ sub.b @er3-,@0x9abcdef0:32 ;01766c3c48309abcdef0 ++ ++ sub.b @+er3,@er1 ;01756c3c0130 ++ sub.b @+er3,@(3:2,er1) ;01756c3c3130 ++ sub.b @+er3,@-er1 ;01756c3cb130 ++ sub.b @+er3,@er1+ ;01756c3c8130 ++ sub.b @+er3,@er1- ;01756c3ca130 ++ sub.b @+er3,@+er1 ;01756c3c9130 ++ sub.b @+er3,@(0xffff9abc:16,er1) ;01756c3cc1309abc ++ sub.b @+er3,@(0x9abcdef0:32,er1) ;01756c3cc9309abcdef0 ++ sub.b @+er3,@(0xffff9abc:16,r2l.b) ;01756c3cd2309abc ++ sub.b @+er3,@(0xffff9abc:16,r2.w) ;01756c3ce2309abc ++ sub.b @+er3,@(0xffff9abc:16,er2.l) ;01756c3cf2309abc ++ sub.b @+er3,@(0x9abcdef0:32,r2l.b) ;01756c3cda309abcdef0 ++ sub.b @+er3,@(0x9abcdef0:32,r2.w) ;01756c3cea309abcdef0 ++ sub.b @+er3,@(0x9abcdef0:32,er2.l) ;01756c3cfa309abcdef0 ++ sub.b @+er3,@0xffff9abc:16 ;01756c3c40309abc ++ sub.b @+er3,@0x9abcdef0:32 ;01756c3c48309abcdef0 ++ ++ sub.b @(0x1234:16,er3),@er1 ;01746e3c12340130 ++ sub.b @(0x1234:16,er3),@(3:2,er1) ;01746e3c12343130 ++ sub.b @(0x1234:16,er3),@-er1 ;01746e3c1234b130 ++ sub.b @(0x1234:16,er3),@er1+ ;01746e3c12348130 ++ sub.b @(0x1234:16,er3),@er1- ;01746e3c1234a130 ++ sub.b @(0x1234:16,er3),@+er1 ;01746e3c12349130 ++ sub.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01746e3c1234c1309abc ++ sub.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01746e3c1234c9309abcdef0 ++ sub.b @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01746e3c1234d2309abc ++ sub.b @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01746e3c1234e2309abc ++ sub.b @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01746e3c1234f2309abc ++ sub.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01746e3c1234da309abcdef0 ++ sub.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01746e3c1234ea309abcdef0 ++ sub.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01746e3c1234fa309abcdef0 ++ sub.b @(0x1234:16,er3),@0xffff9abc:16 ;01746e3c123440309abc ++ sub.b @(0x1234:16,er3),@0x9abcdef0:32 ;01746e3c123448309abcdef0 ++ ++ sub.b @(0x12345678:32,er3),@er1 ;78346a2c123456780130 ++ sub.b @(0x12345678:32,er3),@(3:2,er1) ;78346a2c123456783130 ++ sub.b @(0x12345678:32,er3),@-er1 ;78346a2c12345678b130 ++ sub.b @(0x12345678:32,er3),@er1+ ;78346a2c123456788130 ++ sub.b @(0x12345678:32,er3),@er1- ;78346a2c12345678a130 ++ sub.b @(0x12345678:32,er3),@+er1 ;78346a2c123456789130 ++ sub.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346a2c12345678c1309abc ++ sub.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346a2c12345678c9309abcdef0 ++ sub.b @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346a2c12345678d2309abc ++ sub.b @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346a2c12345678e2309abc ++ sub.b @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346a2c12345678f2309abc ++ sub.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346a2c12345678da309abcdef0 ++ sub.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346a2c12345678ea309abcdef0 ++ sub.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346a2c12345678fa309abcdef0 ++ sub.b @(0x12345678:32,er3),@0xffff9abc:16 ;78346a2c1234567840309abc ++ sub.b @(0x12345678:32,er3),@0x9abcdef0:32 ;78346a2c1234567848309abcdef0 ++ ++ sub.b @(0x1234:16,r3l.b),@er1 ;01756e3c12340130 ++ sub.b @(0x1234:16,r3l.b),@(3:2,er1) ;01756e3c12343130 ++ sub.b @(0x1234:16,r3l.b),@-er1 ;01756e3c1234b130 ++ sub.b @(0x1234:16,r3l.b),@er1+ ;01756e3c12348130 ++ sub.b @(0x1234:16,r3l.b),@er1- ;01756e3c1234a130 ++ sub.b @(0x1234:16,r3l.b),@+er1 ;01756e3c12349130 ++ sub.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01756e3c1234c1309abc ++ sub.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01756e3c1234c9309abcdef0 ++ sub.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01756e3c1234d2309abc ++ sub.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01756e3c1234e2309abc ++ sub.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01756e3c1234f2309abc ++ sub.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01756e3c1234da309abcdef0 ++ sub.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01756e3c1234ea309abcdef0 ++ sub.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01756e3c1234fa309abcdef0 ++ sub.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;01756e3c123440309abc ++ sub.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01756e3c123448309abcdef0 ++ ++ sub.b @(0x1234:16,r3.w),@er1 ;01766e3c12340130 ++ sub.b @(0x1234:16,r3.w),@(3:2,er1) ;01766e3c12343130 ++ sub.b @(0x1234:16,r3.w),@-er1 ;01766e3c1234b130 ++ sub.b @(0x1234:16,r3.w),@er1+ ;01766e3c12348130 ++ sub.b @(0x1234:16,r3.w),@er1- ;01766e3c1234a130 ++ sub.b @(0x1234:16,r3.w),@+er1 ;01766e3c12349130 ++ sub.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01766e3c1234c1309abc ++ sub.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01766e3c1234c9309abcdef0 ++ sub.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01766e3c1234d2309abc ++ sub.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01766e3c1234e2309abc ++ sub.b @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01766e3c1234f2309abc ++ sub.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01766e3c1234da309abcdef0 ++ sub.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01766e3c1234ea309abcdef0 ++ sub.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01766e3c1234fa309abcdef0 ++ sub.b @(0x1234:16,r3.w),@0xffff9abc:16 ;01766e3c123440309abc ++ sub.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;01766e3c123448309abcdef0 ++ ++ sub.b @(0x1234:16,er3.l),@er1 ;01776e3c12340130 ++ sub.b @(0x1234:16,er3.l),@(3:2,er1) ;01776e3c12343130 ++ sub.b @(0x1234:16,er3.l),@-er1 ;01776e3c1234b130 ++ sub.b @(0x1234:16,er3.l),@er1+ ;01776e3c12348130 ++ sub.b @(0x1234:16,er3.l),@er1- ;01776e3c1234a130 ++ sub.b @(0x1234:16,er3.l),@+er1 ;01776e3c12349130 ++ sub.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01776e3c1234c1309abc ++ sub.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01776e3c1234c9309abcdef0 ++ sub.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01776e3c1234d2309abc ++ sub.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01776e3c1234e2309abc ++ sub.b @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01776e3c1234f2309abc ++ sub.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01776e3c1234da309abcdef0 ++ sub.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01776e3c1234ea309abcdef0 ++ sub.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01776e3c1234fa309abcdef0 ++ sub.b @(0x1234:16,er3.l),@0xffff9abc:16 ;01776e3c123440309abc ++ sub.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;01776e3c123448309abcdef0 ++ ++ sub.b @(0x12345678:32,r3l.b),@er1 ;78356a2c123456780130 ++ sub.b @(0x12345678:32,r3l.b),@(3:2,er1) ;78356a2c123456783130 ++ sub.b @(0x12345678:32,r3l.b),@-er1 ;78356a2c12345678b130 ++ sub.b @(0x12345678:32,r3l.b),@er1+ ;78356a2c123456788130 ++ sub.b @(0x12345678:32,r3l.b),@er1- ;78356a2c12345678a130 ++ sub.b @(0x12345678:32,r3l.b),@+er1 ;78356a2c123456789130 ++ sub.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356a2c12345678c1309abc ++ sub.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356a2c12345678c9309abcdef0 ++ sub.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356a2c12345678d2309abc ++ sub.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356a2c12345678e2309abc ++ sub.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356a2c12345678f2309abc ++ sub.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356a2c12345678da309abcdef0 ++ sub.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356a2c12345678ea309abcdef0 ++ sub.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356a2c12345678fa309abcdef0 ++ sub.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356a2c1234567840309abc ++ sub.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356a2c1234567848309abcdef0 ++ ++ sub.b @(0x12345678:32,r3.w),@er1 ;78366a2c123456780130 ++ sub.b @(0x12345678:32,r3.w),@(3:2,er1) ;78366a2c123456783130 ++ sub.b @(0x12345678:32,r3.w),@-er1 ;78366a2c12345678b130 ++ sub.b @(0x12345678:32,r3.w),@er1+ ;78366a2c123456788130 ++ sub.b @(0x12345678:32,r3.w),@er1- ;78366a2c12345678a130 ++ sub.b @(0x12345678:32,r3.w),@+er1 ;78366a2c123456789130 ++ sub.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366a2c12345678c1309abc ++ sub.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366a2c12345678c9309abcdef0 ++ sub.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366a2c12345678d2309abc ++ sub.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366a2c12345678e2309abc ++ sub.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366a2c12345678f2309abc ++ sub.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366a2c12345678da309abcdef0 ++ sub.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366a2c12345678ea309abcdef0 ++ sub.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366a2c12345678fa309abcdef0 ++ sub.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366a2c1234567840309abc ++ sub.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366a2c1234567848309abcdef0 ++ ++ sub.b @(0x12345678:32,er3.l),@er1 ;78376a2c123456780130 ++ sub.b @(0x12345678:32,er3.l),@(3:2,er1) ;78376a2c123456783130 ++ sub.b @(0x12345678:32,er3.l),@-er1 ;78376a2c12345678b130 ++ sub.b @(0x12345678:32,er3.l),@er1+ ;78376a2c123456788130 ++ sub.b @(0x12345678:32,er3.l),@er1- ;78376a2c12345678a130 ++ sub.b @(0x12345678:32,er3.l),@+er1 ;78376a2c123456789130 ++ sub.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376a2c12345678c1309abc ++ sub.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376a2c12345678c9309abcdef0 ++ sub.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376a2c12345678d2309abc ++ sub.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376a2c12345678e2309abc ++ sub.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376a2c12345678f2309abc ++ sub.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376a2c12345678da309abcdef0 ++ sub.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376a2c12345678ea309abcdef0 ++ sub.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376a2c12345678fa309abcdef0 ++ sub.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376a2c1234567840309abc ++ sub.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376a2c1234567848309abcdef0 ++ ++ sub.b @0x1234:16,@er1 ;6a1512340130 ++ sub.b @0x1234:16,@(3:2,er1) ;6a1512343130 ++ sub.b @0x1234:16,@-er1 ;6a151234b130 ++ sub.b @0x1234:16,@er1+ ;6a1512348130 ++ sub.b @0x1234:16,@er1- ;6a151234a130 ++ sub.b @0x1234:16,@+er1 ;6a1512349130 ++ sub.b @0x1234:16,@(0xffff9abc:16,er1) ;6a151234c1309abc ++ sub.b @0x1234:16,@(0x9abcdef0:32,er1) ;6a151234c9309abcdef0 ++ sub.b @0x1234:16,@(0xffff9abc:16,r2l.b) ;6a151234d2309abc ++ sub.b @0x1234:16,@(0xffff9abc:16,r2.w) ;6a151234e2309abc ++ sub.b @0x1234:16,@(0xffff9abc:16,er2.l) ;6a151234f2309abc ++ sub.b @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6a151234da309abcdef0 ++ sub.b @0x1234:16,@(0x9abcdef0:32,r2.w) ;6a151234ea309abcdef0 ++ sub.b @0x1234:16,@(0x9abcdef0:32,er2.l) ;6a151234fa309abcdef0 ++ sub.b @0x1234:16,@0xffff9abc:16 ;6a15123440309abc ++ sub.b @0x1234:16,@0x9abcdef0:32 ;6a15123448309abcdef0 ++ ++ sub.b @0x12345678:32,@er1 ;6a35123456780130 ++ sub.b @0x12345678:32,@(3:2,er1) ;6a35123456783130 ++ sub.b @0x12345678:32,@-er1 ;6a3512345678b130 ++ sub.b @0x12345678:32,@er1+ ;6a35123456788130 ++ sub.b @0x12345678:32,@er1- ;6a3512345678a130 ++ sub.b @0x12345678:32,@+er1 ;6a35123456789130 ++ sub.b @0x12345678:32,@(0xffff9abc:16,er1) ;6a3512345678c1309abc ++ sub.b @0x12345678:32,@(0x9abcdef0:32,er1) ;6a3512345678c9309abcdef0 ++ sub.b @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6a3512345678d2309abc ++ sub.b @0x12345678:32,@(0xffff9abc:16,r2.w) ;6a3512345678e2309abc ++ sub.b @0x12345678:32,@(0xffff9abc:16,er2.l) ;6a3512345678f2309abc ++ sub.b @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6a3512345678da309abcdef0 ++ sub.b @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6a3512345678ea309abcdef0 ++ sub.b @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6a3512345678fa309abcdef0 ++ sub.b @0x12345678:32,@0xffff9abc:16 ;6a351234567840309abc ++ sub.b @0x12345678:32,@0x9abcdef0:32 ;6a351234567848309abcdef0 ++ ++ sub.w #0x1234:16,r1 ;79311234 ++ sub.w #7:3,r2 ;1a72 ++ sub.w #0x1234:16,@er1 ;015e01301234 ++ sub.w #0x1234:16,@(0x6:2,er1) ;015e31301234 ++ sub.w #0x1234:16,@er1+ ;015e81301234 ++ sub.w #0x1234:16,@-er1 ;015eb1301234 ++ sub.w #0x1234:16,@+er1 ;015e91301234 ++ sub.w #0x1234:16,@er1- ;015ea1301234 ++ sub.w #0x1234:16,@(0xffff9abc:16,er1) ;015ec1309abc1234 ++ sub.w #0x1234:16,@(0x9abcdef0:32,er1) ;015ec9309abcdef01234 ++ sub.w #0x1234:16,@(0xffff9abc:16,r2l.b) ;015ed2309abc1234 ++ sub.w #0x1234:16,@(0xffff9abc:16,r2.w) ;015ee2309abc1234 ++ sub.w #0x1234:16,@(0xffff9abc:16,er2.l) ;015ef2309abc1234 ++ sub.w #0x1234:16,@(0x9abcdef0:32,r2l.b) ;015eda309abcdef01234 ++ sub.w #0x1234:16,@(0x9abcdef0:32,r2.w) ;015eea309abcdef01234 ++ sub.w #0x1234:16,@(0x9abcdef0:32,er2.l) ;015efa309abcdef01234 ++ sub.w #0x1234:16,@0xffff9abc:16 ;015e40309abc1234 ++ sub.w #0x1234:16,@0x9abcdef0:32 ;015e48309abcdef01234 ++ ++ sub.w #0x7:3,@er1 ;7d901a70 ++ sub.w #0x7:3,@0x1234:16 ;6b1812341a70 ++ sub.w #0x7:3,@0x12345678:32 ;6b38123456781a70 ++ ++ sub.w r3,r1 ;1931 ++ ++ sub.w r3,@er1 ;7d901930 ++ sub.w r3,@(0x6:2,er1) ;01593133 ++ sub.w r3,@er1+ ;01598133 ++ sub.w r3,@-er1 ;0159b133 ++ sub.w r3,@+er1 ;01599133 ++ sub.w r3,@er1- ;0159a133 ++ sub.w r3,@(0x1234:16,er1) ;0159c1331234 ++ sub.w r3,@(0x12345678:32,er1) ;0159c93312345678 ++ sub.w r3,@(0x1234:16,r2l.b) ;0159d2331234 ++ sub.w r3,@(0x1234:16,r2.w) ;0159e2331234 ++ sub.w r3,@(0x1234:16,er2.l) ;0159f2331234 ++ sub.w r3,@(0x12345678:32,r2l.b) ;0159da3312345678 ++ sub.w r3,@(0x12345678:32,r2.w) ;0159ea3312345678 ++ sub.w r3,@(0x12345678:32,er2.l) ;0159fa3312345678 ++ sub.w r3,@0x1234:16 ;6b1812341930 ++ sub.w r3,@0x12345678:32 ;6b38123456781930 ++ ++ sub.w @er3,r1 ;7cb01901 ++ sub.w @(0x6:2,er3),r1 ;015a3331 ++ sub.w @er3+,r1 ;015a8331 ++ sub.w @-er3,r1 ;015ab331 ++ sub.w @+er3,r1 ;015a9331 ++ sub.w @er3-,r1 ;015aa331 ++ sub.w @(0x1234:16,er1),r1 ;015ac1311234 ++ sub.w @(0x12345678:32,er1),r1 ;015ac93112345678 ++ sub.w @(0x1234:16,r2l.b),r1 ;015ad2311234 ++ sub.w @(0x1234:16,r2.w),r1 ;015ae2311234 ++ sub.w @(0x1234:16,er2.l),r1 ;015af2311234 ++ sub.w @(0x12345678:32,r2l.b),r1 ;015ada3112345678 ++ sub.w @(0x12345678:32,r2.w),r1 ;015aea3112345678 ++ sub.w @(0x12345678:32,er2.l),r1 ;015afa3112345678 ++ sub.w @0x1234:16,r1 ;6b1012341901 ++ sub.w @0x12345678:32,r1 ;6b30123456781901 ++ ++ sub.w @er3,@er1 ;7cb50130 ++ sub.w @er3,@(6:2,er1) ;7cb53130 ++ sub.w @er3,@-er1 ;7cb5b130 ++ sub.w @er3,@er1+ ;7cb58130 ++ sub.w @er3,@er1- ;7cb5a130 ++ sub.w @er3,@+er1 ;7cb59130 ++ sub.w @er3,@(0xffff9abc:16,er1) ;7cb5c1309abc ++ sub.w @er3,@(0x9abcdef0:32,er1) ;7cb5c9309abcdef0 ++ sub.w @er3,@(0xffff9abc:16,r2l.b) ;7cb5d2309abc ++ sub.w @er3,@(0xffff9abc:16,r2.w) ;7cb5e2309abc ++ sub.w @er3,@(0xffff9abc:16,er2.l) ;7cb5f2309abc ++ sub.w @er3,@(0x9abcdef0:32,r2l.b) ;7cb5da309abcdef0 ++ sub.w @er3,@(0x9abcdef0:32,r2.w) ;7cb5ea309abcdef0 ++ sub.w @er3,@(0x9abcdef0:32,er2.l) ;7cb5fa309abcdef0 ++ sub.w @er3,@0xffff9abc:16 ;7cb540309abc ++ sub.w @er3,@0x9abcdef0:32 ;7cb548309abcdef0 ++ ++ sub.w @-er3,@er1 ;01576d3c0130 ++ sub.w @-er3,@(6:2,er1) ;01576d3c3130 ++ sub.w @-er3,@-er1 ;01576d3cb130 ++ sub.w @-er3,@er1+ ;01576d3c8130 ++ sub.w @-er3,@er1- ;01576d3ca130 ++ sub.w @-er3,@+er1 ;01576d3c9130 ++ sub.w @-er3,@(0xffff9abc:16,er1) ;01576d3cc1309abc ++ sub.w @-er3,@(0x9abcdef0:32,er1) ;01576d3cc9309abcdef0 ++ sub.w @-er3,@(0xffff9abc:16,r2l.b) ;01576d3cd2309abc ++ sub.w @-er3,@(0xffff9abc:16,r2.w) ;01576d3ce2309abc ++ sub.w @-er3,@(0xffff9abc:16,er2.l) ;01576d3cf2309abc ++ sub.w @-er3,@(0x9abcdef0:32,r2l.b) ;01576d3cda309abcdef0 ++ sub.w @-er3,@(0x9abcdef0:32,r2.w) ;01576d3cea309abcdef0 ++ sub.w @-er3,@(0x9abcdef0:32,er2.l) ;01576d3cfa309abcdef0 ++ sub.w @-er3,@0xffff9abc:16 ;01576d3c40309abc ++ sub.w @-er3,@0x9abcdef0:32 ;01576d3c48309abcdef0 ++ ++ sub.w @er3+,@er1 ;01546d3c0130 ++ sub.w @er3+,@(6:2,er1) ;01546d3c3130 ++ sub.w @er3+,@-er1 ;01546d3cb130 ++ sub.w @er3+,@er1+ ;01546d3c8130 ++ sub.w @er3+,@er1- ;01546d3ca130 ++ sub.w @er3+,@+er1 ;01546d3c9130 ++ sub.w @er3+,@(0xffff9abc:16,er1) ;01546d3cc1309abc ++ sub.w @er3+,@(0x9abcdef0:32,er1) ;01546d3cc9309abcdef0 ++ sub.w @er3+,@(0xffff9abc:16,r2l.b) ;01546d3cd2309abc ++ sub.w @er3+,@(0xffff9abc:16,r2.w) ;01546d3ce2309abc ++ sub.w @er3+,@(0xffff9abc:16,er2.l) ;01546d3cf2309abc ++ sub.w @er3+,@(0x9abcdef0:32,r2l.b) ;01546d3cda309abcdef0 ++ sub.w @er3+,@(0x9abcdef0:32,r2.w) ;01546d3cea309abcdef0 ++ sub.w @er3+,@(0x9abcdef0:32,er2.l) ;01546d3cfa309abcdef0 ++ sub.w @er3+,@0xffff9abc:16 ;01546d3c40309abc ++ sub.w @er3+,@0x9abcdef0:32 ;01546d3c48309abcdef0 ++ ++ sub.w @er3-,@er1 ;01566d3c0130 ++ sub.w @er3-,@(6:2,er1) ;01566d3c3130 ++ sub.w @er3-,@-er1 ;01566d3cb130 ++ sub.w @er3-,@er1+ ;01566d3c8130 ++ sub.w @er3-,@er1- ;01566d3ca130 ++ sub.w @er3-,@+er1 ;01566d3c9130 ++ sub.w @er3-,@(0xffff9abc:16,er1) ;01566d3cc1309abc ++ sub.w @er3-,@(0x9abcdef0:32,er1) ;01566d3cc9309abcdef0 ++ sub.w @er3-,@(0xffff9abc:16,r2l.b) ;01566d3cd2309abc ++ sub.w @er3-,@(0xffff9abc:16,r2.w) ;01566d3ce2309abc ++ sub.w @er3-,@(0xffff9abc:16,er2.l) ;01566d3cf2309abc ++ sub.w @er3-,@(0x9abcdef0:32,r2l.b) ;01566d3cda309abcdef0 ++ sub.w @er3-,@(0x9abcdef0:32,r2.w) ;01566d3cea309abcdef0 ++ sub.w @er3-,@(0x9abcdef0:32,er2.l) ;01566d3cfa309abcdef0 ++ sub.w @er3-,@0xffff9abc:16 ;01566d3c40309abc ++ sub.w @er3-,@0x9abcdef0:32 ;01566d3c48309abcdef0 ++ ++ sub.w @+er3,@er1 ;01556d3c0130 ++ sub.w @+er3,@(6:2,er1) ;01556d3c3130 ++ sub.w @+er3,@-er1 ;01556d3cb130 ++ sub.w @+er3,@er1+ ;01556d3c8130 ++ sub.w @+er3,@er1- ;01556d3ca130 ++ sub.w @+er3,@+er1 ;01556d3c9130 ++ sub.w @+er3,@(0xffff9abc:16,er1) ;01556d3cc1309abc ++ sub.w @+er3,@(0x9abcdef0:32,er1) ;01556d3cc9309abcdef0 ++ sub.w @+er3,@(0xffff9abc:16,r2l.b) ;01556d3cd2309abc ++ sub.w @+er3,@(0xffff9abc:16,r2.w) ;01556d3ce2309abc ++ sub.w @+er3,@(0xffff9abc:16,er2.l) ;01556d3cf2309abc ++ sub.w @+er3,@(0x9abcdef0:32,r2l.b) ;01556d3cda309abcdef0 ++ sub.w @+er3,@(0x9abcdef0:32,r2.w) ;01556d3cea309abcdef0 ++ sub.w @+er3,@(0x9abcdef0:32,er2.l) ;01556d3cfa309abcdef0 ++ sub.w @+er3,@0xffff9abc:16 ;01556d3c40309abc ++ sub.w @+er3,@0x9abcdef0:32 ;01556d3c48309abcdef0 ++ ++ sub.w @(0x1234:16,er3),@er1 ;01546f3c12340130 ++ sub.w @(0x1234:16,er3),@(6:2,er1) ;01546f3c12343130 ++ sub.w @(0x1234:16,er3),@-er1 ;01546f3c1234b130 ++ sub.w @(0x1234:16,er3),@er1+ ;01546f3c12348130 ++ sub.w @(0x1234:16,er3),@er1- ;01546f3c1234a130 ++ sub.w @(0x1234:16,er3),@+er1 ;01546f3c12349130 ++ sub.w @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01546f3c1234c1309abc ++ sub.w @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01546f3c1234c9309abcdef0 ++ sub.w @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01546f3c1234d2309abc ++ sub.w @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01546f3c1234e2309abc ++ sub.w @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01546f3c1234f2309abc ++ sub.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01546f3c1234da309abcdef0 ++ sub.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01546f3c1234ea309abcdef0 ++ sub.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01546f3c1234fa309abcdef0 ++ sub.w @(0x1234:16,er3),@0xffff9abc:16 ;01546f3c123440309abc ++ sub.w @(0x1234:16,er3),@0x9abcdef0:32 ;01546f3c123448309abcdef0 ++ ++ sub.w @(0x12345678:32,er3),@er1 ;78346b2c123456780130 ++ sub.w @(0x12345678:32,er3),@(6:2,er1) ;78346b2c123456783130 ++ sub.w @(0x12345678:32,er3),@-er1 ;78346b2c12345678b130 ++ sub.w @(0x12345678:32,er3),@er1+ ;78346b2c123456788130 ++ sub.w @(0x12345678:32,er3),@er1- ;78346b2c12345678a130 ++ sub.w @(0x12345678:32,er3),@+er1 ;78346b2c123456789130 ++ sub.w @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346b2c12345678c1309abc ++ sub.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346b2c12345678c9309abcdef0 ++ sub.w @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346b2c12345678d2309abc ++ sub.w @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346b2c12345678e2309abc ++ sub.w @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346b2c12345678f2309abc ++ sub.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346b2c12345678da309abcdef0 ++ sub.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346b2c12345678ea309abcdef0 ++ sub.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346b2c12345678fa309abcdef0 ++ sub.w @(0x12345678:32,er3),@0xffff9abc:16 ;78346b2c1234567840309abc ++ sub.w @(0x12345678:32,er3),@0x9abcdef0:32 ;78346b2c1234567848309abcdef0 ++ ++ sub.w @(0x1234:16,r3l.b),@er1 ;01556f3c12340130 ++ sub.w @(0x1234:16,r3l.b),@(6:2,er1) ;01556f3c12343130 ++ sub.w @(0x1234:16,r3l.b),@-er1 ;01556f3c1234b130 ++ sub.w @(0x1234:16,r3l.b),@er1+ ;01556f3c12348130 ++ sub.w @(0x1234:16,r3l.b),@er1- ;01556f3c1234a130 ++ sub.w @(0x1234:16,r3l.b),@+er1 ;01556f3c12349130 ++ sub.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01556f3c1234c1309abc ++ sub.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01556f3c1234c9309abcdef0 ++ sub.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01556f3c1234d2309abc ++ sub.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01556f3c1234e2309abc ++ sub.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01556f3c1234f2309abc ++ sub.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01556f3c1234da309abcdef0 ++ sub.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01556f3c1234ea309abcdef0 ++ sub.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01556f3c1234fa309abcdef0 ++ sub.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;01556f3c123440309abc ++ sub.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01556f3c123448309abcdef0 ++ ++ sub.w @(0x1234:16,r3.w),@er1 ;01566f3c12340130 ++ sub.w @(0x1234:16,r3.w),@(6:2,er1) ;01566f3c12343130 ++ sub.w @(0x1234:16,r3.w),@-er1 ;01566f3c1234b130 ++ sub.w @(0x1234:16,r3.w),@er1+ ;01566f3c12348130 ++ sub.w @(0x1234:16,r3.w),@er1- ;01566f3c1234a130 ++ sub.w @(0x1234:16,r3.w),@+er1 ;01566f3c12349130 ++ sub.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01566f3c1234c1309abc ++ sub.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01566f3c1234c9309abcdef0 ++ sub.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01566f3c1234d2309abc ++ sub.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01566f3c1234e2309abc ++ sub.w @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01566f3c1234f2309abc ++ sub.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01566f3c1234da309abcdef0 ++ sub.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01566f3c1234ea309abcdef0 ++ sub.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01566f3c1234fa309abcdef0 ++ sub.w @(0x1234:16,r3.w),@0xffff9abc:16 ;01566f3c123440309abc ++ sub.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;01566f3c123448309abcdef0 ++ ++ sub.w @(0x1234:16,er3.l),@er1 ;01576f3c12340130 ++ sub.w @(0x1234:16,er3.l),@(6:2,er1) ;01576f3c12343130 ++ sub.w @(0x1234:16,er3.l),@-er1 ;01576f3c1234b130 ++ sub.w @(0x1234:16,er3.l),@er1+ ;01576f3c12348130 ++ sub.w @(0x1234:16,er3.l),@er1- ;01576f3c1234a130 ++ sub.w @(0x1234:16,er3.l),@+er1 ;01576f3c12349130 ++ sub.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01576f3c1234c1309abc ++ sub.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01576f3c1234c9309abcdef0 ++ sub.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01576f3c1234d2309abc ++ sub.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01576f3c1234e2309abc ++ sub.w @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01576f3c1234f2309abc ++ sub.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01576f3c1234da309abcdef0 ++ sub.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01576f3c1234ea309abcdef0 ++ sub.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01576f3c1234fa309abcdef0 ++ sub.w @(0x1234:16,er3.l),@0xffff9abc:16 ;01576f3c123440309abc ++ sub.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;01576f3c123448309abcdef0 ++ ++ sub.w @(0x12345678:32,r3l.b),@er1 ;78356b2c123456780130 ++ sub.w @(0x12345678:32,r3l.b),@(6:2,er1) ;78356b2c123456783130 ++ sub.w @(0x12345678:32,r3l.b),@-er1 ;78356b2c12345678b130 ++ sub.w @(0x12345678:32,r3l.b),@er1+ ;78356b2c123456788130 ++ sub.w @(0x12345678:32,r3l.b),@er1- ;78356b2c12345678a130 ++ sub.w @(0x12345678:32,r3l.b),@+er1 ;78356b2c123456789130 ++ sub.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356b2c12345678c1309abc ++ sub.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356b2c12345678c9309abcdef0 ++ sub.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356b2c12345678d2309abc ++ sub.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356b2c12345678e2309abc ++ sub.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356b2c12345678f2309abc ++ sub.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356b2c12345678da309abcdef0 ++ sub.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356b2c12345678ea309abcdef0 ++ sub.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356b2c12345678fa309abcdef0 ++ sub.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356b2c1234567840309abc ++ sub.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356b2c1234567848309abcdef0 ++ ++ sub.w @(0x12345678:32,r3.w),@er1 ;78366b2c123456780130 ++ sub.w @(0x12345678:32,r3.w),@(6:2,er1) ;78366b2c123456783130 ++ sub.w @(0x12345678:32,r3.w),@-er1 ;78366b2c12345678b130 ++ sub.w @(0x12345678:32,r3.w),@er1+ ;78366b2c123456788130 ++ sub.w @(0x12345678:32,r3.w),@er1- ;78366b2c12345678a130 ++ sub.w @(0x12345678:32,r3.w),@+er1 ;78366b2c123456789130 ++ sub.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366b2c12345678c1309abc ++ sub.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366b2c12345678c9309abcdef0 ++ sub.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366b2c12345678d2309abc ++ sub.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366b2c12345678e2309abc ++ sub.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366b2c12345678f2309abc ++ sub.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366b2c12345678da309abcdef0 ++ sub.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366b2c12345678ea309abcdef0 ++ sub.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366b2c12345678fa309abcdef0 ++ sub.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366b2c1234567840309abc ++ sub.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366b2c1234567848309abcdef0 ++ ++ sub.w @(0x12345678:32,er3.l),@er1 ;78376b2c123456780130 ++ sub.w @(0x12345678:32,er3.l),@(6:2,er1) ;78376b2c123456783130 ++ sub.w @(0x12345678:32,er3.l),@-er1 ;78376b2c12345678b130 ++ sub.w @(0x12345678:32,er3.l),@er1+ ;78376b2c123456788130 ++ sub.w @(0x12345678:32,er3.l),@er1- ;78376b2c12345678a130 ++ sub.w @(0x12345678:32,er3.l),@+er1 ;78376b2c123456789130 ++ sub.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376b2c12345678c1309abc ++ sub.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376b2c12345678c9309abcdef0 ++ sub.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376b2c12345678d2309abc ++ sub.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376b2c12345678e2309abc ++ sub.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376b2c12345678f2309abc ++ sub.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376b2c12345678da309abcdef0 ++ sub.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376b2c12345678ea309abcdef0 ++ sub.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376b2c12345678fa309abcdef0 ++ sub.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376b2c1234567840309abc ++ sub.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376b2c1234567848309abcdef0 ++ ++ sub.w @0x1234:16,@er1 ;6b1512340130 ++ sub.w @0x1234:16,@(6:2,er1) ;6b1512343130 ++ sub.w @0x1234:16,@-er1 ;6b151234b130 ++ sub.w @0x1234:16,@er1+ ;6b1512348130 ++ sub.w @0x1234:16,@er1- ;6b151234a130 ++ sub.w @0x1234:16,@+er1 ;6b1512349130 ++ sub.w @0x1234:16,@(0xffff9abc:16,er1) ;6b151234c1309abc ++ sub.w @0x1234:16,@(0x9abcdef0:32,er1) ;6b151234c9309abcdef0 ++ sub.w @0x1234:16,@(0xffff9abc:16,r2l.b) ;6b151234d2309abc ++ sub.w @0x1234:16,@(0xffff9abc:16,r2.w) ;6b151234e2309abc ++ sub.w @0x1234:16,@(0xffff9abc:16,er2.l) ;6b151234f2309abc ++ sub.w @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6b151234da309abcdef0 ++ sub.w @0x1234:16,@(0x9abcdef0:32,r2.w) ;6b151234ea309abcdef0 ++ sub.w @0x1234:16,@(0x9abcdef0:32,er2.l) ;6b151234fa309abcdef0 ++ sub.w @0x1234:16,@0xffff9abc:16 ;6b15123440309abc ++ sub.w @0x1234:16,@0x9abcdef0:32 ;6b15123448309abcdef0 ++ ++ sub.w @0x12345678:32,@er1 ;6b35123456780130 ++ sub.w @0x12345678:32,@(6:2,er1) ;6b35123456783130 ++ sub.w @0x12345678:32,@-er1 ;6b3512345678b130 ++ sub.w @0x12345678:32,@er1+ ;6b35123456788130 ++ sub.w @0x12345678:32,@er1- ;6b3512345678a130 ++ sub.w @0x12345678:32,@+er1 ;6b35123456789130 ++ sub.w @0x12345678:32,@(0xffff9abc:16,er1) ;6b3512345678c1309abc ++ sub.w @0x12345678:32,@(0x9abcdef0:32,er1) ;6b3512345678c9309abcdef0 ++ sub.w @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6b3512345678d2309abc ++ sub.w @0x12345678:32,@(0xffff9abc:16,r2.w) ;6b3512345678e2309abc ++ sub.w @0x12345678:32,@(0xffff9abc:16,er2.l) ;6b3512345678f2309abc ++ sub.w @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6b3512345678da309abcdef0 ++ sub.w @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6b3512345678ea309abcdef0 ++ sub.w @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6b3512345678fa309abcdef0 ++ sub.w @0x12345678:32,@0xffff9abc:16 ;6b351234567840309abc ++ sub.w @0x12345678:32,@0x9abcdef0:32 ;6b351234567848309abcdef0 ++ ++ sub.l #0x12345678:32,er1 ;7a3112345678 ++ sub.l #0x1234:16,er1 ;7a391234 ++ sub.l #0x7:3,er2 ;1afa ++ sub.l #0x12345678:32,@er1 ;010e013812345678 ++ sub.l #0x12345678:32,@(0xc:2,er1) ;010e313812345678 ++ sub.l #0x12345678:32,@er1+ ;010e813812345678 ++ sub.l #0x12345678:32,@-er1 ;010eb13812345678 ++ sub.l #0x12345678:32,@+er1 ;010e913812345678 ++ sub.l #0x12345678:32,@er1- ;010ea13812345678 ++ sub.l #0x12345678:32,@(0xffff9abc:16,er1) ;010ec1389abc12345678 ++ sub.l #0x12345678:32,@(0x9abcdef0:32,er1) ;010ec9389abcdef012345678 ++ sub.l #0x12345678:32,@(0xffff9abc:16,r2l.b) ;010ed2389abc12345678 ++ sub.l #0x12345678:32,@(0xffff9abc:16,r2.w) ;010ee2389abc12345678 ++ sub.l #0x12345678:32,@(0xffff9abc:16,er2.l) ;010ef2389abc12345678 ++ sub.l #0x12345678:32,@(0x9abcdef0:32,r2l.b) ;010eda389abcdef012345678 ++ sub.l #0x12345678:32,@(0x9abcdef0:32,r2.w) ;010eea389abcdef012345678 ++ sub.l #0x12345678:32,@(0x9abcdef0:32,er2.l) ;010efa389abcdef012345678 ++ sub.l #0x12345678:32,@0xffff9abc:16 ;010e40389abc12345678 ++ sub.l #0x12345678:32,@0x9abcdef0:32 ;010e48389abcdef012345678 ++ sub.l #0x1234:16,@er1 ;010e01301234 ++ sub.l #0x1234:16,@(0xc:2,er1) ;010e31301234 ++ sub.l #0x1234:16,@er1+ ;010e81301234 ++ sub.l #0x1234:16,@-er1 ;010eb1301234 ++ sub.l #0x1234:16,@+er1 ;010e91301234 ++ sub.l #0x1234:16,@er1- ;010ea1301234 ++ sub.l #0x1234:16,@(0xffff9abc:16,er1) ;010ec1309abc1234 ++ sub.l #0x1234:16,@(0x9abcdef0:32,er1) ;010ec9309abcdef01234 ++ sub.l #0x1234:16,@(0xffff9abc:16,r2l.b) ;010ed2309abc1234 ++ sub.l #0x1234:16,@(0xffff9abc:16,r2.w) ;010ee2309abc1234 ++ sub.l #0x1234:16,@(0xffff9abc:16,er2.l) ;010ef2309abc1234 ++ sub.l #0x1234:16,@(0x9abcdef0:32,r2l.b) ;010eda309abcdef01234 ++ sub.l #0x1234:16,@(0x9abcdef0:32,r2.w) ;010eea309abcdef01234 ++ sub.l #0x1234:16,@(0x9abcdef0:32,er2.l) ;010efa309abcdef01234 ++ sub.l #0x1234:16,@0xffff9abc:16 ;010e40309abc1234 ++ sub.l #0x1234:16,@0x9abcdef0:32 ;010e48309abcdef01234 ++ ++ sub.l er3,er1 ;1ab1 ++ ++ sub.l er3,@er1 ;01090133 ++ sub.l er3,@(0xc:2,er1) ;01093133 ++ sub.l er3,@er1+ ;01098133 ++ sub.l er3,@-er1 ;0109b133 ++ sub.l er3,@+er1 ;01099133 ++ sub.l er3,@er1- ;0109a133 ++ sub.l er3,@(0x1234:16,er1) ;0109c1331234 ++ sub.l er3,@(0x12345678:32,er1) ;0109c93312345678 ++ sub.l er3,@(0x1234:16,r2l.b) ;0109d2331234 ++ sub.l er3,@(0x1234:16,r2.w) ;0109e2331234 ++ sub.l er3,@(0x1234:16,er2.l) ;0109f2331234 ++ sub.l er3,@(0x12345678:32,r2l.b) ;0109da3312345678 ++ sub.l er3,@(0x12345678:32,r2.w) ;0109ea3312345678 ++ sub.l er3,@(0x12345678:32,er2.l) ;0109fa3312345678 ++ sub.l er3,@0x1234:16 ;010940331234 ++ sub.l er3,@0x12345678:32 ;0109483312345678 ++ ++ sub.l @er3,er1 ;010a0331 ++ sub.l @(0xc:2,er3),er1 ;010a3331 ++ sub.l @er3+,er1 ;010a8331 ++ sub.l @-er3,er1 ;010ab331 ++ sub.l @+er3,er1 ;010a9331 ++ sub.l @er3-,er1 ;010aa331 ++ sub.l @(0x1234:16,er1),er1 ;010ac1311234 ++ sub.l @(0x12345678:32,er1),er1 ;010ac93112345678 ++ sub.l @(0x1234:16,r2l.b),er1 ;010ad2311234 ++ sub.l @(0x1234:16,r2.w),er1 ;010ae2311234 ++ sub.l @(0x1234:16,er2.l),er1 ;010af2311234 ++ sub.l @(0x12345678:32,r2l.b),er1 ;010ada3112345678 ++ sub.l @(0x12345678:32,r2.w),er1 ;010aea3112345678 ++ sub.l @(0x12345678:32,er2.l),er1 ;010afa3112345678 ++ sub.l @0x1234:16,er1 ;010a40311234 ++ sub.l @0x12345678:32,er1 ;010a483112345678 ++ ++ sub.l @er3,@er1 ;0104693c0130 ++ sub.l @er3,@(0xc:2,er1) ;0104693c3130 ++ sub.l @er3,@-er1 ;0104693cb130 ++ sub.l @er3,@er1+ ;0104693c8130 ++ sub.l @er3,@er1- ;0104693ca130 ++ sub.l @er3,@+er1 ;0104693c9130 ++ sub.l @er3,@(0xffff9abc:16,er1) ;0104693cc1309abc ++ sub.l @er3,@(0x9abcdef0:32,er1) ;0104693cc9309abcdef0 ++ sub.l @er3,@(0xffff9abc:16,r2l.b) ;0104693cd2309abc ++ sub.l @er3,@(0xffff9abc:16,r2.w) ;0104693ce2309abc ++ sub.l @er3,@(0xffff9abc:16,er2.l) ;0104693cf2309abc ++ sub.l @er3,@(0x9abcdef0:32,r2l.b) ;0104693cda309abcdef0 ++ sub.l @er3,@(0x9abcdef0:32,r2.w) ;0104693cea309abcdef0 ++ sub.l @er3,@(0x9abcdef0:32,er2.l) ;0104693cfa309abcdef0 ++ sub.l @er3,@0xffff9abc:16 ;0104693c40309abc ++ sub.l @er3,@0x9abcdef0:32 ;0104693c48309abcdef0 ++ ++ sub.l @(0xc:2,er3),@er1 ;0107693c0130 ++ sub.l @(0xc:2,er3),@(0xc:2,er1) ;0107693c3130 ++ sub.l @(0xc:2,er3),@-er1 ;0107693cb130 ++ sub.l @(0xc:2,er3),@er1+ ;0107693c8130 ++ sub.l @(0xc:2,er3),@er1- ;0107693ca130 ++ sub.l @(0xc:2,er3),@+er1 ;0107693c9130 ++ sub.l @(0xc:2,er3),@(0xffff9abc:16,er1) ;0107693cc1309abc ++ sub.l @(0xc:2,er3),@(0x9abcdef0:32,er1) ;0107693cc9309abcdef0 ++ sub.l @(0xc:2,er3),@(0xffff9abc:16,r2l.b) ;0107693cd2309abc ++ sub.l @(0xc:2,er3),@(0xffff9abc:16,r2.w) ;0107693ce2309abc ++ sub.l @(0xc:2,er3),@(0xffff9abc:16,er2.l) ;0107693cf2309abc ++ sub.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b) ;0107693cda309abcdef0 ++ sub.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w) ;0107693cea309abcdef0 ++ sub.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l) ;0107693cfa309abcdef0 ++ sub.l @(0xc:2,er3),@0xffff9abc:16 ;0107693c40309abc ++ sub.l @(0xc:2,er3),@0x9abcdef0:32 ;0107693c48309abcdef0 ++ ++ sub.l @-er3,@er1 ;01076d3c0130 ++ sub.l @-er3,@(0xc:2,er1) ;01076d3c3130 ++ sub.l @-er3,@-er1 ;01076d3cb130 ++ sub.l @-er3,@er1+ ;01076d3c8130 ++ sub.l @-er3,@er1- ;01076d3ca130 ++ sub.l @-er3,@+er1 ;01076d3c9130 ++ sub.l @-er3,@(0xffff9abc:16,er1) ;01076d3cc1309abc ++ sub.l @-er3,@(0x9abcdef0:32,er1) ;01076d3cc9309abcdef0 ++ sub.l @-er3,@(0xffff9abc:16,r2l.b) ;01076d3cd2309abc ++ sub.l @-er3,@(0xffff9abc:16,r2.w) ;01076d3ce2309abc ++ sub.l @-er3,@(0xffff9abc:16,er2.l) ;01076d3cf2309abc ++ sub.l @-er3,@(0x9abcdef0:32,r2l.b) ;01076d3cda309abcdef0 ++ sub.l @-er3,@(0x9abcdef0:32,r2.w) ;01076d3cea309abcdef0 ++ sub.l @-er3,@(0x9abcdef0:32,er2.l) ;01076d3cfa309abcdef0 ++ sub.l @-er3,@0xffff9abc:16 ;01076d3c40309abc ++ sub.l @-er3,@0x9abcdef0:32 ;01076d3c48309abcdef0 ++ ++ sub.l @er3+,@er1 ;01046d3c0130 ++ sub.l @er3+,@(0xc:2,er1) ;01046d3c3130 ++ sub.l @er3+,@-er1 ;01046d3cb130 ++ sub.l @er3+,@er1+ ;01046d3c8130 ++ sub.l @er3+,@er1- ;01046d3ca130 ++ sub.l @er3+,@+er1 ;01046d3c9130 ++ sub.l @er3+,@(0xffff9abc:16,er1) ;01046d3cc1309abc ++ sub.l @er3+,@(0x9abcdef0:32,er1) ;01046d3cc9309abcdef0 ++ sub.l @er3+,@(0xffff9abc:16,r2l.b) ;01046d3cd2309abc ++ sub.l @er3+,@(0xffff9abc:16,r2.w) ;01046d3ce2309abc ++ sub.l @er3+,@(0xffff9abc:16,er2.l) ;01046d3cf2309abc ++ sub.l @er3+,@(0x9abcdef0:32,r2l.b) ;01046d3cda309abcdef0 ++ sub.l @er3+,@(0x9abcdef0:32,r2.w) ;01046d3cea309abcdef0 ++ sub.l @er3+,@(0x9abcdef0:32,er2.l) ;01046d3cfa309abcdef0 ++ sub.l @er3+,@0xffff9abc:16 ;01046d3c40309abc ++ sub.l @er3+,@0x9abcdef0:32 ;01046d3c48309abcdef0 ++ ++ sub.l @er3-,@er1 ;01066d3c0130 ++ sub.l @er3-,@(0xc:2,er1) ;01066d3c3130 ++ sub.l @er3-,@-er1 ;01066d3cb130 ++ sub.l @er3-,@er1+ ;01066d3c8130 ++ sub.l @er3-,@er1- ;01066d3ca130 ++ sub.l @er3-,@+er1 ;01066d3c9130 ++ sub.l @er3-,@(0xffff9abc:16,er1) ;01066d3cc1309abc ++ sub.l @er3-,@(0x9abcdef0:32,er1) ;01066d3cc9309abcdef0 ++ sub.l @er3-,@(0xffff9abc:16,r2l.b) ;01066d3cd2309abc ++ sub.l @er3-,@(0xffff9abc:16,r2.w) ;01066d3ce2309abc ++ sub.l @er3-,@(0xffff9abc:16,er2.l) ;01066d3cf2309abc ++ sub.l @er3-,@(0x9abcdef0:32,r2l.b) ;01066d3cda309abcdef0 ++ sub.l @er3-,@(0x9abcdef0:32,r2.w) ;01066d3cea309abcdef0 ++ sub.l @er3-,@(0x9abcdef0:32,er2.l) ;01066d3cfa309abcdef0 ++ sub.l @er3-,@0xffff9abc:16 ;01066d3c40309abc ++ sub.l @er3-,@0x9abcdef0:32 ;01066d3c48309abcdef0 ++ ++ sub.l @+er3,@er1 ;01056d3c0130 ++ sub.l @+er3,@(0xc:2,er1) ;01056d3c3130 ++ sub.l @+er3,@-er1 ;01056d3cb130 ++ sub.l @+er3,@er1+ ;01056d3c8130 ++ sub.l @+er3,@er1- ;01056d3ca130 ++ sub.l @+er3,@+er1 ;01056d3c9130 ++ sub.l @+er3,@(0xffff9abc:16,er1) ;01056d3cc1309abc ++ sub.l @+er3,@(0x9abcdef0:32,er1) ;01056d3cc9309abcdef0 ++ sub.l @+er3,@(0xffff9abc:16,r2l.b) ;01056d3cd2309abc ++ sub.l @+er3,@(0xffff9abc:16,r2.w) ;01056d3ce2309abc ++ sub.l @+er3,@(0xffff9abc:16,er2.l) ;01056d3cf2309abc ++ sub.l @+er3,@(0x9abcdef0:32,r2l.b) ;01056d3cda309abcdef0 ++ sub.l @+er3,@(0x9abcdef0:32,r2.w) ;01056d3cea309abcdef0 ++ sub.l @+er3,@(0x9abcdef0:32,er2.l) ;01056d3cfa309abcdef0 ++ sub.l @+er3,@0xffff9abc:16 ;01056d3c40309abc ++ sub.l @+er3,@0x9abcdef0:32 ;01056d3c48309abcdef0 ++ ++ sub.l @(0x1234:16,er3),@er1 ;01046f3c12340130 ++ sub.l @(0x1234:16,er3),@(0xc:2,er1) ;01046f3c12343130 ++ sub.l @(0x1234:16,er3),@-er1 ;01046f3c1234b130 ++ sub.l @(0x1234:16,er3),@er1+ ;01046f3c12348130 ++ sub.l @(0x1234:16,er3),@er1- ;01046f3c1234a130 ++ sub.l @(0x1234:16,er3),@+er1 ;01046f3c12349130 ++ sub.l @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01046f3c1234c1309abc ++ sub.l @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01046f3c1234c9309abcdef0 ++ sub.l @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01046f3c1234d2309abc ++ sub.l @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01046f3c1234e2309abc ++ sub.l @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01046f3c1234f2309abc ++ sub.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01046f3c1234da309abcdef0 ++ sub.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01046f3c1234ea309abcdef0 ++ sub.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01046f3c1234fa309abcdef0 ++ sub.l @(0x1234:16,er3),@0xffff9abc:16 ;01046f3c123440309abc ++ sub.l @(0x1234:16,er3),@0x9abcdef0:32 ;01046f3c123448309abcdef0 ++ ++ sub.l @(0x12345678:32,er3),@er1 ;78b46b2c123456780130 ++ sub.l @(0x12345678:32,er3),@(0xc:2,er1) ;78b46b2c123456783130 ++ sub.l @(0x12345678:32,er3),@-er1 ;78b46b2c12345678b130 ++ sub.l @(0x12345678:32,er3),@er1+ ;78b46b2c123456788130 ++ sub.l @(0x12345678:32,er3),@er1- ;78b46b2c12345678a130 ++ sub.l @(0x12345678:32,er3),@+er1 ;78b46b2c123456789130 ++ sub.l @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78b46b2c12345678c1309abc ++ sub.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78b46b2c12345678c9309abcdef0 ++ sub.l @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78b46b2c12345678d2309abc ++ sub.l @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78b46b2c12345678e2309abc ++ sub.l @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78b46b2c12345678f2309abc ++ sub.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78b46b2c12345678da309abcdef0 ++ sub.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78b46b2c12345678ea309abcdef0 ++ sub.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78b46b2c12345678fa309abcdef0 ++ sub.l @(0x12345678:32,er3),@0xffff9abc:16 ;78b46b2c1234567840309abc ++ sub.l @(0x12345678:32,er3),@0x9abcdef0:32 ;78b46b2c1234567848309abcdef0 ++ ++ sub.l @(0x1234:16,r3l.b),@er1 ;01056f3c12340130 ++ sub.l @(0x1234:16,r3l.b),@(0xc:2,er1) ;01056f3c12343130 ++ sub.l @(0x1234:16,r3l.b),@-er1 ;01056f3c1234b130 ++ sub.l @(0x1234:16,r3l.b),@er1+ ;01056f3c12348130 ++ sub.l @(0x1234:16,r3l.b),@er1- ;01056f3c1234a130 ++ sub.l @(0x1234:16,r3l.b),@+er1 ;01056f3c12349130 ++ sub.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01056f3c1234c1309abc ++ sub.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01056f3c1234c9309abcdef0 ++ sub.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01056f3c1234d2309abc ++ sub.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01056f3c1234e2309abc ++ sub.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01056f3c1234f2309abc ++ sub.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01056f3c1234da309abcdef0 ++ sub.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01056f3c1234ea309abcdef0 ++ sub.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01056f3c1234fa309abcdef0 ++ sub.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;01056f3c123440309abc ++ sub.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01056f3c123448309abcdef0 ++ ++ sub.l @(0x1234:16,r3.w),@er1 ;01066f3c12340130 ++ sub.l @(0x1234:16,r3.w),@(0xc:2,er1) ;01066f3c12343130 ++ sub.l @(0x1234:16,r3.w),@-er1 ;01066f3c1234b130 ++ sub.l @(0x1234:16,r3.w),@er1+ ;01066f3c12348130 ++ sub.l @(0x1234:16,r3.w),@er1- ;01066f3c1234a130 ++ sub.l @(0x1234:16,r3.w),@+er1 ;01066f3c12349130 ++ sub.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01066f3c1234c1309abc ++ sub.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01066f3c1234c9309abcdef0 ++ sub.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01066f3c1234d2309abc ++ sub.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01066f3c1234e2309abc ++ sub.l @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01066f3c1234f2309abc ++ sub.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01066f3c1234da309abcdef0 ++ sub.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01066f3c1234ea309abcdef0 ++ sub.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01066f3c1234fa309abcdef0 ++ sub.l @(0x1234:16,r3.w),@0xffff9abc:16 ;01066f3c123440309abc ++ sub.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;01066f3c123448309abcdef0 ++ ++ sub.l @(0x1234:16,er3.l),@er1 ;01076f3c12340130 ++ sub.l @(0x1234:16,er3.l),@(0xc:2,er1) ;01076f3c12343130 ++ sub.l @(0x1234:16,er3.l),@-er1 ;01076f3c1234b130 ++ sub.l @(0x1234:16,er3.l),@er1+ ;01076f3c12348130 ++ sub.l @(0x1234:16,er3.l),@er1- ;01076f3c1234a130 ++ sub.l @(0x1234:16,er3.l),@+er1 ;01076f3c12349130 ++ sub.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01076f3c1234c1309abc ++ sub.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01076f3c1234c9309abcdef0 ++ sub.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01076f3c1234d2309abc ++ sub.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01076f3c1234e2309abc ++ sub.l @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01076f3c1234f2309abc ++ sub.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01076f3c1234da309abcdef0 ++ sub.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01076f3c1234ea309abcdef0 ++ sub.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01076f3c1234fa309abcdef0 ++ sub.l @(0x1234:16,er3.l),@0xffff9abc:16 ;01076f3c123440309abc ++ sub.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;01076f3c123448309abcdef0 ++ ++ sub.l @(0x12345678:32,r3l.b),@er1 ;78b56b2c123456780130 ++ sub.l @(0x12345678:32,r3l.b),@(0xc:2,er1) ;78b56b2c123456783130 ++ sub.l @(0x12345678:32,r3l.b),@-er1 ;78b56b2c12345678b130 ++ sub.l @(0x12345678:32,r3l.b),@er1+ ;78b56b2c123456788130 ++ sub.l @(0x12345678:32,r3l.b),@er1- ;78b56b2c12345678a130 ++ sub.l @(0x12345678:32,r3l.b),@+er1 ;78b56b2c123456789130 ++ sub.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78b56b2c12345678c1309abc ++ sub.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78b56b2c12345678c9309abcdef0 ++ sub.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78b56b2c12345678d2309abc ++ sub.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78b56b2c12345678e2309abc ++ sub.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78b56b2c12345678f2309abc ++ sub.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78b56b2c12345678da309abcdef0 ++ sub.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78b56b2c12345678ea309abcdef0 ++ sub.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78b56b2c12345678fa309abcdef0 ++ sub.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78b56b2c1234567840309abc ++ sub.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78b56b2c1234567848309abcdef0 ++ ++ sub.l @(0x12345678:32,r3.w),@er1 ;78b66b2c123456780130 ++ sub.l @(0x12345678:32,r3.w),@(0xc:2,er1) ;78b66b2c123456783130 ++ sub.l @(0x12345678:32,r3.w),@-er1 ;78b66b2c12345678b130 ++ sub.l @(0x12345678:32,r3.w),@er1+ ;78b66b2c123456788130 ++ sub.l @(0x12345678:32,r3.w),@er1- ;78b66b2c12345678a130 ++ sub.l @(0x12345678:32,r3.w),@+er1 ;78b66b2c123456789130 ++ sub.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78b66b2c12345678c1309abc ++ sub.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78b66b2c12345678c9309abcdef0 ++ sub.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78b66b2c12345678d2309abc ++ sub.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78b66b2c12345678e2309abc ++ sub.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78b66b2c12345678f2309abc ++ sub.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78b66b2c12345678da309abcdef0 ++ sub.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78b66b2c12345678ea309abcdef0 ++ sub.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78b66b2c12345678fa309abcdef0 ++ sub.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;78b66b2c1234567840309abc ++ sub.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78b66b2c1234567848309abcdef0 ++ ++ sub.l @(0x12345678:32,er3.l),@er1 ;78b76b2c123456780130 ++ sub.l @(0x12345678:32,er3.l),@(0xc:2,er1) ;78b76b2c123456783130 ++ sub.l @(0x12345678:32,er3.l),@-er1 ;78b76b2c12345678b130 ++ sub.l @(0x12345678:32,er3.l),@er1+ ;78b76b2c123456788130 ++ sub.l @(0x12345678:32,er3.l),@er1- ;78b76b2c12345678a130 ++ sub.l @(0x12345678:32,er3.l),@+er1 ;78b76b2c123456789130 ++ sub.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78b76b2c12345678c1309abc ++ sub.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78b76b2c12345678c9309abcdef0 ++ sub.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78b76b2c12345678d2309abc ++ sub.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78b76b2c12345678e2309abc ++ sub.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78b76b2c12345678f2309abc ++ sub.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78b76b2c12345678da309abcdef0 ++ sub.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78b76b2c12345678ea309abcdef0 ++ sub.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78b76b2c12345678fa309abcdef0 ++ sub.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;78b76b2c1234567840309abc ++ sub.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78b76b2c1234567848309abcdef0 ++ ++ sub.l @0x1234:16,@er1 ;01046b0c12340130 ++ sub.l @0x1234:16,@(0xc:2,er1) ;01046b0c12343130 ++ sub.l @0x1234:16,@-er1 ;01046b0c1234b130 ++ sub.l @0x1234:16,@er1+ ;01046b0c12348130 ++ sub.l @0x1234:16,@er1- ;01046b0c1234a130 ++ sub.l @0x1234:16,@+er1 ;01046b0c12349130 ++ sub.l @0x1234:16,@(0xffff9abc:16,er1) ;01046b0c1234c1309abc ++ sub.l @0x1234:16,@(0x9abcdef0:32,er1) ;01046b0c1234c9309abcdef0 ++ sub.l @0x1234:16,@(0xffff9abc:16,r2l.b) ;01046b0c1234d2309abc ++ sub.l @0x1234:16,@(0xffff9abc:16,r2.w) ;01046b0c1234e2309abc ++ sub.l @0x1234:16,@(0xffff9abc:16,er2.l) ;01046b0c1234f2309abc ++ sub.l @0x1234:16,@(0x9abcdef0:32,r2l.b) ;01046b0c1234da309abcdef0 ++ sub.l @0x1234:16,@(0x9abcdef0:32,r2.w) ;01046b0c1234ea309abcdef0 ++ sub.l @0x1234:16,@(0x9abcdef0:32,er2.l) ;01046b0c1234fa309abcdef0 ++ sub.l @0x1234:16,@0xffff9abc:16 ;01046b0c123440309abc ++ sub.l @0x1234:16,@0x9abcdef0:32 ;01046b0c123448309abcdef0 ++ ++ sub.l @0x12345678:32,@er1 ;01046b2c123456780130 ++ sub.l @0x12345678:32,@(0xc:2,er1) ;01046b2c123456783130 ++ sub.l @0x12345678:32,@-er1 ;01046b2c12345678b130 ++ sub.l @0x12345678:32,@er1+ ;01046b2c123456788130 ++ sub.l @0x12345678:32,@er1- ;01046b2c12345678a130 ++ sub.l @0x12345678:32,@+er1 ;01046b2c123456789130 ++ sub.l @0x12345678:32,@(0xffff9abc:16,er1) ;01046b2c12345678c1309abc ++ sub.l @0x12345678:32,@(0x9abcdef0:32,er1) ;01046b2c12345678c9309abcdef0 ++ sub.l @0x12345678:32,@(0xffff9abc:16,r2l.b) ;01046b2c12345678d2309abc ++ sub.l @0x12345678:32,@(0xffff9abc:16,r2.w) ;01046b2c12345678e2309abc ++ sub.l @0x12345678:32,@(0xffff9abc:16,er2.l) ;01046b2c12345678f2309abc ++ sub.l @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;01046b2c12345678da309abcdef0 ++ sub.l @0x12345678:32,@(0x9abcdef0:32,r2.w) ;01046b2c12345678ea309abcdef0 ++ sub.l @0x12345678:32,@(0x9abcdef0:32,er2.l) ;01046b2c12345678fa309abcdef0 ++ sub.l @0x12345678:32,@0xffff9abc:16 ;01046b2c1234567840309abc ++ sub.l @0x12345678:32,@0x9abcdef0:32 ;01046b2c1234567848309abcdef0 ++ ++ .end diff --git a/gas/testsuite/gas/h8300/t05_cmp.exp b/gas/testsuite/gas/h8300/t05_cmp.exp new file mode 100644 -index 0000000..9c4a602 +index 0000000..e30cd02 --- /dev/null +++ b/gas/testsuite/gas/h8300/t05_cmp.exp -@@ -0,0 +1,2897 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,2896 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1166527,938 +1173704,937 @@ index 0000000..9c4a602 +} diff --git a/gas/testsuite/gas/h8300/t05_cmp.s b/gas/testsuite/gas/h8300/t05_cmp.s new file mode 100644 -index 0000000..9a2a8f1 +index 0000000..5c2af78 --- /dev/null +++ b/gas/testsuite/gas/h8300/t05_cmp.s @@ -0,0 +1,920 @@ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+;arith_1 -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ .h8300sx -+ .text -+_start: -+ cmp.b @er3,@er1 ;7c350120 -+ cmp.b @er3,@(3:2,er1) ;7c353120 -+ cmp.b @er3,@-er1 ;7c35b120 -+ cmp.b @er3,@er1+ ;7c358120 -+ cmp.b @er3,@er1- ;7c35a120 -+ cmp.b @er3,@+er1 ;7c359120 -+ cmp.b @er3,@(0xffff9abc:16,er1) ;7c35c1209abc -+ cmp.b @er3,@(0x9abcdef0:32,er1) ;7c35c9209abcdef0 -+ cmp.b @er3,@(0xffff9abc:16,r2l.b) ;7c35d2209abc -+ cmp.b @er3,@(0xffff9abc:16,r2.w) ;7c35e2209abc -+ cmp.b @er3,@(0xffff9abc:16,er2.l) ;7c35f2209abc -+ cmp.b @er3,@(0x9abcdef0:32,r2l.b) ;7c35da209abcdef0 -+ cmp.b @er3,@(0x9abcdef0:32,r2.w) ;7c35ea209abcdef0 -+ cmp.b @er3,@(0x9abcdef0:32,er2.l) ;7c35fa209abcdef0 -+ cmp.b @er3,@0xffff9abc:16 ;7c3540209abc -+ cmp.b @er3,@0x9abcdef0:32 ;7c3548209abcdef0 -+ -+ cmp.b @-er3,@er1 ;01776c3c0120 -+ cmp.b @-er3,@(3:2,er1) ;01776c3c3120 -+ cmp.b @-er3,@-er1 ;01776c3cb120 -+ cmp.b @-er3,@er1+ ;01776c3c8120 -+ cmp.b @-er3,@er1- ;01776c3ca120 -+ cmp.b @-er3,@+er1 ;01776c3c9120 -+ cmp.b @-er3,@(0xffff9abc:16,er1) ;01776c3cc1209abc -+ cmp.b @-er3,@(0x9abcdef0:32,er1) ;01776c3cc9209abcdef0 -+ cmp.b @-er3,@(0xffff9abc:16,r2l.b) ;01776c3cd2209abc -+ cmp.b @-er3,@(0xffff9abc:16,r2.w) ;01776c3ce2209abc -+ cmp.b @-er3,@(0xffff9abc:16,er2.l) ;01776c3cf2209abc -+ cmp.b @-er3,@(0x9abcdef0:32,r2l.b) ;01776c3cda209abcdef0 -+ cmp.b @-er3,@(0x9abcdef0:32,r2.w) ;01776c3cea209abcdef0 -+ cmp.b @-er3,@(0x9abcdef0:32,er2.l) ;01776c3cfa209abcdef0 -+ cmp.b @-er3,@0xffff9abc:16 ;01776c3c40209abc -+ cmp.b @-er3,@0x9abcdef0:32 ;01776c3c48209abcdef0 -+ -+ cmp.b @er3+,@er1 ;01746c3c0120 -+ cmp.b @er3+,@(3:2,er1) ;01746c3c3120 -+ cmp.b @er3+,@-er1 ;01746c3cb120 -+ cmp.b @er3+,@er1+ ;01746c3c8120 -+ cmp.b @er3+,@er1- ;01746c3ca120 -+ cmp.b @er3+,@+er1 ;01746c3c9120 -+ cmp.b @er3+,@(0xffff9abc:16,er1) ;01746c3cc1209abc -+ cmp.b @er3+,@(0x9abcdef0:32,er1) ;01746c3cc9209abcdef0 -+ cmp.b @er3+,@(0xffff9abc:16,r2l.b) ;01746c3cd2209abc -+ cmp.b @er3+,@(0xffff9abc:16,r2.w) ;01746c3ce2209abc -+ cmp.b @er3+,@(0xffff9abc:16,er2.l) ;01746c3cf2209abc -+ cmp.b @er3+,@(0x9abcdef0:32,r2l.b) ;01746c3cda209abcdef0 -+ cmp.b @er3+,@(0x9abcdef0:32,r2.w) ;01746c3cea209abcdef0 -+ cmp.b @er3+,@(0x9abcdef0:32,er2.l) ;01746c3cfa209abcdef0 -+ cmp.b @er3+,@0xffff9abc:16 ;01746c3c40209abc -+ cmp.b @er3+,@0x9abcdef0:32 ;01746c3c48209abcdef0 -+ -+ cmp.b @er3-,@er1 ;01766c3c0120 -+ cmp.b @er3-,@(3:2,er1) ;01766c3c3120 -+ cmp.b @er3-,@-er1 ;01766c3cb120 -+ cmp.b @er3-,@er1+ ;01766c3c8120 -+ cmp.b @er3-,@er1- ;01766c3ca120 -+ cmp.b @er3-,@+er1 ;01766c3c9120 -+ cmp.b @er3-,@(0xffff9abc:16,er1) ;01766c3cc1209abc -+ cmp.b @er3-,@(0x9abcdef0:32,er1) ;01766c3cc9209abcdef0 -+ cmp.b @er3-,@(0xffff9abc:16,r2l.b) ;01766c3cd2209abc -+ cmp.b @er3-,@(0xffff9abc:16,r2.w) ;01766c3ce2209abc -+ cmp.b @er3-,@(0xffff9abc:16,er2.l) ;01766c3cf2209abc -+ cmp.b @er3-,@(0x9abcdef0:32,r2l.b) ;01766c3cda209abcdef0 -+ cmp.b @er3-,@(0x9abcdef0:32,r2.w) ;01766c3cea209abcdef0 -+ cmp.b @er3-,@(0x9abcdef0:32,er2.l) ;01766c3cfa209abcdef0 -+ cmp.b @er3-,@0xffff9abc:16 ;01766c3c40209abc -+ cmp.b @er3-,@0x9abcdef0:32 ;01766c3c48209abcdef0 -+ -+ cmp.b @+er3,@er1 ;01756c3c0120 -+ cmp.b @+er3,@(3:2,er1) ;01756c3c3120 -+ cmp.b @+er3,@-er1 ;01756c3cb120 -+ cmp.b @+er3,@er1+ ;01756c3c8120 -+ cmp.b @+er3,@er1- ;01756c3ca120 -+ cmp.b @+er3,@+er1 ;01756c3c9120 -+ cmp.b @+er3,@(0xffff9abc:16,er1) ;01756c3cc1209abc -+ cmp.b @+er3,@(0x9abcdef0:32,er1) ;01756c3cc9209abcdef0 -+ cmp.b @+er3,@(0xffff9abc:16,r2l.b) ;01756c3cd2209abc -+ cmp.b @+er3,@(0xffff9abc:16,r2.w) ;01756c3ce2209abc -+ cmp.b @+er3,@(0xffff9abc:16,er2.l) ;01756c3cf2209abc -+ cmp.b @+er3,@(0x9abcdef0:32,r2l.b) ;01756c3cda209abcdef0 -+ cmp.b @+er3,@(0x9abcdef0:32,r2.w) ;01756c3cea209abcdef0 -+ cmp.b @+er3,@(0x9abcdef0:32,er2.l) ;01756c3cfa209abcdef0 -+ cmp.b @+er3,@0xffff9abc:16 ;01756c3c40209abc -+ cmp.b @+er3,@0x9abcdef0:32 ;01756c3c48209abcdef0 -+ -+ cmp.b @(0x1234:16,er3),@er1 ;01746e3c12340120 -+ cmp.b @(0x1234:16,er3),@(3:2,er1) ;01746e3c12343120 -+ cmp.b @(0x1234:16,er3),@-er1 ;01746e3c1234b120 -+ cmp.b @(0x1234:16,er3),@er1+ ;01746e3c12348120 -+ cmp.b @(0x1234:16,er3),@er1- ;01746e3c1234a120 -+ cmp.b @(0x1234:16,er3),@+er1 ;01746e3c12349120 -+ cmp.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01746e3c1234c1209abc -+ cmp.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01746e3c1234c9209abcdef0 -+ cmp.b @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01746e3c1234d2209abc -+ cmp.b @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01746e3c1234e2209abc -+ cmp.b @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01746e3c1234f2209abc -+ cmp.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01746e3c1234da209abcdef0 -+ cmp.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01746e3c1234ea209abcdef0 -+ cmp.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01746e3c1234fa209abcdef0 -+ cmp.b @(0x1234:16,er3),@0xffff9abc:16 ;01746e3c123440209abc -+ cmp.b @(0x1234:16,er3),@0x9abcdef0:32 ;01746e3c123448209abcdef0 -+ -+ cmp.b @(0x12345678:32,er3),@er1 ;78346a2c123456780120 -+ cmp.b @(0x12345678:32,er3),@(3:2,er1) ;78346a2c123456783120 -+ cmp.b @(0x12345678:32,er3),@-er1 ;78346a2c12345678b120 -+ cmp.b @(0x12345678:32,er3),@er1+ ;78346a2c123456788120 -+ cmp.b @(0x12345678:32,er3),@er1- ;78346a2c12345678a120 -+ cmp.b @(0x12345678:32,er3),@+er1 ;78346a2c123456789120 -+ cmp.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346a2c12345678c1209abc -+ cmp.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346a2c12345678c9209abcdef0 -+ cmp.b @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346a2c12345678d2209abc -+ cmp.b @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346a2c12345678e2209abc -+ cmp.b @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346a2c12345678f2209abc -+ cmp.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346a2c12345678da209abcdef0 -+ cmp.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346a2c12345678ea209abcdef0 -+ cmp.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346a2c12345678fa209abcdef0 -+ cmp.b @(0x12345678:32,er3),@0xffff9abc:16 ;78346a2c1234567840209abc -+ cmp.b @(0x12345678:32,er3),@0x9abcdef0:32 ;78346a2c1234567848209abcdef0 -+ -+ cmp.b @(0x1234:16,r3l.b),@er1 ;01756e3c12340120 -+ cmp.b @(0x1234:16,r3l.b),@(3:2,er1) ;01756e3c12343120 -+ cmp.b @(0x1234:16,r3l.b),@-er1 ;01756e3c1234b120 -+ cmp.b @(0x1234:16,r3l.b),@er1+ ;01756e3c12348120 -+ cmp.b @(0x1234:16,r3l.b),@er1- ;01756e3c1234a120 -+ cmp.b @(0x1234:16,r3l.b),@+er1 ;01756e3c12349120 -+ cmp.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01756e3c1234c1209abc -+ cmp.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01756e3c1234c9209abcdef0 -+ cmp.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01756e3c1234d2209abc -+ cmp.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01756e3c1234e2209abc -+ cmp.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01756e3c1234f2209abc -+ cmp.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01756e3c1234da209abcdef0 -+ cmp.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01756e3c1234ea209abcdef0 -+ cmp.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01756e3c1234fa209abcdef0 -+ cmp.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;01756e3c123440209abc -+ cmp.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01756e3c123448209abcdef0 -+ -+ cmp.b @(0x1234:16,r3.w),@er1 ;01766e3c12340120 -+ cmp.b @(0x1234:16,r3.w),@(3:2,er1) ;01766e3c12343120 -+ cmp.b @(0x1234:16,r3.w),@-er1 ;01766e3c1234b120 -+ cmp.b @(0x1234:16,r3.w),@er1+ ;01766e3c12348120 -+ cmp.b @(0x1234:16,r3.w),@er1- ;01766e3c1234a120 -+ cmp.b @(0x1234:16,r3.w),@+er1 ;01766e3c12349120 -+ cmp.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01766e3c1234c1209abc -+ cmp.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01766e3c1234c9209abcdef0 -+ cmp.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01766e3c1234d2209abc -+ cmp.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01766e3c1234e2209abc -+ cmp.b @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01766e3c1234f2209abc -+ cmp.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01766e3c1234da209abcdef0 -+ cmp.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01766e3c1234ea209abcdef0 -+ cmp.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01766e3c1234fa209abcdef0 -+ cmp.b @(0x1234:16,r3.w),@0xffff9abc:16 ;01766e3c123440209abc -+ cmp.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;01766e3c123448209abcdef0 -+ -+ cmp.b @(0x1234:16,er3.l),@er1 ;01776e3c12340120 -+ cmp.b @(0x1234:16,er3.l),@(3:2,er1) ;01776e3c12343120 -+ cmp.b @(0x1234:16,er3.l),@-er1 ;01776e3c1234b120 -+ cmp.b @(0x1234:16,er3.l),@er1+ ;01776e3c12348120 -+ cmp.b @(0x1234:16,er3.l),@er1- ;01776e3c1234a120 -+ cmp.b @(0x1234:16,er3.l),@+er1 ;01776e3c12349120 -+ cmp.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01776e3c1234c1209abc -+ cmp.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01776e3c1234c9209abcdef0 -+ cmp.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01776e3c1234d2209abc -+ cmp.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01776e3c1234e2209abc -+ cmp.b @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01776e3c1234f2209abc -+ cmp.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01776e3c1234da209abcdef0 -+ cmp.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01776e3c1234ea209abcdef0 -+ cmp.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01776e3c1234fa209abcdef0 -+ cmp.b @(0x1234:16,er3.l),@0xffff9abc:16 ;01776e3c123440209abc -+ cmp.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;01776e3c123448209abcdef0 -+ -+ cmp.b @(0x12345678:32,r3l.b),@er1 ;78356a2c123456780120 -+ cmp.b @(0x12345678:32,r3l.b),@(3:2,er1) ;78356a2c123456783120 -+ cmp.b @(0x12345678:32,r3l.b),@-er1 ;78356a2c12345678b120 -+ cmp.b @(0x12345678:32,r3l.b),@er1+ ;78356a2c123456788120 -+ cmp.b @(0x12345678:32,r3l.b),@er1- ;78356a2c12345678a120 -+ cmp.b @(0x12345678:32,r3l.b),@+er1 ;78356a2c123456789120 -+ cmp.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356a2c12345678c1209abc -+ cmp.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356a2c12345678c9209abcdef0 -+ cmp.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356a2c12345678d2209abc -+ cmp.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356a2c12345678e2209abc -+ cmp.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356a2c12345678f2209abc -+ cmp.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356a2c12345678da209abcdef0 -+ cmp.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356a2c12345678ea209abcdef0 -+ cmp.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356a2c12345678fa209abcdef0 -+ cmp.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356a2c1234567840209abc -+ cmp.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356a2c1234567848209abcdef0 -+ -+ cmp.b @(0x12345678:32,r3.w),@er1 ;78366a2c123456780120 -+ cmp.b @(0x12345678:32,r3.w),@(3:2,er1) ;78366a2c123456783120 -+ cmp.b @(0x12345678:32,r3.w),@-er1 ;78366a2c12345678b120 -+ cmp.b @(0x12345678:32,r3.w),@er1+ ;78366a2c123456788120 -+ cmp.b @(0x12345678:32,r3.w),@er1- ;78366a2c12345678a120 -+ cmp.b @(0x12345678:32,r3.w),@+er1 ;78366a2c123456789120 -+ cmp.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366a2c12345678c1209abc -+ cmp.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366a2c12345678c9209abcdef0 -+ cmp.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366a2c12345678d2209abc -+ cmp.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366a2c12345678e2209abc -+ cmp.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366a2c12345678f2209abc -+ cmp.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366a2c12345678da209abcdef0 -+ cmp.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366a2c12345678ea209abcdef0 -+ cmp.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366a2c12345678fa209abcdef0 -+ cmp.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366a2c1234567840209abc -+ cmp.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366a2c1234567848209abcdef0 -+ -+ cmp.b @(0x12345678:32,er3.l),@er1 ;78376a2c123456780120 -+ cmp.b @(0x12345678:32,er3.l),@(3:2,er1) ;78376a2c123456783120 -+ cmp.b @(0x12345678:32,er3.l),@-er1 ;78376a2c12345678b120 -+ cmp.b @(0x12345678:32,er3.l),@er1+ ;78376a2c123456788120 -+ cmp.b @(0x12345678:32,er3.l),@er1- ;78376a2c12345678a120 -+ cmp.b @(0x12345678:32,er3.l),@+er1 ;78376a2c123456789120 -+ cmp.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376a2c12345678c1209abc -+ cmp.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376a2c12345678c9209abcdef0 -+ cmp.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376a2c12345678d2209abc -+ cmp.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376a2c12345678e2209abc -+ cmp.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376a2c12345678f2209abc -+ cmp.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376a2c12345678da209abcdef0 -+ cmp.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376a2c12345678ea209abcdef0 -+ cmp.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376a2c12345678fa209abcdef0 -+ cmp.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376a2c1234567840209abc -+ cmp.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376a2c1234567848209abcdef0 -+ -+ cmp.b @0x1234:16,@er1 ;6a1512340120 -+ cmp.b @0x1234:16,@(3:2,er1) ;6a1512343120 -+ cmp.b @0x1234:16,@-er1 ;6a151234b120 -+ cmp.b @0x1234:16,@er1+ ;6a1512348120 -+ cmp.b @0x1234:16,@er1- ;6a151234a120 -+ cmp.b @0x1234:16,@+er1 ;6a1512349120 -+ cmp.b @0x1234:16,@(0xffff9abc:16,er1) ;6a151234c1209abc -+ cmp.b @0x1234:16,@(0x9abcdef0:32,er1) ;6a151234c9209abcdef0 -+ cmp.b @0x1234:16,@(0xffff9abc:16,r2l.b) ;6a151234d2209abc -+ cmp.b @0x1234:16,@(0xffff9abc:16,r2.w) ;6a151234e2209abc -+ cmp.b @0x1234:16,@(0xffff9abc:16,er2.l) ;6a151234f2209abc -+ cmp.b @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6a151234da209abcdef0 -+ cmp.b @0x1234:16,@(0x9abcdef0:32,r2.w) ;6a151234ea209abcdef0 -+ cmp.b @0x1234:16,@(0x9abcdef0:32,er2.l) ;6a151234fa209abcdef0 -+ cmp.b @0x1234:16,@0xffff9abc:16 ;6a15123440209abc -+ cmp.b @0x1234:16,@0x9abcdef0:32 ;6a15123448209abcdef0 -+ -+ cmp.b @0x12345678:32,@er1 ;6a35123456780120 -+ cmp.b @0x12345678:32,@(3:2,er1) ;6a35123456783120 -+ cmp.b @0x12345678:32,@-er1 ;6a3512345678b120 -+ cmp.b @0x12345678:32,@er1+ ;6a35123456788120 -+ cmp.b @0x12345678:32,@er1- ;6a3512345678a120 -+ cmp.b @0x12345678:32,@+er1 ;6a35123456789120 -+ cmp.b @0x12345678:32,@(0xffff9abc:16,er1) ;6a3512345678c1209abc -+ cmp.b @0x12345678:32,@(0x9abcdef0:32,er1) ;6a3512345678c9209abcdef0 -+ cmp.b @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6a3512345678d2209abc -+ cmp.b @0x12345678:32,@(0xffff9abc:16,r2.w) ;6a3512345678e2209abc -+ cmp.b @0x12345678:32,@(0xffff9abc:16,er2.l) ;6a3512345678f2209abc -+ cmp.b @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6a3512345678da209abcdef0 -+ cmp.b @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6a3512345678ea209abcdef0 -+ cmp.b @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6a3512345678fa209abcdef0 -+ cmp.b @0x12345678:32,@0xffff9abc:16 ;6a351234567840209abc -+ cmp.b @0x12345678:32,@0x9abcdef0:32 ;6a351234567848209abcdef0 -+ -+ cmp.w #0x1234:16,r1 ;79211234 -+ cmp.w #0x7:3,r2 ;1f72 -+ cmp.w #0x1234:16,@er1 ;015e01201234 -+ cmp.w #0x1234:16,@(0x6:2,er1) ;015e31201234 -+ cmp.w #0x1234:16,@er1+ ;015e81201234 -+ cmp.w #0x1234:16,@-er1 ;015eb1201234 -+ cmp.w #0x1234:16,@+er1 ;015e91201234 -+ cmp.w #0x1234:16,@er1- ;015ea1201234 -+ cmp.w #0x1234:16,@(0xffff9abc:16,er1) ;015ec1209abc1234 -+ cmp.w #0x1234:16,@(0x9abcdef0:32,er1) ;015ec9209abcdef01234 -+ cmp.w #0x1234:16,@(0xffff9abc:16,r2l.b) ;015ed2209abc1234 -+ cmp.w #0x1234:16,@(0xffff9abc:16,r2.w) ;015ee2209abc1234 -+ cmp.w #0x1234:16,@(0xffff9abc:16,er2.l) ;015ef2209abc1234 -+ cmp.w #0x1234:16,@(0x9abcdef0:32,r2l.b) ;015eda209abcdef01234 -+ cmp.w #0x1234:16,@(0x9abcdef0:32,r2.w) ;015eea209abcdef01234 -+ cmp.w #0x1234:16,@(0x9abcdef0:32,er2.l) ;015efa209abcdef01234 -+ cmp.w #0x1234:16,@0xffff9abc:16 ;015e40209abc1234 -+ cmp.w #0x1234:16,@0x9abcdef0:32 ;015e48209abcdef01234 -+ -+ cmp.w #0x7:3,@er1 ;7d901f70 -+ cmp.w #0x7:3,@0x1234:16 ;6b1812341f70 -+ cmp.w #0x7:3,@0x12345678:32 ;6b38123456781f70 -+ -+ cmp.w r3,r1 ;1d31 -+ -+ cmp.w r3,@er1 ;7d901d30 -+ cmp.w r3,@(0x6:2,er1) ;01593123 -+ cmp.w r3,@er1+ ;01598123 -+ cmp.w r3,@-er1 ;0159b123 -+ cmp.w r3,@+er1 ;01599123 -+ cmp.w r3,@er1- ;0159a123 -+ cmp.w r3,@(0x1234:16,er1) ;0159c1231234 -+ cmp.w r3,@(0x12345678:32,er1) ;0159c92312345678 -+ cmp.w r3,@(0x1234:16,r2l.b) ;0159d2231234 -+ cmp.w r3,@(0x1234:16,r2.w) ;0159e2231234 -+ cmp.w r3,@(0x1234:16,er2.l) ;0159f2231234 -+ cmp.w r3,@(0x12345678:32,r2l.b) ;0159da2312345678 -+ cmp.w r3,@(0x12345678:32,r2.w) ;0159ea2312345678 -+ cmp.w r3,@(0x12345678:32,er2.l) ;0159fa2312345678 -+ cmp.w r3,@0x1234:16 ;6b1812341d30 -+ cmp.w r3,@0x12345678:32 ;6b38123456781d30 -+ -+ cmp.w @er3,r1 ;7cb01d01 -+ cmp.w @(0x6:2,er3),r1 ;015a3321 -+ cmp.w @er3+,r1 ;015a8321 -+ cmp.w @-er3,r1 ;015ab321 -+ cmp.w @+er3,r1 ;015a9321 -+ cmp.w @er3-,r1 ;015aa321 -+ cmp.w @(0x1234:16,er1),r1 ;015ac1211234 -+ cmp.w @(0x12345678:32,er1),r1 ;015ac92112345678 -+ cmp.w @(0x1234:16,r2l.b),r1 ;015ad2211234 -+ cmp.w @(0x1234:16,r2.w),r1 ;015ae2211234 -+ cmp.w @(0x1234:16,er2.l),r1 ;015af2211234 -+ cmp.w @(0x12345678:32,r2l.b),r1 ;015ada2112345678 -+ cmp.w @(0x12345678:32,r2.w),r1 ;015aea2112345678 -+ cmp.w @(0x12345678:32,er2.l),r1 ;015afa2112345678 -+ cmp.w @0x1234:16,r1 ;6b1012341d01 -+ cmp.w @0x12345678:32,r1 ;6b30123456781d01 -+ -+ cmp.w @er3,@er1 ;7cb50120 -+ cmp.w @er3,@(6:2,er1) ;7cb53120 -+ cmp.w @er3,@-er1 ;7cb5b120 -+ cmp.w @er3,@er1+ ;7cb58120 -+ cmp.w @er3,@er1- ;7cb5a120 -+ cmp.w @er3,@+er1 ;7cb59120 -+ cmp.w @er3,@(0xffff9abc:16,er1) ;7cb5c1209abc -+ cmp.w @er3,@(0x9abcdef0:32,er1) ;7cb5c9209abcdef0 -+ cmp.w @er3,@(0xffff9abc:16,r2l.b) ;7cb5d2209abc -+ cmp.w @er3,@(0xffff9abc:16,r2.w) ;7cb5e2209abc -+ cmp.w @er3,@(0xffff9abc:16,er2.l) ;7cb5f2209abc -+ cmp.w @er3,@(0x9abcdef0:32,r2l.b) ;7cb5da209abcdef0 -+ cmp.w @er3,@(0x9abcdef0:32,r2.w) ;7cb5ea209abcdef0 -+ cmp.w @er3,@(0x9abcdef0:32,er2.l) ;7cb5fa209abcdef0 -+ cmp.w @er3,@0xffff9abc:16 ;7cb540209abc -+ cmp.w @er3,@0x9abcdef0:32 ;7cb548209abcdef0 -+ -+ cmp.w @-er3,@er1 ;01576d3c0120 -+ cmp.w @-er3,@(6:2,er1) ;01576d3c3120 -+ cmp.w @-er3,@-er1 ;01576d3cb120 -+ cmp.w @-er3,@er1+ ;01576d3c8120 -+ cmp.w @-er3,@er1- ;01576d3ca120 -+ cmp.w @-er3,@+er1 ;01576d3c9120 -+ cmp.w @-er3,@(0xffff9abc:16,er1) ;01576d3cc1209abc -+ cmp.w @-er3,@(0x9abcdef0:32,er1) ;01576d3cc9209abcdef0 -+ cmp.w @-er3,@(0xffff9abc:16,r2l.b) ;01576d3cd2209abc -+ cmp.w @-er3,@(0xffff9abc:16,r2.w) ;01576d3ce2209abc -+ cmp.w @-er3,@(0xffff9abc:16,er2.l) ;01576d3cf2209abc -+ cmp.w @-er3,@(0x9abcdef0:32,r2l.b) ;01576d3cda209abcdef0 -+ cmp.w @-er3,@(0x9abcdef0:32,r2.w) ;01576d3cea209abcdef0 -+ cmp.w @-er3,@(0x9abcdef0:32,er2.l) ;01576d3cfa209abcdef0 -+ cmp.w @-er3,@0xffff9abc:16 ;01576d3c40209abc -+ cmp.w @-er3,@0x9abcdef0:32 ;01576d3c48209abcdef0 -+ -+ cmp.w @er3+,@er1 ;01546d3c0120 -+ cmp.w @er3+,@(6:2,er1) ;01546d3c3120 -+ cmp.w @er3+,@-er1 ;01546d3cb120 -+ cmp.w @er3+,@er1+ ;01546d3c8120 -+ cmp.w @er3+,@er1- ;01546d3ca120 -+ cmp.w @er3+,@+er1 ;01546d3c9120 -+ cmp.w @er3+,@(0xffff9abc:16,er1) ;01546d3cc1209abc -+ cmp.w @er3+,@(0x9abcdef0:32,er1) ;01546d3cc9209abcdef0 -+ cmp.w @er3+,@(0xffff9abc:16,r2l.b) ;01546d3cd2209abc -+ cmp.w @er3+,@(0xffff9abc:16,r2.w) ;01546d3ce2209abc -+ cmp.w @er3+,@(0xffff9abc:16,er2.l) ;01546d3cf2209abc -+ cmp.w @er3+,@(0x9abcdef0:32,r2l.b) ;01546d3cda209abcdef0 -+ cmp.w @er3+,@(0x9abcdef0:32,r2.w) ;01546d3cea209abcdef0 -+ cmp.w @er3+,@(0x9abcdef0:32,er2.l) ;01546d3cfa209abcdef0 -+ cmp.w @er3+,@0xffff9abc:16 ;01546d3c40209abc -+ cmp.w @er3+,@0x9abcdef0:32 ;01546d3c48209abcdef0 -+ -+ cmp.w @er3-,@er1 ;01566d3c0120 -+ cmp.w @er3-,@(6:2,er1) ;01566d3c3120 -+ cmp.w @er3-,@-er1 ;01566d3cb120 -+ cmp.w @er3-,@er1+ ;01566d3c8120 -+ cmp.w @er3-,@er1- ;01566d3ca120 -+ cmp.w @er3-,@+er1 ;01566d3c9120 -+ cmp.w @er3-,@(0xffff9abc:16,er1) ;01566d3cc1209abc -+ cmp.w @er3-,@(0x9abcdef0:32,er1) ;01566d3cc9209abcdef0 -+ cmp.w @er3-,@(0xffff9abc:16,r2l.b) ;01566d3cd2209abc -+ cmp.w @er3-,@(0xffff9abc:16,r2.w) ;01566d3ce2209abc -+ cmp.w @er3-,@(0xffff9abc:16,er2.l) ;01566d3cf2209abc -+ cmp.w @er3-,@(0x9abcdef0:32,r2l.b) ;01566d3cda209abcdef0 -+ cmp.w @er3-,@(0x9abcdef0:32,r2.w) ;01566d3cea209abcdef0 -+ cmp.w @er3-,@(0x9abcdef0:32,er2.l) ;01566d3cfa209abcdef0 -+ cmp.w @er3-,@0xffff9abc:16 ;01566d3c40209abc -+ cmp.w @er3-,@0x9abcdef0:32 ;01566d3c48209abcdef0 -+ -+ cmp.w @+er3,@er1 ;01556d3c0120 -+ cmp.w @+er3,@(6:2,er1) ;01556d3c3120 -+ cmp.w @+er3,@-er1 ;01556d3cb120 -+ cmp.w @+er3,@er1+ ;01556d3c8120 -+ cmp.w @+er3,@er1- ;01556d3ca120 -+ cmp.w @+er3,@+er1 ;01556d3c9120 -+ cmp.w @+er3,@(0xffff9abc:16,er1) ;01556d3cc1209abc -+ cmp.w @+er3,@(0x9abcdef0:32,er1) ;01556d3cc9209abcdef0 -+ cmp.w @+er3,@(0xffff9abc:16,r2l.b) ;01556d3cd2209abc -+ cmp.w @+er3,@(0xffff9abc:16,r2.w) ;01556d3ce2209abc -+ cmp.w @+er3,@(0xffff9abc:16,er2.l) ;01556d3cf2209abc -+ cmp.w @+er3,@(0x9abcdef0:32,r2l.b) ;01556d3cda209abcdef0 -+ cmp.w @+er3,@(0x9abcdef0:32,r2.w) ;01556d3cea209abcdef0 -+ cmp.w @+er3,@(0x9abcdef0:32,er2.l) ;01556d3cfa209abcdef0 -+ cmp.w @+er3,@0xffff9abc:16 ;01556d3c40209abc -+ cmp.w @+er3,@0x9abcdef0:32 ;01556d3c48209abcdef0 -+ -+ cmp.w @(0x1234:16,er3),@er1 ;01546f3c12340120 -+ cmp.w @(0x1234:16,er3),@(6:2,er1) ;01546f3c12343120 -+ cmp.w @(0x1234:16,er3),@-er1 ;01546f3c1234b120 -+ cmp.w @(0x1234:16,er3),@er1+ ;01546f3c12348120 -+ cmp.w @(0x1234:16,er3),@er1- ;01546f3c1234a120 -+ cmp.w @(0x1234:16,er3),@+er1 ;01546f3c12349120 -+ cmp.w @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01546f3c1234c1209abc -+ cmp.w @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01546f3c1234c9209abcdef0 -+ cmp.w @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01546f3c1234d2209abc -+ cmp.w @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01546f3c1234e2209abc -+ cmp.w @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01546f3c1234f2209abc -+ cmp.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01546f3c1234da209abcdef0 -+ cmp.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01546f3c1234ea209abcdef0 -+ cmp.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01546f3c1234fa209abcdef0 -+ cmp.w @(0x1234:16,er3),@0xffff9abc:16 ;01546f3c123440209abc -+ cmp.w @(0x1234:16,er3),@0x9abcdef0:32 ;01546f3c123448209abcdef0 -+ -+ cmp.w @(0x12345678:32,er3),@er1 ;78346b2c123456780120 -+ cmp.w @(0x12345678:32,er3),@(6:2,er1) ;78346b2c123456783120 -+ cmp.w @(0x12345678:32,er3),@-er1 ;78346b2c12345678b120 -+ cmp.w @(0x12345678:32,er3),@er1+ ;78346b2c123456788120 -+ cmp.w @(0x12345678:32,er3),@er1- ;78346b2c12345678a120 -+ cmp.w @(0x12345678:32,er3),@+er1 ;78346b2c123456789120 -+ cmp.w @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346b2c12345678c1209abc -+ cmp.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346b2c12345678c9209abcdef0 -+ cmp.w @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346b2c12345678d2209abc -+ cmp.w @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346b2c12345678e2209abc -+ cmp.w @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346b2c12345678f2209abc -+ cmp.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346b2c12345678da209abcdef0 -+ cmp.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346b2c12345678ea209abcdef0 -+ cmp.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346b2c12345678fa209abcdef0 -+ cmp.w @(0x12345678:32,er3),@0xffff9abc:16 ;78346b2c1234567840209abc -+ cmp.w @(0x12345678:32,er3),@0x9abcdef0:32 ;78346b2c1234567848209abcdef0 -+ -+ cmp.w @(0x1234:16,r3l.b),@er1 ;01556f3c12340120 -+ cmp.w @(0x1234:16,r3l.b),@(6:2,er1) ;01556f3c12343120 -+ cmp.w @(0x1234:16,r3l.b),@-er1 ;01556f3c1234b120 -+ cmp.w @(0x1234:16,r3l.b),@er1+ ;01556f3c12348120 -+ cmp.w @(0x1234:16,r3l.b),@er1- ;01556f3c1234a120 -+ cmp.w @(0x1234:16,r3l.b),@+er1 ;01556f3c12349120 -+ cmp.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01556f3c1234c1209abc -+ cmp.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01556f3c1234c9209abcdef0 -+ cmp.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01556f3c1234d2209abc -+ cmp.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01556f3c1234e2209abc -+ cmp.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01556f3c1234f2209abc -+ cmp.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01556f3c1234da209abcdef0 -+ cmp.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01556f3c1234ea209abcdef0 -+ cmp.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01556f3c1234fa209abcdef0 -+ cmp.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;01556f3c123440209abc -+ cmp.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01556f3c123448209abcdef0 -+ -+ cmp.w @(0x1234:16,r3.w),@er1 ;01566f3c12340120 -+ cmp.w @(0x1234:16,r3.w),@(6:2,er1) ;01566f3c12343120 -+ cmp.w @(0x1234:16,r3.w),@-er1 ;01566f3c1234b120 -+ cmp.w @(0x1234:16,r3.w),@er1+ ;01566f3c12348120 -+ cmp.w @(0x1234:16,r3.w),@er1- ;01566f3c1234a120 -+ cmp.w @(0x1234:16,r3.w),@+er1 ;01566f3c12349120 -+ cmp.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01566f3c1234c1209abc -+ cmp.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01566f3c1234c9209abcdef0 -+ cmp.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01566f3c1234d2209abc -+ cmp.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01566f3c1234e2209abc -+ cmp.w @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01566f3c1234f2209abc -+ cmp.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01566f3c1234da209abcdef0 -+ cmp.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01566f3c1234ea209abcdef0 -+ cmp.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01566f3c1234fa209abcdef0 -+ cmp.w @(0x1234:16,r3.w),@0xffff9abc:16 ;01566f3c123440209abc -+ cmp.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;01566f3c123448209abcdef0 -+ -+ cmp.w @(0x1234:16,er3.l),@er1 ;01576f3c12340120 -+ cmp.w @(0x1234:16,er3.l),@(6:2,er1) ;01576f3c12343120 -+ cmp.w @(0x1234:16,er3.l),@-er1 ;01576f3c1234b120 -+ cmp.w @(0x1234:16,er3.l),@er1+ ;01576f3c12348120 -+ cmp.w @(0x1234:16,er3.l),@er1- ;01576f3c1234a120 -+ cmp.w @(0x1234:16,er3.l),@+er1 ;01576f3c12349120 -+ cmp.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01576f3c1234c1209abc -+ cmp.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01576f3c1234c9209abcdef0 -+ cmp.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01576f3c1234d2209abc -+ cmp.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01576f3c1234e2209abc -+ cmp.w @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01576f3c1234f2209abc -+ cmp.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01576f3c1234da209abcdef0 -+ cmp.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01576f3c1234ea209abcdef0 -+ cmp.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01576f3c1234fa209abcdef0 -+ cmp.w @(0x1234:16,er3.l),@0xffff9abc:16 ;01576f3c123440209abc -+ cmp.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;01576f3c123448209abcdef0 -+ -+ cmp.w @(0x12345678:32,r3l.b),@er1 ;78356b2c123456780120 -+ cmp.w @(0x12345678:32,r3l.b),@(6:2,er1) ;78356b2c123456783120 -+ cmp.w @(0x12345678:32,r3l.b),@-er1 ;78356b2c12345678b120 -+ cmp.w @(0x12345678:32,r3l.b),@er1+ ;78356b2c123456788120 -+ cmp.w @(0x12345678:32,r3l.b),@er1- ;78356b2c12345678a120 -+ cmp.w @(0x12345678:32,r3l.b),@+er1 ;78356b2c123456789120 -+ cmp.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356b2c12345678c1209abc -+ cmp.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356b2c12345678c9209abcdef0 -+ cmp.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356b2c12345678d2209abc -+ cmp.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356b2c12345678e2209abc -+ cmp.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356b2c12345678f2209abc -+ cmp.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356b2c12345678da209abcdef0 -+ cmp.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356b2c12345678ea209abcdef0 -+ cmp.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356b2c12345678fa209abcdef0 -+ cmp.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356b2c1234567840209abc -+ cmp.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356b2c1234567848209abcdef0 -+ -+ cmp.w @(0x12345678:32,r3.w),@er1 ;78366b2c123456780120 -+ cmp.w @(0x12345678:32,r3.w),@(6:2,er1) ;78366b2c123456783120 -+ cmp.w @(0x12345678:32,r3.w),@-er1 ;78366b2c12345678b120 -+ cmp.w @(0x12345678:32,r3.w),@er1+ ;78366b2c123456788120 -+ cmp.w @(0x12345678:32,r3.w),@er1- ;78366b2c12345678a120 -+ cmp.w @(0x12345678:32,r3.w),@+er1 ;78366b2c123456789120 -+ cmp.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366b2c12345678c1209abc -+ cmp.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366b2c12345678c9209abcdef0 -+ cmp.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366b2c12345678d2209abc -+ cmp.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366b2c12345678e2209abc -+ cmp.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366b2c12345678f2209abc -+ cmp.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366b2c12345678da209abcdef0 -+ cmp.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366b2c12345678ea209abcdef0 -+ cmp.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366b2c12345678fa209abcdef0 -+ cmp.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366b2c1234567840209abc -+ cmp.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366b2c1234567848209abcdef0 -+ -+ cmp.w @(0x12345678:32,er3.l),@er1 ;78376b2c123456780120 -+ cmp.w @(0x12345678:32,er3.l),@(6:2,er1) ;78376b2c123456783120 -+ cmp.w @(0x12345678:32,er3.l),@-er1 ;78376b2c12345678b120 -+ cmp.w @(0x12345678:32,er3.l),@er1+ ;78376b2c123456788120 -+ cmp.w @(0x12345678:32,er3.l),@er1- ;78376b2c12345678a120 -+ cmp.w @(0x12345678:32,er3.l),@+er1 ;78376b2c123456789120 -+ cmp.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376b2c12345678c1209abc -+ cmp.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376b2c12345678c9209abcdef0 -+ cmp.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376b2c12345678d2209abc -+ cmp.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376b2c12345678e2209abc -+ cmp.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376b2c12345678f2209abc -+ cmp.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376b2c12345678da209abcdef0 -+ cmp.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376b2c12345678ea209abcdef0 -+ cmp.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376b2c12345678fa209abcdef0 -+ cmp.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376b2c1234567840209abc -+ cmp.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376b2c1234567848209abcdef0 -+ -+ cmp.w @0x1234:16,@er1 ;6b1512340120 -+ cmp.w @0x1234:16,@(6:2,er1) ;6b1512343120 -+ cmp.w @0x1234:16,@-er1 ;6b151234b120 -+ cmp.w @0x1234:16,@er1+ ;6b1512348120 -+ cmp.w @0x1234:16,@er1- ;6b151234a120 -+ cmp.w @0x1234:16,@+er1 ;6b1512349120 -+ cmp.w @0x1234:16,@(0xffff9abc:16,er1) ;6b151234c1209abc -+ cmp.w @0x1234:16,@(0x9abcdef0:32,er1) ;6b151234c9209abcdef0 -+ cmp.w @0x1234:16,@(0xffff9abc:16,r2l.b) ;6b151234d2209abc -+ cmp.w @0x1234:16,@(0xffff9abc:16,r2.w) ;6b151234e2209abc -+ cmp.w @0x1234:16,@(0xffff9abc:16,er2.l) ;6b151234f2209abc -+ cmp.w @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6b151234da209abcdef0 -+ cmp.w @0x1234:16,@(0x9abcdef0:32,r2.w) ;6b151234ea209abcdef0 -+ cmp.w @0x1234:16,@(0x9abcdef0:32,er2.l) ;6b151234fa209abcdef0 -+ cmp.w @0x1234:16,@0xffff9abc:16 ;6b15123440209abc -+ cmp.w @0x1234:16,@0x9abcdef0:32 ;6b15123448209abcdef0 -+ -+ cmp.w @0x12345678:32,@er1 ;6b35123456780120 -+ cmp.w @0x12345678:32,@(6:2,er1) ;6b35123456783120 -+ cmp.w @0x12345678:32,@-er1 ;6b3512345678b120 -+ cmp.w @0x12345678:32,@er1+ ;6b35123456788120 -+ cmp.w @0x12345678:32,@er1- ;6b3512345678a120 -+ cmp.w @0x12345678:32,@+er1 ;6b35123456789120 -+ cmp.w @0x12345678:32,@(0xffff9abc:16,er1) ;6b3512345678c1209abc -+ cmp.w @0x12345678:32,@(0x9abcdef0:32,er1) ;6b3512345678c9209abcdef0 -+ cmp.w @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6b3512345678d2209abc -+ cmp.w @0x12345678:32,@(0xffff9abc:16,r2.w) ;6b3512345678e2209abc -+ cmp.w @0x12345678:32,@(0xffff9abc:16,er2.l) ;6b3512345678f2209abc -+ cmp.w @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6b3512345678da209abcdef0 -+ cmp.w @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6b3512345678ea209abcdef0 -+ cmp.w @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6b3512345678fa209abcdef0 -+ cmp.w @0x12345678:32,@0xffff9abc:16 ;6b351234567840209abc -+ cmp.w @0x12345678:32,@0x9abcdef0:32 ;6b351234567848209abcdef0 -+ -+ cmp.l #0x12345678:32,er1 ;7a2112345678 -+ cmp.l #0x1234:16,er1 ;7a291234 -+ cmp.l #0x7:3,er2 ;1ffa -+ cmp.l #0x12345678:32,@er1 ;010e012812345678 -+ cmp.l #0x12345678:32,@(0xc:2,er1) ;010e312812345678 -+ cmp.l #0x12345678:32,@er1+ ;010e812812345678 -+ cmp.l #0x12345678:32,@-er1 ;010eb12812345678 -+ cmp.l #0x12345678:32,@+er1 ;010e912812345678 -+ cmp.l #0x12345678:32,@er1- ;010ea12812345678 -+ cmp.l #0x12345678:32,@(0xffff9abc:16,er1) ;010ec1289abc12345678 -+ cmp.l #0x12345678:32,@(0x9abcdef0:32,er1) ;010ec9289abcdef012345678 -+ cmp.l #0x12345678:32,@(0xffff9abc:16,r2l.b) ;010ed2289abc12345678 -+ cmp.l #0x12345678:32,@(0xffff9abc:16,r2.w) ;010ee2289abc12345678 -+ cmp.l #0x12345678:32,@(0xffff9abc:16,er2.l) ;010ef2289abc12345678 -+ cmp.l #0x12345678:32,@(0x9abcdef0:32,r2l.b) ;010eda289abcdef012345678 -+ cmp.l #0x12345678:32,@(0x9abcdef0:32,r2.w) ;010eea289abcdef012345678 -+ cmp.l #0x12345678:32,@(0x9abcdef0:32,er2.l) ;010efa289abcdef012345678 -+ cmp.l #0x12345678:32,@0xffff9abc:16 ;010e40289abc12345678 -+ cmp.l #0x12345678:32,@0x9abcdef0:32 ;010e48289abcdef012345678 -+ cmp.l #0x1234:16,@er1 ;010e01201234 -+ cmp.l #0x1234:16,@(0xc:2,er1) ;010e31201234 -+ cmp.l #0x1234:16,@er1+ ;010e81201234 -+ cmp.l #0x1234:16,@-er1 ;010eb1201234 -+ cmp.l #0x1234:16,@+er1 ;010e91201234 -+ cmp.l #0x1234:16,@er1- ;010ea1201234 -+ cmp.l #0x1234:16,@(0xffff9abc:16,er1) ;010ec1209abc1234 -+ cmp.l #0x1234:16,@(0x9abcdef0:32,er1) ;010ec9209abcdef01234 -+ cmp.l #0x1234:16,@(0xffff9abc:16,r2l.b) ;010ed2209abc1234 -+ cmp.l #0x1234:16,@(0xffff9abc:16,r2.w) ;010ee2209abc1234 -+ cmp.l #0x1234:16,@(0xffff9abc:16,er2.l) ;010ef2209abc1234 -+ cmp.l #0x1234:16,@(0x9abcdef0:32,r2l.b) ;010eda209abcdef01234 -+ cmp.l #0x1234:16,@(0x9abcdef0:32,r2.w) ;010eea209abcdef01234 -+ cmp.l #0x1234:16,@(0x9abcdef0:32,er2.l) ;010efa209abcdef01234 -+ cmp.l #0x1234:16,@0xffff9abc:16 ;010e40209abc1234 -+ cmp.l #0x1234:16,@0x9abcdef0:32 ;010e48209abcdef01234 -+ -+ cmp.l er3,er1 ;1fb1 -+ -+ cmp.l er3,@er1 ;01090123 -+ cmp.l er3,@(0xc:2,er1) ;01093123 -+ cmp.l er3,@er1+ ;01098123 -+ cmp.l er3,@-er1 ;0109b123 -+ cmp.l er3,@+er1 ;01099123 -+ cmp.l er3,@er1- ;0109a123 -+ cmp.l er3,@(0x1234:16,er1) ;0109c1231234 -+ cmp.l er3,@(0x12345678:32,er1) ;0109c92312345678 -+ cmp.l er3,@(0x1234:16,r2l.b) ;0109d2231234 -+ cmp.l er3,@(0x1234:16,r2.w) ;0109e2231234 -+ cmp.l er3,@(0x1234:16,er2.l) ;0109f2231234 -+ cmp.l er3,@(0x12345678:32,r2l.b) ;0109da2312345678 -+ cmp.l er3,@(0x12345678:32,r2.w) ;0109ea2312345678 -+ cmp.l er3,@(0x12345678:32,er2.l) ;0109fa2312345678 -+ cmp.l er3,@0x1234:16 ;010940231234 -+ cmp.l er3,@0x12345678:32 ;0109482312345678 -+ -+ cmp.l @er3,er1 ;010a0321 -+ cmp.l @(0xc:2,er3),er1 ;010a3321 -+ cmp.l @er3+,er1 ;010a8321 -+ cmp.l @-er3,er1 ;010ab321 -+ cmp.l @+er3,er1 ;010a9321 -+ cmp.l @er3-,er1 ;010aa321 -+ cmp.l @(0x1234:16,er1),er1 ;010ac1211234 -+ cmp.l @(0x12345678:32,er1),er1 ;010ac92112345678 -+ cmp.l @(0x1234:16,r2l.b),er1 ;010ad2211234 -+ cmp.l @(0x1234:16,r2.w),er1 ;010ae2211234 -+ cmp.l @(0x1234:16,er2.l),er1 ;010af2211234 -+ cmp.l @(0x12345678:32,r2l.b),er1 ;010ada2112345678 -+ cmp.l @(0x12345678:32,r2.w),er1 ;010aea2112345678 -+ cmp.l @(0x12345678:32,er2.l),er1 ;010afa2112345678 -+ cmp.l @0x1234:16,er1 ;010a40211234 -+ cmp.l @0x12345678:32,er1 ;010a482112345678 -+ -+ cmp.l @er3,@er1 ;0104693c0120 -+ cmp.l @er3,@(0xc:2,er1) ;0104693c3120 -+ cmp.l @er3,@-er1 ;0104693cb120 -+ cmp.l @er3,@er1+ ;0104693c8120 -+ cmp.l @er3,@er1- ;0104693ca120 -+ cmp.l @er3,@+er1 ;0104693c9120 -+ cmp.l @er3,@(0xffff9abc:16,er1) ;0104693cc1209abc -+ cmp.l @er3,@(0x9abcdef0:32,er1) ;0104693cc9209abcdef0 -+ cmp.l @er3,@(0xffff9abc:16,r2l.b) ;0104693cd2209abc -+ cmp.l @er3,@(0xffff9abc:16,r2.w) ;0104693ce2209abc -+ cmp.l @er3,@(0xffff9abc:16,er2.l) ;0104693cf2209abc -+ cmp.l @er3,@(0x9abcdef0:32,r2l.b) ;0104693cda209abcdef0 -+ cmp.l @er3,@(0x9abcdef0:32,r2.w) ;0104693cea209abcdef0 -+ cmp.l @er3,@(0x9abcdef0:32,er2.l) ;0104693cfa209abcdef0 -+ cmp.l @er3,@0xffff9abc:16 ;0104693c40209abc -+ cmp.l @er3,@0x9abcdef0:32 ;0104693c48209abcdef0 -+ -+ cmp.l @(0xc:2,er3),@er1 ;0107693c0120 -+ cmp.l @(0xc:2,er3),@(0xc:2,er1) ;0107693c3120 -+ cmp.l @(0xc:2,er3),@-er1 ;0107693cb120 -+ cmp.l @(0xc:2,er3),@er1+ ;0107693c8120 -+ cmp.l @(0xc:2,er3),@er1- ;0107693ca120 -+ cmp.l @(0xc:2,er3),@+er1 ;0107693c9120 -+ cmp.l @(0xc:2,er3),@(0xffff9abc:16,er1) ;0107693cc1209abc -+ cmp.l @(0xc:2,er3),@(0x9abcdef0:32,er1) ;0107693cc9209abcdef0 -+ cmp.l @(0xc:2,er3),@(0xffff9abc:16,r2l.b) ;0107693cd2209abc -+ cmp.l @(0xc:2,er3),@(0xffff9abc:16,r2.w) ;0107693ce2209abc -+ cmp.l @(0xc:2,er3),@(0xffff9abc:16,er2.l) ;0107693cf2209abc -+ cmp.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b) ;0107693cda209abcdef0 -+ cmp.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w) ;0107693cea209abcdef0 -+ cmp.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l) ;0107693cfa209abcdef0 -+ cmp.l @(0xc:2,er3),@0xffff9abc:16 ;0107693c40209abc -+ cmp.l @(0xc:2,er3),@0x9abcdef0:32 ;0107693c48209abcdef0 -+ -+ cmp.l @-er3,@er1 ;01076d3c0120 -+ cmp.l @-er3,@(0xc:2,er1) ;01076d3c3120 -+ cmp.l @-er3,@-er1 ;01076d3cb120 -+ cmp.l @-er3,@er1+ ;01076d3c8120 -+ cmp.l @-er3,@er1- ;01076d3ca120 -+ cmp.l @-er3,@+er1 ;01076d3c9120 -+ cmp.l @-er3,@(0xffff9abc:16,er1) ;01076d3cc1209abc -+ cmp.l @-er3,@(0x9abcdef0:32,er1) ;01076d3cc9209abcdef0 -+ cmp.l @-er3,@(0xffff9abc:16,r2l.b) ;01076d3cd2209abc -+ cmp.l @-er3,@(0xffff9abc:16,r2.w) ;01076d3ce2209abc -+ cmp.l @-er3,@(0xffff9abc:16,er2.l) ;01076d3cf2209abc -+ cmp.l @-er3,@(0x9abcdef0:32,r2l.b) ;01076d3cda209abcdef0 -+ cmp.l @-er3,@(0x9abcdef0:32,r2.w) ;01076d3cea209abcdef0 -+ cmp.l @-er3,@(0x9abcdef0:32,er2.l) ;01076d3cfa209abcdef0 -+ cmp.l @-er3,@0xffff9abc:16 ;01076d3c40209abc -+ cmp.l @-er3,@0x9abcdef0:32 ;01076d3c48209abcdef0 -+ -+ cmp.l @er3+,@er1 ;01046d3c0120 -+ cmp.l @er3+,@(0xc:2,er1) ;01046d3c3120 -+ cmp.l @er3+,@-er1 ;01046d3cb120 -+ cmp.l @er3+,@er1+ ;01046d3c8120 -+ cmp.l @er3+,@er1- ;01046d3ca120 -+ cmp.l @er3+,@+er1 ;01046d3c9120 -+ cmp.l @er3+,@(0xffff9abc:16,er1) ;01046d3cc1209abc -+ cmp.l @er3+,@(0x9abcdef0:32,er1) ;01046d3cc9209abcdef0 -+ cmp.l @er3+,@(0xffff9abc:16,r2l.b) ;01046d3cd2209abc -+ cmp.l @er3+,@(0xffff9abc:16,r2.w) ;01046d3ce2209abc -+ cmp.l @er3+,@(0xffff9abc:16,er2.l) ;01046d3cf2209abc -+ cmp.l @er3+,@(0x9abcdef0:32,r2l.b) ;01046d3cda209abcdef0 -+ cmp.l @er3+,@(0x9abcdef0:32,r2.w) ;01046d3cea209abcdef0 -+ cmp.l @er3+,@(0x9abcdef0:32,er2.l) ;01046d3cfa209abcdef0 -+ cmp.l @er3+,@0xffff9abc:16 ;01046d3c40209abc -+ cmp.l @er3+,@0x9abcdef0:32 ;01046d3c48209abcdef0 -+ -+ cmp.l @er3-,@er1 ;01066d3c0120 -+ cmp.l @er3-,@(0xc:2,er1) ;01066d3c3120 -+ cmp.l @er3-,@-er1 ;01066d3cb120 -+ cmp.l @er3-,@er1+ ;01066d3c8120 -+ cmp.l @er3-,@er1- ;01066d3ca120 -+ cmp.l @er3-,@+er1 ;01066d3c9120 -+ cmp.l @er3-,@(0xffff9abc:16,er1) ;01066d3cc1209abc -+ cmp.l @er3-,@(0x9abcdef0:32,er1) ;01066d3cc9209abcdef0 -+ cmp.l @er3-,@(0xffff9abc:16,r2l.b) ;01066d3cd2209abc -+ cmp.l @er3-,@(0xffff9abc:16,r2.w) ;01066d3ce2209abc -+ cmp.l @er3-,@(0xffff9abc:16,er2.l) ;01066d3cf2209abc -+ cmp.l @er3-,@(0x9abcdef0:32,r2l.b) ;01066d3cda209abcdef0 -+ cmp.l @er3-,@(0x9abcdef0:32,r2.w) ;01066d3cea209abcdef0 -+ cmp.l @er3-,@(0x9abcdef0:32,er2.l) ;01066d3cfa209abcdef0 -+ cmp.l @er3-,@0xffff9abc:16 ;01066d3c40209abc -+ cmp.l @er3-,@0x9abcdef0:32 ;01066d3c48209abcdef0 -+ -+ cmp.l @+er3,@er1 ;01056d3c0120 -+ cmp.l @+er3,@(0xc:2,er1) ;01056d3c3120 -+ cmp.l @+er3,@-er1 ;01056d3cb120 -+ cmp.l @+er3,@er1+ ;01056d3c8120 -+ cmp.l @+er3,@er1- ;01056d3ca120 -+ cmp.l @+er3,@+er1 ;01056d3c9120 -+ cmp.l @+er3,@(0xffff9abc:16,er1) ;01056d3cc1209abc -+ cmp.l @+er3,@(0x9abcdef0:32,er1) ;01056d3cc9209abcdef0 -+ cmp.l @+er3,@(0xffff9abc:16,r2l.b) ;01056d3cd2209abc -+ cmp.l @+er3,@(0xffff9abc:16,r2.w) ;01056d3ce2209abc -+ cmp.l @+er3,@(0xffff9abc:16,er2.l) ;01056d3cf2209abc -+ cmp.l @+er3,@(0x9abcdef0:32,r2l.b) ;01056d3cda209abcdef0 -+ cmp.l @+er3,@(0x9abcdef0:32,r2.w) ;01056d3cea209abcdef0 -+ cmp.l @+er3,@(0x9abcdef0:32,er2.l) ;01056d3cfa209abcdef0 -+ cmp.l @+er3,@0xffff9abc:16 ;01056d3c40209abc -+ cmp.l @+er3,@0x9abcdef0:32 ;01056d3c48209abcdef0 -+ -+ cmp.l @(0x1234:16,er3),@er1 ;01046f3c12340120 -+ cmp.l @(0x1234:16,er3),@(0xc:2,er1) ;01046f3c12343120 -+ cmp.l @(0x1234:16,er3),@-er1 ;01046f3c1234b120 -+ cmp.l @(0x1234:16,er3),@er1+ ;01046f3c12348120 -+ cmp.l @(0x1234:16,er3),@er1- ;01046f3c1234a120 -+ cmp.l @(0x1234:16,er3),@+er1 ;01046f3c12349120 -+ cmp.l @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01046f3c1234c1209abc -+ cmp.l @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01046f3c1234c9209abcdef0 -+ cmp.l @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01046f3c1234d2209abc -+ cmp.l @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01046f3c1234e2209abc -+ cmp.l @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01046f3c1234f2209abc -+ cmp.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01046f3c1234da209abcdef0 -+ cmp.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01046f3c1234ea209abcdef0 -+ cmp.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01046f3c1234fa209abcdef0 -+ cmp.l @(0x1234:16,er3),@0xffff9abc:16 ;01046f3c123440209abc -+ cmp.l @(0x1234:16,er3),@0x9abcdef0:32 ;01046f3c123448209abcdef0 -+ -+ cmp.l @(0x12345678:32,er3),@er1 ;78b46b2c123456780120 -+ cmp.l @(0x12345678:32,er3),@(0xc:2,er1) ;78b46b2c123456783120 -+ cmp.l @(0x12345678:32,er3),@-er1 ;78b46b2c12345678b120 -+ cmp.l @(0x12345678:32,er3),@er1+ ;78b46b2c123456788120 -+ cmp.l @(0x12345678:32,er3),@er1- ;78b46b2c12345678a120 -+ cmp.l @(0x12345678:32,er3),@+er1 ;78b46b2c123456789120 -+ cmp.l @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78b46b2c12345678c1209abc -+ cmp.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78b46b2c12345678c9209abcdef0 -+ cmp.l @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78b46b2c12345678d2209abc -+ cmp.l @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78b46b2c12345678e2209abc -+ cmp.l @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78b46b2c12345678f2209abc -+ cmp.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78b46b2c12345678da209abcdef0 -+ cmp.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78b46b2c12345678ea209abcdef0 -+ cmp.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78b46b2c12345678fa209abcdef0 -+ cmp.l @(0x12345678:32,er3),@0xffff9abc:16 ;78b46b2c1234567840209abc -+ cmp.l @(0x12345678:32,er3),@0x9abcdef0:32 ;78b46b2c1234567848209abcdef0 -+ -+ cmp.l @(0x1234:16,r3l.b),@er1 ;01056f3c12340120 -+ cmp.l @(0x1234:16,r3l.b),@(0xc:2,er1) ;01056f3c12343120 -+ cmp.l @(0x1234:16,r3l.b),@-er1 ;01056f3c1234b120 -+ cmp.l @(0x1234:16,r3l.b),@er1+ ;01056f3c12348120 -+ cmp.l @(0x1234:16,r3l.b),@er1- ;01056f3c1234a120 -+ cmp.l @(0x1234:16,r3l.b),@+er1 ;01056f3c12349120 -+ cmp.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01056f3c1234c1209abc -+ cmp.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01056f3c1234c9209abcdef0 -+ cmp.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01056f3c1234d2209abc -+ cmp.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01056f3c1234e2209abc -+ cmp.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01056f3c1234f2209abc -+ cmp.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01056f3c1234da209abcdef0 -+ cmp.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01056f3c1234ea209abcdef0 -+ cmp.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01056f3c1234fa209abcdef0 -+ cmp.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;01056f3c123440209abc -+ cmp.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01056f3c123448209abcdef0 -+ -+ cmp.l @(0x1234:16,r3.w),@er1 ;01066f3c12340120 -+ cmp.l @(0x1234:16,r3.w),@(0xc:2,er1) ;01066f3c12343120 -+ cmp.l @(0x1234:16,r3.w),@-er1 ;01066f3c1234b120 -+ cmp.l @(0x1234:16,r3.w),@er1+ ;01066f3c12348120 -+ cmp.l @(0x1234:16,r3.w),@er1- ;01066f3c1234a120 -+ cmp.l @(0x1234:16,r3.w),@+er1 ;01066f3c12349120 -+ cmp.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01066f3c1234c1209abc -+ cmp.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01066f3c1234c9209abcdef0 -+ cmp.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01066f3c1234d2209abc -+ cmp.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01066f3c1234e2209abc -+ cmp.l @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01066f3c1234f2209abc -+ cmp.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01066f3c1234da209abcdef0 -+ cmp.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01066f3c1234ea209abcdef0 -+ cmp.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01066f3c1234fa209abcdef0 -+ cmp.l @(0x1234:16,r3.w),@0xffff9abc:16 ;01066f3c123440209abc -+ cmp.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;01066f3c123448209abcdef0 -+ -+ cmp.l @(0x1234:16,er3.l),@er1 ;01076f3c12340120 -+ cmp.l @(0x1234:16,er3.l),@(0xc:2,er1) ;01076f3c12343120 -+ cmp.l @(0x1234:16,er3.l),@-er1 ;01076f3c1234b120 -+ cmp.l @(0x1234:16,er3.l),@er1+ ;01076f3c12348120 -+ cmp.l @(0x1234:16,er3.l),@er1- ;01076f3c1234a120 -+ cmp.l @(0x1234:16,er3.l),@+er1 ;01076f3c12349120 -+ cmp.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01076f3c1234c1209abc -+ cmp.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01076f3c1234c9209abcdef0 -+ cmp.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01076f3c1234d2209abc -+ cmp.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01076f3c1234e2209abc -+ cmp.l @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01076f3c1234f2209abc -+ cmp.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01076f3c1234da209abcdef0 -+ cmp.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01076f3c1234ea209abcdef0 -+ cmp.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01076f3c1234fa209abcdef0 -+ cmp.l @(0x1234:16,er3.l),@0xffff9abc:16 ;01076f3c123440209abc -+ cmp.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;01076f3c123448209abcdef0 -+ -+ cmp.l @(0x12345678:32,r3l.b),@er1 ;78b56b2c123456780120 -+ cmp.l @(0x12345678:32,r3l.b),@(0xc:2,er1) ;78b56b2c123456783120 -+ cmp.l @(0x12345678:32,r3l.b),@-er1 ;78b56b2c12345678b120 -+ cmp.l @(0x12345678:32,r3l.b),@er1+ ;78b56b2c123456788120 -+ cmp.l @(0x12345678:32,r3l.b),@er1- ;78b56b2c12345678a120 -+ cmp.l @(0x12345678:32,r3l.b),@+er1 ;78b56b2c123456789120 -+ cmp.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78b56b2c12345678c1209abc -+ cmp.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78b56b2c12345678c9209abcdef0 -+ cmp.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78b56b2c12345678d2209abc -+ cmp.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78b56b2c12345678e2209abc -+ cmp.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78b56b2c12345678f2209abc -+ cmp.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78b56b2c12345678da209abcdef0 -+ cmp.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78b56b2c12345678ea209abcdef0 -+ cmp.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78b56b2c12345678fa209abcdef0 -+ cmp.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78b56b2c1234567840209abc -+ cmp.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78b56b2c1234567848209abcdef0 -+ -+ cmp.l @(0x12345678:32,r3.w),@er1 ;78b66b2c123456780120 -+ cmp.l @(0x12345678:32,r3.w),@(0xc:2,er1) ;78b66b2c123456783120 -+ cmp.l @(0x12345678:32,r3.w),@-er1 ;78b66b2c12345678b120 -+ cmp.l @(0x12345678:32,r3.w),@er1+ ;78b66b2c123456788120 -+ cmp.l @(0x12345678:32,r3.w),@er1- ;78b66b2c12345678a120 -+ cmp.l @(0x12345678:32,r3.w),@+er1 ;78b66b2c123456789120 -+ cmp.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78b66b2c12345678c1209abc -+ cmp.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78b66b2c12345678c9209abcdef0 -+ cmp.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78b66b2c12345678d2209abc -+ cmp.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78b66b2c12345678e2209abc -+ cmp.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78b66b2c12345678f2209abc -+ cmp.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78b66b2c12345678da209abcdef0 -+ cmp.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78b66b2c12345678ea209abcdef0 -+ cmp.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78b66b2c12345678fa209abcdef0 -+ cmp.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;78b66b2c1234567840209abc -+ cmp.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78b66b2c1234567848209abcdef0 -+ -+ cmp.l @(0x12345678:32,er3.l),@er1 ;78b76b2c123456780120 -+ cmp.l @(0x12345678:32,er3.l),@(0xc:2,er1) ;78b76b2c123456783120 -+ cmp.l @(0x12345678:32,er3.l),@-er1 ;78b76b2c12345678b120 -+ cmp.l @(0x12345678:32,er3.l),@er1+ ;78b76b2c123456788120 -+ cmp.l @(0x12345678:32,er3.l),@er1- ;78b76b2c12345678a120 -+ cmp.l @(0x12345678:32,er3.l),@+er1 ;78b76b2c123456789120 -+ cmp.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78b76b2c12345678c1209abc -+ cmp.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78b76b2c12345678c9209abcdef0 -+ cmp.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78b76b2c12345678d2209abc -+ cmp.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78b76b2c12345678e2209abc -+ cmp.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78b76b2c12345678f2209abc -+ cmp.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78b76b2c12345678da209abcdef0 -+ cmp.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78b76b2c12345678ea209abcdef0 -+ cmp.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78b76b2c12345678fa209abcdef0 -+ cmp.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;78b76b2c1234567840209abc -+ cmp.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78b76b2c1234567848209abcdef0 -+ -+ cmp.l @0x1234:16,@er1 ;01046b0c12340120 -+ cmp.l @0x1234:16,@(0xc:2,er1) ;01046b0c12343120 -+ cmp.l @0x1234:16,@-er1 ;01046b0c1234b120 -+ cmp.l @0x1234:16,@er1+ ;01046b0c12348120 -+ cmp.l @0x1234:16,@er1- ;01046b0c1234a120 -+ cmp.l @0x1234:16,@+er1 ;01046b0c12349120 -+ cmp.l @0x1234:16,@(0xffff9abc:16,er1) ;01046b0c1234c1209abc -+ cmp.l @0x1234:16,@(0x9abcdef0:32,er1) ;01046b0c1234c9209abcdef0 -+ cmp.l @0x1234:16,@(0xffff9abc:16,r2l.b) ;01046b0c1234d2209abc -+ cmp.l @0x1234:16,@(0xffff9abc:16,r2.w) ;01046b0c1234e2209abc -+ cmp.l @0x1234:16,@(0xffff9abc:16,er2.l) ;01046b0c1234f2209abc -+ cmp.l @0x1234:16,@(0x9abcdef0:32,r2l.b) ;01046b0c1234da209abcdef0 -+ cmp.l @0x1234:16,@(0x9abcdef0:32,r2.w) ;01046b0c1234ea209abcdef0 -+ cmp.l @0x1234:16,@(0x9abcdef0:32,er2.l) ;01046b0c1234fa209abcdef0 -+ cmp.l @0x1234:16,@0xffff9abc:16 ;01046b0c123440209abc -+ cmp.l @0x1234:16,@0x9abcdef0:32 ;01046b0c123448209abcdef0 -+ -+ cmp.l @0x12345678:32,@er1 ;01046b2c123456780120 -+ cmp.l @0x12345678:32,@(0xc:2,er1) ;01046b2c123456783120 -+ cmp.l @0x12345678:32,@-er1 ;01046b2c12345678b120 -+ cmp.l @0x12345678:32,@er1+ ;01046b2c123456788120 -+ cmp.l @0x12345678:32,@er1- ;01046b2c12345678a120 -+ cmp.l @0x12345678:32,@+er1 ;01046b2c123456789120 -+ cmp.l @0x12345678:32,@(0xffff9abc:16,er1) ;01046b2c12345678c1209abc -+ cmp.l @0x12345678:32,@(0x9abcdef0:32,er1) ;01046b2c12345678c9209abcdef0 -+ cmp.l @0x12345678:32,@(0xffff9abc:16,r2l.b) ;01046b2c12345678d2209abc -+ cmp.l @0x12345678:32,@(0xffff9abc:16,r2.w) ;01046b2c12345678e2209abc -+ cmp.l @0x12345678:32,@(0xffff9abc:16,er2.l) ;01046b2c12345678f2209abc -+ cmp.l @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;01046b2c12345678da209abcdef0 -+ cmp.l @0x12345678:32,@(0x9abcdef0:32,r2.w) ;01046b2c12345678ea209abcdef0 -+ cmp.l @0x12345678:32,@(0x9abcdef0:32,er2.l) ;01046b2c12345678fa209abcdef0 -+ cmp.l @0x12345678:32,@0xffff9abc:16 ;01046b2c1234567840209abc -+ cmp.l @0x12345678:32,@0x9abcdef0:32 ;01046b2c1234567848209abcdef0 -+ -+ .end ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;arith_1 ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ .h8300sx ++ .text ++_start: ++ cmp.b @er3,@er1 ;7c350120 ++ cmp.b @er3,@(3:2,er1) ;7c353120 ++ cmp.b @er3,@-er1 ;7c35b120 ++ cmp.b @er3,@er1+ ;7c358120 ++ cmp.b @er3,@er1- ;7c35a120 ++ cmp.b @er3,@+er1 ;7c359120 ++ cmp.b @er3,@(0xffff9abc:16,er1) ;7c35c1209abc ++ cmp.b @er3,@(0x9abcdef0:32,er1) ;7c35c9209abcdef0 ++ cmp.b @er3,@(0xffff9abc:16,r2l.b) ;7c35d2209abc ++ cmp.b @er3,@(0xffff9abc:16,r2.w) ;7c35e2209abc ++ cmp.b @er3,@(0xffff9abc:16,er2.l) ;7c35f2209abc ++ cmp.b @er3,@(0x9abcdef0:32,r2l.b) ;7c35da209abcdef0 ++ cmp.b @er3,@(0x9abcdef0:32,r2.w) ;7c35ea209abcdef0 ++ cmp.b @er3,@(0x9abcdef0:32,er2.l) ;7c35fa209abcdef0 ++ cmp.b @er3,@0xffff9abc:16 ;7c3540209abc ++ cmp.b @er3,@0x9abcdef0:32 ;7c3548209abcdef0 ++ ++ cmp.b @-er3,@er1 ;01776c3c0120 ++ cmp.b @-er3,@(3:2,er1) ;01776c3c3120 ++ cmp.b @-er3,@-er1 ;01776c3cb120 ++ cmp.b @-er3,@er1+ ;01776c3c8120 ++ cmp.b @-er3,@er1- ;01776c3ca120 ++ cmp.b @-er3,@+er1 ;01776c3c9120 ++ cmp.b @-er3,@(0xffff9abc:16,er1) ;01776c3cc1209abc ++ cmp.b @-er3,@(0x9abcdef0:32,er1) ;01776c3cc9209abcdef0 ++ cmp.b @-er3,@(0xffff9abc:16,r2l.b) ;01776c3cd2209abc ++ cmp.b @-er3,@(0xffff9abc:16,r2.w) ;01776c3ce2209abc ++ cmp.b @-er3,@(0xffff9abc:16,er2.l) ;01776c3cf2209abc ++ cmp.b @-er3,@(0x9abcdef0:32,r2l.b) ;01776c3cda209abcdef0 ++ cmp.b @-er3,@(0x9abcdef0:32,r2.w) ;01776c3cea209abcdef0 ++ cmp.b @-er3,@(0x9abcdef0:32,er2.l) ;01776c3cfa209abcdef0 ++ cmp.b @-er3,@0xffff9abc:16 ;01776c3c40209abc ++ cmp.b @-er3,@0x9abcdef0:32 ;01776c3c48209abcdef0 ++ ++ cmp.b @er3+,@er1 ;01746c3c0120 ++ cmp.b @er3+,@(3:2,er1) ;01746c3c3120 ++ cmp.b @er3+,@-er1 ;01746c3cb120 ++ cmp.b @er3+,@er1+ ;01746c3c8120 ++ cmp.b @er3+,@er1- ;01746c3ca120 ++ cmp.b @er3+,@+er1 ;01746c3c9120 ++ cmp.b @er3+,@(0xffff9abc:16,er1) ;01746c3cc1209abc ++ cmp.b @er3+,@(0x9abcdef0:32,er1) ;01746c3cc9209abcdef0 ++ cmp.b @er3+,@(0xffff9abc:16,r2l.b) ;01746c3cd2209abc ++ cmp.b @er3+,@(0xffff9abc:16,r2.w) ;01746c3ce2209abc ++ cmp.b @er3+,@(0xffff9abc:16,er2.l) ;01746c3cf2209abc ++ cmp.b @er3+,@(0x9abcdef0:32,r2l.b) ;01746c3cda209abcdef0 ++ cmp.b @er3+,@(0x9abcdef0:32,r2.w) ;01746c3cea209abcdef0 ++ cmp.b @er3+,@(0x9abcdef0:32,er2.l) ;01746c3cfa209abcdef0 ++ cmp.b @er3+,@0xffff9abc:16 ;01746c3c40209abc ++ cmp.b @er3+,@0x9abcdef0:32 ;01746c3c48209abcdef0 ++ ++ cmp.b @er3-,@er1 ;01766c3c0120 ++ cmp.b @er3-,@(3:2,er1) ;01766c3c3120 ++ cmp.b @er3-,@-er1 ;01766c3cb120 ++ cmp.b @er3-,@er1+ ;01766c3c8120 ++ cmp.b @er3-,@er1- ;01766c3ca120 ++ cmp.b @er3-,@+er1 ;01766c3c9120 ++ cmp.b @er3-,@(0xffff9abc:16,er1) ;01766c3cc1209abc ++ cmp.b @er3-,@(0x9abcdef0:32,er1) ;01766c3cc9209abcdef0 ++ cmp.b @er3-,@(0xffff9abc:16,r2l.b) ;01766c3cd2209abc ++ cmp.b @er3-,@(0xffff9abc:16,r2.w) ;01766c3ce2209abc ++ cmp.b @er3-,@(0xffff9abc:16,er2.l) ;01766c3cf2209abc ++ cmp.b @er3-,@(0x9abcdef0:32,r2l.b) ;01766c3cda209abcdef0 ++ cmp.b @er3-,@(0x9abcdef0:32,r2.w) ;01766c3cea209abcdef0 ++ cmp.b @er3-,@(0x9abcdef0:32,er2.l) ;01766c3cfa209abcdef0 ++ cmp.b @er3-,@0xffff9abc:16 ;01766c3c40209abc ++ cmp.b @er3-,@0x9abcdef0:32 ;01766c3c48209abcdef0 ++ ++ cmp.b @+er3,@er1 ;01756c3c0120 ++ cmp.b @+er3,@(3:2,er1) ;01756c3c3120 ++ cmp.b @+er3,@-er1 ;01756c3cb120 ++ cmp.b @+er3,@er1+ ;01756c3c8120 ++ cmp.b @+er3,@er1- ;01756c3ca120 ++ cmp.b @+er3,@+er1 ;01756c3c9120 ++ cmp.b @+er3,@(0xffff9abc:16,er1) ;01756c3cc1209abc ++ cmp.b @+er3,@(0x9abcdef0:32,er1) ;01756c3cc9209abcdef0 ++ cmp.b @+er3,@(0xffff9abc:16,r2l.b) ;01756c3cd2209abc ++ cmp.b @+er3,@(0xffff9abc:16,r2.w) ;01756c3ce2209abc ++ cmp.b @+er3,@(0xffff9abc:16,er2.l) ;01756c3cf2209abc ++ cmp.b @+er3,@(0x9abcdef0:32,r2l.b) ;01756c3cda209abcdef0 ++ cmp.b @+er3,@(0x9abcdef0:32,r2.w) ;01756c3cea209abcdef0 ++ cmp.b @+er3,@(0x9abcdef0:32,er2.l) ;01756c3cfa209abcdef0 ++ cmp.b @+er3,@0xffff9abc:16 ;01756c3c40209abc ++ cmp.b @+er3,@0x9abcdef0:32 ;01756c3c48209abcdef0 ++ ++ cmp.b @(0x1234:16,er3),@er1 ;01746e3c12340120 ++ cmp.b @(0x1234:16,er3),@(3:2,er1) ;01746e3c12343120 ++ cmp.b @(0x1234:16,er3),@-er1 ;01746e3c1234b120 ++ cmp.b @(0x1234:16,er3),@er1+ ;01746e3c12348120 ++ cmp.b @(0x1234:16,er3),@er1- ;01746e3c1234a120 ++ cmp.b @(0x1234:16,er3),@+er1 ;01746e3c12349120 ++ cmp.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01746e3c1234c1209abc ++ cmp.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01746e3c1234c9209abcdef0 ++ cmp.b @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01746e3c1234d2209abc ++ cmp.b @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01746e3c1234e2209abc ++ cmp.b @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01746e3c1234f2209abc ++ cmp.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01746e3c1234da209abcdef0 ++ cmp.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01746e3c1234ea209abcdef0 ++ cmp.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01746e3c1234fa209abcdef0 ++ cmp.b @(0x1234:16,er3),@0xffff9abc:16 ;01746e3c123440209abc ++ cmp.b @(0x1234:16,er3),@0x9abcdef0:32 ;01746e3c123448209abcdef0 ++ ++ cmp.b @(0x12345678:32,er3),@er1 ;78346a2c123456780120 ++ cmp.b @(0x12345678:32,er3),@(3:2,er1) ;78346a2c123456783120 ++ cmp.b @(0x12345678:32,er3),@-er1 ;78346a2c12345678b120 ++ cmp.b @(0x12345678:32,er3),@er1+ ;78346a2c123456788120 ++ cmp.b @(0x12345678:32,er3),@er1- ;78346a2c12345678a120 ++ cmp.b @(0x12345678:32,er3),@+er1 ;78346a2c123456789120 ++ cmp.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346a2c12345678c1209abc ++ cmp.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346a2c12345678c9209abcdef0 ++ cmp.b @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346a2c12345678d2209abc ++ cmp.b @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346a2c12345678e2209abc ++ cmp.b @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346a2c12345678f2209abc ++ cmp.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346a2c12345678da209abcdef0 ++ cmp.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346a2c12345678ea209abcdef0 ++ cmp.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346a2c12345678fa209abcdef0 ++ cmp.b @(0x12345678:32,er3),@0xffff9abc:16 ;78346a2c1234567840209abc ++ cmp.b @(0x12345678:32,er3),@0x9abcdef0:32 ;78346a2c1234567848209abcdef0 ++ ++ cmp.b @(0x1234:16,r3l.b),@er1 ;01756e3c12340120 ++ cmp.b @(0x1234:16,r3l.b),@(3:2,er1) ;01756e3c12343120 ++ cmp.b @(0x1234:16,r3l.b),@-er1 ;01756e3c1234b120 ++ cmp.b @(0x1234:16,r3l.b),@er1+ ;01756e3c12348120 ++ cmp.b @(0x1234:16,r3l.b),@er1- ;01756e3c1234a120 ++ cmp.b @(0x1234:16,r3l.b),@+er1 ;01756e3c12349120 ++ cmp.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01756e3c1234c1209abc ++ cmp.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01756e3c1234c9209abcdef0 ++ cmp.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01756e3c1234d2209abc ++ cmp.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01756e3c1234e2209abc ++ cmp.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01756e3c1234f2209abc ++ cmp.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01756e3c1234da209abcdef0 ++ cmp.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01756e3c1234ea209abcdef0 ++ cmp.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01756e3c1234fa209abcdef0 ++ cmp.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;01756e3c123440209abc ++ cmp.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01756e3c123448209abcdef0 ++ ++ cmp.b @(0x1234:16,r3.w),@er1 ;01766e3c12340120 ++ cmp.b @(0x1234:16,r3.w),@(3:2,er1) ;01766e3c12343120 ++ cmp.b @(0x1234:16,r3.w),@-er1 ;01766e3c1234b120 ++ cmp.b @(0x1234:16,r3.w),@er1+ ;01766e3c12348120 ++ cmp.b @(0x1234:16,r3.w),@er1- ;01766e3c1234a120 ++ cmp.b @(0x1234:16,r3.w),@+er1 ;01766e3c12349120 ++ cmp.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01766e3c1234c1209abc ++ cmp.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01766e3c1234c9209abcdef0 ++ cmp.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01766e3c1234d2209abc ++ cmp.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01766e3c1234e2209abc ++ cmp.b @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01766e3c1234f2209abc ++ cmp.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01766e3c1234da209abcdef0 ++ cmp.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01766e3c1234ea209abcdef0 ++ cmp.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01766e3c1234fa209abcdef0 ++ cmp.b @(0x1234:16,r3.w),@0xffff9abc:16 ;01766e3c123440209abc ++ cmp.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;01766e3c123448209abcdef0 ++ ++ cmp.b @(0x1234:16,er3.l),@er1 ;01776e3c12340120 ++ cmp.b @(0x1234:16,er3.l),@(3:2,er1) ;01776e3c12343120 ++ cmp.b @(0x1234:16,er3.l),@-er1 ;01776e3c1234b120 ++ cmp.b @(0x1234:16,er3.l),@er1+ ;01776e3c12348120 ++ cmp.b @(0x1234:16,er3.l),@er1- ;01776e3c1234a120 ++ cmp.b @(0x1234:16,er3.l),@+er1 ;01776e3c12349120 ++ cmp.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01776e3c1234c1209abc ++ cmp.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01776e3c1234c9209abcdef0 ++ cmp.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01776e3c1234d2209abc ++ cmp.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01776e3c1234e2209abc ++ cmp.b @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01776e3c1234f2209abc ++ cmp.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01776e3c1234da209abcdef0 ++ cmp.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01776e3c1234ea209abcdef0 ++ cmp.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01776e3c1234fa209abcdef0 ++ cmp.b @(0x1234:16,er3.l),@0xffff9abc:16 ;01776e3c123440209abc ++ cmp.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;01776e3c123448209abcdef0 ++ ++ cmp.b @(0x12345678:32,r3l.b),@er1 ;78356a2c123456780120 ++ cmp.b @(0x12345678:32,r3l.b),@(3:2,er1) ;78356a2c123456783120 ++ cmp.b @(0x12345678:32,r3l.b),@-er1 ;78356a2c12345678b120 ++ cmp.b @(0x12345678:32,r3l.b),@er1+ ;78356a2c123456788120 ++ cmp.b @(0x12345678:32,r3l.b),@er1- ;78356a2c12345678a120 ++ cmp.b @(0x12345678:32,r3l.b),@+er1 ;78356a2c123456789120 ++ cmp.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356a2c12345678c1209abc ++ cmp.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356a2c12345678c9209abcdef0 ++ cmp.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356a2c12345678d2209abc ++ cmp.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356a2c12345678e2209abc ++ cmp.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356a2c12345678f2209abc ++ cmp.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356a2c12345678da209abcdef0 ++ cmp.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356a2c12345678ea209abcdef0 ++ cmp.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356a2c12345678fa209abcdef0 ++ cmp.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356a2c1234567840209abc ++ cmp.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356a2c1234567848209abcdef0 ++ ++ cmp.b @(0x12345678:32,r3.w),@er1 ;78366a2c123456780120 ++ cmp.b @(0x12345678:32,r3.w),@(3:2,er1) ;78366a2c123456783120 ++ cmp.b @(0x12345678:32,r3.w),@-er1 ;78366a2c12345678b120 ++ cmp.b @(0x12345678:32,r3.w),@er1+ ;78366a2c123456788120 ++ cmp.b @(0x12345678:32,r3.w),@er1- ;78366a2c12345678a120 ++ cmp.b @(0x12345678:32,r3.w),@+er1 ;78366a2c123456789120 ++ cmp.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366a2c12345678c1209abc ++ cmp.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366a2c12345678c9209abcdef0 ++ cmp.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366a2c12345678d2209abc ++ cmp.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366a2c12345678e2209abc ++ cmp.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366a2c12345678f2209abc ++ cmp.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366a2c12345678da209abcdef0 ++ cmp.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366a2c12345678ea209abcdef0 ++ cmp.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366a2c12345678fa209abcdef0 ++ cmp.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366a2c1234567840209abc ++ cmp.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366a2c1234567848209abcdef0 ++ ++ cmp.b @(0x12345678:32,er3.l),@er1 ;78376a2c123456780120 ++ cmp.b @(0x12345678:32,er3.l),@(3:2,er1) ;78376a2c123456783120 ++ cmp.b @(0x12345678:32,er3.l),@-er1 ;78376a2c12345678b120 ++ cmp.b @(0x12345678:32,er3.l),@er1+ ;78376a2c123456788120 ++ cmp.b @(0x12345678:32,er3.l),@er1- ;78376a2c12345678a120 ++ cmp.b @(0x12345678:32,er3.l),@+er1 ;78376a2c123456789120 ++ cmp.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376a2c12345678c1209abc ++ cmp.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376a2c12345678c9209abcdef0 ++ cmp.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376a2c12345678d2209abc ++ cmp.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376a2c12345678e2209abc ++ cmp.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376a2c12345678f2209abc ++ cmp.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376a2c12345678da209abcdef0 ++ cmp.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376a2c12345678ea209abcdef0 ++ cmp.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376a2c12345678fa209abcdef0 ++ cmp.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376a2c1234567840209abc ++ cmp.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376a2c1234567848209abcdef0 ++ ++ cmp.b @0x1234:16,@er1 ;6a1512340120 ++ cmp.b @0x1234:16,@(3:2,er1) ;6a1512343120 ++ cmp.b @0x1234:16,@-er1 ;6a151234b120 ++ cmp.b @0x1234:16,@er1+ ;6a1512348120 ++ cmp.b @0x1234:16,@er1- ;6a151234a120 ++ cmp.b @0x1234:16,@+er1 ;6a1512349120 ++ cmp.b @0x1234:16,@(0xffff9abc:16,er1) ;6a151234c1209abc ++ cmp.b @0x1234:16,@(0x9abcdef0:32,er1) ;6a151234c9209abcdef0 ++ cmp.b @0x1234:16,@(0xffff9abc:16,r2l.b) ;6a151234d2209abc ++ cmp.b @0x1234:16,@(0xffff9abc:16,r2.w) ;6a151234e2209abc ++ cmp.b @0x1234:16,@(0xffff9abc:16,er2.l) ;6a151234f2209abc ++ cmp.b @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6a151234da209abcdef0 ++ cmp.b @0x1234:16,@(0x9abcdef0:32,r2.w) ;6a151234ea209abcdef0 ++ cmp.b @0x1234:16,@(0x9abcdef0:32,er2.l) ;6a151234fa209abcdef0 ++ cmp.b @0x1234:16,@0xffff9abc:16 ;6a15123440209abc ++ cmp.b @0x1234:16,@0x9abcdef0:32 ;6a15123448209abcdef0 ++ ++ cmp.b @0x12345678:32,@er1 ;6a35123456780120 ++ cmp.b @0x12345678:32,@(3:2,er1) ;6a35123456783120 ++ cmp.b @0x12345678:32,@-er1 ;6a3512345678b120 ++ cmp.b @0x12345678:32,@er1+ ;6a35123456788120 ++ cmp.b @0x12345678:32,@er1- ;6a3512345678a120 ++ cmp.b @0x12345678:32,@+er1 ;6a35123456789120 ++ cmp.b @0x12345678:32,@(0xffff9abc:16,er1) ;6a3512345678c1209abc ++ cmp.b @0x12345678:32,@(0x9abcdef0:32,er1) ;6a3512345678c9209abcdef0 ++ cmp.b @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6a3512345678d2209abc ++ cmp.b @0x12345678:32,@(0xffff9abc:16,r2.w) ;6a3512345678e2209abc ++ cmp.b @0x12345678:32,@(0xffff9abc:16,er2.l) ;6a3512345678f2209abc ++ cmp.b @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6a3512345678da209abcdef0 ++ cmp.b @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6a3512345678ea209abcdef0 ++ cmp.b @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6a3512345678fa209abcdef0 ++ cmp.b @0x12345678:32,@0xffff9abc:16 ;6a351234567840209abc ++ cmp.b @0x12345678:32,@0x9abcdef0:32 ;6a351234567848209abcdef0 ++ ++ cmp.w #0x1234:16,r1 ;79211234 ++ cmp.w #0x7:3,r2 ;1f72 ++ cmp.w #0x1234:16,@er1 ;015e01201234 ++ cmp.w #0x1234:16,@(0x6:2,er1) ;015e31201234 ++ cmp.w #0x1234:16,@er1+ ;015e81201234 ++ cmp.w #0x1234:16,@-er1 ;015eb1201234 ++ cmp.w #0x1234:16,@+er1 ;015e91201234 ++ cmp.w #0x1234:16,@er1- ;015ea1201234 ++ cmp.w #0x1234:16,@(0xffff9abc:16,er1) ;015ec1209abc1234 ++ cmp.w #0x1234:16,@(0x9abcdef0:32,er1) ;015ec9209abcdef01234 ++ cmp.w #0x1234:16,@(0xffff9abc:16,r2l.b) ;015ed2209abc1234 ++ cmp.w #0x1234:16,@(0xffff9abc:16,r2.w) ;015ee2209abc1234 ++ cmp.w #0x1234:16,@(0xffff9abc:16,er2.l) ;015ef2209abc1234 ++ cmp.w #0x1234:16,@(0x9abcdef0:32,r2l.b) ;015eda209abcdef01234 ++ cmp.w #0x1234:16,@(0x9abcdef0:32,r2.w) ;015eea209abcdef01234 ++ cmp.w #0x1234:16,@(0x9abcdef0:32,er2.l) ;015efa209abcdef01234 ++ cmp.w #0x1234:16,@0xffff9abc:16 ;015e40209abc1234 ++ cmp.w #0x1234:16,@0x9abcdef0:32 ;015e48209abcdef01234 ++ ++ cmp.w #0x7:3,@er1 ;7d901f70 ++ cmp.w #0x7:3,@0x1234:16 ;6b1812341f70 ++ cmp.w #0x7:3,@0x12345678:32 ;6b38123456781f70 ++ ++ cmp.w r3,r1 ;1d31 ++ ++ cmp.w r3,@er1 ;7d901d30 ++ cmp.w r3,@(0x6:2,er1) ;01593123 ++ cmp.w r3,@er1+ ;01598123 ++ cmp.w r3,@-er1 ;0159b123 ++ cmp.w r3,@+er1 ;01599123 ++ cmp.w r3,@er1- ;0159a123 ++ cmp.w r3,@(0x1234:16,er1) ;0159c1231234 ++ cmp.w r3,@(0x12345678:32,er1) ;0159c92312345678 ++ cmp.w r3,@(0x1234:16,r2l.b) ;0159d2231234 ++ cmp.w r3,@(0x1234:16,r2.w) ;0159e2231234 ++ cmp.w r3,@(0x1234:16,er2.l) ;0159f2231234 ++ cmp.w r3,@(0x12345678:32,r2l.b) ;0159da2312345678 ++ cmp.w r3,@(0x12345678:32,r2.w) ;0159ea2312345678 ++ cmp.w r3,@(0x12345678:32,er2.l) ;0159fa2312345678 ++ cmp.w r3,@0x1234:16 ;6b1812341d30 ++ cmp.w r3,@0x12345678:32 ;6b38123456781d30 ++ ++ cmp.w @er3,r1 ;7cb01d01 ++ cmp.w @(0x6:2,er3),r1 ;015a3321 ++ cmp.w @er3+,r1 ;015a8321 ++ cmp.w @-er3,r1 ;015ab321 ++ cmp.w @+er3,r1 ;015a9321 ++ cmp.w @er3-,r1 ;015aa321 ++ cmp.w @(0x1234:16,er1),r1 ;015ac1211234 ++ cmp.w @(0x12345678:32,er1),r1 ;015ac92112345678 ++ cmp.w @(0x1234:16,r2l.b),r1 ;015ad2211234 ++ cmp.w @(0x1234:16,r2.w),r1 ;015ae2211234 ++ cmp.w @(0x1234:16,er2.l),r1 ;015af2211234 ++ cmp.w @(0x12345678:32,r2l.b),r1 ;015ada2112345678 ++ cmp.w @(0x12345678:32,r2.w),r1 ;015aea2112345678 ++ cmp.w @(0x12345678:32,er2.l),r1 ;015afa2112345678 ++ cmp.w @0x1234:16,r1 ;6b1012341d01 ++ cmp.w @0x12345678:32,r1 ;6b30123456781d01 ++ ++ cmp.w @er3,@er1 ;7cb50120 ++ cmp.w @er3,@(6:2,er1) ;7cb53120 ++ cmp.w @er3,@-er1 ;7cb5b120 ++ cmp.w @er3,@er1+ ;7cb58120 ++ cmp.w @er3,@er1- ;7cb5a120 ++ cmp.w @er3,@+er1 ;7cb59120 ++ cmp.w @er3,@(0xffff9abc:16,er1) ;7cb5c1209abc ++ cmp.w @er3,@(0x9abcdef0:32,er1) ;7cb5c9209abcdef0 ++ cmp.w @er3,@(0xffff9abc:16,r2l.b) ;7cb5d2209abc ++ cmp.w @er3,@(0xffff9abc:16,r2.w) ;7cb5e2209abc ++ cmp.w @er3,@(0xffff9abc:16,er2.l) ;7cb5f2209abc ++ cmp.w @er3,@(0x9abcdef0:32,r2l.b) ;7cb5da209abcdef0 ++ cmp.w @er3,@(0x9abcdef0:32,r2.w) ;7cb5ea209abcdef0 ++ cmp.w @er3,@(0x9abcdef0:32,er2.l) ;7cb5fa209abcdef0 ++ cmp.w @er3,@0xffff9abc:16 ;7cb540209abc ++ cmp.w @er3,@0x9abcdef0:32 ;7cb548209abcdef0 ++ ++ cmp.w @-er3,@er1 ;01576d3c0120 ++ cmp.w @-er3,@(6:2,er1) ;01576d3c3120 ++ cmp.w @-er3,@-er1 ;01576d3cb120 ++ cmp.w @-er3,@er1+ ;01576d3c8120 ++ cmp.w @-er3,@er1- ;01576d3ca120 ++ cmp.w @-er3,@+er1 ;01576d3c9120 ++ cmp.w @-er3,@(0xffff9abc:16,er1) ;01576d3cc1209abc ++ cmp.w @-er3,@(0x9abcdef0:32,er1) ;01576d3cc9209abcdef0 ++ cmp.w @-er3,@(0xffff9abc:16,r2l.b) ;01576d3cd2209abc ++ cmp.w @-er3,@(0xffff9abc:16,r2.w) ;01576d3ce2209abc ++ cmp.w @-er3,@(0xffff9abc:16,er2.l) ;01576d3cf2209abc ++ cmp.w @-er3,@(0x9abcdef0:32,r2l.b) ;01576d3cda209abcdef0 ++ cmp.w @-er3,@(0x9abcdef0:32,r2.w) ;01576d3cea209abcdef0 ++ cmp.w @-er3,@(0x9abcdef0:32,er2.l) ;01576d3cfa209abcdef0 ++ cmp.w @-er3,@0xffff9abc:16 ;01576d3c40209abc ++ cmp.w @-er3,@0x9abcdef0:32 ;01576d3c48209abcdef0 ++ ++ cmp.w @er3+,@er1 ;01546d3c0120 ++ cmp.w @er3+,@(6:2,er1) ;01546d3c3120 ++ cmp.w @er3+,@-er1 ;01546d3cb120 ++ cmp.w @er3+,@er1+ ;01546d3c8120 ++ cmp.w @er3+,@er1- ;01546d3ca120 ++ cmp.w @er3+,@+er1 ;01546d3c9120 ++ cmp.w @er3+,@(0xffff9abc:16,er1) ;01546d3cc1209abc ++ cmp.w @er3+,@(0x9abcdef0:32,er1) ;01546d3cc9209abcdef0 ++ cmp.w @er3+,@(0xffff9abc:16,r2l.b) ;01546d3cd2209abc ++ cmp.w @er3+,@(0xffff9abc:16,r2.w) ;01546d3ce2209abc ++ cmp.w @er3+,@(0xffff9abc:16,er2.l) ;01546d3cf2209abc ++ cmp.w @er3+,@(0x9abcdef0:32,r2l.b) ;01546d3cda209abcdef0 ++ cmp.w @er3+,@(0x9abcdef0:32,r2.w) ;01546d3cea209abcdef0 ++ cmp.w @er3+,@(0x9abcdef0:32,er2.l) ;01546d3cfa209abcdef0 ++ cmp.w @er3+,@0xffff9abc:16 ;01546d3c40209abc ++ cmp.w @er3+,@0x9abcdef0:32 ;01546d3c48209abcdef0 ++ ++ cmp.w @er3-,@er1 ;01566d3c0120 ++ cmp.w @er3-,@(6:2,er1) ;01566d3c3120 ++ cmp.w @er3-,@-er1 ;01566d3cb120 ++ cmp.w @er3-,@er1+ ;01566d3c8120 ++ cmp.w @er3-,@er1- ;01566d3ca120 ++ cmp.w @er3-,@+er1 ;01566d3c9120 ++ cmp.w @er3-,@(0xffff9abc:16,er1) ;01566d3cc1209abc ++ cmp.w @er3-,@(0x9abcdef0:32,er1) ;01566d3cc9209abcdef0 ++ cmp.w @er3-,@(0xffff9abc:16,r2l.b) ;01566d3cd2209abc ++ cmp.w @er3-,@(0xffff9abc:16,r2.w) ;01566d3ce2209abc ++ cmp.w @er3-,@(0xffff9abc:16,er2.l) ;01566d3cf2209abc ++ cmp.w @er3-,@(0x9abcdef0:32,r2l.b) ;01566d3cda209abcdef0 ++ cmp.w @er3-,@(0x9abcdef0:32,r2.w) ;01566d3cea209abcdef0 ++ cmp.w @er3-,@(0x9abcdef0:32,er2.l) ;01566d3cfa209abcdef0 ++ cmp.w @er3-,@0xffff9abc:16 ;01566d3c40209abc ++ cmp.w @er3-,@0x9abcdef0:32 ;01566d3c48209abcdef0 ++ ++ cmp.w @+er3,@er1 ;01556d3c0120 ++ cmp.w @+er3,@(6:2,er1) ;01556d3c3120 ++ cmp.w @+er3,@-er1 ;01556d3cb120 ++ cmp.w @+er3,@er1+ ;01556d3c8120 ++ cmp.w @+er3,@er1- ;01556d3ca120 ++ cmp.w @+er3,@+er1 ;01556d3c9120 ++ cmp.w @+er3,@(0xffff9abc:16,er1) ;01556d3cc1209abc ++ cmp.w @+er3,@(0x9abcdef0:32,er1) ;01556d3cc9209abcdef0 ++ cmp.w @+er3,@(0xffff9abc:16,r2l.b) ;01556d3cd2209abc ++ cmp.w @+er3,@(0xffff9abc:16,r2.w) ;01556d3ce2209abc ++ cmp.w @+er3,@(0xffff9abc:16,er2.l) ;01556d3cf2209abc ++ cmp.w @+er3,@(0x9abcdef0:32,r2l.b) ;01556d3cda209abcdef0 ++ cmp.w @+er3,@(0x9abcdef0:32,r2.w) ;01556d3cea209abcdef0 ++ cmp.w @+er3,@(0x9abcdef0:32,er2.l) ;01556d3cfa209abcdef0 ++ cmp.w @+er3,@0xffff9abc:16 ;01556d3c40209abc ++ cmp.w @+er3,@0x9abcdef0:32 ;01556d3c48209abcdef0 ++ ++ cmp.w @(0x1234:16,er3),@er1 ;01546f3c12340120 ++ cmp.w @(0x1234:16,er3),@(6:2,er1) ;01546f3c12343120 ++ cmp.w @(0x1234:16,er3),@-er1 ;01546f3c1234b120 ++ cmp.w @(0x1234:16,er3),@er1+ ;01546f3c12348120 ++ cmp.w @(0x1234:16,er3),@er1- ;01546f3c1234a120 ++ cmp.w @(0x1234:16,er3),@+er1 ;01546f3c12349120 ++ cmp.w @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01546f3c1234c1209abc ++ cmp.w @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01546f3c1234c9209abcdef0 ++ cmp.w @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01546f3c1234d2209abc ++ cmp.w @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01546f3c1234e2209abc ++ cmp.w @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01546f3c1234f2209abc ++ cmp.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01546f3c1234da209abcdef0 ++ cmp.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01546f3c1234ea209abcdef0 ++ cmp.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01546f3c1234fa209abcdef0 ++ cmp.w @(0x1234:16,er3),@0xffff9abc:16 ;01546f3c123440209abc ++ cmp.w @(0x1234:16,er3),@0x9abcdef0:32 ;01546f3c123448209abcdef0 ++ ++ cmp.w @(0x12345678:32,er3),@er1 ;78346b2c123456780120 ++ cmp.w @(0x12345678:32,er3),@(6:2,er1) ;78346b2c123456783120 ++ cmp.w @(0x12345678:32,er3),@-er1 ;78346b2c12345678b120 ++ cmp.w @(0x12345678:32,er3),@er1+ ;78346b2c123456788120 ++ cmp.w @(0x12345678:32,er3),@er1- ;78346b2c12345678a120 ++ cmp.w @(0x12345678:32,er3),@+er1 ;78346b2c123456789120 ++ cmp.w @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346b2c12345678c1209abc ++ cmp.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346b2c12345678c9209abcdef0 ++ cmp.w @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346b2c12345678d2209abc ++ cmp.w @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346b2c12345678e2209abc ++ cmp.w @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346b2c12345678f2209abc ++ cmp.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346b2c12345678da209abcdef0 ++ cmp.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346b2c12345678ea209abcdef0 ++ cmp.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346b2c12345678fa209abcdef0 ++ cmp.w @(0x12345678:32,er3),@0xffff9abc:16 ;78346b2c1234567840209abc ++ cmp.w @(0x12345678:32,er3),@0x9abcdef0:32 ;78346b2c1234567848209abcdef0 ++ ++ cmp.w @(0x1234:16,r3l.b),@er1 ;01556f3c12340120 ++ cmp.w @(0x1234:16,r3l.b),@(6:2,er1) ;01556f3c12343120 ++ cmp.w @(0x1234:16,r3l.b),@-er1 ;01556f3c1234b120 ++ cmp.w @(0x1234:16,r3l.b),@er1+ ;01556f3c12348120 ++ cmp.w @(0x1234:16,r3l.b),@er1- ;01556f3c1234a120 ++ cmp.w @(0x1234:16,r3l.b),@+er1 ;01556f3c12349120 ++ cmp.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01556f3c1234c1209abc ++ cmp.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01556f3c1234c9209abcdef0 ++ cmp.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01556f3c1234d2209abc ++ cmp.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01556f3c1234e2209abc ++ cmp.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01556f3c1234f2209abc ++ cmp.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01556f3c1234da209abcdef0 ++ cmp.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01556f3c1234ea209abcdef0 ++ cmp.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01556f3c1234fa209abcdef0 ++ cmp.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;01556f3c123440209abc ++ cmp.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01556f3c123448209abcdef0 ++ ++ cmp.w @(0x1234:16,r3.w),@er1 ;01566f3c12340120 ++ cmp.w @(0x1234:16,r3.w),@(6:2,er1) ;01566f3c12343120 ++ cmp.w @(0x1234:16,r3.w),@-er1 ;01566f3c1234b120 ++ cmp.w @(0x1234:16,r3.w),@er1+ ;01566f3c12348120 ++ cmp.w @(0x1234:16,r3.w),@er1- ;01566f3c1234a120 ++ cmp.w @(0x1234:16,r3.w),@+er1 ;01566f3c12349120 ++ cmp.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01566f3c1234c1209abc ++ cmp.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01566f3c1234c9209abcdef0 ++ cmp.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01566f3c1234d2209abc ++ cmp.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01566f3c1234e2209abc ++ cmp.w @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01566f3c1234f2209abc ++ cmp.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01566f3c1234da209abcdef0 ++ cmp.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01566f3c1234ea209abcdef0 ++ cmp.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01566f3c1234fa209abcdef0 ++ cmp.w @(0x1234:16,r3.w),@0xffff9abc:16 ;01566f3c123440209abc ++ cmp.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;01566f3c123448209abcdef0 ++ ++ cmp.w @(0x1234:16,er3.l),@er1 ;01576f3c12340120 ++ cmp.w @(0x1234:16,er3.l),@(6:2,er1) ;01576f3c12343120 ++ cmp.w @(0x1234:16,er3.l),@-er1 ;01576f3c1234b120 ++ cmp.w @(0x1234:16,er3.l),@er1+ ;01576f3c12348120 ++ cmp.w @(0x1234:16,er3.l),@er1- ;01576f3c1234a120 ++ cmp.w @(0x1234:16,er3.l),@+er1 ;01576f3c12349120 ++ cmp.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01576f3c1234c1209abc ++ cmp.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01576f3c1234c9209abcdef0 ++ cmp.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01576f3c1234d2209abc ++ cmp.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01576f3c1234e2209abc ++ cmp.w @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01576f3c1234f2209abc ++ cmp.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01576f3c1234da209abcdef0 ++ cmp.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01576f3c1234ea209abcdef0 ++ cmp.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01576f3c1234fa209abcdef0 ++ cmp.w @(0x1234:16,er3.l),@0xffff9abc:16 ;01576f3c123440209abc ++ cmp.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;01576f3c123448209abcdef0 ++ ++ cmp.w @(0x12345678:32,r3l.b),@er1 ;78356b2c123456780120 ++ cmp.w @(0x12345678:32,r3l.b),@(6:2,er1) ;78356b2c123456783120 ++ cmp.w @(0x12345678:32,r3l.b),@-er1 ;78356b2c12345678b120 ++ cmp.w @(0x12345678:32,r3l.b),@er1+ ;78356b2c123456788120 ++ cmp.w @(0x12345678:32,r3l.b),@er1- ;78356b2c12345678a120 ++ cmp.w @(0x12345678:32,r3l.b),@+er1 ;78356b2c123456789120 ++ cmp.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356b2c12345678c1209abc ++ cmp.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356b2c12345678c9209abcdef0 ++ cmp.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356b2c12345678d2209abc ++ cmp.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356b2c12345678e2209abc ++ cmp.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356b2c12345678f2209abc ++ cmp.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356b2c12345678da209abcdef0 ++ cmp.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356b2c12345678ea209abcdef0 ++ cmp.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356b2c12345678fa209abcdef0 ++ cmp.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356b2c1234567840209abc ++ cmp.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356b2c1234567848209abcdef0 ++ ++ cmp.w @(0x12345678:32,r3.w),@er1 ;78366b2c123456780120 ++ cmp.w @(0x12345678:32,r3.w),@(6:2,er1) ;78366b2c123456783120 ++ cmp.w @(0x12345678:32,r3.w),@-er1 ;78366b2c12345678b120 ++ cmp.w @(0x12345678:32,r3.w),@er1+ ;78366b2c123456788120 ++ cmp.w @(0x12345678:32,r3.w),@er1- ;78366b2c12345678a120 ++ cmp.w @(0x12345678:32,r3.w),@+er1 ;78366b2c123456789120 ++ cmp.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366b2c12345678c1209abc ++ cmp.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366b2c12345678c9209abcdef0 ++ cmp.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366b2c12345678d2209abc ++ cmp.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366b2c12345678e2209abc ++ cmp.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366b2c12345678f2209abc ++ cmp.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366b2c12345678da209abcdef0 ++ cmp.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366b2c12345678ea209abcdef0 ++ cmp.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366b2c12345678fa209abcdef0 ++ cmp.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366b2c1234567840209abc ++ cmp.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366b2c1234567848209abcdef0 ++ ++ cmp.w @(0x12345678:32,er3.l),@er1 ;78376b2c123456780120 ++ cmp.w @(0x12345678:32,er3.l),@(6:2,er1) ;78376b2c123456783120 ++ cmp.w @(0x12345678:32,er3.l),@-er1 ;78376b2c12345678b120 ++ cmp.w @(0x12345678:32,er3.l),@er1+ ;78376b2c123456788120 ++ cmp.w @(0x12345678:32,er3.l),@er1- ;78376b2c12345678a120 ++ cmp.w @(0x12345678:32,er3.l),@+er1 ;78376b2c123456789120 ++ cmp.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376b2c12345678c1209abc ++ cmp.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376b2c12345678c9209abcdef0 ++ cmp.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376b2c12345678d2209abc ++ cmp.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376b2c12345678e2209abc ++ cmp.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376b2c12345678f2209abc ++ cmp.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376b2c12345678da209abcdef0 ++ cmp.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376b2c12345678ea209abcdef0 ++ cmp.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376b2c12345678fa209abcdef0 ++ cmp.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376b2c1234567840209abc ++ cmp.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376b2c1234567848209abcdef0 ++ ++ cmp.w @0x1234:16,@er1 ;6b1512340120 ++ cmp.w @0x1234:16,@(6:2,er1) ;6b1512343120 ++ cmp.w @0x1234:16,@-er1 ;6b151234b120 ++ cmp.w @0x1234:16,@er1+ ;6b1512348120 ++ cmp.w @0x1234:16,@er1- ;6b151234a120 ++ cmp.w @0x1234:16,@+er1 ;6b1512349120 ++ cmp.w @0x1234:16,@(0xffff9abc:16,er1) ;6b151234c1209abc ++ cmp.w @0x1234:16,@(0x9abcdef0:32,er1) ;6b151234c9209abcdef0 ++ cmp.w @0x1234:16,@(0xffff9abc:16,r2l.b) ;6b151234d2209abc ++ cmp.w @0x1234:16,@(0xffff9abc:16,r2.w) ;6b151234e2209abc ++ cmp.w @0x1234:16,@(0xffff9abc:16,er2.l) ;6b151234f2209abc ++ cmp.w @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6b151234da209abcdef0 ++ cmp.w @0x1234:16,@(0x9abcdef0:32,r2.w) ;6b151234ea209abcdef0 ++ cmp.w @0x1234:16,@(0x9abcdef0:32,er2.l) ;6b151234fa209abcdef0 ++ cmp.w @0x1234:16,@0xffff9abc:16 ;6b15123440209abc ++ cmp.w @0x1234:16,@0x9abcdef0:32 ;6b15123448209abcdef0 ++ ++ cmp.w @0x12345678:32,@er1 ;6b35123456780120 ++ cmp.w @0x12345678:32,@(6:2,er1) ;6b35123456783120 ++ cmp.w @0x12345678:32,@-er1 ;6b3512345678b120 ++ cmp.w @0x12345678:32,@er1+ ;6b35123456788120 ++ cmp.w @0x12345678:32,@er1- ;6b3512345678a120 ++ cmp.w @0x12345678:32,@+er1 ;6b35123456789120 ++ cmp.w @0x12345678:32,@(0xffff9abc:16,er1) ;6b3512345678c1209abc ++ cmp.w @0x12345678:32,@(0x9abcdef0:32,er1) ;6b3512345678c9209abcdef0 ++ cmp.w @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6b3512345678d2209abc ++ cmp.w @0x12345678:32,@(0xffff9abc:16,r2.w) ;6b3512345678e2209abc ++ cmp.w @0x12345678:32,@(0xffff9abc:16,er2.l) ;6b3512345678f2209abc ++ cmp.w @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6b3512345678da209abcdef0 ++ cmp.w @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6b3512345678ea209abcdef0 ++ cmp.w @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6b3512345678fa209abcdef0 ++ cmp.w @0x12345678:32,@0xffff9abc:16 ;6b351234567840209abc ++ cmp.w @0x12345678:32,@0x9abcdef0:32 ;6b351234567848209abcdef0 ++ ++ cmp.l #0x12345678:32,er1 ;7a2112345678 ++ cmp.l #0x1234:16,er1 ;7a291234 ++ cmp.l #0x7:3,er2 ;1ffa ++ cmp.l #0x12345678:32,@er1 ;010e012812345678 ++ cmp.l #0x12345678:32,@(0xc:2,er1) ;010e312812345678 ++ cmp.l #0x12345678:32,@er1+ ;010e812812345678 ++ cmp.l #0x12345678:32,@-er1 ;010eb12812345678 ++ cmp.l #0x12345678:32,@+er1 ;010e912812345678 ++ cmp.l #0x12345678:32,@er1- ;010ea12812345678 ++ cmp.l #0x12345678:32,@(0xffff9abc:16,er1) ;010ec1289abc12345678 ++ cmp.l #0x12345678:32,@(0x9abcdef0:32,er1) ;010ec9289abcdef012345678 ++ cmp.l #0x12345678:32,@(0xffff9abc:16,r2l.b) ;010ed2289abc12345678 ++ cmp.l #0x12345678:32,@(0xffff9abc:16,r2.w) ;010ee2289abc12345678 ++ cmp.l #0x12345678:32,@(0xffff9abc:16,er2.l) ;010ef2289abc12345678 ++ cmp.l #0x12345678:32,@(0x9abcdef0:32,r2l.b) ;010eda289abcdef012345678 ++ cmp.l #0x12345678:32,@(0x9abcdef0:32,r2.w) ;010eea289abcdef012345678 ++ cmp.l #0x12345678:32,@(0x9abcdef0:32,er2.l) ;010efa289abcdef012345678 ++ cmp.l #0x12345678:32,@0xffff9abc:16 ;010e40289abc12345678 ++ cmp.l #0x12345678:32,@0x9abcdef0:32 ;010e48289abcdef012345678 ++ cmp.l #0x1234:16,@er1 ;010e01201234 ++ cmp.l #0x1234:16,@(0xc:2,er1) ;010e31201234 ++ cmp.l #0x1234:16,@er1+ ;010e81201234 ++ cmp.l #0x1234:16,@-er1 ;010eb1201234 ++ cmp.l #0x1234:16,@+er1 ;010e91201234 ++ cmp.l #0x1234:16,@er1- ;010ea1201234 ++ cmp.l #0x1234:16,@(0xffff9abc:16,er1) ;010ec1209abc1234 ++ cmp.l #0x1234:16,@(0x9abcdef0:32,er1) ;010ec9209abcdef01234 ++ cmp.l #0x1234:16,@(0xffff9abc:16,r2l.b) ;010ed2209abc1234 ++ cmp.l #0x1234:16,@(0xffff9abc:16,r2.w) ;010ee2209abc1234 ++ cmp.l #0x1234:16,@(0xffff9abc:16,er2.l) ;010ef2209abc1234 ++ cmp.l #0x1234:16,@(0x9abcdef0:32,r2l.b) ;010eda209abcdef01234 ++ cmp.l #0x1234:16,@(0x9abcdef0:32,r2.w) ;010eea209abcdef01234 ++ cmp.l #0x1234:16,@(0x9abcdef0:32,er2.l) ;010efa209abcdef01234 ++ cmp.l #0x1234:16,@0xffff9abc:16 ;010e40209abc1234 ++ cmp.l #0x1234:16,@0x9abcdef0:32 ;010e48209abcdef01234 ++ ++ cmp.l er3,er1 ;1fb1 ++ ++ cmp.l er3,@er1 ;01090123 ++ cmp.l er3,@(0xc:2,er1) ;01093123 ++ cmp.l er3,@er1+ ;01098123 ++ cmp.l er3,@-er1 ;0109b123 ++ cmp.l er3,@+er1 ;01099123 ++ cmp.l er3,@er1- ;0109a123 ++ cmp.l er3,@(0x1234:16,er1) ;0109c1231234 ++ cmp.l er3,@(0x12345678:32,er1) ;0109c92312345678 ++ cmp.l er3,@(0x1234:16,r2l.b) ;0109d2231234 ++ cmp.l er3,@(0x1234:16,r2.w) ;0109e2231234 ++ cmp.l er3,@(0x1234:16,er2.l) ;0109f2231234 ++ cmp.l er3,@(0x12345678:32,r2l.b) ;0109da2312345678 ++ cmp.l er3,@(0x12345678:32,r2.w) ;0109ea2312345678 ++ cmp.l er3,@(0x12345678:32,er2.l) ;0109fa2312345678 ++ cmp.l er3,@0x1234:16 ;010940231234 ++ cmp.l er3,@0x12345678:32 ;0109482312345678 ++ ++ cmp.l @er3,er1 ;010a0321 ++ cmp.l @(0xc:2,er3),er1 ;010a3321 ++ cmp.l @er3+,er1 ;010a8321 ++ cmp.l @-er3,er1 ;010ab321 ++ cmp.l @+er3,er1 ;010a9321 ++ cmp.l @er3-,er1 ;010aa321 ++ cmp.l @(0x1234:16,er1),er1 ;010ac1211234 ++ cmp.l @(0x12345678:32,er1),er1 ;010ac92112345678 ++ cmp.l @(0x1234:16,r2l.b),er1 ;010ad2211234 ++ cmp.l @(0x1234:16,r2.w),er1 ;010ae2211234 ++ cmp.l @(0x1234:16,er2.l),er1 ;010af2211234 ++ cmp.l @(0x12345678:32,r2l.b),er1 ;010ada2112345678 ++ cmp.l @(0x12345678:32,r2.w),er1 ;010aea2112345678 ++ cmp.l @(0x12345678:32,er2.l),er1 ;010afa2112345678 ++ cmp.l @0x1234:16,er1 ;010a40211234 ++ cmp.l @0x12345678:32,er1 ;010a482112345678 ++ ++ cmp.l @er3,@er1 ;0104693c0120 ++ cmp.l @er3,@(0xc:2,er1) ;0104693c3120 ++ cmp.l @er3,@-er1 ;0104693cb120 ++ cmp.l @er3,@er1+ ;0104693c8120 ++ cmp.l @er3,@er1- ;0104693ca120 ++ cmp.l @er3,@+er1 ;0104693c9120 ++ cmp.l @er3,@(0xffff9abc:16,er1) ;0104693cc1209abc ++ cmp.l @er3,@(0x9abcdef0:32,er1) ;0104693cc9209abcdef0 ++ cmp.l @er3,@(0xffff9abc:16,r2l.b) ;0104693cd2209abc ++ cmp.l @er3,@(0xffff9abc:16,r2.w) ;0104693ce2209abc ++ cmp.l @er3,@(0xffff9abc:16,er2.l) ;0104693cf2209abc ++ cmp.l @er3,@(0x9abcdef0:32,r2l.b) ;0104693cda209abcdef0 ++ cmp.l @er3,@(0x9abcdef0:32,r2.w) ;0104693cea209abcdef0 ++ cmp.l @er3,@(0x9abcdef0:32,er2.l) ;0104693cfa209abcdef0 ++ cmp.l @er3,@0xffff9abc:16 ;0104693c40209abc ++ cmp.l @er3,@0x9abcdef0:32 ;0104693c48209abcdef0 ++ ++ cmp.l @(0xc:2,er3),@er1 ;0107693c0120 ++ cmp.l @(0xc:2,er3),@(0xc:2,er1) ;0107693c3120 ++ cmp.l @(0xc:2,er3),@-er1 ;0107693cb120 ++ cmp.l @(0xc:2,er3),@er1+ ;0107693c8120 ++ cmp.l @(0xc:2,er3),@er1- ;0107693ca120 ++ cmp.l @(0xc:2,er3),@+er1 ;0107693c9120 ++ cmp.l @(0xc:2,er3),@(0xffff9abc:16,er1) ;0107693cc1209abc ++ cmp.l @(0xc:2,er3),@(0x9abcdef0:32,er1) ;0107693cc9209abcdef0 ++ cmp.l @(0xc:2,er3),@(0xffff9abc:16,r2l.b) ;0107693cd2209abc ++ cmp.l @(0xc:2,er3),@(0xffff9abc:16,r2.w) ;0107693ce2209abc ++ cmp.l @(0xc:2,er3),@(0xffff9abc:16,er2.l) ;0107693cf2209abc ++ cmp.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b) ;0107693cda209abcdef0 ++ cmp.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w) ;0107693cea209abcdef0 ++ cmp.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l) ;0107693cfa209abcdef0 ++ cmp.l @(0xc:2,er3),@0xffff9abc:16 ;0107693c40209abc ++ cmp.l @(0xc:2,er3),@0x9abcdef0:32 ;0107693c48209abcdef0 ++ ++ cmp.l @-er3,@er1 ;01076d3c0120 ++ cmp.l @-er3,@(0xc:2,er1) ;01076d3c3120 ++ cmp.l @-er3,@-er1 ;01076d3cb120 ++ cmp.l @-er3,@er1+ ;01076d3c8120 ++ cmp.l @-er3,@er1- ;01076d3ca120 ++ cmp.l @-er3,@+er1 ;01076d3c9120 ++ cmp.l @-er3,@(0xffff9abc:16,er1) ;01076d3cc1209abc ++ cmp.l @-er3,@(0x9abcdef0:32,er1) ;01076d3cc9209abcdef0 ++ cmp.l @-er3,@(0xffff9abc:16,r2l.b) ;01076d3cd2209abc ++ cmp.l @-er3,@(0xffff9abc:16,r2.w) ;01076d3ce2209abc ++ cmp.l @-er3,@(0xffff9abc:16,er2.l) ;01076d3cf2209abc ++ cmp.l @-er3,@(0x9abcdef0:32,r2l.b) ;01076d3cda209abcdef0 ++ cmp.l @-er3,@(0x9abcdef0:32,r2.w) ;01076d3cea209abcdef0 ++ cmp.l @-er3,@(0x9abcdef0:32,er2.l) ;01076d3cfa209abcdef0 ++ cmp.l @-er3,@0xffff9abc:16 ;01076d3c40209abc ++ cmp.l @-er3,@0x9abcdef0:32 ;01076d3c48209abcdef0 ++ ++ cmp.l @er3+,@er1 ;01046d3c0120 ++ cmp.l @er3+,@(0xc:2,er1) ;01046d3c3120 ++ cmp.l @er3+,@-er1 ;01046d3cb120 ++ cmp.l @er3+,@er1+ ;01046d3c8120 ++ cmp.l @er3+,@er1- ;01046d3ca120 ++ cmp.l @er3+,@+er1 ;01046d3c9120 ++ cmp.l @er3+,@(0xffff9abc:16,er1) ;01046d3cc1209abc ++ cmp.l @er3+,@(0x9abcdef0:32,er1) ;01046d3cc9209abcdef0 ++ cmp.l @er3+,@(0xffff9abc:16,r2l.b) ;01046d3cd2209abc ++ cmp.l @er3+,@(0xffff9abc:16,r2.w) ;01046d3ce2209abc ++ cmp.l @er3+,@(0xffff9abc:16,er2.l) ;01046d3cf2209abc ++ cmp.l @er3+,@(0x9abcdef0:32,r2l.b) ;01046d3cda209abcdef0 ++ cmp.l @er3+,@(0x9abcdef0:32,r2.w) ;01046d3cea209abcdef0 ++ cmp.l @er3+,@(0x9abcdef0:32,er2.l) ;01046d3cfa209abcdef0 ++ cmp.l @er3+,@0xffff9abc:16 ;01046d3c40209abc ++ cmp.l @er3+,@0x9abcdef0:32 ;01046d3c48209abcdef0 ++ ++ cmp.l @er3-,@er1 ;01066d3c0120 ++ cmp.l @er3-,@(0xc:2,er1) ;01066d3c3120 ++ cmp.l @er3-,@-er1 ;01066d3cb120 ++ cmp.l @er3-,@er1+ ;01066d3c8120 ++ cmp.l @er3-,@er1- ;01066d3ca120 ++ cmp.l @er3-,@+er1 ;01066d3c9120 ++ cmp.l @er3-,@(0xffff9abc:16,er1) ;01066d3cc1209abc ++ cmp.l @er3-,@(0x9abcdef0:32,er1) ;01066d3cc9209abcdef0 ++ cmp.l @er3-,@(0xffff9abc:16,r2l.b) ;01066d3cd2209abc ++ cmp.l @er3-,@(0xffff9abc:16,r2.w) ;01066d3ce2209abc ++ cmp.l @er3-,@(0xffff9abc:16,er2.l) ;01066d3cf2209abc ++ cmp.l @er3-,@(0x9abcdef0:32,r2l.b) ;01066d3cda209abcdef0 ++ cmp.l @er3-,@(0x9abcdef0:32,r2.w) ;01066d3cea209abcdef0 ++ cmp.l @er3-,@(0x9abcdef0:32,er2.l) ;01066d3cfa209abcdef0 ++ cmp.l @er3-,@0xffff9abc:16 ;01066d3c40209abc ++ cmp.l @er3-,@0x9abcdef0:32 ;01066d3c48209abcdef0 ++ ++ cmp.l @+er3,@er1 ;01056d3c0120 ++ cmp.l @+er3,@(0xc:2,er1) ;01056d3c3120 ++ cmp.l @+er3,@-er1 ;01056d3cb120 ++ cmp.l @+er3,@er1+ ;01056d3c8120 ++ cmp.l @+er3,@er1- ;01056d3ca120 ++ cmp.l @+er3,@+er1 ;01056d3c9120 ++ cmp.l @+er3,@(0xffff9abc:16,er1) ;01056d3cc1209abc ++ cmp.l @+er3,@(0x9abcdef0:32,er1) ;01056d3cc9209abcdef0 ++ cmp.l @+er3,@(0xffff9abc:16,r2l.b) ;01056d3cd2209abc ++ cmp.l @+er3,@(0xffff9abc:16,r2.w) ;01056d3ce2209abc ++ cmp.l @+er3,@(0xffff9abc:16,er2.l) ;01056d3cf2209abc ++ cmp.l @+er3,@(0x9abcdef0:32,r2l.b) ;01056d3cda209abcdef0 ++ cmp.l @+er3,@(0x9abcdef0:32,r2.w) ;01056d3cea209abcdef0 ++ cmp.l @+er3,@(0x9abcdef0:32,er2.l) ;01056d3cfa209abcdef0 ++ cmp.l @+er3,@0xffff9abc:16 ;01056d3c40209abc ++ cmp.l @+er3,@0x9abcdef0:32 ;01056d3c48209abcdef0 ++ ++ cmp.l @(0x1234:16,er3),@er1 ;01046f3c12340120 ++ cmp.l @(0x1234:16,er3),@(0xc:2,er1) ;01046f3c12343120 ++ cmp.l @(0x1234:16,er3),@-er1 ;01046f3c1234b120 ++ cmp.l @(0x1234:16,er3),@er1+ ;01046f3c12348120 ++ cmp.l @(0x1234:16,er3),@er1- ;01046f3c1234a120 ++ cmp.l @(0x1234:16,er3),@+er1 ;01046f3c12349120 ++ cmp.l @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01046f3c1234c1209abc ++ cmp.l @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01046f3c1234c9209abcdef0 ++ cmp.l @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01046f3c1234d2209abc ++ cmp.l @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01046f3c1234e2209abc ++ cmp.l @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01046f3c1234f2209abc ++ cmp.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01046f3c1234da209abcdef0 ++ cmp.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01046f3c1234ea209abcdef0 ++ cmp.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01046f3c1234fa209abcdef0 ++ cmp.l @(0x1234:16,er3),@0xffff9abc:16 ;01046f3c123440209abc ++ cmp.l @(0x1234:16,er3),@0x9abcdef0:32 ;01046f3c123448209abcdef0 ++ ++ cmp.l @(0x12345678:32,er3),@er1 ;78b46b2c123456780120 ++ cmp.l @(0x12345678:32,er3),@(0xc:2,er1) ;78b46b2c123456783120 ++ cmp.l @(0x12345678:32,er3),@-er1 ;78b46b2c12345678b120 ++ cmp.l @(0x12345678:32,er3),@er1+ ;78b46b2c123456788120 ++ cmp.l @(0x12345678:32,er3),@er1- ;78b46b2c12345678a120 ++ cmp.l @(0x12345678:32,er3),@+er1 ;78b46b2c123456789120 ++ cmp.l @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78b46b2c12345678c1209abc ++ cmp.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78b46b2c12345678c9209abcdef0 ++ cmp.l @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78b46b2c12345678d2209abc ++ cmp.l @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78b46b2c12345678e2209abc ++ cmp.l @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78b46b2c12345678f2209abc ++ cmp.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78b46b2c12345678da209abcdef0 ++ cmp.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78b46b2c12345678ea209abcdef0 ++ cmp.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78b46b2c12345678fa209abcdef0 ++ cmp.l @(0x12345678:32,er3),@0xffff9abc:16 ;78b46b2c1234567840209abc ++ cmp.l @(0x12345678:32,er3),@0x9abcdef0:32 ;78b46b2c1234567848209abcdef0 ++ ++ cmp.l @(0x1234:16,r3l.b),@er1 ;01056f3c12340120 ++ cmp.l @(0x1234:16,r3l.b),@(0xc:2,er1) ;01056f3c12343120 ++ cmp.l @(0x1234:16,r3l.b),@-er1 ;01056f3c1234b120 ++ cmp.l @(0x1234:16,r3l.b),@er1+ ;01056f3c12348120 ++ cmp.l @(0x1234:16,r3l.b),@er1- ;01056f3c1234a120 ++ cmp.l @(0x1234:16,r3l.b),@+er1 ;01056f3c12349120 ++ cmp.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01056f3c1234c1209abc ++ cmp.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01056f3c1234c9209abcdef0 ++ cmp.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01056f3c1234d2209abc ++ cmp.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01056f3c1234e2209abc ++ cmp.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01056f3c1234f2209abc ++ cmp.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01056f3c1234da209abcdef0 ++ cmp.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01056f3c1234ea209abcdef0 ++ cmp.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01056f3c1234fa209abcdef0 ++ cmp.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;01056f3c123440209abc ++ cmp.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01056f3c123448209abcdef0 ++ ++ cmp.l @(0x1234:16,r3.w),@er1 ;01066f3c12340120 ++ cmp.l @(0x1234:16,r3.w),@(0xc:2,er1) ;01066f3c12343120 ++ cmp.l @(0x1234:16,r3.w),@-er1 ;01066f3c1234b120 ++ cmp.l @(0x1234:16,r3.w),@er1+ ;01066f3c12348120 ++ cmp.l @(0x1234:16,r3.w),@er1- ;01066f3c1234a120 ++ cmp.l @(0x1234:16,r3.w),@+er1 ;01066f3c12349120 ++ cmp.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01066f3c1234c1209abc ++ cmp.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01066f3c1234c9209abcdef0 ++ cmp.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01066f3c1234d2209abc ++ cmp.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01066f3c1234e2209abc ++ cmp.l @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01066f3c1234f2209abc ++ cmp.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01066f3c1234da209abcdef0 ++ cmp.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01066f3c1234ea209abcdef0 ++ cmp.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01066f3c1234fa209abcdef0 ++ cmp.l @(0x1234:16,r3.w),@0xffff9abc:16 ;01066f3c123440209abc ++ cmp.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;01066f3c123448209abcdef0 ++ ++ cmp.l @(0x1234:16,er3.l),@er1 ;01076f3c12340120 ++ cmp.l @(0x1234:16,er3.l),@(0xc:2,er1) ;01076f3c12343120 ++ cmp.l @(0x1234:16,er3.l),@-er1 ;01076f3c1234b120 ++ cmp.l @(0x1234:16,er3.l),@er1+ ;01076f3c12348120 ++ cmp.l @(0x1234:16,er3.l),@er1- ;01076f3c1234a120 ++ cmp.l @(0x1234:16,er3.l),@+er1 ;01076f3c12349120 ++ cmp.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01076f3c1234c1209abc ++ cmp.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01076f3c1234c9209abcdef0 ++ cmp.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01076f3c1234d2209abc ++ cmp.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01076f3c1234e2209abc ++ cmp.l @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01076f3c1234f2209abc ++ cmp.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01076f3c1234da209abcdef0 ++ cmp.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01076f3c1234ea209abcdef0 ++ cmp.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01076f3c1234fa209abcdef0 ++ cmp.l @(0x1234:16,er3.l),@0xffff9abc:16 ;01076f3c123440209abc ++ cmp.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;01076f3c123448209abcdef0 ++ ++ cmp.l @(0x12345678:32,r3l.b),@er1 ;78b56b2c123456780120 ++ cmp.l @(0x12345678:32,r3l.b),@(0xc:2,er1) ;78b56b2c123456783120 ++ cmp.l @(0x12345678:32,r3l.b),@-er1 ;78b56b2c12345678b120 ++ cmp.l @(0x12345678:32,r3l.b),@er1+ ;78b56b2c123456788120 ++ cmp.l @(0x12345678:32,r3l.b),@er1- ;78b56b2c12345678a120 ++ cmp.l @(0x12345678:32,r3l.b),@+er1 ;78b56b2c123456789120 ++ cmp.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78b56b2c12345678c1209abc ++ cmp.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78b56b2c12345678c9209abcdef0 ++ cmp.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78b56b2c12345678d2209abc ++ cmp.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78b56b2c12345678e2209abc ++ cmp.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78b56b2c12345678f2209abc ++ cmp.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78b56b2c12345678da209abcdef0 ++ cmp.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78b56b2c12345678ea209abcdef0 ++ cmp.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78b56b2c12345678fa209abcdef0 ++ cmp.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78b56b2c1234567840209abc ++ cmp.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78b56b2c1234567848209abcdef0 ++ ++ cmp.l @(0x12345678:32,r3.w),@er1 ;78b66b2c123456780120 ++ cmp.l @(0x12345678:32,r3.w),@(0xc:2,er1) ;78b66b2c123456783120 ++ cmp.l @(0x12345678:32,r3.w),@-er1 ;78b66b2c12345678b120 ++ cmp.l @(0x12345678:32,r3.w),@er1+ ;78b66b2c123456788120 ++ cmp.l @(0x12345678:32,r3.w),@er1- ;78b66b2c12345678a120 ++ cmp.l @(0x12345678:32,r3.w),@+er1 ;78b66b2c123456789120 ++ cmp.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78b66b2c12345678c1209abc ++ cmp.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78b66b2c12345678c9209abcdef0 ++ cmp.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78b66b2c12345678d2209abc ++ cmp.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78b66b2c12345678e2209abc ++ cmp.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78b66b2c12345678f2209abc ++ cmp.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78b66b2c12345678da209abcdef0 ++ cmp.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78b66b2c12345678ea209abcdef0 ++ cmp.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78b66b2c12345678fa209abcdef0 ++ cmp.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;78b66b2c1234567840209abc ++ cmp.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78b66b2c1234567848209abcdef0 ++ ++ cmp.l @(0x12345678:32,er3.l),@er1 ;78b76b2c123456780120 ++ cmp.l @(0x12345678:32,er3.l),@(0xc:2,er1) ;78b76b2c123456783120 ++ cmp.l @(0x12345678:32,er3.l),@-er1 ;78b76b2c12345678b120 ++ cmp.l @(0x12345678:32,er3.l),@er1+ ;78b76b2c123456788120 ++ cmp.l @(0x12345678:32,er3.l),@er1- ;78b76b2c12345678a120 ++ cmp.l @(0x12345678:32,er3.l),@+er1 ;78b76b2c123456789120 ++ cmp.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78b76b2c12345678c1209abc ++ cmp.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78b76b2c12345678c9209abcdef0 ++ cmp.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78b76b2c12345678d2209abc ++ cmp.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78b76b2c12345678e2209abc ++ cmp.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78b76b2c12345678f2209abc ++ cmp.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78b76b2c12345678da209abcdef0 ++ cmp.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78b76b2c12345678ea209abcdef0 ++ cmp.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78b76b2c12345678fa209abcdef0 ++ cmp.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;78b76b2c1234567840209abc ++ cmp.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78b76b2c1234567848209abcdef0 ++ ++ cmp.l @0x1234:16,@er1 ;01046b0c12340120 ++ cmp.l @0x1234:16,@(0xc:2,er1) ;01046b0c12343120 ++ cmp.l @0x1234:16,@-er1 ;01046b0c1234b120 ++ cmp.l @0x1234:16,@er1+ ;01046b0c12348120 ++ cmp.l @0x1234:16,@er1- ;01046b0c1234a120 ++ cmp.l @0x1234:16,@+er1 ;01046b0c12349120 ++ cmp.l @0x1234:16,@(0xffff9abc:16,er1) ;01046b0c1234c1209abc ++ cmp.l @0x1234:16,@(0x9abcdef0:32,er1) ;01046b0c1234c9209abcdef0 ++ cmp.l @0x1234:16,@(0xffff9abc:16,r2l.b) ;01046b0c1234d2209abc ++ cmp.l @0x1234:16,@(0xffff9abc:16,r2.w) ;01046b0c1234e2209abc ++ cmp.l @0x1234:16,@(0xffff9abc:16,er2.l) ;01046b0c1234f2209abc ++ cmp.l @0x1234:16,@(0x9abcdef0:32,r2l.b) ;01046b0c1234da209abcdef0 ++ cmp.l @0x1234:16,@(0x9abcdef0:32,r2.w) ;01046b0c1234ea209abcdef0 ++ cmp.l @0x1234:16,@(0x9abcdef0:32,er2.l) ;01046b0c1234fa209abcdef0 ++ cmp.l @0x1234:16,@0xffff9abc:16 ;01046b0c123440209abc ++ cmp.l @0x1234:16,@0x9abcdef0:32 ;01046b0c123448209abcdef0 ++ ++ cmp.l @0x12345678:32,@er1 ;01046b2c123456780120 ++ cmp.l @0x12345678:32,@(0xc:2,er1) ;01046b2c123456783120 ++ cmp.l @0x12345678:32,@-er1 ;01046b2c12345678b120 ++ cmp.l @0x12345678:32,@er1+ ;01046b2c123456788120 ++ cmp.l @0x12345678:32,@er1- ;01046b2c12345678a120 ++ cmp.l @0x12345678:32,@+er1 ;01046b2c123456789120 ++ cmp.l @0x12345678:32,@(0xffff9abc:16,er1) ;01046b2c12345678c1209abc ++ cmp.l @0x12345678:32,@(0x9abcdef0:32,er1) ;01046b2c12345678c9209abcdef0 ++ cmp.l @0x12345678:32,@(0xffff9abc:16,r2l.b) ;01046b2c12345678d2209abc ++ cmp.l @0x12345678:32,@(0xffff9abc:16,r2.w) ;01046b2c12345678e2209abc ++ cmp.l @0x12345678:32,@(0xffff9abc:16,er2.l) ;01046b2c12345678f2209abc ++ cmp.l @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;01046b2c12345678da209abcdef0 ++ cmp.l @0x12345678:32,@(0x9abcdef0:32,r2.w) ;01046b2c12345678ea209abcdef0 ++ cmp.l @0x12345678:32,@(0x9abcdef0:32,er2.l) ;01046b2c12345678fa209abcdef0 ++ cmp.l @0x12345678:32,@0xffff9abc:16 ;01046b2c1234567840209abc ++ cmp.l @0x12345678:32,@0x9abcdef0:32 ;01046b2c1234567848209abcdef0 ++ ++ .end diff --git a/gas/testsuite/gas/h8300/t06_ari2.exp b/gas/testsuite/gas/h8300/t06_ari2.exp new file mode 100644 -index 0000000..dd04911 +index 0000000..48cbfa7 --- /dev/null +++ b/gas/testsuite/gas/h8300/t06_ari2.exp -@@ -0,0 +1,993 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,992 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1168452,205 +1175628,204 @@ index 0000000..dd04911 + diff --git a/gas/testsuite/gas/h8300/t06_ari2.s b/gas/testsuite/gas/h8300/t06_ari2.s new file mode 100644 -index 0000000..c9cf41b +index 0000000..0d59e84 --- /dev/null +++ b/gas/testsuite/gas/h8300/t06_ari2.s @@ -0,0 +1,187 @@ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+;arith_2 -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ .h8300sx -+ .text -+_start: -+ addx.b #0x12:8,r1h ;9112 -+ addx.b #0x12:8,@er1 ;7d109012 -+ addx.b #0x12:8,@er1- ;01766c189012 -+ -+ addx.b r3h,r1h ;0e31 -+ addx.b r3h,@er1 ;7d100e30 -+ addx.b r3h,@er1- ;01766c180e30 -+ -+ addx.b @er3,r1h ;7c300e01 -+ addx.b @er3,@er1 ;0174683d0110 -+ -+ addx.b @er3-,r1h ;01766c300e01 -+ addx.b @er3-,@er1- ;01766c3da110 -+ -+ addx.w #0x1234:16,r1 ;015179111234 -+ addx.w #0x1234:16,@er1 ;7d9179101234 -+ addx.w #0x1234:16,@er1- ;01566d1979101234 -+ -+ addx.w r3,r1 ;01510931 -+ addx.w r3,@er1 ;7d910930 -+ addx.w r3,@er1- ;01566d190930 -+ -+ addx.w @er3,r1 ;7cb10901 -+ addx.w @er3,@er1 ;0154693d0110 -+ -+ addx.w @er3-,r1 ;01566d310901 -+ addx.w @er3-,@er1- ;01566d3da110 -+ -+ addx.l #0x12345678:32,er1 ;01017a1112345678 -+ addx.l #0x12345678:32,@er1 ;010469197a1012345678 -+ addx.l #0x12345678:32,@er1- ;01066d197a1012345678 -+ -+ addx.l er3,er1 ;01010ab1 -+ addx.l er3,@er1 ;010469190ab0 -+ addx.l er3,@er1- ;01066d190ab0 -+ -+ addx.l @er3,er1 ;010469310a81 -+ addx.l @er3,@er1 ;0104693d0110 -+ -+ addx.l @er3-,er1 ;01066d310a81 -+ addx.l @er3-,@er1- ;01066d3da110 -+ -+ subx.b #0x12:8,r1h ;b112 -+ subx.b #0x12:8,@er1 ;7d10b012 -+ subx.b #0x12:8,@er1- ;01766c18b012 -+ -+ subx.b r3h,r1h ;1e31 -+ subx.b r3h,@er1 ;7d101e30 -+ subx.b r3h,@er1- ;01766c181e30 -+ -+ subx.b @er3,r1h ;7c301e01 -+ subx.b @er3,@er1 ;0174683d0130 -+ -+ subx.b @er3-,r1h ;01766c301e01 -+ subx.b @er3-,@er1- ;01766c3da130 -+ -+ subx.w #0x1234:16,r1 ;015179311234 -+ subx.w #0x1234:16,@er1 ;7d9179301234 -+ subx.w #0x1234:16,@er1- ;01566d1979301234 -+ -+ subx.w r3,r1 ;01511931 -+ subx.w r3,@er1 ;7d911930 -+ subx.w r3,@er1- ;01566d191930 -+ -+ subx.w @er3,r1 ;7cb11901 -+ subx.w @er3,@er1 ;0154693d0130 -+ -+ subx.w @er3-,r1 ;01566d311901 -+ subx.w @er3-,@er1- ;01566d3da130 -+ -+ subx.l #0x12345678:32,er1 ;01017a3112345678 -+ subx.l #0x12345678:32,@er1 ;010469197a3012345678 -+ subx.l #0x12345678:32,@er1- ;01066d197a3012345678 -+ -+ subx.l er3,er1 ;01011ab1 -+ subx.l er3,@er1 ;010469191ab0 -+ subx.l er3,@er1- ;01066d191ab0 -+ -+ subx.l @er3,er1 ;010469311a81 -+ subx.l @er3,@er1 ;0104693d0130 -+ -+ subx.l @er3-,er1 ;01066d311a81 -+ subx.l @er3-,@er1- ;01066d3da130 -+ -+ inc.b r1h ;0a01 -+ inc.w #1,r1 ;0b51 -+ inc.w #2,r1 ;0bd1 -+ inc.l #1,er1 ;0b71 -+ inc.l #2,er1 ;0bf1 -+ -+ dec.b r1h ;1a01 -+ dec.w #1,r1 ;1b51 -+ dec.w #2,r1 ;1bd1 -+ dec.l #1,er1 ;1b71 -+ dec.l #2,er1 ;1bf1 -+ -+ adds.l #1,er1 ;0b01 -+ adds.l #2,er1 ;0b81 -+ adds.l #4,er1 ;0b91 -+ -+ subs.l #1,er1 ;1b01 -+ subs.l #2,er1 ;1b81 -+ subs.l #4,er1 ;1b91 -+ -+ daa.b r1h ;0f01 -+ -+ das.b r1h ;1f01 -+ -+ mulxu.b #0xf:4,r1 ;01cc50f1 -+ -+ mulxu.b r3h,r1 ;5031 -+ -+ mulxu.w #0xf:4,er1 ;01cc52f1 -+ -+ mulxu.w r3,er1 ;5231 -+ -+ divxu.b #0xf:4,r1 ;01dc51f1 -+ -+ divxu.b r3h,r1 ;5131 -+ -+ divxu.w #0xf:4,er1 ;01dc53f1 -+ -+ divxu.w r3,er1 ;5331 -+ -+ mulxs.b #0xf:4,r1 ;01c450f1 -+ -+ mulxs.b r3h,r1 ;01c05031 -+ -+ mulxs.w #0xf:4,er1 ;01c452f1 -+ -+ mulxs.w r3,er1 ;01c05231 -+ -+ divxs.b #0xf:4,r1 ;01d451f1 -+ -+ divxs.b r3h,r1 ;01d05131 -+ -+ divxs.w #0xf:4,er1 ;01d453f1 -+ -+ divxs.w r3,er1 ;01d05331 -+ -+ mulu.w #0xf:4,r1 ;01ce50f1 -+ -+ mulu.w r3,r1 ;01ca5031 -+ -+ mulu.l #0xf:4,er1 ;01ce52f1 -+ -+ mulu.l er3,er1 ;01ca5231 -+ -+ mulu/u.l #0xf:4,er1 ;01cf52f1 -+ -+ mulu/u.l er3,er1 ;01cb5231 -+ -+ muls.w #0xf:4,r1 ;01c650f1 -+ -+ muls.w r3,r1 ;01c25031 -+ -+ muls.l #0xf:4,er1 ;01c652f1 -+ -+ muls.l er3,er1 ;01c25231 -+ -+ muls/u.l #0xf:4,er1 ;01c752f1 -+ -+ muls/u.l er3,er1 ;01c35231 -+ -+ divu.w #0xf:4,r1 ;01de51f1 -+ -+ divu.w r3,r1 ;01da5131 -+ -+ divu.l #0xf:4,er1 ;01de53f1 -+ -+ divu.l er3,er1 ;01da5331 -+ -+ divs.w #0xf:4,r1 ;01d651f1 -+ -+ divs.w r3,r1 ;01d25131 -+ -+ divs.l #0xf:4,er1 ;01d653f1 -+ -+ divs.l er3,er1 ;01d25331 -+ -+ .end ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;arith_2 ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ .h8300sx ++ .text ++_start: ++ addx.b #0x12:8,r1h ;9112 ++ addx.b #0x12:8,@er1 ;7d109012 ++ addx.b #0x12:8,@er1- ;01766c189012 ++ ++ addx.b r3h,r1h ;0e31 ++ addx.b r3h,@er1 ;7d100e30 ++ addx.b r3h,@er1- ;01766c180e30 ++ ++ addx.b @er3,r1h ;7c300e01 ++ addx.b @er3,@er1 ;0174683d0110 ++ ++ addx.b @er3-,r1h ;01766c300e01 ++ addx.b @er3-,@er1- ;01766c3da110 ++ ++ addx.w #0x1234:16,r1 ;015179111234 ++ addx.w #0x1234:16,@er1 ;7d9179101234 ++ addx.w #0x1234:16,@er1- ;01566d1979101234 ++ ++ addx.w r3,r1 ;01510931 ++ addx.w r3,@er1 ;7d910930 ++ addx.w r3,@er1- ;01566d190930 ++ ++ addx.w @er3,r1 ;7cb10901 ++ addx.w @er3,@er1 ;0154693d0110 ++ ++ addx.w @er3-,r1 ;01566d310901 ++ addx.w @er3-,@er1- ;01566d3da110 ++ ++ addx.l #0x12345678:32,er1 ;01017a1112345678 ++ addx.l #0x12345678:32,@er1 ;010469197a1012345678 ++ addx.l #0x12345678:32,@er1- ;01066d197a1012345678 ++ ++ addx.l er3,er1 ;01010ab1 ++ addx.l er3,@er1 ;010469190ab0 ++ addx.l er3,@er1- ;01066d190ab0 ++ ++ addx.l @er3,er1 ;010469310a81 ++ addx.l @er3,@er1 ;0104693d0110 ++ ++ addx.l @er3-,er1 ;01066d310a81 ++ addx.l @er3-,@er1- ;01066d3da110 ++ ++ subx.b #0x12:8,r1h ;b112 ++ subx.b #0x12:8,@er1 ;7d10b012 ++ subx.b #0x12:8,@er1- ;01766c18b012 ++ ++ subx.b r3h,r1h ;1e31 ++ subx.b r3h,@er1 ;7d101e30 ++ subx.b r3h,@er1- ;01766c181e30 ++ ++ subx.b @er3,r1h ;7c301e01 ++ subx.b @er3,@er1 ;0174683d0130 ++ ++ subx.b @er3-,r1h ;01766c301e01 ++ subx.b @er3-,@er1- ;01766c3da130 ++ ++ subx.w #0x1234:16,r1 ;015179311234 ++ subx.w #0x1234:16,@er1 ;7d9179301234 ++ subx.w #0x1234:16,@er1- ;01566d1979301234 ++ ++ subx.w r3,r1 ;01511931 ++ subx.w r3,@er1 ;7d911930 ++ subx.w r3,@er1- ;01566d191930 ++ ++ subx.w @er3,r1 ;7cb11901 ++ subx.w @er3,@er1 ;0154693d0130 ++ ++ subx.w @er3-,r1 ;01566d311901 ++ subx.w @er3-,@er1- ;01566d3da130 ++ ++ subx.l #0x12345678:32,er1 ;01017a3112345678 ++ subx.l #0x12345678:32,@er1 ;010469197a3012345678 ++ subx.l #0x12345678:32,@er1- ;01066d197a3012345678 ++ ++ subx.l er3,er1 ;01011ab1 ++ subx.l er3,@er1 ;010469191ab0 ++ subx.l er3,@er1- ;01066d191ab0 ++ ++ subx.l @er3,er1 ;010469311a81 ++ subx.l @er3,@er1 ;0104693d0130 ++ ++ subx.l @er3-,er1 ;01066d311a81 ++ subx.l @er3-,@er1- ;01066d3da130 ++ ++ inc.b r1h ;0a01 ++ inc.w #1,r1 ;0b51 ++ inc.w #2,r1 ;0bd1 ++ inc.l #1,er1 ;0b71 ++ inc.l #2,er1 ;0bf1 ++ ++ dec.b r1h ;1a01 ++ dec.w #1,r1 ;1b51 ++ dec.w #2,r1 ;1bd1 ++ dec.l #1,er1 ;1b71 ++ dec.l #2,er1 ;1bf1 ++ ++ adds.l #1,er1 ;0b01 ++ adds.l #2,er1 ;0b81 ++ adds.l #4,er1 ;0b91 ++ ++ subs.l #1,er1 ;1b01 ++ subs.l #2,er1 ;1b81 ++ subs.l #4,er1 ;1b91 ++ ++ daa.b r1h ;0f01 ++ ++ das.b r1h ;1f01 ++ ++ mulxu.b #0xf:4,r1 ;01cc50f1 ++ ++ mulxu.b r3h,r1 ;5031 ++ ++ mulxu.w #0xf:4,er1 ;01cc52f1 ++ ++ mulxu.w r3,er1 ;5231 ++ ++ divxu.b #0xf:4,r1 ;01dc51f1 ++ ++ divxu.b r3h,r1 ;5131 ++ ++ divxu.w #0xf:4,er1 ;01dc53f1 ++ ++ divxu.w r3,er1 ;5331 ++ ++ mulxs.b #0xf:4,r1 ;01c450f1 ++ ++ mulxs.b r3h,r1 ;01c05031 ++ ++ mulxs.w #0xf:4,er1 ;01c452f1 ++ ++ mulxs.w r3,er1 ;01c05231 ++ ++ divxs.b #0xf:4,r1 ;01d451f1 ++ ++ divxs.b r3h,r1 ;01d05131 ++ ++ divxs.w #0xf:4,er1 ;01d453f1 ++ ++ divxs.w r3,er1 ;01d05331 ++ ++ mulu.w #0xf:4,r1 ;01ce50f1 ++ ++ mulu.w r3,r1 ;01ca5031 ++ ++ mulu.l #0xf:4,er1 ;01ce52f1 ++ ++ mulu.l er3,er1 ;01ca5231 ++ ++ mulu/u.l #0xf:4,er1 ;01cf52f1 ++ ++ mulu/u.l er3,er1 ;01cb5231 ++ ++ muls.w #0xf:4,r1 ;01c650f1 ++ ++ muls.w r3,r1 ;01c25031 ++ ++ muls.l #0xf:4,er1 ;01c652f1 ++ ++ muls.l er3,er1 ;01c25231 ++ ++ muls/u.l #0xf:4,er1 ;01c752f1 ++ ++ muls/u.l er3,er1 ;01c35231 ++ ++ divu.w #0xf:4,r1 ;01de51f1 ++ ++ divu.w r3,r1 ;01da5131 ++ ++ divu.l #0xf:4,er1 ;01de53f1 ++ ++ divu.l er3,er1 ;01da5331 ++ ++ divs.w #0xf:4,r1 ;01d651f1 ++ ++ divs.w r3,r1 ;01d25131 ++ ++ divs.l #0xf:4,er1 ;01d653f1 ++ ++ divs.l er3,er1 ;01d25331 ++ ++ .end diff --git a/gas/testsuite/gas/h8300/t07_ari3.exp b/gas/testsuite/gas/h8300/t07_ari3.exp new file mode 100644 -index 0000000..d4ce917 +index 0000000..61e9744 --- /dev/null +++ b/gas/testsuite/gas/h8300/t07_ari3.exp -@@ -0,0 +1,497 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,496 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1169148,190 +1176323,189 @@ index 0000000..d4ce917 + diff --git a/gas/testsuite/gas/h8300/t07_ari3.s b/gas/testsuite/gas/h8300/t07_ari3.s new file mode 100644 -index 0000000..8343d5c +index 0000000..baf21a8 --- /dev/null +++ b/gas/testsuite/gas/h8300/t07_ari3.s @@ -0,0 +1,172 @@ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+;arith_3 -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ .h8300sx -+ .text -+_start: -+ neg.b r1h ;1781 -+ neg.b @er1 ;7d101780 -+ neg.b @(0x3:2,er1) ;017768181780 -+ neg.b @er1+ ;01746c181780 -+ neg.b @-er1 ;01776c181780 -+ neg.b @+er1 ;01756c181780 -+ neg.b @er1- ;01766c181780 -+ neg.b @(0x1234:16,er1) ;01746e1812341780 -+ neg.b @(0x12345678:32,er1) ;78146a28123456781780 -+ neg.b @(0x1234:16,r2l.b) ;01756e2812341780 -+ neg.b @(0x1234:16,r2.w) ;01766e2812341780 -+ neg.b @(0x1234:16,er2.l) ;01776e2812341780 -+ neg.b @(0x12345678:32,r2l.b) ;78256a28123456781780 -+ neg.b @(0x12345678:32,r2.w) ;78266a28123456781780 -+ neg.b @(0x12345678:32,er2.l) ;78276a28123456781780 -+ neg.b @0xffffff12:8 ;7f121780 -+ neg.b @0x1234:16 ;6a1812341780 -+ neg.b @0x12345678:32 ;6a38123456781780 -+ -+ neg.w r1 ;1791 -+ neg.w @er1 ;7d901790 -+ neg.w @(0x6:2,er1) ;015769181790 -+ neg.w @er1+ ;01546d181790 -+ neg.w @-er1 ;01576d181790 -+ neg.w @+er1 ;01556d181790 -+ neg.w @er1- ;01566d181790 -+ neg.w @(0x1234:16,er1) ;01546f1812341790 -+ neg.w @(0x12345678:32,er1) ;78146b28123456781790 -+ neg.w @(0x1234:16,r2l.b) ;01556f2812341790 -+ neg.w @(0x1234:16,r2.w) ;01566f2812341790 -+ neg.w @(0x1234:16,er2.l) ;01576f2812341790 -+ neg.w @(0x12345678:32,r2l.b) ;78256b28123456781790 -+ neg.w @(0x12345678:32,r2.w) ;78266b28123456781790 -+ neg.w @(0x12345678:32,er2.l) ;78276b28123456781790 -+ neg.w @0x1234:16 ;6b1812341790 -+ neg.w @0x12345678:32 ;6b38123456781790 -+ -+ neg.l er1 ;17b1 -+ neg.l @er1 ;0104691817b0 -+ neg.l @(0xc:2,er1) ;0107691817b0 -+ neg.l @er1+ ;01046d1817b0 -+ neg.l @-er1 ;01076d1817b0 -+ neg.l @+er1 ;01056d1817b0 -+ neg.l @er1- ;01066d1817b0 -+ neg.l @(0x1234:16,er1) ;01046f18123417b0 -+ neg.l @(0x12345678:32,er1) ;78946b281234567817b0 -+ neg.l @(0x1234:16,r2l.b) ;01056f28123417b0 -+ neg.l @(0x1234:16,r2.w) ;01066f28123417b0 -+ neg.l @(0x1234:16,er2.l) ;01076f28123417b0 -+ neg.l @(0x12345678:32,r2l.b) ;78a56b281234567817b0 -+ neg.l @(0x12345678:32,r2.w) ;78a66b281234567817b0 -+ neg.l @(0x12345678:32,er2.l) ;78a76b281234567817b0 -+ neg.l @0x1234:16 ;01046b08123417b0 -+ neg.l @0x12345678:32 ;01046b281234567817b0 -+ -+ tas @er1 ;01e07b1c -+ -+ extu.w r1 ;1751 -+ extu.w @er1 ;7d901750 -+ extu.w @(0x6:2,er1) ;015769181750 -+ extu.w @er1+ ;01546d181750 -+ extu.w @-er1 ;01576d181750 -+ extu.w @+er1 ;01556d181750 -+ extu.w @er1- ;01566d181750 -+ extu.w @(0x1234:16,er1) ;01546f1812341750 -+ extu.w @(0x12345678:32,er1) ;78146b28123456781750 -+ extu.w @(0x1234:16,r2l.b) ;01556f2812341750 -+ extu.w @(0x1234:16,r2.w) ;01566f2812341750 -+ extu.w @(0x1234:16,er2.l) ;01576f2812341750 -+ extu.w @(0x12345678:32,r2l.b) ;78256b28123456781750 -+ extu.w @(0x12345678:32,r2.w) ;78266b28123456781750 -+ extu.w @(0x12345678:32,er2.l) ;78276b28123456781750 -+ extu.w @0x1234:16 ;6b1812341750 -+ extu.w @0x12345678:32 ;6b38123456781750 -+ -+ extu.l er1 ;1771 -+ extu.l @er1 ;010469181770 -+ extu.l @(0xc:2,er1) ;010769181770 -+ extu.l @er1+ ;01046d181770 -+ extu.l @-er1 ;01076d181770 -+ extu.l @+er1 ;01056d181770 -+ extu.l @er1- ;01066d181770 -+ extu.l @(0x1234:16,er1) ;01046f1812341770 -+ extu.l @(0x12345678:32,er1) ;78946b28123456781770 -+ extu.l @(0x1234:16,r2l.b) ;01056f2812341770 -+ extu.l @(0x1234:16,r2.w) ;01066f2812341770 -+ extu.l @(0x1234:16,er2.l) ;01076f2812341770 -+ extu.l @(0x12345678:32,r2l.b) ;78a56b28123456781770 -+ extu.l @(0x12345678:32,r2.w) ;78a66b28123456781770 -+ extu.l @(0x12345678:32,er2.l) ;78a76b28123456781770 -+ extu.l @0x1234:16 ;01046b0812341770 -+ extu.l @0x12345678:32 ;01046b28123456781770 -+ -+ extu.l #2,er1 ;1761 -+ extu.l #2,@er1 ;010469181760 -+ extu.l #2,@(0xc:2,er1) ;010769181760 -+ extu.l #2,@er1+ ;01046d181760 -+ extu.l #2,@-er1 ;01076d181760 -+ extu.l #2,@+er1 ;01056d181760 -+ extu.l #2,@er1- ;01066d181760 -+ extu.l #2,@(0x1234:16,er1) ;01046f1812341760 -+ extu.l #2,@(0x12345678:32,er1) ;78946b28123456781760 -+ extu.l #2,@(0x1234:16,r2l.b) ;01056f2812341760 -+ extu.l #2,@(0x1234:16,r2.w) ;01066f2812341760 -+ extu.l #2,@(0x1234:16,er2.l) ;01076f2812341760 -+ extu.l #2,@(0x12345678:32,r2l.b) ;78a56b28123456781760 -+ extu.l #2,@(0x12345678:32,r2.w) ;78a66b28123456781760 -+ extu.l #2,@(0x12345678:32,er2.l) ;78a76b28123456781760 -+ extu.l #2,@0x1234:16 ;01046b0812341760 -+ extu.l #2,@0x12345678:32 ;01046b28123456781760 -+ -+ exts.w r1 ;17d1 -+ exts.w @er1 ;7d9017d0 -+ exts.w @(0x6:2,er1) ;0157691817d0 -+ exts.w @er1+ ;01546d1817d0 -+ exts.w @-er1 ;01576d1817d0 -+ exts.w @+er1 ;01556d1817d0 -+ exts.w @er1- ;01566d1817d0 -+ exts.w @(0x1234:16,er1) ;01546f18123417d0 -+ exts.w @(0x12345678:32,er1) ;78146b281234567817d0 -+ exts.w @(0x1234:16,r2l.b) ;01556f28123417d0 -+ exts.w @(0x1234:16,r2.w) ;01566f28123417d0 -+ exts.w @(0x1234:16,er2.l) ;01576f28123417d0 -+ exts.w @(0x12345678:32,r2l.b) ;78256b281234567817d0 -+ exts.w @(0x12345678:32,r2.w) ;78266b281234567817d0 -+ exts.w @(0x12345678:32,er2.l) ;78276b281234567817d0 -+ exts.w @0x1234:16 ;6b18123417d0 -+ exts.w @0x12345678:32 ;6b381234567817d0 -+ -+ exts.l er1 ;17f1 -+ exts.l @er1 ;0104691817f0 -+ exts.l @(0xc:2,er1) ;0107691817f0 -+ exts.l @er1+ ;01046d1817f0 -+ exts.l @-er1 ;01076d1817f0 -+ exts.l @+er1 ;01056d1817f0 -+ exts.l @er1- ;01066d1817f0 -+ exts.l @(0x1234:16,er1) ;01046f18123417f0 -+ exts.l @(0x12345678:32,er1) ;78946b281234567817f0 -+ exts.l @(0x1234:16,r2l.b) ;01056f28123417f0 -+ exts.l @(0x1234:16,r2.w) ;01066f28123417f0 -+ exts.l @(0x1234:16,er2.l) ;01076f28123417f0 -+ exts.l @(0x12345678:32,r2l.b) ;78a56b281234567817f0 -+ exts.l @(0x12345678:32,r2.w) ;78a66b281234567817f0 -+ exts.l @(0x12345678:32,er2.l) ;78a76b281234567817f0 -+ exts.l @0x1234:16 ;01046b08123417f0 -+ exts.l @0x12345678:32 ;01046b281234567817f0 -+ -+ exts.l #2,er1 ;17e1 -+ exts.l #2,@er1 ;0104691817e0 -+ exts.l #2,@(0xc:2,er1) ;0107691817e0 -+ exts.l #2,@er1+ ;01046d1817e0 -+ exts.l #2,@-er1 ;01076d1817e0 -+ exts.l #2,@+er1 ;01056d1817e0 -+ exts.l #2,@er1- ;01066d1817e0 -+ exts.l #2,@(0x1234:16,er1) ;01046f18123417e0 -+ exts.l #2,@(0x12345678:32,er1) ;78946b281234567817e0 -+ exts.l #2,@(0x1234:16,r2l.b) ;01056f28123417e0 -+ exts.l #2,@(0x1234:16,r2.w) ;01066f28123417e0 -+ exts.l #2,@(0x1234:16,er2.l) ;01076f28123417e0 -+ exts.l #2,@(0x12345678:32,r2l.b) ;78a56b281234567817e0 -+ exts.l #2,@(0x12345678:32,r2.w) ;78a66b281234567817e0 -+ exts.l #2,@(0x12345678:32,er2.l) ;78a76b281234567817e0 -+ exts.l #2,@0x1234:16 ;01046b08123417e0 -+ exts.l #2,@0x12345678:32 ;01046b281234567817e0 -+ -+ .end ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;arith_3 ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ .h8300sx ++ .text ++_start: ++ neg.b r1h ;1781 ++ neg.b @er1 ;7d101780 ++ neg.b @(0x3:2,er1) ;017768181780 ++ neg.b @er1+ ;01746c181780 ++ neg.b @-er1 ;01776c181780 ++ neg.b @+er1 ;01756c181780 ++ neg.b @er1- ;01766c181780 ++ neg.b @(0x1234:16,er1) ;01746e1812341780 ++ neg.b @(0x12345678:32,er1) ;78146a28123456781780 ++ neg.b @(0x1234:16,r2l.b) ;01756e2812341780 ++ neg.b @(0x1234:16,r2.w) ;01766e2812341780 ++ neg.b @(0x1234:16,er2.l) ;01776e2812341780 ++ neg.b @(0x12345678:32,r2l.b) ;78256a28123456781780 ++ neg.b @(0x12345678:32,r2.w) ;78266a28123456781780 ++ neg.b @(0x12345678:32,er2.l) ;78276a28123456781780 ++ neg.b @0xffffff12:8 ;7f121780 ++ neg.b @0x1234:16 ;6a1812341780 ++ neg.b @0x12345678:32 ;6a38123456781780 ++ ++ neg.w r1 ;1791 ++ neg.w @er1 ;7d901790 ++ neg.w @(0x6:2,er1) ;015769181790 ++ neg.w @er1+ ;01546d181790 ++ neg.w @-er1 ;01576d181790 ++ neg.w @+er1 ;01556d181790 ++ neg.w @er1- ;01566d181790 ++ neg.w @(0x1234:16,er1) ;01546f1812341790 ++ neg.w @(0x12345678:32,er1) ;78146b28123456781790 ++ neg.w @(0x1234:16,r2l.b) ;01556f2812341790 ++ neg.w @(0x1234:16,r2.w) ;01566f2812341790 ++ neg.w @(0x1234:16,er2.l) ;01576f2812341790 ++ neg.w @(0x12345678:32,r2l.b) ;78256b28123456781790 ++ neg.w @(0x12345678:32,r2.w) ;78266b28123456781790 ++ neg.w @(0x12345678:32,er2.l) ;78276b28123456781790 ++ neg.w @0x1234:16 ;6b1812341790 ++ neg.w @0x12345678:32 ;6b38123456781790 ++ ++ neg.l er1 ;17b1 ++ neg.l @er1 ;0104691817b0 ++ neg.l @(0xc:2,er1) ;0107691817b0 ++ neg.l @er1+ ;01046d1817b0 ++ neg.l @-er1 ;01076d1817b0 ++ neg.l @+er1 ;01056d1817b0 ++ neg.l @er1- ;01066d1817b0 ++ neg.l @(0x1234:16,er1) ;01046f18123417b0 ++ neg.l @(0x12345678:32,er1) ;78946b281234567817b0 ++ neg.l @(0x1234:16,r2l.b) ;01056f28123417b0 ++ neg.l @(0x1234:16,r2.w) ;01066f28123417b0 ++ neg.l @(0x1234:16,er2.l) ;01076f28123417b0 ++ neg.l @(0x12345678:32,r2l.b) ;78a56b281234567817b0 ++ neg.l @(0x12345678:32,r2.w) ;78a66b281234567817b0 ++ neg.l @(0x12345678:32,er2.l) ;78a76b281234567817b0 ++ neg.l @0x1234:16 ;01046b08123417b0 ++ neg.l @0x12345678:32 ;01046b281234567817b0 ++ ++ tas @er1 ;01e07b1c ++ ++ extu.w r1 ;1751 ++ extu.w @er1 ;7d901750 ++ extu.w @(0x6:2,er1) ;015769181750 ++ extu.w @er1+ ;01546d181750 ++ extu.w @-er1 ;01576d181750 ++ extu.w @+er1 ;01556d181750 ++ extu.w @er1- ;01566d181750 ++ extu.w @(0x1234:16,er1) ;01546f1812341750 ++ extu.w @(0x12345678:32,er1) ;78146b28123456781750 ++ extu.w @(0x1234:16,r2l.b) ;01556f2812341750 ++ extu.w @(0x1234:16,r2.w) ;01566f2812341750 ++ extu.w @(0x1234:16,er2.l) ;01576f2812341750 ++ extu.w @(0x12345678:32,r2l.b) ;78256b28123456781750 ++ extu.w @(0x12345678:32,r2.w) ;78266b28123456781750 ++ extu.w @(0x12345678:32,er2.l) ;78276b28123456781750 ++ extu.w @0x1234:16 ;6b1812341750 ++ extu.w @0x12345678:32 ;6b38123456781750 ++ ++ extu.l er1 ;1771 ++ extu.l @er1 ;010469181770 ++ extu.l @(0xc:2,er1) ;010769181770 ++ extu.l @er1+ ;01046d181770 ++ extu.l @-er1 ;01076d181770 ++ extu.l @+er1 ;01056d181770 ++ extu.l @er1- ;01066d181770 ++ extu.l @(0x1234:16,er1) ;01046f1812341770 ++ extu.l @(0x12345678:32,er1) ;78946b28123456781770 ++ extu.l @(0x1234:16,r2l.b) ;01056f2812341770 ++ extu.l @(0x1234:16,r2.w) ;01066f2812341770 ++ extu.l @(0x1234:16,er2.l) ;01076f2812341770 ++ extu.l @(0x12345678:32,r2l.b) ;78a56b28123456781770 ++ extu.l @(0x12345678:32,r2.w) ;78a66b28123456781770 ++ extu.l @(0x12345678:32,er2.l) ;78a76b28123456781770 ++ extu.l @0x1234:16 ;01046b0812341770 ++ extu.l @0x12345678:32 ;01046b28123456781770 ++ ++ extu.l #2,er1 ;1761 ++ extu.l #2,@er1 ;010469181760 ++ extu.l #2,@(0xc:2,er1) ;010769181760 ++ extu.l #2,@er1+ ;01046d181760 ++ extu.l #2,@-er1 ;01076d181760 ++ extu.l #2,@+er1 ;01056d181760 ++ extu.l #2,@er1- ;01066d181760 ++ extu.l #2,@(0x1234:16,er1) ;01046f1812341760 ++ extu.l #2,@(0x12345678:32,er1) ;78946b28123456781760 ++ extu.l #2,@(0x1234:16,r2l.b) ;01056f2812341760 ++ extu.l #2,@(0x1234:16,r2.w) ;01066f2812341760 ++ extu.l #2,@(0x1234:16,er2.l) ;01076f2812341760 ++ extu.l #2,@(0x12345678:32,r2l.b) ;78a56b28123456781760 ++ extu.l #2,@(0x12345678:32,r2.w) ;78a66b28123456781760 ++ extu.l #2,@(0x12345678:32,er2.l) ;78a76b28123456781760 ++ extu.l #2,@0x1234:16 ;01046b0812341760 ++ extu.l #2,@0x12345678:32 ;01046b28123456781760 ++ ++ exts.w r1 ;17d1 ++ exts.w @er1 ;7d9017d0 ++ exts.w @(0x6:2,er1) ;0157691817d0 ++ exts.w @er1+ ;01546d1817d0 ++ exts.w @-er1 ;01576d1817d0 ++ exts.w @+er1 ;01556d1817d0 ++ exts.w @er1- ;01566d1817d0 ++ exts.w @(0x1234:16,er1) ;01546f18123417d0 ++ exts.w @(0x12345678:32,er1) ;78146b281234567817d0 ++ exts.w @(0x1234:16,r2l.b) ;01556f28123417d0 ++ exts.w @(0x1234:16,r2.w) ;01566f28123417d0 ++ exts.w @(0x1234:16,er2.l) ;01576f28123417d0 ++ exts.w @(0x12345678:32,r2l.b) ;78256b281234567817d0 ++ exts.w @(0x12345678:32,r2.w) ;78266b281234567817d0 ++ exts.w @(0x12345678:32,er2.l) ;78276b281234567817d0 ++ exts.w @0x1234:16 ;6b18123417d0 ++ exts.w @0x12345678:32 ;6b381234567817d0 ++ ++ exts.l er1 ;17f1 ++ exts.l @er1 ;0104691817f0 ++ exts.l @(0xc:2,er1) ;0107691817f0 ++ exts.l @er1+ ;01046d1817f0 ++ exts.l @-er1 ;01076d1817f0 ++ exts.l @+er1 ;01056d1817f0 ++ exts.l @er1- ;01066d1817f0 ++ exts.l @(0x1234:16,er1) ;01046f18123417f0 ++ exts.l @(0x12345678:32,er1) ;78946b281234567817f0 ++ exts.l @(0x1234:16,r2l.b) ;01056f28123417f0 ++ exts.l @(0x1234:16,r2.w) ;01066f28123417f0 ++ exts.l @(0x1234:16,er2.l) ;01076f28123417f0 ++ exts.l @(0x12345678:32,r2l.b) ;78a56b281234567817f0 ++ exts.l @(0x12345678:32,r2.w) ;78a66b281234567817f0 ++ exts.l @(0x12345678:32,er2.l) ;78a76b281234567817f0 ++ exts.l @0x1234:16 ;01046b08123417f0 ++ exts.l @0x12345678:32 ;01046b281234567817f0 ++ ++ exts.l #2,er1 ;17e1 ++ exts.l #2,@er1 ;0104691817e0 ++ exts.l #2,@(0xc:2,er1) ;0107691817e0 ++ exts.l #2,@er1+ ;01046d1817e0 ++ exts.l #2,@-er1 ;01076d1817e0 ++ exts.l #2,@+er1 ;01056d1817e0 ++ exts.l #2,@er1- ;01066d1817e0 ++ exts.l #2,@(0x1234:16,er1) ;01046f18123417e0 ++ exts.l #2,@(0x12345678:32,er1) ;78946b281234567817e0 ++ exts.l #2,@(0x1234:16,r2l.b) ;01056f28123417e0 ++ exts.l #2,@(0x1234:16,r2.w) ;01066f28123417e0 ++ exts.l #2,@(0x1234:16,er2.l) ;01076f28123417e0 ++ exts.l #2,@(0x12345678:32,r2l.b) ;78a56b281234567817e0 ++ exts.l #2,@(0x12345678:32,r2.w) ;78a66b281234567817e0 ++ exts.l #2,@(0x12345678:32,er2.l) ;78a76b281234567817e0 ++ exts.l #2,@0x1234:16 ;01046b08123417e0 ++ exts.l #2,@0x12345678:32 ;01046b281234567817e0 ++ ++ .end diff --git a/gas/testsuite/gas/h8300/t08_or.exp b/gas/testsuite/gas/h8300/t08_or.exp new file mode 100644 -index 0000000..b444bf4 +index 0000000..7e1cc71 --- /dev/null +++ b/gas/testsuite/gas/h8300/t08_or.exp -@@ -0,0 +1,3019 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,3018 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1172351,989 +1179525,988 @@ index 0000000..b444bf4 + diff --git a/gas/testsuite/gas/h8300/t08_or.s b/gas/testsuite/gas/h8300/t08_or.s new file mode 100644 -index 0000000..e80d361 +index 0000000..3add588 --- /dev/null +++ b/gas/testsuite/gas/h8300/t08_or.s @@ -0,0 +1,971 @@ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+;log_1 -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ .h8300sx -+ .text -+_start: -+ or.b #0x12:8,r1h ;c112 -+ or.b #0x12:8,@er1 ;7d10c012 -+ or.b #0x12:8,@(0x3:2,er1) ;01776818c012 -+ or.b #0x12:8,@er1+ ;01746c18c012 -+ or.b #0x12:8,@-er1 ;01776c18c012 -+ or.b #0x12:8,@+er1 ;01756c18c012 -+ or.b #0x12:8,@er1- ;01766c18c012 -+ or.b #0x12:8,@(0x1234:16,er1) ;01746e181234c012 -+ or.b #0x12:8,@(0x12345678:32,er1) ;78146a2812345678c012 -+ or.b #0x12:8,@(0x1234:16,r2l.b) ;01756e281234c012 -+ or.b #0x12:8,@(0x1234:16,r2.w) ;01766e281234c012 -+ or.b #0x12:8,@(0x1234:16,er2.l) ;01776e281234c012 -+ or.b #0x12:8,@(0x12345678:32,r2l.b) ;78256a2812345678c012 -+ or.b #0x12:8,@(0x12345678:32,r2.w) ;78266a2812345678c012 -+ or.b #0x12:8,@(0x12345678:32,er2.l) ;78276a2812345678c012 -+ or.b #0x12:8,@0xffffff12:8 ;7f12c012 -+ or.b #0x12:8,@0x1234:16 ;6a181234c012 -+ or.b #0x12:8,@0x12345678:32 ;6a3812345678c012 -+ -+ or.b r3h,r1h ;1431 -+ -+ or.b r3h,@er1 ;7d101430 -+ or.b r3h,@(0x3:2,er1) ;01793143 -+ or.b r3h,@er1+ ;01798143 -+ or.b r3h,@-er1 ;0179b143 -+ or.b r3h,@+er1 ;01799143 -+ or.b r3h,@er1- ;0179a143 -+ or.b r3h,@(0x1234:16,er1) ;0179c1431234 -+ or.b r3h,@(0x12345678:32,er1) ;0179c94312345678 -+ or.b r3h,@(0x1234:16,r2l.b) ;0179d2431234 -+ or.b r3h,@(0x1234:16,r2.w) ;0179e2431234 -+ or.b r3h,@(0x1234:16,er2.l) ;0179f2431234 -+ or.b r3h,@(0x12345678:32,r2l.b) ;0179da4312345678 -+ or.b r3h,@(0x12345678:32,r2.w) ;0179ea4312345678 -+ or.b r3h,@(0x12345678:32,er2.l) ;0179fa4312345678 -+ or.b r3h,@0xffffff12:8 ;7f121430 -+ or.b r3h,@0x1234:16 ;6a1812341430 -+ or.b r3h,@0x12345678:32 ;6a38123456781430 -+ -+ or.b @er3,r1h ;7c301401 -+ or.b @(0x3:2,er3),r1h ;017a3341 -+ or.b @er3+,r1h ;017a8341 -+ or.b @-er3,r1h ;017ab341 -+ or.b @+er3,r1h ;017a9341 -+ or.b @er3-,r1h ;017aa341 -+ or.b @(0x1234:16,er1),r1h ;017ac1411234 -+ or.b @(0x12345678:32,er1),r1h ;017ac94112345678 -+ or.b @(0x1234:16,r2l.b),r1h ;017ad2411234 -+ or.b @(0x1234:16,r2.w),r1h ;017ae2411234 -+ or.b @(0x1234:16,er2.l),r1h ;017af2411234 -+ or.b @(0x12345678:32,r2l.b),r1h ;017ada4112345678 -+ or.b @(0x12345678:32,r2.w),r1h ;017aea4112345678 -+ or.b @(0x12345678:32,er2.l),r1h ;017afa4112345678 -+ or.b @0xffffff12:8,r1h ;7e121401 -+ or.b @0x1234:16,r1h ;6a1012341401 -+ or.b @0x12345678:32,r1h ;6a30123456781401 -+ -+ or.b @er3,@er1 ;7c350140 -+ or.b @er3,@(3:2,er1) ;7c353140 -+ or.b @er3,@-er1 ;7c35b140 -+ or.b @er3,@er1+ ;7c358140 -+ or.b @er3,@er1- ;7c35a140 -+ or.b @er3,@+er1 ;7c359140 -+ or.b @er3,@(0xffff9abc:16,er1) ;7c35c1409abc -+ or.b @er3,@(0x9abcdef0:32,er1) ;7c35c9409abcdef0 -+ or.b @er3,@(0xffff9abc:16,r2l.b) ;7c35d2409abc -+ or.b @er3,@(0xffff9abc:16,r2.w) ;7c35e2409abc -+ or.b @er3,@(0xffff9abc:16,er2.l) ;7c35f2409abc -+ or.b @er3,@(0x9abcdef0:32,r2l.b) ;7c35da409abcdef0 -+ or.b @er3,@(0x9abcdef0:32,r2.w) ;7c35ea409abcdef0 -+ or.b @er3,@(0x9abcdef0:32,er2.l) ;7c35fa409abcdef0 -+ or.b @er3,@0xffff9abc:16 ;7c3540409abc -+ or.b @er3,@0x9abcdef0:32 ;7c3548409abcdef0 -+ -+ or.b @-er3,@er1 ;01776c3c0140 -+ or.b @-er3,@(3:2,er1) ;01776c3c3140 -+ or.b @-er3,@-er1 ;01776c3cb140 -+ or.b @-er3,@er1+ ;01776c3c8140 -+ or.b @-er3,@er1- ;01776c3ca140 -+ or.b @-er3,@+er1 ;01776c3c9140 -+ or.b @-er3,@(0xffff9abc:16,er1) ;01776c3cc1409abc -+ or.b @-er3,@(0x9abcdef0:32,er1) ;01776c3cc9409abcdef0 -+ or.b @-er3,@(0xffff9abc:16,r2l.b) ;01776c3cd2409abc -+ or.b @-er3,@(0xffff9abc:16,r2.w) ;01776c3ce2409abc -+ or.b @-er3,@(0xffff9abc:16,er2.l) ;01776c3cf2409abc -+ or.b @-er3,@(0x9abcdef0:32,r2l.b) ;01776c3cda409abcdef0 -+ or.b @-er3,@(0x9abcdef0:32,r2.w) ;01776c3cea409abcdef0 -+ or.b @-er3,@(0x9abcdef0:32,er2.l) ;01776c3cfa409abcdef0 -+ or.b @-er3,@0xffff9abc:16 ;01776c3c40409abc -+ or.b @-er3,@0x9abcdef0:32 ;01776c3c48409abcdef0 -+ -+ or.b @er3+,@er1 ;01746c3c0140 -+ or.b @er3+,@(3:2,er1) ;01746c3c3140 -+ or.b @er3+,@-er1 ;01746c3cb140 -+ or.b @er3+,@er1+ ;01746c3c8140 -+ or.b @er3+,@er1- ;01746c3ca140 -+ or.b @er3+,@+er1 ;01746c3c9140 -+ or.b @er3+,@(0xffff9abc:16,er1) ;01746c3cc1409abc -+ or.b @er3+,@(0x9abcdef0:32,er1) ;01746c3cc9409abcdef0 -+ or.b @er3+,@(0xffff9abc:16,r2l.b) ;01746c3cd2409abc -+ or.b @er3+,@(0xffff9abc:16,r2.w) ;01746c3ce2409abc -+ or.b @er3+,@(0xffff9abc:16,er2.l) ;01746c3cf2409abc -+ or.b @er3+,@(0x9abcdef0:32,r2l.b) ;01746c3cda409abcdef0 -+ or.b @er3+,@(0x9abcdef0:32,r2.w) ;01746c3cea409abcdef0 -+ or.b @er3+,@(0x9abcdef0:32,er2.l) ;01746c3cfa409abcdef0 -+ or.b @er3+,@0xffff9abc:16 ;01746c3c40409abc -+ or.b @er3+,@0x9abcdef0:32 ;01746c3c48409abcdef0 -+ -+ or.b @er3-,@er1 ;01766c3c0140 -+ or.b @er3-,@(3:2,er1) ;01766c3c3140 -+ or.b @er3-,@-er1 ;01766c3cb140 -+ or.b @er3-,@er1+ ;01766c3c8140 -+ or.b @er3-,@er1- ;01766c3ca140 -+ or.b @er3-,@+er1 ;01766c3c9140 -+ or.b @er3-,@(0xffff9abc:16,er1) ;01766c3cc1409abc -+ or.b @er3-,@(0x9abcdef0:32,er1) ;01766c3cc9409abcdef0 -+ or.b @er3-,@(0xffff9abc:16,r2l.b) ;01766c3cd2409abc -+ or.b @er3-,@(0xffff9abc:16,r2.w) ;01766c3ce2409abc -+ or.b @er3-,@(0xffff9abc:16,er2.l) ;01766c3cf2409abc -+ or.b @er3-,@(0x9abcdef0:32,r2l.b) ;01766c3cda409abcdef0 -+ or.b @er3-,@(0x9abcdef0:32,r2.w) ;01766c3cea409abcdef0 -+ or.b @er3-,@(0x9abcdef0:32,er2.l) ;01766c3cfa409abcdef0 -+ or.b @er3-,@0xffff9abc:16 ;01766c3c40409abc -+ or.b @er3-,@0x9abcdef0:32 ;01766c3c48409abcdef0 -+ -+ or.b @+er3,@er1 ;01756c3c0140 -+ or.b @+er3,@(3:2,er1) ;01756c3c3140 -+ or.b @+er3,@-er1 ;01756c3cb140 -+ or.b @+er3,@er1+ ;01756c3c8140 -+ or.b @+er3,@er1- ;01756c3ca140 -+ or.b @+er3,@+er1 ;01756c3c9140 -+ or.b @+er3,@(0xffff9abc:16,er1) ;01756c3cc1409abc -+ or.b @+er3,@(0x9abcdef0:32,er1) ;01756c3cc9409abcdef0 -+ or.b @+er3,@(0xffff9abc:16,r2l.b) ;01756c3cd2409abc -+ or.b @+er3,@(0xffff9abc:16,r2.w) ;01756c3ce2409abc -+ or.b @+er3,@(0xffff9abc:16,er2.l) ;01756c3cf2409abc -+ or.b @+er3,@(0x9abcdef0:32,r2l.b) ;01756c3cda409abcdef0 -+ or.b @+er3,@(0x9abcdef0:32,r2.w) ;01756c3cea409abcdef0 -+ or.b @+er3,@(0x9abcdef0:32,er2.l) ;01756c3cfa409abcdef0 -+ or.b @+er3,@0xffff9abc:16 ;01756c3c40409abc -+ or.b @+er3,@0x9abcdef0:32 ;01756c3c48409abcdef0 -+ -+ or.b @(0x1234:16,er3),@er1 ;01746e3c12340140 -+ or.b @(0x1234:16,er3),@(3:2,er1) ;01746e3c12343140 -+ or.b @(0x1234:16,er3),@-er1 ;01746e3c1234b140 -+ or.b @(0x1234:16,er3),@er1+ ;01746e3c12348140 -+ or.b @(0x1234:16,er3),@er1- ;01746e3c1234a140 -+ or.b @(0x1234:16,er3),@+er1 ;01746e3c12349140 -+ or.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01746e3c1234c1409abc -+ or.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01746e3c1234c9409abcdef0 -+ or.b @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01746e3c1234d2409abc -+ or.b @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01746e3c1234e2409abc -+ or.b @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01746e3c1234f2409abc -+ or.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01746e3c1234da409abcdef0 -+ or.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01746e3c1234ea409abcdef0 -+ or.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01746e3c1234fa409abcdef0 -+ or.b @(0x1234:16,er3),@0xffff9abc:16 ;01746e3c123440409abc -+ or.b @(0x1234:16,er3),@0x9abcdef0:32 ;01746e3c123448409abcdef0 -+ -+ or.b @(0x12345678:32,er3),@er1 ;78346a2c123456780140 -+ or.b @(0x12345678:32,er3),@(3:2,er1) ;78346a2c123456783140 -+ or.b @(0x12345678:32,er3),@-er1 ;78346a2c12345678b140 -+ or.b @(0x12345678:32,er3),@er1+ ;78346a2c123456788140 -+ or.b @(0x12345678:32,er3),@er1- ;78346a2c12345678a140 -+ or.b @(0x12345678:32,er3),@+er1 ;78346a2c123456789140 -+ or.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346a2c12345678c1409abc -+ or.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346a2c12345678c9409abcdef0 -+ or.b @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346a2c12345678d2409abc -+ or.b @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346a2c12345678e2409abc -+ or.b @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346a2c12345678f2409abc -+ or.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346a2c12345678da409abcdef0 -+ or.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346a2c12345678ea409abcdef0 -+ or.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346a2c12345678fa409abcdef0 -+ or.b @(0x12345678:32,er3),@0xffff9abc:16 ;78346a2c1234567840409abc -+ or.b @(0x12345678:32,er3),@0x9abcdef0:32 ;78346a2c1234567848409abcdef0 -+ -+ or.b @(0x1234:16,r3l.b),@er1 ;01756e3c12340140 -+ or.b @(0x1234:16,r3l.b),@(3:2,er1) ;01756e3c12343140 -+ or.b @(0x1234:16,r3l.b),@-er1 ;01756e3c1234b140 -+ or.b @(0x1234:16,r3l.b),@er1+ ;01756e3c12348140 -+ or.b @(0x1234:16,r3l.b),@er1- ;01756e3c1234a140 -+ or.b @(0x1234:16,r3l.b),@+er1 ;01756e3c12349140 -+ or.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01756e3c1234c1409abc -+ or.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01756e3c1234c9409abcdef0 -+ or.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01756e3c1234d2409abc -+ or.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01756e3c1234e2409abc -+ or.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01756e3c1234f2409abc -+ or.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01756e3c1234da409abcdef0 -+ or.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01756e3c1234ea409abcdef0 -+ or.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01756e3c1234fa409abcdef0 -+ or.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;01756e3c123440409abc -+ or.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01756e3c123448409abcdef0 -+ -+ or.b @(0x1234:16,r3.w),@er1 ;01766e3c12340140 -+ or.b @(0x1234:16,r3.w),@(3:2,er1) ;01766e3c12343140 -+ or.b @(0x1234:16,r3.w),@-er1 ;01766e3c1234b140 -+ or.b @(0x1234:16,r3.w),@er1+ ;01766e3c12348140 -+ or.b @(0x1234:16,r3.w),@er1- ;01766e3c1234a140 -+ or.b @(0x1234:16,r3.w),@+er1 ;01766e3c12349140 -+ or.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01766e3c1234c1409abc -+ or.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01766e3c1234c9409abcdef0 -+ or.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01766e3c1234d2409abc -+ or.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01766e3c1234e2409abc -+ or.b @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01766e3c1234f2409abc -+ or.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01766e3c1234da409abcdef0 -+ or.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01766e3c1234ea409abcdef0 -+ or.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01766e3c1234fa409abcdef0 -+ or.b @(0x1234:16,r3.w),@0xffff9abc:16 ;01766e3c123440409abc -+ or.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;01766e3c123448409abcdef0 -+ -+ or.b @(0x1234:16,er3.l),@er1 ;01776e3c12340140 -+ or.b @(0x1234:16,er3.l),@(3:2,er1) ;01776e3c12343140 -+ or.b @(0x1234:16,er3.l),@-er1 ;01776e3c1234b140 -+ or.b @(0x1234:16,er3.l),@er1+ ;01776e3c12348140 -+ or.b @(0x1234:16,er3.l),@er1- ;01776e3c1234a140 -+ or.b @(0x1234:16,er3.l),@+er1 ;01776e3c12349140 -+ or.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01776e3c1234c1409abc -+ or.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01776e3c1234c9409abcdef0 -+ or.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01776e3c1234d2409abc -+ or.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01776e3c1234e2409abc -+ or.b @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01776e3c1234f2409abc -+ or.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01776e3c1234da409abcdef0 -+ or.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01776e3c1234ea409abcdef0 -+ or.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01776e3c1234fa409abcdef0 -+ or.b @(0x1234:16,er3.l),@0xffff9abc:16 ;01776e3c123440409abc -+ or.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;01776e3c123448409abcdef0 -+ -+ or.b @(0x12345678:32,r3l.b),@er1 ;78356a2c123456780140 -+ or.b @(0x12345678:32,r3l.b),@(3:2,er1) ;78356a2c123456783140 -+ or.b @(0x12345678:32,r3l.b),@-er1 ;78356a2c12345678b140 -+ or.b @(0x12345678:32,r3l.b),@er1+ ;78356a2c123456788140 -+ or.b @(0x12345678:32,r3l.b),@er1- ;78356a2c12345678a140 -+ or.b @(0x12345678:32,r3l.b),@+er1 ;78356a2c123456789140 -+ or.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356a2c12345678c1409abc -+ or.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356a2c12345678c9409abcdef0 -+ or.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356a2c12345678d2409abc -+ or.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356a2c12345678e2409abc -+ or.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356a2c12345678f2409abc -+ or.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356a2c12345678da409abcdef0 -+ or.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356a2c12345678ea409abcdef0 -+ or.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356a2c12345678fa409abcdef0 -+ or.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356a2c1234567840409abc -+ or.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356a2c1234567848409abcdef0 -+ -+ or.b @(0x12345678:32,r3.w),@er1 ;78366a2c123456780140 -+ or.b @(0x12345678:32,r3.w),@(3:2,er1) ;78366a2c123456783140 -+ or.b @(0x12345678:32,r3.w),@-er1 ;78366a2c12345678b140 -+ or.b @(0x12345678:32,r3.w),@er1+ ;78366a2c123456788140 -+ or.b @(0x12345678:32,r3.w),@er1- ;78366a2c12345678a140 -+ or.b @(0x12345678:32,r3.w),@+er1 ;78366a2c123456789140 -+ or.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366a2c12345678c1409abc -+ or.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366a2c12345678c9409abcdef0 -+ or.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366a2c12345678d2409abc -+ or.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366a2c12345678e2409abc -+ or.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366a2c12345678f2409abc -+ or.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366a2c12345678da409abcdef0 -+ or.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366a2c12345678ea409abcdef0 -+ or.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366a2c12345678fa409abcdef0 -+ or.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366a2c1234567840409abc -+ or.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366a2c1234567848409abcdef0 -+ -+ or.b @(0x12345678:32,er3.l),@er1 ;78376a2c123456780140 -+ or.b @(0x12345678:32,er3.l),@(3:2,er1) ;78376a2c123456783140 -+ or.b @(0x12345678:32,er3.l),@-er1 ;78376a2c12345678b140 -+ or.b @(0x12345678:32,er3.l),@er1+ ;78376a2c123456788140 -+ or.b @(0x12345678:32,er3.l),@er1- ;78376a2c12345678a140 -+ or.b @(0x12345678:32,er3.l),@+er1 ;78376a2c123456789140 -+ or.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376a2c12345678c1409abc -+ or.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376a2c12345678c9409abcdef0 -+ or.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376a2c12345678d2409abc -+ or.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376a2c12345678e2409abc -+ or.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376a2c12345678f2409abc -+ or.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376a2c12345678da409abcdef0 -+ or.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376a2c12345678ea409abcdef0 -+ or.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376a2c12345678fa409abcdef0 -+ or.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376a2c1234567840409abc -+ or.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376a2c1234567848409abcdef0 -+ -+ or.b @0x1234:16,@er1 ;6a1512340140 -+ or.b @0x1234:16,@(3:2,er1) ;6a1512343140 -+ or.b @0x1234:16,@-er1 ;6a151234b140 -+ or.b @0x1234:16,@er1+ ;6a1512348140 -+ or.b @0x1234:16,@er1- ;6a151234a140 -+ or.b @0x1234:16,@+er1 ;6a1512349140 -+ or.b @0x1234:16,@(0xffff9abc:16,er1) ;6a151234c1409abc -+ or.b @0x1234:16,@(0x9abcdef0:32,er1) ;6a151234c9409abcdef0 -+ or.b @0x1234:16,@(0xffff9abc:16,r2l.b) ;6a151234d2409abc -+ or.b @0x1234:16,@(0xffff9abc:16,r2.w) ;6a151234e2409abc -+ or.b @0x1234:16,@(0xffff9abc:16,er2.l) ;6a151234f2409abc -+ or.b @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6a151234da409abcdef0 -+ or.b @0x1234:16,@(0x9abcdef0:32,r2.w) ;6a151234ea409abcdef0 -+ or.b @0x1234:16,@(0x9abcdef0:32,er2.l) ;6a151234fa409abcdef0 -+ or.b @0x1234:16,@0xffff9abc:16 ;6a15123440409abc -+ or.b @0x1234:16,@0x9abcdef0:32 ;6a15123448409abcdef0 -+ -+ or.b @0x12345678:32,@er1 ;6a35123456780140 -+ or.b @0x12345678:32,@(3:2,er1) ;6a35123456783140 -+ or.b @0x12345678:32,@-er1 ;6a3512345678b140 -+ or.b @0x12345678:32,@er1+ ;6a35123456788140 -+ or.b @0x12345678:32,@er1- ;6a3512345678a140 -+ or.b @0x12345678:32,@+er1 ;6a35123456789140 -+ or.b @0x12345678:32,@(0xffff9abc:16,er1) ;6a3512345678c1409abc -+ or.b @0x12345678:32,@(0x9abcdef0:32,er1) ;6a3512345678c9409abcdef0 -+ or.b @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6a3512345678d2409abc -+ or.b @0x12345678:32,@(0xffff9abc:16,r2.w) ;6a3512345678e2409abc -+ or.b @0x12345678:32,@(0xffff9abc:16,er2.l) ;6a3512345678f2409abc -+ or.b @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6a3512345678da409abcdef0 -+ or.b @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6a3512345678ea409abcdef0 -+ or.b @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6a3512345678fa409abcdef0 -+ or.b @0x12345678:32,@0xffff9abc:16 ;6a351234567840409abc -+ or.b @0x12345678:32,@0x9abcdef0:32 ;6a351234567848409abcdef0 -+ -+ or.w #0x1234:16,r1 ;79411234 -+ or.w #0x1234:16,@er1 ;015e01401234 -+ or.w #0x1234:16,@(0x6:2,er1) ;015e31401234 -+ or.w #0x1234:16,@er1+ ;015e81401234 -+ or.w #0x1234:16,@-er1 ;015eb1401234 -+ or.w #0x1234:16,@+er1 ;015e91401234 -+ or.w #0x1234:16,@er1- ;015ea1401234 -+ or.w #0x1234:16,@(0xffff9abc:16,er1) ;015ec1409abc1234 -+ or.w #0x1234:16,@(0x9abcdef0:32,er1) ;015ec9409abcdef01234 -+ or.w #0x1234:16,@(0xffff9abc:16,r2l.b) ;015ed2409abc1234 -+ or.w #0x1234:16,@(0xffff9abc:16,r2.w) ;015ee2409abc1234 -+ or.w #0x1234:16,@(0xffff9abc:16,er2.l) ;015ef2409abc1234 -+ or.w #0x1234:16,@(0x9abcdef0:32,r2l.b) ;015eda409abcdef01234 -+ or.w #0x1234:16,@(0x9abcdef0:32,r2.w) ;015eea409abcdef01234 -+ or.w #0x1234:16,@(0x9abcdef0:32,er2.l) ;015efa409abcdef01234 -+ or.w #0x1234:16,@0xffff9abc:16 ;015e40409abc1234 -+ or.w #0x1234:16,@0x9abcdef0:32 ;015e48409abcdef01234 -+ -+ or.w r3,r1 ;6431 -+ -+ or.w r3,@er1 ;7d906430 -+ or.w r3,@(0x6:2,er1) ;01593143 -+ or.w r3,@er1+ ;01598143 -+ or.w r3,@-er1 ;0159b143 -+ or.w r3,@+er1 ;01599143 -+ or.w r3,@er1- ;0159a143 -+ or.w r3,@(0x1234:16,er1) ;0159c1431234 -+ or.w r3,@(0x12345678:32,er1) ;0159c94312345678 -+ or.w r3,@(0x1234:16,r2l.b) ;0159d2431234 -+ or.w r3,@(0x1234:16,r2.w) ;0159e2431234 -+ or.w r3,@(0x1234:16,er2.l) ;0159f2431234 -+ or.w r3,@(0x12345678:32,r2l.b) ;0159da4312345678 -+ or.w r3,@(0x12345678:32,r2.w) ;0159ea4312345678 -+ or.w r3,@(0x12345678:32,er2.l) ;0159fa4312345678 -+ or.w r3,@0x1234:16 ;6b1812346430 -+ or.w r3,@0x12345678:32 ;6b38123456786430 -+ -+ or.w @er3,r1 ;7cb06401 -+ or.w @(0x6:2,er3),r1 ;015a3341 -+ or.w @er3+,r1 ;015a8341 -+ or.w @-er3,r1 ;015ab341 -+ or.w @+er3,r1 ;015a9341 -+ or.w @er3-,r1 ;015aa341 -+ or.w @(0x1234:16,er1),r1 ;015ac1411234 -+ or.w @(0x12345678:32,er1),r1 ;015ac94112345678 -+ or.w @(0x1234:16,r2l.b),r1 ;015ad2411234 -+ or.w @(0x1234:16,r2.w),r1 ;015ae2411234 -+ or.w @(0x1234:16,er2.l),r1 ;015af2411234 -+ or.w @(0x12345678:32,r2l.b),r1 ;015ada4112345678 -+ or.w @(0x12345678:32,r2.w),r1 ;015aea4112345678 -+ or.w @(0x12345678:32,er2.l),r1 ;015afa4112345678 -+ or.w @0x1234:16,r1 ;6b1012346401 -+ or.w @0x12345678:32,r1 ;6b30123456786401 -+ -+ or.w @er3,@er1 ;7cb50140 -+ or.w @er3,@(6:2,er1) ;7cb53140 -+ or.w @er3,@-er1 ;7cb5b140 -+ or.w @er3,@er1+ ;7cb58140 -+ or.w @er3,@er1- ;7cb5a140 -+ or.w @er3,@+er1 ;7cb59140 -+ or.w @er3,@(0xffff9abc:16,er1) ;7cb5c1409abc -+ or.w @er3,@(0x9abcdef0:32,er1) ;7cb5c9409abcdef0 -+ or.w @er3,@(0xffff9abc:16,r2l.b) ;7cb5d2409abc -+ or.w @er3,@(0xffff9abc:16,r2.w) ;7cb5e2409abc -+ or.w @er3,@(0xffff9abc:16,er2.l) ;7cb5f2409abc -+ or.w @er3,@(0x9abcdef0:32,r2l.b) ;7cb5da409abcdef0 -+ or.w @er3,@(0x9abcdef0:32,r2.w) ;7cb5ea409abcdef0 -+ or.w @er3,@(0x9abcdef0:32,er2.l) ;7cb5fa409abcdef0 -+ or.w @er3,@0xffff9abc:16 ;7cb540409abc -+ or.w @er3,@0x9abcdef0:32 ;7cb548409abcdef0 -+ -+ or.w @-er3,@er1 ;01576d3c0140 -+ or.w @-er3,@(6:2,er1) ;01576d3c3140 -+ or.w @-er3,@-er1 ;01576d3cb140 -+ or.w @-er3,@er1+ ;01576d3c8140 -+ or.w @-er3,@er1- ;01576d3ca140 -+ or.w @-er3,@+er1 ;01576d3c9140 -+ or.w @-er3,@(0xffff9abc:16,er1) ;01576d3cc1409abc -+ or.w @-er3,@(0x9abcdef0:32,er1) ;01576d3cc9409abcdef0 -+ or.w @-er3,@(0xffff9abc:16,r2l.b) ;01576d3cd2409abc -+ or.w @-er3,@(0xffff9abc:16,r2.w) ;01576d3ce2409abc -+ or.w @-er3,@(0xffff9abc:16,er2.l) ;01576d3cf2409abc -+ or.w @-er3,@(0x9abcdef0:32,r2l.b) ;01576d3cda409abcdef0 -+ or.w @-er3,@(0x9abcdef0:32,r2.w) ;01576d3cea409abcdef0 -+ or.w @-er3,@(0x9abcdef0:32,er2.l) ;01576d3cfa409abcdef0 -+ or.w @-er3,@0xffff9abc:16 ;01576d3c40409abc -+ or.w @-er3,@0x9abcdef0:32 ;01576d3c48409abcdef0 -+ -+ or.w @er3+,@er1 ;01546d3c0140 -+ or.w @er3+,@(6:2,er1) ;01546d3c3140 -+ or.w @er3+,@-er1 ;01546d3cb140 -+ or.w @er3+,@er1+ ;01546d3c8140 -+ or.w @er3+,@er1- ;01546d3ca140 -+ or.w @er3+,@+er1 ;01546d3c9140 -+ or.w @er3+,@(0xffff9abc:16,er1) ;01546d3cc1409abc -+ or.w @er3+,@(0x9abcdef0:32,er1) ;01546d3cc9409abcdef0 -+ or.w @er3+,@(0xffff9abc:16,r2l.b) ;01546d3cd2409abc -+ or.w @er3+,@(0xffff9abc:16,r2.w) ;01546d3ce2409abc -+ or.w @er3+,@(0xffff9abc:16,er2.l) ;01546d3cf2409abc -+ or.w @er3+,@(0x9abcdef0:32,r2l.b) ;01546d3cda409abcdef0 -+ or.w @er3+,@(0x9abcdef0:32,r2.w) ;01546d3cea409abcdef0 -+ or.w @er3+,@(0x9abcdef0:32,er2.l) ;01546d3cfa409abcdef0 -+ or.w @er3+,@0xffff9abc:16 ;01546d3c40409abc -+ or.w @er3+,@0x9abcdef0:32 ;01546d3c48409abcdef0 -+ -+ or.w @er3-,@er1 ;01566d3c0140 -+ or.w @er3-,@(6:2,er1) ;01566d3c3140 -+ or.w @er3-,@-er1 ;01566d3cb140 -+ or.w @er3-,@er1+ ;01566d3c8140 -+ or.w @er3-,@er1- ;01566d3ca140 -+ or.w @er3-,@+er1 ;01566d3c9140 -+ or.w @er3-,@(0xffff9abc:16,er1) ;01566d3cc1409abc -+ or.w @er3-,@(0x9abcdef0:32,er1) ;01566d3cc9409abcdef0 -+ or.w @er3-,@(0xffff9abc:16,r2l.b) ;01566d3cd2409abc -+ or.w @er3-,@(0xffff9abc:16,r2.w) ;01566d3ce2409abc -+ or.w @er3-,@(0xffff9abc:16,er2.l) ;01566d3cf2409abc -+ or.w @er3-,@(0x9abcdef0:32,r2l.b) ;01566d3cda409abcdef0 -+ or.w @er3-,@(0x9abcdef0:32,r2.w) ;01566d3cea409abcdef0 -+ or.w @er3-,@(0x9abcdef0:32,er2.l) ;01566d3cfa409abcdef0 -+ or.w @er3-,@0xffff9abc:16 ;01566d3c40409abc -+ or.w @er3-,@0x9abcdef0:32 ;01566d3c48409abcdef0 -+ -+ or.w @+er3,@er1 ;01556d3c0140 -+ or.w @+er3,@(6:2,er1) ;01556d3c3140 -+ or.w @+er3,@-er1 ;01556d3cb140 -+ or.w @+er3,@er1+ ;01556d3c8140 -+ or.w @+er3,@er1- ;01556d3ca140 -+ or.w @+er3,@+er1 ;01556d3c9140 -+ or.w @+er3,@(0xffff9abc:16,er1) ;01556d3cc1409abc -+ or.w @+er3,@(0x9abcdef0:32,er1) ;01556d3cc9409abcdef0 -+ or.w @+er3,@(0xffff9abc:16,r2l.b) ;01556d3cd2409abc -+ or.w @+er3,@(0xffff9abc:16,r2.w) ;01556d3ce2409abc -+ or.w @+er3,@(0xffff9abc:16,er2.l) ;01556d3cf2409abc -+ or.w @+er3,@(0x9abcdef0:32,r2l.b) ;01556d3cda409abcdef0 -+ or.w @+er3,@(0x9abcdef0:32,r2.w) ;01556d3cea409abcdef0 -+ or.w @+er3,@(0x9abcdef0:32,er2.l) ;01556d3cfa409abcdef0 -+ or.w @+er3,@0xffff9abc:16 ;01556d3c40409abc -+ or.w @+er3,@0x9abcdef0:32 ;01556d3c48409abcdef0 -+ -+ or.w @(0x1234:16,er3),@er1 ;01546f3c12340140 -+ or.w @(0x1234:16,er3),@(6:2,er1) ;01546f3c12343140 -+ or.w @(0x1234:16,er3),@-er1 ;01546f3c1234b140 -+ or.w @(0x1234:16,er3),@er1+ ;01546f3c12348140 -+ or.w @(0x1234:16,er3),@er1- ;01546f3c1234a140 -+ or.w @(0x1234:16,er3),@+er1 ;01546f3c12349140 -+ or.w @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01546f3c1234c1409abc -+ or.w @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01546f3c1234c9409abcdef0 -+ or.w @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01546f3c1234d2409abc -+ or.w @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01546f3c1234e2409abc -+ or.w @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01546f3c1234f2409abc -+ or.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01546f3c1234da409abcdef0 -+ or.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01546f3c1234ea409abcdef0 -+ or.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01546f3c1234fa409abcdef0 -+ or.w @(0x1234:16,er3),@0xffff9abc:16 ;01546f3c123440409abc -+ or.w @(0x1234:16,er3),@0x9abcdef0:32 ;01546f3c123448409abcdef0 -+ -+ or.w @(0x12345678:32,er3),@er1 ;78346b2c123456780140 -+ or.w @(0x12345678:32,er3),@(6:2,er1) ;78346b2c123456783140 -+ or.w @(0x12345678:32,er3),@-er1 ;78346b2c12345678b140 -+ or.w @(0x12345678:32,er3),@er1+ ;78346b2c123456788140 -+ or.w @(0x12345678:32,er3),@er1- ;78346b2c12345678a140 -+ or.w @(0x12345678:32,er3),@+er1 ;78346b2c123456789140 -+ or.w @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346b2c12345678c1409abc -+ or.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346b2c12345678c9409abcdef0 -+ or.w @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346b2c12345678d2409abc -+ or.w @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346b2c12345678e2409abc -+ or.w @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346b2c12345678f2409abc -+ or.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346b2c12345678da409abcdef0 -+ or.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346b2c12345678ea409abcdef0 -+ or.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346b2c12345678fa409abcdef0 -+ or.w @(0x12345678:32,er3),@0xffff9abc:16 ;78346b2c1234567840409abc -+ or.w @(0x12345678:32,er3),@0x9abcdef0:32 ;78346b2c1234567848409abcdef0 -+ -+ or.w @(0x1234:16,r3l.b),@er1 ;01556f3c12340140 -+ or.w @(0x1234:16,r3l.b),@(6:2,er1) ;01556f3c12343140 -+ or.w @(0x1234:16,r3l.b),@-er1 ;01556f3c1234b140 -+ or.w @(0x1234:16,r3l.b),@er1+ ;01556f3c12348140 -+ or.w @(0x1234:16,r3l.b),@er1- ;01556f3c1234a140 -+ or.w @(0x1234:16,r3l.b),@+er1 ;01556f3c12349140 -+ or.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01556f3c1234c1409abc -+ or.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01556f3c1234c9409abcdef0 -+ or.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01556f3c1234d2409abc -+ or.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01556f3c1234e2409abc -+ or.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01556f3c1234f2409abc -+ or.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01556f3c1234da409abcdef0 -+ or.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01556f3c1234ea409abcdef0 -+ or.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01556f3c1234fa409abcdef0 -+ or.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;01556f3c123440409abc -+ or.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01556f3c123448409abcdef0 -+ -+ or.w @(0x1234:16,r3.w),@er1 ;01566f3c12340140 -+ or.w @(0x1234:16,r3.w),@(6:2,er1) ;01566f3c12343140 -+ or.w @(0x1234:16,r3.w),@-er1 ;01566f3c1234b140 -+ or.w @(0x1234:16,r3.w),@er1+ ;01566f3c12348140 -+ or.w @(0x1234:16,r3.w),@er1- ;01566f3c1234a140 -+ or.w @(0x1234:16,r3.w),@+er1 ;01566f3c12349140 -+ or.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01566f3c1234c1409abc -+ or.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01566f3c1234c9409abcdef0 -+ or.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01566f3c1234d2409abc -+ or.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01566f3c1234e2409abc -+ or.w @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01566f3c1234f2409abc -+ or.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01566f3c1234da409abcdef0 -+ or.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01566f3c1234ea409abcdef0 -+ or.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01566f3c1234fa409abcdef0 -+ or.w @(0x1234:16,r3.w),@0xffff9abc:16 ;01566f3c123440409abc -+ or.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;01566f3c123448409abcdef0 -+ -+ or.w @(0x1234:16,er3.l),@er1 ;01576f3c12340140 -+ or.w @(0x1234:16,er3.l),@(6:2,er1) ;01576f3c12343140 -+ or.w @(0x1234:16,er3.l),@-er1 ;01576f3c1234b140 -+ or.w @(0x1234:16,er3.l),@er1+ ;01576f3c12348140 -+ or.w @(0x1234:16,er3.l),@er1- ;01576f3c1234a140 -+ or.w @(0x1234:16,er3.l),@+er1 ;01576f3c12349140 -+ or.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01576f3c1234c1409abc -+ or.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01576f3c1234c9409abcdef0 -+ or.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01576f3c1234d2409abc -+ or.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01576f3c1234e2409abc -+ or.w @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01576f3c1234f2409abc -+ or.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01576f3c1234da409abcdef0 -+ or.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01576f3c1234ea409abcdef0 -+ or.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01576f3c1234fa409abcdef0 -+ or.w @(0x1234:16,er3.l),@0xffff9abc:16 ;01576f3c123440409abc -+ or.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;01576f3c123448409abcdef0 -+ -+ or.w @(0x12345678:32,r3l.b),@er1 ;78356b2c123456780140 -+ or.w @(0x12345678:32,r3l.b),@(6:2,er1) ;78356b2c123456783140 -+ or.w @(0x12345678:32,r3l.b),@-er1 ;78356b2c12345678b140 -+ or.w @(0x12345678:32,r3l.b),@er1+ ;78356b2c123456788140 -+ or.w @(0x12345678:32,r3l.b),@er1- ;78356b2c12345678a140 -+ or.w @(0x12345678:32,r3l.b),@+er1 ;78356b2c123456789140 -+ or.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356b2c12345678c1409abc -+ or.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356b2c12345678c9409abcdef0 -+ or.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356b2c12345678d2409abc -+ or.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356b2c12345678e2409abc -+ or.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356b2c12345678f2409abc -+ or.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356b2c12345678da409abcdef0 -+ or.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356b2c12345678ea409abcdef0 -+ or.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356b2c12345678fa409abcdef0 -+ or.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356b2c1234567840409abc -+ or.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356b2c1234567848409abcdef0 -+ -+ or.w @(0x12345678:32,r3.w),@er1 ;78366b2c123456780140 -+ or.w @(0x12345678:32,r3.w),@(6:2,er1) ;78366b2c123456783140 -+ or.w @(0x12345678:32,r3.w),@-er1 ;78366b2c12345678b140 -+ or.w @(0x12345678:32,r3.w),@er1+ ;78366b2c123456788140 -+ or.w @(0x12345678:32,r3.w),@er1- ;78366b2c12345678a140 -+ or.w @(0x12345678:32,r3.w),@+er1 ;78366b2c123456789140 -+ or.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366b2c12345678c1409abc -+ or.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366b2c12345678c9409abcdef0 -+ or.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366b2c12345678d2409abc -+ or.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366b2c12345678e2409abc -+ or.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366b2c12345678f2409abc -+ or.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366b2c12345678da409abcdef0 -+ or.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366b2c12345678ea409abcdef0 -+ or.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366b2c12345678fa409abcdef0 -+ or.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366b2c1234567840409abc -+ or.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366b2c1234567848409abcdef0 -+ -+ or.w @(0x12345678:32,er3.l),@er1 ;78376b2c123456780140 -+ or.w @(0x12345678:32,er3.l),@(6:2,er1) ;78376b2c123456783140 -+ or.w @(0x12345678:32,er3.l),@-er1 ;78376b2c12345678b140 -+ or.w @(0x12345678:32,er3.l),@er1+ ;78376b2c123456788140 -+ or.w @(0x12345678:32,er3.l),@er1- ;78376b2c12345678a140 -+ or.w @(0x12345678:32,er3.l),@+er1 ;78376b2c123456789140 -+ or.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376b2c12345678c1409abc -+ or.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376b2c12345678c9409abcdef0 -+ or.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376b2c12345678d2409abc -+ or.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376b2c12345678e2409abc -+ or.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376b2c12345678f2409abc -+ or.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376b2c12345678da409abcdef0 -+ or.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376b2c12345678ea409abcdef0 -+ or.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376b2c12345678fa409abcdef0 -+ or.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376b2c1234567840409abc -+ or.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376b2c1234567848409abcdef0 -+ -+ or.w @0x1234:16,@er1 ;6b1512340140 -+ or.w @0x1234:16,@(6:2,er1) ;6b1512343140 -+ or.w @0x1234:16,@-er1 ;6b151234b140 -+ or.w @0x1234:16,@er1+ ;6b1512348140 -+ or.w @0x1234:16,@er1- ;6b151234a140 -+ or.w @0x1234:16,@+er1 ;6b1512349140 -+ or.w @0x1234:16,@(0xffff9abc:16,er1) ;6b151234c1409abc -+ or.w @0x1234:16,@(0x9abcdef0:32,er1) ;6b151234c9409abcdef0 -+ or.w @0x1234:16,@(0xffff9abc:16,r2l.b) ;6b151234d2409abc -+ or.w @0x1234:16,@(0xffff9abc:16,r2.w) ;6b151234e2409abc -+ or.w @0x1234:16,@(0xffff9abc:16,er2.l) ;6b151234f2409abc -+ or.w @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6b151234da409abcdef0 -+ or.w @0x1234:16,@(0x9abcdef0:32,r2.w) ;6b151234ea409abcdef0 -+ or.w @0x1234:16,@(0x9abcdef0:32,er2.l) ;6b151234fa409abcdef0 -+ or.w @0x1234:16,@0xffff9abc:16 ;6b15123440409abc -+ or.w @0x1234:16,@0x9abcdef0:32 ;6b15123448409abcdef0 -+ -+ or.w @0x12345678:32,@er1 ;6b35123456780140 -+ or.w @0x12345678:32,@(6:2,er1) ;6b35123456783140 -+ or.w @0x12345678:32,@-er1 ;6b3512345678b140 -+ or.w @0x12345678:32,@er1+ ;6b35123456788140 -+ or.w @0x12345678:32,@er1- ;6b3512345678a140 -+ or.w @0x12345678:32,@+er1 ;6b35123456789140 -+ or.w @0x12345678:32,@(0xffff9abc:16,er1) ;6b3512345678c1409abc -+ or.w @0x12345678:32,@(0x9abcdef0:32,er1) ;6b3512345678c9409abcdef0 -+ or.w @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6b3512345678d2409abc -+ or.w @0x12345678:32,@(0xffff9abc:16,r2.w) ;6b3512345678e2409abc -+ or.w @0x12345678:32,@(0xffff9abc:16,er2.l) ;6b3512345678f2409abc -+ or.w @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6b3512345678da409abcdef0 -+ or.w @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6b3512345678ea409abcdef0 -+ or.w @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6b3512345678fa409abcdef0 -+ or.w @0x12345678:32,@0xffff9abc:16 ;6b351234567840409abc -+ or.w @0x12345678:32,@0x9abcdef0:32 ;6b351234567848409abcdef0 -+ -+ or.l #0x12345678:32,er1 ;7a4112345678 -+ or.l #0x1234:16,er1 ;7a491234 -+ or.l #0x12345678:32,@er1 ;010e014812345678 -+ or.l #0x12345678:32,@(0xc:2,er1) ;010e314812345678 -+ or.l #0x12345678:32,@er1+ ;010e814812345678 -+ or.l #0x12345678:32,@-er1 ;010eb14812345678 -+ or.l #0x12345678:32,@+er1 ;010e914812345678 -+ or.l #0x12345678:32,@er1- ;010ea14812345678 -+ or.l #0x12345678:32,@(0xffff9abc:16,er1) ;010ec1489abc12345678 -+ or.l #0x12345678:32,@(0x9abcdef0:32,er1) ;010ec9489abcdef012345678 -+ or.l #0x12345678:32,@(0xffff9abc:16,r2l.b) ;010ed2489abc12345678 -+ or.l #0x12345678:32,@(0xffff9abc:16,r2.w) ;010ee2489abc12345678 -+ or.l #0x12345678:32,@(0xffff9abc:16,er2.l) ;010ef2489abc12345678 -+ or.l #0x12345678:32,@(0x9abcdef0:32,r2l.b) ;010eda489abcdef012345678 -+ or.l #0x12345678:32,@(0x9abcdef0:32,r2.w) ;010eea489abcdef012345678 -+ or.l #0x12345678:32,@(0x9abcdef0:32,er2.l) ;010efa489abcdef012345678 -+ or.l #0x12345678:32,@0xffff9abc:16 ;010e40489abc12345678 -+ or.l #0x12345678:32,@0x9abcdef0:32 ;010e48489abcdef012345678 -+ or.l #0x1234:16,@er1 ;010e01401234 -+ or.l #0x1234:16,@(0xc:2,er1) ;010e31401234 -+ or.l #0x1234:16,@er1+ ;010e81401234 -+ or.l #0x1234:16,@-er1 ;010eb1401234 -+ or.l #0x1234:16,@+er1 ;010e91401234 -+ or.l #0x1234:16,@er1- ;010ea1401234 -+ or.l #0x1234:16,@(0xffff9abc:16,er1) ;010ec1409abc1234 -+ or.l #0x1234:16,@(0x9abcdef0:32,er1) ;010ec9409abcdef01234 -+ or.l #0x1234:16,@(0xffff9abc:16,r2l.b) ;010ed2409abc1234 -+ or.l #0x1234:16,@(0xffff9abc:16,r2.w) ;010ee2409abc1234 -+ or.l #0x1234:16,@(0xffff9abc:16,er2.l) ;010ef2409abc1234 -+ or.l #0x1234:16,@(0x9abcdef0:32,r2l.b) ;010eda409abcdef01234 -+ or.l #0x1234:16,@(0x9abcdef0:32,r2.w) ;010eea409abcdef01234 -+ or.l #0x1234:16,@(0x9abcdef0:32,er2.l) ;010efa409abcdef01234 -+ or.l #0x1234:16,@0xffff9abc:16 ;010e40409abc1234 -+ or.l #0x1234:16,@0x9abcdef0:32 ;010e48409abcdef01234 -+ -+ or.l er3,er1 ;01f06431 -+ -+ or.l er3,@er1 ;01090143 -+ or.l er3,@(0xc:2,er1) ;01093143 -+ or.l er3,@er1+ ;01098143 -+ or.l er3,@-er1 ;0109b143 -+ or.l er3,@+er1 ;01099143 -+ or.l er3,@er1- ;0109a143 -+ or.l er3,@(0x1234:16,er1) ;0109c1431234 -+ or.l er3,@(0x12345678:32,er1) ;0109c94312345678 -+ or.l er3,@(0x1234:16,r2l.b) ;0109d2431234 -+ or.l er3,@(0x1234:16,r2.w) ;0109e2431234 -+ or.l er3,@(0x1234:16,er2.l) ;0109f2431234 -+ or.l er3,@(0x12345678:32,r2l.b) ;0109da4312345678 -+ or.l er3,@(0x12345678:32,r2.w) ;0109ea4312345678 -+ or.l er3,@(0x12345678:32,er2.l) ;0109fa4312345678 -+ or.l er3,@0x1234:16 ;010940431234 -+ or.l er3,@0x12345678:32 ;0109484312345678 -+ -+ or.l @er3,er1 ;010a0341 -+ or.l @(0xc:2,er3),er1 ;010a3341 -+ or.l @er3+,er1 ;010a8341 -+ or.l @-er3,er1 ;010ab341 -+ or.l @+er3,er1 ;010a9341 -+ or.l @er3-,er1 ;010aa341 -+ or.l @(0x1234:16,er1),er1 ;010ac1411234 -+ or.l @(0x12345678:32,er1),er1 ;010ac94112345678 -+ or.l @(0x1234:16,r2l.b),er1 ;010ad2411234 -+ or.l @(0x1234:16,r2.w),er1 ;010ae2411234 -+ or.l @(0x1234:16,er2.l),er1 ;010af2411234 -+ or.l @(0x12345678:32,r2l.b),er1 ;010ada4112345678 -+ or.l @(0x12345678:32,r2.w),er1 ;010aea4112345678 -+ or.l @(0x12345678:32,er2.l),er1 ;010afa4112345678 -+ or.l @0x1234:16,er1 ;010a40411234 -+ or.l @0x12345678:32,er1 ;010a484112345678 -+ -+ or.l @er3,@er1 ;0104693c0140 -+ or.l @er3,@(0xc:2,er1) ;0104693c3140 -+ or.l @er3,@-er1 ;0104693cb140 -+ or.l @er3,@er1+ ;0104693c8140 -+ or.l @er3,@er1- ;0104693ca140 -+ or.l @er3,@+er1 ;0104693c9140 -+ or.l @er3,@(0xffff9abc:16,er1) ;0104693cc1409abc -+ or.l @er3,@(0x9abcdef0:32,er1) ;0104693cc9409abcdef0 -+ or.l @er3,@(0xffff9abc:16,r2l.b) ;0104693cd2409abc -+ or.l @er3,@(0xffff9abc:16,r2.w) ;0104693ce2409abc -+ or.l @er3,@(0xffff9abc:16,er2.l) ;0104693cf2409abc -+ or.l @er3,@(0x9abcdef0:32,r2l.b) ;0104693cda409abcdef0 -+ or.l @er3,@(0x9abcdef0:32,r2.w) ;0104693cea409abcdef0 -+ or.l @er3,@(0x9abcdef0:32,er2.l) ;0104693cfa409abcdef0 -+ or.l @er3,@0xffff9abc:16 ;0104693c40409abc -+ or.l @er3,@0x9abcdef0:32 ;0104693c48409abcdef0 -+ -+ or.l @(0xc:2,er3),@er1 ;0107693c0140 -+ or.l @(0xc:2,er3),@(0xc:2,er1) ;0107693c3140 -+ or.l @(0xc:2,er3),@-er1 ;0107693cb140 -+ or.l @(0xc:2,er3),@er1+ ;0107693c8140 -+ or.l @(0xc:2,er3),@er1- ;0107693ca140 -+ or.l @(0xc:2,er3),@+er1 ;0107693c9140 -+ or.l @(0xc:2,er3),@(0xffff9abc:16,er1) ;0107693cc1409abc -+ or.l @(0xc:2,er3),@(0x9abcdef0:32,er1) ;0107693cc9409abcdef0 -+ or.l @(0xc:2,er3),@(0xffff9abc:16,r2l.b) ;0107693cd2409abc -+ or.l @(0xc:2,er3),@(0xffff9abc:16,r2.w) ;0107693ce2409abc -+ or.l @(0xc:2,er3),@(0xffff9abc:16,er2.l) ;0107693cf2409abc -+ or.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b) ;0107693cda409abcdef0 -+ or.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w) ;0107693cea409abcdef0 -+ or.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l) ;0107693cfa409abcdef0 -+ or.l @(0xc:2,er3),@0xffff9abc:16 ;0107693c40409abc -+ or.l @(0xc:2,er3),@0x9abcdef0:32 ;0107693c48409abcdef0 -+ -+ or.l @-er3,@er1 ;01076d3c0140 -+ or.l @-er3,@(0xc:2,er1) ;01076d3c3140 -+ or.l @-er3,@-er1 ;01076d3cb140 -+ or.l @-er3,@er1+ ;01076d3c8140 -+ or.l @-er3,@er1- ;01076d3ca140 -+ or.l @-er3,@+er1 ;01076d3c9140 -+ or.l @-er3,@(0xffff9abc:16,er1) ;01076d3cc1409abc -+ or.l @-er3,@(0x9abcdef0:32,er1) ;01076d3cc9409abcdef0 -+ or.l @-er3,@(0xffff9abc:16,r2l.b) ;01076d3cd2409abc -+ or.l @-er3,@(0xffff9abc:16,r2.w) ;01076d3ce2409abc -+ or.l @-er3,@(0xffff9abc:16,er2.l) ;01076d3cf2409abc -+ or.l @-er3,@(0x9abcdef0:32,r2l.b) ;01076d3cda409abcdef0 -+ or.l @-er3,@(0x9abcdef0:32,r2.w) ;01076d3cea409abcdef0 -+ or.l @-er3,@(0x9abcdef0:32,er2.l) ;01076d3cfa409abcdef0 -+ or.l @-er3,@0xffff9abc:16 ;01076d3c40409abc -+ or.l @-er3,@0x9abcdef0:32 ;01076d3c48409abcdef0 -+ -+ or.l @er3+,@er1 ;01046d3c0140 -+ or.l @er3+,@(0xc:2,er1) ;01046d3c3140 -+ or.l @er3+,@-er1 ;01046d3cb140 -+ or.l @er3+,@er1+ ;01046d3c8140 -+ or.l @er3+,@er1- ;01046d3ca140 -+ or.l @er3+,@+er1 ;01046d3c9140 -+ or.l @er3+,@(0xffff9abc:16,er1) ;01046d3cc1409abc -+ or.l @er3+,@(0x9abcdef0:32,er1) ;01046d3cc9409abcdef0 -+ or.l @er3+,@(0xffff9abc:16,r2l.b) ;01046d3cd2409abc -+ or.l @er3+,@(0xffff9abc:16,r2.w) ;01046d3ce2409abc -+ or.l @er3+,@(0xffff9abc:16,er2.l) ;01046d3cf2409abc -+ or.l @er3+,@(0x9abcdef0:32,r2l.b) ;01046d3cda409abcdef0 -+ or.l @er3+,@(0x9abcdef0:32,r2.w) ;01046d3cea409abcdef0 -+ or.l @er3+,@(0x9abcdef0:32,er2.l) ;01046d3cfa409abcdef0 -+ or.l @er3+,@0xffff9abc:16 ;01046d3c40409abc -+ or.l @er3+,@0x9abcdef0:32 ;01046d3c48409abcdef0 -+ -+ or.l @er3-,@er1 ;01066d3c0140 -+ or.l @er3-,@(0xc:2,er1) ;01066d3c3140 -+ or.l @er3-,@-er1 ;01066d3cb140 -+ or.l @er3-,@er1+ ;01066d3c8140 -+ or.l @er3-,@er1- ;01066d3ca140 -+ or.l @er3-,@+er1 ;01066d3c9140 -+ or.l @er3-,@(0xffff9abc:16,er1) ;01066d3cc1409abc -+ or.l @er3-,@(0x9abcdef0:32,er1) ;01066d3cc9409abcdef0 -+ or.l @er3-,@(0xffff9abc:16,r2l.b) ;01066d3cd2409abc -+ or.l @er3-,@(0xffff9abc:16,r2.w) ;01066d3ce2409abc -+ or.l @er3-,@(0xffff9abc:16,er2.l) ;01066d3cf2409abc -+ or.l @er3-,@(0x9abcdef0:32,r2l.b) ;01066d3cda409abcdef0 -+ or.l @er3-,@(0x9abcdef0:32,r2.w) ;01066d3cea409abcdef0 -+ or.l @er3-,@(0x9abcdef0:32,er2.l) ;01066d3cfa409abcdef0 -+ or.l @er3-,@0xffff9abc:16 ;01066d3c40409abc -+ or.l @er3-,@0x9abcdef0:32 ;01066d3c48409abcdef0 -+ -+ or.l @+er3,@er1 ;01056d3c0140 -+ or.l @+er3,@(0xc:2,er1) ;01056d3c3140 -+ or.l @+er3,@-er1 ;01056d3cb140 -+ or.l @+er3,@er1+ ;01056d3c8140 -+ or.l @+er3,@er1- ;01056d3ca140 -+ or.l @+er3,@+er1 ;01056d3c9140 -+ or.l @+er3,@(0xffff9abc:16,er1) ;01056d3cc1409abc -+ or.l @+er3,@(0x9abcdef0:32,er1) ;01056d3cc9409abcdef0 -+ or.l @+er3,@(0xffff9abc:16,r2l.b) ;01056d3cd2409abc -+ or.l @+er3,@(0xffff9abc:16,r2.w) ;01056d3ce2409abc -+ or.l @+er3,@(0xffff9abc:16,er2.l) ;01056d3cf2409abc -+ or.l @+er3,@(0x9abcdef0:32,r2l.b) ;01056d3cda409abcdef0 -+ or.l @+er3,@(0x9abcdef0:32,r2.w) ;01056d3cea409abcdef0 -+ or.l @+er3,@(0x9abcdef0:32,er2.l) ;01056d3cfa409abcdef0 -+ or.l @+er3,@0xffff9abc:16 ;01056d3c40409abc -+ or.l @+er3,@0x9abcdef0:32 ;01056d3c48409abcdef0 -+ -+ or.l @(0x1234:16,er3),@er1 ;01046f3c12340140 -+ or.l @(0x1234:16,er3),@(0xc:2,er1) ;01046f3c12343140 -+ or.l @(0x1234:16,er3),@-er1 ;01046f3c1234b140 -+ or.l @(0x1234:16,er3),@er1+ ;01046f3c12348140 -+ or.l @(0x1234:16,er3),@er1- ;01046f3c1234a140 -+ or.l @(0x1234:16,er3),@+er1 ;01046f3c12349140 -+ or.l @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01046f3c1234c1409abc -+ or.l @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01046f3c1234c9409abcdef0 -+ or.l @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01046f3c1234d2409abc -+ or.l @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01046f3c1234e2409abc -+ or.l @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01046f3c1234f2409abc -+ or.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01046f3c1234da409abcdef0 -+ or.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01046f3c1234ea409abcdef0 -+ or.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01046f3c1234fa409abcdef0 -+ or.l @(0x1234:16,er3),@0xffff9abc:16 ;01046f3c123440409abc -+ or.l @(0x1234:16,er3),@0x9abcdef0:32 ;01046f3c123448409abcdef0 -+ -+ or.l @(0x12345678:32,er3),@er1 ;78b46b2c123456780140 -+ or.l @(0x12345678:32,er3),@(0xc:2,er1) ;78b46b2c123456783140 -+ or.l @(0x12345678:32,er3),@-er1 ;78b46b2c12345678b140 -+ or.l @(0x12345678:32,er3),@er1+ ;78b46b2c123456788140 -+ or.l @(0x12345678:32,er3),@er1- ;78b46b2c12345678a140 -+ or.l @(0x12345678:32,er3),@+er1 ;78b46b2c123456789140 -+ or.l @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78b46b2c12345678c1409abc -+ or.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78b46b2c12345678c9409abcdef0 -+ or.l @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78b46b2c12345678d2409abc -+ or.l @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78b46b2c12345678e2409abc -+ or.l @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78b46b2c12345678f2409abc -+ or.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78b46b2c12345678da409abcdef0 -+ or.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78b46b2c12345678ea409abcdef0 -+ or.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78b46b2c12345678fa409abcdef0 -+ or.l @(0x12345678:32,er3),@0xffff9abc:16 ;78b46b2c1234567840409abc -+ or.l @(0x12345678:32,er3),@0x9abcdef0:32 ;78b46b2c1234567848409abcdef0 -+ -+ or.l @(0x1234:16,r3l.b),@er1 ;01056f3c12340140 -+ or.l @(0x1234:16,r3l.b),@(0xc:2,er1) ;01056f3c12343140 -+ or.l @(0x1234:16,r3l.b),@-er1 ;01056f3c1234b140 -+ or.l @(0x1234:16,r3l.b),@er1+ ;01056f3c12348140 -+ or.l @(0x1234:16,r3l.b),@er1- ;01056f3c1234a140 -+ or.l @(0x1234:16,r3l.b),@+er1 ;01056f3c12349140 -+ or.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01056f3c1234c1409abc -+ or.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01056f3c1234c9409abcdef0 -+ or.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01056f3c1234d2409abc -+ or.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01056f3c1234e2409abc -+ or.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01056f3c1234f2409abc -+ or.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01056f3c1234da409abcdef0 -+ or.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01056f3c1234ea409abcdef0 -+ or.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01056f3c1234fa409abcdef0 -+ or.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;01056f3c123440409abc -+ or.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01056f3c123448409abcdef0 -+ -+ or.l @(0x1234:16,r3.w),@er1 ;01066f3c12340140 -+ or.l @(0x1234:16,r3.w),@(0xc:2,er1) ;01066f3c12343140 -+ or.l @(0x1234:16,r3.w),@-er1 ;01066f3c1234b140 -+ or.l @(0x1234:16,r3.w),@er1+ ;01066f3c12348140 -+ or.l @(0x1234:16,r3.w),@er1- ;01066f3c1234a140 -+ or.l @(0x1234:16,r3.w),@+er1 ;01066f3c12349140 -+ or.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01066f3c1234c1409abc -+ or.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01066f3c1234c9409abcdef0 -+ or.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01066f3c1234d2409abc -+ or.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01066f3c1234e2409abc -+ or.l @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01066f3c1234f2409abc -+ or.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01066f3c1234da409abcdef0 -+ or.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01066f3c1234ea409abcdef0 -+ or.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01066f3c1234fa409abcdef0 -+ or.l @(0x1234:16,r3.w),@0xffff9abc:16 ;01066f3c123440409abc -+ or.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;01066f3c123448409abcdef0 -+ -+ or.l @(0x1234:16,er3.l),@er1 ;01076f3c12340140 -+ or.l @(0x1234:16,er3.l),@(0xc:2,er1) ;01076f3c12343140 -+ or.l @(0x1234:16,er3.l),@-er1 ;01076f3c1234b140 -+ or.l @(0x1234:16,er3.l),@er1+ ;01076f3c12348140 -+ or.l @(0x1234:16,er3.l),@er1- ;01076f3c1234a140 -+ or.l @(0x1234:16,er3.l),@+er1 ;01076f3c12349140 -+ or.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01076f3c1234c1409abc -+ or.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01076f3c1234c9409abcdef0 -+ or.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01076f3c1234d2409abc -+ or.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01076f3c1234e2409abc -+ or.l @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01076f3c1234f2409abc -+ or.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01076f3c1234da409abcdef0 -+ or.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01076f3c1234ea409abcdef0 -+ or.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01076f3c1234fa409abcdef0 -+ or.l @(0x1234:16,er3.l),@0xffff9abc:16 ;01076f3c123440409abc -+ or.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;01076f3c123448409abcdef0 -+ -+ or.l @(0x12345678:32,r3l.b),@er1 ;78b56b2c123456780140 -+ or.l @(0x12345678:32,r3l.b),@(0xc:2,er1) ;78b56b2c123456783140 -+ or.l @(0x12345678:32,r3l.b),@-er1 ;78b56b2c12345678b140 -+ or.l @(0x12345678:32,r3l.b),@er1+ ;78b56b2c123456788140 -+ or.l @(0x12345678:32,r3l.b),@er1- ;78b56b2c12345678a140 -+ or.l @(0x12345678:32,r3l.b),@+er1 ;78b56b2c123456789140 -+ or.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78b56b2c12345678c1409abc -+ or.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78b56b2c12345678c9409abcdef0 -+ or.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78b56b2c12345678d2409abc -+ or.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78b56b2c12345678e2409abc -+ or.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78b56b2c12345678f2409abc -+ or.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78b56b2c12345678da409abcdef0 -+ or.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78b56b2c12345678ea409abcdef0 -+ or.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78b56b2c12345678fa409abcdef0 -+ or.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78b56b2c1234567840409abc -+ or.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78b56b2c1234567848409abcdef0 -+ -+ or.l @(0x12345678:32,r3.w),@er1 ;78b66b2c123456780140 -+ or.l @(0x12345678:32,r3.w),@(0xc:2,er1) ;78b66b2c123456783140 -+ or.l @(0x12345678:32,r3.w),@-er1 ;78b66b2c12345678b140 -+ or.l @(0x12345678:32,r3.w),@er1+ ;78b66b2c123456788140 -+ or.l @(0x12345678:32,r3.w),@er1- ;78b66b2c12345678a140 -+ or.l @(0x12345678:32,r3.w),@+er1 ;78b66b2c123456789140 -+ or.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78b66b2c12345678c1409abc -+ or.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78b66b2c12345678c9409abcdef0 -+ or.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78b66b2c12345678d2409abc -+ or.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78b66b2c12345678e2409abc -+ or.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78b66b2c12345678f2409abc -+ or.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78b66b2c12345678da409abcdef0 -+ or.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78b66b2c12345678ea409abcdef0 -+ or.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78b66b2c12345678fa409abcdef0 -+ or.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;78b66b2c1234567840409abc -+ or.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78b66b2c1234567848409abcdef0 -+ -+ or.l @(0x12345678:32,er3.l),@er1 ;78b76b2c123456780140 -+ or.l @(0x12345678:32,er3.l),@(0xc:2,er1) ;78b76b2c123456783140 -+ or.l @(0x12345678:32,er3.l),@-er1 ;78b76b2c12345678b140 -+ or.l @(0x12345678:32,er3.l),@er1+ ;78b76b2c123456788140 -+ or.l @(0x12345678:32,er3.l),@er1- ;78b76b2c12345678a140 -+ or.l @(0x12345678:32,er3.l),@+er1 ;78b76b2c123456789140 -+ or.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78b76b2c12345678c1409abc -+ or.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78b76b2c12345678c9409abcdef0 -+ or.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78b76b2c12345678d2409abc -+ or.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78b76b2c12345678e2409abc -+ or.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78b76b2c12345678f2409abc -+ or.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78b76b2c12345678da409abcdef0 -+ or.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78b76b2c12345678ea409abcdef0 -+ or.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78b76b2c12345678fa409abcdef0 -+ or.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;78b76b2c1234567840409abc -+ or.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78b76b2c1234567848409abcdef0 -+ -+ or.l @0x1234:16,@er1 ;01046b0c12340140 -+ or.l @0x1234:16,@(0xc:2,er1) ;01046b0c12343140 -+ or.l @0x1234:16,@-er1 ;01046b0c1234b140 -+ or.l @0x1234:16,@er1+ ;01046b0c12348140 -+ or.l @0x1234:16,@er1- ;01046b0c1234a140 -+ or.l @0x1234:16,@+er1 ;01046b0c12349140 -+ or.l @0x1234:16,@(0xffff9abc:16,er1) ;01046b0c1234c1409abc -+ or.l @0x1234:16,@(0x9abcdef0:32,er1) ;01046b0c1234c9409abcdef0 -+ or.l @0x1234:16,@(0xffff9abc:16,r2l.b) ;01046b0c1234d2409abc -+ or.l @0x1234:16,@(0xffff9abc:16,r2.w) ;01046b0c1234e2409abc -+ or.l @0x1234:16,@(0xffff9abc:16,er2.l) ;01046b0c1234f2409abc -+ or.l @0x1234:16,@(0x9abcdef0:32,r2l.b) ;01046b0c1234da409abcdef0 -+ or.l @0x1234:16,@(0x9abcdef0:32,r2.w) ;01046b0c1234ea409abcdef0 -+ or.l @0x1234:16,@(0x9abcdef0:32,er2.l) ;01046b0c1234fa409abcdef0 -+ or.l @0x1234:16,@0xffff9abc:16 ;01046b0c123440409abc -+ or.l @0x1234:16,@0x9abcdef0:32 ;01046b0c123448409abcdef0 -+ -+ or.l @0x12345678:32,@er1 ;01046b2c123456780140 -+ or.l @0x12345678:32,@(0xc:2,er1) ;01046b2c123456783140 -+ or.l @0x12345678:32,@-er1 ;01046b2c12345678b140 -+ or.l @0x12345678:32,@er1+ ;01046b2c123456788140 -+ or.l @0x12345678:32,@er1- ;01046b2c12345678a140 -+ or.l @0x12345678:32,@+er1 ;01046b2c123456789140 -+ or.l @0x12345678:32,@(0xffff9abc:16,er1) ;01046b2c12345678c1409abc -+ or.l @0x12345678:32,@(0x9abcdef0:32,er1) ;01046b2c12345678c9409abcdef0 -+ or.l @0x12345678:32,@(0xffff9abc:16,r2l.b) ;01046b2c12345678d2409abc -+ or.l @0x12345678:32,@(0xffff9abc:16,r2.w) ;01046b2c12345678e2409abc -+ or.l @0x12345678:32,@(0xffff9abc:16,er2.l) ;01046b2c12345678f2409abc -+ or.l @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;01046b2c12345678da409abcdef0 -+ or.l @0x12345678:32,@(0x9abcdef0:32,r2.w) ;01046b2c12345678ea409abcdef0 -+ or.l @0x12345678:32,@(0x9abcdef0:32,er2.l) ;01046b2c12345678fa409abcdef0 -+ or.l @0x12345678:32,@0xffff9abc:16 ;01046b2c1234567840409abc -+ or.l @0x12345678:32,@0x9abcdef0:32 ;01046b2c1234567848409abcdef0 -+ -+ .end ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;log_1 ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ .h8300sx ++ .text ++_start: ++ or.b #0x12:8,r1h ;c112 ++ or.b #0x12:8,@er1 ;7d10c012 ++ or.b #0x12:8,@(0x3:2,er1) ;01776818c012 ++ or.b #0x12:8,@er1+ ;01746c18c012 ++ or.b #0x12:8,@-er1 ;01776c18c012 ++ or.b #0x12:8,@+er1 ;01756c18c012 ++ or.b #0x12:8,@er1- ;01766c18c012 ++ or.b #0x12:8,@(0x1234:16,er1) ;01746e181234c012 ++ or.b #0x12:8,@(0x12345678:32,er1) ;78146a2812345678c012 ++ or.b #0x12:8,@(0x1234:16,r2l.b) ;01756e281234c012 ++ or.b #0x12:8,@(0x1234:16,r2.w) ;01766e281234c012 ++ or.b #0x12:8,@(0x1234:16,er2.l) ;01776e281234c012 ++ or.b #0x12:8,@(0x12345678:32,r2l.b) ;78256a2812345678c012 ++ or.b #0x12:8,@(0x12345678:32,r2.w) ;78266a2812345678c012 ++ or.b #0x12:8,@(0x12345678:32,er2.l) ;78276a2812345678c012 ++ or.b #0x12:8,@0xffffff12:8 ;7f12c012 ++ or.b #0x12:8,@0x1234:16 ;6a181234c012 ++ or.b #0x12:8,@0x12345678:32 ;6a3812345678c012 ++ ++ or.b r3h,r1h ;1431 ++ ++ or.b r3h,@er1 ;7d101430 ++ or.b r3h,@(0x3:2,er1) ;01793143 ++ or.b r3h,@er1+ ;01798143 ++ or.b r3h,@-er1 ;0179b143 ++ or.b r3h,@+er1 ;01799143 ++ or.b r3h,@er1- ;0179a143 ++ or.b r3h,@(0x1234:16,er1) ;0179c1431234 ++ or.b r3h,@(0x12345678:32,er1) ;0179c94312345678 ++ or.b r3h,@(0x1234:16,r2l.b) ;0179d2431234 ++ or.b r3h,@(0x1234:16,r2.w) ;0179e2431234 ++ or.b r3h,@(0x1234:16,er2.l) ;0179f2431234 ++ or.b r3h,@(0x12345678:32,r2l.b) ;0179da4312345678 ++ or.b r3h,@(0x12345678:32,r2.w) ;0179ea4312345678 ++ or.b r3h,@(0x12345678:32,er2.l) ;0179fa4312345678 ++ or.b r3h,@0xffffff12:8 ;7f121430 ++ or.b r3h,@0x1234:16 ;6a1812341430 ++ or.b r3h,@0x12345678:32 ;6a38123456781430 ++ ++ or.b @er3,r1h ;7c301401 ++ or.b @(0x3:2,er3),r1h ;017a3341 ++ or.b @er3+,r1h ;017a8341 ++ or.b @-er3,r1h ;017ab341 ++ or.b @+er3,r1h ;017a9341 ++ or.b @er3-,r1h ;017aa341 ++ or.b @(0x1234:16,er1),r1h ;017ac1411234 ++ or.b @(0x12345678:32,er1),r1h ;017ac94112345678 ++ or.b @(0x1234:16,r2l.b),r1h ;017ad2411234 ++ or.b @(0x1234:16,r2.w),r1h ;017ae2411234 ++ or.b @(0x1234:16,er2.l),r1h ;017af2411234 ++ or.b @(0x12345678:32,r2l.b),r1h ;017ada4112345678 ++ or.b @(0x12345678:32,r2.w),r1h ;017aea4112345678 ++ or.b @(0x12345678:32,er2.l),r1h ;017afa4112345678 ++ or.b @0xffffff12:8,r1h ;7e121401 ++ or.b @0x1234:16,r1h ;6a1012341401 ++ or.b @0x12345678:32,r1h ;6a30123456781401 ++ ++ or.b @er3,@er1 ;7c350140 ++ or.b @er3,@(3:2,er1) ;7c353140 ++ or.b @er3,@-er1 ;7c35b140 ++ or.b @er3,@er1+ ;7c358140 ++ or.b @er3,@er1- ;7c35a140 ++ or.b @er3,@+er1 ;7c359140 ++ or.b @er3,@(0xffff9abc:16,er1) ;7c35c1409abc ++ or.b @er3,@(0x9abcdef0:32,er1) ;7c35c9409abcdef0 ++ or.b @er3,@(0xffff9abc:16,r2l.b) ;7c35d2409abc ++ or.b @er3,@(0xffff9abc:16,r2.w) ;7c35e2409abc ++ or.b @er3,@(0xffff9abc:16,er2.l) ;7c35f2409abc ++ or.b @er3,@(0x9abcdef0:32,r2l.b) ;7c35da409abcdef0 ++ or.b @er3,@(0x9abcdef0:32,r2.w) ;7c35ea409abcdef0 ++ or.b @er3,@(0x9abcdef0:32,er2.l) ;7c35fa409abcdef0 ++ or.b @er3,@0xffff9abc:16 ;7c3540409abc ++ or.b @er3,@0x9abcdef0:32 ;7c3548409abcdef0 ++ ++ or.b @-er3,@er1 ;01776c3c0140 ++ or.b @-er3,@(3:2,er1) ;01776c3c3140 ++ or.b @-er3,@-er1 ;01776c3cb140 ++ or.b @-er3,@er1+ ;01776c3c8140 ++ or.b @-er3,@er1- ;01776c3ca140 ++ or.b @-er3,@+er1 ;01776c3c9140 ++ or.b @-er3,@(0xffff9abc:16,er1) ;01776c3cc1409abc ++ or.b @-er3,@(0x9abcdef0:32,er1) ;01776c3cc9409abcdef0 ++ or.b @-er3,@(0xffff9abc:16,r2l.b) ;01776c3cd2409abc ++ or.b @-er3,@(0xffff9abc:16,r2.w) ;01776c3ce2409abc ++ or.b @-er3,@(0xffff9abc:16,er2.l) ;01776c3cf2409abc ++ or.b @-er3,@(0x9abcdef0:32,r2l.b) ;01776c3cda409abcdef0 ++ or.b @-er3,@(0x9abcdef0:32,r2.w) ;01776c3cea409abcdef0 ++ or.b @-er3,@(0x9abcdef0:32,er2.l) ;01776c3cfa409abcdef0 ++ or.b @-er3,@0xffff9abc:16 ;01776c3c40409abc ++ or.b @-er3,@0x9abcdef0:32 ;01776c3c48409abcdef0 ++ ++ or.b @er3+,@er1 ;01746c3c0140 ++ or.b @er3+,@(3:2,er1) ;01746c3c3140 ++ or.b @er3+,@-er1 ;01746c3cb140 ++ or.b @er3+,@er1+ ;01746c3c8140 ++ or.b @er3+,@er1- ;01746c3ca140 ++ or.b @er3+,@+er1 ;01746c3c9140 ++ or.b @er3+,@(0xffff9abc:16,er1) ;01746c3cc1409abc ++ or.b @er3+,@(0x9abcdef0:32,er1) ;01746c3cc9409abcdef0 ++ or.b @er3+,@(0xffff9abc:16,r2l.b) ;01746c3cd2409abc ++ or.b @er3+,@(0xffff9abc:16,r2.w) ;01746c3ce2409abc ++ or.b @er3+,@(0xffff9abc:16,er2.l) ;01746c3cf2409abc ++ or.b @er3+,@(0x9abcdef0:32,r2l.b) ;01746c3cda409abcdef0 ++ or.b @er3+,@(0x9abcdef0:32,r2.w) ;01746c3cea409abcdef0 ++ or.b @er3+,@(0x9abcdef0:32,er2.l) ;01746c3cfa409abcdef0 ++ or.b @er3+,@0xffff9abc:16 ;01746c3c40409abc ++ or.b @er3+,@0x9abcdef0:32 ;01746c3c48409abcdef0 ++ ++ or.b @er3-,@er1 ;01766c3c0140 ++ or.b @er3-,@(3:2,er1) ;01766c3c3140 ++ or.b @er3-,@-er1 ;01766c3cb140 ++ or.b @er3-,@er1+ ;01766c3c8140 ++ or.b @er3-,@er1- ;01766c3ca140 ++ or.b @er3-,@+er1 ;01766c3c9140 ++ or.b @er3-,@(0xffff9abc:16,er1) ;01766c3cc1409abc ++ or.b @er3-,@(0x9abcdef0:32,er1) ;01766c3cc9409abcdef0 ++ or.b @er3-,@(0xffff9abc:16,r2l.b) ;01766c3cd2409abc ++ or.b @er3-,@(0xffff9abc:16,r2.w) ;01766c3ce2409abc ++ or.b @er3-,@(0xffff9abc:16,er2.l) ;01766c3cf2409abc ++ or.b @er3-,@(0x9abcdef0:32,r2l.b) ;01766c3cda409abcdef0 ++ or.b @er3-,@(0x9abcdef0:32,r2.w) ;01766c3cea409abcdef0 ++ or.b @er3-,@(0x9abcdef0:32,er2.l) ;01766c3cfa409abcdef0 ++ or.b @er3-,@0xffff9abc:16 ;01766c3c40409abc ++ or.b @er3-,@0x9abcdef0:32 ;01766c3c48409abcdef0 ++ ++ or.b @+er3,@er1 ;01756c3c0140 ++ or.b @+er3,@(3:2,er1) ;01756c3c3140 ++ or.b @+er3,@-er1 ;01756c3cb140 ++ or.b @+er3,@er1+ ;01756c3c8140 ++ or.b @+er3,@er1- ;01756c3ca140 ++ or.b @+er3,@+er1 ;01756c3c9140 ++ or.b @+er3,@(0xffff9abc:16,er1) ;01756c3cc1409abc ++ or.b @+er3,@(0x9abcdef0:32,er1) ;01756c3cc9409abcdef0 ++ or.b @+er3,@(0xffff9abc:16,r2l.b) ;01756c3cd2409abc ++ or.b @+er3,@(0xffff9abc:16,r2.w) ;01756c3ce2409abc ++ or.b @+er3,@(0xffff9abc:16,er2.l) ;01756c3cf2409abc ++ or.b @+er3,@(0x9abcdef0:32,r2l.b) ;01756c3cda409abcdef0 ++ or.b @+er3,@(0x9abcdef0:32,r2.w) ;01756c3cea409abcdef0 ++ or.b @+er3,@(0x9abcdef0:32,er2.l) ;01756c3cfa409abcdef0 ++ or.b @+er3,@0xffff9abc:16 ;01756c3c40409abc ++ or.b @+er3,@0x9abcdef0:32 ;01756c3c48409abcdef0 ++ ++ or.b @(0x1234:16,er3),@er1 ;01746e3c12340140 ++ or.b @(0x1234:16,er3),@(3:2,er1) ;01746e3c12343140 ++ or.b @(0x1234:16,er3),@-er1 ;01746e3c1234b140 ++ or.b @(0x1234:16,er3),@er1+ ;01746e3c12348140 ++ or.b @(0x1234:16,er3),@er1- ;01746e3c1234a140 ++ or.b @(0x1234:16,er3),@+er1 ;01746e3c12349140 ++ or.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01746e3c1234c1409abc ++ or.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01746e3c1234c9409abcdef0 ++ or.b @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01746e3c1234d2409abc ++ or.b @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01746e3c1234e2409abc ++ or.b @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01746e3c1234f2409abc ++ or.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01746e3c1234da409abcdef0 ++ or.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01746e3c1234ea409abcdef0 ++ or.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01746e3c1234fa409abcdef0 ++ or.b @(0x1234:16,er3),@0xffff9abc:16 ;01746e3c123440409abc ++ or.b @(0x1234:16,er3),@0x9abcdef0:32 ;01746e3c123448409abcdef0 ++ ++ or.b @(0x12345678:32,er3),@er1 ;78346a2c123456780140 ++ or.b @(0x12345678:32,er3),@(3:2,er1) ;78346a2c123456783140 ++ or.b @(0x12345678:32,er3),@-er1 ;78346a2c12345678b140 ++ or.b @(0x12345678:32,er3),@er1+ ;78346a2c123456788140 ++ or.b @(0x12345678:32,er3),@er1- ;78346a2c12345678a140 ++ or.b @(0x12345678:32,er3),@+er1 ;78346a2c123456789140 ++ or.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346a2c12345678c1409abc ++ or.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346a2c12345678c9409abcdef0 ++ or.b @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346a2c12345678d2409abc ++ or.b @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346a2c12345678e2409abc ++ or.b @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346a2c12345678f2409abc ++ or.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346a2c12345678da409abcdef0 ++ or.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346a2c12345678ea409abcdef0 ++ or.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346a2c12345678fa409abcdef0 ++ or.b @(0x12345678:32,er3),@0xffff9abc:16 ;78346a2c1234567840409abc ++ or.b @(0x12345678:32,er3),@0x9abcdef0:32 ;78346a2c1234567848409abcdef0 ++ ++ or.b @(0x1234:16,r3l.b),@er1 ;01756e3c12340140 ++ or.b @(0x1234:16,r3l.b),@(3:2,er1) ;01756e3c12343140 ++ or.b @(0x1234:16,r3l.b),@-er1 ;01756e3c1234b140 ++ or.b @(0x1234:16,r3l.b),@er1+ ;01756e3c12348140 ++ or.b @(0x1234:16,r3l.b),@er1- ;01756e3c1234a140 ++ or.b @(0x1234:16,r3l.b),@+er1 ;01756e3c12349140 ++ or.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01756e3c1234c1409abc ++ or.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01756e3c1234c9409abcdef0 ++ or.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01756e3c1234d2409abc ++ or.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01756e3c1234e2409abc ++ or.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01756e3c1234f2409abc ++ or.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01756e3c1234da409abcdef0 ++ or.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01756e3c1234ea409abcdef0 ++ or.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01756e3c1234fa409abcdef0 ++ or.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;01756e3c123440409abc ++ or.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01756e3c123448409abcdef0 ++ ++ or.b @(0x1234:16,r3.w),@er1 ;01766e3c12340140 ++ or.b @(0x1234:16,r3.w),@(3:2,er1) ;01766e3c12343140 ++ or.b @(0x1234:16,r3.w),@-er1 ;01766e3c1234b140 ++ or.b @(0x1234:16,r3.w),@er1+ ;01766e3c12348140 ++ or.b @(0x1234:16,r3.w),@er1- ;01766e3c1234a140 ++ or.b @(0x1234:16,r3.w),@+er1 ;01766e3c12349140 ++ or.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01766e3c1234c1409abc ++ or.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01766e3c1234c9409abcdef0 ++ or.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01766e3c1234d2409abc ++ or.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01766e3c1234e2409abc ++ or.b @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01766e3c1234f2409abc ++ or.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01766e3c1234da409abcdef0 ++ or.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01766e3c1234ea409abcdef0 ++ or.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01766e3c1234fa409abcdef0 ++ or.b @(0x1234:16,r3.w),@0xffff9abc:16 ;01766e3c123440409abc ++ or.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;01766e3c123448409abcdef0 ++ ++ or.b @(0x1234:16,er3.l),@er1 ;01776e3c12340140 ++ or.b @(0x1234:16,er3.l),@(3:2,er1) ;01776e3c12343140 ++ or.b @(0x1234:16,er3.l),@-er1 ;01776e3c1234b140 ++ or.b @(0x1234:16,er3.l),@er1+ ;01776e3c12348140 ++ or.b @(0x1234:16,er3.l),@er1- ;01776e3c1234a140 ++ or.b @(0x1234:16,er3.l),@+er1 ;01776e3c12349140 ++ or.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01776e3c1234c1409abc ++ or.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01776e3c1234c9409abcdef0 ++ or.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01776e3c1234d2409abc ++ or.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01776e3c1234e2409abc ++ or.b @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01776e3c1234f2409abc ++ or.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01776e3c1234da409abcdef0 ++ or.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01776e3c1234ea409abcdef0 ++ or.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01776e3c1234fa409abcdef0 ++ or.b @(0x1234:16,er3.l),@0xffff9abc:16 ;01776e3c123440409abc ++ or.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;01776e3c123448409abcdef0 ++ ++ or.b @(0x12345678:32,r3l.b),@er1 ;78356a2c123456780140 ++ or.b @(0x12345678:32,r3l.b),@(3:2,er1) ;78356a2c123456783140 ++ or.b @(0x12345678:32,r3l.b),@-er1 ;78356a2c12345678b140 ++ or.b @(0x12345678:32,r3l.b),@er1+ ;78356a2c123456788140 ++ or.b @(0x12345678:32,r3l.b),@er1- ;78356a2c12345678a140 ++ or.b @(0x12345678:32,r3l.b),@+er1 ;78356a2c123456789140 ++ or.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356a2c12345678c1409abc ++ or.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356a2c12345678c9409abcdef0 ++ or.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356a2c12345678d2409abc ++ or.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356a2c12345678e2409abc ++ or.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356a2c12345678f2409abc ++ or.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356a2c12345678da409abcdef0 ++ or.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356a2c12345678ea409abcdef0 ++ or.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356a2c12345678fa409abcdef0 ++ or.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356a2c1234567840409abc ++ or.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356a2c1234567848409abcdef0 ++ ++ or.b @(0x12345678:32,r3.w),@er1 ;78366a2c123456780140 ++ or.b @(0x12345678:32,r3.w),@(3:2,er1) ;78366a2c123456783140 ++ or.b @(0x12345678:32,r3.w),@-er1 ;78366a2c12345678b140 ++ or.b @(0x12345678:32,r3.w),@er1+ ;78366a2c123456788140 ++ or.b @(0x12345678:32,r3.w),@er1- ;78366a2c12345678a140 ++ or.b @(0x12345678:32,r3.w),@+er1 ;78366a2c123456789140 ++ or.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366a2c12345678c1409abc ++ or.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366a2c12345678c9409abcdef0 ++ or.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366a2c12345678d2409abc ++ or.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366a2c12345678e2409abc ++ or.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366a2c12345678f2409abc ++ or.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366a2c12345678da409abcdef0 ++ or.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366a2c12345678ea409abcdef0 ++ or.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366a2c12345678fa409abcdef0 ++ or.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366a2c1234567840409abc ++ or.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366a2c1234567848409abcdef0 ++ ++ or.b @(0x12345678:32,er3.l),@er1 ;78376a2c123456780140 ++ or.b @(0x12345678:32,er3.l),@(3:2,er1) ;78376a2c123456783140 ++ or.b @(0x12345678:32,er3.l),@-er1 ;78376a2c12345678b140 ++ or.b @(0x12345678:32,er3.l),@er1+ ;78376a2c123456788140 ++ or.b @(0x12345678:32,er3.l),@er1- ;78376a2c12345678a140 ++ or.b @(0x12345678:32,er3.l),@+er1 ;78376a2c123456789140 ++ or.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376a2c12345678c1409abc ++ or.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376a2c12345678c9409abcdef0 ++ or.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376a2c12345678d2409abc ++ or.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376a2c12345678e2409abc ++ or.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376a2c12345678f2409abc ++ or.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376a2c12345678da409abcdef0 ++ or.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376a2c12345678ea409abcdef0 ++ or.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376a2c12345678fa409abcdef0 ++ or.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376a2c1234567840409abc ++ or.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376a2c1234567848409abcdef0 ++ ++ or.b @0x1234:16,@er1 ;6a1512340140 ++ or.b @0x1234:16,@(3:2,er1) ;6a1512343140 ++ or.b @0x1234:16,@-er1 ;6a151234b140 ++ or.b @0x1234:16,@er1+ ;6a1512348140 ++ or.b @0x1234:16,@er1- ;6a151234a140 ++ or.b @0x1234:16,@+er1 ;6a1512349140 ++ or.b @0x1234:16,@(0xffff9abc:16,er1) ;6a151234c1409abc ++ or.b @0x1234:16,@(0x9abcdef0:32,er1) ;6a151234c9409abcdef0 ++ or.b @0x1234:16,@(0xffff9abc:16,r2l.b) ;6a151234d2409abc ++ or.b @0x1234:16,@(0xffff9abc:16,r2.w) ;6a151234e2409abc ++ or.b @0x1234:16,@(0xffff9abc:16,er2.l) ;6a151234f2409abc ++ or.b @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6a151234da409abcdef0 ++ or.b @0x1234:16,@(0x9abcdef0:32,r2.w) ;6a151234ea409abcdef0 ++ or.b @0x1234:16,@(0x9abcdef0:32,er2.l) ;6a151234fa409abcdef0 ++ or.b @0x1234:16,@0xffff9abc:16 ;6a15123440409abc ++ or.b @0x1234:16,@0x9abcdef0:32 ;6a15123448409abcdef0 ++ ++ or.b @0x12345678:32,@er1 ;6a35123456780140 ++ or.b @0x12345678:32,@(3:2,er1) ;6a35123456783140 ++ or.b @0x12345678:32,@-er1 ;6a3512345678b140 ++ or.b @0x12345678:32,@er1+ ;6a35123456788140 ++ or.b @0x12345678:32,@er1- ;6a3512345678a140 ++ or.b @0x12345678:32,@+er1 ;6a35123456789140 ++ or.b @0x12345678:32,@(0xffff9abc:16,er1) ;6a3512345678c1409abc ++ or.b @0x12345678:32,@(0x9abcdef0:32,er1) ;6a3512345678c9409abcdef0 ++ or.b @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6a3512345678d2409abc ++ or.b @0x12345678:32,@(0xffff9abc:16,r2.w) ;6a3512345678e2409abc ++ or.b @0x12345678:32,@(0xffff9abc:16,er2.l) ;6a3512345678f2409abc ++ or.b @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6a3512345678da409abcdef0 ++ or.b @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6a3512345678ea409abcdef0 ++ or.b @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6a3512345678fa409abcdef0 ++ or.b @0x12345678:32,@0xffff9abc:16 ;6a351234567840409abc ++ or.b @0x12345678:32,@0x9abcdef0:32 ;6a351234567848409abcdef0 ++ ++ or.w #0x1234:16,r1 ;79411234 ++ or.w #0x1234:16,@er1 ;015e01401234 ++ or.w #0x1234:16,@(0x6:2,er1) ;015e31401234 ++ or.w #0x1234:16,@er1+ ;015e81401234 ++ or.w #0x1234:16,@-er1 ;015eb1401234 ++ or.w #0x1234:16,@+er1 ;015e91401234 ++ or.w #0x1234:16,@er1- ;015ea1401234 ++ or.w #0x1234:16,@(0xffff9abc:16,er1) ;015ec1409abc1234 ++ or.w #0x1234:16,@(0x9abcdef0:32,er1) ;015ec9409abcdef01234 ++ or.w #0x1234:16,@(0xffff9abc:16,r2l.b) ;015ed2409abc1234 ++ or.w #0x1234:16,@(0xffff9abc:16,r2.w) ;015ee2409abc1234 ++ or.w #0x1234:16,@(0xffff9abc:16,er2.l) ;015ef2409abc1234 ++ or.w #0x1234:16,@(0x9abcdef0:32,r2l.b) ;015eda409abcdef01234 ++ or.w #0x1234:16,@(0x9abcdef0:32,r2.w) ;015eea409abcdef01234 ++ or.w #0x1234:16,@(0x9abcdef0:32,er2.l) ;015efa409abcdef01234 ++ or.w #0x1234:16,@0xffff9abc:16 ;015e40409abc1234 ++ or.w #0x1234:16,@0x9abcdef0:32 ;015e48409abcdef01234 ++ ++ or.w r3,r1 ;6431 ++ ++ or.w r3,@er1 ;7d906430 ++ or.w r3,@(0x6:2,er1) ;01593143 ++ or.w r3,@er1+ ;01598143 ++ or.w r3,@-er1 ;0159b143 ++ or.w r3,@+er1 ;01599143 ++ or.w r3,@er1- ;0159a143 ++ or.w r3,@(0x1234:16,er1) ;0159c1431234 ++ or.w r3,@(0x12345678:32,er1) ;0159c94312345678 ++ or.w r3,@(0x1234:16,r2l.b) ;0159d2431234 ++ or.w r3,@(0x1234:16,r2.w) ;0159e2431234 ++ or.w r3,@(0x1234:16,er2.l) ;0159f2431234 ++ or.w r3,@(0x12345678:32,r2l.b) ;0159da4312345678 ++ or.w r3,@(0x12345678:32,r2.w) ;0159ea4312345678 ++ or.w r3,@(0x12345678:32,er2.l) ;0159fa4312345678 ++ or.w r3,@0x1234:16 ;6b1812346430 ++ or.w r3,@0x12345678:32 ;6b38123456786430 ++ ++ or.w @er3,r1 ;7cb06401 ++ or.w @(0x6:2,er3),r1 ;015a3341 ++ or.w @er3+,r1 ;015a8341 ++ or.w @-er3,r1 ;015ab341 ++ or.w @+er3,r1 ;015a9341 ++ or.w @er3-,r1 ;015aa341 ++ or.w @(0x1234:16,er1),r1 ;015ac1411234 ++ or.w @(0x12345678:32,er1),r1 ;015ac94112345678 ++ or.w @(0x1234:16,r2l.b),r1 ;015ad2411234 ++ or.w @(0x1234:16,r2.w),r1 ;015ae2411234 ++ or.w @(0x1234:16,er2.l),r1 ;015af2411234 ++ or.w @(0x12345678:32,r2l.b),r1 ;015ada4112345678 ++ or.w @(0x12345678:32,r2.w),r1 ;015aea4112345678 ++ or.w @(0x12345678:32,er2.l),r1 ;015afa4112345678 ++ or.w @0x1234:16,r1 ;6b1012346401 ++ or.w @0x12345678:32,r1 ;6b30123456786401 ++ ++ or.w @er3,@er1 ;7cb50140 ++ or.w @er3,@(6:2,er1) ;7cb53140 ++ or.w @er3,@-er1 ;7cb5b140 ++ or.w @er3,@er1+ ;7cb58140 ++ or.w @er3,@er1- ;7cb5a140 ++ or.w @er3,@+er1 ;7cb59140 ++ or.w @er3,@(0xffff9abc:16,er1) ;7cb5c1409abc ++ or.w @er3,@(0x9abcdef0:32,er1) ;7cb5c9409abcdef0 ++ or.w @er3,@(0xffff9abc:16,r2l.b) ;7cb5d2409abc ++ or.w @er3,@(0xffff9abc:16,r2.w) ;7cb5e2409abc ++ or.w @er3,@(0xffff9abc:16,er2.l) ;7cb5f2409abc ++ or.w @er3,@(0x9abcdef0:32,r2l.b) ;7cb5da409abcdef0 ++ or.w @er3,@(0x9abcdef0:32,r2.w) ;7cb5ea409abcdef0 ++ or.w @er3,@(0x9abcdef0:32,er2.l) ;7cb5fa409abcdef0 ++ or.w @er3,@0xffff9abc:16 ;7cb540409abc ++ or.w @er3,@0x9abcdef0:32 ;7cb548409abcdef0 ++ ++ or.w @-er3,@er1 ;01576d3c0140 ++ or.w @-er3,@(6:2,er1) ;01576d3c3140 ++ or.w @-er3,@-er1 ;01576d3cb140 ++ or.w @-er3,@er1+ ;01576d3c8140 ++ or.w @-er3,@er1- ;01576d3ca140 ++ or.w @-er3,@+er1 ;01576d3c9140 ++ or.w @-er3,@(0xffff9abc:16,er1) ;01576d3cc1409abc ++ or.w @-er3,@(0x9abcdef0:32,er1) ;01576d3cc9409abcdef0 ++ or.w @-er3,@(0xffff9abc:16,r2l.b) ;01576d3cd2409abc ++ or.w @-er3,@(0xffff9abc:16,r2.w) ;01576d3ce2409abc ++ or.w @-er3,@(0xffff9abc:16,er2.l) ;01576d3cf2409abc ++ or.w @-er3,@(0x9abcdef0:32,r2l.b) ;01576d3cda409abcdef0 ++ or.w @-er3,@(0x9abcdef0:32,r2.w) ;01576d3cea409abcdef0 ++ or.w @-er3,@(0x9abcdef0:32,er2.l) ;01576d3cfa409abcdef0 ++ or.w @-er3,@0xffff9abc:16 ;01576d3c40409abc ++ or.w @-er3,@0x9abcdef0:32 ;01576d3c48409abcdef0 ++ ++ or.w @er3+,@er1 ;01546d3c0140 ++ or.w @er3+,@(6:2,er1) ;01546d3c3140 ++ or.w @er3+,@-er1 ;01546d3cb140 ++ or.w @er3+,@er1+ ;01546d3c8140 ++ or.w @er3+,@er1- ;01546d3ca140 ++ or.w @er3+,@+er1 ;01546d3c9140 ++ or.w @er3+,@(0xffff9abc:16,er1) ;01546d3cc1409abc ++ or.w @er3+,@(0x9abcdef0:32,er1) ;01546d3cc9409abcdef0 ++ or.w @er3+,@(0xffff9abc:16,r2l.b) ;01546d3cd2409abc ++ or.w @er3+,@(0xffff9abc:16,r2.w) ;01546d3ce2409abc ++ or.w @er3+,@(0xffff9abc:16,er2.l) ;01546d3cf2409abc ++ or.w @er3+,@(0x9abcdef0:32,r2l.b) ;01546d3cda409abcdef0 ++ or.w @er3+,@(0x9abcdef0:32,r2.w) ;01546d3cea409abcdef0 ++ or.w @er3+,@(0x9abcdef0:32,er2.l) ;01546d3cfa409abcdef0 ++ or.w @er3+,@0xffff9abc:16 ;01546d3c40409abc ++ or.w @er3+,@0x9abcdef0:32 ;01546d3c48409abcdef0 ++ ++ or.w @er3-,@er1 ;01566d3c0140 ++ or.w @er3-,@(6:2,er1) ;01566d3c3140 ++ or.w @er3-,@-er1 ;01566d3cb140 ++ or.w @er3-,@er1+ ;01566d3c8140 ++ or.w @er3-,@er1- ;01566d3ca140 ++ or.w @er3-,@+er1 ;01566d3c9140 ++ or.w @er3-,@(0xffff9abc:16,er1) ;01566d3cc1409abc ++ or.w @er3-,@(0x9abcdef0:32,er1) ;01566d3cc9409abcdef0 ++ or.w @er3-,@(0xffff9abc:16,r2l.b) ;01566d3cd2409abc ++ or.w @er3-,@(0xffff9abc:16,r2.w) ;01566d3ce2409abc ++ or.w @er3-,@(0xffff9abc:16,er2.l) ;01566d3cf2409abc ++ or.w @er3-,@(0x9abcdef0:32,r2l.b) ;01566d3cda409abcdef0 ++ or.w @er3-,@(0x9abcdef0:32,r2.w) ;01566d3cea409abcdef0 ++ or.w @er3-,@(0x9abcdef0:32,er2.l) ;01566d3cfa409abcdef0 ++ or.w @er3-,@0xffff9abc:16 ;01566d3c40409abc ++ or.w @er3-,@0x9abcdef0:32 ;01566d3c48409abcdef0 ++ ++ or.w @+er3,@er1 ;01556d3c0140 ++ or.w @+er3,@(6:2,er1) ;01556d3c3140 ++ or.w @+er3,@-er1 ;01556d3cb140 ++ or.w @+er3,@er1+ ;01556d3c8140 ++ or.w @+er3,@er1- ;01556d3ca140 ++ or.w @+er3,@+er1 ;01556d3c9140 ++ or.w @+er3,@(0xffff9abc:16,er1) ;01556d3cc1409abc ++ or.w @+er3,@(0x9abcdef0:32,er1) ;01556d3cc9409abcdef0 ++ or.w @+er3,@(0xffff9abc:16,r2l.b) ;01556d3cd2409abc ++ or.w @+er3,@(0xffff9abc:16,r2.w) ;01556d3ce2409abc ++ or.w @+er3,@(0xffff9abc:16,er2.l) ;01556d3cf2409abc ++ or.w @+er3,@(0x9abcdef0:32,r2l.b) ;01556d3cda409abcdef0 ++ or.w @+er3,@(0x9abcdef0:32,r2.w) ;01556d3cea409abcdef0 ++ or.w @+er3,@(0x9abcdef0:32,er2.l) ;01556d3cfa409abcdef0 ++ or.w @+er3,@0xffff9abc:16 ;01556d3c40409abc ++ or.w @+er3,@0x9abcdef0:32 ;01556d3c48409abcdef0 ++ ++ or.w @(0x1234:16,er3),@er1 ;01546f3c12340140 ++ or.w @(0x1234:16,er3),@(6:2,er1) ;01546f3c12343140 ++ or.w @(0x1234:16,er3),@-er1 ;01546f3c1234b140 ++ or.w @(0x1234:16,er3),@er1+ ;01546f3c12348140 ++ or.w @(0x1234:16,er3),@er1- ;01546f3c1234a140 ++ or.w @(0x1234:16,er3),@+er1 ;01546f3c12349140 ++ or.w @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01546f3c1234c1409abc ++ or.w @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01546f3c1234c9409abcdef0 ++ or.w @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01546f3c1234d2409abc ++ or.w @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01546f3c1234e2409abc ++ or.w @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01546f3c1234f2409abc ++ or.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01546f3c1234da409abcdef0 ++ or.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01546f3c1234ea409abcdef0 ++ or.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01546f3c1234fa409abcdef0 ++ or.w @(0x1234:16,er3),@0xffff9abc:16 ;01546f3c123440409abc ++ or.w @(0x1234:16,er3),@0x9abcdef0:32 ;01546f3c123448409abcdef0 ++ ++ or.w @(0x12345678:32,er3),@er1 ;78346b2c123456780140 ++ or.w @(0x12345678:32,er3),@(6:2,er1) ;78346b2c123456783140 ++ or.w @(0x12345678:32,er3),@-er1 ;78346b2c12345678b140 ++ or.w @(0x12345678:32,er3),@er1+ ;78346b2c123456788140 ++ or.w @(0x12345678:32,er3),@er1- ;78346b2c12345678a140 ++ or.w @(0x12345678:32,er3),@+er1 ;78346b2c123456789140 ++ or.w @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346b2c12345678c1409abc ++ or.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346b2c12345678c9409abcdef0 ++ or.w @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346b2c12345678d2409abc ++ or.w @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346b2c12345678e2409abc ++ or.w @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346b2c12345678f2409abc ++ or.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346b2c12345678da409abcdef0 ++ or.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346b2c12345678ea409abcdef0 ++ or.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346b2c12345678fa409abcdef0 ++ or.w @(0x12345678:32,er3),@0xffff9abc:16 ;78346b2c1234567840409abc ++ or.w @(0x12345678:32,er3),@0x9abcdef0:32 ;78346b2c1234567848409abcdef0 ++ ++ or.w @(0x1234:16,r3l.b),@er1 ;01556f3c12340140 ++ or.w @(0x1234:16,r3l.b),@(6:2,er1) ;01556f3c12343140 ++ or.w @(0x1234:16,r3l.b),@-er1 ;01556f3c1234b140 ++ or.w @(0x1234:16,r3l.b),@er1+ ;01556f3c12348140 ++ or.w @(0x1234:16,r3l.b),@er1- ;01556f3c1234a140 ++ or.w @(0x1234:16,r3l.b),@+er1 ;01556f3c12349140 ++ or.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01556f3c1234c1409abc ++ or.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01556f3c1234c9409abcdef0 ++ or.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01556f3c1234d2409abc ++ or.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01556f3c1234e2409abc ++ or.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01556f3c1234f2409abc ++ or.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01556f3c1234da409abcdef0 ++ or.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01556f3c1234ea409abcdef0 ++ or.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01556f3c1234fa409abcdef0 ++ or.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;01556f3c123440409abc ++ or.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01556f3c123448409abcdef0 ++ ++ or.w @(0x1234:16,r3.w),@er1 ;01566f3c12340140 ++ or.w @(0x1234:16,r3.w),@(6:2,er1) ;01566f3c12343140 ++ or.w @(0x1234:16,r3.w),@-er1 ;01566f3c1234b140 ++ or.w @(0x1234:16,r3.w),@er1+ ;01566f3c12348140 ++ or.w @(0x1234:16,r3.w),@er1- ;01566f3c1234a140 ++ or.w @(0x1234:16,r3.w),@+er1 ;01566f3c12349140 ++ or.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01566f3c1234c1409abc ++ or.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01566f3c1234c9409abcdef0 ++ or.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01566f3c1234d2409abc ++ or.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01566f3c1234e2409abc ++ or.w @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01566f3c1234f2409abc ++ or.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01566f3c1234da409abcdef0 ++ or.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01566f3c1234ea409abcdef0 ++ or.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01566f3c1234fa409abcdef0 ++ or.w @(0x1234:16,r3.w),@0xffff9abc:16 ;01566f3c123440409abc ++ or.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;01566f3c123448409abcdef0 ++ ++ or.w @(0x1234:16,er3.l),@er1 ;01576f3c12340140 ++ or.w @(0x1234:16,er3.l),@(6:2,er1) ;01576f3c12343140 ++ or.w @(0x1234:16,er3.l),@-er1 ;01576f3c1234b140 ++ or.w @(0x1234:16,er3.l),@er1+ ;01576f3c12348140 ++ or.w @(0x1234:16,er3.l),@er1- ;01576f3c1234a140 ++ or.w @(0x1234:16,er3.l),@+er1 ;01576f3c12349140 ++ or.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01576f3c1234c1409abc ++ or.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01576f3c1234c9409abcdef0 ++ or.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01576f3c1234d2409abc ++ or.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01576f3c1234e2409abc ++ or.w @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01576f3c1234f2409abc ++ or.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01576f3c1234da409abcdef0 ++ or.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01576f3c1234ea409abcdef0 ++ or.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01576f3c1234fa409abcdef0 ++ or.w @(0x1234:16,er3.l),@0xffff9abc:16 ;01576f3c123440409abc ++ or.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;01576f3c123448409abcdef0 ++ ++ or.w @(0x12345678:32,r3l.b),@er1 ;78356b2c123456780140 ++ or.w @(0x12345678:32,r3l.b),@(6:2,er1) ;78356b2c123456783140 ++ or.w @(0x12345678:32,r3l.b),@-er1 ;78356b2c12345678b140 ++ or.w @(0x12345678:32,r3l.b),@er1+ ;78356b2c123456788140 ++ or.w @(0x12345678:32,r3l.b),@er1- ;78356b2c12345678a140 ++ or.w @(0x12345678:32,r3l.b),@+er1 ;78356b2c123456789140 ++ or.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356b2c12345678c1409abc ++ or.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356b2c12345678c9409abcdef0 ++ or.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356b2c12345678d2409abc ++ or.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356b2c12345678e2409abc ++ or.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356b2c12345678f2409abc ++ or.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356b2c12345678da409abcdef0 ++ or.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356b2c12345678ea409abcdef0 ++ or.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356b2c12345678fa409abcdef0 ++ or.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356b2c1234567840409abc ++ or.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356b2c1234567848409abcdef0 ++ ++ or.w @(0x12345678:32,r3.w),@er1 ;78366b2c123456780140 ++ or.w @(0x12345678:32,r3.w),@(6:2,er1) ;78366b2c123456783140 ++ or.w @(0x12345678:32,r3.w),@-er1 ;78366b2c12345678b140 ++ or.w @(0x12345678:32,r3.w),@er1+ ;78366b2c123456788140 ++ or.w @(0x12345678:32,r3.w),@er1- ;78366b2c12345678a140 ++ or.w @(0x12345678:32,r3.w),@+er1 ;78366b2c123456789140 ++ or.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366b2c12345678c1409abc ++ or.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366b2c12345678c9409abcdef0 ++ or.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366b2c12345678d2409abc ++ or.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366b2c12345678e2409abc ++ or.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366b2c12345678f2409abc ++ or.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366b2c12345678da409abcdef0 ++ or.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366b2c12345678ea409abcdef0 ++ or.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366b2c12345678fa409abcdef0 ++ or.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366b2c1234567840409abc ++ or.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366b2c1234567848409abcdef0 ++ ++ or.w @(0x12345678:32,er3.l),@er1 ;78376b2c123456780140 ++ or.w @(0x12345678:32,er3.l),@(6:2,er1) ;78376b2c123456783140 ++ or.w @(0x12345678:32,er3.l),@-er1 ;78376b2c12345678b140 ++ or.w @(0x12345678:32,er3.l),@er1+ ;78376b2c123456788140 ++ or.w @(0x12345678:32,er3.l),@er1- ;78376b2c12345678a140 ++ or.w @(0x12345678:32,er3.l),@+er1 ;78376b2c123456789140 ++ or.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376b2c12345678c1409abc ++ or.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376b2c12345678c9409abcdef0 ++ or.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376b2c12345678d2409abc ++ or.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376b2c12345678e2409abc ++ or.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376b2c12345678f2409abc ++ or.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376b2c12345678da409abcdef0 ++ or.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376b2c12345678ea409abcdef0 ++ or.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376b2c12345678fa409abcdef0 ++ or.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376b2c1234567840409abc ++ or.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376b2c1234567848409abcdef0 ++ ++ or.w @0x1234:16,@er1 ;6b1512340140 ++ or.w @0x1234:16,@(6:2,er1) ;6b1512343140 ++ or.w @0x1234:16,@-er1 ;6b151234b140 ++ or.w @0x1234:16,@er1+ ;6b1512348140 ++ or.w @0x1234:16,@er1- ;6b151234a140 ++ or.w @0x1234:16,@+er1 ;6b1512349140 ++ or.w @0x1234:16,@(0xffff9abc:16,er1) ;6b151234c1409abc ++ or.w @0x1234:16,@(0x9abcdef0:32,er1) ;6b151234c9409abcdef0 ++ or.w @0x1234:16,@(0xffff9abc:16,r2l.b) ;6b151234d2409abc ++ or.w @0x1234:16,@(0xffff9abc:16,r2.w) ;6b151234e2409abc ++ or.w @0x1234:16,@(0xffff9abc:16,er2.l) ;6b151234f2409abc ++ or.w @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6b151234da409abcdef0 ++ or.w @0x1234:16,@(0x9abcdef0:32,r2.w) ;6b151234ea409abcdef0 ++ or.w @0x1234:16,@(0x9abcdef0:32,er2.l) ;6b151234fa409abcdef0 ++ or.w @0x1234:16,@0xffff9abc:16 ;6b15123440409abc ++ or.w @0x1234:16,@0x9abcdef0:32 ;6b15123448409abcdef0 ++ ++ or.w @0x12345678:32,@er1 ;6b35123456780140 ++ or.w @0x12345678:32,@(6:2,er1) ;6b35123456783140 ++ or.w @0x12345678:32,@-er1 ;6b3512345678b140 ++ or.w @0x12345678:32,@er1+ ;6b35123456788140 ++ or.w @0x12345678:32,@er1- ;6b3512345678a140 ++ or.w @0x12345678:32,@+er1 ;6b35123456789140 ++ or.w @0x12345678:32,@(0xffff9abc:16,er1) ;6b3512345678c1409abc ++ or.w @0x12345678:32,@(0x9abcdef0:32,er1) ;6b3512345678c9409abcdef0 ++ or.w @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6b3512345678d2409abc ++ or.w @0x12345678:32,@(0xffff9abc:16,r2.w) ;6b3512345678e2409abc ++ or.w @0x12345678:32,@(0xffff9abc:16,er2.l) ;6b3512345678f2409abc ++ or.w @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6b3512345678da409abcdef0 ++ or.w @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6b3512345678ea409abcdef0 ++ or.w @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6b3512345678fa409abcdef0 ++ or.w @0x12345678:32,@0xffff9abc:16 ;6b351234567840409abc ++ or.w @0x12345678:32,@0x9abcdef0:32 ;6b351234567848409abcdef0 ++ ++ or.l #0x12345678:32,er1 ;7a4112345678 ++ or.l #0x1234:16,er1 ;7a491234 ++ or.l #0x12345678:32,@er1 ;010e014812345678 ++ or.l #0x12345678:32,@(0xc:2,er1) ;010e314812345678 ++ or.l #0x12345678:32,@er1+ ;010e814812345678 ++ or.l #0x12345678:32,@-er1 ;010eb14812345678 ++ or.l #0x12345678:32,@+er1 ;010e914812345678 ++ or.l #0x12345678:32,@er1- ;010ea14812345678 ++ or.l #0x12345678:32,@(0xffff9abc:16,er1) ;010ec1489abc12345678 ++ or.l #0x12345678:32,@(0x9abcdef0:32,er1) ;010ec9489abcdef012345678 ++ or.l #0x12345678:32,@(0xffff9abc:16,r2l.b) ;010ed2489abc12345678 ++ or.l #0x12345678:32,@(0xffff9abc:16,r2.w) ;010ee2489abc12345678 ++ or.l #0x12345678:32,@(0xffff9abc:16,er2.l) ;010ef2489abc12345678 ++ or.l #0x12345678:32,@(0x9abcdef0:32,r2l.b) ;010eda489abcdef012345678 ++ or.l #0x12345678:32,@(0x9abcdef0:32,r2.w) ;010eea489abcdef012345678 ++ or.l #0x12345678:32,@(0x9abcdef0:32,er2.l) ;010efa489abcdef012345678 ++ or.l #0x12345678:32,@0xffff9abc:16 ;010e40489abc12345678 ++ or.l #0x12345678:32,@0x9abcdef0:32 ;010e48489abcdef012345678 ++ or.l #0x1234:16,@er1 ;010e01401234 ++ or.l #0x1234:16,@(0xc:2,er1) ;010e31401234 ++ or.l #0x1234:16,@er1+ ;010e81401234 ++ or.l #0x1234:16,@-er1 ;010eb1401234 ++ or.l #0x1234:16,@+er1 ;010e91401234 ++ or.l #0x1234:16,@er1- ;010ea1401234 ++ or.l #0x1234:16,@(0xffff9abc:16,er1) ;010ec1409abc1234 ++ or.l #0x1234:16,@(0x9abcdef0:32,er1) ;010ec9409abcdef01234 ++ or.l #0x1234:16,@(0xffff9abc:16,r2l.b) ;010ed2409abc1234 ++ or.l #0x1234:16,@(0xffff9abc:16,r2.w) ;010ee2409abc1234 ++ or.l #0x1234:16,@(0xffff9abc:16,er2.l) ;010ef2409abc1234 ++ or.l #0x1234:16,@(0x9abcdef0:32,r2l.b) ;010eda409abcdef01234 ++ or.l #0x1234:16,@(0x9abcdef0:32,r2.w) ;010eea409abcdef01234 ++ or.l #0x1234:16,@(0x9abcdef0:32,er2.l) ;010efa409abcdef01234 ++ or.l #0x1234:16,@0xffff9abc:16 ;010e40409abc1234 ++ or.l #0x1234:16,@0x9abcdef0:32 ;010e48409abcdef01234 ++ ++ or.l er3,er1 ;01f06431 ++ ++ or.l er3,@er1 ;01090143 ++ or.l er3,@(0xc:2,er1) ;01093143 ++ or.l er3,@er1+ ;01098143 ++ or.l er3,@-er1 ;0109b143 ++ or.l er3,@+er1 ;01099143 ++ or.l er3,@er1- ;0109a143 ++ or.l er3,@(0x1234:16,er1) ;0109c1431234 ++ or.l er3,@(0x12345678:32,er1) ;0109c94312345678 ++ or.l er3,@(0x1234:16,r2l.b) ;0109d2431234 ++ or.l er3,@(0x1234:16,r2.w) ;0109e2431234 ++ or.l er3,@(0x1234:16,er2.l) ;0109f2431234 ++ or.l er3,@(0x12345678:32,r2l.b) ;0109da4312345678 ++ or.l er3,@(0x12345678:32,r2.w) ;0109ea4312345678 ++ or.l er3,@(0x12345678:32,er2.l) ;0109fa4312345678 ++ or.l er3,@0x1234:16 ;010940431234 ++ or.l er3,@0x12345678:32 ;0109484312345678 ++ ++ or.l @er3,er1 ;010a0341 ++ or.l @(0xc:2,er3),er1 ;010a3341 ++ or.l @er3+,er1 ;010a8341 ++ or.l @-er3,er1 ;010ab341 ++ or.l @+er3,er1 ;010a9341 ++ or.l @er3-,er1 ;010aa341 ++ or.l @(0x1234:16,er1),er1 ;010ac1411234 ++ or.l @(0x12345678:32,er1),er1 ;010ac94112345678 ++ or.l @(0x1234:16,r2l.b),er1 ;010ad2411234 ++ or.l @(0x1234:16,r2.w),er1 ;010ae2411234 ++ or.l @(0x1234:16,er2.l),er1 ;010af2411234 ++ or.l @(0x12345678:32,r2l.b),er1 ;010ada4112345678 ++ or.l @(0x12345678:32,r2.w),er1 ;010aea4112345678 ++ or.l @(0x12345678:32,er2.l),er1 ;010afa4112345678 ++ or.l @0x1234:16,er1 ;010a40411234 ++ or.l @0x12345678:32,er1 ;010a484112345678 ++ ++ or.l @er3,@er1 ;0104693c0140 ++ or.l @er3,@(0xc:2,er1) ;0104693c3140 ++ or.l @er3,@-er1 ;0104693cb140 ++ or.l @er3,@er1+ ;0104693c8140 ++ or.l @er3,@er1- ;0104693ca140 ++ or.l @er3,@+er1 ;0104693c9140 ++ or.l @er3,@(0xffff9abc:16,er1) ;0104693cc1409abc ++ or.l @er3,@(0x9abcdef0:32,er1) ;0104693cc9409abcdef0 ++ or.l @er3,@(0xffff9abc:16,r2l.b) ;0104693cd2409abc ++ or.l @er3,@(0xffff9abc:16,r2.w) ;0104693ce2409abc ++ or.l @er3,@(0xffff9abc:16,er2.l) ;0104693cf2409abc ++ or.l @er3,@(0x9abcdef0:32,r2l.b) ;0104693cda409abcdef0 ++ or.l @er3,@(0x9abcdef0:32,r2.w) ;0104693cea409abcdef0 ++ or.l @er3,@(0x9abcdef0:32,er2.l) ;0104693cfa409abcdef0 ++ or.l @er3,@0xffff9abc:16 ;0104693c40409abc ++ or.l @er3,@0x9abcdef0:32 ;0104693c48409abcdef0 ++ ++ or.l @(0xc:2,er3),@er1 ;0107693c0140 ++ or.l @(0xc:2,er3),@(0xc:2,er1) ;0107693c3140 ++ or.l @(0xc:2,er3),@-er1 ;0107693cb140 ++ or.l @(0xc:2,er3),@er1+ ;0107693c8140 ++ or.l @(0xc:2,er3),@er1- ;0107693ca140 ++ or.l @(0xc:2,er3),@+er1 ;0107693c9140 ++ or.l @(0xc:2,er3),@(0xffff9abc:16,er1) ;0107693cc1409abc ++ or.l @(0xc:2,er3),@(0x9abcdef0:32,er1) ;0107693cc9409abcdef0 ++ or.l @(0xc:2,er3),@(0xffff9abc:16,r2l.b) ;0107693cd2409abc ++ or.l @(0xc:2,er3),@(0xffff9abc:16,r2.w) ;0107693ce2409abc ++ or.l @(0xc:2,er3),@(0xffff9abc:16,er2.l) ;0107693cf2409abc ++ or.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b) ;0107693cda409abcdef0 ++ or.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w) ;0107693cea409abcdef0 ++ or.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l) ;0107693cfa409abcdef0 ++ or.l @(0xc:2,er3),@0xffff9abc:16 ;0107693c40409abc ++ or.l @(0xc:2,er3),@0x9abcdef0:32 ;0107693c48409abcdef0 ++ ++ or.l @-er3,@er1 ;01076d3c0140 ++ or.l @-er3,@(0xc:2,er1) ;01076d3c3140 ++ or.l @-er3,@-er1 ;01076d3cb140 ++ or.l @-er3,@er1+ ;01076d3c8140 ++ or.l @-er3,@er1- ;01076d3ca140 ++ or.l @-er3,@+er1 ;01076d3c9140 ++ or.l @-er3,@(0xffff9abc:16,er1) ;01076d3cc1409abc ++ or.l @-er3,@(0x9abcdef0:32,er1) ;01076d3cc9409abcdef0 ++ or.l @-er3,@(0xffff9abc:16,r2l.b) ;01076d3cd2409abc ++ or.l @-er3,@(0xffff9abc:16,r2.w) ;01076d3ce2409abc ++ or.l @-er3,@(0xffff9abc:16,er2.l) ;01076d3cf2409abc ++ or.l @-er3,@(0x9abcdef0:32,r2l.b) ;01076d3cda409abcdef0 ++ or.l @-er3,@(0x9abcdef0:32,r2.w) ;01076d3cea409abcdef0 ++ or.l @-er3,@(0x9abcdef0:32,er2.l) ;01076d3cfa409abcdef0 ++ or.l @-er3,@0xffff9abc:16 ;01076d3c40409abc ++ or.l @-er3,@0x9abcdef0:32 ;01076d3c48409abcdef0 ++ ++ or.l @er3+,@er1 ;01046d3c0140 ++ or.l @er3+,@(0xc:2,er1) ;01046d3c3140 ++ or.l @er3+,@-er1 ;01046d3cb140 ++ or.l @er3+,@er1+ ;01046d3c8140 ++ or.l @er3+,@er1- ;01046d3ca140 ++ or.l @er3+,@+er1 ;01046d3c9140 ++ or.l @er3+,@(0xffff9abc:16,er1) ;01046d3cc1409abc ++ or.l @er3+,@(0x9abcdef0:32,er1) ;01046d3cc9409abcdef0 ++ or.l @er3+,@(0xffff9abc:16,r2l.b) ;01046d3cd2409abc ++ or.l @er3+,@(0xffff9abc:16,r2.w) ;01046d3ce2409abc ++ or.l @er3+,@(0xffff9abc:16,er2.l) ;01046d3cf2409abc ++ or.l @er3+,@(0x9abcdef0:32,r2l.b) ;01046d3cda409abcdef0 ++ or.l @er3+,@(0x9abcdef0:32,r2.w) ;01046d3cea409abcdef0 ++ or.l @er3+,@(0x9abcdef0:32,er2.l) ;01046d3cfa409abcdef0 ++ or.l @er3+,@0xffff9abc:16 ;01046d3c40409abc ++ or.l @er3+,@0x9abcdef0:32 ;01046d3c48409abcdef0 ++ ++ or.l @er3-,@er1 ;01066d3c0140 ++ or.l @er3-,@(0xc:2,er1) ;01066d3c3140 ++ or.l @er3-,@-er1 ;01066d3cb140 ++ or.l @er3-,@er1+ ;01066d3c8140 ++ or.l @er3-,@er1- ;01066d3ca140 ++ or.l @er3-,@+er1 ;01066d3c9140 ++ or.l @er3-,@(0xffff9abc:16,er1) ;01066d3cc1409abc ++ or.l @er3-,@(0x9abcdef0:32,er1) ;01066d3cc9409abcdef0 ++ or.l @er3-,@(0xffff9abc:16,r2l.b) ;01066d3cd2409abc ++ or.l @er3-,@(0xffff9abc:16,r2.w) ;01066d3ce2409abc ++ or.l @er3-,@(0xffff9abc:16,er2.l) ;01066d3cf2409abc ++ or.l @er3-,@(0x9abcdef0:32,r2l.b) ;01066d3cda409abcdef0 ++ or.l @er3-,@(0x9abcdef0:32,r2.w) ;01066d3cea409abcdef0 ++ or.l @er3-,@(0x9abcdef0:32,er2.l) ;01066d3cfa409abcdef0 ++ or.l @er3-,@0xffff9abc:16 ;01066d3c40409abc ++ or.l @er3-,@0x9abcdef0:32 ;01066d3c48409abcdef0 ++ ++ or.l @+er3,@er1 ;01056d3c0140 ++ or.l @+er3,@(0xc:2,er1) ;01056d3c3140 ++ or.l @+er3,@-er1 ;01056d3cb140 ++ or.l @+er3,@er1+ ;01056d3c8140 ++ or.l @+er3,@er1- ;01056d3ca140 ++ or.l @+er3,@+er1 ;01056d3c9140 ++ or.l @+er3,@(0xffff9abc:16,er1) ;01056d3cc1409abc ++ or.l @+er3,@(0x9abcdef0:32,er1) ;01056d3cc9409abcdef0 ++ or.l @+er3,@(0xffff9abc:16,r2l.b) ;01056d3cd2409abc ++ or.l @+er3,@(0xffff9abc:16,r2.w) ;01056d3ce2409abc ++ or.l @+er3,@(0xffff9abc:16,er2.l) ;01056d3cf2409abc ++ or.l @+er3,@(0x9abcdef0:32,r2l.b) ;01056d3cda409abcdef0 ++ or.l @+er3,@(0x9abcdef0:32,r2.w) ;01056d3cea409abcdef0 ++ or.l @+er3,@(0x9abcdef0:32,er2.l) ;01056d3cfa409abcdef0 ++ or.l @+er3,@0xffff9abc:16 ;01056d3c40409abc ++ or.l @+er3,@0x9abcdef0:32 ;01056d3c48409abcdef0 ++ ++ or.l @(0x1234:16,er3),@er1 ;01046f3c12340140 ++ or.l @(0x1234:16,er3),@(0xc:2,er1) ;01046f3c12343140 ++ or.l @(0x1234:16,er3),@-er1 ;01046f3c1234b140 ++ or.l @(0x1234:16,er3),@er1+ ;01046f3c12348140 ++ or.l @(0x1234:16,er3),@er1- ;01046f3c1234a140 ++ or.l @(0x1234:16,er3),@+er1 ;01046f3c12349140 ++ or.l @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01046f3c1234c1409abc ++ or.l @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01046f3c1234c9409abcdef0 ++ or.l @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01046f3c1234d2409abc ++ or.l @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01046f3c1234e2409abc ++ or.l @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01046f3c1234f2409abc ++ or.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01046f3c1234da409abcdef0 ++ or.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01046f3c1234ea409abcdef0 ++ or.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01046f3c1234fa409abcdef0 ++ or.l @(0x1234:16,er3),@0xffff9abc:16 ;01046f3c123440409abc ++ or.l @(0x1234:16,er3),@0x9abcdef0:32 ;01046f3c123448409abcdef0 ++ ++ or.l @(0x12345678:32,er3),@er1 ;78b46b2c123456780140 ++ or.l @(0x12345678:32,er3),@(0xc:2,er1) ;78b46b2c123456783140 ++ or.l @(0x12345678:32,er3),@-er1 ;78b46b2c12345678b140 ++ or.l @(0x12345678:32,er3),@er1+ ;78b46b2c123456788140 ++ or.l @(0x12345678:32,er3),@er1- ;78b46b2c12345678a140 ++ or.l @(0x12345678:32,er3),@+er1 ;78b46b2c123456789140 ++ or.l @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78b46b2c12345678c1409abc ++ or.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78b46b2c12345678c9409abcdef0 ++ or.l @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78b46b2c12345678d2409abc ++ or.l @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78b46b2c12345678e2409abc ++ or.l @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78b46b2c12345678f2409abc ++ or.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78b46b2c12345678da409abcdef0 ++ or.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78b46b2c12345678ea409abcdef0 ++ or.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78b46b2c12345678fa409abcdef0 ++ or.l @(0x12345678:32,er3),@0xffff9abc:16 ;78b46b2c1234567840409abc ++ or.l @(0x12345678:32,er3),@0x9abcdef0:32 ;78b46b2c1234567848409abcdef0 ++ ++ or.l @(0x1234:16,r3l.b),@er1 ;01056f3c12340140 ++ or.l @(0x1234:16,r3l.b),@(0xc:2,er1) ;01056f3c12343140 ++ or.l @(0x1234:16,r3l.b),@-er1 ;01056f3c1234b140 ++ or.l @(0x1234:16,r3l.b),@er1+ ;01056f3c12348140 ++ or.l @(0x1234:16,r3l.b),@er1- ;01056f3c1234a140 ++ or.l @(0x1234:16,r3l.b),@+er1 ;01056f3c12349140 ++ or.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01056f3c1234c1409abc ++ or.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01056f3c1234c9409abcdef0 ++ or.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01056f3c1234d2409abc ++ or.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01056f3c1234e2409abc ++ or.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01056f3c1234f2409abc ++ or.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01056f3c1234da409abcdef0 ++ or.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01056f3c1234ea409abcdef0 ++ or.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01056f3c1234fa409abcdef0 ++ or.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;01056f3c123440409abc ++ or.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01056f3c123448409abcdef0 ++ ++ or.l @(0x1234:16,r3.w),@er1 ;01066f3c12340140 ++ or.l @(0x1234:16,r3.w),@(0xc:2,er1) ;01066f3c12343140 ++ or.l @(0x1234:16,r3.w),@-er1 ;01066f3c1234b140 ++ or.l @(0x1234:16,r3.w),@er1+ ;01066f3c12348140 ++ or.l @(0x1234:16,r3.w),@er1- ;01066f3c1234a140 ++ or.l @(0x1234:16,r3.w),@+er1 ;01066f3c12349140 ++ or.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01066f3c1234c1409abc ++ or.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01066f3c1234c9409abcdef0 ++ or.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01066f3c1234d2409abc ++ or.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01066f3c1234e2409abc ++ or.l @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01066f3c1234f2409abc ++ or.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01066f3c1234da409abcdef0 ++ or.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01066f3c1234ea409abcdef0 ++ or.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01066f3c1234fa409abcdef0 ++ or.l @(0x1234:16,r3.w),@0xffff9abc:16 ;01066f3c123440409abc ++ or.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;01066f3c123448409abcdef0 ++ ++ or.l @(0x1234:16,er3.l),@er1 ;01076f3c12340140 ++ or.l @(0x1234:16,er3.l),@(0xc:2,er1) ;01076f3c12343140 ++ or.l @(0x1234:16,er3.l),@-er1 ;01076f3c1234b140 ++ or.l @(0x1234:16,er3.l),@er1+ ;01076f3c12348140 ++ or.l @(0x1234:16,er3.l),@er1- ;01076f3c1234a140 ++ or.l @(0x1234:16,er3.l),@+er1 ;01076f3c12349140 ++ or.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01076f3c1234c1409abc ++ or.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01076f3c1234c9409abcdef0 ++ or.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01076f3c1234d2409abc ++ or.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01076f3c1234e2409abc ++ or.l @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01076f3c1234f2409abc ++ or.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01076f3c1234da409abcdef0 ++ or.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01076f3c1234ea409abcdef0 ++ or.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01076f3c1234fa409abcdef0 ++ or.l @(0x1234:16,er3.l),@0xffff9abc:16 ;01076f3c123440409abc ++ or.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;01076f3c123448409abcdef0 ++ ++ or.l @(0x12345678:32,r3l.b),@er1 ;78b56b2c123456780140 ++ or.l @(0x12345678:32,r3l.b),@(0xc:2,er1) ;78b56b2c123456783140 ++ or.l @(0x12345678:32,r3l.b),@-er1 ;78b56b2c12345678b140 ++ or.l @(0x12345678:32,r3l.b),@er1+ ;78b56b2c123456788140 ++ or.l @(0x12345678:32,r3l.b),@er1- ;78b56b2c12345678a140 ++ or.l @(0x12345678:32,r3l.b),@+er1 ;78b56b2c123456789140 ++ or.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78b56b2c12345678c1409abc ++ or.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78b56b2c12345678c9409abcdef0 ++ or.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78b56b2c12345678d2409abc ++ or.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78b56b2c12345678e2409abc ++ or.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78b56b2c12345678f2409abc ++ or.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78b56b2c12345678da409abcdef0 ++ or.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78b56b2c12345678ea409abcdef0 ++ or.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78b56b2c12345678fa409abcdef0 ++ or.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78b56b2c1234567840409abc ++ or.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78b56b2c1234567848409abcdef0 ++ ++ or.l @(0x12345678:32,r3.w),@er1 ;78b66b2c123456780140 ++ or.l @(0x12345678:32,r3.w),@(0xc:2,er1) ;78b66b2c123456783140 ++ or.l @(0x12345678:32,r3.w),@-er1 ;78b66b2c12345678b140 ++ or.l @(0x12345678:32,r3.w),@er1+ ;78b66b2c123456788140 ++ or.l @(0x12345678:32,r3.w),@er1- ;78b66b2c12345678a140 ++ or.l @(0x12345678:32,r3.w),@+er1 ;78b66b2c123456789140 ++ or.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78b66b2c12345678c1409abc ++ or.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78b66b2c12345678c9409abcdef0 ++ or.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78b66b2c12345678d2409abc ++ or.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78b66b2c12345678e2409abc ++ or.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78b66b2c12345678f2409abc ++ or.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78b66b2c12345678da409abcdef0 ++ or.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78b66b2c12345678ea409abcdef0 ++ or.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78b66b2c12345678fa409abcdef0 ++ or.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;78b66b2c1234567840409abc ++ or.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78b66b2c1234567848409abcdef0 ++ ++ or.l @(0x12345678:32,er3.l),@er1 ;78b76b2c123456780140 ++ or.l @(0x12345678:32,er3.l),@(0xc:2,er1) ;78b76b2c123456783140 ++ or.l @(0x12345678:32,er3.l),@-er1 ;78b76b2c12345678b140 ++ or.l @(0x12345678:32,er3.l),@er1+ ;78b76b2c123456788140 ++ or.l @(0x12345678:32,er3.l),@er1- ;78b76b2c12345678a140 ++ or.l @(0x12345678:32,er3.l),@+er1 ;78b76b2c123456789140 ++ or.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78b76b2c12345678c1409abc ++ or.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78b76b2c12345678c9409abcdef0 ++ or.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78b76b2c12345678d2409abc ++ or.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78b76b2c12345678e2409abc ++ or.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78b76b2c12345678f2409abc ++ or.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78b76b2c12345678da409abcdef0 ++ or.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78b76b2c12345678ea409abcdef0 ++ or.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78b76b2c12345678fa409abcdef0 ++ or.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;78b76b2c1234567840409abc ++ or.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78b76b2c1234567848409abcdef0 ++ ++ or.l @0x1234:16,@er1 ;01046b0c12340140 ++ or.l @0x1234:16,@(0xc:2,er1) ;01046b0c12343140 ++ or.l @0x1234:16,@-er1 ;01046b0c1234b140 ++ or.l @0x1234:16,@er1+ ;01046b0c12348140 ++ or.l @0x1234:16,@er1- ;01046b0c1234a140 ++ or.l @0x1234:16,@+er1 ;01046b0c12349140 ++ or.l @0x1234:16,@(0xffff9abc:16,er1) ;01046b0c1234c1409abc ++ or.l @0x1234:16,@(0x9abcdef0:32,er1) ;01046b0c1234c9409abcdef0 ++ or.l @0x1234:16,@(0xffff9abc:16,r2l.b) ;01046b0c1234d2409abc ++ or.l @0x1234:16,@(0xffff9abc:16,r2.w) ;01046b0c1234e2409abc ++ or.l @0x1234:16,@(0xffff9abc:16,er2.l) ;01046b0c1234f2409abc ++ or.l @0x1234:16,@(0x9abcdef0:32,r2l.b) ;01046b0c1234da409abcdef0 ++ or.l @0x1234:16,@(0x9abcdef0:32,r2.w) ;01046b0c1234ea409abcdef0 ++ or.l @0x1234:16,@(0x9abcdef0:32,er2.l) ;01046b0c1234fa409abcdef0 ++ or.l @0x1234:16,@0xffff9abc:16 ;01046b0c123440409abc ++ or.l @0x1234:16,@0x9abcdef0:32 ;01046b0c123448409abcdef0 ++ ++ or.l @0x12345678:32,@er1 ;01046b2c123456780140 ++ or.l @0x12345678:32,@(0xc:2,er1) ;01046b2c123456783140 ++ or.l @0x12345678:32,@-er1 ;01046b2c12345678b140 ++ or.l @0x12345678:32,@er1+ ;01046b2c123456788140 ++ or.l @0x12345678:32,@er1- ;01046b2c12345678a140 ++ or.l @0x12345678:32,@+er1 ;01046b2c123456789140 ++ or.l @0x12345678:32,@(0xffff9abc:16,er1) ;01046b2c12345678c1409abc ++ or.l @0x12345678:32,@(0x9abcdef0:32,er1) ;01046b2c12345678c9409abcdef0 ++ or.l @0x12345678:32,@(0xffff9abc:16,r2l.b) ;01046b2c12345678d2409abc ++ or.l @0x12345678:32,@(0xffff9abc:16,r2.w) ;01046b2c12345678e2409abc ++ or.l @0x12345678:32,@(0xffff9abc:16,er2.l) ;01046b2c12345678f2409abc ++ or.l @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;01046b2c12345678da409abcdef0 ++ or.l @0x12345678:32,@(0x9abcdef0:32,r2.w) ;01046b2c12345678ea409abcdef0 ++ or.l @0x12345678:32,@(0x9abcdef0:32,er2.l) ;01046b2c12345678fa409abcdef0 ++ or.l @0x12345678:32,@0xffff9abc:16 ;01046b2c1234567840409abc ++ or.l @0x12345678:32,@0x9abcdef0:32 ;01046b2c1234567848409abcdef0 ++ ++ .end diff --git a/gas/testsuite/gas/h8300/t09_xor.exp b/gas/testsuite/gas/h8300/t09_xor.exp new file mode 100644 -index 0000000..3247e58 +index 0000000..abd3c5e --- /dev/null +++ b/gas/testsuite/gas/h8300/t09_xor.exp -@@ -0,0 +1,3019 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,3018 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1176353,989 +1183526,988 @@ index 0000000..3247e58 + diff --git a/gas/testsuite/gas/h8300/t09_xor.s b/gas/testsuite/gas/h8300/t09_xor.s new file mode 100644 -index 0000000..cc88f3f +index 0000000..ae0bd3c --- /dev/null +++ b/gas/testsuite/gas/h8300/t09_xor.s @@ -0,0 +1,971 @@ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+;log_1 -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ .h8300sx -+ .text -+_start: -+ xor.b #0x12:8,r1h ;d112 -+ xor.b #0x12:8,@er1 ;7d10d012 -+ xor.b #0x12:8,@(0x3:2,er1) ;01776818d012 -+ xor.b #0x12:8,@er1+ ;01746c18d012 -+ xor.b #0x12:8,@-er1 ;01776c18d012 -+ xor.b #0x12:8,@+er1 ;01756c18d012 -+ xor.b #0x12:8,@er1- ;01766c18d012 -+ xor.b #0x12:8,@(0x1234:16,er1) ;01746e181234d012 -+ xor.b #0x12:8,@(0x12345678:32,er1) ;78146a2812345678d012 -+ xor.b #0x12:8,@(0x1234:16,r2l.b) ;01756e281234d012 -+ xor.b #0x12:8,@(0x1234:16,r2.w) ;01766e281234d012 -+ xor.b #0x12:8,@(0x1234:16,er2.l) ;01776e281234d012 -+ xor.b #0x12:8,@(0x12345678:32,r2l.b) ;78256a2812345678d012 -+ xor.b #0x12:8,@(0x12345678:32,r2.w) ;78266a2812345678d012 -+ xor.b #0x12:8,@(0x12345678:32,er2.l) ;78276a2812345678d012 -+ xor.b #0x12:8,@0xffffff12:8 ;7f12d012 -+ xor.b #0x12:8,@0x1234:16 ;6a181234d012 -+ xor.b #0x12:8,@0x12345678:32 ;6a3812345678d012 -+ -+ xor.b r3h,r1h ;1531 -+ -+ xor.b r3h,@er1 ;7d101530 -+ xor.b r3h,@(0x3:2,er1) ;01793153 -+ xor.b r3h,@er1+ ;01798153 -+ xor.b r3h,@-er1 ;0179b153 -+ xor.b r3h,@+er1 ;01799153 -+ xor.b r3h,@er1- ;0179a153 -+ xor.b r3h,@(0x1234:16,er1) ;0179c1531234 -+ xor.b r3h,@(0x12345678:32,er1) ;0179c95312345678 -+ xor.b r3h,@(0x1234:16,r2l.b) ;0179d2531234 -+ xor.b r3h,@(0x1234:16,r2.w) ;0179e2531234 -+ xor.b r3h,@(0x1234:16,er2.l) ;0179f2531234 -+ xor.b r3h,@(0x12345678:32,r2l.b) ;0179da5312345678 -+ xor.b r3h,@(0x12345678:32,r2.w) ;0179ea5312345678 -+ xor.b r3h,@(0x12345678:32,er2.l) ;0179fa5312345678 -+ xor.b r3h,@0xffffff12:8 ;7f121530 -+ xor.b r3h,@0x1234:16 ;6a1812341530 -+ xor.b r3h,@0x12345678:32 ;6a38123456781530 -+ -+ xor.b @er3,r1h ;7c301501 -+ xor.b @(0x3:2,er3),r1h ;017a3351 -+ xor.b @er3+,r1h ;017a8351 -+ xor.b @-er3,r1h ;017ab351 -+ xor.b @+er3,r1h ;017a9351 -+ xor.b @er3-,r1h ;017aa351 -+ xor.b @(0x1234:16,er1),r1h ;017ac1511234 -+ xor.b @(0x12345678:32,er1),r1h ;017ac95112345678 -+ xor.b @(0x1234:16,r2l.b),r1h ;017ad2511234 -+ xor.b @(0x1234:16,r2.w),r1h ;017ae2511234 -+ xor.b @(0x1234:16,er2.l),r1h ;017af2511234 -+ xor.b @(0x12345678:32,r2l.b),r1h ;017ada5112345678 -+ xor.b @(0x12345678:32,r2.w),r1h ;017aea5112345678 -+ xor.b @(0x12345678:32,er2.l),r1h ;017afa5112345678 -+ xor.b @0xffffff12:8,r1h ;7e121501 -+ xor.b @0x1234:16,r1h ;6a1012341501 -+ xor.b @0x12345678:32,r1h ;6a30123456781501 -+ -+ xor.b @er3,@er1 ;7c350150 -+ xor.b @er3,@(3:2,er1) ;7c353150 -+ xor.b @er3,@-er1 ;7c35b150 -+ xor.b @er3,@er1+ ;7c358150 -+ xor.b @er3,@er1- ;7c35a150 -+ xor.b @er3,@+er1 ;7c359150 -+ xor.b @er3,@(0xffff9abc:16,er1) ;7c35c1509abc -+ xor.b @er3,@(0x9abcdef0:32,er1) ;7c35c9509abcdef0 -+ xor.b @er3,@(0xffff9abc:16,r2l.b) ;7c35d2509abc -+ xor.b @er3,@(0xffff9abc:16,r2.w) ;7c35e2509abc -+ xor.b @er3,@(0xffff9abc:16,er2.l) ;7c35f2509abc -+ xor.b @er3,@(0x9abcdef0:32,r2l.b) ;7c35da509abcdef0 -+ xor.b @er3,@(0x9abcdef0:32,r2.w) ;7c35ea509abcdef0 -+ xor.b @er3,@(0x9abcdef0:32,er2.l) ;7c35fa509abcdef0 -+ xor.b @er3,@0xffff9abc:16 ;7c3540509abc -+ xor.b @er3,@0x9abcdef0:32 ;7c3548509abcdef0 -+ -+ xor.b @-er3,@er1 ;01776c3c0150 -+ xor.b @-er3,@(3:2,er1) ;01776c3c3150 -+ xor.b @-er3,@-er1 ;01776c3cb150 -+ xor.b @-er3,@er1+ ;01776c3c8150 -+ xor.b @-er3,@er1- ;01776c3ca150 -+ xor.b @-er3,@+er1 ;01776c3c9150 -+ xor.b @-er3,@(0xffff9abc:16,er1) ;01776c3cc1509abc -+ xor.b @-er3,@(0x9abcdef0:32,er1) ;01776c3cc9509abcdef0 -+ xor.b @-er3,@(0xffff9abc:16,r2l.b) ;01776c3cd2509abc -+ xor.b @-er3,@(0xffff9abc:16,r2.w) ;01776c3ce2509abc -+ xor.b @-er3,@(0xffff9abc:16,er2.l) ;01776c3cf2509abc -+ xor.b @-er3,@(0x9abcdef0:32,r2l.b) ;01776c3cda509abcdef0 -+ xor.b @-er3,@(0x9abcdef0:32,r2.w) ;01776c3cea509abcdef0 -+ xor.b @-er3,@(0x9abcdef0:32,er2.l) ;01776c3cfa509abcdef0 -+ xor.b @-er3,@0xffff9abc:16 ;01776c3c40509abc -+ xor.b @-er3,@0x9abcdef0:32 ;01776c3c48509abcdef0 -+ -+ xor.b @er3+,@er1 ;01746c3c0150 -+ xor.b @er3+,@(3:2,er1) ;01746c3c3150 -+ xor.b @er3+,@-er1 ;01746c3cb150 -+ xor.b @er3+,@er1+ ;01746c3c8150 -+ xor.b @er3+,@er1- ;01746c3ca150 -+ xor.b @er3+,@+er1 ;01746c3c9150 -+ xor.b @er3+,@(0xffff9abc:16,er1) ;01746c3cc1509abc -+ xor.b @er3+,@(0x9abcdef0:32,er1) ;01746c3cc9509abcdef0 -+ xor.b @er3+,@(0xffff9abc:16,r2l.b) ;01746c3cd2509abc -+ xor.b @er3+,@(0xffff9abc:16,r2.w) ;01746c3ce2509abc -+ xor.b @er3+,@(0xffff9abc:16,er2.l) ;01746c3cf2509abc -+ xor.b @er3+,@(0x9abcdef0:32,r2l.b) ;01746c3cda509abcdef0 -+ xor.b @er3+,@(0x9abcdef0:32,r2.w) ;01746c3cea509abcdef0 -+ xor.b @er3+,@(0x9abcdef0:32,er2.l) ;01746c3cfa509abcdef0 -+ xor.b @er3+,@0xffff9abc:16 ;01746c3c40509abc -+ xor.b @er3+,@0x9abcdef0:32 ;01746c3c48509abcdef0 -+ -+ xor.b @er3-,@er1 ;01766c3c0150 -+ xor.b @er3-,@(3:2,er1) ;01766c3c3150 -+ xor.b @er3-,@-er1 ;01766c3cb150 -+ xor.b @er3-,@er1+ ;01766c3c8150 -+ xor.b @er3-,@er1- ;01766c3ca150 -+ xor.b @er3-,@+er1 ;01766c3c9150 -+ xor.b @er3-,@(0xffff9abc:16,er1) ;01766c3cc1509abc -+ xor.b @er3-,@(0x9abcdef0:32,er1) ;01766c3cc9509abcdef0 -+ xor.b @er3-,@(0xffff9abc:16,r2l.b) ;01766c3cd2509abc -+ xor.b @er3-,@(0xffff9abc:16,r2.w) ;01766c3ce2509abc -+ xor.b @er3-,@(0xffff9abc:16,er2.l) ;01766c3cf2509abc -+ xor.b @er3-,@(0x9abcdef0:32,r2l.b) ;01766c3cda509abcdef0 -+ xor.b @er3-,@(0x9abcdef0:32,r2.w) ;01766c3cea509abcdef0 -+ xor.b @er3-,@(0x9abcdef0:32,er2.l) ;01766c3cfa509abcdef0 -+ xor.b @er3-,@0xffff9abc:16 ;01766c3c40509abc -+ xor.b @er3-,@0x9abcdef0:32 ;01766c3c48509abcdef0 -+ -+ xor.b @+er3,@er1 ;01756c3c0150 -+ xor.b @+er3,@(3:2,er1) ;01756c3c3150 -+ xor.b @+er3,@-er1 ;01756c3cb150 -+ xor.b @+er3,@er1+ ;01756c3c8150 -+ xor.b @+er3,@er1- ;01756c3ca150 -+ xor.b @+er3,@+er1 ;01756c3c9150 -+ xor.b @+er3,@(0xffff9abc:16,er1) ;01756c3cc1509abc -+ xor.b @+er3,@(0x9abcdef0:32,er1) ;01756c3cc9509abcdef0 -+ xor.b @+er3,@(0xffff9abc:16,r2l.b) ;01756c3cd2509abc -+ xor.b @+er3,@(0xffff9abc:16,r2.w) ;01756c3ce2509abc -+ xor.b @+er3,@(0xffff9abc:16,er2.l) ;01756c3cf2509abc -+ xor.b @+er3,@(0x9abcdef0:32,r2l.b) ;01756c3cda509abcdef0 -+ xor.b @+er3,@(0x9abcdef0:32,r2.w) ;01756c3cea509abcdef0 -+ xor.b @+er3,@(0x9abcdef0:32,er2.l) ;01756c3cfa509abcdef0 -+ xor.b @+er3,@0xffff9abc:16 ;01756c3c40509abc -+ xor.b @+er3,@0x9abcdef0:32 ;01756c3c48509abcdef0 -+ -+ xor.b @(0x1234:16,er3),@er1 ;01746e3c12340150 -+ xor.b @(0x1234:16,er3),@(3:2,er1) ;01746e3c12343150 -+ xor.b @(0x1234:16,er3),@-er1 ;01746e3c1234b150 -+ xor.b @(0x1234:16,er3),@er1+ ;01746e3c12348150 -+ xor.b @(0x1234:16,er3),@er1- ;01746e3c1234a150 -+ xor.b @(0x1234:16,er3),@+er1 ;01746e3c12349150 -+ xor.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01746e3c1234c1509abc -+ xor.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01746e3c1234c9509abcdef0 -+ xor.b @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01746e3c1234d2509abc -+ xor.b @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01746e3c1234e2509abc -+ xor.b @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01746e3c1234f2509abc -+ xor.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01746e3c1234da509abcdef0 -+ xor.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01746e3c1234ea509abcdef0 -+ xor.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01746e3c1234fa509abcdef0 -+ xor.b @(0x1234:16,er3),@0xffff9abc:16 ;01746e3c123440509abc -+ xor.b @(0x1234:16,er3),@0x9abcdef0:32 ;01746e3c123448509abcdef0 -+ -+ xor.b @(0x12345678:32,er3),@er1 ;78346a2c123456780150 -+ xor.b @(0x12345678:32,er3),@(3:2,er1) ;78346a2c123456783150 -+ xor.b @(0x12345678:32,er3),@-er1 ;78346a2c12345678b150 -+ xor.b @(0x12345678:32,er3),@er1+ ;78346a2c123456788150 -+ xor.b @(0x12345678:32,er3),@er1- ;78346a2c12345678a150 -+ xor.b @(0x12345678:32,er3),@+er1 ;78346a2c123456789150 -+ xor.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346a2c12345678c1509abc -+ xor.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346a2c12345678c9509abcdef0 -+ xor.b @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346a2c12345678d2509abc -+ xor.b @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346a2c12345678e2509abc -+ xor.b @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346a2c12345678f2509abc -+ xor.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346a2c12345678da509abcdef0 -+ xor.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346a2c12345678ea509abcdef0 -+ xor.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346a2c12345678fa509abcdef0 -+ xor.b @(0x12345678:32,er3),@0xffff9abc:16 ;78346a2c1234567840509abc -+ xor.b @(0x12345678:32,er3),@0x9abcdef0:32 ;78346a2c1234567848509abcdef0 -+ -+ xor.b @(0x1234:16,r3l.b),@er1 ;01756e3c12340150 -+ xor.b @(0x1234:16,r3l.b),@(3:2,er1) ;01756e3c12343150 -+ xor.b @(0x1234:16,r3l.b),@-er1 ;01756e3c1234b150 -+ xor.b @(0x1234:16,r3l.b),@er1+ ;01756e3c12348150 -+ xor.b @(0x1234:16,r3l.b),@er1- ;01756e3c1234a150 -+ xor.b @(0x1234:16,r3l.b),@+er1 ;01756e3c12349150 -+ xor.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01756e3c1234c1509abc -+ xor.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01756e3c1234c9509abcdef0 -+ xor.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01756e3c1234d2509abc -+ xor.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01756e3c1234e2509abc -+ xor.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01756e3c1234f2509abc -+ xor.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01756e3c1234da509abcdef0 -+ xor.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01756e3c1234ea509abcdef0 -+ xor.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01756e3c1234fa509abcdef0 -+ xor.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;01756e3c123440509abc -+ xor.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01756e3c123448509abcdef0 -+ -+ xor.b @(0x1234:16,r3.w),@er1 ;01766e3c12340150 -+ xor.b @(0x1234:16,r3.w),@(3:2,er1) ;01766e3c12343150 -+ xor.b @(0x1234:16,r3.w),@-er1 ;01766e3c1234b150 -+ xor.b @(0x1234:16,r3.w),@er1+ ;01766e3c12348150 -+ xor.b @(0x1234:16,r3.w),@er1- ;01766e3c1234a150 -+ xor.b @(0x1234:16,r3.w),@+er1 ;01766e3c12349150 -+ xor.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01766e3c1234c1509abc -+ xor.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01766e3c1234c9509abcdef0 -+ xor.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01766e3c1234d2509abc -+ xor.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01766e3c1234e2509abc -+ xor.b @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01766e3c1234f2509abc -+ xor.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01766e3c1234da509abcdef0 -+ xor.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01766e3c1234ea509abcdef0 -+ xor.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01766e3c1234fa509abcdef0 -+ xor.b @(0x1234:16,r3.w),@0xffff9abc:16 ;01766e3c123440509abc -+ xor.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;01766e3c123448509abcdef0 -+ -+ xor.b @(0x1234:16,er3.l),@er1 ;01776e3c12340150 -+ xor.b @(0x1234:16,er3.l),@(3:2,er1) ;01776e3c12343150 -+ xor.b @(0x1234:16,er3.l),@-er1 ;01776e3c1234b150 -+ xor.b @(0x1234:16,er3.l),@er1+ ;01776e3c12348150 -+ xor.b @(0x1234:16,er3.l),@er1- ;01776e3c1234a150 -+ xor.b @(0x1234:16,er3.l),@+er1 ;01776e3c12349150 -+ xor.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01776e3c1234c1509abc -+ xor.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01776e3c1234c9509abcdef0 -+ xor.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01776e3c1234d2509abc -+ xor.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01776e3c1234e2509abc -+ xor.b @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01776e3c1234f2509abc -+ xor.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01776e3c1234da509abcdef0 -+ xor.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01776e3c1234ea509abcdef0 -+ xor.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01776e3c1234fa509abcdef0 -+ xor.b @(0x1234:16,er3.l),@0xffff9abc:16 ;01776e3c123440509abc -+ xor.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;01776e3c123448509abcdef0 -+ -+ xor.b @(0x12345678:32,r3l.b),@er1 ;78356a2c123456780150 -+ xor.b @(0x12345678:32,r3l.b),@(3:2,er1) ;78356a2c123456783150 -+ xor.b @(0x12345678:32,r3l.b),@-er1 ;78356a2c12345678b150 -+ xor.b @(0x12345678:32,r3l.b),@er1+ ;78356a2c123456788150 -+ xor.b @(0x12345678:32,r3l.b),@er1- ;78356a2c12345678a150 -+ xor.b @(0x12345678:32,r3l.b),@+er1 ;78356a2c123456789150 -+ xor.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356a2c12345678c1509abc -+ xor.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356a2c12345678c9509abcdef0 -+ xor.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356a2c12345678d2509abc -+ xor.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356a2c12345678e2509abc -+ xor.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356a2c12345678f2509abc -+ xor.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356a2c12345678da509abcdef0 -+ xor.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356a2c12345678ea509abcdef0 -+ xor.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356a2c12345678fa509abcdef0 -+ xor.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356a2c1234567840509abc -+ xor.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356a2c1234567848509abcdef0 -+ -+ xor.b @(0x12345678:32,r3.w),@er1 ;78366a2c123456780150 -+ xor.b @(0x12345678:32,r3.w),@(3:2,er1) ;78366a2c123456783150 -+ xor.b @(0x12345678:32,r3.w),@-er1 ;78366a2c12345678b150 -+ xor.b @(0x12345678:32,r3.w),@er1+ ;78366a2c123456788150 -+ xor.b @(0x12345678:32,r3.w),@er1- ;78366a2c12345678a150 -+ xor.b @(0x12345678:32,r3.w),@+er1 ;78366a2c123456789150 -+ xor.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366a2c12345678c1509abc -+ xor.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366a2c12345678c9509abcdef0 -+ xor.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366a2c12345678d2509abc -+ xor.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366a2c12345678e2509abc -+ xor.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366a2c12345678f2509abc -+ xor.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366a2c12345678da509abcdef0 -+ xor.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366a2c12345678ea509abcdef0 -+ xor.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366a2c12345678fa509abcdef0 -+ xor.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366a2c1234567840509abc -+ xor.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366a2c1234567848509abcdef0 -+ -+ xor.b @(0x12345678:32,er3.l),@er1 ;78376a2c123456780150 -+ xor.b @(0x12345678:32,er3.l),@(3:2,er1) ;78376a2c123456783150 -+ xor.b @(0x12345678:32,er3.l),@-er1 ;78376a2c12345678b150 -+ xor.b @(0x12345678:32,er3.l),@er1+ ;78376a2c123456788150 -+ xor.b @(0x12345678:32,er3.l),@er1- ;78376a2c12345678a150 -+ xor.b @(0x12345678:32,er3.l),@+er1 ;78376a2c123456789150 -+ xor.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376a2c12345678c1509abc -+ xor.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376a2c12345678c9509abcdef0 -+ xor.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376a2c12345678d2509abc -+ xor.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376a2c12345678e2509abc -+ xor.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376a2c12345678f2509abc -+ xor.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376a2c12345678da509abcdef0 -+ xor.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376a2c12345678ea509abcdef0 -+ xor.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376a2c12345678fa509abcdef0 -+ xor.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376a2c1234567840509abc -+ xor.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376a2c1234567848509abcdef0 -+ -+ xor.b @0x1234:16,@er1 ;6a1512340150 -+ xor.b @0x1234:16,@(3:2,er1) ;6a1512343150 -+ xor.b @0x1234:16,@-er1 ;6a151234b150 -+ xor.b @0x1234:16,@er1+ ;6a1512348150 -+ xor.b @0x1234:16,@er1- ;6a151234a150 -+ xor.b @0x1234:16,@+er1 ;6a1512349150 -+ xor.b @0x1234:16,@(0xffff9abc:16,er1) ;6a151234c1509abc -+ xor.b @0x1234:16,@(0x9abcdef0:32,er1) ;6a151234c9509abcdef0 -+ xor.b @0x1234:16,@(0xffff9abc:16,r2l.b) ;6a151234d2509abc -+ xor.b @0x1234:16,@(0xffff9abc:16,r2.w) ;6a151234e2509abc -+ xor.b @0x1234:16,@(0xffff9abc:16,er2.l) ;6a151234f2509abc -+ xor.b @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6a151234da509abcdef0 -+ xor.b @0x1234:16,@(0x9abcdef0:32,r2.w) ;6a151234ea509abcdef0 -+ xor.b @0x1234:16,@(0x9abcdef0:32,er2.l) ;6a151234fa509abcdef0 -+ xor.b @0x1234:16,@0xffff9abc:16 ;6a15123440509abc -+ xor.b @0x1234:16,@0x9abcdef0:32 ;6a15123448509abcdef0 -+ -+ xor.b @0x12345678:32,@er1 ;6a35123456780150 -+ xor.b @0x12345678:32,@(3:2,er1) ;6a35123456783150 -+ xor.b @0x12345678:32,@-er1 ;6a3512345678b150 -+ xor.b @0x12345678:32,@er1+ ;6a35123456788150 -+ xor.b @0x12345678:32,@er1- ;6a3512345678a150 -+ xor.b @0x12345678:32,@+er1 ;6a35123456789150 -+ xor.b @0x12345678:32,@(0xffff9abc:16,er1) ;6a3512345678c1509abc -+ xor.b @0x12345678:32,@(0x9abcdef0:32,er1) ;6a3512345678c9509abcdef0 -+ xor.b @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6a3512345678d2509abc -+ xor.b @0x12345678:32,@(0xffff9abc:16,r2.w) ;6a3512345678e2509abc -+ xor.b @0x12345678:32,@(0xffff9abc:16,er2.l) ;6a3512345678f2509abc -+ xor.b @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6a3512345678da509abcdef0 -+ xor.b @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6a3512345678ea509abcdef0 -+ xor.b @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6a3512345678fa509abcdef0 -+ xor.b @0x12345678:32,@0xffff9abc:16 ;6a351234567840509abc -+ xor.b @0x12345678:32,@0x9abcdef0:32 ;6a351234567848509abcdef0 -+ -+ xor.w #0x1234:16,r1 ;79511234 -+ xor.w #0x1234:16,@er1 ;015e01501234 -+ xor.w #0x1234:16,@(0x6:2,er1) ;015e31501234 -+ xor.w #0x1234:16,@er1+ ;015e81501234 -+ xor.w #0x1234:16,@-er1 ;015eb1501234 -+ xor.w #0x1234:16,@+er1 ;015e91501234 -+ xor.w #0x1234:16,@er1- ;015ea1501234 -+ xor.w #0x1234:16,@(0xffff9abc:16,er1) ;015ec1509abc1234 -+ xor.w #0x1234:16,@(0x9abcdef0:32,er1) ;015ec9509abcdef01234 -+ xor.w #0x1234:16,@(0xffff9abc:16,r2l.b) ;015ed2509abc1234 -+ xor.w #0x1234:16,@(0xffff9abc:16,r2.w) ;015ee2509abc1234 -+ xor.w #0x1234:16,@(0xffff9abc:16,er2.l) ;015ef2509abc1234 -+ xor.w #0x1234:16,@(0x9abcdef0:32,r2l.b) ;015eda509abcdef01234 -+ xor.w #0x1234:16,@(0x9abcdef0:32,r2.w) ;015eea509abcdef01234 -+ xor.w #0x1234:16,@(0x9abcdef0:32,er2.l) ;015efa509abcdef01234 -+ xor.w #0x1234:16,@0xffff9abc:16 ;015e40509abc1234 -+ xor.w #0x1234:16,@0x9abcdef0:32 ;015e48509abcdef01234 -+ -+ xor.w r3,r1 ;6531 -+ -+ xor.w r3,@er1 ;7d906530 -+ xor.w r3,@(0x6:2,er1) ;01593153 -+ xor.w r3,@-er1 ;0159b153 -+ xor.w r3,@er1+ ;01598153 -+ xor.w r3,@er1- ;0159a153 -+ xor.w r3,@+er1 ;01599153 -+ xor.w r3,@(0x1234:16,er1) ;0159c1531234 -+ xor.w r3,@(0x12345678:32,er1) ;0159c95312345678 -+ xor.w r3,@(0x1234:16,r2l.b) ;0159d2531234 -+ xor.w r3,@(0x1234:16,r2.w) ;0159e2531234 -+ xor.w r3,@(0x1234:16,er2.l) ;0159f2531234 -+ xor.w r3,@(0x12345678:32,r2l.b) ;0159da5312345678 -+ xor.w r3,@(0x12345678:32,r2.w) ;0159ea5312345678 -+ xor.w r3,@(0x12345678:32,er2.l) ;0159fa5312345678 -+ xor.w r3,@0x1234:16 ;6b1812346530 -+ xor.w r3,@0x12345678:32 ;6b38123456786530 -+ -+ xor.w @er3,r1 ;7cb06501 -+ xor.w @(0x6:2,er3),r1 ;015a3351 -+ xor.w @er3+,r1 ;015a8351 -+ xor.w @-er3,r1 ;015ab351 -+ xor.w @+er3,r1 ;015a9351 -+ xor.w @er3-,r1 ;015aa351 -+ xor.w @(0x1234:16,er1),r1 ;015ac1511234 -+ xor.w @(0x12345678:32,er1),r1 ;015ac95112345678 -+ xor.w @(0x1234:16,r2l.b),r1 ;015ad2511234 -+ xor.w @(0x1234:16,r2.w),r1 ;015ae2511234 -+ xor.w @(0x1234:16,er2.l),r1 ;015af2511234 -+ xor.w @(0x12345678:32,r2l.b),r1 ;015ada5112345678 -+ xor.w @(0x12345678:32,r2.w),r1 ;015aea5112345678 -+ xor.w @(0x12345678:32,er2.l),r1 ;015afa5112345678 -+ xor.w @0x1234:16,r1 ;6b1012346501 -+ xor.w @0x12345678:32,r1 ;6b30123456786501 -+ -+ xor.w @er3,@er1 ;7cb50150 -+ xor.w @er3,@(6:2,er1) ;7cb53150 -+ xor.w @er3,@-er1 ;7cb5b150 -+ xor.w @er3,@er1+ ;7cb58150 -+ xor.w @er3,@er1- ;7cb5a150 -+ xor.w @er3,@+er1 ;7cb59150 -+ xor.w @er3,@(0xffff9abc:16,er1) ;7cb5c1509abc -+ xor.w @er3,@(0x9abcdef0:32,er1) ;7cb5c9509abcdef0 -+ xor.w @er3,@(0xffff9abc:16,r2l.b) ;7cb5d2509abc -+ xor.w @er3,@(0xffff9abc:16,r2.w) ;7cb5e2509abc -+ xor.w @er3,@(0xffff9abc:16,er2.l) ;7cb5f2509abc -+ xor.w @er3,@(0x9abcdef0:32,r2l.b) ;7cb5da509abcdef0 -+ xor.w @er3,@(0x9abcdef0:32,r2.w) ;7cb5ea509abcdef0 -+ xor.w @er3,@(0x9abcdef0:32,er2.l) ;7cb5fa509abcdef0 -+ xor.w @er3,@0xffff9abc:16 ;7cb540509abc -+ xor.w @er3,@0x9abcdef0:32 ;7cb548509abcdef0 -+ -+ xor.w @-er3,@er1 ;01576d3c0150 -+ xor.w @-er3,@(6:2,er1) ;01576d3c3150 -+ xor.w @-er3,@-er1 ;01576d3cb150 -+ xor.w @-er3,@er1+ ;01576d3c8150 -+ xor.w @-er3,@er1- ;01576d3ca150 -+ xor.w @-er3,@+er1 ;01576d3c9150 -+ xor.w @-er3,@(0xffff9abc:16,er1) ;01576d3cc1509abc -+ xor.w @-er3,@(0x9abcdef0:32,er1) ;01576d3cc9509abcdef0 -+ xor.w @-er3,@(0xffff9abc:16,r2l.b) ;01576d3cd2509abc -+ xor.w @-er3,@(0xffff9abc:16,r2.w) ;01576d3ce2509abc -+ xor.w @-er3,@(0xffff9abc:16,er2.l) ;01576d3cf2509abc -+ xor.w @-er3,@(0x9abcdef0:32,r2l.b) ;01576d3cda509abcdef0 -+ xor.w @-er3,@(0x9abcdef0:32,r2.w) ;01576d3cea509abcdef0 -+ xor.w @-er3,@(0x9abcdef0:32,er2.l) ;01576d3cfa509abcdef0 -+ xor.w @-er3,@0xffff9abc:16 ;01576d3c40509abc -+ xor.w @-er3,@0x9abcdef0:32 ;01576d3c48509abcdef0 -+ -+ xor.w @er3+,@er1 ;01546d3c0150 -+ xor.w @er3+,@(6:2,er1) ;01546d3c3150 -+ xor.w @er3+,@-er1 ;01546d3cb150 -+ xor.w @er3+,@er1+ ;01546d3c8150 -+ xor.w @er3+,@er1- ;01546d3ca150 -+ xor.w @er3+,@+er1 ;01546d3c9150 -+ xor.w @er3+,@(0xffff9abc:16,er1) ;01546d3cc1509abc -+ xor.w @er3+,@(0x9abcdef0:32,er1) ;01546d3cc9509abcdef0 -+ xor.w @er3+,@(0xffff9abc:16,r2l.b) ;01546d3cd2509abc -+ xor.w @er3+,@(0xffff9abc:16,r2.w) ;01546d3ce2509abc -+ xor.w @er3+,@(0xffff9abc:16,er2.l) ;01546d3cf2509abc -+ xor.w @er3+,@(0x9abcdef0:32,r2l.b) ;01546d3cda509abcdef0 -+ xor.w @er3+,@(0x9abcdef0:32,r2.w) ;01546d3cea509abcdef0 -+ xor.w @er3+,@(0x9abcdef0:32,er2.l) ;01546d3cfa509abcdef0 -+ xor.w @er3+,@0xffff9abc:16 ;01546d3c40509abc -+ xor.w @er3+,@0x9abcdef0:32 ;01546d3c48509abcdef0 -+ -+ xor.w @er3-,@er1 ;01566d3c0150 -+ xor.w @er3-,@(6:2,er1) ;01566d3c3150 -+ xor.w @er3-,@-er1 ;01566d3cb150 -+ xor.w @er3-,@er1+ ;01566d3c8150 -+ xor.w @er3-,@er1- ;01566d3ca150 -+ xor.w @er3-,@+er1 ;01566d3c9150 -+ xor.w @er3-,@(0xffff9abc:16,er1) ;01566d3cc1509abc -+ xor.w @er3-,@(0x9abcdef0:32,er1) ;01566d3cc9509abcdef0 -+ xor.w @er3-,@(0xffff9abc:16,r2l.b) ;01566d3cd2509abc -+ xor.w @er3-,@(0xffff9abc:16,r2.w) ;01566d3ce2509abc -+ xor.w @er3-,@(0xffff9abc:16,er2.l) ;01566d3cf2509abc -+ xor.w @er3-,@(0x9abcdef0:32,r2l.b) ;01566d3cda509abcdef0 -+ xor.w @er3-,@(0x9abcdef0:32,r2.w) ;01566d3cea509abcdef0 -+ xor.w @er3-,@(0x9abcdef0:32,er2.l) ;01566d3cfa509abcdef0 -+ xor.w @er3-,@0xffff9abc:16 ;01566d3c40509abc -+ xor.w @er3-,@0x9abcdef0:32 ;01566d3c48509abcdef0 -+ -+ xor.w @+er3,@er1 ;01556d3c0150 -+ xor.w @+er3,@(6:2,er1) ;01556d3c3150 -+ xor.w @+er3,@-er1 ;01556d3cb150 -+ xor.w @+er3,@er1+ ;01556d3c8150 -+ xor.w @+er3,@er1- ;01556d3ca150 -+ xor.w @+er3,@+er1 ;01556d3c9150 -+ xor.w @+er3,@(0xffff9abc:16,er1) ;01556d3cc1509abc -+ xor.w @+er3,@(0x9abcdef0:32,er1) ;01556d3cc9509abcdef0 -+ xor.w @+er3,@(0xffff9abc:16,r2l.b) ;01556d3cd2509abc -+ xor.w @+er3,@(0xffff9abc:16,r2.w) ;01556d3ce2509abc -+ xor.w @+er3,@(0xffff9abc:16,er2.l) ;01556d3cf2509abc -+ xor.w @+er3,@(0x9abcdef0:32,r2l.b) ;01556d3cda509abcdef0 -+ xor.w @+er3,@(0x9abcdef0:32,r2.w) ;01556d3cea509abcdef0 -+ xor.w @+er3,@(0x9abcdef0:32,er2.l) ;01556d3cfa509abcdef0 -+ xor.w @+er3,@0xffff9abc:16 ;01556d3c40509abc -+ xor.w @+er3,@0x9abcdef0:32 ;01556d3c48509abcdef0 -+ -+ xor.w @(0x1234:16,er3),@er1 ;01546f3c12340150 -+ xor.w @(0x1234:16,er3),@(6:2,er1) ;01546f3c12343150 -+ xor.w @(0x1234:16,er3),@-er1 ;01546f3c1234b150 -+ xor.w @(0x1234:16,er3),@er1+ ;01546f3c12348150 -+ xor.w @(0x1234:16,er3),@er1- ;01546f3c1234a150 -+ xor.w @(0x1234:16,er3),@+er1 ;01546f3c12349150 -+ xor.w @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01546f3c1234c1509abc -+ xor.w @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01546f3c1234c9509abcdef0 -+ xor.w @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01546f3c1234d2509abc -+ xor.w @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01546f3c1234e2509abc -+ xor.w @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01546f3c1234f2509abc -+ xor.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01546f3c1234da509abcdef0 -+ xor.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01546f3c1234ea509abcdef0 -+ xor.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01546f3c1234fa509abcdef0 -+ xor.w @(0x1234:16,er3),@0xffff9abc:16 ;01546f3c123440509abc -+ xor.w @(0x1234:16,er3),@0x9abcdef0:32 ;01546f3c123448509abcdef0 -+ -+ xor.w @(0x12345678:32,er3),@er1 ;78346b2c123456780150 -+ xor.w @(0x12345678:32,er3),@(6:2,er1) ;78346b2c123456783150 -+ xor.w @(0x12345678:32,er3),@-er1 ;78346b2c12345678b150 -+ xor.w @(0x12345678:32,er3),@er1+ ;78346b2c123456788150 -+ xor.w @(0x12345678:32,er3),@er1- ;78346b2c12345678a150 -+ xor.w @(0x12345678:32,er3),@+er1 ;78346b2c123456789150 -+ xor.w @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346b2c12345678c1509abc -+ xor.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346b2c12345678c9509abcdef0 -+ xor.w @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346b2c12345678d2509abc -+ xor.w @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346b2c12345678e2509abc -+ xor.w @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346b2c12345678f2509abc -+ xor.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346b2c12345678da509abcdef0 -+ xor.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346b2c12345678ea509abcdef0 -+ xor.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346b2c12345678fa509abcdef0 -+ xor.w @(0x12345678:32,er3),@0xffff9abc:16 ;78346b2c1234567840509abc -+ xor.w @(0x12345678:32,er3),@0x9abcdef0:32 ;78346b2c1234567848509abcdef0 -+ -+ xor.w @(0x1234:16,r3l.b),@er1 ;01556f3c12340150 -+ xor.w @(0x1234:16,r3l.b),@(6:2,er1) ;01556f3c12343150 -+ xor.w @(0x1234:16,r3l.b),@-er1 ;01556f3c1234b150 -+ xor.w @(0x1234:16,r3l.b),@er1+ ;01556f3c12348150 -+ xor.w @(0x1234:16,r3l.b),@er1- ;01556f3c1234a150 -+ xor.w @(0x1234:16,r3l.b),@+er1 ;01556f3c12349150 -+ xor.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01556f3c1234c1509abc -+ xor.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01556f3c1234c9509abcdef0 -+ xor.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01556f3c1234d2509abc -+ xor.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01556f3c1234e2509abc -+ xor.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01556f3c1234f2509abc -+ xor.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01556f3c1234da509abcdef0 -+ xor.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01556f3c1234ea509abcdef0 -+ xor.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01556f3c1234fa509abcdef0 -+ xor.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;01556f3c123440509abc -+ xor.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01556f3c123448509abcdef0 -+ -+ xor.w @(0x1234:16,r3.w),@er1 ;01566f3c12340150 -+ xor.w @(0x1234:16,r3.w),@(6:2,er1) ;01566f3c12343150 -+ xor.w @(0x1234:16,r3.w),@-er1 ;01566f3c1234b150 -+ xor.w @(0x1234:16,r3.w),@er1+ ;01566f3c12348150 -+ xor.w @(0x1234:16,r3.w),@er1- ;01566f3c1234a150 -+ xor.w @(0x1234:16,r3.w),@+er1 ;01566f3c12349150 -+ xor.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01566f3c1234c1509abc -+ xor.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01566f3c1234c9509abcdef0 -+ xor.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01566f3c1234d2509abc -+ xor.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01566f3c1234e2509abc -+ xor.w @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01566f3c1234f2509abc -+ xor.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01566f3c1234da509abcdef0 -+ xor.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01566f3c1234ea509abcdef0 -+ xor.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01566f3c1234fa509abcdef0 -+ xor.w @(0x1234:16,r3.w),@0xffff9abc:16 ;01566f3c123440509abc -+ xor.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;01566f3c123448509abcdef0 -+ -+ xor.w @(0x1234:16,er3.l),@er1 ;01576f3c12340150 -+ xor.w @(0x1234:16,er3.l),@(6:2,er1) ;01576f3c12343150 -+ xor.w @(0x1234:16,er3.l),@-er1 ;01576f3c1234b150 -+ xor.w @(0x1234:16,er3.l),@er1+ ;01576f3c12348150 -+ xor.w @(0x1234:16,er3.l),@er1- ;01576f3c1234a150 -+ xor.w @(0x1234:16,er3.l),@+er1 ;01576f3c12349150 -+ xor.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01576f3c1234c1509abc -+ xor.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01576f3c1234c9509abcdef0 -+ xor.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01576f3c1234d2509abc -+ xor.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01576f3c1234e2509abc -+ xor.w @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01576f3c1234f2509abc -+ xor.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01576f3c1234da509abcdef0 -+ xor.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01576f3c1234ea509abcdef0 -+ xor.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01576f3c1234fa509abcdef0 -+ xor.w @(0x1234:16,er3.l),@0xffff9abc:16 ;01576f3c123440509abc -+ xor.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;01576f3c123448509abcdef0 -+ -+ xor.w @(0x12345678:32,r3l.b),@er1 ;78356b2c123456780150 -+ xor.w @(0x12345678:32,r3l.b),@(6:2,er1) ;78356b2c123456783150 -+ xor.w @(0x12345678:32,r3l.b),@-er1 ;78356b2c12345678b150 -+ xor.w @(0x12345678:32,r3l.b),@er1+ ;78356b2c123456788150 -+ xor.w @(0x12345678:32,r3l.b),@er1- ;78356b2c12345678a150 -+ xor.w @(0x12345678:32,r3l.b),@+er1 ;78356b2c123456789150 -+ xor.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356b2c12345678c1509abc -+ xor.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356b2c12345678c9509abcdef0 -+ xor.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356b2c12345678d2509abc -+ xor.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356b2c12345678e2509abc -+ xor.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356b2c12345678f2509abc -+ xor.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356b2c12345678da509abcdef0 -+ xor.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356b2c12345678ea509abcdef0 -+ xor.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356b2c12345678fa509abcdef0 -+ xor.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356b2c1234567840509abc -+ xor.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356b2c1234567848509abcdef0 -+ -+ xor.w @(0x12345678:32,r3.w),@er1 ;78366b2c123456780150 -+ xor.w @(0x12345678:32,r3.w),@(6:2,er1) ;78366b2c123456783150 -+ xor.w @(0x12345678:32,r3.w),@-er1 ;78366b2c12345678b150 -+ xor.w @(0x12345678:32,r3.w),@er1+ ;78366b2c123456788150 -+ xor.w @(0x12345678:32,r3.w),@er1- ;78366b2c12345678a150 -+ xor.w @(0x12345678:32,r3.w),@+er1 ;78366b2c123456789150 -+ xor.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366b2c12345678c1509abc -+ xor.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366b2c12345678c9509abcdef0 -+ xor.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366b2c12345678d2509abc -+ xor.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366b2c12345678e2509abc -+ xor.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366b2c12345678f2509abc -+ xor.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366b2c12345678da509abcdef0 -+ xor.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366b2c12345678ea509abcdef0 -+ xor.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366b2c12345678fa509abcdef0 -+ xor.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366b2c1234567840509abc -+ xor.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366b2c1234567848509abcdef0 -+ -+ xor.w @(0x12345678:32,er3.l),@er1 ;78376b2c123456780150 -+ xor.w @(0x12345678:32,er3.l),@(6:2,er1) ;78376b2c123456783150 -+ xor.w @(0x12345678:32,er3.l),@-er1 ;78376b2c12345678b150 -+ xor.w @(0x12345678:32,er3.l),@er1+ ;78376b2c123456788150 -+ xor.w @(0x12345678:32,er3.l),@er1- ;78376b2c12345678a150 -+ xor.w @(0x12345678:32,er3.l),@+er1 ;78376b2c123456789150 -+ xor.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376b2c12345678c1509abc -+ xor.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376b2c12345678c9509abcdef0 -+ xor.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376b2c12345678d2509abc -+ xor.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376b2c12345678e2509abc -+ xor.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376b2c12345678f2509abc -+ xor.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376b2c12345678da509abcdef0 -+ xor.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376b2c12345678ea509abcdef0 -+ xor.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376b2c12345678fa509abcdef0 -+ xor.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376b2c1234567840509abc -+ xor.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376b2c1234567848509abcdef0 -+ -+ xor.w @0x1234:16,@er1 ;6b1512340150 -+ xor.w @0x1234:16,@(6:2,er1) ;6b1512343150 -+ xor.w @0x1234:16,@-er1 ;6b151234b150 -+ xor.w @0x1234:16,@er1+ ;6b1512348150 -+ xor.w @0x1234:16,@er1- ;6b151234a150 -+ xor.w @0x1234:16,@+er1 ;6b1512349150 -+ xor.w @0x1234:16,@(0xffff9abc:16,er1) ;6b151234c1509abc -+ xor.w @0x1234:16,@(0x9abcdef0:32,er1) ;6b151234c9509abcdef0 -+ xor.w @0x1234:16,@(0xffff9abc:16,r2l.b) ;6b151234d2509abc -+ xor.w @0x1234:16,@(0xffff9abc:16,r2.w) ;6b151234e2509abc -+ xor.w @0x1234:16,@(0xffff9abc:16,er2.l) ;6b151234f2509abc -+ xor.w @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6b151234da509abcdef0 -+ xor.w @0x1234:16,@(0x9abcdef0:32,r2.w) ;6b151234ea509abcdef0 -+ xor.w @0x1234:16,@(0x9abcdef0:32,er2.l) ;6b151234fa509abcdef0 -+ xor.w @0x1234:16,@0xffff9abc:16 ;6b15123440509abc -+ xor.w @0x1234:16,@0x9abcdef0:32 ;6b15123448509abcdef0 -+ -+ xor.w @0x12345678:32,@er1 ;6b35123456780150 -+ xor.w @0x12345678:32,@(6:2,er1) ;6b35123456783150 -+ xor.w @0x12345678:32,@-er1 ;6b3512345678b150 -+ xor.w @0x12345678:32,@er1+ ;6b35123456788150 -+ xor.w @0x12345678:32,@er1- ;6b3512345678a150 -+ xor.w @0x12345678:32,@+er1 ;6b35123456789150 -+ xor.w @0x12345678:32,@(0xffff9abc:16,er1) ;6b3512345678c1509abc -+ xor.w @0x12345678:32,@(0x9abcdef0:32,er1) ;6b3512345678c9509abcdef0 -+ xor.w @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6b3512345678d2509abc -+ xor.w @0x12345678:32,@(0xffff9abc:16,r2.w) ;6b3512345678e2509abc -+ xor.w @0x12345678:32,@(0xffff9abc:16,er2.l) ;6b3512345678f2509abc -+ xor.w @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6b3512345678da509abcdef0 -+ xor.w @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6b3512345678ea509abcdef0 -+ xor.w @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6b3512345678fa509abcdef0 -+ xor.w @0x12345678:32,@0xffff9abc:16 ;6b351234567840509abc -+ xor.w @0x12345678:32,@0x9abcdef0:32 ;6b351234567848509abcdef0 -+ -+ xor.l #0x12345678:32,er1 ;7a5112345678 -+ xor.l #0x1234:16,er1 ;7a591234 -+ xor.l #0x12345678:32,@er1 ;010e015812345678 -+ xor.l #0x12345678:32,@(0xc:2,er1) ;010e315812345678 -+ xor.l #0x12345678:32,@er1+ ;010e815812345678 -+ xor.l #0x12345678:32,@-er1 ;010eb15812345678 -+ xor.l #0x12345678:32,@+er1 ;010e915812345678 -+ xor.l #0x12345678:32,@er1- ;010ea15812345678 -+ xor.l #0x12345678:32,@(0xffff9abc:16,er1) ;010ec1589abc12345678 -+ xor.l #0x12345678:32,@(0x9abcdef0:32,er1) ;010ec9589abcdef012345678 -+ xor.l #0x12345678:32,@(0xffff9abc:16,r2l.b) ;010ed2589abc12345678 -+ xor.l #0x12345678:32,@(0xffff9abc:16,r2.w) ;010ee2589abc12345678 -+ xor.l #0x12345678:32,@(0xffff9abc:16,er2.l) ;010ef2589abc12345678 -+ xor.l #0x12345678:32,@(0x9abcdef0:32,r2l.b) ;010eda589abcdef012345678 -+ xor.l #0x12345678:32,@(0x9abcdef0:32,r2.w) ;010eea589abcdef012345678 -+ xor.l #0x12345678:32,@(0x9abcdef0:32,er2.l) ;010efa589abcdef012345678 -+ xor.l #0x12345678:32,@0xffff9abc:16 ;010e40589abc12345678 -+ xor.l #0x12345678:32,@0x9abcdef0:32 ;010e48589abcdef012345678 -+ xor.l #0x1234:16,@er1 ;010e01501234 -+ xor.l #0x1234:16,@(0xc:2,er1) ;010e31501234 -+ xor.l #0x1234:16,@er1+ ;010e81501234 -+ xor.l #0x1234:16,@-er1 ;010eb1501234 -+ xor.l #0x1234:16,@+er1 ;010e91501234 -+ xor.l #0x1234:16,@er1- ;010ea1501234 -+ xor.l #0x1234:16,@(0xffff9abc:16,er1) ;010ec1509abc1234 -+ xor.l #0x1234:16,@(0x9abcdef0:32,er1) ;010ec9509abcdef01234 -+ xor.l #0x1234:16,@(0xffff9abc:16,r2l.b) ;010ed2509abc1234 -+ xor.l #0x1234:16,@(0xffff9abc:16,r2.w) ;010ee2509abc1234 -+ xor.l #0x1234:16,@(0xffff9abc:16,er2.l) ;010ef2509abc1234 -+ xor.l #0x1234:16,@(0x9abcdef0:32,r2l.b) ;010eda509abcdef01234 -+ xor.l #0x1234:16,@(0x9abcdef0:32,r2.w) ;010eea509abcdef01234 -+ xor.l #0x1234:16,@(0x9abcdef0:32,er2.l) ;010efa509abcdef01234 -+ xor.l #0x1234:16,@0xffff9abc:16 ;010e40509abc1234 -+ xor.l #0x1234:16,@0x9abcdef0:32 ;010e48509abcdef01234 -+ -+ xor.l er3,er1 ;01f06531 -+ -+ xor.l er3,@er1 ;01090153 -+ xor.l er3,@(0xc:2,er1) ;01093153 -+ xor.l er3,@er1+ ;01098153 -+ xor.l er3,@-er1 ;0109b153 -+ xor.l er3,@+er1 ;01099153 -+ xor.l er3,@er1- ;0109a153 -+ xor.l er3,@(0x1234:16,er1) ;0109c1531234 -+ xor.l er3,@(0x12345678:32,er1) ;0109c95312345678 -+ xor.l er3,@(0x1234:16,r2l.b) ;0109d2531234 -+ xor.l er3,@(0x1234:16,r2.w) ;0109e2531234 -+ xor.l er3,@(0x1234:16,er2.l) ;0109f2531234 -+ xor.l er3,@(0x12345678:32,r2l.b) ;0109da5312345678 -+ xor.l er3,@(0x12345678:32,r2.w) ;0109ea5312345678 -+ xor.l er3,@(0x12345678:32,er2.l) ;0109fa5312345678 -+ xor.l er3,@0x1234:16 ;010940531234 -+ xor.l er3,@0x12345678:32 ;0109485312345678 -+ -+ xor.l @er3,er1 ;010a0351 -+ xor.l @(0xc:2,er3),er1 ;010a3351 -+ xor.l @er3+,er1 ;010a8351 -+ xor.l @-er3,er1 ;010ab351 -+ xor.l @+er3,er1 ;010a9351 -+ xor.l @er3-,er1 ;010aa351 -+ xor.l @(0x1234:16,er1),er1 ;010ac1511234 -+ xor.l @(0x12345678:32,er1),er1 ;010ac95112345678 -+ xor.l @(0x1234:16,r2l.b),er1 ;010ad2511234 -+ xor.l @(0x1234:16,r2.w),er1 ;010ae2511234 -+ xor.l @(0x1234:16,er2.l),er1 ;010af2511234 -+ xor.l @(0x12345678:32,r2l.b),er1 ;010ada5112345678 -+ xor.l @(0x12345678:32,r2.w),er1 ;010aea5112345678 -+ xor.l @(0x12345678:32,er2.l),er1 ;010afa5112345678 -+ xor.l @0x1234:16,er1 ;010a40511234 -+ xor.l @0x12345678:32,er1 ;010a485112345678 -+ -+ xor.l @er3,@er1 ;0104693c0150 -+ xor.l @er3,@(0xc:2,er1) ;0104693c3150 -+ xor.l @er3,@-er1 ;0104693cb150 -+ xor.l @er3,@er1+ ;0104693c8150 -+ xor.l @er3,@er1- ;0104693ca150 -+ xor.l @er3,@+er1 ;0104693c9150 -+ xor.l @er3,@(0xffff9abc:16,er1) ;0104693cc1509abc -+ xor.l @er3,@(0x9abcdef0:32,er1) ;0104693cc9509abcdef0 -+ xor.l @er3,@(0xffff9abc:16,r2l.b) ;0104693cd2509abc -+ xor.l @er3,@(0xffff9abc:16,r2.w) ;0104693ce2509abc -+ xor.l @er3,@(0xffff9abc:16,er2.l) ;0104693cf2509abc -+ xor.l @er3,@(0x9abcdef0:32,r2l.b) ;0104693cda509abcdef0 -+ xor.l @er3,@(0x9abcdef0:32,r2.w) ;0104693cea509abcdef0 -+ xor.l @er3,@(0x9abcdef0:32,er2.l) ;0104693cfa509abcdef0 -+ xor.l @er3,@0xffff9abc:16 ;0104693c40509abc -+ xor.l @er3,@0x9abcdef0:32 ;0104693c48509abcdef0 -+ -+ xor.l @(0xc:2,er3),@er1 ;0107693c0150 -+ xor.l @(0xc:2,er3),@(0xc:2,er1) ;0107693c3150 -+ xor.l @(0xc:2,er3),@-er1 ;0107693cb150 -+ xor.l @(0xc:2,er3),@er1+ ;0107693c8150 -+ xor.l @(0xc:2,er3),@er1- ;0107693ca150 -+ xor.l @(0xc:2,er3),@+er1 ;0107693c9150 -+ xor.l @(0xc:2,er3),@(0xffff9abc:16,er1) ;0107693cc1509abc -+ xor.l @(0xc:2,er3),@(0x9abcdef0:32,er1) ;0107693cc9509abcdef0 -+ xor.l @(0xc:2,er3),@(0xffff9abc:16,r2l.b) ;0107693cd2509abc -+ xor.l @(0xc:2,er3),@(0xffff9abc:16,r2.w) ;0107693ce2509abc -+ xor.l @(0xc:2,er3),@(0xffff9abc:16,er2.l) ;0107693cf2509abc -+ xor.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b) ;0107693cda509abcdef0 -+ xor.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w) ;0107693cea509abcdef0 -+ xor.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l) ;0107693cfa509abcdef0 -+ xor.l @(0xc:2,er3),@0xffff9abc:16 ;0107693c40509abc -+ xor.l @(0xc:2,er3),@0x9abcdef0:32 ;0107693c48509abcdef0 -+ -+ xor.l @-er3,@er1 ;01076d3c0150 -+ xor.l @-er3,@(0xc:2,er1) ;01076d3c3150 -+ xor.l @-er3,@-er1 ;01076d3cb150 -+ xor.l @-er3,@er1+ ;01076d3c8150 -+ xor.l @-er3,@er1- ;01076d3ca150 -+ xor.l @-er3,@+er1 ;01076d3c9150 -+ xor.l @-er3,@(0xffff9abc:16,er1) ;01076d3cc1509abc -+ xor.l @-er3,@(0x9abcdef0:32,er1) ;01076d3cc9509abcdef0 -+ xor.l @-er3,@(0xffff9abc:16,r2l.b) ;01076d3cd2509abc -+ xor.l @-er3,@(0xffff9abc:16,r2.w) ;01076d3ce2509abc -+ xor.l @-er3,@(0xffff9abc:16,er2.l) ;01076d3cf2509abc -+ xor.l @-er3,@(0x9abcdef0:32,r2l.b) ;01076d3cda509abcdef0 -+ xor.l @-er3,@(0x9abcdef0:32,r2.w) ;01076d3cea509abcdef0 -+ xor.l @-er3,@(0x9abcdef0:32,er2.l) ;01076d3cfa509abcdef0 -+ xor.l @-er3,@0xffff9abc:16 ;01076d3c40509abc -+ xor.l @-er3,@0x9abcdef0:32 ;01076d3c48509abcdef0 -+ -+ xor.l @er3+,@er1 ;01046d3c0150 -+ xor.l @er3+,@(0xc:2,er1) ;01046d3c3150 -+ xor.l @er3+,@-er1 ;01046d3cb150 -+ xor.l @er3+,@er1+ ;01046d3c8150 -+ xor.l @er3+,@er1- ;01046d3ca150 -+ xor.l @er3+,@+er1 ;01046d3c9150 -+ xor.l @er3+,@(0xffff9abc:16,er1) ;01046d3cc1509abc -+ xor.l @er3+,@(0x9abcdef0:32,er1) ;01046d3cc9509abcdef0 -+ xor.l @er3+,@(0xffff9abc:16,r2l.b) ;01046d3cd2509abc -+ xor.l @er3+,@(0xffff9abc:16,r2.w) ;01046d3ce2509abc -+ xor.l @er3+,@(0xffff9abc:16,er2.l) ;01046d3cf2509abc -+ xor.l @er3+,@(0x9abcdef0:32,r2l.b) ;01046d3cda509abcdef0 -+ xor.l @er3+,@(0x9abcdef0:32,r2.w) ;01046d3cea509abcdef0 -+ xor.l @er3+,@(0x9abcdef0:32,er2.l) ;01046d3cfa509abcdef0 -+ xor.l @er3+,@0xffff9abc:16 ;01046d3c40509abc -+ xor.l @er3+,@0x9abcdef0:32 ;01046d3c48509abcdef0 -+ -+ xor.l @er3-,@er1 ;01066d3c0150 -+ xor.l @er3-,@(0xc:2,er1) ;01066d3c3150 -+ xor.l @er3-,@-er1 ;01066d3cb150 -+ xor.l @er3-,@er1+ ;01066d3c8150 -+ xor.l @er3-,@er1- ;01066d3ca150 -+ xor.l @er3-,@+er1 ;01066d3c9150 -+ xor.l @er3-,@(0xffff9abc:16,er1) ;01066d3cc1509abc -+ xor.l @er3-,@(0x9abcdef0:32,er1) ;01066d3cc9509abcdef0 -+ xor.l @er3-,@(0xffff9abc:16,r2l.b) ;01066d3cd2509abc -+ xor.l @er3-,@(0xffff9abc:16,r2.w) ;01066d3ce2509abc -+ xor.l @er3-,@(0xffff9abc:16,er2.l) ;01066d3cf2509abc -+ xor.l @er3-,@(0x9abcdef0:32,r2l.b) ;01066d3cda509abcdef0 -+ xor.l @er3-,@(0x9abcdef0:32,r2.w) ;01066d3cea509abcdef0 -+ xor.l @er3-,@(0x9abcdef0:32,er2.l) ;01066d3cfa509abcdef0 -+ xor.l @er3-,@0xffff9abc:16 ;01066d3c40509abc -+ xor.l @er3-,@0x9abcdef0:32 ;01066d3c48509abcdef0 -+ -+ xor.l @+er3,@er1 ;01056d3c0150 -+ xor.l @+er3,@(0xc:2,er1) ;01056d3c3150 -+ xor.l @+er3,@-er1 ;01056d3cb150 -+ xor.l @+er3,@er1+ ;01056d3c8150 -+ xor.l @+er3,@er1- ;01056d3ca150 -+ xor.l @+er3,@+er1 ;01056d3c9150 -+ xor.l @+er3,@(0xffff9abc:16,er1) ;01056d3cc1509abc -+ xor.l @+er3,@(0x9abcdef0:32,er1) ;01056d3cc9509abcdef0 -+ xor.l @+er3,@(0xffff9abc:16,r2l.b) ;01056d3cd2509abc -+ xor.l @+er3,@(0xffff9abc:16,r2.w) ;01056d3ce2509abc -+ xor.l @+er3,@(0xffff9abc:16,er2.l) ;01056d3cf2509abc -+ xor.l @+er3,@(0x9abcdef0:32,r2l.b) ;01056d3cda509abcdef0 -+ xor.l @+er3,@(0x9abcdef0:32,r2.w) ;01056d3cea509abcdef0 -+ xor.l @+er3,@(0x9abcdef0:32,er2.l) ;01056d3cfa509abcdef0 -+ xor.l @+er3,@0xffff9abc:16 ;01056d3c40509abc -+ xor.l @+er3,@0x9abcdef0:32 ;01056d3c48509abcdef0 -+ -+ xor.l @(0x1234:16,er3),@er1 ;01046f3c12340150 -+ xor.l @(0x1234:16,er3),@(0xc:2,er1) ;01046f3c12343150 -+ xor.l @(0x1234:16,er3),@-er1 ;01046f3c1234b150 -+ xor.l @(0x1234:16,er3),@er1+ ;01046f3c12348150 -+ xor.l @(0x1234:16,er3),@er1- ;01046f3c1234a150 -+ xor.l @(0x1234:16,er3),@+er1 ;01046f3c12349150 -+ xor.l @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01046f3c1234c1509abc -+ xor.l @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01046f3c1234c9509abcdef0 -+ xor.l @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01046f3c1234d2509abc -+ xor.l @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01046f3c1234e2509abc -+ xor.l @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01046f3c1234f2509abc -+ xor.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01046f3c1234da509abcdef0 -+ xor.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01046f3c1234ea509abcdef0 -+ xor.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01046f3c1234fa509abcdef0 -+ xor.l @(0x1234:16,er3),@0xffff9abc:16 ;01046f3c123440509abc -+ xor.l @(0x1234:16,er3),@0x9abcdef0:32 ;01046f3c123448509abcdef0 -+ -+ xor.l @(0x12345678:32,er3),@er1 ;78b46b2c123456780150 -+ xor.l @(0x12345678:32,er3),@(0xc:2,er1) ;78b46b2c123456783150 -+ xor.l @(0x12345678:32,er3),@-er1 ;78b46b2c12345678b150 -+ xor.l @(0x12345678:32,er3),@er1+ ;78b46b2c123456788150 -+ xor.l @(0x12345678:32,er3),@er1- ;78b46b2c12345678a150 -+ xor.l @(0x12345678:32,er3),@+er1 ;78b46b2c123456789150 -+ xor.l @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78b46b2c12345678c1509abc -+ xor.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78b46b2c12345678c9509abcdef0 -+ xor.l @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78b46b2c12345678d2509abc -+ xor.l @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78b46b2c12345678e2509abc -+ xor.l @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78b46b2c12345678f2509abc -+ xor.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78b46b2c12345678da509abcdef0 -+ xor.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78b46b2c12345678ea509abcdef0 -+ xor.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78b46b2c12345678fa509abcdef0 -+ xor.l @(0x12345678:32,er3),@0xffff9abc:16 ;78b46b2c1234567840509abc -+ xor.l @(0x12345678:32,er3),@0x9abcdef0:32 ;78b46b2c1234567848509abcdef0 -+ -+ xor.l @(0x1234:16,r3l.b),@er1 ;01056f3c12340150 -+ xor.l @(0x1234:16,r3l.b),@(0xc:2,er1) ;01056f3c12343150 -+ xor.l @(0x1234:16,r3l.b),@-er1 ;01056f3c1234b150 -+ xor.l @(0x1234:16,r3l.b),@er1+ ;01056f3c12348150 -+ xor.l @(0x1234:16,r3l.b),@er1- ;01056f3c1234a150 -+ xor.l @(0x1234:16,r3l.b),@+er1 ;01056f3c12349150 -+ xor.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01056f3c1234c1509abc -+ xor.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01056f3c1234c9509abcdef0 -+ xor.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01056f3c1234d2509abc -+ xor.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01056f3c1234e2509abc -+ xor.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01056f3c1234f2509abc -+ xor.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01056f3c1234da509abcdef0 -+ xor.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01056f3c1234ea509abcdef0 -+ xor.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01056f3c1234fa509abcdef0 -+ xor.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;01056f3c123440509abc -+ xor.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01056f3c123448509abcdef0 -+ -+ xor.l @(0x1234:16,r3.w),@er1 ;01066f3c12340150 -+ xor.l @(0x1234:16,r3.w),@(0xc:2,er1) ;01066f3c12343150 -+ xor.l @(0x1234:16,r3.w),@-er1 ;01066f3c1234b150 -+ xor.l @(0x1234:16,r3.w),@er1+ ;01066f3c12348150 -+ xor.l @(0x1234:16,r3.w),@er1- ;01066f3c1234a150 -+ xor.l @(0x1234:16,r3.w),@+er1 ;01066f3c12349150 -+ xor.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01066f3c1234c1509abc -+ xor.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01066f3c1234c9509abcdef0 -+ xor.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01066f3c1234d2509abc -+ xor.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01066f3c1234e2509abc -+ xor.l @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01066f3c1234f2509abc -+ xor.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01066f3c1234da509abcdef0 -+ xor.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01066f3c1234ea509abcdef0 -+ xor.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01066f3c1234fa509abcdef0 -+ xor.l @(0x1234:16,r3.w),@0xffff9abc:16 ;01066f3c123440509abc -+ xor.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;01066f3c123448509abcdef0 -+ -+ xor.l @(0x1234:16,er3.l),@er1 ;01076f3c12340150 -+ xor.l @(0x1234:16,er3.l),@(0xc:2,er1) ;01076f3c12343150 -+ xor.l @(0x1234:16,er3.l),@-er1 ;01076f3c1234b150 -+ xor.l @(0x1234:16,er3.l),@er1+ ;01076f3c12348150 -+ xor.l @(0x1234:16,er3.l),@er1- ;01076f3c1234a150 -+ xor.l @(0x1234:16,er3.l),@+er1 ;01076f3c12349150 -+ xor.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01076f3c1234c1509abc -+ xor.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01076f3c1234c9509abcdef0 -+ xor.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01076f3c1234d2509abc -+ xor.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01076f3c1234e2509abc -+ xor.l @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01076f3c1234f2509abc -+ xor.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01076f3c1234da509abcdef0 -+ xor.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01076f3c1234ea509abcdef0 -+ xor.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01076f3c1234fa509abcdef0 -+ xor.l @(0x1234:16,er3.l),@0xffff9abc:16 ;01076f3c123440509abc -+ xor.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;01076f3c123448509abcdef0 -+ -+ xor.l @(0x12345678:32,r3l.b),@er1 ;78b56b2c123456780150 -+ xor.l @(0x12345678:32,r3l.b),@(0xc:2,er1) ;78b56b2c123456783150 -+ xor.l @(0x12345678:32,r3l.b),@-er1 ;78b56b2c12345678b150 -+ xor.l @(0x12345678:32,r3l.b),@er1+ ;78b56b2c123456788150 -+ xor.l @(0x12345678:32,r3l.b),@er1- ;78b56b2c12345678a150 -+ xor.l @(0x12345678:32,r3l.b),@+er1 ;78b56b2c123456789150 -+ xor.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78b56b2c12345678c1509abc -+ xor.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78b56b2c12345678c9509abcdef0 -+ xor.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78b56b2c12345678d2509abc -+ xor.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78b56b2c12345678e2509abc -+ xor.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78b56b2c12345678f2509abc -+ xor.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78b56b2c12345678da509abcdef0 -+ xor.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78b56b2c12345678ea509abcdef0 -+ xor.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78b56b2c12345678fa509abcdef0 -+ xor.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78b56b2c1234567840509abc -+ xor.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78b56b2c1234567848509abcdef0 -+ -+ xor.l @(0x12345678:32,r3.w),@er1 ;78b66b2c123456780150 -+ xor.l @(0x12345678:32,r3.w),@(0xc:2,er1) ;78b66b2c123456783150 -+ xor.l @(0x12345678:32,r3.w),@-er1 ;78b66b2c12345678b150 -+ xor.l @(0x12345678:32,r3.w),@er1+ ;78b66b2c123456788150 -+ xor.l @(0x12345678:32,r3.w),@er1- ;78b66b2c12345678a150 -+ xor.l @(0x12345678:32,r3.w),@+er1 ;78b66b2c123456789150 -+ xor.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78b66b2c12345678c1509abc -+ xor.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78b66b2c12345678c9509abcdef0 -+ xor.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78b66b2c12345678d2509abc -+ xor.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78b66b2c12345678e2509abc -+ xor.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78b66b2c12345678f2509abc -+ xor.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78b66b2c12345678da509abcdef0 -+ xor.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78b66b2c12345678ea509abcdef0 -+ xor.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78b66b2c12345678fa509abcdef0 -+ xor.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;78b66b2c1234567840509abc -+ xor.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78b66b2c1234567848509abcdef0 -+ -+ xor.l @(0x12345678:32,er3.l),@er1 ;78b76b2c123456780150 -+ xor.l @(0x12345678:32,er3.l),@(0xc:2,er1) ;78b76b2c123456783150 -+ xor.l @(0x12345678:32,er3.l),@-er1 ;78b76b2c12345678b150 -+ xor.l @(0x12345678:32,er3.l),@er1+ ;78b76b2c123456788150 -+ xor.l @(0x12345678:32,er3.l),@er1- ;78b76b2c12345678a150 -+ xor.l @(0x12345678:32,er3.l),@+er1 ;78b76b2c123456789150 -+ xor.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78b76b2c12345678c1509abc -+ xor.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78b76b2c12345678c9509abcdef0 -+ xor.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78b76b2c12345678d2509abc -+ xor.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78b76b2c12345678e2509abc -+ xor.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78b76b2c12345678f2509abc -+ xor.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78b76b2c12345678da509abcdef0 -+ xor.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78b76b2c12345678ea509abcdef0 -+ xor.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78b76b2c12345678fa509abcdef0 -+ xor.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;78b76b2c1234567840509abc -+ xor.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78b76b2c1234567848509abcdef0 -+ -+ xor.l @0x1234:16,@er1 ;01046b0c12340150 -+ xor.l @0x1234:16,@(0xc:2,er1) ;01046b0c12343150 -+ xor.l @0x1234:16,@-er1 ;01046b0c1234b150 -+ xor.l @0x1234:16,@er1+ ;01046b0c12348150 -+ xor.l @0x1234:16,@er1- ;01046b0c1234a150 -+ xor.l @0x1234:16,@+er1 ;01046b0c12349150 -+ xor.l @0x1234:16,@(0xffff9abc:16,er1) ;01046b0c1234c1509abc -+ xor.l @0x1234:16,@(0x9abcdef0:32,er1) ;01046b0c1234c9509abcdef0 -+ xor.l @0x1234:16,@(0xffff9abc:16,r2l.b) ;01046b0c1234d2509abc -+ xor.l @0x1234:16,@(0xffff9abc:16,r2.w) ;01046b0c1234e2509abc -+ xor.l @0x1234:16,@(0xffff9abc:16,er2.l) ;01046b0c1234f2509abc -+ xor.l @0x1234:16,@(0x9abcdef0:32,r2l.b) ;01046b0c1234da509abcdef0 -+ xor.l @0x1234:16,@(0x9abcdef0:32,r2.w) ;01046b0c1234ea509abcdef0 -+ xor.l @0x1234:16,@(0x9abcdef0:32,er2.l) ;01046b0c1234fa509abcdef0 -+ xor.l @0x1234:16,@0xffff9abc:16 ;01046b0c123440509abc -+ xor.l @0x1234:16,@0x9abcdef0:32 ;01046b0c123448509abcdef0 -+ -+ xor.l @0x12345678:32,@er1 ;01046b2c123456780150 -+ xor.l @0x12345678:32,@(0xc:2,er1) ;01046b2c123456783150 -+ xor.l @0x12345678:32,@-er1 ;01046b2c12345678b150 -+ xor.l @0x12345678:32,@er1+ ;01046b2c123456788150 -+ xor.l @0x12345678:32,@er1- ;01046b2c12345678a150 -+ xor.l @0x12345678:32,@+er1 ;01046b2c123456789150 -+ xor.l @0x12345678:32,@(0xffff9abc:16,er1) ;01046b2c12345678c1509abc -+ xor.l @0x12345678:32,@(0x9abcdef0:32,er1) ;01046b2c12345678c9509abcdef0 -+ xor.l @0x12345678:32,@(0xffff9abc:16,r2l.b) ;01046b2c12345678d2509abc -+ xor.l @0x12345678:32,@(0xffff9abc:16,r2.w) ;01046b2c12345678e2509abc -+ xor.l @0x12345678:32,@(0xffff9abc:16,er2.l) ;01046b2c12345678f2509abc -+ xor.l @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;01046b2c12345678da509abcdef0 -+ xor.l @0x12345678:32,@(0x9abcdef0:32,r2.w) ;01046b2c12345678ea509abcdef0 -+ xor.l @0x12345678:32,@(0x9abcdef0:32,er2.l) ;01046b2c12345678fa509abcdef0 -+ xor.l @0x12345678:32,@0xffff9abc:16 ;01046b2c1234567840509abc -+ xor.l @0x12345678:32,@0x9abcdef0:32 ;01046b2c1234567848509abcdef0 -+ -+ .end ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;log_1 ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ .h8300sx ++ .text ++_start: ++ xor.b #0x12:8,r1h ;d112 ++ xor.b #0x12:8,@er1 ;7d10d012 ++ xor.b #0x12:8,@(0x3:2,er1) ;01776818d012 ++ xor.b #0x12:8,@er1+ ;01746c18d012 ++ xor.b #0x12:8,@-er1 ;01776c18d012 ++ xor.b #0x12:8,@+er1 ;01756c18d012 ++ xor.b #0x12:8,@er1- ;01766c18d012 ++ xor.b #0x12:8,@(0x1234:16,er1) ;01746e181234d012 ++ xor.b #0x12:8,@(0x12345678:32,er1) ;78146a2812345678d012 ++ xor.b #0x12:8,@(0x1234:16,r2l.b) ;01756e281234d012 ++ xor.b #0x12:8,@(0x1234:16,r2.w) ;01766e281234d012 ++ xor.b #0x12:8,@(0x1234:16,er2.l) ;01776e281234d012 ++ xor.b #0x12:8,@(0x12345678:32,r2l.b) ;78256a2812345678d012 ++ xor.b #0x12:8,@(0x12345678:32,r2.w) ;78266a2812345678d012 ++ xor.b #0x12:8,@(0x12345678:32,er2.l) ;78276a2812345678d012 ++ xor.b #0x12:8,@0xffffff12:8 ;7f12d012 ++ xor.b #0x12:8,@0x1234:16 ;6a181234d012 ++ xor.b #0x12:8,@0x12345678:32 ;6a3812345678d012 ++ ++ xor.b r3h,r1h ;1531 ++ ++ xor.b r3h,@er1 ;7d101530 ++ xor.b r3h,@(0x3:2,er1) ;01793153 ++ xor.b r3h,@er1+ ;01798153 ++ xor.b r3h,@-er1 ;0179b153 ++ xor.b r3h,@+er1 ;01799153 ++ xor.b r3h,@er1- ;0179a153 ++ xor.b r3h,@(0x1234:16,er1) ;0179c1531234 ++ xor.b r3h,@(0x12345678:32,er1) ;0179c95312345678 ++ xor.b r3h,@(0x1234:16,r2l.b) ;0179d2531234 ++ xor.b r3h,@(0x1234:16,r2.w) ;0179e2531234 ++ xor.b r3h,@(0x1234:16,er2.l) ;0179f2531234 ++ xor.b r3h,@(0x12345678:32,r2l.b) ;0179da5312345678 ++ xor.b r3h,@(0x12345678:32,r2.w) ;0179ea5312345678 ++ xor.b r3h,@(0x12345678:32,er2.l) ;0179fa5312345678 ++ xor.b r3h,@0xffffff12:8 ;7f121530 ++ xor.b r3h,@0x1234:16 ;6a1812341530 ++ xor.b r3h,@0x12345678:32 ;6a38123456781530 ++ ++ xor.b @er3,r1h ;7c301501 ++ xor.b @(0x3:2,er3),r1h ;017a3351 ++ xor.b @er3+,r1h ;017a8351 ++ xor.b @-er3,r1h ;017ab351 ++ xor.b @+er3,r1h ;017a9351 ++ xor.b @er3-,r1h ;017aa351 ++ xor.b @(0x1234:16,er1),r1h ;017ac1511234 ++ xor.b @(0x12345678:32,er1),r1h ;017ac95112345678 ++ xor.b @(0x1234:16,r2l.b),r1h ;017ad2511234 ++ xor.b @(0x1234:16,r2.w),r1h ;017ae2511234 ++ xor.b @(0x1234:16,er2.l),r1h ;017af2511234 ++ xor.b @(0x12345678:32,r2l.b),r1h ;017ada5112345678 ++ xor.b @(0x12345678:32,r2.w),r1h ;017aea5112345678 ++ xor.b @(0x12345678:32,er2.l),r1h ;017afa5112345678 ++ xor.b @0xffffff12:8,r1h ;7e121501 ++ xor.b @0x1234:16,r1h ;6a1012341501 ++ xor.b @0x12345678:32,r1h ;6a30123456781501 ++ ++ xor.b @er3,@er1 ;7c350150 ++ xor.b @er3,@(3:2,er1) ;7c353150 ++ xor.b @er3,@-er1 ;7c35b150 ++ xor.b @er3,@er1+ ;7c358150 ++ xor.b @er3,@er1- ;7c35a150 ++ xor.b @er3,@+er1 ;7c359150 ++ xor.b @er3,@(0xffff9abc:16,er1) ;7c35c1509abc ++ xor.b @er3,@(0x9abcdef0:32,er1) ;7c35c9509abcdef0 ++ xor.b @er3,@(0xffff9abc:16,r2l.b) ;7c35d2509abc ++ xor.b @er3,@(0xffff9abc:16,r2.w) ;7c35e2509abc ++ xor.b @er3,@(0xffff9abc:16,er2.l) ;7c35f2509abc ++ xor.b @er3,@(0x9abcdef0:32,r2l.b) ;7c35da509abcdef0 ++ xor.b @er3,@(0x9abcdef0:32,r2.w) ;7c35ea509abcdef0 ++ xor.b @er3,@(0x9abcdef0:32,er2.l) ;7c35fa509abcdef0 ++ xor.b @er3,@0xffff9abc:16 ;7c3540509abc ++ xor.b @er3,@0x9abcdef0:32 ;7c3548509abcdef0 ++ ++ xor.b @-er3,@er1 ;01776c3c0150 ++ xor.b @-er3,@(3:2,er1) ;01776c3c3150 ++ xor.b @-er3,@-er1 ;01776c3cb150 ++ xor.b @-er3,@er1+ ;01776c3c8150 ++ xor.b @-er3,@er1- ;01776c3ca150 ++ xor.b @-er3,@+er1 ;01776c3c9150 ++ xor.b @-er3,@(0xffff9abc:16,er1) ;01776c3cc1509abc ++ xor.b @-er3,@(0x9abcdef0:32,er1) ;01776c3cc9509abcdef0 ++ xor.b @-er3,@(0xffff9abc:16,r2l.b) ;01776c3cd2509abc ++ xor.b @-er3,@(0xffff9abc:16,r2.w) ;01776c3ce2509abc ++ xor.b @-er3,@(0xffff9abc:16,er2.l) ;01776c3cf2509abc ++ xor.b @-er3,@(0x9abcdef0:32,r2l.b) ;01776c3cda509abcdef0 ++ xor.b @-er3,@(0x9abcdef0:32,r2.w) ;01776c3cea509abcdef0 ++ xor.b @-er3,@(0x9abcdef0:32,er2.l) ;01776c3cfa509abcdef0 ++ xor.b @-er3,@0xffff9abc:16 ;01776c3c40509abc ++ xor.b @-er3,@0x9abcdef0:32 ;01776c3c48509abcdef0 ++ ++ xor.b @er3+,@er1 ;01746c3c0150 ++ xor.b @er3+,@(3:2,er1) ;01746c3c3150 ++ xor.b @er3+,@-er1 ;01746c3cb150 ++ xor.b @er3+,@er1+ ;01746c3c8150 ++ xor.b @er3+,@er1- ;01746c3ca150 ++ xor.b @er3+,@+er1 ;01746c3c9150 ++ xor.b @er3+,@(0xffff9abc:16,er1) ;01746c3cc1509abc ++ xor.b @er3+,@(0x9abcdef0:32,er1) ;01746c3cc9509abcdef0 ++ xor.b @er3+,@(0xffff9abc:16,r2l.b) ;01746c3cd2509abc ++ xor.b @er3+,@(0xffff9abc:16,r2.w) ;01746c3ce2509abc ++ xor.b @er3+,@(0xffff9abc:16,er2.l) ;01746c3cf2509abc ++ xor.b @er3+,@(0x9abcdef0:32,r2l.b) ;01746c3cda509abcdef0 ++ xor.b @er3+,@(0x9abcdef0:32,r2.w) ;01746c3cea509abcdef0 ++ xor.b @er3+,@(0x9abcdef0:32,er2.l) ;01746c3cfa509abcdef0 ++ xor.b @er3+,@0xffff9abc:16 ;01746c3c40509abc ++ xor.b @er3+,@0x9abcdef0:32 ;01746c3c48509abcdef0 ++ ++ xor.b @er3-,@er1 ;01766c3c0150 ++ xor.b @er3-,@(3:2,er1) ;01766c3c3150 ++ xor.b @er3-,@-er1 ;01766c3cb150 ++ xor.b @er3-,@er1+ ;01766c3c8150 ++ xor.b @er3-,@er1- ;01766c3ca150 ++ xor.b @er3-,@+er1 ;01766c3c9150 ++ xor.b @er3-,@(0xffff9abc:16,er1) ;01766c3cc1509abc ++ xor.b @er3-,@(0x9abcdef0:32,er1) ;01766c3cc9509abcdef0 ++ xor.b @er3-,@(0xffff9abc:16,r2l.b) ;01766c3cd2509abc ++ xor.b @er3-,@(0xffff9abc:16,r2.w) ;01766c3ce2509abc ++ xor.b @er3-,@(0xffff9abc:16,er2.l) ;01766c3cf2509abc ++ xor.b @er3-,@(0x9abcdef0:32,r2l.b) ;01766c3cda509abcdef0 ++ xor.b @er3-,@(0x9abcdef0:32,r2.w) ;01766c3cea509abcdef0 ++ xor.b @er3-,@(0x9abcdef0:32,er2.l) ;01766c3cfa509abcdef0 ++ xor.b @er3-,@0xffff9abc:16 ;01766c3c40509abc ++ xor.b @er3-,@0x9abcdef0:32 ;01766c3c48509abcdef0 ++ ++ xor.b @+er3,@er1 ;01756c3c0150 ++ xor.b @+er3,@(3:2,er1) ;01756c3c3150 ++ xor.b @+er3,@-er1 ;01756c3cb150 ++ xor.b @+er3,@er1+ ;01756c3c8150 ++ xor.b @+er3,@er1- ;01756c3ca150 ++ xor.b @+er3,@+er1 ;01756c3c9150 ++ xor.b @+er3,@(0xffff9abc:16,er1) ;01756c3cc1509abc ++ xor.b @+er3,@(0x9abcdef0:32,er1) ;01756c3cc9509abcdef0 ++ xor.b @+er3,@(0xffff9abc:16,r2l.b) ;01756c3cd2509abc ++ xor.b @+er3,@(0xffff9abc:16,r2.w) ;01756c3ce2509abc ++ xor.b @+er3,@(0xffff9abc:16,er2.l) ;01756c3cf2509abc ++ xor.b @+er3,@(0x9abcdef0:32,r2l.b) ;01756c3cda509abcdef0 ++ xor.b @+er3,@(0x9abcdef0:32,r2.w) ;01756c3cea509abcdef0 ++ xor.b @+er3,@(0x9abcdef0:32,er2.l) ;01756c3cfa509abcdef0 ++ xor.b @+er3,@0xffff9abc:16 ;01756c3c40509abc ++ xor.b @+er3,@0x9abcdef0:32 ;01756c3c48509abcdef0 ++ ++ xor.b @(0x1234:16,er3),@er1 ;01746e3c12340150 ++ xor.b @(0x1234:16,er3),@(3:2,er1) ;01746e3c12343150 ++ xor.b @(0x1234:16,er3),@-er1 ;01746e3c1234b150 ++ xor.b @(0x1234:16,er3),@er1+ ;01746e3c12348150 ++ xor.b @(0x1234:16,er3),@er1- ;01746e3c1234a150 ++ xor.b @(0x1234:16,er3),@+er1 ;01746e3c12349150 ++ xor.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01746e3c1234c1509abc ++ xor.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01746e3c1234c9509abcdef0 ++ xor.b @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01746e3c1234d2509abc ++ xor.b @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01746e3c1234e2509abc ++ xor.b @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01746e3c1234f2509abc ++ xor.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01746e3c1234da509abcdef0 ++ xor.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01746e3c1234ea509abcdef0 ++ xor.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01746e3c1234fa509abcdef0 ++ xor.b @(0x1234:16,er3),@0xffff9abc:16 ;01746e3c123440509abc ++ xor.b @(0x1234:16,er3),@0x9abcdef0:32 ;01746e3c123448509abcdef0 ++ ++ xor.b @(0x12345678:32,er3),@er1 ;78346a2c123456780150 ++ xor.b @(0x12345678:32,er3),@(3:2,er1) ;78346a2c123456783150 ++ xor.b @(0x12345678:32,er3),@-er1 ;78346a2c12345678b150 ++ xor.b @(0x12345678:32,er3),@er1+ ;78346a2c123456788150 ++ xor.b @(0x12345678:32,er3),@er1- ;78346a2c12345678a150 ++ xor.b @(0x12345678:32,er3),@+er1 ;78346a2c123456789150 ++ xor.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346a2c12345678c1509abc ++ xor.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346a2c12345678c9509abcdef0 ++ xor.b @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346a2c12345678d2509abc ++ xor.b @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346a2c12345678e2509abc ++ xor.b @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346a2c12345678f2509abc ++ xor.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346a2c12345678da509abcdef0 ++ xor.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346a2c12345678ea509abcdef0 ++ xor.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346a2c12345678fa509abcdef0 ++ xor.b @(0x12345678:32,er3),@0xffff9abc:16 ;78346a2c1234567840509abc ++ xor.b @(0x12345678:32,er3),@0x9abcdef0:32 ;78346a2c1234567848509abcdef0 ++ ++ xor.b @(0x1234:16,r3l.b),@er1 ;01756e3c12340150 ++ xor.b @(0x1234:16,r3l.b),@(3:2,er1) ;01756e3c12343150 ++ xor.b @(0x1234:16,r3l.b),@-er1 ;01756e3c1234b150 ++ xor.b @(0x1234:16,r3l.b),@er1+ ;01756e3c12348150 ++ xor.b @(0x1234:16,r3l.b),@er1- ;01756e3c1234a150 ++ xor.b @(0x1234:16,r3l.b),@+er1 ;01756e3c12349150 ++ xor.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01756e3c1234c1509abc ++ xor.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01756e3c1234c9509abcdef0 ++ xor.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01756e3c1234d2509abc ++ xor.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01756e3c1234e2509abc ++ xor.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01756e3c1234f2509abc ++ xor.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01756e3c1234da509abcdef0 ++ xor.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01756e3c1234ea509abcdef0 ++ xor.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01756e3c1234fa509abcdef0 ++ xor.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;01756e3c123440509abc ++ xor.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01756e3c123448509abcdef0 ++ ++ xor.b @(0x1234:16,r3.w),@er1 ;01766e3c12340150 ++ xor.b @(0x1234:16,r3.w),@(3:2,er1) ;01766e3c12343150 ++ xor.b @(0x1234:16,r3.w),@-er1 ;01766e3c1234b150 ++ xor.b @(0x1234:16,r3.w),@er1+ ;01766e3c12348150 ++ xor.b @(0x1234:16,r3.w),@er1- ;01766e3c1234a150 ++ xor.b @(0x1234:16,r3.w),@+er1 ;01766e3c12349150 ++ xor.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01766e3c1234c1509abc ++ xor.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01766e3c1234c9509abcdef0 ++ xor.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01766e3c1234d2509abc ++ xor.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01766e3c1234e2509abc ++ xor.b @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01766e3c1234f2509abc ++ xor.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01766e3c1234da509abcdef0 ++ xor.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01766e3c1234ea509abcdef0 ++ xor.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01766e3c1234fa509abcdef0 ++ xor.b @(0x1234:16,r3.w),@0xffff9abc:16 ;01766e3c123440509abc ++ xor.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;01766e3c123448509abcdef0 ++ ++ xor.b @(0x1234:16,er3.l),@er1 ;01776e3c12340150 ++ xor.b @(0x1234:16,er3.l),@(3:2,er1) ;01776e3c12343150 ++ xor.b @(0x1234:16,er3.l),@-er1 ;01776e3c1234b150 ++ xor.b @(0x1234:16,er3.l),@er1+ ;01776e3c12348150 ++ xor.b @(0x1234:16,er3.l),@er1- ;01776e3c1234a150 ++ xor.b @(0x1234:16,er3.l),@+er1 ;01776e3c12349150 ++ xor.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01776e3c1234c1509abc ++ xor.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01776e3c1234c9509abcdef0 ++ xor.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01776e3c1234d2509abc ++ xor.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01776e3c1234e2509abc ++ xor.b @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01776e3c1234f2509abc ++ xor.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01776e3c1234da509abcdef0 ++ xor.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01776e3c1234ea509abcdef0 ++ xor.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01776e3c1234fa509abcdef0 ++ xor.b @(0x1234:16,er3.l),@0xffff9abc:16 ;01776e3c123440509abc ++ xor.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;01776e3c123448509abcdef0 ++ ++ xor.b @(0x12345678:32,r3l.b),@er1 ;78356a2c123456780150 ++ xor.b @(0x12345678:32,r3l.b),@(3:2,er1) ;78356a2c123456783150 ++ xor.b @(0x12345678:32,r3l.b),@-er1 ;78356a2c12345678b150 ++ xor.b @(0x12345678:32,r3l.b),@er1+ ;78356a2c123456788150 ++ xor.b @(0x12345678:32,r3l.b),@er1- ;78356a2c12345678a150 ++ xor.b @(0x12345678:32,r3l.b),@+er1 ;78356a2c123456789150 ++ xor.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356a2c12345678c1509abc ++ xor.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356a2c12345678c9509abcdef0 ++ xor.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356a2c12345678d2509abc ++ xor.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356a2c12345678e2509abc ++ xor.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356a2c12345678f2509abc ++ xor.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356a2c12345678da509abcdef0 ++ xor.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356a2c12345678ea509abcdef0 ++ xor.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356a2c12345678fa509abcdef0 ++ xor.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356a2c1234567840509abc ++ xor.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356a2c1234567848509abcdef0 ++ ++ xor.b @(0x12345678:32,r3.w),@er1 ;78366a2c123456780150 ++ xor.b @(0x12345678:32,r3.w),@(3:2,er1) ;78366a2c123456783150 ++ xor.b @(0x12345678:32,r3.w),@-er1 ;78366a2c12345678b150 ++ xor.b @(0x12345678:32,r3.w),@er1+ ;78366a2c123456788150 ++ xor.b @(0x12345678:32,r3.w),@er1- ;78366a2c12345678a150 ++ xor.b @(0x12345678:32,r3.w),@+er1 ;78366a2c123456789150 ++ xor.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366a2c12345678c1509abc ++ xor.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366a2c12345678c9509abcdef0 ++ xor.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366a2c12345678d2509abc ++ xor.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366a2c12345678e2509abc ++ xor.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366a2c12345678f2509abc ++ xor.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366a2c12345678da509abcdef0 ++ xor.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366a2c12345678ea509abcdef0 ++ xor.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366a2c12345678fa509abcdef0 ++ xor.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366a2c1234567840509abc ++ xor.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366a2c1234567848509abcdef0 ++ ++ xor.b @(0x12345678:32,er3.l),@er1 ;78376a2c123456780150 ++ xor.b @(0x12345678:32,er3.l),@(3:2,er1) ;78376a2c123456783150 ++ xor.b @(0x12345678:32,er3.l),@-er1 ;78376a2c12345678b150 ++ xor.b @(0x12345678:32,er3.l),@er1+ ;78376a2c123456788150 ++ xor.b @(0x12345678:32,er3.l),@er1- ;78376a2c12345678a150 ++ xor.b @(0x12345678:32,er3.l),@+er1 ;78376a2c123456789150 ++ xor.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376a2c12345678c1509abc ++ xor.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376a2c12345678c9509abcdef0 ++ xor.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376a2c12345678d2509abc ++ xor.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376a2c12345678e2509abc ++ xor.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376a2c12345678f2509abc ++ xor.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376a2c12345678da509abcdef0 ++ xor.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376a2c12345678ea509abcdef0 ++ xor.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376a2c12345678fa509abcdef0 ++ xor.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376a2c1234567840509abc ++ xor.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376a2c1234567848509abcdef0 ++ ++ xor.b @0x1234:16,@er1 ;6a1512340150 ++ xor.b @0x1234:16,@(3:2,er1) ;6a1512343150 ++ xor.b @0x1234:16,@-er1 ;6a151234b150 ++ xor.b @0x1234:16,@er1+ ;6a1512348150 ++ xor.b @0x1234:16,@er1- ;6a151234a150 ++ xor.b @0x1234:16,@+er1 ;6a1512349150 ++ xor.b @0x1234:16,@(0xffff9abc:16,er1) ;6a151234c1509abc ++ xor.b @0x1234:16,@(0x9abcdef0:32,er1) ;6a151234c9509abcdef0 ++ xor.b @0x1234:16,@(0xffff9abc:16,r2l.b) ;6a151234d2509abc ++ xor.b @0x1234:16,@(0xffff9abc:16,r2.w) ;6a151234e2509abc ++ xor.b @0x1234:16,@(0xffff9abc:16,er2.l) ;6a151234f2509abc ++ xor.b @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6a151234da509abcdef0 ++ xor.b @0x1234:16,@(0x9abcdef0:32,r2.w) ;6a151234ea509abcdef0 ++ xor.b @0x1234:16,@(0x9abcdef0:32,er2.l) ;6a151234fa509abcdef0 ++ xor.b @0x1234:16,@0xffff9abc:16 ;6a15123440509abc ++ xor.b @0x1234:16,@0x9abcdef0:32 ;6a15123448509abcdef0 ++ ++ xor.b @0x12345678:32,@er1 ;6a35123456780150 ++ xor.b @0x12345678:32,@(3:2,er1) ;6a35123456783150 ++ xor.b @0x12345678:32,@-er1 ;6a3512345678b150 ++ xor.b @0x12345678:32,@er1+ ;6a35123456788150 ++ xor.b @0x12345678:32,@er1- ;6a3512345678a150 ++ xor.b @0x12345678:32,@+er1 ;6a35123456789150 ++ xor.b @0x12345678:32,@(0xffff9abc:16,er1) ;6a3512345678c1509abc ++ xor.b @0x12345678:32,@(0x9abcdef0:32,er1) ;6a3512345678c9509abcdef0 ++ xor.b @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6a3512345678d2509abc ++ xor.b @0x12345678:32,@(0xffff9abc:16,r2.w) ;6a3512345678e2509abc ++ xor.b @0x12345678:32,@(0xffff9abc:16,er2.l) ;6a3512345678f2509abc ++ xor.b @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6a3512345678da509abcdef0 ++ xor.b @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6a3512345678ea509abcdef0 ++ xor.b @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6a3512345678fa509abcdef0 ++ xor.b @0x12345678:32,@0xffff9abc:16 ;6a351234567840509abc ++ xor.b @0x12345678:32,@0x9abcdef0:32 ;6a351234567848509abcdef0 ++ ++ xor.w #0x1234:16,r1 ;79511234 ++ xor.w #0x1234:16,@er1 ;015e01501234 ++ xor.w #0x1234:16,@(0x6:2,er1) ;015e31501234 ++ xor.w #0x1234:16,@er1+ ;015e81501234 ++ xor.w #0x1234:16,@-er1 ;015eb1501234 ++ xor.w #0x1234:16,@+er1 ;015e91501234 ++ xor.w #0x1234:16,@er1- ;015ea1501234 ++ xor.w #0x1234:16,@(0xffff9abc:16,er1) ;015ec1509abc1234 ++ xor.w #0x1234:16,@(0x9abcdef0:32,er1) ;015ec9509abcdef01234 ++ xor.w #0x1234:16,@(0xffff9abc:16,r2l.b) ;015ed2509abc1234 ++ xor.w #0x1234:16,@(0xffff9abc:16,r2.w) ;015ee2509abc1234 ++ xor.w #0x1234:16,@(0xffff9abc:16,er2.l) ;015ef2509abc1234 ++ xor.w #0x1234:16,@(0x9abcdef0:32,r2l.b) ;015eda509abcdef01234 ++ xor.w #0x1234:16,@(0x9abcdef0:32,r2.w) ;015eea509abcdef01234 ++ xor.w #0x1234:16,@(0x9abcdef0:32,er2.l) ;015efa509abcdef01234 ++ xor.w #0x1234:16,@0xffff9abc:16 ;015e40509abc1234 ++ xor.w #0x1234:16,@0x9abcdef0:32 ;015e48509abcdef01234 ++ ++ xor.w r3,r1 ;6531 ++ ++ xor.w r3,@er1 ;7d906530 ++ xor.w r3,@(0x6:2,er1) ;01593153 ++ xor.w r3,@-er1 ;0159b153 ++ xor.w r3,@er1+ ;01598153 ++ xor.w r3,@er1- ;0159a153 ++ xor.w r3,@+er1 ;01599153 ++ xor.w r3,@(0x1234:16,er1) ;0159c1531234 ++ xor.w r3,@(0x12345678:32,er1) ;0159c95312345678 ++ xor.w r3,@(0x1234:16,r2l.b) ;0159d2531234 ++ xor.w r3,@(0x1234:16,r2.w) ;0159e2531234 ++ xor.w r3,@(0x1234:16,er2.l) ;0159f2531234 ++ xor.w r3,@(0x12345678:32,r2l.b) ;0159da5312345678 ++ xor.w r3,@(0x12345678:32,r2.w) ;0159ea5312345678 ++ xor.w r3,@(0x12345678:32,er2.l) ;0159fa5312345678 ++ xor.w r3,@0x1234:16 ;6b1812346530 ++ xor.w r3,@0x12345678:32 ;6b38123456786530 ++ ++ xor.w @er3,r1 ;7cb06501 ++ xor.w @(0x6:2,er3),r1 ;015a3351 ++ xor.w @er3+,r1 ;015a8351 ++ xor.w @-er3,r1 ;015ab351 ++ xor.w @+er3,r1 ;015a9351 ++ xor.w @er3-,r1 ;015aa351 ++ xor.w @(0x1234:16,er1),r1 ;015ac1511234 ++ xor.w @(0x12345678:32,er1),r1 ;015ac95112345678 ++ xor.w @(0x1234:16,r2l.b),r1 ;015ad2511234 ++ xor.w @(0x1234:16,r2.w),r1 ;015ae2511234 ++ xor.w @(0x1234:16,er2.l),r1 ;015af2511234 ++ xor.w @(0x12345678:32,r2l.b),r1 ;015ada5112345678 ++ xor.w @(0x12345678:32,r2.w),r1 ;015aea5112345678 ++ xor.w @(0x12345678:32,er2.l),r1 ;015afa5112345678 ++ xor.w @0x1234:16,r1 ;6b1012346501 ++ xor.w @0x12345678:32,r1 ;6b30123456786501 ++ ++ xor.w @er3,@er1 ;7cb50150 ++ xor.w @er3,@(6:2,er1) ;7cb53150 ++ xor.w @er3,@-er1 ;7cb5b150 ++ xor.w @er3,@er1+ ;7cb58150 ++ xor.w @er3,@er1- ;7cb5a150 ++ xor.w @er3,@+er1 ;7cb59150 ++ xor.w @er3,@(0xffff9abc:16,er1) ;7cb5c1509abc ++ xor.w @er3,@(0x9abcdef0:32,er1) ;7cb5c9509abcdef0 ++ xor.w @er3,@(0xffff9abc:16,r2l.b) ;7cb5d2509abc ++ xor.w @er3,@(0xffff9abc:16,r2.w) ;7cb5e2509abc ++ xor.w @er3,@(0xffff9abc:16,er2.l) ;7cb5f2509abc ++ xor.w @er3,@(0x9abcdef0:32,r2l.b) ;7cb5da509abcdef0 ++ xor.w @er3,@(0x9abcdef0:32,r2.w) ;7cb5ea509abcdef0 ++ xor.w @er3,@(0x9abcdef0:32,er2.l) ;7cb5fa509abcdef0 ++ xor.w @er3,@0xffff9abc:16 ;7cb540509abc ++ xor.w @er3,@0x9abcdef0:32 ;7cb548509abcdef0 ++ ++ xor.w @-er3,@er1 ;01576d3c0150 ++ xor.w @-er3,@(6:2,er1) ;01576d3c3150 ++ xor.w @-er3,@-er1 ;01576d3cb150 ++ xor.w @-er3,@er1+ ;01576d3c8150 ++ xor.w @-er3,@er1- ;01576d3ca150 ++ xor.w @-er3,@+er1 ;01576d3c9150 ++ xor.w @-er3,@(0xffff9abc:16,er1) ;01576d3cc1509abc ++ xor.w @-er3,@(0x9abcdef0:32,er1) ;01576d3cc9509abcdef0 ++ xor.w @-er3,@(0xffff9abc:16,r2l.b) ;01576d3cd2509abc ++ xor.w @-er3,@(0xffff9abc:16,r2.w) ;01576d3ce2509abc ++ xor.w @-er3,@(0xffff9abc:16,er2.l) ;01576d3cf2509abc ++ xor.w @-er3,@(0x9abcdef0:32,r2l.b) ;01576d3cda509abcdef0 ++ xor.w @-er3,@(0x9abcdef0:32,r2.w) ;01576d3cea509abcdef0 ++ xor.w @-er3,@(0x9abcdef0:32,er2.l) ;01576d3cfa509abcdef0 ++ xor.w @-er3,@0xffff9abc:16 ;01576d3c40509abc ++ xor.w @-er3,@0x9abcdef0:32 ;01576d3c48509abcdef0 ++ ++ xor.w @er3+,@er1 ;01546d3c0150 ++ xor.w @er3+,@(6:2,er1) ;01546d3c3150 ++ xor.w @er3+,@-er1 ;01546d3cb150 ++ xor.w @er3+,@er1+ ;01546d3c8150 ++ xor.w @er3+,@er1- ;01546d3ca150 ++ xor.w @er3+,@+er1 ;01546d3c9150 ++ xor.w @er3+,@(0xffff9abc:16,er1) ;01546d3cc1509abc ++ xor.w @er3+,@(0x9abcdef0:32,er1) ;01546d3cc9509abcdef0 ++ xor.w @er3+,@(0xffff9abc:16,r2l.b) ;01546d3cd2509abc ++ xor.w @er3+,@(0xffff9abc:16,r2.w) ;01546d3ce2509abc ++ xor.w @er3+,@(0xffff9abc:16,er2.l) ;01546d3cf2509abc ++ xor.w @er3+,@(0x9abcdef0:32,r2l.b) ;01546d3cda509abcdef0 ++ xor.w @er3+,@(0x9abcdef0:32,r2.w) ;01546d3cea509abcdef0 ++ xor.w @er3+,@(0x9abcdef0:32,er2.l) ;01546d3cfa509abcdef0 ++ xor.w @er3+,@0xffff9abc:16 ;01546d3c40509abc ++ xor.w @er3+,@0x9abcdef0:32 ;01546d3c48509abcdef0 ++ ++ xor.w @er3-,@er1 ;01566d3c0150 ++ xor.w @er3-,@(6:2,er1) ;01566d3c3150 ++ xor.w @er3-,@-er1 ;01566d3cb150 ++ xor.w @er3-,@er1+ ;01566d3c8150 ++ xor.w @er3-,@er1- ;01566d3ca150 ++ xor.w @er3-,@+er1 ;01566d3c9150 ++ xor.w @er3-,@(0xffff9abc:16,er1) ;01566d3cc1509abc ++ xor.w @er3-,@(0x9abcdef0:32,er1) ;01566d3cc9509abcdef0 ++ xor.w @er3-,@(0xffff9abc:16,r2l.b) ;01566d3cd2509abc ++ xor.w @er3-,@(0xffff9abc:16,r2.w) ;01566d3ce2509abc ++ xor.w @er3-,@(0xffff9abc:16,er2.l) ;01566d3cf2509abc ++ xor.w @er3-,@(0x9abcdef0:32,r2l.b) ;01566d3cda509abcdef0 ++ xor.w @er3-,@(0x9abcdef0:32,r2.w) ;01566d3cea509abcdef0 ++ xor.w @er3-,@(0x9abcdef0:32,er2.l) ;01566d3cfa509abcdef0 ++ xor.w @er3-,@0xffff9abc:16 ;01566d3c40509abc ++ xor.w @er3-,@0x9abcdef0:32 ;01566d3c48509abcdef0 ++ ++ xor.w @+er3,@er1 ;01556d3c0150 ++ xor.w @+er3,@(6:2,er1) ;01556d3c3150 ++ xor.w @+er3,@-er1 ;01556d3cb150 ++ xor.w @+er3,@er1+ ;01556d3c8150 ++ xor.w @+er3,@er1- ;01556d3ca150 ++ xor.w @+er3,@+er1 ;01556d3c9150 ++ xor.w @+er3,@(0xffff9abc:16,er1) ;01556d3cc1509abc ++ xor.w @+er3,@(0x9abcdef0:32,er1) ;01556d3cc9509abcdef0 ++ xor.w @+er3,@(0xffff9abc:16,r2l.b) ;01556d3cd2509abc ++ xor.w @+er3,@(0xffff9abc:16,r2.w) ;01556d3ce2509abc ++ xor.w @+er3,@(0xffff9abc:16,er2.l) ;01556d3cf2509abc ++ xor.w @+er3,@(0x9abcdef0:32,r2l.b) ;01556d3cda509abcdef0 ++ xor.w @+er3,@(0x9abcdef0:32,r2.w) ;01556d3cea509abcdef0 ++ xor.w @+er3,@(0x9abcdef0:32,er2.l) ;01556d3cfa509abcdef0 ++ xor.w @+er3,@0xffff9abc:16 ;01556d3c40509abc ++ xor.w @+er3,@0x9abcdef0:32 ;01556d3c48509abcdef0 ++ ++ xor.w @(0x1234:16,er3),@er1 ;01546f3c12340150 ++ xor.w @(0x1234:16,er3),@(6:2,er1) ;01546f3c12343150 ++ xor.w @(0x1234:16,er3),@-er1 ;01546f3c1234b150 ++ xor.w @(0x1234:16,er3),@er1+ ;01546f3c12348150 ++ xor.w @(0x1234:16,er3),@er1- ;01546f3c1234a150 ++ xor.w @(0x1234:16,er3),@+er1 ;01546f3c12349150 ++ xor.w @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01546f3c1234c1509abc ++ xor.w @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01546f3c1234c9509abcdef0 ++ xor.w @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01546f3c1234d2509abc ++ xor.w @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01546f3c1234e2509abc ++ xor.w @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01546f3c1234f2509abc ++ xor.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01546f3c1234da509abcdef0 ++ xor.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01546f3c1234ea509abcdef0 ++ xor.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01546f3c1234fa509abcdef0 ++ xor.w @(0x1234:16,er3),@0xffff9abc:16 ;01546f3c123440509abc ++ xor.w @(0x1234:16,er3),@0x9abcdef0:32 ;01546f3c123448509abcdef0 ++ ++ xor.w @(0x12345678:32,er3),@er1 ;78346b2c123456780150 ++ xor.w @(0x12345678:32,er3),@(6:2,er1) ;78346b2c123456783150 ++ xor.w @(0x12345678:32,er3),@-er1 ;78346b2c12345678b150 ++ xor.w @(0x12345678:32,er3),@er1+ ;78346b2c123456788150 ++ xor.w @(0x12345678:32,er3),@er1- ;78346b2c12345678a150 ++ xor.w @(0x12345678:32,er3),@+er1 ;78346b2c123456789150 ++ xor.w @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346b2c12345678c1509abc ++ xor.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346b2c12345678c9509abcdef0 ++ xor.w @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346b2c12345678d2509abc ++ xor.w @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346b2c12345678e2509abc ++ xor.w @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346b2c12345678f2509abc ++ xor.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346b2c12345678da509abcdef0 ++ xor.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346b2c12345678ea509abcdef0 ++ xor.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346b2c12345678fa509abcdef0 ++ xor.w @(0x12345678:32,er3),@0xffff9abc:16 ;78346b2c1234567840509abc ++ xor.w @(0x12345678:32,er3),@0x9abcdef0:32 ;78346b2c1234567848509abcdef0 ++ ++ xor.w @(0x1234:16,r3l.b),@er1 ;01556f3c12340150 ++ xor.w @(0x1234:16,r3l.b),@(6:2,er1) ;01556f3c12343150 ++ xor.w @(0x1234:16,r3l.b),@-er1 ;01556f3c1234b150 ++ xor.w @(0x1234:16,r3l.b),@er1+ ;01556f3c12348150 ++ xor.w @(0x1234:16,r3l.b),@er1- ;01556f3c1234a150 ++ xor.w @(0x1234:16,r3l.b),@+er1 ;01556f3c12349150 ++ xor.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01556f3c1234c1509abc ++ xor.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01556f3c1234c9509abcdef0 ++ xor.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01556f3c1234d2509abc ++ xor.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01556f3c1234e2509abc ++ xor.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01556f3c1234f2509abc ++ xor.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01556f3c1234da509abcdef0 ++ xor.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01556f3c1234ea509abcdef0 ++ xor.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01556f3c1234fa509abcdef0 ++ xor.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;01556f3c123440509abc ++ xor.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01556f3c123448509abcdef0 ++ ++ xor.w @(0x1234:16,r3.w),@er1 ;01566f3c12340150 ++ xor.w @(0x1234:16,r3.w),@(6:2,er1) ;01566f3c12343150 ++ xor.w @(0x1234:16,r3.w),@-er1 ;01566f3c1234b150 ++ xor.w @(0x1234:16,r3.w),@er1+ ;01566f3c12348150 ++ xor.w @(0x1234:16,r3.w),@er1- ;01566f3c1234a150 ++ xor.w @(0x1234:16,r3.w),@+er1 ;01566f3c12349150 ++ xor.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01566f3c1234c1509abc ++ xor.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01566f3c1234c9509abcdef0 ++ xor.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01566f3c1234d2509abc ++ xor.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01566f3c1234e2509abc ++ xor.w @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01566f3c1234f2509abc ++ xor.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01566f3c1234da509abcdef0 ++ xor.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01566f3c1234ea509abcdef0 ++ xor.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01566f3c1234fa509abcdef0 ++ xor.w @(0x1234:16,r3.w),@0xffff9abc:16 ;01566f3c123440509abc ++ xor.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;01566f3c123448509abcdef0 ++ ++ xor.w @(0x1234:16,er3.l),@er1 ;01576f3c12340150 ++ xor.w @(0x1234:16,er3.l),@(6:2,er1) ;01576f3c12343150 ++ xor.w @(0x1234:16,er3.l),@-er1 ;01576f3c1234b150 ++ xor.w @(0x1234:16,er3.l),@er1+ ;01576f3c12348150 ++ xor.w @(0x1234:16,er3.l),@er1- ;01576f3c1234a150 ++ xor.w @(0x1234:16,er3.l),@+er1 ;01576f3c12349150 ++ xor.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01576f3c1234c1509abc ++ xor.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01576f3c1234c9509abcdef0 ++ xor.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01576f3c1234d2509abc ++ xor.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01576f3c1234e2509abc ++ xor.w @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01576f3c1234f2509abc ++ xor.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01576f3c1234da509abcdef0 ++ xor.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01576f3c1234ea509abcdef0 ++ xor.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01576f3c1234fa509abcdef0 ++ xor.w @(0x1234:16,er3.l),@0xffff9abc:16 ;01576f3c123440509abc ++ xor.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;01576f3c123448509abcdef0 ++ ++ xor.w @(0x12345678:32,r3l.b),@er1 ;78356b2c123456780150 ++ xor.w @(0x12345678:32,r3l.b),@(6:2,er1) ;78356b2c123456783150 ++ xor.w @(0x12345678:32,r3l.b),@-er1 ;78356b2c12345678b150 ++ xor.w @(0x12345678:32,r3l.b),@er1+ ;78356b2c123456788150 ++ xor.w @(0x12345678:32,r3l.b),@er1- ;78356b2c12345678a150 ++ xor.w @(0x12345678:32,r3l.b),@+er1 ;78356b2c123456789150 ++ xor.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356b2c12345678c1509abc ++ xor.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356b2c12345678c9509abcdef0 ++ xor.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356b2c12345678d2509abc ++ xor.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356b2c12345678e2509abc ++ xor.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356b2c12345678f2509abc ++ xor.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356b2c12345678da509abcdef0 ++ xor.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356b2c12345678ea509abcdef0 ++ xor.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356b2c12345678fa509abcdef0 ++ xor.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356b2c1234567840509abc ++ xor.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356b2c1234567848509abcdef0 ++ ++ xor.w @(0x12345678:32,r3.w),@er1 ;78366b2c123456780150 ++ xor.w @(0x12345678:32,r3.w),@(6:2,er1) ;78366b2c123456783150 ++ xor.w @(0x12345678:32,r3.w),@-er1 ;78366b2c12345678b150 ++ xor.w @(0x12345678:32,r3.w),@er1+ ;78366b2c123456788150 ++ xor.w @(0x12345678:32,r3.w),@er1- ;78366b2c12345678a150 ++ xor.w @(0x12345678:32,r3.w),@+er1 ;78366b2c123456789150 ++ xor.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366b2c12345678c1509abc ++ xor.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366b2c12345678c9509abcdef0 ++ xor.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366b2c12345678d2509abc ++ xor.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366b2c12345678e2509abc ++ xor.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366b2c12345678f2509abc ++ xor.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366b2c12345678da509abcdef0 ++ xor.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366b2c12345678ea509abcdef0 ++ xor.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366b2c12345678fa509abcdef0 ++ xor.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366b2c1234567840509abc ++ xor.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366b2c1234567848509abcdef0 ++ ++ xor.w @(0x12345678:32,er3.l),@er1 ;78376b2c123456780150 ++ xor.w @(0x12345678:32,er3.l),@(6:2,er1) ;78376b2c123456783150 ++ xor.w @(0x12345678:32,er3.l),@-er1 ;78376b2c12345678b150 ++ xor.w @(0x12345678:32,er3.l),@er1+ ;78376b2c123456788150 ++ xor.w @(0x12345678:32,er3.l),@er1- ;78376b2c12345678a150 ++ xor.w @(0x12345678:32,er3.l),@+er1 ;78376b2c123456789150 ++ xor.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376b2c12345678c1509abc ++ xor.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376b2c12345678c9509abcdef0 ++ xor.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376b2c12345678d2509abc ++ xor.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376b2c12345678e2509abc ++ xor.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376b2c12345678f2509abc ++ xor.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376b2c12345678da509abcdef0 ++ xor.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376b2c12345678ea509abcdef0 ++ xor.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376b2c12345678fa509abcdef0 ++ xor.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376b2c1234567840509abc ++ xor.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376b2c1234567848509abcdef0 ++ ++ xor.w @0x1234:16,@er1 ;6b1512340150 ++ xor.w @0x1234:16,@(6:2,er1) ;6b1512343150 ++ xor.w @0x1234:16,@-er1 ;6b151234b150 ++ xor.w @0x1234:16,@er1+ ;6b1512348150 ++ xor.w @0x1234:16,@er1- ;6b151234a150 ++ xor.w @0x1234:16,@+er1 ;6b1512349150 ++ xor.w @0x1234:16,@(0xffff9abc:16,er1) ;6b151234c1509abc ++ xor.w @0x1234:16,@(0x9abcdef0:32,er1) ;6b151234c9509abcdef0 ++ xor.w @0x1234:16,@(0xffff9abc:16,r2l.b) ;6b151234d2509abc ++ xor.w @0x1234:16,@(0xffff9abc:16,r2.w) ;6b151234e2509abc ++ xor.w @0x1234:16,@(0xffff9abc:16,er2.l) ;6b151234f2509abc ++ xor.w @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6b151234da509abcdef0 ++ xor.w @0x1234:16,@(0x9abcdef0:32,r2.w) ;6b151234ea509abcdef0 ++ xor.w @0x1234:16,@(0x9abcdef0:32,er2.l) ;6b151234fa509abcdef0 ++ xor.w @0x1234:16,@0xffff9abc:16 ;6b15123440509abc ++ xor.w @0x1234:16,@0x9abcdef0:32 ;6b15123448509abcdef0 ++ ++ xor.w @0x12345678:32,@er1 ;6b35123456780150 ++ xor.w @0x12345678:32,@(6:2,er1) ;6b35123456783150 ++ xor.w @0x12345678:32,@-er1 ;6b3512345678b150 ++ xor.w @0x12345678:32,@er1+ ;6b35123456788150 ++ xor.w @0x12345678:32,@er1- ;6b3512345678a150 ++ xor.w @0x12345678:32,@+er1 ;6b35123456789150 ++ xor.w @0x12345678:32,@(0xffff9abc:16,er1) ;6b3512345678c1509abc ++ xor.w @0x12345678:32,@(0x9abcdef0:32,er1) ;6b3512345678c9509abcdef0 ++ xor.w @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6b3512345678d2509abc ++ xor.w @0x12345678:32,@(0xffff9abc:16,r2.w) ;6b3512345678e2509abc ++ xor.w @0x12345678:32,@(0xffff9abc:16,er2.l) ;6b3512345678f2509abc ++ xor.w @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6b3512345678da509abcdef0 ++ xor.w @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6b3512345678ea509abcdef0 ++ xor.w @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6b3512345678fa509abcdef0 ++ xor.w @0x12345678:32,@0xffff9abc:16 ;6b351234567840509abc ++ xor.w @0x12345678:32,@0x9abcdef0:32 ;6b351234567848509abcdef0 ++ ++ xor.l #0x12345678:32,er1 ;7a5112345678 ++ xor.l #0x1234:16,er1 ;7a591234 ++ xor.l #0x12345678:32,@er1 ;010e015812345678 ++ xor.l #0x12345678:32,@(0xc:2,er1) ;010e315812345678 ++ xor.l #0x12345678:32,@er1+ ;010e815812345678 ++ xor.l #0x12345678:32,@-er1 ;010eb15812345678 ++ xor.l #0x12345678:32,@+er1 ;010e915812345678 ++ xor.l #0x12345678:32,@er1- ;010ea15812345678 ++ xor.l #0x12345678:32,@(0xffff9abc:16,er1) ;010ec1589abc12345678 ++ xor.l #0x12345678:32,@(0x9abcdef0:32,er1) ;010ec9589abcdef012345678 ++ xor.l #0x12345678:32,@(0xffff9abc:16,r2l.b) ;010ed2589abc12345678 ++ xor.l #0x12345678:32,@(0xffff9abc:16,r2.w) ;010ee2589abc12345678 ++ xor.l #0x12345678:32,@(0xffff9abc:16,er2.l) ;010ef2589abc12345678 ++ xor.l #0x12345678:32,@(0x9abcdef0:32,r2l.b) ;010eda589abcdef012345678 ++ xor.l #0x12345678:32,@(0x9abcdef0:32,r2.w) ;010eea589abcdef012345678 ++ xor.l #0x12345678:32,@(0x9abcdef0:32,er2.l) ;010efa589abcdef012345678 ++ xor.l #0x12345678:32,@0xffff9abc:16 ;010e40589abc12345678 ++ xor.l #0x12345678:32,@0x9abcdef0:32 ;010e48589abcdef012345678 ++ xor.l #0x1234:16,@er1 ;010e01501234 ++ xor.l #0x1234:16,@(0xc:2,er1) ;010e31501234 ++ xor.l #0x1234:16,@er1+ ;010e81501234 ++ xor.l #0x1234:16,@-er1 ;010eb1501234 ++ xor.l #0x1234:16,@+er1 ;010e91501234 ++ xor.l #0x1234:16,@er1- ;010ea1501234 ++ xor.l #0x1234:16,@(0xffff9abc:16,er1) ;010ec1509abc1234 ++ xor.l #0x1234:16,@(0x9abcdef0:32,er1) ;010ec9509abcdef01234 ++ xor.l #0x1234:16,@(0xffff9abc:16,r2l.b) ;010ed2509abc1234 ++ xor.l #0x1234:16,@(0xffff9abc:16,r2.w) ;010ee2509abc1234 ++ xor.l #0x1234:16,@(0xffff9abc:16,er2.l) ;010ef2509abc1234 ++ xor.l #0x1234:16,@(0x9abcdef0:32,r2l.b) ;010eda509abcdef01234 ++ xor.l #0x1234:16,@(0x9abcdef0:32,r2.w) ;010eea509abcdef01234 ++ xor.l #0x1234:16,@(0x9abcdef0:32,er2.l) ;010efa509abcdef01234 ++ xor.l #0x1234:16,@0xffff9abc:16 ;010e40509abc1234 ++ xor.l #0x1234:16,@0x9abcdef0:32 ;010e48509abcdef01234 ++ ++ xor.l er3,er1 ;01f06531 ++ ++ xor.l er3,@er1 ;01090153 ++ xor.l er3,@(0xc:2,er1) ;01093153 ++ xor.l er3,@er1+ ;01098153 ++ xor.l er3,@-er1 ;0109b153 ++ xor.l er3,@+er1 ;01099153 ++ xor.l er3,@er1- ;0109a153 ++ xor.l er3,@(0x1234:16,er1) ;0109c1531234 ++ xor.l er3,@(0x12345678:32,er1) ;0109c95312345678 ++ xor.l er3,@(0x1234:16,r2l.b) ;0109d2531234 ++ xor.l er3,@(0x1234:16,r2.w) ;0109e2531234 ++ xor.l er3,@(0x1234:16,er2.l) ;0109f2531234 ++ xor.l er3,@(0x12345678:32,r2l.b) ;0109da5312345678 ++ xor.l er3,@(0x12345678:32,r2.w) ;0109ea5312345678 ++ xor.l er3,@(0x12345678:32,er2.l) ;0109fa5312345678 ++ xor.l er3,@0x1234:16 ;010940531234 ++ xor.l er3,@0x12345678:32 ;0109485312345678 ++ ++ xor.l @er3,er1 ;010a0351 ++ xor.l @(0xc:2,er3),er1 ;010a3351 ++ xor.l @er3+,er1 ;010a8351 ++ xor.l @-er3,er1 ;010ab351 ++ xor.l @+er3,er1 ;010a9351 ++ xor.l @er3-,er1 ;010aa351 ++ xor.l @(0x1234:16,er1),er1 ;010ac1511234 ++ xor.l @(0x12345678:32,er1),er1 ;010ac95112345678 ++ xor.l @(0x1234:16,r2l.b),er1 ;010ad2511234 ++ xor.l @(0x1234:16,r2.w),er1 ;010ae2511234 ++ xor.l @(0x1234:16,er2.l),er1 ;010af2511234 ++ xor.l @(0x12345678:32,r2l.b),er1 ;010ada5112345678 ++ xor.l @(0x12345678:32,r2.w),er1 ;010aea5112345678 ++ xor.l @(0x12345678:32,er2.l),er1 ;010afa5112345678 ++ xor.l @0x1234:16,er1 ;010a40511234 ++ xor.l @0x12345678:32,er1 ;010a485112345678 ++ ++ xor.l @er3,@er1 ;0104693c0150 ++ xor.l @er3,@(0xc:2,er1) ;0104693c3150 ++ xor.l @er3,@-er1 ;0104693cb150 ++ xor.l @er3,@er1+ ;0104693c8150 ++ xor.l @er3,@er1- ;0104693ca150 ++ xor.l @er3,@+er1 ;0104693c9150 ++ xor.l @er3,@(0xffff9abc:16,er1) ;0104693cc1509abc ++ xor.l @er3,@(0x9abcdef0:32,er1) ;0104693cc9509abcdef0 ++ xor.l @er3,@(0xffff9abc:16,r2l.b) ;0104693cd2509abc ++ xor.l @er3,@(0xffff9abc:16,r2.w) ;0104693ce2509abc ++ xor.l @er3,@(0xffff9abc:16,er2.l) ;0104693cf2509abc ++ xor.l @er3,@(0x9abcdef0:32,r2l.b) ;0104693cda509abcdef0 ++ xor.l @er3,@(0x9abcdef0:32,r2.w) ;0104693cea509abcdef0 ++ xor.l @er3,@(0x9abcdef0:32,er2.l) ;0104693cfa509abcdef0 ++ xor.l @er3,@0xffff9abc:16 ;0104693c40509abc ++ xor.l @er3,@0x9abcdef0:32 ;0104693c48509abcdef0 ++ ++ xor.l @(0xc:2,er3),@er1 ;0107693c0150 ++ xor.l @(0xc:2,er3),@(0xc:2,er1) ;0107693c3150 ++ xor.l @(0xc:2,er3),@-er1 ;0107693cb150 ++ xor.l @(0xc:2,er3),@er1+ ;0107693c8150 ++ xor.l @(0xc:2,er3),@er1- ;0107693ca150 ++ xor.l @(0xc:2,er3),@+er1 ;0107693c9150 ++ xor.l @(0xc:2,er3),@(0xffff9abc:16,er1) ;0107693cc1509abc ++ xor.l @(0xc:2,er3),@(0x9abcdef0:32,er1) ;0107693cc9509abcdef0 ++ xor.l @(0xc:2,er3),@(0xffff9abc:16,r2l.b) ;0107693cd2509abc ++ xor.l @(0xc:2,er3),@(0xffff9abc:16,r2.w) ;0107693ce2509abc ++ xor.l @(0xc:2,er3),@(0xffff9abc:16,er2.l) ;0107693cf2509abc ++ xor.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b) ;0107693cda509abcdef0 ++ xor.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w) ;0107693cea509abcdef0 ++ xor.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l) ;0107693cfa509abcdef0 ++ xor.l @(0xc:2,er3),@0xffff9abc:16 ;0107693c40509abc ++ xor.l @(0xc:2,er3),@0x9abcdef0:32 ;0107693c48509abcdef0 ++ ++ xor.l @-er3,@er1 ;01076d3c0150 ++ xor.l @-er3,@(0xc:2,er1) ;01076d3c3150 ++ xor.l @-er3,@-er1 ;01076d3cb150 ++ xor.l @-er3,@er1+ ;01076d3c8150 ++ xor.l @-er3,@er1- ;01076d3ca150 ++ xor.l @-er3,@+er1 ;01076d3c9150 ++ xor.l @-er3,@(0xffff9abc:16,er1) ;01076d3cc1509abc ++ xor.l @-er3,@(0x9abcdef0:32,er1) ;01076d3cc9509abcdef0 ++ xor.l @-er3,@(0xffff9abc:16,r2l.b) ;01076d3cd2509abc ++ xor.l @-er3,@(0xffff9abc:16,r2.w) ;01076d3ce2509abc ++ xor.l @-er3,@(0xffff9abc:16,er2.l) ;01076d3cf2509abc ++ xor.l @-er3,@(0x9abcdef0:32,r2l.b) ;01076d3cda509abcdef0 ++ xor.l @-er3,@(0x9abcdef0:32,r2.w) ;01076d3cea509abcdef0 ++ xor.l @-er3,@(0x9abcdef0:32,er2.l) ;01076d3cfa509abcdef0 ++ xor.l @-er3,@0xffff9abc:16 ;01076d3c40509abc ++ xor.l @-er3,@0x9abcdef0:32 ;01076d3c48509abcdef0 ++ ++ xor.l @er3+,@er1 ;01046d3c0150 ++ xor.l @er3+,@(0xc:2,er1) ;01046d3c3150 ++ xor.l @er3+,@-er1 ;01046d3cb150 ++ xor.l @er3+,@er1+ ;01046d3c8150 ++ xor.l @er3+,@er1- ;01046d3ca150 ++ xor.l @er3+,@+er1 ;01046d3c9150 ++ xor.l @er3+,@(0xffff9abc:16,er1) ;01046d3cc1509abc ++ xor.l @er3+,@(0x9abcdef0:32,er1) ;01046d3cc9509abcdef0 ++ xor.l @er3+,@(0xffff9abc:16,r2l.b) ;01046d3cd2509abc ++ xor.l @er3+,@(0xffff9abc:16,r2.w) ;01046d3ce2509abc ++ xor.l @er3+,@(0xffff9abc:16,er2.l) ;01046d3cf2509abc ++ xor.l @er3+,@(0x9abcdef0:32,r2l.b) ;01046d3cda509abcdef0 ++ xor.l @er3+,@(0x9abcdef0:32,r2.w) ;01046d3cea509abcdef0 ++ xor.l @er3+,@(0x9abcdef0:32,er2.l) ;01046d3cfa509abcdef0 ++ xor.l @er3+,@0xffff9abc:16 ;01046d3c40509abc ++ xor.l @er3+,@0x9abcdef0:32 ;01046d3c48509abcdef0 ++ ++ xor.l @er3-,@er1 ;01066d3c0150 ++ xor.l @er3-,@(0xc:2,er1) ;01066d3c3150 ++ xor.l @er3-,@-er1 ;01066d3cb150 ++ xor.l @er3-,@er1+ ;01066d3c8150 ++ xor.l @er3-,@er1- ;01066d3ca150 ++ xor.l @er3-,@+er1 ;01066d3c9150 ++ xor.l @er3-,@(0xffff9abc:16,er1) ;01066d3cc1509abc ++ xor.l @er3-,@(0x9abcdef0:32,er1) ;01066d3cc9509abcdef0 ++ xor.l @er3-,@(0xffff9abc:16,r2l.b) ;01066d3cd2509abc ++ xor.l @er3-,@(0xffff9abc:16,r2.w) ;01066d3ce2509abc ++ xor.l @er3-,@(0xffff9abc:16,er2.l) ;01066d3cf2509abc ++ xor.l @er3-,@(0x9abcdef0:32,r2l.b) ;01066d3cda509abcdef0 ++ xor.l @er3-,@(0x9abcdef0:32,r2.w) ;01066d3cea509abcdef0 ++ xor.l @er3-,@(0x9abcdef0:32,er2.l) ;01066d3cfa509abcdef0 ++ xor.l @er3-,@0xffff9abc:16 ;01066d3c40509abc ++ xor.l @er3-,@0x9abcdef0:32 ;01066d3c48509abcdef0 ++ ++ xor.l @+er3,@er1 ;01056d3c0150 ++ xor.l @+er3,@(0xc:2,er1) ;01056d3c3150 ++ xor.l @+er3,@-er1 ;01056d3cb150 ++ xor.l @+er3,@er1+ ;01056d3c8150 ++ xor.l @+er3,@er1- ;01056d3ca150 ++ xor.l @+er3,@+er1 ;01056d3c9150 ++ xor.l @+er3,@(0xffff9abc:16,er1) ;01056d3cc1509abc ++ xor.l @+er3,@(0x9abcdef0:32,er1) ;01056d3cc9509abcdef0 ++ xor.l @+er3,@(0xffff9abc:16,r2l.b) ;01056d3cd2509abc ++ xor.l @+er3,@(0xffff9abc:16,r2.w) ;01056d3ce2509abc ++ xor.l @+er3,@(0xffff9abc:16,er2.l) ;01056d3cf2509abc ++ xor.l @+er3,@(0x9abcdef0:32,r2l.b) ;01056d3cda509abcdef0 ++ xor.l @+er3,@(0x9abcdef0:32,r2.w) ;01056d3cea509abcdef0 ++ xor.l @+er3,@(0x9abcdef0:32,er2.l) ;01056d3cfa509abcdef0 ++ xor.l @+er3,@0xffff9abc:16 ;01056d3c40509abc ++ xor.l @+er3,@0x9abcdef0:32 ;01056d3c48509abcdef0 ++ ++ xor.l @(0x1234:16,er3),@er1 ;01046f3c12340150 ++ xor.l @(0x1234:16,er3),@(0xc:2,er1) ;01046f3c12343150 ++ xor.l @(0x1234:16,er3),@-er1 ;01046f3c1234b150 ++ xor.l @(0x1234:16,er3),@er1+ ;01046f3c12348150 ++ xor.l @(0x1234:16,er3),@er1- ;01046f3c1234a150 ++ xor.l @(0x1234:16,er3),@+er1 ;01046f3c12349150 ++ xor.l @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01046f3c1234c1509abc ++ xor.l @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01046f3c1234c9509abcdef0 ++ xor.l @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01046f3c1234d2509abc ++ xor.l @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01046f3c1234e2509abc ++ xor.l @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01046f3c1234f2509abc ++ xor.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01046f3c1234da509abcdef0 ++ xor.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01046f3c1234ea509abcdef0 ++ xor.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01046f3c1234fa509abcdef0 ++ xor.l @(0x1234:16,er3),@0xffff9abc:16 ;01046f3c123440509abc ++ xor.l @(0x1234:16,er3),@0x9abcdef0:32 ;01046f3c123448509abcdef0 ++ ++ xor.l @(0x12345678:32,er3),@er1 ;78b46b2c123456780150 ++ xor.l @(0x12345678:32,er3),@(0xc:2,er1) ;78b46b2c123456783150 ++ xor.l @(0x12345678:32,er3),@-er1 ;78b46b2c12345678b150 ++ xor.l @(0x12345678:32,er3),@er1+ ;78b46b2c123456788150 ++ xor.l @(0x12345678:32,er3),@er1- ;78b46b2c12345678a150 ++ xor.l @(0x12345678:32,er3),@+er1 ;78b46b2c123456789150 ++ xor.l @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78b46b2c12345678c1509abc ++ xor.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78b46b2c12345678c9509abcdef0 ++ xor.l @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78b46b2c12345678d2509abc ++ xor.l @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78b46b2c12345678e2509abc ++ xor.l @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78b46b2c12345678f2509abc ++ xor.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78b46b2c12345678da509abcdef0 ++ xor.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78b46b2c12345678ea509abcdef0 ++ xor.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78b46b2c12345678fa509abcdef0 ++ xor.l @(0x12345678:32,er3),@0xffff9abc:16 ;78b46b2c1234567840509abc ++ xor.l @(0x12345678:32,er3),@0x9abcdef0:32 ;78b46b2c1234567848509abcdef0 ++ ++ xor.l @(0x1234:16,r3l.b),@er1 ;01056f3c12340150 ++ xor.l @(0x1234:16,r3l.b),@(0xc:2,er1) ;01056f3c12343150 ++ xor.l @(0x1234:16,r3l.b),@-er1 ;01056f3c1234b150 ++ xor.l @(0x1234:16,r3l.b),@er1+ ;01056f3c12348150 ++ xor.l @(0x1234:16,r3l.b),@er1- ;01056f3c1234a150 ++ xor.l @(0x1234:16,r3l.b),@+er1 ;01056f3c12349150 ++ xor.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01056f3c1234c1509abc ++ xor.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01056f3c1234c9509abcdef0 ++ xor.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01056f3c1234d2509abc ++ xor.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01056f3c1234e2509abc ++ xor.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01056f3c1234f2509abc ++ xor.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01056f3c1234da509abcdef0 ++ xor.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01056f3c1234ea509abcdef0 ++ xor.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01056f3c1234fa509abcdef0 ++ xor.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;01056f3c123440509abc ++ xor.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01056f3c123448509abcdef0 ++ ++ xor.l @(0x1234:16,r3.w),@er1 ;01066f3c12340150 ++ xor.l @(0x1234:16,r3.w),@(0xc:2,er1) ;01066f3c12343150 ++ xor.l @(0x1234:16,r3.w),@-er1 ;01066f3c1234b150 ++ xor.l @(0x1234:16,r3.w),@er1+ ;01066f3c12348150 ++ xor.l @(0x1234:16,r3.w),@er1- ;01066f3c1234a150 ++ xor.l @(0x1234:16,r3.w),@+er1 ;01066f3c12349150 ++ xor.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01066f3c1234c1509abc ++ xor.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01066f3c1234c9509abcdef0 ++ xor.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01066f3c1234d2509abc ++ xor.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01066f3c1234e2509abc ++ xor.l @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01066f3c1234f2509abc ++ xor.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01066f3c1234da509abcdef0 ++ xor.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01066f3c1234ea509abcdef0 ++ xor.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01066f3c1234fa509abcdef0 ++ xor.l @(0x1234:16,r3.w),@0xffff9abc:16 ;01066f3c123440509abc ++ xor.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;01066f3c123448509abcdef0 ++ ++ xor.l @(0x1234:16,er3.l),@er1 ;01076f3c12340150 ++ xor.l @(0x1234:16,er3.l),@(0xc:2,er1) ;01076f3c12343150 ++ xor.l @(0x1234:16,er3.l),@-er1 ;01076f3c1234b150 ++ xor.l @(0x1234:16,er3.l),@er1+ ;01076f3c12348150 ++ xor.l @(0x1234:16,er3.l),@er1- ;01076f3c1234a150 ++ xor.l @(0x1234:16,er3.l),@+er1 ;01076f3c12349150 ++ xor.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01076f3c1234c1509abc ++ xor.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01076f3c1234c9509abcdef0 ++ xor.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01076f3c1234d2509abc ++ xor.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01076f3c1234e2509abc ++ xor.l @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01076f3c1234f2509abc ++ xor.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01076f3c1234da509abcdef0 ++ xor.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01076f3c1234ea509abcdef0 ++ xor.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01076f3c1234fa509abcdef0 ++ xor.l @(0x1234:16,er3.l),@0xffff9abc:16 ;01076f3c123440509abc ++ xor.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;01076f3c123448509abcdef0 ++ ++ xor.l @(0x12345678:32,r3l.b),@er1 ;78b56b2c123456780150 ++ xor.l @(0x12345678:32,r3l.b),@(0xc:2,er1) ;78b56b2c123456783150 ++ xor.l @(0x12345678:32,r3l.b),@-er1 ;78b56b2c12345678b150 ++ xor.l @(0x12345678:32,r3l.b),@er1+ ;78b56b2c123456788150 ++ xor.l @(0x12345678:32,r3l.b),@er1- ;78b56b2c12345678a150 ++ xor.l @(0x12345678:32,r3l.b),@+er1 ;78b56b2c123456789150 ++ xor.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78b56b2c12345678c1509abc ++ xor.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78b56b2c12345678c9509abcdef0 ++ xor.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78b56b2c12345678d2509abc ++ xor.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78b56b2c12345678e2509abc ++ xor.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78b56b2c12345678f2509abc ++ xor.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78b56b2c12345678da509abcdef0 ++ xor.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78b56b2c12345678ea509abcdef0 ++ xor.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78b56b2c12345678fa509abcdef0 ++ xor.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78b56b2c1234567840509abc ++ xor.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78b56b2c1234567848509abcdef0 ++ ++ xor.l @(0x12345678:32,r3.w),@er1 ;78b66b2c123456780150 ++ xor.l @(0x12345678:32,r3.w),@(0xc:2,er1) ;78b66b2c123456783150 ++ xor.l @(0x12345678:32,r3.w),@-er1 ;78b66b2c12345678b150 ++ xor.l @(0x12345678:32,r3.w),@er1+ ;78b66b2c123456788150 ++ xor.l @(0x12345678:32,r3.w),@er1- ;78b66b2c12345678a150 ++ xor.l @(0x12345678:32,r3.w),@+er1 ;78b66b2c123456789150 ++ xor.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78b66b2c12345678c1509abc ++ xor.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78b66b2c12345678c9509abcdef0 ++ xor.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78b66b2c12345678d2509abc ++ xor.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78b66b2c12345678e2509abc ++ xor.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78b66b2c12345678f2509abc ++ xor.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78b66b2c12345678da509abcdef0 ++ xor.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78b66b2c12345678ea509abcdef0 ++ xor.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78b66b2c12345678fa509abcdef0 ++ xor.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;78b66b2c1234567840509abc ++ xor.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78b66b2c1234567848509abcdef0 ++ ++ xor.l @(0x12345678:32,er3.l),@er1 ;78b76b2c123456780150 ++ xor.l @(0x12345678:32,er3.l),@(0xc:2,er1) ;78b76b2c123456783150 ++ xor.l @(0x12345678:32,er3.l),@-er1 ;78b76b2c12345678b150 ++ xor.l @(0x12345678:32,er3.l),@er1+ ;78b76b2c123456788150 ++ xor.l @(0x12345678:32,er3.l),@er1- ;78b76b2c12345678a150 ++ xor.l @(0x12345678:32,er3.l),@+er1 ;78b76b2c123456789150 ++ xor.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78b76b2c12345678c1509abc ++ xor.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78b76b2c12345678c9509abcdef0 ++ xor.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78b76b2c12345678d2509abc ++ xor.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78b76b2c12345678e2509abc ++ xor.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78b76b2c12345678f2509abc ++ xor.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78b76b2c12345678da509abcdef0 ++ xor.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78b76b2c12345678ea509abcdef0 ++ xor.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78b76b2c12345678fa509abcdef0 ++ xor.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;78b76b2c1234567840509abc ++ xor.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78b76b2c1234567848509abcdef0 ++ ++ xor.l @0x1234:16,@er1 ;01046b0c12340150 ++ xor.l @0x1234:16,@(0xc:2,er1) ;01046b0c12343150 ++ xor.l @0x1234:16,@-er1 ;01046b0c1234b150 ++ xor.l @0x1234:16,@er1+ ;01046b0c12348150 ++ xor.l @0x1234:16,@er1- ;01046b0c1234a150 ++ xor.l @0x1234:16,@+er1 ;01046b0c12349150 ++ xor.l @0x1234:16,@(0xffff9abc:16,er1) ;01046b0c1234c1509abc ++ xor.l @0x1234:16,@(0x9abcdef0:32,er1) ;01046b0c1234c9509abcdef0 ++ xor.l @0x1234:16,@(0xffff9abc:16,r2l.b) ;01046b0c1234d2509abc ++ xor.l @0x1234:16,@(0xffff9abc:16,r2.w) ;01046b0c1234e2509abc ++ xor.l @0x1234:16,@(0xffff9abc:16,er2.l) ;01046b0c1234f2509abc ++ xor.l @0x1234:16,@(0x9abcdef0:32,r2l.b) ;01046b0c1234da509abcdef0 ++ xor.l @0x1234:16,@(0x9abcdef0:32,r2.w) ;01046b0c1234ea509abcdef0 ++ xor.l @0x1234:16,@(0x9abcdef0:32,er2.l) ;01046b0c1234fa509abcdef0 ++ xor.l @0x1234:16,@0xffff9abc:16 ;01046b0c123440509abc ++ xor.l @0x1234:16,@0x9abcdef0:32 ;01046b0c123448509abcdef0 ++ ++ xor.l @0x12345678:32,@er1 ;01046b2c123456780150 ++ xor.l @0x12345678:32,@(0xc:2,er1) ;01046b2c123456783150 ++ xor.l @0x12345678:32,@-er1 ;01046b2c12345678b150 ++ xor.l @0x12345678:32,@er1+ ;01046b2c123456788150 ++ xor.l @0x12345678:32,@er1- ;01046b2c12345678a150 ++ xor.l @0x12345678:32,@+er1 ;01046b2c123456789150 ++ xor.l @0x12345678:32,@(0xffff9abc:16,er1) ;01046b2c12345678c1509abc ++ xor.l @0x12345678:32,@(0x9abcdef0:32,er1) ;01046b2c12345678c9509abcdef0 ++ xor.l @0x12345678:32,@(0xffff9abc:16,r2l.b) ;01046b2c12345678d2509abc ++ xor.l @0x12345678:32,@(0xffff9abc:16,r2.w) ;01046b2c12345678e2509abc ++ xor.l @0x12345678:32,@(0xffff9abc:16,er2.l) ;01046b2c12345678f2509abc ++ xor.l @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;01046b2c12345678da509abcdef0 ++ xor.l @0x12345678:32,@(0x9abcdef0:32,r2.w) ;01046b2c12345678ea509abcdef0 ++ xor.l @0x12345678:32,@(0x9abcdef0:32,er2.l) ;01046b2c12345678fa509abcdef0 ++ xor.l @0x12345678:32,@0xffff9abc:16 ;01046b2c1234567840509abc ++ xor.l @0x12345678:32,@0x9abcdef0:32 ;01046b2c1234567848509abcdef0 ++ ++ .end diff --git a/gas/testsuite/gas/h8300/t10_and.exp b/gas/testsuite/gas/h8300/t10_and.exp new file mode 100644 -index 0000000..c4f43e8 +index 0000000..a88d353 --- /dev/null +++ b/gas/testsuite/gas/h8300/t10_and.exp -@@ -0,0 +1,3019 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,3018 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1180355,989 +1187527,988 @@ index 0000000..c4f43e8 + diff --git a/gas/testsuite/gas/h8300/t10_and.s b/gas/testsuite/gas/h8300/t10_and.s new file mode 100644 -index 0000000..84ef3eb +index 0000000..9fcb261 --- /dev/null +++ b/gas/testsuite/gas/h8300/t10_and.s @@ -0,0 +1,971 @@ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+;log_1 -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ .h8300sx -+ .text -+_start: -+ and.b #0x12:8,r1h ;e112 -+ and.b #0x12:8,@er1 ;7d10e012 -+ and.b #0x12:8,@(0x3:2,er1) ;01776818e012 -+ and.b #0x12:8,@er1+ ;01746c18e012 -+ and.b #0x12:8,@-er1 ;01776c18e012 -+ and.b #0x12:8,@+er1 ;01756c18e012 -+ and.b #0x12:8,@er1- ;01766c18e012 -+ and.b #0x12:8,@(0x1234:16,er1) ;01746e181234e012 -+ and.b #0x12:8,@(0x12345678:32,er1) ;78146a2812345678e012 -+ and.b #0x12:8,@(0x1234:16,r2l.b) ;01756e281234e012 -+ and.b #0x12:8,@(0x1234:16,r2.w) ;01766e281234e012 -+ and.b #0x12:8,@(0x1234:16,er2.l) ;01776e281234e012 -+ and.b #0x12:8,@(0x12345678:32,r2l.b) ;78256a2812345678e012 -+ and.b #0x12:8,@(0x12345678:32,r2.w) ;78266a2812345678e012 -+ and.b #0x12:8,@(0x12345678:32,er2.l) ;78276a2812345678e012 -+ and.b #0x12:8,@0xffffff12:8 ;7f12e012 -+ and.b #0x12:8,@0x1234:16 ;6a181234e012 -+ and.b #0x12:8,@0x12345678:32 ;6a3812345678e012 -+ -+ and.b r3h,r1h ;1631 -+ -+ and.b r3h,@er1 ;7d101630 -+ and.b r3h,@(0x3:2,er1) ;01793163 -+ and.b r3h,@er1+ ;01798163 -+ and.b r3h,@-er1 ;0179b163 -+ and.b r3h,@+er1 ;01799163 -+ and.b r3h,@er1- ;0179a163 -+ and.b r3h,@(0x1234:16,er1) ;0179c1631234 -+ and.b r3h,@(0x12345678:32,er1) ;0179c96312345678 -+ and.b r3h,@(0x1234:16,r2l.b) ;0179d2631234 -+ and.b r3h,@(0x1234:16,r2.w) ;0179e2631234 -+ and.b r3h,@(0x1234:16,er2.l) ;0179f2631234 -+ and.b r3h,@(0x12345678:32,r2l.b) ;0179da6312345678 -+ and.b r3h,@(0x12345678:32,r2.w) ;0179ea6312345678 -+ and.b r3h,@(0x12345678:32,er2.l) ;0179fa6312345678 -+ and.b r3h,@0xffffff12:8 ;7f121630 -+ and.b r3h,@0x1234:16 ;6a1812341630 -+ and.b r3h,@0x12345678:32 ;6a38123456781630 -+ -+ and.b @er3,r1h ;7c301601 -+ and.b @(0x3:2,er3),r1h ;017a3361 -+ and.b @er3+,r1h ;017a8361 -+ and.b @-er3,r1h ;017ab361 -+ and.b @+er3,r1h ;017a9361 -+ and.b @er3-,r1h ;017aa361 -+ and.b @(0x1234:16,er1),r1h ;017ac1611234 -+ and.b @(0x12345678:32,er1),r1h ;017ac96112345678 -+ and.b @(0x1234:16,r2l.b),r1h ;017ad2611234 -+ and.b @(0x1234:16,r2.w),r1h ;017ae2611234 -+ and.b @(0x1234:16,er2.l),r1h ;017af2611234 -+ and.b @(0x12345678:32,r2l.b),r1h ;017ada6112345678 -+ and.b @(0x12345678:32,r2.w),r1h ;017aea6112345678 -+ and.b @(0x12345678:32,er2.l),r1h ;017afa6112345678 -+ and.b @0xffffff12:8,r1h ;7e121601 -+ and.b @0x1234:16,r1h ;6a1012341601 -+ and.b @0x12345678:32,r1h ;6a30123456781601 -+ -+ and.b @er3,@er1 ;7c350160 -+ and.b @er3,@(3:2,er1) ;7c353160 -+ and.b @er3,@-er1 ;7c35b160 -+ and.b @er3,@er1+ ;7c358160 -+ and.b @er3,@er1- ;7c35a160 -+ and.b @er3,@+er1 ;7c359160 -+ and.b @er3,@(0xffff9abc:16,er1) ;7c35c1609abc -+ and.b @er3,@(0x9abcdef0:32,er1) ;7c35c9609abcdef0 -+ and.b @er3,@(0xffff9abc:16,r2l.b) ;7c35d2609abc -+ and.b @er3,@(0xffff9abc:16,r2.w) ;7c35e2609abc -+ and.b @er3,@(0xffff9abc:16,er2.l) ;7c35f2609abc -+ and.b @er3,@(0x9abcdef0:32,r2l.b) ;7c35da609abcdef0 -+ and.b @er3,@(0x9abcdef0:32,r2.w) ;7c35ea609abcdef0 -+ and.b @er3,@(0x9abcdef0:32,er2.l) ;7c35fa609abcdef0 -+ and.b @er3,@0xffff9abc:16 ;7c3540609abc -+ and.b @er3,@0x9abcdef0:32 ;7c3548609abcdef0 -+ -+ and.b @-er3,@er1 ;01776c3c0160 -+ and.b @-er3,@(3:2,er1) ;01776c3c3160 -+ and.b @-er3,@-er1 ;01776c3cb160 -+ and.b @-er3,@er1+ ;01776c3c8160 -+ and.b @-er3,@er1- ;01776c3ca160 -+ and.b @-er3,@+er1 ;01776c3c9160 -+ and.b @-er3,@(0xffff9abc:16,er1) ;01776c3cc1609abc -+ and.b @-er3,@(0x9abcdef0:32,er1) ;01776c3cc9609abcdef0 -+ and.b @-er3,@(0xffff9abc:16,r2l.b) ;01776c3cd2609abc -+ and.b @-er3,@(0xffff9abc:16,r2.w) ;01776c3ce2609abc -+ and.b @-er3,@(0xffff9abc:16,er2.l) ;01776c3cf2609abc -+ and.b @-er3,@(0x9abcdef0:32,r2l.b) ;01776c3cda609abcdef0 -+ and.b @-er3,@(0x9abcdef0:32,r2.w) ;01776c3cea609abcdef0 -+ and.b @-er3,@(0x9abcdef0:32,er2.l) ;01776c3cfa609abcdef0 -+ and.b @-er3,@0xffff9abc:16 ;01776c3c40609abc -+ and.b @-er3,@0x9abcdef0:32 ;01776c3c48609abcdef0 -+ -+ and.b @er3+,@er1 ;01746c3c0160 -+ and.b @er3+,@(3:2,er1) ;01746c3c3160 -+ and.b @er3+,@-er1 ;01746c3cb160 -+ and.b @er3+,@er1+ ;01746c3c8160 -+ and.b @er3+,@er1- ;01746c3ca160 -+ and.b @er3+,@+er1 ;01746c3c9160 -+ and.b @er3+,@(0xffff9abc:16,er1) ;01746c3cc1609abc -+ and.b @er3+,@(0x9abcdef0:32,er1) ;01746c3cc9609abcdef0 -+ and.b @er3+,@(0xffff9abc:16,r2l.b) ;01746c3cd2609abc -+ and.b @er3+,@(0xffff9abc:16,r2.w) ;01746c3ce2609abc -+ and.b @er3+,@(0xffff9abc:16,er2.l) ;01746c3cf2609abc -+ and.b @er3+,@(0x9abcdef0:32,r2l.b) ;01746c3cda609abcdef0 -+ and.b @er3+,@(0x9abcdef0:32,r2.w) ;01746c3cea609abcdef0 -+ and.b @er3+,@(0x9abcdef0:32,er2.l) ;01746c3cfa609abcdef0 -+ and.b @er3+,@0xffff9abc:16 ;01746c3c40609abc -+ and.b @er3+,@0x9abcdef0:32 ;01746c3c48609abcdef0 -+ -+ and.b @er3-,@er1 ;01766c3c0160 -+ and.b @er3-,@(3:2,er1) ;01766c3c3160 -+ and.b @er3-,@-er1 ;01766c3cb160 -+ and.b @er3-,@er1+ ;01766c3c8160 -+ and.b @er3-,@er1- ;01766c3ca160 -+ and.b @er3-,@+er1 ;01766c3c9160 -+ and.b @er3-,@(0xffff9abc:16,er1) ;01766c3cc1609abc -+ and.b @er3-,@(0x9abcdef0:32,er1) ;01766c3cc9609abcdef0 -+ and.b @er3-,@(0xffff9abc:16,r2l.b) ;01766c3cd2609abc -+ and.b @er3-,@(0xffff9abc:16,r2.w) ;01766c3ce2609abc -+ and.b @er3-,@(0xffff9abc:16,er2.l) ;01766c3cf2609abc -+ and.b @er3-,@(0x9abcdef0:32,r2l.b) ;01766c3cda609abcdef0 -+ and.b @er3-,@(0x9abcdef0:32,r2.w) ;01766c3cea609abcdef0 -+ and.b @er3-,@(0x9abcdef0:32,er2.l) ;01766c3cfa609abcdef0 -+ and.b @er3-,@0xffff9abc:16 ;01766c3c40609abc -+ and.b @er3-,@0x9abcdef0:32 ;01766c3c48609abcdef0 -+ -+ and.b @+er3,@er1 ;01756c3c0160 -+ and.b @+er3,@(3:2,er1) ;01756c3c3160 -+ and.b @+er3,@-er1 ;01756c3cb160 -+ and.b @+er3,@er1+ ;01756c3c8160 -+ and.b @+er3,@er1- ;01756c3ca160 -+ and.b @+er3,@+er1 ;01756c3c9160 -+ and.b @+er3,@(0xffff9abc:16,er1) ;01756c3cc1609abc -+ and.b @+er3,@(0x9abcdef0:32,er1) ;01756c3cc9609abcdef0 -+ and.b @+er3,@(0xffff9abc:16,r2l.b) ;01756c3cd2609abc -+ and.b @+er3,@(0xffff9abc:16,r2.w) ;01756c3ce2609abc -+ and.b @+er3,@(0xffff9abc:16,er2.l) ;01756c3cf2609abc -+ and.b @+er3,@(0x9abcdef0:32,r2l.b) ;01756c3cda609abcdef0 -+ and.b @+er3,@(0x9abcdef0:32,r2.w) ;01756c3cea609abcdef0 -+ and.b @+er3,@(0x9abcdef0:32,er2.l) ;01756c3cfa609abcdef0 -+ and.b @+er3,@0xffff9abc:16 ;01756c3c40609abc -+ and.b @+er3,@0x9abcdef0:32 ;01756c3c48609abcdef0 -+ -+ and.b @(0x1234:16,er3),@er1 ;01746e3c12340160 -+ and.b @(0x1234:16,er3),@(3:2,er1) ;01746e3c12343160 -+ and.b @(0x1234:16,er3),@-er1 ;01746e3c1234b160 -+ and.b @(0x1234:16,er3),@er1+ ;01746e3c12348160 -+ and.b @(0x1234:16,er3),@er1- ;01746e3c1234a160 -+ and.b @(0x1234:16,er3),@+er1 ;01746e3c12349160 -+ and.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01746e3c1234c1609abc -+ and.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01746e3c1234c9609abcdef0 -+ and.b @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01746e3c1234d2609abc -+ and.b @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01746e3c1234e2609abc -+ and.b @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01746e3c1234f2609abc -+ and.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01746e3c1234da609abcdef0 -+ and.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01746e3c1234ea609abcdef0 -+ and.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01746e3c1234fa609abcdef0 -+ and.b @(0x1234:16,er3),@0xffff9abc:16 ;01746e3c123440609abc -+ and.b @(0x1234:16,er3),@0x9abcdef0:32 ;01746e3c123448609abcdef0 -+ -+ and.b @(0x12345678:32,er3),@er1 ;78346a2c123456780160 -+ and.b @(0x12345678:32,er3),@(3:2,er1) ;78346a2c123456783160 -+ and.b @(0x12345678:32,er3),@-er1 ;78346a2c12345678b160 -+ and.b @(0x12345678:32,er3),@er1+ ;78346a2c123456788160 -+ and.b @(0x12345678:32,er3),@er1- ;78346a2c12345678a160 -+ and.b @(0x12345678:32,er3),@+er1 ;78346a2c123456789160 -+ and.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346a2c12345678c1609abc -+ and.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346a2c12345678c9609abcdef0 -+ and.b @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346a2c12345678d2609abc -+ and.b @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346a2c12345678e2609abc -+ and.b @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346a2c12345678f2609abc -+ and.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346a2c12345678da609abcdef0 -+ and.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346a2c12345678ea609abcdef0 -+ and.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346a2c12345678fa609abcdef0 -+ and.b @(0x12345678:32,er3),@0xffff9abc:16 ;78346a2c1234567840609abc -+ and.b @(0x12345678:32,er3),@0x9abcdef0:32 ;78346a2c1234567848609abcdef0 -+ -+ and.b @(0x1234:16,r3l.b),@er1 ;01756e3c12340160 -+ and.b @(0x1234:16,r3l.b),@(3:2,er1) ;01756e3c12343160 -+ and.b @(0x1234:16,r3l.b),@-er1 ;01756e3c1234b160 -+ and.b @(0x1234:16,r3l.b),@er1+ ;01756e3c12348160 -+ and.b @(0x1234:16,r3l.b),@er1- ;01756e3c1234a160 -+ and.b @(0x1234:16,r3l.b),@+er1 ;01756e3c12349160 -+ and.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01756e3c1234c1609abc -+ and.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01756e3c1234c9609abcdef0 -+ and.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01756e3c1234d2609abc -+ and.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01756e3c1234e2609abc -+ and.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01756e3c1234f2609abc -+ and.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01756e3c1234da609abcdef0 -+ and.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01756e3c1234ea609abcdef0 -+ and.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01756e3c1234fa609abcdef0 -+ and.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;01756e3c123440609abc -+ and.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01756e3c123448609abcdef0 -+ -+ and.b @(0x1234:16,r3.w),@er1 ;01766e3c12340160 -+ and.b @(0x1234:16,r3.w),@(3:2,er1) ;01766e3c12343160 -+ and.b @(0x1234:16,r3.w),@-er1 ;01766e3c1234b160 -+ and.b @(0x1234:16,r3.w),@er1+ ;01766e3c12348160 -+ and.b @(0x1234:16,r3.w),@er1- ;01766e3c1234a160 -+ and.b @(0x1234:16,r3.w),@+er1 ;01766e3c12349160 -+ and.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01766e3c1234c1609abc -+ and.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01766e3c1234c9609abcdef0 -+ and.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01766e3c1234d2609abc -+ and.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01766e3c1234e2609abc -+ and.b @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01766e3c1234f2609abc -+ and.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01766e3c1234da609abcdef0 -+ and.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01766e3c1234ea609abcdef0 -+ and.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01766e3c1234fa609abcdef0 -+ and.b @(0x1234:16,r3.w),@0xffff9abc:16 ;01766e3c123440609abc -+ and.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;01766e3c123448609abcdef0 -+ -+ and.b @(0x1234:16,er3.l),@er1 ;01776e3c12340160 -+ and.b @(0x1234:16,er3.l),@(3:2,er1) ;01776e3c12343160 -+ and.b @(0x1234:16,er3.l),@-er1 ;01776e3c1234b160 -+ and.b @(0x1234:16,er3.l),@er1+ ;01776e3c12348160 -+ and.b @(0x1234:16,er3.l),@er1- ;01776e3c1234a160 -+ and.b @(0x1234:16,er3.l),@+er1 ;01776e3c12349160 -+ and.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01776e3c1234c1609abc -+ and.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01776e3c1234c9609abcdef0 -+ and.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01776e3c1234d2609abc -+ and.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01776e3c1234e2609abc -+ and.b @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01776e3c1234f2609abc -+ and.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01776e3c1234da609abcdef0 -+ and.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01776e3c1234ea609abcdef0 -+ and.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01776e3c1234fa609abcdef0 -+ and.b @(0x1234:16,er3.l),@0xffff9abc:16 ;01776e3c123440609abc -+ and.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;01776e3c123448609abcdef0 -+ -+ and.b @(0x12345678:32,r3l.b),@er1 ;78356a2c123456780160 -+ and.b @(0x12345678:32,r3l.b),@(3:2,er1) ;78356a2c123456783160 -+ and.b @(0x12345678:32,r3l.b),@-er1 ;78356a2c12345678b160 -+ and.b @(0x12345678:32,r3l.b),@er1+ ;78356a2c123456788160 -+ and.b @(0x12345678:32,r3l.b),@er1- ;78356a2c12345678a160 -+ and.b @(0x12345678:32,r3l.b),@+er1 ;78356a2c123456789160 -+ and.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356a2c12345678c1609abc -+ and.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356a2c12345678c9609abcdef0 -+ and.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356a2c12345678d2609abc -+ and.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356a2c12345678e2609abc -+ and.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356a2c12345678f2609abc -+ and.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356a2c12345678da609abcdef0 -+ and.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356a2c12345678ea609abcdef0 -+ and.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356a2c12345678fa609abcdef0 -+ and.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356a2c1234567840609abc -+ and.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356a2c1234567848609abcdef0 -+ -+ and.b @(0x12345678:32,r3.w),@er1 ;78366a2c123456780160 -+ and.b @(0x12345678:32,r3.w),@(3:2,er1) ;78366a2c123456783160 -+ and.b @(0x12345678:32,r3.w),@-er1 ;78366a2c12345678b160 -+ and.b @(0x12345678:32,r3.w),@er1+ ;78366a2c123456788160 -+ and.b @(0x12345678:32,r3.w),@er1- ;78366a2c12345678a160 -+ and.b @(0x12345678:32,r3.w),@+er1 ;78366a2c123456789160 -+ and.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366a2c12345678c1609abc -+ and.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366a2c12345678c9609abcdef0 -+ and.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366a2c12345678d2609abc -+ and.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366a2c12345678e2609abc -+ and.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366a2c12345678f2609abc -+ and.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366a2c12345678da609abcdef0 -+ and.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366a2c12345678ea609abcdef0 -+ and.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366a2c12345678fa609abcdef0 -+ and.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366a2c1234567840609abc -+ and.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366a2c1234567848609abcdef0 -+ -+ and.b @(0x12345678:32,er3.l),@er1 ;78376a2c123456780160 -+ and.b @(0x12345678:32,er3.l),@(3:2,er1) ;78376a2c123456783160 -+ and.b @(0x12345678:32,er3.l),@-er1 ;78376a2c12345678b160 -+ and.b @(0x12345678:32,er3.l),@er1+ ;78376a2c123456788160 -+ and.b @(0x12345678:32,er3.l),@er1- ;78376a2c12345678a160 -+ and.b @(0x12345678:32,er3.l),@+er1 ;78376a2c123456789160 -+ and.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376a2c12345678c1609abc -+ and.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376a2c12345678c9609abcdef0 -+ and.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376a2c12345678d2609abc -+ and.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376a2c12345678e2609abc -+ and.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376a2c12345678f2609abc -+ and.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376a2c12345678da609abcdef0 -+ and.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376a2c12345678ea609abcdef0 -+ and.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376a2c12345678fa609abcdef0 -+ and.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376a2c1234567840609abc -+ and.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376a2c1234567848609abcdef0 -+ -+ and.b @0x1234:16,@er1 ;6a1512340160 -+ and.b @0x1234:16,@(3:2,er1) ;6a1512343160 -+ and.b @0x1234:16,@-er1 ;6a151234b160 -+ and.b @0x1234:16,@er1+ ;6a1512348160 -+ and.b @0x1234:16,@er1- ;6a151234a160 -+ and.b @0x1234:16,@+er1 ;6a1512349160 -+ and.b @0x1234:16,@(0xffff9abc:16,er1) ;6a151234c1609abc -+ and.b @0x1234:16,@(0x9abcdef0:32,er1) ;6a151234c9609abcdef0 -+ and.b @0x1234:16,@(0xffff9abc:16,r2l.b) ;6a151234d2609abc -+ and.b @0x1234:16,@(0xffff9abc:16,r2.w) ;6a151234e2609abc -+ and.b @0x1234:16,@(0xffff9abc:16,er2.l) ;6a151234f2609abc -+ and.b @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6a151234da609abcdef0 -+ and.b @0x1234:16,@(0x9abcdef0:32,r2.w) ;6a151234ea609abcdef0 -+ and.b @0x1234:16,@(0x9abcdef0:32,er2.l) ;6a151234fa609abcdef0 -+ and.b @0x1234:16,@0xffff9abc:16 ;6a15123440609abc -+ and.b @0x1234:16,@0x9abcdef0:32 ;6a15123448609abcdef0 -+ -+ and.b @0x12345678:32,@er1 ;6a35123456780160 -+ and.b @0x12345678:32,@(3:2,er1) ;6a35123456783160 -+ and.b @0x12345678:32,@-er1 ;6a3512345678b160 -+ and.b @0x12345678:32,@er1+ ;6a35123456788160 -+ and.b @0x12345678:32,@er1- ;6a3512345678a160 -+ and.b @0x12345678:32,@+er1 ;6a35123456789160 -+ and.b @0x12345678:32,@(0xffff9abc:16,er1) ;6a3512345678c1609abc -+ and.b @0x12345678:32,@(0x9abcdef0:32,er1) ;6a3512345678c9609abcdef0 -+ and.b @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6a3512345678d2609abc -+ and.b @0x12345678:32,@(0xffff9abc:16,r2.w) ;6a3512345678e2609abc -+ and.b @0x12345678:32,@(0xffff9abc:16,er2.l) ;6a3512345678f2609abc -+ and.b @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6a3512345678da609abcdef0 -+ and.b @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6a3512345678ea609abcdef0 -+ and.b @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6a3512345678fa609abcdef0 -+ and.b @0x12345678:32,@0xffff9abc:16 ;6a351234567840609abc -+ and.b @0x12345678:32,@0x9abcdef0:32 ;6a351234567848609abcdef0 -+ -+ and.w #0x1234:16,r1 ;79611234 -+ and.w #0x1234:16,@er1 ;015e01601234 -+ and.w #0x1234:16,@(0x6:2,er1) ;015e31601234 -+ and.w #0x1234:16,@er1+ ;015e81601234 -+ and.w #0x1234:16,@-er1 ;015eb1601234 -+ and.w #0x1234:16,@+er1 ;015e91601234 -+ and.w #0x1234:16,@er1- ;015ea1601234 -+ and.w #0x1234:16,@(0xffff9abc:16,er1) ;015ec1609abc1234 -+ and.w #0x1234:16,@(0x9abcdef0:32,er1) ;015ec9609abcdef01234 -+ and.w #0x1234:16,@(0xffff9abc:16,r2l.b) ;015ed2609abc1234 -+ and.w #0x1234:16,@(0xffff9abc:16,r2.w) ;015ee2609abc1234 -+ and.w #0x1234:16,@(0xffff9abc:16,er2.l) ;015ef2609abc1234 -+ and.w #0x1234:16,@(0x9abcdef0:32,r2l.b) ;015eda609abcdef01234 -+ and.w #0x1234:16,@(0x9abcdef0:32,r2.w) ;015eea609abcdef01234 -+ and.w #0x1234:16,@(0x9abcdef0:32,er2.l) ;015efa609abcdef01234 -+ and.w #0x1234:16,@0xffff9abc:16 ;015e40609abc1234 -+ and.w #0x1234:16,@0x9abcdef0:32 ;015e48609abcdef01234 -+ -+ and.w r3,r1 ;6631 -+ -+ and.w r3,@er1 ;7d906630 -+ and.w r3,@(0x6:2,er1) ;01593163 -+ and.w r3,@er1+ ;01598163 -+ and.w r3,@-er1 ;0159b163 -+ and.w r3,@+er1 ;01599163 -+ and.w r3,@er1- ;0159a163 -+ and.w r3,@(0x1234:16,er1) ;0159c1631234 -+ and.w r3,@(0x12345678:32,er1) ;0159c96312345678 -+ and.w r3,@(0x1234:16,r2l.b) ;0159d2631234 -+ and.w r3,@(0x1234:16,r2.w) ;0159e2631234 -+ and.w r3,@(0x1234:16,er2.l) ;0159f2631234 -+ and.w r3,@(0x12345678:32,r2l.b) ;0159da6312345678 -+ and.w r3,@(0x12345678:32,r2.w) ;0159ea6312345678 -+ and.w r3,@(0x12345678:32,er2.l) ;0159fa6312345678 -+ and.w r3,@0x1234:16 ;6b1812346630 -+ and.w r3,@0x12345678:32 ;6b38123456786630 -+ -+ and.w @er3,r1 ;7cb06601 -+ and.w @(0x6:2,er3),r1 ;015a3361 -+ and.w @er3+,r1 ;015a8361 -+ and.w @-er3,r1 ;015ab361 -+ and.w @+er3,r1 ;015a9361 -+ and.w @er3-,r1 ;015aa361 -+ and.w @(0x1234:16,er1),r1 ;015ac1611234 -+ and.w @(0x12345678:32,er1),r1 ;015ac96112345678 -+ and.w @(0x1234:16,r2l.b),r1 ;015ad2611234 -+ and.w @(0x1234:16,r2.w),r1 ;015ae2611234 -+ and.w @(0x1234:16,er2.l),r1 ;015af2611234 -+ and.w @(0x12345678:32,r2l.b),r1 ;015ada6112345678 -+ and.w @(0x12345678:32,r2.w),r1 ;015aea6112345678 -+ and.w @(0x12345678:32,er2.l),r1 ;015afa6112345678 -+ and.w @0x1234:16,r1 ;6b1012346601 -+ and.w @0x12345678:32,r1 ;6b30123456786601 -+ -+ and.w @er3,@er1 ;7cb50160 -+ and.w @er3,@(6:2,er1) ;7cb53160 -+ and.w @er3,@-er1 ;7cb5b160 -+ and.w @er3,@er1+ ;7cb58160 -+ and.w @er3,@er1- ;7cb5a160 -+ and.w @er3,@+er1 ;7cb59160 -+ and.w @er3,@(0xffff9abc:16,er1) ;7cb5c1609abc -+ and.w @er3,@(0x9abcdef0:32,er1) ;7cb5c9609abcdef0 -+ and.w @er3,@(0xffff9abc:16,r2l.b) ;7cb5d2609abc -+ and.w @er3,@(0xffff9abc:16,r2.w) ;7cb5e2609abc -+ and.w @er3,@(0xffff9abc:16,er2.l) ;7cb5f2609abc -+ and.w @er3,@(0x9abcdef0:32,r2l.b) ;7cb5da609abcdef0 -+ and.w @er3,@(0x9abcdef0:32,r2.w) ;7cb5ea609abcdef0 -+ and.w @er3,@(0x9abcdef0:32,er2.l) ;7cb5fa609abcdef0 -+ and.w @er3,@0xffff9abc:16 ;7cb540609abc -+ and.w @er3,@0x9abcdef0:32 ;7cb548609abcdef0 -+ -+ and.w @-er3,@er1 ;01576d3c0160 -+ and.w @-er3,@(6:2,er1) ;01576d3c3160 -+ and.w @-er3,@-er1 ;01576d3cb160 -+ and.w @-er3,@er1+ ;01576d3c8160 -+ and.w @-er3,@er1- ;01576d3ca160 -+ and.w @-er3,@+er1 ;01576d3c9160 -+ and.w @-er3,@(0xffff9abc:16,er1) ;01576d3cc1609abc -+ and.w @-er3,@(0x9abcdef0:32,er1) ;01576d3cc9609abcdef0 -+ and.w @-er3,@(0xffff9abc:16,r2l.b) ;01576d3cd2609abc -+ and.w @-er3,@(0xffff9abc:16,r2.w) ;01576d3ce2609abc -+ and.w @-er3,@(0xffff9abc:16,er2.l) ;01576d3cf2609abc -+ and.w @-er3,@(0x9abcdef0:32,r2l.b) ;01576d3cda609abcdef0 -+ and.w @-er3,@(0x9abcdef0:32,r2.w) ;01576d3cea609abcdef0 -+ and.w @-er3,@(0x9abcdef0:32,er2.l) ;01576d3cfa609abcdef0 -+ and.w @-er3,@0xffff9abc:16 ;01576d3c40609abc -+ and.w @-er3,@0x9abcdef0:32 ;01576d3c48609abcdef0 -+ -+ and.w @er3+,@er1 ;01546d3c0160 -+ and.w @er3+,@(6:2,er1) ;01546d3c3160 -+ and.w @er3+,@-er1 ;01546d3cb160 -+ and.w @er3+,@er1+ ;01546d3c8160 -+ and.w @er3+,@er1- ;01546d3ca160 -+ and.w @er3+,@+er1 ;01546d3c9160 -+ and.w @er3+,@(0xffff9abc:16,er1) ;01546d3cc1609abc -+ and.w @er3+,@(0x9abcdef0:32,er1) ;01546d3cc9609abcdef0 -+ and.w @er3+,@(0xffff9abc:16,r2l.b) ;01546d3cd2609abc -+ and.w @er3+,@(0xffff9abc:16,r2.w) ;01546d3ce2609abc -+ and.w @er3+,@(0xffff9abc:16,er2.l) ;01546d3cf2609abc -+ and.w @er3+,@(0x9abcdef0:32,r2l.b) ;01546d3cda609abcdef0 -+ and.w @er3+,@(0x9abcdef0:32,r2.w) ;01546d3cea609abcdef0 -+ and.w @er3+,@(0x9abcdef0:32,er2.l) ;01546d3cfa609abcdef0 -+ and.w @er3+,@0xffff9abc:16 ;01546d3c40609abc -+ and.w @er3+,@0x9abcdef0:32 ;01546d3c48609abcdef0 -+ -+ and.w @er3-,@er1 ;01566d3c0160 -+ and.w @er3-,@(6:2,er1) ;01566d3c3160 -+ and.w @er3-,@-er1 ;01566d3cb160 -+ and.w @er3-,@er1+ ;01566d3c8160 -+ and.w @er3-,@er1- ;01566d3ca160 -+ and.w @er3-,@+er1 ;01566d3c9160 -+ and.w @er3-,@(0xffff9abc:16,er1) ;01566d3cc1609abc -+ and.w @er3-,@(0x9abcdef0:32,er1) ;01566d3cc9609abcdef0 -+ and.w @er3-,@(0xffff9abc:16,r2l.b) ;01566d3cd2609abc -+ and.w @er3-,@(0xffff9abc:16,r2.w) ;01566d3ce2609abc -+ and.w @er3-,@(0xffff9abc:16,er2.l) ;01566d3cf2609abc -+ and.w @er3-,@(0x9abcdef0:32,r2l.b) ;01566d3cda609abcdef0 -+ and.w @er3-,@(0x9abcdef0:32,r2.w) ;01566d3cea609abcdef0 -+ and.w @er3-,@(0x9abcdef0:32,er2.l) ;01566d3cfa609abcdef0 -+ and.w @er3-,@0xffff9abc:16 ;01566d3c40609abc -+ and.w @er3-,@0x9abcdef0:32 ;01566d3c48609abcdef0 -+ -+ and.w @+er3,@er1 ;01556d3c0160 -+ and.w @+er3,@(6:2,er1) ;01556d3c3160 -+ and.w @+er3,@-er1 ;01556d3cb160 -+ and.w @+er3,@er1+ ;01556d3c8160 -+ and.w @+er3,@er1- ;01556d3ca160 -+ and.w @+er3,@+er1 ;01556d3c9160 -+ and.w @+er3,@(0xffff9abc:16,er1) ;01556d3cc1609abc -+ and.w @+er3,@(0x9abcdef0:32,er1) ;01556d3cc9609abcdef0 -+ and.w @+er3,@(0xffff9abc:16,r2l.b) ;01556d3cd2609abc -+ and.w @+er3,@(0xffff9abc:16,r2.w) ;01556d3ce2609abc -+ and.w @+er3,@(0xffff9abc:16,er2.l) ;01556d3cf2609abc -+ and.w @+er3,@(0x9abcdef0:32,r2l.b) ;01556d3cda609abcdef0 -+ and.w @+er3,@(0x9abcdef0:32,r2.w) ;01556d3cea609abcdef0 -+ and.w @+er3,@(0x9abcdef0:32,er2.l) ;01556d3cfa609abcdef0 -+ and.w @+er3,@0xffff9abc:16 ;01556d3c40609abc -+ and.w @+er3,@0x9abcdef0:32 ;01556d3c48609abcdef0 -+ -+ and.w @(0x1234:16,er3),@er1 ;01546f3c12340160 -+ and.w @(0x1234:16,er3),@(6:2,er1) ;01546f3c12343160 -+ and.w @(0x1234:16,er3),@-er1 ;01546f3c1234b160 -+ and.w @(0x1234:16,er3),@er1+ ;01546f3c12348160 -+ and.w @(0x1234:16,er3),@er1- ;01546f3c1234a160 -+ and.w @(0x1234:16,er3),@+er1 ;01546f3c12349160 -+ and.w @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01546f3c1234c1609abc -+ and.w @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01546f3c1234c9609abcdef0 -+ and.w @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01546f3c1234d2609abc -+ and.w @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01546f3c1234e2609abc -+ and.w @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01546f3c1234f2609abc -+ and.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01546f3c1234da609abcdef0 -+ and.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01546f3c1234ea609abcdef0 -+ and.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01546f3c1234fa609abcdef0 -+ and.w @(0x1234:16,er3),@0xffff9abc:16 ;01546f3c123440609abc -+ and.w @(0x1234:16,er3),@0x9abcdef0:32 ;01546f3c123448609abcdef0 -+ -+ and.w @(0x12345678:32,er3),@er1 ;78346b2c123456780160 -+ and.w @(0x12345678:32,er3),@(6:2,er1) ;78346b2c123456783160 -+ and.w @(0x12345678:32,er3),@-er1 ;78346b2c12345678b160 -+ and.w @(0x12345678:32,er3),@er1+ ;78346b2c123456788160 -+ and.w @(0x12345678:32,er3),@er1- ;78346b2c12345678a160 -+ and.w @(0x12345678:32,er3),@+er1 ;78346b2c123456789160 -+ and.w @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346b2c12345678c1609abc -+ and.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346b2c12345678c9609abcdef0 -+ and.w @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346b2c12345678d2609abc -+ and.w @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346b2c12345678e2609abc -+ and.w @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346b2c12345678f2609abc -+ and.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346b2c12345678da609abcdef0 -+ and.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346b2c12345678ea609abcdef0 -+ and.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346b2c12345678fa609abcdef0 -+ and.w @(0x12345678:32,er3),@0xffff9abc:16 ;78346b2c1234567840609abc -+ and.w @(0x12345678:32,er3),@0x9abcdef0:32 ;78346b2c1234567848609abcdef0 -+ -+ and.w @(0x1234:16,r3l.b),@er1 ;01556f3c12340160 -+ and.w @(0x1234:16,r3l.b),@(6:2,er1) ;01556f3c12343160 -+ and.w @(0x1234:16,r3l.b),@-er1 ;01556f3c1234b160 -+ and.w @(0x1234:16,r3l.b),@er1+ ;01556f3c12348160 -+ and.w @(0x1234:16,r3l.b),@er1- ;01556f3c1234a160 -+ and.w @(0x1234:16,r3l.b),@+er1 ;01556f3c12349160 -+ and.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01556f3c1234c1609abc -+ and.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01556f3c1234c9609abcdef0 -+ and.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01556f3c1234d2609abc -+ and.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01556f3c1234e2609abc -+ and.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01556f3c1234f2609abc -+ and.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01556f3c1234da609abcdef0 -+ and.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01556f3c1234ea609abcdef0 -+ and.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01556f3c1234fa609abcdef0 -+ and.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;01556f3c123440609abc -+ and.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01556f3c123448609abcdef0 -+ -+ and.w @(0x1234:16,r3.w),@er1 ;01566f3c12340160 -+ and.w @(0x1234:16,r3.w),@(6:2,er1) ;01566f3c12343160 -+ and.w @(0x1234:16,r3.w),@-er1 ;01566f3c1234b160 -+ and.w @(0x1234:16,r3.w),@er1+ ;01566f3c12348160 -+ and.w @(0x1234:16,r3.w),@er1- ;01566f3c1234a160 -+ and.w @(0x1234:16,r3.w),@+er1 ;01566f3c12349160 -+ and.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01566f3c1234c1609abc -+ and.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01566f3c1234c9609abcdef0 -+ and.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01566f3c1234d2609abc -+ and.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01566f3c1234e2609abc -+ and.w @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01566f3c1234f2609abc -+ and.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01566f3c1234da609abcdef0 -+ and.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01566f3c1234ea609abcdef0 -+ and.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01566f3c1234fa609abcdef0 -+ and.w @(0x1234:16,r3.w),@0xffff9abc:16 ;01566f3c123440609abc -+ and.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;01566f3c123448609abcdef0 -+ -+ and.w @(0x1234:16,er3.l),@er1 ;01576f3c12340160 -+ and.w @(0x1234:16,er3.l),@(6:2,er1) ;01576f3c12343160 -+ and.w @(0x1234:16,er3.l),@-er1 ;01576f3c1234b160 -+ and.w @(0x1234:16,er3.l),@er1+ ;01576f3c12348160 -+ and.w @(0x1234:16,er3.l),@er1- ;01576f3c1234a160 -+ and.w @(0x1234:16,er3.l),@+er1 ;01576f3c12349160 -+ and.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01576f3c1234c1609abc -+ and.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01576f3c1234c9609abcdef0 -+ and.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01576f3c1234d2609abc -+ and.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01576f3c1234e2609abc -+ and.w @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01576f3c1234f2609abc -+ and.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01576f3c1234da609abcdef0 -+ and.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01576f3c1234ea609abcdef0 -+ and.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01576f3c1234fa609abcdef0 -+ and.w @(0x1234:16,er3.l),@0xffff9abc:16 ;01576f3c123440609abc -+ and.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;01576f3c123448609abcdef0 -+ -+ and.w @(0x12345678:32,r3l.b),@er1 ;78356b2c123456780160 -+ and.w @(0x12345678:32,r3l.b),@(6:2,er1) ;78356b2c123456783160 -+ and.w @(0x12345678:32,r3l.b),@-er1 ;78356b2c12345678b160 -+ and.w @(0x12345678:32,r3l.b),@er1+ ;78356b2c123456788160 -+ and.w @(0x12345678:32,r3l.b),@er1- ;78356b2c12345678a160 -+ and.w @(0x12345678:32,r3l.b),@+er1 ;78356b2c123456789160 -+ and.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356b2c12345678c1609abc -+ and.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356b2c12345678c9609abcdef0 -+ and.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356b2c12345678d2609abc -+ and.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356b2c12345678e2609abc -+ and.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356b2c12345678f2609abc -+ and.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356b2c12345678da609abcdef0 -+ and.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356b2c12345678ea609abcdef0 -+ and.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356b2c12345678fa609abcdef0 -+ and.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356b2c1234567840609abc -+ and.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356b2c1234567848609abcdef0 -+ -+ and.w @(0x12345678:32,r3.w),@er1 ;78366b2c123456780160 -+ and.w @(0x12345678:32,r3.w),@(6:2,er1) ;78366b2c123456783160 -+ and.w @(0x12345678:32,r3.w),@-er1 ;78366b2c12345678b160 -+ and.w @(0x12345678:32,r3.w),@er1+ ;78366b2c123456788160 -+ and.w @(0x12345678:32,r3.w),@er1- ;78366b2c12345678a160 -+ and.w @(0x12345678:32,r3.w),@+er1 ;78366b2c123456789160 -+ and.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366b2c12345678c1609abc -+ and.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366b2c12345678c9609abcdef0 -+ and.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366b2c12345678d2609abc -+ and.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366b2c12345678e2609abc -+ and.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366b2c12345678f2609abc -+ and.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366b2c12345678da609abcdef0 -+ and.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366b2c12345678ea609abcdef0 -+ and.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366b2c12345678fa609abcdef0 -+ and.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366b2c1234567840609abc -+ and.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366b2c1234567848609abcdef0 -+ -+ and.w @(0x12345678:32,er3.l),@er1 ;78376b2c123456780160 -+ and.w @(0x12345678:32,er3.l),@(6:2,er1) ;78376b2c123456783160 -+ and.w @(0x12345678:32,er3.l),@-er1 ;78376b2c12345678b160 -+ and.w @(0x12345678:32,er3.l),@er1+ ;78376b2c123456788160 -+ and.w @(0x12345678:32,er3.l),@er1- ;78376b2c12345678a160 -+ and.w @(0x12345678:32,er3.l),@+er1 ;78376b2c123456789160 -+ and.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376b2c12345678c1609abc -+ and.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376b2c12345678c9609abcdef0 -+ and.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376b2c12345678d2609abc -+ and.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376b2c12345678e2609abc -+ and.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376b2c12345678f2609abc -+ and.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376b2c12345678da609abcdef0 -+ and.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376b2c12345678ea609abcdef0 -+ and.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376b2c12345678fa609abcdef0 -+ and.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376b2c1234567840609abc -+ and.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376b2c1234567848609abcdef0 -+ -+ and.w @0x1234:16,@er1 ;6b1512340160 -+ and.w @0x1234:16,@(6:2,er1) ;6b1512343160 -+ and.w @0x1234:16,@-er1 ;6b151234b160 -+ and.w @0x1234:16,@er1+ ;6b1512348160 -+ and.w @0x1234:16,@er1- ;6b151234a160 -+ and.w @0x1234:16,@+er1 ;6b1512349160 -+ and.w @0x1234:16,@(0xffff9abc:16,er1) ;6b151234c1609abc -+ and.w @0x1234:16,@(0x9abcdef0:32,er1) ;6b151234c9609abcdef0 -+ and.w @0x1234:16,@(0xffff9abc:16,r2l.b) ;6b151234d2609abc -+ and.w @0x1234:16,@(0xffff9abc:16,r2.w) ;6b151234e2609abc -+ and.w @0x1234:16,@(0xffff9abc:16,er2.l) ;6b151234f2609abc -+ and.w @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6b151234da609abcdef0 -+ and.w @0x1234:16,@(0x9abcdef0:32,r2.w) ;6b151234ea609abcdef0 -+ and.w @0x1234:16,@(0x9abcdef0:32,er2.l) ;6b151234fa609abcdef0 -+ and.w @0x1234:16,@0xffff9abc:16 ;6b15123440609abc -+ and.w @0x1234:16,@0x9abcdef0:32 ;6b15123448609abcdef0 -+ -+ and.w @0x12345678:32,@er1 ;6b35123456780160 -+ and.w @0x12345678:32,@(6:2,er1) ;6b35123456783160 -+ and.w @0x12345678:32,@-er1 ;6b3512345678b160 -+ and.w @0x12345678:32,@er1+ ;6b35123456788160 -+ and.w @0x12345678:32,@er1- ;6b3512345678a160 -+ and.w @0x12345678:32,@+er1 ;6b35123456789160 -+ and.w @0x12345678:32,@(0xffff9abc:16,er1) ;6b3512345678c1609abc -+ and.w @0x12345678:32,@(0x9abcdef0:32,er1) ;6b3512345678c9609abcdef0 -+ and.w @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6b3512345678d2609abc -+ and.w @0x12345678:32,@(0xffff9abc:16,r2.w) ;6b3512345678e2609abc -+ and.w @0x12345678:32,@(0xffff9abc:16,er2.l) ;6b3512345678f2609abc -+ and.w @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6b3512345678da609abcdef0 -+ and.w @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6b3512345678ea609abcdef0 -+ and.w @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6b3512345678fa609abcdef0 -+ and.w @0x12345678:32,@0xffff9abc:16 ;6b351234567840609abc -+ and.w @0x12345678:32,@0x9abcdef0:32 ;6b351234567848609abcdef0 -+ -+ and.l #0x12345678:32,er1 ;7a6112345678 -+ and.l #0x1234:16,er1 ;7a691234 -+ and.l #0x12345678:32,@er1 ;010e016812345678 -+ and.l #0x12345678:32,@(0xc:2,er1) ;010e316812345678 -+ and.l #0x12345678:32,@er1+ ;010e816812345678 -+ and.l #0x12345678:32,@-er1 ;010eb16812345678 -+ and.l #0x12345678:32,@+er1 ;010e916812345678 -+ and.l #0x12345678:32,@er1- ;010ea16812345678 -+ and.l #0x12345678:32,@(0xffff9abc:16,er1) ;010ec1689abc12345678 -+ and.l #0x12345678:32,@(0x9abcdef0:32,er1) ;010ec9689abcdef012345678 -+ and.l #0x12345678:32,@(0xffff9abc:16,r2l.b) ;010ed2689abc12345678 -+ and.l #0x12345678:32,@(0xffff9abc:16,r2.w) ;010ee2689abc12345678 -+ and.l #0x12345678:32,@(0xffff9abc:16,er2.l) ;010ef2689abc12345678 -+ and.l #0x12345678:32,@(0x9abcdef0:32,r2l.b) ;010eda689abcdef012345678 -+ and.l #0x12345678:32,@(0x9abcdef0:32,r2.w) ;010eea689abcdef012345678 -+ and.l #0x12345678:32,@(0x9abcdef0:32,er2.l) ;010efa689abcdef012345678 -+ and.l #0x12345678:32,@0xffff9abc:16 ;010e40689abc12345678 -+ and.l #0x12345678:32,@0x9abcdef0:32 ;010e48689abcdef012345678 -+ and.l #0x1234:16,@er1 ;010e01601234 -+ and.l #0x1234:16,@(0xc:2,er1) ;010e31601234 -+ and.l #0x1234:16,@er1+ ;010e81601234 -+ and.l #0x1234:16,@-er1 ;010eb1601234 -+ and.l #0x1234:16,@+er1 ;010e91601234 -+ and.l #0x1234:16,@er1- ;010ea1601234 -+ and.l #0x1234:16,@(0xffff9abc:16,er1) ;010ec1609abc1234 -+ and.l #0x1234:16,@(0x9abcdef0:32,er1) ;010ec9609abcdef01234 -+ and.l #0x1234:16,@(0xffff9abc:16,r2l.b) ;010ed2609abc1234 -+ and.l #0x1234:16,@(0xffff9abc:16,r2.w) ;010ee2609abc1234 -+ and.l #0x1234:16,@(0xffff9abc:16,er2.l) ;010ef2609abc1234 -+ and.l #0x1234:16,@(0x9abcdef0:32,r2l.b) ;010eda609abcdef01234 -+ and.l #0x1234:16,@(0x9abcdef0:32,r2.w) ;010eea609abcdef01234 -+ and.l #0x1234:16,@(0x9abcdef0:32,er2.l) ;010efa609abcdef01234 -+ and.l #0x1234:16,@0xffff9abc:16 ;010e40609abc1234 -+ and.l #0x1234:16,@0x9abcdef0:32 ;010e48609abcdef01234 -+ -+ and.l er3,er1 ;01f06631 -+ -+ and.l er3,@er1 ;01090163 -+ and.l er3,@(0xc:2,er1) ;01093163 -+ and.l er3,@er1+ ;01098163 -+ and.l er3,@-er1 ;0109b163 -+ and.l er3,@+er1 ;01099163 -+ and.l er3,@er1- ;0109a163 -+ and.l er3,@(0x1234:16,er1) ;0109c1631234 -+ and.l er3,@(0x12345678:32,er1) ;0109c96312345678 -+ and.l er3,@(0x1234:16,r2l.b) ;0109d2631234 -+ and.l er3,@(0x1234:16,r2.w) ;0109e2631234 -+ and.l er3,@(0x1234:16,er2.l) ;0109f2631234 -+ and.l er3,@(0x12345678:32,r2l.b) ;0109da6312345678 -+ and.l er3,@(0x12345678:32,r2.w) ;0109ea6312345678 -+ and.l er3,@(0x12345678:32,er2.l) ;0109fa6312345678 -+ and.l er3,@0x1234:16 ;010940631234 -+ and.l er3,@0x12345678:32 ;0109486312345678 -+ -+ and.l @er3,er1 ;010a0361 -+ and.l @(0xc:2,er3),er1 ;010a3361 -+ and.l @er3+,er1 ;010a8361 -+ and.l @-er3,er1 ;010ab361 -+ and.l @+er3,er1 ;010a9361 -+ and.l @er3-,er1 ;010aa361 -+ and.l @(0x1234:16,er1),er1 ;010ac1611234 -+ and.l @(0x12345678:32,er1),er1 ;010ac96112345678 -+ and.l @(0x1234:16,r2l.b),er1 ;010ad2611234 -+ and.l @(0x1234:16,r2.w),er1 ;010ae2611234 -+ and.l @(0x1234:16,er2.l),er1 ;010af2611234 -+ and.l @(0x12345678:32,r2l.b),er1 ;010ada6112345678 -+ and.l @(0x12345678:32,r2.w),er1 ;010aea6112345678 -+ and.l @(0x12345678:32,er2.l),er1 ;010afa6112345678 -+ and.l @0x1234:16,er1 ;010a40611234 -+ and.l @0x12345678:32,er1 ;010a486112345678 -+ -+ and.l @er3,@er1 ;0104693c0160 -+ and.l @er3,@(0xc:2,er1) ;0104693c3160 -+ and.l @er3,@-er1 ;0104693cb160 -+ and.l @er3,@er1+ ;0104693c8160 -+ and.l @er3,@er1- ;0104693ca160 -+ and.l @er3,@+er1 ;0104693c9160 -+ and.l @er3,@(0xffff9abc:16,er1) ;0104693cc1609abc -+ and.l @er3,@(0x9abcdef0:32,er1) ;0104693cc9609abcdef0 -+ and.l @er3,@(0xffff9abc:16,r2l.b) ;0104693cd2609abc -+ and.l @er3,@(0xffff9abc:16,r2.w) ;0104693ce2609abc -+ and.l @er3,@(0xffff9abc:16,er2.l) ;0104693cf2609abc -+ and.l @er3,@(0x9abcdef0:32,r2l.b) ;0104693cda609abcdef0 -+ and.l @er3,@(0x9abcdef0:32,r2.w) ;0104693cea609abcdef0 -+ and.l @er3,@(0x9abcdef0:32,er2.l) ;0104693cfa609abcdef0 -+ and.l @er3,@0xffff9abc:16 ;0104693c40609abc -+ and.l @er3,@0x9abcdef0:32 ;0104693c48609abcdef0 -+ -+ and.l @(0xc:2,er3),@er1 ;0107693c0160 -+ and.l @(0xc:2,er3),@(0xc:2,er1) ;0107693c3160 -+ and.l @(0xc:2,er3),@-er1 ;0107693cb160 -+ and.l @(0xc:2,er3),@er1+ ;0107693c8160 -+ and.l @(0xc:2,er3),@er1- ;0107693ca160 -+ and.l @(0xc:2,er3),@+er1 ;0107693c9160 -+ and.l @(0xc:2,er3),@(0xffff9abc:16,er1) ;0107693cc1609abc -+ and.l @(0xc:2,er3),@(0x9abcdef0:32,er1) ;0107693cc9609abcdef0 -+ and.l @(0xc:2,er3),@(0xffff9abc:16,r2l.b) ;0107693cd2609abc -+ and.l @(0xc:2,er3),@(0xffff9abc:16,r2.w) ;0107693ce2609abc -+ and.l @(0xc:2,er3),@(0xffff9abc:16,er2.l) ;0107693cf2609abc -+ and.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b) ;0107693cda609abcdef0 -+ and.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w) ;0107693cea609abcdef0 -+ and.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l) ;0107693cfa609abcdef0 -+ and.l @(0xc:2,er3),@0xffff9abc:16 ;0107693c40609abc -+ and.l @(0xc:2,er3),@0x9abcdef0:32 ;0107693c48609abcdef0 -+ -+ and.l @-er3,@er1 ;01076d3c0160 -+ and.l @-er3,@(0xc:2,er1) ;01076d3c3160 -+ and.l @-er3,@-er1 ;01076d3cb160 -+ and.l @-er3,@er1+ ;01076d3c8160 -+ and.l @-er3,@er1- ;01076d3ca160 -+ and.l @-er3,@+er1 ;01076d3c9160 -+ and.l @-er3,@(0xffff9abc:16,er1) ;01076d3cc1609abc -+ and.l @-er3,@(0x9abcdef0:32,er1) ;01076d3cc9609abcdef0 -+ and.l @-er3,@(0xffff9abc:16,r2l.b) ;01076d3cd2609abc -+ and.l @-er3,@(0xffff9abc:16,r2.w) ;01076d3ce2609abc -+ and.l @-er3,@(0xffff9abc:16,er2.l) ;01076d3cf2609abc -+ and.l @-er3,@(0x9abcdef0:32,r2l.b) ;01076d3cda609abcdef0 -+ and.l @-er3,@(0x9abcdef0:32,r2.w) ;01076d3cea609abcdef0 -+ and.l @-er3,@(0x9abcdef0:32,er2.l) ;01076d3cfa609abcdef0 -+ and.l @-er3,@0xffff9abc:16 ;01076d3c40609abc -+ and.l @-er3,@0x9abcdef0:32 ;01076d3c48609abcdef0 -+ -+ and.l @er3+,@er1 ;01046d3c0160 -+ and.l @er3+,@(0xc:2,er1) ;01046d3c3160 -+ and.l @er3+,@-er1 ;01046d3cb160 -+ and.l @er3+,@er1+ ;01046d3c8160 -+ and.l @er3+,@er1- ;01046d3ca160 -+ and.l @er3+,@+er1 ;01046d3c9160 -+ and.l @er3+,@(0xffff9abc:16,er1) ;01046d3cc1609abc -+ and.l @er3+,@(0x9abcdef0:32,er1) ;01046d3cc9609abcdef0 -+ and.l @er3+,@(0xffff9abc:16,r2l.b) ;01046d3cd2609abc -+ and.l @er3+,@(0xffff9abc:16,r2.w) ;01046d3ce2609abc -+ and.l @er3+,@(0xffff9abc:16,er2.l) ;01046d3cf2609abc -+ and.l @er3+,@(0x9abcdef0:32,r2l.b) ;01046d3cda609abcdef0 -+ and.l @er3+,@(0x9abcdef0:32,r2.w) ;01046d3cea609abcdef0 -+ and.l @er3+,@(0x9abcdef0:32,er2.l) ;01046d3cfa609abcdef0 -+ and.l @er3+,@0xffff9abc:16 ;01046d3c40609abc -+ and.l @er3+,@0x9abcdef0:32 ;01046d3c48609abcdef0 -+ -+ and.l @er3-,@er1 ;01066d3c0160 -+ and.l @er3-,@(0xc:2,er1) ;01066d3c3160 -+ and.l @er3-,@-er1 ;01066d3cb160 -+ and.l @er3-,@er1+ ;01066d3c8160 -+ and.l @er3-,@er1- ;01066d3ca160 -+ and.l @er3-,@+er1 ;01066d3c9160 -+ and.l @er3-,@(0xffff9abc:16,er1) ;01066d3cc1609abc -+ and.l @er3-,@(0x9abcdef0:32,er1) ;01066d3cc9609abcdef0 -+ and.l @er3-,@(0xffff9abc:16,r2l.b) ;01066d3cd2609abc -+ and.l @er3-,@(0xffff9abc:16,r2.w) ;01066d3ce2609abc -+ and.l @er3-,@(0xffff9abc:16,er2.l) ;01066d3cf2609abc -+ and.l @er3-,@(0x9abcdef0:32,r2l.b) ;01066d3cda609abcdef0 -+ and.l @er3-,@(0x9abcdef0:32,r2.w) ;01066d3cea609abcdef0 -+ and.l @er3-,@(0x9abcdef0:32,er2.l) ;01066d3cfa609abcdef0 -+ and.l @er3-,@0xffff9abc:16 ;01066d3c40609abc -+ and.l @er3-,@0x9abcdef0:32 ;01066d3c48609abcdef0 -+ -+ and.l @+er3,@er1 ;01056d3c0160 -+ and.l @+er3,@(0xc:2,er1) ;01056d3c3160 -+ and.l @+er3,@-er1 ;01056d3cb160 -+ and.l @+er3,@er1+ ;01056d3c8160 -+ and.l @+er3,@er1- ;01056d3ca160 -+ and.l @+er3,@+er1 ;01056d3c9160 -+ and.l @+er3,@(0xffff9abc:16,er1) ;01056d3cc1609abc -+ and.l @+er3,@(0x9abcdef0:32,er1) ;01056d3cc9609abcdef0 -+ and.l @+er3,@(0xffff9abc:16,r2l.b) ;01056d3cd2609abc -+ and.l @+er3,@(0xffff9abc:16,r2.w) ;01056d3ce2609abc -+ and.l @+er3,@(0xffff9abc:16,er2.l) ;01056d3cf2609abc -+ and.l @+er3,@(0x9abcdef0:32,r2l.b) ;01056d3cda609abcdef0 -+ and.l @+er3,@(0x9abcdef0:32,r2.w) ;01056d3cea609abcdef0 -+ and.l @+er3,@(0x9abcdef0:32,er2.l) ;01056d3cfa609abcdef0 -+ and.l @+er3,@0xffff9abc:16 ;01056d3c40609abc -+ and.l @+er3,@0x9abcdef0:32 ;01056d3c48609abcdef0 -+ -+ and.l @(0x1234:16,er3),@er1 ;01046f3c12340160 -+ and.l @(0x1234:16,er3),@(0xc:2,er1) ;01046f3c12343160 -+ and.l @(0x1234:16,er3),@-er1 ;01046f3c1234b160 -+ and.l @(0x1234:16,er3),@er1+ ;01046f3c12348160 -+ and.l @(0x1234:16,er3),@er1- ;01046f3c1234a160 -+ and.l @(0x1234:16,er3),@+er1 ;01046f3c12349160 -+ and.l @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01046f3c1234c1609abc -+ and.l @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01046f3c1234c9609abcdef0 -+ and.l @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01046f3c1234d2609abc -+ and.l @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01046f3c1234e2609abc -+ and.l @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01046f3c1234f2609abc -+ and.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01046f3c1234da609abcdef0 -+ and.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01046f3c1234ea609abcdef0 -+ and.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01046f3c1234fa609abcdef0 -+ and.l @(0x1234:16,er3),@0xffff9abc:16 ;01046f3c123440609abc -+ and.l @(0x1234:16,er3),@0x9abcdef0:32 ;01046f3c123448609abcdef0 -+ -+ and.l @(0x12345678:32,er3),@er1 ;78b46b2c123456780160 -+ and.l @(0x12345678:32,er3),@(0xc:2,er1) ;78b46b2c123456783160 -+ and.l @(0x12345678:32,er3),@-er1 ;78b46b2c12345678b160 -+ and.l @(0x12345678:32,er3),@er1+ ;78b46b2c123456788160 -+ and.l @(0x12345678:32,er3),@er1- ;78b46b2c12345678a160 -+ and.l @(0x12345678:32,er3),@+er1 ;78b46b2c123456789160 -+ and.l @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78b46b2c12345678c1609abc -+ and.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78b46b2c12345678c9609abcdef0 -+ and.l @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78b46b2c12345678d2609abc -+ and.l @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78b46b2c12345678e2609abc -+ and.l @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78b46b2c12345678f2609abc -+ and.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78b46b2c12345678da609abcdef0 -+ and.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78b46b2c12345678ea609abcdef0 -+ and.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78b46b2c12345678fa609abcdef0 -+ and.l @(0x12345678:32,er3),@0xffff9abc:16 ;78b46b2c1234567840609abc -+ and.l @(0x12345678:32,er3),@0x9abcdef0:32 ;78b46b2c1234567848609abcdef0 -+ -+ and.l @(0x1234:16,r3l.b),@er1 ;01056f3c12340160 -+ and.l @(0x1234:16,r3l.b),@(0xc:2,er1) ;01056f3c12343160 -+ and.l @(0x1234:16,r3l.b),@-er1 ;01056f3c1234b160 -+ and.l @(0x1234:16,r3l.b),@er1+ ;01056f3c12348160 -+ and.l @(0x1234:16,r3l.b),@er1- ;01056f3c1234a160 -+ and.l @(0x1234:16,r3l.b),@+er1 ;01056f3c12349160 -+ and.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01056f3c1234c1609abc -+ and.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01056f3c1234c9609abcdef0 -+ and.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01056f3c1234d2609abc -+ and.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01056f3c1234e2609abc -+ and.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01056f3c1234f2609abc -+ and.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01056f3c1234da609abcdef0 -+ and.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01056f3c1234ea609abcdef0 -+ and.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01056f3c1234fa609abcdef0 -+ and.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;01056f3c123440609abc -+ and.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01056f3c123448609abcdef0 -+ -+ and.l @(0x1234:16,r3.w),@er1 ;01066f3c12340160 -+ and.l @(0x1234:16,r3.w),@(0xc:2,er1) ;01066f3c12343160 -+ and.l @(0x1234:16,r3.w),@-er1 ;01066f3c1234b160 -+ and.l @(0x1234:16,r3.w),@er1+ ;01066f3c12348160 -+ and.l @(0x1234:16,r3.w),@er1- ;01066f3c1234a160 -+ and.l @(0x1234:16,r3.w),@+er1 ;01066f3c12349160 -+ and.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01066f3c1234c1609abc -+ and.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01066f3c1234c9609abcdef0 -+ and.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01066f3c1234d2609abc -+ and.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01066f3c1234e2609abc -+ and.l @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01066f3c1234f2609abc -+ and.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01066f3c1234da609abcdef0 -+ and.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01066f3c1234ea609abcdef0 -+ and.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01066f3c1234fa609abcdef0 -+ and.l @(0x1234:16,r3.w),@0xffff9abc:16 ;01066f3c123440609abc -+ and.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;01066f3c123448609abcdef0 -+ -+ and.l @(0x1234:16,er3.l),@er1 ;01076f3c12340160 -+ and.l @(0x1234:16,er3.l),@(0xc:2,er1) ;01076f3c12343160 -+ and.l @(0x1234:16,er3.l),@-er1 ;01076f3c1234b160 -+ and.l @(0x1234:16,er3.l),@er1+ ;01076f3c12348160 -+ and.l @(0x1234:16,er3.l),@er1- ;01076f3c1234a160 -+ and.l @(0x1234:16,er3.l),@+er1 ;01076f3c12349160 -+ and.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01076f3c1234c1609abc -+ and.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01076f3c1234c9609abcdef0 -+ and.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01076f3c1234d2609abc -+ and.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01076f3c1234e2609abc -+ and.l @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01076f3c1234f2609abc -+ and.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01076f3c1234da609abcdef0 -+ and.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01076f3c1234ea609abcdef0 -+ and.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01076f3c1234fa609abcdef0 -+ and.l @(0x1234:16,er3.l),@0xffff9abc:16 ;01076f3c123440609abc -+ and.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;01076f3c123448609abcdef0 -+ -+ and.l @(0x12345678:32,r3l.b),@er1 ;78b56b2c123456780160 -+ and.l @(0x12345678:32,r3l.b),@(0xc:2,er1) ;78b56b2c123456783160 -+ and.l @(0x12345678:32,r3l.b),@-er1 ;78b56b2c12345678b160 -+ and.l @(0x12345678:32,r3l.b),@er1+ ;78b56b2c123456788160 -+ and.l @(0x12345678:32,r3l.b),@er1- ;78b56b2c12345678a160 -+ and.l @(0x12345678:32,r3l.b),@+er1 ;78b56b2c123456789160 -+ and.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78b56b2c12345678c1609abc -+ and.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78b56b2c12345678c9609abcdef0 -+ and.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78b56b2c12345678d2609abc -+ and.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78b56b2c12345678e2609abc -+ and.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78b56b2c12345678f2609abc -+ and.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78b56b2c12345678da609abcdef0 -+ and.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78b56b2c12345678ea609abcdef0 -+ and.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78b56b2c12345678fa609abcdef0 -+ and.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78b56b2c1234567840609abc -+ and.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78b56b2c1234567848609abcdef0 -+ -+ and.l @(0x12345678:32,r3.w),@er1 ;78b66b2c123456780160 -+ and.l @(0x12345678:32,r3.w),@(0xc:2,er1) ;78b66b2c123456783160 -+ and.l @(0x12345678:32,r3.w),@-er1 ;78b66b2c12345678b160 -+ and.l @(0x12345678:32,r3.w),@er1+ ;78b66b2c123456788160 -+ and.l @(0x12345678:32,r3.w),@er1- ;78b66b2c12345678a160 -+ and.l @(0x12345678:32,r3.w),@+er1 ;78b66b2c123456789160 -+ and.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78b66b2c12345678c1609abc -+ and.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78b66b2c12345678c9609abcdef0 -+ and.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78b66b2c12345678d2609abc -+ and.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78b66b2c12345678e2609abc -+ and.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78b66b2c12345678f2609abc -+ and.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78b66b2c12345678da609abcdef0 -+ and.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78b66b2c12345678ea609abcdef0 -+ and.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78b66b2c12345678fa609abcdef0 -+ and.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;78b66b2c1234567840609abc -+ and.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78b66b2c1234567848609abcdef0 -+ -+ and.l @(0x12345678:32,er3.l),@er1 ;78b76b2c123456780160 -+ and.l @(0x12345678:32,er3.l),@(0xc:2,er1) ;78b76b2c123456783160 -+ and.l @(0x12345678:32,er3.l),@-er1 ;78b76b2c12345678b160 -+ and.l @(0x12345678:32,er3.l),@er1+ ;78b76b2c123456788160 -+ and.l @(0x12345678:32,er3.l),@er1- ;78b76b2c12345678a160 -+ and.l @(0x12345678:32,er3.l),@+er1 ;78b76b2c123456789160 -+ and.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78b76b2c12345678c1609abc -+ and.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78b76b2c12345678c9609abcdef0 -+ and.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78b76b2c12345678d2609abc -+ and.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78b76b2c12345678e2609abc -+ and.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78b76b2c12345678f2609abc -+ and.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78b76b2c12345678da609abcdef0 -+ and.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78b76b2c12345678ea609abcdef0 -+ and.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78b76b2c12345678fa609abcdef0 -+ and.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;78b76b2c1234567840609abc -+ and.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78b76b2c1234567848609abcdef0 -+ -+ and.l @0x1234:16,@er1 ;01046b0c12340160 -+ and.l @0x1234:16,@(0xc:2,er1) ;01046b0c12343160 -+ and.l @0x1234:16,@-er1 ;01046b0c1234b160 -+ and.l @0x1234:16,@er1+ ;01046b0c12348160 -+ and.l @0x1234:16,@er1- ;01046b0c1234a160 -+ and.l @0x1234:16,@+er1 ;01046b0c12349160 -+ and.l @0x1234:16,@(0xffff9abc:16,er1) ;01046b0c1234c1609abc -+ and.l @0x1234:16,@(0x9abcdef0:32,er1) ;01046b0c1234c9609abcdef0 -+ and.l @0x1234:16,@(0xffff9abc:16,r2l.b) ;01046b0c1234d2609abc -+ and.l @0x1234:16,@(0xffff9abc:16,r2.w) ;01046b0c1234e2609abc -+ and.l @0x1234:16,@(0xffff9abc:16,er2.l) ;01046b0c1234f2609abc -+ and.l @0x1234:16,@(0x9abcdef0:32,r2l.b) ;01046b0c1234da609abcdef0 -+ and.l @0x1234:16,@(0x9abcdef0:32,r2.w) ;01046b0c1234ea609abcdef0 -+ and.l @0x1234:16,@(0x9abcdef0:32,er2.l) ;01046b0c1234fa609abcdef0 -+ and.l @0x1234:16,@0xffff9abc:16 ;01046b0c123440609abc -+ and.l @0x1234:16,@0x9abcdef0:32 ;01046b0c123448609abcdef0 -+ -+ and.l @0x12345678:32,@er1 ;01046b2c123456780160 -+ and.l @0x12345678:32,@(0xc:2,er1) ;01046b2c123456783160 -+ and.l @0x12345678:32,@-er1 ;01046b2c12345678b160 -+ and.l @0x12345678:32,@er1+ ;01046b2c123456788160 -+ and.l @0x12345678:32,@er1- ;01046b2c12345678a160 -+ and.l @0x12345678:32,@+er1 ;01046b2c123456789160 -+ and.l @0x12345678:32,@(0xffff9abc:16,er1) ;01046b2c12345678c1609abc -+ and.l @0x12345678:32,@(0x9abcdef0:32,er1) ;01046b2c12345678c9609abcdef0 -+ and.l @0x12345678:32,@(0xffff9abc:16,r2l.b) ;01046b2c12345678d2609abc -+ and.l @0x12345678:32,@(0xffff9abc:16,r2.w) ;01046b2c12345678e2609abc -+ and.l @0x12345678:32,@(0xffff9abc:16,er2.l) ;01046b2c12345678f2609abc -+ and.l @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;01046b2c12345678da609abcdef0 -+ and.l @0x12345678:32,@(0x9abcdef0:32,r2.w) ;01046b2c12345678ea609abcdef0 -+ and.l @0x12345678:32,@(0x9abcdef0:32,er2.l) ;01046b2c12345678fa609abcdef0 -+ and.l @0x12345678:32,@0xffff9abc:16 ;01046b2c1234567840609abc -+ and.l @0x12345678:32,@0x9abcdef0:32 ;01046b2c1234567848609abcdef0 -+ -+ .end ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;log_1 ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ .h8300sx ++ .text ++_start: ++ and.b #0x12:8,r1h ;e112 ++ and.b #0x12:8,@er1 ;7d10e012 ++ and.b #0x12:8,@(0x3:2,er1) ;01776818e012 ++ and.b #0x12:8,@er1+ ;01746c18e012 ++ and.b #0x12:8,@-er1 ;01776c18e012 ++ and.b #0x12:8,@+er1 ;01756c18e012 ++ and.b #0x12:8,@er1- ;01766c18e012 ++ and.b #0x12:8,@(0x1234:16,er1) ;01746e181234e012 ++ and.b #0x12:8,@(0x12345678:32,er1) ;78146a2812345678e012 ++ and.b #0x12:8,@(0x1234:16,r2l.b) ;01756e281234e012 ++ and.b #0x12:8,@(0x1234:16,r2.w) ;01766e281234e012 ++ and.b #0x12:8,@(0x1234:16,er2.l) ;01776e281234e012 ++ and.b #0x12:8,@(0x12345678:32,r2l.b) ;78256a2812345678e012 ++ and.b #0x12:8,@(0x12345678:32,r2.w) ;78266a2812345678e012 ++ and.b #0x12:8,@(0x12345678:32,er2.l) ;78276a2812345678e012 ++ and.b #0x12:8,@0xffffff12:8 ;7f12e012 ++ and.b #0x12:8,@0x1234:16 ;6a181234e012 ++ and.b #0x12:8,@0x12345678:32 ;6a3812345678e012 ++ ++ and.b r3h,r1h ;1631 ++ ++ and.b r3h,@er1 ;7d101630 ++ and.b r3h,@(0x3:2,er1) ;01793163 ++ and.b r3h,@er1+ ;01798163 ++ and.b r3h,@-er1 ;0179b163 ++ and.b r3h,@+er1 ;01799163 ++ and.b r3h,@er1- ;0179a163 ++ and.b r3h,@(0x1234:16,er1) ;0179c1631234 ++ and.b r3h,@(0x12345678:32,er1) ;0179c96312345678 ++ and.b r3h,@(0x1234:16,r2l.b) ;0179d2631234 ++ and.b r3h,@(0x1234:16,r2.w) ;0179e2631234 ++ and.b r3h,@(0x1234:16,er2.l) ;0179f2631234 ++ and.b r3h,@(0x12345678:32,r2l.b) ;0179da6312345678 ++ and.b r3h,@(0x12345678:32,r2.w) ;0179ea6312345678 ++ and.b r3h,@(0x12345678:32,er2.l) ;0179fa6312345678 ++ and.b r3h,@0xffffff12:8 ;7f121630 ++ and.b r3h,@0x1234:16 ;6a1812341630 ++ and.b r3h,@0x12345678:32 ;6a38123456781630 ++ ++ and.b @er3,r1h ;7c301601 ++ and.b @(0x3:2,er3),r1h ;017a3361 ++ and.b @er3+,r1h ;017a8361 ++ and.b @-er3,r1h ;017ab361 ++ and.b @+er3,r1h ;017a9361 ++ and.b @er3-,r1h ;017aa361 ++ and.b @(0x1234:16,er1),r1h ;017ac1611234 ++ and.b @(0x12345678:32,er1),r1h ;017ac96112345678 ++ and.b @(0x1234:16,r2l.b),r1h ;017ad2611234 ++ and.b @(0x1234:16,r2.w),r1h ;017ae2611234 ++ and.b @(0x1234:16,er2.l),r1h ;017af2611234 ++ and.b @(0x12345678:32,r2l.b),r1h ;017ada6112345678 ++ and.b @(0x12345678:32,r2.w),r1h ;017aea6112345678 ++ and.b @(0x12345678:32,er2.l),r1h ;017afa6112345678 ++ and.b @0xffffff12:8,r1h ;7e121601 ++ and.b @0x1234:16,r1h ;6a1012341601 ++ and.b @0x12345678:32,r1h ;6a30123456781601 ++ ++ and.b @er3,@er1 ;7c350160 ++ and.b @er3,@(3:2,er1) ;7c353160 ++ and.b @er3,@-er1 ;7c35b160 ++ and.b @er3,@er1+ ;7c358160 ++ and.b @er3,@er1- ;7c35a160 ++ and.b @er3,@+er1 ;7c359160 ++ and.b @er3,@(0xffff9abc:16,er1) ;7c35c1609abc ++ and.b @er3,@(0x9abcdef0:32,er1) ;7c35c9609abcdef0 ++ and.b @er3,@(0xffff9abc:16,r2l.b) ;7c35d2609abc ++ and.b @er3,@(0xffff9abc:16,r2.w) ;7c35e2609abc ++ and.b @er3,@(0xffff9abc:16,er2.l) ;7c35f2609abc ++ and.b @er3,@(0x9abcdef0:32,r2l.b) ;7c35da609abcdef0 ++ and.b @er3,@(0x9abcdef0:32,r2.w) ;7c35ea609abcdef0 ++ and.b @er3,@(0x9abcdef0:32,er2.l) ;7c35fa609abcdef0 ++ and.b @er3,@0xffff9abc:16 ;7c3540609abc ++ and.b @er3,@0x9abcdef0:32 ;7c3548609abcdef0 ++ ++ and.b @-er3,@er1 ;01776c3c0160 ++ and.b @-er3,@(3:2,er1) ;01776c3c3160 ++ and.b @-er3,@-er1 ;01776c3cb160 ++ and.b @-er3,@er1+ ;01776c3c8160 ++ and.b @-er3,@er1- ;01776c3ca160 ++ and.b @-er3,@+er1 ;01776c3c9160 ++ and.b @-er3,@(0xffff9abc:16,er1) ;01776c3cc1609abc ++ and.b @-er3,@(0x9abcdef0:32,er1) ;01776c3cc9609abcdef0 ++ and.b @-er3,@(0xffff9abc:16,r2l.b) ;01776c3cd2609abc ++ and.b @-er3,@(0xffff9abc:16,r2.w) ;01776c3ce2609abc ++ and.b @-er3,@(0xffff9abc:16,er2.l) ;01776c3cf2609abc ++ and.b @-er3,@(0x9abcdef0:32,r2l.b) ;01776c3cda609abcdef0 ++ and.b @-er3,@(0x9abcdef0:32,r2.w) ;01776c3cea609abcdef0 ++ and.b @-er3,@(0x9abcdef0:32,er2.l) ;01776c3cfa609abcdef0 ++ and.b @-er3,@0xffff9abc:16 ;01776c3c40609abc ++ and.b @-er3,@0x9abcdef0:32 ;01776c3c48609abcdef0 ++ ++ and.b @er3+,@er1 ;01746c3c0160 ++ and.b @er3+,@(3:2,er1) ;01746c3c3160 ++ and.b @er3+,@-er1 ;01746c3cb160 ++ and.b @er3+,@er1+ ;01746c3c8160 ++ and.b @er3+,@er1- ;01746c3ca160 ++ and.b @er3+,@+er1 ;01746c3c9160 ++ and.b @er3+,@(0xffff9abc:16,er1) ;01746c3cc1609abc ++ and.b @er3+,@(0x9abcdef0:32,er1) ;01746c3cc9609abcdef0 ++ and.b @er3+,@(0xffff9abc:16,r2l.b) ;01746c3cd2609abc ++ and.b @er3+,@(0xffff9abc:16,r2.w) ;01746c3ce2609abc ++ and.b @er3+,@(0xffff9abc:16,er2.l) ;01746c3cf2609abc ++ and.b @er3+,@(0x9abcdef0:32,r2l.b) ;01746c3cda609abcdef0 ++ and.b @er3+,@(0x9abcdef0:32,r2.w) ;01746c3cea609abcdef0 ++ and.b @er3+,@(0x9abcdef0:32,er2.l) ;01746c3cfa609abcdef0 ++ and.b @er3+,@0xffff9abc:16 ;01746c3c40609abc ++ and.b @er3+,@0x9abcdef0:32 ;01746c3c48609abcdef0 ++ ++ and.b @er3-,@er1 ;01766c3c0160 ++ and.b @er3-,@(3:2,er1) ;01766c3c3160 ++ and.b @er3-,@-er1 ;01766c3cb160 ++ and.b @er3-,@er1+ ;01766c3c8160 ++ and.b @er3-,@er1- ;01766c3ca160 ++ and.b @er3-,@+er1 ;01766c3c9160 ++ and.b @er3-,@(0xffff9abc:16,er1) ;01766c3cc1609abc ++ and.b @er3-,@(0x9abcdef0:32,er1) ;01766c3cc9609abcdef0 ++ and.b @er3-,@(0xffff9abc:16,r2l.b) ;01766c3cd2609abc ++ and.b @er3-,@(0xffff9abc:16,r2.w) ;01766c3ce2609abc ++ and.b @er3-,@(0xffff9abc:16,er2.l) ;01766c3cf2609abc ++ and.b @er3-,@(0x9abcdef0:32,r2l.b) ;01766c3cda609abcdef0 ++ and.b @er3-,@(0x9abcdef0:32,r2.w) ;01766c3cea609abcdef0 ++ and.b @er3-,@(0x9abcdef0:32,er2.l) ;01766c3cfa609abcdef0 ++ and.b @er3-,@0xffff9abc:16 ;01766c3c40609abc ++ and.b @er3-,@0x9abcdef0:32 ;01766c3c48609abcdef0 ++ ++ and.b @+er3,@er1 ;01756c3c0160 ++ and.b @+er3,@(3:2,er1) ;01756c3c3160 ++ and.b @+er3,@-er1 ;01756c3cb160 ++ and.b @+er3,@er1+ ;01756c3c8160 ++ and.b @+er3,@er1- ;01756c3ca160 ++ and.b @+er3,@+er1 ;01756c3c9160 ++ and.b @+er3,@(0xffff9abc:16,er1) ;01756c3cc1609abc ++ and.b @+er3,@(0x9abcdef0:32,er1) ;01756c3cc9609abcdef0 ++ and.b @+er3,@(0xffff9abc:16,r2l.b) ;01756c3cd2609abc ++ and.b @+er3,@(0xffff9abc:16,r2.w) ;01756c3ce2609abc ++ and.b @+er3,@(0xffff9abc:16,er2.l) ;01756c3cf2609abc ++ and.b @+er3,@(0x9abcdef0:32,r2l.b) ;01756c3cda609abcdef0 ++ and.b @+er3,@(0x9abcdef0:32,r2.w) ;01756c3cea609abcdef0 ++ and.b @+er3,@(0x9abcdef0:32,er2.l) ;01756c3cfa609abcdef0 ++ and.b @+er3,@0xffff9abc:16 ;01756c3c40609abc ++ and.b @+er3,@0x9abcdef0:32 ;01756c3c48609abcdef0 ++ ++ and.b @(0x1234:16,er3),@er1 ;01746e3c12340160 ++ and.b @(0x1234:16,er3),@(3:2,er1) ;01746e3c12343160 ++ and.b @(0x1234:16,er3),@-er1 ;01746e3c1234b160 ++ and.b @(0x1234:16,er3),@er1+ ;01746e3c12348160 ++ and.b @(0x1234:16,er3),@er1- ;01746e3c1234a160 ++ and.b @(0x1234:16,er3),@+er1 ;01746e3c12349160 ++ and.b @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01746e3c1234c1609abc ++ and.b @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01746e3c1234c9609abcdef0 ++ and.b @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01746e3c1234d2609abc ++ and.b @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01746e3c1234e2609abc ++ and.b @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01746e3c1234f2609abc ++ and.b @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01746e3c1234da609abcdef0 ++ and.b @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01746e3c1234ea609abcdef0 ++ and.b @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01746e3c1234fa609abcdef0 ++ and.b @(0x1234:16,er3),@0xffff9abc:16 ;01746e3c123440609abc ++ and.b @(0x1234:16,er3),@0x9abcdef0:32 ;01746e3c123448609abcdef0 ++ ++ and.b @(0x12345678:32,er3),@er1 ;78346a2c123456780160 ++ and.b @(0x12345678:32,er3),@(3:2,er1) ;78346a2c123456783160 ++ and.b @(0x12345678:32,er3),@-er1 ;78346a2c12345678b160 ++ and.b @(0x12345678:32,er3),@er1+ ;78346a2c123456788160 ++ and.b @(0x12345678:32,er3),@er1- ;78346a2c12345678a160 ++ and.b @(0x12345678:32,er3),@+er1 ;78346a2c123456789160 ++ and.b @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346a2c12345678c1609abc ++ and.b @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346a2c12345678c9609abcdef0 ++ and.b @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346a2c12345678d2609abc ++ and.b @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346a2c12345678e2609abc ++ and.b @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346a2c12345678f2609abc ++ and.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346a2c12345678da609abcdef0 ++ and.b @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346a2c12345678ea609abcdef0 ++ and.b @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346a2c12345678fa609abcdef0 ++ and.b @(0x12345678:32,er3),@0xffff9abc:16 ;78346a2c1234567840609abc ++ and.b @(0x12345678:32,er3),@0x9abcdef0:32 ;78346a2c1234567848609abcdef0 ++ ++ and.b @(0x1234:16,r3l.b),@er1 ;01756e3c12340160 ++ and.b @(0x1234:16,r3l.b),@(3:2,er1) ;01756e3c12343160 ++ and.b @(0x1234:16,r3l.b),@-er1 ;01756e3c1234b160 ++ and.b @(0x1234:16,r3l.b),@er1+ ;01756e3c12348160 ++ and.b @(0x1234:16,r3l.b),@er1- ;01756e3c1234a160 ++ and.b @(0x1234:16,r3l.b),@+er1 ;01756e3c12349160 ++ and.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01756e3c1234c1609abc ++ and.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01756e3c1234c9609abcdef0 ++ and.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01756e3c1234d2609abc ++ and.b @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01756e3c1234e2609abc ++ and.b @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01756e3c1234f2609abc ++ and.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01756e3c1234da609abcdef0 ++ and.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01756e3c1234ea609abcdef0 ++ and.b @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01756e3c1234fa609abcdef0 ++ and.b @(0x1234:16,r3l.b),@0xffff9abc:16 ;01756e3c123440609abc ++ and.b @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01756e3c123448609abcdef0 ++ ++ and.b @(0x1234:16,r3.w),@er1 ;01766e3c12340160 ++ and.b @(0x1234:16,r3.w),@(3:2,er1) ;01766e3c12343160 ++ and.b @(0x1234:16,r3.w),@-er1 ;01766e3c1234b160 ++ and.b @(0x1234:16,r3.w),@er1+ ;01766e3c12348160 ++ and.b @(0x1234:16,r3.w),@er1- ;01766e3c1234a160 ++ and.b @(0x1234:16,r3.w),@+er1 ;01766e3c12349160 ++ and.b @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01766e3c1234c1609abc ++ and.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01766e3c1234c9609abcdef0 ++ and.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01766e3c1234d2609abc ++ and.b @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01766e3c1234e2609abc ++ and.b @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01766e3c1234f2609abc ++ and.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01766e3c1234da609abcdef0 ++ and.b @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01766e3c1234ea609abcdef0 ++ and.b @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01766e3c1234fa609abcdef0 ++ and.b @(0x1234:16,r3.w),@0xffff9abc:16 ;01766e3c123440609abc ++ and.b @(0x1234:16,r3.w),@0x9abcdef0:32 ;01766e3c123448609abcdef0 ++ ++ and.b @(0x1234:16,er3.l),@er1 ;01776e3c12340160 ++ and.b @(0x1234:16,er3.l),@(3:2,er1) ;01776e3c12343160 ++ and.b @(0x1234:16,er3.l),@-er1 ;01776e3c1234b160 ++ and.b @(0x1234:16,er3.l),@er1+ ;01776e3c12348160 ++ and.b @(0x1234:16,er3.l),@er1- ;01776e3c1234a160 ++ and.b @(0x1234:16,er3.l),@+er1 ;01776e3c12349160 ++ and.b @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01776e3c1234c1609abc ++ and.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01776e3c1234c9609abcdef0 ++ and.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01776e3c1234d2609abc ++ and.b @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01776e3c1234e2609abc ++ and.b @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01776e3c1234f2609abc ++ and.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01776e3c1234da609abcdef0 ++ and.b @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01776e3c1234ea609abcdef0 ++ and.b @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01776e3c1234fa609abcdef0 ++ and.b @(0x1234:16,er3.l),@0xffff9abc:16 ;01776e3c123440609abc ++ and.b @(0x1234:16,er3.l),@0x9abcdef0:32 ;01776e3c123448609abcdef0 ++ ++ and.b @(0x12345678:32,r3l.b),@er1 ;78356a2c123456780160 ++ and.b @(0x12345678:32,r3l.b),@(3:2,er1) ;78356a2c123456783160 ++ and.b @(0x12345678:32,r3l.b),@-er1 ;78356a2c12345678b160 ++ and.b @(0x12345678:32,r3l.b),@er1+ ;78356a2c123456788160 ++ and.b @(0x12345678:32,r3l.b),@er1- ;78356a2c12345678a160 ++ and.b @(0x12345678:32,r3l.b),@+er1 ;78356a2c123456789160 ++ and.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356a2c12345678c1609abc ++ and.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356a2c12345678c9609abcdef0 ++ and.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356a2c12345678d2609abc ++ and.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356a2c12345678e2609abc ++ and.b @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356a2c12345678f2609abc ++ and.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356a2c12345678da609abcdef0 ++ and.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356a2c12345678ea609abcdef0 ++ and.b @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356a2c12345678fa609abcdef0 ++ and.b @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356a2c1234567840609abc ++ and.b @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356a2c1234567848609abcdef0 ++ ++ and.b @(0x12345678:32,r3.w),@er1 ;78366a2c123456780160 ++ and.b @(0x12345678:32,r3.w),@(3:2,er1) ;78366a2c123456783160 ++ and.b @(0x12345678:32,r3.w),@-er1 ;78366a2c12345678b160 ++ and.b @(0x12345678:32,r3.w),@er1+ ;78366a2c123456788160 ++ and.b @(0x12345678:32,r3.w),@er1- ;78366a2c12345678a160 ++ and.b @(0x12345678:32,r3.w),@+er1 ;78366a2c123456789160 ++ and.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366a2c12345678c1609abc ++ and.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366a2c12345678c9609abcdef0 ++ and.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366a2c12345678d2609abc ++ and.b @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366a2c12345678e2609abc ++ and.b @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366a2c12345678f2609abc ++ and.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366a2c12345678da609abcdef0 ++ and.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366a2c12345678ea609abcdef0 ++ and.b @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366a2c12345678fa609abcdef0 ++ and.b @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366a2c1234567840609abc ++ and.b @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366a2c1234567848609abcdef0 ++ ++ and.b @(0x12345678:32,er3.l),@er1 ;78376a2c123456780160 ++ and.b @(0x12345678:32,er3.l),@(3:2,er1) ;78376a2c123456783160 ++ and.b @(0x12345678:32,er3.l),@-er1 ;78376a2c12345678b160 ++ and.b @(0x12345678:32,er3.l),@er1+ ;78376a2c123456788160 ++ and.b @(0x12345678:32,er3.l),@er1- ;78376a2c12345678a160 ++ and.b @(0x12345678:32,er3.l),@+er1 ;78376a2c123456789160 ++ and.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376a2c12345678c1609abc ++ and.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376a2c12345678c9609abcdef0 ++ and.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376a2c12345678d2609abc ++ and.b @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376a2c12345678e2609abc ++ and.b @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376a2c12345678f2609abc ++ and.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376a2c12345678da609abcdef0 ++ and.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376a2c12345678ea609abcdef0 ++ and.b @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376a2c12345678fa609abcdef0 ++ and.b @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376a2c1234567840609abc ++ and.b @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376a2c1234567848609abcdef0 ++ ++ and.b @0x1234:16,@er1 ;6a1512340160 ++ and.b @0x1234:16,@(3:2,er1) ;6a1512343160 ++ and.b @0x1234:16,@-er1 ;6a151234b160 ++ and.b @0x1234:16,@er1+ ;6a1512348160 ++ and.b @0x1234:16,@er1- ;6a151234a160 ++ and.b @0x1234:16,@+er1 ;6a1512349160 ++ and.b @0x1234:16,@(0xffff9abc:16,er1) ;6a151234c1609abc ++ and.b @0x1234:16,@(0x9abcdef0:32,er1) ;6a151234c9609abcdef0 ++ and.b @0x1234:16,@(0xffff9abc:16,r2l.b) ;6a151234d2609abc ++ and.b @0x1234:16,@(0xffff9abc:16,r2.w) ;6a151234e2609abc ++ and.b @0x1234:16,@(0xffff9abc:16,er2.l) ;6a151234f2609abc ++ and.b @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6a151234da609abcdef0 ++ and.b @0x1234:16,@(0x9abcdef0:32,r2.w) ;6a151234ea609abcdef0 ++ and.b @0x1234:16,@(0x9abcdef0:32,er2.l) ;6a151234fa609abcdef0 ++ and.b @0x1234:16,@0xffff9abc:16 ;6a15123440609abc ++ and.b @0x1234:16,@0x9abcdef0:32 ;6a15123448609abcdef0 ++ ++ and.b @0x12345678:32,@er1 ;6a35123456780160 ++ and.b @0x12345678:32,@(3:2,er1) ;6a35123456783160 ++ and.b @0x12345678:32,@-er1 ;6a3512345678b160 ++ and.b @0x12345678:32,@er1+ ;6a35123456788160 ++ and.b @0x12345678:32,@er1- ;6a3512345678a160 ++ and.b @0x12345678:32,@+er1 ;6a35123456789160 ++ and.b @0x12345678:32,@(0xffff9abc:16,er1) ;6a3512345678c1609abc ++ and.b @0x12345678:32,@(0x9abcdef0:32,er1) ;6a3512345678c9609abcdef0 ++ and.b @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6a3512345678d2609abc ++ and.b @0x12345678:32,@(0xffff9abc:16,r2.w) ;6a3512345678e2609abc ++ and.b @0x12345678:32,@(0xffff9abc:16,er2.l) ;6a3512345678f2609abc ++ and.b @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6a3512345678da609abcdef0 ++ and.b @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6a3512345678ea609abcdef0 ++ and.b @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6a3512345678fa609abcdef0 ++ and.b @0x12345678:32,@0xffff9abc:16 ;6a351234567840609abc ++ and.b @0x12345678:32,@0x9abcdef0:32 ;6a351234567848609abcdef0 ++ ++ and.w #0x1234:16,r1 ;79611234 ++ and.w #0x1234:16,@er1 ;015e01601234 ++ and.w #0x1234:16,@(0x6:2,er1) ;015e31601234 ++ and.w #0x1234:16,@er1+ ;015e81601234 ++ and.w #0x1234:16,@-er1 ;015eb1601234 ++ and.w #0x1234:16,@+er1 ;015e91601234 ++ and.w #0x1234:16,@er1- ;015ea1601234 ++ and.w #0x1234:16,@(0xffff9abc:16,er1) ;015ec1609abc1234 ++ and.w #0x1234:16,@(0x9abcdef0:32,er1) ;015ec9609abcdef01234 ++ and.w #0x1234:16,@(0xffff9abc:16,r2l.b) ;015ed2609abc1234 ++ and.w #0x1234:16,@(0xffff9abc:16,r2.w) ;015ee2609abc1234 ++ and.w #0x1234:16,@(0xffff9abc:16,er2.l) ;015ef2609abc1234 ++ and.w #0x1234:16,@(0x9abcdef0:32,r2l.b) ;015eda609abcdef01234 ++ and.w #0x1234:16,@(0x9abcdef0:32,r2.w) ;015eea609abcdef01234 ++ and.w #0x1234:16,@(0x9abcdef0:32,er2.l) ;015efa609abcdef01234 ++ and.w #0x1234:16,@0xffff9abc:16 ;015e40609abc1234 ++ and.w #0x1234:16,@0x9abcdef0:32 ;015e48609abcdef01234 ++ ++ and.w r3,r1 ;6631 ++ ++ and.w r3,@er1 ;7d906630 ++ and.w r3,@(0x6:2,er1) ;01593163 ++ and.w r3,@er1+ ;01598163 ++ and.w r3,@-er1 ;0159b163 ++ and.w r3,@+er1 ;01599163 ++ and.w r3,@er1- ;0159a163 ++ and.w r3,@(0x1234:16,er1) ;0159c1631234 ++ and.w r3,@(0x12345678:32,er1) ;0159c96312345678 ++ and.w r3,@(0x1234:16,r2l.b) ;0159d2631234 ++ and.w r3,@(0x1234:16,r2.w) ;0159e2631234 ++ and.w r3,@(0x1234:16,er2.l) ;0159f2631234 ++ and.w r3,@(0x12345678:32,r2l.b) ;0159da6312345678 ++ and.w r3,@(0x12345678:32,r2.w) ;0159ea6312345678 ++ and.w r3,@(0x12345678:32,er2.l) ;0159fa6312345678 ++ and.w r3,@0x1234:16 ;6b1812346630 ++ and.w r3,@0x12345678:32 ;6b38123456786630 ++ ++ and.w @er3,r1 ;7cb06601 ++ and.w @(0x6:2,er3),r1 ;015a3361 ++ and.w @er3+,r1 ;015a8361 ++ and.w @-er3,r1 ;015ab361 ++ and.w @+er3,r1 ;015a9361 ++ and.w @er3-,r1 ;015aa361 ++ and.w @(0x1234:16,er1),r1 ;015ac1611234 ++ and.w @(0x12345678:32,er1),r1 ;015ac96112345678 ++ and.w @(0x1234:16,r2l.b),r1 ;015ad2611234 ++ and.w @(0x1234:16,r2.w),r1 ;015ae2611234 ++ and.w @(0x1234:16,er2.l),r1 ;015af2611234 ++ and.w @(0x12345678:32,r2l.b),r1 ;015ada6112345678 ++ and.w @(0x12345678:32,r2.w),r1 ;015aea6112345678 ++ and.w @(0x12345678:32,er2.l),r1 ;015afa6112345678 ++ and.w @0x1234:16,r1 ;6b1012346601 ++ and.w @0x12345678:32,r1 ;6b30123456786601 ++ ++ and.w @er3,@er1 ;7cb50160 ++ and.w @er3,@(6:2,er1) ;7cb53160 ++ and.w @er3,@-er1 ;7cb5b160 ++ and.w @er3,@er1+ ;7cb58160 ++ and.w @er3,@er1- ;7cb5a160 ++ and.w @er3,@+er1 ;7cb59160 ++ and.w @er3,@(0xffff9abc:16,er1) ;7cb5c1609abc ++ and.w @er3,@(0x9abcdef0:32,er1) ;7cb5c9609abcdef0 ++ and.w @er3,@(0xffff9abc:16,r2l.b) ;7cb5d2609abc ++ and.w @er3,@(0xffff9abc:16,r2.w) ;7cb5e2609abc ++ and.w @er3,@(0xffff9abc:16,er2.l) ;7cb5f2609abc ++ and.w @er3,@(0x9abcdef0:32,r2l.b) ;7cb5da609abcdef0 ++ and.w @er3,@(0x9abcdef0:32,r2.w) ;7cb5ea609abcdef0 ++ and.w @er3,@(0x9abcdef0:32,er2.l) ;7cb5fa609abcdef0 ++ and.w @er3,@0xffff9abc:16 ;7cb540609abc ++ and.w @er3,@0x9abcdef0:32 ;7cb548609abcdef0 ++ ++ and.w @-er3,@er1 ;01576d3c0160 ++ and.w @-er3,@(6:2,er1) ;01576d3c3160 ++ and.w @-er3,@-er1 ;01576d3cb160 ++ and.w @-er3,@er1+ ;01576d3c8160 ++ and.w @-er3,@er1- ;01576d3ca160 ++ and.w @-er3,@+er1 ;01576d3c9160 ++ and.w @-er3,@(0xffff9abc:16,er1) ;01576d3cc1609abc ++ and.w @-er3,@(0x9abcdef0:32,er1) ;01576d3cc9609abcdef0 ++ and.w @-er3,@(0xffff9abc:16,r2l.b) ;01576d3cd2609abc ++ and.w @-er3,@(0xffff9abc:16,r2.w) ;01576d3ce2609abc ++ and.w @-er3,@(0xffff9abc:16,er2.l) ;01576d3cf2609abc ++ and.w @-er3,@(0x9abcdef0:32,r2l.b) ;01576d3cda609abcdef0 ++ and.w @-er3,@(0x9abcdef0:32,r2.w) ;01576d3cea609abcdef0 ++ and.w @-er3,@(0x9abcdef0:32,er2.l) ;01576d3cfa609abcdef0 ++ and.w @-er3,@0xffff9abc:16 ;01576d3c40609abc ++ and.w @-er3,@0x9abcdef0:32 ;01576d3c48609abcdef0 ++ ++ and.w @er3+,@er1 ;01546d3c0160 ++ and.w @er3+,@(6:2,er1) ;01546d3c3160 ++ and.w @er3+,@-er1 ;01546d3cb160 ++ and.w @er3+,@er1+ ;01546d3c8160 ++ and.w @er3+,@er1- ;01546d3ca160 ++ and.w @er3+,@+er1 ;01546d3c9160 ++ and.w @er3+,@(0xffff9abc:16,er1) ;01546d3cc1609abc ++ and.w @er3+,@(0x9abcdef0:32,er1) ;01546d3cc9609abcdef0 ++ and.w @er3+,@(0xffff9abc:16,r2l.b) ;01546d3cd2609abc ++ and.w @er3+,@(0xffff9abc:16,r2.w) ;01546d3ce2609abc ++ and.w @er3+,@(0xffff9abc:16,er2.l) ;01546d3cf2609abc ++ and.w @er3+,@(0x9abcdef0:32,r2l.b) ;01546d3cda609abcdef0 ++ and.w @er3+,@(0x9abcdef0:32,r2.w) ;01546d3cea609abcdef0 ++ and.w @er3+,@(0x9abcdef0:32,er2.l) ;01546d3cfa609abcdef0 ++ and.w @er3+,@0xffff9abc:16 ;01546d3c40609abc ++ and.w @er3+,@0x9abcdef0:32 ;01546d3c48609abcdef0 ++ ++ and.w @er3-,@er1 ;01566d3c0160 ++ and.w @er3-,@(6:2,er1) ;01566d3c3160 ++ and.w @er3-,@-er1 ;01566d3cb160 ++ and.w @er3-,@er1+ ;01566d3c8160 ++ and.w @er3-,@er1- ;01566d3ca160 ++ and.w @er3-,@+er1 ;01566d3c9160 ++ and.w @er3-,@(0xffff9abc:16,er1) ;01566d3cc1609abc ++ and.w @er3-,@(0x9abcdef0:32,er1) ;01566d3cc9609abcdef0 ++ and.w @er3-,@(0xffff9abc:16,r2l.b) ;01566d3cd2609abc ++ and.w @er3-,@(0xffff9abc:16,r2.w) ;01566d3ce2609abc ++ and.w @er3-,@(0xffff9abc:16,er2.l) ;01566d3cf2609abc ++ and.w @er3-,@(0x9abcdef0:32,r2l.b) ;01566d3cda609abcdef0 ++ and.w @er3-,@(0x9abcdef0:32,r2.w) ;01566d3cea609abcdef0 ++ and.w @er3-,@(0x9abcdef0:32,er2.l) ;01566d3cfa609abcdef0 ++ and.w @er3-,@0xffff9abc:16 ;01566d3c40609abc ++ and.w @er3-,@0x9abcdef0:32 ;01566d3c48609abcdef0 ++ ++ and.w @+er3,@er1 ;01556d3c0160 ++ and.w @+er3,@(6:2,er1) ;01556d3c3160 ++ and.w @+er3,@-er1 ;01556d3cb160 ++ and.w @+er3,@er1+ ;01556d3c8160 ++ and.w @+er3,@er1- ;01556d3ca160 ++ and.w @+er3,@+er1 ;01556d3c9160 ++ and.w @+er3,@(0xffff9abc:16,er1) ;01556d3cc1609abc ++ and.w @+er3,@(0x9abcdef0:32,er1) ;01556d3cc9609abcdef0 ++ and.w @+er3,@(0xffff9abc:16,r2l.b) ;01556d3cd2609abc ++ and.w @+er3,@(0xffff9abc:16,r2.w) ;01556d3ce2609abc ++ and.w @+er3,@(0xffff9abc:16,er2.l) ;01556d3cf2609abc ++ and.w @+er3,@(0x9abcdef0:32,r2l.b) ;01556d3cda609abcdef0 ++ and.w @+er3,@(0x9abcdef0:32,r2.w) ;01556d3cea609abcdef0 ++ and.w @+er3,@(0x9abcdef0:32,er2.l) ;01556d3cfa609abcdef0 ++ and.w @+er3,@0xffff9abc:16 ;01556d3c40609abc ++ and.w @+er3,@0x9abcdef0:32 ;01556d3c48609abcdef0 ++ ++ and.w @(0x1234:16,er3),@er1 ;01546f3c12340160 ++ and.w @(0x1234:16,er3),@(6:2,er1) ;01546f3c12343160 ++ and.w @(0x1234:16,er3),@-er1 ;01546f3c1234b160 ++ and.w @(0x1234:16,er3),@er1+ ;01546f3c12348160 ++ and.w @(0x1234:16,er3),@er1- ;01546f3c1234a160 ++ and.w @(0x1234:16,er3),@+er1 ;01546f3c12349160 ++ and.w @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01546f3c1234c1609abc ++ and.w @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01546f3c1234c9609abcdef0 ++ and.w @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01546f3c1234d2609abc ++ and.w @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01546f3c1234e2609abc ++ and.w @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01546f3c1234f2609abc ++ and.w @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01546f3c1234da609abcdef0 ++ and.w @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01546f3c1234ea609abcdef0 ++ and.w @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01546f3c1234fa609abcdef0 ++ and.w @(0x1234:16,er3),@0xffff9abc:16 ;01546f3c123440609abc ++ and.w @(0x1234:16,er3),@0x9abcdef0:32 ;01546f3c123448609abcdef0 ++ ++ and.w @(0x12345678:32,er3),@er1 ;78346b2c123456780160 ++ and.w @(0x12345678:32,er3),@(6:2,er1) ;78346b2c123456783160 ++ and.w @(0x12345678:32,er3),@-er1 ;78346b2c12345678b160 ++ and.w @(0x12345678:32,er3),@er1+ ;78346b2c123456788160 ++ and.w @(0x12345678:32,er3),@er1- ;78346b2c12345678a160 ++ and.w @(0x12345678:32,er3),@+er1 ;78346b2c123456789160 ++ and.w @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78346b2c12345678c1609abc ++ and.w @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78346b2c12345678c9609abcdef0 ++ and.w @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78346b2c12345678d2609abc ++ and.w @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78346b2c12345678e2609abc ++ and.w @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78346b2c12345678f2609abc ++ and.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78346b2c12345678da609abcdef0 ++ and.w @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78346b2c12345678ea609abcdef0 ++ and.w @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78346b2c12345678fa609abcdef0 ++ and.w @(0x12345678:32,er3),@0xffff9abc:16 ;78346b2c1234567840609abc ++ and.w @(0x12345678:32,er3),@0x9abcdef0:32 ;78346b2c1234567848609abcdef0 ++ ++ and.w @(0x1234:16,r3l.b),@er1 ;01556f3c12340160 ++ and.w @(0x1234:16,r3l.b),@(6:2,er1) ;01556f3c12343160 ++ and.w @(0x1234:16,r3l.b),@-er1 ;01556f3c1234b160 ++ and.w @(0x1234:16,r3l.b),@er1+ ;01556f3c12348160 ++ and.w @(0x1234:16,r3l.b),@er1- ;01556f3c1234a160 ++ and.w @(0x1234:16,r3l.b),@+er1 ;01556f3c12349160 ++ and.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01556f3c1234c1609abc ++ and.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01556f3c1234c9609abcdef0 ++ and.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01556f3c1234d2609abc ++ and.w @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01556f3c1234e2609abc ++ and.w @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01556f3c1234f2609abc ++ and.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01556f3c1234da609abcdef0 ++ and.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01556f3c1234ea609abcdef0 ++ and.w @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01556f3c1234fa609abcdef0 ++ and.w @(0x1234:16,r3l.b),@0xffff9abc:16 ;01556f3c123440609abc ++ and.w @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01556f3c123448609abcdef0 ++ ++ and.w @(0x1234:16,r3.w),@er1 ;01566f3c12340160 ++ and.w @(0x1234:16,r3.w),@(6:2,er1) ;01566f3c12343160 ++ and.w @(0x1234:16,r3.w),@-er1 ;01566f3c1234b160 ++ and.w @(0x1234:16,r3.w),@er1+ ;01566f3c12348160 ++ and.w @(0x1234:16,r3.w),@er1- ;01566f3c1234a160 ++ and.w @(0x1234:16,r3.w),@+er1 ;01566f3c12349160 ++ and.w @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01566f3c1234c1609abc ++ and.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01566f3c1234c9609abcdef0 ++ and.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01566f3c1234d2609abc ++ and.w @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01566f3c1234e2609abc ++ and.w @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01566f3c1234f2609abc ++ and.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01566f3c1234da609abcdef0 ++ and.w @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01566f3c1234ea609abcdef0 ++ and.w @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01566f3c1234fa609abcdef0 ++ and.w @(0x1234:16,r3.w),@0xffff9abc:16 ;01566f3c123440609abc ++ and.w @(0x1234:16,r3.w),@0x9abcdef0:32 ;01566f3c123448609abcdef0 ++ ++ and.w @(0x1234:16,er3.l),@er1 ;01576f3c12340160 ++ and.w @(0x1234:16,er3.l),@(6:2,er1) ;01576f3c12343160 ++ and.w @(0x1234:16,er3.l),@-er1 ;01576f3c1234b160 ++ and.w @(0x1234:16,er3.l),@er1+ ;01576f3c12348160 ++ and.w @(0x1234:16,er3.l),@er1- ;01576f3c1234a160 ++ and.w @(0x1234:16,er3.l),@+er1 ;01576f3c12349160 ++ and.w @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01576f3c1234c1609abc ++ and.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01576f3c1234c9609abcdef0 ++ and.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01576f3c1234d2609abc ++ and.w @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01576f3c1234e2609abc ++ and.w @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01576f3c1234f2609abc ++ and.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01576f3c1234da609abcdef0 ++ and.w @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01576f3c1234ea609abcdef0 ++ and.w @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01576f3c1234fa609abcdef0 ++ and.w @(0x1234:16,er3.l),@0xffff9abc:16 ;01576f3c123440609abc ++ and.w @(0x1234:16,er3.l),@0x9abcdef0:32 ;01576f3c123448609abcdef0 ++ ++ and.w @(0x12345678:32,r3l.b),@er1 ;78356b2c123456780160 ++ and.w @(0x12345678:32,r3l.b),@(6:2,er1) ;78356b2c123456783160 ++ and.w @(0x12345678:32,r3l.b),@-er1 ;78356b2c12345678b160 ++ and.w @(0x12345678:32,r3l.b),@er1+ ;78356b2c123456788160 ++ and.w @(0x12345678:32,r3l.b),@er1- ;78356b2c12345678a160 ++ and.w @(0x12345678:32,r3l.b),@+er1 ;78356b2c123456789160 ++ and.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78356b2c12345678c1609abc ++ and.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78356b2c12345678c9609abcdef0 ++ and.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78356b2c12345678d2609abc ++ and.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78356b2c12345678e2609abc ++ and.w @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78356b2c12345678f2609abc ++ and.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78356b2c12345678da609abcdef0 ++ and.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78356b2c12345678ea609abcdef0 ++ and.w @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78356b2c12345678fa609abcdef0 ++ and.w @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78356b2c1234567840609abc ++ and.w @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78356b2c1234567848609abcdef0 ++ ++ and.w @(0x12345678:32,r3.w),@er1 ;78366b2c123456780160 ++ and.w @(0x12345678:32,r3.w),@(6:2,er1) ;78366b2c123456783160 ++ and.w @(0x12345678:32,r3.w),@-er1 ;78366b2c12345678b160 ++ and.w @(0x12345678:32,r3.w),@er1+ ;78366b2c123456788160 ++ and.w @(0x12345678:32,r3.w),@er1- ;78366b2c12345678a160 ++ and.w @(0x12345678:32,r3.w),@+er1 ;78366b2c123456789160 ++ and.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78366b2c12345678c1609abc ++ and.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78366b2c12345678c9609abcdef0 ++ and.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78366b2c12345678d2609abc ++ and.w @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78366b2c12345678e2609abc ++ and.w @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78366b2c12345678f2609abc ++ and.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78366b2c12345678da609abcdef0 ++ and.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78366b2c12345678ea609abcdef0 ++ and.w @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78366b2c12345678fa609abcdef0 ++ and.w @(0x12345678:32,r3.w),@0xffff9abc:16 ;78366b2c1234567840609abc ++ and.w @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78366b2c1234567848609abcdef0 ++ ++ and.w @(0x12345678:32,er3.l),@er1 ;78376b2c123456780160 ++ and.w @(0x12345678:32,er3.l),@(6:2,er1) ;78376b2c123456783160 ++ and.w @(0x12345678:32,er3.l),@-er1 ;78376b2c12345678b160 ++ and.w @(0x12345678:32,er3.l),@er1+ ;78376b2c123456788160 ++ and.w @(0x12345678:32,er3.l),@er1- ;78376b2c12345678a160 ++ and.w @(0x12345678:32,er3.l),@+er1 ;78376b2c123456789160 ++ and.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78376b2c12345678c1609abc ++ and.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78376b2c12345678c9609abcdef0 ++ and.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78376b2c12345678d2609abc ++ and.w @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78376b2c12345678e2609abc ++ and.w @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78376b2c12345678f2609abc ++ and.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78376b2c12345678da609abcdef0 ++ and.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78376b2c12345678ea609abcdef0 ++ and.w @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78376b2c12345678fa609abcdef0 ++ and.w @(0x12345678:32,er3.l),@0xffff9abc:16 ;78376b2c1234567840609abc ++ and.w @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78376b2c1234567848609abcdef0 ++ ++ and.w @0x1234:16,@er1 ;6b1512340160 ++ and.w @0x1234:16,@(6:2,er1) ;6b1512343160 ++ and.w @0x1234:16,@-er1 ;6b151234b160 ++ and.w @0x1234:16,@er1+ ;6b1512348160 ++ and.w @0x1234:16,@er1- ;6b151234a160 ++ and.w @0x1234:16,@+er1 ;6b1512349160 ++ and.w @0x1234:16,@(0xffff9abc:16,er1) ;6b151234c1609abc ++ and.w @0x1234:16,@(0x9abcdef0:32,er1) ;6b151234c9609abcdef0 ++ and.w @0x1234:16,@(0xffff9abc:16,r2l.b) ;6b151234d2609abc ++ and.w @0x1234:16,@(0xffff9abc:16,r2.w) ;6b151234e2609abc ++ and.w @0x1234:16,@(0xffff9abc:16,er2.l) ;6b151234f2609abc ++ and.w @0x1234:16,@(0x9abcdef0:32,r2l.b) ;6b151234da609abcdef0 ++ and.w @0x1234:16,@(0x9abcdef0:32,r2.w) ;6b151234ea609abcdef0 ++ and.w @0x1234:16,@(0x9abcdef0:32,er2.l) ;6b151234fa609abcdef0 ++ and.w @0x1234:16,@0xffff9abc:16 ;6b15123440609abc ++ and.w @0x1234:16,@0x9abcdef0:32 ;6b15123448609abcdef0 ++ ++ and.w @0x12345678:32,@er1 ;6b35123456780160 ++ and.w @0x12345678:32,@(6:2,er1) ;6b35123456783160 ++ and.w @0x12345678:32,@-er1 ;6b3512345678b160 ++ and.w @0x12345678:32,@er1+ ;6b35123456788160 ++ and.w @0x12345678:32,@er1- ;6b3512345678a160 ++ and.w @0x12345678:32,@+er1 ;6b35123456789160 ++ and.w @0x12345678:32,@(0xffff9abc:16,er1) ;6b3512345678c1609abc ++ and.w @0x12345678:32,@(0x9abcdef0:32,er1) ;6b3512345678c9609abcdef0 ++ and.w @0x12345678:32,@(0xffff9abc:16,r2l.b) ;6b3512345678d2609abc ++ and.w @0x12345678:32,@(0xffff9abc:16,r2.w) ;6b3512345678e2609abc ++ and.w @0x12345678:32,@(0xffff9abc:16,er2.l) ;6b3512345678f2609abc ++ and.w @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;6b3512345678da609abcdef0 ++ and.w @0x12345678:32,@(0x9abcdef0:32,r2.w) ;6b3512345678ea609abcdef0 ++ and.w @0x12345678:32,@(0x9abcdef0:32,er2.l) ;6b3512345678fa609abcdef0 ++ and.w @0x12345678:32,@0xffff9abc:16 ;6b351234567840609abc ++ and.w @0x12345678:32,@0x9abcdef0:32 ;6b351234567848609abcdef0 ++ ++ and.l #0x12345678:32,er1 ;7a6112345678 ++ and.l #0x1234:16,er1 ;7a691234 ++ and.l #0x12345678:32,@er1 ;010e016812345678 ++ and.l #0x12345678:32,@(0xc:2,er1) ;010e316812345678 ++ and.l #0x12345678:32,@er1+ ;010e816812345678 ++ and.l #0x12345678:32,@-er1 ;010eb16812345678 ++ and.l #0x12345678:32,@+er1 ;010e916812345678 ++ and.l #0x12345678:32,@er1- ;010ea16812345678 ++ and.l #0x12345678:32,@(0xffff9abc:16,er1) ;010ec1689abc12345678 ++ and.l #0x12345678:32,@(0x9abcdef0:32,er1) ;010ec9689abcdef012345678 ++ and.l #0x12345678:32,@(0xffff9abc:16,r2l.b) ;010ed2689abc12345678 ++ and.l #0x12345678:32,@(0xffff9abc:16,r2.w) ;010ee2689abc12345678 ++ and.l #0x12345678:32,@(0xffff9abc:16,er2.l) ;010ef2689abc12345678 ++ and.l #0x12345678:32,@(0x9abcdef0:32,r2l.b) ;010eda689abcdef012345678 ++ and.l #0x12345678:32,@(0x9abcdef0:32,r2.w) ;010eea689abcdef012345678 ++ and.l #0x12345678:32,@(0x9abcdef0:32,er2.l) ;010efa689abcdef012345678 ++ and.l #0x12345678:32,@0xffff9abc:16 ;010e40689abc12345678 ++ and.l #0x12345678:32,@0x9abcdef0:32 ;010e48689abcdef012345678 ++ and.l #0x1234:16,@er1 ;010e01601234 ++ and.l #0x1234:16,@(0xc:2,er1) ;010e31601234 ++ and.l #0x1234:16,@er1+ ;010e81601234 ++ and.l #0x1234:16,@-er1 ;010eb1601234 ++ and.l #0x1234:16,@+er1 ;010e91601234 ++ and.l #0x1234:16,@er1- ;010ea1601234 ++ and.l #0x1234:16,@(0xffff9abc:16,er1) ;010ec1609abc1234 ++ and.l #0x1234:16,@(0x9abcdef0:32,er1) ;010ec9609abcdef01234 ++ and.l #0x1234:16,@(0xffff9abc:16,r2l.b) ;010ed2609abc1234 ++ and.l #0x1234:16,@(0xffff9abc:16,r2.w) ;010ee2609abc1234 ++ and.l #0x1234:16,@(0xffff9abc:16,er2.l) ;010ef2609abc1234 ++ and.l #0x1234:16,@(0x9abcdef0:32,r2l.b) ;010eda609abcdef01234 ++ and.l #0x1234:16,@(0x9abcdef0:32,r2.w) ;010eea609abcdef01234 ++ and.l #0x1234:16,@(0x9abcdef0:32,er2.l) ;010efa609abcdef01234 ++ and.l #0x1234:16,@0xffff9abc:16 ;010e40609abc1234 ++ and.l #0x1234:16,@0x9abcdef0:32 ;010e48609abcdef01234 ++ ++ and.l er3,er1 ;01f06631 ++ ++ and.l er3,@er1 ;01090163 ++ and.l er3,@(0xc:2,er1) ;01093163 ++ and.l er3,@er1+ ;01098163 ++ and.l er3,@-er1 ;0109b163 ++ and.l er3,@+er1 ;01099163 ++ and.l er3,@er1- ;0109a163 ++ and.l er3,@(0x1234:16,er1) ;0109c1631234 ++ and.l er3,@(0x12345678:32,er1) ;0109c96312345678 ++ and.l er3,@(0x1234:16,r2l.b) ;0109d2631234 ++ and.l er3,@(0x1234:16,r2.w) ;0109e2631234 ++ and.l er3,@(0x1234:16,er2.l) ;0109f2631234 ++ and.l er3,@(0x12345678:32,r2l.b) ;0109da6312345678 ++ and.l er3,@(0x12345678:32,r2.w) ;0109ea6312345678 ++ and.l er3,@(0x12345678:32,er2.l) ;0109fa6312345678 ++ and.l er3,@0x1234:16 ;010940631234 ++ and.l er3,@0x12345678:32 ;0109486312345678 ++ ++ and.l @er3,er1 ;010a0361 ++ and.l @(0xc:2,er3),er1 ;010a3361 ++ and.l @er3+,er1 ;010a8361 ++ and.l @-er3,er1 ;010ab361 ++ and.l @+er3,er1 ;010a9361 ++ and.l @er3-,er1 ;010aa361 ++ and.l @(0x1234:16,er1),er1 ;010ac1611234 ++ and.l @(0x12345678:32,er1),er1 ;010ac96112345678 ++ and.l @(0x1234:16,r2l.b),er1 ;010ad2611234 ++ and.l @(0x1234:16,r2.w),er1 ;010ae2611234 ++ and.l @(0x1234:16,er2.l),er1 ;010af2611234 ++ and.l @(0x12345678:32,r2l.b),er1 ;010ada6112345678 ++ and.l @(0x12345678:32,r2.w),er1 ;010aea6112345678 ++ and.l @(0x12345678:32,er2.l),er1 ;010afa6112345678 ++ and.l @0x1234:16,er1 ;010a40611234 ++ and.l @0x12345678:32,er1 ;010a486112345678 ++ ++ and.l @er3,@er1 ;0104693c0160 ++ and.l @er3,@(0xc:2,er1) ;0104693c3160 ++ and.l @er3,@-er1 ;0104693cb160 ++ and.l @er3,@er1+ ;0104693c8160 ++ and.l @er3,@er1- ;0104693ca160 ++ and.l @er3,@+er1 ;0104693c9160 ++ and.l @er3,@(0xffff9abc:16,er1) ;0104693cc1609abc ++ and.l @er3,@(0x9abcdef0:32,er1) ;0104693cc9609abcdef0 ++ and.l @er3,@(0xffff9abc:16,r2l.b) ;0104693cd2609abc ++ and.l @er3,@(0xffff9abc:16,r2.w) ;0104693ce2609abc ++ and.l @er3,@(0xffff9abc:16,er2.l) ;0104693cf2609abc ++ and.l @er3,@(0x9abcdef0:32,r2l.b) ;0104693cda609abcdef0 ++ and.l @er3,@(0x9abcdef0:32,r2.w) ;0104693cea609abcdef0 ++ and.l @er3,@(0x9abcdef0:32,er2.l) ;0104693cfa609abcdef0 ++ and.l @er3,@0xffff9abc:16 ;0104693c40609abc ++ and.l @er3,@0x9abcdef0:32 ;0104693c48609abcdef0 ++ ++ and.l @(0xc:2,er3),@er1 ;0107693c0160 ++ and.l @(0xc:2,er3),@(0xc:2,er1) ;0107693c3160 ++ and.l @(0xc:2,er3),@-er1 ;0107693cb160 ++ and.l @(0xc:2,er3),@er1+ ;0107693c8160 ++ and.l @(0xc:2,er3),@er1- ;0107693ca160 ++ and.l @(0xc:2,er3),@+er1 ;0107693c9160 ++ and.l @(0xc:2,er3),@(0xffff9abc:16,er1) ;0107693cc1609abc ++ and.l @(0xc:2,er3),@(0x9abcdef0:32,er1) ;0107693cc9609abcdef0 ++ and.l @(0xc:2,er3),@(0xffff9abc:16,r2l.b) ;0107693cd2609abc ++ and.l @(0xc:2,er3),@(0xffff9abc:16,r2.w) ;0107693ce2609abc ++ and.l @(0xc:2,er3),@(0xffff9abc:16,er2.l) ;0107693cf2609abc ++ and.l @(0xc:2,er3),@(0x9abcdef0:32,r2l.b) ;0107693cda609abcdef0 ++ and.l @(0xc:2,er3),@(0x9abcdef0:32,r2.w) ;0107693cea609abcdef0 ++ and.l @(0xc:2,er3),@(0x9abcdef0:32,er2.l) ;0107693cfa609abcdef0 ++ and.l @(0xc:2,er3),@0xffff9abc:16 ;0107693c40609abc ++ and.l @(0xc:2,er3),@0x9abcdef0:32 ;0107693c48609abcdef0 ++ ++ and.l @-er3,@er1 ;01076d3c0160 ++ and.l @-er3,@(0xc:2,er1) ;01076d3c3160 ++ and.l @-er3,@-er1 ;01076d3cb160 ++ and.l @-er3,@er1+ ;01076d3c8160 ++ and.l @-er3,@er1- ;01076d3ca160 ++ and.l @-er3,@+er1 ;01076d3c9160 ++ and.l @-er3,@(0xffff9abc:16,er1) ;01076d3cc1609abc ++ and.l @-er3,@(0x9abcdef0:32,er1) ;01076d3cc9609abcdef0 ++ and.l @-er3,@(0xffff9abc:16,r2l.b) ;01076d3cd2609abc ++ and.l @-er3,@(0xffff9abc:16,r2.w) ;01076d3ce2609abc ++ and.l @-er3,@(0xffff9abc:16,er2.l) ;01076d3cf2609abc ++ and.l @-er3,@(0x9abcdef0:32,r2l.b) ;01076d3cda609abcdef0 ++ and.l @-er3,@(0x9abcdef0:32,r2.w) ;01076d3cea609abcdef0 ++ and.l @-er3,@(0x9abcdef0:32,er2.l) ;01076d3cfa609abcdef0 ++ and.l @-er3,@0xffff9abc:16 ;01076d3c40609abc ++ and.l @-er3,@0x9abcdef0:32 ;01076d3c48609abcdef0 ++ ++ and.l @er3+,@er1 ;01046d3c0160 ++ and.l @er3+,@(0xc:2,er1) ;01046d3c3160 ++ and.l @er3+,@-er1 ;01046d3cb160 ++ and.l @er3+,@er1+ ;01046d3c8160 ++ and.l @er3+,@er1- ;01046d3ca160 ++ and.l @er3+,@+er1 ;01046d3c9160 ++ and.l @er3+,@(0xffff9abc:16,er1) ;01046d3cc1609abc ++ and.l @er3+,@(0x9abcdef0:32,er1) ;01046d3cc9609abcdef0 ++ and.l @er3+,@(0xffff9abc:16,r2l.b) ;01046d3cd2609abc ++ and.l @er3+,@(0xffff9abc:16,r2.w) ;01046d3ce2609abc ++ and.l @er3+,@(0xffff9abc:16,er2.l) ;01046d3cf2609abc ++ and.l @er3+,@(0x9abcdef0:32,r2l.b) ;01046d3cda609abcdef0 ++ and.l @er3+,@(0x9abcdef0:32,r2.w) ;01046d3cea609abcdef0 ++ and.l @er3+,@(0x9abcdef0:32,er2.l) ;01046d3cfa609abcdef0 ++ and.l @er3+,@0xffff9abc:16 ;01046d3c40609abc ++ and.l @er3+,@0x9abcdef0:32 ;01046d3c48609abcdef0 ++ ++ and.l @er3-,@er1 ;01066d3c0160 ++ and.l @er3-,@(0xc:2,er1) ;01066d3c3160 ++ and.l @er3-,@-er1 ;01066d3cb160 ++ and.l @er3-,@er1+ ;01066d3c8160 ++ and.l @er3-,@er1- ;01066d3ca160 ++ and.l @er3-,@+er1 ;01066d3c9160 ++ and.l @er3-,@(0xffff9abc:16,er1) ;01066d3cc1609abc ++ and.l @er3-,@(0x9abcdef0:32,er1) ;01066d3cc9609abcdef0 ++ and.l @er3-,@(0xffff9abc:16,r2l.b) ;01066d3cd2609abc ++ and.l @er3-,@(0xffff9abc:16,r2.w) ;01066d3ce2609abc ++ and.l @er3-,@(0xffff9abc:16,er2.l) ;01066d3cf2609abc ++ and.l @er3-,@(0x9abcdef0:32,r2l.b) ;01066d3cda609abcdef0 ++ and.l @er3-,@(0x9abcdef0:32,r2.w) ;01066d3cea609abcdef0 ++ and.l @er3-,@(0x9abcdef0:32,er2.l) ;01066d3cfa609abcdef0 ++ and.l @er3-,@0xffff9abc:16 ;01066d3c40609abc ++ and.l @er3-,@0x9abcdef0:32 ;01066d3c48609abcdef0 ++ ++ and.l @+er3,@er1 ;01056d3c0160 ++ and.l @+er3,@(0xc:2,er1) ;01056d3c3160 ++ and.l @+er3,@-er1 ;01056d3cb160 ++ and.l @+er3,@er1+ ;01056d3c8160 ++ and.l @+er3,@er1- ;01056d3ca160 ++ and.l @+er3,@+er1 ;01056d3c9160 ++ and.l @+er3,@(0xffff9abc:16,er1) ;01056d3cc1609abc ++ and.l @+er3,@(0x9abcdef0:32,er1) ;01056d3cc9609abcdef0 ++ and.l @+er3,@(0xffff9abc:16,r2l.b) ;01056d3cd2609abc ++ and.l @+er3,@(0xffff9abc:16,r2.w) ;01056d3ce2609abc ++ and.l @+er3,@(0xffff9abc:16,er2.l) ;01056d3cf2609abc ++ and.l @+er3,@(0x9abcdef0:32,r2l.b) ;01056d3cda609abcdef0 ++ and.l @+er3,@(0x9abcdef0:32,r2.w) ;01056d3cea609abcdef0 ++ and.l @+er3,@(0x9abcdef0:32,er2.l) ;01056d3cfa609abcdef0 ++ and.l @+er3,@0xffff9abc:16 ;01056d3c40609abc ++ and.l @+er3,@0x9abcdef0:32 ;01056d3c48609abcdef0 ++ ++ and.l @(0x1234:16,er3),@er1 ;01046f3c12340160 ++ and.l @(0x1234:16,er3),@(0xc:2,er1) ;01046f3c12343160 ++ and.l @(0x1234:16,er3),@-er1 ;01046f3c1234b160 ++ and.l @(0x1234:16,er3),@er1+ ;01046f3c12348160 ++ and.l @(0x1234:16,er3),@er1- ;01046f3c1234a160 ++ and.l @(0x1234:16,er3),@+er1 ;01046f3c12349160 ++ and.l @(0x1234:16,er3),@(0xffff9abc:16,er1) ;01046f3c1234c1609abc ++ and.l @(0x1234:16,er3),@(0x9abcdef0:32,er1) ;01046f3c1234c9609abcdef0 ++ and.l @(0x1234:16,er3),@(0xffff9abc:16,r2l.b) ;01046f3c1234d2609abc ++ and.l @(0x1234:16,er3),@(0xffff9abc:16,r2.w) ;01046f3c1234e2609abc ++ and.l @(0x1234:16,er3),@(0xffff9abc:16,er2.l) ;01046f3c1234f2609abc ++ and.l @(0x1234:16,er3),@(0x9abcdef0:32,r2l.b) ;01046f3c1234da609abcdef0 ++ and.l @(0x1234:16,er3),@(0x9abcdef0:32,r2.w) ;01046f3c1234ea609abcdef0 ++ and.l @(0x1234:16,er3),@(0x9abcdef0:32,er2.l) ;01046f3c1234fa609abcdef0 ++ and.l @(0x1234:16,er3),@0xffff9abc:16 ;01046f3c123440609abc ++ and.l @(0x1234:16,er3),@0x9abcdef0:32 ;01046f3c123448609abcdef0 ++ ++ and.l @(0x12345678:32,er3),@er1 ;78b46b2c123456780160 ++ and.l @(0x12345678:32,er3),@(0xc:2,er1) ;78b46b2c123456783160 ++ and.l @(0x12345678:32,er3),@-er1 ;78b46b2c12345678b160 ++ and.l @(0x12345678:32,er3),@er1+ ;78b46b2c123456788160 ++ and.l @(0x12345678:32,er3),@er1- ;78b46b2c12345678a160 ++ and.l @(0x12345678:32,er3),@+er1 ;78b46b2c123456789160 ++ and.l @(0x12345678:32,er3),@(0xffff9abc:16,er1) ;78b46b2c12345678c1609abc ++ and.l @(0x12345678:32,er3),@(0x9abcdef0:32,er1) ;78b46b2c12345678c9609abcdef0 ++ and.l @(0x12345678:32,er3),@(0xffff9abc:16,r2l.b) ;78b46b2c12345678d2609abc ++ and.l @(0x12345678:32,er3),@(0xffff9abc:16,r2.w) ;78b46b2c12345678e2609abc ++ and.l @(0x12345678:32,er3),@(0xffff9abc:16,er2.l) ;78b46b2c12345678f2609abc ++ and.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2l.b) ;78b46b2c12345678da609abcdef0 ++ and.l @(0x12345678:32,er3),@(0x9abcdef0:32,r2.w) ;78b46b2c12345678ea609abcdef0 ++ and.l @(0x12345678:32,er3),@(0x9abcdef0:32,er2.l) ;78b46b2c12345678fa609abcdef0 ++ and.l @(0x12345678:32,er3),@0xffff9abc:16 ;78b46b2c1234567840609abc ++ and.l @(0x12345678:32,er3),@0x9abcdef0:32 ;78b46b2c1234567848609abcdef0 ++ ++ and.l @(0x1234:16,r3l.b),@er1 ;01056f3c12340160 ++ and.l @(0x1234:16,r3l.b),@(0xc:2,er1) ;01056f3c12343160 ++ and.l @(0x1234:16,r3l.b),@-er1 ;01056f3c1234b160 ++ and.l @(0x1234:16,r3l.b),@er1+ ;01056f3c12348160 ++ and.l @(0x1234:16,r3l.b),@er1- ;01056f3c1234a160 ++ and.l @(0x1234:16,r3l.b),@+er1 ;01056f3c12349160 ++ and.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er1) ;01056f3c1234c1609abc ++ and.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er1) ;01056f3c1234c9609abcdef0 ++ and.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2l.b) ;01056f3c1234d2609abc ++ and.l @(0x1234:16,r3l.b),@(0xffff9abc:16,r2.w) ;01056f3c1234e2609abc ++ and.l @(0x1234:16,r3l.b),@(0xffff9abc:16,er2.l) ;01056f3c1234f2609abc ++ and.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2l.b) ;01056f3c1234da609abcdef0 ++ and.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,r2.w) ;01056f3c1234ea609abcdef0 ++ and.l @(0x1234:16,r3l.b),@(0x9abcdef0:32,er2.l) ;01056f3c1234fa609abcdef0 ++ and.l @(0x1234:16,r3l.b),@0xffff9abc:16 ;01056f3c123440609abc ++ and.l @(0x1234:16,r3l.b),@0x9abcdef0:32 ;01056f3c123448609abcdef0 ++ ++ and.l @(0x1234:16,r3.w),@er1 ;01066f3c12340160 ++ and.l @(0x1234:16,r3.w),@(0xc:2,er1) ;01066f3c12343160 ++ and.l @(0x1234:16,r3.w),@-er1 ;01066f3c1234b160 ++ and.l @(0x1234:16,r3.w),@er1+ ;01066f3c12348160 ++ and.l @(0x1234:16,r3.w),@er1- ;01066f3c1234a160 ++ and.l @(0x1234:16,r3.w),@+er1 ;01066f3c12349160 ++ and.l @(0x1234:16,r3.w),@(0xffff9abc:16,er1) ;01066f3c1234c1609abc ++ and.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er1) ;01066f3c1234c9609abcdef0 ++ and.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2l.b) ;01066f3c1234d2609abc ++ and.l @(0x1234:16,r3.w),@(0xffff9abc:16,r2.w) ;01066f3c1234e2609abc ++ and.l @(0x1234:16,r3.w),@(0xffff9abc:16,er2.l) ;01066f3c1234f2609abc ++ and.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2l.b) ;01066f3c1234da609abcdef0 ++ and.l @(0x1234:16,r3.w),@(0x9abcdef0:32,r2.w) ;01066f3c1234ea609abcdef0 ++ and.l @(0x1234:16,r3.w),@(0x9abcdef0:32,er2.l) ;01066f3c1234fa609abcdef0 ++ and.l @(0x1234:16,r3.w),@0xffff9abc:16 ;01066f3c123440609abc ++ and.l @(0x1234:16,r3.w),@0x9abcdef0:32 ;01066f3c123448609abcdef0 ++ ++ and.l @(0x1234:16,er3.l),@er1 ;01076f3c12340160 ++ and.l @(0x1234:16,er3.l),@(0xc:2,er1) ;01076f3c12343160 ++ and.l @(0x1234:16,er3.l),@-er1 ;01076f3c1234b160 ++ and.l @(0x1234:16,er3.l),@er1+ ;01076f3c12348160 ++ and.l @(0x1234:16,er3.l),@er1- ;01076f3c1234a160 ++ and.l @(0x1234:16,er3.l),@+er1 ;01076f3c12349160 ++ and.l @(0x1234:16,er3.l),@(0xffff9abc:16,er1) ;01076f3c1234c1609abc ++ and.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er1) ;01076f3c1234c9609abcdef0 ++ and.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2l.b) ;01076f3c1234d2609abc ++ and.l @(0x1234:16,er3.l),@(0xffff9abc:16,r2.w) ;01076f3c1234e2609abc ++ and.l @(0x1234:16,er3.l),@(0xffff9abc:16,er2.l) ;01076f3c1234f2609abc ++ and.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2l.b) ;01076f3c1234da609abcdef0 ++ and.l @(0x1234:16,er3.l),@(0x9abcdef0:32,r2.w) ;01076f3c1234ea609abcdef0 ++ and.l @(0x1234:16,er3.l),@(0x9abcdef0:32,er2.l) ;01076f3c1234fa609abcdef0 ++ and.l @(0x1234:16,er3.l),@0xffff9abc:16 ;01076f3c123440609abc ++ and.l @(0x1234:16,er3.l),@0x9abcdef0:32 ;01076f3c123448609abcdef0 ++ ++ and.l @(0x12345678:32,r3l.b),@er1 ;78b56b2c123456780160 ++ and.l @(0x12345678:32,r3l.b),@(0xc:2,er1) ;78b56b2c123456783160 ++ and.l @(0x12345678:32,r3l.b),@-er1 ;78b56b2c12345678b160 ++ and.l @(0x12345678:32,r3l.b),@er1+ ;78b56b2c123456788160 ++ and.l @(0x12345678:32,r3l.b),@er1- ;78b56b2c12345678a160 ++ and.l @(0x12345678:32,r3l.b),@+er1 ;78b56b2c123456789160 ++ and.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er1) ;78b56b2c12345678c1609abc ++ and.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er1) ;78b56b2c12345678c9609abcdef0 ++ and.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2l.b) ;78b56b2c12345678d2609abc ++ and.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,r2.w) ;78b56b2c12345678e2609abc ++ and.l @(0x12345678:32,r3l.b),@(0xffff9abc:16,er2.l) ;78b56b2c12345678f2609abc ++ and.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2l.b) ;78b56b2c12345678da609abcdef0 ++ and.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,r2.w) ;78b56b2c12345678ea609abcdef0 ++ and.l @(0x12345678:32,r3l.b),@(0x9abcdef0:32,er2.l) ;78b56b2c12345678fa609abcdef0 ++ and.l @(0x12345678:32,r3l.b),@0xffff9abc:16 ;78b56b2c1234567840609abc ++ and.l @(0x12345678:32,r3l.b),@0x9abcdef0:32 ;78b56b2c1234567848609abcdef0 ++ ++ and.l @(0x12345678:32,r3.w),@er1 ;78b66b2c123456780160 ++ and.l @(0x12345678:32,r3.w),@(0xc:2,er1) ;78b66b2c123456783160 ++ and.l @(0x12345678:32,r3.w),@-er1 ;78b66b2c12345678b160 ++ and.l @(0x12345678:32,r3.w),@er1+ ;78b66b2c123456788160 ++ and.l @(0x12345678:32,r3.w),@er1- ;78b66b2c12345678a160 ++ and.l @(0x12345678:32,r3.w),@+er1 ;78b66b2c123456789160 ++ and.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er1) ;78b66b2c12345678c1609abc ++ and.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er1) ;78b66b2c12345678c9609abcdef0 ++ and.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2l.b) ;78b66b2c12345678d2609abc ++ and.l @(0x12345678:32,r3.w),@(0xffff9abc:16,r2.w) ;78b66b2c12345678e2609abc ++ and.l @(0x12345678:32,r3.w),@(0xffff9abc:16,er2.l) ;78b66b2c12345678f2609abc ++ and.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2l.b) ;78b66b2c12345678da609abcdef0 ++ and.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,r2.w) ;78b66b2c12345678ea609abcdef0 ++ and.l @(0x12345678:32,r3.w),@(0x9abcdef0:32,er2.l) ;78b66b2c12345678fa609abcdef0 ++ and.l @(0x12345678:32,r3.w),@0xffff9abc:16 ;78b66b2c1234567840609abc ++ and.l @(0x12345678:32,r3.w),@0x9abcdef0:32 ;78b66b2c1234567848609abcdef0 ++ ++ and.l @(0x12345678:32,er3.l),@er1 ;78b76b2c123456780160 ++ and.l @(0x12345678:32,er3.l),@(0xc:2,er1) ;78b76b2c123456783160 ++ and.l @(0x12345678:32,er3.l),@-er1 ;78b76b2c12345678b160 ++ and.l @(0x12345678:32,er3.l),@er1+ ;78b76b2c123456788160 ++ and.l @(0x12345678:32,er3.l),@er1- ;78b76b2c12345678a160 ++ and.l @(0x12345678:32,er3.l),@+er1 ;78b76b2c123456789160 ++ and.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er1) ;78b76b2c12345678c1609abc ++ and.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er1) ;78b76b2c12345678c9609abcdef0 ++ and.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2l.b) ;78b76b2c12345678d2609abc ++ and.l @(0x12345678:32,er3.l),@(0xffff9abc:16,r2.w) ;78b76b2c12345678e2609abc ++ and.l @(0x12345678:32,er3.l),@(0xffff9abc:16,er2.l) ;78b76b2c12345678f2609abc ++ and.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2l.b) ;78b76b2c12345678da609abcdef0 ++ and.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,r2.w) ;78b76b2c12345678ea609abcdef0 ++ and.l @(0x12345678:32,er3.l),@(0x9abcdef0:32,er2.l) ;78b76b2c12345678fa609abcdef0 ++ and.l @(0x12345678:32,er3.l),@0xffff9abc:16 ;78b76b2c1234567840609abc ++ and.l @(0x12345678:32,er3.l),@0x9abcdef0:32 ;78b76b2c1234567848609abcdef0 ++ ++ and.l @0x1234:16,@er1 ;01046b0c12340160 ++ and.l @0x1234:16,@(0xc:2,er1) ;01046b0c12343160 ++ and.l @0x1234:16,@-er1 ;01046b0c1234b160 ++ and.l @0x1234:16,@er1+ ;01046b0c12348160 ++ and.l @0x1234:16,@er1- ;01046b0c1234a160 ++ and.l @0x1234:16,@+er1 ;01046b0c12349160 ++ and.l @0x1234:16,@(0xffff9abc:16,er1) ;01046b0c1234c1609abc ++ and.l @0x1234:16,@(0x9abcdef0:32,er1) ;01046b0c1234c9609abcdef0 ++ and.l @0x1234:16,@(0xffff9abc:16,r2l.b) ;01046b0c1234d2609abc ++ and.l @0x1234:16,@(0xffff9abc:16,r2.w) ;01046b0c1234e2609abc ++ and.l @0x1234:16,@(0xffff9abc:16,er2.l) ;01046b0c1234f2609abc ++ and.l @0x1234:16,@(0x9abcdef0:32,r2l.b) ;01046b0c1234da609abcdef0 ++ and.l @0x1234:16,@(0x9abcdef0:32,r2.w) ;01046b0c1234ea609abcdef0 ++ and.l @0x1234:16,@(0x9abcdef0:32,er2.l) ;01046b0c1234fa609abcdef0 ++ and.l @0x1234:16,@0xffff9abc:16 ;01046b0c123440609abc ++ and.l @0x1234:16,@0x9abcdef0:32 ;01046b0c123448609abcdef0 ++ ++ and.l @0x12345678:32,@er1 ;01046b2c123456780160 ++ and.l @0x12345678:32,@(0xc:2,er1) ;01046b2c123456783160 ++ and.l @0x12345678:32,@-er1 ;01046b2c12345678b160 ++ and.l @0x12345678:32,@er1+ ;01046b2c123456788160 ++ and.l @0x12345678:32,@er1- ;01046b2c12345678a160 ++ and.l @0x12345678:32,@+er1 ;01046b2c123456789160 ++ and.l @0x12345678:32,@(0xffff9abc:16,er1) ;01046b2c12345678c1609abc ++ and.l @0x12345678:32,@(0x9abcdef0:32,er1) ;01046b2c12345678c9609abcdef0 ++ and.l @0x12345678:32,@(0xffff9abc:16,r2l.b) ;01046b2c12345678d2609abc ++ and.l @0x12345678:32,@(0xffff9abc:16,r2.w) ;01046b2c12345678e2609abc ++ and.l @0x12345678:32,@(0xffff9abc:16,er2.l) ;01046b2c12345678f2609abc ++ and.l @0x12345678:32,@(0x9abcdef0:32,r2l.b) ;01046b2c12345678da609abcdef0 ++ and.l @0x12345678:32,@(0x9abcdef0:32,r2.w) ;01046b2c12345678ea609abcdef0 ++ and.l @0x12345678:32,@(0x9abcdef0:32,er2.l) ;01046b2c12345678fa609abcdef0 ++ and.l @0x12345678:32,@0xffff9abc:16 ;01046b2c1234567840609abc ++ and.l @0x12345678:32,@0x9abcdef0:32 ;01046b2c1234567848609abcdef0 ++ ++ .end diff --git a/gas/testsuite/gas/h8300/t11_logs.exp b/gas/testsuite/gas/h8300/t11_logs.exp new file mode 100644 -index 0000000..fb07b2d +index 0000000..ff62a6a --- /dev/null +++ b/gas/testsuite/gas/h8300/t11_logs.exp -@@ -0,0 +1,3190 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,3189 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1184528,1194 +1191699,1193 @@ index 0000000..fb07b2d + diff --git a/gas/testsuite/gas/h8300/t11_logs.s b/gas/testsuite/gas/h8300/t11_logs.s new file mode 100644 -index 0000000..4fbba18 +index 0000000..66a9a5a --- /dev/null +++ b/gas/testsuite/gas/h8300/t11_logs.s @@ -0,0 +1,1176 @@ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+;log_sft -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ .h8300sx -+ .text -+_start: -+ not.b r1h ;1701 -+ not.b @er1 ;7d101700 -+ not.b @(0x3:2,er1) ;017768181700 -+ not.b @er1+ ;01746c181700 -+ not.b @-er1 ;01776c181700 -+ not.b @+er1 ;01756c181700 -+ not.b @er1- ;01766c181700 -+ not.b @(0x1234:16,er1) ;01746e1812341700 -+ not.b @(0x12345678:32,er1) ;78146a28123456781700 -+ not.b @(0x1234:16,r2l.b) ;01756e2812341700 -+ not.b @(0x1234:16,r2.w) ;01766e2812341700 -+ not.b @(0x1234:16,er2.l) ;01776e2812341700 -+ not.b @(0x12345678:32,r2l.b) ;78256a28123456781700 -+ not.b @(0x12345678:32,r2.w) ;78266a28123456781700 -+ not.b @(0x12345678:32,er2.l) ;78276a28123456781700 -+ not.b @0xffffff12:8 ;7f121700 -+ not.b @0x1234:16 ;6a1812341700 -+ not.b @0x12345678:32 ;6a38123456781700 -+ -+ not.w r1 ;1711 -+ not.w @er1 ;7d901710 -+ not.w @(0x6:2,er1) ;015769181710 -+ not.w @er1+ ;01546d181710 -+ not.w @-er1 ;01576d181710 -+ not.w @+er1 ;01556d181710 -+ not.w @er1- ;01566d181710 -+ not.w @(0x1234:16,er1) ;01546f1812341710 -+ not.w @(0x12345678:32,er1) ;78146b28123456781710 -+ not.w @(0x1234:16,r2l.b) ;01556f2812341710 -+ not.w @(0x1234:16,r2.w) ;01566f2812341710 -+ not.w @(0x1234:16,er2.l) ;01576f2812341710 -+ not.w @(0x12345678:32,r2l.b) ;78256b28123456781710 -+ not.w @(0x12345678:32,r2.w) ;78266b28123456781710 -+ not.w @(0x12345678:32,er2.l) ;78276b28123456781710 -+ not.w @0x1234:16 ;6b1812341710 -+ not.w @0x12345678:32 ;6b38123456781710 -+ -+ not.l er1 ;1731 -+ not.l @er1 ;010469181730 -+ not.l @(0xc:2,er1) ;010769181730 -+ not.l @er1+ ;01046d181730 -+ not.l @-er1 ;01076d181730 -+ not.l @+er1 ;01056d181730 -+ not.l @er1- ;01066d181730 -+ not.l @(0x1234:16,er1) ;01046f1812341730 -+ not.l @(0x12345678:32,er1) ;78946b28123456781730 -+ not.l @(0x1234:16,r2l.b) ;01056f2812341730 -+ not.l @(0x1234:16,r2.w) ;01066f2812341730 -+ not.l @(0x1234:16,er2.l) ;01076f2812341730 -+ not.l @(0x12345678:32,r2l.b) ;78a56b28123456781730 -+ not.l @(0x12345678:32,r2.w) ;78a66b28123456781730 -+ not.l @(0x12345678:32,er2.l) ;78a76b28123456781730 -+ not.l @0x1234:16 ;01046b0812341730 -+ not.l @0x12345678:32 ;01046b28123456781730 -+ -+ shll.b r1h ;1001 -+ shll.b @er1 ;7d101000 -+ shll.b @(0x3:2,er1) ;017768181000 -+ shll.b @er1+ ;01746c181000 -+ shll.b @-er1 ;01776c181000 -+ shll.b @+er1 ;01756c181000 -+ shll.b @er1- ;01766c181000 -+ shll.b @(0x1234:16,er1) ;01746e1812341000 -+ shll.b @(0x12345678:32,er1) ;78146a28123456781000 -+ shll.b @(0x1234:16,r2l.b) ;01756e2812341000 -+ shll.b @(0x1234:16,r2.w) ;01766e2812341000 -+ shll.b @(0x1234:16,er2.l) ;01776e2812341000 -+ shll.b @(0x12345678:32,r2l.b) ;78256a28123456781000 -+ shll.b @(0x12345678:32,r2.w) ;78266a28123456781000 -+ shll.b @(0x12345678:32,er2.l) ;78276a28123456781000 -+ shll.b @0xffffff12:8 ;7f121000 -+ shll.b @0x1234:16 ;6a1812341000 -+ shll.b @0x12345678:32 ;6a38123456781000 -+ -+ shll.w r1 ;1011 -+ shll.w @er1 ;7d901010 -+ shll.w @(0x6:2,er1) ;015769181010 -+ shll.w @er1+ ;01546d181010 -+ shll.w @-er1 ;01576d181010 -+ shll.w @+er1 ;01556d181010 -+ shll.w @er1- ;01566d181010 -+ shll.w @(0x1234:16,er1) ;01546f1812341010 -+ shll.w @(0x12345678:32,er1) ;78146b28123456781010 -+ shll.w @(0x1234:16,r2l.b) ;01556f2812341010 -+ shll.w @(0x1234:16,r2.w) ;01566f2812341010 -+ shll.w @(0x1234:16,er2.l) ;01576f2812341010 -+ shll.w @(0x12345678:32,r2l.b) ;78256b28123456781010 -+ shll.w @(0x12345678:32,r2.w) ;78266b28123456781010 -+ shll.w @(0x12345678:32,er2.l) ;78276b28123456781010 -+ shll.w @0x1234:16 ;6b1812341010 -+ shll.w @0x12345678:32 ;6b38123456781010 -+ -+ shll.l er1 ;1031 -+ shll.l @er1 ;010469181030 -+ shll.l @(0xc:2,er1) ;010769181030 -+ shll.l @er1+ ;01046d181030 -+ shll.l @-er1 ;01076d181030 -+ shll.l @+er1 ;01056d181030 -+ shll.l @er1- ;01066d181030 -+ shll.l @(0x1234:16,er1) ;01046f1812341030 -+ shll.l @(0x12345678:32,er1) ;78946b28123456781030 -+ shll.l @(0x1234:16,r2l.b) ;01056f2812341030 -+ shll.l @(0x1234:16,r2.w) ;01066f2812341030 -+ shll.l @(0x1234:16,er2.l) ;01076f2812341030 -+ shll.l @(0x12345678:32,r2l.b) ;78a56b28123456781030 -+ shll.l @(0x12345678:32,r2.w) ;78a66b28123456781030 -+ shll.l @(0x12345678:32,er2.l) ;78a76b28123456781030 -+ shll.l @0x1234:16 ;01046b0812341030 -+ shll.l @0x12345678:32 ;01046b28123456781030 -+ -+ shll.b #2,r1h ;1041 -+ shll.b #2,@er1 ;7d101040 -+ shll.b #2,@(0x3:2,er1) ;017768181040 -+ shll.b #2,@er1+ ;01746c181040 -+ shll.b #2,@-er1 ;01776c181040 -+ shll.b #2,@+er1 ;01756c181040 -+ shll.b #2,@er1- ;01766c181040 -+ shll.b #2,@(0x1234:16,er1) ;01746e1812341040 -+ shll.b #2,@(0x12345678:32,er1) ;78146a28123456781040 -+ shll.b #2,@(0x1234:16,r2l.b) ;01756e2812341040 -+ shll.b #2,@(0x1234:16,r2.w) ;01766e2812341040 -+ shll.b #2,@(0x1234:16,er2.l) ;01776e2812341040 -+ shll.b #2,@(0x12345678:32,r2l.b) ;78256a28123456781040 -+ shll.b #2,@(0x12345678:32,r2.w) ;78266a28123456781040 -+ shll.b #2,@(0x12345678:32,er2.l) ;78276a28123456781040 -+ shll.b #2,@0xffffff12:8 ;7f121040 -+ shll.b #2,@0x1234:16 ;6a1812341040 -+ shll.b #2,@0x12345678:32 ;6a38123456781040 -+ -+ shll.w #2,r1 ;1051 -+ shll.w #2,@er1 ;7d901050 -+ shll.w #2,@(0x6:2,er1) ;015769181050 -+ shll.w #2,@er1+ ;01546d181050 -+ shll.w #2,@-er1 ;01576d181050 -+ shll.w #2,@+er1 ;01556d181050 -+ shll.w #2,@er1- ;01566d181050 -+ shll.w #2,@(0x1234:16,er1) ;01546f1812341050 -+ shll.w #2,@(0x12345678:32,er1) ;78146b28123456781050 -+ shll.w #2,@(0x1234:16,r2l.b) ;01556f2812341050 -+ shll.w #2,@(0x1234:16,r2.w) ;01566f2812341050 -+ shll.w #2,@(0x1234:16,er2.l) ;01576f2812341050 -+ shll.w #2,@(0x12345678:32,r2l.b) ;78256b28123456781050 -+ shll.w #2,@(0x12345678:32,r2.w) ;78266b28123456781050 -+ shll.w #2,@(0x12345678:32,er2.l) ;78276b28123456781050 -+ shll.w #2,@0x1234:16 ;6b1812341050 -+ shll.w #2,@0x12345678:32 ;6b38123456781050 -+ -+ shll.l #2,er1 ;1071 -+ shll.l #2,@er1 ;010469181070 -+ shll.l #2,@(0xc:2,er1) ;010769181070 -+ shll.l #2,@er1+ ;01046d181070 -+ shll.l #2,@-er1 ;01076d181070 -+ shll.l #2,@+er1 ;01056d181070 -+ shll.l #2,@er1- ;01066d181070 -+ shll.l #2,@(0x1234:16,er1) ;01046f1812341070 -+ shll.l #2,@(0x12345678:32,er1) ;78946b28123456781070 -+ shll.l #2,@(0x1234:16,r2l.b) ;01056f2812341070 -+ shll.l #2,@(0x1234:16,r2.w) ;01066f2812341070 -+ shll.l #2,@(0x1234:16,er2.l) ;01076f2812341070 -+ shll.l #2,@(0x12345678:32,r2l.b) ;78a56b28123456781070 -+ shll.l #2,@(0x12345678:32,r2.w) ;78a66b28123456781070 -+ shll.l #2,@(0x12345678:32,er2.l) ;78a76b28123456781070 -+ shll.l #2,@0x1234:16 ;01046b0812341070 -+ shll.l #2,@0x12345678:32 ;01046b28123456781070 -+ -+ shll.b #4,r1h ;10a1 -+ shll.b #4,@er1 ;7d1010a0 -+ shll.b #4,@(0x3:2,er1) ;0177681810a0 -+ shll.b #4,@er1+ ;01746c1810a0 -+ shll.b #4,@-er1 ;01776c1810a0 -+ shll.b #4,@+er1 ;01756c1810a0 -+ shll.b #4,@er1- ;01766c1810a0 -+ shll.b #4,@(0x1234:16,er1) ;01746e18123410a0 -+ shll.b #4,@(0x12345678:32,er1) ;78146a281234567810a0 -+ shll.b #4,@(0x1234:16,r2l.b) ;01756e28123410a0 -+ shll.b #4,@(0x1234:16,r2.w) ;01766e28123410a0 -+ shll.b #4,@(0x1234:16,er2.l) ;01776e28123410a0 -+ shll.b #4,@(0x12345678:32,r2l.b) ;78256a281234567810a0 -+ shll.b #4,@(0x12345678:32,r2.w) ;78266a281234567810a0 -+ shll.b #4,@(0x12345678:32,er2.l) ;78276a281234567810a0 -+ shll.b #4,@0xffffff12:8 ;7f1210a0 -+ shll.b #4,@0x1234:16 ;6a18123410a0 -+ shll.b #4,@0x12345678:32 ;6a381234567810a0 -+ -+ shll.w #4,r1 ;1021 -+ shll.w #4,@er1 ;7d901020 -+ shll.w #4,@(0x6:2,er1) ;015769181020 -+ shll.w #4,@er1+ ;01546d181020 -+ shll.w #4,@-er1 ;01576d181020 -+ shll.w #4,@+er1 ;01556d181020 -+ shll.w #4,@er1- ;01566d181020 -+ shll.w #4,@(0x1234:16,er1) ;01546f1812341020 -+ shll.w #4,@(0x12345678:32,er1) ;78146b28123456781020 -+ shll.w #4,@(0x1234:16,r2l.b) ;01556f2812341020 -+ shll.w #4,@(0x1234:16,r2.w) ;01566f2812341020 -+ shll.w #4,@(0x1234:16,er2.l) ;01576f2812341020 -+ shll.w #4,@(0x12345678:32,r2l.b) ;78256b28123456781020 -+ shll.w #4,@(0x12345678:32,r2.w) ;78266b28123456781020 -+ shll.w #4,@(0x12345678:32,er2.l) ;78276b28123456781020 -+ shll.w #4,@0x1234:16 ;6b1812341020 -+ shll.w #4,@0x12345678:32 ;6b38123456781020 -+ -+ shll.l #4,er1 ;1039 -+ shll.l #4,@er1 ;010469181038 -+ shll.l #4,@(0xc:2,er1) ;010769181038 -+ shll.l #4,@er1+ ;01046d181038 -+ shll.l #4,@-er1 ;01076d181038 -+ shll.l #4,@+er1 ;01056d181038 -+ shll.l #4,@er1- ;01066d181038 -+ shll.l #4,@(0x1234:16,er1) ;01046f1812341038 -+ shll.l #4,@(0x12345678:32,er1) ;78946b28123456781038 -+ shll.l #4,@(0x1234:16,r2l.b) ;01056f2812341038 -+ shll.l #4,@(0x1234:16,r2.w) ;01066f2812341038 -+ shll.l #4,@(0x1234:16,er2.l) ;01076f2812341038 -+ shll.l #4,@(0x12345678:32,r2l.b) ;78a56b28123456781038 -+ shll.l #4,@(0x12345678:32,r2.w) ;78a66b28123456781038 -+ shll.l #4,@(0x12345678:32,er2.l) ;78a76b28123456781038 -+ shll.l #4,@0x1234:16 ;01046b0812341038 -+ shll.l #4,@0x12345678:32 ;01046b28123456781038 -+ -+ shll.w #8,r1 ;1061 -+ shll.w #8,@er1 ;7d901060 -+ shll.w #8,@(0x6:2,er1) ;015769181060 -+ shll.w #8,@er1+ ;01546d181060 -+ shll.w #8,@-er1 ;01576d181060 -+ shll.w #8,@+er1 ;01556d181060 -+ shll.w #8,@er1- ;01566d181060 -+ shll.w #8,@(0x1234:16,er1) ;01546f1812341060 -+ shll.w #8,@(0x12345678:32,er1) ;78146b28123456781060 -+ shll.w #8,@(0x1234:16,r2l.b) ;01556f2812341060 -+ shll.w #8,@(0x1234:16,r2.w) ;01566f2812341060 -+ shll.w #8,@(0x1234:16,er2.l) ;01576f2812341060 -+ shll.w #8,@(0x12345678:32,r2l.b) ;78256b28123456781060 -+ shll.w #8,@(0x12345678:32,r2.w) ;78266b28123456781060 -+ shll.w #8,@(0x12345678:32,er2.l) ;78276b28123456781060 -+ shll.w #8,@0x1234:16 ;6b1812341060 -+ shll.w #8,@0x12345678:32 ;6b38123456781060 -+ -+ shll.l #8,er1 ;1079 -+ shll.l #8,@er1 ;010469181078 -+ shll.l #8,@(0xc:2,er1) ;010769181078 -+ shll.l #8,@er1+ ;01046d181078 -+ shll.l #8,@-er1 ;01076d181078 -+ shll.l #8,@+er1 ;01056d181078 -+ shll.l #8,@er1- ;01066d181078 -+ shll.l #8,@(0x1234:16,er1) ;01046f1812341078 -+ shll.l #8,@(0x12345678:32,er1) ;78946b28123456781078 -+ shll.l #8,@(0x1234:16,r2l.b) ;01056f2812341078 -+ shll.l #8,@(0x1234:16,r2.w) ;01066f2812341078 -+ shll.l #8,@(0x1234:16,er2.l) ;01076f2812341078 -+ shll.l #8,@(0x12345678:32,r2l.b) ;78a56b28123456781078 -+ shll.l #8,@(0x12345678:32,r2.w) ;78a66b28123456781078 -+ shll.l #8,@(0x12345678:32,er2.l) ;78a76b28123456781078 -+ shll.l #8,@0x1234:16 ;01046b0812341078 -+ shll.l #8,@0x12345678:32 ;01046b28123456781078 -+ -+ shll.l #16,er1 ;10f9 -+ shll.l #16,@er1 ;0104691810f8 -+ shll.l #16,@(0xc:2,er1) ;0107691810f8 -+ shll.l #16,@er1+ ;01046d1810f8 -+ shll.l #16,@-er1 ;01076d1810f8 -+ shll.l #16,@+er1 ;01056d1810f8 -+ shll.l #16,@er1- ;01066d1810f8 -+ shll.l #16,@(0x1234:16,er1) ;01046f18123410f8 -+ shll.l #16,@(0x12345678:32,er1) ;78946b281234567810f8 -+ shll.l #16,@(0x1234:16,r2l.b) ;01056f28123410f8 -+ shll.l #16,@(0x1234:16,r2.w) ;01066f28123410f8 -+ shll.l #16,@(0x1234:16,er2.l) ;01076f28123410f8 -+ shll.l #16,@(0x12345678:32,r2l.b) ;78a56b281234567810f8 -+ shll.l #16,@(0x12345678:32,r2.w) ;78a66b281234567810f8 -+ shll.l #16,@(0x12345678:32,er2.l) ;78a76b281234567810f8 -+ shll.l #16,@0x1234:16 ;01046b08123410f8 -+ shll.l #16,@0x12345678:32 ;01046b281234567810f8 -+ -+ shll.b #0x7:5,r1h ;03871001 -+ shll.w #0xf:5,r1 ;038f1011 -+ shll.l #0x1f:5,er1 ;039f1031 -+ -+ shll.b r3h,r1h ;78381001 -+ shll.w r3h,r1 ;78381011 -+ shll.l r3h,er1 ;78381031 -+ -+ shlr.b r1h ;1101 -+ shlr.b @er1 ;7d101100 -+ shlr.b @(0x3:2,er1) ;017768181100 -+ shlr.b @er1+ ;01746c181100 -+ shlr.b @-er1 ;01776c181100 -+ shlr.b @+er1 ;01756c181100 -+ shlr.b @er1- ;01766c181100 -+ shlr.b @(0x1234:16,er1) ;01746e1812341100 -+ shlr.b @(0x12345678:32,er1) ;78146a28123456781100 -+ shlr.b @(0x1234:16,r2l.b) ;01756e2812341100 -+ shlr.b @(0x1234:16,r2.w) ;01766e2812341100 -+ shlr.b @(0x1234:16,er2.l) ;01776e2812341100 -+ shlr.b @(0x12345678:32,r2l.b) ;78256a28123456781100 -+ shlr.b @(0x12345678:32,r2.w) ;78266a28123456781100 -+ shlr.b @(0x12345678:32,er2.l) ;78276a28123456781100 -+ shlr.b @0xffffff12:8 ;7f121100 -+ shlr.b @0x1234:16 ;6a1812341100 -+ shlr.b @0x12345678:32 ;6a38123456781100 -+ -+ shlr.w r1 ;1111 -+ shlr.w @er1 ;7d901110 -+ shlr.w @(0x6:2,er1) ;015769181110 -+ shlr.w @er1+ ;01546d181110 -+ shlr.w @-er1 ;01576d181110 -+ shlr.w @+er1 ;01556d181110 -+ shlr.w @er1- ;01566d181110 -+ shlr.w @(0x1234:16,er1) ;01546f1812341110 -+ shlr.w @(0x12345678:32,er1) ;78146b28123456781110 -+ shlr.w @(0x1234:16,r2l.b) ;01556f2812341110 -+ shlr.w @(0x1234:16,r2.w) ;01566f2812341110 -+ shlr.w @(0x1234:16,er2.l) ;01576f2812341110 -+ shlr.w @(0x12345678:32,r2l.b) ;78256b28123456781110 -+ shlr.w @(0x12345678:32,r2.w) ;78266b28123456781110 -+ shlr.w @(0x12345678:32,er2.l) ;78276b28123456781110 -+ shlr.w @0x1234:16 ;6b1812341110 -+ shlr.w @0x12345678:32 ;6b38123456781110 -+ -+ shlr.l er1 ;1131 -+ shlr.l @er1 ;010469181130 -+ shlr.l @(0xc:2,er1) ;010769181130 -+ shlr.l @er1+ ;01046d181130 -+ shlr.l @-er1 ;01076d181130 -+ shlr.l @+er1 ;01056d181130 -+ shlr.l @er1- ;01066d181130 -+ shlr.l @(0x1234:16,er1) ;01046f1812341130 -+ shlr.l @(0x12345678:32,er1) ;78946b28123456781130 -+ shlr.l @(0x1234:16,r2l.b) ;01056f2812341130 -+ shlr.l @(0x1234:16,r2.w) ;01066f2812341130 -+ shlr.l @(0x1234:16,er2.l) ;01076f2812341130 -+ shlr.l @(0x12345678:32,r2l.b) ;78a56b28123456781130 -+ shlr.l @(0x12345678:32,r2.w) ;78a66b28123456781130 -+ shlr.l @(0x12345678:32,er2.l) ;78a76b28123456781130 -+ shlr.l @0x1234:16 ;01046b0812341130 -+ shlr.l @0x12345678:32 ;01046b28123456781130 -+ -+ shlr.b #2,r1h ;1141 -+ shlr.b #2,@er1 ;7d101140 -+ shlr.b #2,@(0x3:2,er1) ;017768181140 -+ shlr.b #2,@er1+ ;01746c181140 -+ shlr.b #2,@-er1 ;01776c181140 -+ shlr.b #2,@+er1 ;01756c181140 -+ shlr.b #2,@er1- ;01766c181140 -+ shlr.b #2,@(0x1234:16,er1) ;01746e1812341140 -+ shlr.b #2,@(0x12345678:32,er1) ;78146a28123456781140 -+ shlr.b #2,@(0x1234:16,r2l.b) ;01756e2812341140 -+ shlr.b #2,@(0x1234:16,r2.w) ;01766e2812341140 -+ shlr.b #2,@(0x1234:16,er2.l) ;01776e2812341140 -+ shlr.b #2,@(0x12345678:32,r2l.b) ;78256a28123456781140 -+ shlr.b #2,@(0x12345678:32,r2.w) ;78266a28123456781140 -+ shlr.b #2,@(0x12345678:32,er2.l) ;78276a28123456781140 -+ shlr.b #2,@0xffffff12:8 ;7f121140 -+ shlr.b #2,@0x1234:16 ;6a1812341140 -+ shlr.b #2,@0x12345678:32 ;6a38123456781140 -+ -+ shlr.w #2,r1 ;1151 -+ shlr.w #2,@er1 ;7d901150 -+ shlr.w #2,@(0x6:2,er1) ;015769181150 -+ shlr.w #2,@er1+ ;01546d181150 -+ shlr.w #2,@-er1 ;01576d181150 -+ shlr.w #2,@+er1 ;01556d181150 -+ shlr.w #2,@er1- ;01566d181150 -+ shlr.w #2,@(0x1234:16,er1) ;01546f1812341150 -+ shlr.w #2,@(0x12345678:32,er1) ;78146b28123456781150 -+ shlr.w #2,@(0x1234:16,r2l.b) ;01556f2812341150 -+ shlr.w #2,@(0x1234:16,r2.w) ;01566f2812341150 -+ shlr.w #2,@(0x1234:16,er2.l) ;01576f2812341150 -+ shlr.w #2,@(0x12345678:32,r2l.b) ;78256b28123456781150 -+ shlr.w #2,@(0x12345678:32,r2.w) ;78266b28123456781150 -+ shlr.w #2,@(0x12345678:32,er2.l) ;78276b28123456781150 -+ shlr.w #2,@0x1234:16 ;6b1812341150 -+ shlr.w #2,@0x12345678:32 ;6b38123456781150 -+ -+ shlr.l #2,er1 ;1171 -+ shlr.l #2,@er1 ;010469181170 -+ shlr.l #2,@(0xc:2,er1) ;010769181170 -+ shlr.l #2,@er1+ ;01046d181170 -+ shlr.l #2,@-er1 ;01076d181170 -+ shlr.l #2,@+er1 ;01056d181170 -+ shlr.l #2,@er1- ;01066d181170 -+ shlr.l #2,@(0x1234:16,er1) ;01046f1812341170 -+ shlr.l #2,@(0x12345678:32,er1) ;78946b28123456781170 -+ shlr.l #2,@(0x1234:16,r2l.b) ;01056f2812341170 -+ shlr.l #2,@(0x1234:16,r2.w) ;01066f2812341170 -+ shlr.l #2,@(0x1234:16,er2.l) ;01076f2812341170 -+ shlr.l #2,@(0x12345678:32,r2l.b) ;78a56b28123456781170 -+ shlr.l #2,@(0x12345678:32,r2.w) ;78a66b28123456781170 -+ shlr.l #2,@(0x12345678:32,er2.l) ;78a76b28123456781170 -+ shlr.l #2,@0x1234:16 ;01046b0812341170 -+ shlr.l #2,@0x12345678:32 ;01046b28123456781170 -+ -+ shlr.b #4,r1h ;11a1 -+ shlr.b #4,@er1 ;7d1011a0 -+ shlr.b #4,@(0x3:2,er1) ;0177681811a0 -+ shlr.b #4,@er1+ ;01746c1811a0 -+ shlr.b #4,@-er1 ;01776c1811a0 -+ shlr.b #4,@+er1 ;01756c1811a0 -+ shlr.b #4,@er1- ;01766c1811a0 -+ shlr.b #4,@(0x1234:16,er1) ;01746e18123411a0 -+ shlr.b #4,@(0x12345678:32,er1) ;78146a281234567811a0 -+ shlr.b #4,@(0x1234:16,r2l.b) ;01756e28123411a0 -+ shlr.b #4,@(0x1234:16,r2.w) ;01766e28123411a0 -+ shlr.b #4,@(0x1234:16,er2.l) ;01776e28123411a0 -+ shlr.b #4,@(0x12345678:32,r2l.b) ;78256a281234567811a0 -+ shlr.b #4,@(0x12345678:32,r2.w) ;78266a281234567811a0 -+ shlr.b #4,@(0x12345678:32,er2.l) ;78276a281234567811a0 -+ shlr.b #4,@0xffffff12:8 ;7f1211a0 -+ shlr.b #4,@0x1234:16 ;6a18123411a0 -+ shlr.b #4,@0x12345678:32 ;6a381234567811a0 -+ -+ shlr.w #4,r1 ;1121 -+ shlr.w #4,@er1 ;7d901120 -+ shlr.w #4,@(0x6:2,er1) ;015769181120 -+ shlr.w #4,@er1+ ;01546d181120 -+ shlr.w #4,@-er1 ;01576d181120 -+ shlr.w #4,@+er1 ;01556d181120 -+ shlr.w #4,@er1- ;01566d181120 -+ shlr.w #4,@(0x1234:16,er1) ;01546f1812341120 -+ shlr.w #4,@(0x12345678:32,er1) ;78146b28123456781120 -+ shlr.w #4,@(0x1234:16,r2l.b) ;01556f2812341120 -+ shlr.w #4,@(0x1234:16,r2.w) ;01566f2812341120 -+ shlr.w #4,@(0x1234:16,er2.l) ;01576f2812341120 -+ shlr.w #4,@(0x12345678:32,r2l.b) ;78256b28123456781120 -+ shlr.w #4,@(0x12345678:32,r2.w) ;78266b28123456781120 -+ shlr.w #4,@(0x12345678:32,er2.l) ;78276b28123456781120 -+ shlr.w #4,@0x1234:16 ;6b1812341120 -+ shlr.w #4,@0x12345678:32 ;6b38123456781120 -+ -+ shlr.l #4,er1 ;1139 -+ shlr.l #4,@er1 ;010469181138 -+ shlr.l #4,@(0xc:2,er1) ;010769181138 -+ shlr.l #4,@er1+ ;01046d181138 -+ shlr.l #4,@-er1 ;01076d181138 -+ shlr.l #4,@+er1 ;01056d181138 -+ shlr.l #4,@er1- ;01066d181138 -+ shlr.l #4,@(0x1234:16,er1) ;01046f1812341138 -+ shlr.l #4,@(0x12345678:32,er1) ;78946b28123456781138 -+ shlr.l #4,@(0x1234:16,r2l.b) ;01056f2812341138 -+ shlr.l #4,@(0x1234:16,r2.w) ;01066f2812341138 -+ shlr.l #4,@(0x1234:16,er2.l) ;01076f2812341138 -+ shlr.l #4,@(0x12345678:32,r2l.b) ;78a56b28123456781138 -+ shlr.l #4,@(0x12345678:32,r2.w) ;78a66b28123456781138 -+ shlr.l #4,@(0x12345678:32,er2.l) ;78a76b28123456781138 -+ shlr.l #4,@0x1234:16 ;01046b0812341138 -+ shlr.l #4,@0x12345678:32 ;01046b28123456781138 -+ -+ shlr.w #8,r1 ;1161 -+ shlr.w #8,@er1 ;7d901160 -+ shlr.w #8,@(0x6:2,er1) ;015769181160 -+ shlr.w #8,@er1+ ;01546d181160 -+ shlr.w #8,@-er1 ;01576d181160 -+ shlr.w #8,@+er1 ;01556d181160 -+ shlr.w #8,@er1- ;01566d181160 -+ shlr.w #8,@(0x1234:16,er1) ;01546f1812341160 -+ shlr.w #8,@(0x12345678:32,er1) ;78146b28123456781160 -+ shlr.w #8,@(0x1234:16,r2l.b) ;01556f2812341160 -+ shlr.w #8,@(0x1234:16,r2.w) ;01566f2812341160 -+ shlr.w #8,@(0x1234:16,er2.l) ;01576f2812341160 -+ shlr.w #8,@(0x12345678:32,r2l.b) ;78256b28123456781160 -+ shlr.w #8,@(0x12345678:32,r2.w) ;78266b28123456781160 -+ shlr.w #8,@(0x12345678:32,er2.l) ;78276b28123456781160 -+ shlr.w #8,@0x1234:16 ;6b1812341160 -+ shlr.w #8,@0x12345678:32 ;6b38123456781160 -+ -+ shlr.l #8,er1 ;1179 -+ shlr.l #8,@er1 ;010469181178 -+ shlr.l #8,@(0xc:2,er1) ;010769181178 -+ shlr.l #8,@er1+ ;01046d181178 -+ shlr.l #8,@-er1 ;01076d181178 -+ shlr.l #8,@+er1 ;01056d181178 -+ shlr.l #8,@er1- ;01066d181178 -+ shlr.l #8,@(0x1234:16,er1) ;01046f1812341178 -+ shlr.l #8,@(0x12345678:32,er1) ;78946b28123456781178 -+ shlr.l #8,@(0x1234:16,r2l.b) ;01056f2812341178 -+ shlr.l #8,@(0x1234:16,r2.w) ;01066f2812341178 -+ shlr.l #8,@(0x1234:16,er2.l) ;01076f2812341178 -+ shlr.l #8,@(0x12345678:32,r2l.b) ;78a56b28123456781178 -+ shlr.l #8,@(0x12345678:32,r2.w) ;78a66b28123456781178 -+ shlr.l #8,@(0x12345678:32,er2.l) ;78a76b28123456781178 -+ shlr.l #8,@0x1234:16 ;01046b0812341178 -+ shlr.l #8,@0x12345678:32 ;01046b28123456781178 -+ -+ shlr.l #16,er1 ;11f9 -+ shlr.l #16,@er1 ;0104691811f8 -+ shlr.l #16,@(0xc:2,er1) ;0107691811f8 -+ shlr.l #16,@er1+ ;01046d1811f8 -+ shlr.l #16,@-er1 ;01076d1811f8 -+ shlr.l #16,@+er1 ;01056d1811f8 -+ shlr.l #16,@er1- ;01066d1811f8 -+ shlr.l #16,@(0x1234:16,er1) ;01046f18123411f8 -+ shlr.l #16,@(0x12345678:32,er1) ;78946b281234567811f8 -+ shlr.l #16,@(0x1234:16,r2l.b) ;01056f28123411f8 -+ shlr.l #16,@(0x1234:16,r2.w) ;01066f28123411f8 -+ shlr.l #16,@(0x1234:16,er2.l) ;01076f28123411f8 -+ shlr.l #16,@(0x12345678:32,r2l.b) ;78a56b281234567811f8 -+ shlr.l #16,@(0x12345678:32,r2.w) ;78a66b281234567811f8 -+ shlr.l #16,@(0x12345678:32,er2.l) ;78a76b281234567811f8 -+ shlr.l #16,@0x1234:16 ;01046b08123411f8 -+ shlr.l #16,@0x12345678:32 ;01046b281234567811f8 -+ -+ shlr.b #0x7:5,r1h ;03871101 -+ shlr.w #0xf:5,r1 ;038f1111 -+ shlr.l #0x1f:5,er1 ;039f1131 -+ -+ shlr.b r3h,r1h ;78381101 -+ shlr.w r3h,r1 ;78381111 -+ shlr.l r3h,er1 ;78381131 -+ -+ shal.b r1h ;1081 -+ shal.b @er1 ;7d101080 -+ shal.b @(0x3:2,er1) ;017768181080 -+ shal.b @er1+ ;01746c181080 -+ shal.b @-er1 ;01776c181080 -+ shal.b @+er1 ;01756c181080 -+ shal.b @er1- ;01766c181080 -+ shal.b @(0x1234:16,er1) ;01746e1812341080 -+ shal.b @(0x12345678:32,er1) ;78146a28123456781080 -+ shal.b @(0x1234:16,r2l.b) ;01756e2812341080 -+ shal.b @(0x1234:16,r2.w) ;01766e2812341080 -+ shal.b @(0x1234:16,er2.l) ;01776e2812341080 -+ shal.b @(0x12345678:32,r2l.b) ;78256a28123456781080 -+ shal.b @(0x12345678:32,r2.w) ;78266a28123456781080 -+ shal.b @(0x12345678:32,er2.l) ;78276a28123456781080 -+ shal.b @0xffffff12:8 ;7f121080 -+ shal.b @0x1234:16 ;6a1812341080 -+ shal.b @0x12345678:32 ;6a38123456781080 -+ -+ shal.w r1 ;1091 -+ shal.w @er1 ;7d901090 -+ shal.w @(0x6:2,er1) ;015769181090 -+ shal.w @er1+ ;01546d181090 -+ shal.w @-er1 ;01576d181090 -+ shal.w @+er1 ;01556d181090 -+ shal.w @er1- ;01566d181090 -+ shal.w @(0x1234:16,er1) ;01546f1812341090 -+ shal.w @(0x12345678:32,er1) ;78146b28123456781090 -+ shal.w @(0x1234:16,r2l.b) ;01556f2812341090 -+ shal.w @(0x1234:16,r2.w) ;01566f2812341090 -+ shal.w @(0x1234:16,er2.l) ;01576f2812341090 -+ shal.w @(0x12345678:32,r2l.b) ;78256b28123456781090 -+ shal.w @(0x12345678:32,r2.w) ;78266b28123456781090 -+ shal.w @(0x12345678:32,er2.l) ;78276b28123456781090 -+ shal.w @0x1234:16 ;6b1812341090 -+ shal.w @0x12345678:32 ;6b38123456781090 -+ -+ shal.l er1 ;10b1 -+ shal.l @er1 ;0104691810b0 -+ shal.l @(0xc:2,er1) ;0107691810b0 -+ shal.l @er1+ ;01046d1810b0 -+ shal.l @-er1 ;01076d1810b0 -+ shal.l @+er1 ;01056d1810b0 -+ shal.l @er1- ;01066d1810b0 -+ shal.l @(0x1234:16,er1) ;01046f18123410b0 -+ shal.l @(0x12345678:32,er1) ;78946b281234567810b0 -+ shal.l @(0x1234:16,r2l.b) ;01056f28123410b0 -+ shal.l @(0x1234:16,r2.w) ;01066f28123410b0 -+ shal.l @(0x1234:16,er2.l) ;01076f28123410b0 -+ shal.l @(0x12345678:32,r2l.b) ;78a56b281234567810b0 -+ shal.l @(0x12345678:32,r2.w) ;78a66b281234567810b0 -+ shal.l @(0x12345678:32,er2.l) ;78a76b281234567810b0 -+ shal.l @0x1234:16 ;01046b08123410b0 -+ shal.l @0x12345678:32 ;01046b281234567810b0 -+ -+ shal.b #2,r1h ;10c1 -+ shal.b #2,@er1 ;7d1010c0 -+ shal.b #2,@(0x3:2,er1) ;0177681810c0 -+ shal.b #2,@er1+ ;01746c1810c0 -+ shal.b #2,@-er1 ;01776c1810c0 -+ shal.b #2,@+er1 ;01756c1810c0 -+ shal.b #2,@er1- ;01766c1810c0 -+ shal.b #2,@(0x1234:16,er1) ;01746e18123410c0 -+ shal.b #2,@(0x12345678:32,er1) ;78146a281234567810c0 -+ shal.b #2,@(0x1234:16,r2l.b) ;01756e28123410c0 -+ shal.b #2,@(0x1234:16,r2.w) ;01766e28123410c0 -+ shal.b #2,@(0x1234:16,er2.l) ;01776e28123410c0 -+ shal.b #2,@(0x12345678:32,r2l.b) ;78256a281234567810c0 -+ shal.b #2,@(0x12345678:32,r2.w) ;78266a281234567810c0 -+ shal.b #2,@(0x12345678:32,er2.l) ;78276a281234567810c0 -+ shal.b #2,@0xffffff12:8 ;7f1210c0 -+ shal.b #2,@0x1234:16 ;6a18123410c0 -+ shal.b #2,@0x12345678:32 ;6a381234567810c0 -+ -+ shal.w #2,r1 ;10d1 -+ shal.w #2,@er1 ;7d9010d0 -+ shal.w #2,@(0x6:2,er1) ;0157691810d0 -+ shal.w #2,@er1+ ;01546d1810d0 -+ shal.w #2,@-er1 ;01576d1810d0 -+ shal.w #2,@+er1 ;01556d1810d0 -+ shal.w #2,@er1- ;01566d1810d0 -+ shal.w #2,@(0x1234:16,er1) ;01546f18123410d0 -+ shal.w #2,@(0x12345678:32,er1) ;78146b281234567810d0 -+ shal.w #2,@(0x1234:16,r2l.b) ;01556f28123410d0 -+ shal.w #2,@(0x1234:16,r2.w) ;01566f28123410d0 -+ shal.w #2,@(0x1234:16,er2.l) ;01576f28123410d0 -+ shal.w #2,@(0x12345678:32,r2l.b) ;78256b281234567810d0 -+ shal.w #2,@(0x12345678:32,r2.w) ;78266b281234567810d0 -+ shal.w #2,@(0x12345678:32,er2.l) ;78276b281234567810d0 -+ shal.w #2,@0x1234:16 ;6b18123410d0 -+ shal.w #2,@0x12345678:32 ;6b381234567810d0 -+ -+ shal.l #2,er1 ;10f1 -+ shal.l #2,@er1 ;0104691810f0 -+ shal.l #2,@(0xc:2,er1) ;0107691810f0 -+ shal.l #2,@er1+ ;01046d1810f0 -+ shal.l #2,@-er1 ;01076d1810f0 -+ shal.l #2,@+er1 ;01056d1810f0 -+ shal.l #2,@er1- ;01066d1810f0 -+ shal.l #2,@(0x1234:16,er1) ;01046f18123410f0 -+ shal.l #2,@(0x12345678:32,er1) ;78946b281234567810f0 -+ shal.l #2,@(0x1234:16,r2l.b) ;01056f28123410f0 -+ shal.l #2,@(0x1234:16,r2.w) ;01066f28123410f0 -+ shal.l #2,@(0x1234:16,er2.l) ;01076f28123410f0 -+ shal.l #2,@(0x12345678:32,r2l.b) ;78a56b281234567810f0 -+ shal.l #2,@(0x12345678:32,r2.w) ;78a66b281234567810f0 -+ shal.l #2,@(0x12345678:32,er2.l) ;78a76b281234567810f0 -+ shal.l #2,@0x1234:16 ;01046b08123410f0 -+ shal.l #2,@0x12345678:32 ;01046b281234567810f0 -+ -+ shar.b r1h ;1181 -+ shar.b @er1 ;7d101180 -+ shar.b @(0x3:2,er1) ;017768181180 -+ shar.b @er1+ ;01746c181180 -+ shar.b @-er1 ;01776c181180 -+ shar.b @+er1 ;01756c181180 -+ shar.b @er1- ;01766c181180 -+ shar.b @(0x1234:16,er1) ;01746e1812341180 -+ shar.b @(0x12345678:32,er1) ;78146a28123456781180 -+ shar.b @(0x1234:16,r2l.b) ;01756e2812341180 -+ shar.b @(0x1234:16,r2.w) ;01766e2812341180 -+ shar.b @(0x1234:16,er2.l) ;01776e2812341180 -+ shar.b @(0x12345678:32,r2l.b) ;78256a28123456781180 -+ shar.b @(0x12345678:32,r2.w) ;78266a28123456781180 -+ shar.b @(0x12345678:32,er2.l) ;78276a28123456781180 -+ shar.b @0xffffff12:8 ;7f121180 -+ shar.b @0x1234:16 ;6a1812341180 -+ shar.b @0x12345678:32 ;6a38123456781180 -+ -+ shar.w r1 ;1191 -+ shar.w @er1 ;7d901190 -+ shar.w @(0x6:2,er1) ;015769181190 -+ shar.w @er1+ ;01546d181190 -+ shar.w @-er1 ;01576d181190 -+ shar.w @+er1 ;01556d181190 -+ shar.w @er1- ;01566d181190 -+ shar.w @(0x1234:16,er1) ;01546f1812341190 -+ shar.w @(0x12345678:32,er1) ;78146b28123456781190 -+ shar.w @(0x1234:16,r2l.b) ;01556f2812341190 -+ shar.w @(0x1234:16,r2.w) ;01566f2812341190 -+ shar.w @(0x1234:16,er2.l) ;01576f2812341190 -+ shar.w @(0x12345678:32,r2l.b) ;78256b28123456781190 -+ shar.w @(0x12345678:32,r2.w) ;78266b28123456781190 -+ shar.w @(0x12345678:32,er2.l) ;78276b28123456781190 -+ shar.w @0x1234:16 ;6b1812341190 -+ shar.w @0x12345678:32 ;6b38123456781190 -+ -+ shar.l er1 ;11b1 -+ shar.l @er1 ;0104691811b0 -+ shar.l @(0xc:2,er1) ;0107691811b0 -+ shar.l @er1+ ;01046d1811b0 -+ shar.l @-er1 ;01076d1811b0 -+ shar.l @+er1 ;01056d1811b0 -+ shar.l @er1- ;01066d1811b0 -+ shar.l @(0x1234:16,er1) ;01046f18123411b0 -+ shar.l @(0x12345678:32,er1) ;78946b281234567811b0 -+ shar.l @(0x1234:16,r2l.b) ;01056f28123411b0 -+ shar.l @(0x1234:16,r2.w) ;01066f28123411b0 -+ shar.l @(0x1234:16,er2.l) ;01076f28123411b0 -+ shar.l @(0x12345678:32,r2l.b) ;78a56b281234567811b0 -+ shar.l @(0x12345678:32,r2.w) ;78a66b281234567811b0 -+ shar.l @(0x12345678:32,er2.l) ;78a76b281234567811b0 -+ shar.l @0x1234:16 ;01046b08123411b0 -+ shar.l @0x12345678:32 ;01046b281234567811b0 -+ -+ shar.b #2,r1h ;11c1 -+ shar.b #2,@er1 ;7d1011c0 -+ shar.b #2,@(0x3:2,er1) ;0177681811c0 -+ shar.b #2,@er1+ ;01746c1811c0 -+ shar.b #2,@-er1 ;01776c1811c0 -+ shar.b #2,@+er1 ;01756c1811c0 -+ shar.b #2,@er1- ;01766c1811c0 -+ shar.b #2,@(0x1234:16,er1) ;01746e18123411c0 -+ shar.b #2,@(0x12345678:32,er1) ;78146a281234567811c0 -+ shar.b #2,@(0x1234:16,r2l.b) ;01756e28123411c0 -+ shar.b #2,@(0x1234:16,r2.w) ;01766e28123411c0 -+ shar.b #2,@(0x1234:16,er2.l) ;01776e28123411c0 -+ shar.b #2,@(0x12345678:32,r2l.b) ;78256a281234567811c0 -+ shar.b #2,@(0x12345678:32,r2.w) ;78266a281234567811c0 -+ shar.b #2,@(0x12345678:32,er2.l) ;78276a281234567811c0 -+ shar.b #2,@0xffffff12:8 ;7f1211c0 -+ shar.b #2,@0x1234:16 ;6a18123411c0 -+ shar.b #2,@0x12345678:32 ;6a381234567811c0 -+ -+ shar.w #2,r1 ;11d1 -+ shar.w #2,@er1 ;7d9011d0 -+ shar.w #2,@(0x6:2,er1) ;0157691811d0 -+ shar.w #2,@er1+ ;01546d1811d0 -+ shar.w #2,@-er1 ;01576d1811d0 -+ shar.w #2,@+er1 ;01556d1811d0 -+ shar.w #2,@er1- ;01566d1811d0 -+ shar.w #2,@(0x1234:16,er1) ;01546f18123411d0 -+ shar.w #2,@(0x12345678:32,er1) ;78146b281234567811d0 -+ shar.w #2,@(0x1234:16,r2l.b) ;01556f28123411d0 -+ shar.w #2,@(0x1234:16,r2.w) ;01566f28123411d0 -+ shar.w #2,@(0x1234:16,er2.l) ;01576f28123411d0 -+ shar.w #2,@(0x12345678:32,r2l.b) ;78256b281234567811d0 -+ shar.w #2,@(0x12345678:32,r2.w) ;78266b281234567811d0 -+ shar.w #2,@(0x12345678:32,er2.l) ;78276b281234567811d0 -+ shar.w #2,@0x1234:16 ;6b18123411d0 -+ shar.w #2,@0x12345678:32 ;6b381234567811d0 -+ -+ shar.l #2,er1 ;11f1 -+ shar.l #2,@er1 ;0104691811f0 -+ shar.l #2,@(0xc:2,er1) ;0107691811f0 -+ shar.l #2,@er1+ ;01046d1811f0 -+ shar.l #2,@-er1 ;01076d1811f0 -+ shar.l #2,@+er1 ;01056d1811f0 -+ shar.l #2,@er1- ;01066d1811f0 -+ shar.l #2,@(0x1234:16,er1) ;01046f18123411f0 -+ shar.l #2,@(0x12345678:32,er1) ;78946b281234567811f0 -+ shar.l #2,@(0x1234:16,r2l.b) ;01056f28123411f0 -+ shar.l #2,@(0x1234:16,r2.w) ;01066f28123411f0 -+ shar.l #2,@(0x1234:16,er2.l) ;01076f28123411f0 -+ shar.l #2,@(0x12345678:32,r2l.b) ;78a56b281234567811f0 -+ shar.l #2,@(0x12345678:32,r2.w) ;78a66b281234567811f0 -+ shar.l #2,@(0x12345678:32,er2.l) ;78a76b281234567811f0 -+ shar.l #2,@0x1234:16 ;01046b08123411f0 -+ shar.l #2,@0x12345678:32 ;01046b281234567811f0 -+ -+ rotxl.b r1h ;1201 -+ rotxl.b @er1 ;7d101200 -+ rotxl.b @(0x3:2,er1) ;017768181200 -+ rotxl.b @er1+ ;01746c181200 -+ rotxl.b @-er1 ;01776c181200 -+ rotxl.b @+er1 ;01756c181200 -+ rotxl.b @er1- ;01766c181200 -+ rotxl.b @(0x1234:16,er1) ;01746e1812341200 -+ rotxl.b @(0x12345678:32,er1) ;78146a28123456781200 -+ rotxl.b @(0x1234:16,r2l.b) ;01756e2812341200 -+ rotxl.b @(0x1234:16,r2.w) ;01766e2812341200 -+ rotxl.b @(0x1234:16,er2.l) ;01776e2812341200 -+ rotxl.b @(0x12345678:32,r2l.b) ;78256a28123456781200 -+ rotxl.b @(0x12345678:32,r2.w) ;78266a28123456781200 -+ rotxl.b @(0x12345678:32,er2.l) ;78276a28123456781200 -+ rotxl.b @0xffffff12:8 ;7f121200 -+ rotxl.b @0x1234:16 ;6a1812341200 -+ rotxl.b @0x12345678:32 ;6a38123456781200 -+ -+ rotxl.w r1 ;1211 -+ rotxl.w @er1 ;7d901210 -+ rotxl.w @(0x6:2,er1) ;015769181210 -+ rotxl.w @er1+ ;01546d181210 -+ rotxl.w @-er1 ;01576d181210 -+ rotxl.w @+er1 ;01556d181210 -+ rotxl.w @er1- ;01566d181210 -+ rotxl.w @(0x1234:16,er1) ;01546f1812341210 -+ rotxl.w @(0x12345678:32,er1) ;78146b28123456781210 -+ rotxl.w @(0x1234:16,r2l.b) ;01556f2812341210 -+ rotxl.w @(0x1234:16,r2.w) ;01566f2812341210 -+ rotxl.w @(0x1234:16,er2.l) ;01576f2812341210 -+ rotxl.w @(0x12345678:32,r2l.b) ;78256b28123456781210 -+ rotxl.w @(0x12345678:32,r2.w) ;78266b28123456781210 -+ rotxl.w @(0x12345678:32,er2.l) ;78276b28123456781210 -+ rotxl.w @0x1234:16 ;6b1812341210 -+ rotxl.w @0x12345678:32 ;6b38123456781210 -+ -+ rotxl.l er1 ;1231 -+ rotxl.l @er1 ;010469181230 -+ rotxl.l @(0xc:2,er1) ;010769181230 -+ rotxl.l @er1+ ;01046d181230 -+ rotxl.l @-er1 ;01076d181230 -+ rotxl.l @+er1 ;01056d181230 -+ rotxl.l @er1- ;01066d181230 -+ rotxl.l @(0x1234:16,er1) ;01046f1812341230 -+ rotxl.l @(0x12345678:32,er1) ;78946b28123456781230 -+ rotxl.l @(0x1234:16,r2l.b) ;01056f2812341230 -+ rotxl.l @(0x1234:16,r2.w) ;01066f2812341230 -+ rotxl.l @(0x1234:16,er2.l) ;01076f2812341230 -+ rotxl.l @(0x12345678:32,r2l.b) ;78a56b28123456781230 -+ rotxl.l @(0x12345678:32,r2.w) ;78a66b28123456781230 -+ rotxl.l @(0x12345678:32,er2.l) ;78a76b28123456781230 -+ rotxl.l @0x1234:16 ;01046b0812341230 -+ rotxl.l @0x12345678:32 ;01046b28123456781230 -+ -+ rotxl.b #2,r1h ;1241 -+ rotxl.b #2,@er1 ;7d101240 -+ rotxl.b #2,@(0x3:2,er1) ;017768181240 -+ rotxl.b #2,@er1+ ;01746c181240 -+ rotxl.b #2,@-er1 ;01776c181240 -+ rotxl.b #2,@+er1 ;01756c181240 -+ rotxl.b #2,@er1- ;01766c181240 -+ rotxl.b #2,@(0x1234:16,er1) ;01746e1812341240 -+ rotxl.b #2,@(0x12345678:32,er1) ;78146a28123456781240 -+ rotxl.b #2,@(0x1234:16,r2l.b) ;01756e2812341240 -+ rotxl.b #2,@(0x1234:16,r2.w) ;01766e2812341240 -+ rotxl.b #2,@(0x1234:16,er2.l) ;01776e2812341240 -+ rotxl.b #2,@(0x12345678:32,r2l.b) ;78256a28123456781240 -+ rotxl.b #2,@(0x12345678:32,r2.w) ;78266a28123456781240 -+ rotxl.b #2,@(0x12345678:32,er2.l) ;78276a28123456781240 -+ rotxl.b #2,@0xffffff12:8 ;7f121240 -+ rotxl.b #2,@0x1234:16 ;6a1812341240 -+ rotxl.b #2,@0x12345678:32 ;6a38123456781240 -+ -+ rotxl.w #2,r1 ;1251 -+ rotxl.w #2,@er1 ;7d901250 -+ rotxl.w #2,@(0x6:2,er1) ;015769181250 -+ rotxl.w #2,@er1+ ;01546d181250 -+ rotxl.w #2,@-er1 ;01576d181250 -+ rotxl.w #2,@+er1 ;01556d181250 -+ rotxl.w #2,@er1- ;01566d181250 -+ rotxl.w #2,@(0x1234:16,er1) ;01546f1812341250 -+ rotxl.w #2,@(0x12345678:32,er1) ;78146b28123456781250 -+ rotxl.w #2,@(0x1234:16,r2l.b) ;01556f2812341250 -+ rotxl.w #2,@(0x1234:16,r2.w) ;01566f2812341250 -+ rotxl.w #2,@(0x1234:16,er2.l) ;01576f2812341250 -+ rotxl.w #2,@(0x12345678:32,r2l.b) ;78256b28123456781250 -+ rotxl.w #2,@(0x12345678:32,r2.w) ;78266b28123456781250 -+ rotxl.w #2,@(0x12345678:32,er2.l) ;78276b28123456781250 -+ rotxl.w #2,@0x1234:16 ;6b1812341250 -+ rotxl.w #2,@0x12345678:32 ;6b38123456781250 -+ -+ rotxl.l #2,er1 ;1271 -+ rotxl.l #2,@er1 ;010469181270 -+ rotxl.l #2,@(0xc:2,er1) ;010769181270 -+ rotxl.l #2,@er1+ ;01046d181270 -+ rotxl.l #2,@-er1 ;01076d181270 -+ rotxl.l #2,@+er1 ;01056d181270 -+ rotxl.l #2,@er1- ;01066d181270 -+ rotxl.l #2,@(0x1234:16,er1) ;01046f1812341270 -+ rotxl.l #2,@(0x12345678:32,er1) ;78946b28123456781270 -+ rotxl.l #2,@(0x1234:16,r2l.b) ;01056f2812341270 -+ rotxl.l #2,@(0x1234:16,r2.w) ;01066f2812341270 -+ rotxl.l #2,@(0x1234:16,er2.l) ;01076f2812341270 -+ rotxl.l #2,@(0x12345678:32,r2l.b) ;78a56b28123456781270 -+ rotxl.l #2,@(0x12345678:32,r2.w) ;78a66b28123456781270 -+ rotxl.l #2,@(0x12345678:32,er2.l) ;78a76b28123456781270 -+ rotxl.l #2,@0x1234:16 ;01046b0812341270 -+ rotxl.l #2,@0x12345678:32 ;01046b28123456781270 -+ -+ rotxr.b r1h ;1301 -+ rotxr.b @er1 ;7d101300 -+ rotxr.b @(0x3:2,er1) ;017768181300 -+ rotxr.b @er1+ ;01746c181300 -+ rotxr.b @-er1 ;01776c181300 -+ rotxr.b @+er1 ;01756c181300 -+ rotxr.b @er1- ;01766c181300 -+ rotxr.b @(0x1234:16,er1) ;01746e1812341300 -+ rotxr.b @(0x12345678:32,er1) ;78146a28123456781300 -+ rotxr.b @(0x1234:16,r2l.b) ;01756e2812341300 -+ rotxr.b @(0x1234:16,r2.w) ;01766e2812341300 -+ rotxr.b @(0x1234:16,er2.l) ;01776e2812341300 -+ rotxr.b @(0x12345678:32,r2l.b) ;78256a28123456781300 -+ rotxr.b @(0x12345678:32,r2.w) ;78266a28123456781300 -+ rotxr.b @(0x12345678:32,er2.l) ;78276a28123456781300 -+ rotxr.b @0xffffff12:8 ;7f121300 -+ rotxr.b @0x1234:16 ;6a1812341300 -+ rotxr.b @0x12345678:32 ;6a38123456781300 -+ -+ rotxr.w r1 ;1311 -+ rotxr.w @er1 ;7d901310 -+ rotxr.w @(0x6:2,er1) ;015769181310 -+ rotxr.w @er1+ ;01546d181310 -+ rotxr.w @-er1 ;01576d181310 -+ rotxr.w @+er1 ;01556d181310 -+ rotxr.w @er1- ;01566d181310 -+ rotxr.w @(0x1234:16,er1) ;01546f1812341310 -+ rotxr.w @(0x12345678:32,er1) ;78146b28123456781310 -+ rotxr.w @(0x1234:16,r2l.b) ;01556f2812341310 -+ rotxr.w @(0x1234:16,r2.w) ;01566f2812341310 -+ rotxr.w @(0x1234:16,er2.l) ;01576f2812341310 -+ rotxr.w @(0x12345678:32,r2l.b) ;78256b28123456781310 -+ rotxr.w @(0x12345678:32,r2.w) ;78266b28123456781310 -+ rotxr.w @(0x12345678:32,er2.l) ;78276b28123456781310 -+ rotxr.w @0x1234:16 ;6b1812341310 -+ rotxr.w @0x12345678:32 ;6b38123456781310 -+ -+ rotxr.l er1 ;1331 -+ rotxr.l @er1 ;010469181330 -+ rotxr.l @(0xc:2,er1) ;010769181330 -+ rotxr.l @er1+ ;01046d181330 -+ rotxr.l @-er1 ;01076d181330 -+ rotxr.l @+er1 ;01056d181330 -+ rotxr.l @er1- ;01066d181330 -+ rotxr.l @(0x1234:16,er1) ;01046f1812341330 -+ rotxr.l @(0x12345678:32,er1) ;78946b28123456781330 -+ rotxr.l @(0x1234:16,r2l.b) ;01056f2812341330 -+ rotxr.l @(0x1234:16,r2.w) ;01066f2812341330 -+ rotxr.l @(0x1234:16,er2.l) ;01076f2812341330 -+ rotxr.l @(0x12345678:32,r2l.b) ;78a56b28123456781330 -+ rotxr.l @(0x12345678:32,r2.w) ;78a66b28123456781330 -+ rotxr.l @(0x12345678:32,er2.l) ;78a76b28123456781330 -+ rotxr.l @0x1234:16 ;01046b0812341330 -+ rotxr.l @0x12345678:32 ;01046b28123456781330 -+ -+ rotxr.b #2,r1h ;1341 -+ rotxr.b #2,@er1 ;7d101340 -+ rotxr.b #2,@(0x3:2,er1) ;017768181340 -+ rotxr.b #2,@er1+ ;01746c181340 -+ rotxr.b #2,@-er1 ;01776c181340 -+ rotxr.b #2,@+er1 ;01756c181340 -+ rotxr.b #2,@er1- ;01766c181340 -+ rotxr.b #2,@(0x1234:16,er1) ;01746e1812341340 -+ rotxr.b #2,@(0x12345678:32,er1) ;78146a28123456781340 -+ rotxr.b #2,@(0x1234:16,r2l.b) ;01756e2812341340 -+ rotxr.b #2,@(0x1234:16,r2.w) ;01766e2812341340 -+ rotxr.b #2,@(0x1234:16,er2.l) ;01776e2812341340 -+ rotxr.b #2,@(0x12345678:32,r2l.b) ;78256a28123456781340 -+ rotxr.b #2,@(0x12345678:32,r2.w) ;78266a28123456781340 -+ rotxr.b #2,@(0x12345678:32,er2.l) ;78276a28123456781340 -+ rotxr.b #2,@0xffffff12:8 ;7f121340 -+ rotxr.b #2,@0x1234:16 ;6a1812341340 -+ rotxr.b #2,@0x12345678:32 ;6a38123456781340 -+ -+ rotxr.w #2,r1 ;1351 -+ rotxr.w #2,@er1 ;7d901350 -+ rotxr.w #2,@(0x6:2,er1) ;015769181350 -+ rotxr.w #2,@er1+ ;01546d181350 -+ rotxr.w #2,@-er1 ;01576d181350 -+ rotxr.w #2,@+er1 ;01556d181350 -+ rotxr.w #2,@er1- ;01566d181350 -+ rotxr.w #2,@(0x1234:16,er1) ;01546f1812341350 -+ rotxr.w #2,@(0x12345678:32,er1) ;78146b28123456781350 -+ rotxr.w #2,@(0x1234:16,r2l.b) ;01556f2812341350 -+ rotxr.w #2,@(0x1234:16,r2.w) ;01566f2812341350 -+ rotxr.w #2,@(0x1234:16,er2.l) ;01576f2812341350 -+ rotxr.w #2,@(0x12345678:32,r2l.b) ;78256b28123456781350 -+ rotxr.w #2,@(0x12345678:32,r2.w) ;78266b28123456781350 -+ rotxr.w #2,@(0x12345678:32,er2.l) ;78276b28123456781350 -+ rotxr.w #2,@0x1234:16 ;6b1812341350 -+ rotxr.w #2,@0x12345678:32 ;6b38123456781350 -+ -+ rotxr.l #2,er1 ;1371 -+ rotxr.l #2,@er1 ;010469181370 -+ rotxr.l #2,@(0xc:2,er1) ;010769181370 -+ rotxr.l #2,@er1+ ;01046d181370 -+ rotxr.l #2,@-er1 ;01076d181370 -+ rotxr.l #2,@+er1 ;01056d181370 -+ rotxr.l #2,@er1- ;01066d181370 -+ rotxr.l #2,@(0x1234:16,er1) ;01046f1812341370 -+ rotxr.l #2,@(0x12345678:32,er1) ;78946b28123456781370 -+ rotxr.l #2,@(0x1234:16,r2l.b) ;01056f2812341370 -+ rotxr.l #2,@(0x1234:16,r2.w) ;01066f2812341370 -+ rotxr.l #2,@(0x1234:16,er2.l) ;01076f2812341370 -+ rotxr.l #2,@(0x12345678:32,r2l.b) ;78a56b28123456781370 -+ rotxr.l #2,@(0x12345678:32,r2.w) ;78a66b28123456781370 -+ rotxr.l #2,@(0x12345678:32,er2.l) ;78a76b28123456781370 -+ rotxr.l #2,@0x1234:16 ;01046b0812341370 -+ rotxr.l #2,@0x12345678:32 ;01046b28123456781370 -+ -+ rotl.b r1h ;1281 -+ rotl.b @er1 ;7d101280 -+ rotl.b @(0x3:2,er1) ;017768181280 -+ rotl.b @er1+ ;01746c181280 -+ rotl.b @-er1 ;01776c181280 -+ rotl.b @+er1 ;01756c181280 -+ rotl.b @er1- ;01766c181280 -+ rotl.b @(0x1234:16,er1) ;01746e1812341280 -+ rotl.b @(0x12345678:32,er1) ;78146a28123456781280 -+ rotl.b @(0x1234:16,r2l.b) ;01756e2812341280 -+ rotl.b @(0x1234:16,r2.w) ;01766e2812341280 -+ rotl.b @(0x1234:16,er2.l) ;01776e2812341280 -+ rotl.b @(0x12345678:32,r2l.b) ;78256a28123456781280 -+ rotl.b @(0x12345678:32,r2.w) ;78266a28123456781280 -+ rotl.b @(0x12345678:32,er2.l) ;78276a28123456781280 -+ rotl.b @0xffffff12:8 ;7f121280 -+ rotl.b @0x1234:16 ;6a1812341280 -+ rotl.b @0x12345678:32 ;6a38123456781280 -+ -+ rotl.w r1 ;1291 -+ rotl.w @er1 ;7d901290 -+ rotl.w @(0x6:2,er1) ;015769181290 -+ rotl.w @-er1 ;01576d181290 -+ rotl.w @er1+ ;01546d181290 -+ rotl.w @er1- ;01566d181290 -+ rotl.w @+er1 ;01556d181290 -+ rotl.w @(0x1234:16,er1) ;01546f1812341290 -+ rotl.w @(0x12345678:32,er1) ;78146b28123456781290 -+ rotl.w @(0x1234:16,r2l.b) ;01556f2812341290 -+ rotl.w @(0x1234:16,r2.w) ;01566f2812341290 -+ rotl.w @(0x1234:16,er2.l) ;01576f2812341290 -+ rotl.w @(0x12345678:32,r2l.b) ;78256b28123456781290 -+ rotl.w @(0x12345678:32,r2.w) ;78266b28123456781290 -+ rotl.w @(0x12345678:32,er2.l) ;78276b28123456781290 -+ rotl.w @0x1234:16 ;6b1812341290 -+ rotl.w @0x12345678:32 ;6b38123456781290 -+ -+ rotl.l er1 ;12b1 -+ rotl.l @er1 ;0104691812b0 -+ rotl.l @(0xc:2,er1) ;0107691812b0 -+ rotl.l @er1+ ;01046d1812b0 -+ rotl.l @-er1 ;01076d1812b0 -+ rotl.l @+er1 ;01056d1812b0 -+ rotl.l @er1- ;01066d1812b0 -+ rotl.l @(0x1234:16,er1) ;01046f18123412b0 -+ rotl.l @(0x12345678:32,er1) ;78946b281234567812b0 -+ rotl.l @(0x1234:16,r2l.b) ;01056f28123412b0 -+ rotl.l @(0x1234:16,r2.w) ;01066f28123412b0 -+ rotl.l @(0x1234:16,er2.l) ;01076f28123412b0 -+ rotl.l @(0x12345678:32,r2l.b) ;78a56b281234567812b0 -+ rotl.l @(0x12345678:32,r2.w) ;78a66b281234567812b0 -+ rotl.l @(0x12345678:32,er2.l) ;78a76b281234567812b0 -+ rotl.l @0x1234:16 ;01046b08123412b0 -+ rotl.l @0x12345678:32 ;01046b281234567812b0 -+ -+ rotl.b #2,r1h ;12c1 -+ rotl.b #2,@er1 ;7d1012c0 -+ rotl.b #2,@(0x3:2,er1) ;0177681812c0 -+ rotl.b #2,@er1+ ;01746c1812c0 -+ rotl.b #2,@-er1 ;01776c1812c0 -+ rotl.b #2,@+er1 ;01756c1812c0 -+ rotl.b #2,@er1- ;01766c1812c0 -+ rotl.b #2,@(0x1234:16,er1) ;01746e18123412c0 -+ rotl.b #2,@(0x12345678:32,er1) ;78146a281234567812c0 -+ rotl.b #2,@(0x1234:16,r2l.b) ;01756e28123412c0 -+ rotl.b #2,@(0x1234:16,r2.w) ;01766e28123412c0 -+ rotl.b #2,@(0x1234:16,er2.l) ;01776e28123412c0 -+ rotl.b #2,@(0x12345678:32,r2l.b) ;78256a281234567812c0 -+ rotl.b #2,@(0x12345678:32,r2.w) ;78266a281234567812c0 -+ rotl.b #2,@(0x12345678:32,er2.l) ;78276a281234567812c0 -+ rotl.b #2,@0xffffff12:8 ;7f1212c0 -+ rotl.b #2,@0x1234:16 ;6a18123412c0 -+ rotl.b #2,@0x12345678:32 ;6a381234567812c0 -+ -+ rotl.w #2,r1 ;12d1 -+ rotl.w #2,@er1 ;7d9012d0 -+ rotl.w #2,@(0x6:2,er1) ;0157691812d0 -+ rotl.w #2,@er1+ ;01546d1812d0 -+ rotl.w #2,@-er1 ;01576d1812d0 -+ rotl.w #2,@+er1 ;01556d1812d0 -+ rotl.w #2,@er1- ;01566d1812d0 -+ rotl.w #2,@(0x1234:16,er1) ;01546f18123412d0 -+ rotl.w #2,@(0x12345678:32,er1) ;78146b281234567812d0 -+ rotl.w #2,@(0x1234:16,r2l.b) ;01556f28123412d0 -+ rotl.w #2,@(0x1234:16,r2.w) ;01566f28123412d0 -+ rotl.w #2,@(0x1234:16,er2.l) ;01576f28123412d0 -+ rotl.w #2,@(0x12345678:32,r2l.b) ;78256b281234567812d0 -+ rotl.w #2,@(0x12345678:32,r2.w) ;78266b281234567812d0 -+ rotl.w #2,@(0x12345678:32,er2.l) ;78276b281234567812d0 -+ rotl.w #2,@0x1234:16 ;6b18123412d0 -+ rotl.w #2,@0x12345678:32 ;6b381234567812d0 -+ -+ rotl.l #2,er1 ;12f1 -+ rotl.l #2,@er1 ;0104691812f0 -+ rotl.l #2,@(0xc:2,er1) ;0107691812f0 -+ rotl.l #2,@er1+ ;01046d1812f0 -+ rotl.l #2,@-er1 ;01076d1812f0 -+ rotl.l #2,@+er1 ;01056d1812f0 -+ rotl.l #2,@er1- ;01066d1812f0 -+ rotl.l #2,@(0x1234:16,er1) ;01046f18123412f0 -+ rotl.l #2,@(0x12345678:32,er1) ;78946b281234567812f0 -+ rotl.l #2,@(0x1234:16,r2l.b) ;01056f28123412f0 -+ rotl.l #2,@(0x1234:16,r2.w) ;01066f28123412f0 -+ rotl.l #2,@(0x1234:16,er2.l) ;01076f28123412f0 -+ rotl.l #2,@(0x12345678:32,r2l.b) ;78a56b281234567812f0 -+ rotl.l #2,@(0x12345678:32,r2.w) ;78a66b281234567812f0 -+ rotl.l #2,@(0x12345678:32,er2.l) ;78a76b281234567812f0 -+ rotl.l #2,@0x1234:16 ;01046b08123412f0 -+ rotl.l #2,@0x12345678:32 ;01046b281234567812f0 -+ -+ rotr.b r1h ;1381 -+ rotr.b @er1 ;7d101380 -+ rotr.b @(0x3:2,er1) ;017768181380 -+ rotr.b @er1+ ;01746c181380 -+ rotr.b @-er1 ;01776c181380 -+ rotr.b @+er1 ;01756c181380 -+ rotr.b @er1- ;01766c181380 -+ rotr.b @(0x1234:16,er1) ;01746e1812341380 -+ rotr.b @(0x12345678:32,er1) ;78146a28123456781380 -+ rotr.b @(0x1234:16,r2l.b) ;01756e2812341380 -+ rotr.b @(0x1234:16,r2.w) ;01766e2812341380 -+ rotr.b @(0x1234:16,er2.l) ;01776e2812341380 -+ rotr.b @(0x12345678:32,r2l.b) ;78256a28123456781380 -+ rotr.b @(0x12345678:32,r2.w) ;78266a28123456781380 -+ rotr.b @(0x12345678:32,er2.l) ;78276a28123456781380 -+ rotr.b @0xffffff12:8 ;7f121380 -+ rotr.b @0x1234:16 ;6a1812341380 -+ rotr.b @0x12345678:32 ;6a38123456781380 -+ -+ rotr.w r1 ;1391 -+ rotr.w @er1 ;7d901390 -+ rotr.w @(0x6:2,er1) ;015769181390 -+ rotr.w @-er1 ;01576d181390 -+ rotr.w @er1+ ;01546d181390 -+ rotr.w @er1- ;01566d181390 -+ rotr.w @+er1 ;01556d181390 -+ rotr.w @(0x1234:16,er1) ;01546f1812341390 -+ rotr.w @(0x12345678:32,er1) ;78146b28123456781390 -+ rotr.w @(0x1234:16,r2l.b) ;01556f2812341390 -+ rotr.w @(0x1234:16,r2.w) ;01566f2812341390 -+ rotr.w @(0x1234:16,er2.l) ;01576f2812341390 -+ rotr.w @(0x12345678:32,r2l.b) ;78256b28123456781390 -+ rotr.w @(0x12345678:32,r2.w) ;78266b28123456781390 -+ rotr.w @(0x12345678:32,er2.l) ;78276b28123456781390 -+ rotr.w @0x1234:16 ;6b1812341390 -+ rotr.w @0x12345678:32 ;6b38123456781390 -+ -+ rotr.l er1 ;13b1 -+ rotr.l @er1 ;0104691813b0 -+ rotr.l @(0xc:2,er1) ;0107691813b0 -+ rotr.l @er1+ ;01046d1813b0 -+ rotr.l @-er1 ;01076d1813b0 -+ rotr.l @+er1 ;01056d1813b0 -+ rotr.l @er1- ;01066d1813b0 -+ rotr.l @(0x1234:16,er1) ;01046f18123413b0 -+ rotr.l @(0x12345678:32,er1) ;78946b281234567813b0 -+ rotr.l @(0x1234:16,r2l.b) ;01056f28123413b0 -+ rotr.l @(0x1234:16,r2.w) ;01066f28123413b0 -+ rotr.l @(0x1234:16,er2.l) ;01076f28123413b0 -+ rotr.l @(0x12345678:32,r2l.b) ;78a56b281234567813b0 -+ rotr.l @(0x12345678:32,r2.w) ;78a66b281234567813b0 -+ rotr.l @(0x12345678:32,er2.l) ;78a76b281234567813b0 -+ rotr.l @0x1234:16 ;01046b08123413b0 -+ rotr.l @0x12345678:32 ;01046b281234567813b0 -+ -+ rotr.b #2,r1h ;13c1 -+ rotr.b #2,@er1 ;7d1013c0 -+ rotr.b #2,@(0x3:2,er1) ;0177681813c0 -+ rotr.b #2,@er1+ ;01746c1813c0 -+ rotr.b #2,@-er1 ;01776c1813c0 -+ rotr.b #2,@+er1 ;01756c1813c0 -+ rotr.b #2,@er1- ;01766c1813c0 -+ rotr.b #2,@(0x1234:16,er1) ;01746e18123413c0 -+ rotr.b #2,@(0x12345678:32,er1) ;78146a281234567813c0 -+ rotr.b #2,@(0x1234:16,r2l.b) ;01756e28123413c0 -+ rotr.b #2,@(0x1234:16,r2.w) ;01766e28123413c0 -+ rotr.b #2,@(0x1234:16,er2.l) ;01776e28123413c0 -+ rotr.b #2,@(0x12345678:32,r2l.b) ;78256a281234567813c0 -+ rotr.b #2,@(0x12345678:32,r2.w) ;78266a281234567813c0 -+ rotr.b #2,@(0x12345678:32,er2.l) ;78276a281234567813c0 -+ rotr.b #2,@0xffffff12:8 ;7f1213c0 -+ rotr.b #2,@0x1234:16 ;6a18123413c0 -+ rotr.b #2,@0x12345678:32 ;6a381234567813c0 -+ -+ rotr.w #2,r1 ;13d1 -+ rotr.w #2,@er1 ;7d9013d0 -+ rotr.w #2,@(0x6:2,er1) ;0157691813d0 -+ rotr.w #2,@er1+ ;01546d1813d0 -+ rotr.w #2,@-er1 ;01576d1813d0 -+ rotr.w #2,@+er1 ;01556d1813d0 -+ rotr.w #2,@er1- ;01566d1813d0 -+ rotr.w #2,@(0x1234:16,er1) ;01546f18123413d0 -+ rotr.w #2,@(0x12345678:32,er1) ;78146b281234567813d0 -+ rotr.w #2,@(0x1234:16,r2l.b) ;01556f28123413d0 -+ rotr.w #2,@(0x1234:16,r2.w) ;01566f28123413d0 -+ rotr.w #2,@(0x1234:16,er2.l) ;01576f28123413d0 -+ rotr.w #2,@(0x12345678:32,r2l.b) ;78256b281234567813d0 -+ rotr.w #2,@(0x12345678:32,r2.w) ;78266b281234567813d0 -+ rotr.w #2,@(0x12345678:32,er2.l) ;78276b281234567813d0 -+ rotr.w #2,@0x1234:16 ;6b18123413d0 -+ rotr.w #2,@0x12345678:32 ;6b381234567813d0 -+ -+ rotr.l #2,er1 ;13f1 -+ rotr.l #2,@er1 ;0104691813f0 -+ rotr.l #2,@(0xc:2,er1) ;0107691813f0 -+ rotr.l #2,@er1+ ;01046d1813f0 -+ rotr.l #2,@-er1 ;01076d1813f0 -+ rotr.l #2,@+er1 ;01056d1813f0 -+ rotr.l #2,@er1- ;01066d1813f0 -+ rotr.l #2,@(0x1234:16,er1) ;01046f18123413f0 -+ rotr.l #2,@(0x12345678:32,er1) ;78946b281234567813f0 -+ rotr.l #2,@(0x1234:16,r2l.b) ;01056f28123413f0 -+ rotr.l #2,@(0x1234:16,r2.w) ;01066f28123413f0 -+ rotr.l #2,@(0x1234:16,er2.l) ;01076f28123413f0 -+ rotr.l #2,@(0x12345678:32,r2l.b) ;78a56b281234567813f0 -+ rotr.l #2,@(0x12345678:32,r2.w) ;78a66b281234567813f0 -+ rotr.l #2,@(0x12345678:32,er2.l) ;78a76b281234567813f0 -+ rotr.l #2,@0x1234:16 ;01046b08123413f0 -+ rotr.l #2,@0x12345678:32 ;01046b281234567813f0 -+ -+ .end ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;log_sft ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ .h8300sx ++ .text ++_start: ++ not.b r1h ;1701 ++ not.b @er1 ;7d101700 ++ not.b @(0x3:2,er1) ;017768181700 ++ not.b @er1+ ;01746c181700 ++ not.b @-er1 ;01776c181700 ++ not.b @+er1 ;01756c181700 ++ not.b @er1- ;01766c181700 ++ not.b @(0x1234:16,er1) ;01746e1812341700 ++ not.b @(0x12345678:32,er1) ;78146a28123456781700 ++ not.b @(0x1234:16,r2l.b) ;01756e2812341700 ++ not.b @(0x1234:16,r2.w) ;01766e2812341700 ++ not.b @(0x1234:16,er2.l) ;01776e2812341700 ++ not.b @(0x12345678:32,r2l.b) ;78256a28123456781700 ++ not.b @(0x12345678:32,r2.w) ;78266a28123456781700 ++ not.b @(0x12345678:32,er2.l) ;78276a28123456781700 ++ not.b @0xffffff12:8 ;7f121700 ++ not.b @0x1234:16 ;6a1812341700 ++ not.b @0x12345678:32 ;6a38123456781700 ++ ++ not.w r1 ;1711 ++ not.w @er1 ;7d901710 ++ not.w @(0x6:2,er1) ;015769181710 ++ not.w @er1+ ;01546d181710 ++ not.w @-er1 ;01576d181710 ++ not.w @+er1 ;01556d181710 ++ not.w @er1- ;01566d181710 ++ not.w @(0x1234:16,er1) ;01546f1812341710 ++ not.w @(0x12345678:32,er1) ;78146b28123456781710 ++ not.w @(0x1234:16,r2l.b) ;01556f2812341710 ++ not.w @(0x1234:16,r2.w) ;01566f2812341710 ++ not.w @(0x1234:16,er2.l) ;01576f2812341710 ++ not.w @(0x12345678:32,r2l.b) ;78256b28123456781710 ++ not.w @(0x12345678:32,r2.w) ;78266b28123456781710 ++ not.w @(0x12345678:32,er2.l) ;78276b28123456781710 ++ not.w @0x1234:16 ;6b1812341710 ++ not.w @0x12345678:32 ;6b38123456781710 ++ ++ not.l er1 ;1731 ++ not.l @er1 ;010469181730 ++ not.l @(0xc:2,er1) ;010769181730 ++ not.l @er1+ ;01046d181730 ++ not.l @-er1 ;01076d181730 ++ not.l @+er1 ;01056d181730 ++ not.l @er1- ;01066d181730 ++ not.l @(0x1234:16,er1) ;01046f1812341730 ++ not.l @(0x12345678:32,er1) ;78946b28123456781730 ++ not.l @(0x1234:16,r2l.b) ;01056f2812341730 ++ not.l @(0x1234:16,r2.w) ;01066f2812341730 ++ not.l @(0x1234:16,er2.l) ;01076f2812341730 ++ not.l @(0x12345678:32,r2l.b) ;78a56b28123456781730 ++ not.l @(0x12345678:32,r2.w) ;78a66b28123456781730 ++ not.l @(0x12345678:32,er2.l) ;78a76b28123456781730 ++ not.l @0x1234:16 ;01046b0812341730 ++ not.l @0x12345678:32 ;01046b28123456781730 ++ ++ shll.b r1h ;1001 ++ shll.b @er1 ;7d101000 ++ shll.b @(0x3:2,er1) ;017768181000 ++ shll.b @er1+ ;01746c181000 ++ shll.b @-er1 ;01776c181000 ++ shll.b @+er1 ;01756c181000 ++ shll.b @er1- ;01766c181000 ++ shll.b @(0x1234:16,er1) ;01746e1812341000 ++ shll.b @(0x12345678:32,er1) ;78146a28123456781000 ++ shll.b @(0x1234:16,r2l.b) ;01756e2812341000 ++ shll.b @(0x1234:16,r2.w) ;01766e2812341000 ++ shll.b @(0x1234:16,er2.l) ;01776e2812341000 ++ shll.b @(0x12345678:32,r2l.b) ;78256a28123456781000 ++ shll.b @(0x12345678:32,r2.w) ;78266a28123456781000 ++ shll.b @(0x12345678:32,er2.l) ;78276a28123456781000 ++ shll.b @0xffffff12:8 ;7f121000 ++ shll.b @0x1234:16 ;6a1812341000 ++ shll.b @0x12345678:32 ;6a38123456781000 ++ ++ shll.w r1 ;1011 ++ shll.w @er1 ;7d901010 ++ shll.w @(0x6:2,er1) ;015769181010 ++ shll.w @er1+ ;01546d181010 ++ shll.w @-er1 ;01576d181010 ++ shll.w @+er1 ;01556d181010 ++ shll.w @er1- ;01566d181010 ++ shll.w @(0x1234:16,er1) ;01546f1812341010 ++ shll.w @(0x12345678:32,er1) ;78146b28123456781010 ++ shll.w @(0x1234:16,r2l.b) ;01556f2812341010 ++ shll.w @(0x1234:16,r2.w) ;01566f2812341010 ++ shll.w @(0x1234:16,er2.l) ;01576f2812341010 ++ shll.w @(0x12345678:32,r2l.b) ;78256b28123456781010 ++ shll.w @(0x12345678:32,r2.w) ;78266b28123456781010 ++ shll.w @(0x12345678:32,er2.l) ;78276b28123456781010 ++ shll.w @0x1234:16 ;6b1812341010 ++ shll.w @0x12345678:32 ;6b38123456781010 ++ ++ shll.l er1 ;1031 ++ shll.l @er1 ;010469181030 ++ shll.l @(0xc:2,er1) ;010769181030 ++ shll.l @er1+ ;01046d181030 ++ shll.l @-er1 ;01076d181030 ++ shll.l @+er1 ;01056d181030 ++ shll.l @er1- ;01066d181030 ++ shll.l @(0x1234:16,er1) ;01046f1812341030 ++ shll.l @(0x12345678:32,er1) ;78946b28123456781030 ++ shll.l @(0x1234:16,r2l.b) ;01056f2812341030 ++ shll.l @(0x1234:16,r2.w) ;01066f2812341030 ++ shll.l @(0x1234:16,er2.l) ;01076f2812341030 ++ shll.l @(0x12345678:32,r2l.b) ;78a56b28123456781030 ++ shll.l @(0x12345678:32,r2.w) ;78a66b28123456781030 ++ shll.l @(0x12345678:32,er2.l) ;78a76b28123456781030 ++ shll.l @0x1234:16 ;01046b0812341030 ++ shll.l @0x12345678:32 ;01046b28123456781030 ++ ++ shll.b #2,r1h ;1041 ++ shll.b #2,@er1 ;7d101040 ++ shll.b #2,@(0x3:2,er1) ;017768181040 ++ shll.b #2,@er1+ ;01746c181040 ++ shll.b #2,@-er1 ;01776c181040 ++ shll.b #2,@+er1 ;01756c181040 ++ shll.b #2,@er1- ;01766c181040 ++ shll.b #2,@(0x1234:16,er1) ;01746e1812341040 ++ shll.b #2,@(0x12345678:32,er1) ;78146a28123456781040 ++ shll.b #2,@(0x1234:16,r2l.b) ;01756e2812341040 ++ shll.b #2,@(0x1234:16,r2.w) ;01766e2812341040 ++ shll.b #2,@(0x1234:16,er2.l) ;01776e2812341040 ++ shll.b #2,@(0x12345678:32,r2l.b) ;78256a28123456781040 ++ shll.b #2,@(0x12345678:32,r2.w) ;78266a28123456781040 ++ shll.b #2,@(0x12345678:32,er2.l) ;78276a28123456781040 ++ shll.b #2,@0xffffff12:8 ;7f121040 ++ shll.b #2,@0x1234:16 ;6a1812341040 ++ shll.b #2,@0x12345678:32 ;6a38123456781040 ++ ++ shll.w #2,r1 ;1051 ++ shll.w #2,@er1 ;7d901050 ++ shll.w #2,@(0x6:2,er1) ;015769181050 ++ shll.w #2,@er1+ ;01546d181050 ++ shll.w #2,@-er1 ;01576d181050 ++ shll.w #2,@+er1 ;01556d181050 ++ shll.w #2,@er1- ;01566d181050 ++ shll.w #2,@(0x1234:16,er1) ;01546f1812341050 ++ shll.w #2,@(0x12345678:32,er1) ;78146b28123456781050 ++ shll.w #2,@(0x1234:16,r2l.b) ;01556f2812341050 ++ shll.w #2,@(0x1234:16,r2.w) ;01566f2812341050 ++ shll.w #2,@(0x1234:16,er2.l) ;01576f2812341050 ++ shll.w #2,@(0x12345678:32,r2l.b) ;78256b28123456781050 ++ shll.w #2,@(0x12345678:32,r2.w) ;78266b28123456781050 ++ shll.w #2,@(0x12345678:32,er2.l) ;78276b28123456781050 ++ shll.w #2,@0x1234:16 ;6b1812341050 ++ shll.w #2,@0x12345678:32 ;6b38123456781050 ++ ++ shll.l #2,er1 ;1071 ++ shll.l #2,@er1 ;010469181070 ++ shll.l #2,@(0xc:2,er1) ;010769181070 ++ shll.l #2,@er1+ ;01046d181070 ++ shll.l #2,@-er1 ;01076d181070 ++ shll.l #2,@+er1 ;01056d181070 ++ shll.l #2,@er1- ;01066d181070 ++ shll.l #2,@(0x1234:16,er1) ;01046f1812341070 ++ shll.l #2,@(0x12345678:32,er1) ;78946b28123456781070 ++ shll.l #2,@(0x1234:16,r2l.b) ;01056f2812341070 ++ shll.l #2,@(0x1234:16,r2.w) ;01066f2812341070 ++ shll.l #2,@(0x1234:16,er2.l) ;01076f2812341070 ++ shll.l #2,@(0x12345678:32,r2l.b) ;78a56b28123456781070 ++ shll.l #2,@(0x12345678:32,r2.w) ;78a66b28123456781070 ++ shll.l #2,@(0x12345678:32,er2.l) ;78a76b28123456781070 ++ shll.l #2,@0x1234:16 ;01046b0812341070 ++ shll.l #2,@0x12345678:32 ;01046b28123456781070 ++ ++ shll.b #4,r1h ;10a1 ++ shll.b #4,@er1 ;7d1010a0 ++ shll.b #4,@(0x3:2,er1) ;0177681810a0 ++ shll.b #4,@er1+ ;01746c1810a0 ++ shll.b #4,@-er1 ;01776c1810a0 ++ shll.b #4,@+er1 ;01756c1810a0 ++ shll.b #4,@er1- ;01766c1810a0 ++ shll.b #4,@(0x1234:16,er1) ;01746e18123410a0 ++ shll.b #4,@(0x12345678:32,er1) ;78146a281234567810a0 ++ shll.b #4,@(0x1234:16,r2l.b) ;01756e28123410a0 ++ shll.b #4,@(0x1234:16,r2.w) ;01766e28123410a0 ++ shll.b #4,@(0x1234:16,er2.l) ;01776e28123410a0 ++ shll.b #4,@(0x12345678:32,r2l.b) ;78256a281234567810a0 ++ shll.b #4,@(0x12345678:32,r2.w) ;78266a281234567810a0 ++ shll.b #4,@(0x12345678:32,er2.l) ;78276a281234567810a0 ++ shll.b #4,@0xffffff12:8 ;7f1210a0 ++ shll.b #4,@0x1234:16 ;6a18123410a0 ++ shll.b #4,@0x12345678:32 ;6a381234567810a0 ++ ++ shll.w #4,r1 ;1021 ++ shll.w #4,@er1 ;7d901020 ++ shll.w #4,@(0x6:2,er1) ;015769181020 ++ shll.w #4,@er1+ ;01546d181020 ++ shll.w #4,@-er1 ;01576d181020 ++ shll.w #4,@+er1 ;01556d181020 ++ shll.w #4,@er1- ;01566d181020 ++ shll.w #4,@(0x1234:16,er1) ;01546f1812341020 ++ shll.w #4,@(0x12345678:32,er1) ;78146b28123456781020 ++ shll.w #4,@(0x1234:16,r2l.b) ;01556f2812341020 ++ shll.w #4,@(0x1234:16,r2.w) ;01566f2812341020 ++ shll.w #4,@(0x1234:16,er2.l) ;01576f2812341020 ++ shll.w #4,@(0x12345678:32,r2l.b) ;78256b28123456781020 ++ shll.w #4,@(0x12345678:32,r2.w) ;78266b28123456781020 ++ shll.w #4,@(0x12345678:32,er2.l) ;78276b28123456781020 ++ shll.w #4,@0x1234:16 ;6b1812341020 ++ shll.w #4,@0x12345678:32 ;6b38123456781020 ++ ++ shll.l #4,er1 ;1039 ++ shll.l #4,@er1 ;010469181038 ++ shll.l #4,@(0xc:2,er1) ;010769181038 ++ shll.l #4,@er1+ ;01046d181038 ++ shll.l #4,@-er1 ;01076d181038 ++ shll.l #4,@+er1 ;01056d181038 ++ shll.l #4,@er1- ;01066d181038 ++ shll.l #4,@(0x1234:16,er1) ;01046f1812341038 ++ shll.l #4,@(0x12345678:32,er1) ;78946b28123456781038 ++ shll.l #4,@(0x1234:16,r2l.b) ;01056f2812341038 ++ shll.l #4,@(0x1234:16,r2.w) ;01066f2812341038 ++ shll.l #4,@(0x1234:16,er2.l) ;01076f2812341038 ++ shll.l #4,@(0x12345678:32,r2l.b) ;78a56b28123456781038 ++ shll.l #4,@(0x12345678:32,r2.w) ;78a66b28123456781038 ++ shll.l #4,@(0x12345678:32,er2.l) ;78a76b28123456781038 ++ shll.l #4,@0x1234:16 ;01046b0812341038 ++ shll.l #4,@0x12345678:32 ;01046b28123456781038 ++ ++ shll.w #8,r1 ;1061 ++ shll.w #8,@er1 ;7d901060 ++ shll.w #8,@(0x6:2,er1) ;015769181060 ++ shll.w #8,@er1+ ;01546d181060 ++ shll.w #8,@-er1 ;01576d181060 ++ shll.w #8,@+er1 ;01556d181060 ++ shll.w #8,@er1- ;01566d181060 ++ shll.w #8,@(0x1234:16,er1) ;01546f1812341060 ++ shll.w #8,@(0x12345678:32,er1) ;78146b28123456781060 ++ shll.w #8,@(0x1234:16,r2l.b) ;01556f2812341060 ++ shll.w #8,@(0x1234:16,r2.w) ;01566f2812341060 ++ shll.w #8,@(0x1234:16,er2.l) ;01576f2812341060 ++ shll.w #8,@(0x12345678:32,r2l.b) ;78256b28123456781060 ++ shll.w #8,@(0x12345678:32,r2.w) ;78266b28123456781060 ++ shll.w #8,@(0x12345678:32,er2.l) ;78276b28123456781060 ++ shll.w #8,@0x1234:16 ;6b1812341060 ++ shll.w #8,@0x12345678:32 ;6b38123456781060 ++ ++ shll.l #8,er1 ;1079 ++ shll.l #8,@er1 ;010469181078 ++ shll.l #8,@(0xc:2,er1) ;010769181078 ++ shll.l #8,@er1+ ;01046d181078 ++ shll.l #8,@-er1 ;01076d181078 ++ shll.l #8,@+er1 ;01056d181078 ++ shll.l #8,@er1- ;01066d181078 ++ shll.l #8,@(0x1234:16,er1) ;01046f1812341078 ++ shll.l #8,@(0x12345678:32,er1) ;78946b28123456781078 ++ shll.l #8,@(0x1234:16,r2l.b) ;01056f2812341078 ++ shll.l #8,@(0x1234:16,r2.w) ;01066f2812341078 ++ shll.l #8,@(0x1234:16,er2.l) ;01076f2812341078 ++ shll.l #8,@(0x12345678:32,r2l.b) ;78a56b28123456781078 ++ shll.l #8,@(0x12345678:32,r2.w) ;78a66b28123456781078 ++ shll.l #8,@(0x12345678:32,er2.l) ;78a76b28123456781078 ++ shll.l #8,@0x1234:16 ;01046b0812341078 ++ shll.l #8,@0x12345678:32 ;01046b28123456781078 ++ ++ shll.l #16,er1 ;10f9 ++ shll.l #16,@er1 ;0104691810f8 ++ shll.l #16,@(0xc:2,er1) ;0107691810f8 ++ shll.l #16,@er1+ ;01046d1810f8 ++ shll.l #16,@-er1 ;01076d1810f8 ++ shll.l #16,@+er1 ;01056d1810f8 ++ shll.l #16,@er1- ;01066d1810f8 ++ shll.l #16,@(0x1234:16,er1) ;01046f18123410f8 ++ shll.l #16,@(0x12345678:32,er1) ;78946b281234567810f8 ++ shll.l #16,@(0x1234:16,r2l.b) ;01056f28123410f8 ++ shll.l #16,@(0x1234:16,r2.w) ;01066f28123410f8 ++ shll.l #16,@(0x1234:16,er2.l) ;01076f28123410f8 ++ shll.l #16,@(0x12345678:32,r2l.b) ;78a56b281234567810f8 ++ shll.l #16,@(0x12345678:32,r2.w) ;78a66b281234567810f8 ++ shll.l #16,@(0x12345678:32,er2.l) ;78a76b281234567810f8 ++ shll.l #16,@0x1234:16 ;01046b08123410f8 ++ shll.l #16,@0x12345678:32 ;01046b281234567810f8 ++ ++ shll.b #0x7:5,r1h ;03871001 ++ shll.w #0xf:5,r1 ;038f1011 ++ shll.l #0x1f:5,er1 ;039f1031 ++ ++ shll.b r3h,r1h ;78381001 ++ shll.w r3h,r1 ;78381011 ++ shll.l r3h,er1 ;78381031 ++ ++ shlr.b r1h ;1101 ++ shlr.b @er1 ;7d101100 ++ shlr.b @(0x3:2,er1) ;017768181100 ++ shlr.b @er1+ ;01746c181100 ++ shlr.b @-er1 ;01776c181100 ++ shlr.b @+er1 ;01756c181100 ++ shlr.b @er1- ;01766c181100 ++ shlr.b @(0x1234:16,er1) ;01746e1812341100 ++ shlr.b @(0x12345678:32,er1) ;78146a28123456781100 ++ shlr.b @(0x1234:16,r2l.b) ;01756e2812341100 ++ shlr.b @(0x1234:16,r2.w) ;01766e2812341100 ++ shlr.b @(0x1234:16,er2.l) ;01776e2812341100 ++ shlr.b @(0x12345678:32,r2l.b) ;78256a28123456781100 ++ shlr.b @(0x12345678:32,r2.w) ;78266a28123456781100 ++ shlr.b @(0x12345678:32,er2.l) ;78276a28123456781100 ++ shlr.b @0xffffff12:8 ;7f121100 ++ shlr.b @0x1234:16 ;6a1812341100 ++ shlr.b @0x12345678:32 ;6a38123456781100 ++ ++ shlr.w r1 ;1111 ++ shlr.w @er1 ;7d901110 ++ shlr.w @(0x6:2,er1) ;015769181110 ++ shlr.w @er1+ ;01546d181110 ++ shlr.w @-er1 ;01576d181110 ++ shlr.w @+er1 ;01556d181110 ++ shlr.w @er1- ;01566d181110 ++ shlr.w @(0x1234:16,er1) ;01546f1812341110 ++ shlr.w @(0x12345678:32,er1) ;78146b28123456781110 ++ shlr.w @(0x1234:16,r2l.b) ;01556f2812341110 ++ shlr.w @(0x1234:16,r2.w) ;01566f2812341110 ++ shlr.w @(0x1234:16,er2.l) ;01576f2812341110 ++ shlr.w @(0x12345678:32,r2l.b) ;78256b28123456781110 ++ shlr.w @(0x12345678:32,r2.w) ;78266b28123456781110 ++ shlr.w @(0x12345678:32,er2.l) ;78276b28123456781110 ++ shlr.w @0x1234:16 ;6b1812341110 ++ shlr.w @0x12345678:32 ;6b38123456781110 ++ ++ shlr.l er1 ;1131 ++ shlr.l @er1 ;010469181130 ++ shlr.l @(0xc:2,er1) ;010769181130 ++ shlr.l @er1+ ;01046d181130 ++ shlr.l @-er1 ;01076d181130 ++ shlr.l @+er1 ;01056d181130 ++ shlr.l @er1- ;01066d181130 ++ shlr.l @(0x1234:16,er1) ;01046f1812341130 ++ shlr.l @(0x12345678:32,er1) ;78946b28123456781130 ++ shlr.l @(0x1234:16,r2l.b) ;01056f2812341130 ++ shlr.l @(0x1234:16,r2.w) ;01066f2812341130 ++ shlr.l @(0x1234:16,er2.l) ;01076f2812341130 ++ shlr.l @(0x12345678:32,r2l.b) ;78a56b28123456781130 ++ shlr.l @(0x12345678:32,r2.w) ;78a66b28123456781130 ++ shlr.l @(0x12345678:32,er2.l) ;78a76b28123456781130 ++ shlr.l @0x1234:16 ;01046b0812341130 ++ shlr.l @0x12345678:32 ;01046b28123456781130 ++ ++ shlr.b #2,r1h ;1141 ++ shlr.b #2,@er1 ;7d101140 ++ shlr.b #2,@(0x3:2,er1) ;017768181140 ++ shlr.b #2,@er1+ ;01746c181140 ++ shlr.b #2,@-er1 ;01776c181140 ++ shlr.b #2,@+er1 ;01756c181140 ++ shlr.b #2,@er1- ;01766c181140 ++ shlr.b #2,@(0x1234:16,er1) ;01746e1812341140 ++ shlr.b #2,@(0x12345678:32,er1) ;78146a28123456781140 ++ shlr.b #2,@(0x1234:16,r2l.b) ;01756e2812341140 ++ shlr.b #2,@(0x1234:16,r2.w) ;01766e2812341140 ++ shlr.b #2,@(0x1234:16,er2.l) ;01776e2812341140 ++ shlr.b #2,@(0x12345678:32,r2l.b) ;78256a28123456781140 ++ shlr.b #2,@(0x12345678:32,r2.w) ;78266a28123456781140 ++ shlr.b #2,@(0x12345678:32,er2.l) ;78276a28123456781140 ++ shlr.b #2,@0xffffff12:8 ;7f121140 ++ shlr.b #2,@0x1234:16 ;6a1812341140 ++ shlr.b #2,@0x12345678:32 ;6a38123456781140 ++ ++ shlr.w #2,r1 ;1151 ++ shlr.w #2,@er1 ;7d901150 ++ shlr.w #2,@(0x6:2,er1) ;015769181150 ++ shlr.w #2,@er1+ ;01546d181150 ++ shlr.w #2,@-er1 ;01576d181150 ++ shlr.w #2,@+er1 ;01556d181150 ++ shlr.w #2,@er1- ;01566d181150 ++ shlr.w #2,@(0x1234:16,er1) ;01546f1812341150 ++ shlr.w #2,@(0x12345678:32,er1) ;78146b28123456781150 ++ shlr.w #2,@(0x1234:16,r2l.b) ;01556f2812341150 ++ shlr.w #2,@(0x1234:16,r2.w) ;01566f2812341150 ++ shlr.w #2,@(0x1234:16,er2.l) ;01576f2812341150 ++ shlr.w #2,@(0x12345678:32,r2l.b) ;78256b28123456781150 ++ shlr.w #2,@(0x12345678:32,r2.w) ;78266b28123456781150 ++ shlr.w #2,@(0x12345678:32,er2.l) ;78276b28123456781150 ++ shlr.w #2,@0x1234:16 ;6b1812341150 ++ shlr.w #2,@0x12345678:32 ;6b38123456781150 ++ ++ shlr.l #2,er1 ;1171 ++ shlr.l #2,@er1 ;010469181170 ++ shlr.l #2,@(0xc:2,er1) ;010769181170 ++ shlr.l #2,@er1+ ;01046d181170 ++ shlr.l #2,@-er1 ;01076d181170 ++ shlr.l #2,@+er1 ;01056d181170 ++ shlr.l #2,@er1- ;01066d181170 ++ shlr.l #2,@(0x1234:16,er1) ;01046f1812341170 ++ shlr.l #2,@(0x12345678:32,er1) ;78946b28123456781170 ++ shlr.l #2,@(0x1234:16,r2l.b) ;01056f2812341170 ++ shlr.l #2,@(0x1234:16,r2.w) ;01066f2812341170 ++ shlr.l #2,@(0x1234:16,er2.l) ;01076f2812341170 ++ shlr.l #2,@(0x12345678:32,r2l.b) ;78a56b28123456781170 ++ shlr.l #2,@(0x12345678:32,r2.w) ;78a66b28123456781170 ++ shlr.l #2,@(0x12345678:32,er2.l) ;78a76b28123456781170 ++ shlr.l #2,@0x1234:16 ;01046b0812341170 ++ shlr.l #2,@0x12345678:32 ;01046b28123456781170 ++ ++ shlr.b #4,r1h ;11a1 ++ shlr.b #4,@er1 ;7d1011a0 ++ shlr.b #4,@(0x3:2,er1) ;0177681811a0 ++ shlr.b #4,@er1+ ;01746c1811a0 ++ shlr.b #4,@-er1 ;01776c1811a0 ++ shlr.b #4,@+er1 ;01756c1811a0 ++ shlr.b #4,@er1- ;01766c1811a0 ++ shlr.b #4,@(0x1234:16,er1) ;01746e18123411a0 ++ shlr.b #4,@(0x12345678:32,er1) ;78146a281234567811a0 ++ shlr.b #4,@(0x1234:16,r2l.b) ;01756e28123411a0 ++ shlr.b #4,@(0x1234:16,r2.w) ;01766e28123411a0 ++ shlr.b #4,@(0x1234:16,er2.l) ;01776e28123411a0 ++ shlr.b #4,@(0x12345678:32,r2l.b) ;78256a281234567811a0 ++ shlr.b #4,@(0x12345678:32,r2.w) ;78266a281234567811a0 ++ shlr.b #4,@(0x12345678:32,er2.l) ;78276a281234567811a0 ++ shlr.b #4,@0xffffff12:8 ;7f1211a0 ++ shlr.b #4,@0x1234:16 ;6a18123411a0 ++ shlr.b #4,@0x12345678:32 ;6a381234567811a0 ++ ++ shlr.w #4,r1 ;1121 ++ shlr.w #4,@er1 ;7d901120 ++ shlr.w #4,@(0x6:2,er1) ;015769181120 ++ shlr.w #4,@er1+ ;01546d181120 ++ shlr.w #4,@-er1 ;01576d181120 ++ shlr.w #4,@+er1 ;01556d181120 ++ shlr.w #4,@er1- ;01566d181120 ++ shlr.w #4,@(0x1234:16,er1) ;01546f1812341120 ++ shlr.w #4,@(0x12345678:32,er1) ;78146b28123456781120 ++ shlr.w #4,@(0x1234:16,r2l.b) ;01556f2812341120 ++ shlr.w #4,@(0x1234:16,r2.w) ;01566f2812341120 ++ shlr.w #4,@(0x1234:16,er2.l) ;01576f2812341120 ++ shlr.w #4,@(0x12345678:32,r2l.b) ;78256b28123456781120 ++ shlr.w #4,@(0x12345678:32,r2.w) ;78266b28123456781120 ++ shlr.w #4,@(0x12345678:32,er2.l) ;78276b28123456781120 ++ shlr.w #4,@0x1234:16 ;6b1812341120 ++ shlr.w #4,@0x12345678:32 ;6b38123456781120 ++ ++ shlr.l #4,er1 ;1139 ++ shlr.l #4,@er1 ;010469181138 ++ shlr.l #4,@(0xc:2,er1) ;010769181138 ++ shlr.l #4,@er1+ ;01046d181138 ++ shlr.l #4,@-er1 ;01076d181138 ++ shlr.l #4,@+er1 ;01056d181138 ++ shlr.l #4,@er1- ;01066d181138 ++ shlr.l #4,@(0x1234:16,er1) ;01046f1812341138 ++ shlr.l #4,@(0x12345678:32,er1) ;78946b28123456781138 ++ shlr.l #4,@(0x1234:16,r2l.b) ;01056f2812341138 ++ shlr.l #4,@(0x1234:16,r2.w) ;01066f2812341138 ++ shlr.l #4,@(0x1234:16,er2.l) ;01076f2812341138 ++ shlr.l #4,@(0x12345678:32,r2l.b) ;78a56b28123456781138 ++ shlr.l #4,@(0x12345678:32,r2.w) ;78a66b28123456781138 ++ shlr.l #4,@(0x12345678:32,er2.l) ;78a76b28123456781138 ++ shlr.l #4,@0x1234:16 ;01046b0812341138 ++ shlr.l #4,@0x12345678:32 ;01046b28123456781138 ++ ++ shlr.w #8,r1 ;1161 ++ shlr.w #8,@er1 ;7d901160 ++ shlr.w #8,@(0x6:2,er1) ;015769181160 ++ shlr.w #8,@er1+ ;01546d181160 ++ shlr.w #8,@-er1 ;01576d181160 ++ shlr.w #8,@+er1 ;01556d181160 ++ shlr.w #8,@er1- ;01566d181160 ++ shlr.w #8,@(0x1234:16,er1) ;01546f1812341160 ++ shlr.w #8,@(0x12345678:32,er1) ;78146b28123456781160 ++ shlr.w #8,@(0x1234:16,r2l.b) ;01556f2812341160 ++ shlr.w #8,@(0x1234:16,r2.w) ;01566f2812341160 ++ shlr.w #8,@(0x1234:16,er2.l) ;01576f2812341160 ++ shlr.w #8,@(0x12345678:32,r2l.b) ;78256b28123456781160 ++ shlr.w #8,@(0x12345678:32,r2.w) ;78266b28123456781160 ++ shlr.w #8,@(0x12345678:32,er2.l) ;78276b28123456781160 ++ shlr.w #8,@0x1234:16 ;6b1812341160 ++ shlr.w #8,@0x12345678:32 ;6b38123456781160 ++ ++ shlr.l #8,er1 ;1179 ++ shlr.l #8,@er1 ;010469181178 ++ shlr.l #8,@(0xc:2,er1) ;010769181178 ++ shlr.l #8,@er1+ ;01046d181178 ++ shlr.l #8,@-er1 ;01076d181178 ++ shlr.l #8,@+er1 ;01056d181178 ++ shlr.l #8,@er1- ;01066d181178 ++ shlr.l #8,@(0x1234:16,er1) ;01046f1812341178 ++ shlr.l #8,@(0x12345678:32,er1) ;78946b28123456781178 ++ shlr.l #8,@(0x1234:16,r2l.b) ;01056f2812341178 ++ shlr.l #8,@(0x1234:16,r2.w) ;01066f2812341178 ++ shlr.l #8,@(0x1234:16,er2.l) ;01076f2812341178 ++ shlr.l #8,@(0x12345678:32,r2l.b) ;78a56b28123456781178 ++ shlr.l #8,@(0x12345678:32,r2.w) ;78a66b28123456781178 ++ shlr.l #8,@(0x12345678:32,er2.l) ;78a76b28123456781178 ++ shlr.l #8,@0x1234:16 ;01046b0812341178 ++ shlr.l #8,@0x12345678:32 ;01046b28123456781178 ++ ++ shlr.l #16,er1 ;11f9 ++ shlr.l #16,@er1 ;0104691811f8 ++ shlr.l #16,@(0xc:2,er1) ;0107691811f8 ++ shlr.l #16,@er1+ ;01046d1811f8 ++ shlr.l #16,@-er1 ;01076d1811f8 ++ shlr.l #16,@+er1 ;01056d1811f8 ++ shlr.l #16,@er1- ;01066d1811f8 ++ shlr.l #16,@(0x1234:16,er1) ;01046f18123411f8 ++ shlr.l #16,@(0x12345678:32,er1) ;78946b281234567811f8 ++ shlr.l #16,@(0x1234:16,r2l.b) ;01056f28123411f8 ++ shlr.l #16,@(0x1234:16,r2.w) ;01066f28123411f8 ++ shlr.l #16,@(0x1234:16,er2.l) ;01076f28123411f8 ++ shlr.l #16,@(0x12345678:32,r2l.b) ;78a56b281234567811f8 ++ shlr.l #16,@(0x12345678:32,r2.w) ;78a66b281234567811f8 ++ shlr.l #16,@(0x12345678:32,er2.l) ;78a76b281234567811f8 ++ shlr.l #16,@0x1234:16 ;01046b08123411f8 ++ shlr.l #16,@0x12345678:32 ;01046b281234567811f8 ++ ++ shlr.b #0x7:5,r1h ;03871101 ++ shlr.w #0xf:5,r1 ;038f1111 ++ shlr.l #0x1f:5,er1 ;039f1131 ++ ++ shlr.b r3h,r1h ;78381101 ++ shlr.w r3h,r1 ;78381111 ++ shlr.l r3h,er1 ;78381131 ++ ++ shal.b r1h ;1081 ++ shal.b @er1 ;7d101080 ++ shal.b @(0x3:2,er1) ;017768181080 ++ shal.b @er1+ ;01746c181080 ++ shal.b @-er1 ;01776c181080 ++ shal.b @+er1 ;01756c181080 ++ shal.b @er1- ;01766c181080 ++ shal.b @(0x1234:16,er1) ;01746e1812341080 ++ shal.b @(0x12345678:32,er1) ;78146a28123456781080 ++ shal.b @(0x1234:16,r2l.b) ;01756e2812341080 ++ shal.b @(0x1234:16,r2.w) ;01766e2812341080 ++ shal.b @(0x1234:16,er2.l) ;01776e2812341080 ++ shal.b @(0x12345678:32,r2l.b) ;78256a28123456781080 ++ shal.b @(0x12345678:32,r2.w) ;78266a28123456781080 ++ shal.b @(0x12345678:32,er2.l) ;78276a28123456781080 ++ shal.b @0xffffff12:8 ;7f121080 ++ shal.b @0x1234:16 ;6a1812341080 ++ shal.b @0x12345678:32 ;6a38123456781080 ++ ++ shal.w r1 ;1091 ++ shal.w @er1 ;7d901090 ++ shal.w @(0x6:2,er1) ;015769181090 ++ shal.w @er1+ ;01546d181090 ++ shal.w @-er1 ;01576d181090 ++ shal.w @+er1 ;01556d181090 ++ shal.w @er1- ;01566d181090 ++ shal.w @(0x1234:16,er1) ;01546f1812341090 ++ shal.w @(0x12345678:32,er1) ;78146b28123456781090 ++ shal.w @(0x1234:16,r2l.b) ;01556f2812341090 ++ shal.w @(0x1234:16,r2.w) ;01566f2812341090 ++ shal.w @(0x1234:16,er2.l) ;01576f2812341090 ++ shal.w @(0x12345678:32,r2l.b) ;78256b28123456781090 ++ shal.w @(0x12345678:32,r2.w) ;78266b28123456781090 ++ shal.w @(0x12345678:32,er2.l) ;78276b28123456781090 ++ shal.w @0x1234:16 ;6b1812341090 ++ shal.w @0x12345678:32 ;6b38123456781090 ++ ++ shal.l er1 ;10b1 ++ shal.l @er1 ;0104691810b0 ++ shal.l @(0xc:2,er1) ;0107691810b0 ++ shal.l @er1+ ;01046d1810b0 ++ shal.l @-er1 ;01076d1810b0 ++ shal.l @+er1 ;01056d1810b0 ++ shal.l @er1- ;01066d1810b0 ++ shal.l @(0x1234:16,er1) ;01046f18123410b0 ++ shal.l @(0x12345678:32,er1) ;78946b281234567810b0 ++ shal.l @(0x1234:16,r2l.b) ;01056f28123410b0 ++ shal.l @(0x1234:16,r2.w) ;01066f28123410b0 ++ shal.l @(0x1234:16,er2.l) ;01076f28123410b0 ++ shal.l @(0x12345678:32,r2l.b) ;78a56b281234567810b0 ++ shal.l @(0x12345678:32,r2.w) ;78a66b281234567810b0 ++ shal.l @(0x12345678:32,er2.l) ;78a76b281234567810b0 ++ shal.l @0x1234:16 ;01046b08123410b0 ++ shal.l @0x12345678:32 ;01046b281234567810b0 ++ ++ shal.b #2,r1h ;10c1 ++ shal.b #2,@er1 ;7d1010c0 ++ shal.b #2,@(0x3:2,er1) ;0177681810c0 ++ shal.b #2,@er1+ ;01746c1810c0 ++ shal.b #2,@-er1 ;01776c1810c0 ++ shal.b #2,@+er1 ;01756c1810c0 ++ shal.b #2,@er1- ;01766c1810c0 ++ shal.b #2,@(0x1234:16,er1) ;01746e18123410c0 ++ shal.b #2,@(0x12345678:32,er1) ;78146a281234567810c0 ++ shal.b #2,@(0x1234:16,r2l.b) ;01756e28123410c0 ++ shal.b #2,@(0x1234:16,r2.w) ;01766e28123410c0 ++ shal.b #2,@(0x1234:16,er2.l) ;01776e28123410c0 ++ shal.b #2,@(0x12345678:32,r2l.b) ;78256a281234567810c0 ++ shal.b #2,@(0x12345678:32,r2.w) ;78266a281234567810c0 ++ shal.b #2,@(0x12345678:32,er2.l) ;78276a281234567810c0 ++ shal.b #2,@0xffffff12:8 ;7f1210c0 ++ shal.b #2,@0x1234:16 ;6a18123410c0 ++ shal.b #2,@0x12345678:32 ;6a381234567810c0 ++ ++ shal.w #2,r1 ;10d1 ++ shal.w #2,@er1 ;7d9010d0 ++ shal.w #2,@(0x6:2,er1) ;0157691810d0 ++ shal.w #2,@er1+ ;01546d1810d0 ++ shal.w #2,@-er1 ;01576d1810d0 ++ shal.w #2,@+er1 ;01556d1810d0 ++ shal.w #2,@er1- ;01566d1810d0 ++ shal.w #2,@(0x1234:16,er1) ;01546f18123410d0 ++ shal.w #2,@(0x12345678:32,er1) ;78146b281234567810d0 ++ shal.w #2,@(0x1234:16,r2l.b) ;01556f28123410d0 ++ shal.w #2,@(0x1234:16,r2.w) ;01566f28123410d0 ++ shal.w #2,@(0x1234:16,er2.l) ;01576f28123410d0 ++ shal.w #2,@(0x12345678:32,r2l.b) ;78256b281234567810d0 ++ shal.w #2,@(0x12345678:32,r2.w) ;78266b281234567810d0 ++ shal.w #2,@(0x12345678:32,er2.l) ;78276b281234567810d0 ++ shal.w #2,@0x1234:16 ;6b18123410d0 ++ shal.w #2,@0x12345678:32 ;6b381234567810d0 ++ ++ shal.l #2,er1 ;10f1 ++ shal.l #2,@er1 ;0104691810f0 ++ shal.l #2,@(0xc:2,er1) ;0107691810f0 ++ shal.l #2,@er1+ ;01046d1810f0 ++ shal.l #2,@-er1 ;01076d1810f0 ++ shal.l #2,@+er1 ;01056d1810f0 ++ shal.l #2,@er1- ;01066d1810f0 ++ shal.l #2,@(0x1234:16,er1) ;01046f18123410f0 ++ shal.l #2,@(0x12345678:32,er1) ;78946b281234567810f0 ++ shal.l #2,@(0x1234:16,r2l.b) ;01056f28123410f0 ++ shal.l #2,@(0x1234:16,r2.w) ;01066f28123410f0 ++ shal.l #2,@(0x1234:16,er2.l) ;01076f28123410f0 ++ shal.l #2,@(0x12345678:32,r2l.b) ;78a56b281234567810f0 ++ shal.l #2,@(0x12345678:32,r2.w) ;78a66b281234567810f0 ++ shal.l #2,@(0x12345678:32,er2.l) ;78a76b281234567810f0 ++ shal.l #2,@0x1234:16 ;01046b08123410f0 ++ shal.l #2,@0x12345678:32 ;01046b281234567810f0 ++ ++ shar.b r1h ;1181 ++ shar.b @er1 ;7d101180 ++ shar.b @(0x3:2,er1) ;017768181180 ++ shar.b @er1+ ;01746c181180 ++ shar.b @-er1 ;01776c181180 ++ shar.b @+er1 ;01756c181180 ++ shar.b @er1- ;01766c181180 ++ shar.b @(0x1234:16,er1) ;01746e1812341180 ++ shar.b @(0x12345678:32,er1) ;78146a28123456781180 ++ shar.b @(0x1234:16,r2l.b) ;01756e2812341180 ++ shar.b @(0x1234:16,r2.w) ;01766e2812341180 ++ shar.b @(0x1234:16,er2.l) ;01776e2812341180 ++ shar.b @(0x12345678:32,r2l.b) ;78256a28123456781180 ++ shar.b @(0x12345678:32,r2.w) ;78266a28123456781180 ++ shar.b @(0x12345678:32,er2.l) ;78276a28123456781180 ++ shar.b @0xffffff12:8 ;7f121180 ++ shar.b @0x1234:16 ;6a1812341180 ++ shar.b @0x12345678:32 ;6a38123456781180 ++ ++ shar.w r1 ;1191 ++ shar.w @er1 ;7d901190 ++ shar.w @(0x6:2,er1) ;015769181190 ++ shar.w @er1+ ;01546d181190 ++ shar.w @-er1 ;01576d181190 ++ shar.w @+er1 ;01556d181190 ++ shar.w @er1- ;01566d181190 ++ shar.w @(0x1234:16,er1) ;01546f1812341190 ++ shar.w @(0x12345678:32,er1) ;78146b28123456781190 ++ shar.w @(0x1234:16,r2l.b) ;01556f2812341190 ++ shar.w @(0x1234:16,r2.w) ;01566f2812341190 ++ shar.w @(0x1234:16,er2.l) ;01576f2812341190 ++ shar.w @(0x12345678:32,r2l.b) ;78256b28123456781190 ++ shar.w @(0x12345678:32,r2.w) ;78266b28123456781190 ++ shar.w @(0x12345678:32,er2.l) ;78276b28123456781190 ++ shar.w @0x1234:16 ;6b1812341190 ++ shar.w @0x12345678:32 ;6b38123456781190 ++ ++ shar.l er1 ;11b1 ++ shar.l @er1 ;0104691811b0 ++ shar.l @(0xc:2,er1) ;0107691811b0 ++ shar.l @er1+ ;01046d1811b0 ++ shar.l @-er1 ;01076d1811b0 ++ shar.l @+er1 ;01056d1811b0 ++ shar.l @er1- ;01066d1811b0 ++ shar.l @(0x1234:16,er1) ;01046f18123411b0 ++ shar.l @(0x12345678:32,er1) ;78946b281234567811b0 ++ shar.l @(0x1234:16,r2l.b) ;01056f28123411b0 ++ shar.l @(0x1234:16,r2.w) ;01066f28123411b0 ++ shar.l @(0x1234:16,er2.l) ;01076f28123411b0 ++ shar.l @(0x12345678:32,r2l.b) ;78a56b281234567811b0 ++ shar.l @(0x12345678:32,r2.w) ;78a66b281234567811b0 ++ shar.l @(0x12345678:32,er2.l) ;78a76b281234567811b0 ++ shar.l @0x1234:16 ;01046b08123411b0 ++ shar.l @0x12345678:32 ;01046b281234567811b0 ++ ++ shar.b #2,r1h ;11c1 ++ shar.b #2,@er1 ;7d1011c0 ++ shar.b #2,@(0x3:2,er1) ;0177681811c0 ++ shar.b #2,@er1+ ;01746c1811c0 ++ shar.b #2,@-er1 ;01776c1811c0 ++ shar.b #2,@+er1 ;01756c1811c0 ++ shar.b #2,@er1- ;01766c1811c0 ++ shar.b #2,@(0x1234:16,er1) ;01746e18123411c0 ++ shar.b #2,@(0x12345678:32,er1) ;78146a281234567811c0 ++ shar.b #2,@(0x1234:16,r2l.b) ;01756e28123411c0 ++ shar.b #2,@(0x1234:16,r2.w) ;01766e28123411c0 ++ shar.b #2,@(0x1234:16,er2.l) ;01776e28123411c0 ++ shar.b #2,@(0x12345678:32,r2l.b) ;78256a281234567811c0 ++ shar.b #2,@(0x12345678:32,r2.w) ;78266a281234567811c0 ++ shar.b #2,@(0x12345678:32,er2.l) ;78276a281234567811c0 ++ shar.b #2,@0xffffff12:8 ;7f1211c0 ++ shar.b #2,@0x1234:16 ;6a18123411c0 ++ shar.b #2,@0x12345678:32 ;6a381234567811c0 ++ ++ shar.w #2,r1 ;11d1 ++ shar.w #2,@er1 ;7d9011d0 ++ shar.w #2,@(0x6:2,er1) ;0157691811d0 ++ shar.w #2,@er1+ ;01546d1811d0 ++ shar.w #2,@-er1 ;01576d1811d0 ++ shar.w #2,@+er1 ;01556d1811d0 ++ shar.w #2,@er1- ;01566d1811d0 ++ shar.w #2,@(0x1234:16,er1) ;01546f18123411d0 ++ shar.w #2,@(0x12345678:32,er1) ;78146b281234567811d0 ++ shar.w #2,@(0x1234:16,r2l.b) ;01556f28123411d0 ++ shar.w #2,@(0x1234:16,r2.w) ;01566f28123411d0 ++ shar.w #2,@(0x1234:16,er2.l) ;01576f28123411d0 ++ shar.w #2,@(0x12345678:32,r2l.b) ;78256b281234567811d0 ++ shar.w #2,@(0x12345678:32,r2.w) ;78266b281234567811d0 ++ shar.w #2,@(0x12345678:32,er2.l) ;78276b281234567811d0 ++ shar.w #2,@0x1234:16 ;6b18123411d0 ++ shar.w #2,@0x12345678:32 ;6b381234567811d0 ++ ++ shar.l #2,er1 ;11f1 ++ shar.l #2,@er1 ;0104691811f0 ++ shar.l #2,@(0xc:2,er1) ;0107691811f0 ++ shar.l #2,@er1+ ;01046d1811f0 ++ shar.l #2,@-er1 ;01076d1811f0 ++ shar.l #2,@+er1 ;01056d1811f0 ++ shar.l #2,@er1- ;01066d1811f0 ++ shar.l #2,@(0x1234:16,er1) ;01046f18123411f0 ++ shar.l #2,@(0x12345678:32,er1) ;78946b281234567811f0 ++ shar.l #2,@(0x1234:16,r2l.b) ;01056f28123411f0 ++ shar.l #2,@(0x1234:16,r2.w) ;01066f28123411f0 ++ shar.l #2,@(0x1234:16,er2.l) ;01076f28123411f0 ++ shar.l #2,@(0x12345678:32,r2l.b) ;78a56b281234567811f0 ++ shar.l #2,@(0x12345678:32,r2.w) ;78a66b281234567811f0 ++ shar.l #2,@(0x12345678:32,er2.l) ;78a76b281234567811f0 ++ shar.l #2,@0x1234:16 ;01046b08123411f0 ++ shar.l #2,@0x12345678:32 ;01046b281234567811f0 ++ ++ rotxl.b r1h ;1201 ++ rotxl.b @er1 ;7d101200 ++ rotxl.b @(0x3:2,er1) ;017768181200 ++ rotxl.b @er1+ ;01746c181200 ++ rotxl.b @-er1 ;01776c181200 ++ rotxl.b @+er1 ;01756c181200 ++ rotxl.b @er1- ;01766c181200 ++ rotxl.b @(0x1234:16,er1) ;01746e1812341200 ++ rotxl.b @(0x12345678:32,er1) ;78146a28123456781200 ++ rotxl.b @(0x1234:16,r2l.b) ;01756e2812341200 ++ rotxl.b @(0x1234:16,r2.w) ;01766e2812341200 ++ rotxl.b @(0x1234:16,er2.l) ;01776e2812341200 ++ rotxl.b @(0x12345678:32,r2l.b) ;78256a28123456781200 ++ rotxl.b @(0x12345678:32,r2.w) ;78266a28123456781200 ++ rotxl.b @(0x12345678:32,er2.l) ;78276a28123456781200 ++ rotxl.b @0xffffff12:8 ;7f121200 ++ rotxl.b @0x1234:16 ;6a1812341200 ++ rotxl.b @0x12345678:32 ;6a38123456781200 ++ ++ rotxl.w r1 ;1211 ++ rotxl.w @er1 ;7d901210 ++ rotxl.w @(0x6:2,er1) ;015769181210 ++ rotxl.w @er1+ ;01546d181210 ++ rotxl.w @-er1 ;01576d181210 ++ rotxl.w @+er1 ;01556d181210 ++ rotxl.w @er1- ;01566d181210 ++ rotxl.w @(0x1234:16,er1) ;01546f1812341210 ++ rotxl.w @(0x12345678:32,er1) ;78146b28123456781210 ++ rotxl.w @(0x1234:16,r2l.b) ;01556f2812341210 ++ rotxl.w @(0x1234:16,r2.w) ;01566f2812341210 ++ rotxl.w @(0x1234:16,er2.l) ;01576f2812341210 ++ rotxl.w @(0x12345678:32,r2l.b) ;78256b28123456781210 ++ rotxl.w @(0x12345678:32,r2.w) ;78266b28123456781210 ++ rotxl.w @(0x12345678:32,er2.l) ;78276b28123456781210 ++ rotxl.w @0x1234:16 ;6b1812341210 ++ rotxl.w @0x12345678:32 ;6b38123456781210 ++ ++ rotxl.l er1 ;1231 ++ rotxl.l @er1 ;010469181230 ++ rotxl.l @(0xc:2,er1) ;010769181230 ++ rotxl.l @er1+ ;01046d181230 ++ rotxl.l @-er1 ;01076d181230 ++ rotxl.l @+er1 ;01056d181230 ++ rotxl.l @er1- ;01066d181230 ++ rotxl.l @(0x1234:16,er1) ;01046f1812341230 ++ rotxl.l @(0x12345678:32,er1) ;78946b28123456781230 ++ rotxl.l @(0x1234:16,r2l.b) ;01056f2812341230 ++ rotxl.l @(0x1234:16,r2.w) ;01066f2812341230 ++ rotxl.l @(0x1234:16,er2.l) ;01076f2812341230 ++ rotxl.l @(0x12345678:32,r2l.b) ;78a56b28123456781230 ++ rotxl.l @(0x12345678:32,r2.w) ;78a66b28123456781230 ++ rotxl.l @(0x12345678:32,er2.l) ;78a76b28123456781230 ++ rotxl.l @0x1234:16 ;01046b0812341230 ++ rotxl.l @0x12345678:32 ;01046b28123456781230 ++ ++ rotxl.b #2,r1h ;1241 ++ rotxl.b #2,@er1 ;7d101240 ++ rotxl.b #2,@(0x3:2,er1) ;017768181240 ++ rotxl.b #2,@er1+ ;01746c181240 ++ rotxl.b #2,@-er1 ;01776c181240 ++ rotxl.b #2,@+er1 ;01756c181240 ++ rotxl.b #2,@er1- ;01766c181240 ++ rotxl.b #2,@(0x1234:16,er1) ;01746e1812341240 ++ rotxl.b #2,@(0x12345678:32,er1) ;78146a28123456781240 ++ rotxl.b #2,@(0x1234:16,r2l.b) ;01756e2812341240 ++ rotxl.b #2,@(0x1234:16,r2.w) ;01766e2812341240 ++ rotxl.b #2,@(0x1234:16,er2.l) ;01776e2812341240 ++ rotxl.b #2,@(0x12345678:32,r2l.b) ;78256a28123456781240 ++ rotxl.b #2,@(0x12345678:32,r2.w) ;78266a28123456781240 ++ rotxl.b #2,@(0x12345678:32,er2.l) ;78276a28123456781240 ++ rotxl.b #2,@0xffffff12:8 ;7f121240 ++ rotxl.b #2,@0x1234:16 ;6a1812341240 ++ rotxl.b #2,@0x12345678:32 ;6a38123456781240 ++ ++ rotxl.w #2,r1 ;1251 ++ rotxl.w #2,@er1 ;7d901250 ++ rotxl.w #2,@(0x6:2,er1) ;015769181250 ++ rotxl.w #2,@er1+ ;01546d181250 ++ rotxl.w #2,@-er1 ;01576d181250 ++ rotxl.w #2,@+er1 ;01556d181250 ++ rotxl.w #2,@er1- ;01566d181250 ++ rotxl.w #2,@(0x1234:16,er1) ;01546f1812341250 ++ rotxl.w #2,@(0x12345678:32,er1) ;78146b28123456781250 ++ rotxl.w #2,@(0x1234:16,r2l.b) ;01556f2812341250 ++ rotxl.w #2,@(0x1234:16,r2.w) ;01566f2812341250 ++ rotxl.w #2,@(0x1234:16,er2.l) ;01576f2812341250 ++ rotxl.w #2,@(0x12345678:32,r2l.b) ;78256b28123456781250 ++ rotxl.w #2,@(0x12345678:32,r2.w) ;78266b28123456781250 ++ rotxl.w #2,@(0x12345678:32,er2.l) ;78276b28123456781250 ++ rotxl.w #2,@0x1234:16 ;6b1812341250 ++ rotxl.w #2,@0x12345678:32 ;6b38123456781250 ++ ++ rotxl.l #2,er1 ;1271 ++ rotxl.l #2,@er1 ;010469181270 ++ rotxl.l #2,@(0xc:2,er1) ;010769181270 ++ rotxl.l #2,@er1+ ;01046d181270 ++ rotxl.l #2,@-er1 ;01076d181270 ++ rotxl.l #2,@+er1 ;01056d181270 ++ rotxl.l #2,@er1- ;01066d181270 ++ rotxl.l #2,@(0x1234:16,er1) ;01046f1812341270 ++ rotxl.l #2,@(0x12345678:32,er1) ;78946b28123456781270 ++ rotxl.l #2,@(0x1234:16,r2l.b) ;01056f2812341270 ++ rotxl.l #2,@(0x1234:16,r2.w) ;01066f2812341270 ++ rotxl.l #2,@(0x1234:16,er2.l) ;01076f2812341270 ++ rotxl.l #2,@(0x12345678:32,r2l.b) ;78a56b28123456781270 ++ rotxl.l #2,@(0x12345678:32,r2.w) ;78a66b28123456781270 ++ rotxl.l #2,@(0x12345678:32,er2.l) ;78a76b28123456781270 ++ rotxl.l #2,@0x1234:16 ;01046b0812341270 ++ rotxl.l #2,@0x12345678:32 ;01046b28123456781270 ++ ++ rotxr.b r1h ;1301 ++ rotxr.b @er1 ;7d101300 ++ rotxr.b @(0x3:2,er1) ;017768181300 ++ rotxr.b @er1+ ;01746c181300 ++ rotxr.b @-er1 ;01776c181300 ++ rotxr.b @+er1 ;01756c181300 ++ rotxr.b @er1- ;01766c181300 ++ rotxr.b @(0x1234:16,er1) ;01746e1812341300 ++ rotxr.b @(0x12345678:32,er1) ;78146a28123456781300 ++ rotxr.b @(0x1234:16,r2l.b) ;01756e2812341300 ++ rotxr.b @(0x1234:16,r2.w) ;01766e2812341300 ++ rotxr.b @(0x1234:16,er2.l) ;01776e2812341300 ++ rotxr.b @(0x12345678:32,r2l.b) ;78256a28123456781300 ++ rotxr.b @(0x12345678:32,r2.w) ;78266a28123456781300 ++ rotxr.b @(0x12345678:32,er2.l) ;78276a28123456781300 ++ rotxr.b @0xffffff12:8 ;7f121300 ++ rotxr.b @0x1234:16 ;6a1812341300 ++ rotxr.b @0x12345678:32 ;6a38123456781300 ++ ++ rotxr.w r1 ;1311 ++ rotxr.w @er1 ;7d901310 ++ rotxr.w @(0x6:2,er1) ;015769181310 ++ rotxr.w @er1+ ;01546d181310 ++ rotxr.w @-er1 ;01576d181310 ++ rotxr.w @+er1 ;01556d181310 ++ rotxr.w @er1- ;01566d181310 ++ rotxr.w @(0x1234:16,er1) ;01546f1812341310 ++ rotxr.w @(0x12345678:32,er1) ;78146b28123456781310 ++ rotxr.w @(0x1234:16,r2l.b) ;01556f2812341310 ++ rotxr.w @(0x1234:16,r2.w) ;01566f2812341310 ++ rotxr.w @(0x1234:16,er2.l) ;01576f2812341310 ++ rotxr.w @(0x12345678:32,r2l.b) ;78256b28123456781310 ++ rotxr.w @(0x12345678:32,r2.w) ;78266b28123456781310 ++ rotxr.w @(0x12345678:32,er2.l) ;78276b28123456781310 ++ rotxr.w @0x1234:16 ;6b1812341310 ++ rotxr.w @0x12345678:32 ;6b38123456781310 ++ ++ rotxr.l er1 ;1331 ++ rotxr.l @er1 ;010469181330 ++ rotxr.l @(0xc:2,er1) ;010769181330 ++ rotxr.l @er1+ ;01046d181330 ++ rotxr.l @-er1 ;01076d181330 ++ rotxr.l @+er1 ;01056d181330 ++ rotxr.l @er1- ;01066d181330 ++ rotxr.l @(0x1234:16,er1) ;01046f1812341330 ++ rotxr.l @(0x12345678:32,er1) ;78946b28123456781330 ++ rotxr.l @(0x1234:16,r2l.b) ;01056f2812341330 ++ rotxr.l @(0x1234:16,r2.w) ;01066f2812341330 ++ rotxr.l @(0x1234:16,er2.l) ;01076f2812341330 ++ rotxr.l @(0x12345678:32,r2l.b) ;78a56b28123456781330 ++ rotxr.l @(0x12345678:32,r2.w) ;78a66b28123456781330 ++ rotxr.l @(0x12345678:32,er2.l) ;78a76b28123456781330 ++ rotxr.l @0x1234:16 ;01046b0812341330 ++ rotxr.l @0x12345678:32 ;01046b28123456781330 ++ ++ rotxr.b #2,r1h ;1341 ++ rotxr.b #2,@er1 ;7d101340 ++ rotxr.b #2,@(0x3:2,er1) ;017768181340 ++ rotxr.b #2,@er1+ ;01746c181340 ++ rotxr.b #2,@-er1 ;01776c181340 ++ rotxr.b #2,@+er1 ;01756c181340 ++ rotxr.b #2,@er1- ;01766c181340 ++ rotxr.b #2,@(0x1234:16,er1) ;01746e1812341340 ++ rotxr.b #2,@(0x12345678:32,er1) ;78146a28123456781340 ++ rotxr.b #2,@(0x1234:16,r2l.b) ;01756e2812341340 ++ rotxr.b #2,@(0x1234:16,r2.w) ;01766e2812341340 ++ rotxr.b #2,@(0x1234:16,er2.l) ;01776e2812341340 ++ rotxr.b #2,@(0x12345678:32,r2l.b) ;78256a28123456781340 ++ rotxr.b #2,@(0x12345678:32,r2.w) ;78266a28123456781340 ++ rotxr.b #2,@(0x12345678:32,er2.l) ;78276a28123456781340 ++ rotxr.b #2,@0xffffff12:8 ;7f121340 ++ rotxr.b #2,@0x1234:16 ;6a1812341340 ++ rotxr.b #2,@0x12345678:32 ;6a38123456781340 ++ ++ rotxr.w #2,r1 ;1351 ++ rotxr.w #2,@er1 ;7d901350 ++ rotxr.w #2,@(0x6:2,er1) ;015769181350 ++ rotxr.w #2,@er1+ ;01546d181350 ++ rotxr.w #2,@-er1 ;01576d181350 ++ rotxr.w #2,@+er1 ;01556d181350 ++ rotxr.w #2,@er1- ;01566d181350 ++ rotxr.w #2,@(0x1234:16,er1) ;01546f1812341350 ++ rotxr.w #2,@(0x12345678:32,er1) ;78146b28123456781350 ++ rotxr.w #2,@(0x1234:16,r2l.b) ;01556f2812341350 ++ rotxr.w #2,@(0x1234:16,r2.w) ;01566f2812341350 ++ rotxr.w #2,@(0x1234:16,er2.l) ;01576f2812341350 ++ rotxr.w #2,@(0x12345678:32,r2l.b) ;78256b28123456781350 ++ rotxr.w #2,@(0x12345678:32,r2.w) ;78266b28123456781350 ++ rotxr.w #2,@(0x12345678:32,er2.l) ;78276b28123456781350 ++ rotxr.w #2,@0x1234:16 ;6b1812341350 ++ rotxr.w #2,@0x12345678:32 ;6b38123456781350 ++ ++ rotxr.l #2,er1 ;1371 ++ rotxr.l #2,@er1 ;010469181370 ++ rotxr.l #2,@(0xc:2,er1) ;010769181370 ++ rotxr.l #2,@er1+ ;01046d181370 ++ rotxr.l #2,@-er1 ;01076d181370 ++ rotxr.l #2,@+er1 ;01056d181370 ++ rotxr.l #2,@er1- ;01066d181370 ++ rotxr.l #2,@(0x1234:16,er1) ;01046f1812341370 ++ rotxr.l #2,@(0x12345678:32,er1) ;78946b28123456781370 ++ rotxr.l #2,@(0x1234:16,r2l.b) ;01056f2812341370 ++ rotxr.l #2,@(0x1234:16,r2.w) ;01066f2812341370 ++ rotxr.l #2,@(0x1234:16,er2.l) ;01076f2812341370 ++ rotxr.l #2,@(0x12345678:32,r2l.b) ;78a56b28123456781370 ++ rotxr.l #2,@(0x12345678:32,r2.w) ;78a66b28123456781370 ++ rotxr.l #2,@(0x12345678:32,er2.l) ;78a76b28123456781370 ++ rotxr.l #2,@0x1234:16 ;01046b0812341370 ++ rotxr.l #2,@0x12345678:32 ;01046b28123456781370 ++ ++ rotl.b r1h ;1281 ++ rotl.b @er1 ;7d101280 ++ rotl.b @(0x3:2,er1) ;017768181280 ++ rotl.b @er1+ ;01746c181280 ++ rotl.b @-er1 ;01776c181280 ++ rotl.b @+er1 ;01756c181280 ++ rotl.b @er1- ;01766c181280 ++ rotl.b @(0x1234:16,er1) ;01746e1812341280 ++ rotl.b @(0x12345678:32,er1) ;78146a28123456781280 ++ rotl.b @(0x1234:16,r2l.b) ;01756e2812341280 ++ rotl.b @(0x1234:16,r2.w) ;01766e2812341280 ++ rotl.b @(0x1234:16,er2.l) ;01776e2812341280 ++ rotl.b @(0x12345678:32,r2l.b) ;78256a28123456781280 ++ rotl.b @(0x12345678:32,r2.w) ;78266a28123456781280 ++ rotl.b @(0x12345678:32,er2.l) ;78276a28123456781280 ++ rotl.b @0xffffff12:8 ;7f121280 ++ rotl.b @0x1234:16 ;6a1812341280 ++ rotl.b @0x12345678:32 ;6a38123456781280 ++ ++ rotl.w r1 ;1291 ++ rotl.w @er1 ;7d901290 ++ rotl.w @(0x6:2,er1) ;015769181290 ++ rotl.w @-er1 ;01576d181290 ++ rotl.w @er1+ ;01546d181290 ++ rotl.w @er1- ;01566d181290 ++ rotl.w @+er1 ;01556d181290 ++ rotl.w @(0x1234:16,er1) ;01546f1812341290 ++ rotl.w @(0x12345678:32,er1) ;78146b28123456781290 ++ rotl.w @(0x1234:16,r2l.b) ;01556f2812341290 ++ rotl.w @(0x1234:16,r2.w) ;01566f2812341290 ++ rotl.w @(0x1234:16,er2.l) ;01576f2812341290 ++ rotl.w @(0x12345678:32,r2l.b) ;78256b28123456781290 ++ rotl.w @(0x12345678:32,r2.w) ;78266b28123456781290 ++ rotl.w @(0x12345678:32,er2.l) ;78276b28123456781290 ++ rotl.w @0x1234:16 ;6b1812341290 ++ rotl.w @0x12345678:32 ;6b38123456781290 ++ ++ rotl.l er1 ;12b1 ++ rotl.l @er1 ;0104691812b0 ++ rotl.l @(0xc:2,er1) ;0107691812b0 ++ rotl.l @er1+ ;01046d1812b0 ++ rotl.l @-er1 ;01076d1812b0 ++ rotl.l @+er1 ;01056d1812b0 ++ rotl.l @er1- ;01066d1812b0 ++ rotl.l @(0x1234:16,er1) ;01046f18123412b0 ++ rotl.l @(0x12345678:32,er1) ;78946b281234567812b0 ++ rotl.l @(0x1234:16,r2l.b) ;01056f28123412b0 ++ rotl.l @(0x1234:16,r2.w) ;01066f28123412b0 ++ rotl.l @(0x1234:16,er2.l) ;01076f28123412b0 ++ rotl.l @(0x12345678:32,r2l.b) ;78a56b281234567812b0 ++ rotl.l @(0x12345678:32,r2.w) ;78a66b281234567812b0 ++ rotl.l @(0x12345678:32,er2.l) ;78a76b281234567812b0 ++ rotl.l @0x1234:16 ;01046b08123412b0 ++ rotl.l @0x12345678:32 ;01046b281234567812b0 ++ ++ rotl.b #2,r1h ;12c1 ++ rotl.b #2,@er1 ;7d1012c0 ++ rotl.b #2,@(0x3:2,er1) ;0177681812c0 ++ rotl.b #2,@er1+ ;01746c1812c0 ++ rotl.b #2,@-er1 ;01776c1812c0 ++ rotl.b #2,@+er1 ;01756c1812c0 ++ rotl.b #2,@er1- ;01766c1812c0 ++ rotl.b #2,@(0x1234:16,er1) ;01746e18123412c0 ++ rotl.b #2,@(0x12345678:32,er1) ;78146a281234567812c0 ++ rotl.b #2,@(0x1234:16,r2l.b) ;01756e28123412c0 ++ rotl.b #2,@(0x1234:16,r2.w) ;01766e28123412c0 ++ rotl.b #2,@(0x1234:16,er2.l) ;01776e28123412c0 ++ rotl.b #2,@(0x12345678:32,r2l.b) ;78256a281234567812c0 ++ rotl.b #2,@(0x12345678:32,r2.w) ;78266a281234567812c0 ++ rotl.b #2,@(0x12345678:32,er2.l) ;78276a281234567812c0 ++ rotl.b #2,@0xffffff12:8 ;7f1212c0 ++ rotl.b #2,@0x1234:16 ;6a18123412c0 ++ rotl.b #2,@0x12345678:32 ;6a381234567812c0 ++ ++ rotl.w #2,r1 ;12d1 ++ rotl.w #2,@er1 ;7d9012d0 ++ rotl.w #2,@(0x6:2,er1) ;0157691812d0 ++ rotl.w #2,@er1+ ;01546d1812d0 ++ rotl.w #2,@-er1 ;01576d1812d0 ++ rotl.w #2,@+er1 ;01556d1812d0 ++ rotl.w #2,@er1- ;01566d1812d0 ++ rotl.w #2,@(0x1234:16,er1) ;01546f18123412d0 ++ rotl.w #2,@(0x12345678:32,er1) ;78146b281234567812d0 ++ rotl.w #2,@(0x1234:16,r2l.b) ;01556f28123412d0 ++ rotl.w #2,@(0x1234:16,r2.w) ;01566f28123412d0 ++ rotl.w #2,@(0x1234:16,er2.l) ;01576f28123412d0 ++ rotl.w #2,@(0x12345678:32,r2l.b) ;78256b281234567812d0 ++ rotl.w #2,@(0x12345678:32,r2.w) ;78266b281234567812d0 ++ rotl.w #2,@(0x12345678:32,er2.l) ;78276b281234567812d0 ++ rotl.w #2,@0x1234:16 ;6b18123412d0 ++ rotl.w #2,@0x12345678:32 ;6b381234567812d0 ++ ++ rotl.l #2,er1 ;12f1 ++ rotl.l #2,@er1 ;0104691812f0 ++ rotl.l #2,@(0xc:2,er1) ;0107691812f0 ++ rotl.l #2,@er1+ ;01046d1812f0 ++ rotl.l #2,@-er1 ;01076d1812f0 ++ rotl.l #2,@+er1 ;01056d1812f0 ++ rotl.l #2,@er1- ;01066d1812f0 ++ rotl.l #2,@(0x1234:16,er1) ;01046f18123412f0 ++ rotl.l #2,@(0x12345678:32,er1) ;78946b281234567812f0 ++ rotl.l #2,@(0x1234:16,r2l.b) ;01056f28123412f0 ++ rotl.l #2,@(0x1234:16,r2.w) ;01066f28123412f0 ++ rotl.l #2,@(0x1234:16,er2.l) ;01076f28123412f0 ++ rotl.l #2,@(0x12345678:32,r2l.b) ;78a56b281234567812f0 ++ rotl.l #2,@(0x12345678:32,r2.w) ;78a66b281234567812f0 ++ rotl.l #2,@(0x12345678:32,er2.l) ;78a76b281234567812f0 ++ rotl.l #2,@0x1234:16 ;01046b08123412f0 ++ rotl.l #2,@0x12345678:32 ;01046b281234567812f0 ++ ++ rotr.b r1h ;1381 ++ rotr.b @er1 ;7d101380 ++ rotr.b @(0x3:2,er1) ;017768181380 ++ rotr.b @er1+ ;01746c181380 ++ rotr.b @-er1 ;01776c181380 ++ rotr.b @+er1 ;01756c181380 ++ rotr.b @er1- ;01766c181380 ++ rotr.b @(0x1234:16,er1) ;01746e1812341380 ++ rotr.b @(0x12345678:32,er1) ;78146a28123456781380 ++ rotr.b @(0x1234:16,r2l.b) ;01756e2812341380 ++ rotr.b @(0x1234:16,r2.w) ;01766e2812341380 ++ rotr.b @(0x1234:16,er2.l) ;01776e2812341380 ++ rotr.b @(0x12345678:32,r2l.b) ;78256a28123456781380 ++ rotr.b @(0x12345678:32,r2.w) ;78266a28123456781380 ++ rotr.b @(0x12345678:32,er2.l) ;78276a28123456781380 ++ rotr.b @0xffffff12:8 ;7f121380 ++ rotr.b @0x1234:16 ;6a1812341380 ++ rotr.b @0x12345678:32 ;6a38123456781380 ++ ++ rotr.w r1 ;1391 ++ rotr.w @er1 ;7d901390 ++ rotr.w @(0x6:2,er1) ;015769181390 ++ rotr.w @-er1 ;01576d181390 ++ rotr.w @er1+ ;01546d181390 ++ rotr.w @er1- ;01566d181390 ++ rotr.w @+er1 ;01556d181390 ++ rotr.w @(0x1234:16,er1) ;01546f1812341390 ++ rotr.w @(0x12345678:32,er1) ;78146b28123456781390 ++ rotr.w @(0x1234:16,r2l.b) ;01556f2812341390 ++ rotr.w @(0x1234:16,r2.w) ;01566f2812341390 ++ rotr.w @(0x1234:16,er2.l) ;01576f2812341390 ++ rotr.w @(0x12345678:32,r2l.b) ;78256b28123456781390 ++ rotr.w @(0x12345678:32,r2.w) ;78266b28123456781390 ++ rotr.w @(0x12345678:32,er2.l) ;78276b28123456781390 ++ rotr.w @0x1234:16 ;6b1812341390 ++ rotr.w @0x12345678:32 ;6b38123456781390 ++ ++ rotr.l er1 ;13b1 ++ rotr.l @er1 ;0104691813b0 ++ rotr.l @(0xc:2,er1) ;0107691813b0 ++ rotr.l @er1+ ;01046d1813b0 ++ rotr.l @-er1 ;01076d1813b0 ++ rotr.l @+er1 ;01056d1813b0 ++ rotr.l @er1- ;01066d1813b0 ++ rotr.l @(0x1234:16,er1) ;01046f18123413b0 ++ rotr.l @(0x12345678:32,er1) ;78946b281234567813b0 ++ rotr.l @(0x1234:16,r2l.b) ;01056f28123413b0 ++ rotr.l @(0x1234:16,r2.w) ;01066f28123413b0 ++ rotr.l @(0x1234:16,er2.l) ;01076f28123413b0 ++ rotr.l @(0x12345678:32,r2l.b) ;78a56b281234567813b0 ++ rotr.l @(0x12345678:32,r2.w) ;78a66b281234567813b0 ++ rotr.l @(0x12345678:32,er2.l) ;78a76b281234567813b0 ++ rotr.l @0x1234:16 ;01046b08123413b0 ++ rotr.l @0x12345678:32 ;01046b281234567813b0 ++ ++ rotr.b #2,r1h ;13c1 ++ rotr.b #2,@er1 ;7d1013c0 ++ rotr.b #2,@(0x3:2,er1) ;0177681813c0 ++ rotr.b #2,@er1+ ;01746c1813c0 ++ rotr.b #2,@-er1 ;01776c1813c0 ++ rotr.b #2,@+er1 ;01756c1813c0 ++ rotr.b #2,@er1- ;01766c1813c0 ++ rotr.b #2,@(0x1234:16,er1) ;01746e18123413c0 ++ rotr.b #2,@(0x12345678:32,er1) ;78146a281234567813c0 ++ rotr.b #2,@(0x1234:16,r2l.b) ;01756e28123413c0 ++ rotr.b #2,@(0x1234:16,r2.w) ;01766e28123413c0 ++ rotr.b #2,@(0x1234:16,er2.l) ;01776e28123413c0 ++ rotr.b #2,@(0x12345678:32,r2l.b) ;78256a281234567813c0 ++ rotr.b #2,@(0x12345678:32,r2.w) ;78266a281234567813c0 ++ rotr.b #2,@(0x12345678:32,er2.l) ;78276a281234567813c0 ++ rotr.b #2,@0xffffff12:8 ;7f1213c0 ++ rotr.b #2,@0x1234:16 ;6a18123413c0 ++ rotr.b #2,@0x12345678:32 ;6a381234567813c0 ++ ++ rotr.w #2,r1 ;13d1 ++ rotr.w #2,@er1 ;7d9013d0 ++ rotr.w #2,@(0x6:2,er1) ;0157691813d0 ++ rotr.w #2,@er1+ ;01546d1813d0 ++ rotr.w #2,@-er1 ;01576d1813d0 ++ rotr.w #2,@+er1 ;01556d1813d0 ++ rotr.w #2,@er1- ;01566d1813d0 ++ rotr.w #2,@(0x1234:16,er1) ;01546f18123413d0 ++ rotr.w #2,@(0x12345678:32,er1) ;78146b281234567813d0 ++ rotr.w #2,@(0x1234:16,r2l.b) ;01556f28123413d0 ++ rotr.w #2,@(0x1234:16,r2.w) ;01566f28123413d0 ++ rotr.w #2,@(0x1234:16,er2.l) ;01576f28123413d0 ++ rotr.w #2,@(0x12345678:32,r2l.b) ;78256b281234567813d0 ++ rotr.w #2,@(0x12345678:32,r2.w) ;78266b281234567813d0 ++ rotr.w #2,@(0x12345678:32,er2.l) ;78276b281234567813d0 ++ rotr.w #2,@0x1234:16 ;6b18123413d0 ++ rotr.w #2,@0x12345678:32 ;6b381234567813d0 ++ ++ rotr.l #2,er1 ;13f1 ++ rotr.l #2,@er1 ;0104691813f0 ++ rotr.l #2,@(0xc:2,er1) ;0107691813f0 ++ rotr.l #2,@er1+ ;01046d1813f0 ++ rotr.l #2,@-er1 ;01076d1813f0 ++ rotr.l #2,@+er1 ;01056d1813f0 ++ rotr.l #2,@er1- ;01066d1813f0 ++ rotr.l #2,@(0x1234:16,er1) ;01046f18123413f0 ++ rotr.l #2,@(0x12345678:32,er1) ;78946b281234567813f0 ++ rotr.l #2,@(0x1234:16,r2l.b) ;01056f28123413f0 ++ rotr.l #2,@(0x1234:16,r2.w) ;01066f28123413f0 ++ rotr.l #2,@(0x1234:16,er2.l) ;01076f28123413f0 ++ rotr.l #2,@(0x12345678:32,r2l.b) ;78a56b281234567813f0 ++ rotr.l #2,@(0x12345678:32,r2.w) ;78a66b281234567813f0 ++ rotr.l #2,@(0x12345678:32,er2.l) ;78a76b281234567813f0 ++ rotr.l #2,@0x1234:16 ;01046b08123413f0 ++ rotr.l #2,@0x12345678:32 ;01046b281234567813f0 ++ ++ .end diff --git a/gas/testsuite/gas/h8300/t12_bit.exp b/gas/testsuite/gas/h8300/t12_bit.exp new file mode 100644 -index 0000000..09ab625 +index 0000000..1b7fc1c --- /dev/null +++ b/gas/testsuite/gas/h8300/t12_bit.exp -@@ -0,0 +1,599 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,598 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1186315,193 +1193485,192 @@ index 0000000..09ab625 + diff --git a/gas/testsuite/gas/h8300/t12_bit.s b/gas/testsuite/gas/h8300/t12_bit.s new file mode 100644 -index 0000000..7075628 +index 0000000..e02cb2d --- /dev/null +++ b/gas/testsuite/gas/h8300/t12_bit.s @@ -0,0 +1,175 @@ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+;bit -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ .h8300sx -+ .text -+_start: -+ bset #0x7,r1h ;7071 -+ bset #0x7,@er1 ;7d107070 -+ bset #0x7,@0xffffff12:8 ;7f127070 -+ bset #0x7,@0x1234:16 ;6a1812347070 -+ bset #0x7,@0x12345678:32 ;6a38123456787070 -+ -+ bset r3h,r1h ;6031 -+ bset r3h,@er1 ;7d106030 -+ bset r3h,@0xffffff12:8 ;7f126030 -+ bset r3h,@0x1234:16 ;6a1812346030 -+ bset r3h,@0x12345678:32 ;6a38123456786030 -+ -+ bset/eq #0x7,@er1 ;7d107077 -+ bset/eq #0x7,@0xffffff12:8 ;7f127077 -+ bset/eq #0x7,@0x1234:16 ;6a1812347077 -+ bset/eq #0x7,@0x12345678:32 ;6a38123456787077 -+ -+ bset/eq r3h,@er1 ;7d106037 -+ bset/eq r3h,@0xffffff12:8 ;7f126037 -+ bset/eq r3h,@0x1234:16 ;6a1812346037 -+ bset/eq r3h,@0x12345678:32 ;6a38123456786037 -+ -+ bset/ne #0x7,@er1 ;7d107076 -+ bset/ne #0x7,@0xffffff12:8 ;7f127076 -+ bset/ne #0x7,@0x1234:16 ;6a1812347076 -+ bset/ne #0x7,@0x12345678:32 ;6a38123456787076 -+ -+ bset/ne r3h,@er1 ;7d106036 -+ bset/ne r3h,@0xffffff12:8 ;7f126036 -+ bset/ne r3h,@0x1234:16 ;6a1812346036 -+ bset/ne r3h,@0x12345678:32 ;6a38123456786036 -+ -+ bnot #0x7,r1h ;7171 -+ bnot #0x7,@er1 ;7d107170 -+ bnot #0x7,@0xffffff12:8 ;7f127170 -+ bnot #0x7,@0x1234:16 ;6a1812347170 -+ bnot #0x7,@0x12345678:32 ;6a38123456787170 -+ -+ bnot r3h,r1h ;6131 -+ bnot r3h,@er1 ;7d106130 -+ bnot r3h,@0xffffff12:8 ;7f126130 -+ bnot r3h,@0x1234:16 ;6a1812346130 -+ bnot r3h,@0x12345678:32 ;6a38123456786130 -+ -+ bclr #0x7,r1h ;7271 -+ bclr #0x7,@er1 ;7d107270 -+ bclr #0x7,@0xffffff12:8 ;7f127270 -+ bclr #0x7,@0x1234:16 ;6a1812347270 -+ bclr #0x7,@0x12345678:32 ;6a38123456787270 -+ -+ bclr r3h,r1h ;6231 -+ bclr r3h,@er1 ;7d106230 -+ bclr r3h,@0xffffff12:8 ;7f126230 -+ bclr r3h,@0x1234:16 ;6a1812346230 -+ bclr r3h,@0x12345678:32 ;6a38123456786230 -+ -+ bclr/eq #0x7,@er1 ;7d107277 -+ bclr/eq #0x7,@0xffffff12:8 ;7f127277 -+ bclr/eq #0x7,@0x1234:16 ;6a1812347277 -+ bclr/eq #0x7,@0x12345678:32 ;6a38123456787277 -+ -+ bclr/eq r3h,@er1 ;7d106237 -+ bclr/eq r3h,@0xffffff12:8 ;7f126237 -+ bclr/eq r3h,@0x1234:16 ;6a1812346237 -+ bclr/eq r3h,@0x12345678:32 ;6a38123456786237 -+ -+ bclr/ne #0x7,@er1 ;7d107276 -+ bclr/ne #0x7,@0xffffff12:8 ;7f127276 -+ bclr/ne #0x7,@0x1234:16 ;6a1812347276 -+ bclr/ne #0x7,@0x12345678:32 ;6a38123456787276 -+ -+ bclr/ne r3h,@er1 ;7d106236 -+ bclr/ne r3h,@0xffffff12:8 ;7f126236 -+ bclr/ne r3h,@0x1234:16 ;6a1812346236 -+ bclr/ne r3h,@0x12345678:32 ;6a38123456786236 -+ -+ btst #0x7,r1h ;7371 -+ btst #0x7,@er1 ;7c107370 -+ btst #0x7,@0xffffff12:8 ;7e127370 -+ btst #0x7,@0x1234:16 ;6a1012347370 -+ btst #0x7,@0x12345678:32 ;6a30123456787370 -+ -+ btst r3h,r1h ;6331 -+ btst r3h,@er1 ;7c106330 -+ btst r3h,@0xffffff12:8 ;7e126330 -+ btst r3h,@0x1234:16 ;6a1012346330 -+ btst r3h,@0x12345678:32 ;6a30123456786330 -+ -+ bor #0x7,r1h ;7471 -+ bor #0x7,@er1 ;7c107470 -+ bor #0x7,@0xffffff12:8 ;7e127470 -+ bor #0x7,@0x1234:16 ;6a1012347470 -+ bor #0x7,@0x12345678:32 ;6a30123456787470 -+ -+ bior #0x7,r1h ;74f1 -+ bior #0x7,@er1 ;7c1074f0 -+ bior #0x7,@0xffffff12:8 ;7e1274f0 -+ bior #0x7,@0x1234:16 ;6a10123474f0 -+ bior #0x7,@0x12345678:32 ;6a301234567874f0 -+ -+ bxor #0x7,r1h ;7571 -+ bxor #0x7,@er1 ;7c107570 -+ bxor #0x7,@0xffffff12:8 ;7e127570 -+ bxor #0x7,@0x1234:16 ;6a1012347570 -+ bxor #0x7,@0x12345678:32 ;6a30123456787570 -+ -+ bixor #0x7,r1h ;75f1 -+ bixor #0x7,@er1 ;7c1075f0 -+ bixor #0x7,@0xffffff12:8 ;7e1275f0 -+ bixor #0x7,@0x1234:16 ;6a10123475f0 -+ bixor #0x7,@0x12345678:32 ;6a301234567875f0 -+ -+ band #0x7,r1h ;7671 -+ band #0x7,@er1 ;7c107670 -+ band #0x7,@0xffffff12:8 ;7e127670 -+ band #0x7,@0x1234:16 ;6a1012347670 -+ band #0x7,@0x12345678:32 ;6a30123456787670 -+ -+ biand #0x7,r1h ;76f1 -+ biand #0x7,@er1 ;7c1076f0 -+ biand #0x7,@0xffffff12:8 ;7e1276f0 -+ biand #0x7,@0x1234:16 ;6a10123476f0 -+ biand #0x7,@0x12345678:32 ;6a301234567876f0 -+ -+ bld #0x7,r1h ;7771 -+ bld #0x7,@er1 ;7c107770 -+ bld #0x7,@0xffffff12:8 ;7e127770 -+ bld #0x7,@0x1234:16 ;6a1012347770 -+ bld #0x7,@0x12345678:32 ;6a30123456787770 -+ -+ bild #0x7,r1h ;77f1 -+ bild #0x7,@er1 ;7c1077f0 -+ bild #0x7,@0xffffff12:8 ;7e1277f0 -+ bild #0x7,@0x1234:16 ;6a10123477f0 -+ bild #0x7,@0x12345678:32 ;6a301234567877f0 -+ -+ bst #0x7,r1h ;6771 -+ bst #0x7,@er1 ;7d106770 -+ bst #0x7,@0xffffff12:8 ;7f126770 -+ bst #0x7,@0x1234:16 ;6a1812346770 -+ bst #0x7,@0x12345678:32 ;6a38123456786770 -+ -+ bstz #0x7,@er1 ;7d106777 -+ bstz #0x7,@0xffffff12:8 ;7f126777 -+ bstz #0x7,@0x1234:16 ;6a1812346777 -+ bstz #0x7,@0x12345678:32 ;6a38123456786777 -+ -+ bist #0x7,r1h ;67f1 -+ bist #0x7,@er1 ;7d1067f0 -+ bist #0x7,@0xffffff12:8 ;7f1267f0 -+ bist #0x7,@0x1234:16 ;6a18123467f0 -+ bist #0x7,@0x12345678:32 ;6a381234567867f0 -+ -+ bistz #0x7,@er1 ;7d1067f7 -+ bistz #0x7,@0xffffff12:8 ;7f1267f7 -+ bistz #0x7,@0x1234:16 ;6a18123467f7 -+ bistz #0x7,@0x12345678:32 ;6a381234567867f7 -+ -+ bfld #0x34:8,@er1,r3h ;7c10f334 -+ bfld #0x34:8,@0xffffff12:8,r3h ;7e12f334 -+ bfld #0x34:8,@0x1234:16,r3h ;6a101234f334 -+ bfld #0x34:8,@0x12345678:32,r3h ;6a3012345678f334 -+ -+ bfst r3h,#0x34:8,@er1 ;7d10f334 -+ bfst r3h,#0x34:8,@0xffffff12:8 ;7f12f334 -+ bfst r3h,#0x34:8,@0x1234:16 ;6a181234f334 -+ bfst r3h,#0x34:8,@0x12345678:32 ;6a3812345678f334 -+ -+ .end ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;bit ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ .h8300sx ++ .text ++_start: ++ bset #0x7,r1h ;7071 ++ bset #0x7,@er1 ;7d107070 ++ bset #0x7,@0xffffff12:8 ;7f127070 ++ bset #0x7,@0x1234:16 ;6a1812347070 ++ bset #0x7,@0x12345678:32 ;6a38123456787070 ++ ++ bset r3h,r1h ;6031 ++ bset r3h,@er1 ;7d106030 ++ bset r3h,@0xffffff12:8 ;7f126030 ++ bset r3h,@0x1234:16 ;6a1812346030 ++ bset r3h,@0x12345678:32 ;6a38123456786030 ++ ++ bset/eq #0x7,@er1 ;7d107077 ++ bset/eq #0x7,@0xffffff12:8 ;7f127077 ++ bset/eq #0x7,@0x1234:16 ;6a1812347077 ++ bset/eq #0x7,@0x12345678:32 ;6a38123456787077 ++ ++ bset/eq r3h,@er1 ;7d106037 ++ bset/eq r3h,@0xffffff12:8 ;7f126037 ++ bset/eq r3h,@0x1234:16 ;6a1812346037 ++ bset/eq r3h,@0x12345678:32 ;6a38123456786037 ++ ++ bset/ne #0x7,@er1 ;7d107076 ++ bset/ne #0x7,@0xffffff12:8 ;7f127076 ++ bset/ne #0x7,@0x1234:16 ;6a1812347076 ++ bset/ne #0x7,@0x12345678:32 ;6a38123456787076 ++ ++ bset/ne r3h,@er1 ;7d106036 ++ bset/ne r3h,@0xffffff12:8 ;7f126036 ++ bset/ne r3h,@0x1234:16 ;6a1812346036 ++ bset/ne r3h,@0x12345678:32 ;6a38123456786036 ++ ++ bnot #0x7,r1h ;7171 ++ bnot #0x7,@er1 ;7d107170 ++ bnot #0x7,@0xffffff12:8 ;7f127170 ++ bnot #0x7,@0x1234:16 ;6a1812347170 ++ bnot #0x7,@0x12345678:32 ;6a38123456787170 ++ ++ bnot r3h,r1h ;6131 ++ bnot r3h,@er1 ;7d106130 ++ bnot r3h,@0xffffff12:8 ;7f126130 ++ bnot r3h,@0x1234:16 ;6a1812346130 ++ bnot r3h,@0x12345678:32 ;6a38123456786130 ++ ++ bclr #0x7,r1h ;7271 ++ bclr #0x7,@er1 ;7d107270 ++ bclr #0x7,@0xffffff12:8 ;7f127270 ++ bclr #0x7,@0x1234:16 ;6a1812347270 ++ bclr #0x7,@0x12345678:32 ;6a38123456787270 ++ ++ bclr r3h,r1h ;6231 ++ bclr r3h,@er1 ;7d106230 ++ bclr r3h,@0xffffff12:8 ;7f126230 ++ bclr r3h,@0x1234:16 ;6a1812346230 ++ bclr r3h,@0x12345678:32 ;6a38123456786230 ++ ++ bclr/eq #0x7,@er1 ;7d107277 ++ bclr/eq #0x7,@0xffffff12:8 ;7f127277 ++ bclr/eq #0x7,@0x1234:16 ;6a1812347277 ++ bclr/eq #0x7,@0x12345678:32 ;6a38123456787277 ++ ++ bclr/eq r3h,@er1 ;7d106237 ++ bclr/eq r3h,@0xffffff12:8 ;7f126237 ++ bclr/eq r3h,@0x1234:16 ;6a1812346237 ++ bclr/eq r3h,@0x12345678:32 ;6a38123456786237 ++ ++ bclr/ne #0x7,@er1 ;7d107276 ++ bclr/ne #0x7,@0xffffff12:8 ;7f127276 ++ bclr/ne #0x7,@0x1234:16 ;6a1812347276 ++ bclr/ne #0x7,@0x12345678:32 ;6a38123456787276 ++ ++ bclr/ne r3h,@er1 ;7d106236 ++ bclr/ne r3h,@0xffffff12:8 ;7f126236 ++ bclr/ne r3h,@0x1234:16 ;6a1812346236 ++ bclr/ne r3h,@0x12345678:32 ;6a38123456786236 ++ ++ btst #0x7,r1h ;7371 ++ btst #0x7,@er1 ;7c107370 ++ btst #0x7,@0xffffff12:8 ;7e127370 ++ btst #0x7,@0x1234:16 ;6a1012347370 ++ btst #0x7,@0x12345678:32 ;6a30123456787370 ++ ++ btst r3h,r1h ;6331 ++ btst r3h,@er1 ;7c106330 ++ btst r3h,@0xffffff12:8 ;7e126330 ++ btst r3h,@0x1234:16 ;6a1012346330 ++ btst r3h,@0x12345678:32 ;6a30123456786330 ++ ++ bor #0x7,r1h ;7471 ++ bor #0x7,@er1 ;7c107470 ++ bor #0x7,@0xffffff12:8 ;7e127470 ++ bor #0x7,@0x1234:16 ;6a1012347470 ++ bor #0x7,@0x12345678:32 ;6a30123456787470 ++ ++ bior #0x7,r1h ;74f1 ++ bior #0x7,@er1 ;7c1074f0 ++ bior #0x7,@0xffffff12:8 ;7e1274f0 ++ bior #0x7,@0x1234:16 ;6a10123474f0 ++ bior #0x7,@0x12345678:32 ;6a301234567874f0 ++ ++ bxor #0x7,r1h ;7571 ++ bxor #0x7,@er1 ;7c107570 ++ bxor #0x7,@0xffffff12:8 ;7e127570 ++ bxor #0x7,@0x1234:16 ;6a1012347570 ++ bxor #0x7,@0x12345678:32 ;6a30123456787570 ++ ++ bixor #0x7,r1h ;75f1 ++ bixor #0x7,@er1 ;7c1075f0 ++ bixor #0x7,@0xffffff12:8 ;7e1275f0 ++ bixor #0x7,@0x1234:16 ;6a10123475f0 ++ bixor #0x7,@0x12345678:32 ;6a301234567875f0 ++ ++ band #0x7,r1h ;7671 ++ band #0x7,@er1 ;7c107670 ++ band #0x7,@0xffffff12:8 ;7e127670 ++ band #0x7,@0x1234:16 ;6a1012347670 ++ band #0x7,@0x12345678:32 ;6a30123456787670 ++ ++ biand #0x7,r1h ;76f1 ++ biand #0x7,@er1 ;7c1076f0 ++ biand #0x7,@0xffffff12:8 ;7e1276f0 ++ biand #0x7,@0x1234:16 ;6a10123476f0 ++ biand #0x7,@0x12345678:32 ;6a301234567876f0 ++ ++ bld #0x7,r1h ;7771 ++ bld #0x7,@er1 ;7c107770 ++ bld #0x7,@0xffffff12:8 ;7e127770 ++ bld #0x7,@0x1234:16 ;6a1012347770 ++ bld #0x7,@0x12345678:32 ;6a30123456787770 ++ ++ bild #0x7,r1h ;77f1 ++ bild #0x7,@er1 ;7c1077f0 ++ bild #0x7,@0xffffff12:8 ;7e1277f0 ++ bild #0x7,@0x1234:16 ;6a10123477f0 ++ bild #0x7,@0x12345678:32 ;6a301234567877f0 ++ ++ bst #0x7,r1h ;6771 ++ bst #0x7,@er1 ;7d106770 ++ bst #0x7,@0xffffff12:8 ;7f126770 ++ bst #0x7,@0x1234:16 ;6a1812346770 ++ bst #0x7,@0x12345678:32 ;6a38123456786770 ++ ++ bstz #0x7,@er1 ;7d106777 ++ bstz #0x7,@0xffffff12:8 ;7f126777 ++ bstz #0x7,@0x1234:16 ;6a1812346777 ++ bstz #0x7,@0x12345678:32 ;6a38123456786777 ++ ++ bist #0x7,r1h ;67f1 ++ bist #0x7,@er1 ;7d1067f0 ++ bist #0x7,@0xffffff12:8 ;7f1267f0 ++ bist #0x7,@0x1234:16 ;6a18123467f0 ++ bist #0x7,@0x12345678:32 ;6a381234567867f0 ++ ++ bistz #0x7,@er1 ;7d1067f7 ++ bistz #0x7,@0xffffff12:8 ;7f1267f7 ++ bistz #0x7,@0x1234:16 ;6a18123467f7 ++ bistz #0x7,@0x12345678:32 ;6a381234567867f7 ++ ++ bfld #0x34:8,@er1,r3h ;7c10f334 ++ bfld #0x34:8,@0xffffff12:8,r3h ;7e12f334 ++ bfld #0x34:8,@0x1234:16,r3h ;6a101234f334 ++ bfld #0x34:8,@0x12345678:32,r3h ;6a3012345678f334 ++ ++ bfst r3h,#0x34:8,@er1 ;7d10f334 ++ bfst r3h,#0x34:8,@0xffffff12:8 ;7f12f334 ++ bfst r3h,#0x34:8,@0x1234:16 ;6a181234f334 ++ bfst r3h,#0x34:8,@0x12345678:32 ;6a3812345678f334 ++ ++ .end diff --git a/gas/testsuite/gas/h8300/t13_otr.exp b/gas/testsuite/gas/h8300/t13_otr.exp new file mode 100644 -index 0000000..f83a8f3 +index 0000000..3750e99 --- /dev/null +++ b/gas/testsuite/gas/h8300/t13_otr.exp -@@ -0,0 +1,488 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,487 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1186990,172 +1194159,172 @@ index 0000000..f83a8f3 + diff --git a/gas/testsuite/gas/h8300/t13_otr.s b/gas/testsuite/gas/h8300/t13_otr.s new file mode 100644 -index 0000000..0dcd24c +index 0000000..5d97044 --- /dev/null +++ b/gas/testsuite/gas/h8300/t13_otr.s @@ -0,0 +1,159 @@ -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+;others -+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -+ .h8300sx -+ .text -+ .org 0x12 -+lab_12: -+ .org 0x1234 -+ .global _start -+_start: -+ bra 0x12+.+2 ;4012 -+ brn 0x12+.+2 ;4112 -+ bhi 0x12+.+2 ;4212 -+ bls 0x12+.+2 ;4312 -+ bcc 0x12+.+2 ;4412 -+ bcs 0x12+.+2 ;4512 -+ bne 0x12+.+2 ;4612 -+ beq 0x12+.+2 ;4712 -+ bvc 0x12+.+2 ;4812 -+ bvs 0x12+.+2 ;4912 -+ bpl 0x12+.+2 ;4a12 -+ bmi 0x12+.+2 ;4b12 -+ bge 0x12+.+2 ;4c12 -+ blt 0x12+.+2 ;4d12 -+ bgt 0x12+.+2 ;4e12 -+ ble 0x12+.+2 ;4f12 -+ -+ bra 0x1234+.+4 ;58001234 -+ brn 0x1234+.+4 ;58101234 -+ bhi 0x1234+.+4 ;58201234 -+ bls 0x1234+.+4 ;58301234 -+ bcc 0x1234+.+4 ;58401234 -+ bcs 0x1234+.+4 ;58501234 -+ bne 0x1234+.+4 ;58601234 -+ beq 0x1234+.+4 ;58701234 -+ bvc 0x1234+.+4 ;58801234 -+ bvs 0x1234+.+4 ;58901234 -+ bpl 0x1234+.+4 ;58a01234 -+ bmi 0x1234+.+4 ;58b01234 -+ bge 0x1234+.+4 ;58c01234 -+ blt 0x1234+.+4 ;58d01234 -+ bgt 0x1234+.+4 ;58e01234 -+ ble 0x1234+.+4 ;58f01234 -+ -+ bra/s 0x12+.+2 ;4013 -+ nop ;0000 -+ -+ bra/bc #0x7,@er2,0x12+.+4 ;7c204712 -+ bra/bc #0x7,@0xffffff9a:8,0x12+.+4 ;7e9a4712 -+ bra/bc #0x7,@0x1234:16,0x12+.+6 ;6a1012344712 -+ bra/bc #0x7,@0x12345678:32,0x12+.+8 ;6a30123456784712 -+ bra/bc #0x7,@er2,0x1234+.+6 ;7c2058701234 -+ bra/bc #0x7,@0xffffff12:8,0x1234+.+6 ;7e1258701234 -+ bra/bc #0x7,@0xffff9abc:16,0x1234+.+8 ;6a109abc58701234 -+ bra/bc #0x7,@0x12345678:32,0x1234+.+0xa ;6a301234567858701234 -+ -+ bra/bs #0x7,@er2,0x12+.+4 ;7c204f12 -+ bra/bs #0x7,@0xffffff9a:8,0x12+.+4 ;7e9a4f12 -+ bra/bs #0x7,@0x1234:16,0x12+.+6 ;6a1012344f12 -+ bra/bs #0x7,@0x12345678:32,0x12+.+8 ;6a30123456784f12 -+ bra/bs #0x7,@er2,0x1234+.+6 ;7c2058f01234 -+ bra/bs #0x7,@0xffffff12:8,0x1234+.+6 ;7e1258f01234 -+ bra/bs #0x7,@0xffff9abc:16,0x1234+.+8 ;6a109abc58f01234 -+ bra/bs #0x7,@0x12345678:32,0x1234+.+0xa ;6a301234567858f01234 -+ -+ bsr/bc #0x7,@er2,0x1234+.+6 ;7c205c701234 -+ bsr/bc #0x7,@0xffffff12:8,0x1234+.+6 ;7e125c701234 -+ bsr/bc #0x7,@0xffff9abc:16,0x1234+.+8 ;6a109abc5c701234 -+ bsr/bc #0x7,@0x12345678:32,0x1234+.+0xa ;6a30123456785c701234 -+ -+ bsr/bs #0x7,@er2,0x1234+.+6 ;7c205cf01234 -+ bsr/bs #0x7,@0xffffff12:8,0x1234+.+6 ;7e125cf01234 -+ bsr/bs #0x7,@0xffff9abc:16,0x1234+.+8 ;6a109abc5cf01234 -+ bsr/bs #0x7,@0x12345678:32,0x1234+.+0xa ;6a30123456785cf01234 -+ -+ bra r2l.b ;5925 -+ bra r2.w ;5926 -+ bra er2.l ;5927 -+ -+ bsr 0x12+.+2 ;5512 -+ bsr 0x1234+.+4 ;5c001234 -+ bsr r2l.b ;5d25 -+ bsr r2.w ;5d26 -+ bsr er2.l ;5d27 -+ -+ jmp @er2 ;5920 -+ jmp @0x123456:24 ;5a123456 -+ jmp @0x12345678:32 ;590812345678 -+ jmp @@0x12 ;5b12 -+ jmp @@0x234 ;598d -+ -+ jsr @er2 ;5d20 -+ jsr @0x123456:24 ;5e123456 -+ jsr @0x12345678:32 ;5d0812345678 -+ jsr @@0x12 ;5f12 -+ jsr @@0x234 ;5d8d -+ -+ rts ;5470 -+ rts/l er3 ;5403 -+ rts/l (er1-er2) ;5412 -+ rts/l (er2-er4) ;5424 -+ rts/l (er3-er6) ;5436 -+ -+ trapa #0x3 ;5730 -+ -+ rte ;5670 -+ rte/l er3 ;5603 -+ rte/l (er1-er2) ;5612 -+ rte/l (er2-er4) ;5624 -+ rte/l (er3-er6) ;5636 -+ -+ ldc.b #0x12:8,ccr ;0712 -+ ldc.b r3h,ccr ;0303 -+ ldc.w @er3,ccr ;01406930 -+ ldc.w @er3+,ccr ;01406d30 -+ ldc.w @(0x1234:16,er3),ccr ;01406f301234 -+ ldc.w @(0x12345678:32,er3),ccr ;014078306b2012345678 -+ ldc.w @0x1234:16,ccr ;01406b001234 -+ ldc.w @0x12345678:32,ccr ;01406b2012345678 -+ -+ ldc.b #0x12:8,exr ;01410712 -+ ldc.b r3h,exr ;0313 -+ ldc.w @er3,exr ;01416930 -+ ldc.w @er3+,exr ;01416d30 -+ ldc.w @(0x1234:16,er3),exr ;01416f301234 -+ ldc.w @(0x12345678:32,er3),exr ;014178306b2012345678 -+ ldc.w @0x1234:16,exr ;01416b001234 -+ ldc.w @0x12345678:32,exr ;01416b2012345678 -+ -+ stc.b ccr,r1h ;0201 -+ stc.w ccr,@er1 ;01406990 -+ stc.w ccr,@-er1 ;01406d90 -+ stc.w ccr,@(0x1234:16,er1) ;01406f901234 -+ stc.w ccr,@(0x12345678:32,er1) ;014078106ba012345678 -+ stc.w ccr,@0x1234:16 ;01406b801234 -+ stc.w ccr,@0x12345678:32 ;01406ba012345678 -+ -+ stc.b exr,r1h ;0211 -+ stc.w exr,@er1 ;01416990 -+ stc.w exr,@-er1 ;01416d90 -+ stc.w exr,@(0x1234:16,er1) ;01416f901234 -+ stc.w exr,@(0x12345678:32,er1) ;014178106ba012345678 -+ stc.w exr,@0x1234:16 ;01416b801234 -+ stc.w exr,@0x12345678:32 ;01416ba012345678 -+ -+ orc.b #0x12:8,ccr ;0412 -+ orc.b #0x12:8,exr ;01410412 -+ -+ xorc.b #0x12:8,ccr ;0512 -+ xorc.b #0x12:8,exr ;01410512 -+ -+ andc.b #0x12:8,ccr ;0612 -+ andc.b #0x12:8,exr ;01410612 -+ -+ sleep ;0180 -+ -+ nop ;0000 -+ -+ .end ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++;others ++;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ++ .h8300sx ++ .text ++ .org 0x12 ++lab_12: ++ .org 0x1234 ++ .global _start ++_start: ++ bra 0x12+.+2 ;4012 ++ brn 0x12+.+2 ;4112 ++ bhi 0x12+.+2 ;4212 ++ bls 0x12+.+2 ;4312 ++ bcc 0x12+.+2 ;4412 ++ bcs 0x12+.+2 ;4512 ++ bne 0x12+.+2 ;4612 ++ beq 0x12+.+2 ;4712 ++ bvc 0x12+.+2 ;4812 ++ bvs 0x12+.+2 ;4912 ++ bpl 0x12+.+2 ;4a12 ++ bmi 0x12+.+2 ;4b12 ++ bge 0x12+.+2 ;4c12 ++ blt 0x12+.+2 ;4d12 ++ bgt 0x12+.+2 ;4e12 ++ ble 0x12+.+2 ;4f12 ++ ++ bra 0x1234+.+4 ;58001234 ++ brn 0x1234+.+4 ;58101234 ++ bhi 0x1234+.+4 ;58201234 ++ bls 0x1234+.+4 ;58301234 ++ bcc 0x1234+.+4 ;58401234 ++ bcs 0x1234+.+4 ;58501234 ++ bne 0x1234+.+4 ;58601234 ++ beq 0x1234+.+4 ;58701234 ++ bvc 0x1234+.+4 ;58801234 ++ bvs 0x1234+.+4 ;58901234 ++ bpl 0x1234+.+4 ;58a01234 ++ bmi 0x1234+.+4 ;58b01234 ++ bge 0x1234+.+4 ;58c01234 ++ blt 0x1234+.+4 ;58d01234 ++ bgt 0x1234+.+4 ;58e01234 ++ ble 0x1234+.+4 ;58f01234 ++ ++ bra/s 0x12+.+2 ;4013 ++ nop ;0000 ++ ++ bra/bc #0x7,@er2,0x12+.+4 ;7c204712 ++ bra/bc #0x7,@0xffffff9a:8,0x12+.+4 ;7e9a4712 ++ bra/bc #0x7,@0x1234:16,0x12+.+6 ;6a1012344712 ++ bra/bc #0x7,@0x12345678:32,0x12+.+8 ;6a30123456784712 ++ bra/bc #0x7,@er2,0x1234+.+6 ;7c2058701234 ++ bra/bc #0x7,@0xffffff12:8,0x1234+.+6 ;7e1258701234 ++ bra/bc #0x7,@0xffff9abc:16,0x1234+.+8 ;6a109abc58701234 ++ bra/bc #0x7,@0x12345678:32,0x1234+.+0xa ;6a301234567858701234 ++ ++ bra/bs #0x7,@er2,0x12+.+4 ;7c204f12 ++ bra/bs #0x7,@0xffffff9a:8,0x12+.+4 ;7e9a4f12 ++ bra/bs #0x7,@0x1234:16,0x12+.+6 ;6a1012344f12 ++ bra/bs #0x7,@0x12345678:32,0x12+.+8 ;6a30123456784f12 ++ bra/bs #0x7,@er2,0x1234+.+6 ;7c2058f01234 ++ bra/bs #0x7,@0xffffff12:8,0x1234+.+6 ;7e1258f01234 ++ bra/bs #0x7,@0xffff9abc:16,0x1234+.+8 ;6a109abc58f01234 ++ bra/bs #0x7,@0x12345678:32,0x1234+.+0xa ;6a301234567858f01234 ++ ++ bsr/bc #0x7,@er2,0x1234+.+6 ;7c205c701234 ++ bsr/bc #0x7,@0xffffff12:8,0x1234+.+6 ;7e125c701234 ++ bsr/bc #0x7,@0xffff9abc:16,0x1234+.+8 ;6a109abc5c701234 ++ bsr/bc #0x7,@0x12345678:32,0x1234+.+0xa ;6a30123456785c701234 ++ ++ bsr/bs #0x7,@er2,0x1234+.+6 ;7c205cf01234 ++ bsr/bs #0x7,@0xffffff12:8,0x1234+.+6 ;7e125cf01234 ++ bsr/bs #0x7,@0xffff9abc:16,0x1234+.+8 ;6a109abc5cf01234 ++ bsr/bs #0x7,@0x12345678:32,0x1234+.+0xa ;6a30123456785cf01234 ++ ++ bra r2l.b ;5925 ++ bra r2.w ;5926 ++ bra er2.l ;5927 ++ ++ bsr 0x12+.+2 ;5512 ++ bsr 0x1234+.+4 ;5c001234 ++ bsr r2l.b ;5d25 ++ bsr r2.w ;5d26 ++ bsr er2.l ;5d27 ++ ++ jmp @er2 ;5920 ++ jmp @0x123456:24 ;5a123456 ++ jmp @0x12345678:32 ;590812345678 ++ jmp @@0x12 ;5b12 ++ jmp @@0x234 ;598d ++ ++ jsr @er2 ;5d20 ++ jsr @0x123456:24 ;5e123456 ++ jsr @0x12345678:32 ;5d0812345678 ++ jsr @@0x12 ;5f12 ++ jsr @@0x234 ;5d8d ++ ++ rts ;5470 ++ rts/l er3 ;5403 ++ rts/l (er1-er2) ;5412 ++ rts/l (er2-er4) ;5424 ++ rts/l (er3-er6) ;5436 ++ ++ trapa #0x3 ;5730 ++ ++ rte ;5670 ++ rte/l er3 ;5603 ++ rte/l (er1-er2) ;5612 ++ rte/l (er2-er4) ;5624 ++ rte/l (er3-er6) ;5636 ++ ++ ldc.b #0x12:8,ccr ;0712 ++ ldc.b r3h,ccr ;0303 ++ ldc.w @er3,ccr ;01406930 ++ ldc.w @er3+,ccr ;01406d30 ++ ldc.w @(0x1234:16,er3),ccr ;01406f301234 ++ ldc.w @(0x12345678:32,er3),ccr ;014078306b2012345678 ++ ldc.w @0x1234:16,ccr ;01406b001234 ++ ldc.w @0x12345678:32,ccr ;01406b2012345678 ++ ++ ldc.b #0x12:8,exr ;01410712 ++ ldc.b r3h,exr ;0313 ++ ldc.w @er3,exr ;01416930 ++ ldc.w @er3+,exr ;01416d30 ++ ldc.w @(0x1234:16,er3),exr ;01416f301234 ++ ldc.w @(0x12345678:32,er3),exr ;014178306b2012345678 ++ ldc.w @0x1234:16,exr ;01416b001234 ++ ldc.w @0x12345678:32,exr ;01416b2012345678 ++ ++ stc.b ccr,r1h ;0201 ++ stc.w ccr,@er1 ;01406990 ++ stc.w ccr,@-er1 ;01406d90 ++ stc.w ccr,@(0x1234:16,er1) ;01406f901234 ++ stc.w ccr,@(0x12345678:32,er1) ;014078106ba012345678 ++ stc.w ccr,@0x1234:16 ;01406b801234 ++ stc.w ccr,@0x12345678:32 ;01406ba012345678 ++ ++ stc.b exr,r1h ;0211 ++ stc.w exr,@er1 ;01416990 ++ stc.w exr,@-er1 ;01416d90 ++ stc.w exr,@(0x1234:16,er1) ;01416f901234 ++ stc.w exr,@(0x12345678:32,er1) ;014178106ba012345678 ++ stc.w exr,@0x1234:16 ;01416b801234 ++ stc.w exr,@0x12345678:32 ;01416ba012345678 ++ ++ orc.b #0x12:8,ccr ;0412 ++ orc.b #0x12:8,exr ;01410412 ++ ++ xorc.b #0x12:8,ccr ;0512 ++ xorc.b #0x12:8,exr ;01410512 ++ ++ andc.b #0x12:8,ccr ;0612 ++ andc.b #0x12:8,exr ;01410612 ++ ++ sleep ;0180 ++ ++ nop ;0000 ++ ++ .end diff --git a/gas/testsuite/gas/hppa/README b/gas/testsuite/gas/hppa/README new file mode 100644 -index 0000000..c9c2827 +index 0000000..e11bd97 --- /dev/null +++ b/gas/testsuite/gas/hppa/README @@ -0,0 +1,40 @@ @@ -1187194,7 +1194363,7 @@ index 0000000..c9c2827 +end up in this directory, they should be broken out into a new class of +tests. + -+Copyright (C) 2012 Free Software Foundation, Inc. ++Copyright (C) 2012-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -1187601,12 +1194770,11 @@ index 0000000..e45171c + addi,tsv,tc,ev 123,%r5,%r6 diff --git a/gas/testsuite/gas/hppa/basic/basic.exp b/gas/testsuite/gas/hppa/basic/basic.exp new file mode 100644 -index 0000000..b4193c3 +index 0000000..637ff00 --- /dev/null +++ b/gas/testsuite/gas/hppa/basic/basic.exp -@@ -0,0 +1,3847 @@ -+# Copyright (C) 1993, 1996, 1997, 1999, 2002, 2005, 2007 -+# Free Software Foundation, Inc. +@@ -0,0 +1,3846 @@ ++# Copyright (C) 1993-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1201856,12 +1209024,11 @@ index 0000000..2904603 + addc %r0,%r0,%r28 diff --git a/gas/testsuite/gas/hppa/parse/parse.exp b/gas/testsuite/gas/hppa/parse/parse.exp new file mode 100644 -index 0000000..b48b587 +index 0000000..dff0466 --- /dev/null +++ b/gas/testsuite/gas/hppa/parse/parse.exp -@@ -0,0 +1,228 @@ -+# Copyright (C) 1993, 1996, 1997, 1999, 2000, 2001, 2002, 2003, 2005, 2007, 2009 -+# Free Software Foundation, Inc. +@@ -0,0 +1,227 @@ ++# Copyright (C) 1993-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1202962,12 +1210129,11 @@ index 0000000..016d12d + .PROCEND diff --git a/gas/testsuite/gas/hppa/reloc/reloc.exp b/gas/testsuite/gas/hppa/reloc/reloc.exp new file mode 100644 -index 0000000..a773696 +index 0000000..10de967 --- /dev/null +++ b/gas/testsuite/gas/hppa/reloc/reloc.exp -@@ -0,0 +1,717 @@ -+# Copyright 1993, 1996, 1997, 2002, 2004, 2005, 2007 -+# Free Software Foundation, Inc. +@@ -0,0 +1,716 @@ ++# Copyright (C) 1993-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1207420,12 +1214586,11 @@ index 0000000..6e98eb2 + diff --git a/gas/testsuite/gas/hppa/unsorted/unsorted.exp b/gas/testsuite/gas/hppa/unsorted/unsorted.exp new file mode 100644 -index 0000000..92b3e58 +index 0000000..234ef17 --- /dev/null +++ b/gas/testsuite/gas/hppa/unsorted/unsorted.exp -@@ -0,0 +1,267 @@ -+# Copyright (C) 1993, 1997, 1999, 2000, 2002, 2004, 2005, 2007 -+# Free Software Foundation, Inc. +@@ -0,0 +1,266 @@ ++# Copyright (C) 1993-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1224247,10 +1231412,10 @@ index 0000000..4d3d13b + vpmovzxbq ymm4,[ecx] diff --git a/gas/testsuite/gas/i386/avx512cd-intel.d b/gas/testsuite/gas/i386/avx512cd-intel.d new file mode 100644 -index 0000000..f48a7dd +index 0000000..c690c3a --- /dev/null +++ b/gas/testsuite/gas/i386/avx512cd-intel.d -@@ -0,0 +1,180 @@ +@@ -0,0 +1,128 @@ +#as: +#objdump: -dwMintel +#name: i386 AVX512CD insns (Intel disassembly) @@ -1224318,32 +1231483,6 @@ index 0000000..f48a7dd +[ ]*[a-f0-9]+: 62 f2 fd 58 44 b2 00 04 00 00 vplzcntq zmm6,QWORD PTR \[edx\+0x400\]\{1to8\} +[ ]*[a-f0-9]+: 62 f2 fd 58 44 72 80 vplzcntq zmm6,QWORD PTR \[edx-0x400\]\{1to8\} +[ ]*[a-f0-9]+: 62 f2 fd 58 44 b2 f8 fb ff ff vplzcntq zmm6,QWORD PTR \[edx-0x408\]\{1to8\} -+[ ]*[a-f0-9]+: 62 f2 56 48 27 ec vptestnmd k5,zmm5,zmm4 -+[ ]*[a-f0-9]+: 62 f2 56 4f 27 ec vptestnmd k5\{k7\},zmm5,zmm4 -+[ ]*[a-f0-9]+: 62 f2 56 48 27 29 vptestnmd k5,zmm5,ZMMWORD PTR \[ecx\] -+[ ]*[a-f0-9]+: 62 f2 56 48 27 ac f4 c0 1d fe ff vptestnmd k5,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] -+[ ]*[a-f0-9]+: 62 f2 56 58 27 28 vptestnmd k5,zmm5,DWORD PTR \[eax\]\{1to16\} -+[ ]*[a-f0-9]+: 62 f2 56 48 27 6a 7f vptestnmd k5,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] -+[ ]*[a-f0-9]+: 62 f2 56 48 27 aa 00 20 00 00 vptestnmd k5,zmm5,ZMMWORD PTR \[edx\+0x2000\] -+[ ]*[a-f0-9]+: 62 f2 56 48 27 6a 80 vptestnmd k5,zmm5,ZMMWORD PTR \[edx-0x2000\] -+[ ]*[a-f0-9]+: 62 f2 56 48 27 aa c0 df ff ff vptestnmd k5,zmm5,ZMMWORD PTR \[edx-0x2040\] -+[ ]*[a-f0-9]+: 62 f2 56 58 27 6a 7f vptestnmd k5,zmm5,DWORD PTR \[edx\+0x1fc\]\{1to16\} -+[ ]*[a-f0-9]+: 62 f2 56 58 27 aa 00 02 00 00 vptestnmd k5,zmm5,DWORD PTR \[edx\+0x200\]\{1to16\} -+[ ]*[a-f0-9]+: 62 f2 56 58 27 6a 80 vptestnmd k5,zmm5,DWORD PTR \[edx-0x200\]\{1to16\} -+[ ]*[a-f0-9]+: 62 f2 56 58 27 aa fc fd ff ff vptestnmd k5,zmm5,DWORD PTR \[edx-0x204\]\{1to16\} -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 ec vptestnmq k5,zmm5,zmm4 -+[ ]*[a-f0-9]+: 62 f2 d6 4f 27 ec vptestnmq k5\{k7\},zmm5,zmm4 -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 29 vptestnmq k5,zmm5,ZMMWORD PTR \[ecx\] -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 ac f4 c0 1d fe ff vptestnmq k5,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] -+[ ]*[a-f0-9]+: 62 f2 d6 58 27 28 vptestnmq k5,zmm5,QWORD PTR \[eax\]\{1to8\} -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 6a 7f vptestnmq k5,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 aa 00 20 00 00 vptestnmq k5,zmm5,ZMMWORD PTR \[edx\+0x2000\] -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 6a 80 vptestnmq k5,zmm5,ZMMWORD PTR \[edx-0x2000\] -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 aa c0 df ff ff vptestnmq k5,zmm5,ZMMWORD PTR \[edx-0x2040\] -+[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 7f vptestnmq k5,zmm5,QWORD PTR \[edx\+0x3f8\]\{1to8\} -+[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa 00 04 00 00 vptestnmq k5,zmm5,QWORD PTR \[edx\+0x400\]\{1to8\} -+[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 80 vptestnmq k5,zmm5,QWORD PTR \[edx-0x400\]\{1to8\} -+[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa f8 fb ff ff vptestnmq k5,zmm5,QWORD PTR \[edx-0x408\]\{1to8\} +[ ]*[a-f0-9]+: 62 f2 7e 48 3a f6 vpbroadcastmw2d zmm6,k6 +[ ]*[a-f0-9]+: 62 f2 fe 48 2a f6 vpbroadcastmb2q zmm6,k6 +[ ]*[a-f0-9]+: 62 f2 7d 48 c4 f5 vpconflictd zmm6,zmm5 @@ -1224402,41 +1231541,15 @@ index 0000000..f48a7dd +[ ]*[a-f0-9]+: 62 f2 fd 58 44 b2 00 04 00 00 vplzcntq zmm6,QWORD PTR \[edx\+0x400\]\{1to8\} +[ ]*[a-f0-9]+: 62 f2 fd 58 44 72 80 vplzcntq zmm6,QWORD PTR \[edx-0x400\]\{1to8\} +[ ]*[a-f0-9]+: 62 f2 fd 58 44 b2 f8 fb ff ff vplzcntq zmm6,QWORD PTR \[edx-0x408\]\{1to8\} -+[ ]*[a-f0-9]+: 62 f2 56 48 27 ec vptestnmd k5,zmm5,zmm4 -+[ ]*[a-f0-9]+: 62 f2 56 4f 27 ec vptestnmd k5\{k7\},zmm5,zmm4 -+[ ]*[a-f0-9]+: 62 f2 56 48 27 29 vptestnmd k5,zmm5,ZMMWORD PTR \[ecx\] -+[ ]*[a-f0-9]+: 62 f2 56 48 27 ac f4 c0 1d fe ff vptestnmd k5,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] -+[ ]*[a-f0-9]+: 62 f2 56 58 27 28 vptestnmd k5,zmm5,DWORD PTR \[eax\]\{1to16\} -+[ ]*[a-f0-9]+: 62 f2 56 48 27 6a 7f vptestnmd k5,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] -+[ ]*[a-f0-9]+: 62 f2 56 48 27 aa 00 20 00 00 vptestnmd k5,zmm5,ZMMWORD PTR \[edx\+0x2000\] -+[ ]*[a-f0-9]+: 62 f2 56 48 27 6a 80 vptestnmd k5,zmm5,ZMMWORD PTR \[edx-0x2000\] -+[ ]*[a-f0-9]+: 62 f2 56 48 27 aa c0 df ff ff vptestnmd k5,zmm5,ZMMWORD PTR \[edx-0x2040\] -+[ ]*[a-f0-9]+: 62 f2 56 58 27 6a 7f vptestnmd k5,zmm5,DWORD PTR \[edx\+0x1fc\]\{1to16\} -+[ ]*[a-f0-9]+: 62 f2 56 58 27 aa 00 02 00 00 vptestnmd k5,zmm5,DWORD PTR \[edx\+0x200\]\{1to16\} -+[ ]*[a-f0-9]+: 62 f2 56 58 27 6a 80 vptestnmd k5,zmm5,DWORD PTR \[edx-0x200\]\{1to16\} -+[ ]*[a-f0-9]+: 62 f2 56 58 27 aa fc fd ff ff vptestnmd k5,zmm5,DWORD PTR \[edx-0x204\]\{1to16\} -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 ec vptestnmq k5,zmm5,zmm4 -+[ ]*[a-f0-9]+: 62 f2 d6 4f 27 ec vptestnmq k5\{k7\},zmm5,zmm4 -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 29 vptestnmq k5,zmm5,ZMMWORD PTR \[ecx\] -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 ac f4 c0 1d fe ff vptestnmq k5,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] -+[ ]*[a-f0-9]+: 62 f2 d6 58 27 28 vptestnmq k5,zmm5,QWORD PTR \[eax\]\{1to8\} -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 6a 7f vptestnmq k5,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 aa 00 20 00 00 vptestnmq k5,zmm5,ZMMWORD PTR \[edx\+0x2000\] -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 6a 80 vptestnmq k5,zmm5,ZMMWORD PTR \[edx-0x2000\] -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 aa c0 df ff ff vptestnmq k5,zmm5,ZMMWORD PTR \[edx-0x2040\] -+[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 7f vptestnmq k5,zmm5,QWORD PTR \[edx\+0x3f8\]\{1to8\} -+[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa 00 04 00 00 vptestnmq k5,zmm5,QWORD PTR \[edx\+0x400\]\{1to8\} -+[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 80 vptestnmq k5,zmm5,QWORD PTR \[edx-0x400\]\{1to8\} -+[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa f8 fb ff ff vptestnmq k5,zmm5,QWORD PTR \[edx-0x408\]\{1to8\} +[ ]*[a-f0-9]+: 62 f2 7e 48 3a f6 vpbroadcastmw2d zmm6,k6 +[ ]*[a-f0-9]+: 62 f2 fe 48 2a f6 vpbroadcastmb2q zmm6,k6 +#pass diff --git a/gas/testsuite/gas/i386/avx512cd.d b/gas/testsuite/gas/i386/avx512cd.d new file mode 100644 -index 0000000..4e9e2e0 +index 0000000..8f786e3 --- /dev/null +++ b/gas/testsuite/gas/i386/avx512cd.d -@@ -0,0 +1,179 @@ +@@ -0,0 +1,127 @@ +#as: +#objdump: -dw +#name: i386 AVX512CD insns @@ -1224503,32 +1231616,6 @@ index 0000000..4e9e2e0 +[ ]*[a-f0-9]+: 62 f2 fd 58 44 b2 00 04 00 00 vplzcntq 0x400\(%edx\)\{1to8\},%zmm6 +[ ]*[a-f0-9]+: 62 f2 fd 58 44 72 80 vplzcntq -0x400\(%edx\)\{1to8\},%zmm6 +[ ]*[a-f0-9]+: 62 f2 fd 58 44 b2 f8 fb ff ff vplzcntq -0x408\(%edx\)\{1to8\},%zmm6 -+[ ]*[a-f0-9]+: 62 f2 56 48 27 ec vptestnmd %zmm4,%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 56 4f 27 ec vptestnmd %zmm4,%zmm5,%k5\{%k7\} -+[ ]*[a-f0-9]+: 62 f2 56 48 27 29 vptestnmd \(%ecx\),%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 56 48 27 ac f4 c0 1d fe ff vptestnmd -0x1e240\(%esp,%esi,8\),%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 56 58 27 28 vptestnmd \(%eax\)\{1to16\},%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 56 48 27 6a 7f vptestnmd 0x1fc0\(%edx\),%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 56 48 27 aa 00 20 00 00 vptestnmd 0x2000\(%edx\),%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 56 48 27 6a 80 vptestnmd -0x2000\(%edx\),%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 56 48 27 aa c0 df ff ff vptestnmd -0x2040\(%edx\),%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 56 58 27 6a 7f vptestnmd 0x1fc\(%edx\)\{1to16\},%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 56 58 27 aa 00 02 00 00 vptestnmd 0x200\(%edx\)\{1to16\},%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 56 58 27 6a 80 vptestnmd -0x200\(%edx\)\{1to16\},%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 56 58 27 aa fc fd ff ff vptestnmd -0x204\(%edx\)\{1to16\},%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 ec vptestnmq %zmm4,%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 d6 4f 27 ec vptestnmq %zmm4,%zmm5,%k5\{%k7\} -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 29 vptestnmq \(%ecx\),%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 ac f4 c0 1d fe ff vptestnmq -0x1e240\(%esp,%esi,8\),%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 d6 58 27 28 vptestnmq \(%eax\)\{1to8\},%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 6a 7f vptestnmq 0x1fc0\(%edx\),%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 aa 00 20 00 00 vptestnmq 0x2000\(%edx\),%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 6a 80 vptestnmq -0x2000\(%edx\),%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 aa c0 df ff ff vptestnmq -0x2040\(%edx\),%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 7f vptestnmq 0x3f8\(%edx\)\{1to8\},%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa 00 04 00 00 vptestnmq 0x400\(%edx\)\{1to8\},%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 80 vptestnmq -0x400\(%edx\)\{1to8\},%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa f8 fb ff ff vptestnmq -0x408\(%edx\)\{1to8\},%zmm5,%k5 +[ ]*[a-f0-9]+: 62 f2 7e 48 3a f6 vpbroadcastmw2d %k6,%zmm6 +[ ]*[a-f0-9]+: 62 f2 fe 48 2a f6 vpbroadcastmb2q %k6,%zmm6 +[ ]*[a-f0-9]+: 62 f2 7d 48 c4 f5 vpconflictd %zmm5,%zmm6 @@ -1224587,41 +1231674,15 @@ index 0000000..4e9e2e0 +[ ]*[a-f0-9]+: 62 f2 fd 58 44 b2 00 04 00 00 vplzcntq 0x400\(%edx\)\{1to8\},%zmm6 +[ ]*[a-f0-9]+: 62 f2 fd 58 44 72 80 vplzcntq -0x400\(%edx\)\{1to8\},%zmm6 +[ ]*[a-f0-9]+: 62 f2 fd 58 44 b2 f8 fb ff ff vplzcntq -0x408\(%edx\)\{1to8\},%zmm6 -+[ ]*[a-f0-9]+: 62 f2 56 48 27 ec vptestnmd %zmm4,%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 56 4f 27 ec vptestnmd %zmm4,%zmm5,%k5\{%k7\} -+[ ]*[a-f0-9]+: 62 f2 56 48 27 29 vptestnmd \(%ecx\),%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 56 48 27 ac f4 c0 1d fe ff vptestnmd -0x1e240\(%esp,%esi,8\),%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 56 58 27 28 vptestnmd \(%eax\)\{1to16\},%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 56 48 27 6a 7f vptestnmd 0x1fc0\(%edx\),%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 56 48 27 aa 00 20 00 00 vptestnmd 0x2000\(%edx\),%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 56 48 27 6a 80 vptestnmd -0x2000\(%edx\),%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 56 48 27 aa c0 df ff ff vptestnmd -0x2040\(%edx\),%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 56 58 27 6a 7f vptestnmd 0x1fc\(%edx\)\{1to16\},%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 56 58 27 aa 00 02 00 00 vptestnmd 0x200\(%edx\)\{1to16\},%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 56 58 27 6a 80 vptestnmd -0x200\(%edx\)\{1to16\},%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 56 58 27 aa fc fd ff ff vptestnmd -0x204\(%edx\)\{1to16\},%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 ec vptestnmq %zmm4,%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 d6 4f 27 ec vptestnmq %zmm4,%zmm5,%k5\{%k7\} -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 29 vptestnmq \(%ecx\),%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 ac f4 c0 1d fe ff vptestnmq -0x1e240\(%esp,%esi,8\),%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 d6 58 27 28 vptestnmq \(%eax\)\{1to8\},%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 6a 7f vptestnmq 0x1fc0\(%edx\),%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 aa 00 20 00 00 vptestnmq 0x2000\(%edx\),%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 6a 80 vptestnmq -0x2000\(%edx\),%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 d6 48 27 aa c0 df ff ff vptestnmq -0x2040\(%edx\),%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 7f vptestnmq 0x3f8\(%edx\)\{1to8\},%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa 00 04 00 00 vptestnmq 0x400\(%edx\)\{1to8\},%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 80 vptestnmq -0x400\(%edx\)\{1to8\},%zmm5,%k5 -+[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa f8 fb ff ff vptestnmq -0x408\(%edx\)\{1to8\},%zmm5,%k5 +[ ]*[a-f0-9]+: 62 f2 7e 48 3a f6 vpbroadcastmw2d %k6,%zmm6 +[ ]*[a-f0-9]+: 62 f2 fe 48 2a f6 vpbroadcastmb2q %k6,%zmm6 +#pass diff --git a/gas/testsuite/gas/i386/avx512cd.s b/gas/testsuite/gas/i386/avx512cd.s new file mode 100644 -index 0000000..6f4869f +index 0000000..eace8ce --- /dev/null +++ b/gas/testsuite/gas/i386/avx512cd.s -@@ -0,0 +1,191 @@ +@@ -0,0 +1,135 @@ +# Check 32bit AVX512CD instructions + + .allow_index_reg @@ -1224688,34 +1231749,6 @@ index 0000000..6f4869f + vplzcntq -1024(%edx){1to8}, %zmm6 # AVX512CD Disp8 + vplzcntq -1032(%edx){1to8}, %zmm6 # AVX512CD + -+ vptestnmd %zmm4, %zmm5, %k5 # AVX512CD -+ vptestnmd %zmm4, %zmm5, %k5{%k7} # AVX512CD -+ vptestnmd (%ecx), %zmm5, %k5 # AVX512CD -+ vptestnmd -123456(%esp,%esi,8), %zmm5, %k5 # AVX512CD -+ vptestnmd (%eax){1to16}, %zmm5, %k5 # AVX512CD -+ vptestnmd 8128(%edx), %zmm5, %k5 # AVX512CD Disp8 -+ vptestnmd 8192(%edx), %zmm5, %k5 # AVX512CD -+ vptestnmd -8192(%edx), %zmm5, %k5 # AVX512CD Disp8 -+ vptestnmd -8256(%edx), %zmm5, %k5 # AVX512CD -+ vptestnmd 508(%edx){1to16}, %zmm5, %k5 # AVX512CD Disp8 -+ vptestnmd 512(%edx){1to16}, %zmm5, %k5 # AVX512CD -+ vptestnmd -512(%edx){1to16}, %zmm5, %k5 # AVX512CD Disp8 -+ vptestnmd -516(%edx){1to16}, %zmm5, %k5 # AVX512CD -+ -+ vptestnmq %zmm4, %zmm5, %k5 # AVX512CD -+ vptestnmq %zmm4, %zmm5, %k5{%k7} # AVX512CD -+ vptestnmq (%ecx), %zmm5, %k5 # AVX512CD -+ vptestnmq -123456(%esp,%esi,8), %zmm5, %k5 # AVX512CD -+ vptestnmq (%eax){1to8}, %zmm5, %k5 # AVX512CD -+ vptestnmq 8128(%edx), %zmm5, %k5 # AVX512CD Disp8 -+ vptestnmq 8192(%edx), %zmm5, %k5 # AVX512CD -+ vptestnmq -8192(%edx), %zmm5, %k5 # AVX512CD Disp8 -+ vptestnmq -8256(%edx), %zmm5, %k5 # AVX512CD -+ vptestnmq 1016(%edx){1to8}, %zmm5, %k5 # AVX512CD Disp8 -+ vptestnmq 1024(%edx){1to8}, %zmm5, %k5 # AVX512CD -+ vptestnmq -1024(%edx){1to8}, %zmm5, %k5 # AVX512CD Disp8 -+ vptestnmq -1032(%edx){1to8}, %zmm5, %k5 # AVX512CD -+ + vpbroadcastmw2d %k6, %zmm6 # AVX512CD + + vpbroadcastmb2q %k6, %zmm6 # AVX512CD @@ -1224781,34 +1231814,6 @@ index 0000000..6f4869f + vplzcntq zmm6, [edx-1024]{1to8} # AVX512CD Disp8 + vplzcntq zmm6, [edx-1032]{1to8} # AVX512CD + -+ vptestnmd k5, zmm5, zmm4 # AVX512CD -+ vptestnmd k5{k7}, zmm5, zmm4 # AVX512CD -+ vptestnmd k5, zmm5, ZMMWORD PTR [ecx] # AVX512CD -+ vptestnmd k5, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512CD -+ vptestnmd k5, zmm5, [eax]{1to16} # AVX512CD -+ vptestnmd k5, zmm5, ZMMWORD PTR [edx+8128] # AVX512CD Disp8 -+ vptestnmd k5, zmm5, ZMMWORD PTR [edx+8192] # AVX512CD -+ vptestnmd k5, zmm5, ZMMWORD PTR [edx-8192] # AVX512CD Disp8 -+ vptestnmd k5, zmm5, ZMMWORD PTR [edx-8256] # AVX512CD -+ vptestnmd k5, zmm5, [edx+508]{1to16} # AVX512CD Disp8 -+ vptestnmd k5, zmm5, [edx+512]{1to16} # AVX512CD -+ vptestnmd k5, zmm5, [edx-512]{1to16} # AVX512CD Disp8 -+ vptestnmd k5, zmm5, [edx-516]{1to16} # AVX512CD -+ -+ vptestnmq k5, zmm5, zmm4 # AVX512CD -+ vptestnmq k5{k7}, zmm5, zmm4 # AVX512CD -+ vptestnmq k5, zmm5, ZMMWORD PTR [ecx] # AVX512CD -+ vptestnmq k5, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512CD -+ vptestnmq k5, zmm5, [eax]{1to8} # AVX512CD -+ vptestnmq k5, zmm5, ZMMWORD PTR [edx+8128] # AVX512CD Disp8 -+ vptestnmq k5, zmm5, ZMMWORD PTR [edx+8192] # AVX512CD -+ vptestnmq k5, zmm5, ZMMWORD PTR [edx-8192] # AVX512CD Disp8 -+ vptestnmq k5, zmm5, ZMMWORD PTR [edx-8256] # AVX512CD -+ vptestnmq k5, zmm5, [edx+1016]{1to8} # AVX512CD Disp8 -+ vptestnmq k5, zmm5, [edx+1024]{1to8} # AVX512CD -+ vptestnmq k5, zmm5, [edx-1024]{1to8} # AVX512CD Disp8 -+ vptestnmq k5, zmm5, [edx-1032]{1to8} # AVX512CD -+ + vpbroadcastmw2d zmm6, k6 # AVX512CD + + vpbroadcastmb2q zmm6, k6 # AVX512CD @@ -1225615,10 +1232620,10 @@ index 0000000..f894e02 + diff --git a/gas/testsuite/gas/i386/avx512f-intel.d b/gas/testsuite/gas/i386/avx512f-intel.d new file mode 100644 -index 0000000..5a7236b +index 0000000..b6b3a2e --- /dev/null +++ b/gas/testsuite/gas/i386/avx512f-intel.d -@@ -0,0 +1,13240 @@ +@@ -0,0 +1,13292 @@ +#as: +#objdump: -dwMintel +#name: i386 AVX512F insns (Intel disassembly) @@ -1229180,10 +1236185,10 @@ index 0000000..5a7236b +[ ]*[a-f0-9]+: 62 f2 fd 49 93 b4 fd 7b 00 00 00 vgatherqpd zmm6\{k1\},ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\] +[ ]*[a-f0-9]+: 62 f2 fd 49 93 74 38 20 vgatherqpd zmm6\{k1\},ZMMWORD PTR \[eax\+zmm7\*1\+0x100\] +[ ]*[a-f0-9]+: 62 f2 fd 49 93 b4 b9 00 04 00 00 vgatherqpd zmm6\{k1\},ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\] -+[ ]*[a-f0-9]+: 62 f2 7d 49 93 b4 fd 7b 00 00 00 vgatherqps ymm6\{k1\},ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\] -+[ ]*[a-f0-9]+: 62 f2 7d 49 93 b4 fd 7b 00 00 00 vgatherqps ymm6\{k1\},ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\] -+[ ]*[a-f0-9]+: 62 f2 7d 49 93 74 38 40 vgatherqps ymm6\{k1\},ZMMWORD PTR \[eax\+zmm7\*1\+0x100\] -+[ ]*[a-f0-9]+: 62 f2 7d 49 93 b4 b9 00 04 00 00 vgatherqps ymm6\{k1\},ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\] ++[ ]*[a-f0-9]+: 62 f2 7d 49 93 b4 fd 7b 00 00 00 vgatherqps ymm6\{k1\},YMMWORD PTR \[ebp\+zmm7\*8\+0x7b\] ++[ ]*[a-f0-9]+: 62 f2 7d 49 93 b4 fd 7b 00 00 00 vgatherqps ymm6\{k1\},YMMWORD PTR \[ebp\+zmm7\*8\+0x7b\] ++[ ]*[a-f0-9]+: 62 f2 7d 49 93 74 38 40 vgatherqps ymm6\{k1\},YMMWORD PTR \[eax\+zmm7\*1\+0x100\] ++[ ]*[a-f0-9]+: 62 f2 7d 49 93 b4 b9 00 04 00 00 vgatherqps ymm6\{k1\},YMMWORD PTR \[ecx\+zmm7\*4\+0x400\] +[ ]*[a-f0-9]+: 62 f2 fd 48 42 f5 vgetexppd zmm6,zmm5 +[ ]*[a-f0-9]+: 62 f2 fd 4f 42 f5 vgetexppd zmm6\{k7\},zmm5 +[ ]*[a-f0-9]+: 62 f2 fd cf 42 f5 vgetexppd zmm6\{k7\}\{z\},zmm5 @@ -1230347,10 +1237352,10 @@ index 0000000..5a7236b +[ ]*[a-f0-9]+: 62 f2 fd 49 90 b4 fd 7b 00 00 00 vpgatherdq zmm6\{k1\},ZMMWORD PTR \[ebp\+ymm7\*8\+0x7b\] +[ ]*[a-f0-9]+: 62 f2 fd 49 90 74 38 20 vpgatherdq zmm6\{k1\},ZMMWORD PTR \[eax\+ymm7\*1\+0x100\] +[ ]*[a-f0-9]+: 62 f2 fd 49 90 b4 b9 00 04 00 00 vpgatherdq zmm6\{k1\},ZMMWORD PTR \[ecx\+ymm7\*4\+0x400\] -+[ ]*[a-f0-9]+: 62 f2 7d 49 91 b4 fd 7b 00 00 00 vpgatherqd ymm6\{k1\},ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b] -+[ ]*[a-f0-9]+: 62 f2 7d 49 91 b4 fd 7b 00 00 00 vpgatherqd ymm6\{k1\},ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b] -+[ ]*[a-f0-9]+: 62 f2 7d 49 91 74 38 40 vpgatherqd ymm6\{k1\},ZMMWORD PTR \[eax\+zmm7\*1\+0x100\] -+[ ]*[a-f0-9]+: 62 f2 7d 49 91 b4 b9 00 04 00 00 vpgatherqd ymm6\{k1\},ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\] ++[ ]*[a-f0-9]+: 62 f2 7d 49 91 b4 fd 7b 00 00 00 vpgatherqd ymm6\{k1\},YMMWORD PTR \[ebp\+zmm7\*8\+0x7b] ++[ ]*[a-f0-9]+: 62 f2 7d 49 91 b4 fd 7b 00 00 00 vpgatherqd ymm6\{k1\},YMMWORD PTR \[ebp\+zmm7\*8\+0x7b] ++[ ]*[a-f0-9]+: 62 f2 7d 49 91 74 38 40 vpgatherqd ymm6\{k1\},YMMWORD PTR \[eax\+zmm7\*1\+0x100\] ++[ ]*[a-f0-9]+: 62 f2 7d 49 91 b4 b9 00 04 00 00 vpgatherqd ymm6\{k1\},YMMWORD PTR \[ecx\+zmm7\*4\+0x400\] +[ ]*[a-f0-9]+: 62 f2 fd 49 91 b4 fd 7b 00 00 00 vpgatherqq zmm6\{k1\},ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\] +[ ]*[a-f0-9]+: 62 f2 fd 49 91 b4 fd 7b 00 00 00 vpgatherqq zmm6\{k1\},ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\] +[ ]*[a-f0-9]+: 62 f2 fd 49 91 74 38 20 vpgatherqq zmm6\{k1\},ZMMWORD PTR \[eax\+zmm7\*1\+0x100\] @@ -1230625,10 +1237630,10 @@ index 0000000..5a7236b +[ ]*[a-f0-9]+: 62 f2 fd 49 a0 b4 fd 7b 00 00 00 vpscatterdq ZMMWORD PTR \[ebp\+ymm7\*8\+0x7b\]\{k1\},zmm6 +[ ]*[a-f0-9]+: 62 f2 fd 49 a0 74 38 20 vpscatterdq ZMMWORD PTR \[eax\+ymm7\*1\+0x100\]\{k1\},zmm6 +[ ]*[a-f0-9]+: 62 f2 fd 49 a0 b4 b9 00 04 00 00 vpscatterdq ZMMWORD PTR \[ecx\+ymm7\*4\+0x400\]\{k1\},zmm6 -+[ ]*[a-f0-9]+: 62 f2 7d 49 a1 b4 fd 7b 00 00 00 vpscatterqd ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\},ymm6 -+[ ]*[a-f0-9]+: 62 f2 7d 49 a1 b4 fd 7b 00 00 00 vpscatterqd ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\},ymm6 -+[ ]*[a-f0-9]+: 62 f2 7d 49 a1 74 38 40 vpscatterqd ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\},ymm6 -+[ ]*[a-f0-9]+: 62 f2 7d 49 a1 b4 b9 00 04 00 00 vpscatterqd ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\},ymm6 ++[ ]*[a-f0-9]+: 62 f2 7d 49 a1 b4 fd 7b 00 00 00 vpscatterqd YMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\},ymm6 ++[ ]*[a-f0-9]+: 62 f2 7d 49 a1 b4 fd 7b 00 00 00 vpscatterqd YMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\},ymm6 ++[ ]*[a-f0-9]+: 62 f2 7d 49 a1 74 38 40 vpscatterqd YMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\},ymm6 ++[ ]*[a-f0-9]+: 62 f2 7d 49 a1 b4 b9 00 04 00 00 vpscatterqd YMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\},ymm6 +[ ]*[a-f0-9]+: 62 f2 fd 49 a1 b4 fd 7b 00 00 00 vpscatterqq ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\},zmm6 +[ ]*[a-f0-9]+: 62 f2 fd 49 a1 b4 fd 7b 00 00 00 vpscatterqq ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\},zmm6 +[ ]*[a-f0-9]+: 62 f2 fd 49 a1 74 38 20 vpscatterqq ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\},zmm6 @@ -1231048,10 +1238053,10 @@ index 0000000..5a7236b +[ ]*[a-f0-9]+: 62 f2 fd 49 a3 b4 fd 7b 00 00 00 vscatterqpd ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\},zmm6 +[ ]*[a-f0-9]+: 62 f2 fd 49 a3 74 38 20 vscatterqpd ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\},zmm6 +[ ]*[a-f0-9]+: 62 f2 fd 49 a3 b4 b9 00 04 00 00 vscatterqpd ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\},zmm6 -+[ ]*[a-f0-9]+: 62 f2 7d 49 a3 b4 fd 7b 00 00 00 vscatterqps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\},ymm6 -+[ ]*[a-f0-9]+: 62 f2 7d 49 a3 b4 fd 7b 00 00 00 vscatterqps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\},ymm6 -+[ ]*[a-f0-9]+: 62 f2 7d 49 a3 74 38 40 vscatterqps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\},ymm6 -+[ ]*[a-f0-9]+: 62 f2 7d 49 a3 b4 b9 00 04 00 00 vscatterqps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\},ymm6 ++[ ]*[a-f0-9]+: 62 f2 7d 49 a3 b4 fd 7b 00 00 00 vscatterqps YMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\},ymm6 ++[ ]*[a-f0-9]+: 62 f2 7d 49 a3 b4 fd 7b 00 00 00 vscatterqps YMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\},ymm6 ++[ ]*[a-f0-9]+: 62 f2 7d 49 a3 74 38 40 vscatterqps YMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\},ymm6 ++[ ]*[a-f0-9]+: 62 f2 7d 49 a3 b4 b9 00 04 00 00 vscatterqps YMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\},ymm6 +[ ]*[a-f0-9]+: 62 f1 d5 48 c6 f4 ab vshufpd zmm6,zmm5,zmm4,0xab +[ ]*[a-f0-9]+: 62 f1 d5 4f c6 f4 ab vshufpd zmm6\{k7\},zmm5,zmm4,0xab +[ ]*[a-f0-9]+: 62 f1 d5 cf c6 f4 ab vshufpd zmm6\{k7\}\{z\},zmm5,zmm4,0xab @@ -1232244,6 +1239249,32 @@ index 0000000..5a7236b +[ ]*[a-f0-9]+: 62 f2 d5 58 77 b2 00 04 00 00 vpermi2pd zmm6,zmm5,QWORD PTR \[edx\+0x400\]\{1to8\} +[ ]*[a-f0-9]+: 62 f2 d5 58 77 72 80 vpermi2pd zmm6,zmm5,QWORD PTR \[edx-0x400\]\{1to8\} +[ ]*[a-f0-9]+: 62 f2 d5 58 77 b2 f8 fb ff ff vpermi2pd zmm6,zmm5,QWORD PTR \[edx-0x408\]\{1to8\} ++[ ]*[a-f0-9]+: 62 f2 56 48 27 ec vptestnmd k5,zmm5,zmm4 ++[ ]*[a-f0-9]+: 62 f2 56 4f 27 ec vptestnmd k5\{k7\},zmm5,zmm4 ++[ ]*[a-f0-9]+: 62 f2 56 48 27 29 vptestnmd k5,zmm5,ZMMWORD PTR \[ecx\] ++[ ]*[a-f0-9]+: 62 f2 56 48 27 ac f4 c0 1d fe ff vptestnmd k5,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] ++[ ]*[a-f0-9]+: 62 f2 56 58 27 28 vptestnmd k5,zmm5,DWORD PTR \[eax\]\{1to16\} ++[ ]*[a-f0-9]+: 62 f2 56 48 27 6a 7f vptestnmd k5,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] ++[ ]*[a-f0-9]+: 62 f2 56 48 27 aa 00 20 00 00 vptestnmd k5,zmm5,ZMMWORD PTR \[edx\+0x2000\] ++[ ]*[a-f0-9]+: 62 f2 56 48 27 6a 80 vptestnmd k5,zmm5,ZMMWORD PTR \[edx-0x2000\] ++[ ]*[a-f0-9]+: 62 f2 56 48 27 aa c0 df ff ff vptestnmd k5,zmm5,ZMMWORD PTR \[edx-0x2040\] ++[ ]*[a-f0-9]+: 62 f2 56 58 27 6a 7f vptestnmd k5,zmm5,DWORD PTR \[edx\+0x1fc\]\{1to16\} ++[ ]*[a-f0-9]+: 62 f2 56 58 27 aa 00 02 00 00 vptestnmd k5,zmm5,DWORD PTR \[edx\+0x200\]\{1to16\} ++[ ]*[a-f0-9]+: 62 f2 56 58 27 6a 80 vptestnmd k5,zmm5,DWORD PTR \[edx-0x200\]\{1to16\} ++[ ]*[a-f0-9]+: 62 f2 56 58 27 aa fc fd ff ff vptestnmd k5,zmm5,DWORD PTR \[edx-0x204\]\{1to16\} ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 ec vptestnmq k5,zmm5,zmm4 ++[ ]*[a-f0-9]+: 62 f2 d6 4f 27 ec vptestnmq k5\{k7\},zmm5,zmm4 ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 29 vptestnmq k5,zmm5,ZMMWORD PTR \[ecx\] ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 ac f4 c0 1d fe ff vptestnmq k5,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] ++[ ]*[a-f0-9]+: 62 f2 d6 58 27 28 vptestnmq k5,zmm5,QWORD PTR \[eax\]\{1to8\} ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 6a 7f vptestnmq k5,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 aa 00 20 00 00 vptestnmq k5,zmm5,ZMMWORD PTR \[edx\+0x2000\] ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 6a 80 vptestnmq k5,zmm5,ZMMWORD PTR \[edx-0x2000\] ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 aa c0 df ff ff vptestnmq k5,zmm5,ZMMWORD PTR \[edx-0x2040\] ++[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 7f vptestnmq k5,zmm5,QWORD PTR \[edx\+0x3f8\]\{1to8\} ++[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa 00 04 00 00 vptestnmq k5,zmm5,QWORD PTR \[edx\+0x400\]\{1to8\} ++[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 80 vptestnmq k5,zmm5,QWORD PTR \[edx-0x400\]\{1to8\} ++[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa f8 fb ff ff vptestnmq k5,zmm5,QWORD PTR \[edx-0x408\]\{1to8\} +[ ]*[a-f0-9]+: 62 f1 d5 48 58 f4 vaddpd zmm6,zmm5,zmm4 +[ ]*[a-f0-9]+: 62 f1 d5 4f 58 f4 vaddpd zmm6\{k7\},zmm5,zmm4 +[ ]*[a-f0-9]+: 62 f1 d5 cf 58 f4 vaddpd zmm6\{k7\}\{z\},zmm5,zmm4 @@ -1235794,10 +1242825,10 @@ index 0000000..5a7236b +[ ]*[a-f0-9]+: 62 f2 fd 49 93 b4 fd 85 ff ff ff vgatherqpd zmm6\{k1\},ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\] +[ ]*[a-f0-9]+: 62 f2 fd 49 93 74 38 20 vgatherqpd zmm6\{k1\},ZMMWORD PTR \[eax\+zmm7\*1\+0x100\] +[ ]*[a-f0-9]+: 62 f2 fd 49 93 b4 b9 00 04 00 00 vgatherqpd zmm6\{k1\},ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\] -+[ ]*[a-f0-9]+: 62 f2 7d 49 93 b4 fd 85 ff ff ff vgatherqps ymm6\{k1\},ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\] -+[ ]*[a-f0-9]+: 62 f2 7d 49 93 b4 fd 85 ff ff ff vgatherqps ymm6\{k1\},ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\] -+[ ]*[a-f0-9]+: 62 f2 7d 49 93 74 38 40 vgatherqps ymm6\{k1\},ZMMWORD PTR \[eax\+zmm7\*1\+0x100\] -+[ ]*[a-f0-9]+: 62 f2 7d 49 93 b4 b9 00 04 00 00 vgatherqps ymm6\{k1\},ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\] ++[ ]*[a-f0-9]+: 62 f2 7d 49 93 b4 fd 85 ff ff ff vgatherqps ymm6\{k1\},YMMWORD PTR \[ebp\+zmm7\*8-0x7b\] ++[ ]*[a-f0-9]+: 62 f2 7d 49 93 b4 fd 85 ff ff ff vgatherqps ymm6\{k1\},YMMWORD PTR \[ebp\+zmm7\*8-0x7b\] ++[ ]*[a-f0-9]+: 62 f2 7d 49 93 74 38 40 vgatherqps ymm6\{k1\},YMMWORD PTR \[eax\+zmm7\*1\+0x100\] ++[ ]*[a-f0-9]+: 62 f2 7d 49 93 b4 b9 00 04 00 00 vgatherqps ymm6\{k1\},YMMWORD PTR \[ecx\+zmm7\*4\+0x400\] +[ ]*[a-f0-9]+: 62 f2 fd 48 42 f5 vgetexppd zmm6,zmm5 +[ ]*[a-f0-9]+: 62 f2 fd 4f 42 f5 vgetexppd zmm6\{k7\},zmm5 +[ ]*[a-f0-9]+: 62 f2 fd cf 42 f5 vgetexppd zmm6\{k7\}\{z\},zmm5 @@ -1236961,10 +1243992,10 @@ index 0000000..5a7236b +[ ]*[a-f0-9]+: 62 f2 fd 49 90 b4 fd 85 ff ff ff vpgatherdq zmm6\{k1\},ZMMWORD PTR \[ebp\+ymm7\*8-0x7b\] +[ ]*[a-f0-9]+: 62 f2 fd 49 90 74 38 20 vpgatherdq zmm6\{k1\},ZMMWORD PTR \[eax\+ymm7\*1\+0x100\] +[ ]*[a-f0-9]+: 62 f2 fd 49 90 b4 b9 00 04 00 00 vpgatherdq zmm6\{k1\},ZMMWORD PTR \[ecx\+ymm7\*4\+0x400\] -+[ ]*[a-f0-9]+: 62 f2 7d 49 91 b4 fd 85 ff ff ff vpgatherqd ymm6\{k1\},ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\] -+[ ]*[a-f0-9]+: 62 f2 7d 49 91 b4 fd 85 ff ff ff vpgatherqd ymm6\{k1\},ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\] -+[ ]*[a-f0-9]+: 62 f2 7d 49 91 74 38 40 vpgatherqd ymm6\{k1\},ZMMWORD PTR \[eax\+zmm7\*1\+0x100\] -+[ ]*[a-f0-9]+: 62 f2 7d 49 91 b4 b9 00 04 00 00 vpgatherqd ymm6\{k1\},ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\] ++[ ]*[a-f0-9]+: 62 f2 7d 49 91 b4 fd 85 ff ff ff vpgatherqd ymm6\{k1\},YMMWORD PTR \[ebp\+zmm7\*8-0x7b\] ++[ ]*[a-f0-9]+: 62 f2 7d 49 91 b4 fd 85 ff ff ff vpgatherqd ymm6\{k1\},YMMWORD PTR \[ebp\+zmm7\*8-0x7b\] ++[ ]*[a-f0-9]+: 62 f2 7d 49 91 74 38 40 vpgatherqd ymm6\{k1\},YMMWORD PTR \[eax\+zmm7\*1\+0x100\] ++[ ]*[a-f0-9]+: 62 f2 7d 49 91 b4 b9 00 04 00 00 vpgatherqd ymm6\{k1\},YMMWORD PTR \[ecx\+zmm7\*4\+0x400\] +[ ]*[a-f0-9]+: 62 f2 fd 49 91 b4 fd 85 ff ff ff vpgatherqq zmm6\{k1\},ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\] +[ ]*[a-f0-9]+: 62 f2 fd 49 91 b4 fd 85 ff ff ff vpgatherqq zmm6\{k1\},ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\] +[ ]*[a-f0-9]+: 62 f2 fd 49 91 74 38 20 vpgatherqq zmm6\{k1\},ZMMWORD PTR \[eax\+zmm7\*1\+0x100\] @@ -1237239,10 +1244270,10 @@ index 0000000..5a7236b +[ ]*[a-f0-9]+: 62 f2 fd 49 a0 b4 fd 85 ff ff ff vpscatterdq ZMMWORD PTR \[ebp\+ymm7\*8-0x7b\]\{k1\},zmm6 +[ ]*[a-f0-9]+: 62 f2 fd 49 a0 74 38 20 vpscatterdq ZMMWORD PTR \[eax\+ymm7\*1\+0x100\]\{k1\},zmm6 +[ ]*[a-f0-9]+: 62 f2 fd 49 a0 b4 b9 00 04 00 00 vpscatterdq ZMMWORD PTR \[ecx\+ymm7\*4\+0x400\]\{k1\},zmm6 -+[ ]*[a-f0-9]+: 62 f2 7d 49 a1 b4 fd 85 ff ff ff vpscatterqd ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\},ymm6 -+[ ]*[a-f0-9]+: 62 f2 7d 49 a1 b4 fd 85 ff ff ff vpscatterqd ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\},ymm6 -+[ ]*[a-f0-9]+: 62 f2 7d 49 a1 74 38 40 vpscatterqd ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\},ymm6 -+[ ]*[a-f0-9]+: 62 f2 7d 49 a1 b4 b9 00 04 00 00 vpscatterqd ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\},ymm6 ++[ ]*[a-f0-9]+: 62 f2 7d 49 a1 b4 fd 85 ff ff ff vpscatterqd YMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\},ymm6 ++[ ]*[a-f0-9]+: 62 f2 7d 49 a1 b4 fd 85 ff ff ff vpscatterqd YMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\},ymm6 ++[ ]*[a-f0-9]+: 62 f2 7d 49 a1 74 38 40 vpscatterqd YMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\},ymm6 ++[ ]*[a-f0-9]+: 62 f2 7d 49 a1 b4 b9 00 04 00 00 vpscatterqd YMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\},ymm6 +[ ]*[a-f0-9]+: 62 f2 fd 49 a1 b4 fd 85 ff ff ff vpscatterqq ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\},zmm6 +[ ]*[a-f0-9]+: 62 f2 fd 49 a1 b4 fd 85 ff ff ff vpscatterqq ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\},zmm6 +[ ]*[a-f0-9]+: 62 f2 fd 49 a1 74 38 20 vpscatterqq ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\},zmm6 @@ -1237662,10 +1244693,10 @@ index 0000000..5a7236b +[ ]*[a-f0-9]+: 62 f2 fd 49 a3 b4 fd 85 ff ff ff vscatterqpd ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\},zmm6 +[ ]*[a-f0-9]+: 62 f2 fd 49 a3 74 38 20 vscatterqpd ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\},zmm6 +[ ]*[a-f0-9]+: 62 f2 fd 49 a3 b4 b9 00 04 00 00 vscatterqpd ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\},zmm6 -+[ ]*[a-f0-9]+: 62 f2 7d 49 a3 b4 fd 85 ff ff ff vscatterqps ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\},ymm6 -+[ ]*[a-f0-9]+: 62 f2 7d 49 a3 b4 fd 85 ff ff ff vscatterqps ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\},ymm6 -+[ ]*[a-f0-9]+: 62 f2 7d 49 a3 74 38 40 vscatterqps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\},ymm6 -+[ ]*[a-f0-9]+: 62 f2 7d 49 a3 b4 b9 00 04 00 00 vscatterqps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\},ymm6 ++[ ]*[a-f0-9]+: 62 f2 7d 49 a3 b4 fd 85 ff ff ff vscatterqps YMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\},ymm6 ++[ ]*[a-f0-9]+: 62 f2 7d 49 a3 b4 fd 85 ff ff ff vscatterqps YMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\},ymm6 ++[ ]*[a-f0-9]+: 62 f2 7d 49 a3 74 38 40 vscatterqps YMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\},ymm6 ++[ ]*[a-f0-9]+: 62 f2 7d 49 a3 b4 b9 00 04 00 00 vscatterqps YMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\},ymm6 +[ ]*[a-f0-9]+: 62 f1 d5 48 c6 f4 ab vshufpd zmm6,zmm5,zmm4,0xab +[ ]*[a-f0-9]+: 62 f1 d5 4f c6 f4 ab vshufpd zmm6\{k7\},zmm5,zmm4,0xab +[ ]*[a-f0-9]+: 62 f1 d5 cf c6 f4 ab vshufpd zmm6\{k7\}\{z\},zmm5,zmm4,0xab @@ -1238858,6 +1245889,32 @@ index 0000000..5a7236b +[ ]*[a-f0-9]+: 62 f2 d5 58 77 b2 00 04 00 00 vpermi2pd zmm6,zmm5,QWORD PTR \[edx\+0x400\]\{1to8\} +[ ]*[a-f0-9]+: 62 f2 d5 58 77 72 80 vpermi2pd zmm6,zmm5,QWORD PTR \[edx-0x400\]\{1to8\} +[ ]*[a-f0-9]+: 62 f2 d5 58 77 b2 f8 fb ff ff vpermi2pd zmm6,zmm5,QWORD PTR \[edx-0x408\]\{1to8\} ++[ ]*[a-f0-9]+: 62 f2 56 48 27 ec vptestnmd k5,zmm5,zmm4 ++[ ]*[a-f0-9]+: 62 f2 56 4f 27 ec vptestnmd k5\{k7\},zmm5,zmm4 ++[ ]*[a-f0-9]+: 62 f2 56 48 27 29 vptestnmd k5,zmm5,ZMMWORD PTR \[ecx\] ++[ ]*[a-f0-9]+: 62 f2 56 48 27 ac f4 c0 1d fe ff vptestnmd k5,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] ++[ ]*[a-f0-9]+: 62 f2 56 58 27 28 vptestnmd k5,zmm5,DWORD PTR \[eax\]\{1to16\} ++[ ]*[a-f0-9]+: 62 f2 56 48 27 6a 7f vptestnmd k5,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] ++[ ]*[a-f0-9]+: 62 f2 56 48 27 aa 00 20 00 00 vptestnmd k5,zmm5,ZMMWORD PTR \[edx\+0x2000\] ++[ ]*[a-f0-9]+: 62 f2 56 48 27 6a 80 vptestnmd k5,zmm5,ZMMWORD PTR \[edx-0x2000\] ++[ ]*[a-f0-9]+: 62 f2 56 48 27 aa c0 df ff ff vptestnmd k5,zmm5,ZMMWORD PTR \[edx-0x2040\] ++[ ]*[a-f0-9]+: 62 f2 56 58 27 6a 7f vptestnmd k5,zmm5,DWORD PTR \[edx\+0x1fc\]\{1to16\} ++[ ]*[a-f0-9]+: 62 f2 56 58 27 aa 00 02 00 00 vptestnmd k5,zmm5,DWORD PTR \[edx\+0x200\]\{1to16\} ++[ ]*[a-f0-9]+: 62 f2 56 58 27 6a 80 vptestnmd k5,zmm5,DWORD PTR \[edx-0x200\]\{1to16\} ++[ ]*[a-f0-9]+: 62 f2 56 58 27 aa fc fd ff ff vptestnmd k5,zmm5,DWORD PTR \[edx-0x204\]\{1to16\} ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 ec vptestnmq k5,zmm5,zmm4 ++[ ]*[a-f0-9]+: 62 f2 d6 4f 27 ec vptestnmq k5\{k7\},zmm5,zmm4 ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 29 vptestnmq k5,zmm5,ZMMWORD PTR \[ecx\] ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 ac f4 c0 1d fe ff vptestnmq k5,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\] ++[ ]*[a-f0-9]+: 62 f2 d6 58 27 28 vptestnmq k5,zmm5,QWORD PTR \[eax\]\{1to8\} ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 6a 7f vptestnmq k5,zmm5,ZMMWORD PTR \[edx\+0x1fc0\] ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 aa 00 20 00 00 vptestnmq k5,zmm5,ZMMWORD PTR \[edx\+0x2000\] ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 6a 80 vptestnmq k5,zmm5,ZMMWORD PTR \[edx-0x2000\] ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 aa c0 df ff ff vptestnmq k5,zmm5,ZMMWORD PTR \[edx-0x2040\] ++[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 7f vptestnmq k5,zmm5,QWORD PTR \[edx\+0x3f8\]\{1to8\} ++[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa 00 04 00 00 vptestnmq k5,zmm5,QWORD PTR \[edx\+0x400\]\{1to8\} ++[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 80 vptestnmq k5,zmm5,QWORD PTR \[edx-0x400\]\{1to8\} ++[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa f8 fb ff ff vptestnmq k5,zmm5,QWORD PTR \[edx-0x408\]\{1to8\} +#pass diff --git a/gas/testsuite/gas/i386/avx512f-nondef.d b/gas/testsuite/gas/i386/avx512f-nondef.d new file mode 100644 @@ -1239291,10 +1246348,10 @@ index 0000000..88fee28 + vmovups zmm6{k7}{z}, zmm5 # AVX512F diff --git a/gas/testsuite/gas/i386/avx512f.d b/gas/testsuite/gas/i386/avx512f.d new file mode 100644 -index 0000000..ad225ee +index 0000000..e5533f9 --- /dev/null +++ b/gas/testsuite/gas/i386/avx512f.d -@@ -0,0 +1,13239 @@ +@@ -0,0 +1,13291 @@ +#as: +#objdump: -dw +#name: i386 AVX512F insns @@ -1245919,6 +1252976,32 @@ index 0000000..ad225ee +[ ]*[a-f0-9]+: 62 f2 d5 58 77 b2 00 04 00 00 vpermi2pd 0x400\(%edx\)\{1to8\},%zmm5,%zmm6 +[ ]*[a-f0-9]+: 62 f2 d5 58 77 72 80 vpermi2pd -0x400\(%edx\)\{1to8\},%zmm5,%zmm6 +[ ]*[a-f0-9]+: 62 f2 d5 58 77 b2 f8 fb ff ff vpermi2pd -0x408\(%edx\)\{1to8\},%zmm5,%zmm6 ++[ ]*[a-f0-9]+: 62 f2 56 48 27 ec vptestnmd %zmm4,%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 56 4f 27 ec vptestnmd %zmm4,%zmm5,%k5\{%k7\} ++[ ]*[a-f0-9]+: 62 f2 56 48 27 29 vptestnmd \(%ecx\),%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 56 48 27 ac f4 c0 1d fe ff vptestnmd -0x1e240\(%esp,%esi,8\),%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 56 58 27 28 vptestnmd \(%eax\)\{1to16\},%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 56 48 27 6a 7f vptestnmd 0x1fc0\(%edx\),%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 56 48 27 aa 00 20 00 00 vptestnmd 0x2000\(%edx\),%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 56 48 27 6a 80 vptestnmd -0x2000\(%edx\),%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 56 48 27 aa c0 df ff ff vptestnmd -0x2040\(%edx\),%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 56 58 27 6a 7f vptestnmd 0x1fc\(%edx\)\{1to16\},%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 56 58 27 aa 00 02 00 00 vptestnmd 0x200\(%edx\)\{1to16\},%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 56 58 27 6a 80 vptestnmd -0x200\(%edx\)\{1to16\},%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 56 58 27 aa fc fd ff ff vptestnmd -0x204\(%edx\)\{1to16\},%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 ec vptestnmq %zmm4,%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 d6 4f 27 ec vptestnmq %zmm4,%zmm5,%k5\{%k7\} ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 29 vptestnmq \(%ecx\),%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 ac f4 c0 1d fe ff vptestnmq -0x1e240\(%esp,%esi,8\),%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 d6 58 27 28 vptestnmq \(%eax\)\{1to8\},%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 6a 7f vptestnmq 0x1fc0\(%edx\),%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 aa 00 20 00 00 vptestnmq 0x2000\(%edx\),%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 6a 80 vptestnmq -0x2000\(%edx\),%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 aa c0 df ff ff vptestnmq -0x2040\(%edx\),%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 7f vptestnmq 0x3f8\(%edx\)\{1to8\},%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa 00 04 00 00 vptestnmq 0x400\(%edx\)\{1to8\},%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 80 vptestnmq -0x400\(%edx\)\{1to8\},%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa f8 fb ff ff vptestnmq -0x408\(%edx\)\{1to8\},%zmm5,%k5 +[ ]*[a-f0-9]+: 62 f1 d5 48 58 f4 vaddpd %zmm4,%zmm5,%zmm6 +[ ]*[a-f0-9]+: 62 f1 d5 4f 58 f4 vaddpd %zmm4,%zmm5,%zmm6\{%k7\} +[ ]*[a-f0-9]+: 62 f1 d5 cf 58 f4 vaddpd %zmm4,%zmm5,%zmm6\{%k7\}\{z\} @@ -1252533,13 +1259616,39 @@ index 0000000..ad225ee +[ ]*[a-f0-9]+: 62 f2 d5 58 77 b2 00 04 00 00 vpermi2pd 0x400\(%edx\)\{1to8\},%zmm5,%zmm6 +[ ]*[a-f0-9]+: 62 f2 d5 58 77 72 80 vpermi2pd -0x400\(%edx\)\{1to8\},%zmm5,%zmm6 +[ ]*[a-f0-9]+: 62 f2 d5 58 77 b2 f8 fb ff ff vpermi2pd -0x408\(%edx\)\{1to8\},%zmm5,%zmm6 ++[ ]*[a-f0-9]+: 62 f2 56 48 27 ec vptestnmd %zmm4,%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 56 4f 27 ec vptestnmd %zmm4,%zmm5,%k5\{%k7\} ++[ ]*[a-f0-9]+: 62 f2 56 48 27 29 vptestnmd \(%ecx\),%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 56 48 27 ac f4 c0 1d fe ff vptestnmd -0x1e240\(%esp,%esi,8\),%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 56 58 27 28 vptestnmd \(%eax\)\{1to16\},%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 56 48 27 6a 7f vptestnmd 0x1fc0\(%edx\),%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 56 48 27 aa 00 20 00 00 vptestnmd 0x2000\(%edx\),%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 56 48 27 6a 80 vptestnmd -0x2000\(%edx\),%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 56 48 27 aa c0 df ff ff vptestnmd -0x2040\(%edx\),%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 56 58 27 6a 7f vptestnmd 0x1fc\(%edx\)\{1to16\},%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 56 58 27 aa 00 02 00 00 vptestnmd 0x200\(%edx\)\{1to16\},%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 56 58 27 6a 80 vptestnmd -0x200\(%edx\)\{1to16\},%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 56 58 27 aa fc fd ff ff vptestnmd -0x204\(%edx\)\{1to16\},%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 ec vptestnmq %zmm4,%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 d6 4f 27 ec vptestnmq %zmm4,%zmm5,%k5\{%k7\} ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 29 vptestnmq \(%ecx\),%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 ac f4 c0 1d fe ff vptestnmq -0x1e240\(%esp,%esi,8\),%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 d6 58 27 28 vptestnmq \(%eax\)\{1to8\},%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 6a 7f vptestnmq 0x1fc0\(%edx\),%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 aa 00 20 00 00 vptestnmq 0x2000\(%edx\),%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 6a 80 vptestnmq -0x2000\(%edx\),%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 d6 48 27 aa c0 df ff ff vptestnmq -0x2040\(%edx\),%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 7f vptestnmq 0x3f8\(%edx\)\{1to8\},%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa 00 04 00 00 vptestnmq 0x400\(%edx\)\{1to8\},%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 d6 58 27 6a 80 vptestnmq -0x400\(%edx\)\{1to8\},%zmm5,%k5 ++[ ]*[a-f0-9]+: 62 f2 d6 58 27 aa f8 fb ff ff vptestnmq -0x408\(%edx\)\{1to8\},%zmm5,%k5 +#pass diff --git a/gas/testsuite/gas/i386/avx512f.s b/gas/testsuite/gas/i386/avx512f.s new file mode 100644 -index 0000000..bd833c2 +index 0000000..25c75ab --- /dev/null +++ b/gas/testsuite/gas/i386/avx512f.s -@@ -0,0 +1,14467 @@ +@@ -0,0 +1,14522 @@ +# Check 32bit AVX512F instructions + + .allow_index_reg @@ -1259776,6 +1266885,34 @@ index 0000000..bd833c2 + vpermi2pd -1024(%edx){1to8}, %zmm5, %zmm6 # AVX512F Disp8 + vpermi2pd -1032(%edx){1to8}, %zmm5, %zmm6 # AVX512F + ++ vptestnmd %zmm4, %zmm5, %k5 # AVX512F ++ vptestnmd %zmm4, %zmm5, %k5{%k7} # AVX512F ++ vptestnmd (%ecx), %zmm5, %k5 # AVX512F ++ vptestnmd -123456(%esp,%esi,8), %zmm5, %k5 # AVX512F ++ vptestnmd (%eax){1to16}, %zmm5, %k5 # AVX512F ++ vptestnmd 8128(%edx), %zmm5, %k5 # AVX512F Disp8 ++ vptestnmd 8192(%edx), %zmm5, %k5 # AVX512F ++ vptestnmd -8192(%edx), %zmm5, %k5 # AVX512F Disp8 ++ vptestnmd -8256(%edx), %zmm5, %k5 # AVX512F ++ vptestnmd 508(%edx){1to16}, %zmm5, %k5 # AVX512F Disp8 ++ vptestnmd 512(%edx){1to16}, %zmm5, %k5 # AVX512F ++ vptestnmd -512(%edx){1to16}, %zmm5, %k5 # AVX512F Disp8 ++ vptestnmd -516(%edx){1to16}, %zmm5, %k5 # AVX512F ++ ++ vptestnmq %zmm4, %zmm5, %k5 # AVX512F ++ vptestnmq %zmm4, %zmm5, %k5{%k7} # AVX512F ++ vptestnmq (%ecx), %zmm5, %k5 # AVX512F ++ vptestnmq -123456(%esp,%esi,8), %zmm5, %k5 # AVX512F ++ vptestnmq (%eax){1to8}, %zmm5, %k5 # AVX512F ++ vptestnmq 8128(%edx), %zmm5, %k5 # AVX512F Disp8 ++ vptestnmq 8192(%edx), %zmm5, %k5 # AVX512F ++ vptestnmq -8192(%edx), %zmm5, %k5 # AVX512F Disp8 ++ vptestnmq -8256(%edx), %zmm5, %k5 # AVX512F ++ vptestnmq 1016(%edx){1to8}, %zmm5, %k5 # AVX512F Disp8 ++ vptestnmq 1024(%edx){1to8}, %zmm5, %k5 # AVX512F ++ vptestnmq -1024(%edx){1to8}, %zmm5, %k5 # AVX512F Disp8 ++ vptestnmq -1032(%edx){1to8}, %zmm5, %k5 # AVX512F ++ + .intel_syntax noprefix + vaddpd zmm6, zmm5, zmm4 # AVX512F + vaddpd zmm6{k7}, zmm5, zmm4 # AVX512F @@ -1263633,10 +1270770,10 @@ index 0000000..bd833c2 + vgatherqpd zmm6{k1}, ZMMWORD PTR [eax+zmm7+256] # AVX512F + vgatherqpd zmm6{k1}, ZMMWORD PTR [ecx+zmm7*4+1024] # AVX512F + -+ vgatherqps ymm6{k1}, ZMMWORD PTR [ebp+zmm7*8-123] # AVX512F -+ vgatherqps ymm6{k1}, ZMMWORD PTR [ebp+zmm7*8-123] # AVX512F -+ vgatherqps ymm6{k1}, zMMWORD PTR [eax+zmm7+256] # AVX512F -+ vgatherqps ymm6{k1}, ZMMWORD PTR [ecx+zmm7*4+1024] # AVX512F ++ vgatherqps ymm6{k1}, YMMWORD PTR [ebp+zmm7*8-123] # AVX512F ++ vgatherqps ymm6{k1}, YMMWORD PTR [ebp+zmm7*8-123] # AVX512F ++ vgatherqps ymm6{k1}, YMMWORD PTR [eax+zmm7+256] # AVX512F ++ vgatherqps ymm6{k1}, YMMWORD PTR [ecx+zmm7*4+1024] # AVX512F + + vgetexppd zmm6, zmm5 # AVX512F + vgetexppd zmm6{k7}, zmm5 # AVX512F @@ -1264920,10 +1272057,10 @@ index 0000000..bd833c2 + vpgatherdq zmm6{k1}, ZMMWORD PTR [eax+ymm7+256] # AVX512F + vpgatherdq zmm6{k1}, ZMMWORD PTR [ecx+ymm7*4+1024] # AVX512F + -+ vpgatherqd ymm6{k1}, ZMMWORD PTR [ebp+zmm7*8-123] # AVX512F -+ vpgatherqd ymm6{k1}, ZMMWORD PTR [ebp+zmm7*8-123] # AVX512F -+ vpgatherqd ymm6{k1}, ZMMWORD PTR [eax+zmm7+256] # AVX512F -+ vpgatherqd ymm6{k1}, ZMMWORD PTR [ecx+zmm7*4+1024] # AVX512F ++ vpgatherqd ymm6{k1}, YMMWORD PTR [ebp+zmm7*8-123] # AVX512F ++ vpgatherqd ymm6{k1}, YMMWORD PTR [ebp+zmm7*8-123] # AVX512F ++ vpgatherqd ymm6{k1}, YMMWORD PTR [eax+zmm7+256] # AVX512F ++ vpgatherqd ymm6{k1}, YMMWORD PTR [ecx+zmm7*4+1024] # AVX512F + + vpgatherqq zmm6{k1}, ZMMWORD PTR [ebp+zmm7*8-123] # AVX512F + vpgatherqq zmm6{k1}, ZMMWORD PTR [ebp+zmm7*8-123] # AVX512F @@ -1265225,10 +1272362,10 @@ index 0000000..bd833c2 + vpscatterdq ZMMWORD PTR [eax+ymm7+256]{k1}, zmm6 # AVX512F + vpscatterdq ZMMWORD PTR [ecx+ymm7*4+1024]{k1}, zmm6 # AVX512F + -+ vpscatterqd ZMMWORD PTR [ebp+zmm7*8-123]{k1}, ymm6 # AVX512F -+ vpscatterqd ZMMWORD PTR [ebp+zmm7*8-123]{k1}, ymm6 # AVX512F -+ vpscatterqd ZMMWORD PTR [eax+zmm7+256]{k1}, ymm6 # AVX512F -+ vpscatterqd ZMMWORD PTR [ecx+zmm7*4+1024]{k1}, ymm6 # AVX512F ++ vpscatterqd YMMWORD PTR [ebp+zmm7*8-123]{k1}, ymm6 # AVX512F ++ vpscatterqd YMMWORD PTR [ebp+zmm7*8-123]{k1}, ymm6 # AVX512F ++ vpscatterqd YMMWORD PTR [eax+zmm7+256]{k1}, ymm6 # AVX512F ++ vpscatterqd YMMWORD PTR [ecx+zmm7*4+1024]{k1}, ymm6 # AVX512F + + vpscatterqq ZMMWORD PTR [ebp+zmm7*8-123]{k1}, zmm6 # AVX512F + vpscatterqq ZMMWORD PTR [ebp+zmm7*8-123]{k1}, zmm6 # AVX512F @@ -1265686,10 +1272823,10 @@ index 0000000..bd833c2 + vscatterqpd ZMMWORD PTR [eax+zmm7+256]{k1}, zmm6 # AVX512F + vscatterqpd ZMMWORD PTR [ecx+zmm7*4+1024]{k1}, zmm6 # AVX512F + -+ vscatterqps ZMMWORD PTR [ebp+zmm7*8-123]{k1}, ymm6 # AVX512F -+ vscatterqps ZMMWORD PTR [ebp+zmm7*8-123]{k1}, ymm6 # AVX512F -+ vscatterqps ZMMWORD PTR [eax+zmm7+256]{k1}, ymm6 # AVX512F -+ vscatterqps ZMMWORD PTR [ecx+zmm7*4+1024]{k1}, ymm6 # AVX512F ++ vscatterqps YMMWORD PTR [ebp+zmm7*8-123]{k1}, ymm6 # AVX512F ++ vscatterqps YMMWORD PTR [ebp+zmm7*8-123]{k1}, ymm6 # AVX512F ++ vscatterqps YMMWORD PTR [eax+zmm7+256]{k1}, ymm6 # AVX512F ++ vscatterqps YMMWORD PTR [ecx+zmm7*4+1024]{k1}, ymm6 # AVX512F + + vshufpd zmm6, zmm5, zmm4, 0xab # AVX512F + vshufpd zmm6{k7}, zmm5, zmm4, 0xab # AVX512F @@ -1267007,12 +1274144,39 @@ index 0000000..bd833c2 + vpermi2pd zmm6, zmm5, [edx-1024]{1to8} # AVX512F Disp8 + vpermi2pd zmm6, zmm5, [edx-1032]{1to8} # AVX512F + ++ vptestnmd k5, zmm5, zmm4 # AVX512F ++ vptestnmd k5{k7}, zmm5, zmm4 # AVX512F ++ vptestnmd k5, zmm5, ZMMWORD PTR [ecx] # AVX512F ++ vptestnmd k5, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512F ++ vptestnmd k5, zmm5, [eax]{1to16} # AVX512F ++ vptestnmd k5, zmm5, ZMMWORD PTR [edx+8128] # AVX512F Disp8 ++ vptestnmd k5, zmm5, ZMMWORD PTR [edx+8192] # AVX512F ++ vptestnmd k5, zmm5, ZMMWORD PTR [edx-8192] # AVX512F Disp8 ++ vptestnmd k5, zmm5, ZMMWORD PTR [edx-8256] # AVX512F ++ vptestnmd k5, zmm5, [edx+508]{1to16} # AVX512F Disp8 ++ vptestnmd k5, zmm5, [edx+512]{1to16} # AVX512F ++ vptestnmd k5, zmm5, [edx-512]{1to16} # AVX512F Disp8 ++ vptestnmd k5, zmm5, [edx-516]{1to16} # AVX512F ++ ++ vptestnmq k5, zmm5, zmm4 # AVX512F ++ vptestnmq k5{k7}, zmm5, zmm4 # AVX512F ++ vptestnmq k5, zmm5, ZMMWORD PTR [ecx] # AVX512F ++ vptestnmq k5, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512F ++ vptestnmq k5, zmm5, [eax]{1to8} # AVX512F ++ vptestnmq k5, zmm5, ZMMWORD PTR [edx+8128] # AVX512F Disp8 ++ vptestnmq k5, zmm5, ZMMWORD PTR [edx+8192] # AVX512F ++ vptestnmq k5, zmm5, ZMMWORD PTR [edx-8192] # AVX512F Disp8 ++ vptestnmq k5, zmm5, ZMMWORD PTR [edx-8256] # AVX512F ++ vptestnmq k5, zmm5, [edx+1016]{1to8} # AVX512F Disp8 ++ vptestnmq k5, zmm5, [edx+1024]{1to8} # AVX512F ++ vptestnmq k5, zmm5, [edx-1024]{1to8} # AVX512F Disp8 ++ vptestnmq k5, zmm5, [edx-1032]{1to8} # AVX512F diff --git a/gas/testsuite/gas/i386/avx512pf-intel.d b/gas/testsuite/gas/i386/avx512pf-intel.d new file mode 100644 -index 0000000..126792f +index 0000000..05fa69b --- /dev/null +++ b/gas/testsuite/gas/i386/avx512pf-intel.d -@@ -0,0 +1,144 @@ +@@ -0,0 +1,140 @@ +#as: +#objdump: -dwMintel +#name: i386 AVX512PF insns (Intel disassembly) @@ -1267036,10 +1274200,10 @@ index 0000000..126792f +[ ]*[a-f0-9]+: 62 f2 fd 49 c7 8c fd 7b 00 00 00 vgatherpf0qpd ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c7 4c 38 20 vgatherpf0qpd ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c7 8c b9 00 04 00 00 vgatherpf0qpd ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 8c fd 7b 00 00 00 vgatherpf0qps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 8c fd 7b 00 00 00 vgatherpf0qps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 4c 38 40 vgatherpf0qps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 8c b9 00 04 00 00 vgatherpf0qps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 8c fd 7b 00 00 00 vgatherpf0qps YMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 8c fd 7b 00 00 00 vgatherpf0qps YMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 4c 38 40 vgatherpf0qps YMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 8c b9 00 04 00 00 vgatherpf0qps YMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c6 94 fd 7b 00 00 00 vgatherpf1dpd ZMMWORD PTR \[ebp\+ymm7\*8\+0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c6 94 fd 7b 00 00 00 vgatherpf1dpd ZMMWORD PTR \[ebp\+ymm7\*8\+0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c6 54 38 20 vgatherpf1dpd ZMMWORD PTR \[eax\+ymm7\*1\+0x100\]\{k1\} @@ -1267052,10 +1274216,10 @@ index 0000000..126792f +[ ]*[a-f0-9]+: 62 f2 fd 49 c7 94 fd 7b 00 00 00 vgatherpf1qpd ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c7 54 38 20 vgatherpf1qpd ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c7 94 b9 00 04 00 00 vgatherpf1qpd ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 94 fd 7b 00 00 00 vgatherpf1qps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 94 fd 7b 00 00 00 vgatherpf1qps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 54 38 40 vgatherpf1qps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 94 b9 00 04 00 00 vgatherpf1qps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 94 fd 7b 00 00 00 vgatherpf1qps YMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 94 fd 7b 00 00 00 vgatherpf1qps YMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 54 38 40 vgatherpf1qps YMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 94 b9 00 04 00 00 vgatherpf1qps YMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c6 ac fd 7b 00 00 00 vscatterpf0dpd ZMMWORD PTR \[ebp\+ymm7\*8\+0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c6 ac fd 7b 00 00 00 vscatterpf0dpd ZMMWORD PTR \[ebp\+ymm7\*8\+0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c6 6c 38 20 vscatterpf0dpd ZMMWORD PTR \[eax\+ymm7\*1\+0x100\]\{k1\} @@ -1267068,10 +1274232,10 @@ index 0000000..126792f +[ ]*[a-f0-9]+: 62 f2 fd 49 c7 ac fd 7b 00 00 00 vscatterpf0qpd ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c7 6c 38 20 vscatterpf0qpd ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c7 ac b9 00 04 00 00 vscatterpf0qpd ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 ac fd 7b 00 00 00 vscatterpf0qps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 ac fd 7b 00 00 00 vscatterpf0qps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 6c 38 40 vscatterpf0qps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 ac b9 00 04 00 00 vscatterpf0qps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 ac fd 7b 00 00 00 vscatterpf0qps YMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 ac fd 7b 00 00 00 vscatterpf0qps YMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 6c 38 40 vscatterpf0qps YMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 ac b9 00 04 00 00 vscatterpf0qps YMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c6 b4 fd 7b 00 00 00 vscatterpf1dpd ZMMWORD PTR \[ebp\+ymm7\*8\+0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c6 b4 fd 7b 00 00 00 vscatterpf1dpd ZMMWORD PTR \[ebp\+ymm7\*8\+0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c6 74 38 20 vscatterpf1dpd ZMMWORD PTR \[eax\+ymm7\*1\+0x100\]\{k1\} @@ -1267084,12 +1274248,10 @@ index 0000000..126792f +[ ]*[a-f0-9]+: 62 f2 fd 49 c7 b4 fd 7b 00 00 00 vscatterpf1qpd ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c7 74 38 20 vscatterpf1qpd ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c7 b4 b9 00 04 00 00 vscatterpf1qpd ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 fd 7b 00 00 00 vscatterpf1qps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 fd 7b 00 00 00 vscatterpf1qps ZMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 74 38 40 vscatterpf1qps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 b9 00 04 00 00 vscatterpf1qps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\} -+[ ]*[a-f0-9]+: 0f 0d 11 prefetchwt1 BYTE PTR \[ecx\] -+[ ]*[a-f0-9]+: 0f 0d 94 f4 c0 1d fe ff prefetchwt1 BYTE PTR \[esp\+esi\*8-0x1e240\] ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 fd 7b 00 00 00 vscatterpf1qps YMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 fd 7b 00 00 00 vscatterpf1qps YMMWORD PTR \[ebp\+zmm7\*8\+0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 74 38 40 vscatterpf1qps YMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 b9 00 04 00 00 vscatterpf1qps YMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c fd 85 ff ff ff vgatherpf0dpd ZMMWORD PTR \[ebp\+ymm7\*8-0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c fd 85 ff ff ff vgatherpf0dpd ZMMWORD PTR \[ebp\+ymm7\*8-0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c6 4c 38 20 vgatherpf0dpd ZMMWORD PTR \[eax\+ymm7\*1\+0x100\]\{k1\} @@ -1267102,10 +1274264,10 @@ index 0000000..126792f +[ ]*[a-f0-9]+: 62 f2 fd 49 c7 8c fd 85 ff ff ff vgatherpf0qpd ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c7 4c 38 20 vgatherpf0qpd ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c7 8c b9 00 04 00 00 vgatherpf0qpd ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 8c fd 85 ff ff ff vgatherpf0qps ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 8c fd 85 ff ff ff vgatherpf0qps ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 4c 38 40 vgatherpf0qps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 8c b9 00 04 00 00 vgatherpf0qps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 8c fd 85 ff ff ff vgatherpf0qps YMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 8c fd 85 ff ff ff vgatherpf0qps YMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 4c 38 40 vgatherpf0qps YMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 8c b9 00 04 00 00 vgatherpf0qps YMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c6 94 fd 85 ff ff ff vgatherpf1dpd ZMMWORD PTR \[ebp\+ymm7\*8-0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c6 94 fd 85 ff ff ff vgatherpf1dpd ZMMWORD PTR \[ebp\+ymm7\*8-0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c6 54 38 20 vgatherpf1dpd ZMMWORD PTR \[eax\+ymm7\*1\+0x100\]\{k1\} @@ -1267118,10 +1274280,10 @@ index 0000000..126792f +[ ]*[a-f0-9]+: 62 f2 fd 49 c7 94 fd 85 ff ff ff vgatherpf1qpd ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c7 54 38 20 vgatherpf1qpd ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c7 94 b9 00 04 00 00 vgatherpf1qpd ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 94 fd 85 ff ff ff vgatherpf1qps ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 94 fd 85 ff ff ff vgatherpf1qps ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 54 38 40 vgatherpf1qps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 94 b9 00 04 00 00 vgatherpf1qps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 94 fd 85 ff ff ff vgatherpf1qps YMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 94 fd 85 ff ff ff vgatherpf1qps YMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 54 38 40 vgatherpf1qps YMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 94 b9 00 04 00 00 vgatherpf1qps YMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c6 ac fd 85 ff ff ff vscatterpf0dpd ZMMWORD PTR \[ebp\+ymm7\*8-0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c6 ac fd 85 ff ff ff vscatterpf0dpd ZMMWORD PTR \[ebp\+ymm7\*8-0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c6 6c 38 20 vscatterpf0dpd ZMMWORD PTR \[eax\+ymm7\*1\+0x100\]\{k1\} @@ -1267134,10 +1274296,10 @@ index 0000000..126792f +[ ]*[a-f0-9]+: 62 f2 fd 49 c7 ac fd 85 ff ff ff vscatterpf0qpd ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c7 6c 38 20 vscatterpf0qpd ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c7 ac b9 00 04 00 00 vscatterpf0qpd ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 ac fd 85 ff ff ff vscatterpf0qps ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 ac fd 85 ff ff ff vscatterpf0qps ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 6c 38 40 vscatterpf0qps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 ac b9 00 04 00 00 vscatterpf0qps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 ac fd 85 ff ff ff vscatterpf0qps YMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 ac fd 85 ff ff ff vscatterpf0qps YMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 6c 38 40 vscatterpf0qps YMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 ac b9 00 04 00 00 vscatterpf0qps YMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c6 b4 fd 85 ff ff ff vscatterpf1dpd ZMMWORD PTR \[ebp\+ymm7\*8-0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c6 b4 fd 85 ff ff ff vscatterpf1dpd ZMMWORD PTR \[ebp\+ymm7\*8-0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c6 74 38 20 vscatterpf1dpd ZMMWORD PTR \[eax\+ymm7\*1\+0x100\]\{k1\} @@ -1267150,19 +1274312,17 @@ index 0000000..126792f +[ ]*[a-f0-9]+: 62 f2 fd 49 c7 b4 fd 85 ff ff ff vscatterpf1qpd ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c7 74 38 20 vscatterpf1qpd ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c7 b4 b9 00 04 00 00 vscatterpf1qpd ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 fd 85 ff ff ff vscatterpf1qps ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 fd 85 ff ff ff vscatterpf1qps ZMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 74 38 40 vscatterpf1qps ZMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\} -+[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 b9 00 04 00 00 vscatterpf1qps ZMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\} -+[ ]*[a-f0-9]+: 0f 0d 11 prefetchwt1 BYTE PTR \[ecx\] -+[ ]*[a-f0-9]+: 0f 0d 94 f4 c0 1d fe ff prefetchwt1 BYTE PTR \[esp\+esi\*8-0x1e240\] ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 fd 85 ff ff ff vscatterpf1qps YMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 fd 85 ff ff ff vscatterpf1qps YMMWORD PTR \[ebp\+zmm7\*8-0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 74 38 40 vscatterpf1qps YMMWORD PTR \[eax\+zmm7\*1\+0x100\]\{k1\} ++[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 b9 00 04 00 00 vscatterpf1qps YMMWORD PTR \[ecx\+zmm7\*4\+0x400\]\{k1\} +#pass diff --git a/gas/testsuite/gas/i386/avx512pf.d b/gas/testsuite/gas/i386/avx512pf.d new file mode 100644 -index 0000000..cff3f48 +index 0000000..16a4e4f --- /dev/null +++ b/gas/testsuite/gas/i386/avx512pf.d -@@ -0,0 +1,143 @@ +@@ -0,0 +1,139 @@ +#as: +#objdump: -dw +#name: i386 AVX512PF insns @@ -1267237,8 +1274397,6 @@ index 0000000..cff3f48 +[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 fd 7b 00 00 00 vscatterpf1qps 0x7b\(%ebp,%zmm7,8\)\{%k1\} +[ ]*[a-f0-9]+: 62 f2 7d 49 c7 74 38 40 vscatterpf1qps 0x100\(%eax,%zmm7,1\)\{%k1\} +[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 b9 00 04 00 00 vscatterpf1qps 0x400\(%ecx,%zmm7,4\)\{%k1\} -+[ ]*[a-f0-9]+: 0f 0d 11 prefetchwt1 \(%ecx\) -+[ ]*[a-f0-9]+: 0f 0d 94 f4 c0 1d fe ff prefetchwt1 -0x1e240\(%esp,%esi,8\) +[ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c fd 85 ff ff ff vgatherpf0dpd -0x7b\(%ebp,%ymm7,8\)\{%k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c6 8c fd 85 ff ff ff vgatherpf0dpd -0x7b\(%ebp,%ymm7,8\)\{%k1\} +[ ]*[a-f0-9]+: 62 f2 fd 49 c6 4c 38 20 vgatherpf0dpd 0x100\(%eax,%ymm7,1\)\{%k1\} @@ -1267303,15 +1274461,13 @@ index 0000000..cff3f48 +[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 fd 85 ff ff ff vscatterpf1qps -0x7b\(%ebp,%zmm7,8\)\{%k1\} +[ ]*[a-f0-9]+: 62 f2 7d 49 c7 74 38 40 vscatterpf1qps 0x100\(%eax,%zmm7,1\)\{%k1\} +[ ]*[a-f0-9]+: 62 f2 7d 49 c7 b4 b9 00 04 00 00 vscatterpf1qps 0x400\(%ecx,%zmm7,4\)\{%k1\} -+[ ]*[a-f0-9]+: 0f 0d 11 prefetchwt1 \(%ecx\) -+[ ]*[a-f0-9]+: 0f 0d 94 f4 c0 1d fe ff prefetchwt1 -0x1e240\(%esp,%esi,8\) +#pass diff --git a/gas/testsuite/gas/i386/avx512pf.s b/gas/testsuite/gas/i386/avx512pf.s new file mode 100644 -index 0000000..301e984 +index 0000000..3476660 --- /dev/null +++ b/gas/testsuite/gas/i386/avx512pf.s -@@ -0,0 +1,173 @@ +@@ -0,0 +1,167 @@ +# Check 32bit AVX512PF instructions + + .allow_index_reg @@ -1267398,9 +1274554,6 @@ index 0000000..301e984 + vscatterpf1qps 256(%eax,%zmm7){%k1} # AVX512PF + vscatterpf1qps 1024(%ecx,%zmm7,4){%k1} # AVX512PF + -+ prefetchwt1 (%ecx) # AVX512PF -+ prefetchwt1 -123456(%esp,%esi,8) # AVX512PF -+ + .intel_syntax noprefix + vgatherpf0dpd ZMMWORD PTR [ebp+ymm7*8-123]{k1} # AVX512PF + vgatherpf0dpd ZMMWORD PTR [ebp+ymm7*8-123]{k1} # AVX512PF @@ -1267417,10 +1274570,10 @@ index 0000000..301e984 + vgatherpf0qpd ZMMWORD PTR [eax+zmm7+256]{k1} # AVX512PF + vgatherpf0qpd ZMMWORD PTR [ecx+zmm7*4+1024]{k1} # AVX512PF + -+ vgatherpf0qps ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF -+ vgatherpf0qps ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF -+ vgatherpf0qps ZMMWORD PTR [eax+zmm7+256]{k1} # AVX512PF -+ vgatherpf0qps ZMMWORD PTR [ecx+zmm7*4+1024]{k1} # AVX512PF ++ vgatherpf0qps YMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF ++ vgatherpf0qps YMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF ++ vgatherpf0qps YMMWORD PTR [eax+zmm7+256]{k1} # AVX512PF ++ vgatherpf0qps YMMWORD PTR [ecx+zmm7*4+1024]{k1} # AVX512PF + + vgatherpf1dpd ZMMWORD PTR [ebp+ymm7*8-123]{k1} # AVX512PF + vgatherpf1dpd ZMMWORD PTR [ebp+ymm7*8-123]{k1} # AVX512PF @@ -1267437,10 +1274590,10 @@ index 0000000..301e984 + vgatherpf1qpd ZMMWORD PTR [eax+zmm7+256]{k1} # AVX512PF + vgatherpf1qpd ZMMWORD PTR [ecx+zmm7*4+1024]{k1} # AVX512PF + -+ vgatherpf1qps ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF -+ vgatherpf1qps ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF -+ vgatherpf1qps ZMMWORD PTR [eax+zmm7+256]{k1} # AVX512PF -+ vgatherpf1qps ZMMWORD PTR [ecx+zmm7*4+1024]{k1} # AVX512PF ++ vgatherpf1qps YMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF ++ vgatherpf1qps YMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF ++ vgatherpf1qps YMMWORD PTR [eax+zmm7+256]{k1} # AVX512PF ++ vgatherpf1qps YMMWORD PTR [ecx+zmm7*4+1024]{k1} # AVX512PF + + vscatterpf0dpd ZMMWORD PTR [ebp+ymm7*8-123]{k1} # AVX512PF + vscatterpf0dpd ZMMWORD PTR [ebp+ymm7*8-123]{k1} # AVX512PF @@ -1267457,10 +1274610,10 @@ index 0000000..301e984 + vscatterpf0qpd ZMMWORD PTR [eax+zmm7+256]{k1} # AVX512PF + vscatterpf0qpd ZMMWORD PTR [ecx+zmm7*4+1024]{k1} # AVX512PF + -+ vscatterpf0qps ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF -+ vscatterpf0qps ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF -+ vscatterpf0qps ZMMWORD PTR [eax+zmm7+256]{k1} # AVX512PF -+ vscatterpf0qps ZMMWORD PTR [ecx+zmm7*4+1024]{k1} # AVX512PF ++ vscatterpf0qps YMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF ++ vscatterpf0qps YMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF ++ vscatterpf0qps YMMWORD PTR [eax+zmm7+256]{k1} # AVX512PF ++ vscatterpf0qps YMMWORD PTR [ecx+zmm7*4+1024]{k1} # AVX512PF + + vscatterpf1dpd ZMMWORD PTR [ebp+ymm7*8-123]{k1} # AVX512PF + vscatterpf1dpd ZMMWORD PTR [ebp+ymm7*8-123]{k1} # AVX512PF @@ -1267477,13 +1274630,10 @@ index 0000000..301e984 + vscatterpf1qpd ZMMWORD PTR [eax+zmm7+256]{k1} # AVX512PF + vscatterpf1qpd ZMMWORD PTR [ecx+zmm7*4+1024]{k1} # AVX512PF + -+ vscatterpf1qps ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF -+ vscatterpf1qps ZMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF -+ vscatterpf1qps ZMMWORD PTR [eax+zmm7+256]{k1} # AVX512PF -+ vscatterpf1qps ZMMWORD PTR [ecx+zmm7*4+1024]{k1} # AVX512PF -+ -+ prefetchwt1 BYTE PTR [ecx] # AVX512PF -+ prefetchwt1 BYTE PTR [esp+esi*8-123456] # AVX512PF ++ vscatterpf1qps YMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF ++ vscatterpf1qps YMMWORD PTR [ebp+zmm7*8-123]{k1} # AVX512PF ++ vscatterpf1qps YMMWORD PTR [eax+zmm7+256]{k1} # AVX512PF ++ vscatterpf1qps YMMWORD PTR [ecx+zmm7*4+1024]{k1} # AVX512PF + diff --git a/gas/testsuite/gas/i386/bad-size.d b/gas/testsuite/gas/i386/bad-size.d new file mode 100644 @@ -1273513,6 +1280663,68 @@ index 0000000..3932f63 + +.p2align 5 + hlt +diff --git a/gas/testsuite/gas/i386/clflushopt-intel.d b/gas/testsuite/gas/i386/clflushopt-intel.d +new file mode 100644 +index 0000000..b062e18 +--- /dev/null ++++ b/gas/testsuite/gas/i386/clflushopt-intel.d +@@ -0,0 +1,16 @@ ++#as: ++#objdump: -dw -Mintel ++#name: i386 CLFLUSHOPT insns (Intel disassembly) ++#source: clflushopt.s ++ ++.*: +file format .* ++ ++ ++Disassembly of section \.text: ++ ++00000000 <_start>: ++[ ]*[a-f0-9]+:[ ]*66 0f ae 39[ ]*clflushopt BYTE PTR \[ecx\] ++[ ]*[a-f0-9]+:[ ]*66 0f ae bc f4 c0 1d fe ff[ ]*clflushopt BYTE PTR \[esp\+esi\*8-0x1e240\] ++[ ]*[a-f0-9]+:[ ]*66 0f ae 39[ ]*clflushopt BYTE PTR \[ecx\] ++[ ]*[a-f0-9]+:[ ]*66 0f ae bc f4 c0 1d fe ff[ ]*clflushopt BYTE PTR \[esp\+esi\*8-0x1e240\] ++#pass +diff --git a/gas/testsuite/gas/i386/clflushopt.d b/gas/testsuite/gas/i386/clflushopt.d +new file mode 100644 +index 0000000..115f5ed +--- /dev/null ++++ b/gas/testsuite/gas/i386/clflushopt.d +@@ -0,0 +1,16 @@ ++#as: ++#objdump: -dw ++#name: i386 CLFLUSHOPT insns ++#source: clflushopt.s ++ ++.*: +file format .* ++ ++ ++Disassembly of section \.text: ++ ++00000000 <_start>: ++[ ]*[a-f0-9]+:[ ]*66 0f ae 39[ ]*clflushopt \(%ecx\) ++[ ]*[a-f0-9]+:[ ]*66 0f ae bc f4 c0 1d fe ff[ ]*clflushopt -0x1e240\(%esp,%esi,8\) ++[ ]*[a-f0-9]+:[ ]*66 0f ae 39[ ]*clflushopt \(%ecx\) ++[ ]*[a-f0-9]+:[ ]*66 0f ae bc f4 c0 1d fe ff[ ]*clflushopt -0x1e240\(%esp,%esi,8\) ++#pass +diff --git a/gas/testsuite/gas/i386/clflushopt.s b/gas/testsuite/gas/i386/clflushopt.s +new file mode 100644 +index 0000000..a6d4990 +--- /dev/null ++++ b/gas/testsuite/gas/i386/clflushopt.s +@@ -0,0 +1,12 @@ ++# Check 32bit CLFLUSHOPT instructions ++ ++ .allow_index_reg ++ .text ++_start: ++ ++ clflushopt (%ecx) # CLFLUSHOPT ++ clflushopt -123456(%esp,%esi,8) # CLFLUSHOPT ++ ++ .intel_syntax noprefix ++ clflushopt BYTE PTR [ecx] # CLFLUSHOPT ++ clflushopt BYTE PTR [esp+esi*8-123456] # CLFLUSHOPT diff --git a/gas/testsuite/gas/i386/clmul-intel.d b/gas/testsuite/gas/i386/clmul-intel.d new file mode 100644 index 0000000..c311860 @@ -1274369,13 +1281581,13 @@ index 0000000..4d1a393 + diff --git a/gas/testsuite/gas/i386/dw2-compress-1.s b/gas/testsuite/gas/i386/dw2-compress-1.s new file mode 100644 -index 0000000..6908da5 +index 0000000..4013ebe --- /dev/null +++ b/gas/testsuite/gas/i386/dw2-compress-1.s @@ -0,0 +1,199 @@ +/* This testcase is copied from a similar test in GDB. + -+ Copyright 2010 Free Software Foundation, Inc. ++ Copyright (C) 2010-2014 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by @@ -1299204,12 +1306416,11 @@ index 0000000..1c6c4cc +#pass diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp new file mode 100644 -index 0000000..b70f01c +index 0000000..6389a07 --- /dev/null +++ b/gas/testsuite/gas/i386/i386.exp -@@ -0,0 +1,608 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,625 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1299479,6 +1306690,15 @@ index 0000000..b70f01c + run_list_test "mpx-inval-1" "-al" + run_dump_test "mpx-add-bnd-prefix" + run_dump_test "sha" ++ run_dump_test "clflushopt" ++ run_dump_test "clflushopt-intel" ++ run_dump_test "xsavec" ++ run_dump_test "xsavec-intel" ++ run_dump_test "xsaves" ++ run_dump_test "xsaves-intel" ++ run_dump_test "prefetchwt1" ++ run_dump_test "prefetchwt1-intel" ++ run_dump_test "se1" + run_dump_test "disassem" + + # These tests require support for 8 and 16 bit relocs, @@ -1299769,6 +1306989,15 @@ index 0000000..b70f01c + run_dump_test "x86-64-mpx-addr32" + run_dump_test "x86-64-mpx-add-bnd-prefix" + run_dump_test "x86-64-sha" ++ run_dump_test "x86-64-clflushopt" ++ run_dump_test "x86-64-clflushopt-intel" ++ run_dump_test "x86-64-xsavec" ++ run_dump_test "x86-64-xsavec-intel" ++ run_dump_test "x86-64-xsaves" ++ run_dump_test "x86-64-xsaves-intel" ++ run_dump_test "x86-64-prefetchwt1" ++ run_dump_test "x86-64-prefetchwt1-intel" ++ run_dump_test "x86-64-se1" + + if { ![istarget "*-*-aix*"] + && ![istarget "*-*-beos*"] @@ -1300767,12 +1307996,11 @@ index 0000000..f2997b0 + diff --git a/gas/testsuite/gas/i386/ilp32/cfi/ilp32.exp b/gas/testsuite/gas/i386/ilp32/cfi/ilp32.exp new file mode 100644 -index 0000000..92d7985 +index 0000000..2db07e3 --- /dev/null +++ b/gas/testsuite/gas/i386/ilp32/cfi/ilp32.exp -@@ -0,0 +1,42 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,41 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1300954,12 +1308182,11 @@ index 0000000..423d102 +#pass diff --git a/gas/testsuite/gas/i386/ilp32/elf/ilp32.exp b/gas/testsuite/gas/i386/ilp32/elf/ilp32.exp new file mode 100644 -index 0000000..92d7985 +index 0000000..2db07e3 --- /dev/null +++ b/gas/testsuite/gas/i386/ilp32/elf/ilp32.exp -@@ -0,0 +1,42 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,41 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1301206,12 +1308433,11 @@ index 0000000..3a37eed +#pass diff --git a/gas/testsuite/gas/i386/ilp32/ilp32.exp b/gas/testsuite/gas/i386/ilp32/ilp32.exp new file mode 100644 -index 0000000..eda802b +index 0000000..c9bb5f6 --- /dev/null +++ b/gas/testsuite/gas/i386/ilp32/ilp32.exp -@@ -0,0 +1,44 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,43 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1301387,12 +1308613,11 @@ index 0000000..d4e6dff + movabsq $0x80000001, %rax diff --git a/gas/testsuite/gas/i386/ilp32/lns/ilp32.exp b/gas/testsuite/gas/i386/ilp32/lns/ilp32.exp new file mode 100644 -index 0000000..92d7985 +index 0000000..2db07e3 --- /dev/null +++ b/gas/testsuite/gas/i386/ilp32/lns/ilp32.exp -@@ -0,0 +1,42 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,41 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1309501,7 +1316726,7 @@ index 0000000..9118db1 +#pass diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-cbw-intel.d b/gas/testsuite/gas/i386/ilp32/x86-64-cbw-intel.d new file mode 100644 -index 0000000..5b89548 +index 0000000..6d955eb --- /dev/null +++ b/gas/testsuite/gas/i386/ilp32/x86-64-cbw-intel.d @@ -0,0 +1,24 @@ @@ -1309519,7 +1316744,7 @@ index 0000000..5b89548 + 3: 48 98 cdqe + 5: 66 40 98 rex cbw + 8: 40 98 rex cwde -+ a: 66 48 98 data32 cdqe ++ a: 66 48 98 data16 cdqe + +0+00d <_cwd>: + d: 66 99 cwd @@ -1309527,11 +1316752,11 @@ index 0000000..5b89548 + 10: 48 99 cqo + 12: 66 40 99 rex cwd + 15: 40 99 rex cdq -+ 17: 66 48 99 data32 cqo ++ 17: 66 48 99 data16 cqo +#pass diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-cbw.d b/gas/testsuite/gas/i386/ilp32/x86-64-cbw.d new file mode 100644 -index 0000000..1eeafaa +index 0000000..3cb0697 --- /dev/null +++ b/gas/testsuite/gas/i386/ilp32/x86-64-cbw.d @@ -0,0 +1,24 @@ @@ -1309549,7 +1316774,7 @@ index 0000000..1eeafaa + 3: 48 98 cltq + 5: 66 40 98 rex cbtw + 8: 40 98 rex cwtl -+ a: 66 48 98 data32 cltq ++ a: 66 48 98 data16 cltq + +0+00d <_cwd>: + d: 66 99 cwtd @@ -1309557,7 +1316782,7 @@ index 0000000..1eeafaa + 10: 48 99 cqto + 12: 66 40 99 rex cwtd + 15: 40 99 rex cltd -+ 17: 66 48 99 data32 cqto ++ 17: 66 48 99 data16 cqto +#pass diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-clmul-intel.d b/gas/testsuite/gas/i386/ilp32/x86-64-clmul-intel.d new file mode 100644 @@ -1311126,7 +1318351,7 @@ index 0000000..74d863d +#pass diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-io-intel.d b/gas/testsuite/gas/i386/ilp32/x86-64-io-intel.d new file mode 100644 -index 0000000..67747b4 +index 0000000..2cdcfde --- /dev/null +++ b/gas/testsuite/gas/i386/ilp32/x86-64-io-intel.d @@ -0,0 +1,24 @@ @@ -1311140,23 +1318365,23 @@ index 0000000..67747b4 + +0+000 <_in>: + 0: 48 ed rex.W in eax,dx -+ 2: 66 48 ed data32 rex.W in eax,dx ++ 2: 66 48 ed data16 rex.W in eax,dx + +0+005 <_out>: + 5: 48 ef rex.W out dx,eax -+ 7: 66 48 ef data32 rex.W out dx,eax ++ 7: 66 48 ef data16 rex.W out dx,eax + +0+00a <_ins>: + a: 48 6d rex.W ins DWORD PTR es:\[rdi\],dx -+ c: 66 48 6d data32 rex.W ins DWORD PTR es:\[rdi\],dx ++ c: 66 48 6d data16 rex.W ins DWORD PTR es:\[rdi\],dx + +0+00f <_outs>: + f: 48 6f rex.W outs dx,DWORD PTR ds:\[rsi\] -+ 11: 66 48 6f data32 rex.W outs dx,DWORD PTR ds:\[rsi\] ++ 11: 66 48 6f data16 rex.W outs dx,DWORD PTR ds:\[rsi\] +#pass diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-io-suffix.d b/gas/testsuite/gas/i386/ilp32/x86-64-io-suffix.d new file mode 100644 -index 0000000..528bfdc +index 0000000..4f4c927 --- /dev/null +++ b/gas/testsuite/gas/i386/ilp32/x86-64-io-suffix.d @@ -0,0 +1,24 @@ @@ -1311170,23 +1318395,23 @@ index 0000000..528bfdc + +0+000 <_in>: + 0: 48 ed rex.W inl \(%dx\),%eax -+ 2: 66 48 ed data32 rex.W inl \(%dx\),%eax ++ 2: 66 48 ed data16 rex.W inl \(%dx\),%eax + +0+005 <_out>: + 5: 48 ef rex.W outl %eax,\(%dx\) -+ 7: 66 48 ef data32 rex.W outl %eax,\(%dx\) ++ 7: 66 48 ef data16 rex.W outl %eax,\(%dx\) + +0+00a <_ins>: + a: 48 6d rex.W insl \(%dx\),%es:\(%rdi\) -+ c: 66 48 6d data32 rex.W insl \(%dx\),%es:\(%rdi\) ++ c: 66 48 6d data16 rex.W insl \(%dx\),%es:\(%rdi\) + +0+00f <_outs>: + f: 48 6f rex.W outsl %ds:\(%rsi\),\(%dx\) -+ 11: 66 48 6f data32 rex.W outsl %ds:\(%rsi\),\(%dx\) ++ 11: 66 48 6f data16 rex.W outsl %ds:\(%rsi\),\(%dx\) +#pass diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-io.d b/gas/testsuite/gas/i386/ilp32/x86-64-io.d new file mode 100644 -index 0000000..fe86273 +index 0000000..889e60e --- /dev/null +++ b/gas/testsuite/gas/i386/ilp32/x86-64-io.d @@ -0,0 +1,24 @@ @@ -1311200,19 +1318425,19 @@ index 0000000..fe86273 + +0+000 <_in>: + 0: 48 ed rex.W in \(%dx\),%eax -+ 2: 66 48 ed data32 rex.W in \(%dx\),%eax ++ 2: 66 48 ed data16 rex.W in \(%dx\),%eax + +0+005 <_out>: + 5: 48 ef rex.W out %eax,\(%dx\) -+ 7: 66 48 ef data32 rex.W out %eax,\(%dx\) ++ 7: 66 48 ef data16 rex.W out %eax,\(%dx\) + +0+00a <_ins>: + a: 48 6d rex.W insl \(%dx\),%es:\(%rdi\) -+ c: 66 48 6d data32 rex.W insl \(%dx\),%es:\(%rdi\) ++ c: 66 48 6d data16 rex.W insl \(%dx\),%es:\(%rdi\) + +0+00f <_outs>: + f: 48 6f rex.W outsl %ds:\(%rsi\),\(%dx\) -+ 11: 66 48 6f data32 rex.W outsl %ds:\(%rsi\),\(%dx\) ++ 11: 66 48 6f data16 rex.W outsl %ds:\(%rsi\),\(%dx\) +#pass diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-localpic.d b/gas/testsuite/gas/i386/ilp32/x86-64-localpic.d new file mode 100644 @@ -1311398,7 +1318623,7 @@ index 0000000..c1aff73 +#pass diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-nops-1-core2.d b/gas/testsuite/gas/i386/ilp32/x86-64-nops-1-core2.d new file mode 100644 -index 0000000..2ae7580 +index 0000000..a174c7d --- /dev/null +++ b/gas/testsuite/gas/i386/ilp32/x86-64-nops-1-core2.d @@ -0,0 +1,156 @@ @@ -1311413,25 +1318638,25 @@ index 0000000..2ae7580 + +0+ : +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+10 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+20 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+30 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+40 : +[ ]*[a-f0-9]+: 90 nop @@ -1311439,7 +1318664,7 @@ index 0000000..2ae7580 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+50 : +[ ]*[a-f0-9]+: 90 nop @@ -1311727,7 +1318952,7 @@ index 0000000..b79ccc1 +#pass diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-nops-1-nocona.d b/gas/testsuite/gas/i386/ilp32/x86-64-nops-1-nocona.d new file mode 100644 -index 0000000..ce8a6c7 +index 0000000..dbd6f7a --- /dev/null +++ b/gas/testsuite/gas/i386/ilp32/x86-64-nops-1-nocona.d @@ -0,0 +1,156 @@ @@ -1311742,25 +1318967,25 @@ index 0000000..ce8a6c7 + +0+ : +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+10 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+20 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+30 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+40 : +[ ]*[a-f0-9]+: 90 nop @@ -1311768,7 +1318993,7 @@ index 0000000..ce8a6c7 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+50 : +[ ]*[a-f0-9]+: 90 nop @@ -1312142,7 +1319367,7 @@ index 0000000..41d6dc3 +#pass diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-nops-1.d b/gas/testsuite/gas/i386/ilp32/x86-64-nops-1.d new file mode 100644 -index 0000000..0b653a6 +index 0000000..772fd3e --- /dev/null +++ b/gas/testsuite/gas/i386/ilp32/x86-64-nops-1.d @@ -0,0 +1,156 @@ @@ -1312157,25 +1319382,25 @@ index 0000000..0b653a6 + +0+ : +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+10 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+20 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+30 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+40 : +[ ]*[a-f0-9]+: 90 nop @@ -1312183,7 +1319408,7 @@ index 0000000..0b653a6 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+50 : +[ ]*[a-f0-9]+: 90 nop @@ -1312304,7 +1319529,7 @@ index 0000000..0b653a6 +#pass diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-nops-2.d b/gas/testsuite/gas/i386/ilp32/x86-64-nops-2.d new file mode 100644 -index 0000000..80aa944 +index 0000000..551ceca --- /dev/null +++ b/gas/testsuite/gas/i386/ilp32/x86-64-nops-2.d @@ -0,0 +1,160 @@ @@ -1312319,29 +1319544,29 @@ index 0000000..80aa944 + +0+ : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+10 : +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+20 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+30 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+40 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+50 : +[ ]*[a-f0-9]+: 90 nop @@ -1312349,7 +1319574,7 @@ index 0000000..80aa944 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+60 : +[ ]*[a-f0-9]+: 90 nop @@ -1312470,7 +1319695,7 @@ index 0000000..80aa944 +#pass diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-nops-3.d b/gas/testsuite/gas/i386/ilp32/x86-64-nops-3.d new file mode 100644 -index 0000000..ba65a5a +index 0000000..f59cd8a --- /dev/null +++ b/gas/testsuite/gas/i386/ilp32/x86-64-nops-3.d @@ -0,0 +1,17 @@ @@ -1312486,14 +1319711,14 @@ index 0000000..ba65a5a +0+ : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) +[ ]*[a-f0-9]+: 89 c3 mov %eax,%ebx -+[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) +#pass diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-nops-4-core2.d b/gas/testsuite/gas/i386/ilp32/x86-64-nops-4-core2.d new file mode 100644 -index 0000000..0417100 +index 0000000..02a8a63 --- /dev/null +++ b/gas/testsuite/gas/i386/ilp32/x86-64-nops-4-core2.d @@ -0,0 +1,210 @@ @@ -1312509,29 +1319734,29 @@ index 0000000..0417100 +0+ : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+20 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+40 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+60 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+80 : +[ ]*[a-f0-9]+: 90 nop @@ -1312539,8 +1319764,8 @@ index 0000000..0417100 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+a0 : +[ ]*[a-f0-9]+: 90 nop @@ -1312549,8 +1319774,8 @@ index 0000000..0417100 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data32 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data16 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+c0 : +[ ]*[a-f0-9]+: 90 nop @@ -1312561,7 +1319786,7 @@ index 0000000..0417100 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+e0 : +[ ]*[a-f0-9]+: 90 nop @@ -1312573,7 +1319798,7 @@ index 0000000..0417100 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 0f 1f 84 00 00 00 00 00 nopw 0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+100 : +[ ]*[a-f0-9]+: 90 nop @@ -1312586,7 +1319811,7 @@ index 0000000..0417100 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 84 00 00 00 00 00 nopl 0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+120 : +[ ]*[a-f0-9]+: 90 nop @@ -1312600,7 +1319825,7 @@ index 0000000..0417100 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%rax\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+140 : +[ ]*[a-f0-9]+: 90 nop @@ -1312615,7 +1319840,7 @@ index 0000000..0417100 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+160 : +[ ]*[a-f0-9]+: 90 nop @@ -1312631,7 +1319856,7 @@ index 0000000..0417100 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+180 : +[ ]*[a-f0-9]+: 90 nop @@ -1312648,7 +1319873,7 @@ index 0000000..0417100 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 40 00 nopl 0x0\(%rax\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+1a0 : +[ ]*[a-f0-9]+: 90 nop @@ -1312666,7 +1319891,7 @@ index 0000000..0417100 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 00 nopl \(%rax\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+1c0 : +[ ]*[a-f0-9]+: 90 nop @@ -1312685,7 +1319910,7 @@ index 0000000..0417100 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 90 xchg %ax,%ax -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+1e0 : +[ ]*[a-f0-9]+: 90 nop @@ -1312705,7 +1319930,7 @@ index 0000000..0417100 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) +#pass diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-nops-4-k8.d b/gas/testsuite/gas/i386/ilp32/x86-64-nops-4-k8.d new file mode 100644 @@ -1312947,7 +1320172,7 @@ index 0000000..a00424f +#pass diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-nops-4.d b/gas/testsuite/gas/i386/ilp32/x86-64-nops-4.d new file mode 100644 -index 0000000..ca59e77 +index 0000000..1419098 --- /dev/null +++ b/gas/testsuite/gas/i386/ilp32/x86-64-nops-4.d @@ -0,0 +1,210 @@ @@ -1312963,29 +1320188,29 @@ index 0000000..ca59e77 +0+ : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+20 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+40 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+60 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+80 : +[ ]*[a-f0-9]+: 90 nop @@ -1312993,8 +1320218,8 @@ index 0000000..ca59e77 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+a0 : +[ ]*[a-f0-9]+: 90 nop @@ -1313003,8 +1320228,8 @@ index 0000000..ca59e77 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data32 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data16 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+c0 : +[ ]*[a-f0-9]+: 90 nop @@ -1313015,7 +1320240,7 @@ index 0000000..ca59e77 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+e0 : +[ ]*[a-f0-9]+: 90 nop @@ -1313027,7 +1320252,7 @@ index 0000000..ca59e77 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 0f 1f 84 00 00 00 00 00 nopw 0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+100 : +[ ]*[a-f0-9]+: 90 nop @@ -1313040,7 +1320265,7 @@ index 0000000..ca59e77 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 84 00 00 00 00 00 nopl 0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+120 : +[ ]*[a-f0-9]+: 90 nop @@ -1313054,7 +1320279,7 @@ index 0000000..ca59e77 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%rax\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+140 : +[ ]*[a-f0-9]+: 90 nop @@ -1313069,7 +1320294,7 @@ index 0000000..ca59e77 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+160 : +[ ]*[a-f0-9]+: 90 nop @@ -1313085,7 +1320310,7 @@ index 0000000..ca59e77 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+180 : +[ ]*[a-f0-9]+: 90 nop @@ -1313102,7 +1320327,7 @@ index 0000000..ca59e77 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 40 00 nopl 0x0\(%rax\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+1a0 : +[ ]*[a-f0-9]+: 90 nop @@ -1313120,7 +1320345,7 @@ index 0000000..ca59e77 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 00 nopl \(%rax\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+1c0 : +[ ]*[a-f0-9]+: 90 nop @@ -1313139,7 +1320364,7 @@ index 0000000..ca59e77 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 90 xchg %ax,%ax -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+1e0 : +[ ]*[a-f0-9]+: 90 nop @@ -1313159,11 +1320384,11 @@ index 0000000..ca59e77 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) +#pass diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-nops-5-k8.d b/gas/testsuite/gas/i386/ilp32/x86-64-nops-5-k8.d new file mode 100644 -index 0000000..df2ef59 +index 0000000..9044e99 --- /dev/null +++ b/gas/testsuite/gas/i386/ilp32/x86-64-nops-5-k8.d @@ -0,0 +1,74 @@ @@ -1313198,19 +1320423,19 @@ index 0000000..df2ef59 + +0+40 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+50 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+60 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+70 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+80 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi @@ -1313234,7 +1320459,7 @@ index 0000000..df2ef59 + +0+c0 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+d0 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi @@ -1313243,7 +1320468,7 @@ index 0000000..df2ef59 +#pass diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-nops-5.d b/gas/testsuite/gas/i386/ilp32/x86-64-nops-5.d new file mode 100644 -index 0000000..09a17a8 +index 0000000..d1ec2c5 --- /dev/null +++ b/gas/testsuite/gas/i386/ilp32/x86-64-nops-5.d @@ -0,0 +1,73 @@ @@ -1313277,19 +1320502,19 @@ index 0000000..09a17a8 + +0+40 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+50 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+60 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+70 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+80 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi @@ -1313313,7 +1320538,7 @@ index 0000000..09a17a8 + +0+c0 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+d0 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi @@ -1318556,7 +1325781,7 @@ index 0000000..8cf2cd6 +#pass diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-stack-intel.d b/gas/testsuite/gas/i386/ilp32/x86-64-stack-intel.d new file mode 100644 -index 0000000..f98b8cd +index 0000000..8d684a9 --- /dev/null +++ b/gas/testsuite/gas/i386/ilp32/x86-64-stack-intel.d @@ -0,0 +1,70 @@ @@ -1318572,56 +1325797,56 @@ index 0000000..f98b8cd +[ ]*[a-f0-9]+: 50 push rax +[ ]*[a-f0-9]+: 66 50 push ax +[ ]*[a-f0-9]+: 48 50 rex.W push rax -+[ ]*[a-f0-9]+: 66 48 50 data32 rex.W push rax ++[ ]*[a-f0-9]+: 66 48 50 data16 rex.W push rax +[ ]*[a-f0-9]+: 58 pop rax +[ ]*[a-f0-9]+: 66 58 pop ax +[ ]*[a-f0-9]+: 48 58 rex.W pop rax -+[ ]*[a-f0-9]+: 66 48 58 data32 rex.W pop rax ++[ ]*[a-f0-9]+: 66 48 58 data16 rex.W pop rax +[ ]*[a-f0-9]+: 8f c0 pop rax +[ ]*[a-f0-9]+: 66 8f c0 pop ax +[ ]*[a-f0-9]+: 48 8f c0 rex.W pop rax -+[ ]*[a-f0-9]+: 66 48 8f c0 data32 rex.W pop rax ++[ ]*[a-f0-9]+: 66 48 8f c0 data16 rex.W pop rax +[ ]*[a-f0-9]+: 8f 00 pop QWORD PTR \[rax\] +[ ]*[a-f0-9]+: 66 8f 00 pop WORD PTR \[rax\] +[ ]*[a-f0-9]+: 48 8f 00 rex.W pop QWORD PTR \[rax\] -+[ ]*[a-f0-9]+: 66 48 8f 00 data32 rex.W pop QWORD PTR \[rax\] ++[ ]*[a-f0-9]+: 66 48 8f 00 data16 rex.W pop QWORD PTR \[rax\] +[ ]*[a-f0-9]+: ff d0 call rax +[ ]*[a-f0-9]+: 66 ff d0 call ax +[ ]*[a-f0-9]+: 48 ff d0 rex.W call rax -+[ ]*[a-f0-9]+: 66 48 ff d0 data32 rex.W call rax ++[ ]*[a-f0-9]+: 66 48 ff d0 data16 rex.W call rax +[ ]*[a-f0-9]+: ff 10 call QWORD PTR \[rax\] +[ ]*[a-f0-9]+: 66 ff 10 call WORD PTR \[rax\] +[ ]*[a-f0-9]+: 48 ff 10 rex.W call QWORD PTR \[rax\] -+[ ]*[a-f0-9]+: 66 48 ff 10 data32 rex.W call QWORD PTR \[rax\] ++[ ]*[a-f0-9]+: 66 48 ff 10 data16 rex.W call QWORD PTR \[rax\] +[ ]*[a-f0-9]+: ff e0 jmp rax +[ ]*[a-f0-9]+: 66 ff e0 jmp ax +[ ]*[a-f0-9]+: 48 ff e0 rex.W jmp rax -+[ ]*[a-f0-9]+: 66 48 ff e0 data32 rex.W jmp rax ++[ ]*[a-f0-9]+: 66 48 ff e0 data16 rex.W jmp rax +[ ]*[a-f0-9]+: ff 20 jmp QWORD PTR \[rax\] +[ ]*[a-f0-9]+: 66 ff 20 jmp WORD PTR \[rax\] +[ ]*[a-f0-9]+: 48 ff 20 rex.W jmp QWORD PTR \[rax\] -+[ ]*[a-f0-9]+: 66 48 ff 20 data32 rex.W jmp QWORD PTR \[rax\] ++[ ]*[a-f0-9]+: 66 48 ff 20 data16 rex.W jmp QWORD PTR \[rax\] +[ ]*[a-f0-9]+: ff f0 push rax +[ ]*[a-f0-9]+: 66 ff f0 push ax +[ ]*[a-f0-9]+: 48 ff f0 rex.W push rax -+[ ]*[a-f0-9]+: 66 48 ff f0 data32 rex.W push rax ++[ ]*[a-f0-9]+: 66 48 ff f0 data16 rex.W push rax +[ ]*[a-f0-9]+: ff 30 push QWORD PTR \[rax\] +[ ]*[a-f0-9]+: 66 ff 30 push WORD PTR \[rax\] +[ ]*[a-f0-9]+: 48 ff 30 rex.W push QWORD PTR \[rax\] -+[ ]*[a-f0-9]+: 66 48 ff 30 data32 rex.W push QWORD PTR \[rax\] ++[ ]*[a-f0-9]+: 66 48 ff 30 data16 rex.W push QWORD PTR \[rax\] +[ ]*[a-f0-9]+: 6a ff push 0xffffffffffffffff +[ ]*[a-f0-9]+: 66 6a ff pushw 0xffff +[ ]*[a-f0-9]+: 48 6a ff rex.W push 0xffffffffffffffff -+[ ]*[a-f0-9]+: 66 48 6a ff data32 rex.W push 0xffffffffffffffff ++[ ]*[a-f0-9]+: 66 48 6a ff data16 rex.W push 0xffffffffffffffff +[ ]*[a-f0-9]+: 68 01 02 03 04 push 0x4030201 +[ ]*[a-f0-9]+: 66 68 01 02 pushw 0x201 +[ ]*[a-f0-9]+: 03 04 48 add eax,DWORD PTR \[rax\+rcx\*2\] +[ ]*[a-f0-9]+: 68 01 02 03 04 push 0x4030201 -+[ ]*[a-f0-9]+: 66 48 68 01 02 03 04 data32 rex.W push 0x4030201 ++[ ]*[a-f0-9]+: 66 48 68 01 02 03 04 data16 rex.W push 0x4030201 +[ ]*[a-f0-9]+: 0f a8 push gs +[ ]*[a-f0-9]+: 66 0f a8 pushw gs +[ ]*[a-f0-9]+: 48 0f a8 rex.W push gs -+[ ]*[a-f0-9]+: 66 48 0f a8 data32 rex.W push gs ++[ ]*[a-f0-9]+: 66 48 0f a8 data16 rex.W push gs +[ ]*[a-f0-9]+: 41 0f a8 rex.B push gs +[ ]*[a-f0-9]+: 66 41 0f a8 rex.B pushw gs +[ ]*[a-f0-9]+: 48 rex.W @@ -1318632,7 +1325857,7 @@ index 0000000..f98b8cd +#pass diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-stack-suffix.d b/gas/testsuite/gas/i386/ilp32/x86-64-stack-suffix.d new file mode 100644 -index 0000000..cecab6d +index 0000000..09d3702 --- /dev/null +++ b/gas/testsuite/gas/i386/ilp32/x86-64-stack-suffix.d @@ -0,0 +1,70 @@ @@ -1318648,56 +1325873,56 @@ index 0000000..cecab6d +[ ]*[a-f0-9]+: 50 pushq %rax +[ ]*[a-f0-9]+: 66 50 pushw %ax +[ ]*[a-f0-9]+: 48 50 rex.W pushq %rax -+[ ]*[a-f0-9]+: 66 48 50 data32 rex.W pushq %rax ++[ ]*[a-f0-9]+: 66 48 50 data16 rex.W pushq %rax +[ ]*[a-f0-9]+: 58 popq %rax +[ ]*[a-f0-9]+: 66 58 popw %ax +[ ]*[a-f0-9]+: 48 58 rex.W popq %rax -+[ ]*[a-f0-9]+: 66 48 58 data32 rex.W popq %rax ++[ ]*[a-f0-9]+: 66 48 58 data16 rex.W popq %rax +[ ]*[a-f0-9]+: 8f c0 popq %rax +[ ]*[a-f0-9]+: 66 8f c0 popw %ax +[ ]*[a-f0-9]+: 48 8f c0 rex.W popq %rax -+[ ]*[a-f0-9]+: 66 48 8f c0 data32 rex.W popq %rax ++[ ]*[a-f0-9]+: 66 48 8f c0 data16 rex.W popq %rax +[ ]*[a-f0-9]+: 8f 00 popq \(%rax\) +[ ]*[a-f0-9]+: 66 8f 00 popw \(%rax\) +[ ]*[a-f0-9]+: 48 8f 00 rex.W popq \(%rax\) -+[ ]*[a-f0-9]+: 66 48 8f 00 data32 rex.W popq \(%rax\) ++[ ]*[a-f0-9]+: 66 48 8f 00 data16 rex.W popq \(%rax\) +[ ]*[a-f0-9]+: ff d0 callq \*%rax +[ ]*[a-f0-9]+: 66 ff d0 callw \*%ax +[ ]*[a-f0-9]+: 48 ff d0 rex.W callq \*%rax -+[ ]*[a-f0-9]+: 66 48 ff d0 data32 rex.W callq \*%rax ++[ ]*[a-f0-9]+: 66 48 ff d0 data16 rex.W callq \*%rax +[ ]*[a-f0-9]+: ff 10 callq \*\(%rax\) +[ ]*[a-f0-9]+: 66 ff 10 callw \*\(%rax\) +[ ]*[a-f0-9]+: 48 ff 10 rex.W callq \*\(%rax\) -+[ ]*[a-f0-9]+: 66 48 ff 10 data32 rex.W callq \*\(%rax\) ++[ ]*[a-f0-9]+: 66 48 ff 10 data16 rex.W callq \*\(%rax\) +[ ]*[a-f0-9]+: ff e0 jmpq \*%rax +[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax +[ ]*[a-f0-9]+: 48 ff e0 rex.W jmpq \*%rax -+[ ]*[a-f0-9]+: 66 48 ff e0 data32 rex.W jmpq \*%rax ++[ ]*[a-f0-9]+: 66 48 ff e0 data16 rex.W jmpq \*%rax +[ ]*[a-f0-9]+: ff 20 jmpq \*\(%rax\) +[ ]*[a-f0-9]+: 66 ff 20 jmpw \*\(%rax\) +[ ]*[a-f0-9]+: 48 ff 20 rex.W jmpq \*\(%rax\) -+[ ]*[a-f0-9]+: 66 48 ff 20 data32 rex.W jmpq \*\(%rax\) ++[ ]*[a-f0-9]+: 66 48 ff 20 data16 rex.W jmpq \*\(%rax\) +[ ]*[a-f0-9]+: ff f0 pushq %rax +[ ]*[a-f0-9]+: 66 ff f0 pushw %ax +[ ]*[a-f0-9]+: 48 ff f0 rex.W pushq %rax -+[ ]*[a-f0-9]+: 66 48 ff f0 data32 rex.W pushq %rax ++[ ]*[a-f0-9]+: 66 48 ff f0 data16 rex.W pushq %rax +[ ]*[a-f0-9]+: ff 30 pushq \(%rax\) +[ ]*[a-f0-9]+: 66 ff 30 pushw \(%rax\) +[ ]*[a-f0-9]+: 48 ff 30 rex.W pushq \(%rax\) -+[ ]*[a-f0-9]+: 66 48 ff 30 data32 rex.W pushq \(%rax\) ++[ ]*[a-f0-9]+: 66 48 ff 30 data16 rex.W pushq \(%rax\) +[ ]*[a-f0-9]+: 6a ff pushq \$0xffffffffffffffff +[ ]*[a-f0-9]+: 66 6a ff pushw \$0xffff +[ ]*[a-f0-9]+: 48 6a ff rex.W pushq \$0xffffffffffffffff -+[ ]*[a-f0-9]+: 66 48 6a ff data32 rex.W pushq \$0xffffffffffffffff ++[ ]*[a-f0-9]+: 66 48 6a ff data16 rex.W pushq \$0xffffffffffffffff +[ ]*[a-f0-9]+: 68 01 02 03 04 pushq \$0x4030201 +[ ]*[a-f0-9]+: 66 68 01 02 pushw \$0x201 +[ ]*[a-f0-9]+: 03 04 48 addl \(%rax,%rcx,2\),%eax +[ ]*[a-f0-9]+: 68 01 02 03 04 pushq \$0x4030201 -+[ ]*[a-f0-9]+: 66 48 68 01 02 03 04 data32 rex.W pushq \$0x4030201 ++[ ]*[a-f0-9]+: 66 48 68 01 02 03 04 data16 rex.W pushq \$0x4030201 +[ ]*[a-f0-9]+: 0f a8 pushq %gs +[ ]*[a-f0-9]+: 66 0f a8 pushw %gs +[ ]*[a-f0-9]+: 48 0f a8 rex.W pushq %gs -+[ ]*[a-f0-9]+: 66 48 0f a8 data32 rex.W pushq %gs ++[ ]*[a-f0-9]+: 66 48 0f a8 data16 rex.W pushq %gs +[ ]*[a-f0-9]+: 41 0f a8 rex.B pushq %gs +[ ]*[a-f0-9]+: 66 41 0f a8 rex.B pushw %gs +[ ]*[a-f0-9]+: 48 rex.W @@ -1318708,7 +1325933,7 @@ index 0000000..cecab6d +#pass diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-stack.d b/gas/testsuite/gas/i386/ilp32/x86-64-stack.d new file mode 100644 -index 0000000..fd649e2 +index 0000000..2fe62aa --- /dev/null +++ b/gas/testsuite/gas/i386/ilp32/x86-64-stack.d @@ -0,0 +1,70 @@ @@ -1318724,56 +1325949,56 @@ index 0000000..fd649e2 +[ ]*[a-f0-9]+: 50 push %rax +[ ]*[a-f0-9]+: 66 50 push %ax +[ ]*[a-f0-9]+: 48 50 rex.W push %rax -+[ ]*[a-f0-9]+: 66 48 50 data32 rex.W push %rax ++[ ]*[a-f0-9]+: 66 48 50 data16 rex.W push %rax +[ ]*[a-f0-9]+: 58 pop %rax +[ ]*[a-f0-9]+: 66 58 pop %ax +[ ]*[a-f0-9]+: 48 58 rex.W pop %rax -+[ ]*[a-f0-9]+: 66 48 58 data32 rex.W pop %rax ++[ ]*[a-f0-9]+: 66 48 58 data16 rex.W pop %rax +[ ]*[a-f0-9]+: 8f c0 pop %rax +[ ]*[a-f0-9]+: 66 8f c0 pop %ax +[ ]*[a-f0-9]+: 48 8f c0 rex.W pop %rax -+[ ]*[a-f0-9]+: 66 48 8f c0 data32 rex.W pop %rax ++[ ]*[a-f0-9]+: 66 48 8f c0 data16 rex.W pop %rax +[ ]*[a-f0-9]+: 8f 00 popq \(%rax\) +[ ]*[a-f0-9]+: 66 8f 00 popw \(%rax\) +[ ]*[a-f0-9]+: 48 8f 00 rex.W popq \(%rax\) -+[ ]*[a-f0-9]+: 66 48 8f 00 data32 rex.W popq \(%rax\) ++[ ]*[a-f0-9]+: 66 48 8f 00 data16 rex.W popq \(%rax\) +[ ]*[a-f0-9]+: ff d0 callq \*%rax +[ ]*[a-f0-9]+: 66 ff d0 callw \*%ax +[ ]*[a-f0-9]+: 48 ff d0 rex.W callq \*%rax -+[ ]*[a-f0-9]+: 66 48 ff d0 data32 rex.W callq \*%rax ++[ ]*[a-f0-9]+: 66 48 ff d0 data16 rex.W callq \*%rax +[ ]*[a-f0-9]+: ff 10 callq \*\(%rax\) +[ ]*[a-f0-9]+: 66 ff 10 callw \*\(%rax\) +[ ]*[a-f0-9]+: 48 ff 10 rex.W callq \*\(%rax\) -+[ ]*[a-f0-9]+: 66 48 ff 10 data32 rex.W callq \*\(%rax\) ++[ ]*[a-f0-9]+: 66 48 ff 10 data16 rex.W callq \*\(%rax\) +[ ]*[a-f0-9]+: ff e0 jmpq \*%rax +[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax +[ ]*[a-f0-9]+: 48 ff e0 rex.W jmpq \*%rax -+[ ]*[a-f0-9]+: 66 48 ff e0 data32 rex.W jmpq \*%rax ++[ ]*[a-f0-9]+: 66 48 ff e0 data16 rex.W jmpq \*%rax +[ ]*[a-f0-9]+: ff 20 jmpq \*\(%rax\) +[ ]*[a-f0-9]+: 66 ff 20 jmpw \*\(%rax\) +[ ]*[a-f0-9]+: 48 ff 20 rex.W jmpq \*\(%rax\) -+[ ]*[a-f0-9]+: 66 48 ff 20 data32 rex.W jmpq \*\(%rax\) ++[ ]*[a-f0-9]+: 66 48 ff 20 data16 rex.W jmpq \*\(%rax\) +[ ]*[a-f0-9]+: ff f0 push %rax +[ ]*[a-f0-9]+: 66 ff f0 push %ax +[ ]*[a-f0-9]+: 48 ff f0 rex.W push %rax -+[ ]*[a-f0-9]+: 66 48 ff f0 data32 rex.W push %rax ++[ ]*[a-f0-9]+: 66 48 ff f0 data16 rex.W push %rax +[ ]*[a-f0-9]+: ff 30 pushq \(%rax\) +[ ]*[a-f0-9]+: 66 ff 30 pushw \(%rax\) +[ ]*[a-f0-9]+: 48 ff 30 rex.W pushq \(%rax\) -+[ ]*[a-f0-9]+: 66 48 ff 30 data32 rex.W pushq \(%rax\) ++[ ]*[a-f0-9]+: 66 48 ff 30 data16 rex.W pushq \(%rax\) +[ ]*[a-f0-9]+: 6a ff pushq \$0xffffffffffffffff +[ ]*[a-f0-9]+: 66 6a ff pushw \$0xffff +[ ]*[a-f0-9]+: 48 6a ff rex.W pushq \$0xffffffffffffffff -+[ ]*[a-f0-9]+: 66 48 6a ff data32 rex.W pushq \$0xffffffffffffffff ++[ ]*[a-f0-9]+: 66 48 6a ff data16 rex.W pushq \$0xffffffffffffffff +[ ]*[a-f0-9]+: 68 01 02 03 04 pushq \$0x4030201 +[ ]*[a-f0-9]+: 66 68 01 02 pushw \$0x201 +[ ]*[a-f0-9]+: 03 04 48 add \(%rax,%rcx,2\),%eax +[ ]*[a-f0-9]+: 68 01 02 03 04 pushq \$0x4030201 -+[ ]*[a-f0-9]+: 66 48 68 01 02 03 04 data32 rex.W pushq \$0x4030201 ++[ ]*[a-f0-9]+: 66 48 68 01 02 03 04 data16 rex.W pushq \$0x4030201 +[ ]*[a-f0-9]+: 0f a8 pushq %gs +[ ]*[a-f0-9]+: 66 0f a8 pushw %gs +[ ]*[a-f0-9]+: 48 0f a8 rex.W pushq %gs -+[ ]*[a-f0-9]+: 66 48 0f a8 data32 rex.W pushq %gs ++[ ]*[a-f0-9]+: 66 48 0f a8 data16 rex.W pushq %gs +[ ]*[a-f0-9]+: 41 0f a8 rex.B pushq %gs +[ ]*[a-f0-9]+: 66 41 0f a8 rex.B pushw %gs +[ ]*[a-f0-9]+: 48 rex.W @@ -1322430,95 +1329655,113 @@ index 0000000..94a64f6 + vcvttpd2dq xmm2,[ecx] diff --git a/gas/testsuite/gas/i386/inval-avx512f.l b/gas/testsuite/gas/i386/inval-avx512f.l new file mode 100644 -index 0000000..6c525f0 +index 0000000..b49a1d5 --- /dev/null +++ b/gas/testsuite/gas/i386/inval-avx512f.l -@@ -0,0 +1,77 @@ +@@ -0,0 +1,94 @@ +.*: Assembler messages: -+.*:4: Error: .* +.*:5: Error: .* +.*:6: Error: .* +.*:7: Error: .* +.*:8: Error: .* +.*:9: Error: .* -+.*:11: Error: .* ++.*:10: Error: .* +.*:12: Error: .* -+.*:14: Error: .* ++.*:13: Error: .* +.*:15: Error: .* -+.*:17: Error: .* ++.*:16: Error: .* ++.*:18: Error: .* ++.*:19: Error: .* +.*:20: Error: .* +.*:21: Error: .* +.*:22: Error: .* -+.*:23: Error: .* -+.*:23: Error: .* -+.*:24: Error: .* -+.*:24: Error: .* -+.*:25: Error: .* +.*:25: Error: .* ++.*:26: Error: .* +.*:27: Error: .* +.*:28: Error: .* ++.*:28: Error: .* ++.*:29: Error: .* ++.*:29: Error: .* +.*:30: Error: .* -+.*:31: Error: .* ++.*:30: Error: .* ++.*:32: Error: .* +.*:33: Error: .* +.*:35: Error: .* +.*:36: Error: .* -+.*:37: Error: .* +.*:38: Error: .* +.*:39: Error: .* +.*:40: Error: .* +.*:41: Error: .* ++.*:42: Error: .* ++.*:44: Error: .* ++.*:45: Error: .* ++.*:46: Error: .* ++.*:47: Error: .* ++.*:48: Error: .* ++.*:49: Error: .* ++.*:50: Error: .* +GAS LISTING .* + + +[ ]*1[ ]+# Check illegal AVX512F instructions +[ ]*2[ ]+\.text -+[ ]*3[ ]+_start: -+[ ]*4[ ]+mov \{sae\}, %eax\{%k1\} -+[ ]*5[ ]+mov \{sae\}, %eax -+[ ]*6[ ]+mov %ebx, %eax\{%k2\} -+[ ]*7[ ]+vaddps %zmm3, %zmm1, %zmm2\{z\}\{%k1\}\{z\} -+[ ]*8[ ]+vaddps %zmm3, %zmm1\{%k3\}, %zmm2\{z\} -+[ ]*9[ ]+vaddps %zmm3, %zmm1\{%k1\}, %zmm2\{%k2\} -+[ ]*10[ ]+ -+[ ]*11[ ]+vcvtps2pd \(%eax\), %zmm1\{1to8\} -+[ ]*12[ ]+vcvtps2pd \(%eax\)\{1to16\}, %zmm1 -+[ ]*13[ ]+ -+[ ]*14[ ]+vcvtps2pd \(%eax\)\{%k1\}, %zmm1 -+[ ]*15[ ]+vcvtps2pd \(%eax\)\{z\}, %zmm1 -+[ ]*16[ ]+ -+[ ]*17[ ]+vgatherqpd \(%rdi,%zmm2,8\),%zmm6 -+[ ]*18[ ]+ -+[ ]*19[ ]+\.intel_syntax noprefix -+[ ]*20[ ]+mov eax\{k1\}, \{sae\} -+[ ]*21[ ]+mov eax, \{sae\} -+[ ]*22[ ]+mov eax\{k2\}, ebx -+[ ]*23[ ]+vaddps zmm2\{z\}\{k1\}\{z\}, zmm1, zmm3 -+[ ]*24[ ]+vaddps zmm2\{z\}, zmm1\{k3\}, zmm3 -+[ ]*25[ ]+vaddps zmm2\{k2\}, zmm1\{k1\}, zmm3 -+[ ]*26[ ]+ -+[ ]*27[ ]+vcvtps2pd zmm1\{1to8\}, \[eax\] -+[ ]*28[ ]+vcvtps2pd zmm1, \[eax\]\{1to16\} -+[ ]*29[ ]+ -+[ ]*30[ ]+vcvtps2pd zmm1, \[eax\]\{k1\} -+[ ]*31[ ]+vcvtps2pd zmm1, \[eax\]\{z\} -+[ ]*32[ ]+ -+[ ]*33[ ]+vgatherqpd zmm6, ZMMWORD PTR \[rdi\+zmm2\*8\] ++[ ]*3[ ]+\.allow_index_reg ++[ ]*4[ ]+_start: ++[ ]*5[ ]+mov \{sae\}, %eax\{%k1\} ++[ ]*6[ ]+mov \{sae\}, %eax ++[ ]*7[ ]+mov %ebx, %eax\{%k2\} ++[ ]*8[ ]+vaddps %zmm3, %zmm1, %zmm2\{z\}\{%k1\}\{z\} ++[ ]*9[ ]+vaddps %zmm3, %zmm1\{%k3\}, %zmm2\{z\} ++[ ]*10[ ]+vaddps %zmm3, %zmm1\{%k1\}, %zmm2\{%k2\} ++[ ]*11[ ]+ ++[ ]*12[ ]+vcvtps2pd \(%eax\), %zmm1\{1to8\} ++[ ]*13[ ]+vcvtps2pd \(%eax\)\{1to16\}, %zmm1 ++[ ]*14[ ]+ ++[ ]*15[ ]+vcvtps2pd \(%eax\)\{%k1\}, %zmm1 ++[ ]*16[ ]+vcvtps2pd \(%eax\)\{z\}, %zmm1 ++[ ]*17[ ]+ ++[ ]*18[ ]+vgatherqpd \(%rdi,%zmm2,8\),%zmm6 ++[ ]*19[ ]+vgatherqpd \(%edi\),%zmm6\{%k1\} ++[ ]*20[ ]+vgatherqpd \(%zmm2\),%zmm6\{%k1\} ++[ ]*21[ ]+vpscatterdd %zmm6,\(%edi\)\{%k1\} ++[ ]*22[ ]+vpscatterdd %zmm6,\(%zmm2\)\{%k1\} ++[ ]*23[ ]+ ++[ ]*24[ ]+\.intel_syntax noprefix ++[ ]*25[ ]+mov eax\{k1\}, \{sae\} ++[ ]*26[ ]+mov eax, \{sae\} ++[ ]*27[ ]+mov eax\{k2\}, ebx ++[ ]*28[ ]+vaddps zmm2\{z\}\{k1\}\{z\}, zmm1, zmm3 ++[ ]*29[ ]+vaddps zmm2\{z\}, zmm1\{k3\}, zmm3 ++[ ]*30[ ]+vaddps zmm2\{k2\}, zmm1\{k1\}, zmm3 ++[ ]*31[ ]+ ++[ ]*32[ ]+vcvtps2pd zmm1\{1to8\}, \[eax\] ++[ ]*33[ ]+vcvtps2pd zmm1, \[eax\]\{1to16\} +[ ]*34[ ]+ -+[ ]*35[ ]+vaddps zmm2, zmm1, QWORD PTR \[eax\]\{1to8\} -+[ ]*36[ ]+vaddps zmm2, zmm1, QWORD PTR \[eax\]\{1to16\} -+[ ]*37[ ]+vaddpd zmm2, zmm1, DWORD PTR \[eax\]\{1to8\} -+[ ]*38[ ]+vaddpd zmm2, zmm1, DWORD PTR \[eax\]\{1to16\} -+[ ]*39[ ]+vaddps zmm2, zmm1, ZMMWORD PTR \[eax\]\{1to16\} -+[ ]*40[ ]+vaddps zmm2, zmm1, DWORD PTR \[eax\] -+[ ]*41[ ]+vaddpd zmm2, zmm1, QWORD PTR \[eax\] ++[ ]*35[ ]+vcvtps2pd zmm1, \[eax\]\{k1\} ++[ ]*36[ ]+vcvtps2pd zmm1, \[eax\]\{z\} ++[ ]*37[ ]+ ++[ ]*38[ ]+vgatherqpd zmm6, ZMMWORD PTR \[rdi\+zmm2\*8\] ++[ ]*39[ ]+vgatherqpd zmm6\{k1\}, ZMMWORD PTR \[edi\] ++[ ]*40[ ]+vgatherqpd zmm6\{k1\}, ZMMWORD PTR \[zmm2\+eiz\] ++[ ]*41[ ]+vpscatterdd ZMMWORD PTR \[edi\]\{k1\}, zmm6 ++[ ]*42[ ]+vpscatterdd ZMMWORD PTR \[zmm2\+eiz\]\{k1\}, zmm6 ++[ ]*43[ ]+ ++[ ]*44[ ]+vaddps zmm2, zmm1, QWORD PTR \[eax\]\{1to8\} ++[ ]*45[ ]+vaddps zmm2, zmm1, QWORD PTR \[eax\]\{1to16\} ++[ ]*46[ ]+vaddpd zmm2, zmm1, DWORD PTR \[eax\]\{1to8\} ++[ ]*47[ ]+vaddpd zmm2, zmm1, DWORD PTR \[eax\]\{1to16\} ++[ ]*48[ ]+vaddps zmm2, zmm1, ZMMWORD PTR \[eax\]\{1to16\} ++[ ]*49[ ]+vaddps zmm2, zmm1, DWORD PTR \[eax\] ++[ ]*50[ ]+vaddpd zmm2, zmm1, QWORD PTR \[eax\] diff --git a/gas/testsuite/gas/i386/inval-avx512f.s b/gas/testsuite/gas/i386/inval-avx512f.s new file mode 100644 -index 0000000..b1ddba4 +index 0000000..f723c5a --- /dev/null +++ b/gas/testsuite/gas/i386/inval-avx512f.s -@@ -0,0 +1,41 @@ +@@ -0,0 +1,50 @@ +# Check illegal AVX512F instructions + .text ++ .allow_index_reg +_start: + mov {sae}, %eax{%k1} + mov {sae}, %eax @@ -1322534,6 +1329777,10 @@ index 0000000..b1ddba4 + vcvtps2pd (%eax){z}, %zmm1 + + vgatherqpd (%rdi,%zmm2,8),%zmm6 ++ vgatherqpd (%edi),%zmm6{%k1} ++ vgatherqpd (%zmm2),%zmm6{%k1} ++ vpscatterdd %zmm6,(%edi){%k1} ++ vpscatterdd %zmm6,(%zmm2){%k1} + + .intel_syntax noprefix + mov eax{k1}, {sae} @@ -1322550,6 +1329797,10 @@ index 0000000..b1ddba4 + vcvtps2pd zmm1, [eax]{z} + + vgatherqpd zmm6, ZMMWORD PTR [rdi+zmm2*8] ++ vgatherqpd zmm6{k1}, ZMMWORD PTR [edi] ++ vgatherqpd zmm6{k1}, ZMMWORD PTR [zmm2+eiz] ++ vpscatterdd ZMMWORD PTR [edi]{k1}, zmm6 ++ vpscatterdd ZMMWORD PTR [zmm2+eiz]{k1}, zmm6 + + vaddps zmm2, zmm1, QWORD PTR [eax]{1to8} + vaddps zmm2, zmm1, QWORD PTR [eax]{1to16} @@ -1322733,7 +1329984,7 @@ index 0000000..fd5ed48 + mov bar2,%eax diff --git a/gas/testsuite/gas/i386/inval-equ-2.l b/gas/testsuite/gas/i386/inval-equ-2.l new file mode 100644 -index 0000000..7a4f483 +index 0000000..eafaf25 --- /dev/null +++ b/gas/testsuite/gas/i386/inval-equ-2.l @@ -0,0 +1,21 @@ @@ -1322754,9 +1330005,9 @@ index 0000000..7a4f483 +[ ]*6[ ]+\.globl bar2 +[ ]*7[ ]+\.set bar3,\(%eax\+1\) +[ ]*8[ ]+\?\?\?\? A12A0000 mov bar3,%eax -+\*\*\*\* Error:can't make global register symbol `bar1' -+\*\*\*\* Error:can't make global register symbol `bar2' -+\*\*\*\* Error:can't make global register symbol `bar3' ++.* Error: can't make global register symbol `bar1' ++.* Error: can't make global register symbol `bar2' ++.* Error: can't make global register symbol `bar3' +[ ]*8[ ]+00 diff --git a/gas/testsuite/gas/i386/inval-equ-2.s b/gas/testsuite/gas/i386/inval-equ-2.s new file mode 100644 @@ -1324004,10 +1331255,10 @@ index 0000000..1a796d8 +#pass diff --git a/gas/testsuite/gas/i386/katmai.d b/gas/testsuite/gas/i386/katmai.d new file mode 100644 -index 0000000..a1c6b97 +index 0000000..50e573f --- /dev/null +++ b/gas/testsuite/gas/i386/katmai.d -@@ -0,0 +1,166 @@ +@@ -0,0 +1,165 @@ +#objdump: -dw +#name: i386 katmai + @@ -1324170,8 +1331421,7 @@ index 0000000..a1c6b97 + 237: 0f 18 0c 98 [ ]*prefetcht0 \(%eax,%ebx,4\) + 23b: 0f 18 12 [ ]*prefetcht1 \(%edx\) + 23e: 0f 18 19 [ ]*prefetcht2 \(%ecx\) -+ 241: 65 [ ]*gs -+ 242: 0f ae[ ]*\(bad\).* ++ 241: 65 0f ae[ ]*gs \(bad\).* + 244: ff 00 [ ]*incl \(%eax\) +#pass diff --git a/gas/testsuite/gas/i386/katmai.s b/gas/testsuite/gas/i386/katmai.s @@ -1325258,7 +1332508,7 @@ index 0000000..0dd493a + lock xor eax,DWORD PTR [ebx] diff --git a/gas/testsuite/gas/i386/long-1-intel.d b/gas/testsuite/gas/i386/long-1-intel.d new file mode 100644 -index 0000000..7a73462 +index 0000000..2e52136 --- /dev/null +++ b/gas/testsuite/gas/i386/long-1-intel.d @@ -0,0 +1,14 @@ @@ -1325272,13 +1332522,13 @@ index 0000000..7a73462 +Disassembly of section .text: + +0+ : -+[ ]*[a-f0-9]+: f2 f0 f0 f0 f2 f2 f2 f2 f2 f2 f0 f0 66 0f 28 repnz lock lock lock repnz repnz repnz repnz repnz repnz lock lock \(bad\) ++[ ]*[a-f0-9]+: f2 f0 f0 f0 f2 f2 f2 f2 f2 f2 f0 f0 f3 0f 10 repnz lock lock lock repnz repnz repnz repnz repnz repnz lock lock \(bad\) +[ ]*[a-f0-9]+: 00 f2 add dl,dh -+[ ]*[a-f0-9]+: f0 f0 f0 f2 f2 f2 f2 f0 f0 f0 f0 66 0f 28 00 lock lock lock repnz repnz repnz repnz lock lock lock lock movapd xmm0,XMMWORD PTR \[eax\] ++[ ]*[a-f0-9]+: f0 f0 f0 f2 f2 f2 f2 f0 f0 f0 f0 f3 0f 10 00 lock lock lock repnz repnz repnz repnz lock lock lock lock movss xmm0,DWORD PTR \[eax\] +#pass diff --git a/gas/testsuite/gas/i386/long-1.d b/gas/testsuite/gas/i386/long-1.d new file mode 100644 -index 0000000..1dccd36 +index 0000000..a8cd073 --- /dev/null +++ b/gas/testsuite/gas/i386/long-1.d @@ -0,0 +1,13 @@ @@ -1325291,13 +1332541,13 @@ index 0000000..1dccd36 +Disassembly of section .text: + +0+ : -+[ ]*[a-f0-9]+: f2 f0 f0 f0 f2 f2 f2 f2 f2 f2 f0 f0 66 0f 28 repnz lock lock lock repnz repnz repnz repnz repnz repnz lock lock \(bad\) ++[ ]*[a-f0-9]+: f2 f0 f0 f0 f2 f2 f2 f2 f2 f2 f0 f0 f3 0f 10 repnz lock lock lock repnz repnz repnz repnz repnz repnz lock lock \(bad\) +[ ]*[a-f0-9]+: 00 f2 add %dh,%dl -+[ ]*[a-f0-9]+: f0 f0 f0 f2 f2 f2 f2 f0 f0 f0 f0 66 0f 28 00 lock lock lock repnz repnz repnz repnz lock lock lock lock movapd \(%eax\),%xmm0 ++[ ]*[a-f0-9]+: f0 f0 f0 f2 f2 f2 f2 f0 f0 f0 f0 f3 0f 10 00 lock lock lock repnz repnz repnz repnz lock lock lock lock movss \(%eax\),%xmm0 +#pass diff --git a/gas/testsuite/gas/i386/long-1.s b/gas/testsuite/gas/i386/long-1.s new file mode 100644 -index 0000000..4551068 +index 0000000..b7e509d --- /dev/null +++ b/gas/testsuite/gas/i386/long-1.s @@ -0,0 +1,30 @@ @@ -1325317,7 +1332567,7 @@ index 0000000..4551068 +.byte 0xf2 +.byte 0xf0 +.byte 0xf0 -+movapd (%eax), %xmm0 ++movss (%eax), %xmm0 +.byte 0xf2 +.byte 0xf0 +.byte 0xf0 @@ -1325330,7 +1332580,7 @@ index 0000000..4551068 +.byte 0xf0 +.byte 0xf0 +.byte 0xf0 -+movapd (%eax), %xmm0 ++movss (%eax), %xmm0 diff --git a/gas/testsuite/gas/i386/lwp.d b/gas/testsuite/gas/i386/lwp.d new file mode 100644 index 0000000..ecb38f1 @@ -1329494,7 +1336744,7 @@ index 0000000..638dafa + loop foo diff --git a/gas/testsuite/gas/i386/mpx-inval-1.l b/gas/testsuite/gas/i386/mpx-inval-1.l new file mode 100644 -index 0000000..41de5a0 +index 0000000..121aad6 --- /dev/null +++ b/gas/testsuite/gas/i386/mpx-inval-1.l @@ -0,0 +1,55 @@ @@ -1329522,37 +1336772,37 @@ index 0000000..41de5a0 +[ ]*4[ ]+\.extern xxx +[ ]*5[ ]+foo: +[ ]*6[ ]+\?\?\?\? F201C3 bnd add %eax, %ebx \# Bad -+\*\*\*\* Error:expecting valid branch instruction after `bnd' ++.* Error: expecting valid branch instruction after `bnd' +[ ]*7[ ]+\?\?\?\? 66F2AB bnd stosw \(%edi\) \# Bad -+\*\*\*\* Error:expecting valid branch instruction after `bnd' ++.* Error: expecting valid branch instruction after `bnd' +[ ]*8[ ]+\?\?\?\? 9A000000 bnd lcall \$0x1234,\$xxx -+\*\*\*\* Error:expecting valid branch instruction after `bnd' -+\*\*\*\* Warning:skipping prefixes on this instruction ++.* Error: expecting valid branch instruction after `bnd' ++.* Warning: skipping prefixes on this instruction +[ ]*8[ ]+003412 +[ ]*9[ ]+\?\?\?\? EA000000 bnd ljmp \$0x1234,\$xxx -+\*\*\*\* Error:expecting valid branch instruction after `bnd' -+\*\*\*\* Warning:skipping prefixes on this instruction ++.* Error: expecting valid branch instruction after `bnd' ++.* Warning: skipping prefixes on this instruction +[ ]*9[ ]+003412 +[ ]*10[ ]+\?\?\?\? F2E200 bnd loop foo -+\*\*\*\* Error:expecting valid branch instruction after `bnd' ++.* Error: expecting valid branch instruction after `bnd' +[ ]*11[ ]+\?\?\?\? 67F2E300 bnd jcxz foo -+\*\*\*\* Error:expecting valid branch instruction after `bnd' ++.* Error: expecting valid branch instruction after `bnd' +[ ]*12[ ]+ +[ ]*13[ ]+\.intel_syntax noprefix +[ ]*14[ ]+\?\?\?\? F201C3 bnd add ebx, eax \# Bad -+\*\*\*\* Error:expecting valid branch instruction after `bnd' ++.* Error: expecting valid branch instruction after `bnd' +[ ]*15[ ]+\?\?\?\? 66F2AB bnd stos WORD PTR\[edi] \# Bad -+\*\*\*\* Error:expecting valid branch instruction after `bnd' ++.* Error: expecting valid branch instruction after `bnd' +[ ]*16[ ]+\?\?\?\? 9A000000 bnd lcall 0x1234,xxx -+\*\*\*\* Error:expecting valid branch instruction after `bnd' ++.* Error: expecting valid branch instruction after `bnd' +[ ]*16[ ]+003412 +[ ]*17[ ]+\?\?\?\? EA000000 bnd ljmp 0x1234,xxx -+\*\*\*\* Error:expecting valid branch instruction after `bnd' ++.* Error: expecting valid branch instruction after `bnd' +[ ]*17[ ]+003412 +[ ]*18[ ]+\?\?\?\? F2E200 bnd loop foo -+\*\*\*\* Error:expecting valid branch instruction after `bnd' ++.* Error: expecting valid branch instruction after `bnd' +[ ]*19[ ]+\?\?\?\? 67F2E300 bnd jcxz foo -+\*\*\*\* Error:expecting valid branch instruction after `bnd' ++.* Error: expecting valid branch instruction after `bnd' diff --git a/gas/testsuite/gas/i386/mpx-inval-1.s b/gas/testsuite/gas/i386/mpx-inval-1.s new file mode 100644 index 0000000..74de4f7 @@ -1331061,7 +1338311,7 @@ index 0000000..7e88b61 +#pass diff --git a/gas/testsuite/gas/i386/nops-1-core2.d b/gas/testsuite/gas/i386/nops-1-core2.d new file mode 100644 -index 0000000..4215408 +index 0000000..f9e2d43 --- /dev/null +++ b/gas/testsuite/gas/i386/nops-1-core2.d @@ -0,0 +1,157 @@ @@ -1331077,25 +1338327,25 @@ index 0000000..4215408 + +0+ : +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+10 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+20 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+30 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+40 : +[ ]*[a-f0-9]+: 90 nop @@ -1331103,7 +1338353,7 @@ index 0000000..4215408 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+50 : +[ ]*[a-f0-9]+: 90 nop @@ -1334984,7 +1342234,7 @@ index 0000000..103ca36 +align: diff --git a/gas/testsuite/gas/i386/nops-4a-i686.d b/gas/testsuite/gas/i386/nops-4a-i686.d new file mode 100644 -index 0000000..b8ac733 +index 0000000..14d88d4 --- /dev/null +++ b/gas/testsuite/gas/i386/nops-4a-i686.d @@ -0,0 +1,210 @@ @@ -1335000,29 +1342250,29 @@ index 0000000..b8ac733 +0+ : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+20 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+40 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+60 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+80 : +[ ]*[a-f0-9]+: 90 nop @@ -1335030,8 +1342280,8 @@ index 0000000..b8ac733 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+a0 : +[ ]*[a-f0-9]+: 90 nop @@ -1335040,8 +1342290,8 @@ index 0000000..b8ac733 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data32 nopw %cs:0x0\(%eax,%eax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data16 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+c0 : +[ ]*[a-f0-9]+: 90 nop @@ -1335052,7 +1342302,7 @@ index 0000000..b8ac733 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%eax,%eax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+e0 : +[ ]*[a-f0-9]+: 90 nop @@ -1335064,7 +1342314,7 @@ index 0000000..b8ac733 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 0f 1f 84 00 00 00 00 00 nopw 0x0\(%eax,%eax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+100 : +[ ]*[a-f0-9]+: 90 nop @@ -1335077,7 +1342327,7 @@ index 0000000..b8ac733 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 84 00 00 00 00 00 nopl 0x0\(%eax,%eax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+120 : +[ ]*[a-f0-9]+: 90 nop @@ -1335091,7 +1342341,7 @@ index 0000000..b8ac733 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%eax\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+140 : +[ ]*[a-f0-9]+: 90 nop @@ -1335106,7 +1342356,7 @@ index 0000000..b8ac733 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%eax,%eax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+160 : +[ ]*[a-f0-9]+: 90 nop @@ -1335122,7 +1342372,7 @@ index 0000000..b8ac733 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%eax,%eax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+180 : +[ ]*[a-f0-9]+: 90 nop @@ -1335139,7 +1342389,7 @@ index 0000000..b8ac733 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 40 00 nopl 0x0\(%eax\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+1a0 : +[ ]*[a-f0-9]+: 90 nop @@ -1335157,7 +1342407,7 @@ index 0000000..b8ac733 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 00 nopl \(%eax\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+1c0 : +[ ]*[a-f0-9]+: 90 nop @@ -1335176,7 +1342426,7 @@ index 0000000..b8ac733 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 90 xchg %ax,%ax -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+1e0 : +[ ]*[a-f0-9]+: 90 nop @@ -1335196,11 +1342446,11 @@ index 0000000..b8ac733 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) +#pass diff --git a/gas/testsuite/gas/i386/nops-5-i686.d b/gas/testsuite/gas/i386/nops-5-i686.d new file mode 100644 -index 0000000..1d42128 +index 0000000..b018441 --- /dev/null +++ b/gas/testsuite/gas/i386/nops-5-i686.d @@ -0,0 +1,74 @@ @@ -1335235,19 +1342485,19 @@ index 0000000..1d42128 + +0+40 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+50 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+60 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+70 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+80 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi @@ -1335271,7 +1342521,7 @@ index 0000000..1d42128 + +0+c0 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+d0 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi @@ -1335280,7 +1342530,7 @@ index 0000000..1d42128 +#pass diff --git a/gas/testsuite/gas/i386/nops-5.d b/gas/testsuite/gas/i386/nops-5.d new file mode 100644 -index 0000000..abff3cc +index 0000000..ff30708 --- /dev/null +++ b/gas/testsuite/gas/i386/nops-5.d @@ -0,0 +1,72 @@ @@ -1335313,19 +1342563,19 @@ index 0000000..abff3cc + +0+40 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+50 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+60 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+70 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+80 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi @@ -1335349,7 +1342599,7 @@ index 0000000..abff3cc + +0+c0 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%eax,%eax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%eax,%eax,1\) + +0+d0 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi @@ -1340248,12 +1347498,74 @@ index 0000000..c0f92ae + +intel_prefetch: + try 0x0f, 0x18 +diff --git a/gas/testsuite/gas/i386/prefetchwt1-intel.d b/gas/testsuite/gas/i386/prefetchwt1-intel.d +new file mode 100644 +index 0000000..c8b1f62 +--- /dev/null ++++ b/gas/testsuite/gas/i386/prefetchwt1-intel.d +@@ -0,0 +1,16 @@ ++#as: ++#objdump: -dwMintel ++#name: i386 PREFETCHWT1 insns (Intel disassembly) ++#source: prefetchwt1.s ++ ++.*: +file format .* ++ ++ ++Disassembly of section .text: ++ ++0+ <_start>: ++[ ]*[a-f0-9]+: 0f 0d 11 prefetchwt1 BYTE PTR \[ecx\] ++[ ]*[a-f0-9]+: 0f 0d 94 f4 c0 1d fe ff prefetchwt1 BYTE PTR \[esp\+esi\*8-0x1e240\] ++[ ]*[a-f0-9]+: 0f 0d 11 prefetchwt1 BYTE PTR \[ecx\] ++[ ]*[a-f0-9]+: 0f 0d 94 f4 c0 1d fe ff prefetchwt1 BYTE PTR \[esp\+esi\*8-0x1e240\] ++#pass +diff --git a/gas/testsuite/gas/i386/prefetchwt1.d b/gas/testsuite/gas/i386/prefetchwt1.d +new file mode 100644 +index 0000000..a1073de +--- /dev/null ++++ b/gas/testsuite/gas/i386/prefetchwt1.d +@@ -0,0 +1,15 @@ ++#as: ++#objdump: -dw ++#name: i386 PREFETCHWT1 insns ++ ++.*: +file format .* ++ ++ ++Disassembly of section .text: ++ ++0+ <_start>: ++[ ]*[a-f0-9]+: 0f 0d 11 prefetchwt1 \(%ecx\) ++[ ]*[a-f0-9]+: 0f 0d 94 f4 c0 1d fe ff prefetchwt1 -0x1e240\(%esp,%esi,8\) ++[ ]*[a-f0-9]+: 0f 0d 11 prefetchwt1 \(%ecx\) ++[ ]*[a-f0-9]+: 0f 0d 94 f4 c0 1d fe ff prefetchwt1 -0x1e240\(%esp,%esi,8\) ++#pass +diff --git a/gas/testsuite/gas/i386/prefetchwt1.s b/gas/testsuite/gas/i386/prefetchwt1.s +new file mode 100644 +index 0000000..ae1b01a +--- /dev/null ++++ b/gas/testsuite/gas/i386/prefetchwt1.s +@@ -0,0 +1,13 @@ ++# Check 32bit AVX512PF instructions ++ ++ .allow_index_reg ++ .text ++_start: ++ ++ prefetchwt1 (%ecx) ++ prefetchwt1 -123456(%esp,%esi,8) ++ ++ .intel_syntax noprefix ++ ++ prefetchwt1 BYTE PTR [ecx] ++ prefetchwt1 BYTE PTR [esp+esi*8-123456] diff --git a/gas/testsuite/gas/i386/prefix.d b/gas/testsuite/gas/i386/prefix.d new file mode 100644 -index 0000000..e155230 +index 0000000..a334ab8 --- /dev/null +++ b/gas/testsuite/gas/i386/prefix.d -@@ -0,0 +1,14 @@ +@@ -0,0 +1,66 @@ +#objdump: -dw +#name: i386 prefix + @@ -1340261,23 +1347573,432 @@ index 0000000..e155230 + +Disassembly of section .text: + -+0+000 : -+ 0: 9b 26 67 d9 3c[ ]+fstcw[ ]+%es:\(%si\) -+ 5: 9b df e0 [ ]*fstsw %ax -+ 8: 9b df e0 [ ]*fstsw %ax -+ b: 9b 67 df e0 [ ]*addr16 fstsw %ax -+ f: 36 67 66 f3 a7 [ ]*repz cmpsw %es:\(%di\),%ss:\(%si\) ++0+ : ++[ ]*[a-f0-9]+: 9b 26 67 d9 3c fstcw %es:\(%si\) ++[ ]*[a-f0-9]+: 9b df e0 fstsw %ax ++[ ]*[a-f0-9]+: 9b df e0 fstsw %ax ++[ ]*[a-f0-9]+: 9b 67 df e0 addr16 fstsw %ax ++[ ]*[a-f0-9]+: 36 67 66 f3 a7 repz cmpsw %es:\(%di\),%ss:\(%si\) ++[ ]*[a-f0-9]+: 26 9b es fwait ++[ ]*[a-f0-9]+: 9b fwait ++[ ]*[a-f0-9]+: 65 c7 05 00 00 00 00 00 00 00 00 movl \$0x0,%gs:0x0 ++[ ]*[a-f0-9]+: 66 f2 0f 38 17 data16 \(bad\) ++[ ]*[a-f0-9]+: f2 66 0f 54 repnz \(bad\) ++[ ]*[a-f0-9]+: f2 0f 54 repnz \(bad\) ++[ ]*[a-f0-9]+: f2 66 0f 11 22 data16 movsd %xmm4,\(%edx\) ++[ ]*[a-f0-9]+: f2 67 66 0f 11 22 data16 movsd %xmm4,\(%bp,%si\) ++[ ]*[a-f0-9]+: f2 67 f0 66 0f 11 22 lock data16 movsd %xmm4,\(%bp,%si\) ++[ ]*[a-f0-9]+: f3 66 0f 11 22 data16 movss %xmm4,\(%edx\) ++[ ]*[a-f0-9]+: f3 67 f0 66 0f 11 22 lock data16 movss %xmm4,\(%bp,%si\) ++[ ]*[a-f0-9]+: f3 67 f2 66 0f 11 22 repz data16 movsd %xmm4,\(%bp,%si\) ++[ ]*[a-f0-9]+: f3 66 3e 0f 11 22 data16 movss %xmm4,%ds:\(%edx\) ++[ ]*[a-f0-9]+: f2 66 36 0f 11 22 data16 movsd %xmm4,%ss:\(%edx\) ++[ ]*[a-f0-9]+: f3 f0 f2 66 36 0f 11 22 repz lock data16 movsd %xmm4,%ss:\(%edx\) ++[ ]*[a-f0-9]+: f2 66 3e 36 0f 11 22 data16 ds movsd %xmm4,%ss:\(%edx\) ++[ ]*[a-f0-9]+: f2 67 66 3e 36 0f 11 22 data16 ds movsd %xmm4,%ss:\(%bp,%si\) ++[ ]*[a-f0-9]+: f2 67 f0 66 3e 36 0f 11 22 lock data16 ds movsd %xmm4,%ss:\(%bp,%si\) ++[ ]*[a-f0-9]+: f3 66 3e 36 0f 11 22 data16 ds movss %xmm4,%ss:\(%edx\) ++[ ]*[a-f0-9]+: f3 f0 66 3e 36 0f 11 22 lock data16 ds movss %xmm4,%ss:\(%edx\) ++[ ]*[a-f0-9]+: f3 67 f2 66 3e 36 0f 11 22 repz data16 ds movsd %xmm4,%ss:\(%bp,%si\) ++[ ]*[a-f0-9]+: f2 66 90 repnz xchg %ax,%ax ++[ ]*[a-f0-9]+: f2 67 66 90 repnz addr16 xchg %ax,%ax ++[ ]*[a-f0-9]+: f2 67 f0 66 90 repnz addr16 lock xchg %ax,%ax ++[ ]*[a-f0-9]+: f3 66 90 data16 pause ++[ ]*[a-f0-9]+: f3 67 f0 66 90 addr16 lock data16 pause ++[ ]*[a-f0-9]+: f3 67 f2 66 90 repz addr16 repnz xchg %ax,%ax ++[ ]*[a-f0-9]+: f2 3e 90 repnz ds nop ++[ ]*[a-f0-9]+: f2 f0 67 3e 90 repnz lock addr16 ds nop ++[ ]*[a-f0-9]+: f3 3e 90 ds pause ++[ ]*[a-f0-9]+: f3 66 3e 90 data16 ds pause ++[ ]*[a-f0-9]+: f3 f0 3e 90 lock ds pause ++[ ]*[a-f0-9]+: f3 f0 67 3e 90 lock addr16 ds pause ++[ ]*[a-f0-9]+: f3 f2 67 3e 90 repz repnz addr16 ds nop ++[ ]*[a-f0-9]+: 66 f0 36 90 lock ss xchg %ax,%ax ++[ ]*[a-f0-9]+: f2 36 90 repnz ss nop ++[ ]*[a-f0-9]+: f2 66 36 90 repnz ss xchg %ax,%ax ++[ ]*[a-f0-9]+: f2 f0 36 90 repnz lock ss nop ++[ ]*[a-f0-9]+: f2 f0 67 36 90 repnz lock addr16 ss nop ++[ ]*[a-f0-9]+: f3 36 90 ss pause ++[ ]*[a-f0-9]+: f3 67 36 90 addr16 ss pause ++[ ]*[a-f0-9]+: f3 f0 67 36 90 lock addr16 ss pause ++[ ]*[a-f0-9]+: f3 f2 36 90 repz repnz ss nop ++[ ]*[a-f0-9]+: f3 f2 67 36 90 repz repnz addr16 ss nop ++[ ]*[a-f0-9]+: f3 f0 f2 66 36 90 repz lock repnz ss xchg %ax,%ax ++[ ]*[a-f0-9]+: 66 3e 36 90 ds ss xchg %ax,%ax ++[ ]*[a-f0-9]+: 67 66 3e 36 90 addr16 ds ss xchg %ax,%ax ++[ ]*[a-f0-9]+: 67 f0 66 3e 36 90 addr16 lock ds ss xchg %ax,%ax ++[ ]*[a-f0-9]+: f3 66 3e 36 90 data16 ds ss pause ++[ ]*[a-f0-9]+: f3 f0 66 3e 36 90 lock data16 ds ss pause ++[ ]*[a-f0-9]+: f3 f2 67 3e 36 90 repz repnz addr16 ds ss nop ++[ ]*[a-f0-9]+: f3 67 f2 66 3e 36 90 repz addr16 repnz ds ss xchg %ax,%ax +#pass diff --git a/gas/testsuite/gas/i386/prefix.s b/gas/testsuite/gas/i386/prefix.s new file mode 100644 -index 0000000..a141ad5 +index 0000000..9f90afa --- /dev/null +++ b/gas/testsuite/gas/i386/prefix.s -@@ -0,0 +1,6 @@ +@@ -0,0 +1,363 @@ +.text ; foo: addr16 fstcw %es:(%si) + fstsw; fstsw %ax; + addr16 fstsw %ax ;addr16 rep cmpsw %es:(%di),%ss:(%si) + ++ es fwait ++ ++ fwait ++ movl $0,%gs:fpu_owner_task ++ ++ .byte 0x66 ++ .byte 0xf2 ++ .byte 0x0f ++ .byte 0x38 ++ .byte 0x17 ++ ++ .byte 0xf2 ++ .byte 0x66 ++ .byte 0x0f ++ .byte 0x54 ++ ++ .byte 0xf2 ++ .byte 0x0f ++ .byte 0x54 ++ ++# data16 movsd %xmm4,(%edx) ++ .byte 0xf2 ++ .byte 0x66 ++ .byte 0x0f ++ .byte 0x11 ++ .byte 0x22 ++ ++# data16 movsd %xmm4,(%bp,%si) ++ .byte 0xf2 ++ .byte 0x67 ++ .byte 0x66 ++ .byte 0x0f ++ .byte 0x11 ++ .byte 0x22 ++ ++# lock data16 movsd %xmm4,(%bp,%si) ++ .byte 0xf2 ++ .byte 0x67 ++ .byte 0xf0 ++ .byte 0x66 ++ .byte 0x0f ++ .byte 0x11 ++ .byte 0x22 ++ ++# data16 movss %xmm4,(%edx) ++ .byte 0xf3 ++ .byte 0x66 ++ .byte 0x0f ++ .byte 0x11 ++ .byte 0x22 ++ ++# lock data16 movss %xmm4,(%bp,%si) ++ .byte 0xf3 ++ .byte 0x67 ++ .byte 0xf0 ++ .byte 0x66 ++ .byte 0x0f ++ .byte 0x11 ++ .byte 0x22 ++ ++# repz data16 movsd %xmm4,(%bp,%si) ++ .byte 0xf3 ++ .byte 0x67 ++ .byte 0xf2 ++ .byte 0x66 ++ .byte 0x0f ++ .byte 0x11 ++ .byte 0x22 ++ ++# data16 movss %xmm4,%ds:(%edx) ++ .byte 0xf3 ++ .byte 0x66 ++ .byte 0x3e ++ .byte 0x0f ++ .byte 0x11 ++ .byte 0x22 ++ ++# data16 movsd %xmm4,%ss:(%edx) ++ .byte 0xf2 ++ .byte 0x66 ++ .byte 0x36 ++ .byte 0x0f ++ .byte 0x11 ++ .byte 0x22 ++ ++# repz lock data16 movsd %xmm4,%ss:(%edx) ++ .byte 0xf3 ++ .byte 0xf0 ++ .byte 0xf2 ++ .byte 0x66 ++ .byte 0x36 ++ .byte 0x0f ++ .byte 0x11 ++ .byte 0x22 ++ ++# data16 ds movsd %xmm4,%ss:(%edx) ++ .byte 0xf2 ++ .byte 0x66 ++ .byte 0x3e ++ .byte 0x36 ++ .byte 0x0f ++ .byte 0x11 ++ .byte 0x22 ++ ++# data16 ds movsd %xmm4,%ss:(%bp,%si) ++ .byte 0xf2 ++ .byte 0x67 ++ .byte 0x66 ++ .byte 0x3e ++ .byte 0x36 ++ .byte 0x0f ++ .byte 0x11 ++ .byte 0x22 ++ ++# lock data16 ds movsd %xmm4,%ss:(%bp,%si) ++ .byte 0xf2 ++ .byte 0x67 ++ .byte 0xf0 ++ .byte 0x66 ++ .byte 0x3e ++ .byte 0x36 ++ .byte 0x0f ++ .byte 0x11 ++ .byte 0x22 ++ ++# data16 ds movss %xmm4,%ss:(%edx) ++ .byte 0xf3 ++ .byte 0x66 ++ .byte 0x3e ++ .byte 0x36 ++ .byte 0x0f ++ .byte 0x11 ++ .byte 0x22 ++ ++# lock data16 ds movss %xmm4,%ss:(%edx) ++ .byte 0xf3 ++ .byte 0xf0 ++ .byte 0x66 ++ .byte 0x3e ++ .byte 0x36 ++ .byte 0x0f ++ .byte 0x11 ++ .byte 0x22 ++ ++# repz data16 ds movsd %xmm4,%ss:(%bp,%si) ++ .byte 0xf3 ++ .byte 0x67 ++ .byte 0xf2 ++ .byte 0x66 ++ .byte 0x3e ++ .byte 0x36 ++ .byte 0x0f ++ .byte 0x11 ++ .byte 0x22 ++ ++# repnz; xchg %ax,%ax ++ .byte 0xf2 ++ .byte 0x66 ++ .byte 0x90 ++ ++# repnz; addr16 xchg %ax,%ax ++ .byte 0xf2 ++ .byte 0x67 ++ .byte 0x66 ++ .byte 0x90 ++ ++# repnz; addr16 lock xchg %ax,%ax ++ .byte 0xf2 ++ .byte 0x67 ++ .byte 0xf0 ++ .byte 0x66 ++ .byte 0x90 ++ ++# data16 pause ++ .byte 0xf3 ++ .byte 0x66 ++ .byte 0x90 ++ ++# addr16 lock data16 pause ++ .byte 0xf3 ++ .byte 0x67 ++ .byte 0xf0 ++ .byte 0x66 ++ .byte 0x90 ++ ++# repz; addr16; repnz; xchg %ax,%ax ++ .byte 0xf3 ++ .byte 0x67 ++ .byte 0xf2 ++ .byte 0x66 ++ .byte 0x90 ++ ++# repnz; ds nop ++ .byte 0xf2 ++ .byte 0x3e ++ .byte 0x90 ++ ++# repnz; lock addr16 ds nop ++ .byte 0xf2 ++ .byte 0xf0 ++ .byte 0x67 ++ .byte 0x3e ++ .byte 0x90 ++ ++# ds pause ++ .byte 0xf3 ++ .byte 0x3e ++ .byte 0x90 ++ ++# data16 ds pause ++ .byte 0xf3 ++ .byte 0x66 ++ .byte 0x3e ++ .byte 0x90 ++ ++# lock ds pause ++ .byte 0xf3 ++ .byte 0xf0 ++ .byte 0x3e ++ .byte 0x90 ++ ++# lock addr16 ds pause ++ .byte 0xf3 ++ .byte 0xf0 ++ .byte 0x67 ++ .byte 0x3e ++ .byte 0x90 ++ ++# repz; repnz; addr16 ds nop ++ .byte 0xf3 ++ .byte 0xf2 ++ .byte 0x67 ++ .byte 0x3e ++ .byte 0x90 ++ ++# lock ss xchg %ax,%ax ++ .byte 0x66 ++ .byte 0xf0 ++ .byte 0x36 ++ .byte 0x90 ++ ++# repnz; ss nop ++ .byte 0xf2 ++ .byte 0x36 ++ .byte 0x90 ++ ++# repnz; ss xchg %ax,%ax ++ .byte 0xf2 ++ .byte 0x66 ++ .byte 0x36 ++ .byte 0x90 ++ ++# repnz; lock ss nop ++ .byte 0xf2 ++ .byte 0xf0 ++ .byte 0x36 ++ .byte 0x90 ++ ++# repnz; lock addr16 ss nop ++ .byte 0xf2 ++ .byte 0xf0 ++ .byte 0x67 ++ .byte 0x36 ++ .byte 0x90 ++ ++# ss pause ++ .byte 0xf3 ++ .byte 0x36 ++ .byte 0x90 ++ ++# addr16 ss pause ++ .byte 0xf3 ++ .byte 0x67 ++ .byte 0x36 ++ .byte 0x90 ++ ++# lock addr16 ss pause ++ .byte 0xf3 ++ .byte 0xf0 ++ .byte 0x67 ++ .byte 0x36 ++ .byte 0x90 ++ ++# repz; repnz; ss nop ++ .byte 0xf3 ++ .byte 0xf2 ++ .byte 0x36 ++ .byte 0x90 ++ ++# repz; repnz; addr16 ss nop ++ .byte 0xf3 ++ .byte 0xf2 ++ .byte 0x67 ++ .byte 0x36 ++ .byte 0x90 ++ ++# repz; lock; repnz; ss xchg %ax,%ax ++ .byte 0xf3 ++ .byte 0xf0 ++ .byte 0xf2 ++ .byte 0x66 ++ .byte 0x36 ++ .byte 0x90 ++ ++# ds ss xchg %ax,%ax ++ .byte 0x66 ++ .byte 0x3e ++ .byte 0x36 ++ .byte 0x90 ++ ++# addr16 ds ss xchg %ax,%ax ++ .byte 0x67 ++ .byte 0x66 ++ .byte 0x3e ++ .byte 0x36 ++ .byte 0x90 ++ ++# addr16 lock ds ss xchg %ax,%ax ++ .byte 0x67 ++ .byte 0xf0 ++ .byte 0x66 ++ .byte 0x3e ++ .byte 0x36 ++ .byte 0x90 ++ ++# data16 ds ss pause ++ .byte 0xf3 ++ .byte 0x66 ++ .byte 0x3e ++ .byte 0x36 ++ .byte 0x90 ++ ++# lock data16 ds ss pause ++ .byte 0xf3 ++ .byte 0xf0 ++ .byte 0x66 ++ .byte 0x3e ++ .byte 0x36 ++ .byte 0x90 ++ ++# repz; repnz; addr16 ds ss nop ++ .byte 0xf3 ++ .byte 0xf2 ++ .byte 0x67 ++ .byte 0x3e ++ .byte 0x36 ++ .byte 0x90 ++ ++# repz; addr16; repnz; ds ss xchg %ax,%ax ++ .byte 0xf3 ++ .byte 0x67 ++ .byte 0xf2 ++ .byte 0x66 ++ .byte 0x3e ++ .byte 0x36 ++ .byte 0x90 ++ +# Get a good alignment. + .p2align 4,0 diff --git a/gas/testsuite/gas/i386/rdrnd-intel.d b/gas/testsuite/gas/i386/rdrnd-intel.d @@ -1341889,143 +1349610,175 @@ index 0000000..0891fcd +2: + xend + xtest +diff --git a/gas/testsuite/gas/i386/se1.d b/gas/testsuite/gas/i386/se1.d +new file mode 100644 +index 0000000..ff2685c +--- /dev/null ++++ b/gas/testsuite/gas/i386/se1.d +@@ -0,0 +1,13 @@ ++#objdump: -dw ++#name: i386 SE1 insns ++#source: se1.s ++ ++.*: +file format .* ++ ++ ++Disassembly of section .text: ++ ++0+ <_start>: ++[ ]*[a-f0-9]+: 0f 01 cf encls ++[ ]*[a-f0-9]+: 0f 01 d7 enclu ++#pass +diff --git a/gas/testsuite/gas/i386/se1.s b/gas/testsuite/gas/i386/se1.s +new file mode 100644 +index 0000000..1b57ac8 +--- /dev/null ++++ b/gas/testsuite/gas/i386/se1.s +@@ -0,0 +1,7 @@ ++# Check SE1 new instructions. ++ ++ .text ++_start: ++ ++ encls ++ enclu diff --git a/gas/testsuite/gas/i386/secrel.d b/gas/testsuite/gas/i386/secrel.d new file mode 100644 -index 0000000..7ae3337 +index 0000000..ac23301 --- /dev/null +++ b/gas/testsuite/gas/i386/secrel.d @@ -0,0 +1,44 @@ -+#objdump: -rs -+#name: i386 secrel reloc -+ -+.*: +file format pe-i386 -+ -+RELOCATION RECORDS FOR \[\.data\]: -+OFFSET[ ]+TYPE[ ]+VALUE -+0+24 secrel32 \.text -+0+29 secrel32 \.text -+0+2e secrel32 \.text -+0+33 secrel32 \.text -+0+44 secrel32 \.data -+0+49 secrel32 \.data -+0+4e secrel32 \.data -+0+53 secrel32 \.data -+0+64 secrel32 \.rdata -+0+69 secrel32 \.rdata -+0+6e secrel32 \.rdata -+0+73 secrel32 \.rdata -+0+84 secrel32 ext24 -+0+89 secrel32 ext2d -+0+8e secrel32 ext36 -+0+93 secrel32 ext3f -+0+a2 secrel32 bar -+ -+Contents of section \.text: -+ 0000 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c >>>><<<<>>>>><<< -+ 0010 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c >>>>>><<>>>>>>>< -+Contents of section \.data: -+ 0000 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c >>>><<<<>>>>><<< -+ 0010 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c >>>>>><<>>>>>>>< -+ 0020 3e3e3e3e 04000000 110d0000 00111600 >>>>............ -+ 0030 0000111f 00000011 3c3c3c3c 3c3c3c3c ........<<<<<<<< -+ 0040 3e3e3e3e 04000000 110d0000 00111600 >>>>............ -+ 0050 0000111f 00000011 3c3c3c3c 3c3c3c3c ........<<<<<<<< -+ 0060 3e3e3e3e 04000000 110d0000 00111600 >>>>............ -+ 0070 0000111f 00000011 3c3c3c3c 3c3c3c3c ........<<<<<<<< -+ 0080 3e3e3e3e 00000000 11000000 00110000 >>>>............ -+ 0090 00001100 00000011 3c3c3c3c 3c3c3c3c ........<<<<<<<< -+ 00a0 8d902c00 00000000 ..,..... -+Contents of section \.rdata: -+ 0000 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c >>>><<<<>>>>><<< -+ 0010 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c >>>>>><<>>>>>>>< -+ 0020 3e3e3e3e 00000000 00000000 00000000 >>>>............ ++#objdump: -rs ++#name: i386 secrel reloc ++ ++.*: +file format pe-i386 ++ ++RELOCATION RECORDS FOR \[\.data\]: ++OFFSET[ ]+TYPE[ ]+VALUE ++0+24 secrel32 \.text ++0+29 secrel32 \.text ++0+2e secrel32 \.text ++0+33 secrel32 \.text ++0+44 secrel32 \.data ++0+49 secrel32 \.data ++0+4e secrel32 \.data ++0+53 secrel32 \.data ++0+64 secrel32 \.rdata ++0+69 secrel32 \.rdata ++0+6e secrel32 \.rdata ++0+73 secrel32 \.rdata ++0+84 secrel32 ext24 ++0+89 secrel32 ext2d ++0+8e secrel32 ext36 ++0+93 secrel32 ext3f ++0+a2 secrel32 bar ++ ++Contents of section \.text: ++ 0000 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c >>>><<<<>>>>><<< ++ 0010 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c >>>>>><<>>>>>>>< ++Contents of section \.data: ++ 0000 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c >>>><<<<>>>>><<< ++ 0010 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c >>>>>><<>>>>>>>< ++ 0020 3e3e3e3e 04000000 110d0000 00111600 >>>>............ ++ 0030 0000111f 00000011 3c3c3c3c 3c3c3c3c ........<<<<<<<< ++ 0040 3e3e3e3e 04000000 110d0000 00111600 >>>>............ ++ 0050 0000111f 00000011 3c3c3c3c 3c3c3c3c ........<<<<<<<< ++ 0060 3e3e3e3e 04000000 110d0000 00111600 >>>>............ ++ 0070 0000111f 00000011 3c3c3c3c 3c3c3c3c ........<<<<<<<< ++ 0080 3e3e3e3e 00000000 11000000 00110000 >>>>............ ++ 0090 00001100 00000011 3c3c3c3c 3c3c3c3c ........<<<<<<<< ++ 00a0 8d902c00 00000000 ..,..... ++Contents of section \.rdata: ++ 0000 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c >>>><<<<>>>>><<< ++ 0010 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c >>>>>><<>>>>>>>< ++ 0020 3e3e3e3e 00000000 00000000 00000000 >>>>............ diff --git a/gas/testsuite/gas/i386/secrel.s b/gas/testsuite/gas/i386/secrel.s new file mode 100644 -index 0000000..f89fe31 +index 0000000..2fc5a25 --- /dev/null +++ b/gas/testsuite/gas/i386/secrel.s @@ -0,0 +1,81 @@ -+.text -+ -+ .ascii ">>>>" -+pre04: .ascii "<<<<" -+ .ascii ">>>>>" -+pre0d: .ascii "<<<" -+ .ascii ">>>>>>" -+pre16: .ascii "<<" -+ .ascii ">>>>>>>" -+pre1f: .ascii "<" -+ -+.data -+ -+ .ascii ">>>>" -+sam04: .ascii "<<<<" -+ .ascii ">>>>>" -+sam0d: .ascii "<<<" -+ .ascii ">>>>>>" -+sam16: .ascii "<<" -+ .ascii ">>>>>>>" -+sam1f: .ascii "<" -+ -+ .ascii ">>>>" -+ .secrel32 pre04 -+ .byte 0x11 -+ .secrel32 pre0d -+ .byte 0x11 -+ .secrel32 pre16 -+ .byte 0x11 -+ .secrel32 pre1f -+ .byte 0x11 -+ .ascii "<<<<<<<<" -+ -+ .ascii ">>>>" -+ .secrel32 sam04 -+ .byte 0x11 -+ .secrel32 sam0d -+ .byte 0x11 -+ .secrel32 sam16 -+ .byte 0x11 -+ .secrel32 sam1f -+ .byte 0x11 -+ .ascii "<<<<<<<<" -+ -+ .ascii ">>>>" -+ .secrel32 nex04 -+ .byte 0x11 -+ .secrel32 nex0d -+ .byte 0x11 -+ .secrel32 nex16 -+ .byte 0x11 -+ .secrel32 nex1f -+ .byte 0x11 -+ .ascii "<<<<<<<<" -+ -+ .ascii ">>>>" -+ .secrel32 ext24 -+ .byte 0x11 -+ .secrel32 ext2d -+ .byte 0x11 -+ .secrel32 ext36 -+ .byte 0x11 -+ .secrel32 ext3f -+ .byte 0x11 -+ .ascii "<<<<<<<<" -+ -+ leal bar@SECREL32+44(%eax), %edx -+ -+.section .rdata -+ -+ .ascii ">>>>" -+nex04: .ascii "<<<<" -+ .ascii ">>>>>" -+nex0d: .ascii "<<<" -+ .ascii ">>>>>>" -+nex16: .ascii "<<" -+ .ascii ">>>>>>>" -+nex1f: .ascii "<" -+ .ascii ">>>>" -+ -+ .p2align 4,0 ++.text ++ ++ .ascii ">>>>" ++pre04: .ascii "<<<<" ++ .ascii ">>>>>" ++pre0d: .ascii "<<<" ++ .ascii ">>>>>>" ++pre16: .ascii "<<" ++ .ascii ">>>>>>>" ++pre1f: .ascii "<" ++ ++.data ++ ++ .ascii ">>>>" ++sam04: .ascii "<<<<" ++ .ascii ">>>>>" ++sam0d: .ascii "<<<" ++ .ascii ">>>>>>" ++sam16: .ascii "<<" ++ .ascii ">>>>>>>" ++sam1f: .ascii "<" ++ ++ .ascii ">>>>" ++ .secrel32 pre04 ++ .byte 0x11 ++ .secrel32 pre0d ++ .byte 0x11 ++ .secrel32 pre16 ++ .byte 0x11 ++ .secrel32 pre1f ++ .byte 0x11 ++ .ascii "<<<<<<<<" ++ ++ .ascii ">>>>" ++ .secrel32 sam04 ++ .byte 0x11 ++ .secrel32 sam0d ++ .byte 0x11 ++ .secrel32 sam16 ++ .byte 0x11 ++ .secrel32 sam1f ++ .byte 0x11 ++ .ascii "<<<<<<<<" ++ ++ .ascii ">>>>" ++ .secrel32 nex04 ++ .byte 0x11 ++ .secrel32 nex0d ++ .byte 0x11 ++ .secrel32 nex16 ++ .byte 0x11 ++ .secrel32 nex1f ++ .byte 0x11 ++ .ascii "<<<<<<<<" ++ ++ .ascii ">>>>" ++ .secrel32 ext24 ++ .byte 0x11 ++ .secrel32 ext2d ++ .byte 0x11 ++ .secrel32 ext36 ++ .byte 0x11 ++ .secrel32 ext3f ++ .byte 0x11 ++ .ascii "<<<<<<<<" ++ ++ leal bar@SECREL32+44(%eax), %edx ++ ++.section .rdata ++ ++ .ascii ">>>>" ++nex04: .ascii "<<<<" ++ .ascii ">>>>>" ++nex0d: .ascii "<<<" ++ .ascii ">>>>>>" ++nex16: .ascii "<<" ++ .ascii ">>>>>>>" ++nex1f: .ascii "<" ++ .ascii ">>>>" ++ ++ .p2align 4,0 diff --git a/gas/testsuite/gas/i386/segment.l b/gas/testsuite/gas/i386/segment.l new file mode 100644 index 0000000..59c081e @@ -1343515,7 +1351268,7 @@ index 0000000..7466675 + .space foo << 4 diff --git a/gas/testsuite/gas/i386/sse-check-error.l b/gas/testsuite/gas/i386/sse-check-error.l new file mode 100644 -index 0000000..bd1c4f6 +index 0000000..5df6d67 --- /dev/null +++ b/gas/testsuite/gas/i386/sse-check-error.l @@ -0,0 +1,40 @@ @@ -1343537,27 +1351290,27 @@ index 0000000..bd1c4f6 +[ ]*5[ ]+ +[ ]*6[ ]+\# SSE instruction +[ ]*7[ ]+\?\?\?\? 0F58CA addps %xmm2,%xmm1 -+\*\*\*\* Error:SSE instruction `addps' is used ++.* Error: SSE instruction `addps' is used +[ ]*8[ ]+ +[ ]*9[ ]+\# SSE2 instruction +[ ]*10[ ]+\?\?\?\? 660F58CA addpd %xmm2,%xmm1 -+\*\*\*\* Error:SSE instruction `addpd' is used ++.* Error: SSE instruction `addpd' is used +[ ]*11[ ]+ +[ ]*12[ ]+\# SSE3 instruction +[ ]*13[ ]+\?\?\?\? 660FD0CA addsubpd %xmm2,%xmm1 -+\*\*\*\* Error:SSE instruction `addsubpd' is used ++.* Error: SSE instruction `addsubpd' is used +[ ]*14[ ]+ +[ ]*15[ ]+\# SSSE3 instruction +[ ]*16[ ]+\?\?\?\? 660F3801 phaddw %xmm2,%xmm1 -+\*\*\*\* Error:SSE instruction `phaddw' is used ++.* Error: SSE instruction `phaddw' is used +[ ]*16[ ]+CA +[ ]*17[ ]+ +[ ]*18[ ]+\# SSE4 instructions +[ ]*19[ ]+\?\?\?\? 660F3815 blendvpd %xmm0,%xmm1,%xmm0 -+\*\*\*\* Error:SSE instruction `blendvpd' is used ++.* Error: SSE instruction `blendvpd' is used +[ ]*19[ ]+C1 +[ ]*20[ ]+\?\?\?\? 660F3837 pcmpgtq %xmm1,%xmm0 -+\*\*\*\* Error:SSE instruction `pcmpgtq' is used ++.* Error: SSE instruction `pcmpgtq' is used +[ ]*20[ ]+C1 diff --git a/gas/testsuite/gas/i386/sse-check-error.s b/gas/testsuite/gas/i386/sse-check-error.s new file mode 100644 @@ -1349752,14 +1357505,22 @@ index 0000000..bd63fd4 + ret diff --git a/gas/testsuite/gas/i386/vgather-check-error.l b/gas/testsuite/gas/i386/vgather-check-error.l new file mode 100644 -index 0000000..41273dc +index 0000000..a86ccd5 --- /dev/null +++ b/gas/testsuite/gas/i386/vgather-check-error.l -@@ -0,0 +1,4 @@ +@@ -0,0 +1,12 @@ +.*: Assembler messages: +.*:6: Error: .* +.*:7: Error: .* +.*:8: Error: .* ++.*:12: Error: .* ++.*:14: Error: .* ++.*:16: Error: .* ++.*:18: Error: .* ++.*:20: Error: .* ++.*:22: Error: .* ++.*:24: Error: .* ++.*:26: Error: .* diff --git a/gas/testsuite/gas/i386/vgather-check-error.s b/gas/testsuite/gas/i386/vgather-check-error.s new file mode 100644 index 0000000..9db69c6 @@ -1349769,10 +1357530,10 @@ index 0000000..9db69c6 +.include "vgather-check.s" diff --git a/gas/testsuite/gas/i386/vgather-check-none.d b/gas/testsuite/gas/i386/vgather-check-none.d new file mode 100644 -index 0000000..b51cc94 +index 0000000..8abdfcb --- /dev/null +++ b/gas/testsuite/gas/i386/vgather-check-none.d -@@ -0,0 +1,14 @@ +@@ -0,0 +1,32 @@ +#as: -moperand-check=error -I${srcdir}/$subdir +#objdump: -dw +#name: i386 vgather check (.operand_check none) @@ -1349786,6 +1357547,24 @@ index 0000000..b51cc94 +[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 14 48[ ]+vgatherdps %xmm2,\(%eax,%xmm1,2\),%xmm2 +[ ]*[a-f0-9]+:[ ]+c4 e2 71 92 04 88[ ]+vgatherdps %xmm1,\(%eax,%xmm1,4\),%xmm0 +[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 0c c8[ ]+vgatherdps %xmm2,\(%eax,%xmm1,8\),%xmm1 ++ ++00000018 : ++[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 92 b4 fd 7b 00 00 00[ ]+vgatherdpd 0x7b\(%ebp,%ymm7,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 92 b4 f5 7b 00 00 00[ ]+vgatherdpd 0x7b\(%ebp,%ymm6,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 92 b4 fd 7b 00 00 00[ ]+vgatherdps 0x7b\(%ebp,%zmm7,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 92 b4 f5 7b 00 00 00[ ]+vgatherdps 0x7b\(%ebp,%zmm6,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 93 b4 fd 7b 00 00 00[ ]+vgatherqpd 0x7b\(%ebp,%zmm7,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 93 b4 f5 7b 00 00 00[ ]+vgatherqpd 0x7b\(%ebp,%zmm6,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 93 b4 fd 7b 00 00 00[ ]+vgatherqps 0x7b\(%ebp,%zmm7,8\),%ymm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 93 b4 f5 7b 00 00 00[ ]+vgatherqps 0x7b\(%ebp,%zmm6,8\),%ymm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 90 b4 fd 7b 00 00 00[ ]+vpgatherdd 0x7b\(%ebp,%zmm7,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 90 b4 f5 7b 00 00 00[ ]+vpgatherdd 0x7b\(%ebp,%zmm6,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 90 b4 fd 7b 00 00 00[ ]+vpgatherdq 0x7b\(%ebp,%ymm7,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 90 b4 f5 7b 00 00 00[ ]+vpgatherdq 0x7b\(%ebp,%ymm6,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 91 b4 fd 7b 00 00 00[ ]+vpgatherqd 0x7b\(%ebp,%zmm7,8\),%ymm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 91 b4 f5 7b 00 00 00[ ]+vpgatherqd 0x7b\(%ebp,%zmm6,8\),%ymm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 91 b4 fd 7b 00 00 00[ ]+vpgatherqq 0x7b\(%ebp,%zmm7,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 91 b4 f5 7b 00 00 00[ ]+vpgatherqq 0x7b\(%ebp,%zmm6,8\),%zmm6\{%k1\} +#pass diff --git a/gas/testsuite/gas/i386/vgather-check-none.s b/gas/testsuite/gas/i386/vgather-check-none.s new file mode 100644 @@ -1349797,10 +1357576,10 @@ index 0000000..cf31039 +.include "vgather-check.s" diff --git a/gas/testsuite/gas/i386/vgather-check-warn.d b/gas/testsuite/gas/i386/vgather-check-warn.d new file mode 100644 -index 0000000..22be247 +index 0000000..985f713 --- /dev/null +++ b/gas/testsuite/gas/i386/vgather-check-warn.d -@@ -0,0 +1,15 @@ +@@ -0,0 +1,33 @@ +#source: vgather-check.s +#stderr: vgather-check-warn.e +#objdump: -dw @@ -1349815,23 +1357594,49 @@ index 0000000..22be247 +[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 14 48[ ]+vgatherdps %xmm2,\(%eax,%xmm1,2\),%xmm2 +[ ]*[a-f0-9]+:[ ]+c4 e2 71 92 04 88[ ]+vgatherdps %xmm1,\(%eax,%xmm1,4\),%xmm0 +[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 0c c8[ ]+vgatherdps %xmm2,\(%eax,%xmm1,8\),%xmm1 ++ ++00000018 : ++[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 92 b4 fd 7b 00 00 00[ ]+vgatherdpd 0x7b\(%ebp,%ymm7,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 92 b4 f5 7b 00 00 00[ ]+vgatherdpd 0x7b\(%ebp,%ymm6,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 92 b4 fd 7b 00 00 00[ ]+vgatherdps 0x7b\(%ebp,%zmm7,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 92 b4 f5 7b 00 00 00[ ]+vgatherdps 0x7b\(%ebp,%zmm6,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 93 b4 fd 7b 00 00 00[ ]+vgatherqpd 0x7b\(%ebp,%zmm7,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 93 b4 f5 7b 00 00 00[ ]+vgatherqpd 0x7b\(%ebp,%zmm6,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 93 b4 fd 7b 00 00 00[ ]+vgatherqps 0x7b\(%ebp,%zmm7,8\),%ymm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 93 b4 f5 7b 00 00 00[ ]+vgatherqps 0x7b\(%ebp,%zmm6,8\),%ymm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 90 b4 fd 7b 00 00 00[ ]+vpgatherdd 0x7b\(%ebp,%zmm7,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 90 b4 f5 7b 00 00 00[ ]+vpgatherdd 0x7b\(%ebp,%zmm6,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 90 b4 fd 7b 00 00 00[ ]+vpgatherdq 0x7b\(%ebp,%ymm7,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 90 b4 f5 7b 00 00 00[ ]+vpgatherdq 0x7b\(%ebp,%ymm6,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 91 b4 fd 7b 00 00 00[ ]+vpgatherqd 0x7b\(%ebp,%zmm7,8\),%ymm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 91 b4 f5 7b 00 00 00[ ]+vpgatherqd 0x7b\(%ebp,%zmm6,8\),%ymm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 91 b4 fd 7b 00 00 00[ ]+vpgatherqq 0x7b\(%ebp,%zmm7,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 91 b4 f5 7b 00 00 00[ ]+vpgatherqq 0x7b\(%ebp,%zmm6,8\),%zmm6\{%k1\} +#pass diff --git a/gas/testsuite/gas/i386/vgather-check-warn.e b/gas/testsuite/gas/i386/vgather-check-warn.e new file mode 100644 -index 0000000..095840b +index 0000000..efd2e0b --- /dev/null +++ b/gas/testsuite/gas/i386/vgather-check-warn.e -@@ -0,0 +1,4 @@ +@@ -0,0 +1,12 @@ +.*: Assembler messages: +.*:6: Warning: .* +.*:7: Warning: .* +.*:8: Warning: .* ++.*:12: Warning: .* ++.*:14: Warning: .* ++.*:16: Warning: .* ++.*:18: Warning: .* ++.*:20: Warning: .* ++.*:22: Warning: .* ++.*:24: Warning: .* ++.*:26: Warning: .* diff --git a/gas/testsuite/gas/i386/vgather-check.d b/gas/testsuite/gas/i386/vgather-check.d new file mode 100644 -index 0000000..25042f4 +index 0000000..c3505f9 --- /dev/null +++ b/gas/testsuite/gas/i386/vgather-check.d -@@ -0,0 +1,14 @@ +@@ -0,0 +1,32 @@ +#as: -moperand-check=none +#objdump: -dw +#name: i386 vgather check (-moperand-check=none) @@ -1349845,13 +1357650,31 @@ index 0000000..25042f4 +[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 14 48[ ]+vgatherdps %xmm2,\(%eax,%xmm1,2\),%xmm2 +[ ]*[a-f0-9]+:[ ]+c4 e2 71 92 04 88[ ]+vgatherdps %xmm1,\(%eax,%xmm1,4\),%xmm0 +[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 0c c8[ ]+vgatherdps %xmm2,\(%eax,%xmm1,8\),%xmm1 ++ ++00000018 : ++[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 92 b4 fd 7b 00 00 00[ ]+vgatherdpd 0x7b\(%ebp,%ymm7,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 92 b4 f5 7b 00 00 00[ ]+vgatherdpd 0x7b\(%ebp,%ymm6,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 92 b4 fd 7b 00 00 00[ ]+vgatherdps 0x7b\(%ebp,%zmm7,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 92 b4 f5 7b 00 00 00[ ]+vgatherdps 0x7b\(%ebp,%zmm6,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 93 b4 fd 7b 00 00 00[ ]+vgatherqpd 0x7b\(%ebp,%zmm7,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 93 b4 f5 7b 00 00 00[ ]+vgatherqpd 0x7b\(%ebp,%zmm6,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 93 b4 fd 7b 00 00 00[ ]+vgatherqps 0x7b\(%ebp,%zmm7,8\),%ymm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 93 b4 f5 7b 00 00 00[ ]+vgatherqps 0x7b\(%ebp,%zmm6,8\),%ymm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 90 b4 fd 7b 00 00 00[ ]+vpgatherdd 0x7b\(%ebp,%zmm7,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 90 b4 f5 7b 00 00 00[ ]+vpgatherdd 0x7b\(%ebp,%zmm6,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 90 b4 fd 7b 00 00 00[ ]+vpgatherdq 0x7b\(%ebp,%ymm7,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 90 b4 f5 7b 00 00 00[ ]+vpgatherdq 0x7b\(%ebp,%ymm6,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 91 b4 fd 7b 00 00 00[ ]+vpgatherqd 0x7b\(%ebp,%zmm7,8\),%ymm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 7d 49 91 b4 f5 7b 00 00 00[ ]+vpgatherqd 0x7b\(%ebp,%zmm6,8\),%ymm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 91 b4 fd 7b 00 00 00[ ]+vpgatherqq 0x7b\(%ebp,%zmm7,8\),%zmm6\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 f2 fd 49 91 b4 f5 7b 00 00 00[ ]+vpgatherqq 0x7b\(%ebp,%zmm6,8\),%zmm6\{%k1\} +#pass diff --git a/gas/testsuite/gas/i386/vgather-check.s b/gas/testsuite/gas/i386/vgather-check.s new file mode 100644 -index 0000000..c784029 +index 0000000..b2735e7 --- /dev/null +++ b/gas/testsuite/gas/i386/vgather-check.s -@@ -0,0 +1,8 @@ +@@ -0,0 +1,26 @@ +# Check vgather instructions + + .text @@ -1349860,6 +1357683,24 @@ index 0000000..c784029 + vgatherdps %xmm2,(%eax,%xmm1,2),%xmm2 + vgatherdps %xmm1,(%eax,%xmm1,4),%xmm0 + vgatherdps %xmm2,(%eax,%xmm1,8),%xmm1 ++ ++avx512vgather: ++ vgatherdpd 123(%ebp,%ymm7,8), %zmm6{%k1} ++ vgatherdpd 123(%ebp,%ymm6,8), %zmm6{%k1} ++ vgatherdps 123(%ebp,%zmm7,8), %zmm6{%k1} ++ vgatherdps 123(%ebp,%zmm6,8), %zmm6{%k1} ++ vgatherqpd 123(%ebp,%zmm7,8), %zmm6{%k1} ++ vgatherqpd 123(%ebp,%zmm6,8), %zmm6{%k1} ++ vgatherqps 123(%ebp,%zmm7,8), %ymm6{%k1} ++ vgatherqps 123(%ebp,%zmm6,8), %ymm6{%k1} ++ vpgatherdd 123(%ebp,%zmm7,8), %zmm6{%k1} ++ vpgatherdd 123(%ebp,%zmm6,8), %zmm6{%k1} ++ vpgatherdq 123(%ebp,%ymm7,8), %zmm6{%k1} ++ vpgatherdq 123(%ebp,%ymm6,8), %zmm6{%k1} ++ vpgatherqd 123(%ebp,%zmm7,8), %ymm6{%k1} ++ vpgatherqd 123(%ebp,%zmm6,8), %ymm6{%k1} ++ vpgatherqq 123(%ebp,%zmm7,8), %zmm6{%k1} ++ vpgatherqq 123(%ebp,%zmm6,8), %zmm6{%k1} diff --git a/gas/testsuite/gas/i386/vmfunc.d b/gas/testsuite/gas/i386/vmfunc.d new file mode 100644 index 0000000..dd6998d @@ -1367279,10 +1375120,10 @@ index 0000000..86d0b60 + vpmovzxbq ymm4,[rcx] diff --git a/gas/testsuite/gas/i386/x86-64-avx512cd-intel.d b/gas/testsuite/gas/i386/x86-64-avx512cd-intel.d new file mode 100644 -index 0000000..a8f7798 +index 0000000..a79e10e --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx512cd-intel.d -@@ -0,0 +1,180 @@ +@@ -0,0 +1,128 @@ +#as: +#objdump: -dwMintel +#name: x86_64 AVX512CD insns (Intel disassembly) @@ -1367350,32 +1375191,6 @@ index 0000000..a8f7798 +[ ]*[a-f0-9]+: 62 62 fd 58 44 b2 00 04 00 00 vplzcntq zmm30,QWORD PTR \[rdx\+0x400\]\{1to8\} +[ ]*[a-f0-9]+: 62 62 fd 58 44 72 80 vplzcntq zmm30,QWORD PTR \[rdx-0x400\]\{1to8\} +[ ]*[a-f0-9]+: 62 62 fd 58 44 b2 f8 fb ff ff vplzcntq zmm30,QWORD PTR \[rdx-0x408\]\{1to8\} -+[ ]*[a-f0-9]+: 62 92 16 40 27 ec vptestnmd k5,zmm29,zmm28 -+[ ]*[a-f0-9]+: 62 92 16 47 27 ec vptestnmd k5\{k7\},zmm29,zmm28 -+[ ]*[a-f0-9]+: 62 f2 16 40 27 29 vptestnmd k5,zmm29,ZMMWORD PTR \[rcx\] -+[ ]*[a-f0-9]+: 62 b2 16 40 27 ac f0 23 01 00 00 vptestnmd k5,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x123\] -+[ ]*[a-f0-9]+: 62 f2 16 50 27 29 vptestnmd k5,zmm29,DWORD PTR \[rcx\]\{1to16\} -+[ ]*[a-f0-9]+: 62 f2 16 40 27 6a 7f vptestnmd k5,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\] -+[ ]*[a-f0-9]+: 62 f2 16 40 27 aa 00 20 00 00 vptestnmd k5,zmm29,ZMMWORD PTR \[rdx\+0x2000\] -+[ ]*[a-f0-9]+: 62 f2 16 40 27 6a 80 vptestnmd k5,zmm29,ZMMWORD PTR \[rdx-0x2000\] -+[ ]*[a-f0-9]+: 62 f2 16 40 27 aa c0 df ff ff vptestnmd k5,zmm29,ZMMWORD PTR \[rdx-0x2040\] -+[ ]*[a-f0-9]+: 62 f2 16 50 27 6a 7f vptestnmd k5,zmm29,DWORD PTR \[rdx\+0x1fc\]\{1to16\} -+[ ]*[a-f0-9]+: 62 f2 16 50 27 aa 00 02 00 00 vptestnmd k5,zmm29,DWORD PTR \[rdx\+0x200\]\{1to16\} -+[ ]*[a-f0-9]+: 62 f2 16 50 27 6a 80 vptestnmd k5,zmm29,DWORD PTR \[rdx-0x200\]\{1to16\} -+[ ]*[a-f0-9]+: 62 f2 16 50 27 aa fc fd ff ff vptestnmd k5,zmm29,DWORD PTR \[rdx-0x204\]\{1to16\} -+[ ]*[a-f0-9]+: 62 92 96 40 27 ec vptestnmq k5,zmm29,zmm28 -+[ ]*[a-f0-9]+: 62 92 96 47 27 ec vptestnmq k5\{k7\},zmm29,zmm28 -+[ ]*[a-f0-9]+: 62 f2 96 40 27 29 vptestnmq k5,zmm29,ZMMWORD PTR \[rcx\] -+[ ]*[a-f0-9]+: 62 b2 96 40 27 ac f0 23 01 00 00 vptestnmq k5,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x123\] -+[ ]*[a-f0-9]+: 62 f2 96 50 27 29 vptestnmq k5,zmm29,QWORD PTR \[rcx\]\{1to8\} -+[ ]*[a-f0-9]+: 62 f2 96 40 27 6a 7f vptestnmq k5,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\] -+[ ]*[a-f0-9]+: 62 f2 96 40 27 aa 00 20 00 00 vptestnmq k5,zmm29,ZMMWORD PTR \[rdx\+0x2000\] -+[ ]*[a-f0-9]+: 62 f2 96 40 27 6a 80 vptestnmq k5,zmm29,ZMMWORD PTR \[rdx-0x2000\] -+[ ]*[a-f0-9]+: 62 f2 96 40 27 aa c0 df ff ff vptestnmq k5,zmm29,ZMMWORD PTR \[rdx-0x2040\] -+[ ]*[a-f0-9]+: 62 f2 96 50 27 6a 7f vptestnmq k5,zmm29,QWORD PTR \[rdx\+0x3f8\]\{1to8\} -+[ ]*[a-f0-9]+: 62 f2 96 50 27 aa 00 04 00 00 vptestnmq k5,zmm29,QWORD PTR \[rdx\+0x400\]\{1to8\} -+[ ]*[a-f0-9]+: 62 f2 96 50 27 6a 80 vptestnmq k5,zmm29,QWORD PTR \[rdx-0x400\]\{1to8\} -+[ ]*[a-f0-9]+: 62 f2 96 50 27 aa f8 fb ff ff vptestnmq k5,zmm29,QWORD PTR \[rdx-0x408\]\{1to8\} +[ ]*[a-f0-9]+: 62 62 7e 48 3a f6 vpbroadcastmw2d zmm30,k6 +[ ]*[a-f0-9]+: 62 62 fe 48 2a f6 vpbroadcastmb2q zmm30,k6 +[ ]*[a-f0-9]+: 62 02 7d 48 c4 f5 vpconflictd zmm30,zmm29 @@ -1367434,41 +1375249,15 @@ index 0000000..a8f7798 +[ ]*[a-f0-9]+: 62 62 fd 58 44 b2 00 04 00 00 vplzcntq zmm30,QWORD PTR \[rdx\+0x400\]\{1to8\} +[ ]*[a-f0-9]+: 62 62 fd 58 44 72 80 vplzcntq zmm30,QWORD PTR \[rdx-0x400\]\{1to8\} +[ ]*[a-f0-9]+: 62 62 fd 58 44 b2 f8 fb ff ff vplzcntq zmm30,QWORD PTR \[rdx-0x408\]\{1to8\} -+[ ]*[a-f0-9]+: 62 92 16 40 27 ec vptestnmd k5,zmm29,zmm28 -+[ ]*[a-f0-9]+: 62 92 16 47 27 ec vptestnmd k5\{k7\},zmm29,zmm28 -+[ ]*[a-f0-9]+: 62 f2 16 40 27 29 vptestnmd k5,zmm29,ZMMWORD PTR \[rcx\] -+[ ]*[a-f0-9]+: 62 b2 16 40 27 ac f0 34 12 00 00 vptestnmd k5,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x1234\] -+[ ]*[a-f0-9]+: 62 f2 16 50 27 29 vptestnmd k5,zmm29,DWORD PTR \[rcx\]\{1to16\} -+[ ]*[a-f0-9]+: 62 f2 16 40 27 6a 7f vptestnmd k5,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\] -+[ ]*[a-f0-9]+: 62 f2 16 40 27 aa 00 20 00 00 vptestnmd k5,zmm29,ZMMWORD PTR \[rdx\+0x2000\] -+[ ]*[a-f0-9]+: 62 f2 16 40 27 6a 80 vptestnmd k5,zmm29,ZMMWORD PTR \[rdx-0x2000\] -+[ ]*[a-f0-9]+: 62 f2 16 40 27 aa c0 df ff ff vptestnmd k5,zmm29,ZMMWORD PTR \[rdx-0x2040\] -+[ ]*[a-f0-9]+: 62 f2 16 50 27 6a 7f vptestnmd k5,zmm29,DWORD PTR \[rdx\+0x1fc\]\{1to16\} -+[ ]*[a-f0-9]+: 62 f2 16 50 27 aa 00 02 00 00 vptestnmd k5,zmm29,DWORD PTR \[rdx\+0x200\]\{1to16\} -+[ ]*[a-f0-9]+: 62 f2 16 50 27 6a 80 vptestnmd k5,zmm29,DWORD PTR \[rdx-0x200\]\{1to16\} -+[ ]*[a-f0-9]+: 62 f2 16 50 27 aa fc fd ff ff vptestnmd k5,zmm29,DWORD PTR \[rdx-0x204\]\{1to16\} -+[ ]*[a-f0-9]+: 62 92 96 40 27 ec vptestnmq k5,zmm29,zmm28 -+[ ]*[a-f0-9]+: 62 92 96 47 27 ec vptestnmq k5\{k7\},zmm29,zmm28 -+[ ]*[a-f0-9]+: 62 f2 96 40 27 29 vptestnmq k5,zmm29,ZMMWORD PTR \[rcx\] -+[ ]*[a-f0-9]+: 62 b2 96 40 27 ac f0 34 12 00 00 vptestnmq k5,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x1234\] -+[ ]*[a-f0-9]+: 62 f2 96 50 27 29 vptestnmq k5,zmm29,QWORD PTR \[rcx\]\{1to8\} -+[ ]*[a-f0-9]+: 62 f2 96 40 27 6a 7f vptestnmq k5,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\] -+[ ]*[a-f0-9]+: 62 f2 96 40 27 aa 00 20 00 00 vptestnmq k5,zmm29,ZMMWORD PTR \[rdx\+0x2000\] -+[ ]*[a-f0-9]+: 62 f2 96 40 27 6a 80 vptestnmq k5,zmm29,ZMMWORD PTR \[rdx-0x2000\] -+[ ]*[a-f0-9]+: 62 f2 96 40 27 aa c0 df ff ff vptestnmq k5,zmm29,ZMMWORD PTR \[rdx-0x2040\] -+[ ]*[a-f0-9]+: 62 f2 96 50 27 6a 7f vptestnmq k5,zmm29,QWORD PTR \[rdx\+0x3f8\]\{1to8\} -+[ ]*[a-f0-9]+: 62 f2 96 50 27 aa 00 04 00 00 vptestnmq k5,zmm29,QWORD PTR \[rdx\+0x400\]\{1to8\} -+[ ]*[a-f0-9]+: 62 f2 96 50 27 6a 80 vptestnmq k5,zmm29,QWORD PTR \[rdx-0x400\]\{1to8\} -+[ ]*[a-f0-9]+: 62 f2 96 50 27 aa f8 fb ff ff vptestnmq k5,zmm29,QWORD PTR \[rdx-0x408\]\{1to8\} +[ ]*[a-f0-9]+: 62 62 7e 48 3a f6 vpbroadcastmw2d zmm30,k6 +[ ]*[a-f0-9]+: 62 62 fe 48 2a f6 vpbroadcastmb2q zmm30,k6 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-avx512cd.d b/gas/testsuite/gas/i386/x86-64-avx512cd.d new file mode 100644 -index 0000000..ff9de77 +index 0000000..8a2e631 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx512cd.d -@@ -0,0 +1,179 @@ +@@ -0,0 +1,127 @@ +#as: +#objdump: -dw +#name: x86_64 AVX512CD insns @@ -1367535,32 +1375324,6 @@ index 0000000..ff9de77 +[ ]*[a-f0-9]+: 62 62 fd 58 44 b2 00 04 00 00 vplzcntq 0x400\(%rdx\)\{1to8\},%zmm30 +[ ]*[a-f0-9]+: 62 62 fd 58 44 72 80 vplzcntq -0x400\(%rdx\)\{1to8\},%zmm30 +[ ]*[a-f0-9]+: 62 62 fd 58 44 b2 f8 fb ff ff vplzcntq -0x408\(%rdx\)\{1to8\},%zmm30 -+[ ]*[a-f0-9]+: 62 92 16 40 27 ec vptestnmd %zmm28,%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 92 16 47 27 ec vptestnmd %zmm28,%zmm29,%k5\{%k7\} -+[ ]*[a-f0-9]+: 62 f2 16 40 27 29 vptestnmd \(%rcx\),%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 b2 16 40 27 ac f0 23 01 00 00 vptestnmd 0x123\(%rax,%r14,8\),%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 16 50 27 29 vptestnmd \(%rcx\)\{1to16\},%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 16 40 27 6a 7f vptestnmd 0x1fc0\(%rdx\),%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 16 40 27 aa 00 20 00 00 vptestnmd 0x2000\(%rdx\),%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 16 40 27 6a 80 vptestnmd -0x2000\(%rdx\),%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 16 40 27 aa c0 df ff ff vptestnmd -0x2040\(%rdx\),%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 16 50 27 6a 7f vptestnmd 0x1fc\(%rdx\)\{1to16\},%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 16 50 27 aa 00 02 00 00 vptestnmd 0x200\(%rdx\)\{1to16\},%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 16 50 27 6a 80 vptestnmd -0x200\(%rdx\)\{1to16\},%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 16 50 27 aa fc fd ff ff vptestnmd -0x204\(%rdx\)\{1to16\},%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 92 96 40 27 ec vptestnmq %zmm28,%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 92 96 47 27 ec vptestnmq %zmm28,%zmm29,%k5\{%k7\} -+[ ]*[a-f0-9]+: 62 f2 96 40 27 29 vptestnmq \(%rcx\),%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 b2 96 40 27 ac f0 23 01 00 00 vptestnmq 0x123\(%rax,%r14,8\),%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 96 50 27 29 vptestnmq \(%rcx\)\{1to8\},%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 96 40 27 6a 7f vptestnmq 0x1fc0\(%rdx\),%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 96 40 27 aa 00 20 00 00 vptestnmq 0x2000\(%rdx\),%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 96 40 27 6a 80 vptestnmq -0x2000\(%rdx\),%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 96 40 27 aa c0 df ff ff vptestnmq -0x2040\(%rdx\),%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 96 50 27 6a 7f vptestnmq 0x3f8\(%rdx\)\{1to8\},%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 96 50 27 aa 00 04 00 00 vptestnmq 0x400\(%rdx\)\{1to8\},%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 96 50 27 6a 80 vptestnmq -0x400\(%rdx\)\{1to8\},%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 96 50 27 aa f8 fb ff ff vptestnmq -0x408\(%rdx\)\{1to8\},%zmm29,%k5 +[ ]*[a-f0-9]+: 62 62 7e 48 3a f6 vpbroadcastmw2d %k6,%zmm30 +[ ]*[a-f0-9]+: 62 62 fe 48 2a f6 vpbroadcastmb2q %k6,%zmm30 +[ ]*[a-f0-9]+: 62 02 7d 48 c4 f5 vpconflictd %zmm29,%zmm30 @@ -1367619,41 +1375382,15 @@ index 0000000..ff9de77 +[ ]*[a-f0-9]+: 62 62 fd 58 44 b2 00 04 00 00 vplzcntq 0x400\(%rdx\)\{1to8\},%zmm30 +[ ]*[a-f0-9]+: 62 62 fd 58 44 72 80 vplzcntq -0x400\(%rdx\)\{1to8\},%zmm30 +[ ]*[a-f0-9]+: 62 62 fd 58 44 b2 f8 fb ff ff vplzcntq -0x408\(%rdx\)\{1to8\},%zmm30 -+[ ]*[a-f0-9]+: 62 92 16 40 27 ec vptestnmd %zmm28,%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 92 16 47 27 ec vptestnmd %zmm28,%zmm29,%k5\{%k7\} -+[ ]*[a-f0-9]+: 62 f2 16 40 27 29 vptestnmd \(%rcx\),%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 b2 16 40 27 ac f0 34 12 00 00 vptestnmd 0x1234\(%rax,%r14,8\),%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 16 50 27 29 vptestnmd \(%rcx\)\{1to16\},%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 16 40 27 6a 7f vptestnmd 0x1fc0\(%rdx\),%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 16 40 27 aa 00 20 00 00 vptestnmd 0x2000\(%rdx\),%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 16 40 27 6a 80 vptestnmd -0x2000\(%rdx\),%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 16 40 27 aa c0 df ff ff vptestnmd -0x2040\(%rdx\),%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 16 50 27 6a 7f vptestnmd 0x1fc\(%rdx\)\{1to16\},%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 16 50 27 aa 00 02 00 00 vptestnmd 0x200\(%rdx\)\{1to16\},%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 16 50 27 6a 80 vptestnmd -0x200\(%rdx\)\{1to16\},%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 16 50 27 aa fc fd ff ff vptestnmd -0x204\(%rdx\)\{1to16\},%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 92 96 40 27 ec vptestnmq %zmm28,%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 92 96 47 27 ec vptestnmq %zmm28,%zmm29,%k5\{%k7\} -+[ ]*[a-f0-9]+: 62 f2 96 40 27 29 vptestnmq \(%rcx\),%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 b2 96 40 27 ac f0 34 12 00 00 vptestnmq 0x1234\(%rax,%r14,8\),%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 96 50 27 29 vptestnmq \(%rcx\)\{1to8\},%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 96 40 27 6a 7f vptestnmq 0x1fc0\(%rdx\),%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 96 40 27 aa 00 20 00 00 vptestnmq 0x2000\(%rdx\),%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 96 40 27 6a 80 vptestnmq -0x2000\(%rdx\),%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 96 40 27 aa c0 df ff ff vptestnmq -0x2040\(%rdx\),%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 96 50 27 6a 7f vptestnmq 0x3f8\(%rdx\)\{1to8\},%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 96 50 27 aa 00 04 00 00 vptestnmq 0x400\(%rdx\)\{1to8\},%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 96 50 27 6a 80 vptestnmq -0x400\(%rdx\)\{1to8\},%zmm29,%k5 -+[ ]*[a-f0-9]+: 62 f2 96 50 27 aa f8 fb ff ff vptestnmq -0x408\(%rdx\)\{1to8\},%zmm29,%k5 +[ ]*[a-f0-9]+: 62 62 7e 48 3a f6 vpbroadcastmw2d %k6,%zmm30 +[ ]*[a-f0-9]+: 62 62 fe 48 2a f6 vpbroadcastmb2q %k6,%zmm30 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-avx512cd.s b/gas/testsuite/gas/i386/x86-64-avx512cd.s new file mode 100644 -index 0000000..1d6e015 +index 0000000..832874e --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx512cd.s -@@ -0,0 +1,191 @@ +@@ -0,0 +1,135 @@ +# Check 64bit AVX512CD instructions + + .allow_index_reg @@ -1367720,34 +1375457,6 @@ index 0000000..1d6e015 + vplzcntq -1024(%rdx){1to8}, %zmm30 # AVX512CD Disp8 + vplzcntq -1032(%rdx){1to8}, %zmm30 # AVX512CD + -+ vptestnmd %zmm28, %zmm29, %k5 # AVX512CD -+ vptestnmd %zmm28, %zmm29, %k5{%k7} # AVX512CD -+ vptestnmd (%rcx), %zmm29, %k5 # AVX512CD -+ vptestnmd 0x123(%rax,%r14,8), %zmm29, %k5 # AVX512CD -+ vptestnmd (%rcx){1to16}, %zmm29, %k5 # AVX512CD -+ vptestnmd 8128(%rdx), %zmm29, %k5 # AVX512CD Disp8 -+ vptestnmd 8192(%rdx), %zmm29, %k5 # AVX512CD -+ vptestnmd -8192(%rdx), %zmm29, %k5 # AVX512CD Disp8 -+ vptestnmd -8256(%rdx), %zmm29, %k5 # AVX512CD -+ vptestnmd 508(%rdx){1to16}, %zmm29, %k5 # AVX512CD Disp8 -+ vptestnmd 512(%rdx){1to16}, %zmm29, %k5 # AVX512CD -+ vptestnmd -512(%rdx){1to16}, %zmm29, %k5 # AVX512CD Disp8 -+ vptestnmd -516(%rdx){1to16}, %zmm29, %k5 # AVX512CD -+ -+ vptestnmq %zmm28, %zmm29, %k5 # AVX512CD -+ vptestnmq %zmm28, %zmm29, %k5{%k7} # AVX512CD -+ vptestnmq (%rcx), %zmm29, %k5 # AVX512CD -+ vptestnmq 0x123(%rax,%r14,8), %zmm29, %k5 # AVX512CD -+ vptestnmq (%rcx){1to8}, %zmm29, %k5 # AVX512CD -+ vptestnmq 8128(%rdx), %zmm29, %k5 # AVX512CD Disp8 -+ vptestnmq 8192(%rdx), %zmm29, %k5 # AVX512CD -+ vptestnmq -8192(%rdx), %zmm29, %k5 # AVX512CD Disp8 -+ vptestnmq -8256(%rdx), %zmm29, %k5 # AVX512CD -+ vptestnmq 1016(%rdx){1to8}, %zmm29, %k5 # AVX512CD Disp8 -+ vptestnmq 1024(%rdx){1to8}, %zmm29, %k5 # AVX512CD -+ vptestnmq -1024(%rdx){1to8}, %zmm29, %k5 # AVX512CD Disp8 -+ vptestnmq -1032(%rdx){1to8}, %zmm29, %k5 # AVX512CD -+ + vpbroadcastmw2d %k6, %zmm30 # AVX512CD + + vpbroadcastmb2q %k6, %zmm30 # AVX512CD @@ -1367813,34 +1375522,6 @@ index 0000000..1d6e015 + vplzcntq zmm30, [rdx-1024]{1to8} # AVX512CD Disp8 + vplzcntq zmm30, [rdx-1032]{1to8} # AVX512CD + -+ vptestnmd k5, zmm29, zmm28 # AVX512CD -+ vptestnmd k5{k7}, zmm29, zmm28 # AVX512CD -+ vptestnmd k5, zmm29, ZMMWORD PTR [rcx] # AVX512CD -+ vptestnmd k5, zmm29, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512CD -+ vptestnmd k5, zmm29, [rcx]{1to16} # AVX512CD -+ vptestnmd k5, zmm29, ZMMWORD PTR [rdx+8128] # AVX512CD Disp8 -+ vptestnmd k5, zmm29, ZMMWORD PTR [rdx+8192] # AVX512CD -+ vptestnmd k5, zmm29, ZMMWORD PTR [rdx-8192] # AVX512CD Disp8 -+ vptestnmd k5, zmm29, ZMMWORD PTR [rdx-8256] # AVX512CD -+ vptestnmd k5, zmm29, [rdx+508]{1to16} # AVX512CD Disp8 -+ vptestnmd k5, zmm29, [rdx+512]{1to16} # AVX512CD -+ vptestnmd k5, zmm29, [rdx-512]{1to16} # AVX512CD Disp8 -+ vptestnmd k5, zmm29, [rdx-516]{1to16} # AVX512CD -+ -+ vptestnmq k5, zmm29, zmm28 # AVX512CD -+ vptestnmq k5{k7}, zmm29, zmm28 # AVX512CD -+ vptestnmq k5, zmm29, ZMMWORD PTR [rcx] # AVX512CD -+ vptestnmq k5, zmm29, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512CD -+ vptestnmq k5, zmm29, [rcx]{1to8} # AVX512CD -+ vptestnmq k5, zmm29, ZMMWORD PTR [rdx+8128] # AVX512CD Disp8 -+ vptestnmq k5, zmm29, ZMMWORD PTR [rdx+8192] # AVX512CD -+ vptestnmq k5, zmm29, ZMMWORD PTR [rdx-8192] # AVX512CD Disp8 -+ vptestnmq k5, zmm29, ZMMWORD PTR [rdx-8256] # AVX512CD -+ vptestnmq k5, zmm29, [rdx+1016]{1to8} # AVX512CD Disp8 -+ vptestnmq k5, zmm29, [rdx+1024]{1to8} # AVX512CD -+ vptestnmq k5, zmm29, [rdx-1024]{1to8} # AVX512CD Disp8 -+ vptestnmq k5, zmm29, [rdx-1032]{1to8} # AVX512CD -+ + vpbroadcastmw2d zmm30, k6 # AVX512CD + + vpbroadcastmb2q zmm30, k6 # AVX512CD @@ -1368647,10 +1376328,10 @@ index 0000000..6e50968 + diff --git a/gas/testsuite/gas/i386/x86-64-avx512f-intel.d b/gas/testsuite/gas/i386/x86-64-avx512f-intel.d new file mode 100644 -index 0000000..ff9b409 +index 0000000..e6e732a --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx512f-intel.d -@@ -0,0 +1,14000 @@ +@@ -0,0 +1,14052 @@ +#as: +#objdump: -dwMintel +#name: x86_64 AVX512F insns (Intel disassembly) @@ -1372319,10 +1380000,10 @@ index 0000000..ff9b409 +[ ]*[a-f0-9]+: 62 02 fd 41 93 b4 fe 7b 00 00 00 vgatherqpd zmm30\{k1\},ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\] +[ ]*[a-f0-9]+: 62 02 fd 41 93 74 39 20 vgatherqpd zmm30\{k1\},ZMMWORD PTR \[r9\+zmm31\*1\+0x100\] +[ ]*[a-f0-9]+: 62 22 fd 41 93 b4 b9 00 04 00 00 vgatherqpd zmm30\{k1\},ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\] -+[ ]*[a-f0-9]+: 62 02 7d 41 93 b4 fe 7b 00 00 00 vgatherqps ymm30\{k1\},ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\] -+[ ]*[a-f0-9]+: 62 02 7d 41 93 b4 fe 7b 00 00 00 vgatherqps ymm30\{k1\},ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\] -+[ ]*[a-f0-9]+: 62 02 7d 41 93 74 39 40 vgatherqps ymm30\{k1\},ZMMWORD PTR \[r9\+zmm31\*1\+0x100\] -+[ ]*[a-f0-9]+: 62 22 7d 41 93 b4 b9 00 04 00 00 vgatherqps ymm30\{k1\},ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\] ++[ ]*[a-f0-9]+: 62 02 7d 41 93 b4 fe 7b 00 00 00 vgatherqps ymm30\{k1\},YMMWORD PTR \[r14\+zmm31\*8\+0x7b\] ++[ ]*[a-f0-9]+: 62 02 7d 41 93 b4 fe 7b 00 00 00 vgatherqps ymm30\{k1\},YMMWORD PTR \[r14\+zmm31\*8\+0x7b\] ++[ ]*[a-f0-9]+: 62 02 7d 41 93 74 39 40 vgatherqps ymm30\{k1\},YMMWORD PTR \[r9\+zmm31\*1\+0x100\] ++[ ]*[a-f0-9]+: 62 22 7d 41 93 b4 b9 00 04 00 00 vgatherqps ymm30\{k1\},YMMWORD PTR \[rcx\+zmm31\*4\+0x400\] +[ ]*[a-f0-9]+: 62 02 fd 48 42 f5 vgetexppd zmm30,zmm29 +[ ]*[a-f0-9]+: 62 02 fd 4f 42 f5 vgetexppd zmm30\{k7\},zmm29 +[ ]*[a-f0-9]+: 62 02 fd cf 42 f5 vgetexppd zmm30\{k7\}\{z\},zmm29 @@ -1373591,10 +1381272,10 @@ index 0000000..ff9b409 +[ ]*[a-f0-9]+: 62 02 fd 41 90 b4 fe 7b 00 00 00 vpgatherdq zmm30\{k1\},ZMMWORD PTR \[r14\+ymm31\*8\+0x7b\] +[ ]*[a-f0-9]+: 62 02 fd 41 90 74 39 20 vpgatherdq zmm30\{k1\},ZMMWORD PTR \[r9\+ymm31\*1\+0x100\] +[ ]*[a-f0-9]+: 62 22 fd 41 90 b4 b9 00 04 00 00 vpgatherdq zmm30\{k1\},ZMMWORD PTR \[rcx\+ymm31\*4\+0x400\] -+[ ]*[a-f0-9]+: 62 02 7d 41 91 b4 fe 7b 00 00 00 vpgatherqd ymm30\{k1\},ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\] -+[ ]*[a-f0-9]+: 62 02 7d 41 91 b4 fe 7b 00 00 00 vpgatherqd ymm30\{k1\},ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\] -+[ ]*[a-f0-9]+: 62 02 7d 41 91 74 39 40 vpgatherqd ymm30\{k1\},ZMMWORD PTR \[r9\+zmm31\*1\+0x100\] -+[ ]*[a-f0-9]+: 62 22 7d 41 91 b4 b9 00 04 00 00 vpgatherqd ymm30\{k1\},ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\] ++[ ]*[a-f0-9]+: 62 02 7d 41 91 b4 fe 7b 00 00 00 vpgatherqd ymm30\{k1\},YMMWORD PTR \[r14\+zmm31\*8\+0x7b\] ++[ ]*[a-f0-9]+: 62 02 7d 41 91 b4 fe 7b 00 00 00 vpgatherqd ymm30\{k1\},YMMWORD PTR \[r14\+zmm31\*8\+0x7b\] ++[ ]*[a-f0-9]+: 62 02 7d 41 91 74 39 40 vpgatherqd ymm30\{k1\},YMMWORD PTR \[r9\+zmm31\*1\+0x100\] ++[ ]*[a-f0-9]+: 62 22 7d 41 91 b4 b9 00 04 00 00 vpgatherqd ymm30\{k1\},YMMWORD PTR \[rcx\+zmm31\*4\+0x400\] +[ ]*[a-f0-9]+: 62 02 fd 41 91 b4 fe 7b 00 00 00 vpgatherqq zmm30\{k1\},ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\] +[ ]*[a-f0-9]+: 62 02 fd 41 91 b4 fe 7b 00 00 00 vpgatherqq zmm30\{k1\},ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\] +[ ]*[a-f0-9]+: 62 02 fd 41 91 74 39 20 vpgatherqq zmm30\{k1\},ZMMWORD PTR \[r9\+zmm31\*1\+0x100\] @@ -1373869,10 +1381550,10 @@ index 0000000..ff9b409 +[ ]*[a-f0-9]+: 62 02 fd 41 a0 b4 fe 7b 00 00 00 vpscatterdq ZMMWORD PTR \[r14\+ymm31\*8\+0x7b\]\{k1\},zmm30 +[ ]*[a-f0-9]+: 62 02 fd 41 a0 74 39 20 vpscatterdq ZMMWORD PTR \[r9\+ymm31\*1\+0x100\]\{k1\},zmm30 +[ ]*[a-f0-9]+: 62 22 fd 41 a0 b4 b9 00 04 00 00 vpscatterdq ZMMWORD PTR \[rcx\+ymm31\*4\+0x400\]\{k1\},zmm30 -+[ ]*[a-f0-9]+: 62 02 7d 41 a1 b4 fe 7b 00 00 00 vpscatterqd ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\},ymm30 -+[ ]*[a-f0-9]+: 62 02 7d 41 a1 b4 fe 7b 00 00 00 vpscatterqd ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\},ymm30 -+[ ]*[a-f0-9]+: 62 02 7d 41 a1 74 39 40 vpscatterqd ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\},ymm30 -+[ ]*[a-f0-9]+: 62 22 7d 41 a1 b4 b9 00 04 00 00 vpscatterqd ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\},ymm30 ++[ ]*[a-f0-9]+: 62 02 7d 41 a1 b4 fe 7b 00 00 00 vpscatterqd YMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\},ymm30 ++[ ]*[a-f0-9]+: 62 02 7d 41 a1 b4 fe 7b 00 00 00 vpscatterqd YMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\},ymm30 ++[ ]*[a-f0-9]+: 62 02 7d 41 a1 74 39 40 vpscatterqd YMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\},ymm30 ++[ ]*[a-f0-9]+: 62 22 7d 41 a1 b4 b9 00 04 00 00 vpscatterqd YMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\},ymm30 +[ ]*[a-f0-9]+: 62 02 fd 41 a1 b4 fe 7b 00 00 00 vpscatterqq ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\},zmm30 +[ ]*[a-f0-9]+: 62 02 fd 41 a1 b4 fe 7b 00 00 00 vpscatterqq ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\},zmm30 +[ ]*[a-f0-9]+: 62 02 fd 41 a1 74 39 20 vpscatterqq ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\},zmm30 @@ -1374292,10 +1381973,10 @@ index 0000000..ff9b409 +[ ]*[a-f0-9]+: 62 02 fd 41 a3 b4 fe 7b 00 00 00 vscatterqpd ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\},zmm30 +[ ]*[a-f0-9]+: 62 02 fd 41 a3 74 39 20 vscatterqpd ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\},zmm30 +[ ]*[a-f0-9]+: 62 22 fd 41 a3 b4 b9 00 04 00 00 vscatterqpd ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\},zmm30 -+[ ]*[a-f0-9]+: 62 02 7d 41 a3 b4 fe 7b 00 00 00 vscatterqps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\},ymm30 -+[ ]*[a-f0-9]+: 62 02 7d 41 a3 b4 fe 7b 00 00 00 vscatterqps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\},ymm30 -+[ ]*[a-f0-9]+: 62 02 7d 41 a3 74 39 40 vscatterqps ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\},ymm30 -+[ ]*[a-f0-9]+: 62 22 7d 41 a3 b4 b9 00 04 00 00 vscatterqps ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\},ymm30 ++[ ]*[a-f0-9]+: 62 02 7d 41 a3 b4 fe 7b 00 00 00 vscatterqps YMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\},ymm30 ++[ ]*[a-f0-9]+: 62 02 7d 41 a3 b4 fe 7b 00 00 00 vscatterqps YMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\},ymm30 ++[ ]*[a-f0-9]+: 62 02 7d 41 a3 74 39 40 vscatterqps YMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\},ymm30 ++[ ]*[a-f0-9]+: 62 22 7d 41 a3 b4 b9 00 04 00 00 vscatterqps YMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\},ymm30 +[ ]*[a-f0-9]+: 62 01 95 40 c6 f4 ab vshufpd zmm30,zmm29,zmm28,0xab +[ ]*[a-f0-9]+: 62 01 95 47 c6 f4 ab vshufpd zmm30\{k7\},zmm29,zmm28,0xab +[ ]*[a-f0-9]+: 62 01 95 c7 c6 f4 ab vshufpd zmm30\{k7\}\{z\},zmm29,zmm28,0xab @@ -1375656,6 +1383337,32 @@ index 0000000..ff9b409 +[ ]*[a-f0-9]+: 62 62 95 50 77 b2 00 04 00 00 vpermi2pd zmm30,zmm29,QWORD PTR \[rdx\+0x400\]\{1to8\} +[ ]*[a-f0-9]+: 62 62 95 50 77 72 80 vpermi2pd zmm30,zmm29,QWORD PTR \[rdx-0x400\]\{1to8\} +[ ]*[a-f0-9]+: 62 62 95 50 77 b2 f8 fb ff ff vpermi2pd zmm30,zmm29,QWORD PTR \[rdx-0x408\]\{1to8\} ++[ ]*[a-f0-9]+: 62 92 16 40 27 ec vptestnmd k5,zmm29,zmm28 ++[ ]*[a-f0-9]+: 62 92 16 47 27 ec vptestnmd k5\{k7\},zmm29,zmm28 ++[ ]*[a-f0-9]+: 62 f2 16 40 27 29 vptestnmd k5,zmm29,ZMMWORD PTR \[rcx\] ++[ ]*[a-f0-9]+: 62 b2 16 40 27 ac f0 23 01 00 00 vptestnmd k5,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x123\] ++[ ]*[a-f0-9]+: 62 f2 16 50 27 29 vptestnmd k5,zmm29,DWORD PTR \[rcx\]\{1to16\} ++[ ]*[a-f0-9]+: 62 f2 16 40 27 6a 7f vptestnmd k5,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\] ++[ ]*[a-f0-9]+: 62 f2 16 40 27 aa 00 20 00 00 vptestnmd k5,zmm29,ZMMWORD PTR \[rdx\+0x2000\] ++[ ]*[a-f0-9]+: 62 f2 16 40 27 6a 80 vptestnmd k5,zmm29,ZMMWORD PTR \[rdx-0x2000\] ++[ ]*[a-f0-9]+: 62 f2 16 40 27 aa c0 df ff ff vptestnmd k5,zmm29,ZMMWORD PTR \[rdx-0x2040\] ++[ ]*[a-f0-9]+: 62 f2 16 50 27 6a 7f vptestnmd k5,zmm29,DWORD PTR \[rdx\+0x1fc\]\{1to16\} ++[ ]*[a-f0-9]+: 62 f2 16 50 27 aa 00 02 00 00 vptestnmd k5,zmm29,DWORD PTR \[rdx\+0x200\]\{1to16\} ++[ ]*[a-f0-9]+: 62 f2 16 50 27 6a 80 vptestnmd k5,zmm29,DWORD PTR \[rdx-0x200\]\{1to16\} ++[ ]*[a-f0-9]+: 62 f2 16 50 27 aa fc fd ff ff vptestnmd k5,zmm29,DWORD PTR \[rdx-0x204\]\{1to16\} ++[ ]*[a-f0-9]+: 62 92 96 40 27 ec vptestnmq k5,zmm29,zmm28 ++[ ]*[a-f0-9]+: 62 92 96 47 27 ec vptestnmq k5\{k7\},zmm29,zmm28 ++[ ]*[a-f0-9]+: 62 f2 96 40 27 29 vptestnmq k5,zmm29,ZMMWORD PTR \[rcx\] ++[ ]*[a-f0-9]+: 62 b2 96 40 27 ac f0 23 01 00 00 vptestnmq k5,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x123\] ++[ ]*[a-f0-9]+: 62 f2 96 50 27 29 vptestnmq k5,zmm29,QWORD PTR \[rcx\]\{1to8\} ++[ ]*[a-f0-9]+: 62 f2 96 40 27 6a 7f vptestnmq k5,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\] ++[ ]*[a-f0-9]+: 62 f2 96 40 27 aa 00 20 00 00 vptestnmq k5,zmm29,ZMMWORD PTR \[rdx\+0x2000\] ++[ ]*[a-f0-9]+: 62 f2 96 40 27 6a 80 vptestnmq k5,zmm29,ZMMWORD PTR \[rdx-0x2000\] ++[ ]*[a-f0-9]+: 62 f2 96 40 27 aa c0 df ff ff vptestnmq k5,zmm29,ZMMWORD PTR \[rdx-0x2040\] ++[ ]*[a-f0-9]+: 62 f2 96 50 27 6a 7f vptestnmq k5,zmm29,QWORD PTR \[rdx\+0x3f8\]\{1to8\} ++[ ]*[a-f0-9]+: 62 f2 96 50 27 aa 00 04 00 00 vptestnmq k5,zmm29,QWORD PTR \[rdx\+0x400\]\{1to8\} ++[ ]*[a-f0-9]+: 62 f2 96 50 27 6a 80 vptestnmq k5,zmm29,QWORD PTR \[rdx-0x400\]\{1to8\} ++[ ]*[a-f0-9]+: 62 f2 96 50 27 aa f8 fb ff ff vptestnmq k5,zmm29,QWORD PTR \[rdx-0x408\]\{1to8\} +[ ]*[a-f0-9]+: 62 01 95 40 58 f4 vaddpd zmm30,zmm29,zmm28 +[ ]*[a-f0-9]+: 62 01 95 47 58 f4 vaddpd zmm30\{k7\},zmm29,zmm28 +[ ]*[a-f0-9]+: 62 01 95 c7 58 f4 vaddpd zmm30\{k7\}\{z\},zmm29,zmm28 @@ -1379313,10 +1387020,10 @@ index 0000000..ff9b409 +[ ]*[a-f0-9]+: 62 02 fd 41 93 b4 fe 85 ff ff ff vgatherqpd zmm30\{k1\},ZMMWORD PTR \[r14\+zmm31\*8-0x7b\] +[ ]*[a-f0-9]+: 62 02 fd 41 93 74 39 20 vgatherqpd zmm30\{k1\},ZMMWORD PTR \[r9\+zmm31\*1\+0x100\] +[ ]*[a-f0-9]+: 62 22 fd 41 93 b4 b9 00 04 00 00 vgatherqpd zmm30\{k1\},ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\] -+[ ]*[a-f0-9]+: 62 02 7d 41 93 b4 fe 85 ff ff ff vgatherqps ymm30\{k1\},ZMMWORD PTR \[r14\+zmm31\*8-0x7b\] -+[ ]*[a-f0-9]+: 62 02 7d 41 93 b4 fe 85 ff ff ff vgatherqps ymm30\{k1\},ZMMWORD PTR \[r14\+zmm31\*8-0x7b\] -+[ ]*[a-f0-9]+: 62 02 7d 41 93 74 39 40 vgatherqps ymm30\{k1\},ZMMWORD PTR \[r9\+zmm31\*1\+0x100\] -+[ ]*[a-f0-9]+: 62 22 7d 41 93 b4 b9 00 04 00 00 vgatherqps ymm30\{k1\},ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\] ++[ ]*[a-f0-9]+: 62 02 7d 41 93 b4 fe 85 ff ff ff vgatherqps ymm30\{k1\},YMMWORD PTR \[r14\+zmm31\*8-0x7b\] ++[ ]*[a-f0-9]+: 62 02 7d 41 93 b4 fe 85 ff ff ff vgatherqps ymm30\{k1\},YMMWORD PTR \[r14\+zmm31\*8-0x7b\] ++[ ]*[a-f0-9]+: 62 02 7d 41 93 74 39 40 vgatherqps ymm30\{k1\},YMMWORD PTR \[r9\+zmm31\*1\+0x100\] ++[ ]*[a-f0-9]+: 62 22 7d 41 93 b4 b9 00 04 00 00 vgatherqps ymm30\{k1\},YMMWORD PTR \[rcx\+zmm31\*4\+0x400\] +[ ]*[a-f0-9]+: 62 02 fd 48 42 f5 vgetexppd zmm30,zmm29 +[ ]*[a-f0-9]+: 62 02 fd 4f 42 f5 vgetexppd zmm30\{k7\},zmm29 +[ ]*[a-f0-9]+: 62 02 fd cf 42 f5 vgetexppd zmm30\{k7\}\{z\},zmm29 @@ -1380585,10 +1388292,10 @@ index 0000000..ff9b409 +[ ]*[a-f0-9]+: 62 02 fd 41 90 b4 fe 85 ff ff ff vpgatherdq zmm30\{k1\},ZMMWORD PTR \[r14\+ymm31\*8-0x7b\] +[ ]*[a-f0-9]+: 62 02 fd 41 90 74 39 20 vpgatherdq zmm30\{k1\},ZMMWORD PTR \[r9\+ymm31\*1\+0x100\] +[ ]*[a-f0-9]+: 62 22 fd 41 90 b4 b9 00 04 00 00 vpgatherdq zmm30\{k1\},ZMMWORD PTR \[rcx\+ymm31\*4\+0x400\] -+[ ]*[a-f0-9]+: 62 02 7d 41 91 b4 fe 85 ff ff ff vpgatherqd ymm30\{k1\},ZMMWORD PTR \[r14\+zmm31\*8-0x7b\] -+[ ]*[a-f0-9]+: 62 02 7d 41 91 b4 fe 85 ff ff ff vpgatherqd ymm30\{k1\},ZMMWORD PTR \[r14\+zmm31\*8-0x7b\] -+[ ]*[a-f0-9]+: 62 02 7d 41 91 74 39 40 vpgatherqd ymm30\{k1\},ZMMWORD PTR \[r9\+zmm31\*1\+0x100\] -+[ ]*[a-f0-9]+: 62 22 7d 41 91 b4 b9 00 04 00 00 vpgatherqd ymm30\{k1\},ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\] ++[ ]*[a-f0-9]+: 62 02 7d 41 91 b4 fe 85 ff ff ff vpgatherqd ymm30\{k1\},YMMWORD PTR \[r14\+zmm31\*8-0x7b\] ++[ ]*[a-f0-9]+: 62 02 7d 41 91 b4 fe 85 ff ff ff vpgatherqd ymm30\{k1\},YMMWORD PTR \[r14\+zmm31\*8-0x7b\] ++[ ]*[a-f0-9]+: 62 02 7d 41 91 74 39 40 vpgatherqd ymm30\{k1\},YMMWORD PTR \[r9\+zmm31\*1\+0x100\] ++[ ]*[a-f0-9]+: 62 22 7d 41 91 b4 b9 00 04 00 00 vpgatherqd ymm30\{k1\},YMMWORD PTR \[rcx\+zmm31\*4\+0x400\] +[ ]*[a-f0-9]+: 62 02 fd 41 91 b4 fe 85 ff ff ff vpgatherqq zmm30\{k1\},ZMMWORD PTR \[r14\+zmm31\*8-0x7b\] +[ ]*[a-f0-9]+: 62 02 fd 41 91 b4 fe 85 ff ff ff vpgatherqq zmm30\{k1\},ZMMWORD PTR \[r14\+zmm31\*8-0x7b\] +[ ]*[a-f0-9]+: 62 02 fd 41 91 74 39 20 vpgatherqq zmm30\{k1\},ZMMWORD PTR \[r9\+zmm31\*1\+0x100\] @@ -1380863,10 +1388570,10 @@ index 0000000..ff9b409 +[ ]*[a-f0-9]+: 62 02 fd 41 a0 b4 fe 85 ff ff ff vpscatterdq ZMMWORD PTR \[r14\+ymm31\*8-0x7b\]\{k1\},zmm30 +[ ]*[a-f0-9]+: 62 02 fd 41 a0 74 39 20 vpscatterdq ZMMWORD PTR \[r9\+ymm31\*1\+0x100\]\{k1\},zmm30 +[ ]*[a-f0-9]+: 62 22 fd 41 a0 b4 b9 00 04 00 00 vpscatterdq ZMMWORD PTR \[rcx\+ymm31\*4\+0x400\]\{k1\},zmm30 -+[ ]*[a-f0-9]+: 62 02 7d 41 a1 b4 fe 85 ff ff ff vpscatterqd ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\},ymm30 -+[ ]*[a-f0-9]+: 62 02 7d 41 a1 b4 fe 85 ff ff ff vpscatterqd ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\},ymm30 -+[ ]*[a-f0-9]+: 62 02 7d 41 a1 74 39 40 vpscatterqd ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\},ymm30 -+[ ]*[a-f0-9]+: 62 22 7d 41 a1 b4 b9 00 04 00 00 vpscatterqd ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\},ymm30 ++[ ]*[a-f0-9]+: 62 02 7d 41 a1 b4 fe 85 ff ff ff vpscatterqd YMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\},ymm30 ++[ ]*[a-f0-9]+: 62 02 7d 41 a1 b4 fe 85 ff ff ff vpscatterqd YMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\},ymm30 ++[ ]*[a-f0-9]+: 62 02 7d 41 a1 74 39 40 vpscatterqd YMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\},ymm30 ++[ ]*[a-f0-9]+: 62 22 7d 41 a1 b4 b9 00 04 00 00 vpscatterqd YMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\},ymm30 +[ ]*[a-f0-9]+: 62 02 fd 41 a1 b4 fe 85 ff ff ff vpscatterqq ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\},zmm30 +[ ]*[a-f0-9]+: 62 02 fd 41 a1 b4 fe 85 ff ff ff vpscatterqq ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\},zmm30 +[ ]*[a-f0-9]+: 62 02 fd 41 a1 74 39 20 vpscatterqq ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\},zmm30 @@ -1381286,10 +1388993,10 @@ index 0000000..ff9b409 +[ ]*[a-f0-9]+: 62 02 fd 41 a3 b4 fe 85 ff ff ff vscatterqpd ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\},zmm30 +[ ]*[a-f0-9]+: 62 02 fd 41 a3 74 39 20 vscatterqpd ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\},zmm30 +[ ]*[a-f0-9]+: 62 22 fd 41 a3 b4 b9 00 04 00 00 vscatterqpd ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\},zmm30 -+[ ]*[a-f0-9]+: 62 02 7d 41 a3 b4 fe 85 ff ff ff vscatterqps ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\},ymm30 -+[ ]*[a-f0-9]+: 62 02 7d 41 a3 b4 fe 85 ff ff ff vscatterqps ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\},ymm30 -+[ ]*[a-f0-9]+: 62 02 7d 41 a3 74 39 40 vscatterqps ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\},ymm30 -+[ ]*[a-f0-9]+: 62 22 7d 41 a3 b4 b9 00 04 00 00 vscatterqps ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\},ymm30 ++[ ]*[a-f0-9]+: 62 02 7d 41 a3 b4 fe 85 ff ff ff vscatterqps YMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\},ymm30 ++[ ]*[a-f0-9]+: 62 02 7d 41 a3 b4 fe 85 ff ff ff vscatterqps YMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\},ymm30 ++[ ]*[a-f0-9]+: 62 02 7d 41 a3 74 39 40 vscatterqps YMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\},ymm30 ++[ ]*[a-f0-9]+: 62 22 7d 41 a3 b4 b9 00 04 00 00 vscatterqps YMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\},ymm30 +[ ]*[a-f0-9]+: 62 01 95 40 c6 f4 ab vshufpd zmm30,zmm29,zmm28,0xab +[ ]*[a-f0-9]+: 62 01 95 47 c6 f4 ab vshufpd zmm30\{k7\},zmm29,zmm28,0xab +[ ]*[a-f0-9]+: 62 01 95 c7 c6 f4 ab vshufpd zmm30\{k7\}\{z\},zmm29,zmm28,0xab @@ -1382650,6 +1390357,32 @@ index 0000000..ff9b409 +[ ]*[a-f0-9]+: 62 62 95 50 77 b2 00 04 00 00 vpermi2pd zmm30,zmm29,QWORD PTR \[rdx\+0x400\]\{1to8\} +[ ]*[a-f0-9]+: 62 62 95 50 77 72 80 vpermi2pd zmm30,zmm29,QWORD PTR \[rdx-0x400\]\{1to8\} +[ ]*[a-f0-9]+: 62 62 95 50 77 b2 f8 fb ff ff vpermi2pd zmm30,zmm29,QWORD PTR \[rdx-0x408\]\{1to8\} ++[ ]*[a-f0-9]+: 62 92 16 40 27 ec vptestnmd k5,zmm29,zmm28 ++[ ]*[a-f0-9]+: 62 92 16 47 27 ec vptestnmd k5\{k7\},zmm29,zmm28 ++[ ]*[a-f0-9]+: 62 f2 16 40 27 29 vptestnmd k5,zmm29,ZMMWORD PTR \[rcx\] ++[ ]*[a-f0-9]+: 62 b2 16 40 27 ac f0 34 12 00 00 vptestnmd k5,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x1234\] ++[ ]*[a-f0-9]+: 62 f2 16 50 27 29 vptestnmd k5,zmm29,DWORD PTR \[rcx\]\{1to16\} ++[ ]*[a-f0-9]+: 62 f2 16 40 27 6a 7f vptestnmd k5,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\] ++[ ]*[a-f0-9]+: 62 f2 16 40 27 aa 00 20 00 00 vptestnmd k5,zmm29,ZMMWORD PTR \[rdx\+0x2000\] ++[ ]*[a-f0-9]+: 62 f2 16 40 27 6a 80 vptestnmd k5,zmm29,ZMMWORD PTR \[rdx-0x2000\] ++[ ]*[a-f0-9]+: 62 f2 16 40 27 aa c0 df ff ff vptestnmd k5,zmm29,ZMMWORD PTR \[rdx-0x2040\] ++[ ]*[a-f0-9]+: 62 f2 16 50 27 6a 7f vptestnmd k5,zmm29,DWORD PTR \[rdx\+0x1fc\]\{1to16\} ++[ ]*[a-f0-9]+: 62 f2 16 50 27 aa 00 02 00 00 vptestnmd k5,zmm29,DWORD PTR \[rdx\+0x200\]\{1to16\} ++[ ]*[a-f0-9]+: 62 f2 16 50 27 6a 80 vptestnmd k5,zmm29,DWORD PTR \[rdx-0x200\]\{1to16\} ++[ ]*[a-f0-9]+: 62 f2 16 50 27 aa fc fd ff ff vptestnmd k5,zmm29,DWORD PTR \[rdx-0x204\]\{1to16\} ++[ ]*[a-f0-9]+: 62 92 96 40 27 ec vptestnmq k5,zmm29,zmm28 ++[ ]*[a-f0-9]+: 62 92 96 47 27 ec vptestnmq k5\{k7\},zmm29,zmm28 ++[ ]*[a-f0-9]+: 62 f2 96 40 27 29 vptestnmq k5,zmm29,ZMMWORD PTR \[rcx\] ++[ ]*[a-f0-9]+: 62 b2 96 40 27 ac f0 34 12 00 00 vptestnmq k5,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x1234\] ++[ ]*[a-f0-9]+: 62 f2 96 50 27 29 vptestnmq k5,zmm29,QWORD PTR \[rcx\]\{1to8\} ++[ ]*[a-f0-9]+: 62 f2 96 40 27 6a 7f vptestnmq k5,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\] ++[ ]*[a-f0-9]+: 62 f2 96 40 27 aa 00 20 00 00 vptestnmq k5,zmm29,ZMMWORD PTR \[rdx\+0x2000\] ++[ ]*[a-f0-9]+: 62 f2 96 40 27 6a 80 vptestnmq k5,zmm29,ZMMWORD PTR \[rdx-0x2000\] ++[ ]*[a-f0-9]+: 62 f2 96 40 27 aa c0 df ff ff vptestnmq k5,zmm29,ZMMWORD PTR \[rdx-0x2040\] ++[ ]*[a-f0-9]+: 62 f2 96 50 27 6a 7f vptestnmq k5,zmm29,QWORD PTR \[rdx\+0x3f8\]\{1to8\} ++[ ]*[a-f0-9]+: 62 f2 96 50 27 aa 00 04 00 00 vptestnmq k5,zmm29,QWORD PTR \[rdx\+0x400\]\{1to8\} ++[ ]*[a-f0-9]+: 62 f2 96 50 27 6a 80 vptestnmq k5,zmm29,QWORD PTR \[rdx-0x400\]\{1to8\} ++[ ]*[a-f0-9]+: 62 f2 96 50 27 aa f8 fb ff ff vptestnmq k5,zmm29,QWORD PTR \[rdx-0x408\]\{1to8\} +#pass diff --git a/gas/testsuite/gas/i386/x86-64-avx512f-nondef.d b/gas/testsuite/gas/i386/x86-64-avx512f-nondef.d new file mode 100644 @@ -1383155,10 +1390888,10 @@ index 0000000..997c846 + vmovups zmm30{k7}{z}, zmm29 # AVX512F diff --git a/gas/testsuite/gas/i386/x86-64-avx512f.d b/gas/testsuite/gas/i386/x86-64-avx512f.d new file mode 100644 -index 0000000..a25ff9b +index 0000000..d672fa5 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx512f.d -@@ -0,0 +1,13999 @@ +@@ -0,0 +1,14051 @@ +#as: +#objdump: -dw +#name: x86_64 AVX512F insns @@ -1390163,6 +1397896,32 @@ index 0000000..a25ff9b +[ ]*[a-f0-9]+: 62 62 95 50 77 b2 00 04 00 00 vpermi2pd 0x400\(%rdx\)\{1to8\},%zmm29,%zmm30 +[ ]*[a-f0-9]+: 62 62 95 50 77 72 80 vpermi2pd -0x400\(%rdx\)\{1to8\},%zmm29,%zmm30 +[ ]*[a-f0-9]+: 62 62 95 50 77 b2 f8 fb ff ff vpermi2pd -0x408\(%rdx\)\{1to8\},%zmm29,%zmm30 ++[ ]*[a-f0-9]+: 62 92 16 40 27 ec vptestnmd %zmm28,%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 92 16 47 27 ec vptestnmd %zmm28,%zmm29,%k5\{%k7\} ++[ ]*[a-f0-9]+: 62 f2 16 40 27 29 vptestnmd \(%rcx\),%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 b2 16 40 27 ac f0 23 01 00 00 vptestnmd 0x123\(%rax,%r14,8\),%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 16 50 27 29 vptestnmd \(%rcx\)\{1to16\},%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 16 40 27 6a 7f vptestnmd 0x1fc0\(%rdx\),%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 16 40 27 aa 00 20 00 00 vptestnmd 0x2000\(%rdx\),%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 16 40 27 6a 80 vptestnmd -0x2000\(%rdx\),%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 16 40 27 aa c0 df ff ff vptestnmd -0x2040\(%rdx\),%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 16 50 27 6a 7f vptestnmd 0x1fc\(%rdx\)\{1to16\},%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 16 50 27 aa 00 02 00 00 vptestnmd 0x200\(%rdx\)\{1to16\},%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 16 50 27 6a 80 vptestnmd -0x200\(%rdx\)\{1to16\},%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 16 50 27 aa fc fd ff ff vptestnmd -0x204\(%rdx\)\{1to16\},%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 92 96 40 27 ec vptestnmq %zmm28,%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 92 96 47 27 ec vptestnmq %zmm28,%zmm29,%k5\{%k7\} ++[ ]*[a-f0-9]+: 62 f2 96 40 27 29 vptestnmq \(%rcx\),%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 b2 96 40 27 ac f0 23 01 00 00 vptestnmq 0x123\(%rax,%r14,8\),%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 96 50 27 29 vptestnmq \(%rcx\)\{1to8\},%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 96 40 27 6a 7f vptestnmq 0x1fc0\(%rdx\),%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 96 40 27 aa 00 20 00 00 vptestnmq 0x2000\(%rdx\),%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 96 40 27 6a 80 vptestnmq -0x2000\(%rdx\),%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 96 40 27 aa c0 df ff ff vptestnmq -0x2040\(%rdx\),%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 96 50 27 6a 7f vptestnmq 0x3f8\(%rdx\)\{1to8\},%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 96 50 27 aa 00 04 00 00 vptestnmq 0x400\(%rdx\)\{1to8\},%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 96 50 27 6a 80 vptestnmq -0x400\(%rdx\)\{1to8\},%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 96 50 27 aa f8 fb ff ff vptestnmq -0x408\(%rdx\)\{1to8\},%zmm29,%k5 +[ ]*[a-f0-9]+: 62 01 95 40 58 f4 vaddpd %zmm28,%zmm29,%zmm30 +[ ]*[a-f0-9]+: 62 01 95 47 58 f4 vaddpd %zmm28,%zmm29,%zmm30\{%k7\} +[ ]*[a-f0-9]+: 62 01 95 c7 58 f4 vaddpd %zmm28,%zmm29,%zmm30\{%k7\}\{z\} @@ -1397157,13 +1404916,39 @@ index 0000000..a25ff9b +[ ]*[a-f0-9]+: 62 62 95 50 77 b2 00 04 00 00 vpermi2pd 0x400\(%rdx\)\{1to8\},%zmm29,%zmm30 +[ ]*[a-f0-9]+: 62 62 95 50 77 72 80 vpermi2pd -0x400\(%rdx\)\{1to8\},%zmm29,%zmm30 +[ ]*[a-f0-9]+: 62 62 95 50 77 b2 f8 fb ff ff vpermi2pd -0x408\(%rdx\)\{1to8\},%zmm29,%zmm30 ++[ ]*[a-f0-9]+: 62 92 16 40 27 ec vptestnmd %zmm28,%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 92 16 47 27 ec vptestnmd %zmm28,%zmm29,%k5\{%k7\} ++[ ]*[a-f0-9]+: 62 f2 16 40 27 29 vptestnmd \(%rcx\),%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 b2 16 40 27 ac f0 34 12 00 00 vptestnmd 0x1234\(%rax,%r14,8\),%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 16 50 27 29 vptestnmd \(%rcx\)\{1to16\},%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 16 40 27 6a 7f vptestnmd 0x1fc0\(%rdx\),%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 16 40 27 aa 00 20 00 00 vptestnmd 0x2000\(%rdx\),%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 16 40 27 6a 80 vptestnmd -0x2000\(%rdx\),%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 16 40 27 aa c0 df ff ff vptestnmd -0x2040\(%rdx\),%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 16 50 27 6a 7f vptestnmd 0x1fc\(%rdx\)\{1to16\},%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 16 50 27 aa 00 02 00 00 vptestnmd 0x200\(%rdx\)\{1to16\},%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 16 50 27 6a 80 vptestnmd -0x200\(%rdx\)\{1to16\},%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 16 50 27 aa fc fd ff ff vptestnmd -0x204\(%rdx\)\{1to16\},%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 92 96 40 27 ec vptestnmq %zmm28,%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 92 96 47 27 ec vptestnmq %zmm28,%zmm29,%k5\{%k7\} ++[ ]*[a-f0-9]+: 62 f2 96 40 27 29 vptestnmq \(%rcx\),%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 b2 96 40 27 ac f0 34 12 00 00 vptestnmq 0x1234\(%rax,%r14,8\),%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 96 50 27 29 vptestnmq \(%rcx\)\{1to8\},%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 96 40 27 6a 7f vptestnmq 0x1fc0\(%rdx\),%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 96 40 27 aa 00 20 00 00 vptestnmq 0x2000\(%rdx\),%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 96 40 27 6a 80 vptestnmq -0x2000\(%rdx\),%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 96 40 27 aa c0 df ff ff vptestnmq -0x2040\(%rdx\),%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 96 50 27 6a 7f vptestnmq 0x3f8\(%rdx\)\{1to8\},%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 96 50 27 aa 00 04 00 00 vptestnmq 0x400\(%rdx\)\{1to8\},%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 96 50 27 6a 80 vptestnmq -0x400\(%rdx\)\{1to8\},%zmm29,%k5 ++[ ]*[a-f0-9]+: 62 f2 96 50 27 aa f8 fb ff ff vptestnmq -0x408\(%rdx\)\{1to8\},%zmm29,%k5 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-avx512f.s b/gas/testsuite/gas/i386/x86-64-avx512f.s new file mode 100644 -index 0000000..856153b +index 0000000..b8479d9 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx512f.s -@@ -0,0 +1,15263 @@ +@@ -0,0 +1,15318 @@ +# Check 64bit AVX512F instructions + + .allow_index_reg @@ -1404798,6 +1412583,34 @@ index 0000000..856153b + vpermi2pd -1024(%rdx){1to8}, %zmm29, %zmm30 # AVX512F Disp8 + vpermi2pd -1032(%rdx){1to8}, %zmm29, %zmm30 # AVX512F + ++ vptestnmd %zmm28, %zmm29, %k5 # AVX512CD ++ vptestnmd %zmm28, %zmm29, %k5{%k7} # AVX512CD ++ vptestnmd (%rcx), %zmm29, %k5 # AVX512CD ++ vptestnmd 0x123(%rax,%r14,8), %zmm29, %k5 # AVX512CD ++ vptestnmd (%rcx){1to16}, %zmm29, %k5 # AVX512CD ++ vptestnmd 8128(%rdx), %zmm29, %k5 # AVX512CD Disp8 ++ vptestnmd 8192(%rdx), %zmm29, %k5 # AVX512CD ++ vptestnmd -8192(%rdx), %zmm29, %k5 # AVX512CD Disp8 ++ vptestnmd -8256(%rdx), %zmm29, %k5 # AVX512CD ++ vptestnmd 508(%rdx){1to16}, %zmm29, %k5 # AVX512CD Disp8 ++ vptestnmd 512(%rdx){1to16}, %zmm29, %k5 # AVX512CD ++ vptestnmd -512(%rdx){1to16}, %zmm29, %k5 # AVX512CD Disp8 ++ vptestnmd -516(%rdx){1to16}, %zmm29, %k5 # AVX512CD ++ ++ vptestnmq %zmm28, %zmm29, %k5 # AVX512CD ++ vptestnmq %zmm28, %zmm29, %k5{%k7} # AVX512CD ++ vptestnmq (%rcx), %zmm29, %k5 # AVX512CD ++ vptestnmq 0x123(%rax,%r14,8), %zmm29, %k5 # AVX512CD ++ vptestnmq (%rcx){1to8}, %zmm29, %k5 # AVX512CD ++ vptestnmq 8128(%rdx), %zmm29, %k5 # AVX512CD Disp8 ++ vptestnmq 8192(%rdx), %zmm29, %k5 # AVX512CD ++ vptestnmq -8192(%rdx), %zmm29, %k5 # AVX512CD Disp8 ++ vptestnmq -8256(%rdx), %zmm29, %k5 # AVX512CD ++ vptestnmq 1016(%rdx){1to8}, %zmm29, %k5 # AVX512CD Disp8 ++ vptestnmq 1024(%rdx){1to8}, %zmm29, %k5 # AVX512CD ++ vptestnmq -1024(%rdx){1to8}, %zmm29, %k5 # AVX512CD Disp8 ++ vptestnmq -1032(%rdx){1to8}, %zmm29, %k5 # AVX512CD ++ + .intel_syntax noprefix + vaddpd zmm30, zmm29, zmm28 # AVX512F + vaddpd zmm30{k7}, zmm29, zmm28 # AVX512F @@ -1408769,10 +1416582,10 @@ index 0000000..856153b + vgatherqpd zmm30{k1}, ZMMWORD PTR [r9+zmm31+256] # AVX512F + vgatherqpd zmm30{k1}, ZMMWORD PTR [rcx+zmm31*4+1024] # AVX512F + -+ vgatherqps ymm30{k1}, ZMMWORD PTR [r14+zmm31*8-123] # AVX512F -+ vgatherqps ymm30{k1}, ZMMWORD PTR [r14+zmm31*8-123] # AVX512F -+ vgatherqps ymm30{k1}, ZMMWORD PTR [r9+zmm31+256] # AVX512F -+ vgatherqps ymm30{k1}, ZMMWORD PTR [rcx+zmm31*4+1024] # AVX512F ++ vgatherqps ymm30{k1}, YMMWORD PTR [r14+zmm31*8-123] # AVX512F ++ vgatherqps ymm30{k1}, YMMWORD PTR [r14+zmm31*8-123] # AVX512F ++ vgatherqps ymm30{k1}, YMMWORD PTR [r9+zmm31+256] # AVX512F ++ vgatherqps ymm30{k1}, YMMWORD PTR [rcx+zmm31*4+1024] # AVX512F + + vgetexppd zmm30, zmm29 # AVX512F + vgetexppd zmm30{k7}, zmm29 # AVX512F @@ -1410166,10 +1417979,10 @@ index 0000000..856153b + vpgatherdq zmm30{k1}, ZMMWORD PTR [r9+ymm31+256] # AVX512F + vpgatherdq zmm30{k1}, ZMMWORD PTR [rcx+ymm31*4+1024] # AVX512F + -+ vpgatherqd ymm30{k1}, ZMMWORD PTR [r14+zmm31*8-123] # AVX512F -+ vpgatherqd ymm30{k1}, ZMMWORD PTR [r14+zmm31*8-123] # AVX512F -+ vpgatherqd ymm30{k1}, ZMMWORD PTR [r9+zmm31+256] # AVX512F -+ vpgatherqd ymm30{k1}, ZMMWORD PTR [rcx+zmm31*4+1024] # AVX512F ++ vpgatherqd ymm30{k1}, YMMWORD PTR [r14+zmm31*8-123] # AVX512F ++ vpgatherqd ymm30{k1}, YMMWORD PTR [r14+zmm31*8-123] # AVX512F ++ vpgatherqd ymm30{k1}, YMMWORD PTR [r9+zmm31+256] # AVX512F ++ vpgatherqd ymm30{k1}, YMMWORD PTR [rcx+zmm31*4+1024] # AVX512F + + vpgatherqq zmm30{k1}, ZMMWORD PTR [r14+zmm31*8-123] # AVX512F + vpgatherqq zmm30{k1}, ZMMWORD PTR [r14+zmm31*8-123] # AVX512F @@ -1410471,10 +1418284,10 @@ index 0000000..856153b + vpscatterdq ZMMWORD PTR [r9+ymm31+256]{k1}, zmm30 # AVX512F + vpscatterdq ZMMWORD PTR [rcx+ymm31*4+1024]{k1}, zmm30 # AVX512F + -+ vpscatterqd ZMMWORD PTR [r14+zmm31*8-123]{k1}, ymm30 # AVX512F -+ vpscatterqd ZMMWORD PTR [r14+zmm31*8-123]{k1}, ymm30 # AVX512F -+ vpscatterqd ZMMWORD PTR [r9+zmm31+256]{k1}, ymm30 # AVX512F -+ vpscatterqd ZMMWORD PTR [rcx+zmm31*4+1024]{k1}, ymm30 # AVX512F ++ vpscatterqd YMMWORD PTR [r14+zmm31*8-123]{k1}, ymm30 # AVX512F ++ vpscatterqd YMMWORD PTR [r14+zmm31*8-123]{k1}, ymm30 # AVX512F ++ vpscatterqd YMMWORD PTR [r9+zmm31+256]{k1}, ymm30 # AVX512F ++ vpscatterqd YMMWORD PTR [rcx+zmm31*4+1024]{k1}, ymm30 # AVX512F + + vpscatterqq ZMMWORD PTR [r14+zmm31*8-123]{k1}, zmm30 # AVX512F + vpscatterqq ZMMWORD PTR [r14+zmm31*8-123]{k1}, zmm30 # AVX512F @@ -1410932,10 +1418745,10 @@ index 0000000..856153b + vscatterqpd ZMMWORD PTR [r9+zmm31+256]{k1}, zmm30 # AVX512F + vscatterqpd ZMMWORD PTR [rcx+zmm31*4+1024]{k1}, zmm30 # AVX512F + -+ vscatterqps ZMMWORD PTR [r14+zmm31*8-123]{k1}, ymm30 # AVX512F -+ vscatterqps ZMMWORD PTR [r14+zmm31*8-123]{k1}, ymm30 # AVX512F -+ vscatterqps ZMMWORD PTR [r9+zmm31+256]{k1}, ymm30 # AVX512F -+ vscatterqps ZMMWORD PTR [rcx+zmm31*4+1024]{k1}, ymm30 # AVX512F ++ vscatterqps YMMWORD PTR [r14+zmm31*8-123]{k1}, ymm30 # AVX512F ++ vscatterqps YMMWORD PTR [r14+zmm31*8-123]{k1}, ymm30 # AVX512F ++ vscatterqps YMMWORD PTR [r9+zmm31+256]{k1}, ymm30 # AVX512F ++ vscatterqps YMMWORD PTR [rcx+zmm31*4+1024]{k1}, ymm30 # AVX512F + + vshufpd zmm30, zmm29, zmm28, 0xab # AVX512F + vshufpd zmm30{k7}, zmm29, zmm28, 0xab # AVX512F @@ -1412427,12 +1420240,39 @@ index 0000000..856153b + vpermi2pd zmm30, zmm29, [rdx-1024]{1to8} # AVX512F Disp8 + vpermi2pd zmm30, zmm29, [rdx-1032]{1to8} # AVX512F + ++ vptestnmd k5, zmm29, zmm28 # AVX512CD ++ vptestnmd k5{k7}, zmm29, zmm28 # AVX512CD ++ vptestnmd k5, zmm29, ZMMWORD PTR [rcx] # AVX512CD ++ vptestnmd k5, zmm29, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512CD ++ vptestnmd k5, zmm29, [rcx]{1to16} # AVX512CD ++ vptestnmd k5, zmm29, ZMMWORD PTR [rdx+8128] # AVX512CD Disp8 ++ vptestnmd k5, zmm29, ZMMWORD PTR [rdx+8192] # AVX512CD ++ vptestnmd k5, zmm29, ZMMWORD PTR [rdx-8192] # AVX512CD Disp8 ++ vptestnmd k5, zmm29, ZMMWORD PTR [rdx-8256] # AVX512CD ++ vptestnmd k5, zmm29, [rdx+508]{1to16} # AVX512CD Disp8 ++ vptestnmd k5, zmm29, [rdx+512]{1to16} # AVX512CD ++ vptestnmd k5, zmm29, [rdx-512]{1to16} # AVX512CD Disp8 ++ vptestnmd k5, zmm29, [rdx-516]{1to16} # AVX512CD ++ ++ vptestnmq k5, zmm29, zmm28 # AVX512CD ++ vptestnmq k5{k7}, zmm29, zmm28 # AVX512CD ++ vptestnmq k5, zmm29, ZMMWORD PTR [rcx] # AVX512CD ++ vptestnmq k5, zmm29, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512CD ++ vptestnmq k5, zmm29, [rcx]{1to8} # AVX512CD ++ vptestnmq k5, zmm29, ZMMWORD PTR [rdx+8128] # AVX512CD Disp8 ++ vptestnmq k5, zmm29, ZMMWORD PTR [rdx+8192] # AVX512CD ++ vptestnmq k5, zmm29, ZMMWORD PTR [rdx-8192] # AVX512CD Disp8 ++ vptestnmq k5, zmm29, ZMMWORD PTR [rdx-8256] # AVX512CD ++ vptestnmq k5, zmm29, [rdx+1016]{1to8} # AVX512CD Disp8 ++ vptestnmq k5, zmm29, [rdx+1024]{1to8} # AVX512CD ++ vptestnmq k5, zmm29, [rdx-1024]{1to8} # AVX512CD Disp8 ++ vptestnmq k5, zmm29, [rdx-1032]{1to8} # AVX512CD diff --git a/gas/testsuite/gas/i386/x86-64-avx512pf-intel.d b/gas/testsuite/gas/i386/x86-64-avx512pf-intel.d new file mode 100644 -index 0000000..c0090ce +index 0000000..4c8b549 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx512pf-intel.d -@@ -0,0 +1,144 @@ +@@ -0,0 +1,140 @@ +#as: +#objdump: -dwMintel +#name: x86_64 AVX512PF insns (Intel disassembly) @@ -1412456,10 +1420296,10 @@ index 0000000..c0090ce +[ ]*[a-f0-9]+: 62 92 fd 41 c7 8c fe 7b 00 00 00 vgatherpf0qpd ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c7 4c 39 20 vgatherpf0qpd ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\} +[ ]*[a-f0-9]+: 62 b2 fd 41 c7 8c b9 00 04 00 00 vgatherpf0qpd ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\} -+[ ]*[a-f0-9]+: 62 92 7d 41 c7 8c fe 7b 00 00 00 vgatherpf0qps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 92 7d 41 c7 8c fe 7b 00 00 00 vgatherpf0qps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 92 7d 41 c7 4c 39 40 vgatherpf0qps ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\} -+[ ]*[a-f0-9]+: 62 b2 7d 41 c7 8c b9 00 04 00 00 vgatherpf0qps ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\} ++[ ]*[a-f0-9]+: 62 92 7d 41 c7 8c fe 7b 00 00 00 vgatherpf0qps YMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 92 7d 41 c7 8c fe 7b 00 00 00 vgatherpf0qps YMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 92 7d 41 c7 4c 39 40 vgatherpf0qps YMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\} ++[ ]*[a-f0-9]+: 62 b2 7d 41 c7 8c b9 00 04 00 00 vgatherpf0qps YMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c6 94 fe 7b 00 00 00 vgatherpf1dpd ZMMWORD PTR \[r14\+ymm31\*8\+0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c6 94 fe 7b 00 00 00 vgatherpf1dpd ZMMWORD PTR \[r14\+ymm31\*8\+0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c6 54 39 20 vgatherpf1dpd ZMMWORD PTR \[r9\+ymm31\*1\+0x100\]\{k1\} @@ -1412472,10 +1420312,10 @@ index 0000000..c0090ce +[ ]*[a-f0-9]+: 62 92 fd 41 c7 94 fe 7b 00 00 00 vgatherpf1qpd ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c7 54 39 20 vgatherpf1qpd ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\} +[ ]*[a-f0-9]+: 62 b2 fd 41 c7 94 b9 00 04 00 00 vgatherpf1qpd ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\} -+[ ]*[a-f0-9]+: 62 92 7d 41 c7 94 fe 7b 00 00 00 vgatherpf1qps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 92 7d 41 c7 94 fe 7b 00 00 00 vgatherpf1qps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 92 7d 41 c7 54 39 40 vgatherpf1qps ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\} -+[ ]*[a-f0-9]+: 62 b2 7d 41 c7 94 b9 00 04 00 00 vgatherpf1qps ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\} ++[ ]*[a-f0-9]+: 62 92 7d 41 c7 94 fe 7b 00 00 00 vgatherpf1qps YMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 92 7d 41 c7 94 fe 7b 00 00 00 vgatherpf1qps YMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 92 7d 41 c7 54 39 40 vgatherpf1qps YMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\} ++[ ]*[a-f0-9]+: 62 b2 7d 41 c7 94 b9 00 04 00 00 vgatherpf1qps YMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c6 ac fe 7b 00 00 00 vscatterpf0dpd ZMMWORD PTR \[r14\+ymm31\*8\+0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c6 ac fe 7b 00 00 00 vscatterpf0dpd ZMMWORD PTR \[r14\+ymm31\*8\+0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c6 6c 39 20 vscatterpf0dpd ZMMWORD PTR \[r9\+ymm31\*1\+0x100\]\{k1\} @@ -1412488,10 +1420328,10 @@ index 0000000..c0090ce +[ ]*[a-f0-9]+: 62 92 fd 41 c7 ac fe 7b 00 00 00 vscatterpf0qpd ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c7 6c 39 20 vscatterpf0qpd ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\} +[ ]*[a-f0-9]+: 62 b2 fd 41 c7 ac b9 00 04 00 00 vscatterpf0qpd ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\} -+[ ]*[a-f0-9]+: 62 92 7d 41 c7 ac fe 7b 00 00 00 vscatterpf0qps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 92 7d 41 c7 ac fe 7b 00 00 00 vscatterpf0qps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 92 7d 41 c7 6c 39 40 vscatterpf0qps ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\} -+[ ]*[a-f0-9]+: 62 b2 7d 41 c7 ac b9 00 04 00 00 vscatterpf0qps ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\} ++[ ]*[a-f0-9]+: 62 92 7d 41 c7 ac fe 7b 00 00 00 vscatterpf0qps YMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 92 7d 41 c7 ac fe 7b 00 00 00 vscatterpf0qps YMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 92 7d 41 c7 6c 39 40 vscatterpf0qps YMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\} ++[ ]*[a-f0-9]+: 62 b2 7d 41 c7 ac b9 00 04 00 00 vscatterpf0qps YMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c6 b4 fe 7b 00 00 00 vscatterpf1dpd ZMMWORD PTR \[r14\+ymm31\*8\+0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c6 b4 fe 7b 00 00 00 vscatterpf1dpd ZMMWORD PTR \[r14\+ymm31\*8\+0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c6 74 39 20 vscatterpf1dpd ZMMWORD PTR \[r9\+ymm31\*1\+0x100\]\{k1\} @@ -1412504,12 +1420344,10 @@ index 0000000..c0090ce +[ ]*[a-f0-9]+: 62 92 fd 41 c7 b4 fe 7b 00 00 00 vscatterpf1qpd ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c7 74 39 20 vscatterpf1qpd ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\} +[ ]*[a-f0-9]+: 62 b2 fd 41 c7 b4 b9 00 04 00 00 vscatterpf1qpd ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\} -+[ ]*[a-f0-9]+: 62 92 7d 41 c7 b4 fe 7b 00 00 00 vscatterpf1qps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 92 7d 41 c7 b4 fe 7b 00 00 00 vscatterpf1qps ZMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 92 7d 41 c7 74 39 40 vscatterpf1qps ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\} -+[ ]*[a-f0-9]+: 62 b2 7d 41 c7 b4 b9 00 04 00 00 vscatterpf1qps ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\} -+[ ]*[a-f0-9]+: 0f 0d 11 prefetchwt1 BYTE PTR \[rcx\] -+[ ]*[a-f0-9]+: 42 0f 0d 94 f0 23 01 00 00 prefetchwt1 BYTE PTR \[rax\+r14\*8\+0x123\] ++[ ]*[a-f0-9]+: 62 92 7d 41 c7 b4 fe 7b 00 00 00 vscatterpf1qps YMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 92 7d 41 c7 b4 fe 7b 00 00 00 vscatterpf1qps YMMWORD PTR \[r14\+zmm31\*8\+0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 92 7d 41 c7 74 39 40 vscatterpf1qps YMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\} ++[ ]*[a-f0-9]+: 62 b2 7d 41 c7 b4 b9 00 04 00 00 vscatterpf1qps YMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c6 8c fe 85 ff ff ff vgatherpf0dpd ZMMWORD PTR \[r14\+ymm31\*8-0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c6 8c fe 85 ff ff ff vgatherpf0dpd ZMMWORD PTR \[r14\+ymm31\*8-0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c6 4c 39 20 vgatherpf0dpd ZMMWORD PTR \[r9\+ymm31\*1\+0x100\]\{k1\} @@ -1412522,10 +1420360,10 @@ index 0000000..c0090ce +[ ]*[a-f0-9]+: 62 92 fd 41 c7 8c fe 85 ff ff ff vgatherpf0qpd ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c7 4c 39 20 vgatherpf0qpd ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\} +[ ]*[a-f0-9]+: 62 b2 fd 41 c7 8c b9 00 04 00 00 vgatherpf0qpd ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\} -+[ ]*[a-f0-9]+: 62 92 7d 41 c7 8c fe 85 ff ff ff vgatherpf0qps ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 92 7d 41 c7 8c fe 85 ff ff ff vgatherpf0qps ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 92 7d 41 c7 4c 39 40 vgatherpf0qps ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\} -+[ ]*[a-f0-9]+: 62 b2 7d 41 c7 8c b9 00 04 00 00 vgatherpf0qps ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\} ++[ ]*[a-f0-9]+: 62 92 7d 41 c7 8c fe 85 ff ff ff vgatherpf0qps YMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 92 7d 41 c7 8c fe 85 ff ff ff vgatherpf0qps YMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 92 7d 41 c7 4c 39 40 vgatherpf0qps YMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\} ++[ ]*[a-f0-9]+: 62 b2 7d 41 c7 8c b9 00 04 00 00 vgatherpf0qps YMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c6 94 fe 85 ff ff ff vgatherpf1dpd ZMMWORD PTR \[r14\+ymm31\*8-0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c6 94 fe 85 ff ff ff vgatherpf1dpd ZMMWORD PTR \[r14\+ymm31\*8-0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c6 54 39 20 vgatherpf1dpd ZMMWORD PTR \[r9\+ymm31\*1\+0x100\]\{k1\} @@ -1412538,10 +1420376,10 @@ index 0000000..c0090ce +[ ]*[a-f0-9]+: 62 92 fd 41 c7 94 fe 85 ff ff ff vgatherpf1qpd ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c7 54 39 20 vgatherpf1qpd ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\} +[ ]*[a-f0-9]+: 62 b2 fd 41 c7 94 b9 00 04 00 00 vgatherpf1qpd ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\} -+[ ]*[a-f0-9]+: 62 92 7d 41 c7 94 fe 85 ff ff ff vgatherpf1qps ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 92 7d 41 c7 94 fe 85 ff ff ff vgatherpf1qps ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 92 7d 41 c7 54 39 40 vgatherpf1qps ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\} -+[ ]*[a-f0-9]+: 62 b2 7d 41 c7 94 b9 00 04 00 00 vgatherpf1qps ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\} ++[ ]*[a-f0-9]+: 62 92 7d 41 c7 94 fe 85 ff ff ff vgatherpf1qps YMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 92 7d 41 c7 94 fe 85 ff ff ff vgatherpf1qps YMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 92 7d 41 c7 54 39 40 vgatherpf1qps YMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\} ++[ ]*[a-f0-9]+: 62 b2 7d 41 c7 94 b9 00 04 00 00 vgatherpf1qps YMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c6 ac fe 85 ff ff ff vscatterpf0dpd ZMMWORD PTR \[r14\+ymm31\*8-0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c6 ac fe 85 ff ff ff vscatterpf0dpd ZMMWORD PTR \[r14\+ymm31\*8-0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c6 6c 39 20 vscatterpf0dpd ZMMWORD PTR \[r9\+ymm31\*1\+0x100\]\{k1\} @@ -1412554,10 +1420392,10 @@ index 0000000..c0090ce +[ ]*[a-f0-9]+: 62 92 fd 41 c7 ac fe 85 ff ff ff vscatterpf0qpd ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c7 6c 39 20 vscatterpf0qpd ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\} +[ ]*[a-f0-9]+: 62 b2 fd 41 c7 ac b9 00 04 00 00 vscatterpf0qpd ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\} -+[ ]*[a-f0-9]+: 62 92 7d 41 c7 ac fe 85 ff ff ff vscatterpf0qps ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 92 7d 41 c7 ac fe 85 ff ff ff vscatterpf0qps ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 92 7d 41 c7 6c 39 40 vscatterpf0qps ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\} -+[ ]*[a-f0-9]+: 62 b2 7d 41 c7 ac b9 00 04 00 00 vscatterpf0qps ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\} ++[ ]*[a-f0-9]+: 62 92 7d 41 c7 ac fe 85 ff ff ff vscatterpf0qps YMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 92 7d 41 c7 ac fe 85 ff ff ff vscatterpf0qps YMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 92 7d 41 c7 6c 39 40 vscatterpf0qps YMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\} ++[ ]*[a-f0-9]+: 62 b2 7d 41 c7 ac b9 00 04 00 00 vscatterpf0qps YMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c6 b4 fe 85 ff ff ff vscatterpf1dpd ZMMWORD PTR \[r14\+ymm31\*8-0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c6 b4 fe 85 ff ff ff vscatterpf1dpd ZMMWORD PTR \[r14\+ymm31\*8-0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c6 74 39 20 vscatterpf1dpd ZMMWORD PTR \[r9\+ymm31\*1\+0x100\]\{k1\} @@ -1412570,19 +1420408,17 @@ index 0000000..c0090ce +[ ]*[a-f0-9]+: 62 92 fd 41 c7 b4 fe 85 ff ff ff vscatterpf1qpd ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c7 74 39 20 vscatterpf1qpd ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\} +[ ]*[a-f0-9]+: 62 b2 fd 41 c7 b4 b9 00 04 00 00 vscatterpf1qpd ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\} -+[ ]*[a-f0-9]+: 62 92 7d 41 c7 b4 fe 85 ff ff ff vscatterpf1qps ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 92 7d 41 c7 b4 fe 85 ff ff ff vscatterpf1qps ZMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\} -+[ ]*[a-f0-9]+: 62 92 7d 41 c7 74 39 40 vscatterpf1qps ZMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\} -+[ ]*[a-f0-9]+: 62 b2 7d 41 c7 b4 b9 00 04 00 00 vscatterpf1qps ZMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\} -+[ ]*[a-f0-9]+: 0f 0d 11 prefetchwt1 BYTE PTR \[rcx\] -+[ ]*[a-f0-9]+: 42 0f 0d 94 f0 34 12 00 00 prefetchwt1 BYTE PTR \[rax\+r14\*8\+0x1234\] ++[ ]*[a-f0-9]+: 62 92 7d 41 c7 b4 fe 85 ff ff ff vscatterpf1qps YMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 92 7d 41 c7 b4 fe 85 ff ff ff vscatterpf1qps YMMWORD PTR \[r14\+zmm31\*8-0x7b\]\{k1\} ++[ ]*[a-f0-9]+: 62 92 7d 41 c7 74 39 40 vscatterpf1qps YMMWORD PTR \[r9\+zmm31\*1\+0x100\]\{k1\} ++[ ]*[a-f0-9]+: 62 b2 7d 41 c7 b4 b9 00 04 00 00 vscatterpf1qps YMMWORD PTR \[rcx\+zmm31\*4\+0x400\]\{k1\} +#pass diff --git a/gas/testsuite/gas/i386/x86-64-avx512pf.d b/gas/testsuite/gas/i386/x86-64-avx512pf.d new file mode 100644 -index 0000000..28c7669 +index 0000000..0e3c0bd --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx512pf.d -@@ -0,0 +1,143 @@ +@@ -0,0 +1,139 @@ +#as: +#objdump: -dw +#name: x86_64 AVX512PF insns @@ -1412657,8 +1420493,6 @@ index 0000000..28c7669 +[ ]*[a-f0-9]+: 62 92 7d 41 c7 b4 fe 7b 00 00 00 vscatterpf1qps 0x7b\(%r14,%zmm31,8\)\{%k1\} +[ ]*[a-f0-9]+: 62 92 7d 41 c7 74 39 40 vscatterpf1qps 0x100\(%r9,%zmm31,1\)\{%k1\} +[ ]*[a-f0-9]+: 62 b2 7d 41 c7 b4 b9 00 04 00 00 vscatterpf1qps 0x400\(%rcx,%zmm31,4\)\{%k1\} -+[ ]*[a-f0-9]+: 0f 0d 11 prefetchwt1 \(%rcx\) -+[ ]*[a-f0-9]+: 42 0f 0d 94 f0 23 01 00 00 prefetchwt1 0x123\(%rax,%r14,8\) +[ ]*[a-f0-9]+: 62 92 fd 41 c6 8c fe 85 ff ff ff vgatherpf0dpd -0x7b\(%r14,%ymm31,8\)\{%k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c6 8c fe 85 ff ff ff vgatherpf0dpd -0x7b\(%r14,%ymm31,8\)\{%k1\} +[ ]*[a-f0-9]+: 62 92 fd 41 c6 4c 39 20 vgatherpf0dpd 0x100\(%r9,%ymm31,1\)\{%k1\} @@ -1412723,15 +1420557,13 @@ index 0000000..28c7669 +[ ]*[a-f0-9]+: 62 92 7d 41 c7 b4 fe 85 ff ff ff vscatterpf1qps -0x7b\(%r14,%zmm31,8\)\{%k1\} +[ ]*[a-f0-9]+: 62 92 7d 41 c7 74 39 40 vscatterpf1qps 0x100\(%r9,%zmm31,1\)\{%k1\} +[ ]*[a-f0-9]+: 62 b2 7d 41 c7 b4 b9 00 04 00 00 vscatterpf1qps 0x400\(%rcx,%zmm31,4\)\{%k1\} -+[ ]*[a-f0-9]+: 0f 0d 11 prefetchwt1 \(%rcx\) -+[ ]*[a-f0-9]+: 42 0f 0d 94 f0 34 12 00 00 prefetchwt1 0x1234\(%rax,%r14,8\) +#pass diff --git a/gas/testsuite/gas/i386/x86-64-avx512pf.s b/gas/testsuite/gas/i386/x86-64-avx512pf.s new file mode 100644 -index 0000000..b2bece4 +index 0000000..bceae73 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-avx512pf.s -@@ -0,0 +1,173 @@ +@@ -0,0 +1,167 @@ +# Check 64bit AVX512PF instructions + + .allow_index_reg @@ -1412818,9 +1420650,6 @@ index 0000000..b2bece4 + vscatterpf1qps 256(%r9,%zmm31){%k1} # AVX512PF + vscatterpf1qps 1024(%rcx,%zmm31,4){%k1} # AVX512PF + -+ prefetchwt1 (%rcx) # AVX512PF -+ prefetchwt1 0x123(%rax,%r14,8) # AVX512PF -+ + .intel_syntax noprefix + vgatherpf0dpd ZMMWORD PTR [r14+ymm31*8-123]{k1} # AVX512PF + vgatherpf0dpd ZMMWORD PTR [r14+ymm31*8-123]{k1} # AVX512PF @@ -1412837,10 +1420666,10 @@ index 0000000..b2bece4 + vgatherpf0qpd ZMMWORD PTR [r9+zmm31+256]{k1} # AVX512PF + vgatherpf0qpd ZMMWORD PTR [rcx+zmm31*4+1024]{k1} # AVX512PF + -+ vgatherpf0qps ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF -+ vgatherpf0qps ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF -+ vgatherpf0qps ZMMWORD PTR [r9+zmm31+256]{k1} # AVX512PF -+ vgatherpf0qps ZMMWORD PTR [rcx+zmm31*4+1024]{k1} # AVX512PF ++ vgatherpf0qps YMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF ++ vgatherpf0qps YMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF ++ vgatherpf0qps YMMWORD PTR [r9+zmm31+256]{k1} # AVX512PF ++ vgatherpf0qps YMMWORD PTR [rcx+zmm31*4+1024]{k1} # AVX512PF + + vgatherpf1dpd ZMMWORD PTR [r14+ymm31*8-123]{k1} # AVX512PF + vgatherpf1dpd ZMMWORD PTR [r14+ymm31*8-123]{k1} # AVX512PF @@ -1412857,10 +1420686,10 @@ index 0000000..b2bece4 + vgatherpf1qpd ZMMWORD PTR [r9+zmm31+256]{k1} # AVX512PF + vgatherpf1qpd ZMMWORD PTR [rcx+zmm31*4+1024]{k1} # AVX512PF + -+ vgatherpf1qps ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF -+ vgatherpf1qps ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF -+ vgatherpf1qps ZMMWORD PTR [r9+zmm31+256]{k1} # AVX512PF -+ vgatherpf1qps ZMMWORD PTR [rcx+zmm31*4+1024]{k1} # AVX512PF ++ vgatherpf1qps YMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF ++ vgatherpf1qps YMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF ++ vgatherpf1qps YMMWORD PTR [r9+zmm31+256]{k1} # AVX512PF ++ vgatherpf1qps YMMWORD PTR [rcx+zmm31*4+1024]{k1} # AVX512PF + + vscatterpf0dpd ZMMWORD PTR [r14+ymm31*8-123]{k1} # AVX512PF + vscatterpf0dpd ZMMWORD PTR [r14+ymm31*8-123]{k1} # AVX512PF @@ -1412877,10 +1420706,10 @@ index 0000000..b2bece4 + vscatterpf0qpd ZMMWORD PTR [r9+zmm31+256]{k1} # AVX512PF + vscatterpf0qpd ZMMWORD PTR [rcx+zmm31*4+1024]{k1} # AVX512PF + -+ vscatterpf0qps ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF -+ vscatterpf0qps ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF -+ vscatterpf0qps ZMMWORD PTR [r9+zmm31+256]{k1} # AVX512PF -+ vscatterpf0qps ZMMWORD PTR [rcx+zmm31*4+1024]{k1} # AVX512PF ++ vscatterpf0qps YMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF ++ vscatterpf0qps YMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF ++ vscatterpf0qps YMMWORD PTR [r9+zmm31+256]{k1} # AVX512PF ++ vscatterpf0qps YMMWORD PTR [rcx+zmm31*4+1024]{k1} # AVX512PF + + vscatterpf1dpd ZMMWORD PTR [r14+ymm31*8-123]{k1} # AVX512PF + vscatterpf1dpd ZMMWORD PTR [r14+ymm31*8-123]{k1} # AVX512PF @@ -1412897,13 +1420726,10 @@ index 0000000..b2bece4 + vscatterpf1qpd ZMMWORD PTR [r9+zmm31+256]{k1} # AVX512PF + vscatterpf1qpd ZMMWORD PTR [rcx+zmm31*4+1024]{k1} # AVX512PF + -+ vscatterpf1qps ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF -+ vscatterpf1qps ZMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF -+ vscatterpf1qps ZMMWORD PTR [r9+zmm31+256]{k1} # AVX512PF -+ vscatterpf1qps ZMMWORD PTR [rcx+zmm31*4+1024]{k1} # AVX512PF -+ -+ prefetchwt1 BYTE PTR [rcx] # AVX512PF -+ prefetchwt1 BYTE PTR [rax+r14*8+0x1234] # AVX512PF ++ vscatterpf1qps YMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF ++ vscatterpf1qps YMMWORD PTR [r14+zmm31*8-123]{k1} # AVX512PF ++ vscatterpf1qps YMMWORD PTR [r9+zmm31+256]{k1} # AVX512PF ++ vscatterpf1qps YMMWORD PTR [rcx+zmm31*4+1024]{k1} # AVX512PF + diff --git a/gas/testsuite/gas/i386/x86-64-bmi-intel.d b/gas/testsuite/gas/i386/x86-64-bmi-intel.d new file mode 100644 @@ -1416337,7 +1424163,7 @@ index 0000000..8272f04 + hlt diff --git a/gas/testsuite/gas/i386/x86-64-cbw-intel.d b/gas/testsuite/gas/i386/x86-64-cbw-intel.d new file mode 100644 -index 0000000..42ab039 +index 0000000..df4173a --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-cbw-intel.d @@ -0,0 +1,24 @@ @@ -1416355,7 +1424181,7 @@ index 0000000..42ab039 + 3: 48 98 cdqe + 5: 66 40 98 rex cbw + 8: 40 98 rex cwde -+ a: 66 48 98 data32 cdqe ++ a: 66 48 98 data16 cdqe + +0+00d <_cwd>: + d: 66 99 cwd @@ -1416363,11 +1424189,11 @@ index 0000000..42ab039 + 10: 48 99 cqo + 12: 66 40 99 rex cwd + 15: 40 99 rex cdq -+ 17: 66 48 99 data32 cqo ++ 17: 66 48 99 data16 cqo +#pass diff --git a/gas/testsuite/gas/i386/x86-64-cbw.d b/gas/testsuite/gas/i386/x86-64-cbw.d new file mode 100644 -index 0000000..6b730d0 +index 0000000..859ef9b --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-cbw.d @@ -0,0 +1,23 @@ @@ -1416384,7 +1424210,7 @@ index 0000000..6b730d0 + 3: 48 98 cltq + 5: 66 40 98 rex cbtw + 8: 40 98 rex cwtl -+ a: 66 48 98 data32 cltq ++ a: 66 48 98 data16 cltq + +0+00d <_cwd>: + d: 66 99 cwtd @@ -1416392,7 +1424218,7 @@ index 0000000..6b730d0 + 10: 48 99 cqto + 12: 66 40 99 rex cwtd + 15: 40 99 rex cltd -+ 17: 66 48 99 data32 cqto ++ 17: 66 48 99 data16 cqto +#pass diff --git a/gas/testsuite/gas/i386/x86-64-cbw.s b/gas/testsuite/gas/i386/x86-64-cbw.s new file mode 100644 @@ -1416418,6 +1424244,68 @@ index 0000000..085c279 + rex64 cwd + + .p2align 4,0 +diff --git a/gas/testsuite/gas/i386/x86-64-clflushopt-intel.d b/gas/testsuite/gas/i386/x86-64-clflushopt-intel.d +new file mode 100644 +index 0000000..6ab5e2c +--- /dev/null ++++ b/gas/testsuite/gas/i386/x86-64-clflushopt-intel.d +@@ -0,0 +1,16 @@ ++#as: ++#objdump: -dw -Mintel ++#name: x86_64 CLFLUSHOPT insns (Intel disassembly) ++#source: x86-64-clflushopt.s ++ ++.*: +file format .* ++ ++ ++Disassembly of section \.text: ++ ++0+ <_start>: ++[ ]*[a-f0-9]+:[ ]*66 0f ae 39[ ]*clflushopt BYTE PTR \[rcx\] ++[ ]*[a-f0-9]+:[ ]*66 42 0f ae bc f0 23 01 00 00[ ]*clflushopt BYTE PTR \[rax\+r14\*8\+0x123\] ++[ ]*[a-f0-9]+:[ ]*66 0f ae 39[ ]*clflushopt BYTE PTR \[rcx\] ++[ ]*[a-f0-9]+:[ ]*66 42 0f ae bc f0 34 12 00 00[ ]*clflushopt BYTE PTR \[rax\+r14\*8\+0x1234\] ++#pass +diff --git a/gas/testsuite/gas/i386/x86-64-clflushopt.d b/gas/testsuite/gas/i386/x86-64-clflushopt.d +new file mode 100644 +index 0000000..3c400a8 +--- /dev/null ++++ b/gas/testsuite/gas/i386/x86-64-clflushopt.d +@@ -0,0 +1,16 @@ ++#as: ++#objdump: -dw ++#name: x86_64 CLFLUSHOPT insns ++#source: x86-64-clflushopt.s ++ ++.*: +file format .* ++ ++ ++Disassembly of section \.text: ++ ++0+ <_start>: ++[ ]*[a-f0-9]+:[ ]*66 0f ae 39[ ]*clflushopt \(%rcx\) ++[ ]*[a-f0-9]+:[ ]*66 42 0f ae bc f0 23 01 00 00[ ]*clflushopt 0x123\(%rax,%r14,8\) ++[ ]*[a-f0-9]+:[ ]*66 0f ae 39[ ]*clflushopt \(%rcx\) ++[ ]*[a-f0-9]+:[ ]*66 42 0f ae bc f0 34 12 00 00[ ]*clflushopt 0x1234\(%rax,%r14,8\) ++#pass +diff --git a/gas/testsuite/gas/i386/x86-64-clflushopt.s b/gas/testsuite/gas/i386/x86-64-clflushopt.s +new file mode 100644 +index 0000000..3e64d06 +--- /dev/null ++++ b/gas/testsuite/gas/i386/x86-64-clflushopt.s +@@ -0,0 +1,12 @@ ++# Check 64bit CLFLUSHOPT instructions ++ ++ .allow_index_reg ++ .text ++_start: ++ ++ clflushopt (%rcx) # CLFLUSHOPT ++ clflushopt 0x123(%rax,%r14,8) # CLFLUSHOPT ++ ++ .intel_syntax noprefix ++ clflushopt BYTE PTR [rcx] # CLFLUSHOPT ++ clflushopt BYTE PTR [rax+r14*8+0x1234] # CLFLUSHOPT diff --git a/gas/testsuite/gas/i386/x86-64-clmul-intel.d b/gas/testsuite/gas/i386/x86-64-clmul-intel.d new file mode 100644 index 0000000..908904f @@ -1444923,89 +1452811,109 @@ index 0000000..d641d51 + vcvttpd2dq xmm2,[rcx] diff --git a/gas/testsuite/gas/i386/x86-64-inval-avx512f.l b/gas/testsuite/gas/i386/x86-64-inval-avx512f.l new file mode 100644 -index 0000000..436acb0 +index 0000000..21c4906 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-inval-avx512f.l -@@ -0,0 +1,71 @@ +@@ -0,0 +1,90 @@ +.*: Assembler messages: -+.*:4: Error: .* +.*:5: Error: .* +.*:6: Error: .* +.*:7: Error: .* +.*:8: Error: .* +.*:9: Error: .* -+.*:11: Error: .* ++.*:10: Error: .* +.*:12: Error: .* -+.*:14: Error: .* ++.*:13: Error: .* +.*:15: Error: .* ++.*:16: Error: .* +.*:18: Error: .* +.*:19: Error: .* +.*:20: Error: .* +.*:21: Error: .* -+.*:21: Error: .* -+.*:22: Error: .* -+.*:22: Error: .* -+.*:23: Error: .* -+.*:23: Error: .* ++.*:24: Error: .* +.*:25: Error: .* +.*:26: Error: .* ++.*:27: Error: .* ++.*:27: Error: .* +.*:28: Error: .* ++.*:28: Error: .* ++.*:29: Error: .* +.*:29: Error: .* +.*:31: Error: .* +.*:32: Error: .* -+.*:33: Error: .* +.*:34: Error: .* +.*:35: Error: .* -+.*:36: Error: .* +.*:37: Error: .* ++.*:38: Error: .* ++.*:39: Error: .* ++.*:40: Error: .* ++.*:42: Error: .* ++.*:43: Error: .* ++.*:44: Error: .* ++.*:45: Error: .* ++.*:46: Error: .* ++.*:47: Error: .* ++.*:48: Error: .* +GAS LISTING .* + + +[ ]*1[ ]+# Check illegal AVX512F instructions +[ ]*2[ ]+\.text -+[ ]*3[ ]+_start: -+[ ]*4[ ]+mov \{sae\}, %rax\{%k1\} -+[ ]*5[ ]+mov \{sae\}, %rax -+[ ]*6[ ]+mov %rbx, %rax\{%k2\} -+[ ]*7[ ]+vaddps %zmm3, %zmm1, %zmm2\{z\}\{%k1\}\{z\} -+[ ]*8[ ]+vaddps %zmm3, %zmm1\{%k3\}, %zmm2\{z\} -+[ ]*9[ ]+vaddps %zmm3, %zmm1\{%k1\}, %zmm2\{%k2\} -+[ ]*10[ ]+ -+[ ]*11[ ]+vcvtps2pd \(%rax\), %zmm1\{1to8\} -+[ ]*12[ ]+vcvtps2pd \(%rax\)\{1to16\}, %zmm1 -+[ ]*13[ ]+ -+[ ]*14[ ]+vcvtps2pd \(%rax\)\{%k1\}, %zmm1 -+[ ]*15[ ]+vcvtps2pd \(%rax\)\{z\}, %zmm1 -+[ ]*16[ ]+ -+[ ]*17[ ]+\.intel_syntax noprefix -+[ ]*18[ ]+mov rax\{k1\}, \{sae\} -+[ ]*19[ ]+mov rax, \{sae\} -+[ ]*20[ ]+mov rax\{k2\}, rbx -+[ ]*21[ ]+vaddps zmm2\{z\}\{k1\}\{z\}, zmm1, zmm3 -+[ ]*22[ ]+vaddps zmm2\{z\}, zmm1\{k3\}, zmm3 -+[ ]*23[ ]+vaddps zmm2\{k2\}, zmm1\{k1\}, zmm3 -+[ ]*24[ ]+ -+[ ]*25[ ]+vcvtps2pd zmm1\{1to8\}, \[rax\] -+[ ]*26[ ]+vcvtps2pd zmm1, \[rax\]\{1to16\} -+[ ]*27[ ]+ -+[ ]*28[ ]+vcvtps2pd zmm1, \[rax\]\{k1\} -+[ ]*29[ ]+vcvtps2pd zmm1, \[rax\]\{z\} ++[ ]*3[ ]+\.allow_index_reg ++[ ]*4[ ]+_start: ++[ ]*5[ ]+mov \{sae\}, %rax\{%k1\} ++[ ]*6[ ]+mov \{sae\}, %rax ++[ ]*7[ ]+mov %rbx, %rax\{%k2\} ++[ ]*8[ ]+vaddps %zmm3, %zmm1, %zmm2\{z\}\{%k1\}\{z\} ++[ ]*9[ ]+vaddps %zmm3, %zmm1\{%k3\}, %zmm2\{z\} ++[ ]*10[ ]+vaddps %zmm3, %zmm1\{%k1\}, %zmm2\{%k2\} ++[ ]*11[ ]+ ++[ ]*12[ ]+vcvtps2pd \(%rax\), %zmm1\{1to8\} ++[ ]*13[ ]+vcvtps2pd \(%rax\)\{1to16\}, %zmm1 ++[ ]*14[ ]+ ++[ ]*15[ ]+vcvtps2pd \(%rax\)\{%k1\}, %zmm1 ++[ ]*16[ ]+vcvtps2pd \(%rax\)\{z\}, %zmm1 ++[ ]*17[ ]+ ++[ ]*18[ ]+vgatherqpd \(%rdi\),%zmm6\{%k1\} ++[ ]*19[ ]+vgatherqpd \(%zmm2\),%zmm6\{%k1\} ++[ ]*20[ ]+vpscatterdd %zmm6,\(%rdi\)\{%k1\} ++[ ]*21[ ]+vpscatterdd %zmm6,\(%zmm2\)\{%k1\} ++[ ]*22[ ]+ ++[ ]*23[ ]+\.intel_syntax noprefix ++[ ]*24[ ]+mov rax\{k1\}, \{sae\} ++[ ]*25[ ]+mov rax, \{sae\} ++[ ]*26[ ]+mov rax\{k2\}, rbx ++[ ]*27[ ]+vaddps zmm2\{z\}\{k1\}\{z\}, zmm1, zmm3 ++[ ]*28[ ]+vaddps zmm2\{z\}, zmm1\{k3\}, zmm3 ++[ ]*29[ ]+vaddps zmm2\{k2\}, zmm1\{k1\}, zmm3 +[ ]*30[ ]+ -+[ ]*31[ ]+vaddps zmm2, zmm1, QWORD PTR \[rax\]\{1to8\} -+[ ]*32[ ]+vaddps zmm2, zmm1, QWORD PTR \[rax\]\{1to16\} -+[ ]*33[ ]+vaddpd zmm2, zmm1, DWORD PTR \[rax\]\{1to8\} -+[ ]*34[ ]+vaddpd zmm2, zmm1, DWORD PTR \[rax\]\{1to16\} -+[ ]*35[ ]+vaddps zmm2, zmm1, ZMMWORD PTR \[rax\]\{1to16\} -+[ ]*36[ ]+vaddps zmm2, zmm1, DWORD PTR \[rax\] -+[ ]*37[ ]+vaddpd zmm2, zmm1, QWORD PTR \[rax\] ++[ ]*31[ ]+vcvtps2pd zmm1\{1to8\}, \[rax\] ++[ ]*32[ ]+vcvtps2pd zmm1, \[rax\]\{1to16\} ++[ ]*33[ ]+ ++[ ]*34[ ]+vcvtps2pd zmm1, \[rax\]\{k1\} ++[ ]*35[ ]+vcvtps2pd zmm1, \[rax\]\{z\} ++[ ]*36[ ]+ ++[ ]*37[ ]+vgatherqpd zmm6\{k1\}, ZMMWORD PTR \[rdi\] ++[ ]*38[ ]+vgatherqpd zmm6\{k1\}, ZMMWORD PTR \[zmm2\+riz\] ++[ ]*39[ ]+vpscatterdd ZMMWORD PTR \[rdi\]\{k1\}, zmm6 ++[ ]*40[ ]+vpscatterdd ZMMWORD PTR \[zmm2\+riz\]\{k1\}, zmm6 ++[ ]*41[ ]+ ++[ ]*42[ ]+vaddps zmm2, zmm1, QWORD PTR \[rax\]\{1to8\} ++[ ]*43[ ]+vaddps zmm2, zmm1, QWORD PTR \[rax\]\{1to16\} ++[ ]*44[ ]+vaddpd zmm2, zmm1, DWORD PTR \[rax\]\{1to8\} ++[ ]*45[ ]+vaddpd zmm2, zmm1, DWORD PTR \[rax\]\{1to16\} ++[ ]*46[ ]+vaddps zmm2, zmm1, ZMMWORD PTR \[rax\]\{1to16\} ++[ ]*47[ ]+vaddps zmm2, zmm1, DWORD PTR \[rax\] ++[ ]*48[ ]+vaddpd zmm2, zmm1, QWORD PTR \[rax\] diff --git a/gas/testsuite/gas/i386/x86-64-inval-avx512f.s b/gas/testsuite/gas/i386/x86-64-inval-avx512f.s new file mode 100644 -index 0000000..5ac7349 +index 0000000..835f677 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-inval-avx512f.s -@@ -0,0 +1,37 @@ +@@ -0,0 +1,48 @@ +# Check illegal AVX512F instructions + .text ++ .allow_index_reg +_start: + mov {sae}, %rax{%k1} + mov {sae}, %rax @@ -1445020,6 +1452928,11 @@ index 0000000..5ac7349 + vcvtps2pd (%rax){%k1}, %zmm1 + vcvtps2pd (%rax){z}, %zmm1 + ++ vgatherqpd (%rdi),%zmm6{%k1} ++ vgatherqpd (%zmm2),%zmm6{%k1} ++ vpscatterdd %zmm6,(%rdi){%k1} ++ vpscatterdd %zmm6,(%zmm2){%k1} ++ + .intel_syntax noprefix + mov rax{k1}, {sae} + mov rax, {sae} @@ -1445034,6 +1452947,11 @@ index 0000000..5ac7349 + vcvtps2pd zmm1, [rax]{k1} + vcvtps2pd zmm1, [rax]{z} + ++ vgatherqpd zmm6{k1}, ZMMWORD PTR [rdi] ++ vgatherqpd zmm6{k1}, ZMMWORD PTR [zmm2+riz] ++ vpscatterdd ZMMWORD PTR [rdi]{k1}, zmm6 ++ vpscatterdd ZMMWORD PTR [zmm2+riz]{k1}, zmm6 ++ + vaddps zmm2, zmm1, QWORD PTR [rax]{1to8} + vaddps zmm2, zmm1, QWORD PTR [rax]{1to16} + vaddpd zmm2, zmm1, DWORD PTR [rax]{1to8} @@ -1445818,7 +1453736,7 @@ index 0000000..89dd211 + invpcid rdx,[rax] diff --git a/gas/testsuite/gas/i386/x86-64-io-intel.d b/gas/testsuite/gas/i386/x86-64-io-intel.d new file mode 100644 -index 0000000..ad22c46 +index 0000000..0555a47 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-io-intel.d @@ -0,0 +1,24 @@ @@ -1445832,23 +1453750,23 @@ index 0000000..ad22c46 + +0+000 <_in>: + 0: 48 ed rex.W in eax,dx -+ 2: 66 48 ed data32 rex.W in eax,dx ++ 2: 66 48 ed data16 rex.W in eax,dx + +0+005 <_out>: + 5: 48 ef rex.W out dx,eax -+ 7: 66 48 ef data32 rex.W out dx,eax ++ 7: 66 48 ef data16 rex.W out dx,eax + +0+00a <_ins>: + a: 48 6d rex.W ins DWORD PTR es:\[rdi\],dx -+ c: 66 48 6d data32 rex.W ins DWORD PTR es:\[rdi\],dx ++ c: 66 48 6d data16 rex.W ins DWORD PTR es:\[rdi\],dx + +0+00f <_outs>: + f: 48 6f rex.W outs dx,DWORD PTR ds:\[rsi\] -+ 11: 66 48 6f data32 rex.W outs dx,DWORD PTR ds:\[rsi\] ++ 11: 66 48 6f data16 rex.W outs dx,DWORD PTR ds:\[rsi\] +#pass diff --git a/gas/testsuite/gas/i386/x86-64-io-suffix.d b/gas/testsuite/gas/i386/x86-64-io-suffix.d new file mode 100644 -index 0000000..6b460dc +index 0000000..121a9ba --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-io-suffix.d @@ -0,0 +1,24 @@ @@ -1445862,23 +1453780,23 @@ index 0000000..6b460dc + +0+000 <_in>: + 0: 48 ed rex.W inl \(%dx\),%eax -+ 2: 66 48 ed data32 rex.W inl \(%dx\),%eax ++ 2: 66 48 ed data16 rex.W inl \(%dx\),%eax + +0+005 <_out>: + 5: 48 ef rex.W outl %eax,\(%dx\) -+ 7: 66 48 ef data32 rex.W outl %eax,\(%dx\) ++ 7: 66 48 ef data16 rex.W outl %eax,\(%dx\) + +0+00a <_ins>: + a: 48 6d rex.W insl \(%dx\),%es:\(%rdi\) -+ c: 66 48 6d data32 rex.W insl \(%dx\),%es:\(%rdi\) ++ c: 66 48 6d data16 rex.W insl \(%dx\),%es:\(%rdi\) + +0+00f <_outs>: + f: 48 6f rex.W outsl %ds:\(%rsi\),\(%dx\) -+ 11: 66 48 6f data32 rex.W outsl %ds:\(%rsi\),\(%dx\) ++ 11: 66 48 6f data16 rex.W outsl %ds:\(%rsi\),\(%dx\) +#pass diff --git a/gas/testsuite/gas/i386/x86-64-io.d b/gas/testsuite/gas/i386/x86-64-io.d new file mode 100644 -index 0000000..7310f1a +index 0000000..7056ac0 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-io.d @@ -0,0 +1,23 @@ @@ -1445891,19 +1453809,19 @@ index 0000000..7310f1a + +0+000 <_in>: + 0: 48 ed rex.W in \(%dx\),%eax -+ 2: 66 48 ed data32 rex.W in \(%dx\),%eax ++ 2: 66 48 ed data16 rex.W in \(%dx\),%eax + +0+005 <_out>: + 5: 48 ef rex.W out %eax,\(%dx\) -+ 7: 66 48 ef data32 rex.W out %eax,\(%dx\) ++ 7: 66 48 ef data16 rex.W out %eax,\(%dx\) + +0+00a <_ins>: + a: 48 6d rex.W insl \(%dx\),%es:\(%rdi\) -+ c: 66 48 6d data32 rex.W insl \(%dx\),%es:\(%rdi\) ++ c: 66 48 6d data16 rex.W insl \(%dx\),%es:\(%rdi\) + +0+00f <_outs>: + f: 48 6f rex.W outsl %ds:\(%rsi\),\(%dx\) -+ 11: 66 48 6f data32 rex.W outsl %ds:\(%rsi\),\(%dx\) ++ 11: 66 48 6f data16 rex.W outsl %ds:\(%rsi\),\(%dx\) +#pass diff --git a/gas/testsuite/gas/i386/x86-64-io.s b/gas/testsuite/gas/i386/x86-64-io.s new file mode 100644 @@ -1446440,7 +1454358,7 @@ index 0000000..8b1f9b0 + lock xor eax,DWORD PTR [rbx] diff --git a/gas/testsuite/gas/i386/x86-64-long-1-intel.d b/gas/testsuite/gas/i386/x86-64-long-1-intel.d new file mode 100644 -index 0000000..28b291a +index 0000000..0ced3f0 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-long-1-intel.d @@ -0,0 +1,14 @@ @@ -1446454,13 +1454372,13 @@ index 0000000..28b291a +Disassembly of section .text: + +0+ : -+[ ]*[a-f0-9]+: f2 f0 f0 f0 f2 f2 f2 f2 f2 f2 f0 f0 66 0f 28 repnz lock lock lock repnz repnz repnz repnz repnz repnz lock lock \(bad\) ++[ ]*[a-f0-9]+: f2 f0 f0 f0 f2 f2 f2 f2 f2 f2 f0 f0 f3 0f 10 repnz lock lock lock repnz repnz repnz repnz repnz repnz lock lock \(bad\) +[ ]*[a-f0-9]+: 00 f2 add dl,dh -+[ ]*[a-f0-9]+: f0 f0 f0 f2 f2 f2 f2 f0 f0 f0 f0 66 0f 28 00 lock lock lock repnz repnz repnz repnz lock lock lock lock movapd xmm0,XMMWORD PTR \[rax\] ++[ ]*[a-f0-9]+: f0 f0 f0 f2 f2 f2 f2 f0 f0 f0 f0 f3 0f 10 00 lock lock lock repnz repnz repnz repnz lock lock lock lock movss xmm0,DWORD PTR \[rax\] +#pass diff --git a/gas/testsuite/gas/i386/x86-64-long-1.d b/gas/testsuite/gas/i386/x86-64-long-1.d new file mode 100644 -index 0000000..dbb603a +index 0000000..20be6f4 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-long-1.d @@ -0,0 +1,13 @@ @@ -1446473,13 +1454391,13 @@ index 0000000..dbb603a +Disassembly of section .text: + +0+ : -+[ ]*[a-f0-9]+: f2 f0 f0 f0 f2 f2 f2 f2 f2 f2 f0 f0 66 0f 28 repnz lock lock lock repnz repnz repnz repnz repnz repnz lock lock \(bad\) ++[ ]*[a-f0-9]+: f2 f0 f0 f0 f2 f2 f2 f2 f2 f2 f0 f0 f3 0f 10 repnz lock lock lock repnz repnz repnz repnz repnz repnz lock lock \(bad\) +[ ]*[a-f0-9]+: 00 f2 add %dh,%dl -+[ ]*[a-f0-9]+: f0 f0 f0 f2 f2 f2 f2 f0 f0 f0 f0 66 0f 28 00 lock lock lock repnz repnz repnz repnz lock lock lock lock movapd \(%rax\),%xmm0 ++[ ]*[a-f0-9]+: f0 f0 f0 f2 f2 f2 f2 f0 f0 f0 f0 f3 0f 10 00 lock lock lock repnz repnz repnz repnz lock lock lock lock movss \(%rax\),%xmm0 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-long-1.s b/gas/testsuite/gas/i386/x86-64-long-1.s new file mode 100644 -index 0000000..73f9a53 +index 0000000..2b91242 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-long-1.s @@ -0,0 +1,30 @@ @@ -1446499,7 +1454417,7 @@ index 0000000..73f9a53 +.byte 0xf2 +.byte 0xf0 +.byte 0xf0 -+movapd (%rax), %xmm0 ++movss (%rax), %xmm0 +.byte 0xf2 +.byte 0xf0 +.byte 0xf0 @@ -1446512,7 +1454430,7 @@ index 0000000..73f9a53 +.byte 0xf0 +.byte 0xf0 +.byte 0xf0 -+movapd (%rax), %xmm0 ++movss (%rax), %xmm0 diff --git a/gas/testsuite/gas/i386/x86-64-lwp.d b/gas/testsuite/gas/i386/x86-64-lwp.d new file mode 100644 index 0000000..fbae74f @@ -1447557,7 +1455475,7 @@ index 0000000..5fe9088 + call foo@plt diff --git a/gas/testsuite/gas/i386/x86-64-mpx-inval-1.l b/gas/testsuite/gas/i386/x86-64-mpx-inval-1.l new file mode 100644 -index 0000000..e78ab7c +index 0000000..16b3aff --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-mpx-inval-1.l @@ -0,0 +1,33 @@ @@ -1447577,23 +1455495,23 @@ index 0000000..e78ab7c +[ ]*2[ ]+\.allow_index_reg +[ ]*3[ ]+\.text +[ ]*4[ ]+\?\?\?\? F24801C3 bnd add %rax, %rbx \# Bad -+\*\*\*\* Error:expecting valid branch instruction after `bnd' ++.* Error: expecting valid branch instruction after `bnd' +[ ]*5[ ]+\?\?\?\? 6766F2AB bnd stosw \(%edi\) \# Bad -+\*\*\*\* Error:expecting valid branch instruction after `bnd' ++.* Error: expecting valid branch instruction after `bnd' +[ ]*6[ ]+\?\?\?\? F2E200 bnd loop foo -+\*\*\*\* Error:expecting valid branch instruction after `bnd' ++.* Error: expecting valid branch instruction after `bnd' +[ ]*7[ ]+\?\?\?\? F2E300 bnd jrcxz foo -+\*\*\*\* Error:expecting valid branch instruction after `bnd' ++.* Error: expecting valid branch instruction after `bnd' +[ ]*8[ ]+ +[ ]*9[ ]+\.intel_syntax noprefix +[ ]*10[ ]+\?\?\?\? F24801C3 bnd add rbx, rax \# Bad -+\*\*\*\* Error:expecting valid branch instruction after `bnd' ++.* Error: expecting valid branch instruction after `bnd' +[ ]*11[ ]+\?\?\?\? 6766F2AB bnd stos WORD PTR \[edi] \# Bad -+\*\*\*\* Error:expecting valid branch instruction after `bnd' ++.* Error: expecting valid branch instruction after `bnd' +[ ]*12[ ]+\?\?\?\? F2E200 bnd loop foo -+\*\*\*\* Error:expecting valid branch instruction after `bnd' ++.* Error: expecting valid branch instruction after `bnd' +[ ]*13[ ]+\?\?\?\? F2E300 bnd jrcxz foo -+\*\*\*\* Error:expecting valid branch instruction after `bnd' ++.* Error: expecting valid branch instruction after `bnd' diff --git a/gas/testsuite/gas/i386/x86-64-mpx-inval-1.s b/gas/testsuite/gas/i386/x86-64-mpx-inval-1.s new file mode 100644 index 0000000..afa04fc @@ -1447615,7 +1455533,7 @@ index 0000000..afa04fc + bnd jrcxz foo diff --git a/gas/testsuite/gas/i386/x86-64-mpx-inval-2.l b/gas/testsuite/gas/i386/x86-64-mpx-inval-2.l new file mode 100644 -index 0000000..820d87a +index 0000000..c7be066 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-mpx-inval-2.l @@ -0,0 +1,173 @@ @@ -1447661,57 +1455579,57 @@ index 0000000..820d87a +[ ]*4[ ]+ +[ ]*5[ ]+\#\#\# bndmk +[ ]*6[ ]+\?\?\?\? 67F30F1B bndmk \(%eax\), %bnd1 -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*6[ ]+08 +[ ]*7[ ]+\?\?\?\? 67F30F1B bndmk 0x3\(%ecx,%ebx,1\), %bnd1 -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*7[ ]+4C1903 +[ ]*8[ ]+ +[ ]*9[ ]+\#\#\# bndmov +[ ]*10[ ]+\?\?\?\? 6766410F bndmov \(%r8d\), %bnd1 -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*10[ ]+1A08 +[ ]*11[ ]+\?\?\?\? 6766410F bndmov 0x3\(%r9d,%edx,1\), %bnd1 -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*11[ ]+1A4C1103 +[ ]*12[ ]+ +[ ]*13[ ]+\?\?\?\? 67660F1B bndmov %bnd1, \(%eax\) -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*13[ ]+08 +[ ]*14[ ]+\?\?\?\? 67660F1B bndmov %bnd1, 0x3\(%ecx,%eax,1\) -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*14[ ]+4C0103 +[ ]*15[ ]+ +[ ]*16[ ]+\#\#\# bndcl +[ ]*17[ ]+\?\?\?\? 67F30F1A bndcl \(%ecx\), %bnd1 -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*17[ ]+09 +[ ]*18[ ]+\?\?\?\? 67F30F1A bndcl 0x3\(%ecx,%eax,1\), %bnd1 -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*18[ ]+4C0103 +[ ]*19[ ]+ +[ ]*20[ ]+\#\#\# bndcu +[ ]*21[ ]+\?\?\?\? 67F20F1A bndcu \(%ecx\), %bnd1 -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*21[ ]+09 +[ ]*22[ ]+\?\?\?\? 67F20F1A bndcu 0x3\(%ecx,%eax,1\), %bnd1 -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*22[ ]+4C0103 +[ ]*23[ ]+ +[ ]*24[ ]+\#\#\# bndcn +[ ]*25[ ]+\?\?\?\? 67F20F1B bndcn \(%ecx\), %bnd1 -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*25[ ]+09 +[ ]*26[ ]+\?\?\?\? 67F20F1B bndcn 0x3\(%ecx,%eax,1\), %bnd1 -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*26[ ]+4C0103 +[ ]*27[ ]+ +[ ]*28[ ]+\#\#\# bndstx +[ ]*29[ ]+\?\?\?\? 670F1B44 bndstx %bnd0, 0x3\(%eax,%ebx,1\) -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*29[ ]+1803 +[ ]*30[ ]+\?\?\?\? 670F1B53 bndstx %bnd2, 3\(%ebx,1\) -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. + GAS LISTING .* + + @@ -1447719,57 +1455637,57 @@ index 0000000..820d87a +[ ]*31[ ]+ +[ ]*32[ ]+\#\#\# bndldx +[ ]*33[ ]+\?\?\?\? 670F1A44 bndldx 0x3\(%eax,%ebx,1\), %bnd0 -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*33[ ]+1803 +[ ]*34[ ]+\?\?\?\? 670F1A53 bndldx 3\(%ebx,1\), %bnd2 -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*34[ ]+03 +[ ]*35[ ]+ +[ ]*36[ ]+\.intel_syntax noprefix +[ ]*37[ ]+\?\?\?\? 67F30F1B bndmk bnd1, \[eax\] -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*37[ ]+08 +[ ]*38[ ]+\?\?\?\? 67F30F1B bndmk bnd1, \[edx\+1\*eax\+0x3\] -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*38[ ]+4C0203 +[ ]*39[ ]+ +[ ]*40[ ]+\#\#\# bndmov +[ ]*41[ ]+\?\?\?\? 67660F1A bndmov bnd1, \[eax\] -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*41[ ]+08 +[ ]*42[ ]+\?\?\?\? 67660F1A bndmov bnd1, \[edx\+1\*eax\+0x3\] -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*42[ ]+4C0203 +[ ]*43[ ]+ +[ ]*44[ ]+\?\?\?\? 67660F1B bndmov \[eax\], bnd1 -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*44[ ]+08 +[ ]*45[ ]+\?\?\?\? 67660F1B bndmov \[edx\+1\*eax\+0x3\], bnd1 -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*45[ ]+4C0203 +[ ]*46[ ]+ +[ ]*47[ ]+\#\#\# bndcl +[ ]*48[ ]+\?\?\?\? 67F30F1A bndcl bnd1, \[eax\] -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*48[ ]+08 +[ ]*49[ ]+\?\?\?\? 67F30F1A bndcl bnd1, \[edx\+1\*eax\+0x3\] -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*49[ ]+4C0203 +[ ]*50[ ]+ +[ ]*51[ ]+\#\#\# bndcu +[ ]*52[ ]+\?\?\?\? 67F20F1A bndcu bnd1, \[eax\] -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*52[ ]+08 +[ ]*53[ ]+\?\?\?\? 67F20F1A bndcu bnd1, \[edx\+1\*eax\+0x3\] -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*53[ ]+4C0203 +[ ]*54[ ]+ +[ ]*55[ ]+\#\#\# bndcn +[ ]*56[ ]+\?\?\?\? 67F20F1B bndcn bnd1, \[eax\] -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*56[ ]+08 +[ ]*57[ ]+\?\?\?\? 67F20F1B bndcn bnd1, \[edx\+1\*eax\+0x3\] -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*57[ ]+4C0203 +[ ]*58[ ]+ + GAS LISTING .* @@ -1447777,19 +1455695,19 @@ index 0000000..820d87a + +[ ]*59[ ]+\#\#\# bndstx +[ ]*60[ ]+\?\?\?\? 670F1B44 bndstx \[eax\+ebx\*1\+0x3\], bnd0 -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*60[ ]+1803 +[ ]*61[ ]+\?\?\?\? 670F1B14 bndstx \[1\*ebx\+3\], bnd2 -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*61[ ]+1D030000 +[ ]*61[ ]+00 +[ ]*62[ ]+ +[ ]*63[ ]+\#\#\# bndldx +[ ]*64[ ]+\?\?\?\? 670F1A44 bndldx bnd0, \[eax\+ebx\*1\+0x3\] -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*64[ ]+1803 +[ ]*65[ ]+\?\?\?\? 670F1A14 bndldx bnd2, \[1\*ebx\+3\] -+\*\*\*\* Error:32-bit address isn't allowed in 64-bit MPX instructions\. ++.* Error: 32-bit address isn't allowed in 64-bit MPX instructions\. +[ ]*65[ ]+1D030000 +[ ]*65[ ]+00 diff --git a/gas/testsuite/gas/i386/x86-64-mpx-inval-2.s b/gas/testsuite/gas/i386/x86-64-mpx-inval-2.s @@ -1449281,7 +1457199,7 @@ index 0000000..8474dca +#pass diff --git a/gas/testsuite/gas/i386/x86-64-nops-1-core2.d b/gas/testsuite/gas/i386/x86-64-nops-1-core2.d new file mode 100644 -index 0000000..420230c +index 0000000..9240669 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-nops-1-core2.d @@ -0,0 +1,157 @@ @@ -1449297,25 +1457215,25 @@ index 0000000..420230c + +0+ : +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+10 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+20 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+30 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+40 : +[ ]*[a-f0-9]+: 90 nop @@ -1449323,7 +1457241,7 @@ index 0000000..420230c +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+50 : +[ ]*[a-f0-9]+: 90 nop @@ -1449444,7 +1457362,7 @@ index 0000000..420230c +#pass diff --git a/gas/testsuite/gas/i386/x86-64-nops-1-g64.d b/gas/testsuite/gas/i386/x86-64-nops-1-g64.d new file mode 100644 -index 0000000..427189d +index 0000000..f197486 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-nops-1-g64.d @@ -0,0 +1,157 @@ @@ -1449460,25 +1457378,25 @@ index 0000000..427189d + +0+ : +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+10 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+20 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+30 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+40 : +[ ]*[a-f0-9]+: 90 nop @@ -1449486,7 +1457404,7 @@ index 0000000..427189d +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+50 : +[ ]*[a-f0-9]+: 90 nop @@ -1449774,7 +1457692,7 @@ index 0000000..c9d8028 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-nops-1-nocona.d b/gas/testsuite/gas/i386/x86-64-nops-1-nocona.d new file mode 100644 -index 0000000..244d06b +index 0000000..d5cdd4c --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-nops-1-nocona.d @@ -0,0 +1,156 @@ @@ -1449789,25 +1457707,25 @@ index 0000000..244d06b + +0+ : +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+10 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+20 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+30 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+40 : +[ ]*[a-f0-9]+: 90 nop @@ -1449815,7 +1457733,7 @@ index 0000000..244d06b +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+50 : +[ ]*[a-f0-9]+: 90 nop @@ -1450189,7 +1458107,7 @@ index 0000000..c080695 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-nops-1.d b/gas/testsuite/gas/i386/x86-64-nops-1.d new file mode 100644 -index 0000000..b385ab5 +index 0000000..9b53ab2 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-nops-1.d @@ -0,0 +1,156 @@ @@ -1450204,25 +1458122,25 @@ index 0000000..b385ab5 + +0+ : +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+10 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+20 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+30 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+40 : +[ ]*[a-f0-9]+: 90 nop @@ -1450230,7 +1458148,7 @@ index 0000000..b385ab5 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+50 : +[ ]*[a-f0-9]+: 90 nop @@ -1450351,7 +1458269,7 @@ index 0000000..b385ab5 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-nops-2.d b/gas/testsuite/gas/i386/x86-64-nops-2.d new file mode 100644 -index 0000000..72616f8 +index 0000000..1fdd4f8 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-nops-2.d @@ -0,0 +1,161 @@ @@ -1450367,29 +1458285,29 @@ index 0000000..72616f8 + +0+ : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+10 : +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+20 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+30 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+40 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+50 : +[ ]*[a-f0-9]+: 90 nop @@ -1450397,7 +1458315,7 @@ index 0000000..72616f8 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+60 : +[ ]*[a-f0-9]+: 90 nop @@ -1450518,7 +1458436,7 @@ index 0000000..72616f8 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-nops-3.d b/gas/testsuite/gas/i386/x86-64-nops-3.d new file mode 100644 -index 0000000..a606f84 +index 0000000..08f6d22 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-nops-3.d @@ -0,0 +1,18 @@ @@ -1450535,14 +1458453,14 @@ index 0000000..a606f84 +0+ : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) +[ ]*[a-f0-9]+: 89 c3 mov %eax,%ebx -+[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) +#pass diff --git a/gas/testsuite/gas/i386/x86-64-nops-4-core2.d b/gas/testsuite/gas/i386/x86-64-nops-4-core2.d new file mode 100644 -index 0000000..4f2a3ed +index 0000000..f9143bf --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-nops-4-core2.d @@ -0,0 +1,211 @@ @@ -1450559,29 +1458477,29 @@ index 0000000..4f2a3ed +0+ : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+20 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+40 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+60 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+80 : +[ ]*[a-f0-9]+: 90 nop @@ -1450589,8 +1458507,8 @@ index 0000000..4f2a3ed +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+a0 : +[ ]*[a-f0-9]+: 90 nop @@ -1450599,8 +1458517,8 @@ index 0000000..4f2a3ed +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data32 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data16 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+c0 : +[ ]*[a-f0-9]+: 90 nop @@ -1450611,7 +1458529,7 @@ index 0000000..4f2a3ed +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+e0 : +[ ]*[a-f0-9]+: 90 nop @@ -1450623,7 +1458541,7 @@ index 0000000..4f2a3ed +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 0f 1f 84 00 00 00 00 00 nopw 0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+100 : +[ ]*[a-f0-9]+: 90 nop @@ -1450636,7 +1458554,7 @@ index 0000000..4f2a3ed +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 84 00 00 00 00 00 nopl 0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+120 : +[ ]*[a-f0-9]+: 90 nop @@ -1450650,7 +1458568,7 @@ index 0000000..4f2a3ed +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%rax\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+140 : +[ ]*[a-f0-9]+: 90 nop @@ -1450665,7 +1458583,7 @@ index 0000000..4f2a3ed +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+160 : +[ ]*[a-f0-9]+: 90 nop @@ -1450681,7 +1458599,7 @@ index 0000000..4f2a3ed +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+180 : +[ ]*[a-f0-9]+: 90 nop @@ -1450698,7 +1458616,7 @@ index 0000000..4f2a3ed +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 40 00 nopl 0x0\(%rax\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+1a0 : +[ ]*[a-f0-9]+: 90 nop @@ -1450716,7 +1458634,7 @@ index 0000000..4f2a3ed +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 00 nopl \(%rax\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+1c0 : +[ ]*[a-f0-9]+: 90 nop @@ -1450735,7 +1458653,7 @@ index 0000000..4f2a3ed +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 90 xchg %ax,%ax -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+1e0 : +[ ]*[a-f0-9]+: 90 nop @@ -1450755,7 +1458673,7 @@ index 0000000..4f2a3ed +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) +#pass diff --git a/gas/testsuite/gas/i386/x86-64-nops-4-k8.d b/gas/testsuite/gas/i386/x86-64-nops-4-k8.d new file mode 100644 @@ -1450997,7 +1458915,7 @@ index 0000000..b1145fc +#pass diff --git a/gas/testsuite/gas/i386/x86-64-nops-4.d b/gas/testsuite/gas/i386/x86-64-nops-4.d new file mode 100644 -index 0000000..91afdc2 +index 0000000..8c20c7f --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-nops-4.d @@ -0,0 +1,211 @@ @@ -1451014,29 +1458932,29 @@ index 0000000..91afdc2 +0+ : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+20 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+40 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+60 : +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+80 : +[ ]*[a-f0-9]+: 90 nop @@ -1451044,8 +1458962,8 @@ index 0000000..91afdc2 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+a0 : +[ ]*[a-f0-9]+: 90 nop @@ -1451054,8 +1458972,8 @@ index 0000000..91afdc2 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data32 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 2e 0f 1f 84 00 00 00 00 00 data16 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+c0 : +[ ]*[a-f0-9]+: 90 nop @@ -1451066,7 +1458984,7 @@ index 0000000..91afdc2 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 2e 0f 1f 84 00 00 00 00 00 nopw %cs:0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+e0 : +[ ]*[a-f0-9]+: 90 nop @@ -1451078,7 +1458996,7 @@ index 0000000..91afdc2 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 0f 1f 84 00 00 00 00 00 nopw 0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+100 : +[ ]*[a-f0-9]+: 90 nop @@ -1451091,7 +1459009,7 @@ index 0000000..91afdc2 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 84 00 00 00 00 00 nopl 0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+120 : +[ ]*[a-f0-9]+: 90 nop @@ -1451105,7 +1459023,7 @@ index 0000000..91afdc2 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%rax\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+140 : +[ ]*[a-f0-9]+: 90 nop @@ -1451120,7 +1459038,7 @@ index 0000000..91afdc2 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+160 : +[ ]*[a-f0-9]+: 90 nop @@ -1451136,7 +1459054,7 @@ index 0000000..91afdc2 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%rax,%rax,1\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+180 : +[ ]*[a-f0-9]+: 90 nop @@ -1451153,7 +1459071,7 @@ index 0000000..91afdc2 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 40 00 nopl 0x0\(%rax\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+1a0 : +[ ]*[a-f0-9]+: 90 nop @@ -1451171,7 +1459089,7 @@ index 0000000..91afdc2 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 0f 1f 00 nopl \(%rax\) -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+1c0 : +[ ]*[a-f0-9]+: 90 nop @@ -1451190,7 +1459108,7 @@ index 0000000..91afdc2 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 66 90 xchg %ax,%ax -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+1e0 : +[ ]*[a-f0-9]+: 90 nop @@ -1451210,11 +1459128,11 @@ index 0000000..91afdc2 +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop +[ ]*[a-f0-9]+: 90 nop -+[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) +#pass diff --git a/gas/testsuite/gas/i386/x86-64-nops-5-k8.d b/gas/testsuite/gas/i386/x86-64-nops-5-k8.d new file mode 100644 -index 0000000..ac86b27 +index 0000000..add71bf --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-nops-5-k8.d @@ -0,0 +1,75 @@ @@ -1451250,19 +1459168,19 @@ index 0000000..ac86b27 + +0+40 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+50 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+60 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+70 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+80 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi @@ -1451286,7 +1459204,7 @@ index 0000000..ac86b27 + +0+c0 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+d0 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi @@ -1451295,7 +1459213,7 @@ index 0000000..ac86b27 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-nops-5.d b/gas/testsuite/gas/i386/x86-64-nops-5.d new file mode 100644 -index 0000000..db65c51 +index 0000000..664b010 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-nops-5.d @@ -0,0 +1,74 @@ @@ -1451330,19 +1459248,19 @@ index 0000000..db65c51 + +0+40 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+50 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+60 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+70 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+80 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi @@ -1451366,7 +1459284,7 @@ index 0000000..db65c51 + +0+c0 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +0+d0 : +[ ]*[a-f0-9]+: 0f be f0 movsbl %al,%esi @@ -1453529,6 +1461447,68 @@ index 0000000..92f09f1 +\s*[a-f0-9]+: 0f 18 28 nop/reserved \(%rax\) +\s*[a-f0-9]+: 0f 18 30 nop/reserved \(%rax\) +\s*[a-f0-9]+: 0f 18 38 nop/reserved \(%rax\) +diff --git a/gas/testsuite/gas/i386/x86-64-prefetchwt1-intel.d b/gas/testsuite/gas/i386/x86-64-prefetchwt1-intel.d +new file mode 100644 +index 0000000..1fbdba4 +--- /dev/null ++++ b/gas/testsuite/gas/i386/x86-64-prefetchwt1-intel.d +@@ -0,0 +1,16 @@ ++#as: ++#objdump: -dwMintel ++#name: x86_64 PREFETCHWT1 insns (Intel disassembly) ++#source: x86-64-prefetchwt1.s ++ ++.*: +file format .* ++ ++ ++Disassembly of section .text: ++ ++0+ <_start>: ++[ ]*[a-f0-9]+: 0f 0d 11 prefetchwt1 BYTE PTR \[rcx\] ++[ ]*[a-f0-9]+: 42 0f 0d 94 f0 23 01 00 00 prefetchwt1 BYTE PTR \[rax\+r14\*8\+0x123\] ++[ ]*[a-f0-9]+: 0f 0d 11 prefetchwt1 BYTE PTR \[rcx\] ++[ ]*[a-f0-9]+: 42 0f 0d 94 f0 34 12 00 00 prefetchwt1 BYTE PTR \[rax\+r14\*8\+0x1234\] ++#pass +diff --git a/gas/testsuite/gas/i386/x86-64-prefetchwt1.d b/gas/testsuite/gas/i386/x86-64-prefetchwt1.d +new file mode 100644 +index 0000000..1118f55 +--- /dev/null ++++ b/gas/testsuite/gas/i386/x86-64-prefetchwt1.d +@@ -0,0 +1,15 @@ ++#as: ++#objdump: -dw ++#name: x86_64 PREFETCHWT1 insns ++ ++.*: +file format .* ++ ++ ++Disassembly of section .text: ++ ++0+ <_start>: ++[ ]*[a-f0-9]+: 0f 0d 11 prefetchwt1 \(%rcx\) ++[ ]*[a-f0-9]+: 42 0f 0d 94 f0 23 01 00 00 prefetchwt1 0x123\(%rax,%r14,8\) ++[ ]*[a-f0-9]+: 0f 0d 11 prefetchwt1 \(%rcx\) ++[ ]*[a-f0-9]+: 42 0f 0d 94 f0 34 12 00 00 prefetchwt1 0x1234\(%rax,%r14,8\) ++#pass +diff --git a/gas/testsuite/gas/i386/x86-64-prefetchwt1.s b/gas/testsuite/gas/i386/x86-64-prefetchwt1.s +new file mode 100644 +index 0000000..ae63b42 +--- /dev/null ++++ b/gas/testsuite/gas/i386/x86-64-prefetchwt1.s +@@ -0,0 +1,13 @@ ++# Check 64bit AVX512PF instructions ++ ++ .allow_index_reg ++ .text ++_start: ++ ++ prefetchwt1 (%rcx) # AVX512PF ++ prefetchwt1 0x123(%rax,%r14,8) # AVX512PF ++ ++ .intel_syntax noprefix ++ ++ prefetchwt1 BYTE PTR [rcx] # AVX512PF ++ prefetchwt1 BYTE PTR [rax+r14*8+0x1234] # AVX512PF diff --git a/gas/testsuite/gas/i386/x86-64-rdrnd-intel.d b/gas/testsuite/gas/i386/x86-64-rdrnd-intel.d new file mode 100644 index 0000000..0bb8798 @@ -1454255,6 +1462235,38 @@ index 0000000..17a1402 +2: + xend + xtest +diff --git a/gas/testsuite/gas/i386/x86-64-se1.d b/gas/testsuite/gas/i386/x86-64-se1.d +new file mode 100644 +index 0000000..29494f0 +--- /dev/null ++++ b/gas/testsuite/gas/i386/x86-64-se1.d +@@ -0,0 +1,13 @@ ++#objdump: -dw ++#name: x86-64 SE1 insns ++#source: x86-64-se1.s ++ ++.*: +file format .* ++ ++ ++Disassembly of section .text: ++ ++0+ <_start>: ++[ ]*[a-f0-9]+: 0f 01 cf encls ++[ ]*[a-f0-9]+: 0f 01 d7 enclu ++#pass +diff --git a/gas/testsuite/gas/i386/x86-64-se1.s b/gas/testsuite/gas/i386/x86-64-se1.s +new file mode 100644 +index 0000000..1b57ac8 +--- /dev/null ++++ b/gas/testsuite/gas/i386/x86-64-se1.s +@@ -0,0 +1,7 @@ ++# Check SE1 new instructions. ++ ++ .text ++_start: ++ ++ encls ++ enclu diff --git a/gas/testsuite/gas/i386/x86-64-segment.l b/gas/testsuite/gas/i386/x86-64-segment.l new file mode 100644 index 0000000..4056fde @@ -1455889,7 +1463901,7 @@ index 0000000..42d248e + .quad zzz@SIZE diff --git a/gas/testsuite/gas/i386/x86-64-size-inval-1.l b/gas/testsuite/gas/i386/x86-64-size-inval-1.l new file mode 100644 -index 0000000..856174d +index 0000000..1d60ac1 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-size-inval-1.l @@ -0,0 +1,25 @@ @@ -1455914,10 +1463926,10 @@ index 0000000..856174d +[ ]*9[ ]+\.data +[ ]*10[ ]+\?\?\?\? 5E000000 \.long xxx@SIZE \+ 100 +[ ]*11[ ]+\?\?\?\? ECFFFFFF \.long yyy@SIZE - 100 -+\*\*\*\* Error:symbol size computation overflow -+\*\*\*\* Error:symbol size computation overflow -+\*\*\*\* Error:symbol size computation overflow -+\*\*\*\* Error:symbol size computation overflow ++.* Error: symbol size computation overflow ++.* Error: symbol size computation overflow ++.* Error: symbol size computation overflow ++.* Error: symbol size computation overflow diff --git a/gas/testsuite/gas/i386/x86-64-size-inval-1.s b/gas/testsuite/gas/i386/x86-64-size-inval-1.s new file mode 100644 index 0000000..020eb10 @@ -1456433,7 +1464445,7 @@ index 0000000..e6b780b +.endr diff --git a/gas/testsuite/gas/i386/x86-64-sse-check-error.l b/gas/testsuite/gas/i386/x86-64-sse-check-error.l new file mode 100644 -index 0000000..bd1c4f6 +index 0000000..5df6d67 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-sse-check-error.l @@ -0,0 +1,40 @@ @@ -1456455,27 +1464467,27 @@ index 0000000..bd1c4f6 +[ ]*5[ ]+ +[ ]*6[ ]+\# SSE instruction +[ ]*7[ ]+\?\?\?\? 0F58CA addps %xmm2,%xmm1 -+\*\*\*\* Error:SSE instruction `addps' is used ++.* Error: SSE instruction `addps' is used +[ ]*8[ ]+ +[ ]*9[ ]+\# SSE2 instruction +[ ]*10[ ]+\?\?\?\? 660F58CA addpd %xmm2,%xmm1 -+\*\*\*\* Error:SSE instruction `addpd' is used ++.* Error: SSE instruction `addpd' is used +[ ]*11[ ]+ +[ ]*12[ ]+\# SSE3 instruction +[ ]*13[ ]+\?\?\?\? 660FD0CA addsubpd %xmm2,%xmm1 -+\*\*\*\* Error:SSE instruction `addsubpd' is used ++.* Error: SSE instruction `addsubpd' is used +[ ]*14[ ]+ +[ ]*15[ ]+\# SSSE3 instruction +[ ]*16[ ]+\?\?\?\? 660F3801 phaddw %xmm2,%xmm1 -+\*\*\*\* Error:SSE instruction `phaddw' is used ++.* Error: SSE instruction `phaddw' is used +[ ]*16[ ]+CA +[ ]*17[ ]+ +[ ]*18[ ]+\# SSE4 instructions +[ ]*19[ ]+\?\?\?\? 660F3815 blendvpd %xmm0,%xmm1,%xmm0 -+\*\*\*\* Error:SSE instruction `blendvpd' is used ++.* Error: SSE instruction `blendvpd' is used +[ ]*19[ ]+C1 +[ ]*20[ ]+\?\?\?\? 660F3837 pcmpgtq %xmm1,%xmm0 -+\*\*\*\* Error:SSE instruction `pcmpgtq' is used ++.* Error: SSE instruction `pcmpgtq' is used +[ ]*20[ ]+C1 diff --git a/gas/testsuite/gas/i386/x86-64-sse-check-error.s b/gas/testsuite/gas/i386/x86-64-sse-check-error.s new file mode 100644 @@ -1461146,7 +1469158,7 @@ index 0000000..f298ba6 + .p2align 4,0 diff --git a/gas/testsuite/gas/i386/x86-64-stack-intel.d b/gas/testsuite/gas/i386/x86-64-stack-intel.d new file mode 100644 -index 0000000..1902337 +index 0000000..b392579 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-stack-intel.d @@ -0,0 +1,70 @@ @@ -1461162,56 +1469174,56 @@ index 0000000..1902337 +[ ]*[a-f0-9]+: 50 push rax +[ ]*[a-f0-9]+: 66 50 push ax +[ ]*[a-f0-9]+: 48 50 rex.W push rax -+[ ]*[a-f0-9]+: 66 48 50 data32 rex.W push rax ++[ ]*[a-f0-9]+: 66 48 50 data16 rex.W push rax +[ ]*[a-f0-9]+: 58 pop rax +[ ]*[a-f0-9]+: 66 58 pop ax +[ ]*[a-f0-9]+: 48 58 rex.W pop rax -+[ ]*[a-f0-9]+: 66 48 58 data32 rex.W pop rax ++[ ]*[a-f0-9]+: 66 48 58 data16 rex.W pop rax +[ ]*[a-f0-9]+: 8f c0 pop rax +[ ]*[a-f0-9]+: 66 8f c0 pop ax +[ ]*[a-f0-9]+: 48 8f c0 rex.W pop rax -+[ ]*[a-f0-9]+: 66 48 8f c0 data32 rex.W pop rax ++[ ]*[a-f0-9]+: 66 48 8f c0 data16 rex.W pop rax +[ ]*[a-f0-9]+: 8f 00 pop QWORD PTR \[rax\] +[ ]*[a-f0-9]+: 66 8f 00 pop WORD PTR \[rax\] +[ ]*[a-f0-9]+: 48 8f 00 rex.W pop QWORD PTR \[rax\] -+[ ]*[a-f0-9]+: 66 48 8f 00 data32 rex.W pop QWORD PTR \[rax\] ++[ ]*[a-f0-9]+: 66 48 8f 00 data16 rex.W pop QWORD PTR \[rax\] +[ ]*[a-f0-9]+: ff d0 call rax +[ ]*[a-f0-9]+: 66 ff d0 call ax +[ ]*[a-f0-9]+: 48 ff d0 rex.W call rax -+[ ]*[a-f0-9]+: 66 48 ff d0 data32 rex.W call rax ++[ ]*[a-f0-9]+: 66 48 ff d0 data16 rex.W call rax +[ ]*[a-f0-9]+: ff 10 call QWORD PTR \[rax\] +[ ]*[a-f0-9]+: 66 ff 10 call WORD PTR \[rax\] +[ ]*[a-f0-9]+: 48 ff 10 rex.W call QWORD PTR \[rax\] -+[ ]*[a-f0-9]+: 66 48 ff 10 data32 rex.W call QWORD PTR \[rax\] ++[ ]*[a-f0-9]+: 66 48 ff 10 data16 rex.W call QWORD PTR \[rax\] +[ ]*[a-f0-9]+: ff e0 jmp rax +[ ]*[a-f0-9]+: 66 ff e0 jmp ax +[ ]*[a-f0-9]+: 48 ff e0 rex.W jmp rax -+[ ]*[a-f0-9]+: 66 48 ff e0 data32 rex.W jmp rax ++[ ]*[a-f0-9]+: 66 48 ff e0 data16 rex.W jmp rax +[ ]*[a-f0-9]+: ff 20 jmp QWORD PTR \[rax\] +[ ]*[a-f0-9]+: 66 ff 20 jmp WORD PTR \[rax\] +[ ]*[a-f0-9]+: 48 ff 20 rex.W jmp QWORD PTR \[rax\] -+[ ]*[a-f0-9]+: 66 48 ff 20 data32 rex.W jmp QWORD PTR \[rax\] ++[ ]*[a-f0-9]+: 66 48 ff 20 data16 rex.W jmp QWORD PTR \[rax\] +[ ]*[a-f0-9]+: ff f0 push rax +[ ]*[a-f0-9]+: 66 ff f0 push ax +[ ]*[a-f0-9]+: 48 ff f0 rex.W push rax -+[ ]*[a-f0-9]+: 66 48 ff f0 data32 rex.W push rax ++[ ]*[a-f0-9]+: 66 48 ff f0 data16 rex.W push rax +[ ]*[a-f0-9]+: ff 30 push QWORD PTR \[rax\] +[ ]*[a-f0-9]+: 66 ff 30 push WORD PTR \[rax\] +[ ]*[a-f0-9]+: 48 ff 30 rex.W push QWORD PTR \[rax\] -+[ ]*[a-f0-9]+: 66 48 ff 30 data32 rex.W push QWORD PTR \[rax\] ++[ ]*[a-f0-9]+: 66 48 ff 30 data16 rex.W push QWORD PTR \[rax\] +[ ]*[a-f0-9]+: 6a ff push 0xffffffffffffffff +[ ]*[a-f0-9]+: 66 6a ff pushw 0xffff +[ ]*[a-f0-9]+: 48 6a ff rex.W push 0xffffffffffffffff -+[ ]*[a-f0-9]+: 66 48 6a ff data32 rex.W push 0xffffffffffffffff ++[ ]*[a-f0-9]+: 66 48 6a ff data16 rex.W push 0xffffffffffffffff +[ ]*[a-f0-9]+: 68 01 02 03 04 push 0x4030201 +[ ]*[a-f0-9]+: 66 68 01 02 pushw 0x201 +[ ]*[a-f0-9]+: 03 04 48 add eax,DWORD PTR \[rax\+rcx\*2\] +[ ]*[a-f0-9]+: 68 01 02 03 04 push 0x4030201 -+[ ]*[a-f0-9]+: 66 48 68 01 02 03 04 data32 rex.W push 0x4030201 ++[ ]*[a-f0-9]+: 66 48 68 01 02 03 04 data16 rex.W push 0x4030201 +[ ]*[a-f0-9]+: 0f a8 push gs +[ ]*[a-f0-9]+: 66 0f a8 pushw gs +[ ]*[a-f0-9]+: 48 0f a8 rex.W push gs -+[ ]*[a-f0-9]+: 66 48 0f a8 data32 rex.W push gs ++[ ]*[a-f0-9]+: 66 48 0f a8 data16 rex.W push gs +[ ]*[a-f0-9]+: 41 0f a8 rex.B push gs +[ ]*[a-f0-9]+: 66 41 0f a8 rex.B pushw gs +[ ]*[a-f0-9]+: 48 rex.W @@ -1461222,7 +1469234,7 @@ index 0000000..1902337 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-stack-suffix.d b/gas/testsuite/gas/i386/x86-64-stack-suffix.d new file mode 100644 -index 0000000..1681d79 +index 0000000..7c52e10 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-stack-suffix.d @@ -0,0 +1,70 @@ @@ -1461238,56 +1469250,56 @@ index 0000000..1681d79 +[ ]*[a-f0-9]+: 50 pushq %rax +[ ]*[a-f0-9]+: 66 50 pushw %ax +[ ]*[a-f0-9]+: 48 50 rex.W pushq %rax -+[ ]*[a-f0-9]+: 66 48 50 data32 rex.W pushq %rax ++[ ]*[a-f0-9]+: 66 48 50 data16 rex.W pushq %rax +[ ]*[a-f0-9]+: 58 popq %rax +[ ]*[a-f0-9]+: 66 58 popw %ax +[ ]*[a-f0-9]+: 48 58 rex.W popq %rax -+[ ]*[a-f0-9]+: 66 48 58 data32 rex.W popq %rax ++[ ]*[a-f0-9]+: 66 48 58 data16 rex.W popq %rax +[ ]*[a-f0-9]+: 8f c0 popq %rax +[ ]*[a-f0-9]+: 66 8f c0 popw %ax +[ ]*[a-f0-9]+: 48 8f c0 rex.W popq %rax -+[ ]*[a-f0-9]+: 66 48 8f c0 data32 rex.W popq %rax ++[ ]*[a-f0-9]+: 66 48 8f c0 data16 rex.W popq %rax +[ ]*[a-f0-9]+: 8f 00 popq \(%rax\) +[ ]*[a-f0-9]+: 66 8f 00 popw \(%rax\) +[ ]*[a-f0-9]+: 48 8f 00 rex.W popq \(%rax\) -+[ ]*[a-f0-9]+: 66 48 8f 00 data32 rex.W popq \(%rax\) ++[ ]*[a-f0-9]+: 66 48 8f 00 data16 rex.W popq \(%rax\) +[ ]*[a-f0-9]+: ff d0 callq \*%rax +[ ]*[a-f0-9]+: 66 ff d0 callw \*%ax +[ ]*[a-f0-9]+: 48 ff d0 rex.W callq \*%rax -+[ ]*[a-f0-9]+: 66 48 ff d0 data32 rex.W callq \*%rax ++[ ]*[a-f0-9]+: 66 48 ff d0 data16 rex.W callq \*%rax +[ ]*[a-f0-9]+: ff 10 callq \*\(%rax\) +[ ]*[a-f0-9]+: 66 ff 10 callw \*\(%rax\) +[ ]*[a-f0-9]+: 48 ff 10 rex.W callq \*\(%rax\) -+[ ]*[a-f0-9]+: 66 48 ff 10 data32 rex.W callq \*\(%rax\) ++[ ]*[a-f0-9]+: 66 48 ff 10 data16 rex.W callq \*\(%rax\) +[ ]*[a-f0-9]+: ff e0 jmpq \*%rax +[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax +[ ]*[a-f0-9]+: 48 ff e0 rex.W jmpq \*%rax -+[ ]*[a-f0-9]+: 66 48 ff e0 data32 rex.W jmpq \*%rax ++[ ]*[a-f0-9]+: 66 48 ff e0 data16 rex.W jmpq \*%rax +[ ]*[a-f0-9]+: ff 20 jmpq \*\(%rax\) +[ ]*[a-f0-9]+: 66 ff 20 jmpw \*\(%rax\) +[ ]*[a-f0-9]+: 48 ff 20 rex.W jmpq \*\(%rax\) -+[ ]*[a-f0-9]+: 66 48 ff 20 data32 rex.W jmpq \*\(%rax\) ++[ ]*[a-f0-9]+: 66 48 ff 20 data16 rex.W jmpq \*\(%rax\) +[ ]*[a-f0-9]+: ff f0 pushq %rax +[ ]*[a-f0-9]+: 66 ff f0 pushw %ax +[ ]*[a-f0-9]+: 48 ff f0 rex.W pushq %rax -+[ ]*[a-f0-9]+: 66 48 ff f0 data32 rex.W pushq %rax ++[ ]*[a-f0-9]+: 66 48 ff f0 data16 rex.W pushq %rax +[ ]*[a-f0-9]+: ff 30 pushq \(%rax\) +[ ]*[a-f0-9]+: 66 ff 30 pushw \(%rax\) +[ ]*[a-f0-9]+: 48 ff 30 rex.W pushq \(%rax\) -+[ ]*[a-f0-9]+: 66 48 ff 30 data32 rex.W pushq \(%rax\) ++[ ]*[a-f0-9]+: 66 48 ff 30 data16 rex.W pushq \(%rax\) +[ ]*[a-f0-9]+: 6a ff pushq \$0xffffffffffffffff +[ ]*[a-f0-9]+: 66 6a ff pushw \$0xffff +[ ]*[a-f0-9]+: 48 6a ff rex.W pushq \$0xffffffffffffffff -+[ ]*[a-f0-9]+: 66 48 6a ff data32 rex.W pushq \$0xffffffffffffffff ++[ ]*[a-f0-9]+: 66 48 6a ff data16 rex.W pushq \$0xffffffffffffffff +[ ]*[a-f0-9]+: 68 01 02 03 04 pushq \$0x4030201 +[ ]*[a-f0-9]+: 66 68 01 02 pushw \$0x201 +[ ]*[a-f0-9]+: 03 04 48 addl \(%rax,%rcx,2\),%eax +[ ]*[a-f0-9]+: 68 01 02 03 04 pushq \$0x4030201 -+[ ]*[a-f0-9]+: 66 48 68 01 02 03 04 data32 rex.W pushq \$0x4030201 ++[ ]*[a-f0-9]+: 66 48 68 01 02 03 04 data16 rex.W pushq \$0x4030201 +[ ]*[a-f0-9]+: 0f a8 pushq %gs +[ ]*[a-f0-9]+: 66 0f a8 pushw %gs +[ ]*[a-f0-9]+: 48 0f a8 rex.W pushq %gs -+[ ]*[a-f0-9]+: 66 48 0f a8 data32 rex.W pushq %gs ++[ ]*[a-f0-9]+: 66 48 0f a8 data16 rex.W pushq %gs +[ ]*[a-f0-9]+: 41 0f a8 rex.B pushq %gs +[ ]*[a-f0-9]+: 66 41 0f a8 rex.B pushw %gs +[ ]*[a-f0-9]+: 48 rex.W @@ -1461298,7 +1469310,7 @@ index 0000000..1681d79 +#pass diff --git a/gas/testsuite/gas/i386/x86-64-stack.d b/gas/testsuite/gas/i386/x86-64-stack.d new file mode 100644 -index 0000000..760d769 +index 0000000..1b2458e --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-stack.d @@ -0,0 +1,69 @@ @@ -1461313,56 +1469325,56 @@ index 0000000..760d769 +[ ]*[a-f0-9]+: 50 push %rax +[ ]*[a-f0-9]+: 66 50 push %ax +[ ]*[a-f0-9]+: 48 50 rex.W push %rax -+[ ]*[a-f0-9]+: 66 48 50 data32 rex.W push %rax ++[ ]*[a-f0-9]+: 66 48 50 data16 rex.W push %rax +[ ]*[a-f0-9]+: 58 pop %rax +[ ]*[a-f0-9]+: 66 58 pop %ax +[ ]*[a-f0-9]+: 48 58 rex.W pop %rax -+[ ]*[a-f0-9]+: 66 48 58 data32 rex.W pop %rax ++[ ]*[a-f0-9]+: 66 48 58 data16 rex.W pop %rax +[ ]*[a-f0-9]+: 8f c0 pop %rax +[ ]*[a-f0-9]+: 66 8f c0 pop %ax +[ ]*[a-f0-9]+: 48 8f c0 rex.W pop %rax -+[ ]*[a-f0-9]+: 66 48 8f c0 data32 rex.W pop %rax ++[ ]*[a-f0-9]+: 66 48 8f c0 data16 rex.W pop %rax +[ ]*[a-f0-9]+: 8f 00 popq \(%rax\) +[ ]*[a-f0-9]+: 66 8f 00 popw \(%rax\) +[ ]*[a-f0-9]+: 48 8f 00 rex.W popq \(%rax\) -+[ ]*[a-f0-9]+: 66 48 8f 00 data32 rex.W popq \(%rax\) ++[ ]*[a-f0-9]+: 66 48 8f 00 data16 rex.W popq \(%rax\) +[ ]*[a-f0-9]+: ff d0 callq \*%rax +[ ]*[a-f0-9]+: 66 ff d0 callw \*%ax +[ ]*[a-f0-9]+: 48 ff d0 rex.W callq \*%rax -+[ ]*[a-f0-9]+: 66 48 ff d0 data32 rex.W callq \*%rax ++[ ]*[a-f0-9]+: 66 48 ff d0 data16 rex.W callq \*%rax +[ ]*[a-f0-9]+: ff 10 callq \*\(%rax\) +[ ]*[a-f0-9]+: 66 ff 10 callw \*\(%rax\) +[ ]*[a-f0-9]+: 48 ff 10 rex.W callq \*\(%rax\) -+[ ]*[a-f0-9]+: 66 48 ff 10 data32 rex.W callq \*\(%rax\) ++[ ]*[a-f0-9]+: 66 48 ff 10 data16 rex.W callq \*\(%rax\) +[ ]*[a-f0-9]+: ff e0 jmpq \*%rax +[ ]*[a-f0-9]+: 66 ff e0 jmpw \*%ax +[ ]*[a-f0-9]+: 48 ff e0 rex.W jmpq \*%rax -+[ ]*[a-f0-9]+: 66 48 ff e0 data32 rex.W jmpq \*%rax ++[ ]*[a-f0-9]+: 66 48 ff e0 data16 rex.W jmpq \*%rax +[ ]*[a-f0-9]+: ff 20 jmpq \*\(%rax\) +[ ]*[a-f0-9]+: 66 ff 20 jmpw \*\(%rax\) +[ ]*[a-f0-9]+: 48 ff 20 rex.W jmpq \*\(%rax\) -+[ ]*[a-f0-9]+: 66 48 ff 20 data32 rex.W jmpq \*\(%rax\) ++[ ]*[a-f0-9]+: 66 48 ff 20 data16 rex.W jmpq \*\(%rax\) +[ ]*[a-f0-9]+: ff f0 push %rax +[ ]*[a-f0-9]+: 66 ff f0 push %ax +[ ]*[a-f0-9]+: 48 ff f0 rex.W push %rax -+[ ]*[a-f0-9]+: 66 48 ff f0 data32 rex.W push %rax ++[ ]*[a-f0-9]+: 66 48 ff f0 data16 rex.W push %rax +[ ]*[a-f0-9]+: ff 30 pushq \(%rax\) +[ ]*[a-f0-9]+: 66 ff 30 pushw \(%rax\) +[ ]*[a-f0-9]+: 48 ff 30 rex.W pushq \(%rax\) -+[ ]*[a-f0-9]+: 66 48 ff 30 data32 rex.W pushq \(%rax\) ++[ ]*[a-f0-9]+: 66 48 ff 30 data16 rex.W pushq \(%rax\) +[ ]*[a-f0-9]+: 6a ff pushq \$0xffffffffffffffff +[ ]*[a-f0-9]+: 66 6a ff pushw \$0xffff +[ ]*[a-f0-9]+: 48 6a ff rex.W pushq \$0xffffffffffffffff -+[ ]*[a-f0-9]+: 66 48 6a ff data32 rex.W pushq \$0xffffffffffffffff ++[ ]*[a-f0-9]+: 66 48 6a ff data16 rex.W pushq \$0xffffffffffffffff +[ ]*[a-f0-9]+: 68 01 02 03 04 pushq \$0x4030201 +[ ]*[a-f0-9]+: 66 68 01 02 pushw \$0x201 +[ ]*[a-f0-9]+: 03 04 48 add \(%rax,%rcx,2\),%eax +[ ]*[a-f0-9]+: 68 01 02 03 04 pushq \$0x4030201 -+[ ]*[a-f0-9]+: 66 48 68 01 02 03 04 data32 rex.W pushq \$0x4030201 ++[ ]*[a-f0-9]+: 66 48 68 01 02 03 04 data16 rex.W pushq \$0x4030201 +[ ]*[a-f0-9]+: 0f a8 pushq %gs +[ ]*[a-f0-9]+: 66 0f a8 pushw %gs +[ ]*[a-f0-9]+: 48 0f a8 rex.W pushq %gs -+[ ]*[a-f0-9]+: 66 48 0f a8 data32 rex.W pushq %gs ++[ ]*[a-f0-9]+: 66 48 0f a8 data16 rex.W pushq %gs +[ ]*[a-f0-9]+: 41 0f a8 rex.B pushq %gs +[ ]*[a-f0-9]+: 66 41 0f a8 rex.B pushw %gs +[ ]*[a-f0-9]+: 48 rex.W @@ -1462509,14 +1470521,22 @@ index 0000000..da6f0f5 +.long 1 diff --git a/gas/testsuite/gas/i386/x86-64-vgather-check-error.l b/gas/testsuite/gas/i386/x86-64-vgather-check-error.l new file mode 100644 -index 0000000..d5c7205 +index 0000000..28fa824 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-vgather-check-error.l -@@ -0,0 +1,4 @@ +@@ -0,0 +1,12 @@ +.*: Assembler messages: +.*:6: Error: .* +.*:8: Error: .* +.*:10: Error: .* ++.*:15: Error: .* ++.*:17: Error: .* ++.*:19: Error: .* ++.*:21: Error: .* ++.*:23: Error: .* ++.*:25: Error: .* ++.*:27: Error: .* ++.*:29: Error: .* diff --git a/gas/testsuite/gas/i386/x86-64-vgather-check-error.s b/gas/testsuite/gas/i386/x86-64-vgather-check-error.s new file mode 100644 index 0000000..f038be2 @@ -1462526,10 +1470546,10 @@ index 0000000..f038be2 +.include "x86-64-vgather-check.s" diff --git a/gas/testsuite/gas/i386/x86-64-vgather-check-none.d b/gas/testsuite/gas/i386/x86-64-vgather-check-none.d new file mode 100644 -index 0000000..e235e00 +index 0000000..a1062f7 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-vgather-check-none.d -@@ -0,0 +1,17 @@ +@@ -0,0 +1,35 @@ +#as: -moperand-check=error -I${srcdir}/$subdir +#objdump: -dw +#name: x86-64 vgather check (.operand_check none) @@ -1462546,6 +1470566,24 @@ index 0000000..e235e00 +[ ]*[a-f0-9]+:[ ]+c4 e2 31 92 04 88[ ]+vgatherdps %xmm9,\(%rax,%xmm1,4\),%xmm0 +[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 0c c8[ ]+vgatherdps %xmm2,\(%rax,%xmm1,8\),%xmm1 +[ ]*[a-f0-9]+:[ ]+c4 62 69 92 0c c8[ ]+vgatherdps %xmm2,\(%rax,%xmm1,8\),%xmm9 ++ ++000000000000002a : ++[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 92 84 cd 7b 00 00 00[ ]+vgatherdpd 0x7b\(%rbp,%ymm17,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 92 84 c5 7b 00 00 00[ ]+vgatherdpd 0x7b\(%rbp,%ymm16,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 92 84 cd 7b 00 00 00[ ]+vgatherdps 0x7b\(%rbp,%zmm17,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 92 84 c5 7b 00 00 00[ ]+vgatherdps 0x7b\(%rbp,%zmm16,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 93 84 cd 7b 00 00 00[ ]+vgatherqpd 0x7b\(%rbp,%zmm17,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 93 84 c5 7b 00 00 00[ ]+vgatherqpd 0x7b\(%rbp,%zmm16,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 93 84 cd 7b 00 00 00[ ]+vgatherqps 0x7b\(%rbp,%zmm17,8\),%ymm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 93 84 c5 7b 00 00 00[ ]+vgatherqps 0x7b\(%rbp,%zmm16,8\),%ymm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 90 84 cd 7b 00 00 00[ ]+vpgatherdd 0x7b\(%rbp,%zmm17,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 90 84 c5 7b 00 00 00[ ]+vpgatherdd 0x7b\(%rbp,%zmm16,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 90 84 cd 7b 00 00 00[ ]+vpgatherdq 0x7b\(%rbp,%ymm17,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 90 84 c5 7b 00 00 00[ ]+vpgatherdq 0x7b\(%rbp,%ymm16,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 91 84 cd 7b 00 00 00[ ]+vpgatherqd 0x7b\(%rbp,%zmm17,8\),%ymm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 91 84 c5 7b 00 00 00[ ]+vpgatherqd 0x7b\(%rbp,%zmm16,8\),%ymm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 91 84 cd 7b 00 00 00[ ]+vpgatherqq 0x7b\(%rbp,%zmm17,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 91 84 c5 7b 00 00 00[ ]+vpgatherqq 0x7b\(%rbp,%zmm16,8\),%zmm16\{%k1\} +#pass diff --git a/gas/testsuite/gas/i386/x86-64-vgather-check-none.s b/gas/testsuite/gas/i386/x86-64-vgather-check-none.s new file mode 100644 @@ -1462557,10 +1470595,10 @@ index 0000000..42d0002 +.include "x86-64-vgather-check.s" diff --git a/gas/testsuite/gas/i386/x86-64-vgather-check-warn.d b/gas/testsuite/gas/i386/x86-64-vgather-check-warn.d new file mode 100644 -index 0000000..33846d2 +index 0000000..3d7a249 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-vgather-check-warn.d -@@ -0,0 +1,18 @@ +@@ -0,0 +1,36 @@ +#source: x86-64-vgather-check.s +#stderr: x86-64-vgather-check-warn.e +#objdump: -dw @@ -1462578,23 +1470616,49 @@ index 0000000..33846d2 +[ ]*[a-f0-9]+:[ ]+c4 e2 31 92 04 88[ ]+vgatherdps %xmm9,\(%rax,%xmm1,4\),%xmm0 +[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 0c c8[ ]+vgatherdps %xmm2,\(%rax,%xmm1,8\),%xmm1 +[ ]*[a-f0-9]+:[ ]+c4 62 69 92 0c c8[ ]+vgatherdps %xmm2,\(%rax,%xmm1,8\),%xmm9 ++ ++000000000000002a : ++[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 92 84 cd 7b 00 00 00[ ]+vgatherdpd 0x7b\(%rbp,%ymm17,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 92 84 c5 7b 00 00 00[ ]+vgatherdpd 0x7b\(%rbp,%ymm16,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 92 84 cd 7b 00 00 00[ ]+vgatherdps 0x7b\(%rbp,%zmm17,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 92 84 c5 7b 00 00 00[ ]+vgatherdps 0x7b\(%rbp,%zmm16,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 93 84 cd 7b 00 00 00[ ]+vgatherqpd 0x7b\(%rbp,%zmm17,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 93 84 c5 7b 00 00 00[ ]+vgatherqpd 0x7b\(%rbp,%zmm16,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 93 84 cd 7b 00 00 00[ ]+vgatherqps 0x7b\(%rbp,%zmm17,8\),%ymm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 93 84 c5 7b 00 00 00[ ]+vgatherqps 0x7b\(%rbp,%zmm16,8\),%ymm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 90 84 cd 7b 00 00 00[ ]+vpgatherdd 0x7b\(%rbp,%zmm17,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 90 84 c5 7b 00 00 00[ ]+vpgatherdd 0x7b\(%rbp,%zmm16,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 90 84 cd 7b 00 00 00[ ]+vpgatherdq 0x7b\(%rbp,%ymm17,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 90 84 c5 7b 00 00 00[ ]+vpgatherdq 0x7b\(%rbp,%ymm16,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 91 84 cd 7b 00 00 00[ ]+vpgatherqd 0x7b\(%rbp,%zmm17,8\),%ymm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 91 84 c5 7b 00 00 00[ ]+vpgatherqd 0x7b\(%rbp,%zmm16,8\),%ymm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 91 84 cd 7b 00 00 00[ ]+vpgatherqq 0x7b\(%rbp,%zmm17,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 91 84 c5 7b 00 00 00[ ]+vpgatherqq 0x7b\(%rbp,%zmm16,8\),%zmm16\{%k1\} +#pass diff --git a/gas/testsuite/gas/i386/x86-64-vgather-check-warn.e b/gas/testsuite/gas/i386/x86-64-vgather-check-warn.e new file mode 100644 -index 0000000..24e6a57 +index 0000000..b17f423 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-vgather-check-warn.e -@@ -0,0 +1,4 @@ +@@ -0,0 +1,12 @@ +.*: Assembler messages: +.*:6: Warning: .* +.*:8: Warning: .* +.*:10: Warning: .* ++.*:15: Warning: .* ++.*:17: Warning: .* ++.*:19: Warning: .* ++.*:21: Warning: .* ++.*:23: Warning: .* ++.*:25: Warning: .* ++.*:27: Warning: .* ++.*:29: Warning: .* diff --git a/gas/testsuite/gas/i386/x86-64-vgather-check.d b/gas/testsuite/gas/i386/x86-64-vgather-check.d new file mode 100644 -index 0000000..bd8ce57 +index 0000000..d51f670 --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-vgather-check.d -@@ -0,0 +1,17 @@ +@@ -0,0 +1,35 @@ +#as: -moperand-check=none +#objdump: -dw +#name: x86-64 vgather check (-moperand-check=none) @@ -1462611,13 +1470675,31 @@ index 0000000..bd8ce57 +[ ]*[a-f0-9]+:[ ]+c4 e2 31 92 04 88[ ]+vgatherdps %xmm9,\(%rax,%xmm1,4\),%xmm0 +[ ]*[a-f0-9]+:[ ]+c4 e2 69 92 0c c8[ ]+vgatherdps %xmm2,\(%rax,%xmm1,8\),%xmm1 +[ ]*[a-f0-9]+:[ ]+c4 62 69 92 0c c8[ ]+vgatherdps %xmm2,\(%rax,%xmm1,8\),%xmm9 ++ ++000000000000002a : ++[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 92 84 cd 7b 00 00 00[ ]+vgatherdpd 0x7b\(%rbp,%ymm17,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 92 84 c5 7b 00 00 00[ ]+vgatherdpd 0x7b\(%rbp,%ymm16,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 92 84 cd 7b 00 00 00[ ]+vgatherdps 0x7b\(%rbp,%zmm17,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 92 84 c5 7b 00 00 00[ ]+vgatherdps 0x7b\(%rbp,%zmm16,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 93 84 cd 7b 00 00 00[ ]+vgatherqpd 0x7b\(%rbp,%zmm17,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 93 84 c5 7b 00 00 00[ ]+vgatherqpd 0x7b\(%rbp,%zmm16,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 93 84 cd 7b 00 00 00[ ]+vgatherqps 0x7b\(%rbp,%zmm17,8\),%ymm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 93 84 c5 7b 00 00 00[ ]+vgatherqps 0x7b\(%rbp,%zmm16,8\),%ymm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 90 84 cd 7b 00 00 00[ ]+vpgatherdd 0x7b\(%rbp,%zmm17,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 90 84 c5 7b 00 00 00[ ]+vpgatherdd 0x7b\(%rbp,%zmm16,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 90 84 cd 7b 00 00 00[ ]+vpgatherdq 0x7b\(%rbp,%ymm17,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 90 84 c5 7b 00 00 00[ ]+vpgatherdq 0x7b\(%rbp,%ymm16,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 91 84 cd 7b 00 00 00[ ]+vpgatherqd 0x7b\(%rbp,%zmm17,8\),%ymm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 7d 41 91 84 c5 7b 00 00 00[ ]+vpgatherqd 0x7b\(%rbp,%zmm16,8\),%ymm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 91 84 cd 7b 00 00 00[ ]+vpgatherqq 0x7b\(%rbp,%zmm17,8\),%zmm16\{%k1\} ++[ ]+[a-f0-9]+:[ ]+62 e2 fd 41 91 84 c5 7b 00 00 00[ ]+vpgatherqq 0x7b\(%rbp,%zmm16,8\),%zmm16\{%k1\} +#pass diff --git a/gas/testsuite/gas/i386/x86-64-vgather-check.s b/gas/testsuite/gas/i386/x86-64-vgather-check.s new file mode 100644 -index 0000000..43b058b +index 0000000..9d5872c --- /dev/null +++ b/gas/testsuite/gas/i386/x86-64-vgather-check.s -@@ -0,0 +1,11 @@ +@@ -0,0 +1,29 @@ +# Check vgather instructions + + .text @@ -1462629,6 +1470711,24 @@ index 0000000..43b058b + vgatherdps %xmm9,(%rax,%xmm1,4),%xmm0 + vgatherdps %xmm2,(%rax,%xmm1,8),%xmm1 + vgatherdps %xmm2,(%rax,%xmm1,8),%xmm9 ++ ++avx512vgather: ++ vgatherdpd 123(%rbp,%ymm17,8), %zmm16{%k1} ++ vgatherdpd 123(%rbp,%ymm16,8), %zmm16{%k1} ++ vgatherdps 123(%rbp,%zmm17,8), %zmm16{%k1} ++ vgatherdps 123(%rbp,%zmm16,8), %zmm16{%k1} ++ vgatherqpd 123(%rbp,%zmm17,8), %zmm16{%k1} ++ vgatherqpd 123(%rbp,%zmm16,8), %zmm16{%k1} ++ vgatherqps 123(%rbp,%zmm17,8), %ymm16{%k1} ++ vgatherqps 123(%rbp,%zmm16,8), %ymm16{%k1} ++ vpgatherdd 123(%rbp,%zmm17,8), %zmm16{%k1} ++ vpgatherdd 123(%rbp,%zmm16,8), %zmm16{%k1} ++ vpgatherdq 123(%rbp,%ymm17,8), %zmm16{%k1} ++ vpgatherdq 123(%rbp,%ymm16,8), %zmm16{%k1} ++ vpgatherqd 123(%rbp,%zmm17,8), %ymm16{%k1} ++ vpgatherqd 123(%rbp,%zmm16,8), %ymm16{%k1} ++ vpgatherqq 123(%rbp,%zmm17,8), %zmm16{%k1} ++ vpgatherqq 123(%rbp,%zmm16,8), %zmm16{%k1} diff --git a/gas/testsuite/gas/i386/x86-64-vmfunc.d b/gas/testsuite/gas/i386/x86-64-vmfunc.d new file mode 100644 index 0000000..2af8761 @@ -1466614,6 +1474714,142 @@ index 0000000..e3316b2 + xsaveopt64 [r8] + xsaveopt64 [r8+rax*1] + xsaveopt64 [rax+r8*1] +diff --git a/gas/testsuite/gas/i386/x86-64-xsavec-intel.d b/gas/testsuite/gas/i386/x86-64-xsavec-intel.d +new file mode 100644 +index 0000000..cb5214d +--- /dev/null ++++ b/gas/testsuite/gas/i386/x86-64-xsavec-intel.d +@@ -0,0 +1,16 @@ ++#as: ++#objdump: -dw -Mintel ++#name: x86_64 XSAVEC insns (Intel disassembly) ++#source: x86-64-xsavec.s ++ ++.*: +file format .* ++ ++ ++Disassembly of section \.text: ++ ++0+ <_start>: ++[ ]*[a-f0-9]+:[ ]*48 0f c7 21[ ]*xsavec64 \[rcx\] ++[ ]*[a-f0-9]+:[ ]*4a 0f c7 a4 f0 23 01 00 00[ ]*xsavec64 \[rax\+r14\*8\+0x123\] ++[ ]*[a-f0-9]+:[ ]*48 0f c7 21[ ]*xsavec64 \[rcx\] ++[ ]*[a-f0-9]+:[ ]*4a 0f c7 a4 f0 34 12 00 00[ ]*xsavec64 \[rax\+r14\*8\+0x1234\] ++#pass +diff --git a/gas/testsuite/gas/i386/x86-64-xsavec.d b/gas/testsuite/gas/i386/x86-64-xsavec.d +new file mode 100644 +index 0000000..939aef8 +--- /dev/null ++++ b/gas/testsuite/gas/i386/x86-64-xsavec.d +@@ -0,0 +1,16 @@ ++#as: ++#objdump: -dw ++#name: x86_64 XSAVEC insns ++#source: x86-64-xsavec.s ++ ++.*: +file format .* ++ ++ ++Disassembly of section \.text: ++ ++0+ <_start>: ++[ ]*[a-f0-9]+:[ ]*48 0f c7 21[ ]*xsavec64 \(%rcx\) ++[ ]*[a-f0-9]+:[ ]*4a 0f c7 a4 f0 23 01 00 00[ ]*xsavec64 0x123\(%rax,%r14,8\) ++[ ]*[a-f0-9]+:[ ]*48 0f c7 21[ ]*xsavec64 \(%rcx\) ++[ ]*[a-f0-9]+:[ ]*4a 0f c7 a4 f0 34 12 00 00[ ]*xsavec64 0x1234\(%rax,%r14,8\) ++#pass +diff --git a/gas/testsuite/gas/i386/x86-64-xsavec.s b/gas/testsuite/gas/i386/x86-64-xsavec.s +new file mode 100644 +index 0000000..7d446d0 +--- /dev/null ++++ b/gas/testsuite/gas/i386/x86-64-xsavec.s +@@ -0,0 +1,12 @@ ++# Check 64bit XSAVEC instructions ++ ++ .allow_index_reg ++ .text ++_start: ++ ++ xsavec64 (%rcx) # XSAVEC ++ xsavec64 0x123(%rax,%r14,8) # XSAVEC ++ ++ .intel_syntax noprefix ++ xsavec64 [rcx] # XSAVEC ++ xsavec64 [rax+r14*8+0x1234] # XSAVEC +diff --git a/gas/testsuite/gas/i386/x86-64-xsaves-intel.d b/gas/testsuite/gas/i386/x86-64-xsaves-intel.d +new file mode 100644 +index 0000000..dde379c +--- /dev/null ++++ b/gas/testsuite/gas/i386/x86-64-xsaves-intel.d +@@ -0,0 +1,20 @@ ++#as: ++#objdump: -dw -Mintel ++#name: x86_64 XSAVES insns (Intel disassembly) ++#source: x86-64-xsaves.s ++ ++.*: +file format .* ++ ++ ++Disassembly of section \.text: ++ ++0+ <_start>: ++[ ]*[a-f0-9]+:[ ]*48 0f c7 29[ ]*xsaves64 \[rcx\] ++[ ]*[a-f0-9]+:[ ]*4a 0f c7 ac f0 23 01 00 00[ ]*xsaves64 \[rax\+r14\*8\+0x123\] ++[ ]*[a-f0-9]+:[ ]*48 0f c7 19[ ]*xrstors64 \[rcx\] ++[ ]*[a-f0-9]+:[ ]*4a 0f c7 9c f0 23 01 00 00[ ]*xrstors64 \[rax\+r14\*8\+0x123\] ++[ ]*[a-f0-9]+:[ ]*48 0f c7 29[ ]*xsaves64 \[rcx\] ++[ ]*[a-f0-9]+:[ ]*4a 0f c7 ac f0 34 12 00 00[ ]*xsaves64 \[rax\+r14\*8\+0x1234\] ++[ ]*[a-f0-9]+:[ ]*48 0f c7 19[ ]*xrstors64 \[rcx\] ++[ ]*[a-f0-9]+:[ ]*4a 0f c7 9c f0 34 12 00 00[ ]*xrstors64 \[rax\+r14\*8\+0x1234\] ++#pass +diff --git a/gas/testsuite/gas/i386/x86-64-xsaves.d b/gas/testsuite/gas/i386/x86-64-xsaves.d +new file mode 100644 +index 0000000..e715529 +--- /dev/null ++++ b/gas/testsuite/gas/i386/x86-64-xsaves.d +@@ -0,0 +1,20 @@ ++#as: ++#objdump: -dw ++#name: x86_64 XSAVES insns ++#source: x86-64-xsaves.s ++ ++.*: +file format .* ++ ++ ++Disassembly of section \.text: ++ ++0+ <_start>: ++[ ]*[a-f0-9]+:[ ]*48 0f c7 29[ ]*xsaves64 \(%rcx\) ++[ ]*[a-f0-9]+:[ ]*4a 0f c7 ac f0 23 01 00 00[ ]*xsaves64 0x123\(%rax,%r14,8\) ++[ ]*[a-f0-9]+:[ ]*48 0f c7 19[ ]*xrstors64 \(%rcx\) ++[ ]*[a-f0-9]+:[ ]*4a 0f c7 9c f0 23 01 00 00[ ]*xrstors64 0x123\(%rax,%r14,8\) ++[ ]*[a-f0-9]+:[ ]*48 0f c7 29[ ]*xsaves64 \(%rcx\) ++[ ]*[a-f0-9]+:[ ]*4a 0f c7 ac f0 34 12 00 00[ ]*xsaves64 0x1234\(%rax,%r14,8\) ++[ ]*[a-f0-9]+:[ ]*48 0f c7 19[ ]*xrstors64 \(%rcx\) ++[ ]*[a-f0-9]+:[ ]*4a 0f c7 9c f0 34 12 00 00[ ]*xrstors64 0x1234\(%rax,%r14,8\) ++#pass +diff --git a/gas/testsuite/gas/i386/x86-64-xsaves.s b/gas/testsuite/gas/i386/x86-64-xsaves.s +new file mode 100644 +index 0000000..f65b51c +--- /dev/null ++++ b/gas/testsuite/gas/i386/x86-64-xsaves.s +@@ -0,0 +1,16 @@ ++# Check 64bit XSAVES instructions ++ ++ .allow_index_reg ++ .text ++_start: ++ ++ xsaves64 (%rcx) # XSAVES ++ xsaves64 0x123(%rax,%r14,8) # XSAVES ++ xrstors64 (%rcx) # XSAVES ++ xrstors64 0x123(%rax,%r14,8) # XSAVES ++ ++ .intel_syntax noprefix ++ xsaves64 [rcx] # XSAVES ++ xsaves64 [rax+r14*8+0x1234] # XSAVES ++ xrstors64 [rcx] # XSAVES ++ xrstors64 [rax+r14*8+0x1234] # XSAVES diff --git a/gas/testsuite/gas/i386/x86_64.d b/gas/testsuite/gas/i386/x86_64.d new file mode 100644 index 0000000..6fed19b @@ -1470922,9 +1479158,145 @@ index 0000000..37c7d50 + xrstor [ecx] + xsave [ecx] + xsaveopt [ecx] +diff --git a/gas/testsuite/gas/i386/xsavec-intel.d b/gas/testsuite/gas/i386/xsavec-intel.d +new file mode 100644 +index 0000000..3751f10 +--- /dev/null ++++ b/gas/testsuite/gas/i386/xsavec-intel.d +@@ -0,0 +1,16 @@ ++#as: ++#objdump: -dw -Mintel ++#name: i386 XSAVEC insns (Intel disassembly) ++#source: xsavec.s ++ ++.*: +file format .* ++ ++ ++Disassembly of section \.text: ++ ++00000000 <_start>: ++[ ]*[a-f0-9]+:[ ]*0f c7 21[ ]*xsavec \[ecx\] ++[ ]*[a-f0-9]+:[ ]*0f c7 a4 f4 c0 1d fe ff[ ]*xsavec \[esp\+esi\*8-0x1e240\] ++[ ]*[a-f0-9]+:[ ]*0f c7 21[ ]*xsavec \[ecx\] ++[ ]*[a-f0-9]+:[ ]*0f c7 a4 f4 c0 1d fe ff[ ]*xsavec \[esp\+esi\*8-0x1e240\] ++#pass +diff --git a/gas/testsuite/gas/i386/xsavec.d b/gas/testsuite/gas/i386/xsavec.d +new file mode 100644 +index 0000000..b0d9ee1 +--- /dev/null ++++ b/gas/testsuite/gas/i386/xsavec.d +@@ -0,0 +1,16 @@ ++#as: ++#objdump: -dw ++#name: i386 XSAVEC insns ++#source: xsavec.s ++ ++.*: +file format .* ++ ++ ++Disassembly of section \.text: ++ ++00000000 <_start>: ++[ ]*[a-f0-9]+:[ ]*0f c7 21[ ]*xsavec \(%ecx\) ++[ ]*[a-f0-9]+:[ ]*0f c7 a4 f4 c0 1d fe ff[ ]*xsavec -0x1e240\(%esp,%esi,8\) ++[ ]*[a-f0-9]+:[ ]*0f c7 21[ ]*xsavec \(%ecx\) ++[ ]*[a-f0-9]+:[ ]*0f c7 a4 f4 c0 1d fe ff[ ]*xsavec -0x1e240\(%esp,%esi,8\) ++#pass +diff --git a/gas/testsuite/gas/i386/xsavec.s b/gas/testsuite/gas/i386/xsavec.s +new file mode 100644 +index 0000000..93415d8 +--- /dev/null ++++ b/gas/testsuite/gas/i386/xsavec.s +@@ -0,0 +1,12 @@ ++# Check 32bit XSAVEC instructions ++ ++ .allow_index_reg ++ .text ++_start: ++ ++ xsavec (%ecx) # XSAVEC ++ xsavec -123456(%esp,%esi,8) # XSAVEC ++ ++ .intel_syntax noprefix ++ xsavec [ecx] # XSAVEC ++ xsavec [esp+esi*8-123456] # XSAVEC +diff --git a/gas/testsuite/gas/i386/xsaves-intel.d b/gas/testsuite/gas/i386/xsaves-intel.d +new file mode 100644 +index 0000000..edb3d57 +--- /dev/null ++++ b/gas/testsuite/gas/i386/xsaves-intel.d +@@ -0,0 +1,20 @@ ++#as: ++#objdump: -dw -Mintel ++#name: i386 XSAVES insns (Intel disassembly) ++#source: xsaves.s ++ ++.*: +file format .* ++ ++ ++Disassembly of section \.text: ++ ++00000000 <_start>: ++[ ]*[a-f0-9]+:[ ]*0f c7 29[ ]*xsaves \[ecx\] ++[ ]*[a-f0-9]+:[ ]*0f c7 ac f4 c0 1d fe ff[ ]*xsaves \[esp\+esi\*8-0x1e240\] ++[ ]*[a-f0-9]+:[ ]*0f c7 19[ ]*xrstors \[ecx\] ++[ ]*[a-f0-9]+:[ ]*0f c7 9c f4 c0 1d fe ff[ ]*xrstors \[esp\+esi\*8-0x1e240\] ++[ ]*[a-f0-9]+:[ ]*0f c7 29[ ]*xsaves \[ecx\] ++[ ]*[a-f0-9]+:[ ]*0f c7 ac f4 c0 1d fe ff[ ]*xsaves \[esp\+esi\*8-0x1e240\] ++[ ]*[a-f0-9]+:[ ]*0f c7 19[ ]*xrstors \[ecx\] ++[ ]*[a-f0-9]+:[ ]*0f c7 9c f4 c0 1d fe ff[ ]*xrstors \[esp\+esi\*8-0x1e240\] ++#pass +diff --git a/gas/testsuite/gas/i386/xsaves.d b/gas/testsuite/gas/i386/xsaves.d +new file mode 100644 +index 0000000..6984b79 +--- /dev/null ++++ b/gas/testsuite/gas/i386/xsaves.d +@@ -0,0 +1,20 @@ ++#as: ++#objdump: -dw ++#name: i386 XSAVES insns ++#source: xsaves.s ++ ++.*: +file format .* ++ ++ ++Disassembly of section \.text: ++ ++00000000 <_start>: ++[ ]*[a-f0-9]+:[ ]*0f c7 29[ ]*xsaves \(%ecx\) ++[ ]*[a-f0-9]+:[ ]*0f c7 ac f4 c0 1d fe ff[ ]*xsaves -0x1e240\(%esp,%esi,8\) ++[ ]*[a-f0-9]+:[ ]*0f c7 19[ ]*xrstors \(%ecx\) ++[ ]*[a-f0-9]+:[ ]*0f c7 9c f4 c0 1d fe ff[ ]*xrstors -0x1e240\(%esp,%esi,8\) ++[ ]*[a-f0-9]+:[ ]*0f c7 29[ ]*xsaves \(%ecx\) ++[ ]*[a-f0-9]+:[ ]*0f c7 ac f4 c0 1d fe ff[ ]*xsaves -0x1e240\(%esp,%esi,8\) ++[ ]*[a-f0-9]+:[ ]*0f c7 19[ ]*xrstors \(%ecx\) ++[ ]*[a-f0-9]+:[ ]*0f c7 9c f4 c0 1d fe ff[ ]*xrstors -0x1e240\(%esp,%esi,8\) ++#pass +diff --git a/gas/testsuite/gas/i386/xsaves.s b/gas/testsuite/gas/i386/xsaves.s +new file mode 100644 +index 0000000..697b3dd +--- /dev/null ++++ b/gas/testsuite/gas/i386/xsaves.s +@@ -0,0 +1,16 @@ ++# Check 32bit XSAVES instructions ++ ++ .allow_index_reg ++ .text ++_start: ++ ++ xsaves (%ecx) # XSAVES ++ xsaves -123456(%esp,%esi,8) # XSAVES ++ xrstors (%ecx) # XSAVES ++ xrstors -123456(%esp,%esi,8) # XSAVES ++ ++ .intel_syntax noprefix ++ xsaves [ecx] # XSAVES ++ xsaves [esp+esi*8-123456] # XSAVES ++ xrstors [ecx] # XSAVES ++ xrstors [esp+esi*8-123456] # XSAVES diff --git a/gas/testsuite/gas/i860/README.i860 b/gas/testsuite/gas/i860/README.i860 new file mode 100644 -index 0000000..57f6526 +index 0000000..41693d5 --- /dev/null +++ b/gas/testsuite/gas/i860/README.i860 @@ -0,0 +1,39 @@ @@ -1470962,7 +1479334,7 @@ index 0000000..57f6526 +Known testsuite failures: + - none. + -+Copyright (C) 2012 Free Software Foundation, Inc. ++Copyright (C) 2012-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -1473830,12 +1482202,11 @@ index 0000000..e73dde6 + diff --git a/gas/testsuite/gas/i860/i860.exp b/gas/testsuite/gas/i860/i860.exp new file mode 100644 -index 0000000..e77d45f +index 0000000..aa1b4e6 --- /dev/null +++ b/gas/testsuite/gas/i860/i860.exp -@@ -0,0 +1,62 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,61 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1479883,7 +1488254,7 @@ index 0000000..ed7f64f + .endp _foo# diff --git a/gas/testsuite/gas/ia64/group-2.d b/gas/testsuite/gas/ia64/group-2.d new file mode 100644 -index 0000000..bf7255d +index 0000000..3b1579c --- /dev/null +++ b/gas/testsuite/gas/ia64/group-2.d @@ -0,0 +1,41 @@ @@ -1479913,7 +1488284,7 @@ index 0000000..bf7255d + \[ 7\] \.gnu\.linkonce\.ia6 IA_64_UNWIND 0000000000000000 00000060 + 0000000000000018 0000000000000000 ALG 5 5 8 + \[ 8\] \.rela\.gnu\.linkonc RELA 0000000000000000 000004e0 -+ 0000000000000048 0000000000000018 10 7 8 ++ 0000000000000048 0000000000000018 I 10 7 8 + \[ 9\] \.shstrtab STRTAB 0000000000000000 00000078 + 0000000000000081 0000000000000000 0 0 1 + \[10\] \.symtab SYMTAB 0000000000000000 00000400 @@ -1479976,12 +1488347,11 @@ index 0000000..75f7a65 + hint.b 0x1ffff diff --git a/gas/testsuite/gas/ia64/ia64.exp b/gas/testsuite/gas/ia64/ia64.exp new file mode 100644 -index 0000000..dffd56c +index 0000000..1634d14 --- /dev/null +++ b/gas/testsuite/gas/ia64/ia64.exp -@@ -0,0 +1,119 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,118 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1498266,7 +1506636,7 @@ index 0000000..3958c71 +#pass diff --git a/gas/testsuite/gas/ia64/xdata.d b/gas/testsuite/gas/ia64/xdata.d new file mode 100644 -index 0000000..e56d24e +index 0000000..dc23b78 --- /dev/null +++ b/gas/testsuite/gas/ia64/xdata.d @@ -0,0 +1,47 @@ @@ -1498297,7 +1506667,7 @@ index 0000000..e56d24e + \[ 8\] "\.xdata5" PROGBITS 0000000000000000 [[:xdigit:]]+ + 0000000000000020 0000000000000000 A 0 0 16 + \[ 9\] \.rela"\.xdata5" RELA 0000000000000000 [[:xdigit:]]+ -+ 0000000000000030 0000000000000018 17 8 8 ++ 0000000000000030 0000000000000018 I 17 8 8 + \[10\] \.xreal\\1 PROGBITS 0000000000000000 [[:xdigit:]]+ + 0000000000000008 0000000000000000 A 0 0 4 + \[11\] \.xreal\+2 PROGBITS 0000000000000000 [[:xdigit:]]+ @@ -1498370,12 +1506740,11 @@ index 0000000..6929405 +.xstringz ".xstr{2}", "xyz" diff --git a/gas/testsuite/gas/ieee-fp/x930509a.exp b/gas/testsuite/gas/ieee-fp/x930509a.exp new file mode 100644 -index 0000000..2667d7e +index 0000000..7f36149 --- /dev/null +++ b/gas/testsuite/gas/ieee-fp/x930509a.exp -@@ -0,0 +1,44 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,43 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1498879,12 +1507248,11 @@ index 0000000..c7178cc + 240: 4f e0 00 00 pkrlr30 r0,0x0,0x0 diff --git a/gas/testsuite/gas/iq2000/allinsn.exp b/gas/testsuite/gas/iq2000/allinsn.exp new file mode 100644 -index 0000000..69b720d +index 0000000..909446e --- /dev/null +++ b/gas/testsuite/gas/iq2000/allinsn.exp -@@ -0,0 +1,22 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,21 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1499600,12 +1507968,11 @@ index 0000000..ecbacb7 + add %8, %1, %9 diff --git a/gas/testsuite/gas/iq2000/load-hazards.exp b/gas/testsuite/gas/iq2000/load-hazards.exp new file mode 100644 -index 0000000..7ffab0e +index 0000000..47fea36 --- /dev/null +++ b/gas/testsuite/gas/iq2000/load-hazards.exp -@@ -0,0 +1,80 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,79 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1499732,12 +1508099,11 @@ index 0000000..119622b +test4: sleep diff --git a/gas/testsuite/gas/iq2000/odd-ldw.exp b/gas/testsuite/gas/iq2000/odd-ldw.exp new file mode 100644 -index 0000000..bff4add +index 0000000..a6d731e --- /dev/null +++ b/gas/testsuite/gas/iq2000/odd-ldw.exp -@@ -0,0 +1,23 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,22 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1499761,12 +1508127,11 @@ index 0000000..bff4add +} diff --git a/gas/testsuite/gas/iq2000/odd-sdw.exp b/gas/testsuite/gas/iq2000/odd-sdw.exp new file mode 100644 -index 0000000..25d56c9 +index 0000000..cffeb7d --- /dev/null +++ b/gas/testsuite/gas/iq2000/odd-sdw.exp -@@ -0,0 +1,23 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,22 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1499822,12 +1508187,11 @@ index 0000000..50d829b + sdw %1, foodata(%12) diff --git a/gas/testsuite/gas/iq2000/yield.exp b/gas/testsuite/gas/iq2000/yield.exp new file mode 100644 -index 0000000..ad6d21e +index 0000000..b0111c0 --- /dev/null +++ b/gas/testsuite/gas/iq2000/yield.exp -@@ -0,0 +1,56 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,55 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1500062,12 +1508426,11 @@ index 0000000..b3bd2d9 +foo: nop diff --git a/gas/testsuite/gas/lm32/all.exp b/gas/testsuite/gas/lm32/all.exp new file mode 100644 -index 0000000..ac237a8 +index 0000000..ed7c2da --- /dev/null +++ b/gas/testsuite/gas/lm32/all.exp -@@ -0,0 +1,23 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,22 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1500670,6 +1509033,37 @@ index 0000000..7543be4 + { .mii; nop 0; nop 0; nop 0 ;; } + .loc 1 7 discriminator 1 + { .mii; nop 0; nop 0; nop 0 ;; } +diff --git a/gas/testsuite/gas/lns/lns-common-1-or1k.s b/gas/testsuite/gas/lns/lns-common-1-or1k.s +new file mode 100644 +index 0000000..b91b681 +--- /dev/null ++++ b/gas/testsuite/gas/lns/lns-common-1-or1k.s +@@ -0,0 +1,25 @@ ++ .file 1 "foo.c" ++ .loc 1 1 ++ l.nop ++ l.nop ++ .loc 1 2 3 ++ l.nop ++ l.nop ++ .loc 1 3 prologue_end ++ l.nop ++ l.nop ++ .loc 1 4 0 epilogue_begin ++ l.nop ++ l.nop ++ .loc 1 5 isa 1 basic_block ++ l.nop ++ l.nop ++ .loc 1 6 is_stmt 0 ++ l.nop ++ l.nop ++ .loc 1 7 is_stmt 1 ++ l.nop ++ l.nop ++ .loc 1 7 discriminator 1 ++ l.nop ++ l.nop diff --git a/gas/testsuite/gas/lns/lns-common-1.d b/gas/testsuite/gas/lns/lns-common-1.d new file mode 100644 index 0000000..81a57ca @@ -1500820,12 +1509214,11 @@ index 0000000..9fea2fe +.Llabel: diff --git a/gas/testsuite/gas/lns/lns.exp b/gas/testsuite/gas/lns/lns.exp new file mode 100644 -index 0000000..8f81998 +index 0000000..7dbd10e --- /dev/null +++ b/gas/testsuite/gas/lns/lns.exp @@ -0,0 +1,51 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1500855,7 +1509248,6 @@ index 0000000..8f81998 + ![istarget i370-*-*] + && ![istarget i960-*-*] + && ![istarget mcore-*-*] -+ && ![istarget or32-*-*] + && ![istarget rx-*-*] + && ![istarget s390*-*-*] +} { @@ -1500871,6 +1509263,8 @@ index 0000000..8f81998 + run_dump_test "lns-big-delta" + } elseif { [istarget ia64*-*-*] } { + run_dump_test "lns-common-1" { { source "lns-common-1-ia64.s" } } ++ } elseif { [istarget or1k*-*-*] } { ++ run_dump_test "lns-common-1" { { source "lns-common-1-or1k.s" } } + } else { + run_dump_test "lns-common-1" + } @@ -1501257,12 +1509651,11 @@ index 0000000..18c80c3 + 1e4: 2d ef f0 00 pop fp \|\| nop diff --git a/gas/testsuite/gas/m32r/allinsn.exp b/gas/testsuite/gas/m32r/allinsn.exp new file mode 100644 -index 0000000..401f791 +index 0000000..d60a58a --- /dev/null +++ b/gas/testsuite/gas/m32r/allinsn.exp -@@ -0,0 +1,22 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,21 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1501792,12 +1510185,11 @@ index 0000000..86b4569 + pop fp diff --git a/gas/testsuite/gas/m32r/error.exp b/gas/testsuite/gas/m32r/error.exp new file mode 100644 -index 0000000..7bb6740 +index 0000000..07e7830 --- /dev/null +++ b/gas/testsuite/gas/m32r/error.exp -@@ -0,0 +1,34 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,33 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1502136,12 +1510528,11 @@ index 0000000..a17ed0f + c0: 50 01 e2 01 srli r0,#0x1 \|\| ldi r2,#1 diff --git a/gas/testsuite/gas/m32r/m32r2.exp b/gas/testsuite/gas/m32r/m32r2.exp new file mode 100644 -index 0000000..97c063d +index 0000000..332e606 --- /dev/null +++ b/gas/testsuite/gas/m32r/m32r2.exp -@@ -0,0 +1,23 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,22 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1502652,12 +1511043,11 @@ index 0000000..89b618b + 22c: 3d 7d 3d fd macwlo fp,fp -> macwlo fp,fp,a1 diff --git a/gas/testsuite/gas/m32r/m32rx.exp b/gas/testsuite/gas/m32r/m32rx.exp new file mode 100644 -index 0000000..f67fddc +index 0000000..5683549 --- /dev/null +++ b/gas/testsuite/gas/m32r/m32rx.exp -@@ -0,0 +1,24 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,23 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1503531,12 +1511921,11 @@ index 0000000..a880a1b + 40: R_M32R_26_PLTREL func diff --git a/gas/testsuite/gas/m32r/pic.exp b/gas/testsuite/gas/m32r/pic.exp new file mode 100644 -index 0000000..94e2de5 +index 0000000..aeed14e --- /dev/null +++ b/gas/testsuite/gas/m32r/pic.exp -@@ -0,0 +1,23 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,22 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1503806,12 +1512195,11 @@ index 0000000..abfe136 + diff --git a/gas/testsuite/gas/m32r/rel32.exp b/gas/testsuite/gas/m32r/rel32.exp new file mode 100644 -index 0000000..a2beaf8 +index 0000000..97bac54 --- /dev/null +++ b/gas/testsuite/gas/m32r/rel32.exp -@@ -0,0 +1,23 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,22 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1507562,12 +1515950,11 @@ index 0000000..568d8a7 + ; END diff --git a/gas/testsuite/gas/m68hc11/m68hc11.exp b/gas/testsuite/gas/m68hc11/m68hc11.exp new file mode 100644 -index 0000000..d03cd25 +index 0000000..c70df38 --- /dev/null +++ b/gas/testsuite/gas/m68hc11/m68hc11.exp -@@ -0,0 +1,227 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,226 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1509400,12 +1517787,11 @@ index 0000000..e4e757f +bb = 10240 diff --git a/gas/testsuite/gas/m68k-coff/gas.exp b/gas/testsuite/gas/m68k-coff/gas.exp new file mode 100644 -index 0000000..dd67727 +index 0000000..8e7f24c --- /dev/null +++ b/gas/testsuite/gas/m68k-coff/gas.exp -@@ -0,0 +1,32 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,31 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1509536,12 +1517922,11 @@ index 0000000..cc015f2 + LV14 = 0 diff --git a/gas/testsuite/gas/m68k/all.exp b/gas/testsuite/gas/m68k/all.exp new file mode 100644 -index 0000000..4804efe +index 0000000..b9c80c4 --- /dev/null +++ b/gas/testsuite/gas/m68k/all.exp -@@ -0,0 +1,127 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,126 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1533981,12 +1542366,11 @@ index 0000000..586feec + .lcomm align_max, 8, 15 diff --git a/gas/testsuite/gas/mach-o/mach-o.exp b/gas/testsuite/gas/mach-o/mach-o.exp new file mode 100644 -index 0000000..e68edae +index 0000000..63b35b7 --- /dev/null +++ b/gas/testsuite/gas/mach-o/mach-o.exp -@@ -0,0 +1,37 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,36 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1536166,12 +1544550,11 @@ index 0000000..f37dd54 + diff --git a/gas/testsuite/gas/macros/macros.exp b/gas/testsuite/gas/macros/macros.exp new file mode 100644 -index 0000000..1253415 +index 0000000..e09f7da --- /dev/null +++ b/gas/testsuite/gas/macros/macros.exp -@@ -0,0 +1,98 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,97 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1537105,12 +1545488,11 @@ index 0000000..a53805b + 10a: 0f00 cmpne r0, r0 diff --git a/gas/testsuite/gas/mcore/allinsn.exp b/gas/testsuite/gas/mcore/allinsn.exp new file mode 100644 -index 0000000..ce29780 +index 0000000..7061369 --- /dev/null +++ b/gas/testsuite/gas/mcore/allinsn.exp -@@ -0,0 +1,22 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,21 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1538638,12 +1547020,11 @@ index 0000000..6171608 + ...: R_MEP_HI16U .text\+0x... diff --git a/gas/testsuite/gas/mep/allinsn.exp b/gas/testsuite/gas/mep/allinsn.exp new file mode 100644 -index 0000000..0098e26 +index 0000000..7d9e19a --- /dev/null +++ b/gas/testsuite/gas/mep/allinsn.exp -@@ -0,0 +1,25 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,24 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1541624,12 +1550005,11 @@ index 0000000..7c69985 + nop diff --git a/gas/testsuite/gas/mep/complex-relocs.exp b/gas/testsuite/gas/mep/complex-relocs.exp new file mode 100644 -index 0000000..13642f6 +index 0000000..eb46fda --- /dev/null +++ b/gas/testsuite/gas/mep/complex-relocs.exp -@@ -0,0 +1,59 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,58 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1633291,14 +1641671,13 @@ index 0000000..87129f7 + FLI SUBRE FX.6,FX.4,FX.2 diff --git a/gas/testsuite/gas/metag/metag.exp b/gas/testsuite/gas/metag/metag.exp new file mode 100644 -index 0000000..49469b1 +index 0000000..9ee2630 --- /dev/null +++ b/gas/testsuite/gas/metag/metag.exp -@@ -0,0 +1,43 @@ +@@ -0,0 +1,42 @@ +# Meta assembler testsuite + -+# Copyright 2013 -+# Free Software Foundation, Inc. ++# Copyright (C) 2013-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1633443,12 +1641822,11 @@ index 0000000..b454fdb + 40: 900001e2 swaph r0, r0 diff --git a/gas/testsuite/gas/microblaze/allinsn.exp b/gas/testsuite/gas/microblaze/allinsn.exp new file mode 100644 -index 0000000..20a7fe4 +index 0000000..9bd3ba4 --- /dev/null +++ b/gas/testsuite/gas/microblaze/allinsn.exp -@@ -0,0 +1,22 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,21 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1633534,12 +1641912,11 @@ index 0000000..ffe91ca + diff --git a/gas/testsuite/gas/microblaze/endian.exp b/gas/testsuite/gas/microblaze/endian.exp new file mode 100644 -index 0000000..325e396 +index 0000000..bd3500e --- /dev/null +++ b/gas/testsuite/gas/microblaze/endian.exp -@@ -0,0 +1,29 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,28 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1633838,12 +1642215,11 @@ index 0000000..571ffe1 + 20: 80000000 or r0, r0, r0 diff --git a/gas/testsuite/gas/microblaze/reloc_sym.exp b/gas/testsuite/gas/microblaze/reloc_sym.exp new file mode 100644 -index 0000000..44ee9ed +index 0000000..76c7a74 --- /dev/null +++ b/gas/testsuite/gas/microblaze/reloc_sym.exp -@@ -0,0 +1,44 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,43 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1633963,12 +1642339,11 @@ index 0000000..c2041fd + 8: 001ff800 add r0, r31, r31 diff --git a/gas/testsuite/gas/microblaze/special_reg.exp b/gas/testsuite/gas/microblaze/special_reg.exp new file mode 100644 -index 0000000..0a0d9ea +index 0000000..6fd096c --- /dev/null +++ b/gas/testsuite/gas/microblaze/special_reg.exp -@@ -0,0 +1,22 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,21 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1637679,6 +1646054,47 @@ index 0000000..62978d3 + +# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... + .space 8 +diff --git a/gas/testsuite/gas/mips/attr-gnu-abi-fp-1.d b/gas/testsuite/gas/mips/attr-gnu-abi-fp-1.d +new file mode 100644 +index 0000000..63eaf8d +--- /dev/null ++++ b/gas/testsuite/gas/mips/attr-gnu-abi-fp-1.d +@@ -0,0 +1,8 @@ ++#as: -32 ++#source: attr-gnu-abi-fp-1.s ++#readelf: -A ++#name: MIPS gnu_attribute Tag_GNU_MIPS_ABI_FP,1 ++ ++Attribute Section: gnu ++File Attributes ++ Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) +diff --git a/gas/testsuite/gas/mips/attr-gnu-abi-fp-1.s b/gas/testsuite/gas/mips/attr-gnu-abi-fp-1.s +new file mode 100644 +index 0000000..a96caaf +--- /dev/null ++++ b/gas/testsuite/gas/mips/attr-gnu-abi-fp-1.s +@@ -0,0 +1 @@ ++.gnu_attribute Tag_GNU_MIPS_ABI_FP,1 +diff --git a/gas/testsuite/gas/mips/attr-gnu-abi-msa-1.d b/gas/testsuite/gas/mips/attr-gnu-abi-msa-1.d +new file mode 100644 +index 0000000..4720029 +--- /dev/null ++++ b/gas/testsuite/gas/mips/attr-gnu-abi-msa-1.d +@@ -0,0 +1,7 @@ ++#source: attr-gnu-abi-msa-1.s ++#readelf: -A ++#name: MIPS gnu_attribute Tag_GNU_MIPS_ABI_MSA,1 ++ ++Attribute Section: gnu ++File Attributes ++ Tag_GNU_MIPS_ABI_MSA: 128-bit MSA +diff --git a/gas/testsuite/gas/mips/attr-gnu-abi-msa-1.s b/gas/testsuite/gas/mips/attr-gnu-abi-msa-1.s +new file mode 100644 +index 0000000..f22883e +--- /dev/null ++++ b/gas/testsuite/gas/mips/attr-gnu-abi-msa-1.s +@@ -0,0 +1 @@ ++.gnu_attribute Tag_GNU_MIPS_ABI_MSA,1 diff --git a/gas/testsuite/gas/mips/baddata1.l b/gas/testsuite/gas/mips/baddata1.l new file mode 100644 index 0000000..6d09cca @@ -1669777,75 +1678193,75 @@ index 0000000..32fea2e + diff --git a/gas/testsuite/gas/mips/loongson-3a-2.s b/gas/testsuite/gas/mips/loongson-3a-2.s new file mode 100644 -index 0000000..7a2a550 +index 0000000..c296b06 --- /dev/null +++ b/gas/testsuite/gas/mips/loongson-3a-2.s @@ -0,0 +1,65 @@ -+ .text -+ .set noreorder -+ -+ campi $2,$3 -+ campv $4,$5 -+ camwi $6,$7,$8 -+ ramri $9,$10 -+ -+ gsle $11,$12 -+ gsgt $13,$14 -+ -+ gslble $2,$3,$4 -+ gslbgt $5,$6,$7 -+ gslhle $8,$9,$10 -+ gslhgt $11,$12,$13 -+ gslwle $14,$15,$16 -+ gslwgt $17,$18,$19 -+ gsldle $20,$21,$22 -+ gsldgt $23,$24,$25 -+ gssble $2,$3,$4 -+ gssbgt $5,$6,$7 -+ gsshle $8,$9,$10 -+ gsshgt $11,$12,$13 -+ gsswle $14,$15,$16 -+ gsswgt $17,$18,$19 -+ gssdle $20,$21,$22 -+ gssdgt $23,$24,$25 -+ -+ gslwlec1 $f0,$2,$3 -+ gslwgtc1 $f1,$4,$5 -+ gsldlec1 $f2,$6,$7 -+ gsldgtc1 $f3,$8,$9 -+ gsswlec1 $f4,$10,$11 -+ gsswgtc1 $f5,$12,$13 -+ gssdlec1 $f6,$14,$15 -+ gssdgtc1 $f7,$16,$17 -+ -+ gslwlc1 $f8,0($18) -+ gslwrc1 $f9,1($19) -+ gsldlc1 $f10,2($20) -+ gsldrc1 $f11,3($21) -+ gsswlc1 $f12,4($22) -+ gsswrc1 $f13,5($23) -+ gssdlc1 $f14,6($24) -+ gssdrc1 $f15,7($25) -+ -+ gslbx $2,0($3,$4) -+ gslhx $5,-1($6,$7) -+ gslwx $8,-2($9,$10) -+ gsldx $11,-3($12,$13) -+ gssbx $14,-4($15,$16) -+ gsshx $17,-5($18,$19) -+ gsswx $20,-6($21,$22) -+ gssdx $23,-7($24,$25) -+ -+ gslwxc1 $f16,127($2,$3) -+ gsldxc1 $f17,-128($4,$5) -+ gsswxc1 $f18,127($6,$7) -+ gssdxc1 $f19,-128($8,$9) -+ -+ gslq $10,$11,4080($12) -+ gssq $13,$14,-4096($15) -+ gslqc1 $f20,$f21,4080($16) -+ gssqc1 $f22,$f23,-4096($17) -+ ++ .text ++ .set noreorder ++ ++ campi $2,$3 ++ campv $4,$5 ++ camwi $6,$7,$8 ++ ramri $9,$10 ++ ++ gsle $11,$12 ++ gsgt $13,$14 ++ ++ gslble $2,$3,$4 ++ gslbgt $5,$6,$7 ++ gslhle $8,$9,$10 ++ gslhgt $11,$12,$13 ++ gslwle $14,$15,$16 ++ gslwgt $17,$18,$19 ++ gsldle $20,$21,$22 ++ gsldgt $23,$24,$25 ++ gssble $2,$3,$4 ++ gssbgt $5,$6,$7 ++ gsshle $8,$9,$10 ++ gsshgt $11,$12,$13 ++ gsswle $14,$15,$16 ++ gsswgt $17,$18,$19 ++ gssdle $20,$21,$22 ++ gssdgt $23,$24,$25 ++ ++ gslwlec1 $f0,$2,$3 ++ gslwgtc1 $f1,$4,$5 ++ gsldlec1 $f2,$6,$7 ++ gsldgtc1 $f3,$8,$9 ++ gsswlec1 $f4,$10,$11 ++ gsswgtc1 $f5,$12,$13 ++ gssdlec1 $f6,$14,$15 ++ gssdgtc1 $f7,$16,$17 ++ ++ gslwlc1 $f8,0($18) ++ gslwrc1 $f9,1($19) ++ gsldlc1 $f10,2($20) ++ gsldrc1 $f11,3($21) ++ gsswlc1 $f12,4($22) ++ gsswrc1 $f13,5($23) ++ gssdlc1 $f14,6($24) ++ gssdrc1 $f15,7($25) ++ ++ gslbx $2,0($3,$4) ++ gslhx $5,-1($6,$7) ++ gslwx $8,-2($9,$10) ++ gsldx $11,-3($12,$13) ++ gssbx $14,-4($15,$16) ++ gsshx $17,-5($18,$19) ++ gsswx $20,-6($21,$22) ++ gssdx $23,-7($24,$25) ++ ++ gslwxc1 $f16,127($2,$3) ++ gsldxc1 $f17,-128($4,$5) ++ gsswxc1 $f18,127($6,$7) ++ gssdxc1 $f19,-128($8,$9) ++ ++ gslq $10,$11,4080($12) ++ gssq $13,$14,-4096($15) ++ gslqc1 $f20,$f21,4080($16) ++ gssqc1 $f22,$f23,-4096($17) ++ diff --git a/gas/testsuite/gas/mips/loongson-3a-3.d b/gas/testsuite/gas/mips/loongson-3a-3.d new file mode 100644 index 0000000..e242c5d @@ -1669877,232 +1678293,232 @@ index 0000000..24f427b +1: diff --git a/gas/testsuite/gas/mips/loongson-3a.d b/gas/testsuite/gas/mips/loongson-3a.d new file mode 100644 -index 0000000..cb28d65 +index 0000000..f0eb0e3 --- /dev/null +++ b/gas/testsuite/gas/mips/loongson-3a.d @@ -0,0 +1,111 @@ -+#as: -march=loongson3a -mabi=o64 -+#objdump: -M reg-names=numeric -dr -+#name: Loongson-3A tests -+ -+.*: file format .* -+ -+Disassembly of section .text: -+ -+[0-9a-f]+ : -+.*: 0064100b movn \$2,\$3,\$4 -+ -+[0-9a-f]+ : -+.*: 70641010 gsmult \$2,\$3,\$4 -+.*: 70c72812 gsmultu \$5,\$6,\$7 -+.*: 712a4011 gsdmult \$8,\$9,\$10 -+.*: 718d5813 gsdmultu \$11,\$12,\$13 -+.*: 71f07014 gsdiv \$14,\$15,\$16 -+.*: 72538816 gsdivu \$17,\$18,\$19 -+.*: 72b6a015 gsddiv \$20,\$21,\$22 -+.*: 7319b817 gsddivu \$23,\$24,\$25 -+.*: 737cd01c gsmod \$26,\$27,\$28 -+.*: 73dfe81e gsmodu \$29,\$30,\$31 -+.*: 7064101d gsdmod \$2,\$3,\$4 -+.*: 70c7281f gsdmodu \$5,\$6,\$7 -+ -+[0-9a-f]+ : -+.*: 4b420802 packsshb \$f0,\$f1,\$f2 -+.*: 4b2520c2 packsswh \$f3,\$f4,\$f5 -+.*: 4b683982 packushb \$f6,\$f7,\$f8 -+.*: 4bcb5240 paddb \$f9,\$f10,\$f11 -+.*: 4b4e6b00 paddh \$f12,\$f13,\$f14 -+.*: 4b7183c0 paddw \$f15,\$f16,\$f17 -+.*: 4bf49c80 paddd \$f18,\$f19,\$f20 -+.*: 4b97b540 paddsb \$f21,\$f22,\$f23 -+.*: 4b1ace00 paddsh \$f24,\$f25,\$f26 -+.*: 4bbde6c0 paddusb \$f27,\$f28,\$f29 -+.*: 4b220800 paddush \$f0,\$f1,\$f2 -+.*: 4be520c2 pandn \$f3,\$f4,\$f5 -+.*: 4b283988 pavgb \$f6,\$f7,\$f8 -+.*: 4b0b5248 pavgh \$f9,\$f10,\$f11 -+.*: 4b8e6b09 pcmpeqb \$f12,\$f13,\$f14 -+.*: 4b5183c9 pcmpeqh \$f15,\$f16,\$f17 -+.*: 4b149c89 pcmpeqw \$f18,\$f19,\$f20 -+.*: 4bb7b549 pcmpgtb \$f21,\$f22,\$f23 -+.*: 4b7ace09 pcmpgth \$f24,\$f25,\$f26 -+.*: 4b3de6c9 pcmpgtw \$f27,\$f28,\$f29 -+.*: 4b42080e pextrh \$f0,\$f1,\$f2 -+.*: 4b8520c3 pinsrh_0 \$f3,\$f4,\$f5 -+.*: 4ba83983 pinsrh_1 \$f6,\$f7,\$f8 -+.*: 4bcb5243 pinsrh_2 \$f9,\$f10,\$f11 -+.*: 4bee6b03 pinsrh_3 \$f12,\$f13,\$f14 -+.*: 4b7183ce pmaddhw \$f15,\$f16,\$f17 -+.*: 4b549c88 pmaxsh \$f18,\$f19,\$f20 -+.*: 4b97b548 pmaxub \$f21,\$f22,\$f23 -+.*: 4b7ace08 pminsh \$f24,\$f25,\$f26 -+.*: 4bbde6c8 pminub \$f27,\$f28,\$f29 -+.*: 4ba0080f pmovmskb \$f0,\$f1 -+.*: 4ba4188a pmulhuh \$f2,\$f3,\$f4 -+.*: 4b67314a pmulhh \$f5,\$f6,\$f7 -+.*: 4b4a4a0a pmullh \$f8,\$f9,\$f10 -+.*: 4b8d62ca pmuluw \$f11,\$f12,\$f13 -+.*: 4b307b8d pasubub \$f14,\$f15,\$f16 -+.*: 4b80944f biadd \$f17,\$f18 -+.*: 4b15a4c2 pshufh \$f19,\$f20,\$f21 -+.*: 4b38bd8a psllh \$f22,\$f23,\$f24 -+.*: 4b1bd64a psllw \$f25,\$f26,\$f27 -+.*: 4b7eef0b psrah \$f28,\$f29,\$f30 -+.*: 4b42080b psraw \$f0,\$f1,\$f2 -+.*: 4b2520cb psrlh \$f3,\$f4,\$f5 -+.*: 4b08398b psrlw \$f6,\$f7,\$f8 -+.*: 4bcb5241 psubb \$f9,\$f10,\$f11 -+.*: 4b4e6b01 psubh \$f12,\$f13,\$f14 -+.*: 4b7183c1 psubw \$f15,\$f16,\$f17 -+.*: 4bf49c81 psubd \$f18,\$f19,\$f20 -+.*: 4b97b541 psubsb \$f21,\$f22,\$f23 -+.*: 4b1ace01 psubsh \$f24,\$f25,\$f26 -+.*: 4bbde6c1 psubusb \$f27,\$f28,\$f29 -+.*: 4b220801 psubush \$f0,\$f1,\$f2 -+.*: 4b6520c3 punpckhbh \$f3,\$f4,\$f5 -+.*: 4b283983 punpckhhw \$f6,\$f7,\$f8 -+.*: 4bab524b punpckhwd \$f9,\$f10,\$f11 -+.*: 4b4e6b03 punpcklbh \$f12,\$f13,\$f14 -+.*: 4b1183c3 punpcklhw \$f15,\$f16,\$f17 -+.*: 4b949c8b punpcklwd \$f18,\$f19,\$f20 -+ -+[0-9a-f]+ : -+.*: 4b42080c add \$f0,\$f1,\$f2 -+.*: 4b0520cc addu \$f3,\$f4,\$f5 -+.*: 4b68398c dadd \$f6,\$f7,\$f8 -+.*: 4b4b524d sub \$f9,\$f10,\$f11 -+.*: 4b0e6b0d subu \$f12,\$f13,\$f14 -+.*: 4b7183cd dsub \$f15,\$f16,\$f17 -+.*: 4b349c8c or \$f18,\$f19,\$f20 -+.*: 4b17b54e sll \$f21,\$f22,\$f23 -+.*: 4b3ace0e dsll \$f24,\$f25,\$f26 -+.*: 4b9de6c2 xor \$f27,\$f28,\$f29 -+.*: 4ba20802 nor \$f0,\$f1,\$f2 -+.*: 4bc520c2 and \$f3,\$f4,\$f5 -+.*: 4b08398f srl \$f6,\$f7,\$f8 -+.*: 4b2b524f dsrl \$f9,\$f10,\$f11 -+.*: 4b4e6b0f sra \$f12,\$f13,\$f14 -+.*: 4b7183cf dsra \$f15,\$f16,\$f17 -+.*: 4b93900c sequ \$f18,\$f19 -+.*: 4b95a00d sltu \$f20,\$f21 -+.*: 4b97b00e sleu \$f22,\$f23 -+.*: 4bb9c00c seq \$f24,\$f25 -+.*: 4bbbd00d slt \$f26,\$f27 -+.*: 4bbde00e sle \$f28,\$f29 -+#pass -+ -+ ++#as: -march=loongson3a -mabi=o64 ++#objdump: -M reg-names=numeric -dr ++#name: Loongson-3A tests ++ ++.*: file format .* ++ ++Disassembly of section .text: ++ ++[0-9a-f]+ : ++.*: 0064100b movn \$2,\$3,\$4 ++ ++[0-9a-f]+ : ++.*: 70641010 gsmult \$2,\$3,\$4 ++.*: 70c72812 gsmultu \$5,\$6,\$7 ++.*: 712a4011 gsdmult \$8,\$9,\$10 ++.*: 718d5813 gsdmultu \$11,\$12,\$13 ++.*: 71f07014 gsdiv \$14,\$15,\$16 ++.*: 72538816 gsdivu \$17,\$18,\$19 ++.*: 72b6a015 gsddiv \$20,\$21,\$22 ++.*: 7319b817 gsddivu \$23,\$24,\$25 ++.*: 737cd01c gsmod \$26,\$27,\$28 ++.*: 73dfe81e gsmodu \$29,\$30,\$31 ++.*: 7064101d gsdmod \$2,\$3,\$4 ++.*: 70c7281f gsdmodu \$5,\$6,\$7 ++ ++[0-9a-f]+ : ++.*: 4b420802 packsshb \$f0,\$f1,\$f2 ++.*: 4b2520c2 packsswh \$f3,\$f4,\$f5 ++.*: 4b683982 packushb \$f6,\$f7,\$f8 ++.*: 4bcb5240 paddb \$f9,\$f10,\$f11 ++.*: 4b4e6b00 paddh \$f12,\$f13,\$f14 ++.*: 4b7183c0 paddw \$f15,\$f16,\$f17 ++.*: 4bf49c80 paddd \$f18,\$f19,\$f20 ++.*: 4b97b540 paddsb \$f21,\$f22,\$f23 ++.*: 4b1ace00 paddsh \$f24,\$f25,\$f26 ++.*: 4bbde6c0 paddusb \$f27,\$f28,\$f29 ++.*: 4b220800 paddush \$f0,\$f1,\$f2 ++.*: 4be520c2 pandn \$f3,\$f4,\$f5 ++.*: 4b283988 pavgb \$f6,\$f7,\$f8 ++.*: 4b0b5248 pavgh \$f9,\$f10,\$f11 ++.*: 4b8e6b09 pcmpeqb \$f12,\$f13,\$f14 ++.*: 4b5183c9 pcmpeqh \$f15,\$f16,\$f17 ++.*: 4b149c89 pcmpeqw \$f18,\$f19,\$f20 ++.*: 4bb7b549 pcmpgtb \$f21,\$f22,\$f23 ++.*: 4b7ace09 pcmpgth \$f24,\$f25,\$f26 ++.*: 4b3de6c9 pcmpgtw \$f27,\$f28,\$f29 ++.*: 4b42080e pextrh \$f0,\$f1,\$f2 ++.*: 4b8520c3 pinsrh_0 \$f3,\$f4,\$f5 ++.*: 4ba83983 pinsrh_1 \$f6,\$f7,\$f8 ++.*: 4bcb5243 pinsrh_2 \$f9,\$f10,\$f11 ++.*: 4bee6b03 pinsrh_3 \$f12,\$f13,\$f14 ++.*: 4b7183ce pmaddhw \$f15,\$f16,\$f17 ++.*: 4b549c88 pmaxsh \$f18,\$f19,\$f20 ++.*: 4b97b548 pmaxub \$f21,\$f22,\$f23 ++.*: 4b7ace08 pminsh \$f24,\$f25,\$f26 ++.*: 4bbde6c8 pminub \$f27,\$f28,\$f29 ++.*: 4ba0080f pmovmskb \$f0,\$f1 ++.*: 4ba4188a pmulhuh \$f2,\$f3,\$f4 ++.*: 4b67314a pmulhh \$f5,\$f6,\$f7 ++.*: 4b4a4a0a pmullh \$f8,\$f9,\$f10 ++.*: 4b8d62ca pmuluw \$f11,\$f12,\$f13 ++.*: 4b307b8d pasubub \$f14,\$f15,\$f16 ++.*: 4b80944f biadd \$f17,\$f18 ++.*: 4b15a4c2 pshufh \$f19,\$f20,\$f21 ++.*: 4b38bd8a psllh \$f22,\$f23,\$f24 ++.*: 4b1bd64a psllw \$f25,\$f26,\$f27 ++.*: 4b7eef0b psrah \$f28,\$f29,\$f30 ++.*: 4b42080b psraw \$f0,\$f1,\$f2 ++.*: 4b2520cb psrlh \$f3,\$f4,\$f5 ++.*: 4b08398b psrlw \$f6,\$f7,\$f8 ++.*: 4bcb5241 psubb \$f9,\$f10,\$f11 ++.*: 4b4e6b01 psubh \$f12,\$f13,\$f14 ++.*: 4b7183c1 psubw \$f15,\$f16,\$f17 ++.*: 4bf49c81 psubd \$f18,\$f19,\$f20 ++.*: 4b97b541 psubsb \$f21,\$f22,\$f23 ++.*: 4b1ace01 psubsh \$f24,\$f25,\$f26 ++.*: 4bbde6c1 psubusb \$f27,\$f28,\$f29 ++.*: 4b220801 psubush \$f0,\$f1,\$f2 ++.*: 4b6520c3 punpckhbh \$f3,\$f4,\$f5 ++.*: 4b283983 punpckhhw \$f6,\$f7,\$f8 ++.*: 4bab524b punpckhwd \$f9,\$f10,\$f11 ++.*: 4b4e6b03 punpcklbh \$f12,\$f13,\$f14 ++.*: 4b1183c3 punpcklhw \$f15,\$f16,\$f17 ++.*: 4b949c8b punpcklwd \$f18,\$f19,\$f20 ++ ++[0-9a-f]+ : ++.*: 4b42080c add \$f0,\$f1,\$f2 ++.*: 4b0520cc addu \$f3,\$f4,\$f5 ++.*: 4b68398c dadd \$f6,\$f7,\$f8 ++.*: 4b4b524d sub \$f9,\$f10,\$f11 ++.*: 4b0e6b0d subu \$f12,\$f13,\$f14 ++.*: 4b7183cd dsub \$f15,\$f16,\$f17 ++.*: 4b349c8c or \$f18,\$f19,\$f20 ++.*: 4b17b54e sll \$f21,\$f22,\$f23 ++.*: 4b3ace0e dsll \$f24,\$f25,\$f26 ++.*: 4b9de6c2 xor \$f27,\$f28,\$f29 ++.*: 4ba20802 nor \$f0,\$f1,\$f2 ++.*: 4bc520c2 and \$f3,\$f4,\$f5 ++.*: 4b08398f srl \$f6,\$f7,\$f8 ++.*: 4b2b524f dsrl \$f9,\$f10,\$f11 ++.*: 4b4e6b0f sra \$f12,\$f13,\$f14 ++.*: 4b7183cf dsra \$f15,\$f16,\$f17 ++.*: 4b93900c sequ \$f18,\$f19 ++.*: 4b95a00d sltu \$f20,\$f21 ++.*: 4b97b00e sleu \$f22,\$f23 ++.*: 4bb9c00c seq \$f24,\$f25 ++.*: 4bbbd00d slt \$f26,\$f27 ++.*: 4bbde00e sle \$f28,\$f29 ++#pass ++ ++ diff --git a/gas/testsuite/gas/mips/loongson-3a.s b/gas/testsuite/gas/mips/loongson-3a.s new file mode 100644 -index 0000000..b441969 +index 0000000..73c00c0 --- /dev/null +++ b/gas/testsuite/gas/mips/loongson-3a.s @@ -0,0 +1,105 @@ -+ .text -+ .set noreorder -+ -+movz_insns: -+ movnz $2, $3, $4 -+ -+integer_insns: -+ gsmult $2, $3, $4 -+ gsmultu $5, $6, $7 -+ gsdmult $8, $9, $10 -+ gsdmultu $11, $12, $13 -+ gsdiv $14, $15, $16 -+ gsdivu $17, $18, $19 -+ gsddiv $20, $21, $22 -+ gsddivu $23, $24, $25 -+ gsmod $26, $27, $28 -+ gsmodu $29, $30, $31 -+ gsdmod $2, $3, $4 -+ gsdmodu $5, $6, $7 -+ -+simd_insns: -+ packsshb $f0, $f1, $f2 -+ packsswh $f3, $f4, $f5 -+ packushb $f6, $f7, $f8 -+ paddb $f9, $f10, $f11 -+ paddh $f12, $f13, $f14 -+ paddw $f15, $f16, $f17 -+ paddd $f18, $f19, $f20 -+ paddsb $f21, $f22, $f23 -+ paddsh $f24, $f25, $f26 -+ paddusb $f27, $f28, $f29 -+ paddush $f0, $f1, $f2 -+ pandn $f3, $f4, $f5 -+ pavgb $f6, $f7, $f8 -+ pavgh $f9, $f10, $f11 -+ pcmpeqb $f12, $f13, $f14 -+ pcmpeqh $f15, $f16, $f17 -+ pcmpeqw $f18, $f19, $f20 -+ pcmpgtb $f21, $f22, $f23 -+ pcmpgth $f24, $f25, $f26 -+ pcmpgtw $f27, $f28, $f29 -+ pextrh $f0, $f1, $f2 -+ pinsrh_0 $f3, $f4, $f5 -+ pinsrh_1 $f6, $f7, $f8 -+ pinsrh_2 $f9, $f10, $f11 -+ pinsrh_3 $f12, $f13, $f14 -+ pmaddhw $f15, $f16, $f17 -+ pmaxsh $f18, $f19, $f20 -+ pmaxub $f21, $f22, $f23 -+ pminsh $f24, $f25, $f26 -+ pminub $f27, $f28, $f29 -+ pmovmskb $f0, $f1 -+ pmulhuh $f2, $f3, $f4 -+ pmulhh $f5, $f6, $f7 -+ pmullh $f8, $f9, $f10 -+ pmuluw $f11, $f12, $f13 -+ pasubub $f14, $f15, $f16 -+ biadd $f17, $f18 -+ pshufh $f19, $f20, $f21 -+ psllh $f22, $f23, $f24 -+ psllw $f25, $f26, $f27 -+ psrah $f28, $f29, $f30 -+ psraw $f0, $f1, $f2 -+ psrlh $f3, $f4, $f5 -+ psrlw $f6, $f7, $f8 -+ psubb $f9, $f10, $f11 -+ psubh $f12, $f13, $f14 -+ psubw $f15, $f16, $f17 -+ psubd $f18, $f19, $f20 -+ psubsb $f21, $f22, $f23 -+ psubsh $f24, $f25, $f26 -+ psubusb $f27, $f28, $f29 -+ psubush $f0, $f1, $f2 -+ punpckhbh $f3, $f4, $f5 -+ punpckhhw $f6, $f7, $f8 -+ punpckhwd $f9, $f10, $f11 -+ punpcklbh $f12, $f13, $f14 -+ punpcklhw $f15, $f16, $f17 -+ punpcklwd $f18, $f19, $f20 -+ -+fixed_point_insns: -+ add $f0, $f1, $f2 -+ addu $f3, $f4, $f5 -+ dadd $f6, $f7, $f8 -+ sub $f9, $f10, $f11 -+ subu $f12, $f13, $f14 -+ dsub $f15, $f16, $f17 -+ or $f18, $f19, $f20 -+ sll $f21, $f22, $f23 -+ dsll $f24, $f25, $f26 -+ xor $f27, $f28, $f29 -+ nor $f0, $f1, $f2 -+ and $f3, $f4, $f5 -+ srl $f6, $f7, $f8 -+ dsrl $f9, $f10, $f11 -+ sra $f12, $f13, $f14 -+ dsra $f15, $f16, $f17 -+ sequ $f18, $f19 -+ sltu $f20, $f21 -+ sleu $f22, $f23 -+ seq $f24, $f25 -+ slt $f26, $f27 -+ sle $f28, $f29 -+ -+ ++ .text ++ .set noreorder ++ ++movz_insns: ++ movnz $2, $3, $4 ++ ++integer_insns: ++ gsmult $2, $3, $4 ++ gsmultu $5, $6, $7 ++ gsdmult $8, $9, $10 ++ gsdmultu $11, $12, $13 ++ gsdiv $14, $15, $16 ++ gsdivu $17, $18, $19 ++ gsddiv $20, $21, $22 ++ gsddivu $23, $24, $25 ++ gsmod $26, $27, $28 ++ gsmodu $29, $30, $31 ++ gsdmod $2, $3, $4 ++ gsdmodu $5, $6, $7 ++ ++simd_insns: ++ packsshb $f0, $f1, $f2 ++ packsswh $f3, $f4, $f5 ++ packushb $f6, $f7, $f8 ++ paddb $f9, $f10, $f11 ++ paddh $f12, $f13, $f14 ++ paddw $f15, $f16, $f17 ++ paddd $f18, $f19, $f20 ++ paddsb $f21, $f22, $f23 ++ paddsh $f24, $f25, $f26 ++ paddusb $f27, $f28, $f29 ++ paddush $f0, $f1, $f2 ++ pandn $f3, $f4, $f5 ++ pavgb $f6, $f7, $f8 ++ pavgh $f9, $f10, $f11 ++ pcmpeqb $f12, $f13, $f14 ++ pcmpeqh $f15, $f16, $f17 ++ pcmpeqw $f18, $f19, $f20 ++ pcmpgtb $f21, $f22, $f23 ++ pcmpgth $f24, $f25, $f26 ++ pcmpgtw $f27, $f28, $f29 ++ pextrh $f0, $f1, $f2 ++ pinsrh_0 $f3, $f4, $f5 ++ pinsrh_1 $f6, $f7, $f8 ++ pinsrh_2 $f9, $f10, $f11 ++ pinsrh_3 $f12, $f13, $f14 ++ pmaddhw $f15, $f16, $f17 ++ pmaxsh $f18, $f19, $f20 ++ pmaxub $f21, $f22, $f23 ++ pminsh $f24, $f25, $f26 ++ pminub $f27, $f28, $f29 ++ pmovmskb $f0, $f1 ++ pmulhuh $f2, $f3, $f4 ++ pmulhh $f5, $f6, $f7 ++ pmullh $f8, $f9, $f10 ++ pmuluw $f11, $f12, $f13 ++ pasubub $f14, $f15, $f16 ++ biadd $f17, $f18 ++ pshufh $f19, $f20, $f21 ++ psllh $f22, $f23, $f24 ++ psllw $f25, $f26, $f27 ++ psrah $f28, $f29, $f30 ++ psraw $f0, $f1, $f2 ++ psrlh $f3, $f4, $f5 ++ psrlw $f6, $f7, $f8 ++ psubb $f9, $f10, $f11 ++ psubh $f12, $f13, $f14 ++ psubw $f15, $f16, $f17 ++ psubd $f18, $f19, $f20 ++ psubsb $f21, $f22, $f23 ++ psubsh $f24, $f25, $f26 ++ psubusb $f27, $f28, $f29 ++ psubush $f0, $f1, $f2 ++ punpckhbh $f3, $f4, $f5 ++ punpckhhw $f6, $f7, $f8 ++ punpckhwd $f9, $f10, $f11 ++ punpcklbh $f12, $f13, $f14 ++ punpcklhw $f15, $f16, $f17 ++ punpcklwd $f18, $f19, $f20 ++ ++fixed_point_insns: ++ add $f0, $f1, $f2 ++ addu $f3, $f4, $f5 ++ dadd $f6, $f7, $f8 ++ sub $f9, $f10, $f11 ++ subu $f12, $f13, $f14 ++ dsub $f15, $f16, $f17 ++ or $f18, $f19, $f20 ++ sll $f21, $f22, $f23 ++ dsll $f24, $f25, $f26 ++ xor $f27, $f28, $f29 ++ nor $f0, $f1, $f2 ++ and $f3, $f4, $f5 ++ srl $f6, $f7, $f8 ++ dsrl $f9, $f10, $f11 ++ sra $f12, $f13, $f14 ++ dsra $f15, $f16, $f17 ++ sequ $f18, $f19 ++ sltu $f20, $f21 ++ sleu $f22, $f23 ++ seq $f24, $f25 ++ slt $f26, $f27 ++ sle $f28, $f29 ++ ++ diff --git a/gas/testsuite/gas/mips/lui-1.l b/gas/testsuite/gas/mips/lui-1.l new file mode 100644 index 0000000..8bf621d @@ -1670136,13 +1678552,13 @@ index 0000000..d4b6590 + lui $2, (($3)) diff --git a/gas/testsuite/gas/mips/lui-2.l b/gas/testsuite/gas/mips/lui-2.l new file mode 100644 -index 0000000..ed97e85 +index 0000000..635f97d --- /dev/null +++ b/gas/testsuite/gas/mips/lui-2.l @@ -0,0 +1,5 @@ +.*\.s: Assembler messages: +.*\.s:10: Error: invalid operands \(\*UND\* and \*UND\* sections\) for `/' -+.*\.s:7: Error: can't resolve `bar' {\*UND\* section} - `foo' {\.text section} ++.*\.s:7: Error: PC-relative reference to a different section +.*\.s:8: Error: can't resolve `baz' {\*UND\* section} - `bar' {\*UND\* section} +.*\.s:9: Error: can't resolve `\.text' {\.text section} - `baz' {\*UND\* section} diff --git a/gas/testsuite/gas/mips/lui-2.s b/gas/testsuite/gas/mips/lui-2.s @@ -1715074,10 +1723490,10 @@ index 0000000..f428bcf + \.\.\. diff --git a/gas/testsuite/gas/mips/micromips@msa-branch.d b/gas/testsuite/gas/mips/micromips@msa-branch.d new file mode 100644 -index 0000000..6c8fdb7 +index 0000000..8b22b9e --- /dev/null +++ b/gas/testsuite/gas/mips/micromips@msa-branch.d -@@ -0,0 +1,319 @@ +@@ -0,0 +1,309 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -Mmsa +#name: MSA branch reorder +#as: -32 -mmsa @@ -1715110,10 +1723526,9 @@ index 0000000..6c8fdb7 +[0-9a-f]+ <[^>]*> 8300 fffe bz\.b \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop -+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 8301 fffe bz\.b \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test -+[0-9a-f]+ <[^>]*> 0c00 nop ++[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 8302 fffe bz\.b \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 @@ -1715141,10 +1723556,9 @@ index 0000000..6c8fdb7 +[0-9a-f]+ <[^>]*> 8320 fffe bz\.h \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop -+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 8321 fffe bz\.h \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test -+[0-9a-f]+ <[^>]*> 0c00 nop ++[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 8322 fffe bz\.h \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 @@ -1715172,10 +1723586,9 @@ index 0000000..6c8fdb7 +[0-9a-f]+ <[^>]*> 8340 fffe bz\.w \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop -+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 8341 fffe bz\.w \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test -+[0-9a-f]+ <[^>]*> 0c00 nop ++[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 8342 fffe bz\.w \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 @@ -1715203,10 +1723616,9 @@ index 0000000..6c8fdb7 +[0-9a-f]+ <[^>]*> 8360 fffe bz\.d \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop -+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 8361 fffe bz\.d \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test -+[0-9a-f]+ <[^>]*> 0c00 nop ++[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 8362 fffe bz\.d \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 @@ -1715234,10 +1723646,9 @@ index 0000000..6c8fdb7 +[0-9a-f]+ <[^>]*> 8160 fffe bz\.v \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop -+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 8161 fffe bz\.v \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test -+[0-9a-f]+ <[^>]*> 0c00 nop ++[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 8162 fffe bz\.v \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 @@ -1715265,10 +1723676,9 @@ index 0000000..6c8fdb7 +[0-9a-f]+ <[^>]*> 8380 fffe bnz\.b \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop -+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 8381 fffe bnz\.b \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test -+[0-9a-f]+ <[^>]*> 0c00 nop ++[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 8382 fffe bnz\.b \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 @@ -1715296,10 +1723706,9 @@ index 0000000..6c8fdb7 +[0-9a-f]+ <[^>]*> 83a0 fffe bnz\.h \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop -+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 83a1 fffe bnz\.h \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test -+[0-9a-f]+ <[^>]*> 0c00 nop ++[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 83a2 fffe bnz\.h \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 @@ -1715327,10 +1723736,9 @@ index 0000000..6c8fdb7 +[0-9a-f]+ <[^>]*> 83c0 fffe bnz\.w \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop -+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 83c1 fffe bnz\.w \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test -+[0-9a-f]+ <[^>]*> 0c00 nop ++[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 83c2 fffe bnz\.w \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 @@ -1715358,10 +1723766,9 @@ index 0000000..6c8fdb7 +[0-9a-f]+ <[^>]*> 83e0 fffe bnz\.d \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop -+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 83e1 fffe bnz\.d \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test -+[0-9a-f]+ <[^>]*> 0c00 nop ++[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 83e2 fffe bnz\.d \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 @@ -1715389,10 +1723796,9 @@ index 0000000..6c8fdb7 +[0-9a-f]+ <[^>]*> 81e0 fffe bnz\.v \$w0,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 0c00 nop -+[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 81e1 fffe bnz\.v \$w1,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test -+[0-9a-f]+ <[^>]*> 0c00 nop ++[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 81e2 fffe bnz\.v \$w2,[0-9a-f]+ <[^>]*> +[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test +[0-9a-f]+ <[^>]*> 5482 0130 add\.d \$f0,\$f2,\$f4 @@ -1719118,12 +1727524,12 @@ index 0000000..2181bb1 + ... diff --git a/gas/testsuite/gas/mips/mips-gp32-fp64.l b/gas/testsuite/gas/mips/mips-gp32-fp64.l new file mode 100644 -index 0000000..de3f3b0 +index 0000000..82b7b17 --- /dev/null +++ b/gas/testsuite/gas/mips/mips-gp32-fp64.l @@ -0,0 +1,2 @@ -+Assembler messages: -+Warning: -mfp64 used with a 32-bit ABI ++.*Assembler messages: ++.* Warning: `fp=64' used with a 32-bit ABI diff --git a/gas/testsuite/gas/mips/mips-gp32-fp64.s b/gas/testsuite/gas/mips/mips-gp32-fp64.s new file mode 100644 index 0000000..66ce7f6 @@ -1719366,12 +1727772,12 @@ index 0000000..52fe8af + ... diff --git a/gas/testsuite/gas/mips/mips-gp64-fp32-pic.l b/gas/testsuite/gas/mips/mips-gp64-fp32-pic.l new file mode 100644 -index 0000000..2d37303 +index 0000000..a02481a --- /dev/null +++ b/gas/testsuite/gas/mips/mips-gp64-fp32-pic.l @@ -0,0 +1,2 @@ -+Assembler messages: -+Warning: -mfp32 used with a 64-bit ABI ++.*Assembler messages: ++.*:16: Warning: `fp=32' used with a 64-bit ABI diff --git a/gas/testsuite/gas/mips/mips-gp64-fp32-pic.s b/gas/testsuite/gas/mips/mips-gp64-fp32-pic.s new file mode 100644 index 0000000..b00370e @@ -1719654,12 +1728060,12 @@ index 0000000..9f7540b + ... diff --git a/gas/testsuite/gas/mips/mips-gp64-fp32.l b/gas/testsuite/gas/mips/mips-gp64-fp32.l new file mode 100644 -index 0000000..e72f085 +index 0000000..5fd9e34 --- /dev/null +++ b/gas/testsuite/gas/mips/mips-gp64-fp32.l @@ -0,0 +1,5 @@ -+Assembler messages: -+Warning: -mfp32 used with a 64-bit ABI ++.*Assembler messages: ++.* Warning: `fp=32' used with a 64-bit ABI +.*:92: Warning: macro instruction expanded into multiple instructions in a branch delay slot +.*:96: Warning: macro instruction expanded into multiple instructions in a branch delay slot +.*:100: Warning: macro instruction expanded into multiple instructions in a branch delay slot @@ -1720528,12 +1728934,11 @@ index 0000000..85e7815 + .word 0 diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp new file mode 100644 -index 0000000..ece3a13 +index 0000000..c3135ca --- /dev/null +++ b/gas/testsuite/gas/mips/mips.exp -@@ -0,0 +1,1173 @@ -+# Copyright 2012, 2013 -+# Free Software Foundation, Inc. +@@ -0,0 +1,1207 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1720951,6 +1729356,14 @@ index 0000000..ece3a13 + { -march=mips32r2 -mtune=mips32r2 } \ + { -mmips:isa32r2 } \ + { mipsisa32r2-*-* mipsisa32r2el-*-* } ++mips_arch_create mips32r3 32 mips32r2 { fpisa3 fpisa4 fpisa5 ror } \ ++ { -march=mips32r3 -mtune=mips32r3 } \ ++ { -mmips:isa32r3 } \ ++ { mipsisa32r3-*-* mipsisa32r3el-*-* } ++mips_arch_create mips32r5 32 mips32r3 { fpisa3 fpisa4 fpisa5 ror } \ ++ { -march=mips32r5 -mtune=mips32r5 } \ ++ { -mmips:isa32r5 } \ ++ { mipsisa32r5-*-* mipsisa32r5el-*-* } +mips_arch_create mips64 64 mips5 { mips32 } \ + { -march=mips64 -mtune=mips64 } { -mmips:isa64 } \ + { mipsisa64-*-* mipsisa64el-*-* } @@ -1720958,10 +1729371,18 @@ index 0000000..ece3a13 + { -march=mips64r2 -mtune=mips64r2 } \ + { -mmips:isa64r2 } \ + { mipsisa64r2-*-* mipsisa64r2el-*-* } ++mips_arch_create mips64r3 64 mips64r2 { mips32r3 ror } \ ++ { -march=mips64r3 -mtune=mips64r3 } \ ++ { -mmips:isa64r3 } \ ++ { mipsisa64r3-*-* mipsisa64r3el-*-* } ++mips_arch_create mips64r5 64 mips64r3 { mips32r5 ror } \ ++ { -march=mips64r5 -mtune=mips64r5 } \ ++ { -mmips:isa64r5 } \ ++ { mipsisa64r5-*-* mipsisa64r5el-*-* } +mips_arch_create mips16 32 {} {} \ + { -march=mips1 -mips16 } { -mmips:16 } +mips_arch_create micromips 64 mips64r2 {} \ -+ { -march=mips64 -mmicromips } {} ++ { -march=mips64r2 -mmicromips } {} +mips_arch_create r3000 32 mips1 {} \ + { -march=r3000 -mtune=r3000 } { -mmips:3000 } +mips_arch_create r3900 32 mips1 { gpr_ilocks } \ @@ -1721306,7 +1729727,7 @@ index 0000000..ece3a13 + run_dump_test "relax-swap1-mips2" + run_dump_test "relax-swap2" + run_dump_test_arches "relax-swap3" [mips_arch_list_all] -+ run_list_test_arches "relax-bc1any" "-mips3d -relax-branch" \ ++ run_list_test_arches "relax-bc1any" "-mips3d -mabi=o64 -relax-branch" \ + [mips_arch_list_matching mips64 \ + !micromips] + run_list_test_arches "relax-bposge" "-mdsp -relax-branch" \ @@ -1721704,6 +1730125,25 @@ index 0000000..ece3a13 + run_dump_test_arches "msa64" [mips_arch_list_matching mips64r2] + run_dump_test_arches "msa-relax" [mips_arch_list_matching mips32r2] + run_dump_test_arches "msa-branch" [mips_arch_list_matching mips32r2] ++ ++ run_dump_test_arches "xpa" [mips_arch_list_matching mips32r2 !micromips] ++ run_dump_test_arches "r5" [mips_arch_list_matching mips32r5 !micromips] ++ ++ run_dump_test "pcrel-1" ++ run_dump_test "pcrel-2" ++ run_list_test "pcrel-3" "" "Invalid cross-section PC-relative references" ++ run_dump_test "pcrel-4-32" ++ if $has_newabi { ++ run_dump_test "pcrel-4-n32" ++ run_dump_test "pcrel-4-64" ++ } ++ ++ run_dump_test "attr-gnu-abi-fp-1" ++ run_dump_test "attr-gnu-abi-msa-1" ++ ++ run_dump_test "module-override" ++ run_dump_test "module-defer-warn1" ++ run_list_test "module-defer-warn2" -32 +} diff --git a/gas/testsuite/gas/mips/mips1-fp.d b/gas/testsuite/gas/mips/mips1-fp.d new file mode 100644 @@ -1736624,12 +1745064,70 @@ index 0000000..8c1e2ea + 0010 00000000 00000000 .* +Contents of section foo: + 0000 03000000 00000000 00000000 00000000 .* +diff --git a/gas/testsuite/gas/mips/module-defer-warn1.d b/gas/testsuite/gas/mips/module-defer-warn1.d +new file mode 100644 +index 0000000..d5ee70e +--- /dev/null ++++ b/gas/testsuite/gas/mips/module-defer-warn1.d +@@ -0,0 +1,7 @@ ++# name: .module deferred warnings ++# source: module-defer-warn1.s ++# objdump: -p ++# as: -32 -march=mips2 -mgp64 ++ ++.*:.*file format.*elf.*mips.* ++private flags = 1.......: .*\[mips2\].* +diff --git a/gas/testsuite/gas/mips/module-defer-warn1.s b/gas/testsuite/gas/mips/module-defer-warn1.s +new file mode 100644 +index 0000000..d9cbf39 +--- /dev/null ++++ b/gas/testsuite/gas/mips/module-defer-warn1.s +@@ -0,0 +1,2 @@ ++.module gp=32 ++addiu $2, $2, 1 +diff --git a/gas/testsuite/gas/mips/module-defer-warn2.l b/gas/testsuite/gas/mips/module-defer-warn2.l +new file mode 100644 +index 0000000..f03ad48 +--- /dev/null ++++ b/gas/testsuite/gas/mips/module-defer-warn2.l +@@ -0,0 +1,3 @@ ++.*: Assembler messages: ++.*:2: Error: `gp=64' used with a 32-bit processor ++.*:2: Error: `fp=64' used with a 32-bit fpu +diff --git a/gas/testsuite/gas/mips/module-defer-warn2.s b/gas/testsuite/gas/mips/module-defer-warn2.s +new file mode 100644 +index 0000000..f7353e5 +--- /dev/null ++++ b/gas/testsuite/gas/mips/module-defer-warn2.s +@@ -0,0 +1,2 @@ ++.module gp=64 ++addiu $2, $2, 1 +diff --git a/gas/testsuite/gas/mips/module-override.d b/gas/testsuite/gas/mips/module-override.d +new file mode 100644 +index 0000000..0305b02 +--- /dev/null ++++ b/gas/testsuite/gas/mips/module-override.d +@@ -0,0 +1,7 @@ ++# name: .module command line override ++# source: module-override.s ++# objdump: -p ++# as: -32 -march=mips32r2 ++ ++.*:.*file format.*elf.*mips.* ++private flags = 1.......: .*\[mips2\].* +diff --git a/gas/testsuite/gas/mips/module-override.s b/gas/testsuite/gas/mips/module-override.s +new file mode 100644 +index 0000000..05f4a17 +--- /dev/null ++++ b/gas/testsuite/gas/mips/module-override.s +@@ -0,0 +1 @@ ++.module mips2 diff --git a/gas/testsuite/gas/mips/msa-branch.d b/gas/testsuite/gas/mips/msa-branch.d new file mode 100644 -index 0000000..567a2a4 +index 0000000..fbab5cc --- /dev/null +++ b/gas/testsuite/gas/mips/msa-branch.d -@@ -0,0 +1,228 @@ +@@ -0,0 +1,218 @@ +#objdump: -dr --prefix-addresses --show-raw-insn -Mmsa +#name: MSA branch reorder +#as: -32 -mmsa @@ -1736638,224 +1745136,214 @@ index 0000000..567a2a4 + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 -+[0-9a-f]+ <[^>]*> 4700fffe bz\.b \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4700.... bz\.b \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 4701fffc bz\.b \$w1,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4701.... bz\.b \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 -+[0-9a-f]+ <[^>]*> 4702fffa bz\.b \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4702.... bz\.b \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 -+[0-9a-f]+ <[^>]*> 4700fff7 bz\.b \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4700.... bz\.b \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 4701fff5 bz\.b \$w1,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4701.... bz\.b \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 -+[0-9a-f]+ <[^>]*> 4702fff3 bz\.b \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4702.... bz\.b \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 -+[0-9a-f]+ <[^>]*> 4700fff0 bz\.b \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4700.... bz\.b \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop ++[0-9a-f]+ <[^>]*> 4701.... bz\.b \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 -+[0-9a-f]+ <[^>]*> 4701ffed bz\.b \$w1,[0-9a-f]+ -+[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 4702ffeb bz\.b \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4702.... bz\.b \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 -+[0-9a-f]+ <[^>]*> 4720ffe8 bz\.h \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4720.... bz\.h \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 4721ffe6 bz\.h \$w1,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4721.... bz\.h \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 -+[0-9a-f]+ <[^>]*> 4722ffe4 bz\.h \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4722.... bz\.h \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 -+[0-9a-f]+ <[^>]*> 4720ffe1 bz\.h \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4720.... bz\.h \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 4721ffdf bz\.h \$w1,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4721.... bz\.h \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 -+[0-9a-f]+ <[^>]*> 4722ffdd bz\.h \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4722.... bz\.h \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 -+[0-9a-f]+ <[^>]*> 4720ffda bz\.h \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4720.... bz\.h \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop ++[0-9a-f]+ <[^>]*> 4721.... bz\.h \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 -+[0-9a-f]+ <[^>]*> 4721ffd7 bz\.h \$w1,[0-9a-f]+ -+[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 4722ffd5 bz\.h \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4722.... bz\.h \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 -+[0-9a-f]+ <[^>]*> 4740ffd2 bz\.w \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4740.... bz\.w \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 4741ffd0 bz\.w \$w1,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4741.... bz\.w \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 -+[0-9a-f]+ <[^>]*> 4742ffce bz\.w \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4742.... bz\.w \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 -+[0-9a-f]+ <[^>]*> 4740ffcb bz\.w \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4740.... bz\.w \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 4741ffc9 bz\.w \$w1,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4741.... bz\.w \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 -+[0-9a-f]+ <[^>]*> 4742ffc7 bz\.w \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4742.... bz\.w \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 -+[0-9a-f]+ <[^>]*> 4740ffc4 bz\.w \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4740.... bz\.w \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop ++[0-9a-f]+ <[^>]*> 4741.... bz\.w \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 -+[0-9a-f]+ <[^>]*> 4741ffc1 bz\.w \$w1,[0-9a-f]+ -+[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 4742ffbf bz\.w \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4742.... bz\.w \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 -+[0-9a-f]+ <[^>]*> 4760ffbc bz\.d \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4760.... bz\.d \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 4761ffba bz\.d \$w1,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4761.... bz\.d \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 -+[0-9a-f]+ <[^>]*> 4762ffb8 bz\.d \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4762.... bz\.d \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 -+[0-9a-f]+ <[^>]*> 4760ffb5 bz\.d \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4760.... bz\.d \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 4761ffb3 bz\.d \$w1,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4761.... bz\.d \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 -+[0-9a-f]+ <[^>]*> 4762ffb1 bz\.d \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4762.... bz\.d \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 -+[0-9a-f]+ <[^>]*> 4760ffae bz\.d \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4760.... bz\.d \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop ++[0-9a-f]+ <[^>]*> 4761.... bz\.d \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 -+[0-9a-f]+ <[^>]*> 4761ffab bz\.d \$w1,[0-9a-f]+ -+[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 4762ffa9 bz\.d \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4762.... bz\.d \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 -+[0-9a-f]+ <[^>]*> 4560ffa6 bz\.v \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4560.... bz\.v \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 4561ffa4 bz\.v \$w1,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4561.... bz\.v \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 -+[0-9a-f]+ <[^>]*> 4562ffa2 bz\.v \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4562.... bz\.v \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 -+[0-9a-f]+ <[^>]*> 4560ff9f bz\.v \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4560.... bz\.v \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 4561ff9d bz\.v \$w1,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4561.... bz\.v \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 -+[0-9a-f]+ <[^>]*> 4562ff9b bz\.v \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4562.... bz\.v \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 -+[0-9a-f]+ <[^>]*> 4560ff98 bz\.v \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4560.... bz\.v \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop ++[0-9a-f]+ <[^>]*> 4561.... bz\.v \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 -+[0-9a-f]+ <[^>]*> 4561ff95 bz\.v \$w1,[0-9a-f]+ -+[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 4562ff93 bz\.v \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4562.... bz\.v \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 -+[0-9a-f]+ <[^>]*> 4780ff90 bnz\.b \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4780.... bnz\.b \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 4781ff8e bnz\.b \$w1,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4781.... bnz\.b \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 -+[0-9a-f]+ <[^>]*> 4782ff8c bnz\.b \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4782.... bnz\.b \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 -+[0-9a-f]+ <[^>]*> 4780ff89 bnz\.b \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4780.... bnz\.b \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 4781ff87 bnz\.b \$w1,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4781.... bnz\.b \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 -+[0-9a-f]+ <[^>]*> 4782ff85 bnz\.b \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4782.... bnz\.b \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 -+[0-9a-f]+ <[^>]*> 4780ff82 bnz\.b \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4780.... bnz\.b \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop ++[0-9a-f]+ <[^>]*> 4781.... bnz\.b \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 -+[0-9a-f]+ <[^>]*> 4781ff7f bnz\.b \$w1,[0-9a-f]+ -+[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 4782ff7d bnz\.b \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 4782.... bnz\.b \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 -+[0-9a-f]+ <[^>]*> 47a0ff7a bnz\.h \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 47a0.... bnz\.h \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 47a1ff78 bnz\.h \$w1,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 47a1.... bnz\.h \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 -+[0-9a-f]+ <[^>]*> 47a2ff76 bnz\.h \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 47a2.... bnz\.h \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 -+[0-9a-f]+ <[^>]*> 47a0ff73 bnz\.h \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 47a0.... bnz\.h \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 47a1ff71 bnz\.h \$w1,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 47a1.... bnz\.h \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 -+[0-9a-f]+ <[^>]*> 47a2ff6f bnz\.h \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 47a2.... bnz\.h \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 -+[0-9a-f]+ <[^>]*> 47a0ff6c bnz\.h \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 47a0.... bnz\.h \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop ++[0-9a-f]+ <[^>]*> 47a1.... bnz\.h \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 -+[0-9a-f]+ <[^>]*> 47a1ff69 bnz\.h \$w1,[0-9a-f]+ -+[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 47a2ff67 bnz\.h \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 47a2.... bnz\.h \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 -+[0-9a-f]+ <[^>]*> 47c0ff64 bnz\.w \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 47c0.... bnz\.w \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 47c1ff62 bnz\.w \$w1,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 47c1.... bnz\.w \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 -+[0-9a-f]+ <[^>]*> 47c2ff60 bnz\.w \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 47c2.... bnz\.w \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 -+[0-9a-f]+ <[^>]*> 47c0ff5d bnz\.w \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 47c0.... bnz\.w \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 47c1ff5b bnz\.w \$w1,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 47c1.... bnz\.w \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 -+[0-9a-f]+ <[^>]*> 47c2ff59 bnz\.w \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 47c2.... bnz\.w \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 -+[0-9a-f]+ <[^>]*> 47c0ff56 bnz\.w \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 47c0.... bnz\.w \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop ++[0-9a-f]+ <[^>]*> 47c1.... bnz\.w \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 -+[0-9a-f]+ <[^>]*> 47c1ff53 bnz\.w \$w1,[0-9a-f]+ -+[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 47c2ff51 bnz\.w \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 47c2.... bnz\.w \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 -+[0-9a-f]+ <[^>]*> 47e0ff4e bnz\.d \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 47e0.... bnz\.d \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 47e1ff4c bnz\.d \$w1,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 47e1.... bnz\.d \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 -+[0-9a-f]+ <[^>]*> 47e2ff4a bnz\.d \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 47e2.... bnz\.d \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 -+[0-9a-f]+ <[^>]*> 47e0ff47 bnz\.d \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 47e0.... bnz\.d \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 47e1ff45 bnz\.d \$w1,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 47e1.... bnz\.d \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 -+[0-9a-f]+ <[^>]*> 47e2ff43 bnz\.d \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 47e2.... bnz\.d \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 -+[0-9a-f]+ <[^>]*> 47e0ff40 bnz\.d \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 47e0.... bnz\.d \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop ++[0-9a-f]+ <[^>]*> 47e1.... bnz\.d \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 -+[0-9a-f]+ <[^>]*> 47e1ff3d bnz\.d \$w1,[0-9a-f]+ -+[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 47e2ff3b bnz\.d \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 47e2.... bnz\.d \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 -+[0-9a-f]+ <[^>]*> 45e0ff38 bnz\.v \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 45e0.... bnz\.v \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 45e1ff36 bnz\.v \$w1,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 45e1.... bnz\.v \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 -+[0-9a-f]+ <[^>]*> 45e2ff34 bnz\.v \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 45e2.... bnz\.v \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 7aa2081c fsune\.d \$w0,\$w1,\$w2 +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 -+[0-9a-f]+ <[^>]*> 45e0ff31 bnz\.v \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 45e0.... bnz\.v \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 45e1ff2f bnz\.v \$w1,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 45e1.... bnz\.v \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 -+[0-9a-f]+ <[^>]*> 45e2ff2d bnz\.v \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 45e2.... bnz\.v \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46020800 add\.s \$f0,\$f1,\$f2 +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 -+[0-9a-f]+ <[^>]*> 45e0ff2a bnz\.v \$w0,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 45e0.... bnz\.v \$w0,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 00000000 nop ++[0-9a-f]+ <[^>]*> 45e1.... bnz\.v \$w1,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 -+[0-9a-f]+ <[^>]*> 45e1ff27 bnz\.v \$w1,[0-9a-f]+ -+[0-9a-f]+ <[^>]*> 00000000 nop -+[0-9a-f]+ <[^>]*> 45e2ff25 bnz\.v \$w2,[0-9a-f]+ ++[0-9a-f]+ <[^>]*> 45e2.... bnz\.v \$w2,[0-9a-f]+ +[0-9a-f]+ <[^>]*> 46241000 add\.d \$f0,\$f2,\$f4 + \.\.\. diff --git a/gas/testsuite/gas/mips/msa-branch.s b/gas/testsuite/gas/mips/msa-branch.s @@ -1740163,6 +1748651,184 @@ index 0000000..045c04d +text_label: + lwxc1 $f1,$4($5) + swxc1 $f3,$4($5) +diff --git a/gas/testsuite/gas/mips/pcrel-1.d b/gas/testsuite/gas/mips/pcrel-1.d +new file mode 100644 +index 0000000..5c9f655 +--- /dev/null ++++ b/gas/testsuite/gas/mips/pcrel-1.d +@@ -0,0 +1,14 @@ ++#objdump: -dr ++#name: Locally-resolvable PC-relative code references ++ ++.*: file format .* ++ ++Disassembly of section .text: ++ ++00000000 : ++ 0: 3c040001 lui a0,0x1 ++ 4: 2484800c addiu a0,a0,-32756 ++ ... ++ ++00008010 : ++#pass +diff --git a/gas/testsuite/gas/mips/pcrel-1.s b/gas/testsuite/gas/mips/pcrel-1.s +new file mode 100644 +index 0000000..ba93a5b +--- /dev/null ++++ b/gas/testsuite/gas/mips/pcrel-1.s +@@ -0,0 +1,13 @@ ++ .text ++ .ent func ++func: ++ lui $4,%hi(foo-.) ++ addiu $4,%lo(foo-.) ++ .end func ++ ++ .space 0x8008 ++ ++ .ent foo ++foo: ++ nop ++ .end foo +diff --git a/gas/testsuite/gas/mips/pcrel-2.d b/gas/testsuite/gas/mips/pcrel-2.d +new file mode 100644 +index 0000000..e1692e0 +--- /dev/null ++++ b/gas/testsuite/gas/mips/pcrel-2.d +@@ -0,0 +1,8 @@ ++#objdump: -s ++#name: Locally-resolvable PC-relative data references ++#as: -EB ++ ++#... ++Contents of section \.data: ++ 0000 ff0f000e 0000000c 00000000 00000008 .* ++#pass +diff --git a/gas/testsuite/gas/mips/pcrel-2.s b/gas/testsuite/gas/mips/pcrel-2.s +new file mode 100644 +index 0000000..781141e +--- /dev/null ++++ b/gas/testsuite/gas/mips/pcrel-2.s +@@ -0,0 +1,7 @@ ++ .data ++ .byte 0xff ++ .byte frob-. ++ .half frob-. ++ .word frob-. ++ .quad frob-. ++frob: +diff --git a/gas/testsuite/gas/mips/pcrel-3.l b/gas/testsuite/gas/mips/pcrel-3.l +new file mode 100644 +index 0000000..f2bfc51 +--- /dev/null ++++ b/gas/testsuite/gas/mips/pcrel-3.l +@@ -0,0 +1,7 @@ ++.*: Assembler messages: ++.*:4: Error: PC-relative reference to a different section ++.*:5: Error: PC-relative reference to a different section ++.*:6: Error: PC-relative reference to a different section ++.*:9: Error: PC-relative reference to a different section ++.*:10: Error: PC-relative reference to a different section ++.*:11: Error: PC-relative reference to a different section +diff --git a/gas/testsuite/gas/mips/pcrel-3.s b/gas/testsuite/gas/mips/pcrel-3.s +new file mode 100644 +index 0000000..6db741c +--- /dev/null ++++ b/gas/testsuite/gas/mips/pcrel-3.s +@@ -0,0 +1,11 @@ ++ .text ++ .ent func ++func: ++ lui $4,%hi(foo-.) ++ addiu $4,%lo(foo-.) ++ lw $4,%got(foo-.)($gp) ++ .end func ++ ++ .byte foo-. ++ .half foo-. ++ .quad foo-. +diff --git a/gas/testsuite/gas/mips/pcrel-4-32.d b/gas/testsuite/gas/mips/pcrel-4-32.d +new file mode 100644 +index 0000000..06bc52b +--- /dev/null ++++ b/gas/testsuite/gas/mips/pcrel-4-32.d +@@ -0,0 +1,18 @@ ++#objdump: -sr ++#name: Valid cross-section PC-relative references (o32) ++#as: -32 -EB ++#source: pcrel-4.s ++ ++.*: file format .* ++ ++RELOCATION RECORDS FOR \[\.data\]: ++OFFSET TYPE VALUE ++00000000 R_MIPS_PC32 foo ++00000004 R_MIPS_PC32 foo ++00000008 R_MIPS_PC32 foo ++0000000c R_MIPS_PC32 foo ++ ++#... ++Contents of section \.data: ++ 0000 00000000 00000004 00000008 fffffff0 ................ ++#pass +diff --git a/gas/testsuite/gas/mips/pcrel-4-64.d b/gas/testsuite/gas/mips/pcrel-4-64.d +new file mode 100644 +index 0000000..931ff96 +--- /dev/null ++++ b/gas/testsuite/gas/mips/pcrel-4-64.d +@@ -0,0 +1,21 @@ ++#objdump: -r ++#name: Valid cross-section PC-relative references (n64) ++#as: -64 -mips3 ++#source: pcrel-4.s ++ ++.*: file format .* ++ ++RELOCATION RECORDS FOR \[\.data\]: ++OFFSET TYPE VALUE ++0+000 R_MIPS_PC32 foo ++0+000 R_MIPS_NONE \*ABS\* ++0+000 R_MIPS_NONE \*ABS\* ++0+004 R_MIPS_PC32 foo\+0x0+004 ++0+004 R_MIPS_NONE \*ABS\*\+0x0+004 ++0+004 R_MIPS_NONE \*ABS\*\+0x0+004 ++0+008 R_MIPS_PC32 foo\+0x0+008 ++0+008 R_MIPS_NONE \*ABS\*\+0x0+008 ++0+008 R_MIPS_NONE \*ABS\*\+0x0+008 ++0+00c R_MIPS_PC32 foo-0x0+010 ++0+00c R_MIPS_NONE \*ABS\*-0x0+010 ++0+00c R_MIPS_NONE \*ABS\*-0x0+010 +diff --git a/gas/testsuite/gas/mips/pcrel-4-n32.d b/gas/testsuite/gas/mips/pcrel-4-n32.d +new file mode 100644 +index 0000000..56ec6ef +--- /dev/null ++++ b/gas/testsuite/gas/mips/pcrel-4-n32.d +@@ -0,0 +1,13 @@ ++#objdump: -r ++#name: Valid cross-section PC-relative references (n32) ++#as: -n32 -mips3 ++#source: pcrel-4.s ++ ++.*: file format .* ++ ++RELOCATION RECORDS FOR \[\.data\]: ++OFFSET TYPE VALUE ++00000000 R_MIPS_PC32 foo ++00000004 R_MIPS_PC32 foo\+0x00000004 ++00000008 R_MIPS_PC32 foo\+0x00000008 ++0000000c R_MIPS_PC32 foo-0x00000010 +diff --git a/gas/testsuite/gas/mips/pcrel-4.s b/gas/testsuite/gas/mips/pcrel-4.s +new file mode 100644 +index 0000000..8f332dc +--- /dev/null ++++ b/gas/testsuite/gas/mips/pcrel-4.s +@@ -0,0 +1,6 @@ ++ .data ++ .word foo-. ++ .word foo-(.-4) ++ .word foo+8-. ++ .word foo-.-16 ++ diff --git a/gas/testsuite/gas/mips/perfcount.d b/gas/testsuite/gas/mips/perfcount.d new file mode 100644 index 0000000..1f0203a @@ -1740458,6 +1749124,36 @@ index 0000000..4a08606 +#name: MIPS s.d +#source: ld.s +#dump: mips1@s_d.d +diff --git a/gas/testsuite/gas/mips/r5.d b/gas/testsuite/gas/mips/r5.d +new file mode 100644 +index 0000000..d1073fe +--- /dev/null ++++ b/gas/testsuite/gas/mips/r5.d +@@ -0,0 +1,8 @@ ++#objdump: -dr --prefix-addresses --show-raw-insn ++#name: Test MIPS32r5 instructions ++ ++.*: +file format .*mips.* ++ ++Disassembly of section \.text: ++[0-9a-f]+ <[^>]*> 42000058 eretnc ++ ... +diff --git a/gas/testsuite/gas/mips/r5.s b/gas/testsuite/gas/mips/r5.s +new file mode 100644 +index 0000000..12260d3 +--- /dev/null ++++ b/gas/testsuite/gas/mips/r5.s +@@ -0,0 +1,10 @@ ++ .text ++ .set noat ++ .set noreorder ++ .set nomacro ++test_r5: ++ eretnc ++ ++# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... ++ .align 2 ++ .space 8 diff --git a/gas/testsuite/gas/mips/r5900-all-vu0.d b/gas/testsuite/gas/mips/r5900-all-vu0.d new file mode 100644 index 0000000..9528c6e @@ -1778129,6 +1786825,71 @@ index 0000000..b92708a + +# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... + .space 8 +diff --git a/gas/testsuite/gas/mips/xpa.d b/gas/testsuite/gas/mips/xpa.d +new file mode 100644 +index 0000000..f1047c9 +--- /dev/null ++++ b/gas/testsuite/gas/mips/xpa.d +@@ -0,0 +1,24 @@ ++#objdump: -dr --prefix-addresses --show-raw-insn -Mxpa,cp0-names=mips32r2 ++#name: XPA instructions ++#as: -32 -mxpa ++ ++.*: +file format .*mips.* ++ ++Disassembly of section \.text: ++[0-9a-f]+ <[^>]*> 40420800 mfhc0 v0,c0_random ++[0-9a-f]+ <[^>]*> 40428000 mfhc0 v0,c0_config ++[0-9a-f]+ <[^>]*> 40420002 mfhc0 v0,c0_mvpconf0 ++[0-9a-f]+ <[^>]*> 40420007 mfhc0 v0,\$0,7 ++[0-9a-f]+ <[^>]*> 40c20800 mthc0 v0,c0_random ++[0-9a-f]+ <[^>]*> 40c28000 mthc0 v0,c0_config ++[0-9a-f]+ <[^>]*> 40c20002 mthc0 v0,c0_mvpconf0 ++[0-9a-f]+ <[^>]*> 40c20007 mthc0 v0,\$0,7 ++[0-9a-f]+ <[^>]*> 40620c00 mfhgc0 v0,c0_random ++[0-9a-f]+ <[^>]*> 40628400 mfhgc0 v0,c0_config ++[0-9a-f]+ <[^>]*> 40620402 mfhgc0 v0,c0_mvpconf0 ++[0-9a-f]+ <[^>]*> 40620407 mfhgc0 v0,\$0,7 ++[0-9a-f]+ <[^>]*> 40620e00 mthgc0 v0,c0_random ++[0-9a-f]+ <[^>]*> 40628600 mthgc0 v0,c0_config ++[0-9a-f]+ <[^>]*> 40620602 mthgc0 v0,c0_mvpconf0 ++[0-9a-f]+ <[^>]*> 40620607 mthgc0 v0,\$0,7 ++ ... +diff --git a/gas/testsuite/gas/mips/xpa.s b/gas/testsuite/gas/mips/xpa.s +new file mode 100644 +index 0000000..4d91f75 +--- /dev/null ++++ b/gas/testsuite/gas/mips/xpa.s +@@ -0,0 +1,29 @@ ++ .text ++ .set noat ++ .set noreorder ++ .set nomacro ++test_xpa: ++ ++ mfhc0 $2, $1 ++ mfhc0 $2, $16 ++ mfhc0 $2, $0, 2 ++ mfhc0 $2, $0, 7 ++ ++ mthc0 $2, $1 ++ mthc0 $2, $16 ++ mthc0 $2, $0, 2 ++ mthc0 $2, $0, 7 ++ ++ mfhgc0 $2, $1 ++ mfhgc0 $2, $16 ++ mfhgc0 $2, $0, 2 ++ mfhgc0 $2, $0, 7 ++ ++ mthgc0 $2, $1 ++ mthgc0 $2, $16 ++ mthgc0 $2, $0, 2 ++ mthgc0 $2, $0, 7 ++ ++# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... ++ .align 2 ++ .space 8 diff --git a/gas/testsuite/gas/mmix/1cjmp1b-n.d b/gas/testsuite/gas/mmix/1cjmp1b-n.d new file mode 100644 index 0000000..ddc4191 @@ -1783591,11 +1792352,11 @@ index 0000000..9550bd1 +LC23 SWYM 14 diff --git a/gas/testsuite/gas/mmix/mmix-err.exp b/gas/testsuite/gas/mmix/mmix-err.exp new file mode 100644 -index 0000000..fab4c1d +index 0000000..9ed9087 --- /dev/null +++ b/gas/testsuite/gas/mmix/mmix-err.exp @@ -0,0 +1,30 @@ -+# Copyright (C) 2001, 2005, 2007 Free Software Foundation, Inc. ++# Copyright (C) 2001-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1783627,11 +1792388,11 @@ index 0000000..fab4c1d +run_mmix_err_tests diff --git a/gas/testsuite/gas/mmix/mmix-list.exp b/gas/testsuite/gas/mmix/mmix-list.exp new file mode 100644 -index 0000000..a93b74d +index 0000000..903b88f --- /dev/null +++ b/gas/testsuite/gas/mmix/mmix-list.exp @@ -0,0 +1,30 @@ -+# Copyright (C) 2001, 2005, 2007 Free Software Foundation, Inc. ++# Copyright (C) 2001-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1783663,11 +1792424,11 @@ index 0000000..a93b74d +run_mmix_list_tests diff --git a/gas/testsuite/gas/mmix/mmix.exp b/gas/testsuite/gas/mmix/mmix.exp new file mode 100644 -index 0000000..e4d5f06 +index 0000000..f1f5c69 --- /dev/null +++ b/gas/testsuite/gas/mmix/mmix.exp @@ -0,0 +1,38 @@ -+# Copyright (C) 2001, 2005, 2007 Free Software Foundation, Inc. ++# Copyright (C) 2001-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1788519,11 +1797280,11 @@ index 0000000..ed251bc + addnf 16,a2 diff --git a/gas/testsuite/gas/mn10200/basic.exp b/gas/testsuite/gas/mn10200/basic.exp new file mode 100644 -index 0000000..85f9bf1 +index 0000000..46a5340 --- /dev/null +++ b/gas/testsuite/gas/mn10200/basic.exp @@ -0,0 +1,836 @@ -+# Copyright (C) 1996, 2002, 2005, 2007 Free Software Foundation, Inc. ++# Copyright (C) 1996-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1789651,11 +1798412,11 @@ index 0000000..16f558f + addc d1,d2 diff --git a/gas/testsuite/gas/mn10300/am33-2.c b/gas/testsuite/gas/mn10300/am33-2.c new file mode 100644 -index 0000000..9783b2b +index 0000000..633db8b --- /dev/null +++ b/gas/testsuite/gas/mn10300/am33-2.c @@ -0,0 +1,745 @@ -+/* Copyright (C) 2000, 2002, 2005, 2007 Free Software Foundation ++/* Copyright (C) 2000-2014 Free Software Foundation, Inc. + Contributed by Alexandre Oliva + + This file is free software; you can redistribute it and/or modify it @@ -1793569,12 +1802330,11 @@ index 0000000..b2a96d9 + diff --git a/gas/testsuite/gas/mn10300/basic.exp b/gas/testsuite/gas/mn10300/basic.exp new file mode 100644 -index 0000000..f84022d +index 0000000..ed54cf4 --- /dev/null +++ b/gas/testsuite/gas/mn10300/basic.exp -@@ -0,0 +1,1810 @@ -+# Copyright (C) 1996, 2000, 2002, 2004, 2005, 2007 -+# Free Software Foundation, Inc. +@@ -0,0 +1,1809 @@ ++# Copyright (C) 1996-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1796637,12 +1805397,11 @@ index 0000000..b8fc728 + movem.l asdf,fdsa diff --git a/gas/testsuite/gas/mri/mri.exp b/gas/testsuite/gas/mri/mri.exp new file mode 100644 -index 0000000..c5accc7 +index 0000000..3acf921 --- /dev/null +++ b/gas/testsuite/gas/mri/mri.exp -@@ -0,0 +1,52 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,51 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1796816,19 +1805575,20 @@ index 0000000..35cbdbb + nop diff --git a/gas/testsuite/gas/msp430/bad.d b/gas/testsuite/gas/msp430/bad.d new file mode 100644 -index 0000000..9302cee +index 0000000..749759e --- /dev/null +++ b/gas/testsuite/gas/msp430/bad.d -@@ -0,0 +1,3 @@ +@@ -0,0 +1,4 @@ +#name: Diagnostics Quality +#source: bad.s ++#as: -my +#error-output: bad.l diff --git a/gas/testsuite/gas/msp430/bad.l b/gas/testsuite/gas/msp430/bad.l new file mode 100644 -index 0000000..218dcd0 +index 0000000..8de1338 --- /dev/null +++ b/gas/testsuite/gas/msp430/bad.l -@@ -0,0 +1,7 @@ +@@ -0,0 +1,14 @@ +[^:]*: Assembler messages: +[^:]*:6: Error: unrecognised instruction size modifier .z +[^:]*:7: Error: junk found after instruction: mov.bc r1,r2 @@ -1796836,12 +1805596,19 @@ index 0000000..218dcd0 +[^:]*:9: Error: junk found after instruction: mov.cd r1,r2 +[^:]*:10: Warning: no size modifier after period, .w assumed +[^:]*:11: Error: instruction bis.a does not exist ++[^:]*:19: Warning: a NOP might be needed here because of successive changes in interrupt state ++[^:]*:20: Warning: a NOP might be needed here because of successive changes in interrupt state ++[^:]*:25: Warning: a NOP might be needed here because of successive changes in interrupt state ++[^:]*:26: Warning: a NOP might be needed here because of successive changes in interrupt state ++[^:]*:27: Warning: a NOP might be needed here because of successive changes in interrupt state ++[^:]*:28: Warning: a NOP might be needed here because of successive changes in interrupt state ++[^:]*: Warning: assembly finished with the last instruction changing interrupt state - a NOP might be needed diff --git a/gas/testsuite/gas/msp430/bad.s b/gas/testsuite/gas/msp430/bad.s new file mode 100644 -index 0000000..2af83b7 +index 0000000..b9c4af2 --- /dev/null +++ b/gas/testsuite/gas/msp430/bad.s -@@ -0,0 +1,13 @@ +@@ -0,0 +1,31 @@ + .text + .cpu 430x + @@ -1796855,13 +1805622,31 @@ index 0000000..2af83b7 + bis.a #8, r2 + +;;; FIXME: Add more tests of assembler error detection here. ++ ++ ;; Changing interrupt states in two successive instructions ++ ;; might cause an interrupt to be missed. The assembler ++ ;; should warn about this, if the -mz command line option ++ ;; is used. ++ eint ++ dint ++ nop ;; No warning needed here. ++ dint ++ and #1, r11 ;; Any instruction will do, not just NOPs. ++ clr r2 ;; Aliases should trigger the warning too. ++ mov #1, r2 ++ BIC #8, SR ++ BIS #8, SR ++ MOV.W #1, SR ++ ;; We will also get a warning if the last instruction in the file ++ ;; changes the interrupt state, since this file could be linked ++ ;; with another that starts with an interrupt change. diff --git a/gas/testsuite/gas/msp430/msp430.exp b/gas/testsuite/gas/msp430/msp430.exp new file mode 100644 -index 0000000..0b5a3ae +index 0000000..46b261d --- /dev/null +++ b/gas/testsuite/gas/msp430/msp430.exp @@ -0,0 +1,25 @@ -+# Copyright 2012-2013 Free Software Foundation, Inc. ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1796888,7 +1805673,7 @@ index 0000000..0b5a3ae +} diff --git a/gas/testsuite/gas/msp430/msp430x.d b/gas/testsuite/gas/msp430/msp430x.d new file mode 100644 -index 0000000..e080854 +index 0000000..6bd6db3 --- /dev/null +++ b/gas/testsuite/gas/msp430/msp430x.d @@ -0,0 +1,227 @@ @@ -1796911,59 +1805696,59 @@ index 0000000..e080854 +0+0026 <[^>]*> 40 18 20 59 addx.w @r9, r0 ; +0+002a <[^>]*> 40 18 00 59 addx.w r9, r0 ; +0+002e <[^>]*> 00 18 70 50 00 00 addx.a #0, r0 ; -+0+0034 <[^>]*> 00 18 50 52 00 00 addx.a &0x0000,r0 ;0x0000 ++0+0034 <[^>]*> 00 18 50 52 00 00 addx.a &0x00000,r0 ; +0+003a <[^>]*> 00 18 70 59 addx.a @r9\+, r0 ; -+0+003e <[^>]*> 00 18 50 50 00 00 addx.a 0x0000, r0 ;PC rel. 0x0042 ++0+003e <[^>]*> 00 18 50 50 00 00 addx.a 0x00000,r0 ;PC rel. 0x00042 +0+0044 <[^>]*> 40 18 42 51 addx.b r1, r2 ; +0+0048 <[^>]*> 40 18 04 53 addx.w #0, r4 ;r3 As==00 +0+004c <[^>]*> 40 18 15 54 00 00 addx.w 0\(r4\), r5 ; -+0+0052 <[^>]*> 40 18 b6 f0 d2 04 04 00 andx.w #1234, 4\(r6\) ;#0x04d2 ++0+0052 <[^>]*> 40 18 b6 f0 d2 04 04 00 andx.w #1234, 4\(r6\) ;0x004d2 +0+005a <[^>]*> 40 18 96 f7 04 00 04 00 andx.w 4\(r7\), 4\(r6\) ; +0+0062 <[^>]*> 40 18 b6 f5 04 00 andx.w @r5\+, 4\(r6\) ; -+0+0068 <[^>]*> 40 18 96 f0 00 00 04 00 andx.w 0x0000, 4\(r6\) ;PC rel. 0x006c -+0+0070 <[^>]*> 40 18 90 f0 00 00 00 00 andx.w 0x0000, 0x0000 ;PC rel. 0x0074, PC rel. 0x0076 ++0+0068 <[^>]*> 40 18 96 f0 00 00 04 00 andx.w 0x00000,4\(r6\) ;PC rel. 0x0006c ++0+0070 <[^>]*> 40 18 90 f0 00 00 00 00 andx.w 0x00000,0x00000 ;PC rel. 0x00074, PC rel. 0x00076 +0+0078 <[^>]*> 00 18 e6 f5 04 00 andx.a @r5, 4\(r6\) ; +0+007e <[^>]*> 00 18 c6 f5 04 00 andx.a r5, 4\(r6\) ; -+0+0084 <[^>]*> 40 18 d6 f2 00 00 04 00 andx.b &0x0000,4\(r6\) ;0x0000 ++0+0084 <[^>]*> 40 18 d6 f2 00 00 04 00 andx.b &0x00000,4\(r6\) ; +0+008c <[^>]*> 40 18 02 f1 andx.w r1, r2 ; -+0+0090 <[^>]*> 40 18 3e c0 a0 00 bicx.w #160, r14 ;#0x00a0 -+0+0096 <[^>]*> 00 18 7e c0 a0 00 bicx.a #160, r14 ;#0x00a0 -+0+009c <[^>]*> 40 18 7e c0 a0 00 bicx.b #160, r14 ;#0x00a0 -+0+00a2 <[^>]*> 40 18 3e c0 a0 00 bicx.w #160, r14 ;#0x00a0 ++0+0090 <[^>]*> 40 18 3e c0 a0 00 bicx.w #160, r14 ;0x000a0 ++0+0096 <[^>]*> 00 18 7e c0 a0 00 bicx.a #160, r14 ;0x000a0 ++0+009c <[^>]*> 40 18 7e c0 a0 00 bicx.b #160, r14 ;0x000a0 ++0+00a2 <[^>]*> 40 18 3e c0 a0 00 bicx.w #160, r14 ;0x000a0 +0+00a8 <[^>]*> 40 18 3b d2 bisx.w #8, r11 ;r2 As==11 +0+00ac <[^>]*> 00 18 7b d2 bisx.a #8, r11 ;r2 As==11 +0+00b0 <[^>]*> 40 18 7b d2 bisx.b #8, r11 ;r2 As==11 +0+00b4 <[^>]*> 40 18 3b d2 bisx.w #8, r11 ;r2 As==11 -+0+00b8 <[^>]*> 40 18 38 b0 14 00 bitx.w #20, r8 ;#0x0014 -+0+00be <[^>]*> 40 18 92 b2 00 00 00 00 bitx.w &0x0000,&0x0000 ;0x0000 -+0+00c6 <[^>]*> 40 18 18 b2 00 00 bitx.w &0x0000,r8 ;0x0000 ++0+00b8 <[^>]*> 40 18 38 b0 14 00 bitx.w #20, r8 ;0x00014 ++0+00be <[^>]*> 40 18 92 b2 00 00 00 00 bitx.w &0x00000,&0x00000; ++0+00c6 <[^>]*> 40 18 18 b2 00 00 bitx.w &0x00000,r8 ; +0+00cc <[^>]*> 40 18 18 b5 02 00 bitx.w 2\(r5\), r8 ; -+0+00d2 <[^>]*> 40 18 92 b1 08 00 00 00 bitx.w 8\(r1\), &0x0000 ; -+0+00da <[^>]*> 40 18 b2 b5 00 00 bitx.w @r5\+, &0x0000 ; ++0+00d2 <[^>]*> 40 18 92 b1 08 00 00 00 bitx.w 8\(r1\), &0x00000; ++0+00da <[^>]*> 40 18 b2 b5 00 00 bitx.w @r5\+, &0x00000; +0+00e0 <[^>]*> 40 18 38 b5 bitx.w @r5\+, r8 ; +0+00e4 <[^>]*> 40 18 28 b5 bitx.w @r5, r8 ; -+0+00e8 <[^>]*> 40 18 92 b0 00 00 00 00 bitx.w 0x0000, &0x0000 ;PC rel. 0x00ec -+0+00f0 <[^>]*> 40 18 f2 b0 0c 00 00 00 bitx.b #12, &0x0000 ;#0x000c -+0+00f8 <[^>]*> 40 18 e2 b5 00 00 bitx.b @r5, &0x0000 ; -+0+00fe <[^>]*> 40 18 58 b0 00 00 bitx.b 0x0000, r8 ;PC rel. 0x0102 ++0+00e8 <[^>]*> 40 18 92 b0 00 00 00 00 bitx.w 0x00000,&0x00000;PC rel. 0x000ec ++0+00f0 <[^>]*> 40 18 f2 b0 0c 00 00 00 bitx.b \#12, &0x00000;0x0000c ++0+00f8 <[^>]*> 40 18 e2 b5 00 00 bitx.b @r5, &0x00000; ++0+00fe <[^>]*> 40 18 58 b0 00 00 bitx.b 0x00000,r8 ;PC rel. 0x00102 +0+0104 <[^>]*> 40 18 48 b5 bitx.b r5, r8 ; -+0+0108 <[^>]*> 40 18 82 b5 00 00 bitx.w r5, &0x0000 ; -+0+010e <[^>]*> 40 18 80 43 00 00 movx.w #0, 0x0000 ;r3 As==00, PC rel. 0x0112 -+0+0114 <[^>]*> 00 18 c0 43 00 00 movx.a #0, 0x0000 ;r3 As==00, PC rel. 0x0118 -+0+011a <[^>]*> 40 18 c0 43 00 00 movx.b #0, 0x0000 ;r3 As==00, PC rel. 0x011e -+0+0120 <[^>]*> 40 18 80 43 00 00 movx.w #0, 0x0000 ;r3 As==00, PC rel. 0x0124 ++0+0108 <[^>]*> 40 18 82 b5 00 00 bitx.w r5, &0x00000; ++0+010e <[^>]*> 40 18 80 43 00 00 movx.w #0, 0x00000 ;r3 As==00, PC rel. 0x00112 ++0+0114 <[^>]*> 00 18 c0 43 00 00 movx.a #0, 0x00000 ;r3 As==00, PC rel. 0x00118 ++0+011a <[^>]*> 40 18 c0 43 00 00 movx.b #0, 0x00000 ;r3 As==00, PC rel. 0x0011e ++0+0120 <[^>]*> 40 18 80 43 00 00 movx.w #0, 0x00000 ;r3 As==00, PC rel. 0x00124 +0+0126 <[^>]*> 40 18 0f 93 cmpx.w #0, r15 ;r3 As==00 -+0+012a <[^>]*> 00 18 f0 90 00 18 00 00 cmpx.a #6144, 0x0000 ;#0x1800, PC rel. 0x0130 ++0+012a <[^>]*> 00 18 f0 90 00 18 00 00 cmpx.a #6144, 0x00000 ;0x01800, PC rel. 0x00130 +0+0132 <[^>]*> 40 18 6f 91 cmpx.b @r1, r15 ; -+0+0136 <[^>]*> 40 18 b2 92 00 00 cmpx.w #8, &0x0000 ;r2 As==11 ++0+0136 <[^>]*> 40 18 b2 92 00 00 cmpx.w #8, &0x00000;r2 As==11 +0+013c <[^>]*> 40 18 80 a3 00 00 dadcx.w 0x0000 ;PC rel. abs addr 0x0140 +0+0142 <[^>]*> 00 18 cc a3 00 00 dadcx.a 0\(r12\) ; +0+0148 <[^>]*> 40 18 c0 a3 00 00 dadcx.b 0x0000 ;PC rel. abs addr 0x014c +0+014e <[^>]*> 40 18 0c a3 dadcx.w r12 ; +0+0152 <[^>]*> 40 18 27 a5 daddx.w @r5, r7 ; -+0+0156 <[^>]*> 00 18 f2 a0 10 00 00 00 daddx.a #16, &0x0000 ;#0x0010 ++0+0156 <[^>]*> 00 18 f2 a0 10 00 00 00 daddx.a #16, &0x00000;0x00010 +0+015e <[^>]*> 40 18 54 a6 02 00 daddx.b 2\(r6\), r4 ; -+0+0164 <[^>]*> 40 18 14 a0 00 00 daddx.w 0x0000, r4 ;PC rel. 0x0168 ++0+0164 <[^>]*> 40 18 14 a0 00 00 daddx.w 0x00000,r4 ;PC rel. 0x00168 +0+016a <[^>]*> 40 18 90 83 00 00 decx.w 0x0000 ;PC rel. abs addr 0x016e +0+0170 <[^>]*> 00 18 d0 83 00 00 decx.a 0x0000 ;PC rel. abs addr 0x0174 +0+0176 <[^>]*> 40 18 d0 83 00 00 decx.b 0x0000 ;PC rel. abs addr 0x017a @@ -1796981,23 +1805766,23 @@ index 0000000..e080854 +0+01b2 <[^>]*> 40 18 6a 53 incdx.b r10 ; +0+01b6 <[^>]*> 40 18 2b 53 incdx.w r11 ; +0+01ba <[^>]*> 40 18 3c e3 invx.w r12 ; -+0+01be <[^>]*> 00 18 f0 e3 00 00 xorx.a #-1, 0x0000 ;r3 As==11, PC rel. 0x01c2 ++0+01be <[^>]*> 00 18 f0 e3 00 00 xorx.a #-1, 0x00000 ;r3 As==11, PC rel. 0x001c2 +0+01c4 <[^>]*> 40 18 7e e3 xorx.b #-1, r14 ;r3 As==11 +0+01c8 <[^>]*> 40 18 3f e3 invx.w r15 ; +0+01cc <[^>]*> 40 18 34 40 00 00 movx.w #0, r4 ; +0+01d2 <[^>]*> 00 18 75 40 00 00 movx.a #0, r5 ; +0+01d8 <[^>]*> 40 18 76 40 00 00 movx.b #0, r6 ; +0+01de <[^>]*> 40 18 37 40 00 00 movx.w #0, r7 ; -+0+01e4 <[^>]*> 40 18 15 42 00 00 movx.w &0x0000,r5 ;0x0000 ++0+01e4 <[^>]*> 40 18 15 42 00 00 movx.w &0x00000,r5 ; +0+01ea <[^>]*> 40 18 35 40 00 00 movx.w #0, r5 ; -+0+01f0 <[^>]*> 40 18 82 45 00 00 movx.w r5, &0x0000 ; -+0+01f6 <[^>]*> 40 1d b2 40 de bc 00 00 movx.w #-344866,&0x0000 ;0xabcde -+0+01fe <[^>]*> 40 18 92 42 00 00 00 00 movx.w &0x0000,&0x0000 ;0x0000 -+0+0206 <[^>]*> 40 18 b2 40 00 00 00 00 movx.w #0, &0x0000 ; -+0+020e <[^>]*> 40 18 15 40 00 00 movx.w 0x0000, r5 ;PC rel. 0x0212 -+0+0214 <[^>]*> 40 18 80 45 00 00 movx.w r5, 0x0000 ; PC rel. 0x0218 -+0+021a <[^>]*> 40 1d b0 40 de bc 00 00 movx.w #-344866,0x0000 ;0xabcde, PC rel. 0x0220 -+0+0222 <[^>]*> 40 18 90 40 00 00 00 00 movx.w 0x0000, 0x0000 ;PC rel. 0x0226, PC rel. 0x0228 ++0+01f0 <[^>]*> 40 18 82 45 00 00 movx.w r5, &0x00000; ++0+01f6 <[^>]*> 40 1d b2 40 de bc 00 00 movx.w #-344866,&0x00000;0xabcde ++0+01fe <[^>]*> 40 18 92 42 00 00 00 00 movx.w &0x00000,&0x00000; ++0+0206 <[^>]*> 40 18 b2 40 00 00 00 00 movx.w #0, &0x00000; ++0+020e <[^>]*> 40 18 15 40 00 00 movx.w 0x00000,r5 ;PC rel. 0x00212 ++0+0214 <[^>]*> 40 18 80 45 00 00 movx.w r5, 0x00000 ; PC rel. 0x00218 ++0+021a <[^>]*> 40 1d b0 40 de bc 00 00 movx.w #-344866,0x00000 ;0xabcde, PC rel. 0x00220 ++0+0222 <[^>]*> 40 18 90 40 00 00 00 00 movx.w 0x00000,0x00000 ;PC rel. 0x00226, PC rel. 0x00228 +0+022a <[^>]*> 40 18 0f 73 sbcx.w r15 ; +0+022e <[^>]*> 00 18 40 73 sbcx.a r0 ; +0+0232 <[^>]*> 40 18 4f 73 sbcx.b r15 ; @@ -1797007,22 +1805792,22 @@ index 0000000..e080854 +0+0246 <[^>]*> 40 18 4f 7f subcx.b r15, r15 ; +0+024a <[^>]*> 40 18 b7 75 00 00 subcx.w @r5\+, 0\(r7\) ; +0+0250 <[^>]*> 40 18 10 86 02 00 subx.w 2\(r6\), r0 ; -+0+0256 <[^>]*> 00 18 f0 80 67 11 00 00 subx.a #4455, 0x0000 ;#0x1167, PC rel. 0x025c ++0+0256 <[^>]*> 00 18 f0 80 67 11 00 00 subx.a #4455, 0x00000 ;0x01167, PC rel. 0x0025c +0+025e <[^>]*> 40 18 50 86 02 00 subx.b 2\(r6\), r0 ; +0+0264 <[^>]*> 40 18 10 86 02 00 subx.w 2\(r6\), r0 ; -+0+026a <[^>]*> 40 18 80 93 00 00 cmpx.w #0, 0x0000 ;r3 As==00, PC rel. 0x026e -+0+0270 <[^>]*> 00 18 c0 93 00 00 cmpx.a #0, 0x0000 ;r3 As==00, PC rel. 0x0274 -+0+0276 <[^>]*> 40 18 c0 93 00 00 cmpx.b #0, 0x0000 ;r3 As==00, PC rel. 0x027a -+0+027c <[^>]*> 40 18 80 93 00 00 cmpx.w #0, 0x0000 ;r3 As==00, PC rel. 0x0280 -+0+0282 <[^>]*> 40 18 b0 e0 5a 5a 00 00 xorx.w #23130, 0x0000 ;#0x5a5a, PC rel. 0x0288 -+0+028a <[^>]*> 40 18 90 e2 00 00 00 00 xorx.w &0x0000,0x0000 ;0x0000, PC rel. 0x0290 -+0+0292 <[^>]*> 40 18 a0 e8 00 00 xorx.w @r8, 0x0000 ; PC rel. 0x0296 -+0+0298 <[^>]*> 40 18 80 e8 00 00 xorx.w r8, 0x0000 ; PC rel. 0x029c -+0+029e <[^>]*> 40 18 d0 e6 02 00 00 00 xorx.b 2\(r6\), 0x0000 ; PC rel. 0x02a4 -+0+02a6 <[^>]*> 40 18 f0 e8 00 00 xorx.b @r8\+, 0x0000 ; PC rel. 0x02aa -+0+02ac <[^>]*> 00 18 d2 e0 00 00 00 00 xorx.a 0x0000, &0x0000 ;PC rel. 0x02b0 ++0+026a <[^>]*> 40 18 80 93 00 00 cmpx.w #0, 0x00000 ;r3 As==00, PC rel. 0x0026e ++0+0270 <[^>]*> 00 18 c0 93 00 00 cmpx.a #0, 0x00000 ;r3 As==00, PC rel. 0x00274 ++0+0276 <[^>]*> 40 18 c0 93 00 00 cmpx.b #0, 0x00000 ;r3 As==00, PC rel. 0x0027a ++0+027c <[^>]*> 40 18 80 93 00 00 cmpx.w #0, 0x00000 ;r3 As==00, PC rel. 0x00280 ++0+0282 <[^>]*> 40 18 b0 e0 5a 5a 00 00 xorx.w #23130, 0x00000 ;0x05a5a, PC rel. 0x00288 ++0+028a <[^>]*> 40 18 90 e2 00 00 00 00 xorx.w &0x00000,0x00000 ; PC rel. 0x00290 ++0+0292 <[^>]*> 40 18 a0 e8 00 00 xorx.w @r8, 0x00000 ; PC rel. 0x00296 ++0+0298 <[^>]*> 40 18 80 e8 00 00 xorx.w r8, 0x00000 ; PC rel. 0x0029c ++0+029e <[^>]*> 40 18 d0 e6 02 00 00 00 xorx.b 2\(r6\), 0x00000 ; PC rel. 0x002a4 ++0+02a6 <[^>]*> 40 18 f0 e8 00 00 xorx.b @r8\+, 0x00000 ; PC rel. 0x002aa ++0+02ac <[^>]*> 00 18 d2 e0 00 00 00 00 xorx.a 0x00000,&0x00000;PC rel. 0x002b0 +0+02b4 <[^>]*> 40 18 26 e5 xorx.w @r5, r6 ; -+0+02b8 <[^>]*> 04 18 ff e0 39 30 78 56 xorx.a #12345, 284280\(r15\);#0x3039, 0x45678 ++0+02b8 <[^>]*> 04 18 ff e0 39 30 78 56 xorx.a #12345, 284280\(r15\);0x03039, 0x45678 +0+02c0 <[^>]*> a7 01 45 23 adda #74565, r7 ;0x12345 +0+02c4 <[^>]*> ee 06 adda r6, r14 ; +0+02c6 <[^>]*> 80 00 00 00 mova #0, r0 ; @@ -1797056,7 +1805841,7 @@ index 0000000..e080854 +0+0320 <[^>]*> 00 13 reti +0+0322 <[^>]*> f6 05 suba r5, r6 ; +0+0324 <[^>]*> b6 0f ff ff suba #1048575,r6 ;0xfffff -+0+0328 <[^>]*> 40 18 80 93 00 00 cmpx.w #0, 0x0000 ;r3 As==00, PC rel. 0x032c ++0+0328 <[^>]*> 40 18 80 93 00 00 cmpx.w #0, 0x00000 ;r3 As==00, PC rel. 0x0032c +0+032e <[^>]*> 05 17 popm #1, r5 ;16-bit words +0+0330 <[^>]*> 2d 16 popm.a #3, r15 ;20-bit words +0+0332 <[^>]*> 75 17 popm #8, r12 ;16-bit words @@ -1797118,7 +1805903,7 @@ index 0000000..e080854 +0+03e8 <[^>]*> c2 01 mova r1, r2 ; +0+03ea <[^>]*> 10 01 reta ; +0+03ec <[^>]*> f2 01 suba r1, r2 ; -+0+03ee <[^>]*> 40 18 80 93 00 00 cmpx.w #0, 0x0000 ;r3 As==00, PC rel. 0x03f2 ++0+03ee <[^>]*> 40 18 80 93 00 00 cmpx.w #0, 0x00000 ;r3 As==00, PC rel. 0x003f2 diff --git a/gas/testsuite/gas/msp430/msp430x.s b/gas/testsuite/gas/msp430/msp430x.s new file mode 100644 index 0000000..d968fae @@ -1797938,12 +1806723,11 @@ index 0000000..8df8215 +andi R1,R2,#-1 diff --git a/gas/testsuite/gas/mt/errors.exp b/gas/testsuite/gas/mt/errors.exp new file mode 100644 -index 0000000..c8a9f68 +index 0000000..cac9334 --- /dev/null +++ b/gas/testsuite/gas/mt/errors.exp -@@ -0,0 +1,96 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,95 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1798453,12 +1807237,11 @@ index 0000000..4ec028c + intlvr R0, #0, R0, #0, #0 diff --git a/gas/testsuite/gas/mt/mt.exp b/gas/testsuite/gas/mt/mt.exp new file mode 100644 -index 0000000..0bb9e5e +index 0000000..474b9dd --- /dev/null +++ b/gas/testsuite/gas/mt/mt.exp -@@ -0,0 +1,28 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,27 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1798561,12 +1807344,11 @@ index 0000000..8546367 + 2030: 00 67 50 00 add R5,R6,R7 diff --git a/gas/testsuite/gas/mt/relocs.exp b/gas/testsuite/gas/mt/relocs.exp new file mode 100644 -index 0000000..15335d9 +index 0000000..0e4d291 --- /dev/null +++ b/gas/testsuite/gas/mt/relocs.exp -@@ -0,0 +1,52 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,51 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1799084,11 +1807866,11 @@ index 0000000..a2dd62a + sbi.bi $r0, [$r1], 1 diff --git a/gas/testsuite/gas/nds32/nds32.exp b/gas/testsuite/gas/nds32/nds32.exp new file mode 100644 -index 0000000..9686e6a +index 0000000..100fafd --- /dev/null +++ b/gas/testsuite/gas/nds32/nds32.exp @@ -0,0 +1,32 @@ -+# Copyright (C) 2012-2013 Free Software Foundation, Inc. ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# Contributed by Andes Technology Corporation. + +# This program is free software; you can redistribute it and/or modify @@ -1800151,6 +1808933,144 @@ index 0000000..dd128a7 +.align 8 +localfunc: + nop +diff --git a/gas/testsuite/gas/nios2/call26_noat.d b/gas/testsuite/gas/nios2/call26_noat.d +new file mode 100644 +index 0000000..34bfe4e +--- /dev/null ++++ b/gas/testsuite/gas/nios2/call26_noat.d +@@ -0,0 +1,76 @@ ++#objdump: -dr --prefix-addresses --show-raw-insn ++#name: NIOS2 nios2-reloc-r-nios2-call26-noat ++ ++# Test the branch instructions. ++.*: +file format elf32-littlenios2 ++ ++Disassembly of section .text: ++[ ]*\.\.\. ++[ ]*0: R_NIOS2_CALL26_NOAT .text\+0x100 ++[ ]*4: R_NIOS2_CALL26_NOAT globalfunc ++0+0008 <[^>]*> 0001883a nop ++0+000c <[^>]*> 0001883a nop ++0+0010 <[^>]*> 0001883a nop ++0+0014 <[^>]*> 0001883a nop ++0+0018 <[^>]*> 0001883a nop ++0+001c <[^>]*> 0001883a nop ++0+0020 <[^>]*> 0001883a nop ++0+0024 <[^>]*> 0001883a nop ++0+0028 <[^>]*> 0001883a nop ++0+002c <[^>]*> 0001883a nop ++0+0030 <[^>]*> 0001883a nop ++0+0034 <[^>]*> 0001883a nop ++0+0038 <[^>]*> 0001883a nop ++0+003c <[^>]*> 0001883a nop ++0+0040 <[^>]*> 0001883a nop ++0+0044 <[^>]*> 0001883a nop ++0+0048 <[^>]*> 0001883a nop ++0+004c <[^>]*> 0001883a nop ++0+0050 <[^>]*> 0001883a nop ++0+0054 <[^>]*> 0001883a nop ++0+0058 <[^>]*> 0001883a nop ++0+005c <[^>]*> 0001883a nop ++0+0060 <[^>]*> 0001883a nop ++0+0064 <[^>]*> 0001883a nop ++0+0068 <[^>]*> 0001883a nop ++0+006c <[^>]*> 0001883a nop ++0+0070 <[^>]*> 0001883a nop ++0+0074 <[^>]*> 0001883a nop ++0+0078 <[^>]*> 0001883a nop ++0+007c <[^>]*> 0001883a nop ++0+0080 <[^>]*> 0001883a nop ++0+0084 <[^>]*> 0001883a nop ++0+0088 <[^>]*> 0001883a nop ++0+008c <[^>]*> 0001883a nop ++0+0090 <[^>]*> 0001883a nop ++0+0094 <[^>]*> 0001883a nop ++0+0098 <[^>]*> 0001883a nop ++0+009c <[^>]*> 0001883a nop ++0+00a0 <[^>]*> 0001883a nop ++0+00a4 <[^>]*> 0001883a nop ++0+00a8 <[^>]*> 0001883a nop ++0+00ac <[^>]*> 0001883a nop ++0+00b0 <[^>]*> 0001883a nop ++0+00b4 <[^>]*> 0001883a nop ++0+00b8 <[^>]*> 0001883a nop ++0+00bc <[^>]*> 0001883a nop ++0+00c0 <[^>]*> 0001883a nop ++0+00c4 <[^>]*> 0001883a nop ++0+00c8 <[^>]*> 0001883a nop ++0+00cc <[^>]*> 0001883a nop ++0+00d0 <[^>]*> 0001883a nop ++0+00d4 <[^>]*> 0001883a nop ++0+00d8 <[^>]*> 0001883a nop ++0+00dc <[^>]*> 0001883a nop ++0+00e0 <[^>]*> 0001883a nop ++0+00e4 <[^>]*> 0001883a nop ++0+00e8 <[^>]*> 0001883a nop ++0+00ec <[^>]*> 0001883a nop ++0+00f0 <[^>]*> 0001883a nop ++0+00f4 <[^>]*> 0001883a nop ++0+00f8 <[^>]*> 0001883a nop ++0+00fc <[^>]*> 0001883a nop ++0+0100 <[^>]*> 0001883a nop ++ ... ++ ++ +diff --git a/gas/testsuite/gas/nios2/call26_noat.s b/gas/testsuite/gas/nios2/call26_noat.s +new file mode 100644 +index 0000000..f0a93e7 +--- /dev/null ++++ b/gas/testsuite/gas/nios2/call26_noat.s +@@ -0,0 +1,13 @@ ++# Test for Nios II 32-bit relocations ++ ++.global globalfunc ++.text ++.set norelax ++.set noat ++start: ++ call localfunc ++ call globalfunc ++ ++.align 8 ++localfunc: ++ nop +diff --git a/gas/testsuite/gas/nios2/call_noat.d b/gas/testsuite/gas/nios2/call_noat.d +new file mode 100644 +index 0000000..03aadb5 +--- /dev/null ++++ b/gas/testsuite/gas/nios2/call_noat.d +@@ -0,0 +1,11 @@ ++# objdump: -dr --prefix-addresses --show-raw-insn ++#name: NIOS2 call noat ++ ++.*: +file format elf32-littlenios2 ++ ++Disassembly of section .text: ++0+0000 <[^>]*> 00000000 call 00000000 <[^>]*> ++[ ]*0: R_NIOS2_CALL26_NOAT .text\+0xc ++0+0004 <[^>]*> 503ee83a callr r10 ++0+0008 <[^>]*> 00000000 call 00000000 <[^>]*> ++[ ]*8: R_NIOS2_CALL26_NOAT external +diff --git a/gas/testsuite/gas/nios2/call_noat.s b/gas/testsuite/gas/nios2/call_noat.s +new file mode 100644 +index 0000000..67613b7 +--- /dev/null ++++ b/gas/testsuite/gas/nios2/call_noat.s +@@ -0,0 +1,14 @@ ++# Source file used to test the call and callr instructions ++.text ++.set norelax ++.set noat ++foo: ++ call func1 ++ callr r10 ++# use external symbol ++ .global external ++ call external ++func1: ++ ++ ++ diff --git a/gas/testsuite/gas/nios2/cmp.d b/gas/testsuite/gas/nios2/cmp.d new file mode 100644 index 0000000..bb588eb @@ -1801646,12 +1810566,11 @@ index 0000000..3e47bc7 +.set defined_symbol, 0x4040 diff --git a/gas/testsuite/gas/nios2/nios2.exp b/gas/testsuite/gas/nios2/nios2.exp new file mode 100644 -index 0000000..d8180c3 +index 0000000..bd68c6c --- /dev/null +++ b/gas/testsuite/gas/nios2/nios2.exp -@@ -0,0 +1,28 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,27 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1801994,6 +1810913,170 @@ index 0000000..a960e19 + srai r4,r4,10 + srl r4,r4,r4 + srli r4,r4,5 +diff --git a/gas/testsuite/gas/nios2/selftest.d b/gas/testsuite/gas/nios2/selftest.d +new file mode 100644 +index 0000000..84b33a4 +--- /dev/null ++++ b/gas/testsuite/gas/nios2/selftest.d +@@ -0,0 +1,18 @@ ++#as: -r ++#objdump: -dr --prefix-addresses --show-raw-insn ++#name: NIOS2 selftest ++ ++# Test the assembler self-test mode on some instructions that ++# manipulate control registers. The purpose of this test is to make ++# sure the assembler doesn't choke, rather than to match the encodings ++# of the particular instructions in the test here. ++ ++.*: +file format elf32-littlenios2 ++ ++ ++Disassembly of section .text: ++0+0000 <[^>]*> 1001703a wrctl status,r2 ++0+0004 <[^>]*> 1001703a wrctl status,r2 ++0+0008 <[^>]*> 1001707a wrctl estatus,r2 ++0+000c <[^>]*> 1001707a wrctl estatus,r2 ++#... +diff --git a/gas/testsuite/gas/nios2/selftest.s b/gas/testsuite/gas/nios2/selftest.s +new file mode 100644 +index 0000000..bbfad1a +--- /dev/null ++++ b/gas/testsuite/gas/nios2/selftest.s +@@ -0,0 +1,134 @@ ++# Use self-test mode to verify that all the expected control register ++# names assemble correctly. ++ ++_start: ++ wrctl ctl0, r2, 0x1001703a ++ wrctl status, r2, 0x1001703a ++ ++ wrctl ctl1, r2, 0x1001707a ++ wrctl estatus, r2, 0x1001707a ++ ++ wrctl ctl2, r2, 0x100170ba ++ wrctl bstatus, r2, 0x100170ba ++ ++ wrctl ctl3, r2, 0x100170fa ++ wrctl ienable, r2, 0x100170fa ++ ++# wrctl ctl4, r2, 0x1001713a # write-only register ++# wrctl ipending, r2, 0x1001713a # ++ ++ wrctl ctl5, r2, 0x1001717a ++ wrctl cpuid, r2, 0x1001717a ++ ++ wrctl ctl6, r2, 0x100171ba ++ ++ wrctl ctl7, r2, 0x100171fa ++ wrctl exception,r2, 0x100171fa ++ ++ wrctl ctl8, r2, 0x1001723a ++ wrctl pteaddr, r2, 0x1001723a ++ ++ wrctl ctl9, r2, 0x1001727a ++ wrctl tlbacc, r2, 0x1001727a ++ ++ wrctl ctl10, r2, 0x100172ba ++ wrctl tlbmisc, r2, 0x100172ba ++ ++ wrctl ctl11, r2, 0x100172fa ++ wrctl eccinj, r2, 0x100172fa ++ ++ wrctl ctl12, r2, 0x1001733a ++ wrctl badaddr, r2, 0x1001733a ++ ++ wrctl ctl13, r2, 0x1001737a ++ wrctl config, r2, 0x1001737a ++ ++ wrctl ctl14, r2, 0x100173ba ++ wrctl mpubase, r2, 0x100173ba ++ ++ wrctl ctl15, r2, 0x100173fa ++ wrctl mpuacc, r2, 0x100173fa ++ ++ wrctl ctl16, r2, 0x1001743a ++ wrctl ctl17, r2, 0x1001747a ++ wrctl ctl18, r2, 0x100174ba ++ wrctl ctl19, r2, 0x100174fa ++ wrctl ctl20, r2, 0x1001753a ++ wrctl ctl21, r2, 0x1001757a ++ wrctl ctl22, r2, 0x100175ba ++ wrctl ctl23, r2, 0x100175fa ++ wrctl ctl24, r2, 0x1001763a ++ wrctl ctl25, r2, 0x1001767a ++ wrctl ctl26, r2, 0x100176ba ++ wrctl ctl27, r2, 0x100176fa ++ wrctl ctl28, r2, 0x1001773a ++ wrctl ctl29, r2, 0x1001777a ++ wrctl ctl30, r2, 0x100177ba ++ wrctl ctl31, r2, 0x100177fa ++ ++ ++ rdctl r2,ctl0, 0x0005303a ++ rdctl r2,status, 0x0005303a ++ ++ rdctl r2,ctl1, 0x0005307a ++ rdctl r2,estatus, 0x0005307a ++ ++ rdctl r2,ctl2, 0x000530ba ++ rdctl r2,bstatus, 0x000530ba ++ ++ rdctl r2,ctl3, 0x000530fa ++ rdctl r2,ienable, 0x000530fa ++ ++ rdctl r2,ctl4, 0x0005313a ++ rdctl r2,ipending, 0x0005313a ++ ++ rdctl r2,ctl5, 0x0005317a ++ rdctl r2,cpuid, 0x0005317a ++ ++ rdctl r2,ctl6, 0x000531ba ++ ++ rdctl r2,ctl7, 0x000531fa ++ rdctl r2,exception,0x000531fa ++ ++ rdctl r2,ctl8, 0x0005323a ++ rdctl r2,pteaddr, 0x0005323a ++ ++ rdctl r2,ctl9, 0x0005327a ++ rdctl r2,tlbacc, 0x0005327a ++ ++ rdctl r2,ctl10, 0x000532ba ++ rdctl r2,tlbmisc, 0x000532ba ++ ++ rdctl r2,ctl11, 0x000532fa ++ rdctl r2,eccinj, 0x000532fa ++ ++ rdctl r2,ctl12, 0x0005333a ++ rdctl r2,badaddr, 0x0005333a ++ ++ rdctl r2,ctl13, 0x0005337a ++ rdctl r2,config, 0x0005337a ++ ++ rdctl r2,ctl14, 0x000533ba ++ rdctl r2,mpubase, 0x000533ba ++ ++ rdctl r2,ctl15, 0x000533fa ++ rdctl r2,mpuacc, 0x000533fa ++ ++ rdctl r2,ctl16, 0x0005343a ++ rdctl r2,ctl17, 0x0005347a ++ rdctl r2,ctl18, 0x000534ba ++ rdctl r2,ctl19, 0x000534fa ++ rdctl r2,ctl20, 0x0005353a ++ rdctl r2,ctl21, 0x0005357a ++ rdctl r2,ctl22, 0x000535ba ++ rdctl r2,ctl23, 0x000535fa ++ rdctl r2,ctl24, 0x0005363a ++ rdctl r2,ctl25, 0x0005367a ++ rdctl r2,ctl26, 0x000536ba ++ rdctl r2,ctl27, 0x000536fa ++ rdctl r2,ctl28, 0x0005373a ++ rdctl r2,ctl29, 0x0005377a ++ rdctl r2,ctl30, 0x000537ba ++ rdctl r2,ctl31, 0x000537fa ++ ++ diff --git a/gas/testsuite/gas/nios2/stb.d b/gas/testsuite/gas/nios2/stb.d new file mode 100644 index 0000000..c8b4ba5 @@ -1803207,600 +1812290,1395 @@ index 0000000..2c558f7 + xorhi r6,r7,0xffff + xori r6,r7,0xffff + -diff --git a/gas/testsuite/gas/openrisc/addi.d b/gas/testsuite/gas/openrisc/addi.d +diff --git a/gas/testsuite/gas/or1k/allinsn.d b/gas/testsuite/gas/or1k/allinsn.d new file mode 100644 -index 0000000..50955d4 +index 0000000..27884fe --- /dev/null -+++ b/gas/testsuite/gas/openrisc/addi.d -@@ -0,0 +1,10 @@ -+#as: -+#objdump: -dr -+#name: addi -+ -+.*: +file format .* -+ -+Disassembly of section .text: -+ -+00000000 : -+ 0: 94 22 ff ff l.addi r1,r2,-1 -diff --git a/gas/testsuite/gas/openrisc/addi.s b/gas/testsuite/gas/openrisc/addi.s -new file mode 100644 -index 0000000..e460e64 ---- /dev/null -+++ b/gas/testsuite/gas/openrisc/addi.s -@@ -0,0 +1,4 @@ -+ .text -+ .global l_addi -+l_addi: -+ l.addi r1, r2, -1 -diff --git a/gas/testsuite/gas/openrisc/allinsn.d b/gas/testsuite/gas/openrisc/allinsn.d -new file mode 100644 -index 0000000..e679739 ---- /dev/null -+++ b/gas/testsuite/gas/openrisc/allinsn.d -@@ -0,0 +1,201 @@ ++++ b/gas/testsuite/gas/or1k/allinsn.d +@@ -0,0 +1,689 @@ +#as: +#objdump: -dr +#name: allinsn + +.*: +file format .* + -+Disassembly of section .text: + -+00000000 : -+ 0: 00 00 00 00 l.j 0 -+ 0: R_OPENRISC_INSN_ABS_26 .text ++Disassembly of section \.text: + -+00000004 : -+ 4: 04 00 00 00 l.jal 0 -+ 4: R_OPENRISC_INSN_ABS_26 .text ++00000000 : ++ 0: 15 00 00 00 l\.nop 0x0 + -+00000008 : -+ 8: 14 00 00 00 l.jr r0 ++00000004 : ++ 4: 15 00 00 00 l\.nop 0x0 + -+0000000c : -+ c: 14 20 00 00 l.jalr r0 ++00000008 : ++ 8: 03 ff ff ff l\.j 4 ++ c: 00 00 00 01 l\.j 10 ++ 10: 00 00 00 00 l\.j 10 ++ 14: 03 ff ff fb l\.j 0 ++ \.\.\. ++ 18: R_OR1K_INSN_REL_26 \.data ++ 1c: R_OR1K_INSN_REL_26 globaltext ++ 20: R_OR1K_INSN_REL_26 globaldata ++ 24: 03 ff ff f9 l\.j 8 ++ 28: 00 00 00 01 l\.j 2c + -+00000010 : -+ 10: 0b ff ff fc l.bal 0 ++0000002c : ++ 2c: 07 ff ff ff l\.jal 28 ++ 30: 04 00 00 01 l\.jal 34 ++ 34: 04 00 00 00 l\.jal 34 ++ 38: 07 ff ff f2 l\.jal 0 ++ 3c: 04 00 00 00 l\.jal 3c ++ 3c: R_OR1K_INSN_REL_26 \.data ++ 40: 04 00 00 00 l\.jal 40 ++ 40: R_OR1K_INSN_REL_26 globaltext ++ 44: 04 00 00 00 l\.jal 44 ++ 44: R_OR1K_INSN_REL_26 globaldata ++ 48: 07 ff ff f0 l\.jal 8 ++ 4c: 07 ff ff f8 l\.jal 2c + -+00000014 : -+ 14: 0f ff ff fb l.bnf 0 ++00000050 : ++ 50: 44 00 00 00 l\.jr r0 ++ 54: 44 00 f8 00 l\.jr r31 ++ 58: 44 00 80 00 l\.jr r16 ++ 5c: 44 00 78 00 l\.jr r15 ++ 60: 44 00 08 00 l\.jr r1 ++ 64: 44 00 d8 00 l\.jr r27 ++ 68: 44 00 70 00 l\.jr r14 ++ 6c: 44 00 b0 00 l\.jr r22 + -+00000018 : -+ 18: 13 ff ff fa l.bf 0 ++00000070 : ++ 70: 48 00 00 00 l\.jalr r0 ++ 74: 48 00 f8 00 l\.jalr r31 ++ 78: 48 00 80 00 l\.jalr r16 ++ 7c: 48 00 78 00 l\.jalr r15 ++ 80: 48 00 08 00 l\.jalr r1 ++ 84: 48 00 d8 00 l\.jalr r27 ++ 88: 48 00 70 00 l\.jalr r14 ++ 8c: 48 00 b0 00 l\.jalr r22 + -+0000001c : -+ 1c: 17 00 00 00 l.brk 0x0 ++00000090 : ++ 90: 0f ff ff ff l\.bnf 8c ++ 94: 0c 00 00 01 l\.bnf 98 ++ 98: 0c 00 00 00 l\.bnf 98 ++ 9c: 0f ff ff d9 l\.bnf 0 ++ a0: 0c 00 00 00 l\.bnf a0 ++ a0: R_OR1K_INSN_REL_26 \.data ++ a4: 0c 00 00 00 l\.bnf a4 ++ a4: R_OR1K_INSN_REL_26 globaltext ++ a8: 0c 00 00 00 l\.bnf a8 ++ a8: R_OR1K_INSN_REL_26 globaldata ++ ac: 0f ff ff d7 l\.bnf 8 ++ b0: 0f ff ff df l\.bnf 2c + -+00000020 : -+ 20: 14 40 00 00 l.rfe r0 ++000000b4 : ++ b4: 13 ff ff ff l\.bf b0 ++ b8: 10 00 00 01 l\.bf bc ++ bc: 10 00 00 00 l\.bf bc ++ c0: 13 ff ff d0 l\.bf 0 ++ c4: 10 00 00 00 l\.bf c4 ++ c4: R_OR1K_INSN_REL_26 \.data ++ c8: 10 00 00 00 l\.bf c8 ++ c8: R_OR1K_INSN_REL_26 globaltext ++ cc: 10 00 00 00 l\.bf cc ++ cc: R_OR1K_INSN_REL_26 globaldata ++ d0: 13 ff ff ce l\.bf 8 ++ d4: 13 ff ff d6 l\.bf 2c + -+00000024 : -+ 24: 16 00 00 00 l.sys 0x0 ++000000d8 : ++ d8: 21 00 00 00 l\.trap 0x0 ++ dc: 21 00 ff ff l\.trap 0xffff ++ e0: 21 00 80 00 l\.trap 0x8000 ++ e4: 21 00 7f ff l\.trap 0x7fff ++ e8: 21 00 00 01 l\.trap 0x1 ++ ec: 21 00 d1 4f l\.trap 0xd14f ++ f0: 21 00 7f 7c l\.trap 0x7f7c ++ f4: 21 00 d2 4a l\.trap 0xd24a + -+00000028 : -+ 28: 15 00 00 00 l.nop ++000000f8 : ++ f8: 20 00 00 00 l\.sys 0x0 ++ fc: 20 00 ff ff l\.sys 0xffff ++ 100: 20 00 80 00 l\.sys 0x8000 ++ 104: 20 00 7f ff l\.sys 0x7fff ++ 108: 20 00 00 01 l\.sys 0x1 ++ 10c: 20 00 d2 85 l\.sys 0xd285 ++ 110: 20 00 e3 15 l\.sys 0xe315 ++ 114: 20 00 80 fa l\.sys 0x80fa + -+0000002c : -+ 2c: 18 00 00 00 l.movhi r0,0 ++00000118 : ++ 118: 24 00 00 00 l\.rfe + -+00000030 : -+ 30: 1c 00 00 00 l.mfsr r0,r0 ++0000011c : ++ 11c: 15 00 00 00 l\.nop 0x0 + -+00000034 : -+ 34: 40 00 00 00 l.mtsr r0,r0 ++00000120 : ++ 120: 18 00 00 00 l\.movhi r0,0x0 ++ 124: 1b e0 ff ff l\.movhi r31,0xffff ++ 128: 1a 00 80 00 l\.movhi r16,0x8000 ++ 12c: 19 e0 7f ff l\.movhi r15,0x7fff ++ 130: 18 20 00 01 l\.movhi r1,0x1 ++ 134: 1b 80 81 ce l\.movhi r28,0x81ce ++ 138: 1a e0 e8 ac l\.movhi r23,0xe8ac ++ 13c: 1a 60 d8 c0 l\.movhi r19,0xd8c0 + -+00000038 : -+ 38: 80 00 00 00 l.lw r0,0\(r0\) ++00000140 : ++ 140: b4 00 00 00 l\.mfspr r0,r0,0x0 ++ 144: b7 ff ff ff l\.mfspr r31,r31,0xffff ++ 148: b6 10 80 00 l\.mfspr r16,r16,0x8000 ++ 14c: b5 ef 7f ff l\.mfspr r15,r15,0x7fff ++ 150: b4 21 00 01 l\.mfspr r1,r1,0x1 ++ 154: b6 fd d4 98 l\.mfspr r23,r29,0xd498 ++ 158: b6 74 11 81 l\.mfspr r19,r20,0x1181 ++ 15c: b7 42 f7 d6 l\.mfspr r26,r2,0xf7d6 + -+0000003c : -+ 3c: 84 00 00 00 l.lbz r0,0\(r0\) ++00000160 : ++ 160: c0 00 00 00 l\.mtspr r0,r0,0x0 ++ 164: c3 ff ff ff l\.mtspr r31,r31,0xffff ++ 168: c2 10 80 00 l\.mtspr r16,r16,0x8000 ++ 16c: c1 ef 7f ff l\.mtspr r15,r15,0x7fff ++ 170: c0 01 08 01 l\.mtspr r1,r1,0x1 ++ 174: c0 fe 33 77 l\.mtspr r30,r6,0x3b77 ++ 178: c2 a9 3c cc l\.mtspr r9,r7,0xaccc ++ 17c: c3 f9 3d 7b l\.mtspr r25,r7,0xfd7b + -+00000040 : -+ 40: 88 00 00 00 l.lbs r0,0\(r0\) ++00000180 : ++ 180: 84 00 00 00 l\.lwz r0,0\(r0\) ++ 184: 87 ff ff ff l\.lwz r31,-1\(r31\) ++ 188: 86 10 80 00 l\.lwz r16,-32768\(r16\) ++ 18c: 85 ef 7f ff l\.lwz r15,32767\(r15\) ++ 190: 84 21 00 01 l\.lwz r1,1\(r1\) ++ 194: 85 f9 0b 75 l\.lwz r15,2933\(r25\) ++ 198: 86 35 fc e1 l\.lwz r17,-799\(r21\) ++ 19c: 84 12 bb 45 l\.lwz r0,-17595\(r18\) + -+00000044 : -+ 44: 8c 00 00 00 l.lhz r0,0\(r0\) ++000001a0 : ++ 1a0: 88 00 00 00 l\.lws r0,0\(r0\) ++ 1a4: 8b ff ff ff l\.lws r31,-1\(r31\) ++ 1a8: 8a 10 80 00 l\.lws r16,-32768\(r16\) ++ 1ac: 89 ef 7f ff l\.lws r15,32767\(r15\) ++ 1b0: 88 21 00 01 l\.lws r1,1\(r1\) ++ 1b4: 88 35 bb 3a l\.lws r1,-17606\(r21\) ++ 1b8: 89 df 69 0b l\.lws r14,26891\(r31\) ++ 1bc: 89 00 6b a0 l\.lws r8,27552\(r0\) + -+00000048 : -+ 48: 90 00 00 00 l.lhs r0,0\(r0\) ++000001c0 : ++ 1c0: 8c 00 00 00 l\.lbz r0,0\(r0\) ++ 1c4: 8f ff ff ff l\.lbz r31,-1\(r31\) ++ 1c8: 8e 10 80 00 l\.lbz r16,-32768\(r16\) ++ 1cc: 8d ef 7f ff l\.lbz r15,32767\(r15\) ++ 1d0: 8c 21 00 01 l\.lbz r1,1\(r1\) ++ 1d4: 8e 74 64 23 l\.lbz r19,25635\(r20\) ++ 1d8: 8d e9 f2 a8 l\.lbz r15,-3416\(r9\) ++ 1dc: 8c 61 45 54 l\.lbz r3,17748\(r1\) + -+0000004c : -+ 4c: d4 00 00 00 l.sw 0\(r0\),r0 ++000001e0 : ++ 1e0: 90 00 00 00 l\.lbs r0,0\(r0\) ++ 1e4: 93 ff ff ff l\.lbs r31,-1\(r31\) ++ 1e8: 92 10 80 00 l\.lbs r16,-32768\(r16\) ++ 1ec: 91 ef 7f ff l\.lbs r15,32767\(r15\) ++ 1f0: 90 21 00 01 l\.lbs r1,1\(r1\) ++ 1f4: 93 48 44 c6 l\.lbs r26,17606\(r8\) ++ 1f8: 92 d0 86 a0 l\.lbs r22,-31072\(r16\) ++ 1fc: 90 c9 44 20 l\.lbs r6,17440\(r9\) + -+00000050 : -+ 50: d8 00 00 00 l.sb 0\(r0\),r0 ++00000200 : ++ 200: 94 00 00 00 l\.lhz r0,0\(r0\) ++ 204: 97 ff ff ff l\.lhz r31,-1\(r31\) ++ 208: 96 10 80 00 l\.lhz r16,-32768\(r16\) ++ 20c: 95 ef 7f ff l\.lhz r15,32767\(r15\) ++ 210: 94 21 00 01 l\.lhz r1,1\(r1\) ++ 214: 94 a4 e9 dd l\.lhz r5,-5667\(r4\) ++ 218: 97 04 16 d8 l\.lhz r24,5848\(r4\) ++ 21c: 95 47 7b bb l\.lhz r10,31675\(r7\) + -+00000054 : -+ 54: dc 00 00 00 l.sh 0\(r0\),r0 ++00000220 : ++ 220: 98 00 00 00 l\.lhs r0,0\(r0\) ++ 224: 9b ff ff ff l\.lhs r31,-1\(r31\) ++ 228: 9a 10 80 00 l\.lhs r16,-32768\(r16\) ++ 22c: 99 ef 7f ff l\.lhs r15,32767\(r15\) ++ 230: 98 21 00 01 l\.lhs r1,1\(r1\) ++ 234: 98 cb ff 72 l\.lhs r6,-142\(r11\) ++ 238: 9a 9d eb 46 l\.lhs r20,-5306\(r29\) ++ 23c: 99 f5 10 52 l\.lhs r15,4178\(r21\) + -+00000058 : -+ 58: e0 00 00 08 l.sll r0,r0,r0 ++00000240 : ++ 240: d4 00 00 00 l\.sw 0\(r0\),r0 ++ 244: d7 ff ff ff l\.sw -1\(r31\),r31 ++ 248: d6 10 80 00 l\.sw -32768\(r16\),r16 ++ 24c: d5 ef 7f ff l\.sw 32767\(r15\),r15 ++ 250: d4 01 08 01 l\.sw 1\(r1\),r1 ++ 254: d7 91 50 e1 l\.sw -7967\(r17\),r10 ++ 258: d4 1e 57 20 l\.sw 1824\(r30\),r10 ++ 25c: d5 ef 23 4e l\.sw 31566\(r15\),r4 + -+0000005c : -+ 5c: b4 00 00 00 l.slli r0,r0,0x0 ++00000260 : ++ 260: d8 00 00 00 l\.sb 0\(r0\),r0 ++ 264: db ff ff ff l\.sb -1\(r31\),r31 ++ 268: da 10 80 00 l\.sb -32768\(r16\),r16 ++ 26c: d9 ef 7f ff l\.sb 32767\(r15\),r15 ++ 270: d8 01 08 01 l\.sb 1\(r1\),r1 ++ 274: d9 4a 06 b8 l\.sb 22200\(r10\),r0 ++ 278: d8 90 df 0b l\.sb 9995\(r16\),r27 ++ 27c: da 4e f9 9c l\.sb -28260\(r14\),r31 + -+00000060 : -+ 60: e0 00 00 28 l.srl r0,r0,r0 ++00000280 : ++ 280: dc 00 00 00 l\.sh 0\(r0\),r0 ++ 284: df ff ff ff l\.sh -1\(r31\),r31 ++ 288: de 10 80 00 l\.sh -32768\(r16\),r16 ++ 28c: dd ef 7f ff l\.sh 32767\(r15\),r15 ++ 290: dc 01 08 01 l\.sh 1\(r1\),r1 ++ 294: dc b5 c9 bd l\.sh 10685\(r21\),r25 ++ 298: df 3c 2c f6 l\.sh -13066\(r28\),r5 ++ 29c: de 49 ef 50 l\.sh -26800\(r9\),r29 + -+00000064 : -+ 64: b4 00 00 20 l.srli r0,r0,0x0 ++000002a0 : ++ 2a0: e0 00 00 08 l\.sll r0,r0,r0 ++ 2a4: e3 ff f8 08 l\.sll r31,r31,r31 ++ 2a8: e2 10 80 08 l\.sll r16,r16,r16 ++ 2ac: e1 ef 78 08 l\.sll r15,r15,r15 ++ 2b0: e0 21 08 08 l\.sll r1,r1,r1 ++ 2b4: e3 f0 40 08 l\.sll r31,r16,r8 ++ 2b8: e3 f1 b0 08 l\.sll r31,r17,r22 ++ 2bc: e1 ee 28 08 l\.sll r15,r14,r5 + -+00000068 : -+ 68: e0 00 00 48 l.sra r0,r0,r0 ++000002c0 : ++ 2c0: b8 00 00 00 l\.slli r0,r0,0x0 ++ 2c4: bb ff 00 3f l\.slli r31,r31,0x3f ++ 2c8: ba 10 00 20 l\.slli r16,r16,0x20 ++ 2cc: b9 ef 00 1f l\.slli r15,r15,0x1f ++ 2d0: b8 21 00 01 l\.slli r1,r1,0x1 ++ 2d4: b9 6e 00 31 l\.slli r11,r14,0x31 ++ 2d8: b8 fb 00 17 l\.slli r7,r27,0x17 ++ 2dc: bb d0 00 0b l\.slli r30,r16,0xb + -+0000006c : -+ 6c: b4 00 00 40 l.srai r0,r0,0x0 ++000002e0 : ++ 2e0: e0 00 00 48 l\.srl r0,r0,r0 ++ 2e4: e3 ff f8 48 l\.srl r31,r31,r31 ++ 2e8: e2 10 80 48 l\.srl r16,r16,r16 ++ 2ec: e1 ef 78 48 l\.srl r15,r15,r15 ++ 2f0: e0 21 08 48 l\.srl r1,r1,r1 ++ 2f4: e1 f9 68 48 l\.srl r15,r25,r13 ++ 2f8: e2 60 88 48 l\.srl r19,r0,r17 ++ 2fc: e1 a0 b8 48 l\.srl r13,r0,r23 + -+00000070 : -+ 70: e0 00 00 88 l.ror r0,r0,r0 ++00000300 : ++ 300: b8 00 00 40 l\.srli r0,r0,0x0 ++ 304: bb ff 00 7f l\.srli r31,r31,0x3f ++ 308: ba 10 00 60 l\.srli r16,r16,0x20 ++ 30c: b9 ef 00 5f l\.srli r15,r15,0x1f ++ 310: b8 21 00 41 l\.srli r1,r1,0x1 ++ 314: b9 fe 00 4d l\.srli r15,r30,0xd ++ 318: b9 a3 00 7f l\.srli r13,r3,0x3f ++ 31c: b8 52 00 5e l\.srli r2,r18,0x1e + -+00000074 : -+ 74: b4 00 00 80 l.rori r0,r0,0x0 ++00000320 : ++ 320: e0 00 00 88 l\.sra r0,r0,r0 ++ 324: e3 ff f8 88 l\.sra r31,r31,r31 ++ 328: e2 10 80 88 l\.sra r16,r16,r16 ++ 32c: e1 ef 78 88 l\.sra r15,r15,r15 ++ 330: e0 21 08 88 l\.sra r1,r1,r1 ++ 334: e0 7a 00 88 l\.sra r3,r26,r0 ++ 338: e3 b2 d8 88 l\.sra r29,r18,r27 ++ 33c: e3 7d 18 88 l\.sra r27,r29,r3 + -+00000078 : -+ 78: e0 00 00 00 l.add r0,r0,r0 ++00000340 : ++ 340: b8 00 00 80 l\.srai r0,r0,0x0 ++ 344: bb ff 00 bf l\.srai r31,r31,0x3f ++ 348: ba 10 00 a0 l\.srai r16,r16,0x20 ++ 34c: b9 ef 00 9f l\.srai r15,r15,0x1f ++ 350: b8 21 00 81 l\.srai r1,r1,0x1 ++ 354: b9 4b 00 9c l\.srai r10,r11,0x1c ++ 358: ba ef 00 b0 l\.srai r23,r15,0x30 ++ 35c: ba 0f 00 a6 l\.srai r16,r15,0x26 + -+0000007c : -+ 7c: 94 00 00 00 l.addi r0,r0,0 ++00000360 : ++ 360: e0 00 00 c8 l\.ror r0,r0,r0 ++ 364: e3 ff f8 c8 l\.ror r31,r31,r31 ++ 368: e2 10 80 c8 l\.ror r16,r16,r16 ++ 36c: e1 ef 78 c8 l\.ror r15,r15,r15 ++ 370: e0 21 08 c8 l\.ror r1,r1,r1 ++ 374: e3 ac 28 c8 l\.ror r29,r12,r5 ++ 378: e2 46 20 c8 l\.ror r18,r6,r4 ++ 37c: e0 50 88 c8 l\.ror r2,r16,r17 + -+00000080 : -+ 80: e0 00 00 02 l.sub r0,r0,r0 ++00000380 : ++ 380: b8 00 00 c0 l\.rori r0,r0,0x0 ++ 384: bb ff 00 ff l\.rori r31,r31,0x3f ++ 388: ba 10 00 e0 l\.rori r16,r16,0x20 ++ 38c: b9 ef 00 df l\.rori r15,r15,0x1f ++ 390: b8 21 00 c1 l\.rori r1,r1,0x1 ++ 394: ba 20 00 d7 l\.rori r17,r0,0x17 ++ 398: ba 1f 00 ea l\.rori r16,r31,0x2a ++ 39c: b9 b5 00 cc l\.rori r13,r21,0xc + -+00000084 : -+ 84: 9c 00 00 00 l.subi r0,r0,0 ++000003a0 : ++ 3a0: e0 00 00 00 l\.add r0,r0,r0 ++ 3a4: e3 ff f8 00 l\.add r31,r31,r31 ++ 3a8: e2 10 80 00 l\.add r16,r16,r16 ++ 3ac: e1 ef 78 00 l\.add r15,r15,r15 ++ 3b0: e0 21 08 00 l\.add r1,r1,r1 ++ 3b4: e3 a7 20 00 l\.add r29,r7,r4 ++ 3b8: e3 aa 90 00 l\.add r29,r10,r18 ++ 3bc: e2 56 b8 00 l\.add r18,r22,r23 + -+00000088 : -+ 88: e0 00 00 03 l.and r0,r0,r0 ++000003c0 : ++ 3c0: e0 00 00 02 l\.sub r0,r0,r0 ++ 3c4: e3 ff f8 02 l\.sub r31,r31,r31 ++ 3c8: e2 10 80 02 l\.sub r16,r16,r16 ++ 3cc: e1 ef 78 02 l\.sub r15,r15,r15 ++ 3d0: e0 21 08 02 l\.sub r1,r1,r1 ++ 3d4: e2 fa 70 02 l\.sub r23,r26,r14 ++ 3d8: e1 58 78 02 l\.sub r10,r24,r15 ++ 3dc: e1 64 90 02 l\.sub r11,r4,r18 + -+0000008c : -+ 8c: a0 00 00 00 l.andi r0,r0,0 ++000003e0 : ++ 3e0: e0 00 00 03 l\.and r0,r0,r0 ++ 3e4: e3 ff f8 03 l\.and r31,r31,r31 ++ 3e8: e2 10 80 03 l\.and r16,r16,r16 ++ 3ec: e1 ef 78 03 l\.and r15,r15,r15 ++ 3f0: e0 21 08 03 l\.and r1,r1,r1 ++ 3f4: e0 1f c8 03 l\.and r0,r31,r25 ++ 3f8: e3 c7 98 03 l\.and r30,r7,r19 ++ 3fc: e2 62 d0 03 l\.and r19,r2,r26 + -+00000090 : -+ 90: e0 00 00 04 l.or r0,r0,r0 ++00000400 : ++ 400: e0 00 00 04 l\.or r0,r0,r0 ++ 404: e3 ff f8 04 l\.or r31,r31,r31 ++ 408: e2 10 80 04 l\.or r16,r16,r16 ++ 40c: e1 ef 78 04 l\.or r15,r15,r15 ++ 410: e0 21 08 04 l\.or r1,r1,r1 ++ 414: e2 2a 10 04 l\.or r17,r10,r2 ++ 418: e0 f3 e8 04 l\.or r7,r19,r29 ++ 41c: e0 71 88 04 l\.or r3,r17,r17 + -+00000094 : -+ 94: a4 00 00 00 l.ori r0,r0,0 ++00000420 : ++ 420: e0 00 00 05 l\.xor r0,r0,r0 ++ 424: e3 ff f8 05 l\.xor r31,r31,r31 ++ 428: e2 10 80 05 l\.xor r16,r16,r16 ++ 42c: e1 ef 78 05 l\.xor r15,r15,r15 ++ 430: e0 21 08 05 l\.xor r1,r1,r1 ++ 434: e3 e5 88 05 l\.xor r31,r5,r17 ++ 438: e2 c4 28 05 l\.xor r22,r4,r5 ++ 43c: e3 d4 d0 05 l\.xor r30,r20,r26 + -+00000098 : -+ 98: e0 00 00 05 l.xor r0,r0,r0 ++00000440 : ++ 440: e0 00 00 01 l\.addc r0,r0,r0 ++ 444: e3 ff f8 01 l\.addc r31,r31,r31 ++ 448: e2 10 80 01 l\.addc r16,r16,r16 ++ 44c: e1 ef 78 01 l\.addc r15,r15,r15 ++ 450: e0 21 08 01 l\.addc r1,r1,r1 ++ 454: e1 1a c0 01 l\.addc r8,r26,r24 ++ 458: e2 46 20 01 l\.addc r18,r6,r4 ++ 45c: e3 a0 90 01 l\.addc r29,r0,r18 + -+0000009c : -+ 9c: a8 00 00 00 l.xori r0,r0,0 ++00000460 : ++ 460: e0 00 03 06 l\.mul r0,r0,r0 ++ 464: e3 ff fb 06 l\.mul r31,r31,r31 ++ 468: e2 10 83 06 l\.mul r16,r16,r16 ++ 46c: e1 ef 7b 06 l\.mul r15,r15,r15 ++ 470: e0 21 0b 06 l\.mul r1,r1,r1 ++ 474: e1 19 6b 06 l\.mul r8,r25,r13 ++ 478: e1 15 eb 06 l\.mul r8,r21,r29 ++ 47c: e3 63 8b 06 l\.mul r27,r3,r17 + -+000000a0 : -+ a0: e0 00 00 06 l.mul r0,r0,r0 ++00000480 : ++ 480: e0 00 03 0b l\.mulu r0,r0,r0 ++ 484: e3 ff fb 0b l\.mulu r31,r31,r31 ++ 488: e2 10 83 0b l\.mulu r16,r16,r16 ++ 48c: e1 ef 7b 0b l\.mulu r15,r15,r15 ++ 490: e0 21 0b 0b l\.mulu r1,r1,r1 ++ 494: e3 4e 83 0b l\.mulu r26,r14,r16 ++ 498: e0 32 5b 0b l\.mulu r1,r18,r11 ++ 49c: e1 d2 8b 0b l\.mulu r14,r18,r17 + -+000000a4 : -+ a4: ac 00 00 00 l.muli r0,r0,0 ++000004a0 : ++ 4a0: e0 00 03 09 l\.div r0,r0,r0 ++ 4a4: e3 ff fb 09 l\.div r31,r31,r31 ++ 4a8: e2 10 83 09 l\.div r16,r16,r16 ++ 4ac: e1 ef 7b 09 l\.div r15,r15,r15 ++ 4b0: e0 21 0b 09 l\.div r1,r1,r1 ++ 4b4: e0 02 e3 09 l\.div r0,r2,r28 ++ 4b8: e3 47 fb 09 l\.div r26,r7,r31 ++ 4bc: e0 52 a3 09 l\.div r2,r18,r20 + -+000000a8 : -+ a8: e0 00 00 09 l.div r0,r0,r0 ++000004c0 : ++ 4c0: e0 00 03 0a l\.divu r0,r0,r0 ++ 4c4: e3 ff fb 0a l\.divu r31,r31,r31 ++ 4c8: e2 10 83 0a l\.divu r16,r16,r16 ++ 4cc: e1 ef 7b 0a l\.divu r15,r15,r15 ++ 4d0: e0 21 0b 0a l\.divu r1,r1,r1 ++ 4d4: e0 a4 cb 0a l\.divu r5,r4,r25 ++ 4d8: e1 0b eb 0a l\.divu r8,r11,r29 ++ 4dc: e1 73 13 0a l\.divu r11,r19,r2 + -+000000ac : -+ ac: e0 00 00 0a l.divu r0,r0,r0 ++000004e0 : ++ 4e0: 9c 00 00 00 l\.addi r0,r0,0 ++ 4e4: 9f ff ff ff l\.addi r31,r31,-1 ++ 4e8: 9e 10 80 00 l\.addi r16,r16,-32768 ++ 4ec: 9d ef 7f ff l\.addi r15,r15,32767 ++ 4f0: 9c 21 00 01 l\.addi r1,r1,1 ++ 4f4: 9d c0 1b 6c l\.addi r14,r0,7020 ++ 4f8: 9d ae 37 33 l\.addi r13,r14,14131 ++ 4fc: 9d d0 97 3b l\.addi r14,r16,-26821 + -+000000b0 : -+ b0: e4 c0 00 00 l.sfgts r0,r0 ++00000500 : ++ 500: a4 00 00 00 l\.andi r0,r0,0x0 ++ 504: a7 ff ff ff l\.andi r31,r31,0xffff ++ 508: a6 10 80 00 l\.andi r16,r16,0x8000 ++ 50c: a5 ef 7f ff l\.andi r15,r15,0x7fff ++ 510: a4 21 00 01 l\.andi r1,r1,0x1 ++ 514: a7 75 2e 97 l\.andi r27,r21,0x2e97 ++ 518: a6 b7 2f 1b l\.andi r21,r23,0x2f1b ++ 51c: a7 de 83 c4 l\.andi r30,r30,0x83c4 + -+000000b4 : -+ b4: e4 40 00 00 l.sfgtu r0,r0 ++00000520 : ++ 520: a8 00 00 00 l\.ori r0,r0,0x0 ++ 524: ab ff ff ff l\.ori r31,r31,0xffff ++ 528: aa 10 80 00 l\.ori r16,r16,0x8000 ++ 52c: a9 ef 7f ff l\.ori r15,r15,0x7fff ++ 530: a8 21 00 01 l\.ori r1,r1,0x1 ++ 534: aa db d8 81 l\.ori r22,r27,0xd881 ++ 538: aa 3f 00 80 l\.ori r17,r31,0x80 ++ 53c: a9 b4 cf 6d l\.ori r13,r20,0xcf6d + -+000000b8 : -+ b8: e4 e0 00 00 l.sfges r0,r0 ++00000540 : ++ 540: ac 00 00 00 l\.xori r0,r0,0 ++ 544: af ff ff ff l\.xori r31,r31,-1 ++ 548: ae 10 80 00 l\.xori r16,r16,-32768 ++ 54c: ad ef 7f ff l\.xori r15,r15,32767 ++ 550: ac 21 00 01 l\.xori r1,r1,1 ++ 554: ae 50 ff ff l\.xori r18,r16,-1 ++ 558: af 2d c0 35 l\.xori r25,r13,-16331 ++ 55c: ad 9d 80 29 l\.xori r12,r29,-32727 + -+000000bc : -+ bc: e4 60 00 00 l.sfgeu r0,r0 ++00000560 : ++ 560: b0 00 00 00 l\.muli r0,r0,0 ++ 564: b3 ff ff ff l\.muli r31,r31,-1 ++ 568: b2 10 80 00 l\.muli r16,r16,-32768 ++ 56c: b1 ef 7f ff l\.muli r15,r15,32767 ++ 570: b0 21 00 01 l\.muli r1,r1,1 ++ 574: b3 67 ed 85 l\.muli r27,r7,-4731 ++ 578: b0 f4 ff ff l\.muli r7,r20,-1 ++ 57c: b3 15 5a b3 l\.muli r24,r21,23219 + -+000000c0 : -+ c0: e5 00 00 00 l.sflts r0,r0 ++00000580 : ++ 580: a0 00 00 00 l\.addic r0,r0,0 ++ 584: a3 ff ff ff l\.addic r31,r31,-1 ++ 588: a2 10 80 00 l\.addic r16,r16,-32768 ++ 58c: a1 ef 7f ff l\.addic r15,r15,32767 ++ 590: a0 21 00 01 l\.addic r1,r1,1 ++ 594: a0 d6 80 44 l\.addic r6,r22,-32700 ++ 598: a2 69 ff ff l\.addic r19,r9,-1 ++ 59c: a3 7c 1a eb l\.addic r27,r28,6891 + -+000000c4 : -+ c4: e4 80 00 00 l.sfltu r0,r0 ++000005a0 : ++ 5a0: e4 40 00 00 l\.sfgtu r0,r0 ++ 5a4: e4 5f f8 00 l\.sfgtu r31,r31 ++ 5a8: e4 50 80 00 l\.sfgtu r16,r16 ++ 5ac: e4 4f 78 00 l\.sfgtu r15,r15 ++ 5b0: e4 41 08 00 l\.sfgtu r1,r1 ++ 5b4: e4 48 20 00 l\.sfgtu r8,r4 ++ 5b8: e4 51 a8 00 l\.sfgtu r17,r21 ++ 5bc: e4 46 28 00 l\.sfgtu r6,r5 + -+000000c8 : -+ c8: e5 20 00 00 l.sfles r0,r0 ++000005c0 : ++ 5c0: e4 60 00 00 l\.sfgeu r0,r0 ++ 5c4: e4 7f f8 00 l\.sfgeu r31,r31 ++ 5c8: e4 70 80 00 l\.sfgeu r16,r16 ++ 5cc: e4 6f 78 00 l\.sfgeu r15,r15 ++ 5d0: e4 61 08 00 l\.sfgeu r1,r1 ++ 5d4: e4 6e 60 00 l\.sfgeu r14,r12 ++ 5d8: e4 76 38 00 l\.sfgeu r22,r7 ++ 5dc: e4 6d 08 00 l\.sfgeu r13,r1 + -+000000cc : -+ cc: e4 a0 00 00 l.sfleu r0,r0 ++000005e0 : ++ 5e0: e4 80 00 00 l\.sfltu r0,r0 ++ 5e4: e4 9f f8 00 l\.sfltu r31,r31 ++ 5e8: e4 90 80 00 l\.sfltu r16,r16 ++ 5ec: e4 8f 78 00 l\.sfltu r15,r15 ++ 5f0: e4 81 08 00 l\.sfltu r1,r1 ++ 5f4: e4 81 68 00 l\.sfltu r1,r13 ++ 5f8: e4 96 f0 00 l\.sfltu r22,r30 ++ 5fc: e4 94 30 00 l\.sfltu r20,r6 + -+000000d0 : -+ d0: b8 c0 00 00 l.sfgtsi r0,0 ++00000600 : ++ 600: e4 a0 00 00 l\.sfleu r0,r0 ++ 604: e4 bf f8 00 l\.sfleu r31,r31 ++ 608: e4 b0 80 00 l\.sfleu r16,r16 ++ 60c: e4 af 78 00 l\.sfleu r15,r15 ++ 610: e4 a1 08 00 l\.sfleu r1,r1 ++ 614: e4 b3 40 00 l\.sfleu r19,r8 ++ 618: e4 bb 78 00 l\.sfleu r27,r15 ++ 61c: e4 bb 18 00 l\.sfleu r27,r3 + -+000000d4 : -+ d4: b8 40 00 00 l.sfgtui r0,0x0 ++00000620 : ++ 620: e5 40 00 00 l\.sfgts r0,r0 ++ 624: e5 5f f8 00 l\.sfgts r31,r31 ++ 628: e5 50 80 00 l\.sfgts r16,r16 ++ 62c: e5 4f 78 00 l\.sfgts r15,r15 ++ 630: e5 41 08 00 l\.sfgts r1,r1 ++ 634: e5 45 28 00 l\.sfgts r5,r5 ++ 638: e5 5f 28 00 l\.sfgts r31,r5 ++ 63c: e5 5e 90 00 l\.sfgts r30,r18 + -+000000d8 : -+ d8: b8 e0 00 00 l.sfgesi r0,0 ++00000640 : ++ 640: e5 60 00 00 l\.sfges r0,r0 ++ 644: e5 7f f8 00 l\.sfges r31,r31 ++ 648: e5 70 80 00 l\.sfges r16,r16 ++ 64c: e5 6f 78 00 l\.sfges r15,r15 ++ 650: e5 61 08 00 l\.sfges r1,r1 ++ 654: e5 71 90 00 l\.sfges r17,r18 ++ 658: e5 60 48 00 l\.sfges r0,r9 ++ 65c: e5 76 c8 00 l\.sfges r22,r25 + -+000000dc : -+ dc: b8 60 00 00 l.sfgeui r0,0x0 ++00000660 : ++ 660: e5 80 00 00 l\.sflts r0,r0 ++ 664: e5 9f f8 00 l\.sflts r31,r31 ++ 668: e5 90 80 00 l\.sflts r16,r16 ++ 66c: e5 8f 78 00 l\.sflts r15,r15 ++ 670: e5 81 08 00 l\.sflts r1,r1 ++ 674: e5 99 c0 00 l\.sflts r25,r24 ++ 678: e5 97 68 00 l\.sflts r23,r13 ++ 67c: e5 8f 40 00 l\.sflts r15,r8 + -+000000e0 : -+ e0: b9 00 00 00 l.sfltsi r0,0 ++00000680 : ++ 680: e5 a0 00 00 l\.sfles r0,r0 ++ 684: e5 bf f8 00 l\.sfles r31,r31 ++ 688: e5 b0 80 00 l\.sfles r16,r16 ++ 68c: e5 af 78 00 l\.sfles r15,r15 ++ 690: e5 a1 08 00 l\.sfles r1,r1 ++ 694: e5 b1 68 00 l\.sfles r17,r13 ++ 698: e5 be c8 00 l\.sfles r30,r25 ++ 69c: e5 a0 60 00 l\.sfles r0,r12 + -+000000e4 : -+ e4: b8 80 00 00 l.sfltui r0,0x0 ++000006a0 : ++ 6a0: bc 40 00 00 l\.sfgtui r0,0 ++ 6a4: bc 5f ff ff l\.sfgtui r31,-1 ++ 6a8: bc 50 80 00 l\.sfgtui r16,-32768 ++ 6ac: bc 4f 7f ff l\.sfgtui r15,32767 ++ 6b0: bc 41 00 01 l\.sfgtui r1,1 ++ 6b4: bc 45 4b 21 l\.sfgtui r5,19233 ++ 6b8: bc 57 91 22 l\.sfgtui r23,-28382 ++ 6bc: bc 51 25 dd l\.sfgtui r17,9693 + -+000000e8 : -+ e8: b9 20 00 00 l.sflesi r0,0 ++000006c0 : ++ 6c0: bc 60 00 00 l\.sfgeui r0,0 ++ 6c4: bc 7f ff ff l\.sfgeui r31,-1 ++ 6c8: bc 70 80 00 l\.sfgeui r16,-32768 ++ 6cc: bc 6f 7f ff l\.sfgeui r15,32767 ++ 6d0: bc 61 00 01 l\.sfgeui r1,1 ++ 6d4: bc 71 ec b6 l\.sfgeui r17,-4938 ++ 6d8: bc 6f 40 13 l\.sfgeui r15,16403 ++ 6dc: bc 66 f1 a4 l\.sfgeui r6,-3676 + -+000000ec : -+ ec: b8 a0 00 00 l.sfleui r0,0x0 ++000006e0 : ++ 6e0: bc 80 00 00 l\.sfltui r0,0 ++ 6e4: bc 9f ff ff l\.sfltui r31,-1 ++ 6e8: bc 90 80 00 l\.sfltui r16,-32768 ++ 6ec: bc 8f 7f ff l\.sfltui r15,32767 ++ 6f0: bc 81 00 01 l\.sfltui r1,1 ++ 6f4: bc 83 cc af l\.sfltui r3,-13137 ++ 6f8: bc 98 4c fd l\.sfltui r24,19709 ++ 6fc: bc 8a 03 3e l\.sfltui r10,830 + -+000000f0 : -+ f0: e4 00 00 00 l.sfeq r0,r0 ++00000700 : ++ 700: bc a0 00 00 l\.sfleui r0,0 ++ 704: bc bf ff ff l\.sfleui r31,-1 ++ 708: bc b0 80 00 l\.sfleui r16,-32768 ++ 70c: bc af 7f ff l\.sfleui r15,32767 ++ 710: bc a1 00 01 l\.sfleui r1,1 ++ 714: bc b7 9b 66 l\.sfleui r23,-25754 ++ 718: bc b1 b6 d7 l\.sfleui r17,-18729 ++ 71c: bc a9 a8 81 l\.sfleui r9,-22399 + -+000000f4 : -+ f4: b8 00 00 00 l.sfeqi r0,0 ++00000720 : ++ 720: bd 40 00 00 l\.sfgtsi r0,0 ++ 724: bd 5f ff ff l\.sfgtsi r31,-1 ++ 728: bd 50 80 00 l\.sfgtsi r16,-32768 ++ 72c: bd 4f 7f ff l\.sfgtsi r15,32767 ++ 730: bd 41 00 01 l\.sfgtsi r1,1 ++ 734: bd 4d b6 82 l\.sfgtsi r13,-18814 ++ 738: bd 4d d6 5f l\.sfgtsi r13,-10657 ++ 73c: bd 5c 97 d5 l\.sfgtsi r28,-26667 + -+000000f8 : -+ f8: e4 20 00 00 l.sfne r0,r0 ++00000740 : ++ 740: bd 60 00 00 l\.sfgesi r0,0 ++ 744: bd 7f ff ff l\.sfgesi r31,-1 ++ 748: bd 70 80 00 l\.sfgesi r16,-32768 ++ 74c: bd 6f 7f ff l\.sfgesi r15,32767 ++ 750: bd 61 00 01 l\.sfgesi r1,1 ++ 754: bd 6c 09 48 l\.sfgesi r12,2376 ++ 758: bd 69 7d 3b l\.sfgesi r9,32059 ++ 75c: bd 6d 50 d8 l\.sfgesi r13,20696 + -+000000fc : -+ fc: b8 20 00 00 l.sfnei r0,0 -diff --git a/gas/testsuite/gas/openrisc/allinsn.exp b/gas/testsuite/gas/openrisc/allinsn.exp ++00000760 : ++ 760: bd 80 00 00 l\.sfltsi r0,0 ++ 764: bd 9f ff ff l\.sfltsi r31,-1 ++ 768: bd 90 80 00 l\.sfltsi r16,-32768 ++ 76c: bd 8f 7f ff l\.sfltsi r15,32767 ++ 770: bd 81 00 01 l\.sfltsi r1,1 ++ 774: bd 9e 0b cd l\.sfltsi r30,3021 ++ 778: bd 85 93 5b l\.sfltsi r5,-27813 ++ 77c: bd 9c dd 90 l\.sfltsi r28,-8816 ++ ++00000780 : ++ 780: bd a0 00 00 l\.sflesi r0,0 ++ 784: bd bf ff ff l\.sflesi r31,-1 ++ 788: bd b0 80 00 l\.sflesi r16,-32768 ++ 78c: bd af 7f ff l\.sflesi r15,32767 ++ 790: bd a1 00 01 l\.sflesi r1,1 ++ 794: bd b2 2c 4a l\.sflesi r18,11338 ++ 798: bd bd 49 b9 l\.sflesi r29,18873 ++ 79c: bd bc 65 c2 l\.sflesi r28,26050 ++ ++000007a0 : ++ 7a0: e4 00 00 00 l\.sfeq r0,r0 ++ 7a4: e4 1f f8 00 l\.sfeq r31,r31 ++ 7a8: e4 10 80 00 l\.sfeq r16,r16 ++ 7ac: e4 0f 78 00 l\.sfeq r15,r15 ++ 7b0: e4 01 08 00 l\.sfeq r1,r1 ++ 7b4: e4 1c d0 00 l\.sfeq r28,r26 ++ 7b8: e4 0d 30 00 l\.sfeq r13,r6 ++ 7bc: e4 1a 48 00 l\.sfeq r26,r9 ++ ++000007c0 : ++ 7c0: bc 00 00 00 l\.sfeqi r0,0 ++ 7c4: bc 1f ff ff l\.sfeqi r31,-1 ++ 7c8: bc 10 80 00 l\.sfeqi r16,-32768 ++ 7cc: bc 0f 7f ff l\.sfeqi r15,32767 ++ 7d0: bc 01 00 01 l\.sfeqi r1,1 ++ 7d4: bc 0a 65 1f l\.sfeqi r10,25887 ++ 7d8: bc 15 4d b6 l\.sfeqi r21,19894 ++ 7dc: bc 12 cb 95 l\.sfeqi r18,-13419 ++ ++000007e0 : ++ 7e0: e4 20 00 00 l\.sfne r0,r0 ++ 7e4: e4 3f f8 00 l\.sfne r31,r31 ++ 7e8: e4 30 80 00 l\.sfne r16,r16 ++ 7ec: e4 2f 78 00 l\.sfne r15,r15 ++ 7f0: e4 21 08 00 l\.sfne r1,r1 ++ 7f4: e4 32 d8 00 l\.sfne r18,r27 ++ 7f8: e4 26 90 00 l\.sfne r6,r18 ++ 7fc: e4 20 f0 00 l\.sfne r0,r30 ++ ++00000800 : ++ 800: bc 20 00 00 l\.sfnei r0,0 ++ 804: bc 3f ff ff l\.sfnei r31,-1 ++ 808: bc 30 80 00 l\.sfnei r16,-32768 ++ 80c: bc 2f 7f ff l\.sfnei r15,32767 ++ 810: bc 21 00 01 l\.sfnei r1,1 ++ 814: bc 28 2c 92 l\.sfnei r8,11410 ++ 818: bc 26 b4 d9 l\.sfnei r6,-19239 ++ 81c: bc 34 a7 01 l\.sfnei r20,-22783 ++ ++00000820 : ++ 820: 9c 21 be ef l\.addi r1,r1,-16657 ++ ++00000824 : ++ 824: 18 20 de ad l\.movhi r1,0xdead ++ ++00000828 : ++ 828: c4 01 10 01 l.mac r1,r2 ++ ++0000082c : ++ 82c: 4c 01 00 00 l\.maci r1,0 ++ 830: 4c 02 ff ff l\.maci r2,-1 ++ 834: 4c 02 7f ff l\.maci r2,32767 ++ 838: 4c 02 80 00 l\.maci r2,-32768 +diff --git a/gas/testsuite/gas/or1k/allinsn.exp b/gas/testsuite/gas/or1k/allinsn.exp new file mode 100644 -index 0000000..1141c3e +index 0000000..11eacd7 --- /dev/null -+++ b/gas/testsuite/gas/openrisc/allinsn.exp -@@ -0,0 +1,25 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. ++++ b/gas/testsuite/gas/or1k/allinsn.exp +@@ -0,0 +1,5 @@ ++# OR1K assembler testsuite. -*- Tcl -*- + -+# This program is free software; you can redistribute it and/or modify -+# it under the terms of the GNU General Public License as published by -+# the Free Software Foundation; either version 3 of the License, or -+# (at your option) any later version. -+# -+# This program is distributed in the hope that it will be useful, -+# but WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+# GNU General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with this program; if not, write to the Free Software -+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. -+ -+# OpenRISC assembler testsuite. -+ -+if [istarget openrisc*-*-*] { -+ run_dump_test "allinsn" -+ run_dump_test "addi" -+ run_dump_test "lohi" -+ run_dump_test "store" ++if [istarget or1k*-*-*] { ++ run_dump_tests [lsort [glob -nocomplain $srcdir/$subdir/*.d]] +} -diff --git a/gas/testsuite/gas/openrisc/allinsn.s b/gas/testsuite/gas/openrisc/allinsn.s +diff --git a/gas/testsuite/gas/or1k/allinsn.s b/gas/testsuite/gas/or1k/allinsn.s new file mode 100644 -index 0000000..f2d8841 +index 0000000..05647f2 --- /dev/null -+++ b/gas/testsuite/gas/openrisc/allinsn.s -@@ -0,0 +1,260 @@ -+ .data -+foodata: .word 42 -+ .text -+footext: ++++ b/gas/testsuite/gas/or1k/allinsn.s +@@ -0,0 +1,677 @@ ++ .data ++localdata: ++ .word 42 + .text -+ .global l_j ++localtext: ++ l.nop ++ .data ++ .global globaldata ++globaldata: ++ .word 43 ++ .text ++ .global globaltext ++globaltext: ++ l.nop ++ +l_j: -+ l.j footext ++ l.j -4 ++ l.j 4 ++ l.j 0 ++ l.j localtext ++ l.j localdata ++ l.j globaltext ++ l.j globaldata ++ l.j l_j ++ l.j l_jal + .text -+ .global l_jal +l_jal: -+ l.jal footext ++ l.jal -4 ++ l.jal 4 ++ l.jal 0 ++ l.jal localtext ++ l.jal localdata ++ l.jal globaltext ++ l.jal globaldata ++ l.jal l_j ++ l.jal l_jal + .text -+ .global l_jr +l_jr: + l.jr r0 ++ l.jr r31 ++ l.jr r16 ++ l.jr r15 ++ l.jr r1 ++ l.jr r27 ++ l.jr r14 ++ l.jr r22 + .text -+ .global l_jalr +l_jalr: + l.jalr r0 ++ l.jalr r31 ++ l.jalr r16 ++ l.jalr r15 ++ l.jalr r1 ++ l.jalr r27 ++ l.jalr r14 ++ l.jalr r22 + .text -+ .global l_bal -+l_bal: -+ l.bal footext -+ .text -+ .global l_bnf +l_bnf: -+ l.bnf footext ++ l.bnf -4 ++ l.bnf 4 ++ l.bnf 0 ++ l.bnf localtext ++ l.bnf localdata ++ l.bnf globaltext ++ l.bnf globaldata ++ l.bnf l_j ++ l.bnf l_jal + .text -+ .global l_bf +l_bf: -+ l.bf footext ++ l.bf -4 ++ l.bf 4 ++ l.bf 0 ++ l.bf localtext ++ l.bf localdata ++ l.bf globaltext ++ l.bf globaldata ++ l.bf l_j ++ l.bf l_jal + .text -+ .global l_brk -+l_brk: -+ l.brk 0 ++l_trap: ++ l.trap 0 ++ l.trap 65535 ++ l.trap 32768 ++ l.trap 32767 ++ l.trap 1 ++ l.trap 53583 ++ l.trap 32636 ++ l.trap 53834 + .text -+ .global l_rfe -+l_rfe: -+ l.rfe r0 -+ .text -+ .global l_sys +l_sys: + l.sys 0 ++ l.sys 65535 ++ l.sys 32768 ++ l.sys 32767 ++ l.sys 1 ++ l.sys 53893 ++ l.sys 58133 ++ l.sys 33018 ++ .text ++l_rfe: ++ l.rfe + .text -+ .global l_nop +l_nop: + l.nop + .text -+ .global l_movhi +l_movhi: + l.movhi r0,0 ++ l.movhi r31,-1 ++ l.movhi r16,-32768 ++ l.movhi r15,32767 ++ l.movhi r1,1 ++ l.movhi r28,-32306 ++ l.movhi r23,-5972 ++ l.movhi r19,-10048 + .text -+ .global l_mfsr -+l_mfsr: -+ l.mfsr r0,r0 ++l_mfspr: ++ l.mfspr r0,r0,0 ++ l.mfspr r31,r31,65535 ++ l.mfspr r16,r16,32768 ++ l.mfspr r15,r15,32767 ++ l.mfspr r1,r1,1 ++ l.mfspr r23,r29,54424 ++ l.mfspr r19,r20,4481 ++ l.mfspr r26,r2,63446 + .text -+ .global l_mtsr -+l_mtsr: -+ l.mtsr r0,r0 ++l_mtspr: ++ l.mtspr r0,r0,0 ++ l.mtspr r31,r31,-1 ++ l.mtspr r16,r16,-32768 ++ l.mtspr r15,r15,32767 ++ l.mtspr r1,r1,1 ++ l.mtspr r30,r6,15223 ++ l.mtspr r9,r7,-21300 ++ l.mtspr r25,r7,-645 + .text -+ .global l_lw -+l_lw: -+ l.lw r0,0(r0) ++l_lwz: ++ l.lwz r0,0(r0) ++ l.lwz r31,-1(r31) ++ l.lwz r16,-32768(r16) ++ l.lwz r15,32767(r15) ++ l.lwz r1,1(r1) ++ l.lwz r15,2933(r25) ++ l.lwz r17,-799(r21) ++ l.lwz r0,-17595(r18) ++ .text ++l_lws: ++ l.lws r0,0(r0) ++ l.lws r31,-1(r31) ++ l.lws r16,-32768(r16) ++ l.lws r15,32767(r15) ++ l.lws r1,1(r1) ++ l.lws r1,-17606(r21) ++ l.lws r14,26891(r31) ++ l.lws r8,27552(r0) + .text -+ .global l_lbz +l_lbz: + l.lbz r0,0(r0) ++ l.lbz r31,-1(r31) ++ l.lbz r16,-32768(r16) ++ l.lbz r15,32767(r15) ++ l.lbz r1,1(r1) ++ l.lbz r19,25635(r20) ++ l.lbz r15,-3416(r9) ++ l.lbz r3,17748(r1) + .text -+ .global l_lbs +l_lbs: + l.lbs r0,0(r0) ++ l.lbs r31,-1(r31) ++ l.lbs r16,-32768(r16) ++ l.lbs r15,32767(r15) ++ l.lbs r1,1(r1) ++ l.lbs r26,17606(r8) ++ l.lbs r22,-31072(r16) ++ l.lbs r6,17440(r9) + .text -+ .global l_lhz +l_lhz: + l.lhz r0,0(r0) ++ l.lhz r31,-1(r31) ++ l.lhz r16,-32768(r16) ++ l.lhz r15,32767(r15) ++ l.lhz r1,1(r1) ++ l.lhz r5,-5667(r4) ++ l.lhz r24,5848(r4) ++ l.lhz r10,31675(r7) + .text -+ .global l_lhs +l_lhs: + l.lhs r0,0(r0) ++ l.lhs r31,-1(r31) ++ l.lhs r16,-32768(r16) ++ l.lhs r15,32767(r15) ++ l.lhs r1,1(r1) ++ l.lhs r6,-142(r11) ++ l.lhs r20,-5306(r29) ++ l.lhs r15,4178(r21) + .text -+ .global l_sw +l_sw: + l.sw 0(r0),r0 ++ l.sw -1(r31),r31 ++ l.sw -32768(r16),r16 ++ l.sw 32767(r15),r15 ++ l.sw 1(r1),r1 ++ l.sw -7967(r17),r10 ++ l.sw 1824(r30),r10 ++ l.sw 31566(r15),r4 + .text -+ .global l_sb +l_sb: + l.sb 0(r0),r0 ++ l.sb -1(r31),r31 ++ l.sb -32768(r16),r16 ++ l.sb 32767(r15),r15 ++ l.sb 1(r1),r1 ++ l.sb 22200(r10),r0 ++ l.sb 9995(r16),r27 ++ l.sb -28260(r14),r31 + .text -+ .global l_sh +l_sh: + l.sh 0(r0),r0 ++ l.sh -1(r31),r31 ++ l.sh -32768(r16),r16 ++ l.sh 32767(r15),r15 ++ l.sh 1(r1),r1 ++ l.sh 10685(r21),r25 ++ l.sh -13066(r28),r5 ++ l.sh -26800(r9),r29 + .text -+ .global l_sll +l_sll: + l.sll r0,r0,r0 ++ l.sll r31,r31,r31 ++ l.sll r16,r16,r16 ++ l.sll r15,r15,r15 ++ l.sll r1,r1,r1 ++ l.sll r31,r16,r8 ++ l.sll r31,r17,r22 ++ l.sll r15,r14,r5 + .text -+ .global l_slli +l_slli: + l.slli r0,r0,0 ++ l.slli r31,r31,63 ++ l.slli r16,r16,32 ++ l.slli r15,r15,31 ++ l.slli r1,r1,1 ++ l.slli r11,r14,49 ++ l.slli r7,r27,23 ++ l.slli r30,r16,11 + .text -+ .global l_srl +l_srl: + l.srl r0,r0,r0 ++ l.srl r31,r31,r31 ++ l.srl r16,r16,r16 ++ l.srl r15,r15,r15 ++ l.srl r1,r1,r1 ++ l.srl r15,r25,r13 ++ l.srl r19,r0,r17 ++ l.srl r13,r0,r23 + .text -+ .global l_srli +l_srli: + l.srli r0,r0,0 ++ l.srli r31,r31,63 ++ l.srli r16,r16,32 ++ l.srli r15,r15,31 ++ l.srli r1,r1,1 ++ l.srli r15,r30,13 ++ l.srli r13,r3,63 ++ l.srli r2,r18,30 + .text -+ .global l_sra +l_sra: + l.sra r0,r0,r0 ++ l.sra r31,r31,r31 ++ l.sra r16,r16,r16 ++ l.sra r15,r15,r15 ++ l.sra r1,r1,r1 ++ l.sra r3,r26,r0 ++ l.sra r29,r18,r27 ++ l.sra r27,r29,r3 + .text -+ .global l_srai +l_srai: + l.srai r0,r0,0 ++ l.srai r31,r31,63 ++ l.srai r16,r16,32 ++ l.srai r15,r15,31 ++ l.srai r1,r1,1 ++ l.srai r10,r11,28 ++ l.srai r23,r15,48 ++ l.srai r16,r15,38 + .text -+ .global l_ror +l_ror: + l.ror r0,r0,r0 ++ l.ror r31,r31,r31 ++ l.ror r16,r16,r16 ++ l.ror r15,r15,r15 ++ l.ror r1,r1,r1 ++ l.ror r29,r12,r5 ++ l.ror r18,r6,r4 ++ l.ror r2,r16,r17 + .text -+ .global l_rori +l_rori: + l.rori r0,r0,0 ++ l.rori r31,r31,63 ++ l.rori r16,r16,32 ++ l.rori r15,r15,31 ++ l.rori r1,r1,1 ++ l.rori r17,r0,23 ++ l.rori r16,r31,42 ++ l.rori r13,r21,12 + .text -+ .global l_add +l_add: + l.add r0,r0,r0 ++ l.add r31,r31,r31 ++ l.add r16,r16,r16 ++ l.add r15,r15,r15 ++ l.add r1,r1,r1 ++ l.add r29,r7,r4 ++ l.add r29,r10,r18 ++ l.add r18,r22,r23 + .text -+ .global l_addi -+l_addi: -+ l.addi r0,r0,0 -+ .text -+ .global l_sub +l_sub: + l.sub r0,r0,r0 ++ l.sub r31,r31,r31 ++ l.sub r16,r16,r16 ++ l.sub r15,r15,r15 ++ l.sub r1,r1,r1 ++ l.sub r23,r26,r14 ++ l.sub r10,r24,r15 ++ l.sub r11,r4,r18 + .text -+ .global l_subi -+l_subi: -+ l.subi r0,r0,0 -+ .text -+ .global l_and +l_and: + l.and r0,r0,r0 ++ l.and r31,r31,r31 ++ l.and r16,r16,r16 ++ l.and r15,r15,r15 ++ l.and r1,r1,r1 ++ l.and r0,r31,r25 ++ l.and r30,r7,r19 ++ l.and r19,r2,r26 + .text -+ .global l_andi -+l_andi: -+ l.andi r0,r0,0 -+ .text -+ .global l_or +l_or: + l.or r0,r0,r0 ++ l.or r31,r31,r31 ++ l.or r16,r16,r16 ++ l.or r15,r15,r15 ++ l.or r1,r1,r1 ++ l.or r17,r10,r2 ++ l.or r7,r19,r29 ++ l.or r3,r17,r17 + .text -+ .global l_ori -+l_ori: -+ l.ori r0,r0,0 -+ .text -+ .global l_xor +l_xor: + l.xor r0,r0,r0 ++ l.xor r31,r31,r31 ++ l.xor r16,r16,r16 ++ l.xor r15,r15,r15 ++ l.xor r1,r1,r1 ++ l.xor r31,r5,r17 ++ l.xor r22,r4,r5 ++ l.xor r30,r20,r26 + .text -+ .global l_xori -+l_xori: -+ l.xori r0,r0,0 ++l_addc: ++ l.addc r0,r0,r0 ++ l.addc r31,r31,r31 ++ l.addc r16,r16,r16 ++ l.addc r15,r15,r15 ++ l.addc r1,r1,r1 ++ l.addc r8,r26,r24 ++ l.addc r18,r6,r4 ++ l.addc r29,r0,r18 + .text -+ .global l_mul +l_mul: + l.mul r0,r0,r0 ++ l.mul r31,r31,r31 ++ l.mul r16,r16,r16 ++ l.mul r15,r15,r15 ++ l.mul r1,r1,r1 ++ l.mul r8,r25,r13 ++ l.mul r8,r21,r29 ++ l.mul r27,r3,r17 + .text -+ .global l_muli -+l_muli: -+ l.muli r0,r0,0 ++l_mulu: ++ l.mulu r0,r0,r0 ++ l.mulu r31,r31,r31 ++ l.mulu r16,r16,r16 ++ l.mulu r15,r15,r15 ++ l.mulu r1,r1,r1 ++ l.mulu r26,r14,r16 ++ l.mulu r1,r18,r11 ++ l.mulu r14,r18,r17 + .text -+ .global l_div +l_div: + l.div r0,r0,r0 ++ l.div r31,r31,r31 ++ l.div r16,r16,r16 ++ l.div r15,r15,r15 ++ l.div r1,r1,r1 ++ l.div r0,r2,r28 ++ l.div r26,r7,r31 ++ l.div r2,r18,r20 + .text -+ .global l_divu +l_divu: + l.divu r0,r0,r0 ++ l.divu r31,r31,r31 ++ l.divu r16,r16,r16 ++ l.divu r15,r15,r15 ++ l.divu r1,r1,r1 ++ l.divu r5,r4,r25 ++ l.divu r8,r11,r29 ++ l.divu r11,r19,r2 + .text -+ .global l_sfgts -+l_sfgts: -+ l.sfgts r0,r0 ++l_addi: ++ l.addi r0,r0,0 ++ l.addi r31,r31,-1 ++ l.addi r16,r16,-32768 ++ l.addi r15,r15,32767 ++ l.addi r1,r1,1 ++ l.addi r14,r0,7020 ++ l.addi r13,r14,14131 ++ l.addi r14,r16,-26821 ++ .text ++l_andi: ++ l.andi r0,r0,0 ++ l.andi r31,r31,-1 ++ l.andi r16,r16,-32768 ++ l.andi r15,r15,32767 ++ l.andi r1,r1,1 ++ l.andi r27,r21,11927 ++ l.andi r21,r23,12059 ++ l.andi r30,r30,-31804 ++ .text ++l_ori: ++ l.ori r0,r0,0 ++ l.ori r31,r31,-1 ++ l.ori r16,r16,-32768 ++ l.ori r15,r15,32767 ++ l.ori r1,r1,1 ++ l.ori r22,r27,-10111 ++ l.ori r17,r31,128 ++ l.ori r13,r20,-12435 ++ .text ++l_xori: ++ l.xori r0,r0,0 ++ l.xori r31,r31,-1 ++ l.xori r16,r16,-32768 ++ l.xori r15,r15,32767 ++ l.xori r1,r1,1 ++ l.xori r18,r16,65535 ++ l.xori r25,r13,-16331 ++ l.xori r12,r29,-32727 ++ .text ++l_muli: ++ l.muli r0,r0,0 ++ l.muli r31,r31,-1 ++ l.muli r16,r16,-32768 ++ l.muli r15,r15,32767 ++ l.muli r1,r1,1 ++ l.muli r27,r7,-4731 ++ l.muli r7,r20,65535 ++ l.muli r24,r21,23219 ++ .text ++l_addic: ++ l.addic r0,r0,0 ++ l.addic r31,r31,-1 ++ l.addic r16,r16,-32768 ++ l.addic r15,r15,32767 ++ l.addic r1,r1,1 ++ l.addic r6,r22,-32700 ++ l.addic r19,r9,65535 ++ l.addic r27,r28,6891 + .text -+ .global l_sfgtu +l_sfgtu: + l.sfgtu r0,r0 ++ l.sfgtu r31,r31 ++ l.sfgtu r16,r16 ++ l.sfgtu r15,r15 ++ l.sfgtu r1,r1 ++ l.sfgtu r8,r4 ++ l.sfgtu r17,r21 ++ l.sfgtu r6,r5 + .text -+ .global l_sfges -+l_sfges: -+ l.sfges r0,r0 -+ .text -+ .global l_sfgeu +l_sfgeu: + l.sfgeu r0,r0 ++ l.sfgeu r31,r31 ++ l.sfgeu r16,r16 ++ l.sfgeu r15,r15 ++ l.sfgeu r1,r1 ++ l.sfgeu r14,r12 ++ l.sfgeu r22,r7 ++ l.sfgeu r13,r1 + .text -+ .global l_sflts -+l_sflts: -+ l.sflts r0,r0 -+ .text -+ .global l_sfltu +l_sfltu: + l.sfltu r0,r0 ++ l.sfltu r31,r31 ++ l.sfltu r16,r16 ++ l.sfltu r15,r15 ++ l.sfltu r1,r1 ++ l.sfltu r1,r13 ++ l.sfltu r22,r30 ++ l.sfltu r20,r6 + .text -+ .global l_sfles -+l_sfles: -+ l.sfles r0,r0 -+ .text -+ .global l_sfleu +l_sfleu: + l.sfleu r0,r0 ++ l.sfleu r31,r31 ++ l.sfleu r16,r16 ++ l.sfleu r15,r15 ++ l.sfleu r1,r1 ++ l.sfleu r19,r8 ++ l.sfleu r27,r15 ++ l.sfleu r27,r3 + .text -+ .global l_sfgtsi -+l_sfgtsi: -+ l.sfgtsi r0,0 ++l_sfgts: ++ l.sfgts r0,r0 ++ l.sfgts r31,r31 ++ l.sfgts r16,r16 ++ l.sfgts r15,r15 ++ l.sfgts r1,r1 ++ l.sfgts r5,r5 ++ l.sfgts r31,r5 ++ l.sfgts r30,r18 ++ .text ++l_sfges: ++ l.sfges r0,r0 ++ l.sfges r31,r31 ++ l.sfges r16,r16 ++ l.sfges r15,r15 ++ l.sfges r1,r1 ++ l.sfges r17,r18 ++ l.sfges r0,r9 ++ l.sfges r22,r25 ++ .text ++l_sflts: ++ l.sflts r0,r0 ++ l.sflts r31,r31 ++ l.sflts r16,r16 ++ l.sflts r15,r15 ++ l.sflts r1,r1 ++ l.sflts r25,r24 ++ l.sflts r23,r13 ++ l.sflts r15,r8 ++ .text ++l_sfles: ++ l.sfles r0,r0 ++ l.sfles r31,r31 ++ l.sfles r16,r16 ++ l.sfles r15,r15 ++ l.sfles r1,r1 ++ l.sfles r17,r13 ++ l.sfles r30,r25 ++ l.sfles r0,r12 + .text -+ .global l_sfgtui +l_sfgtui: + l.sfgtui r0,0 ++ l.sfgtui r31,65535 ++ l.sfgtui r16,32768 ++ l.sfgtui r15,32767 ++ l.sfgtui r1,1 ++ l.sfgtui r5,19233 ++ l.sfgtui r23,37154 ++ l.sfgtui r17,9693 + .text -+ .global l_sfgesi -+l_sfgesi: -+ l.sfgesi r0,0 -+ .text -+ .global l_sfgeui +l_sfgeui: + l.sfgeui r0,0 ++ l.sfgeui r31,65535 ++ l.sfgeui r16,32768 ++ l.sfgeui r15,32767 ++ l.sfgeui r1,1 ++ l.sfgeui r17,60598 ++ l.sfgeui r15,16403 ++ l.sfgeui r6,61860 + .text -+ .global l_sfltsi -+l_sfltsi: -+ l.sfltsi r0,0 -+ .text -+ .global l_sfltui +l_sfltui: + l.sfltui r0,0 ++ l.sfltui r31,65535 ++ l.sfltui r16,32768 ++ l.sfltui r15,32767 ++ l.sfltui r1,1 ++ l.sfltui r3,52399 ++ l.sfltui r24,19709 ++ l.sfltui r10,830 + .text -+ .global l_sflesi -+l_sflesi: -+ l.sflesi r0,0 -+ .text -+ .global l_sfleui +l_sfleui: + l.sfleui r0,0 ++ l.sfleui r31,65535 ++ l.sfleui r16,32768 ++ l.sfleui r15,32767 ++ l.sfleui r1,1 ++ l.sfleui r23,39782 ++ l.sfleui r17,46807 ++ l.sfleui r9,43137 ++ .text ++l_sfgtsi: ++ l.sfgtsi r0,0 ++ l.sfgtsi r31,-1 ++ l.sfgtsi r16,-32768 ++ l.sfgtsi r15,32767 ++ l.sfgtsi r1,1 ++ l.sfgtsi r13,-18814 ++ l.sfgtsi r13,-10657 ++ l.sfgtsi r28,-26667 ++ .text ++l_sfgesi: ++ l.sfgesi r0,0 ++ l.sfgesi r31,-1 ++ l.sfgesi r16,-32768 ++ l.sfgesi r15,32767 ++ l.sfgesi r1,1 ++ l.sfgesi r12,2376 ++ l.sfgesi r9,32059 ++ l.sfgesi r13,20696 ++ .text ++l_sfltsi: ++ l.sfltsi r0,0 ++ l.sfltsi r31,-1 ++ l.sfltsi r16,-32768 ++ l.sfltsi r15,32767 ++ l.sfltsi r1,1 ++ l.sfltsi r30,3021 ++ l.sfltsi r5,-27813 ++ l.sfltsi r28,-8816 ++ .text ++l_sflesi: ++ l.sflesi r0,0 ++ l.sflesi r31,-1 ++ l.sflesi r16,-32768 ++ l.sflesi r15,32767 ++ l.sflesi r1,1 ++ l.sflesi r18,11338 ++ l.sflesi r29,18873 ++ l.sflesi r28,26050 + .text -+ .global l_sfeq +l_sfeq: + l.sfeq r0,r0 ++ l.sfeq r31,r31 ++ l.sfeq r16,r16 ++ l.sfeq r15,r15 ++ l.sfeq r1,r1 ++ l.sfeq r28,r26 ++ l.sfeq r13,r6 ++ l.sfeq r26,r9 + .text -+ .global l_sfeqi +l_sfeqi: + l.sfeqi r0,0 ++ l.sfeqi r31,-1 ++ l.sfeqi r16,-32768 ++ l.sfeqi r15,32767 ++ l.sfeqi r1,1 ++ l.sfeqi r10,25887 ++ l.sfeqi r21,19894 ++ l.sfeqi r18,-13419 + .text -+ .global l_sfne +l_sfne: + l.sfne r0,r0 ++ l.sfne r31,r31 ++ l.sfne r16,r16 ++ l.sfne r15,r15 ++ l.sfne r1,r1 ++ l.sfne r18,r27 ++ l.sfne r6,r18 ++ l.sfne r0,r30 + .text -+ .global l_sfnei +l_sfnei: + l.sfnei r0,0 -diff --git a/gas/testsuite/gas/openrisc/lohi.d b/gas/testsuite/gas/openrisc/lohi.d -new file mode 100644 -index 0000000..51a5a15 ---- /dev/null -+++ b/gas/testsuite/gas/openrisc/lohi.d -@@ -0,0 +1,13 @@ -+#as: -+#objdump: -dr -+#name: lohi ++ l.sfnei r31,-1 ++ l.sfnei r16,-32768 ++ l.sfnei r15,32767 ++ l.sfnei r1,1 ++ l.sfnei r8,11410 ++ l.sfnei r6,-19239 ++ l.sfnei r20,-22783 + -+.*: +file format .* -+ -+Disassembly of section .text: -+ -+00000000 : -+ 0: 94 21 be ef l.addi r1,r1,-16657 -+ -+00000004 : -+ 4: 18 20 de ad l.movhi r1,-8531 -diff --git a/gas/testsuite/gas/openrisc/lohi.s b/gas/testsuite/gas/openrisc/lohi.s -new file mode 100644 -index 0000000..bbed820 ---- /dev/null -+++ b/gas/testsuite/gas/openrisc/lohi.s -@@ -0,0 +1,7 @@ -+ .text -+ .global l_lo +l_lo: + l.addi r1, r1, lo(0xdeadbeef) -+ .global l_hi +l_hi: + l.movhi r1, hi(0xdeadbeef) -diff --git a/gas/testsuite/gas/openrisc/store.d b/gas/testsuite/gas/openrisc/store.d -new file mode 100644 -index 0000000..15591eb ---- /dev/null -+++ b/gas/testsuite/gas/openrisc/store.d -@@ -0,0 +1,13 @@ -+#as: -+#objdump: -dr -+#name: store + -+.*: +file format .* -+ -+Disassembly of section .text: -+ -+00000000 : -+ 0: d7 e1 0f fc l.sw -4\(r1\),r1 -+ -+00000004 : -+ 4: 80 21 ff 9c l.lw r1,-100\(r1\) -diff --git a/gas/testsuite/gas/openrisc/store.s b/gas/testsuite/gas/openrisc/store.s -new file mode 100644 -index 0000000..ef96460 ---- /dev/null -+++ b/gas/testsuite/gas/openrisc/store.s -@@ -0,0 +1,7 @@ -+ .text -+ .global l_sw -+l_sw: -+ l.sw -4(r1), r1 -+ .global l_lw -+l_lw: -+ l.lw r1, -100(r1) ++l_mac: ++ l.mac r1,r2 ++l_maci: ++ l.maci r1,0 ++ l.maci r2,-1 ++ l.maci r2,32767 ++ l.maci r2,-32768 diff --git a/gas/testsuite/gas/pdp11/absreloc.d b/gas/testsuite/gas/pdp11/absreloc.d new file mode 100644 index 0000000..1a47310 @@ -1803824,12 +1813702,12 @@ index 0000000..1a47310 + 14: 0bdf 0014 tst \*\$24 diff --git a/gas/testsuite/gas/pdp11/absreloc.s b/gas/testsuite/gas/pdp11/absreloc.s new file mode 100644 -index 0000000..e4291f0 +index 0000000..aaf69a7 --- /dev/null +++ b/gas/testsuite/gas/pdp11/absreloc.s @@ -0,0 +1,26 @@ +# Test abs operands with relocatable modes for PDP11. -+# Copyright 2011 Free Software Foundation, Inc. ++# Copyright (C) 2011-2014 Free Software Foundation, Inc. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1804085,12 +1813963,12 @@ index 0000000..eeb80da + 1de: ff04 [ ]*ldcff fr4, fr0 diff --git a/gas/testsuite/gas/pdp11/opcode.s b/gas/testsuite/gas/pdp11/opcode.s new file mode 100644 -index 0000000..0a30c1d +index 0000000..9cb5792 --- /dev/null +++ b/gas/testsuite/gas/pdp11/opcode.s @@ -0,0 +1,230 @@ +# Opcode test for PDP-11. -+# Copyright 2002, 2005, 2007 Free Software Foundation, Inc. ++# Copyright (C) 2002-2014 Free Software Foundation, Inc. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1804321,12 +1814199,11 @@ index 0000000..0a30c1d + ldcdf ac4,ac0 diff --git a/gas/testsuite/gas/pdp11/pdp11.exp b/gas/testsuite/gas/pdp11/pdp11.exp new file mode 100644 -index 0000000..8c7d4af +index 0000000..30ffdc2 --- /dev/null +++ b/gas/testsuite/gas/pdp11/pdp11.exp -@@ -0,0 +1,27 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,26 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1804482,16 +1814359,54 @@ index 0000000..bf2b397 + .comm _i, 16, 4 + .comm _j, 16, 2 + .comm _k, 16, 1 +diff --git a/gas/testsuite/gas/pe/big-obj.d b/gas/testsuite/gas/pe/big-obj.d +new file mode 100644 +index 0000000..95ff1d8 +--- /dev/null ++++ b/gas/testsuite/gas/pe/big-obj.d +@@ -0,0 +1,11 @@ ++#as: -mbig-obj ++#objdump: -h ++#name: PE x64 big obj ++ ++.*: *file format pe-bigobj-.* ++ ++Sections: ++#... ++5000. \.data\$a49999 .* ++ CONTENTS, ALLOC, LOAD, DATA ++ +diff --git a/gas/testsuite/gas/pe/big-obj.s b/gas/testsuite/gas/pe/big-obj.s +new file mode 100644 +index 0000000..07edc91 +--- /dev/null ++++ b/gas/testsuite/gas/pe/big-obj.s +@@ -0,0 +1,16 @@ ++ .file "big-obj.s" ++ ++ .irp n,0,1,2,3,4 ++ .irp m,0,1,2,3,4,5,6,7,8,9 ++ .irp c,0,1,2,3,4,5,6,7,8,9 ++ .irp d,0,1,2,3,4,5,6,7,8,9 ++ .irp u,0,1,2,3,4,5,6,7,8,9 ++ .globl a\n\m\c\d\u ++ .section .data$a\n\m\c\d\u,"w" ++a\n\m\c\d\u : ++ .byte 1 ++ .endr ++ .endr ++ .endr ++ .endr ++ .endr diff --git a/gas/testsuite/gas/pe/pe.exp b/gas/testsuite/gas/pe/pe.exp new file mode 100644 -index 0000000..870df11 +index 0000000..c1c5f49 --- /dev/null +++ b/gas/testsuite/gas/pe/pe.exp -@@ -0,0 +1,51 @@ +@@ -0,0 +1,58 @@ +# Expect control script for GAS testsuite PE object-format-specific tests. + -+# Copyright (C) 2009 -+# Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1804539,6 +1814454,14 @@ index 0000000..870df11 + run_dump_test "peseh-x64-5" + run_dump_test "peseh-x64-6" +} ++ ++# Big obj ++ ++ ++if ([istarget "x86_64-*-mingw*"]) then { ++ # Currently only supported on x86_64 ++ run_dump_test "big-obj" ++} diff --git a/gas/testsuite/gas/pe/peseh-x64-2.d b/gas/testsuite/gas/pe/peseh-x64-2.d new file mode 100644 index 0000000..acfd727 @@ -1806341,12 +1816264,11 @@ index 0000000..7c8109b + tm_minfo diff --git a/gas/testsuite/gas/pj/pj.exp b/gas/testsuite/gas/pj/pj.exp new file mode 100644 -index 0000000..d834468 +index 0000000..8d16eaf --- /dev/null +++ b/gas/testsuite/gas/pj/pj.exp -@@ -0,0 +1,24 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,23 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1808525,11 +1818447,11 @@ index 0000000..bcab185 + xoris 10,11,0x1000 diff --git a/gas/testsuite/gas/ppc/aix.exp b/gas/testsuite/gas/ppc/aix.exp new file mode 100644 -index 0000000..9612f27 +index 0000000..2c363d7 --- /dev/null +++ b/gas/testsuite/gas/ppc/aix.exp @@ -0,0 +1,76 @@ -+# Copyright (C) 2001, 2002, 2005, 2007, 2009 Free Software Foundation, Inc. ++# Copyright (C) 2001-2014 Free Software Foundation, Inc. +# Contributed by Red Hat + +# This program is free software; you can redistribute it and/or modify @@ -1812159,12 +1822081,11 @@ index 0000000..8df4f6b + fmrgew 22,7,5 diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp new file mode 100644 -index 0000000..ba29261 +index 0000000..3ba01cd --- /dev/null +++ b/gas/testsuite/gas/ppc/ppc.exp -@@ -0,0 +1,93 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,92 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1818760,15 +1828681,14 @@ index 0000000..60921e6 + .text diff --git a/gas/testsuite/gas/rx/make-d b/gas/testsuite/gas/rx/make-d new file mode 100755 -index 0000000..0f48dd3 +index 0000000..343463c --- /dev/null +++ b/gas/testsuite/gas/rx/make-d -@@ -0,0 +1,48 @@ +@@ -0,0 +1,47 @@ +#!/usr/bin/perl +# -*- perl -*- + -+# Copyright 2012 -+# Free Software Foundation, Inc. ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1819020,7 +1828940,7 @@ index 0000000..e735a64 + min {memx},{reg} diff --git a/gas/testsuite/gas/rx/mov.d b/gas/testsuite/gas/rx/mov.d new file mode 100644 -index 0000000..c8b2d9e +index 0000000..7fc2a2d --- /dev/null +++ b/gas/testsuite/gas/rx/mov.d @@ -0,0 +1,476 @@ @@ -1819084,10 +1829004,10 @@ index 0000000..c8b2d9e + 62: 66 0f mov\.l #0, r15 + 64: 66 f0 mov\.l #15, r0 + 66: 66 ff mov\.l #15, r15 -+ 68: f9 04 04 80 mov\.b #-128, 4\[r0\] -+ 6c: f9 74 04 80 mov\.b #-128, 4\[r7\] -+ 70: f9 04 1c 80 mov\.b #-128, 28\[r0\] -+ 74: f9 74 1c 80 mov\.b #-128, 28\[r7\] ++ 68: f9 04 04 80 mov\.b #128, 4\[r0\] ++ 6c: f9 74 04 80 mov\.b #128, 4\[r7\] ++ 70: f9 04 1c 80 mov\.b #128, 28\[r0\] ++ 74: f9 74 1c 80 mov\.b #128, 28\[r7\] + 78: 3c 04 7f mov\.b #127, 4\[r0\] + 7b: 3c 74 7f mov\.b #127, 4\[r7\] + 7e: 3c 8c 7f mov\.b #127, 28\[r0\] @@ -1819147,11 +1829067,11 @@ index 0000000..c8b2d9e + 12e: fa 04 fc ff 00 mov\.b #0, 65532\[r0\] + 133: fa f4 fc ff 00 mov\.b #0, 65532\[r15\] + 138: 3c 00 ff mov\.b #255, \[r0\] -+ 13b: f8 f4 ff mov\.b #-1, \[r15\] -+ 13e: f9 04 fc ff mov\.b #-1, 252\[r0\] -+ 142: f9 f4 fc ff mov\.b #-1, 252\[r15\] -+ 146: fa 04 fc ff ff mov\.b #-1, 65532\[r0\] -+ 14b: fa f4 fc ff ff mov\.b #-1, 65532\[r15\] ++ 13b: f8 f4 ff mov\.b #255, \[r15\] ++ 13e: f9 04 fc ff mov\.b #255, 252\[r0\] ++ 142: f9 f4 fc ff mov\.b #255, 252\[r15\] ++ 146: fa 04 fc ff ff mov\.b #255, 65532\[r0\] ++ 14b: fa f4 fc ff ff mov\.b #255, 65532\[r15\] + 150: f8 05 80 mov\.w #-128, \[r0\] + 153: f8 f5 80 mov\.w #-128, \[r15\] + 156: f9 05 7e 80 mov\.w #-128, 252\[r0\] @@ -1819170,336 +1829090,336 @@ index 0000000..c8b2d9e + 18a: f9 f5 7e 00 mov\.w #0, 252\[r15\] + 18e: fa 05 fe 7f 00 mov\.w #0, 65532\[r0\] + 193: fa f5 fe 7f 00 mov\.w #0, 65532\[r15\] -+ 198: f8 09 ff ff mov\.w #-1, \[r0\] -+ 19c: f8 f9 ff ff mov\.w #-1, \[r15\] -+ 1a0: f9 09 7e ff ff mov\.w #-1, 252\[r0\] -+ 1a5: f9 f9 7e ff ff mov\.w #-1, 252\[r15\] -+ 1aa: fa 09 fe 7f ff ff mov\.w #-1, 65532\[r0\] -+ 1b0: fa f9 fe 7f ff ff mov\.w #-1, 65532\[r15\] -+ 1b6: f8 06 80 mov\.l #-128, \[r0\] -+ 1b9: f8 f6 80 mov\.l #-128, \[r15\] -+ 1bc: f9 06 3f 80 mov\.l #-128, 252\[r0\] -+ 1c0: f9 f6 3f 80 mov\.l #-128, 252\[r15\] -+ 1c4: fa 06 ff 3f 80 mov\.l #-128, 65532\[r0\] -+ 1c9: fa f6 ff 3f 80 mov\.l #-128, 65532\[r15\] -+ 1ce: 3e 00 7f mov\.l #127, \[r0\] -+ 1d1: f8 f6 7f mov\.l #127, \[r15\] -+ 1d4: f9 06 3f 7f mov\.l #127, 252\[r0\] -+ 1d8: f9 f6 3f 7f mov\.l #127, 252\[r15\] -+ 1dc: fa 06 ff 3f 7f mov\.l #127, 65532\[r0\] -+ 1e1: fa f6 ff 3f 7f mov\.l #127, 65532\[r15\] -+ 1e6: f8 0a 00 80 mov\.l #0xffff8000, \[r0\] -+ 1ea: f8 fa 00 80 mov\.l #0xffff8000, \[r15\] -+ 1ee: f9 0a 3f 00 80 mov\.l #0xffff8000, 252\[r0\] -+ 1f3: f9 fa 3f 00 80 mov\.l #0xffff8000, 252\[r15\] -+ 1f8: fa 0a ff 3f 00 80 mov\.l #0xffff8000, 65532\[r0\] -+ 1fe: fa fa ff 3f 00 80 mov\.l #0xffff8000, 65532\[r15\] -+ 204: f8 0e 00 80 00 mov\.l #0x8000, \[r0\] -+ 209: f8 fe 00 80 00 mov\.l #0x8000, \[r15\] -+ 20e: f9 0e 3f 00 80 00 mov\.l #0x8000, 252\[r0\] -+ 214: f9 fe 3f 00 80 00 mov\.l #0x8000, 252\[r15\] -+ 21a: fa 0e ff 3f 00 80 00 mov\.l #0x8000, 65532\[r0\] -+ 221: fa fe ff 3f 00 80 00 mov\.l #0x8000, 65532\[r15\] -+ 228: f8 0e 00 00 80 mov\.l #0xff800000, \[r0\] -+ 22d: f8 fe 00 00 80 mov\.l #0xff800000, \[r15\] -+ 232: f9 0e 3f 00 00 80 mov\.l #0xff800000, 252\[r0\] -+ 238: f9 fe 3f 00 00 80 mov\.l #0xff800000, 252\[r15\] -+ 23e: fa 0e ff 3f 00 00 80 mov\.l #0xff800000, 65532\[r0\] -+ 245: fa fe ff 3f 00 00 80 mov\.l #0xff800000, 65532\[r15\] -+ 24c: f8 0e ff ff 7f mov\.l #0x7fffff, \[r0\] -+ 251: f8 fe ff ff 7f mov\.l #0x7fffff, \[r15\] -+ 256: f9 0e 3f ff ff 7f mov\.l #0x7fffff, 252\[r0\] -+ 25c: f9 fe 3f ff ff 7f mov\.l #0x7fffff, 252\[r15\] -+ 262: fa 0e ff 3f ff ff 7f mov\.l #0x7fffff, 65532\[r0\] -+ 269: fa fe ff 3f ff ff 7f mov\.l #0x7fffff, 65532\[r15\] -+ 270: f8 02 00 00 00 80 mov\.l #0x80000000, \[r0\] -+ 276: f8 f2 00 00 00 80 mov\.l #0x80000000, \[r15\] -+ 27c: f9 02 3f 00 00 00 80 mov\.l #0x80000000, 252\[r0\] -+ 283: f9 f2 3f 00 00 00 80 mov\.l #0x80000000, 252\[r15\] -+ 28a: fa 02 ff 3f 00 00 00 80 mov\.l #0x80000000, 65532\[r0\] -+ 292: fa f2 ff 3f 00 00 00 80 mov\.l #0x80000000, 65532\[r15\] -+ 29a: f8 02 ff ff ff 7f mov\.l #0x7fffffff, \[r0\] -+ 2a0: f8 f2 ff ff ff 7f mov\.l #0x7fffffff, \[r15\] -+ 2a6: f9 02 3f ff ff ff 7f mov\.l #0x7fffffff, 252\[r0\] -+ 2ad: f9 f2 3f ff ff ff 7f mov\.l #0x7fffffff, 252\[r15\] -+ 2b4: fa 02 ff 3f ff ff ff 7f mov\.l #0x7fffffff, 65532\[r0\] -+ 2bc: fa f2 ff 3f ff ff ff 7f mov\.l #0x7fffffff, 65532\[r15\] -+ 2c4: cc 00 mov\.b \[r0\], r0 -+ 2c6: cc 0f mov\.b \[r0\], r15 -+ 2c8: cc f0 mov\.b \[r15\], r0 -+ 2ca: cc ff mov\.b \[r15\], r15 -+ 2cc: cd 00 fc mov\.b 252\[r0\], r0 -+ 2cf: cd 0f fc mov\.b 252\[r0\], r15 -+ 2d2: cd f0 fc mov\.b 252\[r15\], r0 -+ 2d5: cd ff fc mov\.b 252\[r15\], r15 -+ 2d8: ce 00 fc ff mov\.b 65532\[r0\], r0 -+ 2dc: ce 0f fc ff mov\.b 65532\[r0\], r15 -+ 2e0: ce f0 fc ff mov\.b 65532\[r15\], r0 -+ 2e4: ce ff fc ff mov\.b 65532\[r15\], r15 -+ 2e8: dc 00 mov\.w \[r0\], r0 -+ 2ea: dc 0f mov\.w \[r0\], r15 -+ 2ec: dc f0 mov\.w \[r15\], r0 -+ 2ee: dc ff mov\.w \[r15\], r15 -+ 2f0: dd 00 7e mov\.w 252\[r0\], r0 -+ 2f3: dd 0f 7e mov\.w 252\[r0\], r15 -+ 2f6: dd f0 7e mov\.w 252\[r15\], r0 -+ 2f9: dd ff 7e mov\.w 252\[r15\], r15 -+ 2fc: de 00 fe 7f mov\.w 65532\[r0\], r0 -+ 300: de 0f fe 7f mov\.w 65532\[r0\], r15 -+ 304: de f0 fe 7f mov\.w 65532\[r15\], r0 -+ 308: de ff fe 7f mov\.w 65532\[r15\], r15 -+ 30c: ec 00 mov\.l \[r0\], r0 -+ 30e: ec 0f mov\.l \[r0\], r15 -+ 310: ec f0 mov\.l \[r15\], r0 -+ 312: ec ff mov\.l \[r15\], r15 -+ 314: ed 00 3f mov\.l 252\[r0\], r0 -+ 317: ed 0f 3f mov\.l 252\[r0\], r15 -+ 31a: ed f0 3f mov\.l 252\[r15\], r0 -+ 31d: ed ff 3f mov\.l 252\[r15\], r15 -+ 320: ee 00 ff 3f mov\.l 65532\[r0\], r0 -+ 324: ee 0f ff 3f mov\.l 65532\[r0\], r15 -+ 328: ee f0 ff 3f mov\.l 65532\[r15\], r0 -+ 32c: ee ff ff 3f mov\.l 65532\[r15\], r15 -+ 330: fe 40 00 mov\.b \[r0, r0\], r0 -+ 333: fe 40 0f mov\.b \[r0, r0\], r15 -+ 336: fe 40 f0 mov\.b \[r0, r15\], r0 -+ 339: fe 40 ff mov\.b \[r0, r15\], r15 -+ 33c: fe 4f 00 mov\.b \[r15, r0\], r0 -+ 33f: fe 4f 0f mov\.b \[r15, r0\], r15 -+ 342: fe 4f f0 mov\.b \[r15, r15\], r0 -+ 345: fe 4f ff mov\.b \[r15, r15\], r15 -+ 348: fe 50 00 mov\.w \[r0, r0\], r0 -+ 34b: fe 50 0f mov\.w \[r0, r0\], r15 -+ 34e: fe 50 f0 mov\.w \[r0, r15\], r0 -+ 351: fe 50 ff mov\.w \[r0, r15\], r15 -+ 354: fe 5f 00 mov\.w \[r15, r0\], r0 -+ 357: fe 5f 0f mov\.w \[r15, r0\], r15 -+ 35a: fe 5f f0 mov\.w \[r15, r15\], r0 -+ 35d: fe 5f ff mov\.w \[r15, r15\], r15 -+ 360: fe 60 00 mov\.l \[r0, r0\], r0 -+ 363: fe 60 0f mov\.l \[r0, r0\], r15 -+ 366: fe 60 f0 mov\.l \[r0, r15\], r0 -+ 369: fe 60 ff mov\.l \[r0, r15\], r15 -+ 36c: fe 6f 00 mov\.l \[r15, r0\], r0 -+ 36f: fe 6f 0f mov\.l \[r15, r0\], r15 -+ 372: fe 6f f0 mov\.l \[r15, r15\], r0 -+ 375: fe 6f ff mov\.l \[r15, r15\], r15 -+ 378: c3 01 mov\.b r1, \[r0\] -+ 37a: c3 f1 mov\.b r1, \[r15\] -+ 37c: c7 01 fc mov\.b r1, 252\[r0\] -+ 37f: c7 f1 fc mov\.b r1, 252\[r15\] -+ 382: cb 01 fc ff mov\.b r1, 65532\[r0\] -+ 386: cb f1 fc ff mov\.b r1, 65532\[r15\] -+ 38a: c3 0f mov\.b r15, \[r0\] -+ 38c: c3 ff mov\.b r15, \[r15\] -+ 38e: c7 0f fc mov\.b r15, 252\[r0\] -+ 391: c7 ff fc mov\.b r15, 252\[r15\] -+ 394: cb 0f fc ff mov\.b r15, 65532\[r0\] -+ 398: cb ff fc ff mov\.b r15, 65532\[r15\] -+ 39c: d3 01 mov\.w r1, \[r0\] -+ 39e: d3 f1 mov\.w r1, \[r15\] -+ 3a0: d7 01 7e mov\.w r1, 252\[r0\] -+ 3a3: d7 f1 7e mov\.w r1, 252\[r15\] -+ 3a6: db 01 fe 7f mov\.w r1, 65532\[r0\] -+ 3aa: db f1 fe 7f mov\.w r1, 65532\[r15\] -+ 3ae: d3 0f mov\.w r15, \[r0\] -+ 3b0: d3 ff mov\.w r15, \[r15\] -+ 3b2: d7 0f 7e mov\.w r15, 252\[r0\] -+ 3b5: d7 ff 7e mov\.w r15, 252\[r15\] -+ 3b8: db 0f fe 7f mov\.w r15, 65532\[r0\] -+ 3bc: db ff fe 7f mov\.w r15, 65532\[r15\] -+ 3c0: e3 01 mov\.l r1, \[r0\] -+ 3c2: e3 f1 mov\.l r1, \[r15\] -+ 3c4: e7 01 3f mov\.l r1, 252\[r0\] -+ 3c7: e7 f1 3f mov\.l r1, 252\[r15\] -+ 3ca: eb 01 ff 3f mov\.l r1, 65532\[r0\] -+ 3ce: eb f1 ff 3f mov\.l r1, 65532\[r15\] -+ 3d2: e3 0f mov\.l r15, \[r0\] -+ 3d4: e3 ff mov\.l r15, \[r15\] -+ 3d6: e7 0f 3f mov\.l r15, 252\[r0\] -+ 3d9: e7 ff 3f mov\.l r15, 252\[r15\] -+ 3dc: eb 0f ff 3f mov\.l r15, 65532\[r0\] -+ 3e0: eb ff ff 3f mov\.l r15, 65532\[r15\] -+ 3e4: fe 00 00 mov\.b r0, \[r0, r0\] -+ 3e7: fe 00 f0 mov\.b r0, \[r0, r15\] -+ 3ea: fe 0f 00 mov\.b r0, \[r15, r0\] -+ 3ed: fe 0f f0 mov\.b r0, \[r15, r15\] -+ 3f0: fe 00 0f mov\.b r15, \[r0, r0\] -+ 3f3: fe 00 ff mov\.b r15, \[r0, r15\] -+ 3f6: fe 0f 0f mov\.b r15, \[r15, r0\] -+ 3f9: fe 0f ff mov\.b r15, \[r15, r15\] -+ 3fc: fe 10 00 mov\.w r0, \[r0, r0\] -+ 3ff: fe 10 f0 mov\.w r0, \[r0, r15\] -+ 402: fe 1f 00 mov\.w r0, \[r15, r0\] -+ 405: fe 1f f0 mov\.w r0, \[r15, r15\] -+ 408: fe 10 0f mov\.w r15, \[r0, r0\] -+ 40b: fe 10 ff mov\.w r15, \[r0, r15\] -+ 40e: fe 1f 0f mov\.w r15, \[r15, r0\] -+ 411: fe 1f ff mov\.w r15, \[r15, r15\] -+ 414: fe 20 00 mov\.l r0, \[r0, r0\] -+ 417: fe 20 f0 mov\.l r0, \[r0, r15\] -+ 41a: fe 2f 00 mov\.l r0, \[r15, r0\] -+ 41d: fe 2f f0 mov\.l r0, \[r15, r15\] -+ 420: fe 20 0f mov\.l r15, \[r0, r0\] -+ 423: fe 20 ff mov\.l r15, \[r0, r15\] -+ 426: fe 2f 0f mov\.l r15, \[r15, r0\] -+ 429: fe 2f ff mov\.l r15, \[r15, r15\] -+ 42c: c0 00 mov\.b \[r0\], \[r0\] -+ 42e: c0 0f mov\.b \[r0\], \[r15\] -+ 430: c4 00 fc mov\.b \[r0\], 252\[r0\] -+ 433: c4 0f fc mov\.b \[r0\], 252\[r15\] -+ 436: c8 00 fc ff mov\.b \[r0\], 65532\[r0\] -+ 43a: c8 0f fc ff mov\.b \[r0\], 65532\[r15\] -+ 43e: c0 f0 mov\.b \[r15\], \[r0\] -+ 440: c0 ff mov\.b \[r15\], \[r15\] -+ 442: c4 f0 fc mov\.b \[r15\], 252\[r0\] -+ 445: c4 ff fc mov\.b \[r15\], 252\[r15\] -+ 448: c8 f0 fc ff mov\.b \[r15\], 65532\[r0\] -+ 44c: c8 ff fc ff mov\.b \[r15\], 65532\[r15\] -+ 450: c1 00 fc mov\.b 252\[r0\], \[r0\] -+ 453: c1 0f fc mov\.b 252\[r0\], \[r15\] -+ 456: c5 00 fc fc mov\.b 252\[r0\], 252\[r0\] -+ 45a: c5 0f fc fc mov\.b 252\[r0\], 252\[r15\] -+ 45e: c9 00 fc fc ff mov\.b 252\[r0\], 65532\[r0\] -+ 463: c9 0f fc fc ff mov\.b 252\[r0\], 65532\[r15\] -+ 468: c1 f0 fc mov\.b 252\[r15\], \[r0\] -+ 46b: c1 ff fc mov\.b 252\[r15\], \[r15\] -+ 46e: c5 f0 fc fc mov\.b 252\[r15\], 252\[r0\] -+ 472: c5 ff fc fc mov\.b 252\[r15\], 252\[r15\] -+ 476: c9 f0 fc fc ff mov\.b 252\[r15\], 65532\[r0\] -+ 47b: c9 ff fc fc ff mov\.b 252\[r15\], 65532\[r15\] -+ 480: c2 00 fc ff mov\.b 65532\[r0\], \[r0\] -+ 484: c2 0f fc ff mov\.b 65532\[r0\], \[r15\] -+ 488: c6 00 fc ff fc mov\.b 65532\[r0\], 252\[r0\] -+ 48d: c6 0f fc ff fc mov\.b 65532\[r0\], 252\[r15\] -+ 492: ca 00 fc ff fc ff mov\.b 65532\[r0\], 65532\[r0\] -+ 498: ca 0f fc ff fc ff mov\.b 65532\[r0\], 65532\[r15\] -+ 49e: c2 f0 fc ff mov\.b 65532\[r15\], \[r0\] -+ 4a2: c2 ff fc ff mov\.b 65532\[r15\], \[r15\] -+ 4a6: c6 f0 fc ff fc mov\.b 65532\[r15\], 252\[r0\] -+ 4ab: c6 ff fc ff fc mov\.b 65532\[r15\], 252\[r15\] -+ 4b0: ca f0 fc ff fc ff mov\.b 65532\[r15\], 65532\[r0\] -+ 4b6: ca ff fc ff fc ff mov\.b 65532\[r15\], 65532\[r15\] -+ 4bc: d0 00 mov\.w \[r0\], \[r0\] -+ 4be: d0 0f mov\.w \[r0\], \[r15\] -+ 4c0: d4 00 7e mov\.w \[r0\], 252\[r0\] -+ 4c3: d4 0f 7e mov\.w \[r0\], 252\[r15\] -+ 4c6: d8 00 fe 7f mov\.w \[r0\], 65532\[r0\] -+ 4ca: d8 0f fe 7f mov\.w \[r0\], 65532\[r15\] -+ 4ce: d0 f0 mov\.w \[r15\], \[r0\] -+ 4d0: d0 ff mov\.w \[r15\], \[r15\] -+ 4d2: d4 f0 7e mov\.w \[r15\], 252\[r0\] -+ 4d5: d4 ff 7e mov\.w \[r15\], 252\[r15\] -+ 4d8: d8 f0 fe 7f mov\.w \[r15\], 65532\[r0\] -+ 4dc: d8 ff fe 7f mov\.w \[r15\], 65532\[r15\] -+ 4e0: d1 00 7e mov\.w 252\[r0\], \[r0\] -+ 4e3: d1 0f 7e mov\.w 252\[r0\], \[r15\] -+ 4e6: d5 00 7e 7e mov\.w 252\[r0\], 252\[r0\] -+ 4ea: d5 0f 7e 7e mov\.w 252\[r0\], 252\[r15\] -+ 4ee: d9 00 7e fe 7f mov\.w 252\[r0\], 65532\[r0\] -+ 4f3: d9 0f 7e fe 7f mov\.w 252\[r0\], 65532\[r15\] -+ 4f8: d1 f0 7e mov\.w 252\[r15\], \[r0\] -+ 4fb: d1 ff 7e mov\.w 252\[r15\], \[r15\] -+ 4fe: d5 f0 7e 7e mov\.w 252\[r15\], 252\[r0\] -+ 502: d5 ff 7e 7e mov\.w 252\[r15\], 252\[r15\] -+ 506: d9 f0 7e fe 7f mov\.w 252\[r15\], 65532\[r0\] -+ 50b: d9 ff 7e fe 7f mov\.w 252\[r15\], 65532\[r15\] -+ 510: d2 00 fe 7f mov\.w 65532\[r0\], \[r0\] -+ 514: d2 0f fe 7f mov\.w 65532\[r0\], \[r15\] -+ 518: d6 00 fe 7f 7e mov\.w 65532\[r0\], 252\[r0\] -+ 51d: d6 0f fe 7f 7e mov\.w 65532\[r0\], 252\[r15\] -+ 522: da 00 fe 7f fe 7f mov\.w 65532\[r0\], 65532\[r0\] -+ 528: da 0f fe 7f fe 7f mov\.w 65532\[r0\], 65532\[r15\] -+ 52e: d2 f0 fe 7f mov\.w 65532\[r15\], \[r0\] -+ 532: d2 ff fe 7f mov\.w 65532\[r15\], \[r15\] -+ 536: d6 f0 fe 7f 7e mov\.w 65532\[r15\], 252\[r0\] -+ 53b: d6 ff fe 7f 7e mov\.w 65532\[r15\], 252\[r15\] -+ 540: da f0 fe 7f fe 7f mov\.w 65532\[r15\], 65532\[r0\] -+ 546: da ff fe 7f fe 7f mov\.w 65532\[r15\], 65532\[r15\] -+ 54c: e0 00 mov\.l \[r0\], \[r0\] -+ 54e: e0 0f mov\.l \[r0\], \[r15\] -+ 550: e4 00 3f mov\.l \[r0\], 252\[r0\] -+ 553: e4 0f 3f mov\.l \[r0\], 252\[r15\] -+ 556: e8 00 ff 3f mov\.l \[r0\], 65532\[r0\] -+ 55a: e8 0f ff 3f mov\.l \[r0\], 65532\[r15\] -+ 55e: e0 f0 mov\.l \[r15\], \[r0\] -+ 560: e0 ff mov\.l \[r15\], \[r15\] -+ 562: e4 f0 3f mov\.l \[r15\], 252\[r0\] -+ 565: e4 ff 3f mov\.l \[r15\], 252\[r15\] -+ 568: e8 f0 ff 3f mov\.l \[r15\], 65532\[r0\] -+ 56c: e8 ff ff 3f mov\.l \[r15\], 65532\[r15\] -+ 570: e1 00 3f mov\.l 252\[r0\], \[r0\] -+ 573: e1 0f 3f mov\.l 252\[r0\], \[r15\] -+ 576: e5 00 3f 3f mov\.l 252\[r0\], 252\[r0\] -+ 57a: e5 0f 3f 3f mov\.l 252\[r0\], 252\[r15\] -+ 57e: e9 00 3f ff 3f mov\.l 252\[r0\], 65532\[r0\] -+ 583: e9 0f 3f ff 3f mov\.l 252\[r0\], 65532\[r15\] -+ 588: e1 f0 3f mov\.l 252\[r15\], \[r0\] -+ 58b: e1 ff 3f mov\.l 252\[r15\], \[r15\] -+ 58e: e5 f0 3f 3f mov\.l 252\[r15\], 252\[r0\] -+ 592: e5 ff 3f 3f mov\.l 252\[r15\], 252\[r15\] -+ 596: e9 f0 3f ff 3f mov\.l 252\[r15\], 65532\[r0\] -+ 59b: e9 ff 3f ff 3f mov\.l 252\[r15\], 65532\[r15\] -+ 5a0: e2 00 ff 3f mov\.l 65532\[r0\], \[r0\] -+ 5a4: e2 0f ff 3f mov\.l 65532\[r0\], \[r15\] -+ 5a8: e6 00 ff 3f 3f mov\.l 65532\[r0\], 252\[r0\] -+ 5ad: e6 0f ff 3f 3f mov\.l 65532\[r0\], 252\[r15\] -+ 5b2: ea 00 ff 3f ff 3f mov\.l 65532\[r0\], 65532\[r0\] -+ 5b8: ea 0f ff 3f ff 3f mov\.l 65532\[r0\], 65532\[r15\] -+ 5be: e2 f0 ff 3f mov\.l 65532\[r15\], \[r0\] -+ 5c2: e2 ff ff 3f mov\.l 65532\[r15\], \[r15\] -+ 5c6: e6 f0 ff 3f 3f mov\.l 65532\[r15\], 252\[r0\] -+ 5cb: e6 ff ff 3f 3f mov\.l 65532\[r15\], 252\[r15\] -+ 5d0: ea f0 ff 3f ff 3f mov\.l 65532\[r15\], 65532\[r0\] -+ 5d6: ea ff ff 3f ff 3f mov\.l 65532\[r15\], 65532\[r15\] -+ 5dc: fd 20 00 mov\.b r0, \[r0\+\] -+ 5df: fd 20 f0 mov\.b r0, \[r15\+\] -+ 5e2: fd 20 0f mov\.b r15, \[r0\+\] -+ 5e5: fd 20 ff mov\.b r15, \[r15\+\] -+ 5e8: fd 21 00 mov\.w r0, \[r0\+\] -+ 5eb: fd 21 f0 mov\.w r0, \[r15\+\] -+ 5ee: fd 21 0f mov\.w r15, \[r0\+\] -+ 5f1: fd 21 ff mov\.w r15, \[r15\+\] -+ 5f4: fd 22 00 mov\.l r0, \[r0\+\] -+ 5f7: fd 22 f0 mov\.l r0, \[r15\+\] -+ 5fa: fd 22 0f mov\.l r15, \[r0\+\] -+ 5fd: fd 22 ff mov\.l r15, \[r15\+\] -+ 600: fd 28 00 mov\.b \[r0\+\], r0 -+ 603: fd 28 0f mov\.b \[r0\+\], r15 -+ 606: fd 28 f0 mov\.b \[r15\+\], r0 -+ 609: fd 28 ff mov\.b \[r15\+\], r15 -+ 60c: fd 29 00 mov\.w \[r0\+\], r0 -+ 60f: fd 29 0f mov\.w \[r0\+\], r15 -+ 612: fd 29 f0 mov\.w \[r15\+\], r0 -+ 615: fd 29 ff mov\.w \[r15\+\], r15 -+ 618: fd 2a 00 mov\.l \[r0\+\], r0 -+ 61b: fd 2a 0f mov\.l \[r0\+\], r15 -+ 61e: fd 2a f0 mov\.l \[r15\+\], r0 -+ 621: fd 2a ff mov\.l \[r15\+\], r15 -+ 624: fd 24 00 mov\.b r0, \[-r0\] -+ 627: fd 24 f0 mov\.b r0, \[-r15\] -+ 62a: fd 24 0f mov\.b r15, \[-r0\] -+ 62d: fd 24 ff mov\.b r15, \[-r15\] -+ 630: fd 25 00 mov\.w r0, \[-r0\] -+ 633: fd 25 f0 mov\.w r0, \[-r15\] -+ 636: fd 25 0f mov\.w r15, \[-r0\] -+ 639: fd 25 ff mov\.w r15, \[-r15\] -+ 63c: fd 26 00 mov\.l r0, \[-r0\] -+ 63f: fd 26 f0 mov\.l r0, \[-r15\] -+ 642: fd 26 0f mov\.l r15, \[-r0\] -+ 645: fd 26 ff mov\.l r15, \[-r15\] -+ 648: fd 2c 00 mov\.b \[-r0\], r0 -+ 64b: fd 2c 0f mov\.b \[-r0\], r15 -+ 64e: fd 2c f0 mov\.b \[-r15\], r0 -+ 651: fd 2c ff mov\.b \[-r15\], r15 -+ 654: fd 2d 00 mov\.w \[-r0\], r0 -+ 657: fd 2d 0f mov\.w \[-r0\], r15 -+ 65a: fd 2d f0 mov\.w \[-r15\], r0 -+ 65d: fd 2d ff mov\.w \[-r15\], r15 -+ 660: fd 2e 00 mov\.l \[-r0\], r0 -+ 663: fd 2e 0f mov\.l \[-r0\], r15 -+ 666: fd 2e f0 mov\.l \[-r15\], r0 -+ 669: fd 2e ff mov\.l \[-r15\], r15 ++ 198: f8 05 ff mov.w #-1, \[r0\] ++ 19b: f8 f5 ff mov.w #-1, \[r15\] ++ 19e: f9 05 7e ff mov.w #-1, 252\[r0\] ++ 1a2: f9 f5 7e ff mov.w #-1, 252\[r15\] ++ 1a6: fa 05 fe 7f ff mov.w #-1, 65532\[r0\] ++ 1ab: fa f5 fe 7f ff mov.w #-1, 65532\[r15\] ++ 1b0: f8 06 80 mov.l #-128, \[r0\] ++ 1b3: f8 f6 80 mov.l #-128, \[r15\] ++ 1b6: f9 06 3f 80 mov.l #-128, 252\[r0\] ++ 1ba: f9 f6 3f 80 mov.l #-128, 252\[r15\] ++ 1be: fa 06 ff 3f 80 mov.l #-128, 65532\[r0\] ++ 1c3: fa f6 ff 3f 80 mov.l #-128, 65532\[r15\] ++ 1c8: 3e 00 7f mov.l #127, \[r0\] ++ 1cb: f8 f6 7f mov.l #127, \[r15\] ++ 1ce: f9 06 3f 7f mov.l #127, 252\[r0\] ++ 1d2: f9 f6 3f 7f mov.l #127, 252\[r15\] ++ 1d6: fa 06 ff 3f 7f mov.l #127, 65532\[r0\] ++ 1db: fa f6 ff 3f 7f mov.l #127, 65532\[r15\] ++ 1e0: f8 0a 00 80 mov.l #0xffff8000, \[r0\] ++ 1e4: f8 fa 00 80 mov.l #0xffff8000, \[r15\] ++ 1e8: f9 0a 3f 00 80 mov.l #0xffff8000, 252\[r0\] ++ 1ed: f9 fa 3f 00 80 mov.l #0xffff8000, 252\[r15\] ++ 1f2: fa 0a ff 3f 00 80 mov.l #0xffff8000, 65532\[r0\] ++ 1f8: fa fa ff 3f 00 80 mov.l #0xffff8000, 65532\[r15\] ++ 1fe: f8 0e 00 80 00 mov.l #0x8000, \[r0\] ++ 203: f8 fe 00 80 00 mov.l #0x8000, \[r15\] ++ 208: f9 0e 3f 00 80 00 mov.l #0x8000, 252\[r0\] ++ 20e: f9 fe 3f 00 80 00 mov.l #0x8000, 252\[r15\] ++ 214: fa 0e ff 3f 00 80 00 mov.l #0x8000, 65532\[r0\] ++ 21b: fa fe ff 3f 00 80 00 mov.l #0x8000, 65532\[r15\] ++ 222: f8 0e 00 00 80 mov.l #0xff800000, \[r0\] ++ 227: f8 fe 00 00 80 mov.l #0xff800000, \[r15\] ++ 22c: f9 0e 3f 00 00 80 mov.l #0xff800000, 252\[r0\] ++ 232: f9 fe 3f 00 00 80 mov.l #0xff800000, 252\[r15\] ++ 238: fa 0e ff 3f 00 00 80 mov.l #0xff800000, 65532\[r0\] ++ 23f: fa fe ff 3f 00 00 80 mov.l #0xff800000, 65532\[r15\] ++ 246: f8 0e ff ff 7f mov.l #0x7fffff, \[r0\] ++ 24b: f8 fe ff ff 7f mov.l #0x7fffff, \[r15\] ++ 250: f9 0e 3f ff ff 7f mov.l #0x7fffff, 252\[r0\] ++ 256: f9 fe 3f ff ff 7f mov.l #0x7fffff, 252\[r15\] ++ 25c: fa 0e ff 3f ff ff 7f mov.l #0x7fffff, 65532\[r0\] ++ 263: fa fe ff 3f ff ff 7f mov.l #0x7fffff, 65532\[r15\] ++ 26a: f8 02 00 00 00 80 mov.l #0x80000000, \[r0\] ++ 270: f8 f2 00 00 00 80 mov.l #0x80000000, \[r15\] ++ 276: f9 02 3f 00 00 00 80 mov.l #0x80000000, 252\[r0\] ++ 27d: f9 f2 3f 00 00 00 80 mov.l #0x80000000, 252\[r15\] ++ 284: fa 02 ff 3f 00 00 00 80 mov.l #0x80000000, 65532\[r0\] ++ 28c: fa f2 ff 3f 00 00 00 80 mov.l #0x80000000, 65532\[r15\] ++ 294: f8 02 ff ff ff 7f mov.l #0x7fffffff, \[r0\] ++ 29a: f8 f2 ff ff ff 7f mov.l #0x7fffffff, \[r15\] ++ 2a0: f9 02 3f ff ff ff 7f mov.l #0x7fffffff, 252\[r0\] ++ 2a7: f9 f2 3f ff ff ff 7f mov.l #0x7fffffff, 252\[r15\] ++ 2ae: fa 02 ff 3f ff ff ff 7f mov.l #0x7fffffff, 65532\[r0\] ++ 2b6: fa f2 ff 3f ff ff ff 7f mov.l #0x7fffffff, 65532\[r15\] ++ 2be: cc 00 mov.b \[r0\], r0 ++ 2c0: cc 0f mov.b \[r0\], r15 ++ 2c2: cc f0 mov.b \[r15\], r0 ++ 2c4: cc ff mov.b \[r15\], r15 ++ 2c6: cd 00 fc mov.b 252\[r0\], r0 ++ 2c9: cd 0f fc mov.b 252\[r0\], r15 ++ 2cc: cd f0 fc mov.b 252\[r15\], r0 ++ 2cf: cd ff fc mov.b 252\[r15\], r15 ++ 2d2: ce 00 fc ff mov.b 65532\[r0\], r0 ++ 2d6: ce 0f fc ff mov.b 65532\[r0\], r15 ++ 2da: ce f0 fc ff mov.b 65532\[r15\], r0 ++ 2de: ce ff fc ff mov.b 65532\[r15\], r15 ++ 2e2: dc 00 mov.w \[r0\], r0 ++ 2e4: dc 0f mov.w \[r0\], r15 ++ 2e6: dc f0 mov.w \[r15\], r0 ++ 2e8: dc ff mov.w \[r15\], r15 ++ 2ea: dd 00 7e mov.w 252\[r0\], r0 ++ 2ed: dd 0f 7e mov.w 252\[r0\], r15 ++ 2f0: dd f0 7e mov.w 252\[r15\], r0 ++ 2f3: dd ff 7e mov.w 252\[r15\], r15 ++ 2f6: de 00 fe 7f mov.w 65532\[r0\], r0 ++ 2fa: de 0f fe 7f mov.w 65532\[r0\], r15 ++ 2fe: de f0 fe 7f mov.w 65532\[r15\], r0 ++ 302: de ff fe 7f mov.w 65532\[r15\], r15 ++ 306: ec 00 mov.l \[r0\], r0 ++ 308: ec 0f mov.l \[r0\], r15 ++ 30a: ec f0 mov.l \[r15\], r0 ++ 30c: ec ff mov.l \[r15\], r15 ++ 30e: ed 00 3f mov.l 252\[r0\], r0 ++ 311: ed 0f 3f mov.l 252\[r0\], r15 ++ 314: ed f0 3f mov.l 252\[r15\], r0 ++ 317: ed ff 3f mov.l 252\[r15\], r15 ++ 31a: ee 00 ff 3f mov.l 65532\[r0\], r0 ++ 31e: ee 0f ff 3f mov.l 65532\[r0\], r15 ++ 322: ee f0 ff 3f mov.l 65532\[r15\], r0 ++ 326: ee ff ff 3f mov.l 65532\[r15\], r15 ++ 32a: fe 40 00 mov.b \[r0, r0\], r0 ++ 32d: fe 40 0f mov.b \[r0, r0\], r15 ++ 330: fe 40 f0 mov.b \[r0, r15\], r0 ++ 333: fe 40 ff mov.b \[r0, r15\], r15 ++ 336: fe 4f 00 mov.b \[r15, r0\], r0 ++ 339: fe 4f 0f mov.b \[r15, r0\], r15 ++ 33c: fe 4f f0 mov.b \[r15, r15\], r0 ++ 33f: fe 4f ff mov.b \[r15, r15\], r15 ++ 342: fe 50 00 mov.w \[r0, r0\], r0 ++ 345: fe 50 0f mov.w \[r0, r0\], r15 ++ 348: fe 50 f0 mov.w \[r0, r15\], r0 ++ 34b: fe 50 ff mov.w \[r0, r15\], r15 ++ 34e: fe 5f 00 mov.w \[r15, r0\], r0 ++ 351: fe 5f 0f mov.w \[r15, r0\], r15 ++ 354: fe 5f f0 mov.w \[r15, r15\], r0 ++ 357: fe 5f ff mov.w \[r15, r15\], r15 ++ 35a: fe 60 00 mov.l \[r0, r0\], r0 ++ 35d: fe 60 0f mov.l \[r0, r0\], r15 ++ 360: fe 60 f0 mov.l \[r0, r15\], r0 ++ 363: fe 60 ff mov.l \[r0, r15\], r15 ++ 366: fe 6f 00 mov.l \[r15, r0\], r0 ++ 369: fe 6f 0f mov.l \[r15, r0\], r15 ++ 36c: fe 6f f0 mov.l \[r15, r15\], r0 ++ 36f: fe 6f ff mov.l \[r15, r15\], r15 ++ 372: c3 01 mov.b r1, \[r0\] ++ 374: c3 f1 mov.b r1, \[r15\] ++ 376: c7 01 fc mov.b r1, 252\[r0\] ++ 379: c7 f1 fc mov.b r1, 252\[r15\] ++ 37c: cb 01 fc ff mov.b r1, 65532\[r0\] ++ 380: cb f1 fc ff mov.b r1, 65532\[r15\] ++ 384: c3 0f mov.b r15, \[r0\] ++ 386: c3 ff mov.b r15, \[r15\] ++ 388: c7 0f fc mov.b r15, 252\[r0\] ++ 38b: c7 ff fc mov.b r15, 252\[r15\] ++ 38e: cb 0f fc ff mov.b r15, 65532\[r0\] ++ 392: cb ff fc ff mov.b r15, 65532\[r15\] ++ 396: d3 01 mov.w r1, \[r0\] ++ 398: d3 f1 mov.w r1, \[r15\] ++ 39a: d7 01 7e mov.w r1, 252\[r0\] ++ 39d: d7 f1 7e mov.w r1, 252\[r15\] ++ 3a0: db 01 fe 7f mov.w r1, 65532\[r0\] ++ 3a4: db f1 fe 7f mov.w r1, 65532\[r15\] ++ 3a8: d3 0f mov.w r15, \[r0\] ++ 3aa: d3 ff mov.w r15, \[r15\] ++ 3ac: d7 0f 7e mov.w r15, 252\[r0\] ++ 3af: d7 ff 7e mov.w r15, 252\[r15\] ++ 3b2: db 0f fe 7f mov.w r15, 65532\[r0\] ++ 3b6: db ff fe 7f mov.w r15, 65532\[r15\] ++ 3ba: e3 01 mov.l r1, \[r0\] ++ 3bc: e3 f1 mov.l r1, \[r15\] ++ 3be: e7 01 3f mov.l r1, 252\[r0\] ++ 3c1: e7 f1 3f mov.l r1, 252\[r15\] ++ 3c4: eb 01 ff 3f mov.l r1, 65532\[r0\] ++ 3c8: eb f1 ff 3f mov.l r1, 65532\[r15\] ++ 3cc: e3 0f mov.l r15, \[r0\] ++ 3ce: e3 ff mov.l r15, \[r15\] ++ 3d0: e7 0f 3f mov.l r15, 252\[r0\] ++ 3d3: e7 ff 3f mov.l r15, 252\[r15\] ++ 3d6: eb 0f ff 3f mov.l r15, 65532\[r0\] ++ 3da: eb ff ff 3f mov.l r15, 65532\[r15\] ++ 3de: fe 00 00 mov.b r0, \[r0, r0\] ++ 3e1: fe 00 f0 mov.b r0, \[r0, r15\] ++ 3e4: fe 0f 00 mov.b r0, \[r15, r0\] ++ 3e7: fe 0f f0 mov.b r0, \[r15, r15\] ++ 3ea: fe 00 0f mov.b r15, \[r0, r0\] ++ 3ed: fe 00 ff mov.b r15, \[r0, r15\] ++ 3f0: fe 0f 0f mov.b r15, \[r15, r0\] ++ 3f3: fe 0f ff mov.b r15, \[r15, r15\] ++ 3f6: fe 10 00 mov.w r0, \[r0, r0\] ++ 3f9: fe 10 f0 mov.w r0, \[r0, r15\] ++ 3fc: fe 1f 00 mov.w r0, \[r15, r0\] ++ 3ff: fe 1f f0 mov.w r0, \[r15, r15\] ++ 402: fe 10 0f mov.w r15, \[r0, r0\] ++ 405: fe 10 ff mov.w r15, \[r0, r15\] ++ 408: fe 1f 0f mov.w r15, \[r15, r0\] ++ 40b: fe 1f ff mov.w r15, \[r15, r15\] ++ 40e: fe 20 00 mov.l r0, \[r0, r0\] ++ 411: fe 20 f0 mov.l r0, \[r0, r15\] ++ 414: fe 2f 00 mov.l r0, \[r15, r0\] ++ 417: fe 2f f0 mov.l r0, \[r15, r15\] ++ 41a: fe 20 0f mov.l r15, \[r0, r0\] ++ 41d: fe 20 ff mov.l r15, \[r0, r15\] ++ 420: fe 2f 0f mov.l r15, \[r15, r0\] ++ 423: fe 2f ff mov.l r15, \[r15, r15\] ++ 426: c0 00 mov.b \[r0\], \[r0\] ++ 428: c0 0f mov.b \[r0\], \[r15\] ++ 42a: c4 00 fc mov.b \[r0\], 252\[r0\] ++ 42d: c4 0f fc mov.b \[r0\], 252\[r15\] ++ 430: c8 00 fc ff mov.b \[r0\], 65532\[r0\] ++ 434: c8 0f fc ff mov.b \[r0\], 65532\[r15\] ++ 438: c0 f0 mov.b \[r15\], \[r0\] ++ 43a: c0 ff mov.b \[r15\], \[r15\] ++ 43c: c4 f0 fc mov.b \[r15\], 252\[r0\] ++ 43f: c4 ff fc mov.b \[r15\], 252\[r15\] ++ 442: c8 f0 fc ff mov.b \[r15\], 65532\[r0\] ++ 446: c8 ff fc ff mov.b \[r15\], 65532\[r15\] ++ 44a: c1 00 fc mov.b 252\[r0\], \[r0\] ++ 44d: c1 0f fc mov.b 252\[r0\], \[r15\] ++ 450: c5 00 fc fc mov.b 252\[r0\], 252\[r0\] ++ 454: c5 0f fc fc mov.b 252\[r0\], 252\[r15\] ++ 458: c9 00 fc fc ff mov.b 252\[r0\], 65532\[r0\] ++ 45d: c9 0f fc fc ff mov.b 252\[r0\], 65532\[r15\] ++ 462: c1 f0 fc mov.b 252\[r15\], \[r0\] ++ 465: c1 ff fc mov.b 252\[r15\], \[r15\] ++ 468: c5 f0 fc fc mov.b 252\[r15\], 252\[r0\] ++ 46c: c5 ff fc fc mov.b 252\[r15\], 252\[r15\] ++ 470: c9 f0 fc fc ff mov.b 252\[r15\], 65532\[r0\] ++ 475: c9 ff fc fc ff mov.b 252\[r15\], 65532\[r15\] ++ 47a: c2 00 fc ff mov.b 65532\[r0\], \[r0\] ++ 47e: c2 0f fc ff mov.b 65532\[r0\], \[r15\] ++ 482: c6 00 fc ff fc mov.b 65532\[r0\], 252\[r0\] ++ 487: c6 0f fc ff fc mov.b 65532\[r0\], 252\[r15\] ++ 48c: ca 00 fc ff fc ff mov.b 65532\[r0\], 65532\[r0\] ++ 492: ca 0f fc ff fc ff mov.b 65532\[r0\], 65532\[r15\] ++ 498: c2 f0 fc ff mov.b 65532\[r15\], \[r0\] ++ 49c: c2 ff fc ff mov.b 65532\[r15\], \[r15\] ++ 4a0: c6 f0 fc ff fc mov.b 65532\[r15\], 252\[r0\] ++ 4a5: c6 ff fc ff fc mov.b 65532\[r15\], 252\[r15\] ++ 4aa: ca f0 fc ff fc ff mov.b 65532\[r15\], 65532\[r0\] ++ 4b0: ca ff fc ff fc ff mov.b 65532\[r15\], 65532\[r15\] ++ 4b6: d0 00 mov.w \[r0\], \[r0\] ++ 4b8: d0 0f mov.w \[r0\], \[r15\] ++ 4ba: d4 00 7e mov.w \[r0\], 252\[r0\] ++ 4bd: d4 0f 7e mov.w \[r0\], 252\[r15\] ++ 4c0: d8 00 fe 7f mov.w \[r0\], 65532\[r0\] ++ 4c4: d8 0f fe 7f mov.w \[r0\], 65532\[r15\] ++ 4c8: d0 f0 mov.w \[r15\], \[r0\] ++ 4ca: d0 ff mov.w \[r15\], \[r15\] ++ 4cc: d4 f0 7e mov.w \[r15\], 252\[r0\] ++ 4cf: d4 ff 7e mov.w \[r15\], 252\[r15\] ++ 4d2: d8 f0 fe 7f mov.w \[r15\], 65532\[r0\] ++ 4d6: d8 ff fe 7f mov.w \[r15\], 65532\[r15\] ++ 4da: d1 00 7e mov.w 252\[r0\], \[r0\] ++ 4dd: d1 0f 7e mov.w 252\[r0\], \[r15\] ++ 4e0: d5 00 7e 7e mov.w 252\[r0\], 252\[r0\] ++ 4e4: d5 0f 7e 7e mov.w 252\[r0\], 252\[r15\] ++ 4e8: d9 00 7e fe 7f mov.w 252\[r0\], 65532\[r0\] ++ 4ed: d9 0f 7e fe 7f mov.w 252\[r0\], 65532\[r15\] ++ 4f2: d1 f0 7e mov.w 252\[r15\], \[r0\] ++ 4f5: d1 ff 7e mov.w 252\[r15\], \[r15\] ++ 4f8: d5 f0 7e 7e mov.w 252\[r15\], 252\[r0\] ++ 4fc: d5 ff 7e 7e mov.w 252\[r15\], 252\[r15\] ++ 500: d9 f0 7e fe 7f mov.w 252\[r15\], 65532\[r0\] ++ 505: d9 ff 7e fe 7f mov.w 252\[r15\], 65532\[r15\] ++ 50a: d2 00 fe 7f mov.w 65532\[r0\], \[r0\] ++ 50e: d2 0f fe 7f mov.w 65532\[r0\], \[r15\] ++ 512: d6 00 fe 7f 7e mov.w 65532\[r0\], 252\[r0\] ++ 517: d6 0f fe 7f 7e mov.w 65532\[r0\], 252\[r15\] ++ 51c: da 00 fe 7f fe 7f mov.w 65532\[r0\], 65532\[r0\] ++ 522: da 0f fe 7f fe 7f mov.w 65532\[r0\], 65532\[r15\] ++ 528: d2 f0 fe 7f mov.w 65532\[r15\], \[r0\] ++ 52c: d2 ff fe 7f mov.w 65532\[r15\], \[r15\] ++ 530: d6 f0 fe 7f 7e mov.w 65532\[r15\], 252\[r0\] ++ 535: d6 ff fe 7f 7e mov.w 65532\[r15\], 252\[r15\] ++ 53a: da f0 fe 7f fe 7f mov.w 65532\[r15\], 65532\[r0\] ++ 540: da ff fe 7f fe 7f mov.w 65532\[r15\], 65532\[r15\] ++ 546: e0 00 mov.l \[r0\], \[r0\] ++ 548: e0 0f mov.l \[r0\], \[r15\] ++ 54a: e4 00 3f mov.l \[r0\], 252\[r0\] ++ 54d: e4 0f 3f mov.l \[r0\], 252\[r15\] ++ 550: e8 00 ff 3f mov.l \[r0\], 65532\[r0\] ++ 554: e8 0f ff 3f mov.l \[r0\], 65532\[r15\] ++ 558: e0 f0 mov.l \[r15\], \[r0\] ++ 55a: e0 ff mov.l \[r15\], \[r15\] ++ 55c: e4 f0 3f mov.l \[r15\], 252\[r0\] ++ 55f: e4 ff 3f mov.l \[r15\], 252\[r15\] ++ 562: e8 f0 ff 3f mov.l \[r15\], 65532\[r0\] ++ 566: e8 ff ff 3f mov.l \[r15\], 65532\[r15\] ++ 56a: e1 00 3f mov.l 252\[r0\], \[r0\] ++ 56d: e1 0f 3f mov.l 252\[r0\], \[r15\] ++ 570: e5 00 3f 3f mov.l 252\[r0\], 252\[r0\] ++ 574: e5 0f 3f 3f mov.l 252\[r0\], 252\[r15\] ++ 578: e9 00 3f ff 3f mov.l 252\[r0\], 65532\[r0\] ++ 57d: e9 0f 3f ff 3f mov.l 252\[r0\], 65532\[r15\] ++ 582: e1 f0 3f mov.l 252\[r15\], \[r0\] ++ 585: e1 ff 3f mov.l 252\[r15\], \[r15\] ++ 588: e5 f0 3f 3f mov.l 252\[r15\], 252\[r0\] ++ 58c: e5 ff 3f 3f mov.l 252\[r15\], 252\[r15\] ++ 590: e9 f0 3f ff 3f mov.l 252\[r15\], 65532\[r0\] ++ 595: e9 ff 3f ff 3f mov.l 252\[r15\], 65532\[r15\] ++ 59a: e2 00 ff 3f mov.l 65532\[r0\], \[r0\] ++ 59e: e2 0f ff 3f mov.l 65532\[r0\], \[r15\] ++ 5a2: e6 00 ff 3f 3f mov.l 65532\[r0\], 252\[r0\] ++ 5a7: e6 0f ff 3f 3f mov.l 65532\[r0\], 252\[r15\] ++ 5ac: ea 00 ff 3f ff 3f mov.l 65532\[r0\], 65532\[r0\] ++ 5b2: ea 0f ff 3f ff 3f mov.l 65532\[r0\], 65532\[r15\] ++ 5b8: e2 f0 ff 3f mov.l 65532\[r15\], \[r0\] ++ 5bc: e2 ff ff 3f mov.l 65532\[r15\], \[r15\] ++ 5c0: e6 f0 ff 3f 3f mov.l 65532\[r15\], 252\[r0\] ++ 5c5: e6 ff ff 3f 3f mov.l 65532\[r15\], 252\[r15\] ++ 5ca: ea f0 ff 3f ff 3f mov.l 65532\[r15\], 65532\[r0\] ++ 5d0: ea ff ff 3f ff 3f mov.l 65532\[r15\], 65532\[r15\] ++ 5d6: fd 20 00 mov.b r0, \[r0\+\] ++ 5d9: fd 20 f0 mov.b r0, \[r15\+\] ++ 5dc: fd 20 0f mov.b r15, \[r0\+\] ++ 5df: fd 20 ff mov.b r15, \[r15\+\] ++ 5e2: fd 21 00 mov.w r0, \[r0\+\] ++ 5e5: fd 21 f0 mov.w r0, \[r15\+\] ++ 5e8: fd 21 0f mov.w r15, \[r0\+\] ++ 5eb: fd 21 ff mov.w r15, \[r15\+\] ++ 5ee: fd 22 00 mov.l r0, \[r0\+\] ++ 5f1: fd 22 f0 mov.l r0, \[r15\+\] ++ 5f4: fd 22 0f mov.l r15, \[r0\+\] ++ 5f7: fd 22 ff mov.l r15, \[r15\+\] ++ 5fa: fd 28 00 mov.b \[r0\+\], r0 ++ 5fd: fd 28 0f mov.b \[r0\+\], r15 ++ 600: fd 28 f0 mov.b \[r15\+\], r0 ++ 603: fd 28 ff mov.b \[r15\+\], r15 ++ 606: fd 29 00 mov.w \[r0\+\], r0 ++ 609: fd 29 0f mov.w \[r0\+\], r15 ++ 60c: fd 29 f0 mov.w \[r15\+\], r0 ++ 60f: fd 29 ff mov.w \[r15\+\], r15 ++ 612: fd 2a 00 mov.l \[r0\+\], r0 ++ 615: fd 2a 0f mov.l \[r0\+\], r15 ++ 618: fd 2a f0 mov.l \[r15\+\], r0 ++ 61b: fd 2a ff mov.l \[r15\+\], r15 ++ 61e: fd 24 00 mov.b r0, \[-r0\] ++ 621: fd 24 f0 mov.b r0, \[-r15\] ++ 624: fd 24 0f mov.b r15, \[-r0\] ++ 627: fd 24 ff mov.b r15, \[-r15\] ++ 62a: fd 25 00 mov.w r0, \[-r0\] ++ 62d: fd 25 f0 mov.w r0, \[-r15\] ++ 630: fd 25 0f mov.w r15, \[-r0\] ++ 633: fd 25 ff mov.w r15, \[-r15\] ++ 636: fd 26 00 mov.l r0, \[-r0\] ++ 639: fd 26 f0 mov.l r0, \[-r15\] ++ 63c: fd 26 0f mov.l r15, \[-r0\] ++ 63f: fd 26 ff mov.l r15, \[-r15\] ++ 642: fd 2c 00 mov.b \[-r0\], r0 ++ 645: fd 2c 0f mov.b \[-r0\], r15 ++ 648: fd 2c f0 mov.b \[-r15\], r0 ++ 64b: fd 2c ff mov.b \[-r15\], r15 ++ 64e: fd 2d 00 mov.w \[-r0\], r0 ++ 651: fd 2d 0f mov.w \[-r0\], r15 ++ 654: fd 2d f0 mov.w \[-r15\], r0 ++ 657: fd 2d ff mov.w \[-r15\], r15 ++ 65a: fd 2e 00 mov.l \[-r0\], r0 ++ 65d: fd 2e 0f mov.l \[-r0\], r15 ++ 660: fd 2e f0 mov.l \[-r15\], r0 ++ 663: fd 2e ff mov.l \[-r15\], r15 diff --git a/gas/testsuite/gas/rx/mov.sm b/gas/testsuite/gas/rx/mov.sm new file mode 100644 index 0000000..f68f24c @@ -1821230,12 +1831150,11 @@ index 0000000..1bd6cc6 \ No newline at end of file diff --git a/gas/testsuite/gas/rx/rx.exp b/gas/testsuite/gas/rx/rx.exp new file mode 100644 -index 0000000..408cbdd +index 0000000..310f52d --- /dev/null +++ b/gas/testsuite/gas/rx/rx.exp -@@ -0,0 +1,34 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,33 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1831584,12 +1841503,11 @@ index 0000000..1a72b13 + diff --git a/gas/testsuite/gas/score/relax.exp b/gas/testsuite/gas/score/relax.exp new file mode 100644 -index 0000000..bfdbf23 +index 0000000..8d2120f --- /dev/null +++ b/gas/testsuite/gas/score/relax.exp -@@ -0,0 +1,37 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,36 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1831627,12 +1841545,11 @@ index 0000000..bfdbf23 + diff --git a/gas/testsuite/gas/score/relax_32.exp b/gas/testsuite/gas/score/relax_32.exp new file mode 100644 -index 0000000..e37d1aa +index 0000000..2befec7 --- /dev/null +++ b/gas/testsuite/gas/score/relax_32.exp -@@ -0,0 +1,41 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,40 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1832209,12 +1842126,11 @@ index 0000000..fe89bad + tran "sdbbp 12", "sdbbp! 12" diff --git a/gas/testsuite/gas/sh/arch/arch.exp b/gas/testsuite/gas/sh/arch/arch.exp new file mode 100644 -index 0000000..6498f14 +index 0000000..9dc2caf --- /dev/null +++ b/gas/testsuite/gas/sh/arch/arch.exp -@@ -0,0 +1,522 @@ -+# Copyright (C) 2004, 2005, 2007, 2008 -+# Free Software Foundation, Inc. +@@ -0,0 +1,521 @@ ++# Copyright (C) 2004-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1838186,12 +1848102,11 @@ index 0000000..8d48962 + dct plds m0,MACL ;!/* 11111101xxyynnnn plds ,MACL */ {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up} diff --git a/gas/testsuite/gas/sh/basic.exp b/gas/testsuite/gas/sh/basic.exp new file mode 100644 -index 0000000..2daa038 +index 0000000..13b37fd --- /dev/null +++ b/gas/testsuite/gas/sh/basic.exp -@@ -0,0 +1,182 @@ -+# Copyright (C) 1995, 1996, 1997, 2002, 2003, 2004, 2005, 2006, 2007, 2009 -+# Free Software Foundation, Inc. +@@ -0,0 +1,181 @@ ++# Copyright (C) 1995-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1838613,11 +1848528,11 @@ index 0000000..ec2338a + pclr a0 pmuls x1,y1,a0 ! { dg-warning "register is same" } diff --git a/gas/testsuite/gas/sh/err.exp b/gas/testsuite/gas/sh/err.exp new file mode 100644 -index 0000000..dd54376 +index 0000000..f9fdd40 --- /dev/null +++ b/gas/testsuite/gas/sh/err.exp @@ -0,0 +1,28 @@ -+# Copyright (C) 2000, 2005, 2007 Free Software Foundation, Inc. ++# Copyright (C) 2000-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1845740,11 +1855655,11 @@ index 0000000..b2ec30a +y1: diff --git a/gas/testsuite/gas/sh/sh64/sh64.exp b/gas/testsuite/gas/sh/sh64/sh64.exp new file mode 100644 -index 0000000..43f1898 +index 0000000..b51ee2b --- /dev/null +++ b/gas/testsuite/gas/sh/sh64/sh64.exp @@ -0,0 +1,27 @@ -+# Copyright (C) 2000, 2002, 2005, 2007 Free Software Foundation, Inc. ++# Copyright (C) 2000-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1846965,12 +1856880,11 @@ index 0000000..b67b8f7 + mov.l .L321,r5 diff --git a/gas/testsuite/gas/sparc-solaris/addend.exp b/gas/testsuite/gas/sparc-solaris/addend.exp new file mode 100644 -index 0000000..4cfdc00 +index 0000000..f60ea5a --- /dev/null +++ b/gas/testsuite/gas/sparc-solaris/addend.exp -@@ -0,0 +1,53 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,52 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1847041,12 +1856955,11 @@ index 0000000..18eb108 + .word foo1+4 diff --git a/gas/testsuite/gas/sparc-solaris/gas.exp b/gas/testsuite/gas/sparc-solaris/gas.exp new file mode 100644 -index 0000000..a5740e1 +index 0000000..3d51ced --- /dev/null +++ b/gas/testsuite/gas/sparc-solaris/gas.exp -@@ -0,0 +1,27 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,26 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1848195,12 +1858108,12 @@ index 0000000..c84e3e8 + st %r1, [10+%r18] diff --git a/gas/testsuite/gas/sparc/ldd_std.d b/gas/testsuite/gas/sparc/ldd_std.d new file mode 100644 -index 0000000..2d0083b +index 0000000..6215fe3 --- /dev/null +++ b/gas/testsuite/gas/sparc/ldd_std.d @@ -0,0 +1,13 @@ +#as: -Av8 -+#objdump: -dr ++#objdump: -dr -m sparc +#name: sparc LDD/STD + +.*: +file format .*sparc.* @@ -1848332,12 +1858245,11 @@ index 0000000..fac5e48 +foo: diff --git a/gas/testsuite/gas/sparc/mismatch.exp b/gas/testsuite/gas/sparc/mismatch.exp new file mode 100644 -index 0000000..65a68c0 +index 0000000..5e23a17 --- /dev/null +++ b/gas/testsuite/gas/sparc/mismatch.exp -@@ -0,0 +1,37 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,36 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1848771,10 +1858683,10 @@ index 0000000..18c68bb + prefetcha [%g1]%asi,#one_read diff --git a/gas/testsuite/gas/sparc/rdhpr.d b/gas/testsuite/gas/sparc/rdhpr.d new file mode 100644 -index 0000000..fbbd76d +index 0000000..7a12ad3 --- /dev/null +++ b/gas/testsuite/gas/sparc/rdhpr.d -@@ -0,0 +1,15 @@ +@@ -0,0 +1,17 @@ +#as: -64 -Av9 +#objdump: -dr +#name: sparc64 rdhpr @@ -1848789,13 +1858701,15 @@ index 0000000..fbbd76d + 8: 87 48 c0 00 rdhpr %hintp, %g3 + c: 89 49 40 00 rdhpr %htba, %g4 + 10: 8b 49 80 00 rdhpr %hver, %g5 -+ 14: 8d 4f c0 00 rdhpr %hstick_cmpr, %g6 ++ 14: 8d 4f 00 00 rdhpr %hstick_offset, %g6 ++ 18: 8b 4f 40 00 rdhpr %hstick_enable, %g5 ++ 1c: 89 4f c0 00 rdhpr %hstick_cmpr, %g4 diff --git a/gas/testsuite/gas/sparc/rdhpr.s b/gas/testsuite/gas/sparc/rdhpr.s new file mode 100644 -index 0000000..5e22f07 +index 0000000..8f669c7 --- /dev/null +++ b/gas/testsuite/gas/sparc/rdhpr.s -@@ -0,0 +1,8 @@ +@@ -0,0 +1,10 @@ +# Test rdpr + .text + rdhpr %hpstate,%g1 @@ -1848803,7 +1858717,9 @@ index 0000000..5e22f07 + rdhpr %hintp,%g3 + rdhpr %htba,%g4 + rdhpr %hver,%g5 -+ rdhpr %hstick_cmpr,%g6 ++ rdhpr %hstick_offset,%g6 ++ rdhpr %hstick_enable,%g5 ++ rdhpr %hstick_cmpr,%g4 diff --git a/gas/testsuite/gas/sparc/rdpr.d b/gas/testsuite/gas/sparc/rdpr.d new file mode 100644 index 0000000..6ddc24a @@ -1849218,12 +1859134,11 @@ index 0000000..825036d + setsw -1,%g4 diff --git a/gas/testsuite/gas/sparc/sparc.exp b/gas/testsuite/gas/sparc/sparc.exp new file mode 100644 -index 0000000..28d8a4f +index 0000000..413d2e3 --- /dev/null +++ b/gas/testsuite/gas/sparc/sparc.exp -@@ -0,0 +1,101 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,100 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1850296,10 +1860211,10 @@ index 0000000..38c0410 + invalw diff --git a/gas/testsuite/gas/sparc/wrhpr.d b/gas/testsuite/gas/sparc/wrhpr.d new file mode 100644 -index 0000000..a9ec2b6 +index 0000000..67d7de3 --- /dev/null +++ b/gas/testsuite/gas/sparc/wrhpr.d -@@ -0,0 +1,14 @@ +@@ -0,0 +1,16 @@ +#as: -64 -Av9 +#objdump: -dr +#name: sparc64 wrhpr @@ -1850313,20 +1860228,24 @@ index 0000000..a9ec2b6 + 4: 83 98 80 00 wrhpr %g2, %htstate + 8: 87 98 c0 00 wrhpr %g3, %hintp + c: 8b 99 00 00 wrhpr %g4, %htba -+ 10: bf 99 40 00 wrhpr %g5, %hstick_cmpr ++ 10: b9 99 40 00 wrhpr %g5, %hstick_offset ++ 14: bb 99 80 00 wrhpr %g6, %hstick_enable ++ 18: bf 99 c0 00 wrhpr %g7, %hstick_cmpr diff --git a/gas/testsuite/gas/sparc/wrhpr.s b/gas/testsuite/gas/sparc/wrhpr.s new file mode 100644 -index 0000000..838bb53 +index 0000000..b93733e --- /dev/null +++ b/gas/testsuite/gas/sparc/wrhpr.s -@@ -0,0 +1,7 @@ +@@ -0,0 +1,9 @@ +# Test wrpr + .text + wrhpr %g1,%hpstate + wrhpr %g2,%htstate + wrhpr %g3,%hintp + wrhpr %g4,%htba -+ wrhpr %g5,%hstick_cmpr ++ wrhpr %g5,%hstick_offset ++ wrhpr %g6,%hstick_enable ++ wrhpr %g7,%hstick_cmpr diff --git a/gas/testsuite/gas/sparc/wrpr.d b/gas/testsuite/gas/sparc/wrpr.d new file mode 100644 index 0000000..d0c1b35 @@ -1850403,12 +1860322,11 @@ index 0000000..50ff458 +#0+20 32 +foo1\+0x0+4 diff --git a/gas/testsuite/gas/sun4/addend.exp b/gas/testsuite/gas/sun4/addend.exp new file mode 100644 -index 0000000..5b7169f +index 0000000..0178777 --- /dev/null +++ b/gas/testsuite/gas/sun4/addend.exp -@@ -0,0 +1,24 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,23 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1850450,12 +1860368,11 @@ index 0000000..18eb108 + .word foo1+4 diff --git a/gas/testsuite/gas/symver/symver.exp b/gas/testsuite/gas/symver/symver.exp new file mode 100644 -index 0000000..9b6af4b +index 0000000..98707fd --- /dev/null +++ b/gas/testsuite/gas/symver/symver.exp -@@ -0,0 +1,66 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,65 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -1850522,16 +1860439,17 @@ index 0000000..9b6af4b +} diff --git a/gas/testsuite/gas/symver/symver0.d b/gas/testsuite/gas/symver/symver0.d new file mode 100644 -index 0000000..9ad6c88 +index 0000000..c7accc7 --- /dev/null +++ b/gas/testsuite/gas/symver/symver0.d -@@ -0,0 +1,10 @@ +@@ -0,0 +1,11 @@ +#nm: -n +#name: symver symver0 +# +# The #... and #pass are there to match extra symbols inserted by +# some toolchains, eg arm-elf toolchain will add $d. + ++#... +[ ]+U foo@version1 +#... +0+0000000 D foo1 @@ -1850554,16 +1860472,17 @@ index 0000000..fa690f7 + .size foo1,L_foo1-foo1 diff --git a/gas/testsuite/gas/symver/symver1.d b/gas/testsuite/gas/symver/symver1.d new file mode 100644 -index 0000000..ab9b949 +index 0000000..b480e37 --- /dev/null +++ b/gas/testsuite/gas/symver/symver1.d -@@ -0,0 +1,13 @@ +@@ -0,0 +1,14 @@ +#nm: -n +#name: symver symver1 +# +# The #... and #pass are there to match extra symbols inserted by +# some toolchains, eg arm-elf toolchain will add $d. + ++#... +[ ]+U foo@version1 +#... +0+0000000 D foo1@@version1 @@ -1858285,12 +1868204,11 @@ index 0000000..cf9fa50 + 2d: 071f0000.* diff --git a/gas/testsuite/gas/tic4x/tic4x.exp b/gas/testsuite/gas/tic4x/tic4x.exp new file mode 100644 -index 0000000..99c95ab +index 0000000..731c06b --- /dev/null +++ b/gas/testsuite/gas/tic4x/tic4x.exp -@@ -0,0 +1,81 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,80 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -2203349,68 +2213267,68 @@ index 0000000..1a4a114 + b: 0064.* diff --git a/gas/testsuite/gas/tic54x/macro.s b/gas/testsuite/gas/tic54x/macro.s new file mode 100644 -index 0000000..806473e +index 0000000..0bed366 --- /dev/null +++ b/gas/testsuite/gas/tic54x/macro.s @@ -0,0 +1,40 @@ -+* Macro test -+ .sslist -+ .text -+ .global abc, def, ghi, adr -+ -+* Macro library; load and use a macro in macros.lib -+ .mlib "macros.lib" -+ -+ IN_MLIB abc,def,ghi -+ -+add3 .macro P1,P2,P3,ADDRP -+ ld P1,a -+ add P2,a -+ add P3,a -+ stl a,ADDRP -+ .endm -+ add3 abc, def, ghi, adr -+ -+* Forced substitution within a macro -+force .macro x -+ .asg 0, x -+ .loop 8 -+AUX:x: .set x -+ .eval x+1,x -+ .endloop -+ .endm -+ force -+ -+* Subsripted substitution symbols -+ADDX .macro ABC -+ .var TMP -+ .asg :ABC(1):,TMP -+ .if $symcmp(TMP,"#") == 0 -+ ADD ABC,A -+ .else -+ .emsg "Bad macro parameter 'ABC'" -+ .endif -+ .endm -+ ADDX #100 ; ADD #100,A -+ .end ++* Macro test ++ .sslist ++ .text ++ .global abc, def, ghi, adr ++ ++* Macro library; load and use a macro in macros.lib ++ .mlib "macros.lib" ++ ++ IN_MLIB abc,def,ghi ++ ++add3 .macro P1,P2,P3,ADDRP ++ ld P1,a ++ add P2,a ++ add P3,a ++ stl a,ADDRP ++ .endm ++ add3 abc, def, ghi, adr ++ ++* Forced substitution within a macro ++force .macro x ++ .asg 0, x ++ .loop 8 ++AUX:x: .set x ++ .eval x+1,x ++ .endloop ++ .endm ++ force ++ ++* Subsripted substitution symbols ++ADDX .macro ABC ++ .var TMP ++ .asg :ABC(1):,TMP ++ .if $symcmp(TMP,"#") == 0 ++ ADD ABC,A ++ .else ++ .emsg "Bad macro parameter 'ABC'" ++ .endif ++ .endm ++ ADDX #100 ; ADD #100,A ++ .end diff --git a/gas/testsuite/gas/tic54x/macro1.s b/gas/testsuite/gas/tic54x/macro1.s new file mode 100644 -index 0000000..285fd61 +index 0000000..d92ee54 --- /dev/null +++ b/gas/testsuite/gas/tic54x/macro1.s @@ -0,0 +1,12 @@ -+* Subsripted substitution symbols -+ADDX .macro ABC -+ .var TMP -+ .asg :ABC(1):,TMP -+ .if $symcmp(TMP,"#") == 0 -+ ADD ABC,A -+ .else -+ .emsg "Bad macro parameter 'ABC'" -+ .endif -+ .endm -+ ADDX *AR1 ; should produce an error msg -+ .end ++* Subsripted substitution symbols ++ADDX .macro ABC ++ .var TMP ++ .asg :ABC(1):,TMP ++ .if $symcmp(TMP,"#") == 0 ++ ADD ABC,A ++ .else ++ .emsg "Bad macro parameter 'ABC'" ++ .endif ++ .endm ++ ADDX *AR1 ; should produce an error msg ++ .end diff --git a/gas/testsuite/gas/tic54x/macros.lib b/gas/testsuite/gas/tic54x/macros.lib new file mode 100644 index 0000000..505ca4f @@ -2203490,47 +2213408,47 @@ index 0000000..012a0ad + ... diff --git a/gas/testsuite/gas/tic54x/math.s b/gas/testsuite/gas/tic54x/math.s new file mode 100644 -index 0000000..2e2eac0 +index 0000000..3238e52 --- /dev/null +++ b/gas/testsuite/gas/tic54x/math.s @@ -0,0 +1,37 @@ -+* -+* Math built-in functions -+* -+ .float $acos(0.0) -+ .float $asin(0.0) -+ .float $atan(0.0) -+ .float $atan2(1.0,2.0) -+ .float $ceil(1.5) -+ .float $cosh(0.0) -+ .float $cos(0.0) -+ .float $cvf(1) -+ .int $cvi(2.5) -+ .int $cvi(-2.5) -+ .float $exp(1.0) -+ .float $fabs(-2.5) -+ .float $floor(3.4) -+ .float $fmod(10,4) -+ .int $int(1.2) -+ .float $ldexp(1,2) -+ .float $log10(1.0) -+ .float $log(1.0) -+ .float $max(1.0,2.0) -+ .float $min(1.0,2.0) -+ .float $pow(2.0,3.0) -+ .float $round(4.5) -+ .float $round(-4.5) -+ .int $sgn(-1.0) -+ .int $sgn(0) -+ .int $sgn(1) -+ .float $sin(0.0) -+ .float $sinh(0.0) -+ .float $sqrt(1.0) -+ .float $tan(0.0) -+ .float $tanh(0.0) -+ .float $trunc(-1.5) -+ .float $trunc(1.5) -+ .end ++* ++* Math built-in functions ++* ++ .float $acos(0.0) ++ .float $asin(0.0) ++ .float $atan(0.0) ++ .float $atan2(1.0,2.0) ++ .float $ceil(1.5) ++ .float $cosh(0.0) ++ .float $cos(0.0) ++ .float $cvf(1) ++ .int $cvi(2.5) ++ .int $cvi(-2.5) ++ .float $exp(1.0) ++ .float $fabs(-2.5) ++ .float $floor(3.4) ++ .float $fmod(10,4) ++ .int $int(1.2) ++ .float $ldexp(1,2) ++ .float $log10(1.0) ++ .float $log(1.0) ++ .float $max(1.0,2.0) ++ .float $min(1.0,2.0) ++ .float $pow(2.0,3.0) ++ .float $round(4.5) ++ .float $round(-4.5) ++ .int $sgn(-1.0) ++ .int $sgn(0) ++ .int $sgn(1) ++ .float $sin(0.0) ++ .float $sinh(0.0) ++ .float $sqrt(1.0) ++ .float $tan(0.0) ++ .float $tanh(0.0) ++ .float $trunc(-1.5) ++ .float $trunc(1.5) ++ .end diff --git a/gas/testsuite/gas/tic54x/opcodes.d b/gas/testsuite/gas/tic54x/opcodes.d new file mode 100644 index 0000000..2dab821 @@ -2203831,319 +2213749,319 @@ index 0000000..2dab821 + 11b: 0001 diff --git a/gas/testsuite/gas/tic54x/opcodes.s b/gas/testsuite/gas/tic54x/opcodes.s new file mode 100644 -index 0000000..6cef583 +index 0000000..3e1e84b --- /dev/null +++ b/gas/testsuite/gas/tic54x/opcodes.s @@ -0,0 +1,309 @@ -+ ;; opcodes tests -+ .text -+ .mmregs -+ .global X, Y, Z -+ .global _opcodes, _opcodes_end -+ .label _opcodes_load -+_opcodes: -+ abdst *ar3+, *ar4+ -+ abs a -+ abs a,b -+ add *ar0+, a ; Smem, src -+ add *ar1+, ts, a ; Smem, TS, src -+ add *ar2+, 16, a ; Smem, 16, src [,dst] -+ add *ar3+, a, b ; Smem [,SHIFT], src [,dst] (-16<=SHIFT<=15) -+ -+ add *ar4+, 1, a ; Xmem, SHFT, src (0<=SHFT<=15) -+ add *ar3+, *ar4+, a ; Xmem, Ymem, dst -+ add #-32768, a ; #lk [,SHFT], src [,dst] (-32768<=lk<=32767) -+ -+ add #0,16,a,b ; #lk, 16, src, [,dst] -+ -+ add a,-16,b ; src [,SHIFT][,dst] -+ add a,asm,b ; src, ASM [,dst] -+ addc *ar0+,a -+ addm #1,*ar1+ -+ -+ adds *ar2+,a -+ and *ar3+,a ; Smem,src -+ and #1,1,a,b ; #lk[,SHFT],src[,dst] -+ -+ and #1,#16,a,b ; #lk,16,src[,dst] -+ -+ and a ; src[,SHIFT][,dst] -+ andm #1,*ar0+ -+ -+ b _opcodes_end -+ -+ bd #_opcodes_end -+ nop -+ nop -+ -+ bacc a -+ baccd b -+ nop -+ nop -+ -+ banz _opcodes_end,*ar1+ -+ -+ banzd _opcodes_end,*ar2+ -+ nop -+ nop -+ -+ bc _opcodes_end, AEQ,AOV -+ -+ bcd _opcodes_end, BIO,C,TC -+ nop -+ nop -+ -+ bit *ar3+,1 -+ bitf *ar4+,#-1 -+ -+ bitt *ar5+ -+ cala a -+ calad b -+ nop -+ nop -+ -+ call _opcodes_end -+ -+ calld _opcodes_end -+ nop -+ nop -+ -+ cc _opcodes_end, tc -+ -+ ccd _opcodes_end, aeq -+ nop -+ nop -+ -+ cmpl b,a -+ cmpm *ar0+,#1 -+ -+ cmpr 1,ar1 -+ cmps a,*ar2+ -+ dadd *ar3-, a, b -+ dadst *ar4-, a -+ delay *ar5+ -+ dld *ar6-, a -+ drsub *ar7-, b -+ dsadt *ar0-, a -+ dst a, *ar1- -+ dsub *ar2-, b -+ dsubt *ar3-, a -+ exp a -+ firs *ar3+,*ar4+,_opcodes_end -+ -+ frame -128 -+ idle 2 -+ intr 15 -+ ld *ar0+,a ; Smem,dst -+ ld *ar1+,ts,a ; Smem,TS,dst -+ ld *ar2+,16,a ; Smem,16,dst -+ ld *ar3+,1,a ; Smem[,SHIFT],dst -+ -+ ld *ar4+,1,a ; Xmem,SHFT,dst -+ ld #1,b ; #K,dst -+ ld #32767,1,a ; #lk,[,SHFT],dst -+ -+ ld #32767,16,a ; #lk,16,dst -+ -+ ld a,asm,b ; src,ASM[,dst] -+ ld a,1,b ; src[,SHIFT],dst -+ ld *ar0+,t -+ ld *ar1+,dp -+ ld #_opcodes_end,dp ; FIXME try to print label on disasm -+ ; note: TI assembler doesn't shift -+ ; the address encoding. -+ ld #15,asm -+ ld #7,arp -+ ld *ar2+,asm -+ ldm ar3,a -+ ld *ar2+,a || mac *ar3+,b ; single-line parallell -+ ld *ar4+,b || macr *ar5+,a ; with optional DST_ specified -+ ld *ar2+,a ; double-line parallel -+ || mas *ar3+ -+ ld *ar4+,b ; parallel spans -+ ; inserted line -+ || masr *ar5+ -+ ldr *ar6+,a -+ ldu *ar7+,a -+ lms *ar3+,*ar4+ -+ ltd *ar0+ -+ mac *ar1+,a -+ macr *ar2+,a -+ mac *ar2+,*ar3+,a,b -+ macr *ar4+,*ar5+,a,b -+ mac #1,a,b -+ -+ mac *ar0+,#1,a -+ -+ maca *ar1+ ; *ar6+,b (valid) -+ maca t,a,b -+ macd *ar2+,_opcodes_end,a -+ -+ macp *ar3+,_opcodes_end,a -+ -+ macsu *ar4+,*ar5+,a -+ mar *ar6+ -+ mas *ar7+,a -+ masr *ar0+,a -+ mas *ar3+,*ar4+,a,b -+ masr *ar2+,*ar5+,a,b -+ masa *ar6+ ; *ar6+,b (valid) -+ masa t,a,b -+ masar t,a -+ max a -+ min b -+ mpy *ar7+,a -+ mpy *ar3+,*ar4+,b -+ mpy *ar0,#1,a -+ -+ mpy #1,a -+ -+ mpya *ar0+ -+ mpya b -+ mpyu *ar1+,b -+ mvdd *ar2+,*ar3+ -+ mvdk *ar4+,X -+ -+ mvdm X,ar5 -+ -+ mvdp *ar6+,_opcodes_end -+ -+ mvkd X,*ar7+ -+ -+ mvmd ar0,X -+ -+ mvmm ar1,ar2 -+ mvpd _opcodes_end,*ar3+ -+ -+ neg a,b -+ -+ nop -+ norm a -+ or *ar0+,b -+ or #(3+4),b -+ -+ or #1,16,b -+ -+ or b -+ orm #1,*ar1+ -+ -+ poly *ar2+ -+ popd *ar3+ -+ popm ar4 -+ portr 0,*ar5+ -+ -+ portw *ar6+,0 -+ -+ pshd *ar7+ -+ pshm ar0 -+ rc ANEQ -+ rcd AGT -+ reada *ar1+ -+ reset -+ ret -+ retd -+ nop -+ nop -+ rete -+ reted -+ nop -+ nop -+ retf -+ retfd -+ rol a -+ roltc a -+ ror b -+ rpt *ar0+ -+ nop -+ rpt #32 -+ nop -+ rpt #65535 -+ nop -+ rptb _opcodes_end-1 -+ nop -+ rptbd _opcodes_end-1 -+ nop -+ nop -+ rptz a,#32767 -+ nop -+ rsbx 1,15 -+ saccd a,*ar3+,ALT -+ sat a -+ sfta a,15,b -+ sftc a -+ sftl a,15 -+ sqdst *ar2+,*ar3+ -+ squr *ar4+,b -+ squr a,a -+ squra *ar5+,a -+ squrs *ar6+,a -+ srccd *ar2+,ALEQ -+ ssbx 1,15 -+ st t,*ar0+ -+ st trn,*ar1+ -+ st #32767,*ar2+ -+ -+ sth a,*ar3+ -+ sth a,asm,*ar4+ -+ sth a,15,*ar5+ -+ sth a,-16,*ar6+ -+ -+ stl a,*ar7+ -+ stl a,asm,*ar0+ -+ stl a,15,*ar1+ -+ stl a,15,*ar2+ -+ -+ stlm a,ar3 -+ stm #32767,ar4 -+ -+ st a,*ar5+ -+ || add *ar4+,b -+ st a,*ar3+ -+ || ld *ar2+,b -+ st a,*ar3+ -+ || ld *ar4+,t -+ st a,*ar5+ -+ || mac *ar2+,b -+ st a,*ar3+ -+ || masr *ar4+,b -+ st a,*ar3+ -+ || mpy *ar4+,b -+ st a,*ar3+ -+ || sub *ar4+,b -+ strcd *ar5+,BEQ -+ sub *ar0+,a -+ sub *ar1+,ts,a -+ sub *ar2+,16,a,b -+ sub *ar3+,a,b -+ -+ sub *ar4+,15,a -+ sub *ar5+,*ar4+,b -+ sub #1,15,a,b -+ -+ sub #1,16,a,b -+ -+ sub a,-16,b -+ sub a,asm,b -+ subb *ar0+,a -+ subc *ar1+,a -+ subs *ar2+,a -+ trap 15 -+ writa *ar3+ -+ xc 1,AOV -+ xor *ar4+,a -+ xor #1,a -+ -+ xor #1,16,a -+ -+ xor a,1,b -+ xorm #1,*ar5+ -+_opcodes_end: -+ .data -+X: .word 0 -+Y: .word 1 -+* .word Z -+ .end -+ ++ ;; opcodes tests ++ .text ++ .mmregs ++ .global X, Y, Z ++ .global _opcodes, _opcodes_end ++ .label _opcodes_load ++_opcodes: ++ abdst *ar3+, *ar4+ ++ abs a ++ abs a,b ++ add *ar0+, a ; Smem, src ++ add *ar1+, ts, a ; Smem, TS, src ++ add *ar2+, 16, a ; Smem, 16, src [,dst] ++ add *ar3+, a, b ; Smem [,SHIFT], src [,dst] (-16<=SHIFT<=15) ++ ++ add *ar4+, 1, a ; Xmem, SHFT, src (0<=SHFT<=15) ++ add *ar3+, *ar4+, a ; Xmem, Ymem, dst ++ add #-32768, a ; #lk [,SHFT], src [,dst] (-32768<=lk<=32767) ++ ++ add #0,16,a,b ; #lk, 16, src, [,dst] ++ ++ add a,-16,b ; src [,SHIFT][,dst] ++ add a,asm,b ; src, ASM [,dst] ++ addc *ar0+,a ++ addm #1,*ar1+ ++ ++ adds *ar2+,a ++ and *ar3+,a ; Smem,src ++ and #1,1,a,b ; #lk[,SHFT],src[,dst] ++ ++ and #1,#16,a,b ; #lk,16,src[,dst] ++ ++ and a ; src[,SHIFT][,dst] ++ andm #1,*ar0+ ++ ++ b _opcodes_end ++ ++ bd #_opcodes_end ++ nop ++ nop ++ ++ bacc a ++ baccd b ++ nop ++ nop ++ ++ banz _opcodes_end,*ar1+ ++ ++ banzd _opcodes_end,*ar2+ ++ nop ++ nop ++ ++ bc _opcodes_end, AEQ,AOV ++ ++ bcd _opcodes_end, BIO,C,TC ++ nop ++ nop ++ ++ bit *ar3+,1 ++ bitf *ar4+,#-1 ++ ++ bitt *ar5+ ++ cala a ++ calad b ++ nop ++ nop ++ ++ call _opcodes_end ++ ++ calld _opcodes_end ++ nop ++ nop ++ ++ cc _opcodes_end, tc ++ ++ ccd _opcodes_end, aeq ++ nop ++ nop ++ ++ cmpl b,a ++ cmpm *ar0+,#1 ++ ++ cmpr 1,ar1 ++ cmps a,*ar2+ ++ dadd *ar3-, a, b ++ dadst *ar4-, a ++ delay *ar5+ ++ dld *ar6-, a ++ drsub *ar7-, b ++ dsadt *ar0-, a ++ dst a, *ar1- ++ dsub *ar2-, b ++ dsubt *ar3-, a ++ exp a ++ firs *ar3+,*ar4+,_opcodes_end ++ ++ frame -128 ++ idle 2 ++ intr 15 ++ ld *ar0+,a ; Smem,dst ++ ld *ar1+,ts,a ; Smem,TS,dst ++ ld *ar2+,16,a ; Smem,16,dst ++ ld *ar3+,1,a ; Smem[,SHIFT],dst ++ ++ ld *ar4+,1,a ; Xmem,SHFT,dst ++ ld #1,b ; #K,dst ++ ld #32767,1,a ; #lk,[,SHFT],dst ++ ++ ld #32767,16,a ; #lk,16,dst ++ ++ ld a,asm,b ; src,ASM[,dst] ++ ld a,1,b ; src[,SHIFT],dst ++ ld *ar0+,t ++ ld *ar1+,dp ++ ld #_opcodes_end,dp ; FIXME try to print label on disasm ++ ; note: TI assembler doesn't shift ++ ; the address encoding. ++ ld #15,asm ++ ld #7,arp ++ ld *ar2+,asm ++ ldm ar3,a ++ ld *ar2+,a || mac *ar3+,b ; single-line parallell ++ ld *ar4+,b || macr *ar5+,a ; with optional DST_ specified ++ ld *ar2+,a ; double-line parallel ++ || mas *ar3+ ++ ld *ar4+,b ; parallel spans ++ ; inserted line ++ || masr *ar5+ ++ ldr *ar6+,a ++ ldu *ar7+,a ++ lms *ar3+,*ar4+ ++ ltd *ar0+ ++ mac *ar1+,a ++ macr *ar2+,a ++ mac *ar2+,*ar3+,a,b ++ macr *ar4+,*ar5+,a,b ++ mac #1,a,b ++ ++ mac *ar0+,#1,a ++ ++ maca *ar1+ ; *ar6+,b (valid) ++ maca t,a,b ++ macd *ar2+,_opcodes_end,a ++ ++ macp *ar3+,_opcodes_end,a ++ ++ macsu *ar4+,*ar5+,a ++ mar *ar6+ ++ mas *ar7+,a ++ masr *ar0+,a ++ mas *ar3+,*ar4+,a,b ++ masr *ar2+,*ar5+,a,b ++ masa *ar6+ ; *ar6+,b (valid) ++ masa t,a,b ++ masar t,a ++ max a ++ min b ++ mpy *ar7+,a ++ mpy *ar3+,*ar4+,b ++ mpy *ar0,#1,a ++ ++ mpy #1,a ++ ++ mpya *ar0+ ++ mpya b ++ mpyu *ar1+,b ++ mvdd *ar2+,*ar3+ ++ mvdk *ar4+,X ++ ++ mvdm X,ar5 ++ ++ mvdp *ar6+,_opcodes_end ++ ++ mvkd X,*ar7+ ++ ++ mvmd ar0,X ++ ++ mvmm ar1,ar2 ++ mvpd _opcodes_end,*ar3+ ++ ++ neg a,b ++ ++ nop ++ norm a ++ or *ar0+,b ++ or #(3+4),b ++ ++ or #1,16,b ++ ++ or b ++ orm #1,*ar1+ ++ ++ poly *ar2+ ++ popd *ar3+ ++ popm ar4 ++ portr 0,*ar5+ ++ ++ portw *ar6+,0 ++ ++ pshd *ar7+ ++ pshm ar0 ++ rc ANEQ ++ rcd AGT ++ reada *ar1+ ++ reset ++ ret ++ retd ++ nop ++ nop ++ rete ++ reted ++ nop ++ nop ++ retf ++ retfd ++ rol a ++ roltc a ++ ror b ++ rpt *ar0+ ++ nop ++ rpt #32 ++ nop ++ rpt #65535 ++ nop ++ rptb _opcodes_end-1 ++ nop ++ rptbd _opcodes_end-1 ++ nop ++ nop ++ rptz a,#32767 ++ nop ++ rsbx 1,15 ++ saccd a,*ar3+,ALT ++ sat a ++ sfta a,15,b ++ sftc a ++ sftl a,15 ++ sqdst *ar2+,*ar3+ ++ squr *ar4+,b ++ squr a,a ++ squra *ar5+,a ++ squrs *ar6+,a ++ srccd *ar2+,ALEQ ++ ssbx 1,15 ++ st t,*ar0+ ++ st trn,*ar1+ ++ st #32767,*ar2+ ++ ++ sth a,*ar3+ ++ sth a,asm,*ar4+ ++ sth a,15,*ar5+ ++ sth a,-16,*ar6+ ++ ++ stl a,*ar7+ ++ stl a,asm,*ar0+ ++ stl a,15,*ar1+ ++ stl a,15,*ar2+ ++ ++ stlm a,ar3 ++ stm #32767,ar4 ++ ++ st a,*ar5+ ++ || add *ar4+,b ++ st a,*ar3+ ++ || ld *ar2+,b ++ st a,*ar3+ ++ || ld *ar4+,t ++ st a,*ar5+ ++ || mac *ar2+,b ++ st a,*ar3+ ++ || masr *ar4+,b ++ st a,*ar3+ ++ || mpy *ar4+,b ++ st a,*ar3+ ++ || sub *ar4+,b ++ strcd *ar5+,BEQ ++ sub *ar0+,a ++ sub *ar1+,ts,a ++ sub *ar2+,16,a,b ++ sub *ar3+,a,b ++ ++ sub *ar4+,15,a ++ sub *ar5+,*ar4+,b ++ sub #1,15,a,b ++ ++ sub #1,16,a,b ++ ++ sub a,-16,b ++ sub a,asm,b ++ subb *ar0+,a ++ subc *ar1+,a ++ subs *ar2+,a ++ trap 15 ++ writa *ar3+ ++ xc 1,AOV ++ xor *ar4+,a ++ xor #1,a ++ ++ xor #1,16,a ++ ++ xor a,1,b ++ xorm #1,*ar5+ ++_opcodes_end: ++ .data ++X: .word 0 ++Y: .word 1 ++* .word Z ++ .end ++ diff --git a/gas/testsuite/gas/tic54x/sections.d b/gas/testsuite/gas/tic54x/sections.d new file mode 100644 index 0000000..d1e04b6 @@ -2204464,89 +2214382,88 @@ index 0000000..46bcb27 + ... diff --git a/gas/testsuite/gas/tic54x/subsym.s b/gas/testsuite/gas/tic54x/subsym.s new file mode 100644 -index 0000000..340a192 +index 0000000..aeded97 --- /dev/null +++ b/gas/testsuite/gas/tic54x/subsym.s @@ -0,0 +1,55 @@ -+* -+* String substitution symbols -+* -+ ; if no quotes, interpret as subsymbol -+ ; if quotes, interpret as string, and do forced substitution -+ .sslist -+ .asg value,SYMBOL -+ .asg SYMBOL,SYMBOL1 -+ -+ .global label, x -+ .word x -+ -+* Substitution symbol functions -+label: .word $symlen(SYMBOL) ; 5, substitutes string for symbol -+ .word $symlen(":SYMBOL:") ; 5, forced substitution -+ .word $symlen("SYMBOL") ; 6, uses string directly -+ -+ .word $symcmp(SYMBOL,"value") ; 0 -+ -+ ; requires 2nd arg to be a character; zero if not found -+ .word $firstch(":SYMBOL:",'a') ; 2 -+ .word $lastch(SYMBOL,'a') ; 2 -+ -+ .word $isdefed(SYMBOL) ; 0 (value not in symtab) -+ .word $isdefed("label") ; 1 (string contents in symtab) -+ .word $isdefed("unknown") ; 0 -+ -+ .asg "1,2,3", list -+ ; both args must be identifiers -+ .word $ismember(SYMBOL,list) ; 1 -+ .word SYMBOL ; now 1 -+ .word list ; now 2,3 -+ -+ .word $iscons("010b") ; 1 -+ .word $iscons("11111111B") ; 1 -+ .word $iscons("011") ; 2 (5 -- TI bug) -+ .word $iscons("0x10") ; 3 (0 -- TI bug) -+ .word $iscons("'a'") ; 4 -+ .word $iscons(SYMBOL) ; 5 ("1") -+ .word $iscons("SYMBOL") ; 0 -+ -+ .word $isname(SYMBOL) ; 0 -+ -+ .word $isreg(SYMBOL) ; 0 -+ .word $isreg("AR0") ; -+; .word $isreg("AG") ; should be 0, but we always -+ ; use mmregs -+ .mmregs -+x .word $isreg("AG") ; 1 if .mmregs, 0 otherwise -+tag .struct 10 -+ .word 1 -+ .endstruct -+ .word $structsz(tag) -+ .word $structacc(tag) ; this op is unspecified -+ .end ++* ++* String substitution symbols ++* ++ ; if no quotes, interpret as subsymbol ++ ; if quotes, interpret as string, and do forced substitution ++ .sslist ++ .asg value,SYMBOL ++ .asg SYMBOL,SYMBOL1 ++ ++ .global label, x ++ .word x ++ ++* Substitution symbol functions ++label: .word $symlen(SYMBOL) ; 5, substitutes string for symbol ++ .word $symlen(":SYMBOL:") ; 5, forced substitution ++ .word $symlen("SYMBOL") ; 6, uses string directly ++ ++ .word $symcmp(SYMBOL,"value") ; 0 ++ ++ ; requires 2nd arg to be a character; zero if not found ++ .word $firstch(":SYMBOL:",'a') ; 2 ++ .word $lastch(SYMBOL,'a') ; 2 ++ ++ .word $isdefed(SYMBOL) ; 0 (value not in symtab) ++ .word $isdefed("label") ; 1 (string contents in symtab) ++ .word $isdefed("unknown") ; 0 ++ ++ .asg "1,2,3", list ++ ; both args must be identifiers ++ .word $ismember(SYMBOL,list) ; 1 ++ .word SYMBOL ; now 1 ++ .word list ; now 2,3 ++ ++ .word $iscons("010b") ; 1 ++ .word $iscons("11111111B") ; 1 ++ .word $iscons("011") ; 2 (5 -- TI bug) ++ .word $iscons("0x10") ; 3 (0 -- TI bug) ++ .word $iscons("'a'") ; 4 ++ .word $iscons(SYMBOL) ; 5 ("1") ++ .word $iscons("SYMBOL") ; 0 ++ ++ .word $isname(SYMBOL) ; 0 ++ ++ .word $isreg(SYMBOL) ; 0 ++ .word $isreg("AR0") ; ++; .word $isreg("AG") ; should be 0, but we always ++ ; use mmregs ++ .mmregs ++x .word $isreg("AG") ; 1 if .mmregs, 0 otherwise ++tag .struct 10 ++ .word 1 ++ .endstruct ++ .word $structsz(tag) ++ .word $structacc(tag) ; this op is unspecified ++ .end diff --git a/gas/testsuite/gas/tic54x/subsym1.s b/gas/testsuite/gas/tic54x/subsym1.s new file mode 100644 -index 0000000..ad6ef62 +index 0000000..3682a0e --- /dev/null +++ b/gas/testsuite/gas/tic54x/subsym1.s @@ -0,0 +1,10 @@ -+* -+* String substitution symbol recursion -+* -+* Recursive substitution symbols -+ ; recursion should stop at x -+ .asg "x",z -+ .asg "z",y -+ .asg "y",x -+ add x, A ; add x, A -+ .end ++* ++* String substitution symbol recursion ++* ++* Recursive substitution symbols ++ ; recursion should stop at x ++ .asg "x",z ++ .asg "z",y ++ .asg "y",x ++ add x, A ; add x, A ++ .end diff --git a/gas/testsuite/gas/tic54x/tic54x.exp b/gas/testsuite/gas/tic54x/tic54x.exp new file mode 100644 -index 0000000..359c9d2 +index 0000000..aca18d5 --- /dev/null +++ b/gas/testsuite/gas/tic54x/tic54x.exp -@@ -0,0 +1,47 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,46 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -2218575,12 +2228492,11 @@ index 0000000..2f0bcb3 +add .S1 0xffffffff,a4,a11 diff --git a/gas/testsuite/gas/tic6x/tic6x.exp b/gas/testsuite/gas/tic6x/tic6x.exp new file mode 100644 -index 0000000..5181d5f +index 0000000..29e23df --- /dev/null +++ b/gas/testsuite/gas/tic6x/tic6x.exp -@@ -0,0 +1,20 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,19 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -2240462,12 +2250378,12 @@ index 0000000..c756049 + { xori r5, r6, 5 ; v4int_h r15, r16, r17 } diff --git a/gas/testsuite/gas/tilegx/tilegx.exp b/gas/testsuite/gas/tilegx/tilegx.exp new file mode 100644 -index 0000000..1bf6b4e +index 0000000..d8332fd --- /dev/null +++ b/gas/testsuite/gas/tilegx/tilegx.exp @@ -0,0 +1,23 @@ +# Expect script for TILE-Gx assembler tests. -+# Copyright 2011 Free Software Foundation, Inc. ++# Copyright (C) 2011-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2257795,12 +2267711,12 @@ index 0000000..97bec32 + { xori r5, r6, 5 ; srab r15, r16, r17 } diff --git a/gas/testsuite/gas/tilepro/tilepro.exp b/gas/testsuite/gas/tilepro/tilepro.exp new file mode 100644 -index 0000000..f07e3fd +index 0000000..480b33a --- /dev/null +++ b/gas/testsuite/gas/tilepro/tilepro.exp @@ -0,0 +1,24 @@ +# Expect script for TILEPro assembler tests. -+# Copyright 2011 Free Software Foundation, Inc. ++# Copyright (C) 2011-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2257855,12 +2267771,11 @@ index 0000000..e72140f + subr r5,r6 diff --git a/gas/testsuite/gas/v850/basic.exp b/gas/testsuite/gas/v850/basic.exp new file mode 100644 -index 0000000..cf6aaa3 +index 0000000..0fbeaaa --- /dev/null +++ b/gas/testsuite/gas/v850/basic.exp -@@ -0,0 +1,441 @@ -+# Copyright (C) 1996, 2002, 2003, 2004, 2005, 2007, 2013 -+# Free Software Foundation, Inc. +@@ -0,0 +1,440 @@ ++# Copyright (C) 1996-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -2258792,12 +2268707,11 @@ index 0000000..619685c + .p2align 2 diff --git a/gas/testsuite/gas/vax/vax.exp b/gas/testsuite/gas/vax/vax.exp new file mode 100644 -index 0000000..2037ef9 +index 0000000..4ad7e3b --- /dev/null +++ b/gas/testsuite/gas/vax/vax.exp -@@ -0,0 +1,54 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,53 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -2259942,12 +2269856,11 @@ index 0000000..f8dc87b + trap #0x02 diff --git a/gas/testsuite/gas/xc16x/xc16x.exp b/gas/testsuite/gas/xc16x/xc16x.exp new file mode 100644 -index 0000000..a71ef7f +index 0000000..4e757c5 --- /dev/null +++ b/gas/testsuite/gas/xc16x/xc16x.exp -@@ -0,0 +1,1334 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,1333 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -2261894,12 +2271807,11 @@ index 0000000..e359e68 +block_end: diff --git a/gas/testsuite/gas/xgate/xgate.exp b/gas/testsuite/gas/xgate/xgate.exp new file mode 100644 -index 0000000..3b6f69c +index 0000000..21b68a0 --- /dev/null +++ b/gas/testsuite/gas/xgate/xgate.exp -@@ -0,0 +1,37 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,36 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -2263285,12 +2273197,11 @@ index 0000000..7ede588 + a8e: R_XSTORMY16_12 extsym-0x39f diff --git a/gas/testsuite/gas/xstormy16/allinsn.exp b/gas/testsuite/gas/xstormy16/allinsn.exp new file mode 100644 -index 0000000..105ed73 +index 0000000..e05ec9c --- /dev/null +++ b/gas/testsuite/gas/xstormy16/allinsn.exp -@@ -0,0 +1,25 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,24 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -2266482,12 +2276393,11 @@ index 0000000..6fae78a + jmpf global diff --git a/gas/testsuite/gas/xtensa/all.exp b/gas/testsuite/gas/xtensa/all.exp new file mode 100644 -index 0000000..4cfd5b3 +index 0000000..b1e6c82 --- /dev/null +++ b/gas/testsuite/gas/xtensa/all.exp -@@ -0,0 +1,106 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,107 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -2266587,6 +2276497,8 @@ index 0000000..4cfd5b3 + run_dump_test "pcrel" + run_dump_test "weak-call" + run_dump_test "jlong" ++ run_dump_test "trampoline" ++ run_dump_test "first_frag_align" +} + +if [info exists errorInfo] then { @@ -2266636,6 +2276548,32 @@ index 0000000..5b32538 + beqz a2, 1f@pcrel # { dg-error "relocation not allowed" "" } +1: movi a2, foo@pcrel # { dg-error "relocation not allowed" "" } +foo: .short foo@pcrel # { dg-error "relocations do not fit" "" } +diff --git a/gas/testsuite/gas/xtensa/first_frag_align.d b/gas/testsuite/gas/xtensa/first_frag_align.d +new file mode 100644 +index 0000000..aafcb41 +--- /dev/null ++++ b/gas/testsuite/gas/xtensa/first_frag_align.d +@@ -0,0 +1,9 @@ ++#as: ++#objdump: -s ++#name: record alignment for the first section frag ++ ++.*: +file format .*xtensa.* ++#... ++Contents of section .xt.prop: ++ 0000 00000000 00000000 00002804 .* ++#... +diff --git a/gas/testsuite/gas/xtensa/first_frag_align.s b/gas/testsuite/gas/xtensa/first_frag_align.s +new file mode 100644 +index 0000000..c120af0 +--- /dev/null ++++ b/gas/testsuite/gas/xtensa/first_frag_align.s +@@ -0,0 +1,5 @@ ++ .text ++ .align 4 ++f1: ++ entry a1, 32 ++ retw diff --git a/gas/testsuite/gas/xtensa/j_too_far.s b/gas/testsuite/gas/xtensa/j_too_far.s new file mode 100644 index 0000000..3348d85 @@ -2266819,6 +2276757,65 @@ index 0000000..df2489f + _nop + _nop +.Lplus68: +diff --git a/gas/testsuite/gas/xtensa/trampoline.d b/gas/testsuite/gas/xtensa/trampoline.d +new file mode 100644 +index 0000000..b4f65dc +--- /dev/null ++++ b/gas/testsuite/gas/xtensa/trampoline.d +@@ -0,0 +1,26 @@ ++#as: ++#objdump: -d ++#name: trampolines relaxation ++ ++.*: +file format .*xtensa.* ++#... ++.*0:.*j.0x1194c ++.*3:.*j.0x1194f ++.*6:.*j.0x11952 ++.*9:.*j.0x1d4e4 ++#... ++.*11949:.*j.0x11955 ++.*1194c:.*j.0x24a0e ++.*1194f:.*j.0x24a0e ++.*11952:.*j.0x24a11 ++#... ++.*1d4e1:.*j.0x1d4e7 ++.*1d4e4:.*j.0x33462 ++#... ++.*24a0e:.*j.0x24a0e ++.*24a11:.*j.0x24a11 ++#... ++.*3345f:.*ret ++.*33462:.*j.0x49407 ++#... ++.*49407:.*j.0x49407 +diff --git a/gas/testsuite/gas/xtensa/trampoline.s b/gas/testsuite/gas/xtensa/trampoline.s +new file mode 100644 +index 0000000..259a3bb +--- /dev/null ++++ b/gas/testsuite/gas/xtensa/trampoline.s +@@ -0,0 +1,21 @@ ++ .text ++ j 1f ++ j 1f ++ j 2f ++ j 3f ++ .rep 25000 ++99: ++ and a2, a2, a3 ++ bne a2, a3, 99b ++ .endr ++1: ++ j 1b ++2: ++ j 2b ++ ++ .rep 25000 ++ and a2, a2, a3 ++ _ret ++ .endr ++3: ++ j 3b diff --git a/gas/testsuite/gas/xtensa/weak-call.d b/gas/testsuite/gas/xtensa/weak-call.d new file mode 100644 index 0000000..0b8d84b @@ -2266852,11 +2276849,11 @@ index 0000000..d6800c5 + .end no-longcalls diff --git a/gas/testsuite/gas/xtensa/xtensa-err.exp b/gas/testsuite/gas/xtensa/xtensa-err.exp new file mode 100644 -index 0000000..60ffd36 +index 0000000..d6200e1 --- /dev/null +++ b/gas/testsuite/gas/xtensa/xtensa-err.exp @@ -0,0 +1,30 @@ -+# Copyright (C) 2001, 2007 Free Software Foundation, Inc. ++# Copyright (C) 2001-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -2268823,12 +2278820,11 @@ index 0000000..5cf298b +1010: diff --git a/gas/testsuite/gas/z80/z80.exp b/gas/testsuite/gas/z80/z80.exp new file mode 100644 -index 0000000..dc57c8c +index 0000000..71e186f --- /dev/null +++ b/gas/testsuite/gas/z80/z80.exp -@@ -0,0 +1,54 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,53 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -2271169,12 +2281165,11 @@ index 0000000..3f31260 + .end diff --git a/gas/testsuite/gas/z8k/z8k.exp b/gas/testsuite/gas/z8k/z8k.exp new file mode 100644 -index 0000000..42d91c0 +index 0000000..bc6c81b --- /dev/null +++ b/gas/testsuite/gas/z8k/z8k.exp -@@ -0,0 +1,72 @@ -+# Copyright 2012 -+# Free Software Foundation, Inc. +@@ -0,0 +1,71 @@ ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -2271463,12 +2281458,11 @@ index 0000000..a44da62 +#eof diff --git a/gas/testsuite/lib/gas-defs.exp b/gas/testsuite/lib/gas-defs.exp new file mode 100644 -index 0000000..cb81c18 +index 0000000..9e405f4 --- /dev/null +++ b/gas/testsuite/lib/gas-defs.exp -@@ -0,0 +1,922 @@ -+# Copyright (C) 1993, 1994, 1997, 1998, 1999, 2000, 2001, 2002, 2003, -+# 2004, 2005, 2007, 2008, 2009, 2010, 2012 Free Software Foundation, Inc. +@@ -0,0 +1,921 @@ ++# Copyright (C) 1993-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -2272391,13 +2282385,12 @@ index 0000000..cb81c18 +} diff --git a/gas/testsuite/lib/gas-dg.exp b/gas/testsuite/lib/gas-dg.exp new file mode 100644 -index 0000000..635e06f +index 0000000..1ac6c4f --- /dev/null +++ b/gas/testsuite/lib/gas-dg.exp -@@ -0,0 +1,70 @@ +@@ -0,0 +1,69 @@ +# Define gas callbacks for dg.exp. -+# Copyright 2012 -+# Free Software Foundation, Inc. ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -2272467,14 +2282460,12 @@ index 0000000..635e06f +} diff --git a/gas/write.c b/gas/write.c new file mode 100644 -index 0000000..745abe6 +index 0000000..4ab275d --- /dev/null +++ b/gas/write.c -@@ -0,0 +1,2868 @@ +@@ -0,0 +1,2866 @@ +/* write.c - emit .o file -+ Copyright 1986, 1987, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, -+ 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, -+ 2010, 2011, 2012 Free Software Foundation, Inc. ++ Copyright (C) 1986-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -2274358,7 +2284349,7 @@ index 0000000..745abe6 +#ifdef TC_CONS_FIX_NEW + TC_CONS_FIX_NEW (lie->frag, + lie->word_goes_here - lie->frag->fr_literal, -+ 2, &exp); ++ 2, &exp, TC_PARSE_CONS_RETURN_NONE); +#else + fix_new_exp (lie->frag, + lie->word_goes_here - lie->frag->fr_literal, @@ -2275341,14 +2285332,12 @@ index 0000000..745abe6 +} diff --git a/gas/write.h b/gas/write.h new file mode 100644 -index 0000000..36de533 +index 0000000..c9b3da0 --- /dev/null +++ b/gas/write.h -@@ -0,0 +1,191 @@ +@@ -0,0 +1,189 @@ +/* write.h -+ Copyright 1987, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2000, 2001, -+ 2002, 2003, 2005, 2006, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1987-2014 Free Software Foundation, Inc. + + This file is part of GAS, the GNU Assembler. + @@ -2275537,86 +2285526,709 @@ index 0000000..36de533 + +#endif /* __write_h__ */ diff --git a/gdb/ChangeLog b/gdb/ChangeLog -index 1e0964c..f21fbd6 100644 +index 8fc70c0..4cde71a 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog -@@ -1,3 +1,14 @@ -+2014-04-11 Pierre Langlois -+ -+ PR backtrace/16721 -+ PR backtrace/16832 -+ * avr-tdep.c (struct gdbarch_tdep): Mention avrxmega in the comment. -+ (avr_gdbarch_init): Add xmega architectures given by bfd_architecture -+ when setting the size of call_length. -+ (avr_scan_prologue): Accept push r1 instruction for small stack -+ allocation. -+ * MAINTAINERS (Write After Approval): Add "Pierre Langlois". -+ - 2014-02-06 Joel Brobecker +@@ -99,6 +99,12 @@ + * config.in: Regenerate. + * guile/guile.c (_initialize_guile): Add workaround for libgc 7.4.0. - * version.in: Set GDB version number to 7.7. -diff --git a/gdb/MAINTAINERS b/gdb/MAINTAINERS -index ffd310b..c0297c1 100644 ---- a/gdb/MAINTAINERS -+++ b/gdb/MAINTAINERS -@@ -546,6 +546,7 @@ Jim Kingdon kingdon@panix.com - Paul Koning paul_koning@dell.com - Jan Kratochvil jan.kratochvil@redhat.com - Maxim Kuvyrkov maxim@kugelworks.com -+Pierre Langlois pierre.langlois@embecosm.com - Jonathan Larmour jifl@ecoscentric.com - Jeff Law law@redhat.com - Justin Lebar justin.lebar@gmail.com ++2014-07-25 Pierre Langlois ++ ++ * avr-tdep.c (avr_address_to_pointer): Clarify the conversion in the ++ comments. ++ (avr_pointer_to_address): Likewise. ++ + 2014-07-24 Pedro Alves + + * tui/tui-io.c (tui_prep_terminal): Handle NULL rl_prompt. +@@ -139,6 +145,20 @@ + recorded enabled flag. + (make_command_stats_cleanup): Handle msg_type == 0, startup. + ++ ++2014-07-15 Pierre Langlois ++ ++ * avr-tdep.c (AVR_TYPE_ADDRESS_CLASS_FLASH): New macro. ++ (AVR_TYPE_INSTANCE_FLAG_ADDRESS_CLASS_FLASH): Likewise. ++ (avr_address_to_pointer): Check for AVR_TYPE_ADDRESS_CLASS_FLASH. ++ (avr_pointer_to_address): Likewise. ++ (avr_address_class_type_flags): New function. ++ (avr_address_class_type_flags_to_name): Likewise. ++ (avr_address_class_name_to_type_flags): Likewise. ++ (avr_gdbarch_init): Set address_class_type_flags, ++ address_class_type_flags_to_name and ++ address_class_name_to_type_flags. ++ + 2014-07-14 Pedro Alves + + * utils.c (prompt_for_continue): Call target_terminal_ours. +@@ -220,6 +240,14 @@ + * target.c (target_require_runnable): Also check record_stratum. + Update comment. + ++2014-06-12 Pierre Langlois ++ ++ * regcache.c (struct register_to_invalidate): New structure. ++ (do_register_invalidate, make_cleanup_regcache_invalidate): New ++ functions. ++ (regcache_raw_write): Call make_cleanup_regcache_invalidate. ++ ++ + 2014-07-09 Pedro Alves + + * infcmd.c (attach_command_post_wait): Don't call diff --git a/gdb/avr-tdep.c b/gdb/avr-tdep.c -index cb330ea..1be9e7d 100644 +index 9b0bfaf..1f268f2 100644 --- a/gdb/avr-tdep.c +++ b/gdb/avr-tdep.c -@@ -179,7 +179,7 @@ struct avr_unwind_cache - struct gdbarch_tdep - { - /* Number of bytes stored to the stack by call instructions. -- 2 bytes for avr1-5, 3 bytes for avr6. */ -+ 2 bytes for avr1-5 and avrxmega1-5, 3 bytes for avr6 and avrxmega6-7. */ - int call_length; +@@ -71,6 +71,16 @@ - /* Type for void. */ -@@ -719,7 +719,7 @@ avr_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR pc_beg, CORE_ADDR pc_end, - info->size += gdbarch_tdep (gdbarch)->call_length; - vpc += 2; - } -- else if (insn == 0x920f) /* push r0 */ -+ else if (insn == 0x920f || insn == 0x921f) /* push r0 or push r1 */ - { - info->size += 1; - vpc += 2; -@@ -1355,14 +1355,21 @@ avr_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) - switch (info.bfd_arch_info->mach) + /* Constants: prefixed with AVR_ to avoid name space clashes */ + ++/* Address space flags */ ++ ++/* We are assigning the TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1 to the flash address ++ space. */ ++ ++#define AVR_TYPE_ADDRESS_CLASS_FLASH TYPE_ADDRESS_CLASS_1 ++#define AVR_TYPE_INSTANCE_FLAG_ADDRESS_CLASS_FLASH \ ++ TYPE_INSTANCE_FLAG_ADDRESS_CLASS_1 ++ ++ + enum + { + AVR_REG_W = 24, +@@ -295,10 +305,19 @@ avr_address_to_pointer (struct gdbarch *gdbarch, + { + enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); + ++ /* Is it a data address in flash? */ ++ if (AVR_TYPE_ADDRESS_CLASS_FLASH (type)) ++ { ++ /* A data pointer in flash is byte addressed. */ ++ store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order, ++ avr_convert_iaddr_to_raw (addr)); ++ } + /* Is it a code address? */ +- if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC +- || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD) ++ else if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC ++ || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD) { - case bfd_mach_avr1: -+ case bfd_mach_avrxmega1: - case bfd_mach_avr2: -+ case bfd_mach_avrxmega2: - case bfd_mach_avr3: -+ case bfd_mach_avrxmega3: - case bfd_mach_avr4: -+ case bfd_mach_avrxmega4: - case bfd_mach_avr5: -+ case bfd_mach_avrxmega5: - default: - call_length = 2; - break; - case bfd_mach_avr6: -+ case bfd_mach_avrxmega6: -+ case bfd_mach_avrxmega7: - call_length = 3; - break; ++ /* A code pointer is word (16 bits) addressed. We shift the address down ++ by 1 bit to convert it to a pointer. */ + store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order, + avr_convert_iaddr_to_raw (addr >> 1)); } +@@ -318,11 +337,21 @@ avr_pointer_to_address (struct gdbarch *gdbarch, + CORE_ADDR addr + = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order); + ++ /* Is it a data address in flash? */ ++ if (AVR_TYPE_ADDRESS_CLASS_FLASH (type)) ++ { ++ /* A data pointer in flash is already byte addressed. */ ++ return avr_make_iaddr (addr); ++ } + /* Is it a code address? */ +- if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC +- || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD +- || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type))) +- return avr_make_iaddr (addr << 1); ++ else if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC ++ || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD ++ || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type))) ++ { ++ /* A code pointer is word (16 bits) addressed so we shift it up ++ by 1 bit to convert it to an address. */ ++ return avr_make_iaddr (addr << 1); ++ } + else + return avr_make_saddr (addr); + } +@@ -1342,6 +1371,54 @@ avr_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) + return -1; + } + ++/* Implementation of `address_class_type_flags' gdbarch method. ++ ++ This method maps DW_AT_address_class attributes to a ++ type_instance_flag_value. */ ++ ++static int ++avr_address_class_type_flags (int byte_size, int dwarf2_addr_class) ++{ ++ /* The value 1 of the DW_AT_address_class attribute corresponds to the ++ __flash qualifier. Note that this attribute is only valid with ++ pointer types and therefore the flag is set to the pointer type and ++ not its target type. */ ++ if (dwarf2_addr_class == 1 && byte_size == 2) ++ return AVR_TYPE_INSTANCE_FLAG_ADDRESS_CLASS_FLASH; ++ return 0; ++} ++ ++/* Implementation of `address_class_type_flags_to_name' gdbarch method. ++ ++ Convert a type_instance_flag_value to an address space qualifier. */ ++ ++static const char* ++avr_address_class_type_flags_to_name (struct gdbarch *gdbarch, int type_flags) ++{ ++ if (type_flags & AVR_TYPE_INSTANCE_FLAG_ADDRESS_CLASS_FLASH) ++ return "flash"; ++ else ++ return NULL; ++} ++ ++/* Implementation of `address_class_name_to_type_flags' gdbarch method. ++ ++ Convert an address space qualifier to a type_instance_flag_value. */ ++ ++static int ++avr_address_class_name_to_type_flags (struct gdbarch *gdbarch, ++ const char* name, ++ int *type_flags_ptr) ++{ ++ if (strcmp (name, "flash") == 0) ++ { ++ *type_flags_ptr = AVR_TYPE_INSTANCE_FLAG_ADDRESS_CLASS_FLASH; ++ return 1; ++ } ++ else ++ return 0; ++} ++ + /* Initialize the gdbarch structure for the AVR's. */ + + static struct gdbarch * +@@ -1452,6 +1529,12 @@ avr_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) + set_gdbarch_unwind_pc (gdbarch, avr_unwind_pc); + set_gdbarch_unwind_sp (gdbarch, avr_unwind_sp); + ++ set_gdbarch_address_class_type_flags (gdbarch, avr_address_class_type_flags); ++ set_gdbarch_address_class_name_to_type_flags ++ (gdbarch, avr_address_class_name_to_type_flags); ++ set_gdbarch_address_class_type_flags_to_name ++ (gdbarch, avr_address_class_type_flags_to_name); ++ + return gdbarch; + } + +diff --git a/gdb/regcache.c b/gdb/regcache.c +index 8b588c6..5ee90b0 100644 +--- a/gdb/regcache.c ++++ b/gdb/regcache.c +@@ -267,6 +267,32 @@ make_cleanup_regcache_xfree (struct regcache *regcache) + return make_cleanup (do_regcache_xfree, regcache); + } + ++/* Cleanup routines for invalidating a register. */ ++ ++struct register_to_invalidate ++{ ++ struct regcache *regcache; ++ int regnum; ++}; ++ ++static void ++do_regcache_invalidate (void *data) ++{ ++ struct register_to_invalidate *reg = data; ++ ++ regcache_invalidate (reg->regcache, reg->regnum); ++} ++ ++static struct cleanup * ++make_cleanup_regcache_invalidate (struct regcache *regcache, int regnum) ++{ ++ struct register_to_invalidate* reg = XNEW (struct register_to_invalidate); ++ ++ reg->regcache = regcache; ++ reg->regnum = regnum; ++ return make_cleanup_dtor (do_regcache_invalidate, (void *) reg, xfree); ++} ++ + /* Return REGCACHE's architecture. */ + + struct gdbarch * +@@ -846,7 +872,8 @@ void + regcache_raw_write (struct regcache *regcache, int regnum, + const gdb_byte *buf) + { +- struct cleanup *old_chain; ++ struct cleanup *chain_before_save_inferior; ++ struct cleanup *chain_before_invalidate_register; + + gdb_assert (regcache != NULL && buf != NULL); + gdb_assert (regnum >= 0 && regnum < regcache->descr->nr_raw_registers); +@@ -864,16 +891,26 @@ regcache_raw_write (struct regcache *regcache, int regnum, + regcache->descr->sizeof_register[regnum]) == 0)) + return; + +- old_chain = save_inferior_ptid (); ++ chain_before_save_inferior = save_inferior_ptid (); + inferior_ptid = regcache->ptid; + + target_prepare_to_store (regcache); + memcpy (register_buffer (regcache, regnum), buf, + regcache->descr->sizeof_register[regnum]); + regcache->register_status[regnum] = REG_VALID; ++ ++ /* Register a cleanup function for invalidating the register after it is ++ written, in case of a failure. */ ++ chain_before_invalidate_register ++ = make_cleanup_regcache_invalidate (regcache, regnum); ++ + target_store_registers (regcache, regnum); + +- do_cleanups (old_chain); ++ /* The target did not throw an error so we can discard invalidating the ++ register and restore the cleanup chain to what it was. */ ++ discard_cleanups (chain_before_invalidate_register); ++ ++ do_cleanups (chain_before_save_inferior); + } + + void +diff --git a/gdb/testsuite/gdb.arch/avr-flash-qualifier.c b/gdb/testsuite/gdb.arch/avr-flash-qualifier.c +new file mode 100644 +index 0000000..7bfbe3a +--- /dev/null ++++ b/gdb/testsuite/gdb.arch/avr-flash-qualifier.c +@@ -0,0 +1,33 @@ ++/* This testcase is part of GDB, the GNU debugger. ++ ++ Copyright 2014 Free Software Foundation, Inc. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program. If not, see . */ ++ ++const __flash char data_in_flash = 0xab; ++ ++static void ++pass_to_function (const __flash char *p) ++{ ++} ++ ++int ++main (void) ++{ ++ const __flash char *pointer_to_flash = &data_in_flash; ++ ++ /* break here. */ ++ pass_to_function (&data_in_flash); ++ return 0; ++} +diff --git a/gdb/testsuite/gdb.arch/avr-flash-qualifier.exp b/gdb/testsuite/gdb.arch/avr-flash-qualifier.exp +new file mode 100644 +index 0000000..e9ccb4f +--- /dev/null ++++ b/gdb/testsuite/gdb.arch/avr-flash-qualifier.exp +@@ -0,0 +1,52 @@ ++# Copyright 2014 Free Software Foundation, Inc. ++ ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 3 of the License, or ++# (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program. If not, see . ++# ++# This file is part of the gdb testsuite. ++# ++# Contributed by Pierre Langlois ++# Tests for the AVR __flash named address space qualifier. ++ ++if {![istarget "avr*"]} { ++ verbose "Skipping ${gdb_test_file_name}." ++ return ++} ++ ++# The __flash qualifier was added in GCC 4.7. ++if {[test_compiler_info {gcc-[0-4]-[0-6]}]} { ++ verbose "Skipping ${gdb_test_file_name}." ++ return ++} ++ ++standard_testfile ++if {[prepare_for_testing ${testfile}.exp ${testfile} ${srcfile}]} { ++ return -1 ++} ++ ++if ![runto [gdb_get_line_number "break here."]] { ++ untested "could not run to \"break here.\"" ++ return -1 ++} ++ ++gdb_test "print pointer_to_flash" \ ++ " = $hex .*" ++ ++gdb_breakpoint "pass_to_function" ++gdb_continue_to_breakpoint "pass_to_function" ++ ++gdb_test "print p" \ ++ " = $hex .*" ++ ++gdb_test "backtrace 1" \ ++ "\#0 pass_to_function \\(p=$hex .*\\).*" diff --git a/gold/ChangeLog b/gold/ChangeLog new file mode 100644 -index 0000000..1cec15e +index 0000000..151fcde --- /dev/null +++ b/gold/ChangeLog -@@ -0,0 +1,15500 @@ +@@ -0,0 +1,15835 @@ ++2014-06-09 Cary Coutant ++ ++ * dwarf_reader.cc (Dwarf_pubnames_table::read_header): Check that ++ unit_length is within section bounds. ++ ++2014-06-09 Cary Coutant ++ ++ PR gold/16980 ++ * layout.cc (Layout::print_to_mapfile): Print unattached sections in ++ map. ++ ++2014-06-07 Alan Modra ++ ++ * powerpc.cc (relocate): Treat field of cmpli insn as a bitfield. ++ ++2014-06-06 Cary Coutant ++ ++ * dwarf_reader.h (Dwarf_pubnames_table): Remove output_section_offset_. ++ * dwarf_reader.cc (Dwarf_pubnames_table::read_section): Likewise. ++ (Dwarf_pubnames_table::read_header): Likewise. ++ * layout.cc (gdb_fast_lookup_sections): Add .debug_gnu_pubnames and ++ .debug_gnu_pubtypes. ++ ++2014-06-05 Joel Brobecker ++ ++ * Makefile.am (CONFIG_STATUS_DEPENDENCIES): New. ++ * Makefile.in, configure: Regenerate. ++ ++2014-06-03 Alan Modra ++ ++ * powerpc.cc (addis_12_2): Define. ++ (Stub_table::do_write): Support fusion on ELFv2 stubs. ++ ++2014-06-03 Alan Modra ++ ++ * testsuite/plugin_test.c (parse_readelf_line): Skip non-visibility ++ st_other output. ++ ++2014-06-02 Alan Modra ++ ++ * powerpc.cc (Target_powerpc::local_reloc_may_be_function_pointer): ++ Only ignore relocs on ELFv1. ++ (Target_powerpc::global_reloc_may_be_function_pointer): Likewise. ++ ++2014-05-30 Cary Coutant ++ ++ * testsuite/Makefile.am (ehdr_start_test_4): Fix typo in -B option. ++ * testsuite/Makefile.in: Regenerate. ++ * testsuite/ehdr_start_test_4.sh: Look for "U" instead of "w". ++ ++2014-05-27 H.J. Lu ++ ++ PR gold/16945 ++ * x86_64.cc (Target_x86_64::Relocate::relocate): Use signed int ++ for got_offset. Properly get GOT address for R_X86_64_PLTOFF64. ++ ++2014-05-15 Alan Modra ++ ++ * powerpc.cc (do_plt_fde_location): Handle zero length .glink. ++ Compare FDE contents with DW_CFA_nop rather than 0. ++ ++2014-05-13 Sriraman Tallam ++ ++ * symtab.h (may_need_copy_reloc): Remove check for position independent ++ code. ++ * x86_64.cc (Target_x86_64::Scan::global): Add check for no ++ position independence before pc absolute may_need_copy_reloc call. ++ Add check for executable output befor pc relative may_need_copy_reloc ++ call. ++ * i386.cc: Ditto. ++ * arm.cc: Ditto. ++ * sparc.cc: Ditto. ++ * tilegx.cc: Ditto. ++ * powerpc.cc: Add check for no position independence before ++ may_need_copy_reloc calls. ++ * testsuite/pie_copyrelocs_test.cc: New file. ++ * testsuite/pie_copyrelocs_shared_test.cc: New file. ++ * Makefile.am (pie_copyrelocs_test): New test. ++ * Makefile.in: Regenerate. ++ ++2014-05-08 Martin Liška ++ ++ * output.cc (Sized_relobj_file::do_layout): Fix typo in info message. ++ ++2014-05-06 Cary Coutant ++ ++ PR gold/16900 ++ * i386.cc (Output_data_got_plt_i386): New class. ++ (Output_data_plt_i386::Output_data_plt_i386): Change type of got_plt ++ parameter. Change all callers. ++ (Output_data_plt_i386::layout_): Remove. ++ (Output_data_plt_i386::got_plt_): Change type. ++ (Target_i386::got_plt_): Change type. Change all references. ++ (Target_i386::got_section): Create instance of new class. ++ (Output_data_got_plt_i386::do_write): New function. ++ * x86_64.cc (Output_data_got_plt_x86_64): New class. ++ (Output_data_plt_x86_64::Output_data_plt_x86_64): Change type of got_plt ++ parameter. Change all callers. ++ (Output_data_plt_x86_64::layout_): Remove. ++ (Output_data_plt_x86_64::got_plt_): Change type. ++ (Target_x86_64::got_plt_): Change type. Change all references. ++ (Target_x86_64::got_section): Create instance of new class. ++ (Output_data_got_plt_x86_64::do_write): New function. ++ (Output_data_plt_x86_64::do_write): Don't write reserved words in GOT. ++ (Target_x86_64::init_got_plt_for_update): Create instance of new ++ class. ++ ++2014-05-05 Cary Coutant ++ ++ * gdb-index.cc (Gdb_index_info_reader): Don't complain about language ++ if we have pubnames/pubtypes. ++ ++2014-05-02 Cary Coutant ++ ++ * defstd.cc (in_segment): Define __ehdr_start here... ++ * layout.cc (Layout::finalize): ...Instead of here. Set the ++ output segment when known. ++ * resolve.cc (Symbol::override_base_with_special): Remember ++ the original binding. ++ * symtab.cc (Symbol::set_output_segment): New function. ++ (Symbol::set_undefined): New function. ++ * symtab.h (Symbol::is_weak_undefined): Check original undef ++ binding. ++ (Symbol::is_strong_undefined): New function. ++ (Symbol::set_output_segment): New function. ++ (Symbol::set_undefined): New function. ++ * target-reloc.h (is_strong_undefined): Remove. ++ (issue_undefined_symbol_error): Call Symbol::is_weak_undefined. ++ Check for hidden undefs. ++ (relocate_section): Call Symbol::is_strong_undefined. ++ ++ * testsuite/Makefile.am (ehdr_start_test_1) ++ (ehdr_start_test_2, ehdr_start_test_3) ++ (ehdr_start_test_4, ehdr_start_test_5): New test cases. ++ * testsuite/Makefile.in: Regenerate. ++ * testsuite/ehdr_start_def.cc: New source file. ++ * testsuite/ehdr_start_test.cc: New source file. ++ * testsuite/ehdr_start_test.t: New linker script. ++ * testsuite/ehdr_start_test_4.sh: New shell script. ++ ++2014-04-23 Cary Coutant ++ ++ PR gold/16870 ++ * x86_64.cc (Target_x86_64::Relocate::relocate): Add missing break. ++ ++2014-04-15 Sasa Stankovic ++ ++ * layout.cc (Layout::include_section): Allow a target to decide ++ whether to include a section. ++ * target.h (Target::should_include_section): New function. ++ (Target::do_should_include_section): New function. ++ ++2014-04-15 Sasa Stankovic ++ ++ * copy-relocs.cc (Copy_relocs::Copy_reloc_entry::emit): Remove and ++ inline into ... ++ (Copy_relocs::emit): ... here. ++ * copy-relocs.h (Copy_reloc_entry): Change from class to struct. ++ (Copy_reloc_entry::make_copy_reloc): Change from private to protected. ++ (Copy_reloc_entry::entries_): Change from private to protected. ++ ++2014-04-02 Sriraman Tallam ++ ++ * icf.cc (get_section_contents): Replace copies of reloc ++ vectors with const references. ++ ++2014-04-02 Cary Coutant ++ ++ * configure.ac (HAVE_PUBNAMES): Use C instead of C++. ++ (HAVE_NO_USE_LINKER_PLUGIN): Check for -fno-use-linker-plugin. ++ * configure: Regenerate. ++ * testsuite/Makefile.am (OPT_NO_PLUGINS): New macro for ++ -fno-use-linker-plugin. ++ (LINK1, CXXLINK1): Add it to the link command. ++ * testsuite/Makefile.in: Regenerate. ++ ++2014-03-12 Alan Modra ++ ++ * Makefile.in: Regenerate. ++ ++2014-03-10 Sasa Stankovic ++ ++ * symtab.h (Symbol::set_nonvis): New function. ++ ++2014-03-10 Sasa Stankovic ++ ++ * symtab.cc (Sized_symbol<32>::init_output_data): ++ Instantiate the template. ++ (Sized_symbol<64>::init_output_data): Likewise. ++ ++2014-03-10 Sasa Stankovic ++ ++ * symtab.cc (Symbol_table::sized_write_globals): Allow a target to ++ adjust dynamic symbol value. ++ * target.h (Target::adjust_dyn_symbol): New function. ++ (Target::do_adjust_dyn_symbol): New function. ++ ++2014-03-10 Sasa Stankovic ++ ++ * output.cc (Output_data_dynamic::Dynamic_entry::write): ++ Get the value of DYNAMIC_CUSTOM dynamic entry. ++ * output.h (Output_data_dynamic::add_custom): New function. ++ (Dynamic_entry::Dynamic_entry): New constructor for DYNAMIC_CUSTOM ++ dynamic entry. ++ (enum Dynamic_entry::Classification): Add DYNAMIC_CUSTOM. ++ * target.h (Target::dynamic_tag_custom_value): New function. ++ (Target::do_dynamic_tag_custom_value): New function. ++ ++2014-03-10 Sasa Stankovic ++ ++ * symtab.cc (Symbol_table::set_dynsym_indexes): Allow a target to set ++ dynsym indexes. ++ * target.h (Target::has_custom_set_dynsym_indexes): New function. ++ (Target::do_has_custom_set_dynsym_indexes): New function. ++ (Target::set_dynsym_indexes): New function. ++ (Target::do_set_dynsym_indexes): New function. ++ ++2014-03-07 Alan Modra ++ ++ * powerpc.cc (Powerpc_relocate_functions::Overflow_check): Add ++ CHECK_UNSIGNED, CHECK_LOW_INSN, CHECK_HIGH_INSN. ++ (Powerpc_relocate_functions::has_overflow_unsigned): New function. ++ (Powerpc_relocate_functions::has_overflow_bitfield, ++ overflowed): Use the above. ++ (Target_powerpc::Relocate::relocate): Correct overflow checking ++ for a number of relocations. Modify overflow test for 16-bit ++ fields in instructions to signed/unsigned according to whether ++ the field takes a signed or unsigned value. ++ ++2014-03-05 Alan Modra ++ ++ Update copyright years. ++ ++2014-03-05 Alan Modra ++ ++ * powerpc.cc (Target_powerpc::Scan::local, global): Support ++ R_PPC64_ADDR64_LOCAL. ++ (Target_powerpc::Relocate::relocate): Likewise. ++ ++2014-03-03 Alan Modra ++ ++ * dwp.cc (print_version): Update copyright year to current. ++ ++2014-02-10 Alan Modra ++ ++ * po/gold.pot: Regenerate. ++ ++2014-02-06 Cary Coutant ++ ++ Fix problem where -u is ignored when a weak undef is seen. ++ ++ * archive.cc (Library_base::should_include_member): Reorder ++ code to check for -u option if a weak undef has already been seen. ++ * testsuite/Makefile.am (weak_undef_test_2): New test case. ++ * testsuite/Makefile.in: Regenerate. ++ * testsuite/weak_undef_file3.cc: New file. ++ * testsuite/weak_undef_file4.cc: New file. ++ * testsuite/weak_undef_test_2.cc: New file. ++ ++2014-02-05 Cary Coutant ++ ++ Fix issues with gold undefined symbol diagnostics. ++ ++ PR binutils/15435 ++ * errors.cc (Errors::undefined_symbol): Move undef vtable symbol ++ check to here. ++ * target-reloc.h (is_strong_undefined): New function. ++ (relocate_section): Move undef vtable symbol check from here. ++ Check for is_strong_undefined. ++ ++2014-02-05 Cary Coutant ++ ++ Fix problems with the --dynamic-list option. ++ ++ PR gold/13577 ++ * options.cc (General_options::parse_dynamic_list): ++ Set have_dynamic_list_. ++ (General_options::General_options): Initialize have_dynamic_list_. ++ (General_options::finalize): Turn off -Bsymbolic and ++ -Bsymbolic-functions if --dynamic-list provided. ++ * options.h (General_options::have_dynamic_list): New function. ++ (General_options::have_dynamic_list_): New data member. ++ * symtab.h (Symbol::is_preemptible): Handle --dynamic-list ++ correctly. ++ ++ PR gold/16530 ++ * symtab.cc (Symbol_table::add_from_relobj): If symbol is named ++ in --dynamic-list, mark it. ++ ++ * testsuite/Makefile.am (gc_dynamic_list_test.sh): New test case. ++ (dynamic_list_2): New test case. ++ * testsuite/Makefile.in: Regenerate. ++ * testsuite/dynamic_list_2.cc: New file. ++ * testsuite/dynamic_list_2.t: New file. ++ * testsuite/dynamic_list_lib1.cc: New file. ++ * testsuite/dynamic_list_lib2.cc: New file. ++ * testsuite/gc_dynamic_list_test.c: New file. ++ * testsuite/gc_dynamic_list_test.sh: New file. ++ * testsuite/gc_dynamic_list_test.t: New file. ++ ++2014-01-28 Cary Coutant ++ ++ Add .gdb_index version 7 support. ++ ++ * gold/dwarf_reader.cc: include (for make_pair). ++ (Dwarf_abbrev_table::do_read_abbrevs): Check for compressed ++ debug sections. ++ (Dwarf_ranges_table::read_ranges_table): Likewise. ++ (Dwarf_pubnames_table::read_section): Check for GNU-style ++ sections, and for compressed debug sections. ++ (Dwarf_pubnames_table::read_header): Compute end address of table. ++ (Dwarf_pubnames_table::next_name): Return flag_byte. Check ++ for end of list by offset, not by offset == 0. ++ (Dwarf_info_reader::do_read_string_table): Check for compressed ++ debug sections. ++ * gold/dwarf_reader.h (Dwarf_pubnames_table::Dwarf_pubnames_table): ++ Initialize new data members. ++ (Dwarf_pubnames_table::next_name): return flag_byte. ++ (Dwarf_pubnames_table::end_of_table_): New data member. ++ (Dwarf_pubnames_table::is_gnu_style_): New data member. ++ * gold/gdb-index.cc (gdb_index_version): Update to version 7. ++ (Gdb_index_info_reader::read_pubtable): Read flag_byte. ++ (Gdb_index_info_reader::read_pubnames_and_pubtypes): Don't ++ read skeleton type unit DIEs. ++ (Gdb_index::add_symbol): Add flag_byte; adjust all callers. ++ (Gdb_index::do_write): Write flag_byte. ++ * gold/gdb-index.h (Gdb_index::add_symbol): Add flags parameter. ++ (Gdb_index::Cu_vector): Store flags along with cu indexes. ++ * gold/testsuite/gdb_index_test_3.sh: Allow versions 4-7. ++ * gold/testsuite/gdb_index_test_comm.sh: Likewise. ++ ++2014-01-08 H.J. Lu ++ ++ * version.cc (print_version): Update copyright year to 2014. ++ +2013-12-19 Dimitry Andric + + * stringpool.cc (Stringpool_template::reserve): Add @@ -2291105,7 +2301717,7 @@ index 0000000..1cec15e + + * Added source code to GNU binutils. + -+Copyright (C) 2008-2013 Free Software Foundation, Inc. ++Copyright (C) 2008-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -2291119,14 +2301731,13 @@ index 0000000..1cec15e +End: diff --git a/gold/Makefile.am b/gold/Makefile.am new file mode 100644 -index 0000000..42704ce +index 0000000..54393f9 --- /dev/null +++ b/gold/Makefile.am -@@ -0,0 +1,364 @@ +@@ -0,0 +1,365 @@ +## Process this file with automake to generate Makefile.in +# -+# Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 -+# Free Software Foundation, Inc. ++# Copyright (C) 2006-2014 Free Software Foundation, Inc. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -2291323,6 +2301934,8 @@ index 0000000..42704ce + $(LIBDL) +dwp_LDFLAGS = $(GOLD_LDFLAGS) + ++CONFIG_STATUS_DEPENDENCIES = $(srcdir)/../bfd/development.sh ++ +# Use an explicit dependency for the bison generated header file. +expression.$(OBJEXT): yyscript.h +script-sections.$(OBJEXT): yyscript.h @@ -2291489,7 +2302102,7 @@ index 0000000..42704ce +endif diff --git a/gold/Makefile.in b/gold/Makefile.in new file mode 100644 -index 0000000..661613e +index 0000000..579505a --- /dev/null +++ b/gold/Makefile.in @@ -0,0 +1,1386 @@ @@ -2291511,8 +2302124,7 @@ index 0000000..661613e +@SET_MAKE@ + +# -+# Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 -+# Free Software Foundation, Inc. ++# Copyright (C) 2006-2014 Free Software Foundation, Inc. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -2292060,6 +2302672,7 @@ index 0000000..661613e + $(LIBDL) + +dwp_LDFLAGS = $(GOLD_LDFLAGS) ++CONFIG_STATUS_DEPENDENCIES = $(srcdir)/../bfd/development.sh +POTFILES = $(CCFILES) $(HFILES) $(TARGETSOURCES) +@GCC_TRUE@@NATIVE_LINKER_TRUE@ld1_SOURCES = $(sources_var) +@GCC_TRUE@@NATIVE_LINKER_TRUE@ld1_DEPENDENCIES = $(deps_var) gcctestdir1/ld @@ -2292881,13 +2303494,13 @@ index 0000000..661613e +.NOEXPORT: diff --git a/gold/NEWS b/gold/NEWS new file mode 100644 -index 0000000..d73ceeb +index 0000000..bb246f6 --- /dev/null +++ b/gold/NEWS @@ -0,0 +1,11 @@ +* gold added to GNU binutils. + -+Copyright (C) 2012 Free Software Foundation, Inc. ++Copyright (C) 2012-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -2292898,7 +2303511,7 @@ index 0000000..d73ceeb +End: diff --git a/gold/README b/gold/README new file mode 100644 -index 0000000..0fccc13 +index 0000000..b1b24f1 --- /dev/null +++ b/gold/README @@ -0,0 +1,69 @@ @@ -2292966,7 +2303579,7 @@ index 0000000..0fccc13 +the bison output should already be included. + + -+Copyright (C) 2012 Free Software Foundation, Inc. ++Copyright (C) 2012-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -2294003,14 +2304616,13 @@ index 0000000..8321894 +m4_include([../bfd/warning.m4]) diff --git a/gold/archive.cc b/gold/archive.cc new file mode 100644 -index 0000000..53d88a2 +index 0000000..23cb0be --- /dev/null +++ b/gold/archive.cc -@@ -0,0 +1,1313 @@ +@@ -0,0 +1,1322 @@ +// archive.cc -- archive support for gold + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2013 -+// Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2294106,46 +2304718,56 @@ index 0000000..53d88a2 + + *symp = sym; + -+ if (sym == NULL) ++ if (sym != NULL) + { -+ // Check whether the symbol was named in a -u option. -+ if (parameters->options().is_undefined(sym_name)) -+ { -+ *why = "-u "; -+ *why += sym_name; -+ } -+ else if (parameters->options().is_export_dynamic_symbol(sym_name)) -+ { -+ *why = "--export-dynamic-symbol "; -+ *why += sym_name; -+ } -+ else if (layout->script_options()->is_referenced(sym_name)) -+ { -+ size_t alc = 100 + strlen(sym_name); -+ char* buf = new char[alc]; -+ snprintf(buf, alc, _("script or expression reference to %s"), -+ sym_name); -+ *why = buf; -+ delete[] buf; -+ } -+ else if (strcmp(sym_name, parameters->entry()) == 0) -+ { -+ *why = "entry symbol "; -+ *why += sym_name; -+ } -+ else -+ return Library_base::SHOULD_INCLUDE_UNKNOWN; -+ } -+ else if (!sym->is_undefined()) -+ return Library_base::SHOULD_INCLUDE_NO; -+ // PR 12001: Do not include an archive when the undefined -+ // symbol has actually been defined on the command line. -+ else if (layout->script_options()->is_pending_assignment(sym_name)) -+ return Library_base::SHOULD_INCLUDE_NO; -+ else if (sym->binding() == elfcpp::STB_WEAK) -+ return Library_base::SHOULD_INCLUDE_UNKNOWN; ++ if (!sym->is_undefined()) ++ return Library_base::SHOULD_INCLUDE_NO; + -+ return Library_base::SHOULD_INCLUDE_YES; ++ // PR 12001: Do not include an archive when the undefined ++ // symbol has actually been defined on the command line. ++ if (layout->script_options()->is_pending_assignment(sym_name)) ++ return Library_base::SHOULD_INCLUDE_NO; ++ ++ // If the symbol is weak undefined, we still need to check ++ // for other reasons (like a -u option). ++ if (sym->binding() != elfcpp::STB_WEAK) ++ return Library_base::SHOULD_INCLUDE_YES; ++ } ++ ++ // Check whether the symbol was named in a -u option. ++ if (parameters->options().is_undefined(sym_name)) ++ { ++ *why = "-u "; ++ *why += sym_name; ++ return Library_base::SHOULD_INCLUDE_YES; ++ } ++ ++ if (parameters->options().is_export_dynamic_symbol(sym_name)) ++ { ++ *why = "--export-dynamic-symbol "; ++ *why += sym_name; ++ return Library_base::SHOULD_INCLUDE_YES; ++ } ++ ++ if (layout->script_options()->is_referenced(sym_name)) ++ { ++ size_t alc = 100 + strlen(sym_name); ++ char* buf = new char[alc]; ++ snprintf(buf, alc, _("script or expression reference to %s"), ++ sym_name); ++ *why = buf; ++ delete[] buf; ++ return Library_base::SHOULD_INCLUDE_YES; ++ } ++ ++ if (strcmp(sym_name, parameters->entry()) == 0) ++ { ++ *why = "entry symbol "; ++ *why += sym_name; ++ return Library_base::SHOULD_INCLUDE_YES; ++ } ++ ++ return Library_base::SHOULD_INCLUDE_UNKNOWN; +} + +// The header of an entry in the archive. This is all readable text, @@ -2295322,13 +2305944,13 @@ index 0000000..53d88a2 +} // End namespace gold. diff --git a/gold/archive.h b/gold/archive.h new file mode 100644 -index 0000000..3d75de6 +index 0000000..e031559 --- /dev/null +++ b/gold/archive.h @@ -0,0 +1,571 @@ +// archive.h -- archive support for gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008, 2010, 2011, 2013 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2295899,13 +2306521,13 @@ index 0000000..3d75de6 +#endif // !defined(GOLD_ARCHIVE_H) diff --git a/gold/arm-reloc-property.cc b/gold/arm-reloc-property.cc new file mode 100644 -index 0000000..3259c40 +index 0000000..dfc2fe1 --- /dev/null +++ b/gold/arm-reloc-property.cc @@ -0,0 +1,333 @@ +// arm-reloc-property.cc -- ARM relocation property. + -+// Copyright 2010 Free Software Foundation, Inc. ++// Copyright (C) 2010-2014 Free Software Foundation, Inc. +// Written by Doug Kwan . + +// This file is part of gold. @@ -2296238,13 +2306860,13 @@ index 0000000..3259c40 +} // End namespace gold. diff --git a/gold/arm-reloc-property.h b/gold/arm-reloc-property.h new file mode 100644 -index 0000000..afba293 +index 0000000..d98f644 --- /dev/null +++ b/gold/arm-reloc-property.h @@ -0,0 +1,386 @@ +// arm-reloc-property.h -- ARM relocation properties -*- C++ -*- + -+// Copyright 2010 Free Software Foundation, Inc. ++// Copyright (C) 2010-2014 Free Software Foundation, Inc. +// Written by Doug Kwan . + +// This file is part of gold. @@ -2296630,13 +2307252,13 @@ index 0000000..afba293 +#endif // !defined(GOLD_ARM_RELOC_PROPERTY_H) diff --git a/gold/arm-reloc.def b/gold/arm-reloc.def new file mode 100644 -index 0000000..3a5ab6c +index 0000000..9bccdfa --- /dev/null +++ b/gold/arm-reloc.def @@ -0,0 +1,194 @@ +// arm-reloc.def -- ARM relocation definitions. + -+// Copyright 2010 Free Software Foundation, Inc. ++// Copyright (C) 2010-2014 Free Software Foundation, Inc. +// Written by Doug Kwan . + +// This file is part of gold. @@ -2296830,13 +2307452,13 @@ index 0000000..3a5ab6c +RD(THM_TLS_DESCSEQ32 , STATIC , N, THM32, NONE , N, -1, Y) diff --git a/gold/arm.cc b/gold/arm.cc new file mode 100644 -index 0000000..560f380 +index 0000000..607f9d6 --- /dev/null +++ b/gold/arm.cc -@@ -0,0 +1,12387 @@ +@@ -0,0 +1,12389 @@ +// arm.cc -- arm target support for gold. + -+// Copyright 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Doug Kwan based on the i386 code +// by Ian Lance Taylor . +// This file also contains borrowed and adapted code from @@ -2305137,7 +2315759,8 @@ index 0000000..560f380 + // Make a dynamic relocation if necessary. + if (gsym->needs_dynamic_reloc(Scan::get_reference_flags(r_type))) + { -+ if (gsym->may_need_copy_reloc()) ++ if (!parameters->options().output_is_position_independent() ++ && gsym->may_need_copy_reloc()) + { + target->copy_reloc(symtab, layout, object, + data_shndx, output_section, gsym, reloc); @@ -2305218,7 +2315841,8 @@ index 0000000..560f380 + // Make a dynamic relocation if necessary. + if (gsym->needs_dynamic_reloc(Scan::get_reference_flags(r_type))) + { -+ if (target->may_need_copy_reloc(gsym)) ++ if (parameters->options().output_is_executable() ++ && target->may_need_copy_reloc(gsym)) + { + target->copy_reloc(symtab, layout, object, + data_shndx, output_section, gsym, reloc); @@ -2309223,13 +2319847,13 @@ index 0000000..560f380 +} // End anonymous namespace. diff --git a/gold/attributes.cc b/gold/attributes.cc new file mode 100644 -index 0000000..45ab5a0 +index 0000000..8e2892c --- /dev/null +++ b/gold/attributes.cc @@ -0,0 +1,458 @@ +// attributes.cc -- object attributes for gold + -+// Copyright 2009 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Doug Kwan . +// This file contains code adapted from BFD. + @@ -2309687,13 +2320311,13 @@ index 0000000..45ab5a0 +} // End namespace gold. diff --git a/gold/attributes.h b/gold/attributes.h new file mode 100644 -index 0000000..26fe158 +index 0000000..2aa7a78 --- /dev/null +++ b/gold/attributes.h @@ -0,0 +1,406 @@ +// attributes.h -- object attributes for gold -*- C++ -*- + -+// Copyright 2009, 2010 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Doug Kwan . +// This file contains code adapted from BFD. + @@ -2310099,13 +2320723,13 @@ index 0000000..26fe158 +#endif // !defined(GOLD_ATTRIBUTES_H) diff --git a/gold/binary.cc b/gold/binary.cc new file mode 100644 -index 0000000..6cc99a9 +index 0000000..4dab52c --- /dev/null +++ b/gold/binary.cc @@ -0,0 +1,363 @@ +// binary.cc -- binary input files for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2310468,13 +2321092,13 @@ index 0000000..6cc99a9 +} // End namespace gold. diff --git a/gold/binary.h b/gold/binary.h new file mode 100644 -index 0000000..75bc731 +index 0000000..3ce84c2 --- /dev/null +++ b/gold/binary.h @@ -0,0 +1,116 @@ +// binary.h -- binary input files for gold -*- C++ -*- + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2310590,14 +2321214,13 @@ index 0000000..75bc731 +#endif // !defined(GOLD_BINARY_H) diff --git a/gold/common.cc b/gold/common.cc new file mode 100644 -index 0000000..b0c7d6e +index 0000000..739c890 --- /dev/null +++ b/gold/common.cc -@@ -0,0 +1,365 @@ +@@ -0,0 +1,364 @@ +// common.cc -- handle common symbols for gold + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2012 -+// Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2310961,13 +2321584,13 @@ index 0000000..b0c7d6e +} // End namespace gold. diff --git a/gold/common.h b/gold/common.h new file mode 100644 -index 0000000..4de585c +index 0000000..20c37ab --- /dev/null +++ b/gold/common.h @@ -0,0 +1,67 @@ +// common.h -- handle common symbols for gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008, 2010 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2311034,13 +2321657,13 @@ index 0000000..4de585c +#endif // !defined(GOLD_COMMON_H) diff --git a/gold/compressed_output.cc b/gold/compressed_output.cc new file mode 100644 -index 0000000..9c7c7dd +index 0000000..19a7f63 --- /dev/null +++ b/gold/compressed_output.cc @@ -0,0 +1,247 @@ +// compressed_output.cc -- manage compressed debug sections for gold + -+// Copyright 2007, 2008, 2010 Free Software Foundation, Inc. ++// Copyright (C) 2007-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2311287,13 +2321910,13 @@ index 0000000..9c7c7dd +} // End namespace gold. diff --git a/gold/compressed_output.h b/gold/compressed_output.h new file mode 100644 -index 0000000..2d6ebd9 +index 0000000..96a4baf --- /dev/null +++ b/gold/compressed_output.h @@ -0,0 +1,86 @@ +// compressed_output.h -- compressed output sections for gold -*- C++ -*- + -+// Copyright 2007, 2008, 2010 Free Software Foundation, Inc. ++// Copyright (C) 2007-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2311668,10 +2322291,10 @@ index 0000000..be77810 +#undef _POSIX_SOURCE diff --git a/gold/configure b/gold/configure new file mode 100755 -index 0000000..2257324 +index 0000000..6f53b22 --- /dev/null +++ b/gold/configure -@@ -0,0 +1,9267 @@ +@@ -0,0 +1,9298 @@ +#! /bin/sh +# Guess values for system-dependent variables and create Makefiles. +# Generated by GNU Autoconf 2.64 for gold 0.1. @@ -2312268,10 +2322891,12 @@ index 0000000..2257324 +MAINT +MAINTAINER_MODE_FALSE +MAINTAINER_MODE_TRUE -+HAVE_PUBNAMES_FALSE -+HAVE_PUBNAMES_TRUE +DLOPEN_LIBS +CXXCPP ++HAVE_NO_USE_LINKER_PLUGIN_FALSE ++HAVE_NO_USE_LINKER_PLUGIN_TRUE ++HAVE_PUBNAMES_FALSE ++HAVE_PUBNAMES_TRUE +HAVE_ZLIB_FALSE +HAVE_ZLIB_TRUE +LIBOBJS @@ -2318302,6 +2328927,9 @@ index 0000000..2257324 + + + ++# Set the 'development' global. ++. $srcdir/../bfd/development.sh ++ +GCC_WARN_CFLAGS="-W -Wall -Wstrict-prototypes -Wmissing-prototypes" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ @@ -2318336,8 +2328964,8 @@ index 0000000..2257324 + *) ;; +esac + -+# Enable -Werror by default when using gcc -+if test "${GCC}" = yes -a -z "${ERROR_ON_WARNING}" ; then ++# Enable -Werror by default when using gcc. Turn it off for releases. ++if test "${GCC}" = yes -a -z "${ERROR_ON_WARNING}" -a "$development" = true ; then + ERROR_ON_WARNING=yes +fi + @@ -2318665,6 +2329293,50 @@ index 0000000..2257324 +_ACEOF + + ++save_CFLAGS="$CFLAGS" ++CFLAGS="$CFLAGS -Werror -gpubnames" ++cat confdefs.h - <<_ACEOF >conftest.$ac_ext ++/* end confdefs.h. */ ++int i; ++_ACEOF ++if ac_fn_c_try_compile "$LINENO"; then : ++ have_pubnames=yes ++else ++ have_pubnames=no ++fi ++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext ++CFLAGS="$save_CFLAGS" ++ if test "$have_pubnames" = "yes"; then ++ HAVE_PUBNAMES_TRUE= ++ HAVE_PUBNAMES_FALSE='#' ++else ++ HAVE_PUBNAMES_TRUE='#' ++ HAVE_PUBNAMES_FALSE= ++fi ++ ++ ++save_CFLAGS="$CFLAGS" ++CFLAGS="$CFLAGS -Werror -fno-use-linker-plugin" ++cat confdefs.h - <<_ACEOF >conftest.$ac_ext ++/* end confdefs.h. */ ++int i; ++_ACEOF ++if ac_fn_c_try_compile "$LINENO"; then : ++ have_no_use_linker_plugin=yes ++else ++ have_no_use_linker_plugin=no ++fi ++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext ++CFLAGS="$save_CFLAGS" ++ if test "$have_no_use_linker_plugin" = "yes"; then ++ HAVE_NO_USE_LINKER_PLUGIN_TRUE= ++ HAVE_NO_USE_LINKER_PLUGIN_FALSE='#' ++else ++ HAVE_NO_USE_LINKER_PLUGIN_TRUE='#' ++ HAVE_NO_USE_LINKER_PLUGIN_FALSE= ++fi ++ ++ +ac_ext=cpp +ac_cpp='$CXXCPP $CPPFLAGS' +ac_compile='$CXX -c $CXXFLAGS $CPPFLAGS conftest.$ac_ext >&5' @@ -2319189,28 +2329861,6 @@ index 0000000..2257324 + +fi + -+save_CXXFLAGS="$CXXFLAGS" -+CXXFLAGS="$CXXFLAGS -Werror -gpubnames" -+cat confdefs.h - <<_ACEOF >conftest.$ac_ext -+/* end confdefs.h. */ -+int i; -+_ACEOF -+if ac_fn_cxx_try_compile "$LINENO"; then : -+ have_pubnames=yes -+else -+ have_pubnames=no -+fi -+rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext -+CXXFLAGS="$save_CXXFLAGS" -+ if test "$have_pubnames" = "yes"; then -+ HAVE_PUBNAMES_TRUE= -+ HAVE_PUBNAMES_FALSE='#' -+else -+ HAVE_PUBNAMES_TRUE='#' -+ HAVE_PUBNAMES_FALSE= -+fi -+ -+ +ac_ext=c +ac_cpp='$CPP $CPPFLAGS' +ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' @@ -2319511,6 +2330161,10 @@ index 0000000..2257324 + as_fn_error "conditional \"HAVE_PUBNAMES\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 +fi ++if test -z "${HAVE_NO_USE_LINKER_PLUGIN_TRUE}" && test -z "${HAVE_NO_USE_LINKER_PLUGIN_FALSE}"; then ++ as_fn_error "conditional \"HAVE_NO_USE_LINKER_PLUGIN\" was never defined. ++Usually this means the macro was only invoked conditionally." "$LINENO" 5 ++fi +if test -z "${MAINTAINER_MODE_TRUE}" && test -z "${MAINTAINER_MODE_FALSE}"; then + as_fn_error "conditional \"MAINTAINER_MODE\" was never defined. +Usually this means the macro was only invoked conditionally." "$LINENO" 5 @@ -2320941,14 +2331595,13 @@ index 0000000..2257324 + diff --git a/gold/configure.ac b/gold/configure.ac new file mode 100644 -index 0000000..b2741cf +index 0000000..7ad7302 --- /dev/null +++ b/gold/configure.ac -@@ -0,0 +1,625 @@ +@@ -0,0 +1,631 @@ +dnl Process this file with autoconf to produce a configure script. +dnl -+dnl Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 -+dnl Free Software Foundation, Inc. ++dnl Copyright (C) 2006-2014 Free Software Foundation, Inc. +dnl +dnl This file is free software; you can redistribute it and/or modify +dnl it under the terms of the GNU General Public License as published by @@ -2321468,6 +2332121,25 @@ index 0000000..b2741cf +dnl with C++. +AC_CHECK_DECLS([basename, ffs, asprintf, vasprintf, snprintf, vsnprintf, strverscmp]) + ++dnl Check if gcc supports the -gpubnames option. ++dnl Use -Werror in case of compilers that make unknown -g options warnings. ++dnl They would pass the test here, but fail in actual use when $WARN_CFLAGS ++dnl gets set later by default Autoconf magic to include -Werror. (We are ++dnl assuming here that there is no compiler that groks -gpubnames ++dnl but does not grok -Werror.) ++save_CFLAGS="$CFLAGS" ++CFLAGS="$CFLAGS -Werror -gpubnames" ++AC_COMPILE_IFELSE([int i;], [have_pubnames=yes], [have_pubnames=no]) ++CFLAGS="$save_CFLAGS" ++AM_CONDITIONAL(HAVE_PUBNAMES, test "$have_pubnames" = "yes") ++ ++dnl Check if gcc supports the -fno-use-linker-plugin option. ++save_CFLAGS="$CFLAGS" ++CFLAGS="$CFLAGS -Werror -fno-use-linker-plugin" ++AC_COMPILE_IFELSE([int i;], [have_no_use_linker_plugin=yes], [have_no_use_linker_plugin=no]) ++CFLAGS="$save_CFLAGS" ++AM_CONDITIONAL(HAVE_NO_USE_LINKER_PLUGIN, test "$have_no_use_linker_plugin" = "yes") ++ +AC_LANG_PUSH(C++) + +AC_CHECK_HEADERS(unordered_set unordered_map) @@ -2321549,18 +2332221,6 @@ index 0000000..b2741cf + [Define if struct stat has a field st_mtim with timespec for mtime]) +fi + -+dnl Check if gcc supports the -gpubnames option. -+dnl Use -Werror in case of compilers that make unknown -g options warnings. -+dnl They would pass the test here, but fail in actual use when $WARN_CFLAGS -+dnl gets set later by default Autoconf magic to include -Werror. (We are -+dnl assuming here that there is no compiler that groks -gpubnames -+dnl but does not grok -Werror.) -+save_CXXFLAGS="$CXXFLAGS" -+CXXFLAGS="$CXXFLAGS -Werror -gpubnames" -+AC_COMPILE_IFELSE([int i;], [have_pubnames=yes], [have_pubnames=no]) -+CXXFLAGS="$save_CXXFLAGS" -+AM_CONDITIONAL(HAVE_PUBNAMES, test "$have_pubnames" = "yes") -+ +AC_LANG_POP(C++) + +AC_CHECK_HEADERS(locale.h) @@ -2321572,13 +2332232,13 @@ index 0000000..b2741cf +AC_OUTPUT(Makefile testsuite/Makefile po/Makefile.in:po/Make-in) diff --git a/gold/configure.tgt b/gold/configure.tgt new file mode 100644 -index 0000000..d61647e +index 0000000..aad4f54 --- /dev/null +++ b/gold/configure.tgt @@ -0,0 +1,150 @@ +# configure.tgt -- target configuration for gold -*- sh -*- + -+# Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc. ++# Copyright (C) 2006-2014 Free Software Foundation, Inc. +# Written by Ian Lance Taylor . + +# This file is part of gold. @@ -2321728,13 +2332388,13 @@ index 0000000..d61647e +esac diff --git a/gold/copy-relocs.cc b/gold/copy-relocs.cc new file mode 100644 -index 0000000..92c5aea +index 0000000..41b6563 --- /dev/null +++ b/gold/copy-relocs.cc -@@ -0,0 +1,258 @@ +@@ -0,0 +1,250 @@ +// copy-relocs.cc -- handle COPY relocations for gold. + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2321762,25 +2332422,6 @@ index 0000000..92c5aea +namespace gold +{ + -+// Copy_relocs::Copy_reloc_entry methods. -+ -+// Emit the reloc if appropriate. -+ -+template -+void -+Copy_relocs::Copy_reloc_entry::emit( -+ Output_data_reloc* reloc_section) -+{ -+ // If the symbol is no longer defined in a dynamic object, then we -+ // emitted a COPY relocation, and we do not want to emit this -+ // dynamic relocation. -+ if (this->sym_->is_from_dynobj()) -+ reloc_section->add_global_generic(this->sym_, this->reloc_type_, -+ this->output_section_, this->relobj_, -+ this->shndx_, this->address_, -+ this->addend_); -+} -+ +// Copy_relocs methods. + +// Handle a relocation against a symbol which may force us to generate @@ -2321949,7 +2332590,18 @@ index 0000000..92c5aea + for (typename Copy_reloc_entries::iterator p = this->entries_.begin(); + p != this->entries_.end(); + ++p) -+ p->emit(reloc_section); ++ { ++ Copy_reloc_entry& entry = *p; ++ ++ // If the symbol is no longer defined in a dynamic object, then we ++ // emitted a COPY relocation, and we do not want to emit this ++ // dynamic relocation. ++ if (entry.sym_->is_from_dynobj()) ++ reloc_section->add_global_generic(entry.sym_, entry.reloc_type_, ++ entry.output_section_, entry.relobj_, ++ entry.shndx_, entry.address_, ++ entry.addend_); ++ } + + // We no longer need the saved information. + this->entries_.clear(); @@ -2321992,13 +2332644,13 @@ index 0000000..92c5aea +} // End namespace gold. diff --git a/gold/copy-relocs.h b/gold/copy-relocs.h new file mode 100644 -index 0000000..d1e2323 +index 0000000..800c0e7 --- /dev/null +++ b/gold/copy-relocs.h -@@ -0,0 +1,156 @@ +@@ -0,0 +1,150 @@ +// copy-relocs.h -- handle COPY relocations for gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2322052,7 +2332704,7 @@ index 0000000..d1e2323 + + public: + Copy_relocs(unsigned int copy_reloc_type) -+ : copy_reloc_type_(copy_reloc_type), dynbss_(NULL), entries_() ++ : entries_(), copy_reloc_type_(copy_reloc_type), dynbss_(NULL) + { } + + // This is called while scanning relocs if we see a relocation @@ -2322085,16 +2332737,15 @@ index 0000000..d1e2323 + Output_data*, off_t, + Output_data_reloc*); + -+ private: ++ protected: + typedef typename elfcpp::Elf_types::Elf_Addr Address; + typedef typename elfcpp::Elf_types::Elf_Addr Addend; + + // This POD class holds the relocations we are saving. We will emit + // these relocations if it turns out that the symbol does not + // require a COPY relocation. -+ class Copy_reloc_entry ++ struct Copy_reloc_entry + { -+ public: + Copy_reloc_entry(Symbol* sym, unsigned int reloc_type, + Sized_relobj_file* relobj, + unsigned int shndx, @@ -2322105,13 +2332756,6 @@ index 0000000..d1e2323 + address_(address), addend_(addend) + { } + -+ // Emit this reloc if appropriate. This is called after we have -+ // scanned all the relocations, so we know whether we emitted a -+ // COPY relocation for SYM_. -+ void -+ emit(Output_data_reloc*); -+ -+ private: + Symbol* sym_; + unsigned int reloc_type_; + Sized_relobj_file* relobj_; @@ -2322121,20 +2332765,24 @@ index 0000000..d1e2323 + Addend addend_; + }; + ++ // Make a new COPY reloc and emit it. ++ void ++ make_copy_reloc(Symbol_table*, Layout*, Sized_symbol*, ++ Output_data_reloc*); ++ + // A list of relocs to be saved. + typedef std::vector Copy_reloc_entries; + ++ // The list of relocs we are saving. ++ Copy_reloc_entries entries_; ++ ++ private: + // Return whether we need a COPY reloc. + bool + need_copy_reloc(Sized_symbol* gsym, + Sized_relobj_file* object, + unsigned int shndx) const; + -+ // Make a new COPY reloc and emit it. -+ void -+ make_copy_reloc(Symbol_table*, Layout*, Sized_symbol*, -+ Output_data_reloc*); -+ + // Save a reloc against SYM for possible emission later. + void + save(Symbol*, Sized_relobj_file*, unsigned int shndx, @@ -2322145,8 +2332793,6 @@ index 0000000..d1e2323 + // The dynamic BSS data which goes into the .bss section. This is + // where variables which require COPY relocations are placed. + Output_data_space* dynbss_; -+ // The list of relocs we are saving. -+ Copy_reloc_entries entries_; +}; + +} // End namespace gold. @@ -2322154,13 +2332800,13 @@ index 0000000..d1e2323 +#endif // !defined(GOLD_COPY_RELOCS_H) diff --git a/gold/cref.cc b/gold/cref.cc new file mode 100644 -index 0000000..ebd48a9 +index 0000000..ac6f1c8 --- /dev/null +++ b/gold/cref.cc @@ -0,0 +1,407 @@ +// cref.cc -- cross reference for gold + -+// Copyright 2008, 2010 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2322567,13 +2333213,13 @@ index 0000000..ebd48a9 +} // End namespace gold. diff --git a/gold/cref.h b/gold/cref.h new file mode 100644 -index 0000000..a40a34a +index 0000000..0e72d16 --- /dev/null +++ b/gold/cref.h @@ -0,0 +1,79 @@ +// cref.h -- cross reference reports for gold -*- C++ -*- + -+// Copyright 2008, 2010 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2322652,13 +2333298,13 @@ index 0000000..a40a34a +#endif // !defined(GOLD_CREF_H) diff --git a/gold/debug.h b/gold/debug.h new file mode 100644 -index 0000000..7fdbee7 +index 0000000..63d3d8a --- /dev/null +++ b/gold/debug.h @@ -0,0 +1,80 @@ +// debug.h -- gold internal debugging support -*- C++ -*- + -+// Copyright 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2007-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2322738,13 +2333384,13 @@ index 0000000..7fdbee7 +#endif // !defined(GOLD_DEBUG_H) diff --git a/gold/defstd.cc b/gold/defstd.cc new file mode 100644 -index 0000000..a7a57e4 +index 0000000..cee68a0 --- /dev/null +++ b/gold/defstd.cc -@@ -0,0 +1,274 @@ +@@ -0,0 +1,288 @@ +// defstd.cc -- define standard symbols for gold. + -+// Copyright 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2322885,6 +2333531,20 @@ index 0000000..a7a57e4 + true // only_if_ref + }, + { ++ "__ehdr_start", // name ++ elfcpp::PT_LOAD, // segment_type ++ elfcpp::PF(0), // segment_flags_set ++ elfcpp::PF(0), // segment_flags_clear ++ 0, // value ++ 0, // size ++ elfcpp::STT_NOTYPE, // type ++ elfcpp::STB_GLOBAL, // binding ++ elfcpp::STV_HIDDEN, // visibility ++ 0, // nonvis ++ Symbol::SEGMENT_START, // offset_from_base ++ true // only_if_ref ++ }, ++ { + "etext", // name + elfcpp::PT_LOAD, // segment_type + elfcpp::PF_X, // segment_flags_set @@ -2323018,13 +2333678,13 @@ index 0000000..a7a57e4 +} // End namespace gold. diff --git a/gold/defstd.h b/gold/defstd.h new file mode 100644 -index 0000000..2aea81c +index 0000000..853a1e8 --- /dev/null +++ b/gold/defstd.h @@ -0,0 +1,36 @@ +// defstd.h -- define standard symbols for gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2323060,13 +2333720,13 @@ index 0000000..2aea81c +#endif // !defined(GOLD_DEFSTD_H) diff --git a/gold/descriptors.cc b/gold/descriptors.cc new file mode 100644 -index 0000000..b7fbaa6 +index 0000000..2016b7f --- /dev/null +++ b/gold/descriptors.cc @@ -0,0 +1,280 @@ +// descriptors.cc -- manage file descriptors for gold + -+// Copyright 2008, 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2323346,13 +2334006,13 @@ index 0000000..b7fbaa6 +} // End namespace gold. diff --git a/gold/descriptors.h b/gold/descriptors.h new file mode 100644 -index 0000000..985f804 +index 0000000..c14ac07 --- /dev/null +++ b/gold/descriptors.h @@ -0,0 +1,117 @@ +// descriptors.h -- manage file descriptors for gold -*- C++ -*- + -+// Copyright 2008, 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2323469,13 +2334129,13 @@ index 0000000..985f804 +#endif // !defined(GOLD_DESCRIPTORS_H) diff --git a/gold/dirsearch.cc b/gold/dirsearch.cc new file mode 100644 -index 0000000..a6114a4 +index 0000000..e9e2fa1 --- /dev/null +++ b/gold/dirsearch.cc @@ -0,0 +1,305 @@ +// dirsearch.cc -- directory searching for gold + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2323780,13 +2334440,13 @@ index 0000000..a6114a4 +} // End namespace gold. diff --git a/gold/dirsearch.h b/gold/dirsearch.h new file mode 100644 -index 0000000..ebc0b5b +index 0000000..d020d94 --- /dev/null +++ b/gold/dirsearch.h @@ -0,0 +1,90 @@ +// dirsearch.h -- directory searching for gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2323876,13 +2334536,13 @@ index 0000000..ebc0b5b +#endif // !defined(GOLD_DIRSEARCH_H) diff --git a/gold/dwarf_reader.cc b/gold/dwarf_reader.cc new file mode 100644 -index 0000000..3aad27f +index 0000000..30aea10 --- /dev/null +++ b/gold/dwarf_reader.cc -@@ -0,0 +1,2374 @@ +@@ -0,0 +1,2396 @@ +// dwarf_reader.cc -- parse dwarf2/3 debug information + -+// Copyright 2007, 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc. ++// Copyright (C) 2007-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2323905,6 +2334565,7 @@ index 0000000..3aad27f +#include "gold.h" + +#include ++#include +#include + +#include "elfcpp_swap.h" @@ -2324062,7 +2334723,7 @@ index 0000000..3aad27f + for (unsigned int i = 1; i < object->shnum(); ++i) + { + std::string name = object->section_name(i); -+ if (name == ".debug_abbrev") ++ if (name == ".debug_abbrev" || name == ".zdebug_abbrev") + { + abbrev_shndx = i; + // Correct the offset. For incremental update links, we have a @@ -2324199,7 +2334860,7 @@ index 0000000..3aad27f + for (unsigned int i = 1; i < object->shnum(); ++i) + { + std::string name = object->section_name(i); -+ if (name == ".debug_ranges") ++ if (name == ".debug_ranges" || name == ".zdebug_ranges") + { + ranges_shndx = i; + this->output_section_offset_ = object->output_section_offset(i); @@ -2324368,24 +2335029,36 @@ index 0000000..3aad27f +{ + section_size_type buffer_size; + unsigned int shndx = 0; ++ const char* name = this->is_pubtypes_ ? "pubtypes" : "pubnames"; ++ const char* gnu_name = (this->is_pubtypes_ ++ ? "gnu_pubtypes" ++ : "gnu_pubnames"); + -+ // Find the .debug_pubnames/pubtypes section. -+ const char* name = (this->is_pubtypes_ -+ ? ".debug_pubtypes" -+ : ".debug_pubnames"); + for (unsigned int i = 1; i < object->shnum(); ++i) + { -+ if (object->section_name(i) == name) ++ std::string section_name = object->section_name(i); ++ const char* section_name_suffix = section_name.c_str(); ++ if (is_prefix_of(".debug_", section_name_suffix)) ++ section_name_suffix += 7; ++ else if (is_prefix_of(".zdebug_", section_name_suffix)) ++ section_name_suffix += 8; ++ else ++ continue; ++ if (strcmp(section_name_suffix, name) == 0) + { + shndx = i; -+ this->output_section_offset_ = object->output_section_offset(i); ++ break; ++ } ++ else if (strcmp(section_name_suffix, gnu_name) == 0) ++ { ++ shndx = i; ++ this->is_gnu_style_ = true; + break; + } + } + if (shndx == 0) + return false; + -+ + this->buffer_ = object->decompressed_section_contents(shndx, + &buffer_size, + &this->owns_buffer_); @@ -2324427,11 +2335100,6 @@ index 0000000..3aad27f + // Make sure we have actually read the section. + gold_assert(this->buffer_ != NULL); + -+ // Correct the offset. For incremental update links, we have a -+ // relocated offset that is relative to the output section, but -+ // here we need an offset relative to the input section. -+ offset -= this->output_section_offset_; -+ + if (offset < 0 || offset + 14 >= this->buffer_end_ - this->buffer_) + return false; + @@ -2324452,6 +2335120,13 @@ index 0000000..3aad27f + this->unit_length_ = unit_length + 4; + this->offset_size_ = 4; + } ++ this->end_of_table_ = pinfo + unit_length; ++ ++ // If unit_length is too big, maybe we should reject the whole table, ++ // but in cases we know about, it seems OK to assume that the table ++ // is valid through the actual end of the section. ++ if (this->end_of_table_ > this->buffer_end_) ++ this->end_of_table_ = this->buffer_end_; + + // Check the version. + unsigned int version = this->dwinfo_->read_from_pointer<16>(pinfo); @@ -2324475,20 +2335150,27 @@ index 0000000..3aad27f +// Read the next name from the set. + +const char* -+Dwarf_pubnames_table::next_name() ++Dwarf_pubnames_table::next_name(uint8_t* flag_byte) +{ + const unsigned char* pinfo = this->pinfo_; + -+ // Read the offset within the CU. If this is zero, we have reached -+ // the end of the list. -+ uint32_t offset; -+ if (this->offset_size_ == 4) -+ offset = this->dwinfo_->read_from_pointer<32>(&pinfo); -+ else -+ offset = this->dwinfo_->read_from_pointer<64>(&pinfo); -+ if (offset == 0) ++ // Check for end of list. The table should be terminated by an ++ // entry containing nothing but a DIE offset of 0. ++ if (pinfo + this->offset_size_ >= this->end_of_table_) + return NULL; + ++ // Skip the offset within the CU. If this is zero, but we're not ++ // at the end of the table, then we have a real pubnames entry ++ // whose DIE offset is 0 (likely to be a GCC bug). Since we ++ // don't actually use the DIE offset in building .gdb_index, ++ // it's harmless. ++ pinfo += this->offset_size_; ++ ++ if (this->is_gnu_style_) ++ *flag_byte = *pinfo++; ++ else ++ *flag_byte = 0; ++ + // Return a pointer to the string at the current location, + // and advance the pointer to the next entry. + const char* ret = reinterpret_cast(pinfo); @@ -2325248,7 +2335930,7 @@ index 0000000..3aad27f + for (unsigned int i = 1; i < this->object_->shnum(); ++i) + { + std::string name = object->section_name(i); -+ if (name == ".debug_str") ++ if (name == ".debug_str" || name == ".zdebug_str") + { + string_shndx = i; + this->string_output_section_offset_ = @@ -2326256,14 +2336938,13 @@ index 0000000..3aad27f +} // End namespace gold. diff --git a/gold/dwarf_reader.h b/gold/dwarf_reader.h new file mode 100644 -index 0000000..bbd9667 +index 0000000..cac413b --- /dev/null +++ b/gold/dwarf_reader.h -@@ -0,0 +1,1117 @@ +@@ -0,0 +1,1118 @@ +// dwarf_reader.h -- parse dwarf2/3 debug information for gold -*- C++ -*- + -+// Copyright 2007, 2008, 2009, 2010, 2011, 2012, 2013 -+// Free Software Foundation, Inc. ++// Copyright (C) 2007-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2326662,8 +2337343,9 @@ index 0000000..bbd9667 + public: + Dwarf_pubnames_table(Dwarf_info_reader* dwinfo, bool is_pubtypes) + : dwinfo_(dwinfo), buffer_(NULL), buffer_end_(NULL), owns_buffer_(false), -+ offset_size_(0), pinfo_(NULL), is_pubtypes_(is_pubtypes), -+ output_section_offset_(0), unit_length_(0), cu_offset_(0) ++ offset_size_(0), pinfo_(NULL), end_of_table_(NULL), ++ is_pubtypes_(is_pubtypes), is_gnu_style_(false), ++ unit_length_(0), cu_offset_(0) + { } + + ~Dwarf_pubnames_table() @@ -2326693,9 +2337375,10 @@ index 0000000..bbd9667 + subsection_size() + { return this->unit_length_; } + -+ // Read the next name from the set. ++ // Read the next name from the set. If the pubname table is gnu-style, ++ // FLAG_BYTE is set to the high-byte of a gdb_index version 7 cu_index. + const char* -+ next_name(); ++ next_name(uint8_t* flag_byte); + + private: + // The Dwarf_info_reader, for reading data. @@ -2326709,13 +2337392,13 @@ index 0000000..bbd9667 + unsigned int offset_size_; + // The current position within the buffer. + const unsigned char* pinfo_; ++ // The end of the current pubnames table. ++ const unsigned char* end_of_table_; + // TRUE if this is a .debug_pubtypes section. + bool is_pubtypes_; -+ // For incremental update links, this will hold the offset of the -+ // input section within the output section. Offsets read from -+ // relocated data will be relative to the output section, and need -+ // to be corrected before reading data from the input section. -+ uint64_t output_section_offset_; ++ // Gnu-style pubnames table. This style has an extra flag byte between the ++ // offset and the name, and is used for generating version 7 of gdb-index. ++ bool is_gnu_style_; + // Fields read from the header. + uint64_t unit_length_; + off_t cu_offset_; @@ -2327379,13 +2338062,13 @@ index 0000000..bbd9667 +#endif // !defined(GOLD_DWARF_READER_H) diff --git a/gold/dwp.cc b/gold/dwp.cc new file mode 100644 -index 0000000..04a1447 +index 0000000..6fe5c79 --- /dev/null +++ b/gold/dwp.cc @@ -0,0 +1,2464 @@ +// dwp.cc -- DWARF packaging utility + -+// Copyright 2012 Free Software Foundation, Inc. ++// Copyright (C) 2012-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of dwp, the DWARF packaging utility. @@ -2329732,7 +2340415,7 @@ index 0000000..04a1447 +{ + // This output is intended to follow the GNU standards. + printf("GNU dwp %s\n", BFD_VERSION_STRING); -+ printf(_("Copyright 2012 Free Software Foundation, Inc.\n")); ++ printf(_("Copyright (C) 2014 Free Software Foundation, Inc.\n")); + printf(_("\ +This program is free software; you may redistribute it under the terms of\n\ +the GNU General Public License version 3 or (at your option) any later version.\n\ @@ -2329849,13 +2340532,13 @@ index 0000000..04a1447 +} diff --git a/gold/dwp.h b/gold/dwp.h new file mode 100644 -index 0000000..948c6a9 +index 0000000..6b57eaa --- /dev/null +++ b/gold/dwp.h @@ -0,0 +1,124 @@ +// dwp.h -- general definitions for dwp. + -+// Copyright 2012 Free Software Foundation, Inc. ++// Copyright (C) 2012-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of dwp, the DWARF packaging utility. @@ -2329979,13 +2340662,13 @@ index 0000000..948c6a9 +#endif // !defined(DWP_DWP_H) diff --git a/gold/dynobj.cc b/gold/dynobj.cc new file mode 100644 -index 0000000..ac0c321 +index 0000000..2a1b9a3 --- /dev/null +++ b/gold/dynobj.cc @@ -0,0 +1,1970 @@ +// dynobj.cc -- dynamic object support for gold + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2331955,13 +2342638,13 @@ index 0000000..ac0c321 +} // End namespace gold. diff --git a/gold/dynobj.h b/gold/dynobj.h new file mode 100644 -index 0000000..e027485 +index 0000000..b8d4b90 --- /dev/null +++ b/gold/dynobj.h @@ -0,0 +1,672 @@ +// dynobj.h -- dynamic object support for gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2332633,13 +2343316,13 @@ index 0000000..e027485 +#endif // !defined(GOLD_DYNOBJ_H) diff --git a/gold/ehframe.cc b/gold/ehframe.cc new file mode 100644 -index 0000000..08a9ec6 +index 0000000..699073d --- /dev/null +++ b/gold/ehframe.cc @@ -0,0 +1,1263 @@ +// ehframe.cc -- handle exception frame sections for gold + -+// Copyright 2006, 2007, 2008, 2010, 2011, 2012 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2333902,13 +2344585,13 @@ index 0000000..08a9ec6 +} // End namespace gold. diff --git a/gold/ehframe.h b/gold/ehframe.h new file mode 100644 -index 0000000..8aab8b8 +index 0000000..42ed7f6 --- /dev/null +++ b/gold/ehframe.h @@ -0,0 +1,517 @@ +// ehframe.h -- handle exception frame sections for gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008, 2010, 2011 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2334425,13 +2345108,13 @@ index 0000000..8aab8b8 +#endif // !defined(GOLD_EHFRAME_H) diff --git a/gold/errors.cc b/gold/errors.cc new file mode 100644 -index 0000000..b79764b +index 0000000..8339742 --- /dev/null +++ b/gold/errors.cc -@@ -0,0 +1,420 @@ +@@ -0,0 +1,425 @@ +// errors.cc -- handle errors for gold + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2334624,6 +2345307,11 @@ index 0000000..b79764b + fprintf(stderr, + _("%s: %s: undefined reference to '%s', version '%s'\n"), + location.c_str(), zmsg, sym->demangled_name().c_str(), version); ++ ++ if (sym->is_cxx_vtable()) ++ gold_info(_("%s: the vtable symbol may be undefined because " ++ "the class is missing its key function"), ++ program_name); +} + +// Issue a debugging message. @@ -2334851,13 +2345539,13 @@ index 0000000..b79764b +} // End namespace gold. diff --git a/gold/errors.h b/gold/errors.h new file mode 100644 -index 0000000..1e61c8d +index 0000000..ea8f992 --- /dev/null +++ b/gold/errors.h @@ -0,0 +1,138 @@ +// errors.h -- handle errors for gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2334995,13 +2345683,13 @@ index 0000000..1e61c8d +#endif // !defined(GOLD_ERRORS_H) diff --git a/gold/expression.cc b/gold/expression.cc new file mode 100644 -index 0000000..e31c151 +index 0000000..bdf52fa --- /dev/null +++ b/gold/expression.cc @@ -0,0 +1,1273 @@ +// expression.cc -- expressions in linker scripts for gold + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2336274,13 +2346962,13 @@ index 0000000..e31c151 +} // End namespace gold. diff --git a/gold/ffsll.c b/gold/ffsll.c new file mode 100644 -index 0000000..b247bc3 +index 0000000..292ad80 --- /dev/null +++ b/gold/ffsll.c @@ -0,0 +1,48 @@ +/* ffsll.c -- version of ffsll for gold. */ + -+/* Copyright 2009 Free Software Foundation, Inc. ++/* Copyright (C) 2009-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor . + + This file is part of gold. @@ -2336328,14 +2347016,13 @@ index 0000000..b247bc3 +} diff --git a/gold/fileread.cc b/gold/fileread.cc new file mode 100644 -index 0000000..743a1cd +index 0000000..8c46a1f --- /dev/null +++ b/gold/fileread.cc -@@ -0,0 +1,1140 @@ +@@ -0,0 +1,1139 @@ +// fileread.cc -- read files for gold + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2012 -+// Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2337474,13 +2348161,13 @@ index 0000000..743a1cd +} // End namespace gold. diff --git a/gold/fileread.h b/gold/fileread.h new file mode 100644 -index 0000000..74aeec9 +index 0000000..d64f18a --- /dev/null +++ b/gold/fileread.h @@ -0,0 +1,611 @@ +// fileread.h -- read files for gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2338091,13 +2348778,13 @@ index 0000000..74aeec9 +#endif // !defined(GOLD_FILEREAD_H) diff --git a/gold/freebsd.h b/gold/freebsd.h new file mode 100644 -index 0000000..3bdedce +index 0000000..737da90 --- /dev/null +++ b/gold/freebsd.h @@ -0,0 +1,103 @@ +// freebsd.h -- FreeBSD support for gold -*- C++ -*- + -+// Copyright 2009, 2011, 2012 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2338200,14 +2348887,14 @@ index 0000000..3bdedce +#endif // !defined(GOLD_FREEBSD_H) diff --git a/gold/ftruncate.c b/gold/ftruncate.c new file mode 100644 -index 0000000..102fcd1 +index 0000000..00f357f --- /dev/null +++ b/gold/ftruncate.c @@ -0,0 +1,111 @@ +/* ftruncate emulations that work on some System V's. + This file is in the public domain. */ + -+/* Copyright 2012 Free Software Foundation, Inc. ++/* Copyright (C) 2012-2014 Free Software Foundation, Inc. + + This file is part of gold. + @@ -2338317,13 +2349004,13 @@ index 0000000..102fcd1 +#endif /* not F_CHSIZE */ diff --git a/gold/gc.cc b/gold/gc.cc new file mode 100644 -index 0000000..7a594a5 +index 0000000..4759c00 --- /dev/null +++ b/gold/gc.cc @@ -0,0 +1,74 @@ +// gc.cc -- garbage collection of unused sections + -+// Copyright 2009 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Sriraman Tallam . + +// This file is part of gold. @@ -2338397,13 +2349084,13 @@ index 0000000..7a594a5 + diff --git a/gold/gc.h b/gold/gc.h new file mode 100644 -index 0000000..4224a66 +index 0000000..2f79a24 --- /dev/null +++ b/gold/gc.h @@ -0,0 +1,383 @@ +// gc.h -- garbage collection of unused sections + -+// Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Sriraman Tallam . + +// This file is part of gold. @@ -2338786,13 +2349473,13 @@ index 0000000..4224a66 +#endif diff --git a/gold/gdb-index.cc b/gold/gdb-index.cc new file mode 100644 -index 0000000..d42fbbd +index 0000000..f768827 --- /dev/null +++ b/gold/gdb-index.cc -@@ -0,0 +1,1344 @@ +@@ -0,0 +1,1357 @@ +// gdb-index.cc -- generate .gdb_index section for fast debug lookup + -+// Copyright 2012 Free Software Foundation, Inc. ++// Copyright (C) 2012-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2338824,7 +2349511,7 @@ index 0000000..d42fbbd +namespace gold +{ + -+const int gdb_index_version = 5; ++const int gdb_index_version = 7; + +// Sizes of various records in the .gdb_index section. +const int gdb_index_offset_size = 4; @@ -2339149,20 +2349836,6 @@ index 0000000..d42fbbd + case elfcpp::DW_TAG_compile_unit: + case elfcpp::DW_TAG_type_unit: + this->cu_language_ = die->int_attribute(elfcpp::DW_AT_language); -+ // Check for languages that require specialized knowledge to -+ // construct fully-qualified names, that we don't yet support. -+ if (this->cu_language_ == elfcpp::DW_LANG_Ada83 -+ || this->cu_language_ == elfcpp::DW_LANG_Fortran77 -+ || this->cu_language_ == elfcpp::DW_LANG_Fortran90 -+ || this->cu_language_ == elfcpp::DW_LANG_Java -+ || this->cu_language_ == elfcpp::DW_LANG_Ada95 -+ || this->cu_language_ == elfcpp::DW_LANG_Fortran95) -+ { -+ gold_warning(_("%s: --gdb-index currently supports " -+ "only C and C++ languages"), -+ this->object()->name().c_str()); -+ return; -+ } + if (die->tag() == elfcpp::DW_TAG_compile_unit) + this->record_cu_ranges(die); + // If there is a pubnames and/or pubtypes section for this @@ -2339170,6 +2349843,20 @@ index 0000000..d42fbbd + // info to extract the names. + if (!this->read_pubnames_and_pubtypes(die)) + { ++ // Check for languages that require specialized knowledge to ++ // construct fully-qualified names, that we don't yet support. ++ if (this->cu_language_ == elfcpp::DW_LANG_Ada83 ++ || this->cu_language_ == elfcpp::DW_LANG_Fortran77 ++ || this->cu_language_ == elfcpp::DW_LANG_Fortran90 ++ || this->cu_language_ == elfcpp::DW_LANG_Java ++ || this->cu_language_ == elfcpp::DW_LANG_Ada95 ++ || this->cu_language_ == elfcpp::DW_LANG_Fortran95) ++ { ++ gold_warning(_("%s: --gdb-index currently supports " ++ "only C and C++ languages"), ++ this->object()->name().c_str()); ++ return; ++ } + if (die->tag() == elfcpp::DW_TAG_compile_unit) + ++Gdb_index_info_reader::dwarf_cu_nopubnames_count; + else @@ -2339184,7 +2349871,6 @@ index 0000000..d42fbbd + this->object()->name().c_str()); + return; + } -+ +} + +// Visit the children of PARENT, looking for symbols to add to the index. @@ -2339228,7 +2349914,8 @@ index 0000000..d42fbbd + // If the DIE is not a declaration, add it to the index. + std::string full_name = this->get_qualified_name(die, context); + if (!full_name.empty()) -+ this->gdb_index_->add_symbol(this->cu_index_, full_name.c_str()); ++ this->gdb_index_->add_symbol(this->cu_index_, ++ full_name.c_str(), 0); + } + break; + case elfcpp::DW_TAG_typedef: @@ -2339268,7 +2349955,7 @@ index 0000000..d42fbbd + full_name = this->get_qualified_name(die, context); + if (!full_name.empty()) + this->gdb_index_->add_symbol(this->cu_index_, -+ full_name.c_str()); ++ full_name.c_str(), 0); + } + + // We're interested in the children only for namespaces and @@ -2339662,11 +2350349,12 @@ index 0000000..d42fbbd + return false; + while (true) + { -+ const char* name = table->next_name(); ++ uint8_t flag_byte; ++ const char* name = table->next_name(&flag_byte); + if (name == NULL) + break; + -+ this->gdb_index_->add_symbol(this->cu_index_, name); ++ this->gdb_index_->add_symbol(this->cu_index_, name, flag_byte); + } + return true; +} @@ -2339677,6 +2350365,14 @@ index 0000000..d42fbbd +bool +Gdb_index_info_reader::read_pubnames_and_pubtypes(Dwarf_die* die) +{ ++ // If this is a skeleton debug-type die (generated via ++ // -gsplit-dwarf), then the associated pubnames should have been ++ // read along with the corresponding CU. In any case, there isn't ++ // enough info inside to build a gdb index entry. ++ if (die->tag() == elfcpp::DW_TAG_type_unit ++ && die->string_attribute(elfcpp::DW_AT_GNU_dwo_name)) ++ return true; ++ + // We use stmt_list_off as a unique identifier for the + // compilation unit and its associated type units. + unsigned int shndx; @@ -2339904,7 +2350600,7 @@ index 0000000..d42fbbd +// Add a symbol. + +void -+Gdb_index::add_symbol(int cu_index, const char* sym_name) ++Gdb_index::add_symbol(int cu_index, const char* sym_name, uint8_t flags) +{ + unsigned int hash = mapped_index_string_hash( + reinterpret_cast(sym_name)); @@ -2339931,8 +2350627,10 @@ index 0000000..d42fbbd + // if it's not already on the list. We only need to + // check the last added entry. + Cu_vector* cu_vec = this->cu_vector_list_[found->cu_vector_index]; -+ if (cu_vec->size() == 0 || cu_vec->back() != cu_index) -+ cu_vec->push_back(cu_index); ++ if (cu_vec->size() == 0 ++ || cu_vec->back().first != cu_index ++ || cu_vec->back().second != flags) ++ cu_vec->push_back(std::make_pair(cu_index, flags)); +} + +// Return TRUE if we have already processed the pubnames associated @@ -2340109,9 +2350807,11 @@ index 0000000..d42fbbd + pov += 4; + for (unsigned int j = 0; j < cu_vec->size(); ++j) + { -+ int cu_index = (*cu_vec)[j]; ++ int cu_index = (*cu_vec)[j].first; ++ uint8_t flags = (*cu_vec)[j].second; + if (cu_index < 0) + cu_index = comp_units_count + (-1 - cu_index); ++ cu_index |= flags << 24; + elfcpp::Swap<32, false>::writeval(pov, cu_index); + pov += 4; + } @@ -2340136,13 +2350836,13 @@ index 0000000..d42fbbd +} // End namespace gold. diff --git a/gold/gdb-index.h b/gold/gdb-index.h new file mode 100644 -index 0000000..5d9fe47 +index 0000000..97dfc8f --- /dev/null +++ b/gold/gdb-index.h -@@ -0,0 +1,263 @@ +@@ -0,0 +1,264 @@ +// gdb-index.h -- generate .gdb_index section for fast debug lookup -*- C++ -*- + -+// Copyright 2012 Free Software Foundation, Inc. ++// Copyright (C) 2012-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2340231,9 +2350931,10 @@ index 0000000..5d9fe47 + this->ranges_.push_back(Per_cu_range_list(object, cu_index, ranges)); + } + -+ // Add a symbol. ++ // Add a symbol. FLAGS are the gdb_index version 7 flags to be stored in ++ // the high-byte of the cu_index field. + void -+ add_symbol(int cu_index, const char* sym_name); ++ add_symbol(int cu_index, const char* sym_name, uint8_t flags); + + // Return the offset into the pubnames table for the cu at the given + // offset. @@ -2340355,7 +2351056,7 @@ index 0000000..5d9fe47 + { return this->name_key == symbol->name_key; } + }; + -+ typedef std::vector Cu_vector; ++ typedef std::vector > Cu_vector; + + typedef Unordered_map Pubname_offset_map; + Pubname_offset_map cu_pubname_map_; @@ -2340405,13 +2351106,13 @@ index 0000000..5d9fe47 +#endif // !defined(GOLD_GDB_INDEX_H) diff --git a/gold/gold-threads.cc b/gold/gold-threads.cc new file mode 100644 -index 0000000..2cb293e +index 0000000..ebd9c1f --- /dev/null +++ b/gold/gold-threads.cc @@ -0,0 +1,450 @@ +// gold-threads.cc -- thread support for gold + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2013 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2340861,13 +2351562,13 @@ index 0000000..2cb293e +} // End namespace gold. diff --git a/gold/gold-threads.h b/gold/gold-threads.h new file mode 100644 -index 0000000..5751f62 +index 0000000..571cb94 --- /dev/null +++ b/gold/gold-threads.h @@ -0,0 +1,267 @@ +// gold-threads.h -- thread support for gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2013 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2341134,14 +2351835,13 @@ index 0000000..5751f62 +#endif // !defined(GOLD_THREADS_H) diff --git a/gold/gold.cc b/gold/gold.cc new file mode 100644 -index 0000000..4de9289 +index 0000000..4833aec --- /dev/null +++ b/gold/gold.cc -@@ -0,0 +1,888 @@ +@@ -0,0 +1,887 @@ +// gold.cc -- main linker functions + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2012 -+// Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2342028,13 +2352728,13 @@ index 0000000..4de9289 +} // End namespace gold. diff --git a/gold/gold.h b/gold/gold.h new file mode 100644 -index 0000000..ef95f53 +index 0000000..b78a165 --- /dev/null +++ b/gold/gold.h @@ -0,0 +1,313 @@ +// gold.h -- general definitions for gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2342347,14 +2353047,13 @@ index 0000000..ef95f53 +#endif // !defined(GOLD_GOLD_H) diff --git a/gold/i386.cc b/gold/i386.cc new file mode 100644 -index 0000000..6a3280d +index 0000000..d28c444 --- /dev/null +++ b/gold/i386.cc -@@ -0,0 +1,4168 @@ +@@ -0,0 +1,4205 @@ +// i386.cc -- i386 target support for gold. + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 -+// Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2342401,6 +2353100,32 @@ index 0000000..6a3280d + +using namespace gold; + ++// A class to handle the .got.plt section. ++ ++class Output_data_got_plt_i386 : public Output_section_data_build ++{ ++ public: ++ Output_data_got_plt_i386(Layout* layout) ++ : Output_section_data_build(4), ++ layout_(layout) ++ { } ++ ++ protected: ++ // Write out the PLT data. ++ void ++ do_write(Output_file*); ++ ++ // Write to a map file. ++ void ++ do_print_to_mapfile(Mapfile* mapfile) const ++ { mapfile->print_output_data(this, "** GOT PLT"); } ++ ++ private: ++ // A pointer to the Layout class, so that we can find the .dynamic ++ // section when we write out the GOT PLT section. ++ Layout* layout_; ++}; ++ +// A class to handle the PLT data. +// This is an abstract base class that handles most of the linker details +// but does not know the actual contents of PLT entries. The derived @@ -2342412,7 +2353137,7 @@ index 0000000..6a3280d + typedef Output_data_reloc Reloc_section; + + Output_data_plt_i386(Layout*, uint64_t addralign, -+ Output_data_space*, Output_data_space*); ++ Output_data_got_plt_i386*, Output_data_space*); + + // Add an entry to the PLT. + void @@ -2342555,9 +2353280,6 @@ index 0000000..6a3280d + unsigned int got_offset; + }; + -+ // A pointer to the Layout class, so that we can find the .dynamic -+ // section when we write out the GOT PLT section. -+ Layout* layout_; + // The reloc section. + Reloc_section* rel_; + // The TLS_DESC relocations, if necessary. These must follow the @@ -2342567,7 +2353289,7 @@ index 0000000..6a3280d + // regular relocatoins and the TLS_DESC relocations. + Reloc_section* irelative_rel_; + // The .got.plt section. -+ Output_data_space* got_plt_; ++ Output_data_got_plt_i386* got_plt_; + // The part of the .got.plt section used for IRELATIVE relocs. + Output_data_space* got_irelative_; + // The number of PLT entries. @@ -2342590,7 +2353312,7 @@ index 0000000..6a3280d +{ + public: + Output_data_plt_i386_standard(Layout* layout, -+ Output_data_space* got_plt, ++ Output_data_got_plt_i386* got_plt, + Output_data_space* got_irelative) + : Output_data_plt_i386(layout, plt_entry_size, got_plt, got_irelative) + { } @@ -2342621,7 +2353343,7 @@ index 0000000..6a3280d +{ +public: + Output_data_plt_i386_exec(Layout* layout, -+ Output_data_space* got_plt, ++ Output_data_got_plt_i386* got_plt, + Output_data_space* got_irelative) + : Output_data_plt_i386_standard(layout, got_plt, got_irelative) + { } @@ -2342652,7 +2353374,7 @@ index 0000000..6a3280d +{ + public: + Output_data_plt_i386_dyn(Layout* layout, -+ Output_data_space* got_plt, ++ Output_data_got_plt_i386* got_plt, + Output_data_space* got_irelative) + : Output_data_plt_i386_standard(layout, got_plt, got_irelative) + { } @@ -2342860,14 +2353582,14 @@ index 0000000..6a3280d + // This chooses the right PLT flavor for an executable or a shared object. + Output_data_plt_i386* + make_data_plt(Layout* layout, -+ Output_data_space* got_plt, ++ Output_data_got_plt_i386* got_plt, + Output_data_space* got_irelative, + bool dyn) + { return this->do_make_data_plt(layout, got_plt, got_irelative, dyn); } + + virtual Output_data_plt_i386* + do_make_data_plt(Layout* layout, -+ Output_data_space* got_plt, ++ Output_data_got_plt_i386* got_plt, + Output_data_space* got_irelative, + bool dyn) + { @@ -2343074,7 +2353796,7 @@ index 0000000..6a3280d + got_section(Symbol_table*, Layout*); + + // Get the GOT PLT section. -+ Output_data_space* ++ Output_data_got_plt_i386* + got_plt_section() const + { + gold_assert(this->got_plt_ != NULL); @@ -2343167,7 +2353889,7 @@ index 0000000..6a3280d + // The PLT section. + Output_data_plt_i386* plt_; + // The GOT PLT section. -+ Output_data_space* got_plt_; ++ Output_data_got_plt_i386* got_plt_; + // The GOT section for IRELATIVE relocations. + Output_data_space* got_irelative_; + // The GOT section for TLSDESC relocations. @@ -2343239,7 +2353961,7 @@ index 0000000..6a3280d + | elfcpp::SHF_WRITE), + this->got_, got_order, true); + -+ this->got_plt_ = new Output_data_space(4, "** GOT PLT"); ++ this->got_plt_ = new Output_data_got_plt_i386(layout); + layout->add_output_section_data(".got.plt", elfcpp::SHT_PROGBITS, + (elfcpp::SHF_ALLOC + | elfcpp::SHF_WRITE), @@ -2343326,18 +2354048,39 @@ index 0000000..6a3280d + return this->rel_irelative_; +} + ++// Write the first three reserved words of the .got.plt section. ++// The remainder of the section is written while writing the PLT ++// in Output_data_plt_i386::do_write. ++ ++void ++Output_data_got_plt_i386::do_write(Output_file* of) ++{ ++ // The first entry in the GOT is the address of the .dynamic section ++ // aka the PT_DYNAMIC segment. The next two entries are reserved. ++ // We saved space for them when we created the section in ++ // Target_i386::got_section. ++ const off_t got_file_offset = this->offset(); ++ gold_assert(this->data_size() >= 12); ++ unsigned char* const got_view = of->get_output_view(got_file_offset, 12); ++ Output_section* dynamic = this->layout_->dynamic_section(); ++ uint32_t dynamic_addr = dynamic == NULL ? 0 : dynamic->address(); ++ elfcpp::Swap<32, false>::writeval(got_view, dynamic_addr); ++ memset(got_view + 4, 0, 8); ++ of->write_output_view(got_file_offset, 12, got_view); ++} ++ +// Create the PLT section. The ordinary .got section is an argument, +// since we need to refer to the start. We also create our own .got +// section just for PLT entries. + +Output_data_plt_i386::Output_data_plt_i386(Layout* layout, + uint64_t addralign, -+ Output_data_space* got_plt, ++ Output_data_got_plt_i386* got_plt, + Output_data_space* got_irelative) + : Output_section_data(addralign), -+ layout_(layout), tls_desc_rel_(NULL), -+ irelative_rel_(NULL), got_plt_(got_plt), got_irelative_(got_irelative), -+ count_(0), irelative_count_(0), global_ifuncs_(), local_ifuncs_() ++ tls_desc_rel_(NULL), irelative_rel_(NULL), got_plt_(got_plt), ++ got_irelative_(got_irelative), count_(0), irelative_count_(0), ++ global_ifuncs_(), local_ifuncs_() +{ + this->rel_ = new Reloc_section(false); + layout->add_output_section_data(".rel.plt", elfcpp::SHT_REL, @@ -2343677,6 +2354420,7 @@ index 0000000..6a3280d + const section_size_type got_size = + convert_to_section_size_type(this->got_plt_->data_size() + + this->got_irelative_->data_size()); ++ + unsigned char* const got_view = of->get_output_view(got_file_offset, + got_size); + @@ -2343688,18 +2354432,9 @@ index 0000000..6a3280d + this->fill_first_plt_entry(pov, got_address); + pov += this->get_plt_entry_size(); + -+ unsigned char* got_pov = got_view; -+ -+ // The first entry in the GOT is the address of the .dynamic section -+ // aka the PT_DYNAMIC segment. The next two entries are reserved. -+ // We saved space for them when we created the section in -+ // Target_i386::got_section. -+ Output_section* dynamic = this->layout_->dynamic_section(); -+ uint32_t dynamic_addr = dynamic == NULL ? 0 : dynamic->address(); -+ elfcpp::Swap<32, false>::writeval(got_pov, dynamic_addr); -+ got_pov += 4; -+ memset(got_pov, 0, 8); -+ got_pov += 8; ++ // The first three entries in the GOT are reserved, and are written ++ // by Output_data_got_plt_i386::do_write. ++ unsigned char* got_pov = got_view + 12; + + const int rel_size = elfcpp::Elf_sizes<32>::rel_size; + @@ -2344467,7 +2355202,8 @@ index 0000000..6a3280d + // Make a dynamic relocation if necessary. + if (gsym->needs_dynamic_reloc(Scan::get_reference_flags(r_type))) + { -+ if (gsym->may_need_copy_reloc()) ++ if (!parameters->options().output_is_position_independent() ++ && gsym->may_need_copy_reloc()) + { + target->copy_reloc(symtab, layout, object, + data_shndx, output_section, gsym, reloc); @@ -2344528,7 +2355264,8 @@ index 0000000..6a3280d + // Make a dynamic relocation if necessary. + if (gsym->needs_dynamic_reloc(Scan::get_reference_flags(r_type))) + { -+ if (gsym->may_need_copy_reloc()) ++ if (parameters->options().output_is_executable() ++ && gsym->may_need_copy_reloc()) + { + target->copy_reloc(symtab, layout, object, + data_shndx, output_section, gsym, reloc); @@ -2346188,7 +2356925,7 @@ index 0000000..6a3280d +{ + public: + Output_data_plt_i386_nacl(Layout* layout, -+ Output_data_space* got_plt, ++ Output_data_got_plt_i386* got_plt, + Output_data_space* got_irelative) + : Output_data_plt_i386(layout, plt_entry_size, got_plt, got_irelative) + { } @@ -2346217,7 +2356954,7 @@ index 0000000..6a3280d +{ +public: + Output_data_plt_i386_nacl_exec(Layout* layout, -+ Output_data_space* got_plt, ++ Output_data_got_plt_i386* got_plt, + Output_data_space* got_irelative) + : Output_data_plt_i386_nacl(layout, got_plt, got_irelative) + { } @@ -2346246,7 +2356983,7 @@ index 0000000..6a3280d +{ + public: + Output_data_plt_i386_nacl_dyn(Layout* layout, -+ Output_data_space* got_plt, ++ Output_data_got_plt_i386* got_plt, + Output_data_space* got_irelative) + : Output_data_plt_i386_nacl(layout, got_plt, got_irelative) + { } @@ -2346280,7 +2357017,7 @@ index 0000000..6a3280d + protected: + virtual Output_data_plt_i386* + do_make_data_plt(Layout* layout, -+ Output_data_space* got_plt, ++ Output_data_got_plt_i386* got_plt, + Output_data_space* got_irelative, + bool dyn) + { @@ -2346521,13 +2357258,13 @@ index 0000000..6a3280d +} // End anonymous namespace. diff --git a/gold/icf.cc b/gold/icf.cc new file mode 100644 -index 0000000..a58e34f +index 0000000..ad88715 --- /dev/null +++ b/gold/icf.cc @@ -0,0 +1,849 @@ +// icf.cc -- Identical Code Folding. +// -+// Copyright 2009, 2010, 2011 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Sriraman Tallam . + +// This file is part of gold. @@ -2346796,21 +2357533,21 @@ index 0000000..a58e34f + + if (it_reloc_info_list != reloc_info_list.end()) + { -+ Icf::Sections_reachable_info v = ++ Icf::Sections_reachable_info &v = + (it_reloc_info_list->second).section_info; + // Stores the information of the symbol pointed to by the reloc. -+ Icf::Symbol_info s = (it_reloc_info_list->second).symbol_info; ++ const Icf::Symbol_info &s = (it_reloc_info_list->second).symbol_info; + // Stores the addend and the symbol value. -+ Icf::Addend_info a = (it_reloc_info_list->second).addend_info; ++ Icf::Addend_info &a = (it_reloc_info_list->second).addend_info; + // Stores the offset of the reloc. -+ Icf::Offset_info o = (it_reloc_info_list->second).offset_info; -+ Icf::Reloc_addend_size_info reloc_addend_size_info = ++ const Icf::Offset_info &o = (it_reloc_info_list->second).offset_info; ++ const Icf::Reloc_addend_size_info &reloc_addend_size_info = + (it_reloc_info_list->second).reloc_addend_size_info; + Icf::Sections_reachable_info::iterator it_v = v.begin(); -+ Icf::Symbol_info::iterator it_s = s.begin(); ++ Icf::Symbol_info::const_iterator it_s = s.begin(); + Icf::Addend_info::iterator it_a = a.begin(); -+ Icf::Offset_info::iterator it_o = o.begin(); -+ Icf::Reloc_addend_size_info::iterator it_addend_size = ++ Icf::Offset_info::const_iterator it_o = o.begin(); ++ Icf::Reloc_addend_size_info::const_iterator it_addend_size = + reloc_addend_size_info.begin(); + + for (; it_v != v.end(); ++it_v, ++it_s, ++it_a, ++it_o, ++it_addend_size) @@ -2347376,13 +2358113,13 @@ index 0000000..a58e34f +} // End of namespace gold. diff --git a/gold/icf.h b/gold/icf.h new file mode 100644 -index 0000000..df6bc01 +index 0000000..3118642 --- /dev/null +++ b/gold/icf.h @@ -0,0 +1,179 @@ +// icf.h -- Identical Code Folding + -+// Copyright 2009, 2010, 2013 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Sriraman Tallam . + +// This file is part of gold. @@ -2347561,13 +2358298,13 @@ index 0000000..df6bc01 +#endif diff --git a/gold/incremental-dump.cc b/gold/incremental-dump.cc new file mode 100644 -index 0000000..5365265 +index 0000000..8ef16cf --- /dev/null +++ b/gold/incremental-dump.cc @@ -0,0 +1,518 @@ +// incremental.cc -- incremental linking test/debug tool + -+// Copyright 2009, 2010 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Rafael Avila de Espindola + +// This file is part of gold. @@ -2348085,13 +2358822,13 @@ index 0000000..5365265 +} diff --git a/gold/incremental.cc b/gold/incremental.cc new file mode 100644 -index 0000000..714b198 +index 0000000..2345cf8 --- /dev/null +++ b/gold/incremental.cc @@ -0,0 +1,3123 @@ +// inremental.cc -- incremental linking support for gold + -+// Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Mikolaj Zalewski . + +// This file is part of gold. @@ -2351214,13 +2361951,13 @@ index 0000000..714b198 +} // End namespace gold. diff --git a/gold/incremental.h b/gold/incremental.h new file mode 100644 -index 0000000..77803fc +index 0000000..f84511d --- /dev/null +++ b/gold/incremental.h @@ -0,0 +1,2255 @@ +// inremental.h -- incremental linking support for gold -*- C++ -*- + -+// Copyright 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Mikolaj Zalewski . + +// This file is part of gold. @@ -2353475,13 +2364212,13 @@ index 0000000..77803fc +#endif // !defined(GOLD_INCREMENTAL_H) diff --git a/gold/int_encoding.cc b/gold/int_encoding.cc new file mode 100644 -index 0000000..7887477 +index 0000000..f949d9a --- /dev/null +++ b/gold/int_encoding.cc @@ -0,0 +1,134 @@ +// int_encoding.cc -- variable length and unaligned integer encoding support. + -+// Copyright 2009, 2010 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Doug Kwan by refactoring scattered +// contents from other files in gold. Original code written by Ian +// Lance Taylor and Caleb Howe . @@ -2353615,13 +2364352,13 @@ index 0000000..7887477 +} // End namespace gold. diff --git a/gold/int_encoding.h b/gold/int_encoding.h new file mode 100644 -index 0000000..467d224 +index 0000000..da4a2da --- /dev/null +++ b/gold/int_encoding.h @@ -0,0 +1,158 @@ +// int_encoding.h -- variable length and unaligned integers -*- C++ -*- + -+// Copyright 2009 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Doug Kwan by refactoring scattered +// contents from other files in gold. Original code written by Ian +// Lance Taylor and Caleb Howe . @@ -2353779,14 +2364516,13 @@ index 0000000..467d224 +#endif // !defined(GOLD_INT_ENCODING_H) diff --git a/gold/layout.cc b/gold/layout.cc new file mode 100644 -index 0000000..38fd272 +index 0000000..82db775 --- /dev/null +++ b/gold/layout.cc -@@ -0,0 +1,5909 @@ +@@ -0,0 +1,5922 @@ +// layout.cc -- lay out output file sections for gold + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 -+// Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2354349,7 +2365085,9 @@ index 0000000..38fd272 +{ + "aranges", + "pubnames", ++ "gnu_pubnames", + "pubtypes", ++ "gnu_pubtypes", +}; + +// Returns whether the given debug section is in the list of @@ -2354430,7 +2365168,13 @@ index 0000000..38fd272 + && (shdr.get_sh_flags() & elfcpp::SHF_EXCLUDE)) + return false; + -+ switch (shdr.get_sh_type()) ++ elfcpp::Elf_Word sh_type = shdr.get_sh_type(); ++ ++ if ((sh_type >= elfcpp::SHT_LOOS && sh_type <= elfcpp::SHT_HIOS) ++ || (sh_type >= elfcpp::SHT_LOPROC && sh_type <= elfcpp::SHT_HIPROC)) ++ return parameters->target().should_include_section(sh_type); ++ ++ switch (sh_type) + { + case elfcpp::SHT_NULL: + case elfcpp::SHT_SYMTAB: @@ -2356529,12 +2367273,14 @@ index 0000000..38fd272 + // If there is a load segment that contains the file and program headers, + // provide a symbol __ehdr_start pointing there. + // A program can use this to examine itself robustly. -+ if (load_seg != NULL) -+ symtab->define_in_output_segment("__ehdr_start", NULL, -+ Symbol_table::PREDEFINED, load_seg, 0, 0, -+ elfcpp::STT_NOTYPE, elfcpp::STB_GLOBAL, -+ elfcpp::STV_HIDDEN, 0, -+ Symbol::SEGMENT_START, true); ++ Symbol *ehdr_start = symtab->lookup("__ehdr_start"); ++ if (ehdr_start != NULL && ehdr_start->is_predefined()) ++ { ++ if (load_seg != NULL) ++ ehdr_start->set_output_segment(load_seg, Symbol::SEGMENT_START); ++ else ++ ehdr_start->set_undefined(); ++ } + + // Set the file offsets of all the non-data sections we've seen so + // far which don't have to wait for the input sections. We need @@ -2359270,6 +2370016,10 @@ index 0000000..38fd272 + p != this->segment_list_.end(); + ++p) + (*p)->print_sections_to_mapfile(mapfile); ++ for (Section_list::const_iterator p = this->unattached_section_list_.begin(); ++ p != this->unattached_section_list_.end(); ++ ++p) ++ (*p)->print_to_mapfile(mapfile); +} + +// Print statistical information to stderr. This is used for --stats. @@ -2359694,14 +2370444,13 @@ index 0000000..38fd272 +} // End namespace gold. diff --git a/gold/layout.h b/gold/layout.h new file mode 100644 -index 0000000..792b748 +index 0000000..7c0113c --- /dev/null +++ b/gold/layout.h -@@ -0,0 +1,1629 @@ +@@ -0,0 +1,1628 @@ +// layout.h -- lay out output file sections for gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 -+// Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2361329,13 +2372078,13 @@ index 0000000..792b748 +#endif // !defined(GOLD_LAYOUT_H) diff --git a/gold/main.cc b/gold/main.cc new file mode 100644 -index 0000000..d329298 +index 0000000..bb86613 --- /dev/null +++ b/gold/main.cc @@ -0,0 +1,332 @@ +// main.cc -- gold main function. + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2361667,13 +2372416,13 @@ index 0000000..d329298 +} diff --git a/gold/mapfile.cc b/gold/mapfile.cc new file mode 100644 -index 0000000..2062ae4 +index 0000000..dc995e9 --- /dev/null +++ b/gold/mapfile.cc @@ -0,0 +1,404 @@ +// mapfile.cc -- map file generation for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2362077,13 +2372826,13 @@ index 0000000..2062ae4 +} // End namespace gold. diff --git a/gold/mapfile.h b/gold/mapfile.h new file mode 100644 -index 0000000..808fc66 +index 0000000..da158db --- /dev/null +++ b/gold/mapfile.h @@ -0,0 +1,118 @@ +// mapfile.h -- map file generation for gold -*- C++ -*- + -+// Copyright 2008, 2010 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2362201,13 +2372950,13 @@ index 0000000..808fc66 +#endif // !defined(GOLD_MAP_H) diff --git a/gold/merge.cc b/gold/merge.cc new file mode 100644 -index 0000000..f370c9c +index 0000000..6d444e6 --- /dev/null +++ b/gold/merge.cc @@ -0,0 +1,762 @@ +// merge.cc -- handle section merging for gold + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2362969,13 +2373718,13 @@ index 0000000..f370c9c +} // End namespace gold. diff --git a/gold/merge.h b/gold/merge.h new file mode 100644 -index 0000000..92c634a +index 0000000..b4fd8e1 --- /dev/null +++ b/gold/merge.h @@ -0,0 +1,574 @@ +// merge.h -- handle section merging for gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008, 2010 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2363549,13 +2374298,13 @@ index 0000000..92c634a +#endif // !defined(GOLD_MERGE_H) diff --git a/gold/mremap.c b/gold/mremap.c new file mode 100644 -index 0000000..e165634 +index 0000000..9c0fe6e --- /dev/null +++ b/gold/mremap.c @@ -0,0 +1,87 @@ +/* mremap.c -- version of mremap for gold. */ + -+/* Copyright 2009, 2011 Free Software Foundation, Inc. ++/* Copyright (C) 2009-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor . + + This file is part of gold. @@ -2363642,13 +2374391,13 @@ index 0000000..e165634 +#endif /* !defined(HAVE_MMAP) */ diff --git a/gold/nacl.cc b/gold/nacl.cc new file mode 100644 -index 0000000..b22248c +index 0000000..047f92e --- /dev/null +++ b/gold/nacl.cc @@ -0,0 +1,47 @@ +// nacl.cc -- Native Client support for gold + -+// Copyright 2012 Free Software Foundation, Inc. ++// Copyright (C) 2012-2014 Free Software Foundation, Inc. + +// This file is part of gold. + @@ -2363695,13 +2374444,13 @@ index 0000000..b22248c +} // end namespace gold diff --git a/gold/nacl.h b/gold/nacl.h new file mode 100644 -index 0000000..323f804 +index 0000000..cb0e9d1 --- /dev/null +++ b/gold/nacl.h @@ -0,0 +1,243 @@ +// nacl.h -- Native Client support for gold -*- C++ -*- + -+// Copyright 2012 Free Software Foundation, Inc. ++// Copyright (C) 2012-2014 Free Software Foundation, Inc. + +// This file is part of gold. + @@ -2363944,14 +2374693,13 @@ index 0000000..323f804 +#endif // !defined(GOLD_NACL_H) diff --git a/gold/object.cc b/gold/object.cc new file mode 100644 -index 0000000..b1feacc +index 0000000..c894c13 --- /dev/null +++ b/gold/object.cc -@@ -0,0 +1,3331 @@ +@@ -0,0 +1,3330 @@ +// object.cc -- support for an object file for linking in gold + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 -+// Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2365583,7 +2376331,7 @@ index 0000000..b1feacc + symtab->icf()->get_folded_section(this, i); + Relobj* folded_obj = + reinterpret_cast(folded.first); -+ gold_info(_("%s: ICF folding section '%s' in file '%s'" ++ gold_info(_("%s: ICF folding section '%s' in file '%s' " + "into '%s' in file '%s'"), + program_name, this->section_name(i).c_str(), + this->name().c_str(), @@ -2367281,14 +2378029,13 @@ index 0000000..b1feacc +} // End namespace gold. diff --git a/gold/object.h b/gold/object.h new file mode 100644 -index 0000000..88263b4 +index 0000000..38b06f0 --- /dev/null +++ b/gold/object.h -@@ -0,0 +1,2918 @@ +@@ -0,0 +1,2917 @@ +// object.h -- support for an object file for linking in gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 -+// Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2370205,14 +2380952,13 @@ index 0000000..88263b4 +#endif // !defined(GOLD_OBJECT_H) diff --git a/gold/options.cc b/gold/options.cc new file mode 100644 -index 0000000..000e6d0 +index 0000000..731061d --- /dev/null +++ b/gold/options.cc -@@ -0,0 +1,1499 @@ +@@ -0,0 +1,1507 @@ +// options.c -- handle command line options for gold + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2013 -+// Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2370760,6 +2381506,7 @@ index 0000000..000e6d0 +{ + if (!read_dynamic_list(arg, cmdline, &this->dynamic_list_)) + gold::gold_fatal(_("unable to parse dynamic-list script file %s"), arg); ++ this->have_dynamic_list_ = true; +} + +void @@ -2371129,6 +2381876,7 @@ index 0000000..000e6d0 + do_demangle_(false), + plugins_(NULL), + dynamic_list_(), ++ have_dynamic_list_(false), + incremental_mode_(INCREMENTAL_OFF), + incremental_disposition_(INCREMENTAL_STARTUP), + incremental_startup_disposition_(INCREMENTAL_CHECK), @@ -2371410,6 +2382158,13 @@ index 0000000..000e6d0 + // in the path, as appropriate. + this->add_sysroot(); + ++ // --dynamic-list overrides -Bsymbolic and -Bsymbolic-functions. ++ if (this->have_dynamic_list()) ++ { ++ this->set_Bsymbolic(false); ++ this->set_Bsymbolic_functions(false); ++ } ++ + // Now that we've normalized the options, check for contradictory ones. + if (this->shared() && this->is_static()) + gold_fatal(_("-shared and -static are incompatible")); @@ -2371710,14 +2382465,13 @@ index 0000000..000e6d0 +} // End namespace gold. diff --git a/gold/options.h b/gold/options.h new file mode 100644 -index 0000000..a2f5a88 +index 0000000..a1b74c7 --- /dev/null +++ b/gold/options.h -@@ -0,0 +1,2117 @@ +@@ -0,0 +1,2123 @@ +// options.h -- handle command line options for gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2013 -+// Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2373154,6 +2383908,11 @@ index 0000000..a2f5a88 + in_dynamic_list(const char* symbol) const + { return this->dynamic_list_.version_script_info()->symbol_is_local(symbol); } + ++ // True if a --dynamic-list script was provided. ++ bool ++ have_dynamic_list() const ++ { return this->have_dynamic_list_; } ++ + // Finalize the dynamic list. + void + finalize_dynamic_list() @@ -2373307,6 +2384066,8 @@ index 0000000..a2f5a88 + // script.cc, we store this as a Script_options object, even though + // we only use a single Version_tree from it. + Script_options dynamic_list_; ++ // Whether a --dynamic-list file was provided. ++ bool have_dynamic_list_; + // The incremental linking mode. + Incremental_mode incremental_mode_; + // The disposition given by the --incremental-changed, @@ -2373833,14 +2384594,13 @@ index 0000000..a2f5a88 +#endif // !defined(GOLD_OPTIONS_H) diff --git a/gold/output.cc b/gold/output.cc new file mode 100644 -index 0000000..348ad64 +index 0000000..c078fbb --- /dev/null +++ b/gold/output.cc -@@ -0,0 +1,5568 @@ +@@ -0,0 +1,5571 @@ +// output.cc -- manage the output file for gold + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 -+// Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2375636,6 +2386396,10 @@ index 0000000..348ad64 + val = pool->get_offset(this->u_.str); + break; + ++ case DYNAMIC_CUSTOM: ++ val = parameters->target().dynamic_tag_custom_value(this->tag_); ++ break; ++ + default: + val = this->u_.od->address() + this->offset_; + break; @@ -2379407,14 +2390171,13 @@ index 0000000..348ad64 +} // End namespace gold. diff --git a/gold/output.h b/gold/output.h new file mode 100644 -index 0000000..574d270 +index 0000000..ba0cdaa --- /dev/null +++ b/gold/output.h -@@ -0,0 +1,4866 @@ +@@ -0,0 +1,4877 @@ +// output.h -- manage the output file for gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2013 -+// Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2381991,6 +2392754,11 @@ index 0000000..574d270 + add_string(elfcpp::DT tag, const std::string& str) + { this->add_string(tag, str.c_str()); } + ++ // Add a new dynamic entry with custom value. ++ void ++ add_custom(elfcpp::DT tag) ++ { this->add_entry(Dynamic_entry(tag)); } ++ + protected: + // Adjust the output section to set the entry size. + void @@ -2382055,6 +2392823,11 @@ index 0000000..574d270 + : tag_(tag), offset_(DYNAMIC_STRING) + { this->u_.str = str; } + ++ // Create an entry with a custom value. ++ Dynamic_entry(elfcpp::DT tag) ++ : tag_(tag), offset_(DYNAMIC_CUSTOM) ++ { } ++ + // Return the tag of this entry. + elfcpp::DT + tag() const @@ -2382078,7 +2392851,9 @@ index 0000000..574d270 + // Symbol adress. + DYNAMIC_SYMBOL = -3U, + // String. -+ DYNAMIC_STRING = -4U ++ DYNAMIC_STRING = -4U, ++ // Custom value. ++ DYNAMIC_CUSTOM = -5U + // Any other value indicates a section address plus OFFSET. + }; + @@ -2384279,14 +2395054,13 @@ index 0000000..574d270 +#endif // !defined(GOLD_OUTPUT_H) diff --git a/gold/parameters.cc b/gold/parameters.cc new file mode 100644 -index 0000000..7410e7f +index 0000000..588f448 --- /dev/null +++ b/gold/parameters.cc -@@ -0,0 +1,389 @@ +@@ -0,0 +1,388 @@ +// parameters.cc -- general parameters for a link using gold + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 -+// Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2384674,13 +2395448,13 @@ index 0000000..7410e7f +} // End namespace gold. diff --git a/gold/parameters.h b/gold/parameters.h new file mode 100644 -index 0000000..8d1ec2e +index 0000000..fe5db15 --- /dev/null +++ b/gold/parameters.h @@ -0,0 +1,246 @@ +// parameters.h -- general parameters for a link using gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2013 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2384926,13 +2395700,13 @@ index 0000000..8d1ec2e +#endif // !defined(GOLD_PARAMETERS_H) diff --git a/gold/plugin.cc b/gold/plugin.cc new file mode 100644 -index 0000000..e932c1c +index 0000000..62807b8 --- /dev/null +++ b/gold/plugin.cc @@ -0,0 +1,1862 @@ +// plugin.cc -- plugin manager for gold -*- C++ -*- + -+// Copyright 2008, 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2386794,13 +2397568,13 @@ index 0000000..e932c1c +} // End namespace gold. diff --git a/gold/plugin.h b/gold/plugin.h new file mode 100644 -index 0000000..e4289ff +index 0000000..320b02d --- /dev/null +++ b/gold/plugin.h @@ -0,0 +1,594 @@ +// plugin.h -- plugin manager for gold -*- C++ -*- + -+// Copyright 2008, 2009, 2010, 2011, 2013 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2387394,13 +2398168,13 @@ index 0000000..e4289ff +#endif // !defined(GOLD_PLUGIN_H) diff --git a/gold/po/Make-in b/gold/po/Make-in new file mode 100644 -index 0000000..3f0fc76 +index 0000000..8212bf7 --- /dev/null +++ b/gold/po/Make-in @@ -0,0 +1,258 @@ +# Makefile for program source directory in GNU NLS utilities package. +# Copyright (C) 1995, 1996, 1997 by Ulrich Drepper -+# Copyright 2003, 2006, 2007, 2009 Free Software Foundation, Inc. ++# Copyright (C) 2003-2014 Free Software Foundation, Inc. +# +# This file may be copied and used freely without restrictions. It can +# be used in projects which are not available under the GNU Public License @@ -2392348,10 +2403122,10 @@ index 0000000..59f28eb +#~ msgstr "%s: tukematon ELF-datakoodaus %d" diff --git a/gold/po/gold.pot b/gold/po/gold.pot new file mode 100644 -index 0000000..d58054a +index 0000000..6340518 --- /dev/null +++ b/gold/po/gold.pot -@@ -0,0 +1,2263 @@ +@@ -0,0 +1,3444 @@ +# SOME DESCRIPTIVE TITLE. +# Copyright (C) YEAR THE PACKAGE'S COPYRIGHT HOLDER +# This file is distributed under the same license as the PACKAGE package. @@ -2392362,166 +2403136,415 @@ index 0000000..d58054a +msgstr "" +"Project-Id-Version: PACKAGE VERSION\n" +"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n" -+"POT-Creation-Date: 2010-03-03 15:08+0100\n" ++"POT-Creation-Date: 2014-02-10 09:42+1030\n" +"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" +"Last-Translator: FULL NAME \n" +"Language-Team: LANGUAGE \n" ++"Language: \n" +"MIME-Version: 1.0\n" +"Content-Type: text/plain; charset=CHARSET\n" +"Content-Transfer-Encoding: 8bit\n" + -+#: archive.cc:119 ++#: archive.cc:135 ++#, c-format ++msgid "script or expression reference to %s" ++msgstr "" ++ ++#: archive.cc:229 +#, c-format +msgid "%s: no archive symbol table (run ranlib)" +msgstr "" + -+#: archive.cc:204 ++#: archive.cc:317 +#, c-format +msgid "%s: bad archive symbol table names" +msgstr "" + -+#: archive.cc:236 ++#: archive.cc:349 +#, c-format +msgid "%s: malformed archive header at %zu" +msgstr "" + -+#: archive.cc:256 ++#: archive.cc:369 +#, c-format +msgid "%s: malformed archive header size at %zu" +msgstr "" + -+#: archive.cc:267 ++#: archive.cc:380 +#, c-format +msgid "%s: malformed archive header name at %zu" +msgstr "" + -+#: archive.cc:297 ++#: archive.cc:411 +#, c-format +msgid "%s: bad extended name index at %zu" +msgstr "" + -+#: archive.cc:307 ++#: archive.cc:421 +#, c-format +msgid "%s: bad extended name entry at header %zu" +msgstr "" + -+#: archive.cc:404 ++#: archive.cc:518 +#, c-format +msgid "%s: short archive header at %zu" +msgstr "" + -+#: archive.cc:560 ++#: archive.cc:702 +#, c-format +msgid "%s: member at %zu is not an ELF object" +msgstr "" + -+#: archive.cc:879 ++#: archive.cc:1043 +#, c-format +msgid "%s: archive libraries: %u\n" +msgstr "" + -+#: archive.cc:881 ++#: archive.cc:1045 +#, c-format +msgid "%s: total archive members: %u\n" +msgstr "" + -+#: archive.cc:883 ++#: archive.cc:1047 +#, c-format +msgid "%s: loaded archive members: %u\n" +msgstr "" + -+#: arm.cc:1149 i386.cc:536 sparc.cc:1087 x86_64.cc:565 ++#: archive.cc:1277 ++#, c-format ++msgid "%s: lib groups: %u\n" ++msgstr "" ++ ++#: archive.cc:1279 ++#, c-format ++msgid "%s: total lib groups members: %u\n" ++msgstr "" ++ ++#: archive.cc:1281 ++#, c-format ++msgid "%s: loaded lib groups members: %u\n" ++msgstr "" ++ ++#: arm-reloc-property.cc:303 ++#, c-format ++msgid "invalid reloc %u" ++msgstr "" ++ ++#: arm-reloc-property.cc:316 ++msgid "reloc " ++msgstr "" ++ ++#: arm-reloc-property.cc:316 ++msgid "unimplemented reloc " ++msgstr "" ++ ++#: arm-reloc-property.cc:319 ++msgid "dynamic reloc " ++msgstr "" ++ ++#: arm-reloc-property.cc:322 ++msgid "private reloc " ++msgstr "" ++ ++#: arm-reloc-property.cc:325 ++msgid "obsolete reloc " ++msgstr "" ++ ++#: arm.cc:1074 ++msgid "** ARM cantunwind" ++msgstr "" ++ ++#: arm.cc:4037 ++#, c-format ++msgid "%s: Thumb BLX instruction targets thumb function '%s'." ++msgstr "" ++ ++#: arm.cc:4183 ++msgid "conditional branch to PLT in THUMB-2 not supported yet." ++msgstr "" ++ ++#: arm.cc:5263 ++msgid "PREL31 overflow in EXIDX_CANTUNWIND entry" ++msgstr "" ++ ++#. Something is wrong with this section. Better not touch it. ++#: arm.cc:5509 ++#, c-format ++msgid "uneven .ARM.exidx section size in %s section %u" ++msgstr "" ++ ++#: arm.cc:5835 ++msgid "Found non-EXIDX input sections in EXIDX output section" ++msgstr "" ++ ++#: arm.cc:5889 arm.cc:5893 ++#, c-format ++msgid "" ++"unwinding may not work because EXIDX input section %u of %s is not in EXIDX " ++"output section" ++msgstr "" ++ ++#: arm.cc:6179 ++#, c-format ++msgid "" ++"cannot scan executable section %u of %s for Cortex-A8 erratum because it has " ++"no mapping symbols." ++msgstr "" ++ ++#: arm.cc:6381 object.cc:818 ++#, c-format ++msgid "invalid symbol table name index: %u" ++msgstr "" ++ ++#: arm.cc:6389 object.cc:824 ++#, c-format ++msgid "symbol table name section has wrong type: %u" ++msgstr "" ++ ++#: arm.cc:6639 ++#, c-format ++msgid "EXIDX section %s(%u) links to invalid section %u in %s" ++msgstr "" ++ ++#: arm.cc:6648 ++#, c-format ++msgid "EXIDX sections %s(%u) and %s(%u) both link to text section%s(%u) in %s" ++msgstr "" ++ ++#: arm.cc:6662 ++#, c-format ++msgid "EXIDX section %s(%u) links to non-allocated section %s(%u) in %s" ++msgstr "" ++ ++#. I would like to make this an error but currently ld just ignores ++#. this. ++#: arm.cc:6672 ++#, c-format ++msgid "EXIDX section %s(%u) links to non-executable section %s(%u) in %s" ++msgstr "" ++ ++#: arm.cc:6756 ++#, c-format ++msgid "SHF_LINK_ORDER not set in EXIDX section %s of %s" ++msgstr "" ++ ++#: arm.cc:6789 ++#, c-format ++msgid "relocation section %u has invalid info %u" ++msgstr "" ++ ++#: arm.cc:6795 ++#, c-format ++msgid "section %u has multiple relocation sections %u and %u" ++msgstr "" ++ ++#: arm.cc:7155 ++#, c-format ++msgid "undefined or discarded local symbol %u from object %s in GOT" ++msgstr "" ++ ++#: arm.cc:7177 ++#, c-format ++msgid "undefined or discarded symbol %s in GOT" ++msgstr "" ++ ++#: arm.cc:7293 i386.cc:168 sparc.cc:1349 tilegx.cc:182 x86_64.cc:257 +msgid "** PLT" +msgstr "" + -+#: arm.cc:1364 i386.cc:880 powerpc.cc:1014 sparc.cc:1502 x86_64.cc:955 -+#: x86_64.cc:1265 ++#: arm.cc:7800 i386.cc:1685 powerpc.cc:5111 sparc.cc:2117 tilegx.cc:3123 ++#: tilegx.cc:3575 x86_64.cc:2169 x86_64.cc:2598 +#, c-format +msgid "%s: unsupported reloc %u against local symbol" +msgstr "" + -+#: arm.cc:1404 powerpc.cc:1105 sparc.cc:1592 x86_64.cc:992 -+msgid "requires unsupported dynamic reloc; recompile with -fPIC" ++#: arm.cc:7844 ++#, c-format ++msgid "requires unsupported dynamic reloc %s; recompile with -fPIC" ++msgstr "" ++ ++#: arm.cc:7935 i386.cc:1775 x86_64.cc:2377 ++#, c-format ++msgid "section symbol %u has bad shndx %u" +msgstr "" + +#. These are relocations which should only be seen by the +#. dynamic linker, and should never be seen here. -+#: arm.cc:1519 arm.cc:1739 arm.cc:2354 i386.cc:1002 i386.cc:1334 -+#: powerpc.cc:1223 powerpc.cc:1432 sparc.cc:1877 sparc.cc:2238 x86_64.cc:1145 -+#: x86_64.cc:1453 ++#: arm.cc:8044 arm.cc:8477 i386.cc:1844 i386.cc:2293 sparc.cc:2532 ++#: sparc.cc:3009 tilegx.cc:3570 tilegx.cc:4123 x86_64.cc:2470 x86_64.cc:2931 +#, c-format +msgid "%s: unexpected reloc %u in object file" +msgstr "" + -+#: arm.cc:1538 i386.cc:1171 powerpc.cc:1242 sparc.cc:1896 x86_64.cc:1279 -+#: x86_64.cc:1571 ++#: arm.cc:8076 i386.cc:1878 sparc.cc:2431 tilegx.cc:3474 x86_64.cc:2502 ++#, c-format ++msgid "local symbol %u has bad shndx %u" ++msgstr "" ++ ++#: arm.cc:8177 i386.cc:2021 powerpc.cc:5655 sparc.cc:2551 tilegx.cc:3591 ++#: tilegx.cc:4128 x86_64.cc:2614 x86_64.cc:3053 +#, c-format +msgid "%s: unsupported reloc %u against global symbol %s" +msgstr "" + -+#: arm.cc:1804 i386.cc:1542 ++#: arm.cc:8635 i386.cc:2503 +#, c-format +msgid "%s: unsupported RELA reloc section" +msgstr "" + -+#: arm.cc:2047 ++#: arm.cc:8725 +msgid "" -+"relocation R_ARM_MOVW_ABS_NC cannot be used when makinga shared object; " -+"recompile with -fPIC" ++"unable to provide V4BX reloc interworking fix up; the target profile does " ++"not support BX instruction" +msgstr "" + -+#: arm.cc:2056 -+msgid "" -+"relocation R_ARM_MOVT_ABS cannot be used when makinga shared object; " -+"recompile with -fPIC" -+msgstr "" -+ -+#: arm.cc:2067 -+msgid "" -+"relocation R_ARM_THM_MOVW_ABS_NC cannot be used whenmaking a shared object; " -+"recompile with -fPIC" -+msgstr "" -+ -+#: arm.cc:2077 -+msgid "" -+"relocation R_ARM_THM_MOVT_ABS cannot be used whenmaking a shared object; " -+"recompile with -fPIC" -+msgstr "" -+ -+#: arm.cc:2141 -+msgid "cannot find origin of R_ARM_BASE_PREL" -+msgstr "" -+ -+#: arm.cc:2169 -+msgid "cannot find origin of R_ARM_BASE_ABS" -+msgstr "" -+ -+#: arm.cc:2230 i386.cc:1820 i386.cc:2521 powerpc.cc:1798 sparc.cc:2711 -+#: x86_64.cc:1935 x86_64.cc:2518 ++#: arm.cc:8859 +#, c-format -+msgid "unexpected reloc %u in object file" ++msgid "cannot relocate %s in object file" +msgstr "" + -+#: arm.cc:2236 i386.cc:1852 i386.cc:1931 i386.cc:1983 i386.cc:2014 -+#: i386.cc:2076 powerpc.cc:1804 sparc.cc:2717 sparc.cc:2900 sparc.cc:2961 -+#: sparc.cc:3068 x86_64.cc:1956 x86_64.cc:2039 x86_64.cc:2094 x86_64.cc:2119 ++#: arm.cc:9333 arm.cc:9914 ++#, c-format ++msgid "relocation overflow in %s" ++msgstr "" ++ ++#: arm.cc:9341 arm.cc:9919 ++#, c-format ++msgid "unexpected opcode while processing relocation %s" ++msgstr "" ++ ++#: arm.cc:9485 i386.cc:2841 i386.cc:2923 i386.cc:2994 i386.cc:3030 ++#: i386.cc:3102 powerpc.cc:7562 sparc.cc:3589 sparc.cc:3780 sparc.cc:3841 ++#: sparc.cc:3948 tilegx.cc:4712 x86_64.cc:3486 x86_64.cc:3586 x86_64.cc:3664 ++#: x86_64.cc:3698 +#, c-format +msgid "unsupported reloc %u" +msgstr "" + -+#: arm.cc:2248 ++#: arm.cc:9564 +#, c-format -+msgid "relocation overflow in relocation %u" ++msgid "%s: unexpected %s in object file" +msgstr "" + -+#: arm.cc:2256 ++#: arm.cc:9899 +#, c-format -+msgid "unexpected opcode while processing relocation %u" ++msgid "cannot handle %s in a relocatable link" +msgstr "" + -+#: arm.cc:2359 i386.cc:2535 ++#: arm.cc:10003 +#, c-format -+msgid "unsupported reloc %u in object file" ++msgid "Source object %s has EABI version %d but output has EABI version %d." ++msgstr "" ++ ++#: arm.cc:10100 powerpc.cc:2077 target.cc:94 ++#, c-format ++msgid "%s: unsupported ELF file type %d" ++msgstr "" ++ ++#: arm.cc:10296 ++#, c-format ++msgid "%s: unknown CPU architecture" ++msgstr "" ++ ++#: arm.cc:10333 ++#, c-format ++msgid "%s: conflicting CPU architectures %d/%d" ++msgstr "" ++ ++#: arm.cc:10471 ++#, c-format ++msgid "%s has both the current and legacy Tag_MPextension_use attributes" ++msgstr "" ++ ++#: arm.cc:10499 ++#, c-format ++msgid "%s uses VFP register arguments, output does not" ++msgstr "" ++ ++#: arm.cc:10645 ++#, c-format ++msgid "conflicting architecture profiles %c/%c" ++msgstr "" ++ ++#. It's sometimes ok to mix different configs, so this is only ++#. a warning. ++#: arm.cc:10703 ++#, c-format ++msgid "%s: conflicting platform configuration" ++msgstr "" ++ ++#: arm.cc:10712 ++#, c-format ++msgid "%s: conflicting use of R9" ++msgstr "" ++ ++#: arm.cc:10725 ++#, c-format ++msgid "%s: SB relative addressing conflicts with use of R9" ++msgstr "" ++ ++#: arm.cc:10740 ++#, c-format ++msgid "" ++"%s uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of " ++"wchar_t values across objects may fail" ++msgstr "" ++ ++#: arm.cc:10766 ++#, c-format ++msgid "" ++"%s uses %s enums yet the output is to use %s enums; use of enum values " ++"across objects may fail" ++msgstr "" ++ ++#: arm.cc:10782 ++#, c-format ++msgid "%s uses iWMMXt register arguments, output does not" ++msgstr "" ++ ++#: arm.cc:10803 ++#, c-format ++msgid "fp16 format mismatch between %s and output" ++msgstr "" ++ ++#: arm.cc:10849 ++#, c-format ++msgid "%s has has both the current and legacy Tag_MPextension_use attributes" ++msgstr "" ++ ++#: arm.cc:10895 arm.cc:10988 ++#, c-format ++msgid "%s: unknown mandatory EABI object attribute %d" ++msgstr "" ++ ++#: arm.cc:10899 arm.cc:10993 ++#, c-format ++msgid "%s: unknown EABI object attribute %d" ++msgstr "" ++ ++#: arm.cc:11345 ++#, c-format ++msgid "cannot handle branch to local %u in a merged section %s" ++msgstr "" ++ ++#: arm.cc:11425 target-reloc.h:390 ++msgid "relocation refers to discarded section" ++msgstr "" ++ ++#. We cannot handle this now. ++#: arm.cc:11589 ++#, c-format ++msgid "multiple SHT_ARM_EXIDX sections %s and %s in a non-relocatable link" ++msgstr "" ++ ++#: attributes.cc:410 ++#, c-format ++msgid "%s: must be processed by '%s' toolchain" ++msgstr "" ++ ++#: attributes.cc:418 ++#, c-format ++msgid "%s: object tag '%d, %s' is incompatible with tag '%d, %s'" +msgstr "" + +#: binary.cc:129 @@ -2392529,211 +2403552,249 @@ index 0000000..d58054a +msgid "cannot open %s: %s:" +msgstr "" + -+#: compressed_output.cc:128 ++#: common.cc:352 output.cc:2432 output.cc:2531 ++#, c-format ++msgid "out of patch space in section %s; relink with --incremental-full" ++msgstr "" ++ ++#: compressed_output.cc:225 +msgid "not compressing section data: zlib error" +msgstr "" + -+#: cref.cc:244 ++#: cref.cc:384 +#, c-format +msgid "cannot open symbol count file %s: %s" +msgstr "" + -+#: descriptors.cc:116 ++#: cref.cc:398 ++#, c-format ++msgid "" ++"\n" ++"Cross Reference Table\n" ++"\n" ++msgstr "" ++ ++#: cref.cc:399 ++msgid "Symbol" ++msgstr "" ++ ++#: cref.cc:401 ++msgid "File" ++msgstr "" ++ ++#: descriptors.cc:125 +#, c-format +msgid "file %s was removed during the link" +msgstr "" + -+#: descriptors.cc:169 ++#: descriptors.cc:177 +msgid "out of file descriptors and couldn't close any" +msgstr "" + -+#: descriptors.cc:190 descriptors.cc:226 ++#: descriptors.cc:198 descriptors.cc:234 descriptors.cc:267 +#, c-format +msgid "while closing %s: %s" +msgstr "" + -+#: dirsearch.cc:71 ++#: dirsearch.cc:73 +#, c-format +msgid "%s: can not read directory: %s" +msgstr "" + -+#: dwarf_reader.cc:53 dwarf_reader.cc:84 -+msgid "Unusually large LEB128 decoded, debug information may be corrupted" ++#: dwarf_reader.cc:454 ++#, c-format ++msgid "" ++"%s: DWARF info may be corrupt; offsets in a range list entry are in " ++"different sections" +msgstr "" + -+#: dynobj.cc:164 ++#: dwarf_reader.cc:1513 ++#, c-format ++msgid "%s: corrupt debug info in %s" ++msgstr "" ++ ++#: dynobj.cc:176 +#, c-format +msgid "unexpected duplicate type %u section: %u, %u" +msgstr "" + -+#: dynobj.cc:200 ++#: dynobj.cc:231 +#, c-format +msgid "unexpected link in section %u header: %u != %u" +msgstr "" + -+#: dynobj.cc:236 ++#: dynobj.cc:267 +#, c-format +msgid "DYNAMIC section %u link out of range: %u" +msgstr "" + -+#: dynobj.cc:244 ++#: dynobj.cc:275 +#, c-format +msgid "DYNAMIC section %u link %u is not a strtab" +msgstr "" + -+#: dynobj.cc:273 ++#: dynobj.cc:304 +#, c-format +msgid "DT_SONAME value out of range: %lld >= %lld" +msgstr "" + -+#: dynobj.cc:285 ++#: dynobj.cc:316 +#, c-format +msgid "DT_NEEDED value out of range: %lld >= %lld" +msgstr "" + -+#: dynobj.cc:298 ++#: dynobj.cc:329 +msgid "missing DT_NULL in dynamic segment" +msgstr "" + -+#: dynobj.cc:344 ++#: dynobj.cc:382 +#, c-format +msgid "invalid dynamic symbol table name index: %u" +msgstr "" + -+#: dynobj.cc:351 ++#: dynobj.cc:389 +#, c-format +msgid "dynamic symbol table name section has wrong type: %u" +msgstr "" + -+#: dynobj.cc:438 object.cc:463 object.cc:1106 ++#: dynobj.cc:476 object.cc:690 object.cc:1453 +#, c-format +msgid "bad section name offset for section %u: %lu" +msgstr "" + -+#: dynobj.cc:468 ++#: dynobj.cc:506 +#, c-format +msgid "duplicate definition for version %u" +msgstr "" + -+#: dynobj.cc:497 ++#: dynobj.cc:535 +#, c-format +msgid "unexpected verdef version %u" +msgstr "" + -+#: dynobj.cc:513 ++#: dynobj.cc:551 +#, c-format +msgid "verdef vd_cnt field too small: %u" +msgstr "" + -+#: dynobj.cc:521 ++#: dynobj.cc:559 +#, c-format +msgid "verdef vd_aux field out of range: %u" +msgstr "" + -+#: dynobj.cc:532 ++#: dynobj.cc:570 +#, c-format +msgid "verdaux vda_name field out of range: %u" +msgstr "" + -+#: dynobj.cc:542 ++#: dynobj.cc:580 +#, c-format +msgid "verdef vd_next field out of range: %u" +msgstr "" + -+#: dynobj.cc:576 ++#: dynobj.cc:614 +#, c-format +msgid "unexpected verneed version %u" +msgstr "" + -+#: dynobj.cc:585 ++#: dynobj.cc:623 +#, c-format +msgid "verneed vn_aux field out of range: %u" +msgstr "" + -+#: dynobj.cc:599 ++#: dynobj.cc:637 +#, c-format +msgid "vernaux vna_name field out of range: %u" +msgstr "" + -+#: dynobj.cc:610 ++#: dynobj.cc:648 +#, c-format +msgid "verneed vna_next field out of range: %u" +msgstr "" + -+#: dynobj.cc:621 ++#: dynobj.cc:659 +#, c-format +msgid "verneed vn_next field out of range: %u" +msgstr "" + -+#: dynobj.cc:670 ++#: dynobj.cc:708 +msgid "size of dynamic symbols is not multiple of symbol size" +msgstr "" + -+#: dynobj.cc:1435 ++#: dynobj.cc:1524 +#, c-format +msgid "symbol %s has undefined version %s" +msgstr "" + -+#: ehframe.h:82 ++#: ehframe.cc:381 ++msgid "overflow in PLT unwind data; unwinding through PLT may fail" ++msgstr "" ++ ++#: ehframe.h:78 +msgid "** eh_frame_hdr" +msgstr "" + -+#: ehframe.h:353 ++#: ehframe.h:419 +msgid "** eh_frame" +msgstr "" + -+#: errors.cc:81 ++#: errors.cc:81 errors.cc:92 +#, c-format +msgid "%s: fatal error: " +msgstr "" + -+#: errors.cc:92 ++#: errors.cc:103 errors.cc:139 +#, c-format +msgid "%s: error: " +msgstr "" + -+#: errors.cc:104 ++#: errors.cc:115 errors.cc:155 +#, c-format +msgid "%s: warning: " +msgstr "" + -+#: errors.cc:128 -+#, c-format -+msgid "%s: %s: error: " ++#: errors.cc:179 ++msgid "warning" +msgstr "" + -+#: errors.cc:144 -+#, c-format -+msgid "%s: %s: warning: " ++#: errors.cc:184 ++msgid "error" +msgstr "" + -+#: errors.cc:167 ++#: errors.cc:190 +#, c-format -+msgid "%s: %s: error: undefined reference to '%s'\n" ++msgid "%s: %s: undefined reference to '%s'\n" +msgstr "" + -+#: errors.cc:172 ++#: errors.cc:194 +#, c-format -+msgid "%s: %s: error: undefined reference to '%s', version '%s'\n" ++msgid "%s: %s: undefined reference to '%s', version '%s'\n" +msgstr "" + -+#: errors.cc:182 ++#: errors.cc:198 ++#, c-format ++msgid "" ++"%s: the vtable symbol may be undefined because the class is missing its key " ++"function" ++msgstr "" ++ ++#: errors.cc:208 +#, c-format +msgid "%s: " +msgstr "" + -+#: expression.cc:172 ++#: expression.cc:192 +#, c-format +msgid "undefined symbol '%s' referenced in expression" +msgstr "" + -+#: expression.cc:209 ++#: expression.cc:230 +msgid "invalid reference to dot symbol outside of SECTIONS clause" +msgstr "" + +#. Handle unary operators. We use a preprocessor macro as a hack to +#. capture the C operator. -+#: expression.cc:278 ++#: expression.cc:302 +msgid "unary " +msgstr "" + @@ -2392745,125 +2403806,149 @@ index 0000000..d58054a +#. if the right operand is zero. WARN means that we should warn if +#. used on section relative values in a relocatable link. We always +#. warn if used on values in different sections in a relocatable link. -+#: expression.cc:400 ++#: expression.cc:446 +msgid "binary " +msgstr "" + -+#: expression.cc:404 ++#: expression.cc:450 +msgid " by zero" +msgstr "" + -+#: expression.cc:575 ++#: expression.cc:636 +msgid "max applied to section relative value" +msgstr "" + -+#: expression.cc:610 ++#: expression.cc:687 +msgid "min applied to section relative value" +msgstr "" + -+#: expression.cc:740 ++#: expression.cc:828 +msgid "aligning to section relative value" +msgstr "" + -+#: expression.cc:895 ++#: expression.cc:993 +#, c-format +msgid "unknown constant %s" +msgstr "" + -+#: expression.cc:1126 -+msgid "SEGMENT_START not implemented" -+msgstr "" -+ -+#: expression.cc:1135 -+msgid "ORIGIN not implemented" -+msgstr "" -+ -+#: expression.cc:1141 -+msgid "LENGTH not implemented" -+msgstr "" -+ -+#: fileread.cc:65 ++#: fileread.cc:141 +#, c-format +msgid "munmap failed: %s" +msgstr "" + -+#: fileread.cc:129 ++#: fileread.cc:209 +#, c-format +msgid "%s: fstat failed: %s" +msgstr "" + -+#: fileread.cc:169 ++#: fileread.cc:250 +#, c-format +msgid "could not reopen file %s" +msgstr "" + -+#: fileread.cc:302 ++#: fileread.cc:401 +#, c-format +msgid "%s: pread failed: %s" +msgstr "" + -+#: fileread.cc:308 ++#: fileread.cc:415 +#, c-format +msgid "%s: file too short: read only %lld of %lld bytes at %lld" +msgstr "" + -+#: fileread.cc:372 ++#: fileread.cc:538 +#, c-format +msgid "" +"%s: attempt to map %lld bytes at offset %lld exceeds size of file; the file " +"may be corrupt" +msgstr "" + -+#: fileread.cc:402 -+#, c-format -+msgid "%s: mmap offset %lld size %lld failed: %s" -+msgstr "" -+ -+#: fileread.cc:548 ++#: fileread.cc:678 +#, c-format +msgid "%s: lseek failed: %s" +msgstr "" + -+#: fileread.cc:554 ++#: fileread.cc:684 +#, c-format +msgid "%s: readv failed: %s" +msgstr "" + -+#: fileread.cc:557 ++#: fileread.cc:687 +#, c-format +msgid "%s: file too short: read only %zd of %zd bytes at %lld" +msgstr "" + -+#: fileread.cc:706 ++#: fileread.cc:854 +#, c-format +msgid "%s: total bytes mapped for read: %llu\n" +msgstr "" + -+#: fileread.cc:708 ++#: fileread.cc:856 +#, c-format +msgid "%s: maximum bytes mapped for read at one time: %llu\n" +msgstr "" + -+#: fileread.cc:791 ++#: fileread.cc:949 +#, c-format +msgid "%s: stat failed: %s" +msgstr "" + -+#: fileread.cc:849 ++#: fileread.cc:1046 +#, c-format +msgid "cannot find %s%s" +msgstr "" + -+#: fileread.cc:880 ++#: fileread.cc:1071 +#, c-format +msgid "cannot find %s" +msgstr "" + -+#: fileread.cc:904 ++#: fileread.cc:1110 +#, c-format +msgid "cannot open %s: %s" +msgstr "" + ++#: gdb-index.cc:369 ++#, c-format ++msgid "%s: --gdb-index currently supports only C and C++ languages" ++msgstr "" ++ ++#. The top level DIE should be one of the above. ++#: gdb-index.cc:390 ++#, c-format ++msgid "%s: top level DIE is not DW_TAG_compile_unit or DW_TAG_type_unit" ++msgstr "" ++ ++#: gdb-index.cc:844 ++#, c-format ++msgid "" ++"%s: DWARF info may be corrupt; low_pc and high_pc are in different sections" ++msgstr "" ++ ++#: gdb-index.cc:970 ++#, c-format ++msgid "%s: DWARF CUs: %u\n" ++msgstr "" ++ ++#: gdb-index.cc:972 ++#, c-format ++msgid "%s: DWARF CUs without pubnames/pubtypes: %u\n" ++msgstr "" ++ ++#: gdb-index.cc:974 ++#, c-format ++msgid "%s: DWARF TUs: %u\n" ++msgstr "" ++ ++#: gdb-index.cc:976 ++#, c-format ++msgid "%s: DWARF TUs without pubnames/pubtypes: %u\n" ++msgstr "" ++ ++#: gdb-index.h:149 ++msgid "** gdb_index" ++msgstr "" ++ +#: gold-threads.cc:103 +#, c-format +msgid "pthead_mutextattr_init failed: %s" @@ -2392889,12 +2403974,12 @@ index 0000000..d58054a +msgid "pthread_mutex_destroy failed: %s" +msgstr "" + -+#: gold-threads.cc:131 gold-threads.cc:382 ++#: gold-threads.cc:131 gold-threads.cc:396 +#, c-format +msgid "pthread_mutex_lock failed: %s" +msgstr "" + -+#: gold-threads.cc:139 gold-threads.cc:394 ++#: gold-threads.cc:139 gold-threads.cc:410 +#, c-format +msgid "pthread_mutex_unlock failed: %s" +msgstr "" @@ -2392924,160 +2404009,277 @@ index 0000000..d58054a +msgid "pthread_cond_broadcast failed: %s" +msgstr "" + -+#: gold-threads.cc:388 ++#: gold-threads.cc:403 +#, c-format +msgid "pthread_once failed: %s" +msgstr "" + -+#: gold.cc:91 ++#: gold.cc:101 +#, c-format +msgid "%s: internal error in %s, at %s:%d\n" +msgstr "" + -+#: gold.cc:173 ++#: gold.cc:191 +msgid "no input files" +msgstr "" + -+#: gold.cc:226 ++#: gold.cc:221 ++msgid "linking with --incremental-full" ++msgstr "" ++ ++#: gold.cc:223 ++msgid "restart link with --incremental-full" ++msgstr "" ++ ++#: gold.cc:285 +msgid "cannot mix -r with --gc-sections or --icf" +msgstr "" + -+#: gold.cc:407 ++#: gold.cc:612 +#, c-format +msgid "cannot mix -static with dynamic object %s" +msgstr "" + -+#: gold.cc:411 ++#: gold.cc:616 +#, c-format +msgid "cannot mix -r with dynamic object %s" +msgstr "" + -+#: gold.cc:415 ++#: gold.cc:620 +#, c-format +msgid "cannot use non-ELF output format with dynamic object %s" +msgstr "" + -+#: gold.cc:427 ++#: gold.cc:632 +#, c-format +msgid "cannot mix split-stack '%s' and non-split-stack '%s' when using -r" +msgstr "" + +#. FIXME: This needs to specify the location somehow. -+#: i386.cc:232 i386.cc:1669 sparc.cc:234 sparc.cc:2395 x86_64.cc:237 -+#: x86_64.cc:1732 ++#: i386.cc:601 i386.cc:2655 sparc.cc:312 sparc.cc:3185 x86_64.cc:746 ++#: x86_64.cc:3250 +msgid "missing expected TLS relocation" +msgstr "" + -+#: i386.cc:944 x86_64.cc:1068 ++#: i386.cc:1699 sparc.cc:2229 tilegx.cc:3209 x86_64.cc:2279 +#, c-format -+msgid "section symbol %u has bad shndx %u" ++msgid "%s: unsupported TLS reloc %u for IFUNC symbol" +msgstr "" + -+#: i386.cc:1036 i386.cc:1060 sparc.cc:1777 x86_64.cc:1176 x86_64.cc:1204 ++#: i386.cc:2809 i386.cc:3558 powerpc.cc:7521 sparc.cc:3583 tilegx.cc:4706 ++#: x86_64.cc:3465 x86_64.cc:4205 +#, c-format -+msgid "local symbol %u has bad shndx %u" ++msgid "unexpected reloc %u in object file" +msgstr "" + -+#: i386.cc:1991 ++#: i386.cc:3002 +msgid "both SUN and GNU model TLS relocations" +msgstr "" + -+#: i386.cc:2730 x86_64.cc:2719 ++#: i386.cc:3572 ++#, c-format ++msgid "unsupported reloc %u in object file" ++msgstr "" ++ ++#: i386.cc:3802 x86_64.cc:4459 +#, c-format +msgid "failed to match split-stack sequence at section %u offset %0zx" +msgstr "" + -+#: icf.cc:616 ++#: icf.cc:768 +#, c-format +msgid "%s: ICF Converged after %u iteration(s)" +msgstr "" + -+#: icf.cc:619 ++#: icf.cc:771 +#, c-format +msgid "%s: ICF stopped after %u iteration(s)" +msgstr "" + -+#: icf.cc:633 ++#: icf.cc:785 +#, c-format +msgid "Could not find symbol %s to unfold\n" +msgstr "" + -+#: incremental.cc:242 ++#: incremental.cc:80 ++msgid "** incremental_inputs" ++msgstr "" ++ ++#: incremental.cc:145 +#, c-format +msgid "the link might take longer: cannot perform incremental link: %s" +msgstr "" + -+#: incremental.cc:302 ++#: incremental.cc:411 +msgid "no incremental data from previous build" +msgstr "" + -+#: incremental.cc:309 incremental.cc:332 -+msgid "invalid incremental build data" -+msgstr "" -+ -+#: incremental.cc:321 ++#: incremental.cc:417 +msgid "different version of incremental build data" +msgstr "" + -+#: incremental.cc:338 ++#: incremental.cc:429 +msgid "command line changed" +msgstr "" + -+#: incremental.cc:362 ++#: incremental.cc:456 ++#, c-format ++msgid "%s: script file changed" ++msgstr "" ++ ++#: incremental.cc:859 +#, c-format +msgid "unsupported ELF machine number %d" +msgstr "" + -+#: incremental.cc:387 ++#: incremental.cc:867 object.cc:3063 ++#, c-format ++msgid "%s: incompatible target" ++msgstr "" ++ ++#: incremental.cc:889 +msgid "output is not an ELF file." +msgstr "" + -+#: incremental.cc:410 ++#: incremental.cc:912 +msgid "unsupported file: 32-bit, big-endian" +msgstr "" + -+#: incremental.cc:419 ++#: incremental.cc:921 +msgid "unsupported file: 32-bit, little-endian" +msgstr "" + -+#: incremental.cc:431 ++#: incremental.cc:933 +msgid "unsupported file: 64-bit, big-endian" +msgstr "" + -+#: incremental.cc:440 ++#: incremental.cc:942 +msgid "unsupported file: 64-bit, little-endian" +msgstr "" + -+#: layout.cc:1887 ++#: incremental.cc:2078 ++msgid "COMDAT group has no signature" ++msgstr "" ++ ++#: incremental.cc:2084 ++#, c-format ++msgid "COMDAT group %s included twice in incremental link" ++msgstr "" ++ ++#: int_encoding.cc:50 int_encoding.cc:83 ++msgid "Unusually large LEB128 decoded, debug information may be corrupted" ++msgstr "" ++ ++#: layout.cc:225 ++#, c-format ++msgid "%s: total free lists: %u\n" ++msgstr "" ++ ++#: layout.cc:227 ++#, c-format ++msgid "%s: total free list nodes: %u\n" ++msgstr "" ++ ++#: layout.cc:229 ++#, c-format ++msgid "%s: calls to Free_list::remove: %u\n" ++msgstr "" ++ ++#: layout.cc:231 layout.cc:235 ++#, c-format ++msgid "%s: nodes visited: %u\n" ++msgstr "" ++ ++#: layout.cc:233 ++#, c-format ++msgid "%s: calls to Free_list::allocate: %u\n" ++msgstr "" ++ ++#: layout.cc:946 ++#, c-format ++msgid "" ++"Unable to create output section '%s' because it is not allowed by the " ++"SECTIONS clause of the linker script" ++msgstr "" ++ ++#: layout.cc:2015 ++msgid "" ++"multiple '.interp' sections in input files may cause confusing PT_INTERP " ++"segment" ++msgstr "" ++ ++#: layout.cc:2079 ++#, c-format ++msgid "%s: missing .note.GNU-stack section implies executable stack" ++msgstr "" ++ ++#: layout.cc:2091 ++#, c-format ++msgid "%s: requires executable stack" ++msgstr "" ++ ++#: layout.cc:2590 ++#, c-format ++msgid "unable to open --section-ordering-file file %s: %s" ++msgstr "" ++ ++#: layout.cc:3024 +#, c-format +msgid "--build-id=uuid failed: could not open /dev/urandom: %s" +msgstr "" + -+#: layout.cc:1894 ++#: layout.cc:3031 +#, c-format +msgid "/dev/urandom: read failed: %s" +msgstr "" + -+#: layout.cc:1896 ++#: layout.cc:3033 +#, c-format +msgid "/dev/urandom: expected %zu bytes, got %zd bytes" +msgstr "" + -+#: layout.cc:1918 ++#: layout.cc:3055 +#, c-format +msgid "--build-id argument '%s' not a valid hex number" +msgstr "" + -+#: layout.cc:1924 ++#: layout.cc:3061 +#, c-format +msgid "unrecognized --build-id argument '%s'" +msgstr "" + -+#: layout.cc:2337 ++#: layout.cc:3626 +#, c-format +msgid "load segment overlap [0x%llx -> 0x%llx] and [0x%llx -> 0x%llx]" +msgstr "" + ++#: layout.cc:3785 output.cc:4557 ++#, c-format ++msgid "out of patch space for section %s; relink with --incremental-full" ++msgstr "" ++ ++#: layout.cc:3794 output.cc:4565 ++#, c-format ++msgid "%s: section changed size; relink with --incremental-full" ++msgstr "" ++ ++#: layout.cc:4051 ++msgid "out of patch space for symbol table; relink with --incremental-full" ++msgstr "" ++ ++#: layout.cc:4122 ++msgid "" ++"out of patch space for section header table; relink with --incremental-full" ++msgstr "" ++ ++#: layout.cc:4840 ++msgid "read-only segment has dynamic relocations" ++msgstr "" ++ ++#: layout.cc:4843 ++msgid "shared library text segment is not shareable" ++msgstr "" ++ +#: mapfile.cc:70 +#, c-format +msgid "cannot open map file %s: %s" @@ -2393117,7 +2404319,7 @@ index 0000000..d58054a +"\n" +msgstr "" + -+#: mapfile.cc:361 ++#: mapfile.cc:367 +#, c-format +msgid "" +"\n" @@ -2393125,162 +2404327,168 @@ index 0000000..d58054a +"\n" +msgstr "" + -+#: merge.cc:455 ++#: merge.cc:493 +#, c-format +msgid "%s: %s merged constants size: %lu; input: %zu; output: %zu\n" +msgstr "" + -+#: merge.cc:478 ++#: merge.cc:520 +msgid "mergeable string section length not multiple of character size" +msgstr "" + -+#: merge.cc:494 ++#: merge.cc:529 +#, c-format +msgid "%s: last entry in mergeable string section '%s' not null terminated" +msgstr "" + -+#: merge.cc:613 ++#: merge.cc:604 +#, c-format -+msgid "%s: %s input: %zu\n" ++msgid "" ++"%s: section %s contains incorrectly aligned strings; the alignment of those " ++"strings won't be preserved" +msgstr "" + -+#: merge.h:300 ++#: merge.cc:726 ++#, c-format ++msgid "%s: %s input bytes: %zu\n" ++msgstr "" ++ ++#: merge.cc:728 ++#, c-format ++msgid "%s: %s input strings: %zu\n" ++msgstr "" ++ ++#: merge.h:366 +msgid "** merge constants" +msgstr "" + -+#: merge.h:422 ++#: merge.h:495 +msgid "** merge strings" +msgstr "" + -+#: object.cc:75 -+msgid "missing SHT_SYMTAB_SHNDX section" -+msgstr "" -+ -+#: object.cc:119 -+#, c-format -+msgid "symbol %u out of range for SHT_SYMTAB_SHNDX section" -+msgstr "" -+ -+#: object.cc:126 -+#, c-format -+msgid "extended index for symbol %u out of range: %u" -+msgstr "" -+ -+#: object.cc:148 object.cc:2331 output.cc:4052 ++#: nacl.cc:43 object.cc:174 object.cc:3111 output.cc:5185 +#, c-format +msgid "%s: %s" +msgstr "" + -+#: object.cc:190 ++#: object.cc:101 ++msgid "missing SHT_SYMTAB_SHNDX section" ++msgstr "" ++ ++#: object.cc:145 ++#, c-format ++msgid "symbol %u out of range for SHT_SYMTAB_SHNDX section" ++msgstr "" ++ ++#: object.cc:152 ++#, c-format ++msgid "extended index for symbol %u out of range: %u" ++msgstr "" ++ ++#: object.cc:207 +#, c-format +msgid "section name section has wrong type: %u" +msgstr "" + -+#: object.cc:546 -+#, c-format -+msgid "invalid symbol table name index: %u" -+msgstr "" -+ -+#: object.cc:552 -+#, c-format -+msgid "symbol table name section has wrong type: %u" -+msgstr "" -+ -+#: object.cc:641 ++#: object.cc:914 +#, c-format +msgid "section group %u info %u out of range" +msgstr "" + -+#: object.cc:660 ++#: object.cc:933 +#, c-format +msgid "symbol %u name offset %u out of range" +msgstr "" + -+#: object.cc:678 ++#: object.cc:951 +#, c-format +msgid "symbol %u invalid section index %u" +msgstr "" + -+#: object.cc:723 ++#: object.cc:1003 +#, c-format +msgid "section %u in section group %u out of range" +msgstr "" + -+#: object.cc:731 ++#: object.cc:1011 +#, c-format +msgid "invalid section group %u refers to earlier section %u" +msgstr "" + -+#: object.cc:1037 reloc.cc:271 reloc.cc:838 ++#: object.cc:1380 reloc.cc:290 reloc.cc:939 +#, c-format +msgid "relocation section %u has bad info %u" +msgstr "" + -+#: object.cc:1231 ++#: object.cc:1610 +#, c-format +msgid "%s: removing unused section from '%s' in file '%s'" +msgstr "" + -+#: object.cc:1257 ++#: object.cc:1636 +#, c-format +msgid "%s: ICF folding section '%s' in file '%s'into '%s' in file '%s'" +msgstr "" + -+#: object.cc:1454 ++#: object.cc:1927 +msgid "size of symbols is not multiple of symbol size" +msgstr "" + -+#: object.cc:1563 ++#: object.cc:2156 +#, c-format +msgid "local symbol %u section name out of range: %u >= %u" +msgstr "" + -+#: object.cc:1652 ++#: object.cc:2246 +#, c-format +msgid "unknown section index %u for local symbol %u" +msgstr "" + -+#: object.cc:1661 ++#: object.cc:2256 +#, c-format +msgid "local symbol %u section index %u out of range" +msgstr "" + -+#: object.cc:2169 ++#: object.cc:2826 reloc.cc:870 ++#, c-format ++msgid "could not decompress section %s" ++msgstr "" ++ ++#: object.cc:2942 +#, c-format +msgid "%s is not supported but is required for %s in %s" +msgstr "" + -+#: object.cc:2273 ++#: object.cc:3019 ++msgid "function " ++msgstr "" ++ ++#: object.cc:3053 +#, c-format +msgid "%s: unsupported ELF machine number %d" +msgstr "" + -+#: object.cc:2283 -+#, c-format -+msgid "%s: incompatible target" -+msgstr "" -+ -+#: object.cc:2347 plugin.cc:1019 ++#: object.cc:3127 plugin.cc:1822 +#, c-format +msgid "%s: not configured to support 32-bit big-endian object" +msgstr "" + -+#: object.cc:2363 plugin.cc:1028 ++#: object.cc:3143 plugin.cc:1831 +#, c-format +msgid "%s: not configured to support 32-bit little-endian object" +msgstr "" + -+#: object.cc:2382 plugin.cc:1040 ++#: object.cc:3162 plugin.cc:1843 +#, c-format +msgid "%s: not configured to support 64-bit big-endian object" +msgstr "" + -+#: object.cc:2398 plugin.cc:1049 ++#: object.cc:3178 plugin.cc:1852 +#, c-format +msgid "%s: not configured to support 64-bit little-endian object" +msgstr "" + -+#: options.cc:156 ++#: options.cc:157 +#, c-format +msgid "" +"Usage: %s [options] file...\n" @@ -2393289,1295 +2404497,2029 @@ index 0000000..d58054a + +#. config.guess and libtool.m4 look in ld --help output for the +#. string "supported targets". -+#: options.cc:164 ++#: options.cc:165 +#, c-format +msgid "%s: supported targets:" +msgstr "" + -+#: options.cc:176 ++#: options.cc:174 ++#, c-format ++msgid "%s: supported emulations:" ++msgstr "" ++ ++#: options.cc:186 +#, c-format +msgid "Report bugs to %s\n" +msgstr "" + -+#: options.cc:193 options.cc:203 options.cc:213 ++#: options.cc:203 options.cc:213 options.cc:223 +#, c-format +msgid "%s: invalid option value (expected an integer): %s" +msgstr "" + -+#: options.cc:223 ++#: options.cc:233 options.cc:244 +#, c-format +msgid "%s: invalid option value (expected a floating point number): %s" +msgstr "" + -+#: options.cc:232 ++#: options.cc:253 +#, c-format +msgid "%s: must take a non-empty argument" +msgstr "" + -+#: options.cc:273 ++#: options.cc:294 +#, c-format +msgid "%s: must take one of the following arguments: %s" +msgstr "" + -+#: options.cc:300 ++#: options.cc:325 +#, c-format +msgid " Supported targets:\n" +msgstr "" + -+#: options.cc:409 ++#: options.cc:333 ++#, c-format ++msgid " Supported emulations:\n" ++msgstr "" ++ ++#: options.cc:476 ++msgid "invalid argument to --section-start; must be SECTION=ADDRESS" ++msgstr "" ++ ++#: options.cc:489 ++msgid "--section-start address missing" ++msgstr "" ++ ++#: options.cc:498 ++#, c-format ++msgid "--section-start argument %s is not a valid hex number" ++msgstr "" ++ ++#: options.cc:535 +#, c-format +msgid "unable to parse script file %s" +msgstr "" + -+#: options.cc:417 ++#: options.cc:543 +#, c-format +msgid "unable to parse version script file %s" +msgstr "" + -+#: options.cc:425 ++#: options.cc:551 +#, c-format +msgid "unable to parse dynamic-list script file %s" +msgstr "" + -+#: options.cc:522 ++#: options.cc:663 +#, c-format +msgid "" +"format '%s' not supported; treating as elf (supported formats: elf, binary)" +msgstr "" + -+#: options.cc:538 ++#: options.cc:705 +#, c-format +msgid "%s: use the --help option for usage information\n" +msgstr "" + -+#: options.cc:547 ++#: options.cc:714 +#, c-format +msgid "%s: %s: %s\n" +msgstr "" + -+#: options.cc:651 ++#: options.cc:818 +msgid "unexpected argument" +msgstr "" + -+#: options.cc:664 options.cc:725 ++#: options.cc:831 options.cc:892 +msgid "missing argument" +msgstr "" + -+#: options.cc:736 ++#: options.cc:903 +msgid "unknown -z option" +msgstr "" + -+#: options.cc:935 ++#: options.cc:1115 +#, c-format +msgid "ignoring --threads: %s was compiled without thread support" +msgstr "" + -+#: options.cc:942 ++#: options.cc:1122 +#, c-format +msgid "ignoring --thread-count: %s was compiled without thread support" +msgstr "" + -+#: options.cc:981 ++#: options.cc:1176 +#, c-format +msgid "unable to open -retain-symbols-file file %s: %s" +msgstr "" + -+#: options.cc:1003 ++#: options.cc:1213 +msgid "-shared and -static are incompatible" +msgstr "" + -+#: options.cc:1005 ++#: options.cc:1215 +msgid "-shared and -pie are incompatible" +msgstr "" + -+#: options.cc:1008 ++#: options.cc:1217 ++msgid "-pie and -static are incompatible" ++msgstr "" ++ ++#: options.cc:1220 +msgid "-shared and -r are incompatible" +msgstr "" + -+#: options.cc:1010 ++#: options.cc:1222 +msgid "-pie and -r are incompatible" +msgstr "" + -+#: options.cc:1014 ++#: options.cc:1227 ++msgid "-F/--filter may not used without -shared" ++msgstr "" ++ ++#: options.cc:1229 ++msgid "-f/--auxiliary may not be used without -shared" ++msgstr "" ++ ++#: options.cc:1234 +msgid "-retain-symbols-file does not yet work with -r" +msgstr "" + -+#: options.cc:1020 ++#: options.cc:1240 +msgid "binary output format not compatible with -shared or -pie or -r" +msgstr "" + -+#: options.cc:1026 ++#: options.cc:1246 +#, c-format +msgid "--hash-bucket-empty-fraction value %g out of range [0.0, 1.0)" +msgstr "" + -+#: options.cc:1031 ++#: options.cc:1251 +msgid "" +"Options --incremental-changed, --incremental-unchanged, --incremental-" +"unknown require the use of --incremental" +msgstr "" + -+#: options.cc:1097 ++#: options.cc:1261 ++msgid "incremental linking is not compatible with -r" ++msgstr "" ++ ++#: options.cc:1263 ++msgid "incremental linking is not compatible with --emit-relocs" ++msgstr "" ++ ++#: options.cc:1266 ++msgid "incremental linking is not compatible with --plugin" ++msgstr "" ++ ++#: options.cc:1269 ++msgid "ignoring --gc-sections for an incremental link" ++msgstr "" ++ ++#: options.cc:1274 ++msgid "ignoring --icf for an incremental link" ++msgstr "" ++ ++#: options.cc:1279 ++msgid "ignoring --compress-debug-sections for an incremental link" ++msgstr "" ++ ++#: options.cc:1359 +msgid "May not nest groups" +msgstr "" + -+#: options.cc:1109 ++#: options.cc:1361 ++msgid "may not nest groups in libraries" ++msgstr "" ++ ++#: options.cc:1373 +msgid "Group end without group start" +msgstr "" + ++#: options.cc:1383 ++msgid "may not nest libraries" ++msgstr "" ++ ++#: options.cc:1385 ++msgid "may not nest libraries in groups" ++msgstr "" ++ ++#: options.cc:1397 ++msgid "lib end without lib start" ++msgstr "" ++ +#. I guess it's neither a long option nor a short option. -+#: options.cc:1174 ++#: options.cc:1462 +msgid "unknown option" +msgstr "" + -+#: options.cc:1201 ++#: options.cc:1489 +#, c-format +msgid "%s: missing group end\n" +msgstr "" + -+#: options.h:571 ++#: options.h:624 +msgid "Report usage information" +msgstr "" + -+#: options.h:573 ++#: options.h:626 +msgid "Report version information" +msgstr "" + -+#: options.h:575 ++#: options.h:628 +msgid "Report version and target information" +msgstr "" + -+#: options.h:584 options.h:635 ++#: options.h:637 options.h:712 +msgid "Not supported" +msgstr "" + -+#: options.h:585 options.h:636 ++#: options.h:638 options.h:713 +msgid "Do not copy DT_NEEDED tags from shared libraries" +msgstr "" + -+#: options.h:588 ++#: options.h:641 options.h:1289 ++msgid "Allow multiple definitions of symbols" ++msgstr "" ++ ++#: options.h:642 ++msgid "Do not allow multiple definitions" ++msgstr "" ++ ++#: options.h:645 +msgid "Allow unresolved references in shared libraries" +msgstr "" + -+#: options.h:589 ++#: options.h:646 +msgid "Do not allow unresolved references in shared libraries" +msgstr "" + -+#: options.h:592 ++#: options.h:649 +msgid "Only set DT_NEEDED for shared libraries if used" +msgstr "" + -+#: options.h:593 ++#: options.h:650 +msgid "Always DT_NEEDED for shared libraries" +msgstr "" + -+#: options.h:600 ++#: options.h:653 options.h:831 options.h:1197 options.h:1207 ++msgid "Ignored" ++msgstr "" ++ ++#: options.h:653 ++msgid "[ignored]" ++msgstr "" ++ ++#: options.h:661 +msgid "Set input format" +msgstr "" + -+#: options.h:603 ++#: options.h:664 +msgid "-l searches for shared libraries" +msgstr "" + -+#: options.h:605 ++#: options.h:666 +msgid "-l does not search for shared libraries" +msgstr "" + -+#: options.h:609 ++#: options.h:669 ++msgid "alias for -Bdynamic" ++msgstr "" ++ ++#: options.h:671 ++msgid "alias for -Bstatic" ++msgstr "" ++ ++#: options.h:674 ++msgid "Use group name lookup rules for shared library" ++msgstr "" ++ ++#: options.h:677 +msgid "Bind defined symbols locally" +msgstr "" + -+#: options.h:612 ++#: options.h:680 +msgid "Bind defined function symbols locally" +msgstr "" + -+#: options.h:615 ++#: options.h:683 +msgid "Generate build ID note" +msgstr "" + -+#: options.h:616 options.h:655 ++#: options.h:684 options.h:740 +msgid "[=STYLE]" +msgstr "" + -+#: options.h:619 -+msgid "Check segment addresses for overlaps (default)" -+msgstr "" -+ -+#: options.h:620 -+msgid "Do not check segment addresses for overlaps" -+msgstr "" -+ -+#: options.h:624 options.h:629 -+msgid "Compress .debug_* sections in the output file" -+msgstr "" -+ -+#: options.h:630 -+msgid "[none]" -+msgstr "" -+ -+#: options.h:639 -+msgid "Define common symbols" -+msgstr "" -+ -+#: options.h:640 -+msgid "Do not define common symbols" -+msgstr "" -+ -+#: options.h:642 options.h:644 -+msgid "Alias for -d" -+msgstr "" -+ -+#: options.h:647 -+msgid "Turn on debugging" -+msgstr "" -+ -+#: options.h:648 -+msgid "[all,files,script,task][,...]" -+msgstr "" -+ -+#: options.h:651 -+msgid "Define a symbol" -+msgstr "" -+ -+#: options.h:651 -+msgid "SYMBOL=EXPRESSION" -+msgstr "" -+ -+#: options.h:654 -+msgid "Demangle C++ symbols in log messages" -+msgstr "" -+ -+#: options.h:658 -+msgid "Do not demangle C++ symbols in log messages" -+msgstr "" -+ -+#: options.h:662 -+msgid "Try to detect violations of the One Definition Rule" -+msgstr "" -+ -+#: options.h:666 -+msgid "Delete all temporary local symbols" -+msgstr "" -+ -+#: options.h:669 -+msgid "Add data symbols to dynamic symbols" -+msgstr "" -+ -+#: options.h:672 -+msgid "Add C++ operator new/delete to dynamic symbols" -+msgstr "" -+ -+#: options.h:675 -+msgid "Add C++ typeinfo to dynamic symbols" -+msgstr "" -+ -+#: options.h:678 -+msgid "Read a list of dynamic symbols" -+msgstr "" -+ -+#: options.h:678 options.h:732 options.h:766 options.h:893 options.h:921 -+msgid "FILE" -+msgstr "" -+ -+#: options.h:681 -+msgid "Set program start address" -+msgstr "" -+ -+#: options.h:681 options.h:908 options.h:910 options.h:912 -+msgid "ADDRESS" -+msgstr "" -+ -+#: options.h:684 -+msgid "Exclude libraries from automatic export" -+msgstr "" -+ +#: options.h:688 -+msgid "Export all dynamic symbols" ++msgid "Chunk size for '--build-id=tree'" +msgstr "" + -+#: options.h:689 -+msgid "Do not export all dynamic symbols (default)" -+msgstr "" -+ -+#: options.h:692 -+msgid "Create exception frame header" -+msgstr "" -+ -+#: options.h:695 -+msgid "Treat warnings as errors" -+msgstr "" -+ -+#: options.h:696 -+msgid "Do not treat warnings as errors" -+msgstr "" -+ -+#: options.h:699 -+msgid "Call SYMBOL at unload-time" -+msgstr "" -+ -+#: options.h:699 options.h:729 options.h:873 options.h:915 options.h:936 -+#: options.h:939 -+msgid "SYMBOL" -+msgstr "" -+ -+#: options.h:702 -+msgid "Set shared library name" -+msgstr "" -+ -+#: options.h:702 options.h:792 -+msgid "FILENAME" -+msgstr "" -+ -+#: options.h:705 -+msgid "Min fraction of empty buckets in dynamic hash" -+msgstr "" -+ -+#: options.h:706 -+msgid "FRACTION" -+msgstr "" -+ -+#: options.h:709 -+msgid "Dynamic hash style" -+msgstr "" -+ -+#: options.h:709 -+msgid "[sysv,gnu,both]" -+msgstr "" -+ -+#: options.h:713 -+msgid "Set dynamic linker path" -+msgstr "" -+ -+#: options.h:713 -+msgid "PROGRAM" -+msgstr "" -+ -+#: options.h:716 -+msgid "Work in progress; do not use" -+msgstr "" -+ -+#: options.h:717 -+msgid "Do a full build" -+msgstr "" -+ -+#: options.h:720 -+msgid "Assume files changed" -+msgstr "" -+ -+#: options.h:723 -+msgid "Assume files didn't change" -+msgstr "" -+ -+#: options.h:726 -+msgid "Use timestamps to check files (default)" -+msgstr "" -+ -+#: options.h:729 -+msgid "Call SYMBOL at load-time" -+msgstr "" -+ -+#: options.h:732 -+msgid "Read only symbol values from FILE" -+msgstr "" -+ -+#: options.h:735 -+msgid "Search for library LIBNAME" -+msgstr "" -+ -+#: options.h:735 -+msgid "LIBNAME" -+msgstr "" -+ -+#: options.h:738 -+msgid "Add directory to search path" -+msgstr "" -+ -+#: options.h:738 options.h:813 options.h:816 options.h:820 options.h:887 -+msgid "DIR" -+msgstr "" -+ -+#: options.h:741 -+msgid "Ignored for compatibility" -+msgstr "" -+ -+#: options.h:741 -+msgid "EMULATION" -+msgstr "" -+ -+#: options.h:744 -+msgid "Write map file on standard output" -+msgstr "" -+ -+#: options.h:745 -+msgid "Write map file" -+msgstr "" -+ -+#: options.h:746 -+msgid "MAPFILENAME" -+msgstr "" -+ -+#: options.h:749 -+msgid "Do not page align data" -+msgstr "" -+ -+#: options.h:751 -+msgid "Do not page align data, do not make text readonly" -+msgstr "" -+ -+#: options.h:752 -+msgid "Page align data, make text readonly" -+msgstr "" -+ -+#: options.h:755 -+msgid "Enable use of DT_RUNPATH and DT_FLAGS" -+msgstr "" -+ -+#: options.h:756 -+msgid "Disable use of DT_RUNPATH and DT_FLAGS" -+msgstr "" -+ -+#: options.h:759 -+msgid "Create an output file even if errors occur" -+msgstr "" -+ -+#: options.h:762 options.h:958 -+msgid "Report undefined symbols (even with --shared)" -+msgstr "" -+ -+#: options.h:766 -+msgid "Set output file name" -+msgstr "" -+ -+#: options.h:769 -+msgid "Optimize output file size" -+msgstr "" -+ -+#: options.h:769 -+msgid "LEVEL" -+msgstr "" -+ -+#: options.h:772 -+msgid "Set output format" -+msgstr "" -+ -+#: options.h:772 -+msgid "[binary]" -+msgstr "" -+ -+#: options.h:775 options.h:777 -+msgid "Create a position independent executable" -+msgstr "" -+ -+#: options.h:782 -+msgid "Load a plugin library" -+msgstr "" -+ -+#: options.h:782 -+msgid "PLUGIN" -+msgstr "" -+ -+#: options.h:784 -+msgid "Pass an option to the plugin" -+msgstr "" -+ -+#: options.h:784 -+msgid "OPTION" -+msgstr "" -+ -+#: options.h:788 -+msgid "Preread archive symbols when multi-threaded" -+msgstr "" -+ -+#: options.h:791 -+msgid "Print symbols defined and used for each input" -+msgstr "" -+ -+#: options.h:795 -+msgid "Ignored for SVR4 compatibility" -+msgstr "" -+ -+#: options.h:798 -+msgid "Generate relocations in output" -+msgstr "" -+ -+#: options.h:801 -+msgid "Generate relocatable output" -+msgstr "" -+ -+#: options.h:804 -+msgid "Relax branches on certain targets" -+msgstr "" -+ -+#: options.h:807 -+msgid "keep only symbols listed in this file" -+msgstr "" -+ -+#: options.h:807 -+msgid "[file]" -+msgstr "" -+ -+#: options.h:813 options.h:816 -+msgid "Add DIR to runtime search path" -+msgstr "" -+ -+#: options.h:819 -+msgid "Add DIR to link time shared library search path" -+msgstr "" -+ -+#: options.h:823 -+msgid "Strip all symbols" -+msgstr "" -+ -+#: options.h:825 -+msgid "Strip debugging information" -+msgstr "" -+ -+#: options.h:827 -+msgid "Emit only debug line number information" -+msgstr "" -+ -+#: options.h:829 -+msgid "Strip debug symbols that are unused by gdb (at least versions <= 6.7)" -+msgstr "" -+ -+#: options.h:832 -+msgid "Strip LTO intermediate code sections" -+msgstr "" -+ -+#: options.h:835 -+msgid "" -+"(ARM only) The maximum distance from instructions in a group of sections to " -+"their stubs. Negative values mean stubs are always after the group. 1 means " -+"using default size.\n" -+msgstr "" -+ -+#: options.h:838 options.h:852 options.h:956 options.h:975 ++#: options.h:688 options.h:693 options.h:1086 options.h:1100 options.h:1268 ++#: options.h:1287 +msgid "SIZE" +msgstr "" + -+#: options.h:841 ++#: options.h:692 ++msgid "" ++"Minimum output file size for '--build-id=tree' to work differently than '--" ++"build-id=sha1'" ++msgstr "" ++ ++#: options.h:696 ++msgid "Check segment addresses for overlaps (default)" ++msgstr "" ++ ++#: options.h:697 ++msgid "Do not check segment addresses for overlaps" ++msgstr "" ++ ++#: options.h:701 options.h:706 ++msgid "Compress .debug_* sections in the output file" ++msgstr "" ++ ++#: options.h:707 ++msgid "[none]" ++msgstr "" ++ ++#: options.h:716 ++msgid "Output cross reference table" ++msgstr "" ++ ++#: options.h:717 ++msgid "Do not output cross reference table" ++msgstr "" ++ ++#: options.h:720 ++msgid "Use DT_INIT_ARRAY for all constructors (default)" ++msgstr "" ++ ++#: options.h:721 ++msgid "Handle constructors as directed by compiler" ++msgstr "" ++ ++#: options.h:724 ++msgid "Define common symbols" ++msgstr "" ++ ++#: options.h:725 ++msgid "Do not define common symbols" ++msgstr "" ++ ++#: options.h:727 options.h:729 ++msgid "Alias for -d" ++msgstr "" ++ ++#: options.h:732 ++msgid "Turn on debugging" ++msgstr "" ++ ++#: options.h:733 ++msgid "[all,files,script,task][,...]" ++msgstr "" ++ ++#: options.h:736 ++msgid "Define a symbol" ++msgstr "" ++ ++#: options.h:736 ++msgid "SYMBOL=EXPRESSION" ++msgstr "" ++ ++#: options.h:739 ++msgid "Demangle C++ symbols in log messages" ++msgstr "" ++ ++#: options.h:743 ++msgid "Do not demangle C++ symbols in log messages" ++msgstr "" ++ ++#: options.h:747 ++msgid "Look for violations of the C++ One Definition Rule" ++msgstr "" ++ ++#: options.h:748 ++msgid "Do not look for violations of the C++ One Definition Rule" ++msgstr "" ++ ++#: options.h:751 ++msgid "Delete all local symbols" ++msgstr "" ++ ++#: options.h:753 ++msgid "Delete all temporary local symbols" ++msgstr "" ++ ++#: options.h:756 ++msgid "Add data symbols to dynamic symbols" ++msgstr "" ++ ++#: options.h:759 ++msgid "Add C++ operator new/delete to dynamic symbols" ++msgstr "" ++ ++#: options.h:762 ++msgid "Add C++ typeinfo to dynamic symbols" ++msgstr "" ++ ++#: options.h:765 ++msgid "Read a list of dynamic symbols" ++msgstr "" ++ ++#: options.h:765 options.h:873 options.h:896 options.h:964 options.h:1033 ++#: options.h:1142 options.h:1190 ++msgid "FILE" ++msgstr "" ++ ++#: options.h:768 ++msgid "Set program start address" ++msgstr "" ++ ++#: options.h:768 options.h:1157 options.h:1159 options.h:1161 options.h:1164 ++#: options.h:1166 ++msgid "ADDRESS" ++msgstr "" ++ ++#: options.h:771 ++msgid "Exclude libraries from automatic export" ++msgstr "" ++ ++#: options.h:775 ++msgid "Export all dynamic symbols" ++msgstr "" ++ ++#: options.h:776 ++msgid "Do not export all dynamic symbols (default)" ++msgstr "" ++ ++#: options.h:779 ++msgid "Export SYMBOL to dynamic symbol table" ++msgstr "" ++ ++#: options.h:779 options.h:807 options.h:893 options.h:1122 options.h:1177 ++#: options.h:1234 options.h:1237 ++msgid "SYMBOL" ++msgstr "" ++ ++#: options.h:782 ++msgid "Link big-endian objects." ++msgstr "" ++ ++#: options.h:785 ++msgid "Link little-endian objects." ++msgstr "" ++ ++#: options.h:788 ++msgid "Create exception frame header" ++msgstr "" ++ ++#: options.h:791 ++msgid "(ARM only) Do not warn about objects with incompatible enum sizes" ++msgstr "" ++ ++#: options.h:795 ++msgid "Auxiliary filter for shared object symbol table" ++msgstr "" ++ ++#: options.h:796 options.h:800 ++msgid "SHLIB" ++msgstr "" ++ ++#: options.h:799 ++msgid "Filter for shared object symbol table" ++msgstr "" ++ ++#: options.h:803 ++msgid "Treat warnings as errors" ++msgstr "" ++ ++#: options.h:804 ++msgid "Do not treat warnings as errors" ++msgstr "" ++ ++#: options.h:807 ++msgid "Call SYMBOL at unload-time" ++msgstr "" ++ ++#: options.h:810 ++msgid "(ARM only) Fix binaries for Cortex-A8 erratum." ++msgstr "" ++ ++#: options.h:811 ++msgid "(ARM only) Do not fix binaries for Cortex-A8 erratum." ++msgstr "" ++ ++#: options.h:814 ++msgid "(ARM only) Fix binaries for ARM1176 erratum." ++msgstr "" ++ ++#: options.h:815 ++msgid "(ARM only) Do not fix binaries for ARM1176 erratum." ++msgstr "" ++ ++#: options.h:818 ++msgid "(ARM only) Merge exidx entries in debuginfo." ++msgstr "" ++ ++#: options.h:819 ++msgid "(ARM only) Do not merge exidx entries in debuginfo." ++msgstr "" ++ ++#: options.h:822 ++msgid "(ARM only) Rewrite BX rn as MOV pc, rn for ARMv4" ++msgstr "" ++ ++#: options.h:826 ++msgid "(ARM only) Rewrite BX rn branch to ARMv4 interworking veneer" ++msgstr "" ++ ++#: options.h:834 ++msgid "Generate .gdb_index section" ++msgstr "" ++ ++#: options.h:835 ++msgid "Do not generate .gdb_index section" ++msgstr "" ++ ++#: options.h:838 ++msgid "Enable STB_GNU_UNIQUE symbol binding (default)" ++msgstr "" ++ ++#: options.h:839 ++msgid "Disable STB_GNU_UNIQUE symbol binding" ++msgstr "" ++ ++#: options.h:842 ++msgid "Set shared library name" ++msgstr "" ++ ++#: options.h:842 options.h:1016 options.h:1050 ++msgid "FILENAME" ++msgstr "" ++ ++#: options.h:845 ++msgid "Min fraction of empty buckets in dynamic hash" ++msgstr "" ++ ++#: options.h:846 ++msgid "FRACTION" ++msgstr "" ++ ++#: options.h:849 ++msgid "Dynamic hash style" ++msgstr "" ++ ++#: options.h:849 ++msgid "[sysv,gnu,both]" ++msgstr "" ++ ++#: options.h:853 ++msgid "Set dynamic linker path" ++msgstr "" ++ ++#: options.h:853 ++msgid "PROGRAM" ++msgstr "" ++ ++#: options.h:856 ++msgid "" ++"Do an incremental link if possible; otherwise, do a full link and prepare " ++"output for incremental linking" ++msgstr "" ++ ++#: options.h:861 ++msgid "Do a full link (default)" ++msgstr "" ++ ++#: options.h:864 ++msgid "Do a full link and prepare output for incremental linking" ++msgstr "" ++ ++#: options.h:868 ++msgid "Do an incremental link; exit if not possible" ++msgstr "" ++ ++#: options.h:871 ++msgid "Set base file for incremental linking (default is output file)" ++msgstr "" ++ ++#: options.h:876 ++msgid "Assume files changed" ++msgstr "" ++ ++#: options.h:879 ++msgid "Assume files didn't change" ++msgstr "" ++ ++#: options.h:882 ++msgid "Use timestamps to check files (default)" ++msgstr "" ++ ++#: options.h:885 ++msgid "Assume startup files unchanged (files preceding this option)" ++msgstr "" ++ ++#: options.h:889 ++msgid "Amount of extra space to allocate for patches" ++msgstr "" ++ ++#: options.h:890 ++msgid "PERCENT" ++msgstr "" ++ ++#: options.h:893 ++msgid "Call SYMBOL at load-time" ++msgstr "" ++ ++#: options.h:896 ++msgid "Read only symbol values from FILE" ++msgstr "" ++ ++#: options.h:900 ++msgid "Map whole files to memory (default on 64-bit hosts)" ++msgstr "" ++ ++#: options.h:901 ++msgid "Map relevant file parts to memory (default on 32-bit hosts)" ++msgstr "" ++ ++#: options.h:904 ++msgid "Keep files mapped across passes (default)" ++msgstr "" ++ ++#: options.h:905 ++msgid "Release mapped files after each pass" ++msgstr "" ++ ++#: options.h:908 ++msgid "Generate unwind information for PLT (default)" ++msgstr "" ++ ++#: options.h:909 ++msgid "Do not generate unwind information for PLT" ++msgstr "" ++ ++#: options.h:912 ++msgid "Search for library LIBNAME" ++msgstr "" ++ ++#: options.h:912 ++msgid "LIBNAME" ++msgstr "" ++ ++#: options.h:915 ++msgid "Add directory to search path" ++msgstr "" ++ ++#: options.h:915 options.h:1039 options.h:1042 options.h:1046 options.h:1136 ++msgid "DIR" ++msgstr "" ++ ++#: options.h:918 ++msgid "Enable text section reordering for GCC section names (default)" ++msgstr "" ++ ++#: options.h:920 ++msgid "Disable text section reordering for GCC section names" ++msgstr "" ++ ++#: options.h:923 ++msgid "Only search directories specified on the command line." ++msgstr "" ++ ++#: options.h:927 ++msgid "Put read-only non-executable sections in their own segment" ++msgstr "" ++ ++#: options.h:931 ++msgid "Set offset between executable and read-only segments" ++msgstr "" ++ ++#: options.h:932 ++msgid "OFFSET" ++msgstr "" ++ ++#: options.h:935 ++msgid "Set GNU linker emulation; obsolete" ++msgstr "" ++ ++#: options.h:935 ++msgid "EMULATION" ++msgstr "" ++ ++#: options.h:938 ++msgid "Map the output file for writing (default)." ++msgstr "" ++ ++#: options.h:939 ++msgid "Do not map the output file for writing." ++msgstr "" ++ ++#: options.h:942 ++msgid "Write map file on standard output" ++msgstr "" ++ ++#: options.h:943 ++msgid "Write map file" ++msgstr "" ++ ++#: options.h:944 ++msgid "MAPFILENAME" ++msgstr "" ++ ++#: options.h:947 ++msgid "Do not page align data" ++msgstr "" ++ ++#: options.h:949 ++msgid "Do not page align data, do not make text readonly" ++msgstr "" ++ ++#: options.h:950 ++msgid "Page align data, make text readonly" ++msgstr "" ++ ++#: options.h:953 ++msgid "Enable use of DT_RUNPATH and DT_FLAGS" ++msgstr "" ++ ++#: options.h:954 ++msgid "Disable use of DT_RUNPATH and DT_FLAGS" ++msgstr "" ++ ++#: options.h:957 ++msgid "Create an output file even if errors occur" ++msgstr "" ++ ++#: options.h:960 options.h:1270 ++msgid "Report undefined symbols (even with --shared)" ++msgstr "" ++ ++#: options.h:964 ++msgid "Set output file name" ++msgstr "" ++ ++#: options.h:967 ++msgid "Optimize output file size" ++msgstr "" ++ ++#: options.h:967 ++msgid "LEVEL" ++msgstr "" ++ ++#: options.h:970 ++msgid "Set output format" ++msgstr "" ++ ++#: options.h:970 ++msgid "[binary]" ++msgstr "" ++ ++#: options.h:973 options.h:982 ++msgid "(ARM only) Ignore for backward compatibility" ++msgstr "" ++ ++#: options.h:976 options.h:978 ++msgid "Create a position independent executable" ++msgstr "" ++ ++#: options.h:985 ++msgid "(PowerPC64 only) Align PLT call stubs to fit cache lines" ++msgstr "" ++ ++#: options.h:986 ++msgid "[=P2ALIGN]" ++msgstr "" ++ ++#: options.h:989 ++msgid "(PowerPC64 only) PLT call stubs should load r11" ++msgstr "" ++ ++#: options.h:990 ++msgid "(PowerPC64 only) PLT call stubs should not load r11" ++msgstr "" ++ ++#: options.h:993 ++msgid "(PowerPC64 only) PLT call stubs with load-load barrier" ++msgstr "" ++ ++#: options.h:994 ++msgid "(PowerPC64 only) PLT call stubs without barrier" ++msgstr "" ++ ++#: options.h:998 ++msgid "Load a plugin library" ++msgstr "" ++ ++#: options.h:998 ++msgid "PLUGIN" ++msgstr "" ++ ++#: options.h:1000 ++msgid "Pass an option to the plugin" ++msgstr "" ++ ++#: options.h:1000 ++msgid "OPTION" ++msgstr "" ++ ++#: options.h:1004 ++msgid "Use posix_fallocate to reserve space in the output file (default)." ++msgstr "" ++ ++#: options.h:1006 ++msgid "Use fallocate or ftruncate to reserve space." ++msgstr "" ++ ++#: options.h:1009 ++msgid "Preread archive symbols when multi-threaded" ++msgstr "" ++ ++#: options.h:1012 ++msgid "Print default output format" ++msgstr "" ++ ++#: options.h:1015 ++msgid "Print symbols defined and used for each input" ++msgstr "" ++ ++#: options.h:1019 ++msgid "Ignored for SVR4 compatibility" ++msgstr "" ++ ++#: options.h:1022 ++msgid "Generate relocations in output" ++msgstr "" ++ ++#: options.h:1025 ++msgid "Generate relocatable output" ++msgstr "" ++ ++#: options.h:1027 ++msgid "Synonym for -r" ++msgstr "" ++ ++#: options.h:1030 ++msgid "Relax branches on certain targets" ++msgstr "" ++ ++#: options.h:1033 ++msgid "keep only symbols listed in this file" ++msgstr "" ++ ++#: options.h:1039 options.h:1042 ++msgid "Add DIR to runtime search path" ++msgstr "" ++ ++#: options.h:1045 ++msgid "Add DIR to link time shared library search path" ++msgstr "" ++ ++#: options.h:1049 ++msgid "Layout sections in the order specified." ++msgstr "" ++ ++#: options.h:1053 ++msgid "Set address of section" ++msgstr "" ++ ++#: options.h:1053 ++msgid "SECTION=ADDRESS" ++msgstr "" ++ ++#: options.h:1056 ++msgid "Sort common symbols by alignment" ++msgstr "" ++ ++#: options.h:1057 ++msgid "[={ascending,descending}]" ++msgstr "" ++ ++#: options.h:1060 ++msgid "" ++"Sort sections by name. '--no-text-reorder' will override '--sort-" ++"section=name' for .text" ++msgstr "" ++ ++#: options.h:1062 ++msgid "[none,name]" ++msgstr "" ++ ++#: options.h:1066 ++msgid "Dynamic tag slots to reserve (default 5)" ++msgstr "" ++ ++#: options.h:1067 options.h:1115 options.h:1148 options.h:1150 options.h:1152 ++#: options.h:1154 ++msgid "COUNT" ++msgstr "" ++ ++#: options.h:1070 ++msgid "Strip all symbols" ++msgstr "" ++ ++#: options.h:1072 ++msgid "Strip debugging information" ++msgstr "" ++ ++#: options.h:1074 ++msgid "Emit only debug line number information" ++msgstr "" ++ ++#: options.h:1076 ++msgid "Strip debug symbols that are unused by gdb (at least versions <= 7.4)" ++msgstr "" ++ ++#: options.h:1079 ++msgid "Strip LTO intermediate code sections" ++msgstr "" ++ ++#: options.h:1082 ++msgid "" ++"(ARM, PowerPC only) The maximum distance from instructions in a group of " ++"sections to their stubs. Negative values mean stubs are always after " ++"(PowerPC before) the group. 1 means use default size.\n" ++msgstr "" ++ ++#: options.h:1089 +msgid "" +"Use less memory and more disk I/O (included only for compatibility with GNU " +"ld)" +msgstr "" + -+#: options.h:845 options.h:848 ++#: options.h:1093 options.h:1096 +msgid "Generate shared library" +msgstr "" + -+#: options.h:851 ++#: options.h:1099 +msgid "Stack size when -fsplit-stack function calls non-split" +msgstr "" + -+#: options.h:857 ++#: options.h:1105 +msgid "Do not link against shared libraries" +msgstr "" + -+#: options.h:860 -+msgid "Identical Code Folding. '--icf=safe' folds only ctors and dtors." ++#: options.h:1108 ++msgid "" ++"Identical Code Folding. '--icf=safe' Folds ctors, dtors and functions whose " ++"pointers are definitely not taken." +msgstr "" + -+#: options.h:866 ++#: options.h:1115 +msgid "Number of iterations of ICF (default 2)" +msgstr "" + -+#: options.h:866 options.h:899 options.h:901 options.h:903 options.h:905 -+msgid "COUNT" -+msgstr "" -+ -+#: options.h:869 ++#: options.h:1118 +msgid "List folded identical sections on stderr" +msgstr "" + -+#: options.h:870 ++#: options.h:1119 +msgid "Do not list folded identical sections" +msgstr "" + -+#: options.h:873 ++#: options.h:1122 +msgid "Do not fold this symbol during ICF" +msgstr "" + -+#: options.h:876 ++#: options.h:1125 +msgid "Remove unused sections" +msgstr "" + -+#: options.h:877 ++#: options.h:1126 +msgid "Don't remove unused sections (default)" +msgstr "" + -+#: options.h:880 ++#: options.h:1129 +msgid "List removed unused sections on stderr" +msgstr "" + -+#: options.h:881 ++#: options.h:1130 +msgid "Do not list removed unused sections" +msgstr "" + -+#: options.h:884 ++#: options.h:1133 +msgid "Print resource usage statistics" +msgstr "" + -+#: options.h:887 ++#: options.h:1136 +msgid "Set target system root directory" +msgstr "" + -+#: options.h:890 ++#: options.h:1139 +msgid "Print the name of each input file" +msgstr "" + -+#: options.h:893 ++#: options.h:1142 +msgid "Read linker script" +msgstr "" + -+#: options.h:896 ++#: options.h:1145 +msgid "Run the linker multi-threaded" +msgstr "" + -+#: options.h:897 ++#: options.h:1146 +msgid "Do not run the linker multi-threaded" +msgstr "" + -+#: options.h:899 ++#: options.h:1148 +msgid "Number of threads to use" +msgstr "" + -+#: options.h:901 ++#: options.h:1150 +msgid "Number of threads to use in initial pass" +msgstr "" + -+#: options.h:903 ++#: options.h:1152 +msgid "Number of threads to use in middle pass" +msgstr "" + -+#: options.h:905 ++#: options.h:1154 +msgid "Number of threads to use in final pass" +msgstr "" + -+#: options.h:908 ++#: options.h:1157 +msgid "Set the address of the bss segment" +msgstr "" + -+#: options.h:910 ++#: options.h:1159 +msgid "Set the address of the data segment" +msgstr "" + -+#: options.h:912 ++#: options.h:1161 options.h:1163 +msgid "Set the address of the text segment" +msgstr "" + -+#: options.h:915 ++#: options.h:1166 ++msgid "Set the address of the rodata segment" ++msgstr "" ++ ++#: options.h:1169 ++msgid "(PowerPC64 only) Optimize TOC code sequences" ++msgstr "" ++ ++#: options.h:1170 ++msgid "(PowerPC64 only) Don't optimize TOC code sequences" ++msgstr "" ++ ++#: options.h:1173 ++msgid "(PowerPC64 only) Sort TOC and GOT sections" ++msgstr "" ++ ++#: options.h:1174 ++msgid "(PowerPC64 only) Don't sort TOC and GOT sections" ++msgstr "" ++ ++#: options.h:1177 +msgid "Create undefined reference to SYMBOL" +msgstr "" + -+#: options.h:918 ++#: options.h:1180 ++msgid "How to handle unresolved symbols" ++msgstr "" ++ ++#: options.h:1187 +msgid "Synonym for --debug=files" +msgstr "" + -+#: options.h:921 ++#: options.h:1190 +msgid "Read version script" +msgstr "" + -+#: options.h:924 ++#: options.h:1193 +msgid "Warn about duplicate common symbols" +msgstr "" + -+#: options.h:925 ++#: options.h:1194 +msgid "Do not warn about duplicate common symbols (default)" +msgstr "" + -+#: options.h:928 ++#: options.h:1200 ++msgid "Warn if the stack is executable" ++msgstr "" ++ ++#: options.h:1201 ++msgid "Do not warn if the stack is executable (default)" ++msgstr "" ++ ++#: options.h:1204 ++msgid "Don't warn about mismatched input files" ++msgstr "" ++ ++#: options.h:1210 +msgid "Warn when skipping an incompatible library" +msgstr "" + -+#: options.h:929 ++#: options.h:1211 +msgid "Don't warn when skipping an incompatible library" +msgstr "" + -+#: options.h:932 ++#: options.h:1214 ++msgid "Warn if text segment is not shareable" ++msgstr "" ++ ++#: options.h:1215 ++msgid "Do not warn if text segment is not shareable (default)" ++msgstr "" ++ ++#: options.h:1218 ++msgid "Report unresolved symbols as warnings" ++msgstr "" ++ ++#: options.h:1222 ++msgid "Report unresolved symbols as errors" ++msgstr "" ++ ++#: options.h:1226 ++msgid "(ARM only) Do not warn about objects with incompatible wchar_t sizes" ++msgstr "" ++ ++#: options.h:1230 +msgid "Include all archive contents" +msgstr "" + -+#: options.h:933 ++#: options.h:1231 +msgid "Include only needed archive contents" +msgstr "" + -+#: options.h:936 ++#: options.h:1234 +msgid "Use wrapper functions for SYMBOL" +msgstr "" + -+#: options.h:939 ++#: options.h:1237 +msgid "Trace references to symbol" +msgstr "" + -+#: options.h:942 ++#: options.h:1240 ++msgid "Allow unused version in script (default)" ++msgstr "" ++ ++#: options.h:1241 ++msgid "Do not allow unused version in script" ++msgstr "" ++ ++#: options.h:1244 +msgid "Default search path for Solaris compatibility" +msgstr "" + -+#: options.h:943 ++#: options.h:1245 +msgid "PATH" +msgstr "" + -+#: options.h:946 ++#: options.h:1248 +msgid "Start a library search group" +msgstr "" + -+#: options.h:948 ++#: options.h:1250 +msgid "End a library search group" +msgstr "" + -+#: options.h:953 ++#: options.h:1254 ++msgid "Start a library" ++msgstr "" ++ ++#: options.h:1256 ++msgid "End a library " ++msgstr "" ++ ++#: options.h:1259 ++msgid "Ignored for GCC linker option compatibility" ++msgstr "" ++ ++#: options.h:1265 +msgid "Sort dynamic relocs" +msgstr "" + -+#: options.h:954 ++#: options.h:1266 +msgid "Do not sort dynamic relocs" +msgstr "" + -+#: options.h:956 ++#: options.h:1268 +msgid "Set common page size to SIZE" +msgstr "" + -+#: options.h:961 ++#: options.h:1273 +msgid "Mark output as requiring executable stack" +msgstr "" + -+#: options.h:963 ++#: options.h:1275 +msgid "Mark DSO to be initialized first at runtime" +msgstr "" + -+#: options.h:966 ++#: options.h:1278 +msgid "Mark object to interpose all DSOs but executable" +msgstr "" + -+#: options.h:969 ++#: options.h:1281 +msgid "Mark object for lazy runtime binding (default)" +msgstr "" + -+#: options.h:972 ++#: options.h:1284 +msgid "Mark object requiring immediate process" +msgstr "" + -+#: options.h:975 ++#: options.h:1287 +msgid "Set maximum page size to SIZE" +msgstr "" + -+#: options.h:978 ++#: options.h:1295 +msgid "Do not create copy relocs" +msgstr "" + -+#: options.h:980 ++#: options.h:1297 +msgid "Mark object not to use default search paths" +msgstr "" + -+#: options.h:983 ++#: options.h:1300 +msgid "Mark DSO non-deletable at runtime" +msgstr "" + -+#: options.h:986 ++#: options.h:1303 +msgid "Mark DSO not available to dlopen" +msgstr "" + -+#: options.h:989 ++#: options.h:1306 +msgid "Mark DSO not available to dldump" +msgstr "" + -+#: options.h:992 ++#: options.h:1309 +msgid "Mark output as not requiring executable stack" +msgstr "" + -+#: options.h:994 ++#: options.h:1311 +msgid "Mark object for immediate function binding" +msgstr "" + -+#: options.h:997 ++#: options.h:1314 +msgid "Mark DSO to indicate that needs immediate $ORIGIN processing at runtime" +msgstr "" + -+#: options.h:1000 ++#: options.h:1317 +msgid "Where possible mark variables read-only after relocation" +msgstr "" + -+#: options.h:1001 ++#: options.h:1318 +msgid "Don't mark variables read-only after relocation" +msgstr "" + -+#: output.cc:1132 ++#: options.h:1320 ++msgid "Do not permit relocations in read-only segments" ++msgstr "" ++ ++#: options.h:1321 options.h:1323 ++msgid "Permit relocations in read-only segments (default)" ++msgstr "" ++ ++#: output.cc:1344 +msgid "section group retained but group element discarded" +msgstr "" + -+#: output.cc:1860 ++#: output.cc:1711 output.cc:1743 ++msgid "out of patch space (GOT); relink with --incremental-full" ++msgstr "" ++ ++#: output.cc:2372 +#, c-format +msgid "invalid alignment %lu for section \"%s\"" +msgstr "" + -+#: output.cc:3573 ++#: output.cc:4598 +#, c-format +msgid "dot moves backward in linker script from 0x%llx to 0x%llx" +msgstr "" + -+#: output.cc:3576 ++#: output.cc:4601 +#, c-format +msgid "address of section '%s' moves backward from 0x%llx to 0x%llx" +msgstr "" + -+#: output.cc:3755 ++#: output.cc:4965 +#, c-format -+msgid "nobits section %s may not precede progbits section %s in same segment" ++msgid "%s: incremental base and output file name are the same" +msgstr "" + -+#: output.cc:3907 output.cc:3975 ++#: output.cc:4972 ++#, c-format ++msgid "%s: stat: %s" ++msgstr "" ++ ++#: output.cc:4977 ++#, c-format ++msgid "%s: incremental base file is empty" ++msgstr "" ++ ++#: output.cc:4989 output.cc:5087 +#, c-format +msgid "%s: open: %s" +msgstr "" + -+#: output.cc:3996 ++#: output.cc:5006 ++#, c-format ++msgid "%s: read failed: %s" ++msgstr "" ++ ++#: output.cc:5011 ++#, c-format ++msgid "%s: file too short: read only %lld of %lld bytes" ++msgstr "" ++ ++#: output.cc:5111 +#, c-format +msgid "%s: mremap: %s" +msgstr "" + -+#: output.cc:4005 ++#: output.cc:5130 +#, c-format +msgid "%s: mmap: %s" +msgstr "" + -+#: output.cc:4085 ++#: output.cc:5222 +#, c-format +msgid "%s: mmap: failed to allocate %lu bytes for output file: %s" +msgstr "" + -+#: output.cc:4096 ++#: output.cc:5240 +#, c-format +msgid "%s: munmap: %s" +msgstr "" + -+#: output.cc:4115 ++#: output.cc:5260 +#, c-format +msgid "%s: write: unexpected 0 return-value" +msgstr "" + -+#: output.cc:4117 ++#: output.cc:5262 +#, c-format +msgid "%s: write: %s" +msgstr "" + -+#: output.cc:4132 ++#: output.cc:5277 +#, c-format +msgid "%s: close: %s" +msgstr "" + -+#: output.h:520 ++#: output.h:501 +msgid "** section headers" +msgstr "" + -+#: output.h:565 ++#: output.h:551 +msgid "** segment headers" +msgstr "" + -+#: output.h:613 ++#: output.h:598 +msgid "** file header" +msgstr "" + -+#: output.h:833 ++#: output.h:824 +msgid "** fill" +msgstr "" + -+#: output.h:987 ++#: output.h:990 +msgid "** string table" +msgstr "" + -+#: output.h:1300 ++#: output.h:1513 +msgid "** dynamic relocs" +msgstr "" + -+#: output.h:1301 output.h:1637 ++#: output.h:1514 output.h:2214 +msgid "** relocs" +msgstr "" + -+#: output.h:1662 ++#: output.h:2239 +msgid "** group" +msgstr "" + -+#: output.h:1774 ++#: output.h:2415 +msgid "** GOT" +msgstr "" + -+#: output.h:1916 ++#: output.h:2597 +msgid "** dynamic" +msgstr "" + -+#: output.h:2039 ++#: output.h:2734 +msgid "** symtab xindex" +msgstr "" + -+#: parameters.cc:172 ++#: parameters.cc:221 ++msgid "input file does not match -EB/EL option" ++msgstr "" ++ ++#: parameters.cc:231 ++msgid "-Trodata-segment is meaningless without --rosegment" ++msgstr "" ++ ++#: parameters.cc:339 target-select.cc:199 +#, c-format +msgid "unrecognized output format %s" +msgstr "" + -+#: plugin.cc:106 ++#: parameters.cc:352 +#, c-format -+msgid "%s: could not load plugin library" ++msgid "unrecognized emulation %s" +msgstr "" + -+#: plugin.cc:116 ++#: parameters.cc:375 ++msgid "no supported target for -EB/-EL option" ++msgstr "" ++ ++#: plugin.cc:178 ++#, c-format ++msgid "%s: could not load plugin library: %s" ++msgstr "" ++ ++#: plugin.cc:187 +#, c-format +msgid "%s: could not find onload entry point" +msgstr "" + -+#: plugin.cc:426 -+msgid "" -+"Input files added by plug-ins in --incremental mode not supported yet.\n" ++#: plugin.cc:852 ++msgid "input files added by plug-ins in --incremental mode not supported yet" +msgstr "" + -+#: powerpc.cc:1502 sparc.cc:2307 x86_64.cc:1632 ++#: powerpc.cc:856 ++msgid "missing expected __tls_get_addr call" ++msgstr "" ++ ++#: powerpc.cc:1663 powerpc.cc:1865 ++#, c-format ++msgid "%s: ABI version %d is not compatible with ABI version %d output" ++msgstr "" ++ ++#: powerpc.cc:1697 powerpc.cc:1907 ++#, c-format ++msgid "%s: .opd invalid in abiv%d" ++msgstr "" ++ ++#: powerpc.cc:1765 ++#, c-format ++msgid "%s: unexpected reloc type %u in .opd section" ++msgstr "" ++ ++#: powerpc.cc:1776 ++#, c-format ++msgid "%s: .opd is not a regular array of opd entries" ++msgstr "" ++ ++#: powerpc.cc:1843 ++#, c-format ++msgid "%s: local symbol %d has invalid st_other for ABI version 1" ++msgstr "" ++ ++#: powerpc.cc:2420 ++#, c-format ++msgid "%s:%s exceeds group size" ++msgstr "" ++ ++#: powerpc.cc:2643 ++#, c-format ++msgid "%s:%s: branch in non-executable section, no long branch stub for you" ++msgstr "" ++ ++#: powerpc.cc:3966 ++msgid "** glink" ++msgstr "" ++ ++#: powerpc.cc:4136 powerpc.cc:4500 ++#, c-format ++msgid "%s: linkage table error against `%s'" ++msgstr "" ++ ++#: powerpc.cc:4607 ++msgid "** save/restore" ++msgstr "" ++ ++#: powerpc.cc:5216 sparc.cc:2212 ++msgid "requires unsupported dynamic reloc; recompile with -fPIC" ++msgstr "" ++ ++#: powerpc.cc:5289 ++#, c-format ++msgid "%s: unsupported reloc %u for IFUNC symbol" ++msgstr "" ++ ++#: powerpc.cc:6329 sparc.cc:3076 tilegx.cc:4193 x86_64.cc:3114 +#, c-format +msgid "%s: unsupported REL reloc section" +msgstr "" + -+#: readsyms.cc:191 ++#: powerpc.cc:6626 ++msgid "__tls_get_addr call lacks marker reloc" ++msgstr "" ++ ++#: powerpc.cc:6772 ++msgid "call lacks nop, can't restore toc; recompile with -fPIC" ++msgstr "" ++ ++#: powerpc.cc:7206 powerpc.cc:7230 ++#, c-format ++msgid "toc optimization is not supported for %#08x instruction" ++msgstr "" ++ ++#: powerpc.cc:7568 ++msgid "relocation overflow" ++msgstr "" ++ ++#: readsyms.cc:285 +#, c-format +msgid "%s: file is empty" +msgstr "" + +#. Here we have to handle any other input file types we need. -+#: readsyms.cc:575 ++#: readsyms.cc:920 +#, c-format +msgid "%s: not an object or archive" +msgstr "" + -+#: reduced_debug_output.cc:236 ++#: reduced_debug_output.cc:187 +msgid "" +"Debug abbreviations extend beyond .debug_abbrev section; failed to reduce " +"debug abbreviations" +msgstr "" + -+#: reduced_debug_output.cc:322 ++#: reduced_debug_output.cc:273 +msgid "Extremely large compile unit in debug info; failed to reduce debug info" +msgstr "" + -+#: reduced_debug_output.cc:330 ++#: reduced_debug_output.cc:281 +msgid "" +"Debug info extends beyond .debug_info section;failed to reduce debug info" +msgstr "" + -+#: reduced_debug_output.cc:350 reduced_debug_output.cc:392 ++#: reduced_debug_output.cc:301 reduced_debug_output.cc:343 +msgid "Invalid DIE in debug info; failed to reduce debug info" +msgstr "" + -+#: reduced_debug_output.cc:373 ++#: reduced_debug_output.cc:324 +msgid "" +"Debug info extends beyond .debug_info section; failed to reduce debug info" +msgstr "" + -+#: reloc.cc:297 reloc.cc:858 ++#: reloc.cc:317 reloc.cc:959 +#, c-format +msgid "relocation section %u uses unexpected symbol table %u" +msgstr "" + -+#: reloc.cc:312 reloc.cc:875 ++#: reloc.cc:335 reloc.cc:976 +#, c-format +msgid "unexpected entsize for reloc section %u: %lu != %u" +msgstr "" + -+#: reloc.cc:321 reloc.cc:884 ++#: reloc.cc:344 reloc.cc:985 +#, c-format +msgid "reloc section %u size %lu uneven" +msgstr "" + -+#: reloc.cc:1203 ++#: reloc.cc:1367 +#, c-format +msgid "could not convert call to '%s' to '%s'" +msgstr "" + -+#: reloc.cc:1343 ++#: reloc.cc:1527 +#, c-format +msgid "reloc section size %zu is not a multiple of reloc size %d\n" +msgstr "" + +#. We should only see externally visible symbols in the symbol +#. table. -+#: resolve.cc:191 ++#: resolve.cc:194 +msgid "invalid STB_LOCAL symbol in external symbols" +msgstr "" + +#. Any target which wants to handle STB_LOOS, etc., needs to +#. define a resolve method. -+#: resolve.cc:197 -+msgid "unsupported symbol binding" ++#: resolve.cc:200 ++#, c-format ++msgid "unsupported symbol binding %d" +msgstr "" + +#. A dynamic object cannot reference a hidden or internal symbol +#. defined in another object. -+#: resolve.cc:266 ++#: resolve.cc:284 +#, c-format +msgid "%s symbol '%s' in %s is referenced by DSO %s" +msgstr "" + -+#: resolve.cc:326 ++#: resolve.cc:406 +#, c-format +msgid "common of '%s' overriding smaller common" +msgstr "" + -+#: resolve.cc:331 ++#: resolve.cc:411 +#, c-format +msgid "common of '%s' overidden by larger common" +msgstr "" + -+#: resolve.cc:336 ++#: resolve.cc:416 +#, c-format +msgid "multiple common of '%s'" +msgstr "" + -+#: resolve.cc:442 ++#: resolve.cc:458 ++#, c-format ++msgid "symbol '%s' used as both __thread and non-__thread" ++msgstr "" ++ ++#: resolve.cc:501 +#, c-format +msgid "multiple definition of '%s'" +msgstr "" + -+#: resolve.cc:481 ++#: resolve.cc:540 +#, c-format +msgid "definition of '%s' overriding common" +msgstr "" + -+#: resolve.cc:516 ++#: resolve.cc:575 +#, c-format +msgid "definition of '%s' overriding dynamic common definition" +msgstr "" + -+#: resolve.cc:636 ++#: resolve.cc:725 +#, c-format +msgid "common '%s' overridden by previous definition" +msgstr "" + -+#: resolve.cc:766 resolve.cc:778 ++#: resolve.cc:860 ++msgid "COPY reloc" ++msgstr "" ++ ++#: resolve.cc:864 resolve.cc:887 +msgid "command line" +msgstr "" + -+#: script-sections.cc:690 ++#: resolve.cc:867 ++msgid "linker script" ++msgstr "" ++ ++#: resolve.cc:871 ++msgid "linker defined" ++msgstr "" ++ ++#: script-sections.cc:105 ++#, c-format ++msgid "section %s overflows end of region %s" ++msgstr "" ++ ++#: script-sections.cc:646 ++msgid "Attempt to set a memory region for a non-output section" ++msgstr "" ++ ++#: script-sections.cc:952 script-sections.cc:3583 +msgid "dot may not move backward" +msgstr "" + -+#: script-sections.cc:757 ++#: script-sections.cc:1019 +msgid "** expression" +msgstr "" + -+#: script-sections.cc:941 ++#: script-sections.cc:1204 +msgid "fill value is not absolute" +msgstr "" + -+#: script-sections.cc:1913 ++#: script-sections.cc:2348 +#, c-format +msgid "alignment of section %s is not absolute" +msgstr "" + -+#: script-sections.cc:1957 ++#: script-sections.cc:2449 +#, c-format +msgid "subalign of section %s is not absolute" +msgstr "" + -+#: script-sections.cc:1972 ++#: script-sections.cc:2464 +#, c-format +msgid "fill of section %s is not absolute" +msgstr "" + -+#: script-sections.cc:2048 ++#: script-sections.cc:2577 +msgid "SPECIAL constraints are not implemented" +msgstr "" + -+#: script-sections.cc:2090 ++#: script-sections.cc:2619 +msgid "mismatched definition for constrained sections" +msgstr "" + -+#: script-sections.cc:2634 ++#: script-sections.cc:3095 ++#, c-format ++msgid "region '%.*s' already defined" ++msgstr "" ++ ++#: script-sections.cc:3321 +msgid "DATA_SEGMENT_ALIGN may only appear once in a linker script" +msgstr "" + -+#: script-sections.cc:2649 ++#: script-sections.cc:3336 +msgid "DATA_SEGMENT_RELRO_END may only appear once in a linker script" +msgstr "" + -+#: script-sections.cc:2654 ++#: script-sections.cc:3341 +msgid "DATA_SEGMENT_RELRO_END must follow DATA_SEGMENT_ALIGN" +msgstr "" + -+#: script-sections.cc:2826 ++#: script-sections.cc:3519 +msgid "no matching section constraint" +msgstr "" + -+#: script-sections.cc:3151 ++#: script-sections.cc:3914 ++msgid "" ++"creating a segment to contain the file and program headers outside of any " ++"MEMORY region" ++msgstr "" ++ ++#: script-sections.cc:3963 +msgid "TLS sections are not adjacent" +msgstr "" + -+#: script-sections.cc:3280 -+msgid "allocated section not in any segment" ++#: script-sections.cc:4110 ++#, c-format ++msgid "allocated section %s not in any segment" +msgstr "" + -+#: script-sections.cc:3309 ++#: script-sections.cc:4156 +#, c-format +msgid "no segment %s" +msgstr "" + -+#: script-sections.cc:3323 ++#: script-sections.cc:4169 +msgid "section in two PT_LOAD segments" +msgstr "" + -+#: script-sections.cc:3330 ++#: script-sections.cc:4176 +msgid "allocated section not in any PT_LOAD segment" +msgstr "" + -+#: script-sections.cc:3358 ++#: script-sections.cc:4205 +msgid "may only specify load address for PT_LOAD segment" +msgstr "" + -+#: script-sections.cc:3382 ++#: script-sections.cc:4231 +#, c-format +msgid "PHDRS load address overrides section %s load address" +msgstr "" + +#. We could support this if we wanted to. -+#: script-sections.cc:3393 ++#: script-sections.cc:4242 +msgid "using only one of FILEHDR and PHDRS is not currently supported" +msgstr "" + -+#: script-sections.cc:3408 ++#: script-sections.cc:4257 +msgid "" +"sections loaded on first page without room for file and program headers are " +"not supported" +msgstr "" + -+#: script-sections.cc:3414 ++#: script-sections.cc:4263 +msgid "" +"using FILEHDR and PHDRS on more than one PT_LOAD segment is not currently " +"supported" +msgstr "" + -+#: script.cc:1072 ++#: script.cc:1132 +msgid "invalid use of PROVIDE for dot symbol" +msgstr "" + -+#: script.cc:2132 ++#: script.cc:1508 ++#, c-format ++msgid "%s: SECTIONS seen after other input files; try -T/--script" ++msgstr "" ++ ++#. We have a match for both the global and local entries for a ++#. version tag. That's got to be wrong. ++#: script.cc:2212 ++#, c-format ++msgid "" ++"'%s' appears as both a global and a local symbol for version '%s' in script" ++msgstr "" ++ ++#: script.cc:2239 ++#, c-format ++msgid "wildcard match appears in both version '%s' and '%s' in script" ++msgstr "" ++ ++#: script.cc:2244 ++#, c-format ++msgid "" ++"wildcard match appears as both global and local in version '%s' in script" ++msgstr "" ++ ++#: script.cc:2329 ++#, c-format ++msgid "" ++"using '%s' as version for '%s' which is also named in version '%s' in script" ++msgstr "" ++ ++#: script.cc:2427 ++#, c-format ++msgid "version script assignment of %s to symbol %s failed: symbol not defined" ++msgstr "" ++ ++#: script.cc:2623 +#, c-format +msgid "%s:%d:%d: %s" +msgstr "" + ++#: script.cc:2689 ++msgid "library name must be prefixed with -l" ++msgstr "" ++ +#. There are some options that we could handle here--e.g., +#. -lLIBRARY. Should we bother? -+#: script.cc:2297 ++#: script.cc:2816 +#, c-format +msgid "" +"%s:%d:%d: ignoring command OPTION; OPTION is only valid for scripts " +"specified via -T/--script" +msgstr "" + -+#: script.cc:2362 ++#: script.cc:2881 +#, c-format +msgid "" +"%s:%d:%d: ignoring SEARCH_DIR; SEARCH_DIR is only valid for scripts " +"specified via -T/--script" +msgstr "" + -+#: script.cc:2606 script.cc:2620 ++#: script.cc:2909 ++#, c-format ++msgid "%s:%d:%d: invalid use of VERSION in input file" ++msgstr "" ++ ++#: script.cc:3025 ++#, c-format ++msgid "unrecognized version script language '%s'" ++msgstr "" ++ ++#: script.cc:3144 script.cc:3158 +#, c-format +msgid "%s:%d:%d: DATA_SEGMENT_ALIGN not in SECTIONS clause" +msgstr "" + -+#: script.cc:2739 ++#: script.cc:3277 +msgid "unknown PHDR type (try integer)" +msgstr "" + -+#: stringpool.cc:528 ++#: script.cc:3296 ++#, c-format ++msgid "%s:%d:%d: MEMORY region '%.*s' referred to outside of SECTIONS clause" ++msgstr "" ++ ++#: script.cc:3307 ++#, c-format ++msgid "%s:%d:%d: MEMORY region '%.*s' not declared" ++msgstr "" ++ ++#: script.cc:3352 ++msgid "unknown MEMORY attribute" ++msgstr "" ++ ++#: script.cc:3382 ++#, c-format ++msgid "undefined memory region '%s' referenced in ORIGIN expression" ++msgstr "" ++ ++#: script.cc:3401 ++#, c-format ++msgid "undefined memory region '%s' referenced in LENGTH expression" ++msgstr "" ++ ++#: sparc.cc:4326 ++#, c-format ++msgid "%s: little endian elf flag set on BE object" ++msgstr "" ++ ++#: sparc.cc:4329 ++#, c-format ++msgid "%s: little endian elf flag clear on LE object" ++msgstr "" ++ ++#: stringpool.cc:510 +#, c-format +msgid "%s: %s entries: %zu; buckets: %zu\n" +msgstr "" + -+#: stringpool.cc:532 ++#: stringpool.cc:514 +#, c-format +msgid "%s: %s entries: %zu\n" +msgstr "" + -+#: stringpool.cc:535 ++#: stringpool.cc:517 +#, c-format +msgid "%s: %s Stringdata structures: %zu\n" +msgstr "" + -+#: symtab.cc:857 ++#: symtab.cc:374 ++#, c-format ++msgid "Cannot export local symbol '%s'" ++msgstr "" ++ ++#: symtab.cc:904 +#, c-format +msgid "%s: reference to %s" +msgstr "" + -+#: symtab.cc:859 ++#: symtab.cc:906 +#, c-format +msgid "%s: definition of %s" +msgstr "" + -+#: symtab.cc:1052 ++#: symtab.cc:1104 +#, c-format +msgid "bad global symbol name offset %u at %zu" +msgstr "" + -+#: symtab.cc:1278 ++#: symtab.cc:1358 +msgid "--just-symbols does not make sense with a shared object" +msgstr "" + -+#: symtab.cc:1284 ++#: symtab.cc:1369 +msgid "too few symbol versions" +msgstr "" + -+#: symtab.cc:1333 ++#: symtab.cc:1418 +#, c-format +msgid "bad symbol name offset %u at %zu" +msgstr "" + -+#: symtab.cc:1396 ++#: symtab.cc:1481 +#, c-format +msgid "versym for symbol %zu out of range: %u" +msgstr "" + -+#: symtab.cc:1404 ++#: symtab.cc:1489 +#, c-format +msgid "versym for symbol %zu has no name: %u" +msgstr "" + -+#: symtab.cc:2549 symtab.cc:2681 ++#: symtab.cc:2742 symtab.cc:2881 +#, c-format +msgid "%s: unsupported symbol section 0x%x" +msgstr "" + -+#: symtab.cc:2933 ++#: symtab.cc:3155 +#, c-format +msgid "%s: symbol table entries: %zu; buckets: %zu\n" +msgstr "" + -+#: symtab.cc:2936 ++#: symtab.cc:3158 +#, c-format +msgid "%s: symbol table entries: %zu\n" +msgstr "" + -+#: symtab.cc:3007 ++#: symtab.cc:3310 +#, c-format +msgid "" +"while linking %s: symbol '%s' defined in multiple places (possible ODR " +"violation):" +msgstr "" + -+#: target-reloc.h:259 -+msgid "relocation refers to discarded comdat section" ++#: symtab.cc:3319 symtab.cc:3322 ++#, c-format ++msgid " %s from %s\n" +msgstr "" + -+#: target-reloc.h:298 ++#: target-reloc.h:163 ++msgid "internal" ++msgstr "" ++ ++#: target-reloc.h:166 ++msgid "hidden" ++msgstr "" ++ ++#: target-reloc.h:169 ++msgid "protected" ++msgstr "" ++ ++#: target-reloc.h:174 ++#, c-format ++msgid "%s symbol '%s' is not defined locally" ++msgstr "" ++ ++#: target-reloc.h:414 +#, c-format +msgid "reloc has bad offset %zu" +msgstr "" + -+#: target.cc:90 -+#, c-format -+msgid "%s: unsupported ELF file type %d" -+msgstr "" -+ -+#: target.cc:157 ++#: target.cc:170 +#, c-format +msgid "linker does not include stack split support required by %s" +msgstr "" + ++#: tilegx.cc:2074 x86_64.cc:1244 ++msgid "out of patch space (PLT); relink with --incremental-full" ++msgstr "" ++ ++#: tilegx.cc:2724 x86_64.cc:1871 ++msgid "TLS_DESC not yet supported for incremental linking" ++msgstr "" ++ ++#: tilegx.cc:2779 ++msgid "TLS_DESC not yet supported for TILEGX" ++msgstr "" ++ ++#: tilegx.cc:3188 x86_64.cc:2257 ++#, c-format ++msgid "requires unsupported dynamic reloc %u; recompile with -fPIC" ++msgstr "" ++ +#: tls.h:59 +msgid "TLS relocation out of range" +msgstr "" @@ -2394587,12 +2406529,12 @@ index 0000000..d58054a +msgstr "" + +#. This output is intended to follow the GNU standards. -+#: version.cc:65 ++#: version.cc:66 +#, c-format -+msgid "Copyright 2008 Free Software Foundation, Inc.\n" ++msgid "Copyright 2014 Free Software Foundation, Inc.\n" +msgstr "" + -+#: version.cc:66 ++#: version.cc:67 +#, c-format +msgid "" +"This program is free software; you may redistribute it under the terms of\n" @@ -2394606,12 +2406548,25 @@ index 0000000..d58054a +msgid "%s failed: %s" +msgstr "" + -+#: x86_64.cc:2184 ++#: x86_64.cc:2222 ++msgid "" ++"requires dynamic R_X86_64_32 reloc which may overflow at runtime; recompile " ++"with -fPIC" ++msgstr "" ++ ++#: x86_64.cc:2242 ++#, c-format ++msgid "" ++"requires dynamic %s reloc against '%s' which may overflow at runtime; " ++"recompile with -fPIC" ++msgstr "" ++ ++#: x86_64.cc:3776 +#, c-format +msgid "unsupported reloc type %u" +msgstr "" + -+#: x86_64.cc:2524 ++#: x86_64.cc:4211 +#, c-format +msgid "unsupported reloc %u against local symbol" +msgstr "" @@ -2401016,13 +2412971,13 @@ index 0000000..fadc16f +msgstr "sự định vị lại không được hỗ trợ %u so với ký hiệu cục bộ" diff --git a/gold/powerpc.cc b/gold/powerpc.cc new file mode 100644 -index 0000000..1aa4791 +index 0000000..96432ed --- /dev/null +++ b/gold/powerpc.cc -@@ -0,0 +1,8157 @@ +@@ -0,0 +1,8253 @@ +// powerpc.cc -- powerpc target support for gold. + -+// Copyright 2008, 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by David S. Miller +// and David Edelsohn + @@ -2401969,7 +2413924,7 @@ index 0000000..1aa4791 + inline bool + local_reloc_may_be_function_pointer(Symbol_table* , Layout* , + Target_powerpc* , -+ Sized_relobj_file* , ++ Sized_relobj_file* relobj, + unsigned int , + Output_section* , + const elfcpp::Rela& , @@ -2401980,8 +2413935,13 @@ index 0000000..1aa4791 + // may be folded and we'll still keep function addresses distinct. + // That means no reloc is of concern here. + if (size == 64) -+ return false; -+ // For 32-bit, conservatively assume anything but calls to ++ { ++ Powerpc_relobj* ppcobj = static_cast ++ *>(relobj); ++ if (ppcobj->abiversion() == 1) ++ return false; ++ } ++ // For 32-bit and ELFv2, conservatively assume anything but calls to + // function code might be taking the address of the function. + return !is_branch_reloc(r_type); + } @@ -2401989,7 +2413949,7 @@ index 0000000..1aa4791 + inline bool + global_reloc_may_be_function_pointer(Symbol_table* , Layout* , + Target_powerpc* , -+ Sized_relobj_file* , ++ Sized_relobj_file* relobj, + unsigned int , + Output_section* , + const elfcpp::Rela& , @@ -2401998,7 +2413958,12 @@ index 0000000..1aa4791 + { + // As above. + if (size == 64) -+ return false; ++ { ++ Powerpc_relobj* ppcobj = static_cast ++ *>(relobj); ++ if (ppcobj->abiversion() == 1) ++ return false; ++ } + return !is_branch_reloc(r_type); + } + @@ -2402468,7 +2414433,10 @@ index 0000000..1aa4791 + { + CHECK_NONE, + CHECK_SIGNED, -+ CHECK_BITFIELD ++ CHECK_UNSIGNED, ++ CHECK_BITFIELD, ++ CHECK_LOW_INSN, ++ CHECK_HIGH_INSN + }; + + enum Status @@ -2402494,12 +2414462,20 @@ index 0000000..1aa4791 + + template + static inline bool -+ has_overflow_bitfield(Address value) ++ has_overflow_unsigned(Address value) + { + Address limit = static_cast
(1) << ((valsize - 1) >> 1); + limit <<= ((valsize - 1) >> 1); + limit <<= ((valsize - 1) - 2 * ((valsize - 1) >> 1)); -+ return value > (limit << 1) - 1 && value + limit > (limit << 1) - 1; ++ return value > (limit << 1) - 1; ++ } ++ ++ template ++ static inline bool ++ has_overflow_bitfield(Address value) ++ { ++ return (has_overflow_unsigned(value) ++ && has_overflow_signed(value)); + } + + template @@ -2402511,6 +2414487,11 @@ index 0000000..1aa4791 + if (has_overflow_signed(value)) + return STATUS_OVERFLOW; + } ++ else if (overflow == CHECK_UNSIGNED) ++ { ++ if (has_overflow_unsigned(value)) ++ return STATUS_OVERFLOW; ++ } + else if (overflow == CHECK_BITFIELD) + { + if (has_overflow_bitfield(value)) @@ -2403857,7 +2415838,21 @@ index 0000000..1aa4791 + if (plt == this->glink_) + { + // See Output_data_glink::do_write() for glink contents. -+ if (size == 64) ++ if (len == 0) ++ { ++ gold_assert(parameters->doing_static_link()); ++ // Static linking may need stubs, to support ifunc and long ++ // branches. We need to create an output section for ++ // .eh_frame early in the link process, to have a place to ++ // attach stub .eh_frame info. We also need to have ++ // registered a CIE that matches the stub CIE. Both of ++ // these requirements are satisfied by creating an FDE and ++ // CIE for .glink, even though static linking will leave ++ // .glink zero length. ++ // ??? Hopefully generating an FDE with a zero address range ++ // won't confuse anything that consumes .eh_frame info. ++ } ++ else if (size == 64) + { + // There is one word before __glink_PLTresolve + address += 8; @@ -2403869,7 +2415864,7 @@ index 0000000..1aa4791 + // The first covers the branch table, the second + // __glink_PLTresolve at the end of glink. + off_t resolve_size = this->glink_->pltresolve_size; -+ if (oview[9] == 0) ++ if (oview[9] == elfcpp::DW_CFA_nop) + len -= resolve_size; + else + { @@ -2404059,6 +2416054,7 @@ index 0000000..1aa4791 +static const uint32_t addis_11_2 = 0x3d620000; +static const uint32_t addis_11_11 = 0x3d6b0000; +static const uint32_t addis_11_30 = 0x3d7e0000; ++static const uint32_t addis_12_2 = 0x3d820000; +static const uint32_t addis_12_12 = 0x3d8c0000; +static const uint32_t b = 0x48000000; +static const uint32_t bcl_20_31 = 0x429f0005; @@ -2405192,10 +2417188,20 @@ index 0000000..1aa4791 + { + write_insn(p, std_2_1 + this->targ_->stk_toc()); + p += 4; -+ write_insn(p, addis_11_2 + ha(off)); -+ p += 4; -+ write_insn(p, ld_12_11 + l(off)); -+ p += 4; ++ if (plt_load_toc) ++ { ++ write_insn(p, addis_11_2 + ha(off)); ++ p += 4; ++ write_insn(p, ld_12_11 + l(off)); ++ p += 4; ++ } ++ else ++ { ++ write_insn(p, addis_12_2 + ha(off)); ++ p += 4; ++ write_insn(p, ld_12_12 + l(off)); ++ p += 4; ++ } + if (plt_load_toc + && ha(off + 8 + 8 * static_chain) != ha(off)) + { @@ -2405294,8 +2417300,8 @@ index 0000000..1aa4791 + } + else + { -+ write_insn(p, addis_11_2 + ha(brltoff)), p += 4; -+ write_insn(p, ld_12_11 + l(brltoff)), p += 4; ++ write_insn(p, addis_12_2 + ha(brltoff)), p += 4; ++ write_insn(p, ld_12_12 + l(brltoff)), p += 4; + } + write_insn(p, mtctr_12), p += 4; + write_insn(p, bctr); @@ -2406504,6 +2418510,7 @@ index 0000000..1aa4791 + case elfcpp::R_PPC64_DTPREL16_HIGHESTA: + case elfcpp::R_PPC64_TLSGD: + case elfcpp::R_PPC64_TLSLD: ++ case elfcpp::R_PPC64_ADDR64_LOCAL: + break; + + case elfcpp::R_POWERPC_GOT16: @@ -2406824,7 +2418831,8 @@ index 0000000..1aa4791 + if (gsym->needs_dynamic_reloc(Scan::get_reference_flags(r_type, target)) + || (size == 64 && is_ifunc && target->abiversion() < 2)) + { -+ if (gsym->may_need_copy_reloc()) ++ if (!parameters->options().output_is_position_independent() ++ && gsym->may_need_copy_reloc()) + { + target->copy_reloc(symtab, layout, object, + data_shndx, output_section, gsym, reloc); @@ -2406887,7 +2418895,8 @@ index 0000000..1aa4791 + // Make a dynamic relocation if necessary. + if (gsym->needs_dynamic_reloc(Scan::get_reference_flags(r_type, target))) + { -+ if (gsym->may_need_copy_reloc()) ++ if (!parameters->options().output_is_position_independent() ++ && gsym->may_need_copy_reloc()) + { + target->copy_reloc(symtab, layout, object, + data_shndx, output_section, gsym, @@ -2406950,6 +2418959,7 @@ index 0000000..1aa4791 + case elfcpp::R_PPC64_DTPREL16_HIGHESTA: + case elfcpp::R_PPC64_TLSGD: + case elfcpp::R_PPC64_TLSLD: ++ case elfcpp::R_PPC64_ADDR64_LOCAL: + break; + + case elfcpp::R_POWERPC_GOT16: @@ -2408159,6 +2420169,13 @@ index 0000000..1aa4791 + value -= dtp_offset; + break; + ++ case elfcpp::R_PPC64_ADDR64_LOCAL: ++ if (gsym != NULL) ++ value += object->ppc64_local_entry_offset(gsym); ++ else ++ value += object->ppc64_local_entry_offset(r_sym); ++ break; ++ + default: + break; + } @@ -2408272,6 +2420289,7 @@ index 0000000..1aa4791 + } + + typename Reloc::Overflow_check overflow = Reloc::CHECK_NONE; ++ elfcpp::Shdr shdr(relinfo->data_shdr); + switch (r_type) + { + case elfcpp::R_POWERPC_ADDR32: @@ -2408285,16 +2420303,19 @@ index 0000000..1aa4791 + overflow = Reloc::CHECK_SIGNED; + break; + -+ case elfcpp::R_POWERPC_ADDR24: -+ case elfcpp::R_POWERPC_ADDR16: + case elfcpp::R_POWERPC_UADDR16: -+ case elfcpp::R_PPC64_ADDR16_DS: -+ case elfcpp::R_POWERPC_ADDR14: -+ case elfcpp::R_POWERPC_ADDR14_BRTAKEN: -+ case elfcpp::R_POWERPC_ADDR14_BRNTAKEN: + overflow = Reloc::CHECK_BITFIELD; + break; + ++ case elfcpp::R_POWERPC_ADDR16: ++ // We really should have three separate relocations, ++ // one for 16-bit data, one for insns with 16-bit signed fields, ++ // and one for insns with 16-bit unsigned fields. ++ overflow = Reloc::CHECK_BITFIELD; ++ if ((shdr.get_sh_flags() & elfcpp::SHF_EXECINSTR) != 0) ++ overflow = Reloc::CHECK_LOW_INSN; ++ break; ++ + case elfcpp::R_POWERPC_ADDR16_HI: + case elfcpp::R_POWERPC_ADDR16_HA: + case elfcpp::R_POWERPC_GOT16_HI: @@ -2408321,17 +2420342,31 @@ index 0000000..1aa4791 + case elfcpp::R_POWERPC_GOT_DTPREL16_HA: + case elfcpp::R_POWERPC_REL16_HI: + case elfcpp::R_POWERPC_REL16_HA: -+ if (size == 32) -+ break; -+ case elfcpp::R_POWERPC_REL24: -+ case elfcpp::R_PPC_PLTREL24: -+ case elfcpp::R_PPC_LOCAL24PC: ++ if (size != 32) ++ overflow = Reloc::CHECK_HIGH_INSN; ++ break; ++ + case elfcpp::R_POWERPC_REL16: + case elfcpp::R_PPC64_TOC16: + case elfcpp::R_POWERPC_GOT16: + case elfcpp::R_POWERPC_SECTOFF: + case elfcpp::R_POWERPC_TPREL16: + case elfcpp::R_POWERPC_DTPREL16: ++ case elfcpp::R_POWERPC_GOT_TLSGD16: ++ case elfcpp::R_POWERPC_GOT_TLSLD16: ++ case elfcpp::R_POWERPC_GOT_TPREL16: ++ case elfcpp::R_POWERPC_GOT_DTPREL16: ++ overflow = Reloc::CHECK_LOW_INSN; ++ break; ++ ++ case elfcpp::R_POWERPC_ADDR24: ++ case elfcpp::R_POWERPC_ADDR14: ++ case elfcpp::R_POWERPC_ADDR14_BRTAKEN: ++ case elfcpp::R_POWERPC_ADDR14_BRNTAKEN: ++ case elfcpp::R_PPC64_ADDR16_DS: ++ case elfcpp::R_POWERPC_REL24: ++ case elfcpp::R_PPC_PLTREL24: ++ case elfcpp::R_PPC_LOCAL24PC: + case elfcpp::R_PPC64_TPREL16_DS: + case elfcpp::R_PPC64_DTPREL16_DS: + case elfcpp::R_PPC64_TOC16_DS: @@ -2408340,14 +2420375,29 @@ index 0000000..1aa4791 + case elfcpp::R_POWERPC_REL14: + case elfcpp::R_POWERPC_REL14_BRTAKEN: + case elfcpp::R_POWERPC_REL14_BRNTAKEN: -+ case elfcpp::R_POWERPC_GOT_TLSGD16: -+ case elfcpp::R_POWERPC_GOT_TLSLD16: -+ case elfcpp::R_POWERPC_GOT_TPREL16: -+ case elfcpp::R_POWERPC_GOT_DTPREL16: + overflow = Reloc::CHECK_SIGNED; + break; + } + ++ if (overflow == Reloc::CHECK_LOW_INSN ++ || overflow == Reloc::CHECK_HIGH_INSN) ++ { ++ Insn* iview = reinterpret_cast(view - 2 * big_endian); ++ Insn insn = elfcpp::Swap<32, big_endian>::readval(iview); ++ ++ overflow = Reloc::CHECK_SIGNED; ++ if ((insn & (0x3f << 26)) == 10u << 26 /* cmpli */) ++ overflow = Reloc::CHECK_BITFIELD; ++ else if (overflow == Reloc::CHECK_LOW_INSN ++ ? ((insn & (0x3f << 26)) == 28u << 26 /* andi */ ++ || (insn & (0x3f << 26)) == 24u << 26 /* ori */ ++ || (insn & (0x3f << 26)) == 26u << 26 /* xori */) ++ : ((insn & (0x3f << 26)) == 29u << 26 /* andis */ ++ || (insn & (0x3f << 26)) == 25u << 26 /* oris */ ++ || (insn & (0x3f << 26)) == 27u << 26 /* xoris */)) ++ overflow = Reloc::CHECK_UNSIGNED; ++ } ++ + typename Powerpc_relocate_functions::Status status + = Powerpc_relocate_functions::STATUS_OK; + switch (r_type) @@ -2408361,6 +2420411,7 @@ index 0000000..1aa4791 + case elfcpp::R_PPC64_ADDR64: + case elfcpp::R_PPC64_REL64: + case elfcpp::R_PPC64_TOC: ++ case elfcpp::R_PPC64_ADDR64_LOCAL: + Reloc::addr64(view, value); + break; + @@ -2409179,13 +2421230,13 @@ index 0000000..1aa4791 +} // End anonymous namespace. diff --git a/gold/pread.c b/gold/pread.c new file mode 100644 -index 0000000..2f47565 +index 0000000..eb27411 --- /dev/null +++ b/gold/pread.c @@ -0,0 +1,42 @@ +/* pread.c -- version of pread for gold. */ + -+/* Copyright 2006, 2007, 2009 Free Software Foundation, Inc. ++/* Copyright (C) 2006-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor . + + This file is part of gold. @@ -2409227,13 +2421278,13 @@ index 0000000..2f47565 +} diff --git a/gold/readsyms.cc b/gold/readsyms.cc new file mode 100644 -index 0000000..8e52ccb +index 0000000..8aaa91a --- /dev/null +++ b/gold/readsyms.cc @@ -0,0 +1,946 @@ +// readsyms.cc -- read input file symbols for gold + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2410179,14 +2422230,13 @@ index 0000000..8e52ccb +} // End namespace gold. diff --git a/gold/readsyms.h b/gold/readsyms.h new file mode 100644 -index 0000000..99b2b16 +index 0000000..0276f4d --- /dev/null +++ b/gold/readsyms.h -@@ -0,0 +1,492 @@ +@@ -0,0 +1,491 @@ +// readsyms.h -- read input file symbols for gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2013 -+// Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2410677,13 +2422727,13 @@ index 0000000..99b2b16 +#endif // !defined(GOLD_READSYMS_H) diff --git a/gold/reduced_debug_output.cc b/gold/reduced_debug_output.cc new file mode 100644 -index 0000000..a6158fc +index 0000000..09bdf13 --- /dev/null +++ b/gold/reduced_debug_output.cc @@ -0,0 +1,376 @@ +// reduced_debug_output.cc -- output reduced debugging information to save space + -+// Copyright 2008, 2010, 2012 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Caleb Howe . + +// This file is part of gold. @@ -2411059,13 +2423109,13 @@ index 0000000..a6158fc +} // End namespace gold. diff --git a/gold/reduced_debug_output.h b/gold/reduced_debug_output.h new file mode 100644 -index 0000000..d168228 +index 0000000..a4f9ebb --- /dev/null +++ b/gold/reduced_debug_output.h @@ -0,0 +1,140 @@ +// reduced_debug_output.h -- reduce debugging information -*- C++ -*- + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Caleb Howe . + +// This file is part of gold. @@ -2411205,13 +2423255,13 @@ index 0000000..d168228 +#endif // !defined(GOLD_REDUCED_DEBUG_OUTPUT_H) diff --git a/gold/reloc-types.h b/gold/reloc-types.h new file mode 100644 -index 0000000..f13e64a +index 0000000..e5f235f --- /dev/null +++ b/gold/reloc-types.h @@ -0,0 +1,92 @@ +// reloc-types.h -- ELF relocation templates for gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2411303,13 +2423353,13 @@ index 0000000..f13e64a +#endif // !defined(GOLD_RELOC_TYPE_SH) diff --git a/gold/reloc.cc b/gold/reloc.cc new file mode 100644 -index 0000000..ca7f32f +index 0000000..115ab37 --- /dev/null +++ b/gold/reloc.cc @@ -0,0 +1,1849 @@ +// reloc.cc -- relocate input files for gold. + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2413158,14 +2425208,13 @@ index 0000000..ca7f32f +} // End namespace gold. diff --git a/gold/reloc.h b/gold/reloc.h new file mode 100644 -index 0000000..4eca71a +index 0000000..da14ec1 --- /dev/null +++ b/gold/reloc.h -@@ -0,0 +1,899 @@ +@@ -0,0 +1,898 @@ +// reloc.h -- relocate input files for gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2012 -+// Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2414063,13 +2426112,13 @@ index 0000000..4eca71a +#endif // !defined(GOLD_RELOC_H) diff --git a/gold/resolve.cc b/gold/resolve.cc new file mode 100644 -index 0000000..3b6e706 +index 0000000..8cc637a --- /dev/null +++ b/gold/resolve.cc -@@ -0,0 +1,1085 @@ +@@ -0,0 +1,1089 @@ +// resolve.cc -- symbol resolution for gold + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2414984,6 +2427033,10 @@ index 0000000..3b6e706 + bool same_name = this->name_ == from->name_; + gold_assert(same_name || this->has_alias()); + ++ // If we are overriding an undef, remember the original binding. ++ if (this->is_undefined()) ++ this->set_undef_binding(this->binding_); ++ + this->source_ = from->source_; + switch (from->source_) + { @@ -2415154,13 +2427207,13 @@ index 0000000..3b6e706 +} // End namespace gold. diff --git a/gold/script-c.h b/gold/script-c.h new file mode 100644 -index 0000000..2807950 +index 0000000..f9555fe --- /dev/null +++ b/gold/script-c.h @@ -0,0 +1,566 @@ +/* script-c.h -- C interface for linker scripts in gold. */ + -+/* Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++/* Copyright (C) 2006-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor . + + This file is part of gold. @@ -2415726,13 +2427779,13 @@ index 0000000..2807950 +#endif /* !defined(GOLD_SCRIPT_C_H) */ diff --git a/gold/script-sections.cc b/gold/script-sections.cc new file mode 100644 -index 0000000..a57e53f +index 0000000..799f4ab --- /dev/null +++ b/gold/script-sections.cc @@ -0,0 +1,4372 @@ +// script-sections.cc -- linker script SECTIONS for gold + -+// Copyright 2008, 2009, 2010, 2011 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2420104,13 +2432157,13 @@ index 0000000..a57e53f +} // End namespace gold. diff --git a/gold/script-sections.h b/gold/script-sections.h new file mode 100644 -index 0000000..9ff44ea +index 0000000..daf9f64 --- /dev/null +++ b/gold/script-sections.h @@ -0,0 +1,337 @@ +// script-sections.h -- linker script SECTIONS for gold -*- C++ -*- + -+// Copyright 2008, 2009 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2420447,13 +2432500,13 @@ index 0000000..9ff44ea +#endif // !defined(GOLD_SCRIPT_SECTIONS_H diff --git a/gold/script.cc b/gold/script.cc new file mode 100644 -index 0000000..6a10c40 +index 0000000..b4a6aff --- /dev/null +++ b/gold/script.cc @@ -0,0 +1,3409 @@ +// script.cc -- handle linker scripts for gold. + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2423862,13 +2435915,13 @@ index 0000000..6a10c40 +} diff --git a/gold/script.h b/gold/script.h new file mode 100644 -index 0000000..f41f438 +index 0000000..49b3776 --- /dev/null +++ b/gold/script.h @@ -0,0 +1,594 @@ +// script.h -- handle linker scripts for gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2424462,13 +2436515,13 @@ index 0000000..f41f438 +#endif // !defined(GOLD_SCRIPT_H) diff --git a/gold/sparc.cc b/gold/sparc.cc new file mode 100644 -index 0000000..cbe95b8 +index 0000000..5a5f76a --- /dev/null +++ b/gold/sparc.cc -@@ -0,0 +1,4395 @@ +@@ -0,0 +1,4397 @@ +// sparc.cc -- sparc target support for gold. + -+// Copyright 2008, 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by David S. Miller . + +// This file is part of gold. @@ -2427102,7 +2439155,8 @@ index 0000000..cbe95b8 + // Make a dynamic relocation if necessary. + if (gsym->needs_dynamic_reloc(Scan::get_reference_flags(r_type))) + { -+ if (gsym->may_need_copy_reloc()) ++ if (parameters->options().output_is_executable() ++ && gsym->may_need_copy_reloc()) + { + target->copy_reloc(symtab, layout, object, + data_shndx, output_section, gsym, @@ -2427191,7 +2439245,8 @@ index 0000000..cbe95b8 + break; + } + -+ if (gsym->may_need_copy_reloc()) ++ if (!parameters->options().output_is_position_independent() ++ && gsym->may_need_copy_reloc()) + { + target->copy_reloc(symtab, layout, object, + data_shndx, output_section, gsym, reloc); @@ -2428863,13 +2440918,13 @@ index 0000000..cbe95b8 +} // End anonymous namespace. diff --git a/gold/stringpool.cc b/gold/stringpool.cc new file mode 100644 -index 0000000..00ed184 +index 0000000..02f0da9 --- /dev/null +++ b/gold/stringpool.cc @@ -0,0 +1,532 @@ +// stringpool.cc -- a string pool for gold + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2429401,13 +2441456,13 @@ index 0000000..00ed184 +} // End namespace gold. diff --git a/gold/stringpool.h b/gold/stringpool.h new file mode 100644 -index 0000000..b638329 +index 0000000..8ef8386 --- /dev/null +++ b/gold/stringpool.h @@ -0,0 +1,421 @@ +// stringpool.h -- a string pool for gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2429828,13 +2441883,13 @@ index 0000000..b638329 +#endif // !defined(GOLD_STRINGPOOL_H) diff --git a/gold/symtab.cc b/gold/symtab.cc new file mode 100644 -index 0000000..2e17529 +index 0000000..4e8afb1 --- /dev/null +++ b/gold/symtab.cc -@@ -0,0 +1,3657 @@ +@@ -0,0 +1,3730 @@ +// symtab.cc -- the gold symbol table + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2430361,6 +2442416,31 @@ index 0000000..2e17529 + } +} + ++// Set the symbol's output segment. This is used for pre-defined ++// symbols whose segments aren't known until after layout is done ++// (e.g., __ehdr_start). ++ ++void ++Symbol::set_output_segment(Output_segment* os, Segment_offset_base base) ++{ ++ gold_assert(this->is_predefined_); ++ this->source_ = IN_OUTPUT_SEGMENT; ++ this->u_.in_output_segment.output_segment = os; ++ this->u_.in_output_segment.offset_base = base; ++} ++ ++// Set the symbol to undefined. This is used for pre-defined ++// symbols whose segments aren't known until after layout is done ++// (e.g., __ehdr_start). ++ ++void ++Symbol::set_undefined() ++{ ++ gold_assert(this->is_predefined_); ++ this->source_ = IS_UNDEFINED; ++ this->is_predefined_ = false; ++} ++ +// Class Symbol_table. + +Symbol_table::Symbol_table(unsigned int count, @@ -2431092,7 +2443172,8 @@ index 0000000..2e17529 + && res->is_externally_visible() + && !res->is_from_dynobj() + && (parameters->options().shared() -+ || parameters->options().export_dynamic())) ++ || parameters->options().export_dynamic() ++ || parameters->options().in_dynamic_list(res->name()))) + this->gc_mark_symbol(res); + + if (is_defined_in_discarded_section) @@ -2432204,6 +2444285,25 @@ index 0000000..2e17529 +{ + std::vector as_needed_sym; + ++ // Allow a target to set dynsym indexes. ++ if (parameters->target().has_custom_set_dynsym_indexes()) ++ { ++ std::vector dyn_symbols; ++ for (Symbol_table_type::iterator p = this->table_.begin(); ++ p != this->table_.end(); ++ ++p) ++ { ++ Symbol* sym = p->second; ++ if (!sym->should_add_dynsym_entry(this)) ++ sym->set_dynsym_index(-1U); ++ else ++ dyn_symbols.push_back(sym); ++ } ++ ++ return parameters->target().set_dynsym_indexes(&dyn_symbols, index, syms, ++ dynpool, versions, this); ++ } ++ + for (Symbol_table_type::iterator p = this->table_.begin(); + p != this->table_.end(); + ++p) @@ -2432826,6 +2444926,8 @@ index 0000000..2e17529 + unsigned char* pd = dynamic_view + (dynsym_index * sym_size); + this->sized_write_symbol(sym, dynsym_value, shndx, + binding, dynpool, pd); ++ // Allow a target to adjust dynamic symbol value. ++ parameters->target().adjust_dyn_symbol(sym, pd); + } + } + @@ -2433456,6 +2445558,32 @@ index 0000000..2e17529 + elfcpp::Elf_types<64>::Elf_Addr value); +#endif + ++#if defined(HAVE_TARGET_32_LITTLE) || defined(HAVE_TARGET_32_BIG) ++template ++void ++Sized_symbol<32>::init_output_data(const char* name, const char* version, ++ Output_data* od, Value_type value, ++ Size_type symsize, elfcpp::STT type, ++ elfcpp::STB binding, ++ elfcpp::STV visibility, ++ unsigned char nonvis, ++ bool offset_is_from_end, ++ bool is_predefined); ++#endif ++ ++#if defined(HAVE_TARGET_64_LITTLE) || defined(HAVE_TARGET_64_BIG) ++template ++void ++Sized_symbol<64>::init_output_data(const char* name, const char* version, ++ Output_data* od, Value_type value, ++ Size_type symsize, elfcpp::STT type, ++ elfcpp::STB binding, ++ elfcpp::STV visibility, ++ unsigned char nonvis, ++ bool offset_is_from_end, ++ bool is_predefined); ++#endif ++ +#ifdef HAVE_TARGET_32_LITTLE +template +void @@ -2433491,13 +2445619,13 @@ index 0000000..2e17529 +} // End namespace gold. diff --git a/gold/symtab.h b/gold/symtab.h new file mode 100644 -index 0000000..1232c97 +index 0000000..ab5b5f9 --- /dev/null +++ b/gold/symtab.h -@@ -0,0 +1,1931 @@ +@@ -0,0 +1,1967 @@ +// symtab.h -- the gold symbol table -*- C++ -*- + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2433735,7 +2445863,7 @@ index 0000000..1232c97 + override_visibility(elfcpp::STV); + + // Set whether the symbol was originally a weak undef or a regular undef -+ // when resolved by a dynamic def. ++ // when resolved by a dynamic def or by a special symbol. + inline void + set_undef_binding(elfcpp::STB bind) + { @@ -2433746,7 +2445874,8 @@ index 0000000..1232c97 + } + } + -+ // Return TRUE if a weak undef was resolved by a dynamic def. ++ // Return TRUE if a weak undef was resolved by a dynamic def or ++ // by a special symbol. + inline bool + is_undef_binding_weak() const + { return this->undef_binding_weak_; } @@ -2433756,6 +2445885,11 @@ index 0000000..1232c97 + nonvis() const + { return this->nonvis_; } + ++ // Set the non-visibility part of the st_other field. ++ void ++ set_nonvis(unsigned int nonvis) ++ { this->nonvis_ = nonvis; } ++ + // Return whether this symbol is a forwarder. This will never be + // true of a symbol found in the hash table, but may be true of + // symbol pointers attached to object files. @@ -2434009,7 +2446143,20 @@ index 0000000..1232c97 + // Return whether this is a weak undefined symbol. + bool + is_weak_undefined() const -+ { return this->is_undefined() && this->binding() == elfcpp::STB_WEAK; } ++ { ++ return (this->is_undefined() ++ && (this->binding() == elfcpp::STB_WEAK ++ || this->is_undef_binding_weak())); ++ } ++ ++ // Return whether this is a strong undefined symbol. ++ bool ++ is_strong_undefined() const ++ { ++ return (this->is_undefined() ++ && this->binding() != elfcpp::STB_WEAK ++ && !this->is_undef_binding_weak()); ++ } + + // Return whether this is an absolute symbol. + bool @@ -2434073,8 +2446220,14 @@ index 0000000..1232c97 + if (!parameters->options().shared()) + return false; + -+ // If the user used -Bsymbolic, then nothing is preemptible. -+ if (parameters->options().Bsymbolic()) ++ // If the symbol was named in a --dynamic-list script, it is preemptible. ++ if (parameters->options().in_dynamic_list(this->name())) ++ return true; ++ ++ // If the user used -Bsymbolic or provided a --dynamic-list script, ++ // then nothing (else) is preemptible. ++ if (parameters->options().Bsymbolic() ++ || parameters->options().have_dynamic_list()) + return false; + + // If the user used -Bsymbolic-functions, then functions are not @@ -2434268,6 +2446421,18 @@ index 0000000..1232c97 + void + set_output_section(Output_section*); + ++ // Set the symbol's output segment. This is used for pre-defined ++ // symbols whose segments aren't known until after layout is done ++ // (e.g., __ehdr_start). ++ void ++ set_output_segment(Output_segment*, Segment_offset_base); ++ ++ // Set the symbol to undefined. This is used for pre-defined ++ // symbols whose segments aren't known until after layout is done ++ // (e.g., __ehdr_start). ++ void ++ set_undefined(); ++ + // Return whether there should be a warning for references to this + // symbol. + bool @@ -2434307,8 +2446472,7 @@ index 0000000..1232c97 + bool + may_need_copy_reloc() const + { -+ return (!parameters->options().output_is_position_independent() -+ && parameters->options().copyreloc() ++ return (parameters->options().copyreloc() + && this->is_from_dynobj() + && !this->is_func()); + } @@ -2434516,7 +2446680,7 @@ index 0000000..1232c97 + // True if UNDEF_BINDING_WEAK_ has been set (bit 32). + bool undef_binding_set_ : 1; + // True if this symbol was a weak undef resolved by a dynamic def -+ // (bit 33). ++ // or by a special symbol (bit 33). + bool undef_binding_weak_ : 1; + // True if this symbol is a predefined linker symbol (bit 34). + bool is_predefined_ : 1; @@ -2435428,13 +2447592,13 @@ index 0000000..1232c97 +#endif // !defined(GOLD_SYMTAB_H) diff --git a/gold/system.h b/gold/system.h new file mode 100644 -index 0000000..aea3723 +index 0000000..8d4d6be --- /dev/null +++ b/gold/system.h @@ -0,0 +1,171 @@ +// system.h -- general definitions for gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2012 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2435605,14 +2447769,13 @@ index 0000000..aea3723 +#endif // !defined(SYSTEM_H) diff --git a/gold/target-reloc.h b/gold/target-reloc.h new file mode 100644 -index 0000000..b544c78 +index 0000000..e44519b --- /dev/null +++ b/gold/target-reloc.h -@@ -0,0 +1,835 @@ +@@ -0,0 +1,832 @@ +// target-reloc.h -- target specific relocation support -*- C++ -*- + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 -+// Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2435796,7 +2447959,7 @@ index 0000000..b544c78 + return false; + + // We don't report weak symbols. -+ if (sym->binding() == elfcpp::STB_WEAK) ++ if (sym->is_weak_undefined()) + return false; + + // We don't report symbols defined in discarded sections. @@ -2435822,6 +2447985,10 @@ index 0000000..b544c78 + return false; + } + ++ // If the symbol is hidden, report it. ++ if (sym->visibility() == elfcpp::STV_HIDDEN) ++ return true; ++ + // When creating a shared library, only report unresolved symbols if + // -z defs was used. + if (parameters->options().shared() && !parameters->options().defs()) @@ -2436022,16 +2448189,10 @@ index 0000000..b544c78 + } + + if (issue_undefined_symbol_error(sym)) -+ { -+ gold_undefined_symbol_at_location(sym, relinfo, i, offset); -+ if (sym->is_cxx_vtable()) -+ gold_info(_("%s: the vtable symbol may be undefined because " -+ "the class is missing its key function"), -+ program_name); -+ } ++ gold_undefined_symbol_at_location(sym, relinfo, i, offset); + else if (sym != NULL + && sym->visibility() != elfcpp::STV_DEFAULT -+ && (sym->is_undefined() || sym->is_from_dynobj())) ++ && (sym->is_strong_undefined() || sym->is_from_dynobj())) + visibility_error(sym); + + if (sym != NULL && sym->has_warning()) @@ -2436446,14 +2448607,13 @@ index 0000000..b544c78 +#endif // !defined(GOLD_TARGET_RELOC_H) diff --git a/gold/target-select.cc b/gold/target-select.cc new file mode 100644 -index 0000000..e17cb7d +index 0000000..e5f2597 --- /dev/null +++ b/gold/target-select.cc -@@ -0,0 +1,220 @@ +@@ -0,0 +1,219 @@ +// target-select.cc -- select a target for an object file + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2012 -+// Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2436672,14 +2448832,13 @@ index 0000000..e17cb7d +} // End namespace gold. diff --git a/gold/target-select.h b/gold/target-select.h new file mode 100644 -index 0000000..2e16c2a +index 0000000..c18d84b --- /dev/null +++ b/gold/target-select.h -@@ -0,0 +1,279 @@ +@@ -0,0 +1,278 @@ +// target-select.h -- select a target for an object file -*- C++ -*- + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2012 -+// Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2436957,13 +2449116,13 @@ index 0000000..2e16c2a +#endif // !defined(GOLD_TARGET_SELECT_H) diff --git a/gold/target.cc b/gold/target.cc new file mode 100644 -index 0000000..cad3c95 +index 0000000..81c02cc --- /dev/null +++ b/gold/target.cc @@ -0,0 +1,260 @@ +// target.cc -- target support for gold. + -+// Copyright 2009, 2010, 2011, 2013 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Doug Kwan . + +// This file is part of gold. @@ -2437223,14 +2449382,13 @@ index 0000000..cad3c95 +} // End namespace gold. diff --git a/gold/target.h b/gold/target.h new file mode 100644 -index 0000000..415b7ed +index 0000000..e380591 --- /dev/null +++ b/gold/target.h -@@ -0,0 +1,1037 @@ +@@ -0,0 +1,1095 @@ +// target.h -- target support for gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 -+// Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2437266,6 +2449424,7 @@ index 0000000..415b7ed +#include "elfcpp.h" +#include "options.h" +#include "parameters.h" ++#include "stringpool.h" +#include "debug.h" + +namespace gold @@ -2437291,6 +2449450,7 @@ index 0000000..415b7ed +class Input_objects; +class Task; +struct Symbol_location; ++class Versions; + +// The abstract class for target specific handling. + @@ -2437683,6 +2449843,36 @@ index 0000000..415b7ed + entry_symbol_name() const + { return this->pti_->entry_symbol_name; } + ++ // Whether the target has a custom set_dynsym_indexes method. ++ bool ++ has_custom_set_dynsym_indexes() const ++ { return this->do_has_custom_set_dynsym_indexes(); } ++ ++ // Custom set_dynsym_indexes method for a target. ++ unsigned int ++ set_dynsym_indexes(std::vector* dyn_symbols, unsigned int index, ++ std::vector* syms, Stringpool* dynpool, ++ Versions* versions, Symbol_table* symtab) const ++ { ++ return this->do_set_dynsym_indexes(dyn_symbols, index, syms, dynpool, ++ versions, symtab); ++ } ++ ++ // Get the custom dynamic tag value. ++ unsigned int ++ dynamic_tag_custom_value(elfcpp::DT tag) const ++ { return this->do_dynamic_tag_custom_value(tag); } ++ ++ // Adjust the value written to the dynamic symbol table. ++ void ++ adjust_dyn_symbol(const Symbol* sym, unsigned char* view) const ++ { this->do_adjust_dyn_symbol(sym, view); } ++ ++ // Return whether to include the section in the link. ++ bool ++ should_include_section(elfcpp::Elf_Word sh_type) const ++ { return this->do_should_include_section(sh_type); } ++ + protected: + // This struct holds the constant information for a child class. We + // use a struct to avoid the overhead of virtual function calls for @@ -2437954,6 +2450144,33 @@ index 0000000..415b7ed + do_gc_mark_symbol(Symbol_table*, Symbol*) const + { } + ++ // This may be overridden by the child class. ++ virtual bool ++ do_has_custom_set_dynsym_indexes() const ++ { return false; } ++ ++ // This may be overridden by the child class. ++ virtual unsigned int ++ do_set_dynsym_indexes(std::vector*, unsigned int, ++ std::vector*, Stringpool*, Versions*, ++ Symbol_table*) const ++ { gold_unreachable(); } ++ ++ // This may be overridden by the child class. ++ virtual unsigned int ++ do_dynamic_tag_custom_value(elfcpp::DT) const ++ { gold_unreachable(); } ++ ++ // This may be overridden by the child class. ++ virtual void ++ do_adjust_dyn_symbol(const Symbol*, unsigned char*) const ++ { } ++ ++ // This may be overridden by the child class. ++ virtual bool ++ do_should_include_section(elfcpp::Elf_Word) const ++ { return true; } ++ + private: + // The implementations of the four do_make_elf_object virtual functions are + // almost identical except for their sizes and endianness. We use a template. @@ -2438266,10 +2450483,10 @@ index 0000000..415b7ed +#endif // !defined(GOLD_TARGET_H) diff --git a/gold/testsuite/Makefile.am b/gold/testsuite/Makefile.am new file mode 100644 -index 0000000..aca9df8 +index 0000000..379ac8a --- /dev/null +++ b/gold/testsuite/Makefile.am -@@ -0,0 +1,2914 @@ +@@ -0,0 +1,3013 @@ +# Process this file with automake to generate Makefile.in + +# As far as I can tell automake testing support assumes that the build @@ -2438291,18 +2450508,25 @@ index 0000000..aca9df8 + -DLOCALEDIR="\"$(datadir)/locale\"" \ + @INCINTL@ + ++# Some versions of GCC now automatically enable linker plugins, ++# but we want to run our tests without GCC's plugins. ++if HAVE_NO_USE_LINKER_PLUGIN ++OPT_NO_PLUGINS = -fno-use-linker-plugin ++endif ++ +# COMPILE1, LINK1, CXXCOMPILE1, CXXLINK1 are renamed from COMPILE, LINK, +# CXXCOMPILE and CXXLINK generated by automake 1.11.1. FIXME: they should +# be updated if they are different from automake used by gold. +COMPILE1 = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ + $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -+LINK1 = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@ ++LINK1 = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(OPT_NO_PLUGINS) \ ++ $(AM_LDFLAGS) $(LDFLAGS) -o $@ +CXXCOMPILE1 = $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \ + $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) -+CXXLINK1 = $(CXXLD) $(AM_CXXFLAGS) $(CXXFLAGS) $(AM_LDFLAGS) $(LDFLAGS) \ -+ -o $@ ++CXXLINK1 = $(CXXLD) $(AM_CXXFLAGS) $(CXXFLAGS) $(OPT_NO_PLUGINS) \ ++ $(AM_LDFLAGS) $(LDFLAGS) -o $@ + -+# Strip out -Wp,-D_FORTIFY_SOURCE=, which is rrelevant for the gold ++# Strip out -Wp,-D_FORTIFY_SOURCE=, which is irrelevant for the gold +# testsuite and incompatible with -O0 used in gold tests, from +# COMPILE, LINK, CXXCOMPILE and CXXLINK. +COMPILE = `echo $(COMPILE1) | sed -e 's/-Wp,-D_FORTIFY_SOURCE=[0-9[0-9]]*//'` @@ -2438475,6 +2450699,16 @@ index 0000000..aca9df8 +pr14265.stdout: pr14265 + $(TEST_NM) --format=bsd --numeric-sort $< > $@ + ++check_SCRIPTS += gc_dynamic_list_test.sh ++check_DATA += gc_dynamic_list_test.stdout ++MOSTLYCLEANFILES += gc_dynamic_list_test ++gc_dynamic_list_test.o: gc_dynamic_list_test.c ++ $(COMPILE) -c -ffunction-sections -o $@ $< ++gc_dynamic_list_test: gc_dynamic_list_test.o gcctestdir/ld $(srcdir)/gc_dynamic_list_test.t ++ $(LINK) -Bgcctestdir/ -Wl,--gc-sections -Wl,--dynamic-list,$(srcdir)/gc_dynamic_list_test.t gc_dynamic_list_test.o ++gc_dynamic_list_test.stdout: gc_dynamic_list_test ++ $(TEST_NM) gc_dynamic_list_test > $@ ++ +check_SCRIPTS += icf_test.sh +check_DATA += icf_test.map +MOSTLYCLEANFILES += icf_test icf_test.map @@ -2438772,6 +2451006,16 @@ index 0000000..aca9df8 + two_file_test_2_pie.o two_file_test_main_pie.o gcctestdir/ld + $(CXXLINK) -Bgcctestdir/ -pie two_file_test_1_pie.o two_file_test_1b_pie.o two_file_test_2_pie.o two_file_test_main_pie.o + ++check_PROGRAMS += pie_copyrelocs_test ++pie_copyrelocs_test_SOURCES = pie_copyrelocs_test.cc ++pie_copyrelocs_test_DEPENDENCIES = gcctestdir/ld pie_copyrelocs_shared_test.so ++pie_copyrelocs_test_LDFLAGS = -Bgcctestdir/ -Wl,-R,. -pie ++pie_copyrelocs_test_LDADD = pie_copyrelocs_shared_test.so ++pie_copyrelocs_shared_test.o: pie_copyrelocs_shared_test.cc ++ $(CXXCOMPILE) -O2 -fpic -c -o $@ $< ++pie_copyrelocs_shared_test.so: pie_copyrelocs_shared_test.o gcctestdir/ld ++ $(CXXLINK) -Bgcctestdir/ -shared pie_copyrelocs_shared_test.o ++ +check_SCRIPTS += two_file_shared.sh +check_DATA += two_file_shared.dbg +MOSTLYCLEANFILES += two_file_shared.dbg @@ -2438972,6 +2451216,18 @@ index 0000000..aca9df8 + test -d alt || mkdir -p alt + $(CXXLINK) -Bgcctestdir/ -shared weak_undef_file2.o + ++check_PROGRAMS += weak_undef_test_2 ++weak_undef_test_2_SOURCES = weak_undef_test_2.cc ++weak_undef_test_2_DEPENDENCIES = gcctestdir/ld libweak_undef_2.a ++weak_undef_test_2_LDFLAGS = -Bgcctestdir/ -u weak_undef_2 ++weak_undef_test_2_LDADD = -L . -lweak_undef_2 ++libweak_undef_2.a: weak_undef_file3.o weak_undef_file4.o ++ $(TEST_AR) rc $@ $^ ++weak_undef_file3.o: weak_undef_file3.cc ++ $(CXXCOMPILE) -c -o $@ $< ++weak_undef_file4.o: weak_undef_file4.cc ++ $(CXXCOMPILE) -c -o $@ $< ++ +if FN_PTRS_IN_SO_WITHOUT_PIC +check_PROGRAMS += weak_undef_nonpic_test +MOSTLYCLEANFILES += alt/weak_undef_lib_nonpic.so @@ -2439737,6 +2451993,22 @@ index 0000000..aca9df8 +dynamic_list.stdout: dynamic_list + $(TEST_READELF) -W --dyn-syms dynamic_list > dynamic_list.stdout + ++check_PROGRAMS += dynamic_list_2 ++dynamic_list_2_SOURCES = dynamic_list_2.cc ++dynamic_list_2_DEPENDENCIES = gcctestdir/ld dynamic_list_lib1.so dynamic_list_lib2.so ++dynamic_list_2_LDFLAGS = -Bgcctestdir/ -L. -Wl,-R,. -Wl,--no-as-needed ++dynamic_list_2_LDADD = dynamic_list_lib1.so dynamic_list_lib2.so ++ ++dynamic_list_lib1.so: gcctestdir/ld dynamic_list_lib1.o ++ $(CXXLINK) -Bgcctestdir/ -shared dynamic_list_lib1.o ++dynamic_list_lib1.o: dynamic_list_lib1.cc ++ $(CXXCOMPILE) -c -fpic -o $@ $< ++ ++dynamic_list_lib2.so: gcctestdir/ld dynamic_list_lib2.o $(srcdir)/dynamic_list_2.t ++ $(CXXLINK) -Bgcctestdir/ -shared -Wl,--dynamic-list,$(srcdir)/dynamic_list_2.t dynamic_list_lib2.o ++dynamic_list_lib2.o: dynamic_list_lib2.cc ++ $(CXXCOMPILE) -c -fpic -o $@ $< ++ +check_PROGRAMS += thin_archive_test_1 +MOSTLYCLEANFILES += libthin1.a libthin3.a libthinall.a \ + alt/thin_archive_test_2.o alt/thin_archive_test_4.o \ @@ -2440426,6 +2452698,50 @@ index 0000000..aca9df8 + +endif HAVE_PUBNAMES + ++# Test that __ehdr_start is defined correctly. ++check_PROGRAMS += ehdr_start_test_1 ++ehdr_start_test_1_SOURCES = ehdr_start_test.cc ++ehdr_start_test_1_DEPENDENCIES = gcctestdir/ld ++ehdr_start_test_1_CXXFLAGS = ++ehdr_start_test_1_LDFLAGS = -Bgcctestdir/ ++ehdr_start_test_1_LDADD = ++ ++# Test that __ehdr_start is defined correctly with a weak reference. ++check_PROGRAMS += ehdr_start_test_2 ++ehdr_start_test_2_SOURCES = ehdr_start_test.cc ++ehdr_start_test_2_DEPENDENCIES = gcctestdir/ld ++ehdr_start_test_2_CXXFLAGS = -DEHDR_START_WEAK ++ehdr_start_test_2_LDFLAGS = -Bgcctestdir/ ++ehdr_start_test_2_LDADD = ++ ++# Test that __ehdr_start is defined correctly when used with a linker script. ++check_PROGRAMS += ehdr_start_test_3 ++ehdr_start_test_3_SOURCES = ehdr_start_test.cc ++ehdr_start_test_3_DEPENDENCIES = gcctestdir/ld $(srcdir)/ehdr_start_test.t ++ehdr_start_test_3_CXXFLAGS = -DEHDR_START_WEAK ++ehdr_start_test_3_LDFLAGS = -Bgcctestdir/ -Wl,-T,$(srcdir)/ehdr_start_test.t ++ehdr_start_test_3_LDADD = ++ ++# Test that __ehdr_start is left undefined when the text segment is not ++# appropriately aligned. ++check_SCRIPTS += ehdr_start_test_4.sh ++check_DATA += ehdr_start_test_4.syms ++MOSTLYCLEANFILES += ehdr_start_test_4 ++ehdr_start_test_4.syms: ehdr_start_test_4 ++ $(TEST_NM) ehdr_start_test_4 > $@ ++ehdr_start_test_4: ehdr_start_test_4.o gcctestdir/ld ++ $(CXXLINK) -Bgcctestdir/ -Wl,-Ttext=0x100100 $< ++ehdr_start_test_4.o: ehdr_start_test.cc ++ $(CXXCOMPILE) -c -DEHDR_START_WEAK -o $@ $< ++ ++# Test that __ehdr_start is not overridden when supplied by the user. ++check_PROGRAMS += ehdr_start_test_5 ++ehdr_start_test_5_SOURCES = ehdr_start_test.cc ehdr_start_def.cc ++ehdr_start_test_5_DEPENDENCIES = gcctestdir/ld ++ehdr_start_test_5_CXXFLAGS = -DEHDR_START_USER_DEF ++ehdr_start_test_5_LDFLAGS = -Bgcctestdir/ ++ehdr_start_test_5_LDADD = ++ +# End-to-end incremental linking tests. +# Incremental linking is currently supported only on the x86_64 target. + @@ -2441186,10 +2453502,10 @@ index 0000000..aca9df8 +endif DEFAULT_TARGET_X86_64 diff --git a/gold/testsuite/Makefile.in b/gold/testsuite/Makefile.in new file mode 100644 -index 0000000..b86bea9 +index 0000000..04a42e8 --- /dev/null +++ b/gold/testsuite/Makefile.in -@@ -0,0 +1,5915 @@ +@@ -0,0 +1,6181 @@ +# Makefile.in generated by automake 1.11.1 from Makefile.am. +# @configure_input@ + @@ -2441270,7 +2453586,9 @@ index 0000000..b86bea9 +@GCC_TRUE@@NATIVE_LINKER_TRUE@am__append_2 = incremental_test.sh \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ gc_comdat_test.sh gc_tls_test.sh \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ gc_orphan_section_test.sh \ -+@GCC_TRUE@@NATIVE_LINKER_TRUE@ pr14265.sh icf_test.sh \ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ pr14265.sh \ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ gc_dynamic_list_test.sh \ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ icf_test.sh \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ icf_keep_unique_test.sh \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ icf_safe_test.sh \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ icf_safe_so_test.sh \ @@ -2441301,7 +2453619,9 @@ index 0000000..b86bea9 +@GCC_TRUE@@NATIVE_LINKER_TRUE@ gc_comdat_test.stdout \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ gc_tls_test.stdout \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ gc_orphan_section_test.stdout \ -+@GCC_TRUE@@NATIVE_LINKER_TRUE@ pr14265.stdout icf_test.map \ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ pr14265.stdout \ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ gc_dynamic_list_test.stdout \ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ icf_test.map \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ icf_keep_unique_test.stdout \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ icf_safe_test_1.stdout \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ icf_safe_test_2.stdout \ @@ -2441324,7 +2453644,8 @@ index 0000000..b86bea9 +@GCC_TRUE@@NATIVE_LINKER_TRUE@ incremental_test.cmdline \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ gc_comdat_test gc_tls_test \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ gc_orphan_section_test pr14265 \ -+@GCC_TRUE@@NATIVE_LINKER_TRUE@ icf_test icf_test.map \ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ gc_dynamic_list_test icf_test \ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ icf_test.map \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ icf_keep_unique_test \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ icf_safe_test icf_safe_test.map \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ icf_safe_so_test \ @@ -2441368,7 +2453689,8 @@ index 0000000..b86bea9 +@GCC_TRUE@@NATIVE_LINKER_TRUE@ two_file_separate_shared_12_test \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ two_file_separate_shared_21_test \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ two_file_relocatable_test \ -+@GCC_TRUE@@NATIVE_LINKER_TRUE@ two_file_pie_test ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ two_file_pie_test \ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ pie_copyrelocs_test + +# The nonpic tests will fail on platforms which can not put non-PIC +# code into shared libraries, so we just don't run them in that case. @@ -2441395,7 +2453717,8 @@ index 0000000..b86bea9 +@NATIVE_LINKER_FALSE@exception_test_DEPENDENCIES = +@GCC_TRUE@@HAVE_STATIC_TRUE@@NATIVE_LINKER_TRUE@am__append_14 = exception_static_test +@GCC_TRUE@@NATIVE_LINKER_TRUE@am__append_15 = weak_test \ -+@GCC_TRUE@@NATIVE_LINKER_TRUE@ weak_undef_test ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ weak_undef_test \ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ weak_undef_test_2 +@GCC_FALSE@weak_test_DEPENDENCIES = +@NATIVE_LINKER_FALSE@weak_test_DEPENDENCIES = +@FN_PTRS_IN_SO_WITHOUT_PIC_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@am__append_16 = weak_undef_nonpic_test @@ -2441510,6 +2453833,7 @@ index 0000000..b86bea9 +@GCC_TRUE@@NATIVE_LINKER_TRUE@ script_test_3 \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ tls_phdrs_script_test \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ tls_script_test script_test_11 \ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ dynamic_list_2 \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ thin_archive_test_1 \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ thin_archive_test_2 +@GCC_FALSE@script_test_1_DEPENDENCIES = @@ -2441708,7 +2454032,19 @@ index 0000000..b86bea9 +@NATIVE_LINKER_FALSE@ifuncmain7_DEPENDENCIES = + +# Test that --start-lib and --end-lib function correctly. -+@GCC_TRUE@@NATIVE_LINKER_TRUE@am__append_60 = start_lib_test ++ ++# Test that __ehdr_start is defined correctly. ++ ++# Test that __ehdr_start is defined correctly with a weak reference. ++ ++# Test that __ehdr_start is defined correctly when used with a linker script. ++ ++# Test that __ehdr_start is not overridden when supplied by the user. ++@GCC_TRUE@@NATIVE_LINKER_TRUE@am__append_60 = start_lib_test \ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ ehdr_start_test_1 \ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ ehdr_start_test_2 \ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ ehdr_start_test_3 \ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ ehdr_start_test_5 + +# Test that --gdb-index functions correctly without gcc-generated pubnames. +@GCC_TRUE@@HAVE_PUBNAMES_TRUE@@NATIVE_LINKER_TRUE@am__append_61 = gdb_index_test_1.sh @@ -2441731,10 +2454067,24 @@ index 0000000..b86bea9 +@GCC_TRUE@@HAVE_PUBNAMES_TRUE@@NATIVE_LINKER_TRUE@ gdb_index_test_3 \ +@GCC_TRUE@@HAVE_PUBNAMES_TRUE@@NATIVE_LINKER_TRUE@ gdb_index_test_4.stdout \ +@GCC_TRUE@@HAVE_PUBNAMES_TRUE@@NATIVE_LINKER_TRUE@ gdb_index_test_4 ++@GCC_FALSE@ehdr_start_test_1_DEPENDENCIES = ++@NATIVE_LINKER_FALSE@ehdr_start_test_1_DEPENDENCIES = ++@GCC_FALSE@ehdr_start_test_2_DEPENDENCIES = ++@NATIVE_LINKER_FALSE@ehdr_start_test_2_DEPENDENCIES = ++@GCC_FALSE@ehdr_start_test_3_DEPENDENCIES = ++@NATIVE_LINKER_FALSE@ehdr_start_test_3_DEPENDENCIES = ++ ++# Test that __ehdr_start is left undefined when the text segment is not ++# appropriately aligned. ++@GCC_TRUE@@NATIVE_LINKER_TRUE@am__append_70 = ehdr_start_test_4.sh ++@GCC_TRUE@@NATIVE_LINKER_TRUE@am__append_71 = ehdr_start_test_4.syms ++@GCC_TRUE@@NATIVE_LINKER_TRUE@am__append_72 = ehdr_start_test_4 ++@GCC_FALSE@ehdr_start_test_5_DEPENDENCIES = ++@NATIVE_LINKER_FALSE@ehdr_start_test_5_DEPENDENCIES = + +# Test the --incremental-unchanged flag with an archive library. +# The second link should not update the library. -+@DEFAULT_TARGET_X86_64_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@am__append_70 = incremental_test_2 \ ++@DEFAULT_TARGET_X86_64_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@am__append_73 = incremental_test_2 \ +@DEFAULT_TARGET_X86_64_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@ incremental_test_3 \ +@DEFAULT_TARGET_X86_64_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@ incremental_test_4 \ +@DEFAULT_TARGET_X86_64_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@ incremental_test_5 \ @@ -2441743,7 +2454093,7 @@ index 0000000..b86bea9 +@DEFAULT_TARGET_X86_64_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@ incremental_common_test_1 \ +@DEFAULT_TARGET_X86_64_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@ incremental_comdat_test_1 \ +@DEFAULT_TARGET_X86_64_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@ exception_x86_64_bnd_test -+@DEFAULT_TARGET_X86_64_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@am__append_71 = two_file_test_tmp_2.o \ ++@DEFAULT_TARGET_X86_64_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@am__append_74 = two_file_test_tmp_2.o \ +@DEFAULT_TARGET_X86_64_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@ two_file_test_tmp_3.o \ +@DEFAULT_TARGET_X86_64_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@ incremental_test_4.base \ +@DEFAULT_TARGET_X86_64_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@ two_file_test_tmp_4.o \ @@ -2441753,23 +2454103,23 @@ index 0000000..b86bea9 +# These tests work with native and cross linkers. + +# Test script section order. -+@NATIVE_OR_CROSS_LINKER_TRUE@am__append_72 = script_test_10.sh -+@NATIVE_OR_CROSS_LINKER_TRUE@am__append_73 = script_test_10.stdout -+@NATIVE_OR_CROSS_LINKER_TRUE@am__append_74 = script_test_10 ++@NATIVE_OR_CROSS_LINKER_TRUE@am__append_75 = script_test_10.sh ++@NATIVE_OR_CROSS_LINKER_TRUE@am__append_76 = script_test_10.stdout ++@NATIVE_OR_CROSS_LINKER_TRUE@am__append_77 = script_test_10 + +# These tests work with cross linkers only. -+@DEFAULT_TARGET_I386_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@am__append_75 = split_i386.sh -+@DEFAULT_TARGET_I386_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@am__append_76 = split_i386_1.stdout split_i386_2.stdout \ ++@DEFAULT_TARGET_I386_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@am__append_78 = split_i386.sh ++@DEFAULT_TARGET_I386_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@am__append_79 = split_i386_1.stdout split_i386_2.stdout \ +@DEFAULT_TARGET_I386_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@ split_i386_3.stdout split_i386_4.stdout split_i386_r.stdout + -+@DEFAULT_TARGET_I386_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@am__append_77 = split_i386_1 split_i386_2 split_i386_3 \ ++@DEFAULT_TARGET_I386_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@am__append_80 = split_i386_1 split_i386_2 split_i386_3 \ +@DEFAULT_TARGET_I386_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@ split_i386_4 split_i386_r + -+@DEFAULT_TARGET_X86_64_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@am__append_78 = split_x86_64.sh -+@DEFAULT_TARGET_X86_64_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@am__append_79 = split_x86_64_1.stdout split_x86_64_2.stdout \ ++@DEFAULT_TARGET_X86_64_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@am__append_81 = split_x86_64.sh ++@DEFAULT_TARGET_X86_64_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@am__append_82 = split_x86_64_1.stdout split_x86_64_2.stdout \ +@DEFAULT_TARGET_X86_64_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@ split_x86_64_3.stdout split_x86_64_4.stdout split_x86_64_r.stdout + -+@DEFAULT_TARGET_X86_64_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@am__append_80 = split_x86_64_1 split_x86_64_2 split_x86_64_3 \ ++@DEFAULT_TARGET_X86_64_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@am__append_83 = split_x86_64_1 split_x86_64_2 split_x86_64_3 \ +@DEFAULT_TARGET_X86_64_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@ split_x86_64_4 split_x86_64_r + + @@ -2441784,7 +2454134,7 @@ index 0000000..b86bea9 +# Check Thumb to Thumb farcall veneers + +# Check Thumb to ARM farcall veneers -+@DEFAULT_TARGET_ARM_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@am__append_81 = arm_abs_global.sh \ ++@DEFAULT_TARGET_ARM_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@am__append_84 = arm_abs_global.sh \ +@DEFAULT_TARGET_ARM_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@ arm_branch_in_range.sh \ +@DEFAULT_TARGET_ARM_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@ arm_branch_out_of_range.sh \ +@DEFAULT_TARGET_ARM_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@ arm_fix_v4bx.sh \ @@ -2441798,7 +2454148,7 @@ index 0000000..b86bea9 +@DEFAULT_TARGET_ARM_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@ arm_farcall_arm_thumb.sh \ +@DEFAULT_TARGET_ARM_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@ arm_farcall_thumb_thumb.sh \ +@DEFAULT_TARGET_ARM_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@ arm_farcall_thumb_arm.sh -+@DEFAULT_TARGET_ARM_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@am__append_82 = arm_abs_global.stdout \ ++@DEFAULT_TARGET_ARM_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@am__append_85 = arm_abs_global.stdout \ +@DEFAULT_TARGET_ARM_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@ arm_bl_in_range.stdout \ +@DEFAULT_TARGET_ARM_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@ arm_bl_out_of_range.stdout \ +@DEFAULT_TARGET_ARM_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@ thumb_bl_in_range.stdout \ @@ -2441843,7 +2454193,7 @@ index 0000000..b86bea9 +@DEFAULT_TARGET_ARM_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@ arm_farcall_thumb_thumb_6m.stdout \ +@DEFAULT_TARGET_ARM_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@ arm_farcall_thumb_arm.stdout \ +@DEFAULT_TARGET_ARM_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@ arm_farcall_thumb_arm_5t.stdout -+@DEFAULT_TARGET_ARM_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@am__append_83 = arm_abs_global \ ++@DEFAULT_TARGET_ARM_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@am__append_86 = arm_abs_global \ +@DEFAULT_TARGET_ARM_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@ arm_bl_in_range \ +@DEFAULT_TARGET_ARM_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@ arm_bl_out_of_range \ +@DEFAULT_TARGET_ARM_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@ thumb_bl_in_range \ @@ -2441886,10 +2454236,10 @@ index 0000000..b86bea9 +@DEFAULT_TARGET_ARM_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@ arm_farcall_thumb_thumb_6m \ +@DEFAULT_TARGET_ARM_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@ arm_farcall_thumb_arm \ +@DEFAULT_TARGET_ARM_TRUE@@NATIVE_OR_CROSS_LINKER_TRUE@ arm_farcall_thumb_arm_5t -+@DEFAULT_TARGET_X86_64_TRUE@am__append_84 = *.dwo *.dwp -+@DEFAULT_TARGET_X86_64_TRUE@am__append_85 = dwp_test_1.sh \ ++@DEFAULT_TARGET_X86_64_TRUE@am__append_87 = *.dwo *.dwp ++@DEFAULT_TARGET_X86_64_TRUE@am__append_88 = dwp_test_1.sh \ +@DEFAULT_TARGET_X86_64_TRUE@ dwp_test_2.sh -+@DEFAULT_TARGET_X86_64_TRUE@am__append_86 = dwp_test_1.stdout \ ++@DEFAULT_TARGET_X86_64_TRUE@am__append_89 = dwp_test_1.stdout \ +@DEFAULT_TARGET_X86_64_TRUE@ dwp_test_2.stdout +subdir = testsuite +DIST_COMMON = $(srcdir)/Makefile.in $(srcdir)/Makefile.am @@ -2441941,7 +2454291,8 @@ index 0000000..b86bea9 +@GCC_TRUE@@NATIVE_LINKER_TRUE@ two_file_separate_shared_12_test$(EXEEXT) \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ two_file_separate_shared_21_test$(EXEEXT) \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ two_file_relocatable_test$(EXEEXT) \ -+@GCC_TRUE@@NATIVE_LINKER_TRUE@ two_file_pie_test$(EXEEXT) ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ two_file_pie_test$(EXEEXT) \ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ pie_copyrelocs_test$(EXEEXT) +@FN_PTRS_IN_SO_WITHOUT_PIC_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@am__EXEEXT_9 = two_file_shared_1_nonpic_test$(EXEEXT) \ +@FN_PTRS_IN_SO_WITHOUT_PIC_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@ two_file_shared_2_nonpic_test$(EXEEXT) \ +@FN_PTRS_IN_SO_WITHOUT_PIC_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@ two_file_same_shared_nonpic_test$(EXEEXT) \ @@ -2441963,7 +2454314,8 @@ index 0000000..b86bea9 +@GCC_TRUE@@NATIVE_LINKER_TRUE@ exception_separate_shared_21_test$(EXEEXT) +@GCC_TRUE@@HAVE_STATIC_TRUE@@NATIVE_LINKER_TRUE@am__EXEEXT_11 = exception_static_test$(EXEEXT) +@GCC_TRUE@@NATIVE_LINKER_TRUE@am__EXEEXT_12 = weak_test$(EXEEXT) \ -+@GCC_TRUE@@NATIVE_LINKER_TRUE@ weak_undef_test$(EXEEXT) ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ weak_undef_test$(EXEEXT) \ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ weak_undef_test_2$(EXEEXT) +@FN_PTRS_IN_SO_WITHOUT_PIC_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@am__EXEEXT_13 = weak_undef_nonpic_test$(EXEEXT) +@GCC_TRUE@@NATIVE_LINKER_TRUE@am__EXEEXT_14 = \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ weak_alias_test$(EXEEXT) \ @@ -2442015,6 +2454367,7 @@ index 0000000..b86bea9 +@GCC_TRUE@@NATIVE_LINKER_TRUE@ tls_phdrs_script_test$(EXEEXT) \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ tls_script_test$(EXEEXT) \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ script_test_11$(EXEEXT) \ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ dynamic_list_2$(EXEEXT) \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ thin_archive_test_1$(EXEEXT) \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ thin_archive_test_2$(EXEEXT) +@GCC_TRUE@@NATIVE_LINKER_TRUE@@PLUGINS_TRUE@am__EXEEXT_23 = plugin_test_1$(EXEEXT) \ @@ -2442070,7 +2454423,11 @@ index 0000000..b86bea9 +@GCC_TRUE@@IFUNC_TRUE@@NATIVE_LINKER_TRUE@ ifuncmain7pic$(EXEEXT) \ +@GCC_TRUE@@IFUNC_TRUE@@NATIVE_LINKER_TRUE@ ifuncmain7pie$(EXEEXT) \ +@GCC_TRUE@@IFUNC_TRUE@@NATIVE_LINKER_TRUE@ ifuncvar$(EXEEXT) -+@GCC_TRUE@@NATIVE_LINKER_TRUE@am__EXEEXT_38 = start_lib_test$(EXEEXT) ++@GCC_TRUE@@NATIVE_LINKER_TRUE@am__EXEEXT_38 = start_lib_test$(EXEEXT) \ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ ehdr_start_test_1$(EXEEXT) \ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ ehdr_start_test_2$(EXEEXT) \ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ ehdr_start_test_3$(EXEEXT) \ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ ehdr_start_test_5$(EXEEXT) +@DEFAULT_TARGET_X86_64_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@am__EXEEXT_39 = incremental_test_2$(EXEEXT) \ +@DEFAULT_TARGET_X86_64_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@ incremental_test_3$(EXEEXT) \ +@DEFAULT_TARGET_X86_64_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@ incremental_test_4$(EXEEXT) \ @@ -2442159,6 +2454516,28 @@ index 0000000..b86bea9 + $(am__DEPENDENCIES_1) $(am__DEPENDENCIES_1) +discard_locals_test_LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(discard_locals_test_LDFLAGS) $(LDFLAGS) -o $@ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@am_dynamic_list_2_OBJECTS = \ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ dynamic_list_2.$(OBJEXT) ++dynamic_list_2_OBJECTS = $(am_dynamic_list_2_OBJECTS) ++dynamic_list_2_LINK = $(CXXLD) $(AM_CXXFLAGS) $(CXXFLAGS) \ ++ $(dynamic_list_2_LDFLAGS) $(LDFLAGS) -o $@ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@am_ehdr_start_test_1_OBJECTS = ehdr_start_test_1-ehdr_start_test.$(OBJEXT) ++ehdr_start_test_1_OBJECTS = $(am_ehdr_start_test_1_OBJECTS) ++ehdr_start_test_1_LINK = $(CXXLD) $(ehdr_start_test_1_CXXFLAGS) \ ++ $(CXXFLAGS) $(ehdr_start_test_1_LDFLAGS) $(LDFLAGS) -o $@ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@am_ehdr_start_test_2_OBJECTS = ehdr_start_test_2-ehdr_start_test.$(OBJEXT) ++ehdr_start_test_2_OBJECTS = $(am_ehdr_start_test_2_OBJECTS) ++ehdr_start_test_2_LINK = $(CXXLD) $(ehdr_start_test_2_CXXFLAGS) \ ++ $(CXXFLAGS) $(ehdr_start_test_2_LDFLAGS) $(LDFLAGS) -o $@ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@am_ehdr_start_test_3_OBJECTS = ehdr_start_test_3-ehdr_start_test.$(OBJEXT) ++ehdr_start_test_3_OBJECTS = $(am_ehdr_start_test_3_OBJECTS) ++ehdr_start_test_3_LINK = $(CXXLD) $(ehdr_start_test_3_CXXFLAGS) \ ++ $(CXXFLAGS) $(ehdr_start_test_3_LDFLAGS) $(LDFLAGS) -o $@ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@am_ehdr_start_test_5_OBJECTS = ehdr_start_test_5-ehdr_start_test.$(OBJEXT) \ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ ehdr_start_test_5-ehdr_start_def.$(OBJEXT) ++ehdr_start_test_5_OBJECTS = $(am_ehdr_start_test_5_OBJECTS) ++ehdr_start_test_5_LINK = $(CXXLD) $(ehdr_start_test_5_CXXFLAGS) \ ++ $(CXXFLAGS) $(ehdr_start_test_5_LDFLAGS) $(LDFLAGS) -o $@ +@GCC_TRUE@@NATIVE_LINKER_TRUE@am_exception_same_shared_test_OBJECTS = \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ exception_test_main.$(OBJEXT) +exception_same_shared_test_OBJECTS = \ @@ -2442538,6 +2454917,11 @@ index 0000000..b86bea9 +permission_test_DEPENDENCIES = libgoldtest.a ../libgold.a \ + ../../libiberty/libiberty.a $(am__DEPENDENCIES_1) \ + $(am__DEPENDENCIES_1) $(am__DEPENDENCIES_1) ++@GCC_TRUE@@NATIVE_LINKER_TRUE@am_pie_copyrelocs_test_OBJECTS = \ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ pie_copyrelocs_test.$(OBJEXT) ++pie_copyrelocs_test_OBJECTS = $(am_pie_copyrelocs_test_OBJECTS) ++pie_copyrelocs_test_LINK = $(CXXLD) $(AM_CXXFLAGS) $(CXXFLAGS) \ ++ $(pie_copyrelocs_test_LDFLAGS) $(LDFLAGS) -o $@ +plugin_test_1_SOURCES = plugin_test_1.c +plugin_test_1_OBJECTS = plugin_test_1.$(OBJEXT) +plugin_test_1_LDADD = $(LDADD) @@ -2442953,6 +2455337,11 @@ index 0000000..b86bea9 +weak_undef_test_OBJECTS = $(am_weak_undef_test_OBJECTS) +weak_undef_test_LINK = $(CXXLD) $(AM_CXXFLAGS) $(CXXFLAGS) \ + $(weak_undef_test_LDFLAGS) $(LDFLAGS) -o $@ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@am_weak_undef_test_2_OBJECTS = \ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ weak_undef_test_2.$(OBJEXT) ++weak_undef_test_2_OBJECTS = $(am_weak_undef_test_2_OBJECTS) ++weak_undef_test_2_LINK = $(CXXLD) $(AM_CXXFLAGS) $(CXXFLAGS) \ ++ $(weak_undef_test_2_LDFLAGS) $(LDFLAGS) -o $@ +DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir) +depcomp = $(SHELL) $(top_srcdir)/../depcomp +am__depfiles_maybe = depfiles @@ -2442965,6 +2455354,9 @@ index 0000000..b86bea9 + $(common_test_1_SOURCES) $(common_test_2_SOURCES) \ + $(constructor_static_test_SOURCES) $(constructor_test_SOURCES) \ + $(copy_test_SOURCES) $(discard_locals_test_SOURCES) \ ++ $(dynamic_list_2_SOURCES) $(ehdr_start_test_1_SOURCES) \ ++ $(ehdr_start_test_2_SOURCES) $(ehdr_start_test_3_SOURCES) \ ++ $(ehdr_start_test_5_SOURCES) \ + $(exception_same_shared_test_SOURCES) \ + $(exception_separate_shared_12_test_SOURCES) \ + $(exception_separate_shared_21_test_SOURCES) \ @@ -2442998,14 +2455390,15 @@ index 0000000..b86bea9 + $(large_symbol_alignment_SOURCES) $(leb128_unittest_SOURCES) \ + local_labels_test.c many_sections_r_test.c \ + $(many_sections_test_SOURCES) $(object_unittest_SOURCES) \ -+ permission_test.c plugin_test_1.c plugin_test_2.c \ -+ plugin_test_3.c plugin_test_4.c plugin_test_5.c \ -+ plugin_test_6.c plugin_test_7.c plugin_test_8.c \ -+ plugin_test_tls.c $(protected_1_SOURCES) \ -+ $(protected_2_SOURCES) $(relro_now_test_SOURCES) \ -+ $(relro_script_test_SOURCES) $(relro_strip_test_SOURCES) \ -+ $(relro_test_SOURCES) $(script_test_1_SOURCES) \ -+ script_test_11.c $(script_test_2_SOURCES) script_test_3.c \ ++ permission_test.c $(pie_copyrelocs_test_SOURCES) \ ++ plugin_test_1.c plugin_test_2.c plugin_test_3.c \ ++ plugin_test_4.c plugin_test_5.c plugin_test_6.c \ ++ plugin_test_7.c plugin_test_8.c plugin_test_tls.c \ ++ $(protected_1_SOURCES) $(protected_2_SOURCES) \ ++ $(relro_now_test_SOURCES) $(relro_script_test_SOURCES) \ ++ $(relro_strip_test_SOURCES) $(relro_test_SOURCES) \ ++ $(script_test_1_SOURCES) script_test_11.c \ ++ $(script_test_2_SOURCES) script_test_3.c \ + $(searched_file_test_SOURCES) start_lib_test.c \ + $(thin_archive_test_1_SOURCES) $(thin_archive_test_2_SOURCES) \ + $(tls_phdrs_script_test_SOURCES) $(tls_pic_test_SOURCES) \ @@ -2443039,7 +2455432,8 @@ index 0000000..b86bea9 + $(ver_test_2_SOURCES) $(ver_test_6_SOURCES) \ + $(ver_test_8_SOURCES) $(ver_test_9_SOURCES) \ + $(weak_alias_test_SOURCES) weak_plt.c $(weak_test_SOURCES) \ -+ $(weak_undef_nonpic_test_SOURCES) $(weak_undef_test_SOURCES) ++ $(weak_undef_nonpic_test_SOURCES) $(weak_undef_test_SOURCES) \ ++ $(weak_undef_test_2_SOURCES) +ETAGS = etags +CTAGS = ctags +am__tty_colors = \ @@ -2443267,21 +2455661,27 @@ index 0000000..b86bea9 + @INCINTL@ + + ++# Some versions of GCC now automatically enable linker plugins, ++# but we want to run our tests without GCC's plugins. ++@HAVE_NO_USE_LINKER_PLUGIN_TRUE@OPT_NO_PLUGINS = -fno-use-linker-plugin ++ +# COMPILE1, LINK1, CXXCOMPILE1, CXXLINK1 are renamed from COMPILE, LINK, +# CXXCOMPILE and CXXLINK generated by automake 1.11.1. FIXME: they should +# be updated if they are different from automake used by gold. +COMPILE1 = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ + $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) + -+LINK1 = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@ ++LINK1 = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(OPT_NO_PLUGINS) \ ++ $(AM_LDFLAGS) $(LDFLAGS) -o $@ ++ +CXXCOMPILE1 = $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \ + $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CXXFLAGS) $(CXXFLAGS) + -+CXXLINK1 = $(CXXLD) $(AM_CXXFLAGS) $(CXXFLAGS) $(AM_LDFLAGS) $(LDFLAGS) \ -+ -o $@ ++CXXLINK1 = $(CXXLD) $(AM_CXXFLAGS) $(CXXFLAGS) $(OPT_NO_PLUGINS) \ ++ $(AM_LDFLAGS) $(LDFLAGS) -o $@ + + -+# Strip out -Wp,-D_FORTIFY_SOURCE=, which is rrelevant for the gold ++# Strip out -Wp,-D_FORTIFY_SOURCE=, which is irrelevant for the gold +# testsuite and incompatible with -O0 used in gold tests, from +# COMPILE, LINK, CXXCOMPILE and CXXLINK. +COMPILE = `echo $(COMPILE1) | sed -e 's/-Wp,-D_FORTIFY_SOURCE=[0-9[0-9]]*//'` @@ -2443314,23 +2455714,24 @@ index 0000000..b86bea9 + $(am__append_17) $(am__append_26) $(am__append_28) \ + $(am__append_30) $(am__append_36) $(am__append_40) \ + $(am__append_41) $(am__append_47) $(am__append_63) \ -+ $(am__append_66) $(am__append_69) $(am__append_71) \ ++ $(am__append_66) $(am__append_69) $(am__append_72) \ + $(am__append_74) $(am__append_77) $(am__append_80) \ -+ $(am__append_83) $(am__append_84) ++ $(am__append_83) $(am__append_86) $(am__append_87) + +# We will add to these later, for each individual test. Note +# that we add each test under check_SCRIPTS or check_PROGRAMS; +# the TESTS variable is automatically populated from these. +check_SCRIPTS = $(am__append_2) $(am__append_34) $(am__append_38) \ + $(am__append_42) $(am__append_45) $(am__append_61) \ -+ $(am__append_64) $(am__append_67) $(am__append_72) \ ++ $(am__append_64) $(am__append_67) $(am__append_70) \ + $(am__append_75) $(am__append_78) $(am__append_81) \ -+ $(am__append_85) ++ $(am__append_84) $(am__append_88) +check_DATA = $(am__append_3) $(am__append_27) $(am__append_29) \ + $(am__append_35) $(am__append_39) $(am__append_43) \ + $(am__append_46) $(am__append_62) $(am__append_65) \ -+ $(am__append_68) $(am__append_73) $(am__append_76) \ -+ $(am__append_79) $(am__append_82) $(am__append_86) ++ $(am__append_68) $(am__append_71) $(am__append_76) \ ++ $(am__append_79) $(am__append_82) $(am__append_85) \ ++ $(am__append_89) +BUILT_SOURCES = $(am__append_25) +TESTS = $(check_SCRIPTS) $(check_PROGRAMS) + @@ -2443427,6 +2455828,10 @@ index 0000000..b86bea9 + +@GCC_TRUE@@NATIVE_LINKER_TRUE@two_file_relocatable_test_LDFLAGS = -Bgcctestdir/ -Wl,-R,. +@GCC_TRUE@@NATIVE_LINKER_TRUE@two_file_relocatable_test_LDADD = two_file_relocatable.o ++@GCC_TRUE@@NATIVE_LINKER_TRUE@pie_copyrelocs_test_SOURCES = pie_copyrelocs_test.cc ++@GCC_TRUE@@NATIVE_LINKER_TRUE@pie_copyrelocs_test_DEPENDENCIES = gcctestdir/ld pie_copyrelocs_shared_test.so ++@GCC_TRUE@@NATIVE_LINKER_TRUE@pie_copyrelocs_test_LDFLAGS = -Bgcctestdir/ -Wl,-R,. -pie ++@GCC_TRUE@@NATIVE_LINKER_TRUE@pie_copyrelocs_test_LDADD = pie_copyrelocs_shared_test.so +@FN_PTRS_IN_SO_WITHOUT_PIC_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@two_file_shared_1_nonpic_test_SOURCES = \ +@FN_PTRS_IN_SO_WITHOUT_PIC_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@ two_file_test_2.cc two_file_test_main.cc + @@ -2443540,6 +2455945,10 @@ index 0000000..b86bea9 +@GCC_TRUE@@NATIVE_LINKER_TRUE@weak_undef_test_DEPENDENCIES = gcctestdir/ld weak_undef_lib.so alt/weak_undef_lib.so +@GCC_TRUE@@NATIVE_LINKER_TRUE@weak_undef_test_LDFLAGS = -Bgcctestdir/ -Wl,-R,alt +@GCC_TRUE@@NATIVE_LINKER_TRUE@weak_undef_test_LDADD = -L . weak_undef_lib.so ++@GCC_TRUE@@NATIVE_LINKER_TRUE@weak_undef_test_2_SOURCES = weak_undef_test_2.cc ++@GCC_TRUE@@NATIVE_LINKER_TRUE@weak_undef_test_2_DEPENDENCIES = gcctestdir/ld libweak_undef_2.a ++@GCC_TRUE@@NATIVE_LINKER_TRUE@weak_undef_test_2_LDFLAGS = -Bgcctestdir/ -u weak_undef_2 ++@GCC_TRUE@@NATIVE_LINKER_TRUE@weak_undef_test_2_LDADD = -L . -lweak_undef_2 +@FN_PTRS_IN_SO_WITHOUT_PIC_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@weak_undef_nonpic_test_SOURCES = weak_undef_test.cc +@FN_PTRS_IN_SO_WITHOUT_PIC_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@weak_undef_nonpic_test_DEPENDENCIES = gcctestdir/ld weak_undef_lib_nonpic.so alt/weak_undef_lib_nonpic.so +@FN_PTRS_IN_SO_WITHOUT_PIC_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@weak_undef_nonpic_test_LDFLAGS = -Bgcctestdir/ -Wl,-R,alt @@ -2443708,6 +2456117,10 @@ index 0000000..b86bea9 +@GCC_TRUE@@NATIVE_LINKER_TRUE@tls_script_test_DEPENDENCIES = $(tls_test_DEPENDENCIES) $(srcdir)/script_test_4.t +@GCC_TRUE@@NATIVE_LINKER_TRUE@tls_script_test_LDFLAGS = $(tls_test_LDFLAGS) -Wl,-T,$(srcdir)/script_test_4.t +@GCC_TRUE@@NATIVE_LINKER_TRUE@tls_script_test_LDADD = $(tls_test_LDADD) ++@GCC_TRUE@@NATIVE_LINKER_TRUE@dynamic_list_2_SOURCES = dynamic_list_2.cc ++@GCC_TRUE@@NATIVE_LINKER_TRUE@dynamic_list_2_DEPENDENCIES = gcctestdir/ld dynamic_list_lib1.so dynamic_list_lib2.so ++@GCC_TRUE@@NATIVE_LINKER_TRUE@dynamic_list_2_LDFLAGS = -Bgcctestdir/ -L. -Wl,-R,. -Wl,--no-as-needed ++@GCC_TRUE@@NATIVE_LINKER_TRUE@dynamic_list_2_LDADD = dynamic_list_lib1.so dynamic_list_lib2.so +@GCC_TRUE@@NATIVE_LINKER_TRUE@thin_archive_test_1_SOURCES = thin_archive_main.cc +@GCC_TRUE@@NATIVE_LINKER_TRUE@thin_archive_test_1_DEPENDENCIES = gcctestdir/ld libthin1.a alt/libthin2.a +@GCC_TRUE@@NATIVE_LINKER_TRUE@thin_archive_test_1_LDFLAGS = -Bgcctestdir/ -Lalt @@ -2443790,6 +2456203,26 @@ index 0000000..b86bea9 +@GCC_TRUE@@IFUNC_TRUE@@NATIVE_LINKER_TRUE@ifuncvar_DEPENDENCIES = gcctestdir/ld ifuncvar.so +@GCC_TRUE@@IFUNC_TRUE@@NATIVE_LINKER_TRUE@ifuncvar_LDFLAGS = -Bgcctestdir/ -Wl,-R,. +@GCC_TRUE@@IFUNC_TRUE@@NATIVE_LINKER_TRUE@ifuncvar_LDADD = ifuncvar.so ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ehdr_start_test_1_SOURCES = ehdr_start_test.cc ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ehdr_start_test_1_DEPENDENCIES = gcctestdir/ld ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ehdr_start_test_1_CXXFLAGS = ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ehdr_start_test_1_LDFLAGS = -Bgcctestdir/ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ehdr_start_test_1_LDADD = ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ehdr_start_test_2_SOURCES = ehdr_start_test.cc ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ehdr_start_test_2_DEPENDENCIES = gcctestdir/ld ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ehdr_start_test_2_CXXFLAGS = -DEHDR_START_WEAK ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ehdr_start_test_2_LDFLAGS = -Bgcctestdir/ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ehdr_start_test_2_LDADD = ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ehdr_start_test_3_SOURCES = ehdr_start_test.cc ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ehdr_start_test_3_DEPENDENCIES = gcctestdir/ld $(srcdir)/ehdr_start_test.t ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ehdr_start_test_3_CXXFLAGS = -DEHDR_START_WEAK ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ehdr_start_test_3_LDFLAGS = -Bgcctestdir/ -Wl,-T,$(srcdir)/ehdr_start_test.t ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ehdr_start_test_3_LDADD = ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ehdr_start_test_5_SOURCES = ehdr_start_test.cc ehdr_start_def.cc ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ehdr_start_test_5_DEPENDENCIES = gcctestdir/ld ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ehdr_start_test_5_CXXFLAGS = -DEHDR_START_USER_DEF ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ehdr_start_test_5_LDFLAGS = -Bgcctestdir/ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ehdr_start_test_5_LDADD = +@DEFAULT_TARGET_X86_64_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@exception_x86_64_bnd_test_SOURCES = exception_test_main.cc +@DEFAULT_TARGET_X86_64_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@exception_x86_64_bnd_test_DEPENDENCIES = exception_x86_64_bnd_1.o \ +@DEFAULT_TARGET_X86_64_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@ exception_x86_64_bnd_2.o @@ -2443903,6 +2456336,21 @@ index 0000000..b86bea9 +discard_locals_test$(EXEEXT): $(discard_locals_test_OBJECTS) $(discard_locals_test_DEPENDENCIES) + @rm -f discard_locals_test$(EXEEXT) + $(discard_locals_test_LINK) $(discard_locals_test_OBJECTS) $(discard_locals_test_LDADD) $(LIBS) ++dynamic_list_2$(EXEEXT): $(dynamic_list_2_OBJECTS) $(dynamic_list_2_DEPENDENCIES) ++ @rm -f dynamic_list_2$(EXEEXT) ++ $(dynamic_list_2_LINK) $(dynamic_list_2_OBJECTS) $(dynamic_list_2_LDADD) $(LIBS) ++ehdr_start_test_1$(EXEEXT): $(ehdr_start_test_1_OBJECTS) $(ehdr_start_test_1_DEPENDENCIES) ++ @rm -f ehdr_start_test_1$(EXEEXT) ++ $(ehdr_start_test_1_LINK) $(ehdr_start_test_1_OBJECTS) $(ehdr_start_test_1_LDADD) $(LIBS) ++ehdr_start_test_2$(EXEEXT): $(ehdr_start_test_2_OBJECTS) $(ehdr_start_test_2_DEPENDENCIES) ++ @rm -f ehdr_start_test_2$(EXEEXT) ++ $(ehdr_start_test_2_LINK) $(ehdr_start_test_2_OBJECTS) $(ehdr_start_test_2_LDADD) $(LIBS) ++ehdr_start_test_3$(EXEEXT): $(ehdr_start_test_3_OBJECTS) $(ehdr_start_test_3_DEPENDENCIES) ++ @rm -f ehdr_start_test_3$(EXEEXT) ++ $(ehdr_start_test_3_LINK) $(ehdr_start_test_3_OBJECTS) $(ehdr_start_test_3_LDADD) $(LIBS) ++ehdr_start_test_5$(EXEEXT): $(ehdr_start_test_5_OBJECTS) $(ehdr_start_test_5_DEPENDENCIES) ++ @rm -f ehdr_start_test_5$(EXEEXT) ++ $(ehdr_start_test_5_LINK) $(ehdr_start_test_5_OBJECTS) $(ehdr_start_test_5_LDADD) $(LIBS) +exception_same_shared_test$(EXEEXT): $(exception_same_shared_test_OBJECTS) $(exception_same_shared_test_DEPENDENCIES) + @rm -f exception_same_shared_test$(EXEEXT) + $(exception_same_shared_test_LINK) $(exception_same_shared_test_OBJECTS) $(exception_same_shared_test_LDADD) $(LIBS) @@ -2444317,6 +2456765,9 @@ index 0000000..b86bea9 +@NATIVE_LINKER_FALSE@permission_test$(EXEEXT): $(permission_test_OBJECTS) $(permission_test_DEPENDENCIES) +@NATIVE_LINKER_FALSE@ @rm -f permission_test$(EXEEXT) +@NATIVE_LINKER_FALSE@ $(LINK) $(permission_test_OBJECTS) $(permission_test_LDADD) $(LIBS) ++pie_copyrelocs_test$(EXEEXT): $(pie_copyrelocs_test_OBJECTS) $(pie_copyrelocs_test_DEPENDENCIES) ++ @rm -f pie_copyrelocs_test$(EXEEXT) ++ $(pie_copyrelocs_test_LINK) $(pie_copyrelocs_test_OBJECTS) $(pie_copyrelocs_test_LDADD) $(LIBS) +@GCC_FALSE@plugin_test_1$(EXEEXT): $(plugin_test_1_OBJECTS) $(plugin_test_1_DEPENDENCIES) +@GCC_FALSE@ @rm -f plugin_test_1$(EXEEXT) +@GCC_FALSE@ $(LINK) $(plugin_test_1_OBJECTS) $(plugin_test_1_LDADD) $(LIBS) @@ -2444623,6 +2457074,9 @@ index 0000000..b86bea9 +weak_undef_test$(EXEEXT): $(weak_undef_test_OBJECTS) $(weak_undef_test_DEPENDENCIES) + @rm -f weak_undef_test$(EXEEXT) + $(weak_undef_test_LINK) $(weak_undef_test_OBJECTS) $(weak_undef_test_LDADD) $(LIBS) ++weak_undef_test_2$(EXEEXT): $(weak_undef_test_2_OBJECTS) $(weak_undef_test_2_DEPENDENCIES) ++ @rm -f weak_undef_test_2$(EXEEXT) ++ $(weak_undef_test_2_LINK) $(weak_undef_test_2_OBJECTS) $(weak_undef_test_2_LDADD) $(LIBS) + +mostlyclean-compile: + -rm -f *.$(OBJEXT) @@ -2444641,6 +2457095,12 @@ index 0000000..b86bea9 +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/constructor_test.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/copy_test.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/discard_locals_test.Po@am__quote@ ++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/dynamic_list_2.Po@am__quote@ ++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ehdr_start_test_1-ehdr_start_test.Po@am__quote@ ++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ehdr_start_test_2-ehdr_start_test.Po@am__quote@ ++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ehdr_start_test_3-ehdr_start_test.Po@am__quote@ ++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ehdr_start_test_5-ehdr_start_def.Po@am__quote@ ++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ehdr_start_test_5-ehdr_start_test.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/exception_test_1.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/exception_test_2.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/exception_test_main.Po@am__quote@ @@ -2444698,6 +2457158,7 @@ index 0000000..b86bea9 +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/many_sections_test.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/object_unittest.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/permission_test.Po@am__quote@ ++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pie_copyrelocs_test.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/plugin_test_1.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/plugin_test_2.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/plugin_test_3.Po@am__quote@ @@ -2444743,6 +2457204,7 @@ index 0000000..b86bea9 +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/weak_plt.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/weak_test.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/weak_undef_test.Po@am__quote@ ++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/weak_undef_test_2.Po@am__quote@ + +.c.o: +@am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $< @@ -2444786,6 +2457248,76 @@ index 0000000..b86bea9 +@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCXX_FALSE@ $(CXXCOMPILE) -c -o $@ `$(CYGPATH_W) '$<'` + ++ehdr_start_test_1-ehdr_start_test.o: ehdr_start_test.cc ++@am__fastdepCXX_TRUE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(ehdr_start_test_1_CXXFLAGS) $(CXXFLAGS) -MT ehdr_start_test_1-ehdr_start_test.o -MD -MP -MF $(DEPDIR)/ehdr_start_test_1-ehdr_start_test.Tpo -c -o ehdr_start_test_1-ehdr_start_test.o `test -f 'ehdr_start_test.cc' || echo '$(srcdir)/'`ehdr_start_test.cc ++@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/ehdr_start_test_1-ehdr_start_test.Tpo $(DEPDIR)/ehdr_start_test_1-ehdr_start_test.Po ++@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='ehdr_start_test.cc' object='ehdr_start_test_1-ehdr_start_test.o' libtool=no @AMDEPBACKSLASH@ ++@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@ ++@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(ehdr_start_test_1_CXXFLAGS) $(CXXFLAGS) -c -o ehdr_start_test_1-ehdr_start_test.o `test -f 'ehdr_start_test.cc' || echo '$(srcdir)/'`ehdr_start_test.cc ++ ++ehdr_start_test_1-ehdr_start_test.obj: ehdr_start_test.cc ++@am__fastdepCXX_TRUE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(ehdr_start_test_1_CXXFLAGS) $(CXXFLAGS) -MT ehdr_start_test_1-ehdr_start_test.obj -MD -MP -MF $(DEPDIR)/ehdr_start_test_1-ehdr_start_test.Tpo -c -o ehdr_start_test_1-ehdr_start_test.obj `if test -f 'ehdr_start_test.cc'; then $(CYGPATH_W) 'ehdr_start_test.cc'; else $(CYGPATH_W) '$(srcdir)/ehdr_start_test.cc'; fi` ++@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/ehdr_start_test_1-ehdr_start_test.Tpo $(DEPDIR)/ehdr_start_test_1-ehdr_start_test.Po ++@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='ehdr_start_test.cc' object='ehdr_start_test_1-ehdr_start_test.obj' libtool=no @AMDEPBACKSLASH@ ++@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@ ++@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(ehdr_start_test_1_CXXFLAGS) $(CXXFLAGS) -c -o ehdr_start_test_1-ehdr_start_test.obj `if test -f 'ehdr_start_test.cc'; then $(CYGPATH_W) 'ehdr_start_test.cc'; else $(CYGPATH_W) '$(srcdir)/ehdr_start_test.cc'; fi` ++ ++ehdr_start_test_2-ehdr_start_test.o: ehdr_start_test.cc ++@am__fastdepCXX_TRUE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(ehdr_start_test_2_CXXFLAGS) $(CXXFLAGS) -MT ehdr_start_test_2-ehdr_start_test.o -MD -MP -MF $(DEPDIR)/ehdr_start_test_2-ehdr_start_test.Tpo -c -o ehdr_start_test_2-ehdr_start_test.o `test -f 'ehdr_start_test.cc' || echo '$(srcdir)/'`ehdr_start_test.cc ++@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/ehdr_start_test_2-ehdr_start_test.Tpo $(DEPDIR)/ehdr_start_test_2-ehdr_start_test.Po ++@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='ehdr_start_test.cc' object='ehdr_start_test_2-ehdr_start_test.o' libtool=no @AMDEPBACKSLASH@ ++@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@ ++@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(ehdr_start_test_2_CXXFLAGS) $(CXXFLAGS) -c -o ehdr_start_test_2-ehdr_start_test.o `test -f 'ehdr_start_test.cc' || echo '$(srcdir)/'`ehdr_start_test.cc ++ ++ehdr_start_test_2-ehdr_start_test.obj: ehdr_start_test.cc ++@am__fastdepCXX_TRUE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(ehdr_start_test_2_CXXFLAGS) $(CXXFLAGS) -MT ehdr_start_test_2-ehdr_start_test.obj -MD -MP -MF $(DEPDIR)/ehdr_start_test_2-ehdr_start_test.Tpo -c -o ehdr_start_test_2-ehdr_start_test.obj `if test -f 'ehdr_start_test.cc'; then $(CYGPATH_W) 'ehdr_start_test.cc'; else $(CYGPATH_W) '$(srcdir)/ehdr_start_test.cc'; fi` ++@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/ehdr_start_test_2-ehdr_start_test.Tpo $(DEPDIR)/ehdr_start_test_2-ehdr_start_test.Po ++@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='ehdr_start_test.cc' object='ehdr_start_test_2-ehdr_start_test.obj' libtool=no @AMDEPBACKSLASH@ ++@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@ ++@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(ehdr_start_test_2_CXXFLAGS) $(CXXFLAGS) -c -o ehdr_start_test_2-ehdr_start_test.obj `if test -f 'ehdr_start_test.cc'; then $(CYGPATH_W) 'ehdr_start_test.cc'; else $(CYGPATH_W) '$(srcdir)/ehdr_start_test.cc'; fi` ++ ++ehdr_start_test_3-ehdr_start_test.o: ehdr_start_test.cc ++@am__fastdepCXX_TRUE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(ehdr_start_test_3_CXXFLAGS) $(CXXFLAGS) -MT ehdr_start_test_3-ehdr_start_test.o -MD -MP -MF $(DEPDIR)/ehdr_start_test_3-ehdr_start_test.Tpo -c -o ehdr_start_test_3-ehdr_start_test.o `test -f 'ehdr_start_test.cc' || echo '$(srcdir)/'`ehdr_start_test.cc ++@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/ehdr_start_test_3-ehdr_start_test.Tpo $(DEPDIR)/ehdr_start_test_3-ehdr_start_test.Po ++@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='ehdr_start_test.cc' object='ehdr_start_test_3-ehdr_start_test.o' libtool=no @AMDEPBACKSLASH@ ++@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@ ++@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(ehdr_start_test_3_CXXFLAGS) $(CXXFLAGS) -c -o ehdr_start_test_3-ehdr_start_test.o `test -f 'ehdr_start_test.cc' || echo '$(srcdir)/'`ehdr_start_test.cc ++ ++ehdr_start_test_3-ehdr_start_test.obj: ehdr_start_test.cc ++@am__fastdepCXX_TRUE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(ehdr_start_test_3_CXXFLAGS) $(CXXFLAGS) -MT ehdr_start_test_3-ehdr_start_test.obj -MD -MP -MF $(DEPDIR)/ehdr_start_test_3-ehdr_start_test.Tpo -c -o ehdr_start_test_3-ehdr_start_test.obj `if test -f 'ehdr_start_test.cc'; then $(CYGPATH_W) 'ehdr_start_test.cc'; else $(CYGPATH_W) '$(srcdir)/ehdr_start_test.cc'; fi` ++@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/ehdr_start_test_3-ehdr_start_test.Tpo $(DEPDIR)/ehdr_start_test_3-ehdr_start_test.Po ++@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='ehdr_start_test.cc' object='ehdr_start_test_3-ehdr_start_test.obj' libtool=no @AMDEPBACKSLASH@ ++@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@ ++@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(ehdr_start_test_3_CXXFLAGS) $(CXXFLAGS) -c -o ehdr_start_test_3-ehdr_start_test.obj `if test -f 'ehdr_start_test.cc'; then $(CYGPATH_W) 'ehdr_start_test.cc'; else $(CYGPATH_W) '$(srcdir)/ehdr_start_test.cc'; fi` ++ ++ehdr_start_test_5-ehdr_start_test.o: ehdr_start_test.cc ++@am__fastdepCXX_TRUE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(ehdr_start_test_5_CXXFLAGS) $(CXXFLAGS) -MT ehdr_start_test_5-ehdr_start_test.o -MD -MP -MF $(DEPDIR)/ehdr_start_test_5-ehdr_start_test.Tpo -c -o ehdr_start_test_5-ehdr_start_test.o `test -f 'ehdr_start_test.cc' || echo '$(srcdir)/'`ehdr_start_test.cc ++@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/ehdr_start_test_5-ehdr_start_test.Tpo $(DEPDIR)/ehdr_start_test_5-ehdr_start_test.Po ++@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='ehdr_start_test.cc' object='ehdr_start_test_5-ehdr_start_test.o' libtool=no @AMDEPBACKSLASH@ ++@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@ ++@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(ehdr_start_test_5_CXXFLAGS) $(CXXFLAGS) -c -o ehdr_start_test_5-ehdr_start_test.o `test -f 'ehdr_start_test.cc' || echo '$(srcdir)/'`ehdr_start_test.cc ++ ++ehdr_start_test_5-ehdr_start_test.obj: ehdr_start_test.cc ++@am__fastdepCXX_TRUE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(ehdr_start_test_5_CXXFLAGS) $(CXXFLAGS) -MT ehdr_start_test_5-ehdr_start_test.obj -MD -MP -MF $(DEPDIR)/ehdr_start_test_5-ehdr_start_test.Tpo -c -o ehdr_start_test_5-ehdr_start_test.obj `if test -f 'ehdr_start_test.cc'; then $(CYGPATH_W) 'ehdr_start_test.cc'; else $(CYGPATH_W) '$(srcdir)/ehdr_start_test.cc'; fi` ++@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/ehdr_start_test_5-ehdr_start_test.Tpo $(DEPDIR)/ehdr_start_test_5-ehdr_start_test.Po ++@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='ehdr_start_test.cc' object='ehdr_start_test_5-ehdr_start_test.obj' libtool=no @AMDEPBACKSLASH@ ++@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@ ++@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(ehdr_start_test_5_CXXFLAGS) $(CXXFLAGS) -c -o ehdr_start_test_5-ehdr_start_test.obj `if test -f 'ehdr_start_test.cc'; then $(CYGPATH_W) 'ehdr_start_test.cc'; else $(CYGPATH_W) '$(srcdir)/ehdr_start_test.cc'; fi` ++ ++ehdr_start_test_5-ehdr_start_def.o: ehdr_start_def.cc ++@am__fastdepCXX_TRUE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(ehdr_start_test_5_CXXFLAGS) $(CXXFLAGS) -MT ehdr_start_test_5-ehdr_start_def.o -MD -MP -MF $(DEPDIR)/ehdr_start_test_5-ehdr_start_def.Tpo -c -o ehdr_start_test_5-ehdr_start_def.o `test -f 'ehdr_start_def.cc' || echo '$(srcdir)/'`ehdr_start_def.cc ++@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/ehdr_start_test_5-ehdr_start_def.Tpo $(DEPDIR)/ehdr_start_test_5-ehdr_start_def.Po ++@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='ehdr_start_def.cc' object='ehdr_start_test_5-ehdr_start_def.o' libtool=no @AMDEPBACKSLASH@ ++@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@ ++@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(ehdr_start_test_5_CXXFLAGS) $(CXXFLAGS) -c -o ehdr_start_test_5-ehdr_start_def.o `test -f 'ehdr_start_def.cc' || echo '$(srcdir)/'`ehdr_start_def.cc ++ ++ehdr_start_test_5-ehdr_start_def.obj: ehdr_start_def.cc ++@am__fastdepCXX_TRUE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(ehdr_start_test_5_CXXFLAGS) $(CXXFLAGS) -MT ehdr_start_test_5-ehdr_start_def.obj -MD -MP -MF $(DEPDIR)/ehdr_start_test_5-ehdr_start_def.Tpo -c -o ehdr_start_test_5-ehdr_start_def.obj `if test -f 'ehdr_start_def.cc'; then $(CYGPATH_W) 'ehdr_start_def.cc'; else $(CYGPATH_W) '$(srcdir)/ehdr_start_def.cc'; fi` ++@am__fastdepCXX_TRUE@ $(am__mv) $(DEPDIR)/ehdr_start_test_5-ehdr_start_def.Tpo $(DEPDIR)/ehdr_start_test_5-ehdr_start_def.Po ++@AMDEP_TRUE@@am__fastdepCXX_FALSE@ source='ehdr_start_def.cc' object='ehdr_start_test_5-ehdr_start_def.obj' libtool=no @AMDEPBACKSLASH@ ++@AMDEP_TRUE@@am__fastdepCXX_FALSE@ DEPDIR=$(DEPDIR) $(CXXDEPMODE) $(depcomp) @AMDEPBACKSLASH@ ++@am__fastdepCXX_FALSE@ $(CXX) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(ehdr_start_test_5_CXXFLAGS) $(CXXFLAGS) -c -o ehdr_start_test_5-ehdr_start_def.obj `if test -f 'ehdr_start_def.cc'; then $(CYGPATH_W) 'ehdr_start_def.cc'; else $(CYGPATH_W) '$(srcdir)/ehdr_start_def.cc'; fi` ++ +ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES) + list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \ + unique=`for i in $$list; do \ @@ -2445000,6 +2457532,8 @@ index 0000000..b86bea9 + @p='gc_orphan_section_test.sh'; $(am__check_pre) $(LOG_COMPILE) "$$tst" $(am__check_post) +pr14265.sh.log: pr14265.sh + @p='pr14265.sh'; $(am__check_pre) $(LOG_COMPILE) "$$tst" $(am__check_post) ++gc_dynamic_list_test.sh.log: gc_dynamic_list_test.sh ++ @p='gc_dynamic_list_test.sh'; $(am__check_pre) $(LOG_COMPILE) "$$tst" $(am__check_post) +icf_test.sh.log: icf_test.sh + @p='icf_test.sh'; $(am__check_pre) $(LOG_COMPILE) "$$tst" $(am__check_post) +icf_keep_unique_test.sh.log: icf_keep_unique_test.sh @@ -2445104,6 +2457638,8 @@ index 0000000..b86bea9 + @p='gdb_index_test_3.sh'; $(am__check_pre) $(LOG_COMPILE) "$$tst" $(am__check_post) +gdb_index_test_4.sh.log: gdb_index_test_4.sh + @p='gdb_index_test_4.sh'; $(am__check_pre) $(LOG_COMPILE) "$$tst" $(am__check_post) ++ehdr_start_test_4.sh.log: ehdr_start_test_4.sh ++ @p='ehdr_start_test_4.sh'; $(am__check_pre) $(LOG_COMPILE) "$$tst" $(am__check_post) +script_test_10.sh.log: script_test_10.sh + @p='script_test_10.sh'; $(am__check_pre) $(LOG_COMPILE) "$$tst" $(am__check_post) +split_i386.sh.log: split_i386.sh @@ -2445190,6 +2457726,8 @@ index 0000000..b86bea9 + @p='two_file_relocatable_test$(EXEEXT)'; $(am__check_pre) $(LOG_COMPILE) "$$tst" $(am__check_post) +two_file_pie_test.log: two_file_pie_test$(EXEEXT) + @p='two_file_pie_test$(EXEEXT)'; $(am__check_pre) $(LOG_COMPILE) "$$tst" $(am__check_post) ++pie_copyrelocs_test.log: pie_copyrelocs_test$(EXEEXT) ++ @p='pie_copyrelocs_test$(EXEEXT)'; $(am__check_pre) $(LOG_COMPILE) "$$tst" $(am__check_post) +two_file_shared_1_nonpic_test.log: two_file_shared_1_nonpic_test$(EXEEXT) + @p='two_file_shared_1_nonpic_test$(EXEEXT)'; $(am__check_pre) $(LOG_COMPILE) "$$tst" $(am__check_post) +two_file_shared_2_nonpic_test.log: two_file_shared_2_nonpic_test$(EXEEXT) @@ -2445232,6 +2457770,8 @@ index 0000000..b86bea9 + @p='weak_test$(EXEEXT)'; $(am__check_pre) $(LOG_COMPILE) "$$tst" $(am__check_post) +weak_undef_test.log: weak_undef_test$(EXEEXT) + @p='weak_undef_test$(EXEEXT)'; $(am__check_pre) $(LOG_COMPILE) "$$tst" $(am__check_post) ++weak_undef_test_2.log: weak_undef_test_2$(EXEEXT) ++ @p='weak_undef_test_2$(EXEEXT)'; $(am__check_pre) $(LOG_COMPILE) "$$tst" $(am__check_post) +weak_undef_nonpic_test.log: weak_undef_nonpic_test$(EXEEXT) + @p='weak_undef_nonpic_test$(EXEEXT)'; $(am__check_pre) $(LOG_COMPILE) "$$tst" $(am__check_post) +weak_alias_test.log: weak_alias_test$(EXEEXT) @@ -2445326,6 +2457866,8 @@ index 0000000..b86bea9 + @p='tls_script_test$(EXEEXT)'; $(am__check_pre) $(LOG_COMPILE) "$$tst" $(am__check_post) +script_test_11.log: script_test_11$(EXEEXT) + @p='script_test_11$(EXEEXT)'; $(am__check_pre) $(LOG_COMPILE) "$$tst" $(am__check_post) ++dynamic_list_2.log: dynamic_list_2$(EXEEXT) ++ @p='dynamic_list_2$(EXEEXT)'; $(am__check_pre) $(LOG_COMPILE) "$$tst" $(am__check_post) +thin_archive_test_1.log: thin_archive_test_1$(EXEEXT) + @p='thin_archive_test_1$(EXEEXT)'; $(am__check_pre) $(LOG_COMPILE) "$$tst" $(am__check_post) +thin_archive_test_2.log: thin_archive_test_2$(EXEEXT) @@ -2445424,6 +2457966,14 @@ index 0000000..b86bea9 + @p='ifuncvar$(EXEEXT)'; $(am__check_pre) $(LOG_COMPILE) "$$tst" $(am__check_post) +start_lib_test.log: start_lib_test$(EXEEXT) + @p='start_lib_test$(EXEEXT)'; $(am__check_pre) $(LOG_COMPILE) "$$tst" $(am__check_post) ++ehdr_start_test_1.log: ehdr_start_test_1$(EXEEXT) ++ @p='ehdr_start_test_1$(EXEEXT)'; $(am__check_pre) $(LOG_COMPILE) "$$tst" $(am__check_post) ++ehdr_start_test_2.log: ehdr_start_test_2$(EXEEXT) ++ @p='ehdr_start_test_2$(EXEEXT)'; $(am__check_pre) $(LOG_COMPILE) "$$tst" $(am__check_post) ++ehdr_start_test_3.log: ehdr_start_test_3$(EXEEXT) ++ @p='ehdr_start_test_3$(EXEEXT)'; $(am__check_pre) $(LOG_COMPILE) "$$tst" $(am__check_post) ++ehdr_start_test_5.log: ehdr_start_test_5$(EXEEXT) ++ @p='ehdr_start_test_5$(EXEEXT)'; $(am__check_pre) $(LOG_COMPILE) "$$tst" $(am__check_post) +incremental_test_2.log: incremental_test_2$(EXEEXT) + @p='incremental_test_2$(EXEEXT)'; $(am__check_pre) $(LOG_COMPILE) "$$tst" $(am__check_post) +incremental_test_3.log: incremental_test_3$(EXEEXT) @@ -2445643,6 +2458193,12 @@ index 0000000..b86bea9 +@GCC_TRUE@@NATIVE_LINKER_TRUE@ $(LINK) -Bgcctestdir/ -Wl,--gc-sections -Wl,-T,$(srcdir)/pr14265.t -o $@ $< +@GCC_TRUE@@NATIVE_LINKER_TRUE@pr14265.stdout: pr14265 +@GCC_TRUE@@NATIVE_LINKER_TRUE@ $(TEST_NM) --format=bsd --numeric-sort $< > $@ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@gc_dynamic_list_test.o: gc_dynamic_list_test.c ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ $(COMPILE) -c -ffunction-sections -o $@ $< ++@GCC_TRUE@@NATIVE_LINKER_TRUE@gc_dynamic_list_test: gc_dynamic_list_test.o gcctestdir/ld $(srcdir)/gc_dynamic_list_test.t ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ $(LINK) -Bgcctestdir/ -Wl,--gc-sections -Wl,--dynamic-list,$(srcdir)/gc_dynamic_list_test.t gc_dynamic_list_test.o ++@GCC_TRUE@@NATIVE_LINKER_TRUE@gc_dynamic_list_test.stdout: gc_dynamic_list_test ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ $(TEST_NM) gc_dynamic_list_test > $@ +@GCC_TRUE@@NATIVE_LINKER_TRUE@icf_test.o: icf_test.cc +@GCC_TRUE@@NATIVE_LINKER_TRUE@ $(CXXCOMPILE) -O0 -c -ffunction-sections -g -o $@ $< +@GCC_TRUE@@NATIVE_LINKER_TRUE@icf_test: icf_test.o gcctestdir/ld @@ -2445775,6 +2458331,10 @@ index 0000000..b86bea9 +@GCC_TRUE@@NATIVE_LINKER_TRUE@two_file_pie_test: two_file_test_1_pie.o two_file_test_1b_pie.o \ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ two_file_test_2_pie.o two_file_test_main_pie.o gcctestdir/ld +@GCC_TRUE@@NATIVE_LINKER_TRUE@ $(CXXLINK) -Bgcctestdir/ -pie two_file_test_1_pie.o two_file_test_1b_pie.o two_file_test_2_pie.o two_file_test_main_pie.o ++@GCC_TRUE@@NATIVE_LINKER_TRUE@pie_copyrelocs_shared_test.o: pie_copyrelocs_shared_test.cc ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ $(CXXCOMPILE) -O2 -fpic -c -o $@ $< ++@GCC_TRUE@@NATIVE_LINKER_TRUE@pie_copyrelocs_shared_test.so: pie_copyrelocs_shared_test.o gcctestdir/ld ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ $(CXXLINK) -Bgcctestdir/ -shared pie_copyrelocs_shared_test.o +@GCC_TRUE@@NATIVE_LINKER_TRUE@two_file_shared.dbg: two_file_shared.so +@GCC_TRUE@@NATIVE_LINKER_TRUE@ $(TEST_READELF) -w $< >$@ 2>/dev/null +@FN_PTRS_IN_SO_WITHOUT_PIC_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@two_file_shared_1_nonpic.so: two_file_test_1.o gcctestdir/ld @@ -2445821,6 +2458381,12 @@ index 0000000..b86bea9 +@GCC_TRUE@@NATIVE_LINKER_TRUE@alt/weak_undef_lib.so: weak_undef_file2.o +@GCC_TRUE@@NATIVE_LINKER_TRUE@ test -d alt || mkdir -p alt +@GCC_TRUE@@NATIVE_LINKER_TRUE@ $(CXXLINK) -Bgcctestdir/ -shared weak_undef_file2.o ++@GCC_TRUE@@NATIVE_LINKER_TRUE@libweak_undef_2.a: weak_undef_file3.o weak_undef_file4.o ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ $(TEST_AR) rc $@ $^ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@weak_undef_file3.o: weak_undef_file3.cc ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ $(CXXCOMPILE) -c -o $@ $< ++@GCC_TRUE@@NATIVE_LINKER_TRUE@weak_undef_file4.o: weak_undef_file4.cc ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ $(CXXCOMPILE) -c -o $@ $< +@FN_PTRS_IN_SO_WITHOUT_PIC_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@weak_undef_file1_nonpic.o: weak_undef_file1.cc +@FN_PTRS_IN_SO_WITHOUT_PIC_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@ $(CXXCOMPILE) -c -o $@ $< +@FN_PTRS_IN_SO_WITHOUT_PIC_TRUE@@GCC_TRUE@@NATIVE_LINKER_TRUE@weak_undef_file2_nonpic.o: weak_undef_file2.cc @@ -2446172,6 +2458738,16 @@ index 0000000..b86bea9 +@GCC_TRUE@@NATIVE_LINKER_TRUE@dynamic_list.stdout: dynamic_list +@GCC_TRUE@@NATIVE_LINKER_TRUE@ $(TEST_READELF) -W --dyn-syms dynamic_list > dynamic_list.stdout + ++@GCC_TRUE@@NATIVE_LINKER_TRUE@dynamic_list_lib1.so: gcctestdir/ld dynamic_list_lib1.o ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ $(CXXLINK) -Bgcctestdir/ -shared dynamic_list_lib1.o ++@GCC_TRUE@@NATIVE_LINKER_TRUE@dynamic_list_lib1.o: dynamic_list_lib1.cc ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ $(CXXCOMPILE) -c -fpic -o $@ $< ++ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@dynamic_list_lib2.so: gcctestdir/ld dynamic_list_lib2.o $(srcdir)/dynamic_list_2.t ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ $(CXXLINK) -Bgcctestdir/ -shared -Wl,--dynamic-list,$(srcdir)/dynamic_list_2.t dynamic_list_lib2.o ++@GCC_TRUE@@NATIVE_LINKER_TRUE@dynamic_list_lib2.o: dynamic_list_lib2.cc ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ $(CXXCOMPILE) -c -fpic -o $@ $< ++ +@GCC_TRUE@@NATIVE_LINKER_TRUE@libthin1.a: thin_archive_test_1.o alt/thin_archive_test_2.o +@GCC_TRUE@@NATIVE_LINKER_TRUE@ rm -f $@ +@GCC_TRUE@@NATIVE_LINKER_TRUE@ $(TEST_AR) crT $@ $^ @@ -2446526,6 +2459102,12 @@ index 0000000..b86bea9 +@GCC_TRUE@@HAVE_PUBNAMES_TRUE@@NATIVE_LINKER_TRUE@ $(CXXLINK) -Bgcctestdir/ -Wl,--gdb-index $< +@GCC_TRUE@@HAVE_PUBNAMES_TRUE@@NATIVE_LINKER_TRUE@gdb_index_test_4.stdout: gdb_index_test_4 +@GCC_TRUE@@HAVE_PUBNAMES_TRUE@@NATIVE_LINKER_TRUE@ $(TEST_READELF) --debug-dump=gdb_index $< > $@ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ehdr_start_test_4.syms: ehdr_start_test_4 ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ $(TEST_NM) ehdr_start_test_4 > $@ ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ehdr_start_test_4: ehdr_start_test_4.o gcctestdir/ld ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ $(CXXLINK) -Bgcctestdir/ -Wl,-Ttext=0x100100 $< ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ehdr_start_test_4.o: ehdr_start_test.cc ++@GCC_TRUE@@NATIVE_LINKER_TRUE@ $(CXXCOMPILE) -c -DEHDR_START_WEAK -o $@ $< + +# End-to-end incremental linking tests. +# Incremental linking is currently supported only on the x86_64 target. @@ -2447144,7 +2459726,7 @@ index 0000000..65cb309 + .word _abs32_global_plt diff --git a/gold/testsuite/arm_abs_global.sh b/gold/testsuite/arm_abs_global.sh new file mode 100755 -index 0000000..26abc24 +index 0000000..7445b1c --- /dev/null +++ b/gold/testsuite/arm_abs_global.sh @@ -0,0 +1,57 @@ @@ -2447152,7 +2459734,7 @@ index 0000000..26abc24 + +# arm_abs_global.sh -- test ARM absolute relocations against global symbols. + -+# Copyright 2010 Free Software Foundation, Inc. ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# Written by Doug Kwan + +# This file is part of gold. @@ -2447250,7 +2459832,7 @@ index 0000000..a2d7207 + .comm _abs32_global,4,4 diff --git a/gold/testsuite/arm_attr_merge.sh b/gold/testsuite/arm_attr_merge.sh new file mode 100755 -index 0000000..3066f4f +index 0000000..a579bb4 --- /dev/null +++ b/gold/testsuite/arm_attr_merge.sh @@ -0,0 +1,44 @@ @@ -2447258,7 +2459840,7 @@ index 0000000..3066f4f + +# arm_attr_merge.sh -- test ARM attributes merging. + -+# Copyright 2010 Free Software Foundation, Inc. ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# Written by Doug Kwan + +# This file is part of gold. @@ -2447442,7 +2460024,7 @@ index 0000000..cb5ff53 + .size _forward_target, .-_forward_target diff --git a/gold/testsuite/arm_branch_in_range.sh b/gold/testsuite/arm_branch_in_range.sh new file mode 100755 -index 0000000..dc6f36f +index 0000000..b034c9b --- /dev/null +++ b/gold/testsuite/arm_branch_in_range.sh @@ -0,0 +1,73 @@ @@ -2447451,7 +2460033,7 @@ index 0000000..dc6f36f +# arm_branch_in_range.sh -- test ARM/THUMB/THUMB branch instructions whose +# targets are just within the branch range limits. + -+# Copyright 2010 Free Software Foundation, Inc. ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# Written by Doug Kwan + +# This file is part of gold. @@ -2447521,7 +2460103,7 @@ index 0000000..dc6f36f +exit 0 diff --git a/gold/testsuite/arm_branch_out_of_range.sh b/gold/testsuite/arm_branch_out_of_range.sh new file mode 100755 -index 0000000..aac638f +index 0000000..aba1873 --- /dev/null +++ b/gold/testsuite/arm_branch_out_of_range.sh @@ -0,0 +1,123 @@ @@ -2447530,7 +2460112,7 @@ index 0000000..aac638f +# arm_branch_out_of_range.sh -- test ARM/THUMB/THUMB branch instructions whose +# targets are just out of the branch range limits. + -+# Copyright 2010 Free Software Foundation, Inc. ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# Written by Doug Kwan + +# This file is part of gold. @@ -2447650,13 +2460232,13 @@ index 0000000..aac638f +exit 0 diff --git a/gold/testsuite/arm_branch_range.t b/gold/testsuite/arm_branch_range.t new file mode 100644 -index 0000000..865e404 +index 0000000..7db4c64 --- /dev/null +++ b/gold/testsuite/arm_branch_range.t @@ -0,0 +1,36 @@ +/* arm_banch_range.t -- linker script to test ARM branch range. + -+ Copyright 2010 Free Software Foundation, Inc. ++ Copyright (C) 2010-2014 Free Software Foundation, Inc. + Written by Doug Kwan . + + This file is part of gold. @@ -2447692,7 +2460274,7 @@ index 0000000..865e404 +} diff --git a/gold/testsuite/arm_cortex_a8.sh b/gold/testsuite/arm_cortex_a8.sh new file mode 100755 -index 0000000..5e25c25 +index 0000000..cd7c3c8 --- /dev/null +++ b/gold/testsuite/arm_cortex_a8.sh @@ -0,0 +1,65 @@ @@ -2447700,7 +2460282,7 @@ index 0000000..5e25c25 + +# arm_cortex_a8.sh -- a test case for the Cortex-A8 workaround. + -+# Copyright 2010 Free Software Foundation, Inc. ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# Written by Doug Kwan . + +# This file is part of gold. @@ -2448077,7 +2460659,7 @@ index 0000000..8e550e4 + .word __exidx_end(got) diff --git a/gold/testsuite/arm_exidx_test.sh b/gold/testsuite/arm_exidx_test.sh new file mode 100755 -index 0000000..e196f12 +index 0000000..9f7bd75 --- /dev/null +++ b/gold/testsuite/arm_exidx_test.sh @@ -0,0 +1,60 @@ @@ -2448085,7 +2460667,7 @@ index 0000000..e196f12 + +# arm_exidx_test.sh -- a test case for .ARM.exidx section. + -+# Copyright 2011 Free Software Foundation, Inc. ++# Copyright (C) 2011-2014 Free Software Foundation, Inc. +# Written by Doug Kwan . + +# This file is part of gold. @@ -2448169,7 +2460751,7 @@ index 0000000..00c1e48 + diff --git a/gold/testsuite/arm_farcall_arm_arm.sh b/gold/testsuite/arm_farcall_arm_arm.sh new file mode 100755 -index 0000000..7d95528 +index 0000000..ae59dd2 --- /dev/null +++ b/gold/testsuite/arm_farcall_arm_arm.sh @@ -0,0 +1,44 @@ @@ -2448177,7 +2460759,7 @@ index 0000000..7d95528 + +# arm_farcall_arm_arm.sh -- a test case for ARM->ARM farcall veneers + -+# Copyright 2010, 2011, Free Software Foundation, Inc. ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# Written by Matthew Gretton-Dann +# Based upon arm_cortex_a8.sh +# Written by Doug Kwan . @@ -2448245,7 +2460827,7 @@ index 0000000..c69f31c + diff --git a/gold/testsuite/arm_farcall_arm_thumb.sh b/gold/testsuite/arm_farcall_arm_thumb.sh new file mode 100755 -index 0000000..2df2d65 +index 0000000..8847f44 --- /dev/null +++ b/gold/testsuite/arm_farcall_arm_thumb.sh @@ -0,0 +1,50 @@ @@ -2448253,7 +2460835,7 @@ index 0000000..2df2d65 + +# arm_farcall_arm_thumb.sh -- a test case for ARM->Thumb farcall veneers. + -+# Copyright 2010, 2011, Free Software Foundation, Inc. ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# Written by Matthew Gretton-Dann +# Based upon arm_cortex_a8.sh +# Written by Doug Kwan . @@ -2448334,7 +2460916,7 @@ index 0000000..1fd6a07 + diff --git a/gold/testsuite/arm_farcall_thumb_arm.sh b/gold/testsuite/arm_farcall_thumb_arm.sh new file mode 100755 -index 0000000..e22da46 +index 0000000..b13e783 --- /dev/null +++ b/gold/testsuite/arm_farcall_thumb_arm.sh @@ -0,0 +1,56 @@ @@ -2448342,7 +2460924,7 @@ index 0000000..e22da46 + +# arm_farcall_thumb_arm.sh -- a test case for Thumb->ARM farcall veneers. + -+# Copyright 2010, 2011, Free Software Foundation, Inc. ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# Written by Matthew Gretton-Dann +# Based upon arm_cortex_a8.sh +# Written by Doug Kwan . @@ -2448421,7 +2461003,7 @@ index 0000000..650b1a6 + diff --git a/gold/testsuite/arm_farcall_thumb_thumb.sh b/gold/testsuite/arm_farcall_thumb_thumb.sh new file mode 100755 -index 0000000..23fb0cd +index 0000000..838535c --- /dev/null +++ b/gold/testsuite/arm_farcall_thumb_thumb.sh @@ -0,0 +1,74 @@ @@ -2448429,7 +2461011,7 @@ index 0000000..23fb0cd + +# arm_farcall_thumb_thumb.sh -- a test case for Thumb->Thumb farcall veneers. + -+# Copyright 2010, 2011, Free Software Foundation, Inc. ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# Written by Matthew Gretton-Dann +# Based upon arm_cortex_a8.sh +# Written by Doug Kwan . @@ -2448522,7 +2461104,7 @@ index 0000000..96e0328 + diff --git a/gold/testsuite/arm_fix_1176.sh b/gold/testsuite/arm_fix_1176.sh new file mode 100755 -index 0000000..152b0a3 +index 0000000..4fe5465 --- /dev/null +++ b/gold/testsuite/arm_fix_1176.sh @@ -0,0 +1,61 @@ @@ -2448530,7 +2461112,7 @@ index 0000000..152b0a3 + +# arm_fix_1176.sh -- a test case for the ARM1176 workaround. + -+# Copyright 2010, 2011, Free Software Foundation, Inc. ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# Written by Matthew Gretton-Dann +# Based upon arm_cortex_a8.sh +# Written by Doug Kwan . @@ -2448610,7 +2461192,7 @@ index 0000000..fc3aa2a + .size _start, .-_start diff --git a/gold/testsuite/arm_fix_v4bx.sh b/gold/testsuite/arm_fix_v4bx.sh new file mode 100755 -index 0000000..a331ff9 +index 0000000..aeead67 --- /dev/null +++ b/gold/testsuite/arm_fix_v4bx.sh @@ -0,0 +1,56 @@ @@ -2448618,7 +2461200,7 @@ index 0000000..a331ff9 + +# arm_v4bx.sh -- a test case for --fix-v4bx and --fix-v4bx-interworking. + -+# Copyright 2010 Free Software Foundation, Inc. ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# Written by Doug Kwan . + +# This file is part of gold. @@ -2448735,13 +2461317,13 @@ index 0000000..41f1ce7 + .size _forward_target, .-_forward_target diff --git a/gold/testsuite/arm_thm_jump11.t b/gold/testsuite/arm_thm_jump11.t new file mode 100644 -index 0000000..2ec4143 +index 0000000..abd2252 --- /dev/null +++ b/gold/testsuite/arm_thm_jump11.t @@ -0,0 +1,36 @@ +/* arm_thm_jump11.t -- linker script to test R_ARM_THM_JUMP11 relocation. + -+ Copyright 2011 Free Software Foundation, Inc. ++ Copyright (C) 2011-2014 Free Software Foundation, Inc. + Written by Doug Kwan . + + This file is part of gold. @@ -2448840,13 +2461422,13 @@ index 0000000..540a243 + .size _forward_target, .-_forward_target diff --git a/gold/testsuite/arm_thm_jump8.t b/gold/testsuite/arm_thm_jump8.t new file mode 100644 -index 0000000..fa674b4 +index 0000000..d2af57d --- /dev/null +++ b/gold/testsuite/arm_thm_jump8.t @@ -0,0 +1,36 @@ +/* arm_thm_jump8.t -- linker script to test R_ARM_THM_JUMP8 relocation. + -+ Copyright 2011 Free Software Foundation, Inc. ++ Copyright (C) 2011-2014 Free Software Foundation, Inc. + Written by Doug Kwan . + + This file is part of gold. @@ -2448932,7 +2461514,7 @@ index 0000000..7677bff + .short 0 diff --git a/gold/testsuite/arm_unaligned_reloc.sh b/gold/testsuite/arm_unaligned_reloc.sh new file mode 100755 -index 0000000..39a5a11 +index 0000000..bb1c43e --- /dev/null +++ b/gold/testsuite/arm_unaligned_reloc.sh @@ -0,0 +1,57 @@ @@ -2448940,7 +2461522,7 @@ index 0000000..39a5a11 + +# arm_unaligned_reloc.sh -- test ARM unaligned static data relocations. + -+# Copyright 2011 Free Software Foundation, Inc. ++# Copyright (C) 2011-2014 Free Software Foundation, Inc. +# Written by Doug Kwan + +# This file is part of gold. @@ -2448995,13 +2461577,13 @@ index 0000000..39a5a11 +exit 0 diff --git a/gold/testsuite/basic_test.cc b/gold/testsuite/basic_test.cc new file mode 100644 -index 0000000..94910be +index 0000000..a8729cf --- /dev/null +++ b/gold/testsuite/basic_test.cc @@ -0,0 +1,318 @@ +// basic_test.cc -- a test case for gold + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2449326,13 +2461908,13 @@ index 0000000..cf5d631 +This file is used for the binary test. diff --git a/gold/testsuite/binary_test.cc b/gold/testsuite/binary_test.cc new file mode 100644 -index 0000000..d645536 +index 0000000..be788bd --- /dev/null +++ b/gold/testsuite/binary_test.cc @@ -0,0 +1,46 @@ +// binary_test.cc -- test --format binary for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2449378,13 +2461960,13 @@ index 0000000..d645536 +} diff --git a/gold/testsuite/binary_unittest.cc b/gold/testsuite/binary_unittest.cc new file mode 100644 -index 0000000..fe10922 +index 0000000..f920de8 --- /dev/null +++ b/gold/testsuite/binary_unittest.cc @@ -0,0 +1,184 @@ +// binary_unittest.cc -- test Binary_to_elf + -+// Copyright 2008, 2012 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2449568,13 +2462150,13 @@ index 0000000..fe10922 +} // End namespace gold_testsuite. diff --git a/gold/testsuite/common_test_1.c b/gold/testsuite/common_test_1.c new file mode 100644 -index 0000000..f5a28f4 +index 0000000..8c79a0b --- /dev/null +++ b/gold/testsuite/common_test_1.c @@ -0,0 +1,75 @@ +/* common_test_1.c -- test common symbol sorting + -+ Copyright 2008 Free Software Foundation, Inc. ++ Copyright (C) 2008-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor + + This file is part of gold. @@ -2449649,13 +2462231,13 @@ index 0000000..f5a28f4 +} diff --git a/gold/testsuite/common_test_1_v1.c b/gold/testsuite/common_test_1_v1.c new file mode 100644 -index 0000000..86abc40 +index 0000000..db65063 --- /dev/null +++ b/gold/testsuite/common_test_1_v1.c @@ -0,0 +1,79 @@ +/* common_test_1_v1.c -- test common symbol sorting + -+ Copyright 2008, 2011 Free Software Foundation, Inc. ++ Copyright (C) 2008-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor + + This file is part of gold. @@ -2449734,13 +2462316,13 @@ index 0000000..86abc40 +} diff --git a/gold/testsuite/common_test_1_v2.c b/gold/testsuite/common_test_1_v2.c new file mode 100644 -index 0000000..c66a647 +index 0000000..81614bf --- /dev/null +++ b/gold/testsuite/common_test_1_v2.c @@ -0,0 +1,77 @@ +/* common_test_1_v2.c -- test common symbol sorting + -+ Copyright 2008 Free Software Foundation, Inc. ++ Copyright (C) 2008-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor + + This file is part of gold. @@ -2449817,13 +2462399,13 @@ index 0000000..c66a647 +} diff --git a/gold/testsuite/common_test_2.c b/gold/testsuite/common_test_2.c new file mode 100644 -index 0000000..ef6d83d +index 0000000..9f29dfb --- /dev/null +++ b/gold/testsuite/common_test_2.c @@ -0,0 +1,33 @@ +/* common_test_2.c -- test common symbol name conflicts + -+ Copyright 2009 Free Software Foundation, Inc. ++ Copyright (C) 2009-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor + + This file is part of gold. @@ -2449856,13 +2462438,13 @@ index 0000000..ef6d83d +} diff --git a/gold/testsuite/common_test_3.c b/gold/testsuite/common_test_3.c new file mode 100644 -index 0000000..ba8960c +index 0000000..a8d8120 --- /dev/null +++ b/gold/testsuite/common_test_3.c @@ -0,0 +1,32 @@ +/* common_test_3.c -- test common symbol name conflicts + -+ Copyright 2009 Free Software Foundation, Inc. ++ Copyright (C) 2009-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor + + This file is part of gold. @@ -2449894,13 +2462476,13 @@ index 0000000..ba8960c +__asm__ (".symver c1_v1,c1@@VER1"); diff --git a/gold/testsuite/constructor_test.cc b/gold/testsuite/constructor_test.cc new file mode 100644 -index 0000000..8889a83 +index 0000000..5c3aa53 --- /dev/null +++ b/gold/testsuite/constructor_test.cc @@ -0,0 +1,90 @@ +// constructor_test.cc -- a test case for gold global constructors + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2449990,13 +2462572,13 @@ index 0000000..8889a83 +} diff --git a/gold/testsuite/copy_test.cc b/gold/testsuite/copy_test.cc new file mode 100644 -index 0000000..715529d +index 0000000..856511d --- /dev/null +++ b/gold/testsuite/copy_test.cc @@ -0,0 +1,43 @@ +// copy_test.cc -- test copy relocs for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2450039,13 +2462621,13 @@ index 0000000..715529d +} diff --git a/gold/testsuite/copy_test_1.cc b/gold/testsuite/copy_test_1.cc new file mode 100644 -index 0000000..1471bb5 +index 0000000..b653ded --- /dev/null +++ b/gold/testsuite/copy_test_1.cc @@ -0,0 +1,23 @@ +// copy_test_1.cc -- test copy relocs for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2450068,13 +2462650,13 @@ index 0000000..1471bb5 +char b = 1; diff --git a/gold/testsuite/copy_test_2.cc b/gold/testsuite/copy_test_2.cc new file mode 100644 -index 0000000..0105150 +index 0000000..8fd722a --- /dev/null +++ b/gold/testsuite/copy_test_2.cc @@ -0,0 +1,23 @@ +// copy_test_2.cc -- test copy relocs variables for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2450097,13 +2462679,13 @@ index 0000000..0105150 +long long l = 2; diff --git a/gold/testsuite/copy_test_v1.cc b/gold/testsuite/copy_test_v1.cc new file mode 100644 -index 0000000..63f7dfd +index 0000000..ce02884 --- /dev/null +++ b/gold/testsuite/copy_test_v1.cc @@ -0,0 +1,47 @@ +// copy_test_v1.cc -- test copy relocs for gold + -+// Copyright 2008, 2011 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2450150,13 +2462732,13 @@ index 0000000..63f7dfd +} diff --git a/gold/testsuite/debug_msg.cc b/gold/testsuite/debug_msg.cc new file mode 100644 -index 0000000..0912002 +index 0000000..e5beb5f --- /dev/null +++ b/gold/testsuite/debug_msg.cc @@ -0,0 +1,96 @@ +// debug_msg.cc -- a test case for printing debug info for missing symbols. + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2450252,16 +2462834,15 @@ index 0000000..0912002 +} diff --git a/gold/testsuite/debug_msg.sh b/gold/testsuite/debug_msg.sh new file mode 100755 -index 0000000..1227f3f +index 0000000..4426762 --- /dev/null +++ b/gold/testsuite/debug_msg.sh -@@ -0,0 +1,145 @@ +@@ -0,0 +1,144 @@ +#!/bin/sh + +# debug_msg.sh -- a test case for printing debug info for missing symbols. + -+# Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2013 -+# Free Software Foundation, Inc. ++# Copyright (C) 2006-2014 Free Software Foundation, Inc. +# Written by Ian Lance Taylor . + +# This file is part of gold. @@ -2450403,13 +2462984,13 @@ index 0000000..1227f3f +exit 0 diff --git a/gold/testsuite/discard_locals_relocatable_test.c b/gold/testsuite/discard_locals_relocatable_test.c new file mode 100644 -index 0000000..f7f8b27 +index 0000000..79f82db --- /dev/null +++ b/gold/testsuite/discard_locals_relocatable_test.c @@ -0,0 +1,52 @@ +/* discard_locals_relocatable_test.c -- test --discard-locals/--discard-all -r + -+ Copyright 2010 Free Software Foundation, Inc. ++ Copyright (C) 2010-2014 Free Software Foundation, Inc. + Viktor Kutuzov . + + This file is part of gold. @@ -2450461,13 +2463042,13 @@ index 0000000..f7f8b27 +} diff --git a/gold/testsuite/discard_locals_test.c b/gold/testsuite/discard_locals_test.c new file mode 100644 -index 0000000..b722447 +index 0000000..e8766c8 --- /dev/null +++ b/gold/testsuite/discard_locals_test.c @@ -0,0 +1,40 @@ +/* discard_locals_test.c -- test --discard-locals option. + -+ Copyright 2009 Free Software Foundation, Inc. ++ Copyright (C) 2009-2014 Free Software Foundation, Inc. + Doug Kwan . + + This file is part of gold. @@ -2450507,7 +2463088,7 @@ index 0000000..b722447 + diff --git a/gold/testsuite/discard_locals_test.sh b/gold/testsuite/discard_locals_test.sh new file mode 100755 -index 0000000..3fc679a +index 0000000..185d09b --- /dev/null +++ b/gold/testsuite/discard_locals_test.sh @@ -0,0 +1,63 @@ @@ -2450515,7 +2463096,7 @@ index 0000000..3fc679a + +# discard_locals_test.sh -- test that local symbols are discarded. + -+# Copyright 2009 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# Written by Doug Kwan + +# This file is part of gold. @@ -2450576,13 +2463157,13 @@ index 0000000..3fc679a +exit 0 diff --git a/gold/testsuite/dwp_test.h b/gold/testsuite/dwp_test.h new file mode 100644 -index 0000000..37256d3 +index 0000000..8e265ee --- /dev/null +++ b/gold/testsuite/dwp_test.h @@ -0,0 +1,87 @@ +// dwp_test.h -- a test case for dwp, header file -*- C++ -*- + -+// Copyright 2012 Free Software Foundation, Inc. ++// Copyright (C) 2012-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2450669,13 +2463250,13 @@ index 0000000..37256d3 +extern const char* f18(int); diff --git a/gold/testsuite/dwp_test_1.cc b/gold/testsuite/dwp_test_1.cc new file mode 100644 -index 0000000..71fbc5b +index 0000000..b3ae8bc --- /dev/null +++ b/gold/testsuite/dwp_test_1.cc @@ -0,0 +1,210 @@ +// dwp_test_1.cc -- a test case for dwp + -+// Copyright 2012 Free Software Foundation, Inc. ++// Copyright (C) 2012-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2453551,7 +2466132,7 @@ index 0000000..d3a898d + .section .note.GNU-stack,"",@progbits diff --git a/gold/testsuite/dwp_test_1.sh b/gold/testsuite/dwp_test_1.sh new file mode 100755 -index 0000000..7831a49 +index 0000000..90146ac --- /dev/null +++ b/gold/testsuite/dwp_test_1.sh @@ -0,0 +1,63 @@ @@ -2453559,7 +2466140,7 @@ index 0000000..7831a49 + +# dwp_test_1.sh -- Test the dwp tool. + -+# Copyright 2012 Free Software Foundation, Inc. ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# Written by Cary Coutant . + +# This file is part of gold. @@ -2453620,13 +2466201,13 @@ index 0000000..7831a49 +check_num $STDOUT "DW_AT_name.*: testcase4" 4 diff --git a/gold/testsuite/dwp_test_1b.cc b/gold/testsuite/dwp_test_1b.cc new file mode 100644 -index 0000000..c75376b +index 0000000..7ca28a5 --- /dev/null +++ b/gold/testsuite/dwp_test_1b.cc @@ -0,0 +1,35 @@ +// dwp_test_1b.cc -- a test case for dwp + -+// Copyright 2012 Free Software Foundation, Inc. ++// Copyright (C) 2012-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2454216,13 +2466797,13 @@ index 0000000..9c9891d + .section .note.GNU-stack,"",@progbits diff --git a/gold/testsuite/dwp_test_2.cc b/gold/testsuite/dwp_test_2.cc new file mode 100644 -index 0000000..a1172b3 +index 0000000..10baef0 --- /dev/null +++ b/gold/testsuite/dwp_test_2.cc @@ -0,0 +1,144 @@ +// dwp_test_2.cc -- a test case for dwp + -+// Copyright 2012 Free Software Foundation, Inc. ++// Copyright (C) 2012-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2456086,7 +2468667,7 @@ index 0000000..fa80771 + .section .note.GNU-stack,"",@progbits diff --git a/gold/testsuite/dwp_test_2.sh b/gold/testsuite/dwp_test_2.sh new file mode 100755 -index 0000000..619d73b +index 0000000..dd0fe51 --- /dev/null +++ b/gold/testsuite/dwp_test_2.sh @@ -0,0 +1,63 @@ @@ -2456094,7 +2468675,7 @@ index 0000000..619d73b + +# dwp_test_2.sh -- Test the dwp tool. + -+# Copyright 2012 Free Software Foundation, Inc. ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# Written by Cary Coutant . + +# This file is part of gold. @@ -2456155,13 +2468736,13 @@ index 0000000..619d73b +check_num $STDOUT "DW_AT_name.*: testcase4" 4 diff --git a/gold/testsuite/dwp_test_main.cc b/gold/testsuite/dwp_test_main.cc new file mode 100644 -index 0000000..abddc0f +index 0000000..7cf72ca --- /dev/null +++ b/gold/testsuite/dwp_test_main.cc @@ -0,0 +1,59 @@ +// dwp_test_main.cc -- a test case for dwp + -+// Copyright 2012 Free Software Foundation, Inc. ++// Copyright (C) 2012-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2457625,7 +2470206,7 @@ index 0000000..f864365 + .section .note.GNU-stack,"",@progbits diff --git a/gold/testsuite/dyn_weak_ref.sh b/gold/testsuite/dyn_weak_ref.sh new file mode 100755 -index 0000000..b52efac +index 0000000..e2d200d --- /dev/null +++ b/gold/testsuite/dyn_weak_ref.sh @@ -0,0 +1,42 @@ @@ -2457634,7 +2470215,7 @@ index 0000000..b52efac +# dyn_weak_ref.sh -- test weak reference remains weak in output even if +# gold sees a dynamic weak reference before a static one. + -+# Copyright 2010 Free Software Foundation, Inc. ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# Written by Doug Kwan . + +# This file is part of gold. @@ -2457673,14 +2470254,14 @@ index 0000000..b52efac +exit 0 diff --git a/gold/testsuite/dyn_weak_ref_1.c b/gold/testsuite/dyn_weak_ref_1.c new file mode 100644 -index 0000000..fdd78dd +index 0000000..b32f3a8 --- /dev/null +++ b/gold/testsuite/dyn_weak_ref_1.c @@ -0,0 +1,39 @@ +// dyn_weak_ref_1.c -- test that a weak ref remains weak in output when +// there is a DSO with the same weak ref. + -+// Copyright 2010 Free Software Foundation, Inc. ++// Copyright (C) 2010-2014 Free Software Foundation, Inc. +// Written by Doug Kwan . + +// This file is part of gold. @@ -2457718,14 +2470299,14 @@ index 0000000..fdd78dd +} diff --git a/gold/testsuite/dyn_weak_ref_2.c b/gold/testsuite/dyn_weak_ref_2.c new file mode 100644 -index 0000000..8a087a1 +index 0000000..dfd4be1 --- /dev/null +++ b/gold/testsuite/dyn_weak_ref_2.c @@ -0,0 +1,32 @@ +// dyn_weak_ref_1.c -- test that a weak ref remains weak in output when +// there is a DSO with the same weak ref. + -+// Copyright 2010 Free Software Foundation, Inc. ++// Copyright (C) 2010-2014 Free Software Foundation, Inc. +// Written by Doug Kwan . + +// This file is part of gold. @@ -2457756,7 +2470337,7 @@ index 0000000..8a087a1 +void* ptr2 = weak_ref; diff --git a/gold/testsuite/dynamic_list.sh b/gold/testsuite/dynamic_list.sh new file mode 100755 -index 0000000..dfd9f0f +index 0000000..e2ef9fd --- /dev/null +++ b/gold/testsuite/dynamic_list.sh @@ -0,0 +1,50 @@ @@ -2457764,7 +2470345,7 @@ index 0000000..dfd9f0f + +# dynamic_list.sh -- test --dynamic-list and --dynamic-list-* + -+# Copyright 2008 Free Software Foundation, Inc. ++# Copyright (C) 2008-2014 Free Software Foundation, Inc. +# Written by Ian Lance Taylor . + +# This file is part of gold. @@ -2457827,15 +2470408,391 @@ index 0000000..6457173 + local; + extern; +}; +diff --git a/gold/testsuite/dynamic_list_2.cc b/gold/testsuite/dynamic_list_2.cc +new file mode 100644 +index 0000000..5913312 +--- /dev/null ++++ b/gold/testsuite/dynamic_list_2.cc +@@ -0,0 +1,40 @@ ++// dynamic_list_test_2.cc -- Test --dynamic-list with shared libraries. ++ ++// Copyright (C) 2014 Free Software Foundation, Inc. ++// Written by Cary Coutant . ++ ++// This file is part of gold. ++ ++// This program is free software; you can redistribute it and/or modify ++// it under the terms of the GNU General Public License as published by ++// the Free Software Foundation; either version 3 of the License, or ++// (at your option) any later version. ++ ++// This program is distributed in the hope that it will be useful, ++// but WITHOUT ANY WARRANTY; without even the implied warranty of ++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++// GNU General Public License for more details. ++ ++// You should have received a copy of the GNU General Public License ++// along with this program; if not, write to the Free Software ++// Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ++// MA 02110-1301, USA. ++ ++// The goal of this program is to verify that the --dynamic-list option ++// allows overrides for symbols listed in the file, and does symbolic ++// binding for symbols not listed. ++ ++#include ++ ++extern const char* test_foo(); ++extern const char* test_bar(); ++ ++int ++main(void) ++{ ++ if (strcmp(test_foo(), "override") != 0) ++ return 1; ++ if (strcmp(test_bar(), "original") != 0) ++ return 2; ++ return 0; ++} +diff --git a/gold/testsuite/dynamic_list_2.t b/gold/testsuite/dynamic_list_2.t +new file mode 100644 +index 0000000..eef848d +--- /dev/null ++++ b/gold/testsuite/dynamic_list_2.t +@@ -0,0 +1,27 @@ ++/* dynamic_list_2.t -- script file for building dynamic_list_lib2.so. ++ ++ Copyright (C) 2014 Free Software Foundation, Inc. ++ Written by Cary Coutant . ++ ++ This file is part of gold. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, write to the Free Software ++ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ++ MA 02110-1301, USA. */ ++ ++{ ++ extern "C" { ++ "foo"; ++ }; ++}; +diff --git a/gold/testsuite/dynamic_list_lib1.cc b/gold/testsuite/dynamic_list_lib1.cc +new file mode 100644 +index 0000000..afc36ca +--- /dev/null ++++ b/gold/testsuite/dynamic_list_lib1.cc +@@ -0,0 +1,37 @@ ++// dynamic_list_test_lib1.cc -- Test --dynamic-list with shared libraries. ++ ++// Copyright (C) 2014 Free Software Foundation, Inc. ++// Written by Cary Coutant . ++ ++// This file is part of gold. ++ ++// This program is free software; you can redistribute it and/or modify ++// it under the terms of the GNU General Public License as published by ++// the Free Software Foundation; either version 3 of the License, or ++// (at your option) any later version. ++ ++// This program is distributed in the hope that it will be useful, ++// but WITHOUT ANY WARRANTY; without even the implied warranty of ++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++// GNU General Public License for more details. ++ ++// You should have received a copy of the GNU General Public License ++// along with this program; if not, write to the Free Software ++// Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ++// MA 02110-1301, USA. ++ ++// The goal of this program is to verify that the --dynamic-list option ++// allows overrides for symbols listed in the file, and does symbolic ++// binding for symbols not listed. ++ ++extern "C" const char* ++foo() ++{ ++ return "override"; ++} ++ ++extern "C" const char* ++bar() ++{ ++ return "override"; ++} +diff --git a/gold/testsuite/dynamic_list_lib2.cc b/gold/testsuite/dynamic_list_lib2.cc +new file mode 100644 +index 0000000..8ed5be5 +--- /dev/null ++++ b/gold/testsuite/dynamic_list_lib2.cc +@@ -0,0 +1,49 @@ ++// dynamic_list_test_lib2.cc -- Test --dynamic-list with shared libraries. ++ ++// Copyright (C) 2014 Free Software Foundation, Inc. ++// Written by Cary Coutant . ++ ++// This file is part of gold. ++ ++// This program is free software; you can redistribute it and/or modify ++// it under the terms of the GNU General Public License as published by ++// the Free Software Foundation; either version 3 of the License, or ++// (at your option) any later version. ++ ++// This program is distributed in the hope that it will be useful, ++// but WITHOUT ANY WARRANTY; without even the implied warranty of ++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++// GNU General Public License for more details. ++ ++// You should have received a copy of the GNU General Public License ++// along with this program; if not, write to the Free Software ++// Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ++// MA 02110-1301, USA. ++ ++// The goal of this program is to verify that the --dynamic-list option ++// allows overrides for symbols listed in the file, and does symbolic ++// binding for symbols not listed. ++ ++extern "C" const char* ++foo() ++{ ++ return "original"; ++} ++ ++const char* ++test_foo() ++{ ++ return foo(); ++} ++ ++extern "C" const char* ++bar() ++{ ++ return "original"; ++} ++ ++const char* ++test_bar() ++{ ++ return bar(); ++} +diff --git a/gold/testsuite/ehdr_start_def.cc b/gold/testsuite/ehdr_start_def.cc +new file mode 100644 +index 0000000..f102a78 +--- /dev/null ++++ b/gold/testsuite/ehdr_start_def.cc +@@ -0,0 +1,26 @@ ++// ehdr_start_def.cc -- test for __ehdr_start linker-defined symbol. ++ ++// Copyright (C) 2014 Free Software Foundation, Inc. ++// Written by Cary Coutant . ++ ++// This file is part of gold. ++ ++// This program is free software; you can redistribute it and/or modify ++// it under the terms of the GNU General Public License as published by ++// the Free Software Foundation; either version 3 of the License, or ++// (at your option) any later version. ++ ++// This program is distributed in the hope that it will be useful, ++// but WITHOUT ANY WARRANTY; without even the implied warranty of ++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++// GNU General Public License for more details. ++ ++// You should have received a copy of the GNU General Public License ++// along with this program; if not, write to the Free Software ++// Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ++// MA 02110-1301, USA. ++ ++// We provide a user-defined __ehdr_start, to make sure that the ++// linker does not override this with the linker-defined symbol. ++ ++char __ehdr_start[] = { 'a', 'b', 'c', 'd' }; +diff --git a/gold/testsuite/ehdr_start_test.cc b/gold/testsuite/ehdr_start_test.cc +new file mode 100644 +index 0000000..a119b5e +--- /dev/null ++++ b/gold/testsuite/ehdr_start_test.cc +@@ -0,0 +1,67 @@ ++// ehdr_start_test.cc -- test for __ehdr_start linker-defined symbol. ++ ++// Copyright (C) 2014 Free Software Foundation, Inc. ++// Written by Cary Coutant . ++ ++// This file is part of gold. ++ ++// This program is free software; you can redistribute it and/or modify ++// it under the terms of the GNU General Public License as published by ++// the Free Software Foundation; either version 3 of the License, or ++// (at your option) any later version. ++ ++// This program is distributed in the hope that it will be useful, ++// but WITHOUT ANY WARRANTY; without even the implied warranty of ++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++// GNU General Public License for more details. ++ ++// You should have received a copy of the GNU General Public License ++// along with this program; if not, write to the Free Software ++// Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ++// MA 02110-1301, USA. ++ ++// The goal of this program is to produce as many different types of ++// relocations as we can in a stand-alone program that does not use ++// TLS. This program is compiled without optimization. ++ ++#include "config.h" ++ ++#include ++#include ++ ++#include "elfcpp.h" ++ ++#ifdef EHDR_START_WEAK ++#define WEAK_ATTR __attribute__ ((weak)) ++#else ++#define WEAK_ATTR ++#endif ++ ++extern char __ehdr_start[] WEAK_ATTR; ++ ++int ++main() { ++ printf("&__ehdr_start = %p\n", &__ehdr_start); ++ ++#ifdef EHDR_START_UNDEF ++ assert(&__ehdr_start == 0); ++#else ++ assert(&__ehdr_start != NULL); ++ ++ printf("ELF header: \\x%02x%c%c%c\n", __ehdr_start[0], __ehdr_start[1], ++ __ehdr_start[2], __ehdr_start[3]); ++#ifdef EHDR_START_USER_DEF ++ assert(__ehdr_start[0] == 'a' ++ && __ehdr_start[1] == 'b' ++ && __ehdr_start[2] == 'c' ++ && __ehdr_start[3] == 'd'); ++#else ++ assert(__ehdr_start[elfcpp::EI_MAG0] == elfcpp::ELFMAG0 ++ && __ehdr_start[elfcpp::EI_MAG1] == elfcpp::ELFMAG1 ++ && __ehdr_start[elfcpp::EI_MAG2] == elfcpp::ELFMAG2 ++ && __ehdr_start[elfcpp::EI_MAG3] == elfcpp::ELFMAG3); ++#endif ++#endif ++ ++ return 0; ++} +diff --git a/gold/testsuite/ehdr_start_test.t b/gold/testsuite/ehdr_start_test.t +new file mode 100644 +index 0000000..50daa64 +--- /dev/null ++++ b/gold/testsuite/ehdr_start_test.t +@@ -0,0 +1,42 @@ ++/* ehdr_start_test.t -- __ehdr_start test for gold ++ ++ Copyright (C) 2008-2014 Free Software Foundation, Inc. ++ Written by Ian Lance Taylor . ++ ++ This file is part of gold. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, write to the Free Software ++ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ++ MA 02110-1301, USA. */ ++ ++/* With luck this will work on all platforms. */ ++ ++SECTIONS ++{ ++ /* Set the text segment to start on a non-page boundary. */ ++ . = 0x10000040; ++ ++ .text : { *(.text) } ++ . += 0x100000; ++ . = ALIGN(0x100); ++ ++ .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } ++ .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } ++ .data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) ++ *(.data.rel.ro* .gnu.linkonce.d.rel.ro.*) } ++ .dynamic : { *(.dynamic) } ++ .got : { *(.got) } ++ .got.plt : { *(.got.plt) } ++ .data : { *(.data .data.* .gnu.linkonce.d.*) } ++} +diff --git a/gold/testsuite/ehdr_start_test_4.sh b/gold/testsuite/ehdr_start_test_4.sh +new file mode 100755 +index 0000000..5e3d20f +--- /dev/null ++++ b/gold/testsuite/ehdr_start_test_4.sh +@@ -0,0 +1,40 @@ ++#!/bin/sh ++ ++# ehdr_start_test_4.sh -- test that __ehdr_start symbol is undefined. ++ ++# Copyright (C) 2014 Free Software Foundation, Inc. ++# Written by Cary Coutant . ++ ++# This file is part of gold. ++ ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 3 of the License, or ++# (at your option) any later version. ++ ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++ ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ++# MA 02110-1301, USA. ++ ++check() ++{ ++ if ! grep -q "$2" "$1" ++ then ++ echo "Did not find expected symbol in $1:" ++ echo " $2" ++ echo "" ++ echo "Actual output below:" ++ cat "$1" ++ exit 1 ++ fi ++} ++ ++check ehdr_start_test_4.syms "U __ehdr_start" ++ ++exit 0 diff --git a/gold/testsuite/exception_test.h b/gold/testsuite/exception_test.h new file mode 100644 -index 0000000..0dcd8f2 +index 0000000..f7825bf --- /dev/null +++ b/gold/testsuite/exception_test.h @@ -0,0 +1,27 @@ +// exception_test.h -- exception test case for gold, header file -*- C++ -*- + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2457862,13 +2470819,13 @@ index 0000000..0dcd8f2 +extern void f1(); diff --git a/gold/testsuite/exception_test_1.cc b/gold/testsuite/exception_test_1.cc new file mode 100644 -index 0000000..56ae143 +index 0000000..7972f01 --- /dev/null +++ b/gold/testsuite/exception_test_1.cc @@ -0,0 +1,52 @@ +// exception_test_1.cc -- test exception handling for gold, file 1 of 2 + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2457920,13 +2470877,13 @@ index 0000000..56ae143 +} diff --git a/gold/testsuite/exception_test_2.cc b/gold/testsuite/exception_test_2.cc new file mode 100644 -index 0000000..1098bd1 +index 0000000..1267cf6 --- /dev/null +++ b/gold/testsuite/exception_test_2.cc @@ -0,0 +1,31 @@ +// exception_test_1.cc -- test exception handling for gold, file 1 of 2 + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2457957,13 +2470914,13 @@ index 0000000..1098bd1 +} diff --git a/gold/testsuite/exception_test_main.cc b/gold/testsuite/exception_test_main.cc new file mode 100644 -index 0000000..09a018d +index 0000000..a4c644b --- /dev/null +++ b/gold/testsuite/exception_test_main.cc @@ -0,0 +1,35 @@ +// exception_test_main.cc -- an exception test case for gold, main function + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2458018,7 +2470975,7 @@ index 0000000..85441a0 + diff --git a/gold/testsuite/exclude_libs_test.sh b/gold/testsuite/exclude_libs_test.sh new file mode 100755 -index 0000000..65ce03b +index 0000000..09f50b9 --- /dev/null +++ b/gold/testsuite/exclude_libs_test.sh @@ -0,0 +1,63 @@ @@ -2458026,7 +2470983,7 @@ index 0000000..65ce03b + +# exclude_libs_test.sh -- test that library symbols are not exported. + -+# Copyright 2009 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# Written by Doug Kwan + +# This file is part of gold. @@ -2458185,13 +2471142,13 @@ index 0000000..b4e2635 +} diff --git a/gold/testsuite/final_layout.cc b/gold/testsuite/final_layout.cc new file mode 100644 -index 0000000..f533885 +index 0000000..71065c7 --- /dev/null +++ b/gold/testsuite/final_layout.cc @@ -0,0 +1,48 @@ +// final_layout.cc -- a test case for gold + -+// Copyright 2010 Free Software Foundation, Inc. ++// Copyright (C) 2010-2014 Free Software Foundation, Inc. +// Written by Sriraman Tallam . + +// This file is part of gold. @@ -2458239,7 +2471196,7 @@ index 0000000..f533885 +} diff --git a/gold/testsuite/final_layout.sh b/gold/testsuite/final_layout.sh new file mode 100755 -index 0000000..d9d86ee +index 0000000..c93e265 --- /dev/null +++ b/gold/testsuite/final_layout.sh @@ -0,0 +1,61 @@ @@ -2458247,7 +2471204,7 @@ index 0000000..d9d86ee + +# final_layout.sh -- test --final-layout + -+# Copyright 2010, 2011 Free Software Foundation, Inc. ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# Written by Sriraman Tallam . + +# This file is part of gold. @@ -2458306,7 +2471263,7 @@ index 0000000..d9d86ee +check final_layout.stdout "global_vara" "global_varc" diff --git a/gold/testsuite/gc_comdat_test.sh b/gold/testsuite/gc_comdat_test.sh new file mode 100755 -index 0000000..baff98d +index 0000000..1a38f21 --- /dev/null +++ b/gold/testsuite/gc_comdat_test.sh @@ -0,0 +1,42 @@ @@ -2458314,7 +2471271,7 @@ index 0000000..baff98d + +# gc_comdat_test.sh -- test --gc-sections + -+# Copyright 2009 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# Written by Sriraman Tallam . + +# This file is part of gold. @@ -2458354,13 +2471311,13 @@ index 0000000..baff98d +check gc_comdat_test.stdout "int GetMax(int, int)" diff --git a/gold/testsuite/gc_comdat_test_1.cc b/gold/testsuite/gc_comdat_test_1.cc new file mode 100644 -index 0000000..0b4b286 +index 0000000..8db55e9 --- /dev/null +++ b/gold/testsuite/gc_comdat_test_1.cc @@ -0,0 +1,42 @@ +// gc_comdat_test_1.cc -- a test case for gold + -+// Copyright 2009 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Sriraman Tallam . + +// This file is part of gold. @@ -2458402,13 +2471359,13 @@ index 0000000..0b4b286 +} diff --git a/gold/testsuite/gc_comdat_test_2.cc b/gold/testsuite/gc_comdat_test_2.cc new file mode 100644 -index 0000000..5841bdf +index 0000000..1d68be2 --- /dev/null +++ b/gold/testsuite/gc_comdat_test_2.cc @@ -0,0 +1,35 @@ +// gc_comdat_test_2.cc -- a test case for gold + -+// Copyright 2009 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Sriraman Tallam . + +// This file is part of gold. @@ -2458441,15 +2471398,131 @@ index 0000000..5841bdf +{ + return GetMax (10,11); +} +diff --git a/gold/testsuite/gc_dynamic_list_test.c b/gold/testsuite/gc_dynamic_list_test.c +new file mode 100644 +index 0000000..fb9a92e +--- /dev/null ++++ b/gold/testsuite/gc_dynamic_list_test.c +@@ -0,0 +1,34 @@ ++// gc_dynamic_list_test.cc -- Check that --gc-sections honors --dynamic-list. ++ ++// Copyright (C) 2014 Free Software Foundation, Inc. ++// Written by Cary Coutant . ++ ++// This file is part of gold. ++ ++// This program is free software; you can redistribute it and/or modify ++// it under the terms of the GNU General Public License as published by ++// the Free Software Foundation; either version 3 of the License, or ++// (at your option) any later version. ++ ++// This program is distributed in the hope that it will be useful, ++// but WITHOUT ANY WARRANTY; without even the implied warranty of ++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++// GNU General Public License for more details. ++ ++// You should have received a copy of the GNU General Public License ++// along with this program; if not, write to the Free Software ++// Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ++// MA 02110-1301, USA. ++ ++// The goal of this program is to verify that the symbol "keep" is not ++// garbage-collected when it is named in a --dynamic-list script. ++ ++extern void keep(void); ++ ++void ++keep(void) ++{} ++ ++int ++main(void) ++{ return 0; } +diff --git a/gold/testsuite/gc_dynamic_list_test.sh b/gold/testsuite/gc_dynamic_list_test.sh +new file mode 100755 +index 0000000..a586929 +--- /dev/null ++++ b/gold/testsuite/gc_dynamic_list_test.sh +@@ -0,0 +1,39 @@ ++#!/bin/sh ++ ++# gc_comdat_test.sh -- test --gc-sections ++ ++# Copyright (C) 2014 Free Software Foundation, Inc. ++# Written by Cary Coutant . ++ ++# This file is part of gold. ++ ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 3 of the License, or ++# (at your option) any later version. ++ ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++ ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ++# MA 02110-1301, USA. ++ ++# The goal of this program is to verify if comdat's and garbage ++# collection work together. Files gc_comdat_test_1.cc and ++# gc_comdat_test_2.cc are used in this test. This program checks ++# if the kept comdat section is garbage collected. ++ ++check() ++{ ++ if ! grep -q "$2" "$1" ++ then ++ echo "Garbage collection should not have collected '$2'" ++ exit 1 ++ fi ++} ++ ++check gc_dynamic_list_test.stdout "keep" +diff --git a/gold/testsuite/gc_dynamic_list_test.t b/gold/testsuite/gc_dynamic_list_test.t +new file mode 100644 +index 0000000..c0b818e +--- /dev/null ++++ b/gold/testsuite/gc_dynamic_list_test.t +@@ -0,0 +1,25 @@ ++/* gc_dynamic_list_test.t -- script file for gc_dynamic_list_test.cc ++ ++ Copyright (C) 2014 Free Software Foundation, Inc. ++ Written by Cary Coutant . ++ ++ This file is part of gold. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, write to the Free Software ++ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ++ MA 02110-1301, USA. */ ++ ++{ ++ keep; ++}; diff --git a/gold/testsuite/gc_orphan_section_test.cc b/gold/testsuite/gc_orphan_section_test.cc new file mode 100644 -index 0000000..3443f8d +index 0000000..bcf06e4 --- /dev/null +++ b/gold/testsuite/gc_orphan_section_test.cc @@ -0,0 +1,36 @@ +// gc_orphan_section_test.cc -- a test case for gold + -+// Copyright 2010 Free Software Foundation, Inc. ++// Copyright (C) 2010-2014 Free Software Foundation, Inc. +// Written by Sriraman Tallam . + +// This file is part of gold. @@ -2458485,7 +2471558,7 @@ index 0000000..3443f8d + diff --git a/gold/testsuite/gc_orphan_section_test.sh b/gold/testsuite/gc_orphan_section_test.sh new file mode 100755 -index 0000000..6ce524d +index 0000000..de2d2fe --- /dev/null +++ b/gold/testsuite/gc_orphan_section_test.sh @@ -0,0 +1,46 @@ @@ -2458493,7 +2471566,7 @@ index 0000000..6ce524d + +# gc_orphan_section_test.sh -- test --gc-sections + -+# Copyright 2010 Free Software Foundation, Inc. ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# Written by Sriraman Tallam . + +# This file is part of gold. @@ -2458537,13 +2471610,13 @@ index 0000000..6ce524d +check gc_orphan_section_test.stdout diff --git a/gold/testsuite/gc_tls_test.cc b/gold/testsuite/gc_tls_test.cc new file mode 100644 -index 0000000..1b10d98 +index 0000000..2d29d68 --- /dev/null +++ b/gold/testsuite/gc_tls_test.cc @@ -0,0 +1,32 @@ +// gc_tls_test.cc -- a test case for gold + -+// Copyright 2009 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Sriraman Tallam . + +// This file is part of gold. @@ -2458575,7 +2471648,7 @@ index 0000000..1b10d98 + diff --git a/gold/testsuite/gc_tls_test.sh b/gold/testsuite/gc_tls_test.sh new file mode 100755 -index 0000000..c4635c9 +index 0000000..7b6485e --- /dev/null +++ b/gold/testsuite/gc_tls_test.sh @@ -0,0 +1,39 @@ @@ -2458583,7 +2471656,7 @@ index 0000000..c4635c9 + +# gc_tls_test.sh -- test -- gc + tls + -+# Copyright 2009 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# Written by Sriraman Tallam . + +# This file is part of gold. @@ -2458620,13 +2471693,13 @@ index 0000000..c4635c9 +check gc_tls_test.stdout "number" diff --git a/gold/testsuite/gdb_index_test.cc b/gold/testsuite/gdb_index_test.cc new file mode 100644 -index 0000000..d5ac2f1 +index 0000000..6a562c3 --- /dev/null +++ b/gold/testsuite/gdb_index_test.cc @@ -0,0 +1,149 @@ +// gdb_index_test.cc -- a test case for the --gdb-index option. + -+// Copyright 2012 Free Software Foundation, Inc. ++// Copyright (C) 2012-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2458775,7 +2471848,7 @@ index 0000000..d5ac2f1 +} diff --git a/gold/testsuite/gdb_index_test_1.sh b/gold/testsuite/gdb_index_test_1.sh new file mode 100755 -index 0000000..f04c8a7 +index 0000000..5fae550 --- /dev/null +++ b/gold/testsuite/gdb_index_test_1.sh @@ -0,0 +1,25 @@ @@ -2458783,7 +2471856,7 @@ index 0000000..f04c8a7 + +# gdb_index_test_1.sh -- a test case for the --gdb-index option. + -+# Copyright 2012 Free Software Foundation, Inc. ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# Written by Cary Coutant . + +# This file is part of gold. @@ -2458806,7 +2471879,7 @@ index 0000000..f04c8a7 +exec ${srcdir}/gdb_index_test_comm.sh gdb_index_test_1.stdout diff --git a/gold/testsuite/gdb_index_test_2.sh b/gold/testsuite/gdb_index_test_2.sh new file mode 100755 -index 0000000..e31aa42 +index 0000000..a1d4d83 --- /dev/null +++ b/gold/testsuite/gdb_index_test_2.sh @@ -0,0 +1,25 @@ @@ -2458814,7 +2471887,7 @@ index 0000000..e31aa42 + +# gdb_index_test_2.sh -- a test case for the --gdb-index option. + -+# Copyright 2012 Free Software Foundation, Inc. ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# Written by Cary Coutant . + +# This file is part of gold. @@ -2458837,13 +2471910,13 @@ index 0000000..e31aa42 +exec ${srcdir}/gdb_index_test_comm.sh gdb_index_test_2.stdout diff --git a/gold/testsuite/gdb_index_test_3.c b/gold/testsuite/gdb_index_test_3.c new file mode 100644 -index 0000000..df49261 +index 0000000..683510c --- /dev/null +++ b/gold/testsuite/gdb_index_test_3.c @@ -0,0 +1,39 @@ +// gdb_index_test.c -- a test case for the --gdb-index option. + -+// Copyright 2012 Free Software Foundation, Inc. ++// Copyright (C) 2012-2014 Free Software Foundation, Inc. + +// This file is part of gold. + @@ -2458882,7 +2471955,7 @@ index 0000000..df49261 +} diff --git a/gold/testsuite/gdb_index_test_3.sh b/gold/testsuite/gdb_index_test_3.sh new file mode 100755 -index 0000000..bd1500b +index 0000000..7b4948d --- /dev/null +++ b/gold/testsuite/gdb_index_test_3.sh @@ -0,0 +1,49 @@ @@ -2458890,7 +2471963,7 @@ index 0000000..bd1500b + +# gdb_index_test_3.sh -- a test case for the --gdb-index option. + -+# Copyright 2012 Free Software Foundation, Inc. ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# Written by Cary Coutant . + +# This file is part of gold. @@ -2458925,7 +2471998,7 @@ index 0000000..bd1500b + +STDOUT=gdb_index_test_3.stdout + -+check $STDOUT "^Version [45]" ++check $STDOUT "^Version [4-7]" + +# Look for the symbols we know should be in the symbol table. + @@ -2458937,7 +2472010,7 @@ index 0000000..bd1500b +exit 0 diff --git a/gold/testsuite/gdb_index_test_4.sh b/gold/testsuite/gdb_index_test_4.sh new file mode 100755 -index 0000000..44c8a9a +index 0000000..3d5d66b --- /dev/null +++ b/gold/testsuite/gdb_index_test_4.sh @@ -0,0 +1,25 @@ @@ -2458945,7 +2472018,7 @@ index 0000000..44c8a9a + +# gdb_index_test_4.sh -- a test case for the --gdb-index option. + -+# Copyright 2012 Free Software Foundation, Inc. ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# Written by Cary Coutant . + +# This file is part of gold. @@ -2458968,7 +2472041,7 @@ index 0000000..44c8a9a +exec ${srcdir}/gdb_index_test_comm.sh gdb_index_test_4.stdout diff --git a/gold/testsuite/gdb_index_test_comm.sh b/gold/testsuite/gdb_index_test_comm.sh new file mode 100755 -index 0000000..4ab07b3 +index 0000000..e888825 --- /dev/null +++ b/gold/testsuite/gdb_index_test_comm.sh @@ -0,0 +1,85 @@ @@ -2458976,7 +2472049,7 @@ index 0000000..4ab07b3 + +# gdb_index_test_comm.sh -- common code for --gdb-index tests. + -+# Copyright 2012 Free Software Foundation, Inc. ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# Written by Cary Coutant . + +# This file is part of gold. @@ -2459011,7 +2472084,7 @@ index 0000000..4ab07b3 + +STDOUT="$1" + -+check $STDOUT "^Version [45]" ++check $STDOUT "^Version [4-7]" + +# Look for the symbols we know should be in the symbol table. + @@ -2459059,7 +2472132,7 @@ index 0000000..4ab07b3 +exit 0 diff --git a/gold/testsuite/hidden_test.sh b/gold/testsuite/hidden_test.sh new file mode 100755 -index 0000000..df51b37 +index 0000000..39ebbf6 --- /dev/null +++ b/gold/testsuite/hidden_test.sh @@ -0,0 +1,66 @@ @@ -2459067,7 +2472140,7 @@ index 0000000..df51b37 + +# hidden_test.sh -- a test case for hidden and internal symbols. + -+# Copyright 2009 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# Written by Cary Coutant . + +# This file is part of gold. @@ -2459131,13 +2472204,13 @@ index 0000000..df51b37 +exit 0 diff --git a/gold/testsuite/hidden_test_1.c b/gold/testsuite/hidden_test_1.c new file mode 100644 -index 0000000..f685cab +index 0000000..e9c96e6 --- /dev/null +++ b/gold/testsuite/hidden_test_1.c @@ -0,0 +1,41 @@ +/* hidden_test_1.c -- test hidden and internal symbols + -+ Copyright 2009 Free Software Foundation, Inc. ++ Copyright (C) 2009-2014 Free Software Foundation, Inc. + Written by Cary Coutant + + This file is part of gold. @@ -2459178,13 +2472251,13 @@ index 0000000..f685cab +} diff --git a/gold/testsuite/hidden_test_main.c b/gold/testsuite/hidden_test_main.c new file mode 100644 -index 0000000..c54864d +index 0000000..60b8893 --- /dev/null +++ b/gold/testsuite/hidden_test_main.c @@ -0,0 +1,61 @@ +/* hidden_test_main.c -- test hidden and internal symbols + -+ Copyright 2009 Free Software Foundation, Inc. ++ Copyright (C) 2009-2014 Free Software Foundation, Inc. + Written by Cary Coutant + + This file is part of gold. @@ -2459245,13 +2472318,13 @@ index 0000000..c54864d +} diff --git a/gold/testsuite/icf_keep_unique_test.cc b/gold/testsuite/icf_keep_unique_test.cc new file mode 100644 -index 0000000..37f6437 +index 0000000..75a8385 --- /dev/null +++ b/gold/testsuite/icf_keep_unique_test.cc @@ -0,0 +1,39 @@ +// icf_keep_unique_test.cc -- a test case for gold + -+// Copyright 2009 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Sriraman Tallam . + +// This file is part of gold. @@ -2459290,7 +2472363,7 @@ index 0000000..37f6437 +} diff --git a/gold/testsuite/icf_keep_unique_test.sh b/gold/testsuite/icf_keep_unique_test.sh new file mode 100755 -index 0000000..c267373 +index 0000000..d481d01 --- /dev/null +++ b/gold/testsuite/icf_keep_unique_test.sh @@ -0,0 +1,39 @@ @@ -2459298,7 +2472371,7 @@ index 0000000..c267373 + +# icf_keep_unique_test.sh -- test --icf --keep-unique + -+# Copyright 2009 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# Written by Sriraman Tallam . + +# This file is part of gold. @@ -2459335,13 +2472408,13 @@ index 0000000..c267373 +check icf_keep_unique_test.stdout "kept_func" "unique_func" diff --git a/gold/testsuite/icf_preemptible_functions_test.cc b/gold/testsuite/icf_preemptible_functions_test.cc new file mode 100644 -index 0000000..35a96bc +index 0000000..dc588a3 --- /dev/null +++ b/gold/testsuite/icf_preemptible_functions_test.cc @@ -0,0 +1,47 @@ +// icf_preemptible_functions_test.cc -- a test case for gold + -+// Copyright 2010 Free Software Foundation, Inc. ++// Copyright (C) 2010-2014 Free Software Foundation, Inc. +// Written by Sriraman Tallam . + +// This file is part of gold. @@ -2459388,7 +2472461,7 @@ index 0000000..35a96bc +} diff --git a/gold/testsuite/icf_preemptible_functions_test.sh b/gold/testsuite/icf_preemptible_functions_test.sh new file mode 100755 -index 0000000..dd90d7f +index 0000000..c2a9f1c --- /dev/null +++ b/gold/testsuite/icf_preemptible_functions_test.sh @@ -0,0 +1,37 @@ @@ -2459396,7 +2472469,7 @@ index 0000000..dd90d7f + +# icf_preemptible_functions_test.sh -- test --icf=all + -+# Copyright 2010 Free Software Foundation, Inc. ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# Written by Sriraman Tallam . + +# This file is part of gold. @@ -2459431,13 +2472504,13 @@ index 0000000..dd90d7f +check icf_preemptible_functions_test.stdout "_Z3foov" "_Z3barv" diff --git a/gold/testsuite/icf_safe_so_test.cc b/gold/testsuite/icf_safe_so_test.cc new file mode 100644 -index 0000000..0f50ad6 +index 0000000..bca852f --- /dev/null +++ b/gold/testsuite/icf_safe_so_test.cc @@ -0,0 +1,74 @@ +// icf_safe_so_test.cc -- a test case for gold + -+// Copyright 2010 Free Software Foundation, Inc. ++// Copyright (C) 2010-2014 Free Software Foundation, Inc. +// Written by Sriraman Tallam . + +// This file is part of gold. @@ -2459511,7 +2472584,7 @@ index 0000000..0f50ad6 + diff --git a/gold/testsuite/icf_safe_so_test.sh b/gold/testsuite/icf_safe_so_test.sh new file mode 100755 -index 0000000..813248e +index 0000000..804334d --- /dev/null +++ b/gold/testsuite/icf_safe_so_test.sh @@ -0,0 +1,102 @@ @@ -2459519,7 +2472592,7 @@ index 0000000..813248e + +# icf_safe_so_test.sh -- test --icf=safe + -+# Copyright 2010 Free Software Foundation, Inc. ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# Written by Sriraman Tallam . + +# This file is part of gold. @@ -2459619,13 +2472692,13 @@ index 0000000..813248e +check_nofold icf_safe_so_test_1.stdout "foo_glob" "bar_glob" diff --git a/gold/testsuite/icf_safe_test.cc b/gold/testsuite/icf_safe_test.cc new file mode 100644 -index 0000000..87294dc +index 0000000..46bced1 --- /dev/null +++ b/gold/testsuite/icf_safe_test.cc @@ -0,0 +1,63 @@ +// icf_safe_test.cc -- a test case for gold + -+// Copyright 2009 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Sriraman Tallam . + +// This file is part of gold. @@ -2459688,7 +2472761,7 @@ index 0000000..87294dc +} diff --git a/gold/testsuite/icf_safe_test.sh b/gold/testsuite/icf_safe_test.sh new file mode 100755 -index 0000000..fe224f6 +index 0000000..e18468c --- /dev/null +++ b/gold/testsuite/icf_safe_test.sh @@ -0,0 +1,73 @@ @@ -2459696,7 +2472769,7 @@ index 0000000..fe224f6 + +# icf_safe_test.sh -- test --icf=safe + -+# Copyright 2009 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# Written by Sriraman Tallam . + +# This file is part of gold. @@ -2459767,7 +2472840,7 @@ index 0000000..fe224f6 +check_nofold icf_safe_test_1.stdout "kept_func_3" "kept_func_2" diff --git a/gold/testsuite/icf_sht_rel_addend_test.sh b/gold/testsuite/icf_sht_rel_addend_test.sh new file mode 100755 -index 0000000..9077e25 +index 0000000..64b69d3 --- /dev/null +++ b/gold/testsuite/icf_sht_rel_addend_test.sh @@ -0,0 +1,37 @@ @@ -2459775,7 +2472848,7 @@ index 0000000..9077e25 + +# icf_sht_rel_addend_test.sh -- test --icf=all + -+# Copyright 2010 Free Software Foundation, Inc. ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# Written by Sriraman Tallam . + +# This file is part of gold. @@ -2459810,13 +2472883,13 @@ index 0000000..9077e25 +check icf_sht_rel_addend_test.stdout "name1" "name2" diff --git a/gold/testsuite/icf_sht_rel_addend_test_1.cc b/gold/testsuite/icf_sht_rel_addend_test_1.cc new file mode 100644 -index 0000000..ecc2a1b +index 0000000..8f20a71 --- /dev/null +++ b/gold/testsuite/icf_sht_rel_addend_test_1.cc @@ -0,0 +1,44 @@ +// icf_sht_rel_addend_test_1.cc -- a test case for gold + -+// Copyright 2010 Free Software Foundation, Inc. ++// Copyright (C) 2010-2014 Free Software Foundation, Inc. +// Written by Sriraman Tallam . + +// This file is part of gold. @@ -2459860,13 +2472933,13 @@ index 0000000..ecc2a1b +} diff --git a/gold/testsuite/icf_sht_rel_addend_test_2.cc b/gold/testsuite/icf_sht_rel_addend_test_2.cc new file mode 100644 -index 0000000..d85e3b4 +index 0000000..dfc2bd4 --- /dev/null +++ b/gold/testsuite/icf_sht_rel_addend_test_2.cc @@ -0,0 +1,39 @@ +// icf_sht_rel_addend_test_2.cc -- a test case for gold + -+// Copyright 2010 Free Software Foundation, Inc. ++// Copyright (C) 2010-2014 Free Software Foundation, Inc. +// Written by Sriraman Tallam . + +// This file is part of gold. @@ -2459905,13 +2472978,13 @@ index 0000000..d85e3b4 +} diff --git a/gold/testsuite/icf_string_merge_test.cc b/gold/testsuite/icf_string_merge_test.cc new file mode 100644 -index 0000000..b1e1191 +index 0000000..869ee80 --- /dev/null +++ b/gold/testsuite/icf_string_merge_test.cc @@ -0,0 +1,50 @@ +// icf_string_merge_test.cc -- a test case for gold + -+// Copyright 2010 Free Software Foundation, Inc. ++// Copyright (C) 2010-2014 Free Software Foundation, Inc. +// Written by Sriraman Tallam . + +// This file is part of gold. @@ -2459961,7 +2473034,7 @@ index 0000000..b1e1191 +} diff --git a/gold/testsuite/icf_string_merge_test.sh b/gold/testsuite/icf_string_merge_test.sh new file mode 100755 -index 0000000..e8d70de +index 0000000..a86728c --- /dev/null +++ b/gold/testsuite/icf_string_merge_test.sh @@ -0,0 +1,39 @@ @@ -2459969,7 +2473042,7 @@ index 0000000..e8d70de + +# icf_string_merge_test.sh -- test --icf=all + -+# Copyright 2010 Free Software Foundation, Inc. ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# Written by Sriraman Tallam . + +# This file is part of gold. @@ -2460006,13 +2473079,13 @@ index 0000000..e8d70de +check icf_string_merge_test.stdout "get2" "get3" diff --git a/gold/testsuite/icf_test.cc b/gold/testsuite/icf_test.cc new file mode 100644 -index 0000000..c7a5ea9 +index 0000000..41168ec --- /dev/null +++ b/gold/testsuite/icf_test.cc @@ -0,0 +1,51 @@ +// icf_test.cc -- a test case for gold + -+// Copyright 2009 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Sriraman Tallam . + +// This file is part of gold. @@ -2460063,7 +2473136,7 @@ index 0000000..c7a5ea9 +} diff --git a/gold/testsuite/icf_test.sh b/gold/testsuite/icf_test.sh new file mode 100755 -index 0000000..50abd90 +index 0000000..07af1a9 --- /dev/null +++ b/gold/testsuite/icf_test.sh @@ -0,0 +1,46 @@ @@ -2460071,7 +2473144,7 @@ index 0000000..50abd90 + +# icf_test.sh -- test --icf + -+# Copyright 2009 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# Written by Sriraman Tallam . + +# This file is part of gold. @@ -2460115,13 +2473188,13 @@ index 0000000..50abd90 +check icf_test.map "folded_func" "kept_func" diff --git a/gold/testsuite/icf_virtual_function_folding_test.cc b/gold/testsuite/icf_virtual_function_folding_test.cc new file mode 100644 -index 0000000..ba063c8 +index 0000000..ba144bf --- /dev/null +++ b/gold/testsuite/icf_virtual_function_folding_test.cc @@ -0,0 +1,71 @@ +// icf_virtual_function_folding_test.cc -- a test case for gold + -+// Copyright 2010 Free Software Foundation, Inc. ++// Copyright (C) 2010-2014 Free Software Foundation, Inc. +// Written by Sriraman Tallam . + +// This file is part of gold. @@ -2461144,13 +2474217,13 @@ index 0000000..e078b56 +} diff --git a/gold/testsuite/incr_comdat_test_1.cc b/gold/testsuite/incr_comdat_test_1.cc new file mode 100644 -index 0000000..7a232c2 +index 0000000..7a798bd --- /dev/null +++ b/gold/testsuite/incr_comdat_test_1.cc @@ -0,0 +1,68 @@ +// incr_comdat_test_1.cc -- test incremental update with comdat sections + -+// Copyright 2011 Free Software Foundation, Inc. ++// Copyright (C) 2011-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2461218,13 +2474291,13 @@ index 0000000..7a232c2 +} diff --git a/gold/testsuite/incr_comdat_test_2_v1.cc b/gold/testsuite/incr_comdat_test_2_v1.cc new file mode 100644 -index 0000000..f7d6a8c +index 0000000..02307ac --- /dev/null +++ b/gold/testsuite/incr_comdat_test_2_v1.cc @@ -0,0 +1,44 @@ +// incr_comdat_test_2.cc -- test incremental update with comdat sections + -+// Copyright 2011 Free Software Foundation, Inc. ++// Copyright (C) 2011-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2461268,13 +2474341,13 @@ index 0000000..f7d6a8c +} diff --git a/gold/testsuite/incr_comdat_test_2_v2.cc b/gold/testsuite/incr_comdat_test_2_v2.cc new file mode 100644 -index 0000000..fca7fda +index 0000000..936d7a1 --- /dev/null +++ b/gold/testsuite/incr_comdat_test_2_v2.cc @@ -0,0 +1,44 @@ +// incr_comdat_test_2.cc -- test incremental update with comdat sections + -+// Copyright 2011 Free Software Foundation, Inc. ++// Copyright (C) 2011-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2461318,13 +2474391,13 @@ index 0000000..fca7fda +} diff --git a/gold/testsuite/incr_comdat_test_2_v3.cc b/gold/testsuite/incr_comdat_test_2_v3.cc new file mode 100644 -index 0000000..cbb83c1 +index 0000000..3c402e9 --- /dev/null +++ b/gold/testsuite/incr_comdat_test_2_v3.cc @@ -0,0 +1,44 @@ +// incr_comdat_test_2.cc -- test incremental update with comdat sections + -+// Copyright 2011 Free Software Foundation, Inc. ++// Copyright (C) 2011-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2461368,7 +2474441,7 @@ index 0000000..cbb83c1 +} diff --git a/gold/testsuite/incremental_test.sh b/gold/testsuite/incremental_test.sh new file mode 100755 -index 0000000..930d7d1 +index 0000000..d8c0c84 --- /dev/null +++ b/gold/testsuite/incremental_test.sh @@ -0,0 +1,89 @@ @@ -2461376,7 +2474449,7 @@ index 0000000..930d7d1 + +# incremental_test.sh -- test that incremental linking information is correct. + -+# Copyright 2009, 2010 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# Written by Rafael Avila de Espindola +# and Cary Coutant + @@ -2461463,11 +2474536,11 @@ index 0000000..930d7d1 +exit 0 diff --git a/gold/testsuite/incremental_test_1.c b/gold/testsuite/incremental_test_1.c new file mode 100644 -index 0000000..291caa0 +index 0000000..850d116 --- /dev/null +++ b/gold/testsuite/incremental_test_1.c @@ -0,0 +1,28 @@ -+// Copyright 2009, 2010 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Rafael Avila de Espindola + +// This file is part of gold. @@ -2461497,11 +2474570,11 @@ index 0000000..291caa0 +} diff --git a/gold/testsuite/incremental_test_2.c b/gold/testsuite/incremental_test_2.c new file mode 100644 -index 0000000..7fcecc4 +index 0000000..a86c0fb --- /dev/null +++ b/gold/testsuite/incremental_test_2.c @@ -0,0 +1,29 @@ -+// Copyright 2009 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Rafael Avila de Espindola + +// This file is part of gold. @@ -2461532,13 +2474605,13 @@ index 0000000..7fcecc4 +} diff --git a/gold/testsuite/initpri1.c b/gold/testsuite/initpri1.c new file mode 100644 -index 0000000..1c5252d +index 0000000..2fbe6bd --- /dev/null +++ b/gold/testsuite/initpri1.c @@ -0,0 +1,105 @@ +/* initpri1.c -- test constructor priorities. + -+ Copyright 2007, 2008, 2009 Free Software Foundation, Inc. ++ Copyright (C) 2007-2014 Free Software Foundation, Inc. + Copied from the gcc testsuite, where the test was contributed by + Mark Mitchell . + @@ -2461643,13 +2474716,13 @@ index 0000000..1c5252d +#endif /* !(__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ > 2)) */ diff --git a/gold/testsuite/initpri2.c b/gold/testsuite/initpri2.c new file mode 100644 -index 0000000..525661f +index 0000000..023d76a --- /dev/null +++ b/gold/testsuite/initpri2.c @@ -0,0 +1,118 @@ +/* initpri2.c -- test mixing init_array and ctor priorities. + -+ Copyright 2011 Free Software Foundation, Inc. ++ Copyright (C) 2011-2014 Free Software Foundation, Inc. + Copied from the gcc configury, where the test was contributed by + H.J. Lu . + @@ -2461767,13 +2474840,13 @@ index 0000000..525661f +} diff --git a/gold/testsuite/initpri3.c b/gold/testsuite/initpri3.c new file mode 100644 -index 0000000..01e233d +index 0000000..65963a9 --- /dev/null +++ b/gold/testsuite/initpri3.c @@ -0,0 +1,80 @@ +/* initpri3.c -- test ctor odering when using init_array. + -+ Copyright 2011 Free Software Foundation, Inc. ++ Copyright (C) 2011-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor . + + This file is part of gold. @@ -2461853,13 +2474926,13 @@ index 0000000..01e233d +} diff --git a/gold/testsuite/justsyms.t b/gold/testsuite/justsyms.t new file mode 100644 -index 0000000..45418be +index 0000000..2af2d01 --- /dev/null +++ b/gold/testsuite/justsyms.t @@ -0,0 +1,31 @@ +/* justsyms.t -- test --just-symbols for gold. + -+ Copyright 2008 Free Software Foundation, Inc. ++ Copyright (C) 2008-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor . + + This file is part of gold. @@ -2461890,13 +2474963,13 @@ index 0000000..45418be +} diff --git a/gold/testsuite/justsyms_1.cc b/gold/testsuite/justsyms_1.cc new file mode 100644 -index 0000000..50716b0 +index 0000000..362f939 --- /dev/null +++ b/gold/testsuite/justsyms_1.cc @@ -0,0 +1,54 @@ +// justsyms_1.cc -- test --just-symbols for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2461950,13 +2475023,13 @@ index 0000000..50716b0 +} diff --git a/gold/testsuite/justsyms_2.cc b/gold/testsuite/justsyms_2.cc new file mode 100644 -index 0000000..dbbf4b5 +index 0000000..c0d9c94 --- /dev/null +++ b/gold/testsuite/justsyms_2.cc @@ -0,0 +1,27 @@ +// justsyms_2.cc -- test --just-symbols for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2461983,13 +2475056,13 @@ index 0000000..dbbf4b5 + "justsyms string"; diff --git a/gold/testsuite/justsyms_exec.c b/gold/testsuite/justsyms_exec.c new file mode 100644 -index 0000000..6670286 +index 0000000..3bb6d2f --- /dev/null +++ b/gold/testsuite/justsyms_exec.c @@ -0,0 +1,56 @@ +// justsyms_exec.c -- test --just-symbols for gold + -+// Copyright 2011 Free Software Foundation, Inc. ++// Copyright (C) 2011-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2462045,13 +2475118,13 @@ index 0000000..6670286 +} diff --git a/gold/testsuite/justsyms_lib.c b/gold/testsuite/justsyms_lib.c new file mode 100644 -index 0000000..9666fb7 +index 0000000..9e043d9 --- /dev/null +++ b/gold/testsuite/justsyms_lib.c @@ -0,0 +1,35 @@ +// justsyms_lib.cc -- test --just-symbols for gold + -+// Copyright 2011 Free Software Foundation, Inc. ++// Copyright (C) 2011-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2462086,13 +2475159,13 @@ index 0000000..9666fb7 +} diff --git a/gold/testsuite/large.c b/gold/testsuite/large.c new file mode 100644 -index 0000000..796242a +index 0000000..0702d11 --- /dev/null +++ b/gold/testsuite/large.c @@ -0,0 +1,59 @@ +/* large.c -- a test case for gold + -+ Copyright 2009 Free Software Foundation, Inc. ++ Copyright (C) 2009-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor . + + This file is part of gold. @@ -2462151,13 +2475224,13 @@ index 0000000..796242a +} diff --git a/gold/testsuite/large_symbol_alignment.cc b/gold/testsuite/large_symbol_alignment.cc new file mode 100644 -index 0000000..1b4a63d +index 0000000..296d7aa --- /dev/null +++ b/gold/testsuite/large_symbol_alignment.cc @@ -0,0 +1,49 @@ +// large_symbol_alignment.cc -- a test case for gold + -+// Copyright 2013 Free Software Foundation, Inc. ++// Copyright (C) 2013-2014 Free Software Foundation, Inc. +// Written by Alexander Ivchenko . + +// This file is part of gold. @@ -2462206,13 +2475279,13 @@ index 0000000..1b4a63d +} diff --git a/gold/testsuite/leb128_unittest.cc b/gold/testsuite/leb128_unittest.cc new file mode 100644 -index 0000000..05c7093 +index 0000000..5b438b3 --- /dev/null +++ b/gold/testsuite/leb128_unittest.cc @@ -0,0 +1,88 @@ +// leb_unittest.cc -- test read_signed_LEB_128 and read_unsigned_LEB_128 + -+// Copyright 2012 Free Software Foundation, Inc. ++// Copyright (C) 2012-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2462300,13 +2475373,13 @@ index 0000000..05c7093 +} // End namespace gold_testsuite. diff --git a/gold/testsuite/many_sections_test.cc b/gold/testsuite/many_sections_test.cc new file mode 100644 -index 0000000..e4b74c3 +index 0000000..44530e2 --- /dev/null +++ b/gold/testsuite/many_sections_test.cc @@ -0,0 +1,51 @@ +// many_sections_test.cc -- test lots of sections for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2462377,7 +2475450,7 @@ index 0000000..ce8576c + .long 0x44 diff --git a/gold/testsuite/memory_test.sh b/gold/testsuite/memory_test.sh new file mode 100755 -index 0000000..db3917a +index 0000000..4e85801 --- /dev/null +++ b/gold/testsuite/memory_test.sh @@ -0,0 +1,57 @@ @@ -2462385,7 +2475458,7 @@ index 0000000..db3917a + +# memory_test.sh -- test MEMORY regions. + -+# Copyright 2010 Free Software Foundation, Inc. ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# Written by Nick Clifton + +# This file is part of gold. @@ -2462472,7 +2475545,7 @@ index 0000000..3a35994 +} diff --git a/gold/testsuite/merge_string_literals.sh b/gold/testsuite/merge_string_literals.sh new file mode 100755 -index 0000000..486a895 +index 0000000..f17ab13 --- /dev/null +++ b/gold/testsuite/merge_string_literals.sh @@ -0,0 +1,41 @@ @@ -2462480,7 +2475553,7 @@ index 0000000..486a895 + +# merge_string_literals.sh -- test + -+# Copyright 2013 Free Software Foundation, Inc. ++# Copyright (C) 2013-2014 Free Software Foundation, Inc. +# Written by Alexander Ivchenko . + +# This file is part of gold. @@ -2462519,13 +2475592,13 @@ index 0000000..486a895 +check merge_string_literals.stdout "abcd" 2 diff --git a/gold/testsuite/merge_string_literals_1.cc b/gold/testsuite/merge_string_literals_1.cc new file mode 100644 -index 0000000..fc0487c +index 0000000..b313dfc --- /dev/null +++ b/gold/testsuite/merge_string_literals_1.cc @@ -0,0 +1,31 @@ +// merge_string_literals_1.c -- a test case for gold + -+// Copyright 2013 Free Software Foundation, Inc. ++// Copyright (C) 2013-2014 Free Software Foundation, Inc. +// Written by Alexander Ivchenko + +// This file is part of gold. @@ -2462556,13 +2475629,13 @@ index 0000000..fc0487c +} diff --git a/gold/testsuite/merge_string_literals_2.cc b/gold/testsuite/merge_string_literals_2.cc new file mode 100644 -index 0000000..d1185cd +index 0000000..73265f5 --- /dev/null +++ b/gold/testsuite/merge_string_literals_2.cc @@ -0,0 +1,31 @@ +// merge_string_literals_2.c -- a test case for gold + -+// Copyright 2013 Free Software Foundation, Inc. ++// Copyright (C) 2013-2014 Free Software Foundation, Inc. +// Written by Alexander Ivchenko + +// This file is part of gold. @@ -2462593,13 +2475666,13 @@ index 0000000..d1185cd +} diff --git a/gold/testsuite/missing_key_func.cc b/gold/testsuite/missing_key_func.cc new file mode 100644 -index 0000000..5a5b7d9 +index 0000000..e89e95a --- /dev/null +++ b/gold/testsuite/missing_key_func.cc @@ -0,0 +1,46 @@ +// basic_test.cc -- a test case for gold + -+// Copyright 2013 Free Software Foundation, Inc. ++// Copyright (C) 2013-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2462645,7 +2475718,7 @@ index 0000000..5a5b7d9 +} diff --git a/gold/testsuite/missing_key_func.sh b/gold/testsuite/missing_key_func.sh new file mode 100755 -index 0000000..54c7b57 +index 0000000..0027c7f --- /dev/null +++ b/gold/testsuite/missing_key_func.sh @@ -0,0 +1,58 @@ @@ -2462654,7 +2475727,7 @@ index 0000000..54c7b57 +# missing_key_func.sh -- a test case for printing error messages when +# a class is missing its key function. + -+# Copyright 2013 Free Software Foundation, Inc. ++# Copyright (C) 2013-2014 Free Software Foundation, Inc. +# Written by Cary Coutant + +# This file is part of gold. @@ -2462709,13 +2475782,13 @@ index 0000000..54c7b57 +check missing_key_func.err "class is missing its key function" diff --git a/gold/testsuite/no_version_test.c b/gold/testsuite/no_version_test.c new file mode 100644 -index 0000000..e42d04f +index 0000000..1171fad --- /dev/null +++ b/gold/testsuite/no_version_test.c @@ -0,0 +1,32 @@ +// ver_no_default.c -- a test case for gold + -+// Copyright 2009 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Doug Kwan . + +// This file is part of gold. @@ -2462747,7 +2475820,7 @@ index 0000000..e42d04f +} diff --git a/gold/testsuite/no_version_test.sh b/gold/testsuite/no_version_test.sh new file mode 100755 -index 0000000..f4ca9b1 +index 0000000..cbcf24f --- /dev/null +++ b/gold/testsuite/no_version_test.sh @@ -0,0 +1,45 @@ @@ -2462756,7 +2475829,7 @@ index 0000000..f4ca9b1 +# no_version_test.sh -- test that .gnu.version* sections are not created +# in a shared object when symbol versioning is not used. + -+# Copyright 2009 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# Written by Doug Kwan + +# This file is part of gold. @@ -2462798,13 +2475871,13 @@ index 0000000..f4ca9b1 +exit 0 diff --git a/gold/testsuite/object_unittest.cc b/gold/testsuite/object_unittest.cc new file mode 100644 -index 0000000..7dedeae +index 0000000..adbd275 --- /dev/null +++ b/gold/testsuite/object_unittest.cc @@ -0,0 +1,105 @@ +// object_unittest.cc -- test Object, Relobj, etc. + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2462998,15 +2476071,84 @@ index 0000000..e3d30f3 +OdrBase* CreateOdrDerived2() { + return new OdrDerived; +} +diff --git a/gold/testsuite/pie_copyrelocs_shared_test.cc b/gold/testsuite/pie_copyrelocs_shared_test.cc +new file mode 100644 +index 0000000..8513417 +--- /dev/null ++++ b/gold/testsuite/pie_copyrelocs_shared_test.cc +@@ -0,0 +1,26 @@ ++// pie_copyrelocs_shared_test.cc -- a test case for gold, used ++// by pie_copyrelocs_test ++ ++// Copyright (C) 2014 Free Software Foundation, Inc. ++// Written by Sriraman Tallam . ++ ++// This file is part of gold. ++ ++// This program is free software; you can redistribute it and/or modify ++// it under the terms of the GNU General Public License as published by ++// the Free Software Foundation; either version 3 of the License, or ++// (at your option) any later version. ++ ++// This program is distributed in the hope that it will be useful, ++// but WITHOUT ANY WARRANTY; without even the implied warranty of ++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++// GNU General Public License for more details. ++ ++// You should have received a copy of the GNU General Public License ++// along with this program; if not, write to the Free Software ++// Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ++// MA 02110-1301, USA. ++ ++ ++ ++int glob_a = 128; +diff --git a/gold/testsuite/pie_copyrelocs_test.cc b/gold/testsuite/pie_copyrelocs_test.cc +new file mode 100644 +index 0000000..bebe89d +--- /dev/null ++++ b/gold/testsuite/pie_copyrelocs_test.cc +@@ -0,0 +1,31 @@ ++// pie_coprelocs_test.cc -- a test case for gold ++ ++// Copyright (C) 2014 Free Software Foundation, Inc. ++// Written by Sriraman Tallam . ++ ++// This file is part of gold. ++ ++// This program is free software; you can redistribute it and/or modify ++// it under the terms of the GNU General Public License as published by ++// the Free Software Foundation; either version 3 of the License, or ++// (at your option) any later version. ++ ++// This program is distributed in the hope that it will be useful, ++// but WITHOUT ANY WARRANTY; without even the implied warranty of ++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++// GNU General Public License for more details. ++ ++// You should have received a copy of the GNU General Public License ++// along with this program; if not, write to the Free Software ++// Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ++// MA 02110-1301, USA. ++ ++// Check if copy relocs are used to access globals below when -fpie is ++// is not used to compile but -pie is used to link. ++ ++extern int glob_a; ++ ++int main () ++{ ++ return glob_a - 128; ++} diff --git a/gold/testsuite/plugin_common_test_1.c b/gold/testsuite/plugin_common_test_1.c new file mode 100644 -index 0000000..262c298 +index 0000000..6f764fd --- /dev/null +++ b/gold/testsuite/plugin_common_test_1.c @@ -0,0 +1,48 @@ +/* plugin_common_test_1.c -- test common symbol handling in plugins + -+ Copyright 2010 Free Software Foundation, Inc. ++ Copyright (C) 2010-2014 Free Software Foundation, Inc. + Written by Cary Coutant + + This file is part of gold. @@ -2463054,13 +2476196,13 @@ index 0000000..262c298 +} diff --git a/gold/testsuite/plugin_common_test_2.c b/gold/testsuite/plugin_common_test_2.c new file mode 100644 -index 0000000..54139ce +index 0000000..c0c934c --- /dev/null +++ b/gold/testsuite/plugin_common_test_2.c @@ -0,0 +1,45 @@ +/* plugin_common_test_2.c -- test common symbol handling in plugins + -+ Copyright 2010 Free Software Foundation, Inc. ++ Copyright (C) 2010-2014 Free Software Foundation, Inc. + Written by Cary Coutant + + This file is part of gold. @@ -2463105,13 +2476247,13 @@ index 0000000..54139ce +} diff --git a/gold/testsuite/plugin_final_layout.cc b/gold/testsuite/plugin_final_layout.cc new file mode 100644 -index 0000000..169eeef +index 0000000..a40c5d6 --- /dev/null +++ b/gold/testsuite/plugin_final_layout.cc @@ -0,0 +1,47 @@ +// plugin_final_layout.cc -- a test case for gold + -+// Copyright 2011 Free Software Foundation, Inc. ++// Copyright (C) 2011-2014 Free Software Foundation, Inc. +// Written by Sriraman Tallam . + +// This file is part of gold. @@ -2463158,7 +2476300,7 @@ index 0000000..169eeef +} diff --git a/gold/testsuite/plugin_final_layout.sh b/gold/testsuite/plugin_final_layout.sh new file mode 100755 -index 0000000..75a40d3 +index 0000000..dc456fa --- /dev/null +++ b/gold/testsuite/plugin_final_layout.sh @@ -0,0 +1,90 @@ @@ -2463166,7 +2476308,7 @@ index 0000000..75a40d3 + +# plugin_final_layout.sh -- test + -+# Copyright 2011 Free Software Foundation, Inc. ++# Copyright (C) 2011-2014 Free Software Foundation, Inc. +# Written by Sriraman Tallam . + +# This file is part of gold. @@ -2463254,13 +2476396,13 @@ index 0000000..75a40d3 +check_unique_segment plugin_final_layout_readelf.stdout ".text.plugin_created_unique" diff --git a/gold/testsuite/plugin_section_order.c b/gold/testsuite/plugin_section_order.c new file mode 100644 -index 0000000..fdc6fe4 +index 0000000..48d30df --- /dev/null +++ b/gold/testsuite/plugin_section_order.c @@ -0,0 +1,188 @@ +/* plugin_section_reorder.c -- Simple plugin to reorder function sections + -+ Copyright 2011 Free Software Foundation, Inc. ++ Copyright (C) 2011-2014 Free Software Foundation, Inc. + Written by Sriraman Tallam . + + This file is part of gold. @@ -2463448,13 +2476590,13 @@ index 0000000..fdc6fe4 +} diff --git a/gold/testsuite/plugin_test.c b/gold/testsuite/plugin_test.c new file mode 100644 -index 0000000..47d400a +index 0000000..79ae44e --- /dev/null +++ b/gold/testsuite/plugin_test.c -@@ -0,0 +1,600 @@ +@@ -0,0 +1,607 @@ +/* test_plugin.c -- simple linker plugin test + -+ Copyright 2008, 2009 Free Software Foundation, Inc. ++ Copyright (C) 2008-2014 Free Software Foundation, Inc. + Written by Cary Coutant . + + This file is part of gold. @@ -2464038,6 +2477180,13 @@ index 0000000..47d400a + p += strcspn(p, " "); + p += strspn(p, " "); + ++ if (*p == '[') ++ { ++ /* Skip st_other. */ ++ p += strcspn(p, "]"); ++ p += strspn(p, "] "); ++ } ++ + /* Section field. */ + info->sect = p; + p += strcspn(p, " "); @@ -2464054,7 +2477203,7 @@ index 0000000..47d400a +} diff --git a/gold/testsuite/plugin_test_1.sh b/gold/testsuite/plugin_test_1.sh new file mode 100755 -index 0000000..4d3ed41 +index 0000000..0f9c9b1 --- /dev/null +++ b/gold/testsuite/plugin_test_1.sh @@ -0,0 +1,59 @@ @@ -2464062,7 +2477211,7 @@ index 0000000..4d3ed41 + +# plugin_test_1.sh -- a test case for the plugin API. + -+# Copyright 2008, 2009 Free Software Foundation, Inc. ++# Copyright (C) 2008-2014 Free Software Foundation, Inc. +# Written by Cary Coutant . + +# This file is part of gold. @@ -2464119,7 +2477268,7 @@ index 0000000..4d3ed41 +exit 0 diff --git a/gold/testsuite/plugin_test_2.sh b/gold/testsuite/plugin_test_2.sh new file mode 100755 -index 0000000..293b1f0 +index 0000000..e06a85f --- /dev/null +++ b/gold/testsuite/plugin_test_2.sh @@ -0,0 +1,56 @@ @@ -2464127,7 +2477276,7 @@ index 0000000..293b1f0 + +# plugin_test_2.sh -- a test case for the plugin API. + -+# Copyright 2008, 2009 Free Software Foundation, Inc. ++# Copyright (C) 2008-2014 Free Software Foundation, Inc. +# Written by Cary Coutant . + +# This file is part of gold. @@ -2464181,7 +2477330,7 @@ index 0000000..293b1f0 +exit 0 diff --git a/gold/testsuite/plugin_test_3.sh b/gold/testsuite/plugin_test_3.sh new file mode 100755 -index 0000000..39356d1 +index 0000000..61a7d95 --- /dev/null +++ b/gold/testsuite/plugin_test_3.sh @@ -0,0 +1,59 @@ @@ -2464189,7 +2477338,7 @@ index 0000000..39356d1 + +# plugin_test_3.sh -- a test case for the plugin API. + -+# Copyright 2008, 2009 Free Software Foundation, Inc. ++# Copyright (C) 2008-2014 Free Software Foundation, Inc. +# Written by Cary Coutant . + +# This file is part of gold. @@ -2464246,7 +2477395,7 @@ index 0000000..39356d1 +exit 0 diff --git a/gold/testsuite/plugin_test_4.sh b/gold/testsuite/plugin_test_4.sh new file mode 100755 -index 0000000..89df46c +index 0000000..9500e41 --- /dev/null +++ b/gold/testsuite/plugin_test_4.sh @@ -0,0 +1,58 @@ @@ -2464254,7 +2477403,7 @@ index 0000000..89df46c + +# plugin_test_4.sh -- a test case for the plugin API. + -+# Copyright 2009 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# Written by Cary Coutant . + +# This file is part of gold. @@ -2464310,7 +2477459,7 @@ index 0000000..89df46c +exit 0 diff --git a/gold/testsuite/plugin_test_6.sh b/gold/testsuite/plugin_test_6.sh new file mode 100755 -index 0000000..9b368e7 +index 0000000..1edb461 --- /dev/null +++ b/gold/testsuite/plugin_test_6.sh @@ -0,0 +1,58 @@ @@ -2464318,7 +2477467,7 @@ index 0000000..9b368e7 + +# plugin_test_6.sh -- a test case for the plugin API. + -+# Copyright 2010 Free Software Foundation, Inc. ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# Written by Cary Coutant . + +# This file is part of gold. @@ -2464374,7 +2477523,7 @@ index 0000000..9b368e7 +exit 0 diff --git a/gold/testsuite/plugin_test_7.sh b/gold/testsuite/plugin_test_7.sh new file mode 100755 -index 0000000..27723f9 +index 0000000..04a554a --- /dev/null +++ b/gold/testsuite/plugin_test_7.sh @@ -0,0 +1,56 @@ @@ -2464382,7 +2477531,7 @@ index 0000000..27723f9 + +# plugin_test_7.sh -- a test case for the plugin API with GC. + -+# Copyright 2010 Free Software Foundation, Inc. ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# Written by Rafael Avila de Espindola . + +# This file is part of gold. @@ -2464436,13 +2477585,13 @@ index 0000000..27723f9 +check_not plugin_test_7.syms "fun2" diff --git a/gold/testsuite/plugin_test_7_1.c b/gold/testsuite/plugin_test_7_1.c new file mode 100644 -index 0000000..5f4c4f3 +index 0000000..fdb0074 --- /dev/null +++ b/gold/testsuite/plugin_test_7_1.c @@ -0,0 +1,43 @@ +/* plugin_test_7_1.c -- a test case for the plugin API with GC. + -+ Copyright 2010 Free Software Foundation, Inc. ++ Copyright (C) 2010-2014 Free Software Foundation, Inc. + Written by Rafael Avila de Espindola . + + This file is part of gold. @@ -2464485,13 +2477634,13 @@ index 0000000..5f4c4f3 +} diff --git a/gold/testsuite/plugin_test_7_2.c b/gold/testsuite/plugin_test_7_2.c new file mode 100644 -index 0000000..06b7676 +index 0000000..e2ca426 --- /dev/null +++ b/gold/testsuite/plugin_test_7_2.c @@ -0,0 +1,33 @@ +/* plugin_test_7_1.c -- a test case for the plugin API with GC. + -+ Copyright 2010 Free Software Foundation, Inc. ++ Copyright (C) 2010-2014 Free Software Foundation, Inc. + Written by Rafael Avila de Espindola . + + This file is part of gold. @@ -2464524,7 +2477673,7 @@ index 0000000..06b7676 +} diff --git a/gold/testsuite/plugin_test_tls.sh b/gold/testsuite/plugin_test_tls.sh new file mode 100755 -index 0000000..22b5458 +index 0000000..fe30cf4 --- /dev/null +++ b/gold/testsuite/plugin_test_tls.sh @@ -0,0 +1,60 @@ @@ -2464532,7 +2477681,7 @@ index 0000000..22b5458 + +# plugin_test_tls.sh -- a test case for the plugin API. + -+# Copyright 2013 Free Software Foundation, Inc. ++# Copyright (C) 2013-2014 Free Software Foundation, Inc. +# Written by Cary Coutant . + +# This file is part of gold. @@ -2464590,7 +2477739,7 @@ index 0000000..22b5458 +exit 0 diff --git a/gold/testsuite/pr12826.sh b/gold/testsuite/pr12826.sh new file mode 100755 -index 0000000..a4fa2e3 +index 0000000..bd3e3a9 --- /dev/null +++ b/gold/testsuite/pr12826.sh @@ -0,0 +1,44 @@ @@ -2464598,7 +2477747,7 @@ index 0000000..a4fa2e3 + +# pr12826.sh -- a test case for combining ARM arch attributes. + -+# Copyright 2011 Free Software Foundation, Inc. ++# Copyright (C) 2011-2014 Free Software Foundation, Inc. +# Written by Doug Kwan . + +# This file is part of gold. @@ -2464704,7 +2477853,7 @@ index 0000000..6bb8f9a +} diff --git a/gold/testsuite/pr14265.sh b/gold/testsuite/pr14265.sh new file mode 100755 -index 0000000..4e477b2 +index 0000000..c82875f --- /dev/null +++ b/gold/testsuite/pr14265.sh @@ -0,0 +1,40 @@ @@ -2464712,7 +2477861,7 @@ index 0000000..4e477b2 + +# pr14265.sh -- test --gc-sections with KEEP + -+# Copyright 2012 Free Software Foundation, Inc. ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# Written by Nick Clifton + +# This file is part of gold. @@ -2464781,13 +2477930,13 @@ index 0000000..e6d163a + diff --git a/gold/testsuite/protected_1.cc b/gold/testsuite/protected_1.cc new file mode 100644 -index 0000000..049bda7 +index 0000000..e9725a9 --- /dev/null +++ b/gold/testsuite/protected_1.cc @@ -0,0 +1,58 @@ +// protected_1.cc -- a test case for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2464845,13 +2477994,13 @@ index 0000000..049bda7 +} diff --git a/gold/testsuite/protected_2.cc b/gold/testsuite/protected_2.cc new file mode 100644 -index 0000000..19d8276 +index 0000000..44bd9af --- /dev/null +++ b/gold/testsuite/protected_2.cc @@ -0,0 +1,31 @@ +// protected_2.cc -- a test case for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2464882,13 +2478031,13 @@ index 0000000..19d8276 +} diff --git a/gold/testsuite/protected_3.cc b/gold/testsuite/protected_3.cc new file mode 100644 -index 0000000..8a27a2a +index 0000000..b22181c --- /dev/null +++ b/gold/testsuite/protected_3.cc @@ -0,0 +1,33 @@ +// protected_2.cc -- a test case for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2464921,13 +2478070,13 @@ index 0000000..8a27a2a +} diff --git a/gold/testsuite/protected_4.cc b/gold/testsuite/protected_4.cc new file mode 100644 -index 0000000..58e3e2b +index 0000000..918d7c1 --- /dev/null +++ b/gold/testsuite/protected_4.cc @@ -0,0 +1,32 @@ +// protected_4.cc -- a test case for gold + -+// Copyright 2010 Free Software Foundation, Inc. ++// Copyright (C) 2010-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2464959,13 +2478108,13 @@ index 0000000..58e3e2b +} diff --git a/gold/testsuite/protected_main_1.cc b/gold/testsuite/protected_main_1.cc new file mode 100644 -index 0000000..271446f +index 0000000..b1c3b87 --- /dev/null +++ b/gold/testsuite/protected_main_1.cc @@ -0,0 +1,40 @@ +// protected_main_1.cc -- a test case for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2465005,13 +2478154,13 @@ index 0000000..271446f +} diff --git a/gold/testsuite/protected_main_2.cc b/gold/testsuite/protected_main_2.cc new file mode 100644 -index 0000000..6960322 +index 0000000..29bfcfa --- /dev/null +++ b/gold/testsuite/protected_main_2.cc @@ -0,0 +1,29 @@ +// protected_main_2.cc -- a test case for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2465040,13 +2478189,13 @@ index 0000000..6960322 +} diff --git a/gold/testsuite/protected_main_3.cc b/gold/testsuite/protected_main_3.cc new file mode 100644 -index 0000000..f356f3d +index 0000000..02f4c94 --- /dev/null +++ b/gold/testsuite/protected_main_3.cc @@ -0,0 +1,31 @@ +// protected_main_3.cc -- a test case for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2465077,13 +2478226,13 @@ index 0000000..f356f3d +} diff --git a/gold/testsuite/relro_script_test.t b/gold/testsuite/relro_script_test.t new file mode 100644 -index 0000000..3a6e3e9 +index 0000000..e4af879 --- /dev/null +++ b/gold/testsuite/relro_script_test.t @@ -0,0 +1,54 @@ +/* relro_test.t -- relro script test for gold + -+ Copyright 2008 Free Software Foundation, Inc. ++ Copyright (C) 2008-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor . + + This file is part of gold. @@ -2465137,13 +2478286,13 @@ index 0000000..3a6e3e9 +} diff --git a/gold/testsuite/relro_test.cc b/gold/testsuite/relro_test.cc new file mode 100644 -index 0000000..795ad39 +index 0000000..b64e5cf --- /dev/null +++ b/gold/testsuite/relro_test.cc @@ -0,0 +1,160 @@ +// relro_test.cc -- test -z relro for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2465303,7 +2478452,7 @@ index 0000000..795ad39 +} diff --git a/gold/testsuite/relro_test.sh b/gold/testsuite/relro_test.sh new file mode 100755 -index 0000000..47a9491 +index 0000000..69f0ff7 --- /dev/null +++ b/gold/testsuite/relro_test.sh @@ -0,0 +1,74 @@ @@ -2465311,7 +2478460,7 @@ index 0000000..47a9491 + +# relro_test.sh -- test -z relro + -+# Copyright 2010, 2011 Free Software Foundation, Inc. ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# Written by Cary Coutant . + +# This file is part of gold. @@ -2465383,13 +2478532,13 @@ index 0000000..47a9491 +check relro_test.stdout diff --git a/gold/testsuite/relro_test_main.cc b/gold/testsuite/relro_test_main.cc new file mode 100644 -index 0000000..6f5ea2b +index 0000000..8a14274 --- /dev/null +++ b/gold/testsuite/relro_test_main.cc @@ -0,0 +1,33 @@ +// relro_test_main.cc -- test -z relro for gold, main function + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2465422,7 +2478571,7 @@ index 0000000..6f5ea2b +} diff --git a/gold/testsuite/retain_symbols_file_test.sh b/gold/testsuite/retain_symbols_file_test.sh new file mode 100755 -index 0000000..e0d3ffc +index 0000000..21373d1 --- /dev/null +++ b/gold/testsuite/retain_symbols_file_test.sh @@ -0,0 +1,54 @@ @@ -2465430,7 +2478579,7 @@ index 0000000..e0d3ffc + +# retain_symbols_file_test.sh -- a test case for -retain-symbols-file + -+# Copyright 2009 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# Written by Craig Silverstein . + +# This file is part of gold. @@ -2465482,13 +2478631,13 @@ index 0000000..e0d3ffc +exit 0 diff --git a/gold/testsuite/script_test_1.cc b/gold/testsuite/script_test_1.cc new file mode 100644 -index 0000000..1bdf770 +index 0000000..ecdf67e --- /dev/null +++ b/gold/testsuite/script_test_1.cc @@ -0,0 +1,47 @@ +// script_test_1.cc -- linker script test 1 for gold -*- C++ -*- + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2465535,13 +2478684,13 @@ index 0000000..1bdf770 +} diff --git a/gold/testsuite/script_test_1.t b/gold/testsuite/script_test_1.t new file mode 100644 -index 0000000..af971c6 +index 0000000..22a1e39 --- /dev/null +++ b/gold/testsuite/script_test_1.t @@ -0,0 +1,29 @@ +/* script_test_1.t -- linker script test 1 for gold + -+ Copyright 2008 Free Software Foundation, Inc. ++ Copyright (C) 2008-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor . + + This file is part of gold. @@ -2465590,7 +2478739,7 @@ index 0000000..5f3e30f + diff --git a/gold/testsuite/script_test_10.sh b/gold/testsuite/script_test_10.sh new file mode 100755 -index 0000000..58446ab +index 0000000..41b2bc7 --- /dev/null +++ b/gold/testsuite/script_test_10.sh @@ -0,0 +1,46 @@ @@ -2465598,7 +2478747,7 @@ index 0000000..58446ab + +# script_test_10.sh -- test for the section order. + -+# Copyright 2010 Free Software Foundation, Inc. ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# Written by Viktor Kutuzov . + +# This file is part of gold. @@ -2465642,13 +2478791,13 @@ index 0000000..58446ab + diff --git a/gold/testsuite/script_test_10.t b/gold/testsuite/script_test_10.t new file mode 100644 -index 0000000..98f2107 +index 0000000..14b0578 --- /dev/null +++ b/gold/testsuite/script_test_10.t @@ -0,0 +1,34 @@ +/* script_test_10.t -- test section order for gold. + -+ Copyright 2010 Free Software Foundation, Inc. ++ Copyright (C) 2010-2014 Free Software Foundation, Inc. + Written by Viktor Kutuzov . + + This file is part of gold. @@ -2465718,13 +2478867,13 @@ index 0000000..0ec6bcd +} diff --git a/gold/testsuite/script_test_2.cc b/gold/testsuite/script_test_2.cc new file mode 100644 -index 0000000..7104551 +index 0000000..59c007c --- /dev/null +++ b/gold/testsuite/script_test_2.cc @@ -0,0 +1,74 @@ +// script_test_2.cc -- linker script test 2 for gold -*- C++ -*- + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2465798,13 +2478947,13 @@ index 0000000..7104551 +} diff --git a/gold/testsuite/script_test_2.t b/gold/testsuite/script_test_2.t new file mode 100644 -index 0000000..81ed9aa +index 0000000..eabf4ec --- /dev/null +++ b/gold/testsuite/script_test_2.t @@ -0,0 +1,69 @@ +/* script_test_2.t -- linker script test 2 for gold + -+ Copyright 2008 Free Software Foundation, Inc. ++ Copyright (C) 2008-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor . + + This file is part of gold. @@ -2465873,13 +2479022,13 @@ index 0000000..81ed9aa +} diff --git a/gold/testsuite/script_test_2a.cc b/gold/testsuite/script_test_2a.cc new file mode 100644 -index 0000000..6c665eb +index 0000000..7c1990d --- /dev/null +++ b/gold/testsuite/script_test_2a.cc @@ -0,0 +1,24 @@ +// script_test_2a.cc -- linker script test 2, file 1 -*- C++ -*- + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2465903,13 +2479052,13 @@ index 0000000..6c665eb + "test aa"; diff --git a/gold/testsuite/script_test_2b.cc b/gold/testsuite/script_test_2b.cc new file mode 100644 -index 0000000..9b19eb0 +index 0000000..c99d10d --- /dev/null +++ b/gold/testsuite/script_test_2b.cc @@ -0,0 +1,24 @@ +// script_test_2a.cc -- linker script test 2, file 2 -*- C++ -*- + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2465933,7 +2479082,7 @@ index 0000000..9b19eb0 + "test bb"; diff --git a/gold/testsuite/script_test_3.sh b/gold/testsuite/script_test_3.sh new file mode 100755 -index 0000000..d114edd +index 0000000..a24505e --- /dev/null +++ b/gold/testsuite/script_test_3.sh @@ -0,0 +1,102 @@ @@ -2465941,7 +2479090,7 @@ index 0000000..d114edd + +# script_test_3.sh -- test PHDRS + -+# Copyright 2008 Free Software Foundation, Inc. ++# Copyright (C) 2008-2014 Free Software Foundation, Inc. +# Written by Ian Lance Taylor . + +# This file is part of gold. @@ -2466041,13 +2479190,13 @@ index 0000000..d114edd +exit 0 diff --git a/gold/testsuite/script_test_3.t b/gold/testsuite/script_test_3.t new file mode 100644 -index 0000000..accd055 +index 0000000..22a0c6f --- /dev/null +++ b/gold/testsuite/script_test_3.t @@ -0,0 +1,55 @@ +/* script_test_3.t -- linker script test 3 for gold + -+ Copyright 2008, 2010 Free Software Foundation, Inc. ++ Copyright (C) 2008-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor . + + This file is part of gold. @@ -2466102,7 +2479251,7 @@ index 0000000..accd055 +} diff --git a/gold/testsuite/script_test_4.sh b/gold/testsuite/script_test_4.sh new file mode 100755 -index 0000000..755d1a0 +index 0000000..6a0a26b --- /dev/null +++ b/gold/testsuite/script_test_4.sh @@ -0,0 +1,41 @@ @@ -2466110,7 +2479259,7 @@ index 0000000..755d1a0 + +# script_test_4.sh -- test load segment + -+# Copyright 2008 Free Software Foundation, Inc. ++# Copyright (C) 2008-2014 Free Software Foundation, Inc. +# Written by Ian Lance Taylor . + +# This file is part of gold. @@ -2466149,13 +2479298,13 @@ index 0000000..755d1a0 +check script_test_4.stdout "\\.interp[ ]*PROGBITS[ ]*0*10000400" diff --git a/gold/testsuite/script_test_4.t b/gold/testsuite/script_test_4.t new file mode 100644 -index 0000000..3ba5e93 +index 0000000..c441ad5 --- /dev/null +++ b/gold/testsuite/script_test_4.t @@ -0,0 +1,45 @@ +/* script_test_4.t -- linker script test 4 for gold + -+ Copyright 2008 Free Software Foundation, Inc. ++ Copyright (C) 2008-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor . + + This file is part of gold. @@ -2466200,13 +2479349,13 @@ index 0000000..3ba5e93 +} diff --git a/gold/testsuite/script_test_5.cc b/gold/testsuite/script_test_5.cc new file mode 100644 -index 0000000..b5aec29 +index 0000000..d90477c --- /dev/null +++ b/gold/testsuite/script_test_5.cc @@ -0,0 +1,45 @@ +// script_test_5.cc -- a test case for gold + -+// Copyright 2009 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2466251,7 +2479400,7 @@ index 0000000..b5aec29 +} diff --git a/gold/testsuite/script_test_5.sh b/gold/testsuite/script_test_5.sh new file mode 100755 -index 0000000..76e2e31 +index 0000000..9ff9486 --- /dev/null +++ b/gold/testsuite/script_test_5.sh @@ -0,0 +1,43 @@ @@ -2466259,7 +2479408,7 @@ index 0000000..76e2e31 + +# script_test_5.sh -- test linker script with uncovered sections + -+# Copyright 2009 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# Written by Cary Coutant . + +# This file is part of gold. @@ -2466300,13 +2479449,13 @@ index 0000000..76e2e31 +check_count script_test_5.stdout " .text.foo " 1 diff --git a/gold/testsuite/script_test_5.t b/gold/testsuite/script_test_5.t new file mode 100644 -index 0000000..4a7d13f +index 0000000..65ada93 --- /dev/null +++ b/gold/testsuite/script_test_5.t @@ -0,0 +1,44 @@ +/* script_test_5.t -- linker script test 5 for gold + -+ Copyright 2009 Free Software Foundation, Inc. ++ Copyright (C) 2009-2014 Free Software Foundation, Inc. + Written by Cary Coutant . + + This file is part of gold. @@ -2466350,7 +2479499,7 @@ index 0000000..4a7d13f +} diff --git a/gold/testsuite/script_test_6.sh b/gold/testsuite/script_test_6.sh new file mode 100755 -index 0000000..bbc96d8 +index 0000000..fc8d504 --- /dev/null +++ b/gold/testsuite/script_test_6.sh @@ -0,0 +1,43 @@ @@ -2466358,7 +2479507,7 @@ index 0000000..bbc96d8 + +# script_test_6.sh -- test for -Ttext, -Tdata and -Tbss with a script. + -+# Copyright 2009 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# Written by Doug Kwan . + +# This file is part of gold. @@ -2466399,13 +2479548,13 @@ index 0000000..bbc96d8 +check script_test_6.stdout "\\.bss[ ]*NOBITS[ ]*0*10400000" diff --git a/gold/testsuite/script_test_6.t b/gold/testsuite/script_test_6.t new file mode 100644 -index 0000000..d3127e3 +index 0000000..e123a1e --- /dev/null +++ b/gold/testsuite/script_test_6.t @@ -0,0 +1,45 @@ +/* script_test_5.t -- linker script test 5 for gold + -+ Copyright 2009 Free Software Foundation, Inc. ++ Copyright (C) 2009-2014 Free Software Foundation, Inc. + Written by Cary Coutant . + + This file is part of gold. @@ -2466450,7 +2479599,7 @@ index 0000000..d3127e3 +} diff --git a/gold/testsuite/script_test_7.sh b/gold/testsuite/script_test_7.sh new file mode 100755 -index 0000000..982a1c1 +index 0000000..efcbb4c --- /dev/null +++ b/gold/testsuite/script_test_7.sh @@ -0,0 +1,43 @@ @@ -2466458,7 +2479607,7 @@ index 0000000..982a1c1 + +# script_test_7.sh -- test for SEGMENT_START expressions. + -+# Copyright 2009 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# Written by Doug Kwan . + +# This file is part of gold. @@ -2466499,13 +2479648,13 @@ index 0000000..982a1c1 +check script_test_7.stdout "\\.bss[ ]*NOBITS[ ]*0*10400..." diff --git a/gold/testsuite/script_test_7.t b/gold/testsuite/script_test_7.t new file mode 100644 -index 0000000..ab2bbee +index 0000000..575225d --- /dev/null +++ b/gold/testsuite/script_test_7.t @@ -0,0 +1,45 @@ +/* script_test_5.t -- linker script test 5 for gold + -+ Copyright 2009 Free Software Foundation, Inc. ++ Copyright (C) 2009-2014 Free Software Foundation, Inc. + Written by Cary Coutant . + + This file is part of gold. @@ -2466550,7 +2479699,7 @@ index 0000000..ab2bbee +} diff --git a/gold/testsuite/script_test_8.sh b/gold/testsuite/script_test_8.sh new file mode 100755 -index 0000000..83e8e72 +index 0000000..02531d2 --- /dev/null +++ b/gold/testsuite/script_test_8.sh @@ -0,0 +1,44 @@ @@ -2466559,7 +2479708,7 @@ index 0000000..83e8e72 +# script_test_8.sh -- test for SEGMENT_START expressions with +# -Ttext, -Tdata and -Tbss in a script. + -+# Copyright 2009 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# Written by Doug Kwan . + +# This file is part of gold. @@ -2466600,13 +2479749,13 @@ index 0000000..83e8e72 +check script_test_8.stdout "\\.bss[ ]*NOBITS[ ]*0*2040...." diff --git a/gold/testsuite/script_test_9.cc b/gold/testsuite/script_test_9.cc new file mode 100644 -index 0000000..84f12f6 +index 0000000..19d7153 --- /dev/null +++ b/gold/testsuite/script_test_9.cc @@ -0,0 +1,29 @@ +// script_test_9.cc -- a test case for gold + -+// Copyright 2010 Free Software Foundation, Inc. ++// Copyright (C) 2010-2014 Free Software Foundation, Inc. +// Written by Rafael Avila de Espindola . + +// This file is part of gold. @@ -2466635,7 +2479784,7 @@ index 0000000..84f12f6 +} diff --git a/gold/testsuite/script_test_9.sh b/gold/testsuite/script_test_9.sh new file mode 100755 -index 0000000..9f9aba6 +index 0000000..29a8efe --- /dev/null +++ b/gold/testsuite/script_test_9.sh @@ -0,0 +1,42 @@ @@ -2466644,7 +2479793,7 @@ index 0000000..9f9aba6 +# script_test_9.sh -- Check that the script_test_9.t script has placed +# .init and .text in the same segment. + -+# Copyright 2010 Free Software Foundation, Inc. ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# Written by Rafael Avila de Espindola . + +# This file is part of gold. @@ -2466717,13 +2479866,13 @@ index 0000000..e7138b2 +} diff --git a/gold/testsuite/searched_file_test.cc b/gold/testsuite/searched_file_test.cc new file mode 100644 -index 0000000..aa99e24 +index 0000000..31277f1 --- /dev/null +++ b/gold/testsuite/searched_file_test.cc @@ -0,0 +1,36 @@ +// searched_file_test.cc -- test -l:foo.a for gold + -+// Copyright 2009 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Chris Demetriou . + +// This file is part of gold. @@ -2466759,13 +2479908,13 @@ index 0000000..aa99e24 + diff --git a/gold/testsuite/searched_file_test_lib.cc b/gold/testsuite/searched_file_test_lib.cc new file mode 100644 -index 0000000..0686e52 +index 0000000..340afc4 --- /dev/null +++ b/gold/testsuite/searched_file_test_lib.cc @@ -0,0 +1,27 @@ +// searched_file_test_lib.cc -- test -l:foo.a for gold + -+// Copyright 2009 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Chris Demetriou . + +// This file is part of gold. @@ -2466792,13 +2479941,13 @@ index 0000000..0686e52 +int zero_from_lib = 0; diff --git a/gold/testsuite/section_sorting_name.cc b/gold/testsuite/section_sorting_name.cc new file mode 100644 -index 0000000..e89c1ed +index 0000000..cb7260c --- /dev/null +++ b/gold/testsuite/section_sorting_name.cc @@ -0,0 +1,59 @@ +// section_sorting_name.cc -- a test case for gold + -+// Copyright 2013 Free Software Foundation, Inc. ++// Copyright (C) 2013-2014 Free Software Foundation, Inc. +// Written by Alexander Ivchenko . + +// This file is part of gold. @@ -2466857,7 +2480006,7 @@ index 0000000..e89c1ed +} diff --git a/gold/testsuite/section_sorting_name.sh b/gold/testsuite/section_sorting_name.sh new file mode 100755 -index 0000000..00b6994 +index 0000000..b413299 --- /dev/null +++ b/gold/testsuite/section_sorting_name.sh @@ -0,0 +1,66 @@ @@ -2466865,7 +2480014,7 @@ index 0000000..00b6994 + +# section_sorting_name.sh -- test + -+# Copyright 2013 Free Software Foundation, Inc. ++# Copyright (C) 2013-2014 Free Software Foundation, Inc. +# Written by Alexander Ivchenko . + +# This file is part of gold. @@ -2466929,7 +2480078,7 @@ index 0000000..00b6994 +check section_sorting_name.stdout "vbss_0002" "vbss_0003" diff --git a/gold/testsuite/split_i386.sh b/gold/testsuite/split_i386.sh new file mode 100755 -index 0000000..e94fea2 +index 0000000..f48ea5d --- /dev/null +++ b/gold/testsuite/split_i386.sh @@ -0,0 +1,54 @@ @@ -2466937,7 +2480086,7 @@ index 0000000..e94fea2 + +# split_i386.sh -- test -fstack-split for i386 + -+# Copyright 2009 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# Written by Ian Lance Taylor . + +# This file is part of gold. @@ -2467142,7 +2480291,7 @@ index 0000000..4d4e6e8 + .section .note.GNU-stack,"",@progbits diff --git a/gold/testsuite/split_x86_64.sh b/gold/testsuite/split_x86_64.sh new file mode 100755 -index 0000000..61544b2 +index 0000000..530c4b1 --- /dev/null +++ b/gold/testsuite/split_x86_64.sh @@ -0,0 +1,54 @@ @@ -2467150,7 +2480299,7 @@ index 0000000..61544b2 + +# split_x86_64.sh -- test -fstack-split for x86_64 + -+# Copyright 2009 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# Written by Ian Lance Taylor . + +# This file is part of gold. @@ -2467355,13 +2480504,13 @@ index 0000000..10436b1 + .section .note.GNU-stack,"",@progbits diff --git a/gold/testsuite/start_lib_test_1.c b/gold/testsuite/start_lib_test_1.c new file mode 100644 -index 0000000..024276a +index 0000000..3cd8a51 --- /dev/null +++ b/gold/testsuite/start_lib_test_1.c @@ -0,0 +1,32 @@ +/* start_lib_test_1.c -- test --start-lib/--end-lib. + -+ Copyright 2010 Free Software Foundation, Inc. ++ Copyright (C) 2010-2014 Free Software Foundation, Inc. + Written by Cary Coutant + + This file is part of gold. @@ -2467393,13 +2480542,13 @@ index 0000000..024276a +} diff --git a/gold/testsuite/start_lib_test_2.c b/gold/testsuite/start_lib_test_2.c new file mode 100644 -index 0000000..443a79c +index 0000000..b6a99a1 --- /dev/null +++ b/gold/testsuite/start_lib_test_2.c @@ -0,0 +1,30 @@ +/* start_lib_test_2.c -- test --start-lib/--end-lib. + -+ Copyright 2010 Free Software Foundation, Inc. ++ Copyright (C) 2010-2014 Free Software Foundation, Inc. + Written by Cary Coutant + + This file is part of gold. @@ -2467429,13 +2480578,13 @@ index 0000000..443a79c +} diff --git a/gold/testsuite/start_lib_test_3.c b/gold/testsuite/start_lib_test_3.c new file mode 100644 -index 0000000..79b467b +index 0000000..64a1ebf --- /dev/null +++ b/gold/testsuite/start_lib_test_3.c @@ -0,0 +1,25 @@ +/* start_lib_test_3.c -- test --start-lib/--end-lib. + -+ Copyright 2010 Free Software Foundation, Inc. ++ Copyright (C) 2010-2014 Free Software Foundation, Inc. + Written by Cary Coutant + + This file is part of gold. @@ -2467460,13 +2480609,13 @@ index 0000000..79b467b +static char t3[] __attribute__ ((used)) = "t3"; diff --git a/gold/testsuite/start_lib_test_main.c b/gold/testsuite/start_lib_test_main.c new file mode 100644 -index 0000000..7809baa +index 0000000..6531ba9 --- /dev/null +++ b/gold/testsuite/start_lib_test_main.c @@ -0,0 +1,33 @@ +/* start_lib_test_main.c -- test --start-lib/--end-lib. + -+ Copyright 2010 Free Software Foundation, Inc. ++ Copyright (C) 2010-2014 Free Software Foundation, Inc. + Written by Cary Coutant + + This file is part of gold. @@ -2467499,7 +2480648,7 @@ index 0000000..7809baa +} diff --git a/gold/testsuite/strong_ref_weak_def.sh b/gold/testsuite/strong_ref_weak_def.sh new file mode 100755 -index 0000000..17afc5b +index 0000000..d5b766f --- /dev/null +++ b/gold/testsuite/strong_ref_weak_def.sh @@ -0,0 +1,42 @@ @@ -2467508,7 +2480657,7 @@ index 0000000..17afc5b +# strong_ref_weak_def.sh -- test non-weak reference to a weak symbol defined +# in a DSO. + -+# Copyright 2010 Free Software Foundation, Inc. ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# Written by Doug Kwan . + +# This file is part of gold. @@ -2467547,14 +2480696,14 @@ index 0000000..17afc5b +exit 0 diff --git a/gold/testsuite/strong_ref_weak_def_1.c b/gold/testsuite/strong_ref_weak_def_1.c new file mode 100644 -index 0000000..bc00e77 +index 0000000..61493f2 --- /dev/null +++ b/gold/testsuite/strong_ref_weak_def_1.c @@ -0,0 +1,39 @@ +// strong_ref_weak_def_1.c -- test a strong reference to a weak definition +// in a DSO. + -+// Copyright 2010 Free Software Foundation, Inc. ++// Copyright (C) 2010-2014 Free Software Foundation, Inc. +// Written by Doug Kwan . + +// This file is part of gold. @@ -2467592,14 +2480741,14 @@ index 0000000..bc00e77 +} diff --git a/gold/testsuite/strong_ref_weak_def_2.c b/gold/testsuite/strong_ref_weak_def_2.c new file mode 100644 -index 0000000..4801f6d +index 0000000..c7c9ede --- /dev/null +++ b/gold/testsuite/strong_ref_weak_def_2.c @@ -0,0 +1,37 @@ +// strong_ref_weak_def_2.c -- test a strong reference to a weak definition +// in a DSO. + -+// Copyright 2010 Free Software Foundation, Inc. ++// Copyright (C) 2010-2014 Free Software Foundation, Inc. +// Written by Doug Kwan . + +// This file is part of gold. @@ -2467635,13 +2480784,13 @@ index 0000000..4801f6d +} diff --git a/gold/testsuite/test.cc b/gold/testsuite/test.cc new file mode 100644 -index 0000000..b08d6d7 +index 0000000..80f2ab5 --- /dev/null +++ b/gold/testsuite/test.cc @@ -0,0 +1,107 @@ +// test.cc -- simplistic test framework for gold. + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2467748,13 +2480897,13 @@ index 0000000..b08d6d7 +} // End namespace gold_testsuite. diff --git a/gold/testsuite/test.h b/gold/testsuite/test.h new file mode 100644 -index 0000000..37060d3 +index 0000000..1522bcf --- /dev/null +++ b/gold/testsuite/test.h @@ -0,0 +1,145 @@ +// test.h -- simplistic test framework for gold unittests -*- C++ -*- + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2467899,13 +2481048,13 @@ index 0000000..37060d3 +#endif // !defined(GOLD_TESTSUITE_TEST_H) diff --git a/gold/testsuite/testfile.cc b/gold/testsuite/testfile.cc new file mode 100644 -index 0000000..f360e3d +index 0000000..3defb4d --- /dev/null +++ b/gold/testsuite/testfile.cc @@ -0,0 +1,949 @@ +// testfile.cc -- Dummy ELF objects for testing purposes. + -+// Copyright 2006, 2007, 2008, 2009, 2011, 2012 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2468854,13 +2482003,13 @@ index 0000000..f360e3d +} // End namespace gold_testsuite. diff --git a/gold/testsuite/testfile.h b/gold/testsuite/testfile.h new file mode 100644 -index 0000000..9178179 +index 0000000..dac02ff --- /dev/null +++ b/gold/testsuite/testfile.h @@ -0,0 +1,49 @@ +// testfile.h -- test input files -*- C++ -*- + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2468909,13 +2482058,13 @@ index 0000000..9178179 +#endif // !defined(GOLD_TESTSUITE_TESTFILE_H) diff --git a/gold/testsuite/testmain.cc b/gold/testsuite/testmain.cc new file mode 100644 -index 0000000..ac99000 +index 0000000..a3a105c --- /dev/null +++ b/gold/testsuite/testmain.cc @@ -0,0 +1,40 @@ +// testmain.cc -- main function for simplisitic gold test framework. + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2468955,13 +2482104,13 @@ index 0000000..ac99000 +} diff --git a/gold/testsuite/text_section_grouping.cc b/gold/testsuite/text_section_grouping.cc new file mode 100644 -index 0000000..5a3a809 +index 0000000..dc29a1f --- /dev/null +++ b/gold/testsuite/text_section_grouping.cc @@ -0,0 +1,72 @@ +// text_section_grouping.cc -- a test case for gold + -+// Copyright 2012 Free Software Foundation, Inc. ++// Copyright (C) 2012-2014 Free Software Foundation, Inc. +// Written by Sriraman Tallam . + +// This file is part of gold. @@ -2469033,7 +2482182,7 @@ index 0000000..5a3a809 +} diff --git a/gold/testsuite/text_section_grouping.sh b/gold/testsuite/text_section_grouping.sh new file mode 100755 -index 0000000..84ebe4c +index 0000000..a819e57 --- /dev/null +++ b/gold/testsuite/text_section_grouping.sh @@ -0,0 +1,73 @@ @@ -2469041,7 +2482190,7 @@ index 0000000..84ebe4c + +# text_section_grouping.sh -- test + -+# Copyright 2012 Free Software Foundation, Inc. ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# Written by Sriraman Tallam . + +# This file is part of gold. @@ -2469112,13 +2482261,13 @@ index 0000000..84ebe4c +check text_section_no_grouping.stdout "startup_bar" "unlikely_bar" diff --git a/gold/testsuite/thin_archive_main.cc b/gold/testsuite/thin_archive_main.cc new file mode 100644 -index 0000000..6c38715 +index 0000000..6f19c0a --- /dev/null +++ b/gold/testsuite/thin_archive_main.cc @@ -0,0 +1,39 @@ +// thin_archive_main.cc -- a test case for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2469157,13 +2482306,13 @@ index 0000000..6c38715 +} diff --git a/gold/testsuite/thin_archive_test_1.cc b/gold/testsuite/thin_archive_test_1.cc new file mode 100644 -index 0000000..db23937 +index 0000000..f44b3dd --- /dev/null +++ b/gold/testsuite/thin_archive_test_1.cc @@ -0,0 +1,37 @@ +// thin_archive_test_1.cc -- part of a test case for thin archives + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2469200,13 +2482349,13 @@ index 0000000..db23937 +} diff --git a/gold/testsuite/thin_archive_test_2.cc b/gold/testsuite/thin_archive_test_2.cc new file mode 100644 -index 0000000..2c1ee31 +index 0000000..15c9a7a --- /dev/null +++ b/gold/testsuite/thin_archive_test_2.cc @@ -0,0 +1,37 @@ +// thin_archive_test_2.cc -- part of a test case for thin archives + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2469243,13 +2482392,13 @@ index 0000000..2c1ee31 +} diff --git a/gold/testsuite/thin_archive_test_3.cc b/gold/testsuite/thin_archive_test_3.cc new file mode 100644 -index 0000000..b58c59f +index 0000000..96cd79d --- /dev/null +++ b/gold/testsuite/thin_archive_test_3.cc @@ -0,0 +1,37 @@ +// thin_archive_test_3.cc -- part of a test case for thin archives + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2469286,13 +2482435,13 @@ index 0000000..b58c59f +} diff --git a/gold/testsuite/thin_archive_test_4.cc b/gold/testsuite/thin_archive_test_4.cc new file mode 100644 -index 0000000..1b67c94 +index 0000000..903de11 --- /dev/null +++ b/gold/testsuite/thin_archive_test_4.cc @@ -0,0 +1,35 @@ +// thin_archive_test_4.cc -- part of a test case for thin archives + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2469327,13 +2482476,13 @@ index 0000000..1b67c94 +} diff --git a/gold/testsuite/thumb2_branch_range.t b/gold/testsuite/thumb2_branch_range.t new file mode 100644 -index 0000000..8fdc783 +index 0000000..2002fb9 --- /dev/null +++ b/gold/testsuite/thumb2_branch_range.t @@ -0,0 +1,36 @@ +/* thumb2_banch_range.t -- linker script to test THUMB-2 branch range. + -+ Copyright 2010 Free Software Foundation, Inc. ++ Copyright (C) 2010-2014 Free Software Foundation, Inc. + Written by Doug Kwan . + + This file is part of gold. @@ -2469708,13 +2482857,13 @@ index 0000000..c4f87e0 + .size _forward_target, .-_forward_target diff --git a/gold/testsuite/thumb_branch_range.t b/gold/testsuite/thumb_branch_range.t new file mode 100644 -index 0000000..fa858b5 +index 0000000..2b0e54e --- /dev/null +++ b/gold/testsuite/thumb_branch_range.t @@ -0,0 +1,36 @@ +/* thumb_banch_range.t -- linker script to test ARM branch range. + -+ Copyright 2010 Free Software Foundation, Inc. ++ Copyright (C) 2010-2014 Free Software Foundation, Inc. + Written by Doug Kwan . + + This file is part of gold. @@ -2469750,13 +2482899,13 @@ index 0000000..fa858b5 +} diff --git a/gold/testsuite/tls_test.cc b/gold/testsuite/tls_test.cc new file mode 100644 -index 0000000..c875752 +index 0000000..7d38658 --- /dev/null +++ b/gold/testsuite/tls_test.cc @@ -0,0 +1,224 @@ +// tls_test.cc -- test TLS variables for gold + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2469980,13 +2483129,13 @@ index 0000000..c875752 +} diff --git a/gold/testsuite/tls_test.h b/gold/testsuite/tls_test.h new file mode 100644 -index 0000000..1c98b17 +index 0000000..b70c0ee --- /dev/null +++ b/gold/testsuite/tls_test.h @@ -0,0 +1,56 @@ +// tls_test.h -- test TLS variables for gold, header file -*- C++ -*- + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2470042,13 +2483191,13 @@ index 0000000..1c98b17 +extern __thread int o3; diff --git a/gold/testsuite/tls_test_c.c b/gold/testsuite/tls_test_c.c new file mode 100644 -index 0000000..896191f +index 0000000..918a5b2 --- /dev/null +++ b/gold/testsuite/tls_test_c.c @@ -0,0 +1,65 @@ +/* tls_test_c.c -- test TLS common symbol + -+ Copyright 2008 Free Software Foundation, Inc. ++ Copyright (C) 2008-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor + + This file is part of gold. @@ -2470113,13 +2483262,13 @@ index 0000000..896191f +} diff --git a/gold/testsuite/tls_test_file2.cc b/gold/testsuite/tls_test_file2.cc new file mode 100644 -index 0000000..b02a7bd +index 0000000..86cee67 --- /dev/null +++ b/gold/testsuite/tls_test_file2.cc @@ -0,0 +1,30 @@ +// tls_test.cc -- test TLS variables for gold + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2470149,13 +2483298,13 @@ index 0000000..b02a7bd +__thread int o3; diff --git a/gold/testsuite/tls_test_main.cc b/gold/testsuite/tls_test_main.cc new file mode 100644 -index 0000000..d781a15 +index 0000000..42db36f --- /dev/null +++ b/gold/testsuite/tls_test_main.cc @@ -0,0 +1,173 @@ +// tls_test.cc -- test TLS variables for gold, main function + -+// Copyright 2006, 2007, 2008, 2011 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2470328,7 +2483477,7 @@ index 0000000..d781a15 +} diff --git a/gold/testsuite/two_file_shared.sh b/gold/testsuite/two_file_shared.sh new file mode 100755 -index 0000000..6240311 +index 0000000..84465f8 --- /dev/null +++ b/gold/testsuite/two_file_shared.sh @@ -0,0 +1,30 @@ @@ -2470336,7 +2483485,7 @@ index 0000000..6240311 + +# two_file_shared.sh -- check that debug info gets symbol addresses + -+# Copyright 2009 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# Written by Ian Lance Taylor . + +# This file is part of gold. @@ -2470364,13 +2483513,13 @@ index 0000000..6240311 +fi diff --git a/gold/testsuite/two_file_test.h b/gold/testsuite/two_file_test.h new file mode 100644 -index 0000000..d89f050 +index 0000000..617b8d2 --- /dev/null +++ b/gold/testsuite/two_file_test.h @@ -0,0 +1,78 @@ +// two_file_test.h -- a two file test case for gold, header file -*- C++ -*- + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2470448,13 +2483597,13 @@ index 0000000..d89f050 +extern const char* f18(int); diff --git a/gold/testsuite/two_file_test_1.cc b/gold/testsuite/two_file_test_1.cc new file mode 100644 -index 0000000..8b4c8ad +index 0000000..fdcb7d5 --- /dev/null +++ b/gold/testsuite/two_file_test_1.cc @@ -0,0 +1,238 @@ +// two_file_test_1.cc -- a two file test case for gold, file 1 of 2 + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2470692,13 +2483841,13 @@ index 0000000..8b4c8ad +} diff --git a/gold/testsuite/two_file_test_1_v1.cc b/gold/testsuite/two_file_test_1_v1.cc new file mode 100644 -index 0000000..2a23654 +index 0000000..2518479 --- /dev/null +++ b/gold/testsuite/two_file_test_1_v1.cc @@ -0,0 +1,236 @@ +// two_file_test_1_v1.cc -- a two file test case for gold, file 1 of 2 + -+// Copyright 2006, 2007, 2008, 2011 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2470934,14 +2484083,14 @@ index 0000000..2a23654 +} diff --git a/gold/testsuite/two_file_test_1b.cc b/gold/testsuite/two_file_test_1b.cc new file mode 100644 -index 0000000..8f6d4e6 +index 0000000..4083f0b --- /dev/null +++ b/gold/testsuite/two_file_test_1b.cc @@ -0,0 +1,41 @@ +// two_file_test_1b.cc -- supplementary file for a three-file test case +// for gold. + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2470981,14 +2484130,14 @@ index 0000000..8f6d4e6 +} diff --git a/gold/testsuite/two_file_test_1b_v1.cc b/gold/testsuite/two_file_test_1b_v1.cc new file mode 100644 -index 0000000..0adaf84 +index 0000000..3306e9c --- /dev/null +++ b/gold/testsuite/two_file_test_1b_v1.cc @@ -0,0 +1,46 @@ +// two_file_test_1b_v1.cc -- supplementary file for a three-file test case +// for gold. + -+// Copyright 2008, 2011 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2471033,13 +2484182,13 @@ index 0000000..0adaf84 +} diff --git a/gold/testsuite/two_file_test_2.cc b/gold/testsuite/two_file_test_2.cc new file mode 100644 -index 0000000..e1aeaf4 +index 0000000..e3818f9 --- /dev/null +++ b/gold/testsuite/two_file_test_2.cc @@ -0,0 +1,145 @@ +// two_file_test_2.cc -- a two file test case for gold, file 2 of 2 + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2471184,13 +2484333,13 @@ index 0000000..e1aeaf4 +} diff --git a/gold/testsuite/two_file_test_2_tls.cc b/gold/testsuite/two_file_test_2_tls.cc new file mode 100644 -index 0000000..6c74c69 +index 0000000..3f6dc0b --- /dev/null +++ b/gold/testsuite/two_file_test_2_tls.cc @@ -0,0 +1,147 @@ +// two_file_test_2_tls.cc -- a two file test case for gold, with a TLS symbol + -+// Copyright 2006, 2007, 2008, 2013 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2471337,13 +2484486,13 @@ index 0000000..6c74c69 +} diff --git a/gold/testsuite/two_file_test_2_v1.cc b/gold/testsuite/two_file_test_2_v1.cc new file mode 100644 -index 0000000..ea26c66 +index 0000000..664380b --- /dev/null +++ b/gold/testsuite/two_file_test_2_v1.cc @@ -0,0 +1,150 @@ +// two_file_test_2_v1.cc -- a two file test case for gold, file 2 of 2 + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2471493,13 +2484642,13 @@ index 0000000..ea26c66 +} diff --git a/gold/testsuite/two_file_test_main.cc b/gold/testsuite/two_file_test_main.cc new file mode 100644 -index 0000000..b7e3838 +index 0000000..6c1c52c --- /dev/null +++ b/gold/testsuite/two_file_test_main.cc @@ -0,0 +1,57 @@ +// two_file_test_main.cc -- a two file test case for gold, main function + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2471556,13 +2484705,13 @@ index 0000000..b7e3838 +} diff --git a/gold/testsuite/two_file_test_tls.cc b/gold/testsuite/two_file_test_tls.cc new file mode 100644 -index 0000000..d9a1c39 +index 0000000..5f450a4 --- /dev/null +++ b/gold/testsuite/two_file_test_tls.cc @@ -0,0 +1,60 @@ +// two_file_test_tls.cc -- a two file test case for gold, main function, with TLS + -+// Copyright 2006, 2007, 2008, 2013 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2471622,13 +2484771,13 @@ index 0000000..d9a1c39 +} diff --git a/gold/testsuite/undef_symbol.cc b/gold/testsuite/undef_symbol.cc new file mode 100644 -index 0000000..e35b2b2 +index 0000000..306f29a --- /dev/null +++ b/gold/testsuite/undef_symbol.cc @@ -0,0 +1,40 @@ +// undef_symbol.cc -- a test case for undefined references + -+// Copyright 2007, 2008, 2013 Free Software Foundation, Inc. ++// Copyright (C) 2007-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2471668,7 +2484817,7 @@ index 0000000..e35b2b2 +static Foo foo; diff --git a/gold/testsuite/undef_symbol.sh b/gold/testsuite/undef_symbol.sh new file mode 100755 -index 0000000..b689edc +index 0000000..4f6308f --- /dev/null +++ b/gold/testsuite/undef_symbol.sh @@ -0,0 +1,45 @@ @@ -2471676,7 +2484825,7 @@ index 0000000..b689edc + +# undef_symbol.sh -- a test case for undefined symbols in shared libraries + -+# Copyright 2007, 2008 Free Software Foundation, Inc. ++# Copyright (C) 2007-2014 Free Software Foundation, Inc. +# Written by Ian Lance Taylor . + +# This file is part of gold. @@ -2471719,13 +2484868,13 @@ index 0000000..b689edc +exit 0 diff --git a/gold/testsuite/undef_symbol_main.cc b/gold/testsuite/undef_symbol_main.cc new file mode 100644 -index 0000000..2c21044 +index 0000000..537eed8 --- /dev/null +++ b/gold/testsuite/undef_symbol_main.cc @@ -0,0 +1,29 @@ +// undef_symbol_1.cc -- a test case for undefined references + -+// Copyright 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2007-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2471754,13 +2484903,13 @@ index 0000000..2c21044 +} diff --git a/gold/testsuite/ver_matching_def.cc b/gold/testsuite/ver_matching_def.cc new file mode 100644 -index 0000000..b654dff +index 0000000..ee2edc3 --- /dev/null +++ b/gold/testsuite/ver_matching_def.cc @@ -0,0 +1,73 @@ +// ver_matching_def.cc - test matching rules in version_script.map + -+// Copyright 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2007-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2471833,7 +2484982,7 @@ index 0000000..b654dff +}; diff --git a/gold/testsuite/ver_matching_test.sh b/gold/testsuite/ver_matching_test.sh new file mode 100755 -index 0000000..4880efa +index 0000000..9c7722e --- /dev/null +++ b/gold/testsuite/ver_matching_test.sh @@ -0,0 +1,88 @@ @@ -2471841,7 +2484990,7 @@ index 0000000..4880efa + +# ver_matching_test.sh -- a test case for version script matching + -+# Copyright 2008, 2010 Free Software Foundation, Inc. ++# Copyright (C) 2008-2014 Free Software Foundation, Inc. +# Written by Ian Lance Taylor . + +# This file is part of gold. @@ -2471927,13 +2485076,13 @@ index 0000000..4880efa +exit 0 diff --git a/gold/testsuite/ver_test.h b/gold/testsuite/ver_test.h new file mode 100644 -index 0000000..0b1aea8 +index 0000000..62a4b37 --- /dev/null +++ b/gold/testsuite/ver_test.h @@ -0,0 +1,43 @@ +// ver_test.h -- a test case for gold + -+// Copyright 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2007-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2471976,13 +2485125,13 @@ index 0000000..0b1aea8 +} diff --git a/gold/testsuite/ver_test_1.cc b/gold/testsuite/ver_test_1.cc new file mode 100644 -index 0000000..42a18ec +index 0000000..6336234 --- /dev/null +++ b/gold/testsuite/ver_test_1.cc @@ -0,0 +1,33 @@ +// ver_test_1.cc -- a test case for gold + -+// Copyright 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2007-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2472015,7 +2485164,7 @@ index 0000000..42a18ec +} diff --git a/gold/testsuite/ver_test_1.sh b/gold/testsuite/ver_test_1.sh new file mode 100755 -index 0000000..edf7351 +index 0000000..63d5d49 --- /dev/null +++ b/gold/testsuite/ver_test_1.sh @@ -0,0 +1,30 @@ @@ -2472023,7 +2485172,7 @@ index 0000000..edf7351 + +# ver_test_1.sh -- check that protected symbols are local + -+# Copyright 2009 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# Written by Ian Lance Taylor . + +# This file is part of gold. @@ -2472051,13 +2485200,13 @@ index 0000000..edf7351 +fi diff --git a/gold/testsuite/ver_test_10.script b/gold/testsuite/ver_test_10.script new file mode 100644 -index 0000000..fa9f175 +index 0000000..720220c --- /dev/null +++ b/gold/testsuite/ver_test_10.script @@ -0,0 +1,30 @@ +## ver_test_10.script -- a test case for gold + -+## Copyright 2008 Free Software Foundation, Inc. ++## Copyright (C) 2008-2014 Free Software Foundation, Inc. +## Written by Ian Lance Taylor . + +## This file is part of gold. @@ -2472087,7 +2485236,7 @@ index 0000000..fa9f175 +}; diff --git a/gold/testsuite/ver_test_10.sh b/gold/testsuite/ver_test_10.sh new file mode 100755 -index 0000000..68138a6 +index 0000000..11044f3 --- /dev/null +++ b/gold/testsuite/ver_test_10.sh @@ -0,0 +1,44 @@ @@ -2472095,7 +2485244,7 @@ index 0000000..68138a6 + +# ver_test_10.sh -- test global/local symbols + -+# Copyright 2008 Free Software Foundation, Inc. ++# Copyright (C) 2008-2014 Free Software Foundation, Inc. +# Written by Ian Lance Taylor . + +# This file is part of gold. @@ -2472137,13 +2485286,13 @@ index 0000000..68138a6 +exit 0 diff --git a/gold/testsuite/ver_test_2.cc b/gold/testsuite/ver_test_2.cc new file mode 100644 -index 0000000..b81e62e +index 0000000..bf230d3 --- /dev/null +++ b/gold/testsuite/ver_test_2.cc @@ -0,0 +1,40 @@ +// ver_test_2.cc -- a test case for gold + -+// Copyright 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2007-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2472183,13 +2485332,13 @@ index 0000000..b81e62e +} diff --git a/gold/testsuite/ver_test_2.script b/gold/testsuite/ver_test_2.script new file mode 100644 -index 0000000..15329d7 +index 0000000..bd62fc1 --- /dev/null +++ b/gold/testsuite/ver_test_2.script @@ -0,0 +1,31 @@ +## ver_test_2.script -- a test case for gold + -+## Copyright 2007, 2008 Free Software Foundation, Inc. ++## Copyright (C) 2007-2014 Free Software Foundation, Inc. +## Written by Cary Coutant . + +## This file is part of gold. @@ -2472220,7 +2485369,7 @@ index 0000000..15329d7 +} VER1; diff --git a/gold/testsuite/ver_test_2.sh b/gold/testsuite/ver_test_2.sh new file mode 100755 -index 0000000..0bd0f90 +index 0000000..bd973bc --- /dev/null +++ b/gold/testsuite/ver_test_2.sh @@ -0,0 +1,45 @@ @@ -2472228,7 +2485377,7 @@ index 0000000..0bd0f90 + +# ver_test_2.sh -- test that symbol has correct version + -+# Copyright 2008 Free Software Foundation, Inc. ++# Copyright (C) 2008-2014 Free Software Foundation, Inc. +# Written by Ian Lance Taylor . + +# This file is part of gold. @@ -2472271,13 +2485420,13 @@ index 0000000..0bd0f90 +exit 0 diff --git a/gold/testsuite/ver_test_3.cc b/gold/testsuite/ver_test_3.cc new file mode 100644 -index 0000000..022a888 +index 0000000..ec05792 --- /dev/null +++ b/gold/testsuite/ver_test_3.cc @@ -0,0 +1,33 @@ +// ver_test_3.cc -- a test case for gold + -+// Copyright 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2007-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2472310,13 +2485459,13 @@ index 0000000..022a888 +} diff --git a/gold/testsuite/ver_test_4.cc b/gold/testsuite/ver_test_4.cc new file mode 100644 -index 0000000..404dfbc +index 0000000..ef06e2c --- /dev/null +++ b/gold/testsuite/ver_test_4.cc @@ -0,0 +1,64 @@ +// ver_test_4.cc -- a test case for gold + -+// Copyright 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2007-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2472380,13 +2485529,13 @@ index 0000000..404dfbc +} diff --git a/gold/testsuite/ver_test_4.script b/gold/testsuite/ver_test_4.script new file mode 100644 -index 0000000..e97c74e +index 0000000..071e3f6 --- /dev/null +++ b/gold/testsuite/ver_test_4.script @@ -0,0 +1,35 @@ +## ver_test_4.script -- a test case for gold + -+## Copyright 2007, 2008 Free Software Foundation, Inc. ++## Copyright (C) 2007-2014 Free Software Foundation, Inc. +## Written by Cary Coutant . + +## This file is part of gold. @@ -2472421,7 +2485570,7 @@ index 0000000..e97c74e + diff --git a/gold/testsuite/ver_test_4.sh b/gold/testsuite/ver_test_4.sh new file mode 100755 -index 0000000..3466a5d +index 0000000..f125f2b --- /dev/null +++ b/gold/testsuite/ver_test_4.sh @@ -0,0 +1,44 @@ @@ -2472429,7 +2485578,7 @@ index 0000000..3466a5d + +# ver_test_4.sh -- test that version symbol is visible. + -+# Copyright 2008 Free Software Foundation, Inc. ++# Copyright (C) 2008-2014 Free Software Foundation, Inc. +# Written by Ian Lance Taylor . + +# This file is part of gold. @@ -2472471,13 +2485620,13 @@ index 0000000..3466a5d +exit 0 diff --git a/gold/testsuite/ver_test_5.cc b/gold/testsuite/ver_test_5.cc new file mode 100644 -index 0000000..cffeae6 +index 0000000..d861d48 --- /dev/null +++ b/gold/testsuite/ver_test_5.cc @@ -0,0 +1,29 @@ +// ver_test_5.cc -- a test case for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor + +// This file is part of gold. @@ -2472506,13 +2485655,13 @@ index 0000000..cffeae6 +} diff --git a/gold/testsuite/ver_test_5.script b/gold/testsuite/ver_test_5.script new file mode 100644 -index 0000000..028cdd6 +index 0000000..950adc8 --- /dev/null +++ b/gold/testsuite/ver_test_5.script @@ -0,0 +1,31 @@ +## ver_test_5.script -- a test case for gold + -+## Copyright 2008 Free Software Foundation, Inc. ++## Copyright (C) 2008-2014 Free Software Foundation, Inc. +## Written by Ian Lance Taylor + +## This file is part of gold. @@ -2472543,7 +2485692,7 @@ index 0000000..028cdd6 +}; diff --git a/gold/testsuite/ver_test_5.sh b/gold/testsuite/ver_test_5.sh new file mode 100755 -index 0000000..2eacb45 +index 0000000..0c9b024 --- /dev/null +++ b/gold/testsuite/ver_test_5.sh @@ -0,0 +1,44 @@ @@ -2472551,7 +2485700,7 @@ index 0000000..2eacb45 + +# ver_test_5.sh -- test that symbol has correct version + -+# Copyright 2008 Free Software Foundation, Inc. ++# Copyright (C) 2008-2014 Free Software Foundation, Inc. +# Written by Ian Lance Taylor . + +# This file is part of gold. @@ -2472593,13 +2485742,13 @@ index 0000000..2eacb45 +exit 0 diff --git a/gold/testsuite/ver_test_6.c b/gold/testsuite/ver_test_6.c new file mode 100644 -index 0000000..44b483f +index 0000000..fb96c77 --- /dev/null +++ b/gold/testsuite/ver_test_6.c @@ -0,0 +1,35 @@ +/* ver_test_6.c -- test common symbol with shared library version + -+ Copyright 2008 Free Software Foundation, Inc. ++ Copyright (C) 2008-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor + + This file is part of gold. @@ -2472634,13 +2485783,13 @@ index 0000000..44b483f +} diff --git a/gold/testsuite/ver_test_7.cc b/gold/testsuite/ver_test_7.cc new file mode 100644 -index 0000000..d602a48 +index 0000000..2badcea --- /dev/null +++ b/gold/testsuite/ver_test_7.cc @@ -0,0 +1,37 @@ +// ver_test_7.cc -- test weak duplicate symbol with version + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor + +// This file is part of gold. @@ -2472677,7 +2485826,7 @@ index 0000000..d602a48 +} diff --git a/gold/testsuite/ver_test_7.sh b/gold/testsuite/ver_test_7.sh new file mode 100755 -index 0000000..04d35fc +index 0000000..f0fe8f6 --- /dev/null +++ b/gold/testsuite/ver_test_7.sh @@ -0,0 +1,44 @@ @@ -2472685,7 +2485834,7 @@ index 0000000..04d35fc + +# ver_test_7.sh -- test that symbol has correct version + -+# Copyright 2008 Free Software Foundation, Inc. ++# Copyright (C) 2008-2014 Free Software Foundation, Inc. +# Written by Ian Lance Taylor . + +# This file is part of gold. @@ -2472727,13 +2485876,13 @@ index 0000000..04d35fc +exit 0 diff --git a/gold/testsuite/ver_test_8.script b/gold/testsuite/ver_test_8.script new file mode 100644 -index 0000000..b5bfc3f +index 0000000..9e48e38 --- /dev/null +++ b/gold/testsuite/ver_test_8.script @@ -0,0 +1,26 @@ +## ver_test_8.script -- a test case for gold + -+## Copyright 2008 Free Software Foundation, Inc. ++## Copyright (C) 2008-2014 Free Software Foundation, Inc. +## Written by Ian Lance Taylor + +## This file is part of gold. @@ -2472759,13 +2485908,13 @@ index 0000000..b5bfc3f +}; diff --git a/gold/testsuite/ver_test_9.cc b/gold/testsuite/ver_test_9.cc new file mode 100644 -index 0000000..5d06d4e +index 0000000..d0cc4e7 --- /dev/null +++ b/gold/testsuite/ver_test_9.cc @@ -0,0 +1,50 @@ +// ver_test_9.cc -- a test case for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2472815,13 +2485964,13 @@ index 0000000..5d06d4e +} diff --git a/gold/testsuite/ver_test_main.cc b/gold/testsuite/ver_test_main.cc new file mode 100644 -index 0000000..f8a7b75 +index 0000000..c24beb4 --- /dev/null +++ b/gold/testsuite/ver_test_main.cc @@ -0,0 +1,74 @@ +// ver_test_main.cc -- a test case for gold + -+// Copyright 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2007-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2472895,13 +2486044,13 @@ index 0000000..f8a7b75 +} diff --git a/gold/testsuite/ver_test_main_2.cc b/gold/testsuite/ver_test_main_2.cc new file mode 100644 -index 0000000..1599e0f +index 0000000..9a03191 --- /dev/null +++ b/gold/testsuite/ver_test_main_2.cc @@ -0,0 +1,32 @@ +// ver_test_main_2.cc -- a test case for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2472987,13 +2486136,13 @@ index 0000000..1911631 +}; diff --git a/gold/testsuite/weak_alias_test_1.cc b/gold/testsuite/weak_alias_test_1.cc new file mode 100644 -index 0000000..0ad9265 +index 0000000..67c709d --- /dev/null +++ b/gold/testsuite/weak_alias_test_1.cc @@ -0,0 +1,52 @@ +// weak_alias_test_1.cc -- test weak aliases for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2473045,13 +2486194,13 @@ index 0000000..0ad9265 +int Strong_Symbol = 101; diff --git a/gold/testsuite/weak_alias_test_2.cc b/gold/testsuite/weak_alias_test_2.cc new file mode 100644 -index 0000000..8294525 +index 0000000..5933314 --- /dev/null +++ b/gold/testsuite/weak_alias_test_2.cc @@ -0,0 +1,41 @@ +// weak_alias_test_2.cc -- test weak aliases for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2473092,13 +2486241,13 @@ index 0000000..8294525 +extern int weak_aliased_4 __attribute__ ((weak, alias ("strong_aliased_4"))); diff --git a/gold/testsuite/weak_alias_test_3.cc b/gold/testsuite/weak_alias_test_3.cc new file mode 100644 -index 0000000..99152e2 +index 0000000..ef7b252 --- /dev/null +++ b/gold/testsuite/weak_alias_test_3.cc @@ -0,0 +1,26 @@ +// weak_alias_test_3.cc -- test weak aliases for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2473124,13 +2486273,13 @@ index 0000000..99152e2 +int weak_symbol = 4; diff --git a/gold/testsuite/weak_alias_test_4.cc b/gold/testsuite/weak_alias_test_4.cc new file mode 100644 -index 0000000..714c6d6 +index 0000000..04a0098 --- /dev/null +++ b/gold/testsuite/weak_alias_test_4.cc @@ -0,0 +1,68 @@ +// weak_alias_test_4.cc -- test weak aliases for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2473198,13 +2486347,13 @@ index 0000000..714c6d6 +} diff --git a/gold/testsuite/weak_alias_test_5.cc b/gold/testsuite/weak_alias_test_5.cc new file mode 100644 -index 0000000..df48092 +index 0000000..c3e746e --- /dev/null +++ b/gold/testsuite/weak_alias_test_5.cc @@ -0,0 +1,39 @@ +// weak_alias_test_5.cc -- test versioned weak aliases for gold + -+// Copyright 2011 Free Software Foundation, Inc. ++// Copyright (C) 2011-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2473243,13 +2486392,13 @@ index 0000000..df48092 +} diff --git a/gold/testsuite/weak_alias_test_main.cc b/gold/testsuite/weak_alias_test_main.cc new file mode 100644 -index 0000000..e3f8620 +index 0000000..1b4778d --- /dev/null +++ b/gold/testsuite/weak_alias_test_main.cc @@ -0,0 +1,80 @@ +// weak_alias_test_main.cc -- test weak aliases for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2473329,7 +2486478,7 @@ index 0000000..e3f8620 +} diff --git a/gold/testsuite/weak_plt.sh b/gold/testsuite/weak_plt.sh new file mode 100755 -index 0000000..6c419b8 +index 0000000..2098011 --- /dev/null +++ b/gold/testsuite/weak_plt.sh @@ -0,0 +1,28 @@ @@ -2473337,7 +2486486,7 @@ index 0000000..6c419b8 + +# weak_plt.sh -- test calling a weak undefined function. + -+# Copyright 2008 Free Software Foundation, Inc. ++# Copyright (C) 2008-2014 Free Software Foundation, Inc. +# Written by Ian Lance Taylor . + +# This file is part of gold. @@ -2473363,13 +2486512,13 @@ index 0000000..6c419b8 +LD_PRELOAD=./weak_plt_shared.so ./weak_plt diff --git a/gold/testsuite/weak_plt_main.cc b/gold/testsuite/weak_plt_main.cc new file mode 100644 -index 0000000..33cb35e +index 0000000..39fe46f --- /dev/null +++ b/gold/testsuite/weak_plt_main.cc @@ -0,0 +1,33 @@ +// weak_plt_main.cc -- test call to weak undefined function for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2473402,13 +2486551,13 @@ index 0000000..33cb35e +} diff --git a/gold/testsuite/weak_plt_shared.cc b/gold/testsuite/weak_plt_shared.cc new file mode 100644 -index 0000000..8d82005 +index 0000000..0275a2e --- /dev/null +++ b/gold/testsuite/weak_plt_shared.cc @@ -0,0 +1,29 @@ +// weak_plt_shared.cc -- test call to weak undefined function for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2473437,13 +2486586,13 @@ index 0000000..8d82005 +} diff --git a/gold/testsuite/weak_test.cc b/gold/testsuite/weak_test.cc new file mode 100644 -index 0000000..c14a688 +index 0000000..67c4438 --- /dev/null +++ b/gold/testsuite/weak_test.cc @@ -0,0 +1,47 @@ +// weak_test.cc -- test handling of weak symbols for gold + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2473490,13 +2486639,13 @@ index 0000000..c14a688 +} diff --git a/gold/testsuite/weak_undef.h b/gold/testsuite/weak_undef.h new file mode 100644 -index 0000000..17d5f02 +index 0000000..796dca5 --- /dev/null +++ b/gold/testsuite/weak_undef.h @@ -0,0 +1,25 @@ +// weak_undef.h -- test handling of weak undefined symbols for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2473521,13 +2486670,13 @@ index 0000000..17d5f02 +extern int t3(); diff --git a/gold/testsuite/weak_undef_file1.cc b/gold/testsuite/weak_undef_file1.cc new file mode 100644 -index 0000000..fd28870 +index 0000000..60cf5c3 --- /dev/null +++ b/gold/testsuite/weak_undef_file1.cc @@ -0,0 +1,75 @@ +// weak_undef_file1.cc -- test handling of weak undefined symbols for gold + -+// Copyright 2008, 2010 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2473602,13 +2486751,13 @@ index 0000000..fd28870 +} diff --git a/gold/testsuite/weak_undef_file2.cc b/gold/testsuite/weak_undef_file2.cc new file mode 100644 -index 0000000..33701b2 +index 0000000..7ceff00 --- /dev/null +++ b/gold/testsuite/weak_undef_file2.cc @@ -0,0 +1,70 @@ +// weak_undef_file2.cc -- test handling of weak undefined symbols for gold + -+// Copyright 2008, 2010 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2473676,15 +2486825,85 @@ index 0000000..33701b2 +{ + return (v3 == NULL) ? -1 : *v3; +} +diff --git a/gold/testsuite/weak_undef_file3.cc b/gold/testsuite/weak_undef_file3.cc +new file mode 100644 +index 0000000..1597447 +--- /dev/null ++++ b/gold/testsuite/weak_undef_file3.cc +@@ -0,0 +1,29 @@ ++// weak_undef_file3.cc -- test handling of weak undefined symbols for gold ++ ++// Copyright (C) 2014 Free Software Foundation, Inc. ++// Written by Cary Coutant . ++ ++// This file is part of gold. ++ ++// This program is free software; you can redistribute it and/or modify ++// it under the terms of the GNU General Public License as published by ++// the Free Software Foundation; either version 3 of the License, or ++// (at your option) any later version. ++ ++// This program is distributed in the hope that it will be useful, ++// but WITHOUT ANY WARRANTY; without even the implied warranty of ++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++// GNU General Public License for more details. ++ ++// You should have received a copy of the GNU General Public License ++// along with this program; if not, write to the Free Software ++// Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ++// MA 02110-1301, USA. ++ ++// This file tests that we correctly deal with weak undefined symbols ++// when searching archive libraries. If we have a weak undefined symbol, ++// it should not cause us to link an archive library member that defines ++// that symbol. However, if the symbol is also listed in a -u option on ++// the command line, it should cause the archive member to be linked. ++ ++int weak_undef_1 = 1; +diff --git a/gold/testsuite/weak_undef_file4.cc b/gold/testsuite/weak_undef_file4.cc +new file mode 100644 +index 0000000..a82a49f +--- /dev/null ++++ b/gold/testsuite/weak_undef_file4.cc +@@ -0,0 +1,29 @@ ++// weak_undef_file4.cc -- test handling of weak undefined symbols for gold ++ ++// Copyright (C) 2014 Free Software Foundation, Inc. ++// Written by Cary Coutant . ++ ++// This file is part of gold. ++ ++// This program is free software; you can redistribute it and/or modify ++// it under the terms of the GNU General Public License as published by ++// the Free Software Foundation; either version 3 of the License, or ++// (at your option) any later version. ++ ++// This program is distributed in the hope that it will be useful, ++// but WITHOUT ANY WARRANTY; without even the implied warranty of ++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++// GNU General Public License for more details. ++ ++// You should have received a copy of the GNU General Public License ++// along with this program; if not, write to the Free Software ++// Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ++// MA 02110-1301, USA. ++ ++// This file tests that we correctly deal with weak undefined symbols ++// when searching archive libraries. If we have a weak undefined symbol, ++// it should not cause us to link an archive library member that defines ++// that symbol. However, if the symbol is also listed in a -u option on ++// the command line, it should cause the archive member to be linked. ++ ++int weak_undef_2 = 2; diff --git a/gold/testsuite/weak_undef_test.cc b/gold/testsuite/weak_undef_test.cc new file mode 100644 -index 0000000..880d5cd +index 0000000..16277a2 --- /dev/null +++ b/gold/testsuite/weak_undef_test.cc @@ -0,0 +1,106 @@ +// weak_undef_test.cc -- test handling of weak undefined symbols for gold + -+// Copyright 2008 Free Software Foundation, Inc. ++// Copyright (C) 2008-2014 Free Software Foundation, Inc. +// Written by Cary Coutant . + +// This file is part of gold. @@ -2473788,15 +2487007,100 @@ index 0000000..880d5cd + + return status; +} +diff --git a/gold/testsuite/weak_undef_test_2.cc b/gold/testsuite/weak_undef_test_2.cc +new file mode 100644 +index 0000000..549bd3f +--- /dev/null ++++ b/gold/testsuite/weak_undef_test_2.cc +@@ -0,0 +1,79 @@ ++// weak_undef_test_2.cc -- test handling of weak undefined symbols for gold ++ ++// Copyright (C) 2014 Free Software Foundation, Inc. ++// Written by Cary Coutant . ++ ++// This file is part of gold. ++ ++// This program is free software; you can redistribute it and/or modify ++// it under the terms of the GNU General Public License as published by ++// the Free Software Foundation; either version 3 of the License, or ++// (at your option) any later version. ++ ++// This program is distributed in the hope that it will be useful, ++// but WITHOUT ANY WARRANTY; without even the implied warranty of ++// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++// GNU General Public License for more details. ++ ++// You should have received a copy of the GNU General Public License ++// along with this program; if not, write to the Free Software ++// Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ++// MA 02110-1301, USA. ++ ++// This file tests that we correctly deal with weak undefined symbols ++// when searching archive libraries. If we have a weak undefined symbol, ++// it should not cause us to link an archive library member that defines ++// that symbol. However, if the symbol is also listed in a -u option on ++// the command line, it should cause the archive member to be linked. ++ ++ ++#include ++ ++// This symbol is defined in weak_undef_file3.cc, but we should ++// not load it from the library. ++extern int weak_undef_1 __attribute__ ((weak)); ++ ++// This symbol is defined in weak_undef_file4.cc, but is also ++// listed in a -u option on the link command, so we should ++// load it from the library. ++extern int weak_undef_2 __attribute__ ((weak)); ++ ++int *p1 = &weak_undef_1; ++ ++int *p2 = &weak_undef_2; ++ ++int ++main() ++{ ++ int status = 0; ++ ++ if (&weak_undef_1 != NULL) ++ { ++ fprintf(stderr, "FAILED weak undef test 1: %s\n", ++ "&weak_undef_1 is not NULL"); ++ status = 1; ++ } ++ ++ if (&weak_undef_2 == NULL) ++ { ++ fprintf(stderr, "FAILED weak undef test 2: %s\n", ++ "&weak_undef_2 is NULL"); ++ status = 1; ++ } ++ ++ if (p1 != NULL) ++ { ++ fprintf(stderr, "FAILED weak undef test 3: %s\n", ++ "p1 is not NULL"); ++ status = 1; ++ } ++ ++ if (p2 == NULL) ++ { ++ fprintf(stderr, "FAILED weak undef test 4: %s\n", ++ "p2 is NULL"); ++ status = 1; ++ } ++ ++ return status; ++} diff --git a/gold/tilegx.cc b/gold/tilegx.cc new file mode 100644 -index 0000000..576a28c +index 0000000..1a14dea --- /dev/null +++ b/gold/tilegx.cc -@@ -0,0 +1,4924 @@ +@@ -0,0 +1,4926 @@ +// tilegx.cc -- tilegx target support for gold. + -+// Copyright 2012, 2013 Free Software Foundation, Inc. ++// Copyright (C) 2012-2014 Free Software Foundation, Inc. +// Written by Jiong Wang (jiwang@tilera.com) + +// This file is part of gold. @@ -2477554,7 +2490858,8 @@ index 0000000..576a28c + // Make a dynamic relocation if necessary. + if (gsym->needs_dynamic_reloc(Scan::get_reference_flags(r_type))) + { -+ if (gsym->may_need_copy_reloc()) ++ if (!parameters->options().output_is_position_independent() ++ && gsym->may_need_copy_reloc()) + { + target->copy_reloc(symtab, layout, object, + data_shndx, output_section, gsym, reloc); @@ -2477628,7 +2490933,8 @@ index 0000000..576a28c + // Make a dynamic relocation if necessary. + if (gsym->needs_dynamic_reloc(Scan::get_reference_flags(r_type))) + { -+ if (gsym->may_need_copy_reloc()) ++ if (parameters->options().output_is_executable() ++ && gsym->may_need_copy_reloc()) + { + target->copy_reloc(symtab, layout, object, + data_shndx, output_section, gsym, reloc); @@ -2478720,13 +2492026,13 @@ index 0000000..576a28c +} // End anonymous namespace. diff --git a/gold/timer.cc b/gold/timer.cc new file mode 100644 -index 0000000..f3a1c91 +index 0000000..671439f --- /dev/null +++ b/gold/timer.cc @@ -0,0 +1,133 @@ +// timer.cc -- helper class for time accounting + -+// Copyright 2009, 2010 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Rafael Avila de Espindola . + +// This file is part of gold. @@ -2478859,13 +2492165,13 @@ index 0000000..f3a1c91 +} diff --git a/gold/timer.h b/gold/timer.h new file mode 100644 -index 0000000..4f986ca +index 0000000..fca5b12 --- /dev/null +++ b/gold/timer.h @@ -0,0 +1,80 @@ +// timer.h -- helper class for time accounting -*- C++ -*- + -+// Copyright 2009, 2010 Free Software Foundation, Inc. ++// Copyright (C) 2009-2014 Free Software Foundation, Inc. +// Written by Rafael Avila de Espindola . + +// This file is part of gold. @@ -2478945,13 +2492251,13 @@ index 0000000..4f986ca +#endif diff --git a/gold/tls.h b/gold/tls.h new file mode 100644 -index 0000000..5b5cb6e +index 0000000..1a287ad --- /dev/null +++ b/gold/tls.h @@ -0,0 +1,81 @@ +// tls.h -- Thread-Local Storage utility routines for gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2479032,13 +2492338,13 @@ index 0000000..5b5cb6e +#endif // !defined(GOLD_TLS_H) diff --git a/gold/token.h b/gold/token.h new file mode 100644 -index 0000000..5cf64a0 +index 0000000..47091cb --- /dev/null +++ b/gold/token.h @@ -0,0 +1,335 @@ +// token.h -- lock tokens for gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008, 2010 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2479373,14 +2492679,13 @@ index 0000000..5cf64a0 +#endif // !defined(GOLD_TOKEN_H) diff --git a/gold/version.cc b/gold/version.cc new file mode 100644 -index 0000000..37977e5 +index 0000000..2369541 --- /dev/null +++ b/gold/version.cc -@@ -0,0 +1,82 @@ +@@ -0,0 +1,81 @@ +// version.c -- print gold version information + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 -+// Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2479442,7 +2492747,7 @@ index 0000000..37977e5 + if (!print_short) + { + // This output is intended to follow the GNU standards. -+ printf(_("Copyright 2013 Free Software Foundation, Inc.\n")); ++ printf(_("Copyright (C) 2014 Free Software Foundation, Inc.\n")); + printf(_("\ +This program is free software; you may redistribute it under the terms of\n\ +the GNU General Public License version 3 or (at your option) a later version.\n\ @@ -2479461,13 +2492766,13 @@ index 0000000..37977e5 +} // End namespace gold. diff --git a/gold/workqueue-internal.h b/gold/workqueue-internal.h new file mode 100644 -index 0000000..764dc91 +index 0000000..f27d075 --- /dev/null +++ b/gold/workqueue-internal.h @@ -0,0 +1,109 @@ +// workqueue-internal.h -- internal work queue header for gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2479576,13 +2492881,13 @@ index 0000000..764dc91 +#endif // !defined(GOLD_WORKQUEUE_INTERNAL_H) diff --git a/gold/workqueue-threads.cc b/gold/workqueue-threads.cc new file mode 100644 -index 0000000..de2ce5b +index 0000000..41f0543 --- /dev/null +++ b/gold/workqueue-threads.cc @@ -0,0 +1,199 @@ +// workqueue-threads.cc -- the threaded workqueue for gold + -+// Copyright 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2007-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2479781,13 +2493086,13 @@ index 0000000..de2ce5b +#endif // defined(ENABLE_THREADS) diff --git a/gold/workqueue.cc b/gold/workqueue.cc new file mode 100644 -index 0000000..e78e86b +index 0000000..2d5684e --- /dev/null +++ b/gold/workqueue.cc @@ -0,0 +1,521 @@ +// workqueue.cc -- the workqueue for gold + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2480308,13 +2493613,13 @@ index 0000000..e78e86b +} // End namespace gold. diff --git a/gold/workqueue.h b/gold/workqueue.h new file mode 100644 -index 0000000..424b5e7 +index 0000000..d62071e --- /dev/null +++ b/gold/workqueue.h @@ -0,0 +1,295 @@ +// workqueue.h -- the work queue for gold -*- C++ -*- + -+// Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2480609,14 +2493914,13 @@ index 0000000..424b5e7 +#endif // !defined(GOLD_WORKQUEUE_H) diff --git a/gold/x86_64.cc b/gold/x86_64.cc new file mode 100644 -index 0000000..a0c4fce +index 0000000..f58c843 --- /dev/null +++ b/gold/x86_64.cc -@@ -0,0 +1,4865 @@ +@@ -0,0 +1,4910 @@ +// x86_64.cc -- x86_64 target support for gold. + -+// Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 -+// Free Software Foundation, Inc. ++// Copyright (C) 2006-2014 Free Software Foundation, Inc. +// Written by Ian Lance Taylor . + +// This file is part of gold. @@ -2480664,6 +2493968,37 @@ index 0000000..a0c4fce + +using namespace gold; + ++// A class to handle the .got.plt section. ++ ++class Output_data_got_plt_x86_64 : public Output_section_data_build ++{ ++ public: ++ Output_data_got_plt_x86_64(Layout* layout) ++ : Output_section_data_build(8), ++ layout_(layout) ++ { } ++ ++ Output_data_got_plt_x86_64(Layout* layout, off_t data_size) ++ : Output_section_data_build(data_size, 8), ++ layout_(layout) ++ { } ++ ++ protected: ++ // Write out the PLT data. ++ void ++ do_write(Output_file*); ++ ++ // Write to a map file. ++ void ++ do_print_to_mapfile(Mapfile* mapfile) const ++ { mapfile->print_output_data(this, "** GOT PLT"); } ++ ++ private: ++ // A pointer to the Layout class, so that we can find the .dynamic ++ // section when we write out the GOT PLT section. ++ Layout* layout_; ++}; ++ +// A class to handle the PLT data. +// This is an abstract base class that handles most of the linker details +// but does not know the actual contents of PLT entries. The derived @@ -2480677,9 +2494012,9 @@ index 0000000..a0c4fce + + Output_data_plt_x86_64(Layout* layout, uint64_t addralign, + Output_data_got<64, false>* got, -+ Output_data_space* got_plt, ++ Output_data_got_plt_x86_64* got_plt, + Output_data_space* got_irelative) -+ : Output_section_data(addralign), layout_(layout), tlsdesc_rel_(NULL), ++ : Output_section_data(addralign), tlsdesc_rel_(NULL), + irelative_rel_(NULL), got_(got), got_plt_(got_plt), + got_irelative_(got_irelative), count_(0), irelative_count_(0), + tlsdesc_got_offset_(-1U), free_list_() @@ -2480687,12 +2494022,12 @@ index 0000000..a0c4fce + + Output_data_plt_x86_64(Layout* layout, uint64_t plt_entry_size, + Output_data_got<64, false>* got, -+ Output_data_space* got_plt, ++ Output_data_got_plt_x86_64* got_plt, + Output_data_space* got_irelative, + unsigned int plt_count) + : Output_section_data((plt_count + 1) * plt_entry_size, + plt_entry_size, false), -+ layout_(layout), tlsdesc_rel_(NULL), irelative_rel_(NULL), got_(got), ++ tlsdesc_rel_(NULL), irelative_rel_(NULL), got_(got), + got_plt_(got_plt), got_irelative_(got_irelative), count_(plt_count), + irelative_count_(0), tlsdesc_got_offset_(-1U), free_list_() + { @@ -2480884,9 +2494219,6 @@ index 0000000..a0c4fce + void + do_write(Output_file*); + -+ // A pointer to the Layout class, so that we can find the .dynamic -+ // section when we write out the GOT PLT section. -+ Layout* layout_; + // The reloc section. + Reloc_section* rel_; + // The TLSDESC relocs, if necessary. These must follow the regular @@ -2480898,7 +2494230,7 @@ index 0000000..a0c4fce + // The .got section. + Output_data_got<64, false>* got_; + // The .got.plt section. -+ Output_data_space* got_plt_; ++ Output_data_got_plt_x86_64* got_plt_; + // The part of the .got.plt section used for IRELATIVE relocs. + Output_data_space* got_irelative_; + // The number of PLT entries. @@ -2480919,7 +2494251,7 @@ index 0000000..a0c4fce + public: + Output_data_plt_x86_64_standard(Layout* layout, + Output_data_got<64, false>* got, -+ Output_data_space* got_plt, ++ Output_data_got_plt_x86_64* got_plt, + Output_data_space* got_irelative) + : Output_data_plt_x86_64(layout, plt_entry_size, + got, got_plt, got_irelative) @@ -2480927,7 +2494259,7 @@ index 0000000..a0c4fce + + Output_data_plt_x86_64_standard(Layout* layout, + Output_data_got<64, false>* got, -+ Output_data_space* got_plt, ++ Output_data_got_plt_x86_64* got_plt, + Output_data_space* got_irelative, + unsigned int plt_count) + : Output_data_plt_x86_64(layout, plt_entry_size, @@ -2481234,7 +2494566,7 @@ index 0000000..a0c4fce + Output_data_plt_x86_64* + make_data_plt(Layout* layout, + Output_data_got<64, false>* got, -+ Output_data_space* got_plt, ++ Output_data_got_plt_x86_64* got_plt, + Output_data_space* got_irelative) + { + return this->do_make_data_plt(layout, got, got_plt, got_irelative); @@ -2481243,7 +2494575,7 @@ index 0000000..a0c4fce + Output_data_plt_x86_64* + make_data_plt(Layout* layout, + Output_data_got<64, false>* got, -+ Output_data_space* got_plt, ++ Output_data_got_plt_x86_64* got_plt, + Output_data_space* got_irelative, + unsigned int plt_count) + { @@ -2481254,7 +2494586,7 @@ index 0000000..a0c4fce + virtual Output_data_plt_x86_64* + do_make_data_plt(Layout* layout, + Output_data_got<64, false>* got, -+ Output_data_space* got_plt, ++ Output_data_got_plt_x86_64* got_plt, + Output_data_space* got_irelative) + { + return new Output_data_plt_x86_64_standard(layout, got, got_plt, @@ -2481264,7 +2494596,7 @@ index 0000000..a0c4fce + virtual Output_data_plt_x86_64* + do_make_data_plt(Layout* layout, + Output_data_got<64, false>* got, -+ Output_data_space* got_plt, ++ Output_data_got_plt_x86_64* got_plt, + Output_data_space* got_irelative, + unsigned int plt_count) + { @@ -2481463,7 +2494795,7 @@ index 0000000..a0c4fce + got_section(Symbol_table*, Layout*); + + // Get the GOT PLT section. -+ Output_data_space* ++ Output_data_got_plt_x86_64* + got_plt_section() const + { + gold_assert(this->got_plt_ != NULL); @@ -2481574,7 +2494906,7 @@ index 0000000..a0c4fce + // The PLT section. + Output_data_plt_x86_64* plt_; + // The GOT PLT section. -+ Output_data_space* got_plt_; ++ Output_data_got_plt_x86_64* got_plt_; + // The GOT section for IRELATIVE relocations. + Output_data_space* got_irelative_; + // The GOT section for TLSDESC relocations. @@ -2481690,7 +2495022,7 @@ index 0000000..a0c4fce + | elfcpp::SHF_WRITE), + this->got_, got_order, true); + -+ this->got_plt_ = new Output_data_space(8, "** GOT PLT"); ++ this->got_plt_ = new Output_data_got_plt_x86_64(layout); + layout->add_output_section_data(".got.plt", elfcpp::SHT_PROGBITS, + (elfcpp::SHF_ALLOC + | elfcpp::SHF_WRITE), @@ -2481779,6 +2495111,27 @@ index 0000000..a0c4fce + return this->rela_irelative_; +} + ++// Write the first three reserved words of the .got.plt section. ++// The remainder of the section is written while writing the PLT ++// in Output_data_plt_i386::do_write. ++ ++void ++Output_data_got_plt_x86_64::do_write(Output_file* of) ++{ ++ // The first entry in the GOT is the address of the .dynamic section ++ // aka the PT_DYNAMIC segment. The next two entries are reserved. ++ // We saved space for them when we created the section in ++ // Target_x86_64::got_section. ++ const off_t got_file_offset = this->offset(); ++ gold_assert(this->data_size() >= 24); ++ unsigned char* const got_view = of->get_output_view(got_file_offset, 24); ++ Output_section* dynamic = this->layout_->dynamic_section(); ++ uint64_t dynamic_addr = dynamic == NULL ? 0 : dynamic->address(); ++ elfcpp::Swap<64, false>::writeval(got_view, dynamic_addr); ++ memset(got_view + 8, 0, 16); ++ of->write_output_view(got_file_offset, 24, got_view); ++} ++ +// Initialize the PLT section. + +template @@ -2481814,7 +2495167,7 @@ index 0000000..a0c4fce + unsigned int* pcount; + unsigned int offset; + unsigned int reserved; -+ Output_data_space* got; ++ Output_section_data_build* got; + if (gsym->type() == elfcpp::STT_GNU_IFUNC + && gsym->can_use_relative_reloc(false)) + { @@ -2482221,18 +2495574,9 @@ index 0000000..a0c4fce + this->fill_first_plt_entry(pov, got_address, plt_address); + pov += this->get_plt_entry_size(); + -+ unsigned char* got_pov = got_view; -+ -+ // The first entry in the GOT is the address of the .dynamic section -+ // aka the PT_DYNAMIC segment. The next two entries are reserved. -+ // We saved space for them when we created the section in -+ // Target_x86_64::got_section. -+ Output_section* dynamic = this->layout_->dynamic_section(); -+ uint32_t dynamic_addr = dynamic == NULL ? 0 : dynamic->address(); -+ elfcpp::Swap<64, false>::writeval(got_pov, dynamic_addr); -+ got_pov += 8; -+ memset(got_pov, 0, 16); -+ got_pov += 16; ++ // The first three entries in the GOT are reserved, and are written ++ // by Output_data_got_plt_x86_64::do_write. ++ unsigned char* got_pov = got_view + 24; + + unsigned int plt_offset = this->get_plt_entry_size(); + unsigned int got_offset = 24; @@ -2482393,7 +2495737,7 @@ index 0000000..a0c4fce + true); + + // Add the three reserved entries. -+ this->got_plt_ = new Output_data_space((plt_count + 3) * 8, 8, "** GOT PLT"); ++ this->got_plt_ = new Output_data_got_plt_x86_64(layout, (plt_count + 3) * 8); + layout->add_output_section_data(".got.plt", elfcpp::SHT_PROGBITS, + (elfcpp::SHF_ALLOC + | elfcpp::SHF_WRITE), @@ -2483350,7 +2496694,8 @@ index 0000000..a0c4fce + // Make a dynamic relocation if necessary. + if (gsym->needs_dynamic_reloc(Scan::get_reference_flags(r_type))) + { -+ if (gsym->may_need_copy_reloc()) ++ if (!parameters->options().output_is_position_independent() ++ && gsym->may_need_copy_reloc()) + { + target->copy_reloc(symtab, layout, object, + data_shndx, output_section, gsym, reloc); @@ -2483411,7 +2496756,8 @@ index 0000000..a0c4fce + // Make a dynamic relocation if necessary. + if (gsym->needs_dynamic_reloc(Scan::get_reference_flags(r_type))) + { -+ if (gsym->may_need_copy_reloc()) ++ if (parameters->options().output_is_executable() ++ && gsym->may_need_copy_reloc()) + { + target->copy_reloc(symtab, layout, object, + data_shndx, output_section, gsym, reloc); @@ -2483901,7 +2497247,9 @@ index 0000000..a0c4fce + // We need to subtract the size of the GOT section to get + // the actual offset to use in the relocation. + bool have_got_offset = false; -+ unsigned int got_offset = 0; ++ // Since the actual offset is always negative, we use signed int to ++ // support 64-bit GOT relocations. ++ int got_offset = 0; + switch (r_type) + { + case elfcpp::R_X86_64_GOT32: @@ -2484004,10 +2497352,12 @@ index 0000000..a0c4fce + gold_assert(gsym->has_plt_offset() + || gsym->final_value_is_known()); + typename elfcpp::Elf_types::Elf_Addr got_address; -+ got_address = target->got_section(NULL, NULL)->address(); ++ // This is the address of GLOBAL_OFFSET_TABLE. ++ got_address = target->got_plt_section()->address(); + Relocate_functions::rela64(view, object, psymval, + addend - got_address); + } ++ break; + + case elfcpp::R_X86_64_GOT32: + gold_assert(have_got_offset); @@ -2485115,7 +2498465,7 @@ index 0000000..a0c4fce + public: + Output_data_plt_x86_64_nacl(Layout* layout, + Output_data_got<64, false>* got, -+ Output_data_space* got_plt, ++ Output_data_got_plt_x86_64* got_plt, + Output_data_space* got_irelative) + : Output_data_plt_x86_64(layout, plt_entry_size, + got, got_plt, got_irelative) @@ -2485123,7 +2498473,7 @@ index 0000000..a0c4fce + + Output_data_plt_x86_64_nacl(Layout* layout, + Output_data_got<64, false>* got, -+ Output_data_space* got_plt, ++ Output_data_got_plt_x86_64* got_plt, + Output_data_space* got_irelative, + unsigned int plt_count) + : Output_data_plt_x86_64(layout, plt_entry_size, @@ -2485196,7 +2498546,7 @@ index 0000000..a0c4fce + virtual Output_data_plt_x86_64* + do_make_data_plt(Layout* layout, + Output_data_got<64, false>* got, -+ Output_data_space* got_plt, ++ Output_data_got_plt_x86_64* got_plt, + Output_data_space* got_irelative) + { + return new Output_data_plt_x86_64_nacl(layout, got, got_plt, @@ -2485206,7 +2498556,7 @@ index 0000000..a0c4fce + virtual Output_data_plt_x86_64* + do_make_data_plt(Layout* layout, + Output_data_got<64, false>* got, -+ Output_data_space* got_plt, ++ Output_data_got_plt_x86_64* got_plt, + Output_data_space* got_irelative, + unsigned int plt_count) + { @@ -2485480,13 +2498830,13 @@ index 0000000..a0c4fce +} // End anonymous namespace. diff --git a/gold/yyscript.y b/gold/yyscript.y new file mode 100644 -index 0000000..51c755b +index 0000000..37b2670 --- /dev/null +++ b/gold/yyscript.y @@ -0,0 +1,1133 @@ +/* yyscript.y -- linker script grammar for gold. */ + -+/* Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++/* Copyright (C) 2006-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor . + + This file is part of gold. @@ -2486626,55 +2499976,31 @@ index 0000000..e519472 +dir .. diff --git a/gprof/ChangeLog b/gprof/ChangeLog new file mode 100644 -index 0000000..d08636f +index 0000000..bfb9edf --- /dev/null +++ b/gprof/ChangeLog -@@ -0,0 +1,56 @@ -+2013-11-21 Conrad Hoffmann +@@ -0,0 +1,32 @@ ++2014-06-05 Joel Brobecker + -+ * gprof.c (inline_file_names): New variable. -+ (OPTION_INLINE_FILE_NAMES): Define. -+ (long_options): Add --inline-file-names. -+ (usage): Likewise. -+ (main): Process --inline-file-names. -+ * gprof.h: Add prototype for inline_file_names. -+ * utils.c (print_name_only): Handle inline_file_names. -+ * gprof.texi: Document new command line option. ++ * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on ++ bfd's development.sh. ++ * Makefile.in, configure: Regenerate. + -+2013-11-02 Alan Modra ++2014-03-12 Alan Modra + -+ * Makefile.am (.m.c): Fix input and output file specification. + * Makefile.in: Regenerate. + -+2013-10-09 Nick Clifton ++2014-03-05 Alan Modra + -+ PR gprof/16027 -+ * source.c (annotate_source): Close ifp. -+ * corefile.c (read_function_mappings): Close file. ++ Update copyright years. + -+2013-09-20 Alan Modra ++2014-02-10 Alan Modra + -+ * configure: Regenerate. ++ * po/gprof.pot: Regenerate. + -+2013-08-05 John Tytgat -+ -+ * po/POTFILES.in: Regenerate. -+ -+2013-05-24 Alan Modra -+ -+ * aarch64.c (aarch64_find_call): Promote to bfd_vma before sign -+ extending. -+ -+2013-05-22 Venkataramanan Kumar -+ -+ * aarch64.c: New file. -+ * corefile.c (find_call): Call aarch64_find_call for bfd_arch_aarch64. -+ * Makefile.am (sources): Add aarch64.c. -+ * Makefile.in: Regenerate. -+ -+For older changes see ChangeLog-2012 ++For older changes see ChangeLog-2013 + -+Copyright (C) 2013 Free Software Foundation, Inc. ++Copyright (C) 2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -2488037,6 +2501363,68 @@ index 0000000..cc7f23c +fill-column: 74 +version-control: never +End: +diff --git a/gprof/ChangeLog-2013 b/gprof/ChangeLog-2013 +new file mode 100644 +index 0000000..d08636f +--- /dev/null ++++ b/gprof/ChangeLog-2013 +@@ -0,0 +1,56 @@ ++2013-11-21 Conrad Hoffmann ++ ++ * gprof.c (inline_file_names): New variable. ++ (OPTION_INLINE_FILE_NAMES): Define. ++ (long_options): Add --inline-file-names. ++ (usage): Likewise. ++ (main): Process --inline-file-names. ++ * gprof.h: Add prototype for inline_file_names. ++ * utils.c (print_name_only): Handle inline_file_names. ++ * gprof.texi: Document new command line option. ++ ++2013-11-02 Alan Modra ++ ++ * Makefile.am (.m.c): Fix input and output file specification. ++ * Makefile.in: Regenerate. ++ ++2013-10-09 Nick Clifton ++ ++ PR gprof/16027 ++ * source.c (annotate_source): Close ifp. ++ * corefile.c (read_function_mappings): Close file. ++ ++2013-09-20 Alan Modra ++ ++ * configure: Regenerate. ++ ++2013-08-05 John Tytgat ++ ++ * po/POTFILES.in: Regenerate. ++ ++2013-05-24 Alan Modra ++ ++ * aarch64.c (aarch64_find_call): Promote to bfd_vma before sign ++ extending. ++ ++2013-05-22 Venkataramanan Kumar ++ ++ * aarch64.c: New file. ++ * corefile.c (find_call): Call aarch64_find_call for bfd_arch_aarch64. ++ * Makefile.am (sources): Add aarch64.c. ++ * Makefile.in: Regenerate. ++ ++For older changes see ChangeLog-2012 ++ ++Copyright (C) 2013 Free Software Foundation, Inc. ++ ++Copying and distribution of this file, with or without modification, ++are permitted in any medium without royalty provided the copyright ++notice and this notice are preserved. ++ ++Local Variables: ++mode: change-log ++left-margin: 8 ++fill-column: 74 ++version-control: never ++End: diff --git a/gprof/ChangeLog-9203 b/gprof/ChangeLog-9203 new file mode 100644 index 0000000..0dfb61b @@ -2490189,26 +2503577,26 @@ index 0000000..0dfb61b +End: diff --git a/gprof/MAINTAINERS b/gprof/MAINTAINERS new file mode 100644 -index 0000000..cd933df +index 0000000..360ebd0 --- /dev/null +++ b/gprof/MAINTAINERS @@ -0,0 +1,7 @@ +See ../binutils/MAINTAINERS + -+Copyright (C) 2012 Free Software Foundation, Inc. ++Copyright (C) 2012-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright +notice and this notice are preserved. diff --git a/gprof/Makefile.am b/gprof/Makefile.am new file mode 100644 -index 0000000..cdd69be +index 0000000..2daefac --- /dev/null +++ b/gprof/Makefile.am -@@ -0,0 +1,113 @@ +@@ -0,0 +1,114 @@ +## Process this file with automake to generate Makefile.in +# -+# Copyright 2012 Free Software Foundation ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -2490268,7 +2503656,8 @@ index 0000000..cdd69be + +# We extract version from bfd/configure.in, make sure to rerun configure +# when BFD's version changes. -+CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in ++CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in \ ++ $(BFDDIR)/development.sh + +# This empty rule is a hack against gmake patched by Apple. +%.o:%.m @@ -2490321,10 +2503710,10 @@ index 0000000..cdd69be +endif diff --git a/gprof/Makefile.in b/gprof/Makefile.in new file mode 100644 -index 0000000..76591ce +index 0000000..1706ba7 --- /dev/null +++ b/gprof/Makefile.in -@@ -0,0 +1,1069 @@ +@@ -0,0 +1,1071 @@ +# Makefile.in generated by automake 1.11.1 from Makefile.am. +# @configure_input@ + @@ -2490343,7 +2503732,7 @@ index 0000000..76591ce +@SET_MAKE@ + +# -+# Copyright 2012 Free Software Foundation ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -2490652,7 +2504041,9 @@ index 0000000..76591ce + +# We extract version from bfd/configure.in, make sure to rerun configure +# when BFD's version changes. -+CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in ++CONFIG_STATUS_DEPENDENCIES = $(BFDDIR)/configure.in \ ++ $(BFDDIR)/development.sh ++ +POTFILES = $(sources) $(noinst_HEADERS) +MANCONF = -Dman +TEXI2POD = perl $(srcdir)/../etc/texi2pod.pl $(AM_MAKEINFOFLAGS) @@ -2491396,7 +2504787,7 @@ index 0000000..76591ce +.NOEXPORT: diff --git a/gprof/README b/gprof/README new file mode 100644 -index 0000000..e81992a +index 0000000..f57c5aa --- /dev/null +++ b/gprof/README @@ -0,0 +1,448 @@ @@ -2491843,7 +2505234,7 @@ index 0000000..e81992a +of gcc. In the meantime, contact davidm@cs.arizona.edu for a version +of __bb_exit_func() to is appropriate. + -+Copyright (C) 2012 Free Software Foundation, Inc. ++Copyright (C) 2012-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -2491863,7 +2505254,7 @@ index 0000000..78a9030 +- ensure gprof fails gracefully when no debugging info available diff --git a/gprof/TODO b/gprof/TODO new file mode 100644 -index 0000000..6519ffe +index 0000000..3a4231e --- /dev/null +++ b/gprof/TODO @@ -0,0 +1,75 @@ @@ -2491937,7 +2505328,7 @@ index 0000000..6519ffe + will use the new format for basic-block style profiling but + the old format for regular gpprofiling + -+Copyright (C) 2012 Free Software Foundation, Inc. ++Copyright (C) 2012-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -2493222,16 +2506613,15 @@ index 0000000..1a3ebf9 +} diff --git a/gprof/basic_blocks.c b/gprof/basic_blocks.c new file mode 100644 -index 0000000..3946cf2 +index 0000000..5d35bdf --- /dev/null +++ b/gprof/basic_blocks.c -@@ -0,0 +1,586 @@ +@@ -0,0 +1,585 @@ +/* basic_blocks.c - Basic-block level related code: reading/writing + of basic-block info to/from gmon.out; computing and formatting of + basic-block related statistics. + -+ Copyright 1999, 2000, 2001, 2002, 2004, 2005, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1999-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -2493814,12 +2507204,12 @@ index 0000000..3946cf2 +} diff --git a/gprof/basic_blocks.h b/gprof/basic_blocks.h new file mode 100644 -index 0000000..1c3e975 +index 0000000..a2f2be8 --- /dev/null +++ b/gprof/basic_blocks.h @@ -0,0 +1,34 @@ +/* basic_blocks.h -+ Copyright 2000, 2002, 2004, 2007 Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -2493854,14 +2507244,14 @@ index 0000000..1c3e975 +#endif /* basic_blocks_h */ diff --git a/gprof/bb_exit_func.c b/gprof/bb_exit_func.c new file mode 100644 -index 0000000..110fc2b +index 0000000..3d416a6 --- /dev/null +++ b/gprof/bb_exit_func.c @@ -0,0 +1,93 @@ +/* bb_exit_func.c - dumps all the basic-block statistics linked into + the bb_head chain to .d files. + -+ Copyright 2000, 2001, 2004, 2007 Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -2493953,7 +2507343,7 @@ index 0000000..110fc2b +} diff --git a/gprof/bbconv.pl b/gprof/bbconv.pl new file mode 100755 -index 0000000..5c7a1e3 +index 0000000..123218a --- /dev/null +++ b/gprof/bbconv.pl @@ -0,0 +1,55 @@ @@ -2493962,7 +2507352,7 @@ index 0000000..5c7a1e3 +# This script converts a "bb.out" file into a format +# suitable for processing by gprof +# -+# Copyright 2001, 2007 Free Software Foundation, Inc. ++# Copyright (C) 2001-2014 Free Software Foundation, Inc. +# +# This file is part of GNU Binutils. +# @@ -2494014,7 +2507404,7 @@ index 0000000..5c7a1e3 +} diff --git a/gprof/bsd_callg_bl.m b/gprof/bsd_callg_bl.m new file mode 100644 -index 0000000..23c4725 +index 0000000..d5e7599 --- /dev/null +++ b/gprof/bsd_callg_bl.m @@ -0,0 +1,113 @@ @@ -2494126,20 +2507516,20 @@ index 0000000..23c4725 + the members of the cycle, and their contributions + to the time and call counts of the cycle. + -+Copyright (C) 2012 Free Software Foundation, Inc. ++Copyright (C) 2012-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright +notice and this notice are preserved. diff --git a/gprof/call_graph.c b/gprof/call_graph.c new file mode 100644 -index 0000000..93c34b0 +index 0000000..d109f0b --- /dev/null +++ b/gprof/call_graph.c @@ -0,0 +1,130 @@ +/* call_graph.c - Create call graphs. + -+ Copyright 1999, 2000, 2001, 2002, 2004, 2007 Free Software Foundation, Inc. ++ Copyright (C) 1999-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -2494269,13 +2507659,13 @@ index 0000000..93c34b0 +} diff --git a/gprof/call_graph.h b/gprof/call_graph.h new file mode 100644 -index 0000000..f0d80d4 +index 0000000..02904d3 --- /dev/null +++ b/gprof/call_graph.h @@ -0,0 +1,29 @@ +/* call_graph.h + -+ Copyright 2000, 2001, 2002, 2004, 2007 Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -2494997,11 +2508387,11 @@ index 0000000..1fa619d +} diff --git a/gprof/cg_arcs.h b/gprof/cg_arcs.h new file mode 100644 -index 0000000..33b2be5 +index 0000000..ad82e44 --- /dev/null +++ b/gprof/cg_arcs.h @@ -0,0 +1,52 @@ -+/* Copyright 2012 Free Software Foundation, Inc. ++/* Copyright (C) 2012-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -2495364,11 +2508754,11 @@ index 0000000..1da4c66 +} diff --git a/gprof/cg_dfn.h b/gprof/cg_dfn.h new file mode 100644 -index 0000000..9a1e4c9 +index 0000000..a1439bd --- /dev/null +++ b/gprof/cg_dfn.h @@ -0,0 +1,36 @@ -+/* Copyright 2012 Free Software Foundation, Inc. ++/* Copyright (C) 2012-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -2495406,14 +2508796,13 @@ index 0000000..9a1e4c9 +#endif /* cg_dfn_h */ diff --git a/gprof/cg_print.c b/gprof/cg_print.c new file mode 100644 -index 0000000..8ff1471 +index 0000000..456e510 --- /dev/null +++ b/gprof/cg_print.c -@@ -0,0 +1,1295 @@ +@@ -0,0 +1,1294 @@ +/* cg_print.c - Print routines for displaying call graphs. + -+ Copyright 2000, 2001, 2002, 2004, 2007, 2009, 2011 -+ Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -2496707,13 +2510096,13 @@ index 0000000..8ff1471 +} diff --git a/gprof/cg_print.h b/gprof/cg_print.h new file mode 100644 -index 0000000..85c9c42 +index 0000000..69cf39b --- /dev/null +++ b/gprof/cg_print.h @@ -0,0 +1,32 @@ +/* cg_print.h + -+ Copyright 2000, 2001, 2002, 2004, 2007 Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -2496745,10 +2510134,10 @@ index 0000000..85c9c42 +#endif /* cg_print_h */ diff --git a/gprof/configure b/gprof/configure new file mode 100755 -index 0000000..5a9c81e +index 0000000..3d6b415 --- /dev/null +++ b/gprof/configure -@@ -0,0 +1,14530 @@ +@@ -0,0 +1,14533 @@ +#! /bin/sh +# Guess values for system-dependent variables and create Makefiles. +# Generated by GNU Autoconf 2.64. @@ -2508755,6 +2522144,9 @@ index 0000000..5a9c81e + + + ++# Set the 'development' global. ++. $srcdir/../bfd/development.sh ++ +GCC_WARN_CFLAGS="-W -Wall -Wstrict-prototypes -Wmissing-prototypes" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ @@ -2508789,8 +2522181,8 @@ index 0000000..5a9c81e + *) ;; +esac + -+# Enable -Werror by default when using gcc -+if test "${GCC}" = yes -a -z "${ERROR_ON_WARNING}" ; then ++# Enable -Werror by default when using gcc. Turn it off for releases. ++if test "${GCC}" = yes -a -z "${ERROR_ON_WARNING}" -a "$development" = true ; then + ERROR_ON_WARNING=yes +fi + @@ -2511281,13 +2524673,13 @@ index 0000000..5a9c81e + diff --git a/gprof/configure.in b/gprof/configure.in new file mode 100644 -index 0000000..700bd24 +index 0000000..20c2a57 --- /dev/null +++ b/gprof/configure.in @@ -0,0 +1,79 @@ +dnl Process this file with autoconf to produce a configure script. +dnl -+dnl Copyright 2012 Free Software Foundation ++dnl Copyright (C) 2012-2014 Free Software Foundation, Inc. +dnl +dnl This file is free software; you can redistribute it and/or modify +dnl it under the terms of the GNU General Public License as published by @@ -2511366,13 +2524758,13 @@ index 0000000..700bd24 +AC_OUTPUT diff --git a/gprof/corefile.c b/gprof/corefile.c new file mode 100644 -index 0000000..44184dc +index 0000000..45f7431 --- /dev/null +++ b/gprof/corefile.c @@ -0,0 +1,914 @@ +/* corefile.c + -+ Copyright 1999-2013 Free Software Foundation, Inc. ++ Copyright (C) 1999-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -2512286,13 +2525678,13 @@ index 0000000..44184dc +} diff --git a/gprof/corefile.h b/gprof/corefile.h new file mode 100644 -index 0000000..d3844f0 +index 0000000..7c00038 --- /dev/null +++ b/gprof/corefile.h @@ -0,0 +1,47 @@ +/* corefile.h + -+ Copyright 2000, 2001, 2002, 2004, 2007, 2009 Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -2512877,7 +2526269,7 @@ index 0000000..8805f1a + diff --git a/gprof/flat_bl.m b/gprof/flat_bl.m new file mode 100644 -index 0000000..82697c7 +index 0000000..304e58a --- /dev/null +++ b/gprof/flat_bl.m @@ -0,0 +1,33 @@ @@ -2512909,14 +2526301,14 @@ index 0000000..82697c7 + in parenthesis it shows where it would appear in + the gprof listing if it were to be printed. + -+Copyright (C) 2012 Free Software Foundation, Inc. ++Copyright (C) 2012-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright +notice and this notice are preserved. diff --git a/gprof/fsf_callg_bl.m b/gprof/fsf_callg_bl.m new file mode 100644 -index 0000000..9badfa4 +index 0000000..1b4c91d --- /dev/null +++ b/gprof/fsf_callg_bl.m @@ -0,0 +1,88 @@ @@ -2513003,7 +2526395,7 @@ index 0000000..9badfa4 + for that member, how many times it was called from other members of + the cycle. + -+Copyright (C) 2012 Free Software Foundation, Inc. ++Copyright (C) 2012-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -2513326,14 +2526718,13 @@ index 0000000..be670ff +#endif /* gmon_h */ diff --git a/gprof/gmon_io.c b/gprof/gmon_io.c new file mode 100644 -index 0000000..fbb89f5 +index 0000000..3eb4c84 --- /dev/null +++ b/gprof/gmon_io.c -@@ -0,0 +1,753 @@ +@@ -0,0 +1,752 @@ +/* gmon_io.c - Input and output from/to gmon.out files. + -+ Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007, 2008 -+ Free Software Foundation, Inc. ++ Copyright (C) 1999-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -2514085,14 +2527476,13 @@ index 0000000..fbb89f5 +} diff --git a/gprof/gmon_io.h b/gprof/gmon_io.h new file mode 100644 -index 0000000..29d608d +index 0000000..b8707e2 --- /dev/null +++ b/gprof/gmon_io.h -@@ -0,0 +1,44 @@ +@@ -0,0 +1,43 @@ +/* gmon_io.h + -+ Copyright 2000, 2001, 2002, 2004, 2007, 2008 -+ Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -2514135,13 +2527525,13 @@ index 0000000..29d608d +#endif /* gmon_io_h */ diff --git a/gprof/gmon_out.h b/gprof/gmon_out.h new file mode 100644 -index 0000000..ddc437b +index 0000000..55eda38 --- /dev/null +++ b/gprof/gmon_out.h @@ -0,0 +1,46 @@ +/* gmon_out.h + -+ Copyright 2000, 2001, 2002, 2007 Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -2514983,13 +2528373,13 @@ index 0000000..c919ea4 +#endif /* gprof_h */ diff --git a/gprof/gprof.texi b/gprof/gprof.texi new file mode 100644 -index 0000000..3f210b4 +index 0000000..4b80008 --- /dev/null +++ b/gprof/gprof.texi @@ -0,0 +1,2240 @@ +\input texinfo @c -*-texinfo-*- +@setfilename gprof.info -+@c Copyright 1988-2013 Free Software Foundation, Inc. ++@c Copyright (C) 1988-2014 Free Software Foundation, Inc. +@settitle GNU gprof +@setchapternewpage odd + @@ -2515010,7 +2528400,7 @@ index 0000000..3f210b4 +This file documents the gprof profiler of the GNU system. + +@c man begin COPYRIGHT -+Copyright @copyright{} 1988-2013 Free Software Foundation, Inc. ++Copyright @copyright{} 1988-2014 Free Software Foundation, Inc. + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License, Version 1.3 @@ -2515043,7 +2528433,7 @@ index 0000000..3f210b4 +Eric S. Raymond made some minor corrections and additions in 2003. + +@vskip 0pt plus 1filll -+Copyright @copyright{} 1988-2013 Free Software Foundation, Inc. ++Copyright @copyright{} 1988-2014 Free Software Foundation, Inc. + + Permission is granted to copy, distribute and/or modify this document + under the terms of the GNU Free Documentation License, Version 1.3 @@ -2517298,11 +2530688,11 @@ index 0000000..6fa1db4 +} diff --git a/gprof/hertz.h b/gprof/hertz.h new file mode 100644 -index 0000000..a905420 +index 0000000..1d22561 --- /dev/null +++ b/gprof/hertz.h @@ -0,0 +1,32 @@ -+/* Copyright 2012 Free Software Foundation, Inc. ++/* Copyright (C) 2012-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -2517336,14 +2530726,13 @@ index 0000000..a905420 +#endif /* hertz_h */ diff --git a/gprof/hist.c b/gprof/hist.c new file mode 100644 -index 0000000..91b0000 +index 0000000..9043020 --- /dev/null +++ b/gprof/hist.c -@@ -0,0 +1,755 @@ +@@ -0,0 +1,754 @@ +/* hist.c - Histogram related operations. + -+ Copyright 1999, 2000, 2001, 2002, 2004, 2005, 2007, 2009 -+ Free Software Foundation, Inc. ++ Copyright (C) 1999-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -2518097,14 +2531486,13 @@ index 0000000..91b0000 +} diff --git a/gprof/hist.h b/gprof/hist.h new file mode 100644 -index 0000000..0bd5320 +index 0000000..e6dd75b --- /dev/null +++ b/gprof/hist.h -@@ -0,0 +1,59 @@ +@@ -0,0 +1,58 @@ +/* hist.h + -+ Copyright 2000, 2001, 2002, 2004, 2005, 2007, 2009 -+ Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -2518377,13 +2531765,13 @@ index 0000000..2de87cf +} diff --git a/gprof/po/Make-in b/gprof/po/Make-in new file mode 100644 -index 0000000..28550bf +index 0000000..4bd00ae --- /dev/null +++ b/gprof/po/Make-in @@ -0,0 +1,258 @@ +# Makefile for program source directory in GNU NLS utilities package. +# Copyright (C) 1995, 1996, 1997 by Ulrich Drepper -+# Copyright 2002, 2003, 2006, 2007, 2009 Free Software Foundation, Inc. ++# Copyright (C) 2002-2014 Free Software Foundation, Inc. +# +# This file may be copied and used freely without restrictions. It can +# be used in projects which are not available under the GNU Public License @@ -2523520,7 +2536908,7 @@ index 0000000..6d0fb48 +#~ msgstr "%s: níl `%s' comhoiriúnach leis an chéad chomhad gmon\n" diff --git a/gprof/po/gprof.pot b/gprof/po/gprof.pot new file mode 100644 -index 0000000..6beb36c +index 0000000..4a660f3 --- /dev/null +++ b/gprof/po/gprof.pot @@ -0,0 +1,546 @@ @@ -2523534,7 +2536922,7 @@ index 0000000..6beb36c +msgstr "" +"Project-Id-Version: PACKAGE VERSION\n" +"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n" -+"POT-Creation-Date: 2011-10-18 14:20+0100\n" ++"POT-Creation-Date: 2014-02-10 09:42+1030\n" +"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" +"Last-Translator: FULL NAME \n" +"Language-Team: LANGUAGE \n" @@ -2523647,7 +2537035,7 @@ index 0000000..6beb36c +"\n" +msgstr "" + -+#: cg_print.c:80 hist.c:468 ++#: cg_print.c:80 hist.c:471 +#, c-format +msgid "" +"\n" @@ -2523697,7 +2537085,7 @@ index 0000000..6beb36c +msgid "descendants" +msgstr "" + -+#: cg_print.c:103 hist.c:494 ++#: cg_print.c:103 hist.c:497 +msgid "name" +msgstr "" + @@ -2523742,42 +2537130,42 @@ index 0000000..6beb36c +msgid "%s: unable to parse mapping file %s.\n" +msgstr "" + -+#: corefile.c:85 corefile.c:514 ++#: corefile.c:85 corefile.c:526 +#, c-format +msgid "%s: could not open %s.\n" +msgstr "" + -+#: corefile.c:185 ++#: corefile.c:187 +#, c-format +msgid "%s: %s: not in executable format\n" +msgstr "" + -+#: corefile.c:196 ++#: corefile.c:198 +#, c-format +msgid "%s: can't find .text section in %s\n" +msgstr "" + -+#: corefile.c:271 ++#: corefile.c:273 +#, c-format +msgid "%s: ran out room for %lu bytes of text space\n" +msgstr "" + -+#: corefile.c:285 ++#: corefile.c:287 +#, c-format +msgid "%s: can't do -c\n" +msgstr "" + -+#: corefile.c:324 ++#: corefile.c:330 +#, c-format +msgid "%s: -c not supported on architecture %s\n" +msgstr "" + -+#: corefile.c:523 corefile.c:622 ++#: corefile.c:535 corefile.c:638 +#, c-format +msgid "%s: file `%s' has no symbols\n" +msgstr "" + -+#: corefile.c:884 ++#: corefile.c:905 +#, c-format +msgid "%s: somebody miscounted: ltab.len=%d instead of %ld\n" +msgstr "" @@ -2523872,7 +2537260,7 @@ index 0000000..6beb36c +msgid "\t%d basic-block count records\n" +msgstr "" + -+#: gprof.c:159 ++#: gprof.c:162 +#, c-format +msgid "" +"Usage: %s [-[abcDhilLsTvwxyz]] [-[ACeEfFJnNOpPqSQZ][name]] [-I dirs]\n" @@ -2523880,7 +2537268,7 @@ index 0000000..6beb36c +"\t[--[no-]annotated-source[=name]] [--[no-]exec-counts[=name]]\n" +"\t[--[no-]flat-profile[=name]] [--[no-]graph[=name]]\n" +"\t[--[no-]time=name] [--all-lines] [--brief] [--debug[=level]]\n" -+"\t[--function-ordering] [--file-ordering]\n" ++"\t[--function-ordering] [--file-ordering] [--inline-file-names]\n" +"\t[--directory-path=dirs] [--display-unused-functions]\n" +"\t[--file-format=name] [--file-info] [--help] [--line] [--min-count=n]\n" +"\t[--no-static] [--print-path] [--separate-files]\n" @@ -2523891,61 +2537279,61 @@ index 0000000..6beb36c +"\t[image-file] [profile-file...]\n" +msgstr "" + -+#: gprof.c:175 ++#: gprof.c:178 +#, c-format +msgid "Report bugs to %s\n" +msgstr "" + -+#: gprof.c:251 ++#: gprof.c:254 +#, c-format +msgid "%s: debugging not supported; -d ignored\n" +msgstr "" + -+#: gprof.c:331 ++#: gprof.c:334 +#, c-format +msgid "%s: unknown file format %s\n" +msgstr "" + +#. This output is intended to follow the GNU standards document. -+#: gprof.c:419 ++#: gprof.c:422 +#, c-format +msgid "GNU gprof %s\n" +msgstr "" + -+#: gprof.c:420 ++#: gprof.c:423 +#, c-format +msgid "" +"Based on BSD gprof, copyright 1983 Regents of the University of California.\n" +msgstr "" + -+#: gprof.c:421 ++#: gprof.c:424 +#, c-format +msgid "" +"This program is free software. This program has absolutely no warranty.\n" +msgstr "" + -+#: gprof.c:462 ++#: gprof.c:465 +#, c-format +msgid "%s: unknown demangling style `%s'\n" +msgstr "" + -+#: gprof.c:482 ++#: gprof.c:488 +#, c-format +msgid "" +"%s: Only one of --function-ordering and --file-ordering may be specified.\n" +msgstr "" + -+#: gprof.c:534 ++#: gprof.c:540 +#, c-format +msgid "%s: sorry, file format `prof' is not yet supported\n" +msgstr "" + -+#: gprof.c:588 ++#: gprof.c:594 +#, c-format +msgid "%s: gmon.out file is missing histogram\n" +msgstr "" + -+#: gprof.c:595 ++#: gprof.c:601 +#, c-format +msgid "%s: gmon.out file is missing call-graph data\n" +msgstr "" @@ -2523981,53 +2537369,53 @@ index 0000000..6beb36c +msgid "%s: %s: unexpected EOF after reading %u of %u samples\n" +msgstr "" + -+#: hist.c:464 ++#: hist.c:467 +#, c-format +msgid "%c%c/call" +msgstr "" + -+#: hist.c:472 ++#: hist.c:475 +#, c-format +msgid "" +" for %.2f%% of %.2f %s\n" +"\n" +msgstr "" + -+#: hist.c:478 ++#: hist.c:481 +#, c-format +msgid "" +"\n" +"Each sample counts as %g %s.\n" +msgstr "" + -+#: hist.c:483 ++#: hist.c:486 +#, c-format +msgid "" +" no time accumulated\n" +"\n" +msgstr "" + -+#: hist.c:490 ++#: hist.c:493 +msgid "cumulative" +msgstr "" + -+#: hist.c:490 ++#: hist.c:493 +msgid "self " +msgstr "" + -+#: hist.c:490 ++#: hist.c:493 +msgid "total " +msgstr "" + -+#: hist.c:493 ++#: hist.c:496 +msgid "time" +msgstr "" + -+#: hist.c:493 ++#: hist.c:496 +msgid "calls" +msgstr "" + -+#: hist.c:582 ++#: hist.c:585 +#, c-format +msgid "" +"\n" @@ -2524036,12 +2537424,12 @@ index 0000000..6beb36c +"flat profile:\n" +msgstr "" + -+#: hist.c:588 ++#: hist.c:591 +#, c-format +msgid "Flat profile:\n" +msgstr "" + -+#: hist.c:709 ++#: hist.c:712 +#, c-format +msgid "%s: found a symbol that covers several histogram records" +msgstr "" @@ -2524066,7 +2537454,7 @@ index 0000000..6beb36c +msgid "*** File %s:\n" +msgstr "" + -+#: utils.c:99 ++#: utils.c:106 +#, c-format +msgid " " +msgstr "" @@ -2532382,13 +2545770,13 @@ index 0000000..13ec24c +msgstr " " diff --git a/gprof/search_list.c b/gprof/search_list.c new file mode 100644 -index 0000000..66b5d20 +index 0000000..e26a385 --- /dev/null +++ b/gprof/search_list.c @@ -0,0 +1,60 @@ +/* search-list.c + -+ Copyright 2000, 2001, 2002, 2004, 2007 Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -2532448,13 +2545836,13 @@ index 0000000..66b5d20 +} diff --git a/gprof/search_list.h b/gprof/search_list.h new file mode 100644 -index 0000000..45745d0 +index 0000000..254272b --- /dev/null +++ b/gprof/search_list.h @@ -0,0 +1,49 @@ +/* search-list.h + -+ Copyright 2000, 2001, 2004, 2007 Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -2532503,13 +2545891,13 @@ index 0000000..45745d0 +#endif /* search_list_h */ diff --git a/gprof/source.c b/gprof/source.c new file mode 100644 -index 0000000..120e51a +index 0000000..8ca4c59 --- /dev/null +++ b/gprof/source.c @@ -0,0 +1,264 @@ +/* source.c - Keep track of source files. + -+ Copyright 2000-2013 Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -2532773,13 +2546161,13 @@ index 0000000..120e51a +} diff --git a/gprof/source.h b/gprof/source.h new file mode 100644 -index 0000000..081eece +index 0000000..1e41505 --- /dev/null +++ b/gprof/source.h @@ -0,0 +1,63 @@ +/* source.h + -+ Copyright 2000, 2001, 2002, 2004, 2007 Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -2532946,13 +2546334,13 @@ index 0000000..9788f70 +timestamp diff --git a/gprof/sym_ids.c b/gprof/sym_ids.c new file mode 100644 -index 0000000..1b58978 +index 0000000..cbd16e6 --- /dev/null +++ b/gprof/sym_ids.c @@ -0,0 +1,387 @@ +/* sym_ids.c + -+ Copyright 1999, 2000, 2001, 2002, 2004, 2007 Free Software Foundation, Inc. ++ Copyright (C) 1999-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -2533339,13 +2546727,13 @@ index 0000000..1b58978 +} diff --git a/gprof/sym_ids.h b/gprof/sym_ids.h new file mode 100644 -index 0000000..731de5c +index 0000000..192666e --- /dev/null +++ b/gprof/sym_ids.h @@ -0,0 +1,43 @@ +/* sym_ids.h + -+ Copyright 2000, 2001, 2002, 2004, 2007 Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -2533388,14 +2546776,13 @@ index 0000000..731de5c +#endif /* sym_ids_h */ diff --git a/gprof/symtab.c b/gprof/symtab.c new file mode 100644 -index 0000000..3436f1b +index 0000000..2482350 --- /dev/null +++ b/gprof/symtab.c -@@ -0,0 +1,275 @@ +@@ -0,0 +1,274 @@ +/* symtab.c + -+ Copyright 1999, 2000, 2001, 2002, 2004, 2007, 2008 -+ Free Software Foundation, Inc. ++ Copyright (C) 1999-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -2533669,13 +2547056,13 @@ index 0000000..3436f1b +} diff --git a/gprof/symtab.h b/gprof/symtab.h new file mode 100644 -index 0000000..5805506 +index 0000000..35a7cb4 --- /dev/null +++ b/gprof/symtab.h @@ -0,0 +1,123 @@ +/* symtab.h + -+ Copyright 2000, 2001, 2002, 2004, 2007 Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -2534268,11 +2547655,11 @@ index 0000000..4fc2db6 +} diff --git a/gprof/utils.h b/gprof/utils.h new file mode 100644 -index 0000000..b4a0a3d +index 0000000..91ac646 --- /dev/null +++ b/gprof/utils.h @@ -0,0 +1,26 @@ -+/* Copyright 2012 Free Software Foundation, Inc. ++/* Copyright (C) 2012-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -2534656,882 +2548043,564 @@ index 0000000..99719b9 +} diff --git a/ld/ChangeLog b/ld/ChangeLog new file mode 100644 -index 0000000..b996faf +index 0000000..19f71ab --- /dev/null +++ b/ld/ChangeLog -@@ -0,0 +1,883 @@ -+2013-12-20 H.J. Lu +@@ -0,0 +1,565 @@ ++2014-06-07 Alan Modra + -+ * emulparams/elf_k1om.sh (IREL_IN_PLT): Define. -+ * emulparams/elf_l1om.sh (IREL_IN_PLT): Likewise. ++ * ldexp.c (exp_fold_tree_1 ): Make PROVIDEd ++ linker script symbol value override a built-in linker symbol. + -+2013-12-13 Kuan-Lin Chen -+ Wei-Cheng Wang -+ Hui-Wen Ni ++2014-06-05 Joel Brobecker + -+ * Makefile.am (ALL_EMULATION_SOURCES): Add nds32 target. ++ * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on ++ bfd's development.sh. ++ * Makefile.in, configure: Regenerate. ++ ++2014-06-02 Alan Modra ++ ++ * emulparams/elf32bfin.sh: Rename from bfin.sh. ++ * emulparams/elf32bfinfd.sh: Update to suit. ++ * emulparams/msp430.sh: Rename from msp430all.sh. Remove ++ MSP430_NAME and msp430X vars. ++ * emulparams/msp430X.sh: New. ++ * emulparams/score3_elf.sh: Rename from scoreelf.sh. Remove ++ SCORE_NAME and score7_elf ARCH setting. ++ * emulparams/score7_elf.sh: New. ++ * Makefile.am (eelf32bfin.c, eelf32bfinfd.c): Update dependencies. ++ (emsp430.c, emsp430X.c, escore3_elf.c, escore7_elf.c): Likewise. + * Makefile.in: Regenerate. -+ * configure.tgt: Add case for nds32*le-*-elf*, nds32*be-*-elf*, -+ nds32*le-*-linux-gnu*, and nds32*be-*-linux-gnu*. -+ * emulparams/nds32belf.sh: New file for nds32. -+ * emulparams/nds32belf_linux.sh: Likewise. -+ * emulparams/nds32belf16m.sh: Likewise. -+ * emulparams/nds32elf.sh: Likewise. -+ * emulparams/nds32elf_linux.sh: Likewise. -+ * emulparams/nds32elf16m.sh: Likewise. -+ * emultempl/nds32elf.em: Likewise. -+ * scripttempl/nds32elf.sc}: Likewise. -+ * gen-doc.texi: Set NDS32. -+ * ld.texinfo: Set NDS32. -+ * NEWS: Announce Andes nds32 support. ++ * genscripts.sh: Delete customizer_script param. + -+2013-12-11 H.J. Lu ++2014-05-28 Hans-Peter Nilsson + -+ * ld.texinfo: Remove shared object from -Ttext-segment. -+ -+2013-12-10 Roland McGrath -+ -+ * Makefile.am (install-exec-local): Prefix libtool invocation with -+ $(INSTALL_PROGRAM_ENV). ++ * Makefile.am: Change all rules with ${GENSCRIPTS} ++ invocations to be just dependencies. ++ ($(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES)) ++ (run-genscripts): New rules. + * Makefile.in: Regenerate. + -+2013-12-07 Mike Frysinger ++2014-05-27 DJ Delorie + -+ * ChangeLog-2008: Remove +x file mode. -+ * emulparams/bfin.sh: Likewise. -+ * emulparams/elf32bmipn32.sh: Likewise. -+ * emulparams/elf32fr30.sh: Likewise. -+ * emulparams/elf32frv.sh: Likewise. -+ * emulparams/elf32iq10.sh: Likewise. -+ * emulparams/elf32iq2000.sh: Likewise. -+ * emulparams/elf32mep.sh: Likewise. -+ * emulparams/elf32openrisc.sh: Likewise. -+ * emulparams/elf64bmip.sh: Likewise. -+ * emulparams/elf64hppa.sh: Likewise. -+ * emulparams/i386beos.sh: Likewise. ++ * ld/ldemul.h (extra_map_file_text): New field. ++ (ldemul_extra_map_file_text): Declare. ++ * ld/ldemul.c (ldemul_extra_map_file_text): Define. ++ * ld/ldlang.c (lang_map): Call it. + -+2013-11-26 H.J. Lu ++ * ld/emultempl/rxelf.em: Add extra_map_file_text hook. ++ * ld/emultempl/aix.em: Add NULL extra_map_file_text hook. ++ * ld/emultempl/armcoff.em: Likewise. ++ * ld/emultempl/beos.em: Likewise. ++ * ld/emultempl/elf32.em: Likewise. ++ * ld/emultempl/generic.em: Likewise. ++ * ld/emultempl/gld960.em: Likewise. ++ * ld/emultempl/gld960c.em: Likewise. ++ * ld/emultempl/linux.em: Likewise. ++ * ld/emultempl/lnk960.em: Likewise. ++ * ld/emultempl/m68kcoff.em: Likewise. ++ * ld/emultempl/pe.em: Likewise. ++ * ld/emultempl/pep.em: Likewise. ++ * ld/emultempl/sunos.em: Likewise. ++ * ld/emultempl/ticoff.em: Likewise. ++ * ld/emultempl/vanilla.em: Likewise. + -+ PR ld/16259 -+ * Makefile.am (HOSTING_SLIBS): New. -+ * configure.host (HOSTING_SLIBS): New. Used for PIE. -+ * configure.in (HOSTING_SLIBS): New AC_SUBST. -+ * Makefile.in: Regenerated. -+ * configure: Likewise. ++2014-05-24 Alan Modra + -+2013-11-22 Cory Fields ++ * ldlang.c (base): Move variable to.. ++ * mri.c: ..here, and make static. ++ * ldlang.h (base): Delete declaration. + -+ * pe-dll.c (fill_edata): Only use a real timestamp if -+ --insert-timestamp was used. -+ * emultempl/pe.em: Add the --insert-timestamp option. -+ * emultempl/pep.em: Likewise for 64bit. -+ * ld.texinfo: Document the --insert-timestamp option. ++2014-05-20 Hans-Peter Nilsson + -+2013-11-22 Senthil Kumar Selvaraj -+ -+ * scripttempl/avr.sc: Set .data section's LMA to next available -+ address in text region. -+ -+2013-11-21 Andrew Pinski -+ -+ * Makefile.am (ALL_64_EMULATION_SOURCES): Add eaarch64linux32.c -+ and eaarch64linux32b.c -+ (eaarch64linux32.c): New target. -+ (eaarch64linux32b.c): Likewise. -+ * Makefile.in: Regenerate. -+ * configure.tgt (aarch64_be-*-linux*): Add -+ aarch64linux32 and aarch64linux32b to targ_extra_libpath. -+ (aarch64-*-linux*): Likewise. -+ * emulparams/aarch64elf32.sh (SEPARATE_GOTPLT): Change to 12 (3 words). -+ * emulparams/aarch64linux32.sh: New file. -+ * emulparams/aarch64linux32b.sh: New file. -+ -+2013-11-21 Andrew Pinski -+ -+ * configure.tgt (aarch64_be-*-linux*): Split out the linux targets -+ into targ_extra_libpath. -+ (aarch64-*-linux*): Likewise. -+ -+2013-11-21 Nick Clifton -+ -+ PR ld/16192 -+ * pe-dll.c (pe_create_runtime_relocator_reference): Zero the -+ newly allocated idata5 block. -+ -+2013-11-20 Nick Clifton -+ -+ * scripttempl/elf32msp430.sc (.data): Set the based on the next -+ free location in the text memory region, not a computation based -+ upon the size of the text section. Orphaned sections or other -+ linker scripts might insert new sections between the .text section -+ and the .data section. -+ * scripttempl/elf32msp430_3.sc (.data): Likewise. -+ -+2013-11-19 Roland McGrath -+ Alan Modra -+ -+ * emultempl/elf32.em (gld${EMULATION_NAME}_before_allocation): -+ Don't use bfd_elf_record_link_assignment to mark __ehdr_start -+ hidden. Instead, just do it directly here, and only if it was -+ referenced but not defined. -+ -+2013-11-18 Chung-Lin Tang -+ -+ * emulparams/nios2linux.sh: New emulation file. -+ * configure.tgt: Add nios2*-*-linux* emulation case. -+ * Makefile.am (enios2linux.c): New emulation entry. ++ * Makefile.am (ALL_EMULATION_SOURCES): Add missing eelf32mbel_linux.c. + * Makefile.in: Regenerate. + -+2013-10-14 Nick Clifton ++2014-05-20 Alan Modra + -+ * emultempl/aix.em (_read_file): Close file at end of function. ++ PR 16952 ++ * emulparams/elf32ppccommon.sh (_SDA_BASE_, _SDA2_BASE_): Delete. ++ * emultempl/ppc32elf.em (ppc_before_allocation): Call ++ ppc_elf_maybe_strip_sdata_syms. ++ * ldlang.c (size_input_section): Correct output_offset value ++ for excluded input sections. + -+2013-10-10 Roland McGrath ++2014-05-16 John Marino + -+ * ldmisc.c (vfinfo): Use Boolean ? "" : ":" in place of ":" + Boolean. -+ It silences some compilers' warnings and is much less bizarre to read. ++ * configure.tgt: Add /lib to dragonfly NATIVE_LIB_DIRS. + -+2013-10-09 Roland McGrath ++2014-05-11 Chung-Lin Tang + -+ * emultempl/elf32.em (id_note_section_size): Use ATTRIBUTE_UNUSED -+ rather than a dummy assignment for unused parameter. -+ * plugin.c (get_input_file, release_input_file): Likewise. ++ * emulparams/nios2linux.sh (OTHER_GOT_SYMBOLS): Wrap _gp in HIDDEN(), ++ and gp in PROVIDE_HIDDEN. + -+2013-10-09 Nick Clifton ++2014-05-10 Hans-Peter Nilsson + -+ PR ld/16028 -+ * ldmain.c (add_keepsyms_file): Close file at end of function. ++ * ldlang.c (lang_finish): Don't call bfd_link_hash_table_free here. ++ (output_bfd_hash_table_free_fn): New variable. ++ (open_output): Save the _bfd_link_hash_table_free function for the ++ output_bfd into output_bfd_hash_table_free_fn. ++ * ldmain.c (ld_cleanup): If set, call output_bfd_hash_table_free_fn ++ on link_info.hash. ++ * ldlang.h (output_bfd_hash_table_free_fn): Declare. + -+2013-10-03 Will Newton ++2014-05-02 Alan Modra + -+ * emulparams/aarch64elf.sh: Add IREL_IN_PLT. -+ * emulparams/aarch64elf32.sh: Likewise. -+ -+2013-09-30 Nick Clifton -+ -+ * emulparams/msp430all.sh: Update ARCH names. -+ -+2013-09-24 Alan Modra -+ -+ * emulparams/elf32ppccommon.sh (LIBPATH_SUFFIX): Provide 32-bit -+ and cross-endian values. -+ * emulparams/elf64ppc.sh: Source elf32ppccomon.sh. Delete duplicate, -+ and unset unwanted variables. -+ -+2013-09-24 Alan Modra -+ -+ * genscripts.sh (LIB_PATH): Don't exclude libdir or tooldir when -+ sysrooted. Also, don't always add tooldir when non-sysrooted. -+ Instead add both when native and tooldir also when TOOL_DIR is -+ defined. Always prepend '=' to paths when sysrooted. Always -+ put paths with LIBPATH_SUFFIX first in search order. -+ -+2013-09-20 Chung-Lin Tang -+ -+ * Makefile.am (enios2elf.c): Change tdir_nios2 to tdir_nios2elf. -+ * Makefile.in: Regenerate. -+ -+2013-09-20 Alan Modra -+ -+ * configure: Regenerate. -+ -+2013-09-18 Tristan Gingold -+ -+ * NEWS: Add marker for 2.24. -+ -+2013-09-17 Nick Clifton -+ -+ PR ld/15957 -+ * deffilep.y (def_file_add_directive): Avoid readin past end of -+ buffer. -+ -+2013-08-28 Nick Clifton -+ -+ PR ld/15896 -+ * ld.texinfo: Fix uses of MB abbreviation. -+ -+2013-08-26 Roland McGrath -+ -+ * emulparams/elf_i386_nacl.sh (ARCH): Set to i386:nacl. -+ * emulparams/elf_x86_64_nacl.sh (ARCH): Set to i386:x86-64:nacl. -+ * emulparams/elf32_x86_64_nacl.sh (ARCH): Set to i386:x64-32:nacl. -+ -+2013-08-23 Roland McGrath -+ -+ * emulparams/elf_nacl.sh (nacl_rodata_addr): Don't add in -+ SIZEOF_HEADERS here; elf.sc does it already. -+ -+2013-08-23 Nick Clifton -+ -+ PR ld/15839 -+ * scripttempl/avr.sc: Do not include gc'able sections into general -+ sections during relocatable links. -+ -+2013-08-22 Christian Franke -+ -+ * emultempl/pe.em: Add --disable-large-address-aware option. -+ * ld.texinfo (--disable-large-address-aware): Add documentation. -+ -+2013-08-14 Clemens Lang -+ -+ * ldexp.c: Add LOG2CEIL() builtin function to linker script language -+ * ldgram.y: Likewise -+ * ldlex.l: Likewise -+ * NEWS: Mention the new feature. -+ * ld.texinfo: Document the new feature. -+ -+2013-07-19 Sebastian Huber -+ -+ * ldgram.y: Add ALIGN_WITH_INPUT output section attribute. -+ * ldlang.c: Likewise. -+ * ldlang.h: Likewise. -+ * ldlex.l: Likewise. -+ * mri.c: Likewise. -+ * ld.texinfo: Document new feature. -+ * NEWS: Mention new feature. -+ -+2013-07-18 Roland McGrath -+ -+ * emultempl/armelf.em (elf32_arm_add_stub_section): Take third -+ argument ALIGNMENT_POWER, use it instead of constant 3. -+ -+2013-07-08 Jeff Law -+ -+ * scripttempl/elf.sc: Handle function names and other text after -+ .text.unlikely too. -+ -+2013-07-08 Tristan Gingold -+ -+ * scripttempl/ia64vms.sc: Add support of per data and per function -+ sections. -+ -+2013-07-01 Alan Modra -+ -+ * emultempl/ppc64elf.em: (ppc_layout_sections_again): Call -+ ppc64_elf_set_toc rather than ppc64_elf_toc/_bfd_set_gp_value. -+ (gld${EMULATION_NAME}_after_allocation): Likewise. -+ -+2013-06-26 Yufeng Zhang -+ -+ * emulparams/aarch64elf32.sh: New file. -+ -+2013-06-26 Yufeng Zhang -+ -+ * Makefile.am (ALL_64_EMULATION_SOURCES): Add eaarch64elf32b.c. -+ (eaarch64elf32b.c): New dependency and rule. -+ * Makefile.in: Re-generated. -+ * configure.tgt (aarch64-*-elf): Add aarch64elf32b. -+ (aarch64_be-*-elf, aarch64_be-*-linux*, aarch64-*-linux*): Likewise. -+ * emulparams/aarch64elf32b.sh: New file. -+ -+2013-06-26 Yufeng Zhang -+ -+ * Makefile.am (ALL_64_EMULATION_SOURCES): Add eaarch64elf32.c. -+ (eaarch64elf32.c): New dependency and rule. -+ * Makefile.in: Re-generated. -+ * configure.tgt (aarch64-*-elf): Add aarch64elf32. -+ (aarch64_be-*-elf, aarch64_be-*-linux*, aarch64-*-linux*): Likewise. -+ * emulparams/aarch64elf32.sh: New file. -+ -+2013-06-25 Maciej W. Rozycki -+ -+ * emultempl/mipself.em (insn32): New variable. -+ (mips_create_output_section_statements): Handle insn32 mode. -+ (PARSE_AND_LIST_PROLOGUE): New macro. -+ (PARSE_AND_LIST_LONGOPTS): Likewise. -+ (PARSE_AND_LIST_OPTIONS): Likewise. -+ -+ * gen-doc.texi: Set MIPS. -+ * ld.texinfo: Likewise. -+ (Options specific to MIPS targets): New section. -+ (ld and MIPS family): New node. -+ (Top, Machine Dependent): List the new node. -+ -+2013-06-24 Maciej W. Rozycki -+ -+ * emulparams/elf32btsmip.sh: Arrange for .got.plt to be placed -+ as close to .plt as possible. -+ * scripttempl/elf.sc: Handle $INITIAL_READWRITE_SECTIONS and -+ $PLT_NEXT_DATA variables. -+ -+2013-06-23 Richard Sandiford -+ -+ * Makefile.am (ALL_EMULATION_SOURCES): Move MIPS ELF emulations to... -+ (ALL_64_EMULATION_SOURCES): ...here. -+ * Makefile.in: Regenerate. -+ -+2013-06-22 Richard Sandiford -+ -+ * NEWS: Document the removal of MIPS ECOFF targets. -+ * ld.texinfo (--gpsize=@var{value}): Use MIPS ELF rather than -+ MIPS ECOFF as an example of a target that supports small data. -+ * ldmain.c (g_switch_value): Likewise. -+ * configure.tgt (mips*-*-pe, mips*-dec-ultrix*, mips*-dec-osf*) -+ (mips*-sgi-irix* [v4 and earlier], mips*el-*-ecoff*, mips*-*-ecoff*) -+ (mips*-*-bsd*, mips*-*-lnews*): Remove cases. -+ * Makefile.am (ALL_EMULATION_SOURCES): Remove emipsbig.c, emipsbsd.c, -+ emipsidt.c, emipsidtl.c, emipslit.c, emipslnews.c and emipspe.c. -+ (emipsbig.c, emipsbsd.c, emipsidt.c, emipsidtl.c, emipslit.c) -+ (emipslnews.c, emipspe.c): Delete rules. -+ * Makefile.in: Regenerate. -+ * emulparams/mipsbig.sh, emulparams/mipsbsd.sh, emulparams/mipsidt.sh, -+ emulparams/mipsidtl.sh, emulparams/mipslit.sh, emulparams/mipslnews.sh, -+ emulparams/mipspe.sh, emultempl/mipsecoff.em: Delete. -+ * emultempl/m68kcoff.em: Update comment to say that MIPS ECOFF support -+ has now been removed. -+ * emultempl/pe.em: Remove TARGET_IS_mipspe checks. -+ -+2013-06-19 Will Newton -+ -+ * emulparams/aarch64elf.sh: Remove IREL_IN_PLT. -+ -+2013-06-14 Yufeng Zhang -+ -+ * emulparams/aarch64elf.sh: Add IREL_IN_PLT. -+ -+2013-06-12 Nick Clifton -+ -+ * ldcref.c (output_one_cref): Place common definitions after -+ ordinary definitions but before references. -+ -+2013-06-10 Dilyan Palauzov -+ -+ PR ld/15598 -+ * ld.texinfo (Source Code Reference): Fix typos. -+ -+2013-06-07 Will Newton -+ -+ * emulparams/aarch64elf.sh: Add IREL_IN_PLT. -+ -+2013-06-07 Nick Clifton -+ -+ * ld.texinfo (SEGMENT_START): Rephrase to indicate that a -T -+ option must appear before the SEGMENT_START is encountered in -+ order for the default value to be overridden. -+ -+2013-05-03 Alan Modra -+ -+ PR ld/15365 -+ * emultempl/elf32.em (gld${EMULATION_NAME}_before_allocation): -+ Restrict __ehdr_start's export class to no less than STV_HIDDEN. -+ -+2013-05-03 Alan Modra -+ -+ * emultempl/elf32.em (gld${EMULATION_NAME}_before_allocation): -+ Only call lang_for_each_statement if an ELF hash table is used. -+ -+2013-05-02 Nick Clifton -+ -+ * Makefile.am: Add emsp430X.c -+ * Makefine.in: Regenerate. -+ * configure.tgt (msp430): Add msp430X emulation. -+ * ldmain.c (multiple_definition): Only disable relaxation if it -+ was enabled by the user. -+ * ldmain.h (RELAXATION_ENABLED_BY_USER): New macro. -+ * emulparams/msp430all.sh: Add support for MSP430X. -+ * emultempl/generic.em: (before_parse): Enable relaxation for the -+ MSP430. -+ * scripttempl/msp430.sc: Reorganize sections. Add .rodata -+ section. -+ * scripttempl/msp430_3.sc: Likewise. -+ * NEWS: Mention support for MSP430X. -+ -+2013-05-01 Maciej W. Rozycki -+ -+ * configure.tgt: Replace alpha*-*-linuxecoff* pattern with -+ alpha*-*-linux*ecoff*. Update the `sed' pattern used to convert -+ from alpha*-*-linux-* to alpha*-*-linux*ecoff*. -+ -+2013-05-01 Maciej W. Rozycki -+ -+ * emultempl/elf32.em (gld${EMULATION_NAME}_before_allocation): -+ Use is_elf_hash_table rather than a handcoded condition. -+ -+2013-04-30 Nick Clifton -+ -+ * ld.texinfo (SORT_BY_ALIGNMENT): Fix and clarify typo - sections -+ are sorted by descending order of alignment. -+ -+2013-04-29 Nick Clifton -+ -+ * scripttempl/DWARF.sc: Add support for .debug_line.* and -+ .debug_line_end. -+ -+2013-04-29 Yaakov Selkowitz -+ -+ * emultempl/pe.em [cygwin]: Do not merge rdata with v2 -+ psuedo-relocs. -+ -+2013-04-28 Thomas Schwinge -+ -+ * scripttempl/armbpabi.sc: Replace "source" usage with ".". -+ * scripttempl/avr.sc: Likewise. -+ * scripttempl/elf.sc: Likewise. -+ * scripttempl/elf32cr16.sc: Likewise. -+ * scripttempl/elf32crx.sc: Likewise. -+ * scripttempl/elf32msp430.sc: Likewise. -+ * scripttempl/elf32msp430_3.sc: Likewise. -+ * scripttempl/elf32sh-symbian.sc: Likewise. -+ * scripttempl/elf64hppa.sc: Likewise. -+ * scripttempl/elf_chaos.sc: Likewise. -+ * scripttempl/elfd10v.sc: Likewise. -+ * scripttempl/elfd30v.sc: Likewise. -+ * scripttempl/elfi370.sc: Likewise. -+ * scripttempl/elfm68hc11.sc: Likewise. -+ * scripttempl/elfm68hc12.sc: Likewise. -+ * scripttempl/elfxgate.sc: Likewise. -+ * scripttempl/elfxtensa.sc: Likewise. -+ * scripttempl/epiphany_4x4.sc: Likewise. -+ * scripttempl/i386beos.sc: Likewise. -+ * scripttempl/i386go32.sc: Likewise. -+ * scripttempl/ia64vms.sc: Likewise. -+ * scripttempl/ip2k.sc: Likewise. -+ * scripttempl/iq2000.sc: Likewise. -+ * scripttempl/mep.sc: Likewise. -+ * scripttempl/mmo.sc: Likewise. -+ * scripttempl/v850.sc: Likewise. -+ * scripttempl/v850_rh850.sc: Likewise. -+ * scripttempl/xstormy16.sc: Likewise. -+ -+2013-04-26 Senthil Kumar Selvaraj -+ -+ * scripttempl/avr.sc: Add ALIGN directive after *(.progmem*). -+ -+2013-04-26 Alan Modra -+ -+ * emultempl/elf32.em (gld${EMULATION_NAME}_after_open): Test -+ unresolved_syms_in_shared_libs rather than !executable to -+ determine whether to load DT_NEEDED libraries. -+ -+2013-04-25 Alan Modra -+ -+ * Makefile.am (ALL_EMULATION_SOURCES): Add eelf32lppclinux.c. -+ (eelf32lppclinux.c): New rule. -+ * Makefile.in: Regenerate. -+ * configure.tgt: Merge powerpc-linux and other powerpc-elf targets -+ with corresponding little-endian targets. -+ * emulparams/elf32lppc.sh: Update comment. -+ * emulparams/elf32lppclinux.sh: New. -+ -+2013-04-24 H.J. Lu -+ -+ * configure.tgt (targ_extra_emuls): Adds elf32_x86_64 for -+ x86_64-*-elf*. -+ (targ_extra_libpath): Likewise. -+ (tdir_elf_i386): Replace x86_64 with i386 for x86_64-*-elf*. -+ -+2013-04-24 Yufeng Zhang -+ -+ * emulparams/aarch64elf.sh: Define ELFSIZE=64. -+ * emulparams/aarch64linux.sh: Ditto. -+ * emultempl/aarch64elf.em (aarch64_elf_before_allocation): -+ Replace elf64 with elf${ELFSIZE}. -+ (elf64_aarch64_add_stub_section): Likewise. -+ (build_section_lists): Likewise. -+ (gld${EMULATION_NAME}_after_allocation): Likewise. -+ (gld${EMULATION_NAME}_finish): Likewise. -+ (aarch64_elf_create_output_section_statements): Likewise. -+ -+2013-04-24 Nick Clifton -+ -+ PR ld/15389 -+ * scripttempl/avr.sc: Add .note.gnu.build-id section. -+ -+2013-04-22 Alan Modra -+ -+ * emultempl/ppc64elf.em (ppc_create_output_section_statements): -+ Check return from ppc64_elf_init_stub_bfd. -+ -+2013-04-15 Nick Clifton -+ -+ * Makefile.am (ELF_DEPS): Add a dependency upon -+ scripttempl/DWARF.sc. -+ (ELF_GEN_DEPS): Likewise. -+ (emmo.c): Likewise. -+ * Makefile.in: Regenerate. -+ -+ * scripttempl/armbpabi.sc: Replace DWARF sections with an -+ inclusion of DWARF.sc. -+ * scripttempl/avr.sc: Likewise. -+ * scripttempl/elf.sc: Likewise. -+ * scripttempl/elf32cr16.sc: Likewise. -+ * scripttempl/elf32crx.sc: Likewise. -+ * scripttempl/elf32msp430.sc: Likewise. -+ * scripttempl/elf32msp430_3.sc: Likewise. -+ * scripttempl/elf32sh-symbian.sc: Likewise. -+ * scripttempl/elf64hppa.sc: Likewise. -+ * scripttempl/elf_chaos.sc: Likewise. -+ * scripttempl/elfd10v.sc: Likewise. -+ * scripttempl/elfd30v.sc: Likewise. -+ * scripttempl/elfi370.sc: Likewise. -+ * scripttempl/elfm68hc11.sc: Likewise. -+ * scripttempl/elfm68hc12.sc: Likewise. -+ * scripttempl/elfxgate.sc: Likewise. -+ * scripttempl/elfxtensa.sc: Likewise. -+ * scripttempl/epiphany_4x4.sc: Likewise. -+ * scripttempl/i386beos.sc: Likewise. -+ * scripttempl/i386go32.sc: Likewise. -+ * scripttempl/ia64vms.sc: Likewise. -+ * scripttempl/ip2k.sc: Likewise. -+ * scripttempl/iq2000.sc: Likewise. -+ * scripttempl/mep.sc: Likewise. -+ * scripttempl/mmo.sc: Likewise. -+ * scripttempl/v850.sc: Likewise. -+ * scripttempl/v850_rh850.sc: Likewise. -+ * scripttempl/xstormy16.sc: Likewise. -+ * scripttempl/DWARF.sc: New. -+ -+2013-04-04 Alan Modra -+ -+ * ldlang.c (load_symbols): Report "error adding symbols" on -+ bfd_link_add_symbols failure. -+ * emultempl/elf32.em (gld${EMULATION_NAME}_try_needed): Likewise. -+ * emultempl/sunos.em (gld${EMULATION_NAME}_after_open): Likewise. -+ (gld${EMULATION_NAME}_try_needed): Likewise. -+ -+2013-03-27 Georg-Johann Lay -+ -+ PR ld/13812 -+ * scripttempl/avr.sc: Place trampolines before .progmem section. -+ -+2013-03-25 Kai Tietz -+ -+ * ld.texinfo (--disable-runtime-pseudo-reloc): Adjust default. -+ -+2013-03-21 Michael Schewe -+ -+ * ld.texinfo (H8/300): Add description of relaxation of -+ mov @(disp:32,ERx) to mov @(disp:16,ERx). -+ -+2013-03-21 Kai Tietz -+ -+ * pe-dll.c (process_def_file_and_drectve): Don't handle VC -+ generated C++-symbols as stdcall/fastcall. -+ -+2013-03-18 Alan Modra -+ -+ * ld.texinfo (--as-needed): Update. -+ -+2013-03-14 Jakub Jelinek -+ -+ * emulparams/aarch64linux.sh (LIBPATH_SUFFIX): Set to 64 for -+ aarch64linux* emulations. -+ -+2013-03-07 Alan Modra -+ -+ * ldfile.c (ldfile_open_command_file_1): Return after einfo -+ to avoid warning. -+ -+2013-03-05 Corinna Vinschen -+ -+ * configure.host: Add x86_64-*-cygwin* as valid host. -+ * configure.tgt: Add x86_64-*-cygwin* as valid target. -+ * emultempl/pep.em: Handle different requirements for Cygwin in terms -+ of start addresses for executables and DLLs, based on memory model in -+ http://cygwin.com/ml/cygwin-developers/2013-02/msg00027.html -+ -+2013-03-05 Alan Modra -+ -+ PR ld/15222 -+ * ldlang.c (lang_size_sections_1): When given an lma_region align -+ LMA as per VMA only if lma_region is the same as region. -+ -+2013-02-27 Nick Clifton -+ -+ * scripttempl/elf32msp430.sc: Add placement of .data.* sections. -+ Add alignment of .bss section. -+ * scripttempl/elf32msp430_3.sc: Likewise. -+ -+2013-02-26 Nick Clifton -+ -+ PR ld/15188 -+ * ld.texinfo: Fix typos. -+ -+2013-02-21 Alan Modra -+ -+ * scripttempl/elf.sc (.init_array, .fini_array): Don't sort all -+ .init_array/.fini_array input sections before .ctors/.dtors input -+ sections. -+ (CTORS_IN_INIT_ARRAY, DTORS_IN_INIT_ARRAY): Adjust to suit. -+ -+2013-02-21 Alan Modra -+ -+ * emultempl/elf32.em (write_build_id, setup_build_id): Adjust -+ for elf_tdata changes. -+ -+2013-02-21 Alan Modra -+ -+ * emultempl/elf-generic.em: Use newly defined elf_obj_tdata -+ accessor macros. -+ -+2013-02-20 Alan Modra -+ -+ * Makefile.am: Use $(ELF_DEPS) on a number of eelf*.c rules. -+ * Makefile.in: Regenerate. -+ -+2013-02-19 Sandra Loosemore -+ -+ PR ld/15146 -+ * plugin.c (plugin_notice): Add null check before dereferencing -+ pointer. -+ -+2013-02-19 Alan Modra -+ -+ * emultempl/elf32.em (emit_note_gnu_build_id): New static var. -+ Replace all info->emit_note_gnu_build_id refs. -+ (id_note_section_size): Rename from -+ gld${EMULATION_NAME}_id_note_section_size. -+ (struct build_id_info): Delete. -+ (write_build_id): Rename from -+ gld${EMULATION_NAME}_write_build_id_section. -+ Update elf_tdata usage. Style, formatting. -+ (setup_build_id): New function. -+ (gld${EMULATION_NAME}_after_open): Use setup_build_id. -+ -+2013-02-16 H.J. Lu -+ -+ PR ld/15146 -+ * plugin.c (plugin_notice): Replace the undefined dummy bfd with -+ the real one. -+ -+2013-02-16 H.J. Lu -+ -+ PR ld/15141 -+ * plugin.c (plugin_notice): Also trace symbol from the IR bfd. -+ -+2013-02-15 Kai Tietz -+ -+ * scripttempl/pep.sc (.xdata): Merge .xdata* into .xdata section. -+ (.pdata): Merge .pdata* into .pdata section. -+ -+2013-02-11 Alan Modra -+ -+ * ldlang.c (get_init_priority): Comment typo. -+ (lang_finish): Free link_info.hash and lang_definedness_table. -+ (lang_end): Delete lang_definedness_table comment. -+ -+2013-02-11 Alan Modra -+ -+ PR ld/15130 -+ * ld.texinfo (-rpath-link): Typo fix. -+ -+2013-02-08 Markos Chandras -+ -+ * emultempl/metagelf.em (build_section_lists): Use sec_info_type -+ rather than userdata->flags.just_syms. -+ -+2013-02-06 Sandra Loosemore -+ Andrew Jenner -+ -+ Based on patches from Altera Corporation. -+ -+ * Makefile.am (enios2elf.c): New rule. -+ * Makefile.in: Regenerated. -+ * configure.tgt: Add case for nios2*-*-*. -+ * emulparams/nios2elf.sh: New file. -+ * NEWS: Note Altera Nios II support. -+ -+2013-02-06 Senthil Kumar Selvaraj -+ -+ * emultempl/avrelf.em (avr_elf_before_parse): New function. -+ (LDEMUL_BEFORE_PARSE): Define. -+ -+2013-02-06 Alan Modra -+ -+ PR ld/15096 -+ * emultempl/elf32.em: Revert 2013-02-04, 2013-01-22 and 2013-01-21. -+ * emultempl/alphaelf.em: Revert 2013-02-04. -+ * emultempl/cr16elf.em: Likewise. -+ * emultempl/crxelf.em: Likewise. -+ * emultempl/hppaelf.em: Likewise. -+ * emultempl/ia64elf.em: Likewise. -+ * emultempl/mipself.em: Likewise. -+ * NEWS: Revert 2013-01-21. -+ -+2013-02-04 H.J. Lu -+ -+ PR ld/15096 -+ * emultempl/alphaelf.em (alpha_after_parse): Call -+ gld${EMULATION_NAME}_after_parse instead of after_parse_default. -+ * emultempl/cr16elf.em (cr16elf_after_parse): Likewise. -+ * emultempl/crxelf.em (crxelf_after_parse): Likewise. -+ * emultempl/hppaelf.em (hppaelf_after_parse): Likewise. -+ * emultempl/mipself.em (mips_after_parse): Likewise. -+ -+ * emultempl/ia64elf.em (gld${EMULATION_NAME}_after_parse): Renamed -+ to ... -+ (gld_${EMULATION_NAME}_after_parse): This. Call -+ gld${EMULATION_NAME}_after_parse instead of after_parse_default. -+ (LDEMUL_AFTER_PARSE): Set to gld_${EMULATION_NAME}_after_parse. -+ -+ * emultempl/elf32.em (new_dtags_set): New variable. -+ (gld${EMULATION_NAME}_before_parse): Don't set link_info.new_dtags -+ here. -+ (gld${EMULATION_NAME}_after_parse): New function. -+ (ld_${EMULATION_NAME}_emulation): Replace after_parse_default' -+ with gld${EMULATION_NAME}_after_parse. -+ (gld${EMULATION_NAME}_handle_option): Set new_dtags_set to TRUE -+ when setting link_info.new_dtags. -+ -+2013-01-25 Kai Tietz -+ -+ * deffilep.y (def_image_name): Adjust type of base-address -+ argument. -+ (%union): Add new type bfd_vma as vma. -+ (VMA): New rule. -+ (opt_base): Use VMA instead of NUMBER rule to evaluate value. -+ (def_file_print): Use bfd's fprintf_vma to output base-address. -+ -+2013-01-24 Nick Clifton -+ -+ * NEWS: Mention support for V850E3V5 architecture. -+ -+2013-01-23 Martin Koegler -+ -+ PR ld/15041 -+ * scripttempl/pep.sc (.pdata): Only accept .pdata sections. -+ (.xdata): Similarly. -+ (.debug_frame): Similarly. -+ -+2013-01-23 Georg-Johann Lay -+ -+ PR ld/15037 -+ * scripttempl/avr.sc (.eeprom): Keep it. -+ -+2013-01-23 Leif Ekblad -+ -+ * Makefile.am (ALL_64_EMULATION_SOURCES): Add eelf64rdos.c. -+ (eelf64rdos.c): New rule. -+ * emulparams/elf64rdos.sh: New file. -+ * configure.tgt (x86_64-*-rdos*): Use above. -+ * Makefile.in: Regenerate. -+ -+2013-01-22 Roland McGrath -+ -+ * emultempl/elf32.em (gld${EMULATION_NAME}_before_parse): Set -+ new_dtags to TRUE for *-*-nacl* targets. -+ -+2013-01-21 Mike Frysinger -+ -+ * emultempl/elf32.em (gld${EMULATION_NAME}_before_parse): Set -+ link_info.new_dtags to TRUE for linux/gnu targets. -+ * NEWS: Mention new dtags default. -+ -+2013-01-19 H.J. Lu -+ -+ * Makefile.am (HOSTING_SCRT0): New. -+ -+ * configure.host (HOSTING_SCRT0): New. Used for PIE. -+ -+ * configure.in (HOSTING_SCRT0): New AC_SUBST. -+ -+ * Makefile.in: Regenerated. -+ * configure: Likewise. -+ -+2013-01-18 Mike Frysinger -+ -+ * NEWS: Mention change in behavior with --enable-new-dtags. -+ * ld.texinfo (Options): Clarify --enable-new-dtags behavior. -+ -+2013-01-14 Leif Ekblad -+ Alan Modra -+ -+ * ld.texinfo (-Tldata-segment): Describe. -+ * ldlex.h (OPTION_TLDATA_SEGMENT): New enum value. -+ * lexsup.c (ld_options): Add -Tldata-segment. -+ (parse_args): Handle OPTION_TLDATA_SEGMENT. -+ * scripttempl/elf.sc: Support LARGE_DATA_ADDR. -+ -+2013-01-10 H.J. Lu -+ -+ * deffilep.y: Remove trailing white spaces. -+ * elf-hints-local.h: Likewise. -+ * ldexp.c: Likewise. -+ * ldlang.h: Likewise. -+ * ldmisc.c: Likewise. -+ * ldwrite.c: Likewise. -+ * pe-dll.c: Likewise. -+ * emulparams/criself.sh: Likewise. -+ * emulparams/crislinux.sh: Likewise. -+ * emulparams/elf32_tic6x_le.sh: Likewise. -+ * emulparams/elf32bmipn32-defs.sh: Likewise. -+ * emulparams/elf32mb_linux.sh: Likewise. -+ * emulparams/elf32mep.sh: Likewise. -+ * emulparams/elf32microblaze.sh: Likewise. -+ * emulparams/elf32ppc.sh: Likewise. -+ * emulparams/elf64_s390.sh: Likewise. -+ * emulparams/elf64alpha.sh: Likewise. -+ * emulparams/elf_s390.sh: Likewise. -+ * emulparams/elf_x86_64.sh: Likewise. -+ * emulparams/tic80coff.sh: Likewise. -+ * emultempl/aix.em: Likewise. -+ * emultempl/avrelf.em: Likewise. -+ * emultempl/cr16elf.em: Likewise. -+ * emultempl/pe.em: Likewise. -+ * emultempl/pep.em: Likewise. ++ * emultempl/metagelf.em: Update bfd target vector naming. ++ * emultempl/nios2elf.em: Likewise. + * emultempl/spuelf.em: Likewise. + * emultempl/tic6xdsbt.em: Likewise. + -+2013-01-10 Will Newton ++2014-04-22 Christian Svensson + -+ * Makefile.am: Add Meta. -+ * Makefile.in: Regenerate. -+ * configure.tgt: Add Meta. -+ * emulparams/elf32metag.sh: New file. -+ * emultempl/metagelf.em: New file. -+ -+2013-01-09 Alan Modra -+ -+ * emulparams/elf_x86_64.sh (LARGE_BSS_AFTER_BSS): Define. -+ * emulparams/elf32_x86_64.sh: Likewise. -+ * emulparams/elf_k1om.sh: Likewise. -+ * emulparams/elf_l1om.sh: Likewise. -+ * scripttempl/elf.sc (LARGE_BSS): Define rather than appending to -+ OTHER_BSS_SECTIONS. Substitute in script. -+ -+2013-01-08 Leif Ekblad -+ -+ * scripttempl/elf.sc (RODATA_ADDR): Typo fix. -+ -+2013-01-08 Alan Modra -+ -+ * emultempl/elf32.em (gld${EMULATION_NAME}_check_ld_so_conf): Replace -+ "name" param with a bfd_link_needed_list pointer. Update caller. -+ (gld${EMULATION_NAME}_check_ld_elf_hints): Likewise. -+ -+2013-01-08 Alan Modra -+ -+ * Makefile.am (ALL_EMULATION_SOURCES): Correct eavrxmega entries. ++ * Makefile.am: Remove openrisc and or32 support. Add support for or1k. ++ * configure.tgt: Likewise. ++ * emulparams/elf32or1k.sh: New file. ++ * emulparams/elf32or1k_linux.sh: New file. ++ * emulparams/elf32openrisc.sh: Delete. ++ * emulparams/or32.sh: Delete. ++ * emulparams/or32elf.sh: Delete. ++ * scripttempl/or32.sc: Delete. + * Makefile.in: Regenerate. + -+2013-01-07 H.J. Lu ++2014-04-21 Richard Henderson + -+ * lexsup.c (ld_options): Add fuse-ld= for GCC linker option -+ compatibility. ++ * emultempl/alphaelf.em (alpha_after_parse): Enable 2 relax passes. + -+2013-01-07 Patrice Dumas ++2014-04-16 Steve Ellcey + -+ * ld.texinfo: Replace @ with @@ when it is part of the text. -+ Correct ordering of M68HC11 entry. ++ * emultempl/elf32.em: Include safe-ctype.h. + -+2013-01-04 Juergen Urban ++2014-04-16 Steve Ellcey + -+ * configure.tgt: Support ELF files for Sony Playstation 2 (for -+ ps2dev and ps2sdk). -+ * emulparams/elf32lr5900n32.sh: Create linker script for Sony -+ Playstation 2 ELF files using MIPS ABI n32. -+ * emulparams/elf32lr5900.sh: Create linker script for Sony -+ Playstation 2 ELF files using MIPS ABI o32. -+ * Makefile.am: Add linker scripts for Sony Playstation 2 ELF ++ * ldbuildid.c (generate_build_id): Add ATTRIBUTE_UNUSED to size arg. ++ ++2014-04-09 Nick Clifton ++ ++ * Makefile.am (default-manifest.o): Remove rule. ++ (EMUL_EXTRA_BINARIES): Delete. ++ (ALL_EMUL_EXTRA_BINARIES): Delete. ++ (ld_new_DEPENDENCIES): Remove EMUL_EXTRA_BINARIES. ++ (install-data-local): Remove EMUL_EXTRA_BINARIES. ++ * Makefile.in: Regenerate. ++ * configure.in (all_emul_extra_binaries): Delete. ++ (EMUL_EXTRA_BINARIES): Remove. ++ * configure: Regenerate. ++ * configure.tgt (target_extra_binaries): Delete. ++ * emultempl/default-manifest.rc: Delete. ++ * ld.texinfo: Remove discussion of default manifest. ++ * emulparams/i386pe.sh (DEFAULT_MANIFEST): Delete. ++ * emulparams/i386pep.sh (DEFAULT_MANIFEST): Delete. ++ ++2014-04-09 Alan Modra ++ ++ * emultempl/spuelf.em: Include safe-ctype.h, remove duplicate errno.h. ++ * emultempl/nds32elf.em: Include bfd_stdint.h. ++ * po/POTFILES.in: Regenerate. ++ ++2014-04-09 Alan Modra ++ ++ * emultempl/ppc32elf.em (no_zero_padding, ppc_finish): New functions. ++ (LDEMUL_FINISH): Define. ++ ++2014-04-08 Nick Clifton ++ ++ * scripttempl/pe.sc (R_RSRC): Remove default manifest. ++ * scripttempl/pep.sc (R_RSRC): Remove default manifest. ++ ++2014-04-08 Jon TURNEY ++ ++ * emultempl/elf32.em (id_note_section_size, read_hex, write_build_id): ++ Move code for parsing build-id option and calculating the build-id to... ++ * ldbuildid.c: New file. ++ * ldbuildid.h: New file. ++ * Makefile.am (CFILES, HFILES, OFILES, ld_new_SOURCES): Add new + files. ++ * Makefile.in: Regenerate. ++ * ld.texinfo: Update --build-id description to mention COFF ++ support. ++ * NEWS: Mention support for COFF build ids. ++ * emultempl/pe.em (gld${EMULATION_NAME}_handle_option): ++ (pecoff_checksum_contents, write_build_id, setup_build_id) ++ (gld_${EMULATION_NAME}_after_open): Handle and implement ++ build-id option. ++ * emultempl/pep.em: Likewise. + -+2013-01-02 H.J. Lu ++2014-04-04 Cary Coutant + -+ * ldver.c (ldversion): Update copyright year to 2013. ++ PR gold/16804 ++ * ld.texinfo: Document optional comma following output section ++ command and overlay command. + -+For older changes see ChangeLog-2012 ++2014-04-04 Alan Modra ++ ++ * ldlang.c (lang_size_sections_1 ): Use ++ current "fill", not "output_section_statement->fill". ++ ++2014-03-31 Nick Clifton ++ ++ PR ld/16744 ++ * emultempl/elf32.em (_after_open): Create a .note.GNU-stack ++ section when performing a relocatable link with -z [no]execstack ++ specified. ++ ++2014-03-27 H.J. Lu ++ ++ PR ld/16756 ++ * ldmain.c (symbol_warning): New function. ++ (warning_callback): Use it. Scan all input files for a reference ++ to SYMBOL. ++ ++2014-03-21 Christopher Faylor ++ ++ * ld.texinfo: Document change in handling of --enable-auto-image-base. ++ * emultempl/pe.em (pe_auto_image_base): Set to default base. ++ (gld_${EMULATION_NAME}_list_options): Change usage message to reflect ++ optional --enable-auto-image-base argument. ++ (gld${EMULATION_NAME}_handle_option): Handle optional ++ --enable-auto-image-base argument. ++ (compute_dll_image_base): Eliminate constant. Use pe_auto_image_base. ++ ++2014-03-19 Nick Clifton ++ ++ * Makefile.am (default-manifest.o): Use WINDRES_FOR_TARGET. ++ * Makefile.in: Regenerate. ++ * emultempl/default-manifest.rc: Fix typo. ++ * scripttempl/pe.sc (R_RSRC): Fix default-manifest exclusion. ++ (.rsrc): Add SUBALIGN(4). Remove SORT. ++ * scripttempl/pep.sc: Likewise. ++ ++2014-03-17 Christopher Faylor ++ ++ * Makefile.am: Use host version of windres. ++ * Makefile.in: Regenerate. ++ ++2014-03-14 Romain Geissler ++ Alan Modra ++ ++ * ldlang.h (full_name_provided): New input flag. ++ * ldlang.c (new_afile): Don't use lang_input_file_is_search_file_enum ++ for -l:namespec. Instead use lang_input_file_is_l_enum with ++ full_name_provided flag. ++ * ldlfile.c (ldfile_open_file_search): Don't complete lib name if ++ full_name_provided flag is set. ++ * emultempl/elf32.em (gld${EMULATION_NAME}_open_dynamic_archive): ++ Handle full_name_provided libraries. Tidy EXTRA_SHLIB_EXTENSION ++ support. Set DT_NEEDED for -l:namespec as namespec. ++ * emultempl/aix.em (ppc_after_open_output): Handle full_name_provided. ++ * emultempl/linux.em (gld${EMULATION_NAME}_open_dynamic_archive): ++ Don't handle full_name_provided libraries. ++ * emultempl/pe.em (gld${EMULATION_NAME}_open_dynamic_archive): Ditto. ++ * emultempl/pep.em (gld${EMULATION_NAME}_open_dynamic_archive): Ditto. ++ * emultempl/vms.em (gld${EMULATION_NAME}_open_dynamic_archive): Ditto. ++ ++2014-03-12 Alan Modra ++ ++ * Makefile.in: Regenerate. ++ ++2014-03-05 Alan Modra ++ ++ Update copyright years. ++ ++2014-03-04 Nick Clifton ++ ++ * Makefile.am (ALL_EMUL_EXTRA_BINARIES): Remove default-manifest. ++ * Makefile.in: Regenerate. ++ ++2014-02-27 Yuri Gribov ++ ++ * emultempl/armelf.em (OPTION_LONG_PLT): Define. ++ (PARSE_AND_LIST_LONGOPTS): Add long-plt. ++ (PARSE_AND_LIST_OPTIONS): Likewise. ++ (PARSE_AND_LIST_ARGS_CASES): Handle long-plt. ++ * ld.texinfo: Document --long-plt. ++ ++2014-02-27 Alan Modra ++ ++ * emulparams/elf32ppcvxworks.sh: Source plt_unwind.sh and ++ use ppc32elf.em. ++ * emultempl/ppc32elf.em (ppc_after_open): Don't compile for ++ vxworks. ++ (LDEMUL_AFTER_OPEN): Don't set for vxworks. ++ (PARSE_AND_LIST_LONGOPTS, PARSE_AND_LIST_OPTIONS): Exclude ++ -secure-plt, -bss-plt and -sdata-got when vxworks. ++ ++2014-02-27 Nick Clifton ++ ++ * configure.in (all_emul_extra_binaries): New variable. Populated ++ by invoking configure.tgt. ++ (EMUL_EXTRA_BINARIES): New substitution. ++ * configure: Regenerate. ++ * configure.tgt (target_extra_binaries): New variable. Set to ++ default-manifest.o for Cygwin and MinGW targets. ++ * Makefile.am (EMUL_EXTRA_BINARIES): New variable. Initialised ++ by the configure script. ++ (ALL_EMUL_EXTRA_BINARIES): New variable. ++ (default-manifest.o): New rule to build the default manifest. ++ (ld_new_DEPENDENCIES): Add EMUL_EXTRA_BINARIES. ++ (install-data-local): Add EMUL_EXTRA_BINARIES. ++ * Makefile.in: Regenerate. ++ * ld.texinfo: Document default manifest support. ++ * emulparams/i386pe.sh (DEFAULT_MANIFEST): Define. ++ * emulparams/i386pep.sh (DEFAULT_MANIFEST): Define. ++ * emultempl/default-manifest.rc: New file. ++ * scripttempl/pe.sc (R_RSRC): Include DEFAULT_MANIFEST, if defined. ++ * scripttempl/pep.sc (R_RSRC): Likewise. ++ ++2014-02-26 Dan Mick ++ ++ PR ld/16569 ++ * ldcref.c (cref_sort_array): Compare unmangled names unless ++ demanglng has been requiested. ++ (output_one_cref): Output unmangled name unless demangling has ++ been requested. ++ ++2014-02-19 Igor Zamyatin ++ H.J. Lu ++ ++ * emulparams/elf_x86_64.sh (TINY_READONLY_SECTION): New. ++ ++2014-02-19 Alan Modra ++ ++ * emultempl/ppc64elf.em (params): Init new field. ++ (ppc_create_output_section_statements): Set params.save_restore_funcs ++ default. ++ (PARSE_AND_LIST_*): Add support for --save-restore-funcs and ++ --no-save-restore-funcs. ++ ++2014-02-17 Alan Modra ++ ++ * emultemps/ppc64elf.em (params): New static struct replacing ++ various other static vars. Adjust code throughout file. ++ ++2014-02-17 Alan Modra ++ ++ * emultempl/ppc32elf.em (ppc_after_open_output): Really enable ++ ppc476 workaround for ld -r. ++ ++2014-02-12 Alan Modra ++ ++ * emultempl/ppc32elf.em (pagesize): New static var. ++ (ppc_after_open_output): Set params.pagesize_p2 from pagesize. ++ (PARSE_AND_LIST_ARGS_CASES): Adjust to use pagesize. ++ ++2014-02-11 Andrew Pinski ++ ++ * emulparams/aarch64linux32.sh (LIBPATH_SUFFIX): Change to ilp32. ++ (ELF_INTERPRETER_NAME): Define. ++ * emulparams/aarch64linux32b.sh (ELF_INTERPRETER_NAME): Define. ++ ++2014-02-10 Alan Modra ++ ++ * po/ld.pot: Regenerate. ++ ++2014-02-03 Alan Modra ++ ++ * emultempl/ppc32elf.em (no_tls_get_addr_opt, emit_stub_syms) ++ plt_style): Delete. Adjust all refs to instead use.. ++ (params): ..this. New variable. ++ (ppc_after_open_output): New function. Tweak params and pass to ++ ppc_elf_link_params. ++ (ppc_after_open): Adjust ppc_elf_select_plt_layout call. ++ (ppc_before_allocation): Adjust ppc_elf_tls_setup call. Enable ++ relaxation for ppc476 workaround. ++ (PARSE_AND_LIST_*): Add --{no-,}ppc476-workaround support. ++ (LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS): Define. ++ ++2014-02-02 Sebastian Huber ++ ++ * ld/ld.texinfo: Change ALIGN_WITH_INPUT documentation. ++ * ld/ldlang.c (lang_size_sections_1): Add dotdelta ++ variable which reflects the VMA change due to alignment ++ requirements. Use dotdelta do change the LMA if ++ ALIGN_WITH_INPUT is requested. ++ ++2014-02-01 Hans-Peter Nilsson ++ ++ * emultempl/mmix-elfnmmo.em (mmix_after_allocation): Fix typo in ++ call to bfd_set_section_vma exposed by recent bfd_set_section_vma ++ change. ++ ++2014-01-30 Sandra Loosemore ++ ++ * Makefile.am (enios2elf.c, enios2linux.c): Update dependencies. ++ * Makefile.in: Regenerated. ++ * emulparams/nios2elf.sh (EXTRA_EM_FILE): Set. ++ * emulparams/nios2linux.sh (EXTRA_EM_FILE): Set. ++ * emultempl/nios2elf.em: New file. ++ * gen-doc.texi (NIOSII): Set. ++ * ld.texinfo (NIOSII): Set. ++ ++2014-01-28 Nick Clifton ++ ++ * Makefile.am: Remove obsolete MSP430 emulations. ++ * configure.tgt: Likewise. ++ * emulparams/msp430all.sh: Likewise. ++ * Makefile.in: Regenerate. ++ ++2014-01-24 H.J. Lu ++ ++ PR ld/16498 ++ * emultempl/elf32.em (gld${EMULATION_NAME}_place_orphan): Improve ++ orphaned TLS section handling. ++ ++2014-01-24 Alan Modra ++ ++ * ldlang.c (lang_output_section_find_by_flags): Be careful to ++ test look->bfd_section->flags if available rather than ++ look->flags. Separate SEC_THREAD_LOCAL handling from ++ SEC_READONLY loop, and rewrite. ++ ++2014-01-22 Alan Modra ++ ++ * ldlang.c (asneeded_list_head, asneeded_list_tail): New vars. ++ (lang_init): Initialise them. ++ (lang_print_asneeded): New function. ++ (lang_process): Call lang_print_asneeded. ++ * ldlang.h (struct asneeded_minfo): New. ++ (asneeded_list_tail): Declare. ++ * ldmain.c (add_archive_element): Improve archive map heading. ++ * ldmisc.c (minfo): Stash --as-needed info. ++ ++2014-01-22 Alan Modra ++ ++ * ld.h (struct map_symbol_def): Move to.. ++ * ldlang.h: ..here. ++ * ldlang.c (print_assignment): Don't set expld.assign_name to dot. ++ ++2014-01-22 Alan Modra ++ ++ * ld.texinfo (Output Section Discarding): Mention assigning to dot ++ as a way of keeping otherwise empty sections. ++ * ldexp.c (is_dot, is_value, is_sym_value, is_dot_ne_0, ++ is_dot_plus_0, is_align_conditional): New predicates. ++ (exp_fold_tree_1): Set SEC_KEEP when assigning to dot inside an ++ output section, except for some special cases. ++ * scripttempl/elfmicroblaze.sc: Use canonical form to align at ++ end of .heap and .stack. ++ ++2014-01-20 Marcus Shawcroft ++ ++ * emulparams/aarch64linuxb.sh (ELF_INTERPRETER_NAME): Define. ++ ++2014-01-20 Marcus Shawcroft ++ ++ * emulparams/aarch64linux.sh (ELF_INTERPRETER_NAME): Define. ++ ++2014-01-20 Alan Modra ++ ++ * ldlang.h (struct lang_definedness_hash_entry): Add by_object and ++ by_script. Make iteration a single bit field. ++ (lang_track_definedness, lang_symbol_definition_iteration): Delete. ++ (lang_symbol_defined): Declare. ++ * ldlang.c (lang_statement_iteration): Expand comment a little. ++ (lang_init ): Make it bigger. ++ (lang_track_definedness, lang_symbol_definition): Delete. ++ (lang_definedness_newfunc): Update. ++ (lang_symbol_defined): New function. ++ (lang_update_definedness): Create entries here. Do track whether ++ script definition of symbol is valid, even when also defined in ++ an object file. ++ * ldexp.c (fold_name ): Update. ++ (fold_name ): Allow self-assignment for absolute symbols ++ defined in a linker script. ++ ++2014-01-20 Guy Martin ++ Alan Modra ++ ++ * ldlang.h (lang_output_section_get): Define. ++ * ldlang.c (lang_output_section_get): Likewise. ++ (init_os): Set the output_section userdata to the output ++ section statement. ++ * emultempl/hppaelf.em: Use lang_output_section_get instead of ++ lang_output_section_find where applicable. ++ * emultempl/aarch64elf.em: Likewise. ++ * emultempl/aix.em: Likewise. ++ * emultempl/armelf.em: Likewise. ++ * emultempl/m68hc1xelf.em: Likewise. ++ * emultempl/metagelf.em: Likewise. ++ * emultempl/mipself.em: Likewise. ++ * emultempl/ppc64elf.em: Likewise. ++ * emultempl/spuelf.em: Likewise. ++ ++2014-01-17 Alan Modra ++ ++ * genscripts.sh (COMPILE_IN): Don't set if already set. ++ * emulparams/nds32elf.sh: Don't clear EMULATION_LIBPATH, set ++ COMPILE_IN=no. ++ * emulparams/nds32elf16m.sh: Likewise. ++ * emulparams/nds32elf_linux.sh: Likewise. ++ * emultempl/aix.em: Test COMPILE_IN value is "yes". ++ * emultempl/armcoff.em: Likewise. ++ * emultempl/elf32.em: Likewise. ++ * emultempl/generic.em: Likewise. ++ * emultempl/gld960.em: Likewise. ++ * emultempl/gld960c.em: Likewise. ++ * emultempl/linux.em: Likewise. ++ * emultempl/lnk960.em: Likewise. ++ * emultempl/m68kcoff.em: Likewise. ++ * emultempl/sunos.em: Likewise. ++ * emultempl/ticoff.em: Likewise. ++ ++2014-01-16 H.J. Lu ++ ++ PR ld/16456 ++ * genscripts.sh: Don't search directory with LIBPATH_SUFFIX_SKIP ++ suffix. ++ * emulparams/elf32_x86_64.sh (LIBPATH_SUFFIX_SKIP): Set to 64 ++ for elf32_x86_64 emulation. ++ * emulparams/elf_i386.sh (LIBPATH_SUFFIX_SKIP): Set to 64 ++ for elf_i386 emulation. ++ ++2014-01-16 Alan Modra ++ ++ * ld.h (fat_section_userdata_type, get_userdata): Move to.. ++ * ldlang.h (input_section_userdata_type, get_userdata): ..here. ++ * ldlang.c (init_map_userdata): Delete. Fold into.. ++ (sort_def_symbol): ..here. Don't attach input section userdata ++ to output sections or global bfd sections. ++ (lang_map): Don't pre-allocate input section userdata. ++ (init_os): Don't allocate userdata for output sections. ++ (print_all_symbols): Update. ++ ++2014-01-15 H.J. Lu ++ ++ * emultempl/elf32.em (gld${EMULATION_NAME}_before_allocation): ++ Silence uninitialized warning on ehdr_start_save with older ++ GCC. ++ ++2014-01-15 Alan Modra ++ ++ * emultempl/elf32.em (gld${EMULATION_NAME}_before_allocation): Define ++ __ehdr_start before size_dynamic_sections and restore afterwards. ++ ++2014-01-10 Alan Modra ++ ++ PR ld/14207 ++ PR ld/16322 ++ PR binutils/16323 ++ * ldlang.c (lang_size_sections): Remove unneeded RELRO base ++ adjust. Tidy comments. ++ * ld.texinfo (DATA_SEGMENT_RELRO_END): Correct description. ++ ++2014-01-10 Hans-Peter Nilsson ++ ++ * emulparams/crislinux.sh (COMMONPAGESIZE): Define. ++ ++2014-01-08 H.J. Lu ++ ++ PR ld/14207 ++ PR ld/16322 ++ PR binutils/16323 ++ * ldlang.c (lang_size_sections): Properly align RELRO base. ++ ++2014-01-08 H.J. Lu ++ ++ * ldver.c (ldversion): Update copyright year to 2014. ++ ++For older changes see ChangeLog-2013 + -+Copyright (C) 2013 Free Software Foundation, Inc. ++Copyright (C) 2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -2554692,6 +2567761,895 @@ index 0000000..4a9f308 +fill-column: 74 +version-control: never +End: +diff --git a/ld/ChangeLog-2013 b/ld/ChangeLog-2013 +new file mode 100644 +index 0000000..b996faf +--- /dev/null ++++ b/ld/ChangeLog-2013 +@@ -0,0 +1,883 @@ ++2013-12-20 H.J. Lu ++ ++ * emulparams/elf_k1om.sh (IREL_IN_PLT): Define. ++ * emulparams/elf_l1om.sh (IREL_IN_PLT): Likewise. ++ ++2013-12-13 Kuan-Lin Chen ++ Wei-Cheng Wang ++ Hui-Wen Ni ++ ++ * Makefile.am (ALL_EMULATION_SOURCES): Add nds32 target. ++ * Makefile.in: Regenerate. ++ * configure.tgt: Add case for nds32*le-*-elf*, nds32*be-*-elf*, ++ nds32*le-*-linux-gnu*, and nds32*be-*-linux-gnu*. ++ * emulparams/nds32belf.sh: New file for nds32. ++ * emulparams/nds32belf_linux.sh: Likewise. ++ * emulparams/nds32belf16m.sh: Likewise. ++ * emulparams/nds32elf.sh: Likewise. ++ * emulparams/nds32elf_linux.sh: Likewise. ++ * emulparams/nds32elf16m.sh: Likewise. ++ * emultempl/nds32elf.em: Likewise. ++ * scripttempl/nds32elf.sc}: Likewise. ++ * gen-doc.texi: Set NDS32. ++ * ld.texinfo: Set NDS32. ++ * NEWS: Announce Andes nds32 support. ++ ++2013-12-11 H.J. Lu ++ ++ * ld.texinfo: Remove shared object from -Ttext-segment. ++ ++2013-12-10 Roland McGrath ++ ++ * Makefile.am (install-exec-local): Prefix libtool invocation with ++ $(INSTALL_PROGRAM_ENV). ++ * Makefile.in: Regenerate. ++ ++2013-12-07 Mike Frysinger ++ ++ * ChangeLog-2008: Remove +x file mode. ++ * emulparams/bfin.sh: Likewise. ++ * emulparams/elf32bmipn32.sh: Likewise. ++ * emulparams/elf32fr30.sh: Likewise. ++ * emulparams/elf32frv.sh: Likewise. ++ * emulparams/elf32iq10.sh: Likewise. ++ * emulparams/elf32iq2000.sh: Likewise. ++ * emulparams/elf32mep.sh: Likewise. ++ * emulparams/elf32openrisc.sh: Likewise. ++ * emulparams/elf64bmip.sh: Likewise. ++ * emulparams/elf64hppa.sh: Likewise. ++ * emulparams/i386beos.sh: Likewise. ++ ++2013-11-26 H.J. Lu ++ ++ PR ld/16259 ++ * Makefile.am (HOSTING_SLIBS): New. ++ * configure.host (HOSTING_SLIBS): New. Used for PIE. ++ * configure.in (HOSTING_SLIBS): New AC_SUBST. ++ * Makefile.in: Regenerated. ++ * configure: Likewise. ++ ++2013-11-22 Cory Fields ++ ++ * pe-dll.c (fill_edata): Only use a real timestamp if ++ --insert-timestamp was used. ++ * emultempl/pe.em: Add the --insert-timestamp option. ++ * emultempl/pep.em: Likewise for 64bit. ++ * ld.texinfo: Document the --insert-timestamp option. ++ ++2013-11-22 Senthil Kumar Selvaraj ++ ++ * scripttempl/avr.sc: Set .data section's LMA to next available ++ address in text region. ++ ++2013-11-21 Andrew Pinski ++ ++ * Makefile.am (ALL_64_EMULATION_SOURCES): Add eaarch64linux32.c ++ and eaarch64linux32b.c ++ (eaarch64linux32.c): New target. ++ (eaarch64linux32b.c): Likewise. ++ * Makefile.in: Regenerate. ++ * configure.tgt (aarch64_be-*-linux*): Add ++ aarch64linux32 and aarch64linux32b to targ_extra_libpath. ++ (aarch64-*-linux*): Likewise. ++ * emulparams/aarch64elf32.sh (SEPARATE_GOTPLT): Change to 12 (3 words). ++ * emulparams/aarch64linux32.sh: New file. ++ * emulparams/aarch64linux32b.sh: New file. ++ ++2013-11-21 Andrew Pinski ++ ++ * configure.tgt (aarch64_be-*-linux*): Split out the linux targets ++ into targ_extra_libpath. ++ (aarch64-*-linux*): Likewise. ++ ++2013-11-21 Nick Clifton ++ ++ PR ld/16192 ++ * pe-dll.c (pe_create_runtime_relocator_reference): Zero the ++ newly allocated idata5 block. ++ ++2013-11-20 Nick Clifton ++ ++ * scripttempl/elf32msp430.sc (.data): Set the based on the next ++ free location in the text memory region, not a computation based ++ upon the size of the text section. Orphaned sections or other ++ linker scripts might insert new sections between the .text section ++ and the .data section. ++ * scripttempl/elf32msp430_3.sc (.data): Likewise. ++ ++2013-11-19 Roland McGrath ++ Alan Modra ++ ++ * emultempl/elf32.em (gld${EMULATION_NAME}_before_allocation): ++ Don't use bfd_elf_record_link_assignment to mark __ehdr_start ++ hidden. Instead, just do it directly here, and only if it was ++ referenced but not defined. ++ ++2013-11-18 Chung-Lin Tang ++ ++ * emulparams/nios2linux.sh: New emulation file. ++ * configure.tgt: Add nios2*-*-linux* emulation case. ++ * Makefile.am (enios2linux.c): New emulation entry. ++ * Makefile.in: Regenerate. ++ ++2013-10-14 Nick Clifton ++ ++ * emultempl/aix.em (_read_file): Close file at end of function. ++ ++2013-10-10 Roland McGrath ++ ++ * ldmisc.c (vfinfo): Use Boolean ? "" : ":" in place of ":" + Boolean. ++ It silences some compilers' warnings and is much less bizarre to read. ++ ++2013-10-09 Roland McGrath ++ ++ * emultempl/elf32.em (id_note_section_size): Use ATTRIBUTE_UNUSED ++ rather than a dummy assignment for unused parameter. ++ * plugin.c (get_input_file, release_input_file): Likewise. ++ ++2013-10-09 Nick Clifton ++ ++ PR ld/16028 ++ * ldmain.c (add_keepsyms_file): Close file at end of function. ++ ++2013-10-03 Will Newton ++ ++ * emulparams/aarch64elf.sh: Add IREL_IN_PLT. ++ * emulparams/aarch64elf32.sh: Likewise. ++ ++2013-09-30 Nick Clifton ++ ++ * emulparams/msp430all.sh: Update ARCH names. ++ ++2013-09-24 Alan Modra ++ ++ * emulparams/elf32ppccommon.sh (LIBPATH_SUFFIX): Provide 32-bit ++ and cross-endian values. ++ * emulparams/elf64ppc.sh: Source elf32ppccomon.sh. Delete duplicate, ++ and unset unwanted variables. ++ ++2013-09-24 Alan Modra ++ ++ * genscripts.sh (LIB_PATH): Don't exclude libdir or tooldir when ++ sysrooted. Also, don't always add tooldir when non-sysrooted. ++ Instead add both when native and tooldir also when TOOL_DIR is ++ defined. Always prepend '=' to paths when sysrooted. Always ++ put paths with LIBPATH_SUFFIX first in search order. ++ ++2013-09-20 Chung-Lin Tang ++ ++ * Makefile.am (enios2elf.c): Change tdir_nios2 to tdir_nios2elf. ++ * Makefile.in: Regenerate. ++ ++2013-09-20 Alan Modra ++ ++ * configure: Regenerate. ++ ++2013-09-18 Tristan Gingold ++ ++ * NEWS: Add marker for 2.24. ++ ++2013-09-17 Nick Clifton ++ ++ PR ld/15957 ++ * deffilep.y (def_file_add_directive): Avoid readin past end of ++ buffer. ++ ++2013-08-28 Nick Clifton ++ ++ PR ld/15896 ++ * ld.texinfo: Fix uses of MB abbreviation. ++ ++2013-08-26 Roland McGrath ++ ++ * emulparams/elf_i386_nacl.sh (ARCH): Set to i386:nacl. ++ * emulparams/elf_x86_64_nacl.sh (ARCH): Set to i386:x86-64:nacl. ++ * emulparams/elf32_x86_64_nacl.sh (ARCH): Set to i386:x64-32:nacl. ++ ++2013-08-23 Roland McGrath ++ ++ * emulparams/elf_nacl.sh (nacl_rodata_addr): Don't add in ++ SIZEOF_HEADERS here; elf.sc does it already. ++ ++2013-08-23 Nick Clifton ++ ++ PR ld/15839 ++ * scripttempl/avr.sc: Do not include gc'able sections into general ++ sections during relocatable links. ++ ++2013-08-22 Christian Franke ++ ++ * emultempl/pe.em: Add --disable-large-address-aware option. ++ * ld.texinfo (--disable-large-address-aware): Add documentation. ++ ++2013-08-14 Clemens Lang ++ ++ * ldexp.c: Add LOG2CEIL() builtin function to linker script language ++ * ldgram.y: Likewise ++ * ldlex.l: Likewise ++ * NEWS: Mention the new feature. ++ * ld.texinfo: Document the new feature. ++ ++2013-07-19 Sebastian Huber ++ ++ * ldgram.y: Add ALIGN_WITH_INPUT output section attribute. ++ * ldlang.c: Likewise. ++ * ldlang.h: Likewise. ++ * ldlex.l: Likewise. ++ * mri.c: Likewise. ++ * ld.texinfo: Document new feature. ++ * NEWS: Mention new feature. ++ ++2013-07-18 Roland McGrath ++ ++ * emultempl/armelf.em (elf32_arm_add_stub_section): Take third ++ argument ALIGNMENT_POWER, use it instead of constant 3. ++ ++2013-07-08 Jeff Law ++ ++ * scripttempl/elf.sc: Handle function names and other text after ++ .text.unlikely too. ++ ++2013-07-08 Tristan Gingold ++ ++ * scripttempl/ia64vms.sc: Add support of per data and per function ++ sections. ++ ++2013-07-01 Alan Modra ++ ++ * emultempl/ppc64elf.em: (ppc_layout_sections_again): Call ++ ppc64_elf_set_toc rather than ppc64_elf_toc/_bfd_set_gp_value. ++ (gld${EMULATION_NAME}_after_allocation): Likewise. ++ ++2013-06-26 Yufeng Zhang ++ ++ * emulparams/aarch64elf32.sh: New file. ++ ++2013-06-26 Yufeng Zhang ++ ++ * Makefile.am (ALL_64_EMULATION_SOURCES): Add eaarch64elf32b.c. ++ (eaarch64elf32b.c): New dependency and rule. ++ * Makefile.in: Re-generated. ++ * configure.tgt (aarch64-*-elf): Add aarch64elf32b. ++ (aarch64_be-*-elf, aarch64_be-*-linux*, aarch64-*-linux*): Likewise. ++ * emulparams/aarch64elf32b.sh: New file. ++ ++2013-06-26 Yufeng Zhang ++ ++ * Makefile.am (ALL_64_EMULATION_SOURCES): Add eaarch64elf32.c. ++ (eaarch64elf32.c): New dependency and rule. ++ * Makefile.in: Re-generated. ++ * configure.tgt (aarch64-*-elf): Add aarch64elf32. ++ (aarch64_be-*-elf, aarch64_be-*-linux*, aarch64-*-linux*): Likewise. ++ * emulparams/aarch64elf32.sh: New file. ++ ++2013-06-25 Maciej W. Rozycki ++ ++ * emultempl/mipself.em (insn32): New variable. ++ (mips_create_output_section_statements): Handle insn32 mode. ++ (PARSE_AND_LIST_PROLOGUE): New macro. ++ (PARSE_AND_LIST_LONGOPTS): Likewise. ++ (PARSE_AND_LIST_OPTIONS): Likewise. ++ ++ * gen-doc.texi: Set MIPS. ++ * ld.texinfo: Likewise. ++ (Options specific to MIPS targets): New section. ++ (ld and MIPS family): New node. ++ (Top, Machine Dependent): List the new node. ++ ++2013-06-24 Maciej W. Rozycki ++ ++ * emulparams/elf32btsmip.sh: Arrange for .got.plt to be placed ++ as close to .plt as possible. ++ * scripttempl/elf.sc: Handle $INITIAL_READWRITE_SECTIONS and ++ $PLT_NEXT_DATA variables. ++ ++2013-06-23 Richard Sandiford ++ ++ * Makefile.am (ALL_EMULATION_SOURCES): Move MIPS ELF emulations to... ++ (ALL_64_EMULATION_SOURCES): ...here. ++ * Makefile.in: Regenerate. ++ ++2013-06-22 Richard Sandiford ++ ++ * NEWS: Document the removal of MIPS ECOFF targets. ++ * ld.texinfo (--gpsize=@var{value}): Use MIPS ELF rather than ++ MIPS ECOFF as an example of a target that supports small data. ++ * ldmain.c (g_switch_value): Likewise. ++ * configure.tgt (mips*-*-pe, mips*-dec-ultrix*, mips*-dec-osf*) ++ (mips*-sgi-irix* [v4 and earlier], mips*el-*-ecoff*, mips*-*-ecoff*) ++ (mips*-*-bsd*, mips*-*-lnews*): Remove cases. ++ * Makefile.am (ALL_EMULATION_SOURCES): Remove emipsbig.c, emipsbsd.c, ++ emipsidt.c, emipsidtl.c, emipslit.c, emipslnews.c and emipspe.c. ++ (emipsbig.c, emipsbsd.c, emipsidt.c, emipsidtl.c, emipslit.c) ++ (emipslnews.c, emipspe.c): Delete rules. ++ * Makefile.in: Regenerate. ++ * emulparams/mipsbig.sh, emulparams/mipsbsd.sh, emulparams/mipsidt.sh, ++ emulparams/mipsidtl.sh, emulparams/mipslit.sh, emulparams/mipslnews.sh, ++ emulparams/mipspe.sh, emultempl/mipsecoff.em: Delete. ++ * emultempl/m68kcoff.em: Update comment to say that MIPS ECOFF support ++ has now been removed. ++ * emultempl/pe.em: Remove TARGET_IS_mipspe checks. ++ ++2013-06-19 Will Newton ++ ++ * emulparams/aarch64elf.sh: Remove IREL_IN_PLT. ++ ++2013-06-14 Yufeng Zhang ++ ++ * emulparams/aarch64elf.sh: Add IREL_IN_PLT. ++ ++2013-06-12 Nick Clifton ++ ++ * ldcref.c (output_one_cref): Place common definitions after ++ ordinary definitions but before references. ++ ++2013-06-10 Dilyan Palauzov ++ ++ PR ld/15598 ++ * ld.texinfo (Source Code Reference): Fix typos. ++ ++2013-06-07 Will Newton ++ ++ * emulparams/aarch64elf.sh: Add IREL_IN_PLT. ++ ++2013-06-07 Nick Clifton ++ ++ * ld.texinfo (SEGMENT_START): Rephrase to indicate that a -T ++ option must appear before the SEGMENT_START is encountered in ++ order for the default value to be overridden. ++ ++2013-05-03 Alan Modra ++ ++ PR ld/15365 ++ * emultempl/elf32.em (gld${EMULATION_NAME}_before_allocation): ++ Restrict __ehdr_start's export class to no less than STV_HIDDEN. ++ ++2013-05-03 Alan Modra ++ ++ * emultempl/elf32.em (gld${EMULATION_NAME}_before_allocation): ++ Only call lang_for_each_statement if an ELF hash table is used. ++ ++2013-05-02 Nick Clifton ++ ++ * Makefile.am: Add emsp430X.c ++ * Makefine.in: Regenerate. ++ * configure.tgt (msp430): Add msp430X emulation. ++ * ldmain.c (multiple_definition): Only disable relaxation if it ++ was enabled by the user. ++ * ldmain.h (RELAXATION_ENABLED_BY_USER): New macro. ++ * emulparams/msp430all.sh: Add support for MSP430X. ++ * emultempl/generic.em: (before_parse): Enable relaxation for the ++ MSP430. ++ * scripttempl/msp430.sc: Reorganize sections. Add .rodata ++ section. ++ * scripttempl/msp430_3.sc: Likewise. ++ * NEWS: Mention support for MSP430X. ++ ++2013-05-01 Maciej W. Rozycki ++ ++ * configure.tgt: Replace alpha*-*-linuxecoff* pattern with ++ alpha*-*-linux*ecoff*. Update the `sed' pattern used to convert ++ from alpha*-*-linux-* to alpha*-*-linux*ecoff*. ++ ++2013-05-01 Maciej W. Rozycki ++ ++ * emultempl/elf32.em (gld${EMULATION_NAME}_before_allocation): ++ Use is_elf_hash_table rather than a handcoded condition. ++ ++2013-04-30 Nick Clifton ++ ++ * ld.texinfo (SORT_BY_ALIGNMENT): Fix and clarify typo - sections ++ are sorted by descending order of alignment. ++ ++2013-04-29 Nick Clifton ++ ++ * scripttempl/DWARF.sc: Add support for .debug_line.* and ++ .debug_line_end. ++ ++2013-04-29 Yaakov Selkowitz ++ ++ * emultempl/pe.em [cygwin]: Do not merge rdata with v2 ++ psuedo-relocs. ++ ++2013-04-28 Thomas Schwinge ++ ++ * scripttempl/armbpabi.sc: Replace "source" usage with ".". ++ * scripttempl/avr.sc: Likewise. ++ * scripttempl/elf.sc: Likewise. ++ * scripttempl/elf32cr16.sc: Likewise. ++ * scripttempl/elf32crx.sc: Likewise. ++ * scripttempl/elf32msp430.sc: Likewise. ++ * scripttempl/elf32msp430_3.sc: Likewise. ++ * scripttempl/elf32sh-symbian.sc: Likewise. ++ * scripttempl/elf64hppa.sc: Likewise. ++ * scripttempl/elf_chaos.sc: Likewise. ++ * scripttempl/elfd10v.sc: Likewise. ++ * scripttempl/elfd30v.sc: Likewise. ++ * scripttempl/elfi370.sc: Likewise. ++ * scripttempl/elfm68hc11.sc: Likewise. ++ * scripttempl/elfm68hc12.sc: Likewise. ++ * scripttempl/elfxgate.sc: Likewise. ++ * scripttempl/elfxtensa.sc: Likewise. ++ * scripttempl/epiphany_4x4.sc: Likewise. ++ * scripttempl/i386beos.sc: Likewise. ++ * scripttempl/i386go32.sc: Likewise. ++ * scripttempl/ia64vms.sc: Likewise. ++ * scripttempl/ip2k.sc: Likewise. ++ * scripttempl/iq2000.sc: Likewise. ++ * scripttempl/mep.sc: Likewise. ++ * scripttempl/mmo.sc: Likewise. ++ * scripttempl/v850.sc: Likewise. ++ * scripttempl/v850_rh850.sc: Likewise. ++ * scripttempl/xstormy16.sc: Likewise. ++ ++2013-04-26 Senthil Kumar Selvaraj ++ ++ * scripttempl/avr.sc: Add ALIGN directive after *(.progmem*). ++ ++2013-04-26 Alan Modra ++ ++ * emultempl/elf32.em (gld${EMULATION_NAME}_after_open): Test ++ unresolved_syms_in_shared_libs rather than !executable to ++ determine whether to load DT_NEEDED libraries. ++ ++2013-04-25 Alan Modra ++ ++ * Makefile.am (ALL_EMULATION_SOURCES): Add eelf32lppclinux.c. ++ (eelf32lppclinux.c): New rule. ++ * Makefile.in: Regenerate. ++ * configure.tgt: Merge powerpc-linux and other powerpc-elf targets ++ with corresponding little-endian targets. ++ * emulparams/elf32lppc.sh: Update comment. ++ * emulparams/elf32lppclinux.sh: New. ++ ++2013-04-24 H.J. Lu ++ ++ * configure.tgt (targ_extra_emuls): Adds elf32_x86_64 for ++ x86_64-*-elf*. ++ (targ_extra_libpath): Likewise. ++ (tdir_elf_i386): Replace x86_64 with i386 for x86_64-*-elf*. ++ ++2013-04-24 Yufeng Zhang ++ ++ * emulparams/aarch64elf.sh: Define ELFSIZE=64. ++ * emulparams/aarch64linux.sh: Ditto. ++ * emultempl/aarch64elf.em (aarch64_elf_before_allocation): ++ Replace elf64 with elf${ELFSIZE}. ++ (elf64_aarch64_add_stub_section): Likewise. ++ (build_section_lists): Likewise. ++ (gld${EMULATION_NAME}_after_allocation): Likewise. ++ (gld${EMULATION_NAME}_finish): Likewise. ++ (aarch64_elf_create_output_section_statements): Likewise. ++ ++2013-04-24 Nick Clifton ++ ++ PR ld/15389 ++ * scripttempl/avr.sc: Add .note.gnu.build-id section. ++ ++2013-04-22 Alan Modra ++ ++ * emultempl/ppc64elf.em (ppc_create_output_section_statements): ++ Check return from ppc64_elf_init_stub_bfd. ++ ++2013-04-15 Nick Clifton ++ ++ * Makefile.am (ELF_DEPS): Add a dependency upon ++ scripttempl/DWARF.sc. ++ (ELF_GEN_DEPS): Likewise. ++ (emmo.c): Likewise. ++ * Makefile.in: Regenerate. ++ ++ * scripttempl/armbpabi.sc: Replace DWARF sections with an ++ inclusion of DWARF.sc. ++ * scripttempl/avr.sc: Likewise. ++ * scripttempl/elf.sc: Likewise. ++ * scripttempl/elf32cr16.sc: Likewise. ++ * scripttempl/elf32crx.sc: Likewise. ++ * scripttempl/elf32msp430.sc: Likewise. ++ * scripttempl/elf32msp430_3.sc: Likewise. ++ * scripttempl/elf32sh-symbian.sc: Likewise. ++ * scripttempl/elf64hppa.sc: Likewise. ++ * scripttempl/elf_chaos.sc: Likewise. ++ * scripttempl/elfd10v.sc: Likewise. ++ * scripttempl/elfd30v.sc: Likewise. ++ * scripttempl/elfi370.sc: Likewise. ++ * scripttempl/elfm68hc11.sc: Likewise. ++ * scripttempl/elfm68hc12.sc: Likewise. ++ * scripttempl/elfxgate.sc: Likewise. ++ * scripttempl/elfxtensa.sc: Likewise. ++ * scripttempl/epiphany_4x4.sc: Likewise. ++ * scripttempl/i386beos.sc: Likewise. ++ * scripttempl/i386go32.sc: Likewise. ++ * scripttempl/ia64vms.sc: Likewise. ++ * scripttempl/ip2k.sc: Likewise. ++ * scripttempl/iq2000.sc: Likewise. ++ * scripttempl/mep.sc: Likewise. ++ * scripttempl/mmo.sc: Likewise. ++ * scripttempl/v850.sc: Likewise. ++ * scripttempl/v850_rh850.sc: Likewise. ++ * scripttempl/xstormy16.sc: Likewise. ++ * scripttempl/DWARF.sc: New. ++ ++2013-04-04 Alan Modra ++ ++ * ldlang.c (load_symbols): Report "error adding symbols" on ++ bfd_link_add_symbols failure. ++ * emultempl/elf32.em (gld${EMULATION_NAME}_try_needed): Likewise. ++ * emultempl/sunos.em (gld${EMULATION_NAME}_after_open): Likewise. ++ (gld${EMULATION_NAME}_try_needed): Likewise. ++ ++2013-03-27 Georg-Johann Lay ++ ++ PR ld/13812 ++ * scripttempl/avr.sc: Place trampolines before .progmem section. ++ ++2013-03-25 Kai Tietz ++ ++ * ld.texinfo (--disable-runtime-pseudo-reloc): Adjust default. ++ ++2013-03-21 Michael Schewe ++ ++ * ld.texinfo (H8/300): Add description of relaxation of ++ mov @(disp:32,ERx) to mov @(disp:16,ERx). ++ ++2013-03-21 Kai Tietz ++ ++ * pe-dll.c (process_def_file_and_drectve): Don't handle VC ++ generated C++-symbols as stdcall/fastcall. ++ ++2013-03-18 Alan Modra ++ ++ * ld.texinfo (--as-needed): Update. ++ ++2013-03-14 Jakub Jelinek ++ ++ * emulparams/aarch64linux.sh (LIBPATH_SUFFIX): Set to 64 for ++ aarch64linux* emulations. ++ ++2013-03-07 Alan Modra ++ ++ * ldfile.c (ldfile_open_command_file_1): Return after einfo ++ to avoid warning. ++ ++2013-03-05 Corinna Vinschen ++ ++ * configure.host: Add x86_64-*-cygwin* as valid host. ++ * configure.tgt: Add x86_64-*-cygwin* as valid target. ++ * emultempl/pep.em: Handle different requirements for Cygwin in terms ++ of start addresses for executables and DLLs, based on memory model in ++ http://cygwin.com/ml/cygwin-developers/2013-02/msg00027.html ++ ++2013-03-05 Alan Modra ++ ++ PR ld/15222 ++ * ldlang.c (lang_size_sections_1): When given an lma_region align ++ LMA as per VMA only if lma_region is the same as region. ++ ++2013-02-27 Nick Clifton ++ ++ * scripttempl/elf32msp430.sc: Add placement of .data.* sections. ++ Add alignment of .bss section. ++ * scripttempl/elf32msp430_3.sc: Likewise. ++ ++2013-02-26 Nick Clifton ++ ++ PR ld/15188 ++ * ld.texinfo: Fix typos. ++ ++2013-02-21 Alan Modra ++ ++ * scripttempl/elf.sc (.init_array, .fini_array): Don't sort all ++ .init_array/.fini_array input sections before .ctors/.dtors input ++ sections. ++ (CTORS_IN_INIT_ARRAY, DTORS_IN_INIT_ARRAY): Adjust to suit. ++ ++2013-02-21 Alan Modra ++ ++ * emultempl/elf32.em (write_build_id, setup_build_id): Adjust ++ for elf_tdata changes. ++ ++2013-02-21 Alan Modra ++ ++ * emultempl/elf-generic.em: Use newly defined elf_obj_tdata ++ accessor macros. ++ ++2013-02-20 Alan Modra ++ ++ * Makefile.am: Use $(ELF_DEPS) on a number of eelf*.c rules. ++ * Makefile.in: Regenerate. ++ ++2013-02-19 Sandra Loosemore ++ ++ PR ld/15146 ++ * plugin.c (plugin_notice): Add null check before dereferencing ++ pointer. ++ ++2013-02-19 Alan Modra ++ ++ * emultempl/elf32.em (emit_note_gnu_build_id): New static var. ++ Replace all info->emit_note_gnu_build_id refs. ++ (id_note_section_size): Rename from ++ gld${EMULATION_NAME}_id_note_section_size. ++ (struct build_id_info): Delete. ++ (write_build_id): Rename from ++ gld${EMULATION_NAME}_write_build_id_section. ++ Update elf_tdata usage. Style, formatting. ++ (setup_build_id): New function. ++ (gld${EMULATION_NAME}_after_open): Use setup_build_id. ++ ++2013-02-16 H.J. Lu ++ ++ PR ld/15146 ++ * plugin.c (plugin_notice): Replace the undefined dummy bfd with ++ the real one. ++ ++2013-02-16 H.J. Lu ++ ++ PR ld/15141 ++ * plugin.c (plugin_notice): Also trace symbol from the IR bfd. ++ ++2013-02-15 Kai Tietz ++ ++ * scripttempl/pep.sc (.xdata): Merge .xdata* into .xdata section. ++ (.pdata): Merge .pdata* into .pdata section. ++ ++2013-02-11 Alan Modra ++ ++ * ldlang.c (get_init_priority): Comment typo. ++ (lang_finish): Free link_info.hash and lang_definedness_table. ++ (lang_end): Delete lang_definedness_table comment. ++ ++2013-02-11 Alan Modra ++ ++ PR ld/15130 ++ * ld.texinfo (-rpath-link): Typo fix. ++ ++2013-02-08 Markos Chandras ++ ++ * emultempl/metagelf.em (build_section_lists): Use sec_info_type ++ rather than userdata->flags.just_syms. ++ ++2013-02-06 Sandra Loosemore ++ Andrew Jenner ++ ++ Based on patches from Altera Corporation. ++ ++ * Makefile.am (enios2elf.c): New rule. ++ * Makefile.in: Regenerated. ++ * configure.tgt: Add case for nios2*-*-*. ++ * emulparams/nios2elf.sh: New file. ++ * NEWS: Note Altera Nios II support. ++ ++2013-02-06 Senthil Kumar Selvaraj ++ ++ * emultempl/avrelf.em (avr_elf_before_parse): New function. ++ (LDEMUL_BEFORE_PARSE): Define. ++ ++2013-02-06 Alan Modra ++ ++ PR ld/15096 ++ * emultempl/elf32.em: Revert 2013-02-04, 2013-01-22 and 2013-01-21. ++ * emultempl/alphaelf.em: Revert 2013-02-04. ++ * emultempl/cr16elf.em: Likewise. ++ * emultempl/crxelf.em: Likewise. ++ * emultempl/hppaelf.em: Likewise. ++ * emultempl/ia64elf.em: Likewise. ++ * emultempl/mipself.em: Likewise. ++ * NEWS: Revert 2013-01-21. ++ ++2013-02-04 H.J. Lu ++ ++ PR ld/15096 ++ * emultempl/alphaelf.em (alpha_after_parse): Call ++ gld${EMULATION_NAME}_after_parse instead of after_parse_default. ++ * emultempl/cr16elf.em (cr16elf_after_parse): Likewise. ++ * emultempl/crxelf.em (crxelf_after_parse): Likewise. ++ * emultempl/hppaelf.em (hppaelf_after_parse): Likewise. ++ * emultempl/mipself.em (mips_after_parse): Likewise. ++ ++ * emultempl/ia64elf.em (gld${EMULATION_NAME}_after_parse): Renamed ++ to ... ++ (gld_${EMULATION_NAME}_after_parse): This. Call ++ gld${EMULATION_NAME}_after_parse instead of after_parse_default. ++ (LDEMUL_AFTER_PARSE): Set to gld_${EMULATION_NAME}_after_parse. ++ ++ * emultempl/elf32.em (new_dtags_set): New variable. ++ (gld${EMULATION_NAME}_before_parse): Don't set link_info.new_dtags ++ here. ++ (gld${EMULATION_NAME}_after_parse): New function. ++ (ld_${EMULATION_NAME}_emulation): Replace after_parse_default' ++ with gld${EMULATION_NAME}_after_parse. ++ (gld${EMULATION_NAME}_handle_option): Set new_dtags_set to TRUE ++ when setting link_info.new_dtags. ++ ++2013-01-25 Kai Tietz ++ ++ * deffilep.y (def_image_name): Adjust type of base-address ++ argument. ++ (%union): Add new type bfd_vma as vma. ++ (VMA): New rule. ++ (opt_base): Use VMA instead of NUMBER rule to evaluate value. ++ (def_file_print): Use bfd's fprintf_vma to output base-address. ++ ++2013-01-24 Nick Clifton ++ ++ * NEWS: Mention support for V850E3V5 architecture. ++ ++2013-01-23 Martin Koegler ++ ++ PR ld/15041 ++ * scripttempl/pep.sc (.pdata): Only accept .pdata sections. ++ (.xdata): Similarly. ++ (.debug_frame): Similarly. ++ ++2013-01-23 Georg-Johann Lay ++ ++ PR ld/15037 ++ * scripttempl/avr.sc (.eeprom): Keep it. ++ ++2013-01-23 Leif Ekblad ++ ++ * Makefile.am (ALL_64_EMULATION_SOURCES): Add eelf64rdos.c. ++ (eelf64rdos.c): New rule. ++ * emulparams/elf64rdos.sh: New file. ++ * configure.tgt (x86_64-*-rdos*): Use above. ++ * Makefile.in: Regenerate. ++ ++2013-01-22 Roland McGrath ++ ++ * emultempl/elf32.em (gld${EMULATION_NAME}_before_parse): Set ++ new_dtags to TRUE for *-*-nacl* targets. ++ ++2013-01-21 Mike Frysinger ++ ++ * emultempl/elf32.em (gld${EMULATION_NAME}_before_parse): Set ++ link_info.new_dtags to TRUE for linux/gnu targets. ++ * NEWS: Mention new dtags default. ++ ++2013-01-19 H.J. Lu ++ ++ * Makefile.am (HOSTING_SCRT0): New. ++ ++ * configure.host (HOSTING_SCRT0): New. Used for PIE. ++ ++ * configure.in (HOSTING_SCRT0): New AC_SUBST. ++ ++ * Makefile.in: Regenerated. ++ * configure: Likewise. ++ ++2013-01-18 Mike Frysinger ++ ++ * NEWS: Mention change in behavior with --enable-new-dtags. ++ * ld.texinfo (Options): Clarify --enable-new-dtags behavior. ++ ++2013-01-14 Leif Ekblad ++ Alan Modra ++ ++ * ld.texinfo (-Tldata-segment): Describe. ++ * ldlex.h (OPTION_TLDATA_SEGMENT): New enum value. ++ * lexsup.c (ld_options): Add -Tldata-segment. ++ (parse_args): Handle OPTION_TLDATA_SEGMENT. ++ * scripttempl/elf.sc: Support LARGE_DATA_ADDR. ++ ++2013-01-10 H.J. Lu ++ ++ * deffilep.y: Remove trailing white spaces. ++ * elf-hints-local.h: Likewise. ++ * ldexp.c: Likewise. ++ * ldlang.h: Likewise. ++ * ldmisc.c: Likewise. ++ * ldwrite.c: Likewise. ++ * pe-dll.c: Likewise. ++ * emulparams/criself.sh: Likewise. ++ * emulparams/crislinux.sh: Likewise. ++ * emulparams/elf32_tic6x_le.sh: Likewise. ++ * emulparams/elf32bmipn32-defs.sh: Likewise. ++ * emulparams/elf32mb_linux.sh: Likewise. ++ * emulparams/elf32mep.sh: Likewise. ++ * emulparams/elf32microblaze.sh: Likewise. ++ * emulparams/elf32ppc.sh: Likewise. ++ * emulparams/elf64_s390.sh: Likewise. ++ * emulparams/elf64alpha.sh: Likewise. ++ * emulparams/elf_s390.sh: Likewise. ++ * emulparams/elf_x86_64.sh: Likewise. ++ * emulparams/tic80coff.sh: Likewise. ++ * emultempl/aix.em: Likewise. ++ * emultempl/avrelf.em: Likewise. ++ * emultempl/cr16elf.em: Likewise. ++ * emultempl/pe.em: Likewise. ++ * emultempl/pep.em: Likewise. ++ * emultempl/spuelf.em: Likewise. ++ * emultempl/tic6xdsbt.em: Likewise. ++ ++2013-01-10 Will Newton ++ ++ * Makefile.am: Add Meta. ++ * Makefile.in: Regenerate. ++ * configure.tgt: Add Meta. ++ * emulparams/elf32metag.sh: New file. ++ * emultempl/metagelf.em: New file. ++ ++2013-01-09 Alan Modra ++ ++ * emulparams/elf_x86_64.sh (LARGE_BSS_AFTER_BSS): Define. ++ * emulparams/elf32_x86_64.sh: Likewise. ++ * emulparams/elf_k1om.sh: Likewise. ++ * emulparams/elf_l1om.sh: Likewise. ++ * scripttempl/elf.sc (LARGE_BSS): Define rather than appending to ++ OTHER_BSS_SECTIONS. Substitute in script. ++ ++2013-01-08 Leif Ekblad ++ ++ * scripttempl/elf.sc (RODATA_ADDR): Typo fix. ++ ++2013-01-08 Alan Modra ++ ++ * emultempl/elf32.em (gld${EMULATION_NAME}_check_ld_so_conf): Replace ++ "name" param with a bfd_link_needed_list pointer. Update caller. ++ (gld${EMULATION_NAME}_check_ld_elf_hints): Likewise. ++ ++2013-01-08 Alan Modra ++ ++ * Makefile.am (ALL_EMULATION_SOURCES): Correct eavrxmega entries. ++ * Makefile.in: Regenerate. ++ ++2013-01-07 H.J. Lu ++ ++ * lexsup.c (ld_options): Add fuse-ld= for GCC linker option ++ compatibility. ++ ++2013-01-07 Patrice Dumas ++ ++ * ld.texinfo: Replace @ with @@ when it is part of the text. ++ Correct ordering of M68HC11 entry. ++ ++2013-01-04 Juergen Urban ++ ++ * configure.tgt: Support ELF files for Sony Playstation 2 (for ++ ps2dev and ps2sdk). ++ * emulparams/elf32lr5900n32.sh: Create linker script for Sony ++ Playstation 2 ELF files using MIPS ABI n32. ++ * emulparams/elf32lr5900.sh: Create linker script for Sony ++ Playstation 2 ELF files using MIPS ABI o32. ++ * Makefile.am: Add linker scripts for Sony Playstation 2 ELF ++ files. ++ ++2013-01-02 H.J. Lu ++ ++ * ldver.c (ldversion): Update copyright year to 2013. ++ ++For older changes see ChangeLog-2012 ++ ++Copyright (C) 2013 Free Software Foundation, Inc. ++ ++Copying and distribution of this file, with or without modification, ++are permitted in any medium without royalty provided the copyright ++notice and this notice are preserved. ++ ++Local Variables: ++mode: change-log ++left-margin: 8 ++fill-column: 74 ++version-control: never ++End: diff --git a/ld/ChangeLog-9197 b/ld/ChangeLog-9197 new file mode 100644 index 0000000..ca31620 @@ -2564427,26 +2578385,26 @@ index 0000000..7370a32 +End: diff --git a/ld/MAINTAINERS b/ld/MAINTAINERS new file mode 100644 -index 0000000..e7d8ff8 +index 0000000..9ee4884 --- /dev/null +++ b/ld/MAINTAINERS @@ -0,0 +1,7 @@ +See ../binutils/MAINTAINERS + -+Copyright (C) 2012 Free Software Foundation, Inc. ++Copyright (C) 2012-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright +notice and this notice are preserved. diff --git a/ld/Makefile.am b/ld/Makefile.am new file mode 100644 -index 0000000..1abb340 +index 0000000..44e7ca6 --- /dev/null +++ b/ld/Makefile.am -@@ -0,0 +1,2393 @@ +@@ -0,0 +1,2119 @@ +## Process this file with automake to generate Makefile.in +# -+# Copyright 2012, 2013 Free Software Foundation ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -2564506,6 +2578464,7 @@ index 0000000..1abb340 +EMULATION_OFILES = @EMULATION_OFILES@ +EMUL_EXTRA_OFILES = @EMUL_EXTRA_OFILES@ + ++ +# Search path to override the default search path for -lfoo libraries. +# If LIB_PATH is empty, the ones in the script (if any) are left alone. +# (The default is usually /lib:/usr/lib:/usr/local/lib, unless building @@ -2564683,6 +2578642,7 @@ index 0000000..1abb340 + eelf32lppcsim.c \ + eelf32m32c.c \ + eelf32mb_linux.c \ ++ eelf32mbel_linux.c \ + eelf32mcore.c \ + eelf32mep.c \ + eelf32metag.c \ @@ -2564690,7 +2578650,8 @@ index 0000000..1abb340 + eelf32microblaze.c \ + eelf32moxie.c \ + eelf32mt.c \ -+ eelf32openrisc.c \ ++ eelf32or1k.c \ ++ eelf32or1k_linux.c \ + eelf32ppc.c \ + eelf32ppc_fbsd.c \ + eelf32ppclinux.c \ @@ -2564783,65 +2578744,7 @@ index 0000000..1abb340 + emcorepe.c \ + emn10200.c \ + emn10300.c \ -+ emsp430x110.c \ -+ emsp430x1101.c \ -+ emsp430x1111.c \ -+ emsp430x112.c \ -+ emsp430x1121.c \ -+ emsp430x1122.c \ -+ emsp430x1132.c \ -+ emsp430x122.c \ -+ emsp430x1222.c \ -+ emsp430x123.c \ -+ emsp430x1232.c \ -+ emsp430x133.c \ -+ emsp430x1331.c \ -+ emsp430x135.c \ -+ emsp430x1351.c \ -+ emsp430x147.c \ -+ emsp430x148.c \ -+ emsp430x149.c \ -+ emsp430x155.c \ -+ emsp430x156.c \ -+ emsp430x157.c \ -+ emsp430x1610.c \ -+ emsp430x1611.c \ -+ emsp430x1612.c \ -+ emsp430x167.c \ -+ emsp430x168.c \ -+ emsp430x169.c \ -+ emsp430x2101.c \ -+ emsp430x2111.c \ -+ emsp430x2121.c \ -+ emsp430x2131.c \ -+ emsp430x311.c \ -+ emsp430x312.c \ -+ emsp430x313.c \ -+ emsp430x314.c \ -+ emsp430x315.c \ -+ emsp430x323.c \ -+ emsp430x325.c \ -+ emsp430x336.c \ -+ emsp430x337.c \ -+ emsp430x412.c \ -+ emsp430x413.c \ -+ emsp430x415.c \ -+ emsp430x417.c \ -+ emsp430x435.c \ -+ emsp430x436.c \ -+ emsp430x437.c \ -+ emsp430x447.c \ -+ emsp430x448.c \ -+ emsp430x449.c \ -+ emsp430xE423.c \ -+ emsp430xE425.c \ -+ emsp430xE427.c \ -+ emsp430xG437.c \ -+ emsp430xG438.c \ -+ emsp430xG439.c \ -+ emsp430xW423.c \ -+ emsp430xW425.c \ -+ emsp430xW427.c \ ++ emsp430.c \ + emsp430X.c \ + ends32elf.c \ + ends32elf16m.c \ @@ -2564851,8 +2578754,6 @@ index 0000000..1abb340 + ends32belf_linux.c \ + enews.c \ + ens32knbsd.c \ -+ eor32.c \ -+ eor32elf.c \ + epc532macha.c \ + epdp11.c \ + epjelf.c \ @@ -2564996,12 +2578897,12 @@ index 0000000..1abb340 +CFILES = ldctor.c ldemul.c ldexp.c ldfile.c ldlang.c \ + ldmain.c ldmisc.c ldver.c ldwrite.c lexsup.c \ + mri.c ldcref.c pe-dll.c pep-dll.c ldlex-wrapper.c \ -+ $(PLUGIN_C) ++ $(PLUGIN_C) ldbuildid.c + +HFILES = ld.h ldctor.h ldemul.h ldexp.h ldfile.h \ + ldlang.h ldlex.h ldmain.h ldmisc.h ldver.h \ + ldwrite.h mri.h deffile.h pe-dll.h pep-dll.h \ -+ elf-hints-local.h $(PLUGIN_H) ++ elf-hints-local.h $(PLUGIN_H) ldbuildid.h + +GENERATED_CFILES = ldgram.c ldlex.c deffilep.c +GENERATED_HFILES = ldgram.h ldemul-list.h deffilep.h @@ -2565013,7 +2578914,8 @@ index 0000000..1abb340 +OFILES = ldgram.@OBJEXT@ ldlex-wrapper.@OBJEXT@ lexsup.@OBJEXT@ ldlang.@OBJEXT@ \ + mri.@OBJEXT@ ldctor.@OBJEXT@ ldmain.@OBJEXT@ $(PLUGIN_OBJECT) \ + ldwrite.@OBJEXT@ ldexp.@OBJEXT@ ldemul.@OBJEXT@ ldver.@OBJEXT@ ldmisc.@OBJEXT@ \ -+ ldfile.@OBJEXT@ ldcref.@OBJEXT@ ${EMULATION_OFILES} ${EMUL_EXTRA_OFILES} ++ ldfile.@OBJEXT@ ldcref.@OBJEXT@ ${EMULATION_OFILES} ${EMUL_EXTRA_OFILES} \ ++ ldbuildid.@OBJEXT@ + +STAGESTUFF = *.@OBJEXT@ ldscripts/* e*.c + @@ -2565141,94 +2579043,108 @@ index 0000000..1abb340 + +@TDIRS@ + ++# We can't use pattern rules as we don't want to depend on GNU ++# make, or else these rules could have been expressed in one ++# two-liner: 'e%.c:' and ' ${GENSCRIPTS} $* "$(tdir_$*)"'. ++# (The recursive variable expansion is portable.) ++ ++run-genscripts: ++ ${GENSCRIPTS} $(script_target) "$($(script_tdirname))" ++ ++.PHONY: run-genscripts ++ ++$(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): ++ base=`echo $@ | sed -e 's,e\(.*\).c,\1,'`; \ ++ $(MAKE) run-genscripts "script_target=$$base" "script_tdirname=tdir_$$base" ++ +eaix5ppc.c: $(srcdir)/emulparams/aix5ppc.sh \ + $(srcdir)/emultempl/aix.em $(srcdir)/scripttempl/aix.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} aix5ppc "$(tdir_aixppc)" ++ +eaix5rs6.c: $(srcdir)/emulparams/aix5rs6.sh \ + $(srcdir)/emultempl/aix.em $(srcdir)/scripttempl/aix.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} aix5rs6 "$(tdir_aixrs6)" ++ +eaixppc.c: $(srcdir)/emulparams/aixppc.sh \ + $(srcdir)/emultempl/aix.em $(srcdir)/scripttempl/aix.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} aixppc "$(tdir_aixppc)" ++ +eaixrs6.c: $(srcdir)/emulparams/aixrs6.sh \ + $(srcdir)/emultempl/aix.em $(srcdir)/scripttempl/aix.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} aixrs6 "$(tdir_aixrs6)" ++ +ealpha.c: $(srcdir)/emulparams/alpha.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/alpha.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} alpha "$(tdir_alpha)" ++ +ealphavms.c: $(srcdir)/emulparams/alphavms.sh \ + $(srcdir)/emultempl/vms.em $(srcdir)/scripttempl/alphavms.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} alphavms "$(tdir_alphavms)" ++ +earcelf.c: $(srcdir)/emulparams/arcelf.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} arcelf "$(tdir_arcelf)" ++ +earm_epoc_pe.c: $(srcdir)/emulparams/arm_epoc_pe.sh \ + $(srcdir)/emultempl/pe.em $(srcdir)/scripttempl/epocpe.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} arm_epoc_pe "$(tdir_armpe)" ++ +earm_wince_pe.c: $(srcdir)/emulparams/arm_wince_pe.sh \ + $(srcdir)/emultempl/pe.em $(srcdir)/scripttempl/pe.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} arm_wince_pe "$(tdir_armpe)" ++ +earmaoutb.c: $(srcdir)/emulparams/armaoutb.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/armaout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armaoutb "$(tdir_armaoutb)" ++ +earmaoutl.c: $(srcdir)/emulparams/armaoutl.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/armaout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armaoutl "$(tdir_armaoutl)" ++ +earmcoff.c: $(srcdir)/emulparams/armcoff.sh \ + $(srcdir)/emultempl/armcoff.em $(srcdir)/scripttempl/armcoff.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armcoff "$(tdir_armcoff)" ++ +earmelf.c: $(srcdir)/emulparams/armelf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armelf "$(tdir_armelf)" ++ +earmelf_fbsd.c: $(srcdir)/emulparams/armelf_fbsd.sh \ + $(srcdir)/emulparams/armelf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armelf_fbsd "$(tdir_armelf_fbsd)" ++ +earmelf_linux.c: $(srcdir)/emulparams/armelf_linux.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armelf_linux "$(tdir_armelf_linux)" ++ +earmelf_linux_eabi.c: $(srcdir)/emulparams/armelf_linux_eabi.sh \ + $(srcdir)/emulparams/armelf_linux.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armelf_linux_eabi "$(tdir_armelf_linux_abi)" ++ +earmelf_nacl.c: $(srcdir)/emulparams/armelf_nacl.sh \ + $(srcdir)/emulparams/armelf_linux_eabi.sh \ + $(srcdir)/emulparams/armelf_linux.sh \ + $(srcdir)/emulparams/elf_nacl.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armelf_nacl "$(tdir_armelf_nacl)" ++ +earmelf_nbsd.c: $(srcdir)/emulparams/armelf_nbsd.sh \ + $(srcdir)/emulparams/armelf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armelf_nbsd "$(tdir_armelf_nbsd)" ++ +earmelf_vxworks.c: $(srcdir)/emulparams/armelf_vxworks.sh \ + $(srcdir)/emulparams/vxworks.sh $(srcdir)/emulparams/armelf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/vxworks.em \ + $(srcdir)/emultempl/armelf.em $(srcdir)/scripttempl/elf.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} armelf_vxworks "$(tdir_armelf)" ++ +earmelfb.c: $(srcdir)/emulparams/armelfb.sh $(srcdir)/emulparams/armelf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armelfb "$(tdir_armelfb)" ++ +earmelfb_linux.c: $(srcdir)/emulparams/armelfb_linux.sh \ + $(srcdir)/emulparams/armelf_linux.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armelfb_linux "$(tdir_armelfb_linux)" ++ +earmelfb_linux_eabi.c: $(srcdir)/emulparams/armelfb_linux_eabi.sh \ + $(srcdir)/emulparams/armelf_linux_eabi.sh \ + $(srcdir)/emulparams/armelf_linux.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armelfb_linux_eabi "$(tdir_armelfb_linux_abi)" ++ +earmelfb_nacl.c: $(srcdir)/emulparams/armelfb_nacl.sh \ + $(srcdir)/emulparams/armelf_nacl.sh \ + $(srcdir)/emulparams/armelf_linux_eabi.sh \ @@ -2565236,154 +2579152,154 @@ index 0000000..1abb340 + $(srcdir)/emulparams/elf_nacl.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armelfb_nacl "$(tdir_armelfb_nacl)" ++ +earmelfb_nbsd.c: $(srcdir)/emulparams/armelfb_nbsd.sh \ + $(srcdir)/emulparams/armelf_nbsd.sh \ + $(srcdir)/emulparams/armelf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armelfb_nbsd "$(tdir_armelfb_nbsd)" ++ +earmnbsd.c: $(srcdir)/emulparams/armnbsd.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armnbsd "$(tdir_armnbsd)" ++ +earmnto.c: $(srcdir)/emulparams/armnto.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armnto "$(tdir_armnto)" ++ +earmpe.c: $(srcdir)/emulparams/armpe.sh \ + $(srcdir)/emultempl/pe.em $(srcdir)/scripttempl/pe.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armpe "$(tdir_armpe)" ++ +earmsymbian.c: $(srcdir)/emulparams/armsymbian.sh \ + $(srcdir)/emulparams/armelf.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/armelf.em $(srcdir)/scripttempl/armbpabi.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} armsymbian "$(tdir_armelf)" ++ +eavr1.c: $(srcdir)/emulparams/avr1.sh $(srcdir)/emultempl/avrelf.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avr1 "$(tdir_avr2)" ++ +eavr2.c: $(srcdir)/emulparams/avr2.sh $(srcdir)/emultempl/avrelf.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avr2 "$(tdir_avr2)" ++ +eavr25.c: $(srcdir)/emulparams/avr25.sh $(srcdir)/emultempl/avrelf.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avr25 "$(tdir_avr2)" ++ +eavr3.c: $(srcdir)/emulparams/avr3.sh $(srcdir)/emultempl/avrelf.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avr3 "$(tdir_avr2)" ++ +eavr31.c: $(srcdir)/emulparams/avr31.sh $(srcdir)/emultempl/avrelf.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avr31 "$(tdir_avr2)" ++ +eavr35.c: $(srcdir)/emulparams/avr35.sh $(srcdir)/emultempl/avrelf.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avr35 "$(tdir_avr2)" ++ +eavr4.c: $(srcdir)/emulparams/avr4.sh $(srcdir)/emultempl/avrelf.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avr4 "$(tdir_avr2)" ++ +eavr5.c: $(srcdir)/emulparams/avr5.sh $(srcdir)/emultempl/avrelf.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avr5 "$(tdir_avr2)" ++ +eavr51.c: $(srcdir)/emulparams/avr51.sh $(srcdir)/emultempl/avrelf.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avr51 "$(tdir_avr2)" ++ +eavr6.c: $(srcdir)/emulparams/avr6.sh $(srcdir)/emultempl/avrelf.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avr6 "$(tdir_avr2)" ++ +eavrxmega1.c: $(srcdir)/emulparams/avrxmega1.sh \ + $(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avrxmega1 "$(tdir_avr2)" ++ +eavrxmega2.c: $(srcdir)/emulparams/avrxmega2.sh \ + $(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avrxmega2 "$(tdir_avr2)" ++ +eavrxmega3.c: $(srcdir)/emulparams/avrxmega3.sh \ + $(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avrxmega3 "$(tdir_avr2)" ++ +eavrxmega4.c: $(srcdir)/emulparams/avrxmega4.sh \ + $(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avrxmega4 "$(tdir_avr2)" ++ +eavrxmega5.c: $(srcdir)/emulparams/avrxmega5.sh \ + $(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avrxmega5 "$(tdir_avr2)" ++ +eavrxmega6.c: $(srcdir)/emulparams/avrxmega6.sh \ + $(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avrxmega6 "$(tdir_avr2)" ++ +eavrxmega7.c: $(srcdir)/emulparams/avrxmega7.sh \ + $(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avrxmega7 "$(tdir_avr2)" ++ +ecoff_i860.c: $(srcdir)/emulparams/coff_i860.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/i860coff.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} coff_i860 "$(tdir_coff_i860)" ++ +ecoff_sparc.c: $(srcdir)/emulparams/coff_sparc.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/sparccoff.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} coff_sparc "$(tdir_coff_sparc)" ++ +ecrisaout.c: $(srcdir)/emulparams/crisaout.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/crisaout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} crisaout "$(tdir_cris)" ++ +ecriself.c: $(srcdir)/emulparams/criself.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} criself "$(tdir_cris)" ++ +ecrislinux.c: $(srcdir)/emulparams/crislinux.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} crislinux "$(tdir_cris)" ++ +ed10velf.c: $(srcdir)/emulparams/d10velf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elfd10v.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} d10velf "$(tdir_d10v)" ++ +ed30v_e.c: $(srcdir)/emulparams/d30v_e.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elfd30v.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} d30v_e "$(tdir_d30v)" ++ +ed30v_o.c: $(srcdir)/emulparams/d30v_o.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elfd30v.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} d30v_o "$(tdir_d30v)" ++ +ed30velf.c: $(srcdir)/emulparams/d30velf.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elfd30v.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} d30velf "$(tdir_d30v)" ++ +edelta68.c: $(srcdir)/emulparams/delta68.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/delta68.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} delta68 "$(tdir_delta68)" ++ +eelf32_dlx.c: $(srcdir)/emulparams/elf32_dlx.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/dlx.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_dlx "$(tdir_elf32_dlx)" ++ +eelf32_i860.c: $(srcdir)/emulparams/elf32_i860.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_i860 "$(tdir_elf32_i860)" ++ +eelf32_i960.c: $(srcdir)/emulparams/elf32_i960.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_i960 "$(tdir_elf32_i960)" ++ +eelf32_sparc.c: $(srcdir)/emulparams/elf32_sparc.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_sparc "$(tdir_elf32_sparc)" ++ +eelf32_sparc_sol2.c: $(srcdir)/emulparams/elf32_sparc_sol2.sh \ + $(srcdir)/emulparams/elf32_sparc.sh \ + $(srcdir)/emulparams/solaris2.sh \ + $(srcdir)/emultempl/solaris2.em $(ELF_DEPS) \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_sparc_sol2 "$(tdir_elf32_sparc_sol2)" ++ +eelf32_sparc_vxworks.c: $(srcdir)/emulparams/elf32_sparc_vxworks.sh \ + $(srcdir)/emulparams/vxworks.sh $(srcdir)/emulparams/elf32_sparc.sh \ + $(srcdir)/emultempl/vxworks.em $(ELF_DEPS) \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_sparc_vxworks "$(tdir_elf32_sparc_vxworks)" ++ +eelf32_spu.c: $(srcdir)/emulparams/elf32_spu.sh $(srcdir)/emultempl/spuelf.em \ + $(srcdir)/emultempl/spu_ovl.@OBJEXT@_c $(srcdir)/emultempl/spu_icache.@OBJEXT@_c \ + ldemul-list.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_spu "$(tdir_elf32_spu)" ++ +$(srcdir)/emultempl/spu_ovl.@OBJEXT@_c: @MAINT@ $(srcdir)/emultempl/spu_ovl.S + if ../gas/as-new --version \ + | grep 'target.*spu' >/dev/null 2>/dev/null; then \ @@ -2565401,1259 +2579317,1024 @@ index 0000000..1abb340 +eelf32_tic6x_be.c: $(srcdir)/emulparams/elf32_tic6x_be.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc $(srcdir)/emultempl/tic6xdsbt.em \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_tic6x_be "$(tdir_elf32_tic6x_be)" ++ +eelf32_tic6x_elf_be.c: $(srcdir)/emulparams/elf32_tic6x_elf_be.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc $(srcdir)/emultempl/tic6xdsbt.em \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_tic6x_elf_be "$(tdir_elf32_tic6x_elf_be)" ++ +eelf32_tic6x_elf_le.c: $(srcdir)/emulparams/elf32_tic6x_elf_le.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc $(srcdir)/emultempl/tic6xdsbt.em \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_tic6x_elf_le "$(tdir_elf32_tic6x_elf_le)" ++ +eelf32_tic6x_le.c: $(srcdir)/emulparams/elf32_tic6x_le.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc $(srcdir)/emultempl/tic6xdsbt.em \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_tic6x_le "$(tdir_elf32_tic6x_le)" ++ +eelf32_tic6x_linux_be.c: $(srcdir)/emulparams/elf32_tic6x_linux_be.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc $(srcdir)/emultempl/tic6xdsbt.em \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_tic6x_linux_be "$(tdir_elf32_tic6x_linux_be)" ++ +eelf32_tic6x_linux_le.c: $(srcdir)/emulparams/elf32_tic6x_linux_le.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc $(srcdir)/emultempl/tic6xdsbt.em \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_tic6x_linux_le "$(tdir_elf32_tic6x_linux_le)" ++ +eelf32am33lin.c: $(srcdir)/emulparams/elf32am33lin.sh \ + $(srcdir)/emulparams/elf32am33lin.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32am33lin "$(tdir_elf32am33lin)" ++ +eelf32b4300.c: $(srcdir)/emulparams/elf32b4300.sh \ + $(srcdir)/emulparams/elf32bmip.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32b4300 "$(tdir_elf32b4300)" -+eelf32bfin.c: $(srcdir)/emulparams/bfin.sh \ ++ ++eelf32bfin.c: $(srcdir)/emulparams/elf32bfin.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/bfin.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32bfin "$(tdir_elf32bfin)" bfin ++ +eelf32bfinfd.c: $(srcdir)/emulparams/elf32bfinfd.sh \ -+ $(srcdir)/emulparams/bfin.sh \ ++ $(srcdir)/emulparams/elf32bfin.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/bfin.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32bfinfd "$(tdir_elf32bfinfd)" elf32bfinfd ++ +eelf32bmip.c: $(srcdir)/emulparams/elf32bmip.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32bmip "$(tdir_elf32bmip)" ++ +eelf32bmipn32.c: $(srcdir)/emulparams/elf32bmipn32.sh \ + $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/irix.em $(srcdir)/emultempl/mipself.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32bmipn32 "$(tdir_elf32bmipn32)" ++ +eelf32bsmip.c: $(srcdir)/emulparams/elf32bsmip.sh \ + $(srcdir)/emulparams/elf32bmip.sh $(ELF_DEPS) $(srcdir)/emultempl/irix.em \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32bsmip "$(tdir_elf32bsmip)" ++ +eelf32btsmip.c: $(srcdir)/emulparams/elf32btsmip.sh \ + $(srcdir)/emulparams/elf32bmip.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32btsmip "$(tdir_elf32btsmip)" ++ +eelf32btsmip_fbsd.c: $(srcdir)/emulparams/elf32btsmip_fbsd.sh \ + $(srcdir)/emulparams/elf32bmip.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32btsmip_fbsd "$(tdir_elf32btsmip_fbsd)" ++ +eelf32btsmipn32.c: $(srcdir)/emulparams/elf32btsmipn32.sh \ + $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32btsmipn32 "$(tdir_elf32btsmipn32)" ++ +eelf32btsmipn32_fbsd.c: $(srcdir)/emulparams/elf32btsmipn32_fbsd.sh \ + $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32btsmipn32_fbsd "$(tdir_elf32btsmipn32_fbsd)" ++ +eelf32cr16.c: $(srcdir)/emulparams/elf32cr16.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/cr16elf.em \ + $(srcdir)/scripttempl/elf32cr16.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32cr16 "$(tdir_elf32crx)" ++ +eelf32cr16c.c: $(srcdir)/emulparams/elf32cr16c.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf32cr16c.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32cr16c "$(tdir_elf32cr16c)" ++ +eelf32crx.c: $(srcdir)/emulparams/elf32crx.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/crxelf.em \ + $(srcdir)/scripttempl/elf32crx.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32crx "$(tdir_elf32crx)" ++ +eelf32ebmip.c: $(srcdir)/emulparams/elf32ebmip.sh \ + $(srcdir)/emulparams/elf32bmip.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ebmip "$(tdir_elf32ebmip)" ++ +eelf32ebmipvxworks.c: $(srcdir)/emulparams/elf32ebmipvxworks.sh \ + $(srcdir)/emulparams/elf32bmip.sh $(srcdir)/emulparams/vxworks.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/generic.em $(srcdir)/emultempl/mipself.em \ + $(srcdir)/emultempl/vxworks.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ebmipvxworks "$(tdir_elf32ebmipvxworks)" ++ +eelf32elmip.c: $(srcdir)/emulparams/elf32elmip.sh \ + $(srcdir)/emulparams/elf32lmip.sh $(srcdir)/emulparams/elf32bmip.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32elmip "$(tdir_elf32elmip)" ++ +eelf32elmipvxworks.c: $(srcdir)/emulparams/elf32elmipvxworks.sh \ + $(srcdir)/emulparams/elf32bmip.sh $(srcdir)/emulparams/vxworks.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/generic.em $(srcdir)/emultempl/mipself.em \ + $(srcdir)/emultempl/vxworks.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32elmipvxworks "$(tdir_elf32elmipvxworks)" ++ +eelf32lr5900.c: $(srcdir)/emulparams/elf32lr5900.sh \ + $(srcdir)/emulparams/elf32bmip.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32lr5900 "$(tdir_elf32lr5900)" ++ +eelf32lr5900n32.c: $(srcdir)/emulparams/elf32lr5900n32.sh \ + $(srcdir)/emulparams/elf32bmipn32-defs.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32lr5900n32 "$(tdir_elf32lr5900n32)" ++ +eelf32epiphany.c: $(srcdir)/emulparams/elf32epiphany.sh \ + $(ELF_DEPS) ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32epiphany "$(tdir_epiphany)" ++ +eelf32epiphany_4x4.c: $(srcdir)/emulparams/elf32epiphany_4x4.sh \ + $(srcdir)/emultempl/elf32.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/epiphany_4x4.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32epiphany_4x4 "$(tdir_epiphany_4x4)" ++ +eelf32fr30.c: $(srcdir)/emulparams/elf32fr30.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32fr30 "$(tdir_fr30)" ++ +eelf32frv.c: $(srcdir)/emulparams/elf32frv.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32frv "$(tdir_frv)" ++ +eelf32frvfd.c: $(srcdir)/emulparams/elf32frvfd.sh \ + $(srcdir)/emulparams/elf32frv.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32frvfd "$(tdir_frv)" ++ +eelf32i370.c: $(srcdir)/emulparams/elf32i370.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elfi370.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32i370 "$(tdir_elf32i370)" ++ +eelf32ip2k.c: $(srcdir)/emulparams/elf32ip2k.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ip2k "$(tdir_ip2k)" ++ +eelf32iq10.c: $(srcdir)/emulparams/elf32iq10.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/iq2000.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32iq10 "$(tdir_iq10)" ++ +eelf32iq2000.c: $(srcdir)/emulparams/elf32iq2000.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/iq2000.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32iq2000 "$(tdir_iq2000)" ++ +eelf32l4300.c: $(srcdir)/emulparams/elf32l4300.sh \ + $(srcdir)/emulparams/elf32b4300.sh $(srcdir)/emulparams/elf32bmip.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32l4300 "$(tdir_elf32l4300)" ++ +eelf32lm32.c: $(srcdir)/emulparams/elf32lm32.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32lm32 "$(tdir_elf32lm32)" ++ +eelf32lm32fd.c: $(srcdir)/emulparams/elf32lm32fd.sh \ + $(srcdir)/emulparams/elf32lm32.sh $(ELF_DEPS) \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32lm32fd "$(tdir_elf32lm32fd)" ++ +eelf32lmip.c: $(srcdir)/emulparams/elf32lmip.sh \ + $(srcdir)/emulparams/elf32bmip.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32lmip "$(tdir_elf32lmip)" ++ +eelf32lppc.c: $(srcdir)/emulparams/elf32lppc.sh \ + $(srcdir)/emulparams/elf32ppccommon.sh \ + $(srcdir)/emulparams/elf32ppc.sh $(srcdir)/emultempl/ppc32elf.em \ + ldemul-list.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32lppc "$(tdir_elf32lppc)" ++ +eelf32lppclinux.c: $(srcdir)/emulparams/elf32lppclinux.sh \ + $(srcdir)/emulparams/elf32lppc.sh $(srcdir)/emulparams/elf32ppc.sh \ + $(srcdir)/emulparams/elf32ppccommon.sh $(srcdir)/emultempl/ppc32elf.em \ + ldemul-list.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32lppclinux "$(tdir_elf32lppclinux)" ++ +eelf32lppcnto.c: $(srcdir)/emulparams/elf32lppcnto.sh \ + $(srcdir)/emulparams/elf32ppc.sh $(srcdir)/emulparams/elf32ppccommon.sh \ + $(srcdir)/emultempl/ppc32elf.em $(ELF_DEPS) \ + ldemul-list.h \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32lppcnto "$(tdir_elf32lppcnto)" ++ +eelf32lppcsim.c: $(srcdir)/emulparams/elf32lppcsim.sh \ + $(srcdir)/emulparams/elf32lppc.sh $(srcdir)/emulparams/elf32ppc.sh \ + $(srcdir)/emulparams/elf32ppccommon.sh $(srcdir)/emultempl/ppc32elf.em \ + ldemul-list.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32lppcsim "$(tdir_elf32lppcsim)" ++ +eelf32lsmip.c: $(srcdir)/emulparams/elf32lsmip.sh \ + $(srcdir)/emulparams/elf32lmip.sh $(srcdir)/emulparams/elf32bmip.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32lsmip "$(tdir_elf32lsmip)" ++ +eelf32ltsmip.c: $(srcdir)/emulparams/elf32ltsmip.sh \ + $(srcdir)/emulparams/elf32btsmip.sh $(srcdir)/emulparams/elf32bmip.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ltsmip "$(tdir_elf32ltsmip)" ++ +eelf32ltsmip_fbsd.c: $(srcdir)/emulparams/elf32ltsmip_fbsd.sh \ + $(srcdir)/emulparams/elf32btsmip.sh $(srcdir)/emulparams/elf32bmip.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ltsmip_fbsd "$(tdir_elf32ltsmip_fbsd)" ++ +eelf32ltsmipn32.c: $(srcdir)/emulparams/elf32ltsmipn32.sh \ + $(srcdir)/emulparams/elf32btsmipn32.sh \ + $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ltsmipn32 "$(tdir_elf32ltsmipn32)" ++ +eelf32ltsmipn32_fbsd.c: $(srcdir)/emulparams/elf32ltsmipn32_fbsd.sh \ + $(srcdir)/emulparams/elf32btsmipn32.sh \ + $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ltsmipn32_fbsd "$(tdir_elf32ltsmipn32_fbsd)" ++ +eelf32m32c.c: $(srcdir)/emulparams/elf32m32c.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/needrelax.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32m32c "$(tdir_m32c)" ++ +eelf32mbel_linux.c: $(srcdir)/emulparams/elf32mbel_linux.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32mbel_linux "$(tdir_microblazeel)" ++ +eelf32mb_linux.c: $(srcdir)/emulparams/elf32mb_linux.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32mb_linux "$(tdir_microblaze)" ++ +eelf32mcore.c: $(srcdir)/emulparams/elf32mcore.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32mcore "$(tdir_mcore)" ++ +eelf32mep.c: $(srcdir)/emulparams/elf32mep.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/mep.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32mep "$(tdir_mep)" ++ +eelf32metag.c: $(srcdir)/emulparams/elf32metag.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/metagelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32metag "$(tdir_metag)" ++ +eelf32microblazeel.c: $(srcdir)/emulparams/elf32microblazeel.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elfmicroblaze.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32microblazeel "$(tdir_microblazeel)" ++ +eelf32microblaze.c: $(srcdir)/emulparams/elf32microblaze.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elfmicroblaze.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32microblaze "$(tdir_microblaze)" ++ +eelf32mipswindiss.c: $(srcdir)/emulparams/elf32mipswindiss.sh $(ELF_DEPS) \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32mipswindiss "$(tdir_elf32mipswindiss)" ++ +eelf32moxie.c: $(srcdir)/emulparams/elf32moxie.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32moxie "$(tdir_moxie)" ++ +eelf32mt.c: $(srcdir)/emulparams/elf32mt.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32mt "$(tdir_mt)" -+eelf32openrisc.c: $(srcdir)/emulparams/elf32openrisc.sh \ -+ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32openrisc "$(tdir_openrisc)" ++ ++eelf32or1k.c: $(srcdir)/emulparams/elf32or1k.sh \ ++ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} ++ ++eelf32or1k_linux.c: $(srcdir)/emulparams/elf32or1k_linux.sh \ ++ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} ++ +eelf32ppc.c: $(srcdir)/emulparams/elf32ppc.sh \ + $(srcdir)/emulparams/elf32ppccommon.sh $(srcdir)/emultempl/ppc32elf.em \ + ldemul-list.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ppc "$(tdir_elf32ppc)" ++ +eelf32ppc_fbsd.c: $(srcdir)/emulparams/elf32ppc_fbsd.sh \ + $(srcdir)/emulparams/elf32ppc.sh $(srcdir)/emulparams/elf32ppccommon.sh \ + $(srcdir)/emultempl/ppc32elf.em $(ELF_DEPS) \ + ldemul-list.h \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ppc_fbsd "$(tdir_elf32ppc_fbsd)" ++ +eelf32ppclinux.c: $(srcdir)/emulparams/elf32ppclinux.sh \ + $(srcdir)/emulparams/elf32ppc.sh $(srcdir)/emulparams/elf32ppccommon.sh \ + $(srcdir)/emultempl/ppc32elf.em $(ELF_DEPS) \ + ldemul-list.h \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ppclinux "$(tdir_elf32ppclinux)" ++ +eelf32ppcnto.c: $(srcdir)/emulparams/elf32ppcnto.sh \ + $(srcdir)/emulparams/elf32ppc.sh $(srcdir)/emulparams/elf32ppccommon.sh \ + $(srcdir)/emultempl/ppc32elf.em $(ELF_DEPS) \ + ldemul-list.h \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ppcnto "$(tdir_elf32ppcnto)" ++ +eelf32ppcsim.c: $(srcdir)/emulparams/elf32ppcsim.sh \ + $(srcdir)/emulparams/elf32ppc.sh $(srcdir)/emulparams/elf32ppccommon.sh \ + $(srcdir)/emultempl/ppc32elf.em $(ELF_DEPS) \ + ldemul-list.h \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ppcsim "$(tdir_elf32ppcsim)" ++ +eelf32ppcvxworks.c: $(srcdir)/emulparams/elf32ppcvxworks.sh \ + $(srcdir)/emulparams/elf32ppccommon.sh $(srcdir)/emulparams/vxworks.sh \ + $(srcdir)/emultempl/vxworks.em $(ELF_DEPS) \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ppcvxworks "$(tdir_elf32ppcvxworks)" ++ +eelf32ppcwindiss.c: $(srcdir)/emulparams/elf32ppcwindiss.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ppcwindiss "$(tdir_elf32ppcwindiss)" ++ +eelf32rl78.c: $(srcdir)/emulparams/elf32rl78.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32rl78 "$(tdir_elf32rl78)" ++ +eelf32rx.c: $(srcdir)/emulparams/elf32rx.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32rx "$(tdir_elf32rx)" ++ +eelf32tilegx.c: $(srcdir)/emulparams/elf32tilegx.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/needrelax.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32tilegx "$(tdir_tilegx)" ++ +eelf32tilegx_be.c: $(srcdir)/emulparams/elf32tilegx_be.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/needrelax.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32tilegx_be "$(tdir_tilegx_be)" ++ +eelf32tilepro.c: $(srcdir)/emulparams/elf32tilepro.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/needrelax.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32tilepro "$(tdir_tilepro)" ++ +eelf32vax.c: $(srcdir)/emulparams/elf32vax.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32vax "$(tdir_elf32vax)" ++ +eelf32xc16x.c: $(srcdir)/emulparams/elf32xc16x.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/needrelax.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32xc16x "$(tdir_xc16x)" ++ +eelf32xc16xl.c: $(srcdir)/emulparams/elf32xc16xl.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/needrelax.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32xc16xl "$(tdir_xc16xl)" ++ +eelf32xc16xs.c: $(srcdir)/emulparams/elf32xc16xs.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/needrelax.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32xc16xs "$(tdir_xc16xs)" ++ +eelf32xstormy16.c: $(srcdir)/emulparams/elf32xstormy16.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/needrelax.em \ + $(srcdir)/scripttempl/xstormy16.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32xstormy16 "$(tdir_xstormy16)" ++ +eelf32xtensa.c: $(srcdir)/emulparams/elf32xtensa.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/xtensaelf.em $(INCDIR)/xtensa-config.h \ + $(BFDDIR)/elf-bfd.h $(BFDDIR)/libbfd.h $(INCDIR)/elf/xtensa.h \ + $(srcdir)/scripttempl/elfxtensa.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32xtensa "$(tdir_elf32xtensa)" ++ +eelf_i386.c: $(srcdir)/emulparams/elf_i386.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_i386 "$(tdir_elf_i386)" ++ +eelf_i386_be.c: $(srcdir)/emulparams/elf_i386_be.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_i386_be "$(tdir_elf_i386_be)" ++ +eelf_i386_chaos.c: $(srcdir)/emulparams/elf_i386_chaos.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf_chaos.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_i386_chaos "$(tdir_elf_i386_chaos)" ++ +eelf_i386_fbsd.c: $(srcdir)/emulparams/elf_i386_fbsd.sh \ + $(srcdir)/emulparams/elf_i386.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_i386_fbsd "$(tdir_elf_i386_fbsd)" ++ +eelf_i386_ldso.c: $(srcdir)/emulparams/elf_i386_ldso.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_i386_ldso "$(tdir_elf_i386_ldso)" ++ +eelf_i386_nacl.c: $(srcdir)/emulparams/elf_i386_nacl.sh \ + $(srcdir)/emulparams/elf_i386.sh \ + $(srcdir)/emulparams/elf_nacl.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_i386_nacl "$(tdir_elf_i386_nacl)" ++ +eelf_i386_sol2.c: $(srcdir)/emulparams/elf_i386_sol2.sh \ + $(srcdir)/emulparams/solaris2.sh \ + $(srcdir)/emultempl/solaris2.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_i386_sol2 "$(tdir_elf_i386_sol2)" ++ +eelf_i386_vxworks.c: $(srcdir)/emulparams/elf_i386_vxworks.sh \ + $(srcdir)/emulparams/vxworks.sh $(srcdir)/emultempl/vxworks.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_i386_vxworks "$(tdir_elf_i386_vxworks)" ++ +eelf_s390.c: $(srcdir)/emulparams/elf_s390.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_s390 "$(tdir_elf_s390)" ++ +egld960.c: $(srcdir)/emulparams/gld960.sh \ + $(srcdir)/emultempl/gld960.em $(srcdir)/scripttempl/i960.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} gld960 "$(tdir_gld960)" ++ +egld960coff.c: $(srcdir)/emulparams/gld960coff.sh \ + $(srcdir)/emultempl/gld960c.em $(srcdir)/scripttempl/i960.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} gld960coff "$(tdir_gld960coff)" ++ +eh8300.c: $(srcdir)/emulparams/h8300.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/h8300.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300 "$(tdir_h8300)" ++ +eh8300elf.c: $(srcdir)/emulparams/h8300elf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300elf "$(tdir_h8300elf)" ++ +eh8300h.c: $(srcdir)/emulparams/h8300h.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/h8300h.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300h "$(tdir_h8300h)" ++ +eh8300helf.c: $(srcdir)/emulparams/h8300helf.sh \ + $(srcdir)/emulparams/h8300elf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300helf "$(tdir_h8300helf)" ++ +eh8300hn.c: $(srcdir)/emulparams/h8300hn.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/h8300hn.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300hn "$(tdir_h8300hn)" ++ +eh8300hnelf.c: $(srcdir)/emulparams/h8300hnelf.sh \ + $(srcdir)/emulparams/h8300elf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300hnelf "$(tdir_h8300hnelf)" ++ +eh8300s.c: $(srcdir)/emulparams/h8300s.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/h8300s.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300s "$(tdir_h8300s)" ++ +eh8300self.c: $(srcdir)/emulparams/h8300self.sh \ + $(srcdir)/emulparams/h8300elf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300self "$(tdir_h8300self)" ++ +eh8300sn.c: $(srcdir)/emulparams/h8300sn.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/h8300sn.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300sn "$(tdir_h8300sn)" ++ +eh8300snelf.c: $(srcdir)/emulparams/h8300snelf.sh \ + $(srcdir)/emulparams/h8300elf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300snelf "$(tdir_h8300snelf)" ++ +eh8300sx.c: $(srcdir)/emulparams/h8300sx.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/h8300sx.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300sx "$(tdir_h8300sx)" ++ +eh8300sxelf.c: $(srcdir)/emulparams/h8300sxelf.sh \ + $(srcdir)/emulparams/h8300elf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300sxelf "$(tdir_h8300sxelf)" ++ +eh8300sxn.c: $(srcdir)/emulparams/h8300sxn.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/h8300sxn.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300sxn "$(tdir_h8300sxn)" ++ +eh8300sxnelf.c: $(srcdir)/emulparams/h8300sxnelf.sh \ + $(srcdir)/emulparams/h8300elf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300sxnelf "$(tdir_h8300sxnelf)" ++ +eh8500.c: $(srcdir)/emulparams/h8500.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/h8500.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8500 "$(tdir_h8500)" ++ +eh8500b.c: $(srcdir)/emulparams/h8500b.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/h8500b.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8500b "$(tdir_h8500b)" ++ +eh8500c.c: $(srcdir)/emulparams/h8500c.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/h8500c.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8500c "$(tdir_h8500c)" ++ +eh8500m.c: $(srcdir)/emulparams/h8500m.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/h8500m.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8500m "$(tdir_h8500m)" ++ +eh8500s.c: $(srcdir)/emulparams/h8500s.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/h8500s.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8500s "$(tdir_h8500s)" ++ +ehp300bsd.c: $(srcdir)/emulparams/hp300bsd.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} hp300bsd "$(tdir_hp300bsd)" ++ +ehp3hpux.c: $(srcdir)/emulparams/hp3hpux.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} hp3hpux "$(tdir_hp3hpux)" ++ +ehppaelf.c: $(srcdir)/emulparams/hppaelf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/hppaelf.em \ + $(srcdir)/scripttempl/hppaelf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} hppaelf "$(tdir_hppaelf)" ++ +ehppalinux.c: $(srcdir)/emulparams/hppalinux.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/hppaelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} hppalinux "$(tdir_hppalinux)" ++ +ehppanbsd.c: $(srcdir)/emulparams/hppanbsd.sh \ + $(srcdir)/emulparams/hppaelf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/hppaelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} hppanbsd "$(tdir_hppanbsd)" ++ +ehppaobsd.c: $(srcdir)/emulparams/hppaobsd.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/hppaelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} hppaobsd "$(tdir_hppaobsd)" ++ +ei386aout.c: $(srcdir)/emulparams/i386aout.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386aout "$(tdir_i386aout)" ++ +ei386beos.c: $(srcdir)/emulparams/i386beos.sh \ + $(srcdir)/emultempl/beos.em $(srcdir)/scripttempl/i386beos.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386beos "$(tdir_i386beos)" ++ +ei386bsd.c: $(srcdir)/emulparams/i386bsd.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386bsd "$(tdir_i386bsd)" ++ +ei386coff.c: $(srcdir)/emulparams/i386coff.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/i386coff.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386coff "$(tdir_i386coff)" ++ +ei386go32.c: $(srcdir)/emulparams/i386go32.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/i386go32.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386go32 "$(tdir_i386go32)" ++ +ei386linux.c: $(srcdir)/emulparams/i386linux.sh \ + $(srcdir)/emultempl/linux.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386linux "$(tdir_i386linux)" ++ +ei386lynx.c: $(srcdir)/emulparams/i386lynx.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386lynx "$(tdir_i386lynx)" ++ +ei386mach.c: $(srcdir)/emulparams/i386mach.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386mach "$(tdir_i386mach)" ++ +ei386moss.c: $(srcdir)/emulparams/i386moss.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386moss "$(tdir_i386moss)" ++ +ei386msdos.c: $(srcdir)/emulparams/i386msdos.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/i386msdos.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386msdos "$(tdir_i386msdos)" ++ +ei386nbsd.c: $(srcdir)/emulparams/i386nbsd.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386nbsd "$(tdir_i386nbsd)" ++ +ei386nto.c: $(srcdir)/emulparams/i386nto.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386nto "$(tdir_i386nto)" ++ +ei386nw.c: $(srcdir)/emulparams/i386nw.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/nw.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386nw "$(tdir_i386nw)" ++ +ei386pe.c: $(srcdir)/emulparams/i386pe.sh \ + $(srcdir)/emultempl/pe.em $(srcdir)/scripttempl/pe.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386pe "$(tdir_i386pe)" ++ +ei386pe_posix.c: $(srcdir)/emulparams/i386pe_posix.sh \ + $(srcdir)/emultempl/pe.em $(srcdir)/scripttempl/pe.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386pe_posix "$(tdir_i386pe_posix)" ++ +ei386pep.c: $(srcdir)/emulparams/i386pep.sh \ + $(srcdir)/emultempl/pep.em $(srcdir)/scripttempl/pep.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386pep "$(tdir_i386pe)" ++ +elnk960.c: $(srcdir)/emulparams/lnk960.sh \ + $(srcdir)/emultempl/lnk960.em $(srcdir)/scripttempl/i960.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} lnk960 "$(tdir_lnk960)" ++ +em32relf.c: $(srcdir)/emulparams/m32relf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m32relf "$(tdir_m32r)" ++ +em32relf_linux.c: $(srcdir)/emulparams/m32relf_linux.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m32relf_linux "$(tdir_m32relf_linux)" ++ +em32rlelf.c: $(srcdir)/emulparams/m32rlelf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m32rlelf "$(tdir_m32rlelf)" ++ +em32rlelf_linux.c: $(srcdir)/emulparams/m32rlelf_linux.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m32rlelf_linux "$(tdir_m32rlelf_linux)" ++ +em68hc11elf.c: $(srcdir)/emulparams/m68hc11elf.sh \ + $(srcdir)/emultempl/m68hc1xelf.em $(ELF_DEPS) \ + $(srcdir)/scripttempl/elfm68hc11.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m68hc11elf "$(tdir_m68hc11)" ++ +em68hc11elfb.c: $(srcdir)/emulparams/m68hc11elfb.sh \ + $(srcdir)/emultempl/m68hc1xelf.em $(ELF_DEPS) \ + $(srcdir)/scripttempl/elfm68hc11.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m68hc11elfb "$(tdir_m68hc11b)" ++ +em68hc12elf.c: $(srcdir)/emulparams/m68hc12elf.sh \ + $(srcdir)/emultempl/m68hc1xelf.em $(ELF_DEPS) \ + $(srcdir)/scripttempl/elfm68hc12.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m68hc12elf "$(tdir_m68hc12)" ++ +em68hc12elfb.c: $(srcdir)/emulparams/m68hc12elfb.sh \ + $(srcdir)/emultempl/m68hc1xelf.em $(ELF_DEPS) \ + $(srcdir)/scripttempl/elfm68hc12.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m68hc12elfb "$(tdir_m68hc12b)" ++ +em68k4knbsd.c: $(srcdir)/emulparams/m68k4knbsd.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m68k4knbsd "$(tdir_m68k4knbsd)" ++ +em68kaout.c: $(srcdir)/emulparams/m68kaout.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m68kaout "$(tdir_m68kaout)" ++ +em68kaux.c: $(srcdir)/emulparams/m68kaux.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/m68kaux.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m68kaux "$(tdir_m68kaux)" ++ +em68kcoff.c: $(srcdir)/emulparams/m68kcoff.sh \ + $(srcdir)/emultempl/m68kcoff.em $(srcdir)/scripttempl/m68kcoff.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m68kcoff "$(tdir_m68kcoff)" ++ +em68kelf.c: $(srcdir)/emulparams/m68kelf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/m68kelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m68kelf "$(tdir_m68kelf)" ++ +em68kelfnbsd.c: $(srcdir)/emulparams/m68kelfnbsd.sh \ + $(srcdir)/emulparams/m68kelf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/m68kelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m68kelfnbsd "$(tdir_m68kelfnbsd)" ++ +em68klinux.c: $(srcdir)/emulparams/m68klinux.sh \ + $(srcdir)/emultempl/linux.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m68klinux "$(tdir_m68klinux)" ++ +em68knbsd.c: $(srcdir)/emulparams/m68knbsd.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m68knbsd "$(tdir_m68knbsd)" ++ +em68kpsos.c: $(srcdir)/emulparams/m68kpsos.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/psos.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m68kpsos "$(tdir_m68kpsos)" ++ +em88kbcs.c: $(srcdir)/emulparams/m88kbcs.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/m88kbcs.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m88kbcs "$(tdir_m88kbcs)" ++ +emcorepe.c: $(srcdir)/emulparams/mcorepe.sh \ + $(srcdir)/emultempl/pe.em $(srcdir)/scripttempl/pe.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} mcorepe "$(tdir_mcorepe)" ++ +emn10200.c: $(srcdir)/emulparams/mn10200.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} mn10200 "$(tdir_mn10200)" ++ +emn10300.c: $(srcdir)/emulparams/mn10300.sh \ + $(srcdir)/emulparams/mn10200.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} mn10300 "$(tdir_mn10300)" -+emsp430x110.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x110 "$(tdir_msp430x110)" msp430all -+emsp430x1101.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x1101 "$(tdir_msp430x1101)" msp430all -+emsp430x1111.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x1111 "$(tdir_msp430x1111)" msp430all -+emsp430x112.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x112 "$(tdir_msp430x112)" msp430all -+emsp430x1121.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x1121 "$(tdir_msp430x1121)" msp430all -+emsp430x1122.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x1122 "$(tdir_msp430x1122)" msp430all -+emsp430x1132.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x1132 "$(tdir_msp430x1132)" msp430all -+emsp430x122.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x122 "$(tdir_msp430x122)" msp430all -+emsp430x1222.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x1222 "$(tdir_msp430x1222)" msp430all -+emsp430x123.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x123 "$(tdir_msp430x123)" msp430all -+emsp430x1232.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x1232 "$(tdir_msp430x1232)" msp430all -+emsp430x133.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x133 "$(tdir_msp430x133)" msp430all -+emsp430x1331.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x1331 "$(tdir_msp430x1331)" msp430all -+emsp430x135.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x135 "$(tdir_msp430x135)" msp430all -+emsp430x1351.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x1351 "$(tdir_msp430x1351)" msp430all -+emsp430x147.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x147 "$(tdir_msp430x147)" msp430all -+emsp430x148.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x148 "$(tdir_msp430x148)" msp430all -+emsp430x149.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x149 "$(tdir_msp430x149)" msp430all -+emsp430x155.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x155 "$(tdir_msp430x155)" msp430all -+emsp430x156.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x156 "$(tdir_msp430x156)" msp430all -+emsp430x157.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x157 "$(tdir_msp430x157)" msp430all -+emsp430x1610.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x1610 "$(tdir_msp430x1610)" msp430all -+emsp430x1611.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x1611 "$(tdir_msp430x1611)" msp430all -+emsp430x1612.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x1612 "$(tdir_msp430x1612)" msp430all -+emsp430x167.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x167 "$(tdir_msp430x167)" msp430all -+emsp430x168.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x168 "$(tdir_msp430x168)" msp430all -+emsp430x169.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x169 "$(tdir_msp430x169)" msp430all -+emsp430x2101.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x2101 "$(tdir_msp430x2101)" msp430all -+emsp430x2111.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x2111 "$(tdir_msp430x2111)" msp430all -+emsp430x2121.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x2121 "$(tdir_msp430x2121)" msp430all -+emsp430x2131.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x2131 "$(tdir_msp430x2131)" msp430all -+emsp430x311.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x311 "$(tdir_msp430x311)" msp430all -+emsp430x312.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x312 "$(tdir_msp430x312)" msp430all -+emsp430x313.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x313 "$(tdir_msp430x313)" msp430all -+emsp430x314.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x314 "$(tdir_msp430x314)" msp430all -+emsp430x315.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x315 "$(tdir_msp430x315)" msp430all -+emsp430x323.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x323 "$(tdir_msp430x323)" msp430all -+emsp430x325.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x325 "$(tdir_msp430x325)" msp430all -+emsp430x336.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x336 "$(tdir_msp430x336)" msp430all -+emsp430x337.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x337 "$(tdir_msp430x337)" msp430all -+emsp430x412.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x412 "$(tdir_msp430x412)" msp430all -+emsp430x413.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x413 "$(tdir_msp430x413)" msp430all -+emsp430x415.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x415 "$(tdir_msp430x415)" msp430all -+emsp430x417.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x417 "$(tdir_msp430x417)" msp430all -+emsp430x435.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x435 "$(tdir_msp430x435)" msp430all -+emsp430x436.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x436 "$(tdir_msp430x436)" msp430all -+emsp430x437.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x437 "$(tdir_msp430x437)" msp430all -+emsp430x447.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x447 "$(tdir_msp430x447)" msp430all -+emsp430x448.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x448 "$(tdir_msp430x448)" msp430all -+emsp430x449.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x449 "$(tdir_msp430x449)" msp430all -+emsp430xE423.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430xE423 "$(tdir_msp430xE423)" msp430all -+emsp430xE425.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430xE425 "$(tdir_msp430xE425)" msp430all -+emsp430xE427.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430xE427 "$(tdir_msp430xE427)" msp430all -+emsp430xG437.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430xG437 "$(tdir_msp430xG437)" msp430all -+emsp430xG438.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430xG438 "$(tdir_msp430xG438)" msp430all -+emsp430xG439.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430xG439 "$(tdir_msp430xG439)" msp430all -+emsp430xW423.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430xW423 "$(tdir_msp430xW423)" msp430all -+emsp430xW425.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430xW425 "$(tdir_msp430xW425)" msp430all -+emsp430xW427.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430xW427 "$(tdir_msp430xW427)" msp430all -+emsp430X.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430X "$(tdir_msp430X)" msp430all ++ ++emsp430.c: $(srcdir)/emulparams/msp430.sh \ ++ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc ${GEN_DEPENDS} ++ ++emsp430X.c: $(srcdir)/emulparams/msp430.sh $(srcdir)/emulparams/msp430X.sh \ ++ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc ${GEN_DEPENDS} ++ +ends32elf.c: $(srcdir)/emulparams/nds32elf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/nds32elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} nds32elf "$(tdir_nds32)" ++ +ends32elf16m.c: $(srcdir)/emulparams/nds32elf16m.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/nds32elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} nds32elf16m "$(tdir_nds32)" ++ +ends32belf.c: $(srcdir)/emulparams/nds32belf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/nds32elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} nds32belf "$(tdir_nds32belf)" ++ +ends32belf16m.c: $(srcdir)/emulparams/nds32belf16m.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/nds32elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} nds32belf16m "$(tdir_nds32belf)" ++ +ends32elf_linux.c: $(srcdir)/emulparams/nds32elf_linux.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/nds32elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} nds32elf_linux "$(tdir_nds32elf_linux)" ++ +ends32belf_linux.c: $(srcdir)/emulparams/nds32belf_linux.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/nds32elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} nds32belf_linux "$(tdir_nds32belf_linux)" ++ +enews.c: $(srcdir)/emulparams/news.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} news "$(tdir_news)" ++ +enios2elf.c: $(srcdir)/emulparams/nios2elf.sh \ -+ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} nios2elf "$(tdir_nios2elf)" ++ $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/nios2elf.em \ ++ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} ++ +enios2linux.c: $(srcdir)/emulparams/nios2linux.sh \ -+ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} nios2linux "$(tdir_nios2linux)" ++ $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/nios2elf.em \ ++ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} ++ +ens32knbsd.c: $(srcdir)/emulparams/ns32knbsd.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/emultempl/netbsd.em \ + $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} ns32knbsd "$(tdir_ns32knbsd)" ++ +eaarch64elf.c: $(srcdir)/emulparams/aarch64elf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} aarch64elf "$(tdir_aarch64elf)" ++ +eaarch64elf32.c: $(srcdir)/emulparams/aarch64elf32.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} aarch64elf32 "$(tdir_aarch64elf32)" ++ +eaarch64elfb.c: $(srcdir)/emulparams/aarch64elfb.sh $(srcdir)/emulparams/aarch64elf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} aarch64elfb "$(tdir_aarch64elfb)" ++ +eaarch64elf32b.c: $(srcdir)/emulparams/aarch64elf32b.sh $(srcdir)/emulparams/aarch64elf32.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} aarch64elf32b "$(tdir_aarch64elf32b)" ++ +eaarch64linux.c: $(srcdir)/emulparams/aarch64linux.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} aarch64linux "$(tdir_aarch64linux)" ++ +eaarch64linuxb.c: $(srcdir)/emulparams/aarch64linuxb.sh $(srcdir)/emulparams/aarch64linux.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} aarch64linuxb "$(tdir_aarch64linuxb)" ++ +eaarch64linux32.c: $(srcdir)/emulparams/aarch64linux32.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} aarch64linux32 "$(tdir_aarch64linux32)" ++ +eaarch64linux32b.c: $(srcdir)/emulparams/aarch64linux32b.sh $(srcdir)/emulparams/aarch64linux32.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} aarch64linux32b "$(tdir_aarch64linux32b)" -+eor32.c: $(srcdir)/emulparams/or32.sh \ -+ $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/or32.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} or32 "$(tdir_or32)" -+eor32elf.c: $(srcdir)/emulparams/or32elf.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} or32elf "$(tdir_or32elf)" ++ +epc532macha.c: $(srcdir)/emulparams/pc532macha.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} pc532macha "$(tdir_pc532macha)" ++ +epdp11.c: $(srcdir)/emulparams/pdp11.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} pdp11 "$(tdir_pdp11)" ++ +epjelf.c: $(srcdir)/emulparams/pjelf.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} pjelf "$(tdir_pjelf)" ++ +epjlelf.c: $(srcdir)/emulparams/pjlelf.sh $(srcdir)/emulparams/pjelf.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} pjlelf "$(tdir_pjlelf)" ++ +eppclynx.c: $(srcdir)/emulparams/ppclynx.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} ppclynx "$(tdir_ppclynx)" ++ +eppcmacos.c: $(srcdir)/emulparams/ppcmacos.sh \ + $(srcdir)/emultempl/aix.em $(srcdir)/scripttempl/aix.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} ppcmacos "$(tdir_ppcmacos)" ++ +eppcnw.c: $(srcdir)/emulparams/ppcnw.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/nw.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} ppcnw "$(tdir_ppcnw)" ++ +eppcpe.c: $(srcdir)/emulparams/ppcpe.sh \ + $(srcdir)/emultempl/pe.em $(srcdir)/scripttempl/ppcpe.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} ppcpe "$(tdir_ppcpe)" ++ +eriscix.c: $(srcdir)/emulparams/riscix.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} riscix "$(tdir_riscix)" -+escore3_elf.c: $(srcdir)/emulparams/scoreelf.sh \ ++ ++escore3_elf.c: $(srcdir)/emulparams/score3_elf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/scoreelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} score3_elf "$(tdir_score3_elf)" scoreelf -+escore7_elf.c: $(srcdir)/emulparams/scoreelf.sh \ ++ ++escore7_elf.c: $(srcdir)/emulparams/score3_elf.sh \ ++ $(srcdir)/emulparams/score7_elf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/scoreelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} score7_elf "$(tdir_score7_elf)" scoreelf ++ +esh.c: $(srcdir)/emulparams/sh.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/sh.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} sh "$(tdir_sh)" ++ +eshelf.c: $(srcdir)/emulparams/shelf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shelf "$(tdir_shelf)" ++ +eshelf32.c: $(srcdir)/emulparams/shelf32.sh \ + $(BFDDIR)/libbfd.h $(INCDIR)/libiberty.h \ + $(srcdir)/emultempl/sh64elf.em $(INCDIR)/elf/sh.h $(BFDDIR)/elf-bfd.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shelf32 "$(tdir_shelf32)" ++ +eshelf32_linux.c: $(srcdir)/emulparams/shelf32_linux.sh \ + $(srcdir)/emulparams/shelf32.sh \ + $(BFDDIR)/libbfd.h $(INCDIR)/libiberty.h \ + $(srcdir)/emultempl/sh64elf.em $(INCDIR)/elf/sh.h $(BFDDIR)/elf-bfd.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shelf32_linux "$(tdir_shelf32_linux)" ++ +eshelf32_nbsd.c: $(srcdir)/emulparams/shelf32_nbsd.sh \ + $(srcdir)/emulparams/shelf32.sh \ + $(BFDDIR)/libbfd.h $(INCDIR)/libiberty.h \ + $(srcdir)/emultempl/sh64elf.em $(INCDIR)/elf/sh.h $(BFDDIR)/elf-bfd.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shelf32_nbsd "$(tdir_shelf32_nbsd)" ++ +eshelf_fd.c: $(srcdir)/emulparams/shelf_fd.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shelf_fd "$(tdir_shelf_fd)" ++ +eshelf_linux.c: $(srcdir)/emulparams/shelf_linux.sh \ + $(srcdir)/emulparams/shlelf_linux.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shelf_linux "$(tdir_shelf_linux)" ++ +eshelf_nbsd.c: $(srcdir)/emulparams/shelf_nbsd.sh \ + $(srcdir)/emulparams/shelf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shelf_nbsd "$(tdir_shelf_nbsd)" ++ +eshelf_nto.c: $(srcdir)/emulparams/shelf_nto.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shelf_nto "$(tdir_shelf_nto)" ++ +eshelf_uclinux.c: $(srcdir)/emulparams/shelf_uclinux.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shelf_uclinux "$(tdir_shelf_uclinux)" ++ +eshelf_vxworks.c: $(srcdir)/emulparams/shelf_vxworks.sh \ + $(srcdir)/emulparams/vxworks.sh $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc \ + $(srcdir)/emultempl/vxworks.em ${GEN_DEPENDS} -+ ${GENSCRIPTS} shelf_vxworks "$(tdir_shelf_vxworks)" ++ +eshl.c: $(srcdir)/emulparams/shl.sh \ + $(srcdir)/emulparams/sh.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/sh.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shl "$(tdir_shl)" ++ +eshlelf.c: $(srcdir)/emulparams/shlelf.sh \ + $(srcdir)/emulparams/shelf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shlelf "$(tdir_shlelf)" ++ +eshlelf32.c: $(srcdir)/emulparams/shlelf32.sh \ + $(BFDDIR)/libbfd.h $(INCDIR)/libiberty.h $(srcdir)/emulparams/shelf32.sh \ + $(srcdir)/emultempl/sh64elf.em $(INCDIR)/elf/sh.h $(BFDDIR)/elf-bfd.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shlelf32 "$(tdir_shlelf32)" ++ +eshlelf32_linux.c: $(srcdir)/emulparams/shlelf32_linux.sh \ + $(srcdir)/emulparams/shelf32_linux.sh $(srcdir)/emulparams/shelf32.sh \ + $(BFDDIR)/libbfd.h $(INCDIR)/libiberty.h \ + $(srcdir)/emultempl/sh64elf.em $(INCDIR)/elf/sh.h $(BFDDIR)/elf-bfd.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shlelf32_linux "$(tdir_shlelf32_linux)" ++ +eshlelf32_nbsd.c: $(srcdir)/emulparams/shlelf32_nbsd.sh \ + $(srcdir)/emulparams/shelf32_nbsd.sh $(srcdir)/emulparams/shelf32.sh \ + $(BFDDIR)/libbfd.h $(INCDIR)/libiberty.h \ + $(srcdir)/emultempl/sh64elf.em $(INCDIR)/elf/sh.h $(BFDDIR)/elf-bfd.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shlelf32_nbsd "$(tdir_shlelf32_nbsd)" ++ +eshlelf_fd.c: $(srcdir)/emulparams/shlelf_fd.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shlelf_fd "$(tdir_shlelf_fd)" ++ +eshlelf_linux.c: $(srcdir)/emulparams/shlelf_linux.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shlelf_linux "$(tdir_shlelf_linux)" ++ +eshlelf_nbsd.c: $(srcdir)/emulparams/shlelf_nbsd.sh \ + $(srcdir)/emulparams/shelf_nbsd.sh \ + $(srcdir)/emulparams/shelf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shlelf_nbsd "$(tdir_shlelf_nbsd)" ++ +eshlelf_nto.c: $(srcdir)/emulparams/shlelf_nto.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shlelf_nto "$(tdir_shlelf_nto)" ++ +eshlelf_vxworks.c: $(srcdir)/emulparams/shlelf_vxworks.sh \ + $(srcdir)/emulparams/shelf_vxworks.sh $(srcdir)/emulparams/vxworks.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc $(srcdir)/emultempl/vxworks.em \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} shlelf_vxworks "$(tdir_shlelf_vxworks)" ++ +eshlsymbian.c: $(srcdir)/emulparams/shlsymbian.sh \ + $(srcdir)/emulparams/shelf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf32sh-symbian.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shlsymbian "$(tdir_shlelf)" ++ +eshpe.c: $(srcdir)/emulparams/shpe.sh \ + $(srcdir)/emultempl/pe.em $(srcdir)/scripttempl/pe.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shpe "$(tdir_shl)" ++ +esparcaout.c: $(srcdir)/emulparams/sparcaout.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} sparcaout "$(tdir_sparcaout)" ++ +esparclinux.c: $(srcdir)/emulparams/sparclinux.sh \ + $(srcdir)/emultempl/linux.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} sparclinux "$(tdir_sparclinux)" ++ +esparcnbsd.c: $(srcdir)/emulparams/sparcnbsd.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} sparcnbsd "$(tdir_sparcnbsd)" ++ +est2000.c: $(srcdir)/emulparams/st2000.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/st2000.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} st2000 "$(tdir_st2000)" ++ +esun3.c: $(srcdir)/emulparams/sun3.sh \ + $(srcdir)/emultempl/sunos.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} sun3 "$(tdir_sun3)" ++ +esun4.c: $(srcdir)/emulparams/sun4.sh \ + $(srcdir)/emultempl/sunos.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} sun4 "$(tdir_sun4)" ++ +etic30aout.c: $(srcdir)/emulparams/tic30aout.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/tic30aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} tic30aout "$(tdir_tic30aout)" ++ +etic30coff.c: $(srcdir)/emulparams/tic30coff.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/tic30coff.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} tic30coff "$(tdir_tic30coff)" ++ +etic3xcoff.c: $(srcdir)/emulparams/tic3xcoff.sh \ + $(srcdir)/emultempl/ticoff.em $(srcdir)/scripttempl/tic4xcoff.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} tic3xcoff "$(tdir_tic4xcoff)" ++ +etic3xcoff_onchip.c: $(srcdir)/emulparams/tic3xcoff_onchip.sh \ + $(srcdir)/emultempl/ticoff.em $(srcdir)/scripttempl/tic4xcoff.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} tic3xcoff_onchip "$(tdir_tic4xcoff)" ++ +etic4xcoff.c: $(srcdir)/emulparams/tic4xcoff.sh \ + $(srcdir)/emultempl/ticoff.em $(srcdir)/scripttempl/tic4xcoff.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} tic4xcoff "$(tdir_tic4xcoff)" ++ +etic54xcoff.c: $(srcdir)/emulparams/tic54xcoff.sh \ + $(srcdir)/emultempl/ticoff.em $(srcdir)/scripttempl/tic54xcoff.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} tic54xcoff "$(tdir_tic54xcoff)" ++ +etic80coff.c: $(srcdir)/emulparams/tic80coff.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/tic80coff.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} tic80coff "$(tdir_tic80coff)" ++ +ev850.c: $(srcdir)/emulparams/v850.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/v850.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} v850 "$(tdir_v850)" ++ +ev850_rh850.c: $(srcdir)/emulparams/v850_rh850.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/v850_rh850.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} v850_rh850 "$(tdir_v850_rh850)" ++ +evanilla.c: $(srcdir)/emulparams/vanilla.sh \ + $(srcdir)/emultempl/vanilla.em $(srcdir)/scripttempl/vanilla.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} vanilla "$(tdir_vanilla)" ++ +evax.c: $(srcdir)/emulparams/vax.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} vax "$(tdir_vax)" ++ +evaxnbsd.c: $(srcdir)/emulparams/vaxnbsd.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} vaxnbsd "$(tdir_vaxnbsd)" ++ +evsta.c: $(srcdir)/emulparams/vsta.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} vsta "$(tdir_vsta)" ++ +ew65.c: $(srcdir)/emulparams/w65.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/w65.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} w65 "$(tdir_w65)" ++ +exgateelf.c: $(srcdir)/emulparams/xgateelf.sh \ + $(srcdir)/emultempl/generic.em $(ELF_DEPS) \ + $(srcdir)/scripttempl/elfxgate.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} xgateelf "$(tdir_xgate)" ++ +ez80.c: $(srcdir)/emulparams/z80.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/emultempl/z80.em \ + $(srcdir)/scripttempl/z80.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} z80 "$(tdir_z80)" ++ +ez8001.c: $(srcdir)/emulparams/z8001.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/z8000.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} z8001 "$(tdir_z8001)" ++ +ez8002.c: $(srcdir)/emulparams/z8002.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/z8000.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} z8002 "$(tdir_z8002)" + +eelf32_x86_64.c: $(srcdir)/emulparams/elf32_x86_64.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_x86_64 "$(tdir_elf32_x86_64)" ++ +eelf32_x86_64_nacl.c: $(srcdir)/emulparams/elf32_x86_64_nacl.sh \ + $(srcdir)/emulparams/elf32_x86_64.sh \ + $(srcdir)/emulparams/elf_nacl.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_x86_64_nacl "$(tdir_elf32_x86_64_nacl)" ++ +eelf64_aix.c: $(srcdir)/emulparams/elf64_aix.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64_aix "$(tdir_elf64_aix)" ++ +eelf64_ia64.c: $(srcdir)/emulparams/elf64_ia64.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/ia64elf.em \ + $(srcdir)/emultempl/needrelax.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64_ia64 "$(tdir_elf64_ia64)" ++ +eelf64_ia64_fbsd.c: $(srcdir)/emulparams/elf64_ia64_fbsd.sh \ + $(srcdir)/emulparams/elf64_ia64.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/ia64elf.em \ + $(srcdir)/emultempl/needrelax.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64_ia64_fbsd "$(tdir_elf64_ia64_fbsd)" ++ +eelf64_ia64_vms.c: $(srcdir)/emulparams/elf64_ia64_vms.sh \ + $(srcdir)/emultempl/vms.em $(srcdir)/emultempl/elf-generic.em \ + $(srcdir)/scripttempl/ia64vms.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64_ia64_vms "$(tdir_elf64_ia64_vms)" ++ +eelf64_s390.c: $(srcdir)/emulparams/elf64_s390.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64_s390 "$(tdir_elf64_s390)" ++ +eelf64_sparc.c: $(srcdir)/emulparams/elf64_sparc.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64_sparc "$(tdir_elf64_sparc)" ++ +eelf64_sparc_fbsd.c: $(srcdir)/emulparams/elf64_sparc_fbsd.sh \ + $(srcdir)/emulparams/elf64_sparc.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64_sparc_fbsd "$(tdir_elf64_sparc_fbsd)" ++ +eelf64_sparc_sol2.c: $(srcdir)/emulparams/elf64_sparc_sol2.sh \ + $(srcdir)/emulparams/elf64_sparc.sh \ + $(srcdir)/emulparams/solaris2.sh \ + $(srcdir)/emultempl/solaris2.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64_sparc_sol2 "$(tdir_elf64_sparc_sol2)" ++ +eelf64alpha.c: $(srcdir)/emulparams/elf64alpha.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/alphaelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64alpha "$(tdir_elf64alpha)" ++ +eelf64alpha_fbsd.c: $(srcdir)/emulparams/elf64alpha_fbsd.sh \ + $(srcdir)/emulparams/elf64alpha.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/alphaelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64alpha_fbsd "$(tdir_elf64alpha_fbsd)" ++ +eelf64alpha_nbsd.c: $(srcdir)/emulparams/elf64alpha_nbsd.sh \ + $(srcdir)/emulparams/elf64alpha.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/alphaelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64alpha_nbsd "$(tdir_elf64alpha_nbsd)" ++ +eelf64bmip.c: $(srcdir)/emulparams/elf64bmip.sh \ + $(srcdir)/emulparams/elf64bmip-defs.sh \ + $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/irix.em $(srcdir)/emultempl/mipself.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64bmip "$(tdir_elf64bmip)" ++ +eelf64btsmip.c: $(srcdir)/emulparams/elf64btsmip.sh \ + $(srcdir)/emulparams/elf64bmip-defs.sh \ + $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64btsmip "$(tdir_elf64btsmip)" ++ +eelf64btsmip_fbsd.c: $(srcdir)/emulparams/elf64btsmip_fbsd.sh \ + $(srcdir)/emulparams/elf64bmip-defs.sh \ + $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64btsmip_fbsd "$(tdir_elf64btsmip_fbsd)" ++ +eelf64hppa.c: $(srcdir)/emulparams/elf64hppa.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf64hppa.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64hppa "$(tdir_elf64hppa)" ++ +eelf64lppc.c: $(srcdir)/emulparams/elf64lppc.sh \ + $(srcdir)/emulparams/elf64ppc.sh $(srcdir)/emultempl/ppc64elf.em \ + ldemul-list.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64lppc "$(tdir_elf64lppc)" ++ +eelf64ltsmip.c: $(srcdir)/emulparams/elf64ltsmip.sh \ + $(srcdir)/emulparams/elf64btsmip.sh $(srcdir)/emulparams/elf64bmip-defs.sh \ + $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64ltsmip "$(tdir_elf64ltsmip)" ++ +eelf64ltsmip_fbsd.c: $(srcdir)/emulparams/elf64ltsmip_fbsd.sh \ + $(srcdir)/emulparams/elf64btsmip_fbsd.sh $(srcdir)/emulparams/elf64bmip-defs.sh \ + $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64ltsmip_fbsd "$(tdir_elf64ltsmip_fbsd)" ++ +eelf64mmix.c: $(srcdir)/emulparams/elf64mmix.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/mmix-elfnmmo.em \ + $(srcdir)/emultempl/mmixelf.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64mmix "$(tdir_elf64mmix)" ++ +eelf64ppc.c: $(srcdir)/emulparams/elf64ppc.sh $(srcdir)/emultempl/ppc64elf.em \ + ldemul-list.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64ppc "$(tdir_elf64ppc)" ++ +eelf64ppc_fbsd.c: $(srcdir)/emulparams/elf64ppc_fbsd.sh \ + $(srcdir)/emultempl/ppc64elf.em ldemul-list.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64ppc_fbsd "$(tdir_elf64ppc_fbsd)" ++ +eelf64rdos.c: $(srcdir)/emulparams/elf64rdos.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64rdos "$(tdir_elf64rdos)" ++ +eelf64tilegx.c: $(srcdir)/emulparams/elf64tilegx.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/needrelax.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64tilegx "$(tdir_tilegx)" ++ +eelf64tilegx_be.c: $(srcdir)/emulparams/elf64tilegx_be.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/needrelax.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64tilegx_be "$(tdir_tilegx_be)" ++ +eelf_l1om.c: $(srcdir)/emulparams/elf_l1om.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_l1om "$(tdir_elf_l1om)" ++ +eelf_l1om_fbsd.c: $(srcdir)/emulparams/elf_l1om_fbsd.sh \ + $(srcdir)/emulparams/elf_l1om.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_l1om_fbsd "$(tdir_elf_l1om_fbsd)" ++ +eelf_k1om.c: $(srcdir)/emulparams/elf_k1om.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_k1om "$(tdir_elf_k1om)" ++ +eelf_k1om_fbsd.c: $(srcdir)/emulparams/elf_k1om_fbsd.sh \ + $(srcdir)/emulparams/elf_k1om.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_k1om_fbsd "$(tdir_elf_k1om_fbsd)" ++ +eelf_x86_64.c: $(srcdir)/emulparams/elf_x86_64.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_x86_64 "$(tdir_elf_x86_64)" ++ +eelf_x86_64_fbsd.c: $(srcdir)/emulparams/elf_x86_64_fbsd.sh \ + $(srcdir)/emulparams/elf_x86_64.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_x86_64_fbsd "$(tdir_elf_x86_64_fbsd)" ++ +eelf_x86_64_nacl.c: $(srcdir)/emulparams/elf_x86_64_nacl.sh \ + $(srcdir)/emulparams/elf_x86_64.sh \ + $(srcdir)/emulparams/elf_nacl.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_x86_64_nacl "$(tdir_elf_x86_64_nacl)" ++ +eelf_x86_64_sol2.c: $(srcdir)/emulparams/elf_x86_64_sol2.sh \ + $(srcdir)/emulparams/elf_x86_64.sh \ + $(srcdir)/emulparams/solaris2.sh \ + $(srcdir)/emultempl/solaris2.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_x86_64_sol2 "$(tdir_elf_x86_64_sol2)" ++ +ehppa64linux.c: $(srcdir)/emulparams/hppa64linux.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} hppa64linux "$(tdir_hppa64linux)" ++ +emmo.c: $(srcdir)/emulparams/mmo.sh $(srcdir)/emultempl/mmix-elfnmmo.em \ + $(srcdir)/emultempl/generic.em $(srcdir)/emultempl/elf-generic.em \ + $(srcdir)/emultempl/mmo.em $(srcdir)/scripttempl/DWARF.sc \ + $(srcdir)/scripttempl/mmo.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} mmo "$(tdir_mmo)" ++ +eshelf64.c: $(srcdir)/emulparams/shelf64.sh $(srcdir)/emulparams/shelf32.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shelf64 "$(tdir_shelf64)" ++ +eshelf64_nbsd.c: $(srcdir)/emulparams/shelf64_nbsd.sh \ + $(srcdir)/emulparams/shelf32_nbsd.sh $(srcdir)/emulparams/shelf32.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shelf64_nbsd "$(tdir_shelf64_nbsd)" ++ +eshlelf64.c: $(srcdir)/emulparams/shlelf64.sh \ + $(srcdir)/emulparams/shelf64.sh $(srcdir)/emulparams/shelf32.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shlelf64 "$(tdir_shlelf64)" ++ +eshlelf64_nbsd.c: $(srcdir)/emulparams/shlelf64_nbsd.sh \ + $(srcdir)/emulparams/shelf64_nbsd.sh \ + $(srcdir)/emulparams/shelf32_nbsd.sh $(srcdir)/emulparams/shelf32.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shlelf64_nbsd "$(tdir_shlelf64_nbsd)" ++ + +# We need this for automake to use YLWRAP. +EXTRA_ld_new_SOURCES = deffilep.y ldlex.l @@ -2566661,8 +2580342,10 @@ index 0000000..1abb340 +EXTRA_ld_new_SOURCES += pep-dll.c pe-dll.c + +ld_new_SOURCES = ldgram.y ldlex-wrapper.c lexsup.c ldlang.c mri.c ldctor.c ldmain.c \ -+ ldwrite.c ldexp.c ldemul.c ldver.c ldmisc.c ldfile.c ldcref.c $(PLUGIN_C) -+ld_new_DEPENDENCIES = $(EMULATION_OFILES) $(EMUL_EXTRA_OFILES) $(BFDLIB) $(LIBIBERTY) $(LIBINTL_DEP) ++ ldwrite.c ldexp.c ldemul.c ldver.c ldmisc.c ldfile.c ldcref.c $(PLUGIN_C) \ ++ ldbuildid.c ++ld_new_DEPENDENCIES = $(EMULATION_OFILES) $(EMUL_EXTRA_OFILES) \ ++ $(BFDLIB) $(LIBIBERTY) $(LIBINTL_DEP) +ld_new_LDADD = $(EMULATION_OFILES) $(EMUL_EXTRA_OFILES) $(BFDLIB) $(LIBIBERTY) $(LIBINTL) + +# Dependency tracking for the generated emulation files. @@ -2566778,7 +2580461,8 @@ index 0000000..1abb340 +# We want to reconfigure if configure.host or configure.tgt changes. We +# extract version from bfd/configure.in, so we must depend on that also. +CONFIG_STATUS_DEPENDENCIES = $(srcdir)/configure.host $(srcdir)/configure.tgt \ -+ $(srcdir)/../bfd/configure.in ++ $(srcdir)/../bfd/configure.in \ ++ $(srcdir)/../bfd/development.sh + +MOSTLYCLEANFILES = $(STAGESTUFF) ld1$(EXEEXT) ld2$(EXEEXT) ld3$(EXEEXT) \ + ldemul-list.h crtbegin.@OBJEXT@ crtend.@OBJEXT@ ld.log ld.sum @@ -2566810,7 +2580494,7 @@ index 0000000..1abb340 + +install-data-local: + $(mkinstalldirs) $(DESTDIR)$(scriptdir)/ldscripts -+ for f in ldscripts/*; do \ ++ for f in ldscripts/* ; do \ + $(INSTALL_DATA) $$f $(DESTDIR)$(scriptdir)/$$f ; \ + done + @@ -2566839,10 +2580523,10 @@ index 0000000..1abb340 +endif diff --git a/ld/Makefile.in b/ld/Makefile.in new file mode 100644 -index 0000000..47a41cb +index 0000000..2582cea --- /dev/null +++ b/ld/Makefile.in -@@ -0,0 +1,3803 @@ +@@ -0,0 +1,3471 @@ +# Makefile.in generated by automake 1.11.1 from Makefile.am. +# @configure_input@ + @@ -2566861,7 +2580545,7 @@ index 0000000..47a41cb +@SET_MAKE@ + +# -+# Copyright 2012, 2013 Free Software Foundation ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -2566954,7 +2580638,7 @@ index 0000000..47a41cb + ldctor.$(OBJEXT) ldmain.$(OBJEXT) ldwrite.$(OBJEXT) \ + ldexp.$(OBJEXT) ldemul.$(OBJEXT) ldver.$(OBJEXT) \ + ldmisc.$(OBJEXT) ldfile.$(OBJEXT) ldcref.$(OBJEXT) \ -+ $(am__objects_1) ++ $(am__objects_1) ldbuildid.$(OBJEXT) +ld_new_OBJECTS = $(am_ld_new_OBJECTS) +am__DEPENDENCIES_1 = +DEFAULT_INCLUDES = -I.@am__isrc@ @@ -2567390,6 +2581074,7 @@ index 0000000..47a41cb + eelf32lppcsim.c \ + eelf32m32c.c \ + eelf32mb_linux.c \ ++ eelf32mbel_linux.c \ + eelf32mcore.c \ + eelf32mep.c \ + eelf32metag.c \ @@ -2567397,7 +2581082,8 @@ index 0000000..47a41cb + eelf32microblaze.c \ + eelf32moxie.c \ + eelf32mt.c \ -+ eelf32openrisc.c \ ++ eelf32or1k.c \ ++ eelf32or1k_linux.c \ + eelf32ppc.c \ + eelf32ppc_fbsd.c \ + eelf32ppclinux.c \ @@ -2567490,65 +2581176,7 @@ index 0000000..47a41cb + emcorepe.c \ + emn10200.c \ + emn10300.c \ -+ emsp430x110.c \ -+ emsp430x1101.c \ -+ emsp430x1111.c \ -+ emsp430x112.c \ -+ emsp430x1121.c \ -+ emsp430x1122.c \ -+ emsp430x1132.c \ -+ emsp430x122.c \ -+ emsp430x1222.c \ -+ emsp430x123.c \ -+ emsp430x1232.c \ -+ emsp430x133.c \ -+ emsp430x1331.c \ -+ emsp430x135.c \ -+ emsp430x1351.c \ -+ emsp430x147.c \ -+ emsp430x148.c \ -+ emsp430x149.c \ -+ emsp430x155.c \ -+ emsp430x156.c \ -+ emsp430x157.c \ -+ emsp430x1610.c \ -+ emsp430x1611.c \ -+ emsp430x1612.c \ -+ emsp430x167.c \ -+ emsp430x168.c \ -+ emsp430x169.c \ -+ emsp430x2101.c \ -+ emsp430x2111.c \ -+ emsp430x2121.c \ -+ emsp430x2131.c \ -+ emsp430x311.c \ -+ emsp430x312.c \ -+ emsp430x313.c \ -+ emsp430x314.c \ -+ emsp430x315.c \ -+ emsp430x323.c \ -+ emsp430x325.c \ -+ emsp430x336.c \ -+ emsp430x337.c \ -+ emsp430x412.c \ -+ emsp430x413.c \ -+ emsp430x415.c \ -+ emsp430x417.c \ -+ emsp430x435.c \ -+ emsp430x436.c \ -+ emsp430x437.c \ -+ emsp430x447.c \ -+ emsp430x448.c \ -+ emsp430x449.c \ -+ emsp430xE423.c \ -+ emsp430xE425.c \ -+ emsp430xE427.c \ -+ emsp430xG437.c \ -+ emsp430xG438.c \ -+ emsp430xG439.c \ -+ emsp430xW423.c \ -+ emsp430xW425.c \ -+ emsp430xW427.c \ ++ emsp430.c \ + emsp430X.c \ + ends32elf.c \ + ends32elf16m.c \ @@ -2567558,8 +2581186,6 @@ index 0000000..47a41cb + ends32belf_linux.c \ + enews.c \ + ens32knbsd.c \ -+ eor32.c \ -+ eor32elf.c \ + epc532macha.c \ + epdp11.c \ + epjelf.c \ @@ -2567701,12 +2581327,12 @@ index 0000000..47a41cb +CFILES = ldctor.c ldemul.c ldexp.c ldfile.c ldlang.c \ + ldmain.c ldmisc.c ldver.c ldwrite.c lexsup.c \ + mri.c ldcref.c pe-dll.c pep-dll.c ldlex-wrapper.c \ -+ $(PLUGIN_C) ++ $(PLUGIN_C) ldbuildid.c + +HFILES = ld.h ldctor.h ldemul.h ldexp.h ldfile.h \ + ldlang.h ldlex.h ldmain.h ldmisc.h ldver.h \ + ldwrite.h mri.h deffile.h pe-dll.h pep-dll.h \ -+ elf-hints-local.h $(PLUGIN_H) ++ elf-hints-local.h $(PLUGIN_H) ldbuildid.h + +GENERATED_CFILES = ldgram.c ldlex.c deffilep.c +GENERATED_HFILES = ldgram.h ldemul-list.h deffilep.h @@ -2567717,7 +2581343,8 @@ index 0000000..47a41cb +OFILES = ldgram.@OBJEXT@ ldlex-wrapper.@OBJEXT@ lexsup.@OBJEXT@ ldlang.@OBJEXT@ \ + mri.@OBJEXT@ ldctor.@OBJEXT@ ldmain.@OBJEXT@ $(PLUGIN_OBJECT) \ + ldwrite.@OBJEXT@ ldexp.@OBJEXT@ ldemul.@OBJEXT@ ldver.@OBJEXT@ ldmisc.@OBJEXT@ \ -+ ldfile.@OBJEXT@ ldcref.@OBJEXT@ ${EMULATION_OFILES} ${EMUL_EXTRA_OFILES} ++ ldfile.@OBJEXT@ ldcref.@OBJEXT@ ${EMULATION_OFILES} ${EMUL_EXTRA_OFILES} \ ++ ldbuildid.@OBJEXT@ + +STAGESTUFF = *.@OBJEXT@ ldscripts/* e*.c + @@ -2567739,9 +2581366,12 @@ index 0000000..47a41cb +EXTRA_ld_new_SOURCES = deffilep.y ldlex.l pep-dll.c pe-dll.c \ + $(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES) +ld_new_SOURCES = ldgram.y ldlex-wrapper.c lexsup.c ldlang.c mri.c ldctor.c ldmain.c \ -+ ldwrite.c ldexp.c ldemul.c ldver.c ldmisc.c ldfile.c ldcref.c $(PLUGIN_C) ++ ldwrite.c ldexp.c ldemul.c ldver.c ldmisc.c ldfile.c ldcref.c $(PLUGIN_C) \ ++ ldbuildid.c ++ ++ld_new_DEPENDENCIES = $(EMULATION_OFILES) $(EMUL_EXTRA_OFILES) \ ++ $(BFDLIB) $(LIBIBERTY) $(LIBINTL_DEP) + -+ld_new_DEPENDENCIES = $(EMULATION_OFILES) $(EMUL_EXTRA_OFILES) $(BFDLIB) $(LIBIBERTY) $(LIBINTL_DEP) +ld_new_LDADD = $(EMULATION_OFILES) $(EMUL_EXTRA_OFILES) $(BFDLIB) $(LIBIBERTY) $(LIBINTL) + +# A test program for C++ constructors and destructors. @@ -2567787,7 +2581417,8 @@ index 0000000..47a41cb +# We want to reconfigure if configure.host or configure.tgt changes. We +# extract version from bfd/configure.in, so we must depend on that also. +CONFIG_STATUS_DEPENDENCIES = $(srcdir)/configure.host $(srcdir)/configure.tgt \ -+ $(srcdir)/../bfd/configure.in ++ $(srcdir)/../bfd/configure.in \ ++ $(srcdir)/../bfd/development.sh + +MOSTLYCLEANFILES = $(STAGESTUFF) ld1$(EXEEXT) ld2$(EXEEXT) ld3$(EXEEXT) \ + ldemul-list.h crtbegin.@OBJEXT@ crtend.@OBJEXT@ ld.log ld.sum @@ -2568055,6 +2581686,7 @@ index 0000000..47a41cb +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ltsmipn32_fbsd.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32m32c.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32mb_linux.Po@am__quote@ ++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32mbel_linux.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32mcore.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32mep.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32metag.Po@am__quote@ @@ -2568063,7 +2581695,8 @@ index 0000000..47a41cb +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32mipswindiss.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32moxie.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32mt.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32openrisc.Po@am__quote@ ++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32or1k.Po@am__quote@ ++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32or1k_linux.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ppc.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ppc_fbsd.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eelf32ppclinux.Po@am__quote@ @@ -2568190,66 +2581823,8 @@ index 0000000..47a41cb +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emmo.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emn10200.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emn10300.Po@am__quote@ ++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430X.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x110.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x1101.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x1111.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x112.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x1121.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x1122.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x1132.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x122.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x1222.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x123.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x1232.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x133.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x1331.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x135.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x1351.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x147.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x148.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x149.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x155.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x156.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x157.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x1610.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x1611.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x1612.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x167.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x168.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x169.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x2101.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x2111.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x2121.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x2131.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x311.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x312.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x313.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x314.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x315.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x323.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x325.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x336.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x337.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x412.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x413.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x415.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x417.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x435.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x436.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x437.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x447.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x448.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430x449.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430xE423.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430xE425.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430xE427.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430xG437.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430xG438.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430xG439.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430xW423.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430xW425.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/emsp430xW427.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ends32belf.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ends32belf16m.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ends32belf_linux.Po@am__quote@ @@ -2568258,8 +2581833,6 @@ index 0000000..47a41cb +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ends32elf_linux.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/enews.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ens32knbsd.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eor32.Po@am__quote@ -+@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/eor32elf.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epc532macha.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epdp11.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/epjelf.Po@am__quote@ @@ -2568322,6 +2581895,7 @@ index 0000000..47a41cb +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ez80.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ez8001.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ez8002.Po@am__quote@ ++@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ldbuildid.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ldcref.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ldctor.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/ldemul.Po@am__quote@ @@ -2569030,94 +2582604,108 @@ index 0000000..47a41cb + +@TDIRS@ + ++# We can't use pattern rules as we don't want to depend on GNU ++# make, or else these rules could have been expressed in one ++# two-liner: 'e%.c:' and ' ${GENSCRIPTS} $* "$(tdir_$*)"'. ++# (The recursive variable expansion is portable.) ++ ++run-genscripts: ++ ${GENSCRIPTS} $(script_target) "$($(script_tdirname))" ++ ++.PHONY: run-genscripts ++ ++$(ALL_EMULATION_SOURCES) $(ALL_64_EMULATION_SOURCES): ++ base=`echo $@ | sed -e 's,e\(.*\).c,\1,'`; \ ++ $(MAKE) run-genscripts "script_target=$$base" "script_tdirname=tdir_$$base" ++ +eaix5ppc.c: $(srcdir)/emulparams/aix5ppc.sh \ + $(srcdir)/emultempl/aix.em $(srcdir)/scripttempl/aix.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} aix5ppc "$(tdir_aixppc)" ++ +eaix5rs6.c: $(srcdir)/emulparams/aix5rs6.sh \ + $(srcdir)/emultempl/aix.em $(srcdir)/scripttempl/aix.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} aix5rs6 "$(tdir_aixrs6)" ++ +eaixppc.c: $(srcdir)/emulparams/aixppc.sh \ + $(srcdir)/emultempl/aix.em $(srcdir)/scripttempl/aix.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} aixppc "$(tdir_aixppc)" ++ +eaixrs6.c: $(srcdir)/emulparams/aixrs6.sh \ + $(srcdir)/emultempl/aix.em $(srcdir)/scripttempl/aix.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} aixrs6 "$(tdir_aixrs6)" ++ +ealpha.c: $(srcdir)/emulparams/alpha.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/alpha.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} alpha "$(tdir_alpha)" ++ +ealphavms.c: $(srcdir)/emulparams/alphavms.sh \ + $(srcdir)/emultempl/vms.em $(srcdir)/scripttempl/alphavms.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} alphavms "$(tdir_alphavms)" ++ +earcelf.c: $(srcdir)/emulparams/arcelf.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} arcelf "$(tdir_arcelf)" ++ +earm_epoc_pe.c: $(srcdir)/emulparams/arm_epoc_pe.sh \ + $(srcdir)/emultempl/pe.em $(srcdir)/scripttempl/epocpe.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} arm_epoc_pe "$(tdir_armpe)" ++ +earm_wince_pe.c: $(srcdir)/emulparams/arm_wince_pe.sh \ + $(srcdir)/emultempl/pe.em $(srcdir)/scripttempl/pe.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} arm_wince_pe "$(tdir_armpe)" ++ +earmaoutb.c: $(srcdir)/emulparams/armaoutb.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/armaout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armaoutb "$(tdir_armaoutb)" ++ +earmaoutl.c: $(srcdir)/emulparams/armaoutl.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/armaout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armaoutl "$(tdir_armaoutl)" ++ +earmcoff.c: $(srcdir)/emulparams/armcoff.sh \ + $(srcdir)/emultempl/armcoff.em $(srcdir)/scripttempl/armcoff.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armcoff "$(tdir_armcoff)" ++ +earmelf.c: $(srcdir)/emulparams/armelf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armelf "$(tdir_armelf)" ++ +earmelf_fbsd.c: $(srcdir)/emulparams/armelf_fbsd.sh \ + $(srcdir)/emulparams/armelf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armelf_fbsd "$(tdir_armelf_fbsd)" ++ +earmelf_linux.c: $(srcdir)/emulparams/armelf_linux.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armelf_linux "$(tdir_armelf_linux)" ++ +earmelf_linux_eabi.c: $(srcdir)/emulparams/armelf_linux_eabi.sh \ + $(srcdir)/emulparams/armelf_linux.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armelf_linux_eabi "$(tdir_armelf_linux_abi)" ++ +earmelf_nacl.c: $(srcdir)/emulparams/armelf_nacl.sh \ + $(srcdir)/emulparams/armelf_linux_eabi.sh \ + $(srcdir)/emulparams/armelf_linux.sh \ + $(srcdir)/emulparams/elf_nacl.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armelf_nacl "$(tdir_armelf_nacl)" ++ +earmelf_nbsd.c: $(srcdir)/emulparams/armelf_nbsd.sh \ + $(srcdir)/emulparams/armelf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armelf_nbsd "$(tdir_armelf_nbsd)" ++ +earmelf_vxworks.c: $(srcdir)/emulparams/armelf_vxworks.sh \ + $(srcdir)/emulparams/vxworks.sh $(srcdir)/emulparams/armelf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/vxworks.em \ + $(srcdir)/emultempl/armelf.em $(srcdir)/scripttempl/elf.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} armelf_vxworks "$(tdir_armelf)" ++ +earmelfb.c: $(srcdir)/emulparams/armelfb.sh $(srcdir)/emulparams/armelf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armelfb "$(tdir_armelfb)" ++ +earmelfb_linux.c: $(srcdir)/emulparams/armelfb_linux.sh \ + $(srcdir)/emulparams/armelf_linux.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armelfb_linux "$(tdir_armelfb_linux)" ++ +earmelfb_linux_eabi.c: $(srcdir)/emulparams/armelfb_linux_eabi.sh \ + $(srcdir)/emulparams/armelf_linux_eabi.sh \ + $(srcdir)/emulparams/armelf_linux.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armelfb_linux_eabi "$(tdir_armelfb_linux_abi)" ++ +earmelfb_nacl.c: $(srcdir)/emulparams/armelfb_nacl.sh \ + $(srcdir)/emulparams/armelf_nacl.sh \ + $(srcdir)/emulparams/armelf_linux_eabi.sh \ @@ -2569125,154 +2582713,154 @@ index 0000000..47a41cb + $(srcdir)/emulparams/elf_nacl.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armelfb_nacl "$(tdir_armelfb_nacl)" ++ +earmelfb_nbsd.c: $(srcdir)/emulparams/armelfb_nbsd.sh \ + $(srcdir)/emulparams/armelf_nbsd.sh \ + $(srcdir)/emulparams/armelf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armelfb_nbsd "$(tdir_armelfb_nbsd)" ++ +earmnbsd.c: $(srcdir)/emulparams/armnbsd.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armnbsd "$(tdir_armnbsd)" ++ +earmnto.c: $(srcdir)/emulparams/armnto.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/armelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armnto "$(tdir_armnto)" ++ +earmpe.c: $(srcdir)/emulparams/armpe.sh \ + $(srcdir)/emultempl/pe.em $(srcdir)/scripttempl/pe.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} armpe "$(tdir_armpe)" ++ +earmsymbian.c: $(srcdir)/emulparams/armsymbian.sh \ + $(srcdir)/emulparams/armelf.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/armelf.em $(srcdir)/scripttempl/armbpabi.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} armsymbian "$(tdir_armelf)" ++ +eavr1.c: $(srcdir)/emulparams/avr1.sh $(srcdir)/emultempl/avrelf.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avr1 "$(tdir_avr2)" ++ +eavr2.c: $(srcdir)/emulparams/avr2.sh $(srcdir)/emultempl/avrelf.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avr2 "$(tdir_avr2)" ++ +eavr25.c: $(srcdir)/emulparams/avr25.sh $(srcdir)/emultempl/avrelf.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avr25 "$(tdir_avr2)" ++ +eavr3.c: $(srcdir)/emulparams/avr3.sh $(srcdir)/emultempl/avrelf.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avr3 "$(tdir_avr2)" ++ +eavr31.c: $(srcdir)/emulparams/avr31.sh $(srcdir)/emultempl/avrelf.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avr31 "$(tdir_avr2)" ++ +eavr35.c: $(srcdir)/emulparams/avr35.sh $(srcdir)/emultempl/avrelf.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avr35 "$(tdir_avr2)" ++ +eavr4.c: $(srcdir)/emulparams/avr4.sh $(srcdir)/emultempl/avrelf.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avr4 "$(tdir_avr2)" ++ +eavr5.c: $(srcdir)/emulparams/avr5.sh $(srcdir)/emultempl/avrelf.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avr5 "$(tdir_avr2)" ++ +eavr51.c: $(srcdir)/emulparams/avr51.sh $(srcdir)/emultempl/avrelf.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avr51 "$(tdir_avr2)" ++ +eavr6.c: $(srcdir)/emulparams/avr6.sh $(srcdir)/emultempl/avrelf.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avr6 "$(tdir_avr2)" ++ +eavrxmega1.c: $(srcdir)/emulparams/avrxmega1.sh \ + $(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avrxmega1 "$(tdir_avr2)" ++ +eavrxmega2.c: $(srcdir)/emulparams/avrxmega2.sh \ + $(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avrxmega2 "$(tdir_avr2)" ++ +eavrxmega3.c: $(srcdir)/emulparams/avrxmega3.sh \ + $(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avrxmega3 "$(tdir_avr2)" ++ +eavrxmega4.c: $(srcdir)/emulparams/avrxmega4.sh \ + $(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avrxmega4 "$(tdir_avr2)" ++ +eavrxmega5.c: $(srcdir)/emulparams/avrxmega5.sh \ + $(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avrxmega5 "$(tdir_avr2)" ++ +eavrxmega6.c: $(srcdir)/emulparams/avrxmega6.sh \ + $(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avrxmega6 "$(tdir_avr2)" ++ +eavrxmega7.c: $(srcdir)/emulparams/avrxmega7.sh \ + $(srcdir)/emultempl/avrelf.em $(ELF_DEPS) $(srcdir)/scripttempl/avr.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} avrxmega7 "$(tdir_avr2)" ++ +ecoff_i860.c: $(srcdir)/emulparams/coff_i860.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/i860coff.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} coff_i860 "$(tdir_coff_i860)" ++ +ecoff_sparc.c: $(srcdir)/emulparams/coff_sparc.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/sparccoff.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} coff_sparc "$(tdir_coff_sparc)" ++ +ecrisaout.c: $(srcdir)/emulparams/crisaout.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/crisaout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} crisaout "$(tdir_cris)" ++ +ecriself.c: $(srcdir)/emulparams/criself.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} criself "$(tdir_cris)" ++ +ecrislinux.c: $(srcdir)/emulparams/crislinux.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} crislinux "$(tdir_cris)" ++ +ed10velf.c: $(srcdir)/emulparams/d10velf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elfd10v.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} d10velf "$(tdir_d10v)" ++ +ed30v_e.c: $(srcdir)/emulparams/d30v_e.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elfd30v.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} d30v_e "$(tdir_d30v)" ++ +ed30v_o.c: $(srcdir)/emulparams/d30v_o.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elfd30v.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} d30v_o "$(tdir_d30v)" ++ +ed30velf.c: $(srcdir)/emulparams/d30velf.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elfd30v.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} d30velf "$(tdir_d30v)" ++ +edelta68.c: $(srcdir)/emulparams/delta68.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/delta68.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} delta68 "$(tdir_delta68)" ++ +eelf32_dlx.c: $(srcdir)/emulparams/elf32_dlx.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/dlx.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_dlx "$(tdir_elf32_dlx)" ++ +eelf32_i860.c: $(srcdir)/emulparams/elf32_i860.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_i860 "$(tdir_elf32_i860)" ++ +eelf32_i960.c: $(srcdir)/emulparams/elf32_i960.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_i960 "$(tdir_elf32_i960)" ++ +eelf32_sparc.c: $(srcdir)/emulparams/elf32_sparc.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_sparc "$(tdir_elf32_sparc)" ++ +eelf32_sparc_sol2.c: $(srcdir)/emulparams/elf32_sparc_sol2.sh \ + $(srcdir)/emulparams/elf32_sparc.sh \ + $(srcdir)/emulparams/solaris2.sh \ + $(srcdir)/emultempl/solaris2.em $(ELF_DEPS) \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_sparc_sol2 "$(tdir_elf32_sparc_sol2)" ++ +eelf32_sparc_vxworks.c: $(srcdir)/emulparams/elf32_sparc_vxworks.sh \ + $(srcdir)/emulparams/vxworks.sh $(srcdir)/emulparams/elf32_sparc.sh \ + $(srcdir)/emultempl/vxworks.em $(ELF_DEPS) \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_sparc_vxworks "$(tdir_elf32_sparc_vxworks)" ++ +eelf32_spu.c: $(srcdir)/emulparams/elf32_spu.sh $(srcdir)/emultempl/spuelf.em \ + $(srcdir)/emultempl/spu_ovl.@OBJEXT@_c $(srcdir)/emultempl/spu_icache.@OBJEXT@_c \ + ldemul-list.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_spu "$(tdir_elf32_spu)" ++ +$(srcdir)/emultempl/spu_ovl.@OBJEXT@_c: @MAINT@ $(srcdir)/emultempl/spu_ovl.S + if ../gas/as-new --version \ + | grep 'target.*spu' >/dev/null 2>/dev/null; then \ @@ -2569290,1259 +2582878,1023 @@ index 0000000..47a41cb +eelf32_tic6x_be.c: $(srcdir)/emulparams/elf32_tic6x_be.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc $(srcdir)/emultempl/tic6xdsbt.em \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_tic6x_be "$(tdir_elf32_tic6x_be)" ++ +eelf32_tic6x_elf_be.c: $(srcdir)/emulparams/elf32_tic6x_elf_be.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc $(srcdir)/emultempl/tic6xdsbt.em \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_tic6x_elf_be "$(tdir_elf32_tic6x_elf_be)" ++ +eelf32_tic6x_elf_le.c: $(srcdir)/emulparams/elf32_tic6x_elf_le.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc $(srcdir)/emultempl/tic6xdsbt.em \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_tic6x_elf_le "$(tdir_elf32_tic6x_elf_le)" ++ +eelf32_tic6x_le.c: $(srcdir)/emulparams/elf32_tic6x_le.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc $(srcdir)/emultempl/tic6xdsbt.em \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_tic6x_le "$(tdir_elf32_tic6x_le)" ++ +eelf32_tic6x_linux_be.c: $(srcdir)/emulparams/elf32_tic6x_linux_be.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc $(srcdir)/emultempl/tic6xdsbt.em \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_tic6x_linux_be "$(tdir_elf32_tic6x_linux_be)" ++ +eelf32_tic6x_linux_le.c: $(srcdir)/emulparams/elf32_tic6x_linux_le.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc $(srcdir)/emultempl/tic6xdsbt.em \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_tic6x_linux_le "$(tdir_elf32_tic6x_linux_le)" ++ +eelf32am33lin.c: $(srcdir)/emulparams/elf32am33lin.sh \ + $(srcdir)/emulparams/elf32am33lin.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32am33lin "$(tdir_elf32am33lin)" ++ +eelf32b4300.c: $(srcdir)/emulparams/elf32b4300.sh \ + $(srcdir)/emulparams/elf32bmip.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32b4300 "$(tdir_elf32b4300)" -+eelf32bfin.c: $(srcdir)/emulparams/bfin.sh \ ++ ++eelf32bfin.c: $(srcdir)/emulparams/elf32bfin.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/bfin.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32bfin "$(tdir_elf32bfin)" bfin ++ +eelf32bfinfd.c: $(srcdir)/emulparams/elf32bfinfd.sh \ -+ $(srcdir)/emulparams/bfin.sh \ ++ $(srcdir)/emulparams/elf32bfin.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/bfin.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32bfinfd "$(tdir_elf32bfinfd)" elf32bfinfd ++ +eelf32bmip.c: $(srcdir)/emulparams/elf32bmip.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32bmip "$(tdir_elf32bmip)" ++ +eelf32bmipn32.c: $(srcdir)/emulparams/elf32bmipn32.sh \ + $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/irix.em $(srcdir)/emultempl/mipself.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32bmipn32 "$(tdir_elf32bmipn32)" ++ +eelf32bsmip.c: $(srcdir)/emulparams/elf32bsmip.sh \ + $(srcdir)/emulparams/elf32bmip.sh $(ELF_DEPS) $(srcdir)/emultempl/irix.em \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32bsmip "$(tdir_elf32bsmip)" ++ +eelf32btsmip.c: $(srcdir)/emulparams/elf32btsmip.sh \ + $(srcdir)/emulparams/elf32bmip.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32btsmip "$(tdir_elf32btsmip)" ++ +eelf32btsmip_fbsd.c: $(srcdir)/emulparams/elf32btsmip_fbsd.sh \ + $(srcdir)/emulparams/elf32bmip.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32btsmip_fbsd "$(tdir_elf32btsmip_fbsd)" ++ +eelf32btsmipn32.c: $(srcdir)/emulparams/elf32btsmipn32.sh \ + $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32btsmipn32 "$(tdir_elf32btsmipn32)" ++ +eelf32btsmipn32_fbsd.c: $(srcdir)/emulparams/elf32btsmipn32_fbsd.sh \ + $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32btsmipn32_fbsd "$(tdir_elf32btsmipn32_fbsd)" ++ +eelf32cr16.c: $(srcdir)/emulparams/elf32cr16.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/cr16elf.em \ + $(srcdir)/scripttempl/elf32cr16.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32cr16 "$(tdir_elf32crx)" ++ +eelf32cr16c.c: $(srcdir)/emulparams/elf32cr16c.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf32cr16c.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32cr16c "$(tdir_elf32cr16c)" ++ +eelf32crx.c: $(srcdir)/emulparams/elf32crx.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/crxelf.em \ + $(srcdir)/scripttempl/elf32crx.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32crx "$(tdir_elf32crx)" ++ +eelf32ebmip.c: $(srcdir)/emulparams/elf32ebmip.sh \ + $(srcdir)/emulparams/elf32bmip.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ebmip "$(tdir_elf32ebmip)" ++ +eelf32ebmipvxworks.c: $(srcdir)/emulparams/elf32ebmipvxworks.sh \ + $(srcdir)/emulparams/elf32bmip.sh $(srcdir)/emulparams/vxworks.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/generic.em $(srcdir)/emultempl/mipself.em \ + $(srcdir)/emultempl/vxworks.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ebmipvxworks "$(tdir_elf32ebmipvxworks)" ++ +eelf32elmip.c: $(srcdir)/emulparams/elf32elmip.sh \ + $(srcdir)/emulparams/elf32lmip.sh $(srcdir)/emulparams/elf32bmip.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32elmip "$(tdir_elf32elmip)" ++ +eelf32elmipvxworks.c: $(srcdir)/emulparams/elf32elmipvxworks.sh \ + $(srcdir)/emulparams/elf32bmip.sh $(srcdir)/emulparams/vxworks.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/generic.em $(srcdir)/emultempl/mipself.em \ + $(srcdir)/emultempl/vxworks.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32elmipvxworks "$(tdir_elf32elmipvxworks)" ++ +eelf32lr5900.c: $(srcdir)/emulparams/elf32lr5900.sh \ + $(srcdir)/emulparams/elf32bmip.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32lr5900 "$(tdir_elf32lr5900)" ++ +eelf32lr5900n32.c: $(srcdir)/emulparams/elf32lr5900n32.sh \ + $(srcdir)/emulparams/elf32bmipn32-defs.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32lr5900n32 "$(tdir_elf32lr5900n32)" ++ +eelf32epiphany.c: $(srcdir)/emulparams/elf32epiphany.sh \ + $(ELF_DEPS) ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32epiphany "$(tdir_epiphany)" ++ +eelf32epiphany_4x4.c: $(srcdir)/emulparams/elf32epiphany_4x4.sh \ + $(srcdir)/emultempl/elf32.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/epiphany_4x4.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32epiphany_4x4 "$(tdir_epiphany_4x4)" ++ +eelf32fr30.c: $(srcdir)/emulparams/elf32fr30.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32fr30 "$(tdir_fr30)" ++ +eelf32frv.c: $(srcdir)/emulparams/elf32frv.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32frv "$(tdir_frv)" ++ +eelf32frvfd.c: $(srcdir)/emulparams/elf32frvfd.sh \ + $(srcdir)/emulparams/elf32frv.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32frvfd "$(tdir_frv)" ++ +eelf32i370.c: $(srcdir)/emulparams/elf32i370.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elfi370.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32i370 "$(tdir_elf32i370)" ++ +eelf32ip2k.c: $(srcdir)/emulparams/elf32ip2k.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ip2k "$(tdir_ip2k)" ++ +eelf32iq10.c: $(srcdir)/emulparams/elf32iq10.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/iq2000.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32iq10 "$(tdir_iq10)" ++ +eelf32iq2000.c: $(srcdir)/emulparams/elf32iq2000.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/iq2000.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32iq2000 "$(tdir_iq2000)" ++ +eelf32l4300.c: $(srcdir)/emulparams/elf32l4300.sh \ + $(srcdir)/emulparams/elf32b4300.sh $(srcdir)/emulparams/elf32bmip.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32l4300 "$(tdir_elf32l4300)" ++ +eelf32lm32.c: $(srcdir)/emulparams/elf32lm32.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32lm32 "$(tdir_elf32lm32)" ++ +eelf32lm32fd.c: $(srcdir)/emulparams/elf32lm32fd.sh \ + $(srcdir)/emulparams/elf32lm32.sh $(ELF_DEPS) \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32lm32fd "$(tdir_elf32lm32fd)" ++ +eelf32lmip.c: $(srcdir)/emulparams/elf32lmip.sh \ + $(srcdir)/emulparams/elf32bmip.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32lmip "$(tdir_elf32lmip)" ++ +eelf32lppc.c: $(srcdir)/emulparams/elf32lppc.sh \ + $(srcdir)/emulparams/elf32ppccommon.sh \ + $(srcdir)/emulparams/elf32ppc.sh $(srcdir)/emultempl/ppc32elf.em \ + ldemul-list.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32lppc "$(tdir_elf32lppc)" ++ +eelf32lppclinux.c: $(srcdir)/emulparams/elf32lppclinux.sh \ + $(srcdir)/emulparams/elf32lppc.sh $(srcdir)/emulparams/elf32ppc.sh \ + $(srcdir)/emulparams/elf32ppccommon.sh $(srcdir)/emultempl/ppc32elf.em \ + ldemul-list.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32lppclinux "$(tdir_elf32lppclinux)" ++ +eelf32lppcnto.c: $(srcdir)/emulparams/elf32lppcnto.sh \ + $(srcdir)/emulparams/elf32ppc.sh $(srcdir)/emulparams/elf32ppccommon.sh \ + $(srcdir)/emultempl/ppc32elf.em $(ELF_DEPS) \ + ldemul-list.h \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32lppcnto "$(tdir_elf32lppcnto)" ++ +eelf32lppcsim.c: $(srcdir)/emulparams/elf32lppcsim.sh \ + $(srcdir)/emulparams/elf32lppc.sh $(srcdir)/emulparams/elf32ppc.sh \ + $(srcdir)/emulparams/elf32ppccommon.sh $(srcdir)/emultempl/ppc32elf.em \ + ldemul-list.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32lppcsim "$(tdir_elf32lppcsim)" ++ +eelf32lsmip.c: $(srcdir)/emulparams/elf32lsmip.sh \ + $(srcdir)/emulparams/elf32lmip.sh $(srcdir)/emulparams/elf32bmip.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32lsmip "$(tdir_elf32lsmip)" ++ +eelf32ltsmip.c: $(srcdir)/emulparams/elf32ltsmip.sh \ + $(srcdir)/emulparams/elf32btsmip.sh $(srcdir)/emulparams/elf32bmip.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ltsmip "$(tdir_elf32ltsmip)" ++ +eelf32ltsmip_fbsd.c: $(srcdir)/emulparams/elf32ltsmip_fbsd.sh \ + $(srcdir)/emulparams/elf32btsmip.sh $(srcdir)/emulparams/elf32bmip.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ltsmip_fbsd "$(tdir_elf32ltsmip_fbsd)" ++ +eelf32ltsmipn32.c: $(srcdir)/emulparams/elf32ltsmipn32.sh \ + $(srcdir)/emulparams/elf32btsmipn32.sh \ + $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ltsmipn32 "$(tdir_elf32ltsmipn32)" ++ +eelf32ltsmipn32_fbsd.c: $(srcdir)/emulparams/elf32ltsmipn32_fbsd.sh \ + $(srcdir)/emulparams/elf32btsmipn32.sh \ + $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ltsmipn32_fbsd "$(tdir_elf32ltsmipn32_fbsd)" ++ +eelf32m32c.c: $(srcdir)/emulparams/elf32m32c.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/needrelax.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32m32c "$(tdir_m32c)" ++ +eelf32mbel_linux.c: $(srcdir)/emulparams/elf32mbel_linux.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32mbel_linux "$(tdir_microblazeel)" ++ +eelf32mb_linux.c: $(srcdir)/emulparams/elf32mb_linux.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32mb_linux "$(tdir_microblaze)" ++ +eelf32mcore.c: $(srcdir)/emulparams/elf32mcore.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32mcore "$(tdir_mcore)" ++ +eelf32mep.c: $(srcdir)/emulparams/elf32mep.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/mep.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32mep "$(tdir_mep)" ++ +eelf32metag.c: $(srcdir)/emulparams/elf32metag.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/metagelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32metag "$(tdir_metag)" ++ +eelf32microblazeel.c: $(srcdir)/emulparams/elf32microblazeel.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elfmicroblaze.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32microblazeel "$(tdir_microblazeel)" ++ +eelf32microblaze.c: $(srcdir)/emulparams/elf32microblaze.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elfmicroblaze.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32microblaze "$(tdir_microblaze)" ++ +eelf32mipswindiss.c: $(srcdir)/emulparams/elf32mipswindiss.sh $(ELF_DEPS) \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32mipswindiss "$(tdir_elf32mipswindiss)" ++ +eelf32moxie.c: $(srcdir)/emulparams/elf32moxie.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32moxie "$(tdir_moxie)" ++ +eelf32mt.c: $(srcdir)/emulparams/elf32mt.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32mt "$(tdir_mt)" -+eelf32openrisc.c: $(srcdir)/emulparams/elf32openrisc.sh \ -+ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32openrisc "$(tdir_openrisc)" ++ ++eelf32or1k.c: $(srcdir)/emulparams/elf32or1k.sh \ ++ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} ++ ++eelf32or1k_linux.c: $(srcdir)/emulparams/elf32or1k_linux.sh \ ++ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} ++ +eelf32ppc.c: $(srcdir)/emulparams/elf32ppc.sh \ + $(srcdir)/emulparams/elf32ppccommon.sh $(srcdir)/emultempl/ppc32elf.em \ + ldemul-list.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ppc "$(tdir_elf32ppc)" ++ +eelf32ppc_fbsd.c: $(srcdir)/emulparams/elf32ppc_fbsd.sh \ + $(srcdir)/emulparams/elf32ppc.sh $(srcdir)/emulparams/elf32ppccommon.sh \ + $(srcdir)/emultempl/ppc32elf.em $(ELF_DEPS) \ + ldemul-list.h \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ppc_fbsd "$(tdir_elf32ppc_fbsd)" ++ +eelf32ppclinux.c: $(srcdir)/emulparams/elf32ppclinux.sh \ + $(srcdir)/emulparams/elf32ppc.sh $(srcdir)/emulparams/elf32ppccommon.sh \ + $(srcdir)/emultempl/ppc32elf.em $(ELF_DEPS) \ + ldemul-list.h \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ppclinux "$(tdir_elf32ppclinux)" ++ +eelf32ppcnto.c: $(srcdir)/emulparams/elf32ppcnto.sh \ + $(srcdir)/emulparams/elf32ppc.sh $(srcdir)/emulparams/elf32ppccommon.sh \ + $(srcdir)/emultempl/ppc32elf.em $(ELF_DEPS) \ + ldemul-list.h \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ppcnto "$(tdir_elf32ppcnto)" ++ +eelf32ppcsim.c: $(srcdir)/emulparams/elf32ppcsim.sh \ + $(srcdir)/emulparams/elf32ppc.sh $(srcdir)/emulparams/elf32ppccommon.sh \ + $(srcdir)/emultempl/ppc32elf.em $(ELF_DEPS) \ + ldemul-list.h \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ppcsim "$(tdir_elf32ppcsim)" ++ +eelf32ppcvxworks.c: $(srcdir)/emulparams/elf32ppcvxworks.sh \ + $(srcdir)/emulparams/elf32ppccommon.sh $(srcdir)/emulparams/vxworks.sh \ + $(srcdir)/emultempl/vxworks.em $(ELF_DEPS) \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ppcvxworks "$(tdir_elf32ppcvxworks)" ++ +eelf32ppcwindiss.c: $(srcdir)/emulparams/elf32ppcwindiss.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32ppcwindiss "$(tdir_elf32ppcwindiss)" ++ +eelf32rl78.c: $(srcdir)/emulparams/elf32rl78.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32rl78 "$(tdir_elf32rl78)" ++ +eelf32rx.c: $(srcdir)/emulparams/elf32rx.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32rx "$(tdir_elf32rx)" ++ +eelf32tilegx.c: $(srcdir)/emulparams/elf32tilegx.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/needrelax.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32tilegx "$(tdir_tilegx)" ++ +eelf32tilegx_be.c: $(srcdir)/emulparams/elf32tilegx_be.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/needrelax.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32tilegx_be "$(tdir_tilegx_be)" ++ +eelf32tilepro.c: $(srcdir)/emulparams/elf32tilepro.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/needrelax.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32tilepro "$(tdir_tilepro)" ++ +eelf32vax.c: $(srcdir)/emulparams/elf32vax.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32vax "$(tdir_elf32vax)" ++ +eelf32xc16x.c: $(srcdir)/emulparams/elf32xc16x.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/needrelax.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32xc16x "$(tdir_xc16x)" ++ +eelf32xc16xl.c: $(srcdir)/emulparams/elf32xc16xl.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/needrelax.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32xc16xl "$(tdir_xc16xl)" ++ +eelf32xc16xs.c: $(srcdir)/emulparams/elf32xc16xs.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/needrelax.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32xc16xs "$(tdir_xc16xs)" ++ +eelf32xstormy16.c: $(srcdir)/emulparams/elf32xstormy16.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/needrelax.em \ + $(srcdir)/scripttempl/xstormy16.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32xstormy16 "$(tdir_xstormy16)" ++ +eelf32xtensa.c: $(srcdir)/emulparams/elf32xtensa.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/xtensaelf.em $(INCDIR)/xtensa-config.h \ + $(BFDDIR)/elf-bfd.h $(BFDDIR)/libbfd.h $(INCDIR)/elf/xtensa.h \ + $(srcdir)/scripttempl/elfxtensa.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32xtensa "$(tdir_elf32xtensa)" ++ +eelf_i386.c: $(srcdir)/emulparams/elf_i386.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_i386 "$(tdir_elf_i386)" ++ +eelf_i386_be.c: $(srcdir)/emulparams/elf_i386_be.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_i386_be "$(tdir_elf_i386_be)" ++ +eelf_i386_chaos.c: $(srcdir)/emulparams/elf_i386_chaos.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf_chaos.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_i386_chaos "$(tdir_elf_i386_chaos)" ++ +eelf_i386_fbsd.c: $(srcdir)/emulparams/elf_i386_fbsd.sh \ + $(srcdir)/emulparams/elf_i386.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_i386_fbsd "$(tdir_elf_i386_fbsd)" ++ +eelf_i386_ldso.c: $(srcdir)/emulparams/elf_i386_ldso.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_i386_ldso "$(tdir_elf_i386_ldso)" ++ +eelf_i386_nacl.c: $(srcdir)/emulparams/elf_i386_nacl.sh \ + $(srcdir)/emulparams/elf_i386.sh \ + $(srcdir)/emulparams/elf_nacl.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_i386_nacl "$(tdir_elf_i386_nacl)" ++ +eelf_i386_sol2.c: $(srcdir)/emulparams/elf_i386_sol2.sh \ + $(srcdir)/emulparams/solaris2.sh \ + $(srcdir)/emultempl/solaris2.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_i386_sol2 "$(tdir_elf_i386_sol2)" ++ +eelf_i386_vxworks.c: $(srcdir)/emulparams/elf_i386_vxworks.sh \ + $(srcdir)/emulparams/vxworks.sh $(srcdir)/emultempl/vxworks.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_i386_vxworks "$(tdir_elf_i386_vxworks)" ++ +eelf_s390.c: $(srcdir)/emulparams/elf_s390.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_s390 "$(tdir_elf_s390)" ++ +egld960.c: $(srcdir)/emulparams/gld960.sh \ + $(srcdir)/emultempl/gld960.em $(srcdir)/scripttempl/i960.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} gld960 "$(tdir_gld960)" ++ +egld960coff.c: $(srcdir)/emulparams/gld960coff.sh \ + $(srcdir)/emultempl/gld960c.em $(srcdir)/scripttempl/i960.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} gld960coff "$(tdir_gld960coff)" ++ +eh8300.c: $(srcdir)/emulparams/h8300.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/h8300.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300 "$(tdir_h8300)" ++ +eh8300elf.c: $(srcdir)/emulparams/h8300elf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300elf "$(tdir_h8300elf)" ++ +eh8300h.c: $(srcdir)/emulparams/h8300h.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/h8300h.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300h "$(tdir_h8300h)" ++ +eh8300helf.c: $(srcdir)/emulparams/h8300helf.sh \ + $(srcdir)/emulparams/h8300elf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300helf "$(tdir_h8300helf)" ++ +eh8300hn.c: $(srcdir)/emulparams/h8300hn.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/h8300hn.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300hn "$(tdir_h8300hn)" ++ +eh8300hnelf.c: $(srcdir)/emulparams/h8300hnelf.sh \ + $(srcdir)/emulparams/h8300elf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300hnelf "$(tdir_h8300hnelf)" ++ +eh8300s.c: $(srcdir)/emulparams/h8300s.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/h8300s.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300s "$(tdir_h8300s)" ++ +eh8300self.c: $(srcdir)/emulparams/h8300self.sh \ + $(srcdir)/emulparams/h8300elf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300self "$(tdir_h8300self)" ++ +eh8300sn.c: $(srcdir)/emulparams/h8300sn.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/h8300sn.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300sn "$(tdir_h8300sn)" ++ +eh8300snelf.c: $(srcdir)/emulparams/h8300snelf.sh \ + $(srcdir)/emulparams/h8300elf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300snelf "$(tdir_h8300snelf)" ++ +eh8300sx.c: $(srcdir)/emulparams/h8300sx.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/h8300sx.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300sx "$(tdir_h8300sx)" ++ +eh8300sxelf.c: $(srcdir)/emulparams/h8300sxelf.sh \ + $(srcdir)/emulparams/h8300elf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300sxelf "$(tdir_h8300sxelf)" ++ +eh8300sxn.c: $(srcdir)/emulparams/h8300sxn.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/h8300sxn.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300sxn "$(tdir_h8300sxn)" ++ +eh8300sxnelf.c: $(srcdir)/emulparams/h8300sxnelf.sh \ + $(srcdir)/emulparams/h8300elf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8300sxnelf "$(tdir_h8300sxnelf)" ++ +eh8500.c: $(srcdir)/emulparams/h8500.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/h8500.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8500 "$(tdir_h8500)" ++ +eh8500b.c: $(srcdir)/emulparams/h8500b.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/h8500b.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8500b "$(tdir_h8500b)" ++ +eh8500c.c: $(srcdir)/emulparams/h8500c.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/h8500c.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8500c "$(tdir_h8500c)" ++ +eh8500m.c: $(srcdir)/emulparams/h8500m.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/h8500m.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8500m "$(tdir_h8500m)" ++ +eh8500s.c: $(srcdir)/emulparams/h8500s.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/h8500s.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} h8500s "$(tdir_h8500s)" ++ +ehp300bsd.c: $(srcdir)/emulparams/hp300bsd.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} hp300bsd "$(tdir_hp300bsd)" ++ +ehp3hpux.c: $(srcdir)/emulparams/hp3hpux.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} hp3hpux "$(tdir_hp3hpux)" ++ +ehppaelf.c: $(srcdir)/emulparams/hppaelf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/hppaelf.em \ + $(srcdir)/scripttempl/hppaelf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} hppaelf "$(tdir_hppaelf)" ++ +ehppalinux.c: $(srcdir)/emulparams/hppalinux.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/hppaelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} hppalinux "$(tdir_hppalinux)" ++ +ehppanbsd.c: $(srcdir)/emulparams/hppanbsd.sh \ + $(srcdir)/emulparams/hppaelf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/hppaelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} hppanbsd "$(tdir_hppanbsd)" ++ +ehppaobsd.c: $(srcdir)/emulparams/hppaobsd.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/hppaelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} hppaobsd "$(tdir_hppaobsd)" ++ +ei386aout.c: $(srcdir)/emulparams/i386aout.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386aout "$(tdir_i386aout)" ++ +ei386beos.c: $(srcdir)/emulparams/i386beos.sh \ + $(srcdir)/emultempl/beos.em $(srcdir)/scripttempl/i386beos.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386beos "$(tdir_i386beos)" ++ +ei386bsd.c: $(srcdir)/emulparams/i386bsd.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386bsd "$(tdir_i386bsd)" ++ +ei386coff.c: $(srcdir)/emulparams/i386coff.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/i386coff.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386coff "$(tdir_i386coff)" ++ +ei386go32.c: $(srcdir)/emulparams/i386go32.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/i386go32.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386go32 "$(tdir_i386go32)" ++ +ei386linux.c: $(srcdir)/emulparams/i386linux.sh \ + $(srcdir)/emultempl/linux.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386linux "$(tdir_i386linux)" ++ +ei386lynx.c: $(srcdir)/emulparams/i386lynx.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386lynx "$(tdir_i386lynx)" ++ +ei386mach.c: $(srcdir)/emulparams/i386mach.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386mach "$(tdir_i386mach)" ++ +ei386moss.c: $(srcdir)/emulparams/i386moss.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386moss "$(tdir_i386moss)" ++ +ei386msdos.c: $(srcdir)/emulparams/i386msdos.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/i386msdos.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386msdos "$(tdir_i386msdos)" ++ +ei386nbsd.c: $(srcdir)/emulparams/i386nbsd.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386nbsd "$(tdir_i386nbsd)" ++ +ei386nto.c: $(srcdir)/emulparams/i386nto.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386nto "$(tdir_i386nto)" ++ +ei386nw.c: $(srcdir)/emulparams/i386nw.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/nw.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386nw "$(tdir_i386nw)" ++ +ei386pe.c: $(srcdir)/emulparams/i386pe.sh \ + $(srcdir)/emultempl/pe.em $(srcdir)/scripttempl/pe.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386pe "$(tdir_i386pe)" ++ +ei386pe_posix.c: $(srcdir)/emulparams/i386pe_posix.sh \ + $(srcdir)/emultempl/pe.em $(srcdir)/scripttempl/pe.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386pe_posix "$(tdir_i386pe_posix)" ++ +ei386pep.c: $(srcdir)/emulparams/i386pep.sh \ + $(srcdir)/emultempl/pep.em $(srcdir)/scripttempl/pep.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} i386pep "$(tdir_i386pe)" ++ +elnk960.c: $(srcdir)/emulparams/lnk960.sh \ + $(srcdir)/emultempl/lnk960.em $(srcdir)/scripttempl/i960.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} lnk960 "$(tdir_lnk960)" ++ +em32relf.c: $(srcdir)/emulparams/m32relf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m32relf "$(tdir_m32r)" ++ +em32relf_linux.c: $(srcdir)/emulparams/m32relf_linux.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m32relf_linux "$(tdir_m32relf_linux)" ++ +em32rlelf.c: $(srcdir)/emulparams/m32rlelf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m32rlelf "$(tdir_m32rlelf)" ++ +em32rlelf_linux.c: $(srcdir)/emulparams/m32rlelf_linux.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m32rlelf_linux "$(tdir_m32rlelf_linux)" ++ +em68hc11elf.c: $(srcdir)/emulparams/m68hc11elf.sh \ + $(srcdir)/emultempl/m68hc1xelf.em $(ELF_DEPS) \ + $(srcdir)/scripttempl/elfm68hc11.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m68hc11elf "$(tdir_m68hc11)" ++ +em68hc11elfb.c: $(srcdir)/emulparams/m68hc11elfb.sh \ + $(srcdir)/emultempl/m68hc1xelf.em $(ELF_DEPS) \ + $(srcdir)/scripttempl/elfm68hc11.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m68hc11elfb "$(tdir_m68hc11b)" ++ +em68hc12elf.c: $(srcdir)/emulparams/m68hc12elf.sh \ + $(srcdir)/emultempl/m68hc1xelf.em $(ELF_DEPS) \ + $(srcdir)/scripttempl/elfm68hc12.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m68hc12elf "$(tdir_m68hc12)" ++ +em68hc12elfb.c: $(srcdir)/emulparams/m68hc12elfb.sh \ + $(srcdir)/emultempl/m68hc1xelf.em $(ELF_DEPS) \ + $(srcdir)/scripttempl/elfm68hc12.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m68hc12elfb "$(tdir_m68hc12b)" ++ +em68k4knbsd.c: $(srcdir)/emulparams/m68k4knbsd.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m68k4knbsd "$(tdir_m68k4knbsd)" ++ +em68kaout.c: $(srcdir)/emulparams/m68kaout.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m68kaout "$(tdir_m68kaout)" ++ +em68kaux.c: $(srcdir)/emulparams/m68kaux.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/m68kaux.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m68kaux "$(tdir_m68kaux)" ++ +em68kcoff.c: $(srcdir)/emulparams/m68kcoff.sh \ + $(srcdir)/emultempl/m68kcoff.em $(srcdir)/scripttempl/m68kcoff.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m68kcoff "$(tdir_m68kcoff)" ++ +em68kelf.c: $(srcdir)/emulparams/m68kelf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/m68kelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m68kelf "$(tdir_m68kelf)" ++ +em68kelfnbsd.c: $(srcdir)/emulparams/m68kelfnbsd.sh \ + $(srcdir)/emulparams/m68kelf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/m68kelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m68kelfnbsd "$(tdir_m68kelfnbsd)" ++ +em68klinux.c: $(srcdir)/emulparams/m68klinux.sh \ + $(srcdir)/emultempl/linux.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m68klinux "$(tdir_m68klinux)" ++ +em68knbsd.c: $(srcdir)/emulparams/m68knbsd.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m68knbsd "$(tdir_m68knbsd)" ++ +em68kpsos.c: $(srcdir)/emulparams/m68kpsos.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/psos.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m68kpsos "$(tdir_m68kpsos)" ++ +em88kbcs.c: $(srcdir)/emulparams/m88kbcs.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/m88kbcs.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} m88kbcs "$(tdir_m88kbcs)" ++ +emcorepe.c: $(srcdir)/emulparams/mcorepe.sh \ + $(srcdir)/emultempl/pe.em $(srcdir)/scripttempl/pe.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} mcorepe "$(tdir_mcorepe)" ++ +emn10200.c: $(srcdir)/emulparams/mn10200.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} mn10200 "$(tdir_mn10200)" ++ +emn10300.c: $(srcdir)/emulparams/mn10300.sh \ + $(srcdir)/emulparams/mn10200.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} mn10300 "$(tdir_mn10300)" -+emsp430x110.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x110 "$(tdir_msp430x110)" msp430all -+emsp430x1101.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x1101 "$(tdir_msp430x1101)" msp430all -+emsp430x1111.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x1111 "$(tdir_msp430x1111)" msp430all -+emsp430x112.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x112 "$(tdir_msp430x112)" msp430all -+emsp430x1121.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x1121 "$(tdir_msp430x1121)" msp430all -+emsp430x1122.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x1122 "$(tdir_msp430x1122)" msp430all -+emsp430x1132.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x1132 "$(tdir_msp430x1132)" msp430all -+emsp430x122.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x122 "$(tdir_msp430x122)" msp430all -+emsp430x1222.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x1222 "$(tdir_msp430x1222)" msp430all -+emsp430x123.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x123 "$(tdir_msp430x123)" msp430all -+emsp430x1232.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x1232 "$(tdir_msp430x1232)" msp430all -+emsp430x133.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x133 "$(tdir_msp430x133)" msp430all -+emsp430x1331.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x1331 "$(tdir_msp430x1331)" msp430all -+emsp430x135.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x135 "$(tdir_msp430x135)" msp430all -+emsp430x1351.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x1351 "$(tdir_msp430x1351)" msp430all -+emsp430x147.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x147 "$(tdir_msp430x147)" msp430all -+emsp430x148.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x148 "$(tdir_msp430x148)" msp430all -+emsp430x149.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x149 "$(tdir_msp430x149)" msp430all -+emsp430x155.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x155 "$(tdir_msp430x155)" msp430all -+emsp430x156.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x156 "$(tdir_msp430x156)" msp430all -+emsp430x157.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x157 "$(tdir_msp430x157)" msp430all -+emsp430x1610.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x1610 "$(tdir_msp430x1610)" msp430all -+emsp430x1611.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x1611 "$(tdir_msp430x1611)" msp430all -+emsp430x1612.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x1612 "$(tdir_msp430x1612)" msp430all -+emsp430x167.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x167 "$(tdir_msp430x167)" msp430all -+emsp430x168.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x168 "$(tdir_msp430x168)" msp430all -+emsp430x169.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x169 "$(tdir_msp430x169)" msp430all -+emsp430x2101.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x2101 "$(tdir_msp430x2101)" msp430all -+emsp430x2111.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x2111 "$(tdir_msp430x2111)" msp430all -+emsp430x2121.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x2121 "$(tdir_msp430x2121)" msp430all -+emsp430x2131.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x2131 "$(tdir_msp430x2131)" msp430all -+emsp430x311.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x311 "$(tdir_msp430x311)" msp430all -+emsp430x312.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x312 "$(tdir_msp430x312)" msp430all -+emsp430x313.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x313 "$(tdir_msp430x313)" msp430all -+emsp430x314.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x314 "$(tdir_msp430x314)" msp430all -+emsp430x315.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x315 "$(tdir_msp430x315)" msp430all -+emsp430x323.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x323 "$(tdir_msp430x323)" msp430all -+emsp430x325.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x325 "$(tdir_msp430x325)" msp430all -+emsp430x336.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x336 "$(tdir_msp430x336)" msp430all -+emsp430x337.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430_3.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x337 "$(tdir_msp430x337)" msp430all -+emsp430x412.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x412 "$(tdir_msp430x412)" msp430all -+emsp430x413.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x413 "$(tdir_msp430x413)" msp430all -+emsp430x415.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x415 "$(tdir_msp430x415)" msp430all -+emsp430x417.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x417 "$(tdir_msp430x417)" msp430all -+emsp430x435.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x435 "$(tdir_msp430x435)" msp430all -+emsp430x436.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x436 "$(tdir_msp430x436)" msp430all -+emsp430x437.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x437 "$(tdir_msp430x437)" msp430all -+emsp430x447.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x447 "$(tdir_msp430x447)" msp430all -+emsp430x448.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x448 "$(tdir_msp430x448)" msp430all -+emsp430x449.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430x449 "$(tdir_msp430x449)" msp430all -+emsp430xE423.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430xE423 "$(tdir_msp430xE423)" msp430all -+emsp430xE425.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430xE425 "$(tdir_msp430xE425)" msp430all -+emsp430xE427.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430xE427 "$(tdir_msp430xE427)" msp430all -+emsp430xG437.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430xG437 "$(tdir_msp430xG437)" msp430all -+emsp430xG438.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430xG438 "$(tdir_msp430xG438)" msp430all -+emsp430xG439.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430xG439 "$(tdir_msp430xG439)" msp430all -+emsp430xW423.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430xW423 "$(tdir_msp430xW423)" msp430all -+emsp430xW425.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430xW425 "$(tdir_msp430xW425)" msp430all -+emsp430xW427.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430xW427 "$(tdir_msp430xW427)" msp430all -+emsp430X.c: $(srcdir)/emulparams/msp430all.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc \ -+ ${GEN_DEPENDS} -+ ${GENSCRIPTS} msp430X "$(tdir_msp430X)" msp430all ++ ++emsp430.c: $(srcdir)/emulparams/msp430.sh \ ++ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc ${GEN_DEPENDS} ++ ++emsp430X.c: $(srcdir)/emulparams/msp430.sh $(srcdir)/emulparams/msp430X.sh \ ++ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf32msp430.sc ${GEN_DEPENDS} ++ +ends32elf.c: $(srcdir)/emulparams/nds32elf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/nds32elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} nds32elf "$(tdir_nds32)" ++ +ends32elf16m.c: $(srcdir)/emulparams/nds32elf16m.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/nds32elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} nds32elf16m "$(tdir_nds32)" ++ +ends32belf.c: $(srcdir)/emulparams/nds32belf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/nds32elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} nds32belf "$(tdir_nds32belf)" ++ +ends32belf16m.c: $(srcdir)/emulparams/nds32belf16m.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/nds32elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} nds32belf16m "$(tdir_nds32belf)" ++ +ends32elf_linux.c: $(srcdir)/emulparams/nds32elf_linux.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/nds32elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} nds32elf_linux "$(tdir_nds32elf_linux)" ++ +ends32belf_linux.c: $(srcdir)/emulparams/nds32belf_linux.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/nds32elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} nds32belf_linux "$(tdir_nds32belf_linux)" ++ +enews.c: $(srcdir)/emulparams/news.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} news "$(tdir_news)" ++ +enios2elf.c: $(srcdir)/emulparams/nios2elf.sh \ -+ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} nios2elf "$(tdir_nios2elf)" ++ $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/nios2elf.em \ ++ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} ++ +enios2linux.c: $(srcdir)/emulparams/nios2linux.sh \ -+ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} nios2linux "$(tdir_nios2linux)" ++ $(srcdir)/emultempl/elf32.em $(srcdir)/emultempl/nios2elf.em \ ++ $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} ++ +ens32knbsd.c: $(srcdir)/emulparams/ns32knbsd.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/emultempl/netbsd.em \ + $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} ns32knbsd "$(tdir_ns32knbsd)" ++ +eaarch64elf.c: $(srcdir)/emulparams/aarch64elf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} aarch64elf "$(tdir_aarch64elf)" ++ +eaarch64elf32.c: $(srcdir)/emulparams/aarch64elf32.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} aarch64elf32 "$(tdir_aarch64elf32)" ++ +eaarch64elfb.c: $(srcdir)/emulparams/aarch64elfb.sh $(srcdir)/emulparams/aarch64elf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} aarch64elfb "$(tdir_aarch64elfb)" ++ +eaarch64elf32b.c: $(srcdir)/emulparams/aarch64elf32b.sh $(srcdir)/emulparams/aarch64elf32.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} aarch64elf32b "$(tdir_aarch64elf32b)" ++ +eaarch64linux.c: $(srcdir)/emulparams/aarch64linux.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} aarch64linux "$(tdir_aarch64linux)" ++ +eaarch64linuxb.c: $(srcdir)/emulparams/aarch64linuxb.sh $(srcdir)/emulparams/aarch64linux.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} aarch64linuxb "$(tdir_aarch64linuxb)" ++ +eaarch64linux32.c: $(srcdir)/emulparams/aarch64linux32.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} aarch64linux32 "$(tdir_aarch64linux32)" ++ +eaarch64linux32b.c: $(srcdir)/emulparams/aarch64linux32b.sh $(srcdir)/emulparams/aarch64linux32.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/aarch64elf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} aarch64linux32b "$(tdir_aarch64linux32b)" -+eor32.c: $(srcdir)/emulparams/or32.sh \ -+ $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/or32.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} or32 "$(tdir_or32)" -+eor32elf.c: $(srcdir)/emulparams/or32elf.sh \ -+ $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} or32elf "$(tdir_or32elf)" ++ +epc532macha.c: $(srcdir)/emulparams/pc532macha.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} pc532macha "$(tdir_pc532macha)" ++ +epdp11.c: $(srcdir)/emulparams/pdp11.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} pdp11 "$(tdir_pdp11)" ++ +epjelf.c: $(srcdir)/emulparams/pjelf.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} pjelf "$(tdir_pjelf)" ++ +epjlelf.c: $(srcdir)/emulparams/pjlelf.sh $(srcdir)/emulparams/pjelf.sh \ + $(ELF_GEN_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} pjlelf "$(tdir_pjlelf)" ++ +eppclynx.c: $(srcdir)/emulparams/ppclynx.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} ppclynx "$(tdir_ppclynx)" ++ +eppcmacos.c: $(srcdir)/emulparams/ppcmacos.sh \ + $(srcdir)/emultempl/aix.em $(srcdir)/scripttempl/aix.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} ppcmacos "$(tdir_ppcmacos)" ++ +eppcnw.c: $(srcdir)/emulparams/ppcnw.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/nw.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} ppcnw "$(tdir_ppcnw)" ++ +eppcpe.c: $(srcdir)/emulparams/ppcpe.sh \ + $(srcdir)/emultempl/pe.em $(srcdir)/scripttempl/ppcpe.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} ppcpe "$(tdir_ppcpe)" ++ +eriscix.c: $(srcdir)/emulparams/riscix.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} riscix "$(tdir_riscix)" -+escore3_elf.c: $(srcdir)/emulparams/scoreelf.sh \ ++ ++escore3_elf.c: $(srcdir)/emulparams/score3_elf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/scoreelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} score3_elf "$(tdir_score3_elf)" scoreelf -+escore7_elf.c: $(srcdir)/emulparams/scoreelf.sh \ ++ ++escore7_elf.c: $(srcdir)/emulparams/score3_elf.sh \ ++ $(srcdir)/emulparams/score7_elf.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/scoreelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} score7_elf "$(tdir_score7_elf)" scoreelf ++ +esh.c: $(srcdir)/emulparams/sh.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/sh.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} sh "$(tdir_sh)" ++ +eshelf.c: $(srcdir)/emulparams/shelf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shelf "$(tdir_shelf)" ++ +eshelf32.c: $(srcdir)/emulparams/shelf32.sh \ + $(BFDDIR)/libbfd.h $(INCDIR)/libiberty.h \ + $(srcdir)/emultempl/sh64elf.em $(INCDIR)/elf/sh.h $(BFDDIR)/elf-bfd.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shelf32 "$(tdir_shelf32)" ++ +eshelf32_linux.c: $(srcdir)/emulparams/shelf32_linux.sh \ + $(srcdir)/emulparams/shelf32.sh \ + $(BFDDIR)/libbfd.h $(INCDIR)/libiberty.h \ + $(srcdir)/emultempl/sh64elf.em $(INCDIR)/elf/sh.h $(BFDDIR)/elf-bfd.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shelf32_linux "$(tdir_shelf32_linux)" ++ +eshelf32_nbsd.c: $(srcdir)/emulparams/shelf32_nbsd.sh \ + $(srcdir)/emulparams/shelf32.sh \ + $(BFDDIR)/libbfd.h $(INCDIR)/libiberty.h \ + $(srcdir)/emultempl/sh64elf.em $(INCDIR)/elf/sh.h $(BFDDIR)/elf-bfd.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shelf32_nbsd "$(tdir_shelf32_nbsd)" ++ +eshelf_fd.c: $(srcdir)/emulparams/shelf_fd.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shelf_fd "$(tdir_shelf_fd)" ++ +eshelf_linux.c: $(srcdir)/emulparams/shelf_linux.sh \ + $(srcdir)/emulparams/shlelf_linux.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shelf_linux "$(tdir_shelf_linux)" ++ +eshelf_nbsd.c: $(srcdir)/emulparams/shelf_nbsd.sh \ + $(srcdir)/emulparams/shelf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shelf_nbsd "$(tdir_shelf_nbsd)" ++ +eshelf_nto.c: $(srcdir)/emulparams/shelf_nto.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shelf_nto "$(tdir_shelf_nto)" ++ +eshelf_uclinux.c: $(srcdir)/emulparams/shelf_uclinux.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shelf_uclinux "$(tdir_shelf_uclinux)" ++ +eshelf_vxworks.c: $(srcdir)/emulparams/shelf_vxworks.sh \ + $(srcdir)/emulparams/vxworks.sh $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc \ + $(srcdir)/emultempl/vxworks.em ${GEN_DEPENDS} -+ ${GENSCRIPTS} shelf_vxworks "$(tdir_shelf_vxworks)" ++ +eshl.c: $(srcdir)/emulparams/shl.sh \ + $(srcdir)/emulparams/sh.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/sh.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shl "$(tdir_shl)" ++ +eshlelf.c: $(srcdir)/emulparams/shlelf.sh \ + $(srcdir)/emulparams/shelf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shlelf "$(tdir_shlelf)" ++ +eshlelf32.c: $(srcdir)/emulparams/shlelf32.sh \ + $(BFDDIR)/libbfd.h $(INCDIR)/libiberty.h $(srcdir)/emulparams/shelf32.sh \ + $(srcdir)/emultempl/sh64elf.em $(INCDIR)/elf/sh.h $(BFDDIR)/elf-bfd.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shlelf32 "$(tdir_shlelf32)" ++ +eshlelf32_linux.c: $(srcdir)/emulparams/shlelf32_linux.sh \ + $(srcdir)/emulparams/shelf32_linux.sh $(srcdir)/emulparams/shelf32.sh \ + $(BFDDIR)/libbfd.h $(INCDIR)/libiberty.h \ + $(srcdir)/emultempl/sh64elf.em $(INCDIR)/elf/sh.h $(BFDDIR)/elf-bfd.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shlelf32_linux "$(tdir_shlelf32_linux)" ++ +eshlelf32_nbsd.c: $(srcdir)/emulparams/shlelf32_nbsd.sh \ + $(srcdir)/emulparams/shelf32_nbsd.sh $(srcdir)/emulparams/shelf32.sh \ + $(BFDDIR)/libbfd.h $(INCDIR)/libiberty.h \ + $(srcdir)/emultempl/sh64elf.em $(INCDIR)/elf/sh.h $(BFDDIR)/elf-bfd.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shlelf32_nbsd "$(tdir_shlelf32_nbsd)" ++ +eshlelf_fd.c: $(srcdir)/emulparams/shlelf_fd.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shlelf_fd "$(tdir_shlelf_fd)" ++ +eshlelf_linux.c: $(srcdir)/emulparams/shlelf_linux.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shlelf_linux "$(tdir_shlelf_linux)" ++ +eshlelf_nbsd.c: $(srcdir)/emulparams/shlelf_nbsd.sh \ + $(srcdir)/emulparams/shelf_nbsd.sh \ + $(srcdir)/emulparams/shelf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shlelf_nbsd "$(tdir_shlelf_nbsd)" ++ +eshlelf_nto.c: $(srcdir)/emulparams/shlelf_nto.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shlelf_nto "$(tdir_shlelf_nto)" ++ +eshlelf_vxworks.c: $(srcdir)/emulparams/shlelf_vxworks.sh \ + $(srcdir)/emulparams/shelf_vxworks.sh $(srcdir)/emulparams/vxworks.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc $(srcdir)/emultempl/vxworks.em \ + ${GEN_DEPENDS} -+ ${GENSCRIPTS} shlelf_vxworks "$(tdir_shlelf_vxworks)" ++ +eshlsymbian.c: $(srcdir)/emulparams/shlsymbian.sh \ + $(srcdir)/emulparams/shelf.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf32sh-symbian.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shlsymbian "$(tdir_shlelf)" ++ +eshpe.c: $(srcdir)/emulparams/shpe.sh \ + $(srcdir)/emultempl/pe.em $(srcdir)/scripttempl/pe.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shpe "$(tdir_shl)" ++ +esparcaout.c: $(srcdir)/emulparams/sparcaout.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} sparcaout "$(tdir_sparcaout)" ++ +esparclinux.c: $(srcdir)/emulparams/sparclinux.sh \ + $(srcdir)/emultempl/linux.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} sparclinux "$(tdir_sparclinux)" ++ +esparcnbsd.c: $(srcdir)/emulparams/sparcnbsd.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} sparcnbsd "$(tdir_sparcnbsd)" ++ +est2000.c: $(srcdir)/emulparams/st2000.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/st2000.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} st2000 "$(tdir_st2000)" ++ +esun3.c: $(srcdir)/emulparams/sun3.sh \ + $(srcdir)/emultempl/sunos.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} sun3 "$(tdir_sun3)" ++ +esun4.c: $(srcdir)/emulparams/sun4.sh \ + $(srcdir)/emultempl/sunos.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} sun4 "$(tdir_sun4)" ++ +etic30aout.c: $(srcdir)/emulparams/tic30aout.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/tic30aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} tic30aout "$(tdir_tic30aout)" ++ +etic30coff.c: $(srcdir)/emulparams/tic30coff.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/tic30coff.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} tic30coff "$(tdir_tic30coff)" ++ +etic3xcoff.c: $(srcdir)/emulparams/tic3xcoff.sh \ + $(srcdir)/emultempl/ticoff.em $(srcdir)/scripttempl/tic4xcoff.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} tic3xcoff "$(tdir_tic4xcoff)" ++ +etic3xcoff_onchip.c: $(srcdir)/emulparams/tic3xcoff_onchip.sh \ + $(srcdir)/emultempl/ticoff.em $(srcdir)/scripttempl/tic4xcoff.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} tic3xcoff_onchip "$(tdir_tic4xcoff)" ++ +etic4xcoff.c: $(srcdir)/emulparams/tic4xcoff.sh \ + $(srcdir)/emultempl/ticoff.em $(srcdir)/scripttempl/tic4xcoff.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} tic4xcoff "$(tdir_tic4xcoff)" ++ +etic54xcoff.c: $(srcdir)/emulparams/tic54xcoff.sh \ + $(srcdir)/emultempl/ticoff.em $(srcdir)/scripttempl/tic54xcoff.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} tic54xcoff "$(tdir_tic54xcoff)" ++ +etic80coff.c: $(srcdir)/emulparams/tic80coff.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/tic80coff.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} tic80coff "$(tdir_tic80coff)" ++ +ev850.c: $(srcdir)/emulparams/v850.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/v850.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} v850 "$(tdir_v850)" ++ +ev850_rh850.c: $(srcdir)/emulparams/v850_rh850.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/v850_rh850.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} v850_rh850 "$(tdir_v850_rh850)" ++ +evanilla.c: $(srcdir)/emulparams/vanilla.sh \ + $(srcdir)/emultempl/vanilla.em $(srcdir)/scripttempl/vanilla.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} vanilla "$(tdir_vanilla)" ++ +evax.c: $(srcdir)/emulparams/vax.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} vax "$(tdir_vax)" ++ +evaxnbsd.c: $(srcdir)/emulparams/vaxnbsd.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} vaxnbsd "$(tdir_vaxnbsd)" ++ +evsta.c: $(srcdir)/emulparams/vsta.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/aout.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} vsta "$(tdir_vsta)" ++ +ew65.c: $(srcdir)/emulparams/w65.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/w65.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} w65 "$(tdir_w65)" ++ +exgateelf.c: $(srcdir)/emulparams/xgateelf.sh \ + $(srcdir)/emultempl/generic.em $(ELF_DEPS) \ + $(srcdir)/scripttempl/elfxgate.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} xgateelf "$(tdir_xgate)" ++ +ez80.c: $(srcdir)/emulparams/z80.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/emultempl/z80.em \ + $(srcdir)/scripttempl/z80.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} z80 "$(tdir_z80)" ++ +ez8001.c: $(srcdir)/emulparams/z8001.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/z8000.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} z8001 "$(tdir_z8001)" ++ +ez8002.c: $(srcdir)/emulparams/z8002.sh \ + $(srcdir)/emultempl/generic.em $(srcdir)/scripttempl/z8000.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} z8002 "$(tdir_z8002)" + +eelf32_x86_64.c: $(srcdir)/emulparams/elf32_x86_64.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_x86_64 "$(tdir_elf32_x86_64)" ++ +eelf32_x86_64_nacl.c: $(srcdir)/emulparams/elf32_x86_64_nacl.sh \ + $(srcdir)/emulparams/elf32_x86_64.sh \ + $(srcdir)/emulparams/elf_nacl.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf32_x86_64_nacl "$(tdir_elf32_x86_64_nacl)" ++ +eelf64_aix.c: $(srcdir)/emulparams/elf64_aix.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64_aix "$(tdir_elf64_aix)" ++ +eelf64_ia64.c: $(srcdir)/emulparams/elf64_ia64.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/ia64elf.em \ + $(srcdir)/emultempl/needrelax.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64_ia64 "$(tdir_elf64_ia64)" ++ +eelf64_ia64_fbsd.c: $(srcdir)/emulparams/elf64_ia64_fbsd.sh \ + $(srcdir)/emulparams/elf64_ia64.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/ia64elf.em \ + $(srcdir)/emultempl/needrelax.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64_ia64_fbsd "$(tdir_elf64_ia64_fbsd)" ++ +eelf64_ia64_vms.c: $(srcdir)/emulparams/elf64_ia64_vms.sh \ + $(srcdir)/emultempl/vms.em $(srcdir)/emultempl/elf-generic.em \ + $(srcdir)/scripttempl/ia64vms.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64_ia64_vms "$(tdir_elf64_ia64_vms)" ++ +eelf64_s390.c: $(srcdir)/emulparams/elf64_s390.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64_s390 "$(tdir_elf64_s390)" ++ +eelf64_sparc.c: $(srcdir)/emulparams/elf64_sparc.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64_sparc "$(tdir_elf64_sparc)" ++ +eelf64_sparc_fbsd.c: $(srcdir)/emulparams/elf64_sparc_fbsd.sh \ + $(srcdir)/emulparams/elf64_sparc.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64_sparc_fbsd "$(tdir_elf64_sparc_fbsd)" ++ +eelf64_sparc_sol2.c: $(srcdir)/emulparams/elf64_sparc_sol2.sh \ + $(srcdir)/emulparams/elf64_sparc.sh \ + $(srcdir)/emulparams/solaris2.sh \ + $(srcdir)/emultempl/solaris2.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64_sparc_sol2 "$(tdir_elf64_sparc_sol2)" ++ +eelf64alpha.c: $(srcdir)/emulparams/elf64alpha.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/alphaelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64alpha "$(tdir_elf64alpha)" ++ +eelf64alpha_fbsd.c: $(srcdir)/emulparams/elf64alpha_fbsd.sh \ + $(srcdir)/emulparams/elf64alpha.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/alphaelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64alpha_fbsd "$(tdir_elf64alpha_fbsd)" ++ +eelf64alpha_nbsd.c: $(srcdir)/emulparams/elf64alpha_nbsd.sh \ + $(srcdir)/emulparams/elf64alpha.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/alphaelf.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64alpha_nbsd "$(tdir_elf64alpha_nbsd)" ++ +eelf64bmip.c: $(srcdir)/emulparams/elf64bmip.sh \ + $(srcdir)/emulparams/elf64bmip-defs.sh \ + $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/irix.em $(srcdir)/emultempl/mipself.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64bmip "$(tdir_elf64bmip)" ++ +eelf64btsmip.c: $(srcdir)/emulparams/elf64btsmip.sh \ + $(srcdir)/emulparams/elf64bmip-defs.sh \ + $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64btsmip "$(tdir_elf64btsmip)" ++ +eelf64btsmip_fbsd.c: $(srcdir)/emulparams/elf64btsmip_fbsd.sh \ + $(srcdir)/emulparams/elf64bmip-defs.sh \ + $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64btsmip_fbsd "$(tdir_elf64btsmip_fbsd)" ++ +eelf64hppa.c: $(srcdir)/emulparams/elf64hppa.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf64hppa.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64hppa "$(tdir_elf64hppa)" ++ +eelf64lppc.c: $(srcdir)/emulparams/elf64lppc.sh \ + $(srcdir)/emulparams/elf64ppc.sh $(srcdir)/emultempl/ppc64elf.em \ + ldemul-list.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64lppc "$(tdir_elf64lppc)" ++ +eelf64ltsmip.c: $(srcdir)/emulparams/elf64ltsmip.sh \ + $(srcdir)/emulparams/elf64btsmip.sh $(srcdir)/emulparams/elf64bmip-defs.sh \ + $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64ltsmip "$(tdir_elf64ltsmip)" ++ +eelf64ltsmip_fbsd.c: $(srcdir)/emulparams/elf64ltsmip_fbsd.sh \ + $(srcdir)/emulparams/elf64btsmip_fbsd.sh $(srcdir)/emulparams/elf64bmip-defs.sh \ + $(srcdir)/emulparams/elf32bmipn32-defs.sh $(ELF_DEPS) \ + $(srcdir)/emultempl/mipself.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64ltsmip_fbsd "$(tdir_elf64ltsmip_fbsd)" ++ +eelf64mmix.c: $(srcdir)/emulparams/elf64mmix.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/mmix-elfnmmo.em \ + $(srcdir)/emultempl/mmixelf.em $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64mmix "$(tdir_elf64mmix)" ++ +eelf64ppc.c: $(srcdir)/emulparams/elf64ppc.sh $(srcdir)/emultempl/ppc64elf.em \ + ldemul-list.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64ppc "$(tdir_elf64ppc)" ++ +eelf64ppc_fbsd.c: $(srcdir)/emulparams/elf64ppc_fbsd.sh \ + $(srcdir)/emultempl/ppc64elf.em ldemul-list.h \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64ppc_fbsd "$(tdir_elf64ppc_fbsd)" ++ +eelf64rdos.c: $(srcdir)/emulparams/elf64rdos.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64rdos "$(tdir_elf64rdos)" ++ +eelf64tilegx.c: $(srcdir)/emulparams/elf64tilegx.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/needrelax.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64tilegx "$(tdir_tilegx)" ++ +eelf64tilegx_be.c: $(srcdir)/emulparams/elf64tilegx_be.sh \ + $(ELF_DEPS) $(srcdir)/emultempl/needrelax.em \ + $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf64tilegx_be "$(tdir_tilegx_be)" ++ +eelf_l1om.c: $(srcdir)/emulparams/elf_l1om.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_l1om "$(tdir_elf_l1om)" ++ +eelf_l1om_fbsd.c: $(srcdir)/emulparams/elf_l1om_fbsd.sh \ + $(srcdir)/emulparams/elf_l1om.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_l1om_fbsd "$(tdir_elf_l1om_fbsd)" ++ +eelf_k1om.c: $(srcdir)/emulparams/elf_k1om.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_k1om "$(tdir_elf_k1om)" ++ +eelf_k1om_fbsd.c: $(srcdir)/emulparams/elf_k1om_fbsd.sh \ + $(srcdir)/emulparams/elf_k1om.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_k1om_fbsd "$(tdir_elf_k1om_fbsd)" ++ +eelf_x86_64.c: $(srcdir)/emulparams/elf_x86_64.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_x86_64 "$(tdir_elf_x86_64)" ++ +eelf_x86_64_fbsd.c: $(srcdir)/emulparams/elf_x86_64_fbsd.sh \ + $(srcdir)/emulparams/elf_x86_64.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_x86_64_fbsd "$(tdir_elf_x86_64_fbsd)" ++ +eelf_x86_64_nacl.c: $(srcdir)/emulparams/elf_x86_64_nacl.sh \ + $(srcdir)/emulparams/elf_x86_64.sh \ + $(srcdir)/emulparams/elf_nacl.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_x86_64_nacl "$(tdir_elf_x86_64_nacl)" ++ +eelf_x86_64_sol2.c: $(srcdir)/emulparams/elf_x86_64_sol2.sh \ + $(srcdir)/emulparams/elf_x86_64.sh \ + $(srcdir)/emulparams/solaris2.sh \ + $(srcdir)/emultempl/solaris2.em \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} elf_x86_64_sol2 "$(tdir_elf_x86_64_sol2)" ++ +ehppa64linux.c: $(srcdir)/emulparams/hppa64linux.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} hppa64linux "$(tdir_hppa64linux)" ++ +emmo.c: $(srcdir)/emulparams/mmo.sh $(srcdir)/emultempl/mmix-elfnmmo.em \ + $(srcdir)/emultempl/generic.em $(srcdir)/emultempl/elf-generic.em \ + $(srcdir)/emultempl/mmo.em $(srcdir)/scripttempl/DWARF.sc \ + $(srcdir)/scripttempl/mmo.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} mmo "$(tdir_mmo)" ++ +eshelf64.c: $(srcdir)/emulparams/shelf64.sh $(srcdir)/emulparams/shelf32.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shelf64 "$(tdir_shelf64)" ++ +eshelf64_nbsd.c: $(srcdir)/emulparams/shelf64_nbsd.sh \ + $(srcdir)/emulparams/shelf32_nbsd.sh $(srcdir)/emulparams/shelf32.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shelf64_nbsd "$(tdir_shelf64_nbsd)" ++ +eshlelf64.c: $(srcdir)/emulparams/shlelf64.sh \ + $(srcdir)/emulparams/shelf64.sh $(srcdir)/emulparams/shelf32.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shlelf64 "$(tdir_shlelf64)" ++ +eshlelf64_nbsd.c: $(srcdir)/emulparams/shlelf64_nbsd.sh \ + $(srcdir)/emulparams/shelf64_nbsd.sh \ + $(srcdir)/emulparams/shelf32_nbsd.sh $(srcdir)/emulparams/shelf32.sh \ + $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS} -+ ${GENSCRIPTS} shlelf64_nbsd "$(tdir_shlelf64_nbsd)" + +check-DEJAGNU: site.exp + srcroot=`cd $(srcdir) && pwd`; export srcroot; \ @@ -2570631,7 +2583983,7 @@ index 0000000..47a41cb + +install-data-local: + $(mkinstalldirs) $(DESTDIR)$(scriptdir)/ldscripts -+ for f in ldscripts/*; do \ ++ for f in ldscripts/* ; do \ + $(INSTALL_DATA) $$f $(DESTDIR)$(scriptdir)/$$f ; \ + done +diststuff: info $(EXTRA_DIST) @@ -2570648,12 +2584000,18 @@ index 0000000..47a41cb +.NOEXPORT: diff --git a/ld/NEWS b/ld/NEWS new file mode 100644 -index 0000000..c59040e +index 0000000..344f98d --- /dev/null +++ b/ld/NEWS -@@ -0,0 +1,591 @@ +@@ -0,0 +1,597 @@ +-*- text -*- + ++* Replace support for openrisc and or32 with support for or1k. ++ ++* Add support for the --build-id command line option to COFF based targets. ++ ++* x86/x86_64 pe-coff now supports the --build-id option. ++ +* Add support for the Andes NDS32. + +Changes in 2.24: @@ -2571234,7 +2584592,7 @@ index 0000000..c59040e + other utilities should work on Risc/Ultrix and Irix. + + -+Copyright (C) 2012 Free Software Foundation, Inc. ++Copyright (C) 2012-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -2571245,7 +2584603,7 @@ index 0000000..c59040e +End: diff --git a/ld/README b/ld/README new file mode 100644 -index 0000000..64fc2cb +index 0000000..71c3177 --- /dev/null +++ b/ld/README @@ -0,0 +1,73 @@ @@ -2571317,7 +2584675,7 @@ index 0000000..64fc2cb + genscripts.sh with "sh ${srcdir}..." (no parens) and make sure the + emulparams script used exports any shell variables it sets. + -+Copyright (C) 2012 Free Software Foundation, Inc. ++Copyright (C) 2012-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -2572597,10 +2585955,10 @@ index 0000000..f4a8a23 +#undef _POSIX_SOURCE diff --git a/ld/configure b/ld/configure new file mode 100755 -index 0000000..8452a13 +index 0000000..6dd7bc6 --- /dev/null +++ b/ld/configure -@@ -0,0 +1,19770 @@ +@@ -0,0 +1,19774 @@ +#! /bin/sh +# Guess values for system-dependent variables and create Makefiles. +# Generated by GNU Autoconf 2.64. @@ -2577245,6 +2590603,9 @@ index 0000000..8452a13 + + + ++# Set the 'development' global. ++. $srcdir/../bfd/development.sh ++ +GCC_WARN_CFLAGS="-W -Wall -Wstrict-prototypes -Wmissing-prototypes" +cat confdefs.h - <<_ACEOF >conftest.$ac_ext +/* end confdefs.h. */ @@ -2577279,8 +2590640,8 @@ index 0000000..8452a13 + *) ;; +esac + -+# Enable -Werror by default when using gcc -+if test "${GCC}" = yes -a -z "${ERROR_ON_WARNING}" ; then ++# Enable -Werror by default when using gcc. Turn it off for releases. ++if test "${GCC}" = yes -a -z "${ERROR_ON_WARNING}" -a "$development" = true ; then + ERROR_ON_WARNING=yes +fi + @@ -2584796,7 +2598157,7 @@ index 0000000..8452a13 + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF -+#line 12196 "configure" ++#line 12199 "configure" +#include "confdefs.h" + +#if HAVE_DLFCN_H @@ -2584902,7 +2598263,7 @@ index 0000000..8452a13 + lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 + lt_status=$lt_dlunknown + cat > conftest.$ac_ext <<_LT_EOF -+#line 12302 "configure" ++#line 12305 "configure" +#include "confdefs.h" + +#if HAVE_DLFCN_H @@ -2589547,6 +2602908,7 @@ index 0000000..8452a13 + ;; + esac + done ++ + fi +done + @@ -2592373,7 +2605735,7 @@ index 0000000..8452a13 + diff --git a/ld/configure.host b/ld/configure.host new file mode 100644 -index 0000000..57fba6c +index 0000000..042ebbc --- /dev/null +++ b/ld/configure.host @@ -0,0 +1,258 @@ @@ -2592382,7 +2605744,7 @@ index 0000000..57fba6c +# file lets us skip running autoconf when modifying host specific +# information. +# -+# Copyright 2012 Free Software Foundation ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -2592637,13 +2605999,13 @@ index 0000000..57fba6c +fi diff --git a/ld/configure.in b/ld/configure.in new file mode 100644 -index 0000000..619c151 +index 0000000..d8607e2 --- /dev/null +++ b/ld/configure.in -@@ -0,0 +1,411 @@ +@@ -0,0 +1,412 @@ +dnl Process this file with autoconf to produce a configure script +dnl -+dnl Copyright 2012 Free Software Foundation ++dnl Copyright (C) 2012-2014 Free Software Foundation, Inc. +dnl +dnl This file is free software; you can redistribute it and/or modify +dnl it under the terms of the GNU General Public License as published by @@ -2592996,6 +2606358,7 @@ index 0000000..619c151 + ;; + esac + done ++ + fi +done + @@ -2593054,13 +2606417,13 @@ index 0000000..619c151 +AC_OUTPUT diff --git a/ld/configure.tgt b/ld/configure.tgt new file mode 100644 -index 0000000..72d7090 +index 0000000..0eb743d --- /dev/null +++ b/ld/configure.tgt -@@ -0,0 +1,834 @@ +@@ -0,0 +1,833 @@ +# configure.tgt +# -+# Copyright 2013 Free Software Foundation ++# Copyright (C) 2013-2014 Free Software Foundation, Inc. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -2593086,7 +2606449,7 @@ index 0000000..72d7090 +# targ_emul name of linker emulation to use +# targ_extra_emuls additional linker emulations to provide +# targ_extra_libpath additional linker emulations using LIB_PATH -+# targ_extra_ofiles additional objects needed by the emulation ++# targ_extra_ofiles additional host-compiled objects needed by the emulation +# targ64_extra_emuls additional linker emulations to provide if +# --enable-64-bit-bfd is given or if host is 64 bit. +# targ64_extra_libpath additional linker emulations using LIB_PATH if @@ -2593373,7 +2606736,7 @@ index 0000000..72d7090 +i[3-7]86-*-pe) targ_emul=i386pe ; + targ_extra_ofiles="deffilep.o pe-dll.o" ;; +i[3-7]86-*-cygwin*) targ_emul=i386pe ; -+ targ_extra_ofiles="deffilep.o pe-dll.o" ++ targ_extra_ofiles="deffilep.o pe-dll.o" ; + test "$targ" != "$host" && LIB_PATH='${tooldir}/lib/w32api' ;; +i[3-7]86-*-mingw32*) targ_emul=i386pe ; + targ_extra_ofiles="deffilep.o pe-dll.o" ;; @@ -2593571,8 +2606934,8 @@ index 0000000..72d7090 + ;; +mt-*elf) targ_emul=elf32mt + ;; -+msp430-*-*) targ_emul=msp430x110 -+ targ_extra_emuls="msp430x112 msp430x1101 msp430x1111 msp430x1121 msp430x1122 msp430x1132 msp430x122 msp430x123 msp430x1222 msp430x1232 msp430x133 msp430x135 msp430x1331 msp430x1351 msp430x147 msp430x148 msp430x149 msp430x155 msp430x156 msp430x157 msp430x167 msp430x168 msp430x169 msp430x1610 msp430x1611 msp430x1612 msp430x2101 msp430x2111 msp430x2121 msp430x2131 msp430x311 msp430x312 msp430x313 msp430x314 msp430x315 msp430x323 msp430x325 msp430x336 msp430x337 msp430x412 msp430x413 msp430x415 msp430x417 msp430xE423 msp430xE425 msp430xE427 msp430xW423 msp430xW425 msp430xW427 msp430xG437 msp430xG438 msp430xG439 msp430x435 msp430x436 msp430x437 msp430x447 msp430x448 msp430x449 msp430X" ++msp430-*-*) targ_emul=msp430 ++ targ_extra_emuls="msp430X" + ;; +nds32*le-*-elf*) targ_emul=nds32elf + targ_extra_emuls="nds32elf16m nds32belf nds32belf16m" @@ -2593587,10 +2606950,9 @@ index 0000000..72d7090 +ns32k-pc532-mach* | ns32k-pc532-ux*) targ_emul=pc532macha ;; +ns32k-*-netbsd* | ns32k-pc532-lites*) targ_emul=ns32knbsd + ;; -+openrisc-*-*) targ_emul=elf32openrisc ;; -+or32-*-coff) targ_emul=or32 ;; -+or32-*-elf) targ_emul=or32elf ;; -+or32-*-rtems*) targ_emul=or32elf ++or1k-*-elf | or1knd-*-elf) targ_emul=elf32or1k ;; ++or1k-*-linux* | or1knd-*-linux*) targ_emul=elf32or1k_linux ;; ++or1k-*-rtems* | or1knd-*-rtems*) targ_emul=elf32or1k + ;; +pdp11-*-*) targ_emul=pdp11 + ;; @@ -2593820,7 +2607182,7 @@ index 0000000..72d7090 + ;; +xtensa*-*-*) targ_emul=elf32xtensa + ;; -+xgate-*-*) targ_emul=xgateelf ++xgate-*-*) targ_emul=xgateelf + ;; +z80-*-coff) targ_emul=z80 + ;; @@ -2593841,7 +2607203,7 @@ index 0000000..72d7090 +case "${target}" in + +*-*-dragonfly*) -+ NATIVE_LIB_DIRS='/usr/lib /usr/pkg/lib /usr/local/lib' ++ NATIVE_LIB_DIRS='/lib /usr/lib /usr/pkg/lib /usr/local/lib' + ;; + +*-*-freebsd*) @@ -2593894,13 +2607256,12 @@ index 0000000..72d7090 +esac diff --git a/ld/deffile.h b/ld/deffile.h new file mode 100644 -index 0000000..ca8c779 +index 0000000..0d400ad --- /dev/null +++ b/ld/deffile.h -@@ -0,0 +1,118 @@ +@@ -0,0 +1,117 @@ +/* deffile.h - header for .DEF file parser -+ Copyright 1998, 1999, 2000, 2002, 2003, 2005, 2006, 2007, 2009 -+ Free Software Foundation, Inc. ++ Copyright (C) 1998-2014 Free Software Foundation, Inc. + Written by DJ Delorie dj@cygnus.com + + This file is part of the GNU Binutils. @@ -2594018,14 +2607379,13 @@ index 0000000..ca8c779 +#endif /* DEFFILE_H */ diff --git a/ld/deffilep.y b/ld/deffilep.y new file mode 100644 -index 0000000..2dd21be +index 0000000..438bd5b --- /dev/null +++ b/ld/deffilep.y -@@ -0,0 +1,1493 @@ +@@ -0,0 +1,1492 @@ +%{ /* deffilep.y - parser for .def files */ + -+/* Copyright 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006, -+ 2007, 2009 Free Software Foundation, Inc. ++/* Copyright (C) 1995-2014 Free Software Foundation, Inc. + + This file is part of GNU Binutils. + @@ -2595595,14 +2608955,14 @@ index 0000000..02dd019 +#endif /* !_ELF_HINTS_H_ */ diff --git a/ld/emulparams/README b/ld/emulparams/README new file mode 100644 -index 0000000..58e3170 +index 0000000..2d67bb2 --- /dev/null +++ b/ld/emulparams/README @@ -0,0 +1,8 @@ +The files in this directory are read by genscripts.sh as shell commands. +They set parameters for the emulations. + -+Copyright (C) 2012 Free Software Foundation, Inc. ++Copyright (C) 2012-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -2595711,10 +2609071,10 @@ index 0000000..7a3ff97 +OUTPUT_FORMAT="elf64-bigaarch64" diff --git a/ld/emulparams/aarch64linux.sh b/ld/emulparams/aarch64linux.sh new file mode 100644 -index 0000000..d864296 +index 0000000..9867b33 --- /dev/null +++ b/ld/emulparams/aarch64linux.sh -@@ -0,0 +1,47 @@ +@@ -0,0 +1,49 @@ +ARCH=aarch64 +MACHINE= +NOP=0 @@ -2595762,12 +2609122,14 @@ index 0000000..d864296 + esac + ;; +esac ++ ++ELF_INTERPRETER_NAME=\"/lib/ld-linux-aarch64.so.1\" diff --git a/ld/emulparams/aarch64linux32.sh b/ld/emulparams/aarch64linux32.sh new file mode 100644 -index 0000000..573b432 +index 0000000..b84eb45 --- /dev/null +++ b/ld/emulparams/aarch64linux32.sh -@@ -0,0 +1,47 @@ +@@ -0,0 +1,49 @@ +ARCH="aarch64:ilp32" +MACHINE= +NOP=0 @@ -2595811,26 +2609173,30 @@ index 0000000..573b432 +case "$target" in + aarch64*-linux*) + case "$EMULATION_NAME" in -+ aarch64linux*) LIBPATH_SUFFIX=32 ;; ++ aarch64linux*) LIBPATH_SUFFIX=ilp32 ;; + esac + ;; +esac ++ ++ELF_INTERPRETER_NAME=\"/lib/ld-linux-aarch64_ilp32.so.1\" diff --git a/ld/emulparams/aarch64linux32b.sh b/ld/emulparams/aarch64linux32b.sh new file mode 100644 -index 0000000..f878b18 +index 0000000..e92feec --- /dev/null +++ b/ld/emulparams/aarch64linux32b.sh -@@ -0,0 +1,2 @@ +@@ -0,0 +1,3 @@ +. ${srcdir}/emulparams/aarch64linux32.sh +OUTPUT_FORMAT="elf32-bigaarch64" ++ELF_INTERPRETER_NAME=\"/lib/ld-linux-aarch64_be_ilp32.so.1\" diff --git a/ld/emulparams/aarch64linuxb.sh b/ld/emulparams/aarch64linuxb.sh new file mode 100644 -index 0000000..2bdf602 +index 0000000..7523205 --- /dev/null +++ b/ld/emulparams/aarch64linuxb.sh -@@ -0,0 +1,2 @@ +@@ -0,0 +1,3 @@ +. ${srcdir}/emulparams/aarch64linux.sh +OUTPUT_FORMAT="elf64-bigaarch64" ++ELF_INTERPRETER_NAME=\"/lib/ld-linux-aarch64_be.so.1\" diff --git a/ld/emulparams/aix5ppc.sh b/ld/emulparams/aix5ppc.sh new file mode 100644 index 0000000..ff94530 @@ -2596566,24 +2609932,6 @@ index 0000000..b84a0ba +DATA_ORIGIN=0x802000 +DATA_LENGTH=0xffa0 +EXTRA_EM_FILE=avrelf -diff --git a/ld/emulparams/bfin.sh b/ld/emulparams/bfin.sh -new file mode 100644 -index 0000000..6c0bb40 ---- /dev/null -+++ b/ld/emulparams/bfin.sh -@@ -0,0 +1,12 @@ -+SCRIPT_NAME=elf -+OUTPUT_FORMAT="elf32-bfin" -+TEXT_START_ADDR=0x0 -+MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" -+TARGET_PAGE_SIZE=0x1000 -+ARCH=bfin -+MACHINE= -+TEMPLATE_NAME=elf32 -+GENERATE_SHLIB_SCRIPT=yes -+EMBEDDED=yes -+USER_LABEL_PREFIX=_ -+EXTRA_EM_FILE=bfin diff --git a/ld/emulparams/coff_i860.sh b/ld/emulparams/coff_i860.sh new file mode 100644 index 0000000..03b6493 @@ -2596734,10 +2610082,10 @@ index 0000000..9c8ab31 +NO_SMALL_DATA=yes diff --git a/ld/emulparams/crislinux.sh b/ld/emulparams/crislinux.sh new file mode 100644 -index 0000000..47a9c51 +index 0000000..c072dba --- /dev/null +++ b/ld/emulparams/crislinux.sh -@@ -0,0 +1,40 @@ +@@ -0,0 +1,41 @@ +# This is an approximation of what we want for a real linux system (with MMU and ELF). +MACHINE= +SCRIPT_NAME=elf @@ -2596756,6 +2610104,7 @@ index 0000000..47a9c51 +TEXT_START_ADDR=0x80000 + +MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" ++COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)" + +# We don't do the hoops through DEFINED to provide [_]*start, as it +# doesn't work with --gc-sections, and the start-name is pretty fixed @@ -2597129,10 +2610478,10 @@ index 0000000..06defa0 +BIG_OUTPUT_FORMAT="elf32-tic6x-linux-be" diff --git a/ld/emulparams/elf32_x86_64.sh b/ld/emulparams/elf32_x86_64.sh new file mode 100644 -index 0000000..d34297b +index 0000000..11d17ad --- /dev/null +++ b/ld/emulparams/elf32_x86_64.sh -@@ -0,0 +1,36 @@ +@@ -0,0 +1,41 @@ +. ${srcdir}/emulparams/plt_unwind.sh +SCRIPT_NAME=elf +ELFSIZE=32 @@ -2597164,8 +2610513,13 @@ index 0000000..d34297b +case "$target" in + x86_64*-linux*|i[3-7]86-*-linux-*) + case "$EMULATION_NAME" in -+ *32*) LIBPATH_SUFFIX=x32 ;; -+ *64*) LIBPATH_SUFFIX=64 ;; ++ *32*) ++ LIBPATH_SUFFIX=x32 ++ LIBPATH_SUFFIX_SKIP=64 ++ ;; ++ *64*) ++ LIBPATH_SUFFIX=64 ++ ;; + esac + ;; +esac @@ -2597211,13 +2610565,31 @@ index 0000000..52fa295 +unset SHLIB_TEXT_START_ADDR +EXECUTABLE_SYMBOLS='_DYNAMIC_LINK = 0;' +DYNAMIC_LINK=FALSE +diff --git a/ld/emulparams/elf32bfin.sh b/ld/emulparams/elf32bfin.sh +new file mode 100644 +index 0000000..6c0bb40 +--- /dev/null ++++ b/ld/emulparams/elf32bfin.sh +@@ -0,0 +1,12 @@ ++SCRIPT_NAME=elf ++OUTPUT_FORMAT="elf32-bfin" ++TEXT_START_ADDR=0x0 ++MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" ++TARGET_PAGE_SIZE=0x1000 ++ARCH=bfin ++MACHINE= ++TEMPLATE_NAME=elf32 ++GENERATE_SHLIB_SCRIPT=yes ++EMBEDDED=yes ++USER_LABEL_PREFIX=_ ++EXTRA_EM_FILE=bfin diff --git a/ld/emulparams/elf32bfinfd.sh b/ld/emulparams/elf32bfinfd.sh new file mode 100644 -index 0000000..26f8f47 +index 0000000..4c96bc9 --- /dev/null +++ b/ld/emulparams/elf32bfinfd.sh @@ -0,0 +1,46 @@ -+. ${srcdir}/emulparams/bfin.sh ++. ${srcdir}/emulparams/elf32bfin.sh +unset STACK_ADDR +OUTPUT_FORMAT="elf32-bfinfdpic" +MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" @@ -2598493,23 +2611865,37 @@ index 0000000..04fc1ed + }" +# We do not need .stack for shared library. +test -n "$CREATE_SHLIB" && OTHER_SECTIONS="" -diff --git a/ld/emulparams/elf32openrisc.sh b/ld/emulparams/elf32openrisc.sh +diff --git a/ld/emulparams/elf32or1k.sh b/ld/emulparams/elf32or1k.sh new file mode 100644 -index 0000000..bbe9a3e +index 0000000..e8d59b8 --- /dev/null -+++ b/ld/emulparams/elf32openrisc.sh -@@ -0,0 +1,11 @@ -+MACHINE= ++++ b/ld/emulparams/elf32or1k.sh +@@ -0,0 +1,14 @@ +SCRIPT_NAME=elf -+OUTPUT_FORMAT="elf32-openrisc" -+NO_RELA_RELOCS=yes -+TEXT_START_ADDR=0x10000 -+ARCH=openrisc -+MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" -+ENTRY=_start -+EMBEDDED=yes ++MACHINE= ++TEMPLATE_NAME=elf32 ++OUTPUT_FORMAT="elf32-or1k" +NOP=0x15000000 -+ ++TEXT_START_ADDR=0x0000 ++TARGET_PAGE_SIZE=0x2000 ++MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" ++EMBEDDED=yes ++ARCH=or1k ++ELFSIZE=32 ++INITIAL_READONLY_SECTIONS=".vectors ${RELOCATING-0} : { KEEP (*(.vectors)) }" ++NO_REL_RELOCS=yes ++COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)" +diff --git a/ld/emulparams/elf32or1k_linux.sh b/ld/emulparams/elf32or1k_linux.sh +new file mode 100644 +index 0000000..a5bf129 +--- /dev/null ++++ b/ld/emulparams/elf32or1k_linux.sh +@@ -0,0 +1,5 @@ ++. ${srcdir}/emulparams/elf32or1k.sh ++unset EMBEDDED ++GENERATE_SHLIB_SCRIPT=yes ++GENERATE_PIE_SCRIPT=yes ++GENERATE_COMBRELOC_SCRIPT=yes diff --git a/ld/emulparams/elf32ppc.sh b/ld/emulparams/elf32ppc.sh new file mode 100644 index 0000000..c3da115 @@ -2598555,10 +2611941,10 @@ index 0000000..0025b61 + diff --git a/ld/emulparams/elf32ppccommon.sh b/ld/emulparams/elf32ppccommon.sh new file mode 100644 -index 0000000..049fdb9 +index 0000000..1f54ef8 --- /dev/null +++ b/ld/emulparams/elf32ppccommon.sh -@@ -0,0 +1,58 @@ +@@ -0,0 +1,56 @@ +# The PLT-agnostic parts of a generic 32-bit ELF PowerPC target. Included by: +# elf32ppc.sh elf32ppcvxworks.sh elf64ppc.sh +TEMPLATE_NAME=elf32 @@ -2598574,8 +2611960,6 @@ index 0000000..049fdb9 +MACHINE= +EXECUTABLE_SYMBOLS='PROVIDE (__stack = 0); PROVIDE (___stack = 0);' +if test -z "${CREATE_SHLIB}"; then -+ SDATA_START_SYMBOLS="PROVIDE (_SDA_BASE_ = 32768);" -+ SDATA2_START_SYMBOLS="PROVIDE (_SDA2_BASE_ = 32768);" + SBSS_START_SYMBOLS="PROVIDE (__sbss_start = .); PROVIDE (___sbss_start = .);" + SBSS_END_SYMBOLS="PROVIDE (__sbss_end = .); PROVIDE (___sbss_end = .);" +else @@ -2598651,11 +2612035,13 @@ index 0000000..c3466cf +TEXT_START_ADDR=0x10000000 diff --git a/ld/emulparams/elf32ppcvxworks.sh b/ld/emulparams/elf32ppcvxworks.sh new file mode 100644 -index 0000000..1bc3f30 +index 0000000..88c1da0 --- /dev/null +++ b/ld/emulparams/elf32ppcvxworks.sh -@@ -0,0 +1,3 @@ +@@ -0,0 +1,5 @@ +. ${srcdir}/emulparams/elf32ppccommon.sh ++. ${srcdir}/emulparams/plt_unwind.sh ++EXTRA_EM_FILE=ppc32elf +OUTPUT_FORMAT="elf32-powerpc-vxworks" +. ${srcdir}/emulparams/vxworks.sh diff --git a/ld/emulparams/elf32ppcwindiss.sh b/ld/emulparams/elf32ppcwindiss.sh @@ -2599618,10 +2613004,10 @@ index 0000000..2ea646e +ELF_INTERPRETER_NAME=\"/usr/libexec/ld-elf.so.1\" diff --git a/ld/emulparams/elf_i386.sh b/ld/emulparams/elf_i386.sh new file mode 100644 -index 0000000..add700f +index 0000000..93f1992 --- /dev/null +++ b/ld/emulparams/elf_i386.sh -@@ -0,0 +1,25 @@ +@@ -0,0 +1,28 @@ +. ${srcdir}/emulparams/plt_unwind.sh +SCRIPT_NAME=elf +OUTPUT_FORMAT="elf32-i386" @@ -2599643,7 +2613029,10 @@ index 0000000..add700f +case "$target" in + x86_64*-linux* | i[3-7]86*-linux*) + case "$EMULATION_NAME" in -+ *i386*) LIBPATH_SUFFIX=32 ;; ++ *i386*) ++ LIBPATH_SUFFIX=32 ++ LIBPATH_SUFFIX_SKIP=64 ++ ;; + esac + ;; +esac @@ -2599890,10 +2613279,10 @@ index 0000000..f2286ec +IREL_IN_PLT= diff --git a/ld/emulparams/elf_x86_64.sh b/ld/emulparams/elf_x86_64.sh new file mode 100644 -index 0000000..4842257 +index 0000000..d8cb6bf --- /dev/null +++ b/ld/emulparams/elf_x86_64.sh -@@ -0,0 +1,39 @@ +@@ -0,0 +1,41 @@ +. ${srcdir}/emulparams/plt_unwind.sh +SCRIPT_NAME=elf +ELFSIZE=64 @@ -2599912,6 +2613301,8 @@ index 0000000..4842257 +LARGE_BSS_AFTER_BSS= +SEPARATE_GOTPLT="SIZEOF (.got.plt) >= 24 ? 24 : 0" +IREL_IN_PLT= ++# Reuse TINY_READONLY_SECTION which is placed right after .plt section. ++TINY_READONLY_SECTION=".plt.bnd ${RELOCATING-0} : { *(.plt.bnd) }" + +if [ "x${host}" = "x${target}" ]; then + case " $EMULATION_LIBPATH " in @@ -2600993,18 +2614384,16 @@ index 0000000..121987c +TEMPLATE_NAME=elf32 +unset EXTRA_EM_FILE +GENERATE_SHLIB_SCRIPT=yes -diff --git a/ld/emulparams/msp430all.sh b/ld/emulparams/msp430all.sh +diff --git a/ld/emulparams/msp430.sh b/ld/emulparams/msp430.sh new file mode 100644 -index 0000000..33d975e +index 0000000..b459698 --- /dev/null -+++ b/ld/emulparams/msp430all.sh -@@ -0,0 +1,562 @@ ++++ b/ld/emulparams/msp430.sh +@@ -0,0 +1,18 @@ +#!/bin/sh + +# This called by genscripts_extra.sh + -+MSP430_NAME=${EMULATION_NAME} -+ +SCRIPT_NAME=elf32msp430 +TEMPLATE_NAME=generic +EXTRA_EM_FILE=genelf @@ -2601013,554 +2614402,26 @@ index 0000000..33d975e +MAXPAGESIZE=1 +EMBEDDED=yes + -+if [ "${MSP430_NAME}" = "msp430x110" ] ; then -+ARCH=MSP430 -+ROM_START=0xfc00 -+ROM_SIZE=0x3e0 -+RAM_START=0x0200 -+RAM_SIZE=128 -+STACK=0x280 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x1101" ] ; then -+ARCH=MSP430x11x1 -+ROM_START=0xfc00 -+ROM_SIZE=0x3e0 -+RAM_START=0x0200 -+RAM_SIZE=128 -+STACK=0x280 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x1111" ] ; then -+ARCH=MSP430x11x1 -+ROM_START=0xf800 -+ROM_SIZE=0x07e0 -+RAM_START=0x0200 -+RAM_SIZE=128 -+STACK=0x280 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x112" ] ; then -+ARCH=MSP430 -+ROM_START=0xf000 -+ROM_SIZE=0xfe0 -+RAM_START=0x0200 -+RAM_SIZE=256 -+STACK=0x300 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x1121" ] ; then -+ARCH=MSP430x11x1 -+ROM_START=0xf000 -+ROM_SIZE=0x0fe0 -+RAM_START=0x0200 -+RAM_SIZE=256 -+STACK=0x300 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x1122" ] ; then -+ARCH=MSP430x11x1 -+ROM_START=0xf000 -+ROM_SIZE=0x0fe0 -+RAM_START=0x0200 -+RAM_SIZE=256 -+STACK=0x300 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x1132" ] ; then -+ARCH=MSP430x11x1 -+ROM_START=0xe000 -+ROM_SIZE=0x1fe0 -+RAM_START=0x0200 -+RAM_SIZE=256 -+STACK=0x300 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x122" ] ; then -+ARCH=msp:12 -+ROM_START=0xf000 -+ROM_SIZE=0xfe0 -+RAM_START=0x0200 -+RAM_SIZE=256 -+STACK=0x300 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x1222" ] ; then -+ARCH=MSP430x12 -+ROM_START=0xf000 -+ROM_SIZE=0xfe0 -+RAM_START=0x0200 -+RAM_SIZE=256 -+STACK=0x300 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x123" ] ; then -+ARCH=MSP430x12 -+ROM_START=0xe000 -+ROM_SIZE=0x1fe0 -+RAM_START=0x0200 -+RAM_SIZE=256 -+STACK=0x300 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x1232" ] ; then -+ARCH=MSP430x12 -+ROM_START=0xe000 -+ROM_SIZE=0x1fe0 -+RAM_START=0x0200 -+RAM_SIZE=256 -+STACK=0x300 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x133" ] ; then -+ARCH=MSP430x13 -+ROM_START=0xe000 -+ROM_SIZE=0x1fe0 -+RAM_START=0x0200 -+RAM_SIZE=256 -+STACK=0x300 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x1331" ] ; then -+ARCH=MSP430x13 -+ROM_START=0xe000 -+ROM_SIZE=0x1fe0 -+RAM_START=0x0200 -+RAM_SIZE=256 -+STACK=0x300 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x135" ] ; then -+ARCH=MSP430x13 -+ROM_START=0xc000 -+ROM_SIZE=0x3fe0 -+RAM_START=0x0200 -+RAM_SIZE=512 -+STACK=0x400 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x1351" ] ; then -+ARCH=MSP430x13 -+ROM_START=0xc000 -+ROM_SIZE=0x3fe0 -+RAM_START=0x0200 -+RAM_SIZE=512 -+STACK=0x400 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x147" ] ; then -+ARCH=MSP430x14 ++ARCH=msp:14 +ROM_START=0x8000 +ROM_SIZE=0x7fe0 +RAM_START=0x0200 +RAM_SIZE=1K +STACK=0x600 -+fi +diff --git a/ld/emulparams/msp430X.sh b/ld/emulparams/msp430X.sh +new file mode 100644 +index 0000000..fea669b +--- /dev/null ++++ b/ld/emulparams/msp430X.sh +@@ -0,0 +1,8 @@ ++. ${srcdir}/emulparams/msp430.sh + -+if [ "${MSP430_NAME}" = "msp430x148" ] ; then -+ARCH=MSP430x14 -+ROM_START=0x4000 -+ROM_SIZE=0xbfe0 -+RAM_START=0x0200 -+RAM_SIZE=0x0800 -+STACK=0xa00 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x149" ] ; then -+ARCH=MSP430x14 -+ROM_START=0x1100 -+ROM_SIZE=0xeee0 -+RAM_START=0x0200 -+RAM_SIZE=0x0800 -+STACK=0xa00 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x155" ] ; then -+ARCH=MSP430x15 -+ROM_START=0xc000 -+ROM_SIZE=0x3fe0 -+RAM_START=0x0200 -+RAM_SIZE=512 -+STACK=0x400 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x156" ] ; then -+ARCH=MSP430x15 -+ROM_START=0xa000 -+ROM_SIZE=0x5fe0 -+RAM_START=0x0200 -+RAM_SIZE=512 -+STACK=0x400 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x157" ] ; then -+ARCH=MSP430x15 -+ROM_START=0x8000 -+ROM_SIZE=0x7fe0 -+RAM_START=0x0200 -+RAM_SIZE=1K -+STACK=0x600 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x167" ] ; then -+ARCH=MSP430X16 -+ROM_START=0x8000 -+ROM_SIZE=0x7fe0 -+RAM_START=0x0200 -+RAM_SIZE=1K -+STACK=0x600 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x168" ] ; then -+ARCH=MSP430X16 -+ROM_START=0x4000 -+ROM_SIZE=0xbfe0 -+RAM_START=0x0200 -+RAM_SIZE=0x0800 -+STACK=0xa00 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x169" ] ; then -+ARCH=MSP430X16 -+ROM_START=0x1100 -+ROM_SIZE=0xeee0 -+RAM_START=0x0200 -+RAM_SIZE=0x0800 -+STACK=0xa00 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x1610" ] ; then -+ARCH=MSP430X16 -+ROM_START=0x8000 -+ROM_SIZE=0x7fe0 -+RAM_START=0x1100 -+RAM_SIZE=0x1400 -+STACK=0x2500 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x1611" ] ; then -+ARCH=MSP430X16 -+ROM_START=0x4000 -+ROM_SIZE=0xbfe0 -+RAM_START=0x1100 -+RAM_SIZE=0x2800 -+STACK=0x3900 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x1612" ] ; then -+ARCH=MSP430X16 -+ROM_START=0x2500 -+ROM_SIZE=0xdae0 -+RAM_START=0x1100 -+RAM_SIZE=0x1400 -+STACK=0x2500 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x2101" ] ; then -+ARCH=MSP430x21 -+ROM_START=0xFC00 -+ROM_SIZE=0x03e0 -+RAM_START=0x0200 -+RAM_SIZE=128 -+STACK=0x280 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x2111" ] ; then -+ARCH=MSP430x21 -+ROM_START=0xF800 -+ROM_SIZE=0x07e0 -+RAM_START=0x0200 -+RAM_SIZE=128 -+STACK=0x280 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x2121" ] ; then -+ARCH=MSP430x21 -+ROM_START=0xf000 -+ROM_SIZE=0x0fe0 -+RAM_START=0x0200 -+RAM_SIZE=256 -+STACK=0x300 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x2131" ] ; then -+ARCH=MSP430x21 -+ROM_START=0xe000 -+ROM_SIZE=0x1fe0 -+RAM_START=0x0200 -+RAM_SIZE=256 -+STACK=0x300 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x311" ] ; then -+ARCH=MSP430x31 -+SCRIPT_NAME=elf32msp430_3 -+ROM_START=0xf800 -+ROM_SIZE=0x07e0 -+RAM_START=0x0200 -+RAM_SIZE=128 -+STACK=0x280 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x312" ] ; then -+ARCH=MSP430x31 -+SCRIPT_NAME=elf32msp430_3 -+ROM_START=0xf000 -+ROM_SIZE=0x0fe0 -+RAM_START=0x0200 -+RAM_SIZE=256 -+STACK=0x300 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x313" ] ; then -+ARCH=MSP430x31 -+SCRIPT_NAME=elf32msp430_3 -+ROM_START=0xe000 -+ROM_SIZE=0x1fe0 -+RAM_START=0x0200 -+RAM_SIZE=256 -+STACK=0x300 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x314" ] ; then -+ARCH=MSP430x31 -+SCRIPT_NAME=elf32msp430_3 -+ROM_START=0xd000 -+ROM_SIZE=0x2fe0 -+RAM_START=0x0200 -+RAM_SIZE=512 -+STACK=0x400 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x315" ] ; then -+ARCH=MSP430x31 -+SCRIPT_NAME=elf32msp430_3 -+ROM_START=0xc000 -+ROM_SIZE=0x3fe0 -+RAM_START=0x0200 -+RAM_SIZE=512 -+STACK=0x400 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x323" ] ; then -+ARCH=MSP430x32 -+SCRIPT_NAME=elf32msp430_3 -+ROM_START=0xe000 -+ROM_SIZE=0x1fe0 -+RAM_START=0x0200 -+RAM_SIZE=256 -+STACK=0x300 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x325" ] ; then -+ARCH=MSP430x32 -+SCRIPT_NAME=elf32msp430_3 -+ROM_START=0xc000 -+ROM_SIZE=0x3fe0 -+RAM_START=0x0200 -+RAM_SIZE=512 -+STACK=0x400 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x336" ] ; then -+ARCH=MSP430x33 -+SCRIPT_NAME=elf32msp430_3 -+ROM_START=0xa000 -+ROM_SIZE=0x5fe0 -+RAM_START=0x0200 -+RAM_SIZE=1024 -+STACK=0x600 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x337" ] ; then -+ARCH=MSP430x33 -+SCRIPT_NAME=elf32msp430_3 -+ROM_START=0x8000 -+ROM_SIZE=0x7fe0 -+RAM_START=0x0200 -+RAM_SIZE=1024 -+STACK=0x600 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x412" ] ; then -+ARCH=MSP430x41 -+ROM_START=0xf000 -+ROM_SIZE=0x0fe0 -+RAM_START=0x0200 -+RAM_SIZE=256 -+STACK=0x300 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x413" ] ; then -+ARCH=MSP430x41 -+ROM_START=0xe000 -+ROM_SIZE=0x1fe0 -+RAM_START=0x0200 -+RAM_SIZE=256 -+STACK=0x300 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x415" ] ; then -+ARCH=MSP430x41 -+ROM_START=0xc000 -+ROM_SIZE=0x3fe0 -+RAM_START=0x0200 -+RAM_SIZE=512 -+STACK=0x400 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x417" ] ; then -+ARCH=MSP430x41 -+ROM_START=0x8000 -+ROM_SIZE=0x7fe0 -+RAM_START=0x0200 -+RAM_SIZE=1024 -+STACK=0x600 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x435" ] ; then -+ARCH=MSP430x43 -+ROM_START=0xc000 -+ROM_SIZE=0x3fe0 -+RAM_START=0x0200 -+RAM_SIZE=512 -+STACK=0x400 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x436" ] ; then -+ARCH=MSP430x43 -+ROM_START=0xa000 -+ROM_SIZE=0x5fe0 -+RAM_START=0x0200 -+RAM_SIZE=1024 -+STACK=0x600 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x437" ] ; then -+ARCH=MSP430x43 -+ROM_START=0x8000 -+ROM_SIZE=0x7fe0 -+RAM_START=0x0200 -+RAM_SIZE=1024 -+STACK=0x600 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x447" ] ; then -+ARCH=msp:44 -+ROM_START=0x8000 -+ROM_SIZE=0x7fe0 -+RAM_START=0x0200 -+RAM_SIZE=1024 -+STACK=0x600 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x448" ] ; then -+ARCH=msp:44 -+ROM_START=0x4000 -+ROM_SIZE=0xbfe0 -+RAM_START=0x0200 -+RAM_SIZE=0x0800 -+STACK=0xa00 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430x449" ] ; then -+ARCH=msp:44 -+ROM_START=0x1100 -+ROM_SIZE=0xeee0 -+RAM_START=0x0200 -+RAM_SIZE=0x0800 -+STACK=0xa00 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430xE423" ] ; then -+ARCH=msp:42 -+ROM_START=0xe000 -+ROM_SIZE=0x1fe0 -+RAM_START=0x0200 -+RAM_SIZE=256 -+STACK=0x300 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430xE425" ] ; then -+ARCH=msp:42 -+ROM_START=0xc000 -+ROM_SIZE=0x3fe0 -+RAM_START=0x0200 -+RAM_SIZE=512 -+STACK=0x400 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430xE427" ] ; then -+ARCH=msp:42 -+ROM_START=0x8000 -+ROM_SIZE=0x7fe0 -+RAM_START=0x0200 -+RAM_SIZE=1024 -+STACK=0x600 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430xG437" ] ; then -+ARCH=MSP430x43 -+ROM_START=0x8000 -+ROM_SIZE=0x7fe0 -+RAM_START=0x0200 -+RAM_SIZE=1024 -+STACK=0x600 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430xG438" ] ; then -+ARCH=MSP430x43 -+ROM_START=0x4000 -+ROM_SIZE=0xbef0 -+RAM_START=0x0200 -+RAM_SIZE=0x0800 -+STACK=0xa00 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430xG439" ] ; then -+ARCH=MSP430x43 -+ROM_START=0x1100 -+ROM_SIZE=0xeee0 -+RAM_START=0x0200 -+RAM_SIZE=0x0800 -+STACK=0xa00 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430xW423" ] ; then -+ARCH=msp:42 -+ROM_START=0xe000 -+ROM_SIZE=0x1fe0 -+RAM_START=0x0200 -+RAM_SIZE=256 -+STACK=0x300 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430xW425" ] ; then -+ARCH=msp:42 -+ROM_START=0xc000 -+ROM_SIZE=0x3fe0 -+RAM_START=0x0200 -+RAM_SIZE=512 -+STACK=0x400 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430xW427" ] ; then -+ARCH=msp:42 -+ROM_START=0x8000 -+ROM_SIZE=0x7fe0 -+RAM_START=0x0200 -+RAM_SIZE=0x400 -+STACK=0x600 -+fi -+ -+if [ "${MSP430_NAME}" = "msp430X" ] ; then +ARCH=MSP430x43 +ROM_START=0x02000 +ROM_SIZE=0x0dfe0 +RAM_START=0x10000 +RAM_SIZE=0x30000 +STACK=0x600 -+fi diff --git a/ld/emulparams/nds32belf.sh b/ld/emulparams/nds32belf.sh new file mode 100644 index 0000000..eee48fa @@ -2601587,10 +2614448,10 @@ index 0000000..bc99e38 +OUTPUT_FORMAT="$BIG_OUTPUT_FORMAT" diff --git a/ld/emulparams/nds32elf.sh b/ld/emulparams/nds32elf.sh new file mode 100644 -index 0000000..c12048d +index 0000000..f0a7c31 --- /dev/null +++ b/ld/emulparams/nds32elf.sh -@@ -0,0 +1,19 @@ +@@ -0,0 +1,18 @@ +TEXT_START_ADDR=0x500000 +# This sets the stack to the top of simulator memory (48MB). +OTHER_END_SYMBOLS='PROVIDE (_stack = 0x3000000);' @@ -2601607,15 +2614468,14 @@ index 0000000..c12048d +EMBEDDED=yes +COMMONPAGESIZE=0x20 + -+# Instruct genscripts.sh not to compile scripts in by COMPILE_IN -+# in order to use external linker scripts files. -+EMULATION_LIBPATH= ++# Use external linker script files. ++COMPILE_IN=no diff --git a/ld/emulparams/nds32elf16m.sh b/ld/emulparams/nds32elf16m.sh new file mode 100644 -index 0000000..7d3b063 +index 0000000..deb8699 --- /dev/null +++ b/ld/emulparams/nds32elf16m.sh -@@ -0,0 +1,19 @@ +@@ -0,0 +1,18 @@ +TEXT_START_ADDR=0x300000 +# This sets the stack to the top of simulator memory (48MB). +OTHER_END_SYMBOLS='PROVIDE (_stack = 0x780000);' @@ -2601632,15 +2614492,14 @@ index 0000000..7d3b063 +EMBEDDED=yes +COMMONPAGESIZE=0x20 + -+# Instruct genscripts.sh not to compile scripts in by COMPILE_IN -+# in order to use external linker scripts files. -+EMULATION_LIBPATH= ++# Use external linker script files. ++COMPILE_IN=no diff --git a/ld/emulparams/nds32elf_linux.sh b/ld/emulparams/nds32elf_linux.sh new file mode 100644 -index 0000000..6d89f79 +index 0000000..1145c0e --- /dev/null +++ b/ld/emulparams/nds32elf_linux.sh -@@ -0,0 +1,36 @@ +@@ -0,0 +1,35 @@ +DEFAULT_TEXT_START_ADDR=0 +DEFAULT_STACK_START_ADDR=0 +MACHINE= @@ -2601674,9 +2614533,8 @@ index 0000000..6d89f79 +GENERATE_SHLIB_SCRIPT=yes +GENERATE_PIE_SCRIPT=yes + -+# Instruct genscripts.sh not to compile scripts in by COMPILE_IN -+# in order to use external linker scripts files. -+EMULATION_LIBPATH= ++# Use external linker script files. ++COMPILE_IN=no diff --git a/ld/emulparams/news.sh b/ld/emulparams/news.sh new file mode 100644 index 0000000..310ddf9 @@ -2601690,13 +2614548,13 @@ index 0000000..310ddf9 +ARCH=m68k diff --git a/ld/emulparams/nios2elf.sh b/ld/emulparams/nios2elf.sh new file mode 100644 -index 0000000..767f3de +index 0000000..7ccde97 --- /dev/null +++ b/ld/emulparams/nios2elf.sh @@ -0,0 +1,20 @@ +SCRIPT_NAME=elf +TEMPLATE_NAME=elf32 -+EXTRA_EM_FILE= ++EXTRA_EM_FILE=nios2elf +OUTPUT_FORMAT="elf32-littlenios2" +LITTLE_OUTPUT_FORMAT="elf32-littlenios2" +BIG_OUTPUT_FORMAT="elf32-bignios2" @@ -2601716,20 +2614574,20 @@ index 0000000..767f3de +GENERATE_PIE_SCRIPT=yes diff --git a/ld/emulparams/nios2linux.sh b/ld/emulparams/nios2linux.sh new file mode 100644 -index 0000000..aa409a9 +index 0000000..e654250 --- /dev/null +++ b/ld/emulparams/nios2linux.sh @@ -0,0 +1,20 @@ +SCRIPT_NAME=elf +TEMPLATE_NAME=elf32 -+EXTRA_EM_FILE= ++EXTRA_EM_FILE="nios2elf" +OUTPUT_FORMAT="elf32-littlenios2" +LITTLE_OUTPUT_FORMAT="elf32-littlenios2" +BIG_OUTPUT_FORMAT="elf32-bignios2" +TEXT_START_ADDR=0x2000 +OTHER_GOT_SYMBOLS=' -+ _gp = ALIGN(16) + 0x7ff0; -+ PROVIDE(gp = _gp); ++ HIDDEN (_gp = ALIGN(16) + 0x7ff0); ++ PROVIDE_HIDDEN (gp = _gp); +' +ARCH=nios2 +MACHINE= @@ -2601756,32 +2614614,6 @@ index 0000000..12e4b09 +ARCH=ns32k +EXECUTABLE_SYMBOLS='__DYNAMIC = 0;' +EXTRA_EM_FILE=netbsd -diff --git a/ld/emulparams/or32.sh b/ld/emulparams/or32.sh -new file mode 100644 -index 0000000..0e22e45 ---- /dev/null -+++ b/ld/emulparams/or32.sh -@@ -0,0 +1,5 @@ -+SCRIPT_NAME=or32 -+OUTPUT_FORMAT="coff-or32-big" -+TEXT_START_ADDR=0x1000000 -+TARGET_PAGE_SIZE=0x1000000 -+ARCH=or32 -diff --git a/ld/emulparams/or32elf.sh b/ld/emulparams/or32elf.sh -new file mode 100644 -index 0000000..5d85b04 ---- /dev/null -+++ b/ld/emulparams/or32elf.sh -@@ -0,0 +1,9 @@ -+SCRIPT_NAME=elf -+TEMPLATE_NAME=generic -+EXTRA_EM_FILE=genelf -+OUTPUT_FORMAT="elf32-or32" -+NO_RELA_RELOCS=yes -+TEXT_START_ADDR=0x1000000 -+TARGET_PAGE_SIZE=0x1000000 -+MAXPAGESIZE="CONSTANT (MAXPAGESIZE)" -+ARCH=or32 diff --git a/ld/emulparams/pc532macha.sh b/ld/emulparams/pc532macha.sh new file mode 100644 index 0000000..2b70618 @@ -2601940,12 +2614772,12 @@ index 0000000..e7f6d92 +TEXT_START_ADDR=0x8000 +TARGET_PAGE_SIZE=0x8000 +ARCH=arm -diff --git a/ld/emulparams/scoreelf.sh b/ld/emulparams/scoreelf.sh +diff --git a/ld/emulparams/score3_elf.sh b/ld/emulparams/score3_elf.sh new file mode 100644 -index 0000000..3a7ed31 +index 0000000..4636cd3 --- /dev/null -+++ b/ld/emulparams/scoreelf.sh -@@ -0,0 +1,41 @@ ++++ b/ld/emulparams/score3_elf.sh +@@ -0,0 +1,33 @@ +MACHINE= +SCRIPT_NAME=elf +TEMPLATE_NAME=elf32 @@ -2601974,19 +2614806,19 @@ index 0000000..3a7ed31 +# This sets the stack to the top of the simulator memory (2^19 bytes). +STACK_ADDR=0x8000000 + -+SCORE_NAME=${EMULATION_NAME} -+if [ "${SCORE_NAME}" = "score3_elf" ] ; then +ARCH=score3 -+fi -+ -+if [ "${SCORE_NAME}" = "score7_elf" ] ; then -+ARCH=score7 -+fi -+ +MACHINE= +ENTRY=_start +EMBEDDED=yes +GENERATE_SHLIB_SCRIPT=yes +diff --git a/ld/emulparams/score7_elf.sh b/ld/emulparams/score7_elf.sh +new file mode 100644 +index 0000000..9b7ce9b +--- /dev/null ++++ b/ld/emulparams/score7_elf.sh +@@ -0,0 +1,2 @@ ++. ${srcdir}/emulparams/score3_elf.sh ++ARCH=score7 diff --git a/ld/emulparams/sh.sh b/ld/emulparams/sh.sh new file mode 100644 index 0000000..52d1443 @@ -2602934,7 +2615766,7 @@ index 0000000..299b5f5 +ARCH=z8002 diff --git a/ld/emultempl/README b/ld/emultempl/README new file mode 100644 -index 0000000..c3c7472 +index 0000000..f81ce08 --- /dev/null +++ b/ld/emultempl/README @@ -0,0 +1,9 @@ @@ -2602942,19 +2615774,19 @@ index 0000000..c3c7472 +setting some variables to substitute in, to produce +C source files that contain jump tables for each emulation. + -+Copyright (C) 2012 Free Software Foundation, Inc. ++Copyright (C) 2012-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright +notice and this notice are preserved. diff --git a/ld/emultempl/aarch64elf.em b/ld/emultempl/aarch64elf.em new file mode 100644 -index 0000000..b3279bf +index 0000000..6134855 --- /dev/null +++ b/ld/emultempl/aarch64elf.em -@@ -0,0 +1,416 @@ +@@ -0,0 +1,414 @@ +# This shell script emits a C file. -*- C -*- -+# Copyright 2009-2012 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# Contributed by ARM Ltd. +# +# This file is part of the GNU Binutils. @@ -2603114,7 +2615946,6 @@ index 0000000..b3279bf + asection *stub_sec; + flagword flags; + asection *output_section; -+ const char *secname; + lang_output_section_statement_type *os; + struct hook_stub_info info; + @@ -2603128,8 +2615959,7 @@ index 0000000..b3279bf + bfd_set_section_alignment (stub_file->the_bfd, stub_sec, 3); + + output_section = input_section->output_section; -+ secname = bfd_get_section_name (output_section->owner, output_section); -+ os = lang_output_section_find (secname); ++ os = lang_output_section_get (output_section); + + info.input_section = input_section; + lang_list_init (&info.add); @@ -2603371,10 +2616201,10 @@ index 0000000..b3279bf +LDEMUL_FINISH=gld${EMULATION_NAME}_finish diff --git a/ld/emultempl/aix.em b/ld/emultempl/aix.em new file mode 100644 -index 0000000..aa72ce6 +index 0000000..56985cf --- /dev/null +++ b/ld/emultempl/aix.em -@@ -0,0 +1,1552 @@ +@@ -0,0 +1,1559 @@ +# This shell script emits a C file. -*- C -*- +# It does some substitutions. +if [ -z "$MACHINE" ]; then @@ -2603386,7 +2616216,7 @@ index 0000000..aa72ce6 +/* This file is is generated by a shell script. DO NOT EDIT! */ + +/* AIX emulation code for ${EMULATION_NAME} -+ Copyright 1991-2013 Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + Written by Steve Chamberlain + AIX support by Ian Lance Taylor + AIX 64 bit support by Tom Rix @@ -2604231,7 +2617061,7 @@ index 0000000..aa72ce6 + /* Remove this section from the list of the output section. + This assumes we know what the script looks like. */ + is = NULL; -+ os = lang_output_section_find (sec->output_section->name); ++ os = lang_output_section_get (sec->output_section); + if (os == NULL) + einfo ("%P%F: can't find output section %s\n", + sec->output_section->name); @@ -2604776,7 +2617606,7 @@ index 0000000..aa72ce6 +gld${EMULATION_NAME}_get_script (int *isfile) +EOF + -+if test -n "$COMPILE_IN" ++if test x"$COMPILE_IN" = xyes +then +# Scripts compiled in. + @@ -2604886,7 +2617716,13 @@ index 0000000..aa72ce6 + if (!entry->flags.maybe_archive) + return FALSE; + -+ path = concat (search->name, "/lib", entry->filename, arch, ".a", NULL); ++ if (entry->flags.full_name_provided) ++ path = concat (search->name, "/", entry->filename, ++ (const char *) NULL); ++ else ++ path = concat (search->name, "/lib", entry->filename, arch, ".a", ++ (const char *) NULL); ++ + if (!ldfile_try_open_bfd (path, entry)) + { + free (path); @@ -2604924,18 +2617760,18 @@ index 0000000..aa72ce6 + NULL, /* list_options */ + NULL, /* recognized_file */ + NULL, /* find potential_libraries */ -+ NULL /* new_vers_pattern */ ++ NULL, /* new_vers_pattern */ ++ NULL /* extra_map_file_text */ +}; +EOF diff --git a/ld/emultempl/alphaelf.em b/ld/emultempl/alphaelf.em new file mode 100644 -index 0000000..21064ad +index 0000000..a36fc7d --- /dev/null +++ b/ld/emultempl/alphaelf.em @@ -0,0 +1,148 @@ +# This shell script emits a C file. -*- C -*- -+# Copyright 2003, 2004, 2005, 2007, 2008, 2009 -+# Free Software Foundation, Inc. ++# Copyright (C) 2003-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2605008,6 +2617844,7 @@ index 0000000..21064ad +static void +alpha_after_parse (void) +{ ++ link_info.relax_pass = 2; + if (limit_32bit && !link_info.shared && !link_info.relocatable) + lang_section_start (".interp", + exp_binop ('+', @@ -2605083,7 +2617920,7 @@ index 0000000..21064ad +LDEMUL_FINISH=alpha_finish diff --git a/ld/emultempl/armcoff.em b/ld/emultempl/armcoff.em new file mode 100644 -index 0000000..20bff14 +index 0000000..de10a6c --- /dev/null +++ b/ld/emultempl/armcoff.em @@ -0,0 +1,285 @@ @@ -2605093,8 +2617930,7 @@ index 0000000..20bff14 +/* This file is is generated by a shell script. DO NOT EDIT! */ + +/* emulate the original gld for the given ${EMULATION_NAME} -+ Copyright 1991, 1993, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, -+ 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + Written by Steve Chamberlain steve@cygnus.com + + This file is part of the GNU Binutils. @@ -2605294,7 +2618130,7 @@ index 0000000..20bff14 +gld${EMULATION_NAME}_get_script (int *isfile) +EOF + -+if test -n "$COMPILE_IN" ++if test x"$COMPILE_IN" = xyes +then +# Scripts compiled in. + @@ -2605369,17 +2618205,18 @@ index 0000000..20bff14 + gld${EMULATION_NAME}_list_options, + NULL, /* recognized file */ + NULL, /* find_potential_libraries */ -+ NULL /* new_vers_pattern */ ++ NULL, /* new_vers_pattern */ ++ NULL /* extra_map_file_text */ +}; +EOF diff --git a/ld/emultempl/armelf.em b/ld/emultempl/armelf.em new file mode 100644 -index 0000000..eee6af1 +index 0000000..34028ee --- /dev/null +++ b/ld/emultempl/armelf.em -@@ -0,0 +1,692 @@ +@@ -0,0 +1,698 @@ +# This shell script emits a C file. -*- C -*- -+# Copyright 1991-2013 Free Software Foundation, Inc. ++# Copyright (C) 1991-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2605408,10 +2618245,10 @@ index 0000000..eee6af1 +#include "ldctor.h" +#include "elf/arm.h" + -+static char *thumb_entry_symbol = NULL; ++static char * thumb_entry_symbol = NULL; +static int byteswap_code = 0; +static int target1_is_rel = 0${TARGET1_IS_REL}; -+static char *target2_type = "${TARGET2_TYPE}"; ++static char * target2_type = "${TARGET2_TYPE}"; +static int fix_v4bx = 0; +static int use_blx = 0; +static bfd_arm_vfp11_fix vfp11_denorm_fix = BFD_ARM_VFP11_FIX_DEFAULT; @@ -2605569,7 +2618406,6 @@ index 0000000..eee6af1 + asection *stub_sec; + flagword flags; + asection *output_section; -+ const char *secname; + lang_output_section_statement_type *os; + struct hook_stub_info info; + @@ -2605583,8 +2618419,7 @@ index 0000000..eee6af1 + bfd_set_section_alignment (stub_file->the_bfd, stub_sec, alignment_power); + + output_section = input_section->output_section; -+ secname = bfd_get_section_name (output_section->owner, output_section); -+ os = lang_output_section_find (secname); ++ os = lang_output_section_get (output_section); + + info.input_section = input_section; + lang_list_init (&info.add); @@ -2605913,6 +2618748,7 @@ index 0000000..eee6af1 +#define OPTION_NO_MERGE_EXIDX_ENTRIES 316 +#define OPTION_FIX_ARM1176 317 +#define OPTION_NO_FIX_ARM1176 318 ++#define OPTION_LONG_PLT 319 +' + +PARSE_AND_LIST_SHORTOPTS=p @@ -2605937,6 +2618773,7 @@ index 0000000..eee6af1 + { "no-merge-exidx-entries", no_argument, NULL, OPTION_NO_MERGE_EXIDX_ENTRIES }, + { "fix-arm1176", no_argument, NULL, OPTION_FIX_ARM1176 }, + { "no-fix-arm1176", no_argument, NULL, OPTION_NO_FIX_ARM1176 }, ++ { "long-plt", no_argument, NULL, OPTION_LONG_PLT }, +' + +PARSE_AND_LIST_OPTIONS=' @@ -2605954,6 +2618791,8 @@ index 0000000..eee6af1 + fprintf (file, _(" --no-wchar-size-warning Don'\''t warn about objects with incompatible\n" + " wchar_t sizes\n")); + fprintf (file, _(" --pic-veneer Always generate PIC interworking veneers\n")); ++ fprintf (file, _(" --long-plt Generate long .plt entries\n" ++ " to handle large .plt/.got displacements\n")); + fprintf (file, _("\ + --stub-group-size=N Maximum size of a group of input sections that\n\ + can be handled by one stub section. A negative\n\ @@ -2606057,6 +2618896,10 @@ index 0000000..eee6af1 + case OPTION_NO_FIX_ARM1176: + fix_arm1176 = 0; + break; ++ ++ case OPTION_LONG_PLT: ++ bfd_elf32_arm_use_long_plt (); ++ break; +' + +# We have our own before_allocation etc. functions, but they call @@ -2606091,13 +2618934,12 @@ index 0000000..08bd8a6 +$ s/\\n"n"$/\\n"/ diff --git a/ld/emultempl/avrelf.em b/ld/emultempl/avrelf.em new file mode 100644 -index 0000000..90894a1 +index 0000000..170dc3e --- /dev/null +++ b/ld/emultempl/avrelf.em -@@ -0,0 +1,277 @@ +@@ -0,0 +1,276 @@ +# This shell script emits a C file. -*- C -*- -+# Copyright 2006, 2007, 2008, 2009 -+# Free Software Foundation, Inc. ++# Copyright (C) 2006-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2606374,7 +2619216,7 @@ index 0000000..90894a1 +LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS=avr_elf_create_output_section_statements diff --git a/ld/emultempl/beos.em b/ld/emultempl/beos.em new file mode 100644 -index 0000000..f59e000 +index 0000000..732abfd --- /dev/null +++ b/ld/emultempl/beos.em @@ -0,0 +1,783 @@ @@ -2606387,8 +2619229,7 @@ index 0000000..f59e000 +fi +fragment < +# +# This file is part of the GNU Binutils. @@ -2607423,13 +2620265,12 @@ index 0000000..f76b95e +LDEMUL_BEFORE_ALLOCATION=cr16elf_before_allocation diff --git a/ld/emultempl/crxelf.em b/ld/emultempl/crxelf.em new file mode 100644 -index 0000000..c6d5a8d +index 0000000..da59429 --- /dev/null +++ b/ld/emultempl/crxelf.em -@@ -0,0 +1,71 @@ +@@ -0,0 +1,70 @@ +# This shell script emits a C file. -*- C -*- -+# Copyright 2004, 2005, 2007, 2009 -+# Free Software Foundation, Inc. ++# Copyright (C) 2004-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2607500,12 +2620341,12 @@ index 0000000..c6d5a8d +LDEMUL_BEFORE_ALLOCATION=crxelf_before_allocation diff --git a/ld/emultempl/elf-generic.em b/ld/emultempl/elf-generic.em new file mode 100644 -index 0000000..2c850f1 +index 0000000..32c102d --- /dev/null +++ b/ld/emultempl/elf-generic.em @@ -0,0 +1,71 @@ +# This shell script emits a C file. -*- C -*- -+# Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc. ++# Copyright (C) 2006-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2607577,10 +2620418,10 @@ index 0000000..2c850f1 +EOF diff --git a/ld/emultempl/elf32.em b/ld/emultempl/elf32.em new file mode 100644 -index 0000000..9a2fe89 +index 0000000..3ebf3b5 --- /dev/null +++ b/ld/emultempl/elf32.em -@@ -0,0 +1,2544 @@ +@@ -0,0 +1,2504 @@ +# This shell script emits a C file. -*- C -*- +# It does some substitutions. +# This file is now misnamed, because it supports both 32 bit and 64 bit @@ -2607595,9 +2620436,7 @@ index 0000000..9a2fe89 +/* This file is is generated by a shell script. DO NOT EDIT! */ + +/* ${ELFSIZE} bit ELF emulation code for ${EMULATION_NAME} -+ Copyright 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, -+ 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 -+ Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + Written by Steve Chamberlain + ELF support by Ian Lance Taylor + @@ -2607623,11 +2620462,9 @@ index 0000000..9a2fe89 +#include "sysdep.h" +#include "bfd.h" +#include "libiberty.h" -+#include "filenames.h" +#include "safe-ctype.h" ++#include "filenames.h" +#include "getopt.h" -+#include "md5.h" -+#include "sha1.h" +#include + +#include "bfdlink.h" @@ -2607639,6 +2620476,7 @@ index 0000000..9a2fe89 +#include "ldlang.h" +#include "ldfile.h" +#include "ldemul.h" ++#include "ldbuildid.h" +#include +#include "elf/common.h" +#include "elf-bfd.h" @@ -2608480,53 +2621318,20 @@ index 0000000..9a2fe89 +{ + const char *style = emit_note_gnu_build_id; + bfd_size_type size; ++ bfd_size_type build_id_size; + + size = offsetof (Elf_External_Note, name[sizeof "GNU"]); + size = (size + 3) & -(bfd_size_type) 4; + -+ if (!strcmp (style, "md5") || !strcmp (style, "uuid")) -+ size += 128 / 8; -+ else if (!strcmp (style, "sha1")) -+ size += 160 / 8; -+ else if (!strncmp (style, "0x", 2)) -+ { -+ /* ID is in string form (hex). Convert to bits. */ -+ const char *id = style + 2; -+ do -+ { -+ if (ISXDIGIT (id[0]) && ISXDIGIT (id[1])) -+ { -+ ++size; -+ id += 2; -+ } -+ else if (*id == '-' || *id == ':') -+ ++id; -+ else -+ { -+ size = 0; -+ break; -+ } -+ } while (*id != '\0'); -+ } ++ build_id_size = compute_build_id_size (style); ++ if (build_id_size) ++ size += build_id_size; + else + size = 0; + + return size; +} + -+static unsigned char -+read_hex (const char xdigit) -+{ -+ if (ISDIGIT (xdigit)) -+ return xdigit - '0'; -+ if (ISUPPER (xdigit)) -+ return xdigit - 'A' + 0xa; -+ if (ISLOWER (xdigit)) -+ return xdigit - 'a' + 0xa; -+ abort (); -+ return 0; -+} -+ +static bfd_boolean +write_build_id (bfd *abfd) +{ @@ -2608539,7 +2621344,6 @@ index 0000000..9a2fe89 + bfd_size_type size; + file_ptr position; + Elf_External_Note *e_note; -+ typedef void (*sum_fn) (const void *, size_t, void *); + + style = t->o->build_id.style; + asec = t->o->build_id.sec; @@ -2608571,55 +2621375,7 @@ index 0000000..9a2fe89 + bfd_h_put_32 (abfd, NT_GNU_BUILD_ID, &e_note->type); + memcpy (e_note->name, "GNU", sizeof "GNU"); + -+ if (strcmp (style, "md5") == 0) -+ { -+ struct md5_ctx ctx; -+ -+ md5_init_ctx (&ctx); -+ if (!bed->s->checksum_contents (abfd, (sum_fn) &md5_process_bytes, &ctx)) -+ return FALSE; -+ md5_finish_ctx (&ctx, id_bits); -+ } -+ else if (strcmp (style, "sha1") == 0) -+ { -+ struct sha1_ctx ctx; -+ -+ sha1_init_ctx (&ctx); -+ if (!bed->s->checksum_contents (abfd, (sum_fn) &sha1_process_bytes, &ctx)) -+ return FALSE; -+ sha1_finish_ctx (&ctx, id_bits); -+ } -+ else if (strcmp (style, "uuid") == 0) -+ { -+ int n; -+ int fd = open ("/dev/urandom", O_RDONLY); -+ if (fd < 0) -+ return FALSE; -+ n = read (fd, id_bits, size); -+ close (fd); -+ if (n < (int) size) -+ return FALSE; -+ } -+ else if (strncmp (style, "0x", 2) == 0) -+ { -+ /* ID is in string form (hex). Convert to bits. */ -+ const char *id = style + 2; -+ size_t n = 0; -+ do -+ { -+ if (ISXDIGIT (id[0]) && ISXDIGIT (id[1])) -+ { -+ id_bits[n] = read_hex (*id++) << 4; -+ id_bits[n++] |= read_hex (*id++); -+ } -+ else if (*id == '-' || *id == ':') -+ ++id; -+ else -+ abort (); /* Should have been validated earlier. */ -+ } while (*id != '\0'); -+ } -+ else -+ abort (); /* Should have been validated earlier. */ ++ generate_build_id (abfd, style, bed->s->checksum_contents, id_bits, size); + + position = i_shdr->sh_offset + asec->output_offset; + size = asec->size; @@ -2608697,7 +2621453,20 @@ index 0000000..9a2fe89 + } + + if (link_info.relocatable) -+ return; ++ { ++ if (link_info.execstack == ! link_info.noexecstack) ++ /* PR ld/16744: If "-z [no]execstack" has been specified on the ++ command line and we are perfoming a relocatable link then no ++ PT_GNU_STACK segment will be created and so the ++ linkinfo.[no]execstack values set in _handle_option() will have no ++ effect. Instead we create a .note.GNU-stack section in much the ++ same way as the assembler does with its --[no]execstack option. */ ++ (void) bfd_make_section_with_flags (link_info.input_bfds, ++ ".note.GNU-stack", ++ SEC_READONLY | (link_info.execstack ? SEC_CODE : 0)); ++ ++ return; ++ } + + if (link_info.eh_frame_hdr + && !link_info.traditional_format) @@ -2609063,6 +2621832,8 @@ index 0000000..9a2fe89 + const char *rpath; + asection *sinterp; + bfd *abfd; ++ struct elf_link_hash_entry *ehdr_start = NULL; ++ struct bfd_link_hash_entry ehdr_start_save = ehdr_start_save; + + if (is_elf_hash_table (link_info.hash)) + { @@ -2609087,6 +2621858,16 @@ index 0000000..9a2fe89 + _bfd_elf_link_hash_hide_symbol (&link_info, h, TRUE); + if (ELF_ST_VISIBILITY (h->other) != STV_INTERNAL) + h->other = (h->other & ~ELF_ST_VISIBILITY (-1)) | STV_HIDDEN; ++ /* Don't leave the symbol undefined. Undefined hidden ++ symbols typically won't have dynamic relocations, but ++ we most likely will need dynamic relocations for ++ __ehdr_start if we are building a PIE or shared ++ library. */ ++ ehdr_start = h; ++ ehdr_start_save = h->root; ++ h->root.type = bfd_link_hash_defined; ++ h->root.u.def.section = bfd_abs_section_ptr; ++ h->root.u.def.value = 0; + } + } + @@ -2609203,6 +2621984,14 @@ index 0000000..9a2fe89 + + if (!bfd_elf_size_dynsym_hash_dynstr (link_info.output_bfd, &link_info)) + einfo ("%P%F: failed to set dynamic section sizes: %E\n"); ++ ++ if (ehdr_start != NULL) ++ { ++ /* If we twiddled __ehdr_start to defined earlier, put it back ++ as it was. */ ++ ehdr_start->root.type = ehdr_start_save.type; ++ ehdr_start->root.u = ehdr_start_save.u; ++ } +} + +EOF @@ -2609221,42 +2622010,46 @@ index 0000000..9a2fe89 +{ + const char *filename; + char *string; ++ size_t len; ++ bfd_boolean opened = FALSE; + + if (! entry->flags.maybe_archive) + return FALSE; + + filename = entry->filename; -+ -+ /* This allocates a few bytes too many when EXTRA_SHLIB_EXTENSION -+ is defined, but it does not seem worth the headache to optimize -+ away those two bytes of space. */ -+ string = (char *) xmalloc (strlen (search->name) -+ + strlen (filename) -+ + strlen (arch) -+#ifdef EXTRA_SHLIB_EXTENSION -+ + strlen (EXTRA_SHLIB_EXTENSION) -+#endif -+ + sizeof "/lib.so"); -+ -+ sprintf (string, "%s/lib%s%s.so", search->name, filename, arch); -+ -+#ifdef EXTRA_SHLIB_EXTENSION -+ /* Try the .so extension first. If that fails build a new filename -+ using EXTRA_SHLIB_EXTENSION. */ -+ if (! ldfile_try_open_bfd (string, entry)) ++ len = strlen (search->name) + strlen (filename); ++ if (entry->flags.full_name_provided) + { -+ sprintf (string, "%s/lib%s%s%s", search->name, -+ filename, arch, EXTRA_SHLIB_EXTENSION); -+#endif ++ len += sizeof "/"; ++ string = (char *) xmalloc (len); ++ sprintf (string, "%s/%s", search->name, filename); ++ } ++ else ++ { ++ size_t xlen = 0; + -+ if (! ldfile_try_open_bfd (string, entry)) ++ len += strlen (arch) + sizeof "/lib.so"; ++#ifdef EXTRA_SHLIB_EXTENSION ++ xlen = (strlen (EXTRA_SHLIB_EXTENSION) > 3 ++ ? strlen (EXTRA_SHLIB_EXTENSION) - 3 ++ : 0); ++#endif ++ string = (char *) xmalloc (len + xlen); ++ sprintf (string, "%s/lib%s%s.so", search->name, filename, arch); ++#ifdef EXTRA_SHLIB_EXTENSION ++ /* Try the .so extension first. If that fails build a new filename ++ using EXTRA_SHLIB_EXTENSION. */ ++ opened = ldfile_try_open_bfd (string, entry); ++ if (!opened) ++ strcpy (string + len - 4, EXTRA_SHLIB_EXTENSION); ++#endif ++ } ++ ++ if (!opened && !ldfile_try_open_bfd (string, entry)) + { + free (string); + return FALSE; + } -+#ifdef EXTRA_SHLIB_EXTENSION -+ } -+#endif + + entry->filename = string; + @@ -2609281,7 +2622074,8 @@ index 0000000..9a2fe89 + /* Rather than duplicating the logic above. Just use the + filename we recorded earlier. */ + -+ filename = lbasename (entry->filename); ++ if (!entry->flags.full_name_provided) ++ filename = lbasename (entry->filename); + bfd_elf_set_dt_needed_name (entry->the_bfd, filename); + } + @@ -2609375,6 +2622169,9 @@ index 0000000..9a2fe89 + { ".rodata", + SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_DATA, + 0, 0, 0, 0 }, ++ { ".tdata", ++ SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_DATA | SEC_THREAD_LOCAL, ++ 0, 0, 0, 0 }, + { ".data", + SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_DATA, + 0, 0, 0, 0 }, @@ -2609398,6 +2622195,7 @@ index 0000000..9a2fe89 + { + orphan_text = 0, + orphan_rodata, ++ orphan_tdata, + orphan_data, + orphan_bss, + orphan_rel, @@ -2609525,6 +2622323,8 @@ index 0000000..9a2fe89 + place = &hold[orphan_bss]; + else if ((s->flags & SEC_SMALL_DATA) != 0) + place = &hold[orphan_sdata]; ++ else if ((s->flags & SEC_THREAD_LOCAL) != 0) ++ place = &hold[orphan_tdata]; + else if ((s->flags & SEC_READONLY) == 0) + place = &hold[orphan_data]; + else if (((iself && (sh_type == SHT_RELA || sh_type == SHT_REL)) @@ -2609580,7 +2622380,7 @@ index 0000000..9a2fe89 +gld${EMULATION_NAME}_get_script (int *isfile) +EOF + -+if test -n "$COMPILE_IN" ++if test x"$COMPILE_IN" = xyes +then +# Scripts compiled in. + @@ -2610122,19 +2622922,18 @@ index 0000000..9a2fe89 + ${LDEMUL_LIST_OPTIONS-gld${EMULATION_NAME}_list_options}, + ${LDEMUL_RECOGNIZED_FILE-gld${EMULATION_NAME}_load_symbols}, + ${LDEMUL_FIND_POTENTIAL_LIBRARIES-NULL}, -+ ${LDEMUL_NEW_VERS_PATTERN-NULL} ++ ${LDEMUL_NEW_VERS_PATTERN-NULL}, ++ ${LDEMUL_EXTRA_MAP_FILE_TEXT-NULL} +}; +EOF diff --git a/ld/emultempl/epiphanyelf_4x4.em b/ld/emultempl/epiphanyelf_4x4.em new file mode 100644 -index 0000000..9f913ea +index 0000000..650604a --- /dev/null +++ b/ld/emultempl/epiphanyelf_4x4.em -@@ -0,0 +1,32 @@ +@@ -0,0 +1,30 @@ +# This shell script emits a C file. -*- C -*- -+# Copyright 1991, 1993, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, -+# 2004, 2005, 2007, 2008 -+# Free Software Foundation, Inc. ++# Copyright (C) 1991-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2610165,12 +2622964,12 @@ index 0000000..9f913ea + diff --git a/ld/emultempl/genelf.em b/ld/emultempl/genelf.em new file mode 100644 -index 0000000..ce416eb +index 0000000..8561c17 --- /dev/null +++ b/ld/emultempl/genelf.em @@ -0,0 +1,71 @@ +# This shell script emits a C file. -*- C -*- -+# Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc. ++# Copyright (C) 2006-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2610242,7 +2623041,7 @@ index 0000000..ce416eb +LDEMUL_AFTER_ALLOCATION=gld${EMULATION_NAME}_after_allocation diff --git a/ld/emultempl/generic.em b/ld/emultempl/generic.em new file mode 100644 -index 0000000..dce2bff +index 0000000..111b1c1 --- /dev/null +++ b/ld/emultempl/generic.em @@ -0,0 +1,161 @@ @@ -2610252,8 +2623051,7 @@ index 0000000..dce2bff +/* This file is is generated by a shell script. DO NOT EDIT! */ + +/* emulate the original gld for the given ${EMULATION_NAME} -+ Copyright 1991, 1992, 1994, 1996, 1999, 2000, 2001, 2002, 2003, 2004, 2005, -+ 2007 Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + Written by Steve Chamberlain steve@cygnus.com + + This file is part of the GNU Binutils. @@ -2610329,7 +2623127,7 @@ index 0000000..dce2bff +gld${EMULATION_NAME}_get_script (int *isfile) +EOF + -+if test -n "$COMPILE_IN" ++if test x"$COMPILE_IN" = xyes +then +# Scripts compiled in. + @@ -2610404,20 +2623202,20 @@ index 0000000..dce2bff + ${LDEMUL_LIST_OPTIONS-NULL}, + ${LDEMUL_RECOGNIZED_FILE-NULL}, + ${LDEMUL_FIND_POTENTIAL_LIBRARIES-NULL}, -+ ${LDEMUL_NEW_VERS_PATTERN-NULL} ++ ${LDEMUL_NEW_VERS_PATTERN-NULL}, ++ ${LDEMUL_EXTRA_MAP_FILE_TEXT-NULL} +}; +EOF diff --git a/ld/emultempl/gld960.em b/ld/emultempl/gld960.em new file mode 100644 -index 0000000..4ba3eec +index 0000000..5632f31 --- /dev/null +++ b/ld/emultempl/gld960.em @@ -0,0 +1,154 @@ +# This shell script emits a C file. -*- C -*- +# It does some substitutions. +fragment <output_section; -+ secname = bfd_get_section_name (output_section->owner, output_section); -+ os = lang_output_section_find (secname); ++ os = lang_output_section_get (output_section); + + info.input_section = input_section; + lang_list_init (&info.add); @@ -2611128,12 +2623924,12 @@ index 0000000..65c1ea5 +LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS=hppaelf_create_output_section_statements diff --git a/ld/emultempl/ia64elf.em b/ld/emultempl/ia64elf.em new file mode 100644 -index 0000000..88d5748 +index 0000000..b14cb3d --- /dev/null +++ b/ld/emultempl/ia64elf.em @@ -0,0 +1,65 @@ +# This shell script emits a C file. -*- C -*- -+# Copyright 2003, 2005, 2006, 2007, 2009 Free Software Foundation, Inc. ++# Copyright (C) 2003-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2611199,12 +2623995,12 @@ index 0000000..88d5748 +source_em ${srcdir}/emultempl/needrelax.em diff --git a/ld/emultempl/irix.em b/ld/emultempl/irix.em new file mode 100644 -index 0000000..41b8ce4 +index 0000000..502d4a5 --- /dev/null +++ b/ld/emultempl/irix.em @@ -0,0 +1,44 @@ +# This shell script emits a C file. -*- C -*- -+# Copyright 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. ++# Copyright (C) 2004-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2611249,7 +2624045,7 @@ index 0000000..41b8ce4 +source_em "${srcdir}/emultempl/mipself.em" diff --git a/ld/emultempl/linux.em b/ld/emultempl/linux.em new file mode 100644 -index 0000000..61c7df4 +index 0000000..bbc5946 --- /dev/null +++ b/ld/emultempl/linux.em @@ -0,0 +1,211 @@ @@ -2611264,8 +2624060,7 @@ index 0000000..61c7df4 +/* This file is is generated by a shell script. DO NOT EDIT! */ + +/* Linux a.out emulation code for ${EMULATION_NAME} -+ Copyright 1991, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, 2002, -+ 2003, 2004, 2005, 2007, 2008, 2012 Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + Written by Steve Chamberlain + Linux support by Eric Youngdale + @@ -2611317,7 +2624112,7 @@ index 0000000..61c7df4 +{ + char *string; + -+ if (! entry->flags.maybe_archive) ++ if (! entry->flags.maybe_archive || entry->flags.full_name_provided) + return FALSE; + + string = (char *) xmalloc (strlen (search->name) @@ -2611386,7 +2624181,7 @@ index 0000000..61c7df4 +gld${EMULATION_NAME}_get_script (int *isfile) +EOF + -+if test -n "$COMPILE_IN" ++if test x"$COMPILE_IN" = xyes +then +# Scripts compiled in. + @@ -2611461,12 +2624256,13 @@ index 0000000..61c7df4 + NULL, /* list options */ + NULL, /* recognized file */ + NULL, /* find_potential_libraries */ -+ NULL /* new_vers_pattern */ ++ NULL, /* new_vers_pattern */ ++ NULL /* extra_map_file_text */ +}; +EOF diff --git a/ld/emultempl/lnk960.em b/ld/emultempl/lnk960.em new file mode 100644 -index 0000000..e556d43 +index 0000000..6364f6d --- /dev/null +++ b/ld/emultempl/lnk960.em @@ -0,0 +1,348 @@ @@ -2611474,8 +2624270,7 @@ index 0000000..e556d43 +# It does some substitutions. +fragment <output_section; -+ secname = bfd_get_section_name (output_section->owner, output_section); -+ os = lang_output_section_find (secname); ++ os = lang_output_section_get (output_section); + + /* Try to put the new section at the same place as an existing + .tramp section. Such .tramp section exists in most cases and @@ -2612199,7 +2624992,7 @@ index 0000000..594b193 +LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS=m68hc11elf_create_output_section_statements diff --git a/ld/emultempl/m68kcoff.em b/ld/emultempl/m68kcoff.em new file mode 100644 -index 0000000..f68866c +index 0000000..e46889a --- /dev/null +++ b/ld/emultempl/m68kcoff.em @@ -0,0 +1,245 @@ @@ -2612209,8 +2625002,7 @@ index 0000000..f68866c +/* This file is is generated by a shell script. DO NOT EDIT! */ + +/* Handle embedded relocs for m68k. -+ Copyright 2000, 2002, 2003, 2004, 2005, 2007, 2008 -+ Free Software Foundation, Inc. ++ Copyright (C) 2000-2014 Free Software Foundation, Inc. + Written by Michael Sokolov , based on generic.em + by Steve Chamberlain , embedded relocs code based on + mipsecoff.em by Ian Lance Taylor (now removed). @@ -2612370,7 +2625162,7 @@ index 0000000..f68866c +gld${EMULATION_NAME}_get_script (int *isfile) +EOF + -+if test -n "$COMPILE_IN" ++if test x"$COMPILE_IN" = xyes +then +# Scripts compiled in. + @@ -2612445,18 +2625237,18 @@ index 0000000..f68866c + NULL, /* list options */ + NULL, /* recognized file */ + NULL, /* find_potential_libraries */ -+ NULL /* new_vers_pattern */ ++ NULL, /* new_vers_pattern */ ++ NULL /* extra_map_file_text */ +}; +EOF diff --git a/ld/emultempl/m68kelf.em b/ld/emultempl/m68kelf.em new file mode 100644 -index 0000000..48a50bc +index 0000000..35b3088 --- /dev/null +++ b/ld/emultempl/m68kelf.em -@@ -0,0 +1,250 @@ +@@ -0,0 +1,249 @@ +# This shell script emits a C file. -*- C -*- -+# Copyright 2000, 2001, 2003, 2005, 2007, 2008, 2009 -+# Free Software Foundation, Inc. ++# Copyright (C) 2000-2014 Free Software Foundation, Inc. +# Written by Michael Sokolov , based on armelf.em +# +# This file is part of the GNU Binutils. @@ -2612706,12 +2625498,12 @@ index 0000000..48a50bc +LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS=elf_m68k_create_output_section_statements diff --git a/ld/emultempl/metagelf.em b/ld/emultempl/metagelf.em new file mode 100644 -index 0000000..21e3e94 +index 0000000..1f77ecd --- /dev/null +++ b/ld/emultempl/metagelf.em -@@ -0,0 +1,337 @@ +@@ -0,0 +1,335 @@ +# This shell script emits a C file. -*- C -*- -+# Copyright 2013 Free Software Foundation, Inc. ++# Copyright (C) 2013-2014 Free Software Foundation, Inc. +# +# This file is part of GNU Binutils. +# @@ -2612757,9 +2625549,9 @@ index 0000000..21e3e94 +static void +metagelf_create_output_section_statements (void) +{ -+ extern const bfd_target bfd_elf32_metag_vec; ++ extern const bfd_target metag_elf32_vec; + -+ if (link_info.output_bfd->xvec != &bfd_elf32_metag_vec) ++ if (link_info.output_bfd->xvec != &metag_elf32_vec) + return; + + stub_file = lang_add_input_file ("linker stubs", @@ -2612866,7 +2625658,6 @@ index 0000000..21e3e94 + asection *stub_sec; + flagword flags; + asection *output_section; -+ const char *secname; + lang_output_section_statement_type *os; + struct hook_stub_info info; + @@ -2612878,8 +2625669,7 @@ index 0000000..21e3e94 + goto err_ret; + + output_section = input_section->output_section; -+ secname = bfd_get_section_name (output_section->owner, output_section); -+ os = lang_output_section_find (secname); ++ os = lang_output_section_get (output_section); + + info.input_section = input_section; + lang_list_init (&info.add); @@ -2613049,12 +2625839,12 @@ index 0000000..21e3e94 +LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS=metagelf_create_output_section_statements diff --git a/ld/emultempl/mipself.em b/ld/emultempl/mipself.em new file mode 100644 -index 0000000..3c6ec9f +index 0000000..b6e17ce --- /dev/null +++ b/ld/emultempl/mipself.em -@@ -0,0 +1,286 @@ +@@ -0,0 +1,283 @@ +# This shell script emits a C file. -*- C -*- -+# Copyright 2004, 2006, 2007, 2008 Free Software Foundation, Inc. ++# Copyright (C) 2004-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2613191,7 +2625981,6 @@ index 0000000..3c6ec9f +{ + asection *stub_sec; + flagword flags; -+ const char *secname; + lang_output_section_statement_type *os; + struct hook_stub_info info; + @@ -2613231,9 +2626020,7 @@ index 0000000..3c6ec9f + if (!bfd_set_section_flags (stub_bfd, stub_sec, flags)) + goto err_ret; + -+ /* Create an output section statement. */ -+ secname = bfd_get_section_name (output_section->owner, output_section); -+ os = lang_output_section_find (secname); ++ os = lang_output_section_get (output_section); + + /* Initialize a statement list that contains only the new statement. */ + lang_list_init (&info.add); @@ -2613341,13 +2626128,12 @@ index 0000000..3c6ec9f +LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS=mips_create_output_section_statements diff --git a/ld/emultempl/mmix-elfnmmo.em b/ld/emultempl/mmix-elfnmmo.em new file mode 100644 -index 0000000..0059792 +index 0000000..5ef5e5e --- /dev/null +++ b/ld/emultempl/mmix-elfnmmo.em -@@ -0,0 +1,116 @@ +@@ -0,0 +1,115 @@ +# This shell script emits a C file. -*- C -*- -+# Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 -+# Free Software Foundation, Inc. ++# Copyright (C) 2001-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2613449,7 +2626235,7 @@ index 0000000..0059792 + This section is only present when there are register symbols. */ + sec = bfd_get_section_by_name (link_info.output_bfd, MMIX_REG_SECTION_NAME); + if (sec != NULL) -+ bfd_set_section_vma (abfd, sec, 0); ++ bfd_set_section_vma (sec->owner, sec, 0); + + if (!_bfd_mmix_after_linker_allocation (link_info.output_bfd, &link_info)) + { @@ -2613463,12 +2626249,12 @@ index 0000000..0059792 +LDEMUL_BEFORE_ALLOCATION=mmix_before_allocation diff --git a/ld/emultempl/mmixelf.em b/ld/emultempl/mmixelf.em new file mode 100644 -index 0000000..89c60c9 +index 0000000..566eeb0 --- /dev/null +++ b/ld/emultempl/mmixelf.em @@ -0,0 +1,46 @@ +# This shell script emits a C file. -*- C -*- -+# Copyright 2001, 2002, 2003, 2005, 2007, 2012 Free Software Foundation, Inc. ++# Copyright (C) 2001-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2613515,13 +2626301,12 @@ index 0000000..89c60c9 +LDEMUL_BEFORE_PARSE=elfmmix_before_parse diff --git a/ld/emultempl/mmo.em b/ld/emultempl/mmo.em new file mode 100644 -index 0000000..b895a9a +index 0000000..f7deaaa --- /dev/null +++ b/ld/emultempl/mmo.em -@@ -0,0 +1,221 @@ +@@ -0,0 +1,220 @@ +# This shell script emits a C file. -*- C -*- -+# Copyright 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 -+# Free Software Foundation, Inc. ++# Copyright (C) 2001-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2613742,12 +2626527,12 @@ index 0000000..b895a9a +LDEMUL_AFTER_OPEN=mmo_after_open diff --git a/ld/emultempl/nds32elf.em b/ld/emultempl/nds32elf.em new file mode 100644 -index 0000000..d94506a +index 0000000..96e6aa3 --- /dev/null +++ b/ld/emultempl/nds32elf.em -@@ -0,0 +1,475 @@ +@@ -0,0 +1,476 @@ +# This shell script emits a C file. -*- C -*- -+# Copyright (C) 2012-2013 Free Software Foundation, Inc. ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# Contributed by Andes Technology Corporation. +# +# This file is part of the GNU Binutils. @@ -2613773,6 +2626558,7 @@ index 0000000..d94506a +#include "libbfd.h" +#include "elf-bfd.h" +#include "elf/nds32.h" ++#include "bfd_stdint.h" +#include "elf32-nds32.h" + +static int relax_fp_as_gp = 1; /* --mrelax-omit-fp */ @@ -2614223,12 +2627009,12 @@ index 0000000..d94506a +LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS=nds32_elf_create_output_section_statements diff --git a/ld/emultempl/needrelax.em b/ld/emultempl/needrelax.em new file mode 100644 -index 0000000..7f90224 +index 0000000..a89f122 --- /dev/null +++ b/ld/emultempl/needrelax.em @@ -0,0 +1,39 @@ +# This shell script emits a C file. -*- C -*- -+# Copyright 2001, 2002, 2003, 2005, 2007 Free Software Foundation, Inc. ++# Copyright (C) 2001-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2614268,12 +2627054,12 @@ index 0000000..7f90224 +EOF diff --git a/ld/emultempl/netbsd.em b/ld/emultempl/netbsd.em new file mode 100644 -index 0000000..99b48b0 +index 0000000..82478b2 --- /dev/null +++ b/ld/emultempl/netbsd.em @@ -0,0 +1,34 @@ +# This shell script emits a C file. -*- C -*- -+# Copyright 2007 Free Software Foundation, Inc. ++# Copyright (C) 2007-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2614306,6 +2627092,329 @@ index 0000000..99b48b0 + link_info.common_skip_ar_symbols = bfd_link_common_skip_text; +} +EOF +diff --git a/ld/emultempl/nios2elf.em b/ld/emultempl/nios2elf.em +new file mode 100644 +index 0000000..991a11b +--- /dev/null ++++ b/ld/emultempl/nios2elf.em +@@ -0,0 +1,317 @@ ++# This shell script emits a C file. -*- C -*- ++# Copyright (C) 2013-2014 Free Software Foundation, Inc. ++# ++# This file is part of GNU Binutils. ++# ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 3 of the License, or ++# (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ++# MA 02110-1301, USA. ++# ++ ++# This file is sourced from elf32.em, and defines extra Nios II ELF ++# specific routines. Taken from metagelf.em. ++# ++fragment <xvec != &nios2_elf32_le_vec ++ && link_info.output_bfd->xvec != &nios2_elf32_be_vec) ++ return; ++ ++ /* If --no-relax was not explicitly specified by the user, enable ++ relaxation. If it's not enabled (either explicitly or by default), ++ we're done, as we won't need to create any stubs. */ ++ if (!link_info.relocatable && RELAXATION_DISABLED_BY_DEFAULT) ++ ENABLE_RELAXATION; ++ if (!RELAXATION_ENABLED) ++ return; ++ ++ stub_file = lang_add_input_file ("linker stubs", ++ lang_input_file_is_fake_enum, ++ NULL); ++ stub_file->the_bfd = bfd_create ("linker stubs", link_info.output_bfd); ++ if (stub_file->the_bfd == NULL ++ || ! bfd_set_arch_mach (stub_file->the_bfd, ++ bfd_get_arch (link_info.output_bfd), ++ bfd_get_mach (link_info.output_bfd))) ++ { ++ einfo ("%X%P: can not create BFD %E\n"); ++ return; ++ } ++ ++ stub_file->the_bfd->flags |= BFD_LINKER_CREATED; ++ ldlang_add_file (stub_file); ++} ++ ++ ++struct hook_stub_info ++{ ++ lang_statement_list_type add; ++ asection *input_section; ++}; ++ ++/* Traverse the linker tree to find the spot where the stub goes. */ ++ ++static bfd_boolean ++hook_in_stub (struct hook_stub_info *info, lang_statement_union_type **lp, ++ bfd_boolean afterp) ++{ ++ lang_statement_union_type *l; ++ bfd_boolean ret; ++ ++ for (; (l = *lp) != NULL; lp = &l->header.next) ++ { ++ switch (l->header.type) ++ { ++ case lang_constructors_statement_enum: ++ ret = hook_in_stub (info, &constructor_list.head, afterp); ++ if (ret) ++ return ret; ++ break; ++ ++ case lang_output_section_statement_enum: ++ ret = hook_in_stub (info, ++ &l->output_section_statement.children.head, ++ afterp); ++ if (ret) ++ return ret; ++ break; ++ ++ case lang_wild_statement_enum: ++ ret = hook_in_stub (info, &l->wild_statement.children.head, afterp); ++ if (ret) ++ return ret; ++ break; ++ ++ case lang_group_statement_enum: ++ ret = hook_in_stub (info, &l->group_statement.children.head, afterp); ++ if (ret) ++ return ret; ++ break; ++ ++ case lang_input_section_enum: ++ if (l->input_section.section == info->input_section) ++ { ++ /* We've found our section. Insert the stub immediately ++ before or after its associated input section. */ ++ if (afterp) ++ { ++ *(info->add.tail) = l->header.next; ++ l->header.next = info->add.head; ++ } ++ else ++ { ++ *lp = info->add.head; ++ *(info->add.tail) = l; ++ } ++ return TRUE; ++ } ++ break; ++ ++ case lang_data_statement_enum: ++ case lang_reloc_statement_enum: ++ case lang_object_symbols_statement_enum: ++ case lang_output_statement_enum: ++ case lang_target_statement_enum: ++ case lang_input_statement_enum: ++ case lang_assignment_statement_enum: ++ case lang_padding_statement_enum: ++ case lang_address_statement_enum: ++ case lang_fill_statement_enum: ++ break; ++ ++ default: ++ FAIL (); ++ break; ++ } ++ } ++ return FALSE; ++} ++ ++/* Call-back for elf32_nios2_size_stubs. */ ++ ++/* Create a new stub section, and arrange for it to be linked ++ immediately before or after INPUT_SECTION, according to AFTERP. */ ++ ++static asection * ++nios2elf_add_stub_section (const char *stub_sec_name, asection *input_section, ++ bfd_boolean afterp) ++{ ++ asection *stub_sec; ++ flagword flags; ++ asection *output_section; ++ const char *secname; ++ lang_output_section_statement_type *os; ++ struct hook_stub_info info; ++ ++ flags = (SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE ++ | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY | SEC_KEEP); ++ stub_sec = bfd_make_section_anyway_with_flags (stub_file->the_bfd, ++ stub_sec_name, flags); ++ if (stub_sec == NULL) ++ goto err_ret; ++ ++ output_section = input_section->output_section; ++ secname = bfd_get_section_name (output_section->owner, output_section); ++ os = lang_output_section_find (secname); ++ ++ info.input_section = input_section; ++ lang_list_init (&info.add); ++ lang_add_section (&info.add, stub_sec, NULL, os); ++ ++ if (info.add.head == NULL) ++ goto err_ret; ++ ++ if (hook_in_stub (&info, &os->children.head, afterp)) ++ return stub_sec; ++ ++ err_ret: ++ einfo ("%X%P: can not make stub section: %E\n"); ++ return NULL; ++} ++ ++ ++/* Another call-back for elf32_nios2_size_stubs. */ ++ ++static void ++nios2elf_layout_sections_again (void) ++{ ++ /* If we have changed sizes of the stub sections, then we need ++ to recalculate all the section offsets. This may mean we need to ++ add even more stubs. */ ++ gld${EMULATION_NAME}_map_segments (TRUE); ++ need_laying_out = -1; ++} ++ ++ ++static void ++build_section_lists (lang_statement_union_type *statement) ++{ ++ if (statement->header.type == lang_input_section_enum) ++ { ++ asection *i = statement->input_section.section; ++ ++ if (i->sec_info_type != SEC_INFO_TYPE_JUST_SYMS ++ && (i->flags & SEC_EXCLUDE) == 0 ++ && i->output_section != NULL ++ && i->output_section->owner == link_info.output_bfd) ++ { ++ nios2_elf32_next_input_section (&link_info, i); ++ } ++ } ++} ++ ++ ++/* For Nios II we use this opportunity to build linker stubs. */ ++ ++static void ++gld${EMULATION_NAME}_after_allocation (void) ++{ ++ /* bfd_elf_discard_info just plays with data and debugging sections, ++ ie. doesn't affect code size, so we can delay resizing the ++ sections. It's likely we'll resize everything in the process of ++ adding stubs. */ ++ if (bfd_elf_discard_info (link_info.output_bfd, &link_info)) ++ need_laying_out = 1; ++ ++ /* If generating a relocatable output file, then we don't ++ have to examine the relocs. */ ++ if (stub_file != NULL && !link_info.relocatable && RELAXATION_ENABLED) ++ { ++ int ret = nios2_elf32_setup_section_lists (link_info.output_bfd, ++ &link_info); ++ ++ if (ret != 0) ++ { ++ if (ret < 0) ++ { ++ einfo ("%X%P: can not size stub section: %E\n"); ++ return; ++ } ++ ++ lang_for_each_statement (build_section_lists); ++ ++ /* Call into the BFD backend to do the real work. */ ++ if (! nios2_elf32_size_stubs (link_info.output_bfd, ++ stub_file->the_bfd, ++ &link_info, ++ &nios2elf_add_stub_section, ++ &nios2elf_layout_sections_again)) ++ { ++ einfo ("%X%P: can not size stub section: %E\n"); ++ return; ++ } ++ } ++ } ++ ++ if (need_laying_out != -1) ++ gld${EMULATION_NAME}_map_segments (need_laying_out); ++ ++ if (!link_info.relocatable && RELAXATION_ENABLED) ++ { ++ /* Now build the linker stubs. */ ++ if (stub_file != NULL && stub_file->the_bfd->sections != NULL) ++ { ++ if (! nios2_elf32_build_stubs (&link_info)) ++ einfo ("%X%P: can not build stubs: %E\n"); ++ } ++ } ++} ++ ++ ++/* Avoid processing the fake stub_file in vercheck, stat_needed and ++ check_needed routines. */ ++ ++static void (*real_func) (lang_input_statement_type *); ++ ++static void nios2_for_each_input_file_wrapper (lang_input_statement_type *l) ++{ ++ if (l != stub_file) ++ (*real_func) (l); ++} ++ ++static void ++nios2_lang_for_each_input_file (void (*func) (lang_input_statement_type *)) ++{ ++ real_func = func; ++ lang_for_each_input_file (&nios2_for_each_input_file_wrapper); ++} ++ ++#define lang_for_each_input_file nios2_lang_for_each_input_file ++ ++EOF ++ ++ ++# Put these extra nios2elf routines in ld_${EMULATION_NAME}_emulation ++# ++LDEMUL_AFTER_ALLOCATION=gld${EMULATION_NAME}_after_allocation ++LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS=nios2elf_create_output_section_statements diff --git a/ld/emultempl/ostring.sed b/ld/emultempl/ostring.sed new file mode 100644 index 0000000..a526d3f @@ -2614318,10 +2627427,10 @@ index 0000000..a526d3f +$ s/$/n"/ diff --git a/ld/emultempl/pe.em b/ld/emultempl/pe.em new file mode 100644 -index 0000000..5d6da9e +index 0000000..3a37508 --- /dev/null +++ b/ld/emultempl/pe.em -@@ -0,0 +1,2239 @@ +@@ -0,0 +1,2455 @@ +# This shell script emits a C file. -*- C -*- +# It does some substitutions. +if [ -z "$MACHINE" ]; then @@ -2614332,7 +2627441,7 @@ index 0000000..5d6da9e +rm -f e${EMULATION_NAME}.c +(echo;echo;echo;echo;echo)>e${EMULATION_NAME}.c # there, now line numbers match ;-) +fragment < Generate import library\n")); + fprintf (file, _(" --output-def Generate a .DEF file for the built DLL\n")); -+ fprintf (file, _(" --warn-duplicate-exports Warn about duplicate exports.\n")); ++ fprintf (file, _(" --warn-duplicate-exports Warn about duplicate exports\n")); + fprintf (file, _(" --compat-implib Create backward compatible import libs;\n\ + create __imp_ as well.\n")); -+ fprintf (file, _(" --enable-auto-image-base Automatically choose image base for DLLs\n\ -+ unless user specifies one\n")); ++ fprintf (file, _(" --enable-auto-image-base[=
] Automatically choose image base for DLLs\n\ ++ (optionally starting with address) unless\n\ ++ specifically set with --image-base\n")); + fprintf (file, _(" --disable-auto-image-base Do not auto-choose image base. (default)\n")); + fprintf (file, _(" --dll-search-prefix= When linking dynamically to a dll without\n\ + an importlib, use .dll\n\ @@ -2614817,6 +2627933,7 @@ index 0000000..5d6da9e + fprintf (file, _(" --no-bind Do not bind this image\n")); + fprintf (file, _(" --wdmdriver Driver uses the WDM model\n")); + fprintf (file, _(" --tsaware Image is Terminal Server aware\n")); ++ fprintf (file, _(" --build-id[=STYLE] Generate build ID\n")); +} + + @@ -2615011,6 +2628128,7 @@ index 0000000..5d6da9e + einfo (_("%P%F: strange hex info for PE parameter '%s'\n"), optarg); +} + ++#define DEFAULT_BUILD_ID_STYLE "md5" + +static bfd_boolean +gld${EMULATION_NAME}_handle_option (int optc) @@ -2615126,6 +2628244,12 @@ index 0000000..5d6da9e + break; + case OPTION_ENABLE_AUTO_IMAGE_BASE: + pe_enable_auto_image_base = 1; ++ if (optarg && *optarg) ++ { ++ char *end; ++ pe_auto_image_base = strtoul (optarg, &end, 0); ++ /* XXX should check that we actually parsed something */ ++ } + break; + case OPTION_DISABLE_AUTO_IMAGE_BASE: + pe_enable_auto_image_base = 0; @@ -2615196,6 +2628320,17 @@ index 0000000..5d6da9e + case OPTION_TERMINAL_SERVER_AWARE: + pe_dll_characteristics |= IMAGE_DLLCHARACTERISTICS_TERMINAL_SERVER_AWARE; + break; ++ case OPTION_BUILD_ID: ++ if (emit_build_id != NULL) ++ { ++ free ((char *) emit_build_id); ++ emit_build_id = NULL; ++ } ++ if (optarg == NULL) ++ optarg = DEFAULT_BUILD_ID_STYLE; ++ if (strcmp (optarg, "none")) ++ emit_build_id = xstrdup (optarg); ++ break; + } + + /* Set DLLCharacteristics bits */ @@ -2615235,7 +2628370,7 @@ index 0000000..5d6da9e +compute_dll_image_base (const char *ofile) +{ + unsigned long hash = strhash (ofile); -+ return 0x61300000 + ((hash << 16) & 0x0FFC0000); ++ return pe_auto_image_base + ((hash << 16) & 0x0FFC0000); +} +#endif + @@ -2615551,6 +2628686,169 @@ index 0000000..5d6da9e + *found = 1; +} + ++static bfd_boolean ++pecoff_checksum_contents (bfd *abfd, ++ void (*process) (const void *, size_t, void *), ++ void *arg) ++{ ++ file_ptr filepos = (file_ptr) 0; ++ ++ while (1) ++ { ++ unsigned char b; ++ int status; ++ ++ if (bfd_seek (abfd, filepos, SEEK_SET) != 0) ++ return 0; ++ ++ status = bfd_bread (&b, (bfd_size_type) 1, abfd); ++ if (status < 1) ++ { ++ break; ++ } ++ ++ (*process) (&b, 1, arg); ++ filepos += 1; ++ } ++ ++ return TRUE; ++} ++ ++static bfd_boolean ++write_build_id (bfd *abfd) ++{ ++ struct pe_tdata *t = pe_data (abfd); ++ asection *asec; ++ struct bfd_link_order *link_order = NULL; ++ unsigned char *contents; ++ bfd_size_type size; ++ bfd_size_type build_id_size; ++ unsigned char *build_id; ++ ++ /* Find the section the .build-id output section has been merged info. */ ++ for (asec = abfd->sections; asec != NULL; asec = asec->next) ++ { ++ struct bfd_link_order *l = NULL; ++ for (l = asec->map_head.link_order; l != NULL; l = l->next) ++ { ++ if ((l->type == bfd_indirect_link_order)) ++ { ++ if (l->u.indirect.section == t->build_id.sec) ++ { ++ link_order = l; ++ break; ++ } ++ } ++ } ++ ++ if (link_order) ++ break; ++ } ++ ++ if (!link_order) ++ { ++ einfo (_("%P: warning: .build-id section discarded," ++ " --build-id ignored.\n")); ++ return TRUE; ++ } ++ ++ if (t->build_id.sec->contents == NULL) ++ t->build_id.sec->contents = (unsigned char *) xmalloc (t->build_id.sec->size); ++ contents = t->build_id.sec->contents; ++ size = t->build_id.sec->size; ++ ++ build_id_size = compute_build_id_size (t->build_id.style); ++ build_id = xmalloc (build_id_size); ++ generate_build_id (abfd, t->build_id.style, pecoff_checksum_contents, build_id, build_id_size); ++ ++ bfd_vma ib = pe_data (link_info.output_bfd)->pe_opthdr.ImageBase; ++ ++ /* Construct a debug directory entry which points to an immediately following CodeView record. */ ++ struct internal_IMAGE_DEBUG_DIRECTORY idd; ++ idd.Characteristics = 0; ++ idd.TimeDateStamp = 0; ++ idd.MajorVersion = 0; ++ idd.MinorVersion = 0; ++ idd.Type = PE_IMAGE_DEBUG_TYPE_CODEVIEW; ++ idd.SizeOfData = sizeof (CV_INFO_PDB70) + 1; ++ idd.AddressOfRawData = asec->vma - ib + link_order->offset ++ + sizeof (struct external_IMAGE_DEBUG_DIRECTORY); ++ idd.PointerToRawData = asec->filepos + link_order->offset ++ + sizeof (struct external_IMAGE_DEBUG_DIRECTORY); ++ ++ struct external_IMAGE_DEBUG_DIRECTORY *ext = (struct external_IMAGE_DEBUG_DIRECTORY *)contents; ++ _bfd_XXi_swap_debugdir_out (abfd, &idd, ext); ++ ++ /* Write the debug directory entry. */ ++ if (bfd_seek (abfd, asec->filepos + link_order->offset, SEEK_SET) != 0) ++ return 0; ++ ++ if ((bfd_bwrite (contents, size, abfd) != size)) ++ return 0; ++ ++ /* Construct the CodeView record. */ ++ CODEVIEW_INFO cvinfo; ++ cvinfo.CVSignature = CVINFO_PDB70_CVSIGNATURE; ++ cvinfo.Age = 1; ++ ++ /* Zero pad or truncate the generated build_id to fit in the CodeView record. */ ++ memset (&(cvinfo.Signature), 0, CV_INFO_SIGNATURE_LENGTH); ++ memcpy (&(cvinfo.Signature), build_id, (build_id_size > CV_INFO_SIGNATURE_LENGTH) ++ ? CV_INFO_SIGNATURE_LENGTH : build_id_size); ++ ++ free (build_id); ++ ++ /* Write the codeview record. */ ++ if (_bfd_XXi_write_codeview_record (abfd, idd.PointerToRawData, &cvinfo) == 0) ++ return 0; ++ ++ /* Record the location of the debug directory in the data directory. */ ++ pe_data (link_info.output_bfd)->pe_opthdr.DataDirectory[PE_DEBUG_DATA].VirtualAddress ++ = asec->vma - ib + link_order->offset; ++ pe_data (link_info.output_bfd)->pe_opthdr.DataDirectory[PE_DEBUG_DATA].Size ++ = sizeof (struct external_IMAGE_DEBUG_DIRECTORY); ++ ++ return TRUE; ++} ++ ++/* Make .build-id section, and set up coff_tdata->build_id. */ ++static bfd_boolean ++setup_build_id (bfd *ibfd) ++{ ++ asection *s; ++ flagword flags; ++ ++ if (!validate_build_id_style (emit_build_id)) ++ { ++ einfo ("%P: warning: unrecognized --build-id style ignored.\n"); ++ return FALSE; ++ } ++ ++ flags = (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_IN_MEMORY ++ | SEC_LINKER_CREATED | SEC_READONLY | SEC_DATA); ++ s = bfd_make_section_anyway_with_flags (ibfd, ".build-id", flags); ++ if (s != NULL) ++ { ++ struct pe_tdata *t = pe_data (link_info.output_bfd); ++ t->build_id.after_write_object_contents = &write_build_id; ++ t->build_id.style = emit_build_id; ++ t->build_id.sec = s; ++ ++ /* Section is a fixed size: ++ One IMAGE_DEBUG_DIRECTORY entry, of type IMAGE_DEBUG_TYPE_CODEVIEW, ++ pointing at a CV_INFO_PDB70 record containing the build-id, with a ++ null byte for PdbFileName. */ ++ s->size = sizeof (struct external_IMAGE_DEBUG_DIRECTORY) ++ + sizeof (CV_INFO_PDB70) + 1; ++ ++ return TRUE; ++ } ++ ++ einfo ("%P: warning: Cannot create .build-id section," ++ " --build-id ignored.\n"); ++ return FALSE; ++} ++ +static void +gld_${EMULATION_NAME}_after_open (void) +{ @@ -2615573,6 +2628871,26 @@ index 0000000..5d6da9e + } +#endif + ++ if (emit_build_id != NULL) ++ { ++ bfd *abfd; ++ ++ /* Find a COFF input. */ ++ for (abfd = link_info.input_bfds; ++ abfd != (bfd *) NULL; abfd = abfd->link_next) ++ if (bfd_get_flavour (abfd) == bfd_target_coff_flavour) ++ break; ++ ++ /* If there are no COFF input files do not try to ++ add a build-id section. */ ++ if (abfd == NULL ++ || !setup_build_id (abfd)) ++ { ++ free ((char *) emit_build_id); ++ emit_build_id = NULL; ++ } ++ } ++ + /* Pass the wacky PE command line options into the output bfd. + FIXME: This should be done via a function, rather than by + including an internal BFD header. */ @@ -2615595,17 +2628913,23 @@ index 0000000..5d6da9e + find it, so enable it in that case. */ + if (pe_use_coff_long_section_names < 0 && link_info.strip == strip_none) + { -+ /* Iterate over all sections of all input BFDs, checking -+ for any that begin 'debug_' and are long names. */ -+ LANG_FOR_EACH_INPUT_STATEMENT (is) ++ if (link_info.relocatable) ++ pe_use_coff_long_section_names = 1; ++ else + { -+ int found_debug = 0; -+ bfd_map_over_sections (is->the_bfd, debug_section_p, &found_debug); -+ if (found_debug) -+ { -+ pe_use_coff_long_section_names = 1; -+ break; -+ } ++ /* Iterate over all sections of all input BFDs, checking ++ for any that begin 'debug_' and are long names. */ ++ LANG_FOR_EACH_INPUT_STATEMENT (is) ++ { ++ int found_debug = 0; ++ ++ bfd_map_over_sections (is->the_bfd, debug_section_p, &found_debug); ++ if (found_debug) ++ { ++ pe_use_coff_long_section_names = 1; ++ break; ++ } ++ } + } + } + @@ -2616432,7 +2629756,7 @@ index 0000000..5d6da9e + unsigned int i; + + -+ if (! entry->flags.maybe_archive) ++ if (! entry->flags.maybe_archive || entry->flags.full_name_provided) + return FALSE; + + filename = entry->filename; @@ -2616558,15 +2629882,16 @@ index 0000000..5d6da9e + gld_${EMULATION_NAME}_list_options, + gld_${EMULATION_NAME}_recognized_file, + gld_${EMULATION_NAME}_find_potential_libraries, -+ NULL /* new_vers_pattern. */ ++ NULL, /* new_vers_pattern. */ ++ NULL /* extra_map_file_text. */ +}; +EOF diff --git a/ld/emultempl/pep.em b/ld/emultempl/pep.em new file mode 100644 -index 0000000..b738800 +index 0000000..1f78655 --- /dev/null +++ b/ld/emultempl/pep.em -@@ -0,0 +1,2010 @@ +@@ -0,0 +1,2219 @@ +# This shell script emits a C file. -*- C -*- +# It does some substitutions. +if [ -z "$MACHINE" ]; then @@ -2616587,7 +2629912,7 @@ index 0000000..b738800 +rm -f e${EMULATION_NAME}.c +(echo;echo;echo;echo;echo)>e${EMULATION_NAME}.c # there, now line numbers match ;-) +fragment <name, sizeof (".debug_") - 1) == 0) + *found = 1; +} + ++static bfd_boolean ++pecoff_checksum_contents (bfd *abfd, ++ void (*process) (const void *, size_t, void *), ++ void *arg) ++{ ++ file_ptr filepos = (file_ptr) 0; ++ ++ while (1) ++ { ++ unsigned char b; ++ int status; ++ ++ if (bfd_seek (abfd, filepos, SEEK_SET) != 0) ++ return 0; ++ ++ status = bfd_bread (&b, (bfd_size_type) 1, abfd); ++ if (status < 1) ++ { ++ break; ++ } ++ ++ (*process) (&b, 1, arg); ++ filepos += 1; ++ } ++ ++ return TRUE; ++} ++ ++static bfd_boolean ++write_build_id (bfd *abfd) ++{ ++ struct pe_tdata *t = pe_data (abfd); ++ asection *asec; ++ struct bfd_link_order *link_order = NULL; ++ unsigned char *contents; ++ bfd_size_type size; ++ bfd_size_type build_id_size; ++ unsigned char *build_id; ++ ++ /* Find the section the .build-id output section has been merged info. */ ++ for (asec = abfd->sections; asec != NULL; asec = asec->next) ++ { ++ struct bfd_link_order *l = NULL; ++ for (l = asec->map_head.link_order; l != NULL; l = l->next) ++ { ++ if ((l->type == bfd_indirect_link_order)) ++ { ++ if (l->u.indirect.section == t->build_id.sec) ++ { ++ link_order = l; ++ break; ++ } ++ } ++ } ++ ++ if (link_order) ++ break; ++ } ++ ++ if (!link_order) ++ { ++ einfo (_("%P: warning: .build-id section discarded," ++ " --build-id ignored.\n")); ++ return TRUE; ++ } ++ ++ if (t->build_id.sec->contents == NULL) ++ t->build_id.sec->contents = (unsigned char *) xmalloc (t->build_id.sec->size); ++ contents = t->build_id.sec->contents; ++ size = t->build_id.sec->size; ++ ++ build_id_size = compute_build_id_size (t->build_id.style); ++ build_id = xmalloc (build_id_size); ++ generate_build_id (abfd, t->build_id.style, pecoff_checksum_contents, build_id, build_id_size); ++ ++ bfd_vma ib = pe_data (link_info.output_bfd)->pe_opthdr.ImageBase; ++ ++ /* Construct a debug directory entry which points to an immediately following CodeView record. */ ++ struct internal_IMAGE_DEBUG_DIRECTORY idd; ++ idd.Characteristics = 0; ++ idd.TimeDateStamp = 0; ++ idd.MajorVersion = 0; ++ idd.MinorVersion = 0; ++ idd.Type = PE_IMAGE_DEBUG_TYPE_CODEVIEW; ++ idd.SizeOfData = sizeof (CV_INFO_PDB70) + 1; ++ idd.AddressOfRawData = asec->vma - ib + link_order->offset ++ + sizeof (struct external_IMAGE_DEBUG_DIRECTORY); ++ idd.PointerToRawData = asec->filepos + link_order->offset ++ + sizeof (struct external_IMAGE_DEBUG_DIRECTORY); ++ ++ struct external_IMAGE_DEBUG_DIRECTORY *ext = (struct external_IMAGE_DEBUG_DIRECTORY *)contents; ++ _bfd_XXi_swap_debugdir_out (abfd, &idd, ext); ++ ++ /* Write the debug directory enttry */ ++ if (bfd_seek (abfd, asec->filepos + link_order->offset, SEEK_SET) != 0) ++ return 0; ++ ++ if ((bfd_bwrite (contents, size, abfd) != size)) ++ return 0; ++ ++ /* Construct the CodeView record. */ ++ CODEVIEW_INFO cvinfo; ++ cvinfo.CVSignature = CVINFO_PDB70_CVSIGNATURE; ++ cvinfo.Age = 1; ++ ++ /* Zero pad or truncate the generated build_id to fit in the CodeView record. */ ++ memset (&(cvinfo.Signature), 0, CV_INFO_SIGNATURE_LENGTH); ++ memcpy (&(cvinfo.Signature), build_id, (build_id_size > CV_INFO_SIGNATURE_LENGTH) ++ ? CV_INFO_SIGNATURE_LENGTH : build_id_size); ++ ++ free (build_id); ++ ++ /* Write the codeview record. */ ++ if (_bfd_XXi_write_codeview_record (abfd, idd.PointerToRawData, &cvinfo) == 0) ++ return 0; ++ ++ /* Record the location of the debug directory in the data directory. */ ++ pe_data (link_info.output_bfd)->pe_opthdr.DataDirectory[PE_DEBUG_DATA].VirtualAddress ++ = asec->vma - ib + link_order->offset; ++ pe_data (link_info.output_bfd)->pe_opthdr.DataDirectory[PE_DEBUG_DATA].Size ++ = sizeof (struct external_IMAGE_DEBUG_DIRECTORY); ++ ++ return TRUE; ++} ++ ++/* Make .build-id section, and set up coff_tdata->build_id. */ ++static bfd_boolean ++setup_build_id (bfd *ibfd) ++{ ++ asection *s; ++ flagword flags; ++ ++ if (!validate_build_id_style (emit_build_id)) ++ { ++ einfo ("%P: warning: unrecognized --build-id style ignored.\n"); ++ return FALSE; ++ } ++ ++ flags = (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_IN_MEMORY ++ | SEC_LINKER_CREATED | SEC_READONLY | SEC_DATA); ++ s = bfd_make_section_anyway_with_flags (ibfd, ".build-id", flags); ++ if (s != NULL) ++ { ++ struct pe_tdata *t = pe_data (link_info.output_bfd); ++ t->build_id.after_write_object_contents = &write_build_id; ++ t->build_id.style = emit_build_id; ++ t->build_id.sec = s; ++ ++ /* Section is a fixed size: ++ One IMAGE_DEBUG_DIRECTORY entry, of type IMAGE_DEBUG_TYPE_CODEVIEW, ++ pointing at a CV_INFO_PDB70 record containing the build-id, with a ++ null byte for PdbFileName. */ ++ s->size = sizeof (struct external_IMAGE_DEBUG_DIRECTORY) ++ + sizeof (CV_INFO_PDB70) + 1; ++ ++ return TRUE; ++ } ++ ++ einfo ("%P: warning: Cannot create .build-id section," ++ " --build-id ignored.\n"); ++ return FALSE; ++} ++ +static void +gld_${EMULATION_NAME}_after_open (void) +{ @@ -2617783,6 +2631290,26 @@ index 0000000..b738800 + } +#endif + ++ if (emit_build_id != NULL) ++ { ++ bfd *abfd; ++ ++ /* Find a COFF input. */ ++ for (abfd = link_info.input_bfds; ++ abfd != (bfd *) NULL; abfd = abfd->link_next) ++ if (bfd_get_flavour (abfd) == bfd_target_coff_flavour) ++ break; ++ ++ /* If there are no COFF input files do not try to ++ add a build-id section. */ ++ if (abfd == NULL ++ || !setup_build_id (abfd)) ++ { ++ free ((char *) emit_build_id); ++ emit_build_id = NULL; ++ } ++ } ++ + /* Pass the wacky PE command line options into the output bfd. + FIXME: This should be done via a function, rather than by + including an internal BFD header. */ @@ -2617805,17 +2631332,23 @@ index 0000000..b738800 + find it, so enable it in that case. */ + if (pep_use_coff_long_section_names < 0 && link_info.strip == strip_none) + { -+ /* Iterate over all sections of all input BFDs, checking -+ for any that begin 'debug_' and are long names. */ -+ LANG_FOR_EACH_INPUT_STATEMENT (is) ++ if (link_info.relocatable) ++ pep_use_coff_long_section_names = 1; ++ else + { -+ int found_debug = 0; -+ bfd_map_over_sections (is->the_bfd, debug_section_p, &found_debug); -+ if (found_debug) -+ { -+ pep_use_coff_long_section_names = 1; -+ break; -+ } ++ /* Iterate over all sections of all input BFDs, checking ++ for any that begin 'debug_' and are long names. */ ++ LANG_FOR_EACH_INPUT_STATEMENT (is) ++ { ++ int found_debug = 0; ++ ++ bfd_map_over_sections (is->the_bfd, debug_section_p, &found_debug); ++ if (found_debug) ++ { ++ pep_use_coff_long_section_names = 1; ++ break; ++ } ++ } + } + } + @@ -2618448,7 +2631981,7 @@ index 0000000..b738800 + unsigned int i; + + -+ if (! entry->flags.maybe_archive) ++ if (! entry->flags.maybe_archive || entry->flags.full_name_provided) + return FALSE; + + filename = entry->filename; @@ -2618574,18 +2632107,18 @@ index 0000000..b738800 + gld_${EMULATION_NAME}_list_options, + gld_${EMULATION_NAME}_recognized_file, + gld_${EMULATION_NAME}_find_potential_libraries, -+ NULL /* new_vers_pattern. */ ++ NULL, /* new_vers_pattern. */ ++ NULL /* extra_map_file_text */ +}; +EOF diff --git a/ld/emultempl/ppc32elf.em b/ld/emultempl/ppc32elf.em new file mode 100644 -index 0000000..6843770 +index 0000000..0e2af12 --- /dev/null +++ b/ld/emultempl/ppc32elf.em -@@ -0,0 +1,251 @@ +@@ -0,0 +1,348 @@ +# This shell script emits a C file. -*- C -*- -+# Copyright 2003, 2005, 2007, 2008, 2009, 2010, 2011, 2012 -+# Free Software Foundation, Inc. ++# Copyright (C) 2003-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2618613,6 +2632146,7 @@ index 0000000..6843770 +#include "libbfd.h" +#include "elf32-ppc.h" +#include "ldlex.h" ++#include "ldlang.h" + +#define is_ppc_elf(bfd) \ + (bfd_get_flavour (bfd) == bfd_target_elf_flavour \ @@ -2618620,15 +2632154,30 @@ index 0000000..6843770 + +/* Whether to run tls optimization. */ +static int notlsopt = 0; -+static int no_tls_get_addr_opt = 0; + -+/* Whether to emit symbols for stubs. */ -+static int emit_stub_syms = -1; -+ -+/* Chooses the correct place for .plt and .got. */ -+static enum ppc_elf_plt_type plt_style = PLT_UNSET; ++/* Choose the correct place for .got. */ +static int old_got = 0; + ++static bfd_vma pagesize = 0; ++ ++static struct ppc_elf_params params = { PLT_UNSET, -1, 0, 0, 0, 0 }; ++ ++static void ++ppc_after_open_output (void) ++{ ++ if (params.emit_stub_syms < 0) ++ params.emit_stub_syms = link_info.emitrelocations || link_info.shared; ++ if (pagesize == 0) ++ pagesize = config.commonpagesize; ++ params.pagesize_p2 = bfd_log2 (pagesize); ++ ppc_elf_link_params (&link_info, ¶ms); ++} ++ ++EOF ++ ++# No --secure-plt, --bss-plt, or --sdata-got for vxworks. ++if test -z "$VXWORKS_BASE_EM_FILE" ; then ++ fragment <vma + o->rawsize - 1; + } + if (high > low && high - low > (1 << 25) - 1) -+ ENABLE_RELAXATION; ++ params.branch_trampolines = 1; + } ++ ++ if (params.ppc476_workaround || params.branch_trampolines) ++ ENABLE_RELAXATION; ++} ++ ++/* Replaces default zero fill padding in executable sections with ++ "ba 0" instructions. This works around the ppc476 icache bug if we ++ have a function pointer tail call near the end of a page, some ++ small amount of padding, then the function called at the beginning ++ of the next page. If the "ba 0" is ever executed we should hit a ++ segv, so it's almost as good as an illegal instruction (zero). */ ++ ++static void ++no_zero_padding (lang_statement_union_type *l) ++{ ++ if (l->header.type == lang_padding_statement_enum ++ && l->padding_statement.size != 0 ++ && l->padding_statement.output_section != NULL ++ && (l->padding_statement.output_section->flags & SEC_CODE) != 0 ++ && l->padding_statement.fill->size == 0) ++ { ++ struct _ppc_fill_type ++ { ++ size_t size; ++ unsigned char data[4]; ++ }; ++ static struct _ppc_fill_type fill_be = { 4, {0x48, 0, 0, 2} }; ++ static struct _ppc_fill_type fill_le = { 4, {2, 0, 0, 0x48} }; ++ ++ if (bfd_big_endian (link_info.output_bfd)) ++ l->padding_statement.fill = (struct _fill_type *) &fill_be; ++ else ++ l->padding_statement.fill = (struct _fill_type *) &fill_le; ++ } ++} ++ ++static void ++ppc_finish (void) ++{ ++ if (params.ppc476_workaround) ++ lang_for_each_statement (no_zero_padding); ++ finish_default (); +} + +EOF @@ -2618771,16 +2632366,24 @@ index 0000000..6843770 +#define OPTION_OLD_GOT (OPTION_OLD_PLT + 1) +#define OPTION_STUBSYMS (OPTION_OLD_GOT + 1) +#define OPTION_NO_STUBSYMS (OPTION_STUBSYMS + 1) ++#define OPTION_PPC476_WORKAROUND (OPTION_NO_STUBSYMS + 1) ++#define OPTION_NO_PPC476_WORKAROUND (OPTION_PPC476_WORKAROUND + 1) +' + +PARSE_AND_LIST_LONGOPTS=${PARSE_AND_LIST_LONGOPTS}' + { "emit-stub-syms", no_argument, NULL, OPTION_STUBSYMS }, + { "no-emit-stub-syms", no_argument, NULL, OPTION_NO_STUBSYMS }, + { "no-tls-optimize", no_argument, NULL, OPTION_NO_TLS_OPT }, -+ { "no-tls-get-addr-optimize", no_argument, NULL, OPTION_NO_TLS_GET_ADDR_OPT }, ++ { "no-tls-get-addr-optimize", no_argument, NULL, OPTION_NO_TLS_GET_ADDR_OPT },' ++if test -z "$VXWORKS_BASE_EM_FILE" ; then ++ PARSE_AND_LIST_LONGOPTS=${PARSE_AND_LIST_LONGOPTS}' + { "secure-plt", no_argument, NULL, OPTION_NEW_PLT }, + { "bss-plt", no_argument, NULL, OPTION_OLD_PLT }, -+ { "sdata-got", no_argument, NULL, OPTION_OLD_GOT }, ++ { "sdata-got", no_argument, NULL, OPTION_OLD_GOT },' ++fi ++PARSE_AND_LIST_LONGOPTS=${PARSE_AND_LIST_LONGOPTS}' ++ { "ppc476-workaround", optional_argument, NULL, OPTION_PPC476_WORKAROUND }, ++ { "no-ppc476-workaround", no_argument, NULL, OPTION_NO_PPC476_WORKAROUND }, +' + +PARSE_AND_LIST_OPTIONS=${PARSE_AND_LIST_OPTIONS}' @@ -2618788,20 +2632391,27 @@ index 0000000..6843770 + --emit-stub-syms Label linker stubs with a symbol.\n\ + --no-emit-stub-syms Don'\''t label linker stubs with a symbol.\n\ + --no-tls-optimize Don'\''t try to optimize TLS accesses.\n\ -+ --no-tls-get-addr-optimize Don'\''t use a special __tls_get_addr call.\n\ ++ --no-tls-get-addr-optimize Don'\''t use a special __tls_get_addr call.\n' ++if test -z "$VXWORKS_BASE_EM_FILE" ; then ++ PARSE_AND_LIST_OPTIONS=${PARSE_AND_LIST_OPTIONS}'\ + --secure-plt Use new-style PLT if possible.\n\ + --bss-plt Force old-style BSS PLT.\n\ -+ --sdata-got Force GOT location just before .sdata.\n" ++ --sdata-got Force GOT location just before .sdata.\n' ++fi ++PARSE_AND_LIST_OPTIONS=${PARSE_AND_LIST_OPTIONS}'\ ++ --ppc476-workaround [=pagesize]\n\ ++ Avoid a cache bug on ppc476.\n\ ++ --no-ppc476-workaround Disable workaround.\n" + )); +' + +PARSE_AND_LIST_ARGS_CASES=${PARSE_AND_LIST_ARGS_CASES}' + case OPTION_STUBSYMS: -+ emit_stub_syms = 1; ++ params.emit_stub_syms = 1; + break; + + case OPTION_NO_STUBSYMS: -+ emit_stub_syms = 0; ++ params.emit_stub_syms = 0; + break; + + case OPTION_NO_TLS_OPT: @@ -2618809,15 +2632419,15 @@ index 0000000..6843770 + break; + + case OPTION_NO_TLS_GET_ADDR_OPT: -+ no_tls_get_addr_opt = 1; ++ params.no_tls_get_addr_opt = 1; + break; + + case OPTION_NEW_PLT: -+ plt_style = PLT_NEW; ++ params.plt_style = PLT_NEW; + break; + + case OPTION_OLD_PLT: -+ plt_style = PLT_OLD; ++ params.plt_style = PLT_OLD; + break; + + case OPTION_OLD_GOT: @@ -2618826,23 +2632436,43 @@ index 0000000..6843770 + + case OPTION_TRADITIONAL_FORMAT: + notlsopt = 1; -+ no_tls_get_addr_opt = 1; ++ params.no_tls_get_addr_opt = 1; + return FALSE; ++ ++ case OPTION_PPC476_WORKAROUND: ++ params.ppc476_workaround = 1; ++ if (optarg != NULL) ++ { ++ char *end; ++ pagesize = strtoul (optarg, &end, 0); ++ if (*end ++ || (pagesize < 4096 && pagesize != 0) ++ || pagesize != (pagesize & -pagesize)) ++ einfo (_("%P%F: invalid pagesize `%s'\''\n"), optarg); ++ } ++ break; ++ ++ case OPTION_NO_PPC476_WORKAROUND: ++ params.ppc476_workaround = 0; ++ break; +' + +# Put these extra ppc32elf routines in ld_${EMULATION_NAME}_emulation +# -+LDEMUL_AFTER_OPEN=ppc_after_open ++LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS=ppc_after_open_output ++if test -z "$VXWORKS_BASE_EM_FILE" ; then ++ LDEMUL_AFTER_OPEN=ppc_after_open ++fi +LDEMUL_BEFORE_ALLOCATION=ppc_before_allocation ++LDEMUL_FINISH=ppc_finish diff --git a/ld/emultempl/ppc64elf.em b/ld/emultempl/ppc64elf.em new file mode 100644 -index 0000000..f2085d7 +index 0000000..78faf68 --- /dev/null +++ b/ld/emultempl/ppc64elf.em -@@ -0,0 +1,871 @@ +@@ -0,0 +1,874 @@ +# This shell script emits a C file. -*- C -*- -+# Copyright 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 -+# Free Software Foundation, Inc. ++# Copyright (C) 2002-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2618873,6 +2632503,16 @@ index 0000000..f2085d7 +#include "elf64-ppc.h" +#include "ldlex.h" + ++static asection *ppc_add_stub_section (const char *, asection *); ++static void ppc_layout_sections_again (void); ++ ++static struct ppc64_elf_params params = { NULL, ++ &ppc_add_stub_section, ++ &ppc_layout_sections_again, ++ 1, 0, 0, ++ ${DEFAULT_PLT_STATIC_CHAIN-0}, -1, 0, ++ 0, -1, -1}; ++ +/* Fake input file for stubs. */ +static lang_input_statement_type *stub_file; +static int stub_added = 0; @@ -2618880,17 +2632520,11 @@ index 0000000..f2085d7 +/* Whether we need to call ppc_layout_sections_again. */ +static int need_laying_out = 0; + -+/* Maximum size of a group of input sections that can be handled by -+ one stub section. A value of +/-1 indicates the bfd back-end -+ should use a suitable default size. */ -+static bfd_signed_vma group_size = 1; -+ +/* Whether to add ".foo" entries for each "foo" in a version script. */ +static int dotsyms = 1; + +/* Whether to run tls optimization. */ +static int no_tls_opt = 0; -+static int no_tls_get_addr_opt = 0; + +/* Whether to run opd optimization. */ +static int no_opd_opt = 0; @@ -2618898,30 +2632532,14 @@ index 0000000..f2085d7 +/* Whether to run toc optimization. */ +static int no_toc_opt = 0; + -+/* Whether to allow multiple toc sections. */ -+static int no_multi_toc = 0; -+ +/* Whether to sort input toc and got sections. */ +static int no_toc_sort = 0; + -+/* Set if PLT call stubs should load r11. */ -+static int plt_static_chain = ${DEFAULT_PLT_STATIC_CHAIN-0}; -+ -+/* Set if PLT call stubs need to be thread safe on power7+. */ -+static int plt_thread_safe = -1; -+ +/* Set if individual PLT call stubs should be aligned. */ +static int plt_stub_align = 0; + -+/* Whether to emit symbols for stubs. */ -+static int emit_stub_syms = -1; -+ +static asection *toc_section = 0; + -+/* Whether to canonicalize .opd so that there are no overlapping -+ .opd entries. */ -+static int non_overlapping_opd = 0; -+ +/* This is called before the input files are opened. We create a new + fake input file to hold the stub sections. */ + @@ -2618949,7 +2632567,10 @@ index 0000000..f2085d7 + + stub_file->the_bfd->flags |= BFD_LINKER_CREATED; + ldlang_add_file (stub_file); -+ if (!ppc64_elf_init_stub_bfd (stub_file->the_bfd, &link_info)) ++ params.stub_bfd = stub_file->the_bfd; ++ if (params.save_restore_funcs < 0) ++ params.save_restore_funcs = !link_info.relocatable; ++ if (!ppc64_elf_init_stub_bfd (&link_info, ¶ms)) + einfo ("%F%P: can not init BFD: %E\n"); +} + @@ -2619098,10 +2632719,10 @@ index 0000000..f2085d7 + if (stub_file != NULL) + { + if (!no_opd_opt -+ && !ppc64_elf_edit_opd (&link_info, non_overlapping_opd)) ++ && !ppc64_elf_edit_opd (&link_info)) + einfo ("%X%P: can not edit %s: %E\n", "opd"); + -+ if (ppc64_elf_tls_setup (&link_info, no_tls_get_addr_opt, &no_multi_toc) ++ if (ppc64_elf_tls_setup (&link_info) + && !no_tls_opt) + { + /* Size the sections. This is premature, but we want to know the @@ -2619220,7 +2632841,6 @@ index 0000000..f2085d7 + asection *stub_sec; + flagword flags; + asection *output_section; -+ const char *secname; + lang_output_section_statement_type *os; + struct hook_stub_info info; + @@ -2619234,8 +2632854,7 @@ index 0000000..f2085d7 + goto err_ret; + + output_section = input_section->output_section; -+ secname = bfd_get_section_name (output_section->owner, output_section); -+ os = lang_output_section_find (secname); ++ os = lang_output_section_get (output_section); + + info.input_section = input_section; + lang_list_init (&info.add); @@ -2619324,16 +2632943,14 @@ index 0000000..f2085d7 + stubs. */ + if (stub_file != NULL && !link_info.relocatable) + { -+ int ret = ppc64_elf_setup_section_lists (&link_info, -+ &ppc_add_stub_section, -+ &ppc_layout_sections_again); ++ int ret = ppc64_elf_setup_section_lists (&link_info); + if (ret < 0) + einfo ("%X%P: can not size stub section: %E\n"); + else if (ret > 0) + { + ppc64_elf_start_multitoc_partition (&link_info); + -+ if (!no_multi_toc) ++ if (!params.no_multi_toc) + { + toc_section = bfd_get_section_by_name (link_info.output_bfd, + ".got"); @@ -2619342,7 +2632959,7 @@ index 0000000..f2085d7 + } + + if (ppc64_elf_layout_multitoc (&link_info) -+ && !no_multi_toc ++ && !params.no_multi_toc + && toc_section != NULL) + lang_for_each_statement (build_toc_list); + @@ -2619354,9 +2632971,7 @@ index 0000000..f2085d7 + einfo ("%P: .init/.fini fragments use differing TOC pointers\n"); + + /* Call into the BFD backend to do the real work. */ -+ if (!ppc64_elf_size_stubs (&link_info, group_size, -+ plt_static_chain, plt_thread_safe, -+ plt_stub_align)) ++ if (!ppc64_elf_size_stubs (&link_info)) + einfo ("%X%P: can not size stub section: %E\n"); + } + } @@ -2619386,10 +2633001,9 @@ index 0000000..f2085d7 + char *msg = NULL; + char *line, *endline; + -+ if (emit_stub_syms < 0) -+ emit_stub_syms = 1; -+ if (!ppc64_elf_build_stubs (emit_stub_syms, &link_info, -+ config.stats ? &msg : NULL)) ++ if (params.emit_stub_syms < 0) ++ params.emit_stub_syms = 1; ++ if (!ppc64_elf_build_stubs (&link_info, config.stats ? &msg : NULL)) + einfo ("%X%P: can not build stubs: %E\n"); + + fflush (stdout); @@ -2619506,7 +2633120,9 @@ index 0000000..f2085d7 +#define OPTION_NO_PLT_ALIGN (OPTION_PLT_ALIGN + 1) +#define OPTION_STUBSYMS (OPTION_NO_PLT_ALIGN + 1) +#define OPTION_NO_STUBSYMS (OPTION_STUBSYMS + 1) -+#define OPTION_DOTSYMS (OPTION_NO_STUBSYMS + 1) ++#define OPTION_SAVRES (OPTION_NO_STUBSYMS + 1) ++#define OPTION_NO_SAVRES (OPTION_SAVRES + 1) ++#define OPTION_DOTSYMS (OPTION_NO_SAVRES + 1) +#define OPTION_NO_DOTSYMS (OPTION_DOTSYMS + 1) +#define OPTION_NO_TLS_OPT (OPTION_NO_DOTSYMS + 1) +#define OPTION_NO_TLS_GET_ADDR_OPT (OPTION_NO_TLS_OPT + 1) @@ -2619529,6 +2633145,8 @@ index 0000000..f2085d7 + { "no-emit-stub-syms", no_argument, NULL, OPTION_NO_STUBSYMS }, + { "dotsyms", no_argument, NULL, OPTION_DOTSYMS }, + { "no-dotsyms", no_argument, NULL, OPTION_NO_DOTSYMS }, ++ { "save-restore-funcs", no_argument, NULL, OPTION_SAVRES }, ++ { "no-save-restore-funcs", no_argument, NULL, OPTION_NO_SAVRES }, + { "no-tls-optimize", no_argument, NULL, OPTION_NO_TLS_OPT }, + { "no-tls-get-addr-optimize", no_argument, NULL, OPTION_NO_TLS_GET_ADDR_OPT }, + { "no-opd-optimize", no_argument, NULL, OPTION_NO_OPD_OPT }, @@ -2619583,6 +2633201,14 @@ index 0000000..f2085d7 + --no-dotsyms Don'\''t do anything special in version scripts.\n" + )); + fprintf (file, _("\ ++ --save-restore-funcs Provide register save and restore routines used\n\ ++ by gcc -Os code. Defaults to on for normal\n\ ++ final link, off for ld -r.\n" ++ )); ++ fprintf (file, _("\ ++ --no-save-restore-funcs Don'\''t provide these routines.\n" ++ )); ++ fprintf (file, _("\ + --no-tls-optimize Don'\''t try to optimize TLS accesses.\n" + )); + fprintf (file, _("\ @@ -2619610,26 +2633236,26 @@ index 0000000..f2085d7 + case OPTION_STUBGROUP_SIZE: + { + const char *end; -+ group_size = bfd_scan_vma (optarg, &end, 0); ++ params.group_size = bfd_scan_vma (optarg, &end, 0); + if (*end) + einfo (_("%P%F: invalid number `%s'\''\n"), optarg); + } + break; + + case OPTION_PLT_STATIC_CHAIN: -+ plt_static_chain = 1; ++ params.plt_static_chain = 1; + break; + + case OPTION_NO_PLT_STATIC_CHAIN: -+ plt_static_chain = 0; ++ params.plt_static_chain = 0; + break; + + case OPTION_PLT_THREAD_SAFE: -+ plt_thread_safe = 1; ++ params.plt_thread_safe = 1; + break; + + case OPTION_NO_PLT_THREAD_SAFE: -+ plt_thread_safe = 0; ++ params.plt_thread_safe = 0; + break; + + case OPTION_PLT_ALIGN: @@ -2619650,11 +2633276,11 @@ index 0000000..f2085d7 + break; + + case OPTION_STUBSYMS: -+ emit_stub_syms = 1; ++ params.emit_stub_syms = 1; + break; + + case OPTION_NO_STUBSYMS: -+ emit_stub_syms = 0; ++ params.emit_stub_syms = 0; + break; + + case OPTION_DOTSYMS: @@ -2619665,12 +2633291,20 @@ index 0000000..f2085d7 + dotsyms = 0; + break; + ++ case OPTION_SAVRES: ++ params.save_restore_funcs = 1; ++ break; ++ ++ case OPTION_NO_SAVRES: ++ params.save_restore_funcs = 0; ++ break; ++ + case OPTION_NO_TLS_OPT: + no_tls_opt = 1; + break; + + case OPTION_NO_TLS_GET_ADDR_OPT: -+ no_tls_get_addr_opt = 1; ++ params.no_tls_get_addr_opt = 1; + break; + + case OPTION_NO_OPD_OPT: @@ -2619682,7 +2633316,7 @@ index 0000000..f2085d7 + break; + + case OPTION_NO_MULTI_TOC: -+ no_multi_toc = 1; ++ params.no_multi_toc = 1; + break; + + case OPTION_NO_TOC_SORT: @@ -2619690,17 +2633324,17 @@ index 0000000..f2085d7 + break; + + case OPTION_NON_OVERLAPPING_OPD: -+ non_overlapping_opd = 1; ++ params.non_overlapping_opd = 1; + break; + + case OPTION_TRADITIONAL_FORMAT: + no_tls_opt = 1; -+ no_tls_get_addr_opt = 1; ++ params.no_tls_get_addr_opt = 1; + no_opd_opt = 1; + no_toc_opt = 1; -+ no_multi_toc = 1; ++ params.no_multi_toc = 1; + no_toc_sort = 1; -+ plt_static_chain = 1; ++ params.plt_static_chain = 1; + return FALSE; +' + @@ -2619713,12 +2633347,12 @@ index 0000000..f2085d7 +LDEMUL_NEW_VERS_PATTERN=gld${EMULATION_NAME}_new_vers_pattern diff --git a/ld/emultempl/rxelf.em b/ld/emultempl/rxelf.em new file mode 100644 -index 0000000..f27e8e6 +index 0000000..6386abd --- /dev/null +++ b/ld/emultempl/rxelf.em -@@ -0,0 +1,88 @@ +@@ -0,0 +1,92 @@ +# This shell script emits a C file. -*- C -*- -+# Copyright 2009, 2011 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2619744,6 +2633378,8 @@ index 0000000..f27e8e6 +test -z "$TARGET2_TYPE" && TARGET2_TYPE="rel" +fragment < + + This file is part of the GNU Binutils. @@ -2620670,13 +2634307,13 @@ index 0000000..2006fe2 +0x6c,0x6c,0x5f,0x68,0x61,0x6e,0x64,0x6c,0x65,0x72,0x00, diff --git a/ld/emultempl/spu_ovl.S b/ld/emultempl/spu_ovl.S new file mode 100644 -index 0000000..509397a +index 0000000..03fecc6 --- /dev/null +++ b/ld/emultempl/spu_ovl.S @@ -0,0 +1,471 @@ +/* Overlay manager for SPU. + -+ Copyright 2006, 2007, 2008 Free Software Foundation, Inc. ++ Copyright (C) 2006-2014 Free Software Foundation, Inc. + + This file is part of the GNU Binutils. + @@ -2621254,13 +2634891,12 @@ index 0000000..c9eff93 +0x00,0x00,0x01,0x05,0x00,0x00,0x01,0xf4, diff --git a/ld/emultempl/spuelf.em b/ld/emultempl/spuelf.em new file mode 100644 -index 0000000..e14fa26 +index 0000000..1b4d72f --- /dev/null +++ b/ld/emultempl/spuelf.em @@ -0,0 +1,836 @@ +# This shell script emits a C file. -*- C -*- -+# Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2012 -+# Free Software Foundation, Inc. ++# Copyright (C) 2006-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2621350,9 +2634986,9 @@ index 0000000..e14fa26 +static int +is_spu_target (void) +{ -+ extern const bfd_target bfd_elf32_spu_vec; ++ extern const bfd_target spu_elf32_vec; + -+ return link_info.output_bfd->xvec == &bfd_elf32_spu_vec; ++ return link_info.output_bfd->xvec == &spu_elf32_vec; +} + +/* Create our note section. */ @@ -2621398,8 +2635034,9 @@ index 0000000..e14fa26 + lang_output_section_statement_type *os; + + if (o != NULL) -+ output_name = o->name; -+ os = lang_output_section_find (output_name); ++ os = lang_output_section_get (o); ++ else ++ os = lang_output_section_find (output_name); + if (os == NULL) + { + os = gld${EMULATION_NAME}_place_orphan (s, output_name, 0); @@ -2621707,7 +2635344,7 @@ index 0000000..e14fa26 + +if grep -q 'ld_elf.*ppc.*_emulation' ldemul-list.h; then + fragment < ++#include "safe-ctype.h" +#include "filenames.h" +#include "libiberty.h" + @@ -2622096,10 +2635733,10 @@ index 0000000..e14fa26 +LDEMUL_CHOOSE_TARGET=gld${EMULATION_NAME}_choose_target diff --git a/ld/emultempl/sunos.em b/ld/emultempl/sunos.em new file mode 100644 -index 0000000..af11027 +index 0000000..e57e1f0 --- /dev/null +++ b/ld/emultempl/sunos.em -@@ -0,0 +1,1040 @@ +@@ -0,0 +1,1039 @@ +# This shell script emits a C file. -*- C -*- +# It does some substitutions. +if [ -z "$MACHINE" ]; then @@ -2622111,9 +2635748,7 @@ index 0000000..af11027 +/* This file is is generated by a shell script. DO NOT EDIT! */ + +/* SunOS emulation code for ${EMULATION_NAME} -+ Copyright 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, -+ 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + Written by Steve Chamberlain + SunOS shared library support by Ian Lance Taylor + @@ -2623062,7 +2636697,7 @@ index 0000000..af11027 +gld${EMULATION_NAME}_get_script (int *isfile) +EOF + -+if test -n "$COMPILE_IN" ++if test x"$COMPILE_IN" = xyes +then +# Scripts compiled in. + @@ -2623137,17 +2636772,18 @@ index 0000000..af11027 + NULL, /* list options */ + NULL, /* recognized file */ + NULL, /* find_potential_libraries */ -+ NULL /* new_vers_pattern */ ++ NULL, /* new_vers_pattern */ ++ NULL /* extra_map_file_text */ +}; +EOF diff --git a/ld/emultempl/tic6xdsbt.em b/ld/emultempl/tic6xdsbt.em new file mode 100644 -index 0000000..01923b3 +index 0000000..ca957c4 --- /dev/null +++ b/ld/emultempl/tic6xdsbt.em @@ -0,0 +1,207 @@ +# This shell script emits a C file. -*- C -*- -+# Copyright 2011, 2012 Free Software Foundation, Inc. ++# Copyright (C) 2011-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2623184,19 +2636820,19 @@ index 0000000..01923b3 +static int +is_tic6x_target (void) +{ -+ extern const bfd_target bfd_elf32_tic6x_le_vec; -+ extern const bfd_target bfd_elf32_tic6x_be_vec; -+ extern const bfd_target bfd_elf32_tic6x_linux_le_vec; -+ extern const bfd_target bfd_elf32_tic6x_linux_be_vec; -+ extern const bfd_target bfd_elf32_tic6x_elf_le_vec; -+ extern const bfd_target bfd_elf32_tic6x_elf_be_vec; ++ extern const bfd_target tic6x_elf32_le_vec; ++ extern const bfd_target tic6x_elf32_be_vec; ++ extern const bfd_target tic6x_elf32_linux_le_vec; ++ extern const bfd_target tic6x_elf32_linux_be_vec; ++ extern const bfd_target tic6x_elf32_c6000_le_vec; ++ extern const bfd_target tic6x_elf32_c6000_be_vec; + -+ return (link_info.output_bfd->xvec == &bfd_elf32_tic6x_le_vec -+ || link_info.output_bfd->xvec == &bfd_elf32_tic6x_be_vec -+ || link_info.output_bfd->xvec == &bfd_elf32_tic6x_linux_le_vec -+ || link_info.output_bfd->xvec == &bfd_elf32_tic6x_linux_be_vec -+ || link_info.output_bfd->xvec == &bfd_elf32_tic6x_elf_le_vec -+ || link_info.output_bfd->xvec == &bfd_elf32_tic6x_elf_be_vec); ++ return (link_info.output_bfd->xvec == &tic6x_elf32_le_vec ++ || link_info.output_bfd->xvec == &tic6x_elf32_be_vec ++ || link_info.output_bfd->xvec == &tic6x_elf32_linux_le_vec ++ || link_info.output_bfd->xvec == &tic6x_elf32_linux_be_vec ++ || link_info.output_bfd->xvec == &tic6x_elf32_c6000_le_vec ++ || link_info.output_bfd->xvec == &tic6x_elf32_c6000_be_vec); +} + +/* Pass params to backend. */ @@ -2623355,7 +2636991,7 @@ index 0000000..01923b3 +LDEMUL_AFTER_ALLOCATION=gld${EMULATION_NAME}_after_allocation diff --git a/ld/emultempl/ticoff.em b/ld/emultempl/ticoff.em new file mode 100644 -index 0000000..dff1d70 +index 0000000..c403d56 --- /dev/null +++ b/ld/emultempl/ticoff.em @@ -0,0 +1,186 @@ @@ -2623364,8 +2637000,7 @@ index 0000000..dff1d70 +(echo;echo;echo;echo)>e${EMULATION_NAME}.c # there, now line numbers match ;-) +fragment <flags.maybe_archive) ++ if (! entry->flags.maybe_archive || entry->flags.full_name_provided) + return FALSE; + + string = (char *) xmalloc (strlen (search->name) @@ -2623884,12 +2637519,12 @@ index 0000000..30c1a16 +LDEMUL_LIST_OPTIONS=gld"$EMULATION_NAME"_list_options diff --git a/ld/emultempl/vxworks.em b/ld/emultempl/vxworks.em new file mode 100644 -index 0000000..7a21ac3 +index 0000000..4bdc088 --- /dev/null +++ b/ld/emultempl/vxworks.em @@ -0,0 +1,102 @@ +# This shell script emits a C file. -*- C -*- -+# Copyright 2006, 2007, 2008, 2010 Free Software Foundation, Inc. ++# Copyright (C) 2006-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2623992,13 +2637627,12 @@ index 0000000..7a21ac3 +done diff --git a/ld/emultempl/xtensaelf.em b/ld/emultempl/xtensaelf.em new file mode 100644 -index 0000000..1e6eb07 +index 0000000..151eea4 --- /dev/null +++ b/ld/emultempl/xtensaelf.em -@@ -0,0 +1,1962 @@ +@@ -0,0 +1,1961 @@ +# This shell script emits a C file. -*- C -*- -+# Copyright 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 -+# Free Software Foundation, Inc. ++# Copyright (C) 2003-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2625960,14 +2639594,14 @@ index 0000000..1e6eb07 +LDEMUL_BEFORE_ALLOCATION=elf_xtensa_before_allocation diff --git a/ld/emultempl/z80.em b/ld/emultempl/z80.em new file mode 100644 -index 0000000..eeb3213 +index 0000000..9411f5b --- /dev/null +++ b/ld/emultempl/z80.em @@ -0,0 +1,104 @@ +# This shell script emits C code -*- C -*- +# to keep track of the machine type of Z80 object files +# It does some substitutions. -+# Copyright 2005, 2007, 2008 Free Software Foundation, Inc. ++# Copyright (C) 2005-2014 Free Software Foundation, Inc. +# This file is part of the GNU Binutils. +# +# This program is free software; you can redistribute it and/or modify @@ -2626581,12 +2640215,11 @@ index 0000000..7c26c34 +@c End: diff --git a/ld/gen-doc.texi b/ld/gen-doc.texi new file mode 100644 -index 0000000..acc6c57 +index 0000000..2a76ae7 --- /dev/null +++ b/ld/gen-doc.texi @@ -0,0 +1,33 @@ -+@c Copyright 2012 -+@c Free Software Foundation, Inc. ++@c Copyright (C) 2012-2014 Free Software Foundation, Inc. +@c For copying conditions, see the file ld.texinfo. + +@c ------------------------------ CONFIGURATION VARS: @@ -2626605,6 +2640238,7 @@ index 0000000..acc6c57 +@set MMIX +@set MSP430 +@set NDS32 ++@set NIOSII +@set POWERPC +@set POWERPC64 +@set Renesas @@ -2626642,13 +2640276,13 @@ index 0000000..030cb7d +} diff --git a/ld/genscripts.sh b/ld/genscripts.sh new file mode 100755 -index 0000000..a4da92d +index 0000000..499607a --- /dev/null +++ b/ld/genscripts.sh -@@ -0,0 +1,436 @@ +@@ -0,0 +1,440 @@ +#!/bin/sh +# genscripts.sh - generate the ld-emulation-target specific files -+# Copyright 2004, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. ++# Copyright (C) 2004-2014 Free Software Foundation, Inc. +# +# This file is part of the Gnu Linker. +# @@ -2626681,8 +2640315,7 @@ index 0000000..a4da92d +# enable_initfini_array \ +# this_emulation \ +# optional: -+# tool_dir \ -+# customizer_script ++# tool_dir +# +# Sample usage: +# @@ -2626741,14 +2640374,9 @@ index 0000000..a4da92d +ENABLE_INITFINI_ARRAY=$2 +EMULATION_NAME=$3 +TOOL_LIB=$4 -+CUSTOMIZER_SCRIPT=$5 -+ -+if [ "x${CUSTOMIZER_SCRIPT}" = "x" ] ; then -+ CUSTOMIZER_SCRIPT=${EMULATION_NAME} -+fi -+CUSTOMIZER_SCRIPT="${srcdir}/emulparams/${CUSTOMIZER_SCRIPT}.sh" + +# Include the emulation-specific parameters: ++CUSTOMIZER_SCRIPT="${srcdir}/emulparams/${EMULATION_NAME}.sh" +. ${CUSTOMIZER_SCRIPT} + +if test -d ldscripts; then @@ -2626808,6 +2640436,7 @@ index 0000000..a4da92d + if [ "x${use_sysroot}" = "xyes" ] ; then + lib="=${lib}" + fi ++ skip_lib=no + if test -n "${LIBPATH_SUFFIX}"; then + case "${lib}" in + *${LIBPATH_SUFFIX}) @@ -2626817,18 +2640446,27 @@ index 0000000..a4da92d + *) lib_path1=${lib_path1}:${lib} ;; + esac ;; + *) -+ case :${lib_path1}: in -+ *:${lib}${LIBPATH_SUFFIX}:*) ;; -+ ::) lib_path1=${lib}${LIBPATH_SUFFIX} ;; -+ *) lib_path1=${lib_path1}:${lib}${LIBPATH_SUFFIX} ;; -+ esac ;; ++ if test -n "${LIBPATH_SUFFIX_SKIP}"; then ++ case "${lib}" in ++ *${LIBPATH_SUFFIX_SKIP}) skip_lib=yes ;; ++ esac ++ fi ++ if test "${skip_lib}" = "no"; then ++ case :${lib_path1}: in ++ *:${lib}${LIBPATH_SUFFIX}:*) ;; ++ ::) lib_path1=${lib}${LIBPATH_SUFFIX} ;; ++ *) lib_path1=${lib_path1}:${lib}${LIBPATH_SUFFIX} ;; ++ esac ++ fi ;; ++ esac ++ fi ++ if test "${skip_lib}" = "no"; then ++ case :${lib_path1}:${lib_path2}: in ++ *:${lib}:*) ;; ++ *::) lib_path2=${lib} ;; ++ *) lib_path2=${lib_path2}:${lib} ;; + esac + fi -+ case :${lib_path1}:${lib_path2}: in -+ *:${lib}:*) ;; -+ *::) lib_path2=${lib} ;; -+ *) lib_path2=${lib_path2}:${lib} ;; -+ esac + done + fi +} @@ -2627051,8 +2640689,8 @@ index 0000000..a4da92d + ) | sed -e '/^ *$/d;s/[ ]*$//' > ldscripts/${EMULATION_NAME}.xa +fi + -+case " $EMULATION_LIBPATH " in -+ *" ${EMULATION_NAME} "*) COMPILE_IN=true;; ++case "$COMPILE_IN: $EMULATION_LIBPATH " in ++ :*" ${EMULATION_NAME} "*) COMPILE_IN=yes;; +esac + +# PR ld/5652: @@ -2627084,12 +2640722,11 @@ index 0000000..a4da92d +source_em ${srcdir}/emultempl/${TEMPLATE_NAME-generic}.em diff --git a/ld/h8-doc.texi b/ld/h8-doc.texi new file mode 100644 -index 0000000..023f2cc +index 0000000..6dbca1f --- /dev/null +++ b/ld/h8-doc.texi -@@ -0,0 +1,18 @@ -+@c Copyright 2012 -+@c Free Software Foundation, Inc. +@@ -0,0 +1,17 @@ ++@c Copyright (C) 2012-2014 Free Software Foundation, Inc. +@c For copying conditions, see the file ld.texinfo. + +@c ------------------------------ CONFIGURATION VARS: @@ -2627108,14 +2640745,12 @@ index 0000000..023f2cc + diff --git a/ld/ld.h b/ld/ld.h new file mode 100644 -index 0000000..4acb721 +index 0000000..f773ce7 --- /dev/null +++ b/ld/ld.h -@@ -0,0 +1,321 @@ +@@ -0,0 +1,302 @@ +/* ld.h -- general linker header file -+ Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, -+ 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + + This file is part of the GNU Binutils. + @@ -2627218,23 +2640853,6 @@ index 0000000..4acb721 + struct wildcard_spec spec; +}; + -+struct map_symbol_def { -+ struct bfd_link_hash_entry *entry; -+ struct map_symbol_def *next; -+}; -+ -+/* The initial part of fat_user_section_struct has to be idential with -+ lean_user_section_struct. */ -+typedef struct fat_user_section_struct { -+ /* For input sections, when writing a map file: head / tail of a linked -+ list of hash table entries for symbols defined in this section. */ -+ struct map_symbol_def *map_symbol_def_head; -+ struct map_symbol_def **map_symbol_def_tail; -+ unsigned long map_symbol_def_count; -+} fat_section_userdata_type; -+ -+#define get_userdata(x) ((x)->userdata) -+ +#define BYTE_SIZE (1) +#define SHORT_SIZE (2) +#define LONG_SIZE (4) @@ -2627435,13 +2641053,13 @@ index 0000000..4acb721 +#endif diff --git a/ld/ld.texinfo b/ld/ld.texinfo new file mode 100644 -index 0000000..398dd59 +index 0000000..e3d0469 --- /dev/null +++ b/ld/ld.texinfo -@@ -0,0 +1,8041 @@ +@@ -0,0 +1,8104 @@ +\input texinfo +@setfilename ld.info -+@c Copyright 1991-2013 Free Software Foundation, Inc. ++@c Copyright (C) 1991-2014 Free Software Foundation, Inc. +@syncodeindex ky cp +@c man begin INCLUDE +@include configdoc.texi @@ -2627471,6 +2641089,7 @@ index 0000000..398dd59 +@set MMIX +@set MSP430 +@set NDS32 ++@set NIOSII +@set POWERPC +@set POWERPC64 +@set Renesas @@ -2627495,7 +2641114,7 @@ index 0000000..398dd59 +@end ifset +version @value{VERSION}. + -+Copyright @copyright{} 1991-2013 Free Software Foundation, Inc. ++Copyright @copyright{} 1991-2014 Free Software Foundation, Inc. + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License, Version 1.3 @@ -2627532,7 +2641151,7 @@ index 0000000..398dd59 + +@vskip 0pt plus 1filll +@c man begin COPYRIGHT -+Copyright @copyright{} 1991-2013 Free Software Foundation, Inc. ++Copyright @copyright{} 1991-2014 Free Software Foundation, Inc. + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License, Version 1.3 @@ -2629046,6 +2642665,9 @@ index 0000000..398dd59 +@ifset M68HC11 +@xref{M68HC11/68HC12,,@command{ld} and the 68HC11 and 68HC12}. +@end ifset ++@ifset NIOSII ++@xref{Nios II,,@command{ld} and the Altera Nios II}. ++@end ifset +@ifset POWERPC +@xref{PowerPC ELF32,,@command{ld} and PowerPC 32-bit ELF Support}. +@end ifset @@ -2629597,16 +2643219,16 @@ index 0000000..398dd59 +@kindex --build-id=@var{style} +@item --build-id +@itemx --build-id=@var{style} -+Request creation of @code{.note.gnu.build-id} ELF note section. -+The contents of the note are unique bits identifying this linked -+file. @var{style} can be @code{uuid} to use 128 random bits, -+@code{sha1} to use a 160-bit @sc{SHA1} hash on the normative -+parts of the output contents, @code{md5} to use a 128-bit -+@sc{MD5} hash on the normative parts of the output contents, or -+@code{0x@var{hexstring}} to use a chosen bit string specified as -+an even number of hexadecimal digits (@code{-} and @code{:} -+characters between digit pairs are ignored). If @var{style} is -+omitted, @code{sha1} is used. ++Request the creation of a @code{.note.gnu.build-id} ELF note section ++or a @code{.build-id} COFF section. The contents of the note are ++unique bits identifying this linked file. @var{style} can be ++@code{uuid} to use 128 random bits, @code{sha1} to use a 160-bit ++@sc{SHA1} hash on the normative parts of the output contents, ++@code{md5} to use a 128-bit @sc{MD5} hash on the normative parts of ++the output contents, or @code{0x@var{hexstring}} to use a chosen bit ++string specified as an even number of hexadecimal digits (@code{-} and ++@code{:} characters between digit pairs are ignored). If @var{style} ++is omitted, @code{sha1} is used. + +The @code{md5} and @code{sha1} styles produces an identifier +that is always the same in an identical output file, but will be @@ -2629852,11 +2643474,12 @@ index 0000000..398dd59 + +@kindex --enable-auto-image-base +@item --enable-auto-image-base -+Automatically choose the image base for DLLs, unless one is specified -+using the @code{--image-base} argument. By using a hash generated -+from the dllname to create unique image bases for each DLL, in-memory -+collisions and relocations which can delay program execution are -+avoided. ++@itemx --enable-auto-image-base=@var{value} ++Automatically choose the image base for DLLs, optionally starting with base ++@var{value}, unless one is specified using the @code{--image-base} argument. ++By using a hash generated from the dllname to create unique image bases ++for each DLL, in-memory collisions and relocations which can delay program ++execution are avoided. +[This option is specific to the i386 PE targeted port of the linker] + +@kindex --disable-auto-image-base @@ -2631224,7 +2644847,7 @@ index 0000000..398dd59 + @var{output-section-command} + @var{output-section-command} + @dots{} -+ @} [>@var{region}] [AT>@var{lma_region}] [:@var{phdr} :@var{phdr} @dots{}] [=@var{fillexp}] ++ @} [>@var{region}] [AT>@var{lma_region}] [:@var{phdr} :@var{phdr} @dots{}] [=@var{fillexp}] [,] +@end group +@end smallexample + @@ -2631232,6 +2644855,8 @@ index 0000000..398dd59 + +The whitespace around @var{section} is required, so that the section +name is unambiguous. The colon and the curly braces are also required. ++The comma at the end may be required if a @var{fillexp} is used and ++the next @var{sections-command} looks like a continuation of the expression. +The line breaks and other white space are optional. + +Each @var{output-section-command} may be one of the following: @@ -2631847,9 +2645472,9 @@ index 0000000..398dd59 +@cindex discarding sections +@cindex sections, discarding +@cindex removing sections -+The linker will not create output sections with no contents. This is -+for convenience when referring to input sections that may or may not -+be present in any of the input files. For example: ++The linker will not normally create output sections with no contents. ++This is for convenience when referring to input sections that may or ++may not be present in any of the input files. For example: +@smallexample +.foo : @{ *(.foo) @} +@end smallexample @@ -2631857,7 +2645482,12 @@ index 0000000..398dd59 +will only create a @samp{.foo} section in the output file if there is a +@samp{.foo} section in at least one input file, and if the input +sections are not all empty. Other link script directives that allocate -+space in an output section will also create the output section. ++space in an output section will also create the output section. So ++too will assignments to dot even if the assignment does not create ++space, except for @samp{. = 0}, @samp{. = . + 0}, @samp{. = sym}, ++@samp{. = . + sym} and @samp{. = ALIGN (. != 0, expr, 1)} when ++@samp{sym} is an absolute symbol of value 0 defined in the script. ++This allows you to force output of an empty section with @samp{. = .}. + +The linker will ignore address assignments (@pxref{Output Section Address}) +on discarded output sections, except when the linker script defines @@ -2632041,10 +2645671,8 @@ index 0000000..398dd59 +@cindex forcing output section alignment +@cindex output section alignment +You can increase an output section's alignment by using ALIGN. As an -+alternative you can force the output section alignment to the maximum alignment -+of all its input sections with ALIGN_WITH_INPUT. The alignment forced by -+ALIGN_WITH_INPUT is used even in case the load and virtual memory regions are -+different. ++alternative you can enforce that the difference between the VMA and LMA remains ++intact throughout this output section with the ALIGN_WITH_INPUT attribute. + +@node Forced Input Alignment +@subsubsection Forced Input Alignment @@ -2632162,7 +2645790,7 @@ index 0000000..398dd59 + @dots{} + @} [:@var{phdr}@dots{}] [=@var{fill}] + @dots{} -+ @} [>@var{region}] [:@var{phdr}@dots{}] [=@var{fill}] ++ @} [>@var{region}] [:@var{phdr}@dots{}] [=@var{fill}] [,] +@end group +@end smallexample + @@ -2632173,6 +2645801,9 @@ index 0000000..398dd59 +except that no addresses and no memory regions may be defined for +sections within an @code{OVERLAY}. + ++The comma at the end may be required if a @var{fill} is used and ++the next @var{sections-command} looks like a continuation of the expression. ++ +The sections are all defined with the same starting address. The load +addresses of the sections are arranged such that they are consecutive in +memory starting at the load address used for the @code{OVERLAY} as a @@ -2633357,13 +2646988,15 @@ index 0000000..398dd59 +@item DATA_SEGMENT_RELRO_END(@var{offset}, @var{exp}) +@kindex DATA_SEGMENT_RELRO_END(@var{offset}, @var{exp}) +This defines the end of the @code{PT_GNU_RELRO} segment when -+@samp{-z relro} option is used. Second argument is returned. ++@samp{-z relro} option is used. +When @samp{-z relro} option is not present, @code{DATA_SEGMENT_RELRO_END} +does nothing, otherwise @code{DATA_SEGMENT_ALIGN} is padded so that +@var{exp} + @var{offset} is aligned to the most commonly used page +boundary for particular target. If present in the linker script, +it must always come in between @code{DATA_SEGMENT_ALIGN} and -+@code{DATA_SEGMENT_END}. ++@code{DATA_SEGMENT_END}. Evaluates to the second argument plus any ++padding needed at the end of the @code{PT_GNU_RELRO} segment due to ++section alignment. + +@smallexample + . = DATA_SEGMENT_RELRO_END(24, .); @@ -2633539,6 +2647172,9 @@ index 0000000..398dd59 +@ifset NDS32 +* NDS32:: @command{ld} and NDS32 +@end ifset ++@ifset NIOSII ++* Nios II:: @command{ld} and the Altera Nios II ++@end ifset +@ifset POWERPC +* PowerPC ELF32:: @command{ld} and PowerPC 32-bit ELF Support +@end ifset @@ -2633686,17 +2647322,6 @@ index 0000000..398dd59 +target subroutine is a leaf routine (that is, the target subroutine does +not itself call any subroutines). + -+@cindex Cortex-A8 erratum workaround -+@kindex --fix-cortex-a8 -+@kindex --no-fix-cortex-a8 -+The @samp{--fix-cortex-a8} switch enables a link-time workaround for an erratum in certain Cortex-A8 processors. The workaround is enabled by default if you are targeting the ARM v7-A architecture profile. It can be enabled otherwise by specifying @samp{--fix-cortex-a8}, or disabled unconditionally by specifying @samp{--no-fix-cortex-a8}. -+ -+The erratum only affects Thumb-2 code. Please contact ARM for further details. -+ -+@kindex --merge-exidx-entries -+@kindex --no-merge-exidx-entries -+The @samp{--no-merge-exidx-entries} switch disables the merging of adjacent exidx entries in debuginfo. -+ +@ifclear GENERIC +@lowersections +@end ifclear @@ -2633955,6 +2647580,24 @@ index 0000000..398dd59 +only, because it relies on object files properties not present +otherwise. + ++@cindex Cortex-A8 erratum workaround ++@kindex --fix-cortex-a8 ++@kindex --no-fix-cortex-a8 ++The @samp{--fix-cortex-a8} switch enables a link-time workaround for an erratum in certain Cortex-A8 processors. The workaround is enabled by default if you are targeting the ARM v7-A architecture profile. It can be enabled otherwise by specifying @samp{--fix-cortex-a8}, or disabled unconditionally by specifying @samp{--no-fix-cortex-a8}. ++ ++The erratum only affects Thumb-2 code. Please contact ARM for further details. ++ ++@kindex --merge-exidx-entries ++@kindex --no-merge-exidx-entries ++@cindex Merging exidx entries ++The @samp{--no-merge-exidx-entries} switch disables the merging of adjacent exidx entries in debuginfo. ++ ++@kindex --long-plt ++@cindex 32-bit PLT entries ++The @samp{--long-plt} option enables the use of 16 byte PLT entries ++which support up to 4Gb of code. The default is to use 12 byte PLT ++entries which only support 512Mb of code. ++ +@ifclear GENERIC +@lowersections +@end ifclear @@ -2634177,6 +2647820,43 @@ index 0000000..398dd59 +@end ifclear +@end ifset + ++@ifset NIOSII ++@ifclear GENERIC ++@raisesections ++@end ifclear ++ ++@node Nios II ++@section @command{ld} and the Altera Nios II ++@cindex Nios II call relaxation ++@kindex --relax on Nios II ++ ++Call and immediate jump instructions on Nios II processors are limited to ++transferring control to addresses in the same 256MB memory segment, ++which may result in @command{ld} giving ++@samp{relocation truncated to fit} errors with very large programs. ++The command-line option @option{--relax} enables the generation of ++trampolines that can access the entire 32-bit address space for calls ++outside the normal @code{call} and @code{jmpi} address range. These ++trampolines are inserted at section boundaries, so may not themselves ++be reachable if an input section and its associated call trampolines are ++larger than 256MB. ++ ++The @option{--relax} option is enabled by default unless @option{-r} ++is also specified. You can disable trampoline generation by using the ++@option{--no-relax} linker option. You can also disable this optimization ++locally by using the @samp{set .noat} directive in assembly-language ++source files, as the linker-inserted trampolines use the @code{at} ++register as a temporary. ++ ++Note that the linker @option{--relax} option is independent of assembler ++relaxation options, and that using the GNU assembler's @option{-relax-all} ++option interferes with the linker's more selective call instruction relaxation. ++ ++@ifclear GENERIC ++@lowersections ++@end ifclear ++@end ifset ++ +@ifset POWERPC +@ifclear GENERIC +@raisesections @@ -2634977,6 +2648657,7 @@ index 0000000..398dd59 +tools will be able to process object files employing this GNU extension, +but will fail to respect the alignment instructions, and may issue noisy +warnings about unknown linker directives. ++ +@end table + +@ifclear GENERIC @@ -2635480,14 +2649161,223 @@ index 0000000..398dd59 +@end tex + +@bye +diff --git a/ld/ldbuildid.c b/ld/ldbuildid.c +new file mode 100644 +index 0000000..0e1a9bf +--- /dev/null ++++ b/ld/ldbuildid.c +@@ -0,0 +1,158 @@ ++/* ldbuildid.c - Build Id support routines ++ Copyright 2013, 2014 Free Software Foundation, Inc. ++ ++ This file is part of the GNU Binutils. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, write to the Free Software ++ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ++ MA 02110-1301, USA. */ ++ ++#include "sysdep.h" ++#include "bfd.h" ++#include "safe-ctype.h" ++#include "md5.h" ++#include "sha1.h" ++#include "ldbuildid.h" ++ ++#define streq(a,b) strcmp ((a), (b)) == 0 ++#define strneq(a,b,n) strncmp ((a), (b), (n)) == 0 ++ ++bfd_boolean ++validate_build_id_style (const char *style) ++{ ++ if ((streq (style, "md5")) || (streq (style, "sha1")) ++#ifndef __MINGW32__ ++ || (streq (style, "uuid")) ++#endif ++ || (strneq (style, "0x", 2))) ++ return TRUE; ++ ++ return FALSE; ++} ++ ++bfd_size_type ++compute_build_id_size (const char *style) ++{ ++ if (streq (style, "md5") || streq (style, "uuid")) ++ return 128 / 8; ++ ++ if (streq (style, "sha1")) ++ return 160 / 8; ++ ++ if (strneq (style, "0x", 2)) ++ { ++ bfd_size_type size = 0; ++ /* ID is in string form (hex). Count the bytes. */ ++ const char *id = style + 2; ++ ++ do ++ { ++ if (ISXDIGIT (id[0]) && ISXDIGIT (id[1])) ++ { ++ ++size; ++ id += 2; ++ } ++ else if (*id == '-' || *id == ':') ++ ++id; ++ else ++ { ++ size = 0; ++ break; ++ } ++ } while (*id != '\0'); ++ return size; ++ } ++ ++ return 0; ++} ++ ++static unsigned char ++read_hex (const char xdigit) ++{ ++ if (ISDIGIT (xdigit)) ++ return xdigit - '0'; ++ ++ if (ISUPPER (xdigit)) ++ return xdigit - 'A' + 0xa; ++ ++ if (ISLOWER (xdigit)) ++ return xdigit - 'a' + 0xa; ++ ++ abort (); ++ return 0; ++} ++ ++bfd_boolean ++generate_build_id (bfd *abfd, ++ const char *style, ++ checksum_fn checksum_contents, ++ unsigned char *id_bits, ++ int size ATTRIBUTE_UNUSED) ++{ ++ if (streq (style, "md5")) ++ { ++ struct md5_ctx ctx; ++ ++ md5_init_ctx (&ctx); ++ if (!(*checksum_contents) (abfd, (sum_fn) &md5_process_bytes, &ctx)) ++ return FALSE; ++ md5_finish_ctx (&ctx, id_bits); ++ } ++ else if (streq (style, "sha1")) ++ { ++ struct sha1_ctx ctx; ++ ++ sha1_init_ctx (&ctx); ++ if (!(*checksum_contents) (abfd, (sum_fn) &sha1_process_bytes, &ctx)) ++ return FALSE; ++ sha1_finish_ctx (&ctx, id_bits); ++ } ++#ifndef __MINGW32__ ++ else if (streq (style, "uuid")) ++ { ++ int n; ++ int fd = open ("/dev/urandom", O_RDONLY); ++ ++ if (fd < 0) ++ return FALSE; ++ n = read (fd, id_bits, size); ++ close (fd); ++ if (n < size) ++ return FALSE; ++ } ++#endif ++ else if (strneq (style, "0x", 2)) ++ { ++ /* ID is in string form (hex). Convert to bits. */ ++ const char *id = style + 2; ++ size_t n = 0; ++ ++ do ++ { ++ if (ISXDIGIT (id[0]) && ISXDIGIT (id[1])) ++ { ++ id_bits[n] = read_hex (*id++) << 4; ++ id_bits[n++] |= read_hex (*id++); ++ } ++ else if (*id == '-' || *id == ':') ++ ++id; ++ else ++ abort (); /* Should have been validated earlier. */ ++ } while (*id != '\0'); ++ } ++ else ++ abort (); /* Should have been validated earlier. */ ++ ++ return TRUE; ++} +diff --git a/ld/ldbuildid.h b/ld/ldbuildid.h +new file mode 100644 +index 0000000..a91ac1a +--- /dev/null ++++ b/ld/ldbuildid.h +@@ -0,0 +1,39 @@ ++/* ldbuildid.h - ++ Copyright 2013, 2014 Free Software Foundation, Inc. ++ ++ This file is part of the GNU Binutils. ++ ++ This program is free software; you can redistribute it and/or modify ++ it under the terms of the GNU General Public License as published by ++ the Free Software Foundation; either version 3 of the License, or ++ (at your option) any later version. ++ ++ This program is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, write to the Free Software ++ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ++ MA 02110-1301, USA. */ ++ ++#ifndef LDBUILDID_H ++#define LDBUILDID_H ++ ++extern bfd_boolean ++validate_build_id_style (const char *); ++ ++extern bfd_size_type ++compute_build_id_size (const char *); ++ ++typedef void (*sum_fn) (const void *, size_t, void *); ++ ++typedef bfd_boolean (*checksum_fn) (bfd *, ++ void (*) (const void *, size_t, void *), ++ void *); ++ ++extern bfd_boolean ++generate_build_id (bfd *, const char *, checksum_fn, unsigned char *, int); ++ ++#endif /* LDBUILDID_H */ diff --git a/ld/ldcref.c b/ld/ldcref.c new file mode 100644 -index 0000000..56b917d +index 0000000..19c9062 --- /dev/null +++ b/ld/ldcref.c -@@ -0,0 +1,704 @@ +@@ -0,0 +1,718 @@ +/* ldcref.c -- output a cross reference table -+ Copyright 1996-2013 Free Software Foundation, Inc. ++ Copyright (C) 1996-2014 Free Software Foundation, Inc. + Written by Ian Lance Taylor + + This file is part of the GNU Binutils. @@ -2635528,7 +2649418,8 @@ index 0000000..56b917d +/* We keep an instance of this structure for each reference to a + symbol from a given object. */ + -+struct cref_ref { ++struct cref_ref ++{ + /* The next reference. */ + struct cref_ref *next; + /* The object. */ @@ -2635543,7 +2649434,8 @@ index 0000000..56b917d + +/* We keep a hash table of symbols. Each entry looks like this. */ + -+struct cref_hash_entry { ++struct cref_hash_entry ++{ + struct bfd_hash_entry root; + /* The demangled name. */ + const char *demangled; @@ -2635553,7 +2649445,8 @@ index 0000000..56b917d + +/* This is what the hash table looks like. */ + -+struct cref_hash_table { ++struct cref_hash_table ++{ + struct bfd_hash_table root; +}; + @@ -2635597,8 +2649490,8 @@ index 0000000..56b917d +static struct bfd_hash_entry **old_table; +static unsigned int old_size; +static unsigned int old_count; -+static void *old_tab; -+static void *alloc_mark; ++static void * old_tab; ++static void * alloc_mark; +static size_t tabsize, entsize, refsize; +static size_t old_symcount; + @@ -2635836,7 +2649729,10 @@ index 0000000..56b917d + const struct cref_hash_entry * const *p2 = + (const struct cref_hash_entry * const *) a2; + -+ return strcmp ((*p1)->demangled, (*p2)->demangled); ++ if (demangling) ++ return strcmp ((*p1)->demangled, (*p2)->demangled); ++ else ++ return strcmp ((*p1)->root.string, (*p2)->root.string); +} + +/* Write out the cref table. */ @@ -2635914,8 +2649810,16 @@ index 0000000..56b917d + } + } + -+ fprintf (fp, "%s ", h->demangled); -+ len = strlen (h->demangled) + 1; ++ if (demangling) ++ { ++ fprintf (fp, "%s ", h->demangled); ++ len = strlen (h->demangled) + 1; ++ } ++ else ++ { ++ fprintf (fp, "%s ", h->root.string); ++ len = strlen (h->root.string) + 1; ++ } + + for (r = h->refs; r != NULL; r = r->next) + { @@ -2636192,14 +2650096,12 @@ index 0000000..56b917d +} diff --git a/ld/ldctor.c b/ld/ldctor.c new file mode 100644 -index 0000000..b29c1e0 +index 0000000..610a82c --- /dev/null +++ b/ld/ldctor.c -@@ -0,0 +1,378 @@ +@@ -0,0 +1,376 @@ +/* ldctor.c -- constructor support routines -+ Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, -+ 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2011 -+ Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + By Steve Chamberlain + + This file is part of the GNU Binutils. @@ -2636576,13 +2650478,12 @@ index 0000000..b29c1e0 +} diff --git a/ld/ldctor.h b/ld/ldctor.h new file mode 100644 -index 0000000..27edc61 +index 0000000..7cd0c84 --- /dev/null +++ b/ld/ldctor.h -@@ -0,0 +1,60 @@ +@@ -0,0 +1,59 @@ +/* ldctor.h - linker constructor support -+ Copyright 1991, 1992, 1993, 1994, 1995, 1998, 2000, 2002, 2003, 2005, -+ 2007, 2008 Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + + This file is part of the GNU Binutils. + @@ -2636642,14 +2650543,12 @@ index 0000000..27edc61 +#endif diff --git a/ld/ldemul.c b/ld/ldemul.c new file mode 100644 -index 0000000..85baeab +index 0000000..6145c47 --- /dev/null +++ b/ld/ldemul.c -@@ -0,0 +1,352 @@ +@@ -0,0 +1,357 @@ +/* ldemul.c -- clearing house for ld emulation states -+ Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, -+ 2001, 2002, 2003, 2005, 2007, 2008, 2009, 2010, 2011, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + + This file is part of the GNU Binutils. + @@ -2636998,16 +2650897,21 @@ index 0000000..85baeab + entry = (*ld_emulation->new_vers_pattern) (entry); + return entry; +} ++ ++void ++ldemul_extra_map_file_text (bfd *abfd, struct bfd_link_info *info, FILE *mapf) ++{ ++ if (ld_emulation->extra_map_file_text) ++ ld_emulation->extra_map_file_text (abfd, info, mapf); ++} diff --git a/ld/ldemul.h b/ld/ldemul.h new file mode 100644 -index 0000000..890107f +index 0000000..27b13ad --- /dev/null +++ b/ld/ldemul.h -@@ -0,0 +1,209 @@ +@@ -0,0 +1,214 @@ +/* ld-emul.h - Linker emulation header file -+ Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000, 2001, -+ 2002, 2003, 2004, 2005, 2007, 2008 -+ Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + + This file is part of the GNU Binutils. + @@ -2637102,6 +2651006,8 @@ index 0000000..890107f + (char *, struct lang_input_statement_struct *); +extern struct bfd_elf_version_expr *ldemul_new_vers_pattern + (struct bfd_elf_version_expr *); ++extern void ldemul_extra_map_file_text ++ (bfd *, struct bfd_link_info *, FILE *); + +typedef struct ld_emulation_xfer_struct { + /* Run before parsing the command line and script file. @@ -2637202,6 +2651108,11 @@ index 0000000..890107f + struct bfd_elf_version_expr * (*new_vers_pattern) + (struct bfd_elf_version_expr *); + ++ /* Called when printing the map file, in case there are ++ emulation-specific sections for it. */ ++ void (*extra_map_file_text) ++ (bfd *, struct bfd_link_info *, FILE *); ++ +} ld_emulation_xfer_type; + +typedef enum { @@ -2637215,12 +2651126,12 @@ index 0000000..890107f +#endif diff --git a/ld/ldexp.c b/ld/ldexp.c new file mode 100644 -index 0000000..49e7c65 +index 0000000..5c4f8dd --- /dev/null +++ b/ld/ldexp.c -@@ -0,0 +1,1357 @@ +@@ -0,0 +1,1472 @@ +/* This module handles expression trees. -+ Copyright 1991-2013 Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + Written by Steve Chamberlain of Cygnus Support . + + This file is part of the GNU Binutils. @@ -2637796,13 +2651707,10 @@ index 0000000..49e7c65 + break; + + case DEFINED: -+ if (expld.phase == lang_first_phase_enum) -+ lang_track_definedness (tree->name.name); -+ else ++ if (expld.phase != lang_first_phase_enum) + { + struct bfd_link_hash_entry *h; -+ int def_iteration -+ = lang_symbol_definition_iteration (tree->name.name); ++ struct lang_definedness_hash_entry *def; + + h = bfd_wrapped_link_hash_lookup (link_info.output_bfd, + &link_info, @@ -2637812,15 +2651720,33 @@ index 0000000..49e7c65 + && (h->type == bfd_link_hash_defined + || h->type == bfd_link_hash_defweak + || h->type == bfd_link_hash_common) -+ && (def_iteration == lang_statement_iteration -+ || def_iteration == -1)); ++ && ((def = lang_symbol_defined (tree->name.name)) == NULL ++ || def->by_object ++ || def->iteration == (lang_statement_iteration & 1))); + } + break; + + case NAME: + if (expld.assign_name != NULL + && strcmp (expld.assign_name, tree->name.name) == 0) -+ expld.assign_name = NULL; ++ { ++ /* Self-assignment is only allowed for absolute symbols ++ defined in a linker script. */ ++ struct bfd_link_hash_entry *h; ++ struct lang_definedness_hash_entry *def; ++ ++ h = bfd_wrapped_link_hash_lookup (link_info.output_bfd, ++ &link_info, ++ tree->name.name, ++ FALSE, FALSE, TRUE); ++ if (!(h != NULL ++ && (h->type == bfd_link_hash_defined ++ || h->type == bfd_link_hash_defweak) ++ && h->u.def.section == bfd_abs_section_ptr ++ && (def = lang_symbol_defined (tree->name.name)) != NULL ++ && def->iteration == (lang_statement_iteration & 1))) ++ expld.assign_name = NULL; ++ } + if (expld.phase == lang_first_phase_enum) + ; + else if (tree->name.name[0] == '.' && tree->name.name[1] == 0) @@ -2637996,6 +2651922,89 @@ index 0000000..49e7c65 + } +} + ++/* Return true if TREE is '.'. */ ++ ++static bfd_boolean ++is_dot (const etree_type *tree) ++{ ++ return (tree->type.node_class == etree_name ++ && tree->type.node_code == NAME ++ && tree->name.name[0] == '.' ++ && tree->name.name[1] == 0); ++} ++ ++/* Return true if TREE is a constant equal to VAL. */ ++ ++static bfd_boolean ++is_value (const etree_type *tree, bfd_vma val) ++{ ++ return (tree->type.node_class == etree_value ++ && tree->value.value == val); ++} ++ ++/* Return true if TREE is an absolute symbol equal to VAL defined in ++ a linker script. */ ++ ++static bfd_boolean ++is_sym_value (const etree_type *tree, bfd_vma val) ++{ ++ struct bfd_link_hash_entry *h; ++ struct lang_definedness_hash_entry *def; ++ ++ return (tree->type.node_class == etree_name ++ && tree->type.node_code == NAME ++ && (def = lang_symbol_defined (tree->name.name)) != NULL ++ && def->by_script ++ && def->iteration == (lang_statement_iteration & 1) ++ && (h = bfd_wrapped_link_hash_lookup (link_info.output_bfd, ++ &link_info, ++ tree->name.name, ++ FALSE, FALSE, TRUE)) != NULL ++ && h->type == bfd_link_hash_defined ++ && h->u.def.section == bfd_abs_section_ptr ++ && h->u.def.value == val); ++} ++ ++/* Return true if TREE is ". != 0". */ ++ ++static bfd_boolean ++is_dot_ne_0 (const etree_type *tree) ++{ ++ return (tree->type.node_class == etree_binary ++ && tree->type.node_code == NE ++ && is_dot (tree->binary.lhs) ++ && is_value (tree->binary.rhs, 0)); ++} ++ ++/* Return true if TREE is ". = . + 0" or ". = . + sym" where sym is an ++ absolute constant with value 0 defined in a linker script. */ ++ ++static bfd_boolean ++is_dot_plus_0 (const etree_type *tree) ++{ ++ return (tree->type.node_class == etree_binary ++ && tree->type.node_code == '+' ++ && is_dot (tree->binary.lhs) ++ && (is_value (tree->binary.rhs, 0) ++ || is_sym_value (tree->binary.rhs, 0))); ++} ++ ++/* Return true if TREE is "ALIGN (. != 0 ? some_expression : 1)". */ ++ ++static bfd_boolean ++is_align_conditional (const etree_type *tree) ++{ ++ if (tree->type.node_class == etree_unary ++ && tree->type.node_code == ALIGN_K) ++ { ++ tree = tree->unary.child; ++ return (tree->type.node_class == etree_trinary ++ && is_dot_ne_0 (tree->trinary.cond) ++ && is_value (tree->trinary.rhs, 1)); ++ } ++ return 0; ++} ++ +static void +exp_fold_tree_1 (etree_type *tree) +{ @@ -2638060,6 +2652069,20 @@ index 0000000..49e7c65 + exp_fold_tree_1 (tree->assign.src); + expld.assigning_to_dot = FALSE; + ++ /* If we are assigning to dot inside an output section ++ arrange to keep the section, except for certain ++ expressions that evaluate to zero. We ignore . = 0, ++ . = . + 0, and . = ALIGN (. != 0 ? expr : 1). */ ++ if (expld.phase == lang_mark_phase_enum ++ && expld.section != bfd_abs_section_ptr ++ && !(expld.result.valid_p ++ && expld.result.value == 0 ++ && (is_value (tree->assign.src, 0) ++ || is_sym_value (tree->assign.src, 0) ++ || is_dot_plus_0 (tree->assign.src) ++ || is_align_conditional (tree->assign.src)))) ++ expld.section->flags |= SEC_KEEP; ++ + if (!expld.result.valid_p) + { + if (expld.phase != lang_mark_phase_enum) @@ -2638110,7 +2652133,10 @@ index 0000000..49e7c65 + if (h == NULL + || (h->type != bfd_link_hash_new + && h->type != bfd_link_hash_undefined -+ && h->type != bfd_link_hash_common)) ++ && h->type != bfd_link_hash_common ++ && !(h->type == bfd_link_hash_defined ++ && (h->u.def.section->flags ++ & SEC_LINKER_CREATED) != 0))) + { + /* Do nothing. The symbol was never referenced, or was + defined by some object. */ @@ -2638578,13 +2652604,12 @@ index 0000000..49e7c65 +} diff --git a/ld/ldexp.h b/ld/ldexp.h new file mode 100644 -index 0000000..2c726e7 +index 0000000..6a02b39 --- /dev/null +++ b/ld/ldexp.h -@@ -0,0 +1,226 @@ +@@ -0,0 +1,225 @@ +/* ldexp.h - -+ Copyright 1991, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2002, -+ 2003, 2004, 2005, 2007, 2011, 2012 Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + + This file is part of the GNU Binutils. + @@ -2638810,14 +2652835,12 @@ index 0000000..2c726e7 +#endif diff --git a/ld/ldfile.c b/ld/ldfile.c new file mode 100644 -index 0000000..16baef8 +index 0000000..782ed7f --- /dev/null +++ b/ld/ldfile.c -@@ -0,0 +1,670 @@ +@@ -0,0 +1,668 @@ +/* Linker file opening and searching. -+ Copyright 1991, 1992, 1993, 1994, 1995, 1998, 1999, 2000, 2001, 2002, -+ 2003, 2004, 2005, 2007, 2008, 2009, 2010, 2011, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + + This file is part of the GNU Binutils. + @@ -2639185,7 +2653208,7 @@ index 0000000..16baef8 + return TRUE; + } + -+ if (entry->flags.maybe_archive) ++ if (entry->flags.maybe_archive && !entry->flags.full_name_provided) + string = concat (search->name, slash, lib, entry->filename, + arch, suffix, (const char *) NULL); + else @@ -2639486,13 +2653509,12 @@ index 0000000..16baef8 +} diff --git a/ld/ldfile.h b/ld/ldfile.h new file mode 100644 -index 0000000..9456092 +index 0000000..cbcd7cb --- /dev/null +++ b/ld/ldfile.h -@@ -0,0 +1,62 @@ +@@ -0,0 +1,61 @@ +/* ldfile.h - -+ Copyright 1991, 1992, 1993, 1994, 1995, 2000, 2002, 2003, 2004, 2005, -+ 2007, 2012 Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + + This file is part of the GNU Binutils. + @@ -2639554,12 +2653576,12 @@ index 0000000..9456092 +#endif diff --git a/ld/ldgram.y b/ld/ldgram.y new file mode 100644 -index 0000000..1ded4e7 +index 0000000..4875fa7 --- /dev/null +++ b/ld/ldgram.y @@ -0,0 +1,1477 @@ +/* A YACC grammar to parse a superset of the AT&T linker scripting language. -+ Copyright 1991-2013 Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + Written by Steve Chamberlain of Cygnus Support (steve@cygnus.com). + + This file is part of the GNU Binutils. @@ -2641037,15 +2655059,13 @@ index 0000000..1ded4e7 +} diff --git a/ld/ldint.texinfo b/ld/ldint.texinfo new file mode 100644 -index 0000000..19272c5 +index 0000000..99a5da2 --- /dev/null +++ b/ld/ldint.texinfo -@@ -0,0 +1,704 @@ +@@ -0,0 +1,700 @@ +\input texinfo +@setfilename ldint.info -+@c Copyright 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, -+@c 2003, 2005, 2006, 2007 -+@c Free Software Foundation, Inc. ++@c Copyright (C) 1992-2014 Free Software Foundation, Inc. + +@ifnottex +@dircategory Software development @@ -2641057,8 +2655077,7 @@ index 0000000..19272c5 +@copying +This file documents the internals of the GNU linker ld. + -+Copyright @copyright{} 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2007 -+Free Software Foundation, Inc. ++Copyright @copyright{} 1992-2014 Free Software Foundation, Inc. +Contributed by Cygnus Support. + +Permission is granted to copy, distribute and/or modify this document @@ -2641101,8 +2655120,7 @@ index 0000000..19272c5 +@end tex + +@vskip 0pt plus 1filll -+Copyright @copyright{} 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000 -+Free Software Foundation, Inc. ++Copyright @copyright{} 1992-2014 Free Software Foundation, Inc. + + Permission is granted to copy, distribute and/or modify this document + under the terms of the GNU Free Documentation License, Version 1.3 @@ -2641747,12 +2655765,12 @@ index 0000000..19272c5 +@bye diff --git a/ld/ldlang.c b/ld/ldlang.c new file mode 100644 -index 0000000..ba7f493 +index 0000000..585914f --- /dev/null +++ b/ld/ldlang.c -@@ -0,0 +1,8063 @@ +@@ -0,0 +1,8118 @@ +/* Linker command language support. -+ Copyright 1991-2013 Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + + This file is part of the GNU Binutils. + @@ -2641820,10 +2655838,10 @@ index 0000000..ba7f493 +static lang_statement_list_type *stat_save[10]; +static lang_statement_list_type **stat_save_ptr = &stat_save[0]; +static struct unique_sections *unique_section_list; ++static struct asneeded_minfo *asneeded_list_head; + +/* Forward declarations. */ +static void exp_init_os (etree_type *); -+static void init_map_userdata (bfd *, asection *, void *); +static lang_input_statement_type *lookup_name (const char *); +static struct bfd_hash_entry *lang_definedness_newfunc + (struct bfd_hash_entry *, struct bfd_hash_table *, const char *); @@ -2641859,13 +2655877,12 @@ index 0000000..ba7f493 +bfd_boolean delete_output_file_on_failure = FALSE; +struct lang_phdr *lang_phdr_list; +struct lang_nocrossrefs *nocrossref_list; ++struct asneeded_minfo **asneeded_list_tail; + + /* Functions that traverse the linker script and might evaluate -+ DEFINED() need to increment this. */ ++ DEFINED() need to increment this at the start of the traversal. */ +int lang_statement_iteration = 0; + -+etree_type *base; /* Relocation base - or null */ -+ +/* Return TRUE if the PATTERN argument is a wildcard pattern. + Although backslashes are treated specially if a pattern contains + wildcards, we do not consider the mere presence of a backslash to @@ -2642815,13 +2656832,6 @@ index 0000000..ba7f493 + p->flags.whole_archive = input_flags.whole_archive; + p->flags.sysrooted = input_flags.sysrooted; + -+ if (file_type == lang_input_file_is_l_enum -+ && name[0] == ':' && name[1] != '\0') -+ { -+ file_type = lang_input_file_is_search_file_enum; -+ name = name + 1; -+ } -+ + switch (file_type) + { + case lang_input_file_is_symbols_only_enum: @@ -2642835,7 +2656845,13 @@ index 0000000..ba7f493 + p->local_sym_name = name; + break; + case lang_input_file_is_l_enum: -+ p->filename = name; ++ if (name[0] == ':' && name[1] != '\0') ++ { ++ p->filename = name + 1; ++ p->flags.full_name_provided = TRUE; ++ } ++ else ++ p->filename = name; + p->local_sym_name = concat ("-l", name, (const char *) NULL); + p->flags.maybe_archive = TRUE; + p->flags.real = TRUE; @@ -2642975,23 +2656991,21 @@ index 0000000..ba7f493 + + abs_output_section->bfd_section = bfd_abs_section_ptr; + -+ /* The value "3" is ad-hoc, somewhat related to the expected number of -+ DEFINED expressions in a linker script. For most default linker -+ scripts, there are none. Why a hash table then? Well, it's somewhat -+ simpler to re-use working machinery than using a linked list in terms -+ of code-complexity here in ld, besides the initialization which just -+ looks like other code here. */ ++ /* The value "13" is ad-hoc, somewhat related to the expected number of ++ assignments in a linker script. */ + if (!bfd_hash_table_init_n (&lang_definedness_table, + lang_definedness_newfunc, + sizeof (struct lang_definedness_hash_entry), -+ 3)) ++ 13)) + einfo (_("%P%F: can not create hash table: %E\n")); ++ ++ asneeded_list_head = NULL; ++ asneeded_list_tail = &asneeded_list_head; +} + +void +lang_finish (void) +{ -+ bfd_link_hash_table_free (link_info.output_bfd, link_info.hash); + bfd_hash_table_free (&lang_definedness_table); + output_section_statement_table_free (); +} @@ -2643130,6 +2657144,14 @@ index 0000000..ba7f493 + return lang_memory_region_lookup (DEFAULT_MEMORY_REGION, FALSE); +} + ++/* Get the output section statement directly from the userdata. */ ++ ++lang_output_section_statement_type * ++lang_output_section_get (const asection *output_section) ++{ ++ return get_userdata (output_section); ++} ++ +/* Find or create an output_section_statement with the given NAME. + If CONSTRAINT is non-zero match one with that constraint, otherwise + match any non-negative constraint. If CREATE, always make a @@ -2643240,7 +2657262,7 @@ index 0000000..ba7f493 + lang_match_sec_type_func match_type) +{ + lang_output_section_statement_type *first, *look, *found; -+ flagword flags; ++ flagword look_flags, sec_flags, differ; + + /* We know the first statement on this list is *ABS*. May as well + skip it. */ @@ -2643248,21 +2657270,22 @@ index 0000000..ba7f493 + first = first->next; + + /* First try for an exact match. */ ++ sec_flags = sec->flags; + found = NULL; + for (look = first; look; look = look->next) + { -+ flags = look->flags; ++ look_flags = look->flags; + if (look->bfd_section != NULL) + { -+ flags = look->bfd_section->flags; ++ look_flags = look->bfd_section->flags; + if (match_type && !match_type (link_info.output_bfd, + look->bfd_section, + sec->owner, sec)) + continue; + } -+ flags ^= sec->flags; -+ if (!(flags & (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_READONLY -+ | SEC_CODE | SEC_SMALL_DATA | SEC_THREAD_LOCAL))) ++ differ = look_flags ^ sec_flags; ++ if (!(differ & (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_READONLY ++ | SEC_CODE | SEC_SMALL_DATA | SEC_THREAD_LOCAL))) + found = look; + } + if (found != NULL) @@ -2643272,115 +2657295,144 @@ index 0000000..ba7f493 + return found; + } + -+ if ((sec->flags & SEC_CODE) != 0 -+ && (sec->flags & SEC_ALLOC) != 0) ++ if ((sec_flags & SEC_CODE) != 0 ++ && (sec_flags & SEC_ALLOC) != 0) + { + /* Try for a rw code section. */ + for (look = first; look; look = look->next) + { -+ flags = look->flags; ++ look_flags = look->flags; + if (look->bfd_section != NULL) + { -+ flags = look->bfd_section->flags; ++ look_flags = look->bfd_section->flags; + if (match_type && !match_type (link_info.output_bfd, + look->bfd_section, + sec->owner, sec)) + continue; + } -+ flags ^= sec->flags; -+ if (!(flags & (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD -+ | SEC_CODE | SEC_SMALL_DATA | SEC_THREAD_LOCAL))) ++ differ = look_flags ^ sec_flags; ++ if (!(differ & (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD ++ | SEC_CODE | SEC_SMALL_DATA | SEC_THREAD_LOCAL))) + found = look; + } + } -+ else if ((sec->flags & (SEC_READONLY | SEC_THREAD_LOCAL)) != 0 -+ && (sec->flags & SEC_ALLOC) != 0) ++ else if ((sec_flags & SEC_READONLY) != 0 ++ && (sec_flags & SEC_ALLOC) != 0) + { + /* .rodata can go after .text, .sdata2 after .rodata. */ + for (look = first; look; look = look->next) + { -+ flags = look->flags; ++ look_flags = look->flags; + if (look->bfd_section != NULL) + { -+ flags = look->bfd_section->flags; ++ look_flags = look->bfd_section->flags; + if (match_type && !match_type (link_info.output_bfd, + look->bfd_section, + sec->owner, sec)) + continue; + } -+ flags ^= sec->flags; -+ if (!(flags & (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD -+ | SEC_READONLY | SEC_SMALL_DATA)) -+ || (!(flags & (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD -+ | SEC_READONLY)) -+ && !(look->flags & SEC_SMALL_DATA)) -+ || (!(flags & (SEC_THREAD_LOCAL | SEC_ALLOC)) -+ && (look->flags & SEC_THREAD_LOCAL) -+ && (!(flags & SEC_LOAD) -+ || (look->flags & SEC_LOAD)))) ++ differ = look_flags ^ sec_flags; ++ if (!(differ & (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD ++ | SEC_READONLY | SEC_SMALL_DATA)) ++ || (!(differ & (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD ++ | SEC_READONLY)) ++ && !(look_flags & SEC_SMALL_DATA))) + found = look; + } + } -+ else if ((sec->flags & SEC_SMALL_DATA) != 0 -+ && (sec->flags & SEC_ALLOC) != 0) ++ else if ((sec_flags & SEC_THREAD_LOCAL) != 0 ++ && (sec_flags & SEC_ALLOC) != 0) ++ { ++ /* .tdata can go after .data, .tbss after .tdata. Treat .tbss ++ as if it were a loaded section, and don't use match_type. */ ++ bfd_boolean seen_thread_local = FALSE; ++ ++ match_type = NULL; ++ for (look = first; look; look = look->next) ++ { ++ look_flags = look->flags; ++ if (look->bfd_section != NULL) ++ look_flags = look->bfd_section->flags; ++ ++ differ = look_flags ^ (sec_flags | SEC_LOAD | SEC_HAS_CONTENTS); ++ if (!(differ & (SEC_THREAD_LOCAL | SEC_ALLOC))) ++ { ++ /* .tdata and .tbss must be adjacent and in that order. */ ++ if (!(look_flags & SEC_LOAD) ++ && (sec_flags & SEC_LOAD)) ++ /* ..so if we're at a .tbss section and we're placing ++ a .tdata section stop looking and return the ++ previous section. */ ++ break; ++ found = look; ++ seen_thread_local = TRUE; ++ } ++ else if (seen_thread_local) ++ break; ++ else if (!(differ & (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD))) ++ found = look; ++ } ++ } ++ else if ((sec_flags & SEC_SMALL_DATA) != 0 ++ && (sec_flags & SEC_ALLOC) != 0) + { + /* .sdata goes after .data, .sbss after .sdata. */ + for (look = first; look; look = look->next) + { -+ flags = look->flags; ++ look_flags = look->flags; + if (look->bfd_section != NULL) + { -+ flags = look->bfd_section->flags; ++ look_flags = look->bfd_section->flags; + if (match_type && !match_type (link_info.output_bfd, + look->bfd_section, + sec->owner, sec)) + continue; + } -+ flags ^= sec->flags; -+ if (!(flags & (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD -+ | SEC_THREAD_LOCAL)) -+ || ((look->flags & SEC_SMALL_DATA) -+ && !(sec->flags & SEC_HAS_CONTENTS))) ++ differ = look_flags ^ sec_flags; ++ if (!(differ & (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD ++ | SEC_THREAD_LOCAL)) ++ || ((look_flags & SEC_SMALL_DATA) ++ && !(sec_flags & SEC_HAS_CONTENTS))) + found = look; + } + } -+ else if ((sec->flags & SEC_HAS_CONTENTS) != 0 -+ && (sec->flags & SEC_ALLOC) != 0) ++ else if ((sec_flags & SEC_HAS_CONTENTS) != 0 ++ && (sec_flags & SEC_ALLOC) != 0) + { + /* .data goes after .rodata. */ + for (look = first; look; look = look->next) + { -+ flags = look->flags; ++ look_flags = look->flags; + if (look->bfd_section != NULL) + { -+ flags = look->bfd_section->flags; ++ look_flags = look->bfd_section->flags; + if (match_type && !match_type (link_info.output_bfd, + look->bfd_section, + sec->owner, sec)) + continue; + } -+ flags ^= sec->flags; -+ if (!(flags & (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD -+ | SEC_SMALL_DATA | SEC_THREAD_LOCAL))) ++ differ = look_flags ^ sec_flags; ++ if (!(differ & (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD ++ | SEC_SMALL_DATA | SEC_THREAD_LOCAL))) + found = look; + } + } -+ else if ((sec->flags & SEC_ALLOC) != 0) ++ else if ((sec_flags & SEC_ALLOC) != 0) + { + /* .bss goes after any other alloc section. */ + for (look = first; look; look = look->next) + { -+ flags = look->flags; ++ look_flags = look->flags; + if (look->bfd_section != NULL) + { -+ flags = look->bfd_section->flags; ++ look_flags = look->bfd_section->flags; + if (match_type && !match_type (link_info.output_bfd, + look->bfd_section, + sec->owner, sec)) + continue; + } -+ flags ^= sec->flags; -+ if (!(flags & SEC_ALLOC)) ++ differ = look_flags ^ sec_flags; ++ if (!(differ & SEC_ALLOC)) + found = look; + } + } @@ -2643389,11 +2657441,11 @@ index 0000000..ba7f493 + /* non-alloc go last. */ + for (look = first; look; look = look->next) + { -+ flags = look->flags; ++ look_flags = look->flags; + if (look->bfd_section != NULL) -+ flags = look->bfd_section->flags; -+ flags ^= sec->flags; -+ if (!(flags & SEC_DEBUGGING)) ++ look_flags = look->bfd_section->flags; ++ differ = look_flags ^ sec_flags; ++ if (!(differ & SEC_DEBUGGING)) + found = look; + } + return found; @@ -2643704,6 +2657756,43 @@ index 0000000..ba7f493 +} + +static void ++lang_print_asneeded (void) ++{ ++ struct asneeded_minfo *m; ++ char buf[100]; ++ ++ if (asneeded_list_head == NULL) ++ return; ++ ++ sprintf (buf, _("\nAs-needed library included " ++ "to satisfy reference by file (symbol)\n\n")); ++ minfo ("%s", buf); ++ ++ for (m = asneeded_list_head; m != NULL; m = m->next) ++ { ++ size_t len; ++ ++ minfo ("%s", m->soname); ++ len = strlen (m->soname); ++ ++ if (len >= 29) ++ { ++ print_nl (); ++ len = 0; ++ } ++ while (len < 30) ++ { ++ print_space (); ++ ++len; ++ } ++ ++ if (m->ref != NULL) ++ minfo ("%B ", m->ref); ++ minfo ("(%T)\n", m->name); ++ } ++} ++ ++static void +lang_map_flags (flagword flag) +{ + if (flag & SEC_ALLOC) @@ -2643727,7 +2657816,6 @@ index 0000000..ba7f493 +{ + lang_memory_region_type *m; + bfd_boolean dis_header_printed = FALSE; -+ bfd *p; + + LANG_FOR_EACH_INPUT_STATEMENT (file) + { @@ -2643799,50 +2657887,36 @@ index 0000000..ba7f493 + if (! link_info.reduce_memory_overheads) + { + obstack_begin (&map_obstack, 1000); -+ for (p = link_info.input_bfds; p != (bfd *) NULL; p = p->link_next) -+ bfd_map_over_sections (p, init_map_userdata, 0); + bfd_link_hash_traverse (link_info.hash, sort_def_symbol, 0); + } -+ lang_statement_iteration ++; ++ lang_statement_iteration++; + print_statements (); -+} + -+static void -+init_map_userdata (bfd *abfd ATTRIBUTE_UNUSED, -+ asection *sec, -+ void *data ATTRIBUTE_UNUSED) -+{ -+ fat_section_userdata_type *new_data -+ = ((fat_section_userdata_type *) (stat_alloc -+ (sizeof (fat_section_userdata_type)))); -+ -+ ASSERT (get_userdata (sec) == NULL); -+ get_userdata (sec) = new_data; -+ new_data->map_symbol_def_tail = &new_data->map_symbol_def_head; -+ new_data->map_symbol_def_count = 0; ++ ldemul_extra_map_file_text (link_info.output_bfd, &link_info, config.map_file); +} + +static bfd_boolean +sort_def_symbol (struct bfd_link_hash_entry *hash_entry, + void *info ATTRIBUTE_UNUSED) +{ -+ if (hash_entry->type == bfd_link_hash_defined -+ || hash_entry->type == bfd_link_hash_defweak) ++ if ((hash_entry->type == bfd_link_hash_defined ++ || hash_entry->type == bfd_link_hash_defweak) ++ && hash_entry->u.def.section->owner != link_info.output_bfd ++ && hash_entry->u.def.section->owner != NULL) + { -+ struct fat_user_section_struct *ud; ++ input_section_userdata_type *ud; + struct map_symbol_def *def; + -+ ud = (struct fat_user_section_struct *) -+ get_userdata (hash_entry->u.def.section); -+ if (! ud) ++ ud = ((input_section_userdata_type *) ++ get_userdata (hash_entry->u.def.section)); ++ if (!ud) + { -+ /* ??? What do we have to do to initialize this beforehand? */ -+ /* The first time we get here is bfd_abs_section... */ -+ init_map_userdata (0, hash_entry->u.def.section, 0); -+ ud = (struct fat_user_section_struct *) -+ get_userdata (hash_entry->u.def.section); ++ ud = (input_section_userdata_type *) stat_alloc (sizeof (*ud)); ++ get_userdata (hash_entry->u.def.section) = ud; ++ ud->map_symbol_def_tail = &ud->map_symbol_def_head; ++ ud->map_symbol_def_count = 0; + } -+ else if (!ud->map_symbol_def_tail) ++ else if (!ud->map_symbol_def_tail) + ud->map_symbol_def_tail = &ud->map_symbol_def_head; + + def = (struct map_symbol_def *) obstack_alloc (&map_obstack, sizeof *def); @@ -2643875,13 +2657949,9 @@ index 0000000..ba7f493 + s->bfd_section->output_section = s->bfd_section; + s->bfd_section->output_offset = 0; + -+ if (!link_info.reduce_memory_overheads) -+ { -+ fat_section_userdata_type *new_userdata = (fat_section_userdata_type *) -+ stat_alloc (sizeof (fat_section_userdata_type)); -+ memset (new_userdata, 0, sizeof (fat_section_userdata_type)); -+ get_userdata (s->bfd_section) = new_userdata; -+ } ++ /* Set the userdata of the output section to the output section ++ statement to avoid lookup. */ ++ get_userdata (s->bfd_section) = s; + + /* If there is a base address, make sure that any sections it might + mention are initialized. */ @@ -2644773,6 +2658843,9 @@ index 0000000..ba7f493 + return default_target; +} + ++/* Stashed function to free link_info.hash; see open_output. */ ++void (*output_bfd_hash_table_free_fn) (struct bfd_link_hash_table *); ++ +/* Open the output file. */ + +static void @@ -2644852,6 +2658925,18 @@ index 0000000..ba7f493 + if (link_info.hash == NULL) + einfo (_("%P%F: can not create hash table: %E\n")); + ++ /* We want to please memory leak checkers by deleting link_info.hash. ++ We can't do it in lang_finish, as a bfd target may hold references to ++ symbols in this table and use them when their _bfd_write_contents ++ function is invoked, as part of bfd_close on the output_bfd. But, ++ output_bfd is deallocated at bfd_close, so we can't refer to ++ output_bfd after that time, and dereferencing it is needed to call ++ "bfd_link_hash_table_free". Smash this dependency deadlock and grab ++ the function pointer; arrange to call it on link_info.hash in ++ ld_cleanup. */ ++ output_bfd_hash_table_free_fn ++ = link_info.output_bfd->xvec->_bfd_link_hash_table_free; ++ + bfd_set_gp_size (link_info.output_bfd, g_switch_value); +} + @@ -2645053,15 +2659138,6 @@ index 0000000..ba7f493 + einfo ("%F"); +} + -+/* Add a symbol to a hash of symbols used in DEFINED (NAME) expressions. */ -+ -+void -+lang_track_definedness (const char *name) -+{ -+ if (bfd_hash_lookup (&lang_definedness_table, name, TRUE, FALSE) == NULL) -+ einfo (_("%P%F: bfd_hash_lookup failed creating symbol %s\n"), name); -+} -+ +/* New-function for the definedness hash table. */ + +static struct bfd_hash_entry * @@ -2645079,28 +2659155,22 @@ index 0000000..ba7f493 + if (ret == NULL) + einfo (_("%P%F: bfd_hash_allocate failed creating symbol %s\n"), name); + -+ ret->iteration = -1; ++ ret->by_object = 0; ++ ret->by_script = 0; ++ ret->iteration = 0; + return &ret->root; +} + -+/* Return the iteration when the definition of NAME was last updated. A -+ value of -1 means that the symbol is not defined in the linker script -+ or the command line, but may be defined in the linker symbol table. */ ++/* Called during processing of linker script script expressions. ++ For symbols assigned in a linker script, return a struct describing ++ where the symbol is defined relative to the current expression, ++ otherwise return NULL. */ + -+int -+lang_symbol_definition_iteration (const char *name) ++struct lang_definedness_hash_entry * ++lang_symbol_defined (const char *name) +{ -+ struct lang_definedness_hash_entry *defentry -+ = (struct lang_definedness_hash_entry *) -+ bfd_hash_lookup (&lang_definedness_table, name, FALSE, FALSE); -+ -+ /* We've already created this one on the presence of DEFINED in the -+ script, so it can't be NULL unless something is borked elsewhere in -+ the code. */ -+ if (defentry == NULL) -+ FAIL (); -+ -+ return defentry->iteration; ++ return ((struct lang_definedness_hash_entry *) ++ bfd_hash_lookup (&lang_definedness_table, name, FALSE, FALSE)); +} + +/* Update the definedness state of NAME. */ @@ -2645110,25 +2659180,20 @@ index 0000000..ba7f493 +{ + struct lang_definedness_hash_entry *defentry + = (struct lang_definedness_hash_entry *) -+ bfd_hash_lookup (&lang_definedness_table, name, FALSE, FALSE); ++ bfd_hash_lookup (&lang_definedness_table, name, TRUE, FALSE); + -+ /* We don't keep track of symbols not tested with DEFINED. */ + if (defentry == NULL) -+ return; ++ einfo (_("%P%F: bfd_hash_lookup failed creating symbol %s\n"), name); + -+ /* If the symbol was already defined, and not from an earlier statement -+ iteration, don't update the definedness iteration, because that'd -+ make the symbol seem defined in the linker script at this point, and -+ it wasn't; it was defined in some object. If we do anyway, DEFINED -+ would start to yield false before this point and the construct "sym = -+ DEFINED (sym) ? sym : X;" would change sym to X despite being defined -+ in an object. */ -+ if (h->type != bfd_link_hash_undefined ++ /* If the symbol was already defined, and not by a script, then it ++ must be defined by an object file. */ ++ if (!defentry->by_script ++ && h->type != bfd_link_hash_undefined + && h->type != bfd_link_hash_common -+ && h->type != bfd_link_hash_new -+ && defentry->iteration == -1) -+ return; ++ && h->type != bfd_link_hash_new) ++ defentry->by_object = 1; + ++ defentry->by_script = 1; + defentry->iteration = lang_statement_iteration; +} + @@ -2645726,7 +2659791,8 @@ index 0000000..ba7f493 + const char *dst = assignment->exp->assign.dst; + + is_dot = (dst[0] == '.' && dst[1] == 0); -+ expld.assign_name = dst; ++ if (!is_dot) ++ expld.assign_name = dst; + tree = assignment->exp->assign.src; + } + @@ -2645836,8 +2659902,8 @@ index 0000000..ba7f493 +static void +print_all_symbols (asection *sec) +{ -+ struct fat_user_section_struct *ud = -+ (struct fat_user_section_struct *) get_userdata (sec); ++ input_section_userdata_type *ud ++ = (input_section_userdata_type *) get_userdata (sec); + struct map_symbol_def *def; + struct bfd_link_hash_entry **entries; + unsigned int i; @@ -2646313,12 +2660379,15 @@ index 0000000..ba7f493 +{ + lang_input_section_type *is = &((*this_ptr)->input_section); + asection *i = is->section; ++ asection *o = output_section_statement->bfd_section; + -+ if (i->sec_info_type != SEC_INFO_TYPE_JUST_SYMS -+ && (i->flags & SEC_EXCLUDE) == 0) ++ if (i->sec_info_type == SEC_INFO_TYPE_JUST_SYMS) ++ i->output_offset = i->vma - o->vma; ++ else if ((i->flags & SEC_EXCLUDE) != 0) ++ i->output_offset = dot - o->vma; ++ else + { + bfd_size_type alignment_needed; -+ asection *o; + + /* Align this section first to the input sections requirement, + then to the output section's requirement. If this alignment @@ -2646328,7 +2660397,6 @@ index 0000000..ba7f493 + if (output_section_statement->subsection_alignment != -1) + i->alignment_power = output_section_statement->subsection_alignment; + -+ o = output_section_statement->bfd_section; + if (o->alignment_power < i->alignment_power) + o->alignment_power = i->alignment_power; + @@ -2646341,17 +2660409,12 @@ index 0000000..ba7f493 + } + + /* Remember where in the output section this input section goes. */ -+ + i->output_offset = dot - o->vma; + + /* Mark how big the output section must be to contain this now. */ + dot += TO_ADDR (i->size); + o->size = TO_SIZE (dot - o->vma); + } -+ else -+ { -+ i->output_offset = i->vma - output_section_statement->bfd_section->vma; -+ } + + return dot; +} @@ -2646526,7 +2660589,7 @@ index 0000000..ba7f493 + { + case lang_output_section_statement_enum: + { -+ bfd_vma newdot, after; ++ bfd_vma newdot, after, dotdelta; + lang_output_section_statement_type *os; + lang_memory_region_type *r; + int section_alignment = 0; @@ -2646592,6 +2660655,7 @@ index 0000000..ba7f493 + } + + newdot = dot; ++ dotdelta = 0; + if (bfd_is_abs_section (os->bfd_section)) + { + /* No matter what happens, an abs section starts at zero. */ @@ -2646660,13 +2660724,14 @@ index 0000000..ba7f493 + bfd_vma savedot = newdot; + newdot = align_power (newdot, section_alignment); + -+ if (newdot != savedot ++ dotdelta = newdot - savedot; ++ if (dotdelta != 0 + && (config.warn_section_align + || os->addr_tree != NULL) + && expld.phase != lang_mark_phase_enum) + einfo (_("%P: warning: changing start of section" + " %s by %lu bytes\n"), -+ os->name, (unsigned long) (newdot - savedot)); ++ os->name, (unsigned long) dotdelta); + } + + bfd_set_section_vma (0, os->bfd_section, newdot); @@ -2646714,15 +2660779,20 @@ index 0000000..ba7f493 + { + bfd_vma lma = os->lma_region->current; + -+ /* When LMA_REGION is the same as REGION, align the LMA -+ as we did for the VMA, possibly including alignment -+ from the bfd section. If a different region, then -+ only align according to the value in the output -+ statement unless specified otherwise. */ -+ if (os->lma_region != os->region && !os->align_lma_with_input) -+ section_alignment = os->section_alignment; -+ if (section_alignment > 0) -+ lma = align_power (lma, section_alignment); ++ if (os->align_lma_with_input) ++ lma += dotdelta; ++ else ++ { ++ /* When LMA_REGION is the same as REGION, align the LMA ++ as we did for the VMA, possibly including alignment ++ from the bfd section. If a different region, then ++ only align according to the value in the output ++ statement. */ ++ if (os->lma_region != os->region) ++ section_alignment = os->section_alignment; ++ if (section_alignment > 0) ++ lma = align_power (lma, section_alignment); ++ } + os->bfd_section->lma = lma; + } + else if (r->last_os != NULL @@ -2646798,7 +2660868,10 @@ index 0000000..ba7f493 + if ((os->bfd_section->flags & SEC_HAS_CONTENTS) != 0 + || (os->bfd_section->flags & SEC_THREAD_LOCAL) == 0 + || link_info.relocatable) -+ dot += TO_ADDR (os->bfd_section->size); ++ dotdelta = TO_ADDR (os->bfd_section->size); ++ else ++ dotdelta = 0; ++ dot += dotdelta; + + if (os->update_dot_tree != 0) + exp_fold_tree (os->update_dot_tree, bfd_abs_section_ptr, &dot); @@ -2646818,10 +2660891,10 @@ index 0000000..ba7f493 + os->bfd_section->vma); + + if (os->lma_region != NULL && os->lma_region != os->region -+ && (os->bfd_section->flags & SEC_LOAD)) ++ && ((os->bfd_section->flags & SEC_LOAD) ++ || os->align_lma_with_input)) + { -+ os->lma_region->current -+ = os->bfd_section->lma + TO_ADDR (os->bfd_section->size); ++ os->lma_region->current = os->bfd_section->lma + dotdelta; + + if (check_regions) + os_region_check (os, os->lma_region, NULL, @@ -2646922,7 +2660995,7 @@ index 0000000..ba7f493 + *relax = TRUE; + } + dot = size_input_section (prev, output_section_statement, -+ output_section_statement->fill, dot); ++ fill, dot); + } + break; + @@ -2647115,18 +2661188,14 @@ index 0000000..ba7f493 + && link_info.relro && expld.dataseg.relro_end) + { + /* If DATA_SEGMENT_ALIGN DATA_SEGMENT_RELRO_END pair was seen, try -+ to put expld.dataseg.relro on a (common) page boundary. */ -+ bfd_vma min_base, old_base, relro_end, maxpage; ++ to put expld.dataseg.relro_end on a (common) page boundary. */ ++ bfd_vma min_base, relro_end, maxpage; + + expld.dataseg.phase = exp_dataseg_relro_adjust; + maxpage = expld.dataseg.maxpagesize; + /* MIN_BASE is the absolute minimum address we are allowed to start the + read-write segment (byte before will be mapped read-only). */ + min_base = (expld.dataseg.min_base + maxpage - 1) & ~(maxpage - 1); -+ /* OLD_BASE is the address for a feasible minimum address which will -+ still not cause a data overlap inside MAXPAGE causing file offset skip -+ by MAXPAGE. */ -+ old_base = expld.dataseg.base; + expld.dataseg.base += (-expld.dataseg.relro_end + & (expld.dataseg.pagesize - 1)); + /* Compute the expected PT_GNU_RELRO segment end. */ @@ -2647142,9 +2661211,9 @@ index 0000000..ba7f493 + if (expld.dataseg.relro_end > relro_end) + { + /* The alignment of sections between DATA_SEGMENT_ALIGN -+ and DATA_SEGMENT_RELRO_END caused huge padding to be -+ inserted at DATA_SEGMENT_RELRO_END. Try to start a bit lower so -+ that the section alignments will fit in. */ ++ and DATA_SEGMENT_RELRO_END can cause excessive padding to ++ be inserted at DATA_SEGMENT_RELRO_END. Try to start a ++ bit lower so that the section alignments will fit in. */ + asection *sec; + unsigned int max_alignment_power = 0; + @@ -2647158,9 +2661227,11 @@ index 0000000..ba7f493 + + if (((bfd_vma) 1 << max_alignment_power) < expld.dataseg.pagesize) + { -+ if (expld.dataseg.base - (1 << max_alignment_power) < old_base) -+ expld.dataseg.base += expld.dataseg.pagesize; -+ expld.dataseg.base -= (1 << max_alignment_power); ++ /* Aligning the adjusted base guarantees the padding ++ between sections won't change. This is better than ++ simply subtracting 1 << max_alignment_power which is ++ what we used to do here. */ ++ expld.dataseg.base &= ~((1 << max_alignment_power) - 1); + lang_reset_memory_regions (); + one_lang_size_sections_pass (relax, check_regions); + } @@ -2648421,6 +2662492,8 @@ index 0000000..ba7f493 + link_info.gc_sym_list = ldlang_undef_chain_list_head; + + ldemul_after_open (); ++ if (config.map_file != NULL) ++ lang_print_asneeded (); + + bfd_section_already_linked_table_free (); + @@ -2649816,12 +2663889,12 @@ index 0000000..ba7f493 +} diff --git a/ld/ldlang.h b/ld/ldlang.h new file mode 100644 -index 0000000..2dbec5a +index 0000000..7d69c56 --- /dev/null +++ b/ld/ldlang.h -@@ -0,0 +1,663 @@ +@@ -0,0 +1,696 @@ +/* ldlang.h - linker command language support -+ Copyright 1991-2013 Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + + This file is part of the GNU Binutils. + @@ -2650057,6 +2664130,9 @@ index 0000000..2dbec5a + /* 1 means this file was specified in a -l option. */ + unsigned int maybe_archive : 1; + ++ /* 1 means this file was specified in a -l:namespec option. */ ++ unsigned int full_name_provided : 1; ++ + /* 1 means search a set of directories for this file. */ + unsigned int search_dirs : 1; + @@ -2650135,6 +2664211,23 @@ index 0000000..2dbec5a + asection *section; +} lang_input_section_type; + ++struct map_symbol_def { ++ struct bfd_link_hash_entry *entry; ++ struct map_symbol_def *next; ++}; ++ ++/* For input sections, when writing a map file: head / tail of a linked ++ list of hash table entries for symbols defined in this section. */ ++typedef struct input_section_userdata_struct ++{ ++ struct map_symbol_def *map_symbol_def_head; ++ struct map_symbol_def **map_symbol_def_tail; ++ unsigned long map_symbol_def_count; ++} input_section_userdata_type; ++ ++#define get_userdata(x) ((x)->userdata) ++ ++ +typedef struct lang_wild_statement_struct lang_wild_statement_type; + +typedef void (*callback_t) (lang_wild_statement_type *, struct wildcard_list *, @@ -2650275,7 +2664368,9 @@ index 0000000..2dbec5a +struct lang_definedness_hash_entry +{ + struct bfd_hash_entry root; -+ int iteration; ++ unsigned int by_object : 1; ++ unsigned int by_script : 1; ++ unsigned int iteration : 1; +}; + +/* Used by place_orphan to keep track of orphan sections and statements. */ @@ -2650290,6 +2664385,14 @@ index 0000000..2dbec5a + lang_output_section_statement_type **os_tail; +}; + ++struct asneeded_minfo ++{ ++ struct asneeded_minfo *next; ++ const char *soname; ++ bfd *ref; ++ const char *name; ++}; ++ +extern struct lang_phdr *lang_phdr_list; +extern struct lang_nocrossrefs *nocrossref_list; +extern const char *output_target; @@ -2650297,7 +2664400,6 @@ index 0000000..2dbec5a +extern lang_statement_list_type lang_output_section_statement; +extern struct lang_input_statement_flags input_flags; +extern bfd_boolean lang_has_input_file; -+extern etree_type *base; +extern lang_statement_list_type *stat_ptr; +extern bfd_boolean delete_output_file_on_failure; + @@ -2650308,6 +2664410,9 @@ index 0000000..2dbec5a +extern lang_statement_list_type input_file_chain; + +extern int lang_statement_iteration; ++extern struct asneeded_minfo **asneeded_list_tail; ++ ++extern void (*output_bfd_hash_table_free_fn) (struct bfd_link_hash_table *); + +extern void lang_init + (void); @@ -2650394,6 +2664499,8 @@ index 0000000..2dbec5a + (const char *, lang_input_file_enum_type, const char *); +extern void lang_add_keepsyms_file + (const char *); ++extern lang_output_section_statement_type *lang_output_section_get ++ (const asection *); +extern lang_output_section_statement_type *lang_output_section_statement_lookup + (const char *, int, bfd_boolean); +extern lang_output_section_statement_type *next_matching_output_section_statement @@ -2650466,8 +2664573,7 @@ index 0000000..2dbec5a + (const char *); +extern const char *lang_get_output_target + (void); -+extern void lang_track_definedness (const char *); -+extern int lang_symbol_definition_iteration (const char *); ++extern struct lang_definedness_hash_entry *lang_symbol_defined (const char *); +extern void lang_update_definedness + (const char *, struct bfd_link_hash_entry *); + @@ -2650485,11 +2664591,11 @@ index 0000000..2dbec5a +#endif diff --git a/ld/ldlex-wrapper.c b/ld/ldlex-wrapper.c new file mode 100644 -index 0000000..0e5eba8 +index 0000000..52705b7 --- /dev/null +++ b/ld/ldlex-wrapper.c @@ -0,0 +1,26 @@ -+/* Copyright 2012 Free Software Foundation, Inc. ++/* Copyright (C) 2012-2014 Free Software Foundation, Inc. + + This file is part of the GNU Binutils. + @@ -2650517,13 +2664623,12 @@ index 0000000..0e5eba8 +#include "ldlex.c" diff --git a/ld/ldlex.h b/ld/ldlex.h new file mode 100644 -index 0000000..99f4282 +index 0000000..b2753c3 --- /dev/null +++ b/ld/ldlex.h -@@ -0,0 +1,181 @@ +@@ -0,0 +1,180 @@ +/* ldlex.h - -+ Copyright 1991, 1992, 1993, 1994, 1995, 1997, 2000, 2003, 2005, 2006, -+ 2007, 2012 Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + + This file is part of the GNU Binutils. + @@ -2650704,7 +2664809,7 @@ index 0000000..99f4282 +#endif diff --git a/ld/ldlex.l b/ld/ldlex.l new file mode 100644 -index 0000000..1695c27 +index 0000000..234867c --- /dev/null +++ b/ld/ldlex.l @@ -0,0 +1,707 @@ @@ -2650712,7 +2664817,7 @@ index 0000000..1695c27 + +%{ + -+/* Copyright 1991-2013 Free Software Foundation, Inc. ++/* Copyright (C) 1991-2014 Free Software Foundation, Inc. + Written by Steve Chamberlain of Cygnus Support. + + This file is part of the GNU Binutils. @@ -2651417,12 +2665522,12 @@ index 0000000..1695c27 +} diff --git a/ld/ldmain.c b/ld/ldmain.c new file mode 100644 -index 0000000..019df71 +index 0000000..2d987b8 --- /dev/null +++ b/ld/ldmain.c -@@ -0,0 +1,1469 @@ +@@ -0,0 +1,1497 @@ +/* Main program of GNU linker. -+ Copyright 1991-2013 Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + Written by Steve Chamberlain steve@cygnus.com + + This file is part of the GNU Binutils. @@ -2651594,6 +2665699,10 @@ index 0000000..019df71 +#endif + if (output_filename && delete_output_file_on_failure) + unlink_if_ordinary (output_filename); ++ ++ /* See open_output in ldlang.c. */ ++ if (output_bfd_hash_table_free_fn != NULL) ++ (*output_bfd_hash_table_free_fn) (link_info.hash); +} + +/* If there's a BFD assertion, we'll notice and exit with an error @@ -2651801,6 +2665910,13 @@ index 0000000..019df71 + + lang_final (); + ++ /* If the only command line argument has been -v or --version or --verbose ++ then ignore any input files provided by linker scripts and exit now. ++ We do not want to create an output file when the linker is just invoked ++ to provide version information. */ ++ if (argc == 2 && version_printed) ++ xexit (0); ++ + if (!lang_has_input_file) + { + if (version_printed || command_line.print_output_format) @@ -2651848,7 +2665964,14 @@ index 0000000..019df71 + output_cref (config.map_file != NULL ? config.map_file : stdout); + if (nocrossref_list != NULL) + check_nocrossrefs (); ++#if 0 ++ { ++ struct bfd_link_hash_entry * h; + ++ h = bfd_link_hash_lookup (link_info.hash, "__image_base__", 0,0,1); ++ fprintf (stderr, "lookup = %p val %lx\n", h, h ? h->u.def.value : 1); ++ } ++#endif + lang_finish (); + + /* Even if we're producing relocatable output, some non-fatal errors should @@ -2652264,7 +2666387,8 @@ index 0000000..019df71 + { + char buf[100]; + -+ sprintf (buf, _("Archive member included because of file (symbol)\n\n")); ++ sprintf (buf, _("Archive member included " ++ "to satisfy reference by file (symbol)\n\n")); + minfo ("%s", buf); + header_printed = TRUE; + } @@ -2652572,6 +2666696,25 @@ index 0000000..019df71 + asymbol **asymbols; +}; + ++/* Look through the relocs to see if we can find a plausible address ++ for SYMBOL in ABFD. Return TRUE if found. Otherwise return FALSE. */ ++ ++static bfd_boolean ++symbol_warning (const char *warning, const char *symbol, bfd *abfd) ++{ ++ struct warning_callback_info cinfo; ++ ++ if (!bfd_generic_link_read_symbols (abfd)) ++ einfo (_("%B%F: could not read symbols: %E\n"), abfd); ++ ++ cinfo.found = FALSE; ++ cinfo.warning = warning; ++ cinfo.symbol = symbol; ++ cinfo.asymbols = bfd_get_outsymbols (abfd); ++ bfd_map_over_sections (abfd, warning_find_reloc, &cinfo); ++ return cinfo.found; ++} ++ +/* This is called when there is a reference to a warning symbol. */ + +static bfd_boolean @@ -2652594,24 +2666737,14 @@ index 0000000..019df71 + einfo ("%P: %s%s\n", _("warning: "), warning); + else if (symbol == NULL) + einfo ("%B: %s%s\n", abfd, _("warning: "), warning); -+ else ++ else if (! symbol_warning (warning, symbol, abfd)) + { -+ struct warning_callback_info cinfo; -+ -+ /* Look through the relocs to see if we can find a plausible -+ address. */ -+ -+ if (!bfd_generic_link_read_symbols (abfd)) -+ einfo (_("%B%F: could not read symbols: %E\n"), abfd); -+ -+ cinfo.found = FALSE; -+ cinfo.warning = warning; -+ cinfo.symbol = symbol; -+ cinfo.asymbols = bfd_get_outsymbols (abfd); -+ bfd_map_over_sections (abfd, warning_find_reloc, &cinfo); -+ -+ if (! cinfo.found) -+ einfo ("%B: %s%s\n", abfd, _("warning: "), warning); ++ bfd *b; ++ /* Search all input files for a reference to SYMBOL. */ ++ for (b = info->input_bfds; b; b = b->link_next) ++ if (b != abfd && symbol_warning (warning, symbol, b)) ++ return TRUE; ++ einfo ("%B: %s%s\n", abfd, _("warning: "), warning); + } + + return TRUE; @@ -2652892,12 +2667025,12 @@ index 0000000..019df71 +} diff --git a/ld/ldmain.h b/ld/ldmain.h new file mode 100644 -index 0000000..90558a1 +index 0000000..dce9650 --- /dev/null +++ b/ld/ldmain.h @@ -0,0 +1,62 @@ +/* ldmain.h - -+ Copyright 1991-2013 Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + + This file is part of the GNU Binutils. + @@ -2652960,14 +2667093,12 @@ index 0000000..90558a1 +#endif diff --git a/ld/ldmisc.c b/ld/ldmisc.c new file mode 100644 -index 0000000..1b69ab1 +index 0000000..5e18013 --- /dev/null +++ b/ld/ldmisc.c -@@ -0,0 +1,530 @@ +@@ -0,0 +1,543 @@ +/* ldmisc.c -+ Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, -+ 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2010, 2011, 2012, 2013 -+ Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + Written by Steve Chamberlain of Cygnus Support. + + This file is part of the GNU Binutils. @@ -2653450,7 +2667581,22 @@ index 0000000..1b69ab1 + va_list arg; + + va_start (arg, fmt); -+ vfinfo (config.map_file, fmt, arg, FALSE); ++ if (fmt[0] == '%' && fmt[1] == '!' && fmt[2] == 0) ++ { ++ /* Stash info about --as-needed shared libraries. Print ++ later so they don't appear intermingled with archive ++ library info. */ ++ struct asneeded_minfo *m = xmalloc (sizeof *m); ++ ++ m->next = NULL; ++ m->soname = va_arg (arg, const char *); ++ m->ref = va_arg (arg, bfd *); ++ m->name = va_arg (arg, const char *); ++ *asneeded_list_tail = m; ++ asneeded_list_tail = &m->next; ++ } ++ else ++ vfinfo (config.map_file, fmt, arg, FALSE); + va_end (arg); + } +} @@ -2653496,13 +2667642,12 @@ index 0000000..1b69ab1 +} diff --git a/ld/ldmisc.h b/ld/ldmisc.h new file mode 100644 -index 0000000..82a498d +index 0000000..5103211 --- /dev/null +++ b/ld/ldmisc.h -@@ -0,0 +1,45 @@ +@@ -0,0 +1,44 @@ +/* ldmisc.h - -+ Copyright 1991, 1992, 1993, 1994, 1996, 1997, 2001, 2003, 2004, 2005, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + + This file is part of the GNU Binutils. + @@ -2653547,14 +2667692,12 @@ index 0000000..82a498d +#endif diff --git a/ld/ldver.c b/ld/ldver.c new file mode 100644 -index 0000000..d083b71 +index 0000000..5760cf0 --- /dev/null +++ b/ld/ldver.c -@@ -0,0 +1,61 @@ +@@ -0,0 +1,59 @@ +/* ldver.c -- Print linker version. -+ Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2001, 2002, -+ 2003, 2005, 2007, 2008, 2009, 2010, 2011, 2012, 2013 -+ Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + + This file is part of the GNU Binutils. + @@ -2653593,7 +2667736,7 @@ index 0000000..d083b71 + + if (noisy & 2) + { -+ printf (_("Copyright 2013 Free Software Foundation, Inc.\n")); ++ printf (_("Copyright (C) 2014 Free Software Foundation, Inc.\n")); + printf (_("\ +This program is free software; you may redistribute it under the terms of\n\ +the GNU General Public License version 3 or (at your option) a later version.\n\ @@ -2653614,13 +2667757,12 @@ index 0000000..d083b71 +} diff --git a/ld/ldver.h b/ld/ldver.h new file mode 100644 -index 0000000..0779ce8 +index 0000000..a2e9adb --- /dev/null +++ b/ld/ldver.h -@@ -0,0 +1,22 @@ +@@ -0,0 +1,21 @@ +/* ldver.h -- Header file for ldver.c. -+ Copyright 1991, 1992, 1993, 1996, 2001, 2003, 2005, 2007 -+ Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + + This file is part of the GNU Binutils. + @@ -2653642,14 +2667784,12 @@ index 0000000..0779ce8 +void ldversion (int); diff --git a/ld/ldwrite.c b/ld/ldwrite.c new file mode 100644 -index 0000000..aad0850 +index 0000000..963cb98 --- /dev/null +++ b/ld/ldwrite.c -@@ -0,0 +1,593 @@ +@@ -0,0 +1,591 @@ +/* ldwrite.c -- write out the linked file -+ Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000, 2002, -+ 2003, 2004, 2005, 2006, 2007, 2008, 2010, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + Written by Steve Chamberlain sac@cygnus.com + + This file is part of the GNU Binutils. @@ -2654241,12 +2668381,12 @@ index 0000000..aad0850 +} diff --git a/ld/ldwrite.h b/ld/ldwrite.h new file mode 100644 -index 0000000..521f467 +index 0000000..1402a7f --- /dev/null +++ b/ld/ldwrite.h @@ -0,0 +1,21 @@ +/* ldwrite.h - -+ Copyright 1991, 1992, 1993, 2003, 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + + This file is part of the GNU Binutils. + @@ -2654268,14 +2668408,12 @@ index 0000000..521f467 +extern void ldwrite (void); diff --git a/ld/lexsup.c b/ld/lexsup.c new file mode 100644 -index 0000000..2f71750 +index 0000000..a8c57d2 --- /dev/null +++ b/ld/lexsup.c -@@ -0,0 +1,1718 @@ +@@ -0,0 +1,1716 @@ +/* Parse options for the GNU linker. -+ Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, -+ 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2011, 2012 -+ Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + + This file is part of the GNU Binutils. + @@ -2655992,13 +2670130,12 @@ index 0000000..2f71750 +} diff --git a/ld/mri.c b/ld/mri.c new file mode 100644 -index 0000000..450cdf7 +index 0000000..70d4e02 --- /dev/null +++ b/ld/mri.c -@@ -0,0 +1,319 @@ +@@ -0,0 +1,320 @@ +/* mri.c -- handle MRI style linker scripts -+ Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 1999, 2000, 2001, -+ 2002, 2003, 2004, 2005, 2007, 2011 Free Software Foundation, Inc. ++ Copyright (C) 1991-2014 Free Software Foundation, Inc. + Contributed by Steve Chamberlain . + + This file is part of the GNU Binutils. @@ -2656043,6 +2670180,8 @@ index 0000000..450cdf7 +}; + +static unsigned int symbol_truncate = 10000; ++static etree_type *base; /* Relocation base - or null */ ++ +static struct section_name_struct *order; +static struct section_name_struct *only_load; +static struct section_name_struct *address; @@ -2656317,12 +2670456,12 @@ index 0000000..450cdf7 +} diff --git a/ld/mri.h b/ld/mri.h new file mode 100644 -index 0000000..24dd322 +index 0000000..5fe565a --- /dev/null +++ b/ld/mri.h @@ -0,0 +1,38 @@ +/* mri.h -- header file for MRI scripting functions -+ Copyright 1993, 1995, 1996, 2003, 2005, 2007 Free Software Foundation, Inc. ++ Copyright (C) 1993-2014 Free Software Foundation, Inc. + + This file is part of the GNU Binutils. + @@ -2656361,12 +2670500,12 @@ index 0000000..24dd322 +#endif diff --git a/ld/pe-dll.c b/ld/pe-dll.c new file mode 100644 -index 0000000..8777efb +index 0000000..0455606 --- /dev/null +++ b/ld/pe-dll.c @@ -0,0 +1,3451 @@ +/* Routines to help build PEI-format DLLs (Win32 etc) -+ Copyright 1998-2013 Free Software Foundation, Inc. ++ Copyright (C) 1998-2014 Free Software Foundation, Inc. + Written by DJ Delorie + + This file is part of the GNU Binutils. @@ -2659818,13 +2673957,12 @@ index 0000000..8777efb +} diff --git a/ld/pe-dll.h b/ld/pe-dll.h new file mode 100644 -index 0000000..4697390 +index 0000000..24ea302 --- /dev/null +++ b/ld/pe-dll.h -@@ -0,0 +1,74 @@ +@@ -0,0 +1,73 @@ +/* pe-dll.h: Header file for routines used to build Windows DLLs. -+ Copyright 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007, 2008, 2009 -+ Free Software Foundation, Inc. ++ Copyright (C) 1999-2014 Free Software Foundation, Inc. + + This file is part of the GNU Binutils. + @@ -2659898,12 +2674036,12 @@ index 0000000..4697390 +#endif /* PE_DLL_H */ diff --git a/ld/pep-dll.c b/ld/pep-dll.c new file mode 100644 -index 0000000..0e5e8b1 +index 0000000..8ccd52f --- /dev/null +++ b/ld/pep-dll.c @@ -0,0 +1,66 @@ +/* Routines to help build PEPI-format DLLs (Win64 etc) -+ Copyright 2006, 2007, 2009 Free Software Foundation, Inc. ++ Copyright (C) 2006-2014 Free Software Foundation, Inc. + Written by Kai Tietz, OneVision Software GmbH&CoKg. + + This file is part of the GNU Binutils. @@ -2659970,12 +2674108,12 @@ index 0000000..0e5e8b1 +#include "pe-dll.c" diff --git a/ld/pep-dll.h b/ld/pep-dll.h new file mode 100644 -index 0000000..1e7e3d6 +index 0000000..52127ff --- /dev/null +++ b/ld/pep-dll.h @@ -0,0 +1,61 @@ +/* pep-dll.h: Header file for routines used to build Windows DLLs. -+ Copyright 2006, 2007, 2008, 2009 Free Software Foundation, Inc. ++ Copyright (C) 2006-2014 Free Software Foundation, Inc. + Written by Kai Tietz, OneVision Software GmbH&CoKg. + + This file is part of the GNU Binutils. @@ -2660037,12 +2674175,12 @@ index 0000000..1e7e3d6 +#endif /* PEP_DLL_H */ diff --git a/ld/plugin.c b/ld/plugin.c new file mode 100644 -index 0000000..0d5339f +index 0000000..2a6d7c5 --- /dev/null +++ b/ld/plugin.c @@ -0,0 +1,1041 @@ +/* Plugin control for the GNU linker. -+ Copyright 2010, 2011, 2012, 2013 Free Software Foundation, Inc. ++ Copyright (C) 2010-2014 Free Software Foundation, Inc. + + This file is part of the GNU Binutils. + @@ -2661084,12 +2675222,12 @@ index 0000000..0d5339f +} diff --git a/ld/plugin.h b/ld/plugin.h new file mode 100644 -index 0000000..a227575 +index 0000000..beae7ab --- /dev/null +++ b/ld/plugin.h @@ -0,0 +1,72 @@ +/* Plugin control for the GNU linker. -+ Copyright 2010, 2011 Free Software Foundation, Inc. ++ Copyright (C) 2010-2014 Free Software Foundation, Inc. + + This file is part of the GNU Binutils. + @@ -2661162,13 +2675300,13 @@ index 0000000..a227575 +#endif /* !def GLD_PLUGIN_H */ diff --git a/ld/po/Make-in b/ld/po/Make-in new file mode 100644 -index 0000000..5e0798b +index 0000000..fb8bbed --- /dev/null +++ b/ld/po/Make-in @@ -0,0 +1,258 @@ +# Makefile for program source directory in GNU NLS utilities package. +# Copyright (C) 1995, 1996, 1997 by Ulrich Drepper -+# Copyright 2003, 2006, 2007, 2009 Free Software Foundation, Inc. ++# Copyright (C) 2003-2014 Free Software Foundation, Inc. +# +# This file may be copied and used freely without restrictions. It can +# be used in projects which are not available under the GNU Public License @@ -2661426,15 +2675564,17 @@ index 0000000..5e0798b +.NOEXPORT: diff --git a/ld/po/POTFILES.in b/ld/po/POTFILES.in new file mode 100644 -index 0000000..55cbd13 +index 0000000..fcc2894 --- /dev/null +++ b/ld/po/POTFILES.in -@@ -0,0 +1,35 @@ +@@ -0,0 +1,37 @@ +deffile.h +elf-hints-local.h +emultempl/armcoff.em +emultempl/pe.em +ld.h ++ldbuildid.c ++ldbuildid.h +ldcref.c +ldctor.c +ldctor.h @@ -2681811,10 +2695951,10 @@ index 0000000..d78d1c4 +#~ msgstr "%P%x: %s: 誤ã£ãŸ IR シンボルタイプ %d ã§ã™" diff --git a/ld/po/ld.pot b/ld/po/ld.pot new file mode 100644 -index 0000000..790cfdd +index 0000000..fb32163 --- /dev/null +++ b/ld/po/ld.pot -@@ -0,0 +1,2243 @@ +@@ -0,0 +1,2285 @@ +# SOME DESCRIPTIVE TITLE. +# Copyright (C) YEAR THE PACKAGE'S COPYRIGHT HOLDER +# This file is distributed under the same license as the PACKAGE package. @@ -2681825,7 +2695965,7 @@ index 0000000..790cfdd +msgstr "" +"Project-Id-Version: PACKAGE VERSION\n" +"Report-Msgid-Bugs-To: bug-binutils@gnu.org\n" -+"POT-Creation-Date: 2011-10-25 11:20+0100\n" ++"POT-Creation-Date: 2014-02-10 09:42+1030\n" +"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" +"Last-Translator: FULL NAME \n" +"Language-Team: LANGUAGE \n" @@ -2681850,200 +2695990,212 @@ index 0000000..790cfdd +msgid "Errors encountered processing file %s" +msgstr "" + -+#: emultempl/armcoff.em:192 emultempl/pe.em:1812 ++#: emultempl/armcoff.em:192 emultempl/pe.em:1827 +msgid "%P: warning: '--thumb-entry %s' is overriding '-e %s'\n" +msgstr "" + -+#: emultempl/armcoff.em:197 emultempl/pe.em:1817 ++#: emultempl/armcoff.em:197 emultempl/pe.em:1832 +msgid "%P: warning: cannot find thumb start symbol %s\n" +msgstr "" + -+#: emultempl/pe.em:419 ++#: emultempl/pe.em:425 +#, c-format +msgid "" +" --base_file Generate a base file for relocatable " +"DLLs\n" +msgstr "" + -+#: emultempl/pe.em:420 ++#: emultempl/pe.em:426 +#, c-format +msgid "" +" --dll Set image base to the default for DLLs\n" +msgstr "" + -+#: emultempl/pe.em:421 ++#: emultempl/pe.em:427 +#, c-format +msgid " --file-alignment Set file alignment\n" +msgstr "" + -+#: emultempl/pe.em:422 ++#: emultempl/pe.em:428 +#, c-format +msgid " --heap Set initial size of the heap\n" +msgstr "" + -+#: emultempl/pe.em:423 ++#: emultempl/pe.em:429 +#, c-format +msgid "" +" --image-base
Set start address of the executable\n" +msgstr "" + -+#: emultempl/pe.em:424 ++#: emultempl/pe.em:430 +#, c-format +msgid "" +" --major-image-version Set version number of the executable\n" +msgstr "" + -+#: emultempl/pe.em:425 ++#: emultempl/pe.em:431 +#, c-format +msgid " --major-os-version Set minimum required OS version\n" +msgstr "" + -+#: emultempl/pe.em:426 ++#: emultempl/pe.em:432 +#, c-format +msgid "" +" --major-subsystem-version Set minimum required OS subsystem " +"version\n" +msgstr "" + -+#: emultempl/pe.em:427 ++#: emultempl/pe.em:433 +#, c-format +msgid "" +" --minor-image-version Set revision number of the executable\n" +msgstr "" + -+#: emultempl/pe.em:428 ++#: emultempl/pe.em:434 +#, c-format +msgid " --minor-os-version Set minimum required OS revision\n" +msgstr "" + -+#: emultempl/pe.em:429 ++#: emultempl/pe.em:435 +#, c-format +msgid "" +" --minor-subsystem-version Set minimum required OS subsystem " +"revision\n" +msgstr "" + -+#: emultempl/pe.em:430 ++#: emultempl/pe.em:436 +#, c-format +msgid " --section-alignment Set section alignment\n" +msgstr "" + -+#: emultempl/pe.em:431 ++#: emultempl/pe.em:437 +#, c-format +msgid " --stack Set size of the initial stack\n" +msgstr "" + -+#: emultempl/pe.em:432 ++#: emultempl/pe.em:438 +#, c-format +msgid "" +" --subsystem [:] Set required OS subsystem [& version]\n" +msgstr "" + -+#: emultempl/pe.em:433 ++#: emultempl/pe.em:439 +#, c-format +msgid "" +" --support-old-code Support interworking with old code\n" +msgstr "" + -+#: emultempl/pe.em:434 ++#: emultempl/pe.em:440 +#, c-format +msgid "" +" --[no-]leading-underscore Set explicit symbol underscore prefix " +"mode\n" +msgstr "" + -+#: emultempl/pe.em:435 ++#: emultempl/pe.em:441 +#, c-format +msgid "" +" --thumb-entry= Set the entry point to be Thumb " +"\n" +msgstr "" + -+#: emultempl/pe.em:437 ++#: emultempl/pe.em:442 ++#, c-format ++msgid "" ++" --insert-timestamp Use a real timestamp rather than zero.\n" ++msgstr "" ++ ++#: emultempl/pe.em:443 ++#, c-format ++msgid "" ++" This makes binaries non-deterministic\n" ++msgstr "" ++ ++#: emultempl/pe.em:445 +#, c-format +msgid "" +" --add-stdcall-alias Export symbols with and without @nn\n" +msgstr "" + -+#: emultempl/pe.em:438 ++#: emultempl/pe.em:446 +#, c-format +msgid " --disable-stdcall-fixup Don't link _sym to _sym@nn\n" +msgstr "" + -+#: emultempl/pe.em:439 ++#: emultempl/pe.em:447 +#, c-format +msgid "" +" --enable-stdcall-fixup Link _sym to _sym@nn without warnings\n" +msgstr "" + -+#: emultempl/pe.em:440 ++#: emultempl/pe.em:448 +#, c-format +msgid "" +" --exclude-symbols sym,sym,... Exclude symbols from automatic export\n" +msgstr "" + -+#: emultempl/pe.em:441 ++#: emultempl/pe.em:449 +#, c-format +msgid "" +" --exclude-all-symbols Exclude all symbols from automatic " +"export\n" +msgstr "" + -+#: emultempl/pe.em:442 ++#: emultempl/pe.em:450 +#, c-format +msgid "" +" --exclude-libs lib,lib,... Exclude libraries from automatic " +"export\n" +msgstr "" + -+#: emultempl/pe.em:443 ++#: emultempl/pe.em:451 +#, c-format +msgid " --exclude-modules-for-implib mod,mod,...\n" +msgstr "" + -+#: emultempl/pe.em:444 ++#: emultempl/pe.em:452 +#, c-format +msgid "" +" Exclude objects, archive members from " +"auto\n" +msgstr "" + -+#: emultempl/pe.em:445 ++#: emultempl/pe.em:453 +#, c-format +msgid "" +" export, place into import library " +"instead.\n" +msgstr "" + -+#: emultempl/pe.em:446 ++#: emultempl/pe.em:454 +#, c-format +msgid "" +" --export-all-symbols Automatically export all globals to " +"DLL\n" +msgstr "" + -+#: emultempl/pe.em:447 ++#: emultempl/pe.em:455 +#, c-format +msgid " --kill-at Remove @nn from exported symbols\n" +msgstr "" + -+#: emultempl/pe.em:448 ++#: emultempl/pe.em:456 +#, c-format +msgid " --out-implib Generate import library\n" +msgstr "" + -+#: emultempl/pe.em:449 ++#: emultempl/pe.em:457 +#, c-format +msgid "" +" --output-def Generate a .DEF file for the built DLL\n" +msgstr "" + -+#: emultempl/pe.em:450 ++#: emultempl/pe.em:458 +#, c-format +msgid " --warn-duplicate-exports Warn about duplicate exports.\n" +msgstr "" + -+#: emultempl/pe.em:451 ++#: emultempl/pe.em:459 +#, c-format +msgid "" +" --compat-implib Create backward compatible import " @@ -2682051,7 +2696203,7 @@ index 0000000..790cfdd +" create __imp_ as well.\n" +msgstr "" + -+#: emultempl/pe.em:453 ++#: emultempl/pe.em:461 +#, c-format +msgid "" +" --enable-auto-image-base Automatically choose image base for " @@ -2682059,14 +2696211,14 @@ index 0000000..790cfdd +" unless user specifies one\n" +msgstr "" + -+#: emultempl/pe.em:455 ++#: emultempl/pe.em:463 +#, c-format +msgid "" +" --disable-auto-image-base Do not auto-choose image base. " +"(default)\n" +msgstr "" + -+#: emultempl/pe.em:456 ++#: emultempl/pe.em:464 +#, c-format +msgid "" +" --dll-search-prefix= When linking dynamically to a dll " @@ -2682076,21 +2696228,21 @@ index 0000000..790cfdd +" in preference to lib.dll \n" +msgstr "" + -+#: emultempl/pe.em:459 ++#: emultempl/pe.em:467 +#, c-format +msgid "" +" --enable-auto-import Do sophisticated linking of _sym to\n" +" __imp_sym for DATA references\n" +msgstr "" + -+#: emultempl/pe.em:461 ++#: emultempl/pe.em:469 +#, c-format +msgid "" +" --disable-auto-import Do not auto-import DATA items from " +"DLLs\n" +msgstr "" + -+#: emultempl/pe.em:462 ++#: emultempl/pe.em:470 +#, c-format +msgid "" +" --enable-runtime-pseudo-reloc Work around auto-import limitations by\n" @@ -2682099,7 +2696251,7 @@ index 0000000..790cfdd +" runtime.\n" +msgstr "" + -+#: emultempl/pe.em:465 ++#: emultempl/pe.em:473 +#, c-format +msgid "" +" --disable-runtime-pseudo-reloc Do not add runtime pseudo-relocations " @@ -2682107,7 +2696259,7 @@ index 0000000..790cfdd +" auto-imported DATA.\n" +msgstr "" + -+#: emultempl/pe.em:467 ++#: emultempl/pe.em:475 +#, c-format +msgid "" +" --enable-extra-pe-debug Enable verbose debug output when " @@ -2682116,21 +2696268,28 @@ index 0000000..790cfdd +"import)\n" +msgstr "" + -+#: emultempl/pe.em:470 ++#: emultempl/pe.em:478 +#, c-format +msgid "" +" --large-address-aware Executable supports virtual addresses\n" +" greater than 2 gigabytes\n" +msgstr "" + -+#: emultempl/pe.em:472 ++#: emultempl/pe.em:480 ++#, c-format ++msgid "" ++" --disable-large-address-aware Executable does not support virtual\n" ++" addresses greater than 2 gigabytes\n" ++msgstr "" ++ ++#: emultempl/pe.em:482 +#, c-format +msgid "" +" --enable-long-section-names Use long COFF section names even in\n" +" executable image files\n" +msgstr "" + -+#: emultempl/pe.em:474 ++#: emultempl/pe.em:484 +#, c-format +msgid "" +" --disable-long-section-names Never use long COFF section names, " @@ -2682138,106 +2696297,106 @@ index 0000000..790cfdd +" in object files\n" +msgstr "" + -+#: emultempl/pe.em:476 ++#: emultempl/pe.em:486 +#, c-format +msgid "" +" --dynamicbase\t\t\t Image base address may be relocated using\n" +"\t\t\t\t address space layout randomization (ASLR)\n" +msgstr "" + -+#: emultempl/pe.em:478 ++#: emultempl/pe.em:488 +#, c-format +msgid " --forceinteg\t\t Code integrity checks are enforced\n" +msgstr "" + -+#: emultempl/pe.em:479 ++#: emultempl/pe.em:489 +#, c-format +msgid " --nxcompat\t\t Image is compatible with data execution prevention\n" +msgstr "" + -+#: emultempl/pe.em:480 ++#: emultempl/pe.em:490 +#, c-format +msgid "" +" --no-isolation\t\t Image understands isolation but do not isolate the " +"image\n" +msgstr "" + -+#: emultempl/pe.em:481 ++#: emultempl/pe.em:491 +#, c-format +msgid "" +" --no-seh\t\t\t Image does not use SEH. No SE handler may\n" +"\t\t\t\t be called in this image\n" +msgstr "" + -+#: emultempl/pe.em:483 ++#: emultempl/pe.em:493 +#, c-format +msgid " --no-bind\t\t\t Do not bind this image\n" +msgstr "" + -+#: emultempl/pe.em:484 ++#: emultempl/pe.em:494 +#, c-format +msgid " --wdmdriver\t\t Driver uses the WDM model\n" +msgstr "" + -+#: emultempl/pe.em:485 ++#: emultempl/pe.em:495 +#, c-format +msgid " --tsaware Image is Terminal Server aware\n" +msgstr "" + -+#: emultempl/pe.em:614 ++#: emultempl/pe.em:624 +msgid "%P: warning: bad version number in -subsystem option\n" +msgstr "" + -+#: emultempl/pe.em:639 ++#: emultempl/pe.em:649 +msgid "%P%F: invalid subsystem type %s\n" +msgstr "" + -+#: emultempl/pe.em:660 ++#: emultempl/pe.em:670 +msgid "%P%F: invalid hex number for PE parameter '%s'\n" +msgstr "" + -+#: emultempl/pe.em:677 ++#: emultempl/pe.em:687 +msgid "%P%F: strange hex info for PE parameter '%s'\n" +msgstr "" + -+#: emultempl/pe.em:692 ++#: emultempl/pe.em:702 +msgid "%F%P: cannot open base file %s\n" +msgstr "" + -+#: emultempl/pe.em:965 ++#: emultempl/pe.em:981 +msgid "%P: warning, file alignment > section alignment.\n" +msgstr "" + -+#: emultempl/pe.em:978 ++#: emultempl/pe.em:994 +msgid "" +"%P: warning: --export-dynamic is not supported for PE targets, did you mean " +"--export-all-symbols?\n" +msgstr "" + -+#: emultempl/pe.em:1054 emultempl/pe.em:1081 ++#: emultempl/pe.em:1070 emultempl/pe.em:1097 +#, c-format +msgid "Warning: resolving %s by linking to %s\n" +msgstr "" + -+#: emultempl/pe.em:1059 emultempl/pe.em:1086 ++#: emultempl/pe.em:1075 emultempl/pe.em:1102 +msgid "Use --enable-stdcall-fixup to disable these warnings\n" +msgstr "" + -+#: emultempl/pe.em:1060 emultempl/pe.em:1087 ++#: emultempl/pe.em:1076 emultempl/pe.em:1103 +msgid "Use --disable-stdcall-fixup to disable these fixups\n" +msgstr "" + -+#: emultempl/pe.em:1106 ++#: emultempl/pe.em:1122 +#, c-format +msgid "%C: Cannot get section contents - auto-import exception\n" +msgstr "" + -+#: emultempl/pe.em:1146 ++#: emultempl/pe.em:1162 +#, c-format +msgid "Info: resolving %s by linking to %s (auto-import)\n" +msgstr "" + -+#: emultempl/pe.em:1153 ++#: emultempl/pe.em:1169 +msgid "" +"%P: warning: auto-importing has been activated without --enable-auto-import " +"specified on the command line.\n" @@ -2682245,44 +2696404,43 @@ index 0000000..790cfdd +"symbols from auto-imported DLLs.\n" +msgstr "" + -+#: emultempl/pe.em:1160 emultempl/pe.em:1366 emultempl/pe.em:1573 ldcref.c:490 -+#: ldcref.c:588 ldmain.c:1158 ldmisc.c:290 pe-dll.c:706 pe-dll.c:1254 -+#: pe-dll.c:1349 ++#: emultempl/pe.em:1176 emultempl/pe.em:1383 emultempl/pe.em:1590 ldcref.c:503 ++#: ldcref.c:601 ldmain.c:1183 ldmisc.c:300 pe-dll.c:710 pe-dll.c:1276 ++#: pe-dll.c:1371 +msgid "%B%F: could not read symbols: %E\n" +msgstr "" + -+#: emultempl/pe.em:1242 ++#: emultempl/pe.em:1258 +msgid "%F%P: cannot perform PE operations on non PE output file '%B'.\n" +msgstr "" + -+#: emultempl/pe.em:1616 ++#: emultempl/pe.em:1633 +#, c-format +msgid "Errors encountered processing file %s\n" +msgstr "" + -+#: emultempl/pe.em:1639 ++#: emultempl/pe.em:1656 +#, c-format +msgid "Errors encountered processing file %s for interworking\n" +msgstr "" + -+#: emultempl/pe.em:1701 ldexp.c:581 ldlang.c:3458 ldlang.c:6992 ldlang.c:7023 -+#: ldmain.c:1103 ++#: emultempl/pe.em:1718 ldexp.c:631 ldlang.c:3451 ldmain.c:1128 +msgid "%P%F: bfd_link_hash_lookup failed: %E\n" +msgstr "" + -+#: ldcref.c:168 ++#: ldcref.c:167 +msgid "%X%P: bfd_hash_table_init of cref table failed: %E\n" +msgstr "" + -+#: ldcref.c:174 ++#: ldcref.c:173 +msgid "%X%P: cref_hash_lookup failed: %E\n" +msgstr "" + -+#: ldcref.c:184 ++#: ldcref.c:183 +msgid "%X%P: cref alloc failed: %E\n" +msgstr "" + -+#: ldcref.c:366 ++#: ldcref.c:365 +#, c-format +msgid "" +"\n" @@ -2682290,25 +2696448,25 @@ index 0000000..790cfdd +"\n" +msgstr "" + -+#: ldcref.c:367 ++#: ldcref.c:366 +msgid "Symbol" +msgstr "" + -+#: ldcref.c:375 ++#: ldcref.c:374 +#, c-format +msgid "File\n" +msgstr "" + -+#: ldcref.c:379 ++#: ldcref.c:378 +#, c-format +msgid "No symbols\n" +msgstr "" + -+#: ldcref.c:532 ++#: ldcref.c:545 +msgid "%P: symbol `%T' missing from main hash table\n" +msgstr "" + -+#: ldcref.c:650 ldcref.c:657 ldmain.c:1192 ldmain.c:1199 ++#: ldcref.c:663 ldcref.c:670 ldmain.c:1217 ldmain.c:1224 +msgid "%B%F: could not read relocs: %E\n" +msgstr "" + @@ -2682316,7 +2696474,7 @@ index 0000000..790cfdd +#. in OUTSECNAME. This reloc is from a section which is +#. mapped into a section from which references to OUTSECNAME +#. are prohibited. We must report an error. -+#: ldcref.c:684 ++#: ldcref.c:697 +msgid "%X%C: prohibited cross reference from %s to `%T' in %s\n" +msgstr "" + @@ -2682336,7 +2696494,7 @@ index 0000000..790cfdd +msgid "%P%X: Unsupported size %d for set %s\n" +msgstr "" + -+#: ldctor.c:337 ++#: ldctor.c:339 +msgid "" +"\n" +"Set Symbol\n" @@ -2682366,158 +2696524,166 @@ index 0000000..790cfdd +msgid " no emulation specific options.\n" +msgstr "" + -+#: ldexp.c:314 ++#: ldexp.c:346 +msgid "%P: warning: address of `%s' isn't multiple of maximum page size\n" +msgstr "" + -+#: ldexp.c:407 ++#: ldexp.c:439 +#, c-format +msgid "%F%S %% by zero\n" +msgstr "" + -+#: ldexp.c:417 ++#: ldexp.c:449 +#, c-format +msgid "%F%S / by zero\n" +msgstr "" + -+#: ldexp.c:591 ++#: ldexp.c:643 +#, c-format +msgid "%X%S: unresolvable symbol `%s' referenced in expression\n" +msgstr "" + -+#: ldexp.c:605 ++#: ldexp.c:658 +#, c-format +msgid "%F%S: undefined symbol `%s' referenced in expression\n" +msgstr "" + -+#: ldexp.c:626 ldexp.c:643 ldexp.c:670 ++#: ldexp.c:680 ldexp.c:698 ldexp.c:726 +#, c-format +msgid "%F%S: undefined section `%s' referenced in expression\n" +msgstr "" + -+#: ldexp.c:697 ldexp.c:711 ++#: ldexp.c:756 ldexp.c:771 +#, c-format +msgid "%F%S: undefined MEMORY region `%s' referenced in expression\n" +msgstr "" + -+#: ldexp.c:722 ++#: ldexp.c:783 +#, c-format +msgid "%F%S: unknown constant `%s' referenced in expression\n" +msgstr "" + -+#: ldexp.c:787 ++#: ldexp.c:931 +#, c-format +msgid "%F%S can not PROVIDE assignment to location counter\n" +msgstr "" + -+#: ldexp.c:805 ++#: ldexp.c:957 +#, c-format +msgid "%F%S invalid assignment to location counter\n" +msgstr "" + -+#: ldexp.c:808 ++#: ldexp.c:961 +#, c-format -+msgid "%F%S assignment to location counter invalid outside of SECTION\n" ++msgid "%F%S assignment to location counter invalid outside of SECTIONS\n" +msgstr "" + -+#: ldexp.c:821 ++#: ldexp.c:980 +msgid "%F%S cannot move location counter backwards (from %V to %V)\n" +msgstr "" + -+#: ldexp.c:882 ++#: ldexp.c:1035 +msgid "%P%F:%s: hash creation failed\n" +msgstr "" + -+#: ldexp.c:1191 ldexp.c:1216 ldexp.c:1276 ++#: ldexp.c:1368 ldexp.c:1394 ldexp.c:1454 +#, c-format +msgid "%F%S: nonconstant expression for %s\n" +msgstr "" + -+#: ldfile.c:142 ++#: ldfile.c:132 +#, c-format +msgid "attempt to open %s failed\n" +msgstr "" + -+#: ldfile.c:144 ++#: ldfile.c:134 +#, c-format +msgid "attempt to open %s succeeded\n" +msgstr "" + -+#: ldfile.c:150 ++#: ldfile.c:140 +msgid "%F%P: invalid BFD target `%s'\n" +msgstr "" + -+#: ldfile.c:267 ldfile.c:296 ++#: ldfile.c:257 ldfile.c:286 +msgid "%P: skipping incompatible %s when searching for %s\n" +msgstr "" + -+#: ldfile.c:280 ++#: ldfile.c:270 +msgid "%F%P: attempted static link of dynamic object `%s'\n" +msgstr "" + -+#: ldfile.c:426 ++#: ldfile.c:408 +msgid "%P: cannot find %s (%s): %E\n" +msgstr "" + -+#: ldfile.c:429 ++#: ldfile.c:411 +msgid "%P: cannot find %s: %E\n" +msgstr "" + -+#: ldfile.c:464 ++#: ldfile.c:446 +msgid "%P: cannot find %s inside %s\n" +msgstr "" + -+#: ldfile.c:467 ++#: ldfile.c:449 +msgid "%P: cannot find %s\n" +msgstr "" + -+#: ldfile.c:486 ldfile.c:504 ++#: ldfile.c:471 +#, c-format +msgid "cannot find script file %s\n" +msgstr "" + -+#: ldfile.c:488 ldfile.c:506 ++#: ldfile.c:473 +#, c-format +msgid "opened script file %s\n" +msgstr "" + -+#: ldfile.c:636 ++#: ldfile.c:604 +msgid "%P%F: cannot open linker script file %s: %E\n" +msgstr "" + -+#: ldfile.c:701 ++#: ldfile.c:669 +msgid "%P%F: cannot represent machine `%s'\n" +msgstr "" + -+#: ldlang.c:1221 ldlang.c:1263 ldlang.c:3143 ++#: ldlang.c:1194 ldlang.c:1232 ldlang.c:3154 +msgid "%P%F: can not create hash table: %E\n" +msgstr "" + -+#: ldlang.c:1314 ++#: ldlang.c:1288 +msgid "%P:%S: warning: redeclaration of memory region `%s'\n" +msgstr "" + -+#: ldlang.c:1320 ++#: ldlang.c:1294 +msgid "%P:%S: warning: memory region `%s' not declared\n" +msgstr "" + -+#: ldlang.c:1354 ++#: ldlang.c:1329 +msgid "%F%P:%S: error: alias for default memory region\n" +msgstr "" + -+#: ldlang.c:1365 ++#: ldlang.c:1340 +msgid "%F%P:%S: error: redefinition of memory region alias `%s'\n" +msgstr "" + -+#: ldlang.c:1372 ++#: ldlang.c:1347 +msgid "%F%P:%S: error: memory region `%s' for alias `%s' does not exist\n" +msgstr "" + -+#: ldlang.c:1424 ldlang.c:1463 ++#: ldlang.c:1406 ldlang.c:1445 +msgid "%P%F: failed creating section `%s': %E\n" +msgstr "" + -+#: ldlang.c:2025 ++#: ldlang.c:2000 ++#, c-format ++msgid "" ++"\n" ++"As-needed library included to satisfy reference by file (symbol)\n" ++"\n" ++msgstr "" ++ ++#: ldlang.c:2068 +#, c-format +msgid "" +"\n" @@ -2682525,30 +2696691,30 @@ index 0000000..790cfdd +"\n" +msgstr "" + -+#: ldlang.c:2033 ++#: ldlang.c:2076 +msgid "" +"\n" +"Memory Configuration\n" +"\n" +msgstr "" + -+#: ldlang.c:2035 ++#: ldlang.c:2078 +msgid "Name" +msgstr "" + -+#: ldlang.c:2035 ++#: ldlang.c:2078 +msgid "Origin" +msgstr "" + -+#: ldlang.c:2035 ++#: ldlang.c:2078 +msgid "Length" +msgstr "" + -+#: ldlang.c:2035 ++#: ldlang.c:2078 +msgid "Attributes" +msgstr "" + -+#: ldlang.c:2075 ++#: ldlang.c:2118 +#, c-format +msgid "" +"\n" @@ -2682556,514 +2696722,505 @@ index 0000000..790cfdd +"\n" +msgstr "" + -+#: ldlang.c:2141 ++#: ldlang.c:2168 +msgid "%P%F: Illegal use of `%s' section\n" +msgstr "" + -+#: ldlang.c:2150 ++#: ldlang.c:2177 +msgid "%P%F: output format %s cannot represent section called %s\n" +msgstr "" + -+#: ldlang.c:2728 ++#: ldlang.c:2739 +msgid "%B: file not recognized: %E\n" +msgstr "" + -+#: ldlang.c:2729 ++#: ldlang.c:2740 +msgid "%B: matching formats:" +msgstr "" + -+#: ldlang.c:2736 ++#: ldlang.c:2747 +msgid "%F%B: file not recognized: %E\n" +msgstr "" + -+#: ldlang.c:2810 ++#: ldlang.c:2821 +msgid "%F%B: member %B in archive is not an object\n" +msgstr "" + -+#: ldlang.c:2825 ldlang.c:2839 -+msgid "%F%B: could not read symbols: %E\n" ++#: ldlang.c:2836 ldlang.c:2850 ++msgid "%F%B: error adding symbols: %E\n" +msgstr "" + -+#: ldlang.c:3113 ++#: ldlang.c:3124 +msgid "" +"%P: warning: could not find any targets that match endianness requirement\n" +msgstr "" + -+#: ldlang.c:3127 ++#: ldlang.c:3138 +msgid "%P%F: target %s not found\n" +msgstr "" + -+#: ldlang.c:3129 ++#: ldlang.c:3140 +msgid "%P%F: cannot open output file %s: %E\n" +msgstr "" + -+#: ldlang.c:3135 ++#: ldlang.c:3146 +msgid "%P%F:%s: can not make object file: %E\n" +msgstr "" + -+#: ldlang.c:3139 ++#: ldlang.c:3150 +msgid "%P%F:%s: can not set architecture: %E\n" +msgstr "" + -+#: ldlang.c:3309 ++#: ldlang.c:3322 +msgid "%P: warning: %s contains output sections; did you forget -T?\n" +msgstr "" + -+#: ldlang.c:3350 -+msgid "%P%F: bfd_hash_lookup failed creating symbol %s\n" -+msgstr "" -+ -+#: ldlang.c:3368 ++#: ldlang.c:3372 +msgid "%P%F: bfd_hash_allocate failed creating symbol %s\n" +msgstr "" + -+#: ldlang.c:3764 ++#: ldlang.c:3402 ++msgid "%P%F: bfd_hash_lookup failed creating symbol %s\n" ++msgstr "" ++ ++#: ldlang.c:3759 +msgid "%F%P: %s not found for insert\n" +msgstr "" + -+#: ldlang.c:3979 ++#: ldlang.c:3974 +msgid " load address 0x%V" +msgstr "" + -+#: ldlang.c:4254 ++#: ldlang.c:4201 +msgid "%W (size before relaxing)\n" +msgstr "" + -+#: ldlang.c:4345 ++#: ldlang.c:4292 +#, c-format +msgid "Address of section %s set to " +msgstr "" + -+#: ldlang.c:4498 ++#: ldlang.c:4445 +#, c-format +msgid "Fail with %d\n" +msgstr "" + -+#: ldlang.c:4785 ++#: ldlang.c:4733 +msgid "" +"%X%P: section %s loaded at [%V,%V] overlaps section %s loaded at [%V,%V]\n" +msgstr "" + -+#: ldlang.c:4801 ++#: ldlang.c:4749 +msgid "%X%P: region `%s' overflowed by %ld bytes\n" +msgstr "" + -+#: ldlang.c:4824 ++#: ldlang.c:4772 +msgid "%X%P: address 0x%v of %B section `%s' is not within region `%s'\n" +msgstr "" + -+#: ldlang.c:4835 ++#: ldlang.c:4783 +msgid "%X%P: %B section `%s' will not fit in region `%s'\n" +msgstr "" + -+#: ldlang.c:4892 ++#: ldlang.c:4840 +#, c-format +msgid "" +"%F%S: non constant or forward reference address expression for section %s\n" +msgstr "" + -+#: ldlang.c:4917 ++#: ldlang.c:4865 +msgid "%P%X: Internal error on COFF shared library section %s\n" +msgstr "" + -+#: ldlang.c:4974 ++#: ldlang.c:4923 +msgid "%P%F: error: no memory region specified for loadable section `%s'\n" +msgstr "" + -+#: ldlang.c:4979 ++#: ldlang.c:4928 +msgid "%P: warning: no memory region specified for loadable section `%s'\n" +msgstr "" + -+#: ldlang.c:5001 ++#: ldlang.c:4951 +msgid "%P: warning: changing start of section %s by %lu bytes\n" +msgstr "" + -+#: ldlang.c:5078 ++#: ldlang.c:5040 +msgid "%P: warning: dot moved backwards before `%s'\n" +msgstr "" + -+#: ldlang.c:5244 ++#: ldlang.c:5212 +msgid "%P%F: can't relax section: %E\n" +msgstr "" + -+#: ldlang.c:5573 ++#: ldlang.c:5557 +msgid "%F%P: invalid data statement\n" +msgstr "" + -+#: ldlang.c:5606 ++#: ldlang.c:5590 +msgid "%F%P: invalid reloc statement\n" +msgstr "" + -+#: ldlang.c:5725 ++#: ldlang.c:5802 +msgid "%P%F: gc-sections requires either an entry or an undefined symbol\n" +msgstr "" + -+#: ldlang.c:5750 ++#: ldlang.c:5827 +msgid "%P%F:%s: can't set start address\n" +msgstr "" + -+#: ldlang.c:5763 ldlang.c:5782 ++#: ldlang.c:5840 ldlang.c:5859 +msgid "%P%F: can't set start address\n" +msgstr "" + -+#: ldlang.c:5775 ++#: ldlang.c:5852 +msgid "%P: warning: cannot find entry symbol %s; defaulting to %V\n" +msgstr "" + -+#: ldlang.c:5787 ++#: ldlang.c:5864 +msgid "%P: warning: cannot find entry symbol %s; not setting start address\n" +msgstr "" + -+#: ldlang.c:5842 ++#: ldlang.c:5916 +msgid "" +"%P%F: Relocatable linking with relocations from format %s (%B) to format %s " +"(%B) is not supported\n" +msgstr "" + -+#: ldlang.c:5852 ++#: ldlang.c:5926 +msgid "" +"%P%X: %s architecture of input file `%B' is incompatible with %s output\n" +msgstr "" + -+#: ldlang.c:5874 ++#: ldlang.c:5948 +msgid "%P%X: failed to merge target specific data of file %B\n" +msgstr "" + -+#: ldlang.c:5945 ++#: ldlang.c:6019 +msgid "%P%F: Could not define common symbol `%T': %E\n" +msgstr "" + -+#: ldlang.c:5957 ++#: ldlang.c:6031 +msgid "" +"\n" +"Allocating common symbols\n" +msgstr "" + -+#: ldlang.c:5958 ++#: ldlang.c:6032 +msgid "" +"Common symbol size file\n" +"\n" +msgstr "" + -+#: ldlang.c:6104 ++#: ldlang.c:6178 +msgid "%P%F: invalid syntax in flags\n" +msgstr "" + -+#: ldlang.c:6566 ++#: ldlang.c:6304 ++msgid "%F%P:%S: error: align with input and explicit align specified\n" ++msgstr "" ++ ++#: ldlang.c:6645 +msgid "%P%F: Failed to create hash table\n" +msgstr "" + -+#: ldlang.c:6589 ++#: ldlang.c:6668 +msgid "%P%F: %s: plugin reported error after all symbols read\n" +msgstr "" + -+#: ldlang.c:6905 ++#: ldlang.c:6991 +msgid "%P%F: multiple STARTUP files\n" +msgstr "" + -+#: ldlang.c:6951 ++#: ldlang.c:7037 +msgid "%X%P:%S: section has both a load address and a load region\n" +msgstr "" + -+#: ldlang.c:7138 ++#: ldlang.c:7162 +msgid "" +"%X%P:%S: PHDRS and FILEHDR are not supported when prior PT_LOAD headers lack " +"them\n" +msgstr "" + -+#: ldlang.c:7210 ++#: ldlang.c:7235 +msgid "%F%P: no sections assigned to phdrs\n" +msgstr "" + -+#: ldlang.c:7248 ++#: ldlang.c:7273 +msgid "%F%P: bfd_record_phdr failed: %E\n" +msgstr "" + -+#: ldlang.c:7268 ++#: ldlang.c:7293 +msgid "%X%P: section `%s' assigned to non-existent phdr `%s'\n" +msgstr "" + -+#: ldlang.c:7677 ++#: ldlang.c:7705 +msgid "%X%P: unknown language `%s' in version information\n" +msgstr "" + -+#: ldlang.c:7822 ++#: ldlang.c:7850 +msgid "" +"%X%P: anonymous version tag cannot be combined with other version tags\n" +msgstr "" + -+#: ldlang.c:7831 ++#: ldlang.c:7859 +msgid "%X%P: duplicate version tag `%s'\n" +msgstr "" + -+#: ldlang.c:7852 ldlang.c:7861 ldlang.c:7879 ldlang.c:7889 ++#: ldlang.c:7880 ldlang.c:7889 ldlang.c:7907 ldlang.c:7917 +msgid "%X%P: duplicate expression `%s' in version information\n" +msgstr "" + -+#: ldlang.c:7929 ++#: ldlang.c:7957 +msgid "%X%P: unable to find version dependency `%s'\n" +msgstr "" + -+#: ldlang.c:7952 ++#: ldlang.c:7980 +msgid "%X%P: unable to read .exports section contents\n" +msgstr "" + -+#: ldlang.c:8076 ++#: ldlang.c:8104 +msgid "%X%P: unknown feature `%s'\n" +msgstr "" + -+#: ldmain.c:239 ++#: ldmain.c:246 +msgid "%X%P: can't set BFD default target to `%s': %E\n" +msgstr "" + -+#: ldmain.c:303 lexsup.c:1071 -+msgid "%P%F: %s: error loading plugin\n" ++#: ldmain.c:336 ++msgid "built in linker script" +msgstr "" + -+#: ldmain.c:340 ++#: ldmain.c:346 +msgid "using external linker script:" +msgstr "" + -+#: ldmain.c:342 ++#: ldmain.c:348 +msgid "using internal linker script:" +msgstr "" + -+#: ldmain.c:379 ++#: ldmain.c:385 +msgid "%P%F: no input files\n" +msgstr "" + -+#: ldmain.c:383 ++#: ldmain.c:389 +msgid "%P: mode %s\n" +msgstr "" + -+#: ldmain.c:399 ++#: ldmain.c:405 +msgid "%P%F: cannot open map file %s: %E\n" +msgstr "" + -+#: ldmain.c:431 ++#: ldmain.c:437 +msgid "%P: link errors found, deleting executable `%s'\n" +msgstr "" + -+#: ldmain.c:440 ++#: ldmain.c:446 +msgid "%F%B: final close failed: %E\n" +msgstr "" + -+#: ldmain.c:466 ++#: ldmain.c:472 +msgid "%X%P: unable to open for source of copy `%s'\n" +msgstr "" + -+#: ldmain.c:469 ++#: ldmain.c:475 +msgid "%X%P: unable to open for destination of copy `%s'\n" +msgstr "" + -+#: ldmain.c:476 ++#: ldmain.c:482 +msgid "%P: Error writing file `%s'\n" +msgstr "" + -+#: ldmain.c:481 pe-dll.c:1739 ++#: ldmain.c:487 pe-dll.c:1761 +#, c-format +msgid "%P: Error closing file `%s'\n" +msgstr "" + -+#: ldmain.c:498 ++#: ldmain.c:504 +#, c-format +msgid "%s: total time in link: %ld.%06ld\n" +msgstr "" + -+#: ldmain.c:501 ++#: ldmain.c:507 +#, c-format +msgid "%s: data size %ld\n" +msgstr "" + -+#: ldmain.c:585 ++#: ldmain.c:591 +msgid "%P%F: missing argument to -m\n" +msgstr "" + -+#: ldmain.c:633 ldmain.c:653 ldmain.c:685 ++#: ldmain.c:639 ldmain.c:656 ldmain.c:676 ldmain.c:708 +msgid "%P%F: bfd_hash_table_init failed: %E\n" +msgstr "" + -+#: ldmain.c:637 ldmain.c:657 ++#: ldmain.c:643 ldmain.c:660 ldmain.c:680 +msgid "%P%F: bfd_hash_lookup failed: %E\n" +msgstr "" + -+#: ldmain.c:671 ++#: ldmain.c:694 +msgid "%X%P: error: duplicate retain-symbols-file\n" +msgstr "" + -+#: ldmain.c:715 ++#: ldmain.c:738 +msgid "%P%F: bfd_hash_lookup for insertion failed: %E\n" +msgstr "" + -+#: ldmain.c:720 ++#: ldmain.c:743 +msgid "%P: `-retain-symbols-file' overrides `-s' and `-S'\n" +msgstr "" + -+#: ldmain.c:820 ++#: ldmain.c:844 +#, c-format +msgid "" -+"Archive member included because of file (symbol)\n" ++"Archive member included to satisfy reference by file (symbol)\n" +"\n" +msgstr "" + -+#: ldmain.c:926 ++#: ldmain.c:951 +msgid "%X%C: multiple definition of `%T'\n" +msgstr "" + -+#: ldmain.c:929 ++#: ldmain.c:954 +msgid "%D: first defined here\n" +msgstr "" + -+#: ldmain.c:933 ++#: ldmain.c:958 +msgid "%P: Disabling relaxation: it will not work with multiple definitions\n" +msgstr "" + -+#: ldmain.c:987 ++#: ldmain.c:1012 +msgid "%B: warning: definition of `%T' overriding common\n" +msgstr "" + -+#: ldmain.c:990 ++#: ldmain.c:1015 +msgid "%B: warning: common is here\n" +msgstr "" + -+#: ldmain.c:997 ++#: ldmain.c:1022 +msgid "%B: warning: common of `%T' overridden by definition\n" +msgstr "" + -+#: ldmain.c:1000 ++#: ldmain.c:1025 +msgid "%B: warning: defined here\n" +msgstr "" + -+#: ldmain.c:1007 ++#: ldmain.c:1032 +msgid "%B: warning: common of `%T' overridden by larger common\n" +msgstr "" + -+#: ldmain.c:1010 ++#: ldmain.c:1035 +msgid "%B: warning: larger common is here\n" +msgstr "" + -+#: ldmain.c:1014 ++#: ldmain.c:1039 +msgid "%B: warning: common of `%T' overriding smaller common\n" +msgstr "" + -+#: ldmain.c:1017 ++#: ldmain.c:1042 +msgid "%B: warning: smaller common is here\n" +msgstr "" + -+#: ldmain.c:1021 ++#: ldmain.c:1046 +msgid "%B: warning: multiple common of `%T'\n" +msgstr "" + -+#: ldmain.c:1023 ++#: ldmain.c:1048 +msgid "%B: warning: previous common is here\n" +msgstr "" + -+#: ldmain.c:1043 ldmain.c:1081 ++#: ldmain.c:1068 ldmain.c:1106 +msgid "%P: warning: global constructor %s used\n" +msgstr "" + -+#: ldmain.c:1091 ++#: ldmain.c:1116 +msgid "%P%F: BFD backend error: BFD_RELOC_CTOR unsupported\n" +msgstr "" + +#. We found a reloc for the symbol we are looking for. -+#: ldmain.c:1145 ldmain.c:1147 ldmain.c:1149 ldmain.c:1167 ldmain.c:1212 ++#: ldmain.c:1170 ldmain.c:1172 ldmain.c:1174 ldmain.c:1192 ldmain.c:1237 +msgid "warning: " +msgstr "" + -+#: ldmain.c:1248 -+msgid "%F%P: bfd_hash_table_init failed: %E\n" -+msgstr "" -+ -+#: ldmain.c:1255 -+msgid "%F%P: bfd_hash_lookup failed: %E\n" -+msgstr "" -+ -+#: ldmain.c:1276 ++#: ldmain.c:1290 +msgid "%X%C: undefined reference to `%T'\n" +msgstr "" + -+#: ldmain.c:1279 ++#: ldmain.c:1293 +msgid "%C: warning: undefined reference to `%T'\n" +msgstr "" + -+#: ldmain.c:1285 ++#: ldmain.c:1299 +msgid "%X%D: more undefined references to `%T' follow\n" +msgstr "" + -+#: ldmain.c:1288 ++#: ldmain.c:1302 +msgid "%D: warning: more undefined references to `%T' follow\n" +msgstr "" + -+#: ldmain.c:1299 ++#: ldmain.c:1313 +msgid "%X%B: undefined reference to `%T'\n" +msgstr "" + -+#: ldmain.c:1302 ++#: ldmain.c:1316 +msgid "%B: warning: undefined reference to `%T'\n" +msgstr "" + -+#: ldmain.c:1308 ++#: ldmain.c:1322 +msgid "%X%B: more undefined references to `%T' follow\n" +msgstr "" + -+#: ldmain.c:1311 ++#: ldmain.c:1325 +msgid "%B: warning: more undefined references to `%T' follow\n" +msgstr "" + -+#: ldmain.c:1350 ++#: ldmain.c:1364 +msgid " additional relocation overflows omitted from the output\n" +msgstr "" + -+#: ldmain.c:1363 ++#: ldmain.c:1377 +msgid " relocation truncated to fit: %s against undefined symbol `%T'" +msgstr "" + -+#: ldmain.c:1368 ++#: ldmain.c:1382 +msgid "" +" relocation truncated to fit: %s against symbol `%T' defined in %A section " +"in %B" +msgstr "" + -+#: ldmain.c:1380 ++#: ldmain.c:1394 +msgid " relocation truncated to fit: %s against `%T'" +msgstr "" + -+#: ldmain.c:1397 ++#: ldmain.c:1411 +msgid "%X%H: dangerous relocation: %s\n" +msgstr "" + -+#: ldmain.c:1412 ++#: ldmain.c:1426 +msgid "%X%H: reloc refers to symbol `%T' which is not being output\n" +msgstr "" + -+#: ldmisc.c:151 ++#: ldmisc.c:154 +#, c-format +msgid "no symbol" +msgstr "" + -+#: ldmisc.c:248 -+#, c-format -+msgid "built in linker script:%u" -+msgstr "" -+ -+#: ldmisc.c:329 ++#: ldmisc.c:339 +msgid "%B: In function `%T':\n" +msgstr "" + -+#: ldmisc.c:464 ++#: ldmisc.c:474 +msgid "%F%P: internal error %s %d\n" +msgstr "" + -+#: ldmisc.c:513 ++#: ldmisc.c:538 +msgid "%P: internal error: aborting at %s line %d in %s\n" +msgstr "" + -+#: ldmisc.c:516 ++#: ldmisc.c:541 +msgid "%P: internal error: aborting at %s line %d\n" +msgstr "" + -+#: ldmisc.c:518 ++#: ldmisc.c:543 +msgid "%P%F: please report this bug\n" +msgstr "" + @@ -2683075,7 +2697232,7 @@ index 0000000..790cfdd + +#: ldver.c:43 +#, c-format -+msgid "Copyright 2011 Free Software Foundation, Inc.\n" ++msgid "Copyright 2014 Free Software Foundation, Inc.\n" +msgstr "" + +#: ldver.c:44 @@ -2683092,614 +2697249,627 @@ index 0000000..790cfdd +msgid " Supported emulations:\n" +msgstr "" + -+#: ldwrite.c:62 ldwrite.c:207 ++#: ldwrite.c:62 ldwrite.c:208 +msgid "%P%F: bfd_new_link_order failed\n" +msgstr "" + -+#: ldwrite.c:365 ++#: ldwrite.c:366 +msgid "%F%P: cannot create split section name for %s\n" +msgstr "" + -+#: ldwrite.c:377 ++#: ldwrite.c:378 +msgid "%F%P: clone section failed: %E\n" +msgstr "" + -+#: ldwrite.c:418 ++#: ldwrite.c:419 +#, c-format +msgid "%8x something else\n" +msgstr "" + -+#: ldwrite.c:588 ++#: ldwrite.c:589 +msgid "%F%P: final link failed: %E\n" +msgstr "" + -+#: lexsup.c:220 lexsup.c:374 ++#: lexsup.c:104 lexsup.c:261 +msgid "KEYWORD" +msgstr "" + -+#: lexsup.c:220 ++#: lexsup.c:104 +msgid "Shared library control for HP/UX compatibility" +msgstr "" + -+#: lexsup.c:223 ++#: lexsup.c:107 +msgid "ARCH" +msgstr "" + -+#: lexsup.c:223 ++#: lexsup.c:107 +msgid "Set architecture" +msgstr "" + -+#: lexsup.c:225 lexsup.c:493 ++#: lexsup.c:109 lexsup.c:380 +msgid "TARGET" +msgstr "" + -+#: lexsup.c:225 ++#: lexsup.c:109 +msgid "Specify target for following input files" +msgstr "" + -+#: lexsup.c:228 lexsup.c:279 lexsup.c:303 lexsup.c:316 lexsup.c:318 -+#: lexsup.c:447 lexsup.c:509 lexsup.c:572 lexsup.c:585 ++#: lexsup.c:112 lexsup.c:163 lexsup.c:190 lexsup.c:203 lexsup.c:205 ++#: lexsup.c:334 lexsup.c:396 lexsup.c:463 lexsup.c:476 +msgid "FILE" +msgstr "" + -+#: lexsup.c:228 ++#: lexsup.c:112 +msgid "Read MRI format linker script" +msgstr "" + -+#: lexsup.c:230 ++#: lexsup.c:114 +msgid "Force common symbols to be defined" +msgstr "" + -+#: lexsup.c:234 lexsup.c:553 lexsup.c:555 lexsup.c:557 lexsup.c:559 ++#: lexsup.c:118 lexsup.c:440 lexsup.c:442 lexsup.c:444 lexsup.c:446 ++#: lexsup.c:448 lexsup.c:450 +msgid "ADDRESS" +msgstr "" + -+#: lexsup.c:234 ++#: lexsup.c:118 +msgid "Set start address" +msgstr "" + -+#: lexsup.c:236 ++#: lexsup.c:120 +msgid "Export all dynamic symbols" +msgstr "" + -+#: lexsup.c:238 ++#: lexsup.c:122 +msgid "Undo the effect of --export-dynamic" +msgstr "" + -+#: lexsup.c:240 ++#: lexsup.c:124 +msgid "Link big-endian objects" +msgstr "" + -+#: lexsup.c:242 ++#: lexsup.c:126 +msgid "Link little-endian objects" +msgstr "" + -+#: lexsup.c:244 lexsup.c:247 ++#: lexsup.c:128 lexsup.c:131 +msgid "SHLIB" +msgstr "" + -+#: lexsup.c:244 ++#: lexsup.c:128 +msgid "Auxiliary filter for shared object symbol table" +msgstr "" + -+#: lexsup.c:247 ++#: lexsup.c:131 +msgid "Filter for shared object symbol table" +msgstr "" + -+#: lexsup.c:250 ++#: lexsup.c:134 +msgid "Ignored" +msgstr "" + -+#: lexsup.c:252 ++#: lexsup.c:136 +msgid "SIZE" +msgstr "" + -+#: lexsup.c:252 ++#: lexsup.c:136 +msgid "Small data size (if no size, same as --shared)" +msgstr "" + -+#: lexsup.c:255 ++#: lexsup.c:139 +msgid "FILENAME" +msgstr "" + -+#: lexsup.c:255 ++#: lexsup.c:139 +msgid "Set internal name of shared library" +msgstr "" + -+#: lexsup.c:257 ++#: lexsup.c:141 +msgid "PROGRAM" +msgstr "" + -+#: lexsup.c:257 ++#: lexsup.c:141 +msgid "Set PROGRAM as the dynamic linker to use" +msgstr "" + -+#: lexsup.c:260 ++#: lexsup.c:144 +msgid "LIBNAME" +msgstr "" + -+#: lexsup.c:260 ++#: lexsup.c:144 +msgid "Search for library LIBNAME" +msgstr "" + -+#: lexsup.c:262 ++#: lexsup.c:146 +msgid "DIRECTORY" +msgstr "" + -+#: lexsup.c:262 ++#: lexsup.c:146 +msgid "Add DIRECTORY to library search path" +msgstr "" + -+#: lexsup.c:265 ++#: lexsup.c:149 +msgid "Override the default sysroot location" +msgstr "" + -+#: lexsup.c:267 ++#: lexsup.c:151 +msgid "EMULATION" +msgstr "" + -+#: lexsup.c:267 ++#: lexsup.c:151 +msgid "Set emulation" +msgstr "" + -+#: lexsup.c:269 ++#: lexsup.c:153 +msgid "Print map file on standard output" +msgstr "" + -+#: lexsup.c:271 ++#: lexsup.c:155 +msgid "Do not page align data" +msgstr "" + -+#: lexsup.c:273 ++#: lexsup.c:157 +msgid "Do not page align data, do not make text readonly" +msgstr "" + -+#: lexsup.c:276 ++#: lexsup.c:160 +msgid "Page align data, make text readonly" +msgstr "" + -+#: lexsup.c:279 ++#: lexsup.c:163 +msgid "Set output file name" +msgstr "" + -+#: lexsup.c:281 ++#: lexsup.c:165 +msgid "Optimize output file" +msgstr "" + -+#: lexsup.c:284 ++#: lexsup.c:168 +msgid "PLUGIN" +msgstr "" + -+#: lexsup.c:284 ++#: lexsup.c:168 +msgid "Load named plugin" +msgstr "" + -+#: lexsup.c:286 ++#: lexsup.c:170 +msgid "ARG" +msgstr "" + -+#: lexsup.c:286 ++#: lexsup.c:170 +msgid "Send arg to last-loaded plugin" +msgstr "" + -+#: lexsup.c:288 lexsup.c:291 ++#: lexsup.c:172 lexsup.c:175 +msgid "Ignored for GCC LTO option compatibility" +msgstr "" + -+#: lexsup.c:295 ++#: lexsup.c:179 ++msgid "Ignored for GCC linker option compatibility" ++msgstr "" ++ ++#: lexsup.c:182 +msgid "Ignored for SVR4 compatibility" +msgstr "" + -+#: lexsup.c:299 ++#: lexsup.c:186 +msgid "Generate relocatable output" +msgstr "" + -+#: lexsup.c:303 ++#: lexsup.c:190 +msgid "Just link symbols (if directory, same as --rpath)" +msgstr "" + -+#: lexsup.c:306 ++#: lexsup.c:193 +msgid "Strip all symbols" +msgstr "" + -+#: lexsup.c:308 ++#: lexsup.c:195 +msgid "Strip debugging symbols" +msgstr "" + -+#: lexsup.c:310 ++#: lexsup.c:197 +msgid "Strip symbols in discarded sections" +msgstr "" + -+#: lexsup.c:312 ++#: lexsup.c:199 +msgid "Do not strip symbols in discarded sections" +msgstr "" + -+#: lexsup.c:314 ++#: lexsup.c:201 +msgid "Trace file opens" +msgstr "" + -+#: lexsup.c:316 ++#: lexsup.c:203 +msgid "Read linker script" +msgstr "" + -+#: lexsup.c:318 ++#: lexsup.c:205 +msgid "Read default linker script" +msgstr "" + -+#: lexsup.c:322 lexsup.c:340 lexsup.c:424 lexsup.c:445 lexsup.c:546 -+#: lexsup.c:575 lexsup.c:614 ++#: lexsup.c:209 lexsup.c:227 lexsup.c:311 lexsup.c:332 lexsup.c:433 ++#: lexsup.c:466 lexsup.c:505 lexsup.c:508 +msgid "SYMBOL" +msgstr "" + -+#: lexsup.c:322 ++#: lexsup.c:209 +msgid "Start with undefined reference to SYMBOL" +msgstr "" + -+#: lexsup.c:325 ++#: lexsup.c:212 +msgid "[=SECTION]" +msgstr "" + -+#: lexsup.c:326 ++#: lexsup.c:213 +msgid "Don't merge input [SECTION | orphan] sections" +msgstr "" + -+#: lexsup.c:328 ++#: lexsup.c:215 +msgid "Build global constructor/destructor tables" +msgstr "" + -+#: lexsup.c:330 ++#: lexsup.c:217 +msgid "Print version information" +msgstr "" + -+#: lexsup.c:332 ++#: lexsup.c:219 +msgid "Print version and emulation information" +msgstr "" + -+#: lexsup.c:334 ++#: lexsup.c:221 +msgid "Discard all local symbols" +msgstr "" + -+#: lexsup.c:336 ++#: lexsup.c:223 +msgid "Discard temporary local symbols (default)" +msgstr "" + -+#: lexsup.c:338 ++#: lexsup.c:225 +msgid "Don't discard any local symbols" +msgstr "" + -+#: lexsup.c:340 ++#: lexsup.c:227 +msgid "Trace mentions of SYMBOL" +msgstr "" + -+#: lexsup.c:342 lexsup.c:511 lexsup.c:513 ++#: lexsup.c:229 lexsup.c:398 lexsup.c:400 +msgid "PATH" +msgstr "" + -+#: lexsup.c:342 ++#: lexsup.c:229 +msgid "Default search path for Solaris compatibility" +msgstr "" + -+#: lexsup.c:345 ++#: lexsup.c:232 +msgid "Start a group" +msgstr "" + -+#: lexsup.c:347 ++#: lexsup.c:234 +msgid "End a group" +msgstr "" + -+#: lexsup.c:351 ++#: lexsup.c:238 +msgid "Accept input files whose architecture cannot be determined" +msgstr "" + -+#: lexsup.c:355 ++#: lexsup.c:242 +msgid "Reject input files whose architecture is unknown" +msgstr "" + -+#: lexsup.c:367 ++#: lexsup.c:254 +msgid "Only set DT_NEEDED for following dynamic libs if used" +msgstr "" + -+#: lexsup.c:370 ++#: lexsup.c:257 +msgid "" +"Always set DT_NEEDED for dynamic libraries mentioned on\n" +" the command line" +msgstr "" + -+#: lexsup.c:374 ++#: lexsup.c:261 +msgid "Ignored for SunOS compatibility" +msgstr "" + -+#: lexsup.c:376 ++#: lexsup.c:263 +msgid "Link against shared libraries" +msgstr "" + -+#: lexsup.c:382 ++#: lexsup.c:269 +msgid "Do not link against shared libraries" +msgstr "" + -+#: lexsup.c:390 ++#: lexsup.c:277 +msgid "Bind global references locally" +msgstr "" + -+#: lexsup.c:392 ++#: lexsup.c:279 +msgid "Bind global function references locally" +msgstr "" + -+#: lexsup.c:394 ++#: lexsup.c:281 +msgid "Check section addresses for overlaps (default)" +msgstr "" + -+#: lexsup.c:397 ++#: lexsup.c:284 +msgid "Do not check section addresses for overlaps" +msgstr "" + -+#: lexsup.c:401 ++#: lexsup.c:288 +msgid "Copy DT_NEEDED links mentioned inside DSOs that follow" +msgstr "" + -+#: lexsup.c:405 ++#: lexsup.c:292 +msgid "Do not copy DT_NEEDED links mentioned inside DSOs that follow" +msgstr "" + -+#: lexsup.c:409 ++#: lexsup.c:296 +msgid "Output cross reference table" +msgstr "" + -+#: lexsup.c:411 ++#: lexsup.c:298 +msgid "SYMBOL=EXPRESSION" +msgstr "" + -+#: lexsup.c:411 ++#: lexsup.c:298 +msgid "Define a symbol" +msgstr "" + -+#: lexsup.c:413 ++#: lexsup.c:300 +msgid "[=STYLE]" +msgstr "" + -+#: lexsup.c:413 ++#: lexsup.c:300 +msgid "Demangle symbol names [using STYLE]" +msgstr "" + -+#: lexsup.c:416 ++#: lexsup.c:303 +msgid "Generate embedded relocs" +msgstr "" + -+#: lexsup.c:418 ++#: lexsup.c:305 +msgid "Treat warnings as errors" +msgstr "" + -+#: lexsup.c:421 ++#: lexsup.c:308 +msgid "Do not treat warnings as errors (default)" +msgstr "" + -+#: lexsup.c:424 ++#: lexsup.c:311 +msgid "Call SYMBOL at unload-time" +msgstr "" + -+#: lexsup.c:426 ++#: lexsup.c:313 +msgid "Force generation of file with .exe suffix" +msgstr "" + -+#: lexsup.c:428 ++#: lexsup.c:315 +msgid "Remove unused sections (on some targets)" +msgstr "" + -+#: lexsup.c:431 ++#: lexsup.c:318 +msgid "Don't remove unused sections (default)" +msgstr "" + -+#: lexsup.c:434 ++#: lexsup.c:321 +msgid "List removed unused sections on stderr" +msgstr "" + -+#: lexsup.c:437 ++#: lexsup.c:324 +msgid "Do not list removed unused sections" +msgstr "" + -+#: lexsup.c:440 ++#: lexsup.c:327 +msgid "Set default hash table size close to " +msgstr "" + -+#: lexsup.c:443 ++#: lexsup.c:330 +msgid "Print option help" +msgstr "" + -+#: lexsup.c:445 ++#: lexsup.c:332 +msgid "Call SYMBOL at load-time" +msgstr "" + -+#: lexsup.c:447 ++#: lexsup.c:334 +msgid "Write a map file" +msgstr "" + -+#: lexsup.c:449 ++#: lexsup.c:336 +msgid "Do not define Common storage" +msgstr "" + -+#: lexsup.c:451 ++#: lexsup.c:338 +msgid "Do not demangle symbol names" +msgstr "" + -+#: lexsup.c:453 ++#: lexsup.c:340 +msgid "Use less memory and more disk I/O" +msgstr "" + -+#: lexsup.c:455 ++#: lexsup.c:342 +msgid "Do not allow unresolved references in object files" +msgstr "" + -+#: lexsup.c:458 ++#: lexsup.c:345 +msgid "Allow unresolved references in shared libraries" +msgstr "" + -+#: lexsup.c:462 ++#: lexsup.c:349 +msgid "Do not allow unresolved references in shared libs" +msgstr "" + -+#: lexsup.c:466 ++#: lexsup.c:353 +msgid "Allow multiple definitions" +msgstr "" + -+#: lexsup.c:468 ++#: lexsup.c:355 +msgid "Disallow undefined version" +msgstr "" + -+#: lexsup.c:470 ++#: lexsup.c:357 +msgid "Create default symbol version" +msgstr "" + -+#: lexsup.c:473 ++#: lexsup.c:360 +msgid "Create default symbol version for imported symbols" +msgstr "" + -+#: lexsup.c:476 ++#: lexsup.c:363 +msgid "Don't warn about mismatched input files" +msgstr "" + -+#: lexsup.c:479 ++#: lexsup.c:366 +msgid "Don't warn on finding an incompatible library" +msgstr "" + -+#: lexsup.c:482 ++#: lexsup.c:369 +msgid "Turn off --whole-archive" +msgstr "" + -+#: lexsup.c:484 ++#: lexsup.c:371 +msgid "Create an output file even if errors occur" +msgstr "" + -+#: lexsup.c:489 ++#: lexsup.c:376 +msgid "" +"Only use library directories specified on\n" +" the command line" +msgstr "" + -+#: lexsup.c:493 ++#: lexsup.c:380 +msgid "Specify target of output file" +msgstr "" + -+#: lexsup.c:496 ++#: lexsup.c:383 +msgid "Print default output format" +msgstr "" + -+#: lexsup.c:498 ++#: lexsup.c:385 +msgid "Ignored for Linux compatibility" +msgstr "" + -+#: lexsup.c:501 ++#: lexsup.c:388 +msgid "Reduce memory overheads, possibly taking much longer" +msgstr "" + -+#: lexsup.c:504 ++#: lexsup.c:391 +msgid "Reduce code size by using target specific optimizations" +msgstr "" + -+#: lexsup.c:506 ++#: lexsup.c:393 +msgid "Do not use relaxation techniques to reduce code size" +msgstr "" + -+#: lexsup.c:509 ++#: lexsup.c:396 +msgid "Keep only symbols listed in FILE" +msgstr "" + -+#: lexsup.c:511 ++#: lexsup.c:398 +msgid "Set runtime shared library search path" +msgstr "" + -+#: lexsup.c:513 ++#: lexsup.c:400 +msgid "Set link time shared library search path" +msgstr "" + -+#: lexsup.c:516 ++#: lexsup.c:403 +msgid "Create a shared library" +msgstr "" + -+#: lexsup.c:520 ++#: lexsup.c:407 +msgid "Create a position independent executable" +msgstr "" + -+#: lexsup.c:524 ++#: lexsup.c:411 +msgid "[=ascending|descending]" +msgstr "" + -+#: lexsup.c:525 ++#: lexsup.c:412 +msgid "Sort common symbols by alignment [in specified order]" +msgstr "" + -+#: lexsup.c:530 ++#: lexsup.c:417 +msgid "name|alignment" +msgstr "" + -+#: lexsup.c:531 ++#: lexsup.c:418 +msgid "Sort sections by name or maximum alignment" +msgstr "" + -+#: lexsup.c:533 ++#: lexsup.c:420 +msgid "COUNT" +msgstr "" + -+#: lexsup.c:533 ++#: lexsup.c:420 +msgid "How many tags to reserve in .dynamic section" +msgstr "" + -+#: lexsup.c:536 ++#: lexsup.c:423 +msgid "[=SIZE]" +msgstr "" + -+#: lexsup.c:536 ++#: lexsup.c:423 +msgid "Split output sections every SIZE octets" +msgstr "" + -+#: lexsup.c:539 ++#: lexsup.c:426 +msgid "[=COUNT]" +msgstr "" + -+#: lexsup.c:539 ++#: lexsup.c:426 +msgid "Split output sections every COUNT relocs" +msgstr "" + -+#: lexsup.c:542 ++#: lexsup.c:429 +msgid "Print memory usage statistics" +msgstr "" + -+#: lexsup.c:544 ++#: lexsup.c:431 +msgid "Display target specific options" +msgstr "" + -+#: lexsup.c:546 ++#: lexsup.c:433 +msgid "Do task level linking" +msgstr "" + -+#: lexsup.c:548 ++#: lexsup.c:435 +msgid "Use same format as native linker" +msgstr "" + -+#: lexsup.c:550 ++#: lexsup.c:437 +msgid "SECTION=ADDRESS" +msgstr "" + -+#: lexsup.c:550 ++#: lexsup.c:437 +msgid "Set address of named section" +msgstr "" + -+#: lexsup.c:553 ++#: lexsup.c:440 +msgid "Set address of .bss section" +msgstr "" + -+#: lexsup.c:555 ++#: lexsup.c:442 +msgid "Set address of .data section" +msgstr "" + -+#: lexsup.c:557 ++#: lexsup.c:444 +msgid "Set address of .text section" +msgstr "" + -+#: lexsup.c:559 ++#: lexsup.c:446 +msgid "Set address of text segment" +msgstr "" + -+#: lexsup.c:562 ++#: lexsup.c:448 ++msgid "Set address of rodata segment" ++msgstr "" ++ ++#: lexsup.c:450 ++msgid "Set address of ldata segment" ++msgstr "" ++ ++#: lexsup.c:453 +msgid "" +"How to handle unresolved symbols. is:\n" +" ignore-all, report-all, ignore-in-object-" @@ -2683707,113 +2697877,117 @@ index 0000000..790cfdd +" ignore-in-shared-libs" +msgstr "" + -+#: lexsup.c:567 ++#: lexsup.c:458 +msgid "[=NUMBER]" +msgstr "" + -+#: lexsup.c:568 ++#: lexsup.c:459 +msgid "Output lots of information during link" +msgstr "" + -+#: lexsup.c:572 ++#: lexsup.c:463 +msgid "Read version information script" +msgstr "" + -+#: lexsup.c:575 ++#: lexsup.c:466 +msgid "" +"Take export symbols list from .exports, using\n" +" SYMBOL as the version." +msgstr "" + -+#: lexsup.c:579 ++#: lexsup.c:470 +msgid "Add data symbols to dynamic list" +msgstr "" + -+#: lexsup.c:581 ++#: lexsup.c:472 +msgid "Use C++ operator new/delete dynamic list" +msgstr "" + -+#: lexsup.c:583 ++#: lexsup.c:474 +msgid "Use C++ typeinfo dynamic list" +msgstr "" + -+#: lexsup.c:585 ++#: lexsup.c:476 +msgid "Read dynamic list" +msgstr "" + -+#: lexsup.c:587 ++#: lexsup.c:478 +msgid "Warn about duplicate common symbols" +msgstr "" + -+#: lexsup.c:589 ++#: lexsup.c:480 +msgid "Warn if global constructors/destructors are seen" +msgstr "" + -+#: lexsup.c:592 ++#: lexsup.c:483 +msgid "Warn if the multiple GP values are used" +msgstr "" + -+#: lexsup.c:594 ++#: lexsup.c:485 +msgid "Warn only once per undefined symbol" +msgstr "" + -+#: lexsup.c:596 ++#: lexsup.c:487 +msgid "Warn if start of section changes due to alignment" +msgstr "" + -+#: lexsup.c:599 ++#: lexsup.c:490 +msgid "Warn if shared object has DT_TEXTREL" +msgstr "" + -+#: lexsup.c:602 ++#: lexsup.c:493 +msgid "Warn if an object has alternate ELF machine code" +msgstr "" + -+#: lexsup.c:606 ++#: lexsup.c:497 +msgid "Report unresolved symbols as warnings" +msgstr "" + -+#: lexsup.c:609 ++#: lexsup.c:500 +msgid "Report unresolved symbols as errors" +msgstr "" + -+#: lexsup.c:611 ++#: lexsup.c:502 +msgid "Include all objects from following archives" +msgstr "" + -+#: lexsup.c:614 ++#: lexsup.c:505 +msgid "Use wrapper functions for SYMBOL" +msgstr "" + -+#: lexsup.c:763 ++#: lexsup.c:509 ++msgid "Unresolved SYMBOL will not cause an error or warning" ++msgstr "" ++ ++#: lexsup.c:659 +msgid "%P: unrecognized option '%s'\n" +msgstr "" + -+#: lexsup.c:767 ++#: lexsup.c:663 +msgid "%P%F: use the --help option for usage information\n" +msgstr "" + -+#: lexsup.c:785 ++#: lexsup.c:681 +msgid "%P%F: unrecognized -a option `%s'\n" +msgstr "" + -+#: lexsup.c:798 ++#: lexsup.c:694 +msgid "%P%F: unrecognized -assert option `%s'\n" +msgstr "" + -+#: lexsup.c:841 -+msgid "%F%P: unknown demangling style `%s'" ++#: lexsup.c:735 ++msgid "%F%P: unknown demangling style `%s'\n" +msgstr "" + -+#: lexsup.c:907 lexsup.c:1341 ++#: lexsup.c:801 lexsup.c:1239 +msgid "%P%F: invalid number `%s'\n" +msgstr "" + -+#: lexsup.c:1005 ++#: lexsup.c:899 +msgid "%P%F: bad --unresolved-symbols option: %s\n" +msgstr "" + -+#: lexsup.c:1076 ++#: lexsup.c:968 +msgid "%P%F: bad -plugin-opt option\n" +msgstr "" + @@ -2683825,112 +2697999,112 @@ index 0000000..790cfdd +#. an error message here. We cannot just make this a warning, +#. increment optind, and continue because getopt is too confused +#. and will seg-fault the next time around. -+#: lexsup.c:1093 ++#: lexsup.c:985 +msgid "%P%F: bad -rpath option\n" +msgstr "" + -+#: lexsup.c:1207 ++#: lexsup.c:1099 +msgid "%P%F: -shared not supported\n" +msgstr "" + -+#: lexsup.c:1216 ++#: lexsup.c:1108 +msgid "%P%F: -pie not supported\n" +msgstr "" + -+#: lexsup.c:1224 ++#: lexsup.c:1116 +msgid "descending" +msgstr "" + -+#: lexsup.c:1226 ++#: lexsup.c:1118 +msgid "ascending" +msgstr "" + -+#: lexsup.c:1229 ++#: lexsup.c:1121 +msgid "%P%F: invalid common section sorting option: %s\n" +msgstr "" + -+#: lexsup.c:1233 ++#: lexsup.c:1125 +msgid "name" +msgstr "" + -+#: lexsup.c:1235 ++#: lexsup.c:1127 +msgid "alignment" +msgstr "" + -+#: lexsup.c:1238 ++#: lexsup.c:1130 +msgid "%P%F: invalid section sorting option: %s\n" +msgstr "" + -+#: lexsup.c:1272 ++#: lexsup.c:1164 +msgid "%P%F: invalid argument to option \"--section-start\"\n" +msgstr "" + -+#: lexsup.c:1279 ++#: lexsup.c:1171 +msgid "%P%F: missing argument(s) to option \"--section-start\"\n" +msgstr "" + -+#: lexsup.c:1513 ++#: lexsup.c:1414 +msgid "%P%F: group ended before it began (--help for usage)\n" +msgstr "" + -+#: lexsup.c:1541 ++#: lexsup.c:1442 +msgid "%P%X: --hash-size needs a numeric argument\n" +msgstr "" + -+#: lexsup.c:1572 ++#: lexsup.c:1473 +msgid "%P%F: -r and -shared may not be used together\n" +msgstr "" + -+#: lexsup.c:1615 ++#: lexsup.c:1516 +msgid "%P%F: -F may not be used without -shared\n" +msgstr "" + -+#: lexsup.c:1617 ++#: lexsup.c:1518 +msgid "%P%F: -f may not be used without -shared\n" +msgstr "" + -+#: lexsup.c:1661 lexsup.c:1674 ++#: lexsup.c:1562 lexsup.c:1575 +msgid "%P%F: invalid hex number `%s'\n" +msgstr "" + -+#: lexsup.c:1710 ++#: lexsup.c:1611 +#, c-format +msgid "Usage: %s [options] file...\n" +msgstr "" + -+#: lexsup.c:1712 ++#: lexsup.c:1613 +#, c-format +msgid "Options:\n" +msgstr "" + -+#: lexsup.c:1790 ++#: lexsup.c:1691 +#, c-format +msgid " @FILE" +msgstr "" + -+#: lexsup.c:1793 ++#: lexsup.c:1694 +#, c-format +msgid "Read options from FILE\n" +msgstr "" + +#. Note: Various tools (such as libtool) depend upon the +#. format of the listings below - do not change them. -+#: lexsup.c:1798 ++#: lexsup.c:1699 +#, c-format +msgid "%s: supported targets:" +msgstr "" + -+#: lexsup.c:1806 ++#: lexsup.c:1707 +#, c-format +msgid "%s: supported emulations: " +msgstr "" + -+#: lexsup.c:1811 ++#: lexsup.c:1712 +#, c-format +msgid "%s: emulation specific options:\n" +msgstr "" + -+#: lexsup.c:1816 ++#: lexsup.c:1717 +#, c-format +msgid "Report bugs to %s\n" +msgstr "" @@ -2683939,124 +2698113,132 @@ index 0000000..790cfdd +msgid "%P%F: unknown format type %s\n" +msgstr "" + -+#: pe-dll.c:431 ++#: pe-dll.c:430 +#, c-format +msgid "%XUnsupported PEI architecture: %s\n" +msgstr "" + -+#: pe-dll.c:788 ++#: pe-dll.c:799 +#, c-format +msgid "%XCannot export %s: invalid export name\n" +msgstr "" + -+#: pe-dll.c:845 ++#: pe-dll.c:851 +#, c-format +msgid "%XError, duplicate EXPORT with ordinals: %s (%d vs %d)\n" +msgstr "" + -+#: pe-dll.c:852 ++#: pe-dll.c:858 +#, c-format +msgid "Warning, duplicate EXPORT: %s\n" +msgstr "" + -+#: pe-dll.c:939 ++#: pe-dll.c:961 +#, c-format +msgid "%XCannot export %s: symbol not defined\n" +msgstr "" + -+#: pe-dll.c:945 ++#: pe-dll.c:967 +#, c-format +msgid "%XCannot export %s: symbol wrong type (%d vs %d)\n" +msgstr "" + -+#: pe-dll.c:952 ++#: pe-dll.c:974 +#, c-format +msgid "%XCannot export %s: symbol not found\n" +msgstr "" + -+#: pe-dll.c:1066 ++#: pe-dll.c:1088 +#, c-format +msgid "%XError, ordinal used twice: %d (%s vs %s)\n" +msgstr "" + -+#: pe-dll.c:1456 ++#: pe-dll.c:1478 +#, c-format +msgid "%XError: %d-bit reloc in dll\n" +msgstr "" + -+#: pe-dll.c:1584 ++#: pe-dll.c:1606 +#, c-format +msgid "%s: Can't open output def file %s\n" +msgstr "" + -+#: pe-dll.c:1735 ++#: pe-dll.c:1757 +#, c-format +msgid "; no contents available\n" +msgstr "" + -+#: pe-dll.c:2662 ++#: pe-dll.c:2684 +msgid "" +"%C: variable '%T' can't be auto-imported. Please read the documentation for " +"ld's --enable-auto-import for details.\n" +msgstr "" + -+#: pe-dll.c:2692 ++#: pe-dll.c:2714 +#, c-format +msgid "%XCan't open .lib file: %s\n" +msgstr "" + -+#: pe-dll.c:2697 ++#: pe-dll.c:2720 +#, c-format +msgid "Creating library file: %s\n" +msgstr "" + -+#: pe-dll.c:2726 ++#: pe-dll.c:2749 +#, c-format +msgid "%Xbfd_openr %s: %E\n" +msgstr "" + -+#: pe-dll.c:2738 ++#: pe-dll.c:2761 +#, c-format +msgid "%X%s(%s): can't find member in non-archive file" +msgstr "" + -+#: pe-dll.c:2750 ++#: pe-dll.c:2773 +#, c-format +msgid "%X%s(%s): can't find member in archive" +msgstr "" + -+#: pe-dll.c:3189 ++#: pe-dll.c:3356 +#, c-format +msgid "%XError: can't use long section names on this arch\n" +msgstr "" + -+#: plugin.c:177 plugin.c:211 ++#: plugin.c:185 plugin.c:218 +msgid "" +msgstr "" + -+#: plugin.c:250 ++#: plugin.c:199 plugin.c:814 ++msgid "%P%F: %s: error loading plugin: %s\n" ++msgstr "" ++ ++#: plugin.c:257 +#, c-format +msgid "could not create dummy IR bfd: %F%E\n" +msgstr "" + -+#: plugin.c:343 ++#: plugin.c:350 +msgid "%P%F: %s: non-ELF symbol in ELF BFD!\n" +msgstr "" + -+#: plugin.c:347 ++#: plugin.c:354 +msgid "%P%F: unknown ELF symbol visibility: %d!\n" +msgstr "" + -+#: plugin.c:586 ++#: plugin.c:591 +msgid "%P: %B: symbol `%s' definition: %d, visibility: %d, resolution: %d\n" +msgstr "" + -+#: plugin.c:863 ++#: plugin.c:821 ++msgid "%P%F: %s: plugin error: %d\n" ++msgstr "" ++ ++#: plugin.c:871 +msgid "%P%F: %s: plugin reported error claiming file\n" +msgstr "" + -+#: plugin.c:934 -+msgid "%P: %s: error in plugin cleanup (ignored)\n" ++#: plugin.c:936 ++msgid "%P: %s: error in plugin cleanup: %d (ignored)\n" +msgstr "" diff --git a/ld/po/sv.po b/ld/po/sv.po new file mode 100644 @@ -2696326,7 +2710508,7 @@ index 0000000..89ff919 +EOF diff --git a/ld/scripttempl/README b/ld/scripttempl/README new file mode 100644 -index 0000000..e20f931 +index 0000000..3b5df9a --- /dev/null +++ b/ld/scripttempl/README @@ -0,0 +1,10 @@ @@ -2696335,7 +2710517,7 @@ index 0000000..e20f931 +EMULATION.sc, to generate EMULATION.{x,xr,xu,xn,xbn} -- the script +files for default, -r, -Ur, -n, -N. + -+Copyright (C) 2012 Free Software Foundation, Inc. ++Copyright (C) 2012-2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -2702157,7 +2716339,7 @@ index 0000000..a737481 +EOF diff --git a/ld/scripttempl/elfmicroblaze.sc b/ld/scripttempl/elfmicroblaze.sc new file mode 100644 -index 0000000..a54b891 +index 0000000..8d2e6f2 --- /dev/null +++ b/ld/scripttempl/elfmicroblaze.sc @@ -0,0 +1,222 @@ @@ -2702346,7 +2716528,7 @@ index 0000000..a54b891 + ${RELOCATING+*(.bss.*)} + ${RELOCATING+*(.gnu.linkonce.b.*)} + ${RELOCATING+*(COMMON)} -+ ${RELOCATING+. = ALIGN(4);} ++ ${RELOCATING+. = ALIGN(. != 0 ? 4 : 1);} + + ${RELOCATING+PROVIDE (__bss_end = .);} + @@ -2702366,7 +2716548,7 @@ index 0000000..a54b891 + .stack : { + ${RELOCATING+ _stack_end = .;} + ${RELOCATING+ . += _STACK_SIZE;} -+ ${RELOCATING+ . = ALIGN(8);} ++ ${RELOCATING+ . = ALIGN(. != 0 ? 8 : 1);} + ${RELOCATING+ _stack = .;} + ${RELOCATING+ _end = .;} + } @@ -2708213,55 +2722395,12 @@ index 0000000..3fb9bce + ${OTHER_SECTIONS} +} +EOF -diff --git a/ld/scripttempl/or32.sc b/ld/scripttempl/or32.sc -new file mode 100644 -index 0000000..2825b1e ---- /dev/null -+++ b/ld/scripttempl/or32.sc -@@ -0,0 +1,37 @@ -+cat < +@@ -0,0 +1,506 @@ ++2014-07-16 H.J. Lu + -+ PR binutils/16317 -+ * ld-elf/linkinfo1.s: New file. -+ * ld-elf/linkinfo1a.d: Likewise. -+ * ld-elf/linkinfo1b.d: Likewise. ++ PR binutils/17154 ++ * ld-ifunc/pr17154-i386.d: New file. ++ * ld-ifunc/pr17154-x86-64.d: Likewise. ++ * ld-ifunc/pr17154-x86.s: Likewise. ++ * ld-x86-64/bnd-ifunc-2.d: Likewise. ++ * ld-x86-64/bnd-ifunc-2.s: Likewise. ++ * ld-x86-64/mpx.exp: Run bnd-ifunc-2. ++ * ld-x86-64/tlsdesc-nacl.pd: Updated. ++ * ld-x86-64/tlsdesc.pd: Likewise. + -+2013-12-18 Vidya Praveen ++2014-06-09 Ryan Mansfield + -+ * lib/ld-lib.exp (check_lto_available): Support cflags, ldflags and -+ test by compiling for an executable rather than shared library. ++ * config/default.exp (GASP): Remove. + -+2013-12-13 Vidya Praveen ++2014-06-03 Alan Modra + -+ * lib/ld-lib.exp (default_ld_link): Use ldflags from board description -+ file. -+ (default_ld_simple_link): Likewise. -+ (default_ld_compile): Use cflags from board description file. ++ * ld-powerpc/elfv2exe.d: Update for changed plt call stubs. + -+2013-12-13 Kuan-Lin Chen ++2014-05-28 Matthew Fortune + -+ * lib/ld-lib.exp: Add NDS32 to list of targets that do not support -+ shared library generation. -+ * ld-nds32: New directory. -+ * ld-nds32/branch.d: New test. -+ * ld-nds32/branch.ld: New test. -+ * ld-nds32/branch.s: New test. -+ * ld-nds32/diff.d: New test. -+ * ld-nds32/diff.ld: New test. -+ * ld-nds32/diff.s: New test. -+ * ld-nds32/gp.d: New test. -+ * ld-nds32/gp.ld: New test. -+ * ld-nds32/gp.s: New test. -+ * ld-nds32/imm.d: New test. -+ * ld-nds32/imm.ld: New test. -+ * ld-nds32/imm.s: New test. -+ * ld-nds32/imm_symbol.s: New test. -+ * ld-nds32/relax_jmp.d: New test. -+ * ld-nds32/relax_jmp.ld: New test. -+ * ld-nds32/relax_jmp.s: New test. -+ * ld-nds32/relax_load_store.d: New test. -+ * ld-nds32/relax_load_store.ld: New test. -+ * ld-nds32/relax_load_store.s: New test. -+ * ld-nds32/nds32.exp: New file. ++ * lib/ld-lib.exp: Add objcopy_objects command to run_dump_test. ++ This allows each input object to be optionally run through ++ objcopy before linking. + -+2013-12-12 H.J. Lu ++2014-05-20 Will Newton + -+ * ld-elf/ehdr_start-userdef.d: Add "#...". ++ * ld-shared/shared.exp: Mark non-PIC shared object tests ++ as xfail on aarch64. + -+2013-12-12 H.J. Lu ++2014-05-19 Andreas Tobler + -+ * ld-pie/vaddr-0.d: New file. -+ * ld-pie/vaddr-1.d: Likewise. -+ * ld-pie/vaddr.s: Likewise. ++ * ld-elf/shared.exp: Introduce the extralibs variable to control ++ the libraries to be linked. Don't link -ldl on *-*-freebsd*. + -+2013-12-11 Will Newton ++ * ld-bootstrap/bootstrap.exp: Do not add -ldl to the extralibs on ++ *-*-freebsd*. + -+ * ld-aarch64/ifunc-21.d: Make test more generic to support -+ aarch64_be and ELF targets. -+ * ld-aarch64/ifunc-22.d: Likewise. ++2014-05-10 Hans-Peter Nilsson + -+2013-12-11 H.J. Lu ++ * ld-mmix/wrap1.d, ld-mmix/wrap1a.s, ld-mmix/wrap1b.s, ++ ld-mmix/wrap1c.s, ld-mmix/wrap2.d, ld-mmix/wrap3.d, ++ ld-mmix/wrap3a.s, ld-mmix/wrap3b.s, ld-mmix/wrap4.d: New ++ tests. + -+ * ld-elf/shared.exp (build_tests): Add libneeded2a.so, -+ libneeded2b.so, libneeded2c.o and needed2. ++2014-05-09 H.J. Lu + -+ * ld-elf/needed2.ver: New file. -+ * ld-elf/needed2a.c: Likewise. -+ * ld-elf/needed2b.c: Likewise. -+ * ld-elf/needed2c.c: Likewise. -+ -+2013-12-07 Mike Frysinger -+ -+ * ld-pe/aligncomm-1.c: Remove +x file mode. -+ * ld-pe/aligncomm-2.c: Likewise. -+ * ld-pe/aligncomm-3.c: Likewise. -+ * ld-pe/aligncomm-4.c: Likewise. -+ * ld-pe/aligncomm.d: Likewise. -+ * ld-pe/export_dynamic_warning.s: Likewise. -+ * ld-pe/exports64.d: Likewise. -+ * ld-pe/longsecn-1.d: Likewise. -+ * ld-pe/longsecn-2.d: Likewise. -+ * ld-pe/longsecn-3.d: Likewise. -+ * ld-pe/longsecn-4.d: Likewise. -+ * ld-pe/longsecn-5.d: Likewise. -+ * ld-pe/longsecn.d: Likewise. -+ * ld-pe/longsecn.s: Likewise. -+ * ld-pe/non-c-lang-syms.d: Likewise. -+ * ld-pe/non-c-lang-syms.s: Likewise. -+ * ld-pe/pe-compile.exp: Likewise. -+ * ld-pe/pe-run.exp: Likewise. -+ * ld-pe/tlssec.s: Likewise. -+ * ld-pe/tlssec32.d: Likewise. -+ * ld-pe/tlssec64.d: Likewise. -+ * ld-pe/vers-script-1.ver: Likewise. -+ * ld-pe/vers-script-2.ver: Likewise. -+ * ld-pe/vers-script-3.ver: Likewise. -+ * ld-pe/vers-script-4.ver: Likewise. -+ * ld-pe/vers-script-dll.c: Likewise. -+ -+2013-11-27 Kyrylo Tkachov -+ -+ * ld-plugin/lto.exp: Add -ffat-lto-objects. -+ * lib/ld-lib.exp (check_lto_available): Likewise. -+ -+2013-11-27 Matthew Fortune -+ -+ * ld-mips-elf/mips-elf.exp: Consider mips-mti-elf the same as -+ mips-sde-elf -+ -+2013-11-26 H.J. Lu -+ -+ PR ld/16259 -+ * config/default.exp (get_target_emul): Also set HOSTING_SLIBS. -+ * lib/ld-lib.exp (default_ld_link): Use HOSTING_SLIBS for -pie. -+ -+2013-11-26 Will Newton -+ -+ * ld-aarch64/aarch64-elf.exp: Add ifunc-22. -+ * ld-aarch64/ifunc-22.d: New file. -+ * ld-aarch64/ifunc-22.s: Likewise. -+ -+2013-11-26 Will Newton -+ -+ * ld-aarch64/aarch64-elf.exp: Add ifunc-21 test. -+ * ld-aarch64/ifunc-21.d: New file. -+ * ld-aarch64/ifunc-21.s: Likewise. -+ -+2013-11-21 H.J. Lu -+ -+ * ld-x86-64/mpx.exp: Run bnd-branch-1. -+ * ld-x86-64/bnd-branch-1.d: New file. -+ * ld-x86-64/bnd-branch-1.s: Likewise. -+ -+2013-11-20 H.J. Lu -+ -+ * ld-x86-64/mpx.exp (build_tests): Add libmpx2a.a, libmpx2b.a -+ and libmpx2c.a. -+ (run_tests): Add mpx1static, mpx2 and mpx2static. -+ * ld-x86-64/mpx2.out: Likewise. -+ * ld-x86-64/mpx2a.c: Likewise. -+ * ld-x86-64/mpx2a.rd: Likewise. -+ * ld-x86-64/mpx2b.c: Likewise. -+ * ld-x86-64/mpx2c.c: Likewise. -+ * ld-x86-64/mpx2c.rd: Likewise. -+ -+2013-11-19 Roland McGrath -+ -+ * ld-elf/ehdr_start-userdef.t: New file. -+ * ld-elf/ehdr_start-userdef.d: New file. -+ * ld-elf/ehdr_start-strongref.s: New file. -+ * ld-elf/ehdr_start-missing.t: New file. -+ * ld-elf/ehdr_start-missing.d: New file. -+ * ld-elf/ehdr_start-weak.d: New file. -+ * ld-mips-elf/ehdr_start-2.nd: Expect __ehdr_start to be global. -+ -+2013-11-17 H.J. Lu -+ -+ * ld-x86-64/mpx.exp: New file. -+ * ld-x86-64/mpx1.out: Likewise. -+ * ld-x86-64/mpx1a.c: Likewise. -+ * ld-x86-64/mpx1a.rd: Likewise. -+ * ld-x86-64/mpx1b.c: Likewise. -+ * ld-x86-64/mpx1c.c: Likewise. -+ * ld-x86-64/mpx1c.rd: Likewise. -+ -+2013-11-14 Will Newton -+ -+ * ld-arm/script-type.sym: Remove redundant STT_FILE symbol. -+ -+2013-11-07 Roland McGrath -+ -+ * ld-x86-64/x86-64.exp (mixed1, mixed2): Loosen error string match -+ so it accepts "i386:nacl" in place of "i386". -+ * ld-x86-64/ilp32-2.d: Likewise. -+ * ld-x86-64/ilp32-3.d: Likewise. -+ * ld-x86-64/lp64-2.d: Likewise. -+ * ld-x86-64/lp64-3.d: Likewise. -+ -+2013-11-05 H.J. Lu -+ -+ PR ld/4409 -+ * ld-ia64/error1.d: New file. -+ * ld-ia64/error1.s: Likewise. -+ * ld-ia64/error2.d: Likewise. -+ * ld-ia64/error3.d: Likewise. -+ -+2013-11-04 Alan Modra -+ -+ * ld-powerpc/elfv2exe.d: Adjust for non-PIC global entry. -+ -+2013-11-04 Alan Modra -+ -+ * ld-elfvers/vers24.rd: Allow extra readelf output after -+ symbol visibility. -+ * ld-ifunc/ifunc.exp: Likewise. -+ -+2013-11-04 Alan Modra -+ -+ * ld-scripts/crossref.exp: Don't allow changes made to CFLAGS -+ for this test to bleed into following tests. Don't set -+ -mcall-aixdesc for powerpc64le. -+ -+2013-11-02 Alan Modra -+ -+ * ld-pe/cfi.d: Allow wide display of addresses. -+ -+2013-11-01 Roland McGrath -+ -+ * ld-x86-64/plt-nacl.pd: Update expected disassembly for PLT nop fix. ++ * ld-x86-64/tlsbin.dd: Replace data32 with data16. + * ld-x86-64/tlsdesc-nacl.pd: Likewise. -+ -+2013-10-30 Alan Modra -+ -+ * ld-powerpc/elfv2.s, -+ * ld-powerpc/elfv2so.d, -+ * ld-powerpc/elfv2exe.d: New tests. -+ * ld-powerpc/powerpc.exp: Run them. -+ -+2013-10-30 Alan Modra -+ -+ * ld-powerpc/tls.s: Add proper .opd entry for _start. -+ * ld-powerpc/tlstoc.s: Likewise. -+ * ld-powerpc/relbrlt.d: Update for changed stubs. -+ * ld-powerpc/tls.d: Update for changed stubs and _start .opd entry. -+ * ld-powerpc/tls.g: Likewise. -+ * ld-powerpc/tlsexe.d: Likewise. -+ * ld-powerpc/tlsexe.g: Likewise. -+ * ld-powerpc/tlsexe.r: Likewise. -+ * ld-powerpc/tlsexetoc.d: Likewise. -+ * ld-powerpc/tlsexetoc.g: Likewise. -+ * ld-powerpc/tlsexetoc.r: Likewise. -+ * ld-powerpc/tlsso.d: Likewise. -+ * ld-powerpc/tlsso.g: Likewise. -+ * ld-powerpc/tlsso.r: Likewise. -+ * ld-powerpc/tlstoc.d: Likewise. -+ * ld-powerpc/tlstoc.g: Likewise. -+ * ld-powerpc/tlstocso.d: Likewise. -+ * ld-powerpc/tlstocso.g: Likewise. -+ * ld-powerpc/tlstocso.r: Likewise. -+ -+2013-10-29 Jan Beulich -+ -+ * ld-cris/tls-e-tpoffcomm1.d: Drop expectation of no longer -+ present STT_FILE symbol. -+ * ld-mmix/bpo-18.d: Likewise. -+ * ld-mmix/bpo-22.d: Likewise. -+ * ld-mmix/greg-6.d: Likewise. -+ * ld-mmix/greg-7.d: Likewise. -+ * ld-mmix/loc4.d: Likewise. -+ * ld-mmix/local1.d: Likewise. -+ * ld-mmix/local3.d: Likewise. -+ * ld-mmix/local5.d: Likewise. -+ * ld-mmix/local7.d: Likewise. -+ * ld-mmix/loct-1.d: Likewise. -+ * ld-sh/sh64/abi32.xd: Likewise. -+ * ld-sh/sh64/abi64.xd: Likewise. -+ * ld-sh/sh64/cmpct1.xd: Likewise. -+ * ld-sh/sh64/crange1.rd: Likewise. -+ * ld-sh/sh64/crange2.rd: Likewise. -+ * ld-sh/sh64/crange3-cmpct.rd: Likewise. -+ * ld-sh/sh64/crange3-media.rd: Likewise. -+ * ld-sh/sh64/crange3.rd: Likewise. -+ * ld-sh/sh64/crangerel1.rd: Likewise. -+ * ld-sh/sh64/crangerel2.rd: Likewise. -+ * ld-sh/sh64/mix1.xd: Likewise. -+ * ld-sh/sh64/mix2.xd: Likewise. -+ * ld-sh/sh64/shdl32.xd: Likewise. -+ * ld-sh/sh64/shdl64.xd: Likewise. -+ -+2013-10-18 Hans-Peter Nilsson -+ -+ * ld-cris/asneed1.d: New test. -+ -+2013-10-14 Chao-ying Fu -+ -+ * ld-mips-elf/attr-gnu-8-0.s, ld-mips-elf/attr-gnu-8-1.s, -+ ld-mips-elf/attr-gnu-8-2.s, -+ ld-mips-elf/attr-gnu-8-00.d, ld-mips-elf/attr-gnu-8-01.d, -+ ld-mips-elf/attr-gnu-8-02.d, ld-mips-elf/attr-gnu-8-10.d, -+ ld-mips-elf/attr-gnu-8-11.d, ld-mips-elf/attr-gnu-8-12.d, -+ ld-mips-elf/attr-gnu-8-20.d, ld-mips-elf/attr-gnu-8-21.d, -+ ld-mips-elf/attr-gnu-8-22.d: New. -+ * ld-mips-elf/mips-elf.exp: Run new tests. -+ -+2013-10-13 Richard Sandiford -+ -+ * lib/ld-lib.exp (default_ld_compile): Add a -I option for the source -+ directory. -+ * ld-mips-elf/compressed-plt-1.ld, ld-mips-elf/compressed-plt-1.s, -+ ld-mips-elf/compressed-plt-1-dyn.s, ld-mips-elf/compressed-plt-1a.s, -+ ld-mips-elf/compressed-plt-1b.s, ld-mips-elf/compressed-plt-1c.s, -+ ld-mips-elf/compressed-plt-1d.s, ld-mips-elf/compressed-plt-1e.s, -+ ld-mips-elf/compressed-plt-1-o32-se.rd, -+ ld-mips-elf/compressed-plt-1-o32-se.od, -+ ld-mips-elf/compressed-plt-1-o32-mips16-only.rd, -+ ld-mips-elf/compressed-plt-1-o32-mips16-only.od, -+ ld-mips-elf/compressed-plt-1-o32-umips-only.rd, -+ ld-mips-elf/compressed-plt-1-o32-umips-only.od, -+ ld-mips-elf/compressed-plt-1-o32-mips16.rd, -+ ld-mips-elf/compressed-plt-1-o32-mips16.od, -+ ld-mips-elf/compressed-plt-1-o32-mips16-got.rd, -+ ld-mips-elf/compressed-plt-1-o32-mips16-got.od, -+ ld-mips-elf/compressed-plt-1-o32-mips16-word.rd, -+ ld-mips-elf/compressed-plt-1-o32-mips16-word.od, -+ ld-mips-elf/compressed-plt-1-o32-umips.rd, -+ ld-mips-elf/compressed-plt-1-o32-umips.od, -+ ld-mips-elf/compressed-plt-1-o32-umips-got.rd, -+ ld-mips-elf/compressed-plt-1-o32-umips-got.od, -+ ld-mips-elf/compressed-plt-1-o32-umips-word.rd, -+ ld-mips-elf/compressed-plt-1-o32-umips-word.od, -+ ld-mips-elf/compressed-plt-1-n32-mips16.rd, -+ ld-mips-elf/compressed-plt-1-n32-mips16.od, -+ ld-mips-elf/compressed-plt-1-n32-umips.rd, -+ ld-mips-elf/compressed-plt-1-n32-umips.od: New tests. -+ * ld-mips-elf/mips-elf.exp: Run them. -+ -+2013-10-13 Richard Sandiford -+ -+ * ld-mips-elf/pic-and-nonpic-6-n32.ad, -+ ld-mips-elf/pic-and-nonpic-6-n32.dd, -+ ld-mips-elf/pic-and-nonpic-6-n32.gd, -+ ld-mips-elf/pic-and-nonpic-6-n32.nd, -+ ld-mips-elf/pic-and-nonpic-6-n32.rd, -+ ld-mips-elf/pic-and-nonpic-6-n64.ad, -+ ld-mips-elf/pic-and-nonpic-6-n64.dd, -+ ld-mips-elf/pic-and-nonpic-6-n64.gd, -+ ld-mips-elf/pic-and-nonpic-6-n64.nd, -+ ld-mips-elf/pic-and-nonpic-6-n64.rd, -+ ld-mips-elf/pic-and-nonpic-6-o32.ad, -+ ld-mips-elf/pic-and-nonpic-6-o32.dd, -+ ld-mips-elf/pic-and-nonpic-6-o32.gd, -+ ld-mips-elf/pic-and-nonpic-6-o32.nd, -+ ld-mips-elf/pic-and-nonpic-6-o32.rd: Fix symbol value of extf4. -+ No longer expect extf3, extf4 and extd2 to be in the global GOT. -+ -+2013-10-03 Will Newton -+ -+ * ld-ifunc/ifunc.exp: Enable ifunc tests for AArch64. -+ * ld-aarch64/aarch64-elf.exp: Run ifunc tests. -+ * ld-aarch64/ifunc-1-local.d: New file. -+ * ld-aarch64/ifunc-1-local.s: Likewise. -+ * ld-aarch64/ifunc-1.d: Likewise. -+ * ld-aarch64/ifunc-1.s: Likewise. -+ * ld-aarch64/ifunc-10.d: Likewise. -+ * ld-aarch64/ifunc-10.s: Likewise. -+ * ld-aarch64/ifunc-11.d: Likewise. -+ * ld-aarch64/ifunc-11.s: Likewise. -+ * ld-aarch64/ifunc-12.d: Likewise. -+ * ld-aarch64/ifunc-12.s: Likewise. -+ * ld-aarch64/ifunc-13.d: Likewise. -+ * ld-aarch64/ifunc-13a.s: Likewise. -+ * ld-aarch64/ifunc-13b.s: Likewise. -+ * ld-aarch64/ifunc-14a.d: Likewise. -+ * ld-aarch64/ifunc-14a.s: Likewise. -+ * ld-aarch64/ifunc-14b.d: Likewise. -+ * ld-aarch64/ifunc-14b.s: Likewise. -+ * ld-aarch64/ifunc-14c.d: Likewise. -+ * ld-aarch64/ifunc-14c.s: Likewise. -+ * ld-aarch64/ifunc-14d.d: Likewise. -+ * ld-aarch64/ifunc-14e.d: Likewise. -+ * ld-aarch64/ifunc-14f.d: Likewise. -+ * ld-aarch64/ifunc-15.d: Likewise. -+ * ld-aarch64/ifunc-15.s: Likewise. -+ * ld-aarch64/ifunc-16.d: Likewise. -+ * ld-aarch64/ifunc-16.s: Likewise. -+ * ld-aarch64/ifunc-17a.d: Likewise. -+ * ld-aarch64/ifunc-17a.s: Likewise. -+ * ld-aarch64/ifunc-17b.d: Likewise. -+ * ld-aarch64/ifunc-17b.s: Likewise. -+ * ld-aarch64/ifunc-18a.d: Likewise. -+ * ld-aarch64/ifunc-18a.s: Likewise. -+ * ld-aarch64/ifunc-18b.d: Likewise. -+ * ld-aarch64/ifunc-18b.s: Likewise. -+ * ld-aarch64/ifunc-19a.d: Likewise. -+ * ld-aarch64/ifunc-19a.s: Likewise. -+ * ld-aarch64/ifunc-19b.d: Likewise. -+ * ld-aarch64/ifunc-19b.s: Likewise. -+ * ld-aarch64/ifunc-2-local.d: Likewise. -+ * ld-aarch64/ifunc-2-local.s: Likewise. -+ * ld-aarch64/ifunc-2.d: Likewise. -+ * ld-aarch64/ifunc-2.s: Likewise. -+ * ld-aarch64/ifunc-20.d: Likewise. -+ * ld-aarch64/ifunc-20.s: Likewise. -+ * ld-aarch64/ifunc-3.s: Likewise. -+ * ld-aarch64/ifunc-3a.d: Likewise. -+ * ld-aarch64/ifunc-3b.d: Likewise. -+ * ld-aarch64/ifunc-4.d: Likewise. -+ * ld-aarch64/ifunc-4.s: Likewise. -+ * ld-aarch64/ifunc-4a.d: Likewise. -+ * ld-aarch64/ifunc-5-local.s: Likewise. -+ * ld-aarch64/ifunc-5.s: Likewise. -+ * ld-aarch64/ifunc-5a-local.d: Likewise. -+ * ld-aarch64/ifunc-5a.d: Likewise. -+ * ld-aarch64/ifunc-5b-local.d: Likewise. -+ * ld-aarch64/ifunc-5b.d: Likewise. -+ * ld-aarch64/ifunc-5r-local.d: Likewise. -+ * ld-aarch64/ifunc-6.s: Likewise. -+ * ld-aarch64/ifunc-6a.d: Likewise. -+ * ld-aarch64/ifunc-6b.d: Likewise. -+ * ld-aarch64/ifunc-7.s: Likewise. -+ * ld-aarch64/ifunc-7a.d: Likewise. -+ * ld-aarch64/ifunc-7b.d: Likewise. -+ * ld-aarch64/ifunc-7c.d: Likewise. -+ * ld-aarch64/ifunc-8.d: Likewise. -+ * ld-aarch64/ifunc-8a.s: Likewise. -+ * ld-aarch64/ifunc-8b.s: Likewise. -+ * ld-aarch64/ifunc-9.d: Likewise. -+ * ld-aarch64/ifunc-9.s: Likewise. -+ -+2013-09-24 Gregory Fong -+ -+ * ld-mips-elf/eh-frame5.d, ld-mips-elf/jalx-2.dd, -+ ld-mips-elf/mips-elf.exp, ld-mips-elf/mips16-pic-2.ad, -+ ld-mips-elf/mips16-pic-2.nd, ld-mips-elf/pic-and-nonpic-3a.dd, -+ ld-mips-elf/pic-and-nonpic-3b.ad, ld-mips-elf/pic-and-nonpic-3b.dd, -+ ld-mips-elf/pic-and-nonpic-3b.nd, ld-mips-elf/pic-and-nonpic-4b.ad, -+ ld-mips-elf/pic-and-nonpic-4b.nd, ld-mips-elf/pic-and-nonpic-4b.rd, -+ ld-mips-elf/pic-and-nonpic-5b.ad, ld-mips-elf/pic-and-nonpic-5b.nd, -+ ld-mips-elf/pic-and-nonpic-6-n32.ad, -+ ld-mips-elf/pic-and-nonpic-6-n32.dd, -+ ld-mips-elf/pic-and-nonpic-6-n32.nd, -+ ld-mips-elf/pic-and-nonpic-6-n64.ad, -+ ld-mips-elf/pic-and-nonpic-6-n64.dd, -+ ld-mips-elf/pic-and-nonpic-6-n64.nd, -+ ld-mips-elf/pic-and-nonpic-6-o32.ad, -+ ld-mips-elf/pic-and-nonpic-6-o32.dd, -+ ld-mips-elf/pic-and-nonpic-6-o32.nd, ld-mips-elf/rel32-n32.d, -+ ld-mips-elf/rel32-o32.d, ld-mips-elf/rel64.d, -+ ld-mips-elf/tls-multi-got-1.got, ld-mips-elf/tls-multi-got-1.r, -+ ld-mips-elf/tlsdyn-o32-1.d, ld-mips-elf/tlsdyn-o32-1.got, -+ ld-mips-elf/tlsdyn-o32-2.d, ld-mips-elf/tlsdyn-o32-2.got, -+ ld-mips-elf/tlsdyn-o32-3.d, ld-mips-elf/tlsdyn-o32-3.got, -+ ld-mips-elf/tlsdyn-o32.d, ld-mips-elf/tlsdyn-o32.got, -+ ld-mips-elf/tlslib-o32-ver.got, ld-mips-elf/tlslib-o32.got: Update -+ for removal of _GLOBAL_OFFSET_TABLE_ from .dynsym. -+ -+2013-09-18 Kyrylo Tkachov -+ -+ * ld-aarch64/eh-frame.d: Update expected output to allow for -+ 64-bit addresses. -+ -+2013-09-12 Nick Clifton -+ -+ * ld-elf/eh1.d: Update expected output to allow for -+ 64-bit addresses. -+ * ld-elf/eh2.d: Likewise. -+ * ld-elf/eh3.d: Likewise. -+ * ld-elf/eh4.d: Likewise. -+ * ld-elf/eh5.d: Likewise. -+ * ld-elf/eh6.d: Likewise. -+ * ld-mips-elf/eh-frame1-n64.d: Likewise. -+ * ld-mips-elf/eh-frame2-n64.d: Likewise. -+ * ld-mips-elf/eh-frame3.d: Likewise. -+ -+2013-09-04 Vidya Praveen -+ -+ * ld-arm/export-class.exp: Fix the condition. -+ -+2013-08-29 Jakub Jelinek -+ -+ * ld-x86-64/x86-64.exp: Add tlsld3, tlsgd7 and tlsgd8 tests. -+ * ld-x86-64/tlspic1.s: Add -mcmodel=large -fpic TLS GD and LD -+ sequences. -+ * ld-x86-64/tlspic.dd: Adjusted. -+ * ld-x86-64/tlspic.rd: Adjusted. -+ * ld-x86-64/tlspic-nacl.rd: Adjusted. -+ * ld-x86-64/tlsld3.dd: New test. -+ * ld-x86-64/tlsld3.s: New file. -+ * ld-x86-64/tlsgd7.dd: New test. -+ * ld-x86-64/tlsgd7.s: New file. -+ * ld-x86-64/tlsgd8.dd: New test. -+ * ld-x86-64/tlsgd8.s: New file. -+ -+2013-08-26 Roland McGrath -+ -+ * ld-x86-64/x86-64.exp (Mixed x86_64 and i386 input test 1): -+ Loosen string match to admit i386:x86-64*. -+ (Mixed x86_64 and i386 input test 2): Likewise. -+ * ld-x86-64/ilp32-2.d: Likewise. -+ * ld-x86-64/ilp32-3.d: Likewise. -+ * ld-x86-64/lp64-2.d: Likewise. -+ * ld-x86-64/lp64-3.d: Likewise. -+ * ld-x86-64/ia32-2.d: Likewise, and i386.* too. -+ * ld-x86-64/ia32-3.d: Likewise. -+ -+2013-08-26 Roland McGrath -+ -+ * ld-x86-64/ilp32-4-nacl.d: Loosen .shstrtab line regexp to match -+ any file offset. -+ * ld-x86-64/tlsbin-nacl.rd: Update expected code segment PT_LOAD. -+ * ld-x86-64/tlsbindesc-nacl.rd: Likewise. -+ * ld-scripts/rgn-at3.d: XFAIL for *-*-nacl* targets. -+ * ld-scripts/rgn-over8-ok.d: Likewise. -+ -+2013-08-24 Maciej W. Rozycki -+ -+ * ld-elf/comm-data.exp: Use check_shared_lib_support rather than -+ explicit patterns for test target qualification. Define extra -+ tool flags for *-*-hpux* and tic6x-*-* targets. Link with a -+ linker script. Use alternative patterns for targets that do not -+ eliminate copy relocs, currently mn10300-*-* and vax-*-*. -+ * ld-elf/comm-data2.s: Handle HPUX's `.comm' syntax. -+ * ld-elf/comm-data2.ld: New test linker script. -+ * ld-elf/comm-data2.xd: Match section's VMA too. Ignore ASCII -+ data dump. -+ * ld-elf/comm-data2r.rd: New test pattern. -+ * ld-elf/comm-data2r.sd: New test pattern. -+ * ld-elf/comm-data2r.xd: New test pattern. -+ * ld-mips-elf/comm-data.exp: Use check_shared_lib_support rather -+ than an explicit pattern for test target qualification. Link -+ with a linker script. -+ -+2013-08-24 Maciej W. Rozycki -+ -+ * ld-arm/export-class.exp: Handle non-EABI targets. -+ -+2013-08-23 Roland McGrath -+ -+ * ld-x86-64/ilp32-4-nacl.d: Update for 2013-05-31 gas alignment change. -+ * ld/testsuite/ld-x86-64/tlsbin-nacl.rd: Likewise. -+ * ld/testsuite/ld-x86-64/tlsbindesc-nacl.rd: Likewise. -+ * ld/testsuite/ld-x86-64/tlsdesc-nacl.rd: Likewise. -+ * ld/testsuite/ld-x86-64/tlspic-nacl.rd: Likewise. -+ -+2013-08-23 Yuri Chornoivan -+ -+ PR binutils/15834 -+ * ld-mips-elf/mips16-pic-1.inc: Fix typos. -+ -+2013-08-22 Alan Modra -+ -+ * ld-powerpc/powerpc.exp: Substitute for le in options_regsub(ld). -+ Correct ppc64elftests option replacement. -+ (supports_ppc64): Match elf64lppc too. -+ * ld-powerpc/relbrlt.d: Update for little-endian. -+ * ld-powerpc/symtocbase.d: Likewise. -+ * ld-powerpc/tls.t: Likewise. -+ * ld-powerpc/tlsexetoc.g: Likewise. -+ * ld-powerpc/tlsso.d: Likewise. -+ * ld-powerpc/tlsso.g: Likewise. -+ * ld-powerpc/tlstoc.t: Likewise. -+ * ld-powerpc/tlstocso.d: Likewise. -+ * ld-powerpc/tlstocso.g: Likewise. -+ * ld-powerpc/tlstocso.t: Likewise. -+ * ld-powerpc/tocopt.d: Likewise. -+ * ld-powerpc/tocopt2.d: Likewise. -+ * ld-powerpc/tocopt3.d: Likewise. -+ * ld-powerpc/tocopt4.d: Likewise. -+ * ld-powerpc/tocopt5.d: Likewise. -+ -+2013-08-14 Clemens Lang -+ -+ * ld-scripts/log2.exp: New: Run the new log2 test. -+ * ld-scripts/log2.s: Source for the new test. -+ * ld-scripts/log2.t: Linker script for new test. -+ -+2013-08-14 John Tytgat -+ -+ PR ld/15787 -+ * ld-arm/group-relocs-ldr-bad.s: Redefine bar into foo section -+ beyond 16 bit offset width. -+ * ld-arm/group-relocs-ldrs-bad.s: Likewise. -+ * ld-arm/group-relocs-ldr-bad.d: Adjust expected result. -+ * ld-arm/group-relocs-ldrs-bad.d: Likewise. -+ * ld-arm/group-relocs.s: Add comments. Move symbols used for sb -+ group relocations into .data section. Drop section zero. Use pc/r0 -+ as base register when pc/sb group relocations are used. -+ * ld-arm/group-relocs.d: Adjust expected result. -+ * ld-arm/group-relocs-alu-bad-2.d: New test for sb group relocation. -+ * ld-arm/group-relocs-ldc-bad-2.d: Likewise. -+ * ld-arm/group-relocs-ldr-bad-2.d: New test for pc group relocation. -+ * ld-arm/group-relocs-ldrs-bad-2.d: Likewise. -+ * ld-arm/unresolved-2.d: Add sb relocation failure test. -+ * ld-arm/group-relocs-alu-bad-2.s: New test source. -+ * ld-arm/group-relocs-ldr-bad-2.s: Likewise. -+ * ld-arm/group-relocs-ldrs-bad-2.s: Likewise. -+ * ld-arm/group-relocs-ldc-bad-2.s: Likewise. -+ * ld-arm/unresolved-2.s: Likewise. -+ * ld-arm/arm-elf.exp: For group-relocs, drop section zero start -+ definition. Run the new tests. -+ -+2013-08-09 Nick Clifton -+ -+ * lib/ld-lib.exp (check_shared_lib_support): Note that the RL78 -+ does not support shared library generation. -+ -+2013-07-31 John Tytgat -+ -+ PR ld/15787 -+ * ld-arm/group-relocs-alu-bad-2.d; New. -+ * ld-arm/group-relocs-alu-bad-2.s: New. -+ * ld-arm/group-relocs-ldc-bad-2.d: New. -+ * ld-arm/group-relocs-ldc-bad-2.s: New. -+ * ld-arm/group-relocs-ldr-bad-2.d: New. -+ * ld-arm/group-relocs-ldr-bad-2.s: New. -+ * ld-arm/group-relocs-ldrs-bad-2.d: New. -+ * ld-arm/group-relocs-ldrs-bad-2: New. -+ * ld-arm/arm-elf.exp: Add the new tests. -+ * ld-arm/group-relocs-ldr-bad.d: Update expected output. -+ * ld-arm/group-relocs-ldr-bad.s: Likewise. -+ * ld-arm/group-relocs-ldrs-bad.d: Likewise. -+ * ld-arm/group-relocs-ldrs-bad.s: Likewise. -+ * ld-arm/group-relocs.d: Likewise. -+ * ld-arm/group-relocs.s: Likewise. -+ -+2013-07-27 Maciej W. Rozycki -+ -+ * ld-vax-elf/export-class-call.dd: New test. -+ * ld-vax-elf/export-class-call.rd: New test. -+ * ld-vax-elf/export-class-call.xd: New test. -+ * ld-vax-elf/export-class-data.dd: New test. -+ * ld-vax-elf/export-class-data.rd: New test. -+ * ld-vax-elf/export-class-data.xd: New test. -+ * ld-vax-elf/export-class.ld: New test linker script. -+ * ld-vax-elf/export-class-call.s: New test source. -+ * ld-vax-elf/export-class-data.s: New test source. -+ * ld-vax-elf/export-class-def.s: New test source. -+ * ld-vax-elf/vax-elf.exp: Run the new tests. -+ * ld-vax-elf/vax-export-class.rd: New test. -+ * ld-vax-elf/vax-export-class.xd: New test. -+ * ld-vax-elf/export-class.exp: New test script. -+ -+2013-07-27 Maciej W. Rozycki -+ -+ * ld-vax-elf/got-local-exe.xd: New test. -+ * ld-vax-elf/got-local-lib.xd: New test. -+ * ld-vax-elf/got-local-aux.s: New test source. -+ * ld-vax-elf/got-local-def.s: New test source. -+ * ld-vax-elf/got-local-ref.s: New test source. -+ * ld-vax-elf/vax-elf.exp: Run the new tests. -+ -+2013-07-24 H.J. Lu -+ -+ PR ld/15762 -+ * ld-elf/shared.exp (build_tests): Check .gnu.warning section -+ in the libbarw.so library. -+ * ld-elf/libbarw.rd: New. -+ -+ * lib/ld-lib.exp (run_cc_link_tests): Support checking on -+ output with warning message. -+ -+2013-07-22 Sebastian Huber -+ -+ * ld-scripts/script.exp: Use run_dump_test instead of -+ ld_simple_link to check the error message. -+ * ld-scripts/align-with-input.d: New file. -+ * ld-scripts/region-alias-1.d: Likewise. -+ * ld-scripts/region-alias-2.d: Likewise. -+ * ld-scripts/region-alias-3.d: Likewise. -+ * ld-scripts/region-alias-4.d: Likewise. -+ -+2013-07-19 Sebastian Huber -+ -+ * ld-scripts/script.exp: Run align with input test. -+ * ld-scripts/align-with-input.t: New file. -+ * ld-scripts/rgn-at8.d: Likewise. -+ * ld-scripts/rgn-at8.t: Likewise. -+ -+2013-07-18 Terry Guo -+ -+ * ld-arm/thumb-b-lks-sym.d: Updated to be more flexible. -+ * ld-arm/thumb-bl-lks-sym.d: Likewise. -+ -+2013-07-18 Roland McGrath -+ -+ * ld-arm/farcall-arm-nacl.d: New file. -+ * ld-arm/farcall-arm-nacl-pic.d: New file. -+ * ld-arm/farcall-data-nacl.d: New file. -+ * ld-arm/arm-elf.exp (armeabitests_common): Add extra element to -+ "action" lists for those cases to use a different dump file for NaCl -+ targets. -+ Massage $armeabitests_common to drop the extra element or the one -+ before it, depending on [istarget "arm*-*-nacl*"]. -+ -+ * ld-arm/arm-elf.exp (armelftests_common): Move all "Cortex-A8 -+ erratum fix", Thumb-only and interworking cases to ... -+ (armelftests_nonacl): ... here. -+ (armeabitests_common): Move all "erratum 760522 fix", Thumb-only -+ and interworking cases to ... -+ (armeabitests_nonacl): ... here. -+ -+2013-07-12 Maciej W. Rozycki -+ -+ * ld-mips-elf/nan-2008.d: New test. -+ * ld-mips-elf/nan-legacy.d: New test. -+ * ld-mips-elf/nan-mixed-1.d: New test. -+ * ld-mips-elf/nan-mixed-2.d: New test. -+ * ld-mips-elf/nan-2008.s: New test source. -+ * ld-mips-elf/nan-legacy.s: New test source. -+ -+2013-07-03 Marcus Shawcroft -+ -+ * ld-aarch64/emit-relocs-309.s: Replace got_prel19 with got. -+ * ld-aarch64/gc-relocs-309.s: Likewise. -+ -+2013-07-02 Marcus Shawcroft -+ -+ * ld-aarch64/gc-plt-relocs.d: Adjust expected .got offsets. -+ * ld-aarch64/tls-desc-ie.d: Likewise. -+ * ld-aarch64/emit-relocs-311.d: Adjust expected symbol. -+ * ld-aarch64/tls-relax-all.d: Likewise. -+ * ld-aarch64/tls-relax-gd-ie.d: Likewise. -+ * ld-aarch64/tls-relax-gdesc-ie.d: Likewise. -+ * ld-aarch64/tls-relax-gdesc-ie-2.d: Likewise. -+ -+2013-07-01 H.J. Lu -+ -+ * ld-x86-64/tlsg.sd: Adjusted. -+ -+2013-06-28 H.J. Lu -+ -+ PR ld/15685 -+ * ld-x86-64/tlsg.s: Add a test for R_X86_64_DTPOFF64. -+ * ld-x86-64/tlsg.sd: Updated. -+ -+2013-06-24 Maciej W. Rozycki -+ -+ * ld-mips-elf/jalx-2.dd: Update for microMIPS PLT support. -+ * ld-mips-elf/pic-and-nonpic-3a.dd: Update for the _MIPS_STUBS_ -+ magic symbol. -+ * ld-mips-elf/pic-and-nonpic-3b.dd: Likewise. -+ * ld-mips-elf/pic-and-nonpic-6-n32.dd: Likewise. -+ * ld-mips-elf/pic-and-nonpic-6-n64.dd: Likewise. -+ * ld-mips-elf/pic-and-nonpic-6-o32.dd: Likewise. -+ * ld-mips-elf/stub-dynsym-1-10000.d: Likewise. -+ * ld-mips-elf/stub-dynsym-1-2fe80.d: Likewise. -+ * ld-mips-elf/stub-dynsym-1-7fff.d: Likewise. -+ * ld-mips-elf/stub-dynsym-1-8000.d: Likewise. -+ * ld-mips-elf/stub-dynsym-1-fff0.d: Likewise. -+ * ld-mips-elf/tlslib-o32.d: Likewise. -+ -+2013-06-19 Will Newton -+ -+ * ld-aarch64/aarch64-elf.exp: Remove ifunc tests. -+ * ld-ifunc/ifunc.exp: Disable ifunc tests on AArch64. -+ * ld-aarch64/ifunc-1-local.d: Remove. -+ * ld-aarch64/ifunc-1-local.s: Likewise. -+ * ld-aarch64/ifunc-1.d: Likewise. -+ * ld-aarch64/ifunc-1.s: Likewise. -+ * ld-aarch64/ifunc-10.d: Likewise. -+ * ld-aarch64/ifunc-10.s: Likewise. -+ * ld-aarch64/ifunc-11.d: Likewise. -+ * ld-aarch64/ifunc-11.s: Likewise. -+ * ld-aarch64/ifunc-12.d: Likewise. -+ * ld-aarch64/ifunc-12.s: Likewise. -+ * ld-aarch64/ifunc-13.d: Likewise. -+ * ld-aarch64/ifunc-13a.s: Likewise. -+ * ld-aarch64/ifunc-13b.s: Likewise. -+ * ld-aarch64/ifunc-14a.d: Likewise. -+ * ld-aarch64/ifunc-14a.s: Likewise. -+ * ld-aarch64/ifunc-14b.d: Likewise. -+ * ld-aarch64/ifunc-14b.s: Likewise. -+ * ld-aarch64/ifunc-14c.d: Likewise. -+ * ld-aarch64/ifunc-14c.s: Likewise. -+ * ld-aarch64/ifunc-14d.d: Likewise. -+ * ld-aarch64/ifunc-14e.d: Likewise. -+ * ld-aarch64/ifunc-14f.d: Likewise. -+ * ld-aarch64/ifunc-15.d: Likewise. -+ * ld-aarch64/ifunc-15.s: Likewise. -+ * ld-aarch64/ifunc-16.d: Likewise. -+ * ld-aarch64/ifunc-16.s: Likewise. -+ * ld-aarch64/ifunc-17a.d: Likewise. -+ * ld-aarch64/ifunc-17a.s: Likewise. -+ * ld-aarch64/ifunc-17b.d: Likewise. -+ * ld-aarch64/ifunc-17b.s: Likewise. -+ * ld-aarch64/ifunc-18a.d: Likewise. -+ * ld-aarch64/ifunc-18a.s: Likewise. -+ * ld-aarch64/ifunc-18b.d: Likewise. -+ * ld-aarch64/ifunc-18b.s: Likewise. -+ * ld-aarch64/ifunc-19a.d: Likewise. -+ * ld-aarch64/ifunc-19a.s: Likewise. -+ * ld-aarch64/ifunc-19b.d: Likewise. -+ * ld-aarch64/ifunc-19b.s: Likewise. -+ * ld-aarch64/ifunc-2-local.d: Likewise. -+ * ld-aarch64/ifunc-2-local.s: Likewise. -+ * ld-aarch64/ifunc-2.d: Likewise. -+ * ld-aarch64/ifunc-2.s: Likewise. -+ * ld-aarch64/ifunc-20.d: Likewise. -+ * ld-aarch64/ifunc-20.s: Likewise. -+ * ld-aarch64/ifunc-3.s: Likewise. -+ * ld-aarch64/ifunc-3a.d: Likewise. -+ * ld-aarch64/ifunc-3b.d: Likewise. -+ * ld-aarch64/ifunc-4.d: Likewise. -+ * ld-aarch64/ifunc-4.s: Likewise. -+ * ld-aarch64/ifunc-4a.d: Likewise. -+ * ld-aarch64/ifunc-5-local.s: Likewise. -+ * ld-aarch64/ifunc-5.s: Likewise. -+ * ld-aarch64/ifunc-5a-local.d: Likewise. -+ * ld-aarch64/ifunc-5a.d: Likewise. -+ * ld-aarch64/ifunc-5b-local.d: Likewise. -+ * ld-aarch64/ifunc-5b.d: Likewise. -+ * ld-aarch64/ifunc-5r-local.d: Likewise. -+ * ld-aarch64/ifunc-6.s: Likewise. -+ * ld-aarch64/ifunc-6a.d: Likewise. -+ * ld-aarch64/ifunc-6b.d: Likewise. -+ * ld-aarch64/ifunc-7.s: Likewise. -+ * ld-aarch64/ifunc-7a.d: Likewise. -+ * ld-aarch64/ifunc-7b.d: Likewise. -+ * ld-aarch64/ifunc-7c.d: Likewise. -+ * ld-aarch64/ifunc-8.d: Likewise. -+ * ld-aarch64/ifunc-8a.s: Likewise. -+ * ld-aarch64/ifunc-8b.s: Likewise. -+ * ld-aarch64/ifunc-9.d: Likewise. -+ * ld-aarch64/ifunc-9.s: Likewise. -+ -+2013-06-17 Will Newton -+ -+ * ld-aarch64/ifunc-1-local.d: Enable test on aarch64_be. -+ * ld-aarch64/ifunc-1.d: Likewise. -+ * ld-aarch64/ifunc-10.d: Likewise. -+ * ld-aarch64/ifunc-11.d: Likewise. -+ * ld-aarch64/ifunc-12.d: Likewise. -+ * ld-aarch64/ifunc-13.d: Likewise. -+ * ld-aarch64/ifunc-14a.d: Likewise. -+ * ld-aarch64/ifunc-14b.d: Likewise. -+ * ld-aarch64/ifunc-14c.d: Likewise. -+ * ld-aarch64/ifunc-14d.d: Likewise. -+ * ld-aarch64/ifunc-14e.d: Likewise. -+ * ld-aarch64/ifunc-14f.d: Likewise. -+ * ld-aarch64/ifunc-15.d: Likewise. -+ * ld-aarch64/ifunc-16.d: Likewise. -+ * ld-aarch64/ifunc-17a.d: Likewise. -+ * ld-aarch64/ifunc-17b.d: Likewise. -+ * ld-aarch64/ifunc-18a.d: Likewise. -+ * ld-aarch64/ifunc-18b.d: Likewise. -+ * ld-aarch64/ifunc-19a.d: Likewise. -+ * ld-aarch64/ifunc-19b.d: Likewise. -+ * ld-aarch64/ifunc-2-local.d: Likewise. -+ * ld-aarch64/ifunc-2.d: Likewise. -+ * ld-aarch64/ifunc-20.d: Likewise. -+ * ld-aarch64/ifunc-3a.d: Likewise. -+ * ld-aarch64/ifunc-3b.d: Likewise. -+ * ld-aarch64/ifunc-4.d: Likewise. -+ * ld-aarch64/ifunc-4a.d: Likewise. -+ * ld-aarch64/ifunc-5a-local.d: Likewise. -+ * ld-aarch64/ifunc-5a.d: Likewise. -+ * ld-aarch64/ifunc-5b-local.d: Likewise. -+ * ld-aarch64/ifunc-5b.d: Likewise. -+ * ld-aarch64/ifunc-5r-local.d: Likewise. -+ * ld-aarch64/ifunc-6a.d: Likewise. -+ * ld-aarch64/ifunc-6b.d: Likewise. -+ * ld-aarch64/ifunc-7a.d: Likewise. -+ * ld-aarch64/ifunc-7b.d: Likewise. -+ * ld-aarch64/ifunc-8.d: Likewise. -+ * ld-aarch64/ifunc-9.d: Likewise. -+ * ld-ifunc/ifunc.exp: Likewise. -+ -+2013-06-14 Yufeng Zhang -+ -+ * ld-aarch64/aarch64-elf.exp: Add 'ifunc-7c'. -+ * ld-aarch64/ifunc-7c.d: New test. -+ -+2013-06-14 Yufeng Zhang -+ -+ * ld-aarch64/ifunc-1-local.d: Replace hard-coded immediate offset -+ with regexp. -+ * ld-aarch64/ifunc-1.d: Likewise. -+ * ld-aarch64/ifunc-2-local.d: Likewise. -+ * ld-aarch64/ifunc-2.d: Likewise. -+ * ld-aarch64/ifunc-3a.d: Likewise. -+ * ld-aarch64/ifunc-2-local.s: Change not to declare __GI_foo and foo -+ global. -+ -+2013-06-13 Terry Guo -+ -+ PR ld/15302 -+ * ld-arm/branch-lks-sym.ld: New script. -+ * ld-arm/thumb-b-lks-sym.s: New test. -+ * ld-arm/thumb-b-lks-sym.d: Expected disassembly. -+ * ld-arm/thumb-bl-lks-sym.s: New test. -+ * ld-arm/thumb-bl-lks-sym.d: Expected disassembly. -+ * ld-arm/arm-elf.exp: Run the new tests. -+ -+2013-06-07 Will Newton -+ -+ * ld-ifunc/ifunc.exp: Enable ifunc tests for AArch64. -+ * ld-aarch64/aarch64-elf.exp: Add ifunc tests. -+ * ld-aarch64/ifunc-1-local.d: New file. -+ * ld-aarch64/ifunc-1-local.s: Likewise. -+ * ld-aarch64/ifunc-1.d: Likewise. -+ * ld-aarch64/ifunc-1.s: Likewise. -+ * ld-aarch64/ifunc-10.d: Likewise. -+ * ld-aarch64/ifunc-10.s: Likewise. -+ * ld-aarch64/ifunc-11.d: Likewise. -+ * ld-aarch64/ifunc-11.s: Likewise. -+ * ld-aarch64/ifunc-12.d: Likewise. -+ * ld-aarch64/ifunc-12.s: Likewise. -+ * ld-aarch64/ifunc-13.d: Likewise. -+ * ld-aarch64/ifunc-13a.s: Likewise. -+ * ld-aarch64/ifunc-13b.s: Likewise. -+ * ld-aarch64/ifunc-14a.d: Likewise. -+ * ld-aarch64/ifunc-14a.s: Likewise. -+ * ld-aarch64/ifunc-14b.d: Likewise. -+ * ld-aarch64/ifunc-14b.s: Likewise. -+ * ld-aarch64/ifunc-14c.d: Likewise. -+ * ld-aarch64/ifunc-14c.s: Likewise. -+ * ld-aarch64/ifunc-14d.d: Likewise. -+ * ld-aarch64/ifunc-14e.d: Likewise. -+ * ld-aarch64/ifunc-14f.d: Likewise. -+ * ld-aarch64/ifunc-15.d: Likewise. -+ * ld-aarch64/ifunc-15.s: Likewise. -+ * ld-aarch64/ifunc-16.d: Likewise. -+ * ld-aarch64/ifunc-16.s: Likewise. -+ * ld-aarch64/ifunc-17a.d: Likewise. -+ * ld-aarch64/ifunc-17a.s: Likewise. -+ * ld-aarch64/ifunc-17b.d: Likewise. -+ * ld-aarch64/ifunc-17b.s: Likewise. -+ * ld-aarch64/ifunc-18a.d: Likewise. -+ * ld-aarch64/ifunc-18a.s: Likewise. -+ * ld-aarch64/ifunc-18b.d: Likewise. -+ * ld-aarch64/ifunc-18b.s: Likewise. -+ * ld-aarch64/ifunc-19a.d: Likewise. -+ * ld-aarch64/ifunc-19a.s: Likewise. -+ * ld-aarch64/ifunc-19b.d: Likewise. -+ * ld-aarch64/ifunc-19b.s: Likewise. -+ * ld-aarch64/ifunc-2-local.d: Likewise. -+ * ld-aarch64/ifunc-2-local.s: Likewise. -+ * ld-aarch64/ifunc-2.d: Likewise. -+ * ld-aarch64/ifunc-2.s: Likewise. -+ * ld-aarch64/ifunc-20.d: Likewise. -+ * ld-aarch64/ifunc-20.s: Likewise. -+ * ld-aarch64/ifunc-3.s: Likewise. -+ * ld-aarch64/ifunc-3a.d: Likewise. -+ * ld-aarch64/ifunc-3b.d: Likewise. -+ * ld-aarch64/ifunc-4.d: Likewise. -+ * ld-aarch64/ifunc-4.s: Likewise. -+ * ld-aarch64/ifunc-4a.d: Likewise. -+ * ld-aarch64/ifunc-5-local.s: Likewise. -+ * ld-aarch64/ifunc-5.s: Likewise. -+ * ld-aarch64/ifunc-5a-local.d: Likewise. -+ * ld-aarch64/ifunc-5a.d: Likewise. -+ * ld-aarch64/ifunc-5b-local.d: Likewise. -+ * ld-aarch64/ifunc-5b.d: Likewise. -+ * ld-aarch64/ifunc-5r-local.d: Likewise. -+ * ld-aarch64/ifunc-6.s: Likewise. -+ * ld-aarch64/ifunc-6a.d: Likewise. -+ * ld-aarch64/ifunc-6b.d: Likewise. -+ * ld-aarch64/ifunc-7.s: Likewise. -+ * ld-aarch64/ifunc-7a.d: Likewise. -+ * ld-aarch64/ifunc-7b.d: Likewise. -+ * ld-aarch64/ifunc-8.d: Likewise. -+ * ld-aarch64/ifunc-8a.s: Likewise. -+ * ld-aarch64/ifunc-8b.s: Likewise. -+ * ld-aarch64/ifunc-9.d: Likewise. -+ * ld-aarch64/ifunc-9.s: Likewise. -+ -+2013-06-04 Roland McGrath -+ -+ * ld-size/size.exp: For *-*-nacl* targets, use options_regsub(ld) -+ to massage -m arguments into _nacl variants. -+ * ld/testsuite/ld-size/size32-1-i386.d: Loosen regexps so they -+ don't care what the exact addresses are. -+ * ld/testsuite/ld-size/size32-1-x32.d: Likewise. -+ * ld/testsuite/ld-size/size32-1-x86-64.d: Likewise. -+ * ld/testsuite/ld-size/size32-2-i386.d: Likewise. -+ * ld/testsuite/ld-size/size32-2-x32.d: Likewise. -+ * ld/testsuite/ld-size/size32-2-x86-64.d: Likewise. -+ * ld/testsuite/ld-size/size64-1-x32.d: Likewise. -+ * ld/testsuite/ld-size/size64-1-x86-64.d: Likewise. -+ * ld/testsuite/ld-size/size64-2-x32.d: Likewise. -+ * ld/testsuite/ld-size/size64-2-x86-64.d: Likewise. -+ -+2013-06-04 H.J. Lu -+ -+ * ld-i386/tlsbindesc-nacl.rd: Updated for text/data/bss section -+ alignment change. -+ * ld-x86-64/split-by-file-nacl.rd: Likewise. -+ -+2013-05-31 H.J. Lu -+ -+ * ld-i386/pr12718.d: Updated for text/data/bss section alignment -+ change. -+ * ld-i386/tlsbindesc.dd: Likewise. -+ * ld-i386/tlsbindesc.rd: Likewise. -+ * ld-i386/tlsnopic.dd: Likewise. -+ * ld-i386/tlspic.dd: Likewise. -+ * ld-x86-64/ilp32-4.d: Likewise. -+ * ld-x86-64/pr12718.d: Likewise. -+ * ld-x86-64/split-by-file.rd: Likewise. -+ * ld-x86-64/tlsbin.dd: Likewise. -+ * ld-x86-64/tlsbin.rd: Likewise. -+ * ld-x86-64/tlsbindesc.dd: Likewise. -+ * ld-x86-64/tlsbindesc.rd: Likewise. -+ * ld-x86-64/tlsdesc.dd: Likewise. -+ * ld-x86-64/tlsdesc.rd: Likewise. ++ * ld-x86-64/tlsgdesc.dd: Likewise. ++ * ld-x86-64/tlsld1.dd: Likewise. ++ * ld-x86-64/tlsld3.dd: Likewise. + * ld-x86-64/tlspic.dd: Likewise. -+ * ld-x86-64/tlspic.rd: Likewise. + -+2013-05-29 Maciej W. Rozycki ++2014-05-02 Max Filippov + -+ * ld-mips-elf/jalr3.dd: New test. -+ * ld-mips-elf/jalr3.ld: New test linker script. -+ * ld-mips-elf/mips-elf.exp: Run the new test. ++ * ld-xtensa/diff_overflow.exp, * ld-xtensa/diff_overflow1.s, ++ * ld-xtensa/diff_overflow2.s: Add test for DIFF* relocation ++ signedness and overflow checking. + -+2013-05-21 Alan Modra ++2014-05-01 Hans-Peter Nilsson + -+ PR ld/12982 -+ * ld-plugin/pr12982.d: Fail if RWE GNU_STACK present. ++ * ld-mmix/sec-11.d, ld-mmix/sec-11.ld, ld-mmix/sec-10.s, ++ ld-mmix/sec-10.d, ld-mmix/b-offlocmis.s, ld-mmix/sec-12.d: New ++ tests. ++ * ld-mmix/b-offloc.s: Correct address in comment. + -+2013-05-21 Alan Modra ++2014-04-23 Will Newton + -+ * ld-powerpc/export-class.exp (supports_ppc64): Delete. -+ (powerpc_export_class_test): Add "endian" param. -+ (abis): Add little-endian targets and test. -+ * ld-powerpc/powerpc-64-export-class.xd: Update for little-endian. -+ -+2013-05-10 Joel Brobecker -+ -+ * ld-powerpc/aix-core-sec-1.hd, ld-powerpc/aix-core-sec-2.hd, -+ ld-powerpc/aix-core-sec-3.hd: Adjust expected section flags -+ for section .loader. -+ -+2013-05-03 Maciej W. Rozycki -+ -+ PR ld/15365 -+ * ld-elf/ehdr_start.d: Expect __ehdr_start to be STB_LOCAL. -+ * ld-mips-elf/ehdr_start-1.nd: New test. -+ * ld-mips-elf/ehdr_start-2.nd: New test. -+ * ld-mips-elf/ehdr_start-1.ld: New test linker script. -+ * ld-mips-elf/ehdr_start-2.ld: New test linker script. -+ * ld-mips-elf/ehdr_start-new.s: New test source. -+ * ld-mips-elf/ehdr_start-o32.s: New test source. -+ * ld-mips-elf/mips-elf.exp: Run the new tests. -+ -+2013-05-03 Maciej W. Rozycki -+ -+ * ld-elf/provide-hidden-s.nd: New test. -+ * ld-elf/provide-hidden-abs.nd: New test. -+ * ld-elf/provide-hidden-def.nd: New test. -+ * ld-elf/provide-hidden-dyn.nd: New test. -+ * ld-elf/provide-hidden-sec.nd: New test. -+ * ld-elf/provide-hidden-dynabs.nd: New test. -+ * ld-elf/provide-hidden-dynsec.nd: New test. -+ * ld-elf/provide-hidden-s.ld: New test linker script. -+ * ld-elf/provide-hidden-1.ld: New test linker script. -+ * ld-elf/provide-hidden-2.ld: New test linker script. -+ * ld-elf/provide-hidden-1.s: New test source. -+ * ld-elf/provide-hidden-2.s: New test source. -+ * ld-elf/provide-hidden-3.s: New test source. -+ * ld-elf/provide-hidden-4.s: New test source. -+ * ld-elf/provide-hidden.exp: New test script. -+ -+2013-05-02 Nick Clifton -+ -+ * ld-elf/flags1.d: Expect this test to pass on the MSP430. -+ * ld-elf/init-fini-arrays.d: Expect this test to fail on the -+ MSP430. -+ * ld-elf/merge.d: Expect this test to pass on the MSP430. -+ * ld-elf/sec64k.exp: Skip these tests for the MSP430. -+ * ld-gc/pr13683.d: Expect this test to fail on the MSP430. -+ * ld-srec/srec.exp: Expect these tests to fail on the MSP430. -+ * ld-undefined/undefined.exp: Expect the UNDEFINED LINE test to -+ fail on the MSP430. -+ -+2013-05-01 Maciej W. Rozycki -+ -+ * lib/ld-lib.exp (check_shared_lib_support): Also exclude -+ mips*-*-elf. -+ -+2013-04-30 Hans-Peter Nilsson -+ -+ * lib/ld-lib.exp (check_shared_lib_support): Match cris*-*-elf as -+ a negative pattern instead of cris*-*-*. -+ -+2013-04-30 Will Newton -+ -+ * ld-arm/arm-elf.exp: Use linker script for IFUNC test 17. -+ * ld-arm/ifunc-17.dd: Update offsets for linker script. ++ * ld-arm/arm-no-rel-plt.ld: Remove OUTPUT_FORMAT and ++ SEARCH_DIR commands. ++ * ld-arm/arm-rel32.d: Update regexps to allow test to ++ pass on armeb-linux-eabi configuration. ++ * ld-arm/data-only-map.d: Likewise. ++ * ld-arm/fix-arm1176-off.d: Likewise. ++ * ld-arm/fix-arm1176-on.d: Likewise. ++ * ld-arm/ifunc-1.gd: Likewise. ++ * ld-arm/ifunc-10.gd: Likewise. ++ * ld-arm/ifunc-11.gd: Likewise. ++ * ld-arm/ifunc-12.gd: Likewise. ++ * ld-arm/ifunc-13.gd: Likewise. ++ * ld-arm/ifunc-14.gd: Likewise. ++ * ld-arm/ifunc-15.gd: Likewise. ++ * ld-arm/ifunc-16.gd: Likewise. + * ld-arm/ifunc-17.gd: Likewise. -+ * ld-arm/ifunc-17.rd: Likewise. ++ * ld-arm/ifunc-2.gd: Likewise. ++ * ld-arm/ifunc-3.gd: Likewise. ++ * ld-arm/ifunc-4.gd: Likewise. ++ * ld-arm/ifunc-5.gd: Likewise. ++ * ld-arm/ifunc-6.gd: Likewise. ++ * ld-arm/ifunc-7.gd: Likewise. ++ * ld-arm/ifunc-8.gd: Likewise. ++ * ld-arm/ifunc-9.gd: Likewise. ++ * ld-arm/jump-reloc-veneers-long.d: Likewise. ++ * ld-arm/reloc-boundaries.d: Likewise. + -+2013-04-29 Will Newton ++2014-04-22 H.J. Lu + -+ * ld-arm/arm-elf.exp: Add IFUNC test 17. -+ * ld-arm/ifunc-17.dd: New file. -+ * ld-arm/ifunc-17.gd: Likewise. -+ * ld-arm/ifunc-17.rd: Likewise. -+ * ld-arm/ifunc-17.s: Likweise. -+ * ld-arm/ifunc-1.rd: Reorder relocs to match linker output. -+ * ld-arm/ifunc-2.rd: Likewise. -+ * ld-arm/ifunc-5.rd: Likewise. -+ * ld-arm/ifunc-6.rd: Likewise. ++ PR ld/16846 ++ * ld-plugin/lto.exp (lto_link_tests): Add tests for PR ld/16846. ++ * ld-plugin/pr16846a.c: New file. ++ * ld-plugin/pr16846b.c: Likewise. ++ * ld-plugin/pr16846c.c: Likewise. + -+2013-04-29 Will Newton ++2014-04-22 Christian Svensson + -+ * ld-plugin/lto.exp: Disable ld/12942 test for gcc < 4.7.0. -+ -+2013-04-22 Alan Modra -+ -+ * ld-powerpc/tlsexe.d: Adjust for section id changes. -+ * ld-powerpc/tlsexe.r: Likewise. -+ * ld-powerpc/tlsexetoc.d: Likewise. -+ * ld-powerpc/tlsexetoc.r: Likewise. -+ * ld-powerpc/tlsso.d: Likewise. -+ * ld-powerpc/tlsso.r: Likewise. -+ * ld-powerpc/tlstocso.d: Likewise. -+ * ld-powerpc/tlstocso.r: Likewise. -+ -+2013-04-15 H.J. Lu -+ -+ PR ld/15371 -+ * ld-ifunc/ifunc-20-i386.d: New file. -+ * ld-ifunc/ifunc-20-x86-64.d: Likewise. -+ * ld-ifunc/ifunc-20.s: Likewise. -+ -+2013-04-10 Venkataramanan Kumar -+ -+ * ld-aarch64/gc-plt1.s: New file. -+ * ld-aarch64/gc-plt2.s: Likewise. -+ * ld-aarch64/gc-plt-hidden.s: Likewise. -+ * ld-aarch64/gc-plt-main.s: Likewise. -+ * ld-aarch64/gc-relocs-257.s: Likewise. -+ * ld-aarch64/gc-plt-relocs.d: Update expected objdump. -+ * ld-aarch64/gc-relocs-257.d: Likewise. -+ * ld-aarch64/gc-relocs-257-dyn.d: Likewise. -+ * ld-aarch64/aarch64-elf.exp: Add test. -+ -+2013-04-08 Ramana Radhakrishnan -+ -+ * ld-aarch64/gc-tls-relocs.d: Handle big endian format. -+ * ld-aarch64/gc-got-relocs.d: Likewise. -+ -+2013-04-04 Alan Modra -+ -+ * ld-elf/shared.exp: Update regexp on --no-add-needed and -+ --no-copy-dt-needed-entries tests. -+ -+2013-04-03 Alan Modra -+ -+ PR ld/15227 -+ * ld-plugin/lto.exp (PR ld/12942 (3)): Remove file name and -+ line number from regexp. -+ (PR ld/15146 (2)): Similarly. -+ * ld-plugin/pr12942a.cc (main): Use __builtin_abort. -+ -+2013-03-30 Alan Modra -+ -+ PR ld/15323 -+ * ld-plugin/lto.exp (pr15323a.c): Compile without -flto rather -+ than using -r to effectively strip out lto info. -+ -+2013-03-29 H.J. Lu -+ -+ PR ld/15323 -+ * ld-plugin/lto.exp (lto_link_tests): Add pr15323a-r.o. -+ (lto_run_tests): Add a test for PR ld/15323. -+ -+ * ld-plugin/pr15323.out: New file. -+ * ld-plugin/pr15323a.c: Likewise. -+ * ld-plugin/pr15323b.c: Likewise. -+ -+2013-03-22 Nick Clifton -+ -+ * ld-elf/init0.s: Add alloc attribute to .section directive. -+ * ld-elf/fini1.s: Likewise. -+ * ld-elf/fini2.s: Likewise. -+ * ld-elf/fini3.s: Likewise. -+ * ld-elf/finin.s: Likewise. -+ * ld-elf/init0.s: Likewise. -+ * ld-elf/init1.s: Likewise. -+ * ld-elf/init2.s: Likewise. -+ * ld-elf/init3.s: Likewise. -+ * ld-elf/initn.s: Likewise. -+ -+2013-02-02 Michael Schewe -+ -+ * ld-h8300/h8300.exp: Add new relax-7 test on ELF. -+ * ld-h8300/relax-2.s: Add other direction and .w/.l variants of -+ mov insns. -+ * ld-h8300/relax-2.d: Update expected disassembly. -+ * ld-h8300/relax-7a.s: New: tests for mov @(disp:32,ERx) -> mov -+ @(disp:16,ERx). -+ * ld-h8300/relax-7b.s: New: Likewise. -+ * ld-h8300/relax-7.d: New: expected disassembly. -+ -+2013-03-20 Venkataramanan Kumar -+ -+ * ld-elf/group8a.d (notarget): Remove aarch64*-*-*. ++ * ld-discard/extern.d: Remove openrisc and or32 support. Add ++ support for or1k. ++ * ld-discard/start.d: Likewise. ++ * ld-discard/static.d: Likewise. ++ * ld-elf/group1.d: Likewise. ++ * ld-elf/group3b.d: Likewise. ++ * ld-elf/group8a.d: Likewise. + * ld-elf/group8b.d: Likewise. + * ld-elf/group9a.d: Likewise. + * ld-elf/group9b.d: Likewise. ++ * ld-elf/linkonce2.d: Likewise. ++ * ld-elf/merge.d: Likewise. ++ * ld-elf/merge2.d: Likewise. ++ * ld-elf/orphan-region.d: Likewise. ++ * ld-elf/orphan.d: Likewise. ++ * ld-elf/orphan3.d: Likewise. + * ld-elf/pr12851.d: Likewise. + * ld-elf/pr12975.d: Likewise. + * ld-elf/pr13177.d: Likewise. + * ld-elf/pr13195.d: Likewise. ++ * ld-elf/pr349.d: Likewise. ++ * ld-elf/sec64k.exp: Likewise. ++ * ld-elf/warn1.d: Likewise. ++ * ld-elf/warn2.d: Likewise. ++ * ld-elf/warn3.d: Likewise. ++ * ld-scripts/weak.exp: Likewise. ++ * lib/ld-lib.exp: Likewise. + -+2013-03-20 Will Newton -+ -+ * ld-elfvers/vers.exp (objdump_symstuff): Sort objdump output -+ based on the symbol name rather than address. -+ * ld-elfvers/vers1.sym: Reorder contents to match changes to vers.exp. -+ * ld-elfvers/vers15.sym: Likewise. -+ * ld-elfvers/vers18.sym: Likewise. -+ * ld-elfvers/vers21.sym: Likewise. -+ * ld-elfvers/vers9.sym: Likewise. -+ -+2013-03-20 Alan Modra -+ -+ * ld-elf/rel.c, ld-elf/relmain.c, ld-elf/relmain.out: New test. -+ * ld-elf/shared.exp: Build and run it. -+ -+2013-03-20 Alan Modra -+ Will Newton -+ -+ * ld-elf/pr14862.out: Expect no output. -+ -+2013-03-15 Will Newton -+ -+ * ld-arm/arm-elf.exp: Expand *-*eabi test to cover *-*eabi*. -+ * ld-arm/gc-hidden-1.d: Likewise. -+ * ld-elfvsb/elfvsb.exp: Likewise. -+ * ld-shared/shared.exp: Likewise. -+ -+2013-03-08 Venkataramanan Kumar -+ -+ * lib/ld-lib.exp (check_gc_sections_available): Remove aarch64 -+ from list of targets that don't support gc-section. -+ -+2013-03-05 Alan Modra -+ -+ * ld-scripts/rgn-at6.s, * ld-scripts/rgn-at6.t, * ld-scripts/rgn-at6.d, -+ * ld-scripts/rgn-at7.t, * ld-scripts/rgn-at7.d: New tests. -+ -+2013-02-28 Nathan Sidwell -+ -+ * ld-arm/tls-local-static.s: New test. -+ * ld-arm/tls-local-static.d: New. -+ * ld-arm/arm-elf.exp (tls-local-static): Add test. -+ -+2013-02-21 H.J. Lu -+ -+ PR ld/15167 -+ * ld-unique/unique.exp: Add a test for shared library with -+ reference. -+ -+2013-02-19 Maciej W. Rozycki -+ -+ * lib/ld-lib.exp (run_ld_link_tests): Add another argument, pass -+ its contents to ar_simple_create and ld_simple_link after -+ objfiles. -+ * ld-aarch64/aarch64-elf.exp: Adjust accordingly. -+ * ld-alpha/alpha.exp: Likewise. -+ * ld-arm/arm-elf.exp: Likewise. -+ * ld-arm/export-class.exp: Likewise. -+ * ld-elf/comm-data.exp: Likewise. -+ * ld-elf/eh-group.exp: Likewise. -+ * ld-elf/elf.exp: Likewise. -+ * ld-elf/export-class.exp: Likewise. -+ * ld-elfvers/vers.exp: Likewise. -+ * ld-frv/tls.exp: Likewise. -+ * ld-i386/export-class.exp: Likewise. -+ * ld-i386/i386.exp: Likewise. -+ * ld-ia64/ia64.exp: Likewise. -+ * ld-libs/libs.exp: Likewise. -+ * ld-m68k/m68k.exp: Likewise. -+ * ld-metag/metag.exp: Likewise. -+ * ld-mips-elf/comm-data.exp: Likewise. -+ * ld-mips-elf/export-class.exp: Likewise. -+ * ld-mips-elf/mips-elf.exp: Likewise. -+ * ld-mn10300/mn10300.exp: Likewise. -+ * ld-pe/pe-compile.exp: Likewise. -+ * ld-pe/pe.exp: Likewise. -+ * ld-plugin/plugin.exp: Likewise. -+ * ld-powerpc/aix52.exp: Likewise. -+ * ld-powerpc/export-class.exp: Likewise. -+ * ld-powerpc/powerpc.exp: Likewise. -+ * ld-s390/s390.exp: Likewise. -+ * ld-sh/sh-vxworks.exp: Likewise. -+ * ld-sh/sh64/sh64.exp: Likewise. -+ * ld-sparc/sparc.exp: Likewise. -+ * ld-tic6x/tic6x.exp: Likewise. -+ * ld-tilegx/tilegx.exp: Likewise. -+ * ld-tilepro/tilepro.exp: Likewise. -+ * ld-undefined/entry.exp: Likewise. -+ * ld-vax-elf/vax-elf.exp: Likewise. -+ * ld-x86-64/dwarfreloc.exp: Likewise. -+ * ld-x86-64/export-class.exp: Likewise. -+ * ld-x86-64/x86-64.exp: Likewise. -+ * ld-xc16x/xc16x.exp: Likewise. -+ * ld-xstormy16/xstormy16.exp: Likewise. -+ * ld-xtensa/xtensa.exp: Likewise. -+ -+2013-02-18 Maciej W. Rozycki -+ -+ * ld-mips-elf/jalx-2.ld: Include .rel.plt in output, give .plt a -+ mapping. -+ * ld-mips-elf/jalx-2.dd: Adjust disassembly accordingly. -+ -+2013-02-18 Alan Modra -+ -+ * ld-plugin/lto.exp (Build pr15146b.so) Add -Wl,--no-as-needed. -+ (PR ld/15146 (1), (2)): Likewise. -+ (LTO 7): Likewise. -+ -+2013-02-16 H.J. Lu -+ -+ PR ld/15146 -+ * ld-plugin/pr15146.d: New file. -+ * ld-plugin/pr15146a.c: Likewise. -+ * ld-plugin/pr15146b.c: Likewise. -+ * ld-plugin/pr15146c.c: Likewise. -+ * ld-plugin/pr15146d.c: Likewise. -+ -+ * ld-plugin/lto.exp: Add tests for PR ld/15146. -+ -+2013-02-15 Markos Chandras -+ -+ * ld-metag/pcrel.d: Fix the expected disassembler -+ output to be in little endian format -+ * ld-metag/shared.d: likewise -+ * ld-metag/stub.d: likewise -+ * ld-metag/stub_pic_app.d: likewise -+ * ld-metag/stub_pic_shared.d: likewise -+ * ld-metag/stub_shared.d: likewise -+ -+2013-02-13 Richard Sandiford -+ -+ * ld-mips-elf/mips16-pic-2.dd, -+ ld-mips-elf/mips16-pic-2.gd: Remove 3 unused local GOT entries. -+ * ld-mips-elf/got-page-4a.s, ld-mips-elf/got-page-4b.s, -+ ld-mips-elf/got-page-4a.d, ld-mips-elf/got-page-4a.got, -+ ld-mips-elf/got-page-4b.d, ld-mips-elf/got-page-4b.got, -+ ld-mips-elf/got-page-5.s, ld-mips-elf/got-page-5.d, -+ ld-mips-elf/got-page-5.got, ld-mips-elf/got-page-6.s, -+ ld-mips-elf/got-page-6.d, ld-mips-elf/got-page-6.got, -+ ld-mips-elf/got-page-7a.s, ld-mips-elf/got-page-7b.s, -+ ld-mips-elf/got-page-7c.s, ld-mips-elf/got-page-7d.s, -+ ld-mips-elf/got-page-7e.s, ld-mips-elf/got-page-7.d, -+ ld-mips-elf/got-page-7.got: New tests. -+ * ld-mips-elf/mips-elf.exp: Run them. -+ -+2013-02-11 Richard Sandiford -+ -+ * ld-mips-elf/tlsdyn-o32-1.d, ld-mips-elf/tlsdyn-o32-1.got, -+ ld-mips-elf/tlsdyn-o32-2.d, ld-mips-elf/tlsdyn-o32-2.got, -+ ld-mips-elf/tlsdyn-o32-3.d, ld-mips-elf/tlsdyn-o32-3.got, -+ ld-mips-elf/tls-hidden3.d, ld-mips-elf/tls-hidden3.got: Update -+ for new hash table order. -+ -+2013-02-11 Richard Sandiford -+ -+ * ld-mips-elf/tls-hidden4.got, ld-mips-elf/tls-multi-got-1.d, -+ ld-mips-elf/tls-multi-got-1.got: Update for changes in the order -+ that symbols are added to per-bfd GOTs. -+ -+2013-02-11 Richard Sandiford -+ -+ * ld-mips-elf/tls-hidden3.d, ld-mips-elf/tls-hidden3.got, -+ ld-mips-elf/tls-multi-got-1.got, ld-mips-elf/tlsbin-o32.d, -+ ld-mips-elf/tlsbin-o32.got, ld-mips-elf/tlsdyn-o32-1.d, -+ ld-mips-elf/tlsdyn-o32-1.got, ld-mips-elf/tlsdyn-o32-2.d, -+ ld-mips-elf/tlsdyn-o32-2.got, ld-mips-elf/tlsdyn-o32-3.d, -+ ld-mips-elf/tlsdyn-o32-3.got, ld-mips-elf/tlsdyn-o32.d, -+ ld-mips-elf/tlsdyn-o32.got, ld-mips-elf/tlslib-o32.d, -+ ld-mips-elf/tlslib-o32.got, ld-mips-elf/tlslib-o32-hidden.got, -+ ld-mips-elf/tlslib-o32-ver.got: Adjust GOT layout for new -+ got_entry hash function. -+ -+2013-02-11 Richard Sandiford -+ -+ * ld-mips-elf/tlsdyn-o32-2.got, ld-mips-elf/tlsdyn-o32-3.got: Remove -+ unused GOT entries. -+ -+2013-02-07 H.J. Lu -+ -+ PR ld/15107 -+ * ld-unique/unique_empty.s: Add reference to "b". -+ -+2013-02-06 H.J. Lu -+ -+ * ld-size/size-10.rd: Updated. -+ * ld-size/size-8.rd: Likewise. -+ * ld-size/size32-2-i386.d: Likewise. -+ * ld-size/size32-2-x32.d: Likewise. -+ * ld-size/size32-2-x86-64.d: Likewise. -+ * ld-size/size64-2-x32.d: Likewise. -+ * ld-size/size64-2-x86-64.d: Likewise. -+ -+ * ld-size/size.exp (run_time_tests): Pass --hash-styl=gnu to -+ linker for size-8 test. -+ -+2013-02-06 Sandra Loosemore -+ Andrew Jenner -+ -+ Based on patches from Altera Corporation. -+ -+ * ld-nios2/emit-relocs-1a.s: New. -+ * ld-nios2/emit-relocs-1b.s: New. -+ * ld-nios2/emit-relocs-1.d: New. -+ * ld-nios2/emit-relocs-1.ld: New. -+ * ld-nios2/gprel.d: New. -+ * ld-nios2/gprel.s: New. -+ * ld-nios2/hilo16.d: New. -+ * ld-nios2/hilo16.s: New. -+ * ld-nios2/hilo16_symbol.s: New. -+ * ld-nios2/imm5.d: New. -+ * ld-nios2/imm5.s: New. -+ * ld-nios2/imm5_symbol.s: New. -+ * ld-nios2/nios2.exp: New. -+ * ld-nios2/pcrel16.d: New. -+ * ld-nios2/pcrel16_label.s: New. -+ * ld-nios2/pcrel16.s: New. -+ * ld-nios2/relax_callr.d: New. -+ * ld-nios2/relax_callr.ld: New. -+ * ld-nios2/relax_callr.s: New. -+ * ld-nios2/relax_cjmp.d: New. -+ * ld-nios2/relax_cjmp.s: New. -+ * ld-nios2/relax_jmp.ld: New. -+ * ld-nios2/relax_section.d: New. -+ * ld-nios2/relax_section.s: New. -+ * ld-nios2/relax_ujmp.d: New. -+ * ld-nios2/relax_ujmp.s: New. -+ * ld-nios2/reloc.d: New. -+ * ld-nios2/reloc.s: New. -+ * ld-nios2/reloc_symbol.s: New. -+ * ld-nios2/s16.d: New. -+ * ld-nios2/s16.s: New. -+ * ld-nios2/s16_symbol.s: New. -+ * ld-nios2/u16.d: New. -+ * ld-nios2/u16.s: New. -+ * ld-nios2/u16_symbol.s: New. -+ * ld-elf/indirect.exp: Skip on targets that don't support -+ -shared -fPIC. -+ * ld-elfcomm/elfcomm.exp: Build with -G0 for nios2. -+ * ld-plugin/lto.exp: Skip shared library tests on targets that -+ don't support them. Skip execution tests on non-native targets. -+ -+2013-02-06 H.J. Lu -+ -+ * ld-elf/now-1.d: New file. -+ * ld-elf/now-2.d: Likewise. -+ * ld-elf/now-3.d: Likewise. -+ * ld-elf/now-4.d: Likewise. -+ * ld-elf/rpath-1.d: Likewise. -+ * ld-elf/rpath-2.d: Likewise. -+ * ld-elf/runpath-1.d: Likewise. -+ * ld-elf/runpath-2.d: Likewise. -+ -+2013-02-06 Alan Modra -+ -+ PR ld/15096 -+ * ld-elf/new-dtags-1.d: Delete. -+ * ld-elf/new-dtags-2.d: Likewise. -+ * ld-elf/new-dtags-3.d: Likewise. -+ * ld-elf/new-dtags-4.d: Likewise. -+ * ld-elf/new-dtags-5.d: Likewise. -+ * ld-elf/new-dtags-6.d: Likewise. -+ * ld-elf/new-dtags-7.d: Likewise. -+ * ld-elf/new-dtags-8.d: Likewise. -+ -+2013-02-04 H.J. Lu -+ -+ PR ld/15096 -+ * ld-elf/new-dtags-1.d: New test. -+ * ld-elf/new-dtags-2.d: Likewise. -+ * ld-elf/new-dtags-3.d: Likewise. -+ * ld-elf/new-dtags-4.d: Likewise. -+ * ld-elf/new-dtags-5.d: Likewise. -+ * ld-elf/new-dtags-6.d: Likewise. -+ * ld-elf/new-dtags-7.d: Likewise. -+ * ld-elf/new-dtags-8.d: Likewise. -+ -+2013-01-31 Alan Modra -+ -+ * ld-powerpc/tlsexe.d: Update for changed stub names. -+ * ld-powerpc/tlsexe.r: Likewise. -+ * ld-powerpc/tlsexetoc.d: Likewise. -+ * ld-powerpc/tlsexetoc.r: Likewise. -+ * ld-powerpc/tlsso.d: Likewise. -+ * ld-powerpc/tlsso.r: Likewise. -+ * ld-powerpc/tlstocso.d: Likewise. -+ * ld-powerpc/tlstocso.r: Likewise. -+ -+2013-01-31 Hans-Peter Nilsson -+ -+ * ld-cris/libdso-13.d: Adjust for --enable-new-dtags now -+ default for *-*-linux-* by passing explicitly for all targets. -+ -+2013-01-21 Alan Modra -+ -+ * ld-size/size.exp (build_tests ): Pass -+ --no-as-needed in cflags. -+ -+2013-01-19 H.J. Lu -+ -+ * config/default.exp (get_target_emul): Also set HOSTING_SCRT0. -+ -+ * lib/ld-lib.exp (default_ld_link): Use HOSTING_SCRT0 for -pie. -+ -+2013-01-18 H.J. Lu -+ -+ * ld-size/size-10.rd: Updated. -+ * ld-size/size-8.rd: Likewise. -+ * ld-size/size32-2-i386.d: Likewise. -+ * ld-size/size32-2-x32.d: Likewise. -+ * ld-size/size32-2-x86-64.d: Likewise. -+ * ld-size/size64-2-x32.d: Likewise. -+ * ld-size/size64-2-x86-64.d: Likewise. -+ -+2013-01-17 H.J. Lu -+ -+ * ld-size/size-7.out: New file. -+ * ld-size/size-8.out: Likewise. -+ * ld-size/size-9.out: Likewise. -+ * ld-size/size-9.rd: Likewise. -+ * ld-size/size-9a.c: Likewise. -+ * ld-size/size-9b.c: Likewise. -+ * ld-size/size-10.out: Likewise. -+ * ld-size/size-10.rd: Likewise. -+ * ld-size/size-10a.c: Likewise. -+ * ld-size/size-10b.c: Likewise. -+ -+ * ld-size/size.exp (build_tests): Build libsize-9.so and -+ libsize-10.so. -+ Run-time size relocation tests if supported. -+ (run_time_tests): New. -+ -+2013-01-17 H.J. Lu -+ -+ * ld-size/size-1.c: New file. -+ * ld-size/size-1.out: Likewise. -+ * ld-size/size-1a.c: Likewise. -+ * ld-size/size-1b.c: Likewise. -+ * ld-size/size-2.c: Likewise. -+ * ld-size/size-2.out: Likewise. -+ * ld-size/size-2a.c: Likewise. -+ * ld-size/size-2b.c: Likewise. -+ -+ * ld-size/size.exp (build_tests): Build libsize-1.so and -+ libsize-2.so. -+ (run_tests): Run size-1 and size-2. -+ -+2013-01-17 H.J. Lu -+ -+ * ld-size/size32-3-i386.d: New file. -+ * ld-size/size32-3-x32.d: Likewise. -+ * ld-size/size32-3-x86-64.d: Likewise. -+ * ld-size/size32-3a.s: Likewise. -+ * ld-size/size32-3b.s: Likewise. -+ -+2013-01-16 H.J. Lu -+ -+ * ld-size/size.exp: New file. -+ * ld-size/size32-1-i386.d: Likewise. -+ * ld-size/size32-1-x32.d: Likewise. -+ * ld-size/size32-1-x86-64.d: Likewise. -+ * ld-size/size32-1.s: Likewise. -+ * ld-size/size32-2-i386.d: Likewise. -+ * ld-size/size32-2-x32.d: Likewise. -+ * ld-size/size32-2-x86-64.d: Likewise. -+ * ld-size/size32-2.s: Likewise. -+ * ld-size/size64-1-x32.d: Likewise. -+ * ld-size/size64-1-x86-64.d: Likewise. -+ * ld-size/size64-1.s: Likewise. -+ * ld-size/size64-2-x32.d: Likewise. -+ * ld-size/size64-2-x86-64.d: Likewise. -+ * ld-size/size64-2.s: Likewise. -+ * ld-size/size-3.c: Likewise. -+ * ld-size/size-3.out: Likewise. -+ * ld-size/size-3a.c: Likewise. -+ * ld-size/size-3b.c: Likewise. -+ * ld-size/size-3c.c: Likewise. -+ * ld-size/size-4.out: Likewise. -+ * ld-size/size-4a.c: Likewise. -+ * ld-size/size-4b.c: Likewise. -+ * ld-size/size-5.out: Likewise. -+ * ld-size/size-5a.c: Likewise. -+ * ld-size/size-5b.c: Likewise. -+ * ld-size/size-6.out: Likewise. -+ * ld-size/size-6a.c: Likewise. -+ * ld-size/size-6b.c: Likewise. -+ * ld-size/size-7.rd: Likewise. -+ * ld-size/size-7a.c: Likewise. -+ * ld-size/size-7b.c: Likewise. -+ * ld-size/size-8.rd: Likewise. -+ * ld-size/size-8a.c: Likewise. -+ * ld-size/size-8b.c: Likewise. -+ -+2013-01-16 Alan Modra -+ -+ * ld-plugin/lto.exp (lto-9.o, pr13229.o): Pass -finline. -+ -+2013-01-15 Alan Modra -+ -+ * ld-powerpc/tlsso.d: Adjust for plt-thread-safe stubs. -+ * ld-powerpc/tlsso.g: Likewise. -+ * ld-powerpc/tlsso.r: Likewise. -+ * ld-powerpc/tlstocso.d: Likewise. -+ * ld-powerpc/tlstocso.g: Likewise. -+ -+2013-01-15 Alan Modra -+ -+ * ld-plugin/lto-16a.d: Match powerpc64 function symbol type. -+ * ld-plugin/lto-16b.d: Likewise. -+ * ld-plugin/lto-17a.d: Likewise. -+ * ld-plugin/lto-17b-2.d: Likewise. -+ -+2013-01-14 Alan Modra -+ -+ * ld-elf/pr14926.d: Disable for d10v, msp, xstormy. -+ * ld-elf/sec-to-seg.exp: Choose correct variant output to suit -+ updated microblaze page size. -+ -+2013-01-10 Will Newton -+ -+ * ld-elf/merge.d: Mark Meta as xfail. -+ * ld-gc/start.d: Skip this test on Meta. -+ * ld-gc/personality.d: Skip this test on Meta. -+ * ld-metag/external.s: New file. -+ * ld-metag/metag.exp: New file. -+ * ld-metag/pcrel.d: New file. -+ * ld-metag/pcrel.s: New file. -+ * ld-metag/shared.d: New file. -+ * ld-metag/shared.r: New file. -+ * ld-metag/shared.s: New file. -+ * ld-metag/stub.d: New file. -+ * ld-metag/stub.s: New file. -+ * ld-metag/stub_pic_app.d: New file. -+ * ld-metag/stub_pic_app.r: New file. -+ * ld-metag/stub_pic_app.s: New file. -+ * ld-metag/stub_pic_shared.d: New file. -+ * ld-metag/stub_pic_shared.s: New file. -+ * ld-metag/stub_shared.d: New file. -+ * ld-metag/stub_shared.r: New file. -+ * ld-metag/stub_shared.s: New file. -+ -+2013-01-08 Thomas Schwinge -+ -+ * ld-i386/export-class.exp: Restore (and reword) comment about -+ excluded targets. -+ -+2013-01-04 Yufeng Zhang -+ -+ * ld-aarch64/emit-relocs-264.d: Append the '-Mno-aliases' option to -+ the objdump directive. -+ * ld-aarch64/emit-relocs-266.d: Ditto. -+ * ld-aarch64/emit-relocs-268.d: Ditto. -+ * ld-aarch64/emit-relocs-269.d: Ditto. -+ * ld-aarch64/emit-relocs-270.d: Ditto. -+ * ld-aarch64/emit-relocs-271.d: Ditto. -+ * ld-aarch64/emit-relocs-272.d: Ditto. -+ -+For older changes see ChangeLog-2012 ++2014-04-17 Kwok Cheung Yeung ++ ++ * ld-mips-elf/elf-rel-xgot-n32.d: Update for new GOT layout. ++ * ld-mips-elf/elf-rel-xgot-n32-embed.d: Likewise. ++ * ld-mips-elf/elf-rel-xgot-n64.d: Likewise. ++ * ld-mips-elf/elf-rel-xgot-n64-embed.d: Likewise. ++ * ld-mips-elf/elf-rel-xgot-n64-linux.d: Likewise. ++ ++2014-04-15 Marcus Shawcroft ++ ++ * ld-aarch64/tls-relax-gdesc-ie.s (var): Adjust test case ++ to include all 5 bits of LDR destination register. ++ ++2014-04-10 Senthil Kumar Selvaraj ++ ++ * ld-avr/norelax_diff.d: New testcase. ++ * ld-avr/relax_diff.d: Likewise. ++ * ld-avr/relax.s: Likewise. ++ ++2014-04-05 Andreas Schwab ++ ++ * ld-plugin/lto.exp: Make "-Wp," prefix optional when filtering ++ out _FORTIFY_SOURCE. ++ ("Build libdummy.a 9", "PR ld/12696"): Mark as c++. ++ ++2014-04-04 Alan Modra ++ ++ * ld-scripts/fill.d, * ld-scripts/fill.t, * ld-scripts/fill_0.s, ++ * ld-scripts/fill_1.s, * ld-scripts/fill_2.s: New test. ++ * ld-scripts/data.exp: Run it. ++ ++2014-03-31 Marcus Shawcroft ++ ++ * ld-aarch64/eh-frame.d: Adjust FDE pc address. ++ ++2014-03-27 H.J. Lu ++ ++ PR ld/16756 ++ * ld-plugin/lto.exp: Expect filename and line number for PR ++ ld/12760 test. ++ ++2014-03-27 Yury Gribov ++ Pavel Fedin ++ ++ * ld-arm/arm-app-abs32.d: Update expected disassembly, taking into ++ account the pretty printing of PLT entries. ++ * ld-arm/arm-app.d: Likewise. ++ * ld-arm/arm-lib-plt32.d: Likewise. ++ * ld-arm/arm-lib.d: Likewise. ++ * ld-arm/armthumb-lib.d: Likewise. ++ * ld-arm/cortex-a8-fix-b-plt.d: Likewise. ++ * ld-arm/cortex-a8-fix-bcc-plt.d: Likewise. ++ * ld-arm/cortex-a8-fix-bl-plt.d: Likewise. ++ * ld-arm/cortex-a8-fix-bl-rel-plt.d: Likewise. ++ * ld-arm/cortex-a8-fix-blx-plt.d: Likewise. ++ * ld-arm/farcall-mixed-app-v5.d: Likewise. ++ * ld-arm/farcall-mixed-app.d: Likewise. ++ * ld-arm/farcall-mixed-lib-v4t.d: Likewise. ++ * ld-arm/farcall-mixed-lib.d: Likewise. ++ * ld-arm/ifunc-10.dd: Likewise. ++ * ld-arm/ifunc-14.dd: Likewise. ++ * ld-arm/ifunc-15.dd: Likewise. ++ * ld-arm/ifunc-3.dd: Likewise. ++ * ld-arm/ifunc-4.dd: Likewise. ++ * ld-arm/ifunc-7.dd: Likewise. ++ * ld-arm/ifunc-8.dd: Likewise. ++ * ld-arm/ifunc-9.dd: Likewise. ++ * ld-arm/long-plt-format.d: Likewise. ++ * ld-arm/mixed-app-v5.d: Likewise. ++ * ld-arm/mixed-app.d: Likewise. ++ * ld-arm/mixed-lib.d: Likewise. ++ * ld-arm/thumb2-bl-undefweak.d: Likewise. ++ * ld-arm/thumb2-bl-undefweak1.d: Likewise. ++ ++2014-03-26 Alan Modra ++ ++ * ld-powerpc/startv1.s, * ld-powerpc/startv2.s, * ld-powerpc/funref.s, ++ * ld-powerpc/funv1.s, * ld-powerpc/funv2.s, ++ * ld-powerpc/ambiguousv1.d, * ld-powerpc/ambiguousv2.d: New test files. ++ * ld-powerpc/powerpc.exp: Run new tests. ++ ++2014-03-25 Will Newton ++ ++ * ld-aarch64/aarch64-elf.exp: Add relasz dump test. ++ * ld-aarch64/relasz.d: New file. ++ * ld-aarch64/relasz.s: Likewise. ++ ++2014-03-20 Richard Sandiford ++ ++ * ld-elf/merge.d: Remove MIPS XFAIL. ++ ++2014-03-20 Will Newton ++ ++ * ld-arm/ifunc-14.rd: Update symbol values. ++ ++2014-03-19 Nick Clifton ++ ++ * config/default.exp (ASFLAGS): For the RX target add: ++ -muse-conventional-section-names. ++ ++2014-03-15 Alan Modra ++ ++ * ld-powerpc/vle-reloc-3.d: Remove addresses. ++ ++2014-03-14 Alan Modra ++ ++ * ld-powerpc/vle.ld: Place .PPC.EMB.sdata0 within 32k of 0. ++ * ld-powerpc/vle-reloc-3.d: Update. ++ ++2014-03-06 Roland McGrath ++ ++ * ld-arm/gc-hidden-1.d: Remove target, add not-target to match ++ other ELF-only tests in this directory. Loosen regexps so they ++ don't care what the exact addresses are. ++ ++2014-03-06 Roland McGrath ++ ++ * ld-arm/arm-elf.exp (armelftests_common): Move long-plt case ... ++ (armelftests_nonacl): ... here. ++ ++2014-03-05 Alan Modra ++ ++ Update copyright years. ++ ++2014-03-05 Alan Modra ++ ++ * ld-powerpc/elfv2-2a.s, ld-powerpc/elfv2-2b.s: New files. ++ * ld-powerpc/elfv2-2exe.d, ld-powerpc/elfv2-2so.d: New files. ++ * ld-powerpc/powerpc.exp: Run new test. ++ ++2014-03-03 Alan Modra ++ ++ * ld-scripts/phdrs2.exp: Correct copyright punctuation. ++ * ld-v850/v850.exp: Correct copyright typo. ++ ++2014-03-01 Yuri Gribov ++ ++ * ld-arm/long-plt-format.d, ld-arm/arm-elf.exp: Adjust for arm-eabi. ++ ++2014-02-27 Yuri Gribov ++ ++ * ld-arm/long-plt-format.s: New test case. ++ * ld-arm/long-plt-format.d: Expected disassembly. ++ * ld-arm/arm-elf.exp: Run the new test. ++ ++2014-02-27 Nick Clifton ++ ++ * ld-pe/longsecn-1.d: Allow for extra sections. ++ * ld-pe/longsecn-2.d: Likewise. ++ * ld-pe/longsecn.d: Likewise. ++ * ld-pe/secrel.d: Likewise. ++ ++2014-02-21 Alan Modra ++ ++ * ld-bootstrap/bootstrap.exp: Add ppc476 workaround test. ++ * ld-bootstrap/ppc476.t: New file. ++ ++2014-02-19 Igor Zamyatin ++ H.J. Lu ++ ++ * ld-x86-64/mpx.exp: Run bnd-ifunc-1 and bnd-plt-1. ++ * ld-x86-64/bnd-ifunc-1.d: New file. ++ * ld-x86-64/bnd-ifunc-1.s: Likewise. ++ * ld-x86-64/bnd-plt-1.d: Likewise. ++ ++2014-02-18 Jack Carter ++ ++ * ld-mips-elf/pic-and-nonpic-3a.sd: Check DYNAMIC segment flags. ++ ++2014-02-16 Thomas Schwinge ++ ++ * ld-elfweak/elfweak.exp (setup_xfail_gnu_hurd): Remove function ++ and all usage of it. ++ ++2014-02-10 H.J. Lu ++ ++ PR gold/16530 ++ * ld-elf/dynamic-1.c: New file. ++ * ld-elf/dynamic-1.rd: Likewise. ++ * ld-elf/dynamic-1.syms: Likewise. ++ ++ * ld-elf/shared.exp (build_tests): Add dynamic-1. ++ ++2014-02-02 Sebastian Huber ++ ++ * ld-scripts/rgn-at9.d: New file. ++ * ld-scripts/rgn-at9.t: Likewise. ++ * ld-scripts/rgn-at10.d: Likewise. ++ * ld-scripts/rgn-at10.s: Likewise. ++ * ld-scripts/rgn-at10.t: Likewise. ++ * ld-scripts/rgn-at11.d: Likewise. ++ * ld-scripts/rgn-at11.t: Likewise. ++ ++2014-01-30 Sandra Loosemore ++ ++ * ld-nios2/relax_call26.s: New. ++ * ld-nios2/relax_call26_boundary.ld: New. ++ * ld-nios2/relax_call26_boundary.s: New. ++ * ld-nios2/relax_call26_boundary_c8.d: New. ++ * ld-nios2/relax_call26_boundary_cc.d: New. ++ * ld-nios2/relax_call26_boundary_d0.d: New. ++ * ld-nios2/relax_call26_boundary_d4.d: New. ++ * ld-nios2/relax_call26_boundary_d8.d: New. ++ * ld-nios2/relax_call26_boundary_dc.d: New. ++ * ld-nios2/relax_call26_boundary_f0.d: New. ++ * ld-nios2/relax_call26_boundary_f4.d: New. ++ * ld-nios2/relax_call26_boundary_f8.d: New. ++ * ld-nios2/relax_call26_boundary_fc.d: New. ++ * ld-nios2/relax_call26_cache.d: New. ++ * ld-nios2/relax_call26_cache.ld: New. ++ * ld-nios2/relax_call26_cache.s: New. ++ * ld-nios2/relax_call26_multi.d: New. ++ * ld-nios2/relax_call26_multi.ld: New. ++ * ld-nios2/relax_call26_norelax.d: New. ++ * ld-nios2/relax_call26_shared.d: New. ++ * ld-nios2/relax_call26_shared.ld: New. ++ ++2014-01-29 H.J. Lu ++ ++ * ld-elf/rdynamic-1.c: New file. ++ * ld-elf/rdynamic-1.rd: Likewise. ++ ++ * ld-elf/shared.exp (build_tests): Add rdynamic-1. ++ ++2014-01-28 Nick Clifton ++ ++ PR binutils/16317 ++ * ld-tic6x/shlib-1.rd: Expect I attribute with RELA sections. ++ * ld-tic6x/shlib-1b.rd: Likewise. ++ * ld-tic6x/shlib-1r.rd: Likewise. ++ * ld-tic6x/shlib-1rb.rd: Likewise. ++ * ld-tic6x/shlib-app-1rd: Likewise. ++ * ld-tic6x/shlib-app-1b.rd: Likewise. ++ * ld-tic6x/shlib-app-1r.rd: Likewise. ++ * ld-tic6x/shlib-app-1rb.rd: Likewise. ++ * ld-tic6x/shlib-noindex.rd: Likewise. ++ * ld-tic6x/static-app-1.rd: Likewise. ++ * ld-tic6x/static-app-1b.rd: Likewise. ++ * ld-tic6x/static-app-1r.rd: Likewise. ++ * ld-tic6x/static-app-1rb.rd: Likewise. ++ PR binutils/16318 ++ * ld-tic6x/tic6x.exp: Expect C6000 osabi value in relocatable ++ objects. ++ ++2014-01-24 H.J. Lu ++ ++ * ld-elf/pr16498a.s: Replace .align with .p2align. ++ ++2014-01-24 H.J. Lu ++ ++ PR ld/16498 ++ * ld-elf/pr16498b.d: New file. ++ * ld-elf/pr16498b.t: Likewise. ++ ++2014-01-24 H.J. Lu ++ ++ PR ld/16498 ++ * ld-elf/pr16498a.d: New file. ++ * ld-elf/pr16498a.s: Likewise. ++ * ld-elf/pr16498a.t: Likewise. ++ ++2014-01-22 Alan Modra ++ ++ * ld-scripts/pr14962-2.d: Correct target triple. ++ ++2014-01-22 Alan Modra ++ ++ * ld-shared/elf-offset.ld: Align end of .bss with canonical form ++ of ALIGN that allows an empty .bss to be removed. ++ * ld-arm/arm-dyn.ld: Likewise. ++ * ld-arm/arm-lib.ld: Likewise. ++ * ld-elfvsb/elf-offset.ld: Likewise. ++ * ld-mips-elf/mips-dyn.ld: Likewise. ++ * ld-mips-elf/mips-lib.ld: Likewise. ++ * ld-arm/arm-no-rel-plt.ld: Remove duplicate ALIGN. ++ * ld-powerpc/vle-multiseg-1.ld: Remove ALIGN at start of section. ++ ALIGN address of section instead. ++ * ld-powerpc/vle-multiseg-2.ld: Likewise. ++ * ld-powerpc/vle-multiseg-3.ld: Likewise. ++ * ld-powerpc/vle-multiseg-4.ld: Likewise. ++ * ld-powerpc/vle-multiseg-6.ld: Likewise. ++ * ld-scripts/empty-aligned.d: Check section headers not program ++ headers. Remove xfail and notarget. ++ * ld-scripts/empty-aligned.t: Use canonical ALIGN for end of .text2. ++ ++2014-01-21 H.J. Lu ++ ++ PR ld/16467 ++ * ld-ifunc/dummy.c: New file. ++ * ld-ifunc/pr16467.out: Likewise. ++ * ld-ifunc/pr16467a.c: Likewise. ++ * ld-ifunc/pr16467a.map: Likewise. ++ * ld-ifunc/pr16467b.c: Likewise. ++ * ld-ifunc/pr16467b.map: Likewise. ++ * ld-ifunc/pr16467c.c: Likewise. ++ ++ * ld-ifunc/ifunc.exp (run_cc_link_tests): New. ++ (run_ld_link_exec_tests): Run pr16467. ++ ++2014-01-21 H.J. Lu ++ ++ PR ld/2404 ++ * ld-elf/shared.exp: Add a PIE test for PR ld/2404. ++ ++2014-01-20 H.J. Lu ++ ++ PR ld/2404 ++ * ld-elf/pr2404.out: New file. ++ * ld-elf/pr2404a.c: Likewise. ++ * ld-elf/pr2404b.c: Likewise. ++ ++ * ld-elf/shared.exp (build_tests): Build libpr2404a.so and ++ libpr2404b.a. ++ (run_tests): Run pr2404. ++ ++2014-01-20 Alan Modra ++ ++ * ld-scripts/pr14962-2.d, ++ * ld-scripts/pr14962-2.t: New test. ++ * ld-scripts/expr.exp: Run it. ++ ++2014-01-15 Alan Modra ++ ++ * ld-elf/ehdr_start-shared.d: New. ++ * ld-elf/ehdr_start-userdef.d: xfail frv. ++ * ld-elf/ehdr_start-weak.d: Likewise. ++ * ld-elf/ehdr_start.d: Likewise. ++ ++2014-01-14 Vidya Praveen ++ ++ * lib/ld-lib.exp (default_ld_link): Remove support for ldflags. ++ (default_ld_simple_link): Likewise. ++ ++2014-01-10 Alan Modra ++ ++ * ld-x86-64/pr14207.d: Adjust. ++ ++2014-01-09 H.J. Lu ++ ++ * ld-elf/binutils.exp (binutils_test): Check if GNU_RELRO segment ++ is generated. ++ ++2014-01-09 Vidya Praveen ++ ++ * lib/ld-lib.exp (check_lto_shared_available): New check. ++ * ld-plugin/lto.exp: Use check_lto_shared_available. ++ ++2014-01-08 H.J. Lu ++ ++ PR ld/14207 ++ PR ld/16322 ++ PR binutils/16323 ++ * ld-elf/pr16322.d: New file. ++ * ld-elf/pr16322.s: Likewise. ++ ++ * ld-x86-64/pr14207.d: Expect PT_GNU_RELRO segment. ++ ++For older changes see ChangeLog-2013 + -+Copyright (C) 2013 Free Software Foundation, Inc. ++Copyright (C) 2014 Free Software Foundation, Inc. + +Copying and distribution of this file, with or without modification, +are permitted in any medium without royalty provided the copyright @@ -2725626,6 +2738608,1676 @@ index 0000000..5b0ef94 +fill-column: 74 +version-control: never +End: +diff --git a/ld/testsuite/ChangeLog-2013 b/ld/testsuite/ChangeLog-2013 +new file mode 100644 +index 0000000..519c2cd +--- /dev/null ++++ b/ld/testsuite/ChangeLog-2013 +@@ -0,0 +1,1664 @@ ++2013-12-19 H.J. Lu ++ ++ PR binutils/16317 ++ * ld-elf/linkinfo1.s: New file. ++ * ld-elf/linkinfo1a.d: Likewise. ++ * ld-elf/linkinfo1b.d: Likewise. ++ ++2013-12-18 Vidya Praveen ++ ++ * lib/ld-lib.exp (check_lto_available): Support cflags, ldflags and ++ test by compiling for an executable rather than shared library. ++ ++2013-12-13 Vidya Praveen ++ ++ * lib/ld-lib.exp (default_ld_link): Use ldflags from board description ++ file. ++ (default_ld_simple_link): Likewise. ++ (default_ld_compile): Use cflags from board description file. ++ ++2013-12-13 Kuan-Lin Chen ++ ++ * lib/ld-lib.exp: Add NDS32 to list of targets that do not support ++ shared library generation. ++ * ld-nds32: New directory. ++ * ld-nds32/branch.d: New test. ++ * ld-nds32/branch.ld: New test. ++ * ld-nds32/branch.s: New test. ++ * ld-nds32/diff.d: New test. ++ * ld-nds32/diff.ld: New test. ++ * ld-nds32/diff.s: New test. ++ * ld-nds32/gp.d: New test. ++ * ld-nds32/gp.ld: New test. ++ * ld-nds32/gp.s: New test. ++ * ld-nds32/imm.d: New test. ++ * ld-nds32/imm.ld: New test. ++ * ld-nds32/imm.s: New test. ++ * ld-nds32/imm_symbol.s: New test. ++ * ld-nds32/relax_jmp.d: New test. ++ * ld-nds32/relax_jmp.ld: New test. ++ * ld-nds32/relax_jmp.s: New test. ++ * ld-nds32/relax_load_store.d: New test. ++ * ld-nds32/relax_load_store.ld: New test. ++ * ld-nds32/relax_load_store.s: New test. ++ * ld-nds32/nds32.exp: New file. ++ ++2013-12-12 H.J. Lu ++ ++ * ld-elf/ehdr_start-userdef.d: Add "#...". ++ ++2013-12-12 H.J. Lu ++ ++ * ld-pie/vaddr-0.d: New file. ++ * ld-pie/vaddr-1.d: Likewise. ++ * ld-pie/vaddr.s: Likewise. ++ ++2013-12-11 Will Newton ++ ++ * ld-aarch64/ifunc-21.d: Make test more generic to support ++ aarch64_be and ELF targets. ++ * ld-aarch64/ifunc-22.d: Likewise. ++ ++2013-12-11 H.J. Lu ++ ++ * ld-elf/shared.exp (build_tests): Add libneeded2a.so, ++ libneeded2b.so, libneeded2c.o and needed2. ++ ++ * ld-elf/needed2.ver: New file. ++ * ld-elf/needed2a.c: Likewise. ++ * ld-elf/needed2b.c: Likewise. ++ * ld-elf/needed2c.c: Likewise. ++ ++2013-12-07 Mike Frysinger ++ ++ * ld-pe/aligncomm-1.c: Remove +x file mode. ++ * ld-pe/aligncomm-2.c: Likewise. ++ * ld-pe/aligncomm-3.c: Likewise. ++ * ld-pe/aligncomm-4.c: Likewise. ++ * ld-pe/aligncomm.d: Likewise. ++ * ld-pe/export_dynamic_warning.s: Likewise. ++ * ld-pe/exports64.d: Likewise. ++ * ld-pe/longsecn-1.d: Likewise. ++ * ld-pe/longsecn-2.d: Likewise. ++ * ld-pe/longsecn-3.d: Likewise. ++ * ld-pe/longsecn-4.d: Likewise. ++ * ld-pe/longsecn-5.d: Likewise. ++ * ld-pe/longsecn.d: Likewise. ++ * ld-pe/longsecn.s: Likewise. ++ * ld-pe/non-c-lang-syms.d: Likewise. ++ * ld-pe/non-c-lang-syms.s: Likewise. ++ * ld-pe/pe-compile.exp: Likewise. ++ * ld-pe/pe-run.exp: Likewise. ++ * ld-pe/tlssec.s: Likewise. ++ * ld-pe/tlssec32.d: Likewise. ++ * ld-pe/tlssec64.d: Likewise. ++ * ld-pe/vers-script-1.ver: Likewise. ++ * ld-pe/vers-script-2.ver: Likewise. ++ * ld-pe/vers-script-3.ver: Likewise. ++ * ld-pe/vers-script-4.ver: Likewise. ++ * ld-pe/vers-script-dll.c: Likewise. ++ ++2013-11-27 Kyrylo Tkachov ++ ++ * ld-plugin/lto.exp: Add -ffat-lto-objects. ++ * lib/ld-lib.exp (check_lto_available): Likewise. ++ ++2013-11-27 Matthew Fortune ++ ++ * ld-mips-elf/mips-elf.exp: Consider mips-mti-elf the same as ++ mips-sde-elf ++ ++2013-11-26 H.J. Lu ++ ++ PR ld/16259 ++ * config/default.exp (get_target_emul): Also set HOSTING_SLIBS. ++ * lib/ld-lib.exp (default_ld_link): Use HOSTING_SLIBS for -pie. ++ ++2013-11-26 Will Newton ++ ++ * ld-aarch64/aarch64-elf.exp: Add ifunc-22. ++ * ld-aarch64/ifunc-22.d: New file. ++ * ld-aarch64/ifunc-22.s: Likewise. ++ ++2013-11-26 Will Newton ++ ++ * ld-aarch64/aarch64-elf.exp: Add ifunc-21 test. ++ * ld-aarch64/ifunc-21.d: New file. ++ * ld-aarch64/ifunc-21.s: Likewise. ++ ++2013-11-21 H.J. Lu ++ ++ * ld-x86-64/mpx.exp: Run bnd-branch-1. ++ * ld-x86-64/bnd-branch-1.d: New file. ++ * ld-x86-64/bnd-branch-1.s: Likewise. ++ ++2013-11-20 H.J. Lu ++ ++ * ld-x86-64/mpx.exp (build_tests): Add libmpx2a.a, libmpx2b.a ++ and libmpx2c.a. ++ (run_tests): Add mpx1static, mpx2 and mpx2static. ++ * ld-x86-64/mpx2.out: Likewise. ++ * ld-x86-64/mpx2a.c: Likewise. ++ * ld-x86-64/mpx2a.rd: Likewise. ++ * ld-x86-64/mpx2b.c: Likewise. ++ * ld-x86-64/mpx2c.c: Likewise. ++ * ld-x86-64/mpx2c.rd: Likewise. ++ ++2013-11-19 Roland McGrath ++ ++ * ld-elf/ehdr_start-userdef.t: New file. ++ * ld-elf/ehdr_start-userdef.d: New file. ++ * ld-elf/ehdr_start-strongref.s: New file. ++ * ld-elf/ehdr_start-missing.t: New file. ++ * ld-elf/ehdr_start-missing.d: New file. ++ * ld-elf/ehdr_start-weak.d: New file. ++ * ld-mips-elf/ehdr_start-2.nd: Expect __ehdr_start to be global. ++ ++2013-11-17 H.J. Lu ++ ++ * ld-x86-64/mpx.exp: New file. ++ * ld-x86-64/mpx1.out: Likewise. ++ * ld-x86-64/mpx1a.c: Likewise. ++ * ld-x86-64/mpx1a.rd: Likewise. ++ * ld-x86-64/mpx1b.c: Likewise. ++ * ld-x86-64/mpx1c.c: Likewise. ++ * ld-x86-64/mpx1c.rd: Likewise. ++ ++2013-11-14 Will Newton ++ ++ * ld-arm/script-type.sym: Remove redundant STT_FILE symbol. ++ ++2013-11-07 Roland McGrath ++ ++ * ld-x86-64/x86-64.exp (mixed1, mixed2): Loosen error string match ++ so it accepts "i386:nacl" in place of "i386". ++ * ld-x86-64/ilp32-2.d: Likewise. ++ * ld-x86-64/ilp32-3.d: Likewise. ++ * ld-x86-64/lp64-2.d: Likewise. ++ * ld-x86-64/lp64-3.d: Likewise. ++ ++2013-11-05 H.J. Lu ++ ++ PR ld/4409 ++ * ld-ia64/error1.d: New file. ++ * ld-ia64/error1.s: Likewise. ++ * ld-ia64/error2.d: Likewise. ++ * ld-ia64/error3.d: Likewise. ++ ++2013-11-04 Alan Modra ++ ++ * ld-powerpc/elfv2exe.d: Adjust for non-PIC global entry. ++ ++2013-11-04 Alan Modra ++ ++ * ld-elfvers/vers24.rd: Allow extra readelf output after ++ symbol visibility. ++ * ld-ifunc/ifunc.exp: Likewise. ++ ++2013-11-04 Alan Modra ++ ++ * ld-scripts/crossref.exp: Don't allow changes made to CFLAGS ++ for this test to bleed into following tests. Don't set ++ -mcall-aixdesc for powerpc64le. ++ ++2013-11-02 Alan Modra ++ ++ * ld-pe/cfi.d: Allow wide display of addresses. ++ ++2013-11-01 Roland McGrath ++ ++ * ld-x86-64/plt-nacl.pd: Update expected disassembly for PLT nop fix. ++ * ld-x86-64/tlsdesc-nacl.pd: Likewise. ++ ++2013-10-30 Alan Modra ++ ++ * ld-powerpc/elfv2.s, ++ * ld-powerpc/elfv2so.d, ++ * ld-powerpc/elfv2exe.d: New tests. ++ * ld-powerpc/powerpc.exp: Run them. ++ ++2013-10-30 Alan Modra ++ ++ * ld-powerpc/tls.s: Add proper .opd entry for _start. ++ * ld-powerpc/tlstoc.s: Likewise. ++ * ld-powerpc/relbrlt.d: Update for changed stubs. ++ * ld-powerpc/tls.d: Update for changed stubs and _start .opd entry. ++ * ld-powerpc/tls.g: Likewise. ++ * ld-powerpc/tlsexe.d: Likewise. ++ * ld-powerpc/tlsexe.g: Likewise. ++ * ld-powerpc/tlsexe.r: Likewise. ++ * ld-powerpc/tlsexetoc.d: Likewise. ++ * ld-powerpc/tlsexetoc.g: Likewise. ++ * ld-powerpc/tlsexetoc.r: Likewise. ++ * ld-powerpc/tlsso.d: Likewise. ++ * ld-powerpc/tlsso.g: Likewise. ++ * ld-powerpc/tlsso.r: Likewise. ++ * ld-powerpc/tlstoc.d: Likewise. ++ * ld-powerpc/tlstoc.g: Likewise. ++ * ld-powerpc/tlstocso.d: Likewise. ++ * ld-powerpc/tlstocso.g: Likewise. ++ * ld-powerpc/tlstocso.r: Likewise. ++ ++2013-10-29 Jan Beulich ++ ++ * ld-cris/tls-e-tpoffcomm1.d: Drop expectation of no longer ++ present STT_FILE symbol. ++ * ld-mmix/bpo-18.d: Likewise. ++ * ld-mmix/bpo-22.d: Likewise. ++ * ld-mmix/greg-6.d: Likewise. ++ * ld-mmix/greg-7.d: Likewise. ++ * ld-mmix/loc4.d: Likewise. ++ * ld-mmix/local1.d: Likewise. ++ * ld-mmix/local3.d: Likewise. ++ * ld-mmix/local5.d: Likewise. ++ * ld-mmix/local7.d: Likewise. ++ * ld-mmix/loct-1.d: Likewise. ++ * ld-sh/sh64/abi32.xd: Likewise. ++ * ld-sh/sh64/abi64.xd: Likewise. ++ * ld-sh/sh64/cmpct1.xd: Likewise. ++ * ld-sh/sh64/crange1.rd: Likewise. ++ * ld-sh/sh64/crange2.rd: Likewise. ++ * ld-sh/sh64/crange3-cmpct.rd: Likewise. ++ * ld-sh/sh64/crange3-media.rd: Likewise. ++ * ld-sh/sh64/crange3.rd: Likewise. ++ * ld-sh/sh64/crangerel1.rd: Likewise. ++ * ld-sh/sh64/crangerel2.rd: Likewise. ++ * ld-sh/sh64/mix1.xd: Likewise. ++ * ld-sh/sh64/mix2.xd: Likewise. ++ * ld-sh/sh64/shdl32.xd: Likewise. ++ * ld-sh/sh64/shdl64.xd: Likewise. ++ ++2013-10-18 Hans-Peter Nilsson ++ ++ * ld-cris/asneed1.d: New test. ++ ++2013-10-14 Chao-ying Fu ++ ++ * ld-mips-elf/attr-gnu-8-0.s, ld-mips-elf/attr-gnu-8-1.s, ++ ld-mips-elf/attr-gnu-8-2.s, ++ ld-mips-elf/attr-gnu-8-00.d, ld-mips-elf/attr-gnu-8-01.d, ++ ld-mips-elf/attr-gnu-8-02.d, ld-mips-elf/attr-gnu-8-10.d, ++ ld-mips-elf/attr-gnu-8-11.d, ld-mips-elf/attr-gnu-8-12.d, ++ ld-mips-elf/attr-gnu-8-20.d, ld-mips-elf/attr-gnu-8-21.d, ++ ld-mips-elf/attr-gnu-8-22.d: New. ++ * ld-mips-elf/mips-elf.exp: Run new tests. ++ ++2013-10-13 Richard Sandiford ++ ++ * lib/ld-lib.exp (default_ld_compile): Add a -I option for the source ++ directory. ++ * ld-mips-elf/compressed-plt-1.ld, ld-mips-elf/compressed-plt-1.s, ++ ld-mips-elf/compressed-plt-1-dyn.s, ld-mips-elf/compressed-plt-1a.s, ++ ld-mips-elf/compressed-plt-1b.s, ld-mips-elf/compressed-plt-1c.s, ++ ld-mips-elf/compressed-plt-1d.s, ld-mips-elf/compressed-plt-1e.s, ++ ld-mips-elf/compressed-plt-1-o32-se.rd, ++ ld-mips-elf/compressed-plt-1-o32-se.od, ++ ld-mips-elf/compressed-plt-1-o32-mips16-only.rd, ++ ld-mips-elf/compressed-plt-1-o32-mips16-only.od, ++ ld-mips-elf/compressed-plt-1-o32-umips-only.rd, ++ ld-mips-elf/compressed-plt-1-o32-umips-only.od, ++ ld-mips-elf/compressed-plt-1-o32-mips16.rd, ++ ld-mips-elf/compressed-plt-1-o32-mips16.od, ++ ld-mips-elf/compressed-plt-1-o32-mips16-got.rd, ++ ld-mips-elf/compressed-plt-1-o32-mips16-got.od, ++ ld-mips-elf/compressed-plt-1-o32-mips16-word.rd, ++ ld-mips-elf/compressed-plt-1-o32-mips16-word.od, ++ ld-mips-elf/compressed-plt-1-o32-umips.rd, ++ ld-mips-elf/compressed-plt-1-o32-umips.od, ++ ld-mips-elf/compressed-plt-1-o32-umips-got.rd, ++ ld-mips-elf/compressed-plt-1-o32-umips-got.od, ++ ld-mips-elf/compressed-plt-1-o32-umips-word.rd, ++ ld-mips-elf/compressed-plt-1-o32-umips-word.od, ++ ld-mips-elf/compressed-plt-1-n32-mips16.rd, ++ ld-mips-elf/compressed-plt-1-n32-mips16.od, ++ ld-mips-elf/compressed-plt-1-n32-umips.rd, ++ ld-mips-elf/compressed-plt-1-n32-umips.od: New tests. ++ * ld-mips-elf/mips-elf.exp: Run them. ++ ++2013-10-13 Richard Sandiford ++ ++ * ld-mips-elf/pic-and-nonpic-6-n32.ad, ++ ld-mips-elf/pic-and-nonpic-6-n32.dd, ++ ld-mips-elf/pic-and-nonpic-6-n32.gd, ++ ld-mips-elf/pic-and-nonpic-6-n32.nd, ++ ld-mips-elf/pic-and-nonpic-6-n32.rd, ++ ld-mips-elf/pic-and-nonpic-6-n64.ad, ++ ld-mips-elf/pic-and-nonpic-6-n64.dd, ++ ld-mips-elf/pic-and-nonpic-6-n64.gd, ++ ld-mips-elf/pic-and-nonpic-6-n64.nd, ++ ld-mips-elf/pic-and-nonpic-6-n64.rd, ++ ld-mips-elf/pic-and-nonpic-6-o32.ad, ++ ld-mips-elf/pic-and-nonpic-6-o32.dd, ++ ld-mips-elf/pic-and-nonpic-6-o32.gd, ++ ld-mips-elf/pic-and-nonpic-6-o32.nd, ++ ld-mips-elf/pic-and-nonpic-6-o32.rd: Fix symbol value of extf4. ++ No longer expect extf3, extf4 and extd2 to be in the global GOT. ++ ++2013-10-03 Will Newton ++ ++ * ld-ifunc/ifunc.exp: Enable ifunc tests for AArch64. ++ * ld-aarch64/aarch64-elf.exp: Run ifunc tests. ++ * ld-aarch64/ifunc-1-local.d: New file. ++ * ld-aarch64/ifunc-1-local.s: Likewise. ++ * ld-aarch64/ifunc-1.d: Likewise. ++ * ld-aarch64/ifunc-1.s: Likewise. ++ * ld-aarch64/ifunc-10.d: Likewise. ++ * ld-aarch64/ifunc-10.s: Likewise. ++ * ld-aarch64/ifunc-11.d: Likewise. ++ * ld-aarch64/ifunc-11.s: Likewise. ++ * ld-aarch64/ifunc-12.d: Likewise. ++ * ld-aarch64/ifunc-12.s: Likewise. ++ * ld-aarch64/ifunc-13.d: Likewise. ++ * ld-aarch64/ifunc-13a.s: Likewise. ++ * ld-aarch64/ifunc-13b.s: Likewise. ++ * ld-aarch64/ifunc-14a.d: Likewise. ++ * ld-aarch64/ifunc-14a.s: Likewise. ++ * ld-aarch64/ifunc-14b.d: Likewise. ++ * ld-aarch64/ifunc-14b.s: Likewise. ++ * ld-aarch64/ifunc-14c.d: Likewise. ++ * ld-aarch64/ifunc-14c.s: Likewise. ++ * ld-aarch64/ifunc-14d.d: Likewise. ++ * ld-aarch64/ifunc-14e.d: Likewise. ++ * ld-aarch64/ifunc-14f.d: Likewise. ++ * ld-aarch64/ifunc-15.d: Likewise. ++ * ld-aarch64/ifunc-15.s: Likewise. ++ * ld-aarch64/ifunc-16.d: Likewise. ++ * ld-aarch64/ifunc-16.s: Likewise. ++ * ld-aarch64/ifunc-17a.d: Likewise. ++ * ld-aarch64/ifunc-17a.s: Likewise. ++ * ld-aarch64/ifunc-17b.d: Likewise. ++ * ld-aarch64/ifunc-17b.s: Likewise. ++ * ld-aarch64/ifunc-18a.d: Likewise. ++ * ld-aarch64/ifunc-18a.s: Likewise. ++ * ld-aarch64/ifunc-18b.d: Likewise. ++ * ld-aarch64/ifunc-18b.s: Likewise. ++ * ld-aarch64/ifunc-19a.d: Likewise. ++ * ld-aarch64/ifunc-19a.s: Likewise. ++ * ld-aarch64/ifunc-19b.d: Likewise. ++ * ld-aarch64/ifunc-19b.s: Likewise. ++ * ld-aarch64/ifunc-2-local.d: Likewise. ++ * ld-aarch64/ifunc-2-local.s: Likewise. ++ * ld-aarch64/ifunc-2.d: Likewise. ++ * ld-aarch64/ifunc-2.s: Likewise. ++ * ld-aarch64/ifunc-20.d: Likewise. ++ * ld-aarch64/ifunc-20.s: Likewise. ++ * ld-aarch64/ifunc-3.s: Likewise. ++ * ld-aarch64/ifunc-3a.d: Likewise. ++ * ld-aarch64/ifunc-3b.d: Likewise. ++ * ld-aarch64/ifunc-4.d: Likewise. ++ * ld-aarch64/ifunc-4.s: Likewise. ++ * ld-aarch64/ifunc-4a.d: Likewise. ++ * ld-aarch64/ifunc-5-local.s: Likewise. ++ * ld-aarch64/ifunc-5.s: Likewise. ++ * ld-aarch64/ifunc-5a-local.d: Likewise. ++ * ld-aarch64/ifunc-5a.d: Likewise. ++ * ld-aarch64/ifunc-5b-local.d: Likewise. ++ * ld-aarch64/ifunc-5b.d: Likewise. ++ * ld-aarch64/ifunc-5r-local.d: Likewise. ++ * ld-aarch64/ifunc-6.s: Likewise. ++ * ld-aarch64/ifunc-6a.d: Likewise. ++ * ld-aarch64/ifunc-6b.d: Likewise. ++ * ld-aarch64/ifunc-7.s: Likewise. ++ * ld-aarch64/ifunc-7a.d: Likewise. ++ * ld-aarch64/ifunc-7b.d: Likewise. ++ * ld-aarch64/ifunc-7c.d: Likewise. ++ * ld-aarch64/ifunc-8.d: Likewise. ++ * ld-aarch64/ifunc-8a.s: Likewise. ++ * ld-aarch64/ifunc-8b.s: Likewise. ++ * ld-aarch64/ifunc-9.d: Likewise. ++ * ld-aarch64/ifunc-9.s: Likewise. ++ ++2013-09-24 Gregory Fong ++ ++ * ld-mips-elf/eh-frame5.d, ld-mips-elf/jalx-2.dd, ++ ld-mips-elf/mips-elf.exp, ld-mips-elf/mips16-pic-2.ad, ++ ld-mips-elf/mips16-pic-2.nd, ld-mips-elf/pic-and-nonpic-3a.dd, ++ ld-mips-elf/pic-and-nonpic-3b.ad, ld-mips-elf/pic-and-nonpic-3b.dd, ++ ld-mips-elf/pic-and-nonpic-3b.nd, ld-mips-elf/pic-and-nonpic-4b.ad, ++ ld-mips-elf/pic-and-nonpic-4b.nd, ld-mips-elf/pic-and-nonpic-4b.rd, ++ ld-mips-elf/pic-and-nonpic-5b.ad, ld-mips-elf/pic-and-nonpic-5b.nd, ++ ld-mips-elf/pic-and-nonpic-6-n32.ad, ++ ld-mips-elf/pic-and-nonpic-6-n32.dd, ++ ld-mips-elf/pic-and-nonpic-6-n32.nd, ++ ld-mips-elf/pic-and-nonpic-6-n64.ad, ++ ld-mips-elf/pic-and-nonpic-6-n64.dd, ++ ld-mips-elf/pic-and-nonpic-6-n64.nd, ++ ld-mips-elf/pic-and-nonpic-6-o32.ad, ++ ld-mips-elf/pic-and-nonpic-6-o32.dd, ++ ld-mips-elf/pic-and-nonpic-6-o32.nd, ld-mips-elf/rel32-n32.d, ++ ld-mips-elf/rel32-o32.d, ld-mips-elf/rel64.d, ++ ld-mips-elf/tls-multi-got-1.got, ld-mips-elf/tls-multi-got-1.r, ++ ld-mips-elf/tlsdyn-o32-1.d, ld-mips-elf/tlsdyn-o32-1.got, ++ ld-mips-elf/tlsdyn-o32-2.d, ld-mips-elf/tlsdyn-o32-2.got, ++ ld-mips-elf/tlsdyn-o32-3.d, ld-mips-elf/tlsdyn-o32-3.got, ++ ld-mips-elf/tlsdyn-o32.d, ld-mips-elf/tlsdyn-o32.got, ++ ld-mips-elf/tlslib-o32-ver.got, ld-mips-elf/tlslib-o32.got: Update ++ for removal of _GLOBAL_OFFSET_TABLE_ from .dynsym. ++ ++2013-09-18 Kyrylo Tkachov ++ ++ * ld-aarch64/eh-frame.d: Update expected output to allow for ++ 64-bit addresses. ++ ++2013-09-12 Nick Clifton ++ ++ * ld-elf/eh1.d: Update expected output to allow for ++ 64-bit addresses. ++ * ld-elf/eh2.d: Likewise. ++ * ld-elf/eh3.d: Likewise. ++ * ld-elf/eh4.d: Likewise. ++ * ld-elf/eh5.d: Likewise. ++ * ld-elf/eh6.d: Likewise. ++ * ld-mips-elf/eh-frame1-n64.d: Likewise. ++ * ld-mips-elf/eh-frame2-n64.d: Likewise. ++ * ld-mips-elf/eh-frame3.d: Likewise. ++ ++2013-09-04 Vidya Praveen ++ ++ * ld-arm/export-class.exp: Fix the condition. ++ ++2013-08-29 Jakub Jelinek ++ ++ * ld-x86-64/x86-64.exp: Add tlsld3, tlsgd7 and tlsgd8 tests. ++ * ld-x86-64/tlspic1.s: Add -mcmodel=large -fpic TLS GD and LD ++ sequences. ++ * ld-x86-64/tlspic.dd: Adjusted. ++ * ld-x86-64/tlspic.rd: Adjusted. ++ * ld-x86-64/tlspic-nacl.rd: Adjusted. ++ * ld-x86-64/tlsld3.dd: New test. ++ * ld-x86-64/tlsld3.s: New file. ++ * ld-x86-64/tlsgd7.dd: New test. ++ * ld-x86-64/tlsgd7.s: New file. ++ * ld-x86-64/tlsgd8.dd: New test. ++ * ld-x86-64/tlsgd8.s: New file. ++ ++2013-08-26 Roland McGrath ++ ++ * ld-x86-64/x86-64.exp (Mixed x86_64 and i386 input test 1): ++ Loosen string match to admit i386:x86-64*. ++ (Mixed x86_64 and i386 input test 2): Likewise. ++ * ld-x86-64/ilp32-2.d: Likewise. ++ * ld-x86-64/ilp32-3.d: Likewise. ++ * ld-x86-64/lp64-2.d: Likewise. ++ * ld-x86-64/lp64-3.d: Likewise. ++ * ld-x86-64/ia32-2.d: Likewise, and i386.* too. ++ * ld-x86-64/ia32-3.d: Likewise. ++ ++2013-08-26 Roland McGrath ++ ++ * ld-x86-64/ilp32-4-nacl.d: Loosen .shstrtab line regexp to match ++ any file offset. ++ * ld-x86-64/tlsbin-nacl.rd: Update expected code segment PT_LOAD. ++ * ld-x86-64/tlsbindesc-nacl.rd: Likewise. ++ * ld-scripts/rgn-at3.d: XFAIL for *-*-nacl* targets. ++ * ld-scripts/rgn-over8-ok.d: Likewise. ++ ++2013-08-24 Maciej W. Rozycki ++ ++ * ld-elf/comm-data.exp: Use check_shared_lib_support rather than ++ explicit patterns for test target qualification. Define extra ++ tool flags for *-*-hpux* and tic6x-*-* targets. Link with a ++ linker script. Use alternative patterns for targets that do not ++ eliminate copy relocs, currently mn10300-*-* and vax-*-*. ++ * ld-elf/comm-data2.s: Handle HPUX's `.comm' syntax. ++ * ld-elf/comm-data2.ld: New test linker script. ++ * ld-elf/comm-data2.xd: Match section's VMA too. Ignore ASCII ++ data dump. ++ * ld-elf/comm-data2r.rd: New test pattern. ++ * ld-elf/comm-data2r.sd: New test pattern. ++ * ld-elf/comm-data2r.xd: New test pattern. ++ * ld-mips-elf/comm-data.exp: Use check_shared_lib_support rather ++ than an explicit pattern for test target qualification. Link ++ with a linker script. ++ ++2013-08-24 Maciej W. Rozycki ++ ++ * ld-arm/export-class.exp: Handle non-EABI targets. ++ ++2013-08-23 Roland McGrath ++ ++ * ld-x86-64/ilp32-4-nacl.d: Update for 2013-05-31 gas alignment change. ++ * ld/testsuite/ld-x86-64/tlsbin-nacl.rd: Likewise. ++ * ld/testsuite/ld-x86-64/tlsbindesc-nacl.rd: Likewise. ++ * ld/testsuite/ld-x86-64/tlsdesc-nacl.rd: Likewise. ++ * ld/testsuite/ld-x86-64/tlspic-nacl.rd: Likewise. ++ ++2013-08-23 Yuri Chornoivan ++ ++ PR binutils/15834 ++ * ld-mips-elf/mips16-pic-1.inc: Fix typos. ++ ++2013-08-22 Alan Modra ++ ++ * ld-powerpc/powerpc.exp: Substitute for le in options_regsub(ld). ++ Correct ppc64elftests option replacement. ++ (supports_ppc64): Match elf64lppc too. ++ * ld-powerpc/relbrlt.d: Update for little-endian. ++ * ld-powerpc/symtocbase.d: Likewise. ++ * ld-powerpc/tls.t: Likewise. ++ * ld-powerpc/tlsexetoc.g: Likewise. ++ * ld-powerpc/tlsso.d: Likewise. ++ * ld-powerpc/tlsso.g: Likewise. ++ * ld-powerpc/tlstoc.t: Likewise. ++ * ld-powerpc/tlstocso.d: Likewise. ++ * ld-powerpc/tlstocso.g: Likewise. ++ * ld-powerpc/tlstocso.t: Likewise. ++ * ld-powerpc/tocopt.d: Likewise. ++ * ld-powerpc/tocopt2.d: Likewise. ++ * ld-powerpc/tocopt3.d: Likewise. ++ * ld-powerpc/tocopt4.d: Likewise. ++ * ld-powerpc/tocopt5.d: Likewise. ++ ++2013-08-14 Clemens Lang ++ ++ * ld-scripts/log2.exp: New: Run the new log2 test. ++ * ld-scripts/log2.s: Source for the new test. ++ * ld-scripts/log2.t: Linker script for new test. ++ ++2013-08-14 John Tytgat ++ ++ PR ld/15787 ++ * ld-arm/group-relocs-ldr-bad.s: Redefine bar into foo section ++ beyond 16 bit offset width. ++ * ld-arm/group-relocs-ldrs-bad.s: Likewise. ++ * ld-arm/group-relocs-ldr-bad.d: Adjust expected result. ++ * ld-arm/group-relocs-ldrs-bad.d: Likewise. ++ * ld-arm/group-relocs.s: Add comments. Move symbols used for sb ++ group relocations into .data section. Drop section zero. Use pc/r0 ++ as base register when pc/sb group relocations are used. ++ * ld-arm/group-relocs.d: Adjust expected result. ++ * ld-arm/group-relocs-alu-bad-2.d: New test for sb group relocation. ++ * ld-arm/group-relocs-ldc-bad-2.d: Likewise. ++ * ld-arm/group-relocs-ldr-bad-2.d: New test for pc group relocation. ++ * ld-arm/group-relocs-ldrs-bad-2.d: Likewise. ++ * ld-arm/unresolved-2.d: Add sb relocation failure test. ++ * ld-arm/group-relocs-alu-bad-2.s: New test source. ++ * ld-arm/group-relocs-ldr-bad-2.s: Likewise. ++ * ld-arm/group-relocs-ldrs-bad-2.s: Likewise. ++ * ld-arm/group-relocs-ldc-bad-2.s: Likewise. ++ * ld-arm/unresolved-2.s: Likewise. ++ * ld-arm/arm-elf.exp: For group-relocs, drop section zero start ++ definition. Run the new tests. ++ ++2013-08-09 Nick Clifton ++ ++ * lib/ld-lib.exp (check_shared_lib_support): Note that the RL78 ++ does not support shared library generation. ++ ++2013-07-31 John Tytgat ++ ++ PR ld/15787 ++ * ld-arm/group-relocs-alu-bad-2.d; New. ++ * ld-arm/group-relocs-alu-bad-2.s: New. ++ * ld-arm/group-relocs-ldc-bad-2.d: New. ++ * ld-arm/group-relocs-ldc-bad-2.s: New. ++ * ld-arm/group-relocs-ldr-bad-2.d: New. ++ * ld-arm/group-relocs-ldr-bad-2.s: New. ++ * ld-arm/group-relocs-ldrs-bad-2.d: New. ++ * ld-arm/group-relocs-ldrs-bad-2: New. ++ * ld-arm/arm-elf.exp: Add the new tests. ++ * ld-arm/group-relocs-ldr-bad.d: Update expected output. ++ * ld-arm/group-relocs-ldr-bad.s: Likewise. ++ * ld-arm/group-relocs-ldrs-bad.d: Likewise. ++ * ld-arm/group-relocs-ldrs-bad.s: Likewise. ++ * ld-arm/group-relocs.d: Likewise. ++ * ld-arm/group-relocs.s: Likewise. ++ ++2013-07-27 Maciej W. Rozycki ++ ++ * ld-vax-elf/export-class-call.dd: New test. ++ * ld-vax-elf/export-class-call.rd: New test. ++ * ld-vax-elf/export-class-call.xd: New test. ++ * ld-vax-elf/export-class-data.dd: New test. ++ * ld-vax-elf/export-class-data.rd: New test. ++ * ld-vax-elf/export-class-data.xd: New test. ++ * ld-vax-elf/export-class.ld: New test linker script. ++ * ld-vax-elf/export-class-call.s: New test source. ++ * ld-vax-elf/export-class-data.s: New test source. ++ * ld-vax-elf/export-class-def.s: New test source. ++ * ld-vax-elf/vax-elf.exp: Run the new tests. ++ * ld-vax-elf/vax-export-class.rd: New test. ++ * ld-vax-elf/vax-export-class.xd: New test. ++ * ld-vax-elf/export-class.exp: New test script. ++ ++2013-07-27 Maciej W. Rozycki ++ ++ * ld-vax-elf/got-local-exe.xd: New test. ++ * ld-vax-elf/got-local-lib.xd: New test. ++ * ld-vax-elf/got-local-aux.s: New test source. ++ * ld-vax-elf/got-local-def.s: New test source. ++ * ld-vax-elf/got-local-ref.s: New test source. ++ * ld-vax-elf/vax-elf.exp: Run the new tests. ++ ++2013-07-24 H.J. Lu ++ ++ PR ld/15762 ++ * ld-elf/shared.exp (build_tests): Check .gnu.warning section ++ in the libbarw.so library. ++ * ld-elf/libbarw.rd: New. ++ ++ * lib/ld-lib.exp (run_cc_link_tests): Support checking on ++ output with warning message. ++ ++2013-07-22 Sebastian Huber ++ ++ * ld-scripts/script.exp: Use run_dump_test instead of ++ ld_simple_link to check the error message. ++ * ld-scripts/align-with-input.d: New file. ++ * ld-scripts/region-alias-1.d: Likewise. ++ * ld-scripts/region-alias-2.d: Likewise. ++ * ld-scripts/region-alias-3.d: Likewise. ++ * ld-scripts/region-alias-4.d: Likewise. ++ ++2013-07-19 Sebastian Huber ++ ++ * ld-scripts/script.exp: Run align with input test. ++ * ld-scripts/align-with-input.t: New file. ++ * ld-scripts/rgn-at8.d: Likewise. ++ * ld-scripts/rgn-at8.t: Likewise. ++ ++2013-07-18 Terry Guo ++ ++ * ld-arm/thumb-b-lks-sym.d: Updated to be more flexible. ++ * ld-arm/thumb-bl-lks-sym.d: Likewise. ++ ++2013-07-18 Roland McGrath ++ ++ * ld-arm/farcall-arm-nacl.d: New file. ++ * ld-arm/farcall-arm-nacl-pic.d: New file. ++ * ld-arm/farcall-data-nacl.d: New file. ++ * ld-arm/arm-elf.exp (armeabitests_common): Add extra element to ++ "action" lists for those cases to use a different dump file for NaCl ++ targets. ++ Massage $armeabitests_common to drop the extra element or the one ++ before it, depending on [istarget "arm*-*-nacl*"]. ++ ++ * ld-arm/arm-elf.exp (armelftests_common): Move all "Cortex-A8 ++ erratum fix", Thumb-only and interworking cases to ... ++ (armelftests_nonacl): ... here. ++ (armeabitests_common): Move all "erratum 760522 fix", Thumb-only ++ and interworking cases to ... ++ (armeabitests_nonacl): ... here. ++ ++2013-07-12 Maciej W. Rozycki ++ ++ * ld-mips-elf/nan-2008.d: New test. ++ * ld-mips-elf/nan-legacy.d: New test. ++ * ld-mips-elf/nan-mixed-1.d: New test. ++ * ld-mips-elf/nan-mixed-2.d: New test. ++ * ld-mips-elf/nan-2008.s: New test source. ++ * ld-mips-elf/nan-legacy.s: New test source. ++ ++2013-07-03 Marcus Shawcroft ++ ++ * ld-aarch64/emit-relocs-309.s: Replace got_prel19 with got. ++ * ld-aarch64/gc-relocs-309.s: Likewise. ++ ++2013-07-02 Marcus Shawcroft ++ ++ * ld-aarch64/gc-plt-relocs.d: Adjust expected .got offsets. ++ * ld-aarch64/tls-desc-ie.d: Likewise. ++ * ld-aarch64/emit-relocs-311.d: Adjust expected symbol. ++ * ld-aarch64/tls-relax-all.d: Likewise. ++ * ld-aarch64/tls-relax-gd-ie.d: Likewise. ++ * ld-aarch64/tls-relax-gdesc-ie.d: Likewise. ++ * ld-aarch64/tls-relax-gdesc-ie-2.d: Likewise. ++ ++2013-07-01 H.J. Lu ++ ++ * ld-x86-64/tlsg.sd: Adjusted. ++ ++2013-06-28 H.J. Lu ++ ++ PR ld/15685 ++ * ld-x86-64/tlsg.s: Add a test for R_X86_64_DTPOFF64. ++ * ld-x86-64/tlsg.sd: Updated. ++ ++2013-06-24 Maciej W. Rozycki ++ ++ * ld-mips-elf/jalx-2.dd: Update for microMIPS PLT support. ++ * ld-mips-elf/pic-and-nonpic-3a.dd: Update for the _MIPS_STUBS_ ++ magic symbol. ++ * ld-mips-elf/pic-and-nonpic-3b.dd: Likewise. ++ * ld-mips-elf/pic-and-nonpic-6-n32.dd: Likewise. ++ * ld-mips-elf/pic-and-nonpic-6-n64.dd: Likewise. ++ * ld-mips-elf/pic-and-nonpic-6-o32.dd: Likewise. ++ * ld-mips-elf/stub-dynsym-1-10000.d: Likewise. ++ * ld-mips-elf/stub-dynsym-1-2fe80.d: Likewise. ++ * ld-mips-elf/stub-dynsym-1-7fff.d: Likewise. ++ * ld-mips-elf/stub-dynsym-1-8000.d: Likewise. ++ * ld-mips-elf/stub-dynsym-1-fff0.d: Likewise. ++ * ld-mips-elf/tlslib-o32.d: Likewise. ++ ++2013-06-19 Will Newton ++ ++ * ld-aarch64/aarch64-elf.exp: Remove ifunc tests. ++ * ld-ifunc/ifunc.exp: Disable ifunc tests on AArch64. ++ * ld-aarch64/ifunc-1-local.d: Remove. ++ * ld-aarch64/ifunc-1-local.s: Likewise. ++ * ld-aarch64/ifunc-1.d: Likewise. ++ * ld-aarch64/ifunc-1.s: Likewise. ++ * ld-aarch64/ifunc-10.d: Likewise. ++ * ld-aarch64/ifunc-10.s: Likewise. ++ * ld-aarch64/ifunc-11.d: Likewise. ++ * ld-aarch64/ifunc-11.s: Likewise. ++ * ld-aarch64/ifunc-12.d: Likewise. ++ * ld-aarch64/ifunc-12.s: Likewise. ++ * ld-aarch64/ifunc-13.d: Likewise. ++ * ld-aarch64/ifunc-13a.s: Likewise. ++ * ld-aarch64/ifunc-13b.s: Likewise. ++ * ld-aarch64/ifunc-14a.d: Likewise. ++ * ld-aarch64/ifunc-14a.s: Likewise. ++ * ld-aarch64/ifunc-14b.d: Likewise. ++ * ld-aarch64/ifunc-14b.s: Likewise. ++ * ld-aarch64/ifunc-14c.d: Likewise. ++ * ld-aarch64/ifunc-14c.s: Likewise. ++ * ld-aarch64/ifunc-14d.d: Likewise. ++ * ld-aarch64/ifunc-14e.d: Likewise. ++ * ld-aarch64/ifunc-14f.d: Likewise. ++ * ld-aarch64/ifunc-15.d: Likewise. ++ * ld-aarch64/ifunc-15.s: Likewise. ++ * ld-aarch64/ifunc-16.d: Likewise. ++ * ld-aarch64/ifunc-16.s: Likewise. ++ * ld-aarch64/ifunc-17a.d: Likewise. ++ * ld-aarch64/ifunc-17a.s: Likewise. ++ * ld-aarch64/ifunc-17b.d: Likewise. ++ * ld-aarch64/ifunc-17b.s: Likewise. ++ * ld-aarch64/ifunc-18a.d: Likewise. ++ * ld-aarch64/ifunc-18a.s: Likewise. ++ * ld-aarch64/ifunc-18b.d: Likewise. ++ * ld-aarch64/ifunc-18b.s: Likewise. ++ * ld-aarch64/ifunc-19a.d: Likewise. ++ * ld-aarch64/ifunc-19a.s: Likewise. ++ * ld-aarch64/ifunc-19b.d: Likewise. ++ * ld-aarch64/ifunc-19b.s: Likewise. ++ * ld-aarch64/ifunc-2-local.d: Likewise. ++ * ld-aarch64/ifunc-2-local.s: Likewise. ++ * ld-aarch64/ifunc-2.d: Likewise. ++ * ld-aarch64/ifunc-2.s: Likewise. ++ * ld-aarch64/ifunc-20.d: Likewise. ++ * ld-aarch64/ifunc-20.s: Likewise. ++ * ld-aarch64/ifunc-3.s: Likewise. ++ * ld-aarch64/ifunc-3a.d: Likewise. ++ * ld-aarch64/ifunc-3b.d: Likewise. ++ * ld-aarch64/ifunc-4.d: Likewise. ++ * ld-aarch64/ifunc-4.s: Likewise. ++ * ld-aarch64/ifunc-4a.d: Likewise. ++ * ld-aarch64/ifunc-5-local.s: Likewise. ++ * ld-aarch64/ifunc-5.s: Likewise. ++ * ld-aarch64/ifunc-5a-local.d: Likewise. ++ * ld-aarch64/ifunc-5a.d: Likewise. ++ * ld-aarch64/ifunc-5b-local.d: Likewise. ++ * ld-aarch64/ifunc-5b.d: Likewise. ++ * ld-aarch64/ifunc-5r-local.d: Likewise. ++ * ld-aarch64/ifunc-6.s: Likewise. ++ * ld-aarch64/ifunc-6a.d: Likewise. ++ * ld-aarch64/ifunc-6b.d: Likewise. ++ * ld-aarch64/ifunc-7.s: Likewise. ++ * ld-aarch64/ifunc-7a.d: Likewise. ++ * ld-aarch64/ifunc-7b.d: Likewise. ++ * ld-aarch64/ifunc-7c.d: Likewise. ++ * ld-aarch64/ifunc-8.d: Likewise. ++ * ld-aarch64/ifunc-8a.s: Likewise. ++ * ld-aarch64/ifunc-8b.s: Likewise. ++ * ld-aarch64/ifunc-9.d: Likewise. ++ * ld-aarch64/ifunc-9.s: Likewise. ++ ++2013-06-17 Will Newton ++ ++ * ld-aarch64/ifunc-1-local.d: Enable test on aarch64_be. ++ * ld-aarch64/ifunc-1.d: Likewise. ++ * ld-aarch64/ifunc-10.d: Likewise. ++ * ld-aarch64/ifunc-11.d: Likewise. ++ * ld-aarch64/ifunc-12.d: Likewise. ++ * ld-aarch64/ifunc-13.d: Likewise. ++ * ld-aarch64/ifunc-14a.d: Likewise. ++ * ld-aarch64/ifunc-14b.d: Likewise. ++ * ld-aarch64/ifunc-14c.d: Likewise. ++ * ld-aarch64/ifunc-14d.d: Likewise. ++ * ld-aarch64/ifunc-14e.d: Likewise. ++ * ld-aarch64/ifunc-14f.d: Likewise. ++ * ld-aarch64/ifunc-15.d: Likewise. ++ * ld-aarch64/ifunc-16.d: Likewise. ++ * ld-aarch64/ifunc-17a.d: Likewise. ++ * ld-aarch64/ifunc-17b.d: Likewise. ++ * ld-aarch64/ifunc-18a.d: Likewise. ++ * ld-aarch64/ifunc-18b.d: Likewise. ++ * ld-aarch64/ifunc-19a.d: Likewise. ++ * ld-aarch64/ifunc-19b.d: Likewise. ++ * ld-aarch64/ifunc-2-local.d: Likewise. ++ * ld-aarch64/ifunc-2.d: Likewise. ++ * ld-aarch64/ifunc-20.d: Likewise. ++ * ld-aarch64/ifunc-3a.d: Likewise. ++ * ld-aarch64/ifunc-3b.d: Likewise. ++ * ld-aarch64/ifunc-4.d: Likewise. ++ * ld-aarch64/ifunc-4a.d: Likewise. ++ * ld-aarch64/ifunc-5a-local.d: Likewise. ++ * ld-aarch64/ifunc-5a.d: Likewise. ++ * ld-aarch64/ifunc-5b-local.d: Likewise. ++ * ld-aarch64/ifunc-5b.d: Likewise. ++ * ld-aarch64/ifunc-5r-local.d: Likewise. ++ * ld-aarch64/ifunc-6a.d: Likewise. ++ * ld-aarch64/ifunc-6b.d: Likewise. ++ * ld-aarch64/ifunc-7a.d: Likewise. ++ * ld-aarch64/ifunc-7b.d: Likewise. ++ * ld-aarch64/ifunc-8.d: Likewise. ++ * ld-aarch64/ifunc-9.d: Likewise. ++ * ld-ifunc/ifunc.exp: Likewise. ++ ++2013-06-14 Yufeng Zhang ++ ++ * ld-aarch64/aarch64-elf.exp: Add 'ifunc-7c'. ++ * ld-aarch64/ifunc-7c.d: New test. ++ ++2013-06-14 Yufeng Zhang ++ ++ * ld-aarch64/ifunc-1-local.d: Replace hard-coded immediate offset ++ with regexp. ++ * ld-aarch64/ifunc-1.d: Likewise. ++ * ld-aarch64/ifunc-2-local.d: Likewise. ++ * ld-aarch64/ifunc-2.d: Likewise. ++ * ld-aarch64/ifunc-3a.d: Likewise. ++ * ld-aarch64/ifunc-2-local.s: Change not to declare __GI_foo and foo ++ global. ++ ++2013-06-13 Terry Guo ++ ++ PR ld/15302 ++ * ld-arm/branch-lks-sym.ld: New script. ++ * ld-arm/thumb-b-lks-sym.s: New test. ++ * ld-arm/thumb-b-lks-sym.d: Expected disassembly. ++ * ld-arm/thumb-bl-lks-sym.s: New test. ++ * ld-arm/thumb-bl-lks-sym.d: Expected disassembly. ++ * ld-arm/arm-elf.exp: Run the new tests. ++ ++2013-06-07 Will Newton ++ ++ * ld-ifunc/ifunc.exp: Enable ifunc tests for AArch64. ++ * ld-aarch64/aarch64-elf.exp: Add ifunc tests. ++ * ld-aarch64/ifunc-1-local.d: New file. ++ * ld-aarch64/ifunc-1-local.s: Likewise. ++ * ld-aarch64/ifunc-1.d: Likewise. ++ * ld-aarch64/ifunc-1.s: Likewise. ++ * ld-aarch64/ifunc-10.d: Likewise. ++ * ld-aarch64/ifunc-10.s: Likewise. ++ * ld-aarch64/ifunc-11.d: Likewise. ++ * ld-aarch64/ifunc-11.s: Likewise. ++ * ld-aarch64/ifunc-12.d: Likewise. ++ * ld-aarch64/ifunc-12.s: Likewise. ++ * ld-aarch64/ifunc-13.d: Likewise. ++ * ld-aarch64/ifunc-13a.s: Likewise. ++ * ld-aarch64/ifunc-13b.s: Likewise. ++ * ld-aarch64/ifunc-14a.d: Likewise. ++ * ld-aarch64/ifunc-14a.s: Likewise. ++ * ld-aarch64/ifunc-14b.d: Likewise. ++ * ld-aarch64/ifunc-14b.s: Likewise. ++ * ld-aarch64/ifunc-14c.d: Likewise. ++ * ld-aarch64/ifunc-14c.s: Likewise. ++ * ld-aarch64/ifunc-14d.d: Likewise. ++ * ld-aarch64/ifunc-14e.d: Likewise. ++ * ld-aarch64/ifunc-14f.d: Likewise. ++ * ld-aarch64/ifunc-15.d: Likewise. ++ * ld-aarch64/ifunc-15.s: Likewise. ++ * ld-aarch64/ifunc-16.d: Likewise. ++ * ld-aarch64/ifunc-16.s: Likewise. ++ * ld-aarch64/ifunc-17a.d: Likewise. ++ * ld-aarch64/ifunc-17a.s: Likewise. ++ * ld-aarch64/ifunc-17b.d: Likewise. ++ * ld-aarch64/ifunc-17b.s: Likewise. ++ * ld-aarch64/ifunc-18a.d: Likewise. ++ * ld-aarch64/ifunc-18a.s: Likewise. ++ * ld-aarch64/ifunc-18b.d: Likewise. ++ * ld-aarch64/ifunc-18b.s: Likewise. ++ * ld-aarch64/ifunc-19a.d: Likewise. ++ * ld-aarch64/ifunc-19a.s: Likewise. ++ * ld-aarch64/ifunc-19b.d: Likewise. ++ * ld-aarch64/ifunc-19b.s: Likewise. ++ * ld-aarch64/ifunc-2-local.d: Likewise. ++ * ld-aarch64/ifunc-2-local.s: Likewise. ++ * ld-aarch64/ifunc-2.d: Likewise. ++ * ld-aarch64/ifunc-2.s: Likewise. ++ * ld-aarch64/ifunc-20.d: Likewise. ++ * ld-aarch64/ifunc-20.s: Likewise. ++ * ld-aarch64/ifunc-3.s: Likewise. ++ * ld-aarch64/ifunc-3a.d: Likewise. ++ * ld-aarch64/ifunc-3b.d: Likewise. ++ * ld-aarch64/ifunc-4.d: Likewise. ++ * ld-aarch64/ifunc-4.s: Likewise. ++ * ld-aarch64/ifunc-4a.d: Likewise. ++ * ld-aarch64/ifunc-5-local.s: Likewise. ++ * ld-aarch64/ifunc-5.s: Likewise. ++ * ld-aarch64/ifunc-5a-local.d: Likewise. ++ * ld-aarch64/ifunc-5a.d: Likewise. ++ * ld-aarch64/ifunc-5b-local.d: Likewise. ++ * ld-aarch64/ifunc-5b.d: Likewise. ++ * ld-aarch64/ifunc-5r-local.d: Likewise. ++ * ld-aarch64/ifunc-6.s: Likewise. ++ * ld-aarch64/ifunc-6a.d: Likewise. ++ * ld-aarch64/ifunc-6b.d: Likewise. ++ * ld-aarch64/ifunc-7.s: Likewise. ++ * ld-aarch64/ifunc-7a.d: Likewise. ++ * ld-aarch64/ifunc-7b.d: Likewise. ++ * ld-aarch64/ifunc-8.d: Likewise. ++ * ld-aarch64/ifunc-8a.s: Likewise. ++ * ld-aarch64/ifunc-8b.s: Likewise. ++ * ld-aarch64/ifunc-9.d: Likewise. ++ * ld-aarch64/ifunc-9.s: Likewise. ++ ++2013-06-04 Roland McGrath ++ ++ * ld-size/size.exp: For *-*-nacl* targets, use options_regsub(ld) ++ to massage -m arguments into _nacl variants. ++ * ld/testsuite/ld-size/size32-1-i386.d: Loosen regexps so they ++ don't care what the exact addresses are. ++ * ld/testsuite/ld-size/size32-1-x32.d: Likewise. ++ * ld/testsuite/ld-size/size32-1-x86-64.d: Likewise. ++ * ld/testsuite/ld-size/size32-2-i386.d: Likewise. ++ * ld/testsuite/ld-size/size32-2-x32.d: Likewise. ++ * ld/testsuite/ld-size/size32-2-x86-64.d: Likewise. ++ * ld/testsuite/ld-size/size64-1-x32.d: Likewise. ++ * ld/testsuite/ld-size/size64-1-x86-64.d: Likewise. ++ * ld/testsuite/ld-size/size64-2-x32.d: Likewise. ++ * ld/testsuite/ld-size/size64-2-x86-64.d: Likewise. ++ ++2013-06-04 H.J. Lu ++ ++ * ld-i386/tlsbindesc-nacl.rd: Updated for text/data/bss section ++ alignment change. ++ * ld-x86-64/split-by-file-nacl.rd: Likewise. ++ ++2013-05-31 H.J. Lu ++ ++ * ld-i386/pr12718.d: Updated for text/data/bss section alignment ++ change. ++ * ld-i386/tlsbindesc.dd: Likewise. ++ * ld-i386/tlsbindesc.rd: Likewise. ++ * ld-i386/tlsnopic.dd: Likewise. ++ * ld-i386/tlspic.dd: Likewise. ++ * ld-x86-64/ilp32-4.d: Likewise. ++ * ld-x86-64/pr12718.d: Likewise. ++ * ld-x86-64/split-by-file.rd: Likewise. ++ * ld-x86-64/tlsbin.dd: Likewise. ++ * ld-x86-64/tlsbin.rd: Likewise. ++ * ld-x86-64/tlsbindesc.dd: Likewise. ++ * ld-x86-64/tlsbindesc.rd: Likewise. ++ * ld-x86-64/tlsdesc.dd: Likewise. ++ * ld-x86-64/tlsdesc.rd: Likewise. ++ * ld-x86-64/tlspic.dd: Likewise. ++ * ld-x86-64/tlspic.rd: Likewise. ++ ++2013-05-29 Maciej W. Rozycki ++ ++ * ld-mips-elf/jalr3.dd: New test. ++ * ld-mips-elf/jalr3.ld: New test linker script. ++ * ld-mips-elf/mips-elf.exp: Run the new test. ++ ++2013-05-21 Alan Modra ++ ++ PR ld/12982 ++ * ld-plugin/pr12982.d: Fail if RWE GNU_STACK present. ++ ++2013-05-21 Alan Modra ++ ++ * ld-powerpc/export-class.exp (supports_ppc64): Delete. ++ (powerpc_export_class_test): Add "endian" param. ++ (abis): Add little-endian targets and test. ++ * ld-powerpc/powerpc-64-export-class.xd: Update for little-endian. ++ ++2013-05-10 Joel Brobecker ++ ++ * ld-powerpc/aix-core-sec-1.hd, ld-powerpc/aix-core-sec-2.hd, ++ ld-powerpc/aix-core-sec-3.hd: Adjust expected section flags ++ for section .loader. ++ ++2013-05-03 Maciej W. Rozycki ++ ++ PR ld/15365 ++ * ld-elf/ehdr_start.d: Expect __ehdr_start to be STB_LOCAL. ++ * ld-mips-elf/ehdr_start-1.nd: New test. ++ * ld-mips-elf/ehdr_start-2.nd: New test. ++ * ld-mips-elf/ehdr_start-1.ld: New test linker script. ++ * ld-mips-elf/ehdr_start-2.ld: New test linker script. ++ * ld-mips-elf/ehdr_start-new.s: New test source. ++ * ld-mips-elf/ehdr_start-o32.s: New test source. ++ * ld-mips-elf/mips-elf.exp: Run the new tests. ++ ++2013-05-03 Maciej W. Rozycki ++ ++ * ld-elf/provide-hidden-s.nd: New test. ++ * ld-elf/provide-hidden-abs.nd: New test. ++ * ld-elf/provide-hidden-def.nd: New test. ++ * ld-elf/provide-hidden-dyn.nd: New test. ++ * ld-elf/provide-hidden-sec.nd: New test. ++ * ld-elf/provide-hidden-dynabs.nd: New test. ++ * ld-elf/provide-hidden-dynsec.nd: New test. ++ * ld-elf/provide-hidden-s.ld: New test linker script. ++ * ld-elf/provide-hidden-1.ld: New test linker script. ++ * ld-elf/provide-hidden-2.ld: New test linker script. ++ * ld-elf/provide-hidden-1.s: New test source. ++ * ld-elf/provide-hidden-2.s: New test source. ++ * ld-elf/provide-hidden-3.s: New test source. ++ * ld-elf/provide-hidden-4.s: New test source. ++ * ld-elf/provide-hidden.exp: New test script. ++ ++2013-05-02 Nick Clifton ++ ++ * ld-elf/flags1.d: Expect this test to pass on the MSP430. ++ * ld-elf/init-fini-arrays.d: Expect this test to fail on the ++ MSP430. ++ * ld-elf/merge.d: Expect this test to pass on the MSP430. ++ * ld-elf/sec64k.exp: Skip these tests for the MSP430. ++ * ld-gc/pr13683.d: Expect this test to fail on the MSP430. ++ * ld-srec/srec.exp: Expect these tests to fail on the MSP430. ++ * ld-undefined/undefined.exp: Expect the UNDEFINED LINE test to ++ fail on the MSP430. ++ ++2013-05-01 Maciej W. Rozycki ++ ++ * lib/ld-lib.exp (check_shared_lib_support): Also exclude ++ mips*-*-elf. ++ ++2013-04-30 Hans-Peter Nilsson ++ ++ * lib/ld-lib.exp (check_shared_lib_support): Match cris*-*-elf as ++ a negative pattern instead of cris*-*-*. ++ ++2013-04-30 Will Newton ++ ++ * ld-arm/arm-elf.exp: Use linker script for IFUNC test 17. ++ * ld-arm/ifunc-17.dd: Update offsets for linker script. ++ * ld-arm/ifunc-17.gd: Likewise. ++ * ld-arm/ifunc-17.rd: Likewise. ++ ++2013-04-29 Will Newton ++ ++ * ld-arm/arm-elf.exp: Add IFUNC test 17. ++ * ld-arm/ifunc-17.dd: New file. ++ * ld-arm/ifunc-17.gd: Likewise. ++ * ld-arm/ifunc-17.rd: Likewise. ++ * ld-arm/ifunc-17.s: Likweise. ++ * ld-arm/ifunc-1.rd: Reorder relocs to match linker output. ++ * ld-arm/ifunc-2.rd: Likewise. ++ * ld-arm/ifunc-5.rd: Likewise. ++ * ld-arm/ifunc-6.rd: Likewise. ++ ++2013-04-29 Will Newton ++ ++ * ld-plugin/lto.exp: Disable ld/12942 test for gcc < 4.7.0. ++ ++2013-04-22 Alan Modra ++ ++ * ld-powerpc/tlsexe.d: Adjust for section id changes. ++ * ld-powerpc/tlsexe.r: Likewise. ++ * ld-powerpc/tlsexetoc.d: Likewise. ++ * ld-powerpc/tlsexetoc.r: Likewise. ++ * ld-powerpc/tlsso.d: Likewise. ++ * ld-powerpc/tlsso.r: Likewise. ++ * ld-powerpc/tlstocso.d: Likewise. ++ * ld-powerpc/tlstocso.r: Likewise. ++ ++2013-04-15 H.J. Lu ++ ++ PR ld/15371 ++ * ld-ifunc/ifunc-20-i386.d: New file. ++ * ld-ifunc/ifunc-20-x86-64.d: Likewise. ++ * ld-ifunc/ifunc-20.s: Likewise. ++ ++2013-04-10 Venkataramanan Kumar ++ ++ * ld-aarch64/gc-plt1.s: New file. ++ * ld-aarch64/gc-plt2.s: Likewise. ++ * ld-aarch64/gc-plt-hidden.s: Likewise. ++ * ld-aarch64/gc-plt-main.s: Likewise. ++ * ld-aarch64/gc-relocs-257.s: Likewise. ++ * ld-aarch64/gc-plt-relocs.d: Update expected objdump. ++ * ld-aarch64/gc-relocs-257.d: Likewise. ++ * ld-aarch64/gc-relocs-257-dyn.d: Likewise. ++ * ld-aarch64/aarch64-elf.exp: Add test. ++ ++2013-04-08 Ramana Radhakrishnan ++ ++ * ld-aarch64/gc-tls-relocs.d: Handle big endian format. ++ * ld-aarch64/gc-got-relocs.d: Likewise. ++ ++2013-04-04 Alan Modra ++ ++ * ld-elf/shared.exp: Update regexp on --no-add-needed and ++ --no-copy-dt-needed-entries tests. ++ ++2013-04-03 Alan Modra ++ ++ PR ld/15227 ++ * ld-plugin/lto.exp (PR ld/12942 (3)): Remove file name and ++ line number from regexp. ++ (PR ld/15146 (2)): Similarly. ++ * ld-plugin/pr12942a.cc (main): Use __builtin_abort. ++ ++2013-03-30 Alan Modra ++ ++ PR ld/15323 ++ * ld-plugin/lto.exp (pr15323a.c): Compile without -flto rather ++ than using -r to effectively strip out lto info. ++ ++2013-03-29 H.J. Lu ++ ++ PR ld/15323 ++ * ld-plugin/lto.exp (lto_link_tests): Add pr15323a-r.o. ++ (lto_run_tests): Add a test for PR ld/15323. ++ ++ * ld-plugin/pr15323.out: New file. ++ * ld-plugin/pr15323a.c: Likewise. ++ * ld-plugin/pr15323b.c: Likewise. ++ ++2013-03-22 Nick Clifton ++ ++ * ld-elf/init0.s: Add alloc attribute to .section directive. ++ * ld-elf/fini1.s: Likewise. ++ * ld-elf/fini2.s: Likewise. ++ * ld-elf/fini3.s: Likewise. ++ * ld-elf/finin.s: Likewise. ++ * ld-elf/init0.s: Likewise. ++ * ld-elf/init1.s: Likewise. ++ * ld-elf/init2.s: Likewise. ++ * ld-elf/init3.s: Likewise. ++ * ld-elf/initn.s: Likewise. ++ ++2013-02-02 Michael Schewe ++ ++ * ld-h8300/h8300.exp: Add new relax-7 test on ELF. ++ * ld-h8300/relax-2.s: Add other direction and .w/.l variants of ++ mov insns. ++ * ld-h8300/relax-2.d: Update expected disassembly. ++ * ld-h8300/relax-7a.s: New: tests for mov @(disp:32,ERx) -> mov ++ @(disp:16,ERx). ++ * ld-h8300/relax-7b.s: New: Likewise. ++ * ld-h8300/relax-7.d: New: expected disassembly. ++ ++2013-03-20 Venkataramanan Kumar ++ ++ * ld-elf/group8a.d (notarget): Remove aarch64*-*-*. ++ * ld-elf/group8b.d: Likewise. ++ * ld-elf/group9a.d: Likewise. ++ * ld-elf/group9b.d: Likewise. ++ * ld-elf/pr12851.d: Likewise. ++ * ld-elf/pr12975.d: Likewise. ++ * ld-elf/pr13177.d: Likewise. ++ * ld-elf/pr13195.d: Likewise. ++ ++2013-03-20 Will Newton ++ ++ * ld-elfvers/vers.exp (objdump_symstuff): Sort objdump output ++ based on the symbol name rather than address. ++ * ld-elfvers/vers1.sym: Reorder contents to match changes to vers.exp. ++ * ld-elfvers/vers15.sym: Likewise. ++ * ld-elfvers/vers18.sym: Likewise. ++ * ld-elfvers/vers21.sym: Likewise. ++ * ld-elfvers/vers9.sym: Likewise. ++ ++2013-03-20 Alan Modra ++ ++ * ld-elf/rel.c, ld-elf/relmain.c, ld-elf/relmain.out: New test. ++ * ld-elf/shared.exp: Build and run it. ++ ++2013-03-20 Alan Modra ++ Will Newton ++ ++ * ld-elf/pr14862.out: Expect no output. ++ ++2013-03-15 Will Newton ++ ++ * ld-arm/arm-elf.exp: Expand *-*eabi test to cover *-*eabi*. ++ * ld-arm/gc-hidden-1.d: Likewise. ++ * ld-elfvsb/elfvsb.exp: Likewise. ++ * ld-shared/shared.exp: Likewise. ++ ++2013-03-08 Venkataramanan Kumar ++ ++ * lib/ld-lib.exp (check_gc_sections_available): Remove aarch64 ++ from list of targets that don't support gc-section. ++ ++2013-03-05 Alan Modra ++ ++ * ld-scripts/rgn-at6.s, * ld-scripts/rgn-at6.t, * ld-scripts/rgn-at6.d, ++ * ld-scripts/rgn-at7.t, * ld-scripts/rgn-at7.d: New tests. ++ ++2013-02-28 Nathan Sidwell ++ ++ * ld-arm/tls-local-static.s: New test. ++ * ld-arm/tls-local-static.d: New. ++ * ld-arm/arm-elf.exp (tls-local-static): Add test. ++ ++2013-02-21 H.J. Lu ++ ++ PR ld/15167 ++ * ld-unique/unique.exp: Add a test for shared library with ++ reference. ++ ++2013-02-19 Maciej W. Rozycki ++ ++ * lib/ld-lib.exp (run_ld_link_tests): Add another argument, pass ++ its contents to ar_simple_create and ld_simple_link after ++ objfiles. ++ * ld-aarch64/aarch64-elf.exp: Adjust accordingly. ++ * ld-alpha/alpha.exp: Likewise. ++ * ld-arm/arm-elf.exp: Likewise. ++ * ld-arm/export-class.exp: Likewise. ++ * ld-elf/comm-data.exp: Likewise. ++ * ld-elf/eh-group.exp: Likewise. ++ * ld-elf/elf.exp: Likewise. ++ * ld-elf/export-class.exp: Likewise. ++ * ld-elfvers/vers.exp: Likewise. ++ * ld-frv/tls.exp: Likewise. ++ * ld-i386/export-class.exp: Likewise. ++ * ld-i386/i386.exp: Likewise. ++ * ld-ia64/ia64.exp: Likewise. ++ * ld-libs/libs.exp: Likewise. ++ * ld-m68k/m68k.exp: Likewise. ++ * ld-metag/metag.exp: Likewise. ++ * ld-mips-elf/comm-data.exp: Likewise. ++ * ld-mips-elf/export-class.exp: Likewise. ++ * ld-mips-elf/mips-elf.exp: Likewise. ++ * ld-mn10300/mn10300.exp: Likewise. ++ * ld-pe/pe-compile.exp: Likewise. ++ * ld-pe/pe.exp: Likewise. ++ * ld-plugin/plugin.exp: Likewise. ++ * ld-powerpc/aix52.exp: Likewise. ++ * ld-powerpc/export-class.exp: Likewise. ++ * ld-powerpc/powerpc.exp: Likewise. ++ * ld-s390/s390.exp: Likewise. ++ * ld-sh/sh-vxworks.exp: Likewise. ++ * ld-sh/sh64/sh64.exp: Likewise. ++ * ld-sparc/sparc.exp: Likewise. ++ * ld-tic6x/tic6x.exp: Likewise. ++ * ld-tilegx/tilegx.exp: Likewise. ++ * ld-tilepro/tilepro.exp: Likewise. ++ * ld-undefined/entry.exp: Likewise. ++ * ld-vax-elf/vax-elf.exp: Likewise. ++ * ld-x86-64/dwarfreloc.exp: Likewise. ++ * ld-x86-64/export-class.exp: Likewise. ++ * ld-x86-64/x86-64.exp: Likewise. ++ * ld-xc16x/xc16x.exp: Likewise. ++ * ld-xstormy16/xstormy16.exp: Likewise. ++ * ld-xtensa/xtensa.exp: Likewise. ++ ++2013-02-18 Maciej W. Rozycki ++ ++ * ld-mips-elf/jalx-2.ld: Include .rel.plt in output, give .plt a ++ mapping. ++ * ld-mips-elf/jalx-2.dd: Adjust disassembly accordingly. ++ ++2013-02-18 Alan Modra ++ ++ * ld-plugin/lto.exp (Build pr15146b.so) Add -Wl,--no-as-needed. ++ (PR ld/15146 (1), (2)): Likewise. ++ (LTO 7): Likewise. ++ ++2013-02-16 H.J. Lu ++ ++ PR ld/15146 ++ * ld-plugin/pr15146.d: New file. ++ * ld-plugin/pr15146a.c: Likewise. ++ * ld-plugin/pr15146b.c: Likewise. ++ * ld-plugin/pr15146c.c: Likewise. ++ * ld-plugin/pr15146d.c: Likewise. ++ ++ * ld-plugin/lto.exp: Add tests for PR ld/15146. ++ ++2013-02-15 Markos Chandras ++ ++ * ld-metag/pcrel.d: Fix the expected disassembler ++ output to be in little endian format ++ * ld-metag/shared.d: likewise ++ * ld-metag/stub.d: likewise ++ * ld-metag/stub_pic_app.d: likewise ++ * ld-metag/stub_pic_shared.d: likewise ++ * ld-metag/stub_shared.d: likewise ++ ++2013-02-13 Richard Sandiford ++ ++ * ld-mips-elf/mips16-pic-2.dd, ++ ld-mips-elf/mips16-pic-2.gd: Remove 3 unused local GOT entries. ++ * ld-mips-elf/got-page-4a.s, ld-mips-elf/got-page-4b.s, ++ ld-mips-elf/got-page-4a.d, ld-mips-elf/got-page-4a.got, ++ ld-mips-elf/got-page-4b.d, ld-mips-elf/got-page-4b.got, ++ ld-mips-elf/got-page-5.s, ld-mips-elf/got-page-5.d, ++ ld-mips-elf/got-page-5.got, ld-mips-elf/got-page-6.s, ++ ld-mips-elf/got-page-6.d, ld-mips-elf/got-page-6.got, ++ ld-mips-elf/got-page-7a.s, ld-mips-elf/got-page-7b.s, ++ ld-mips-elf/got-page-7c.s, ld-mips-elf/got-page-7d.s, ++ ld-mips-elf/got-page-7e.s, ld-mips-elf/got-page-7.d, ++ ld-mips-elf/got-page-7.got: New tests. ++ * ld-mips-elf/mips-elf.exp: Run them. ++ ++2013-02-11 Richard Sandiford ++ ++ * ld-mips-elf/tlsdyn-o32-1.d, ld-mips-elf/tlsdyn-o32-1.got, ++ ld-mips-elf/tlsdyn-o32-2.d, ld-mips-elf/tlsdyn-o32-2.got, ++ ld-mips-elf/tlsdyn-o32-3.d, ld-mips-elf/tlsdyn-o32-3.got, ++ ld-mips-elf/tls-hidden3.d, ld-mips-elf/tls-hidden3.got: Update ++ for new hash table order. ++ ++2013-02-11 Richard Sandiford ++ ++ * ld-mips-elf/tls-hidden4.got, ld-mips-elf/tls-multi-got-1.d, ++ ld-mips-elf/tls-multi-got-1.got: Update for changes in the order ++ that symbols are added to per-bfd GOTs. ++ ++2013-02-11 Richard Sandiford ++ ++ * ld-mips-elf/tls-hidden3.d, ld-mips-elf/tls-hidden3.got, ++ ld-mips-elf/tls-multi-got-1.got, ld-mips-elf/tlsbin-o32.d, ++ ld-mips-elf/tlsbin-o32.got, ld-mips-elf/tlsdyn-o32-1.d, ++ ld-mips-elf/tlsdyn-o32-1.got, ld-mips-elf/tlsdyn-o32-2.d, ++ ld-mips-elf/tlsdyn-o32-2.got, ld-mips-elf/tlsdyn-o32-3.d, ++ ld-mips-elf/tlsdyn-o32-3.got, ld-mips-elf/tlsdyn-o32.d, ++ ld-mips-elf/tlsdyn-o32.got, ld-mips-elf/tlslib-o32.d, ++ ld-mips-elf/tlslib-o32.got, ld-mips-elf/tlslib-o32-hidden.got, ++ ld-mips-elf/tlslib-o32-ver.got: Adjust GOT layout for new ++ got_entry hash function. ++ ++2013-02-11 Richard Sandiford ++ ++ * ld-mips-elf/tlsdyn-o32-2.got, ld-mips-elf/tlsdyn-o32-3.got: Remove ++ unused GOT entries. ++ ++2013-02-07 H.J. Lu ++ ++ PR ld/15107 ++ * ld-unique/unique_empty.s: Add reference to "b". ++ ++2013-02-06 H.J. Lu ++ ++ * ld-size/size-10.rd: Updated. ++ * ld-size/size-8.rd: Likewise. ++ * ld-size/size32-2-i386.d: Likewise. ++ * ld-size/size32-2-x32.d: Likewise. ++ * ld-size/size32-2-x86-64.d: Likewise. ++ * ld-size/size64-2-x32.d: Likewise. ++ * ld-size/size64-2-x86-64.d: Likewise. ++ ++ * ld-size/size.exp (run_time_tests): Pass --hash-styl=gnu to ++ linker for size-8 test. ++ ++2013-02-06 Sandra Loosemore ++ Andrew Jenner ++ ++ Based on patches from Altera Corporation. ++ ++ * ld-nios2/emit-relocs-1a.s: New. ++ * ld-nios2/emit-relocs-1b.s: New. ++ * ld-nios2/emit-relocs-1.d: New. ++ * ld-nios2/emit-relocs-1.ld: New. ++ * ld-nios2/gprel.d: New. ++ * ld-nios2/gprel.s: New. ++ * ld-nios2/hilo16.d: New. ++ * ld-nios2/hilo16.s: New. ++ * ld-nios2/hilo16_symbol.s: New. ++ * ld-nios2/imm5.d: New. ++ * ld-nios2/imm5.s: New. ++ * ld-nios2/imm5_symbol.s: New. ++ * ld-nios2/nios2.exp: New. ++ * ld-nios2/pcrel16.d: New. ++ * ld-nios2/pcrel16_label.s: New. ++ * ld-nios2/pcrel16.s: New. ++ * ld-nios2/relax_callr.d: New. ++ * ld-nios2/relax_callr.ld: New. ++ * ld-nios2/relax_callr.s: New. ++ * ld-nios2/relax_cjmp.d: New. ++ * ld-nios2/relax_cjmp.s: New. ++ * ld-nios2/relax_jmp.ld: New. ++ * ld-nios2/relax_section.d: New. ++ * ld-nios2/relax_section.s: New. ++ * ld-nios2/relax_ujmp.d: New. ++ * ld-nios2/relax_ujmp.s: New. ++ * ld-nios2/reloc.d: New. ++ * ld-nios2/reloc.s: New. ++ * ld-nios2/reloc_symbol.s: New. ++ * ld-nios2/s16.d: New. ++ * ld-nios2/s16.s: New. ++ * ld-nios2/s16_symbol.s: New. ++ * ld-nios2/u16.d: New. ++ * ld-nios2/u16.s: New. ++ * ld-nios2/u16_symbol.s: New. ++ * ld-elf/indirect.exp: Skip on targets that don't support ++ -shared -fPIC. ++ * ld-elfcomm/elfcomm.exp: Build with -G0 for nios2. ++ * ld-plugin/lto.exp: Skip shared library tests on targets that ++ don't support them. Skip execution tests on non-native targets. ++ ++2013-02-06 H.J. Lu ++ ++ * ld-elf/now-1.d: New file. ++ * ld-elf/now-2.d: Likewise. ++ * ld-elf/now-3.d: Likewise. ++ * ld-elf/now-4.d: Likewise. ++ * ld-elf/rpath-1.d: Likewise. ++ * ld-elf/rpath-2.d: Likewise. ++ * ld-elf/runpath-1.d: Likewise. ++ * ld-elf/runpath-2.d: Likewise. ++ ++2013-02-06 Alan Modra ++ ++ PR ld/15096 ++ * ld-elf/new-dtags-1.d: Delete. ++ * ld-elf/new-dtags-2.d: Likewise. ++ * ld-elf/new-dtags-3.d: Likewise. ++ * ld-elf/new-dtags-4.d: Likewise. ++ * ld-elf/new-dtags-5.d: Likewise. ++ * ld-elf/new-dtags-6.d: Likewise. ++ * ld-elf/new-dtags-7.d: Likewise. ++ * ld-elf/new-dtags-8.d: Likewise. ++ ++2013-02-04 H.J. Lu ++ ++ PR ld/15096 ++ * ld-elf/new-dtags-1.d: New test. ++ * ld-elf/new-dtags-2.d: Likewise. ++ * ld-elf/new-dtags-3.d: Likewise. ++ * ld-elf/new-dtags-4.d: Likewise. ++ * ld-elf/new-dtags-5.d: Likewise. ++ * ld-elf/new-dtags-6.d: Likewise. ++ * ld-elf/new-dtags-7.d: Likewise. ++ * ld-elf/new-dtags-8.d: Likewise. ++ ++2013-01-31 Alan Modra ++ ++ * ld-powerpc/tlsexe.d: Update for changed stub names. ++ * ld-powerpc/tlsexe.r: Likewise. ++ * ld-powerpc/tlsexetoc.d: Likewise. ++ * ld-powerpc/tlsexetoc.r: Likewise. ++ * ld-powerpc/tlsso.d: Likewise. ++ * ld-powerpc/tlsso.r: Likewise. ++ * ld-powerpc/tlstocso.d: Likewise. ++ * ld-powerpc/tlstocso.r: Likewise. ++ ++2013-01-31 Hans-Peter Nilsson ++ ++ * ld-cris/libdso-13.d: Adjust for --enable-new-dtags now ++ default for *-*-linux-* by passing explicitly for all targets. ++ ++2013-01-21 Alan Modra ++ ++ * ld-size/size.exp (build_tests ): Pass ++ --no-as-needed in cflags. ++ ++2013-01-19 H.J. Lu ++ ++ * config/default.exp (get_target_emul): Also set HOSTING_SCRT0. ++ ++ * lib/ld-lib.exp (default_ld_link): Use HOSTING_SCRT0 for -pie. ++ ++2013-01-18 H.J. Lu ++ ++ * ld-size/size-10.rd: Updated. ++ * ld-size/size-8.rd: Likewise. ++ * ld-size/size32-2-i386.d: Likewise. ++ * ld-size/size32-2-x32.d: Likewise. ++ * ld-size/size32-2-x86-64.d: Likewise. ++ * ld-size/size64-2-x32.d: Likewise. ++ * ld-size/size64-2-x86-64.d: Likewise. ++ ++2013-01-17 H.J. Lu ++ ++ * ld-size/size-7.out: New file. ++ * ld-size/size-8.out: Likewise. ++ * ld-size/size-9.out: Likewise. ++ * ld-size/size-9.rd: Likewise. ++ * ld-size/size-9a.c: Likewise. ++ * ld-size/size-9b.c: Likewise. ++ * ld-size/size-10.out: Likewise. ++ * ld-size/size-10.rd: Likewise. ++ * ld-size/size-10a.c: Likewise. ++ * ld-size/size-10b.c: Likewise. ++ ++ * ld-size/size.exp (build_tests): Build libsize-9.so and ++ libsize-10.so. ++ Run-time size relocation tests if supported. ++ (run_time_tests): New. ++ ++2013-01-17 H.J. Lu ++ ++ * ld-size/size-1.c: New file. ++ * ld-size/size-1.out: Likewise. ++ * ld-size/size-1a.c: Likewise. ++ * ld-size/size-1b.c: Likewise. ++ * ld-size/size-2.c: Likewise. ++ * ld-size/size-2.out: Likewise. ++ * ld-size/size-2a.c: Likewise. ++ * ld-size/size-2b.c: Likewise. ++ ++ * ld-size/size.exp (build_tests): Build libsize-1.so and ++ libsize-2.so. ++ (run_tests): Run size-1 and size-2. ++ ++2013-01-17 H.J. Lu ++ ++ * ld-size/size32-3-i386.d: New file. ++ * ld-size/size32-3-x32.d: Likewise. ++ * ld-size/size32-3-x86-64.d: Likewise. ++ * ld-size/size32-3a.s: Likewise. ++ * ld-size/size32-3b.s: Likewise. ++ ++2013-01-16 H.J. Lu ++ ++ * ld-size/size.exp: New file. ++ * ld-size/size32-1-i386.d: Likewise. ++ * ld-size/size32-1-x32.d: Likewise. ++ * ld-size/size32-1-x86-64.d: Likewise. ++ * ld-size/size32-1.s: Likewise. ++ * ld-size/size32-2-i386.d: Likewise. ++ * ld-size/size32-2-x32.d: Likewise. ++ * ld-size/size32-2-x86-64.d: Likewise. ++ * ld-size/size32-2.s: Likewise. ++ * ld-size/size64-1-x32.d: Likewise. ++ * ld-size/size64-1-x86-64.d: Likewise. ++ * ld-size/size64-1.s: Likewise. ++ * ld-size/size64-2-x32.d: Likewise. ++ * ld-size/size64-2-x86-64.d: Likewise. ++ * ld-size/size64-2.s: Likewise. ++ * ld-size/size-3.c: Likewise. ++ * ld-size/size-3.out: Likewise. ++ * ld-size/size-3a.c: Likewise. ++ * ld-size/size-3b.c: Likewise. ++ * ld-size/size-3c.c: Likewise. ++ * ld-size/size-4.out: Likewise. ++ * ld-size/size-4a.c: Likewise. ++ * ld-size/size-4b.c: Likewise. ++ * ld-size/size-5.out: Likewise. ++ * ld-size/size-5a.c: Likewise. ++ * ld-size/size-5b.c: Likewise. ++ * ld-size/size-6.out: Likewise. ++ * ld-size/size-6a.c: Likewise. ++ * ld-size/size-6b.c: Likewise. ++ * ld-size/size-7.rd: Likewise. ++ * ld-size/size-7a.c: Likewise. ++ * ld-size/size-7b.c: Likewise. ++ * ld-size/size-8.rd: Likewise. ++ * ld-size/size-8a.c: Likewise. ++ * ld-size/size-8b.c: Likewise. ++ ++2013-01-16 Alan Modra ++ ++ * ld-plugin/lto.exp (lto-9.o, pr13229.o): Pass -finline. ++ ++2013-01-15 Alan Modra ++ ++ * ld-powerpc/tlsso.d: Adjust for plt-thread-safe stubs. ++ * ld-powerpc/tlsso.g: Likewise. ++ * ld-powerpc/tlsso.r: Likewise. ++ * ld-powerpc/tlstocso.d: Likewise. ++ * ld-powerpc/tlstocso.g: Likewise. ++ ++2013-01-15 Alan Modra ++ ++ * ld-plugin/lto-16a.d: Match powerpc64 function symbol type. ++ * ld-plugin/lto-16b.d: Likewise. ++ * ld-plugin/lto-17a.d: Likewise. ++ * ld-plugin/lto-17b-2.d: Likewise. ++ ++2013-01-14 Alan Modra ++ ++ * ld-elf/pr14926.d: Disable for d10v, msp, xstormy. ++ * ld-elf/sec-to-seg.exp: Choose correct variant output to suit ++ updated microblaze page size. ++ ++2013-01-10 Will Newton ++ ++ * ld-elf/merge.d: Mark Meta as xfail. ++ * ld-gc/start.d: Skip this test on Meta. ++ * ld-gc/personality.d: Skip this test on Meta. ++ * ld-metag/external.s: New file. ++ * ld-metag/metag.exp: New file. ++ * ld-metag/pcrel.d: New file. ++ * ld-metag/pcrel.s: New file. ++ * ld-metag/shared.d: New file. ++ * ld-metag/shared.r: New file. ++ * ld-metag/shared.s: New file. ++ * ld-metag/stub.d: New file. ++ * ld-metag/stub.s: New file. ++ * ld-metag/stub_pic_app.d: New file. ++ * ld-metag/stub_pic_app.r: New file. ++ * ld-metag/stub_pic_app.s: New file. ++ * ld-metag/stub_pic_shared.d: New file. ++ * ld-metag/stub_pic_shared.s: New file. ++ * ld-metag/stub_shared.d: New file. ++ * ld-metag/stub_shared.r: New file. ++ * ld-metag/stub_shared.s: New file. ++ ++2013-01-08 Thomas Schwinge ++ ++ * ld-i386/export-class.exp: Restore (and reword) comment about ++ excluded targets. ++ ++2013-01-04 Yufeng Zhang ++ ++ * ld-aarch64/emit-relocs-264.d: Append the '-Mno-aliases' option to ++ the objdump directive. ++ * ld-aarch64/emit-relocs-266.d: Ditto. ++ * ld-aarch64/emit-relocs-268.d: Ditto. ++ * ld-aarch64/emit-relocs-269.d: Ditto. ++ * ld-aarch64/emit-relocs-270.d: Ditto. ++ * ld-aarch64/emit-relocs-271.d: Ditto. ++ * ld-aarch64/emit-relocs-272.d: Ditto. ++ ++For older changes see ChangeLog-2012 ++ ++Copyright (C) 2013 Free Software Foundation, Inc. ++ ++Copying and distribution of this file, with or without modification, ++are permitted in any medium without royalty provided the copyright ++notice and this notice are preserved. ++ ++Local Variables: ++mode: change-log ++left-margin: 8 ++fill-column: 74 ++version-control: never ++End: diff --git a/ld/testsuite/ChangeLog-9303 b/ld/testsuite/ChangeLog-9303 new file mode 100644 index 0000000..4f441bf @@ -2729016,13 +2743668,12 @@ index 0000000..4f441bf +End: diff --git a/ld/testsuite/config/default.exp b/ld/testsuite/config/default.exp new file mode 100644 -index 0000000..1d3ce6a +index 0000000..8b776a6 --- /dev/null +++ b/ld/testsuite/config/default.exp @@ -0,0 +1,287 @@ +# Basic expect script for LD Regression Tests -+# Copyright 1993, 1994, 1995, 1997, 1998, 1999, 2001, 2003, 2005, 2007, 2009 -+# 2011, 2012 Free Software Foundation, Inc. ++# Copyright (C) 1993-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2729129,6 +2743780,11 @@ index 0000000..1d3ce6a + append gcc_gas_flag " -mabi=n32" +} + ++if { [istarget rx-*-*] } { ++ global ASFLAGS ++ set ASFLAGS "-muse-conventional-section-names" ++} ++ +# load the utility procedures +load_lib ld-lib.exp + @@ -2729260,10 +2743916,6 @@ index 0000000..1d3ce6a + set AS $as +} + -+if ![info exists GASP] then { -+ set GASP [findfile $base_dir/../gas/gasp-new $base_dir/../gas/gasp-new [transform gasp]] -+} -+ +if ![info exists ASFLAGS] then { + set ASFLAGS "" +} @@ -2729309,12 +2743961,12 @@ index 0000000..1d3ce6a +} diff --git a/ld/testsuite/ld-aarch64/aarch64-elf.exp b/ld/testsuite/ld-aarch64/aarch64-elf.exp new file mode 100644 -index 0000000..692bf34 +index 0000000..845ea20 --- /dev/null +++ b/ld/testsuite/ld-aarch64/aarch64-elf.exp -@@ -0,0 +1,159 @@ +@@ -0,0 +1,161 @@ +# Expect script for various AARCH64 ELF tests. -+# Copyright 2009-2013 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2729472,6 +2744124,8 @@ index 0000000..692bf34 +run_dump_test "ifunc-20" +run_dump_test "ifunc-21" +run_dump_test "ifunc-22" ++ ++run_dump_test "relasz" diff --git a/ld/testsuite/ld-aarch64/aarch64.ld b/ld/testsuite/ld-aarch64/aarch64.ld new file mode 100644 index 0000000..75ee3b5 @@ -2729604,7 +2744258,7 @@ index 0000000..c077ef2 + diff --git a/ld/testsuite/ld-aarch64/eh-frame.d b/ld/testsuite/ld-aarch64/eh-frame.d new file mode 100644 -index 0000000..f3daeb2 +index 0000000..15d5c5c --- /dev/null +++ b/ld/testsuite/ld-aarch64/eh-frame.d @@ -0,0 +1,86 @@ @@ -2729644,7 +2744298,7 @@ index 0000000..f3daeb2 + DW_CFA_nop + DW_CFA_nop + -+0+0048 0+0014 0+004c FDE cie=0+0000 pc=f+fffff80..f+fffffc0 ++0+0048 0+0014 0+004c FDE cie=0+0000 pc=0+8000..0+8040 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop @@ -2729685,7 +2744339,7 @@ index 0000000..f3daeb2 + DW_CFA_nop + DW_CFA_nop + -+0+00a8 0+0014 0+004c FDE cie=0+0060 pc=f+fffffc0..0+0000 ++0+00a8 0+0014 0+004c FDE cie=0+0060 pc=0+8040..0+8080 + DW_CFA_nop + DW_CFA_nop + DW_CFA_nop @@ -2733110,6 +2747764,45 @@ index 0000000..72f47a5 + .type bar, @function +bar: + ret +diff --git a/ld/testsuite/ld-aarch64/relasz.d b/ld/testsuite/ld-aarch64/relasz.d +new file mode 100644 +index 0000000..5cc5595 +--- /dev/null ++++ b/ld/testsuite/ld-aarch64/relasz.d +@@ -0,0 +1,18 @@ ++#source: relasz.s ++#ld: -shared -Taarch64.ld ++#readelf: -d ++# Check that the RELASZ section has the correct size even if we are ++# using a non-default linker script that merges .rela.dyn and .rela.plt ++# in the output. ++ ++Dynamic section at offset 0x[0-9a-f]+ contains 9 entries: ++ Tag Type Name/Value ++ 0x0000000000000004 \(HASH\) 0x[0-9a-f]+ ++ 0x0000000000000005 \(STRTAB\) 0x[0-9a-f]+ ++ 0x0000000000000006 \(SYMTAB\) 0x[0-9a-f]+ ++ 0x000000000000000a \(STRSZ\) [0-9]+ \(bytes\) ++ 0x000000000000000b \(SYMENT\) [0-9]+ \(bytes\) ++ 0x0000000000000007 \(RELA\) 0x[0-9a-f]+ ++ 0x0000000000000008 \(RELASZ\) 24 \(bytes\) ++ 0x0000000000000009 \(RELAENT\) 24 \(bytes\) ++ 0x0000000000000000 \(NULL\) 0x0 +diff --git a/ld/testsuite/ld-aarch64/relasz.s b/ld/testsuite/ld-aarch64/relasz.s +new file mode 100644 +index 0000000..8c7f891 +--- /dev/null ++++ b/ld/testsuite/ld-aarch64/relasz.s +@@ -0,0 +1,9 @@ ++ .text ++ .global func ++ .type func, %function ++func: ++ adrp x0, :got:foo ++ ldr x0, [x0, #:got_lo12:foo] ++ ldr w0, [x0] ++ ret ++ .size func, .-func diff --git a/ld/testsuite/ld-aarch64/relocs.ld b/ld/testsuite/ld-aarch64/relocs.ld new file mode 100644 index 0000000..f42176e @@ -2733451,7 +2748144,7 @@ index 0000000..634a55a + +10018: b9400000 ldr w0, \[x0\] diff --git a/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s b/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s new file mode 100644 -index 0000000..c20690c +index 0000000..38b3721 --- /dev/null +++ b/ld/testsuite/ld-aarch64/tls-relax-gdesc-ie.s @@ -0,0 +1,13 @@ @@ -2733461,7 +2748154,7 @@ index 0000000..c20690c + .word 2 + .text + adrp x0, :tlsdesc:var -+ ldr x1, [x0, #:tlsdesc_lo12:var] ++ ldr x17, [x0, #:tlsdesc_lo12:var] + add x0, x0, :tlsdesc_lo12:var + .tlsdesccall var + blr x1 @@ -2733772,12 +2748465,12 @@ index 0000000..6c48ba9 + .balign 4096 diff --git a/ld/testsuite/ld-alpha/alpha.exp b/ld/testsuite/ld-alpha/alpha.exp new file mode 100644 -index 0000000..c04a798 +index 0000000..6c014eb --- /dev/null +++ b/ld/testsuite/ld-alpha/alpha.exp @@ -0,0 +1,70 @@ +# Expect script for ld-alpha tests -+# Copyright (C) 2003, 2005, 2007 Free Software Foundation ++# Copyright (C) 2003-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2734969,10 +2749662,10 @@ index 0000000..1148b20 + .eabi_attribute 4, "arch_v6t2" diff --git a/ld/testsuite/ld-arm/arm-app-abs32.d b/ld/testsuite/ld-arm/arm-app-abs32.d new file mode 100644 -index 0000000..e6c4632 +index 0000000..2f56c08 --- /dev/null +++ b/ld/testsuite/ld-arm/arm-app-abs32.d -@@ -0,0 +1,29 @@ +@@ -0,0 +1,30 @@ + +tmpdir/arm-app-abs32: file format elf32-(little|big)arm.* +architecture: armv4t, flags 0x00000112: @@ -2734981,12 +2749674,13 @@ index 0000000..e6c4632 + +Disassembly of section .plt: + -+.* <.plt>: ++.* : + +.*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) -+ +.*: e59fe004 ldr lr, \[pc, #4\] ; .* <_start-0x10> ++ +.*: e59fe004 ldr lr, \[pc, #4\] ; .* + +.*: e08fe00e add lr, pc, lr + +.*: e5bef008 ldr pc, \[lr, #8\]! + +.*: .* .* ++.* : + +.*: e28fc6.* add ip, pc, #.* + +.*: e28cca.* add ip, ip, #.* ; .* + +.*: e5bcf.* ldr pc, \[ip, #.*\]!.* @@ -2735057,10 +2749751,10 @@ index 0000000..55ced97 + bx lr diff --git a/ld/testsuite/ld-arm/arm-app.d b/ld/testsuite/ld-arm/arm-app.d new file mode 100644 -index 0000000..88169af +index 0000000..9788db0 --- /dev/null +++ b/ld/testsuite/ld-arm/arm-app.d -@@ -0,0 +1,35 @@ +@@ -0,0 +1,36 @@ + +tmpdir/arm-app: file format elf32-(little|big)arm +architecture: armv4t, flags 0x00000112: @@ -2735069,12 +2749763,13 @@ index 0000000..88169af + +Disassembly of section .plt: + -+.* <.plt>: ++.* : + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) -+ .*: e59fe004 ldr lr, \[pc, #4\] ; .* <_start-0x10> ++ .*: e59fe004 ldr lr, \[pc, #4\] ; .* + .*: e08fe00e add lr, pc, lr + .*: e5bef008 ldr pc, \[lr, #8\]! + .*: .* ++.* : + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* @@ -2735090,7 +2749785,7 @@ index 0000000..88169af +.* : + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} -+ .*: ebfffff4 bl .* <_start-0xc> ++ .*: ebfffff4 bl .* + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + @@ -2735316,7 +2750011,7 @@ index 0000000..02aa379 + blx _start diff --git a/ld/testsuite/ld-arm/arm-dyn.ld b/ld/testsuite/ld-arm/arm-dyn.ld new file mode 100644 -index 0000000..bef9a18 +index 0000000..71cb4c9 --- /dev/null +++ b/ld/testsuite/ld-arm/arm-dyn.ld @@ -0,0 +1,195 @@ @@ -2735471,7 +2750166,7 @@ index 0000000..bef9a18 + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ -+ . = ALIGN(32 / 8); ++ . = ALIGN(. != 0 ? 32 / 8 : 1); + } + . = ALIGN(32 / 8); + _end = .; @@ -2735517,12 +2750212,12 @@ index 0000000..bef9a18 + diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp new file mode 100644 -index 0000000..4c0f802 +index 0000000..c255587 --- /dev/null +++ b/ld/testsuite/ld-arm/arm-elf.exp -@@ -0,0 +1,840 @@ +@@ -0,0 +1,844 @@ +# Expect script for various ARM ELF tests. -+# Copyright 2002-2013 Free Software Foundation, Inc. ++# Copyright (C) 2002-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2735979,6 +2750674,10 @@ index 0000000..4c0f802 + {objdump {-s -j.data -j.got} ifunc-17.gd} + {readelf -r ifunc-17.rd}} + "ifunc-17"} ++ {"Long PLT entries in executables" "--long-plt -shared --section-start=.plt=0x1000 --section-start=.got=0xf0001100" "" ++ "" {long-plt-format.s} ++ {{objdump "-d -j .plt" long-plt-format.d}} ++ "long-plt-format"} +} + +run_ld_link_tests $armelftests_common @@ -2736438,10 +2751137,10 @@ index 0000000..fa5b135 + .word foo diff --git a/ld/testsuite/ld-arm/arm-lib-plt32.d b/ld/testsuite/ld-arm/arm-lib-plt32.d new file mode 100644 -index 0000000..279ea5a +index 0000000..e04adb8 --- /dev/null +++ b/ld/testsuite/ld-arm/arm-lib-plt32.d -@@ -0,0 +1,28 @@ +@@ -0,0 +1,29 @@ + +tmpdir/arm-lib-plt32.so: file format elf32-(little|big)arm +architecture: armv4t, flags 0x00000150: @@ -2736450,12 +2751149,13 @@ index 0000000..279ea5a + +Disassembly of section .plt: + -+.* <.plt>: ++.* : + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) -+ .*: e59fe004 ldr lr, \[pc, #4\] ; .* ++ .*: e59fe004 ldr lr, \[pc, #4\] ; .* + .*: e08fe00e add lr, pc, lr + .*: e5bef008 ldr pc, \[lr, #8\]! + .*: .* ++.* : + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* @@ -2736464,7 +2751164,7 @@ index 0000000..279ea5a +.* : + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} -+ .*: ebfffff9 bl .* ++ .*: ebfffff9 bl .* + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + @@ -2736509,10 +2751209,10 @@ index 0000000..d6c4787 + .size lib_func2, . - lib_func2 diff --git a/ld/testsuite/ld-arm/arm-lib.d b/ld/testsuite/ld-arm/arm-lib.d new file mode 100644 -index 0000000..22e21d5 +index 0000000..887880f --- /dev/null +++ b/ld/testsuite/ld-arm/arm-lib.d -@@ -0,0 +1,28 @@ +@@ -0,0 +1,29 @@ + +tmpdir/arm-lib.so: file format elf32-(little|big)arm.* +architecture: armv4t, flags 0x00000150: @@ -2736521,12 +2751221,13 @@ index 0000000..22e21d5 + +Disassembly of section .plt: + -+.* <.plt>: ++.* : + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) -+ .*: e59fe004 ldr lr, \[pc, #4\] ; .* ++ .*: e59fe004 ldr lr, \[pc, #4\] ; .* + .*: e08fe00e add lr, pc, lr + .*: e5bef008 ldr pc, \[lr, #8\]! + .*: .* ++.* : + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* @@ -2736535,7 +2751236,7 @@ index 0000000..22e21d5 +.* : + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} -+ .*: ebfffff9 bl .* ++ .*: ebfffff9 bl .* + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + @@ -2736543,7 +2751244,7 @@ index 0000000..22e21d5 + .*: e12fff1e bx lr diff --git a/ld/testsuite/ld-arm/arm-lib.ld b/ld/testsuite/ld-arm/arm-lib.ld new file mode 100644 -index 0000000..c9482c3 +index 0000000..f158c23 --- /dev/null +++ b/ld/testsuite/ld-arm/arm-lib.ld @@ -0,0 +1,187 @@ @@ -2736690,7 +2751391,7 @@ index 0000000..c9482c3 + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ -+ . = ALIGN(32 / 8); ++ . = ALIGN(. != 0 ? 32 / 8 : 1); + } + . = ALIGN(32 / 8); + _end = .; @@ -2736875,16 +2751576,13 @@ index 0000000..ba8b1c5 + movt r0, #:upper16:(thumb1 - arm2) diff --git a/ld/testsuite/ld-arm/arm-no-rel-plt.ld b/ld/testsuite/ld-arm/arm-no-rel-plt.ld new file mode 100644 -index 0000000..439909c +index 0000000..391e663 --- /dev/null +++ b/ld/testsuite/ld-arm/arm-no-rel-plt.ld -@@ -0,0 +1,233 @@ +@@ -0,0 +1,229 @@ +/* Script for -z combreloc: combine and sort reloc sections */ -+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", -+ "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) -+SEARCH_DIR("/home/meadori/Code/install/arm-none-eabi/lib"); +SECTIONS +{ + /* Read-only sections, merged into text segment: */ @@ -2737062,7 +2751760,6 @@ index 0000000..439909c + } + _bss_end__ = . ; __bss_end__ = . ; + . = ALIGN(32 / 8); -+ . = ALIGN(32 / 8); + __end__ = . ; + _end = .; PROVIDE (end = .); + /* Stabs debugging sections. */ @@ -2737195,7 +2751892,7 @@ index 0000000..37eee66 +foo: diff --git a/ld/testsuite/ld-arm/arm-rel32.d b/ld/testsuite/ld-arm/arm-rel32.d new file mode 100644 -index 0000000..919aaa4 +index 0000000..ff26386 --- /dev/null +++ b/ld/testsuite/ld-arm/arm-rel32.d @@ -0,0 +1,12 @@ @@ -2737210,7 +2751907,7 @@ index 0000000..919aaa4 + + +Contents of section \.data: -+ [^ ]+ 00000000 00010000 .* ++ [^ ]+ 00000000 (00010000|00000100) .* diff --git a/ld/testsuite/ld-arm/arm-rel32.s b/ld/testsuite/ld-arm/arm-rel32.s new file mode 100644 index 0000000..885b87c @@ -2737415,10 +2752112,10 @@ index 0000000..8e3fac2 +} diff --git a/ld/testsuite/ld-arm/armthumb-lib.d b/ld/testsuite/ld-arm/armthumb-lib.d new file mode 100644 -index 0000000..dae72ed +index 0000000..b63e3e6 --- /dev/null +++ b/ld/testsuite/ld-arm/armthumb-lib.d -@@ -0,0 +1,44 @@ +@@ -0,0 +1,45 @@ + +tmpdir/armthumb-lib.so: file format elf32-(little|big)arm +architecture: armv4t, flags 0x00000150: @@ -2737427,12 +2752124,13 @@ index 0000000..dae72ed + +Disassembly of section .plt: + -+.* <.plt>: ++.* : + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) -+ .*: e59fe004 ldr lr, \[pc, #4\] ; .* ++ .*: e59fe004 ldr lr, \[pc, #4\] ; .* + .*: e08fe00e add lr, pc, lr + .*: e5bef008 ldr pc, \[lr, #8\]! + .*: .* ++.* : + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* @@ -2737441,7 +2752139,7 @@ index 0000000..dae72ed +.* : + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} -+ .*: ebfffff. bl .* ++ .*: ebfffff. bl .* + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + .*: e1a00000 nop ; \(mov r0, r0\) @@ -2739333,22 +2754031,23 @@ index 0000000..e327ac1 + 80102e: f7ff bfe4 b.w 800ffa diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-b-plt.d b/ld/testsuite/ld-arm/cortex-a8-fix-b-plt.d new file mode 100644 -index 0000000..4f1078d +index 0000000..0f40861 --- /dev/null +++ b/ld/testsuite/ld-arm/cortex-a8-fix-b-plt.d -@@ -0,0 +1,30 @@ +@@ -0,0 +1,31 @@ + +.* + + +Disassembly of section \.plt: + -+00008000 <\.plt>: ++00008000 : + 8000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) -+ 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 ++ 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 + 8008: e08fe00e add lr, pc, lr + 800c: e5bef008 ldr pc, \[lr, #8\]! + 8010: 00000ffc \.word 0x00000ffc ++00008014 : + 8014: 4778 bx pc + 8016: 46c0 nop ; \(mov r8, r8\) + 8018: e28fc600 add ip, pc, #0, 12 @@ -2739366,7 +2754065,7 @@ index 0000000..4f1078d + 9002: 0000 movs r0, r0 + 9004: 0000 movs r0, r0 + 9006: 0000 movs r0, r0 -+ 9008: f7ff b804 b\.w 8014 ++ 9008: f7ff b804 b\.w 8014 diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-b-plt.s b/ld/testsuite/ld-arm/cortex-a8-fix-b-plt.s new file mode 100644 index 0000000..afd340d @@ -2739733,22 +2754432,23 @@ index 0000000..c0f21ac + bx lr diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bcc-plt.d b/ld/testsuite/ld-arm/cortex-a8-fix-bcc-plt.d new file mode 100644 -index 0000000..1e0cab2 +index 0000000..b6e6fff --- /dev/null +++ b/ld/testsuite/ld-arm/cortex-a8-fix-bcc-plt.d -@@ -0,0 +1,32 @@ +@@ -0,0 +1,33 @@ + +.* + + +Disassembly of section \.plt: + -+00008000 <\.plt>: ++00008000 : + 8000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) -+ 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 ++ 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 + 8008: e08fe00e add lr, pc, lr + 800c: e5bef008 ldr pc, \[lr, #8\]! + 8010: 00001004 \.word 0x00001004 ++00008014 : + 8014: 4778 bx pc + 8016: 46c0 nop ; \(mov r8, r8\) + 8018: e28fc600 add ip, pc, #0, 12 @@ -2739768,7 +2754468,7 @@ index 0000000..1e0cab2 + 9006: 0000 movs r0, r0 + 9008: d001 beq\.n 900e + 900a: f7ff bffa b\.w 9002 -+ 900e: f7ff b801 b\.w 8014 ++ 900e: f7ff b801 b\.w 8014 diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bcc-plt.s b/ld/testsuite/ld-arm/cortex-a8-fix-bcc-plt.s new file mode 100644 index 0000000..026fa95 @@ -2740047,22 +2754747,23 @@ index 0000000..8a667a3 + bx lr diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bl-plt.d b/ld/testsuite/ld-arm/cortex-a8-fix-bl-plt.d new file mode 100644 -index 0000000..ebb480f +index 0000000..baad3d0 --- /dev/null +++ b/ld/testsuite/ld-arm/cortex-a8-fix-bl-plt.d -@@ -0,0 +1,28 @@ +@@ -0,0 +1,29 @@ + +.* + + +Disassembly of section \.plt: + -+00008000 <\.plt>: ++00008000 : + 8000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) -+ 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 ++ 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 + 8008: e08fe00e add lr, pc, lr + 800c: e5bef008 ldr pc, \[lr, #8\]! + 8010: 00000ffc \.word 0x00000ffc ++00008014 : + 8014: e28fc600 add ip, pc, #0, 12 + 8018: e28cca00 add ip, ip, #0, 20 + 801c: e5bcfffc ldr pc, \[ip, #4092\]! ; 0xffc @@ -2740078,7 +2754779,7 @@ index 0000000..ebb480f + 9002: 0000 movs r0, r0 + 9004: 0000 movs r0, r0 + 9006: 0000 movs r0, r0 -+ 9008: eafffc01 b 8014 ++ 9008: eafffc01 b 8014 diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bl-plt.s b/ld/testsuite/ld-arm/cortex-a8-fix-bl-plt.s new file mode 100644 index 0000000..7f2db05 @@ -2740182,22 +2754883,23 @@ index 0000000..fcb3bab + 9010: eaffffba b 8f00 diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-plt.d b/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-plt.d new file mode 100644 -index 0000000..f8a9c24 +index 0000000..e2fd8ac --- /dev/null +++ b/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-plt.d -@@ -0,0 +1,92 @@ +@@ -0,0 +1,93 @@ + +.*: file format .* + + +Disassembly of section \.plt: + -+00008e00 <\.plt>: ++00008e00 : + 8e00: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) -+ 8e04: e59fe004 ldr lr, \[pc, #4\] ; 8e10 ++ 8e04: e59fe004 ldr lr, \[pc, #4\] ; 8e10 + 8e08: e08fe00e add lr, pc, lr + 8e0c: e5bef008 ldr pc, \[lr, #8\]! + 8e10: 0000827c \.word 0x0000827c ++00008e14 : + 8e14: e28fc600 add ip, pc, #0, 12 + 8e18: e28cca08 add ip, ip, #8, 20 ; 0x8000 + 8e1c: e5bcf27c ldr pc, \[ip, #636\]! ; 0x27c @@ -2740212,72 +2754914,72 @@ index 0000000..f8a9c24 +00008f08 <_start>: + 8f08: bf00 nop + 8f0a: eb01 0002 add\.w r0, r1, r2 -+ 8f0e: f7ff ef82 blx 8e14 ++ 8f0e: f7ff ef82 blx 8e14 + 8f12: eb01 0002 add\.w r0, r1, r2 -+ 8f16: f7ff ef7e blx 8e14 ++ 8f16: f7ff ef7e blx 8e14 + 8f1a: eb01 0002 add\.w r0, r1, r2 -+ 8f1e: f7ff ef7a blx 8e14 ++ 8f1e: f7ff ef7a blx 8e14 + 8f22: eb01 0002 add\.w r0, r1, r2 -+ 8f26: f7ff ef76 blx 8e14 ++ 8f26: f7ff ef76 blx 8e14 + 8f2a: eb01 0002 add\.w r0, r1, r2 -+ 8f2e: f7ff ef72 blx 8e14 ++ 8f2e: f7ff ef72 blx 8e14 + 8f32: eb01 0002 add\.w r0, r1, r2 -+ 8f36: f7ff ef6e blx 8e14 ++ 8f36: f7ff ef6e blx 8e14 + 8f3a: eb01 0002 add\.w r0, r1, r2 -+ 8f3e: f7ff ef6a blx 8e14 ++ 8f3e: f7ff ef6a blx 8e14 + 8f42: eb01 0002 add\.w r0, r1, r2 -+ 8f46: f7ff ef66 blx 8e14 ++ 8f46: f7ff ef66 blx 8e14 + 8f4a: eb01 0002 add\.w r0, r1, r2 -+ 8f4e: f7ff ef62 blx 8e14 ++ 8f4e: f7ff ef62 blx 8e14 + 8f52: eb01 0002 add\.w r0, r1, r2 -+ 8f56: f7ff ef5e blx 8e14 ++ 8f56: f7ff ef5e blx 8e14 + 8f5a: eb01 0002 add\.w r0, r1, r2 -+ 8f5e: f7ff ef5a blx 8e14 ++ 8f5e: f7ff ef5a blx 8e14 + 8f62: eb01 0002 add\.w r0, r1, r2 -+ 8f66: f7ff ef56 blx 8e14 ++ 8f66: f7ff ef56 blx 8e14 + 8f6a: eb01 0002 add\.w r0, r1, r2 -+ 8f6e: f7ff ef52 blx 8e14 ++ 8f6e: f7ff ef52 blx 8e14 + 8f72: eb01 0002 add\.w r0, r1, r2 -+ 8f76: f7ff ef4e blx 8e14 ++ 8f76: f7ff ef4e blx 8e14 + 8f7a: eb01 0002 add\.w r0, r1, r2 -+ 8f7e: f7ff ef4a blx 8e14 ++ 8f7e: f7ff ef4a blx 8e14 + 8f82: eb01 0002 add\.w r0, r1, r2 -+ 8f86: f7ff ef46 blx 8e14 ++ 8f86: f7ff ef46 blx 8e14 + 8f8a: eb01 0002 add\.w r0, r1, r2 -+ 8f8e: f7ff ef42 blx 8e14 ++ 8f8e: f7ff ef42 blx 8e14 + 8f92: eb01 0002 add\.w r0, r1, r2 -+ 8f96: f7ff ef3e blx 8e14 ++ 8f96: f7ff ef3e blx 8e14 + 8f9a: eb01 0002 add\.w r0, r1, r2 -+ 8f9e: f7ff ef3a blx 8e14 ++ 8f9e: f7ff ef3a blx 8e14 + 8fa2: eb01 0002 add\.w r0, r1, r2 -+ 8fa6: f7ff ef36 blx 8e14 ++ 8fa6: f7ff ef36 blx 8e14 + 8faa: eb01 0002 add\.w r0, r1, r2 -+ 8fae: f7ff ef32 blx 8e14 ++ 8fae: f7ff ef32 blx 8e14 + 8fb2: eb01 0002 add\.w r0, r1, r2 -+ 8fb6: f7ff ef2e blx 8e14 ++ 8fb6: f7ff ef2e blx 8e14 + 8fba: eb01 0002 add\.w r0, r1, r2 -+ 8fbe: f7ff ef2a blx 8e14 ++ 8fbe: f7ff ef2a blx 8e14 + 8fc2: eb01 0002 add\.w r0, r1, r2 -+ 8fc6: f7ff ef26 blx 8e14 ++ 8fc6: f7ff ef26 blx 8e14 + 8fca: eb01 0002 add\.w r0, r1, r2 -+ 8fce: f7ff ef22 blx 8e14 ++ 8fce: f7ff ef22 blx 8e14 + 8fd2: eb01 0002 add\.w r0, r1, r2 -+ 8fd6: f7ff ef1e blx 8e14 ++ 8fd6: f7ff ef1e blx 8e14 + 8fda: eb01 0002 add\.w r0, r1, r2 -+ 8fde: f7ff ef1a blx 8e14 ++ 8fde: f7ff ef1a blx 8e14 + 8fe2: eb01 0002 add\.w r0, r1, r2 -+ 8fe6: f7ff ef16 blx 8e14 ++ 8fe6: f7ff ef16 blx 8e14 + 8fea: eb01 0002 add\.w r0, r1, r2 -+ 8fee: f7ff ef12 blx 8e14 ++ 8fee: f7ff ef12 blx 8e14 + 8ff2: eb01 0002 add\.w r0, r1, r2 -+ 8ff6: f7ff ef0e blx 8e14 ++ 8ff6: f7ff ef0e blx 8e14 + 8ffa: eb01 0002 add\.w r0, r1, r2 + 8ffe: f000 e808 blx 9010 <_start\+0x108> + 9002: eb01 0002 add\.w r0, r1, r2 -+ 9006: f7ff ef06 blx 8e14 ++ 9006: f7ff ef06 blx 8e14 + 900a: 4770 bx lr + 900c: f3af 8000 nop\.w -+ 9010: eaffff7f b 8e14 ++ 9010: eaffff7f b 8e14 diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-thumb.d b/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-thumb.d new file mode 100644 index 0000000..8cbd3e0 @@ -2741738,22 +2756440,23 @@ index 0000000..cb40fb4 + bx lr diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-blx-plt.d b/ld/testsuite/ld-arm/cortex-a8-fix-blx-plt.d new file mode 100644 -index 0000000..ebb480f +index 0000000..baad3d0 --- /dev/null +++ b/ld/testsuite/ld-arm/cortex-a8-fix-blx-plt.d -@@ -0,0 +1,28 @@ +@@ -0,0 +1,29 @@ + +.* + + +Disassembly of section \.plt: + -+00008000 <\.plt>: ++00008000 : + 8000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) -+ 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 ++ 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 + 8008: e08fe00e add lr, pc, lr + 800c: e5bef008 ldr pc, \[lr, #8\]! + 8010: 00000ffc \.word 0x00000ffc ++00008014 : + 8014: e28fc600 add ip, pc, #0, 12 + 8018: e28cca00 add ip, ip, #0, 20 + 801c: e5bcfffc ldr pc, \[ip, #4092\]! ; 0xffc @@ -2741769,7 +2756472,7 @@ index 0000000..ebb480f + 9002: 0000 movs r0, r0 + 9004: 0000 movs r0, r0 + 9006: 0000 movs r0, r0 -+ 9008: eafffc01 b 8014 ++ 9008: eafffc01 b 8014 diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-blx-plt.s b/ld/testsuite/ld-arm/cortex-a8-fix-blx-plt.s new file mode 100644 index 0000000..1932034 @@ -2742244,12 +2756947,12 @@ index 0000000..96c180f + bx lr diff --git a/ld/testsuite/ld-arm/data-only-map.d b/ld/testsuite/ld-arm/data-only-map.d new file mode 100644 -index 0000000..706e709 +index 0000000..fee073a --- /dev/null +++ b/ld/testsuite/ld-arm/data-only-map.d @@ -0,0 +1,13 @@ + -+[^:]*: file format elf32-littlearm.* ++[^:]*: file format elf32-(big|little)arm.* + + +Disassembly of section \.text: @@ -2742522,13 +2757225,13 @@ index 0000000..71546d7 + .size _start,.-_start diff --git a/ld/testsuite/ld-arm/export-class.exp b/ld/testsuite/ld-arm/export-class.exp new file mode 100644 -index 0000000..8fac9ec +index 0000000..97d3c0a --- /dev/null +++ b/ld/testsuite/ld-arm/export-class.exp @@ -0,0 +1,86 @@ +# Expect script for symbol export classes, ARM variation. +# -+# Copyright 2012 Free Software Foundation, Inc. ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2743405,10 +2758108,10 @@ index 0000000..803e8d0 + diff --git a/ld/testsuite/ld-arm/farcall-mixed-app-v5.d b/ld/testsuite/ld-arm/farcall-mixed-app-v5.d new file mode 100644 -index 0000000..781b972 +index 0000000..7466883 --- /dev/null +++ b/ld/testsuite/ld-arm/farcall-mixed-app-v5.d -@@ -0,0 +1,85 @@ +@@ -0,0 +1,87 @@ + +tmpdir/farcall-mixed-app-v5: file format elf32-(little|big)arm +architecture: armv4t, flags 0x00000112: @@ -2743417,15 +2758120,17 @@ index 0000000..781b972 + +Disassembly of section .plt: + -+.* <.plt>: ++.* : + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) -+ .*: e59fe004 ldr lr, \[pc, #4\] ; .* <_start-0x28> ++ .*: e59fe004 ldr lr, \[pc, #4\] ; .* + .*: e08fe00e add lr, pc, lr + .*: e5bef008 ldr pc, \[lr, #8\]! + .*: .* ++.* : + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* ++.* : + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* @@ -2743436,15 +2758141,15 @@ index 0000000..781b972 + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} + .*: eb000008 bl .* <__app_func_veneer> -+ .*: ebfffff5 bl .* <_start-0x18> -+ .*: ebfffff1 bl .* <_start-0x24> ++ .*: ebfffff5 bl .* ++ .*: ebfffff1 bl .* + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + .*: e1a00000 nop ; \(mov r0, r0\) + +.* : + .*: b500 push {lr} -+ .*: f7ff efdc blx .* <_start-0x24> ++ .*: f7ff efdc blx .* + .*: bd00 pop {pc} + .*: 4770 bx lr + .*: 46c0 nop ; \(mov r8, r8\) @@ -2743496,10 +2758201,10 @@ index 0000000..781b972 + .*: 000081dc .word 0x000081dc diff --git a/ld/testsuite/ld-arm/farcall-mixed-app.d b/ld/testsuite/ld-arm/farcall-mixed-app.d new file mode 100644 -index 0000000..b6cc2d0 +index 0000000..cfe31a4 --- /dev/null +++ b/ld/testsuite/ld-arm/farcall-mixed-app.d -@@ -0,0 +1,90 @@ +@@ -0,0 +1,92 @@ + +tmpdir/farcall-mixed-app: file format elf32-(little|big)arm +architecture: armv4t, flags 0x00000112: @@ -2743508,17 +2758213,19 @@ index 0000000..b6cc2d0 + +Disassembly of section .plt: + -+.* <.plt>: ++.* : + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) -+ .*: e59fe004 ldr lr, \[pc, #4\] ; .* <_start-0x28> ++ .*: e59fe004 ldr lr, \[pc, #4\] ; .* + .*: e08fe00e add lr, pc, lr + .*: e5bef008 ldr pc, \[lr, #8\]! + .*: .* ++.* : + .*: 4778 bx pc + .*: 46c0 nop ; \(mov r8, r8\) + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* ++.* : + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* @@ -2743529,15 +2758236,15 @@ index 0000000..b6cc2d0 + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} + .*: eb000008 bl .* <__app_func_veneer> -+ .*: ebfffff6 bl .* <_start-0x14> -+ .*: ebfffff2 bl .* <_start-0x20> ++ .*: ebfffff6 bl .* ++ .*: ebfffff2 bl .* + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + .*: e1a00000 nop ; \(mov r0, r0\) + +.* : + .*: b500 push {lr} -+ .*: f7ff ffdb bl 81dc <_start-0x24> ++ .*: f7ff ffdb bl 81dc + .*: bd00 pop {pc} + .*: 4770 bx lr + .*: 46c0 nop ; \(mov r8, r8\) @@ -2743696,10 +2758403,10 @@ index 0000000..093397c + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +12 _bss_end__ diff --git a/ld/testsuite/ld-arm/farcall-mixed-lib-v4t.d b/ld/testsuite/ld-arm/farcall-mixed-lib-v4t.d new file mode 100644 -index 0000000..3be297b +index 0000000..eec8de6 --- /dev/null +++ b/ld/testsuite/ld-arm/farcall-mixed-lib-v4t.d -@@ -0,0 +1,123 @@ +@@ -0,0 +1,127 @@ +tmpdir/farcall-mixed-lib.so: file format elf32-(little|big)arm +architecture: armv4t, flags 0x00000150: +HAS_SYMS, DYNAMIC, D_PAGED @@ -2743707,27 +2758414,31 @@ index 0000000..3be297b + +Disassembly of section .plt: + -+.* <.plt>: ++.* : + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) -+ .*: e59fe004 ldr lr, \[pc, #4\] ; .* ++ .*: e59fe004 ldr lr, \[pc, #4\] ; .* + .*: e08fe00e add lr, pc, lr + .*: e5bef008 ldr pc, \[lr, #8\]! + .*: .* .word .* ++.* : + .*: 4778 bx pc + .*: 46c0 nop ; \(mov r8, r8\) + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]! ; .* ++.* : + .*: 4778 bx pc + .*: 46c0 nop ; \(mov r8, r8\) + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]! ; 0x.* ++.* : + .*: 4778 bx pc + .*: 46c0 nop ; \(mov r8, r8\) + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]! ; 0x.* ++.* : + .*: 4778 bx pc + .*: 46c0 nop ; \(mov r8, r8\) + .*: e28fc6.* add ip, pc, #.* @@ -2743739,10 +2758450,10 @@ index 0000000..3be297b +.* : + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} -+ .*: ebffff.. bl .* -+ .*: ebffff.. bl .* -+ .*: ebffff.. bl .* -+ .*: ebffff.. bl .* ++ .*: ebffff.. bl .* ++ .*: ebffff.. bl .* ++ .*: ebffff.. bl .* ++ .*: ebffff.. bl .* + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + ... @@ -2743825,10 +2758536,10 @@ index 0000000..3be297b + .*: feffff55 .word 0xfeffff55 diff --git a/ld/testsuite/ld-arm/farcall-mixed-lib.d b/ld/testsuite/ld-arm/farcall-mixed-lib.d new file mode 100644 -index 0000000..05578f4 +index 0000000..9577af9 --- /dev/null +++ b/ld/testsuite/ld-arm/farcall-mixed-lib.d -@@ -0,0 +1,92 @@ +@@ -0,0 +1,96 @@ +tmpdir/farcall-mixed-lib.so: file format elf32-(little|big)arm +architecture: armv5t, flags 0x00000150: +HAS_SYMS, DYNAMIC, D_PAGED @@ -2743836,21 +2758547,25 @@ index 0000000..05578f4 + +Disassembly of section .plt: + -+.* <.plt>: ++.* : + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) -+ .*: e59fe004 ldr lr, \[pc, #4\] ; .* ++ .*: e59fe004 ldr lr, \[pc, #4\] ; .* + .*: e08fe00e add lr, pc, lr + .*: e5bef008 ldr pc, \[lr, #8\]! + .*: .* ++.* : + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* ++.* : + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* ++.* : + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* ++.* : + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* @@ -2743860,10 +2758575,10 @@ index 0000000..05578f4 +.* : + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} -+ .*: ebffff.. bl .* -+ .*: ebffff.. bl .* -+ .*: ebfffff. bl .* -+ .*: ebfffff. bl .* ++ .*: ebffff.. bl .* ++ .*: ebffff.. bl .* ++ .*: ebfffff. bl .* ++ .*: ebfffff. bl .* + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + ... @@ -2744403,12 +2759118,12 @@ index 0000000..650b1a6 + diff --git a/ld/testsuite/ld-arm/fix-arm1176-off.d b/ld/testsuite/ld-arm/fix-arm1176-off.d new file mode 100644 -index 0000000..89f01e2 +index 0000000..2693873 --- /dev/null +++ b/ld/testsuite/ld-arm/fix-arm1176-off.d @@ -0,0 +1,17 @@ + -+.*: file format elf32-littlearm.* ++.*: file format elf32-(big|little)arm.* + + +Disassembly of section .foo: @@ -2744426,12 +2759141,12 @@ index 0000000..89f01e2 + +[0-9a-f]+: e12fff1e bx lr diff --git a/ld/testsuite/ld-arm/fix-arm1176-on.d b/ld/testsuite/ld-arm/fix-arm1176-on.d new file mode 100644 -index 0000000..6417a33 +index 0000000..834618e --- /dev/null +++ b/ld/testsuite/ld-arm/fix-arm1176-on.d @@ -0,0 +1,20 @@ + -+.+: file format elf32-littlearm.* ++.+: file format elf32-(big|little)arm.* + + +Disassembly of section .foo: @@ -2744473,16 +2759188,17 @@ index 0000000..96e0328 + diff --git a/ld/testsuite/ld-arm/gc-hidden-1.d b/ld/testsuite/ld-arm/gc-hidden-1.d new file mode 100644 -index 0000000..fe77abc +index 0000000..f0f1fd4 --- /dev/null +++ b/ld/testsuite/ld-arm/gc-hidden-1.d -@@ -0,0 +1,25 @@ -+#target: arm*-*-*eabi* +@@ -0,0 +1,26 @@ +#source: main.s +#source: gcdfn.s +#source: hidfn.s +#ld: --gc-sections --shared --version-script hideall.ld +#objdump: -dRT ++# This test is only valid on ELF based ports. ++# not-target: *-*-*coff *-*-pe *-*-wince *-*-*aout* *-*-netbsd *-*-riscix* + +# See PR ld/13990: a forced-local PLT reference to a +# forced-local symbol is GC'ed, trigging a BFD_ASSERT. @@ -2744490,18 +2759206,18 @@ index 0000000..fe77abc +.*: file format elf32-.* + +DYNAMIC SYMBOL TABLE: -+0+124 l d .text 0+ .text ++0+[0-9a-f]+ l d .text 0+ .text +0+ g DO \*ABS\* 0+ NS NS + +Disassembly of section .text: + -+0+124 <_start>: -+ 124: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) -+ 128: eb000000 bl 130 -+ 12c: e8bd8000 ldmfd sp!, {pc} ++0+[0-9a-f]+ <_start>: ++\s*[0-9a-f]+:\s+e52de004\s+push {lr} ; \(str lr, \[sp, #-4\]!\) ++\s*[0-9a-f]+:\s+eb000000\s+bl [0-9a-f]+ ++\s*[0-9a-f]+:\s+e8bd8000\s+ldmfd sp!, {pc} + -+0+130 : -+ 130: e8bd8000 ldmfd sp!, {pc} ++0+[0-9a-f]+ : ++\s*[0-9a-f]+:\s+e8bd8000\s+ldmfd sp!, {pc} diff --git a/ld/testsuite/ld-arm/gc-thumb-lib.s b/ld/testsuite/ld-arm/gc-thumb-lib.s new file mode 100644 index 0000000..2065d35 @@ -2745296,7 +2760012,7 @@ index 0000000..14b1482 + a0b8: 00006f6c \.word 0x00006f6c diff --git a/ld/testsuite/ld-arm/ifunc-1.gd b/ld/testsuite/ld-arm/ifunc-1.gd new file mode 100644 -index 0000000..ff51d37 +index 0000000..f76f6cd --- /dev/null +++ b/ld/testsuite/ld-arm/ifunc-1.gd @@ -0,0 +1,29 @@ @@ -2745307,7 +2760023,7 @@ index 0000000..ff51d37 +#------------------------------------------------------------------------------ +#------ 00010000: foo +#------------------------------------------------------------------------------ -+ 10000 44332211 00800000 18800000 .* ++ 10000 (44332211 00800000 18800000|11223344 00008000 00008018) .* +Contents of section \.got: +#------------------------------------------------------------------------------ +#------ 00011000: .got.plt @@ -2745315,20 +2760031,20 @@ index 0000000..ff51d37 +#------ 00011008: reserved .got.plt entry +#------ 0001100c: f1's .igot.plt entry [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 11000 00000000 00000000 00000000 00a00000 .* ++ 11000 00000000 00000000 00000000 (00a00000|0000a000) .* +#------------------------------------------------------------------------------ +#------ 00011010: f3's .igot.plt pointer to 0xa008 [R_ARM_IRELATIVE] +#------ 00011014: f2's .igot.plt pointer to 0xa004 [R_ARM_IRELATIVE] +#------ 00011018: .got entry for foo +#------ 0001101c: .got entry for f1's .iplt entry +#------------------------------------------------------------------------------ -+ 11010 08a00000 04a00000 00000100 00900000 .* ++ 11010 (08a00000 04a00000 00000100 00900000|0000a008 0000a004 00010000 00009000) .* +#------------------------------------------------------------------------------ +#------ 00011020: .got entry for foo +#------ 00011024: .got entry for f3 +#------ 00011028: .got entry for f2 +#------------------------------------------------------------------------------ -+ 11020 00000100 0c900000 18900000 .* ++ 11020 (00000100 0c900000 18900000|00010000 0000900c 00009018) .* diff --git a/ld/testsuite/ld-arm/ifunc-1.rd b/ld/testsuite/ld-arm/ifunc-1.rd new file mode 100644 index 0000000..2644123 @@ -2745399,19 +2760115,19 @@ index 0000000..7745c54 + .word __irel_end diff --git a/ld/testsuite/ld-arm/ifunc-10.dd b/ld/testsuite/ld-arm/ifunc-10.dd new file mode 100644 -index 0000000..105b09b +index 0000000..88bae50 --- /dev/null +++ b/ld/testsuite/ld-arm/ifunc-10.dd -@@ -0,0 +1,951 @@ +@@ -0,0 +1,963 @@ + +.* + + +Disassembly of section \.plt: + -+00009000 <\.plt>: ++00009000 : + 9000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) -+ 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 ++ 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 + 9008: e08fe00e add lr, pc, lr + 900c: e5bef008 ldr pc, \[lr, #8\]! +#------------------------------------------------------------------------------ @@ -2745421,6 +2760137,7 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ thumb entry to atf2's .plt entry +#------------------------------------------------------------------------------ ++00009014 : + 9014: 4778 bx pc + 9016: 46c0 nop ; \(mov r8, r8\) +#------------------------------------------------------------------------------ @@ -2745432,12 +2760149,14 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ aaf4's .plt entry +#------------------------------------------------------------------------------ ++00009024 : + 9024: e28fc600 add ip, pc, #0, 12 + 9028: e28cca07 add ip, ip, #28672 ; 0x7000 + 902c: e5bcffe4 ldr pc, \[ip, #4068\]! ; 0xfe4 +#------------------------------------------------------------------------------ +#------ thumb entry to ttf2's .plt entry +#------------------------------------------------------------------------------ ++00009030 : + 9030: 4778 bx pc + 9032: 46c0 nop ; \(mov r8, r8\) +#------------------------------------------------------------------------------ @@ -2745449,6 +2760168,7 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ thumb entry to tbf2's .plt entry +#------------------------------------------------------------------------------ ++00009040 : + 9040: 4778 bx pc + 9042: 46c0 nop ; \(mov r8, r8\) +#------------------------------------------------------------------------------ @@ -2745460,18 +2760180,21 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ taf2's .plt entry +#------------------------------------------------------------------------------ ++00009050 : + 9050: e28fc600 add ip, pc, #0, 12 + 9054: e28cca07 add ip, ip, #28672 ; 0x7000 + 9058: e5bcffc4 ldr pc, \[ip, #4036\]! ; 0xfc4 +#------------------------------------------------------------------------------ +#------ aaf2's .plt entry +#------------------------------------------------------------------------------ ++0000905c : + 905c: e28fc600 add ip, pc, #0, 12 + 9060: e28cca07 add ip, ip, #28672 ; 0x7000 + 9064: e5bcffbc ldr pc, \[ip, #4028\]! ; 0xfbc +#------------------------------------------------------------------------------ +#------ thumb entry to abf4's .plt entry +#------------------------------------------------------------------------------ ++00009068 : + 9068: 4778 bx pc + 906a: 46c0 nop ; \(mov r8, r8\) +#------------------------------------------------------------------------------ @@ -2745483,6 +2760206,7 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ thumb entry to tbf4's .plt entry +#------------------------------------------------------------------------------ ++00009078 : + 9078: 4778 bx pc + 907a: 46c0 nop ; \(mov r8, r8\) +#------------------------------------------------------------------------------ @@ -2745494,6 +2760218,7 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ thumb entry to ttf4's .plt entry +#------------------------------------------------------------------------------ ++00009088 : + 9088: 4778 bx pc + 908a: 46c0 nop ; \(mov r8, r8\) +#------------------------------------------------------------------------------ @@ -2745505,6 +2760230,7 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ thumb entry to atf4's .plt entry +#------------------------------------------------------------------------------ ++00009098 : + 9098: 4778 bx pc + 909a: 46c0 nop ; \(mov r8, r8\) +#------------------------------------------------------------------------------ @@ -2745516,12 +2760242,14 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ taf4's .plt entry +#------------------------------------------------------------------------------ ++000090a8 : + 90a8: e28fc600 add ip, pc, #0, 12 + 90ac: e28cca07 add ip, ip, #28672 ; 0x7000 + 90b0: e5bcff84 ldr pc, \[ip, #3972\]! ; 0xf84 +#------------------------------------------------------------------------------ +#------ thumb entry to abf2's .plt entry +#------------------------------------------------------------------------------ ++000090b4 : + 90b4: 4778 bx pc + 90b6: 46c0 nop ; \(mov r8, r8\) +#------------------------------------------------------------------------------ @@ -2745686,15 +2760414,15 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ aaf1's .iplt entry +#------------------------------------------------------------------------------ -+ a044: ebfffc1e bl 90c4 ++ a044: ebfffc1e bl 90c4 +#------------------------------------------------------------------------------ +#------ aaf1's .iplt entry +#------------------------------------------------------------------------------ -+ a048: eafffc1d b 90c4 ++ a048: eafffc1d b 90c4 +#------------------------------------------------------------------------------ +#------ aaf1's .iplt entry +#------------------------------------------------------------------------------ -+ a04c: 0afffc1c beq 90c4 ++ a04c: 0afffc1c beq 90c4 + a050: e59f4000 ldr r4, \[pc\] ; a058 <_start\+0x30> + a054: e59f4000 ldr r4, \[pc\] ; a05c <_start\+0x34> +#------------------------------------------------------------------------------ @@ -2745708,15 +2760436,15 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ taf1's .iplt entry +#------------------------------------------------------------------------------ -+ a060: ebfffc22 bl 90f0 ++ a060: ebfffc22 bl 90f0 +#------------------------------------------------------------------------------ +#------ taf1's .iplt entry +#------------------------------------------------------------------------------ -+ a064: eafffc21 b 90f0 ++ a064: eafffc21 b 90f0 +#------------------------------------------------------------------------------ +#------ taf1's .iplt entry +#------------------------------------------------------------------------------ -+ a068: 0afffc20 beq 90f0 ++ a068: 0afffc20 beq 90f0 + a06c: e59f4000 ldr r4, \[pc\] ; a074 <_start\+0x4c> + a070: e59f4000 ldr r4, \[pc\] ; a078 <_start\+0x50> +#------------------------------------------------------------------------------ @@ -2745730,15 +2760458,15 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ abf1's .iplt entry +#------------------------------------------------------------------------------ -+ a07c: ebfffc18 bl 90e4 ++ a07c: ebfffc18 bl 90e4 +#------------------------------------------------------------------------------ +#------ abf1's .iplt entry +#------------------------------------------------------------------------------ -+ a080: eafffc17 b 90e4 ++ a080: eafffc17 b 90e4 +#------------------------------------------------------------------------------ +#------ abf1's .iplt entry +#------------------------------------------------------------------------------ -+ a084: 0afffc16 beq 90e4 ++ a084: 0afffc16 beq 90e4 + a088: e59f4000 ldr r4, \[pc\] ; a090 <_start\+0x68> + a08c: e59f4000 ldr r4, \[pc\] ; a094 <_start\+0x6c> +#------------------------------------------------------------------------------ @@ -2745752,15 +2760480,15 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ tbf1's .iplt entry +#------------------------------------------------------------------------------ -+ a098: ebfffc1c bl 9110 ++ a098: ebfffc1c bl 9110 +#------------------------------------------------------------------------------ +#------ tbf1's .iplt entry +#------------------------------------------------------------------------------ -+ a09c: eafffc1b b 9110 ++ a09c: eafffc1b b 9110 +#------------------------------------------------------------------------------ +#------ tbf1's .iplt entry +#------------------------------------------------------------------------------ -+ a0a0: 0afffc1a beq 9110 ++ a0a0: 0afffc1a beq 9110 + a0a4: e59f4000 ldr r4, \[pc\] ; a0ac <_start\+0x84> + a0a8: e59f4000 ldr r4, \[pc\] ; a0b0 <_start\+0x88> +#------------------------------------------------------------------------------ @@ -2745774,15 +2760502,15 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ aaf2's .plt entry +#------------------------------------------------------------------------------ -+ a0b4: ebfffbe8 bl 905c ++ a0b4: ebfffbe8 bl 905c +#------------------------------------------------------------------------------ +#------ aaf2's .plt entry +#------------------------------------------------------------------------------ -+ a0b8: eafffbe7 b 905c ++ a0b8: eafffbe7 b 905c +#------------------------------------------------------------------------------ +#------ aaf2's .plt entry +#------------------------------------------------------------------------------ -+ a0bc: 0afffbe6 beq 905c ++ a0bc: 0afffbe6 beq 905c + a0c0: e59f4000 ldr r4, \[pc\] ; a0c8 <_start\+0xa0> + a0c4: e59f4000 ldr r4, \[pc\] ; a0cc <_start\+0xa4> +#------------------------------------------------------------------------------ @@ -2745796,15 +2760524,15 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ taf2's .plt entry +#------------------------------------------------------------------------------ -+ a0d0: ebfffbde bl 9050 ++ a0d0: ebfffbde bl 9050 +#------------------------------------------------------------------------------ +#------ taf2's .plt entry +#------------------------------------------------------------------------------ -+ a0d4: eafffbdd b 9050 ++ a0d4: eafffbdd b 9050 +#------------------------------------------------------------------------------ +#------ taf2's .plt entry +#------------------------------------------------------------------------------ -+ a0d8: 0afffbdc beq 9050 ++ a0d8: 0afffbdc beq 9050 + a0dc: e59f4000 ldr r4, \[pc\] ; a0e4 <_start\+0xbc> + a0e0: e59f4000 ldr r4, \[pc\] ; a0e8 <_start\+0xc0> +#------------------------------------------------------------------------------ @@ -2745818,15 +2760546,15 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ abf2's .plt entry +#------------------------------------------------------------------------------ -+ a0ec: ebfffbf1 bl 90b8 ++ a0ec: ebfffbf1 bl 90b8 +#------------------------------------------------------------------------------ +#------ abf2's .plt entry +#------------------------------------------------------------------------------ -+ a0f0: eafffbf0 b 90b8 ++ a0f0: eafffbf0 b 90b8 +#------------------------------------------------------------------------------ +#------ abf2's .plt entry +#------------------------------------------------------------------------------ -+ a0f4: 0afffbef beq 90b8 ++ a0f4: 0afffbef beq 90b8 + a0f8: e59f4000 ldr r4, \[pc\] ; a100 <_start\+0xd8> + a0fc: e59f4000 ldr r4, \[pc\] ; a104 <_start\+0xdc> +#------------------------------------------------------------------------------ @@ -2745840,15 +2760568,15 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ tbf2's .plt entry +#------------------------------------------------------------------------------ -+ a108: ebfffbcd bl 9044 ++ a108: ebfffbcd bl 9044 +#------------------------------------------------------------------------------ +#------ tbf2's .plt entry +#------------------------------------------------------------------------------ -+ a10c: eafffbcc b 9044 ++ a10c: eafffbcc b 9044 +#------------------------------------------------------------------------------ +#------ tbf2's .plt entry +#------------------------------------------------------------------------------ -+ a110: 0afffbcb beq 9044 ++ a110: 0afffbcb beq 9044 + a114: e59f4000 ldr r4, \[pc\] ; a11c <_start\+0xf4> + a118: e59f4000 ldr r4, \[pc\] ; a120 <_start\+0xf8> +#------------------------------------------------------------------------------ @@ -2745914,15 +2760642,15 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ aaf4's .plt entry +#------------------------------------------------------------------------------ -+ a194: ebfffba2 bl 9024 ++ a194: ebfffba2 bl 9024 +#------------------------------------------------------------------------------ +#------ aaf4's .plt entry +#------------------------------------------------------------------------------ -+ a198: eafffba1 b 9024 ++ a198: eafffba1 b 9024 +#------------------------------------------------------------------------------ +#------ aaf4's .plt entry +#------------------------------------------------------------------------------ -+ a19c: 0afffba0 beq 9024 ++ a19c: 0afffba0 beq 9024 + a1a0: e59f4000 ldr r4, \[pc\] ; a1a8 <_start\+0x180> + a1a4: e59f4000 ldr r4, \[pc\] ; a1ac <_start\+0x184> +#------------------------------------------------------------------------------ @@ -2745936,15 +2760664,15 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ taf4's .plt entry +#------------------------------------------------------------------------------ -+ a1b0: ebfffbbc bl 90a8 ++ a1b0: ebfffbbc bl 90a8 +#------------------------------------------------------------------------------ +#------ taf4's .plt entry +#------------------------------------------------------------------------------ -+ a1b4: eafffbbb b 90a8 ++ a1b4: eafffbbb b 90a8 +#------------------------------------------------------------------------------ +#------ taf4's .plt entry +#------------------------------------------------------------------------------ -+ a1b8: 0afffbba beq 90a8 ++ a1b8: 0afffbba beq 90a8 + a1bc: e59f4000 ldr r4, \[pc\] ; a1c4 <_start\+0x19c> + a1c0: e59f4000 ldr r4, \[pc\] ; a1c8 <_start\+0x1a0> +#------------------------------------------------------------------------------ @@ -2745958,15 +2760686,15 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ abf4's .plt entry +#------------------------------------------------------------------------------ -+ a1cc: ebfffba6 bl 906c ++ a1cc: ebfffba6 bl 906c +#------------------------------------------------------------------------------ +#------ abf4's .plt entry +#------------------------------------------------------------------------------ -+ a1d0: eafffba5 b 906c ++ a1d0: eafffba5 b 906c +#------------------------------------------------------------------------------ +#------ abf4's .plt entry +#------------------------------------------------------------------------------ -+ a1d4: 0afffba4 beq 906c ++ a1d4: 0afffba4 beq 906c + a1d8: e59f4000 ldr r4, \[pc\] ; a1e0 <_start\+0x1b8> + a1dc: e59f4000 ldr r4, \[pc\] ; a1e4 <_start\+0x1bc> +#------------------------------------------------------------------------------ @@ -2745980,15 +2760708,15 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ tbf4's .plt entry +#------------------------------------------------------------------------------ -+ a1e8: ebfffba3 bl 907c ++ a1e8: ebfffba3 bl 907c +#------------------------------------------------------------------------------ +#------ tbf4's .plt entry +#------------------------------------------------------------------------------ -+ a1ec: eafffba2 b 907c ++ a1ec: eafffba2 b 907c +#------------------------------------------------------------------------------ +#------ tbf4's .plt entry +#------------------------------------------------------------------------------ -+ a1f0: 0afffba1 beq 907c ++ a1f0: 0afffba1 beq 907c + a1f4: e59f4000 ldr r4, \[pc\] ; a1fc <_start\+0x1d4> + a1f8: e59f4000 ldr r4, \[pc\] ; a200 <_start\+0x1d8> +#------------------------------------------------------------------------------ @@ -2746017,15 +2760745,15 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ atf1's .iplt entry +#------------------------------------------------------------------------------ -+ a21c: f7fe ef5a blx 90d4 ++ a21c: f7fe ef5a blx 90d4 +#------------------------------------------------------------------------------ +#------ thumb entry to atf1's .iplt entry +#------------------------------------------------------------------------------ -+ a220: f7fe bf56 b\.w 90d0 ++ a220: f7fe bf56 b\.w 90d0 +#------------------------------------------------------------------------------ +#------ thumb entry to atf1's .iplt entry +#------------------------------------------------------------------------------ -+ a224: f43e af54 beq\.w 90d0 ++ a224: f43e af54 beq\.w 90d0 + a228: 4c00 ldr r4, \[pc, #0\] ; \(a22c <_thumb\+0x28>\) + a22a: 4c01 ldr r4, \[pc, #4\] ; \(a230 <_thumb\+0x2c>\) +#------------------------------------------------------------------------------ @@ -2746039,15 +2760767,15 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ ttf1's .iplt entry +#------------------------------------------------------------------------------ -+ a234: f7fe ef64 blx 9100 ++ a234: f7fe ef64 blx 9100 +#------------------------------------------------------------------------------ +#------ thumb entry to ttf1's .iplt entry +#------------------------------------------------------------------------------ -+ a238: f7fe bf60 b\.w 90fc ++ a238: f7fe bf60 b\.w 90fc +#------------------------------------------------------------------------------ +#------ thumb entry to ttf1's .iplt entry +#------------------------------------------------------------------------------ -+ a23c: f43e af5e beq\.w 90fc ++ a23c: f43e af5e beq\.w 90fc + a240: 4c00 ldr r4, \[pc, #0\] ; \(a244 <_thumb\+0x40>\) + a242: 4c01 ldr r4, \[pc, #4\] ; \(a248 <_thumb\+0x44>\) +#------------------------------------------------------------------------------ @@ -2746061,15 +2760789,15 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ abf1's .iplt entry +#------------------------------------------------------------------------------ -+ a24c: f7fe ef4a blx 90e4 ++ a24c: f7fe ef4a blx 90e4 +#------------------------------------------------------------------------------ +#------ thumb entry to abf1's .iplt entry +#------------------------------------------------------------------------------ -+ a250: f7fe bf46 b\.w 90e0 ++ a250: f7fe bf46 b\.w 90e0 +#------------------------------------------------------------------------------ +#------ thumb entry to abf1's .iplt entry +#------------------------------------------------------------------------------ -+ a254: f43e af44 beq\.w 90e0 ++ a254: f43e af44 beq\.w 90e0 + a258: 4c00 ldr r4, \[pc, #0\] ; \(a25c <_thumb\+0x58>\) + a25a: 4c01 ldr r4, \[pc, #4\] ; \(a260 <_thumb\+0x5c>\) +#------------------------------------------------------------------------------ @@ -2746083,15 +2760811,15 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ tbf1's .iplt entry +#------------------------------------------------------------------------------ -+ a264: f7fe ef54 blx 9110 ++ a264: f7fe ef54 blx 9110 +#------------------------------------------------------------------------------ +#------ thumb entry to tbf1's .iplt entry +#------------------------------------------------------------------------------ -+ a268: f7fe bf50 b\.w 910c ++ a268: f7fe bf50 b\.w 910c +#------------------------------------------------------------------------------ +#------ thumb entry to tbf1's .iplt entry +#------------------------------------------------------------------------------ -+ a26c: f43e af4e beq\.w 910c ++ a26c: f43e af4e beq\.w 910c + a270: 4c00 ldr r4, \[pc, #0\] ; \(a274 <_thumb\+0x70>\) + a272: 4c01 ldr r4, \[pc, #4\] ; \(a278 <_thumb\+0x74>\) +#------------------------------------------------------------------------------ @@ -2746105,15 +2760833,15 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ atf2's .plt entry +#------------------------------------------------------------------------------ -+ a27c: f7fe eecc blx 9018 ++ a27c: f7fe eecc blx 9018 +#------------------------------------------------------------------------------ +#------ thumb entry to atf2's .plt entry +#------------------------------------------------------------------------------ -+ a280: f7fe bec8 b\.w 9014 ++ a280: f7fe bec8 b\.w 9014 +#------------------------------------------------------------------------------ +#------ thumb entry to atf2's .plt entry +#------------------------------------------------------------------------------ -+ a284: f43e aec6 beq\.w 9014 ++ a284: f43e aec6 beq\.w 9014 + a288: 4c00 ldr r4, \[pc, #0\] ; \(a28c <_thumb\+0x88>\) + a28a: 4c01 ldr r4, \[pc, #4\] ; \(a290 <_thumb\+0x8c>\) +#------------------------------------------------------------------------------ @@ -2746127,15 +2760855,15 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ ttf2's .plt entry +#------------------------------------------------------------------------------ -+ a294: f7fe eece blx 9034 ++ a294: f7fe eece blx 9034 +#------------------------------------------------------------------------------ +#------ thumb entry to ttf2's .plt entry +#------------------------------------------------------------------------------ -+ a298: f7fe beca b\.w 9030 ++ a298: f7fe beca b\.w 9030 +#------------------------------------------------------------------------------ +#------ thumb entry to ttf2's .plt entry +#------------------------------------------------------------------------------ -+ a29c: f43e aec8 beq\.w 9030 ++ a29c: f43e aec8 beq\.w 9030 + a2a0: 4c00 ldr r4, \[pc, #0\] ; \(a2a4 <_thumb\+0xa0>\) + a2a2: 4c01 ldr r4, \[pc, #4\] ; \(a2a8 <_thumb\+0xa4>\) +#------------------------------------------------------------------------------ @@ -2746149,15 +2760877,15 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ abf2's .plt entry +#------------------------------------------------------------------------------ -+ a2ac: f7fe ef04 blx 90b8 ++ a2ac: f7fe ef04 blx 90b8 +#------------------------------------------------------------------------------ +#------ thumb entry to abf2's .plt entry +#------------------------------------------------------------------------------ -+ a2b0: f7fe bf00 b\.w 90b4 ++ a2b0: f7fe bf00 b\.w 90b4 +#------------------------------------------------------------------------------ +#------ thumb entry to abf2's .plt entry +#------------------------------------------------------------------------------ -+ a2b4: f43e aefe beq\.w 90b4 ++ a2b4: f43e aefe beq\.w 90b4 + a2b8: 4c00 ldr r4, \[pc, #0\] ; \(a2bc <_thumb\+0xb8>\) + a2ba: 4c01 ldr r4, \[pc, #4\] ; \(a2c0 <_thumb\+0xbc>\) +#------------------------------------------------------------------------------ @@ -2746171,15 +2760899,15 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ tbf2's .plt entry +#------------------------------------------------------------------------------ -+ a2c4: f7fe eebe blx 9044 ++ a2c4: f7fe eebe blx 9044 +#------------------------------------------------------------------------------ +#------ thumb entry to tbf2's .plt entry +#------------------------------------------------------------------------------ -+ a2c8: f7fe beba b\.w 9040 ++ a2c8: f7fe beba b\.w 9040 +#------------------------------------------------------------------------------ +#------ thumb entry to tbf2's .plt entry +#------------------------------------------------------------------------------ -+ a2cc: f43e aeb8 beq\.w 9040 ++ a2cc: f43e aeb8 beq\.w 9040 + a2d0: 4c00 ldr r4, \[pc, #0\] ; \(a2d4 <_thumb\+0xd0>\) + a2d2: 4c01 ldr r4, \[pc, #4\] ; \(a2d8 <_thumb\+0xd4>\) +#------------------------------------------------------------------------------ @@ -2746194,11 +2760922,11 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ thumb entry to atf3 +#------------------------------------------------------------------------------ -+ a2e0: f7fe bf1c b\.w 911c ++ a2e0: f7fe bf1c b\.w 911c +#------------------------------------------------------------------------------ +#------ thumb entry to atf3 +#------------------------------------------------------------------------------ -+ a2e4: f43e af1a beq\.w 911c ++ a2e4: f43e af1a beq\.w 911c + a2e8: 4c00 ldr r4, \[pc, #0\] ; \(a2ec <_thumb\+0xe8>\) + a2ea: 4c01 ldr r4, \[pc, #4\] ; \(a2f0 <_thumb\+0xec>\) +#------------------------------------------------------------------------------ @@ -2746269,15 +2760997,15 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ atf4's .plt entry +#------------------------------------------------------------------------------ -+ a33c: f7fe eeae blx 909c ++ a33c: f7fe eeae blx 909c +#------------------------------------------------------------------------------ +#------ thumb entry to atf4's .plt entry +#------------------------------------------------------------------------------ -+ a340: f7fe beaa b\.w 9098 ++ a340: f7fe beaa b\.w 9098 +#------------------------------------------------------------------------------ +#------ thumb entry to atf4's .plt entry +#------------------------------------------------------------------------------ -+ a344: f43e aea8 beq\.w 9098 ++ a344: f43e aea8 beq\.w 9098 + a348: 4c00 ldr r4, \[pc, #0\] ; \(a34c <_thumb\+0x148>\) + a34a: 4c01 ldr r4, \[pc, #4\] ; \(a350 <_thumb\+0x14c>\) +#------------------------------------------------------------------------------ @@ -2746291,15 +2761019,15 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ ttf4's .plt entry +#------------------------------------------------------------------------------ -+ a354: f7fe ee9a blx 908c ++ a354: f7fe ee9a blx 908c +#------------------------------------------------------------------------------ +#------ thumb entry to ttf4's .plt entry +#------------------------------------------------------------------------------ -+ a358: f7fe be96 b\.w 9088 ++ a358: f7fe be96 b\.w 9088 +#------------------------------------------------------------------------------ +#------ thumb entry to ttf4's .plt entry +#------------------------------------------------------------------------------ -+ a35c: f43e ae94 beq\.w 9088 ++ a35c: f43e ae94 beq\.w 9088 + a360: 4c00 ldr r4, \[pc, #0\] ; \(a364 <_thumb\+0x160>\) + a362: 4c01 ldr r4, \[pc, #4\] ; \(a368 <_thumb\+0x164>\) +#------------------------------------------------------------------------------ @@ -2746313,15 +2761041,15 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ abf4's .plt entry +#------------------------------------------------------------------------------ -+ a36c: f7fe ee7e blx 906c ++ a36c: f7fe ee7e blx 906c +#------------------------------------------------------------------------------ +#------ thumb entry to abf4's .plt entry +#------------------------------------------------------------------------------ -+ a370: f7fe be7a b\.w 9068 ++ a370: f7fe be7a b\.w 9068 +#------------------------------------------------------------------------------ +#------ thumb entry to abf4's .plt entry +#------------------------------------------------------------------------------ -+ a374: f43e ae78 beq\.w 9068 ++ a374: f43e ae78 beq\.w 9068 + a378: 4c00 ldr r4, \[pc, #0\] ; \(a37c <_thumb\+0x178>\) + a37a: 4c01 ldr r4, \[pc, #4\] ; \(a380 <_thumb\+0x17c>\) +#------------------------------------------------------------------------------ @@ -2746335,15 +2761063,15 @@ index 0000000..105b09b +#------------------------------------------------------------------------------ +#------ tbf4's .plt entry +#------------------------------------------------------------------------------ -+ a384: f7fe ee7a blx 907c ++ a384: f7fe ee7a blx 907c +#------------------------------------------------------------------------------ +#------ thumb entry to tbf4's .plt entry +#------------------------------------------------------------------------------ -+ a388: f7fe be76 b\.w 9078 ++ a388: f7fe be76 b\.w 9078 +#------------------------------------------------------------------------------ +#------ thumb entry to tbf4's .plt entry +#------------------------------------------------------------------------------ -+ a38c: f43e ae74 beq\.w 9078 ++ a38c: f43e ae74 beq\.w 9078 + a390: 4c00 ldr r4, \[pc, #0\] ; \(a394 <_thumb\+0x190>\) + a392: 4c01 ldr r4, \[pc, #4\] ; \(a398 <_thumb\+0x194>\) +#------------------------------------------------------------------------------ @@ -2746356,7 +2761084,7 @@ index 0000000..105b09b + a398: 00006d24 \.word 0x00006d24 diff --git a/ld/testsuite/ld-arm/ifunc-10.gd b/ld/testsuite/ld-arm/ifunc-10.gd new file mode 100644 -index 0000000..be3e09f +index 0000000..b35e10b --- /dev/null +++ b/ld/testsuite/ld-arm/ifunc-10.gd @@ -0,0 +1,188 @@ @@ -2746370,88 +2761098,88 @@ index 0000000..be3e09f +#------ 00010008: contains PC-relative offset of aaf1's .iplt entry +#------ 0001000c: contains atf1's .iplt entry +#------------------------------------------------------------------------------ -+ 10000 44332211 c4900000 bc90ffff d4900000 .* ++ 10000 (44332211 c4900000 bc90ffff d4900000|11223344 000090c4 ffff90bc 000090d4) .* +#------------------------------------------------------------------------------ +#------ 00010010: contains PC-relative offset of atf1's .iplt entry +#------ 00010014: contains abf1's .iplt entry +#------ 00010018: contains PC-relative offset of abf1's .iplt entry +#------ 0001001c: contains taf1's .iplt entry +#------------------------------------------------------------------------------ -+ 10010 c490ffff e4900000 cc90ffff f0900000 .* ++ 10010 (c490ffff e4900000 cc90ffff f0900000|ffff90c4 000090e4 ffff90cc 000090f0) .* +#------------------------------------------------------------------------------ +#------ 00010020: contains PC-relative offset of taf1's .iplt entry +#------ 00010024: contains ttf1's .iplt entry +#------ 00010028: contains PC-relative offset of ttf1's .iplt entry +#------ 0001002c: contains tbf1's .iplt entry +#------------------------------------------------------------------------------ -+ 10020 d090ffff 00910000 d890ffff 10910000 .* ++ 10020 (d090ffff 00910000 d890ffff 10910000|ffff90d0 00009100 ffff90d8 00009110) .* +#------------------------------------------------------------------------------ +#------ 00010030: contains PC-relative offset of tbf1's .iplt entry +#------ 00010034: contains aaf2's .plt entry +#------ 00010038: contains PC-relative offset of aaf2's .plt entry +#------ 0001003c: contains atf2's .plt entry +#------------------------------------------------------------------------------ -+ 10030 e090ffff 5c900000 2490ffff 18900000 .* ++ 10030 (e090ffff 5c900000 2490ffff 18900000|ffff90e0 0000905c ffff9024 00009018) .* +#------------------------------------------------------------------------------ +#------ 00010040: contains PC-relative offset of atf2's .plt entry +#------ 00010044: contains abf2's .plt entry +#------ 00010048: contains PC-relative offset of abf2's .plt entry +#------ 0001004c: contains taf2's .plt entry +#------------------------------------------------------------------------------ -+ 10040 d88fffff b8900000 7090ffff 50900000 .* ++ 10040 (d88fffff b8900000 7090ffff 50900000|ffff8fd8 000090b8 ffff9070 00009050) .* +#------------------------------------------------------------------------------ +#------ 00010050: contains PC-relative offset of taf2's .plt entry +#------ 00010054: contains ttf2's .plt entry +#------ 00010058: contains PC-relative offset of ttf2's .plt entry +#------ 0001005c: contains tbf2's .plt entry +#------------------------------------------------------------------------------ -+ 10050 0090ffff 34900000 dc8fffff 44900000 .* ++ 10050 (0090ffff 34900000 dc8fffff 44900000|ffff9000 00009034 ffff8fdc 00009044) .* +#------------------------------------------------------------------------------ +#------ 00010060: contains PC-relative offset of tbf2's .plt entry +#------ 00010064: contains aaf3 +#------ 00010068: contains PC-relative offset of aaf3 +#------ 0001006c: contains atf3 +#------------------------------------------------------------------------------ -+ 10060 e48fffff 68910000 0091ffff 20910000 .* ++ 10060 (e48fffff 68910000 0091ffff 20910000|ffff8fe4 00009168 ffff9100 00009120) .* +#------------------------------------------------------------------------------ +#------ 00010070: contains PC-relative offset of atf3 +#------ 00010074: contains abf3 +#------ 00010078: contains PC-relative offset of abf3 +#------ 0001007c: contains taf3 +#------------------------------------------------------------------------------ -+ 10070 b090ffff 30910000 b890ffff 5c910000 .* ++ 10070 (b090ffff 30910000 b890ffff 5c910000|ffff90b0 00009130 ffff90b8 0000915c) .* +#------------------------------------------------------------------------------ +#------ 00010080: contains PC-relative offset of taf3 +#------ 00010084: contains ttf3 +#------ 00010088: contains PC-relative offset of ttf3 +#------ 0001008c: contains tbf3 +#------------------------------------------------------------------------------ -+ 10080 dc90ffff 40910000 b890ffff 50910000 .* ++ 10080 (dc90ffff 40910000 b890ffff 50910000|ffff90dc 00009140 ffff90b8 00009150) .* +#------------------------------------------------------------------------------ +#------ 00010090: contains PC-relative offset of tbf3 +#------ 00010094: contains aaf4's .plt entry +#------ 00010098: contains PC-relative offset of aaf4's .plt entry +#------ 0001009c: contains atf4's .plt entry +#------------------------------------------------------------------------------ -+ 10090 c090ffff 24900000 8c8fffff 9c900000 .* ++ 10090 (c090ffff 24900000 8c8fffff 9c900000|ffff90c0 00009024 ffff8f8c 0000909c) .* +#------------------------------------------------------------------------------ +#------ 000100a0: contains PC-relative offset of atf4's .plt entry +#------ 000100a4: contains abf4's .plt entry +#------ 000100a8: contains PC-relative offset of abf4's .plt entry +#------ 000100ac: contains taf4's .plt entry +#------------------------------------------------------------------------------ -+ 100a0 fc8fffff 6c900000 c48fffff a8900000 .* ++ 100a0 (fc8fffff 6c900000 c48fffff a8900000|ffff8ffc 0000906c ffff8fc4 000090a8) .* +#------------------------------------------------------------------------------ +#------ 000100b0: contains PC-relative offset of taf4's .plt entry +#------ 000100b4: contains ttf4's .plt entry +#------ 000100b8: contains PC-relative offset of ttf4's .plt entry +#------ 000100bc: contains tbf4's .plt entry +#------------------------------------------------------------------------------ -+ 100b0 f88fffff 8c900000 d48fffff 7c900000 .* ++ 100b0 (f88fffff 8c900000 d48fffff 7c900000|ffff8ff8 0000908c ffff8fd4 0000907c) .* +#------------------------------------------------------------------------------ +#------ 000100c0: contains PC-relative offset of tbf4's .plt entry +#------------------------------------------------------------------------------ -+ 100c0 bc8fffff .* ++ 100c0 (bc8fffff|ffff8fbc) .* +Contents of section \.got: +#------------------------------------------------------------------------------ +#------ 00011000: .got.plt @@ -2746459,91 +2761187,91 @@ index 0000000..be3e09f +#------ 00011008: reserved .got.plt entry +#------ 0001100c: atf2's .got.plt entry [R_ARM_JUMP_SLOT] +#------------------------------------------------------------------------------ -+ 11000 00200100 00000000 00000000 00900000 .* ++ 11000 (00200100 00000000 00000000 00900000|00012000 00000000 00000000 00009000) .* +#------------------------------------------------------------------------------ +#------ 00011010: aaf4's .got.plt entry [R_ARM_JUMP_SLOT] +#------ 00011014: ttf2's .got.plt entry [R_ARM_JUMP_SLOT] +#------ 00011018: tbf2's .got.plt entry [R_ARM_JUMP_SLOT] +#------ 0001101c: taf2's .got.plt entry [R_ARM_JUMP_SLOT] +#------------------------------------------------------------------------------ -+ 11010 00900000 00900000 00900000 00900000 .* ++ 11010 (00900000 00900000 00900000 00900000|00009000 00009000 00009000 00009000) .* +#------------------------------------------------------------------------------ +#------ 00011020: aaf2's .got.plt entry [R_ARM_JUMP_SLOT] +#------ 00011024: abf4's .got.plt entry [R_ARM_JUMP_SLOT] +#------ 00011028: tbf4's .got.plt entry [R_ARM_JUMP_SLOT] +#------ 0001102c: ttf4's .got.plt entry [R_ARM_JUMP_SLOT] +#------------------------------------------------------------------------------ -+ 11020 00900000 00900000 00900000 00900000 .* ++ 11020 (00900000 00900000 00900000 00900000|00009000 00009000 00009000 00009000) .* +#------------------------------------------------------------------------------ +#------ 00011030: atf4's .got.plt entry [R_ARM_JUMP_SLOT] +#------ 00011034: taf4's .got.plt entry [R_ARM_JUMP_SLOT] +#------ 00011038: abf2's .got.plt entry [R_ARM_JUMP_SLOT] +#------ 0001103c: aaf1's .igot.plt entry [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 11030 00900000 00900000 00900000 00a00000 .* ++ 11030 (00900000 00900000 00900000 00a00000|00009000 00009000 00009000 0000a000) .* +#------------------------------------------------------------------------------ +#------ 00011040: atf1's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011044: abf1's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011048: taf1's .igot.plt entry [R_ARM_IRELATIVE] +#------ 0001104c: ttf1's .igot.plt entry [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 11040 04a00000 08a00000 0da00000 0fa00000 .* ++ 11040 (04a00000 08a00000 0da00000 0fa00000|0000a004 0000a008 0000a00d 0000a00f) .* +#------------------------------------------------------------------------------ +#------ 00011050: tbf1's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011054: atf3's .igot.plt pointer to 0xa018 [R_ARM_IRELATIVE] +#------ 00011058: abf3's .igot.plt pointer to 0xa01c [R_ARM_IRELATIVE] +#------ 0001105c: ttf3's .igot.plt pointer to 0xa023 [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 11050 11a00000 18a00000 1ca00000 23a00000 .* ++ 11050 (11a00000 18a00000 1ca00000 23a00000|0000a011 0000a018 0000a01c 0000a023) .* +#------------------------------------------------------------------------------ +#------ 00011060: tbf3's .igot.plt pointer to 0xa025 [R_ARM_IRELATIVE] +#------ 00011064: taf3's .igot.plt pointer to 0xa021 [R_ARM_IRELATIVE] +#------ 00011068: aaf3's .igot.plt pointer to 0xa014 [R_ARM_IRELATIVE] +#------ 0001106c: .got entry for foo +#------------------------------------------------------------------------------ -+ 11060 25a00000 21a00000 14a00000 00000100 .* ++ 11060 (25a00000 21a00000 14a00000 00000100|0000a025 0000a021 0000a014 00010000) .* +#------------------------------------------------------------------------------ +#------ 00011070: .got entry for aaf1's .iplt entry +#------ 00011074: .got entry for atf1's .iplt entry +#------ 00011078: .got entry for abf1's .iplt entry +#------ 0001107c: .got entry for taf1's .iplt entry +#------------------------------------------------------------------------------ -+ 11070 c4900000 d4900000 e4900000 f0900000 .* ++ 11070 (c4900000 d4900000 e4900000 f0900000|000090c4 000090d4 000090e4 000090f0) .* +#------------------------------------------------------------------------------ +#------ 00011080: .got entry for ttf1's .iplt entry +#------ 00011084: .got entry for tbf1's .iplt entry +#------ 00011088: .got entry for foo +#------ 0001108c: .got entry for atf2 [R_ARM_GLOB_DAT] +#------------------------------------------------------------------------------ -+ 11080 00910000 10910000 00000100 00000000 .* ++ 11080 (00910000 10910000 00000100|00009100 00009110 00010000) 00000000 .* +#------------------------------------------------------------------------------ +#------ 00011090: .got entry for aaf4 [R_ARM_GLOB_DAT] +#------ 00011094: .got entry for ttf2 [R_ARM_GLOB_DAT] +#------ 00011098: .got entry for tbf2 [R_ARM_GLOB_DAT] +#------ 0001109c: .got entry for atf3 +#------------------------------------------------------------------------------ -+ 11090 00000000 00000000 00000000 20910000 .* ++ 11090 00000000 00000000 00000000 (20910000|00009120) .* +#------------------------------------------------------------------------------ +#------ 000110a0: .got entry for abf3 +#------ 000110a4: .got entry for taf2 [R_ARM_GLOB_DAT] +#------ 000110a8: .got entry for aaf2 [R_ARM_GLOB_DAT] +#------ 000110ac: .got entry for ttf3 +#------------------------------------------------------------------------------ -+ 110a0 30910000 00000000 00000000 40910000 .* ++ 110a0 (30910000 00000000 00000000 40910000|00009130 00000000 00000000 00009140) .* +#------------------------------------------------------------------------------ +#------ 000110b0: .got entry for tbf3 +#------ 000110b4: .got entry for taf3 +#------ 000110b8: .got entry for abf4 [R_ARM_GLOB_DAT] +#------ 000110bc: .got entry for tbf4 [R_ARM_GLOB_DAT] +#------------------------------------------------------------------------------ -+ 110b0 50910000 5c910000 00000000 00000000 .* ++ 110b0 (50910000 5c910000|00009150 0000915c) 00000000 00000000 .* +#------------------------------------------------------------------------------ +#------ 000110c0: .got entry for ttf4 [R_ARM_GLOB_DAT] +#------ 000110c4: .got entry for aaf3 +#------ 000110c8: .got entry for atf4 [R_ARM_GLOB_DAT] +#------ 000110cc: .got entry for taf4 [R_ARM_GLOB_DAT] +#------------------------------------------------------------------------------ -+ 110c0 00000000 68910000 00000000 00000000 .* ++ 110c0 00000000 (68910000|00009168) 00000000 00000000 .* +#------------------------------------------------------------------------------ +#------ 000110d0: .got entry for abf2 [R_ARM_GLOB_DAT] +#------------------------------------------------------------------------------ @@ -2746795,7 +2761523,7 @@ index 0000000..89a7530 + a064: 00006fc4 \.word 0x00006fc4 diff --git a/ld/testsuite/ld-arm/ifunc-11.gd b/ld/testsuite/ld-arm/ifunc-11.gd new file mode 100644 -index 0000000..aea1583 +index 0000000..b62524c --- /dev/null +++ b/ld/testsuite/ld-arm/ifunc-11.gd @@ -0,0 +1,29 @@ @@ -2746806,7 +2761534,7 @@ index 0000000..aea1583 +#------------------------------------------------------------------------------ +#------ 00010000: foo +#------------------------------------------------------------------------------ -+ 10000 44332211 00800000 30800000 .* ++ 10000 (44332211 00800000 30800000|11223344 00008000 00008030) .* +Contents of section \.got: +#------------------------------------------------------------------------------ +#------ 00011000: .got.plt @@ -2746814,20 +2761542,20 @@ index 0000000..aea1583 +#------ 00011008: reserved .got.plt entry +#------ 0001100c: .got entry for foo +#------------------------------------------------------------------------------ -+ 11000 00000000 00000000 00000000 00000100 .* ++ 11000 00000000 00000000 00000000 (00000100|00010000) .* +#------------------------------------------------------------------------------ +#------ 00011010: .got entry for f1 [R_ARM_IRELATIVE] +#------ 00011014: .got entry for f1t [R_ARM_IRELATIVE] +#------ 00011018: .got entry for foo +#------ 0001101c: .got entry for f2t [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 11010 00a00000 0da00000 00000100 0fa00000 .* ++ 11010 (00a00000 0da00000 00000100 0fa00000|0000a000 0000a00d 00010000 0000a00f) .* +#------------------------------------------------------------------------------ +#------ 00011020: .got entry for f3 [R_ARM_IRELATIVE] +#------ 00011024: .got entry for f2 [R_ARM_IRELATIVE] +#------ 00011028: .got entry for f3t [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 11020 08a00000 04a00000 11a00000 .* ++ 11020 (08a00000 04a00000 11a00000|0000a008 0000a004 0000a011) .* diff --git a/ld/testsuite/ld-arm/ifunc-11.rd b/ld/testsuite/ld-arm/ifunc-11.rd new file mode 100644 index 0000000..82ce9b7 @@ -2747006,7 +2761734,7 @@ index 0000000..89a7530 + a064: 00006fc4 \.word 0x00006fc4 diff --git a/ld/testsuite/ld-arm/ifunc-12.gd b/ld/testsuite/ld-arm/ifunc-12.gd new file mode 100644 -index 0000000..721c315 +index 0000000..7f1c0ef --- /dev/null +++ b/ld/testsuite/ld-arm/ifunc-12.gd @@ -0,0 +1,39 @@ @@ -2747020,14 +2761748,14 @@ index 0000000..721c315 +#------ 00010008: f2 [R_ARM_ABS32] +#------ 0001000c: contains f3 [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 10000 44332211 00a00000 00000000 08a00000 .* ++ 10000 (44332211 00a00000 00000000 08a00000|11223344 0000a000 00000000 0000a008) .* +#------------------------------------------------------------------------------ +#------ 00010010: contains f1t [R_ARM_IRELATIVE] +#------ 00010014: f2t [R_ARM_ABS32] +#------ 00010018: contains f3t [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 10010 0da00000 00000000 11a00000 80800000 .* -+ 10020 80800000 .* ++ 10010 (0da00000 00000000 11a00000 80800000|0000a00d 00000000 0000a011 00008080) .* ++ 10020 (80800000|00008080) .* +Contents of section \.got: +#------------------------------------------------------------------------------ +#------ 00011000: .got.plt @@ -2747035,20 +2761763,20 @@ index 0000000..721c315 +#------ 00011008: reserved .got.plt entry +#------ 0001100c: .got entry for foo [R_ARM_RELATIVE] +#------------------------------------------------------------------------------ -+ 11000 00200100 00000000 00000000 00000100 .* ++ 11000 (00200100 00000000 00000000 00000100|00012000 00000000 00000000 00010000) .* +#------------------------------------------------------------------------------ +#------ 00011010: .got entry for f1 [R_ARM_IRELATIVE] +#------ 00011014: .got entry for f1t [R_ARM_IRELATIVE] +#------ 00011018: .got entry for foo [R_ARM_RELATIVE] +#------ 0001101c: .got entry for f2t [R_ARM_GLOB_DAT] +#------------------------------------------------------------------------------ -+ 11010 00a00000 0da00000 00000100 00000000 .* ++ 11010 (00a00000 0da00000 00000100|0000a000 0000a00d 00010000) 00000000 .* +#------------------------------------------------------------------------------ +#------ 00011020: .got entry for f3 [R_ARM_IRELATIVE] +#------ 00011024: .got entry for f2 [R_ARM_GLOB_DAT] +#------ 00011028: .got entry for f3t [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 11020 08a00000 00000000 11a00000 .* ++ 11020 (08a00000 00000000 11a00000|0000a008 00000000 0000a011) .* diff --git a/ld/testsuite/ld-arm/ifunc-12.rd b/ld/testsuite/ld-arm/ifunc-12.rd new file mode 100644 index 0000000..c5d62c1 @@ -2747235,7 +2761963,7 @@ index 0000000..d5df382 + a05c: 00006fcc \.word 0x00006fcc diff --git a/ld/testsuite/ld-arm/ifunc-13.gd b/ld/testsuite/ld-arm/ifunc-13.gd new file mode 100644 -index 0000000..9b5dbcb +index 0000000..43f8aad --- /dev/null +++ b/ld/testsuite/ld-arm/ifunc-13.gd @@ -0,0 +1,29 @@ @@ -2747246,7 +2761974,7 @@ index 0000000..9b5dbcb +#------------------------------------------------------------------------------ +#------ 00010000: foo +#------------------------------------------------------------------------------ -+ 10000 44332211 30800000 30800000 .* ++ 10000 (44332211 30800000 30800000|11223344 00008030 00008030) .* +Contents of section \.got: +#------------------------------------------------------------------------------ +#------ 00011000: .got.plt @@ -2747254,20 +2761982,20 @@ index 0000000..9b5dbcb +#------ 00011008: reserved .got.plt entry +#------ 0001100c: .got entry for foo +#------------------------------------------------------------------------------ -+ 11000 00200100 00000000 00000000 00000100 .* ++ 11000 (00200100 00000000 00000000 00000100|00012000 00000000 00000000 00010000) .* +#------------------------------------------------------------------------------ +#------ 00011010: .got entry for f1 [R_ARM_IRELATIVE] +#------ 00011014: .got entry for f1t [R_ARM_IRELATIVE] +#------ 00011018: .got entry for foo +#------ 0001101c: .got entry for f2t [R_ARM_GLOB_DAT] +#------------------------------------------------------------------------------ -+ 11010 00a00000 09a00000 00000100 00000000 .* ++ 11010 (00a00000 09a00000 00000100 00000000|0000a000 0000a009 00010000 00000000) .* +#------------------------------------------------------------------------------ +#------ 00011020: .got entry for f3 [R_ARM_IRELATIVE] +#------ 00011024: .got entry for f2 [R_ARM_GLOB_DAT] +#------ 00011028: .got entry for f3t [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 11020 04a00000 00000000 0ba00000 .* ++ 11020 (04a00000 00000000 0ba00000|0000a004 00000000 0000a00b) .* diff --git a/ld/testsuite/ld-arm/ifunc-13.rd b/ld/testsuite/ld-arm/ifunc-13.rd new file mode 100644 index 0000000..c58ab8a @@ -2747341,17 +2762069,17 @@ index 0000000..467f06f + .word __irel_end diff --git a/ld/testsuite/ld-arm/ifunc-14.dd b/ld/testsuite/ld-arm/ifunc-14.dd new file mode 100644 -index 0000000..861f687 +index 0000000..cbad1c8 --- /dev/null +++ b/ld/testsuite/ld-arm/ifunc-14.dd -@@ -0,0 +1,100 @@ +@@ -0,0 +1,102 @@ + +.* + + +Disassembly of section \.plt: + -+00009000 <\.plt>: ++00009000 : + 9000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) + 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 <__irel_end\+0xff0> + 9008: e08fe00e add lr, pc, lr @@ -2747363,12 +2762091,14 @@ index 0000000..861f687 +#------------------------------------------------------------------------------ +#------ f2t's .plt entry +#------------------------------------------------------------------------------ ++00009014 : + 9014: e28fc600 add ip, pc, #0, 12 + 9018: e28cca07 add ip, ip, #28672 ; 0x7000 + 901c: e5bcfff0 ldr pc, \[ip, #4080\]! ; 0xff0 +#------------------------------------------------------------------------------ +#------ f2's .plt entry +#------------------------------------------------------------------------------ ++00009020 : + 9020: e28fc600 add ip, pc, #0, 12 + 9024: e28cca07 add ip, ip, #28672 ; 0x7000 + 9028: e5bcffe8 ldr pc, \[ip, #4072\]! ; 0xfe8 @@ -2747447,7 +2762177,7 @@ index 0000000..861f687 + a040: fffff010 \.word 0xfffff010 diff --git a/ld/testsuite/ld-arm/ifunc-14.gd b/ld/testsuite/ld-arm/ifunc-14.gd new file mode 100644 -index 0000000..c054e6b +index 0000000..40479cc --- /dev/null +++ b/ld/testsuite/ld-arm/ifunc-14.gd @@ -0,0 +1,27 @@ @@ -2747458,7 +2762188,7 @@ index 0000000..c054e6b +#------------------------------------------------------------------------------ +#------ 00010000: foo +#------------------------------------------------------------------------------ -+ 10000 44332211 00800000 20800000 .* ++ 10000 (44332211 00800000 20800000|11223344 00008000 00008020) .* +Contents of section \.got: +#------------------------------------------------------------------------------ +#------ 00011000: .got.plt @@ -2747466,21 +2762196,21 @@ index 0000000..c054e6b +#------ 00011008: reserved .got.plt entry +#------ 0001100c: f2t's .got.plt entry [R_ARM_JUMP_SLOT] +#------------------------------------------------------------------------------ -+ 11000 00200100 00000000 00000000 00900000 .* ++ 11000 (00200100 00000000 00000000 00900000|00012000 00000000 00000000 00009000) .* +#------------------------------------------------------------------------------ +#------ 00011010: f2's .got.plt entry [R_ARM_JUMP_SLOT] +#------ 00011014: f1's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011018: f1t's .igot.plt entry [R_ARM_IRELATIVE] +#------ 0001101c: f3's .igot.plt pointer to 0xa004 [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 11010 00900000 00a00000 09a00000 04a00000 .* ++ 11010 (00900000 00a00000 09a00000 04a00000|00009000 0000a000 0000a009 0000a004) .* +#------------------------------------------------------------------------------ +#------ 00011020: f3t's .igot.plt pointer to 0xa00b [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 11020 0ba00000 .* ++ 11020 (0ba00000|0000a00b) .* diff --git a/ld/testsuite/ld-arm/ifunc-14.rd b/ld/testsuite/ld-arm/ifunc-14.rd new file mode 100644 -index 0000000..59ea29b +index 0000000..9c44092 --- /dev/null +++ b/ld/testsuite/ld-arm/ifunc-14.rd @@ -0,0 +1,12 @@ @@ -2747494,8 +2762224,8 @@ index 0000000..59ea29b + +Relocation section '\.rel\.plt' at offset 0x8020 contains 2 entries: + Offset Info Type Sym\.Value Sym\. Name -+0001100c ......16 R_ARM_JUMP_SLOT 00009014 f2t -+00011010 ......16 R_ARM_JUMP_SLOT 00009020 f2 ++0001100c ......16 R_ARM_JUMP_SLOT 00000000 f2t ++00011010 ......16 R_ARM_JUMP_SLOT 00000000 f2 diff --git a/ld/testsuite/ld-arm/ifunc-14.s b/ld/testsuite/ld-arm/ifunc-14.s new file mode 100644 index 0000000..8a166af @@ -2747551,17 +2762281,17 @@ index 0000000..8a166af + .word __irel_end diff --git a/ld/testsuite/ld-arm/ifunc-15.dd b/ld/testsuite/ld-arm/ifunc-15.dd new file mode 100644 -index 0000000..d764841 +index 0000000..f23e8e8 --- /dev/null +++ b/ld/testsuite/ld-arm/ifunc-15.dd -@@ -0,0 +1,100 @@ +@@ -0,0 +1,102 @@ + +.* + + +Disassembly of section \.plt: + -+00009000 <\.plt>: ++00009000 : + 9000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) + 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 <__irel_end\+0xff0> + 9008: e08fe00e add lr, pc, lr @@ -2747573,12 +2762303,14 @@ index 0000000..d764841 +#------------------------------------------------------------------------------ +#------ f2t's .plt entry +#------------------------------------------------------------------------------ ++00009014 : + 9014: e28fc600 add ip, pc, #0, 12 + 9018: e28cca07 add ip, ip, #28672 ; 0x7000 + 901c: e5bcfff0 ldr pc, \[ip, #4080\]! ; 0xff0 +#------------------------------------------------------------------------------ +#------ f2's .plt entry +#------------------------------------------------------------------------------ ++00009020 : + 9020: e28fc600 add ip, pc, #0, 12 + 9024: e28cca07 add ip, ip, #28672 ; 0x7000 + 9028: e5bcffe8 ldr pc, \[ip, #4072\]! ; 0xfe8 @@ -2747657,7 +2762389,7 @@ index 0000000..d764841 + a040: 00009050 \.word 0x00009050 diff --git a/ld/testsuite/ld-arm/ifunc-15.gd b/ld/testsuite/ld-arm/ifunc-15.gd new file mode 100644 -index 0000000..c054e6b +index 0000000..40479cc --- /dev/null +++ b/ld/testsuite/ld-arm/ifunc-15.gd @@ -0,0 +1,27 @@ @@ -2747668,7 +2762400,7 @@ index 0000000..c054e6b +#------------------------------------------------------------------------------ +#------ 00010000: foo +#------------------------------------------------------------------------------ -+ 10000 44332211 00800000 20800000 .* ++ 10000 (44332211 00800000 20800000|11223344 00008000 00008020) .* +Contents of section \.got: +#------------------------------------------------------------------------------ +#------ 00011000: .got.plt @@ -2747676,18 +2762408,18 @@ index 0000000..c054e6b +#------ 00011008: reserved .got.plt entry +#------ 0001100c: f2t's .got.plt entry [R_ARM_JUMP_SLOT] +#------------------------------------------------------------------------------ -+ 11000 00200100 00000000 00000000 00900000 .* ++ 11000 (00200100 00000000 00000000 00900000|00012000 00000000 00000000 00009000) .* +#------------------------------------------------------------------------------ +#------ 00011010: f2's .got.plt entry [R_ARM_JUMP_SLOT] +#------ 00011014: f1's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011018: f1t's .igot.plt entry [R_ARM_IRELATIVE] +#------ 0001101c: f3's .igot.plt pointer to 0xa004 [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 11010 00900000 00a00000 09a00000 04a00000 .* ++ 11010 (00900000 00a00000 09a00000 04a00000|00009000 0000a000 0000a009 0000a004) .* +#------------------------------------------------------------------------------ +#------ 00011020: f3t's .igot.plt pointer to 0xa00b [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 11020 0ba00000 .* ++ 11020 (0ba00000|0000a00b) .* diff --git a/ld/testsuite/ld-arm/ifunc-15.rd b/ld/testsuite/ld-arm/ifunc-15.rd new file mode 100644 index 0000000..59ea29b @@ -2747855,7 +2762587,7 @@ index 0000000..16c2a97 + a044: 0000903c \.word 0x0000903c diff --git a/ld/testsuite/ld-arm/ifunc-16.gd b/ld/testsuite/ld-arm/ifunc-16.gd new file mode 100644 -index 0000000..7c4e820 +index 0000000..b3a1902 --- /dev/null +++ b/ld/testsuite/ld-arm/ifunc-16.gd @@ -0,0 +1,27 @@ @@ -2747866,7 +2762598,7 @@ index 0000000..7c4e820 +#------------------------------------------------------------------------------ +#------ 00010000: foo +#------------------------------------------------------------------------------ -+ 10000 44332211 00800000 30800000 .* ++ 10000 (44332211 00800000 30800000|11223344 00008000 00008030) .* +Contents of section \.got: +#------------------------------------------------------------------------------ +#------ 00011000: .got.plt @@ -2747874,18 +2762606,18 @@ index 0000000..7c4e820 +#------ 00011008: reserved .got.plt entry +#------ 0001100c: f1's .igot.plt entry [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 11000 00200100 00000000 00000000 00a00000 .* ++ 11000 (00200100 00000000 00000000 00a00000|00012000 00000000 00000000 0000a000) .* +#------------------------------------------------------------------------------ +#------ 00011010: f1t's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011014: f2t's .igot.plt pointer to 0xa00f [R_ARM_IRELATIVE] +#------ 00011018: f3's .igot.plt pointer to 0xa008 [R_ARM_IRELATIVE] +#------ 0001101c: f2's .igot.plt pointer to 0xa004 [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 11010 0da00000 0fa00000 08a00000 04a00000 .* ++ 11010 (0da00000 0fa00000 08a00000 04a00000|0000a00d 0000a00f 0000a008 0000a004) .* +#------------------------------------------------------------------------------ +#------ 00011020: f3t's .igot.plt pointer to 0xa011 [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 11020 11a00000 .* ++ 11020 (11a00000|0000a011) .* diff --git a/ld/testsuite/ld-arm/ifunc-16.rd b/ld/testsuite/ld-arm/ifunc-16.rd new file mode 100644 index 0000000..7296316 @@ -2747989,7 +2762721,7 @@ index 0000000..ee5cd05 + a008: 00000010 \.word 0x00000010 diff --git a/ld/testsuite/ld-arm/ifunc-17.gd b/ld/testsuite/ld-arm/ifunc-17.gd new file mode 100644 -index 0000000..dadfc9e +index 0000000..41e3adf --- /dev/null +++ b/ld/testsuite/ld-arm/ifunc-17.gd @@ -0,0 +1,10 @@ @@ -2748001,8 +2762733,8 @@ index 0000000..dadfc9e +#------ 0001100c: 0xa001 (appfunc1) +#------ 00011010: 0xa003 (appfunc2) +#------------------------------------------------------------------------------ -+ 11000 00000000 00000000 00000000 01a00000 .* -+ 11010 03a00000 .* ++ 11000 00000000 00000000 00000000 (01a00000|0000a001) .* ++ 11010 (03a00000|0000a003) .* diff --git a/ld/testsuite/ld-arm/ifunc-17.rd b/ld/testsuite/ld-arm/ifunc-17.rd new file mode 100644 index 0000000..b167f45 @@ -2748497,7 +2763229,7 @@ index 0000000..f6d57fa + a24c: 00006e00 \.word 0x00006e00 diff --git a/ld/testsuite/ld-arm/ifunc-2.gd b/ld/testsuite/ld-arm/ifunc-2.gd new file mode 100644 -index 0000000..0917a75 +index 0000000..864d902 --- /dev/null +++ b/ld/testsuite/ld-arm/ifunc-2.gd @@ -0,0 +1,48 @@ @@ -2748508,7 +2763240,7 @@ index 0000000..0917a75 +#------------------------------------------------------------------------------ +#------ 00010000: foo +#------------------------------------------------------------------------------ -+ 10000 44332211 .* ++ 10000 (44332211|11223344) .* +Contents of section \.got: +#------------------------------------------------------------------------------ +#------ 00011000: .got.plt @@ -2748516,39 +2763248,39 @@ index 0000000..0917a75 +#------ 00011008: reserved .got.plt entry +#------ 0001100c: f1's .igot.plt entry [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 11000 00000000 00000000 00000000 00a00000 .* ++ 11000 00000000 00000000 00000000 (00a00000|0000a000) .* +#------------------------------------------------------------------------------ +#------ 00011010: f2's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011014: f3's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011018: f4's .igot.plt entry [R_ARM_IRELATIVE] +#------ 0001101c: f7's .igot.plt pointer to 0xa018 [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 11010 05a00000 08a00000 0da00000 18a00000 .* ++ 11010 (05a00000 08a00000 0da00000 18a00000|0000a005 0000a008 0000a00d 0000a018) .* +#------------------------------------------------------------------------------ +#------ 00011020: f5's .igot.plt pointer to 0xa010 [R_ARM_IRELATIVE] +#------ 00011024: f8's .igot.plt pointer to 0xa01d [R_ARM_IRELATIVE] +#------ 00011028: f6's .igot.plt pointer to 0xa015 [R_ARM_IRELATIVE] +#------ 0001102c: .got entry for foo +#------------------------------------------------------------------------------ -+ 11020 10a00000 1da00000 15a00000 00000100 .* ++ 11020 (10a00000 1da00000 15a00000 00000100|0000a010 0000a01d 0000a015 00010000) .* +#------------------------------------------------------------------------------ +#------ 00011030: .got entry for f1's .iplt entry +#------ 00011034: .got entry for f2's .iplt entry +#------ 00011038: .got entry for f3's .iplt entry +#------ 0001103c: .got entry for f4's .iplt entry +#------------------------------------------------------------------------------ -+ 11030 00900000 0c900000 1c900000 2c900000 .* ++ 11030 (00900000 0c900000 1c900000 2c900000|00009000 0000900c 0000901c 0000902c) .* +#------------------------------------------------------------------------------ +#------ 00011040: .got entry for foo +#------ 00011044: .got entry for f7 +#------ 00011048: .got entry for f5 +#------ 0001104c: .got entry for f8 +#------------------------------------------------------------------------------ -+ 11040 00000100 3c900000 48900000 58900000 .* ++ 11040 (00000100 3c900000 48900000 58900000|00010000 0000903c 00009048 00009058) .* +#------------------------------------------------------------------------------ +#------ 00011050: .got entry for f6 +#------------------------------------------------------------------------------ -+ 11050 64900000 .* ++ 11050 (64900000|00009064) .* diff --git a/ld/testsuite/ld-arm/ifunc-2.rd b/ld/testsuite/ld-arm/ifunc-2.rd new file mode 100644 index 0000000..7bbabf4 @@ -2748650,19 +2763382,19 @@ index 0000000..8834fbc + .word 0x11223344 diff --git a/ld/testsuite/ld-arm/ifunc-3.dd b/ld/testsuite/ld-arm/ifunc-3.dd new file mode 100644 -index 0000000..a1fb37a +index 0000000..b267bf1 --- /dev/null +++ b/ld/testsuite/ld-arm/ifunc-3.dd -@@ -0,0 +1,126 @@ +@@ -0,0 +1,127 @@ + +.* + + +Disassembly of section \.plt: + -+00009000 <\.plt>: ++00009000 : + 9000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) -+ 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 ++ 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 + 9008: e08fe00e add lr, pc, lr + 900c: e5bef008 ldr pc, \[lr, #8\]! +#------------------------------------------------------------------------------ @@ -2748672,6 +2763404,7 @@ index 0000000..a1fb37a +#------------------------------------------------------------------------------ +#------ f2's .plt entry +#------------------------------------------------------------------------------ ++00009014 : + 9014: e28fc600 add ip, pc, #0, 12 + 9018: e28cca07 add ip, ip, #28672 ; 0x7000 + 901c: e5bcfff0 ldr pc, \[ip, #4080\]! ; 0xff0 @@ -2748727,7 +2763460,7 @@ index 0000000..a1fb37a +#------------------------------------------------------------------------------ +#------ f1's .iplt entry +#------------------------------------------------------------------------------ -+ a024: ebfffbfd bl 9020 ++ a024: ebfffbfd bl 9020 + a028: e59f4000 ldr r4, \[pc\] ; a030 + a02c: e59f4000 ldr r4, \[pc\] ; a034 +#------------------------------------------------------------------------------ @@ -2748741,7 +2763474,7 @@ index 0000000..a1fb37a +#------------------------------------------------------------------------------ +#------ f2's .plt entry +#------------------------------------------------------------------------------ -+ a038: ebfffbf5 bl 9014 ++ a038: ebfffbf5 bl 9014 + a03c: e59f4000 ldr r4, \[pc\] ; a044 + a040: e59f4000 ldr r4, \[pc\] ; a048 +#------------------------------------------------------------------------------ @@ -2748755,7 +2763488,7 @@ index 0000000..a1fb37a +#------------------------------------------------------------------------------ +#------ f3's .iplt entry +#------------------------------------------------------------------------------ -+ a04c: ebfffbf6 bl 902c ++ a04c: ebfffbf6 bl 902c + a050: e59f4000 ldr r4, \[pc\] ; a058 + a054: e59f4000 ldr r4, \[pc\] ; a05c +#------------------------------------------------------------------------------ @@ -2748769,7 +2763502,7 @@ index 0000000..a1fb37a +#------------------------------------------------------------------------------ +#------ f4's .iplt entry +#------------------------------------------------------------------------------ -+ a060: ebfffbf4 bl 9038 ++ a060: ebfffbf4 bl 9038 + a064: e59f4000 ldr r4, \[pc\] ; a06c + a068: e59f4000 ldr r4, \[pc\] ; a070 +#------------------------------------------------------------------------------ @@ -2748782,7 +2763515,7 @@ index 0000000..a1fb37a + a070: 00006fb8 \.word 0x00006fb8 diff --git a/ld/testsuite/ld-arm/ifunc-3.gd b/ld/testsuite/ld-arm/ifunc-3.gd new file mode 100644 -index 0000000..db7fd42 +index 0000000..ef6f2df --- /dev/null +++ b/ld/testsuite/ld-arm/ifunc-3.gd @@ -0,0 +1,45 @@ @@ -2748796,20 +2763529,20 @@ index 0000000..db7fd42 +#------ 00010008: contains PC-relative offset of foo +#------ 0001000c: contains f1 [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 10000 44332211 00000100 f8ffffff 00a00000 .* ++ 10000 (44332211 00000100 f8ffffff 00a00000|11223344 00010000 fffffff8 0000a000) .* +#------------------------------------------------------------------------------ +#------ 00010010: contains PC-relative offset of f1's .iplt entry +#------ 00010014: f2 [R_ARM_ABS32] +#------ 00010018: f2 [R_ARM_REL32] +#------ 0001001c: contains f3 [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 10010 1090ffff 00000000 00000000 08a00000 .* ++ 10010 (1090ffff 00000000 00000000 08a00000|ffff9010 00000000 00000000 0000a008) .* +#------------------------------------------------------------------------------ +#------ 00010020: contains PC-relative offset of f3's .iplt entry +#------ 00010024: f4 [R_ARM_ABS32] +#------ 00010028: contains PC-relative offset of f4's .iplt entry +#------------------------------------------------------------------------------ -+ 10020 0c90ffff 00000000 1090ffff .* ++ 10020 (0c90ffff 00000000 1090ffff|ffff900c 00000000 ffff9010) .* +Contents of section \.got: +#------------------------------------------------------------------------------ +#------ 00011000: .got.plt @@ -2748817,20 +2763550,20 @@ index 0000000..db7fd42 +#------ 00011008: reserved .got.plt entry +#------ 0001100c: f2's .got.plt entry [R_ARM_JUMP_SLOT] +#------------------------------------------------------------------------------ -+ 11000 00200100 00000000 00000000 00900000 .* ++ 11000 (00200100 00000000 00000000 00900000|00012000 00000000 00000000 00009000) .* +#------------------------------------------------------------------------------ +#------ 00011010: f1's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011014: f3's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011018: f4's .igot.plt entry [R_ARM_IRELATIVE] +#------ 0001101c: .got entry for foo [R_ARM_RELATIVE] +#------------------------------------------------------------------------------ -+ 11010 00a00000 08a00000 0ca00000 00000100 .* ++ 11010 (00a00000 08a00000 0ca00000 00000100|0000a000 0000a008 0000a00c 00010000) .* +#------------------------------------------------------------------------------ +#------ 00011020: .got entry for foo [R_ARM_RELATIVE] +#------ 00011024: .got entry for f2 [R_ARM_GLOB_DAT] +#------ 00011028: .got entry for f4 [R_ARM_GLOB_DAT] +#------------------------------------------------------------------------------ -+ 11020 00000100 00000000 00000000 .* ++ 11020 (00000100|00010000) 00000000 00000000 .* diff --git a/ld/testsuite/ld-arm/ifunc-3.rd b/ld/testsuite/ld-arm/ifunc-3.rd new file mode 100644 index 0000000..4acb314 @@ -2748914,19 +2763647,19 @@ index 0000000..ace3598 + .size arm,.-arm diff --git a/ld/testsuite/ld-arm/ifunc-4.dd b/ld/testsuite/ld-arm/ifunc-4.dd new file mode 100644 -index 0000000..f5a4d91 +index 0000000..6ce996b --- /dev/null +++ b/ld/testsuite/ld-arm/ifunc-4.dd -@@ -0,0 +1,1055 @@ +@@ -0,0 +1,1061 @@ + +.* + + +Disassembly of section \.plt: + -+00009000 <\.plt>: ++00009000 : + 9000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) -+ 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 ++ 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 + 9008: e08fe00e add lr, pc, lr + 900c: e5bef008 ldr pc, \[lr, #8\]! +#------------------------------------------------------------------------------ @@ -2748936,6 +2763669,7 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ thumb entry to atf2's .plt entry +#------------------------------------------------------------------------------ ++00009014 : + 9014: 4778 bx pc + 9016: 46c0 nop ; \(mov r8, r8\) +#------------------------------------------------------------------------------ @@ -2748947,6 +2763681,7 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ thumb entry to ttf2's .plt entry +#------------------------------------------------------------------------------ ++00009024 : + 9024: 4778 bx pc + 9026: 46c0 nop ; \(mov r8, r8\) +#------------------------------------------------------------------------------ @@ -2748958,6 +2763693,7 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ thumb entry to tbf2's .plt entry +#------------------------------------------------------------------------------ ++00009034 : + 9034: 4778 bx pc + 9036: 46c0 nop ; \(mov r8, r8\) +#------------------------------------------------------------------------------ @@ -2748969,18 +2763705,21 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ taf2's .plt entry +#------------------------------------------------------------------------------ ++00009044 : + 9044: e28fc600 add ip, pc, #0, 12 + 9048: e28cca07 add ip, ip, #28672 ; 0x7000 + 904c: e5bcffcc ldr pc, \[ip, #4044\]! ; 0xfcc +#------------------------------------------------------------------------------ +#------ aaf2's .plt entry +#------------------------------------------------------------------------------ ++00009050 : + 9050: e28fc600 add ip, pc, #0, 12 + 9054: e28cca07 add ip, ip, #28672 ; 0x7000 + 9058: e5bcffc4 ldr pc, \[ip, #4036\]! ; 0xfc4 +#------------------------------------------------------------------------------ +#------ thumb entry to abf2's .plt entry +#------------------------------------------------------------------------------ ++0000905c : + 905c: 4778 bx pc + 905e: 46c0 nop ; \(mov r8, r8\) +#------------------------------------------------------------------------------ @@ -2749257,15 +2763996,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ aaf1's .iplt entry +#------------------------------------------------------------------------------ -+ a06c: ebfffbfe bl 906c ++ a06c: ebfffbfe bl 906c +#------------------------------------------------------------------------------ +#------ aaf1's .iplt entry +#------------------------------------------------------------------------------ -+ a070: eafffbfd b 906c ++ a070: eafffbfd b 906c +#------------------------------------------------------------------------------ +#------ aaf1's .iplt entry +#------------------------------------------------------------------------------ -+ a074: 0afffbfc beq 906c ++ a074: 0afffbfc beq 906c + a078: e59f4000 ldr r4, \[pc\] ; a080 + a07c: e59f4000 ldr r4, \[pc\] ; a084 +#------------------------------------------------------------------------------ @@ -2749279,15 +2764018,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ taf1's .iplt entry +#------------------------------------------------------------------------------ -+ a088: ebfffc02 bl 9098 ++ a088: ebfffc02 bl 9098 +#------------------------------------------------------------------------------ +#------ taf1's .iplt entry +#------------------------------------------------------------------------------ -+ a08c: eafffc01 b 9098 ++ a08c: eafffc01 b 9098 +#------------------------------------------------------------------------------ +#------ taf1's .iplt entry +#------------------------------------------------------------------------------ -+ a090: 0afffc00 beq 9098 ++ a090: 0afffc00 beq 9098 + a094: e59f4000 ldr r4, \[pc\] ; a09c + a098: e59f4000 ldr r4, \[pc\] ; a0a0 +#------------------------------------------------------------------------------ @@ -2749301,15 +2764040,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ abf1's .iplt entry +#------------------------------------------------------------------------------ -+ a0a4: ebfffbf8 bl 908c ++ a0a4: ebfffbf8 bl 908c +#------------------------------------------------------------------------------ +#------ abf1's .iplt entry +#------------------------------------------------------------------------------ -+ a0a8: eafffbf7 b 908c ++ a0a8: eafffbf7 b 908c +#------------------------------------------------------------------------------ +#------ abf1's .iplt entry +#------------------------------------------------------------------------------ -+ a0ac: 0afffbf6 beq 908c ++ a0ac: 0afffbf6 beq 908c + a0b0: e59f4000 ldr r4, \[pc\] ; a0b8 + a0b4: e59f4000 ldr r4, \[pc\] ; a0bc +#------------------------------------------------------------------------------ @@ -2749323,15 +2764062,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ tbf1's .iplt entry +#------------------------------------------------------------------------------ -+ a0c0: ebfffbfc bl 90b8 ++ a0c0: ebfffbfc bl 90b8 +#------------------------------------------------------------------------------ +#------ tbf1's .iplt entry +#------------------------------------------------------------------------------ -+ a0c4: eafffbfb b 90b8 ++ a0c4: eafffbfb b 90b8 +#------------------------------------------------------------------------------ +#------ tbf1's .iplt entry +#------------------------------------------------------------------------------ -+ a0c8: 0afffbfa beq 90b8 ++ a0c8: 0afffbfa beq 90b8 + a0cc: e59f4000 ldr r4, \[pc\] ; a0d4 + a0d0: e59f4000 ldr r4, \[pc\] ; a0d8 +#------------------------------------------------------------------------------ @@ -2749345,15 +2764084,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ aaf2's .plt entry +#------------------------------------------------------------------------------ -+ a0dc: ebfffbdb bl 9050 ++ a0dc: ebfffbdb bl 9050 +#------------------------------------------------------------------------------ +#------ aaf2's .plt entry +#------------------------------------------------------------------------------ -+ a0e0: eafffbda b 9050 ++ a0e0: eafffbda b 9050 +#------------------------------------------------------------------------------ +#------ aaf2's .plt entry +#------------------------------------------------------------------------------ -+ a0e4: 0afffbd9 beq 9050 ++ a0e4: 0afffbd9 beq 9050 + a0e8: e59f4000 ldr r4, \[pc\] ; a0f0 + a0ec: e59f4000 ldr r4, \[pc\] ; a0f4 +#------------------------------------------------------------------------------ @@ -2749367,15 +2764106,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ taf2's .plt entry +#------------------------------------------------------------------------------ -+ a0f8: ebfffbd1 bl 9044 ++ a0f8: ebfffbd1 bl 9044 +#------------------------------------------------------------------------------ +#------ taf2's .plt entry +#------------------------------------------------------------------------------ -+ a0fc: eafffbd0 b 9044 ++ a0fc: eafffbd0 b 9044 +#------------------------------------------------------------------------------ +#------ taf2's .plt entry +#------------------------------------------------------------------------------ -+ a100: 0afffbcf beq 9044 ++ a100: 0afffbcf beq 9044 + a104: e59f4000 ldr r4, \[pc\] ; a10c + a108: e59f4000 ldr r4, \[pc\] ; a110 +#------------------------------------------------------------------------------ @@ -2749389,15 +2764128,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ abf2's .plt entry +#------------------------------------------------------------------------------ -+ a114: ebfffbd1 bl 9060 ++ a114: ebfffbd1 bl 9060 +#------------------------------------------------------------------------------ +#------ abf2's .plt entry +#------------------------------------------------------------------------------ -+ a118: eafffbd0 b 9060 ++ a118: eafffbd0 b 9060 +#------------------------------------------------------------------------------ +#------ abf2's .plt entry +#------------------------------------------------------------------------------ -+ a11c: 0afffbcf beq 9060 ++ a11c: 0afffbcf beq 9060 + a120: e59f4000 ldr r4, \[pc\] ; a128 + a124: e59f4000 ldr r4, \[pc\] ; a12c +#------------------------------------------------------------------------------ @@ -2749411,15 +2764150,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ tbf2's .plt entry +#------------------------------------------------------------------------------ -+ a130: ebfffbc0 bl 9038 ++ a130: ebfffbc0 bl 9038 +#------------------------------------------------------------------------------ +#------ tbf2's .plt entry +#------------------------------------------------------------------------------ -+ a134: eafffbbf b 9038 ++ a134: eafffbbf b 9038 +#------------------------------------------------------------------------------ +#------ tbf2's .plt entry +#------------------------------------------------------------------------------ -+ a138: 0afffbbe beq 9038 ++ a138: 0afffbbe beq 9038 + a13c: e59f4000 ldr r4, \[pc\] ; a144 + a140: e59f4000 ldr r4, \[pc\] ; a148 +#------------------------------------------------------------------------------ @@ -2749433,15 +2764172,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ aaf3's .iplt entry +#------------------------------------------------------------------------------ -+ a14c: ebfffbfe bl 914c ++ a14c: ebfffbfe bl 914c +#------------------------------------------------------------------------------ +#------ aaf3's .iplt entry +#------------------------------------------------------------------------------ -+ a150: eafffbfd b 914c ++ a150: eafffbfd b 914c +#------------------------------------------------------------------------------ +#------ aaf3's .iplt entry +#------------------------------------------------------------------------------ -+ a154: 0afffbfc beq 914c ++ a154: 0afffbfc beq 914c + a158: e59f4000 ldr r4, \[pc\] ; a160 + a15c: e59f4000 ldr r4, \[pc\] ; a164 +#------------------------------------------------------------------------------ @@ -2749455,15 +2764194,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ taf3's .iplt entry +#------------------------------------------------------------------------------ -+ a168: ebfffbe8 bl 9110 ++ a168: ebfffbe8 bl 9110 +#------------------------------------------------------------------------------ +#------ taf3's .iplt entry +#------------------------------------------------------------------------------ -+ a16c: eafffbe7 b 9110 ++ a16c: eafffbe7 b 9110 +#------------------------------------------------------------------------------ +#------ taf3's .iplt entry +#------------------------------------------------------------------------------ -+ a170: 0afffbe6 beq 9110 ++ a170: 0afffbe6 beq 9110 + a174: e59f4000 ldr r4, \[pc\] ; a17c + a178: e59f4000 ldr r4, \[pc\] ; a180 +#------------------------------------------------------------------------------ @@ -2749477,15 +2764216,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ abf3's .iplt entry +#------------------------------------------------------------------------------ -+ a184: ebfffbd6 bl 90e4 ++ a184: ebfffbd6 bl 90e4 +#------------------------------------------------------------------------------ +#------ abf3's .iplt entry +#------------------------------------------------------------------------------ -+ a188: eafffbd5 b 90e4 ++ a188: eafffbd5 b 90e4 +#------------------------------------------------------------------------------ +#------ abf3's .iplt entry +#------------------------------------------------------------------------------ -+ a18c: 0afffbd4 beq 90e4 ++ a18c: 0afffbd4 beq 90e4 + a190: e59f4000 ldr r4, \[pc\] ; a198 + a194: e59f4000 ldr r4, \[pc\] ; a19c +#------------------------------------------------------------------------------ @@ -2749499,15 +2764238,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ tbf3's .iplt entry +#------------------------------------------------------------------------------ -+ a1a0: ebfffbd7 bl 9104 ++ a1a0: ebfffbd7 bl 9104 +#------------------------------------------------------------------------------ +#------ tbf3's .iplt entry +#------------------------------------------------------------------------------ -+ a1a4: eafffbd6 b 9104 ++ a1a4: eafffbd6 b 9104 +#------------------------------------------------------------------------------ +#------ tbf3's .iplt entry +#------------------------------------------------------------------------------ -+ a1a8: 0afffbd5 beq 9104 ++ a1a8: 0afffbd5 beq 9104 + a1ac: e59f4000 ldr r4, \[pc\] ; a1b4 + a1b0: e59f4000 ldr r4, \[pc\] ; a1b8 +#------------------------------------------------------------------------------ @@ -2749521,15 +2764260,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ aaf4's .iplt entry +#------------------------------------------------------------------------------ -+ a1bc: ebfffbc0 bl 90c4 ++ a1bc: ebfffbc0 bl 90c4 +#------------------------------------------------------------------------------ +#------ aaf4's .iplt entry +#------------------------------------------------------------------------------ -+ a1c0: eafffbbf b 90c4 ++ a1c0: eafffbbf b 90c4 +#------------------------------------------------------------------------------ +#------ aaf4's .iplt entry +#------------------------------------------------------------------------------ -+ a1c4: 0afffbbe beq 90c4 ++ a1c4: 0afffbbe beq 90c4 + a1c8: e59f4000 ldr r4, \[pc\] ; a1d0 + a1cc: e59f4000 ldr r4, \[pc\] ; a1d4 +#------------------------------------------------------------------------------ @@ -2749543,15 +2764282,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ taf4's .iplt entry +#------------------------------------------------------------------------------ -+ a1d8: ebfffbe2 bl 9168 ++ a1d8: ebfffbe2 bl 9168 +#------------------------------------------------------------------------------ +#------ taf4's .iplt entry +#------------------------------------------------------------------------------ -+ a1dc: eafffbe1 b 9168 ++ a1dc: eafffbe1 b 9168 +#------------------------------------------------------------------------------ +#------ taf4's .iplt entry +#------------------------------------------------------------------------------ -+ a1e0: 0afffbe0 beq 9168 ++ a1e0: 0afffbe0 beq 9168 + a1e4: e59f4000 ldr r4, \[pc\] ; a1ec + a1e8: e59f4000 ldr r4, \[pc\] ; a1f0 +#------------------------------------------------------------------------------ @@ -2749565,15 +2764304,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ abf4's .iplt entry +#------------------------------------------------------------------------------ -+ a1f4: ebfffbc9 bl 9120 ++ a1f4: ebfffbc9 bl 9120 +#------------------------------------------------------------------------------ +#------ abf4's .iplt entry +#------------------------------------------------------------------------------ -+ a1f8: eafffbc8 b 9120 ++ a1f8: eafffbc8 b 9120 +#------------------------------------------------------------------------------ +#------ abf4's .iplt entry +#------------------------------------------------------------------------------ -+ a1fc: 0afffbc7 beq 9120 ++ a1fc: 0afffbc7 beq 9120 + a200: e59f4000 ldr r4, \[pc\] ; a208 + a204: e59f4000 ldr r4, \[pc\] ; a20c +#------------------------------------------------------------------------------ @@ -2749587,15 +2764326,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ tbf4's .iplt entry +#------------------------------------------------------------------------------ -+ a210: ebfffbc6 bl 9130 ++ a210: ebfffbc6 bl 9130 +#------------------------------------------------------------------------------ +#------ tbf4's .iplt entry +#------------------------------------------------------------------------------ -+ a214: eafffbc5 b 9130 ++ a214: eafffbc5 b 9130 +#------------------------------------------------------------------------------ +#------ tbf4's .iplt entry +#------------------------------------------------------------------------------ -+ a218: 0afffbc4 beq 9130 ++ a218: 0afffbc4 beq 9130 + a21c: e59f4000 ldr r4, \[pc\] ; a224 + a220: e59f4000 ldr r4, \[pc\] ; a228 +#------------------------------------------------------------------------------ @@ -2749624,15 +2764363,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ atf1's .iplt entry +#------------------------------------------------------------------------------ -+ a244: f7fe ef1a blx 907c ++ a244: f7fe ef1a blx 907c +#------------------------------------------------------------------------------ +#------ thumb entry to atf1's .iplt entry +#------------------------------------------------------------------------------ -+ a248: f7fe bf16 b\.w 9078 ++ a248: f7fe bf16 b\.w 9078 +#------------------------------------------------------------------------------ +#------ thumb entry to atf1's .iplt entry +#------------------------------------------------------------------------------ -+ a24c: f43e af14 beq\.w 9078 ++ a24c: f43e af14 beq\.w 9078 + a250: 4c00 ldr r4, \[pc, #0\] ; \(a254 <_thumb\+0x28>\) + a252: 4c01 ldr r4, \[pc, #4\] ; \(a258 <_thumb\+0x2c>\) +#------------------------------------------------------------------------------ @@ -2749646,15 +2764385,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ ttf1's .iplt entry +#------------------------------------------------------------------------------ -+ a25c: f7fe ef24 blx 90a8 ++ a25c: f7fe ef24 blx 90a8 +#------------------------------------------------------------------------------ +#------ thumb entry to ttf1's .iplt entry +#------------------------------------------------------------------------------ -+ a260: f7fe bf20 b\.w 90a4 ++ a260: f7fe bf20 b\.w 90a4 +#------------------------------------------------------------------------------ +#------ thumb entry to ttf1's .iplt entry +#------------------------------------------------------------------------------ -+ a264: f43e af1e beq\.w 90a4 ++ a264: f43e af1e beq\.w 90a4 + a268: 4c00 ldr r4, \[pc, #0\] ; \(a26c <_thumb\+0x40>\) + a26a: 4c01 ldr r4, \[pc, #4\] ; \(a270 <_thumb\+0x44>\) +#------------------------------------------------------------------------------ @@ -2749668,15 +2764407,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ abf1's .iplt entry +#------------------------------------------------------------------------------ -+ a274: f7fe ef0a blx 908c ++ a274: f7fe ef0a blx 908c +#------------------------------------------------------------------------------ +#------ thumb entry to abf1's .iplt entry +#------------------------------------------------------------------------------ -+ a278: f7fe bf06 b\.w 9088 ++ a278: f7fe bf06 b\.w 9088 +#------------------------------------------------------------------------------ +#------ thumb entry to abf1's .iplt entry +#------------------------------------------------------------------------------ -+ a27c: f43e af04 beq\.w 9088 ++ a27c: f43e af04 beq\.w 9088 + a280: 4c00 ldr r4, \[pc, #0\] ; \(a284 <_thumb\+0x58>\) + a282: 4c01 ldr r4, \[pc, #4\] ; \(a288 <_thumb\+0x5c>\) +#------------------------------------------------------------------------------ @@ -2749690,15 +2764429,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ tbf1's .iplt entry +#------------------------------------------------------------------------------ -+ a28c: f7fe ef14 blx 90b8 ++ a28c: f7fe ef14 blx 90b8 +#------------------------------------------------------------------------------ +#------ thumb entry to tbf1's .iplt entry +#------------------------------------------------------------------------------ -+ a290: f7fe bf10 b\.w 90b4 ++ a290: f7fe bf10 b\.w 90b4 +#------------------------------------------------------------------------------ +#------ thumb entry to tbf1's .iplt entry +#------------------------------------------------------------------------------ -+ a294: f43e af0e beq\.w 90b4 ++ a294: f43e af0e beq\.w 90b4 + a298: 4c00 ldr r4, \[pc, #0\] ; \(a29c <_thumb\+0x70>\) + a29a: 4c01 ldr r4, \[pc, #4\] ; \(a2a0 <_thumb\+0x74>\) +#------------------------------------------------------------------------------ @@ -2749712,15 +2764451,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ atf2's .plt entry +#------------------------------------------------------------------------------ -+ a2a4: f7fe eeb8 blx 9018 ++ a2a4: f7fe eeb8 blx 9018 +#------------------------------------------------------------------------------ +#------ thumb entry to atf2's .plt entry +#------------------------------------------------------------------------------ -+ a2a8: f7fe beb4 b\.w 9014 ++ a2a8: f7fe beb4 b\.w 9014 +#------------------------------------------------------------------------------ +#------ thumb entry to atf2's .plt entry +#------------------------------------------------------------------------------ -+ a2ac: f43e aeb2 beq\.w 9014 ++ a2ac: f43e aeb2 beq\.w 9014 + a2b0: 4c00 ldr r4, \[pc, #0\] ; \(a2b4 <_thumb\+0x88>\) + a2b2: 4c01 ldr r4, \[pc, #4\] ; \(a2b8 <_thumb\+0x8c>\) +#------------------------------------------------------------------------------ @@ -2749734,15 +2764473,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ ttf2's .plt entry +#------------------------------------------------------------------------------ -+ a2bc: f7fe eeb4 blx 9028 ++ a2bc: f7fe eeb4 blx 9028 +#------------------------------------------------------------------------------ +#------ thumb entry to ttf2's .plt entry +#------------------------------------------------------------------------------ -+ a2c0: f7fe beb0 b\.w 9024 ++ a2c0: f7fe beb0 b\.w 9024 +#------------------------------------------------------------------------------ +#------ thumb entry to ttf2's .plt entry +#------------------------------------------------------------------------------ -+ a2c4: f43e aeae beq\.w 9024 ++ a2c4: f43e aeae beq\.w 9024 + a2c8: 4c00 ldr r4, \[pc, #0\] ; \(a2cc <_thumb\+0xa0>\) + a2ca: 4c01 ldr r4, \[pc, #4\] ; \(a2d0 <_thumb\+0xa4>\) +#------------------------------------------------------------------------------ @@ -2749756,15 +2764495,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ abf2's .plt entry +#------------------------------------------------------------------------------ -+ a2d4: f7fe eec4 blx 9060 ++ a2d4: f7fe eec4 blx 9060 +#------------------------------------------------------------------------------ +#------ thumb entry to abf2's .plt entry +#------------------------------------------------------------------------------ -+ a2d8: f7fe bec0 b\.w 905c ++ a2d8: f7fe bec0 b\.w 905c +#------------------------------------------------------------------------------ +#------ thumb entry to abf2's .plt entry +#------------------------------------------------------------------------------ -+ a2dc: f43e aebe beq\.w 905c ++ a2dc: f43e aebe beq\.w 905c + a2e0: 4c00 ldr r4, \[pc, #0\] ; \(a2e4 <_thumb\+0xb8>\) + a2e2: 4c01 ldr r4, \[pc, #4\] ; \(a2e8 <_thumb\+0xbc>\) +#------------------------------------------------------------------------------ @@ -2749778,15 +2764517,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ tbf2's .plt entry +#------------------------------------------------------------------------------ -+ a2ec: f7fe eea4 blx 9038 ++ a2ec: f7fe eea4 blx 9038 +#------------------------------------------------------------------------------ +#------ thumb entry to tbf2's .plt entry +#------------------------------------------------------------------------------ -+ a2f0: f7fe bea0 b\.w 9034 ++ a2f0: f7fe bea0 b\.w 9034 +#------------------------------------------------------------------------------ +#------ thumb entry to tbf2's .plt entry +#------------------------------------------------------------------------------ -+ a2f4: f43e ae9e beq\.w 9034 ++ a2f4: f43e ae9e beq\.w 9034 + a2f8: 4c00 ldr r4, \[pc, #0\] ; \(a2fc <_thumb\+0xd0>\) + a2fa: 4c01 ldr r4, \[pc, #4\] ; \(a300 <_thumb\+0xd4>\) +#------------------------------------------------------------------------------ @@ -2749800,15 +2764539,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ atf3's .iplt entry +#------------------------------------------------------------------------------ -+ a304: f7fe eee6 blx 90d4 ++ a304: f7fe eee6 blx 90d4 +#------------------------------------------------------------------------------ +#------ thumb entry to atf3's .iplt entry +#------------------------------------------------------------------------------ -+ a308: f7fe bee2 b\.w 90d0 ++ a308: f7fe bee2 b\.w 90d0 +#------------------------------------------------------------------------------ +#------ thumb entry to atf3's .iplt entry +#------------------------------------------------------------------------------ -+ a30c: f43e aee0 beq\.w 90d0 ++ a30c: f43e aee0 beq\.w 90d0 + a310: 4c00 ldr r4, \[pc, #0\] ; \(a314 <_thumb\+0xe8>\) + a312: 4c01 ldr r4, \[pc, #4\] ; \(a318 <_thumb\+0xec>\) +#------------------------------------------------------------------------------ @@ -2749822,15 +2764561,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ ttf3's .iplt entry +#------------------------------------------------------------------------------ -+ a31c: f7fe eeea blx 90f4 ++ a31c: f7fe eeea blx 90f4 +#------------------------------------------------------------------------------ +#------ thumb entry to ttf3's .iplt entry +#------------------------------------------------------------------------------ -+ a320: f7fe bee6 b\.w 90f0 ++ a320: f7fe bee6 b\.w 90f0 +#------------------------------------------------------------------------------ +#------ thumb entry to ttf3's .iplt entry +#------------------------------------------------------------------------------ -+ a324: f43e aee4 beq\.w 90f0 ++ a324: f43e aee4 beq\.w 90f0 + a328: 4c00 ldr r4, \[pc, #0\] ; \(a32c <_thumb\+0x100>\) + a32a: 4c01 ldr r4, \[pc, #4\] ; \(a330 <_thumb\+0x104>\) +#------------------------------------------------------------------------------ @@ -2749844,15 +2764583,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ abf3's .iplt entry +#------------------------------------------------------------------------------ -+ a334: f7fe eed6 blx 90e4 ++ a334: f7fe eed6 blx 90e4 +#------------------------------------------------------------------------------ +#------ thumb entry to abf3's .iplt entry +#------------------------------------------------------------------------------ -+ a338: f7fe bed2 b\.w 90e0 ++ a338: f7fe bed2 b\.w 90e0 +#------------------------------------------------------------------------------ +#------ thumb entry to abf3's .iplt entry +#------------------------------------------------------------------------------ -+ a33c: f43e aed0 beq\.w 90e0 ++ a33c: f43e aed0 beq\.w 90e0 + a340: 4c00 ldr r4, \[pc, #0\] ; \(a344 <_thumb\+0x118>\) + a342: 4c01 ldr r4, \[pc, #4\] ; \(a348 <_thumb\+0x11c>\) +#------------------------------------------------------------------------------ @@ -2749866,15 +2764605,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ tbf3's .iplt entry +#------------------------------------------------------------------------------ -+ a34c: f7fe eeda blx 9104 ++ a34c: f7fe eeda blx 9104 +#------------------------------------------------------------------------------ +#------ thumb entry to tbf3's .iplt entry +#------------------------------------------------------------------------------ -+ a350: f7fe bed6 b\.w 9100 ++ a350: f7fe bed6 b\.w 9100 +#------------------------------------------------------------------------------ +#------ thumb entry to tbf3's .iplt entry +#------------------------------------------------------------------------------ -+ a354: f43e aed4 beq\.w 9100 ++ a354: f43e aed4 beq\.w 9100 + a358: 4c00 ldr r4, \[pc, #0\] ; \(a35c <_thumb\+0x130>\) + a35a: 4c01 ldr r4, \[pc, #4\] ; \(a360 <_thumb\+0x134>\) +#------------------------------------------------------------------------------ @@ -2749888,15 +2764627,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ atf4's .iplt entry +#------------------------------------------------------------------------------ -+ a364: f7fe eefa blx 915c ++ a364: f7fe eefa blx 915c +#------------------------------------------------------------------------------ +#------ thumb entry to atf4's .iplt entry +#------------------------------------------------------------------------------ -+ a368: f7fe bef6 b\.w 9158 ++ a368: f7fe bef6 b\.w 9158 +#------------------------------------------------------------------------------ +#------ thumb entry to atf4's .iplt entry +#------------------------------------------------------------------------------ -+ a36c: f43e aef4 beq\.w 9158 ++ a36c: f43e aef4 beq\.w 9158 + a370: 4c00 ldr r4, \[pc, #0\] ; \(a374 <_thumb\+0x148>\) + a372: 4c01 ldr r4, \[pc, #4\] ; \(a378 <_thumb\+0x14c>\) +#------------------------------------------------------------------------------ @@ -2749910,15 +2764649,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ ttf4's .iplt entry +#------------------------------------------------------------------------------ -+ a37c: f7fe eee0 blx 9140 ++ a37c: f7fe eee0 blx 9140 +#------------------------------------------------------------------------------ +#------ thumb entry to ttf4's .iplt entry +#------------------------------------------------------------------------------ -+ a380: f7fe bedc b\.w 913c ++ a380: f7fe bedc b\.w 913c +#------------------------------------------------------------------------------ +#------ thumb entry to ttf4's .iplt entry +#------------------------------------------------------------------------------ -+ a384: f43e aeda beq\.w 913c ++ a384: f43e aeda beq\.w 913c + a388: 4c00 ldr r4, \[pc, #0\] ; \(a38c <_thumb\+0x160>\) + a38a: 4c01 ldr r4, \[pc, #4\] ; \(a390 <_thumb\+0x164>\) +#------------------------------------------------------------------------------ @@ -2749932,15 +2764671,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ abf4's .iplt entry +#------------------------------------------------------------------------------ -+ a394: f7fe eec4 blx 9120 ++ a394: f7fe eec4 blx 9120 +#------------------------------------------------------------------------------ +#------ thumb entry to abf4's .iplt entry +#------------------------------------------------------------------------------ -+ a398: f7fe bec0 b\.w 911c ++ a398: f7fe bec0 b\.w 911c +#------------------------------------------------------------------------------ +#------ thumb entry to abf4's .iplt entry +#------------------------------------------------------------------------------ -+ a39c: f43e aebe beq\.w 911c ++ a39c: f43e aebe beq\.w 911c + a3a0: 4c00 ldr r4, \[pc, #0\] ; \(a3a4 <_thumb\+0x178>\) + a3a2: 4c01 ldr r4, \[pc, #4\] ; \(a3a8 <_thumb\+0x17c>\) +#------------------------------------------------------------------------------ @@ -2749954,15 +2764693,15 @@ index 0000000..f5a4d91 +#------------------------------------------------------------------------------ +#------ tbf4's .iplt entry +#------------------------------------------------------------------------------ -+ a3ac: f7fe eec0 blx 9130 ++ a3ac: f7fe eec0 blx 9130 +#------------------------------------------------------------------------------ +#------ thumb entry to tbf4's .iplt entry +#------------------------------------------------------------------------------ -+ a3b0: f7fe bebc b\.w 912c ++ a3b0: f7fe bebc b\.w 912c +#------------------------------------------------------------------------------ +#------ thumb entry to tbf4's .iplt entry +#------------------------------------------------------------------------------ -+ a3b4: f43e aeba beq\.w 912c ++ a3b4: f43e aeba beq\.w 912c + a3b8: 4c00 ldr r4, \[pc, #0\] ; \(a3bc <_thumb\+0x190>\) + a3ba: 4c01 ldr r4, \[pc, #4\] ; \(a3c0 <_thumb\+0x194>\) +#------------------------------------------------------------------------------ @@ -2749975,7 +2764714,7 @@ index 0000000..f5a4d91 + a3c0: 00006cd0 \.word 0x00006cd0 diff --git a/ld/testsuite/ld-arm/ifunc-4.gd b/ld/testsuite/ld-arm/ifunc-4.gd new file mode 100644 -index 0000000..f768c68 +index 0000000..bb7a8d6 --- /dev/null +++ b/ld/testsuite/ld-arm/ifunc-4.gd @@ -0,0 +1,167 @@ @@ -2749989,28 +2764728,28 @@ index 0000000..f768c68 +#------ 00010008: contains PC-relative offset of aaf1's .iplt entry +#------ 0001000c: contains atf1 [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 10000 44332211 00a00000 6490ffff 04a00000 .* ++ 10000 (44332211 00a00000 6490ffff 04a00000|11223344 0000a000 ffff9064 0000a004) .* +#------------------------------------------------------------------------------ +#------ 00010010: contains PC-relative offset of atf1's .iplt entry +#------ 00010014: contains abf1 [R_ARM_IRELATIVE] +#------ 00010018: contains PC-relative offset of abf1's .iplt entry +#------ 0001001c: contains taf1 [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 10010 6c90ffff 08a00000 7490ffff 0da00000 .* ++ 10010 (6c90ffff 08a00000 7490ffff 0da00000|ffff906c 0000a008 ffff9074 0000a00d) .* +#------------------------------------------------------------------------------ +#------ 00010020: contains PC-relative offset of taf1's .iplt entry +#------ 00010024: contains ttf1 [R_ARM_IRELATIVE] +#------ 00010028: contains PC-relative offset of ttf1's .iplt entry +#------ 0001002c: contains tbf1 [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 10020 7890ffff 0fa00000 8090ffff 11a00000 .* ++ 10020 (7890ffff 0fa00000 8090ffff 11a00000|ffff9078 0000a00f ffff9080 0000a011) .* +#------------------------------------------------------------------------------ +#------ 00010030: contains PC-relative offset of tbf1's .iplt entry +#------ 00010034: aaf2 [R_ARM_ABS32] +#------ 00010038: aaf2 [R_ARM_REL32] +#------ 0001003c: atf2 [R_ARM_ABS32] +#------------------------------------------------------------------------------ -+ 10030 8890ffff 00000000 00000000 00000000 .* ++ 10030 (8890ffff|ffff9088) 00000000 00000000 00000000 .* +#------------------------------------------------------------------------------ +#------ 00010040: atf2 [R_ARM_REL32] +#------ 00010044: abf2 [R_ARM_ABS32] @@ -2750031,46 +2764770,46 @@ index 0000000..f768c68 +#------ 00010068: contains PC-relative offset of aaf3's .iplt entry +#------ 0001006c: contains atf3 [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 10060 00000000 28a00000 e490ffff 2ca00000 .* ++ 10060 00000000 (28a00000 e490ffff 2ca00000|0000a028 ffff90e4 0000a02c) .* +#------------------------------------------------------------------------------ +#------ 00010070: contains PC-relative offset of atf3's .iplt entry +#------ 00010074: contains abf3 [R_ARM_IRELATIVE] +#------ 00010078: contains PC-relative offset of abf3's .iplt entry +#------ 0001007c: contains taf3 [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 10070 6490ffff 30a00000 6c90ffff 35a00000 .* ++ 10070 (6490ffff 30a00000 6c90ffff 35a00000|ffff9064 0000a030 ffff906c 0000a035) .* +#------------------------------------------------------------------------------ +#------ 00010080: contains PC-relative offset of taf3's .iplt entry +#------ 00010084: contains ttf3 [R_ARM_IRELATIVE] +#------ 00010088: contains PC-relative offset of ttf3's .iplt entry +#------ 0001008c: contains tbf3 [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 10080 9090ffff 37a00000 6c90ffff 39a00000 .* ++ 10080 (9090ffff 37a00000 6c90ffff 39a00000|ffff9090 0000a037 ffff906c 0000a039) .* +#------------------------------------------------------------------------------ +#------ 00010090: contains PC-relative offset of tbf3's .iplt entry +#------ 00010094: aaf4 [R_ARM_ABS32] +#------ 00010098: contains PC-relative offset of aaf4's .iplt entry +#------ 0001009c: atf4 [R_ARM_ABS32] +#------------------------------------------------------------------------------ -+ 10090 7490ffff 00000000 2c90ffff 00000000 .* ++ 10090 (7490ffff 00000000 2c90ffff|ffff9074 00000000 ffff902c) 00000000 .* +#------------------------------------------------------------------------------ +#------ 000100a0: contains PC-relative offset of atf4's .iplt entry +#------ 000100a4: abf4 [R_ARM_ABS32] +#------ 000100a8: contains PC-relative offset of abf4's .iplt entry +#------ 000100ac: taf4 [R_ARM_ABS32] +#------------------------------------------------------------------------------ -+ 100a0 bc90ffff 00000000 7890ffff 00000000 .* ++ 100a0 (bc90ffff 00000000 7890ffff|ffff90bc 00000000 ffff9078) 00000000 .* +#------------------------------------------------------------------------------ +#------ 000100b0: contains PC-relative offset of taf4's .iplt entry +#------ 000100b4: ttf4 [R_ARM_ABS32] +#------ 000100b8: contains PC-relative offset of ttf4's .iplt entry +#------ 000100bc: tbf4 [R_ARM_ABS32] +#------------------------------------------------------------------------------ -+ 100b0 b890ffff 00000000 8890ffff 00000000 .* ++ 100b0 (b890ffff 00000000 8890ffff|ffff90b8 00000000 ffff9088) 00000000 .* +#------------------------------------------------------------------------------ +#------ 000100c0: contains PC-relative offset of tbf4's .iplt entry +#------------------------------------------------------------------------------ -+ 100c0 7090ffff .* ++ 100c0 (7090ffff|ffff9070) .* +Contents of section \.got: +#------------------------------------------------------------------------------ +#------ 00011000: .got.plt @@ -2750078,56 +2764817,56 @@ index 0000000..f768c68 +#------ 00011008: reserved .got.plt entry +#------ 0001100c: atf2's .got.plt entry [R_ARM_JUMP_SLOT] +#------------------------------------------------------------------------------ -+ 11000 00200100 00000000 00000000 00900000 .* ++ 11000 (00200100 00000000 00000000 00900000|00012000 00000000 00000000 00009000) .* +#------------------------------------------------------------------------------ +#------ 00011010: ttf2's .got.plt entry [R_ARM_JUMP_SLOT] +#------ 00011014: tbf2's .got.plt entry [R_ARM_JUMP_SLOT] +#------ 00011018: taf2's .got.plt entry [R_ARM_JUMP_SLOT] +#------ 0001101c: aaf2's .got.plt entry [R_ARM_JUMP_SLOT] +#------------------------------------------------------------------------------ -+ 11010 00900000 00900000 00900000 00900000 .* ++ 11010 (00900000 00900000 00900000 00900000|00009000 00009000 00009000 00009000) .* +#------------------------------------------------------------------------------ +#------ 00011020: abf2's .got.plt entry [R_ARM_JUMP_SLOT] +#------ 00011024: aaf1's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011028: atf1's .igot.plt entry [R_ARM_IRELATIVE] +#------ 0001102c: abf1's .igot.plt entry [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 11020 00900000 00a00000 04a00000 08a00000 .* ++ 11020 (00900000 00a00000 04a00000 08a00000|00009000 0000a000 0000a004 0000a008) .* +#------------------------------------------------------------------------------ +#------ 00011030: taf1's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011034: ttf1's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011038: tbf1's .igot.plt entry [R_ARM_IRELATIVE] +#------ 0001103c: aaf4's .igot.plt entry [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 11030 0da00000 0fa00000 11a00000 3ca00000 .* ++ 11030 (0da00000 0fa00000 11a00000 3ca00000|0000a00d 0000a00f 0000a011 0000a03c) .* +#------------------------------------------------------------------------------ +#------ 00011040: atf3's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011044: abf3's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011048: ttf3's .igot.plt entry [R_ARM_IRELATIVE] +#------ 0001104c: tbf3's .igot.plt entry [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 11040 2ca00000 30a00000 37a00000 39a00000 .* ++ 11040 (2ca00000 30a00000 37a00000 39a00000|0000a02c 0000a030 0000a037 0000a039) .* +#------------------------------------------------------------------------------ +#------ 00011050: taf3's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011054: abf4's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011058: tbf4's .igot.plt entry [R_ARM_IRELATIVE] +#------ 0001105c: ttf4's .igot.plt entry [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 11050 35a00000 44a00000 4da00000 4ba00000 .* ++ 11050 (35a00000 44a00000 4da00000 4ba00000|0000a035 0000a044 0000a04d 0000a04b) .* +#------------------------------------------------------------------------------ +#------ 00011060: aaf3's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011064: atf4's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011068: taf4's .igot.plt entry [R_ARM_IRELATIVE] +#------ 0001106c: .got entry for foo [R_ARM_RELATIVE] +#------------------------------------------------------------------------------ -+ 11060 28a00000 40a00000 49a00000 00000100 .* ++ 11060 (28a00000 40a00000 49a00000 00000100|0000a028 0000a040 0000a049 00010000) .* +#------------------------------------------------------------------------------ +#------ 00011070: .got entry for foo [R_ARM_RELATIVE] +#------ 00011074: .got entry for atf2 [R_ARM_GLOB_DAT] +#------ 00011078: .got entry for aaf4 [R_ARM_GLOB_DAT] +#------ 0001107c: .got entry for ttf2 [R_ARM_GLOB_DAT] +#------------------------------------------------------------------------------ -+ 11070 00000100 00000000 00000000 00000000 .* ++ 11070 (00000100|00010000) 00000000 00000000 00000000 .* +#------------------------------------------------------------------------------ +#------ 00011080: .got entry for tbf2 [R_ARM_GLOB_DAT] +#------ 00011084: .got entry for taf2 [R_ARM_GLOB_DAT] @@ -2750426,7 +2765165,7 @@ index 0000000..b0bf597 + a058: 00006fb8 \.word 0x00006fb8 diff --git a/ld/testsuite/ld-arm/ifunc-5.gd b/ld/testsuite/ld-arm/ifunc-5.gd new file mode 100644 -index 0000000..8cd69df +index 0000000..fba1512 --- /dev/null +++ b/ld/testsuite/ld-arm/ifunc-5.gd @@ -0,0 +1,23 @@ @@ -2750437,7 +2765176,7 @@ index 0000000..8cd69df +#------------------------------------------------------------------------------ +#------ 00010000: foo +#------------------------------------------------------------------------------ -+ 10000 44332211 00800000 18800000 .* ++ 10000 (44332211 00800000 18800000|11223344 00008000 00008018) .* +Contents of section \.got: +#------------------------------------------------------------------------------ +#------ 00011000: .got.plt @@ -2750445,14 +2765184,14 @@ index 0000000..8cd69df +#------ 00011008: reserved .got.plt entry +#------ 0001100c: f1's .igot.plt entry [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 11000 00000000 00000000 00000000 00a00000 .* ++ 11000 00000000 00000000 00000000 (00a00000|0000a000) .* +#------------------------------------------------------------------------------ +#------ 00011010: f3's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011014: f2's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011018: .got entry for foo +#------ 0001101c: .got entry for foo +#------------------------------------------------------------------------------ -+ 11010 08a00000 04a00000 00000100 00000100 .* ++ 11010 (08a00000 04a00000 00000100 00000100|0000a008 0000a004 00010000 00010000) .* diff --git a/ld/testsuite/ld-arm/ifunc-5.rd b/ld/testsuite/ld-arm/ifunc-5.rd new file mode 100644 index 0000000..2644123 @@ -2750695,7 +2765434,7 @@ index 0000000..3c9cbd5 + a0a8: 00006f6c \.word 0x00006f6c diff --git a/ld/testsuite/ld-arm/ifunc-6.gd b/ld/testsuite/ld-arm/ifunc-6.gd new file mode 100644 -index 0000000..45fd914 +index 0000000..649a57b --- /dev/null +++ b/ld/testsuite/ld-arm/ifunc-6.gd @@ -0,0 +1,27 @@ @@ -2750706,7 +2765445,7 @@ index 0000000..45fd914 +#------------------------------------------------------------------------------ +#------ 00010000: foo +#------------------------------------------------------------------------------ -+ 10000 44332211 00800000 20800000 .* ++ 10000 (44332211 00800000 20800000|11223344 00008000 00008020) .* +Contents of section \.got: +#------------------------------------------------------------------------------ +#------ 00011000: .got.plt @@ -2750714,18 +2765453,18 @@ index 0000000..45fd914 +#------ 00011008: reserved .got.plt entry +#------ 0001100c: f3's .igot.plt entry [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 11000 00000000 00000000 00000000 08a00000 .* ++ 11000 00000000 00000000 00000000 (08a00000|0000a008) .* +#------------------------------------------------------------------------------ +#------ 00011010: f2's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011014: f4's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011018: f1's .igot.plt entry [R_ARM_IRELATIVE] +#------ 0001101c: .got entry for foo +#------------------------------------------------------------------------------ -+ 11010 05a00000 0da00000 00a00000 00000100 .* ++ 11010 (05a00000 0da00000 00a00000 00000100|0000a005 0000a00d 0000a000 00010000) .* +#------------------------------------------------------------------------------ +#------ 00011020: .got entry for foo +#------------------------------------------------------------------------------ -+ 11020 00000100 .* ++ 11020 (00000100|00010000) .* diff --git a/ld/testsuite/ld-arm/ifunc-6.rd b/ld/testsuite/ld-arm/ifunc-6.rd new file mode 100644 index 0000000..04c18a9 @@ -2750808,19 +2765547,19 @@ index 0000000..4596fa3 + .word __irel_end diff --git a/ld/testsuite/ld-arm/ifunc-7.dd b/ld/testsuite/ld-arm/ifunc-7.dd new file mode 100644 -index 0000000..e9a9681 +index 0000000..f82fd37 --- /dev/null +++ b/ld/testsuite/ld-arm/ifunc-7.dd -@@ -0,0 +1,120 @@ +@@ -0,0 +1,122 @@ + +.* + + +Disassembly of section \.plt: + -+00009000 <\.plt>: ++00009000 : + 9000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) -+ 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 ++ 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 + 9008: e08fe00e add lr, pc, lr + 900c: e5bef008 ldr pc, \[lr, #8\]! +#------------------------------------------------------------------------------ @@ -2750830,12 +2765569,14 @@ index 0000000..e9a9681 +#------------------------------------------------------------------------------ +#------ f2's .plt entry +#------------------------------------------------------------------------------ ++00009014 : + 9014: e28fc600 add ip, pc, #0, 12 + 9018: e28cca07 add ip, ip, #28672 ; 0x7000 + 901c: e5bcfff0 ldr pc, \[ip, #4080\]! ; 0xff0 +#------------------------------------------------------------------------------ +#------ f4's .plt entry +#------------------------------------------------------------------------------ ++00009020 : + 9020: e28fc600 add ip, pc, #0, 12 + 9024: e28cca07 add ip, ip, #28672 ; 0x7000 + 9028: e5bcffe8 ldr pc, \[ip, #4072\]! ; 0xfe8 @@ -2750879,7 +2765620,7 @@ index 0000000..e9a9681 +#------------------------------------------------------------------------------ +#------ f1's .iplt entry +#------------------------------------------------------------------------------ -+ a01c: ebfffc02 bl 902c ++ a01c: ebfffc02 bl 902c + a020: e59f4000 ldr r4, \[pc\] ; a028 + a024: e59f4000 ldr r4, \[pc\] ; a02c +#------------------------------------------------------------------------------ @@ -2750893,7 +2765634,7 @@ index 0000000..e9a9681 +#------------------------------------------------------------------------------ +#------ f2's .plt entry +#------------------------------------------------------------------------------ -+ a030: ebfffbf7 bl 9014 ++ a030: ebfffbf7 bl 9014 + a034: e59f4000 ldr r4, \[pc\] ; a03c + a038: e59f4000 ldr r4, \[pc\] ; a040 +#------------------------------------------------------------------------------ @@ -2750907,7 +2765648,7 @@ index 0000000..e9a9681 +#------------------------------------------------------------------------------ +#------ f3's .iplt entry +#------------------------------------------------------------------------------ -+ a044: ebfffbfb bl 9038 ++ a044: ebfffbfb bl 9038 + a048: e59f4000 ldr r4, \[pc\] ; a050 + a04c: e59f4000 ldr r4, \[pc\] ; a054 +#------------------------------------------------------------------------------ @@ -2750921,7 +2765662,7 @@ index 0000000..e9a9681 +#------------------------------------------------------------------------------ +#------ f4's .plt entry +#------------------------------------------------------------------------------ -+ a058: ebfffbf0 bl 9020 ++ a058: ebfffbf0 bl 9020 + a05c: e59f4000 ldr r4, \[pc\] ; a064 + a060: e59f4000 ldr r4, \[pc\] ; a068 +#------------------------------------------------------------------------------ @@ -2750934,7 +2765675,7 @@ index 0000000..e9a9681 + a068: 00006fc0 \.word 0x00006fc0 diff --git a/ld/testsuite/ld-arm/ifunc-7.gd b/ld/testsuite/ld-arm/ifunc-7.gd new file mode 100644 -index 0000000..a116aaf +index 0000000..3251c45 --- /dev/null +++ b/ld/testsuite/ld-arm/ifunc-7.gd @@ -0,0 +1,45 @@ @@ -2750948,20 +2765689,20 @@ index 0000000..a116aaf +#------ 00010008: contains PC-relative offset of foo +#------ 0001000c: contains f1 [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 10000 44332211 00000100 f8ffffff 00a00000 .* ++ 10000 (44332211 00000100 f8ffffff 00a00000|11223344 00010000 fffffff8 0000a000) .* +#------------------------------------------------------------------------------ +#------ 00010010: contains PC-relative offset of f1's .iplt entry +#------ 00010014: f2 [R_ARM_ABS32] +#------ 00010018: f2 [R_ARM_REL32] +#------ 0001001c: contains f3 [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 10010 1c90ffff 00000000 00000000 04a00000 .* ++ 10010 (1c90ffff 00000000 00000000 04a00000|ffff901c 00000000 00000000 0000a004) .* +#------------------------------------------------------------------------------ +#------ 00010020: contains PC-relative offset of f3's .iplt entry +#------ 00010024: f4 [R_ARM_ABS32] +#------ 00010028: f4 [R_ARM_REL32] +#------------------------------------------------------------------------------ -+ 10020 1890ffff 00000000 00000000 .* ++ 10020 (1890ffff|ffff9018) 00000000 00000000 .* +Contents of section \.got: +#------------------------------------------------------------------------------ +#------ 00011000: .got.plt @@ -2750969,20 +2765710,20 @@ index 0000000..a116aaf +#------ 00011008: reserved .got.plt entry +#------ 0001100c: f2's .got.plt entry [R_ARM_JUMP_SLOT] +#------------------------------------------------------------------------------ -+ 11000 00200100 00000000 00000000 00900000 .* ++ 11000 (00200100 00000000 00000000 00900000|00012000 00000000 00000000 00009000) .* +#------------------------------------------------------------------------------ +#------ 00011010: f4's .got.plt entry [R_ARM_JUMP_SLOT] +#------ 00011014: f1's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011018: f3's .igot.plt entry [R_ARM_IRELATIVE] +#------ 0001101c: .got entry for foo [R_ARM_RELATIVE] +#------------------------------------------------------------------------------ -+ 11010 00900000 00a00000 04a00000 00000100 .* ++ 11010 (00900000 00a00000 04a00000 00000100|00009000 0000a000 0000a004 00010000) .* +#------------------------------------------------------------------------------ +#------ 00011020: .got entry for foo [R_ARM_RELATIVE] +#------ 00011024: .got entry for f2 [R_ARM_GLOB_DAT] +#------ 00011028: .got entry for f4 [R_ARM_GLOB_DAT] +#------------------------------------------------------------------------------ -+ 11020 00000100 00000000 00000000 .* ++ 11020 (00000100|00010000) 00000000 00000000 .* diff --git a/ld/testsuite/ld-arm/ifunc-7.rd b/ld/testsuite/ld-arm/ifunc-7.rd new file mode 100644 index 0000000..a29b184 @@ -2751060,19 +2765801,19 @@ index 0000000..85ffb68 + .size arm,.-arm diff --git a/ld/testsuite/ld-arm/ifunc-8.dd b/ld/testsuite/ld-arm/ifunc-8.dd new file mode 100644 -index 0000000..5b255e2 +index 0000000..3cca17c --- /dev/null +++ b/ld/testsuite/ld-arm/ifunc-8.dd -@@ -0,0 +1,1017 @@ +@@ -0,0 +1,1029 @@ + +.* + + +Disassembly of section \.plt: + -+00009000 <\.plt>: ++00009000 : + 9000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) -+ 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 ++ 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 + 9008: e08fe00e add lr, pc, lr + 900c: e5bef008 ldr pc, \[lr, #8\]! +#------------------------------------------------------------------------------ @@ -2751082,6 +2765823,7 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ thumb entry to atf2's .plt entry +#------------------------------------------------------------------------------ ++00009014 : + 9014: 4778 bx pc + 9016: 46c0 nop ; \(mov r8, r8\) +#------------------------------------------------------------------------------ @@ -2751093,12 +2765835,14 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ aaf4's .plt entry +#------------------------------------------------------------------------------ ++00009024 : + 9024: e28fc600 add ip, pc, #0, 12 + 9028: e28cca07 add ip, ip, #28672 ; 0x7000 + 902c: e5bcffe4 ldr pc, \[ip, #4068\]! ; 0xfe4 +#------------------------------------------------------------------------------ +#------ thumb entry to ttf2's .plt entry +#------------------------------------------------------------------------------ ++00009030 : + 9030: 4778 bx pc + 9032: 46c0 nop ; \(mov r8, r8\) +#------------------------------------------------------------------------------ @@ -2751110,6 +2765854,7 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ thumb entry to tbf2's .plt entry +#------------------------------------------------------------------------------ ++00009040 : + 9040: 4778 bx pc + 9042: 46c0 nop ; \(mov r8, r8\) +#------------------------------------------------------------------------------ @@ -2751121,18 +2765866,21 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ taf2's .plt entry +#------------------------------------------------------------------------------ ++00009050 : + 9050: e28fc600 add ip, pc, #0, 12 + 9054: e28cca07 add ip, ip, #28672 ; 0x7000 + 9058: e5bcffc4 ldr pc, \[ip, #4036\]! ; 0xfc4 +#------------------------------------------------------------------------------ +#------ aaf2's .plt entry +#------------------------------------------------------------------------------ ++0000905c : + 905c: e28fc600 add ip, pc, #0, 12 + 9060: e28cca07 add ip, ip, #28672 ; 0x7000 + 9064: e5bcffbc ldr pc, \[ip, #4028\]! ; 0xfbc +#------------------------------------------------------------------------------ +#------ thumb entry to abf4's .plt entry +#------------------------------------------------------------------------------ ++00009068 : + 9068: 4778 bx pc + 906a: 46c0 nop ; \(mov r8, r8\) +#------------------------------------------------------------------------------ @@ -2751144,6 +2765892,7 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ thumb entry to tbf4's .plt entry +#------------------------------------------------------------------------------ ++00009078 : + 9078: 4778 bx pc + 907a: 46c0 nop ; \(mov r8, r8\) +#------------------------------------------------------------------------------ @@ -2751155,6 +2765904,7 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ thumb entry to ttf4's .plt entry +#------------------------------------------------------------------------------ ++00009088 : + 9088: 4778 bx pc + 908a: 46c0 nop ; \(mov r8, r8\) +#------------------------------------------------------------------------------ @@ -2751166,6 +2765916,7 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ thumb entry to atf4's .plt entry +#------------------------------------------------------------------------------ ++00009098 : + 9098: 4778 bx pc + 909a: 46c0 nop ; \(mov r8, r8\) +#------------------------------------------------------------------------------ @@ -2751177,12 +2765928,14 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ taf4's .plt entry +#------------------------------------------------------------------------------ ++000090a8 : + 90a8: e28fc600 add ip, pc, #0, 12 + 90ac: e28cca07 add ip, ip, #28672 ; 0x7000 + 90b0: e5bcff84 ldr pc, \[ip, #3972\]! ; 0xf84 +#------------------------------------------------------------------------------ +#------ thumb entry to abf2's .plt entry +#------------------------------------------------------------------------------ ++000090b4 : + 90b4: 4778 bx pc + 90b6: 46c0 nop ; \(mov r8, r8\) +#------------------------------------------------------------------------------ @@ -2751365,15 +2766118,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ aaf1's .iplt entry +#------------------------------------------------------------------------------ -+ a044: ebfffc1e bl 90c4 ++ a044: ebfffc1e bl 90c4 +#------------------------------------------------------------------------------ +#------ aaf1's .iplt entry +#------------------------------------------------------------------------------ -+ a048: eafffc1d b 90c4 ++ a048: eafffc1d b 90c4 +#------------------------------------------------------------------------------ +#------ aaf1's .iplt entry +#------------------------------------------------------------------------------ -+ a04c: 0afffc1c beq 90c4 ++ a04c: 0afffc1c beq 90c4 + a050: e59f4000 ldr r4, \[pc\] ; a058 + a054: e59f4000 ldr r4, \[pc\] ; a05c +#------------------------------------------------------------------------------ @@ -2751387,15 +2766140,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ taf1's .iplt entry +#------------------------------------------------------------------------------ -+ a060: ebfffc22 bl 90f0 ++ a060: ebfffc22 bl 90f0 +#------------------------------------------------------------------------------ +#------ taf1's .iplt entry +#------------------------------------------------------------------------------ -+ a064: eafffc21 b 90f0 ++ a064: eafffc21 b 90f0 +#------------------------------------------------------------------------------ +#------ taf1's .iplt entry +#------------------------------------------------------------------------------ -+ a068: 0afffc20 beq 90f0 ++ a068: 0afffc20 beq 90f0 + a06c: e59f4000 ldr r4, \[pc\] ; a074 + a070: e59f4000 ldr r4, \[pc\] ; a078 +#------------------------------------------------------------------------------ @@ -2751409,15 +2766162,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ abf1's .iplt entry +#------------------------------------------------------------------------------ -+ a07c: ebfffc18 bl 90e4 ++ a07c: ebfffc18 bl 90e4 +#------------------------------------------------------------------------------ +#------ abf1's .iplt entry +#------------------------------------------------------------------------------ -+ a080: eafffc17 b 90e4 ++ a080: eafffc17 b 90e4 +#------------------------------------------------------------------------------ +#------ abf1's .iplt entry +#------------------------------------------------------------------------------ -+ a084: 0afffc16 beq 90e4 ++ a084: 0afffc16 beq 90e4 + a088: e59f4000 ldr r4, \[pc\] ; a090 + a08c: e59f4000 ldr r4, \[pc\] ; a094 +#------------------------------------------------------------------------------ @@ -2751431,15 +2766184,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ tbf1's .iplt entry +#------------------------------------------------------------------------------ -+ a098: ebfffc1c bl 9110 ++ a098: ebfffc1c bl 9110 +#------------------------------------------------------------------------------ +#------ tbf1's .iplt entry +#------------------------------------------------------------------------------ -+ a09c: eafffc1b b 9110 ++ a09c: eafffc1b b 9110 +#------------------------------------------------------------------------------ +#------ tbf1's .iplt entry +#------------------------------------------------------------------------------ -+ a0a0: 0afffc1a beq 9110 ++ a0a0: 0afffc1a beq 9110 + a0a4: e59f4000 ldr r4, \[pc\] ; a0ac + a0a8: e59f4000 ldr r4, \[pc\] ; a0b0 +#------------------------------------------------------------------------------ @@ -2751453,15 +2766206,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ aaf2's .plt entry +#------------------------------------------------------------------------------ -+ a0b4: ebfffbe8 bl 905c ++ a0b4: ebfffbe8 bl 905c +#------------------------------------------------------------------------------ +#------ aaf2's .plt entry +#------------------------------------------------------------------------------ -+ a0b8: eafffbe7 b 905c ++ a0b8: eafffbe7 b 905c +#------------------------------------------------------------------------------ +#------ aaf2's .plt entry +#------------------------------------------------------------------------------ -+ a0bc: 0afffbe6 beq 905c ++ a0bc: 0afffbe6 beq 905c + a0c0: e59f4000 ldr r4, \[pc\] ; a0c8 + a0c4: e59f4000 ldr r4, \[pc\] ; a0cc +#------------------------------------------------------------------------------ @@ -2751475,15 +2766228,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ taf2's .plt entry +#------------------------------------------------------------------------------ -+ a0d0: ebfffbde bl 9050 ++ a0d0: ebfffbde bl 9050 +#------------------------------------------------------------------------------ +#------ taf2's .plt entry +#------------------------------------------------------------------------------ -+ a0d4: eafffbdd b 9050 ++ a0d4: eafffbdd b 9050 +#------------------------------------------------------------------------------ +#------ taf2's .plt entry +#------------------------------------------------------------------------------ -+ a0d8: 0afffbdc beq 9050 ++ a0d8: 0afffbdc beq 9050 + a0dc: e59f4000 ldr r4, \[pc\] ; a0e4 + a0e0: e59f4000 ldr r4, \[pc\] ; a0e8 +#------------------------------------------------------------------------------ @@ -2751497,15 +2766250,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ abf2's .plt entry +#------------------------------------------------------------------------------ -+ a0ec: ebfffbf1 bl 90b8 ++ a0ec: ebfffbf1 bl 90b8 +#------------------------------------------------------------------------------ +#------ abf2's .plt entry +#------------------------------------------------------------------------------ -+ a0f0: eafffbf0 b 90b8 ++ a0f0: eafffbf0 b 90b8 +#------------------------------------------------------------------------------ +#------ abf2's .plt entry +#------------------------------------------------------------------------------ -+ a0f4: 0afffbef beq 90b8 ++ a0f4: 0afffbef beq 90b8 + a0f8: e59f4000 ldr r4, \[pc\] ; a100 + a0fc: e59f4000 ldr r4, \[pc\] ; a104 +#------------------------------------------------------------------------------ @@ -2751519,15 +2766272,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ tbf2's .plt entry +#------------------------------------------------------------------------------ -+ a108: ebfffbcd bl 9044 ++ a108: ebfffbcd bl 9044 +#------------------------------------------------------------------------------ +#------ tbf2's .plt entry +#------------------------------------------------------------------------------ -+ a10c: eafffbcc b 9044 ++ a10c: eafffbcc b 9044 +#------------------------------------------------------------------------------ +#------ tbf2's .plt entry +#------------------------------------------------------------------------------ -+ a110: 0afffbcb beq 9044 ++ a110: 0afffbcb beq 9044 + a114: e59f4000 ldr r4, \[pc\] ; a11c + a118: e59f4000 ldr r4, \[pc\] ; a120 +#------------------------------------------------------------------------------ @@ -2751541,15 +2766294,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ aaf3's .iplt entry +#------------------------------------------------------------------------------ -+ a124: ebfffc0f bl 9168 ++ a124: ebfffc0f bl 9168 +#------------------------------------------------------------------------------ +#------ aaf3's .iplt entry +#------------------------------------------------------------------------------ -+ a128: eafffc0e b 9168 ++ a128: eafffc0e b 9168 +#------------------------------------------------------------------------------ +#------ aaf3's .iplt entry +#------------------------------------------------------------------------------ -+ a12c: 0afffc0d beq 9168 ++ a12c: 0afffc0d beq 9168 + a130: e59f4000 ldr r4, \[pc\] ; a138 + a134: e59f4000 ldr r4, \[pc\] ; a13c +#------------------------------------------------------------------------------ @@ -2751563,15 +2766316,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ taf3's .iplt entry +#------------------------------------------------------------------------------ -+ a140: ebfffc05 bl 915c ++ a140: ebfffc05 bl 915c +#------------------------------------------------------------------------------ +#------ taf3's .iplt entry +#------------------------------------------------------------------------------ -+ a144: eafffc04 b 915c ++ a144: eafffc04 b 915c +#------------------------------------------------------------------------------ +#------ taf3's .iplt entry +#------------------------------------------------------------------------------ -+ a148: 0afffc03 beq 915c ++ a148: 0afffc03 beq 915c + a14c: e59f4000 ldr r4, \[pc\] ; a154 + a150: e59f4000 ldr r4, \[pc\] ; a158 +#------------------------------------------------------------------------------ @@ -2751585,15 +2766338,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ abf3's .iplt entry +#------------------------------------------------------------------------------ -+ a15c: ebfffbf3 bl 9130 ++ a15c: ebfffbf3 bl 9130 +#------------------------------------------------------------------------------ +#------ abf3's .iplt entry +#------------------------------------------------------------------------------ -+ a160: eafffbf2 b 9130 ++ a160: eafffbf2 b 9130 +#------------------------------------------------------------------------------ +#------ abf3's .iplt entry +#------------------------------------------------------------------------------ -+ a164: 0afffbf1 beq 9130 ++ a164: 0afffbf1 beq 9130 + a168: e59f4000 ldr r4, \[pc\] ; a170 + a16c: e59f4000 ldr r4, \[pc\] ; a174 +#------------------------------------------------------------------------------ @@ -2751607,15 +2766360,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ tbf3's .iplt entry +#------------------------------------------------------------------------------ -+ a178: ebfffbf4 bl 9150 ++ a178: ebfffbf4 bl 9150 +#------------------------------------------------------------------------------ +#------ tbf3's .iplt entry +#------------------------------------------------------------------------------ -+ a17c: eafffbf3 b 9150 ++ a17c: eafffbf3 b 9150 +#------------------------------------------------------------------------------ +#------ tbf3's .iplt entry +#------------------------------------------------------------------------------ -+ a180: 0afffbf2 beq 9150 ++ a180: 0afffbf2 beq 9150 + a184: e59f4000 ldr r4, \[pc\] ; a18c + a188: e59f4000 ldr r4, \[pc\] ; a190 +#------------------------------------------------------------------------------ @@ -2751629,15 +2766382,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ aaf4's .plt entry +#------------------------------------------------------------------------------ -+ a194: ebfffba2 bl 9024 ++ a194: ebfffba2 bl 9024 +#------------------------------------------------------------------------------ +#------ aaf4's .plt entry +#------------------------------------------------------------------------------ -+ a198: eafffba1 b 9024 ++ a198: eafffba1 b 9024 +#------------------------------------------------------------------------------ +#------ aaf4's .plt entry +#------------------------------------------------------------------------------ -+ a19c: 0afffba0 beq 9024 ++ a19c: 0afffba0 beq 9024 + a1a0: e59f4000 ldr r4, \[pc\] ; a1a8 + a1a4: e59f4000 ldr r4, \[pc\] ; a1ac +#------------------------------------------------------------------------------ @@ -2751651,15 +2766404,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ taf4's .plt entry +#------------------------------------------------------------------------------ -+ a1b0: ebfffbbc bl 90a8 ++ a1b0: ebfffbbc bl 90a8 +#------------------------------------------------------------------------------ +#------ taf4's .plt entry +#------------------------------------------------------------------------------ -+ a1b4: eafffbbb b 90a8 ++ a1b4: eafffbbb b 90a8 +#------------------------------------------------------------------------------ +#------ taf4's .plt entry +#------------------------------------------------------------------------------ -+ a1b8: 0afffbba beq 90a8 ++ a1b8: 0afffbba beq 90a8 + a1bc: e59f4000 ldr r4, \[pc\] ; a1c4 + a1c0: e59f4000 ldr r4, \[pc\] ; a1c8 +#------------------------------------------------------------------------------ @@ -2751673,15 +2766426,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ abf4's .plt entry +#------------------------------------------------------------------------------ -+ a1cc: ebfffba6 bl 906c ++ a1cc: ebfffba6 bl 906c +#------------------------------------------------------------------------------ +#------ abf4's .plt entry +#------------------------------------------------------------------------------ -+ a1d0: eafffba5 b 906c ++ a1d0: eafffba5 b 906c +#------------------------------------------------------------------------------ +#------ abf4's .plt entry +#------------------------------------------------------------------------------ -+ a1d4: 0afffba4 beq 906c ++ a1d4: 0afffba4 beq 906c + a1d8: e59f4000 ldr r4, \[pc\] ; a1e0 + a1dc: e59f4000 ldr r4, \[pc\] ; a1e4 +#------------------------------------------------------------------------------ @@ -2751695,15 +2766448,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ tbf4's .plt entry +#------------------------------------------------------------------------------ -+ a1e8: ebfffba3 bl 907c ++ a1e8: ebfffba3 bl 907c +#------------------------------------------------------------------------------ +#------ tbf4's .plt entry +#------------------------------------------------------------------------------ -+ a1ec: eafffba2 b 907c ++ a1ec: eafffba2 b 907c +#------------------------------------------------------------------------------ +#------ tbf4's .plt entry +#------------------------------------------------------------------------------ -+ a1f0: 0afffba1 beq 907c ++ a1f0: 0afffba1 beq 907c + a1f4: e59f4000 ldr r4, \[pc\] ; a1fc + a1f8: e59f4000 ldr r4, \[pc\] ; a200 +#------------------------------------------------------------------------------ @@ -2751732,15 +2766485,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ atf1's .iplt entry +#------------------------------------------------------------------------------ -+ a21c: f7fe ef5a blx 90d4 ++ a21c: f7fe ef5a blx 90d4 +#------------------------------------------------------------------------------ +#------ thumb entry to atf1's .iplt entry +#------------------------------------------------------------------------------ -+ a220: f7fe bf56 b\.w 90d0 ++ a220: f7fe bf56 b\.w 90d0 +#------------------------------------------------------------------------------ +#------ thumb entry to atf1's .iplt entry +#------------------------------------------------------------------------------ -+ a224: f43e af54 beq\.w 90d0 ++ a224: f43e af54 beq\.w 90d0 + a228: 4c00 ldr r4, \[pc, #0\] ; \(a22c <_thumb\+0x28>\) + a22a: 4c01 ldr r4, \[pc, #4\] ; \(a230 <_thumb\+0x2c>\) +#------------------------------------------------------------------------------ @@ -2751754,15 +2766507,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ ttf1's .iplt entry +#------------------------------------------------------------------------------ -+ a234: f7fe ef64 blx 9100 ++ a234: f7fe ef64 blx 9100 +#------------------------------------------------------------------------------ +#------ thumb entry to ttf1's .iplt entry +#------------------------------------------------------------------------------ -+ a238: f7fe bf60 b\.w 90fc ++ a238: f7fe bf60 b\.w 90fc +#------------------------------------------------------------------------------ +#------ thumb entry to ttf1's .iplt entry +#------------------------------------------------------------------------------ -+ a23c: f43e af5e beq\.w 90fc ++ a23c: f43e af5e beq\.w 90fc + a240: 4c00 ldr r4, \[pc, #0\] ; \(a244 <_thumb\+0x40>\) + a242: 4c01 ldr r4, \[pc, #4\] ; \(a248 <_thumb\+0x44>\) +#------------------------------------------------------------------------------ @@ -2751776,15 +2766529,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ abf1's .iplt entry +#------------------------------------------------------------------------------ -+ a24c: f7fe ef4a blx 90e4 ++ a24c: f7fe ef4a blx 90e4 +#------------------------------------------------------------------------------ +#------ thumb entry to abf1's .iplt entry +#------------------------------------------------------------------------------ -+ a250: f7fe bf46 b\.w 90e0 ++ a250: f7fe bf46 b\.w 90e0 +#------------------------------------------------------------------------------ +#------ thumb entry to abf1's .iplt entry +#------------------------------------------------------------------------------ -+ a254: f43e af44 beq\.w 90e0 ++ a254: f43e af44 beq\.w 90e0 + a258: 4c00 ldr r4, \[pc, #0\] ; \(a25c <_thumb\+0x58>\) + a25a: 4c01 ldr r4, \[pc, #4\] ; \(a260 <_thumb\+0x5c>\) +#------------------------------------------------------------------------------ @@ -2751798,15 +2766551,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ tbf1's .iplt entry +#------------------------------------------------------------------------------ -+ a264: f7fe ef54 blx 9110 ++ a264: f7fe ef54 blx 9110 +#------------------------------------------------------------------------------ +#------ thumb entry to tbf1's .iplt entry +#------------------------------------------------------------------------------ -+ a268: f7fe bf50 b\.w 910c ++ a268: f7fe bf50 b\.w 910c +#------------------------------------------------------------------------------ +#------ thumb entry to tbf1's .iplt entry +#------------------------------------------------------------------------------ -+ a26c: f43e af4e beq\.w 910c ++ a26c: f43e af4e beq\.w 910c + a270: 4c00 ldr r4, \[pc, #0\] ; \(a274 <_thumb\+0x70>\) + a272: 4c01 ldr r4, \[pc, #4\] ; \(a278 <_thumb\+0x74>\) +#------------------------------------------------------------------------------ @@ -2751820,15 +2766573,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ atf2's .plt entry +#------------------------------------------------------------------------------ -+ a27c: f7fe eecc blx 9018 ++ a27c: f7fe eecc blx 9018 +#------------------------------------------------------------------------------ +#------ thumb entry to atf2's .plt entry +#------------------------------------------------------------------------------ -+ a280: f7fe bec8 b\.w 9014 ++ a280: f7fe bec8 b\.w 9014 +#------------------------------------------------------------------------------ +#------ thumb entry to atf2's .plt entry +#------------------------------------------------------------------------------ -+ a284: f43e aec6 beq\.w 9014 ++ a284: f43e aec6 beq\.w 9014 + a288: 4c00 ldr r4, \[pc, #0\] ; \(a28c <_thumb\+0x88>\) + a28a: 4c01 ldr r4, \[pc, #4\] ; \(a290 <_thumb\+0x8c>\) +#------------------------------------------------------------------------------ @@ -2751842,15 +2766595,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ ttf2's .plt entry +#------------------------------------------------------------------------------ -+ a294: f7fe eece blx 9034 ++ a294: f7fe eece blx 9034 +#------------------------------------------------------------------------------ +#------ thumb entry to ttf2's .plt entry +#------------------------------------------------------------------------------ -+ a298: f7fe beca b\.w 9030 ++ a298: f7fe beca b\.w 9030 +#------------------------------------------------------------------------------ +#------ thumb entry to ttf2's .plt entry +#------------------------------------------------------------------------------ -+ a29c: f43e aec8 beq\.w 9030 ++ a29c: f43e aec8 beq\.w 9030 + a2a0: 4c00 ldr r4, \[pc, #0\] ; \(a2a4 <_thumb\+0xa0>\) + a2a2: 4c01 ldr r4, \[pc, #4\] ; \(a2a8 <_thumb\+0xa4>\) +#------------------------------------------------------------------------------ @@ -2751864,15 +2766617,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ abf2's .plt entry +#------------------------------------------------------------------------------ -+ a2ac: f7fe ef04 blx 90b8 ++ a2ac: f7fe ef04 blx 90b8 +#------------------------------------------------------------------------------ +#------ thumb entry to abf2's .plt entry +#------------------------------------------------------------------------------ -+ a2b0: f7fe bf00 b\.w 90b4 ++ a2b0: f7fe bf00 b\.w 90b4 +#------------------------------------------------------------------------------ +#------ thumb entry to abf2's .plt entry +#------------------------------------------------------------------------------ -+ a2b4: f43e aefe beq\.w 90b4 ++ a2b4: f43e aefe beq\.w 90b4 + a2b8: 4c00 ldr r4, \[pc, #0\] ; \(a2bc <_thumb\+0xb8>\) + a2ba: 4c01 ldr r4, \[pc, #4\] ; \(a2c0 <_thumb\+0xbc>\) +#------------------------------------------------------------------------------ @@ -2751886,15 +2766639,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ tbf2's .plt entry +#------------------------------------------------------------------------------ -+ a2c4: f7fe eebe blx 9044 ++ a2c4: f7fe eebe blx 9044 +#------------------------------------------------------------------------------ +#------ thumb entry to tbf2's .plt entry +#------------------------------------------------------------------------------ -+ a2c8: f7fe beba b\.w 9040 ++ a2c8: f7fe beba b\.w 9040 +#------------------------------------------------------------------------------ +#------ thumb entry to tbf2's .plt entry +#------------------------------------------------------------------------------ -+ a2cc: f43e aeb8 beq\.w 9040 ++ a2cc: f43e aeb8 beq\.w 9040 + a2d0: 4c00 ldr r4, \[pc, #0\] ; \(a2d4 <_thumb\+0xd0>\) + a2d2: 4c01 ldr r4, \[pc, #4\] ; \(a2d8 <_thumb\+0xd4>\) +#------------------------------------------------------------------------------ @@ -2751908,15 +2766661,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ atf3's .iplt entry +#------------------------------------------------------------------------------ -+ a2dc: f7fe ef20 blx 9120 ++ a2dc: f7fe ef20 blx 9120 +#------------------------------------------------------------------------------ +#------ thumb entry to atf3's .iplt entry +#------------------------------------------------------------------------------ -+ a2e0: f7fe bf1c b\.w 911c ++ a2e0: f7fe bf1c b\.w 911c +#------------------------------------------------------------------------------ +#------ thumb entry to atf3's .iplt entry +#------------------------------------------------------------------------------ -+ a2e4: f43e af1a beq\.w 911c ++ a2e4: f43e af1a beq\.w 911c + a2e8: 4c00 ldr r4, \[pc, #0\] ; \(a2ec <_thumb\+0xe8>\) + a2ea: 4c01 ldr r4, \[pc, #4\] ; \(a2f0 <_thumb\+0xec>\) +#------------------------------------------------------------------------------ @@ -2751930,15 +2766683,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ ttf3's .iplt entry +#------------------------------------------------------------------------------ -+ a2f4: f7fe ef24 blx 9140 ++ a2f4: f7fe ef24 blx 9140 +#------------------------------------------------------------------------------ +#------ thumb entry to ttf3's .iplt entry +#------------------------------------------------------------------------------ -+ a2f8: f7fe bf20 b\.w 913c ++ a2f8: f7fe bf20 b\.w 913c +#------------------------------------------------------------------------------ +#------ thumb entry to ttf3's .iplt entry +#------------------------------------------------------------------------------ -+ a2fc: f43e af1e beq\.w 913c ++ a2fc: f43e af1e beq\.w 913c + a300: 4c00 ldr r4, \[pc, #0\] ; \(a304 <_thumb\+0x100>\) + a302: 4c01 ldr r4, \[pc, #4\] ; \(a308 <_thumb\+0x104>\) +#------------------------------------------------------------------------------ @@ -2751952,15 +2766705,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ abf3's .iplt entry +#------------------------------------------------------------------------------ -+ a30c: f7fe ef10 blx 9130 ++ a30c: f7fe ef10 blx 9130 +#------------------------------------------------------------------------------ +#------ thumb entry to abf3's .iplt entry +#------------------------------------------------------------------------------ -+ a310: f7fe bf0c b\.w 912c ++ a310: f7fe bf0c b\.w 912c +#------------------------------------------------------------------------------ +#------ thumb entry to abf3's .iplt entry +#------------------------------------------------------------------------------ -+ a314: f43e af0a beq\.w 912c ++ a314: f43e af0a beq\.w 912c + a318: 4c00 ldr r4, \[pc, #0\] ; \(a31c <_thumb\+0x118>\) + a31a: 4c01 ldr r4, \[pc, #4\] ; \(a320 <_thumb\+0x11c>\) +#------------------------------------------------------------------------------ @@ -2751974,15 +2766727,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ tbf3's .iplt entry +#------------------------------------------------------------------------------ -+ a324: f7fe ef14 blx 9150 ++ a324: f7fe ef14 blx 9150 +#------------------------------------------------------------------------------ +#------ thumb entry to tbf3's .iplt entry +#------------------------------------------------------------------------------ -+ a328: f7fe bf10 b\.w 914c ++ a328: f7fe bf10 b\.w 914c +#------------------------------------------------------------------------------ +#------ thumb entry to tbf3's .iplt entry +#------------------------------------------------------------------------------ -+ a32c: f43e af0e beq\.w 914c ++ a32c: f43e af0e beq\.w 914c + a330: 4c00 ldr r4, \[pc, #0\] ; \(a334 <_thumb\+0x130>\) + a332: 4c01 ldr r4, \[pc, #4\] ; \(a338 <_thumb\+0x134>\) +#------------------------------------------------------------------------------ @@ -2751996,15 +2766749,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ atf4's .plt entry +#------------------------------------------------------------------------------ -+ a33c: f7fe eeae blx 909c ++ a33c: f7fe eeae blx 909c +#------------------------------------------------------------------------------ +#------ thumb entry to atf4's .plt entry +#------------------------------------------------------------------------------ -+ a340: f7fe beaa b\.w 9098 ++ a340: f7fe beaa b\.w 9098 +#------------------------------------------------------------------------------ +#------ thumb entry to atf4's .plt entry +#------------------------------------------------------------------------------ -+ a344: f43e aea8 beq\.w 9098 ++ a344: f43e aea8 beq\.w 9098 + a348: 4c00 ldr r4, \[pc, #0\] ; \(a34c <_thumb\+0x148>\) + a34a: 4c01 ldr r4, \[pc, #4\] ; \(a350 <_thumb\+0x14c>\) +#------------------------------------------------------------------------------ @@ -2752018,15 +2766771,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ ttf4's .plt entry +#------------------------------------------------------------------------------ -+ a354: f7fe ee9a blx 908c ++ a354: f7fe ee9a blx 908c +#------------------------------------------------------------------------------ +#------ thumb entry to ttf4's .plt entry +#------------------------------------------------------------------------------ -+ a358: f7fe be96 b\.w 9088 ++ a358: f7fe be96 b\.w 9088 +#------------------------------------------------------------------------------ +#------ thumb entry to ttf4's .plt entry +#------------------------------------------------------------------------------ -+ a35c: f43e ae94 beq\.w 9088 ++ a35c: f43e ae94 beq\.w 9088 + a360: 4c00 ldr r4, \[pc, #0\] ; \(a364 <_thumb\+0x160>\) + a362: 4c01 ldr r4, \[pc, #4\] ; \(a368 <_thumb\+0x164>\) +#------------------------------------------------------------------------------ @@ -2752040,15 +2766793,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ abf4's .plt entry +#------------------------------------------------------------------------------ -+ a36c: f7fe ee7e blx 906c ++ a36c: f7fe ee7e blx 906c +#------------------------------------------------------------------------------ +#------ thumb entry to abf4's .plt entry +#------------------------------------------------------------------------------ -+ a370: f7fe be7a b\.w 9068 ++ a370: f7fe be7a b\.w 9068 +#------------------------------------------------------------------------------ +#------ thumb entry to abf4's .plt entry +#------------------------------------------------------------------------------ -+ a374: f43e ae78 beq\.w 9068 ++ a374: f43e ae78 beq\.w 9068 + a378: 4c00 ldr r4, \[pc, #0\] ; \(a37c <_thumb\+0x178>\) + a37a: 4c01 ldr r4, \[pc, #4\] ; \(a380 <_thumb\+0x17c>\) +#------------------------------------------------------------------------------ @@ -2752062,15 +2766815,15 @@ index 0000000..5b255e2 +#------------------------------------------------------------------------------ +#------ tbf4's .plt entry +#------------------------------------------------------------------------------ -+ a384: f7fe ee7a blx 907c ++ a384: f7fe ee7a blx 907c +#------------------------------------------------------------------------------ +#------ thumb entry to tbf4's .plt entry +#------------------------------------------------------------------------------ -+ a388: f7fe be76 b\.w 9078 ++ a388: f7fe be76 b\.w 9078 +#------------------------------------------------------------------------------ +#------ thumb entry to tbf4's .plt entry +#------------------------------------------------------------------------------ -+ a38c: f43e ae74 beq\.w 9078 ++ a38c: f43e ae74 beq\.w 9078 + a390: 4c00 ldr r4, \[pc, #0\] ; \(a394 <_thumb\+0x190>\) + a392: 4c01 ldr r4, \[pc, #4\] ; \(a398 <_thumb\+0x194>\) +#------------------------------------------------------------------------------ @@ -2752083,7 +2766836,7 @@ index 0000000..5b255e2 + a398: 00006cf8 \.word 0x00006cf8 diff --git a/ld/testsuite/ld-arm/ifunc-8.gd b/ld/testsuite/ld-arm/ifunc-8.gd new file mode 100644 -index 0000000..7efefa0 +index 0000000..356f042 --- /dev/null +++ b/ld/testsuite/ld-arm/ifunc-8.gd @@ -0,0 +1,167 @@ @@ -2752097,28 +2766850,28 @@ index 0000000..7efefa0 +#------ 00010008: contains PC-relative offset of aaf1's .iplt entry +#------ 0001000c: contains atf1 [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 10000 44332211 00a00000 bc90ffff 04a00000 .* ++ 10000 (44332211 00a00000 bc90ffff 04a00000|11223344 0000a000 ffff90bc 0000a004) .* +#------------------------------------------------------------------------------ +#------ 00010010: contains PC-relative offset of atf1's .iplt entry +#------ 00010014: contains abf1 [R_ARM_IRELATIVE] +#------ 00010018: contains PC-relative offset of abf1's .iplt entry +#------ 0001001c: contains taf1 [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 10010 c490ffff 08a00000 cc90ffff 0da00000 .* ++ 10010 (c490ffff 08a00000 cc90ffff 0da00000|ffff90c4 0000a008 ffff90cc 0000a00d) .* +#------------------------------------------------------------------------------ +#------ 00010020: contains PC-relative offset of taf1's .iplt entry +#------ 00010024: contains ttf1 [R_ARM_IRELATIVE] +#------ 00010028: contains PC-relative offset of ttf1's .iplt entry +#------ 0001002c: contains tbf1 [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 10020 d090ffff 0fa00000 d890ffff 11a00000 .* ++ 10020 (d090ffff 0fa00000 d890ffff 11a00000|ffff90d0 0000a00f ffff90d8 0000a011) .* +#------------------------------------------------------------------------------ +#------ 00010030: contains PC-relative offset of tbf1's .iplt entry +#------ 00010034: aaf2 [R_ARM_ABS32] +#------ 00010038: aaf2 [R_ARM_REL32] +#------ 0001003c: atf2 [R_ARM_ABS32] +#------------------------------------------------------------------------------ -+ 10030 e090ffff 00000000 00000000 00000000 .* ++ 10030 (e090ffff|ffff90e0) 00000000 00000000 00000000 .* +#------------------------------------------------------------------------------ +#------ 00010040: atf2 [R_ARM_REL32] +#------ 00010044: abf2 [R_ARM_ABS32] @@ -2752139,28 +2766892,28 @@ index 0000000..7efefa0 +#------ 00010068: contains PC-relative offset of aaf3's .iplt entry +#------ 0001006c: contains atf3 [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 10060 00000000 14a00000 0091ffff 18a00000 .* ++ 10060 00000000 (14a00000 0091ffff 18a00000|0000a014 ffff9100 0000a018) .* +#------------------------------------------------------------------------------ +#------ 00010070: contains PC-relative offset of atf3's .iplt entry +#------ 00010074: contains abf3 [R_ARM_IRELATIVE] +#------ 00010078: contains PC-relative offset of abf3's .iplt entry +#------ 0001007c: contains taf3 [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 10070 b090ffff 1ca00000 b890ffff 21a00000 .* ++ 10070 (b090ffff 1ca00000 b890ffff 21a00000|ffff90b0 0000a01c ffff90b8 0000a021) .* +#------------------------------------------------------------------------------ +#------ 00010080: contains PC-relative offset of taf3's .iplt entry +#------ 00010084: contains ttf3 [R_ARM_IRELATIVE] +#------ 00010088: contains PC-relative offset of ttf3's .iplt entry +#------ 0001008c: contains tbf3 [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 10080 dc90ffff 23a00000 b890ffff 25a00000 .* ++ 10080 (dc90ffff 23a00000 b890ffff 25a00000|ffff90dc 0000a023 ffff90b8 0000a025) .* +#------------------------------------------------------------------------------ +#------ 00010090: contains PC-relative offset of tbf3's .iplt entry +#------ 00010094: aaf4 [R_ARM_ABS32] +#------ 00010098: aaf4 [R_ARM_REL32] +#------ 0001009c: atf4 [R_ARM_ABS32] +#------------------------------------------------------------------------------ -+ 10090 c090ffff 00000000 00000000 00000000 .* ++ 10090 (c090ffff|ffff90c0) 00000000 00000000 00000000 .* +#------------------------------------------------------------------------------ +#------ 000100a0: atf4 [R_ARM_REL32] +#------ 000100a4: abf4 [R_ARM_ABS32] @@ -2752186,56 +2766939,56 @@ index 0000000..7efefa0 +#------ 00011008: reserved .got.plt entry +#------ 0001100c: atf2's .got.plt entry [R_ARM_JUMP_SLOT] +#------------------------------------------------------------------------------ -+ 11000 00200100 00000000 00000000 00900000 .* ++ 11000 (00200100 00000000 00000000 00900000|00012000 00000000 00000000 00009000) .* +#------------------------------------------------------------------------------ +#------ 00011010: aaf4's .got.plt entry [R_ARM_JUMP_SLOT] +#------ 00011014: ttf2's .got.plt entry [R_ARM_JUMP_SLOT] +#------ 00011018: tbf2's .got.plt entry [R_ARM_JUMP_SLOT] +#------ 0001101c: taf2's .got.plt entry [R_ARM_JUMP_SLOT] +#------------------------------------------------------------------------------ -+ 11010 00900000 00900000 00900000 00900000 .* ++ 11010 (00900000 00900000 00900000 00900000|00009000 00009000 00009000 00009000) .* +#------------------------------------------------------------------------------ +#------ 00011020: aaf2's .got.plt entry [R_ARM_JUMP_SLOT] +#------ 00011024: abf4's .got.plt entry [R_ARM_JUMP_SLOT] +#------ 00011028: tbf4's .got.plt entry [R_ARM_JUMP_SLOT] +#------ 0001102c: ttf4's .got.plt entry [R_ARM_JUMP_SLOT] +#------------------------------------------------------------------------------ -+ 11020 00900000 00900000 00900000 00900000 .* ++ 11020 (00900000 00900000 00900000 00900000|00009000 00009000 00009000 00009000) .* +#------------------------------------------------------------------------------ +#------ 00011030: atf4's .got.plt entry [R_ARM_JUMP_SLOT] +#------ 00011034: taf4's .got.plt entry [R_ARM_JUMP_SLOT] +#------ 00011038: abf2's .got.plt entry [R_ARM_JUMP_SLOT] +#------ 0001103c: aaf1's .igot.plt entry [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 11030 00900000 00900000 00900000 00a00000 .* ++ 11030 (00900000 00900000 00900000 00a00000|00009000 00009000 00009000 0000a000) .* +#------------------------------------------------------------------------------ +#------ 00011040: atf1's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011044: abf1's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011048: taf1's .igot.plt entry [R_ARM_IRELATIVE] +#------ 0001104c: ttf1's .igot.plt entry [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 11040 04a00000 08a00000 0da00000 0fa00000 .* ++ 11040 (04a00000 08a00000 0da00000 0fa00000|0000a004 0000a008 0000a00d 0000a00f) .* +#------------------------------------------------------------------------------ +#------ 00011050: tbf1's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011054: atf3's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011058: abf3's .igot.plt entry [R_ARM_IRELATIVE] +#------ 0001105c: ttf3's .igot.plt entry [R_ARM_IRELATIVE] +#------------------------------------------------------------------------------ -+ 11050 11a00000 18a00000 1ca00000 23a00000 .* ++ 11050 (11a00000 18a00000 1ca00000 23a00000|0000a011 0000a018 0000a01c 0000a023) .* +#------------------------------------------------------------------------------ +#------ 00011060: tbf3's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011064: taf3's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011068: aaf3's .igot.plt entry [R_ARM_IRELATIVE] +#------ 0001106c: .got entry for foo [R_ARM_RELATIVE] +#------------------------------------------------------------------------------ -+ 11060 25a00000 21a00000 14a00000 00000100 .* ++ 11060 (25a00000 21a00000 14a00000 00000100|0000a025 0000a021 0000a014 00010000) .* +#------------------------------------------------------------------------------ +#------ 00011070: .got entry for foo [R_ARM_RELATIVE] +#------ 00011074: .got entry for atf2 [R_ARM_GLOB_DAT] +#------ 00011078: .got entry for aaf4 [R_ARM_GLOB_DAT] +#------ 0001107c: .got entry for ttf2 [R_ARM_GLOB_DAT] +#------------------------------------------------------------------------------ -+ 11070 00000100 00000000 00000000 00000000 .* ++ 11070 (00000100|00010000) 00000000 00000000 00000000 .* +#------------------------------------------------------------------------------ +#------ 00011080: .got entry for tbf2 [R_ARM_GLOB_DAT] +#------ 00011084: .got entry for taf2 [R_ARM_GLOB_DAT] @@ -2752436,19 +2767189,19 @@ index 0000000..3947f7f + alldirs diff,f4 diff --git a/ld/testsuite/ld-arm/ifunc-9.dd b/ld/testsuite/ld-arm/ifunc-9.dd new file mode 100644 -index 0000000..36139d9 +index 0000000..af7ec4b --- /dev/null +++ b/ld/testsuite/ld-arm/ifunc-9.dd -@@ -0,0 +1,154 @@ +@@ -0,0 +1,155 @@ + +.* + + +Disassembly of section \.plt: + -+00009000 <\.plt>: ++00009000 : + 9000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) -+ 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 ++ 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 + 9008: e08fe00e add lr, pc, lr + 900c: e5bef008 ldr pc, \[lr, #8\]! +#------------------------------------------------------------------------------ @@ -2752458,6 +2767211,7 @@ index 0000000..36139d9 +#------------------------------------------------------------------------------ +#------ f2's .plt entry +#------------------------------------------------------------------------------ ++00009014 : + 9014: e28fc600 add ip, pc, #0, 12 + 9018: e28cca07 add ip, ip, #28672 ; 0x7000 + 901c: e5bcfff0 ldr pc, \[ip, #4080\]! ; 0xff0 @@ -2752513,7 +2767267,7 @@ index 0000000..36139d9 +#------------------------------------------------------------------------------ +#------ f1's .iplt entry +#------------------------------------------------------------------------------ -+ a034: ebfffbf9 bl 9020 ++ a034: ebfffbf9 bl 9020 + a038: e59f400c ldr r4, \[pc, #12\] ; a04c <_start\+0x44> + a03c: e59f400c ldr r4, \[pc, #12\] ; a050 <_start\+0x48> + a040: e59f400c ldr r4, \[pc, #12\] ; a054 <_start\+0x4c> @@ -2752542,7 +2767296,7 @@ index 0000000..36139d9 +#------------------------------------------------------------------------------ +#------ f2's .plt entry +#------------------------------------------------------------------------------ -+ a060: ebfffbeb bl 9014 ++ a060: ebfffbeb bl 9014 + a064: e59f400c ldr r4, \[pc, #12\] ; a078 <_start\+0x70> + a068: e59f400c ldr r4, \[pc, #12\] ; a07c <_start\+0x74> + a06c: e59f400c ldr r4, \[pc, #12\] ; a080 <_start\+0x78> @@ -2752596,7 +2767350,7 @@ index 0000000..36139d9 + a0b4: 00006f70 \.word 0x00006f70 diff --git a/ld/testsuite/ld-arm/ifunc-9.gd b/ld/testsuite/ld-arm/ifunc-9.gd new file mode 100644 -index 0000000..6f220d1 +index 0000000..54cd830 --- /dev/null +++ b/ld/testsuite/ld-arm/ifunc-9.gd @@ -0,0 +1,29 @@ @@ -2752607,7 +2767361,7 @@ index 0000000..6f220d1 +#------------------------------------------------------------------------------ +#------ 00010000: foo +#------------------------------------------------------------------------------ -+ 10000 44332211 .* ++ 10000 (44332211|11223344) .* +Contents of section \.got: +#------------------------------------------------------------------------------ +#------ 00011000: .got.plt @@ -2752615,20 +2767369,20 @@ index 0000000..6f220d1 +#------ 00011008: reserved .got.plt entry +#------ 0001100c: f2's .got.plt entry [R_ARM_JUMP_SLOT] +#------------------------------------------------------------------------------ -+ 11000 00200100 00000000 00000000 00900000 .* ++ 11000 (00200100 00000000 00000000 00900000|00012000 00000000 00000000 00009000) .* +#------------------------------------------------------------------------------ +#------ 00011010: f1's .igot.plt entry [R_ARM_IRELATIVE] +#------ 00011014: f3's .igot.plt pointer to 0xa004 [R_ARM_IRELATIVE] +#------ 00011018: .got entry for foo +#------ 0001101c: .got entry for f1's .iplt entry +#------------------------------------------------------------------------------ -+ 11010 00a00000 04a00000 00000100 20900000 .* ++ 11010 (00a00000 04a00000 00000100 20900000|0000a000 0000a004 00010000 00009020) .* +#------------------------------------------------------------------------------ +#------ 00011020: .got entry for foo +#------ 00011024: .got entry for f3 +#------ 00011028: .got entry for f2 [R_ARM_GLOB_DAT] +#------------------------------------------------------------------------------ -+ 11020 00000100 2c900000 00000000 .* ++ 11020 (00000100 2c900000|00010000 0000902c) 00000000 .* diff --git a/ld/testsuite/ld-arm/ifunc-9.rd b/ld/testsuite/ld-arm/ifunc-9.rd new file mode 100644 index 0000000..689f663 @@ -2752763,7 +2767517,7 @@ index 0000000..80cf6a2 +} diff --git a/ld/testsuite/ld-arm/jump-reloc-veneers-long.d b/ld/testsuite/ld-arm/jump-reloc-veneers-long.d new file mode 100644 -index 0000000..c69e688 +index 0000000..6bd5652 --- /dev/null +++ b/ld/testsuite/ld-arm/jump-reloc-veneers-long.d @@ -0,0 +1,21 @@ @@ -2752779,7 +2767533,7 @@ index 0000000..c69e688 +Disassembly of section .text: + +000080.. <[^>]*>: -+ 80..: b802f000 .word 0xb802f000 ++ 80..: (b802f000|f000b802) .word 0x(b802f000|f000b802) + 80..: 00000000 andeq r0, r0, r0 + +000080.. <[^>]*>: @@ -2752880,6 +2767634,41 @@ index 0000000..1e3ddf0 + .weak bar +bar: + bx lr +diff --git a/ld/testsuite/ld-arm/long-plt-format.d b/ld/testsuite/ld-arm/long-plt-format.d +new file mode 100644 +index 0000000..b0a1abc +--- /dev/null ++++ b/ld/testsuite/ld-arm/long-plt-format.d +@@ -0,0 +1,16 @@ ++.*: file format elf32-.* ++ ++ ++Disassembly of section .plt: ++ ++.* : ++ .*: .* ++ .*: .* ++ .*: .* ++ .*: .* ++ .*: .* .word .* ++.* : ++ .*: .* add ip, pc, #-268435456 ; 0xf0000000 ++ .*: .* add ip, ip, #0, 12 ++ .*: .* add ip, ip, #0, 20 ++ .*: .* ldr pc, [ip, #[0-9]*]! ; 0x.* +diff --git a/ld/testsuite/ld-arm/long-plt-format.s b/ld/testsuite/ld-arm/long-plt-format.s +new file mode 100644 +index 0000000..bb0c3a2 +--- /dev/null ++++ b/ld/testsuite/ld-arm/long-plt-format.s +@@ -0,0 +1,7 @@ ++ .globl _start ++ .type _start,%function ++ .globl foo ++_start: ++ bl foo(PLT) ++ .size _start,.-_start ++ diff --git a/ld/testsuite/ld-arm/main.s b/ld/testsuite/ld-arm/main.s new file mode 100644 index 0000000..046d19d @@ -2752896,10 +2767685,10 @@ index 0000000..046d19d + .size _start, . - _start diff --git a/ld/testsuite/ld-arm/mixed-app-v5.d b/ld/testsuite/ld-arm/mixed-app-v5.d new file mode 100644 -index 0000000..82013f3 +index 0000000..92b5ebb --- /dev/null +++ b/ld/testsuite/ld-arm/mixed-app-v5.d -@@ -0,0 +1,56 @@ +@@ -0,0 +1,58 @@ + +tmpdir/mixed-app-v5: file format elf32-(little|big)arm +architecture: armv4t, flags 0x00000112: @@ -2752908,15 +2767697,17 @@ index 0000000..82013f3 + +Disassembly of section .plt: + -+.* <.plt>: ++.* : + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) -+ .*: e59fe004 ldr lr, \[pc, #4\] ; .* <_start-0x28> ++ .*: e59fe004 ldr lr, \[pc, #4\] ; .* + .*: e08fe00e add lr, pc, lr + .*: e5bef008 ldr pc, \[lr, #8\]! + .*: .* ++.* : + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* ++.* : + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* @@ -2752950,7 +2767741,7 @@ index 0000000..82013f3 + +.* : + .*: b500 push {lr} -+ .*: f7ff efc. blx .* <_start-0x..> ++ .*: f7ff efc. blx .* + .*: bd00 pop {pc} + .*: 4770 bx lr + .*: 46c0 nop ; \(mov r8, r8\) @@ -2752958,10 +2767749,10 @@ index 0000000..82013f3 + .*: 46c0 nop ; \(mov r8, r8\) diff --git a/ld/testsuite/ld-arm/mixed-app.d b/ld/testsuite/ld-arm/mixed-app.d new file mode 100644 -index 0000000..4de8e57 +index 0000000..06166f0 --- /dev/null +++ b/ld/testsuite/ld-arm/mixed-app.d -@@ -0,0 +1,58 @@ +@@ -0,0 +1,60 @@ + +tmpdir/mixed-app: file format elf32-(little|big)arm +architecture: armv4t, flags 0x00000112: @@ -2752970,17 +2767761,19 @@ index 0000000..4de8e57 + +Disassembly of section .plt: + -+.* <.plt>: ++.* : + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) -+ .*: e59fe004 ldr lr, \[pc, #4\] ; .* <_start-0x28> ++ .*: e59fe004 ldr lr, \[pc, #4\] ; .* + .*: e08fe00e add lr, pc, lr + .*: e5bef008 ldr pc, \[lr, #8\]! + .*: .* ++.* : + .*: 4778 bx pc + .*: 46c0 nop ; \(mov r8, r8\) + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* ++.* : + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* @@ -2753014,7 +2767807,7 @@ index 0000000..4de8e57 + +.* : + .*: b500 push {lr} -+ .*: f7ff ffc. bl .* <_start-0x..> ++ .*: f7ff ffc. bl .* + .*: bd00 pop {pc} + .*: 4770 bx lr + .*: 46c0 nop ; \(mov r8, r8\) @@ -2753104,10 +2767897,10 @@ index 0000000..cfa35f5 + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +12 _bss_end__ diff --git a/ld/testsuite/ld-arm/mixed-lib.d b/ld/testsuite/ld-arm/mixed-lib.d new file mode 100644 -index 0000000..d3a9ff9 +index 0000000..6b344a5 --- /dev/null +++ b/ld/testsuite/ld-arm/mixed-lib.d -@@ -0,0 +1,38 @@ +@@ -0,0 +1,39 @@ + +tmpdir/mixed-lib.so: file format elf32-(little|big)arm +architecture: armv4t, flags 0x00000150: @@ -2753116,12 +2767909,13 @@ index 0000000..d3a9ff9 + +Disassembly of section .plt: + -+.* <.plt>: ++.* : + .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\) -+ .*: e59fe004 ldr lr, \[pc, #4\] ; .* ++ .*: e59fe004 ldr lr, \[pc, #4\] ; .* + .*: e08fe00e add lr, pc, lr + .*: e5bef008 ldr pc, \[lr, #8\]! + .*: .* ++.* : + .*: e28fc6.* add ip, pc, #.* + .*: e28cca.* add ip, ip, #.* ; 0x.* + .*: e5bcf.* ldr pc, \[ip, #.*\]!.* @@ -2753130,7 +2767924,7 @@ index 0000000..d3a9ff9 +.* : + .*: e1a0c00d mov ip, sp + .*: e92dd800 push {fp, ip, lr, pc} -+ .*: ebfffff. bl .* ++ .*: ebfffff. bl .* + .*: e89d6800 ldm sp, {fp, sp, lr} + .*: e12fff1e bx lr + .*: e1a00000 nop ; \(mov r0, r0\) @@ -2753401,7 +2768195,7 @@ index 0000000..ec1d6be + +.. +..: ........ +0 +NOTYPE +GLOBAL +DEFAULT +10 _bss_end__ diff --git a/ld/testsuite/ld-arm/reloc-boundaries.d b/ld/testsuite/ld-arm/reloc-boundaries.d new file mode 100644 -index 0000000..4bfaf0a +index 0000000..e71c5ae --- /dev/null +++ b/ld/testsuite/ld-arm/reloc-boundaries.d @@ -0,0 +1,6 @@ @@ -2753409,7 +2768203,7 @@ index 0000000..4bfaf0a +[^:]*: file format elf32-(little|big)arm.* + +Contents of section .text: -+ [0-9a-f]+ 80ff0080 ffff ...... ++ [0-9a-f]+ (80ff0080|80ff8000) ffff ...... +#... diff --git a/ld/testsuite/ld-arm/reloc-boundaries.s b/ld/testsuite/ld-arm/reloc-boundaries.s new file mode 100644 @@ -2754152,7 +2768946,7 @@ index 0000000..dba46af + do_calls diff --git a/ld/testsuite/ld-arm/thumb2-bl-undefweak.d b/ld/testsuite/ld-arm/thumb2-bl-undefweak.d new file mode 100644 -index 0000000..5c286be +index 0000000..c501aa2 --- /dev/null +++ b/ld/testsuite/ld-arm/thumb2-bl-undefweak.d @@ -0,0 +1,9 @@ @@ -2754164,7 +2768958,7 @@ index 0000000..5c286be +Disassembly of section .text: + +.* : -+ +[0-9a-f]+: .... .... bl. [0-9a-f]+ ++ +[0-9a-f]+: .... .... bl. [0-9a-f]+ diff --git a/ld/testsuite/ld-arm/thumb2-bl-undefweak.s b/ld/testsuite/ld-arm/thumb2-bl-undefweak.s new file mode 100644 index 0000000..5e70eea @@ -2754183,7 +2768977,7 @@ index 0000000..5e70eea + .weak bar diff --git a/ld/testsuite/ld-arm/thumb2-bl-undefweak1.d b/ld/testsuite/ld-arm/thumb2-bl-undefweak1.d new file mode 100644 -index 0000000..a6907f5 +index 0000000..806f66c --- /dev/null +++ b/ld/testsuite/ld-arm/thumb2-bl-undefweak1.d @@ -0,0 +1,9 @@ @@ -2754195,7 +2768989,7 @@ index 0000000..a6907f5 +Disassembly of section .text: + +.* : -+ +[0-9a-f]+: ........ bl [0-9a-f]+ ++ +[0-9a-f]+: ........ bl [0-9a-f]+ diff --git a/ld/testsuite/ld-arm/thumb2-bl-undefweak1.s b/ld/testsuite/ld-arm/thumb2-bl-undefweak1.s new file mode 100644 index 0000000..a302811 @@ -2757467,13 +2772261,12 @@ index 0000000..5ff87d3 +#... diff --git a/ld/testsuite/ld-auto-import/auto-import.exp b/ld/testsuite/ld-auto-import/auto-import.exp new file mode 100644 -index 0000000..f9a26e1 +index 0000000..21fad17 --- /dev/null +++ b/ld/testsuite/ld-auto-import/auto-import.exp -@@ -0,0 +1,177 @@ +@@ -0,0 +1,176 @@ +# Expect script for ld-auto-import tests -+# Copyright 2002, 2005, 2007, 2008, 2009 -+# Free Software Foundation, Inc. ++# Copyright (C) 2002-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2757650,105 +2772443,198 @@ index 0000000..f9a26e1 +} diff --git a/ld/testsuite/ld-auto-import/client.c b/ld/testsuite/ld-auto-import/client.c new file mode 100644 -index 0000000..c597079 +index 0000000..b883fdb --- /dev/null +++ b/ld/testsuite/ld-auto-import/client.c @@ -0,0 +1,60 @@ -+#include -+ -+extern int var; -+extern void (*func_ptr)(void); -+extern void print_var (void); -+extern void print_foo (void); -+extern int foo; -+extern int var2[2]; -+ -+typedef struct -+{ -+ int * var; -+ void (* func_ptr)(void); -+ int * var_with_offset; -+} -+TEST; -+ -+TEST xyz = { & var, print_var, & var }; -+ -+const TEST const_xyz = { & var, print_var, & var }; -+ -+int -+main (void) -+{ -+ print_var (); -+ -+ printf ("We see var = %d\n", var); -+ printf ("Setting var = 456\n"); -+ -+ var = 456; -+ -+ print_var (); -+ printf ("We see var = %d\n\n", var); -+ -+ var = 90; -+ print_var (); -+ printf ("We see var = %d\n\n", var); -+ -+ print_foo (); -+ printf ("We see foo = %d\n", foo); -+ printf ("Setting foo = 19\n"); -+ foo = 19; -+ print_foo (); -+ printf ("We see foo = %d\n\n", foo); -+ fflush (stdout); -+ -+ printf ("Calling dllimported function pointer\n"); -+ func_ptr (); -+ -+ printf ("Calling functions using global structure\n"); -+ xyz.func_ptr (); -+ * xyz.var = 40; -+ xyz.func_ptr (); -+ -+ printf ("We see var2[0] = %d\n\n", var2[0]); -+ -+ printf ("We see const xyz %x %x\n", const_xyz.var, const_xyz.var_with_offset); -+ -+ return 0; -+} ++#include ++ ++extern int var; ++extern void (*func_ptr)(void); ++extern void print_var (void); ++extern void print_foo (void); ++extern int foo; ++extern int var2[2]; ++ ++typedef struct ++{ ++ int * var; ++ void (* func_ptr)(void); ++ int * var_with_offset; ++} ++TEST; ++ ++TEST xyz = { & var, print_var, & var }; ++ ++const TEST const_xyz = { & var, print_var, & var }; ++ ++int ++main (void) ++{ ++ print_var (); ++ ++ printf ("We see var = %d\n", var); ++ printf ("Setting var = 456\n"); ++ ++ var = 456; ++ ++ print_var (); ++ printf ("We see var = %d\n\n", var); ++ ++ var = 90; ++ print_var (); ++ printf ("We see var = %d\n\n", var); ++ ++ print_foo (); ++ printf ("We see foo = %d\n", foo); ++ printf ("Setting foo = 19\n"); ++ foo = 19; ++ print_foo (); ++ printf ("We see foo = %d\n\n", foo); ++ fflush (stdout); ++ ++ printf ("Calling dllimported function pointer\n"); ++ func_ptr (); ++ ++ printf ("Calling functions using global structure\n"); ++ xyz.func_ptr (); ++ * xyz.var = 40; ++ xyz.func_ptr (); ++ ++ printf ("We see var2[0] = %d\n\n", var2[0]); ++ ++ printf ("We see const xyz %x %x\n", const_xyz.var, const_xyz.var_with_offset); ++ ++ return 0; ++} diff --git a/ld/testsuite/ld-auto-import/dll.c b/ld/testsuite/ld-auto-import/dll.c new file mode 100644 -index 0000000..5da2ac8 +index 0000000..ccf85e4 --- /dev/null +++ b/ld/testsuite/ld-auto-import/dll.c @@ -0,0 +1,20 @@ -+int var = 123; -+int foo = 121; ++int var = 123; ++int foo = 121; ++ ++int var2[2]= { 123, 456 }; ++ ++#include ++ ++void ++print_var (void) ++{ ++ printf ("DLL sees var = %d\n", var); ++} ++ ++void ++print_foo (void) ++{ ++ printf ("DLL sees foo = %d\n", foo); ++} ++ ++void (* func_ptr)(void) = print_foo; +diff --git a/ld/testsuite/ld-avr/avr.exp b/ld/testsuite/ld-avr/avr.exp +new file mode 100644 +index 0000000..d196d96 +--- /dev/null ++++ b/ld/testsuite/ld-avr/avr.exp +@@ -0,0 +1,31 @@ ++# Copyright 2014 ++# Free Software Foundation, Inc. + -+int var2[2]= { 123, 456 }; ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 3 of the License, or ++# (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. + -+#include ++# ++# Some AVR tests ++# + -+void -+print_var (void) -+{ -+ printf ("DLL sees var = %d\n", var); ++if {![istarget avr-*-*]} { ++ return +} + -+void -+print_foo (void) -+{ -+ printf ("DLL sees foo = %d\n", foo); ++set avr_test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]] ++foreach avr_test $avr_test_list { ++ verbose [file rootname $avr_test] ++ run_dump_test [file rootname $avr_test] +} + -+void (* func_ptr)(void) = print_foo; +diff --git a/ld/testsuite/ld-avr/norelax_diff.d b/ld/testsuite/ld-avr/norelax_diff.d +new file mode 100644 +index 0000000..1891d6e +--- /dev/null ++++ b/ld/testsuite/ld-avr/norelax_diff.d +@@ -0,0 +1,13 @@ ++#name: AVR No change in behavior without relaxation ++#as: -mmcu=avrxmega2 ++#ld: -mavrxmega2 ++#source: relax.s ++#objdump: -s ++#target: avr-*-* ++ ++.*: file format elf32-avr ++ ++Contents of section .text: ++ 0000 0c940000 .* ++Contents of section .data: ++ 802000 0400 .* +diff --git a/ld/testsuite/ld-avr/relax.s b/ld/testsuite/ld-avr/relax.s +new file mode 100644 +index 0000000..fbb7bae +--- /dev/null ++++ b/ld/testsuite/ld-avr/relax.s +@@ -0,0 +1,12 @@ ++ .file "relax.s" ++.section .text,"ax",@progbits ++main: ++L1: ++ jmp L1 ++L2: ++.global x ++ .section .data ++ .type x, @object ++ .size x, 2 ++x: ++ .word L2 - L1 +diff --git a/ld/testsuite/ld-avr/relax_diff.d b/ld/testsuite/ld-avr/relax_diff.d +new file mode 100644 +index 0000000..b84df81 +--- /dev/null ++++ b/ld/testsuite/ld-avr/relax_diff.d +@@ -0,0 +1,14 @@ ++#name: AVR Account for relaxation in label differences ++#as: -mmcu=avrxmega2 -mlink-relax ++#ld: -mavrxmega2 --relax ++#source: relax.s ++#objdump: -s ++#target: avr-*-* ++ ++.*: file format elf32-avr ++ ++Contents of section .text: ++ 0000 ffcf .* ++Contents of section .data: ++ 802000 0200 .* ++ diff --git a/ld/testsuite/ld-bootstrap/bootstrap.exp b/ld/testsuite/ld-bootstrap/bootstrap.exp new file mode 100644 -index 0000000..1893873 +index 0000000..bbd4fd8 --- /dev/null +++ b/ld/testsuite/ld-bootstrap/bootstrap.exp -@@ -0,0 +1,210 @@ +@@ -0,0 +1,219 @@ +# Expect script for LD Bootstrap Tests -+# Copyright 1993, 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2004, -+# 2005, 2006, 2007, 2009, 2010 Free Software Foundation, Inc. ++# Copyright (C) 1993-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2757797,9 +2772683,13 @@ index 0000000..1893873 +# order to test -r. Then link the result into an executable, ld1, to +# really test -r. Use ld1 to link a fresh ld, ld2. Use ld2 to link a +# new ld, ld3. ld2 and ld3 should be identical. ++set test_flags {"" "strip" "--static" "--traditional-format" ++ "--no-keep-memory" "--relax"} ++if { [istarget "powerpc-*-*"] } { ++ lappend test_flags "--ppc476-workaround" ++} + -+foreach flags {"" "strip" "--static" "--traditional-format" -+ "--no-keep-memory" "--relax"} { ++foreach flags $test_flags { + set do_strip "no" + if {"$flags" == "strip"} { + set testname "bootstrap with $flags" @@ -2757817,6 +2772707,10 @@ index 0000000..1893873 + set partial_flags "" + } + ++ if { $partial_flags == "--ppc476-workaround" } { ++ append partial_flags " -T $srcdir/$subdir/ppc476.t" ++ } ++ + # This test can only be run if we have the ld build directory, + # since we need the object files. + if {$ld != "$objdir/ld-new"} { @@ -2757863,7 +2772757,9 @@ index 0000000..1893873 + + # Plugin support requires linking with libdl. + if { $plugins == "yes" } { -+ set extralibs "$extralibs -ldl" ++ if { ![istarget "*-*-freebsd*"]} { ++ set extralibs "$extralibs -ldl" ++ } + } + + # On Irix 5, linking with --static only works if all the files are @@ -2757956,6 +2772852,19 @@ index 0000000..1893873 + +catch "exec rm -f tmpdir/ld-partial.o tmpdir/ld1 tmpdir/ld2 tmpdir/ld3" status +catch "exec rm -f tmpdir/ld2tail tmpdir/ld3tail" status +diff --git a/ld/testsuite/ld-bootstrap/ppc476.t b/ld/testsuite/ld-bootstrap/ppc476.t +new file mode 100644 +index 0000000..46ab8a7 +--- /dev/null ++++ b/ld/testsuite/ld-bootstrap/ppc476.t +@@ -0,0 +1,7 @@ ++SECTIONS ++{ ++ .text : ALIGN (4096) ++ { ++ *(.text .text.* .gnu.linkonce.t*) ++ } ++} diff --git a/ld/testsuite/ld-cdtest/cdtest-bar.cc b/ld/testsuite/ld-cdtest/cdtest-bar.cc new file mode 100644 index 0000000..79000e3 @@ -2758192,13 +2773101,12 @@ index 0000000..39be0db +Destructing Foo(1) "static_foo" (remaining foos: 0) diff --git a/ld/testsuite/ld-cdtest/cdtest.exp b/ld/testsuite/ld-cdtest/cdtest.exp new file mode 100644 -index 0000000..a25b437 +index 0000000..858c58b --- /dev/null +++ b/ld/testsuite/ld-cdtest/cdtest.exp -@@ -0,0 +1,127 @@ +@@ -0,0 +1,126 @@ +# Expect script for LD cdtest Tests -+# Copyright 1993, 1994, 1995, 1997, 2001, 2004, 2005, 2007 -+# Free Software Foundation, Inc. ++# Copyright (C) 1993-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2758342,12 +2773250,12 @@ index 0000000..86e7310 + .lcomm dummy, 0x12 diff --git a/ld/testsuite/ld-checks/checks.exp b/ld/testsuite/ld-checks/checks.exp new file mode 100644 -index 0000000..af281d0 +index 0000000..a3f3d25 --- /dev/null +++ b/ld/testsuite/ld-checks/checks.exp @@ -0,0 +1,81 @@ +# Expect script for LD section checks tests -+# Copyright 1999, 2001, 2003, 2005, 2007, 2009 Free Software Foundation, Inc. ++# Copyright (C) 1999-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2758503,12 +2773411,12 @@ index 0000000..5be25d8 + move.d c3:PLT,$r10 diff --git a/ld/testsuite/ld-cris/cris.exp b/ld/testsuite/ld-cris/cris.exp new file mode 100644 -index 0000000..ebe4bff +index 0000000..4b737c6 --- /dev/null +++ b/ld/testsuite/ld-cris/cris.exp @@ -0,0 +1,56 @@ +# Expect script for ld-cris tests -+# Copyright 2002, 2005, 2007, 2009 Free Software Foundation, Inc. ++# Copyright (C) 2002-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2766006,12 +2780914,12 @@ index 0000000..79de291 + diff --git a/ld/testsuite/ld-crx/crx.exp b/ld/testsuite/ld-crx/crx.exp new file mode 100644 -index 0000000..4136ebe +index 0000000..5b31a6b --- /dev/null +++ b/ld/testsuite/ld-crx/crx.exp @@ -0,0 +1,35 @@ +# Expect script for ld-crx tests -+# Copyright 2004, 2005, 2007 Free Software Foundation, Inc. ++# Copyright (C) 2004-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2766636,164 +2781544,163 @@ index 0000000..9692f3c +foo8: diff --git a/ld/testsuite/ld-cygwin/exe-export.exp b/ld/testsuite/ld-cygwin/exe-export.exp new file mode 100644 -index 0000000..7eb6765 +index 0000000..d81ec65 --- /dev/null +++ b/ld/testsuite/ld-cygwin/exe-export.exp -@@ -0,0 +1,154 @@ -+# Expect script for export table in executables tests -+# Copyright 2003, 2005, 2007, 2009 -+# Free Software Foundation, Inc. -+# -+# This file is part of the GNU Binutils. -+# -+# This program is free software; you can redistribute it and/or modify -+# it under the terms of the GNU General Public License as published by -+# the Free Software Foundation; either version 3 of the License, or -+# (at your option) any later version. -+# -+# This program is distributed in the hope that it will be useful, -+# but WITHOUT ANY WARRANTY; without even the implied warranty of -+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+# GNU General Public License for more details. -+# -+# You should have received a copy of the GNU General Public License -+# along with this program; if not, write to the Free Software -+# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, -+# MA 02110-1301, USA. -+# -+# Written by Fabrizio Gennari -+# Based on auto-import.exp by Ralf.Habacker@freenet.de -+# -+ -+# This test can only be run on a cygwin platforms. -+if {![istarget *-pc-cygwin]} { -+ verbose "Not a cygwin target." -+ return -+} -+ -+# No compiler, no test. -+if { [which $CC] == 0 } { -+ untested "Exe export test (no compiler available)" -+ return -+} -+ -+proc run_dlltool { lib_file def_file } { -+ global dlltool -+ global base_dir -+ global as -+ -+ if ![info exists dlltool] then { -+ set dlltool [findfile $base_dir/../binutils/dlltool] -+ } -+ -+ if { [which $dlltool] == 0 } then { -+ verbose "$dlltool does not exist" -+ return 0 -+ } -+ -+ verbose "$dlltool --as $as -l $lib_file -d $def_file" -+ catch "exec $dlltool --as $as -l $lib_file -d $def_file" dlltool_output -+ -+ #remove empty lines -+ regsub -all "\n+" $dlltool_output "" dlltool_output -+ -+ if [string match "" $dlltool_output] then { -+ return 1 -+ } -+ -+ verbose -log "$dlltool_output" -+ return 0 -+} -+ -+# ld_special_link -+# A copy of ld_simple_link (from ld-lib.exp) with extra -+# code to strip warnings about creating libraries. -+# -+proc ld_special_link { ld target objects } { -+ global host_triplet -+ global link_output -+ -+ if { [which $ld] == 0 } then { -+ verbose "$ld does not exist" -+ return 0 -+ } -+ -+ if [is_endian_output_format $objects] then { -+ set flags [big_or_little_endian] -+ } else { -+ set flags "" -+ } -+ -+ verbose -log "$ld $flags -o $target $objects" -+ catch "exec $ld $flags -o $target $objects" link_output -+ -+ set exec_output [prune_warnings $link_output] -+ -+ # We don't care if we get a warning about a non-existent start -+ # symbol, since the default linker script might use ENTRY. -+ regsub -all "(^|\n)(\[^\n\]*: warning: cannot find entry symbol\[^\n\]*\n?)" $exec_output "\\1" exec_output -+ -+ # We don't care if we get a message about creating a library file. -+ regsub -all "(^|\n)(Creating library file\[^\n\]*\n?)" $exec_output "\\1" exec_output -+ -+ if [string match "" $exec_output] then { -+ return 1 -+ } -+ -+ verbose -log "$exec_output" -+ return 0 -+} -+ -+set tmpdir tmpdir -+ -+# Set some libs needed for cygwin. -+set MYLDFLAGS "-Wl,--out-implib,$tmpdir/testexe.lib -nostartfiles -nostdlib" -+ -+# Build an export library for testdll -+if ![run_dlltool $tmpdir/testdll.lib $srcdir/$subdir/testdll.def] { -+ fail "building an export library for the shared lib" -+ return -+} -+ -+# Compile the executable. -+if ![ld_compile "$CC $CFLAGS" $srcdir/$subdir/testexe.c $tmpdir/testexe.o] { -+ fail "compiling executable" -+ return -+} -+ -+if ![ld_special_link "$CC $LDFLAGS $MYLDFLAGS -e _testexe_main@16" $tmpdir/testexe.exe "$tmpdir/testexe.o $srcdir/$subdir/testexe.def $tmpdir/testdll.lib -lkernel32"] { -+ fail "linking executable" -+ return -+} -+ -+# Compile the dll. -+if ![ld_compile "$CC $CFLAGS" $srcdir/$subdir/testdll.c $tmpdir/testdll.o] { -+ fail "compiling shared lib" -+ return -+} -+ -+if ![ld_special_link "$CC $LDFLAGS -nostartfiles -nostdlib -e _testdll_main@12" $tmpdir/testdll.dll "$tmpdir/testdll.o $srcdir/$subdir/testdll.def $tmpdir/testexe.lib"] { -+ fail "linking shared lib" -+ return -+} -+ -+# This is as far as we can go with a cross-compiler -+if ![isnative] then { -+ verbose "Not running natively, so cannot execute binary" -+ pass "Compile and link and executable with an export table" -+ return -+} -+ -+verbose -log "executing $tmpdir/testexe.exe" -+catch "exec $tmpdir/testexe.exe" prog_output -+ -+set expected "" -+if [string match $expected $prog_output] then { -+ pass "export table in executable" -+} else { -+ verbose $prog_output -+ fail "Output does not match expected string $expected" -+} +@@ -0,0 +1,153 @@ ++# Expect script for export table in executables tests ++# Copyright (C) 2003-2014 Free Software Foundation, Inc. ++# ++# This file is part of the GNU Binutils. ++# ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 3 of the License, or ++# (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ++# MA 02110-1301, USA. ++# ++# Written by Fabrizio Gennari ++# Based on auto-import.exp by Ralf.Habacker@freenet.de ++# ++ ++# This test can only be run on a cygwin platforms. ++if {![istarget *-pc-cygwin]} { ++ verbose "Not a cygwin target." ++ return ++} ++ ++# No compiler, no test. ++if { [which $CC] == 0 } { ++ untested "Exe export test (no compiler available)" ++ return ++} ++ ++proc run_dlltool { lib_file def_file } { ++ global dlltool ++ global base_dir ++ global as ++ ++ if ![info exists dlltool] then { ++ set dlltool [findfile $base_dir/../binutils/dlltool] ++ } ++ ++ if { [which $dlltool] == 0 } then { ++ verbose "$dlltool does not exist" ++ return 0 ++ } ++ ++ verbose "$dlltool --as $as -l $lib_file -d $def_file" ++ catch "exec $dlltool --as $as -l $lib_file -d $def_file" dlltool_output ++ ++ #remove empty lines ++ regsub -all "\n+" $dlltool_output "" dlltool_output ++ ++ if [string match "" $dlltool_output] then { ++ return 1 ++ } ++ ++ verbose -log "$dlltool_output" ++ return 0 ++} ++ ++# ld_special_link ++# A copy of ld_simple_link (from ld-lib.exp) with extra ++# code to strip warnings about creating libraries. ++# ++proc ld_special_link { ld target objects } { ++ global host_triplet ++ global link_output ++ ++ if { [which $ld] == 0 } then { ++ verbose "$ld does not exist" ++ return 0 ++ } ++ ++ if [is_endian_output_format $objects] then { ++ set flags [big_or_little_endian] ++ } else { ++ set flags "" ++ } ++ ++ verbose -log "$ld $flags -o $target $objects" ++ catch "exec $ld $flags -o $target $objects" link_output ++ ++ set exec_output [prune_warnings $link_output] ++ ++ # We don't care if we get a warning about a non-existent start ++ # symbol, since the default linker script might use ENTRY. ++ regsub -all "(^|\n)(\[^\n\]*: warning: cannot find entry symbol\[^\n\]*\n?)" $exec_output "\\1" exec_output ++ ++ # We don't care if we get a message about creating a library file. ++ regsub -all "(^|\n)(Creating library file\[^\n\]*\n?)" $exec_output "\\1" exec_output ++ ++ if [string match "" $exec_output] then { ++ return 1 ++ } ++ ++ verbose -log "$exec_output" ++ return 0 ++} ++ ++set tmpdir tmpdir ++ ++# Set some libs needed for cygwin. ++set MYLDFLAGS "-Wl,--out-implib,$tmpdir/testexe.lib -nostartfiles -nostdlib" ++ ++# Build an export library for testdll ++if ![run_dlltool $tmpdir/testdll.lib $srcdir/$subdir/testdll.def] { ++ fail "building an export library for the shared lib" ++ return ++} ++ ++# Compile the executable. ++if ![ld_compile "$CC $CFLAGS" $srcdir/$subdir/testexe.c $tmpdir/testexe.o] { ++ fail "compiling executable" ++ return ++} ++ ++if ![ld_special_link "$CC $LDFLAGS $MYLDFLAGS -e _testexe_main@16" $tmpdir/testexe.exe "$tmpdir/testexe.o $srcdir/$subdir/testexe.def $tmpdir/testdll.lib -lkernel32"] { ++ fail "linking executable" ++ return ++} ++ ++# Compile the dll. ++if ![ld_compile "$CC $CFLAGS" $srcdir/$subdir/testdll.c $tmpdir/testdll.o] { ++ fail "compiling shared lib" ++ return ++} ++ ++if ![ld_special_link "$CC $LDFLAGS -nostartfiles -nostdlib -e _testdll_main@12" $tmpdir/testdll.dll "$tmpdir/testdll.o $srcdir/$subdir/testdll.def $tmpdir/testexe.lib"] { ++ fail "linking shared lib" ++ return ++} ++ ++# This is as far as we can go with a cross-compiler ++if ![isnative] then { ++ verbose "Not running natively, so cannot execute binary" ++ pass "Compile and link and executable with an export table" ++ return ++} ++ ++verbose -log "executing $tmpdir/testexe.exe" ++catch "exec $tmpdir/testexe.exe" prog_output ++ ++set expected "" ++if [string match $expected $prog_output] then { ++ pass "export table in executable" ++} else { ++ verbose $prog_output ++ fail "Output does not match expected string $expected" ++} diff --git a/ld/testsuite/ld-cygwin/testdll.c b/ld/testsuite/ld-cygwin/testdll.c new file mode 100644 index 0000000..2064307 @@ -2766816,14 +2781723,14 @@ index 0000000..2064307 +} diff --git a/ld/testsuite/ld-cygwin/testdll.def b/ld/testsuite/ld-cygwin/testdll.def new file mode 100644 -index 0000000..e1f33ef +index 0000000..05e6c88 --- /dev/null +++ b/ld/testsuite/ld-cygwin/testdll.def @@ -0,0 +1,4 @@ -+LIBRARY testdll -+ -+EXPORTS -+dllwrite ++LIBRARY testdll ++ ++EXPORTS ++dllwrite diff --git a/ld/testsuite/ld-cygwin/testexe.c b/ld/testsuite/ld-cygwin/testexe.c new file mode 100644 index 0000000..50a980b @@ -2766863,23 +2781770,23 @@ index 0000000..50a980b + diff --git a/ld/testsuite/ld-cygwin/testexe.def b/ld/testsuite/ld-cygwin/testexe.def new file mode 100644 -index 0000000..8fc3d80 +index 0000000..7570578 --- /dev/null +++ b/ld/testsuite/ld-cygwin/testexe.def @@ -0,0 +1,5 @@ -+NAME testexe.exe -+ -+EXPORTS -+exewrite -+global_a DATA ++NAME testexe.exe ++ ++EXPORTS ++exewrite ++global_a DATA diff --git a/ld/testsuite/ld-d10v/d10v.exp b/ld/testsuite/ld-d10v/d10v.exp new file mode 100644 -index 0000000..3d65ce0 +index 0000000..395f4a0 --- /dev/null +++ b/ld/testsuite/ld-d10v/d10v.exp @@ -0,0 +1,253 @@ +# Expect script for ld-d10v tests -+# Copyright 2002, 2005, 2007 Free Software Foundation, Inc. ++# Copyright (C) 2002-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2767796,12 +2782703,12 @@ index 0000000..8a304f9 + diff --git a/ld/testsuite/ld-discard/discard.exp b/ld/testsuite/ld-discard/discard.exp new file mode 100644 -index 0000000..4fd4c43 +index 0000000..7fe2d00 --- /dev/null +++ b/ld/testsuite/ld-discard/discard.exp @@ -0,0 +1,48 @@ +# Expect script for ld discard tests -+# Copyright 2001, 2002, 2005, 2007, 2010, 2012 Free Software Foundation, Inc. ++# Copyright (C) 2001-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2767877,7 +2782784,7 @@ index 0000000..c852978 +text: diff --git a/ld/testsuite/ld-discard/extern.d b/ld/testsuite/ld-discard/extern.d new file mode 100644 -index 0000000..bb596d5 +index 0000000..089beca --- /dev/null +++ b/ld/testsuite/ld-discard/extern.d @@ -0,0 +1,13 @@ @@ -2767885,7 +2782792,7 @@ index 0000000..bb596d5 +#ld: -T discard.ld +#error: .*data.* referenced in section `\.text' of tmpdir/dump0.o: defined in discarded section `\.data\.exit' of tmpdir/dump0.o +#objdump: -p -+#xfail: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-* ++#xfail: arc-*-* d30v-*-* dlx-*-* i960-*-* pj*-*-* +#xfail: m68hc12-*-* m6812-*-* +#pass +# The expected warning used to start with "`data' referenced..." but @@ -2767915,7 +2782822,7 @@ index 0000000..464be8b + .long text diff --git a/ld/testsuite/ld-discard/start.d b/ld/testsuite/ld-discard/start.d new file mode 100644 -index 0000000..06207ee +index 0000000..50c5574 --- /dev/null +++ b/ld/testsuite/ld-discard/start.d @@ -0,0 +1,8 @@ @@ -2767924,7 +2782831,7 @@ index 0000000..06207ee +#ld: -T discard.ld +#error: `data' referenced in section `\.text' of tmpdir/dump0.o: defined in discarded section `\.data\.exit' of tmpdir/dump1.o +#objdump: -p -+#xfail: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-* ++#xfail: arc-*-* d30v-*-* dlx-*-* i960-*-* pj*-*-* +#xfail: m68hc12-*-* m6812-*-* +#pass diff --git a/ld/testsuite/ld-discard/start.s b/ld/testsuite/ld-discard/start.s @@ -2767942,7 +2782849,7 @@ index 0000000..70f4187 + .long text diff --git a/ld/testsuite/ld-discard/static.d b/ld/testsuite/ld-discard/static.d new file mode 100644 -index 0000000..b001d72 +index 0000000..7335ae5 --- /dev/null +++ b/ld/testsuite/ld-discard/static.d @@ -0,0 +1,7 @@ @@ -2767950,7 +2782857,7 @@ index 0000000..b001d72 +#ld: -T discard.ld +#error: `(\.data\.exit|data)' referenced in section `\.text' of tmpdir/dump0.o: defined in discarded section `\.data\.exit' of tmpdir/dump0.o +#objdump: -p -+#xfail: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-* ++#xfail: arc-*-* d30v-*-* dlx-*-* i960-*-* pj*-*-* +#xfail: m68hc12-*-* m6812-*-* +#pass diff --git a/ld/testsuite/ld-discard/static.s b/ld/testsuite/ld-discard/static.s @@ -2768036,12 +2782943,12 @@ index 0000000..f3f0b3c + .long 0 diff --git a/ld/testsuite/ld-elf/audit.exp b/ld/testsuite/ld-elf/audit.exp new file mode 100644 -index 0000000..407c61a +index 0000000..3b05868 --- /dev/null +++ b/ld/testsuite/ld-elf/audit.exp @@ -0,0 +1,65 @@ +# Expect script for various ELF tests. -+# Copyright 2009 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2768142,12 +2783049,12 @@ index 0000000..ebe2819 + = { foo }; diff --git a/ld/testsuite/ld-elf/binutils.exp b/ld/testsuite/ld-elf/binutils.exp new file mode 100644 -index 0000000..0101512 +index 0000000..4ade8cb --- /dev/null +++ b/ld/testsuite/ld-elf/binutils.exp -@@ -0,0 +1,154 @@ +@@ -0,0 +1,178 @@ +# Expect script for binutils tests -+# Copyright 2006, 2007, 2008, 2009, 2010, 2012 Free Software Foundation, Inc. ++# Copyright (C) 2006-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2768227,6 +2783134,30 @@ index 0000000..0101512 + return + } + ++ if [string match "*-z relro*" $ld_options] { ++ # Check if GNU_RELRO segment is generated. ++ set got [remote_exec host "grep GNU_RELRO tmpdir/$test.exp"] ++ if { ![string match "*GNU_RELRO*" $got] } then { ++ set got [remote_exec host "cat tmpdir/$test.exp"] ++ if { [string match "*.data.rel.ro*" $got] ++ || [string match "*.dynamic*" $got] ++ || [string match "*.got*" $got] ++ || [string match "*.eh_frame*" $got] ++ || [string match "*.gcc_except_table*" $got] ++ || [string match "*.exception_ranges*" $got] ++ || [string match "*.ctors*" $got] ++ || [string match "*.dtors*" $got] ++ || [string match "*.tdata*" $got] ++ || [string match "*.preinit_array*" $got] ++ || [string match "*.init_array*" $got] ++ || [string match "*.fini_array*" $got] } then { ++ # Fail if GNU_RELRO segment isn't generated, but should. ++ fail "$test_name" ++ return ++ } ++ } ++ } ++ + send_log "$prog tmpdir/$test\n" + set got [remote_exec host "$prog tmpdir/$test"] + if { [lindex $got 0] != 0 || ![string match "" [lindex $got 1]] } then { @@ -2768302,13 +2783233,13 @@ index 0000000..0101512 +} diff --git a/ld/testsuite/ld-elf/comm-data.exp b/ld/testsuite/ld-elf/comm-data.exp new file mode 100644 -index 0000000..71613c5 +index 0000000..2706bce --- /dev/null +++ b/ld/testsuite/ld-elf/comm-data.exp @@ -0,0 +1,117 @@ +# Expect script for common symbol override. +# -+# Copyright 2011, 2012 Free Software Foundation, Inc. ++# Copyright (C) 2011-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2768725,12 +2783656,12 @@ index 0000000..e4d582b +#pass diff --git a/ld/testsuite/ld-elf/compress.exp b/ld/testsuite/ld-elf/compress.exp new file mode 100644 -index 0000000..55269ee +index 0000000..6bfc040 --- /dev/null +++ b/ld/testsuite/ld-elf/compress.exp @@ -0,0 +1,63 @@ +# Expect script for ELF compressed debug section tests. -+# Copyright 2010 Free Software Foundation, Inc. ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2768794,13 +2783725,13 @@ index 0000000..55269ee +run_ld_link_exec_tests [] $run_tests diff --git a/ld/testsuite/ld-elf/compress1.s b/ld/testsuite/ld-elf/compress1.s new file mode 100644 -index 0000000..8ef0a15 +index 0000000..f75c7be --- /dev/null +++ b/ld/testsuite/ld-elf/compress1.s @@ -0,0 +1,216 @@ +/* This testcase is derived from a similar test in GDB. + -+ Copyright 2008, 2009, 2010 Free Software Foundation, Inc. ++ Copyright (C) 2008-2014 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by @@ -2769916,12 +2784847,12 @@ index 0000000..5c03287 +/* An empty file. */ diff --git a/ld/testsuite/ld-elf/dwarf.exp b/ld/testsuite/ld-elf/dwarf.exp new file mode 100644 -index 0000000..c313236 +index 0000000..4ec26f1 --- /dev/null +++ b/ld/testsuite/ld-elf/dwarf.exp @@ -0,0 +1,114 @@ +# Expect script for various DWARF tests. -+# Copyright 2006, 2007 Free Software Foundation, Inc. ++# Copyright (C) 2006-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2770085,6 +2785016,42 @@ index 0000000..9045198 + doprintf (); + return 0; +} +diff --git a/ld/testsuite/ld-elf/dynamic-1.c b/ld/testsuite/ld-elf/dynamic-1.c +new file mode 100644 +index 0000000..439ffd1 +--- /dev/null ++++ b/ld/testsuite/ld-elf/dynamic-1.c +@@ -0,0 +1,10 @@ ++void ++dynamic () ++{ ++} ++ ++int ++main () ++{ ++ return 0; ++} +diff --git a/ld/testsuite/ld-elf/dynamic-1.rd b/ld/testsuite/ld-elf/dynamic-1.rd +new file mode 100644 +index 0000000..2c2f23b +--- /dev/null ++++ b/ld/testsuite/ld-elf/dynamic-1.rd +@@ -0,0 +1,5 @@ ++Symbol table '\.dynsym' contains [0-9]+ entries: ++ +Num: +Value +Size Type +Bind +Vis +Ndx Name ++#... ++ +[0-9]+: +[0-9a-f]+ +[0-9a-f]+ +FUNC +GLOBAL +DEFAULT +[0-9]+ +_?dynamic ++#... +diff --git a/ld/testsuite/ld-elf/dynamic-1.syms b/ld/testsuite/ld-elf/dynamic-1.syms +new file mode 100644 +index 0000000..c9517f8 +--- /dev/null ++++ b/ld/testsuite/ld-elf/dynamic-1.syms +@@ -0,0 +1,3 @@ ++{ ++ dynamic; ++}; diff --git a/ld/testsuite/ld-elf/dynamic1.d b/ld/testsuite/ld-elf/dynamic1.d new file mode 100644 index 0000000..6a8ba55 @@ -2770165,7 +2785132,7 @@ index 0000000..b354aae +#pass diff --git a/ld/testsuite/ld-elf/eh-frame-hdr.d b/ld/testsuite/ld-elf/eh-frame-hdr.d new file mode 100644 -index 0000000..1122cba +index 0000000..45a890d --- /dev/null +++ b/ld/testsuite/ld-elf/eh-frame-hdr.d @@ -0,0 +1,9 @@ @@ -2770173,7 +2785140,7 @@ index 0000000..1122cba +#ld: -e _start --eh-frame-hdr +#objdump: -hw +#target: cfi -+#xfail: avr*-*-* ++#xfail: avr*-*-* or1k-*-* +# avr doesn't support shared libraries. +#... + [0-9] .eh_frame_hdr 0*[12][048c] .* @@ -2770192,12 +2785159,12 @@ index 0000000..e5d3318 + .cfi_endproc diff --git a/ld/testsuite/ld-elf/eh-group.exp b/ld/testsuite/ld-elf/eh-group.exp new file mode 100644 -index 0000000..6fe7058 +index 0000000..e0b8f00 --- /dev/null +++ b/ld/testsuite/ld-elf/eh-group.exp @@ -0,0 +1,72 @@ +# Expect script for .eh_frame entries to a removed section. -+# Copyright 2008, 2009 Free Software Foundation, Inc. ++# Copyright (C) 2008-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2771056,6 +2786023,21 @@ index 0000000..a4daf06 + . = 0x20000000; + .rodata : { *(.rodata) } +} +diff --git a/ld/testsuite/ld-elf/ehdr_start-shared.d b/ld/testsuite/ld-elf/ehdr_start-shared.d +new file mode 100644 +index 0000000..c17516a +--- /dev/null ++++ b/ld/testsuite/ld-elf/ehdr_start-shared.d +@@ -0,0 +1,9 @@ ++#source: ehdr_start.s ++#ld: -e _start -shared ++#nm: -n ++#target: *-*-linux* *-*-gnu* *-*-nacl* ++#xfail: cris*-*-* frv-*-* ++ ++#... ++[0-9a-f]*000 [Adrt] __ehdr_start ++#pass diff --git a/ld/testsuite/ld-elf/ehdr_start-strongref.s b/ld/testsuite/ld-elf/ehdr_start-strongref.s new file mode 100644 index 0000000..3937507 @@ -2771073,14 +2786055,15 @@ index 0000000..3937507 + .dc.a __ehdr_start diff --git a/ld/testsuite/ld-elf/ehdr_start-userdef.d b/ld/testsuite/ld-elf/ehdr_start-userdef.d new file mode 100644 -index 0000000..2a88e98 +index 0000000..b58ae3f --- /dev/null +++ b/ld/testsuite/ld-elf/ehdr_start-userdef.d -@@ -0,0 +1,10 @@ +@@ -0,0 +1,11 @@ +#source: ehdr_start-strongref.s +#ld: -e _start -T ehdr_start-userdef.t +#readelf: -Ws +#target: *-*-linux* *-*-gnu* *-*-nacl* ++#xfail: frv-*-* + +#... +Symbol table '\.symtab' contains [0-9]+ entries: @@ -2771105,28 +2786088,30 @@ index 0000000..6ef1de7 +} diff --git a/ld/testsuite/ld-elf/ehdr_start-weak.d b/ld/testsuite/ld-elf/ehdr_start-weak.d new file mode 100644 -index 0000000..8bd9035 +index 0000000..24ae34c --- /dev/null +++ b/ld/testsuite/ld-elf/ehdr_start-weak.d -@@ -0,0 +1,8 @@ +@@ -0,0 +1,9 @@ +#source: ehdr_start.s +#ld: -e _start -T ehdr_start-missing.t +#nm: -n +#target: *-*-linux* *-*-gnu* *-*-nacl* ++#xfail: frv-*-* + +#... +\s+[wU] __ehdr_start +#pass diff --git a/ld/testsuite/ld-elf/ehdr_start.d b/ld/testsuite/ld-elf/ehdr_start.d new file mode 100644 -index 0000000..52e5b54 +index 0000000..d538b66 --- /dev/null +++ b/ld/testsuite/ld-elf/ehdr_start.d -@@ -0,0 +1,8 @@ +@@ -0,0 +1,9 @@ +#source: ehdr_start.s +#ld: -e _start +#nm: -n +#target: *-*-linux* *-*-gnu* *-*-nacl* ++#xfail: frv-*-* + +#... +[0-9a-f]*000 [Adrt] __ehdr_start @@ -2771149,13 +2786134,12 @@ index 0000000..2efe8a6 + .dc.a __ehdr_start diff --git a/ld/testsuite/ld-elf/elf.exp b/ld/testsuite/ld-elf/elf.exp new file mode 100644 -index 0000000..236e15b +index 0000000..4c8ca3a --- /dev/null +++ b/ld/testsuite/ld-elf/elf.exp -@@ -0,0 +1,193 @@ +@@ -0,0 +1,192 @@ +# Expect script for various ELF tests. -+# Copyright 2002, 2003, 2005, 2007, 2009, 2010, 2011, 2012 -+# Free Software Foundation, Inc. ++# Copyright (C) 2002-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2771465,12 +2786449,12 @@ index 0000000..b6b39ea +} diff --git a/ld/testsuite/ld-elf/exclude.exp b/ld/testsuite/ld-elf/exclude.exp new file mode 100644 -index 0000000..28a34ab +index 0000000..db5b767 --- /dev/null +++ b/ld/testsuite/ld-elf/exclude.exp @@ -0,0 +1,148 @@ +# Expect script for --exclude-libs tests -+# Copyright 2004, 2005, 2007 Free Software Foundation, Inc. ++# Copyright (C) 2004-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2771801,13 +2786785,13 @@ index 0000000..4e45c02 + .dc.a internal_baz diff --git a/ld/testsuite/ld-elf/export-class.exp b/ld/testsuite/ld-elf/export-class.exp new file mode 100644 -index 0000000..38c635c +index 0000000..cc43ef0 --- /dev/null +++ b/ld/testsuite/ld-elf/export-class.exp @@ -0,0 +1,87 @@ +# Expect script for symbol export classes. +# -+# Copyright 2012 Free Software Foundation, Inc. ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2772332,12 +2787316,12 @@ index 0000000..9aa3b85 + .size last,.-last diff --git a/ld/testsuite/ld-elf/frame.exp b/ld/testsuite/ld-elf/frame.exp new file mode 100644 -index 0000000..b9307d4 +index 0000000..0f34d72 --- /dev/null +++ b/ld/testsuite/ld-elf/frame.exp @@ -0,0 +1,90 @@ +# Expect script for frame section tests -+# Copyright 2004, 2005, 2007 Free Software Foundation, Inc. ++# Copyright (C) 2004-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2772470,7 +2787454,7 @@ index 0000000..123ab26 +} diff --git a/ld/testsuite/ld-elf/group1.d b/ld/testsuite/ld-elf/group1.d new file mode 100644 -index 0000000..6ee74cb +index 0000000..ff67535 --- /dev/null +++ b/ld/testsuite/ld-elf/group1.d @@ -0,0 +1,12 @@ @@ -2772478,7 +2787462,7 @@ index 0000000..6ee74cb +#source: group1b.s +#ld: -T group.ld +#readelf: -s -+#xfail: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-* ++#xfail: arc-*-* d30v-*-* dlx-*-* i960-*-* pj*-*-* +# generic linker targets don't comply with all symbol merging rules + +Symbol table '.symtab' contains .* entries: @@ -2772598,7 +2787582,7 @@ index 0000000..5e6a686 + .word 0 diff --git a/ld/testsuite/ld-elf/group3b.d b/ld/testsuite/ld-elf/group3b.d new file mode 100644 -index 0000000..1b8a2a2 +index 0000000..5182f3d --- /dev/null +++ b/ld/testsuite/ld-elf/group3b.d @@ -0,0 +1,11 @@ @@ -2772606,7 +2787590,7 @@ index 0000000..1b8a2a2 +#source: group3a.s +#ld: -T group.ld +#readelf: -s -+#xfail: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-* ++#xfail: arc-*-* d30v-*-* dlx-*-* i960-*-* pj*-*-* +# generic linker targets don't comply with all symbol merging rules + +Symbol table '.symtab' contains .* entries: @@ -2772758,14 +2787742,14 @@ index 0000000..7766c6c + .byte 0 diff --git a/ld/testsuite/ld-elf/group8a.d b/ld/testsuite/ld-elf/group8a.d new file mode 100644 -index 0000000..bad4123 +index 0000000..f645256 --- /dev/null +++ b/ld/testsuite/ld-elf/group8a.d @@ -0,0 +1,13 @@ +#source: group8.s +#ld: -r --gc-sections --entry foo +#readelf: -g --wide -+#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-* ++#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* pj*-*-* +#notarget: hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-* +#xfail: cr16-*-* crx-*-* +# generic linker targets don't support --gc-sections, nor do a bunch of others @@ -2772777,14 +2787761,14 @@ index 0000000..bad4123 + \[[ 0-9]+\] .text.foo diff --git a/ld/testsuite/ld-elf/group8b.d b/ld/testsuite/ld-elf/group8b.d new file mode 100644 -index 0000000..fb37198 +index 0000000..2ce6b1a --- /dev/null +++ b/ld/testsuite/ld-elf/group8b.d @@ -0,0 +1,13 @@ +#source: group8.s +#ld: -r --gc-sections --entry bar +#readelf: -g --wide -+#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-* ++#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* pj*-*-* +#notarget: hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-* +#xfail: cr16-*-* crx-*-* +# generic linker targets don't support --gc-sections, nor do a bunch of others @@ -2772817,14 +2787801,14 @@ index 0000000..933c9f9 + .long foo.data diff --git a/ld/testsuite/ld-elf/group9a.d b/ld/testsuite/ld-elf/group9a.d new file mode 100644 -index 0000000..fd04c48 +index 0000000..62215a5 --- /dev/null +++ b/ld/testsuite/ld-elf/group9a.d @@ -0,0 +1,14 @@ +#source: group9.s +#ld: -r --gc-sections --entry foo +#readelf: -g --wide -+#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-* ++#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* pj*-*-* +#notarget: alpha-*-* hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-* +#xfail: cr16-*-* crx-*-* +# generic linker targets don't support --gc-sections, nor do a bunch of others @@ -2772837,14 +2787821,14 @@ index 0000000..fd04c48 + \[[ 0-9]+\] .data.foo diff --git a/ld/testsuite/ld-elf/group9b.d b/ld/testsuite/ld-elf/group9b.d new file mode 100644 -index 0000000..3f19fd6 +index 0000000..c4600d8 --- /dev/null +++ b/ld/testsuite/ld-elf/group9b.d @@ -0,0 +1,18 @@ +#source: group9.s +#ld: -r --gc-sections --entry bar +#readelf: -g --wide -+#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-* ++#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* pj*-*-* +#notarget: alpha-*-* hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-* +#xfail: cr16-*-* crx-*-* +# generic linker targets don't support --gc-sections, nor do a bunch of others @@ -2772932,12 +2787916,12 @@ index 0000000..7ad7cbe +MAIN diff --git a/ld/testsuite/ld-elf/indirect.exp b/ld/testsuite/ld-elf/indirect.exp new file mode 100644 -index 0000000..d5d3abc +index 0000000..15ab929 --- /dev/null +++ b/ld/testsuite/ld-elf/indirect.exp @@ -0,0 +1,137 @@ +# Expect script for various indirect symbol tests. -+# Copyright 2012 Free Software Foundation, Inc. ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -2773641,7 +2788625,7 @@ index 0000000..fd45cec + .long foo diff --git a/ld/testsuite/ld-elf/linkonce2.d b/ld/testsuite/ld-elf/linkonce2.d new file mode 100644 -index 0000000..0cbb3ad +index 0000000..edc135f --- /dev/null +++ b/ld/testsuite/ld-elf/linkonce2.d @@ -0,0 +1,14 @@ @@ -2773649,7 +2788633,7 @@ index 0000000..0cbb3ad +#source: linkonce1b.s +#ld: -emit-relocs +#objdump: -r -+#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-* ++#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* pj*-*-* +# generic elf targets don't emit relocs + +.*: file format .* @@ -2774146,7 +2789130,7 @@ index 0000000..7f19343 +} diff --git a/ld/testsuite/ld-elf/merge.d b/ld/testsuite/ld-elf/merge.d new file mode 100644 -index 0000000..c50de10 +index 0000000..450ee07 --- /dev/null +++ b/ld/testsuite/ld-elf/merge.d @@ -0,0 +1,17 @@ @@ -2774156,7 +2789140,7 @@ index 0000000..c50de10 +#xfail: "arc-*-*" "avr-*-*" "bfin-*-*" "cr16-*-*" "cris*-*-*" "crx-*-*" "d10v-*-*" "d30v-*-*" +#xfail: "dlx-*-*" "fr30-*-*" "frv-*-*" "hppa*64*-*-*" "h8300-*-*" "score-*-*" +#xfail: "i370-*-*" "i860-*-*" "i960-*-*" "ip2k-*-*" "iq2000-*-*" "lm32-*-*" -+#xfail: "mcore-*-*" "mn102*-*-*" "mips*-*-*" "ms1-*-*" "mep-*-*" ++#xfail: "mcore-*-*" "mn102*-*-*" "ms1-*-*" "mep-*-*" +#xfail: "or32-*-*" "pj-*-*" "sparc*-*-*" "tic6x-*-*" "vax-*-*" "xstormy16-*-*" +#xfail: "xtensa*-*-*" "metag-*-*" + @@ -2774202,7 +2789186,7 @@ index 0000000..1e6e0e3 + .long .LC1-.LT0 diff --git a/ld/testsuite/ld-elf/merge2.d b/ld/testsuite/ld-elf/merge2.d new file mode 100644 -index 0000000..4770621 +index 0000000..f7a18d6 --- /dev/null +++ b/ld/testsuite/ld-elf/merge2.d @@ -0,0 +1,17 @@ @@ -2774210,7 +2789194,7 @@ index 0000000..4770621 +#ld: -T merge.ld +#objdump: -s +#xfail: "arc-*-*" "d30v-*-*" "dlx-*-*" "hppa64-*-*" -+#xfail: "i960-*-*" "ip2k-*-*" "or32-*-*" "pj-*-*" ++#xfail: "i960-*-*" "ip2k-*-*" "pj-*-*" + +.*: file format .*elf.* + @@ -2774823,7 +2789807,7 @@ index 0000000..8d9d02f +#pass diff --git a/ld/testsuite/ld-elf/orphan-region.d b/ld/testsuite/ld-elf/orphan-region.d new file mode 100644 -index 0000000..bf65356 +index 0000000..481d822 --- /dev/null +++ b/ld/testsuite/ld-elf/orphan-region.d @@ -0,0 +1,21 @@ @@ -2774831,7 +2789815,7 @@ index 0000000..bf65356 +#ld: -T orphan-region.ld -N -z stack-size=0 +#readelf: -S -l --wide +#xfail: arc-*-* d30v-*-* dlx-*-* fr30-*-* frv-*-elf i860-*-* i960-*-* -+#xfail: iq*-*-* mn10200-*-* moxie-*-* msp*-*-* mt-*-* or32-*-* pj*-*-* ++#xfail: iq*-*-* mn10200-*-* moxie-*-* msp*-*-* mt-*-* pj*-*-* +#xfail: spu-*-* hppa*64*-*-* *-*-nacl* +# if not using elf32.em, you don't get fancy orphan handling +# spu twiddles LOAD range, hppa64 adds PHDR, nacl splits to two segments @@ -2774881,7 +2789865,7 @@ index 0000000..0268686 + .long 0 diff --git a/ld/testsuite/ld-elf/orphan.d b/ld/testsuite/ld-elf/orphan.d new file mode 100644 -index 0000000..7955c8b +index 0000000..630e596 --- /dev/null +++ b/ld/testsuite/ld-elf/orphan.d @@ -0,0 +1,16 @@ @@ -2774889,7 +2789873,7 @@ index 0000000..7955c8b +#ld: -T orphan.ld +#readelf: -S --wide +#xfail: arc-*-* d30v-*-* dlx-*-* fr30-*-* frv-*-elf i860-*-* i960-*-* -+#xfail: iq*-*-* mn10200-*-* moxie-*-* msp*-*-* mt-*-* or32-*-* pj*-*-* ++#xfail: iq*-*-* mn10200-*-* moxie-*-* msp*-*-* mt-*-* pj*-*-* +# if not using elf32.em, you don't get fancy orphan handling + +#... @@ -2774960,7 +2789944,7 @@ index 0000000..bed8dcd + .long 0 diff --git a/ld/testsuite/ld-elf/orphan3.d b/ld/testsuite/ld-elf/orphan3.d new file mode 100644 -index 0000000..ea600d3 +index 0000000..dbaaa43 --- /dev/null +++ b/ld/testsuite/ld-elf/orphan3.d @@ -0,0 +1,21 @@ @@ -2774974,7 +2789958,7 @@ index 0000000..ea600d3 +#readelf: -S --wide +#xfail: "arc-*-*" "d30v-*-*" "dlx-*-*" "fr30-*-*" "frv-*-elf" +#xfail: "i860-*-*" "i960-*-*" "iq2000-*-*" "mn10200-*-*" "msp430-*-*" "mt-*-*" -+#xfail: "or32-*-*" "pj-*-*" ++#xfail: "pj-*-*" +#xfail: "xstormy16-*-*" + +#... @@ -2775247,7 +2790231,7 @@ index 0000000..75fcd37 + .long 0 diff --git a/ld/testsuite/ld-elf/pr12851.d b/ld/testsuite/ld-elf/pr12851.d new file mode 100644 -index 0000000..fb61c5a +index 0000000..8aa48e9 --- /dev/null +++ b/ld/testsuite/ld-elf/pr12851.d @@ -0,0 +1,11 @@ @@ -2775255,7 +2790239,7 @@ index 0000000..fb61c5a +#source: start.s +#ld: --gc-sections +#readelf: -s --wide -+#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-* ++#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* pj*-*-* +#notarget: hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-* +# generic linker targets don't support --gc-sections, nor do a bunch of others + @@ -2775275,14 +2790259,14 @@ index 0000000..784b91f + .size _.stapsdt.base,1 diff --git a/ld/testsuite/ld-elf/pr12975.d b/ld/testsuite/ld-elf/pr12975.d new file mode 100644 -index 0000000..b361cc2 +index 0000000..11ace1f --- /dev/null +++ b/ld/testsuite/ld-elf/pr12975.d @@ -0,0 +1,11 @@ +#ld: --gc-sections -shared -version-script pr12975.t +#readelf: -s --wide +#target: *-*-linux* *-*-gnu* -+#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-* ++#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* pj*-*-* +#notarget: hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-* +# generic linker targets don't support --gc-sections, nor do a bunch of others + @@ -2775320,7 +2790304,7 @@ index 0000000..902c1f7 +}; diff --git a/ld/testsuite/ld-elf/pr13177.d b/ld/testsuite/ld-elf/pr13177.d new file mode 100644 -index 0000000..e56e865 +index 0000000..a009988 --- /dev/null +++ b/ld/testsuite/ld-elf/pr13177.d @@ -0,0 +1,12 @@ @@ -2775328,7 +2790312,7 @@ index 0000000..e56e865 +#ld: --gc-sections -shared +#readelf: -s -D --wide +#target: *-*-linux* *-*-gnu* -+#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-* ++#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* pj*-*-* +#notarget: hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-* +# generic linker targets don't support --gc-sections, nor do a bunch of others + @@ -2775364,14 +2790348,14 @@ index 0000000..a9bce4a +} diff --git a/ld/testsuite/ld-elf/pr13195.d b/ld/testsuite/ld-elf/pr13195.d new file mode 100644 -index 0000000..796102b +index 0000000..6b39f2d --- /dev/null +++ b/ld/testsuite/ld-elf/pr13195.d @@ -0,0 +1,10 @@ +#ld: --gc-sections -shared -version-script pr13195.t +#readelf: -s --wide -D +#target: *-*-linux* *-*-gnu* -+#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-* ++#notarget: arc-*-* d30v-*-* dlx-*-* i960-*-* pj*-*-* +#notarget: hppa64-*-* i370-*-* i860-*-* ia64-*-* mep-*-* mn10200-*-* +# generic linker targets don't support --gc-sections, nor do a bunch of others + @@ -2775789,6 +2790773,168 @@ index 0000000..3d132f6 +_start: +__start: + .byte 0 +diff --git a/ld/testsuite/ld-elf/pr16322.d b/ld/testsuite/ld-elf/pr16322.d +new file mode 100644 +index 0000000..40a7975 +--- /dev/null ++++ b/ld/testsuite/ld-elf/pr16322.d +@@ -0,0 +1,7 @@ ++#ld: -shared -z relro ++#readelf: -l --wide ++#target: *-*-linux-gnu *-*-gnu* *-*-nacl* ++ ++#... ++ GNU_RELRO .* ++#pass +diff --git a/ld/testsuite/ld-elf/pr16322.s b/ld/testsuite/ld-elf/pr16322.s +new file mode 100644 +index 0000000..c95817a +--- /dev/null ++++ b/ld/testsuite/ld-elf/pr16322.s +@@ -0,0 +1,6 @@ ++ .globl p1 ++ .section .data.rel.ro,"aw",%progbits ++ .p2align 5 ++ .type p1, %object ++p1: ++ .dc.a f1 +diff --git a/ld/testsuite/ld-elf/pr16498a.d b/ld/testsuite/ld-elf/pr16498a.d +new file mode 100644 +index 0000000..436bf97 +--- /dev/null ++++ b/ld/testsuite/ld-elf/pr16498a.d +@@ -0,0 +1,9 @@ ++#ld: -shared -T pr16498a.t ++#readelf: -l --wide ++#target: *-*-linux* *-*-gnu* *-*-nacl* ++ ++#... ++ TLS .* ++#... ++[ ]+[0-9]+[ ]+.tdata .tbss[ ]* ++#pass +diff --git a/ld/testsuite/ld-elf/pr16498a.s b/ld/testsuite/ld-elf/pr16498a.s +new file mode 100644 +index 0000000..be503a2 +--- /dev/null ++++ b/ld/testsuite/ld-elf/pr16498a.s +@@ -0,0 +1,23 @@ ++ .globl data ++ .data ++ .p2align 5 ++ .type data, %object ++ .size data, 120 ++data: ++ .long 1 ++ .zero 116 ++ .globl foo ++ .section .tbss,"awT",%nobits ++ .p2align 2 ++ .type foo, %object ++ .size foo, 4 ++foo: ++ .zero 4 ++ .globl bar ++ .section .tdata,"awT",%progbits ++ .p2align 4 ++ .type bar, %object ++ .size bar, 80 ++bar: ++ .long 1 ++ .zero 76 +diff --git a/ld/testsuite/ld-elf/pr16498a.t b/ld/testsuite/ld-elf/pr16498a.t +new file mode 100644 +index 0000000..928724f +--- /dev/null ++++ b/ld/testsuite/ld-elf/pr16498a.t +@@ -0,0 +1,6 @@ ++SECTIONS ++{ ++ .tdata : { *(.tdata) } ++ .data : { *(.data) ++ } ++} +diff --git a/ld/testsuite/ld-elf/pr16498b.d b/ld/testsuite/ld-elf/pr16498b.d +new file mode 100644 +index 0000000..c70c239 +--- /dev/null ++++ b/ld/testsuite/ld-elf/pr16498b.d +@@ -0,0 +1,10 @@ ++#source: pr16498a.s ++#ld: -shared -T pr16498b.t ++#readelf: -l --wide ++#target: *-*-linux* *-*-gnu* *-*-nacl* ++ ++#... ++ TLS .* ++#... ++[ ]+[0-9]+[ ]+tls_data_init .tbss[ ]* ++#pass +diff --git a/ld/testsuite/ld-elf/pr16498b.t b/ld/testsuite/ld-elf/pr16498b.t +new file mode 100644 +index 0000000..b88f9b8 +--- /dev/null ++++ b/ld/testsuite/ld-elf/pr16498b.t +@@ -0,0 +1,6 @@ ++SECTIONS ++{ ++ tls_data_init : { *(.tdata) } ++ .data : { *(.data) ++ } ++} +diff --git a/ld/testsuite/ld-elf/pr2404.out b/ld/testsuite/ld-elf/pr2404.out +new file mode 100644 +index 0000000..d1aa5fe +--- /dev/null ++++ b/ld/testsuite/ld-elf/pr2404.out +@@ -0,0 +1,4 @@ ++times: -1 ++times: 20 ++time: 0 ++time: 10 +diff --git a/ld/testsuite/ld-elf/pr2404a.c b/ld/testsuite/ld-elf/pr2404a.c +new file mode 100644 +index 0000000..4b2b5a9 +--- /dev/null ++++ b/ld/testsuite/ld-elf/pr2404a.c +@@ -0,0 +1,10 @@ ++#include ++#include ++ ++int ++bar (void) ++{ ++ struct tms buf; ++ clock_t ticks = times (&buf); ++ return ticks == 0 && time (NULL) == 0; ++} +diff --git a/ld/testsuite/ld-elf/pr2404b.c b/ld/testsuite/ld-elf/pr2404b.c +new file mode 100644 +index 0000000..5f0f7b4 +--- /dev/null ++++ b/ld/testsuite/ld-elf/pr2404b.c +@@ -0,0 +1,21 @@ ++#include ++ ++extern int bar (void); ++ ++int times = -1; ++int time; ++ ++int ++main () ++{ ++ printf ("times: %d\n", times); ++ times = 20; ++ printf ("times: %d\n", times); ++ ++ printf ("time: %d\n", time); ++ time = 10; ++ printf ("time: %d\n", time); ++ bar (); ++ ++ return 0; ++} diff --git a/ld/testsuite/ld-elf/pr349-1.s b/ld/testsuite/ld-elf/pr349-1.s new file mode 100644 index 0000000..a205905 @@ -2775807,7 +2790953,7 @@ index 0000000..85f36ca + .long 2 diff --git a/ld/testsuite/ld-elf/pr349.d b/ld/testsuite/ld-elf/pr349.d new file mode 100644 -index 0000000..48e3256 +index 0000000..f2a577f --- /dev/null +++ b/ld/testsuite/ld-elf/pr349.d @@ -0,0 +1,13 @@ @@ -2775816,7 +2790962,7 @@ index 0000000..48e3256 +#ld: -r +#readelf: -S +#xfail: arc-*-* d30v-*-* dlx-*-* fr30-*-* frv-*-elf i860-*-* i960-*-* -+#xfail: iq*-*-* mn10200-*-* moxie-*-* msp*-*-* mt-*-* or32-*-* pj*-*-* ++#xfail: iq*-*-* mn10200-*-* moxie-*-* msp*-*-* mt-*-* pj*-*-* +# if not using elf32.em, you don't get fancy section handling + +#... @@ -2776182,13 +2791328,13 @@ index 0000000..f155d66 +#pass diff --git a/ld/testsuite/ld-elf/provide-hidden.exp b/ld/testsuite/ld-elf/provide-hidden.exp new file mode 100644 -index 0000000..7246d11 +index 0000000..8bf5fdc --- /dev/null +++ b/ld/testsuite/ld-elf/provide-hidden.exp @@ -0,0 +1,154 @@ +# Expect script for the PROVIDE_HIDDEN linker script command. +# -+# Copyright 2013 Free Software Foundation, Inc. ++# Copyright (C) 2013-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2776340,6 +2791486,33 @@ index 0000000..7246d11 + [list readelf -s provide-hidden-abs.nd] \ + [list readelf -s provide-hidden-dyn.nd]] \ + "provide-hidden-12"]] +diff --git a/ld/testsuite/ld-elf/rdynamic-1.c b/ld/testsuite/ld-elf/rdynamic-1.c +new file mode 100644 +index 0000000..7c9d1ab +--- /dev/null ++++ b/ld/testsuite/ld-elf/rdynamic-1.c +@@ -0,0 +1,10 @@ ++void ++rdynamic () ++{ ++} ++ ++int ++main () ++{ ++ return 0; ++} +diff --git a/ld/testsuite/ld-elf/rdynamic-1.rd b/ld/testsuite/ld-elf/rdynamic-1.rd +new file mode 100644 +index 0000000..dbf3602 +--- /dev/null ++++ b/ld/testsuite/ld-elf/rdynamic-1.rd +@@ -0,0 +1,5 @@ ++Symbol table '\.dynsym' contains [0-9]+ entries: ++ +Num: +Value +Size Type +Bind +Vis +Ndx Name ++#... ++ +[0-9]+: +[0-9a-f]+ +[0-9a-f]+ +FUNC +GLOBAL +DEFAULT +[0-9]+ +_?rdynamic ++#... diff --git a/ld/testsuite/ld-elf/rel.c b/ld/testsuite/ld-elf/rel.c new file mode 100644 index 0000000..fd94f71 @@ -2776542,13 +2791715,13 @@ index 0000000..2b50f7e +} diff --git a/ld/testsuite/ld-elf/sec-to-seg.exp b/ld/testsuite/ld-elf/sec-to-seg.exp new file mode 100644 -index 0000000..c963055 +index 0000000..612dd0c --- /dev/null +++ b/ld/testsuite/ld-elf/sec-to-seg.exp @@ -0,0 +1,100 @@ +# Test the assigment of sections to segments. +# -+# Copyright 2008, 2010 Free Software Foundation, Inc. ++# Copyright (C) 2008-2014 Free Software Foundation, Inc. +# Contributed by Red Hat. +# +# This file is part of the GNU Binutils. @@ -2776682,13 +2791855,12 @@ index 0000000..b1dd078 + diff --git a/ld/testsuite/ld-elf/sec64k.exp b/ld/testsuite/ld-elf/sec64k.exp new file mode 100644 -index 0000000..7c9f292 +index 0000000..6821692 --- /dev/null +++ b/ld/testsuite/ld-elf/sec64k.exp -@@ -0,0 +1,207 @@ +@@ -0,0 +1,206 @@ +# Expect script for tests for >64k sections -+# Copyright 2002, 2003, 2005, 2006, 2007, 2008 -+# Free Software Foundation, Inc. ++# Copyright (C) 2002-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2776723,7 +2791895,7 @@ index 0000000..7c9f292 + || [istarget "dlx-*-*"] + || [istarget "i960-*-*"] + || [istarget "msp430*-*-*"] -+ || [istarget "or32-*-*"] ++ || [istarget "or1k*-*-*"] + || [istarget "pj*-*-*"] + || [istarget "m32r-*-*"] } { + return @@ -2776956,13 +2792128,12 @@ index 0000000..2f86acf +} diff --git a/ld/testsuite/ld-elf/shared.exp b/ld/testsuite/ld-elf/shared.exp new file mode 100644 -index 0000000..3162547 +index 0000000..0763cd4 --- /dev/null +++ b/ld/testsuite/ld-elf/shared.exp -@@ -0,0 +1,446 @@ +@@ -0,0 +1,491 @@ +# Expect script for various ELF tests. -+# Copyright 2006, 2007, 2008, 2009, 2010, 2011, 2012 -+# Free Software Foundation, Inc. ++# Copyright (C) 2006-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2777000,6 +2792171,11 @@ index 0000000..3162547 + return +} + ++# Add -ldl to extralibs if needed ++if { ![istarget *-*-freebsd*]} { ++ set extralibs "-ldl" ++} ++ +set build_tests { + {"Build libfoo.so" + "-shared" "-fPIC" @@ -2777180,6 +2792356,18 @@ index 0000000..3162547 + {"Build needed2" + "tmpdir/libneeded2c.o -Wl,--as-needed tmpdir/libneeded2a.so tmpdir/libneeded2b.so" "" + {dummy.c} {} "needed2"} ++ {"Build libpr2404a.so" ++ "-shared" "-fPIC" ++ {pr2404a.c} {} "libpr2404a.so"} ++ {"Build libpr2404b.a" ++ "" "" ++ {pr2404b.c} {} "libpr2404b.a"} ++ {"Build rdynamic-1" ++ "-rdynamic -Wl,--gc-sections" "-ffunction-sections" ++ {rdynamic-1.c} {{readelf {-s} rdynamic-1.rd}} "rdynamic-1"} ++ {"Build dynamic-1" ++ "-Wl,--dynamic-list,dynamic-1.syms -Wl,--gc-sections" "-ffunction-sections" ++ {dynamic-1.c} {{readelf {-s} dynamic-1.rd}} "dynamic-1"} +} + +run_cc_link_tests $build_tests @@ -2777226,10 +2792414,10 @@ index 0000000..3162547 + "tmpdir/libbarhfoov.so tmpdir/libfoov.so" "" + {main.c} "hidden" "hidden.out"} + {"Run dl1a with --dynamic-list=dl1.list and dlopen on libdl1.so" -+ "--dynamic-list=dl1.list -ldl" "" ++ "--dynamic-list=dl1.list $extralibs" "" + {dl1main.c} "dl1a" "dl1.out"} + {"Run dl1b with --dynamic-list-data and dlopen on libdl1.so" -+ "--dynamic-list-data -ldl" "" ++ "--dynamic-list-data $extralibs" "" + {dl1main.c} "dl1b" "dl1.out"} + {"Run with libdl2a.so" + "tmpdir/libdl2a.so" "" @@ -2777259,37 +2792447,37 @@ index 0000000..3162547 + "tmpdir/libdl4f.so" "" + {dl4main.c} "dl4f" "dl4a.out"} + {"Run dl6a1 with --dynamic-list-data and dlopen on libdl6a.so" -+ "--dynamic-list-data -ldl" "" ++ "--dynamic-list-data $extralibs" "" + {dl6amain.c} "dl6a1" "dl6a.out"} + {"Run dl6a2 with -Bsymbolic-functions and dlopen on libdl6a.so" -+ "-Bsymbolic-functions -ldl" "" ++ "-Bsymbolic-functions $extralibs" "" + {dl6amain.c} "dl6a2" "dl6b.out"} + {"Run dl6a3 with -Bsymbolic and dlopen on libdl6a.so" -+ "-Bsymbolic -ldl" "" ++ "-Bsymbolic $extralibs" "" + {dl6amain.c} "dl6a3" "dl6b.out"} + {"Run dl6a4 with -Bsymbolic --dynamic-list-data and dlopen on libdl6a.so" -+ "-Bsymbolic --dynamic-list-data -ldl" "" ++ "-Bsymbolic --dynamic-list-data $extralibs" "" + {dl6amain.c} "dl6a4" "dl6a.out"} + {"Run dl6a5 with -Bsymbolic-functions --dynamic-list-cpp-new and dlopen on libdl6a.so" -+ "-Bsymbolic-functions --dynamic-list-cpp-new -ldl" "" ++ "-Bsymbolic-functions --dynamic-list-cpp-new $extralibs" "" + {dl6amain.c} "dl6a5" "dl6b.out"} + {"Run dl6a6 with --dynamic-list-cpp-new -Bsymbolic-functions and dlopen on libdl6a.so" -+ "--dynamic-list-cpp-new -Bsymbolic-functions -ldl" "" ++ "--dynamic-list-cpp-new -Bsymbolic-functions $extralibs" "" + {dl6amain.c} "dl6a6" "dl6b.out"} + {"Run dl6a7 with --dynamic-list-data -Bsymbolic and dlopen on libdl6a.so" -+ "--dynamic-list-data -Bsymbolic -ldl" "" ++ "--dynamic-list-data -Bsymbolic $extralibs" "" + {dl6amain.c} "dl6a7" "dl6a.out"} + {"Run dl6b1 with --dynamic-list-data and dlopen on libdl6b.so" -+ "--dynamic-list-data -ldl" "" ++ "--dynamic-list-data $extralibs" "" + {dl6bmain.c} "dl6b1" "dl6a.out"} + {"Run dl6b2 with dlopen on libdl6b.so" -+ "-ldl" "" ++ "$extralibs" "" + {dl6bmain.c} "dl6b2" "dl6b.out"} + {"Run dl6c1 with --dynamic-list-data and dlopen on libdl6c.so" -+ "--dynamic-list-data -ldl" "" ++ "--dynamic-list-data $extralibs" "" + {dl6cmain.c} "dl6c1" "dl6b.out"} + {"Run dl6d1 with --dynamic-list-data and dlopen on libdl6d.so" -+ "--dynamic-list-data -ldl" "" ++ "--dynamic-list-data $extralibs" "" + {dl6dmain.c} "dl6d1" "dl6b.out"} + {"Run with libdata1.so" + "tmpdir/libdata1.so" "" @@ -2777327,6 +2792515,9 @@ index 0000000..3162547 + {"Run relmain" + "--no-as-needed -rpath=tmpdir -Ltmpdir -lrel" "" + {relmain.c} "relmain" "relmain.out"} ++ {"Run pr2404" ++ "tmpdir/pr2404b.o tmpdir/libpr2404a.so" "" ++ {dummy.c} "pr2404" "pr2404.out"} +} + +# NetBSD ELF systems do not currently support the .*_array sections. @@ -2777406,6 +2792597,32 @@ index 0000000..3162547 + +run_cc_link_tests $build_cxx_tests +run_ld_link_exec_tests [] $run_cxx_tests ++ ++if { [istarget *-*-linux*] ++ || [istarget *-*-nacl*] ++ || [istarget *-*-gnu*] } { ++ run_cc_link_tests [list \ ++ [list \ ++ "Build libpr2404b.a with PIE" \ ++ "" \ ++ "-fPIE" \ ++ { pr2404b.c } \ ++ {} \ ++ "libpr2404b.a" \ ++ ] \ ++ ] ++ run_ld_link_exec_tests [] [list \ ++ [list \ ++ "Run pr2404 with PIE" \ ++ "-pie tmpdir/pr2404b.o tmpdir/libpr2404a.so" \ ++ "" \ ++ { dummy.c } \ ++ "pr2404pie" \ ++ "pr2404.out" \ ++ "-fPIE" \ ++ ] \ ++ ] ++} diff --git a/ld/testsuite/ld-elf/simple.s b/ld/testsuite/ld-elf/simple.s new file mode 100644 index 0000000..2834182 @@ -2777821,12 +2793038,12 @@ index 0000000..b4237db +#pass diff --git a/ld/testsuite/ld-elf/tls_common.exp b/ld/testsuite/ld-elf/tls_common.exp new file mode 100644 -index 0000000..fee4031 +index 0000000..48a833f --- /dev/null +++ b/ld/testsuite/ld-elf/tls_common.exp @@ -0,0 +1,73 @@ +# Expect script for .tls_common tests -+# Copyright 2006, 2007, 2010, 2012 Free Software Foundation, Inc. ++# Copyright (C) 2006-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2778047,7 +2793264,7 @@ index 0000000..ba836ce +MAIN diff --git a/ld/testsuite/ld-elf/warn1.d b/ld/testsuite/ld-elf/warn1.d new file mode 100644 -index 0000000..3ef5032 +index 0000000..b22b64f --- /dev/null +++ b/ld/testsuite/ld-elf/warn1.d @@ -0,0 +1,15 @@ @@ -2778058,7 +2793275,7 @@ index 0000000..3ef5032 +#warning: ^[^\\n]*\): warning: witty one-liner$ +#readelf: -s +#notarget: "sparc64-*-solaris2*" "sparcv9-*-solaris2*" -+#xfail: "arc-*-*" "d30v-*-*" "dlx-*-*" "i960-*-*" "or32-*-*" "pj-*-*" ++#xfail: "arc-*-*" "d30v-*-*" "dlx-*-*" "i960-*-*" "pj-*-*" + +# Check that warnings are generated for the .gnu.warning.SYMBOL +# construct and that the symbol still appears as expected. @@ -2778068,7 +2793285,7 @@ index 0000000..3ef5032 +#pass diff --git a/ld/testsuite/ld-elf/warn2.d b/ld/testsuite/ld-elf/warn2.d new file mode 100644 -index 0000000..95b7ef4 +index 0000000..ee7220e --- /dev/null +++ b/ld/testsuite/ld-elf/warn2.d @@ -0,0 +1,17 @@ @@ -2778080,7 +2793297,7 @@ index 0000000..95b7ef4 +#readelf: -s +#notarget: "sparc64-*-solaris2*" "sparcv9-*-solaris2*" +#xfail: arc-*-* d30v-*-* dlx-*-* fr30-*-* frv-*-elf i860-*-* i960-*-* -+#xfail: iq*-*-* mn10200-*-* moxie-*-* msp*-*-* mt-*-* or32-*-* pj*-*-* ++#xfail: iq*-*-* mn10200-*-* moxie-*-* msp*-*-* mt-*-* pj*-*-* +# if not using elf32.em, you don't get fancy section handling + +# Check that warnings are generated for the symbols in .gnu.warning @@ -2778091,7 +2793308,7 @@ index 0000000..95b7ef4 +#pass diff --git a/ld/testsuite/ld-elf/warn3.d b/ld/testsuite/ld-elf/warn3.d new file mode 100644 -index 0000000..53dee18 +index 0000000..dc24540 --- /dev/null +++ b/ld/testsuite/ld-elf/warn3.d @@ -0,0 +1,14 @@ @@ -2778100,7 +2793317,7 @@ index 0000000..53dee18 +#warning: .*: warning: badsym warning$ +#readelf: -s +#notarget: hppa64*-hpux* -+#xfail: arc-*-* d30v-*-* dlx-*-* i960-*-* or32-*-* pj*-*-* ++#xfail: arc-*-* d30v-*-* dlx-*-* i960-*-* pj*-*-* +# generic linker targets don't support .gnu.warning sections. + +# Check that warnings are generated for the symbols in .gnu.warning @@ -2778182,12 +2793399,12 @@ index 0000000..82642bb +} diff --git a/ld/testsuite/ld-elf/wrap.exp b/ld/testsuite/ld-elf/wrap.exp new file mode 100644 -index 0000000..70e433d +index 0000000..3bf0588 --- /dev/null +++ b/ld/testsuite/ld-elf/wrap.exp @@ -0,0 +1,57 @@ +# Expect script for wrap ELF tests. -+# Copyright 2006, 2007 Free Software Foundation, Inc. ++# Copyright (C) 2006-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2778323,13 +2793540,12 @@ index 0000000..a375c90 +char foo2 [4]; diff --git a/ld/testsuite/ld-elfcomm/elfcomm.exp b/ld/testsuite/ld-elfcomm/elfcomm.exp new file mode 100644 -index 0000000..c5c7539 +index 0000000..ce2ff34 --- /dev/null +++ b/ld/testsuite/ld-elfcomm/elfcomm.exp -@@ -0,0 +1,273 @@ +@@ -0,0 +1,272 @@ +# Expect script for common symbol tests -+# Copyright 2003, 2005, 2006, 2007, 2008, 2009 -+# Free Software Foundation, Inc. ++# Copyright (C) 2003-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2778614,13 +2793830,12 @@ index 0000000..478d73e + diff --git a/ld/testsuite/ld-elfvers/vers.exp b/ld/testsuite/ld-elfvers/vers.exp new file mode 100644 -index 0000000..d1eedb7 +index 0000000..0743309 --- /dev/null +++ b/ld/testsuite/ld-elfvers/vers.exp -@@ -0,0 +1,1008 @@ +@@ -0,0 +1,1007 @@ +# Expect script for ld-version tests -+# Copyright 1997, 1998, 1999, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, -+# 2009, 2010, 2011, 2012 Free Software Foundation, Inc. ++# Copyright (C) 1997-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2781686,7 +2796901,7 @@ index 0000000..b38e3e0 +internal: diff --git a/ld/testsuite/ld-elfvsb/elf-offset.ld b/ld/testsuite/ld-elfvsb/elf-offset.ld new file mode 100644 -index 0000000..7c64824 +index 0000000..cd90bcc --- /dev/null +++ b/ld/testsuite/ld-elfvsb/elf-offset.ld @@ -0,0 +1,173 @@ @@ -2781823,7 +2797038,7 @@ index 0000000..7c64824 + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ -+ . = ALIGN(32 / 8); ++ . = ALIGN(. != 0 ? 32 / 8 : 1); + } + . = ALIGN(32 / 8); + _end = . ; @@ -2781897,13 +2797112,12 @@ index 0000000..bad3b1e +shlib_visibility_checkweak () == 1 diff --git a/ld/testsuite/ld-elfvsb/elfvsb.exp b/ld/testsuite/ld-elfvsb/elfvsb.exp new file mode 100644 -index 0000000..3a04501 +index 0000000..0577146 --- /dev/null +++ b/ld/testsuite/ld-elfvsb/elfvsb.exp -@@ -0,0 +1,535 @@ +@@ -0,0 +1,534 @@ +# Expect script for ld-visibility tests -+# Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2010, 2012 -+# Free Software Foundation, Inc. ++# Copyright (C) 2000-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2783537,13 +2798751,12 @@ index 0000000..5fdc694 +[0-9a-f]+[ ]+w[ ]+DO[ ]+\.s?data[ ]+[0-9a-f]+[ ]+(Base[ ]+|[ ]*)deallocate_foo diff --git a/ld/testsuite/ld-elfweak/elfweak.exp b/ld/testsuite/ld-elfweak/elfweak.exp new file mode 100644 -index 0000000..3a27465 +index 0000000..5da23d7 --- /dev/null +++ b/ld/testsuite/ld-elfweak/elfweak.exp -@@ -0,0 +1,523 @@ +@@ -0,0 +1,505 @@ +# Expect script for ld-weak tests -+# Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2010, 2012 -+# Free Software Foundation, Inc. ++# Copyright (C) 2001-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2783614,17 +2798827,6 @@ index 0000000..3a27465 +set shared "--shared -Wl,--no-as-needed" + + -+# -+proc setup_xfail_gnu_hurd {} { -+ global target_triplet -+ # Be cautious to not XFAIL for *-*-linux-gnu*, *-*-kfreebsd-gnu*, etc. -+ switch -regexp $target_triplet { -+ ^\[^-\]*-\[^-\]*-gnu.*$ { -+ setup_xfail "*-*-*" -+ } -+ } -+} -+ +# +# objdump_symstuff +# Dump non-dynamic symbol stuff and make sure that it is sane. @@ -2784011,9 +2799213,7 @@ index 0000000..3a27465 +build_lib "ELF DSO weak func last DSO" libfoo "libbar.so foo.o" dsow.dsym +build_exec "ELF weak func first" foo "main.o bar.o" "" strong "" strong.sym +build_exec "ELF weak func last" foo "bar.o main.o" "" strong "" strong.sym -+setup_xfail_gnu_hurd +build_exec "ELF weak func first DSO" foo "main.o libbar.so" "-Wl,-rpath,.,--no-as-needed" weak weak.dsym "" -+setup_xfail_gnu_hurd +build_exec "ELF weak func last DSO" foo "libbar.so main.o" "-Wl,-rpath,.,--no-as-needed" weak weak.dsym "" + +build_lib "ELF DSO weak data first" libfoo "bar1a.o foo1a.o" dsodata.dsym @@ -2784026,13 +2799226,9 @@ index 0000000..3a27465 +build_exec "ELF weak data last" foo "foo1a.o main1.o bar1a.o" "" strongdata "" strongdata.sym +build_exec "ELF weak data first common" foo "main1.o bar1a.o foo1b.o" "" strongdata "" strongcomm.sym +build_exec "ELF weak data last common" foo "foo1b.o main1.o bar1a.o" "" strongdata "" strongcomm.sym -+setup_xfail_gnu_hurd +build_exec "ELF weak data first DSO" foo "main1.o libbar1a.so libfoo1a.so" "-Wl,-rpath,.,--no-as-needed" weakdata weakdata.dsym "" -+setup_xfail_gnu_hurd +build_exec "ELF weak data last DSO" foo "libfoo1a.so main1.o libbar1a.so" "-Wl,-rpath,.,--no-as-needed" weakdata weakdata.dsym "" -+setup_xfail_gnu_hurd +build_exec "ELF weak data first DSO common" foo "main1.o libbar1a.so libfoo1b.so" "-Wl,-rpath,.,--no-as-needed" weakdata weakdata.dsym "" -+setup_xfail_gnu_hurd +build_exec "ELF weak data last DSO common" foo "libfoo1b.so main1.o libbar1a.so" "-Wl,-rpath,.,--no-as-needed" weakdata weakdata.dsym "" + +if ![ld_compile "$CC $CFLAGS $picflag" $srcdir/$subdir/size_foo.c $tmpdir/size_foo.o] { @@ -2784339,12 +2799535,12 @@ index 0000000..d8df66d +@extern_fastcall_function@0: diff --git a/ld/testsuite/ld-fastcall/fastcall.exp b/ld/testsuite/ld-fastcall/fastcall.exp new file mode 100644 -index 0000000..f0ee316 +index 0000000..bdc1eda --- /dev/null +++ b/ld/testsuite/ld-fastcall/fastcall.exp @@ -0,0 +1,52 @@ +# Test that the linker can handle fastcall symbols correctly. -+# Copyright 2002, 2005, 2006, 2007 Free Software Foundation, Inc. ++# Copyright (C) 2002-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2786028,12 +2801224,12 @@ index 0000000..c0cc732 +[0-9a-f ]+: 00 01 00 9c addx\.p gr16,gr28,gr0,icc0 diff --git a/ld/testsuite/ld-frv/fdpic.exp b/ld/testsuite/ld-frv/fdpic.exp new file mode 100644 -index 0000000..90da0d3 +index 0000000..21e8f6d --- /dev/null +++ b/ld/testsuite/ld-frv/fdpic.exp @@ -0,0 +1,69 @@ +# Expect script for FRV FDPIC linker tests -+# Copyright 2003, 2004, 2005, 2007 Free Software Foundation, Inc. ++# Copyright (C) 2003-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2786804,12 +2802000,12 @@ index 0000000..4e7fe2f + nop diff --git a/ld/testsuite/ld-frv/frv-elf.exp b/ld/testsuite/ld-frv/frv-elf.exp new file mode 100644 -index 0000000..961e0de +index 0000000..37dfa4f --- /dev/null +++ b/ld/testsuite/ld-frv/frv-elf.exp @@ -0,0 +1,23 @@ +# Expect script for FRV specific linker tests -+# Copyright (C) 2007 Free Software Foundation ++# Copyright (C) 2007-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2789397,12 +2804593,12 @@ index 0000000..e761cc8 + \.\.\. diff --git a/ld/testsuite/ld-frv/tls.exp b/ld/testsuite/ld-frv/tls.exp new file mode 100644 -index 0000000..1266be7 +index 0000000..630d0f4 --- /dev/null +++ b/ld/testsuite/ld-frv/tls.exp @@ -0,0 +1,65 @@ +# Expect script for FRV FDPIC TLS linker tests -+# Copyright 2003, 2004, 2005, 2007 Free Software Foundation, Inc. ++# Copyright (C) 2003-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2789558,13 +2804754,12 @@ index 0000000..3b0e655 +} diff --git a/ld/testsuite/ld-gc/gc.exp b/ld/testsuite/ld-gc/gc.exp new file mode 100644 -index 0000000..ddbbd51 +index 0000000..bb30a51 --- /dev/null +++ b/ld/testsuite/ld-gc/gc.exp -@@ -0,0 +1,138 @@ +@@ -0,0 +1,137 @@ +# Expect script for ld-gc tests -+# Copyright 2008, 2009, 2010, 2012 -+# Free Software Foundation, Inc. ++# Copyright (C) 2008-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2789830,38 +2805025,38 @@ index 0000000..fc26940 +# error: undefined reference to `unresolved_detected_at_runtime_not_at_linktime' diff --git a/ld/testsuite/ld-gc/pr13683.c b/ld/testsuite/ld-gc/pr13683.c new file mode 100644 -index 0000000..f8c8750 +index 0000000..c585e06 --- /dev/null +++ b/ld/testsuite/ld-gc/pr13683.c @@ -0,0 +1,28 @@ -+void foo(void); -+ -+int main(void) -+{ -+ foo (); -+ -+ for (;;) -+ ; -+} -+ -+int a; -+ -+void foo1(void) -+{ -+ a = 1; -+} -+ -+void foo2(void) -+{ -+ a = 2; -+} -+ -+void foo3(void) -+{ -+ a = 3; -+} -+ -+ ++void foo(void); ++ ++int main(void) ++{ ++ foo (); ++ ++ for (;;) ++ ; ++} ++ ++int a; ++ ++void foo1(void) ++{ ++ a = 1; ++} ++ ++void foo2(void) ++{ ++ a = 2; ++} ++ ++void foo3(void) ++{ ++ a = 3; ++} ++ ++ diff --git a/ld/testsuite/ld-gc/pr13683.d b/ld/testsuite/ld-gc/pr13683.d new file mode 100644 index 0000000..b38b9d1 @@ -2790064,12 +2805259,12 @@ index 0000000..2149ee9 + .end diff --git a/ld/testsuite/ld-h8300/h8300.exp b/ld/testsuite/ld-h8300/h8300.exp new file mode 100644 -index 0000000..240c7c3 +index 0000000..f047d2f --- /dev/null +++ b/ld/testsuite/ld-h8300/h8300.exp @@ -0,0 +1,45 @@ +# Expect script for ld-h8300 tests -+# Copyright 2002-2013 Free Software Foundation, Inc. ++# Copyright (C) 2002-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2790428,82 +2805623,82 @@ index 0000000..b8d38ce + 1e0: band #0x6,@0xff:8 diff --git a/ld/testsuite/ld-h8300/relax-4.s b/ld/testsuite/ld-h8300/relax-4.s new file mode 100644 -index 0000000..a537e10 +index 0000000..32b5b06 --- /dev/null +++ b/ld/testsuite/ld-h8300/relax-4.s @@ -0,0 +1,72 @@ -+; Relaxation is possible for following bit manipulation instructions -+; BAND, BCLR, BIAND, BILD, BIOR, BIST, BIXOR, BLD, BNOT, BOR, BSET, BST, BTST, BXOR -+ .h8300s -+ .globl _start -+ _start: -+ # s3-s6 aren't valid 16-bit addresses. -+ mov.b #0x3,r0l -+ mov.b #0x5,r2l -+; -+; Relaxation of aa:16 -+; -+ bset r0l,@s10:16 -+ bset r2l,@s9:16 -+ btst r2l,@s10:16 -+ btst r0l,@s9:16 -+ -+ bset #5,@s1:16 -+ bset #5,@s2:16 -+ bset #5,@s7:16 -+ bset #5,@s8:16 -+ bset #5,@s9:16 -+ bset #5,@s10:16 -+ -+ band #5,@s1:16 -+ band #5,@s2:16 -+ band #5,@s7:16 -+ band #5,@s8:16 -+ band #5,@s9:16 -+ band #5,@s10:16 -+; -+; Relaxation of aa:32 -+; -+ bset r2l,@s10:32 -+ bset r0l,@s9:32 -+ btst r0l,@s10:32 -+ btst r2l,@s9:32 -+ -+ bset #6,@s1:32 -+ bset #6,@s2:32 -+ bset #6,@s3:32 -+ bset #6,@s4:32 -+ bset #6,@s5:32 -+ bset #6,@s6:32 -+ bset #6,@s7:32 -+ bset #6,@s8:32 -+ bset #6,@s9:32 -+ bset #6,@s10:32 -+ -+ band #6,@s1:32 -+ band #6,@s2:32 -+ band #6,@s3:32 -+ band #6,@s4:32 -+ band #6,@s5:32 -+ band #6,@s6:32 -+ band #6,@s7:32 -+ band #6,@s8:32 -+ band #6,@s9:32 -+ band #6,@s10:32 -+ -+ .equ s1,0 -+ .equ s2,0x7fff -+ .equ s3,0x8000 -+ .equ s4,0xff00 -+ .equ s5,0xffff00 -+ .equ s6,0xffff7fff -+ .equ s7,0xffff8000 -+ .equ s8,0xfffffeff -+ .equ s9,0xffffff00 -+ .equ s10,0xffffffff -+ -+ .end -+ ++; Relaxation is possible for following bit manipulation instructions ++; BAND, BCLR, BIAND, BILD, BIOR, BIST, BIXOR, BLD, BNOT, BOR, BSET, BST, BTST, BXOR ++ .h8300s ++ .globl _start ++ _start: ++ # s3-s6 aren't valid 16-bit addresses. ++ mov.b #0x3,r0l ++ mov.b #0x5,r2l ++; ++; Relaxation of aa:16 ++; ++ bset r0l,@s10:16 ++ bset r2l,@s9:16 ++ btst r2l,@s10:16 ++ btst r0l,@s9:16 ++ ++ bset #5,@s1:16 ++ bset #5,@s2:16 ++ bset #5,@s7:16 ++ bset #5,@s8:16 ++ bset #5,@s9:16 ++ bset #5,@s10:16 ++ ++ band #5,@s1:16 ++ band #5,@s2:16 ++ band #5,@s7:16 ++ band #5,@s8:16 ++ band #5,@s9:16 ++ band #5,@s10:16 ++; ++; Relaxation of aa:32 ++; ++ bset r2l,@s10:32 ++ bset r0l,@s9:32 ++ btst r0l,@s10:32 ++ btst r2l,@s9:32 ++ ++ bset #6,@s1:32 ++ bset #6,@s2:32 ++ bset #6,@s3:32 ++ bset #6,@s4:32 ++ bset #6,@s5:32 ++ bset #6,@s6:32 ++ bset #6,@s7:32 ++ bset #6,@s8:32 ++ bset #6,@s9:32 ++ bset #6,@s10:32 ++ ++ band #6,@s1:32 ++ band #6,@s2:32 ++ band #6,@s3:32 ++ band #6,@s4:32 ++ band #6,@s5:32 ++ band #6,@s6:32 ++ band #6,@s7:32 ++ band #6,@s8:32 ++ band #6,@s9:32 ++ band #6,@s10:32 ++ ++ .equ s1,0 ++ .equ s2,0x7fff ++ .equ s3,0x8000 ++ .equ s4,0xff00 ++ .equ s5,0xffff00 ++ .equ s6,0xffff7fff ++ .equ s7,0xffff8000 ++ .equ s8,0xfffffeff ++ .equ s9,0xffffff00 ++ .equ s10,0xffffffff ++ ++ .end ++ diff --git a/ld/testsuite/ld-h8300/relax-5-coff.d b/ld/testsuite/ld-h8300/relax-5-coff.d new file mode 100644 index 0000000..eed2ba0 @@ -2791367,13 +2806562,13 @@ index 0000000..e609a2e + call foo@plt diff --git a/ld/testsuite/ld-i386/export-class.exp b/ld/testsuite/ld-i386/export-class.exp new file mode 100644 -index 0000000..98524a3 +index 0000000..7f24a79 --- /dev/null +++ b/ld/testsuite/ld-i386/export-class.exp @@ -0,0 +1,87 @@ +# Expect script for symbol export classes, i386 variation. +# -+# Copyright 2012 Free Software Foundation, Inc. ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2791575,13 +2806770,12 @@ index 0000000..a797f20 + 0x12340090 a0003412 00000000 00000000 00000000 .* diff --git a/ld/testsuite/ld-i386/i386.exp b/ld/testsuite/ld-i386/i386.exp new file mode 100644 -index 0000000..2667381 +index 0000000..04c399b --- /dev/null +++ b/ld/testsuite/ld-i386/i386.exp -@@ -0,0 +1,257 @@ +@@ -0,0 +1,256 @@ +# Expect script for ld-i386 tests -+# Copyright (C) 2002, 2005, 2006, 2007, 2008, 2009, 2010, 2012 -+# Free Software Foundation ++# Copyright (C) 2002-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2799349,12 +2814543,12 @@ index 0000000..e14d451 +#pass diff --git a/ld/testsuite/ld-ia64/ia64.exp b/ld/testsuite/ld-ia64/ia64.exp new file mode 100644 -index 0000000..1f658ac +index 0000000..490bffa --- /dev/null +++ b/ld/testsuite/ld-ia64/ia64.exp @@ -0,0 +1,64 @@ +# Expect script for ld-ia64 tests -+# Copyright (C) 2002, 2003, 2005, 2007 Free Software Foundation ++# Copyright (C) 2002-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2799419,13 +2814613,13 @@ index 0000000..1f658ac +} diff --git a/ld/testsuite/ld-ia64/line.exp b/ld/testsuite/ld-ia64/line.exp new file mode 100644 -index 0000000..2ebc7d6 +index 0000000..ab750ae --- /dev/null +++ b/ld/testsuite/ld-ia64/line.exp @@ -0,0 +1,57 @@ +# Test that the linker reports undefined symbol line number correctly. +# -+# Copyright 2007 Free Software Foundation, Inc. ++# Copyright (C) 2007-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2800796,12 +2815990,12 @@ index 0000000..d563c62 + stringz "function" diff --git a/ld/testsuite/ld-ifunc/binutils.exp b/ld/testsuite/ld-ifunc/binutils.exp new file mode 100644 -index 0000000..e035421 +index 0000000..91d4a8a --- /dev/null +++ b/ld/testsuite/ld-ifunc/binutils.exp @@ -0,0 +1,103 @@ +# Expect script for binutils tests -+# Copyright 2009, 2010, 2012 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2800903,6 +2816097,13 @@ index 0000000..e035421 +binutils_test objcopy "" ifunc-4-x86 +binutils_test strip "" ifunc-4-local-x86 +binutils_test objcopy "" ifunc-4-local-x86 +diff --git a/ld/testsuite/ld-ifunc/dummy.c b/ld/testsuite/ld-ifunc/dummy.c +new file mode 100644 +index 0000000..5c03287 +--- /dev/null ++++ b/ld/testsuite/ld-ifunc/dummy.c +@@ -0,0 +1 @@ ++/* An empty file. */ diff --git a/ld/testsuite/ld-ifunc/ifunc-1-local-x86.d b/ld/testsuite/ld-ifunc/ifunc-1-local-x86.d new file mode 100644 index 0000000..5408668 @@ -2803050,13 +2818251,13 @@ index 0000000..1235942 +} diff --git a/ld/testsuite/ld-ifunc/ifunc.exp b/ld/testsuite/ld-ifunc/ifunc.exp new file mode 100644 -index 0000000..fb106c6 +index 0000000..3faced1 --- /dev/null +++ b/ld/testsuite/ld-ifunc/ifunc.exp -@@ -0,0 +1,378 @@ +@@ -0,0 +1,423 @@ +# Expect script for linker support of IFUNC symbols and relocations. +# -+# Copyright 2009, 2010, 2012 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# Contributed by Red Hat. +# +# This file is part of the GNU Binutils. @@ -2803405,6 +2818606,42 @@ index 0000000..fb106c6 + remote_file host delete "tmpdir/static_nonifunc_prog" +} + ++run_cc_link_tests [list \ ++ [list \ ++ "Build libpr16467a.so" \ ++ "-shared -Wl,--version-script=pr16467a.map" \ ++ "-fPIC" \ ++ { pr16467a.c } \ ++ {} \ ++ "libpr16467a.so" \ ++ ] \ ++ [list \ ++ "Build libpr16467b.a" \ ++ "" \ ++ "-fPIC" \ ++ { pr16467b.c } \ ++ {} \ ++ "libpr16467b.a" \ ++ ] \ ++ [list \ ++ "Build libpr16467b.so" \ ++ "-shared tmpdir/pr16467b.o tmpdir/libpr16467a.so \ ++ -Wl,--version-script=pr16467b.map" \ ++ "-fPIC" \ ++ { dummy.c } \ ++ {} \ ++ "libpr16467b.so" \ ++ ] \ ++ [list \ ++ "Build libpr16467c.a" \ ++ "" \ ++ "" \ ++ { pr16467c.c } \ ++ {} \ ++ "libpr16467c.a" \ ++ ] \ ++] ++ +run_ld_link_exec_tests [] [list \ + [list \ + "Common symbol override ifunc test 1a" \ @@ -2803424,6 +2818661,15 @@ index 0000000..fb106c6 + "ifunc-common-1.out" \ + "-g" \ + ] \ ++ [list \ ++ "Run pr16467" \ ++ "tmpdir/pr16467c.o tmpdir/libpr16467b.so tmpdir/libpr16467a.so" \ ++ "" \ ++ { dummy.c } \ ++ "pr16467" \ ++ "pr16467.out" \ ++ "" \ ++ ] \ +] + +set test_list [lsort [glob -nocomplain $srcdir/$subdir/*.d]] @@ -2803477,6 +2818723,211 @@ index 0000000..393dabf +} + +#endif +diff --git a/ld/testsuite/ld-ifunc/pr16467.out b/ld/testsuite/ld-ifunc/pr16467.out +new file mode 100644 +index 0000000..d86bac9 +--- /dev/null ++++ b/ld/testsuite/ld-ifunc/pr16467.out +@@ -0,0 +1 @@ ++OK +diff --git a/ld/testsuite/ld-ifunc/pr16467a.c b/ld/testsuite/ld-ifunc/pr16467a.c +new file mode 100644 +index 0000000..ae3f084 +--- /dev/null ++++ b/ld/testsuite/ld-ifunc/pr16467a.c +@@ -0,0 +1,5 @@ ++const char * ++sd_get_seats(void) ++{ ++ return "OK"; ++} +diff --git a/ld/testsuite/ld-ifunc/pr16467a.map b/ld/testsuite/ld-ifunc/pr16467a.map +new file mode 100644 +index 0000000..d677f37 +--- /dev/null ++++ b/ld/testsuite/ld-ifunc/pr16467a.map +@@ -0,0 +1,4 @@ ++LIBSYSTEMD_209 { ++global: ++ sd_get_seats; ++}; +diff --git a/ld/testsuite/ld-ifunc/pr16467b.c b/ld/testsuite/ld-ifunc/pr16467b.c +new file mode 100644 +index 0000000..264f6cf +--- /dev/null ++++ b/ld/testsuite/ld-ifunc/pr16467b.c +@@ -0,0 +1,7 @@ ++void new_sd_get_seats(void); ++__asm__(".symver new_sd_get_seats,sd_get_seats@LIBSYSTEMD_209"); ++void (*resolve_sd_get_seats(void)) (void) __asm__ ("sd_get_seats"); ++void (*resolve_sd_get_seats(void)) (void) { ++ return new_sd_get_seats; ++} ++__asm__(".type sd_get_seats, %gnu_indirect_function"); +diff --git a/ld/testsuite/ld-ifunc/pr16467b.map b/ld/testsuite/ld-ifunc/pr16467b.map +new file mode 100644 +index 0000000..1f263de +--- /dev/null ++++ b/ld/testsuite/ld-ifunc/pr16467b.map +@@ -0,0 +1,4 @@ ++LIBSYSTEMD_208 { ++global: ++ sd_get_seats; ++}; +diff --git a/ld/testsuite/ld-ifunc/pr16467c.c b/ld/testsuite/ld-ifunc/pr16467c.c +new file mode 100644 +index 0000000..e2a901c +--- /dev/null ++++ b/ld/testsuite/ld-ifunc/pr16467c.c +@@ -0,0 +1,9 @@ ++#include ++const char* sd_get_seats(void); ++ ++int ++main (int argc, char **argv) ++{ ++ printf("%s\n", sd_get_seats()); ++ return 0; ++} +diff --git a/ld/testsuite/ld-ifunc/pr17154-i386.d b/ld/testsuite/ld-ifunc/pr17154-i386.d +new file mode 100644 +index 0000000..e526223 +--- /dev/null ++++ b/ld/testsuite/ld-ifunc/pr17154-i386.d +@@ -0,0 +1,47 @@ ++#source: pr17154-x86.s ++#ld: -m elf_i386 -shared ++#as: --32 ++#objdump: -dw ++#target: x86_64-*-* i?86-*-* ++ ++#... ++0+1d0 <\*ABS\*@plt-0x10>: ++[ ]*[a-f0-9]+: ff b3 04 00 00 00 pushl 0x4\(%ebx\) ++[ ]*[a-f0-9]+: ff a3 08 00 00 00 jmp \*0x8\(%ebx\) ++[ ]*[a-f0-9]+: 00 00 add %al,\(%eax\) ++ ... ++ ++0+1e0 <\*ABS\*@plt>: ++[ ]*[a-f0-9]+: ff a3 0c 00 00 00 jmp \*0xc\(%ebx\) ++[ ]*[a-f0-9]+: 68 18 00 00 00 push \$0x18 ++[ ]*[a-f0-9]+: e9 e0 ff ff ff jmp 1d0 <\*ABS\*@plt-0x10> ++ ++0+1f0 : ++[ ]*[a-f0-9]+: ff a3 10 00 00 00 jmp \*0x10\(%ebx\) ++[ ]*[a-f0-9]+: 68 00 00 00 00 push \$0x0 ++[ ]*[a-f0-9]+: e9 d0 ff ff ff jmp 1d0 <\*ABS\*@plt-0x10> ++ ++0+200 : ++[ ]*[a-f0-9]+: ff a3 14 00 00 00 jmp \*0x14\(%ebx\) ++[ ]*[a-f0-9]+: 68 08 00 00 00 push \$0x8 ++[ ]*[a-f0-9]+: e9 c0 ff ff ff jmp 1d0 <\*ABS\*@plt-0x10> ++ ++0+210 <\*ABS\*@plt>: ++[ ]*[a-f0-9]+: ff a3 18 00 00 00 jmp \*0x18\(%ebx\) ++[ ]*[a-f0-9]+: 68 10 00 00 00 push \$0x10 ++[ ]*[a-f0-9]+: e9 b0 ff ff ff jmp 1d0 <\*ABS\*@plt-0x10> ++ ++Disassembly of section .text: ++ ++0+220 : ++[ ]*[a-f0-9]+: e8 cb ff ff ff call 1f0 ++ ++0+225 : ++[ ]*[a-f0-9]+: e9 e6 ff ff ff jmp 210 <\*ABS\*@plt> ++ ++0+22a : ++[ ]*[a-f0-9]+: e8 d1 ff ff ff call 200 ++ ++0+22f : ++[ ]*[a-f0-9]+: e9 ac ff ff ff jmp 1e0 <\*ABS\*@plt> ++#pass +diff --git a/ld/testsuite/ld-ifunc/pr17154-x86-64.d b/ld/testsuite/ld-ifunc/pr17154-x86-64.d +new file mode 100644 +index 0000000..0dbc547 +--- /dev/null ++++ b/ld/testsuite/ld-ifunc/pr17154-x86-64.d +@@ -0,0 +1,46 @@ ++#source: pr17154-x86.s ++#as: --64 ++#ld: -shared -melf_x86_64 ++#objdump: -dw ++#target: x86_64-*-* ++ ++#... ++0+2d0 <\*ABS\*\+0x32a@plt-0x10>: ++[ ]*[a-f0-9]+: ff 35 5a 01 20 00 pushq 0x20015a\(%rip\) # 200430 <_GLOBAL_OFFSET_TABLE_\+0x8> ++[ ]*[a-f0-9]+: ff 25 5c 01 20 00 jmpq \*0x20015c\(%rip\) # 200438 <_GLOBAL_OFFSET_TABLE_\+0x10> ++[ ]*[a-f0-9]+: 0f 1f 40 00 nopl 0x0\(%rax\) ++ ++0+2e0 <\*ABS\*\+0x32a@plt>: ++[ ]*[a-f0-9]+: ff 25 5a 01 20 00 jmpq \*0x20015a\(%rip\) # 200440 <_GLOBAL_OFFSET_TABLE_\+0x18> ++[ ]*[a-f0-9]+: 68 03 00 00 00 pushq \$0x3 ++[ ]*[a-f0-9]+: e9 e0 ff ff ff jmpq 2d0 <\*ABS\*\+0x32a@plt-0x10> ++ ++0+2f0 : ++[ ]*[a-f0-9]+: ff 25 52 01 20 00 jmpq \*0x200152\(%rip\) # 200448 <_GLOBAL_OFFSET_TABLE_\+0x20> ++[ ]*[a-f0-9]+: 68 00 00 00 00 pushq \$0x0 ++[ ]*[a-f0-9]+: e9 d0 ff ff ff jmpq 2d0 <\*ABS\*\+0x32a@plt-0x10> ++ ++0+300 : ++[ ]*[a-f0-9]+: ff 25 4a 01 20 00 jmpq \*0x20014a\(%rip\) # 200450 <_GLOBAL_OFFSET_TABLE_\+0x28> ++[ ]*[a-f0-9]+: 68 01 00 00 00 pushq \$0x1 ++[ ]*[a-f0-9]+: e9 c0 ff ff ff jmpq 2d0 <\*ABS\*\+0x32a@plt-0x10> ++ ++0+310 <\*ABS\*\+0x320@plt>: ++[ ]*[a-f0-9]+: ff 25 42 01 20 00 jmpq \*0x200142\(%rip\) # 200458 <_GLOBAL_OFFSET_TABLE_\+0x30> ++[ ]*[a-f0-9]+: 68 02 00 00 00 pushq \$0x2 ++[ ]*[a-f0-9]+: e9 b0 ff ff ff jmpq 2d0 <\*ABS\*\+0x32a@plt-0x10> ++ ++Disassembly of section .text: ++ ++0+320 : ++[ ]*[a-f0-9]+: e8 cb ff ff ff callq 2f0 ++ ++0+325 : ++[ ]*[a-f0-9]+: e9 e6 ff ff ff jmpq 310 <\*ABS\*\+0x320@plt> ++ ++0+32a : ++[ ]*[a-f0-9]+: e8 d1 ff ff ff callq 300 ++ ++0+32f : ++[ ]*[a-f0-9]+: e9 ac ff ff ff jmpq 2e0 <\*ABS\*\+0x32a@plt> ++#pass +diff --git a/ld/testsuite/ld-ifunc/pr17154-x86.s b/ld/testsuite/ld-ifunc/pr17154-x86.s +new file mode 100644 +index 0000000..86470a2 +--- /dev/null ++++ b/ld/testsuite/ld-ifunc/pr17154-x86.s +@@ -0,0 +1,28 @@ ++ .text ++ .globl fct1 ++ .type fct1, @gnu_indirect_function ++ .set fct1,resolve1 ++ .hidden int_fct1 ++ .globl int_fct1 ++ .set int_fct1,fct1 ++ .type resolve1, @function ++resolve1: ++ call func1@PLT ++ .globl g1 ++ .type g1, @function ++g1: ++ jmp int_fct1@PLT ++ ++ .globl fct2 ++ .type fct2, @gnu_indirect_function ++ .set fct2,resolve2 ++ .hidden int_fct2 ++ .globl int_fct2 ++ .set int_fct2,fct2 ++ .type resolve2, @function ++resolve2: ++ call func2@PLT ++ .globl g2 ++ .type g2, @function ++g2: ++ jmp int_fct2@PLT diff --git a/ld/testsuite/ld-ifunc/prog.c b/ld/testsuite/ld-ifunc/prog.c new file mode 100644 index 0000000..da786a5 @@ -2803575,12 +2819026,12 @@ index 0000000..b1544f3 + bar == 0x1000 diff --git a/ld/testsuite/ld-libs/libs.exp b/ld/testsuite/ld-libs/libs.exp new file mode 100644 -index 0000000..96d9850 +index 0000000..d067585 --- /dev/null +++ b/ld/testsuite/ld-libs/libs.exp @@ -0,0 +1,30 @@ +# Expect script for the linker's -l command line option -+# Copyright (C) 2007 Free Software Foundation ++# Copyright (C) 2007-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2803611,12 +2819062,12 @@ index 0000000..96d9850 +} diff --git a/ld/testsuite/ld-linkonce/linkonce.exp b/ld/testsuite/ld-linkonce/linkonce.exp new file mode 100644 -index 0000000..0211114 +index 0000000..b811db1 --- /dev/null +++ b/ld/testsuite/ld-linkonce/linkonce.exp @@ -0,0 +1,47 @@ +# Expect script for ld linkonce tests -+# Copyright 2001, 2002, 2005, 2007, 2010, 2012 Free Software Foundation, Inc. ++# Copyright (C) 2001-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2804614,12 +2820065,12 @@ index 0000000..868d4cf + bra _start diff --git a/ld/testsuite/ld-m68hc11/m68hc11.exp b/ld/testsuite/ld-m68hc11/m68hc11.exp new file mode 100644 -index 0000000..d673bc0 +index 0000000..3f02216 --- /dev/null +++ b/ld/testsuite/ld-m68hc11/m68hc11.exp @@ -0,0 +1,35 @@ +# Expect script for run_dump_test based ld-m68hc11 tests. -+# Copyright 2002, 2005, 2007, 2012 Free Software Foundation, Inc. ++# Copyright (C) 2002-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2805634,12 +2821085,12 @@ index 0000000..3f93db7 + nop diff --git a/ld/testsuite/ld-m68k/m68k-got.exp b/ld/testsuite/ld-m68k/m68k-got.exp new file mode 100644 -index 0000000..fbd98bc +index 0000000..992e14f --- /dev/null +++ b/ld/testsuite/ld-m68k/m68k-got.exp @@ -0,0 +1,250 @@ +# Expect script for run_dump_test based ld-m68k GOT tests. -+# Copyright 2008, 2009 Free Software Foundation, Inc. ++# Copyright (C) 2008-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2805890,12 +2821341,12 @@ index 0000000..fbd98bc +got_test "got-xgot-12-13-14-15-34-35-ok" diff --git a/ld/testsuite/ld-m68k/m68k.exp b/ld/testsuite/ld-m68k/m68k.exp new file mode 100644 -index 0000000..6917436 +index 0000000..05a6728 --- /dev/null +++ b/ld/testsuite/ld-m68k/m68k.exp @@ -0,0 +1,93 @@ +# Expect script for run_dump_test based ld-m68k tests. -+# Copyright 2006, 2007, 2008, 2009, 2012 Free Software Foundation, Inc. ++# Copyright (C) 2006-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2806853,12 +2822304,12 @@ index 0000000..4e59919 + .section .note.GNU-stack,"",@progbits diff --git a/ld/testsuite/ld-mep/mep.exp b/ld/testsuite/ld-mep/mep.exp new file mode 100644 -index 0000000..3c54f8f +index 0000000..cf8f159 --- /dev/null +++ b/ld/testsuite/ld-mep/mep.exp @@ -0,0 +1,38 @@ +# Expect script for ld-mep tests -+# Copyright 2002, 2007 Free Software Foundation, Inc. ++# Copyright (C) 2002-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2806942,13 +2822393,13 @@ index 0000000..2907e9e \ No newline at end of file diff --git a/ld/testsuite/ld-metag/metag.exp b/ld/testsuite/ld-metag/metag.exp new file mode 100644 -index 0000000..b817e10 +index 0000000..5b1df3b --- /dev/null +++ b/ld/testsuite/ld-metag/metag.exp @@ -0,0 +1,61 @@ +# Expect script for ld-metag tests +# -+# Copyright (C) 2013 Free Software Foundation, Inc. ++# Copyright (C) 2013-2014 Free Software Foundation, Inc. +# Contributed by Imagination Technologies Ltd. +# +# This program is free software; you can redistribute it and/or modify @@ -2808062,13 +2823513,13 @@ index 0000000..0cd3701 +#pass diff --git a/ld/testsuite/ld-mips-elf/comm-data.exp b/ld/testsuite/ld-mips-elf/comm-data.exp new file mode 100644 -index 0000000..2b6fa83 +index 0000000..76f1c39 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/comm-data.exp @@ -0,0 +1,90 @@ +# Expect script for common symbol override, MIPS variation. +# -+# Copyright 2011 Free Software Foundation, Inc. ++# Copyright (C) 2011-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2818406,7 +2833857,7 @@ index 0000000..55dd7ae + \.\.\. diff --git a/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32-embed.d b/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32-embed.d new file mode 100644 -index 0000000..1d0c045 +index 0000000..a0bef16 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32-embed.d @@ -0,0 +1,434 @@ @@ -2818430,382 +2833881,382 @@ index 0000000..1d0c045 +10000074 : +10000074: 3c050000 lui a1,0x0 +10000078: 00bc2821 addu a1,a1,gp -+1000007c: 8ca58018 lw a1,-32744\(a1\) ++1000007c: 8ca58038 lw a1,-32712\(a1\) +10000080: 3c050000 lui a1,0x0 +10000084: 00bc2821 addu a1,a1,gp -+10000088: 8ca58018 lw a1,-32744\(a1\) ++10000088: 8ca58038 lw a1,-32712\(a1\) +1000008c: 24a5000c addiu a1,a1,12 +10000090: 3c050000 lui a1,0x0 +10000094: 00bc2821 addu a1,a1,gp -+10000098: 8ca58018 lw a1,-32744\(a1\) ++10000098: 8ca58038 lw a1,-32712\(a1\) +1000009c: 3c010001 lui at,0x1 +100000a0: 3421e240 ori at,at,0xe240 +100000a4: 00a12821 addu a1,a1,at +100000a8: 3c050000 lui a1,0x0 +100000ac: 00bc2821 addu a1,a1,gp -+100000b0: 8ca58018 lw a1,-32744\(a1\) ++100000b0: 8ca58038 lw a1,-32712\(a1\) +100000b4: 00b12821 addu a1,a1,s1 +100000b8: 3c050000 lui a1,0x0 +100000bc: 00bc2821 addu a1,a1,gp -+100000c0: 8ca58018 lw a1,-32744\(a1\) ++100000c0: 8ca58038 lw a1,-32712\(a1\) +100000c4: 24a5000c addiu a1,a1,12 +100000c8: 00b12821 addu a1,a1,s1 +100000cc: 3c050000 lui a1,0x0 +100000d0: 00bc2821 addu a1,a1,gp -+100000d4: 8ca58018 lw a1,-32744\(a1\) ++100000d4: 8ca58038 lw a1,-32712\(a1\) +100000d8: 3c010001 lui at,0x1 +100000dc: 3421e240 ori at,at,0xe240 +100000e0: 00a12821 addu a1,a1,at +100000e4: 00b12821 addu a1,a1,s1 +100000e8: 3c050000 lui a1,0x0 +100000ec: 00bc2821 addu a1,a1,gp -+100000f0: 8ca58018 lw a1,-32744\(a1\) ++100000f0: 8ca58038 lw a1,-32712\(a1\) +100000f4: 8ca50000 lw a1,0\(a1\) +100000f8: 3c050000 lui a1,0x0 +100000fc: 00bc2821 addu a1,a1,gp -+10000100: 8ca58018 lw a1,-32744\(a1\) ++10000100: 8ca58038 lw a1,-32712\(a1\) +10000104: 8ca5000c lw a1,12\(a1\) +10000108: 3c050000 lui a1,0x0 +1000010c: 00bc2821 addu a1,a1,gp -+10000110: 8ca58018 lw a1,-32744\(a1\) ++10000110: 8ca58038 lw a1,-32712\(a1\) +10000114: 00b12821 addu a1,a1,s1 +10000118: 8ca50000 lw a1,0\(a1\) +1000011c: 3c050000 lui a1,0x0 +10000120: 00bc2821 addu a1,a1,gp -+10000124: 8ca58018 lw a1,-32744\(a1\) ++10000124: 8ca58038 lw a1,-32712\(a1\) +10000128: 00b12821 addu a1,a1,s1 +1000012c: 8ca5000c lw a1,12\(a1\) +10000130: 3c010000 lui at,0x0 +10000134: 003c0821 addu at,at,gp -+10000138: 8c218018 lw at,-32744\(at\) ++10000138: 8c218038 lw at,-32712\(at\) +1000013c: 00250821 addu at,at,a1 +10000140: 8c250022 lw a1,34\(at\) +10000144: 3c010000 lui at,0x0 +10000148: 003c0821 addu at,at,gp -+1000014c: 8c218018 lw at,-32744\(at\) ++1000014c: 8c218038 lw at,-32712\(at\) +10000150: 00250821 addu at,at,a1 +10000154: ac250038 sw a1,56\(at\) +10000158: 3c010000 lui at,0x0 +1000015c: 003c0821 addu at,at,gp -+10000160: 8c218018 lw at,-32744\(at\) ++10000160: 8c218038 lw at,-32712\(at\) +10000164: 88250000 lwl a1,0\(at\) +10000168: 98250003 lwr a1,3\(at\) +1000016c: 3c010000 lui at,0x0 +10000170: 003c0821 addu at,at,gp -+10000174: 8c218018 lw at,-32744\(at\) ++10000174: 8c218038 lw at,-32712\(at\) +10000178: 2421000c addiu at,at,12 +1000017c: 88250000 lwl a1,0\(at\) +10000180: 98250003 lwr a1,3\(at\) +10000184: 3c010000 lui at,0x0 +10000188: 003c0821 addu at,at,gp -+1000018c: 8c218018 lw at,-32744\(at\) ++1000018c: 8c218038 lw at,-32712\(at\) +10000190: 00310821 addu at,at,s1 +10000194: 88250000 lwl a1,0\(at\) +10000198: 98250003 lwr a1,3\(at\) +1000019c: 3c010000 lui at,0x0 +100001a0: 003c0821 addu at,at,gp -+100001a4: 8c218018 lw at,-32744\(at\) ++100001a4: 8c218038 lw at,-32712\(at\) +100001a8: 2421000c addiu at,at,12 +100001ac: 00310821 addu at,at,s1 +100001b0: 88250000 lwl a1,0\(at\) +100001b4: 98250003 lwr a1,3\(at\) +100001b8: 3c010000 lui at,0x0 +100001bc: 003c0821 addu at,at,gp -+100001c0: 8c218018 lw at,-32744\(at\) ++100001c0: 8c218038 lw at,-32712\(at\) +100001c4: 24210022 addiu at,at,34 +100001c8: 00250821 addu at,at,a1 +100001cc: 88250000 lwl a1,0\(at\) +100001d0: 98250003 lwr a1,3\(at\) +100001d4: 3c010000 lui at,0x0 +100001d8: 003c0821 addu at,at,gp -+100001dc: 8c218018 lw at,-32744\(at\) ++100001dc: 8c218038 lw at,-32712\(at\) +100001e0: 24210038 addiu at,at,56 +100001e4: 00250821 addu at,at,a1 +100001e8: a8250000 swl a1,0\(at\) +100001ec: b8250003 swr a1,3\(at\) -+100001f0: 8f85801c lw a1,-32740\(gp\) ++100001f0: 8f858018 lw a1,-32744\(gp\) +100001f4: 24a506b8 addiu a1,a1,1720 -+100001f8: 8f85801c lw a1,-32740\(gp\) ++100001f8: 8f858018 lw a1,-32744\(gp\) +100001fc: 24a506c4 addiu a1,a1,1732 -+10000200: 8f858020 lw a1,-32736\(gp\) ++10000200: 8f85801c lw a1,-32740\(gp\) +10000204: 24a5e8f8 addiu a1,a1,-5896 -+10000208: 8f85801c lw a1,-32740\(gp\) ++10000208: 8f858018 lw a1,-32744\(gp\) +1000020c: 24a506b8 addiu a1,a1,1720 +10000210: 00b12821 addu a1,a1,s1 -+10000214: 8f85801c lw a1,-32740\(gp\) ++10000214: 8f858018 lw a1,-32744\(gp\) +10000218: 24a506c4 addiu a1,a1,1732 +1000021c: 00b12821 addu a1,a1,s1 -+10000220: 8f858020 lw a1,-32736\(gp\) ++10000220: 8f85801c lw a1,-32740\(gp\) +10000224: 24a5e8f8 addiu a1,a1,-5896 +10000228: 00b12821 addu a1,a1,s1 -+1000022c: 8f85801c lw a1,-32740\(gp\) ++1000022c: 8f858018 lw a1,-32744\(gp\) +10000230: 8ca506b8 lw a1,1720\(a1\) -+10000234: 8f85801c lw a1,-32740\(gp\) ++10000234: 8f858018 lw a1,-32744\(gp\) +10000238: 8ca506c4 lw a1,1732\(a1\) -+1000023c: 8f85801c lw a1,-32740\(gp\) ++1000023c: 8f858018 lw a1,-32744\(gp\) +10000240: 00b12821 addu a1,a1,s1 +10000244: 8ca506b8 lw a1,1720\(a1\) -+10000248: 8f85801c lw a1,-32740\(gp\) ++10000248: 8f858018 lw a1,-32744\(gp\) +1000024c: 00b12821 addu a1,a1,s1 +10000250: 8ca506c4 lw a1,1732\(a1\) -+10000254: 8f81801c lw at,-32740\(gp\) ++10000254: 8f818018 lw at,-32744\(gp\) +10000258: 00250821 addu at,at,a1 +1000025c: 8c2506da lw a1,1754\(at\) -+10000260: 8f81801c lw at,-32740\(gp\) ++10000260: 8f818018 lw at,-32744\(gp\) +10000264: 00250821 addu at,at,a1 +10000268: ac2506f0 sw a1,1776\(at\) -+1000026c: 8f81801c lw at,-32740\(gp\) ++1000026c: 8f818018 lw at,-32744\(gp\) +10000270: 242106b8 addiu at,at,1720 +10000274: 88250000 lwl a1,0\(at\) +10000278: 98250003 lwr a1,3\(at\) -+1000027c: 8f81801c lw at,-32740\(gp\) ++1000027c: 8f818018 lw at,-32744\(gp\) +10000280: 242106c4 addiu at,at,1732 +10000284: 88250000 lwl a1,0\(at\) +10000288: 98250003 lwr a1,3\(at\) -+1000028c: 8f81801c lw at,-32740\(gp\) ++1000028c: 8f818018 lw at,-32744\(gp\) +10000290: 242106b8 addiu at,at,1720 +10000294: 00310821 addu at,at,s1 +10000298: 88250000 lwl a1,0\(at\) +1000029c: 98250003 lwr a1,3\(at\) -+100002a0: 8f81801c lw at,-32740\(gp\) ++100002a0: 8f818018 lw at,-32744\(gp\) +100002a4: 242106c4 addiu at,at,1732 +100002a8: 00310821 addu at,at,s1 +100002ac: 88250000 lwl a1,0\(at\) +100002b0: 98250003 lwr a1,3\(at\) -+100002b4: 8f81801c lw at,-32740\(gp\) ++100002b4: 8f818018 lw at,-32744\(gp\) +100002b8: 242106da addiu at,at,1754 +100002bc: 00250821 addu at,at,a1 +100002c0: 88250000 lwl a1,0\(at\) +100002c4: 98250003 lwr a1,3\(at\) -+100002c8: 8f81801c lw at,-32740\(gp\) ++100002c8: 8f818018 lw at,-32744\(gp\) +100002cc: 242106f0 addiu at,at,1776 +100002d0: 00250821 addu at,at,a1 +100002d4: a8250000 swl a1,0\(at\) +100002d8: b8250003 swr a1,3\(at\) +100002dc: 3c050000 lui a1,0x0 +100002e0: 00bc2821 addu a1,a1,gp -+100002e4: 8ca58024 lw a1,-32732\(a1\) -+100002e8: 8f858028 lw a1,-32728\(gp\) ++100002e4: 8ca58034 lw a1,-32716\(a1\) ++100002e8: 8f858020 lw a1,-32736\(gp\) +100002ec: 24a50074 addiu a1,a1,116 +100002f0: 3c190000 lui t9,0x0 +100002f4: 033cc821 addu t9,t9,gp -+100002f8: 8f398024 lw t9,-32732\(t9\) -+100002fc: 8f998028 lw t9,-32728\(gp\) ++100002f8: 8f398034 lw t9,-32716\(t9\) ++100002fc: 8f998020 lw t9,-32736\(gp\) +10000300: 27390074 addiu t9,t9,116 +10000304: 3c190000 lui t9,0x0 +10000308: 033cc821 addu t9,t9,gp -+1000030c: 8f398024 lw t9,-32732\(t9\) ++1000030c: 8f398034 lw t9,-32716\(t9\) +10000310: 0411ff58 bal 10000074 +10000314: 00000000 nop -+10000318: 8f998028 lw t9,-32728\(gp\) ++10000318: 8f998020 lw t9,-32736\(gp\) +1000031c: 27390074 addiu t9,t9,116 +10000320: 0411ff54 bal 10000074 +10000324: 00000000 nop +10000328: 3c050000 lui a1,0x0 +1000032c: 00bc2821 addu a1,a1,gp -+10000330: 8ca5802c lw a1,-32724\(a1\) ++10000330: 8ca58030 lw a1,-32720\(a1\) +10000334: 3c050000 lui a1,0x0 +10000338: 00bc2821 addu a1,a1,gp -+1000033c: 8ca5802c lw a1,-32724\(a1\) ++1000033c: 8ca58030 lw a1,-32720\(a1\) +10000340: 24a5000c addiu a1,a1,12 +10000344: 3c050000 lui a1,0x0 +10000348: 00bc2821 addu a1,a1,gp -+1000034c: 8ca5802c lw a1,-32724\(a1\) ++1000034c: 8ca58030 lw a1,-32720\(a1\) +10000350: 3c010001 lui at,0x1 +10000354: 3421e240 ori at,at,0xe240 +10000358: 00a12821 addu a1,a1,at +1000035c: 3c050000 lui a1,0x0 +10000360: 00bc2821 addu a1,a1,gp -+10000364: 8ca5802c lw a1,-32724\(a1\) ++10000364: 8ca58030 lw a1,-32720\(a1\) +10000368: 00b12821 addu a1,a1,s1 +1000036c: 3c050000 lui a1,0x0 +10000370: 00bc2821 addu a1,a1,gp -+10000374: 8ca5802c lw a1,-32724\(a1\) ++10000374: 8ca58030 lw a1,-32720\(a1\) +10000378: 24a5000c addiu a1,a1,12 +1000037c: 00b12821 addu a1,a1,s1 +10000380: 3c050000 lui a1,0x0 +10000384: 00bc2821 addu a1,a1,gp -+10000388: 8ca5802c lw a1,-32724\(a1\) ++10000388: 8ca58030 lw a1,-32720\(a1\) +1000038c: 3c010001 lui at,0x1 +10000390: 3421e240 ori at,at,0xe240 +10000394: 00a12821 addu a1,a1,at +10000398: 00b12821 addu a1,a1,s1 +1000039c: 3c050000 lui a1,0x0 +100003a0: 00bc2821 addu a1,a1,gp -+100003a4: 8ca5802c lw a1,-32724\(a1\) ++100003a4: 8ca58030 lw a1,-32720\(a1\) +100003a8: 8ca50000 lw a1,0\(a1\) +100003ac: 3c050000 lui a1,0x0 +100003b0: 00bc2821 addu a1,a1,gp -+100003b4: 8ca5802c lw a1,-32724\(a1\) ++100003b4: 8ca58030 lw a1,-32720\(a1\) +100003b8: 8ca5000c lw a1,12\(a1\) +100003bc: 3c050000 lui a1,0x0 +100003c0: 00bc2821 addu a1,a1,gp -+100003c4: 8ca5802c lw a1,-32724\(a1\) ++100003c4: 8ca58030 lw a1,-32720\(a1\) +100003c8: 00b12821 addu a1,a1,s1 +100003cc: 8ca50000 lw a1,0\(a1\) +100003d0: 3c050000 lui a1,0x0 +100003d4: 00bc2821 addu a1,a1,gp -+100003d8: 8ca5802c lw a1,-32724\(a1\) ++100003d8: 8ca58030 lw a1,-32720\(a1\) +100003dc: 00b12821 addu a1,a1,s1 +100003e0: 8ca5000c lw a1,12\(a1\) +100003e4: 3c010000 lui at,0x0 +100003e8: 003c0821 addu at,at,gp -+100003ec: 8c21802c lw at,-32724\(at\) ++100003ec: 8c218030 lw at,-32720\(at\) +100003f0: 00250821 addu at,at,a1 +100003f4: 8c250022 lw a1,34\(at\) +100003f8: 3c010000 lui at,0x0 +100003fc: 003c0821 addu at,at,gp -+10000400: 8c21802c lw at,-32724\(at\) ++10000400: 8c218030 lw at,-32720\(at\) +10000404: 00250821 addu at,at,a1 +10000408: ac250038 sw a1,56\(at\) +1000040c: 3c010000 lui at,0x0 +10000410: 003c0821 addu at,at,gp -+10000414: 8c21802c lw at,-32724\(at\) ++10000414: 8c218030 lw at,-32720\(at\) +10000418: 88250000 lwl a1,0\(at\) +1000041c: 98250003 lwr a1,3\(at\) +10000420: 3c010000 lui at,0x0 +10000424: 003c0821 addu at,at,gp -+10000428: 8c21802c lw at,-32724\(at\) ++10000428: 8c218030 lw at,-32720\(at\) +1000042c: 2421000c addiu at,at,12 +10000430: 88250000 lwl a1,0\(at\) +10000434: 98250003 lwr a1,3\(at\) +10000438: 3c010000 lui at,0x0 +1000043c: 003c0821 addu at,at,gp -+10000440: 8c21802c lw at,-32724\(at\) ++10000440: 8c218030 lw at,-32720\(at\) +10000444: 00310821 addu at,at,s1 +10000448: 88250000 lwl a1,0\(at\) +1000044c: 98250003 lwr a1,3\(at\) +10000450: 3c010000 lui at,0x0 +10000454: 003c0821 addu at,at,gp -+10000458: 8c21802c lw at,-32724\(at\) ++10000458: 8c218030 lw at,-32720\(at\) +1000045c: 2421000c addiu at,at,12 +10000460: 00310821 addu at,at,s1 +10000464: 88250000 lwl a1,0\(at\) +10000468: 98250003 lwr a1,3\(at\) +1000046c: 3c010000 lui at,0x0 +10000470: 003c0821 addu at,at,gp -+10000474: 8c21802c lw at,-32724\(at\) ++10000474: 8c218030 lw at,-32720\(at\) +10000478: 24210022 addiu at,at,34 +1000047c: 00250821 addu at,at,a1 +10000480: 88250000 lwl a1,0\(at\) +10000484: 98250003 lwr a1,3\(at\) +10000488: 3c010000 lui at,0x0 +1000048c: 003c0821 addu at,at,gp -+10000490: 8c21802c lw at,-32724\(at\) ++10000490: 8c218030 lw at,-32720\(at\) +10000494: 24210038 addiu at,at,56 +10000498: 00250821 addu at,at,a1 +1000049c: a8250000 swl a1,0\(at\) +100004a0: b8250003 swr a1,3\(at\) -+100004a4: 8f85801c lw a1,-32740\(gp\) ++100004a4: 8f858018 lw a1,-32744\(gp\) +100004a8: 24a50730 addiu a1,a1,1840 -+100004ac: 8f85801c lw a1,-32740\(gp\) ++100004ac: 8f858018 lw a1,-32744\(gp\) +100004b0: 24a5073c addiu a1,a1,1852 -+100004b4: 8f858020 lw a1,-32736\(gp\) ++100004b4: 8f85801c lw a1,-32740\(gp\) +100004b8: 24a5e970 addiu a1,a1,-5776 -+100004bc: 8f85801c lw a1,-32740\(gp\) ++100004bc: 8f858018 lw a1,-32744\(gp\) +100004c0: 24a50730 addiu a1,a1,1840 +100004c4: 00b12821 addu a1,a1,s1 -+100004c8: 8f85801c lw a1,-32740\(gp\) ++100004c8: 8f858018 lw a1,-32744\(gp\) +100004cc: 24a5073c addiu a1,a1,1852 +100004d0: 00b12821 addu a1,a1,s1 -+100004d4: 8f858020 lw a1,-32736\(gp\) ++100004d4: 8f85801c lw a1,-32740\(gp\) +100004d8: 24a5e970 addiu a1,a1,-5776 +100004dc: 00b12821 addu a1,a1,s1 -+100004e0: 8f85801c lw a1,-32740\(gp\) ++100004e0: 8f858018 lw a1,-32744\(gp\) +100004e4: 8ca50730 lw a1,1840\(a1\) -+100004e8: 8f85801c lw a1,-32740\(gp\) ++100004e8: 8f858018 lw a1,-32744\(gp\) +100004ec: 8ca5073c lw a1,1852\(a1\) -+100004f0: 8f85801c lw a1,-32740\(gp\) ++100004f0: 8f858018 lw a1,-32744\(gp\) +100004f4: 00b12821 addu a1,a1,s1 +100004f8: 8ca50730 lw a1,1840\(a1\) -+100004fc: 8f85801c lw a1,-32740\(gp\) ++100004fc: 8f858018 lw a1,-32744\(gp\) +10000500: 00b12821 addu a1,a1,s1 +10000504: 8ca5073c lw a1,1852\(a1\) -+10000508: 8f81801c lw at,-32740\(gp\) ++10000508: 8f818018 lw at,-32744\(gp\) +1000050c: 00250821 addu at,at,a1 +10000510: 8c250752 lw a1,1874\(at\) -+10000514: 8f81801c lw at,-32740\(gp\) ++10000514: 8f818018 lw at,-32744\(gp\) +10000518: 00250821 addu at,at,a1 +1000051c: ac250768 sw a1,1896\(at\) -+10000520: 8f81801c lw at,-32740\(gp\) ++10000520: 8f818018 lw at,-32744\(gp\) +10000524: 24210730 addiu at,at,1840 +10000528: 88250000 lwl a1,0\(at\) +1000052c: 98250003 lwr a1,3\(at\) -+10000530: 8f81801c lw at,-32740\(gp\) ++10000530: 8f818018 lw at,-32744\(gp\) +10000534: 2421073c addiu at,at,1852 +10000538: 88250000 lwl a1,0\(at\) +1000053c: 98250003 lwr a1,3\(at\) -+10000540: 8f81801c lw at,-32740\(gp\) ++10000540: 8f818018 lw at,-32744\(gp\) +10000544: 24210730 addiu at,at,1840 +10000548: 00310821 addu at,at,s1 +1000054c: 88250000 lwl a1,0\(at\) +10000550: 98250003 lwr a1,3\(at\) -+10000554: 8f81801c lw at,-32740\(gp\) ++10000554: 8f818018 lw at,-32744\(gp\) +10000558: 2421073c addiu at,at,1852 +1000055c: 00310821 addu at,at,s1 +10000560: 88250000 lwl a1,0\(at\) +10000564: 98250003 lwr a1,3\(at\) -+10000568: 8f81801c lw at,-32740\(gp\) ++10000568: 8f818018 lw at,-32744\(gp\) +1000056c: 24210752 addiu at,at,1874 +10000570: 00250821 addu at,at,a1 +10000574: 88250000 lwl a1,0\(at\) +10000578: 98250003 lwr a1,3\(at\) -+1000057c: 8f81801c lw at,-32740\(gp\) ++1000057c: 8f818018 lw at,-32744\(gp\) +10000580: 24210768 addiu at,at,1896 +10000584: 00250821 addu at,at,a1 +10000588: a8250000 swl a1,0\(at\) +1000058c: b8250003 swr a1,3\(at\) +10000590: 3c050000 lui a1,0x0 +10000594: 00bc2821 addu a1,a1,gp -+10000598: 8ca58030 lw a1,-32720\(a1\) -+1000059c: 8f858028 lw a1,-32728\(gp\) ++10000598: 8ca5802c lw a1,-32724\(a1\) ++1000059c: 8f858020 lw a1,-32736\(gp\) +100005a0: 24a50674 addiu a1,a1,1652 +100005a4: 3c190000 lui t9,0x0 +100005a8: 033cc821 addu t9,t9,gp -+100005ac: 8f398030 lw t9,-32720\(t9\) -+100005b0: 8f998028 lw t9,-32728\(gp\) ++100005ac: 8f39802c lw t9,-32724\(t9\) ++100005b0: 8f998020 lw t9,-32736\(gp\) +100005b4: 27390674 addiu t9,t9,1652 +100005b8: 3c190000 lui t9,0x0 +100005bc: 033cc821 addu t9,t9,gp -+100005c0: 8f398030 lw t9,-32720\(t9\) ++100005c0: 8f39802c lw t9,-32724\(t9\) +100005c4: 0411002b bal 10000674 +100005c8: 00000000 nop -+100005cc: 8f998028 lw t9,-32728\(gp\) ++100005cc: 8f998020 lw t9,-32736\(gp\) +100005d0: 27390674 addiu t9,t9,1652 +100005d4: 04110027 bal 10000674 +100005d8: 00000000 nop +100005dc: 3c050000 lui a1,0x0 +100005e0: 00bc2821 addu a1,a1,gp -+100005e4: 8ca58018 lw a1,-32744\(a1\) ++100005e4: 8ca58038 lw a1,-32712\(a1\) +100005e8: 1000fea2 b 10000074 +100005ec: 00000000 nop +100005f0: 3c050000 lui a1,0x0 +100005f4: 00bc2821 addu a1,a1,gp -+100005f8: 8ca5802c lw a1,-32724\(a1\) ++100005f8: 8ca58030 lw a1,-32720\(a1\) +100005fc: 8ca50000 lw a1,0\(a1\) +10000600: 1000001c b 10000674 +10000604: 00000000 nop -+10000608: 8f85801c lw a1,-32740\(gp\) ++10000608: 8f858018 lw a1,-32744\(gp\) +1000060c: 24a506b8 addiu a1,a1,1720 +10000610: 1000fe98 b 10000074 +10000614: 00000000 nop -+10000618: 8f85801c lw a1,-32740\(gp\) ++10000618: 8f858018 lw a1,-32744\(gp\) +1000061c: 24a5073c addiu a1,a1,1852 +10000620: 10000014 b 10000674 +10000624: 00000000 nop -+10000628: 8f858020 lw a1,-32736\(gp\) ++10000628: 8f85801c lw a1,-32740\(gp\) +1000062c: 24a5e8f8 addiu a1,a1,-5896 +10000630: 1000fe90 b 10000074 +10000634: 00000000 nop -+10000638: 8f85801c lw a1,-32740\(gp\) ++10000638: 8f858018 lw a1,-32744\(gp\) +1000063c: 8ca50730 lw a1,1840\(a1\) +10000640: 1000000c b 10000674 +10000644: 00000000 nop -+10000648: 8f85801c lw a1,-32740\(gp\) ++10000648: 8f858018 lw a1,-32744\(gp\) +1000064c: 8ca506c4 lw a1,1732\(a1\) +10000650: 1000fe88 b 10000074 +10000654: 00000000 nop -+10000658: 8f81801c lw at,-32740\(gp\) ++10000658: 8f818018 lw at,-32744\(gp\) +1000065c: 00250821 addu at,at,a1 +10000660: 8c250752 lw a1,1874\(at\) +10000664: 10000003 b 10000674 @@ -2818834,19 +2834285,19 @@ index 0000000..1d0c045 +10010770 <_GLOBAL_OFFSET_TABLE_>: +10010770: 00000000 .* +10010774: 80000000 .* -+10010778: 100106b8 .* -+1001077c: 10010000 .* -+10010780: 10030000 .* -+10010784: 10000074 .* -+10010788: 10000000 .* -+1001078c: 10010730 .* -+10010790: 10000674 .* -+10010794: 00000000 .* -+10010798: 00000000 .* ++10010778: 10010000 .* ++1001077c: 10030000 .* ++10010780: 10000000 .* ++10010784: 00000000 .* ++10010788: 00000000 .* ++1001078c: 10000674 .* ++10010790: 10010730 .* ++10010794: 10000074 .* ++10010798: 100106b8 .* +#pass diff --git a/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32.d b/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32.d new file mode 100644 -index 0000000..4e105aa +index 0000000..a909aa9 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32.d @@ -0,0 +1,434 @@ @@ -2818870,382 +2834321,382 @@ index 0000000..4e105aa +100000b0 : +100000b0: 3c050000 lui a1,0x0 +100000b4: 00bc2821 addu a1,a1,gp -+100000b8: 8ca58018 lw a1,-32744\(a1\) ++100000b8: 8ca58038 lw a1,-32712\(a1\) +100000bc: 3c050000 lui a1,0x0 +100000c0: 00bc2821 addu a1,a1,gp -+100000c4: 8ca58018 lw a1,-32744\(a1\) ++100000c4: 8ca58038 lw a1,-32712\(a1\) +100000c8: 24a5000c addiu a1,a1,12 +100000cc: 3c050000 lui a1,0x0 +100000d0: 00bc2821 addu a1,a1,gp -+100000d4: 8ca58018 lw a1,-32744\(a1\) ++100000d4: 8ca58038 lw a1,-32712\(a1\) +100000d8: 3c010001 lui at,0x1 +100000dc: 3421e240 ori at,at,0xe240 +100000e0: 00a12821 addu a1,a1,at +100000e4: 3c050000 lui a1,0x0 +100000e8: 00bc2821 addu a1,a1,gp -+100000ec: 8ca58018 lw a1,-32744\(a1\) ++100000ec: 8ca58038 lw a1,-32712\(a1\) +100000f0: 00b12821 addu a1,a1,s1 +100000f4: 3c050000 lui a1,0x0 +100000f8: 00bc2821 addu a1,a1,gp -+100000fc: 8ca58018 lw a1,-32744\(a1\) ++100000fc: 8ca58038 lw a1,-32712\(a1\) +10000100: 24a5000c addiu a1,a1,12 +10000104: 00b12821 addu a1,a1,s1 +10000108: 3c050000 lui a1,0x0 +1000010c: 00bc2821 addu a1,a1,gp -+10000110: 8ca58018 lw a1,-32744\(a1\) ++10000110: 8ca58038 lw a1,-32712\(a1\) +10000114: 3c010001 lui at,0x1 +10000118: 3421e240 ori at,at,0xe240 +1000011c: 00a12821 addu a1,a1,at +10000120: 00b12821 addu a1,a1,s1 +10000124: 3c050000 lui a1,0x0 +10000128: 00bc2821 addu a1,a1,gp -+1000012c: 8ca58018 lw a1,-32744\(a1\) ++1000012c: 8ca58038 lw a1,-32712\(a1\) +10000130: 8ca50000 lw a1,0\(a1\) +10000134: 3c050000 lui a1,0x0 +10000138: 00bc2821 addu a1,a1,gp -+1000013c: 8ca58018 lw a1,-32744\(a1\) ++1000013c: 8ca58038 lw a1,-32712\(a1\) +10000140: 8ca5000c lw a1,12\(a1\) +10000144: 3c050000 lui a1,0x0 +10000148: 00bc2821 addu a1,a1,gp -+1000014c: 8ca58018 lw a1,-32744\(a1\) ++1000014c: 8ca58038 lw a1,-32712\(a1\) +10000150: 00b12821 addu a1,a1,s1 +10000154: 8ca50000 lw a1,0\(a1\) +10000158: 3c050000 lui a1,0x0 +1000015c: 00bc2821 addu a1,a1,gp -+10000160: 8ca58018 lw a1,-32744\(a1\) ++10000160: 8ca58038 lw a1,-32712\(a1\) +10000164: 00b12821 addu a1,a1,s1 +10000168: 8ca5000c lw a1,12\(a1\) +1000016c: 3c010000 lui at,0x0 +10000170: 003c0821 addu at,at,gp -+10000174: 8c218018 lw at,-32744\(at\) ++10000174: 8c218038 lw at,-32712\(at\) +10000178: 00250821 addu at,at,a1 +1000017c: 8c250022 lw a1,34\(at\) +10000180: 3c010000 lui at,0x0 +10000184: 003c0821 addu at,at,gp -+10000188: 8c218018 lw at,-32744\(at\) ++10000188: 8c218038 lw at,-32712\(at\) +1000018c: 00250821 addu at,at,a1 +10000190: ac250038 sw a1,56\(at\) +10000194: 3c010000 lui at,0x0 +10000198: 003c0821 addu at,at,gp -+1000019c: 8c218018 lw at,-32744\(at\) ++1000019c: 8c218038 lw at,-32712\(at\) +100001a0: 88250000 lwl a1,0\(at\) +100001a4: 98250003 lwr a1,3\(at\) +100001a8: 3c010000 lui at,0x0 +100001ac: 003c0821 addu at,at,gp -+100001b0: 8c218018 lw at,-32744\(at\) ++100001b0: 8c218038 lw at,-32712\(at\) +100001b4: 2421000c addiu at,at,12 +100001b8: 88250000 lwl a1,0\(at\) +100001bc: 98250003 lwr a1,3\(at\) +100001c0: 3c010000 lui at,0x0 +100001c4: 003c0821 addu at,at,gp -+100001c8: 8c218018 lw at,-32744\(at\) ++100001c8: 8c218038 lw at,-32712\(at\) +100001cc: 00310821 addu at,at,s1 +100001d0: 88250000 lwl a1,0\(at\) +100001d4: 98250003 lwr a1,3\(at\) +100001d8: 3c010000 lui at,0x0 +100001dc: 003c0821 addu at,at,gp -+100001e0: 8c218018 lw at,-32744\(at\) ++100001e0: 8c218038 lw at,-32712\(at\) +100001e4: 2421000c addiu at,at,12 +100001e8: 00310821 addu at,at,s1 +100001ec: 88250000 lwl a1,0\(at\) +100001f0: 98250003 lwr a1,3\(at\) +100001f4: 3c010000 lui at,0x0 +100001f8: 003c0821 addu at,at,gp -+100001fc: 8c218018 lw at,-32744\(at\) ++100001fc: 8c218038 lw at,-32712\(at\) +10000200: 24210022 addiu at,at,34 +10000204: 00250821 addu at,at,a1 +10000208: 88250000 lwl a1,0\(at\) +1000020c: 98250003 lwr a1,3\(at\) +10000210: 3c010000 lui at,0x0 +10000214: 003c0821 addu at,at,gp -+10000218: 8c218018 lw at,-32744\(at\) ++10000218: 8c218038 lw at,-32712\(at\) +1000021c: 24210038 addiu at,at,56 +10000220: 00250821 addu at,at,a1 +10000224: a8250000 swl a1,0\(at\) +10000228: b8250003 swr a1,3\(at\) -+1000022c: 8f85801c lw a1,-32740\(gp\) ++1000022c: 8f858018 lw a1,-32744\(gp\) +10000230: 24a506fc addiu a1,a1,1788 -+10000234: 8f85801c lw a1,-32740\(gp\) ++10000234: 8f858018 lw a1,-32744\(gp\) +10000238: 24a50708 addiu a1,a1,1800 -+1000023c: 8f858020 lw a1,-32736\(gp\) ++1000023c: 8f85801c lw a1,-32740\(gp\) +10000240: 24a5e93c addiu a1,a1,-5828 -+10000244: 8f85801c lw a1,-32740\(gp\) ++10000244: 8f858018 lw a1,-32744\(gp\) +10000248: 24a506fc addiu a1,a1,1788 +1000024c: 00b12821 addu a1,a1,s1 -+10000250: 8f85801c lw a1,-32740\(gp\) ++10000250: 8f858018 lw a1,-32744\(gp\) +10000254: 24a50708 addiu a1,a1,1800 +10000258: 00b12821 addu a1,a1,s1 -+1000025c: 8f858020 lw a1,-32736\(gp\) ++1000025c: 8f85801c lw a1,-32740\(gp\) +10000260: 24a5e93c addiu a1,a1,-5828 +10000264: 00b12821 addu a1,a1,s1 -+10000268: 8f85801c lw a1,-32740\(gp\) ++10000268: 8f858018 lw a1,-32744\(gp\) +1000026c: 8ca506fc lw a1,1788\(a1\) -+10000270: 8f85801c lw a1,-32740\(gp\) ++10000270: 8f858018 lw a1,-32744\(gp\) +10000274: 8ca50708 lw a1,1800\(a1\) -+10000278: 8f85801c lw a1,-32740\(gp\) ++10000278: 8f858018 lw a1,-32744\(gp\) +1000027c: 00b12821 addu a1,a1,s1 +10000280: 8ca506fc lw a1,1788\(a1\) -+10000284: 8f85801c lw a1,-32740\(gp\) ++10000284: 8f858018 lw a1,-32744\(gp\) +10000288: 00b12821 addu a1,a1,s1 +1000028c: 8ca50708 lw a1,1800\(a1\) -+10000290: 8f81801c lw at,-32740\(gp\) ++10000290: 8f818018 lw at,-32744\(gp\) +10000294: 00250821 addu at,at,a1 +10000298: 8c25071e lw a1,1822\(at\) -+1000029c: 8f81801c lw at,-32740\(gp\) ++1000029c: 8f818018 lw at,-32744\(gp\) +100002a0: 00250821 addu at,at,a1 +100002a4: ac250734 sw a1,1844\(at\) -+100002a8: 8f81801c lw at,-32740\(gp\) ++100002a8: 8f818018 lw at,-32744\(gp\) +100002ac: 242106fc addiu at,at,1788 +100002b0: 88250000 lwl a1,0\(at\) +100002b4: 98250003 lwr a1,3\(at\) -+100002b8: 8f81801c lw at,-32740\(gp\) ++100002b8: 8f818018 lw at,-32744\(gp\) +100002bc: 24210708 addiu at,at,1800 +100002c0: 88250000 lwl a1,0\(at\) +100002c4: 98250003 lwr a1,3\(at\) -+100002c8: 8f81801c lw at,-32740\(gp\) ++100002c8: 8f818018 lw at,-32744\(gp\) +100002cc: 242106fc addiu at,at,1788 +100002d0: 00310821 addu at,at,s1 +100002d4: 88250000 lwl a1,0\(at\) +100002d8: 98250003 lwr a1,3\(at\) -+100002dc: 8f81801c lw at,-32740\(gp\) ++100002dc: 8f818018 lw at,-32744\(gp\) +100002e0: 24210708 addiu at,at,1800 +100002e4: 00310821 addu at,at,s1 +100002e8: 88250000 lwl a1,0\(at\) +100002ec: 98250003 lwr a1,3\(at\) -+100002f0: 8f81801c lw at,-32740\(gp\) ++100002f0: 8f818018 lw at,-32744\(gp\) +100002f4: 2421071e addiu at,at,1822 +100002f8: 00250821 addu at,at,a1 +100002fc: 88250000 lwl a1,0\(at\) +10000300: 98250003 lwr a1,3\(at\) -+10000304: 8f81801c lw at,-32740\(gp\) ++10000304: 8f818018 lw at,-32744\(gp\) +10000308: 24210734 addiu at,at,1844 +1000030c: 00250821 addu at,at,a1 +10000310: a8250000 swl a1,0\(at\) +10000314: b8250003 swr a1,3\(at\) +10000318: 3c050000 lui a1,0x0 +1000031c: 00bc2821 addu a1,a1,gp -+10000320: 8ca58024 lw a1,-32732\(a1\) -+10000324: 8f858028 lw a1,-32728\(gp\) ++10000320: 8ca58034 lw a1,-32716\(a1\) ++10000324: 8f858020 lw a1,-32736\(gp\) +10000328: 24a500b0 addiu a1,a1,176 +1000032c: 3c190000 lui t9,0x0 +10000330: 033cc821 addu t9,t9,gp -+10000334: 8f398024 lw t9,-32732\(t9\) -+10000338: 8f998028 lw t9,-32728\(gp\) ++10000334: 8f398034 lw t9,-32716\(t9\) ++10000338: 8f998020 lw t9,-32736\(gp\) +1000033c: 273900b0 addiu t9,t9,176 +10000340: 3c190000 lui t9,0x0 +10000344: 033cc821 addu t9,t9,gp -+10000348: 8f398024 lw t9,-32732\(t9\) ++10000348: 8f398034 lw t9,-32716\(t9\) +1000034c: 0411ff58 bal 100000b0 +10000350: 00000000 nop -+10000354: 8f998028 lw t9,-32728\(gp\) ++10000354: 8f998020 lw t9,-32736\(gp\) +10000358: 273900b0 addiu t9,t9,176 +1000035c: 0411ff54 bal 100000b0 +10000360: 00000000 nop +10000364: 3c050000 lui a1,0x0 +10000368: 00bc2821 addu a1,a1,gp -+1000036c: 8ca5802c lw a1,-32724\(a1\) ++1000036c: 8ca58030 lw a1,-32720\(a1\) +10000370: 3c050000 lui a1,0x0 +10000374: 00bc2821 addu a1,a1,gp -+10000378: 8ca5802c lw a1,-32724\(a1\) ++10000378: 8ca58030 lw a1,-32720\(a1\) +1000037c: 24a5000c addiu a1,a1,12 +10000380: 3c050000 lui a1,0x0 +10000384: 00bc2821 addu a1,a1,gp -+10000388: 8ca5802c lw a1,-32724\(a1\) ++10000388: 8ca58030 lw a1,-32720\(a1\) +1000038c: 3c010001 lui at,0x1 +10000390: 3421e240 ori at,at,0xe240 +10000394: 00a12821 addu a1,a1,at +10000398: 3c050000 lui a1,0x0 +1000039c: 00bc2821 addu a1,a1,gp -+100003a0: 8ca5802c lw a1,-32724\(a1\) ++100003a0: 8ca58030 lw a1,-32720\(a1\) +100003a4: 00b12821 addu a1,a1,s1 +100003a8: 3c050000 lui a1,0x0 +100003ac: 00bc2821 addu a1,a1,gp -+100003b0: 8ca5802c lw a1,-32724\(a1\) ++100003b0: 8ca58030 lw a1,-32720\(a1\) +100003b4: 24a5000c addiu a1,a1,12 +100003b8: 00b12821 addu a1,a1,s1 +100003bc: 3c050000 lui a1,0x0 +100003c0: 00bc2821 addu a1,a1,gp -+100003c4: 8ca5802c lw a1,-32724\(a1\) ++100003c4: 8ca58030 lw a1,-32720\(a1\) +100003c8: 3c010001 lui at,0x1 +100003cc: 3421e240 ori at,at,0xe240 +100003d0: 00a12821 addu a1,a1,at +100003d4: 00b12821 addu a1,a1,s1 +100003d8: 3c050000 lui a1,0x0 +100003dc: 00bc2821 addu a1,a1,gp -+100003e0: 8ca5802c lw a1,-32724\(a1\) ++100003e0: 8ca58030 lw a1,-32720\(a1\) +100003e4: 8ca50000 lw a1,0\(a1\) +100003e8: 3c050000 lui a1,0x0 +100003ec: 00bc2821 addu a1,a1,gp -+100003f0: 8ca5802c lw a1,-32724\(a1\) ++100003f0: 8ca58030 lw a1,-32720\(a1\) +100003f4: 8ca5000c lw a1,12\(a1\) +100003f8: 3c050000 lui a1,0x0 +100003fc: 00bc2821 addu a1,a1,gp -+10000400: 8ca5802c lw a1,-32724\(a1\) ++10000400: 8ca58030 lw a1,-32720\(a1\) +10000404: 00b12821 addu a1,a1,s1 +10000408: 8ca50000 lw a1,0\(a1\) +1000040c: 3c050000 lui a1,0x0 +10000410: 00bc2821 addu a1,a1,gp -+10000414: 8ca5802c lw a1,-32724\(a1\) ++10000414: 8ca58030 lw a1,-32720\(a1\) +10000418: 00b12821 addu a1,a1,s1 +1000041c: 8ca5000c lw a1,12\(a1\) +10000420: 3c010000 lui at,0x0 +10000424: 003c0821 addu at,at,gp -+10000428: 8c21802c lw at,-32724\(at\) ++10000428: 8c218030 lw at,-32720\(at\) +1000042c: 00250821 addu at,at,a1 +10000430: 8c250022 lw a1,34\(at\) +10000434: 3c010000 lui at,0x0 +10000438: 003c0821 addu at,at,gp -+1000043c: 8c21802c lw at,-32724\(at\) ++1000043c: 8c218030 lw at,-32720\(at\) +10000440: 00250821 addu at,at,a1 +10000444: ac250038 sw a1,56\(at\) +10000448: 3c010000 lui at,0x0 +1000044c: 003c0821 addu at,at,gp -+10000450: 8c21802c lw at,-32724\(at\) ++10000450: 8c218030 lw at,-32720\(at\) +10000454: 88250000 lwl a1,0\(at\) +10000458: 98250003 lwr a1,3\(at\) +1000045c: 3c010000 lui at,0x0 +10000460: 003c0821 addu at,at,gp -+10000464: 8c21802c lw at,-32724\(at\) ++10000464: 8c218030 lw at,-32720\(at\) +10000468: 2421000c addiu at,at,12 +1000046c: 88250000 lwl a1,0\(at\) +10000470: 98250003 lwr a1,3\(at\) +10000474: 3c010000 lui at,0x0 +10000478: 003c0821 addu at,at,gp -+1000047c: 8c21802c lw at,-32724\(at\) ++1000047c: 8c218030 lw at,-32720\(at\) +10000480: 00310821 addu at,at,s1 +10000484: 88250000 lwl a1,0\(at\) +10000488: 98250003 lwr a1,3\(at\) +1000048c: 3c010000 lui at,0x0 +10000490: 003c0821 addu at,at,gp -+10000494: 8c21802c lw at,-32724\(at\) ++10000494: 8c218030 lw at,-32720\(at\) +10000498: 2421000c addiu at,at,12 +1000049c: 00310821 addu at,at,s1 +100004a0: 88250000 lwl a1,0\(at\) +100004a4: 98250003 lwr a1,3\(at\) +100004a8: 3c010000 lui at,0x0 +100004ac: 003c0821 addu at,at,gp -+100004b0: 8c21802c lw at,-32724\(at\) ++100004b0: 8c218030 lw at,-32720\(at\) +100004b4: 24210022 addiu at,at,34 +100004b8: 00250821 addu at,at,a1 +100004bc: 88250000 lwl a1,0\(at\) +100004c0: 98250003 lwr a1,3\(at\) +100004c4: 3c010000 lui at,0x0 +100004c8: 003c0821 addu at,at,gp -+100004cc: 8c21802c lw at,-32724\(at\) ++100004cc: 8c218030 lw at,-32720\(at\) +100004d0: 24210038 addiu at,at,56 +100004d4: 00250821 addu at,at,a1 +100004d8: a8250000 swl a1,0\(at\) +100004dc: b8250003 swr a1,3\(at\) -+100004e0: 8f85801c lw a1,-32740\(gp\) ++100004e0: 8f858018 lw a1,-32744\(gp\) +100004e4: 24a50774 addiu a1,a1,1908 -+100004e8: 8f85801c lw a1,-32740\(gp\) ++100004e8: 8f858018 lw a1,-32744\(gp\) +100004ec: 24a50780 addiu a1,a1,1920 -+100004f0: 8f858020 lw a1,-32736\(gp\) ++100004f0: 8f85801c lw a1,-32740\(gp\) +100004f4: 24a5e9b4 addiu a1,a1,-5708 -+100004f8: 8f85801c lw a1,-32740\(gp\) ++100004f8: 8f858018 lw a1,-32744\(gp\) +100004fc: 24a50774 addiu a1,a1,1908 +10000500: 00b12821 addu a1,a1,s1 -+10000504: 8f85801c lw a1,-32740\(gp\) ++10000504: 8f858018 lw a1,-32744\(gp\) +10000508: 24a50780 addiu a1,a1,1920 +1000050c: 00b12821 addu a1,a1,s1 -+10000510: 8f858020 lw a1,-32736\(gp\) ++10000510: 8f85801c lw a1,-32740\(gp\) +10000514: 24a5e9b4 addiu a1,a1,-5708 +10000518: 00b12821 addu a1,a1,s1 -+1000051c: 8f85801c lw a1,-32740\(gp\) ++1000051c: 8f858018 lw a1,-32744\(gp\) +10000520: 8ca50774 lw a1,1908\(a1\) -+10000524: 8f85801c lw a1,-32740\(gp\) ++10000524: 8f858018 lw a1,-32744\(gp\) +10000528: 8ca50780 lw a1,1920\(a1\) -+1000052c: 8f85801c lw a1,-32740\(gp\) ++1000052c: 8f858018 lw a1,-32744\(gp\) +10000530: 00b12821 addu a1,a1,s1 +10000534: 8ca50774 lw a1,1908\(a1\) -+10000538: 8f85801c lw a1,-32740\(gp\) ++10000538: 8f858018 lw a1,-32744\(gp\) +1000053c: 00b12821 addu a1,a1,s1 +10000540: 8ca50780 lw a1,1920\(a1\) -+10000544: 8f81801c lw at,-32740\(gp\) ++10000544: 8f818018 lw at,-32744\(gp\) +10000548: 00250821 addu at,at,a1 +1000054c: 8c250796 lw a1,1942\(at\) -+10000550: 8f81801c lw at,-32740\(gp\) ++10000550: 8f818018 lw at,-32744\(gp\) +10000554: 00250821 addu at,at,a1 +10000558: ac2507ac sw a1,1964\(at\) -+1000055c: 8f81801c lw at,-32740\(gp\) ++1000055c: 8f818018 lw at,-32744\(gp\) +10000560: 24210774 addiu at,at,1908 +10000564: 88250000 lwl a1,0\(at\) +10000568: 98250003 lwr a1,3\(at\) -+1000056c: 8f81801c lw at,-32740\(gp\) ++1000056c: 8f818018 lw at,-32744\(gp\) +10000570: 24210780 addiu at,at,1920 +10000574: 88250000 lwl a1,0\(at\) +10000578: 98250003 lwr a1,3\(at\) -+1000057c: 8f81801c lw at,-32740\(gp\) ++1000057c: 8f818018 lw at,-32744\(gp\) +10000580: 24210774 addiu at,at,1908 +10000584: 00310821 addu at,at,s1 +10000588: 88250000 lwl a1,0\(at\) +1000058c: 98250003 lwr a1,3\(at\) -+10000590: 8f81801c lw at,-32740\(gp\) ++10000590: 8f818018 lw at,-32744\(gp\) +10000594: 24210780 addiu at,at,1920 +10000598: 00310821 addu at,at,s1 +1000059c: 88250000 lwl a1,0\(at\) +100005a0: 98250003 lwr a1,3\(at\) -+100005a4: 8f81801c lw at,-32740\(gp\) ++100005a4: 8f818018 lw at,-32744\(gp\) +100005a8: 24210796 addiu at,at,1942 +100005ac: 00250821 addu at,at,a1 +100005b0: 88250000 lwl a1,0\(at\) +100005b4: 98250003 lwr a1,3\(at\) -+100005b8: 8f81801c lw at,-32740\(gp\) ++100005b8: 8f818018 lw at,-32744\(gp\) +100005bc: 242107ac addiu at,at,1964 +100005c0: 00250821 addu at,at,a1 +100005c4: a8250000 swl a1,0\(at\) +100005c8: b8250003 swr a1,3\(at\) +100005cc: 3c050000 lui a1,0x0 +100005d0: 00bc2821 addu a1,a1,gp -+100005d4: 8ca58030 lw a1,-32720\(a1\) -+100005d8: 8f858028 lw a1,-32728\(gp\) ++100005d4: 8ca5802c lw a1,-32724\(a1\) ++100005d8: 8f858020 lw a1,-32736\(gp\) +100005dc: 24a506b0 addiu a1,a1,1712 +100005e0: 3c190000 lui t9,0x0 +100005e4: 033cc821 addu t9,t9,gp -+100005e8: 8f398030 lw t9,-32720\(t9\) -+100005ec: 8f998028 lw t9,-32728\(gp\) ++100005e8: 8f39802c lw t9,-32724\(t9\) ++100005ec: 8f998020 lw t9,-32736\(gp\) +100005f0: 273906b0 addiu t9,t9,1712 +100005f4: 3c190000 lui t9,0x0 +100005f8: 033cc821 addu t9,t9,gp -+100005fc: 8f398030 lw t9,-32720\(t9\) ++100005fc: 8f39802c lw t9,-32724\(t9\) +10000600: 0411002b bal 100006b0 +10000604: 00000000 nop -+10000608: 8f998028 lw t9,-32728\(gp\) ++10000608: 8f998020 lw t9,-32736\(gp\) +1000060c: 273906b0 addiu t9,t9,1712 +10000610: 04110027 bal 100006b0 +10000614: 00000000 nop +10000618: 3c050000 lui a1,0x0 +1000061c: 00bc2821 addu a1,a1,gp -+10000620: 8ca58018 lw a1,-32744\(a1\) ++10000620: 8ca58038 lw a1,-32712\(a1\) +10000624: 1000fea2 b 100000b0 +10000628: 00000000 nop +1000062c: 3c050000 lui a1,0x0 +10000630: 00bc2821 addu a1,a1,gp -+10000634: 8ca5802c lw a1,-32724\(a1\) ++10000634: 8ca58030 lw a1,-32720\(a1\) +10000638: 8ca50000 lw a1,0\(a1\) +1000063c: 1000001c b 100006b0 +10000640: 00000000 nop -+10000644: 8f85801c lw a1,-32740\(gp\) ++10000644: 8f858018 lw a1,-32744\(gp\) +10000648: 24a506fc addiu a1,a1,1788 +1000064c: 1000fe98 b 100000b0 +10000650: 00000000 nop -+10000654: 8f85801c lw a1,-32740\(gp\) ++10000654: 8f858018 lw a1,-32744\(gp\) +10000658: 24a50780 addiu a1,a1,1920 +1000065c: 10000014 b 100006b0 +10000660: 00000000 nop -+10000664: 8f858020 lw a1,-32736\(gp\) ++10000664: 8f85801c lw a1,-32740\(gp\) +10000668: 24a5e93c addiu a1,a1,-5828 +1000066c: 1000fe90 b 100000b0 +10000670: 00000000 nop -+10000674: 8f85801c lw a1,-32740\(gp\) ++10000674: 8f858018 lw a1,-32744\(gp\) +10000678: 8ca50774 lw a1,1908\(a1\) +1000067c: 1000000c b 100006b0 +10000680: 00000000 nop -+10000684: 8f85801c lw a1,-32740\(gp\) ++10000684: 8f858018 lw a1,-32744\(gp\) +10000688: 8ca50708 lw a1,1800\(a1\) +1000068c: 1000fe88 b 100000b0 +10000690: 00000000 nop -+10000694: 8f81801c lw at,-32740\(gp\) ++10000694: 8f818018 lw at,-32744\(gp\) +10000698: 00250821 addu at,at,a1 +1000069c: 8c250796 lw a1,1942\(at\) +100006a0: 10000003 b 100006b0 @@ -2819274,19 +2834725,19 @@ index 0000000..4e105aa +100107b0 <_GLOBAL_OFFSET_TABLE_>: +100107b0: 00000000 .* +100107b4: 80000000 .* -+100107b8: 100106fc .* -+100107bc: 10010000 .* -+100107c0: 10030000 .* -+100107c4: 100000b0 .* -+100107c8: 10000000 .* -+100107cc: 10010774 .* -+100107d0: 100006b0 .* -+100107d4: 00000000 .* -+100107d8: 00000000 .* ++100107b8: 10010000 .* ++100107bc: 10030000 .* ++100107c0: 10000000 .* ++100107c4: 00000000 .* ++100107c8: 00000000 .* ++100107cc: 100006b0 .* ++100107d0: 10010774 .* ++100107d4: 100000b0 .* ++100107d8: 100106fc .* +#pass diff --git a/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-embed.d b/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-embed.d new file mode 100644 -index 0000000..6da691c +index 0000000..271257f --- /dev/null +++ b/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-embed.d @@ -0,0 +1,444 @@ @@ -2819313,382 +2834764,382 @@ index 0000000..6da691c +00000001200000b0 : + 1200000b0: 3c050000 lui a1,0x0 + 1200000b4: 00bc282d daddu a1,a1,gp -+ 1200000b8: dca58020 ld a1,-32736\(a1\) ++ 1200000b8: dca58060 ld a1,-32672\(a1\) + 1200000bc: 3c050000 lui a1,0x0 + 1200000c0: 00bc282d daddu a1,a1,gp -+ 1200000c4: dca58020 ld a1,-32736\(a1\) ++ 1200000c4: dca58060 ld a1,-32672\(a1\) + 1200000c8: 64a5000c daddiu a1,a1,12 + 1200000cc: 3c050000 lui a1,0x0 + 1200000d0: 00bc282d daddu a1,a1,gp -+ 1200000d4: dca58020 ld a1,-32736\(a1\) ++ 1200000d4: dca58060 ld a1,-32672\(a1\) + 1200000d8: 3c010001 lui at,0x1 + 1200000dc: 3421e240 ori at,at,0xe240 + 1200000e0: 00a1282d daddu a1,a1,at + 1200000e4: 3c050000 lui a1,0x0 + 1200000e8: 00bc282d daddu a1,a1,gp -+ 1200000ec: dca58020 ld a1,-32736\(a1\) ++ 1200000ec: dca58060 ld a1,-32672\(a1\) + 1200000f0: 00b1282d daddu a1,a1,s1 + 1200000f4: 3c050000 lui a1,0x0 + 1200000f8: 00bc282d daddu a1,a1,gp -+ 1200000fc: dca58020 ld a1,-32736\(a1\) ++ 1200000fc: dca58060 ld a1,-32672\(a1\) + 120000100: 64a5000c daddiu a1,a1,12 + 120000104: 00b1282d daddu a1,a1,s1 + 120000108: 3c050000 lui a1,0x0 + 12000010c: 00bc282d daddu a1,a1,gp -+ 120000110: dca58020 ld a1,-32736\(a1\) ++ 120000110: dca58060 ld a1,-32672\(a1\) + 120000114: 3c010001 lui at,0x1 + 120000118: 3421e240 ori at,at,0xe240 + 12000011c: 00a1282d daddu a1,a1,at + 120000120: 00b1282d daddu a1,a1,s1 + 120000124: 3c050000 lui a1,0x0 + 120000128: 00bc282d daddu a1,a1,gp -+ 12000012c: dca58020 ld a1,-32736\(a1\) ++ 12000012c: dca58060 ld a1,-32672\(a1\) + 120000130: dca50000 ld a1,0\(a1\) + 120000134: 3c050000 lui a1,0x0 + 120000138: 00bc282d daddu a1,a1,gp -+ 12000013c: dca58020 ld a1,-32736\(a1\) ++ 12000013c: dca58060 ld a1,-32672\(a1\) + 120000140: dca5000c ld a1,12\(a1\) + 120000144: 3c050000 lui a1,0x0 + 120000148: 00bc282d daddu a1,a1,gp -+ 12000014c: dca58020 ld a1,-32736\(a1\) ++ 12000014c: dca58060 ld a1,-32672\(a1\) + 120000150: 00b1282d daddu a1,a1,s1 + 120000154: dca50000 ld a1,0\(a1\) + 120000158: 3c050000 lui a1,0x0 + 12000015c: 00bc282d daddu a1,a1,gp -+ 120000160: dca58020 ld a1,-32736\(a1\) ++ 120000160: dca58060 ld a1,-32672\(a1\) + 120000164: 00b1282d daddu a1,a1,s1 + 120000168: dca5000c ld a1,12\(a1\) + 12000016c: 3c010000 lui at,0x0 + 120000170: 003c082d daddu at,at,gp -+ 120000174: dc218020 ld at,-32736\(at\) ++ 120000174: dc218060 ld at,-32672\(at\) + 120000178: 0025082d daddu at,at,a1 + 12000017c: dc250022 ld a1,34\(at\) + 120000180: 3c010000 lui at,0x0 + 120000184: 003c082d daddu at,at,gp -+ 120000188: dc218020 ld at,-32736\(at\) ++ 120000188: dc218060 ld at,-32672\(at\) + 12000018c: 0025082d daddu at,at,a1 + 120000190: fc250038 sd a1,56\(at\) + 120000194: 3c010000 lui at,0x0 + 120000198: 003c082d daddu at,at,gp -+ 12000019c: dc218020 ld at,-32736\(at\) ++ 12000019c: dc218060 ld at,-32672\(at\) + 1200001a0: 88250000 lwl a1,0\(at\) + 1200001a4: 98250003 lwr a1,3\(at\) + 1200001a8: 3c010000 lui at,0x0 + 1200001ac: 003c082d daddu at,at,gp -+ 1200001b0: dc218020 ld at,-32736\(at\) ++ 1200001b0: dc218060 ld at,-32672\(at\) + 1200001b4: 6421000c daddiu at,at,12 + 1200001b8: 88250000 lwl a1,0\(at\) + 1200001bc: 98250003 lwr a1,3\(at\) + 1200001c0: 3c010000 lui at,0x0 + 1200001c4: 003c082d daddu at,at,gp -+ 1200001c8: dc218020 ld at,-32736\(at\) ++ 1200001c8: dc218060 ld at,-32672\(at\) + 1200001cc: 0031082d daddu at,at,s1 + 1200001d0: 88250000 lwl a1,0\(at\) + 1200001d4: 98250003 lwr a1,3\(at\) + 1200001d8: 3c010000 lui at,0x0 + 1200001dc: 003c082d daddu at,at,gp -+ 1200001e0: dc218020 ld at,-32736\(at\) ++ 1200001e0: dc218060 ld at,-32672\(at\) + 1200001e4: 6421000c daddiu at,at,12 + 1200001e8: 0031082d daddu at,at,s1 + 1200001ec: 88250000 lwl a1,0\(at\) + 1200001f0: 98250003 lwr a1,3\(at\) + 1200001f4: 3c010000 lui at,0x0 + 1200001f8: 003c082d daddu at,at,gp -+ 1200001fc: dc218020 ld at,-32736\(at\) ++ 1200001fc: dc218060 ld at,-32672\(at\) + 120000200: 64210022 daddiu at,at,34 + 120000204: 0025082d daddu at,at,a1 + 120000208: 88250000 lwl a1,0\(at\) + 12000020c: 98250003 lwr a1,3\(at\) + 120000210: 3c010000 lui at,0x0 + 120000214: 003c082d daddu at,at,gp -+ 120000218: dc218020 ld at,-32736\(at\) ++ 120000218: dc218060 ld at,-32672\(at\) + 12000021c: 64210038 daddiu at,at,56 + 120000220: 0025082d daddu at,at,a1 + 120000224: a8250000 swl a1,0\(at\) + 120000228: b8250003 swr a1,3\(at\) -+ 12000022c: df858028 ld a1,-32728\(gp\) ++ 12000022c: df858020 ld a1,-32736\(gp\) + 120000230: 64a506f4 daddiu a1,a1,1780 -+ 120000234: df858028 ld a1,-32728\(gp\) ++ 120000234: df858020 ld a1,-32736\(gp\) + 120000238: 64a50700 daddiu a1,a1,1792 -+ 12000023c: df858030 ld a1,-32720\(gp\) ++ 12000023c: df858028 ld a1,-32728\(gp\) + 120000240: 64a5e934 daddiu a1,a1,-5836 -+ 120000244: df858028 ld a1,-32728\(gp\) ++ 120000244: df858020 ld a1,-32736\(gp\) + 120000248: 64a506f4 daddiu a1,a1,1780 + 12000024c: 00b1282d daddu a1,a1,s1 -+ 120000250: df858028 ld a1,-32728\(gp\) ++ 120000250: df858020 ld a1,-32736\(gp\) + 120000254: 64a50700 daddiu a1,a1,1792 + 120000258: 00b1282d daddu a1,a1,s1 -+ 12000025c: df858030 ld a1,-32720\(gp\) ++ 12000025c: df858028 ld a1,-32728\(gp\) + 120000260: 64a5e934 daddiu a1,a1,-5836 + 120000264: 00b1282d daddu a1,a1,s1 -+ 120000268: df858028 ld a1,-32728\(gp\) ++ 120000268: df858020 ld a1,-32736\(gp\) + 12000026c: dca506f4 ld a1,1780\(a1\) -+ 120000270: df858028 ld a1,-32728\(gp\) ++ 120000270: df858020 ld a1,-32736\(gp\) + 120000274: dca50700 ld a1,1792\(a1\) -+ 120000278: df858028 ld a1,-32728\(gp\) ++ 120000278: df858020 ld a1,-32736\(gp\) + 12000027c: 00b1282d daddu a1,a1,s1 + 120000280: dca506f4 ld a1,1780\(a1\) -+ 120000284: df858028 ld a1,-32728\(gp\) ++ 120000284: df858020 ld a1,-32736\(gp\) + 120000288: 00b1282d daddu a1,a1,s1 + 12000028c: dca50700 ld a1,1792\(a1\) -+ 120000290: df818028 ld at,-32728\(gp\) ++ 120000290: df818020 ld at,-32736\(gp\) + 120000294: 0025082d daddu at,at,a1 + 120000298: dc250716 ld a1,1814\(at\) -+ 12000029c: df818028 ld at,-32728\(gp\) ++ 12000029c: df818020 ld at,-32736\(gp\) + 1200002a0: 0025082d daddu at,at,a1 + 1200002a4: fc25072c sd a1,1836\(at\) -+ 1200002a8: df818028 ld at,-32728\(gp\) ++ 1200002a8: df818020 ld at,-32736\(gp\) + 1200002ac: 642106f4 daddiu at,at,1780 + 1200002b0: 88250000 lwl a1,0\(at\) + 1200002b4: 98250003 lwr a1,3\(at\) -+ 1200002b8: df818028 ld at,-32728\(gp\) ++ 1200002b8: df818020 ld at,-32736\(gp\) + 1200002bc: 64210700 daddiu at,at,1792 + 1200002c0: 88250000 lwl a1,0\(at\) + 1200002c4: 98250003 lwr a1,3\(at\) -+ 1200002c8: df818028 ld at,-32728\(gp\) ++ 1200002c8: df818020 ld at,-32736\(gp\) + 1200002cc: 642106f4 daddiu at,at,1780 + 1200002d0: 0031082d daddu at,at,s1 + 1200002d4: 88250000 lwl a1,0\(at\) + 1200002d8: 98250003 lwr a1,3\(at\) -+ 1200002dc: df818028 ld at,-32728\(gp\) ++ 1200002dc: df818020 ld at,-32736\(gp\) + 1200002e0: 64210700 daddiu at,at,1792 + 1200002e4: 0031082d daddu at,at,s1 + 1200002e8: 88250000 lwl a1,0\(at\) + 1200002ec: 98250003 lwr a1,3\(at\) -+ 1200002f0: df818028 ld at,-32728\(gp\) ++ 1200002f0: df818020 ld at,-32736\(gp\) + 1200002f4: 64210716 daddiu at,at,1814 + 1200002f8: 0025082d daddu at,at,a1 + 1200002fc: 88250000 lwl a1,0\(at\) + 120000300: 98250003 lwr a1,3\(at\) -+ 120000304: df818028 ld at,-32728\(gp\) ++ 120000304: df818020 ld at,-32736\(gp\) + 120000308: 6421072c daddiu at,at,1836 + 12000030c: 0025082d daddu at,at,a1 + 120000310: a8250000 swl a1,0\(at\) + 120000314: b8250003 swr a1,3\(at\) + 120000318: 3c050000 lui a1,0x0 + 12000031c: 00bc282d daddu a1,a1,gp -+ 120000320: dca58038 ld a1,-32712\(a1\) -+ 120000324: df858040 ld a1,-32704\(gp\) ++ 120000320: dca58058 ld a1,-32680\(a1\) ++ 120000324: df858030 ld a1,-32720\(gp\) + 120000328: 64a500b0 daddiu a1,a1,176 + 12000032c: 3c190000 lui t9,0x0 + 120000330: 033cc82d daddu t9,t9,gp -+ 120000334: df398038 ld t9,-32712\(t9\) -+ 120000338: df998040 ld t9,-32704\(gp\) ++ 120000334: df398058 ld t9,-32680\(t9\) ++ 120000338: df998030 ld t9,-32720\(gp\) + 12000033c: 673900b0 daddiu t9,t9,176 + 120000340: 3c190000 lui t9,0x0 + 120000344: 033cc82d daddu t9,t9,gp -+ 120000348: df398038 ld t9,-32712\(t9\) ++ 120000348: df398058 ld t9,-32680\(t9\) + 12000034c: 0411ff58 bal 1200000b0 + 120000350: 00000000 nop -+ 120000354: df998040 ld t9,-32704\(gp\) ++ 120000354: df998030 ld t9,-32720\(gp\) + 120000358: 673900b0 daddiu t9,t9,176 + 12000035c: 0411ff54 bal 1200000b0 + 120000360: 00000000 nop + 120000364: 3c050000 lui a1,0x0 + 120000368: 00bc282d daddu a1,a1,gp -+ 12000036c: dca58048 ld a1,-32696\(a1\) ++ 12000036c: dca58050 ld a1,-32688\(a1\) + 120000370: 3c050000 lui a1,0x0 + 120000374: 00bc282d daddu a1,a1,gp -+ 120000378: dca58048 ld a1,-32696\(a1\) ++ 120000378: dca58050 ld a1,-32688\(a1\) + 12000037c: 64a5000c daddiu a1,a1,12 + 120000380: 3c050000 lui a1,0x0 + 120000384: 00bc282d daddu a1,a1,gp -+ 120000388: dca58048 ld a1,-32696\(a1\) ++ 120000388: dca58050 ld a1,-32688\(a1\) + 12000038c: 3c010001 lui at,0x1 + 120000390: 3421e240 ori at,at,0xe240 + 120000394: 00a1282d daddu a1,a1,at + 120000398: 3c050000 lui a1,0x0 + 12000039c: 00bc282d daddu a1,a1,gp -+ 1200003a0: dca58048 ld a1,-32696\(a1\) ++ 1200003a0: dca58050 ld a1,-32688\(a1\) + 1200003a4: 00b1282d daddu a1,a1,s1 + 1200003a8: 3c050000 lui a1,0x0 + 1200003ac: 00bc282d daddu a1,a1,gp -+ 1200003b0: dca58048 ld a1,-32696\(a1\) ++ 1200003b0: dca58050 ld a1,-32688\(a1\) + 1200003b4: 64a5000c daddiu a1,a1,12 + 1200003b8: 00b1282d daddu a1,a1,s1 + 1200003bc: 3c050000 lui a1,0x0 + 1200003c0: 00bc282d daddu a1,a1,gp -+ 1200003c4: dca58048 ld a1,-32696\(a1\) ++ 1200003c4: dca58050 ld a1,-32688\(a1\) + 1200003c8: 3c010001 lui at,0x1 + 1200003cc: 3421e240 ori at,at,0xe240 + 1200003d0: 00a1282d daddu a1,a1,at + 1200003d4: 00b1282d daddu a1,a1,s1 + 1200003d8: 3c050000 lui a1,0x0 + 1200003dc: 00bc282d daddu a1,a1,gp -+ 1200003e0: dca58048 ld a1,-32696\(a1\) ++ 1200003e0: dca58050 ld a1,-32688\(a1\) + 1200003e4: dca50000 ld a1,0\(a1\) + 1200003e8: 3c050000 lui a1,0x0 + 1200003ec: 00bc282d daddu a1,a1,gp -+ 1200003f0: dca58048 ld a1,-32696\(a1\) ++ 1200003f0: dca58050 ld a1,-32688\(a1\) + 1200003f4: dca5000c ld a1,12\(a1\) + 1200003f8: 3c050000 lui a1,0x0 + 1200003fc: 00bc282d daddu a1,a1,gp -+ 120000400: dca58048 ld a1,-32696\(a1\) ++ 120000400: dca58050 ld a1,-32688\(a1\) + 120000404: 00b1282d daddu a1,a1,s1 + 120000408: dca50000 ld a1,0\(a1\) + 12000040c: 3c050000 lui a1,0x0 + 120000410: 00bc282d daddu a1,a1,gp -+ 120000414: dca58048 ld a1,-32696\(a1\) ++ 120000414: dca58050 ld a1,-32688\(a1\) + 120000418: 00b1282d daddu a1,a1,s1 + 12000041c: dca5000c ld a1,12\(a1\) + 120000420: 3c010000 lui at,0x0 + 120000424: 003c082d daddu at,at,gp -+ 120000428: dc218048 ld at,-32696\(at\) ++ 120000428: dc218050 ld at,-32688\(at\) + 12000042c: 0025082d daddu at,at,a1 + 120000430: dc250022 ld a1,34\(at\) + 120000434: 3c010000 lui at,0x0 + 120000438: 003c082d daddu at,at,gp -+ 12000043c: dc218048 ld at,-32696\(at\) ++ 12000043c: dc218050 ld at,-32688\(at\) + 120000440: 0025082d daddu at,at,a1 + 120000444: fc250038 sd a1,56\(at\) + 120000448: 3c010000 lui at,0x0 + 12000044c: 003c082d daddu at,at,gp -+ 120000450: dc218048 ld at,-32696\(at\) ++ 120000450: dc218050 ld at,-32688\(at\) + 120000454: 88250000 lwl a1,0\(at\) + 120000458: 98250003 lwr a1,3\(at\) + 12000045c: 3c010000 lui at,0x0 + 120000460: 003c082d daddu at,at,gp -+ 120000464: dc218048 ld at,-32696\(at\) ++ 120000464: dc218050 ld at,-32688\(at\) + 120000468: 6421000c daddiu at,at,12 + 12000046c: 88250000 lwl a1,0\(at\) + 120000470: 98250003 lwr a1,3\(at\) + 120000474: 3c010000 lui at,0x0 + 120000478: 003c082d daddu at,at,gp -+ 12000047c: dc218048 ld at,-32696\(at\) ++ 12000047c: dc218050 ld at,-32688\(at\) + 120000480: 0031082d daddu at,at,s1 + 120000484: 88250000 lwl a1,0\(at\) + 120000488: 98250003 lwr a1,3\(at\) + 12000048c: 3c010000 lui at,0x0 + 120000490: 003c082d daddu at,at,gp -+ 120000494: dc218048 ld at,-32696\(at\) ++ 120000494: dc218050 ld at,-32688\(at\) + 120000498: 6421000c daddiu at,at,12 + 12000049c: 0031082d daddu at,at,s1 + 1200004a0: 88250000 lwl a1,0\(at\) + 1200004a4: 98250003 lwr a1,3\(at\) + 1200004a8: 3c010000 lui at,0x0 + 1200004ac: 003c082d daddu at,at,gp -+ 1200004b0: dc218048 ld at,-32696\(at\) ++ 1200004b0: dc218050 ld at,-32688\(at\) + 1200004b4: 64210022 daddiu at,at,34 + 1200004b8: 0025082d daddu at,at,a1 + 1200004bc: 88250000 lwl a1,0\(at\) + 1200004c0: 98250003 lwr a1,3\(at\) + 1200004c4: 3c010000 lui at,0x0 + 1200004c8: 003c082d daddu at,at,gp -+ 1200004cc: dc218048 ld at,-32696\(at\) ++ 1200004cc: dc218050 ld at,-32688\(at\) + 1200004d0: 64210038 daddiu at,at,56 + 1200004d4: 0025082d daddu at,at,a1 + 1200004d8: a8250000 swl a1,0\(at\) + 1200004dc: b8250003 swr a1,3\(at\) -+ 1200004e0: df858028 ld a1,-32728\(gp\) ++ 1200004e0: df858020 ld a1,-32736\(gp\) + 1200004e4: 64a5076c daddiu a1,a1,1900 -+ 1200004e8: df858028 ld a1,-32728\(gp\) ++ 1200004e8: df858020 ld a1,-32736\(gp\) + 1200004ec: 64a50778 daddiu a1,a1,1912 -+ 1200004f0: df858030 ld a1,-32720\(gp\) ++ 1200004f0: df858028 ld a1,-32728\(gp\) + 1200004f4: 64a5e9ac daddiu a1,a1,-5716 -+ 1200004f8: df858028 ld a1,-32728\(gp\) ++ 1200004f8: df858020 ld a1,-32736\(gp\) + 1200004fc: 64a5076c daddiu a1,a1,1900 + 120000500: 00b1282d daddu a1,a1,s1 -+ 120000504: df858028 ld a1,-32728\(gp\) ++ 120000504: df858020 ld a1,-32736\(gp\) + 120000508: 64a50778 daddiu a1,a1,1912 + 12000050c: 00b1282d daddu a1,a1,s1 -+ 120000510: df858030 ld a1,-32720\(gp\) ++ 120000510: df858028 ld a1,-32728\(gp\) + 120000514: 64a5e9ac daddiu a1,a1,-5716 + 120000518: 00b1282d daddu a1,a1,s1 -+ 12000051c: df858028 ld a1,-32728\(gp\) ++ 12000051c: df858020 ld a1,-32736\(gp\) + 120000520: dca5076c ld a1,1900\(a1\) -+ 120000524: df858028 ld a1,-32728\(gp\) ++ 120000524: df858020 ld a1,-32736\(gp\) + 120000528: dca50778 ld a1,1912\(a1\) -+ 12000052c: df858028 ld a1,-32728\(gp\) ++ 12000052c: df858020 ld a1,-32736\(gp\) + 120000530: 00b1282d daddu a1,a1,s1 + 120000534: dca5076c ld a1,1900\(a1\) -+ 120000538: df858028 ld a1,-32728\(gp\) ++ 120000538: df858020 ld a1,-32736\(gp\) + 12000053c: 00b1282d daddu a1,a1,s1 + 120000540: dca50778 ld a1,1912\(a1\) -+ 120000544: df818028 ld at,-32728\(gp\) ++ 120000544: df818020 ld at,-32736\(gp\) + 120000548: 0025082d daddu at,at,a1 + 12000054c: dc25078e ld a1,1934\(at\) -+ 120000550: df818028 ld at,-32728\(gp\) ++ 120000550: df818020 ld at,-32736\(gp\) + 120000554: 0025082d daddu at,at,a1 + 120000558: fc2507a4 sd a1,1956\(at\) -+ 12000055c: df818028 ld at,-32728\(gp\) ++ 12000055c: df818020 ld at,-32736\(gp\) + 120000560: 6421076c daddiu at,at,1900 + 120000564: 88250000 lwl a1,0\(at\) + 120000568: 98250003 lwr a1,3\(at\) -+ 12000056c: df818028 ld at,-32728\(gp\) ++ 12000056c: df818020 ld at,-32736\(gp\) + 120000570: 64210778 daddiu at,at,1912 + 120000574: 88250000 lwl a1,0\(at\) + 120000578: 98250003 lwr a1,3\(at\) -+ 12000057c: df818028 ld at,-32728\(gp\) ++ 12000057c: df818020 ld at,-32736\(gp\) + 120000580: 6421076c daddiu at,at,1900 + 120000584: 0031082d daddu at,at,s1 + 120000588: 88250000 lwl a1,0\(at\) + 12000058c: 98250003 lwr a1,3\(at\) -+ 120000590: df818028 ld at,-32728\(gp\) ++ 120000590: df818020 ld at,-32736\(gp\) + 120000594: 64210778 daddiu at,at,1912 + 120000598: 0031082d daddu at,at,s1 + 12000059c: 88250000 lwl a1,0\(at\) + 1200005a0: 98250003 lwr a1,3\(at\) -+ 1200005a4: df818028 ld at,-32728\(gp\) ++ 1200005a4: df818020 ld at,-32736\(gp\) + 1200005a8: 6421078e daddiu at,at,1934 + 1200005ac: 0025082d daddu at,at,a1 + 1200005b0: 88250000 lwl a1,0\(at\) + 1200005b4: 98250003 lwr a1,3\(at\) -+ 1200005b8: df818028 ld at,-32728\(gp\) ++ 1200005b8: df818020 ld at,-32736\(gp\) + 1200005bc: 642107a4 daddiu at,at,1956 + 1200005c0: 0025082d daddu at,at,a1 + 1200005c4: a8250000 swl a1,0\(at\) + 1200005c8: b8250003 swr a1,3\(at\) + 1200005cc: 3c050000 lui a1,0x0 + 1200005d0: 00bc282d daddu a1,a1,gp -+ 1200005d4: dca58050 ld a1,-32688\(a1\) -+ 1200005d8: df858040 ld a1,-32704\(gp\) ++ 1200005d4: dca58048 ld a1,-32696\(a1\) ++ 1200005d8: df858030 ld a1,-32720\(gp\) + 1200005dc: 64a506b0 daddiu a1,a1,1712 + 1200005e0: 3c190000 lui t9,0x0 + 1200005e4: 033cc82d daddu t9,t9,gp -+ 1200005e8: df398050 ld t9,-32688\(t9\) -+ 1200005ec: df998040 ld t9,-32704\(gp\) ++ 1200005e8: df398048 ld t9,-32696\(t9\) ++ 1200005ec: df998030 ld t9,-32720\(gp\) + 1200005f0: 673906b0 daddiu t9,t9,1712 + 1200005f4: 3c190000 lui t9,0x0 + 1200005f8: 033cc82d daddu t9,t9,gp -+ 1200005fc: df398050 ld t9,-32688\(t9\) ++ 1200005fc: df398048 ld t9,-32696\(t9\) + 120000600: 0411002b bal 1200006b0 + 120000604: 00000000 nop -+ 120000608: df998040 ld t9,-32704\(gp\) ++ 120000608: df998030 ld t9,-32720\(gp\) + 12000060c: 673906b0 daddiu t9,t9,1712 + 120000610: 04110027 bal 1200006b0 + 120000614: 00000000 nop + 120000618: 3c050000 lui a1,0x0 + 12000061c: 00bc282d daddu a1,a1,gp -+ 120000620: dca58020 ld a1,-32736\(a1\) ++ 120000620: dca58060 ld a1,-32672\(a1\) + 120000624: 1000fea2 b 1200000b0 + 120000628: 00000000 nop + 12000062c: 3c050000 lui a1,0x0 + 120000630: 00bc282d daddu a1,a1,gp -+ 120000634: dca58048 ld a1,-32696\(a1\) ++ 120000634: dca58050 ld a1,-32688\(a1\) + 120000638: dca50000 ld a1,0\(a1\) + 12000063c: 1000001c b 1200006b0 + 120000640: 00000000 nop -+ 120000644: df858028 ld a1,-32728\(gp\) ++ 120000644: df858020 ld a1,-32736\(gp\) + 120000648: 64a506f4 daddiu a1,a1,1780 + 12000064c: 1000fe98 b 1200000b0 + 120000650: 00000000 nop -+ 120000654: df858028 ld a1,-32728\(gp\) ++ 120000654: df858020 ld a1,-32736\(gp\) + 120000658: 64a50778 daddiu a1,a1,1912 + 12000065c: 10000014 b 1200006b0 + 120000660: 00000000 nop -+ 120000664: df858030 ld a1,-32720\(gp\) ++ 120000664: df858028 ld a1,-32728\(gp\) + 120000668: 64a5e934 daddiu a1,a1,-5836 + 12000066c: 1000fe90 b 1200000b0 + 120000670: 00000000 nop -+ 120000674: df858028 ld a1,-32728\(gp\) ++ 120000674: df858020 ld a1,-32736\(gp\) + 120000678: dca5076c ld a1,1900\(a1\) + 12000067c: 1000000c b 1200006b0 + 120000680: 00000000 nop -+ 120000684: df858028 ld a1,-32728\(gp\) ++ 120000684: df858020 ld a1,-32736\(gp\) + 120000688: dca50700 ld a1,1792\(a1\) + 12000068c: 1000fe88 b 1200000b0 + 120000690: 00000000 nop -+ 120000694: df818028 ld at,-32728\(gp\) ++ 120000694: df818020 ld at,-32736\(gp\) + 120000698: 0025082d daddu at,at,a1 + 12000069c: dc25078e ld a1,1934\(at\) + 1200006a0: 10000003 b 1200006b0 @@ -2819719,24 +2835170,24 @@ index 0000000..6da691c + 1200107b8: 80000000 .* + 1200107bc: 00000000 .* + 1200107c0: 00000001 .* -+ 1200107c4: 200106f4 .* ++ 1200107c4: 20010000 .* + 1200107c8: 00000001 .* -+ 1200107cc: 20010000 .* ++ 1200107cc: 20030000 .* + 1200107d0: 00000001 .* -+ 1200107d4: 20030000 .* -+ 1200107d8: 00000001 .* -+ 1200107dc: 200000b0 .* -+ 1200107e0: 00000001 .* -+ 1200107e4: 20000000 .* -+ 1200107e8: 00000001 .* -+ 1200107ec: 2001076c .* -+ 1200107f0: 00000001 .* -+ 1200107f4: 200006b0 .* ++ 1200107d4: 20000000 .* + \.\.\. ++ 1200107e8: 00000001 .* ++ 1200107ec: 200006b0 .* ++ 1200107f0: 00000001 .* ++ 1200107f4: 2001076c .* ++ 1200107f8: 00000001 .* ++ 1200107fc: 200000b0 .* ++ 120010800: 00000001 .* ++ 120010804: 200106f4 .* +#pass diff --git a/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-linux.d b/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-linux.d new file mode 100644 -index 0000000..be446f0 +index 0000000..4579700 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-linux.d @@ -0,0 +1,444 @@ @@ -2819763,382 +2835214,382 @@ index 0000000..be446f0 +00000001200000e0 : + 1200000e0: 3c050000 lui a1,0x0 + 1200000e4: 00bc282d daddu a1,a1,gp -+ 1200000e8: dca58020 ld a1,-32736\(a1\) ++ 1200000e8: dca58060 ld a1,-32672\(a1\) + 1200000ec: 3c050000 lui a1,0x0 + 1200000f0: 00bc282d daddu a1,a1,gp -+ 1200000f4: dca58020 ld a1,-32736\(a1\) ++ 1200000f4: dca58060 ld a1,-32672\(a1\) + 1200000f8: 64a5000c daddiu a1,a1,12 + 1200000fc: 3c050000 lui a1,0x0 + 120000100: 00bc282d daddu a1,a1,gp -+ 120000104: dca58020 ld a1,-32736\(a1\) ++ 120000104: dca58060 ld a1,-32672\(a1\) + 120000108: 3c010001 lui at,0x1 + 12000010c: 3421e240 ori at,at,0xe240 + 120000110: 00a1282d daddu a1,a1,at + 120000114: 3c050000 lui a1,0x0 + 120000118: 00bc282d daddu a1,a1,gp -+ 12000011c: dca58020 ld a1,-32736\(a1\) ++ 12000011c: dca58060 ld a1,-32672\(a1\) + 120000120: 00b1282d daddu a1,a1,s1 + 120000124: 3c050000 lui a1,0x0 + 120000128: 00bc282d daddu a1,a1,gp -+ 12000012c: dca58020 ld a1,-32736\(a1\) ++ 12000012c: dca58060 ld a1,-32672\(a1\) + 120000130: 64a5000c daddiu a1,a1,12 + 120000134: 00b1282d daddu a1,a1,s1 + 120000138: 3c050000 lui a1,0x0 + 12000013c: 00bc282d daddu a1,a1,gp -+ 120000140: dca58020 ld a1,-32736\(a1\) ++ 120000140: dca58060 ld a1,-32672\(a1\) + 120000144: 3c010001 lui at,0x1 + 120000148: 3421e240 ori at,at,0xe240 + 12000014c: 00a1282d daddu a1,a1,at + 120000150: 00b1282d daddu a1,a1,s1 + 120000154: 3c050000 lui a1,0x0 + 120000158: 00bc282d daddu a1,a1,gp -+ 12000015c: dca58020 ld a1,-32736\(a1\) ++ 12000015c: dca58060 ld a1,-32672\(a1\) + 120000160: dca50000 ld a1,0\(a1\) + 120000164: 3c050000 lui a1,0x0 + 120000168: 00bc282d daddu a1,a1,gp -+ 12000016c: dca58020 ld a1,-32736\(a1\) ++ 12000016c: dca58060 ld a1,-32672\(a1\) + 120000170: dca5000c ld a1,12\(a1\) + 120000174: 3c050000 lui a1,0x0 + 120000178: 00bc282d daddu a1,a1,gp -+ 12000017c: dca58020 ld a1,-32736\(a1\) ++ 12000017c: dca58060 ld a1,-32672\(a1\) + 120000180: 00b1282d daddu a1,a1,s1 + 120000184: dca50000 ld a1,0\(a1\) + 120000188: 3c050000 lui a1,0x0 + 12000018c: 00bc282d daddu a1,a1,gp -+ 120000190: dca58020 ld a1,-32736\(a1\) ++ 120000190: dca58060 ld a1,-32672\(a1\) + 120000194: 00b1282d daddu a1,a1,s1 + 120000198: dca5000c ld a1,12\(a1\) + 12000019c: 3c010000 lui at,0x0 + 1200001a0: 003c082d daddu at,at,gp -+ 1200001a4: dc218020 ld at,-32736\(at\) ++ 1200001a4: dc218060 ld at,-32672\(at\) + 1200001a8: 0025082d daddu at,at,a1 + 1200001ac: dc250022 ld a1,34\(at\) + 1200001b0: 3c010000 lui at,0x0 + 1200001b4: 003c082d daddu at,at,gp -+ 1200001b8: dc218020 ld at,-32736\(at\) ++ 1200001b8: dc218060 ld at,-32672\(at\) + 1200001bc: 0025082d daddu at,at,a1 + 1200001c0: fc250038 sd a1,56\(at\) + 1200001c4: 3c010000 lui at,0x0 + 1200001c8: 003c082d daddu at,at,gp -+ 1200001cc: dc218020 ld at,-32736\(at\) ++ 1200001cc: dc218060 ld at,-32672\(at\) + 1200001d0: 88250000 lwl a1,0\(at\) + 1200001d4: 98250003 lwr a1,3\(at\) + 1200001d8: 3c010000 lui at,0x0 + 1200001dc: 003c082d daddu at,at,gp -+ 1200001e0: dc218020 ld at,-32736\(at\) ++ 1200001e0: dc218060 ld at,-32672\(at\) + 1200001e4: 6421000c daddiu at,at,12 + 1200001e8: 88250000 lwl a1,0\(at\) + 1200001ec: 98250003 lwr a1,3\(at\) + 1200001f0: 3c010000 lui at,0x0 + 1200001f4: 003c082d daddu at,at,gp -+ 1200001f8: dc218020 ld at,-32736\(at\) ++ 1200001f8: dc218060 ld at,-32672\(at\) + 1200001fc: 0031082d daddu at,at,s1 + 120000200: 88250000 lwl a1,0\(at\) + 120000204: 98250003 lwr a1,3\(at\) + 120000208: 3c010000 lui at,0x0 + 12000020c: 003c082d daddu at,at,gp -+ 120000210: dc218020 ld at,-32736\(at\) ++ 120000210: dc218060 ld at,-32672\(at\) + 120000214: 6421000c daddiu at,at,12 + 120000218: 0031082d daddu at,at,s1 + 12000021c: 88250000 lwl a1,0\(at\) + 120000220: 98250003 lwr a1,3\(at\) + 120000224: 3c010000 lui at,0x0 + 120000228: 003c082d daddu at,at,gp -+ 12000022c: dc218020 ld at,-32736\(at\) ++ 12000022c: dc218060 ld at,-32672\(at\) + 120000230: 64210022 daddiu at,at,34 + 120000234: 0025082d daddu at,at,a1 + 120000238: 88250000 lwl a1,0\(at\) + 12000023c: 98250003 lwr a1,3\(at\) + 120000240: 3c010000 lui at,0x0 + 120000244: 003c082d daddu at,at,gp -+ 120000248: dc218020 ld at,-32736\(at\) ++ 120000248: dc218060 ld at,-32672\(at\) + 12000024c: 64210038 daddiu at,at,56 + 120000250: 0025082d daddu at,at,a1 + 120000254: a8250000 swl a1,0\(at\) + 120000258: b8250003 swr a1,3\(at\) -+ 12000025c: df858028 ld a1,-32728\(gp\) ++ 12000025c: df858020 ld a1,-32736\(gp\) + 120000260: 64a5072c daddiu a1,a1,1836 -+ 120000264: df858028 ld a1,-32728\(gp\) ++ 120000264: df858020 ld a1,-32736\(gp\) + 120000268: 64a50738 daddiu a1,a1,1848 -+ 12000026c: df858030 ld a1,-32720\(gp\) ++ 12000026c: df858028 ld a1,-32728\(gp\) + 120000270: 64a5e96c daddiu a1,a1,-5780 -+ 120000274: df858028 ld a1,-32728\(gp\) ++ 120000274: df858020 ld a1,-32736\(gp\) + 120000278: 64a5072c daddiu a1,a1,1836 + 12000027c: 00b1282d daddu a1,a1,s1 -+ 120000280: df858028 ld a1,-32728\(gp\) ++ 120000280: df858020 ld a1,-32736\(gp\) + 120000284: 64a50738 daddiu a1,a1,1848 + 120000288: 00b1282d daddu a1,a1,s1 -+ 12000028c: df858030 ld a1,-32720\(gp\) ++ 12000028c: df858028 ld a1,-32728\(gp\) + 120000290: 64a5e96c daddiu a1,a1,-5780 + 120000294: 00b1282d daddu a1,a1,s1 -+ 120000298: df858028 ld a1,-32728\(gp\) ++ 120000298: df858020 ld a1,-32736\(gp\) + 12000029c: dca5072c ld a1,1836\(a1\) -+ 1200002a0: df858028 ld a1,-32728\(gp\) ++ 1200002a0: df858020 ld a1,-32736\(gp\) + 1200002a4: dca50738 ld a1,1848\(a1\) -+ 1200002a8: df858028 ld a1,-32728\(gp\) ++ 1200002a8: df858020 ld a1,-32736\(gp\) + 1200002ac: 00b1282d daddu a1,a1,s1 + 1200002b0: dca5072c ld a1,1836\(a1\) -+ 1200002b4: df858028 ld a1,-32728\(gp\) ++ 1200002b4: df858020 ld a1,-32736\(gp\) + 1200002b8: 00b1282d daddu a1,a1,s1 + 1200002bc: dca50738 ld a1,1848\(a1\) -+ 1200002c0: df818028 ld at,-32728\(gp\) ++ 1200002c0: df818020 ld at,-32736\(gp\) + 1200002c4: 0025082d daddu at,at,a1 + 1200002c8: dc25074e ld a1,1870\(at\) -+ 1200002cc: df818028 ld at,-32728\(gp\) ++ 1200002cc: df818020 ld at,-32736\(gp\) + 1200002d0: 0025082d daddu at,at,a1 + 1200002d4: fc250764 sd a1,1892\(at\) -+ 1200002d8: df818028 ld at,-32728\(gp\) ++ 1200002d8: df818020 ld at,-32736\(gp\) + 1200002dc: 6421072c daddiu at,at,1836 + 1200002e0: 88250000 lwl a1,0\(at\) + 1200002e4: 98250003 lwr a1,3\(at\) -+ 1200002e8: df818028 ld at,-32728\(gp\) ++ 1200002e8: df818020 ld at,-32736\(gp\) + 1200002ec: 64210738 daddiu at,at,1848 + 1200002f0: 88250000 lwl a1,0\(at\) + 1200002f4: 98250003 lwr a1,3\(at\) -+ 1200002f8: df818028 ld at,-32728\(gp\) ++ 1200002f8: df818020 ld at,-32736\(gp\) + 1200002fc: 6421072c daddiu at,at,1836 + 120000300: 0031082d daddu at,at,s1 + 120000304: 88250000 lwl a1,0\(at\) + 120000308: 98250003 lwr a1,3\(at\) -+ 12000030c: df818028 ld at,-32728\(gp\) ++ 12000030c: df818020 ld at,-32736\(gp\) + 120000310: 64210738 daddiu at,at,1848 + 120000314: 0031082d daddu at,at,s1 + 120000318: 88250000 lwl a1,0\(at\) + 12000031c: 98250003 lwr a1,3\(at\) -+ 120000320: df818028 ld at,-32728\(gp\) ++ 120000320: df818020 ld at,-32736\(gp\) + 120000324: 6421074e daddiu at,at,1870 + 120000328: 0025082d daddu at,at,a1 + 12000032c: 88250000 lwl a1,0\(at\) + 120000330: 98250003 lwr a1,3\(at\) -+ 120000334: df818028 ld at,-32728\(gp\) ++ 120000334: df818020 ld at,-32736\(gp\) + 120000338: 64210764 daddiu at,at,1892 + 12000033c: 0025082d daddu at,at,a1 + 120000340: a8250000 swl a1,0\(at\) + 120000344: b8250003 swr a1,3\(at\) + 120000348: 3c050000 lui a1,0x0 + 12000034c: 00bc282d daddu a1,a1,gp -+ 120000350: dca58038 ld a1,-32712\(a1\) -+ 120000354: df858040 ld a1,-32704\(gp\) ++ 120000350: dca58058 ld a1,-32680\(a1\) ++ 120000354: df858030 ld a1,-32720\(gp\) + 120000358: 64a500e0 daddiu a1,a1,224 + 12000035c: 3c190000 lui t9,0x0 + 120000360: 033cc82d daddu t9,t9,gp -+ 120000364: df398038 ld t9,-32712\(t9\) -+ 120000368: df998040 ld t9,-32704\(gp\) ++ 120000364: df398058 ld t9,-32680\(t9\) ++ 120000368: df998030 ld t9,-32720\(gp\) + 12000036c: 673900e0 daddiu t9,t9,224 + 120000370: 3c190000 lui t9,0x0 + 120000374: 033cc82d daddu t9,t9,gp -+ 120000378: df398038 ld t9,-32712\(t9\) ++ 120000378: df398058 ld t9,-32680\(t9\) + 12000037c: 0411ff58 bal 1200000e0 + 120000380: 00000000 nop -+ 120000384: df998040 ld t9,-32704\(gp\) ++ 120000384: df998030 ld t9,-32720\(gp\) + 120000388: 673900e0 daddiu t9,t9,224 + 12000038c: 0411ff54 bal 1200000e0 + 120000390: 00000000 nop + 120000394: 3c050000 lui a1,0x0 + 120000398: 00bc282d daddu a1,a1,gp -+ 12000039c: dca58048 ld a1,-32696\(a1\) ++ 12000039c: dca58050 ld a1,-32688\(a1\) + 1200003a0: 3c050000 lui a1,0x0 + 1200003a4: 00bc282d daddu a1,a1,gp -+ 1200003a8: dca58048 ld a1,-32696\(a1\) ++ 1200003a8: dca58050 ld a1,-32688\(a1\) + 1200003ac: 64a5000c daddiu a1,a1,12 + 1200003b0: 3c050000 lui a1,0x0 + 1200003b4: 00bc282d daddu a1,a1,gp -+ 1200003b8: dca58048 ld a1,-32696\(a1\) ++ 1200003b8: dca58050 ld a1,-32688\(a1\) + 1200003bc: 3c010001 lui at,0x1 + 1200003c0: 3421e240 ori at,at,0xe240 + 1200003c4: 00a1282d daddu a1,a1,at + 1200003c8: 3c050000 lui a1,0x0 + 1200003cc: 00bc282d daddu a1,a1,gp -+ 1200003d0: dca58048 ld a1,-32696\(a1\) ++ 1200003d0: dca58050 ld a1,-32688\(a1\) + 1200003d4: 00b1282d daddu a1,a1,s1 + 1200003d8: 3c050000 lui a1,0x0 + 1200003dc: 00bc282d daddu a1,a1,gp -+ 1200003e0: dca58048 ld a1,-32696\(a1\) ++ 1200003e0: dca58050 ld a1,-32688\(a1\) + 1200003e4: 64a5000c daddiu a1,a1,12 + 1200003e8: 00b1282d daddu a1,a1,s1 + 1200003ec: 3c050000 lui a1,0x0 + 1200003f0: 00bc282d daddu a1,a1,gp -+ 1200003f4: dca58048 ld a1,-32696\(a1\) ++ 1200003f4: dca58050 ld a1,-32688\(a1\) + 1200003f8: 3c010001 lui at,0x1 + 1200003fc: 3421e240 ori at,at,0xe240 + 120000400: 00a1282d daddu a1,a1,at + 120000404: 00b1282d daddu a1,a1,s1 + 120000408: 3c050000 lui a1,0x0 + 12000040c: 00bc282d daddu a1,a1,gp -+ 120000410: dca58048 ld a1,-32696\(a1\) ++ 120000410: dca58050 ld a1,-32688\(a1\) + 120000414: dca50000 ld a1,0\(a1\) + 120000418: 3c050000 lui a1,0x0 + 12000041c: 00bc282d daddu a1,a1,gp -+ 120000420: dca58048 ld a1,-32696\(a1\) ++ 120000420: dca58050 ld a1,-32688\(a1\) + 120000424: dca5000c ld a1,12\(a1\) + 120000428: 3c050000 lui a1,0x0 + 12000042c: 00bc282d daddu a1,a1,gp -+ 120000430: dca58048 ld a1,-32696\(a1\) ++ 120000430: dca58050 ld a1,-32688\(a1\) + 120000434: 00b1282d daddu a1,a1,s1 + 120000438: dca50000 ld a1,0\(a1\) + 12000043c: 3c050000 lui a1,0x0 + 120000440: 00bc282d daddu a1,a1,gp -+ 120000444: dca58048 ld a1,-32696\(a1\) ++ 120000444: dca58050 ld a1,-32688\(a1\) + 120000448: 00b1282d daddu a1,a1,s1 + 12000044c: dca5000c ld a1,12\(a1\) + 120000450: 3c010000 lui at,0x0 + 120000454: 003c082d daddu at,at,gp -+ 120000458: dc218048 ld at,-32696\(at\) ++ 120000458: dc218050 ld at,-32688\(at\) + 12000045c: 0025082d daddu at,at,a1 + 120000460: dc250022 ld a1,34\(at\) + 120000464: 3c010000 lui at,0x0 + 120000468: 003c082d daddu at,at,gp -+ 12000046c: dc218048 ld at,-32696\(at\) ++ 12000046c: dc218050 ld at,-32688\(at\) + 120000470: 0025082d daddu at,at,a1 + 120000474: fc250038 sd a1,56\(at\) + 120000478: 3c010000 lui at,0x0 + 12000047c: 003c082d daddu at,at,gp -+ 120000480: dc218048 ld at,-32696\(at\) ++ 120000480: dc218050 ld at,-32688\(at\) + 120000484: 88250000 lwl a1,0\(at\) + 120000488: 98250003 lwr a1,3\(at\) + 12000048c: 3c010000 lui at,0x0 + 120000490: 003c082d daddu at,at,gp -+ 120000494: dc218048 ld at,-32696\(at\) ++ 120000494: dc218050 ld at,-32688\(at\) + 120000498: 6421000c daddiu at,at,12 + 12000049c: 88250000 lwl a1,0\(at\) + 1200004a0: 98250003 lwr a1,3\(at\) + 1200004a4: 3c010000 lui at,0x0 + 1200004a8: 003c082d daddu at,at,gp -+ 1200004ac: dc218048 ld at,-32696\(at\) ++ 1200004ac: dc218050 ld at,-32688\(at\) + 1200004b0: 0031082d daddu at,at,s1 + 1200004b4: 88250000 lwl a1,0\(at\) + 1200004b8: 98250003 lwr a1,3\(at\) + 1200004bc: 3c010000 lui at,0x0 + 1200004c0: 003c082d daddu at,at,gp -+ 1200004c4: dc218048 ld at,-32696\(at\) ++ 1200004c4: dc218050 ld at,-32688\(at\) + 1200004c8: 6421000c daddiu at,at,12 + 1200004cc: 0031082d daddu at,at,s1 + 1200004d0: 88250000 lwl a1,0\(at\) + 1200004d4: 98250003 lwr a1,3\(at\) + 1200004d8: 3c010000 lui at,0x0 + 1200004dc: 003c082d daddu at,at,gp -+ 1200004e0: dc218048 ld at,-32696\(at\) ++ 1200004e0: dc218050 ld at,-32688\(at\) + 1200004e4: 64210022 daddiu at,at,34 + 1200004e8: 0025082d daddu at,at,a1 + 1200004ec: 88250000 lwl a1,0\(at\) + 1200004f0: 98250003 lwr a1,3\(at\) + 1200004f4: 3c010000 lui at,0x0 + 1200004f8: 003c082d daddu at,at,gp -+ 1200004fc: dc218048 ld at,-32696\(at\) ++ 1200004fc: dc218050 ld at,-32688\(at\) + 120000500: 64210038 daddiu at,at,56 + 120000504: 0025082d daddu at,at,a1 + 120000508: a8250000 swl a1,0\(at\) + 12000050c: b8250003 swr a1,3\(at\) -+ 120000510: df858028 ld a1,-32728\(gp\) ++ 120000510: df858020 ld a1,-32736\(gp\) + 120000514: 64a507a4 daddiu a1,a1,1956 -+ 120000518: df858028 ld a1,-32728\(gp\) ++ 120000518: df858020 ld a1,-32736\(gp\) + 12000051c: 64a507b0 daddiu a1,a1,1968 -+ 120000520: df858030 ld a1,-32720\(gp\) ++ 120000520: df858028 ld a1,-32728\(gp\) + 120000524: 64a5e9e4 daddiu a1,a1,-5660 -+ 120000528: df858028 ld a1,-32728\(gp\) ++ 120000528: df858020 ld a1,-32736\(gp\) + 12000052c: 64a507a4 daddiu a1,a1,1956 + 120000530: 00b1282d daddu a1,a1,s1 -+ 120000534: df858028 ld a1,-32728\(gp\) ++ 120000534: df858020 ld a1,-32736\(gp\) + 120000538: 64a507b0 daddiu a1,a1,1968 + 12000053c: 00b1282d daddu a1,a1,s1 -+ 120000540: df858030 ld a1,-32720\(gp\) ++ 120000540: df858028 ld a1,-32728\(gp\) + 120000544: 64a5e9e4 daddiu a1,a1,-5660 + 120000548: 00b1282d daddu a1,a1,s1 -+ 12000054c: df858028 ld a1,-32728\(gp\) ++ 12000054c: df858020 ld a1,-32736\(gp\) + 120000550: dca507a4 ld a1,1956\(a1\) -+ 120000554: df858028 ld a1,-32728\(gp\) ++ 120000554: df858020 ld a1,-32736\(gp\) + 120000558: dca507b0 ld a1,1968\(a1\) -+ 12000055c: df858028 ld a1,-32728\(gp\) ++ 12000055c: df858020 ld a1,-32736\(gp\) + 120000560: 00b1282d daddu a1,a1,s1 + 120000564: dca507a4 ld a1,1956\(a1\) -+ 120000568: df858028 ld a1,-32728\(gp\) ++ 120000568: df858020 ld a1,-32736\(gp\) + 12000056c: 00b1282d daddu a1,a1,s1 + 120000570: dca507b0 ld a1,1968\(a1\) -+ 120000574: df818028 ld at,-32728\(gp\) ++ 120000574: df818020 ld at,-32736\(gp\) + 120000578: 0025082d daddu at,at,a1 + 12000057c: dc2507c6 ld a1,1990\(at\) -+ 120000580: df818028 ld at,-32728\(gp\) ++ 120000580: df818020 ld at,-32736\(gp\) + 120000584: 0025082d daddu at,at,a1 + 120000588: fc2507dc sd a1,2012\(at\) -+ 12000058c: df818028 ld at,-32728\(gp\) ++ 12000058c: df818020 ld at,-32736\(gp\) + 120000590: 642107a4 daddiu at,at,1956 + 120000594: 88250000 lwl a1,0\(at\) + 120000598: 98250003 lwr a1,3\(at\) -+ 12000059c: df818028 ld at,-32728\(gp\) ++ 12000059c: df818020 ld at,-32736\(gp\) + 1200005a0: 642107b0 daddiu at,at,1968 + 1200005a4: 88250000 lwl a1,0\(at\) + 1200005a8: 98250003 lwr a1,3\(at\) -+ 1200005ac: df818028 ld at,-32728\(gp\) ++ 1200005ac: df818020 ld at,-32736\(gp\) + 1200005b0: 642107a4 daddiu at,at,1956 + 1200005b4: 0031082d daddu at,at,s1 + 1200005b8: 88250000 lwl a1,0\(at\) + 1200005bc: 98250003 lwr a1,3\(at\) -+ 1200005c0: df818028 ld at,-32728\(gp\) ++ 1200005c0: df818020 ld at,-32736\(gp\) + 1200005c4: 642107b0 daddiu at,at,1968 + 1200005c8: 0031082d daddu at,at,s1 + 1200005cc: 88250000 lwl a1,0\(at\) + 1200005d0: 98250003 lwr a1,3\(at\) -+ 1200005d4: df818028 ld at,-32728\(gp\) ++ 1200005d4: df818020 ld at,-32736\(gp\) + 1200005d8: 642107c6 daddiu at,at,1990 + 1200005dc: 0025082d daddu at,at,a1 + 1200005e0: 88250000 lwl a1,0\(at\) + 1200005e4: 98250003 lwr a1,3\(at\) -+ 1200005e8: df818028 ld at,-32728\(gp\) ++ 1200005e8: df818020 ld at,-32736\(gp\) + 1200005ec: 642107dc daddiu at,at,2012 + 1200005f0: 0025082d daddu at,at,a1 + 1200005f4: a8250000 swl a1,0\(at\) + 1200005f8: b8250003 swr a1,3\(at\) + 1200005fc: 3c050000 lui a1,0x0 + 120000600: 00bc282d daddu a1,a1,gp -+ 120000604: dca58050 ld a1,-32688\(a1\) -+ 120000608: df858040 ld a1,-32704\(gp\) ++ 120000604: dca58048 ld a1,-32696\(a1\) ++ 120000608: df858030 ld a1,-32720\(gp\) + 12000060c: 64a506e0 daddiu a1,a1,1760 + 120000610: 3c190000 lui t9,0x0 + 120000614: 033cc82d daddu t9,t9,gp -+ 120000618: df398050 ld t9,-32688\(t9\) -+ 12000061c: df998040 ld t9,-32704\(gp\) ++ 120000618: df398048 ld t9,-32696\(t9\) ++ 12000061c: df998030 ld t9,-32720\(gp\) + 120000620: 673906e0 daddiu t9,t9,1760 + 120000624: 3c190000 lui t9,0x0 + 120000628: 033cc82d daddu t9,t9,gp -+ 12000062c: df398050 ld t9,-32688\(t9\) ++ 12000062c: df398048 ld t9,-32696\(t9\) + 120000630: 0411002b bal 1200006e0 + 120000634: 00000000 nop -+ 120000638: df998040 ld t9,-32704\(gp\) ++ 120000638: df998030 ld t9,-32720\(gp\) + 12000063c: 673906e0 daddiu t9,t9,1760 + 120000640: 04110027 bal 1200006e0 + 120000644: 00000000 nop + 120000648: 3c050000 lui a1,0x0 + 12000064c: 00bc282d daddu a1,a1,gp -+ 120000650: dca58020 ld a1,-32736\(a1\) ++ 120000650: dca58060 ld a1,-32672\(a1\) + 120000654: 1000fea2 b 1200000e0 + 120000658: 00000000 nop + 12000065c: 3c050000 lui a1,0x0 + 120000660: 00bc282d daddu a1,a1,gp -+ 120000664: dca58048 ld a1,-32696\(a1\) ++ 120000664: dca58050 ld a1,-32688\(a1\) + 120000668: dca50000 ld a1,0\(a1\) + 12000066c: 1000001c b 1200006e0 + 120000670: 00000000 nop -+ 120000674: df858028 ld a1,-32728\(gp\) ++ 120000674: df858020 ld a1,-32736\(gp\) + 120000678: 64a5072c daddiu a1,a1,1836 + 12000067c: 1000fe98 b 1200000e0 + 120000680: 00000000 nop -+ 120000684: df858028 ld a1,-32728\(gp\) ++ 120000684: df858020 ld a1,-32736\(gp\) + 120000688: 64a507b0 daddiu a1,a1,1968 + 12000068c: 10000014 b 1200006e0 + 120000690: 00000000 nop -+ 120000694: df858030 ld a1,-32720\(gp\) ++ 120000694: df858028 ld a1,-32728\(gp\) + 120000698: 64a5e96c daddiu a1,a1,-5780 + 12000069c: 1000fe90 b 1200000e0 + 1200006a0: 00000000 nop -+ 1200006a4: df858028 ld a1,-32728\(gp\) ++ 1200006a4: df858020 ld a1,-32736\(gp\) + 1200006a8: dca507a4 ld a1,1956\(a1\) + 1200006ac: 1000000c b 1200006e0 + 1200006b0: 00000000 nop -+ 1200006b4: df858028 ld a1,-32728\(gp\) ++ 1200006b4: df858020 ld a1,-32736\(gp\) + 1200006b8: dca50738 ld a1,1848\(a1\) + 1200006bc: 1000fe88 b 1200000e0 + 1200006c0: 00000000 nop -+ 1200006c4: df818028 ld at,-32728\(gp\) ++ 1200006c4: df818020 ld at,-32736\(gp\) + 1200006c8: 0025082d daddu at,at,a1 + 1200006cc: dc2507c6 ld a1,1990\(at\) + 1200006d0: 10000003 b 1200006e0 @@ -2820169,27 +2835620,27 @@ index 0000000..be446f0 + 1200107e8: 80000000 .* + 1200107ec: 00000000 .* + 1200107f0: 00000001 .* -+ 1200107f4: 2001072c .* ++ 1200107f4: 20010000 .* + 1200107f8: 00000001 .* -+ 1200107fc: 20010000 .* ++ 1200107fc: 20030000 .* + 120010800: 00000001 .* -+ 120010804: 20030000 .* -+ 120010808: 00000001 .* -+ 12001080c: 200000e0 .* -+ 120010810: 00000001 .* -+ 120010814: 20000000 .* -+ 120010818: 00000001 .* -+ 12001081c: 200107a4 .* -+ 120010820: 00000001 .* -+ 120010824: 200006e0 .* ++ 120010804: 20000000 .* + \.\.\. ++ 120010818: 00000001 .* ++ 12001081c: 200006e0 .* ++ 120010820: 00000001 .* ++ 120010824: 200107a4 .* ++ 120010828: 00000001 .* ++ 12001082c: 200000e0 .* ++ 120010830: 00000001 .* ++ 120010834: 2001072c .* +#pass diff --git a/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64.d b/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64.d new file mode 100644 -index 0000000..6a9ea40 +index 0000000..72ac666 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64.d -@@ -0,0 +1,439 @@ +@@ -0,0 +1,438 @@ +#name: MIPS ELF xgot reloc n64 +#as: -march=from-abi -EB -64 -KPIC -xgot +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s @@ -2820211,382 +2835662,382 @@ index 0000000..6a9ea40 +0000000010000110 : + 10000110: 3c050000 lui a1,0x0 + 10000114: 00bc282d daddu a1,a1,gp -+ 10000118: dca58020 ld a1,-32736\(a1\) ++ 10000118: dca58060 ld a1,-32672\(a1\) + 1000011c: 3c050000 lui a1,0x0 + 10000120: 00bc282d daddu a1,a1,gp -+ 10000124: dca58020 ld a1,-32736\(a1\) ++ 10000124: dca58060 ld a1,-32672\(a1\) + 10000128: 64a5000c daddiu a1,a1,12 + 1000012c: 3c050000 lui a1,0x0 + 10000130: 00bc282d daddu a1,a1,gp -+ 10000134: dca58020 ld a1,-32736\(a1\) ++ 10000134: dca58060 ld a1,-32672\(a1\) + 10000138: 3c010001 lui at,0x1 + 1000013c: 3421e240 ori at,at,0xe240 + 10000140: 00a1282d daddu a1,a1,at + 10000144: 3c050000 lui a1,0x0 + 10000148: 00bc282d daddu a1,a1,gp -+ 1000014c: dca58020 ld a1,-32736\(a1\) ++ 1000014c: dca58060 ld a1,-32672\(a1\) + 10000150: 00b1282d daddu a1,a1,s1 + 10000154: 3c050000 lui a1,0x0 + 10000158: 00bc282d daddu a1,a1,gp -+ 1000015c: dca58020 ld a1,-32736\(a1\) ++ 1000015c: dca58060 ld a1,-32672\(a1\) + 10000160: 64a5000c daddiu a1,a1,12 + 10000164: 00b1282d daddu a1,a1,s1 + 10000168: 3c050000 lui a1,0x0 + 1000016c: 00bc282d daddu a1,a1,gp -+ 10000170: dca58020 ld a1,-32736\(a1\) ++ 10000170: dca58060 ld a1,-32672\(a1\) + 10000174: 3c010001 lui at,0x1 + 10000178: 3421e240 ori at,at,0xe240 + 1000017c: 00a1282d daddu a1,a1,at + 10000180: 00b1282d daddu a1,a1,s1 + 10000184: 3c050000 lui a1,0x0 + 10000188: 00bc282d daddu a1,a1,gp -+ 1000018c: dca58020 ld a1,-32736\(a1\) ++ 1000018c: dca58060 ld a1,-32672\(a1\) + 10000190: dca50000 ld a1,0\(a1\) + 10000194: 3c050000 lui a1,0x0 + 10000198: 00bc282d daddu a1,a1,gp -+ 1000019c: dca58020 ld a1,-32736\(a1\) ++ 1000019c: dca58060 ld a1,-32672\(a1\) + 100001a0: dca5000c ld a1,12\(a1\) + 100001a4: 3c050000 lui a1,0x0 + 100001a8: 00bc282d daddu a1,a1,gp -+ 100001ac: dca58020 ld a1,-32736\(a1\) ++ 100001ac: dca58060 ld a1,-32672\(a1\) + 100001b0: 00b1282d daddu a1,a1,s1 + 100001b4: dca50000 ld a1,0\(a1\) + 100001b8: 3c050000 lui a1,0x0 + 100001bc: 00bc282d daddu a1,a1,gp -+ 100001c0: dca58020 ld a1,-32736\(a1\) ++ 100001c0: dca58060 ld a1,-32672\(a1\) + 100001c4: 00b1282d daddu a1,a1,s1 + 100001c8: dca5000c ld a1,12\(a1\) + 100001cc: 3c010000 lui at,0x0 + 100001d0: 003c082d daddu at,at,gp -+ 100001d4: dc218020 ld at,-32736\(at\) ++ 100001d4: dc218060 ld at,-32672\(at\) + 100001d8: 0025082d daddu at,at,a1 + 100001dc: dc250022 ld a1,34\(at\) + 100001e0: 3c010000 lui at,0x0 + 100001e4: 003c082d daddu at,at,gp -+ 100001e8: dc218020 ld at,-32736\(at\) ++ 100001e8: dc218060 ld at,-32672\(at\) + 100001ec: 0025082d daddu at,at,a1 + 100001f0: fc250038 sd a1,56\(at\) + 100001f4: 3c010000 lui at,0x0 + 100001f8: 003c082d daddu at,at,gp -+ 100001fc: dc218020 ld at,-32736\(at\) ++ 100001fc: dc218060 ld at,-32672\(at\) + 10000200: 88250000 lwl a1,0\(at\) + 10000204: 98250003 lwr a1,3\(at\) + 10000208: 3c010000 lui at,0x0 + 1000020c: 003c082d daddu at,at,gp -+ 10000210: dc218020 ld at,-32736\(at\) ++ 10000210: dc218060 ld at,-32672\(at\) + 10000214: 6421000c daddiu at,at,12 + 10000218: 88250000 lwl a1,0\(at\) + 1000021c: 98250003 lwr a1,3\(at\) + 10000220: 3c010000 lui at,0x0 + 10000224: 003c082d daddu at,at,gp -+ 10000228: dc218020 ld at,-32736\(at\) ++ 10000228: dc218060 ld at,-32672\(at\) + 1000022c: 0031082d daddu at,at,s1 + 10000230: 88250000 lwl a1,0\(at\) + 10000234: 98250003 lwr a1,3\(at\) + 10000238: 3c010000 lui at,0x0 + 1000023c: 003c082d daddu at,at,gp -+ 10000240: dc218020 ld at,-32736\(at\) ++ 10000240: dc218060 ld at,-32672\(at\) + 10000244: 6421000c daddiu at,at,12 + 10000248: 0031082d daddu at,at,s1 + 1000024c: 88250000 lwl a1,0\(at\) + 10000250: 98250003 lwr a1,3\(at\) + 10000254: 3c010000 lui at,0x0 + 10000258: 003c082d daddu at,at,gp -+ 1000025c: dc218020 ld at,-32736\(at\) ++ 1000025c: dc218060 ld at,-32672\(at\) + 10000260: 64210022 daddiu at,at,34 + 10000264: 0025082d daddu at,at,a1 + 10000268: 88250000 lwl a1,0\(at\) + 1000026c: 98250003 lwr a1,3\(at\) + 10000270: 3c010000 lui at,0x0 + 10000274: 003c082d daddu at,at,gp -+ 10000278: dc218020 ld at,-32736\(at\) ++ 10000278: dc218060 ld at,-32672\(at\) + 1000027c: 64210038 daddiu at,at,56 + 10000280: 0025082d daddu at,at,a1 + 10000284: a8250000 swl a1,0\(at\) + 10000288: b8250003 swr a1,3\(at\) -+ 1000028c: df858028 ld a1,-32728\(gp\) ++ 1000028c: df858020 ld a1,-32736\(gp\) + 10000290: 64a5075c daddiu a1,a1,1884 -+ 10000294: df858028 ld a1,-32728\(gp\) ++ 10000294: df858020 ld a1,-32736\(gp\) + 10000298: 64a50768 daddiu a1,a1,1896 -+ 1000029c: df858030 ld a1,-32720\(gp\) ++ 1000029c: df858028 ld a1,-32728\(gp\) + 100002a0: 64a5e99c daddiu a1,a1,-5732 -+ 100002a4: df858028 ld a1,-32728\(gp\) ++ 100002a4: df858020 ld a1,-32736\(gp\) + 100002a8: 64a5075c daddiu a1,a1,1884 + 100002ac: 00b1282d daddu a1,a1,s1 -+ 100002b0: df858028 ld a1,-32728\(gp\) ++ 100002b0: df858020 ld a1,-32736\(gp\) + 100002b4: 64a50768 daddiu a1,a1,1896 + 100002b8: 00b1282d daddu a1,a1,s1 -+ 100002bc: df858030 ld a1,-32720\(gp\) ++ 100002bc: df858028 ld a1,-32728\(gp\) + 100002c0: 64a5e99c daddiu a1,a1,-5732 + 100002c4: 00b1282d daddu a1,a1,s1 -+ 100002c8: df858028 ld a1,-32728\(gp\) ++ 100002c8: df858020 ld a1,-32736\(gp\) + 100002cc: dca5075c ld a1,1884\(a1\) -+ 100002d0: df858028 ld a1,-32728\(gp\) ++ 100002d0: df858020 ld a1,-32736\(gp\) + 100002d4: dca50768 ld a1,1896\(a1\) -+ 100002d8: df858028 ld a1,-32728\(gp\) ++ 100002d8: df858020 ld a1,-32736\(gp\) + 100002dc: 00b1282d daddu a1,a1,s1 + 100002e0: dca5075c ld a1,1884\(a1\) -+ 100002e4: df858028 ld a1,-32728\(gp\) ++ 100002e4: df858020 ld a1,-32736\(gp\) + 100002e8: 00b1282d daddu a1,a1,s1 + 100002ec: dca50768 ld a1,1896\(a1\) -+ 100002f0: df818028 ld at,-32728\(gp\) ++ 100002f0: df818020 ld at,-32736\(gp\) + 100002f4: 0025082d daddu at,at,a1 + 100002f8: dc25077e ld a1,1918\(at\) -+ 100002fc: df818028 ld at,-32728\(gp\) ++ 100002fc: df818020 ld at,-32736\(gp\) + 10000300: 0025082d daddu at,at,a1 + 10000304: fc250794 sd a1,1940\(at\) -+ 10000308: df818028 ld at,-32728\(gp\) ++ 10000308: df818020 ld at,-32736\(gp\) + 1000030c: 6421075c daddiu at,at,1884 + 10000310: 88250000 lwl a1,0\(at\) + 10000314: 98250003 lwr a1,3\(at\) -+ 10000318: df818028 ld at,-32728\(gp\) ++ 10000318: df818020 ld at,-32736\(gp\) + 1000031c: 64210768 daddiu at,at,1896 + 10000320: 88250000 lwl a1,0\(at\) + 10000324: 98250003 lwr a1,3\(at\) -+ 10000328: df818028 ld at,-32728\(gp\) ++ 10000328: df818020 ld at,-32736\(gp\) + 1000032c: 6421075c daddiu at,at,1884 + 10000330: 0031082d daddu at,at,s1 + 10000334: 88250000 lwl a1,0\(at\) + 10000338: 98250003 lwr a1,3\(at\) -+ 1000033c: df818028 ld at,-32728\(gp\) ++ 1000033c: df818020 ld at,-32736\(gp\) + 10000340: 64210768 daddiu at,at,1896 + 10000344: 0031082d daddu at,at,s1 + 10000348: 88250000 lwl a1,0\(at\) + 1000034c: 98250003 lwr a1,3\(at\) -+ 10000350: df818028 ld at,-32728\(gp\) ++ 10000350: df818020 ld at,-32736\(gp\) + 10000354: 6421077e daddiu at,at,1918 + 10000358: 0025082d daddu at,at,a1 + 1000035c: 88250000 lwl a1,0\(at\) + 10000360: 98250003 lwr a1,3\(at\) -+ 10000364: df818028 ld at,-32728\(gp\) ++ 10000364: df818020 ld at,-32736\(gp\) + 10000368: 64210794 daddiu at,at,1940 + 1000036c: 0025082d daddu at,at,a1 + 10000370: a8250000 swl a1,0\(at\) + 10000374: b8250003 swr a1,3\(at\) + 10000378: 3c050000 lui a1,0x0 + 1000037c: 00bc282d daddu a1,a1,gp -+ 10000380: dca58038 ld a1,-32712\(a1\) -+ 10000384: df858040 ld a1,-32704\(gp\) ++ 10000380: dca58058 ld a1,-32680\(a1\) ++ 10000384: df858030 ld a1,-32720\(gp\) + 10000388: 64a50110 daddiu a1,a1,272 + 1000038c: 3c190000 lui t9,0x0 + 10000390: 033cc82d daddu t9,t9,gp -+ 10000394: df398038 ld t9,-32712\(t9\) -+ 10000398: df998040 ld t9,-32704\(gp\) ++ 10000394: df398058 ld t9,-32680\(t9\) ++ 10000398: df998030 ld t9,-32720\(gp\) + 1000039c: 67390110 daddiu t9,t9,272 + 100003a0: 3c190000 lui t9,0x0 + 100003a4: 033cc82d daddu t9,t9,gp -+ 100003a8: df398038 ld t9,-32712\(t9\) ++ 100003a8: df398058 ld t9,-32680\(t9\) + 100003ac: 0411ff58 bal 10000110 + 100003b0: 00000000 nop -+ 100003b4: df998040 ld t9,-32704\(gp\) ++ 100003b4: df998030 ld t9,-32720\(gp\) + 100003b8: 67390110 daddiu t9,t9,272 + 100003bc: 0411ff54 bal 10000110 + 100003c0: 00000000 nop + 100003c4: 3c050000 lui a1,0x0 + 100003c8: 00bc282d daddu a1,a1,gp -+ 100003cc: dca58048 ld a1,-32696\(a1\) ++ 100003cc: dca58050 ld a1,-32688\(a1\) + 100003d0: 3c050000 lui a1,0x0 + 100003d4: 00bc282d daddu a1,a1,gp -+ 100003d8: dca58048 ld a1,-32696\(a1\) ++ 100003d8: dca58050 ld a1,-32688\(a1\) + 100003dc: 64a5000c daddiu a1,a1,12 + 100003e0: 3c050000 lui a1,0x0 + 100003e4: 00bc282d daddu a1,a1,gp -+ 100003e8: dca58048 ld a1,-32696\(a1\) ++ 100003e8: dca58050 ld a1,-32688\(a1\) + 100003ec: 3c010001 lui at,0x1 + 100003f0: 3421e240 ori at,at,0xe240 + 100003f4: 00a1282d daddu a1,a1,at + 100003f8: 3c050000 lui a1,0x0 + 100003fc: 00bc282d daddu a1,a1,gp -+ 10000400: dca58048 ld a1,-32696\(a1\) ++ 10000400: dca58050 ld a1,-32688\(a1\) + 10000404: 00b1282d daddu a1,a1,s1 + 10000408: 3c050000 lui a1,0x0 + 1000040c: 00bc282d daddu a1,a1,gp -+ 10000410: dca58048 ld a1,-32696\(a1\) ++ 10000410: dca58050 ld a1,-32688\(a1\) + 10000414: 64a5000c daddiu a1,a1,12 + 10000418: 00b1282d daddu a1,a1,s1 + 1000041c: 3c050000 lui a1,0x0 + 10000420: 00bc282d daddu a1,a1,gp -+ 10000424: dca58048 ld a1,-32696\(a1\) ++ 10000424: dca58050 ld a1,-32688\(a1\) + 10000428: 3c010001 lui at,0x1 + 1000042c: 3421e240 ori at,at,0xe240 + 10000430: 00a1282d daddu a1,a1,at + 10000434: 00b1282d daddu a1,a1,s1 + 10000438: 3c050000 lui a1,0x0 + 1000043c: 00bc282d daddu a1,a1,gp -+ 10000440: dca58048 ld a1,-32696\(a1\) ++ 10000440: dca58050 ld a1,-32688\(a1\) + 10000444: dca50000 ld a1,0\(a1\) + 10000448: 3c050000 lui a1,0x0 + 1000044c: 00bc282d daddu a1,a1,gp -+ 10000450: dca58048 ld a1,-32696\(a1\) ++ 10000450: dca58050 ld a1,-32688\(a1\) + 10000454: dca5000c ld a1,12\(a1\) + 10000458: 3c050000 lui a1,0x0 + 1000045c: 00bc282d daddu a1,a1,gp -+ 10000460: dca58048 ld a1,-32696\(a1\) ++ 10000460: dca58050 ld a1,-32688\(a1\) + 10000464: 00b1282d daddu a1,a1,s1 + 10000468: dca50000 ld a1,0\(a1\) + 1000046c: 3c050000 lui a1,0x0 + 10000470: 00bc282d daddu a1,a1,gp -+ 10000474: dca58048 ld a1,-32696\(a1\) ++ 10000474: dca58050 ld a1,-32688\(a1\) + 10000478: 00b1282d daddu a1,a1,s1 + 1000047c: dca5000c ld a1,12\(a1\) + 10000480: 3c010000 lui at,0x0 + 10000484: 003c082d daddu at,at,gp -+ 10000488: dc218048 ld at,-32696\(at\) ++ 10000488: dc218050 ld at,-32688\(at\) + 1000048c: 0025082d daddu at,at,a1 + 10000490: dc250022 ld a1,34\(at\) + 10000494: 3c010000 lui at,0x0 + 10000498: 003c082d daddu at,at,gp -+ 1000049c: dc218048 ld at,-32696\(at\) ++ 1000049c: dc218050 ld at,-32688\(at\) + 100004a0: 0025082d daddu at,at,a1 + 100004a4: fc250038 sd a1,56\(at\) + 100004a8: 3c010000 lui at,0x0 + 100004ac: 003c082d daddu at,at,gp -+ 100004b0: dc218048 ld at,-32696\(at\) ++ 100004b0: dc218050 ld at,-32688\(at\) + 100004b4: 88250000 lwl a1,0\(at\) + 100004b8: 98250003 lwr a1,3\(at\) + 100004bc: 3c010000 lui at,0x0 + 100004c0: 003c082d daddu at,at,gp -+ 100004c4: dc218048 ld at,-32696\(at\) ++ 100004c4: dc218050 ld at,-32688\(at\) + 100004c8: 6421000c daddiu at,at,12 + 100004cc: 88250000 lwl a1,0\(at\) + 100004d0: 98250003 lwr a1,3\(at\) + 100004d4: 3c010000 lui at,0x0 + 100004d8: 003c082d daddu at,at,gp -+ 100004dc: dc218048 ld at,-32696\(at\) ++ 100004dc: dc218050 ld at,-32688\(at\) + 100004e0: 0031082d daddu at,at,s1 + 100004e4: 88250000 lwl a1,0\(at\) + 100004e8: 98250003 lwr a1,3\(at\) + 100004ec: 3c010000 lui at,0x0 + 100004f0: 003c082d daddu at,at,gp -+ 100004f4: dc218048 ld at,-32696\(at\) ++ 100004f4: dc218050 ld at,-32688\(at\) + 100004f8: 6421000c daddiu at,at,12 + 100004fc: 0031082d daddu at,at,s1 + 10000500: 88250000 lwl a1,0\(at\) + 10000504: 98250003 lwr a1,3\(at\) + 10000508: 3c010000 lui at,0x0 + 1000050c: 003c082d daddu at,at,gp -+ 10000510: dc218048 ld at,-32696\(at\) ++ 10000510: dc218050 ld at,-32688\(at\) + 10000514: 64210022 daddiu at,at,34 + 10000518: 0025082d daddu at,at,a1 + 1000051c: 88250000 lwl a1,0\(at\) + 10000520: 98250003 lwr a1,3\(at\) + 10000524: 3c010000 lui at,0x0 + 10000528: 003c082d daddu at,at,gp -+ 1000052c: dc218048 ld at,-32696\(at\) ++ 1000052c: dc218050 ld at,-32688\(at\) + 10000530: 64210038 daddiu at,at,56 + 10000534: 0025082d daddu at,at,a1 + 10000538: a8250000 swl a1,0\(at\) + 1000053c: b8250003 swr a1,3\(at\) -+ 10000540: df858028 ld a1,-32728\(gp\) ++ 10000540: df858020 ld a1,-32736\(gp\) + 10000544: 64a507d4 daddiu a1,a1,2004 -+ 10000548: df858028 ld a1,-32728\(gp\) ++ 10000548: df858020 ld a1,-32736\(gp\) + 1000054c: 64a507e0 daddiu a1,a1,2016 -+ 10000550: df858030 ld a1,-32720\(gp\) ++ 10000550: df858028 ld a1,-32728\(gp\) + 10000554: 64a5ea14 daddiu a1,a1,-5612 -+ 10000558: df858028 ld a1,-32728\(gp\) ++ 10000558: df858020 ld a1,-32736\(gp\) + 1000055c: 64a507d4 daddiu a1,a1,2004 + 10000560: 00b1282d daddu a1,a1,s1 -+ 10000564: df858028 ld a1,-32728\(gp\) ++ 10000564: df858020 ld a1,-32736\(gp\) + 10000568: 64a507e0 daddiu a1,a1,2016 + 1000056c: 00b1282d daddu a1,a1,s1 -+ 10000570: df858030 ld a1,-32720\(gp\) ++ 10000570: df858028 ld a1,-32728\(gp\) + 10000574: 64a5ea14 daddiu a1,a1,-5612 + 10000578: 00b1282d daddu a1,a1,s1 -+ 1000057c: df858028 ld a1,-32728\(gp\) ++ 1000057c: df858020 ld a1,-32736\(gp\) + 10000580: dca507d4 ld a1,2004\(a1\) -+ 10000584: df858028 ld a1,-32728\(gp\) ++ 10000584: df858020 ld a1,-32736\(gp\) + 10000588: dca507e0 ld a1,2016\(a1\) -+ 1000058c: df858028 ld a1,-32728\(gp\) ++ 1000058c: df858020 ld a1,-32736\(gp\) + 10000590: 00b1282d daddu a1,a1,s1 + 10000594: dca507d4 ld a1,2004\(a1\) -+ 10000598: df858028 ld a1,-32728\(gp\) ++ 10000598: df858020 ld a1,-32736\(gp\) + 1000059c: 00b1282d daddu a1,a1,s1 + 100005a0: dca507e0 ld a1,2016\(a1\) -+ 100005a4: df818028 ld at,-32728\(gp\) ++ 100005a4: df818020 ld at,-32736\(gp\) + 100005a8: 0025082d daddu at,at,a1 + 100005ac: dc2507f6 ld a1,2038\(at\) -+ 100005b0: df818028 ld at,-32728\(gp\) ++ 100005b0: df818020 ld at,-32736\(gp\) + 100005b4: 0025082d daddu at,at,a1 + 100005b8: fc25080c sd a1,2060\(at\) -+ 100005bc: df818028 ld at,-32728\(gp\) ++ 100005bc: df818020 ld at,-32736\(gp\) + 100005c0: 642107d4 daddiu at,at,2004 + 100005c4: 88250000 lwl a1,0\(at\) + 100005c8: 98250003 lwr a1,3\(at\) -+ 100005cc: df818028 ld at,-32728\(gp\) ++ 100005cc: df818020 ld at,-32736\(gp\) + 100005d0: 642107e0 daddiu at,at,2016 + 100005d4: 88250000 lwl a1,0\(at\) + 100005d8: 98250003 lwr a1,3\(at\) -+ 100005dc: df818028 ld at,-32728\(gp\) ++ 100005dc: df818020 ld at,-32736\(gp\) + 100005e0: 642107d4 daddiu at,at,2004 + 100005e4: 0031082d daddu at,at,s1 + 100005e8: 88250000 lwl a1,0\(at\) + 100005ec: 98250003 lwr a1,3\(at\) -+ 100005f0: df818028 ld at,-32728\(gp\) ++ 100005f0: df818020 ld at,-32736\(gp\) + 100005f4: 642107e0 daddiu at,at,2016 + 100005f8: 0031082d daddu at,at,s1 + 100005fc: 88250000 lwl a1,0\(at\) + 10000600: 98250003 lwr a1,3\(at\) -+ 10000604: df818028 ld at,-32728\(gp\) ++ 10000604: df818020 ld at,-32736\(gp\) + 10000608: 642107f6 daddiu at,at,2038 + 1000060c: 0025082d daddu at,at,a1 + 10000610: 88250000 lwl a1,0\(at\) + 10000614: 98250003 lwr a1,3\(at\) -+ 10000618: df818028 ld at,-32728\(gp\) ++ 10000618: df818020 ld at,-32736\(gp\) + 1000061c: 6421080c daddiu at,at,2060 + 10000620: 0025082d daddu at,at,a1 + 10000624: a8250000 swl a1,0\(at\) + 10000628: b8250003 swr a1,3\(at\) + 1000062c: 3c050000 lui a1,0x0 + 10000630: 00bc282d daddu a1,a1,gp -+ 10000634: dca58050 ld a1,-32688\(a1\) -+ 10000638: df858040 ld a1,-32704\(gp\) ++ 10000634: dca58048 ld a1,-32696\(a1\) ++ 10000638: df858030 ld a1,-32720\(gp\) + 1000063c: 64a50710 daddiu a1,a1,1808 + 10000640: 3c190000 lui t9,0x0 + 10000644: 033cc82d daddu t9,t9,gp -+ 10000648: df398050 ld t9,-32688\(t9\) -+ 1000064c: df998040 ld t9,-32704\(gp\) ++ 10000648: df398048 ld t9,-32696\(t9\) ++ 1000064c: df998030 ld t9,-32720\(gp\) + 10000650: 67390710 daddiu t9,t9,1808 + 10000654: 3c190000 lui t9,0x0 + 10000658: 033cc82d daddu t9,t9,gp -+ 1000065c: df398050 ld t9,-32688\(t9\) ++ 1000065c: df398048 ld t9,-32696\(t9\) + 10000660: 0411002b bal 10000710 + 10000664: 00000000 nop -+ 10000668: df998040 ld t9,-32704\(gp\) ++ 10000668: df998030 ld t9,-32720\(gp\) + 1000066c: 67390710 daddiu t9,t9,1808 + 10000670: 04110027 bal 10000710 + 10000674: 00000000 nop + 10000678: 3c050000 lui a1,0x0 + 1000067c: 00bc282d daddu a1,a1,gp -+ 10000680: dca58020 ld a1,-32736\(a1\) ++ 10000680: dca58060 ld a1,-32672\(a1\) + 10000684: 1000fea2 b 10000110 + 10000688: 00000000 nop + 1000068c: 3c050000 lui a1,0x0 + 10000690: 00bc282d daddu a1,a1,gp -+ 10000694: dca58048 ld a1,-32696\(a1\) ++ 10000694: dca58050 ld a1,-32688\(a1\) + 10000698: dca50000 ld a1,0\(a1\) + 1000069c: 1000001c b 10000710 + 100006a0: 00000000 nop -+ 100006a4: df858028 ld a1,-32728\(gp\) ++ 100006a4: df858020 ld a1,-32736\(gp\) + 100006a8: 64a5075c daddiu a1,a1,1884 + 100006ac: 1000fe98 b 10000110 + 100006b0: 00000000 nop -+ 100006b4: df858028 ld a1,-32728\(gp\) ++ 100006b4: df858020 ld a1,-32736\(gp\) + 100006b8: 64a507e0 daddiu a1,a1,2016 + 100006bc: 10000014 b 10000710 + 100006c0: 00000000 nop -+ 100006c4: df858030 ld a1,-32720\(gp\) ++ 100006c4: df858028 ld a1,-32728\(gp\) + 100006c8: 64a5e99c daddiu a1,a1,-5732 + 100006cc: 1000fe90 b 10000110 + 100006d0: 00000000 nop -+ 100006d4: df858028 ld a1,-32728\(gp\) ++ 100006d4: df858020 ld a1,-32736\(gp\) + 100006d8: dca507d4 ld a1,2004\(a1\) + 100006dc: 1000000c b 10000710 + 100006e0: 00000000 nop -+ 100006e4: df858028 ld a1,-32728\(gp\) ++ 100006e4: df858020 ld a1,-32736\(gp\) + 100006e8: dca50768 ld a1,1896\(a1\) + 100006ec: 1000fe88 b 10000110 + 100006f0: 00000000 nop -+ 100006f4: df818028 ld at,-32728\(gp\) ++ 100006f4: df818020 ld at,-32736\(gp\) + 100006f8: 0025082d daddu at,at,a1 + 100006fc: dc2507f6 ld a1,2038\(at\) + 10000700: 10000003 b 10000710 @@ -2820614,21 +2836065,20 @@ index 0000000..6a9ea40 + \.\.\. + 10010818: 80000000 .* + \.\.\. -+ 10010824: 1001075c .* ++ 10010824: 10010000 .* + 10010828: 00000000 .* -+ 1001082c: 10010000 .* ++ 1001082c: 10030000 .* + 10010830: 00000000 .* -+ 10010834: 10030000 .* ++ 10010834: 10000000 .* + 10010838: 00000000 .* -+ 1001083c: 10000110 .* -+ 10010840: 00000000 .* -+ 10010844: 10000000 .* -+ 10010848: 00000000 .* -+ 1001084c: 100107d4 .* -+ 10010850: 00000000 .* -+ 10010854: 10000710 .* -+ 10010858: 00000000 .* + \.\.\. ++ 1001084c: 10000710 .* ++ 10010850: 00000000 .* ++ 10010854: 100107d4 .* ++ 10010858: 00000000 .* ++ 1001085c: 10000110 .* ++ 10010860: 00000000 .* ++ 10010864: 1001075c .* diff --git a/ld/testsuite/ld-mips-elf/emit-relocs-1.d b/ld/testsuite/ld-mips-elf/emit-relocs-1.d new file mode 100644 index 0000000..bff7c70 @@ -2821136,13 +2836586,13 @@ index 0000000..39f6367 +} diff --git a/ld/testsuite/ld-mips-elf/export-class.exp b/ld/testsuite/ld-mips-elf/export-class.exp new file mode 100644 -index 0000000..150cc41 +index 0000000..7946d3c --- /dev/null +++ b/ld/testsuite/ld-mips-elf/export-class.exp @@ -0,0 +1,96 @@ +# Expect script for symbol export classes, MIPS variation. +# -+# Copyright 2012 Free Software Foundation, Inc. ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2823054,7 +2838504,7 @@ index 0000000..d0388ad + 0x12340090 00000000 123400a0 00000000 00000000 .* diff --git a/ld/testsuite/ld-mips-elf/mips-dyn.ld b/ld/testsuite/ld-mips-elf/mips-dyn.ld new file mode 100644 -index 0000000..e4f90d2 +index 0000000..b931e1b --- /dev/null +++ b/ld/testsuite/ld-mips-elf/mips-dyn.ld @@ -0,0 +1,223 @@ @@ -2823239,7 +2838689,7 @@ index 0000000..e4f90d2 + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ -+ . = ALIGN(32 / 8); ++ . = ALIGN(. != 0 ? 32 / 8 : 1); + } + . = ALIGN(32 / 8); + _end = .; @@ -2823283,11 +2838733,11 @@ index 0000000..e4f90d2 +} diff --git a/ld/testsuite/ld-mips-elf/mips-elf-flags.exp b/ld/testsuite/ld-mips-elf/mips-elf-flags.exp new file mode 100644 -index 0000000..a7e4453 +index 0000000..0e4b9a0 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/mips-elf-flags.exp @@ -0,0 +1,170 @@ -+# Copyright 2003, 2005, 2007 Free Software Foundation, Inc. ++# Copyright (C) 2003-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2823459,13 +2838909,12 @@ index 0000000..a7e4453 +good_combination { "-mips5 -mabi=o64" "-mips64r2 -mabi=o64" } { mips64r2 o64 } diff --git a/ld/testsuite/ld-mips-elf/mips-elf.exp b/ld/testsuite/ld-mips-elf/mips-elf.exp new file mode 100644 -index 0000000..a9d16ec +index 0000000..a2632b2 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/mips-elf.exp -@@ -0,0 +1,841 @@ +@@ -0,0 +1,840 @@ +# Expect script for MIPS ELF linker tests -+# Copyright 2002, 2003, 2004, 2005, 2006, 2007, 2008 -+# Free Software Foundation, Inc. ++# Copyright (C) 2002-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2824306,7 +2839755,7 @@ index 0000000..a9d16ec +run_dump_test "attr-gnu-8-22" diff --git a/ld/testsuite/ld-mips-elf/mips-lib.ld b/ld/testsuite/ld-mips-elf/mips-lib.ld new file mode 100644 -index 0000000..5073d9f +index 0000000..1d66c62 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/mips-lib.ld @@ -0,0 +1,218 @@ @@ -2824485,7 +2839934,7 @@ index 0000000..5073d9f + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ -+ . = ALIGN(32 / 8); ++ . = ALIGN(. != 0 ? 32 / 8 : 1); + } + . = ALIGN(32 / 8); + _end = .; @@ -2889395,7 +2904844,7 @@ index 0000000..385e7fd +data: .word 0x12345678 diff --git a/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.sd b/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.sd new file mode 100644 -index 0000000..58b50c3 +index 0000000..b178bdf --- /dev/null +++ b/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.sd @@ -0,0 +1,20 @@ @@ -2889409,7 +2904858,7 @@ index 0000000..58b50c3 + * REGINFO * [^ ]+ * 0x0+00000 * 0x0+00000 [^ ]+ * [^ ]+ * R * 0x.* + * LOAD * [^ ]+ * 0x0+00000 * 0x0+00000 [^ ]+ * [^ ]+ * R E * 0x.* + * LOAD * [^ ]+ * 0x0+10000 * 0x0+10000 [^ ]+ * [^ ]+ * RW * 0x.* -+ * DYNAMIC * [^ ]+ * 0x0+00400 * 0x0+00400 .* ++ * DYNAMIC * [^ ]+ * 0x0+00400 * 0x0+00400 [^ ]+ * [^ ]+ * R * 0x.* + * NULL * .* + + *Section to Segment mapping: @@ -2895838,12 +2911287,12 @@ index 0000000..5ff87d3 +#... diff --git a/ld/testsuite/ld-misc/defsym.exp b/ld/testsuite/ld-misc/defsym.exp new file mode 100644 -index 0000000..f554c2c +index 0000000..a7d6034 --- /dev/null +++ b/ld/testsuite/ld-misc/defsym.exp @@ -0,0 +1,37 @@ +# Test handling of --defsym -+# Copyright 2011 Free Software Foundation, Inc. ++# Copyright (C) 2011-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2896448,19 +2911897,42 @@ index 0000000..08bfdbf + .byte 0x98,0x0b,0x00,0x00,0x98,0x0c,0x00,0x00 diff --git a/ld/testsuite/ld-mmix/b-offloc.s b/ld/testsuite/ld-mmix/b-offloc.s new file mode 100644 -index 0000000..c2fb2cc +index 0000000..1114b34 --- /dev/null +++ b/ld/testsuite/ld-mmix/b-offloc.s @@ -0,0 +1,9 @@ +% The .text contents is supposed to be linked --oformat binary with +% b-post1.s and b-goodmain.s. The code below will provide a LOP_LOC -+% with a 64-bit address (0x789abcdef0123456) then 16 bytes of % random data. ++% with a 64-bit address (0x789abcdef0123458) then 16 bytes of % random data. + + .text + .byte 0x98,1,0,2 + .8byte 0x789abcdef0123458 + .byte 0xb0,0x45,0x19,0x7d,0x2c,0x1b,0x3,0xb2 + .byte 0xe4,0xdb,0xf8,0x77,0xf,0xc7,0x66,0xfb +diff --git a/ld/testsuite/ld-mmix/b-offlocmis.s b/ld/testsuite/ld-mmix/b-offlocmis.s +new file mode 100644 +index 0000000..4f2b340 +--- /dev/null ++++ b/ld/testsuite/ld-mmix/b-offlocmis.s +@@ -0,0 +1,17 @@ ++% The .text contents is supposed to be linked --oformat binary with ++% b-post1.s and b-goodmain.s. The code below will provide a LOP_LOC ++% with a 64-bit address (0x789abcdef012345b) then 16 bytes of % random ++% data. Note that the address is misaligned and the contents should ++% be handled as at 0x789abcdef0123458. After that, there's another ++% LOP_LOC, about 32 bytes further on, also at a misaligned address: ++% this time the data (0x12345677) is entered with a LOP_QUOTE. ++ ++ .text ++ .byte 0x98,1,0,2 ++ .8byte 0x789abcdef012345b ++ .byte 0xb0,0x45,0x19,0x7d,0x2c,0x1b,0x3,0xb2 ++ .byte 0xe4,0xdb,0xf8,0x77,0xf,0xc7,0x66,0xfb ++ .byte 0x98,1,0,2 ++ .8byte 0x789abcdef012347a ++ .byte 0x98,0,0,1 ++ .byte 0x12,0x34,0x56,0x77 diff --git a/ld/testsuite/ld-mmix/b-post1.s b/ld/testsuite/ld-mmix/b-post1.s new file mode 100644 index 0000000..a60aece @@ -2902275,12 +2917747,12 @@ index 0000000..212d1ef + SET $253,1 diff --git a/ld/testsuite/ld-mmix/mmix.exp b/ld/testsuite/ld-mmix/mmix.exp new file mode 100644 -index 0000000..e44101e +index 0000000..a7b7de0 --- /dev/null +++ b/ld/testsuite/ld-mmix/mmix.exp @@ -0,0 +1,35 @@ +# Expect script for ld-mmix tests -+# Copyright 2001, 2005, 2007 Free Software Foundation, Inc. ++# Copyright (C) 2001-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2904055,6 +2919527,105 @@ index 0000000..77e26e3 + + .section .a.fourth.section,"a" + OCTA 8888888,808080808 +diff --git a/ld/testsuite/ld-mmix/sec-10.d b/ld/testsuite/ld-mmix/sec-10.d +new file mode 100644 +index 0000000..a1c558d +--- /dev/null ++++ b/ld/testsuite/ld-mmix/sec-10.d +@@ -0,0 +1,18 @@ ++#source: start.s ++#source: sec-10.s ++#ld: -m mmo ++#objdump: -s ++ ++# There was yet another bug in the strip-zeros-at-beginning-and-end-of-data ++# code: it requires outputting the location when data is stripped, and that ++# location is only valid for tetra alignments as the low bits are ignored. ++ ++.*: file format mmo ++ ++Contents of section \.text: ++ 0*0 e3fd0001 2a000000 00000000 00000000 .* ++ 0*10 00000000 00000000 00000000 00000000 .* ++#... ++ 0*7ff0 00000000 00000000 00000000 00000000 .* ++ 0*8000 00000000 00000000 00000000 2b2c0000 .* ++ +diff --git a/ld/testsuite/ld-mmix/sec-10.s b/ld/testsuite/ld-mmix/sec-10.s +new file mode 100644 +index 0000000..2729e55 +--- /dev/null ++++ b/ld/testsuite/ld-mmix/sec-10.s +@@ -0,0 +1,8 @@ ++ .section .text.1 ++ .byte 42 ++ .byte 0,0,0,0, 0,0,0,0, 0,0,0,0 ++ ++ .section .text.2 ++ .space 32752 ++ .byte 0,0,0,0, 0,0,0,0, 0,0,0 ++ .byte 43,44,0,0 +diff --git a/ld/testsuite/ld-mmix/sec-11.d b/ld/testsuite/ld-mmix/sec-11.d +new file mode 100644 +index 0000000..3a60934 +--- /dev/null ++++ b/ld/testsuite/ld-mmix/sec-11.d +@@ -0,0 +1,7 @@ ++#source: start.s ++#ld: -m mmo -T$srcdir/$subdir/sec-11.ld ++#error: contents at non-multiple-of-4 address ++ ++# A trivial check that we get a graceful error when trying to emit ++# (loadable, addressable) contents at a misaligned address. Note ++# that e.g. debug sections do not have loadable contents. +diff --git a/ld/testsuite/ld-mmix/sec-11.ld b/ld/testsuite/ld-mmix/sec-11.ld +new file mode 100644 +index 0000000..a36ca1e +--- /dev/null ++++ b/ld/testsuite/ld-mmix/sec-11.ld +@@ -0,0 +1,10 @@ ++OUTPUT_ARCH(mmix) ++ENTRY(Main) ++SECTIONS ++{ ++ .text 0x101 : /* Note the misaligned address; must trig a linker error. */ ++ { *(.text*); Main = _start; } ++ ++ .MMIX.reg_contents : ++ { *(.MMIX.reg_contents.linker_allocated); *(.MMIX.reg_contents); } ++} +diff --git a/ld/testsuite/ld-mmix/sec-12.d b/ld/testsuite/ld-mmix/sec-12.d +new file mode 100644 +index 0000000..720789e +--- /dev/null ++++ b/ld/testsuite/ld-mmix/sec-12.d +@@ -0,0 +1,26 @@ ++#source: b-twoinsn.s ++#source: b-offlocmis.s ++#source: b-post1.s ++#source: b-goodmain.s ++#ld: --oformat binary ++#objdump: -sh ++ ++# Check that a LOP_LOC at a misaligned location followed by a ++# LOP_QUOTE hits the corresponding aligned address. This is a ++# variant of sec-5.d with the lop_loc having a misalignment, followed ++# by another misaligned lop_loc with a lop_quot. ++ ++.*: file format mmo ++ ++Sections: ++Idx Name Size VMA LMA File off Algn ++ 0 \.text 0+8 0+ 0+ 0+ 2\*\*2 ++ CONTENTS, ALLOC, LOAD, CODE ++ 1 \.MMIX\.sec\.0 0+24 789abcdef0123458 789abcdef0123458 0+ 2\*\*2 ++ CONTENTS, ALLOC, LOAD ++Contents of section \.text: ++ 0+ e3fd0001 e3fd0004 .* ++Contents of section \.MMIX\.sec\.0: ++ 789abcdef0123458 b045197d 2c1b03b2 e4dbf877 0fc766fb .* ++ 789abcdef0123468 00000000 00000000 00000000 00000000 .* ++ 789abcdef0123478 12345677 .* diff --git a/ld/testsuite/ld-mmix/sec-2.d b/ld/testsuite/ld-mmix/sec-2.d new file mode 100644 index 0000000..10623f3 @@ -2905332,6 +2920903,160 @@ index 0000000..08e1df1 +0+ g \.text Main +0+ g \*UND\* undefd +0+ g \.text _start +diff --git a/ld/testsuite/ld-mmix/wrap1.d b/ld/testsuite/ld-mmix/wrap1.d +new file mode 100644 +index 0000000..02d7bef +--- /dev/null ++++ b/ld/testsuite/ld-mmix/wrap1.d +@@ -0,0 +1,21 @@ ++#source: start.s ++#source: wrap1a.s ++#source: wrap1b.s ++#source: wrap1c.s ++#ld: -m mmo --wrap deal ++#as: -no-expand ++#objdump: -d ++ ++.*: file format mmo ++ ++Disassembly of section \.text: ++ ++0+ <(_start|Main)>: ++ 0: e3fd0001 setl \$253,0x1 ++ 4: f2000001 pushj \$0,8 <__wrap_deal> ++ ++0+8 <__wrap_deal>: ++ 8: f0000001 jmp c ++ ++0+c : ++ c: fd000000 swym 0,0,0 +diff --git a/ld/testsuite/ld-mmix/wrap1a.s b/ld/testsuite/ld-mmix/wrap1a.s +new file mode 100644 +index 0000000..88a5cd2 +--- /dev/null ++++ b/ld/testsuite/ld-mmix/wrap1a.s +@@ -0,0 +1,2 @@ ++ .text ++ pushj $0,deal +diff --git a/ld/testsuite/ld-mmix/wrap1b.s b/ld/testsuite/ld-mmix/wrap1b.s +new file mode 100644 +index 0000000..367aea0 +--- /dev/null ++++ b/ld/testsuite/ld-mmix/wrap1b.s +@@ -0,0 +1,4 @@ ++ .text ++ .globl __wrap_deal ++__wrap_deal: ++ jmp __real_deal +diff --git a/ld/testsuite/ld-mmix/wrap1c.s b/ld/testsuite/ld-mmix/wrap1c.s +new file mode 100644 +index 0000000..a7678d4 +--- /dev/null ++++ b/ld/testsuite/ld-mmix/wrap1c.s +@@ -0,0 +1,4 @@ ++ .text ++ .globl deal ++deal: ++ swym 0 +diff --git a/ld/testsuite/ld-mmix/wrap2.d b/ld/testsuite/ld-mmix/wrap2.d +new file mode 100644 +index 0000000..49b4d3b +--- /dev/null ++++ b/ld/testsuite/ld-mmix/wrap2.d +@@ -0,0 +1,21 @@ ++#source: start.s ++#source: wrap1a.s ++#source: wrap1b.s ++#source: wrap1c.s ++#ld: -m elf64mmix --wrap deal ++#as: -no-expand ++#objdump: -d ++ ++.*: file format elf64-mmix ++ ++Disassembly of section \.text: ++ ++0+ <(_start|Main)>: ++ 0: e3fd0001 setl \$253,0x1 ++ 4: f2000001 pushj \$0,8 <__wrap_deal> ++ ++0+8 <__wrap_deal>: ++ 8: f0000001 jmp c ++ ++0+c : ++ c: fd000000 swym 0,0,0 +diff --git a/ld/testsuite/ld-mmix/wrap3.d b/ld/testsuite/ld-mmix/wrap3.d +new file mode 100644 +index 0000000..80b20f1 +--- /dev/null ++++ b/ld/testsuite/ld-mmix/wrap3.d +@@ -0,0 +1,21 @@ ++#source: start.s ++#source: wrap3a.s ++#source: wrap3b.s ++#source: wrap1c.s ++#ld: -m mmo ++#as: -no-expand ++#objdump: -d ++ ++.*: file format mmo ++ ++Disassembly of section \.text: ++ ++0+ <(_start|Main)>: ++ 0: e3fd0001 setl \$253,0x1 ++ 4: f2000001 pushj \$0,8 <__wrap_deal> ++ ++0+8 <__wrap_deal>: ++ 8: f0000001 jmp c ++ ++0+c : ++ c: fd000000 swym 0,0,0 +diff --git a/ld/testsuite/ld-mmix/wrap3a.s b/ld/testsuite/ld-mmix/wrap3a.s +new file mode 100644 +index 0000000..7192a93 +--- /dev/null ++++ b/ld/testsuite/ld-mmix/wrap3a.s +@@ -0,0 +1,2 @@ ++ .text ++ pushj $0,__wrap_deal +diff --git a/ld/testsuite/ld-mmix/wrap3b.s b/ld/testsuite/ld-mmix/wrap3b.s +new file mode 100644 +index 0000000..6a8a606 +--- /dev/null ++++ b/ld/testsuite/ld-mmix/wrap3b.s +@@ -0,0 +1,4 @@ ++ .text ++ .globl __wrap_deal ++__wrap_deal: ++ jmp deal +diff --git a/ld/testsuite/ld-mmix/wrap4.d b/ld/testsuite/ld-mmix/wrap4.d +new file mode 100644 +index 0000000..a64578d +--- /dev/null ++++ b/ld/testsuite/ld-mmix/wrap4.d +@@ -0,0 +1,21 @@ ++#source: start.s ++#source: wrap3a.s ++#source: wrap3b.s ++#source: wrap1c.s ++#ld: -m elf64mmix ++#as: -no-expand ++#objdump: -d ++ ++.*: file format elf64-mmix ++ ++Disassembly of section \.text: ++ ++0+ <(_start|Main)>: ++ 0: e3fd0001 setl \$253,0x1 ++ 4: f2000001 pushj \$0,8 <__wrap_deal> ++ ++0+8 <__wrap_deal>: ++ 8: f0000001 jmp c ++ ++0+c : ++ c: fd000000 swym 0,0,0 diff --git a/ld/testsuite/ld-mmix/x.s b/ld/testsuite/ld-mmix/x.s new file mode 100644 index 0000000..e7222b1 @@ -2906054,12 +2921779,12 @@ index 0000000..84c1d83 + .string "\n" diff --git a/ld/testsuite/ld-mn10300/mn10300.exp b/ld/testsuite/ld-mn10300/mn10300.exp new file mode 100644 -index 0000000..8eb666d +index 0000000..213ba39 --- /dev/null +++ b/ld/testsuite/ld-mn10300/mn10300.exp @@ -0,0 +1,163 @@ +# Expect script for ld-mn10300 tests -+# Copyright (C) 2007 Free Software Foundation ++# Copyright (C) 2007-2014 Free Software Foundation, Inc. +# +# This file is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -2906489,11 +2922214,11 @@ index 0000000..1c75db2 +.set imm5, 0xf diff --git a/ld/testsuite/ld-nds32/nds32.exp b/ld/testsuite/ld-nds32/nds32.exp new file mode 100644 -index 0000000..6f95c17 +index 0000000..3102b21 --- /dev/null +++ b/ld/testsuite/ld-nds32/nds32.exp @@ -0,0 +1,26 @@ -+# Copyright (C) 2012-2013 Free Software Foundation, Inc. ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# Contributed by Andes Technology Corporation. + +# This program is free software; you can redistribute it and/or modify @@ -2906950,6 +2922675,441 @@ index 0000000..3a76612 + nop + nop +.global ext_label +diff --git a/ld/testsuite/ld-nios2/relax_call26.s b/ld/testsuite/ld-nios2/relax_call26.s +new file mode 100644 +index 0000000..b3b28df +--- /dev/null ++++ b/ld/testsuite/ld-nios2/relax_call26.s +@@ -0,0 +1,27 @@ ++# test for call26 relaxation via linker stubs ++ ++.globl text0 ++.section text0, "ax", @progbits ++ call func0 # in same section ++ call func1 # in nearby section ++ call func2a # in distant section ++ jmpi func2b # also in distant section ++ ++func0: ++ ret ++ ++.section text1, "ax", @progbits ++func1: ++ nop ++ nop ++ call func2a # in distant section ++ ret ++ ++.section text2, "ax", @progbits ++func2a: ++ nop ++ nop ++ nop ++ ret ++func2b: ++ nop +diff --git a/ld/testsuite/ld-nios2/relax_call26_boundary.ld b/ld/testsuite/ld-nios2/relax_call26_boundary.ld +new file mode 100644 +index 0000000..313ef8c +--- /dev/null ++++ b/ld/testsuite/ld-nios2/relax_call26_boundary.ld +@@ -0,0 +1,14 @@ ++/* Simple script for testing call26 relaxation via linker stubs. ++ This script is used for a bunch of tests that vary the placement of ++ section text0 near a 256 memory segment boundary, by using ++ --section-start command-line options. */ ++ ++OUTPUT_FORMAT("elf32-littlenios2", "elf32-littlenios2", "elf32-littlenios2") ++OUTPUT_ARCH(nios2) ++ENTRY(_start) ++SECTIONS ++{ ++ _start = .; ++ text0 : { *(text0) *(text1) } ++ text2 0x40000000 : { *(text2) } ++} +diff --git a/ld/testsuite/ld-nios2/relax_call26_boundary.s b/ld/testsuite/ld-nios2/relax_call26_boundary.s +new file mode 100644 +index 0000000..ce79ebd +--- /dev/null ++++ b/ld/testsuite/ld-nios2/relax_call26_boundary.s +@@ -0,0 +1,29 @@ ++# Test for call26 relaxation via linker stubs. ++# This .s file is used with several different linker scripts that vary the ++# placement of the sections in the output. ++# Section text0 is 32 bytes long and requires at least 2 linker stubs ++# (12 bytes each) to reach the call destinations in text2. Another stub ++# may be required to reach func0 if the section is laid out so that it crosses ++# a 256MB memory segment boundary. ++ ++.globl text0 ++.section text0, "ax", @progbits ++ call func0 # in same section ++ call func2a # in distant section ++ nop ++ nop ++ nop ++ nop ++ jmpi func2b # in distant section ++ ++func0: ++ ret ++ ++.section text2, "ax", @progbits ++func2a: ++ nop ++ nop ++ nop ++ ret ++func2b: ++ nop +diff --git a/ld/testsuite/ld-nios2/relax_call26_boundary_c8.d b/ld/testsuite/ld-nios2/relax_call26_boundary_c8.d +new file mode 100644 +index 0000000..61fd858 +--- /dev/null ++++ b/ld/testsuite/ld-nios2/relax_call26_boundary_c8.d +@@ -0,0 +1,9 @@ ++#name: NIOS2 relax_call26_boundary_c8 ++#ld: --relax -Trelax_call26_boundary.ld --section-start=text0=0x0fffffc8 ++#source: relax_call26_boundary.s ++#objdump: -dr --prefix-addresses ++# Test relaxation of call26 relocations via linker stubs. We don't need to ++# check the exact layout of stubs for this test, only verify that it ++# links without "relocation truncated to fit" errors. ++ ++#pass +diff --git a/ld/testsuite/ld-nios2/relax_call26_boundary_cc.d b/ld/testsuite/ld-nios2/relax_call26_boundary_cc.d +new file mode 100644 +index 0000000..c3a571a +--- /dev/null ++++ b/ld/testsuite/ld-nios2/relax_call26_boundary_cc.d +@@ -0,0 +1,9 @@ ++#name: NIOS2 relax_call26_boundary_cc ++#ld: --relax -Trelax_call26_boundary.ld --section-start=text0=0x0fffffcc ++#source: relax_call26_boundary.s ++#objdump: -dr --prefix-addresses ++# Test relaxation of call26 relocations via linker stubs. We don't need to ++# check the exact layout of stubs for this test, only verify that it ++# links without "relocation truncated to fit" errors. ++ ++#pass +diff --git a/ld/testsuite/ld-nios2/relax_call26_boundary_d0.d b/ld/testsuite/ld-nios2/relax_call26_boundary_d0.d +new file mode 100644 +index 0000000..67f28ce +--- /dev/null ++++ b/ld/testsuite/ld-nios2/relax_call26_boundary_d0.d +@@ -0,0 +1,9 @@ ++#name: NIOS2 relax_call26_boundary_d0 ++#ld: --relax -Trelax_call26_boundary.ld --section-start=text0=0x0fffffd0 ++#source: relax_call26_boundary.s ++#objdump: -dr --prefix-addresses ++# Test relaxation of call26 relocations via linker stubs. We don't need to ++# check the exact layout of stubs for this test, only verify that it ++# links without "relocation truncated to fit" errors. ++ ++#pass +diff --git a/ld/testsuite/ld-nios2/relax_call26_boundary_d4.d b/ld/testsuite/ld-nios2/relax_call26_boundary_d4.d +new file mode 100644 +index 0000000..9ffdf0e +--- /dev/null ++++ b/ld/testsuite/ld-nios2/relax_call26_boundary_d4.d +@@ -0,0 +1,9 @@ ++#name: NIOS2 relax_call26_boundary_d4 ++#ld: --relax -Trelax_call26_boundary.ld --section-start=text0=0x0fffffd4 ++#source: relax_call26_boundary.s ++#objdump: -dr --prefix-addresses ++# Test relaxation of call26 relocations via linker stubs. We don't need to ++# check the exact layout of stubs for this test, only verify that it ++# links without "relocation truncated to fit" errors. ++ ++#pass +diff --git a/ld/testsuite/ld-nios2/relax_call26_boundary_d8.d b/ld/testsuite/ld-nios2/relax_call26_boundary_d8.d +new file mode 100644 +index 0000000..168d532 +--- /dev/null ++++ b/ld/testsuite/ld-nios2/relax_call26_boundary_d8.d +@@ -0,0 +1,9 @@ ++#name: NIOS2 relax_call26_boundary_d8 ++#ld: --relax -Trelax_call26_boundary.ld --section-start=text0=0x0fffffd8 ++#source: relax_call26_boundary.s ++#objdump: -dr --prefix-addresses ++# Test relaxation of call26 relocations via linker stubs. We don't need to ++# check the exact layout of stubs for this test, only verify that it ++# links without "relocation truncated to fit" errors. ++ ++#pass +diff --git a/ld/testsuite/ld-nios2/relax_call26_boundary_dc.d b/ld/testsuite/ld-nios2/relax_call26_boundary_dc.d +new file mode 100644 +index 0000000..539051e +--- /dev/null ++++ b/ld/testsuite/ld-nios2/relax_call26_boundary_dc.d +@@ -0,0 +1,9 @@ ++#name: NIOS2 relax_call26_boundary_dc ++#ld: --relax -Trelax_call26_boundary.ld --section-start=text0=0x0fffffdc ++#source: relax_call26_boundary.s ++#objdump: -dr --prefix-addresses ++# Test relaxation of call26 relocations via linker stubs. We don't need to ++# check the exact layout of stubs for this test, only verify that it ++# links without "relocation truncated to fit" errors. ++ ++#pass +diff --git a/ld/testsuite/ld-nios2/relax_call26_boundary_f0.d b/ld/testsuite/ld-nios2/relax_call26_boundary_f0.d +new file mode 100644 +index 0000000..fe83151 +--- /dev/null ++++ b/ld/testsuite/ld-nios2/relax_call26_boundary_f0.d +@@ -0,0 +1,9 @@ ++#name: NIOS2 relax_call26_boundary_f0 ++#ld: --relax -Trelax_call26_boundary.ld --section-start=text0=0x0ffffff0 ++#source: relax_call26_boundary.s ++#objdump: -dr --prefix-addresses ++# Test relaxation of call26 relocations via linker stubs. We don't need to ++# check the exact layout of stubs for this test, only verify that it ++# links without "relocation truncated to fit" errors. ++ ++#pass +diff --git a/ld/testsuite/ld-nios2/relax_call26_boundary_f4.d b/ld/testsuite/ld-nios2/relax_call26_boundary_f4.d +new file mode 100644 +index 0000000..4006ff2 +--- /dev/null ++++ b/ld/testsuite/ld-nios2/relax_call26_boundary_f4.d +@@ -0,0 +1,9 @@ ++#name: NIOS2 relax_call26_boundary_f4 ++#ld: --relax -Trelax_call26_boundary.ld --section-start=text0=0x0ffffff4 ++#source: relax_call26_boundary.s ++#objdump: -dr --prefix-addresses ++# Test relaxation of call26 relocations via linker stubs. We don't need to ++# check the exact layout of stubs for this test, only verify that it ++# links without "relocation truncated to fit" errors. ++ ++#pass +diff --git a/ld/testsuite/ld-nios2/relax_call26_boundary_f8.d b/ld/testsuite/ld-nios2/relax_call26_boundary_f8.d +new file mode 100644 +index 0000000..10eb654 +--- /dev/null ++++ b/ld/testsuite/ld-nios2/relax_call26_boundary_f8.d +@@ -0,0 +1,9 @@ ++#name: NIOS2 relax_call26_boundary_f8 ++#ld: --relax -Trelax_call26_boundary.ld --section-start=text0=0x0ffffff8 ++#source: relax_call26_boundary.s ++#objdump: -dr --prefix-addresses ++# Test relaxation of call26 relocations via linker stubs. We don't need to ++# check the exact layout of stubs for this test, only verify that it ++# links without "relocation truncated to fit" errors. ++ ++#pass +diff --git a/ld/testsuite/ld-nios2/relax_call26_boundary_fc.d b/ld/testsuite/ld-nios2/relax_call26_boundary_fc.d +new file mode 100644 +index 0000000..cf93b5a +--- /dev/null ++++ b/ld/testsuite/ld-nios2/relax_call26_boundary_fc.d +@@ -0,0 +1,9 @@ ++#name: NIOS2 relax_call26_boundary_fc ++#ld: --relax -Trelax_call26_boundary.ld --section-start=text0=0x0ffffffc ++#source: relax_call26_boundary.s ++#objdump: -dr --prefix-addresses ++# Test relaxation of call26 relocations via linker stubs. We don't need to ++# check the exact layout of stubs for this test, only verify that it ++# links without "relocation truncated to fit" errors. ++ ++#pass +diff --git a/ld/testsuite/ld-nios2/relax_call26_cache.d b/ld/testsuite/ld-nios2/relax_call26_cache.d +new file mode 100644 +index 0000000..43121c0 +--- /dev/null ++++ b/ld/testsuite/ld-nios2/relax_call26_cache.d +@@ -0,0 +1,9 @@ ++#name: NIOS2 relax_call26_cache ++#ld: --relax -Trelax_call26_cache.ld ++#source: relax_call26_cache.s ++#objdump: -dr --prefix-addresses ++# Test relaxation of call26 relocations via linker stubs. We don't need to ++# check the exact layout of stubs for this test, only verify that it ++# links without "relocation truncated to fit" errors. ++ ++#pass +diff --git a/ld/testsuite/ld-nios2/relax_call26_cache.ld b/ld/testsuite/ld-nios2/relax_call26_cache.ld +new file mode 100644 +index 0000000..d3c4307 +--- /dev/null ++++ b/ld/testsuite/ld-nios2/relax_call26_cache.ld +@@ -0,0 +1,13 @@ ++/* Simple script for testing call26 relaxation via linker stubs. ++ In this case, input sections text0 and text1 are placed in the ++ same output section in the same 256MB segment, so they can share stubs. */ ++ ++OUTPUT_FORMAT("elf32-littlenios2", "elf32-littlenios2", "elf32-littlenios2") ++OUTPUT_ARCH(nios2) ++ENTRY(_start) ++SECTIONS ++{ ++ _start = .; ++ text0 0x0fffffe0 : { *(text0) *(text1) } ++ text2 0x40000000 : { *(text2) } ++} +diff --git a/ld/testsuite/ld-nios2/relax_call26_cache.s b/ld/testsuite/ld-nios2/relax_call26_cache.s +new file mode 100644 +index 0000000..3712853 +--- /dev/null ++++ b/ld/testsuite/ld-nios2/relax_call26_cache.s +@@ -0,0 +1,28 @@ ++# test for call26 relaxation via linker stubs ++# ++# The purpose of this test is to ensure that, when section text0 straddles ++# a 256MB memory segment boundary with calls to the same function on either ++# side, the stub caching doesn't get confused and incorrectly use a stub ++# on the wrong side. ++ ++.globl text0 ++.section text0, "ax", @progbits ++ call func2a # in distant section ++ call func2a # in distant section ++ nop ++ nop ++ nop ++ nop ++ nop ++ nop ++ nop ++ nop ++ nop ++ nop ++ call func2a # in distant section ++ call func2a # in distant section ++ ++.section text2, "ax", @progbits ++.globl func2a ++func2a: ++ ret +diff --git a/ld/testsuite/ld-nios2/relax_call26_multi.d b/ld/testsuite/ld-nios2/relax_call26_multi.d +new file mode 100644 +index 0000000..28279ef +--- /dev/null ++++ b/ld/testsuite/ld-nios2/relax_call26_multi.d +@@ -0,0 +1,36 @@ ++#name: NIOS2 relax_call26_multi ++#ld: --relax -Trelax_call26_multi.ld ++#source: relax_call26.s ++#objdump: -dr --prefix-addresses ++# Test relaxation of call26 relocations via linker stubs ++ ++.*: +file format elf32-littlenios2 ++ ++Disassembly of section text0: ++00000000 <_start> call 00000010 ++00000004 <[^>]*> call 0000002c ++00000008 <[^>]*> call 00000020 <[^>]*> ++0000000c <[^>]*> jmpi 00000014 <[^>]*> ++00000010 ret ++00000014 <[^>]*> movhi at,16384 ++00000018 <[^>]*> addi at,at,16 ++0000001c <[^>]*> jmp at ++00000020 <[^>]*> movhi at,16384 ++00000024 <[^>]*> addi at,at,0 ++00000028 <[^>]*> jmp at ++ ++Disassembly of section text1: ++0000002c nop ++00000030 <[^>]*> nop ++00000034 <[^>]*> call 0000003c <[^>]*> ++00000038 <[^>]*> ret ++0000003c <[^>]*> movhi at,16384 ++00000040 <[^>]*> addi at,at,0 ++00000044 <[^>]*> jmp at ++ ++Disassembly of section text2: ++40000000 nop ++40000004 <[^>]*> nop ++40000008 <[^>]*> nop ++4000000c <[^>]*> ret ++40000010 nop +diff --git a/ld/testsuite/ld-nios2/relax_call26_multi.ld b/ld/testsuite/ld-nios2/relax_call26_multi.ld +new file mode 100644 +index 0000000..750f747 +--- /dev/null ++++ b/ld/testsuite/ld-nios2/relax_call26_multi.ld +@@ -0,0 +1,14 @@ ++/* Simple script for testing call26 relaxation via linker stubs. ++ In this case, input sections text0 and text1 cannot share stubs ++ because they are in different output sections. */ ++ ++OUTPUT_FORMAT("elf32-littlenios2", "elf32-littlenios2", "elf32-littlenios2") ++OUTPUT_ARCH(nios2) ++ENTRY(_start) ++SECTIONS ++{ ++ _start = .; ++ text0 0 : { *(text0) } ++ text1 : { *(text1) } ++ text2 0x40000000 : { *(text2) } ++} +diff --git a/ld/testsuite/ld-nios2/relax_call26_norelax.d b/ld/testsuite/ld-nios2/relax_call26_norelax.d +new file mode 100644 +index 0000000..7c7371c +--- /dev/null ++++ b/ld/testsuite/ld-nios2/relax_call26_norelax.d +@@ -0,0 +1,5 @@ ++#name: NIOS2 relax_call26_norelax ++#ld: --no-relax -Trelax_call26_multi.ld ++#source: relax_call26.s ++#error: .*relocation truncated to fit: R_NIOS2_CALL26.* ++# Test relaxation of call26 relocations via linker stubs +diff --git a/ld/testsuite/ld-nios2/relax_call26_shared.d b/ld/testsuite/ld-nios2/relax_call26_shared.d +new file mode 100644 +index 0000000..75ccbca +--- /dev/null ++++ b/ld/testsuite/ld-nios2/relax_call26_shared.d +@@ -0,0 +1,31 @@ ++#name: NIOS2 relax_call26_shared ++#ld: --relax -Trelax_call26_shared.ld ++#source: relax_call26.s ++#objdump: -dr --prefix-addresses ++# Test relaxation of call26 relocations via linker stubs ++ ++.*: +file format elf32-littlenios2 ++ ++Disassembly of section text0: ++00000000 <_start> call 00000010 ++00000004 <[^>]*> call 00000014 ++00000008 <[^>]*> call 00000030 <[^>]*> ++0000000c <[^>]*> jmpi 00000024 <[^>]*> ++00000010 ret ++00000014 nop ++00000018 <[^>]*> nop ++0000001c <[^>]*> call 00000030 <[^>]*> ++00000020 <[^>]*> ret ++00000024 <[^>]*> movhi at,16384 ++00000028 <[^>]*> addi at,at,16 ++0000002c <[^>]*> jmp at ++00000030 <[^>]*> movhi at,16384 ++00000034 <[^>]*> addi at,at,0 ++00000038 <[^>]*> jmp at ++ ++Disassembly of section text2: ++40000000 nop ++40000004 <[^>]*> nop ++40000008 <[^>]*> nop ++4000000c <[^>]*> ret ++40000010 nop +diff --git a/ld/testsuite/ld-nios2/relax_call26_shared.ld b/ld/testsuite/ld-nios2/relax_call26_shared.ld +new file mode 100644 +index 0000000..6e6fd44 +--- /dev/null ++++ b/ld/testsuite/ld-nios2/relax_call26_shared.ld +@@ -0,0 +1,13 @@ ++/* Simple script for testing call26 relaxation via linker stubs. ++ In this case, input sections text0 and text1 are placed in the ++ same output section in the same 256MB segment, so they can share stubs. */ ++ ++OUTPUT_FORMAT("elf32-littlenios2", "elf32-littlenios2", "elf32-littlenios2") ++OUTPUT_ARCH(nios2) ++ENTRY(_start) ++SECTIONS ++{ ++ _start = .; ++ text0 0 : { *(text0) *(text1) } ++ text2 0x40000000 : { *(text2) } ++} diff --git a/ld/testsuite/ld-nios2/relax_callr.d b/ld/testsuite/ld-nios2/relax_callr.d new file mode 100644 index 0000000..7d40fe4 @@ -2907956,7 +2924116,7 @@ index 0000000..f646eca +} diff --git a/ld/testsuite/ld-pe/longsecn-1.d b/ld/testsuite/ld-pe/longsecn-1.d new file mode 100644 -index 0000000..95b3337 +index 0000000..81a44a7 --- /dev/null +++ b/ld/testsuite/ld-pe/longsecn-1.d @@ -0,0 +1,22 @@ @@ -2907981,13 +2924141,13 @@ index 0000000..95b3337 + CONTENTS, ALLOC, LOAD, DATA + 5 \.idata [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9] + CONTENTS, ALLOC, LOAD, DATA -+ ++#... diff --git a/ld/testsuite/ld-pe/longsecn-2.d b/ld/testsuite/ld-pe/longsecn-2.d new file mode 100644 -index 0000000..8170006 +index 0000000..64d1627 --- /dev/null +++ b/ld/testsuite/ld-pe/longsecn-2.d -@@ -0,0 +1,21 @@ +@@ -0,0 +1,22 @@ +#name: PE-COFF Long section names (enabled) +#ld: --enable-long-section-names +#objdump: -h @@ -2908009,12 +2924169,13 @@ index 0000000..8170006 + CONTENTS, ALLOC, LOAD, DATA + 5 \.idata [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9] + CONTENTS, ALLOC, LOAD, DATA ++#... diff --git a/ld/testsuite/ld-pe/longsecn-3.d b/ld/testsuite/ld-pe/longsecn-3.d new file mode 100644 -index 0000000..0317be3 +index 0000000..c86a828 --- /dev/null +++ b/ld/testsuite/ld-pe/longsecn-3.d -@@ -0,0 +1,41 @@ +@@ -0,0 +1,40 @@ +#name: PE-COFF Long section names in objects (default) +#ld: -r +#objdump: -h @@ -2908054,14 +2924215,13 @@ index 0000000..0317be3 + CONTENTS, ALLOC, LOAD, DATA + 14 \.rodata\.very\.long\.section\$1234 [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9] + CONTENTS, ALLOC, LOAD, DATA -+ 15 \.(bss |text) [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9] -+ (ALLOC|CONTENTS, ALLOC, LOAD, (READONLY, )?CODE) ++#... diff --git a/ld/testsuite/ld-pe/longsecn-4.d b/ld/testsuite/ld-pe/longsecn-4.d new file mode 100644 -index 0000000..565ef38 +index 0000000..e326d98 --- /dev/null +++ b/ld/testsuite/ld-pe/longsecn-4.d -@@ -0,0 +1,41 @@ +@@ -0,0 +1,40 @@ +#name: PE-COFF Long section names in objects (disabled) +#ld: --disable-long-section-names -r +#objdump: -h @@ -2908101,14 +2924261,13 @@ index 0000000..565ef38 + CONTENTS, ALLOC, LOAD, DATA + 14 \.rodata\. [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9] + CONTENTS, ALLOC, LOAD, DATA -+ 15 \.(bss |text) [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9] -+ (ALLOC|CONTENTS, ALLOC, LOAD, (READONLY, )?CODE) ++#... diff --git a/ld/testsuite/ld-pe/longsecn-5.d b/ld/testsuite/ld-pe/longsecn-5.d new file mode 100644 -index 0000000..82d94b8 +index 0000000..f3ef22b --- /dev/null +++ b/ld/testsuite/ld-pe/longsecn-5.d -@@ -0,0 +1,41 @@ +@@ -0,0 +1,40 @@ +#name: PE-COFF Long section names in objects (enabled) +#ld: --enable-long-section-names -r +#objdump: -h @@ -2908148,11 +2924307,10 @@ index 0000000..82d94b8 + CONTENTS, ALLOC, LOAD, DATA + 14 \.rodata\.very\.long\.section\$1234 [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9] + CONTENTS, ALLOC, LOAD, DATA -+ 15 \.(bss |text) [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9] -+ (ALLOC|CONTENTS, ALLOC, LOAD, (READONLY, )?CODE) ++#... diff --git a/ld/testsuite/ld-pe/longsecn.d b/ld/testsuite/ld-pe/longsecn.d new file mode 100644 -index 0000000..2dcde35 +index 0000000..e77f6ee --- /dev/null +++ b/ld/testsuite/ld-pe/longsecn.d @@ -0,0 +1,22 @@ @@ -2908177,7 +2924335,7 @@ index 0000000..2dcde35 + CONTENTS, ALLOC, LOAD, DATA + 5 \.idata [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ [0-9a-fA-F]+ 2\*\*[0-9] + CONTENTS, ALLOC, LOAD, DATA -+ ++#... diff --git a/ld/testsuite/ld-pe/longsecn.s b/ld/testsuite/ld-pe/longsecn.s new file mode 100644 index 0000000..1fc4da3 @@ -2908246,11 +2924404,10 @@ index 0000000..3c7fa93 +#... diff --git a/ld/testsuite/ld-pe/non-c-lang-syms.s b/ld/testsuite/ld-pe/non-c-lang-syms.s new file mode 100644 -index 0000000..e849d9e +index 0000000..28006a1 --- /dev/null +++ b/ld/testsuite/ld-pe/non-c-lang-syms.s -@@ -0,0 +1,15 @@ -+ +@@ -0,0 +1,14 @@ +main: +_main: + nop @@ -2908319,13 +2924476,15 @@ index 0000000..6510491 + .space 16 diff --git a/ld/testsuite/ld-pe/orphana_nu.s b/ld/testsuite/ld-pe/orphana_nu.s new file mode 100644 -index 0000000..d3c564f +index 0000000..618789c --- /dev/null +++ b/ld/testsuite/ld-pe/orphana_nu.s -@@ -0,0 +1,8 @@ +@@ -0,0 +1,10 @@ ++ .globl _mainCRTStartup + .globl mainCRTStartup + .globl start + .text ++_mainCRTStartup: +mainCRTStartup: +start: + @@ -2908357,14 +2924516,13 @@ index 0000000..aff3e84 + .long 4,4,4,4 diff --git a/ld/testsuite/ld-pe/pe-compile.exp b/ld/testsuite/ld-pe/pe-compile.exp new file mode 100644 -index 0000000..750f5c0 +index 0000000..ccc8516 --- /dev/null +++ b/ld/testsuite/ld-pe/pe-compile.exp -@@ -0,0 +1,143 @@ +@@ -0,0 +1,142 @@ +# Expect script for complex PE tests that require a C compiler +# in addition to the just-built binutils. -+# Copyright 2009 -+# Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2908506,14 +2924664,13 @@ index 0000000..750f5c0 +run_ld_link_tests $align_tests diff --git a/ld/testsuite/ld-pe/pe-run.exp b/ld/testsuite/ld-pe/pe-run.exp new file mode 100644 -index 0000000..709fb19 +index 0000000..fb82340 --- /dev/null +++ b/ld/testsuite/ld-pe/pe-run.exp -@@ -0,0 +1,149 @@ +@@ -0,0 +1,148 @@ +# Expect script for complex PE tests that require a C compiler and the ability +# to run target executables natively, in addition to the just-built binutils. -+# Copyright 2006, 2007, 2009 -+# Free Software Foundation, Inc. ++# Copyright (C) 2006-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2908661,14 +2924818,13 @@ index 0000000..709fb19 +directdll_execute "$tmpdir/direct_client_symlink_dll.exe" "running direct linked dll (symlink -> .dll)" diff --git a/ld/testsuite/ld-pe/pe-run2.exp b/ld/testsuite/ld-pe/pe-run2.exp new file mode 100644 -index 0000000..6cc066e +index 0000000..ab580d3 --- /dev/null +++ b/ld/testsuite/ld-pe/pe-run2.exp -@@ -0,0 +1,151 @@ +@@ -0,0 +1,150 @@ +# Expect script for complex PE tests that require a C compiler and the ability +# to run target executables natively, in addition to the just-built binutils. -+# Copyright 2006, 2007, 2009 -+# Free Software Foundation, Inc. ++# Copyright (C) 2006-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2908818,13 +2924974,12 @@ index 0000000..6cc066e +directdll_execute "$tmpdir/direct2_client_symlink_dll.exe" "running direct linked dll (symlink -> .dll) fastcall/stdcall" diff --git a/ld/testsuite/ld-pe/pe.exp b/ld/testsuite/ld-pe/pe.exp new file mode 100644 -index 0000000..df26f6d +index 0000000..6fdfb79 --- /dev/null +++ b/ld/testsuite/ld-pe/pe.exp -@@ -0,0 +1,91 @@ +@@ -0,0 +1,90 @@ +# Expect script for simple PE tests that require the just-built binutils only. -+# Copyright 2004, 2005, 2006, 2007, 2009 -+# Free Software Foundation, Inc. ++# Copyright (C) 2004-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2908915,176 +2925070,177 @@ index 0000000..df26f6d +run_ld_link_tests $foreign_sym_test diff --git a/ld/testsuite/ld-pe/secrel.d b/ld/testsuite/ld-pe/secrel.d new file mode 100644 -index 0000000..d0537ee +index 0000000..3f1bb4a --- /dev/null +++ b/ld/testsuite/ld-pe/secrel.d -@@ -0,0 +1,27 @@ -+ -+tmpdir/secrel\.x: +file format pei-.* -+ -+Contents of section \.text: -+ .*1000 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c >>>><<<<>>>>><<< -+ .*1010 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c >>>>>><<>>>>>>>< -+ .*1020 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c >>>><<<<>>>>><<< -+ .*1030 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c >>>>>><<>>>>>>>< -+ .*1040 ........ ........ ........ ........ ................ -+Contents of section \.data: -+ .*2000 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c >>>><<<<>>>>><<< -+ .*2010 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c >>>>>><<>>>>>>>< -+ .*2020 3e3e3e3e 04000000 110d0000 00111600 >>>>............ -+ .*2030 0000111f 00000011 3c3c3c3c 3c3c3c3c ........<<<<<<<< -+ .*2040 3e3e3e3e 04000000 110d0000 00111600 >>>>............ -+ .*2050 0000111f 00000011 3c3c3c3c 3c3c3c3c ........<<<<<<<< -+ .*2060 3e3e3e3e 04000000 110d0000 00111600 >>>>............ -+ .*2070 0000111f 00000011 3c3c3c3c 3c3c3c3c ........<<<<<<<< -+ .*2080 3e3e3e3e 24000000 112d0000 00113600 >>>>\$....-....6. -+ .*2090 0000113f 00000011 3c3c3c3c 3c3c3c3c ...\?....<<<<<<<< -+Contents of section \.rdata: -+ .*3000 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c >>>><<<<>>>>><<< -+ .*3010 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c >>>>>><<>>>>>>>< -+ .*3020 3e3e3e3e 00000000 00000000 00000000 >>>>............ -+Contents of section \.idata: -+ .*4000 00000000 00000000 00000000 00000000 ................ -+ .*4010 00000000 .... +@@ -0,0 +1,28 @@ ++ ++tmpdir/secrel\.x: +file format pei-.* ++ ++Contents of section \.text: ++ .*1000 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c >>>><<<<>>>>><<< ++ .*1010 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c >>>>>><<>>>>>>>< ++ .*1020 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c >>>><<<<>>>>><<< ++ .*1030 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c >>>>>><<>>>>>>>< ++ .*1040 ........ ........ ........ ........ ................ ++Contents of section \.data: ++ .*2000 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c >>>><<<<>>>>><<< ++ .*2010 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c >>>>>><<>>>>>>>< ++ .*2020 3e3e3e3e 04000000 110d0000 00111600 >>>>............ ++ .*2030 0000111f 00000011 3c3c3c3c 3c3c3c3c ........<<<<<<<< ++ .*2040 3e3e3e3e 04000000 110d0000 00111600 >>>>............ ++ .*2050 0000111f 00000011 3c3c3c3c 3c3c3c3c ........<<<<<<<< ++ .*2060 3e3e3e3e 04000000 110d0000 00111600 >>>>............ ++ .*2070 0000111f 00000011 3c3c3c3c 3c3c3c3c ........<<<<<<<< ++ .*2080 3e3e3e3e 24000000 112d0000 00113600 >>>>\$....-....6. ++ .*2090 0000113f 00000011 3c3c3c3c 3c3c3c3c ...\?....<<<<<<<< ++Contents of section \.rdata: ++ .*3000 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c >>>><<<<>>>>><<< ++ .*3010 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c >>>>>><<>>>>>>>< ++ .*3020 3e3e3e3e 00000000 00000000 00000000 >>>>............ ++Contents of section \.idata: ++ .*4000 00000000 00000000 00000000 00000000 ................ ++ .*4010 00000000 .... ++#... diff --git a/ld/testsuite/ld-pe/secrel1.s b/ld/testsuite/ld-pe/secrel1.s new file mode 100644 -index 0000000..4453b11 +index 0000000..c162990 --- /dev/null +++ b/ld/testsuite/ld-pe/secrel1.s @@ -0,0 +1,79 @@ -+.text -+ -+ .ascii ">>>>" -+pre04: .ascii "<<<<" -+ .ascii ">>>>>" -+pre0d: .ascii "<<<" -+ .ascii ">>>>>>" -+pre16: .ascii "<<" -+ .ascii ">>>>>>>" -+pre1f: .ascii "<" -+ -+.data -+ -+ .ascii ">>>>" -+sam04: .ascii "<<<<" -+ .ascii ">>>>>" -+sam0d: .ascii "<<<" -+ .ascii ">>>>>>" -+sam16: .ascii "<<" -+ .ascii ">>>>>>>" -+sam1f: .ascii "<" -+ -+ .ascii ">>>>" -+ .secrel32 pre04 -+ .byte 0x11 -+ .secrel32 pre0d -+ .byte 0x11 -+ .secrel32 pre16 -+ .byte 0x11 -+ .secrel32 pre1f -+ .byte 0x11 -+ .ascii "<<<<<<<<" -+ -+ .ascii ">>>>" -+ .secrel32 sam04 -+ .byte 0x11 -+ .secrel32 sam0d -+ .byte 0x11 -+ .secrel32 sam16 -+ .byte 0x11 -+ .secrel32 sam1f -+ .byte 0x11 -+ .ascii "<<<<<<<<" -+ -+ .ascii ">>>>" -+ .secrel32 nex04 -+ .byte 0x11 -+ .secrel32 nex0d -+ .byte 0x11 -+ .secrel32 nex16 -+ .byte 0x11 -+ .secrel32 nex1f -+ .byte 0x11 -+ .ascii "<<<<<<<<" -+ -+ .ascii ">>>>" -+ .secrel32 ext24 -+ .byte 0x11 -+ .secrel32 ext2d -+ .byte 0x11 -+ .secrel32 ext36 -+ .byte 0x11 -+ .secrel32 ext3f -+ .byte 0x11 -+ .ascii "<<<<<<<<" -+ -+.section .rdata -+ -+ .ascii ">>>>" -+nex04: .ascii "<<<<" -+ .ascii ">>>>>" -+nex0d: .ascii "<<<" -+ .ascii ">>>>>>" -+nex16: .ascii "<<" -+ .ascii ">>>>>>>" -+nex1f: .ascii "<" -+ .ascii ">>>>" -+ -+ .p2align 4,0 ++.text ++ ++ .ascii ">>>>" ++pre04: .ascii "<<<<" ++ .ascii ">>>>>" ++pre0d: .ascii "<<<" ++ .ascii ">>>>>>" ++pre16: .ascii "<<" ++ .ascii ">>>>>>>" ++pre1f: .ascii "<" ++ ++.data ++ ++ .ascii ">>>>" ++sam04: .ascii "<<<<" ++ .ascii ">>>>>" ++sam0d: .ascii "<<<" ++ .ascii ">>>>>>" ++sam16: .ascii "<<" ++ .ascii ">>>>>>>" ++sam1f: .ascii "<" ++ ++ .ascii ">>>>" ++ .secrel32 pre04 ++ .byte 0x11 ++ .secrel32 pre0d ++ .byte 0x11 ++ .secrel32 pre16 ++ .byte 0x11 ++ .secrel32 pre1f ++ .byte 0x11 ++ .ascii "<<<<<<<<" ++ ++ .ascii ">>>>" ++ .secrel32 sam04 ++ .byte 0x11 ++ .secrel32 sam0d ++ .byte 0x11 ++ .secrel32 sam16 ++ .byte 0x11 ++ .secrel32 sam1f ++ .byte 0x11 ++ .ascii "<<<<<<<<" ++ ++ .ascii ">>>>" ++ .secrel32 nex04 ++ .byte 0x11 ++ .secrel32 nex0d ++ .byte 0x11 ++ .secrel32 nex16 ++ .byte 0x11 ++ .secrel32 nex1f ++ .byte 0x11 ++ .ascii "<<<<<<<<" ++ ++ .ascii ">>>>" ++ .secrel32 ext24 ++ .byte 0x11 ++ .secrel32 ext2d ++ .byte 0x11 ++ .secrel32 ext36 ++ .byte 0x11 ++ .secrel32 ext3f ++ .byte 0x11 ++ .ascii "<<<<<<<<" ++ ++.section .rdata ++ ++ .ascii ">>>>" ++nex04: .ascii "<<<<" ++ .ascii ">>>>>" ++nex0d: .ascii "<<<" ++ .ascii ">>>>>>" ++nex16: .ascii "<<" ++ .ascii ">>>>>>>" ++nex1f: .ascii "<" ++ .ascii ">>>>" ++ ++ .p2align 4,0 diff --git a/ld/testsuite/ld-pe/secrel2.s b/ld/testsuite/ld-pe/secrel2.s new file mode 100644 -index 0000000..4bc4a52 +index 0000000..a1f871f --- /dev/null +++ b/ld/testsuite/ld-pe/secrel2.s @@ -0,0 +1,14 @@ -+.text -+ -+ .ascii ">>>>" -+.global ext24 -+ext24: .ascii "<<<<" -+ .ascii ">>>>>" -+.global ext2d -+ext2d: .ascii "<<<" -+ .ascii ">>>>>>" -+.global ext36 -+ext36: .ascii "<<" -+ .ascii ">>>>>>>" -+.global ext3f -+ext3f: .ascii "<" ++.text ++ ++ .ascii ">>>>" ++.global ext24 ++ext24: .ascii "<<<<" ++ .ascii ">>>>>" ++.global ext2d ++ext2d: .ascii "<<<" ++ .ascii ">>>>>>" ++.global ext36 ++ext36: .ascii "<<" ++ .ascii ">>>>>>>" ++.global ext3f ++ext3f: .ascii "<" diff --git a/ld/testsuite/ld-pe/secrel_64.d b/ld/testsuite/ld-pe/secrel_64.d new file mode 100644 -index 0000000..4f1da93 +index 0000000..aba1bf1 --- /dev/null +++ b/ld/testsuite/ld-pe/secrel_64.d @@ -0,0 +1,28 @@ -+ -+tmpdir/secrel\.x: +file format pei-.* -+ -+Contents of section \.text: -+ .*1000 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c >>>><<<<>>>>><<< -+ .*1010 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c >>>>>><<>>>>>>>< -+ .*1020 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c >>>><<<<>>>>><<< -+ .*1030 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c >>>>>><<>>>>>>>< -+ .*1040 ffffffff ffffffff 00000000 00000000 ................ -+ .*1050 ffffffff ffffffff 00000000 00000000 ................ -+Contents of section \.data: -+ .*2000 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c >>>><<<<>>>>><<< -+ .*2010 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c >>>>>><<>>>>>>>< -+ .*2020 3e3e3e3e 04000000 110d0000 00111600 >>>>............ -+ .*2030 0000111f 00000011 3c3c3c3c 3c3c3c3c ........<<<<<<<< -+ .*2040 3e3e3e3e 04000000 110d0000 00111600 >>>>............ -+ .*2050 0000111f 00000011 3c3c3c3c 3c3c3c3c ........<<<<<<<< -+ .*2060 3e3e3e3e 04000000 110d0000 00111600 >>>>............ -+ .*2070 0000111f 00000011 3c3c3c3c 3c3c3c3c ........<<<<<<<< -+ .*2080 3e3e3e3e 24000000 112d0000 00113600 >>>>\$....-....6. -+ .*2090 0000113f 00000011 3c3c3c3c 3c3c3c3c ...\?....<<<<<<<< -+Contents of section \.rdata: -+ .*3000 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c >>>><<<<>>>>><<< -+ .*3010 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c >>>>>><<>>>>>>>< -+ .*3020 3e3e3e3e 00000000 00000000 00000000 >>>>............ -+Contents of section \.idata: -+ .*4000 00000000 00000000 00000000 00000000 ................ -+ .*4010 00000000 .... ++ ++tmpdir/secrel\.x: +file format pei-.* ++ ++Contents of section \.text: ++ .*1000 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c >>>><<<<>>>>><<< ++ .*1010 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c >>>>>><<>>>>>>>< ++ .*1020 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c >>>><<<<>>>>><<< ++ .*1030 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c >>>>>><<>>>>>>>< ++ .*1040 ffffffff ffffffff 00000000 00000000 ................ ++ .*1050 ffffffff ffffffff 00000000 00000000 ................ ++Contents of section \.data: ++ .*2000 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c >>>><<<<>>>>><<< ++ .*2010 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c >>>>>><<>>>>>>>< ++ .*2020 3e3e3e3e 04000000 110d0000 00111600 >>>>............ ++ .*2030 0000111f 00000011 3c3c3c3c 3c3c3c3c ........<<<<<<<< ++ .*2040 3e3e3e3e 04000000 110d0000 00111600 >>>>............ ++ .*2050 0000111f 00000011 3c3c3c3c 3c3c3c3c ........<<<<<<<< ++ .*2060 3e3e3e3e 04000000 110d0000 00111600 >>>>............ ++ .*2070 0000111f 00000011 3c3c3c3c 3c3c3c3c ........<<<<<<<< ++ .*2080 3e3e3e3e 24000000 112d0000 00113600 >>>>\$....-....6. ++ .*2090 0000113f 00000011 3c3c3c3c 3c3c3c3c ...\?....<<<<<<<< ++Contents of section \.rdata: ++ .*3000 3e3e3e3e 3c3c3c3c 3e3e3e3e 3e3c3c3c >>>><<<<>>>>><<< ++ .*3010 3e3e3e3e 3e3e3c3c 3e3e3e3e 3e3e3e3c >>>>>><<>>>>>>>< ++ .*3020 3e3e3e3e 00000000 00000000 00000000 >>>>............ ++Contents of section \.idata: ++ .*4000 00000000 00000000 00000000 00000000 ................ ++ .*4010 00000000 .... diff --git a/ld/testsuite/ld-pe/tlssec.s b/ld/testsuite/ld-pe/tlssec.s new file mode 100644 index 0000000..ba14881 @@ -2909684,12 +2925840,12 @@ index 0000000..a9bce4a +} diff --git a/ld/testsuite/ld-pie/pie.exp b/ld/testsuite/ld-pie/pie.exp new file mode 100644 -index 0000000..15bd638 +index 0000000..f939107 --- /dev/null +++ b/ld/testsuite/ld-pie/pie.exp @@ -0,0 +1,51 @@ +# Expect script for various PIE tests. -+# Copyright 2006, 2007, 2009, 2010, 2012 Free Software Foundation, Inc. ++# Copyright (C) 2006-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2910576,13 +2926732,12 @@ index 0000000..4b5bcf8 +#... diff --git a/ld/testsuite/ld-plugin/lto.exp b/ld/testsuite/ld-plugin/lto.exp new file mode 100644 -index 0000000..69946de +index 0000000..6ff474e --- /dev/null +++ b/ld/testsuite/ld-plugin/lto.exp -@@ -0,0 +1,354 @@ +@@ -0,0 +1,364 @@ +# Expect script for ld-plugin LTO tests -+# Copyright 2011, 2012, 2013 -+# Free Software Foundation, Inc. ++# Copyright (C) 2011-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2910611,8 +2926766,8 @@ index 0000000..69946de +global CXXFLAGS +set saved_CFLAGS "$CFLAGS" +set saved_CXXFLAGS "$CXXFLAGS" -+regsub -all "\\-Wp,-D_FORTIFY_SOURCE=\[0-9\]+" $CFLAGS "" CFLAGS -+regsub -all "\\-Wp,-D_FORTIFY_SOURCE=\[0-9\]+" $CXXFLAGS "" CXXFLAGS ++regsub -all "(\\-Wp,)?-D_FORTIFY_SOURCE=\[0-9\]+" $CFLAGS "" CFLAGS ++regsub -all "(\\-Wp,)?-D_FORTIFY_SOURCE=\[0-9\]+" $CXXFLAGS "" CXXFLAGS + +proc restore_notify { } { + global saved_CFLAGS @@ -2910652,7 +2926807,7 @@ index 0000000..69946de + {lto-6.c} {} "lto-6.exe" "c"} + {"Build libdummy.a 9" + "" "-O2 -finline -flto" -+ {lto-9.cc} {} "libdummy.a"} ++ {lto-9.cc} {} "libdummy.a" "c++"} + {"Build libdummy.a 11a" + "" "-O -flto" + {lto-11a.c} {} "libdummy.a"} @@ -2910688,7 +2926843,7 @@ index 0000000..69946de + {lto-15b.c} {} "liblto-15.a"} + {"PR ld/12696" + "-O2 -flto -fuse-linker-plugin -r -nostdlib" "-O2 -flto" -+ {pr12696-1.cc} {} "pr12696-1r.o" "c"} ++ {pr12696-1.cc} {} "pr12696-1r.o" "c++"} + {"Build libdummy.a PR ld/12758" + "" "" + {pr12758a.s} {} "libdummy.a"} @@ -2910699,14 +2926854,14 @@ index 0000000..69946de + "-O2 -Wl,-e,foo -nostdlib -flto -fuse-linker-plugin tmpdir/pr12758a.o -Wl,--start-group tmpdir/libpr12758.a -Wl,--end-group" "" + {dummy.c} {} "pr12758.exe"} + {"Build libdummy.a PR ld/12760" -+ "" "" ++ "" "-g -O0" + {pr12760a.c} {} "libdummy.a"} + {"Build libpr12760.a" + "" "-flto -O2 -ffat-lto-objects" + {pr12760b.c} {} "libpr12760.a"} + {"PR ld/12760" + "-O2 -Wl,-e,foo -nostdlib -flto -fuse-linker-plugin tmpdir/pr12760a.o -Wl,--start-group tmpdir/libpr12760.a -Wl,--end-group" "" -+ {dummy.c} {} "pr12760.exe" "c" "warning: Bad bar"} ++ {dummy.c} {} "pr12760.exe" "c" "pr12760a.c:6: warning: Bad bar"} + {"Build libpr13183.a" + "-T" "-flto -O2 -ffat-lto-objects" + {pr13183a.c} {} "libpr13183.a"} @@ -2910722,6 +2926877,18 @@ index 0000000..69946de + {"PR ld/15323" + "" "-O2" + {pr15323a.c} {} "libdummy.a" "c"} ++ {"Build libdummy.a(1) PR ld/pr16846" ++ "" "-flto" ++ {pr16846a.c pr16846b.c} {} "libdummy.a"} ++ {"Build libdummy.a(2) PR ld/pr16846" ++ "" "" ++ {pr16846c.c} {} "libdummy.a"} ++ {"PR ld/pr16846(1)" ++ "-flto -fuse-linker-plugin tmpdir/pr16846a.o tmpdir/pr16846b.o tmpdir/pr16846c.o" "" ++ {dummy.c} {} "pr16846a.exe"} ++ {"PR ld/pr16846(2)" ++ "-flto -fuse-linker-plugin tmpdir/pr16846a.o tmpdir/pr16846c.o tmpdir/pr16846b.o" "" ++ {dummy.c} {} "pr16846b.exe"} +} + +if { [at_least_gcc_version 4 7] } { @@ -2910882,8 +2927049,7 @@ index 0000000..69946de +run_cc_link_tests $lto_link_tests + +# Restrict these to ELF targets that support shared libs and PIC. -+if { [is_elf_format] -+ && [run_host_cmd_yesno $CC "-shared -fPIC $srcdir/$subdir/dummy.c -o tmpdir/t.so"] } { ++if { [is_elf_format] && [check_lto_shared_available] } { + run_cc_link_tests $lto_link_elf_tests + set testname "PR ld/15146 (2)" + set exec_output [run_host_cmd "$CC" "$gcc_gas_flag $gcc_ld_flag -O2 -flto -fuse-linker-plugin -Wl,-rpath-link,. -Wl,--no-copy-dt-needed-entries -Wl,--no-as-needed tmpdir/pr15146d.o tmpdir/pr15146c.so"] @@ -2911380,13 +2927546,12 @@ index 0000000..02c0e22 +#... diff --git a/ld/testsuite/ld-plugin/plugin.exp b/ld/testsuite/ld-plugin/plugin.exp new file mode 100644 -index 0000000..329d511 +index 0000000..1fdf9ed --- /dev/null +++ b/ld/testsuite/ld-plugin/plugin.exp -@@ -0,0 +1,194 @@ +@@ -0,0 +1,193 @@ +# Expect script for ld-plugin tests -+# Copyright 2010 -+# Free Software Foundation, Inc. ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2912082,6 +2928247,39 @@ index 0000000..3ce5063 +extern int x; + +void foobar (void) { x--; } +diff --git a/ld/testsuite/ld-plugin/pr16846a.c b/ld/testsuite/ld-plugin/pr16846a.c +new file mode 100644 +index 0000000..2f119a4 +--- /dev/null ++++ b/ld/testsuite/ld-plugin/pr16846a.c +@@ -0,0 +1,7 @@ ++extern int bar (void); ++ ++int ++main () ++{ ++ return bar (); ++} +diff --git a/ld/testsuite/ld-plugin/pr16846b.c b/ld/testsuite/ld-plugin/pr16846b.c +new file mode 100644 +index 0000000..bd8ddf3 +--- /dev/null ++++ b/ld/testsuite/ld-plugin/pr16846b.c +@@ -0,0 +1,7 @@ ++extern __thread int foo; ++ ++int ++bar (void) ++{ ++ return foo; ++} +diff --git a/ld/testsuite/ld-plugin/pr16846c.c b/ld/testsuite/ld-plugin/pr16846c.c +new file mode 100644 +index 0000000..3f39c5b +--- /dev/null ++++ b/ld/testsuite/ld-plugin/pr16846c.c +@@ -0,0 +1 @@ ++__thread int foo; diff --git a/ld/testsuite/ld-plugin/run-ie.c b/ld/testsuite/ld-plugin/run-ie.c new file mode 100644 index 0000000..32afa0a @@ -2914323,12 +2930521,12 @@ index 0000000..4e69082 + .endif diff --git a/ld/testsuite/ld-powerpc/aix52.exp b/ld/testsuite/ld-powerpc/aix52.exp new file mode 100644 -index 0000000..9241159 +index 0000000..4387018 --- /dev/null +++ b/ld/testsuite/ld-powerpc/aix52.exp @@ -0,0 +1,265 @@ +# Expect script for AIX 5.2+ tests -+# Copyright 2009 Free Software Foundation ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2914592,6 +2930790,42 @@ index 0000000..9241159 +run_dump_test "aix-glink-3-64" +run_dump_test "aix-weak-3-32" +run_dump_test "aix-weak-3-64" +diff --git a/ld/testsuite/ld-powerpc/ambiguousv1.d b/ld/testsuite/ld-powerpc/ambiguousv1.d +new file mode 100644 +index 0000000..73beab9 +--- /dev/null ++++ b/ld/testsuite/ld-powerpc/ambiguousv1.d +@@ -0,0 +1,12 @@ ++#source: startv1.s ++#source: funref.s ++#as: -a64 ++#ld: -melf64ppc ++#ld_after_inputfiles: tmpdir/funv1.so ++#readelf: -r --wide ++# check that we do the right thing with funref.s that doesn't have ++# anything to mark it as ELFv1 or ELFv2 ++ ++Relocation section .* contains 1 entries: ++.* ++.* R_PPC64_ADDR64 +0+ my_func \+ 0 +diff --git a/ld/testsuite/ld-powerpc/ambiguousv2.d b/ld/testsuite/ld-powerpc/ambiguousv2.d +new file mode 100644 +index 0000000..5cf047b +--- /dev/null ++++ b/ld/testsuite/ld-powerpc/ambiguousv2.d +@@ -0,0 +1,12 @@ ++#source: startv2.s ++#source: funref.s ++#as: -a64 ++#ld: -melf64ppc ++#ld_after_inputfiles: tmpdir/funv2.so ++#readelf: -r --wide ++# check that we do the right thing with funref.s that doesn't have ++# anything to mark it as ELFv1 or ELFv2 ++ ++Relocation section .*contains 1 entries: ++.* ++.* R_PPC64_JMP_SLOT .* my_func \+ 0 diff --git a/ld/testsuite/ld-powerpc/apuinfo-nul.rd b/ld/testsuite/ld-powerpc/apuinfo-nul.rd new file mode 100644 index 0000000..d617b68 @@ -2915089,6 +2931323,120 @@ index 0000000..53e8f99 +Attribute Section: gnu +File Attributes + Tag_GNU_Power_ABI_Vector: SPE +diff --git a/ld/testsuite/ld-powerpc/elfv2-2a.s b/ld/testsuite/ld-powerpc/elfv2-2a.s +new file mode 100644 +index 0000000..303087a +--- /dev/null ++++ b/ld/testsuite/ld-powerpc/elfv2-2a.s +@@ -0,0 +1,27 @@ ++ .globl f1 ++ .type f1,@function ++ .text ++f1: ++ addis 2,12,.TOC.-f1@ha ++ addi 2,2,.TOC.-f1@l ++ .localentry f1,.-f1 ++ blr ++ .size f1,.-f1 ++ ++ .globl f2 ++ .type f2,@function ++ .text ++f2: ++ addi 2,12,.TOC.-f2 ++ .localentry f2,.-f2 ++ blr ++ .size f2,.-f2 ++ ++ .quad f1 ++ .quad f1@localentry ++ .quad f2 ++ .quad f2@localentry ++ .quad f3 ++ .quad f3@localentry ++ .quad f4 ++ .quad f4@localentry +diff --git a/ld/testsuite/ld-powerpc/elfv2-2b.s b/ld/testsuite/ld-powerpc/elfv2-2b.s +new file mode 100644 +index 0000000..9c9d75e +--- /dev/null ++++ b/ld/testsuite/ld-powerpc/elfv2-2b.s +@@ -0,0 +1,17 @@ ++ .globl f3 ++ .type f3,@function ++ .text ++f3: ++ addis 2,12,.TOC.-f3@ha ++ addi 2,2,.TOC.-f3@l ++ .localentry f3,.-f3 ++ blr ++ .size f3,.-f3 ++ ++ .globl f4 ++ .type f4,@function ++ .text ++f4: ++ .localentry f4,0 ++ blr ++ .size f4,.-f4 +diff --git a/ld/testsuite/ld-powerpc/elfv2-2exe.d b/ld/testsuite/ld-powerpc/elfv2-2exe.d +new file mode 100644 +index 0000000..c8deda1 +--- /dev/null ++++ b/ld/testsuite/ld-powerpc/elfv2-2exe.d +@@ -0,0 +1,41 @@ ++#source: elfv2-2a.s ++#source: elfv2-2b.s ++#as: -a64 ++#ld: -melf64ppc -e f1 ++#objdump: -dr ++ ++.* ++ ++Disassembly of section \.text: ++ ++0+10000078 : ++.*: (3c 40 10 01|01 10 40 3c) lis r2,4097 ++.*: (38 42 80 78|78 80 42 38) addi r2,r2,-32648 ++.*: (4e 80 00 20|20 00 80 4e) blr ++0+10000084 : ++.*: (38 4c 7f f4|f4 7f 4c 38) addi r2,r12,32756 ++.*: (4e 80 00 20|20 00 80 4e) blr ++.*: (00 00 00 00|78 00 00 10) .* ++.*: (10 00 00 78|00 00 00 00) .* ++.*: (00 00 00 00|80 00 00 10) .* ++.*: (10 00 00 80|00 00 00 00) .* ++.*: (00 00 00 00|84 00 00 10) .* ++.*: (10 00 00 84|00 00 00 00) .* ++.*: (00 00 00 00|88 00 00 10) .* ++.*: (10 00 00 88|00 00 00 00) .* ++.*: (00 00 00 00|cc 00 00 10) .* ++.*: (10 00 00 cc|00 00 00 00) .* ++.*: (00 00 00 00|d4 00 00 10) .* ++.*: (10 00 00 d4|00 00 00 00) .* ++.*: (00 00 00 00|d8 00 00 10) .* ++.*: (10 00 00 d8|00 00 00 00) .* ++.*: (00 00 00 00|d8 00 00 10) .* ++.*: (10 00 00 d8|00 00 00 00) .* ++ ++0+100000cc : ++.*: (3c 40 10 01|01 10 40 3c) lis r2,4097 ++.*: (38 42 80 78|78 80 42 38) addi r2,r2,-32648 ++.*: (4e 80 00 20|20 00 80 4e) blr ++ ++0+100000d8 : ++.*: (4e 80 00 20|20 00 80 4e) blr +diff --git a/ld/testsuite/ld-powerpc/elfv2-2so.d b/ld/testsuite/ld-powerpc/elfv2-2so.d +new file mode 100644 +index 0000000..56b1434 +--- /dev/null ++++ b/ld/testsuite/ld-powerpc/elfv2-2so.d +@@ -0,0 +1,5 @@ ++#source: elfv2-2a.s ++#source: elfv2-2b.s ++#as: -a64 ++#ld: -melf64ppc -shared -e f1 ++#error: .* R_PPC64_ADDR64_LOCAL reloc unsupported in shared libraries and PIEs.* diff --git a/ld/testsuite/ld-powerpc/elfv2.s b/ld/testsuite/ld-powerpc/elfv2.s new file mode 100644 index 0000000..c2a4c3b @@ -2915129,7 +2931477,7 @@ index 0000000..c2a4c3b + .size f1,.-f1 diff --git a/ld/testsuite/ld-powerpc/elfv2exe.d b/ld/testsuite/ld-powerpc/elfv2exe.d new file mode 100644 -index 0000000..7ff9d38 +index 0000000..9ea816c --- /dev/null +++ b/ld/testsuite/ld-powerpc/elfv2exe.d @@ -0,0 +1,40 @@ @@ -2915143,14 +2931491,14 @@ index 0000000..7ff9d38 +Disassembly of section \.text: + +0+100000c0 <.*\.plt_branch\.f2>: -+.*: (ff ff 62 3d|3d 62 ff ff) addis r11,r2,-1 -+.*: (f0 7f 8b e9|e9 8b 7f f0) ld r12,32752\(r11\) ++.*: (ff ff 82 3d|3d 82 ff ff) addis r12,r2,-1 ++.*: (f0 7f 8c e9|e9 8c 7f f0) ld r12,32752\(r12\) +.*: (a6 03 89 7d|7d 89 03 a6) mtctr r12 +.*: (20 04 80 4e|4e 80 04 20) bctr + +0+100000d0 <.*\.plt_branch\.f4>: -+.*: (ff ff 62 3d|3d 62 ff ff) addis r11,r2,-1 -+.*: (f8 7f 8b e9|e9 8b 7f f8) ld r12,32760\(r11\) ++.*: (ff ff 82 3d|3d 82 ff ff) addis r12,r2,-1 ++.*: (f8 7f 8c e9|e9 8c 7f f8) ld r12,32760\(r12\) +.*: (a6 03 89 7d|7d 89 03 a6) mtctr r12 +.*: (20 04 80 4e|4e 80 04 20) bctr + @@ -2915263,13 +2931611,13 @@ index 0000000..963dbb6 +.*: (bc ff ff 4b|4b ff ff bc) b .* <__glink_PLTresolve> diff --git a/ld/testsuite/ld-powerpc/export-class.exp b/ld/testsuite/ld-powerpc/export-class.exp new file mode 100644 -index 0000000..6171d13 +index 0000000..017eeb4 --- /dev/null +++ b/ld/testsuite/ld-powerpc/export-class.exp @@ -0,0 +1,97 @@ +# Expect script for symbol export classes, PowerPC variation. +# -+# Copyright 2012 Free Software Foundation, Inc. ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2915364,6 +2931712,44 @@ index 0000000..6171d13 + powerpc_export_class_test $abi $endian $emul + } +} +diff --git a/ld/testsuite/ld-powerpc/funref.s b/ld/testsuite/ld-powerpc/funref.s +new file mode 100644 +index 0000000..3f7de47 +--- /dev/null ++++ b/ld/testsuite/ld-powerpc/funref.s +@@ -0,0 +1,4 @@ ++ .data ++ .globl func_tab ++func_tab: ++ .dc.a my_func +diff --git a/ld/testsuite/ld-powerpc/funv1.s b/ld/testsuite/ld-powerpc/funv1.s +new file mode 100644 +index 0000000..e79009d +--- /dev/null ++++ b/ld/testsuite/ld-powerpc/funv1.s +@@ -0,0 +1,10 @@ ++ .globl my_func ++ .type my_func,@function ++ .section .opd,"aw",@progbits ++my_func: ++ .quad .Lmy_func, .TOC.@tocbase ++ ++ .text ++.Lmy_func: ++ blr ++ .size my_func,.-.Lmy_func +diff --git a/ld/testsuite/ld-powerpc/funv2.s b/ld/testsuite/ld-powerpc/funv2.s +new file mode 100644 +index 0000000..eaff0b3 +--- /dev/null ++++ b/ld/testsuite/ld-powerpc/funv2.s +@@ -0,0 +1,6 @@ ++ .abiversion 2 ++ .globl my_func ++ .type my_func,@function ++my_func: ++ blr ++ .size my_func,.-my_func diff --git a/ld/testsuite/ld-powerpc/oldtlslib.s b/ld/testsuite/ld-powerpc/oldtlslib.s new file mode 100644 index 0000000..5786df1 @@ -2915510,13 +2931896,12 @@ index 0000000..264803c + 0x12340090 (00000000|a0003412) (123400a0|00000000) 00000000 00000000 .* diff --git a/ld/testsuite/ld-powerpc/powerpc.exp b/ld/testsuite/ld-powerpc/powerpc.exp new file mode 100644 -index 0000000..87e4ea8 +index 0000000..1eaedaa --- /dev/null +++ b/ld/testsuite/ld-powerpc/powerpc.exp -@@ -0,0 +1,309 @@ +@@ -0,0 +1,314 @@ +# Expect script for ld-powerpc tests -+# Copyright 2002, 2003, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012 -+# Free Software Foundation ++# Copyright (C) 2002-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2915729,6 +2932114,8 @@ index 0000000..87e4ea8 + {tocopt4a.s tocopt4b.s} {{objdump -s tocopt4.d}} "tocopt4"} + {"TOC opt5" "-melf64ppc" "" "-a64" {tocopt5.s} + {{objdump -s tocopt5.d}} "tocopt5"} ++ {"ambig shared v1" "-shared -melf64ppc" "" "-a64" {funv1.s} {} "funv1.so"} ++ {"ambig shared v2" "-shared -melf64ppc" "" "-a64" {funv2.s} {} "funv2.so"} +} + +set ppceabitests { @@ -2915787,6 +2932174,10 @@ index 0000000..87e4ea8 + run_dump_test "relbrlt" + run_dump_test "elfv2so" + run_dump_test "elfv2exe" ++ run_dump_test "elfv2-2so" ++ run_dump_test "elfv2-2exe" ++ run_dump_test "ambiguousv1" ++ run_dump_test "ambiguousv2" +} + +if { [istarget "powerpc*-eabi*"] } { @@ -2916063,6 +2932454,31 @@ index 0000000..69b0391 + .size lib_var, 2 +lib_var: + .word 1 +diff --git a/ld/testsuite/ld-powerpc/startv1.s b/ld/testsuite/ld-powerpc/startv1.s +new file mode 100644 +index 0000000..c54e1b0 +--- /dev/null ++++ b/ld/testsuite/ld-powerpc/startv1.s +@@ -0,0 +1,8 @@ ++ .globl _start ++ .section .opd,"aw",@progbits ++_start: ++ .quad .L_start, .TOC.@tocbase ++ ++ .text ++.L_start: ++ b _start +diff --git a/ld/testsuite/ld-powerpc/startv2.s b/ld/testsuite/ld-powerpc/startv2.s +new file mode 100644 +index 0000000..7187aa5 +--- /dev/null ++++ b/ld/testsuite/ld-powerpc/startv2.s +@@ -0,0 +1,5 @@ ++ .abiversion 2 ++ .text ++ .globl _start ++_start: ++ b _start diff --git a/ld/testsuite/ld-powerpc/symtocbase-1.s b/ld/testsuite/ld-powerpc/symtocbase-1.s new file mode 100644 index 0000000..ba6f073 @@ -2919114,17 +2935530,16 @@ index 0000000..d9554a1 + 01 .text_vle .text_iv .iv_handlers diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-1.ld b/ld/testsuite/ld-powerpc/vle-multiseg-1.ld new file mode 100644 -index 0000000..f2ff319 +index 0000000..3fe37b9 --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-multiseg-1.ld -@@ -0,0 +1,17 @@ +@@ -0,0 +1,16 @@ +SECTIONS +{ + .data 0x00000400 : + { *(.data) *(.ctors) *(.dtors) *(.eh_frame) *(.jcr) } + .text_vle 0x00001000 : + { -+ . = ALIGN(16); + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text_vle) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init) @@ -2919132,7 +2935547,7 @@ index 0000000..f2ff319 + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini_vle) + } -+ .text_iv . : { . = ALIGN(16); *(.text_iv) } ++ .text_iv ALIGN(16) : { *(.text_iv) } + .iv_handlers 0x0001F000 : { *(.iv_handlers) } +} diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-2.d b/ld/testsuite/ld-powerpc/vle-multiseg-2.d @@ -2919159,15 +2935574,14 @@ index 0000000..9d83bb5 + 02 .text_iv .iv_handlers diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-2.ld b/ld/testsuite/ld-powerpc/vle-multiseg-2.ld new file mode 100644 -index 0000000..2320b61 +index 0000000..da9a79d --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-multiseg-2.ld -@@ -0,0 +1,17 @@ +@@ -0,0 +1,16 @@ +SECTIONS +{ + .text_vle 0x00001000 : + { -+ . = ALIGN(16); + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text_vle) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init) @@ -2919177,7 +2935591,7 @@ index 0000000..2320b61 + } + .data 0x00001400 : + { *(.data) *(.ctors) *(.dtors) *(.eh_frame) *(.jcr) } -+ .text_iv . : { . = ALIGN(16); *(.text_iv) } ++ .text_iv ALIGN(16) : { *(.text_iv) } + .iv_handlers 0x0001F000 : { *(.iv_handlers) } +} diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-3.d b/ld/testsuite/ld-powerpc/vle-multiseg-3.d @@ -2919204,15 +2935618,14 @@ index 0000000..957b990 + 02 .iv_handlers diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-3.ld b/ld/testsuite/ld-powerpc/vle-multiseg-3.ld new file mode 100644 -index 0000000..0ed2f44 +index 0000000..cfb1d88 --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-multiseg-3.ld -@@ -0,0 +1,17 @@ +@@ -0,0 +1,16 @@ +SECTIONS +{ + .text_vle 0x00001000 : + { -+ . = ALIGN(16); + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text_vle) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init) @@ -2919220,7 +2935633,7 @@ index 0000000..0ed2f44 + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini_vle) + } -+ .text_iv . : { . = ALIGN(16); *(.text_iv) } ++ .text_iv ALIGN(16) : { *(.text_iv) } + .data 0x00001400 : + { *(.data) *(.ctors) *(.dtors) *(.eh_frame) *(.jcr) } + .iv_handlers 0x0001F000 : { *(.iv_handlers) } @@ -2919247,15 +2935660,14 @@ index 0000000..9edbe06 + 01 .data diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-4.ld b/ld/testsuite/ld-powerpc/vle-multiseg-4.ld new file mode 100644 -index 0000000..503fe06 +index 0000000..2130427 --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-multiseg-4.ld -@@ -0,0 +1,17 @@ +@@ -0,0 +1,16 @@ +SECTIONS +{ + .text_vle 0x00001000 : + { -+ . = ALIGN(16); + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text_vle) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init) @@ -2919263,7 +2935675,7 @@ index 0000000..503fe06 + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini_vle) + } -+ .text_iv . : { . = ALIGN(16); *(.text_iv) } ++ .text_iv ALIGN(16) : { *(.text_iv) } + .iv_handlers 0x0001F000 : { *(.iv_handlers) } + .data 0x00020400 : + { *(.data) *(.ctors) *(.dtors) *(.eh_frame) *(.jcr) } @@ -2919373,10 +2935785,10 @@ index 0000000..5c3c210 + 03 .text diff --git a/ld/testsuite/ld-powerpc/vle-multiseg-6.ld b/ld/testsuite/ld-powerpc/vle-multiseg-6.ld new file mode 100644 -index 0000000..c8d88dd +index 0000000..2db76cc --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-multiseg-6.ld -@@ -0,0 +1,37 @@ +@@ -0,0 +1,34 @@ +MEMORY +{ + vle_seg1 (rxw): org = 0x00000000, len = 0x10000 @@ -2919395,7 +2935807,6 @@ index 0000000..c8d88dd + } + .text_vle 0x00001000 : + { -+ . = ALIGN(16); + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text*) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.init*) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.fini*) @@ -2919403,14 +2935814,12 @@ index 0000000..c8d88dd + + .text_iv 0x100000 : + { -+ . = ALIGN(16); + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.text_iv) + INPUT_SECTION_FLAGS (SHF_PPC_VLE) *(.iv_handlers) + } >vle_seg2 + + .text 0x101000 : + { -+ . = ALIGN(16); + INPUT_SECTION_FLAGS (!SHF_PPC_VLE) *(.text*) + } +} @@ -2919814,7 +2936223,7 @@ index 0000000..34cc32d + e_mull2i 2, high_adjust_sdarel@sdarel@ha diff --git a/ld/testsuite/ld-powerpc/vle-reloc-3.d b/ld/testsuite/ld-powerpc/vle-reloc-3.d new file mode 100644 -index 0000000..e29f4f0 +index 0000000..b867bcc --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle-reloc-3.d @@ -0,0 +1,8 @@ @@ -2919822,10 +2936231,10 @@ index 0000000..e29f4f0 + +Disassembly of section .text: + -+01800094 : -+ 1800094: 1c ad 80 08 e_add16i r5,r13,-32760 -+ 1800098: 1c a2 80 04 e_add16i r5,r2,-32764 -+ 180009c: 70 00 00 ac e_li r0,172 ++.* : ++.*: 1c ad 80 08 e_add16i r5,r13,-32760 ++.*: 1c a2 80 04 e_add16i r5,r2,-32764 ++.*: 70 b0 78 04 e_li r5,-32764 diff --git a/ld/testsuite/ld-powerpc/vle-reloc-3.s b/ld/testsuite/ld-powerpc/vle-reloc-3.s new file mode 100644 index 0000000..3c7dfae @@ -2919945,19 +2936354,20 @@ index 0000000..e3b843b +exbss1b: .int diff --git a/ld/testsuite/ld-powerpc/vle.ld b/ld/testsuite/ld-powerpc/vle.ld new file mode 100644 -index 0000000..01b6598 +index 0000000..ff92a05 --- /dev/null +++ b/ld/testsuite/ld-powerpc/vle.ld -@@ -0,0 +1,11 @@ +@@ -0,0 +1,12 @@ +SECTIONS +{ + . = 0x01800000 + SIZEOF_HEADERS; + .text : { *(.text) } -+ .PPC.EMB.sdata0 : { *(.PPC.EMB.sdata0) } + .sdata2 : { PROVIDE (_SDA2_BASE_ = 32768); *(.sdata2) } + . = ALIGN (0x10000) + (. & (0x10000 - 1)); + .data : { *(.data) } + .sdata : { PROVIDE (_SDA_BASE_ = 32768); *(.sdata) } ++ . = 0xffff8000; ++ .PPC.EMB.sdata0 : { *(.PPC.EMB.sdata0) } + /DISCARD/ : { *(*) } +} diff --git a/ld/testsuite/ld-powerpc/vxworks-relax-2.rd b/ld/testsuite/ld-powerpc/vxworks-relax-2.rd @@ -2920457,12 +2936867,12 @@ index 0000000..8c8c619 +.*: 00 00 01 23 .long 0x00000123 diff --git a/ld/testsuite/ld-s390/s390.exp b/ld/testsuite/ld-s390/s390.exp new file mode 100644 -index 0000000..1ac11c7 +index 0000000..ea9c018 --- /dev/null +++ b/ld/testsuite/ld-s390/s390.exp @@ -0,0 +1,86 @@ +# Expect script for ld-s390 tests -+# Copyright (C) 2003, 2005, 2007 Free Software Foundation ++# Copyright (C) 2003-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2923240,14 +2939650,13 @@ index 0000000..616061c +} diff --git a/ld/testsuite/ld-scripts/align.exp b/ld/testsuite/ld-scripts/align.exp new file mode 100644 -index 0000000..9ea46d0 +index 0000000..1eac9cb --- /dev/null +++ b/ld/testsuite/ld-scripts/align.exp -@@ -0,0 +1,53 @@ +@@ -0,0 +1,52 @@ +# Test ALIGN in a linker script. +# By Nathan Sidwell, CodeSourcery LLC -+# Copyright 2004, 2005, 2006, 2007 -+# Free Software Foundation, Inc. ++# Copyright (C) 2004-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2923408,12 +2939817,12 @@ index 0000000..4e56d4a + .long 0x12345678 diff --git a/ld/testsuite/ld-scripts/alignof.exp b/ld/testsuite/ld-scripts/alignof.exp new file mode 100644 -index 0000000..0f05aeb +index 0000000..ecdd8dc --- /dev/null +++ b/ld/testsuite/ld-scripts/alignof.exp @@ -0,0 +1,67 @@ +# Test ALIGNOF in a linker script. -+# Copyright 2007 Free Software Foundation, Inc. ++# Copyright (C) 2007-2014 Free Software Foundation, Inc. +# Contributed by Nathan Sidwell +# +# This file is part of the GNU Binutils. @@ -2923517,14 +2939926,13 @@ index 0000000..1241112 +alignof_data = ALIGNOF(.data); diff --git a/ld/testsuite/ld-scripts/assert.exp b/ld/testsuite/ld-scripts/assert.exp new file mode 100644 -index 0000000..b4169ac +index 0000000..3b8280c --- /dev/null +++ b/ld/testsuite/ld-scripts/assert.exp -@@ -0,0 +1,36 @@ +@@ -0,0 +1,35 @@ +# Test ASSERT in a linker script. +# By Nathan Sidwell, CodeSourcery LLC -+# Copyright 2004, 2005, 2007 -+# Free Software Foundation, Inc. ++# Copyright (C) 2004-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2923731,14 +2940139,13 @@ index 0000000..aef8dfd +void (*dummy) () = foo; diff --git a/ld/testsuite/ld-scripts/crossref.exp b/ld/testsuite/ld-scripts/crossref.exp new file mode 100644 -index 0000000..01fdeb4 +index 0000000..4e84481 --- /dev/null +++ b/ld/testsuite/ld-scripts/crossref.exp -@@ -0,0 +1,148 @@ +@@ -0,0 +1,147 @@ +# Test NOCROSSREFS in a linker script. +# By Ian Lance Taylor, Cygnus Support. -+# Copyright 2000, 2001, 2002, 2003, 2004, 2005, 2007 -+# Free Software Foundation, Inc. ++# Copyright (C) 2000-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2923900,14 +2940307,13 @@ index 0000000..10b3d08 +#pass diff --git a/ld/testsuite/ld-scripts/data.exp b/ld/testsuite/ld-scripts/data.exp new file mode 100644 -index 0000000..feb22aa +index 0000000..ad25e9b --- /dev/null +++ b/ld/testsuite/ld-scripts/data.exp -@@ -0,0 +1,30 @@ +@@ -0,0 +1,31 @@ +# Test DATA STATEMENT in a linker script. +# By Nathan Sidwell, CodeSourcery LLC -+# Copyright 2004, 2005, 2007 -+# Free Software Foundation, Inc. ++# Copyright (C) 2004-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2923930,10 +2940336,12 @@ index 0000000..feb22aa +# text segment, confusing run_dump_test. +if {[is_aout_format]} { + unsupported data ++ unsupported fill + return +} + +run_dump_test data ++run_dump_test fill diff --git a/ld/testsuite/ld-scripts/data.s b/ld/testsuite/ld-scripts/data.s new file mode 100644 index 0000000..8b13789 @@ -2923960,13 +2940368,12 @@ index 0000000..f56d10f +} diff --git a/ld/testsuite/ld-scripts/default-script.exp b/ld/testsuite/ld-scripts/default-script.exp new file mode 100644 -index 0000000..2e6fce0 +index 0000000..3e37154 --- /dev/null +++ b/ld/testsuite/ld-scripts/default-script.exp -@@ -0,0 +1,34 @@ +@@ -0,0 +1,33 @@ +# Test --default-script/-dT -+# Copyright 2007, 2009 -+# Free Software Foundation, Inc. ++# Copyright (C) 2007-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2924083,14 +2940490,13 @@ index 0000000..0010084 +#pass diff --git a/ld/testsuite/ld-scripts/defined.exp b/ld/testsuite/ld-scripts/defined.exp new file mode 100644 -index 0000000..bfee102 +index 0000000..b871004 --- /dev/null +++ b/ld/testsuite/ld-scripts/defined.exp -@@ -0,0 +1,73 @@ +@@ -0,0 +1,72 @@ +# Test DEFINED in a linker script. +# By Ian Lance Taylor, Cygnus Support. -+# Copyright 2001, 2003, 2005, 2006, 2007, 2010 -+# Free Software Foundation, Inc. ++# Copyright (C) 2001-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2924399,11 +2940805,11 @@ index 0000000..279107d +#pass diff --git a/ld/testsuite/ld-scripts/dynamic-sections.exp b/ld/testsuite/ld-scripts/dynamic-sections.exp new file mode 100644 -index 0000000..b1b3ae7 +index 0000000..ff611b7 --- /dev/null +++ b/ld/testsuite/ld-scripts/dynamic-sections.exp @@ -0,0 +1,27 @@ -+# Copyright 2007 Free Software Foundation, Inc. ++# Copyright (C) 2007-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2924670,14 +2941076,13 @@ index 0000000..6de5198 +} diff --git a/ld/testsuite/ld-scripts/empty-address.exp b/ld/testsuite/ld-scripts/empty-address.exp new file mode 100644 -index 0000000..6a2150f +index 0000000..048ace9 --- /dev/null +++ b/ld/testsuite/ld-scripts/empty-address.exp -@@ -0,0 +1,32 @@ +@@ -0,0 +1,31 @@ +# Make sure that "dot" is updated for empty sections if their addresses +# are set. -+# Copyright 2006, 2007, 2009 -+# Free Software Foundation, Inc. ++# Copyright (C) 2006-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2924708,33 +2941113,26 @@ index 0000000..6a2150f +run_dump_test empty-address-3c diff --git a/ld/testsuite/ld-scripts/empty-aligned.d b/ld/testsuite/ld-scripts/empty-aligned.d new file mode 100644 -index 0000000..d9916dd +index 0000000..ff131eb --- /dev/null +++ b/ld/testsuite/ld-scripts/empty-aligned.d -@@ -0,0 +1,14 @@ +@@ -0,0 +1,8 @@ +#source: empty-aligned.s +#ld: -T empty-aligned.t -+#readelf: -l --wide -+#xfail: "hppa64-*-*" -+#notarget: frv-*-*linux* ++#readelf: -S --wide + +#... -+Program Headers: -+ +Type +Offset +VirtAddr +PhysAddr +FileSiz +MemSiz +Flg +Align -+ +LOAD +0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ 0x[0-9a-f]+ [RWE ]+ +0x[0-9a-f]+ -+! +LOAD .* -+#... -+ +Segment Sections\.\.\. -+ +00 +.text ++.* .text .* ++!.* .text[234] .* ++#pass diff --git a/ld/testsuite/ld-scripts/empty-aligned.exp b/ld/testsuite/ld-scripts/empty-aligned.exp new file mode 100644 -index 0000000..70da61d +index 0000000..cbf9662 --- /dev/null +++ b/ld/testsuite/ld-scripts/empty-aligned.exp -@@ -0,0 +1,29 @@ +@@ -0,0 +1,28 @@ +# Make sure empty aligned sections do not change output layout. -+# Copyright 2005, 2007 -+# Free Software Foundation, Inc. ++# Copyright (C) 2005-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2924771,7 +2941169,7 @@ index 0000000..2079aa7 + .long 123 diff --git a/ld/testsuite/ld-scripts/empty-aligned.t b/ld/testsuite/ld-scripts/empty-aligned.t new file mode 100644 -index 0000000..e59bc20 +index 0000000..5f6a38d --- /dev/null +++ b/ld/testsuite/ld-scripts/empty-aligned.t @@ -0,0 +1,29 @@ @@ -2924783,14 +2941181,14 @@ index 0000000..e59bc20 + { + *(.text1) + } -+ /* Same for alignment at beginning and end. */ ++ /* Same for alignment at beginning and end, although we need to be ++ careful in the expression used to align. */ + .text2 ALIGN (4096) : + { + *(.text2) -+ . = ALIGN (4096); ++ . = ALIGN (. != 0 ? 4096 : 1); + } -+ /* Same for alignment just at end, although we need to be careful in -+ the expression used to align. */ ++ /* Same for alignment just at end. */ + .text3 : + { + *(.text3) @@ -2924818,14 +2941216,13 @@ index 0000000..7bd9b9a +#pass diff --git a/ld/testsuite/ld-scripts/empty-orphan.exp b/ld/testsuite/ld-scripts/empty-orphan.exp new file mode 100644 -index 0000000..0c6ebd7 +index 0000000..6ceba79 --- /dev/null +++ b/ld/testsuite/ld-scripts/empty-orphan.exp -@@ -0,0 +1,37 @@ +@@ -0,0 +1,36 @@ +# Make sure orphan sections do not lead to huge output files. +# By David Heine, Tensilica, Inc. -+# Copyright 2005, 2006, 2007, 2009 -+# Free Software Foundation, Inc. ++# Copyright (C) 2005-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2924899,14 +2941296,13 @@ index 0000000..b57e164 +} diff --git a/ld/testsuite/ld-scripts/expr.exp b/ld/testsuite/ld-scripts/expr.exp new file mode 100644 -index 0000000..0f92d97 +index 0000000..eaf0662 --- /dev/null +++ b/ld/testsuite/ld-scripts/expr.exp @@ -0,0 +1,27 @@ +# Test expressions in a linker script. +# By Nathan Sidwell, CodeSourcery LLC -+# Copyright 2006, 2007, 2010 -+# Free Software Foundation, Inc. ++# Copyright (C) 2006-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2924930,6 +2941326,7 @@ index 0000000..0f92d97 +run_dump_test sane1 +run_dump_test assign-loc +run_dump_test pr14962 ++run_dump_test pr14962-2 diff --git a/ld/testsuite/ld-scripts/expr1.d b/ld/testsuite/ld-scripts/expr1.d new file mode 100644 index 0000000..d96dfc1 @@ -2925006,14 +2941403,13 @@ index 0000000..634eab2 +ASSERT (_end - _text <= 0x100, "fail"); diff --git a/ld/testsuite/ld-scripts/extern.exp b/ld/testsuite/ld-scripts/extern.exp new file mode 100644 -index 0000000..f05cd35 +index 0000000..3823f8d --- /dev/null +++ b/ld/testsuite/ld-scripts/extern.exp -@@ -0,0 +1,71 @@ +@@ -0,0 +1,70 @@ +# Test EXTERN in a linker script. +# By Nathan Sidwell, CodeSourcery LLC -+# Copyright 2007 -+# Free Software Foundation, Inc. ++# Copyright (C) 2007-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2925108,6 +2941504,93 @@ index 0000000..b2a012a +SECTIONS +{ +} +diff --git a/ld/testsuite/ld-scripts/fill.d b/ld/testsuite/ld-scripts/fill.d +new file mode 100644 +index 0000000..8dd789b +--- /dev/null ++++ b/ld/testsuite/ld-scripts/fill.d +@@ -0,0 +1,29 @@ ++#source: fill_0.s ++#source: fill_1.s ++#source: fill_2.s ++#ld: -T fill.t ++#objdump: -s -j .text ++#xfail: ia64-*-* alpha-*-*ecoff m32c-*-* mips*-*-* sh-*-pe sparc*-*-coff ++#xfail: tic30-*-coff tic4x-*-* tic54x-*-* ++#xfail: x86_64-*-pe* x86_64-*-mingw* x86_64-*-cygwin z8k-*-* ++# Breaks on ia64 due to minimum alignment of code. The section alignment ++# could be increased to suit ia64 but then we'd break many coff targets ++# that don't support alignment other than 4 bytes. ++# alpha-linuxecoff always aligns code to 16 bytes. ++# m32c pads out code sections to 8 bytes. ++# mips aligns to 16 bytes ++# sh-pe pads out code sections to 16 bytes ++# sparc-coff aligns to 8 bytes ++# tic30-coff aligns to 2 bytes ++# tic4x has 4 octet bytes ++# tic54x doesn't support .p2align ++# x86_64-pe aligns to 16 bytes ++# z8k-coff aligns to 2 bytes ++ ++.*: file format .* ++ ++Contents of section .text: ++ [0-9a-f]+ cafebabe 01010101 02020202 12232323 .* ++ [0-9a-f]+ 03030303 00345600 00004567 000089ab .* ++ [0-9a-f]+ (deadbeef|efbeadde) 00004567 000089ab 0000cdef .* ++ [0-9a-f]+ 00004567 000089ab 0000cdef 00000123 .* +diff --git a/ld/testsuite/ld-scripts/fill.t b/ld/testsuite/ld-scripts/fill.t +new file mode 100644 +index 0000000..835e009 +--- /dev/null ++++ b/ld/testsuite/ld-scripts/fill.t +@@ -0,0 +1,20 @@ ++SECTIONS ++{ ++ .text : ++ { ++ . += 4; ++ *0.o(.text) ++ FILL (0x12) ++ *1.o(.text) ++ . += 1; ++ FILL (0x23) ++ *2.o(.text) ++ FILL (0x003456) ++ . += 4; ++ FILL (0x00004567000089ab0000cdef00000123) ++ . += 8; ++ LONG (0xdeadbeef) ++ . += 12; ++ . += 16; ++ } =0xcafebabe ++} +diff --git a/ld/testsuite/ld-scripts/fill_0.s b/ld/testsuite/ld-scripts/fill_0.s +new file mode 100644 +index 0000000..2494a6e +--- /dev/null ++++ b/ld/testsuite/ld-scripts/fill_0.s +@@ -0,0 +1,2 @@ ++ .text ++ .byte 1,1,1,1 +diff --git a/ld/testsuite/ld-scripts/fill_1.s b/ld/testsuite/ld-scripts/fill_1.s +new file mode 100644 +index 0000000..2bbb28e +--- /dev/null ++++ b/ld/testsuite/ld-scripts/fill_1.s +@@ -0,0 +1,3 @@ ++ .text ++ .p2align 2 ++ .byte 2,2,2,2 +diff --git a/ld/testsuite/ld-scripts/fill_2.s b/ld/testsuite/ld-scripts/fill_2.s +new file mode 100644 +index 0000000..0b85fb5 +--- /dev/null ++++ b/ld/testsuite/ld-scripts/fill_2.s +@@ -0,0 +1,3 @@ ++ .text ++ .p2align 2 ++ .byte 3,3,3,3 diff --git a/ld/testsuite/ld-scripts/include-1.d b/ld/testsuite/ld-scripts/include-1.d new file mode 100644 index 0000000..4ad1fe8 @@ -2925186,12 +2941669,12 @@ index 0000000..136c9f4 + diff --git a/ld/testsuite/ld-scripts/include.exp b/ld/testsuite/ld-scripts/include.exp new file mode 100644 -index 0000000..08fa1b6 +index 0000000..e4ecf3c --- /dev/null +++ b/ld/testsuite/ld-scripts/include.exp @@ -0,0 +1,40 @@ +# Test for proper diagnosis of overflowed memory regions. -+# Copyright 2008, 2009 Free Software Foundation, Inc. ++# Copyright (C) 2008-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2925243,14 +2941726,13 @@ index 0000000..e9fca05 + .fill 16,1,0x34 diff --git a/ld/testsuite/ld-scripts/log2.exp b/ld/testsuite/ld-scripts/log2.exp new file mode 100644 -index 0000000..43827dc +index 0000000..f3fd7f8 --- /dev/null +++ b/ld/testsuite/ld-scripts/log2.exp -@@ -0,0 +1,34 @@ +@@ -0,0 +1,33 @@ +# Test LOG2() expression in linker script language. +# By Clemens Lang -+# Copyright 2013 -+# Free Software Foundation, Inc. ++# Copyright (C) 2013-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2925322,12 +2941804,12 @@ index 0000000..7877ca4 +#pass diff --git a/ld/testsuite/ld-scripts/map-address.exp b/ld/testsuite/ld-scripts/map-address.exp new file mode 100644 -index 0000000..499a824 +index 0000000..70348e9 --- /dev/null +++ b/ld/testsuite/ld-scripts/map-address.exp @@ -0,0 +1,47 @@ +# Test address printed by --print-map -+# Copyright 2002, 2005, 2007 Free Software Foundation, Inc. ++# Copyright (C) 2002-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2925504,12 +2941986,12 @@ index 0000000..78a9c92 +#pass diff --git a/ld/testsuite/ld-scripts/overlay-size.exp b/ld/testsuite/ld-scripts/overlay-size.exp new file mode 100644 -index 0000000..42c4348 +index 0000000..df3407a --- /dev/null +++ b/ld/testsuite/ld-scripts/overlay-size.exp @@ -0,0 +1,34 @@ +# Test the OVERLAY statement. -+# Copyright 2002, 2005, 2007 Free Software Foundation, Inc. ++# Copyright (C) 2002-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2925645,14 +2942127,13 @@ index 0000000..0d9af35 +} diff --git a/ld/testsuite/ld-scripts/phdrs.exp b/ld/testsuite/ld-scripts/phdrs.exp new file mode 100644 -index 0000000..b7f3682 +index 0000000..64ed7e4 --- /dev/null +++ b/ld/testsuite/ld-scripts/phdrs.exp -@@ -0,0 +1,76 @@ +@@ -0,0 +1,75 @@ +# Test PHDRS in a linker script. +# By Ian Lance Taylor, Cygnus Support. -+# Copyright 1999, 2000, 2001, 2002, 2003, 2005, 2006, 2007 -+# Free Software Foundation, Inc. ++# Copyright (C) 1999-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2925763,12 +2942244,12 @@ index 0000000..283e30c +} diff --git a/ld/testsuite/ld-scripts/phdrs2.exp b/ld/testsuite/ld-scripts/phdrs2.exp new file mode 100644 -index 0000000..b680d85 +index 0000000..59bbd6f --- /dev/null +++ b/ld/testsuite/ld-scripts/phdrs2.exp @@ -0,0 +1,75 @@ +# Test PHDRS with empty sections in a linker script. -+# Copyright 2006, 2005, 2007, 2010 Free Software Foundation, Inc, ++# Copyright (C) 2005-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2925896,13 +2942377,13 @@ index 0000000..7b37d80 +# error: \A[^ \n]*:[^:\n]*:5: PHDRS and FILEHDR.* diff --git a/ld/testsuite/ld-scripts/phdrs3.exp b/ld/testsuite/ld-scripts/phdrs3.exp new file mode 100644 -index 0000000..9ab8363 +index 0000000..e1d2e7d --- /dev/null +++ b/ld/testsuite/ld-scripts/phdrs3.exp @@ -0,0 +1,39 @@ +# Test PHDRS in a linker script. +# By Nathan Sidwell -+# Copyright 2009 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2925997,6 +2942478,39 @@ index 0000000..c07ff34 + .data : { *(.data) } :data + /DISCARD/ : { *(.*) } +} +diff --git a/ld/testsuite/ld-scripts/pr14962-2.d b/ld/testsuite/ld-scripts/pr14962-2.d +new file mode 100644 +index 0000000..7dd244e +--- /dev/null ++++ b/ld/testsuite/ld-scripts/pr14962-2.d +@@ -0,0 +1,10 @@ ++#ld: -T pr14962-2.t ++#source: pr14962a.s ++#nm: -n ++#notarget: rx-*-* frv-*-*linux* ++ ++#... ++0+2000 [AT] _start ++#... ++0+2000 A x ++#pass +diff --git a/ld/testsuite/ld-scripts/pr14962-2.t b/ld/testsuite/ld-scripts/pr14962-2.t +new file mode 100644 +index 0000000..f2c603b +--- /dev/null ++++ b/ld/testsuite/ld-scripts/pr14962-2.t +@@ -0,0 +1,11 @@ ++TOTO = 4096; ++TOTO += 4096; ++ ++SECTIONS ++{ ++ .text TOTO : ++ { ++ x = ABSOLUTE(TOTO); ++ *(*.text) ++ } ++} diff --git a/ld/testsuite/ld-scripts/pr14962.d b/ld/testsuite/ld-scripts/pr14962.d new file mode 100644 index 0000000..06b223e @@ -2926178,14 +2942692,13 @@ index 0000000..f6229d4 +} diff --git a/ld/testsuite/ld-scripts/provide.exp b/ld/testsuite/ld-scripts/provide.exp new file mode 100644 -index 0000000..6db399f +index 0000000..a6d3514 --- /dev/null +++ b/ld/testsuite/ld-scripts/provide.exp -@@ -0,0 +1,45 @@ +@@ -0,0 +1,44 @@ +# Test PROVIDE in a linker script. +# By Nathan Sidwell, CodeSourcery LLC -+# Copyright 2004, 2005, 2006, 2007 -+# Free Software Foundation, Inc. ++# Copyright (C) 2004-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2926314,12 +2942827,12 @@ index 0000000..da9dff5 +REGION_ALIAS ("*default*", MY_REGION); diff --git a/ld/testsuite/ld-scripts/rgn-at.exp b/ld/testsuite/ld-scripts/rgn-at.exp new file mode 100644 -index 0000000..9095273 +index 0000000..cc31fa4 --- /dev/null +++ b/ld/testsuite/ld-scripts/rgn-at.exp @@ -0,0 +1,33 @@ +# Test for proper diagnosis of overflowed memory regions. -+# Copyright 2009 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2926403,6 +2942916,95 @@ index 0000000..610be2a + .bss : { *(.bss) } >ram + /DISCARD/ : { *(*) } +} +diff --git a/ld/testsuite/ld-scripts/rgn-at10.d b/ld/testsuite/ld-scripts/rgn-at10.d +new file mode 100644 +index 0000000..73ebfcc +--- /dev/null ++++ b/ld/testsuite/ld-scripts/rgn-at10.d +@@ -0,0 +1,12 @@ ++#source: rgn-at10.s ++#ld: -T rgn-at10.t ++#objdump: -h --wide ++#xfail: rx-*-* ++# Test that lma is adjusted in case the section start vma is aligned and ++# lma_region != region if requested by script. Make sure this works with ++# non-load sections. ++ ++#... ++.* 0+10000 +0+20000 .* ++.* 0+10100 +0+20100 .* ++.* 0+10100 +0+20100 .* +diff --git a/ld/testsuite/ld-scripts/rgn-at10.s b/ld/testsuite/ld-scripts/rgn-at10.s +new file mode 100644 +index 0000000..b538205 +--- /dev/null ++++ b/ld/testsuite/ld-scripts/rgn-at10.s +@@ -0,0 +1,10 @@ ++ .text ++ .long 0 ++ ++ .section .tbss,"awT",%nobits ++ .p2align 8 ++ .zero 4 ++ ++ .data ++ .p2align 4 ++ .long 0 +diff --git a/ld/testsuite/ld-scripts/rgn-at10.t b/ld/testsuite/ld-scripts/rgn-at10.t +new file mode 100644 +index 0000000..0aa0b27 +--- /dev/null ++++ b/ld/testsuite/ld-scripts/rgn-at10.t +@@ -0,0 +1,13 @@ ++MEMORY ++{ ++ ram : ORIGIN = 0x10000, LENGTH = 0x10000 ++ rom : ORIGIN = 0x20000, LENGTH = 0x10000 ++} ++ ++SECTIONS ++{ ++ .text : ALIGN_WITH_INPUT {*(.text)} > ram AT> rom ++ .tbss : ALIGN_WITH_INPUT {*(.tbss)} > ram AT> rom ++ .data : ALIGN_WITH_INPUT {*(.data)} > ram AT> rom ++ /DISCARD/ : {*(*)} ++} +diff --git a/ld/testsuite/ld-scripts/rgn-at11.d b/ld/testsuite/ld-scripts/rgn-at11.d +new file mode 100644 +index 0000000..9ebbd28 +--- /dev/null ++++ b/ld/testsuite/ld-scripts/rgn-at11.d +@@ -0,0 +1,11 @@ ++#source: rgn-at10.s ++#ld: -T rgn-at11.t ++#objdump: -h --wide ++#xfail: rx-*-* ++# Test that lma is not adjusted in case the section start vma is aligned and ++# lma_region != region if not requested by script. ++ ++#... ++.* 0+10000 +0+20000 .* ++.* 0+10100 +0+20004 .* ++.* 0+10100 +0+20004 .* +diff --git a/ld/testsuite/ld-scripts/rgn-at11.t b/ld/testsuite/ld-scripts/rgn-at11.t +new file mode 100644 +index 0000000..4f07c9d +--- /dev/null ++++ b/ld/testsuite/ld-scripts/rgn-at11.t +@@ -0,0 +1,13 @@ ++MEMORY ++{ ++ ram : ORIGIN = 0x10000, LENGTH = 0x10000 ++ rom : ORIGIN = 0x20000, LENGTH = 0x10000 ++} ++ ++SECTIONS ++{ ++ .text : ALIGN_WITH_INPUT {*(.text)} > ram AT> rom ++ .tbss : {*(.tbss)} > ram AT> rom ++ .data : ALIGN_WITH_INPUT {*(.data)} > ram AT> rom ++ /DISCARD/ : {*(*)} ++} diff --git a/ld/testsuite/ld-scripts/rgn-at2.d b/ld/testsuite/ld-scripts/rgn-at2.d new file mode 100644 index 0000000..8fd5f1a @@ -2926718,14 +2943320,48 @@ index 0000000..e8aa1c7 + .data : ALIGN_WITH_INPUT {*(.data)} > ram AT> rom + /DISCARD/ : {*(*)} +} +diff --git a/ld/testsuite/ld-scripts/rgn-at9.d b/ld/testsuite/ld-scripts/rgn-at9.d +new file mode 100644 +index 0000000..e6384b4 +--- /dev/null ++++ b/ld/testsuite/ld-scripts/rgn-at9.d +@@ -0,0 +1,10 @@ ++#source: rgn-at6.s ++#ld: -T rgn-at9.t ++#objdump: -h --wide ++#xfail: rx-*-* ++# Test that lma is adjusted in case the section start vma is aligned and ++# lma_region != region if requested by script. ++ ++#... ++.* 0+10000 +0+20080 .* ++.* 0+10100 +0+20180 .* +diff --git a/ld/testsuite/ld-scripts/rgn-at9.t b/ld/testsuite/ld-scripts/rgn-at9.t +new file mode 100644 +index 0000000..7342e64 +--- /dev/null ++++ b/ld/testsuite/ld-scripts/rgn-at9.t +@@ -0,0 +1,12 @@ ++MEMORY ++{ ++ ram : ORIGIN = 0x10000, LENGTH = 0x10000 ++ rom : ORIGIN = 0x20080, LENGTH = 0x10000 ++} ++ ++SECTIONS ++{ ++ .text : ALIGN_WITH_INPUT {*(.text)} > ram AT> rom ++ .data : ALIGN_WITH_INPUT {*(.data)} > ram AT> rom ++ /DISCARD/ : {*(*)} ++} diff --git a/ld/testsuite/ld-scripts/rgn-over.exp b/ld/testsuite/ld-scripts/rgn-over.exp new file mode 100644 -index 0000000..8192487 +index 0000000..881f3bf --- /dev/null +++ b/ld/testsuite/ld-scripts/rgn-over.exp @@ -0,0 +1,54 @@ +# Test for proper diagnosis of overflowed memory regions. -+# Copyright 2007, 2008 Free Software Foundation, Inc. ++# Copyright (C) 2007-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2927390,13 +2944026,13 @@ index 0000000..037a62c +} diff --git a/ld/testsuite/ld-scripts/script.exp b/ld/testsuite/ld-scripts/script.exp new file mode 100644 -index 0000000..41432f9 +index 0000000..68346e0 --- /dev/null +++ b/ld/testsuite/ld-scripts/script.exp @@ -0,0 +1,135 @@ +# Test basic linker script functionality +# By Ian Lance Taylor, Cygnus Support -+# Copyright 1999-2013 Free Software Foundation, Inc. ++# Copyright (C) 1999-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2927644,7 +2944280,7 @@ index 0000000..ca5ae63 +} diff --git a/ld/testsuite/ld-scripts/section-flags.exp b/ld/testsuite/ld-scripts/section-flags.exp new file mode 100644 -index 0000000..0d36f65 +index 0000000..f48100c --- /dev/null +++ b/ld/testsuite/ld-scripts/section-flags.exp @@ -0,0 +1,43 @@ @@ -2927652,7 +2944288,7 @@ index 0000000..0d36f65 +# +# This file is part of the GNU Binutils. +# -+# Copyright 2012 Free Software Foundation, Inc. ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by @@ -2927748,12 +2944384,12 @@ index 0000000..155b3dc +} diff --git a/ld/testsuite/ld-scripts/section-match.exp b/ld/testsuite/ld-scripts/section-match.exp new file mode 100644 -index 0000000..bdca8cf +index 0000000..f118b65 --- /dev/null +++ b/ld/testsuite/ld-scripts/section-match.exp @@ -0,0 +1,22 @@ +# Expect script for section regular expressions tests -+# Copyright (C) 2010 Free Software Foundation ++# Copyright (C) 2010-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2927891,12 +2944527,12 @@ index 0000000..e67b3fa +} diff --git a/ld/testsuite/ld-scripts/size.exp b/ld/testsuite/ld-scripts/size.exp new file mode 100644 -index 0000000..1d59158 +index 0000000..06ffc8a --- /dev/null +++ b/ld/testsuite/ld-scripts/size.exp @@ -0,0 +1,41 @@ +# Expect script for SIZEOF tests -+# Copyright (C) 2004, 2005, 2007 Free Software Foundation ++# Copyright (C) 2004-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2927938,15 +2944574,14 @@ index 0000000..1d59158 +run_dump_test size-2 diff --git a/ld/testsuite/ld-scripts/sizeof.exp b/ld/testsuite/ld-scripts/sizeof.exp new file mode 100644 -index 0000000..ed5d191 +index 0000000..24003cd --- /dev/null +++ b/ld/testsuite/ld-scripts/sizeof.exp -@@ -0,0 +1,74 @@ +@@ -0,0 +1,73 @@ +# Test SIZEOF in a linker script. +# By Ian Lance Taylor, Cygnus Support +# Based on a bug report from anders.blomdell@control.lth.se. -+# Copyright 2001, 2005, 2007 -+# Free Software Foundation, Inc. ++# Copyright (C) 2001-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2928048,14 +2944683,13 @@ index 0000000..6244a37 +sizeof_data = SIZEOF(.data); diff --git a/ld/testsuite/ld-scripts/sort.exp b/ld/testsuite/ld-scripts/sort.exp new file mode 100644 -index 0000000..47950a7 +index 0000000..7371ee8 --- /dev/null +++ b/ld/testsuite/ld-scripts/sort.exp -@@ -0,0 +1,40 @@ +@@ -0,0 +1,39 @@ +# Test SORT_BY_NAME/SORT_BY_ALIGNMENT/SORT in a linker script. +# By H.J. Lu -+# Copyright 2004, 2005, 2007 -+# Free Software Foundation, Inc. ++# Copyright (C) 2004-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2928774,14 +2945408,13 @@ index 0000000..d797c79 +} diff --git a/ld/testsuite/ld-scripts/weak.exp b/ld/testsuite/ld-scripts/weak.exp new file mode 100644 -index 0000000..cba6e25 +index 0000000..39a49f5 --- /dev/null +++ b/ld/testsuite/ld-scripts/weak.exp -@@ -0,0 +1,80 @@ +@@ -0,0 +1,79 @@ +# Test weak symbols. +# By Ian Lance Taylor, Cygnus Solutions. -+# Copyright 1999, 2000, 2002, 2004, 2005, 2006, 2007, 2009, 2011 -+# Free Software Foundation, Inc. ++# Copyright (C) 1999-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2928814,8 +2945447,8 @@ index 0000000..cba6e25 + setup_xfail *-*-pe* +} + -+# hppa64 and or32 are incredibly broken -+setup_xfail hppa64-*-* or32-*-* ++# hppa64 is incredibly broken ++setup_xfail hppa64-*-* + +if {! [ld_assemble $as $srcdir/$subdir/weak1.s tmpdir/weak1.o] + || ! [ld_assemble $as $srcdir/$subdir/weak2.s tmpdir/weak2.o]} then { @@ -2929169,12 +2945802,12 @@ index 0000000..9f053d3 +} diff --git a/ld/testsuite/ld-selective/sel-dump.exp b/ld/testsuite/ld-selective/sel-dump.exp new file mode 100644 -index 0000000..d9ac24b +index 0000000..324caef --- /dev/null +++ b/ld/testsuite/ld-selective/sel-dump.exp @@ -0,0 +1,32 @@ +# Expect script for ld selective linking tests running run_dump_test -+# Copyright 2002, 2005, 2004, 2007, 2011 Free Software Foundation, Inc. ++# Copyright (C) 2002-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2929207,13 +2945840,12 @@ index 0000000..d9ac24b +} diff --git a/ld/testsuite/ld-selective/selective.exp b/ld/testsuite/ld-selective/selective.exp new file mode 100644 -index 0000000..23c23dd +index 0000000..99ea012 --- /dev/null +++ b/ld/testsuite/ld-selective/selective.exp -@@ -0,0 +1,225 @@ +@@ -0,0 +1,224 @@ +# Expect script for LD selective linking tests -+# Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2009, -+# 2010, 2011 Free Software Foundation, Inc. ++# Copyright (C) 1998-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2929438,12 +2946070,11 @@ index 0000000..23c23dd +} diff --git a/ld/testsuite/ld-sh/arch/arch.exp b/ld/testsuite/ld-sh/arch/arch.exp new file mode 100644 -index 0000000..acc322e +index 0000000..c4e6f6f --- /dev/null +++ b/ld/testsuite/ld-sh/arch/arch.exp -@@ -0,0 +1,257 @@ -+# Copyright (C) 2004, 2005, 2006, 2007, 2008 -+# Free Software Foundation, Inc. +@@ -0,0 +1,256 @@ ++# Copyright (C) 2004-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2935818,12 +2952449,12 @@ index 0000000..94e0658 +bar: diff --git a/ld/testsuite/ld-sh/rd-sh.exp b/ld/testsuite/ld-sh/rd-sh.exp new file mode 100644 -index 0000000..b600961 +index 0000000..0146780 --- /dev/null +++ b/ld/testsuite/ld-sh/rd-sh.exp @@ -0,0 +1,71 @@ +# Expect script for run_dump_test based ld-sh tests. -+# Copyright 2001, 2002, 2003, 2005, 2006, 2007 Free Software Foundation, Inc. ++# Copyright (C) 2001-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2935982,12 +2952613,12 @@ index 0000000..e579034 + .word foo + 0x123 diff --git a/ld/testsuite/ld-sh/sh-vxworks.exp b/ld/testsuite/ld-sh/sh-vxworks.exp new file mode 100644 -index 0000000..ab2c1c8 +index 0000000..de943a5 --- /dev/null +++ b/ld/testsuite/ld-sh/sh-vxworks.exp @@ -0,0 +1,62 @@ +# Expect script for VxWorks targeted SH linker tests -+# Copyright 2006, 2007 Free Software Foundation, Inc. ++# Copyright (C) 2006-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2936050,13 +2952681,12 @@ index 0000000..ab2c1c8 +run_dump_test "vxworks1-static" diff --git a/ld/testsuite/ld-sh/sh.exp b/ld/testsuite/ld-sh/sh.exp new file mode 100644 -index 0000000..90afaee +index 0000000..31181a9 --- /dev/null +++ b/ld/testsuite/ld-sh/sh.exp -@@ -0,0 +1,168 @@ +@@ -0,0 +1,167 @@ +# Expect script for ld-sh tests -+# Copyright 1995, 1996, 1997, 2001, 2002, 2003, 2005, 2006, 2007, 2010 -+# Free Software Foundation, Inc. ++# Copyright (C) 1995-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2937837,12 +2954467,12 @@ index 0000000..518e67e +0+10c8 g .* 0+ ___dtors_end diff --git a/ld/testsuite/ld-sh/sh64/rd-sh64.exp b/ld/testsuite/ld-sh/sh64/rd-sh64.exp new file mode 100644 -index 0000000..ebeed0a +index 0000000..b480387 --- /dev/null +++ b/ld/testsuite/ld-sh/sh64/rd-sh64.exp @@ -0,0 +1,44 @@ +# Expect script for run_dump_test based ld-sh/sh64 tests. -+# Copyright 2002, 2003, 2005, 2007 Free Software Foundation, Inc. ++# Copyright (C) 2002-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2938189,12 +2954819,12 @@ index 0000000..986e013 + 0000 deaddead .* diff --git a/ld/testsuite/ld-sh/sh64/relax.exp b/ld/testsuite/ld-sh/sh64/relax.exp new file mode 100644 -index 0000000..bb05e43 +index 0000000..ca1a8dd --- /dev/null +++ b/ld/testsuite/ld-sh/sh64/relax.exp @@ -0,0 +1,155 @@ +# Expect script for ld-sh tests -+# Copyright (C) 2001, 2002, 2003, 2004, 2005, 2007 Free Software Foundation ++# Copyright (C) 2001-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2939468,12 +2956098,12 @@ index 0000000..8bd5502 + 0x00000220 00000000 00000000 .* diff --git a/ld/testsuite/ld-sh/sh64/relfail.exp b/ld/testsuite/ld-sh/sh64/relfail.exp new file mode 100644 -index 0000000..fbdf80a +index 0000000..ebfdd13 --- /dev/null +++ b/ld/testsuite/ld-sh/sh64/relfail.exp @@ -0,0 +1,219 @@ +# Expect script for ld-sh tests -+# Copyright (C) 2001, 2002, 2003, 2004, 2005, 2007 Free Software Foundation ++# Copyright (C) 2001-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2939794,12 +2956424,12 @@ index 0000000..8ca24c0 + nop diff --git a/ld/testsuite/ld-sh/sh64/sh64.exp b/ld/testsuite/ld-sh/sh64/sh64.exp new file mode 100644 -index 0000000..2c64775 +index 0000000..ca49db7 --- /dev/null +++ b/ld/testsuite/ld-sh/sh64/sh64.exp @@ -0,0 +1,137 @@ +# Expect script for ld-sh tests -+# Copyright (C) 2000, 2001, 2002, 2003, 2005, 2007 Free Software Foundation ++# Copyright (C) 2000-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2943742,7 +2960372,7 @@ index 0000000..79192af + diff --git a/ld/testsuite/ld-shared/elf-offset.ld b/ld/testsuite/ld-shared/elf-offset.ld new file mode 100644 -index 0000000..125d879 +index 0000000..ee587f9 --- /dev/null +++ b/ld/testsuite/ld-shared/elf-offset.ld @@ -0,0 +1,170 @@ @@ -2943876,7 +2960506,7 @@ index 0000000..125d879 + /* Align here to ensure that the .bss section occupies space up to + _end. Align after .bss to ensure correct alignment even if the + .bss section disappears because there are no input sections. */ -+ . = ALIGN(32 / 8); ++ . = ALIGN(. != 0 ? 32 / 8 : 1); + } + . = ALIGN(32 / 8); + _end = . ; @@ -2944230,14 +2960860,12 @@ index 0000000..40ee37f +shlib_check () == 1 diff --git a/ld/testsuite/ld-shared/shared.exp b/ld/testsuite/ld-shared/shared.exp new file mode 100644 -index 0000000..ebb2237 +index 0000000..c723ef7 --- /dev/null +++ b/ld/testsuite/ld-shared/shared.exp -@@ -0,0 +1,351 @@ +@@ -0,0 +1,352 @@ +# Expect script for ld-shared tests -+# Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, -+# 2004, 2005, 2007, 2008, 2009, 2010, 2012 -+# Free Software Foundation, Inc. ++# Copyright (C) 1994-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2944482,6 +2961110,7 @@ index 0000000..ebb2237 + if [ string match $shared_needs_pic "yes" ] { + setup_xfail "arm*-*-linux*" + } ++ setup_xfail "aarch64*-*-linux*" + shared_test shnp "shared (non PIC)" mainnp.o sh1np.o sh2np.o shared + + # Test ELF shared library relocations with a non-zero load @@ -2944508,6 +2961137,7 @@ index 0000000..ebb2237 + if [ string match $shared_needs_pic "yes" ] { + setup_xfail "arm*-*-linux*" + } ++ setup_xfail "aarch64*-*-linux*" + shared_test shnp "shared (non PIC, load offset)" \ + mainnp.o sh1np.o sh2np.o shared \ + "-T $srcdir/$subdir/elf-offset.ld" @@ -2944564,6 +2961194,7 @@ index 0000000..ebb2237 + if [ string match $shared_needs_pic "yes" ] { + setup_xfail "arm*-*-linux*" + } ++ setup_xfail "aarch64*-*-linux*" + shared_test shmpnp "shared (PIC main, non PIC so)" mainp.o sh1np.o sh2np.o shared + } + } else { @@ -2945171,13 +2961802,13 @@ index 0000000..16890d1 +char *bar_size = &size_of_bar; diff --git a/ld/testsuite/ld-size/size.exp b/ld/testsuite/ld-size/size.exp new file mode 100644 -index 0000000..9eedfd5 +index 0000000..af9d6aa --- /dev/null +++ b/ld/testsuite/ld-size/size.exp @@ -0,0 +1,176 @@ +# Expect script for linker support of size relocations. +# -+# Copyright 2013 Free Software Foundation, Inc. ++# Copyright (C) 2013-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2946185,12 +2962816,12 @@ index 0000000..28d40ed +#pass diff --git a/ld/testsuite/ld-sparc/sparc.exp b/ld/testsuite/ld-sparc/sparc.exp new file mode 100644 -index 0000000..3caa494 +index 0000000..4593aa9 --- /dev/null +++ b/ld/testsuite/ld-sparc/sparc.exp @@ -0,0 +1,135 @@ +# Expect script for ld-sparc tests -+# Copyright (C) 2002, 2003, 2005, 2006, 2007, 2008 Free Software Foundation ++# Copyright (C) 2002-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2951417,12 +2968048,12 @@ index 0000000..4df3e4b +ext = 0x5678 diff --git a/ld/testsuite/ld-spu/spu.exp b/ld/testsuite/ld-spu/spu.exp new file mode 100644 -index 0000000..39d1c96 +index 0000000..c5bfb5d --- /dev/null +++ b/ld/testsuite/ld-spu/spu.exp @@ -0,0 +1,94 @@ +# Expect script for ld-spu tests -+# Copyright (C) 2006, 2007 Free Software Foundation ++# Copyright (C) 2006-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2951705,13 +2968336,13 @@ index 0000000..0b5fa7e +} diff --git a/ld/testsuite/ld-srec/srec.exp b/ld/testsuite/ld-srec/srec.exp new file mode 100644 -index 0000000..4a433d1 +index 0000000..eff1bd1 --- /dev/null +++ b/ld/testsuite/ld-srec/srec.exp @@ -0,0 +1,429 @@ +# Test linking directly to S-records. +# By Ian Lance Taylor, Cygnus Support. -+# Copyright 1999-2013 Free Software Foundation, Inc. ++# Copyright (C) 1999-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2956971,7 +2973602,7 @@ index 0000000..d33887e + \.\.\. diff --git a/ld/testsuite/ld-tic6x/shlib-1.rd b/ld/testsuite/ld-tic6x/shlib-1.rd new file mode 100644 -index 0000000..029bda1 +index 0000000..1fe043b --- /dev/null +++ b/ld/testsuite/ld-tic6x/shlib-1.rd @@ -0,0 +1,124 @@ @@ -2956983,10 +2973614,10 @@ index 0000000..029bda1 + \[ 1\] \.hash HASH 00008000 001000 000048 04 A 2 0 4 + \[ 2\] \.dynsym DYNSYM 00008048 001048 0000d0 10 A 3 6 4 + \[ 3\] \.dynstr STRTAB 00008118 001118 000025 00 A 0 0 1 -+ \[ 4\] \.rela\.got RELA 00008140 001140 000024 0c A 2 10 4 -+ \[ 5\] \.rela\.neardata RELA 00008164 001164 000018 0c A 2 11 4 ++ \[ 4\] \.rela\.got RELA 00008140 001140 000024 0c AI 2 10 4 ++ \[ 5\] \.rela\.neardata RELA 00008164 001164 000018 0c AI 2 11 4 + \[ 6\] \.dynamic DYNAMIC 0000817c 00117c 0000a8 08 WA 3 0 4 -+ \[ 7\] \.rela\.plt RELA 10000000 002000 000018 0c A 2 8 4 ++ \[ 7\] \.rela\.plt RELA 10000000 002000 000018 0c AI 2 8 4 + \[ 8\] \.plt PROGBITS 10000020 002020 000060 18 AX 0 0 32 + \[ 9\] \.text PROGBITS 10000080 002080 000080 00 AX 0 0 32 + \[10\] \.got PROGBITS 10000100 002100 000028 00 WA 0 0 4 @@ -2957237,7 +2973868,7 @@ index 0000000..658da73 + \.\.\. diff --git a/ld/testsuite/ld-tic6x/shlib-1b.rd b/ld/testsuite/ld-tic6x/shlib-1b.rd new file mode 100644 -index 0000000..029bda1 +index 0000000..1fe043b --- /dev/null +++ b/ld/testsuite/ld-tic6x/shlib-1b.rd @@ -0,0 +1,124 @@ @@ -2957249,10 +2973880,10 @@ index 0000000..029bda1 + \[ 1\] \.hash HASH 00008000 001000 000048 04 A 2 0 4 + \[ 2\] \.dynsym DYNSYM 00008048 001048 0000d0 10 A 3 6 4 + \[ 3\] \.dynstr STRTAB 00008118 001118 000025 00 A 0 0 1 -+ \[ 4\] \.rela\.got RELA 00008140 001140 000024 0c A 2 10 4 -+ \[ 5\] \.rela\.neardata RELA 00008164 001164 000018 0c A 2 11 4 ++ \[ 4\] \.rela\.got RELA 00008140 001140 000024 0c AI 2 10 4 ++ \[ 5\] \.rela\.neardata RELA 00008164 001164 000018 0c AI 2 11 4 + \[ 6\] \.dynamic DYNAMIC 0000817c 00117c 0000a8 08 WA 3 0 4 -+ \[ 7\] \.rela\.plt RELA 10000000 002000 000018 0c A 2 8 4 ++ \[ 7\] \.rela\.plt RELA 10000000 002000 000018 0c AI 2 8 4 + \[ 8\] \.plt PROGBITS 10000020 002020 000060 18 AX 0 0 32 + \[ 9\] \.text PROGBITS 10000080 002080 000080 00 AX 0 0 32 + \[10\] \.got PROGBITS 10000100 002100 000028 00 WA 0 0 4 @@ -2957453,7 +2974084,7 @@ index 0000000..e20eb74 + \.\.\. diff --git a/ld/testsuite/ld-tic6x/shlib-1r.rd b/ld/testsuite/ld-tic6x/shlib-1r.rd new file mode 100644 -index 0000000..029bda1 +index 0000000..1fe043b --- /dev/null +++ b/ld/testsuite/ld-tic6x/shlib-1r.rd @@ -0,0 +1,124 @@ @@ -2957465,10 +2974096,10 @@ index 0000000..029bda1 + \[ 1\] \.hash HASH 00008000 001000 000048 04 A 2 0 4 + \[ 2\] \.dynsym DYNSYM 00008048 001048 0000d0 10 A 3 6 4 + \[ 3\] \.dynstr STRTAB 00008118 001118 000025 00 A 0 0 1 -+ \[ 4\] \.rela\.got RELA 00008140 001140 000024 0c A 2 10 4 -+ \[ 5\] \.rela\.neardata RELA 00008164 001164 000018 0c A 2 11 4 ++ \[ 4\] \.rela\.got RELA 00008140 001140 000024 0c AI 2 10 4 ++ \[ 5\] \.rela\.neardata RELA 00008164 001164 000018 0c AI 2 11 4 + \[ 6\] \.dynamic DYNAMIC 0000817c 00117c 0000a8 08 WA 3 0 4 -+ \[ 7\] \.rela\.plt RELA 10000000 002000 000018 0c A 2 8 4 ++ \[ 7\] \.rela\.plt RELA 10000000 002000 000018 0c AI 2 8 4 + \[ 8\] \.plt PROGBITS 10000020 002020 000060 18 AX 0 0 32 + \[ 9\] \.text PROGBITS 10000080 002080 000080 00 AX 0 0 32 + \[10\] \.got PROGBITS 10000100 002100 000028 00 WA 0 0 4 @@ -2957669,7 +2974300,7 @@ index 0000000..ee1a607 + \.\.\. diff --git a/ld/testsuite/ld-tic6x/shlib-1rb.rd b/ld/testsuite/ld-tic6x/shlib-1rb.rd new file mode 100644 -index 0000000..029bda1 +index 0000000..1fe043b --- /dev/null +++ b/ld/testsuite/ld-tic6x/shlib-1rb.rd @@ -0,0 +1,124 @@ @@ -2957681,10 +2974312,10 @@ index 0000000..029bda1 + \[ 1\] \.hash HASH 00008000 001000 000048 04 A 2 0 4 + \[ 2\] \.dynsym DYNSYM 00008048 001048 0000d0 10 A 3 6 4 + \[ 3\] \.dynstr STRTAB 00008118 001118 000025 00 A 0 0 1 -+ \[ 4\] \.rela\.got RELA 00008140 001140 000024 0c A 2 10 4 -+ \[ 5\] \.rela\.neardata RELA 00008164 001164 000018 0c A 2 11 4 ++ \[ 4\] \.rela\.got RELA 00008140 001140 000024 0c AI 2 10 4 ++ \[ 5\] \.rela\.neardata RELA 00008164 001164 000018 0c AI 2 11 4 + \[ 6\] \.dynamic DYNAMIC 0000817c 00117c 0000a8 08 WA 3 0 4 -+ \[ 7\] \.rela\.plt RELA 10000000 002000 000018 0c A 2 8 4 ++ \[ 7\] \.rela\.plt RELA 10000000 002000 000018 0c AI 2 8 4 + \[ 8\] \.plt PROGBITS 10000020 002020 000060 18 AX 0 0 32 + \[ 9\] \.text PROGBITS 10000080 002080 000080 00 AX 0 0 32 + \[10\] \.got PROGBITS 10000100 002100 000028 00 WA 0 0 4 @@ -2957906,7 +2974537,7 @@ index 0000000..f2f5cab + diff --git a/ld/testsuite/ld-tic6x/shlib-app-1.rd b/ld/testsuite/ld-tic6x/shlib-app-1.rd new file mode 100644 -index 0000000..9c691c9 +index 0000000..74b090e --- /dev/null +++ b/ld/testsuite/ld-tic6x/shlib-app-1.rd @@ -0,0 +1,128 @@ @@ -2957918,11 +2974549,11 @@ index 0000000..9c691c9 + \[ 1\] \.hash HASH 00008000 001000 000044 04 A 2 0 4 + \[ 2\] \.dynsym DYNSYM 00008044 001044 0000c0 10 A 3 6 4 + \[ 3\] \.dynstr STRTAB 00008104 001104 000035 00 A 0 0 1 -+ \[ 4\] \.rela\.got RELA 0000813c 00113c 000018 0c A 2 11 4 -+ \[ 5\] \.rela\.neardata RELA 00008154 001154 000018 0c A 2 12 4 -+ \[ 6\] \.rela\.bss RELA 0000816c 00116c 00000c 0c A 2 13 4 ++ \[ 4\] \.rela\.got RELA 0000813c 00113c 000018 0c AI 2 11 4 ++ \[ 5\] \.rela\.neardata RELA 00008154 001154 000018 0c AI 2 12 4 ++ \[ 6\] \.rela\.bss RELA 0000816c 00116c 00000c 0c AI 2 13 4 + \[ 7\] \.dynamic DYNAMIC 00008178 001178 0000b8 08 WA 3 0 4 -+ \[ 8\] \.rela\.plt RELA 10000000 002000 00000c 0c A 2 9 4 ++ \[ 8\] \.rela\.plt RELA 10000000 002000 00000c 0c AI 2 9 4 + \[ 9\] \.plt PROGBITS 10000020 002020 000040 18 AX 0 0 32 + \[10\] \.text PROGBITS 10000060 002060 000040 00 AX 0 0 32 + \[11\] \.got PROGBITS 100000a0 0020a0 000020 00 WA 0 0 4 @@ -2958154,7 +2974785,7 @@ index 0000000..4a9c60b + diff --git a/ld/testsuite/ld-tic6x/shlib-app-1b.rd b/ld/testsuite/ld-tic6x/shlib-app-1b.rd new file mode 100644 -index 0000000..a541a5c +index 0000000..9c0610d --- /dev/null +++ b/ld/testsuite/ld-tic6x/shlib-app-1b.rd @@ -0,0 +1,128 @@ @@ -2958166,11 +2974797,11 @@ index 0000000..a541a5c + \[ 1\] \.hash HASH 00008000 001000 000044 04 A 2 0 4 + \[ 2\] \.dynsym DYNSYM 00008044 001044 0000c0 10 A 3 6 4 + \[ 3\] \.dynstr STRTAB 00008104 001104 000036 00 A 0 0 1 -+ \[ 4\] \.rela\.got RELA 0000813c 00113c 000018 0c A 2 11 4 -+ \[ 5\] \.rela\.neardata RELA 00008154 001154 000018 0c A 2 12 4 -+ \[ 6\] \.rela\.bss RELA 0000816c 00116c 00000c 0c A 2 13 4 ++ \[ 4\] \.rela\.got RELA 0000813c 00113c 000018 0c AI 2 11 4 ++ \[ 5\] \.rela\.neardata RELA 00008154 001154 000018 0c AI 2 12 4 ++ \[ 6\] \.rela\.bss RELA 0000816c 00116c 00000c 0c AI 2 13 4 + \[ 7\] \.dynamic DYNAMIC 00008178 001178 0000b8 08 WA 3 0 4 -+ \[ 8\] \.rela\.plt RELA 10000000 002000 00000c 0c A 2 9 4 ++ \[ 8\] \.rela\.plt RELA 10000000 002000 00000c 0c AI 2 9 4 + \[ 9\] \.plt PROGBITS 10000020 002020 000040 18 AX 0 0 32 + \[10\] \.text PROGBITS 10000060 002060 000040 00 AX 0 0 32 + \[11\] \.got PROGBITS 100000a0 0020a0 000020 00 WA 0 0 4 @@ -2958359,7 +2974990,7 @@ index 0000000..15c2973 + diff --git a/ld/testsuite/ld-tic6x/shlib-app-1r.rd b/ld/testsuite/ld-tic6x/shlib-app-1r.rd new file mode 100644 -index 0000000..5c1b675 +index 0000000..5cba27e --- /dev/null +++ b/ld/testsuite/ld-tic6x/shlib-app-1r.rd @@ -0,0 +1,116 @@ @@ -2958371,10 +2975002,10 @@ index 0000000..5c1b675 + \[ 1\] \.hash HASH 00008000 001000 00003c 04 A 2 0 4 + \[ 2\] \.dynsym DYNSYM 0000803c 00103c 0000a0 10 A 3 6 4 + \[ 3\] \.dynstr STRTAB 000080dc 0010dc 000030 00 A 0 0 1 -+ \[ 4\] \.rela\.got RELA 0000810c 00110c 000018 0c A 2 10 4 -+ \[ 5\] \.rela\.bss RELA 00008124 001124 00000c 0c A 2 12 4 ++ \[ 4\] \.rela\.got RELA 0000810c 00110c 000018 0c AI 2 10 4 ++ \[ 5\] \.rela\.bss RELA 00008124 001124 00000c 0c AI 2 12 4 + \[ 6\] \.dynamic DYNAMIC 00008130 001130 0000b8 08 WA 3 0 4 -+ \[ 7\] \.rela\.plt RELA 10000000 002000 00000c 0c A 2 8 4 ++ \[ 7\] \.rela\.plt RELA 10000000 002000 00000c 0c AI 2 8 4 + \[ 8\] \.plt PROGBITS 10000020 002020 000040 18 AX 0 0 32 + \[ 9\] \.text PROGBITS 10000060 002060 000040 00 AX 0 0 32 + \[10\] \.got PROGBITS 100000a0 0020a0 000020 00 WA 0 0 4 @@ -2958577,7 +2975208,7 @@ index 0000000..c313ed7 + diff --git a/ld/testsuite/ld-tic6x/shlib-app-1rb.rd b/ld/testsuite/ld-tic6x/shlib-app-1rb.rd new file mode 100644 -index 0000000..d121832 +index 0000000..7119945 --- /dev/null +++ b/ld/testsuite/ld-tic6x/shlib-app-1rb.rd @@ -0,0 +1,116 @@ @@ -2958589,10 +2975220,10 @@ index 0000000..d121832 + \[ 1\] \.hash HASH 00008000 001000 00003c 04 A 2 0 4 + \[ 2\] \.dynsym DYNSYM 0000803c 00103c 0000a0 10 A 3 6 4 + \[ 3\] \.dynstr STRTAB 000080dc 0010dc 000031 00 A 0 0 1 -+ \[ 4\] \.rela\.got RELA 00008110 001110 000018 0c A 2 10 4 -+ \[ 5\] \.rela\.bss RELA 00008128 001128 00000c 0c A 2 12 4 ++ \[ 4\] \.rela\.got RELA 00008110 001110 000018 0c AI 2 10 4 ++ \[ 5\] \.rela\.bss RELA 00008128 001128 00000c 0c AI 2 12 4 + \[ 6\] \.dynamic DYNAMIC 00008134 001134 0000b8 08 WA 3 0 4 -+ \[ 7\] \.rela\.plt RELA 10000000 002000 00000c 0c A 2 8 4 ++ \[ 7\] \.rela\.plt RELA 10000000 002000 00000c 0c AI 2 8 4 + \[ 8\] \.plt PROGBITS 10000020 002020 000040 18 AX 0 0 32 + \[ 9\] \.text PROGBITS 10000060 002060 000040 00 AX 0 0 32 + \[10\] \.got PROGBITS 100000a0 0020a0 000020 00 WA 0 0 4 @@ -2958784,7 +2975415,7 @@ index 0000000..bfdf499 + \.\.\. diff --git a/ld/testsuite/ld-tic6x/shlib-noindex.rd b/ld/testsuite/ld-tic6x/shlib-noindex.rd new file mode 100644 -index 0000000..e030b17 +index 0000000..b4de2e5 --- /dev/null +++ b/ld/testsuite/ld-tic6x/shlib-noindex.rd @@ -0,0 +1,131 @@ @@ -2958796,11 +2975427,11 @@ index 0000000..e030b17 + \[ 1\] \.hash HASH 00008000 001000 000048 04 A 2 0 4 + \[ 2\] \.dynsym DYNSYM 00008048 001048 0000d0 10 A 3 6 4 + \[ 3\] \.dynstr STRTAB 00008118 001118 000025 00 A 0 0 1 -+ \[ 4\] \.rela\.text RELA 00008140 001140 00000c 0c A 2 10 4 -+ \[ 5\] \.rela\.got RELA 0000814c 00114c 000024 0c A 2 11 4 -+ \[ 6\] \.rela\.neardata RELA 00008170 001170 000018 0c A 2 12 4 ++ \[ 4\] \.rela\.text RELA 00008140 001140 00000c 0c AI 2 10 4 ++ \[ 5\] \.rela\.got RELA 0000814c 00114c 000024 0c AI 2 11 4 ++ \[ 6\] \.rela\.neardata RELA 00008170 001170 000018 0c AI 2 12 4 + \[ 7\] \.dynamic DYNAMIC 00008188 001188 0000b0 08 WA 3 0 4 -+ \[ 8\] \.rela\.plt RELA 10000000 002000 000018 0c A 2 9 4 ++ \[ 8\] \.rela\.plt RELA 10000000 002000 000018 0c AI 2 9 4 + \[ 9\] \.plt PROGBITS 10000020 002020 000060 18 AX 0 0 32 + \[10\] \.text PROGBITS 10000080 002080 000080 00 AX 0 0 32 + \[11\] \.got PROGBITS 10000100 002100 000028 00 WA 0 0 4 @@ -2959016,7 +2975647,7 @@ index 0000000..d07cd6e + diff --git a/ld/testsuite/ld-tic6x/static-app-1.rd b/ld/testsuite/ld-tic6x/static-app-1.rd new file mode 100644 -index 0000000..c56d637 +index 0000000..ebe3675 --- /dev/null +++ b/ld/testsuite/ld-tic6x/static-app-1.rd @@ -0,0 +1,114 @@ @@ -2959028,8 +2975659,8 @@ index 0000000..c56d637 + \[ 1\] \.hash HASH 00008000 001000 00003c 04 A 2 0 4 + \[ 2\] \.dynsym DYNSYM 0000803c 00103c 0000a0 10 A 3 5 4 + \[ 3\] \.dynstr STRTAB 000080dc 0010dc 00001d 00 A 0 0 1 -+ \[ 4\] \.rela\.got RELA 000080fc 0010fc 000024 0c A 2 8 4 -+ \[ 5\] \.rela\.neardata RELA 00008120 001120 000030 0c A 2 9 4 ++ \[ 4\] \.rela\.got RELA 000080fc 0010fc 000024 0c AI 2 8 4 ++ \[ 5\] \.rela\.neardata RELA 00008120 001120 000030 0c AI 2 9 4 + \[ 6\] \.dynamic DYNAMIC 00008150 001150 000090 08 WA 3 0 4 + \[ 7\] \.text PROGBITS 10000000 002000 0000c0 00 AX 0 0 32 + \[ 8\] \.got PROGBITS 100000c0 0020c0 000020 00 WA 0 0 4 @@ -2959230,7 +2975861,7 @@ index 0000000..a35d194 + diff --git a/ld/testsuite/ld-tic6x/static-app-1b.rd b/ld/testsuite/ld-tic6x/static-app-1b.rd new file mode 100644 -index 0000000..c56d637 +index 0000000..ebe3675 --- /dev/null +++ b/ld/testsuite/ld-tic6x/static-app-1b.rd @@ -0,0 +1,114 @@ @@ -2959242,8 +2975873,8 @@ index 0000000..c56d637 + \[ 1\] \.hash HASH 00008000 001000 00003c 04 A 2 0 4 + \[ 2\] \.dynsym DYNSYM 0000803c 00103c 0000a0 10 A 3 5 4 + \[ 3\] \.dynstr STRTAB 000080dc 0010dc 00001d 00 A 0 0 1 -+ \[ 4\] \.rela\.got RELA 000080fc 0010fc 000024 0c A 2 8 4 -+ \[ 5\] \.rela\.neardata RELA 00008120 001120 000030 0c A 2 9 4 ++ \[ 4\] \.rela\.got RELA 000080fc 0010fc 000024 0c AI 2 8 4 ++ \[ 5\] \.rela\.neardata RELA 00008120 001120 000030 0c AI 2 9 4 + \[ 6\] \.dynamic DYNAMIC 00008150 001150 000090 08 WA 3 0 4 + \[ 7\] \.text PROGBITS 10000000 002000 0000c0 00 AX 0 0 32 + \[ 8\] \.got PROGBITS 100000c0 0020c0 000020 00 WA 0 0 4 @@ -2959438,7 +2976069,7 @@ index 0000000..06f8d50 + diff --git a/ld/testsuite/ld-tic6x/static-app-1r.rd b/ld/testsuite/ld-tic6x/static-app-1r.rd new file mode 100644 -index 0000000..588e422 +index 0000000..66bde12 --- /dev/null +++ b/ld/testsuite/ld-tic6x/static-app-1r.rd @@ -0,0 +1,111 @@ @@ -2959450,8 +2976081,8 @@ index 0000000..588e422 + \[ 1\] \.hash HASH 00008000 001000 00003c 04 A 2 0 4 + \[ 2\] \.dynsym DYNSYM 0000803c 00103c 0000a0 10 A 3 5 4 + \[ 3\] \.dynstr STRTAB 000080dc 0010dc 00001d 00 A 0 0 1 -+ \[ 4\] \.rela\.got RELA 000080fc 0010fc 000024 0c A 2 8 4 -+ \[ 5\] \.rela\.neardata RELA 00008120 001120 000018 0c A 2 9 4 ++ \[ 4\] \.rela\.got RELA 000080fc 0010fc 000024 0c AI 2 8 4 ++ \[ 5\] \.rela\.neardata RELA 00008120 001120 000018 0c AI 2 9 4 + \[ 6\] \.dynamic DYNAMIC 00008138 001138 000090 08 WA 3 0 4 + \[ 7\] \.text PROGBITS 10000000 002000 0000c0 00 AX 0 0 32 + \[ 8\] \.got PROGBITS 100000c0 0020c0 000020 00 WA 0 0 4 @@ -2959643,7 +2976274,7 @@ index 0000000..13d4255 + diff --git a/ld/testsuite/ld-tic6x/static-app-1rb.rd b/ld/testsuite/ld-tic6x/static-app-1rb.rd new file mode 100644 -index 0000000..588e422 +index 0000000..66bde12 --- /dev/null +++ b/ld/testsuite/ld-tic6x/static-app-1rb.rd @@ -0,0 +1,111 @@ @@ -2959655,8 +2976286,8 @@ index 0000000..588e422 + \[ 1\] \.hash HASH 00008000 001000 00003c 04 A 2 0 4 + \[ 2\] \.dynsym DYNSYM 0000803c 00103c 0000a0 10 A 3 5 4 + \[ 3\] \.dynstr STRTAB 000080dc 0010dc 00001d 00 A 0 0 1 -+ \[ 4\] \.rela\.got RELA 000080fc 0010fc 000024 0c A 2 8 4 -+ \[ 5\] \.rela\.neardata RELA 00008120 001120 000018 0c A 2 9 4 ++ \[ 4\] \.rela\.got RELA 000080fc 0010fc 000024 0c AI 2 8 4 ++ \[ 5\] \.rela\.neardata RELA 00008120 001120 000018 0c AI 2 9 4 + \[ 6\] \.dynamic DYNAMIC 00008138 001138 000090 08 WA 3 0 4 + \[ 7\] \.text PROGBITS 10000000 002000 0000c0 00 AX 0 0 32 + \[ 8\] \.got PROGBITS 100000c0 0020c0 000020 00 WA 0 0 4 @@ -2959772,13 +2976403,13 @@ index 0000000..8d7bd0d +[ \t]*100000d0 00000000 00000000 100000ec 00000000 .* diff --git a/ld/testsuite/ld-tic6x/tic6x.exp b/ld/testsuite/ld-tic6x/tic6x.exp new file mode 100644 -index 0000000..fe47650 +index 0000000..90674af --- /dev/null +++ b/ld/testsuite/ld-tic6x/tic6x.exp -@@ -0,0 +1,201 @@ +@@ -0,0 +1,199 @@ +# Expect script for ld-tic6x tests +# -+# Copyright 2012 Free Software Foundation, Inc. ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2959973,8 +2976604,6 @@ index 0000000..fe47650 +check_osabi_tic6x "C6X dynamic app OSABI, LE" tmpdir/dynapp-1 +check_osabi_tic6x "C6X dynamic app OSABI, BE" tmpdir/dynapp-1b + -+set expected_osabi "UNIX - System V" -+ +check_osabi_tic6x "C6X relocatable link OSABI, LE" tmpdir/shlib.o +check_osabi_tic6x "C6X relocatable link OSABI, BE" tmpdir/shlibb.o diff --git a/ld/testsuite/ld-tic6x/unwind-1.d b/ld/testsuite/ld-tic6x/unwind-1.d @@ -2960680,12 +2977309,12 @@ index 0000000..4a19388 + .short hw0(external_64a) diff --git a/ld/testsuite/ld-tilegx/tilegx.exp b/ld/testsuite/ld-tilegx/tilegx.exp new file mode 100644 -index 0000000..7e0dbf9 +index 0000000..5cd6ca2 --- /dev/null +++ b/ld/testsuite/ld-tilegx/tilegx.exp @@ -0,0 +1,44 @@ +# Expect script for TILE-Gx linker tests. -+# Copyright 2011 Free Software Foundation, Inc. ++# Copyright (C) 2011-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2960880,12 +2977509,12 @@ index 0000000..cc9ed0e + .short ha16(external_32b) diff --git a/ld/testsuite/ld-tilepro/tilepro.exp b/ld/testsuite/ld-tilepro/tilepro.exp new file mode 100644 -index 0000000..be10a20 +index 0000000..4cef8d8 --- /dev/null +++ b/ld/testsuite/ld-tilepro/tilepro.exp @@ -0,0 +1,37 @@ +# Expect script for TILEPro linker tests. -+# Copyright 2011 Free Software Foundation, Inc. ++# Copyright (C) 2011-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2961028,12 +2977657,12 @@ index 0000000..c3d0410 + diff --git a/ld/testsuite/ld-undefined/entry.exp b/ld/testsuite/ld-undefined/entry.exp new file mode 100644 -index 0000000..d90fbbb +index 0000000..1f795cd --- /dev/null +++ b/ld/testsuite/ld-undefined/entry.exp @@ -0,0 +1,35 @@ +# Expect script for ld --entry tests -+# Copyright (C) 2009 Free Software Foundation ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2961095,15 +2977724,14 @@ index 0000000..ef2aec6 +} diff --git a/ld/testsuite/ld-undefined/undefined.exp b/ld/testsuite/ld-undefined/undefined.exp new file mode 100644 -index 0000000..49af737 +index 0000000..12afc03 --- /dev/null +++ b/ld/testsuite/ld-undefined/undefined.exp -@@ -0,0 +1,148 @@ +@@ -0,0 +1,147 @@ +# Test that the linker reports undefined symbol errors correctly. +# By Ian Lance Taylor, Cygnus Support +# -+# Copyright 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, -+# 2005, 2007, 2008, 2010, 2011 Free Software Foundation, Inc. ++# Copyright (C) 1995-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2961249,13 +2977877,12 @@ index 0000000..49af737 +checkund $ml $testline diff --git a/ld/testsuite/ld-undefined/weak-undef.exp b/ld/testsuite/ld-undefined/weak-undef.exp new file mode 100644 -index 0000000..c802a11 +index 0000000..fd25ca9 --- /dev/null +++ b/ld/testsuite/ld-undefined/weak-undef.exp -@@ -0,0 +1,85 @@ +@@ -0,0 +1,84 @@ +# Test handling of weak undefined symbols -+# Copyright 2001, 2002, 2004, 2005, 2007, 2010, 2011, 2012 -+# Free Software Foundation, Inc. ++# Copyright (C) 2001-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2961365,13 +2977992,13 @@ index 0000000..a95bbcf +} diff --git a/ld/testsuite/ld-unique/unique.exp b/ld/testsuite/ld-unique/unique.exp new file mode 100644 -index 0000000..9bc65e0 +index 0000000..a93f9b2 --- /dev/null +++ b/ld/testsuite/ld-unique/unique.exp @@ -0,0 +1,268 @@ +# Expect script for linker support of STB_GNU_UNIQUE symbols +# -+# Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc. ++# Copyright (C) 2009-2014 Free Software Foundation, Inc. +# Contributed by Red Hat. +# +# This file is part of the GNU Binutils. @@ -2961747,11 +2978374,11 @@ index 0000000..7eaae41 + ld.bu lo(odd)[r1],r2 diff --git a/ld/testsuite/ld-v850/v850.exp b/ld/testsuite/ld-v850/v850.exp new file mode 100644 -index 0000000..2a2f9ae +index 0000000..7fff03f --- /dev/null +++ b/ld/testsuite/ld-v850/v850.exp @@ -0,0 +1,21 @@ -+# Copyright 2007 Free Software Foundtaion, Inc. ++# Copyright (C) 2007-2014 Free Software Foundation, Inc. +# This file is part of the GNU Binutils. +# +# This program is free software; you can redistribute it and/or modify @@ -2961932,13 +2978559,13 @@ index 0000000..a548dbf + .size internal_foo, . - internal_foo diff --git a/ld/testsuite/ld-vax-elf/export-class.exp b/ld/testsuite/ld-vax-elf/export-class.exp new file mode 100644 -index 0000000..83df770 +index 0000000..70e0d6d --- /dev/null +++ b/ld/testsuite/ld-vax-elf/export-class.exp @@ -0,0 +1,80 @@ +# Expect script for symbol export classes, VAX variation. +# -+# Copyright 2013 Free Software Foundation, Inc. ++# Copyright (C) 2013-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2962472,12 +2979099,12 @@ index 0000000..b1fa8f0 + .size foo_local, . - foo_local diff --git a/ld/testsuite/ld-vax-elf/vax-elf.exp b/ld/testsuite/ld-vax-elf/vax-elf.exp new file mode 100644 -index 0000000..440e2da +index 0000000..e93bae0 --- /dev/null +++ b/ld/testsuite/ld-vax-elf/vax-elf.exp @@ -0,0 +1,107 @@ +# Expect script for VAX ELF linker tests -+# Copyright 2012 Free Software Foundation, Inc. ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2962914,143 +2979541,143 @@ index 0000000..1a5c4e3 +} diff --git a/ld/testsuite/ld-versados/t1.ook b/ld/testsuite/ld-versados/t1.ook new file mode 100644 -index 0000000..08361fd +index 0000000..3984b94 --- /dev/null +++ b/ld/testsuite/ld-versados/t1.ook @@ -0,0 +1,133 @@ -+S00C000074312E6F75742E6F6BC0 -+S118000000000A205341464553544F52452041202020202052BE -+S118001531332E33202020202020205231332E32202020202077 -+S118002A202000B5E86600B5E9B11DA15B9900001F0000000A50 -+S118003F640000003E0000005C00A800BA00F000040001000251 -+S1180054000000000000000000000006004031CF52544C4942D0 -+S1180069434F4E0004E5EC52544C4942434F4E0004E5ED5254F0 -+S118007E4C4942434F4E004031D252544C4942434F4E00000A08 -+S11800937D52544C49425354520010A4A852544C494246494CAD -+S11800A8000200B5E86D0000016000B5E873000002540002006A -+S11800BDB5E937534146455052494E5420000006000200080079 -+S11800D20000034200B5E86E494E4954534146455354000002C9 -+S11800E71800000E00000009020030000000004E56FFD8BA8FDB -+S11800FC63062E4E6100001641FA003243EEFFD8702612D85149 -+S1180111C8FFFC4E5E4E752B57FFF22F3C0000000A6000000259 -+S11801263B6F0002FFF62F2D00382F2D00344E4C4E4A434F50E7 -+S118013B5952494748542054656C65666F6E204142204C204D6B -+S1180150204572696373736F6E2C2031393933004E56FFFCBAB5 -+S11801658F63042E4E61AC202E000C06800000000C4E7656807C -+S118017A4E760280FFFFFFFC4AD56604610000B02D40FFFC200B -+S118018F6C003A2208242C003694814E7604820000000C4E76D2 -+S11801A44AD566046100008EB0826E0C0CAE00000001000C6CEB -+S11801B900000C207C0000000061000060206C003A200866046C -+S11801CE610000762208D2AEFFFC68046100005C2081216E0043 -+S11801E3100004216E000C0008220806810000000C68046100C2 -+S11801F800402D4100142950003A206C003A24086604610000BC -+S118020D3A429042A8000442A800084E5E225F285F508F4EE922 -+S118022200022B5FFFF24E5ED1DF285F2F082B48FFF2D0D04EDA -+S1180237D02B57FFF22F3C0000000E6000FEE22B57FFF22F3CD4 -+S118024C000000106000FED44E56FFFCBA8F63062E4E6100FE2B -+S1180261B82D6C0032FFFC600000122B5FFFF24FEEFFFC42AEF1 -+S1180276FFFC600000824AAEFFFC6700007A206EFFFC200866A7 -+S118028B00000461B622280004B2AE001067000062220802810B -+S11802A0000000034A8166402208226C003A2409B2826E3426B6 -+S11802B510280806840000000C68046100FF76B6846D2026101B -+S11802CA280896844E7604830000000C4E764AD566046100FFCD -+S11802DF5AB6A800086C0000046182206EFFFC20086604610077 -+S11802F4FF522D50FFFC60804AAEFFFC6700002C206EFFFC2019 -+S11803090866046100FF38226E000C22A80008220806810000B2 -+S118031E000C68046100FF142D4100146000000C206E000C4210 -+S11803339042AE00144E5E205F285F508F4ED04FEDFF00707F44 -+S1180348204F425851C8FFFC486DFF081F3C00043F3C00019F49 -+S118035DFC0000000C224F45FA04FE22DA22DA22DA266C00281F -+S11803722F0C286C002C4EAB0068486DFFB8486DFFB42F0C20E7 -+S11803876C0000286C00044E909FFC000000522F2DFFC62F0C32 -+S118039C206C0008286C000C4E907052266C00204EAB001E416A -+S11803B1FA04BE266C00204EAB007E266C00204EAB009E41EDD7 -+S11803C6FFBA266C00204EAB007E266C00204EAB009E1F3C0098 -+S11803DB283F3C0001266C00204EAB009E9FFC00000052302DD2 -+S11803F0FFCA48C02F002F0C206C0008286C000C4E90705226BF -+S11804056C00204EAB001E266C00204EAB009E41FA045E266CC3 -+S118041A00204EAB007E266C00204EAB009E41EDFF9E70162672 -+S118042F6C00204EAB00CA600000162B5FFFF24FEDFF002B7C92 -+S118044400000001FFB4600003E4486DFF089FFC0000005220DB -+S11804594F43EDFF9E3019725092406F024241D04130C06F0A23 -+S118046E5340E24030D951C8FFFC9FFC00000052224F45FA0303 -+S1180483F632DA266C00282F0C286C002C4EAB0050FFAA486D02 -+S1180498FF08266C00282F0C286C002C4EAB00A0FF9642ADFF73 -+S11804AD002B6C0032FF04487A03C43F3CFFFF486DFF08266C1A -+S11804C200282F0C286C002C4EAB00C0FF70486DFF08266C0088 -+S11804D7282F0C286C002C4EAB00A4FF5C600000782B5FFFF29E -+S11804EC4FEDFF00487A03BA3F3CFFFF486DFF08266C00282F1F -+S11805010C286C002C4EAB00C0FF349FFC00000052206DFF04AC -+S118051620082F002F0C206C0010286C00144E902F0F3F3CFF60 -+S118052BFF486DFF08266C00282F0C286C002C4EAB00C0FF008F -+S1180540DFFC00000052486DFF08266C00282F0C286C002C4EB6 -+S1180555AB00A4FEE6600001F0206DFF042008660261804A902E -+S118056A6700016A22100281000000034A81664A2210242C00F1 -+S118057F3604820000000C68046100FCAEB2826E3422102408F0 -+S118059406820000000C68046100FC9AB2826D202210240892A6 -+S11805A9824E7604810000000C4E764AD566046100FC7EB2A8E0 -+S11805BE00086C0000066100FF22206DFF04200866046100FFA6 -+S11805D31622280008D2ADFF0068046100FC582B41FF009FFC02 -+S11805E80000005224082F022F0C206C0010286C00144E902FBF -+S11805FD0F3F3C000C486DFF08266C00282F0C286C002C4EABE5 -+S118061200C0FE2ADFFC00000052206DFF04200866046100FE39 -+S1180627C22F2800043F3C000C486DFF08266C00282F0C286CD1 -+S118063C002C4EAB00BCFDFC206DFF04200866046100FE9A2F81 -+S11806512800083F3C000C486DFF08266C00282F0C286C002C68 -+S11806664EAB00BCFDD49FFC00000052206DFF04200866046185 -+S118067B00FE6C22102F012F0C206C0010286C00144E902F0FFF -+S11806903F3C000C486DFF08266C00282F0C286C002C4EAB0060 -+S11806A5C0FD98DFFC00000052486DFF08266C00282F0C286C75 -+S11806BA002C4EAB00A4FD7E206DFF04200866046100FE1C2B1B -+S11806CF50FF046000FE8A206C003AB1EDFF046700006C487ADB -+S11806E401E83F3CFFFF486DFF08266C00282F0C286C002C4EDC -+S11806F9AB00C0FD429FFC00000052206DFF0420082F002F0C2F -+S118070E206C0010286C00144E902F0F3F3CFFFF486DFF082617 -+S11807236C00282F0C286C002C4EAB00C0FD0EDFFC000000523D -+S1180738486DFF08266C00282F0C286C002C4EAB00A4FCF44862 -+S118074D7A01983F3CFFFF486DFF08266C00282F0C286C002C96 -+S11807624EAB00C0FCD8486DFF08266C00282F0C286C002C4E32 -+S1180777AB00A4FCC4487A016A3F3CFFFF486DFF08266C00283E -+S118078C2F0C286C002C4EAB00C0FCA8486DFF08266C00282F57 -+S11807A10C286C002C4EAB00A4FC94206DFF0420080680000008 -+S11807B600184E76222C003692804E760281FFFFFFFC4AD566F3 -+S11807CB046100FA6A2F013F3C000C486DFF08266C00282F0CE4 -+S11807E0286C002C4EAB00BCFC562F2DFF003F3C000C486DFFA3 -+S11807F508266C00282F0C286C002C4EAB00BCFC3A486DFF0887 -+S118080A266C00282F0C286C002C4EAB00A4FC26486DFF081F86 -+S118081F3C0001266C00282F0C286C002C4EAB0054486DFFB815 -+S1180834486DFFB42F0C206C0018286C001C4E90486DFF0842D8 -+S118084927266C00282F0C286C002C4EAB005442A72F2D0038F0 -+S118085E2F2D00344E4A000A4631202020202020202000023A9C -+S11808733A0002293A0000003020202020204164647265737337 -+S1180888202020204964656E746974792020202020202020533A -+S118089D697A6520202020202020204E657874001D496E7661B0 -+S11808B26C6964207365676D656E74207374617274696E672035 -+S11808C761743A202000185365676D656E74206C69737420637F -+S11808DC6F727275707465643A2000000018202020417661693B -+S11808F16C61626C652020202020202020557365644FEDFFF230 -+S11809069FFC0000000A6100015641EC003020DF20DF30DF20F1 -+S118091B2C003256804E760280FFFFFFFC4AD566046100F90A63 -+S1180930294000322940003A6000003E2B5FFFF24FEDFFF2200A -+S11809452C003256804E760280FFFFFFFC4AD566046100F8E064 -+S118095A2940003A206C003A220866046100F8DE429042A80094 -+S118096F0442A800086000009E4A2C00306700001A206C003A8E -+S11809842008660261B2429042A8000442A800086000007E2007 -+S11809996C003A20086602619A4A906700006E221002810000B0 -+S11809AE00034A81664A2210242C003604820000000C6804619B -+S11809C300F874B2826E342210240806820000000C680461001A -+S11809D8F860B2826D202210240892824E7604810000000C4ED8 -+S11809ED764AD566046100F844B2A800086C0000066100FF3CE5 -+S1180A02206C003A200866046100FF302950003A608442A72F44 -+S1180A172D00382F2D00344E4A4E560000518F42A71F3C000E63 -+S1180A2C4267487A0012426742272F3C00B5E86E4E49000E50B7 -+S1180A418F4E5E205F285F4EE80002207C0000000060042B5F99 -+S1180A56FFF24E5ED1DF285F2F08D0D04ED043FA0004D3FC00AE -+S1180A6B02704E2F49000A43FA0004D3FC000000402F49000662 -+S1180A8041FA0004D1FCFFFFF57A202800566600002222099201 -+S1180A95882141005642812448D25AB5C96DFA4441D368005AAE -+S1110AAA1F7C000100044E75422F00044E759F -+S9030000FC ++S00C000074312E6F75742E6F6BC0 ++S118000000000A205341464553544F52452041202020202052BE ++S118001531332E33202020202020205231332E32202020202077 ++S118002A202000B5E86600B5E9B11DA15B9900001F0000000A50 ++S118003F640000003E0000005C00A800BA00F000040001000251 ++S1180054000000000000000000000006004031CF52544C4942D0 ++S1180069434F4E0004E5EC52544C4942434F4E0004E5ED5254F0 ++S118007E4C4942434F4E004031D252544C4942434F4E00000A08 ++S11800937D52544C49425354520010A4A852544C494246494CAD ++S11800A8000200B5E86D0000016000B5E873000002540002006A ++S11800BDB5E937534146455052494E5420000006000200080079 ++S11800D20000034200B5E86E494E4954534146455354000002C9 ++S11800E71800000E00000009020030000000004E56FFD8BA8FDB ++S11800FC63062E4E6100001641FA003243EEFFD8702612D85149 ++S1180111C8FFFC4E5E4E752B57FFF22F3C0000000A6000000259 ++S11801263B6F0002FFF62F2D00382F2D00344E4C4E4A434F50E7 ++S118013B5952494748542054656C65666F6E204142204C204D6B ++S1180150204572696373736F6E2C2031393933004E56FFFCBAB5 ++S11801658F63042E4E61AC202E000C06800000000C4E7656807C ++S118017A4E760280FFFFFFFC4AD56604610000B02D40FFFC200B ++S118018F6C003A2208242C003694814E7604820000000C4E76D2 ++S11801A44AD566046100008EB0826E0C0CAE00000001000C6CEB ++S11801B900000C207C0000000061000060206C003A200866046C ++S11801CE610000762208D2AEFFFC68046100005C2081216E0043 ++S11801E3100004216E000C0008220806810000000C68046100C2 ++S11801F800402D4100142950003A206C003A24086604610000BC ++S118020D3A429042A8000442A800084E5E225F285F508F4EE922 ++S118022200022B5FFFF24E5ED1DF285F2F082B48FFF2D0D04EDA ++S1180237D02B57FFF22F3C0000000E6000FEE22B57FFF22F3CD4 ++S118024C000000106000FED44E56FFFCBA8F63062E4E6100FE2B ++S1180261B82D6C0032FFFC600000122B5FFFF24FEEFFFC42AEF1 ++S1180276FFFC600000824AAEFFFC6700007A206EFFFC200866A7 ++S118028B00000461B622280004B2AE001067000062220802810B ++S11802A0000000034A8166402208226C003A2409B2826E3426B6 ++S11802B510280806840000000C68046100FF76B6846D2026101B ++S11802CA280896844E7604830000000C4E764AD566046100FFCD ++S11802DF5AB6A800086C0000046182206EFFFC20086604610077 ++S11802F4FF522D50FFFC60804AAEFFFC6700002C206EFFFC2019 ++S11803090866046100FF38226E000C22A80008220806810000B2 ++S118031E000C68046100FF142D4100146000000C206E000C4210 ++S11803339042AE00144E5E205F285F508F4ED04FEDFF00707F44 ++S1180348204F425851C8FFFC486DFF081F3C00043F3C00019F49 ++S118035DFC0000000C224F45FA04FE22DA22DA22DA266C00281F ++S11803722F0C286C002C4EAB0068486DFFB8486DFFB42F0C20E7 ++S11803876C0000286C00044E909FFC000000522F2DFFC62F0C32 ++S118039C206C0008286C000C4E907052266C00204EAB001E416A ++S11803B1FA04BE266C00204EAB007E266C00204EAB009E41EDD7 ++S11803C6FFBA266C00204EAB007E266C00204EAB009E1F3C0098 ++S11803DB283F3C0001266C00204EAB009E9FFC00000052302DD2 ++S11803F0FFCA48C02F002F0C206C0008286C000C4E90705226BF ++S11804056C00204EAB001E266C00204EAB009E41FA045E266CC3 ++S118041A00204EAB007E266C00204EAB009E41EDFF9E70162672 ++S118042F6C00204EAB00CA600000162B5FFFF24FEDFF002B7C92 ++S118044400000001FFB4600003E4486DFF089FFC0000005220DB ++S11804594F43EDFF9E3019725092406F024241D04130C06F0A23 ++S118046E5340E24030D951C8FFFC9FFC00000052224F45FA0303 ++S1180483F632DA266C00282F0C286C002C4EAB0050FFAA486D02 ++S1180498FF08266C00282F0C286C002C4EAB00A0FF9642ADFF73 ++S11804AD002B6C0032FF04487A03C43F3CFFFF486DFF08266C1A ++S11804C200282F0C286C002C4EAB00C0FF70486DFF08266C0088 ++S11804D7282F0C286C002C4EAB00A4FF5C600000782B5FFFF29E ++S11804EC4FEDFF00487A03BA3F3CFFFF486DFF08266C00282F1F ++S11805010C286C002C4EAB00C0FF349FFC00000052206DFF04AC ++S118051620082F002F0C206C0010286C00144E902F0F3F3CFF60 ++S118052BFF486DFF08266C00282F0C286C002C4EAB00C0FF008F ++S1180540DFFC00000052486DFF08266C00282F0C286C002C4EB6 ++S1180555AB00A4FEE6600001F0206DFF042008660261804A902E ++S118056A6700016A22100281000000034A81664A2210242C00F1 ++S118057F3604820000000C68046100FCAEB2826E3422102408F0 ++S118059406820000000C68046100FC9AB2826D202210240892A6 ++S11805A9824E7604810000000C4E764AD566046100FC7EB2A8E0 ++S11805BE00086C0000066100FF22206DFF04200866046100FFA6 ++S11805D31622280008D2ADFF0068046100FC582B41FF009FFC02 ++S11805E80000005224082F022F0C206C0010286C00144E902FBF ++S11805FD0F3F3C000C486DFF08266C00282F0C286C002C4EABE5 ++S118061200C0FE2ADFFC00000052206DFF04200866046100FE39 ++S1180627C22F2800043F3C000C486DFF08266C00282F0C286CD1 ++S118063C002C4EAB00BCFDFC206DFF04200866046100FE9A2F81 ++S11806512800083F3C000C486DFF08266C00282F0C286C002C68 ++S11806664EAB00BCFDD49FFC00000052206DFF04200866046185 ++S118067B00FE6C22102F012F0C206C0010286C00144E902F0FFF ++S11806903F3C000C486DFF08266C00282F0C286C002C4EAB0060 ++S11806A5C0FD98DFFC00000052486DFF08266C00282F0C286C75 ++S11806BA002C4EAB00A4FD7E206DFF04200866046100FE1C2B1B ++S11806CF50FF046000FE8A206C003AB1EDFF046700006C487ADB ++S11806E401E83F3CFFFF486DFF08266C00282F0C286C002C4EDC ++S11806F9AB00C0FD429FFC00000052206DFF0420082F002F0C2F ++S118070E206C0010286C00144E902F0F3F3CFFFF486DFF082617 ++S11807236C00282F0C286C002C4EAB00C0FD0EDFFC000000523D ++S1180738486DFF08266C00282F0C286C002C4EAB00A4FCF44862 ++S118074D7A01983F3CFFFF486DFF08266C00282F0C286C002C96 ++S11807624EAB00C0FCD8486DFF08266C00282F0C286C002C4E32 ++S1180777AB00A4FCC4487A016A3F3CFFFF486DFF08266C00283E ++S118078C2F0C286C002C4EAB00C0FCA8486DFF08266C00282F57 ++S11807A10C286C002C4EAB00A4FC94206DFF0420080680000008 ++S11807B600184E76222C003692804E760281FFFFFFFC4AD566F3 ++S11807CB046100FA6A2F013F3C000C486DFF08266C00282F0CE4 ++S11807E0286C002C4EAB00BCFC562F2DFF003F3C000C486DFFA3 ++S11807F508266C00282F0C286C002C4EAB00BCFC3A486DFF0887 ++S118080A266C00282F0C286C002C4EAB00A4FC26486DFF081F86 ++S118081F3C0001266C00282F0C286C002C4EAB0054486DFFB815 ++S1180834486DFFB42F0C206C0018286C001C4E90486DFF0842D8 ++S118084927266C00282F0C286C002C4EAB005442A72F2D0038F0 ++S118085E2F2D00344E4A000A4631202020202020202000023A9C ++S11808733A0002293A0000003020202020204164647265737337 ++S1180888202020204964656E746974792020202020202020533A ++S118089D697A6520202020202020204E657874001D496E7661B0 ++S11808B26C6964207365676D656E74207374617274696E672035 ++S11808C761743A202000185365676D656E74206C69737420637F ++S11808DC6F727275707465643A2000000018202020417661693B ++S11808F16C61626C652020202020202020557365644FEDFFF230 ++S11809069FFC0000000A6100015641EC003020DF20DF30DF20F1 ++S118091B2C003256804E760280FFFFFFFC4AD566046100F90A63 ++S1180930294000322940003A6000003E2B5FFFF24FEDFFF2200A ++S11809452C003256804E760280FFFFFFFC4AD566046100F8E064 ++S118095A2940003A206C003A220866046100F8DE429042A80094 ++S118096F0442A800086000009E4A2C00306700001A206C003A8E ++S11809842008660261B2429042A8000442A800086000007E2007 ++S11809996C003A20086602619A4A906700006E221002810000B0 ++S11809AE00034A81664A2210242C003604820000000C6804619B ++S11809C300F874B2826E342210240806820000000C680461001A ++S11809D8F860B2826D202210240892824E7604810000000C4ED8 ++S11809ED764AD566046100F844B2A800086C0000066100FF3CE5 ++S1180A02206C003A200866046100FF302950003A608442A72F44 ++S1180A172D00382F2D00344E4A4E560000518F42A71F3C000E63 ++S1180A2C4267487A0012426742272F3C00B5E86E4E49000E50B7 ++S1180A418F4E5E205F285F4EE80002207C0000000060042B5F99 ++S1180A56FFF24E5ED1DF285F2F08D0D04ED043FA0004D3FC00AE ++S1180A6B02704E2F49000A43FA0004D3FC000000402F49000662 ++S1180A8041FA0004D1FCFFFFF57A202800566600002222099201 ++S1180A95882141005642812448D25AB5C96DFA4441D368005AAE ++S1110AAA1F7C000100044E75422F00044E759F ++S9030000FC diff --git a/ld/testsuite/ld-versados/t2-1.ro b/ld/testsuite/ld-versados/t2-1.ro new file mode 100644 index 0000000..633a7cc @@ -2963352,117 +2979979,117 @@ index 0000000..5e1e413 +} diff --git a/ld/testsuite/ld-versados/t2.ook b/ld/testsuite/ld-versados/t2.ook new file mode 100644 -index 0000000..db50659 +index 0000000..03f24a5 --- /dev/null +++ b/ld/testsuite/ld-versados/t2.ook @@ -0,0 +1,99 @@ -+S0120000696E6974746573745F6570632E7372CF -+S118000000000000494E495454455354202050413035202052AB -+S118001531332E33202020202020205231332E32202020202077 -+S118002A202000934B5B00B5E6C11B089DD600005400000005F9 -+S118003F5A00000048005C00A60000010A0126000400010002CB -+S1180054009000000000000000000002004020200000494F5F8A -+S11800695245534552564152544C4942434F4E0040484501003B -+S118007E505F414C4C202020202052544C4942434F4E010000E3 -+S118009300009C01000000000000085345504152415445000852 -+S11800A80008004031CF52544C4942434F4E0004E5EC52544CD3 -+S11800BD4942434F4E00B5E86D5341464553544F5200004F28D7 -+S11800D253595354454D494D00B5E8735341464553544F520023 -+S11800E74031D252544C4942434F4E00000A7D52544C49425309 -+S11800FC54520010A4A852544C494246494C000100B5E6C049EC -+S11801114E495454455354202000000616020008000000023210 -+S11801260048000000004E56FFF0BA8F63062E4E610000BC4159 -+S118013BFA00F443EEFFF032D82D7C00000001FFFC206E000858 -+S118015020086604610000BA222EFFFC53814A816C046100002E -+S11801659E2248D3E9FFFC41F01800B3C863EE4A1066000006E7 -+S118017A6000006241EEFFF0266C00384EAB007E206E00082095 -+S118018F0866046100007C222EFFFC53814A816C0461000060ED -+S11801A42248D3E9FFFC41F01800B3C863EE1F103F3C0001263B -+S11801B96C00384EAB009E41EEFFF0700C266C00384EAB00CACB -+S11801CE52AEFFFC0CAE0000000AFFFC6F00FF7041EEFFF0431F -+S11801E3EE000C22D822D822D84E5E205F588F4ED02B57FFF278 -+S11801F82F3C0000000A6000001E2B57FFF22F3C0000000F60AE -+S118020D0000102B57FFF22F3C00000010600000023B6F0002CC -+S1180222FFF62F2D00382F2D00344E4C4E4A00004FEDFEEA2034 -+S11802373C0000008A204F425851C8FFFC486DFEEA1F3C0004CF -+S118024C3F3C00019FFC0000000C224F45FA02D422DA22DA22D6 -+S1180261DA266C00402F0C286C00444EAB0068486DFFB8486D43 -+S1180276FFB42F0C206C0008286C000C4E909FFC000000522F53 -+S118028B2DFFC62F0C206C0010286C00144E907052266C00387F -+S11802A04EAB001E41FA0294266C00384EAB007E266C00384E04 -+S11802B5AB009E41EDFFBA266C00384EAB007E266C00384EABFC -+S11802CA009E1F3C00283F3C0001266C00384EAB009E9FFC0082 -+S11802DF000052302DFFCA48C02F002F0C206C0010286C0014D8 -+S11802F44E907052266C00384EAB001E266C00384EAB009E41CE -+S1180309FA0234266C00384EAB007E266C00384EAB009E41EDDB -+S118031EFF807016266C00384EAB00CA9FFC0000000E61000228 -+S11803332841EDFF9E20DF20DF20DF30DF4A2DFF9E6700003AFD -+S1180348598F2F2DFFA02F2DFFA82F0C206C0018286C001C4ED9 -+S118035D9001B82B5FFF9A2F2DFF9A2F2DFFA42F2DFFA82F0CE9 -+S1180372206C0020286C00244E9060000034598F2F2DFFA04871 -+S11803876DFFA82F0C206C0028286C002C4E902B5FFF962F2D41 -+S118039CFFA42F2DFF962F2DFFA82F0C206C0020286C00244EC4 -+S11803B190486DFEEA9FFC00000052204F43EDFF8030197250F0 -+S11803C692406F024241D04130C06F0A5340E24030D951C8FF08 -+S11803DBFC9FFC00000052224F45FA015C32DA266C00402F0CFA -+S11803F0286C00444EAB0050012C486DFEEA266C00402F0C28D4 -+S11804056C00444EAB00A00118487A01343F3CFFFF486DFEEA6F -+S118041A266C00402F0C286C00444EAB00C000FC486DFEEA266C -+S118042F6C00402F0C286C00444EAB00A400E842ADFFB02B7C2B -+S118044400000001FFAC598F2F2DFFAC6100017E2B5FFFB02BC0 -+S118045940FFB02F2DFFAC3F3C000A486DFEEA266C00402F0C65 -+S118046E286C00444EAB00BC00AE9FFC0000000C2F2DFFB06127 -+S118048300FCA82F0F3F3C000A486DFEEA266C00402F0C286CBB -+S118049800444EAB00C00086DFFC0000000C486DFEEA266C00B2 -+S11804AD402F0C286C00444EAB00A4006C52ADFFAC0CAD000077 -+S11804C2000AFFAC6F82486DFEEA1F3C0001266C00402F0C284D -+S11804D76C00444EAB0054486DFFB8486DFFB42F0C206C003044 -+S11804EC286C00344E90486DFEEA4227266C00402F0C286C00AA -+S1180501444EAB005442A72F2D00382F2D00344E4A2B57FFF238 -+S11805162F3C0000000C6000FD002B57FFF22F3C000000646056 -+S118052B00FCF2000A4631202020202020202000023A3A0002D0 -+S1180540293A000000142020202020204361736520202020521D -+S11805556573756C7441FA0004D1FCFFFFFAA02028003C43FAFB -+S118056A0004D3FC000001D645FA0004D5FC0000025E260A58D2 -+S118057F8AD0885580222800566600002E2408265AD5B0B8008F -+S1180594B5C06DF6220992882141005642812648D25BB7C96D2E -+S11805A9FA4441D368005A123C00016000000442411F4100048B -+S11805BE2F68003400062F49000A96892F43000E4E754E56FFCC -+S11805D3F0202E000847FA0004D7FC000001A6220B41FA00049E -+S11805E8D1FC000001B62D58FFF02D58FFF42D58FFF82D50FF92 -+S11805FDFC53807408B4806500012C41FA0004D1FC0000000EBA -+S1180612D080303008004EFB00020012002200320042004800DC -+S118062758006C00A000DC41FA0004D1FC0000011820106000C5 -+S118063C010247FA0004D7FC0000010C200B600000F241FA00C5 -+S118065104D1FC000001102010600000E22001600000DC47FA9E -+S11806660004D7FC00000120200B600000CC43FA0004D3FC001C -+S118067B0000FA41E9000C2010600000B8242EFFF447FA000464 -+S1180690D7FC000000FEB48B6600001247FA0004D7FC000001B0 -+S11806A514200B6000009447FA0004D7FC0000010A200B60005B -+S11806BA008441FA0004D1FC0000008A205047FA0004D7FC0085 -+S11806CF000082B1CB6600001247FA0004D7FC000000E0200B79 -+S11806E46000005847FA0004D7FC000000D2200B600000484147 -+S11806F9FA0004D1FC0000004E43FA0004D3FC0000003EB3D0FE -+S118070E6600001247FA0004D7FC000000AE200B6000001E47A4 -+S1180723FA0004D7FC000000A6200B6000000E47FA0004D7FC95 -+S118073800000098200B4E5E4E740004000053756E65000000D8 -+S118074D0007464F74746F00000000000A0000000C50656C6CFD -+S118076265000000075E5374696E61004B6172696E00000000C0 -+S11807770500000768000000030000076E5075747465004B61BF -+S118078C6C6C65005374696E613100004B6172696E31000000C1 -+S11807A1000033000007900000001F0000079878797A7A0000D2 -+S11807B64F6C6C650000370038005065746572005376756C6C19 -+S11807CB6F00003900536C75740000000000000000074C000072 -+S11507E007640000077800000780000007A4000007AC34 -+S9030000FC ++S0120000696E6974746573745F6570632E7372CF ++S118000000000000494E495454455354202050413035202052AB ++S118001531332E33202020202020205231332E32202020202077 ++S118002A202000934B5B00B5E6C11B089DD600005400000005F9 ++S118003F5A00000048005C00A60000010A0126000400010002CB ++S1180054009000000000000000000002004020200000494F5F8A ++S11800695245534552564152544C4942434F4E0040484501003B ++S118007E505F414C4C202020202052544C4942434F4E010000E3 ++S118009300009C01000000000000085345504152415445000852 ++S11800A80008004031CF52544C4942434F4E0004E5EC52544CD3 ++S11800BD4942434F4E00B5E86D5341464553544F5200004F28D7 ++S11800D253595354454D494D00B5E8735341464553544F520023 ++S11800E74031D252544C4942434F4E00000A7D52544C49425309 ++S11800FC54520010A4A852544C494246494C000100B5E6C049EC ++S11801114E495454455354202000000616020008000000023210 ++S11801260048000000004E56FFF0BA8F63062E4E610000BC4159 ++S118013BFA00F443EEFFF032D82D7C00000001FFFC206E000858 ++S118015020086604610000BA222EFFFC53814A816C046100002E ++S11801659E2248D3E9FFFC41F01800B3C863EE4A1066000006E7 ++S118017A6000006241EEFFF0266C00384EAB007E206E00082095 ++S118018F0866046100007C222EFFFC53814A816C0461000060ED ++S11801A42248D3E9FFFC41F01800B3C863EE1F103F3C0001263B ++S11801B96C00384EAB009E41EEFFF0700C266C00384EAB00CACB ++S11801CE52AEFFFC0CAE0000000AFFFC6F00FF7041EEFFF0431F ++S11801E3EE000C22D822D822D84E5E205F588F4ED02B57FFF278 ++S11801F82F3C0000000A6000001E2B57FFF22F3C0000000F60AE ++S118020D0000102B57FFF22F3C00000010600000023B6F0002CC ++S1180222FFF62F2D00382F2D00344E4C4E4A00004FEDFEEA2034 ++S11802373C0000008A204F425851C8FFFC486DFEEA1F3C0004CF ++S118024C3F3C00019FFC0000000C224F45FA02D422DA22DA22D6 ++S1180261DA266C00402F0C286C00444EAB0068486DFFB8486D43 ++S1180276FFB42F0C206C0008286C000C4E909FFC000000522F53 ++S118028B2DFFC62F0C206C0010286C00144E907052266C00387F ++S11802A04EAB001E41FA0294266C00384EAB007E266C00384E04 ++S11802B5AB009E41EDFFBA266C00384EAB007E266C00384EABFC ++S11802CA009E1F3C00283F3C0001266C00384EAB009E9FFC0082 ++S11802DF000052302DFFCA48C02F002F0C206C0010286C0014D8 ++S11802F44E907052266C00384EAB001E266C00384EAB009E41CE ++S1180309FA0234266C00384EAB007E266C00384EAB009E41EDDB ++S118031EFF807016266C00384EAB00CA9FFC0000000E61000228 ++S11803332841EDFF9E20DF20DF20DF30DF4A2DFF9E6700003AFD ++S1180348598F2F2DFFA02F2DFFA82F0C206C0018286C001C4ED9 ++S118035D9001B82B5FFF9A2F2DFF9A2F2DFFA42F2DFFA82F0CE9 ++S1180372206C0020286C00244E9060000034598F2F2DFFA04871 ++S11803876DFFA82F0C206C0028286C002C4E902B5FFF962F2D41 ++S118039CFFA42F2DFF962F2DFFA82F0C206C0020286C00244EC4 ++S11803B190486DFEEA9FFC00000052204F43EDFF8030197250F0 ++S11803C692406F024241D04130C06F0A5340E24030D951C8FF08 ++S11803DBFC9FFC00000052224F45FA015C32DA266C00402F0CFA ++S11803F0286C00444EAB0050012C486DFEEA266C00402F0C28D4 ++S11804056C00444EAB00A00118487A01343F3CFFFF486DFEEA6F ++S118041A266C00402F0C286C00444EAB00C000FC486DFEEA266C ++S118042F6C00402F0C286C00444EAB00A400E842ADFFB02B7C2B ++S118044400000001FFAC598F2F2DFFAC6100017E2B5FFFB02BC0 ++S118045940FFB02F2DFFAC3F3C000A486DFEEA266C00402F0C65 ++S118046E286C00444EAB00BC00AE9FFC0000000C2F2DFFB06127 ++S118048300FCA82F0F3F3C000A486DFEEA266C00402F0C286CBB ++S118049800444EAB00C00086DFFC0000000C486DFEEA266C00B2 ++S11804AD402F0C286C00444EAB00A4006C52ADFFAC0CAD000077 ++S11804C2000AFFAC6F82486DFEEA1F3C0001266C00402F0C284D ++S11804D76C00444EAB0054486DFFB8486DFFB42F0C206C003044 ++S11804EC286C00344E90486DFEEA4227266C00402F0C286C00AA ++S1180501444EAB005442A72F2D00382F2D00344E4A2B57FFF238 ++S11805162F3C0000000C6000FD002B57FFF22F3C000000646056 ++S118052B00FCF2000A4631202020202020202000023A3A0002D0 ++S1180540293A000000142020202020204361736520202020521D ++S11805556573756C7441FA0004D1FCFFFFFAA02028003C43FAFB ++S118056A0004D3FC000001D645FA0004D5FC0000025E260A58D2 ++S118057F8AD0885580222800566600002E2408265AD5B0B8008F ++S1180594B5C06DF6220992882141005642812648D25BB7C96D2E ++S11805A9FA4441D368005A123C00016000000442411F4100048B ++S11805BE2F68003400062F49000A96892F43000E4E754E56FFCC ++S11805D3F0202E000847FA0004D7FC000001A6220B41FA00049E ++S11805E8D1FC000001B62D58FFF02D58FFF42D58FFF82D50FF92 ++S11805FDFC53807408B4806500012C41FA0004D1FC0000000EBA ++S1180612D080303008004EFB00020012002200320042004800DC ++S118062758006C00A000DC41FA0004D1FC0000011820106000C5 ++S118063C010247FA0004D7FC0000010C200B600000F241FA00C5 ++S118065104D1FC000001102010600000E22001600000DC47FA9E ++S11806660004D7FC00000120200B600000CC43FA0004D3FC001C ++S118067B0000FA41E9000C2010600000B8242EFFF447FA000464 ++S1180690D7FC000000FEB48B6600001247FA0004D7FC000001B0 ++S11806A514200B6000009447FA0004D7FC0000010A200B60005B ++S11806BA008441FA0004D1FC0000008A205047FA0004D7FC0085 ++S11806CF000082B1CB6600001247FA0004D7FC000000E0200B79 ++S11806E46000005847FA0004D7FC000000D2200B600000484147 ++S11806F9FA0004D1FC0000004E43FA0004D3FC0000003EB3D0FE ++S118070E6600001247FA0004D7FC000000AE200B6000001E47A4 ++S1180723FA0004D7FC000000A6200B6000000E47FA0004D7FC95 ++S118073800000098200B4E5E4E740004000053756E65000000D8 ++S118074D0007464F74746F00000000000A0000000C50656C6CFD ++S118076265000000075E5374696E61004B6172696E00000000C0 ++S11807770500000768000000030000076E5075747465004B61BF ++S118078C6C6C65005374696E613100004B6172696E31000000C1 ++S11807A1000033000007900000001F0000079878797A7A0000D2 ++S11807B64F6C6C650000370038005065746572005376756C6C19 ++S11807CB6F00003900536C75740000000000000000074C000072 ++S11507E007640000077800000780000007A4000007AC34 ++S9030000FC diff --git a/ld/testsuite/ld-versados/versados.exp b/ld/testsuite/ld-versados/versados.exp new file mode 100644 -index 0000000..422fd4a +index 0000000..3c0e6b1 --- /dev/null +++ b/ld/testsuite/ld-versados/versados.exp @@ -0,0 +1,102 @@ +# Expect script for ld-versados tests -+# Copyright 1995, 1997, 2005, 2007 Free Software Foundation, Inc. ++# Copyright (C) 1995-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2963759,12 +2980386,12 @@ index 0000000..39420c2 + diff --git a/ld/testsuite/ld-vxworks/vxworks.exp b/ld/testsuite/ld-vxworks/vxworks.exp new file mode 100644 -index 0000000..a305265 +index 0000000..989fa19 --- /dev/null +++ b/ld/testsuite/ld-vxworks/vxworks.exp @@ -0,0 +1,27 @@ +# Expect script for VxWorks tests -+# Copyright 2007 Free Software Foundation, Inc. ++# Copyright (C) 2007-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2963975,6 +2980602,196 @@ index 0000000..bf62981 + call foo4@plt +bnd call foo3@plt + jmp foo4@plt +diff --git a/ld/testsuite/ld-x86-64/bnd-ifunc-1.d b/ld/testsuite/ld-x86-64/bnd-ifunc-1.d +new file mode 100644 +index 0000000..cdcb4f6 +--- /dev/null ++++ b/ld/testsuite/ld-x86-64/bnd-ifunc-1.d +@@ -0,0 +1,7 @@ ++#as: --64 -madd-bnd-prefix ++#ld: -shared -melf_x86_64 ++#objdump: -dw ++ ++#... ++[ ]*[a-f0-9]+: f2 e8 f0 ff ff ff bnd callq 220 <\*ABS\*\+0x228@plt> ++#pass +diff --git a/ld/testsuite/ld-x86-64/bnd-ifunc-1.s b/ld/testsuite/ld-x86-64/bnd-ifunc-1.s +new file mode 100644 +index 0000000..82b64f0 +--- /dev/null ++++ b/ld/testsuite/ld-x86-64/bnd-ifunc-1.s +@@ -0,0 +1,16 @@ ++ .type foo, %gnu_indirect_function ++ .global __GI_foo ++ .hidden __GI_foo ++ .set __GI_foo, foo ++ .text ++.globl foo ++ .type foo, @function ++foo: ++ ret ++ .size foo, .-foo ++.globl bar ++ .type bar, @function ++bar: ++ call __GI_foo@PLT ++ ret ++ .size bar, .-bar +diff --git a/ld/testsuite/ld-x86-64/bnd-ifunc-2.d b/ld/testsuite/ld-x86-64/bnd-ifunc-2.d +new file mode 100644 +index 0000000..43e3356 +--- /dev/null ++++ b/ld/testsuite/ld-x86-64/bnd-ifunc-2.d +@@ -0,0 +1,54 @@ ++#as: --64 -madd-bnd-prefix ++#ld: -shared -melf_x86_64 ++#objdump: -dw ++ ++#... ++0+2d0 <.plt>: ++[ ]*[a-f0-9]+: ff 35 7a 01 20 00 pushq 0x20017a\(%rip\) # 200450 <_GLOBAL_OFFSET_TABLE_\+0x8> ++[ ]*[a-f0-9]+: f2 ff 25 7b 01 20 00 bnd jmpq \*0x20017b\(%rip\) # 200458 <_GLOBAL_OFFSET_TABLE_\+0x10> ++[ ]*[a-f0-9]+: 0f 1f 00 nopl \(%rax\) ++[ ]*[a-f0-9]+: 68 03 00 00 00 pushq \$0x3 ++[ ]*[a-f0-9]+: f2 e9 e5 ff ff ff bnd jmpq 2d0 <\*ABS\*\+0x34c@plt-0x50> ++[ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 68 00 00 00 00 pushq \$0x0 ++[ ]*[a-f0-9]+: f2 e9 d5 ff ff ff bnd jmpq 2d0 <\*ABS\*\+0x34c@plt-0x50> ++[ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 68 01 00 00 00 pushq \$0x1 ++[ ]*[a-f0-9]+: f2 e9 c5 ff ff ff bnd jmpq 2d0 <\*ABS\*\+0x34c@plt-0x50> ++[ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 68 02 00 00 00 pushq \$0x2 ++[ ]*[a-f0-9]+: f2 e9 b5 ff ff ff bnd jmpq 2d0 <\*ABS\*\+0x34c@plt-0x50> ++[ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%rax,%rax,1\) ++ ++Disassembly of section .plt.bnd: ++ ++0+320 <\*ABS\*\+0x34c@plt>: ++[ ]*[a-f0-9]+: f2 ff 25 39 01 20 00 bnd jmpq \*0x200139\(%rip\) # 200460 <_GLOBAL_OFFSET_TABLE_\+0x18> ++[ ]*[a-f0-9]+: 90 nop ++ ++0+328 : ++[ ]*[a-f0-9]+: f2 ff 25 39 01 20 00 bnd jmpq \*0x200139\(%rip\) # 200468 <_GLOBAL_OFFSET_TABLE_\+0x20> ++[ ]*[a-f0-9]+: 90 nop ++ ++0+330 : ++[ ]*[a-f0-9]+: f2 ff 25 39 01 20 00 bnd jmpq \*0x200139\(%rip\) # 200470 <_GLOBAL_OFFSET_TABLE_\+0x28> ++[ ]*[a-f0-9]+: 90 nop ++ ++0+338 <\*ABS\*\+0x340@plt>: ++[ ]*[a-f0-9]+: f2 ff 25 39 01 20 00 bnd jmpq \*0x200139\(%rip\) # 200478 <_GLOBAL_OFFSET_TABLE_\+0x30> ++[ ]*[a-f0-9]+: 90 nop ++ ++Disassembly of section .text: ++ ++0+340 : ++[ ]*[a-f0-9]+: f2 e8 e2 ff ff ff bnd callq 328 ++ ++0+346 : ++[ ]*[a-f0-9]+: f2 e9 ec ff ff ff bnd jmpq 338 <\*ABS\*\+0x340@plt> ++ ++0+34c : ++[ ]*[a-f0-9]+: f2 e8 de ff ff ff bnd callq 330 ++ ++0+352 : ++[ ]*[a-f0-9]+: f2 e9 c8 ff ff ff bnd jmpq 320 <\*ABS\*\+0x34c@plt> ++#pass +diff --git a/ld/testsuite/ld-x86-64/bnd-ifunc-2.s b/ld/testsuite/ld-x86-64/bnd-ifunc-2.s +new file mode 100644 +index 0000000..86470a2 +--- /dev/null ++++ b/ld/testsuite/ld-x86-64/bnd-ifunc-2.s +@@ -0,0 +1,28 @@ ++ .text ++ .globl fct1 ++ .type fct1, @gnu_indirect_function ++ .set fct1,resolve1 ++ .hidden int_fct1 ++ .globl int_fct1 ++ .set int_fct1,fct1 ++ .type resolve1, @function ++resolve1: ++ call func1@PLT ++ .globl g1 ++ .type g1, @function ++g1: ++ jmp int_fct1@PLT ++ ++ .globl fct2 ++ .type fct2, @gnu_indirect_function ++ .set fct2,resolve2 ++ .hidden int_fct2 ++ .globl int_fct2 ++ .set int_fct2,fct2 ++ .type resolve2, @function ++resolve2: ++ call func2@PLT ++ .globl g2 ++ .type g2, @function ++g2: ++ jmp int_fct2@PLT +diff --git a/ld/testsuite/ld-x86-64/bnd-plt-1.d b/ld/testsuite/ld-x86-64/bnd-plt-1.d +new file mode 100644 +index 0000000..3cfe9e6 +--- /dev/null ++++ b/ld/testsuite/ld-x86-64/bnd-plt-1.d +@@ -0,0 +1,55 @@ ++#source: bnd-branch-1.s ++#as: --64 ++#ld: -shared -melf_x86_64 ++#objdump: -dw ++ ++.*: +file format .* ++ ++ ++Disassembly of section .plt: ++ ++0+2b0 <.plt>: ++[ ]*[a-f0-9]+: ff 35 82 01 20 00 pushq 0x200182\(%rip\) # 200438 <_GLOBAL_OFFSET_TABLE_\+0x8> ++[ ]*[a-f0-9]+: f2 ff 25 83 01 20 00 bnd jmpq \*0x200183\(%rip\) # 200440 <_GLOBAL_OFFSET_TABLE_\+0x10> ++[ ]*[a-f0-9]+: 0f 1f 00 nopl \(%rax\) ++[ ]*[a-f0-9]+: 68 00 00 00 00 pushq \$0x0 ++[ ]*[a-f0-9]+: e9 e6 ff ff ff jmpq 2b0 ++[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 68 01 00 00 00 pushq \$0x1 ++[ ]*[a-f0-9]+: f2 e9 d5 ff ff ff bnd jmpq 2b0 ++[ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 68 02 00 00 00 pushq \$0x2 ++[ ]*[a-f0-9]+: f2 e9 c5 ff ff ff bnd jmpq 2b0 ++[ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 68 03 00 00 00 pushq \$0x3 ++[ ]*[a-f0-9]+: e9 b6 ff ff ff jmpq 2b0 ++[ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%rax,%rax,1\) ++ ++Disassembly of section .plt.bnd: ++ ++0+300 : ++[ ]*[a-f0-9]+: ff 25 42 01 20 00 jmpq \*0x200142\(%rip\) # 200448 <_GLOBAL_OFFSET_TABLE_\+0x18> ++[ ]*[a-f0-9]+: 66 90 xchg %ax,%ax ++ ++0+308 : ++[ ]*[a-f0-9]+: f2 ff 25 41 01 20 00 bnd jmpq \*0x200141\(%rip\) # 200450 <_GLOBAL_OFFSET_TABLE_\+0x20> ++[ ]*[a-f0-9]+: 90 nop ++ ++0+310 : ++[ ]*[a-f0-9]+: f2 ff 25 41 01 20 00 bnd jmpq \*0x200141\(%rip\) # 200458 <_GLOBAL_OFFSET_TABLE_\+0x28> ++[ ]*[a-f0-9]+: 90 nop ++ ++0+318 : ++[ ]*[a-f0-9]+: ff 25 42 01 20 00 jmpq \*0x200142\(%rip\) # 200460 <_GLOBAL_OFFSET_TABLE_\+0x30> ++[ ]*[a-f0-9]+: 66 90 xchg %ax,%ax ++ ++Disassembly of section .text: ++ ++0+320 <_start>: ++[ ]*[a-f0-9]+: f2 e9 ea ff ff ff bnd jmpq 310 ++[ ]*[a-f0-9]+: e8 d5 ff ff ff callq 300 ++[ ]*[a-f0-9]+: e9 d8 ff ff ff jmpq 308 ++[ ]*[a-f0-9]+: e8 e3 ff ff ff callq 318 ++[ ]*[a-f0-9]+: f2 e8 cd ff ff ff bnd callq 308 ++[ ]*[a-f0-9]+: e9 d8 ff ff ff jmpq 318 ++#pass diff --git a/ld/testsuite/ld-x86-64/compressed1.d b/ld/testsuite/ld-x86-64/compressed1.d new file mode 100644 index 0000000..1dd0f4c @@ -2964222,12 +2981039,12 @@ index 0000000..403f980 +# Dummy diff --git a/ld/testsuite/ld-x86-64/dwarfreloc.exp b/ld/testsuite/ld-x86-64/dwarfreloc.exp new file mode 100644 -index 0000000..b7e133e +index 0000000..5cc7b92 --- /dev/null +++ b/ld/testsuite/ld-x86-64/dwarfreloc.exp @@ -0,0 +1,87 @@ +# Expect script for DWARF relocation test. -+# Copyright 2008, 2012 Free Software Foundation, Inc. ++# Copyright (C) 2008-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2964545,13 +2981362,13 @@ index 0000000..dee3b87 + .section .note.GNU-stack,"",@progbits diff --git a/ld/testsuite/ld-x86-64/export-class.exp b/ld/testsuite/ld-x86-64/export-class.exp new file mode 100644 -index 0000000..7bad2a8 +index 0000000..420b7a8 --- /dev/null +++ b/ld/testsuite/ld-x86-64/export-class.exp @@ -0,0 +1,93 @@ +# Expect script for symbol export classes, x86-64 variation. +# -+# Copyright 2012 Free Software Foundation, Inc. ++# Copyright (C) 2012-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2965294,13 +2982111,13 @@ index 0000000..1df2bc1 +#... diff --git a/ld/testsuite/ld-x86-64/line.exp b/ld/testsuite/ld-x86-64/line.exp new file mode 100644 -index 0000000..3ddaf17 +index 0000000..17e48c0 --- /dev/null +++ b/ld/testsuite/ld-x86-64/line.exp @@ -0,0 +1,64 @@ +# Test that the linker reports undefined symbol line number correctly. +# -+# Copyright 2007, 2012 Free Software Foundation, Inc. ++# Copyright (C) 2007-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2965548,13 +2982365,12 @@ index 0000000..955d33e +#pass diff --git a/ld/testsuite/ld-x86-64/mpx.exp b/ld/testsuite/ld-x86-64/mpx.exp new file mode 100644 -index 0000000..df6bc6f +index 0000000..f2a50d4 --- /dev/null +++ b/ld/testsuite/ld-x86-64/mpx.exp -@@ -0,0 +1,80 @@ +@@ -0,0 +1,82 @@ +# Expect script for ELF MPX tests. -+# Copyright 2013 -+# Free Software Foundation, Inc. ++# Copyright (C) 2013-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2965632,6 +2982448,9 @@ index 0000000..df6bc6f +run_ld_link_exec_tests [] $run_tests + +run_dump_test "bnd-branch-1" ++run_dump_test "bnd-ifunc-1" ++run_dump_test "bnd-ifunc-2" ++run_dump_test "bnd-plt-1" diff --git a/ld/testsuite/ld-x86-64/mpx1.out b/ld/testsuite/ld-x86-64/mpx1.out new file mode 100644 index 0000000..4630211 @@ -2965854,7 +2982673,7 @@ index 0000000..17a3bba +#error: .*relocation truncated to fit: R_X86_64_PC8 .* diff --git a/ld/testsuite/ld-x86-64/plt-nacl.pd b/ld/testsuite/ld-x86-64/plt-nacl.pd new file mode 100644 -index 0000000..2f5bab5 +index 0000000..b17bf71 --- /dev/null +++ b/ld/testsuite/ld-x86-64/plt-nacl.pd @@ -0,0 +1,55 @@ @@ -2965876,10 +2982695,10 @@ index 0000000..2f5bab5 + +[0-9a-f]+: 41 ff e3 jmpq \*%r11 + +[0-9a-f]+: 66 0f 1f 84 00 00 00 nopw 0x0\(%rax,%rax,1\) + +[0-9a-f]+: 00 00 * -+ +[0-9a-f]+: 66 66 66 66 66 66 2e data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++ +[0-9a-f]+: 66 66 66 66 66 66 2e data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +[0-9a-f]+: 0f 1f 84 00 00 00 00 * + +[0-9a-f]+: 00 * -+ +[0-9a-f]+: 66 66 66 66 66 66 2e data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++ +[0-9a-f]+: 66 66 66 66 66 66 2e data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +[0-9a-f]+: 0f 1f 84 00 00 00 00 * + +[0-9a-f]+: 00 * + +[0-9a-f]+: 66 90 xchg %ax,%ax @@ -2965889,12 +2982708,12 @@ index 0000000..2f5bab5 + +[0-9a-f]+: 41 83 e3 e0 and \$0xffffffe0,%r11d + +[0-9a-f]+: 4d 01 fb add %r15,%r11 + +[0-9a-f]+: 41 ff e3 jmpq \*%r11 -+ +[0-9a-f]+: 66 66 66 66 66 66 2e data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++ +[0-9a-f]+: 66 66 66 66 66 66 2e data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +[0-9a-f]+: 0f 1f 84 00 00 00 00 * + +[0-9a-f]+: 00 * + +[0-9a-f]+: 68 00 00 00 00 pushq \$0x0 + +[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmpq [0-9a-f]+ -+ +[0-9a-f]+: 66 66 66 66 66 66 2e data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++ +[0-9a-f]+: 66 66 66 66 66 66 2e data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +[0-9a-f]+: 0f 1f 84 00 00 00 00 * + +[0-9a-f]+: 00 * + +[0-9a-f]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%rax\) @@ -2965904,12 +2982723,12 @@ index 0000000..2f5bab5 + +[0-9a-f]+: 41 83 e3 e0 and \$0xffffffe0,%r11d + +[0-9a-f]+: 4d 01 fb add %r15,%r11 + +[0-9a-f]+: 41 ff e3 jmpq \*%r11 -+ +[0-9a-f]+: 66 66 66 66 66 66 2e data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++ +[0-9a-f]+: 66 66 66 66 66 66 2e data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +[0-9a-f]+: 0f 1f 84 00 00 00 00 * + +[0-9a-f]+: 00 * + +[0-9a-f]+: 68 01 00 00 00 pushq \$0x1 + +[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmpq [0-9a-f]+ -+ +[0-9a-f]+: 66 66 66 66 66 66 2e data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++ +[0-9a-f]+: 66 66 66 66 66 66 2e data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +[0-9a-f]+: 0f 1f 84 00 00 00 00 * + +[0-9a-f]+: 00 * + +[0-9a-f]+: 0f 1f 80 00 00 00 00 nopl 0x0\(%rax\) @@ -2966461,19 +2983280,34 @@ index 0000000..71928cb + call bar@PLT diff --git a/ld/testsuite/ld-x86-64/pr14207.d b/ld/testsuite/ld-x86-64/pr14207.d new file mode 100644 -index 0000000..2362e88 +index 0000000..d4e22a1 --- /dev/null +++ b/ld/testsuite/ld-x86-64/pr14207.d -@@ -0,0 +1,9 @@ +@@ -0,0 +1,24 @@ +#name: PR ld/14207 +#as: --64 +#ld: -melf_x86_64 -shared -z relro -z now +#readelf: -l --wide ++#target: x86_64-*-linux* + -+#failif -+#... -+ NULL +.* -+#... ++Elf file type is DYN \(Shared object file\) ++Entry point 0x1d9 ++There are 4 program headers, starting at offset 64 ++ ++Program Headers: ++ Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align ++ LOAD 0x000000 0x0000000000000000 0x0000000000000000 0x0001e0 0x0001e0 R 0x200000 ++ LOAD 0x000b48 0x0000000000200b48 0x0000000000200b48 0x0004b0 0x000cf8 RW 0x200000 ++ DYNAMIC 0x000b90 0x0000000000200b90 0x0000000000200b90 0x0001c0 0x0001c0 RW 0x8 ++ GNU_RELRO 0x000b48 0x0000000000200b48 0x0000000000200b48 0x0004b8 0x0004b8 R 0x1 ++ ++ Section to Segment mapping: ++ Segment Sections... ++ 00 .hash .dynsym .dynstr ++ 01 .init_array .fini_array .jcr .data.rel.ro .dynamic .got .bss ++ 02 .dynamic ++ 03 .init_array .fini_array .jcr .data.rel.ro .dynamic .got ++#pass diff --git a/ld/testsuite/ld-x86-64/pr14207.s b/ld/testsuite/ld-x86-64/pr14207.s new file mode 100644 index 0000000..496e67e @@ -2967039,7 +2983873,7 @@ index 0000000..86f1fe1 +.* TLS +GLOBAL +DEFAULT +10 bg4 diff --git a/ld/testsuite/ld-x86-64/tlsbin.dd b/ld/testsuite/ld-x86-64/tlsbin.dd new file mode 100644 -index 0000000..a9b1227 +index 0000000..c89e7ee --- /dev/null +++ b/ld/testsuite/ld-x86-64/tlsbin.dd @@ -0,0 +1,310 @@ @@ -2967113,7 +2983947,7 @@ index 0000000..a9b1227 + +[0-9a-f]+: 90[ ]+nop * + +[0-9a-f]+: 90[ ]+nop * +# LD -> LE -+ +[0-9a-f]+: 66 66 66 64 48 8b 04[ ]+data32 data32 data32 mov %fs:0x0,%rax ++ +[0-9a-f]+: 66 66 66 64 48 8b 04[ ]+data16 data16 data16 mov %fs:0x0,%rax + +[0-9a-f]+: 25 00 00 00 00 * + +[0-9a-f]+: 90[ ]+nop * + +[0-9a-f]+: 90[ ]+nop * @@ -2967128,7 +2983962,7 @@ index 0000000..a9b1227 + +[0-9a-f]+: 90[ ]+nop * + +[0-9a-f]+: 90[ ]+nop * +# LD -> LE against hidden variables -+ +[0-9a-f]+: 66 66 66 64 48 8b 04[ ]+data32 data32 data32 mov %fs:0x0,%rax ++ +[0-9a-f]+: 66 66 66 64 48 8b 04[ ]+data16 data16 data16 mov %fs:0x0,%rax + +[0-9a-f]+: 25 00 00 00 00 * + +[0-9a-f]+: 90[ ]+nop * + +[0-9a-f]+: 90[ ]+nop * @@ -2968586,10 +2985420,10 @@ index 0000000..2819a8f + ret diff --git a/ld/testsuite/ld-x86-64/tlsdesc-nacl.pd b/ld/testsuite/ld-x86-64/tlsdesc-nacl.pd new file mode 100644 -index 0000000..61e6049 +index 0000000..eff90a8 --- /dev/null +++ b/ld/testsuite/ld-x86-64/tlsdesc-nacl.pd -@@ -0,0 +1,42 @@ +@@ -0,0 +1,40 @@ +#source: tlsdesc.s +#source: tlspic2.s +#as: --64 @@ -2968601,7 +2985435,7 @@ index 0000000..61e6049 + +Disassembly of section .plt: + -+[0-9a-f]+ <.*@plt-0x40>: ++[0-9a-f]+ <.plt>: + +[0-9a-f]+: ff 35 .. .. .. .. pushq 0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x8> + +[0-9a-f]+: 4c 8b 1d .. .. .. .. mov 0x[0-9a-f]+\(%rip\),%r11 +# [0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x10> + +[0-9a-f]+: 41 83 e3 e0 and \$0xffffffe0,%r11d @@ -2968609,15 +2985443,13 @@ index 0000000..61e6049 + +[0-9a-f]+: 41 ff e3 jmpq \*%r11 + +[0-9a-f]+: 66 0f 1f 84 00 00 00 nopw 0x0\(%rax,%rax,1\) + +[0-9a-f]+: 00 00 * -+ +[0-9a-f]+: 66 66 66 66 66 66 2e data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++ +[0-9a-f]+: 66 66 66 66 66 66 2e data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +[0-9a-f]+: 0f 1f 84 00 00 00 00 * + +[0-9a-f]+: 00 * -+ +[0-9a-f]+: 66 66 66 66 66 66 2e data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++ +[0-9a-f]+: 66 66 66 66 66 66 2e data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +[0-9a-f]+: 0f 1f 84 00 00 00 00 * + +[0-9a-f]+: 00 * + +[0-9a-f]+: 66 90 xchg %ax,%ax -+ -+[0-9a-f]+ <.*@plt>: + +[0-9a-f]+: ff 35 .. .. .. .. pushq 0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x8> + +[0-9a-f]+: 4c 8b 1d .. .. .. .. mov 0x[0-9a-f]+\(%rip\),%r11 +# [0-9a-f]+ <_DYNAMIC\+0x190> + +[0-9a-f]+: 41 83 e3 e0 and \$0xffffffe0,%r11d @@ -2968625,10 +2985457,10 @@ index 0000000..61e6049 + +[0-9a-f]+: 41 ff e3 jmpq \*%r11 + +[0-9a-f]+: 66 0f 1f 84 00 00 00 nopw 0x0\(%rax,%rax,1\) + +[0-9a-f]+: 00 00 * -+ +[0-9a-f]+: 66 66 66 66 66 66 2e data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++ +[0-9a-f]+: 66 66 66 66 66 66 2e data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +[0-9a-f]+: 0f 1f 84 00 00 00 00 * + +[0-9a-f]+: 00 * -+ +[0-9a-f]+: 66 66 66 66 66 66 2e data32 data32 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++ +[0-9a-f]+: 66 66 66 66 66 66 2e data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) + +[0-9a-f]+: 0f 1f 84 00 00 00 00 * + +[0-9a-f]+: 00 * + +[0-9a-f]+: 66 90 xchg %ax,%ax @@ -2969009,10 +2985841,10 @@ index 0000000..a6f22b6 + +[0-9a-f]+: c3[ ]+retq * diff --git a/ld/testsuite/ld-x86-64/tlsdesc.pd b/ld/testsuite/ld-x86-64/tlsdesc.pd new file mode 100644 -index 0000000..2176576 +index 0000000..c24403c --- /dev/null +++ b/ld/testsuite/ld-x86-64/tlsdesc.pd -@@ -0,0 +1,20 @@ +@@ -0,0 +1,19 @@ +#source: tlsdesc.s +#source: tlspic2.s +#as: --64 @@ -2969024,11 +2985856,10 @@ index 0000000..2176576 + +Disassembly of section .plt: + -+[0-9a-f]+ <.*@plt-0x10>: ++[0-9a-f]+ <.plt>: + [0-9a-f]+: ff 35 .. .. 20 00 pushq .*\(%rip\) # 201358 <_GLOBAL_OFFSET_TABLE_\+0x8> + [0-9a-f]+: ff 25 .. .. 20 00 jmpq \*.*\(%rip\) # 201360 <_GLOBAL_OFFSET_TABLE_\+0x10> + [0-9a-f]+: 0f 1f 40 00 nopl 0x0\(%rax\) -+[0-9a-f]+ <.*@plt>: + [0-9a-f]+: ff 35 .. .. 20 00 pushq .*\(%rip\) # 201358 <_GLOBAL_OFFSET_TABLE_\+0x8> + [0-9a-f]+: ff 25 .. .. 20 00 jmpq \*.*\(%rip\) # 201348 <_DYNAMIC\+0x190> + [0-9a-f]+: 0f 1f 40 00 nopl 0x0\(%rax\) @@ -2969895,7 +2986726,7 @@ index 0000000..e867862 + +[0-9]+: [0-9a-f]+ +0 +NOTYPE +GLOBAL +DEFAULT +10 _end diff --git a/ld/testsuite/ld-x86-64/tlsgdesc.dd b/ld/testsuite/ld-x86-64/tlsgdesc.dd new file mode 100644 -index 0000000..635974c +index 0000000..85b219f --- /dev/null +++ b/ld/testsuite/ld-x86-64/tlsgdesc.dd @@ -0,0 +1,163 @@ @@ -2969939,10 +2986770,10 @@ index 0000000..635974c + +[0-9a-f]+: 90[ ]+nop * + +[0-9a-f]+: 90[ ]+nop * +# GD, gd first -+ +[0-9a-f]+: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data32 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x180> ++ +[0-9a-f]+: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x180> + +[0-9a-f]+: [0-9a-f]{2} * +# -> R_X86_64_DTPMOD64 sG1 -+ +[0-9a-f]+: 66 66 48 e8 ([0-9a-f]{2} ){3}[ ]+data32 data32 callq [0-9a-f]+ <__tls_get_addr@plt> ++ +[0-9a-f]+: 66 66 48 e8 ([0-9a-f]{2} ){3}[ ]+data16 data16 callq [0-9a-f]+ <__tls_get_addr@plt> + +[0-9a-f]+: [0-9a-f]{2} * +# -> R_X86_64_JUMP_SLOT __tls_get_addr + +[0-9a-f]+: 90[ ]+nop * @@ -2969964,10 +2986795,10 @@ index 0000000..635974c + +[0-9a-f]+: 90[ ]+nop * + +[0-9a-f]+: 90[ ]+nop * + +[0-9a-f]+: 90[ ]+nop * -+ +[0-9a-f]+: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data32 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x160> ++ +[0-9a-f]+: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x160> + +[0-9a-f]+: [0-9a-f]{2} * +# -> R_X86_64_DTPMOD64 sG2 -+ +[0-9a-f]+: 66 66 48 e8 ([0-9a-f]{2} ){3}[ ]+data32 data32 callq [0-9a-f]+ <__tls_get_addr@plt> ++ +[0-9a-f]+: 66 66 48 e8 ([0-9a-f]{2} ){3}[ ]+data16 data16 callq [0-9a-f]+ <__tls_get_addr@plt> + +[0-9a-f]+: [0-9a-f]{2} * +# -> R_X86_64_JUMP_SLOT __tls_get_addr + +[0-9a-f]+: 90[ ]+nop * @@ -2970430,7 +2987261,7 @@ index 0000000..ca63546 + .long 100 diff --git a/ld/testsuite/ld-x86-64/tlsld1.dd b/ld/testsuite/ld-x86-64/tlsld1.dd new file mode 100644 -index 0000000..e91ce08 +index 0000000..ec7467a --- /dev/null +++ b/ld/testsuite/ld-x86-64/tlsld1.dd @@ -0,0 +1,13 @@ @@ -2970445,7 +2987276,7 @@ index 0000000..e91ce08 +Disassembly of section .text: + +[a-f0-9]+ <_start>: -+[ ]*[a-f0-9]+: 66 66 66 64 48 8b 04 25 00 00 00 00 data32 data32 data32 mov %fs:0x0,%rax ++[ ]*[a-f0-9]+: 66 66 66 64 48 8b 04 25 00 00 00 00 data16 data16 data16 mov %fs:0x0,%rax +#pass diff --git a/ld/testsuite/ld-x86-64/tlsld1.s b/ld/testsuite/ld-x86-64/tlsld1.s new file mode 100644 @@ -2970505,7 +2987336,7 @@ index 0000000..6dcdd69 + .long 100 diff --git a/ld/testsuite/ld-x86-64/tlsld3.dd b/ld/testsuite/ld-x86-64/tlsld3.dd new file mode 100644 -index 0000000..0b639c6 +index 0000000..f9c8de2 --- /dev/null +++ b/ld/testsuite/ld-x86-64/tlsld3.dd @@ -0,0 +1,23 @@ @@ -2970525,7 +2987356,7 @@ index 0000000..0b639c6 +[ ]*[a-f0-9]+: 53 push %rbx +[ ]*[a-f0-9]+: 48 8d 1d ed ff ff ff lea -0x13\(%rip\),%rbx # [0-9a-f]+ <_start> +[ ]*[a-f0-9]+: 4c 01 db add %r11,%rbx -+[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data32 data32 data32 nopw %cs:0x0\(%rax,%rax,1\) ++[ ]*[a-f0-9]+: 66 66 66 66 2e 0f 1f 84 00 00 00 00 00 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\) +[ ]*[a-f0-9]+: 64 48 8b 04 25 00 00 00 00 mov %fs:0x0,%rax +[ ]*[a-f0-9]+: 8b 80 fc ff ff ff mov -0x4\(%rax\),%eax +[ ]*[a-f0-9]+: 5b pop %rbx @@ -2970774,7 +2987605,7 @@ index 0000000..d2cf7ba +.* NOTYPE +GLOBAL +DEFAULT +12 _end diff --git a/ld/testsuite/ld-x86-64/tlspic.dd b/ld/testsuite/ld-x86-64/tlspic.dd new file mode 100644 -index 0000000..2f85586 +index 0000000..26d83e9 --- /dev/null +++ b/ld/testsuite/ld-x86-64/tlspic.dd @@ -0,0 +1,385 @@ @@ -2970797,10 +2987628,10 @@ index 0000000..2f85586 + +1006: 90[ ]+nop * + +1007: 90[ ]+nop * +# GD -+ +1008: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data32 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x180> ++ +1008: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x180> + +100f: [0-9a-f ]+ +# -> R_X86_64_DTPMOD64 sg1 -+ +1010: 66 66 48 e8 [0-9a-f ]+data32 data32 callq [0-9a-f]+ <.*> ++ +1010: 66 66 48 e8 [0-9a-f ]+data16 data16 callq [0-9a-f]+ <.*> +# -> R_X86_64_JUMP_SLOT __tls_get_addr + +1017: [0-9a-f ]+ + +1018: 90[ ]+nop * @@ -2970817,10 +2987648,10 @@ index 0000000..2f85586 + +102e: 90[ ]+nop * + +102f: 90[ ]+nop * +# GD against local variable -+ +1030: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data32 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x130> ++ +1030: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x130> + +1037: [0-9a-f ]+ +# -> R_X86_64_DTPMOD64 [0 0x2000000000000000] -+ +1038: 66 66 48 e8 [0-9a-f ]+data32 data32 callq [0-9a-f]+ <.*> ++ +1038: 66 66 48 e8 [0-9a-f ]+data16 data16 callq [0-9a-f]+ <.*> +# -> R_X86_64_JUMP_SLOT __tls_get_addr + +103f: [0-9a-f ]+ + +1040: 90[ ]+nop * @@ -2970837,10 +2987668,10 @@ index 0000000..2f85586 + +1056: 90[ ]+nop * + +1057: 90[ ]+nop * +# GD against hidden and local variable -+ +1058: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data32 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x1a8> ++ +1058: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x1a8> + +105f: [0-9a-f ]+ +# -> R_X86_64_DTPMOD64 [0 0x4000000000000000] -+ +1060: 66 66 48 e8 [0-9a-f ]+data32 data32 callq [0-9a-f]+ <.*> ++ +1060: 66 66 48 e8 [0-9a-f ]+data16 data16 callq [0-9a-f]+ <.*> +# -> R_X86_64_JUMP_SLOT __tls_get_addr + +1067: [0-9a-f ]+ + +1068: 90[ ]+nop * @@ -2970857,10 +2987688,10 @@ index 0000000..2f85586 + +107e: 90[ ]+nop * + +107f: 90[ ]+nop * +# GD against hidden but not local variable -+ +1080: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data32 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x160> ++ +1080: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x160> + +1087: [0-9a-f ]+ +# -> R_X86_64_DTPMOD64 [0 0x6000000000000000] -+ +1088: 66 66 48 e8 [0-9a-f ]+data32 data32 callq [0-9a-f]+ <.*> ++ +1088: 66 66 48 e8 [0-9a-f ]+data16 data16 callq [0-9a-f]+ <.*> +# -> R_X86_64_JUMP_SLOT __tls_get_addr + +108f: [0-9a-f ]+ + +1090: 90[ ]+nop * @@ -2971989,13 +2988820,12 @@ index 0000000..7118cb9 +#... diff --git a/ld/testsuite/ld-x86-64/x86-64.exp b/ld/testsuite/ld-x86-64/x86-64.exp new file mode 100644 -index 0000000..32927b6 +index 0000000..f6c392b --- /dev/null +++ b/ld/testsuite/ld-x86-64/x86-64.exp -@@ -0,0 +1,327 @@ +@@ -0,0 +1,326 @@ +# Expect script for ld-x86_64 tests -+# Copyright (C) 2002, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012, 2013 -+# Free Software Foundation ++# Copyright (C) 2002-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2972550,12 +2989380,12 @@ index 0000000..48d9c82 + c0032a: bb fd callr 253 diff --git a/ld/testsuite/ld-xc16x/xc16x.exp b/ld/testsuite/ld-xc16x/xc16x.exp new file mode 100644 -index 0000000..5ab08c1 +index 0000000..b79ce2b --- /dev/null +++ b/ld/testsuite/ld-xc16x/xc16x.exp @@ -0,0 +1,68 @@ +# Expect script for ld-xstormy16 tests -+# Copyright (C) 2003, 2006, 2007 Free Software Foundation ++# Copyright (C) 2003-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2972712,12 +2989542,12 @@ index 0000000..6128e51 + nop diff --git a/ld/testsuite/ld-xstormy16/xstormy16.exp b/ld/testsuite/ld-xstormy16/xstormy16.exp new file mode 100644 -index 0000000..ceb6075 +index 0000000..c372adb --- /dev/null +++ b/ld/testsuite/ld-xstormy16/xstormy16.exp @@ -0,0 +1,41 @@ +# Expect script for ld-xstormy16 tests -+# Copyright (C) 2003, 2005, 2007 Free Software Foundation ++# Copyright (C) 2003-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2972759,14 +2989589,13 @@ index 0000000..ceb6075 +run_ld_link_tests $xstormy16_tests diff --git a/ld/testsuite/ld-xtensa/coalesce.exp b/ld/testsuite/ld-xtensa/coalesce.exp new file mode 100644 -index 0000000..c122263 +index 0000000..371f778 --- /dev/null +++ b/ld/testsuite/ld-xtensa/coalesce.exp -@@ -0,0 +1,100 @@ +@@ -0,0 +1,99 @@ +# Test literal coaslescing for Xtensa targets. +# By David Heine, Tensilica, Inc. -+# Copyright 2002, 2003, 2005, 2007, 2008 -+# Free Software Foundation, Inc. ++# Copyright (C) 2002-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2972912,16 +2989741,127 @@ index 0000000..7c9a83d + movi a6,g_name + movi a7,50000 + ret +diff --git a/ld/testsuite/ld-xtensa/diff_overflow.exp b/ld/testsuite/ld-xtensa/diff_overflow.exp +new file mode 100644 +index 0000000..89deb38 +--- /dev/null ++++ b/ld/testsuite/ld-xtensa/diff_overflow.exp +@@ -0,0 +1,45 @@ ++# Test DIFF* relocation signedness and overflow checking ++# By Max Filippov, Cadence Design Systems, Inc. ++# Copyright (C) 2014 Free Software Foundation, Inc. ++# ++# This file is part of the GNU Binutils. ++# ++# This program is free software; you can redistribute it and/or modify ++# it under the terms of the GNU General Public License as published by ++# the Free Software Foundation; either version 3 of the License, or ++# (at your option) any later version. ++# ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY; without even the implied warranty of ++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++# GNU General Public License for more details. ++# ++# You should have received a copy of the GNU General Public License ++# along with this program; if not, write to the Free Software ++# Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, ++# MA 02110-1301, USA. ++ ++if ![istarget "xtensa*-*-*"] { ++ return ++} ++ ++set testname "DIFF_OVERFLOW" ++ ++if ![ld_assemble $as "--text-section-literals $srcdir/$subdir/diff_overflow1.s" tmpdir/diff_overflow1.o] { ++ unresolved $testname ++ return ++} ++if ![ld_assemble $as "--text-section-literals $srcdir/$subdir/diff_overflow2.s" tmpdir/diff_overflow2.o] { ++ unresolved $testname ++ return ++} ++ ++set object "tmpdir/diff_overflow" ++ ++if ![ld_simple_link $ld $object "tmpdir/diff_overflow1.o tmpdir/diff_overflow2.o"] { ++ verbose -log "failure in ld" ++ fail $testname ++ return ++} ++ ++pass $testname +diff --git a/ld/testsuite/ld-xtensa/diff_overflow1.s b/ld/testsuite/ld-xtensa/diff_overflow1.s +new file mode 100644 +index 0000000..38519da +--- /dev/null ++++ b/ld/testsuite/ld-xtensa/diff_overflow1.s +@@ -0,0 +1,27 @@ ++ .section .text.f0,"axG",@progbits,f0,comdat ++ .literal_position ++ .literal .L0, 0 ++ .align 4 ++f0: ++ entry a1, 32 ++ l32r a2, .L0 ++ retw ++ ++ .section .text ++ .literal_position ++ .global _start ++_start: ++ entry a1, 32 ++ retw ++ ++ .section .text.f1,"axG",@progbits,f1,comdat ++ .literal_position ++ .literal .L1, 0 ++ .literal .L2, 0 ++ .align 4 ++ .global f1 ++f1: ++ entry a1, 32 ++ l32r a2, .L1 ++ l32r a3, .L2 ++ retw +diff --git a/ld/testsuite/ld-xtensa/diff_overflow2.s b/ld/testsuite/ld-xtensa/diff_overflow2.s +new file mode 100644 +index 0000000..096ae39 +--- /dev/null ++++ b/ld/testsuite/ld-xtensa/diff_overflow2.s +@@ -0,0 +1,22 @@ ++ .section .text.f1,"axG",@progbits,f1,comdat ++ .literal_position ++ .literal .L5, 0 ++ .align 4 ++f4: ++ entry a1, 32 ++.Lf4: ++ l32r a2, .L5 ++ l32r a2, .L5 ++ nop ++ nop ++ retw ++ ++ .section .text ++f5: ++ entry a1, 32 ++.Lf5: ++ retw ++ ++ .section .debug_frame,"",@progbits ++ .byte .Lf4 - f4 ++ .byte .Lf5 - f5 diff --git a/ld/testsuite/ld-xtensa/lcall.exp b/ld/testsuite/ld-xtensa/lcall.exp new file mode 100644 -index 0000000..599c69c +index 0000000..0915277 --- /dev/null +++ b/ld/testsuite/ld-xtensa/lcall.exp -@@ -0,0 +1,114 @@ +@@ -0,0 +1,113 @@ +# Test Xtensa longcall optimization. +# By David Heine, Tensilica, Inc. -+# Copyright 2002, 2003, 2005, 2007, 2008 -+# Free Software Foundation, Inc. ++# Copyright (C) 2002-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2973861,12 +2990801,12 @@ index 0000000..9f337e7 +sH8: .space 4 diff --git a/ld/testsuite/ld-xtensa/xtensa.exp b/ld/testsuite/ld-xtensa/xtensa.exp new file mode 100644 -index 0000000..f2986ab +index 0000000..f212479 --- /dev/null +++ b/ld/testsuite/ld-xtensa/xtensa.exp @@ -0,0 +1,54 @@ +# Expect script for ld-xtensa tests -+# Copyright (C) 2008 Free Software Foundation ++# Copyright (C) 2008-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2973921,12 +2990861,12 @@ index 0000000..f2986ab +run_ld_link_tests $xtensatests diff --git a/ld/testsuite/lib/ld-lib.exp b/ld/testsuite/lib/ld-lib.exp new file mode 100644 -index 0000000..c04b56f +index 0000000..27bfc08 --- /dev/null +++ b/ld/testsuite/lib/ld-lib.exp -@@ -0,0 +1,1716 @@ +@@ -0,0 +1,1781 @@ +# Support routines for LD testsuite. -+# Copyright 1994-2013 Free Software Foundation, Inc. ++# Copyright (C) 1994-2014 Free Software Foundation, Inc. +# +# This file is part of the GNU Binutils. +# @@ -2974126,10 +2991066,6 @@ index 0000000..c04b56f + set flags "" + } + -+ if [board_info [target_info name] exists ldflags] { -+ append flags " [board_info [target_info name] ldflags]" -+ } -+ + remote_file host delete $target + + return [run_host_cmd_yesno "$ld" "$HOSTING_EMU $flags -o $target $objs $libs"] @@ -2974148,10 +2991084,6 @@ index 0000000..c04b56f + set flags "" + } + -+ if [board_info [target_info name] exists ldflags] { -+ append flags " [board_info [target_info name] ldflags]" -+ } -+ + # If we are compiling with gcc, we want to add gcc_ld_flag to + # flags. Rather than determine this in some complex way, we guess + # based on the name of the compiler. @@ -2974432,6 +2991364,11 @@ index 0000000..c04b56f +# ld_after_inputfiles: FLAGS +# Similar to "ld", but put after all input files. +# ++# objcopy_objects: FLAGS ++# Run objcopy with the specified flags after assembling any source ++# that has the special marker RUN_OBJCOPY in the source specific ++# flags. ++# +# objcopy_linked_file: FLAGS +# Run objcopy on the linked file with the specified flags. +# This lets you transform the linked file using objcopy, before the @@ -2974540,6 +2991477,7 @@ index 0000000..c04b56f + set opts(error) {} + set opts(warning) {} + set opts(objcopy_linked_file) {} ++ set opts(objcopy_objects) {} + + foreach i $opt_array { + set opt_name [lindex $i 0] @@ -2974719,6 +2991657,12 @@ index 0000000..c04b56f + for { set i 0 } { $i < [llength $sourcefiles] } { incr i } { + set sourcefile [lindex $sourcefiles $i] + set sourceasflags [lindex $asflags $i] ++ set run_objcopy_objects 0 ++ ++ if { [string match "*RUN_OBJCOPY*" $sourceasflags] } { ++ set run_objcopy_objects 1 ++ } ++ regsub "RUN_OBJCOPY" $sourceasflags "" sourceasflags + + set objfile "tmpdir/dump$i.o" + catch "exec rm -f $objfile" exec_output @@ -2974742,6 +2991686,30 @@ index 0000000..c04b56f + fail $testname + return + } ++ ++ if { $run_objcopy_objects } { ++ set cmd "$OBJCOPY $opts(objcopy_objects) $objfile" ++ ++ send_log "$cmd\n" ++ set cmdret [remote_exec host [concat sh -c [list "$cmd 2>&1"]] \ ++ "" "/dev/null" "objcopy.tmp"] ++ remote_upload host "objcopy.tmp" ++ set comp_output [prune_warnings [file_contents "objcopy.tmp"]] ++ remote_file host delete "objcopy.tmp" ++ remote_file build delete "objcopy.tmp" ++ ++ if { [lindex $cmdret 0] != 0 \ ++ || ![string match "" $comp_output] } { ++ send_log "$comp_output\n" ++ verbose "$comp_output" 3 ++ ++ set exitstat "succeeded" ++ if { $cmdret != 0 } { set exitstat "failed" } ++ verbose -log "$exitstat with: <$comp_output>" ++ fail $testname ++ return ++ } ++ } + } + + set expmsg $opts(error) @@ -2975463,7 +2992431,6 @@ index 0000000..c04b56f + || [istarget d30v-*-*] + || [istarget dlx-*-*] + || [istarget i960-*-*] -+ || [istarget or32-*-*] + || [istarget pj*-*-*] + || [istarget alpha-*-*] + || [istarget hppa*64-*-*] @@ -2975536,8 +2992503,7 @@ index 0000000..c04b56f + && ![istarget msp430-*-*] + && ![istarget mt-*-*] + && ![istarget nds32*-*-*] -+ && ![istarget openrisc-*-*] -+ && ![istarget or32-*-*] ++ && ![istarget or1k*-*-*] + && ![istarget pj-*-*] + && ![istarget rl78-*-*] + && ![istarget rx-*-*] @@ -2975606,6 +2992572,45 @@ index 0000000..c04b56f + return $lto_available_saved +} + ++# Returns true if the target compiler supports LTO and -shared ++proc check_lto_shared_available { } { ++ global lto_shared_available_saved ++ global CC ++ ++ set flags "" ++ ++ if [board_info [target_info name] exists cflags] { ++ append flags " [board_info [target_info name] cflags]" ++ } ++ ++ if [board_info [target_info name] exists ldflags] { ++ append flags " [board_info [target_info name] ldflags]" ++ } ++ ++ if {![info exists lto_shared_available_saved]} { ++ # Check if gcc supports -flto -fuse-linker-plugin -shared ++ if { [which $CC] == 0 } { ++ set lto_shared_available_saved 0 ++ return 0 ++ } ++ set basename "lto_shared" ++ set src ${basename}[pid].c ++ set output ${basename}[pid].so ++ set f [open $src "w"] ++ puts $f "" ++ close $f ++ set status [remote_exec host $CC "$flags -shared -fPIC -B[pwd]/tmpdir/ld/ -flto -fuse-linker-plugin $src -o $output"] ++ if { [lindex $status 0] == 0 } { ++ set lto_shared_available_saved 1 ++ } else { ++ set lto_shared_available_saved 0 ++ } ++ file delete $src ++ file delete $output ++ } ++ return $lto_shared_available_saved ++} ++ +# Check if the assembler supports CFI statements. + +proc check_as_cfi { } { diff --git a/gdb.build.bash b/gdb.build.bash index 9062e2c..4e7bb97 100755 --- a/gdb.build.bash +++ b/gdb.build.bash @@ -12,15 +12,15 @@ cd - export PATH="$TOOLS_BIN_PATH:$PATH" -if [[ ! -f gdb-7.7.tar.bz2 ]] ; +if [[ ! -f gdb-7.8.tar.xz ]] ; then - wget http://mirror.switch.ch/ftp/mirror/gnu/gdb/gdb-7.7.tar.bz2 + wget http://mirror.switch.ch/ftp/mirror/gnu/gdb/gdb-7.8.tar.xz fi -tar xfjv gdb-7.7.tar.bz2 +tar xfv gdb-7.8.tar.xz -cd gdb-7.7 -for p in ../gdb-patches/*.patch; do echo Applying $p; patch -p1 < $p; done +cd gdb-7.8 +for p in ../gdb-patches/*.patch; do echo Applying $p; patch --binary -p1 < $p; done cd - mkdir -p objdir @@ -38,7 +38,7 @@ CONFARGS=" \ --disable-binutils \ --target=avr" -CFLAGS="-w -O2 -g0 $CFLAGS" CXXFLAGS="-w -O2 -g0 $CXXFLAGS" LDFLAGS="-s $LDFLAGS" ../gdb-7.7/configure $CONFARGS +CFLAGS="-w -O2 -g0 $CFLAGS" CXXFLAGS="-w -O2 -g0 $CXXFLAGS" LDFLAGS="-s $LDFLAGS" ../gdb-7.8/configure $CONFARGS if [ -z "$MAKE_JOBS" ]; then MAKE_JOBS="2" diff --git a/libusb.build.bash b/libusb.build.bash index e958ff8..8370a85 100755 --- a/libusb.build.bash +++ b/libusb.build.bash @@ -31,7 +31,7 @@ then wget http://switch.dl.sourceforge.net/project/libusb/libusb-1.0/libusb-1.0.18/libusb-1.0.18.tar.bz2 fi - tar xfjv libusb-1.0.18.tar.bz2 + tar xfv libusb-1.0.18.tar.bz2 mkdir -p libusb-1.0-build cd libusb-1.0-build @@ -59,7 +59,7 @@ then wget http://switch.dl.sourceforge.net/project/libusb/libusb-compat-0.1/libusb-compat-0.1.5/libusb-compat-0.1.5.tar.bz2 fi - tar xfjv libusb-compat-0.1.5.tar.bz2 + tar xfv libusb-compat-0.1.5.tar.bz2 mkdir -p libusb-0.1-build cd libusb-0.1-build